Abstract:
In a usage parameter control device for an asynchronous transfer mode communications system, a determination is made as to whether either of the respective storage elements maintaining values for (1) the time of arrival of a cell (T TA  and (2) the time value at which the “bucket” will have drained to an empty condition (T TAT ) has wrapped relative to the other. The wrap determination is made prior to the comparison between the T TA  and T TAT  values which is made in order to determine whether the user is complying with his or her contracted parameters. If one of the storage elements has wrapped relative to the other, the comparison between the T TA  and T TAT  values is modified accordingly.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application is a continuation of U.S. patent application Ser. No. 09/144,289 filed Aug. 31, 1998 and entitled “Usage Parameter Control Device for Asynchronous Transfer Mode System” now U.S. Pat. No. ______. 
     
    
     
       TECHNICAL FIELD OF INVENTION  
         [0002]    The following invention relates generally to the improved operation of a usage parameter control (UPC) device for asynchronous transfer mode (ATM) communications systems, and in particular, to following wrapping of finite counter and register elements used to keep track of infinitely progressing time.  
         BACKGROUND OF THE INVENTION  
         [0003]    In recent years, ATM communication has become increasingly popular. Prior to this preference for ATM, time division multiplexing (TDM) systems were the preferred mode of communication. In TDM systems, each user was allocated a particular time slot within a standard time interval during which a communication channel would be dedicated to the user. In this system, the time slot would be unavailable to other users regardless of whether the allocated user was actually using it which frequently resulted in wasted bandwidth.  
           [0004]    In ATM systems, by contrast, information is transmitted as bandwidth is available without regard to time. In order to keep ATM traffic flowing, each user agrees, by way of a contract with the ATM network operator, to a minimum length of time, t, between transmission of his or her cells. A maximum number of cells which may be transmitted in an interval, T, is also agreed upon. The time, t, determines the user&#39;s peak cell rate (PCR) and the interval, T, determines the user&#39;s sustained cell rate (SCR). A third parameter, maximum burst size (MBS) which specifies the maximum number of cells which are permitted to be transmitted consecutively at the PCR, is also contracted for. In order to prevent users from exceeding their respective limitations, ATM networks may employ a UPC device which can monitor these and other usage parameters.  
           [0005]    In an ATM system, UPC monitoring is typically performed in accordance with standard generic cell rate algorithms (GCRAs). Once such GCRA is a “leaky bucket” algorithm, in which a figurative bucket “fills” proportional to the actual cell rate received from a user and “drains” at a fixed rate proportional to the contracted service rate parameters. If the user exceeds the limits on contracted parameters, such as PCR or SCR, the “bucket” will “overflow” and the user&#39;s cells may be either discarded or tagged as having a low priority.  
           [0006]    ATM communications may be carried out using a constant bit rate (CBR) or using a variable bit rate (VBR). A CBR connection essentially mimics the old TDM systems. Monitoring of a CBR connection is accomplished using a single leaky bucket. Conformance is characterized by the peak cell rate (PCR) and the corresponding cell delay variation tolerance (CDVT) due to, e.g., head-of-line blocking. The CDVT is defined in relation to the PCR. The capacity of the leaky bucket is 1/PCR (a.k.a. IP)+CDVT specified for the cell flow. The drain rate of the PCR bucket is 1/PCR.  
           [0007]    [0007]FIG. 1 is a flow chart illustrating the operation of a leaky bucket GCRA used to monitor usage parameters for a CBR connection. In block  102 , a cell arrives at time T . Thereafter T TATp  for the particular user is read from memory in block  105 . T TATp  is the time value at which the “bucket” will have drained to an empty condition in the absence of new cell arrivals. It is calculated during cell arrivals and is adjusted in proportion to the contracted PCR rate for CBR service. In Block  107  a comparison between T TA  and T TATp  is performed. If T TA  is greater than T TATp , i.e. the cell arrived after the bucket had completely emptied, then the cell is accepted at block  111 , and, at block  114 , T TATp  is set to T TA +1/PCR. If T TA  is not greater than T TATp , i.e. the bucket is not completely empty, a check is done in block  117  to determine if there is enough room in the partially full bucket to accept the cell based on its maximum capacity of 1/PCR+CDVT. If not, the cell is discarded at block  120 . If so, the cell is accepted at block  122 , and T TATp  is updated at block  125  to equal T TATp +1/PCR.  
           [0008]    In a variable bit rate (VBR) system, a second leaky bucket GCRA is used in addition to the first leaky bucket GCRA described above in order to ensure compliance with the contracted sustained cell rate (SCR) and maximum burst size (MBS). The capacity of this second leaky bucket is 1/SCR+Burst Tolerance (BT)+CDVT. Burst tolerance is calculated from the contracted SCR, PCR, and MBS, and is the additional bucket depth required to hold “MBS−1” more cells arriving at the PCR rate (BT={MBS−1}×{1/SCR−1/PCR}). The sum of BT and CDVT is given the identifier “L”. The drain rate of this bucket is 1/SCR  
           [0009]    [0009]FIG. 2 shows the flow diagram for this second GCRA for the case where it is used in conjunction with the GCRA of FIG. 1. If a cell is accepted in accordance with the GCRA of FIG. 1, i.e., either of boxes  128  or  131  of FIG. 1 are reached, then T TATs  is retrieved from memory in block  137 . T TATs  is the time value at which the “bucket” will have drained to an empty condition in the absence of new cell arrivals, and is calculated in increments of 1/SCR which provides enough time for a full bucket to leak enough to provide room for another cell. A comparison between the T TA  of the cell from box  102  of FIG. 1 and the theoretical arrival time, T TATs , is then performed at box  140 .  
           [0010]    If the result of the comparison of box  140  is that T TA  is greater than T TATs , then the cell is accepted at box  143 , and T TATs  is set to T TA +1/SCR at box  146 . If the result of box  140  is that T TA  is not greater than T TATs , then the system checks at box  149  to see whether the sum of T TA  plus the burst tolerance (BT) plus the CDVT is greater than T TATs , where BT is a function of the contracted parameters MBS, PCR and SCR. If not, the cell is non-conforming and is discarded at box  152 . If, on the other hand, the condition T TA +BT+CDVT&gt;T TATs  is met, the cell is accepted at box  155  and T TATs  is set to T TATs +1/SCR at box  158 .  
           [0011]    A brief example using simple, if not practical, hypothetical figures for SCR, MBS and PCR will better illustrate the operation of the leaky bucket of FIG. 2. Assuming a VBR service with contracted parameters of SCR=5 cells/sec, a MBS=3 cells, and a PCR of 100 cells/sec and CDVT of 0.02 sec. This results in 1/SCR=IS=0.2 sec/cell, BT=0.38 sec, and L=BT+CDVT=0.4 sec. For the purposes of this example, assume that the criteria of the first leaky bucket check against PCR and CDVT is always favorable and that the initial value of T TATs  is 0.0. If a first cell is transmitted at 0.01 seconds, i.e., T TA =0.01, the result of box  140  is that T TA &gt;T TATs  so that the cell is accepted at box  143  and T TATs  is set to T TATs +1/SCR, i.e., 0.0+0.2=0.2 sec at box  146 . A second cell now arrives at time 0.02 seconds. The result of box  140  is that T TA &lt;T TATs  so that the condition T TA +L&gt;T TATs  is checked at box  149 . We find that this condition is met (0.02+0.4&gt;0.2). The cell is accepted at box  155  and T TATs  is set to T TATs +1/SCR, i.e., 0.2+0.2=0.4 sec at box  158 . Similarly, a third cell arrivals at 0.03 sec, the cell is accepted and T TATs  is set to 0.6 sec. If a fourth cell arrives at 0.04 sec, T TA +L will not be greater than T TATs . The fourth cell is therefore discarded at box  152  and T TATS  remains unchanged at 0.6 sec. The same result occurs for any cell received earlier than time 0.2 seconds. After that time, the condition T TA +L&gt;T TATs  of box  149  is again met. Furthermore, if the fifth cell does not arrive until a time later than 0.6 sec, the bucket will be completely empty and the T TA &gt;T TATs  condition will be met.  
           [0012]    Those skilled in the art will appreciate that the above description is a simplified explanation of ATM systems, the role of UPC devices and leaky buckets generally. With respect to ATM systems, detailed explanations of the operation of such systems may be found in User Network Interface Specification (UNI) 3.1 published by the ATM Forum. The present invention is intended for use in systems designed in accordance with the standards presented therein, but is not so limited. Moreover, leaky bucket GCRAs have myriad design applications in which the present invention may be employed.  
           [0013]    While the UNI Specification provides broad standards for designing ATM systems, there is little or no guidance provided for many practical problems encountered in implementation. One such problem is that counters and registers of infinite memory are not available to keep track of time, and finite-memory counters and registers will eventually reach their limit and reset to zero. This problem is hereafter referred to as “wrapping.” A wrapping of the current time counter from which the cell arrival time T TA  is read and/or the register which stores T TA  without a consequent wrapping of the register which stores the theoretical arrival time T TAT  will cause subsequent comparisons between T TAT  and T TA  to yield unwanted results. For example, if the current time counter wraps to zero, it will appear that the arrival time, T TA , is much earlier than it actually is, and the comparison between T TA  and T TAT  will show that T TA  is less than T TAT , indicating a violation of the contracted transmission rate when, in fact, no such violation occurred.  
         SUMMARY OF THE INVENTION  
         [0014]    In accordance with the present invention, in a usage parameter control device for an asynchronous transfer mode communications system, a determination is made as to whether either of the respective storage elements maintaining values for (1) the time of arrival of a cell (T TA ) and (2) the time value at which the “bucket” will have drained to an empty condition (T TAT ) has wrapped relative to the other. The determination is made prior to comparing the T TA  and T TAT  values in order to determine whether the user is complying with his or her contracted parameters.  
           [0015]    In accordance with a further aspect of the invention, a wrap state is maintained for each virtual connection (VC). A wrap state indicates the wrap status of the respective storage elements maintaining values for T TA  and T TAT  relative to one another. The comparisons between T TA  and T TAT  which determine whether a user is in conformance with his or her contracted parameters are then modified accordingly. The wrap state for each VC is updated during a wrap audit each time the current time counter, i.e., the counter from which T TA  is read, wraps.  
           [0016]    In accordance with a further aspect of the invention, in order to avoid excessive delays in cell processing which may be caused by the wrap audit in a system capable of maintaining a relatively large number of VCs, the VCs are divided into a predetermined number of groups and the current time counter is divided into an equal number of phases such that wrap state audits are performed on a staggered group-by-group basis.  
           [0017]    It is therefore an object of the present invention to provide a UPC system which will take into account the wrapping of storage elements containing the values of T TAT  and T TA .  
           [0018]    It is a further object of the present invention to provide a UPC system with the ability to perform wrap audits for each VC on a regular basis without causing unacceptable delay to the function of the ATM system.  
           [0019]    For a better understanding of the present invention, together with other and further objects, reference is made to the following description, taken in conjunction with the accompanying drawings and its scope will be pointed out in the appended claims.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    [0020]FIG. 1 is a flow chart illustrating the operation of a first prior art leaky bucket generic cell rate algorithm;  
         [0021]    [0021]FIG. 2 is a flow diagram for a second prior art leaky bucket generic cell rate algorithm which may be used in conjunction with the leaky bucket algorithm of FIG. 1;  
         [0022]    [0022]FIG. 3 is a flow diagram for a leaky bucket generic cell rate algorithm in accordance with the present invention;  
         [0023]    [0023]FIG. 4 depicts an example of a wrap state RAM partition according to the present invention for an ATM system capable of handling 1024 virtual connections; and  
         [0024]    [0024]FIG. 5 is a block diagram of one particular implementation for maintaining arrival time and sixteen current time phases in accordance with the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
     Wrap States  
       [0025]    In an ATM system according to the present invention each GCRA for a virtual connection (VC) will have a two-bit state machine which will maintain relative wrap states, W S , between the registers storing the values for T TAT  and T TA  (hereafter “the T TAT  register” and “the T TA  register,” respectively). The term “register” is used herein in a generic sense and is intended to encompass any suitable storage element. The wrap states are shown in the following Table 1.  
                           TABLE 1                                   W S     Definition                           00   T TAT  register and T TA  register are synchronized           01   T TAT  register is wrapped ahead of T TA  register           1X   T TA  register is wrapped ahead of T TAT  register                      
 
         [0026]    A wrap state of 00 indicates that the T TAT  and the T TA  registers are in synch with one another, i.e., neither is wrapped relative to the other. A wrap state of 01 indicates that the T TAT  register has wrapped ahead of the T TA  register. A wrap state of 1×, i.e., either 10 or 11, indicates that the T TA  register has wrapped ahead of the T TAT  register. In a system employing two leaky buckets, one state machine is used to keep track of the wrap state between the respective registers used to store T TATp  and T TA , and a second state machine is used to keep track of the wrap state between the respective registers used to store T TATs  and T TA .  
         [0027]    [0027]FIG. 3 depicts an improved leaky bucket GCRA in accordance with the present invention. For purposes of simplification, neither CBR nor VBR is assumed. Also, for purposes of illustrating the operation of the invention, 25-bit registers for T TA  and T TAT , a 25-bit counter for maintaining current time, and a 6.25 MHZ counter clock (one quarter of a 25 MHZ system clock) are assumed. In such a system, the 25-bit current time counter, i.e., the counter from which T TA  is read, will be updated every 160 nsec and hence will wrap every 5.368 seconds.  
         [0028]    At box  220  of FIG. 3, a cell arrives when the current time counter is at T TA , and T TA  is stored in the T TA  register. Thereafter, the T TAT  for the connection is read from the T TAT  register at box  223 . Next, at box  226 , the wrap state for the connection is read from another register. If, at box  229 , the wrap state is either 10 or 11, then the T TA  register is wrapped ahead of the T TAT  register. At any given time, the T TA  register may be wrapped ahead of the T TAT  register multiple times. It is enough to know that it happened at least once. Thereafter, T TA  must be greater than T TAT . The cell, therefore, is conforming and is accepted at box  232 . At box  235 , a new T TAT  is generated by adding 1 to T TA  which re-synchronizes the wrap time base and eliminates the T TA  wrap ahead condition. The value of I will be either 1/PCR or 1/SCR depending on which parameter is being monitored. With reference to box  238 , if the new T TAT  does not exceed 2 25 −1, i.e., the 25-bit T TAT  register has not wrapped, the new W S  is set to 00 at box  241 . Otherwise, W S  is set to 01 at box  244 , indicating that the T TAT  register wrapped ahead of the T TA  register. In either case, the 25 least significant bits of the addition are stored in the T TAT  register as the new T TAT  value.  
         [0029]    With reference to box  247 , if the wrap state for the connection is 00, then the T TA  and T TAT  registers have not wrapped relative to each other, and the same tests used in the prior art leaky bucket GCRAs are used at boxes  250  and  253 . At box  250 , if T TA &gt;T TAT , then the cell is accepted at box  232  and the sequence of boxes  235 ,  238  and either of  241  or  244  is performed as discussed above to determine the wrap state. If T TA  NOT&gt;T TAT , then, at box  253 , a determination as to whether T TA +L&gt;T TAT  is made, where L is either CDVT or BT+CDVT. If the condition is not present, the cell is discarded at box  258 . If the condition is met, the cell is accepted at box  261 , and, at box  264 , a new T TAT  is generated by adding I to the current T TAT  after which the sequence of boxes  235 ,  238  and either of  241  or  244  is performed as discussed above to determine the wrap state.  
         [0030]    With reference to boxes  229  and  247  of FIG. 3, if W S  is neither 1× or 00, then it is 01, which indicates that the T TAT  register has wrapped ahead of the T TA  register. T TA  therefore cannot be greater than T TAT . Rather than check for T TA +L&gt;T TAT , as in the prior art GCRAs, according to the present invention, at box  267  the modified test in a system using 25-bit counters when W S =01 is whether T TA +L&gt;T TAT +2 25 . If so, then a new T TAT  is calculated at box  264  as T TAT+ 1, and W S  will remain 01, indicating that the T TAT  register continues to be wrapped ahead of the T TA  register. If not, the cell will be discarded at box  270 .  
         [0031]    This embodiment of the invention is based on the premise that at any given time the T TAT  register can only be wrapped ahead of the T TA  register once. This can be guaranteed by setting limits on the L and I values. For a cell to be accepted, the largest value of T TAT −T TA  is L max −1. The largest value of T TAT  is therefore T TAmax +L max +I−1. Since T TA  and T TAT  are both modulo 2 25 , the T TAT  register cannot wrap ahead of the T TA  register more than once provided that L+1 is less than 2 25 −1. This restriction can be generalized as L+I&lt;2 n −1, where n is the width of the current time counter, and T TAT  and T TA  storage elements. The range of L or I may be increased simply by adding width to these elements. The L and I values of a particular UPC system can be set, as follows, such that this criteria is always met.  
         [0032]    In one embodiment, a software provisionable 16 bit storage element will be used for I. At a 6.25 MHZ clock rate (160 ns), this allows PCR and SCR values as low as 95.4 cells/sec (I=(1/rate)(1/160 ns)=0xFFFF) and in excess of the 100K cells/sec (I=0x003E). For each leaky bucket, a software provisionable 25 bit storage element with a resolution 160 ns is used to specify L. The following is an example of a set of attainable requirements.  
         [0033]    MBS=512 cells  
         [0034]    Minimum SCR=150 cells/sec (i.e., 56 kb/s)  
         [0035]    Maximum PCR=100K cells/sec  
         [0036]    Maximum CDVT=1.024 ms  
         [0037]    L max =((MBS−1)[(1/SCR min )−(1/PCR max )]+CDVT)=3.41 sec.  
         [0038]    This corresponds to an L parameter of 3.41s/160 ns=0x144FB7E. Those skilled in the art will appreciate that larger values of L can be obtained. According to the particular embodiment of the present invention under discussion, however, there is a restriction that (L+I)&lt;(2 25 −1).  
         [0039]    In a particular embodiment of the invention, the W S  states are maintained in a RAM which is only processed by hardware. In a system with 1024 VCs, for example, the RAM is organized as 256×16. FIG. 4 shows a particular W S  state RAM partition for the VCs. Since each VC may need as many as 4 bits for W S  state bits (one W S  state machine per GCRA), four VCs can be supported per 16 bit word. Using this RAM partition, the eight most significant bits of the VC identifier may be used to represent the RAM address.  
         [0040]    In accordance with the present invention, the wrap state, W S , for each VC is updated on a periodic audit basis each time the current time counter, i.e., the counter from which T TA  is read, wraps. The audit state transitions are shown in the following Table:  
                           TABLE 2                                   W S     Next W S                             00   10           (T TAT  register and   (T TA  register is wrapped           T TA  register are synchronized)   ahead of T TAT  register)           01   00           (T TAT  register is wrapped   (T TAT  register and           ahead of T TA  register)   T TA  register are synchronized)           1X   10           (T TA  register is wrapped   (T TA  register is wrapped           ahead of T TAT  register)   ahead of T TAT  register)                      
 
         [0041]    With reference to Table 2, if W S  is 00, indicating that the T TA  and T TAT  registers are in synch with one another, and the current time counter then wraps, W S  is updated to 10, indicating that the T TA  register has wrapped ahead of the T TAT  register. If W S  is 01, indicating that the T TAT  register is wrapped ahead of the T TA  register, and the current time counter then wraps, W S  is updated to 00 indicating that the T TA  and  
         [0042]    T TAT  registers are now in synch. If W S . is 1×, indicating that the T TA  register is wrapped ahead of the T TAT  register, and the current time counter then wraps, W S  is set to 10 indicating that the T TA  register is still wrapped ahead of the T TAT  register.  
         [0043]    With this approach all relevant information required for wrap state processing of a GCRA can be summarized in two state bits. This permits the packing of such state information into conventional wide storage elements (e.g., ×16 RAM, ×32 RAM, etc.) and results in the ability to simultaneously process audits for multiple GCRAs and reduce the necessary RAM access bandwidth and clock cycles for such processing.  
       Multi-Phase Current Time Counter  
       [0044]    One potential problem which may be encountered when implementing the above-described improved UPC system is that in ATM systems handling a large number of VCs, the time needed to perform the wrap state audits may be prohibitively high, as cell processing is put on hold during such audits. In these situations the cell processing latency for updating the W S  for all VCs may be minimized by breaking the VCs into a predetermined number of groups and performing the wrap state audits on a staggered group-by-group basis rather than auditing all VCs at once. By way of example, in an ATM system handling 1024 VCs, sixteen groups of 64 VCs can be created. If sixteen different phases of the current time counter are maintained, 16 unique wrap events will occur. The VCs may be broken into 16 audit groups of 64 VCs as shown in the following table:  
                           TABLE 3                                       W S  Audit and           VC Identifier   Current Time Phase Group                           0000000000 through 0000111111    0           0001000000 through 0001111111    1           .   .           .   .           .   .           1110000000 through 1110111111   14           1111000000 through 1111111111   15                      
 
         [0045]    The groups are audited in a round robin fashion. In a system having 25-bit counters and a 6.25 MHZ counter clock (one quarter of a 25 MHZ system clock), the audits are spaced by approximately 335 ms (2 21 ×160 nsec) with each group being updated every 5.368 seconds (2 25 ×160 nsec). The 64 VCs in a group can be serviced in 32 clocks at 40 nsec (i.e., 64 VCs×(2 accesses/4 VCs)×1clock/access). Those skilled in the art will appreciate that the audit time can be reduced by any of a number of design choices, e.g., using wider RAMs or using faster system clocks.  
         [0046]    [0046]FIG. 5 illustrates a particular implementation for maintaining T TA  and the sixteen current time phases in accordance with the present invention. Counter  202  keeps the 21 least significant bits of the 25-bit current time counter while counter  205  keeps the four most significant bits. For every wrap of counter  205 , counter  202  wrap sixteen times and, consequently, trigger its terminal count (TC) output sixteen times. The TC output is used both to trigger counter  205  and to issue a wrap audit request as shown in the figure. On which of the sixteen groups of VCs shown in Table 3 the W S  audit will be performed is determined by the four most significant bits of the 25-bit current time (CT) counter which are shown in FIG. 5 as the output of counter  205  labeled Audit Group-1.  
         [0047]    Rather than use sixteen separate but synchronized 25-bit counters to create the sixteen phases of current time described above, a 4 bit subtractor  208 , where input A is subtracted from input B, is used. Input A of the subractor  208  is the four most significant bits of the 25-bit current time counter, i.e., the output from counter  205 . Input B is the four most significant bits of the VC identifier of the cell being processed. The four most significant bits of the VC identifier indicate which of the sixteen W S  audit and current time phase groups the VC is in, as shown in Table 3 above. The 4-bit output of the subtractor  208  is used as the four most significant bits for each of the sixteen current time phases (CTP) at the start of the cell processing, while the 21 least significant bits are the same as the current time counter, i.e., the output from counter  202 . In this way, sixteen current time phases, each offset from one another by one-sixteenth of the total time kept by the 25-bit current time counter, are maintained. Upon the arrival of a cell, a cell process begin signal causes element  211  to read as the arrival time, T TA , the output of subtractor  208  as its four most significant bits and the output of counter  202  as its 21 least significant bits.  
         [0048]    While this invention has been described with reference to several illustrative examples and embodiments, they should not be interpreted as limiting the scope or spirit of the attributes invention. In actual practice many modifications may be made by those of ordinary skill in the art without deviating from the scope of the invention as expressed in the appended claims.