Abstract:
A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.

Description:
RELATED APPLICATION(S) 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/860,059, filed on Nov. 20, 2006. The entire teachings of the above application(s) are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to shift register circuits, and more particularly to shift register designs adapted for providing the lowest possible power consumption. 
         [0003]      FIG. 1  illustrates one conventional design for a single stage static shift register. As with any shift register, this circuit  10  has a signal input in, a clock ck and in this configuration complimentary outputs out and out *. The circuit is powered by a supply voltage provided by two rail voltages VDD and VSS. 
         [0004]    This specific circuit uses an input signal buffer transistor MP 1  that feeds a pair of cross-coupled transistors MP 2  and MP 3  to store the input signal state. Inverters INV 1  and INV 2  connected to the output of MP 1  serve to buffer output voltage and current levels. Clock switch transistors MN 1 , MN 2 , MN 3  and MN 4  turn on the shift register to accept a digital input signal, such as from a previous stage. 
         [0005]    The switches MN 1 -MN 4  must be fully turned on or off for the shift register to function, thus requiring a full rail-to-rail voltage swing on their gate terminals. Even if external low voltage clock signals are applied, level shifters and clock buffers (not shown in  FIG. 1 ) must be used to bring the gate control voltages to full rail voltage swing. Unfortunately, the power consumption in these clock buffers is equal to V 2 C p f c , where V is the power supply voltage difference (VDD−VSS), C p  is the total parasitic capacitance connected to the clock buffer outputs, and f c  is clock frequency. With a high voltage supply (10v or more), a large number of shift registers in series, long connection wires, and high clock frequency, a shift register using the stage circuit of  FIG. 1  can therefore consume a significant amount of power. 
         [0006]      FIG. 2  illustrates another known shift register stage circuit  20  that improves to some extent on the design of  FIG. 1 . This shift register stage circuit is adapted to operate with a low voltage swing clock signal, but high voltage swing logic circuits. For example, the voltage range between VDD and VSS might be 10 volts to provide high speed. However, the voltage swing from the clock input ck might be much less that—on the order of three volts or so—to reduce power consumption. 
         [0007]    The input and output signals for the circuit  20  of  FIG. 2  are as follows: 
         [0000]    
       
         
               
               
             
           
               
                   
               
             
             
               
                 ck 
                 clock signal with peak-to-peak voltage from VEE to VDD 
               
               
                   
                 (VEE &gt; VSS) 
               
               
                 e* 
                 complementary output from previous shift register stage 
               
               
                 o and o* 
                 register output and its complementary output, respectively 
               
               
                 r 
                 reset signal for individual shifter register 
               
               
                 vgp 
                 an analog bias voltage 
               
               
                 pc 
                 a pre-charge signal to initialize all shifter registers 
               
               
                   
                 to low before start 
               
               
                   
               
             
          
         
       
     
         [0008]    The circuit  20  is configured such that an internal node a serves as both a collection point for input signal state and for driving output buffer INV 1 . Here, the number of state transistors has been reduced to only two, MP 2  and MP 1 , arranged in cascode series. The ck signal input is fed to the source of MP 2 . The VDD supply voltage is fed to bias the body of transistor MP 2 . The gate of MP 2  is fed by complimentary output from the previous shift register stage. 
         [0009]    The gate of MP 1  is controlled by vgp which is an analog bias voltage. MP 1  is biased such that it conducts when its source voltage is greater than vgp by an amount, Vtp, where Vtp is the threshold voltage of MP 1 . A pre-charge input pc and a reset input r feed the drain of MP 1  which also sets the voltage at node a. 
         [0010]    In operation, the voltage vgp is thus set so that VEE−vgp&lt;Vtp where Vtp is the threshold voltage of transistor MP 1 . When ck is low (VEE), MP 1  is off and node a is held at its previous value; when ck is high (VDD) and the previous stage output e is high—which means that e* is low (VSS)—node a is charged up to a high voltage (VDD) through transistor MP 1  and MP 2 . 
         [0011]    The circuit  20  of  FIG. 2  thus offers reduced power consumption as compared to the circuit  10  of  FIG. 1 . In designs such as this, however, with a high voltage swing shift register driven by a low voltage swing input clock, internal or external level shifters and clock buffers are thus often necessary. 
       SUMMARY OF THE INVENTION 
       [0012]    The present invention is an improved design for a high voltage shift register which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly by a single input transistor. This arrangement allows for reduced power consumption. 
         [0013]    The invention also provides improved speed. The speed of the shift register stage is mainly determined by parasitic capacitance connected to the single node a, and a small signal resistance from a clock signal input ck to node a. The parasitic capacitance includes wiring capacitance and capacitance of the transistors connected to node a. 
         [0014]    A number of applications can take advantage of the resulting low power consumption and high speed. These include displays designed to use a shift register according to the new invention; portable devices that run on batteries such as video eyewear; electronic viewfinders for camcorder and digital cameras; military systems such as thermal weapon sights and night vision goggles; and other end uses. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention. 
           [0016]      FIG. 1  illustrates a prior art shift register stage that accommodates low voltage swing clock signal inputs. 
           [0017]      FIG. 2  illustrates another prior art shift register stage. 
           [0018]      FIG. 3  illustrates one embodiment of the invention. 
           [0019]      FIGS. 4A and 4B  illustrate clock signals in more detail. 
           [0020]      FIGS. 5A and 5B  show how multiple stages of  FIG. 3  are combined and a timing diagram. 
           [0021]      FIG. 6  is a high level diagram illustrating a bidirectional shift register. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0022]    A description of example embodiments of the invention follows. 
         [0023]      FIG. 3  illustrates a circuit  30  that improves over the arrangements of  FIGS. 1 and 2 . Here, the clock signal input ck also drives a stage transistor MP 1 . However, the gate of MP 1  is fed from a pair of cascode transistors MP 2  and MP 3  that set the state at node a as determined by inputs e* and vgp. The inverted input from the previous stage e* is fed to the input terminal of inverter INV 3  to control the gate of transistor MP 3 . The MP 3  drain terminal controls the gate of transistor MP 1 . The source terminal of transistor MP 2  is fed from voltage VDD. 
         [0024]    An intended pre-charge input pc* is fed through the single NAND gate together with a reset signal r*. The output of the single NAND gate drives the gate terminal of signal buffer transistor MN 1 . The first inverter INV 1  and second inverter INV 2  provide, respectively, the inverted outputs out* and non-inverted output out. 
         [0025]    Operation of circuit  20  is similar to that of circuit  20  of  FIG. 2 . However, the number of transistors connected to node a is reduced. In addition, through inverters INV 1  and INV 2 , node a is shielded from external wiring and devices driven by shift register stage  30 . The resistance from ck to node a is also reduced from that of a pair of cascode transistors to that of a single transistor. 
         [0026]    As for the circuit  20  of  FIG. 2 , vgp is set as VEE-vgp&lt;Vtp, where Vtp is the threshold voltage of transistor MP 1 . The diagram of  FIG. 4A  can help visualize this situation, where Vsw is the switching threshold of transistor MP 1  and Vtp is the p-channel threshold voltage of MP 1 . 
         [0027]      FIG. 4B  illustrates, more particularly, the situation of low voltage clock signal ck where the signal value varies from a high rail voltage VDD only down to a voltage VEE that is much greater than the low rail voltage VSS. The swing between VEE and VDD may, for example, be only 3.3 volts with the threshold voltage V th  set to slightly above VEE. 
         [0028]    The speed of the shift register stage  30  of  FIG. 3  is thus mainly determined by the parasitic capacitance connected to node a and the small signal resistance from the clock input ck to node a. This parasitic capacitance includes wiring capacitance and the capacitance of those transistors that are connected to node a. 
         [0029]    Transistor MP 1  is in turn biased such that it barely turns on when charging node a. Since this switching operation will already be relatively slow (i.e., it is controlled by a clock signal having a low voltage swing), one wants to avoid introducing extra resistance there. 
         [0030]    The output load presented by output driver inverters INV 1  and INV 2  is furthermore now reduced since node a need only drive the single input to inverter INV 1  and no external outputs directly. The inverters INV 1  and INV 2  thus also provide isolation from both outputs out and out*, providing circuit  30  with further isolation from the impedances that would be presented by external circuitry. 
         [0031]    The inverters INV 1  and INV 2  may comprise fast 10 volt swing gates that are of less concern in terms of power consumption than the rest of internal shift register  20  circuitry driven by the low voltage swing clock signals. This arrangement also reduces the capacitive load on node a by having only the single connection. 
         [0032]    The circuit  30  of  FIG. 3  thus allows node a to swing from VDD to VSS being driven only by a low voltage swing clock signal ck (swinging from a much lower voltage range from 0-3 volts), while minimizing both resistance load and capacitance load. The circuit  30  of  FIG. 3  thus provides advantages over the circuits  10  or  20  of  FIG. 1  and/or  FIG. 2  for the following reasons: 
         [0033]    1. By combining the small r* and pc* inputs, only one transistor (MN 1 ) is used to provide for pre-charging or resetting node a. 
         [0034]    2. By combining inputs vgp and e* before applying them to the stage circuitry, only one other transistor, MP 1 , is needed to drive the node a. This arrangement reduces the resistance provided from the clock input to node a thus, the resistance times capacitance (RC) delay, is also lower. 
         [0035]    3. By isolating both output signals out and out* with high voltage swing (10 volt) gates, increased speed is achieved. 
         [0036]      FIGS. 5A and 5B  illustrate how multiple individual stages  30  of  FIG. 3  may be combined to provide a pipelined shift register  50 . Here, at least three individual stages  30  are required to feed a logic bit  1  from input to output. The series connected (pipelined) stages  30 - 1 ,  30 - 2 , and  30 - 3  each have inverted output signals o* feeding the next successive inverted input signal e*. A pair of offset clock signals, ck 0  and ck 1 , feed respective stages. The output of a given stage  30 - 3  feeds the reset input of the initial stage. This circuit thus provides a type of circulating shift register in which a bit value may be shifted from input to output. 
         [0037]    The timing diagram of  FIG. 5B  illustrates that, for example, on the rising edge of the pre-charge pc signal all stages (o 0 , o 1 , o 2 , o 3 , etc.), are reset to a zero logic state. On the next rising edge of ck 0 , the output o 0  (from the first stage  30 - 1 ) will switch to a high logic value state. On the next rising edge of clock signal ck 1 , a similar change occurs in the state of o 1  (the output of second stage  30 - 2 ). On the next rising edge of clock signal ck 0 , output o 2  will also then reach a high voltage state. The feedback connection from the output o 2  of the third stage ( 30 - 3 ) back to the first stage  30 - 1  will then cause the output state o 0  of the first stage  30 - 1  to return to a low logic value. 
         [0038]    The feedback signal from the output o 3  of a stage  30 - 4  (not shown) similarly controls second stage  30 - 2 , and so on, in a string of such stages depending on the desired length of the shift register. 
         [0039]      FIG. 6  is a high level diagram illustrating how a pipelined shift register  50  such as shown in  FIG. 5A  may be arranged to provide a bidirectional shift register  60 . One such pipeline  50 - 1  is arranged to shift from left to right, and a second pipeline  50 - 2  to shift to right to left. Multiplexers  51 - 1 , . . .  51 - n - 1 ,  51 - n  connected to each output bit permit selection of the direction to be used. 
         [0040]    Shift registers according to the present invention may be used in many different applications. As but one example, displays of the type described in co-pending U.S. application Ser. No. 11/784,215 filed Apr. 5, 2007, hereby incorporated by reference, include an array of pixel elements. As is known in the art, those pixel elements are controlled by row select lines and column select lines. These select lines may be fed from respective shift registers  50  that are implemented as described herein. Displays of that type may in turn be used in digital cameras, digital Single Lens Reflex (SLR) cameras, night vision displays, handheld video games, mobile telephones, video eyewear devices, and other similar products. 
         [0041]    While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.