Abstract:
Circuits and methods for automated real-time tuning of wide range frequency/delay voltage controlled oscillators (VCO) using a reset mechanism, to account for run-time variations such as power supply, temperature, reference clock frequency and input slew drift etc is described. It finds extensive applications in wide range, multi frequency band phase and delay locked loops. In one embodiment, an automated Jump-Down band switching structure and method for use in VCOs with a plurality of frequency bands is described. This involves monitoring the VCO&#39;s analog control voltage signal until it reaches a predetermined lower limit, at which time band switching to an overlapping lower frequency band is triggered by an internally generated reset signal, while simultaneously charging the analog control voltage to a limit in a pre-determined range of the lower band, to avoid phase detector malfunctions in the PLL/DLL system at lower control voltages during band switch.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This U.S. Patent Application is related to U.S. patent application Ser. No. 11/928,093, filed Oct. 30, 2007, titled “DESIGN STRUCTURE FOR AN AUTOMATED REAL-TIME FREQUENCY BAND SELECTION CIRCUIT FOR USE WITH A VOLTAGE CONTROLLED OSCILLATOR”, which is a continuation in part of U.S. patent application Ser. No. 11/618,952, Filed Jan. 2, 2007, titled: “AUTOMATED REAL-TIME FREQUENCY BAND SELECTION CIRCUIT FOR USE WITH A VOLTAGE CONTROLLED OSCILLATOR”, and assigned to the present Assignee. 
     FIELD OF THE INVENTION 
     The present invention generally relates to the field of voltage controlled oscillators. The invention is directed to an automated real-time frequency band selection circuit and method for use with Voltage controlled oscillators that typically find usage in different circuits including Phase Locked Loops and Delay Locked loops. 
     BACKGROUND OF THE INVENTION 
     Voltage Controlled Oscillators(VCO) find usage in many circuits including Phase Locked Loop(PLL) and Delay Locked Loop(DLL) systems, where the VCO generates output frequencies depending on an input bias voltage to it. PLLs and DLLs are closed loop systems with feedback that employ voltage controlled elements and methods to generate reference frequencies for the loop to lock. VCOs can be implemented in many different known architectures such as LC tanks, Voltage bias controlled Inverter delay chains etc. Though the PLL is a different architecture than a DLL, they both use an Analog control voltage to control the VCO explained as follows. 
     In PLLs, based on feedback of how much the phase and/or frequency of a reference input signal is off from a derivative of VCO generated frequency, the VCO&#39;s bias voltage automatically moves in a direction so as to gradually increase/decrease the VCO&#39;s frequency for the loop to lock. Alternatively, in DLLs, based on feedback of how much the delay (hence phase) of a delayed signal from a reference input signal is off, the bias voltage controlling the delay of the inverters automatically moves in a direction so as to gradually increase/decrease the delay equal to an exact 1 period shift (or 360 degree phase shift). Both the PLLs and DLLs employ a phase detector that compares the reference input signal to the VCO derivative signal/inverter delayed signal generating increment or decrement pulses that in-turn increase or decrease a certain analog control voltage maintained by a charge pump, which is then fed back to the VCO/Delay inverters. 
     In an integrated circuit, a PLL or DLL circuit can be used to generate internal reference clock signals, their frequency divisions, precise phase shifts of one signal based on the frequency of the other etc. Because of process variations in an integrated circuit, and the Application&#39;s temperature and supply voltage variations, a VCO in an integrated circuit may require several frequency bands from which its operating frequency is selected. Consequently, a VCO may be provided that has a fixed set of frequency bands from which to choose at the initial start up of the PLL circuit (e.g., during the power-up sequence). However, when the VCO is operating, power supply voltage variations and temperature variations over time may affect the VCO frequency. For example, if the capacitance of an LC tank VCO changes with temperature or supply voltage or both, or if the Delay of inverter chain VCO changes with temperature or supply voltage or both, the PLL/DLL circuit has no mechanism for automatically adjusting its frequency band during operation and, consequently, the PLL/DLL circuit may lose its lock status and operate inefficiently possibly providing incorrect output frequencies, which is not acceptable. 
     A frequency band corresponds to a range of VCO output frequencies from a minimum to a maximum that is achieved by sweeping its control voltage in operational limits, covering all possible process, supply voltage and temperature conditions, and other specifications if any. Multiple frequency bands correspond to different bands provided by the same VCO when its architecture/operation is configured differently under the same above mentioned PVT and other specifications range. For continuity in frequencies covered by any two adjacent bands, there should be an overlap of frequencies. Configuring the VCO differently to fall in different bands can be linked to digital tune bits that can be externally controlled. This invention is targeted for automated band switching that involves internal automated real time tune bit transitions to change bands. 
     Currently known methods for automated band switching mechanisms include: band jumping from a higher band to the next lower band and so on; band jumping from a lower band to the next higher band and so on; intermingled band jumping. All of the art retains the control voltage while the band is switched. A different VCO frequency (or delay) occurs at the new band for each of the same control voltages. This could be a problem in certain situations where the control voltage in the new band is outside that band&#39;s operational limit. 
     One such situation is described in  FIG. 4A , which is a graph of VCO frequency vs. VCO control voltage.  FIG. 4B  shows five problem waveforms. Referring to the graph in  FIG. 4A , Let OP A  be the current operating point in higher band HB. Assuming a temperature or voltage supply drift, or lowering of input frequency to PLL/DLL system tends to make OP A  drift lower down the band to OP B . The VCO control voltage is at HB 0 . If delay 1/f 2  is not slow enough for a lock in the PLL/DLL system, then the system requires a band switch to a lower frequency band. When a switch from HB to a lower frequency band LB is made from operating point OP B  to OP C , the VCO&#39;s control voltage HB 0  stays the same while the internal tune bits automatically change. If the delay (inverse of new VCO frequency: 1/f 3 ) produced at the new control point is greater than 2× the input clock period f in , this causes the phase detector to malfunction by skipping one or more reference edges. This could happen if the frequency range covered by 2 bands is very large. The waveforms in  FIG. 4B  have voltage (y axis) vs. time (x axis) representation, the first waveform is a reference clock with a frequency f in  to the DLL. The second waveform is the VCO generated clock that is the delayed version of first waveform. The aim of the VCO is to shift each pulse of the reference clock by 1 period (360 degree phase shift), eg, 1 st  pulse of reference clock to dotted pulse of VCO clock. So the 2 nd  rising edge of reference clock aligns with the dotted VCO clock pulse&#39;s rising edge for DLL to lock. The dashed-line pulse shown represents operating point OP B  and is the reference&#39;s first pulse shifted by delay of 1/f 2 . The solid first pulse of the VCO clock is the reference clock delayed by 1/f 3 , represents the operating point OPc. The third waveform is a phase detector generated increment pulse that goes to the loop-controlling charge pump of the DLL. The solid-lined first increment pulse is an indication to move the first solid pulse of VCO clock towards the 3 rd  rising edge of the reference clock (which is a 720 degree phase shift) and is incorrectly locked. The correct increment pulse would be represented as the dashed pulse. So if a strobe signal is shifted by 90 degrees of reference clock in a locked DLL system, and if waveform  5  indicates the delayed strobe signal, then the dashed strobe signal is the correct output, but the DLL system shifts it incorrectly shown by the solid strobe signal, with an extra 360 degree phase of reference clock. 
     One embodiment describes methods and structures for the automated tuning of wide range frequency/delay VCOs used in wide range frequency PLLs and wide range delay DLLs, the large range accomplished with the use of multiple frequency or delay tuning bands, the automation utilizing a reset function that is invoked during band switching. This advance in structure is particularly needed in VCOs that have very wide delay tuning ranges using the analog tuning voltage within each individual tuning band. Presence of very large steps between the tuning ranges or bands even after sufficient overlap between the bands is possible. When large band switching steps (or coarse digital tuning) toward larger delays (smaller frequencies) are allowed, it makes possible a hazard of locking to an integer multiple greater than one of the desired delay increment/frequency decrement. The embodiments describe methods and structures to automatically switch bands with appropriate internal reset mechanisms, to a higher or a lower band depending on the current value of the VCO&#39;s control voltage, that could have moved and reached the end limit of the current band due to variations including supply voltage/temperature drifts or reference input frequency changes to the PLL/DLL system over time. 
     SUMMARY OF THE INVENTION 
     A structure of an automated band switching mechanism for use in VCOs with a plurality of frequency bands is described. The structure has a Jump-Down bands and a Jump-up bands. 
     The Jump Down structure takes the VCO&#39;s analog control voltage that adjusts the frequency within a chosen frequency band as input. The band switching is from a higher band to an overlapping lower band, if the analog control voltage has reached a lower operational limit in that band and is still not at the desired stable operation point, hence requiring a downward band shift. The structure comprises a monitoring circuitry configured to automatically monitor the analog control signal to preset limits and generate intermediate digital monitor control signals; an internal reset generation circuitry using the intermediate digital monitor control signals and issues a digital reset control signal signifying band switch and suspend the operation of the VCO until the analog control voltage is reset to a value in a predetermined range; a band selection circuit for automatically generating appropriate band selection tuning signal(s), as a function of the internal reset and current tuning values, the tuning bits combinations distinguishing one band from another; and charge up circuitry to raise the analog control voltage to a value in a pre-determined range for the next lower frequency band. 
     The Jump-up structure takes the VCO&#39;s analog control voltage as input. The band switches from a lower band to a higher band if the analog control voltage has reached a higher operational limit in the lower band and is still not at the desired stable operating point, thereby requiring an upward band shift. The structure comprises monitoring circuitry configured to automatically monitor the analog control signal to preset limits and generate intermediate digital monitor control signals; internal reset generation circuitry using the intermediate digital monitor control signals and issues a digital reset control signal signifying band switch and suspend the operation of the VCO until the analog control voltage is reset to a value in a predetermined range; a band selection circuit for automatically generating appropriate band selection tuning signal(s), as a function of the internal reset and current tuning values, the tuning bits combinations distinguishing one band from another; and charge down circuitry to lower the analog control voltage to a value in a pre-determined range for the next higher frequency band. 
     A Method of automated tuning is also provided. The method automatically monitors, selects and switches to a different frequency band from the current frequency band, among a plurality of bands during functional operation of a VCO system, depending on a variety of constraints. It comprises both Jump-down band and Jump-up band methods. 
     The jump-down method involves selecting a lower frequency band from higher frequency band in a multi-band VCO. This method includes a monitor procedure to monitor and compare an analog control voltage signal received from a VCO relative to a low pre-determined limit; a reset issue procedure to detect when the analog control voltage reaches its predetermined functional limit and issues an internal reset to suspend the VCO&#39;s operation while setting the analog control voltage to a value in a predetermined operable range for the next lower band; a band selection procedure for generating a band selection signal to select the next lower band; and a reset release procedure to put the VCO back in functional mode in the newly selected frequency band. 
     The jump-up method includes selecting a higher frequency band from lower frequency band in a multi-band VCO. This method includes a monitor procedure to monitor and compare an analog control voltage signal received from a VCO relative to a high pre -determined limit; a reset issue procedure to detect when the analog control voltage reaches its predetermined limit and issues an internal reset to suspend the VCO&#39;s operation while setting the analog control voltage to a value in a predetermined operable range for the next higher band; a band selection procedure for generating a band selection signal to select the next higher band; and a reset release procedure to put the VCO back in functional mode in the newly selected frequency band. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein: 
         FIG. 1   a  illustrates a high level block diagram of the automated tuning structure for band switching with internal reset, consisting of Jump-down and Jump-up structures 
         FIG. 1   b  illustrates a detailed block diagram of the Jump-Down structure of  FIG. 1   a    
         FIG. 1   c  illustrates a detailed block diagram of the Jump-Up structure of  FIG. 1   a    
         FIG. 2   a  is a graph illustrating the Jump-down band switching from a higher band to a lower band with the reset concept 
         FIG. 2   b  is a graph illustrating the Jump-up band switching from a lower band to a higher band 
         FIG. 3  is a flowchart illustrating the method for automated band switching using reset mechanism graphed in  FIGS. 2   a  and  2   b    
         FIG. 4  illustrates the a potential problem overcome by the invention 
         FIG. 5  shows a plot of internal reset signal generation, during band switching 
     
    
    
     DETAILED DESCRIPTION 
     A VCO has N frequency bands, with N being the highest frequency band, with adjoining bands having some frequency overlap. For selection each of the N bands, x tune bits are required where N&lt;=2^x. Referring  FIGS. 2   a  and  2   b , Let HB and LB be the higher and lower frequency bands of the VCO designed. Let ABS_LL and ABS_HL be the absolute lowest and highest operating value for the analog control voltage ACNTL to the VCO. These values depend on the architecture of the circuit (eg. Charge pump) that generates the control voltage, in the application the VCO is used in and is determine by how high and how low that circuit can go till, assuming a VCO system that puts out the highest frequency for a high control voltage. Extra tolerance can be built around each ABS_LL and ABS_HL value. So LL is functional low limit (ABS_LL+tolerance) at which band switch to lower band is triggered and HL is functional high limit (ABS_HL−tolerance) at which band switch to higher band is triggered. Let HB&#39;s frequency range be from fh 0  to fh 1 , fh 1  being the higher frequency corresponding to HL and fh 0  being the lower frequency corresponding to LL. Let LB&#39;s frequency range be from fl 0  to fl 1 , fl 1  being the higher frequency corresponding to HL and fl 0  being the lower frequency corresponding to LL. The bands overlap for continuity between fh 0  and fl 1 . 
     For given two overlapping bands a and b: If a is the higher band, then value RL[a,b] (reset limit) is recorded as that value of ACNTL, whose band b frequency corresponds to that band a frequency at control voltage LL. corresponding to frequency at LL of band a. For a&gt;b, the value UL is chosen as RL[a,b]&lt;=UL&lt;HL. If a is the lower band, then value RL[a,b] is recorded as that value of ACNTL, whose band a frequency corresponds to that band b frequency at control voltage HL. All combinations of overlapping bands are formed in a 2 dimensional matrix of RL[a,b]. Thus for given 2 bands a and b, For a&lt;b, The value DL is chosen as RL[a,b]&lt;=DL&lt;HL. 
       FIG. 2   a  is a graph illustrating the Jump-down band switching method from a higher band to an overlapping lower band with the reset concept. Let us assume that the VCO system is currently running stable condition in band HB at point OP 1  for a PLL/DLL system. Now if Temperature, supply voltage or other specifications to the VCO system drifts, or if the input frequency to the PLL/DLL changes so as to move OP 1  lower in the band in order to maintain lock in the PLL/DLL system, this will require a band jump to a lower band LB once OP 1  reaches switching SwP 1 . During Band switch from HB to LB, an internal reset signal can be issued that puts the VCO, PLL/DLL system is in suspended mode. The analog control voltage is then re-assigned a new starting value for the new band, and then the functional operation resumes after ACNTL is reset. This primarily overcomes situation described in paragraph [0008]. The new assigned value is chosen from a range of UL, between RL[HB,LB] and HL. If UL is chosen as RL[HB,LB], then Short Reset path(SRP 1 ) is chosen to reassign ACNTL to operating point OP 2  in the lower band LB after which the internal reset signal is released and the VCO system is in functional mode. If UL is chosen as just less than HL, then Long Reset path(LRP 1 ) is chosen to reassign ACNTL to operating point OP 3  in the lower band LB after which the internal reset signal is released and the VCO system is in functional mode. The shaded area represents the range in which the reset paths can be chosen. Once in functional mode, the operating point is free to move upwards or downwards within the lower band looking for lock in the PLL/DLL system. 
     Thus corresponding to the new higher starting value of ACNTL in the lower band, the starting delay (frequency inverse) in the lower band will not be more than twice the delay (frequency inverse) that was achieved in the higher band. The starting delay thus matches or is less than the slowest delay in the higher band. This new approach allows the delay ratio in adjacent delay bands to be larger and therefore can enable simpler designs with fewer bands to cover very large tuning ratios (maximum delay to minimum delay ratio). 
       FIG. 2   b  is a graph illustrating the Jump-up band switching method from a lower band to an overlapping higher band with the reset concept. Let us assume that the VCO system is currently running stable condition in band LB at point OP 4  for a PLL/DLL system. Now if Temperature, supply voltage or other specifications to the VCO system drifts, or if the input frequency to the PLL/DLL changes so as to move OP 4  higher in the band in order to maintain lock in the PLL/DLL system, this will require a band jump to a higher band HB once OP 4  reaches switching SwP 2 . During Band switch from LB to HB, an internal reset signal can be issued that puts the VCO, PLL/DLL system is in suspended mode. The analog control voltage is then re-assigned a new starting value for the new band, and then the functional operation resumes after ACNTL is reset. The new assigned value is chosen from a range of DL, between RL[LB,HB] and HL. If DL is chosen as RL[LB,HB], then Long Reset path(LRP 2 ) is chosen to reassign ACNTL to operating point OP 6  in the higher band HB after which the internal reset signal is released and the VCO system is in functional mode. If DL is chosen as just less than HL, then Short Reset path(SRP 2 ) is chosen to reassign ACNTL to operating point OP 5  in the higher band HB after which the internal reset signal is released and the VCO system is in functional mode. The shaded area represents the range in which the reset paths can be chosen. Once in functional mode, the operating point is free to move upwards or downwards within the higher band looking for lock in the PLL/DLL system. For the jump-up procedure, the two bands need not necessarily be overlapping in which case DL&#39;s range is between LL to HL. 
       FIG. 3  is a flowchart illustrating the method  300  for automated band switching using reset mechanism graphed in  FIGS. 2   a  and  2   b . Though this flowchart incorporates Jump-up method  300   a  and Jump-down method  300   b  combined, the flows of the Jump-up and Jump -down can also be independently in a VCO system. In a PLL/DLL system utilizing a VCO with N frequency bands, a flow described in  FIG. 2   b  can be used where band switching happens in a linear fashion from the highest frequency band to the next highest band during band jump-down, and where band switching happens in a linear fashion from the lowest frequency band to the next highest frequency band during band jump-up, until the PLL reaches lock in a stable operating point in one of the bands. The flow takes into account operating point drifts in a band due to temperature, supply voltage and/or other input variations. 
     Jump-down flow  300   a : A VCO system with 1 to N frequency bands in increasing order operating in functional mode is the start of the sequence (step  304 ). The current frequency band is defined as i (step  308 ). A monitor procedure (step  312 ) keeps track of the control voltage ACNTL. If ACNTL reaches the operating lowest value LL for a given band i, then (YES; step  316 ) a switch to the next lower band could be initiated, else (NO; step  308 ). (Step  316 )If the current band is already the lowest, then (YES; step  320 ) frequency range covered by the bands is not enough and error can be reported with the operating point either continuing to stay at LL or issuing a PLL/DLL system stop. If not (No; step  324 ), a reset issue procedure issues an internal reset signal IRjd. IRjd is then used to suspend appropriate circuitry in the VCO and/or PLL/DLL system (step  328 ). It then initializes (step  332 ) the ACNTL to an operational value for the next lower band, that value being UL that is between RL[i,i−1] and HL. A band selection procedure (step  336 ) changes the tune bits to set appropriate circuitry in the VCO and/or PLL/DLL system to select operation in the next lower frequency band i−1. A reset release procedure (step  340 ) then releases the internal reset signal IRjd, and the VCo and/or PLL/DLL system is in functional mode going back to step  308 . This flow is a continuous real-time flow in the VCO&#39;s operation. 
     Jump-up flow  300   b : A VCO system with 1 to N frequency bands in increasing order operating in functional mode is the start of the sequence (step  304 ). The current frequency band is defined as i (step  308 ). A monitor procedure (step  362 ) keeps track of the control voltage ACNTL. If ACNTL reaches the operating highest value HL for a given band i, the (YES; step  366 ) a switch to the next higher band could be initiated, else (NO; step  308 ). (Step  366 )If the current band is already the highest, then (YES; step  370 ) frequency range covered by the bands is not enough and error can be reported with the operating point either continuing to stay at HL or issuing a PLL/DLL system stop. If not (No; step  374 ), a reset issue procedure issues an internal reset signal IRju. IRju is then used to suspend appropriate circuitry in the VCO and/or PLL/DLL system (step  378 ). It then initializes (step  382 ) the ACNTL to an operational value for the next higher band, that value being DL that is between RL[i,i+1] and HL. A band selection procedure (step  386 ) changes the tune bits to set appropriate circuitry in the VCO and/or PLL/DLL system to select operation in the next higher frequency band i+1. A reset release procedure (step  390 ) then releases the internal reset signal IRju, and the VCO and/or PLL/DLL system is in functional mode going back to step  308 . This flow is a continuous real-time flow in the VCO&#39;s operation. 
     Both the Jump-down and Jump-up mechanisms can be used in tandem to make it an automated tuning system for bi-direction band switching. To generalize, the Jump-down method and the Jump-up methods described can be applied for any given two bands, not necessarily adjacent to each other among a plurality of bands. 
       FIG. 1   a  illustrates a high level block diagram of the automated tuning structure  10  for band switching with internal reset, consisting of Jump-down structure  100  and Jump-up structure  200 . Inputs to structure  10  are VCO&#39;s control voltage ACNTL, External Reset ER which is a digital signal. Outputs to structure  10  are ACNTL (fed back to input), Tune bits TUNE[ 1  to x] which are digital signals, Internal reset signals IRjd and IRju which are digital signals. 
     The Jump-down structure  100  consists of a Jump down Monitor circuit  110 , Internal Reset generation circuit  120 , a Charge-up circuit  130 , a Band selection circuit  199 , and a switch SWjd. Circuit  110  takes the VCO&#39;s analog control voltage ACNTL as an input, and outputs HIa and LOa that are edge-triggered pulses based on events happening inside circuit  110 . Circuit  110  also takes band selecting tune bits TUNE[ 1 -X] as input, which is used to compute different limits used by the monitor circuit  110 . Internal Reset Generation Circuit  110  takes HIa and LOa as inputs, and puts out a digital signal called Internal reset IRjd whose On -time (or Off-time if logic is reversed) is a function of HIa and LOa. IRjd is could be asynchronous or asynchronous to the VCO&#39;s frequency based on an optional synchoronous structure inside  120 . Band Select Circuit  199  is a state machine circuit that takes ER, IRjd, IRju and TUNE[ 1  to x] as inputs and outputs new tune bits TUNE[ 1  to x] that is fed back in. x signals are needed if at least N&lt;=2^x frequency bands are present. Outputs of Jump-Down Circuit  100  are ACNTL and TUNE[ 1  to x] signals that go to the VCO for changing bands, IRjd that go to the VCO and other PLL/DLL related circuitry to trigger band switching. Charge-up circuit  130  takes IRjd and ACNTL as input and outputs an analog signal ACNTLjd. Switch SWjd takes ACNTLjd as input and is controlled by another input IRjd such that if the reset is issued then the switch is closed and ACNTLjd is propagated as output to ACNTL, else the switch is open. 
     The Jump-up structure  200  consists of a Jump up Monitor circuit  210 , Internal Reset generation circuit  220 , a Charge-down circuit  230 , a Band selection circuit  199 , and a switch SWju. Circuit  210  takes the VCO&#39;s analog control voltage ACNTL as an input, and outputs HIb and LOb that are edge-triggered pulses based on events happening inside circuit  210 . Circuit  210  also takes band selecting tune bits TUNE[ 1 -X] as input, which is used to compute different limits used by the monitor circuit  210 . Internal Reset Generation Circuit  210  takes HIb and LOb as inputs, and puts out a digital signal called Internal reset IRju whose On -time (or Off-time if logic is reversed) is a function of HIb and LOb. ITRju is synchronous or asynchronous to the VCO&#39;s frequency based on an optional synchronous structure inside  220 . Band Select Circuit  199  is a state machine circuit that takes ER, IRjd, IRju and TUNE[ 1  to x] as inputs and outputs new tune bits TUNE[ 1  to x] that is fed back in. x signals are needed if at least N&lt;=2^x frequency bands are present. Outputs of Jump-up Circuit  200  are ACNTL and TUNE[ 1  to x] signals that go to the VCO for changing bands, IRju that go to the VCO and other PLL/DLL related circuitry to trigger band switching. Charge-down circuit  230  takes IRju and ACNTL as input and outputs an analog signal ACNTLju. Switch SWju takes ACNTLju as input and is controlled by another input IRju such that if the reset is issued then the switch is closed and ACNTLju is propagated as output to ACNTL, else the switch is open. 
       FIG. 1   b  illustrates a detailed block diagram of the Jump-Down circuit  100  of  FIG. 1   a . Jump-down monitor circuit  110  consists of an Upper Limit setter circuit  111   a , Lower Limit setter circuit  111   b , Upper Comparator  112   a , Lower Comparator  112   b , Edge -triggered Pulse generator  113   a  and  113   b  and Limit determiner logic  115 .  111   a  and  111   b  are required to output analog signal levels with values UL and LL that are used as references for  112   a  and  112   b . A typical implementation of Limit setters  111   a  and  111   b  can be done using voltage divider structures that divide down a regulated supply value to provide analog values, among other known ways to provide a voltage reference value. Typically resistor dividers that could appropriately voltage controlled to provide a variable value could be used. Limit Determiner logic  115  takes Tune[ 1  to x] bits as input, and inturn consists of a Current band decoder  116  and a Lookup table  117 . The Current band decoder  116  can use a typical decoder structure to uniquely identify the current band off the list of 1 to N bands, using the unique Tune bit setting, and output signals identifying the current band (CB) and next lower band (LB). This can then be used to look up on the pre-determined lookup 2-D RL table, based on VCO frequency band design results as described in para[0018]. The result of this lookup can then be appropriately coupled to the  111   a  circuit that should then output a voltage reference output of UL. Circuit  111   b  always puts out a voltage reference value of LL. Low comparator  112   b  compares the current ACNTL value to reference LL and outputs a digital value LL 1  when ACNTL goes equal or below LL from a higher value. This event is then recognized by edge-triggered pulse generator  113   b  implemented by standard latching techniques, that generates a one-shotted pulse signifying issuance of a reset signal IRjd to suspend VCO operation and start band switch to a lower band.  113   b  should be designed such that the width of the pulse at LOa should be just as small to turn switch SW 2  on, then propagate the logic 1 to inverter I 1 , and then propagate a 0 to I 2  input. Up comparator  112   a  compares the current ACNTL value to reference UL and outputs a digital signal UL 1  when ACNTL equals or goes beyond UL from a lower value. This event is then recognized by edge-triggered pulse generator  113   a  implemented by standard latching techniques, that generates a one-shotted pulse signifying completion of band switch to a lower band, reset of ACNTL value, and the release of reset signal IRjd to resume VCO operation.  113   a  should be designed such that the width of the pulse at HIa should be just as small to turn switch SW 1  on, then propagate the logic 0 to inverter I 1 &#39;s input, and then propagate a logic1 to I 2 &#39;s input.  112   a  and  112   b  can typically be implemented using known arts of Differential amplifier structures. In general, any pre-available comparator circuit for  112   a  and  112   b  can be used. It typically can be implemented using known arts of Differential amplifier structures. 
     Internal Reset circuit  120 &#39;s purpose is to provide an internal reset signal IRjd based on pulses at LOa and HIa. The block is designed such that reset IRjd is issued, when the LOa pulse occurs, and stays issued until the HIa pulse occurs during when it is released. One such implementation is described below: Internal reset generation circuit  120  comprises of switch SW 1 , switch SW 2 , Inverters I 1 , I 2  and I 3 , an optional synchronous reset circuit  121 . Inverter I 1 &#39;s output connects to Inverter I 2  and I 3 &#39;s input. I 3  is a weak inverter to feed back to its output back to I 1  to hold steady I 1 &#39;s input if SW 1  and SW 2  are open. SW 2 &#39;s one end connects to a high potential source such as supply to signify logic 1, and the other end connects to input of inverter I 1 . LOa described in above paragraph to signify reset issue, controls and turns SW 2  on for the duration of the one-shotted pulse LOa. SW 1 &#39;s one end connects to a low potential source such as ground to signify logic 0, and the other end is tied to input of inverter I 1 . HIa described in above paragraph to signify reset release, controls and turns SW 1  on for the duration of the one-shotted pulse HIa. Inverter I 2 &#39;s output goes as input to Synchronous Reset circuit  121  that in turn outputs digital reset signal IRjd. This is an optional circuit, implemented with standard latching techniques that can be used if the application of the VCO in a PLL/DLL system requires the reset signal to the different blocks in the PLL/DLL system to be synchronous with respect to a reference clock. Thus when LOa is triggered, the IRjd goes logic 1, and when HIa is triggered, IRjd goes logic 01. To generalize, the polarities can be reversed if the potentials at the ends of switches are reversed. 
     Charge-up circuit  130  takes IRjd and ACNTL as inputs and outputs analog signal ACNTLjd. When IRjd is issued, the value of ACNTLjd (initially having the same value as ACNTL) is made to rise over time until IRjd is released. It can typically be implemented with known structures of charge pumps, with the use of capacitors to retain the charged value. Switch SWjd connects ACNTLjd to the output that goes as ACNTL. IRjd controls the switch such that when it is issued, then the switch is closed, else it is open. 
     Band-select circuit  199  takes inputs IRjd and TUNE[ 1  to x] bits, and outputs TUNE[ 1  to x]. Assuming a sequential table of frequency bands, and their Tune bit settings, Circuit  199  is a state machine controller, that is implemented such that when reset IRjd is issued, the tune bits are changed so as to select the Tune bits[ 1  to x] corresponding to the next lower band. 
       FIG. 1   c  illustrates a detailed block diagram of the Jump-Up circuit  200  of  FIG. 1   a . Jump-up monitor circuit  210  consists of an Upper Limit setter circuit  211   a , Lower Limit setter circuit  211   b , Upper Comparator  212   a , Lower Comparator  212   b , Edge -triggered Pulse generator  213   a  and  213   b  and Limit determiner logic  215 .  211   a  and  211   b  are required to output analog signal levels with values HL and DL that are used as references for  212   a  and  212   b . A typical implementation of Limit setters  211   a  and  211   b  can be done using voltage divider structures that divide down a regulated supply value to provide analog values, among other known ways to provide a voltage reference value. Typically resistor dividers that could appropriately voltage controlled to provide a variable value could be used. Limit Determiner logic  215  takes TUNE[ 1  to x] bits as input, and in turn consists of a Current-band decoder  216  and a Lookup table  217 . This table is the same as Lookup table  117 . The Current-band decoder  216  can use a typical decoder structure to uniquely identify the current band off the list of 1 to N bands, using the unique Tune bit setting, and output signals identifying the current band (CB) and next higher band (HB). This can then be used to look up on the pre-determined lookup 2-D RL table, based on VCO frequency band design results as described in para[0018]. The result of this lookup can then be appropriately coupled to the  211   b  circuit that should then output a voltage reference output of DL. Circuit  211   b  always puts out a voltage reference value of HL. Upper comparator  212   a  compares the current ACNTL value to reference HL and outputs a digital value HL 1  when ACNTL goes equal or higher than HL from a lower value. This event is then recognized by edge-triggered pulse generator  213   a  implemented by standard latching techniques, that generates a one-shotted pulse signifying issuance of a reset signal IRju to suspend VCO operation and start band switch to a higher band.  213   a  should be designed such that the width of the pulse at HIb should be just as small to turn switch SW 3  on, then propagate the logic 1 to inverter I 4 , and then propagate a logic 0 to I 5 &#39;s input. Low comparator  212   b  compares the current ACNTL value to reference DL and outputs a digital signal DL 1  when ACNTL equals or goes lower than DL from a higher value. This event is then recognized by edge-triggered pulse generator  213   b  implemented by standard latching techniques, that generates a one-shotted pulse signifying completion of band switch to a higher band, ACNTL resetting, and the release of reset signal IRju to resume VCO operation.  213   b  should be designed such that the width of the pulse at LOb should be just as small to turn switch SW 4  on, then propagate the logic 0 to inverter I 4 , and then propagate a logic 1 to I 5 &#39;s input. In general, any pre-available comparator circuit for  212   a  and  212   b  can be used. It typically can be implemented using known arts of Differential amplifier structures. 
     Internal Reset circuit  220 &#39;s purpose is to provide an internal reset signal IRju based on pulses at HIb and LOb. The block is designed such that reset IRju is issued, when the HIb pulse occurs, and stays issued until the LOb pulse occurs during when it is released. One such implementation is described below: Internal reset generation circuit  220  comprises of switch SW 3 , switch SW 4 , Inverters I 4 , I 5  and I 6 , an optional synchronous reset circuit  221 . Inverter I 4 &#39;s output connects to Inverter I 5  and I 6 &#39;s input. I 6  is a weak inverter to feed back to its output back to I 4  to hold steady I 4 &#39;s input if SW 3  and SW 4  are open. SW 3 &#39;s one end connects to a high potential source such as supply to signify logic 1, and the other end connects to input of inverter I 4 . HIb described in above paragraph to signify reset issue, controls and turns SW 3  on for the duration of the one-shotted pulse HIb. SW 4 &#39;s one end connects to a low potential source such as ground to signify logic 0, and the other end is tied to input of inverter I 4 . LOb described in above paragraph to signify reset release, controls and turns SW 4  on for the duration of the one-shotted pulse LOb. Inverter I 5 &#39;s output goes as input to Synchronous Reset circuit  221  that in-turn outputs digital reset signal IRju. This is an optional circuit, implemented with standard latching techniques that can be used if the application of the VCO in a PLL/DLL system requires the reset signal to the different blocks in the PLL/DLL system to be synchronous with respect to a reference clock. Thus when HIb is triggered, the IRju goes logic 1, and when LOb is triggered, IRju goes logic 0. To generalize, the polarities can be reversed if the potentials at the ends of switches are reversed. 
     Charge-down circuit  230  takes IRju and ACNTL as inputs and outputs analog signal ACNTLju. When IRju is issued, the value of ACNTLju (initially having the same value as ACNTL) is made to fall over time until IRju is released. It can typically be implemented with known structures of charge pumps, with the use of capacitors to retain the charged value. Switch SWju connects ACNTLju to the output that goes as ACNTL. IRju controls the switch such that when it is issued, then the switch is closed, else it is open. 
     Band-select circuit  199  takes inputs IRju and TUNE[ 1  to x] bits, and outputs TUNE[ 1  to x]. Assuming a sequential table of frequency bands, and their Tune bit settings, Circuit  199  is a state machine controller, that is implemented such that when reset IRju is issued, the tune bits are changed so as to select the Tune bits[ 1  to x] corresponding to the next higher band. 
     Now that the basic building blocks of the structure have been defined, the working of the entire structure is now described, referring  FIG. 5 . If the VCO system is used in a PLL/DLL system, a starting frequency band and starting Analog control voltage ACNTL need to be initialized. This can be done using the External reset signal ER to set the starting frequency band, using the Band select  199  that selects the appropriate tune bits TUNE[ 1  to x]. For a given hardware and supply voltage and temperature conditions, let OP 1  (in  FIG. 5 ) be the current operating point in a locked system in functional mode in band i. Since the control voltage ACNTL is steady at OP 1  in band i, IRjd and IRju have not been issued, hence switches SWjd and SWju are open. Circuit  211   a  is set to output reference voltage HL. Circuit  211   b  is set to output reference voltage DL from the RL table  117  with value RL[i,i+1]. Circuit  111   a  is set to output reference voltage UL from the same RL table  117  with value RL[i,i−1]. Circuit  112   a  is set to output reference voltage LL. Since ACNTL at OP 1  is above LL, comparator  112   b &#39;s output, hence  113   b &#39;s output LOa is a logic 0. Hence switch SW 2  is open at this time. UL 1  could be a high or low depending on whether the OP 1 &#39;s ACNTL value is lower or higher than UL respectively. Since UL 1  is not in transition, pulse generator  113   a  does not trigger any pulse and its output HIa is 0. Now Assume Temperature or Voltage drifts or PLL/DLL reference clock changes push OP 1  down to SwP 1 . ACNTL is now at LL. This triggers comparator  112   b  to make LL 1  transit from 0 to high, which in turn makes pulse generator  113   b  produce a one-shotted pulse at LOa, This pulse briefly closes switch SW 2  feeding a logic1 to inverter I 1  input which propagates to optional circuit  121 . This makes IRj d go high, signifying reset issue. Even after the pulse at LOa goes away, the reset IRjd is maintained high even though SW 1  and SW 2  are open, due to inverter feedback using weak inverter I 3 . The issue of IRjd is now used to set appropriate circuitry in the VCO and PLL/DLL system to put the systems in suspend mode. Charge-up circuit  130  recognizes the IRjd issue and raises ACNTLjd over time, the rate of rise depending on  130 &#39;s architecture. IRjd&#39;s issue triggers band switching in circuit  199 , and the tune bits TUNE[ 1  to x] are now switched to represent the next lower band during the suspend mode. IRjd&#39;s issue also closes switch SWjd propagating the raised ACNTLjd back to ACNTL, raising it. This increase of ACNTL continues to happen until its value equals or goes higher than UL. This is detected by Up-comparator  112   a  that triggers UL 1  to go low. This transition is recognized by Pulse generator  113   a , generating a one-shotted pulse at HIa. This pulse briefly closes SW 1 , which is enough to propagate a logic 0 through the I 1 , I 2  inverter chain to optional circuit  121 , that makes IRjd go low (let us term this as reset release). Even after HIa pulse goes away making SW 1  open, the weak inverter I 3  feedback will maintain a low at input of I 1 , hence maintaining IRjd low. The reset release makes the Charge-up circuit  130  to not increase ACNTLjd anymore, hence maintaining ACNTL at UL. Reset release also opens switch SWjd, and puts the VCO and PLL/DLL in functional mode, in the next lower frequency band. ACNTL is now free to move up or down appropriately in the new band in a direction to make the PLL/DLL lock. The structures of the Jump-down  100  and Jump-up  200 , specifically the monitors  110  and  210 , and Internal reset generators  120  and  220 , are such that IRju and IRjd will never issue at the same time. Thus while the Jump-down  100  and Jump-up  200  are operational during the lower band transition described above, Switch SWju is open during the entire duration of the above events. So structure  200  does not affect the operation of  100  while  100  is working towards switching to a lower band and resetting the control voltage ACNTL to an operational value in the next band.  FIG. 5  also shows an illustration the issue and release of IRjd, corresponding to the events of OP 1 &#39;s downward drift resulting in a band switch to a lower band. 
     Now opposite to the above case, let us consider the upward movement of the operating point OP 4  in current band I, referring  FIG. 5 . For a given hardware and supply voltage and temperature conditions, let OP 4  (in  FIG. 5 ) be the current operating point in a locked system in functional mode. Since the control voltage ACNTL is steady at OP 4  in band i, IRjd and IRju have not been issued, hence switches SWjd and SWju are open. Circuit  211   a  is set to output reference voltage HL. Circuit  211   b  is set to output reference voltage DL from the RL table  117  with value RL[i,i+1]. Circuit  111   a  is set to output reference voltage UL from the same RL table  117  with value RL[i,i−1]. Circuit  112   a  is set to output reference voltage LL. Since ACNTL at OP 4  is below HL, comparator  212   a &#39;s output, hence  213   b &#39;s output HIb is a logic 0. Hence switch SW 3  is open at this time. DL 1  could be a high or low depending on whether the OP 4 &#39;s ACNTL value is higher or lower than DL respectively. Since DL 1  is not in transition, pulse generator  213   b  does not trigger any pulse and its output LOb is 0. Now assume Temperature or Voltage drifts or PLL/DLL reference clock changes push OP 4  up to SwP 2 . ACNTL is now at HL. This triggers comparator  212   a  to make HL 1  transit from 0 to high, which in turn makes pulse generator  213   a  produce a one-shotted pulse at HIb, This pulse briefly closes switch SW 3  feeding a logic 1 to inverter I 4  input which propagates to optional circuit  221  through I 5 . This makes IRju go high, signifying reset issue. Even after the pulse at HIb goes away, the reset IRju is maintained high even though SW 3  and SW 4  are open, due to inverter feedback using weak inverter I 6 . The issue of IRju is now used to set appropriate circuitry in the VCO and PLL/DLL system to put the systems in suspend mode. Charge-up circuit  230  recognizes the IRju issue and reduces ACNTLju over time, the rate of fall depending on  230 &#39;s architecture. IRju&#39;s issue triggers band switching in circuit  199 , and the tune bits TUNE[ 1  to x] are now switched to represent the next higher band during the suspend mode. IRju&#39;s issue also closes switch SWju propagating the lowered ACNTLju back to ACNTL, raising it. This lowering of ACNTL continues to happen until its value equals or goes lower than DL. This is detected by comparator  212   b  that triggers DL 1  to go low. This transition is recognized by Pulse generator  213   b , generating a one-shotted pulse at LOb. This pulse briefly closes SW 4 , which is enough to propagate a logic 0 through the I 4 , I 5  inverter chain to optional circuit  221 , that makes IRju go low (let us term this as reset release). Even after LOb pulse goes away making SW 4  open, the weak inverter I 6  feedback will maintain a low at input of I 4 , hence maintaining IRju low. The reset release makes the Charge-down circuit  130  to not decrease ACNTLju anymore, hence maintaining ACNTL at DL. Reset release also opens switch SWju, and puts the VCO and PLL/DLL in functional mode, in the next higher frequency band. ACNTL is now free to move up or down appropriately in the new band in a direction to make the PLL/DLL lock. Since IRju and IRjd will never issue at the same time, Switch SWju is open during the entire duration of the above higher band switching events. So structure  100  does not affect the operation of 200 while 200 is working towards switching to a higher band and resetting the control voltage ACNTL to an operational value in the next band. 
     The same sequence of band switching can be used when the PLL/DLL system utilizing the VCO is powered up in a certain band, and needs to switch one or more bands to achieve the final operating point after when lock is achieved.  FIG. 5  also shows an illustration the issue and release of IRju, corresponding to the events of OP 4 &#39;s downward drift resulting in a band switch to a lower band. 
     An exemplary embodiment has been disclosed above and illustrated in the accompanying drawings. It will be understood by those skilled in the art that various changes, omissions and additions may be made to that which is specifically disclosed herein without departing from the spirit and scope of the present invention. 
     The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.