Abstract:
A method for manufacturing a semiconductor device comprises forming a first plate electrode that defines a storage node region over a semiconductor substrate, forming a first dielectric film at sidewalls of the storage node region, forming a storage node over the storage node region, and forming a second dielectric film and a second plate electrode over the resulting structure, thereby preventing collapse of the storage node and also preventing generation of defects by electric short between capacitors.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The priority of Korean patent application No. 10-2008-0095360 filed Sep. 29, 2008, the disclosure of which is hereby incorporated in its entirety by reference, is claimed. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a capacitor. 
         [0003]    As the area occupied by a capacitor is decreased due to increasing integration of semiconductor devices, the effective surface of the capacitor is decreased so that it is impossible to secure sufficient capacitance of the capacitor. 
         [0004]    The capacitance of a capacitor increases as a dielectric constant of a dielectric film and the effective surface of an electrode is increased. By using this characteristic, a method for securing the capacitance of the capacitor has been studied. 
         [0005]    In order to secure the capacitance of the capacitor, the storage node is formed to have a three-dimensional concave or cylinder structure, thereby increasing the effective surface of the electrode. 
         [0006]    A concave-structured capacitor is obtained as follows. A hole in which an electrode of the capacitor is to be formed is formed in an interlayer insulating film. A storage node of the capacitor is formed over the inner surface of the hole. A dielectric film and an upper electrode are deposited over the resulting structure. As a result, the concave-structured capacitor is formed. 
         [0007]    However, due to the high integration of semiconductor devices, it is difficult to secure sufficient capacitance of the capacitor required per cell in the limited cell area with the concave-structured capacitor. 
         [0008]    As a result, a cylinder-structured capacitor is suggested to provide a larger surface than the concave-structured capacitor. 
         [0009]      FIGS. 1   a  to  1   d  are cross-sectional diagrams illustrating a method for manufacturing a conventional cylinder-structured capacitor. 
         [0010]    As shown in  FIG. 1   a,  a first interlayer insulating film  14 , a nitride film  16  for supporting a capacitor, and a second interlayer insulating film  18  are formed over a semiconductor substrate  10  in which a storage node contact plug  12  is formed. A hole  20  in which a storage node is to be formed is formed so as to connect the storage node contact plug  12 . 
         [0011]    As shown in  FIG. 1   b,  after a storage node  22  is formed in the hole  20 , a chemical mechanical polishing (CMP) process is performed to expose the top portion of the second interlayer insulating film  18 . 
         [0012]    As shown in  FIG. 1   c,  the first interlayer insulating film  14  and the second interlayer insulating film  18  are etched to form a capacitor dielectric film  24  over the storage node  22  and the nitride film  16 . 
         [0013]    As shown in  FIG. 1   d,  a plate electrode  26  is formed over the dielectric film  24 . 
         [0014]    The cylinder-structured capacitor may use the inner and outer surfaces of the storage node as the effective surface of the capacitor. As a result, the cylinder-structured capacitor can have a larger capacitance than the concave-structured capacitor. 
         [0015]    A dip-out process is required in order to remove the interlayer insulating film when the cylinder-structured capacitor is formed. 
         [0016]    However, the dip-out process causes leaning and collapse of the storage node because the dip-out process is performed by a wet method using a chemical solution. 
         [0017]    When the interlayer insulating film is removed while the aspect ratio of the storage node is increased due to the high integration of semiconductor devices, the supporting strength of the storage node is reduced to generate a bridge with other storage nodes, thereby degrading characteristics of the semiconductor device. 
         [0018]    In order to prevent the bridge, the interlayer insulating film for manufacturing a capacitor is configured to include a nitride film. However, the nitride film causes defects in deposition of dielectric materials. 
       BRIEF SUMMARY OF THE INVENTION 
       [0019]    Various embodiments of the invention relates to a method for manufacturing a semiconductor device that prevents collapse of a storage node when removing an interlayer insulating film in order to increase capacitance of a capacitor. 
         [0020]    According to an embodiment of the invention, a method for manufacturing a semiconductor device comprises: forming a first plate electrode that defines a storage node region (or hole) over a semiconductor substrate; forming a storage node in the storage node region; and forming a second dielectric film and a second plate electrode over the resulting structure. 
         [0021]    Preferably, the forming-a-first-plate-electrode includes: forming a first plate material over the semiconductor substrate; and etching the first plate material with a storage node mask to form the storage node region. 
         [0022]    Preferably, the forming-a-storage-node includes: forming a first dielectric film over the resulting structure including the first plate electrode; removing the first dielectric film disposed in the bottom of the storage node region; thereafter forming a storage node layer over the resulting structure including the first dielectric film; and thereafter etching the storage node layer and the first dielectric film to expose a top portion of the first plate electrode. 
         [0023]    Preferably, the removing-the-first-dielectric-film includes forming a photoresist pattern that exposes the bottom portion of the storage node region to etch the first dielectric film with the photoresist pattern as an etching mask. 
         [0024]    Preferably, the etching-the-storage-node-layer-and-the-first-dielectric-film includes: forming a photoresist pattern to expose the first dielectric film and the first storage node which are located at the top portion of the first plate electrode, and etching the storage node layer and the first dielectric film with the photoresist pattern as an etching mask. 
         [0025]    Preferably, the etching-the-storage-node-layer-and-the-first-dielectric-film includes: forming an insulating film planarized over the resulting structure; and performing a planarizing process to expose the first plate electrode. 
         [0026]    Preferably, the forming-a-storage-node includes: forming a first dielectric film over the resulting structure including the first plate electrode; performing a blanket-etching process on the first dielectric film; thereafter forming a storage node layer over the resulting structure; and thereafter etching the storage node layer to expose a top portion of the first plate electrode. 
         [0027]    Preferably, the etching-the-storage-node-layer includes forming a photoresist pattern to expose the first storage node disposed over the first plate electrode, and etching the storage node layer with the photoresist pattern as an etching mask. 
         [0028]    Preferably, the etching-the-storage-layer includes: forming an insulating film planarized over the resulting structure; and performing a planarizing process to expose the first plate electrode. 
         [0029]    Preferably, after forming the second plate electrode, the method further comprises: forming an interlayer insulating film over the second plate electrode; etching the interlayer insulating film to form a metal line contact hole; and filling a conductive material in the metal line contact hole to form a metal line contact plug. 
         [0030]    Preferably, the forming-a-metal-line-contact-hole includes etching the second plate electrode, the second dielectric film and the first plate electrode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIGS. 1   a  to  1   d  are cross-sectional diagrams illustrating a conventional method for manufacturing a semiconductor device; and 
           [0032]      FIGS. 2   a  to  2   i  are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0033]    Hereinafter, an embodiment of the invention will be illustrated in detail with reference to the attached drawings. 
         [0034]      FIGS. 2   a  to  2   i  are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention. 
         [0035]    Referring to  FIG. 2   a,  a first plate electrode  104  is formed over a semiconductor substrate  100  including a storage node contact plug  102 . 
         [0036]    Since the first plate electrode  104  determines a height of a capacitor, a thickness of the first plate electrode  104  can be formed corresponding to the height of the capacitor. That is forming the plate electrode  104  instead of the interlayer insulating film in order to determine the height of the capacitor. As a result, the disclosed method may prevent collapse of the storage node when the interlayer insulating film is removed because a process for removing the interlayer insulating film is not performed. 
         [0037]    As shown in  FIG. 2   b,  a photoresist film (not shown) is coated over the first plate electrode  104 . An exposing and developing process is performed with an exposure mask for defining a storage node to form a photoresist pattern (not shown). 
         [0038]    The first plate electrode  104  is etched with the photoresist pattern as an etching mask to form a hole  106  in which a storage node is to be formed. 
         [0039]    As shown in  FIG. 2   c,  a first dielectric film  108  is formed in the hole  106  and over the first plate electrode  104 . 
         [0040]    As shown in  FIG. 2   d,  a photoresist pattern (not shown) is formed over the first dielectric film  108 . The first dielectric film  108  is etched with the photoresist pattern as an etching mask so that the first dielectric film  108  disposed at the bottom of the hole  106  is etched. A blanket-etching process is performed on the first dielectric film  108  to expose the storage node contact plug  102 . 
         [0041]    The blanket-etching process is performed to connect the storage node contact plug  102  to a storage node layer  110  which is to be formed in a subsequent process. 
         [0042]    As shown in  FIG. 2   e,  the storage node layer  110  is formed over the first dielectric film  108  and in the hole  106 . The bottom of the storage node layer  110  contacts the storage node contact plug  102 . 
         [0043]    As shown in  FIG. 2   f,  the storage node layer  110  and the first dielectric film  108  are etched to expose the top portion of the first plate electrode  104 . As a result the storage node layer  110  is converted to a storage node that is defined within the hole  106 . The process of removing part of the first dielectric film  108  does not correspond to the blanket-etching process of the first dielectric film  108 , but to a mask process for etching the first dielectric film  108  to expose the contact plug  102  at the bottom of the hole  106 . In order to etch the storage node layer  110  and the first dielectric film  108 , an insulating film planarized (not shown) over the storage node layer  110  is formed, and a planarizing process is performed to expose the first plate electrode  104 . Otherwise, a photoresist pattern (not shown) is formed to expose the first dielectric film  108  and the storage node  110  formed over the first plate electrode  104 , and the storage node  110  and the first dielectric film  108  are removed using the photoresist pattern as an etching mask. 
         [0044]    As shown in  FIG. 2   g,  a second dielectric film  112  is formed over the storage node  110 , the top portion of the first dielectric film  108  and the first plate electrode  104 . 
         [0045]    As shown in  FIG. 2   h,  a second plate electrode  114  is formed over the second dielectric film  112 . 
         [0046]    As shown in  FIG. 2   i,  an interlayer insulating film  116  is formed over the second plate electrode  114 . A photoresist film is coated over the interlayer insulating film  116 . An exposing and developing process is performed on the photoresist film to form a photoresist pattern (not shown) that defines a metal line contact plug region. 
         [0047]    The interlayer insulating film  116  is etched with the photoresist pattern as an etching mask to form a metal line contact hole (not shown). A conductive material is filled in a metal line contact hole to form a metal line contact plug  118 . 
         [0048]    While the interlayer insulating film  116  is etched to form a metal line contact hole, the second plate electrode  114 , the second dielectric film  112 , and the first plate electrode  104  are etched to form a metal line contact hole (not shown). As a result, a metal line contact plug is formed to connect the second plate electrode  114  to the first plate electrode  104 . 
         [0049]    A metal line contact hole is formed over and into the first plate electrode  104  of the current invention. As a result, the metal line contact plug  118  is configured to connect the second plate electrode  114  electrically to the first plate electrode  104 . 
         [0050]    The method for electrically connecting the first plate electrode  104  to the second plate electrode  114  is not limited herein. 
         [0051]    However, it is preferable to connect the first plate electrode  104  electrically to the second plate electrode  114  because the aforementioned method does not require any additional processes. 
         [0052]    The disclosed method for manufacturing a capacitor does not comprise forming an interlayer insulating film but forming a plate electrode instead of the interlayer insulating film in order to determine the height of the capacitor. As a result, the disclosed method may prevent collapse of the storage node when the interlayer insulating film is removed because a process for removing the interlayer insulating film is not performed. 
         [0053]    Also, the disclosed method may prevent degradation of characteristics of the semiconductor device due to the collapse of the storage node when the aspect ratio of the storage node becomes larger due to high integration. 
         [0054]    The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps describe herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.