Abstract:
A dual mode satellite signal receiver capable of supporting at least two global navigation satellite systems and a satellite signal receiving method are provided. The dual mode satellite signal receiver comprises a frequency synthesizer for generating a local oscillator signal based on a reference frequency; a mixer for mixing the local oscillator signal with a satellite signal and outputting the mixed signal as a signal of an intermediate frequency band; a first filter for filtering the signal output from the mixer to reject an image signal and output only an actual signal; a second filter for filtering the actual signal to output only a predetermined bandwidth according to a positioning mode; and an amplifier for amplifying the second filter output signal to a predetermined level and outputting the amplified signal.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of the U.S. Provisional Application No. 61/067,642, filed on Feb. 29, 2008, the entire contents of which are incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The invention relates to a satellite signal receiver and a satellite signal receiving method. In particular, the invention relates to a satellite signal receiver and a receiving method that support a plurality of global navigation satellite systems. 
       BACKGROUND OF THE INVENTION 
       [0003]    The Global Navigation Satellite System (GNSS) accurately tracks the position of a target object on the ground using a network of artificial satellites in space. The GNSS includes the Global Positioning System (GPS) operated by the United States Department of Defense and the European Union&#39;s Galileo positioning system (Galileo) in the initial development phase. The GNSS is used in many applications, such as, for example, in positioning of aircraft or shipping vessels and in information/communications technology such as telematics. 
         [0004]    GPS is a global navigation satellite system that provides location information using signals from satellites orbiting the earth. GPS was primarily established for military purposes, but since 2000, selective availability (SA, an intentional noise) was removed from the signals making GPS widely available in various fields. Meanwhile, the Galileo positioning system is a global navigation satellite system intended primarily for civilian use. Galileo provides more precise measurement and enhanced signaling than GPS, and it is expected that the Galileo positioning system will be used in various fields in the future. However, the GPS and Galileo positioning systems are complementary to each other, and it is expected that the two systems will co-exist. Therefore, a satellite signal receiver operable in both GPS and Galileo positioning systems is desirable. 
       SUMMARY OF THE INVENTION 
       [0005]    An object of the invention is to provide a dual mode satellite signal receiver that is applicable to both GPS and Galileo Positioning Systems, and to provide a satellite signal receiving method for the dual mode satellite signal receiver. 
         [0006]    According to one aspect of the invention, a dual mode satellite signal receiver comprises: (1) a frequency synthesizer for generating a local oscillator signal based on a reference frequency; (2) a mixer for mixing the local oscillator signal with a satellite signal, and outputting the mixed signal as a signal of an intermediate frequency band; (3) a first filter for filtering the signal output from the mixer to reject an image/noise signal and output only an actual signal; (4) a second filter for filtering the actual signal output from the first filter to output only a predetermined bandwidth according to a positioning mode; and (5) an amplifier for amplifying the signal output from the second filter to a predetermined level and then outputting the amplified signal. 
         [0007]    According to another aspect of the invention, a dual mode satellite signal receiving method for a dual mode satellite signal receiver supporting at least two global navigation satellite systems comprises: (a) generating a local oscillator signal based on a reference frequency; (b) mixing the local oscillator signal with a satellite signal and outputting the mixed signal as a signal of an intermediate frequency band; (c) filtering the mixed signal to reject an image/noise signal and output only an actual signal; (d) filtering the actual signal to output only a predetermined bandwidth according to a positioning mode; and (e) amplifying the signal with the predetermined bandwidth to a predetermined level and then outputting the amplified signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a block circuit diagram of a dual mode satellite signal receiver according to an embodiment of the invention. 
           [0009]      FIG. 2  illustrates a configuration of the variable gain amplifier of  FIG. 1 . 
           [0010]      FIG. 3  is a circuit diagram illustrating an embodiment of the exponential current generator of  FIG. 2  according to the invention. 
           [0011]      FIG. 4  is a circuit diagram illustrating another embodiment of the exponential current generator of  FIG. 2  according to the invention. 
           [0012]      FIG. 5  is a block diagram of an embodiment of the fractional-N phase locked loop of  FIG. 1  according to the invention. 
           [0013]      FIG. 6  is a flow chart illustrating an embodiment a satellite signal receiving method of the dual mode satellite signal receiver according to of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0014]      FIG. 1  shows a dual mode satellite signal receiver according to the invention. The receiver comprises a low noise amplifier  100 , mixers  101  and  102 , buffers  103  and  104 , a passive poly-phase filter  105 , a buffer  106 , a band-pass filter  107 , a variable gain amplifier  108 , an analog-to-digital converter  109  and a fractional-N phase locked loop  110 . 
         [0015]    The low noise amplifier  100  amplifies the received satellite signal and outputs the amplified signal. The low noise amplifier  100  outputs a satellite signal of single phase as a differential signal. That is, the low noise amplifier  100  outputs a satellite signal of single phase as an ‘I’ (In-phase) signal and a ‘Q’ (Quadrature-phase) signal. Preferably, the satellite signal has a frequency of 1.575 GHz. The low noise amplifier  100  is designed to have a small noise factor and a gain of approximately 26 dB. 
         [0016]    The mixers  101  and  102  mix the satellite signal output from the low noise amplifier  100  with a signal output from the fractional-N phase locked loop  110 , and down-convert the mixed signal to an intermediate frequency band. The mixer  101 , which is an ‘I’ (In-phase) mixer, converts the ‘I’ signal output from the low noise amplifier  100  to an intermediate frequency band, and the mixer  102 , which is a ‘Q’ (Quadrature-phase) mixer, converts the ‘Q’ signal output from the low noise amplifier  100  to an intermediate frequency band. The mixer  101  and the mixer  102  have a phase difference of 90 degrees. Preferably, the mixers  101  and  102  down-convert a satellite signal of 1.575 GHz to a frequency of 4 MHz. 
         [0017]    When a satellite signal of 1.575 GHz is down-converted to a frequency of 4 MHz, the down conversion also creates a component of the 1.575 GHz signal at a frequency of −4 MHz. The signal component at the frequency of −4 MHz cannot be distinguished from a signal component at the frequency of 4 MHz. Therefore, the mixers  101  and  102  have a 90-degree phase difference to remove the signal component at the frequency of −4 MHz. The intermediate frequency signals output from the mixers  101  and  102  are respectively fed through the buffers  103  and  104 . 
         [0018]    The passive poly-phase filter  105  receives the 90-degree phase difference signals from the buffers  103  and  104 , rejects an image signal at the frequency −4 MHz, and outputs the actual signal at the frequency 4 MHz to the buffer  106 . In other words, between the signals at the frequencies of 4 MHz and −4 MHz, the passive poly-phase filter  105  rejects the noise/image signal, i.e. the signal at the frequency of −4 MHz, and passes the signal at the frequency of 4 MHz. 
         [0019]    The band-pass filter  107  filters and outputs a predetermined bandwidth of the signal from the buffer  106  based on a center frequency of 4 MHz, and rejects the other bandwidth. That is, in a GPS mode, the band-pass filter  107  passes a bandwidth of 2 MHz or 4 MHz based on a center frequency of 4 MHz, and in a Galileo mode, the band-pass filter  107  passes a bandwidth of 6 MHz based on a center frequency of 4 MHz. The center frequency of the band-pass filter  107  is automatically tuned to 4 MHz by a tuning loop  111 . 
         [0020]    The variable gain amplifier  108  amplifies the signal received from the band-pass filter  107  to a predetermined level, and outputs the amplified signal to the analog-to-digital converter  109 . To properly operate the analog-to-digital converter  109 , a signal level should be constant. An automatic gain control loop (AGC loop)  112  senses an output level of the variable gain amplifier  108 . If the output level is high, the automatic gain control loop  112  reduces a gain control voltage, so that a gain of the variable gain amplifier  108  is reduced. If the output level is low, the automatic gain control loop  112  increases a gain control voltage, so that a gain of the variable gain amplifier  108  is increased. The variable gain amplifier  108  controls a gain linearly in dB, and is discussed in more detail below. 
         [0021]    The analog-to-digital converter  109  converts an analog signal received from the variable gain amplifier  108  into a digital signal. Preferably, the analog-to-digital converter  109  converts an analog signal received from the variable gain amplifier  108  into a 2-bit digital signal according to a clock provided by the fractional-N phase locked loop  110 . 
         [0022]    The fractional-N phase locked loop  110  is a frequency synthesizer, and generates an accurate local oscillator (F LO ) signal using a reference frequency (Fref) and outputs the local oscillator signal to the mixers  101  and  102 . Because there is only one channel in GPS and Galileo Positioning Systems, it is possible to use an integer-N phase locked loop frequency synthesizer. However, the satellite signal receiver according to the invention may share a temperature compensated crystal oscillator (TCXO) with the other RF (radio frequency) transceiver coexisting on the same system. Therefore, the satellite signal receiver according to the invention uses a fractional-N phase locked loop that is capable of supporting multiple reference frequencies generated from the temperature compensated crystal oscillator. 
         [0023]    As mentioned above, the fractional-N phase locked loop  110  generates and outputs a local oscillator signal. In addition, the fractional-N phase locked loop  110  provides a clock signal to the tuning loop that automatically tunes the center frequency of the band-pass filter  107 , and provides a clock signal for signal sampling of the analog-to-digital converter  109 . 
         [0024]      FIG. 2  shows variable gain amplifier  108 , which includes an exponential current generator  201 , an exponential current-to-voltage converter  203  and an amplifier  205 . The exponential current generator  201  generates two exponential currents according to a linear gain control voltage received from an automatic gain control loop. The exponential currents indicates that the ratio of two generated currents has a characteristic of an exponential function. An equation of the ratio may represent either NMOS, PMOS or both. When an equation of the ratio includes both NMOS and PMOS, the property of exponential currents is influenced by a physical difference between NMOS and PMOS. However, where an equation of the ratio represents either NMOS or PMOS, the above-mentioned influence can be removed. The exponential currents generated in the exponential current generator  201  exhibit a linear characteristic when converting into unit of dB. 
         [0025]    The exponential current-to-voltage converter  203  converts the exponential currents generated in the exponential current generator  201  into voltage and outputs that voltage. The exponential current-to-voltage converter  203  converts the two currents into voltage. The voltage output from the exponential current-to-voltage converter  203  is referred to as a differential voltage. 
         [0026]    The amplifier  205  amplifies an input signal by controlling a gain according to the differential voltage received from the exponential current-to-voltage converter  203 , and outputs the amplified signal. The gain control in the amplifier  205  has a linear-in-dB characteristic. That is, in dB scale, the gain varies linearly to the differential voltage. 
         [0027]      FIG. 3  shows an embodiment of the exponential current generator of  FIG. 2  according to the invention. The exponential current generator  201  includes a single-to-differential converter  301 , a first current generator  303 , a first current mirror  304 , a second current generator  305  and a second current mirror  306 . The single-to-differential converter  301  amplifies a single-ended input signal and outputs the amplified signal as two differential signals.  FIG. 3  shows only a differential amplifier. As a differential signal, the single-to-differential converter  301  outputs the sum of a common-mode voltage (Vcm) and a control voltage (Vc), and a difference between a common-mode voltage (Vcm) and a control voltage (Vc). 
         [0028]    The first current generator  303  includes a PMOS transistor (M p1 ) and an NMOS transistor (M n1 ). A source terminal of the PMOS transistor (M p1 ) is connected to a direct voltage (VDD), a drain terminal of the PMOS transistor (M p1 ) is connected to a drain terminal of the NMOS transistor (M n1 ), and a gate terminal of the PMOS transistor (M p1 ) is connected to a gate terminal of the first current mirror  304 . 
         [0029]    The difference (Vcm−Vc) between a common-mode voltage (Vcm) and a control voltage (Vc) output from the single-to-differential converter  301  is inputted into a gate terminal of the NMOS transistor (M n1 ) of the first current generator  303 . The drain terminal of the NMOS transistor (M n1 ) is connected to a current source (I On1 ), and a source terminal of the NMOS transistor (M n1 ) is ground. In the first current generator  303 , a current (I D1 ) generated by the NMOS transistor (M n1 ) and the current source (I On1 ) are mirrored and output to the first current mirror  304  through the gate terminal of the PMOS transistor (M p1 ). Thus, a current output to the first current mirror  304  is the sum of the current (I D1 ) generated by the NMOS transistor (M n1 ) and the current source (I On1 ). 
         [0030]    The first current mirror  304  includes an NMOS transistor (M n3 ) and a PMOS transistor (M p3 ). As mentioned above, the first current mirror  304  outputs the sum of the current (I D1 ) generated by the NMOS transistor (M n1 ) and the current source (I On1 ) as a first current (I C1 ). 
         [0031]    Meanwhile, the second current generator  305  has the same circuit configuration as the first current generator  303 . A source terminal of a PMOS transistor (M p2 ) of the second current generator  305  is connected to a direct voltage (VDD), a drain terminal of the PMOS transistor (M p2 ) is connected to a drain terminal of an NMOS transistor (M n2 ), and a gate terminal of the PMOS transistor (M p2 ) is connected to a gate terminal of the second current mirror  306 . However, the sum (Vcm+Vc) of a common-mode voltage (Vcm) and a control voltage (Vc) generated from the single-to-differential converter  301  is input to a gate terminal of the NMOS transistor (M n2 ) of the second current generator  305 . 
         [0032]    In the second current generator  305 , a current (I D2 ) generated by the NMOS transistor (M n2 ) and a current source (I On2 ) are mirrored and output to the second current mirror  306  through the gate terminal of the PMOS transistor (M p2 ). Therefore, a current output to the second current mirror  306  is the sum of the current (I D2 ) generated by the NMOS transistor (M n2 ) and the current source (I On2 ). 
         [0033]    The second current mirror  306  includes an NMOS transistor (M n4 ) and a PMOS transistor (M p4 ). As mentioned above, the second current mirror  306  outputs the sum of the current (I D2 ) generated by the NMOS transistor (M n2 ) of the second current generator  305  and the current source (I On2 ) as a second current (I C2 ). 
         [0034]    The first current (I C1 ) of the first current mirror  304  and the second current (I C2 ) of the second current mirror  306  are input to the exponential current-to-voltage converter  203  of  FIG. 2 , which converts the currents into a differential voltage to be used in the amplifier  205 . 
         [0035]    The gain of the amplifier  205  is a ratio of input signal voltage to output signal voltage. A ratio of the first current (I C1 ) to the second current (I C2 ) of the exponential current generator  201  can be represented as an exponential function, so that the voltage ratio exhibits a linear characteristic in dB. The exponential function can be typically approximated with the Taylor Series. An approximation equation is represented by Equation 1. 
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                                                   n 
                                                 
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                                                     - 
                                                     
                                                       V 
                                                       THn 
                                                     
                                                   
                                                   ) 
                                                 
                                               
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                                           + 
                                         
                                       
                                     
                                     
                                       
                                         
                                           
                                             ( 
                                             
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                                               - 
                                               
                                                 
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                                             ) 
                                           
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                                   } 
                                 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
         [0037]    Here, K n1  and K n2  are current constants of the NMOS transistor (M n1 ) and the NMOS transistor (M n2 ), respectively. V THn1  and V THn2  are threshold voltages of the NMOS transistor (M n1 ) and the NMOS transistor (M n2 ), respectively. 
         [0038]    As shown in Equation 2, the ratio of the first current (I C1 ) to the second current (I C2 ) of  FIG. 3  is in the same form as the approximation equation of Equation 1. The ratio exhibits a characteristic of an exponential function. Therefore, the gain of amplifier  205  exhibits a linear characteristic in dB. Furthermore, the ratio of two currents is represented in the equation in terms of only NMOS constants K n1 , K n2 , V THn1  and V THn2 . Thus, the ratio maintains a characteristic of an exponential function even if a mismatch between NMOS and PMOS occurs due to change in temperature, process or supply voltage. 
         [0039]      FIG. 4  shows another embodiment of the exponential current generator of  FIG. 2  according to the invention. This exponential current generator includes a single-to-differential converter  401 , a first current generator  403 , a first current mirror  404 , a second current generator  405  and a second current mirror  406 . 
         [0040]    The single-to-differential converter  401  amplifies a single-ended input signal, converts the amplified signal into two differential signals, and outputs the differential signals.  FIG. 4  shows only a differential amplifier. As a differential signal, the single-to-differential converter  401  outputs the sum of a common-mode voltage (Vcm) and a control voltage (Vc), and a difference between a common-mode voltage (Vcm) and a control voltage (Vc). 
         [0041]    The first current generator  403  includes a PMOS transistor (M p1 ) and an NMOS transistor (M n1 ). Unlike the embodiment of  FIG. 3 , a source terminal of the PMOS transistor (M n1 ) is connected to a direct voltage (VDD), a drain terminal of the PMOS transistor (M p1 ) is connected to a drain terminal of the NMOS transistor (M n1 ), and the sum (Vcm+Vc) is connected to a gate terminal of the PMOS transistor (M p1 ). 
         [0042]    Meanwhile, a gate terminal of the NMOS transistor (M n1 ) of the first current generator  403  is connected to a gate terminal of an NMOS transistor (M n3 ) of the first mirror  404 . In the first current generator  403 , a current (I D1 ) generated by the PMOS transistor (M p1 ) and a current source (I On1 ) are mirrored and output to the first current mirror  404  through the gate terminal of the NMOS transistor (M n1 ). Therefore, a current received by the first current mirror  404  is the sum of the current (I D1 ) generated by the PMOS transistor (M p1 ) and the current source (I On1 ). 
         [0043]    The first current mirror  404  includes an NMOS transistor (M n3 ) and a PMOS transistor (M p3 ). As mentioned above, the first current mirror  404  outputs the sum of the current (I D1 ) and the current source (I On1 ) as a first current (I C1 ). 
         [0044]    Meanwhile, the second current generator  405  has the same circuit configuration as the first current generator  403 . A source terminal of a PMOS transistor (M p2 ) of the second current generator  405  is connected to a direct voltage (VDD), and a drain terminal of the PMOS transistor (M p2 ) is connected to a drain terminal of an NMOS transistor (M n2 ). However, the difference (Vcm-Vc) of a common-mode voltage (Vcm) and a control voltage (Vc) received from the single-to-differential converter  401  is input to a gate terminal of the PMOS transistor (M p2 ) of the second current generator  405 . 
         [0045]    In the second current generator  405 , a current (I D2 ) generated by the PMOS transistor (M p2 ) and a current source (I On2 ) are mirrored and output to the second current mirror  406  through a gate terminal of the NMOS transistor (M n2 ). Therefore, a current output to the second current mirror  406  is the sum of the current (I D2 ) generated by the PMOS transistor (M p2 ) and the current source (I On2 ). 
         [0046]    The second current mirror  406  includes an NMOS transistor (M n4 ) and a PMOS transistor (M p4 ). As mentioned above, the second current mirror  406  outputs the sum of the current (I D2 ) and the current source (Ion) as a second current (I C2 ). 
         [0047]    The first current (I C1 ) of the first current mirror  404  and the second current (I C2 ) of the second current mirror  406  are input to the exponential current-to-voltage converter  203  of  FIG. 2 , which converts the currents into a differential voltage to be used in the amplifier  205 . 
         [0048]    A ratio of the first current (I C1 ) to the second current (I C2 ) generated in the circuit of  FIG. 4 , is represented by Equation 3. 
         [0000]    
       
         
           
             
               
                 
                   
                     
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                             . 
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     3 
                   
                   ] 
                 
               
             
           
         
       
     
         [0049]    Here, K p1  and K p2  are current constants of the PMOS transistor (M p1 ) and the PMOS transistor (M p2 ), respectively, and V THp1  and V THp2  are threshold voltages of the PMOS transistor (M p1 ) and the PMOS transistor (M p2 ), respectively. 
         [0050]    As shown in Equation 3, the ratio of the first current (IC X ) to the second current (I C2 ) of  FIG. 4  is in the same form as the approximation equation of Equation 1. The ratio exhibits a characteristic of an exponential function. Therefore, the gain of the amplifier of  FIG. 2  exhibits a linear characteristic in dB. Furthermore, a ratio of two currents is represented in the equation in terms of only PMOS constants K p1 , K p2 , V THp1  and V THp2 . Thus, the ratio maintains a characteristic of an exponential function even if a mismatch between NMOS and PMOS occurs due to change in temperature, process or supply voltage. 
         [0051]      FIG. 5  shows an embodiment of the fractional-N phase locked loop  110  of  FIG. 1 , which includes a frequency detector  510 , a pulse-voltage converter  520 , a voltage controlled oscillator  530 , a ½ divider  540  and a fractional-N divider  550 . The frequency detector  510  compares a reference frequency with an output frequency of the fractional-N divider  550 , and outputs a pulse signal to the pulse-voltage converter  520 . Specifically, the frequency detector  510  compares the reference frequency to the output frequency of the fractional-N divider  550 . If the reference frequency is greater than the frequency of the factional-N-divider  550 , frequency detector  510  outputs an ‘up’ pulse signal. If the reference frequency is smaller than the frequency of the factional-N-divider  550 , the frequency detector  510  outputs a ‘down’ pulse signal. 
         [0052]    The reference frequency may be not a fixed frequency. As mentioned above, the satellite signal receiver according to the invention can share a temperature compensated crystal oscillator (TCXO) with the other RF (radio frequency) transceiver coexisting on the same system. Therefore, the reference frequency generated from the temperature compensated crystal oscillator may vary depending on the other RF transceiver. 
         [0053]    The pulse-voltage converter  520  generates and outputs a predetermined voltage according to the pulse signal output from the frequency detector  510 . The pulse-voltage converter  520  includes a charge pump  521  and a loop filter  522 . The charge pump  521  may provide or receive current depending on the signal from the frequency detector  510 . That is, when the pulse-voltage converter  520  receives an ‘up’ pulse signal from the frequency detector  510 , the pulse-voltage converter  520  provides current to the loop filter  522 . When the pulse-voltage converter  520  receives a ‘down’ pulse signal, the pulse-voltage converter  520  receives current from the loop filter  522 . When the loop filter  522  receives current from the charge pump  521 , an electric charge is accumulated in a capacitor to increase an output voltage, and when the loop filter  522  provides current to the charge pump  521 , an electric charge in the capacitor is dissipated to reduce an output voltage. The output voltage serves as a control voltage of the voltage controlled oscillator  530 . 
         [0054]    The voltage controlled oscillator  530  outputs a signal with a predetermined frequency according to the output voltage of the pulse-voltage converter  520 . An operating frequency of the voltage controlled oscillator  530  is determined by a coarse tuning controller  570 . The voltage controlled oscillator  530  adjusts the frequency according to the output voltage of the pulse-voltage converter  520  and outputs a signal. 
         [0055]    The ½ divider  540  divides by 2 the output frequency of the voltage controlled oscillator  530 , and outputs local oscillator signals. Specifically, the ½ divider  540  divides by ½ the output frequency of the voltage controlled oscillator  530 , and outputs two local oscillator signals of I-Phase having different phases (0 degree and 180 degrees) and two local oscillator signals of Q-Phase having different phases (90 degree and 270 degrees). 
         [0056]    The fractional-N divider  550  divides by N the frequency of the local oscillator signal output from the ½ divider  540 , and outputs the divided oscillator signal to the frequency detector  510 . The fraction divisor (a value of N in 1/N) of the fractional-N divider  550  is determined based on a reference frequency. As mentioned above, the reference frequency may vary depending on the other RF transceiver coexisting on the same system, and the fraction divisor is determined according to the determined reference frequency. 
         [0057]    The fractional-N divider  550  selects a fraction divisor according to a signal received from a sigma-delta modulator  560  to improve a phase noise performance. In particular, the fractional-N divider  550  selectively selects two fraction divisors (N and N+1) according to the signal received from a sigma-delta modulator  560  and divides the signal. The sigma-delta modulator  560  controls the fractional-N divider  550  so that an average of the fraction divisors selected by the fractional-N divider  550  is uniform, thereby improving the frequency resolution and compensating for fractional spurs. 
         [0058]      FIG. 6  is a flow chart illustrating an embodiment of a satellite signal receiving method of the dual mode satellite signal receiver according to the invention. The dual mode satellite signal receiver is first set to any one mode, either GPS mode or a Galileo Positioning System mode (S 601 ). After the mode is set, the dual mode satellite signal receiver receives a satellite signal. The low noise amplifier  100  amplifies the received satellite signal and outputs the amplified signal (S 603 ). Specifically, the low noise amplifier  100  has a small noise factor and a gain of approximately 26 dB. The amplifier amplifies the signal and outputs a single phase signal to two differential signal paths (‘I’ signal and ‘Q’ signal). 
         [0059]    Next, the mixers  101  and  102  mix the satellite signals received from the low noise amplifier  100  with local oscillator signals received from the fractional-N phase locked loop  110 , and down-convert the mixed signals to an intermediate frequency band (S 605 ). The mixer  101  and the mixer  102  output signals with phase differences of 90 degrees. Thus, an output signal of the mixer  101  is an ‘I’ signal of an intermediate frequency band, and an output signal of the mixer  102  is a ‘Q’ signal of an intermediate frequency band. Preferably, the mixers  101  and  102  down-convert a satellite signal of 1.575 GHz to a frequency of 4 MHz. 
         [0060]    Subsequently, the passive poly-phase filter  105  receives the ‘I’ and the ‘Q’ signals of a 90-degree phase difference from the mixers  101  and  102 , and rejects an image/noise signal and outputs only the actual signal (S 607 ). That is, the passive poly-phase filter  105  receives a 4 MHz signal and a −4 MHz signal, and rejects the image/noise signal, i.e. the signal of a frequency of −4 MHz. Only the 4 MHz signal passes through the passive poly-phase filter  105 . 
         [0061]    Next, the band-pass filter  107  outputs a predetermined bandwidth of the signal received from the passive poly-phase filter  105  based on a center frequency of 4 MHz, and rejects the other bandwidth (S 609 ). That is, in a GPS mode, the band-pass filter  107  passes a bandwidth of 2 MHz or 4 MHz based on a center frequency of 4 MHz, and in a Galileo mode, the band-pass filter  107  passes a bandwidth of 6 MHz based on a center frequency of 4 MHz. 
         [0062]    Subsequently, the variable gain amplifier  108  amplifies the signal received from the band-pass filter  107  to a predetermined level, and outputs the amplified signal to the analog-to-digital converter  109  (S 611 ). To properly operate the analog-to-digital converter  109 , the signal level should be constant. The automatic gain control loop senses the output level of the variable gain amplifier  108 . If the output level is high, the automatic gain control loop reduces a gain control voltage, so that a gain of the variable gain amplifier  108  is reduced. On the other hand, if the output level is low, the automatic gain control loop increases the gain control voltage, so that the gain of the variable gain amplifier  108  is increased. The variable gain amplifier  108  controls the gain linearly in dB. 
         [0063]    The analog-to-digital converter  109  then converts an analog signal received from the variable gain amplifier  108  into a digital signal. Preferably, the analog-to-digital converter  109  converts an analog signal into a 2-bit digital signal, and outputs the digital signal. 
         [0064]    The satellite signal receiving method according to the invention may be incorporated as a computer readable code in a computer readable medium. The computer readable medium includes all kinds of storage devices for storing data readable by a computer system. For example, the computer readable medium may be a CD-ROM (Compact Disc Read Only Memory), RAM (Random Access Memory), ROM (Read Only Memory), floppy disc, hard disc or magneto-optical disc. 
         [0065]    The above embodiments should not be deemed to limit the scope of this invention. Other embodiments, implementations, enhancements and variations may be within the scope of the invention based on what is described and illustrated herein.