Abstract:
A method and apparatus for detecting an error rate of a data stream. The data stream is divided into a sequence of blocks, and a detection interval is defined including a predetermined number of blocks in the sequence. For one or more of the blocks in the detection interval, respective error measures are computed responsive to the error rate of the data stream. The one or more blocks in the detection interval are classified as good or bad blocks by comparing the respective error measures to a first threshold. It is estimated that an error condition exists in the data stream by comparing a count of the bad blocks in the interval to a second threshold.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to high-speed digital communications, and specifically to SONET/SDH communication networks. 
     BACKGROUND OF THE INVENTION 
     SONET (Synchronous Optical Network) and SDH (Synchronous Digital Hierarchy) are two families of closely-related and mutually-compatible standards for high-speed data communication. These standards govern interface parameters; rates, formats and multiplexing methods; and operations, administration, maintenance and provisioning for high-speed signal transmission. SONET and SDH use frame formats for transmitting data. SDH/SONET requires that errors in transmission be detected and an alarm condition be set when a bit error rate in a data stream exceeds a specified level. The bit error rate (BER) is defined as the number of erred bits in a frame divided by the total number of bits in the frame. Typically, the BER alarm is an indication that a fiber channel over which the transmission is being conveyed has degraded, and the transmission is then switched to a different, undegraded channel. 
     The maximum permitted BER is a function of line type. Typically a defect condition is detected when the BER exceeds 10 −3 . A hysteresis is introduced in clearing the defect condition, so that typically only when the BER drops back below 10 −4  is the defect condition cleared. According to requirements set by the International Telecommunications Union (ITU) in standard G.783, detection and clearing of the defect state must take place within a specified detection time. Other requirement levels have different BER limits, such as 10 −4  or 10 −5 , and different detection times. 
     SDH/SONET data frames include bytes set aside for error detection using bit interleaved parity (BIP) checks. For each frame, the BIP is calculated before transmission and is then transmitted with the next frame. At the receiving end, the BIP is recalculated and compared with the transmitted BIP value in the next frame. A discrepancy between recalculated and transmitted BIPs is noted as a BIP error. It is intuitively clear that the number of BIP errors in a given time period is a function of the current BER, and therefore BIP error detection is used for the purpose of BER defect detection and clearing. The relation between BIP errors and BER is probabilistic, so that a certain amount of uncertainty is inevitable in using BIP errors to track BER defects. The ITU requires that when BER≧10 −3 , BIP processing (or any other estimation method that is used) detect the defect condition within the permitted detection time (40 ms in one specific case) with a detection probability of ≧0.99, whereas when BER≦10 −4 , the false alarm probability, i.e., the chance of incorrectly reporting a detected defect condition, should be ≦10 −6 . By the same token, when BER≦10 −4 , the probability of clearing an existing defect condition should be ≧0.99, whereas the probability of clearing while BER≧10 −3  should be ≦10 −6 . The required calculations must be performed at high speed and impose a heavy load on the hardware and software responsible for BER defect detection. 
     A number of methods have been proposed to reduce the hardware and software resources required for BER detection. For example, U.S. Pat. No. 5,764,651, whose disclosure is incorporated herein by reference, describes a system for finding an error rate in a data stream using a variable length window to sample erred bits in the data stream. If the measured error rate, based on BIP calculation, is greater than an allowable threshold, the window length is reduced. When the window length reaches zero, a defect condition is detected. 
     European Patent Application EP 862,292, whose disclosure is incorporated herein by reference, describes a method for BER detection using two or more BIP monitors with respective fixed window lengths. Each of the monitors detects the presence or absence of a particular BER, for example, 10 −6  and 10 −7 , respectively, by integrating BIP errors over time. A monitor client reacts to notifications from the BER monitors so as to determine that the BER state of the data stream has changed and to generate an alarm when appropriate. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide improved methods and apparatus for monitoring the BER of a data stream. 
     In some aspects of the present invention, the methods and apparatus are applied to a SDH/SONET data stream so as to detect and clear BER defect states in accordance with accepted communications standards. 
     It is a further object of some aspects of the present invention to provide reliable and flexible methods and devices for detecting and clearing BER defect states based on BIP error detection. 
     In preferred embodiments of the present invention, an error detection method for detection of BER conditions in a SDH/SONET data stream comprises first and second processing stages. In the first stage, data blocks of given size are successively processed to determine a measure of bit errors in each block, preferably based on the number of BIP errors in the block. If the error measure in a given block exceeds a first predetermined threshold, the block is noted as an error block. In the second stage, the error results are stored, preferably in a shift register, for an interval of time containing a selected number of successive blocks. The shift register thus defines a “rolling window” in time. If the number of error blocks within the interval exceeds a second threshold, then a BER defect condition is detected. The size of the data blocks, the duration of the window, and the first and second thresholds are chosen based on the statistical relationship of the number of BIP errors to the BER of the data stream, so that the actual BER condition is detected within the time permitted and with the levels of confidence (i.e., high detection rate and low false alarm rate) dictated by applicable standards. 
     Once the BER defect condition is detected, one or more of the detection parameters, preferably including the second threshold, are readjusted. The new second threshold represents a maximum number of error blocks in the rolling window for which the error condition will be maintained. When the number of error blocks in the window drops below this threshold, the BER condition is cleared. Optionally, other parameters, such as the block size, window length and first threshold, may also be changed when seeking to clear the BER defect condition. Maintaining these other parameters at the same values for both the defect detection and defect clearing phases of operation is generally advantageous, however, since it simplifies the hardware and software design of the device. 
     Preferably, for the sake of computational simplicity and speed, the errors are determined with respect to a BIP 2  calculation, comprising a 2-bit result in which one bit is the XOR of all of the even bits in a given data frame, and the other bit is the XOR of all of the odd bits. Alternatively, however, any other type of BIP calculation, such as BIP8 (yielding an eight-bit result) or error detection calculations of other types, may be used. 
     There is therefore provided, in accordance with a preferred embodiment of the present invention, a method for detecting an error rate of a data stream, including: 
     dividing the data stream into a sequence of blocks; 
     defining a detection interval including a predetermined number of blocks in the sequence; 
     computing for one or more of the blocks in the detection interval respective error measures responsive to the error rate of the data stream; 
     classifying the one or more blocks in the detection interval as good or bad blocks by comparing the respective error measures to a first threshold; and 
     estimating that an error condition exists in the data stream by comparing a count of the bad blocks in the interval to a second threshold. 
     Preferably, computing the error measures includes computing bit interleave parity (BIP) values and comparing the computed BIP values to reference BIP values transmitted with the data stream to find BIP errors. Further preferably, each of the blocks includes a predetermined number of data frames, and computing and comparing the BIP values includes computing BIP values with respect to the frames. Most preferably, the BIP values include BIP 2  values. 
     Preferably, computing the BIP values includes counting how many BIP errors occur in a given one of the blocks. Most preferably, the first threshold defines a number of BIP errors that may occur in the block, such that classifying the one or more blocks includes counting a block as bad if the number of BIP errors in the block is greater than or equal to the defined number. Further preferably, estimating that the error condition exists includes estimating that the error rate of the data stream exceeds a permitted bit error rate (BER) and setting a BER output responsive to the estimation. 
     Preferably, the data stream is conveyed over a SDH/SONET network element. 
     Preferably, estimating that the error condition exists includes determining that there is a detection probability greater than a minimum detection probability that the error rate of the data stream exceeds a predetermined error level. Further preferably, estimating that the error condition exists includes determining that there is a false alarm probability less than a maximum false alarm probability that the error rate of the data stream is less than a predetermined clear level. Most preferably, the first and second thresholds are chosen responsive to the minimum detection probability and maximum false alarm probability. In a preferred embodiment, dividing the data stream into blocks includes selecting a block size responsive to the minimum detection probability and maximum false alarm probability, and wherein the first and second thresholds are chosen responsive to the block size. 
     Preferably, defining the detection interval includes defining an interval that is no greater than a maximum detection time permitted for estimating that the error condition exists when the error rate of the data stream exceeds a predetermined error level. 
     In a preferred embodiment, defining the detection interval includes defining a sliding window, such that periodically a new block in the sequence is added to the interval, and the earliest block in the sequence that is contained in the interval is removed therefrom. Preferably, estimating that the error condition exists includes estimating that an error condition exists if all of the blocks in the interval have error measures greater than or equal to the first threshold. 
     In a further preferred embodiment, the method includes: 
     defining a clear interval including a predetermined number of blocks in the sequence; 
     computing the respective error measures for the blocks in the clear interval; 
     classifying the one or more blocks in the clear interval as good or bad blocks by comparing the respective error measures to a third threshold; and 
     estimating that the error condition in the data stream is cleared by comparing a count of the bad blocks in the clear interval threshold to a fourth threshold. 
     Preferably, the fourth threshold is set so that the error condition is cleared when none of the blocks in the clear interval have error measures greater than or equal to the third threshold. Additionally or alternatively, the third threshold is equal to the first threshold. Further additionally or alternatively, the clear interval is equal in length to the detection interval. 
     There is also provided, in accordance with a preferred embodiment of the present invention, an error detection unit for detecting an error rate of a data stream, which is divided into a sequence of data blocks, the unit including: 
     an error accumulator, which computes respective error measures for data blocks in the data stream, responsive to the error rate of the data stream; 
     a comparator, which compares the error measures of the blocks to a first threshold so as to identify bad blocks in the data stream; and 
     decision logic, which receives the identification of the bad blocks from the comparator and estimates that an error condition exists responsive to a comparison of a count of the bad blocks in the data stream within a predetermined detection interval to a second threshold. 
     Preferably, the unit includes an integration counter, which counts the frames in the data stream and is programmed to issue a signal to the error accumulator indicative of the end of a block after the predetermined number of frames has passed. Most preferably, the predetermined number of the frames in the block and the first and second thresholds are programmable responsive to error condition criteria associated with the data stream. 
     Preferably, the data stream is conveyed over a SDH/SONET network element. 
     Additionally or alternatively, the unit includes a shift register, which receives and stores the identification output by the comparator for a number of the blocks in sequence corresponding to the predetermined detection interval, wherein periodically the identification of a new block in the sequence is input to the shift register, thereby defining a sliding detection window. Preferably, the decision logic estimates that the error condition exists if all of the blocks in the interval are identified in the shift register as bad blocks. 
    
    
     The present invention will be more fully understood from the following detailed description of the preferred embodiments thereof, taken together with the drawings in which: 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a flow chart that schematically illustrates a method for BER defect detection and clearing, in accordance with a preferred embodiment of the present invention; 
     FIG. 2 is a flow chart that schematically illustrates details of the method for BER defect detection shown in FIG. 1, in accordance with a preferred embodiment of the present invention; 
     FIG. 3 is a flow chart that schematically illustrates details of the method for BER defect clearing shown in FIG. 1, in accordance with a preferred embodiment of the present invention; 
     FIG. 4 is a flow chart that schematically illustrates details of a method for finding block errors, in accordance with a preferred embodiment of the present invention; and 
     FIG. 5 is a block diagram that schematically illustrates an error detection unit for BER defect detection and clearing, in accordance with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 is a flow chart that schematically illustrates a method for detecting and clearing a defect condition in the bit error rate (BER) of a SDH/SONET data stream, in accordance with a preferred embodiment of the present invention. The method is based on determining the number of bit interleave parity (BIP) errors in the data stream. 
     For the sake of computational simplicity and speed, the errors are determined with respect to a BIP 2  calculation, comprising a 2-bit result in which one bit is the XOR of all of the even bits in a given data frame, and the other bit is the XOR of all of the odd bits. As described in greater detail hereinbelow, the method compares the number of BIP 2  errors, n d , in each data block in the data stream to a first predetermined threshold, or BIP 2  threshold, N t   d , in order to classify the block as acceptable or errored (or “bad”). When the number of bad blocks, m d , in a block sequence (or interval) of a given length, M d , exceeds a second threshold, or block threshold, M t   d , the BER condition is considered to exist. By way of introduction to the preferred implementation of the method shown in FIG. 1, the following description of the theoretical basis for this method is first presented. 
     For a given BER, the probability that the BIP 2  even parity bit or the odd parity bit is errored is given by:                P   BIP     =       ∑       i   =   1     ,   3   ,   …   ,   L                  C   L   i          (   BER   )       i            (     1   -   BER     )       L   -   i                   (   1   )                                
     wherein L is the number of bits in the checksum (L=416 for a standard SDH frame, for example), and                C   L   i     =       L   !         i   !            (     L   -   i     )     !                 (   2   )                                
     For the purposes of BER detection based on the BIP 2  results, a block is defined as containing a certain number of data frames K d . The number of BIP 2  bits in a block is thus N d =2K d . The number of frames in the block is chosen so as to ensure that the BER condition will be detected or cleared within the requisite time limit. In the case of the ITU requirements described in the Background of the Invention, the time limit for use with VT1.5 is 40 ms. Since the duration of each frame is 0.5 ms, there are 4 BIP 2  bits received per millisecond. In a preferred embodiment of the present invention described hereinbelow, a suitable block size for use with VT1.5 SDH/SONET lines has been found to be 24 frames, so that the duration of a block is 12 ms. To meet the detection time limit, therefore, the BER condition must be detected or cleared within three such blocks, allowing 36 ms for data collection and 4 ms additional for processing and communications. For a 12 ms block, there are thus N d =48 BIP 2  bits. 
     A block is considered to be errored if the number of BIP 2  errors in the block n d  is greater than the selected BIP 2  threshold N t   d . The probability of such an occurrence for a given value of P BIP  (from equation 1) is given by:                P     bad        -        block       =         ∑     N   d           n   d     =     N   t   d                    C     N   d       n   d            (     P   BIP     )         n   d              (     1   -     P   BIP       )         N   d     -     n   d                     (   3   )                                
     When N d  is large, this definition can be simplified using the Poisson approximation, as is known in the art:                P     bad        -        block       ≈            [       -     N   d            P   BIP       ]                ∑     N   d           n   d     =     N   t   d                  (       N   d          P   BIP       )       n   d           n   d     !                   (   4   )                                
     The probability of detecting a BER defect state is defined to be the probability that within the M d  blocks considered in a given interval, there are at least M t   d  errored blocks, as given by:                P   defect     =         ∑     M   d           m   d     =     M   t   d                    C     M   d       m   d            (     P     bad        -        block       )         m   d              (     1   -     P     bad        -        block         )         M   d     -     m   d                     (   5   )                                
     This formula is used to determine values of P defect  for various choices of the parameters N d , N t   d , M d  and M t   d , so that the defect detection requirements of the applicable standard are met. Thus, for example, to meet the ITU requirements described in the Background of the Invention, when BER≧10 −3 , P defect  must be at least 0.99 (i.e., 99% probability of detection), whereas if BER≦14 −4 , P defect  must be no greater than 10 −6 . As noted above, N d  and M d  must also be chosen so as to satisfy the time limit for BER detection, 40 ms. 
     Table I illustrates values of N t   d , M d , and M t   d  determined using equations (1) through (5) hereinabove for BER error detection in accordance with ITU requirements for a VT1.5 SDH/SONET line. Each entry in the table represents choices of N t   d  that can, theoretically, satisfy the detection requirements for a given pair of values of M d  and M t   d . Two choices of N t   d  are given for each entry, N max  and N min  (in the format N min ;N max ), wherein N max  is the largest choice of N t   d  that will satisfy the 99% correct detection requirement, and N min  is the smallest choice of N t   d  that will satisfy the false alarm requirement. The actual BIP error threshold N t   d  must be chosen to satisfy both of these requirements, so that entries for which N min &gt;N max  cannot be used. 
     
       
         
               
               
               
             
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE I 
               
             
             
               
                   
                   
               
               
                   
                 M t   d   
                   
               
             
          
           
               
                 M d   
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
                 7 
                 8 
               
               
                   
               
               
                 1 
                 20;28 
                   
                   
                   
                   
                   
                   
                   
               
               
                 2 
                 14;16 
                 10;10 
               
               
                 3 
                 12;10 
                 8;8 
                 6;6 
               
               
                 4 
                 10;8  
                 6;6 
                 6;6 
                 4;2 
               
               
                 5 
                 10;6  
                 6;6 
                 4;4 
                 4;4 
                 4;2 
               
               
                 6 
                 8;6 
                 6;6 
                 4;4 
                 4;4 
                 4;2 
                 2;0 
               
               
                 7 
                 8;6 
                 6;4 
                 4;4 
                 4;4 
                 4;2 
                 2;2 
                 2;0 
               
               
                 8 
                 8;4 
                 6;4 
                 4;4 
                 4;2 
                 2;2 
                 2;2 
                 2;0 
                 2;0 
               
               
                   
               
             
          
         
       
     
     Equations (1) through (5) are also used to find values of the parameters N d , N t   d , M d  and M t   d  to be used in clearing the BER defect condition. The chosen parameters must lead to values of P defect  that satisfy the applicable clear detection and false alarm rate requirements, i.e., such that for BER≦10 −4 , (1−P defect ) ≧0.99, and for BER≧10 −3 , (1−P defect )≦10 −6 . Values of N t   d  meeting these requirements are shown in Table II, in the same format as in Table I. 
     
       
         
               
               
               
             
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE II 
               
             
             
               
                   
                   
               
               
                   
                 M t   d   
                   
               
             
          
           
               
                 M d   
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
                 7 
                 8 
               
               
                   
               
               
                 1 
                 12;16 
                   
                   
                   
                   
                   
                   
                   
               
               
                 2 
                 8;8 
                 6;4 
               
               
                 3 
                 6;6 
                 4;4 
                 4;0 
               
               
                 4 
                 6;4 
                 4;4 
                 4;2 
                 2;0 
               
               
                 5 
                 6;4 
                 4;2 
                 2;2 
                 2;0 
                 2;0 
               
               
                 6 
                 6;4 
                 4;2 
                 2;2 
                 2;2 
                 2;0 
                 2;0 
               
               
                 7 
                 4;2 
                 4;2 
                 2;2 
                 2;2 
                 2;0 
                 2;0 
                 2;0 
               
               
                 8 
                 4;2 
                 4;2 
                 2;2 
                 2;2 
                 2;0 
                 2;0 
                 2;0 
                 2;0 
               
               
                   
               
             
          
         
       
     
     For the purposes of hardware simplicity in implementation, it is desirable that the parameters N d , M d  and M t   d  have the same values for defect clearing as for defect detection. The values must in any case meet the defection and clearing time requirements of the applicable standard, in this case, 40 ms. It is also desirable that several blocks be examined before setting or clearing the error condition, i.e., that M d &gt;1, in order to reduce the sensitivity of defect detection to transient burst errors. Preferably, for the purpose of defect detection, M d =M t   d ; and for defect clearing M t   d =1. These conditions imply that the BER defect is detected when m d =M d , so that all of the blocks found within a sequence of M d  consecutive blocks are errored; and the defect state is cleared only if m d =0, when there are no errored blocks found within a sequence of M d  consecutive blocks that are considered. 
     With regard to the values of N t   d  shown in Tables I and II, it is seen that these criteria are satisfied by choosing M d =3, with M t   d =3 for defect detection and M t   d =0 for clearing. In both cases, N t   d =6 out of a total N d =48 (12 ms blocks, as noted hereinabove). These choices of values lead to a simple, reliable hardware-based detection design, as shown in FIG.  5  and described hereinbelow. It will be appreciated, however, that other choices of the detection parameters are also feasible. Although the example shown in Tables I and II and described in detail herein relates specifically to a VT1.5 line in accordance with applicable ITU standards, those skilled in the art will be able to apply the principles and formulas presented hereinabove to determine suitable parameter values for use with data streams of other types, having different data rates and different BER defect criteria. 
     Returning now to FIG. 1, in order to detect a BER defect condition, an appropriate threshold number M t   d  of errored blocks (or “bad” blocks) is selected, along with a BIP 2  error threshold N t   d  for determining a block to be bad. The bad block threshold and BIP 2  error threshold are preferably chosen in accordance with the criteria described hereinabove, such that M t   d =3 and N t   d =6. A BER detection unit begins to receive successive blocks in a data stream and checks the blocks, at a BER detection step  20 , in order to determine whether the defect detection thresholds are met. (A suitable BER detection unit for this purpose is shown in FIG.  5  and described in detail with reference thereto.) If and when the thresholds are met or exceeded, the detection unit sets a BER defect condition and outputs an indication, such as a BER alarm, that such a condition has been encountered. 
     Once the defect condition is set, the parameters of the detection unit are altered so as to be able to determine when the defect is cleared. Alteration of the parameters includes setting a new threshold number of bad blocks M t   d  and, optionally, a new BIP 2  error threshold N t   d . In the present embodiment, M t   d =0 for defect clearing, while N t   d  remains unchanged at 6. The detection unit receives data blocks and checks the blocks at a clear detection step  30 . When the clear criteria have been met, the unit sets a BER clear condition and cancels the BER alarm. The unit then returns to its initial settings of the bad block and error thresholds and is again prepared to detect defect conditions. 
     FIG. 2 is a flow chart that schematically illustrates details of BER detection step  20 , in accordance with a preferred embodiment of the present invention. Blocks received by the BER detection unit are checked at a block error detection step  40  in order to determine whether the number of actual BIP 2  errors n d  in each of the blocks exceeds the error threshold N t   d . The error result for each block is recorded in a memory, preferably in a shift register having a length equal to M d . The results in the shift register show the number of bad blocks that occurred in a sliding time window having a duration equal to the cumulative duration of M d  successive blocks. In the present embodiment, the shift register is three bits long, and the window duration is 3×12 ms=36 ms. If the number of bad blocks recorded in the shift register at any given time m d  is equal to or greater than the selected threshold value M t   d , the BER defect condition is set. In the present embodiment, wherein M t   d =3, the defect condition is set if all of the three entries in the shift register indicate that the corresponding blocks were bad blocks. Otherwise, the unit continues to receive and check new blocks. 
     FIG. 3 is a flow chart that schematically illustrates details of clear detection step  30 , in accordance with a preferred embodiment of the present invention. Clear detection proceeds in a manner substantially similar to defect detection, as described with reference to FIG. 2, with block errors being detected at step  40  and the results entered in the shift register. In clear detection, however, the number of bad blocks recorded in the shift register is compared to a different threshold value M t   d , and the defect condition is cleared only if m d  is less than the threshold value. In the present embodiment, a clear condition is set only when m d =0, i.e., when no bad blocks are recorded in the shift register. Otherwise, the unit remains in the defect state and continues to receive and check new blocks to determine when a clear state occurs. 
     FIG. 4 is a flow chart that schematically illustrates details of block error detection step  40 , in accordance with a preferred embodiment of the present invention. For each frame received in a given block, a BIP result, preferably a BIP 2  result, is calculated. The calculated result is compared to a reference BIP value for the frame, which was determined before the frame was transmitted and was then sent with the subsequent frame in the data stream, as is known in the art. If there is a discrepancy between the calculated and reference BIP values for a given frame, that frame is counted as bad, and the count of bad frames in the block, n d , is incremented. When the block is finished, n d  is compared to the block error threshold N t   d . If n d ≧N t   d , the block is recorded as a bad block. 
     FIG. 5 is a block diagram that schematically illustrates a BER detection unit  50  that performs the methods described hereinabove, in accordance with a preferred embodiment of the present invention. Unit  50  is preferably implemented as part of an ASIC device for use in a SDH/SONET communications controller, operating under the control of a system clock signal CLK at a preferred clock rate of 6.48 MHz. Various parameters of unit  50  are programmable, so that the unit can be adapted for use with different line types, such as VT1.5, VT2, VT3 and VT6. 
     A BIP 2  error detector  52  calculates the BIP 2  error for each frame and compares the result to a reference BIP 2  value for the frame, so as to generate a BIP 2 BERR output, indicating number of BIP 2  errors in the frame (0, 1 or 2). An accumulator  54  receives the BIP 2  error output and, each time an erroneous frame is noted, increments a total error count for the present block that is maintained in a six-bit accumulator register  56 . A frame clock EN — 2K, preferably with a period of 0.5 ms, equal to the standard VT1.5 frame duration, controls the loading of each new BIP 2 BERR result into the accumulator. 
     An eight-bit integration counter  60  receives frame clock EN — 2K and counts the number of frames received so as to determine when the present block is finished. Preferably, counter  60  counts 24 frames, over 12 ms, to mark off a single block, but the counter may also be programmed for other block sizes, such as 240 frames (120 ms) by means of a mode select input BIP 2 EXER 0 _M. The block size is selected, as described hereinabove, based on system specifications as to how rapidly a defect condition must be detected or cleared, and with what level of certainty. Thus, for a maximum BER of 10 −3 , the block size is set to 24 frames (12 ms detection time), whereas for a 10 −4  maximum BER level, the block size is set to 240 frames (120 ms). Preferably, the same block size is used for both defect detection and defect clearing, unlike BER detection systems known in the art. Count logic  62  receives the count output INTEG_CNT from counter  60  and issues a CNT_TC signal at the end of the block, after the appropriate number of frames have passed (24 or 240 in the present embodiment). 
     The CNT_TC signal is received by an interval register  58 , causing the register to load the accumulated error count from register  56 . The CNT_TC signal is received at the next clock cycle by register  56  and by counter  60 , via respective OR gates  66  and  64 , so that the frame count and error count are initialized for the next block to arrive. A BIP 2 BERR_RST signal can also be applied to reset all elements of unit  50 . 
     For each block, the accumulated number of frame errors BIP 2 ERR_INTG 1  (or n d , in accordance with the notation used hereinabove) is output by register  58  to a threshold comparator  68 . The comparator compares this number to the appropriate threshold N t   d  for detecting a BER defect (BIP 2 BERTD_M) or for clearing a defect (BIP 2 BERTC_M), depending on the state of unit  50 . The values of BIP 2 BERTD_M and BIP 2 BERTC_M are programmable and, in the present embodiment, are both preferably set to the value 6. The output of comparator  68 , SIN, is high when the number of frame errors is greater than or equal to the applicable threshold. This output is recorded in a shift register  70 , preferably a three-bit shift register in the present embodiment. 
     Shift register  70  provides a four-bit output SHR_OUT to decision logic  72 . The logic compares the number of high bits in the shift register to a bad block threshold value (M t   d ), which is set to either a defect detect threshold (BIP 2 BERBLKD_M) or to a defect clear threshold (BIP 2 BERBLKC_M), depending on the state of unit  50 . The thresholds are programmable, wherein for the present embodiment, BIP 2 BERBLKD_M=3 and BIP 2 BERBLKC_M=1, as described hereinabove. Based on the comparison, when a change of state from clear to defective or defective to clear is mandated, logic  72  outputs a SET_BER or CLEAR_BER signal, respectively, to a flip-flop  74 . The SET_BER and CLEAR_BER signals indicate the current BER status to the communications controller, which may take action accordingly. The flip-flop generates a RBIP 2 BER_ST change-of-state output, which causes the threshold values BIP 2 BERTx_M and BIP 2 BERBLKx_M to be reselected for the altered state of unit  50 . 
     Although the preferred embodiment described hereinabove is based on a dedicated hardware device, it will be appreciated that the principles of the present invention may also be implemented in software on a general-purpose processor or using off-shelf hardware devices or in different combinations of dedicated devices, off-shelf components and software. 
     Furthermore, although preferred embodiments are described hereinabove with reference to SDH/SONET networks and standards, those skilled in the art will be able to apply the principles of the present invention in a straightforward manner to other types of synchronous data networks in which error rates need to be monitored. It will thus be appreciated that the preferred embodiments described above are cited by way of example, and the full scope of the invention is limited only by the claims.