Abstract:
Embodiments of apparatuses, articles, methods, and systems for calibrating receive chain to reduce second order intermodulation distortion are disclosed herein. In some embodiments, a reference sensing chain is used to generate reference second-order intermodulation distortion signals that may be used to adjust a calibration code. In some embodiments, a calibration code may be adjusted using one or more feedback loops of a baseband amplifier. The embodiments may be employed, e.g., to manage power in wireless networks. Other embodiments and usages may be described and claimed.

Description:
FIELD 
     Embodiments of the present disclosure relate generally to the field of radio frequency (RF) receivers, and more particularly to, calibrating receive chain to reduce second order intermodulation distortion (IMD2). 
     BACKGROUND 
     A direct conversion RF receiver (DCR) may be used to demodulate an incoming signal by mixing it with a local oscillator (LO) synchronized in frequency to a carrier wave of a wanted signal. A DCR may also be referred to as a zero intermediate frequency (IF) receiver. 
     DCR architectures have been widely adopted due to their high integration levels, low costs on complementary metal oxide semiconductor (CMOS) processes, and flexibility in implementing multi-standard receivers. One of the fundamental difficulties with a DCR is that IMD2 may cause signal quality degradation under strong blocker conditions. 
     High second order linearity may be desired to avoid signal to noise plus distortion ratio (SNDR) degradation by IMD2. For example, a second order intercept point (IP2) of 65 decibels referenced to milliwatt (dBm) or greater may be desired to detect a −82 dBm 54 megabit per second (Mb/s) signal (e.g., a 802.11g signal) in the presence of wireless code division multiple access (WCDMA) blocker. A good RF/analog design alone may not guarantee such a high IP2. This is due to the fact that IP2 depends on not only RF/analog design but also blocker frequency, local oscillator (LO) frequency, power supply voltage, ambient temperature variation, etc. IP2 may ultimately be limited by matching requirements, which may not be met with high yield for IP2 above 35-40 dBm without adjustment. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements. 
         FIG. 1  illustrates a receiver in accordance with various embodiments. 
         FIG. 2  illustrates a mixer in accordance with various embodiments. 
         FIG. 3  illustrates a receiver in accordance with various embodiments. 
         FIG. 4  illustrates a mixer with two cores in accordance with various embodiments. 
         FIG. 5  illustrates a receiver with a two-branch receive chain in accordance with various embodiments. 
         FIG. 6  is a flowchart depicting a calibration operation in accordance with various embodiments. 
         FIG. 7  illustrates a receiver in accordance with various embodiments. 
         FIG. 8  illustrates a platform in accordance with various embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that alternate embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific devices and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that alternate embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments. 
     Further, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. 
     The phrase “in one embodiment” is used repeatedly. The phrase generally does not refer to the same embodiment; however, it may. The terms “comprising,” “having,” and “including” are synonymous, unless the context dictates otherwise. 
     In providing some clarifying context to language that may be used in connection with various embodiments, the phrases “A/B” and “A and/or B” mean (A), (B), or (A and B); and the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). 
     As used herein, reference to an “element” may refer to a hardware, a software, and/or a firmware element employed to obtain a desired outcome. Although only a given number of discrete elements may be illustrated and/or described, such elements may nonetheless be represented by additional elements or fewer elements without departing from the spirit and scope of embodiments of this disclosure. 
       FIG. 1  illustrates a receiver  100  in accordance with various embodiments. The receiver  100  may include an antenna structure  104  having one or more antennas to receive over-the-air RF signals. The received RF signals may be amplified through a low-noise amplifier (LNA)  108  and provided to a mixer  112 . The mixer  112  may mix the received RF signal with an LO signal, having a frequency ω LO  of a carrier wave of a wanted signal, from an LO  116 , to downconvert the RF signal to a zero IF signal. 
     The mixer  112  may provide the downconverted signal to a receive chain  120  of the receiver  100 . The receive chain  120  may include a baseband amplifier  124  to provide a controlled gain to the downconverted signal, an analog-to-digital converter (ADC)  128  to digitize the signal, and a high pass filter (HPF)  132  to filter out unwanted low-frequency portions of the signal. The HPF  132  may output an output signal z n  expressed by:
 
 z   n   =g   1   s   n   +wkq   n   +g   2   q   n   +n   n   EQ. 1
 
     where s n  is the wanted signal, q n  is a Ref IMD2 signal, n n  is noise, g 1  is receiver gain, g 2  includes unintentional IMD2 gain, w is a calibration code, and k is a constant whose sign may be determined with designing the receiver  100 . 
     The IMD2 component, e.g., the g 2 q n , may be the result of second order nonlinearities associated with various circuits in the receiver, e.g., the mixer  112  and/or baseband amplifier  124 , that generate spectral components from blocker signals as direct current (DC) components in-band with the RF signal that is processed through the receive chain  120 . These DC components may cause a DC offset that distorts the wanted signal. Accordingly, various embodiments provide for the measuring of these IMD2 components and providing the calibration code to control an intentional mismatch (e.g., DC offset voltage) provided to the mixer  112 . This will, in turn, improve performance of the receiver  100  in the presence of inter- and intra-platform blocker signals. 
     The mixer  112  may also provide a reference signal to a reference sensing chain  136  of the receiver  100  that may correspond to the IMD2 component. The reference sensing chain  136  may include a low pass filter (LPF)  140  for filtering out unwanted high-frequency portions of the signal, an ADC  144  to digitize the reference signal, and a HPF  148  to filter out unwanted low-frequency portions of the signal. The HPF  148  may output the Ref IMD2 signal q n . 
     Various equalization sections may be employed in the reference sensing chain  136  and/or the receive chain  120  if there is a large difference between transfer functions of the respective chains. 
     The receiver  100  may include a calibrator  152  that may receive the output signal z n  from the receiver chain, the Ref IMD2 signal q n  from the reference sensing chain, and generate the calibration code w, which is fed back to the mixer  112 . 
     When a power of z n  is reduced, the IP2 may be increased. This may be due to q n  being uncorrelated to s n  and g 1  being almost independent of w. A least mean square (LMS) algorithm to provide w is:
 
 w   n+1   =w   n −2μ kz   n   q   n ,  Equation 2
 
     where μ&gt;0 and controls learning speed and algorithm stability. The term z n q n  may be replaced by its short-term average (z n q n +z n+1 q n+1 + . . . +z n+L q n+L )/L to get a more stable result. 
     Equation 1 may utilize a hardware multiplier to correlate z n  and q n . This multiplier may be eliminated by using a sign algorithm such as
 
 w   n+1   =w   n −2μsign( k )sign( q   n ) z   n ,  Equation 3
 
or
 
 w   n+1   =w   n −2μsign( k )sign( q   n )sign( z   n ).  Equation 4
 
     Then the correlation operation may be implemented by using an XOR gate or multiplexer in the calibrator  152 . The correlation result may be substituted by its short-term average. 
       FIG. 2  illustrates a mixer  200  in accordance with various embodiments. The mixer  200  may be similar to and substantially interchangeable with mixer  112  and/or any other mixer described herein. 
     The mixer  200  may include a core  204  and a transconductor  208 . The core  204  may include four transistors, e.g., transistors  212 ,  216 ,  220 , and  224 , coupled to one another as shown. A first differential LO input LO+ may be provided to gates of transistors  212  and  224 , while a second differential LO input LO− may be provided to gates of transistors  216  and  220 . The sources of the transistors  212 ,  216 ,  220 , and  224  may be coupled to the transconductor  208 , while the drains of the transistors may be coupled to the receive chain, e.g., receive chain  120 . 
     The transconductor  208  may have a first branch having a capacitor  228  and a transistor  232  and a second branch having a capacitor  236  and a transistor  240 . The transistors  232  and  240  may be gated by a first differential RF signal RF+ and a second differential RF signal RF− signal, respectively. Sources of the transistors  232  and  240  may be coupled to a ground, while their drains may be coupled to sources of the transistors  212 ,  216 ,  220 , and  224  through capacitors  244  and  248  as shown. 
     In some embodiments, the mixer  200  may be a passive mixer with no DC current flow on the core  204 . As shown in  FIG. 2 , this may be achieved by the capacitors  228  and  236  preventing DC current from flowing to the core  204 . Used in this context, the capacitors  228  and  236  may also be referred to as DC blocking capacitors. In other embodiments, passivity of the mixer  200  may be provided through other arrangements. 
     The Ref IMD2 signal may be taken at a node  244  that is between the core  204  and the transconductor  208 . The node  244  may be bracketed by resistors  248  and  252  to condition the signal. While the node  244  is shown in  FIG. 2  as the point between resistors  248  and  252 , it may also refer to the entire segment connecting the branches of the transconductor  208 . 
     In various embodiments, the Ref IMD2 signal may be taken at alternative locations shown as P 1  and P 2  in  FIG. 2 . However, the Ref IMD2 signal at the node  244  between the core  204  and the capacitors  228  and  236  of the transconductor  208  may be strongly correlated to the IMD2 component of the output signal z n . Furthermore, the level of Ref IMD2 when taken at the point shown may be high, which may facilitate the design of the circuitry of the reference sensing chain  136 . 
     As is generally shown in  FIG. 2 , the LO signal and RF signal provided to the mixer  200  and the mixed signal provided to the receive chain  120 , may be balanced differential signals, while the Ref IMD may be a single ended signal. 
       FIG. 3  illustrates the receiver  100  in additional detail in accordance with various embodiments. As shown, the baseband amplifier  124  may include an operational amplifier  304  with a pair of feedback loops  308  and  312 . The feedback loop  308  may include a capacitor  316  coupled to a resistor  320  in parallel. Similarly, the feedback loop  312  may include a capacitor  324  coupled to a resistor  328  in parallel. The calibrator  152  may include a calibration engine  332  configured to implement a calibration algorithm, and a digital-to-analog converter (DAC)  336  to convert the digital calibration code w to an analog calibration code w that may be used to provide the DC offset to the mixer  112 . In some embodiments, the DC offset may be provided to the mixer  112  by shifting a DC bias on the gates of the transistors of the mixer  112  in a manner that will change the IP2 in the desired direction. 
     While the DC offset is provided to the mixer  112  in  FIGS. 1 and 3 , other embodiments may provide for DC offset at additional/alternative locations. For example, the DC offset may be provided at the baseband level through adjustment of the feedback loops  308  and/or  312 . For another example, the DC offset may be provided through the LO  116 . 
     The mixer  112  is shown with a circuit topology similar to mixer  200  of  FIG. 2 . In this embodiment, the mixer  112  also includes a number of capacitors  334  coupled to respective gate terminals of the core transistors. These capacitors  334  act to couple alternating current (AC) of the LO drive to the mixer  112  to establish a peak-to-peak voltage swing independently from the DC bias gate voltage. 
     The reference sensing chain  136  may have an operational amplifier  340  having feedback loops  344  and  348 , similar to baseband amplifier  124 . The output of the operational amplifier  340  may be coupled to the ADC  144  and provide a voltage V d . The reference sensing chain  136  may also include a DC cancellation loop  352  to cancel the DC component in V d  so that the ADC  144  will not be saturated. The DC cancellation loop may have a low-pass filter  356 , a controller  360 , and a DAC  364 . The output of the DC cancellation loop  352  may provide a biasing voltage V bias  to an input of the operational amplifier  340 . Other embodiments may utilize additional/alternative DC cancellation procedures. 
     The above described embodiments show the receive chain  120  having one branch. In other embodiments, a DCR may include two branches, e.g., an in-phase carrier (I) branch and a quadrature carrier (Q) branch, in order to obtain an orthogonal baseband signal. 
       FIG. 4  illustrates a mixer  400  that may support a receive chain having and I and a Q branch in accordance with various embodiments. Except as otherwise noted, the mixer  400  may be similar to and substantially interchangeable with mixer  112  and/or mixer  200 . 
     The mixer  400  may include an I core  404  and a Q core  408 . Each core may have a number of transistors intercoupled as shown. The I core  404  and the Q core  408  may both be coupled to a transconductor  412 . 
     In some embodiments, the transconductor  412  may be coupled with a positive supply voltage V dd  applied between inductors  416  and  420 . The supply voltage V dd  and inductors  416  and  420  may provide a high impedance and biasing current to the transistors of the transconductor  412 . Other mixers described herein may also include similar mechanisms for providing appropriate impedances/biasing currents. 
       FIG. 5  illustrates a receiver  500  with a receive chain with two branches in accordance with some embodiments. In particular, the receiver  500  may include an I branch  504  and a Q branch  508 . 
     The I branch  504  may include a baseband amplifier  512 , an ADC  516 , and an HPF  520  operating similar to like-named elements described above with reference to the receive chain  120 . Similarly, the Q branch  508  may include a baseband amplifier  524 , an ADC  528 , and an HPF  532 . 
     The receiver  500  may include an I branch calibrator  536  to provide an I branch calibration code w I  to the I core  404  of the mixer  400 . The receiver  500  may also include a Q branch calibrator  540  to provide a Q branch calibration code w Q  to the Q core  408 . While these calibrators are shown as separate elements in  FIG. 5 , they may be combined in a single element that generates and provides both calibration codes. 
     The receiver  500  may include a reference sensing chain  544  coupled to the transconductor  412  of the mixer  400 . The reference sensing chain  544  may have an LPF  548 , an ADC  552 , and an HPF  556  that operate similar to like-named components of reference sensing chain  136  described above. 
     Both the I and the Q branches may be calibrated. In some embodiments, part of the IMD2 current from the I branch may flow into the Q branch and vice versa. This may be due to the passive nature of the mixer  400  and, in particular, to high impedance of the capacitors of the transconductor  412  at the frequency of the IMD2 components. This IMD2 coupling between the I and the Q branches may be represented by the following equations.
 
 z   In   =g   I1   s   In +( k   II   w   I   +k   IQ   w   Q   +g   I     2   ) q   n   +n   In   Equation 5
 
 z   Qn   =g   Q1   s   Qn +( k   QI   w   I   +k   QQ   w   Q   +g   Q     2   ) q   n   +n   Qn   Equation 6
 
     where k II  is a constant providing the slope of the calibration constant for the I chain that is provided by influence of the I branch, k IQ  is a constant providing the slope of the calibration constant for the I chain that is provided by influence of the Q branch, k QI  is a constant providing the slope o the calibration constant for the Q chain that is provided by influence of the I branch, and k QQ  is a constant providing the slope o the calibration constant for the Q chain that is provided by influence of the Q branch. 
     A calibration operation of the I branch  504  and the Q branch  508  may reduce, to an acceptably low value (e.g., an absolute minimum, a relative minimum, etc.), a power of z In  and z Qn , simultaneously, or their total power. 
       FIG. 6  illustrates calibration operations of the calibrators  536  and/or  540  in accordance with some embodiments. At block  604 , the calibrators may set w i  and w q  to initial values. At block  608 , the calibrator  540  may hold w q  constant while calibrator  536  adjusts w i  until an IMD2 component associated with the I branch  504  is reduced to an acceptable level at block  612 . This calibration may be done in accordance with Equations 7, 8, or 9 as follows:
 
 w   I,m,n+1   =w   I,m,n −2μ k   II   z   In   q   n   Equation 7
 
 w   I,m,n+1   =w   I,m,n −2μsign( k   II )sign( q   n ) z   In   Equation 8
 
 w   I,m,n+1   =w   I,m,n −2μsign( k   II )sign( z   In )sign( q   n )  Equation 9
 
     The final w I  of a particular calibration iteration is w I,m . 
     At block  616 , the calibrator  536  may hold w I  constant while the calibrator  540  adjusts w Q  until an IMD2 component associated with the Q branch  508  is reduced to an acceptable level at block  620 . 
     At block  624 , it may be determined whether a convergence event is detected. In some embodiments, a convergence event may be that the IMD2 components of the two branches converge to an acceptably low level. In other embodiments, the convergence event may be a completion of a predetermined number of one or more calibration iterations (a calibration iteration being the operations represented by blocks  608  to  620 ) or some other event associated with an acceptable convergence. 
     If a convergence event is not detected at block  624 , the process may loop back to block  608  for another calibration iteration. If a convergence event is detected at block  624  the calibration process may end at block  628 . When the calibration process ends, the calibration codes may be fixed and the reference sensing chain  544  may be powered down for an extended period of time. 
     It has been shown that the calibration operation described in  FIG. 6  converges given that |k II |&gt;|k IQ | and |k QQ |&gt;|k QI |. 
       FIG. 7  illustrates a receiver  700  in accordance with another embodiment. In this embodiment, a reference sensing chain  704  utilizes elements of first branch of the receiver  700  when calibrating a second branch of the receiver and vice versa. 
     When calibrating an I branch  708 , all of the switches shown may be positioned in the I setting as shown in  FIG. 7 . During this calibration, elements of the Q branch  712 , e.g., an ADC  716  and an HPF  720  may be used for a reference sensing chain with LPF  724 . 
     When calibrating the Q branch  712 , all of the switches may be positioned in the Q setting and the reference sensing chain may incorporate elements of the I branch, e.g., ADC  728  and  732 . 
     When the I branch  708  is being calibrated, a baseband amplifier  736  of the Q branch  712  may be coupled to a dummy load  740 . Conversely, when the Q branch  712  is being calibrated, a baseband amplifier  744  of the I branch  708  may be coupled to the dummy load  740 . 
     Other than these switching aspects, the calibration of the receiver  700  may be similar to the calibration of the receiver  500  with its dedicated receiver sensing chain  544 . 
       FIG. 8  illustrates a platform  800  capable of employing calibration techniques in accordance with various embodiments. The platform  800  may include an antenna structure  804  and an RF front end  808  having a plurality of radios, e.g., radio  812  and radio  816 . 
     The antenna structure  804  may include one or more directional antennas, which radiate or receive primarily in one direction (e.g., for 120 degrees), cooperatively coupled to one another to provide substantially omnidirectional coverage. In other embodiments, the antenna structure  804  may include one or more omnidirectional antennas that radiate or receive equally well in all directions. 
     Each of the radios  812  and  816  may have a transceiver, including a receiver similar to any of the receivers discussed herein, configured to communicate via the antenna structure  804  in a different band and/or with different communication protocols/standards. The communication protocols/standards may be selected from any of the Institute of Electrical and Electronics Engineers (IEEE) wireless standards (e.g., 802.11, 802.16, etc.), mobile digital television (MDTV), ultra-wide band (UWB), wideband-CDMA (WCDMA), Bluetooth, etc. In some embodiments, radios  812  and  816  may operate simultaneously with one another and cause intra-platform interference that may result in the IMD2 as discussed above. 
     The platform may also have a processor  820 , storage  824 , and memory  828  coupled to each other as shown. In some embodiments, one or more of these elements may be coupled to each other through one or more buses (not shown). 
     Memory  828  and storage  824  may include in particular, temporal and persistent copies of calibration logic  832 , respectively. The calibration logic  832  may include instructions that when executed by the processor  820  result in the platform  800  and, in particular, the radio  812  and/or radio  816  performing calibration operations described herein. 
     In various embodiments, the processor  820  may include one or more single-core processors, multiple-core processors, controllers, application-specific integrated circuits (ASICs), etc. 
     In various embodiments, the memory  828  may include RAM, dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), dual-data rate RAM (DDRRAM), etc. 
     In various embodiments, storage  824  may include integrated and/or peripheral storage devices, such as, but not limited to, disks and associated drives (e.g., magnetic, optical), universal serial bus (USB) storage devices and associated ports, flash memory, read-only memory (ROM), non-volatile semiconductor devices, etc. 
     In various embodiments, storage  824  may be a storage resource physically part of the platform  800  or it may be accessible by, but not necessarily a part of, the platform  800 . For example, the storage  824  may be accessed over a network. 
     In various embodiments, the platform  800  may have more or less elements, and/or different architectures. In various embodiments, the platform  800  may be any type of wireless communication device including mobile network client devices such as, but not limited to, a personal computing device, a laptop computing device, a phone, etc., or network infrastructure devices, e.g., a base station, an access point, etc. 
     Although the present disclosure has been described in terms of the above-illustrated embodiments, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. Those with skill in the art will readily appreciate that the present disclosure may be implemented in a very wide variety of embodiments. This description is intended to be regarded as illustrative instead of restrictive on embodiments of the present disclosure.