Abstract:
A metal interconnection of a semiconductor device and a method for forming the same include a diffusion barrier having favorable EM (electro migration) and SM (stress induced migration) properties, thereby preventing voids or other defects in copper interconnections. The diffusion barrier is made of two layers to better match coefficients of thermal expansion at the boundaries between layers, while also providing better adhesion between layers.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0134354 (filed on Dec. 29, 2005), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    As semiconductor devices have trended towards higher speeds and larger scale integration, metal interconnections formed in semiconductor devices have sub-micron feature sizes and a multi-layer structure. As the width of metal interconnections is narrowed, an increased signal delay is generated due to the increased resistance or capacitance of the metal interconnections. Thus, copper interconnections, which have a relatively low resistance, have been used to reduce such signal delay. 
         [0003]    Since copper is not as easily etched as compared with aluminum, for example, a trench is formed to properly shape a copper interconnection. A copper layer is deposited to fill the trench, and then a damascene process including the chemical and mechanical polishing (CMP) is performed, thereby forming the copper interconnection. 
         [0004]    However, a diffusion barrier must be formed between the copper interconnection and an insulating layer due to the propensity of copper to diffuse into other layers. A diffusion barrier should adhere well to both the copper layer and an interlayer dielectric layer. It should also possess excellent EM (electro migration) and SM (stress induced migration) properties. 
         [0005]    However, most diffusion barriers have a shortcoming. The diffusion barriers with good EM properties have poor SM properties, and diffusion barriers having good SM properties have poor EM properties. 
         [0006]    In particular, the SM property may be deteriorated by a difference in the thermal expansion coefficients between the diffusion barrier and the copper or between the diffusion barrier and the insulating layer, and a void may be generated. 
         [0007]    Such a void may interrupt the signal transmission in the copper interconnection, thereby reducing reliability of the device. 
       SUMMARY 
       [0008]    Embodiments relate to a metal interconnection of a semiconductor device and a method for forming the same, in which a diffusion barrier having favorable SM properties and EM properties is formed, thereby preventing a copper interconnection from being disconnected. 
         [0009]    To accomplish the above object of the embodiments, there is provided a metal interconnection in a semiconductor device comprising a semiconductor substrate including an electric conductor. First and second diffusion barriers are formed over the semiconductor substrate. An interlayer dielectric layer may be formed over the second diffusion barrier having a trench exposing the electric conductor. A metal interconnection is formed to fill the trench. The difference in thermal expansion coefficients between the second diffusion barrier and the interlayer dielectric layer is smaller than a difference in thermal expansion coefficients between the first diffusion barrier and the interlayer dielectric layer. 
         [0010]    According to embodiments, a method for forming a metal interconnection of a semiconductor device includes stacking a first diffusion barrier, a second diffusion barrier and an interlayer dielectric layer over a semiconductor substrate having an electric conductor formed therein. A trench is formed by a selective etching process to expose the second diffusion barrier. A metal interconnection is formed to fill the trench. 
         [0011]    The difference in thermal expansion coefficients between the second diffusion barrier and the interlayer dielectric layer is smaller than the difference in thermal expansion coefficients between the first diffusion barrier and the interlayer dielectric layer. 
         [0012]    The first diffusion barrier may include SiN, SiC or SiCN. 
         [0013]    The second diffusion barrier may include SiC or SiON. 
         [0014]    The first diffusion barrier may be two layers; the first layer may be SiN and the second layer may be SiCN. The second diffusion barrier may be made of SiC. 
         [0015]    The electric conductor and the metal interconnection may be made of copper. 
         [0016]    The above and other objects, features and advantages of the embodiments will be apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    Example  FIG. 1  is a cross-sectional view showing a metal interconnection of a semiconductor device according to embodiments. 
           [0018]    Example  FIGS. 2 to 3  are cross-sectional views showing a method for forming a metal interconnection of a semiconductor device according to embodiments. 
           [0019]    Example  FIG. 4  is a cross-sectional view showing a copper interconnection in a semiconductor device according to embodiments. 
           [0020]    Example  FIGS. 5 to 7  are cross-sectional views showing a method for forming a metal interconnection in a semiconductor device according to embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    As shown in  FIG. 1 , a diffusion barrier  106  and an interlayer dielectric layer  108  are sequentially deposited over a substrate  100 . 
         [0022]    The substrate  100  includes individual elements (not shown) or a lower conductor  102 . The lower conductor  102  may be an interconnection formed of a copper or the like, having a relatively low resistance. 
         [0023]    The diffusion barrier  106  includes a first diffusion barrier  104   a  and a second diffusion barrier  104   b , which differ from each other in their characteristics. The first diffusion barrier  104   a  may be formed of any one of SiN, SiC or SiCN, and the second diffusion barrier  104   b  may be formed of SiC or SiON. 
         [0024]    The first diffusion barrier  104   a  may be made of a material having a high adhesion with the lower conductor  10  since it directly abuts against the lower conductor  102 . The second diffusion barrier  104   b  may be made of a material having a low thermal expansion coefficient with respect to the lower conductor  102  although it has a lower adhesion as compared to the first diffusion barrier  104   a.    
         [0025]    In this regard, the diffusion barrier  106  may be formed of SiN/SiC, SiCN/SiC, or SiC/SiON. The first diffusion barrier  104   a  may also be formed in a double layer structure, with the second diffusion barrier  104   b  in a single layer structure, thereby forming a diffusion barrier with a triple layer structure. For example, the diffusion barrier  106  may be formed of SiN/SiCN/SiC. The SiCN has an intermediate physical property between SiC and SiN, and may function as a buffer between them. 
         [0026]    The interlayer dielectric layer  108  may be an organic insulator, an inorganic insulator, or the like, such as FSG (fluorine silicate glass), USG (un-doped silicate glass), or SiH4, TEOS (tetra ethyl ortho silicate) deposited in a single layer or multiple layers. The interlayer dielectric layer  108  may be formed using materials having low dielectric constant of ≦3.0 such as BD (black diamond), Silica xerogels, mesoporous silica, polyimide nanofoams, Teflon-AF, Teflon microemulsion, or the like. 
         [0027]    The interlayer dielectric layer  108  and the diffusion barrier  106  include a trench (T) formed therein, exposing the lower conductor  102  or individual elements. 
         [0028]    The trench (T) includes a barrier metal  110  and a metal interconnection  112 , to which the lower conductor  102  or individual elements are electrically connected. The thin barrier metal  110  is formed along the inner surface of the trench (T), and the metal interconnection  110  fills the trench defined by the inner surface of barrier metal  110 . 
         [0029]    The barrier metal  110  functions to prevent metal interconnection  112  from diffusing into other layers such as the interlayer dielectric layer  108 . The barrier metal  110  also improves the adhesion between the metal interconnection  112  and the interlayer dielectric layer  108 . 
         [0030]    The barrier metal may be made of a material such as TaN, Ta, TiN, TaSiN, TiSiN, etc., and may be formed in a single layer or multiple layers. The metal interconnection  112  is made of a conductive material, for example copper, having a relatively low resistance. 
         [0031]    Example  FIGS. 2 to 3  are cross-sectional views showing a method for forming a metal interconnection of a semiconductor device according to embodiments. 
         [0032]    As shown in  FIG. 2 , a diffusion barrier  106  including the first and second diffusion barriers  104   a ,  104   b  is formed over substrate  100 . 
         [0033]    The first diffusion barrier  104   a  may be formed of SiN, SiC, SiCN or the like, and the second diffusion barrier  104   b  may be formed of SiC or SiON. 
         [0034]    The SiN may be formed by the reaction of SiH4 gas and NH3 gas. The SiON may be formed by the reaction of SiH4 gas, CO gas and O2 gas, and the SiCN may be formed by the reaction of SiH4 gas, NH3 gas, and CH4 gas. 
         [0035]    If the first diffusion barrier  104   a  is formed by SiN, it may have a thickness about 100˜300 Å. If the first diffusion barrier  104   a  is formed by SiC, it may have a thickness about 300˜700 Å. The second diffusion barrier  104   b  may be formed with a thickness of about 500˜1,000 Å. 
         [0036]    As shown in  FIG. 3 , the interlayer dielectric layer  108  is formed by depositing an insulating material over the diffusion barrier  106 . The interlayer dielectric layer  108  may be etched by a selective etching process, forming trench (T) exposing the diffusion barrier  106 . 
         [0037]    As shown in  FIG. 1 , a first metal layer is formed by depositing a metal over the substrate  100  including the trench (T). Then, a second metal layer is formed by depositing copper, filling the trench. 
         [0038]    The chemical and mechanical polishing (CMP) is used to flatten or planarize the substrate  100 , thereby forming the barrier metal  100  and the metal interconnection  112  into a shape similar to that shown in  FIG. 1 . 
         [0039]      FIG. 4  is a cross-sectional view showing a copper interconnection of a semiconductor according to different embodiments. 
         [0040]    As shown in  FIG. 4 , a diffusion barrier  106  and an interlayer dielectric layer  108  are sequentially deposited over a substrate  100 . 
         [0041]    The substrate  200  includes individual elements (not shown) and a lower conductor  102 . The lower conductor  102  may be an interconnection formed of copper, for example, having a relatively low resistance. 
         [0042]    The diffusion barrier  106  includes a first diffusion barrier  104   a  and a second diffusion barrier  104   b , which differ from each other in their characteristics. The first diffusion barrier  104   a  may be formed of any one of SiN, SiC or SiCN, and the second diffusion barrier  104   b  may be formed of SiC or SiON. 
         [0043]    The first diffusion barrier  104   a  may be made of a material having a high adhesion with the lower conductor  10  since it directly abuts against the lower conductor  102 . The second diffusion barrier  104   b  may be made of a material having a low thermal expansion coefficient with respect to the lower conductor  102  although it has a lower adhesion as compared to the first diffusion barrier  104   a.    
         [0044]    In this regard, the diffusion barrier  106  may be formed of SiN/SiC, SiCN/SiC, or SiC/SiON. The first diffusion barrier  104   a  may also be formed in a double layer structure, with the second diffusion barrier  104   b  in a single layer structure, thereby forming a diffusion barrier with a triple layer structure. For example, the diffusion barrier  106  may be formed of SiN/SiCN/SiC. The SiCN has an intermediate physical property between SiC and SiN, and may function as a buffer between them. 
         [0045]    The interlayer dielectric layer  108  may be an organic insulator, an inorganic insulator, or the like, such as FSG (fluorine silicate glass), USG (un-doped silicate glass), or SiH4, TEOS (tetra ethyl ortho silicate) deposited in a single layer or multiple layers. The interlayer dielectric layer  108  may be formed using materials having low dielectric constant of ≦3.0 such as BD (black diamond), Silica xerogels, mesoporous silica, polyimide nanofoams, Teflon-AF, Teflon microemulsion, or the like. 
         [0046]    The interlayer dielectric layer  108  and the diffusion barrier  106  include a via (V) formed therein for exposing the lower conductor  102  or individual elements. The interlayer dielectric layer  108  includes a trench (T) formed therein for exposing the via (V). 
         [0047]    The via (V) and the trench (T) include a barrier metal  110  and a metal interconnection  112 , to which the lower conductor  102  or individual elements are electrically connected. The thin barrier metal  110  is formed along the inner surfaces of the via (V) and the trench (T), and the metal interconnection  110  fills the via and trench defined by the inner surface of barrier metal  110 . 
         [0048]    The barrier metal  110  functions to prevent metal interconnection  112  from diffusing into other layers such as the interlayer dielectric layer  108 . The barrier metal  110  also improves the adhesion between the metal interconnection  112  and the interlayer dielectric layer  108 . 
         [0049]    The barrier metal may be made of a material such as TaN, Ta, TiN, TaSiN, TiSiN, etc., and may be formed in a single layer or multiple layers. The metal interconnection  112  is made of a conductive material, for example copper, having a relatively low resistance. 
         [0050]    Hereinafter, a method for forming a metal interconnection of such semiconductor described above will be described in detail with reference to  FIGS. 5 to 7 . 
         [0051]    Example  FIGS. 5 to 7  are cross-sectional views showing a method for forming a metal interconnection in a semiconductor device according to embodiments. 
         [0052]    As shown in  FIG. 5 , a diffusion barrier  106  including the first and second diffusion barriers  104   a ,  104   b  is formed over substrate  100 . 
         [0053]    The first diffusion barrier  104   a  may be formed of SiN, SiC, SiCN or the like, and the second diffusion barrier  104   b  may be formed of SiC or SiON. 
         [0054]    The SiN may be formed by the reaction of SiH4 gas and NH3 gas. The SiON may be formed by the reaction of SiH4 gas, CO gas and O2 gas, and the SiCN may be formed by the reaction of SiH4 gas, NH3 gas, and CH4 gas. 
         [0055]    If the first diffusion barrier  104   a  is formed by SiN, it may have a thickness about 100˜300 Å. If the first diffusion barrier  104   a  is formed by SiC, it may have a thickness about 300˜700 Å. The second diffusion barrier  104   b  may be formed with a thickness of about 500˜1,000 Å. 
         [0056]    As shown in  FIG. 6 , the interlayer dielectric layer  108  is formed by depositing an insulating material over the diffusion barrier  106 . The interlayer dielectric layer  108  is etched by a selective etching process, forming the via (V) exposing the diffusion barrier  106 . The diffusion layer  106  may be used as an etch stop layer while forming the via (V). 
         [0057]    As shown in  FIG. 7 , the trench (T) for exposing the via (V) is formed in the interlayer dielectric layer  108  using a selective etching process. If the interlayer dielectric layer  108  is formed in multiple layers, any one layer of the interlayer dielectric layer  108  may be used as an etching stop layer for forming the trench (T). 
         [0058]    As shown in  FIG. 4 , a first metal layer is formed by depositing a metal over the substrate  100  including the via (V) and the trench (T). A second metal layer is formed by depositing a copper layer, filling the via and the trench. 
         [0059]    A CMP process flattens the substrate  100 , thereby finishing barrier metal  100  and metal interconnection  112 . 
         [0060]    As described above, in accordance with embodiments, a layer having excellent adhesion and a layer having a small difference in thermal expansion coefficients with other layers are formed together as a diffusion barrier. This prevents metal diffusion from the metal interconnection, and improves the reliability of an interconnection without causing a void. 
         [0061]    The diffusion barriers having different characteristics can be easily formed without separate additional processes, but rather by changing gases forming the diffusion barrier. 
         [0062]    It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.