Abstract:
Systems for controlling pixels are provided. A representative system comprises a scan driver comprises: a data signal line operative to provide data to the pixel; and a scan driver operative to control illumination of the pixel during sequential time periods such that, if data provided by the data signal line is different between a first time period and a second time period, brightness of the pixel differs during a third time period and a sequential fourth time period. The pixel is illuminated during the third time period and the fourth time period.

Description:
BACKGROUND 
     The disclosure relates to display devices. 
     Electroluminescence (EL) display devices include organic light emitting diode (OLED) displays and polymeric light emitting diode (PLED) displays. In accordance with associated driving methods, an OLED can be an active matrix type or a positive matrix type. An active matrix OLED (AM-OLED) display typically is thin and exhibits lightweight characteristics, spontaneous luminescence with high luminance efficiency and low driving voltage. Additionally, an AM-OLED display provides the perceived advantages of increased viewing angle, high contrast, high-response speed, full color and flexibility. 
     An AM-OLED display is driven by electric current. Specifically, each of the matrix-array pixel areas of an AM-OLED display includes at least one thin film transistor (TFT), serving as a driving TFT, to modulate the driving current. Driving current is modulated based on the variation of capacitor storage potential to control the brightness and gray level of the pixel areas. 
     The gray level is selected by using a voltage divider comprising resistors.  FIG. 1   a  is a schematic diagram of a conventional voltage divider. The voltage divider  10  comprises resistors serially connected between a high voltage source (Vcc) and a low voltage source (Gnd). Each point between two resistors has a corresponding voltage indicating a particular gray level. 
     A point  110  of voltage divider  10  can provide a maximum gray level indicating a maximum brightness of the AM-OLED. Since a voltage divider only provides one maximum gray level, if a user desires to adjust the maximum brightness of the AM-OLED higher, the AM-OLED requires several voltage dividers. 
       FIG. 1   b  is a schematic diagram of another conventional voltage divider. A voltage between two resistors can be adjusted according to the resistance of two resistors. In this case, a first maximum gray level provided by voltage divider  10  is 100 nits, a second maximum gray level provided by voltage divider  12  is 150 nits, and a third maximum gray level provided by voltage divider  14  is 200 nits. Therefore, the brightness of the AM-OLED can be adjusted by providing different maximum gray levels; however, the cost and volume of the AM-OLED are increased. 
     SUMMARY 
     Systems for controlling pixels are provided. An exemplary embodiment of such a system comprises a scan driver comprising: a first shift-register unit operative to output a first shift signal according to a first start signal; a second shift-register unit operative to output a second shift signal according to the first shift signal for lighting the first pixel; a third shift-register unit operative to output a third shift signal according to the second shift signal; and a first processor operative to control the first pixel to receive the first data signal according to the first, the second, and the third shift signals. A duty cycle of the first start signal determines a light-emitting duration of the first pixel. 
     Another embodiment of a system for controlling a pixel comprises: a data signal line operative to provide data to the pixel; and a scan driver operative to control illumination of the pixel during sequential time periods such that, if data provided by the data signal line is different between a first time period and a second time period, brightness of the pixel differs during a third time period and a sequential fourth time period. The pixel is illuminated during the third time period and the fourth time period. 
     Another embodiment of a system for controlling a pixel comprises a display device. The display device comprises a display panel comprising a first pixel; an EL driver operative to output a start signal; a data driver operative to output a first data signal to the first pixel; and a scan driver operative to output a first scan signal and a second scan signal to the first pixel. The first pixel is operative to receive the first data signal according to the first scan signal and the first pixel is illuminated according to the second scan signal. The scan driver comprises: a first shift-register unit operative to output a first shift signal according to the first start signal; a second shift-register unit operative to output a second shift signal according to the first shift signal for lighting the first pixel; a third shift-register unit operative to output a third shift signal according to the second shift signal; and a first processor operative to control the first pixel to receive the first data signal according to the first, the second, and the third shift signals. A duty cycle of the first start signal establishes a light-emitting duration of the first pixel. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with reference made to the accompanying drawings, wherein: 
         FIG. 1   a  is a schematic diagram of a conventional voltage divider; 
         FIG. 1   b  is a schematic diagram of another conventional voltage divider; 
         FIG. 2   a  is a schematic diagram of an embodiment of a system for controlling pixels; 
         FIG. 2   b  is a schematic diagram of an embodiment of a display device used in the system of  FIG. 2   a;    
         FIG. 3  is a schematic diagram of an embodiment of a scan driver; 
         FIG. 4  is a timing diagram of the scan driver of  FIG. 3 ; 
         FIG. 5  is a schematic diagram of another embodiment of a scan driver; 
         FIG. 6  is a schematic diagram of another embodiment of a scan driver. 
     
    
    
     DETAILED DESCRIPTION 
     Systems for controlling pixels are provided. As will be described with reference to several exemplary embodiments, brightness of the pixels of a display can be adjusted, such as by increasing the light-emitting duration of the pixels. In this regard,  FIG. 2   a  is a schematic diagram of an embodiment of a system for controlling pixels that is implemented as an electronic device. Note that such an electronic device can be provided in various configurations, such as a PDA, a display monitor, a notebook computer, a tablet computer, or a cellular phone. Electronic device  2  comprises a display device  20  and a digital-to-analog converter (DAC)  25 . DAC  25  supplies power to display device  20 . 
       FIG. 2   b  is a schematic diagram of an embodiment of display device  20 . As shown in  FIG. 2   b , display device  20  comprises a display panel  21  comprising pixels P 11 ˜P mn , a data driver  22 , a scan driver  23 , and an electroluminescence (EL) driver  24 , which can be implemented by an integrated circuit (IC). 
     Data driver  22  provides data signals D 1 ˜D m  to pixels P 11 ˜P mn . Scan driver  23  receives a start signal (STV) output from EL driver  24  and controls pixels P 11 ˜P mn  by scan signals S 1 ˜S n  and XS 1 ˜XS n . Pixels P 11 ˜P mn  receive data signals D 1 ˜D m  according to scan signals S 1 ˜S n  and pixels P 11 ˜P mn  are illuminated according to scan signals XS 1 ˜XS n . 
       FIG. 3  is a schematic diagram of an embodiment of a scan driver. For clarity, only two pixels of the display are shown. The structures of the pixels shown in  FIG. 3  are given as an example; however, in other embodiments, other configurations can be used. 
     Scan driver  23  comprises a shift register circuit  33  and processors  34 ˜ 37 . Shift register circuit  33  comprises shift register units VSR 1 ˜VSR 4 . Each shift register unit outputs a shift signal according to a duty cycle of start signal STV. 
     Processor  34  comprises logic units  341  and  342 . A first input terminal of logic unit  341  is floating and a second input terminal of logic unit  341  receives shift signal SS 1 . A first input terminal of logic unit  342  is coupled to an output terminal of logic unit  341  and a second input terminal of logic unit  342  receives shift signal SS 2 . Since the first input terminal of logic unit  341  is floating, an output terminal of logic unit  342  does not control a pixel. Processor  35  comprises logic units  351  and  352 . Logic unit  351  receives shift signals SS 1  and SS 2 . Logic unit  352  receives an output signal of logic unit  351  and shift signal SS 3  to generate scan signal SD 1 . Pixel  31  receives data signal DS according to scan signal SD 1 . Shift signal SS 2  also corresponds to scan signals XSD 1 . Pixel  31  is illuminated according to scan signal XSD 1 . 
     Processor  36  comprises logic units  361  and  362 . Logic unit  361  receives shift signals SS 2  and SS 3 . Logic unit  362  receives an output signal of logic unit  361  and shift signal SS 4  to generate scan signal SD 2 . Pixel  32  receives data signal DS according to scan signal SD 2 . Shift signal SS 3  corresponds to scan signals XSD 2 . Pixel  32  is illuminated according to scan signal XSD 2 . 
     Processor  37  comprises logic units  371  and  372 . Logic unit  371  receives shift signals SS 3  and SS 4 . A first input terminal of logic unit  372  receives an output signal of logic unit  371  and a second input terminal of logic unit  372  is floating. Since the second input terminal of logic unit  372  is floating, an output terminal of logic unit  372  does not control a pixel. 
     In this embodiment, logic units  341 ,  351 ,  361 , and  371  are XOR gates and logic units  342 ,  352 ,  362 , and  372  are AND gates. 
       FIG. 4  is a timing diagram of the embodiment of the scan driver depicted in  FIG. 3 . In  FIG. 3 , shift register units VSR 1 ˜VSR 4 , respectively, output shift signals SS 1 ˜SS 4  responsive to shift register unit VSR 1  receiving start signal STV. 
     Pixel  31  receives data signal DS according to shift signals SS 1 ˜SS 3  received by processor  35 . As shown in  FIG. 4 , a logic level of shift signal SS 1  is low and those of shift signals SS 2  and SS 3  are high such that a logic level of scan signal SD 1  is high in period P 1 . 
     Therefore, transistor  311  can be turned on. A data signal is transmitted to capacitor  312  through transistor  311  to charge capacitor  312 . Transistor  313  is turned on for outputting driving current I 1  as a voltage of capacitor  312  reaches a first preset value. Since a logic level of scan signal XSD 1  is high, transistor  314  is turned on in period P 1 . Light-emitting element  315  is illuminated as driving current I 1  is transmitted to light-emitting element  315  by transistor  314 . 
     In period P 2 , the logic level of scan signal XSD 1  is low such that light-emitting element  315  is extinguished. Since the logic level of scan signal SD 2  is high, capacitor  322  is charged such that driving current I 2  is provided by transistor  323 . Light-emitting element  325  receives driving current I 2  and is illuminated as the logic level of scan signal SD 2  is high. 
     In period P 3 , the logic level of scan signal XSD 2  is low such that light-emitting element  325  is extinguished. In period P 4 , the logic level of scan signal XSD 1  is high such that transistor  314  is turned on. Since the voltage of capacitor  312  maintains the first preset value, transistor  313  generates driving current I 1 , which is provided to light-emitting element  315  for illustrating that element. 
     In period P 5 , since the logic level of scan signal SD 1  is high, capacitor  312  is again charged according to data signal DS such that the voltage of capacitor  312  reaches a second preset value. Transistor  313  generates new driving current I 1  according to the new voltage of capacitor  312 . Since the logic level of scan signal XSD 1  is also high, light-emitting element  315  is illuminated. 
     In period P 4 , the voltage of capacitor  312  depends on the data signal DS received by transistor  311  in period P 1 . In period P 5 , the voltage of capacitor  312  depends on the data signal DS received by transistor  311  in period P 5 . Although light-emitting element  315  is illuminated in periods P 4  and P 5 , if data signal DS in period P 1  is different than the data signal DS in period P 5 , the brightness of light-emitting element  315  in period P 4  differs from the brightness of light-emitting element  315  in period P 5 . 
     In period P 6 , the logic level of scan signal XSD 2  is high such that transistor  324  is turned on. Since the voltage of capacitor  322  can turn on transistor  323 , light-emitting element  325  receives driving current I 2  and is illuminated. 
     In period P 7 ; since the logic level of scan signal SD 2  is high, capacitor  322  is again charged according to data signal DS. Transistor  323  outputs new driving current I 2  according to the voltage of capacitor  322 . Since the logic level of scan signal XSD 2  is also high, light-emitting element  325  is illuminated. 
     The voltage of capacitor  322  in period P 6  depends on the data signal DS received by transistor  321  in period P 2 . The voltage of capacitor  322  in period P 7  depends on the data signal DS received by transistor  321  in period P 7 . Although light-emitting element  325  is illuminated in periods P 6  and P 7 , if data signal DS in period P 2  is different than the data signal DS in period P 7 , the brightness of light-emitting element  325  in period P 6  is different from the brightness of light-emitting element  325  in period P 7 . 
     Taking pixel  31  as an example, since start signal STV only has a cycle in period P 8 , the light-emitting state of light-emitting element  315  is luminous-dark-luminous in periods P 1 ˜P 4 . If transistor  314  is replaced by a PMOS transistor or the start signal cycle is inverted, the light-emitting state of light-emitting element  315  is changed to dark-luminous-dark in periods P 1 ˜P 4 . The light-emitting state of light-emitting element  315  is luminous-dark-luminous-dark-luminous as start signal STV has two cycles in period P 8 . 
     Duration of each light-emitting state depends on the duty cycle of start signal STV. Assume a display panel requires 16.63 ms to display an image and the light-emitting states of all light-emitting elements in the display panel are luminous-dark-luminous. Then, if the duration of the luminous state is 16.63 ms, the brightness of the display panel is 100%, if the duration of the luminous state is 13.304 ms, the brightness of the display panel is 80%. If the duration of the luminous state is 8.315 ms, the brightness of the display panel is 50%. 
     For example, assume light-emitting element  315  is illuminated during periods P 1 , P 4 , and P 5  according to scan signal XSD 1 . If the light-emitting duration (the duration of periods P 1 , P 4 , and P 5 ) of light-emitting element  315  is 13.304 ms, the brightness of the display panel is 50%. Therefore, the duty cycle of start signal STV controls the light-emitting duration of light-emitting element and thus controls the brightness of the display panel. Because of this, a user can adjust the brightness of the display panel according to actual requirements for reducing power consumption. 
       FIG. 5  is a schematic diagram of another embodiment of a scan driver. Each of the logic units  342 ,  352 ,  362 , and  372  further receives a vertical output enable signal ENBV. Each of the buffers  371 ˜ 374  has an amplification function. Buffer  371  amplifies scan signal SD 1  for turning on transistor  311 . Buffer  372  amplifies scan signal XSD 1  for turning on transistor  314 . Buffer  373  amplifies scan signal SD 2  for turning on transistor  321 . Buffer  374  amplifies scan signal XSD 1  for turning on transistor  321 . 
       FIG. 6  is a schematic diagram of another embodiment of a scan driver. Each pixel comprises three sub-pixels for displaying red, green and blue, respectively. For clarity,  FIG. 6  only shows a pixel comprising sub-pixels  61 ˜ 63  respectively displaying red, green and blue. 
     Each shift register unit VSR 1B ˜VSR 3B  provides a shift signal as shift register unit VSR 1B  receives start signal STV B . Processor  64  receives shift signals provided by shift register units VSR 1B ˜VSR 3B  for generating scan signal SD 1 . Sub-pixels  61 ˜ 63  respectively receive data signals DS R , DS G  and DS B  according to scan signal SD 1 . A shift signal provided by shift register unit VSR 2B  is scan signal XSD 1B . Sub-pixel  63  is illuminated according to scan signal XSD 1B . 
     When shift register unit VSR 1R  receives start signal STV R , a shift signal provided by shift register unit VSR 2R  is used as scan signal XSD 1R . Sub-pixel  61  is illuminated according to scan signal XSD 1R . 
     When shift register unit VSR 1G  receives start signal STV G , a shift signal provided by shift register unit VSR 2G  is used as scan signal XSD 1G . Sub-pixels  62  is illuminated according to scan signal XSD 1G . 
     The light-emitting duration of sub-pixels  61 ˜ 63  are respectively controlled by duty cycles of start signals STV R , STV G  and STV G . 
     In summary, the light-emitting duration of the pixels of a display can be controlled by the duty cycle of start signal STV. The brightness of the display panel is brighter as the light-emitting duration of the pixels is longer, and vice versa. Therefore, a user can adjust the brightness of the display panel according to actual requirements. 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.