Abstract:
A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Description:
TECHNICAL FIELD 
   The described embodiments relate to clock input filters. 
   BACKGROUND INFORMATION 
     FIGS. 1-4  (Prior Art) illustrate various examples of prior art clock input filter circuits. The circuit of  FIG. 1  (see U.S. Pat. No. 5,650,739 for further details) involves analog circuitry including a pair of comparators. This circuit is fairly large when realized in integrated circuit form, consumes a substantial amount of static power, and involves an external threshold voltage generator. The circuit of  FIG. 2  (see U.S. Pat. No. 6,507,221 for further details) involves a pair of delay circuits and digital Schmitt triggers rather than the delay circuits and analog comparators of  FIG. 1 , but the circuit of  FIG. 2  involves an intercoupling between the outputs of the Schmitt triggers and the delay circuit supplying the other Schmitt trigger. The circuit of  FIG. 3  (see U.S. Pat. No. 6,535,057 for further details) has only a single programmable delay line that supplies the input signals to the AND and BAND gates. Similarly, the circuit of  FIG. 4  (see U.S. Pat. No. 6,535,057 for further details) involves only a single delay circuit DELBUF. None of the circuits of  FIGS. 1-4  is readily programmable to adjust the duty cycle of the output signal. A more versatile and processor-configurable clock input filter circuit having low static power consumption and having a duty cycle adjust capability is desired. 
   SUMMARY 
   A clock input filter uses a first programmable low-pass delay element to low-pass filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to low-pass filter during a high period of the input clock signal and to output a RESET signal. A latch is set by the SET signal. The latch is reset by the RESET signal. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of filtered and duty cycle adjusted versions of the input signal. One of the filtered and duty cycle adjusted versions of the input signal has a duty cycle that is greater than the duty cycle of the input signal. The other of the filtered and duty cycle adjusted versions of the input signal has a duty cycle that is smaller than the duty cycle of the input signal. The clock input filter includes output multiplexing circuitry that outputs either the filtered output of the latch, or the filtered and increased duty cycle version of the input signal, or the filtered and decreased duty cycle version of the input signal, or an unfiltered version of the input signal. 
   In one embodiment, the SET signal is a signal output by a first logic gate. A first input lead of the first logic gate is coupled to receive a buffered or inverted version of the input clock signal. The buffered or inverted version of the input clock signal is referred to as the first signal. The first signal is supplied onto an input lead of the first programmable low-pass delay element such that the first programmable low-pass delay element outputs a filtered and delayed version of the first signal onto the second input lead of the first logic gate. The first programmable low-pass delay element includes a first RC network, the RC time constant of which is controllable by a processor. 
   Similarly, the RESET signal is a signal output by a second logic gate. A first input lead of the first logic gate is coupled to receive the first signal. The first signal is supplied onto an input lead of the second programmable low-pass delay element such that the second programmable low-pass delay element outputs a filtered and delayed version of the first signal onto the second input lead of the second logic gate. The second programmable low-pass delay element includes a second RC network, the RC time constant of which is controllable by the processor. In one embodiment, the clock input filter performs its filtering and duty cycle adjusting functions without using any analog differential comparators. The clock input filter performs a glitch filtering function in the sense that the signal output from the clock input filter has the same number of clock edges as the input signal would have had had the input signal had no glitches. The first and second programmable low-pass delay elements consume some switching power, but consume substantially no static power. In this embodiment, the duty cycle of the signal output from the clock input filter (in a glitch free condition) varies no more than twenty percent over standard process, temperature and voltage ranges. 
   Further details and embodiments are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, where like numerals indicate like components, illustrate embodiments of the invention. 
       FIGS. 1-4  (Prior Art) are diagrams of various prior art clock filter circuits. 
       FIG. 5  is a circuit diagram of a novel clock input filter circuit within a microcontroller integrated circuit. 
       FIG. 6  is a simplified waveform diagram that illustrates how the clock input filter circuit of  FIG. 5  filters an input signal IN, generates a filtered version of the input signal that has an increased duty cycle, and that generates a filtered version of the input signal that has a decreased duty cycle. 
       FIGS. 7 and 8  are tables that set forth the decoding performed by the decoders of the circuit of  FIG. 5 . 
       FIG. 9  is a simplified waveform diagram that illustrates an operation of low-pass delay element  15  of  FIG. 5 . The waveforms of  FIGS. 6 and 9  and the associated description is simplified. More accurate circuit operation can be observed by simulating the circuit of  FIG. 5  using SPICE or another similar circuit simulation program using models appropriate for the particular semiconductor process employed to realize the circuit. Component values and sizes can be adjusted to customize timing and circuit operation for a particular application. 
       FIG. 10  is a simplified waveform diagram that illustrates how low-pass delay element  15  performs a glitch filtering function. 
       FIG. 11  is a flowchart of a method in accordance with one novel method. 
   

   DETAILED DESCRIPTION 
     FIG. 5  is a diagram of a microcontroller integrated circuit  1  in accordance with one novel aspect. Microcontroller integrated circuit  1  includes a novel clock input filter circuit  2 , a digital processor  3 , a crystal oscillator circuit  4 , a clock multiplexer circuit  5 , and two terminals  6  and  7 . Other parts of the microcontroller integrated circuit are not illustrated. An external crystal  8  is coupled to the crystal oscillator circuit  4  via the two terminals  6  and  7 . Processor  3  is coupled to and controls the clock input filter circuit  2  via the local bus  9  of the microcontroller. Oscillator circuit  4  outputs a clock signal IN onto the input lead  10  of the clock input filter circuit  2 . The clock input filter circuit  2  conditions and filters the signal IN and outputs the resulting signal OUT onto the output lead  11  of the clock input filter circuit  2 . The signal OUT is multiplexed through clock multiplexer circuit  5  and is supplied as the signal CLK onto the clock input lead  12  of processor  3 . Although not illustrated in  FIG. 1 , the clock multiplexer circuit  5  can multiplex a selected one of several other clock signals (for example, an output of an internal precision oscillator or an output of a low-power internal watchdog timer oscillator) onto the clock input lead  12  of processor  3 . For further information on clock multiplexer circuit  5 , see U.S. patent application Ser. No. 10/764,391, entitled “Clock Controller With Clock Source Fail-Safe Logic”, filed Jan. 23, 2004, by Richmond et al. (the subject matter of which is incorporated herein by reference). 
   Operation of clock input filter circuit  2  is described in further detail in connection with the simplified waveform diagram of  FIG. 6 . For simplicity of illustration, the waveforms are illustrated in idealized fashion having straight edges. The waveform labeled IN represents the signal IN on input lead  10  of clock input filter circuit  2 . Input lead  10  is referred to here as node N 1 . In this example, configuration signal T 0  is a digital logic high. NAND gate  13  therefore inverts the signal IN and supplies an inverted version of the signal IN onto node N 2 . The signal on node N 2  is referred to here as the first signal. The waveform labeled N 2  in  FIG. 6  represents the first signal on node N 2 . The first signal is supplied directly onto the upper input lead of NAND gate  14 . A first low-pass delay element  15  receives the first signal on node N 2  and outputs a delayed and filtered version of the first signal onto the lower input lead NAND gate  14 . The lower input lead is node N 3  in  FIG. 5 . The waveform labeled N 3  in  FIG. 6  represents the delayed and filtered version of the first signal on node N 3 . NAND gate  14  outputs a digital logic low signal if the signals on both its upper and lower input leads are digital logic high levels. The waveform labeled N 5  in  FIG. 6  represents the signal output by NAND gate  14 . The signal on node N 5  therefore pulses low during the time labeled as “SET” in the waveform of  FIG. 6 . 
   In similar fashion, the first signal on node N 2  is supplied directly onto the lower input lead of NOR gate  16 . A second low-pass delay element  17  receives the first signal and supplies a delayed and filtered version of the first signal onto the upper input lead of NOR gate  16 . The upper input lead of NOR gate  16  is node N 4  in  FIG. 5 . The waveform labeled N 4  in  FIG. 6  represents the delayed and filtered version of the first signal that is output by second low-pass delay element  17 . NOR gate  16  outputs a digital logic high signal if the signals on both its upper and lower input leads are digital logic low levels. The signal output from NOR gate  16  is inverted by inverter  18 . The signal on node N 6 A is therefore a digital logic low if the signals on both input leads of NOR gate  16  are digital logic low levels. NOR gate  16  and inverter  18  may be considered together to be a single OR gate. The signal output by this OR gate onto node N 6 A is represented by the waveform labeled N 6 A in  FIG. 6 . The signal on node N 6 A pulses low during the time labeled “RESET” in the waveform of  FIG. 6 . 
   Node N 5  is the active low SET input (level sensitive) of a sequential logic element  19 . Node N 6 A is the active low RESET input (level sensitive) of sequential logic element  19 . Sequential logic element  19  in this example is an SR-latch involving a pair of cross-coupled NAND gates  20  and  21 . The “S” in  FIG. 5  designates the SET input of the latch. The “R” in  FIG. 6  designates the RESET input of the latch. 
   Sequential logic element  19  supplies the signal SROUT onto node N 7 . The waveform labeled N 7  in  FIG. 6  represents the signal SROUT. When the latch is in the “set” state then latch asserts SROUT to a digital logic high level, whereas when the latch is in the “reset” state then the latch asserts SROUT to a digital logic low level. From the waveforms of  FIG. 6 , it is recognized that a low pulse of the “SET” signal on node N 5  sets the latch such that the signal SROUT on node N 7  is forced high. A low pulse of the “RESET” signal on node N 6 A resets the latch such that the signal SROUT on node N 7  is forced low. The clock input filter circuit  2  of  FIG. 5  works in this way, setting and resetting the latch in alternating fashion. 
   Processor  3  can write a five-bit value in parallel into register  22 . The bits of this five-bit value are designated A 2 , A 1 , A 0 , B 1  and B 0 . The values of these five bits are decoded by decoders  23  and  24  to generate configuration and control signals S 7 -S 0  and T 3 -T 0 . The decoding functions performed by decoders  23  and  24  are set forth in the tables of  FIGS. 7 and 8 . 
   If bit B 1  has a digital low value and bit B 0  has a digital high value, then the values of T 0 -T 3  are [1, 1, 0, 0] as indicated by the second row of the table of  FIG. 8 . The SROUT signal on node N 7  is communicated from the upper input lead of multiplexer  25  and onto the upper input lead of NAND gate  26 . Because signal T 1  is a digital logic high, NAND gate  26  inverts the signal output by multiplexer  25  and supplies the resulting signal onto the center input lead of three-input NAND gate  27 . Because T 2  and T 3  both have digital logic low values, NAND gates  28  and  29  output digital logic high signals. Three-input NAND gate  27  therefore serves to invert the signal output by NAND gate  26 . The resulting signal is designated signal OUT and is supplied onto node N 10 . The logic inversions of gates  26  and  27  cancel one another such that the polarity of the signal OUT on node N 10  is the same as the polarity of the signal SROUT on node N 7 . The waveform  100  in  FIG. 6  represents this operation wherein the clock input filter circuit  2  receives the input signal IN and outputs the signal OUT such that the input signal IN is filtered (as will be explained in further detail below) and such that the signal OUT has substantially the same duty cycle as the input signal IN. In one example, clock multiplexer  5  supplies the signal OUT as signal CLK onto the CLK input lead  12  of processor  3 . 
   Clock input filter circuit  2  can be configured and controlled by processor  3  to receive the input signal IN and to output the signal OUT such that the input signal IN is filtered and such that the signal OUT has a substantially larger duty cycle that the signal IN. To do this, processor  3  writes a five-bit value into register  22  such that bits B 1  and B 0  are “1” and “0”, respectively. Decoder  24  outputs the values T 0 -T 3  to be [1, 0, 1, 0] as indicated in the third row of the table of  FIG. 8 . T 1  is a digital logic low so NAND gate  26  outputs a constant digital logic high onto the middle input lead of NAND gate  27 , thereby blocking the SROUT signal supplied through multiplexer  25 . T 3  is a digital logic low, thereby causing NAND gate  29  to output a constant digital logic high value onto the lower input lead of NAND gate  27 , thereby blocking the signal on node N 9  from being supplied in inverted fashion onto the lower input lead of NAND gate  27 . T 2  is, however, a digital logic high. The signal on node N 8  therefore is supplied in inverted fashion onto the upper input lead of NAND gate  27 . NAND gate  27 , because digital logic high values are present on its middle and lower input lead, inverts the signal on its upper input lead and supplies the resulting signal onto node N 10  as the signal OUT. 
   Multiplexer  25  and gates  28 ,  26 ,  29 , and  27  together form a four-input multiplexer structure. In this situation where T 0 =1, T 1 =0, T 2 =1 and T 3 =0, the signal on node N 8  is selected to be coupled to the output of the four-input multiplexer structure. 
   NAND gate  30  outputs a digital logic low level if the signals on both of its input leads have digital logic high levels. The waveform N 8  in  FIG. 6  illustrates the operation of NAND gate  30 . The signals on the two input leads of NAND gate  30  are the signals designated N 2  and N 7 . The signal output by NAND gate  30  is the signal designated N 8 . Note that the signal on node N 8  transitions from high-to-low as a result of the low-to-high transition  101  of non-duty-cycle adjusted signal SROUT on node N 7 . Note, however, that the signal on node N 8  then transitions from low-to-high prior to the low-to-high transition  102  of the non-duty cycle adjusted signal on node N 7 . The signal on node N 8  transitions from low-to-high due to the high-to-low transition  103  of the first signal on node N 2 . The result is a shortening of the amount of time that the signal on node N 8  is low in comparison to the amount of time that the signal IN is low. The signal on node N 8  passes through two inversions of gates  28  and  27  and is supplied onto node N 10  as the signal OUT. In  FIG. 6 , the waveform  104  labeled OUT represents the signal OUT when the clock input filter circuit  2  is configured to increase the duty cycle of the signal OUT. What is increased in this example is the amount of time that the signal OUT is at a digital logic level high as compared to the amount of time that the signal IN is at a digital logic level high. The amount of the increase is the propagation delay of a high-to-low transition on node N 2  passing to node N 7  (through gates  14  and  20 ). The amount of increase of the high time of the signal OUT is roughly designated with reference numeral  105  in  FIG. 6 . 
   Clock input filter circuit  2  can also be configured and controlled by processor  3  to receive the input signal IN and to output the signal OUT such that the signal OUT has a substantially smaller duty cycle that the signal IN. To do this, processor  3  writes a five-bit value into register  22  such that bits B 1  and B 0  are “1” and “1”, respectively. Decoder  24  therefore outputs the values T 0 -T 3  to be [1, 0, 0, 1] as indicated in the fourth row of the table of  FIG. 8 . T 1  is a digital logic low so NAND gate  26  outputs a constant digital logic high onto the middle input lead of NAND gate  27 , thereby blocking the SROUT signal supplied through multiplexer  25 . T 2  is a digital logic low so NAND gate  28  outputs a constant digital logic high value onto the upper input lead of NAND gate  27 , thereby blocking the signal on node N 8  from being supplied in inverted fashion onto the upper input lead of NAND gate  27 . T 3  is, however, a digital logic high. The signal on node N 9  therefore is supplied in inverted fashion onto the lower input lead of NAND gate  27 . NAND gate  27 , because digital logic high values are present on its upper and middle input leads, inverts the signal on its lower input lead and supplies the resulting signal onto node N 10  as the signal OUT. 
   NOR gate  31  outputs a digital logic high level if the signals on both of its input leads have digital logic low levels. The waveform labeled N 9  in  FIG. 6  illustrates the operation of NOR gate  31 . The signals on the two input leads of NOR gate  31  are the signals designated N 2  and N 7 . The signal output by NOR gate  31  is the signal designated N 9 . Note that the signal on node N 9  transitions from low-to-high as a result of the high-to-low transition  106  of non-duty-cycle adjusted signal SROUT on node N 7 . Note, however, that the signal on node N 9  transitions from high-to-low prior to the low-to-high transition  107  of the non-duty cycle adjusted signal on node N 7 . The signal on node N 9  transitions from high-to-low due to the low-to-high transition  108  of the first signal on node N 2 . The result is a lengthening of the amount of time that the signal on node N 9  is low in comparison to the amount of time that the signal IN is low. The signal on node N 9  passes through two inversions of gates  29  and  27  and is supplied onto node N 10  as the signal OUT. In  FIG. 6 , the waveform  109  labeled OUT represents the signal OUT when the clock input filter circuit  2  is configured to decrease the duty cycle of the signal OUT. What is decreased in this example is the amount of time that the signal OUT is at a digital logic level high as compared to the amount of time that the signal IN is at a digital logic level high. The amount of the decrease is the propagation delay of a low-to-high transition on node N 2  passing to node N 7  (through gates  16 ,  18  and  21 ). The amount of decrease of the high time of the signal OUT is designated with reference numeral  110  in  FIG. 6 . 
   Low-pass delay element  15  includes an inverter  32 , a resistor  33 , eight capacitors  34 - 41 , and a hysteresis logic gate  42 . Each of the eight capacitors  34 - 41  has its own switch (in this example, each switch is a passgate that involves a pair of N-channel and P-channel transistors coupled in parallel). In the specific embodiment of FIG.  5 , the gate capacitances of P-channel transistors are utilized to realize capacitors  34 - 41 . If the passgate of a capacitor is controlled to be conductive, then one plate of the capacitor is coupled to node N 2 B, otherwise the passgate is nonconductive and the plate of the capacitor is not coupled to node N 2 B. The passgates are identified by reference numerals  42 - 49 . Which of the capacitors is/are coupled to node N 2 B is determined by the values of control bits A 2 , A 1  and A 0  that are output from register  22 . The table of  FIG. 7  sets forth how the bit values A 2 , A 1  and A 0  are decoded by decoder  23  to generate the pass-gate control signals S 0 -S 7 . If, for example, passgate control signal S 0  is a digital logic high, then the leftmost passgate  42  is conductive and the gate plate of capacitor  34  is coupled through passgate  42  to node N 2 B. Resistor  33  and the total capacitance of all the capacitors  34 - 41  that is/are controlled to be coupled to node N 2 B form a low-pass RC network. The RC time constant of the low-pass RC filter of the low-pass delay element  15  is programmably adjustable by processor  3  by changing the values of the bits A 2 , A 1  and A 0 . 
   Low-pass delay element  15  low-pass filters low-to-high transitions of the signal on node N 2  (high-to-low transitions of the signal IN), but is not to filter high-to-low transitions of the signal on node N 2  (low-to-high transitions of the signal IN). A P-channel pullup transistor  50  has its drain coupled to node N 2 B and its gate coupled to node N 2 . When the signal on node N 2  transitions from a digital logic high to a digital logic low, P-channel transistor  50  is made conductive thereby discharging the capacitance on node N 2 B to supply voltage VDD. Similarly, when the signal on node N 2  transitions from a digital logic high to a digital logic low, then an inverter  44  drives a digital logic high signal onto node N 2 C and onto the gate of an N-channel pulldown transistor  43 . The drain of N-channel pulldown transistor  43  is coupled to node N 3 . Transistor  43  is made conductive, such that the voltage of the signal on node N 3  is pulled down to a digital logic low level. Accordingly, when the level of the signal on node N 2  is low (such as upon a high-to-low transition of the signal on node N 2 ), then the input lead of hysteresis gate  42  is forced to a digital logic high and the output lead of hysteresis gate  42  is forced to a digital logic low. The low-pass delay element  15  therefore does not low-pass filter the high-to-low transitions of the signal on node N 2 , but rather only low-pass filters low-to-high transitions of the signal on node N 2 . 
     FIG. 9  is a waveform diagram that illustrates an operation of low-pass delay element  15 . Signal IN begins transitioning from high to low at time T 1  and then transitions from low to high at time T 4 . NAND gate  13 , operating as an inverter, inverts the signal IN on node N 1  and supplies the first signal onto node N 2 . Inverter  32  of the low-pass delay element  15  in turn inverts the first signal on node N 2  and outputs an inverted version of the first signal onto node N 2 A. The waveform labeled N 2 A in  FIG. 9  illustrates the signal on node N 2 A. Node N 2 B is the output node of the RC filter made up of resistor  33  and the capacitances  34 - 41 . The voltage on node N 2 B decreases relatively slowly in accordance with how fast inverter  32  can charge the capacitance on node N 2 B. The waveform labeled N 2 B in  FIG. 9  illustrates the voltage on node N 2 B decreasing slowly after the falling edge of the signal on node N 2 A. The slope of the voltage on node N 2 B can be adjusted and changed by processor  3 . Although waveform N 2 B is illustrated as decreasing linearly, the actual signal decreases in a substantially exponential manner characteristic of an RC network. When the voltage on node N 2 B decreases to the point that it reaches the high-to-low threshold THRESH 2  of hysteresis logic gate  42 , then gate  42  switches and asserts the voltage signal on node N 3  to a digital logic high. At the time that the voltage on node N 3  transitions high, the signals on both input leads of NAND gate  14  are digital logic high values. NAND gate  14  therefore forces the signal on node N 5  to a digital logic low at time T 3 . The total delay from the beginning of the high-to-low transition of the signal IN at time T 1  to the corresponding high-to-low transition of the signal on node N 5  at time T 3  is designated D 1  in  FIG. 9 . 
   Next, in the example of  FIG. 9  the signal IN transitions from a digital logic low level to a digital logic high level beginning at time T 4 . Inverter  32  switches such that the signal on node N 2 A transitions from low to high. The digital logic low value of the signal on node N 2  causes P-channel pullup transistor  50  to be made conductive, thereby rapidly pulling the voltage on node N 2 B up to the supply voltage VDD potential. This action of pulling the voltage on node N 2 B up to VDD is represented in  FIG. 9  by arrow  201 . The digital logic low value of the signal on node N 2  also causes inverter  44  to make the N-channel pulldown transistor  43  conductive, thereby rapidly pulling the voltage on node N 3  down to ground potential. This pulling down of the voltage on node N 3  is represented in  FIG. 9  by arrow  202 . The delay D 2  between times T 4  and T 5  is therefore shorter than the delay D 1 . Due to the operation of transistors  50  and  43 , the RC network within low-pass delay element  15  does not operate to delay a low-to-high transition of the signal. IN. 
   Low-pass delay element  17  functions in the same manner as low-pass delay element  15 , except that low-pass delay element  17  operates in a complementary fashion. The rate at which inverter  51  can charge node N 2 D up to the low-to-high switching voltage of hysteresis gate  54  is determined by an RC network. High-to-low transitions of the signal IN are not delayed by low-pass delay element  17  due to P-channel pullup transistor  52  and N-channel transistor  53  being made conductive when the signal IN transitions from high to low. 
     FIG. 10  is a simplified waveform diagram showing a glitch filtering function performed by low-pass delay element  15 . A glitch  200  occurs in the signal IN during the time the signal IN is at a digital logic low level. When the voltage on node N 2  decreases to the threshold of transistor  50 , transistor  50  is made conductive such that the voltage on node N 2 B is pulled to a digital logic high level (the capacitance on node N 2 B is discharged rapidly by transistor  50 ). The rapidly rising edge  201  is illustrated in the waveform N 2 B in  FIG. 10 . Similarly, when glitch  200  causes the voltage on node N 2 C to increase to the threshold voltage of transistor  43 , transistor  43  is made conductive and the voltage on node N 3  is pulled to a digital logic low level. This is illustrated as edge  202  in  FIG. 10 . When glitch  200  passes and the voltage on node N 2  returns high, the transistors  50  and  43  are again made non-conductive. At this time, inverter  32  again outputs a digital logic low level onto node N 2 A as illustrated in  FIG. 10 . The voltage on node N 2 B therefore slowly falls due to the operation of the RC network in low-pass delay element  15 . If the capacitance on node N 2 B is set to have an appropriate magnitude, then the next rising edge  203  of the input signal IN will occur before the voltage on node N 2 B reaches the high-to-low threshold voltage THRESH 2  of hysteresis gate  42 . Hysteresis gate  42  will not switch. The output signal on node N 5  therefore has two edges rather than the four edges of the input signal IN. The extra two edges in the input signal IN due to the glitch do not pass through the low-pass delay element  15  to node N 5 . Glitch  200  does not cause an extra low pulse on node N 5 . Glitch  200  only causes the low SET pulse on node N 5  to terminate sooner than it would if there were no glitch. The low SET pulse begins at the same time it would have begun had there been no glitch. Glitch  200  does not affect the output of latch  19 , and does not affect the duty cycle or frequency of the output signal OUT on node N 10 . 
     FIG. 11  is a simplified flowchart of a method in accordance with one novel aspect. In one example, the first gate of steps  301 - 303  is gate  14  of  FIG. 5 , the latch of steps  303  and  307  is latch  19  of  FIG. 5 , the second gate of steps  305 - 307  is gate  16  and inverter  18  of  FIG. 5 , and the processor of step  308  is processor  3  of  FIG. 5 . The feedback arrows of the flowchart of  FIG. 10  are merely illustrative of two possible times that the processor can change the RC time constant. Processor  3  of  FIG. 5  can change the RC time constant of the RC network of low-pass delay element  15  at any time by writing an appropriate value into register  22 . 
   Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. One or both of the transistors  43  and  50  can be omitted from low-pass delay element  15  in some embodiments in order to modify the glitch filtering function performed by low-pass delay element  15 . One or both of the transistors  53  and  52  can be omitted from low-pass delay element  17  in order to modify the glitch filtering function performed by low-pass delay element  17 . Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.