Abstract:
An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.

Description:
PRIORITY CLAIM 
       [0001]    This application claims priority from Chinese Application for Patent No. 201610088186.X filed Feb. 16, 2016, the disclosure of which is incorporated by reference. 
       TECHNICAL FIELD 
       [0002]    This disclosure relates to the field of power switches, and, more particularly, to a driver circuit for precisely controlling the slew rate of the gate node of the power switching. 
       BACKGROUND 
       [0003]    Power switches, such as field effect transistors, are widely used in a variety of circuits and a variety of devices. An ideal power switch would be capable of switching on immediately when instructed to do so by a control signal. However, real world devices are not ideal, and thus there is a delay between receipt of the control signal by the power switch and the actual turning on of the switch. The converse is true with respect to the turning off of the power switch. 
         [0004]    The delay in the switching operation of the power switch imposes a constraint on the switching frequency and duty cycle of power switch. During the switching of the power switch, the voltage slew rate of the switching node should be controlled to improve EMI (Electro Magnetic Interference) behavior so as to not disturb operation of other portions of an electronic device incorporating the power switch. For a low side driving power switch, the switching node is drain of the power switch. For a high side driving power switch, the switching node is the source of the power switch. If the slew rate of the switch node is fast, an undesirable amount of EMI is generated. However, if the slew rate of the switch node is slow, the efficiency of the power switch is low since power consumption during switching is high. 
         [0005]    Therefore, a need exists for a driving circuit for a power switch that can carefully and precisely control the slew rate of the switch node. 
       SUMMARY 
       [0006]    This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter. 
         [0007]    One embodiment is directed to an electronic circuit for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry configured to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry is configured to generate a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry is configured to compare a drain voltage at the drain node to a reference voltage, and to activate third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage. 
         [0008]    A further embodiment is directed to an electronic device having a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic device includes first turn off circuitry coupled to the gate node and configured to draw a first current from the gate node in response to assertion of the OFF signal, the first current being proportional to a gate to source voltage of the power transistor. Second turn off circuitry is coupled to the gate node and configured to draw a second current from the gate node in response to assertion of the OFF signal, the second current being substantially constant. Second comparison circuitry is configured to compare a gate voltage at the gate node to a reference voltage, and to draw a third current from the gate node when the gate voltage is less than the reference voltage. 
         [0009]    An additional embodiment is directed to an electronic device for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic device includes first current sourcing circuitry configured to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current sourcing circuitry is configured to generate a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry is configured to compare a drain voltage at the drain node to a reference voltage, and to activate third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage. First current sinking circuitry coupled is to the gate node and configured to draw a fourth current from the gate node in response to assertion of the OFF signal, the fourth current being proportional to a gate to source voltage of the power transistor. Second current sinking circuitry is coupled to the gate node and configured to draw a fifth current from the gate node in response to assertion of the OFF signal, the fifth current being substantially constant. Second comparison circuitry is configured to compare a gate voltage at the gate node to a reference voltage, and to draw a sixth current from the gate node when the gate voltage is less than the reference voltage. 
         [0010]    A method aspect is directed to a method of switching a power transistor that includes turning on the power transistor. Where a gate to source voltage of the power transistor is less than a miller plateau voltage of the power transistor, a first current is generated to flow into a gate of the power transistor in response to assertion of an ON signal, the first current being substantially constant. Where the gate to source voltage is within a threshold of the miller plateau voltage, a second current is generated to flow into the gate in response to deassertion of an OFF signal, the second current being inversely proportional to the gate to source voltage. Where the gate to source voltage is higher than the miller plateau voltage, a third current is generated to flow into the gate of the power transistor, the third current being substantially constant. 
         [0011]    A further method aspect is directed to a method of switching a power transistor. The method includes turning off the power transistor. Where a gate to source voltage of the power transistor is greater than a miller plateau voltage of the transistor, a first current is drawn from a gate of the power transistor in response to assertion of the OFF signal, the first current being proportional to the gate to source voltage. Where the gate to source voltage is within a threshold of the miller plateau voltage, a second current is drawn from the gate of the power transistor in response to assertion of the OFF signal, the second current being substantially constant. Where the gate to source voltage is less than the miller plateau voltage, a third current is drawn from the gate of the power transistor, the third current being substantially constant. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a schematic diagram of a driving circuit for a power switch, in accordance with this disclosure. 
           [0013]      FIG. 2  shows a high side driving power switch utilizing the driving circuit of  FIG. 1 . 
           [0014]      FIG. 3  shows a low side driving power switch utilizing the driving circuit of  FIG. 1 . 
           [0015]      FIG. 4  is a timing diagram showing various signals of the driving circuit of  FIG. 1  during operation. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    In the following description, numerous details are set forth to provide an understanding of the present disclosure. It will be understood by those skilled in the art, however, that the embodiments of the present disclosure may be practiced without these details and that numerous variations or modifications from the described embodiments may be possible. 
         [0017]    Generally speaking, this disclosure provides for methods to minimize or reduce the delay associated with turn on and turn off of a power switch. To that end, the methods disclosed herein provide for accurate control of the slew rate of the drain or source of a power switch during switching so as to reduce the EMI (electromagnetic interference) generated from said switching. So as to optimize EMS (electromagnetic sensitivity), a strong turn on and strong turn off are implemented. The power switch can be a low side switch or a high side switch. 
         [0018]    During a charging phase of the gate of power switch, the current charging the gate is adjusted according to the status of the power switch, which may be in an off status, at its Miller plateau, or in a fully turned on status. During a discharging phase, the gate of power switch likewise adjusted according to the status of the power switch. The power switch is turned on when a control signal instructing turn on arrives so as to minimize or reduce the turn on delay, and is turned off when a control signal instructing turn off arrives. During switching, the voltage slew rate on drain or source of the power switch is carefully controlled to minimize or reduce emission to other electrical circuits or devices. The strong turn on/off is implemented to help ensure full turn on/off the power switch to thereby improve robustness in case power is injected to the output of power switch. 
         [0019]    With reference to  FIG. 1 , a driving circuit  100  for driving a power switch M 10  is now described. Transistor M 0  has a source coupled to a positive power supply Vdd, and a gate coupled to its drain. Transistor M 1  has its source coupled to Vdd and its gate coupled to the gate of transistor M 0 . The drain of transistor M 0  is coupled to the drain of transistor M 13 , which has its source coupled to current source CS 1  and its gate coupled to receive the “ON” signal. Current source CS 1  is coupled between the drain of transistor M 13  and the negative power supply Vss. 
         [0020]    The drain of transistor M 1  is coupled to the drain of transistor M 8  and thus the gate of transistor M 8 . Transistor M 18  has its drain coupled to the source of transistor M 8 , its gate coupled to its drain, and its source coupled Vss. Transistor M 9  has its drain coupled to Vdd, its gate coupled to the gate of transistor M 8 , and its source coupled to the gate of the power switch M 10 . Transistor M 19  has its drain coupled to the gates of transistors M 8  and M 9 , its source coupled to Vss, and its gate coupled to receive the “OFF” signal. 
         [0021]    Transistor M 2  has its source coupled to Vdd, its drain coupled to the gate of the power switch M 10 , and its gate coupled to the gates of transistors M 1  and M 0 . Transistor M 3  has its source coupled to Vdd, its drain coupled to the drain of transistor M 20 , and its gate coupled to the gates of transistors M 2 , M 1 , and M 0 . Transistor M 20  has its source coupled to Vss and its gate coupled to Vdd. 
         [0022]    Comparator  102  has an inverting terminal coupled to the drain of the power switch M 10 , its non-inveting terminal coupled to the drains of transistors M 3  and M 20 , and its output coupled to an input of NAND gate  104 . NAND gate  104  has its other input coupled to receive the “ON” signal, and provides its output to an input of NOR gate  106 . NOR gate  106  has its other input coupled to receive the “ON_dly” signal, which is a delayed and truncated version of the “ON” signal, and its output coupled to the gate of transistor M 7 . Transistor M 7  has its source coupled to Vdd and its drain coupled to the gate of the power switch M 10 . 
         [0023]    Transistor M 4  has its source coupled to Vdd, its drain coupled to the drain of transistor M 14 , and its gate coupled to its drain. Transistor M 14  has its source coupled to current source CS 2 , and its gate coupled to receive the “OFF” signal. Current source CS 2  is coupled between the source of transistor M 14  and Vss. 
         [0024]    Transistor M 5  has its source coupled to Vdd, its drain coupled to node N 1 , and its gate coupled to the gate and drain of transistor M 4 . Transistor M 21  has its drain coupled to node N 1 , its source coupled to Vss, and its gate coupled to its drain. Transistor M 22  has its drain coupled to the gate of the power switch M 10 , its source coupled to Vss, and its gate coupled to the gate and drain of transistor M 21 . 
         [0025]    Transistor M 16  has its drain coupled to node N 1 , its source coupled to Vss, and its gate coupled to the gate of transistor M 17 . Transistor M 17  has its drain coupled to the gate of the power switch M 10 , its source soupled to Vss, and its gate coupled to the gate of transistor M 16 . 
         [0026]    Transistor M 11  has its source coupled to the drain of transistor M 12  as well as to the gate of the power switch M 10 , its drain coupled to the source of transistor M 12  as well as to the drain of transistor M 24 , and its gate coupled to the gate of transistor M 24 . Transistor M 24  has its source coupled to Vss, and its gate also coupled to the gate of transistor M 12  through an inverter  108 . The gate of transistor M 12  and input of the inverter  108  receive the “OFF” signal. 
         [0027]    Transistor M 6  has its source coupled to Vdd, its drain coupled to node N 2 , and its gate coupled to the gates of transistors M 4  and M 5 . Transistor M 23  has its gate coupled to the gate of transistor M 10 , its source coupled to Vss, and its drain coupled to node N 2 . NAND gate  110  has a first input coupled to receive the “OFF” signal and a second input coupled to node N 2 , and provides its output to an input of OR gate  112 . OR gate  112  has a first input that receives the signal “OFF_dly”, which is a delayed and truncated version of the “OFF” signal, and has its output coupled to the gate of transistor M 15 . Transistor M 15  has its drain coupled to the gate of the power switch M 10  and its source coupled to Vss. 
         [0028]    M 10  is an on chip NMOS power switch. The positive supply Vdd and negative supply Vss are floating supply rails, where Vdd is maintained at certain voltage higher than Vss. Vss is connected to the source of M 10 . Where M 10  is a low side switch, as shown in  FIG. 1 , Vss is at a ground voltage. Where M 10  is a high side switch, Vss is a floating rail, as shown in  FIG. 3 . ON is the turn on signal of the power switch M 10 , while OFF is the turn off signal of the power switch M 10 . ON_dly is a delay signal of ON from logic ‘0’ to logic ‘1’. The delay time is a function of how long time it will take for the switch M 10  to be fully turned on. OFF_dly is a delay signal of OFF from logic ‘0’ to logic ‘1’. The delay time is a function of how long time it will take for the switch M 10  to be fully turned off. 
         [0029]      FIG. 4  shows the plots of ON, ON_dly, OFF, OFF_dly, the gate-source voltage of transistor M 10 , and the drain-source voltage of M 10 . To simply the description, the voltages hereafter will be described relative to Vss. 
         [0030]    Assume at time t 0  that the power switch M 10  is initially off, OFF is at a logic ‘1’, and ON is at a logic ‘0’. OFF_dly is at a logic ‘1’, and ON_dly is at a logic ‘0’. When OFF is at a logic ‘1’, transistor M 19  is on and drives the gate of transistor M 9  to ground to turn off transistor M 9 . Transistor M 15  is turned on by OR gate  112  in response to OFF_dly at a logic “1” to fully turn off the switch M 10  as a strong turn off. This addresses the case where there is interference on the source or drain of switch M 10 . Such a strong turn off can help ensure the switch M 10  is not turned on by interference on the source or drain of the switch M 10  when it should otherwise be off. For example, there may be a power injection on the source or drain of the switch M 10 . This strong turn off can improve the EMS (Electro Magnetic Sensitivity) of the switch M 10 . 
         [0031]    When ON changes from a logic ‘0’ to a logic ‘1’ at time t 1 , OFF and OFF_dly change to a logic ‘0’ nearly at the same time. M 13  is a transistor whose gate is controlled by ON. When transistor M 13  is on, the current I 0  flows through transistor M 13  to transistor M 0 . Then a current mirror formed by transistors M 1 , M 2  and M 3  is activated. Because OFF is now at a logic ‘0’, transistor M 19  is switched off. The current I 2  then biases the gate of transistor M 9  to a voltage based on current I 2 , transistor M 8 , and transistor M 18 . Since the voltage of the gate of the power switch M 10  is zero, the gate-source voltage of the transistor M 9  is Vgs_M 8 +Vgs_M 18 . 
         [0032]    The gate of the power switch M 10  is then charged by currents  13  and  14 . The current I 4  is held nearly constant as the gate voltage of the switch M 10  increases. The current I 3  is a relatively large current when Vgs_M 10  is small. As Vgs_M 10  increases, the current I 3  decreases. By choosing a proper value or size of the current I 2 , transistor M 8 , and transistor M 18 , Vgs_M 10  can be charged to the threshold voltage of the switch M 10  nearly immediately by the current I 3 . Then the current I 3  decreases to a small value or zero since Vgs_M 9  decreases as Vgs_M 10  increases. 
         [0033]    Thereafter, the switch M 10  enters the Miller plateau and its gate is charged by the current I 4 . By properly selecting I 4 , the voltage slew rate of Vds_M 10  at time t 3  can thus be controlled. As shown in  FIG. 4 , Vgs_M 10  changes from A to B in the Miller plateau during the turn on phase. Vds_M 10  changes from E to F in the Miller plateau during the turn on phase. Transistor M 20 , transistor M 3 , and comparator  102  are a detection circuit for the drain voltage of the switch M 10 . The transistor M 20  is same type of transistor as the switch M 10 , yet is smaller in size. The gate of M 20  is connected to Vcc to make it permanently on. The current from transistor M 3  biases the drain voltage of transistor M 20  to a voltage used as a reference voltage for comparator  102  to check whether the drain voltage of the switch M 10  is low enough such that the Miller plateau comes to an end during turn on phase at time t 3 . If the drain voltage of switch M 10  is lower than Vref_D at the drain of the transistor M 20 , the drain voltage detection circuit indicates that the Miller plateau will end by changing the output of comparator  102 . This “END” signal is logically combined with “ON” by logic circuits  104 . The logic low from  106  will cause the transistor M 7  turn on to pull the gate of M 10  to Vdd. 
         [0034]    The transistor M 7  works as a strong turn on for the switcch M 10  to improve EMS. Since M 20  is same type as M 10 , the reference voltage Vref_D changes with temperature. The temperature drift of the drain voltage of M 10  at the end of Miller plateau is compensated. ON_dly can also turn on M 7  after a delay time when ON signal is logic ‘1’. If there is something wrong with the drain voltage detection circuit, M 7  can be turned on by ON_dly signal. The delay time between ON and ON_DLY going high is set to ensure there is enough time for the slew rate control works during Miller plateau zone. This is shown by time t 4  in relation to time t 3 . Thus, the power switch M 10  is fully turned on. 
         [0035]    When the power switch M 10  is to be turned off, the ON signal goes from a logic ‘1’ to a logic ‘0’, at time t 5 , as does ON_dly. OFF goes from a logic ‘0’ to a logic ‘1’. Transistor M 19  is then turned on to drive the gate of transistor M 9  to Vss to switch off the transistor M 9 . Transistor M 14  will also be turned on. The current I 1  flows through transistor M 14 , and the current mirror formed by transistors M 5  and M 6  is activated. Transistors M 11  and M 12  are also turned on to short the drain and gate of transistor M 17 . Then, the transistor M 17  is working as a diode connected NMOS. 
         [0036]    The transistor M 17  is the same type transistor as M 10  although smaller. Thus, the transistor M 17  helps discharge the gate of the switch M 10  quickly. The transistor M 16  mirrors the drain current of the transistor M 17 . By choosing proper sizes of the transistors M 17 , M 16 , M 21  and M 22 , the discharge current of the gate of the gate M 10  can be made to change as follows—when Vgs_M 10  is high, the discharge current is large to thereby quickly discharge the gate voltage, and as Vgs_M 10  decreases, the discharge current decreases. When the gate to source voltage of transistor M 17 , Vgs_M 17 , is lower than its threshold voltage, the current I 10  goes to zero. 
         [0037]    The discharge current of the gate of the switch M 10  is thus set by the ratio of the current mirror of M 21  and M 22 . The power switch M 10  is then operating at the Miller plateau at time t 6 . The current I 8  is a constant current. By controlling the current I 8 , the voltage slew rate of Vds_M 10  is controlled. The transistors M 23  and M 6  are a gate voltage detection circuit of power switch M 10 . When the gate voltage of the switch M 10  is lower than a threshold set by transistors M 23  and M 6 , the drain voltage of transistor M 23  will go from low to high. That results in the Miller plateau of the switch M 10  during the turn off phase coming to an end at time t 7 . This signal “END” is logically combined with “OFF” by logic circuit  110 . The logic high output from  112  causes the transistor M 15  to tur on as a strong turn off of M 10  to improve EMS. OFF_dly can also turn on M 15  after a delay time of OFF signal if the gate voltage detection circuit experiences component failure. The delay time is set to help ensure that there is enough time for the Miller plateau. This is shown by time t 8  in relation to time t 7 . Thus, the power switch M 10  is fully turned off. 
         [0038]    The advantages of this design are that turn on delay is reduced by the current I 3  and the corresponding circuits. The voltage slew rate of Vds_M 10  during the turn on phase is controlled by I 4  and the corresponding circuits. The strong turn on is provided by the drain voltage detection circuit, transistor M 7  and the corresponding circuits. The turn off delay is reduced by transistor M 17  and the corresponding circuits. The voltage slew rate of Vds_M 10  during the turn off phase is controlled by the current I 8  and the corresponding circuits. The strong turn off is provided by the gate voltage detection circuit, transistor M 15 , and the corresponding circuits. Each working phase of the power switch M 10  during turn on/off is properly controlled and optimized. 
         [0039]    This design can be used as high side pre-driver or low side pre-driver for an N type power switch.  FIG. 2  shows how this design works as pre-driver of a low side switch.  FIG. 3  shows how the invention works as a pre-driver of a high side switch. 
         [0040]    Although the preceding description has been described herein with reference to particular means, materials and embodiments, it is not intended to be limited to the particulars disclosed herein; rather, it extends to all functionally equivalent structures, methods, and uses, such as are within the scope of the appended claims.