Abstract:
Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit. Apparatus and systems having such structures and methods of forming these structures for apparatus and systems are disclosed.

Description:
RELATED APPLICATIONS 
   This application is a continuation of U.S. application Ser. No. 10/789,882, filed Feb. 27, 2004, now U.S. Pat. No. 7,394,157, which is a divisional of U.S. application Ser. No. 10/117,041, filed Apr. 5, 2002, now U.S. Pat. No. 7,105,914, which is a divisional of U.S. application Ser. No. 09/484,002, filed Jan. 18, 2000, now U.S. Pat. No. 6,376,370, each of which are incorporated herein by reference in their entirety. 
   This application is related to the following commonly assigned applications: U.S. application Ser. No. 09/128,859 filed Aug. 4, 1998, now U.S. Pat. No. 6,284,656, U.S. application Ser. No. 09/488,098, filed Jan. 18, 2000, now U.S. Pat. No. 6,429,120, and U.S. application Ser. No. 09/484,303, filed Jan. 18, 2000, now U.S. Pat. No. 7,262,130, each of which are hereby incorporated by reference in their entirety. 

   FIELD OF THE INVENTION 
   The present invention relates generally to integrated circuits. More particularly, it pertains to structures and methods for providing seed layers for integrated circuit metallurgy. 
   BACKGROUND OF THE INVENTION 
   One of the main problems confronting the semiconductor processing industry, in the ULSI age, is that of Capacitive-Resistance loss in the wiring levels. This has led to a large effort to reduce the resistance of and lower the capacitive loading on the wiring levels. Since its beginning, the industry has relied on aluminum and aluminum alloys for wiring. In a like manner, the industry has mainly relied on SiO 2  as the insulator of choice, although polyimide was used in a number of products by one vendor (IBM), for a number of years. The capacitive resistance problem grows with each succeeding generation of technology. As the dimensions decrease the minimum line space combination decreases, thus increasing both capacitance and resistance, if the designer is to take advantage of the improved ground rules. 
   To improve the conductivity, it has been suggested by numerous investigators, that copper or perhaps silver or gold metallurgy be substituted for the aluminum metallurgy, now being used. Several potential problems have been encountered in the development of these proposed metallurgies. One of the main ones is the fast diffusion of copper through both silicon and SiO 2 . This along with the known junction poising effects of copper and gold have led to proposals to use a liner, to separate these metallurgies from the SiO 2  insulator. 
   For example, an article authored by Karen Holloway and Peter M. Fryer, entitled, “Tantalum as a diffusion barrier between copper and silicon”, Appl. Phys. Letter vol. 57, No. 17, 22 Oct. 1990, pp. 1736-1738, suggests the use of a tantalum metal liner. In another article authored by T. Laursen and J. W. Mayer, entitled, “Encapsulation of Copper by Nitridation of Cu—Ti Alloy/Bilayer Structures”, International Conference on Metallurgical Coatings and Thin Films, San Diego, Calif., Apr. 21-25, 1997, Abstract No. H1.03, pg. 309, suggests using a compound such as CuTi as the liner. Still another article published by Vee S. C. Len, R. E. Hurley, N. McCusker, D. W. McNill, B. M. Armstrong and H. S. Gamble, entitled, “An investigation into the performance of diffusion barrier materials against copper diffusion using metal-oxide-semiconductor (MOS) capacitor structures”, Solid-State Electronics 43 (1999) pp. 1045-1049 suggests using a compound such as TaN as the liner. These approaches, however, do not fully resolve the above-stated problem of the minimum line space decreases. Thus, the shrinking line size in the metal line and liner combination again increases both the capacitance and resistance. 
   At the same time other investigators, in looking at the capacitive loading effect, have been studying various polymers such as fluorinated polyimides as possible substitutions for SiO 2  insulators. Several of these materials have dielectric constants considerably lower than SiO 2 . However as in the case of SiO 2 , an incompatibility problem with copper metallurgy has been found. For example, in a presentation by D. J. Godbey, L. J. Buckley, A. P. Purdy and A. W. Snow, entitled, “Copper Diffusion in Organic Polymer Resists and Inter-level Dielectrics”, at the International Conference on Metallurgical Coatings and Thin Films, San Diego, Calif., Apr. 21-25, 1997, Abstract H2.04 pg. 313, it was shown that polyimide, and many other polymers, react with copper during the curing process, forming a conductive oxide CuO 2 , which is dispersed within the polymer. This then raises the effective dielectric constant of the polymer and in many cases increases the polymers conductivity. In addition it has been found that reactive ion etching (RIE) of all three metals, copper, silver or gold, is difficult at best. 
   Other approaches by investigators have continued to look for ways to continue to use aluminum wiring with a lower dielectric constant insulator. This would decrease the capacitive load with a given inter-line space but require wider or thicker lines. The use of thicker lines would increase the capacitive loading in direct proportion to the thickness increase. Thus to some measure, it defeats the objectives of decreasing the capacitive loading effects. Therefore, the use of thicker lines should be avoided as much as possible. As the resistivity of the line is directly proportional to its cross-sectional area, if it cannot be made thicker, it must be made wider. If however the lines are made wider, fewer wiring channels can be provided in each metal level. To obtain the same number of wiring channels, additional levels of metal must be provided. This increases the chip cost. So if this approach is to be followed, it is imperative that a low cost process sequence be adopted. 
   One approach provided by the present inventor in a co-pending application, entitled, “Copper Metallurgy in Integrated Circuits”, filed Aug. 4, 1998, application Ser. No. 09/128,859, proposes a method to solve many of the problems associated with using copper in a polymer insulator. This process, which was specifically designed to be compatible with a polymer or foam insulation, required that the unwanted copper on the surface of each layer be removed by Chemical Mechanical Polishing (CMP) or a similar planarizing process. However, this method may require careful process control, leading to additional expense. Another approach is provided in a co-pending application by Kie Ahn and Leonard Forbes, entitled “Method for Making Copper and Other Metal Interconnections in Integrated Circuits”, filed Feb. 27, 1998, U.S. Ser. No. 09/032,197, which proposes a method using ionized sputtering to form the underlayer, then forming a low wetting layer on the areas where no copper is desired using jet vapor deposition. The copper is deposited with ionized Magnetron sputtering followed by hydrogen annealing. The excess copper is then removed by CMP as in the aforementioned application. 
   Another process is described by the present inventor in a co-pending application, entitled, “Integrated Circuit with Oxidation Resistant Polymeric Layer”, filed Sep. 1, 1998, U.S. Ser. No. 09/145,012, which eliminates many of the CMP processes and uses lift-off to define the trench and the seed layer simultaneously. A process is also described by the present inventor in a co-pending application, entitled, “Conductive Structures in Integrated Circuits” filed Mar. 1, 1999, U.S. Ser. No. 09/259,849, which required a CMP process to remove unwanted seed material prior to a selective deposition of the metal layers in a damascene or dual damascene process. 
   The use of CMP has proven to be effective in reducing local non-planarity. However, extensive dishing in wide lines and rounding of corners of the insulator are a common occurrence. It has been found that by maintaining a regular structure through the use of dummy structures and small feature sizes, it is possible to planarize a level to a nearly flat surface. The use of these techniques are however costly and in some cases come with density or performance penalties. It is, however, generally possible to planarize a structure prior to the metal levels using these methods with little or no density penalty. The use of electroless plating has been suggested in an article authored by Yosi Schacham-Diamand and Valery M. Dubin, entitled “Copper electroless deposition technology for ultra-large scale-integration (ULSI) metallization”, Microelectronic Engineering 33 (1997) 47-58, however a simple process for obtaining both a barrier layer as well as a seed layer is needed to improve the cost effectiveness of this technique. One technique for seeding polyimide and silicon surfaces using high energy (10-20 Kilo Electron Volts {KEV}) ion implantation has been demonstrated in an article authored by S. Bhansali, D. K. Sood and R. B. Zmood, entitled “Selective electroless copper plating on silicon seeded by copper ion implantation”, Thin Solid Films V253 (1994) pp. 391-394. However this process has not been shown to be implementable into a product structure where a barrier and/or adhesion layer is required. 
   For the reasons stated above and for others which will become apparent from reading the following disclosure, structures and methods are needed which alleviate the problems associated with via and metal line fabrication processes. These structures and methods for via and metal line fabrication must be streamlined and accommodate the demand for higher performance in integrated circuits even as the fabrication design rules shrink. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The following detailed description of the preferred embodiments can best be understood when read in conjunction with the following drawings, in which: 
       FIG. 1A-1K  illustrate one embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention; 
       FIG. 2A-2K  illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention; 
       FIG. 3A-3K  illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention; 
       FIG. 4A-4L  illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention; 
       FIG. 5  is an illustration of an integrated circuit formed according to the teachings of the present invention. 
       FIG. 6  illustrates an embodiment of a system including a portion of an integrated circuit formed according to any of the embodiments described in the present application. 
   

   DETAILED DESCRIPTION 
   In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. 
   The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term insulator is defined to include any material that is less electrically conductive than the materials generally referred to as conductors by those skilled in the art. The following detailed description is, therefore, not to be taken in a limiting sense. 
   What is disclosed herein is a low cost process to achieve reduced capacitance and resistance loss in wiring levels. The present invention requires only one complete CMP planarizing coupled with the formation of the first level vias, no matter how many levels of metallurgy are used. What are essentially cleanup CMP steps on each metal level are used in one process sequence. This process can be used with an aluminum, copper, silver, gold or any other material which can subsequently be electrolessly plated or deposited by selective CVD or any other selective deposition process. A polyimide, other polymer or foam polymer can be used as an insulator. It can also be used with an oxide or other inorganic insulating structure if the insulating stack is compatible with the metal being used. It can also be used to form air bridge structures as well. The process uses low energy ion implantation to deposit both the adhesion and/or barrier layer along with the seed layer. This is coupled with using the resist layer which defines the damascene trench as the blocking layer to define the implant areas. Low energy implantation allows the placing of distinct layers of both barrier/adhesion and seed layers. The use of the same resist layers to define both the trench and seed layers allows a low cost implementation of the process. 
   The structures and methods of embodiments of the present invention include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. According to the teachings of the present invention, the selective deposition of the metal lines avoids the need for multiple chemical mechanical planarization (CMP) steps. The low energy ion implantation of the present invention allows for the distinct placement of both the diffusion barrier and the seed layer. A residual resist can be used to remove the diffusion barrier and the seed layer from unwanted areas on a wafer surface. 
   In particular one illustrative embodiment of the present invention includes a method of making a diffusion barrier and a seed layer in an integrated circuit. The method includes patterning an insulator material to define a number of trenches in the insulator layer opening to a number of first level vias in a planarized surface. A barrier/adhesion layer is deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. This novel methodology further accommodates the formation of aluminum, copper, gold, and/or silver metal interconnects. 
   Embodiment of a Metal Interconnect Using Copper and Polyimide 
     FIGS. 1A-1K  illustrate a novel methodology for the formation of metal interconnects and/or a wiring structure in an integrated circuit according to the teachings of the present invention. The novel methodology includes the novel formation of a barrier/adhesion layer and a seed layer in an integrated circuit using a low energy ion implantation. The novel methodology also encompasses a novel method of making copper, silver, aluminum, or gold interconnect for an integrated circuit. 
     FIG. 1A  illustrates a portion of an integrated circuit structure, namely an integrated circuit having a number of semiconductor devices formed in a substrate.  FIG. 1  illustrates the structure after a device structure is formed in the substrate and the contact structure to the device structure is in place. One of ordinary skill in the art will understand upon reading this disclosure the manner in which a number of semiconductor structures, e.g. transistors, can be formed in a substrate. One of ordinary skill in the art will also understand upon reading this disclosure the manner in which a contact structure can be formed connecting to a given semiconductor device in a substrate. For example,  FIG. 1A  illustrates the structure after a number of device structures, e.g. transistor  101 A and  101 B are formed in the substrate  100 . An insulator layer  102  is deposited over the number of semiconductors  101 A and  101 B. The deposition of the insulator layer  102  can include depositing a layer of Si 3 N 4  having a thickness in the range of 100 to 500 Angstroms (Å). This insulator layer will also serve as an additional barrier to impurities coming from subsequent processing steps. Contact holes  105 A and  105 B are opened to the number of device structures  101 A and  101 B using a photolithography technique. One of ordinary skill in the are will understand, upon reading this disclosure, the manner in which a photolithography technique can be used to create contact holes  105 A and  105 B. In one embodiment of the present invention a titanium silicide liner  106 A and  106 B is placed in the contact holes  105 A and  105 B, such a through a process such as chemical vapor deposition (CVD). Next, tungsten vias  107 A and  107 B can be deposited in the contact holes  105 A and  105 B. The tungsten vias  107 A and  107 B can be deposited in the contact holes using any suitable technique such as using a CVD process. The excess tungsten is then removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface  109 . 
   As shown in  FIG. 1B , a first polymer layer  108 , or first layer of polyimide  108 , is deposited over the wafer surface. The first polymer layer  108  may be deposited using, for example, the process and material described in co-pending and commonly assigned application U.S. Ser. No. 09/128,859, entitled “Copper Metallurgy in Integrated Circuits,” which is hereby incorporated by reference. In one embodiment, depositing a first polymer layer  108  includes depositing a foamed polymer layer  108 . In one embodiment, the first layer of polyimide  108  is deposited and cured, forming a 5000 Å thick layer of polymer  108  after curing. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the first layer of polyimide  108 , or insulator layer/material  108 , may also be deposited as suited for forming a first level metal pattern, the invention is not so limited. The first layer of polyimide  108 , or first insulator layer/material  108  is patterned to define a number of trenches  110  in the first insulator layer  108  opening to a number of first level vias, e.g. tungsten vias  107 A and  107 B in planarized surface  109 . In other words, a first level metal pattern  110  is defined in a mask layer of photoresist  112  and then the first layer of polyimide  108  is etched, using any suitable process, e.g. reactive ion etching (RIE), such that the first level metal pattern  110  is defined in the polyimide. According to the teachings of the present invention, a residual photoresist layer  112  is left in place on the first insulator layer  108  in a number of region  113  outside of the number trenches  110 . The structure is now as appears in  FIG. 1B . 
   As shown in  FIG. 1C , a first barrier/adhesion layer  114  is deposited in the number of trenches  110  using a low energy ion implantation. In one embodiment according to the teachings of the present invention, depositing the barrier/adhesion layer  114  includes depositing a layer of zirconium  114  having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the barrier/adhesion layer  114  includes depositing a barrier/adhesion layer  114  of titanium and/or hafnium. In one embodiment, depositing the depositing a layer of zirconium  114  includes depositing a layer of zirconium  114  having a thickness of approximately 50 Å. This can be achieved using a 10 17  ion implant of zirconium, i.e. 10 17  ions of zirconium per square centimeter (cm 2 ). According to the teachings of the present invention, the layer of zirconium  114  is implanted at 100 electron volts (eV) into the surface of the trenches  110  in the polymer layer  108  using a varying angle implant (∞), as represented by arrows  111 , where the angle of implantation is changed from normal to the wafer surface to 15 degrees off normal. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation is changed from normal to the planarized surface  109  to approximately 15 degrees off normal deposits the barrier/adhesion layer  114  on all surfaces in the number of trenches  110 . The structure is now as appears in  FIG. 1C . 
   In  FIG. 1D , a first seed layer  116  is deposited on the first barrier/adhesion layer  114  using a low energy ion implantation. According to the broader teachings of the present invention, depositing the seed layer  116  on the barrier/adhesion layer  114  includes depositing a seed layer  116  selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer  116  includes depositing a layer of copper  116  having a thickness of approximately a 100 Å. This can be achieved using an 8×10 16  ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper  116  at 100 electron volts (eV) into the surface of the trenches  110  in the polymer layer. Also the layer of copper  116  is implanted at an angle normal to the wafer&#39;s surface, as shown by arrows  115 . As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper  116  at an angle normal to the planarized surface results in the seed layer of copper  116  remaining on a bottom surface  118  in the number of trenches  110  and to a much lesser extent on the side surfaces  117  of the number of trenches  110 . In one embodiment, an optional layer of aluminum  121  is deposited over the copper seed layer  116  again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum  121  is deposited to have a thickness of approximately a 50 Å. This can be achieved using a 3×10 16  ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum  121  is used to protect the copper seed layer  116  from oxidation prior to subsequent processing steps. The structure is now as shown in  FIG. 1D . 
     FIG. 1E  illustrates the structure after the next sequence of process steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer  112  has served as a blocking layer to define the implant areas for the barrier/adhesion layer  114 , the seed layer  116 , and the layer of aluminum  121 . The residual photoresist layer  112  is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer  112  includes removing the unwanted aluminum layer  121 , the unwanted seed layer  116 , and the unwanted barrier/adhesion layer  114  from other areas of the wafer&#39;s surface, e.g., from over a number of regions  113  outside of the trenches  110  on a top surface  119  of the first insulator layer  108 . The structure is now as shown in  FIG. 1E . 
   In  FIG. 1F , a metallic conductor  120 , or number of first level metal lines  120 , is deposited over the seed layer  116  in the number of trenches  110 . According to teachings of the present invention, metallic conductor  120 , or number of first level metal lines  120 , is selected from the group consisting of aluminum, copper, silver, and gold depending on the type of seed layer  116  which was deposited. According to this embodiment, the metallic conductor  120 , or number of first level metal lines  120  are selectively formed on the copper seed layer  116  such that the number of copper metal lines  120 , or first level copper metal lines  120  are not formed on the top surface  119  of the first insulator layer  108 . In one embodiment, the metallic conductor  120 , or number of first level metal lines  120 , is deposited using a selective CVD process. In another embodiment, depositing a metallic conductor  120 , or number of first level metal lines  120 , over the seed layer  116  includes depositing a metallic conductor  120  using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the number of trenches  110  to the top surface  119  of the first insulator layer  108 . 
   As shown in  FIG. 1G , the process sequence may be continued to form any number of subsequent metal layers in a multilayer wiring structure.  FIG. 1G  illustrates the structure after the next sequence of processing steps. In  FIG. 1G , a dual damascene process is used to define and fill a first to a second level of vias and a second level metallurgy. To do so, a second polymer layer  124 , or second layer of polyimide  124 , is deposited over the wafer surface, e.g. the metallic conductor  120 , or number of first level metal lines  120 , and the first polymer layer  108 . The second polymer layer  124  may similarly be deposited using, for example, the process and material described in co-pending and commonly assigned application U.S. Ser. No. 09/128,859, entitled “Copper Metallurgy in Integrated Circuits,” which is hereby incorporated by reference. In one embodiment, depositing a second polymer layer  124  includes depositing a foamed second polymer layer  124 . In one embodiment, the second polymer layer  124  is deposited and cured, forming a 10,000 Å thick second polymer layer  124  after curing. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the second polymer layer  124 , or second insulator layer/material  124 , may also be deposited as suited for forming a first to a second level of vias, e.g. second level vias, and a number of second level metal lines, the invention is not so limited. The second polymer layer  124 , or second insulator layer/material  124  is patterned to define a second level of vias and a number of second level metal lines in the second insulator layer/material  124  opening to the metallic conductor  120 , or number of first level metal lines  120 . In other words, a second level of vias is defined in a second mask layer of photoresist  126  and then the second polymer layer  124  is etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of via openings  128  are defined in the polyimide. Using the dual damascene process, a number of second level metal lines are also defined in a second mask layer of photoresist  126  and the second polymer layer  124  is again etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of metal line trenches  130  are defined in the polyimide. One of ordinary skill in the art will understand upon reading this disclosure, the manner in which a photoresist layer  126  can be mask, exposed, and developed using a dual damascene process to pattern a second level of via openings  128  and a second level of metal line trenches  130  in the second insulator layer/material  124 . 
   As described previously, and according to the teachings of the present invention, a residual photoresist layer  126  is left in place on the second insulator layer/material  124  in a number of regions  132  outside of the second level of metal line trenches  130 . A suitable plasma and/or wet cleaning process is used to remove any contaminates from the second level of via openings  128  and a second level of metal line trenches  130 , as the same will be understood by one of ordinary skill in the art upon reading this disclosure. The structure is now as appears in  FIG. 1G . 
     FIG. 1H  illustrates the structure  100  after the next sequence of processing steps. In  FIG. 1H , a second barrier/adhesion layer  134  is deposited in the second level of via openings  128  and a second level of metal line trenches  130  using a low energy ion implantation. As described above, in one embodiment according to the teachings of the present invention, depositing the second barrier/adhesion layer  134  includes depositing a layer of zirconium  134  having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the second barrier/adhesion layer  134  includes depositing a barrier/adhesion layer  134  of titanium and/or hafnium. In one embodiment, depositing the layer of zirconium  134  includes depositing a layer of zirconium  134  having a thickness of approximately 50 Å. In one embodiment, this is achieved using a 10 17  ion implant of zirconium. According to the teachings of the present invention, the layer of zirconium  134  is implanted at 100 electron volts (eV) into the surface of the second level of via openings  128  and a second level of metal line trenches  130  in the second polymer layer  124  using a varying angle, as shown by arrows  125 , implant where the angle of implantation is changed from normal to the wafer surface to 15 degrees off normal. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation is changed from normal to the wafer surface to approximately 15 degrees off normal deposits the barrier/adhesion layer  134  on all surfaces in the second level of via openings  128  and a second level of metal line trenches  130 . The structure is now as appears in  FIG. 1H . 
     FIG. 1I  illustrates the structure  100  after the next sequence of processing steps. In  FIG. 1I , a second seed layer  136  is deposited on the second barrier/adhesion layer  134  using a low energy ion implantation. According to the broader teachings of the present invention, depositing the second seed layer  136  on the second barrier/adhesion layer  114  includes depositing a second seed layer  136  selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the second seed layer  136  includes depositing a second layer of copper  136  having a thickness of approximately a 100 Å. In one embodiment, this is achieved using an 8×10 16  ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper  136  at 100 electron volts (eV) into the surfaces of the second level of via openings  128  and the polymer layer. Also the layer of copper  136  is implanted at an angle normal to the wafer&#39;s surface as shown by arrows  137 . As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper  136  at an angle normal to the planarized surface results in the second seed layer of copper  136  remaining on a bottom surface  138  in the second level of via openings  128  and second level of metal line trenches  130  and to a much lesser extent on the side surfaces  140  of the second level of via openings  128  and a second level of metal line trenches  130 . In one embodiment, an optional layer of aluminum  141  is deposited over the second copper seed layer  136  again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum is deposited to have a thickness of approximately a 50 Å. In one embodiment, this is achieved using a 3×10 16  ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum  141  is used to protect the second copper seed layer  136  from oxidation prior to subsequent processing steps. 
     FIG. 1J  illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer  126  has served as a blocking layer to define the implant areas for the second barrier/adhesion layer  134 , the second seed layer  136 , and the aluminum layer  141 . The residual photoresist layer  126  is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer  126  includes removing the unwanted aluminum layer  141 , the unwanted seed layer  136 , and the unwanted barrier/adhesion layer  134  from other areas of the wafer&#39;s surface, e.g. from over a number of regions  132  outside of second level of metal line trenches  130  on a top surface  142  of the second insulator layer  124 . The structure is now as shown in  FIG. 1J . 
   In  FIG. 1K , a second metallic conductor  144 , or second core conductor  144 , is deposited over or formed on the second seed layer  136  and within the second barrier/adhesion layer  134  in the second level of via openings  128  and the second level of metal line trenches  130  in the polymer layer. In this embodiment the second metallic conductor  144 , or second core conductor  144 , is copper, but in other embodiments of the present invention can be selected from the group consisting of aluminum, silver, and gold. In one embodiment, the second metallic conductor  144 , or second core conductor  144 , is deposited using a selective CVD process such that the second metallic conductor  144 , or second core conductor  144  is not formed on a top surface  142  of the second insulator layer  124 . In another embodiment, depositing a second metallic conductor  144 , or second core conductor  144 , over on the second seed layer  136  and within the second barrier/adhesion layer  134  includes depositing a second metallic conductor  144 , or second core conductor  144 , using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the second level of via openings  128  and the second level of metal line trenches  130  to the top surface  142  of the second insulator layer  124 . Thus, the second barrier/adhesion layer  134 , the second seed layer  136 , and the second metallic conductor  144 , or second core conductor  144 , constitute a second number of conductive structures which includes a number of second level vias and a number of second level metal lines which are formed over and connect to a first number of conductive structures, e.g. the first level metal lines  120 . 
   Embodiment of a Metal Interconnect Using Aluminum Metal Lines and Oxide Insulators 
     FIGS. 2A-2K  illustrate a novel methodology for the formation of metal interconnects and/or a wiring structure in an integrated circuit according to the teachings of the present invention. The novel methodology includes the novel formation of a barrier/adhesion layer and a seed layer in an integrated circuit using a low energy ion implantation. The novel methodology also encompasses a novel method of making copper, silver, aluminum, or gold interconnect for an integrated circuit. 
     FIG. 2A  illustrates a portion of an integrated circuit structure, namely an integrated circuit having a number of semiconductor devices formed in a substrate as described above in connection with  FIG. 1A . That is,  FIG. 2A  illustrates the structure after a device structure is formed in the substrate and the contact structure to the device structure is in place. Like  FIG. 1A ,  FIG. 2A  illustrates the structure after a number of device structures, e.g. transistor  201 A and  201 B are formed in the substrate  200 . An insulator layer  202  is deposited over the number of semiconductors  201 A and  201 B. The deposition of the insulator layer  202  can include depositing a layer of Si 3 N 4  having a thickness in the range of 100 to 500 Angstroms (Å). This insulator layer will also serve as an additional barrier to impurities coming from subsequent processing steps. Contact holes  205 A and  205 B are opened to the number of device structures  201 A and  201 B using a photolithography technique. One of ordinary skill in the are will understand, upon reading this disclosure, the manner in which a photolithography technique can be used to create contact holes  205 A and  205 B. In one embodiment of the present invention a titanium silicide liner  206 A and  206 B is placed in the contact holes  205 A and  205 B, such a through a process such as chemical vapor deposition (CVD). Next, tungsten vias  207 A and  207 B can be deposited in the contact holes  205 A and  205 B. The tungsten vias  207 A and  207 B can be deposited in the contact holes using any suitable technique such as using a CVD process. The excess tungsten is then removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface  209 . 
   As shown in  FIG. 2B , a first oxide layer  208 , e.g. a silicon dioxide layer (SiO 2 ), is deposited over the wafer surface. In one embodiment, depositing a first oxide layer  208  includes depositing a fluorinated silicon oxide layer  208 . The first oxide layer  208  may be deposited using any suitable technique, such as, for example, using a CVD process. In one embodiment, depositing a first oxide layer  208  having a thickness of approximately 5000 Å. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thicknesses for the first oxide layer  208  may also be deposited as suited for forming a first level metal pattern, the invention is not so limited. The first oxide layer  208  is patterned to define a number of trenches  210  in the first oxide layer  208  opening to a number of first level vias, e.g. tungsten vias  207 A and  207 B in planarized surface  209 . In other words, a first level metal pattern  210  is defined in a mask layer of photoresist  212  and then the first oxide layer  208  is etched, using any suitable process, e.g. reactive ion etching (RIE), such that the first level metal pattern  210  is defined in the first oxide layer  208 . One of ordinary skill in the art will understand upon reading this disclosure that any desired first level metal pattern  210  can be created using a photolithography technique. According to the teachings of the present invention, a residual photoresist layer  212  is left in place on the first oxide layer  208  in a number of region  213  outside of the number trenches  210 . The structure is now as appears in  FIG. 2B . 
   As shown in  FIG. 2C , a first barrier/adhesion layer  214  is deposited in the number of trenches  210  using a low energy ion implantation. In one embodiment according to the teachings of the present invention, depositing the barrier/adhesion layer  214  includes depositing a layer of zirconium  214  having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the barrier/adhesion layer  214  includes depositing a barrier/adhesion layer  214  of titanium and/or hafnium. In one embodiment, depositing the depositing a layer of zirconium  214  includes depositing a layer of zirconium  214  having a thickness of approximately 50 Å. This can be achieved using a 10 17  ion implant of zirconium. According to the teachings of the present invention, the layer of zirconium  214  is implanted at 100 electron volts (eV) into the surface of the trenches  210  in the first oxide layer  208  using a varying angle implant (∞), as represented by arrows  211 , where the angle of implantation is changed from normal to the wafer surface to 15 degrees off normal. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation (∞) is changed from normal to the wafer&#39;s surface to approximately 15 degrees off normal deposits the barrier/adhesion layer  214  on all surfaces in the number of trenches  210 . The structure is now as appears in  FIG. 2C . 
   In  FIG. 2D , a first seed layer  216  is deposited on the first barrier/adhesion layer  214  using a low energy ion implantation. According to the broader teachings of the present invention, depositing the seed layer  216  on the barrier/adhesion layer  214  includes depositing a first seed layer  216  selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer  216  includes depositing a layer of an aluminum copper alloy  216  having a thickness of approximately 110 Å. This can be achieved by depositing a first layer of aluminum  281  on the barrier/adhesion layer  214  to a thickness of approximately 50 Å using a low energy ion implantation of approximately 100 electron volts (eV). A layer of copper  282  is then deposited on the first layer of aluminum  281  to a thickness of approximately 10 Å using a low energy ion implantation of approximately 100 eV. A second layer of aluminum  283  is then deposited on the layer of copper  282  to a thickness of approximately 50 Å using a low energy ion implantation of approximately 100 eV. Also the first seed layer  216  is implanted at an angle normal to the planarized surface, as shown by arrows  215 . As one of ordinary skill in the art will understand upon reading this disclosure, implanting the first seed layer  216  at an angle normal to the planarized surface results in the first seed layer  216  remaining on a bottom surface  218  in the number of trenches  210  and to a much lesser extent on the side surfaces  217  of the number of trenches  210 . 
     FIG. 2E  illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer  212  has served as a blocking layer to define the implant areas for the barrier/adhesion layer  214  and the seed layer  216 . The residual photoresist layer  212  is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer  212  includes removing the unwanted seed layer  216  and the unwanted barrier/adhesion layer  214  from other areas of the wafer&#39;s surface, e.g. from over a number of regions  213  outside of the trenches  210  on a top surface  219  of the first insulator layer  208 . The structure is now as shown in  FIG. 2E . 
   In  FIG. 2F , a metallic conductor  220 , or number of first level metal lines  220 , is deposited over the first seed layer  216  and within the first barrier/adhesion layer  214  in the number of trenches  210 . In this embodiment, the metallic conductor  220 , or number of first level metal lines  220 , is aluminum, but in other embodiments of the present invention the metallic conductor  220 , or number of first level metal lines  220 , is selected from the group consisting of copper, silver, and gold depending on the type of seed layer  216  which was deposited. In one embodiment, the metallic conductor  220 , or number of first level metal lines  220 , is deposited using a selective CVD process. In another embodiment, depositing a metallic conductor  220 , or number of first level metal lines  220 , over the seed layer  216  includes depositing a metallic conductor  220  using electroless plating. According to the teachings of the present invention the number of first level aluminum metal lines  220 , is deposited to fill the number of trenches  210  to the top surface  219  of the first oxide layer  208 . Thus, the first level aluminum metal lines  220 , the first seed layer  216 , and the first barrier/adhesion layer  214  in the number of trenches  210  constitute a first number of conductive structures. The copper composition of the first seed layer  216  can be adjusted to give the appropriate percentage of copper in the completed first number of conductive structures. For example, in the above described embodiment the layer thicknesses of the aluminum copper sandwich was designed to give a 0.7 weight percent of copper in the first number of conductive structures. 
   As shown in  FIG. 2G , the process sequence may be continued to form any number of subsequent metal layers in a multilayer wiring structure.  FIG. 2G  illustrates the structure after the next sequence of processing steps. In  FIG. 2G , a dual damascene process is used to define and fill a first to a second level of vias and a second level metallurgy. To do so, a second oxide layer  224  is deposited over the wafer surface, e.g. the metallic conductor  220 , or number of first level metal lines  220 , and the first oxide layer  208 . In one embodiment, depositing a second oxide layer  224  includes depositing a second fluorinated silicon oxide layer  224 . In one embodiment, the second oxide layer  224  is formed to have a thickness of approximately 10,000 Å. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the second oxide layer  224  may also be deposited as suited for forming a first to a second level of vias, e.g. second level vias, and a number of second level metal lines, the invention is not so limited. The second oxide layer  224  is patterned to define a second level of vias and a number of second level metal lines in the second oxide layer  224  opening to the metallic conductor  220 , or number of first level metal lines  220 . In other words, a second level of vias is defined in a second mask layer of photoresist  226  and then the second oxide layer  224  is etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of via openings  228  are defined in the polyimide. Using the dual damascene process, a number of second level metal lines are also defined in a second mask layer of photoresist  226  and the second oxide layer  224  is again etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of metal line trenches  230  are defined in the second oxide layer  224 . One of ordinary skill in the art will understand upon reading this disclosure, the manner in which a photoresist layer  226  can be mask, exposed, and developed using a dual damascene process to pattern a second level of via openings  228  and a second level of metal line trenches  230  in the second oxide layer  224 . 
   As described previously, and according to the teachings of the present invention, a residual photoresist layer  226  is left in place on the second oxide layer  224  in a number of regions  232  outside of the second level of metal line trenches  230 . A suitable plasma and/or wet cleaning process is used to remove any contaminates from the second level of via openings  228  and a second level of metal line trenches  230 , as the same will be understood by one of ordinary skill in the art upon reading this disclosure. The structure is now as appears in  FIG. 2G . 
     FIG. 2H  illustrates the structure after the next sequence of processing steps. In  FIG. 2H , a second barrier/adhesion layer  234  is deposited in the second level of via openings  228  and a second level of metal line trenches  230  using a low energy ion implantation. As described above, in one embodiment according to the teachings of the present invention, depositing the second barrier/adhesion layer  234  includes depositing a layer of zirconium  234  having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the second barrier/adhesion layer  234  includes depositing a barrier/adhesion layer  234  of titanium and/or hafnium. In one embodiment, depositing the layer of zirconium  234  includes depositing a layer of zirconium  234  having a thickness of approximately 50 Å. In one embodiment, this is achieved using a 10 17  ion implant of zirconium (that is 10 17  ions per square centimeter). According to the teachings of the present invention, the layer of zirconium  234  is implanted at 100 electron volts (eV) into the surface of the second level of via openings  228  and a second level of metal line trenches  230  in the second polymer layer  224  using a varying angle implant (∞), as shown by arrows  225  where the angle of implantation is changed from normal to the wafer surface to 15 degrees off normal. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation, ∞, is changed from normal to the wafer surface to approximately 15 degrees off normal deposits the barrier/adhesion layer  234  on all surfaces in the second level of via openings  228  and a second level of metal line trenches  230 . The structure is now as appears in  FIG. 2H . 
     FIG. 2I  illustrates the structure after the next sequence of processing steps. In  FIG. 2I , a second seed layer  236  is deposited on the second barrier/adhesion layer  234  using a low energy ion implantation. According to the broader teachings of the present invention, depositing the second seed layer  236  on the second barrier/adhesion layer  214  includes depositing a second seed layer  236  selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer  216  includes depositing a layer of an aluminum copper alloy  216  having a thickness of approximately 110 Å. This can be achieved by depositing a first layer of aluminum  284  on the barrier/adhesion layer  214  to a thickness of approximately 50 Å using a low energy ion implantation of approximately 100 electron volts (eV). A layer of copper  285  is then deposited on the first layer of aluminum  284  to a thickness of approximately 10 Å using a low energy ion implantation of approximately 100 eV. A second layer of aluminum  286  is then deposited on the layer of copper  285  to a thickness of approximately 50 Å using a low energy ion implantation of approximately 100 eV. Also the first seed layer  216  is implanted at an angle normal to the wafer&#39;s surface as shown by arrows  237 . As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper  236  at an angle normal to the planarized surface results in the second seed layer of copper  236  remaining on a bottom surface  238  in the second level of via openings  228  and to a much lesser extent on the side surfaces  240  of the second level of via openings  228  and a second level of metal line trenches  230 . 
     FIG. 2J  illustrates the structure following the next sequence of process steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer  226  has served as a blocking layer to define the implant areas for the second barrier/adhesion layer  234  and the second seed layer  236 . The residual photoresist layer  226  is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer  226  includes removing the unwanted barrier/adhesion layer  234  and the unwanted second seed layer  236 , from other areas of the wafer&#39;s surface, e.g. from over a number of regions  232  outside of second level of metal line trenches  230  on a top surface  242  of the second oxide layer  224 . The structure is now as shown in  FIG. 2J . 
   In  FIG. 2K , a second metallic conductor  244 , or second core conductor  244 , is deposited over or formed on the second seed layer  236  and within the second barrier/adhesion layer  234  in the second level of via openings  228  and the second level of metal line trenches  230  in the polymer layer. In this embodiment the second metallic conductor  244 , or second core conductor  244 , is aluminum, but in other embodiments of the present invention the second metallic conductor  244 , or second core conductor  244 , can be selected from the group consisting of copper, silver, and gold. In one embodiment, the second metallic conductor  244 , or second core conductor  244 , is deposited using a selective CVD process. In another embodiment, depositing a second metallic conductor  244 , or second core conductor  244 , over on the second seed layer  236  and within the second barrier/adhesion layer  234  includes depositing a second metallic conductor  244 , or second core conductor  244 , using electroless plating. The second aluminum conductor  244 , or second core conductor  244  is deposited to fill the second level of via openings  228  and the second level of metal line trenches  230  to the top surface  242  of the second insulator layer  224 . Thus, the second barrier/adhesion layer  234 , the second seed layer  236 , and the second metallic conductor  244 , or second core conductor  244 , constitute a second number of conductive structures which includes a number of second level vias and a number of second level metal lines which are formed over and connect to a first number of conductive structures, e.g. the first level of vias  207 A and  207 B. 
   Embodiment of a Metal Interconnect Using Copper Metal Lines and Oxide Insulators 
     FIGS. 3A-3K  illustrate a novel methodology for the formation of metal interconnects and/or a wiring structure in an integrated circuit according to the teachings of the present invention. The novel methodology includes the novel formation of a barrier/adhesion layer and a seed layer in an integrated circuit using a low energy ion implantation. The novel methodology also encompasses a novel method of making copper, silver, aluminum, or gold interconnect for an integrated circuit. 
     FIG. 3A  illustrates a portion of an integrated circuit structure, namely an integrated circuit having a number of semiconductor devices formed in a substrate.  FIG. 3  illustrates the structure after a device structure is formed in the substrate and the contact structure to the device structure is in place. One of ordinary skill in the art will understand upon reading this disclosure the manner in which a number of semiconductor structures, e.g. transistors, can be formed in a substrate. One of ordinary skill in the art will also understand upon reading this disclosure the manner in which a contact structure can be formed connecting to a given semiconductor device in a substrate, such as explained in connection with  FIG. 1A . For example,  FIG. 3A  illustrates the structure after a number of device structures, e.g. transistor  301 A and  301 B are formed in the substrate  300 . An insulator layer  302  is deposited over the number of semiconductors  301 A and  301 B. The deposition of the insulator layer  302  can include depositing a layer of Si 3 N 4  having a thickness in the range of 100 to 500 Angstroms (Å). This insulator layer will also serve as an additional barrier to impurities coming from subsequent processing steps. Contact holes  305 A and  305 B are opened to the number of device structures  301 A and  301 B using a photolithography technique. One of ordinary skill in the are will understand, upon reading this disclosure, the manner in which a photolithography technique can be used to create contact holes  305 A and  305 B. In one embodiment of the present invention a titanium silicide liner  306 A and  306 B is placed in the contact holes  305 A and  305 B, such a through a process such as chemical vapor deposition (CVD). Next, tungsten vias  306 A and  306 B can be deposited in the contact holes  305 A and  305 B. The tungsten vias  307 A and  307 B can be deposited in the contact holes using any suitable technique such as using a CVD process. The excess tungsten is then removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface  309 . 
   As shown in  FIG. 3B , a first polymer layer  308 , or first layer of polyimide  308 , is deposited over the wafer surface. The first oxide layer  308  may be deposited using any suitable technique such as, for example, a CVD process. In one embodiment, depositing a first oxide layer  308  includes depositing a fluorinated silicon oxide layer  308 . In one embodiment, the first oxide layer  308  is deposited to have a thickness of approximately 5000 Å. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the first oxide layer  308  may also be deposited as suited for forming a first level metal pattern, the invention is not so limited. The first oxide layer  308  is patterned to define a number of trenches  310  in the first oxide layer  308  opening to a number of first level vias, e.g. tungsten vias  307 A and  307 B in planarized surface  309 . In other words, a first level metal pattern  310  is defined in a mask layer of photoresist  312  and then the first oxide layer  308  is etched, using any suitable process, e.g. reactive ion etching (RIE), such that the first level metal pattern  310  is defined in the first oxide layer  308 . According to the teachings of the present invention, a residual photoresist layer  312  is left in place on the first oxide layer  308  in a number of region  313  outside of the number trenches  310 . The structure is now as appears in  FIG. 3B . 
   As shown in  FIG. 3C , a first barrier/adhesion layer  314  is deposited in the number of trenches  310  using a low energy ion implantation. In one embodiment according to the teachings of the present invention, depositing the barrier/adhesion layer  314  includes depositing a tantalum nitride layer  314  having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the barrier/adhesion layer  314  includes depositing a barrier/adhesion layer  314  of tantalum and/or CuTi. In one embodiment, depositing the tantalum nitride layer  314  includes first depositing a layer of tantalum  381  to have a thickness of approximately 100 Å using a low energy ion implantation of approximately 100 electron volts (eV) at a varying angle implant (∞), e.g. the angle of implantation (∞) is changed from normal to the planarized surface  309  to approximately 15 degrees off normal as shown by arrows  311 . In one embodiment, this is achieved using a 10 17  ion implant of tantalum. Next, according to the teachings of the present invention, a layer of nitrogen  382  is implanted at 700 electron volts (eV) into the layer of tantalum  381 . In one embodiment, this is achieved using an 8×10 16  ion implant of nitrogen. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation is changed from normal to the planarized surface  309  to approximately 15 degrees off normal deposits the barrier/adhesion layer  314  on all surfaces in the number of trenches  310 . The structure is now as appears in  FIG. 3C . 
   In  FIG. 3D , a first seed layer  316  is deposited on the first barrier/adhesion layer  314  using a low energy ion implantation. According to the broader teachings of the present invention, depositing the seed layer  316  on the barrier/adhesion layer  314  includes depositing a seed layer  316  selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer  316  includes depositing a layer of copper  316  having a thickness of approximately 50 Å. This can be achieved using an 8×10 16  ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper  316  at 100 electron volts (eV) into the first barrier/adhesion layer  314 . Also the layer of copper  316  is implanted at an angle normal to the planarized surface  309  as shown by arrows  315 . As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper  316  at an angle normal to the planarized surface results in the seed layer of copper  316  remaining on a bottom surface  318  in the number of trenches  310  and to a much lesser extent on the side surfaces  320  of the number of trenches  310 . In one embodiment, an optional layer of aluminum  321  is deposited over the copper seed layer  316  again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum  321  is deposited to have a thickness of approximately a 50 Å. This can be achieved using a 3×10 16  ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum  321  is used to protect the copper seed layer  316  from oxidation prior to subsequent processing steps. The structure is now as appears in  FIG. 3D . 
     FIG. 3E  illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer  312  has served as a blocking layer to define the implant areas for the barrier/adhesion layer  314 , the seed layer  316 , and the layer of aluminum  321 . The residual photoresist layer  312  is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer  312  includes removing the unwanted aluminum layer  321 , the unwanted seed layer  316 , and the unwanted barrier/adhesion layer  314  from other areas of the wafer&#39;s surface, e.g. from over a number of regions outside of the trenches  310  on a top surface  319  of the first insulator layer  308 . The structure is now as shown in  FIG. 3E . 
   In  FIG. 3F , a metallic conductor  320 , or number of first level metal lines  320 , is deposited over the seed layer  316  in the number of trenches  310 . According to teachings of the present embodiment, the metallic conductor  320 , or number of first level metal lines  320 , is copper. In one embodiment, the metallic conductor  320 , or number of first level metal lines  320 , is deposited using a selective CVD process. In another embodiment, depositing a metallic conductor  320 , or number of first level metal lines  320 , over the seed layer  316  includes depositing a metallic conductor  320  using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the number of trenches  310  to a level approximately 100 Å below the top surface  319  of the first oxide layer  308 . At this point, a second layer of tantalum nitride  323  is deposited to a thickness of approximately 100 Å on the copper metallic conductor  320 , or number of first level copper lines  320 . A chemical mechanical planarization (CMP) cleanup process is then used to remove the tantalum nitride from the top surface  319  of the first oxide layer  308 . 
   As shown in  FIG. 3G , the process sequence may be continued to form any number of subsequent metal layers in a multilayer wiring structure.  FIG. 3G  illustrates the structure after the next sequence of processing steps. In  FIG. 3G , a dual damascene process is used to define and fill a first to a second level of vias and a second level metallurgy. To do so, a second oxide layer  324  is deposited over the wafer surface, e.g. the metallic conductor  320 , or number of first level metal lines  320 , and the first oxide layer  308 . The second oxide layer  324  is again deposited using any suitable technique. In one embodiment, depositing a second oxide layer  324  includes depositing a fluorinated silicon oxide layer  324 . In one embodiment, the second oxide layer  324  is deposited to have a thickness of approximately 10,000 Å. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the second oxide layer  324  may also be deposited as suited for forming a first to a second level of vias, e.g. second level vias, and a number of second level metal lines, the invention is not so limited. The second oxide layer  324  is patterned to define a second level of vias and a number of second level metal lines in the second oxide layer  324  opening to the metallic conductor  320 , or number of first level metal lines  320 . In other words, a second level of vias is defined in a second mask layer of photoresist  326  and then the second oxide layer  324  is etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of via openings  328  are defined in the second oxide layer  324 . Using the dual damascene process, a number of second level metal lines are also defined in a second mask layer of photoresist  326  and the second oxide layer  324  is again etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of metal line trenches  330  are defined in the oxide. One of ordinary skill in the art will understand upon reading this disclosure, the manner in which a photoresist layer  326  can be mask, exposed, and developed using a dual damascene process to pattern a second level of via openings  328  and a second level of metal line trenches  330  in the second oxide layer  324 . 
   As described previously, and according to the teachings of the present invention, a residual photoresist layer  326  is left in place on the second oxide layer  324  in a number of regions  332  outside of the second level of metal line trenches  330 . A suitable plasma and/or wet cleaning process is used to remove any contaminates from the second level of via openings  328  and a second level of metal line trenches  330 , as the same will be understood by one of ordinary skill in the art upon reading this disclosure. The structure is now as appears in  FIG. 3G . 
     FIG. 3H  illustrates the structure after the next sequence of processing steps. In  FIG. 3H , a second barrier/adhesion layer  334  is deposited in the second level of via openings  328  and a second level of metal line trenches  330  using a low energy ion implantation. As described above, in one embodiment according to the teachings of the present invention, depositing the second barrier/adhesion layer  334  includes depositing a tantalum nitride layer  334  having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the second barrier/adhesion layer  334  includes depositing a second barrier/adhesion layer  334  of tantalum and/or CuTi. In one embodiment, depositing the tantalum nitride layer  334  includes first depositing a layer of tantalum  383  to have a thickness of approximately 100 Å using a low energy ion implantation of approximately 100 electron volts (eV) at a varying angle implant (∞), e.g. the angle of implantation (∞) is changed from normal to the wafer&#39;s surface to approximately 15 degrees off normal as shown by arrows  325 . In one embodiment, this is achieved using a 10 17  ion implant of tantalum. Next, according to the teachings of the present invention, a layer of nitrogen  384  is implanted at 700 electron volts (eV) into the layer of tantalum  383 . In one embodiment, this is achieved using an 8×10 16  ion implant of nitrogen. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant (∞), where an angle of implantation is changed from normal to the wafer&#39;s surface to approximately 15 degrees off normal deposits the second barrier/adhesion layer  334  on all surfaces in the second level of via openings  328  and in the second level of metal line trenches  330  formed in the second oxide layer  324 . The structure is now as appears in  FIG. 3H . 
     FIG. 3I  illustrates the structure after the next sequence of processing steps. In  FIG. 3I , a second seed layer  336  is deposited on the second barrier/adhesion layer  334  using a low energy ion implantation. According to the broader teachings of the present invention, depositing the second seed layer  336  on the second barrier/adhesion layer  314  includes depositing a second seed layer  336  selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the second seed layer  336  includes depositing a second layer of copper  336  having a thickness of approximately 50 Å. In one embodiment, this is achieved using an 8×10 16  ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper  336  at 100 electron volts (eV) into the surfaces of the second level of via openings  328  and the second level of metal line trenches  330  in the polymer layer. Also the layer of copper  336  is implanted at an angle normal to the wafer&#39;s surface as shown by arrows  337 . As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper  336  at an angle normal to the wafer&#39;s surface results in the second seed layer of copper  336  remaining on a bottom surface  338  in the second level of via openings  328  and to a much lesser extent on the side surfaces  340  of the second level of via openings  328  and a second level of metal line trenches  330 . In one embodiment, an optional layer of aluminum  341  is deposited over the second copper seed layer  336  again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum is deposited to have a thickness of approximately a 50 Å. In one embodiment, this is achieved using a 3×10 16  ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum  341  is used to protect the second copper seed layer  336  from oxidation prior to subsequent processing steps. The structure is now as shown in  FIG. 3I . 
     FIG. 3J  illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer  326  has served as a blocking layer to define the implant areas for the second barrier/adhesion layer  334 , the second seed layer  336 , and the aluminum layer  341 . The residual photoresist layer  326  is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer  326  includes removing the unwanted aluminum layer  341 , the unwanted seed layer  336 , and the unwanted barrier/adhesion layer  334  from other areas of the wafer&#39;s surface, e.g. from over a number of regions  332  outside of second level of metal line trenches  330  on a top surface  342  of the second insulator layer  324 . The structure is now as shown in  FIG. 3J . 
   In  FIG. 3K , a second metallic conductor  344 , or second core conductor  344 , is deposited over or formed on the second seed layer  336  and within the second barrier/adhesion layer  334  in the second level of via openings  328  and the second level of metal line trenches  330  in the polymer layer. In this embodiment the second metallic conductor  344 , or second core conductor  344 , is copper, but in other embodiments of the present invention the second metallic conductor  344 , or second core conductor  344 , can be selected from the group consisting of aluminum, silver, and gold. In one embodiment, the second metallic conductor  344 , or second core conductor  344 , is deposited using a selective CVD process. In another embodiment, depositing a second metallic conductor  344 , or second core conductor  344 , over on the second seed layer  336  and within the second barrier/adhesion layer  334  includes depositing a second metallic conductor  344 , or second core conductor  344 , using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the second level of via openings  328  and the second level of metal line trenches  330  to level approximately 100 Å below the top surface  342  of the second insulator layer  324 . At this point, a second layer of tantalum nitride  346  is deposited to a thickness of approximately 100 Å on the second metallic conductor  344 , or second core conductor  344 . A chemical mechanical planarization (CMP) cleanup process is then used to remove the tantalum nitride from the top surface  342  of the second insulator layer  324 . Thus, the second barrier/adhesion layer  334 , the second seed layer  336 , and the second metallic conductor  344 , or second core conductor  344 , constitute a second number of conductive structures which includes a number of second level vias and a number of second level metal lines which are formed over and connect to a first number of conductive structures, e.g. the metallic conductor  320 , or number of first level metal lines  320 . 
   Another Embodiment of a Metal Interconnect Using Copper 
     FIGS. 4A-4L  illustrate a novel methodology for the formation of metal interconnects and/or a wiring structure in an integrated circuit according to the teachings of the present invention. The novel methodology includes the novel formation of a barrier/adhesion layer and a seed layer in an integrated circuit using a low energy ion implantation. The novel methodology also encompasses a novel method of making copper, silver, aluminum, or gold interconnect for an integrated circuit. 
     FIG. 4A  illustrates a portion of an integrated circuit structure, namely an integrated circuit having a number of semiconductor devices formed in a substrate.  FIG. 4A  illustrates the structure after a device structure is formed in the substrate and the contact structure to the device structure is in place. One of ordinary skill in the art will understand upon reading this disclosure the manner in which a number of semiconductor structures, e.g. transistors, can be formed in a substrate. One of ordinary skill in the art will also understand upon reading this disclosure the manner in which a contact structure can be formed connecting to a given semiconductor device in a substrate, such as described in connection with  FIG. 1A . For example,  FIG. 4A  illustrates the structure after a number of device structures, e.g. transistor  401 A and  401 B are formed in the substrate  400 . An insulator layer  402  is deposited over the number of semiconductors  401 A and  401 B. The deposition of the insulator layer  402  can include depositing a layer of Si 3 N 4  having a thickness in the range of 100 to 500 Angstroms (Å). This insulator layer will also serve as an additional barrier to impurities coming from subsequent processing steps. Contact holes  405 A and  405 B are opened to the number of device structures  401 A and  401 B using a photolithography technique. One of ordinary skill in the are will understand, upon reading this disclosure, the manner in which a photolithography technique can be used to create contact holes  405 A and  405 B. In one embodiment of the present invention a titanium silicide liner  406 A and  406 B is placed in the contact holes  405 A and  405 B, such a through a process such as chemical vapor deposition (CVD). Next, tungsten vias  407 A and  407 B can be deposited in the contact holes  405 A and  405 B. The tungsten vias  407 A and  407 B can be deposited in the contact holes using any suitable technique such as using a CVD process. The excess tungsten is then removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface  409 . 
   As shown in  FIG. 4B , a first polymer layer  408 , or first layer of polyimide  408 , is deposited over the wafer surface. The first polymer layer  408  may be deposited using, for example, the process and material described in co-pending and commonly assigned application U.S. Ser. No. 09/128,859, entitled “Copper Metallurgy in Integrated Circuits,” which is hereby incorporated by reference. In one embodiment, depositing a first polymer layer  408  includes depositing a foamed polymer layer  408 . In one embodiment, the first layer of polyimide  408  is deposited and cured, forming a 5000 Å thick layer of polymer  408  after curing. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the first layer of polyimide  408 , or insulator layer/material  408 , may also be deposited as suited for forming a first level metal pattern, the invention is not so limited. The first layer of polyimide  408 , or first insulator layer/material  408  is patterned to define a number of trenches  410  in the first insulator layer  408  opening to a number of first level vias, e.g. tungsten vias  407 A and  407 B in planarized surface  409 . In other words, a first level metal pattern  410  is defined in a mask layer of photoresist  412  and then the first layer of polyimide  408  is etched, using any suitable process, e.g. reactive ion etching (RIE), such that the first level metal pattern  410  is defined in the polyimide. According to the teachings of the present invention, a residual photoresist layer  412  is left in place on the first insulator layer  408  in a number of region  413  outside of the number trenches  410 . The structure is now as appears in  FIG. 4B . 
   As shown in  FIG. 4C , a first barrier/adhesion layer  414  is deposited in the number of trenches  410  using a low energy ion implantation. In one embodiment according to the teachings of the present invention, depositing the barrier/adhesion layer  414  includes depositing a layer of zirconium  414  having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the barrier/adhesion layer  414  includes depositing a barrier/adhesion layer  414  of titanium and/or hafnium. In one embodiment, depositing the depositing a layer of zirconium  414  includes depositing a layer of zirconium  414  having a thickness of approximately 15 Å. This can be achieved using a 10 17  ion implant of zirconium. According to the teachings of the present invention, the layer of zirconium  414  is implanted at 100 electron volts (eV) into the surface of the trenches  410  in the polymer layer  408  using an angle of implant normal to the wafer&#39;s surface as shown by arrows  411 . The structure is now as appears in  FIG. 4C . 
   In  FIG. 4D , a first seed layer  416  is deposited on the first barrier/adhesion layer  414  using a low energy ion implantation. According to the broader teachings of the present invention, depositing the seed layer  416  on the barrier/adhesion layer  414  includes depositing a seed layer  416  selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer  416  includes depositing a layer of copper  416  having a thickness of approximately a 50 Å. This can be achieved using an 8×10 16  ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper  416  at 100 electron volts (eV) into the surface of the trenches  410  in the polymer layer. Also the layer of copper  416  is implanted at an angle normal to the wafer&#39;s surface as shown by arrows  415 . As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper  416  at an angle normal to the wafer&#39;s surface results in the seed layer of copper  416  remaining on a bottom surface  418  in the number of trenches  410  and to a much lesser extent on the side surfaces  420  of the number of trenches  410 . In one embodiment, an optional layer of aluminum  421  is deposited over the copper seed layer  416  again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum  421  is deposited to have a thickness of approximately a 50 Å. This can be achieved using a 3×10 16  ion implant of aluminum normal to the wafer surface as shown by arrows  415 . As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum  421  is used to protect the copper seed layer  416  from oxidation prior to subsequent processing steps. The structure is now as appears in  FIG. 4D . 
     FIG. 4E  illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer  412  has served as a blocking layer to define the implant areas for the barrier/adhesion layer  414 , the seed layer  416 , and the layer of aluminum  421 . The residual photoresist layer  412  is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer  412  includes removing the unwanted aluminum layer  421 , the unwanted seed layer  416 , and the unwanted barrier/adhesion layer  414  from other areas of the wafer&#39;s surface, e.g. from over a number of regions  413  outside of the trenches  410  on a top surface  419  of the first insulator layer  408 . The structure is now as shown in  FIG. 4E . 
   In  FIG. 4F , a metallic conductor  420 , or number of first level metal lines  420 , is deposited over the seed layer  416  in the number of trenches  410 . According to teachings of the metallic conductor  420 , or number of first level metal lines  420 , is selected from the group consisting of aluminum, copper, silver, and gold depending on the type of seed layer  416  which was deposited. According to this embodiment, a number of copper metal lines  420 , or first level copper metal lines  420  are selectively formed on the copper seed layer  416 . In one embodiment, the metallic conductor  420 , or number of first level metal lines  420 , is deposited using a selective CVD process. In another embodiment, depositing a metallic conductor  420 , or number of first level metal lines  420 , over the seed layer  416  includes depositing a metallic conductor  420  using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the number of trenches  410  to the top surface  419  of the first insulator layer  408 . 
   As shown in  FIG. 4G , the process sequence may be continued to form any number of subsequent metal layers in a multilayer wiring structure.  FIG. 4G  illustrates the structure after the next sequence of processing steps. In  FIG. 4G , a dual damascene process is used to define and fill a first to a second level of vias and a second level metallurgy. To do so, a second polymer layer  424 , or second layer of polyimide  424 , is deposited over the wafer surface, e.g. the metallic conductor  420 , or number of first level metal lines  420 , and the first polymer layer  408 . The second polymer layer  424  may similarly be deposited using, for example, the process and material described in co-pending and commonly assigned application U.S. Ser. No. 09/128,859, entitled “Copper Metallurgy in Integrated Circuits,” which is hereby incorporated by reference. In one embodiment, depositing a second polymer layer  424  includes depositing a foamed second polymer layer  424 . In one embodiment, the second polymer layer  424  is deposited and cured, forming a 10,000 Å thick second polymer layer  424  after curing. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the second polymer layer  424 , or second insulator layer/material  424 , may also be deposited as suited for forming a first to a second level of vias, e.g. second level vias, and a number of second level metal lines, the invention is not so limited. The second polymer layer  424 , or second insulator layer/material  424  is patterned to define a second level of vias and a number of second level metal lines in the second insulator layer/material  424  opening to the metallic conductor  420 , or number of first level metal lines  420 . In other words, a second level of vias is defined in a second mask layer of photoresist  426  and then the second polymer layer  424  is etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of via openings  428  are defined in the polyimide. Using the dual damascene process, a number of second level metal lines are also defined in a second mask layer of photoresist  426  and the second polymer layer  424  is again etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of metal line trenches  430  are defined in the polyimide. One of ordinary skill in the art will understand upon reading this disclosure, the manner in which a photoresist layer  426  can be mask, exposed, and developed using a dual damascene process to pattern a second level of via openings  428  and a second level of metal line trenches  430  in the second insulator layer/material  424 . 
   As described previously, and according to the teachings of the present invention, a residual photoresist layer  426  is left in place on the second insulator layer/material  424  in a number of regions  432  outside of the second level of metal line trenches  430 . A suitable plasma and/or wet cleaning process is used to remove any contaminates from the second level of via openings  428  and a second level of metal line trenches  430 , as the same will be understood by one of ordinary skill in the art upon reading this disclosure. The structure is now as appears in  FIG. 4G . 
     FIG. 4H  illustrates the structure after the next sequence of processing steps. In  FIG. 4H , a second barrier/adhesion layer  434  is deposited in the second level of via openings  428  and a second level of metal line trenches  430  using a low energy ion implantation. As described above, in one embodiment according to the teachings of the present invention, depositing the second barrier/adhesion layer  434  includes depositing a layer of zirconium  434  having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the second barrier/adhesion layer  434  includes depositing a barrier/adhesion layer  434  of titanium and/or hafnium. In one embodiment, depositing the layer of zirconium  434  includes depositing a layer of zirconium  434  having a thickness of approximately 15 Å. In one embodiment, this is achieved using a 10 17  ion implant of zirconium. According to the teachings of the present invention, the layer of zirconium  434  is implanted at 100 electron volts (eV) into the surface of the second level of via openings  428  and a second level of metal line trenches  430  in the second polymer layer  424  using an implant angle normal to the wafer&#39;s surface as shown by arrows  425 . The structure is now as appears in  FIG. 4H . 
     FIG. 4I  illustrates the structure after the next sequence of processing steps. In  FIG. 4I , a second seed layer  436  is deposited on the second barrier/adhesion layer  434  using a low energy ion implantation. According to the broader teachings of the present invention, depositing the second seed layer  436  on the second barrier/adhesion layer  414  includes depositing a second seed layer  436  selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the second seed layer  436  includes depositing a second layer of copper  436  having a thickness of approximately a 50 Å. In one embodiment, this is achieved using an 8×10 16  ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper  436  at 100 electron volts (eV) into the second level of via openings  428  and the second level of metal line trenches  430  in the polymer layer. Also the layer of copper  436  is implanted at an angle normal to the wafer&#39;s surface as shown by arrows  437 . As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper  436  at an angle normal to the wafer&#39;s surface results in the second seed layer of copper  436  remaining on a bottom surface  438  in the second level of via openings  428  and to a much lesser extent on the side surfaces  440  of the second level of via openings  428  and a second level of metal line trenches  430 . In one embodiment, an optional layer of aluminum  441  is deposited over the second copper seed layer  436  again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum is deposited to have a thickness of approximately a 50 Å. In one embodiment, this is achieved using a 3×10 16  ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum  441  is used to protect the second copper seed layer  436  from oxidation prior to subsequent processing steps. The structure is now as appears in  FIG. 4I . 
     FIG. 4J  illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer  426  has served as a blocking layer to define the implant areas for the second barrier/adhesion layer  434 , the second seed layer  436 , and the aluminum layer  441 . The residual photoresist layer  426  is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer  426  includes removing the unwanted aluminum layer  441 , the unwanted seed layer  436 , and the unwanted barrier/adhesion layer  434  from other areas of the wafer&#39;s surface, e.g. from over a number of regions  432  outside of second level of metal line trenches  430  on a top surface  442  of the second insulator layer  424 . The structure is now as shown in  FIG. 4J . 
   In  FIG. 4K , a second metallic conductor  444 , or second core conductor  444 , is deposited over or formed on the second seed layer  436  and within the second barrier/adhesion layer  434  in the second level of via openings  428  and the second level of metal line trenches  430  in the polymer layer. In this embodiment the second metallic conductor  444 , or second core conductor  444 , is copper, but in other embodiments of the present invention the second metallic conductor  444 , or second core conductor  444 , can be selected from the group consisting of aluminum, silver, and gold. In one embodiment, the second metallic conductor  444 , or second core conductor  444 , is deposited using a selective CVD process. In another embodiment, depositing a second metallic conductor  444 , or second core conductor  444 , over on the second seed layer  436  and within the second barrier/adhesion layer  434  includes depositing a second metallic conductor  444 , or second core conductor  444 , using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the second level of via openings  428  and the second level of metal line trenches  430  to the top surface  442  of the second insulator layer  424 . Thus, the second barrier/adhesion layer  434 , the second seed layer  436 , and the second metallic conductor  444 , or second core conductor  444 , constitute a second number of conductive structures which includes a number of second level vias and a number of second level metal lines which are formed over and connect to a first number of conductive structures, e.g. the metallic conductor  420 , or number of first level metal lines  420 . 
   As one of ordinary skill in the art will understand upon reading this disclosure, the above described method embodiments can be repeated until the requisite number of metal layers are formed. 
     FIG. 4L  illustrates the structure following the final sequence of processing steps. Upon completion of the last level of metal, the entire polymer structure, e.g. first polymer layer  408  and second polymer layer  424 , are removed using an O 2  plasma etch. The structure is now as appears in  FIG. 4L . 
     FIG. 5 , is an illustration of an embodiment of an integrated circuit formed according to the teachings of the present invention. As shown in  FIG. 5 , the integrated circuit includes a metal layer in an integrated circuit. The metal layer  FIG. 5 , is an illustration of an embodiment of an integrated circuit  503  formed according to the teachings of the present invention. As shown in  FIG. 5 , the integrated circuit  503  includes a metal layer in an integrated circuit. The metal layer includes a number of first level vias  507 A and  507 B connecting to a number of silicon devices  501 A and  501 B in a substrate  500 . A number of first level metal lines  520  are formed above and connect to the number of first level vias  507 A and  507 B. A barrier/adhesion layer  514  having a thickness in the range of 5 to 150 Angstroms is formed on the number of first level vias  507 A and  507 B. A seed layer  516  having a thickness in the range of 5 to 150 Angstroms is formed at least between a portion of the barrier/adhesion layer  514  and the number of first level metal lines  520 . As described above the barrier adhesion layer  514  having a thickness in the range of 5 to 150 Angstroms includes a barrier/adhesion layer selected from the group consisting of titanium, zirconium, and hafnium. In one embodiment, as shown in  FIG. 5 , the number of first level vias  507 A and  507 B connecting to a number of silicon devices  501 A and  501 B in substrate  500  are surrounded by an insulator layer  502 . 
   As described above the number of first level metal lines is selected from the group consisting of Aluminum, Copper, Silver, and Gold. In one embodiment, the integrated circuit  503  comprises a portion of an integrated memory circuit  503 . In this embodiment, the number of silicon devices  501 A and  501 B includes one or more transistors  501 A and  501 B in the substrate  500 . 
   As one of ordinary skill in the art will understand upon reading this disclosure, any one of the embodiments as shown in  FIGS. 1K ,  2 K,  3 K, and/or  4 L can comprise a portion of an integrated circuit according to the teachings of the present invention. 
     FIG. 6  illustrates an embodiment of a system  600  including a portion of an integrated circuit formed according to any of the embodiments described in the present application. As one of ordinary skill in the art will understand upon reading this disclosure, this system  600  includes a processor  610  and an integrated circuit, or integrated memory circuit  630  coupled to the processor  610 . The processor  610  can be coupled to the integrated memory circuit  630  via any suitable bus, as the same are known and understood by one of ordinary skill in the art. In the embodiment, the processor  610  and integrated circuit  630  are located on a single wafer or die. Again, at least a portion of the integrated circuit  630  includes a portion of an integrated circuit  603  as disclosed in the various embodiments provided herein. 
   CONCLUSION 
   Thus, structures and methods have been provided which improve the performance of integrated circuits according to shrinking design rules. The structures and methods include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. According to the teachings of the present invention, the selective deposition of the metal lines avoids the need for multiple chemical mechanical planarization (CMP) steps. The low energy ion implantation of the present invention allows for the distinct placement of both the diffusion barrier and the seed layer. A residual resist can be used to remove the diffusion barrier and the seed layer from unwanted areas on a wafer surface. The structures formed by the described novel processes accommodate aluminum, copper, gold, and silver metal interconnects. 
   Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.