Abstract:
A non-linear correction current ICTAT 2  (current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between transistor collector current and base-emitter voltage. The resulting ICTAT 2  current (current complementary to the square of absolute temperature) is injected into a node of a bandgap reference circuit to compensate for non-linear temperature effects on output voltage. A more general correction circuit generates both IPTAT 2  and ICTAT 2 , and applies each to a respective multiplier which, in a preferred embodiment, is a current DAC configured as a multiplier. Control inputs CTL 1  and CTL 2  to respective multipliers set the amplitudes of the modified IPTAT 2  and ICTAT 2  output currents, which are then summed to generate the compensating current Icomp which is injected to the appropriate node in the bandgap reference circuit as described above. By adjusting the relative amplitudes of the IPTAT 2  and ICTAT 2  currents, a wide range of compensating current versus voltage curves is produced, allowing the optimization of a wide range of bandgap reference circuits. An optimal value for CTL 1  is determined by holding CTL 2  constant, then measuring curvature at a plurality of CTL 1  values. That CTL 1  value closest to the interpolated value at which curvature is minimized is then used.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates generally to temperature compensation of bandgap voltage references, and more specifically to correction of non-linear output voltage versus temperature errors by generating and applying a correction signal or a superposition of a plurality of correction signals having a second or higher order relationship to temperature, proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT). 
         [0003]    2. Description of the Related Art 
         [0004]    Bandgap references such as that using a Brokaw architecture typically generate an output voltage which is the sum of 1) the voltage drop across a semiconductor junction, having a temperature coefficient complementary to absolute temperature (CTAT), and 2) a voltage having a temperature coefficient proportional to absolute temperature (PTAT); wherein the temperature coefficients of the CTAT and PTAT voltages have approximately the same magnitude but opposite sign. The resulting output voltage is thus relatively stable over a wide range of temperature, since the positive and negative temperature coefficients of the summed voltages cancel. There remains, however, a residual temperature effect on voltage which, in theory, introduces an increasingly negative error as temperature varies either above or below the nominal operating temperature (Tn). Theory predicts second and higher order effects, but terms higher than second order are quite small. The theoretical equation has a T*ln(T) term, and the second order correction compensates for the parabolic term of the Taylor expansion of this T*ln(T) dependency. The resulting voltage versus temperature curve appears to have primarily a parabolic curvature. 
         [0005]    Correction circuits have been developed which typically generate a current proportional to the square of temperature, which, when injected at an appropriate node in the bandgap reference circuit, acts to decrease the output voltage error. The current typically generated is PTAT 2  (IPTAT 2 ) which increases as the square of temperature. This current is injected into a node of the bandgap reference circuit, generating a correction voltage. When the resulting correction voltage is added to the parabolic uncompensated output voltage, the parabolic curve thus becomes more S-shaped, reducing the output voltage error over a given temperature span. 
         [0006]    In some actual integrated bandgap reference circuits, however, the uncompensated voltage versus temperature relationship is not the parabolic curve predicted by theory. Differences in processes, structures, and other variables lead, in many cases, to a voltage having little error above a nominal temperature, but pronounced curvature (voltage error increasing as the square of change in temperature) as temperature decreases from nominal. Applying known compensation to such circuits has a smaller than desired effect on error below Tn, and may increase rather than reduce the error above Tn. 
         [0007]    A circuit which will correct the output voltage of a bandgap reference circuit over a wide temperature range is therefore desirable, providing correction in the temperature region or regions needing such correction, in whichever direction is required, and without introducing additional error in a temperature region not needing correction. 
       SUMMARY OF THE INVENTION 
       [0008]    The invention provides a method and apparatus for generating a correction current in a bandgap reference circuit, wherein the correction current is, in one embodiment, small at some nominal temperature Tn, increasing in a non-linear or 1/T manner as temperature decreases below Tn. This correction current is generated in a circuit having a known architecture which has as inputs both a PTAT current and a CTAT current. Whereas in the prior art such currents in this architecture result in a current PTAT 2  (which will also be referred to herein as IPTAT 2 ), in the embodiment to be described, a CTAT correction current (ICTAT 2 ) is generated by reversing the PTAT and CTAT inputs to the same circuit topology. The resulting correction current is injected to a node in the bandgap reference circuit which converts the current into a corresponding voltage correction. This correction current has little effect on output voltage above a nominal temperature, while providing increasing correction as temperature decreases from nominal. 
         [0009]    Another embodiment generates both a IPTAT 2  current, increasing as a square or higher order function of increasing temperature, and a ICTAT 2  current, increasing as a square or higher order function of decreasing temperature. Control signals are applied to two multipliers, one having IPTAT 2  as an input, the other having ICTAT 2  as an input. The outputs of these multipliers are summed, and the resulting current is applied to an appropriate node in the bandgap reference circuit to effect the desired correction of output voltage. By modifying the control signal to each multiplier and thereby adjusting the gain of each multiplier, the relative amounts of ICTAT 2  and IPTAT 2  currents are adjusted to optimize correction. 
         [0010]    As further described below, the disclosed embodiments provide a combination of desirable properties not available in the known art. Further benefits and advantages will become apparent to those skilled in the art to which the invention relates. 
     
    
     
       DESCRIPTION OF THE VIEWS OF THE DRAWINGS 
         [0011]      FIG. 1  (prior art) is a block diagram of a typical Brokaw bandgap reference 
           [0012]      FIG. 2  is a graph showing the theoretical and actual uncompensated output voltages of a bandgap reference circuit. 
           [0013]      FIG. 3  is a block diagram of a circuit which generates IPTAT 2  and one which generates ICTAT 2 , and graphs of the respective voltage versus temperature compensation each provides. 
           [0014]      FIG. 4  is a block diagram of a correction circuit generating both IPTAT 2  and ICTAT 2  currents, controlling the relative amplitudes of each, and summing the resulting currents, so as to provide an adjustable, generalized correction. 
           [0015]      FIG. 5  is a graph of the curvature (output voltage change over temperature) for a plurality of values of CTL 1  of the circuit described in  FIG. 4 , showing an optimal value of CTL 1  which minimizes curvature. 
           [0016]      FIG. 6  is a flow chart describing a method for determining that optimal value of CTL 1  in the circuit of  FIG. 4 . 
           [0017]      FIG. 7  is a flow chart describing another method for determining that optimal value of CTL 1  in the circuit of  FIG. 4 . 
       
    
    
       [0018]    Throughout the drawings, like elements are referred to by like numerals. 
       DETAILED DESCRIPTION 
       [0019]    In  FIG. 1  (prior art), the output of amplifier  110  is coupled to a first terminal of resistors  102  and  104  and to output terminal  118 . The second terminal of resistor  102  is coupled to the non-inverting input of amplifier  110  and to the collector and base of transistor  106 . The second terminal of resistor  104  is coupled to the inverting input of amplifier  110  and to a first terminal of resistor  112 . The second terminal of resistor  112  is coupled to the collector and base of transistor  108 . The emitters of both transistor  106  and transistor  108  are coupled together, and are coupled to the first terminal of resistor  114 , terminal  120 , and current source  116 . The second terminal of  114  is coupled to ground. 
         [0020]    In operation, because resistor  102  and resistor  104  are substantially equal, when equal currents flow through both resistors the voltage drops across them are substantially equal. Since the currents flowing into the inputs of amplifier  110  are typically negligible, the current in transistor  106  is substantially equal to the current in transistor  108 . The junction area of transistor  108  is larger than the junction area of transistor  106 . Because of this difference in current density in these transistors, when substantially equal currents flow through them, the voltage drop across the base-emitter junction of the larger junction in transistor  108  is less than the voltage drop across the base-emitter junction of transistor  106 . As described in the literature, the theoretical difference in voltage drop is deltaVbe=(kT/q)ln(J 1 /J 2 ), where J 1  and J 2  are the current densities of transistor  106  and transistor  108  respectively. This deltaVbe is proportional to absolute temperature, commonly referred to as PTAT. With equal currents in both transistors and with the inputs to amplifier  110  substantially equal, the voltage deltaVbe, with PTAT characteristic, appears across resistor  112 . The current flowing through resistor  112  thus also has a PTAT characteristic, but with a temperature coefficient significantly less than the negative temperature coefficient of the voltage drop across the base emitter junction of transistor  108 . Since negligible current flows into the inputs of amplifier  110 , the PTAT current through resistor  112  is substantially the same as the current through resistor  104 . By selecting the value of resistor  104 , the PTAT temperature coefficient of the voltage drop across the series combination of resistor  112  and resistor  104  is made substantially the same as the CTAT temperature coefficient of the base emitter junction of transistor  108 . The output of amplifier  110  is thus a reference voltage of approximately 1.2 volts, which is substantially constant over a wide temperature range. 
         [0021]    In  FIG. 2 , the predominant second order temperature versus voltage characteristic of a theoretical bandgap reference circuit of  FIG. 1  is shown by curve  202  (higher order temperature effects on voltage are assumed small and therefore are ignored in this case). The temperature versus voltage characteristic of a representative actual bandgap reference circuit is shown by curve  204 . Prior art compensation circuits typically generate a current IPTAT 2 , which increases with the square of temperature. While this IPTAT 2  compensation is appropriate given a bandgap reference having the characteristic of curve  202 , it is inappropriate for that bandgap reference circuit having the characteristic of curve  204 . It is desirable to compensate the actual curve  204  with a voltage which increases in a non-linear manner as temperature decreases rather than increases. 
         [0022]    In  FIG. 3A , a known circuit for generating current IPTAT 2  is shown. The topology described in  FIG. 3  utilizes bipolar transistors having a control terminal which is a base, a first current terminal which is an emitter, and a second current terminal which is a collector. Transistor  302  has its emitter coupled to ground, its collector coupled to its base, to the base of transistor  304 , and to the emitter of transistor  306 . The base of transistor  306  is coupled to the collector of transistor  306 , to the second terminal of current source  312  and to the base of transistor  308 . The first terminal of current source  312  is coupled to the collector of transistor  308  and the supply voltage. The emitter of transistor  308  is coupled to the collector of transistor  304 , the first terminal of current source  314 , and the base of transistor  310 . The second terminal of current source  314  is coupled to ground, as are the emitters of transistor  304  and transistor  310 . The collector of transistor  310  is coupled to output terminal  316 . 
         [0023]    In operation, the topology of the circuit of  FIG. 3A , when current IPTAT and current ICTAT are coupled as shown, results in a current IPTAT 2  at output terminal  316  which is proportional to the square of temperature and increases with increasing absolute temperature as shown in graph  320  of  FIG. 3B . The operation of the circuit of  FIG. 3A  is known and described in the literature. In this circuit, a PTAT current and a first-order temperature-stable current is used in a base-emitter loop to produce the desired IPTAT 2  current. Summing a CTAT and a PTAT current generates the temperature-independent current. The intrinsic voltage loop is composed of transistors  302 ,  306 ,  310 ,  308 . The resulting output current is derived by summing the voltages in the loop (applying Kirchhoffs Voltage Law) as shown in the following equation: 
         [0000]        V   BE (302)− V   BE (306)= V   BE (310)− V   BE (308). 
         [0000]    In the following, the definitions I C ( 310 )=I OUT  and I C ( 306 )=I C ( 302 )=I C ( 304 )=I PTAT  as well as I C ( 308 )=I PTAT +I CTAT  will be used, and—to simplify calculations—it is assumed that transistors  302 ,  304 ,  306 ,  308  and  310  have the same emitter area A.
 
Then, substituting equation
 
         [0000]    
       
         
           
             
               V 
               BE 
             
             = 
             
               
                 V 
                 T 
               
                
               
                 ln 
                  
                 
                   ( 
                   
                     
                       I 
                       C 
                     
                     
                       
                         I 
                         S 
                       
                       · 
                       A 
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    for each base-emitter voltage, where V T , A, and I S  are constants, yields 
         [0000]    
       
         
           
             
               ln 
                
               
                 [ 
                 
                   
                     
                       I 
                       out 
                     
                     · 
                     
                       ( 
                       
                         IPTAT 
                         + 
                         ICTAT 
                       
                       ) 
                     
                   
                   
                     IPTAT 
                     + 
                     IPTAT 
                   
                 
                 ] 
               
             
             = 
             0 
           
         
       
       
         
           
             o 
              
             r 
           
         
       
       
         
           
             
               I 
               OUT 
             
             = 
             
               
                 
                   IPTAT 
                   2 
                 
                 
                   ( 
                   
                     IPTAT 
                     + 
                     ICTAT 
                   
                   ) 
                 
               
               ≈ 
               
                 
                   IPTAT 
                   2 
                 
                 K 
               
               ≡ 
               
                 IPTAT 
                  
                 
                     
                 
                  
                 2 
               
             
           
         
       
     
         [0000]    where K is substantially constant. Another embodiment of the prior art circuit uses MOSFET transistors for transistors  306  and  308 . The MOS devices, however, must operate in the subthreshold (weak inversion) region. This requirement arises because the drain current is exponentially dependent on the gate-source voltage only in subthreshold, which is the characteristic exploited by the circuit topology. In this case, 
         [0000]    
       
         
           
             
               V 
               GS 
             
             = 
             
               
                 V 
                 T 
               
                
               
                 ln 
                  
                 
                   ( 
                   
                     
                       I 
                       DS 
                     
                     
                       c 
                       · 
                       
                         W 
                         / 
                         L 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    holds—where V T  and c are constant and W/L is the aspect ration of the MOS device—and the calculation can be carried out in a similar manner as shown above. 
         [0024]    In  FIG. 3C , the circuit of  FIG. 3A  is shown, however the ICTAT and IPTAT generators are interchanged. Therefore, in the topology of  FIG. 3C , the first terminal of current source  314  is coupled to the supply voltage, while the second terminal of current source  314  is coupled to the node comprising the base and collector of transistor  306 , and the base of transistor  308 . The first terminal of current source  312  is coupled to the node comprising the emitter of transistor  308 , the collector of transistor  304 , and the base of transistor  310 . The second terminal of current source  312  is coupled to ground. 
         [0025]    In operation, the interchange of IPTAT current source  312  and ICTAT current source  314  causes the creation of a current ICTAT 2  which is complementary to the square of temperature, thereby increasing with decreasing absolute temperature as shown in graph  322  of  FIG. 3D . This current ICTAT 2  is coupled to output terminal  316 . In this circuit, a PTAT current and a first-order temperature-stable current is used in a base-emitter loop to produce the desired ICTAT 2  current. Summing a CTAT and a PTAT current generates the temperature-independent current. The intrinsic voltage loop is composed of transistors  302 ,  306 ,  310 ,  308 . The resulting output current is derived by summing the voltages in the loop (applying Kirchhoffs Voltage Law) as shown in the following equation: 
         [0000]        V   BE (302)− V   BE (306)= V   BE (310)− V   BE (308). 
         [0000]    In the following, the definitions I C ( 310 )=I OUT  and I C ( 306 )=I C ( 302 )=I C ( 304 )=I CTAT  as well as I C ( 308 )=I PTAT +I CTAT  will be used, and—to simplify calculations—it is assumed that transistors  302 ,  304 ,  306 ,  308  and  310  have the same emitter area A.
 
Then, substituting equation
 
         [0000]    
       
         
           
             
               V 
               BE 
             
             = 
             
               
                 V 
                 T 
               
                
               
                 ln 
                  
                 
                   ( 
                   
                     
                       I 
                       C 
                     
                     
                       
                         I 
                         S 
                       
                       · 
                       A 
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    for each base-emitter voltage, where V T , A, and I S  are constants, yields 
         [0000]    
       
         
           
             
               ln 
                
               
                 [ 
                 
                   
                     
                       I 
                       out 
                     
                     · 
                     
                       ( 
                       
                         ICTAT 
                         + 
                         IPTAT 
                       
                       ) 
                     
                   
                   
                     ICTAT 
                     · 
                     ICTAT 
                   
                 
                 ] 
               
             
             = 
             0 
           
         
       
       
         
           
             o 
              
             r 
           
         
       
       
         
           
             
               I 
               OUT 
             
             = 
             
               
                 
                   ICTAT 
                   2 
                 
                 
                   ( 
                   
                     ICTAT 
                     + 
                     IPTAT 
                   
                   ) 
                 
               
               ≈ 
               
                 
                   ICTAT 
                   2 
                 
                 K 
               
               ≡ 
               
                 ICTAT 
                  
                 
                     
                 
                  
                 2 
               
             
           
         
       
     
         [0000]    where K is substantially constant. Another embodiment of the invention uses MOSFET transistors for transistors  306  and  308 . The MOS devices, however, must operate in the subthreshold (weak inversion) region. This requirement arises because the drain current is exponentially dependent on the gate-source voltage only in subthreshold, which is the characteristic exploited by the circuit topology. In this case, 
         [0000]    
       
         
           
             
               V 
               GS 
             
             = 
             
               
                 V 
                 T 
               
                
               
                 ln 
                  
                 
                   ( 
                   
                     
                       I 
                       DS 
                     
                     
                       c 
                       · 
                       
                         W 
                         / 
                         L 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    holds—where V T  and c are constant and W/L is the aspect ration of the MOS device—and the calculation can be carried out in a similar manner as shown above. 
         [0026]    In  FIG. 4 , another embodiment of the invention generates a plurality of currents having differing temperature coefficients, the amplitude each of which is controlled, which are then added together. A current generator IPTAT 2   324  has its output coupled to reference input REF_IN  406  of a first current digital to analog converter (DAC)  402 . A digital control signal CTL 1   404  is coupled to the data input DATA_IN of said first current DAC  402 . Because the output of a typical current DAC is the reference current multiplied by the digital input, the current DAC in this embodiment acts as a multiplier of the analog IPTAT 2  input current and the CTL 1  digital control signal to generate a modified current IPTAT 2 M. A current generator ICTAT 2   326  has its output coupled to reference input REF_IN  414  of a next current DAC  410 . A digital control signal CTL 2   412  is coupled to the data input DATA_IN of said next current DAC  410 . The said next current DAC acts as a multiplier of the analog ICTAT 2  input current and the CTL 2  digital control signal to generate a modified current ICTAT 2 M. Output  408  of current DAC  402  and output  416  of current DAC  410  are coupled to first and next inputs of summing node  418 . The output of summing node  418  is coupled to compensation injection node  120  of bandgap reference circuit  122 . 
         [0027]    In operation, a digital signal proportional to the desired positive or negative modified amplitude of IPTAT 2  is input to the control input CTL 1  of first current DAC  402 , while the unmodified signal IPTAT 2  is input to the reference input of current DAC  402 . The resulting current IPTAT 2 M output from current DAC  402  is thus the reference current IPTAT 2  multiplied by the CTL 1  value. 
         [0028]    In a similar fashion, a digital signal proportional to the desired positive or negative modified amplitude of ICTAT 2  is input to the control input CTL 2  of next current DAC  410 , while the unmodified signal ICTAT 2  is input to the reference input of current DAC  410 . The resulting current ICTAT 2 M output from current DAC  410  is thus the reference current ICTAT 2  multiplied by the CTL 2  value. The outputs of current DAC  402  and current DAC  410  are then summed in summing node  418 , which output is thus the superposition of the plurality of currents generated as described above. By adjusting the control inputs, the superposition of currents from the plurality of current DACs thus can generate a plurality of compensating current versus temperature curves. Those skilled in the art will recognize that other embodiments might use differing circuits to multiply the current by a control signal, with substantially equivalent results. 
         [0029]    Determination of optimal values for CTL 1  and CTL 2  may be done, manually or in an automated manner, using a novel method described below. As described in the detail of operation for the circuits of  FIG. 3 , the IPTAT 2  compensation current is proportional to the square of increasing temperature, and as such its compensating influence is primarily in the region above a nominal temperature. The ICTAT 2  compensation current, on the other hand, is proportional to the square of decreasing temperature, and as such its compensating influence is primarily in the region below a nominal temperature. While there is some interdependence of effect of IPTAT 2  and ICTAT 2  in the temperature region around nominal temperature, this interdependence shrinks at temperatures well above or well below nominal. It is therefore possible to vary CTL 1  (affecting IPTAT 2 ) while measuring its effect on curvature in a region above nominal temperature, and determine what value of CTL 1  minimizes curvature in that region. Likewise, CTL 2  may be varied and its effect in curvature in a temperature region below nominal may be measured, to determine an optimal value for CTL 2  which minimizes curvature in this second region. Additional iterations of this process may be done to further minimize any effects of interdependence between IPTAT 2  and ICTAT 2  compensation. 
         [0030]    As shown in  FIG. 5 , the curvature of output voltage versus temperature at a plurality of CTL 1  values may be measured and plotted, to determine that optimal value of CTL 1  where the curvature is zero. In  FIG. 5 , curvature, expressed in ppm/degree C. change in the compensated output voltage versus temperature, is plotted against decimal values for CTL 1  of (for example) 0, 1, 2, 4, 8, 16, 32, and 48. By interpolating the resulting set of data points of curvature versus CTL 1 , the decimal value for CTL 1  at curvature nearest zero may be determined. The optimal binary value of CTL 1  is then that binary value closest to the interpolated decimal value. 
         [0031]    It will be apparent to those skilled in the art that, for some circuits, a suitably accurate optimal CTL 1  may be computed from a small subset of data points, in some cases as few as two. For example, with CTL 1  equal to 16 and 48 in the example of  FIG. 5 , a linear interpolation between these two data points crosses the zero curvature axis at approximately CTL 1 =27. In other applications, other values for CTL 1 , represented by one or more bits, may be effectively utilized in determining the nearest CTL 1  value for zero curvature. 
         [0032]      FIG. 6  shows a flow chart for creating a set of curvature C versus CTL 1  values when CTL 1  is a binary number. At step  602 , CTL 2  is set to a value, for example zero, which will remain constant for the rest of the process. At step  604 , a counter value N, representing the bit number of binary number CTL 1 , is set to a starting value of 1. This bit  1  represents the least significant bit (LSB) of CTL 1 . At step  606 , bit N is set to “1”. In the first iteration of the process, N=1 so bit  1  is the LSB. At step  608 , the output voltage V(N,T) of the compensated circuit, with CTL 1  compensation having bit N at “1”, is measured at a plurality of temperatures, and the curvature C(N) of the V versus T function for a CTL 1  value having bit N at “1” is computed and stored. At step  610 , N is compared with a value MAX to determine if all bits of the binary value CTL 1  have been set to “1”, indicating no further iteration is needed. The number MAX is the number of bits in CTL 1 . If N is not greater than MAX, at step  612  N is incremented by 1, then the process reverts to step  606 . If N is greater than MAX, indicating all bits of CTL 1  have been set to “1” in sequence, the process continues with step  614 , where, by interpolation, the decimal value for CTL 1  nearest that value at which C(N) is zero is determined. This decimal value of CTL 1  is therefore that optimal value for CTL 1  to minimize curvature C. At step  616 , this decimal value for the optimal CTL 1  is converted to binary and applied to the control inputs CTL 1 . 
         [0033]    Those skilled in the art will recognize the efficiency of the process described above, in that the number of iterations used to generate the optimal CTL 1  value is only the number of bits MAX. It will also be recognized that once an optimal CTL 1  value is determined, a substantially identical process may be used to determine the optimal CTL 2  value, by holding CTL 1  constant while varying the value of CTL 2  bit by bit as described above. Those skilled in the art will also recognize that the value at which CTL 2  is held while CTL 1  is varied does not need to be zero, but may rather be some other value, for example a value determined by statistical measurement of a plurality of circuits to be an average optimal value for the plurality of circuits. It is also clear that not every bit of CTL 1  or CTL 2  must be exercised (set to “1”), as long as those values chosen for CTL 1  or CTL 2  generate data points both above and below the zero curvature axis. Also, it is apparent that two or more temperatures may be used in determining C(N), and that computations may be carried out by special purpose or general purpose computers. 
         [0034]    It will also be understood that there may be some interaction between CTL 1  and CTL 2 ; that is, the optimal value for CTL 1  with CTL 2 = 0  may not be the same optimal value of CTL 1  with CTL 2  at a non-zero value, such as its value after optimization. In this case, a next iteration of CTL 1  may be desirable while holding CTL 2  at its optimal value, followed if desired by a next iteration of CTL 2  with the value of CTL 1  resulting from its next iteration. In some cases it may be found that an average value of CTL 2  is acceptable, and that only CTL 1  need be optimized using the process described (or vice-versa). 
         [0035]    In  FIG. 7 , curvature values C(N) are computed and stored for a set of multi-bit values of CTL 1 . At step  702 , CTL 2  is set to a value, for example zero, which will remain constant for the rest of the process. At step  704 , a counter value N, representing the Nth value of a plurality of binary values for CTL 1 , is set to a starting value of 1. At step  706 , CTL 1  is set to the first stored value CTL 1 (N). At step  708 , the output voltage V(N,T) of the compensated circuit, with CTL 1  compensation having a value CTL 1 (N), is measured at a plurality of temperatures, and the curvature of the V versus T function at the CTL 1 (N) value is computed and stored. At step  710 , N is compared with a value NUM to determine if all of the plurality of N stored binary values for CTL 1  have been used, indicating no further iteration is needed. The number NUM is the number of stored binary values for CTL 1 . If N is less than or equal to NUM, another iteration is called for, and N is incremented by 1 at step  712 , then the process reverts to step  706 . If N is greater than NUM, indicating all stored values for CTL 1  have been used, the process continues with step  714 , where, by interpolation, the decimal value for CTL 1  nearest that value at which C(N) is zero is determined. This decimal value of CTL 1  is therefore that optimal value for CTL 1  to minimize curvature C. At step  716 , this decimal value for the optimal CTL 1  is converted to binary and applied to the control inputs CTL 1 . 
         [0036]    Those skilled in the art to which the invention relates will appreciate that, while the above methods describe optimizing the CTL 1  value, an optimal value for CTL 2  may be similarly determined by interchanging CTL 1  and CTL 2  in the methods described above. It is also obvious that in some cases there will be interaction between the CTL 1  and CTL 2  values, and therefore additional iterations may be desirable to optimize the combination of CTL 1  and CTL 2  for some circuits. 
         [0037]    It should be understood that the use of Vdd, Vref, ground, etc., are illustrative only, and that implementations using single or dual power supplies and the like are equally possible. Moreover, reference voltages developed either internal to the circuit or external to the circuit will suffice. While field-effect and bipolar transistors have been shown in these embodiments, alternative topologies using field effect and bipolar transistors in differing topologies will provide substantially equivalent operation. 
         [0038]    Those skilled in the art to which the invention relates will also appreciate that yet other substitutions and modifications can be made to the described embodiments, without departing from the spirit and scope of the invention as described by the claims below. Many alternatives to the circuits and sub circuits described are possible while retaining the scope and spirit of the invention.