Abstract:
The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar selection transistor that is provided in the substrate and connected via the buried contact The invention likewise provides a corresponding trench capacitor.

Description:
CLAIM FOR PRIORITY  
       [0001]     This application claims the benefit of priority to German Application No. 10 2004 040 046.6, filed in the German language on Aug. 18, 2004, the contents of which are hereby incorporated by reference.  
       TECHNICAL FIELD OF THE INVENTION  
       [0002]     The present invention provides a method for fabricating a trench capacitor with an insulation collar which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell, and to a corresponding trench capacitor.  
       BACKGROUND OF THE INVENTION  
       [0003]     Although applicable in principle to any desired integrated circuits, the present invention and the problem area on which it is based are explained with regard to integrated memory circuits in silicon technology.  
         [0004]      FIG. 1  shows a diagrammatic sectional illustration of a semiconductor memory cell with a trench capacitor and a planar selection transistor connected thereto.  
         [0005]     In  FIG. 1 , reference symbol  1  designates a silicon semiconductor substrate. Provided in the semiconductor substrate  1  are trench capacitors GK 1 , GK 2  having trenches G 1 , G 2 , the electrically conductive fillings  20   a ,  20   b  of which form first capacitor electrodes. The conductive fillings  20   a ,  20   b  are insulated in the lower and central trench region by a dielectric  30   a ,  30   b  from the semiconductor substrate  1 , which, for its part, forms the second capacitor electrodes (if appropriate in the form of a buried plate (not shown)).  
         [0006]     Provided in the central and upper region of the trenches G 1 , G 2  are peripheral insulation collars  10   a ,  10   b , above which are provided buried contacts  15   a ,  15   b , which are in electrical contact with the conductive fillings  20   a ,  20   b  and the adjoining semiconductor substrate  1 . The buried contacts  15   a ,  15   b  are connected to the semiconductor substrate  1  only on one side (cf.  FIGS. 2   a, b ) . Insulation regions  16   a ,  16   b  insulate the other side of the substrate from the buried contacts  15   a ,  15   b  or insulate the buried contacts  15   a ,  15   b  toward the top side of the trenches G 1 , G 2 .  
         [0007]     This enables a very high packing density of the trench capacitors GK 1 , GK 2  and of the associated selection transistors, which will now be explained. In this case, reference is made principally to the selection transistor which is associated with the trench capacitor GK 2 , since only the drain region D 1  or the source region S 3 , respectively, of adjacent selection transistors is depicted. The selection transistor associated with the trench capacitor GK 2  has a source region S 2 , a channel region K 2  and a drain region D 2 . The source region S 2  is connected via a bit line contact BLK to a bit line (not shown) arranged above an insulation layer I. The drain region D 2  is connected to the buried contact  15   b  on one side. A word line WL 2  having a gate stack GS 2  and a gate insulator G 12  surrounding the latter runs above the channel region K 2 . The word line WL 2  is an active word line for the selection transistor of the trench capacitor GK 2 .  
         [0008]     Running parallel adjacent to the word line WL 2  are word lines WL 1  comprising gate stack GS 1  and gate insulator GI 1  and word line WL 3  comprising gate stack GS 3  and gate insulator GI 3 , which are passive word lines for the selection transistor of the trench capacitor GK 2 . Said word lines WL 1 , WL 3  serve for driving selection transistors which are displaced in the third dimension with respect to the sectional illustration shown.  
         [0009]      FIG. 1  illustrates the fact that this type of connection on one side of the buried contact enables the trenches and the adjacent source regions or drain regions of relevant selection transistors to be arranged directly beside one another. As a result, the length of a memory cell may amount to just 4 F and the width to just 2 F, where F is the minimum length unit that can be realized technologically (cf.  FIGS. 2   a, b ).  
         [0010]      FIG. 2A  shows a plan view of a memory cell array with memory cells in accordance with  FIG. 1  in a first arrangement possibility.  
         [0011]     Reference symbol DT in  FIG. 2A  designates trenches which are arranged row-wise at a distance of 3 F from one another and columnwise at a distance of 2 F. Adjacent rows are displaced by 2 F relative to one another. UC in  FIG. 2A  designates the area of a unit cell, which amounts to 4 F×2 F=8 F 2 . STI designates isolation trenches which are arranged at a distance of 1 F from one another in the row direction and insulate adjacent active regions from one another. Bit lines BL likewise run at a distance of 1 F from one another in the row direction, whereas the word lines run at a distance of 1 F from one another in the column direction. In this arrangement example, all the trenches DT have a contact region KS of the buried contact to the substrate on the left-hand side and an insulation region IS on the right-hand side (regions  15   a, b  and  16   a, b , respectively, in  FIG. 1 ).  
         [0012]      FIG. 2B  shows a plan view of a memory cell array with memory cells in accordance with  FIG. 1  in a second arrangement possibility.  
         [0013]     In this second arrangement possibility, the rows of trenches have alternating connection regions and insulation regions of the buried contacts, respectively. Thus, in the bottommost row of  FIG. 2B , the buried contacts are in each case provided with a contact region KS 1  on the left-hand side and with an insulation region IS 1  on the right-hand side. By contrast, in the row located above that, all the trenches DT are provided with each insulation region IS 2  on the left-hand side and with a contact region KS 2  on the right-hand side. This arrangement alternates in the column direction.  
         [0014]     For DRAM memory devices with trench capacitors in sub-100 nm technologies, the resistance of the trench and of the buried contact are a main contribution to the total RC delay, and thus determine the speed of the DRAM. The relatively low conductivity and the pinch-off, which is produced by an overlay displacement of the STI etching, results in a dramatic increase in the series resistance in the trench.  
         [0015]     This problem has been tackled by introducing polysilicon that is highly doped with arsenic, improving the overlay between the active regions and the trench, introducing self-aligned fabrication of a buried contact with a connection on one side and thinning the nitrided contact point of the buried contact. The SiN interface nevertheless significantly increases the series resistance since the charge carriers have to tunnel through the SiN interface.  
       SUMMARY OF THE INVENTION  
       [0016]     The present invention discloses an improved method for fabricating a trench capacitor connected on one side and having a shorter RC delay.  
         [0017]     The present invention provides a process in which the SiN interface can be dispensed with since a buried contact made of an amorphous conductive material is used.  
         [0018]     In particular ternary or quaternary systems which remain amorphous even up to high temperatures are suitable for the buried contact according to the invention, thus e.g. TiAlN, TiSiN, TaSiN, HfSiN, TiTaN, TiHfN, TiZrN, TiZrSiN and the like.  
         [0019]     In an advantageous manner, in the case of such a buried contact made of an amorphous conductive material, no dislocations can grow into the crystalline silicon substrate since no grain boundaries exist.  
         [0020]     By varying the stoichiometry, it is possible to set a work function of 4.0 to 4.2 eV and thus avoid a Schottky barrier. The materials specified can be deposited very well by means of the ALD method, as a result of which it is possible to vary the composition by way of the layer thickness.  
         [0021]     In accordance with one preferred embodiment, after the conductive amorphous metal filling has been etched back, an insulation cover is provided in the upper trench region at least as far as the top side of the substrate.  
         [0022]     In accordance with a further preferred embodiment, the filling is provided as far as the top side of the insulation collar, then a nitride liner layer is deposited and then the trench is completely filled with the filling material, an STI trench fabrication process is effected and the filling material is removed.  
         [0023]     In accordance with a further preferred embodiment, after removal of the filling material, spacers are formed on the trench walls above the insulation collar and the spacer lying above the connection region is removed, the spacer lying above the insulation region being masked with a silicon liner.  
         [0024]     In accordance with a further preferred embodiment, the conductive amorphous metal filling is deposited by means of the ALD method (ALD=atomic layer deposition).  
         [0025]     In accordance with a further preferred development, the conductive amorphous metal filling comprises one of the systems TiAlN, TiSiN, TaSiN, HfSiN, ZrSiN, TiTaN, TiHfN, TiZrN, TiZrSiN, TiHfSiN, TiZrAlN, TiHfAlN.  
         [0026]     In accordance with a further preferred embodiment, the stoichiometric composition of the conductive amorphous metal filling is varied by way of its thickness.  
         [0027]     In accordance with a further preferred embodiment, the stoichiometric composition is set in such a way that it amounts to 4.0 to 4.2 eV at the interface with the substrate. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]     Exemplary embodiments of the invention are illustrated in the drawings and explained in more detail in the description below.  
         [0029]     In the figures:  
         [0030]      FIG. 1  shows a semiconductor memory cell with a trench capacitor and a planar selection transistor connected thereto.  
         [0031]      FIGS. 2A , B show a respective plan view of a memory cell array with memory cells in accordance with  FIG. 1  in a first and second arrangement possibility.  
         [0032]     FIGS.  3 A-F show method stages of a fabrication method as an embodiment of the present invention. 
     
    
       [0033]     In the figures, identical reference symbols designate identical or functionally identical constituent parts.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0034]     In the embodiments described below, for reasons of clarity, a portrayal of the fabrication of the planar selection transistors is dispensed with and only the formation of the buried contact of the trench capacitor, which buried contact is connected on one side, is discussed in detail. Unless expressly mentioned otherwise, the steps of fabricating the planar selection transistors are the same as in the prior art.  
         [0035]     FIGS.  3 A-F are diagrammatic illustrations of successive method stages of a fabrication method as first embodiment of the present invention.  
         [0036]     In  FIG. 3A , reference symbol  5  designates a trench provided in the silicon semiconductor substrate  1 . Provided on the top side OS of the semiconductor substrate  1  is a hard mask comprising a pad oxide layer  2  and a pad nitride layer  3 . A dielectric  30  is provided in the lower and central region of the trench  5 , said dielectric insulating an electrically conductive filling  20  from the surrounding semiconductor substrate  1 . A peripheral insulation collar  10  is provided in the upper and central region of the trench  5 , said insulation collar being sunk into the trench  5  to approximately the same level as the conductive filling  20 . An exemplary material for the insulation collar  10  is silicon oxide, and polysilicon for the electrically conductive filling  20 . However, other material combinations are also conceivable, of course.  
         [0037]     In accordance with  FIG. 3B , firstly a liner layer  40  is deposited above the structure in accordance with  FIG. 3A , which comprises silicon nitride or silicon nitride/silicon oxide, e.g. thermal SiO 2  and LPCVD-Si 3 N 4 .  
         [0038]     The trench  5  is thereupon closed again with a polysilicon filling  50 , for example by deposition and subsequent chemical mechanical polishing.  
         [0039]     In a subsequent process step, not illustrated in the figures, a hard mask is then formed above the structure in accordance with STI trenches to be formed which lie in parallel planes in front of and behind the plane of the drawing, whereupon the STI trenches are etched and filled (high-temperature process). Afterward, the hard mask for the STI trench formation is removed again.  
         [0040]     The purpose of this advanced high-temperature step is to prevent the high-temperature step from having any further influence later on the buried contact that is then to be formed.  
         [0041]     Furthermore, with reference to  FIG. 3C , in which STT designates the STI trench depth, the polysilicon filling  50  is then removed by means of a wet etching, and the liner layer  40  is subjected to an anisotropic spacer etching in order to form spacers  40 ′. As can be seen from  FIG. 3C , during the etching back of the polysilicon filling, the trench polysilicon filling  20  is also etched back to below the top side of the insulation collar  10 , so that the STI trench depth STT lies between the top side of the insulation collar  10  and the top side of the trench polysilicon filling  20 .  
         [0042]     With reference to  FIG. 3D , an amorphous silicon liner  60  is subsequently deposited conformally over the resulting structure, into which boron ions are implanted by means of an oblique implantation I 1 , reference symbol  60   a  designating a region shaded from the implantation. The region  60   a  of the silicon liner  60  which is shaded from the implantation has a higher etching rate with regard to an NH 4 OH etching carried out as the next process step.  
         [0043]     With reference to  FIG. 3E , an NH 4 OH etching has the effect that the region  60   a  can be removed selectively with respect to the remaining, implanted region of the silicon liner  60 .  
         [0044]     In a subsequent process step, the uncovered region of the nitride spacer  40 ′ which is situated on the right-hand side of the figure is selectively etched by means of H 3 PO 4  in order to uncover the later contact region KS of the buried contact.  
         [0045]     With reference to  FIG. 3F , a metal deposition of e.g. TiTaN without prior SiN interface formation is then effected directly onto the crystalline silicon substrate  1  in order to form a conductive amorphous filling  70  in the contact region KS.  
         [0046]     At the beginning of the deposition, a Ta-rich layer is deposited in order to set the work function to 4.0 to 4.2 eV. In the course of the deposition, the Ti proportion in the layer is gradually increased in order to reduce the electrical resistance.  
         [0047]     Afterward, the conductive amorphous filling  70  is etched back to below the top side OS of the substrate  1  but to above the uncovered region of the insulation collar  10 .  
         [0048]     Finally, the trench  5  is filled with an insulation cover  80  in a known manner, said insulation cover comprising silicon oxide, for example.  
         [0049]     Although the present invention has been described above on the basis of a preferred exemplary embodiment, it is not restricted thereto, but rather can be modified in diverse ways.  
         [0050]     In particular, the selection of the layer materials is only by way of example and can be varied in many different ways.