Abstract:
A port circuit for a hard disk backplane of a server system includes a control microchip and at least one selecting microchip. The hard disk backplane includes a number of ports. The server system includes a number of servers connected to a portion of the ports. The at least one selecting microchip is connected to the control microchip and other portion of ports of a hard disk backplane. When the control microchip detects that one or more standby servers form part of the server system, the control microchip selects the one or more standby server to connect to the other portion of the ports. When the control microchip does not detect that the one or more standby servers form part of the server system, the control microchip selects the servers to connect to the other portion of the ports.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The disclosure generally relates to hardware circuits for computers, and particularly to a port circuit for a hard disk backplane and a server system using the port circuit. 
         [0003]    2. Description of Related Art 
         [0004]    A 4-in-1 2U server system includes four servers sharing a hard disk backplane. Commonly, each server can provide six groups of serial advanced technology attachment (SATA) signals to the hard disk backplane to support hard disks installed on the hard disk backplane, and each hard disk backplane usually includes twelve ports configured for inserting twelve hard disks. Therefore, to control the twelve hard disks, each server outputs three groups of SATA signals to control three hard disks of the total twelve hard disks. 
         [0005]    However, when the 2U server system needs to electronically connect to another server system, such as a server system that includes two servers, if each server maintains to control three hard disks, the 2U server system can only support six hard disks and only six hard disks can be used although the 2U server actually can provide twelve groups of SATA signals, which is an inefficient use of hardware. 
         [0006]    Therefore, there is room for improvement within the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0007]    Many aspects of the present disclosure can be better understood with reference to the following drawing. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the disclosure. 
           [0008]    The FIGURE is a circuit diagram of a port circuit for hard disk backplane for a server system, according to an exemplary embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    The FIGURE is a circuit diagram of a port circuit  100  for hard disk backplane  200  for a server system, according to an exemplary embodiment of the disclosure. The server system may be a 2U or 3U server system, in this embodiment, the port circuit  100  is applied to the 2U server system as an example. The 2U server system includes two servers S 1 , S 2  and two standby servers S 3 , S 4 . The two servers S 1 , S 2  form part of the 2U server system, and the two standby servers S 3 , S 4  can selectively form part of the 2U server system. The term “form part” means that the servers are electronically connected in the appropriate connection for a 2U or a 3U server configuration. 
         [0010]    The port circuit  100  is installed on the hard disk backplane  200 . The hard disk backplane  200  includes twelve ports Port 1 -Port 12  configured for inserting hard disks. The port circuit  100  includes a control microchip  10  and two selecting microchips  30 ,  50 . 
         [0011]    The server S 1  includes a group of SATA signal output terminals S 1 - 1 , S 1 - 2 , S 1 - 3 , S 1 - 4 , S 1 - 5 , and S 1 - 6 . The SATA signal output terminals S 1 - 1 , S 1 - 2 , and S 1 - 3  are respectively connected to the ports Port 1 -Port 3  of the hard disk backplane  200  and respectively output SATA signals S 11 , S 12  and S 13  to the ports Port 1 -Port 2 . The SATA signal output terminals S 1 - 4  S 1 - 5  and S 1 - 6  are electrically connected to the selecting microchip  30  and respectively output SATA signal S 14 , S 15 , and S 16  to the selecting microchip  30 . 
         [0012]    The structure of the server S 2  is substantially similar to the server S 1  and includes a group of SATA signal output terminals S 2 - 1 , S 2 - 2 , S 2 - 3 , S 2 - 4 , S 2 - 5  and S 2 - 6 . The SATA signal output terminals S 2 - 1 , S 2 - 2 , and S 2 - 3  are respectively connected to the ports Port 4 -Port 6  of the hard disk backplane  200  and respectively output SATA signals S 21 , S 22  and S 23  to the ports Port 4 -Port 6  of the hard disk backplane  200 . The SATA signal output terminals S 2 - 4 , S 2 - 5  and S 2 - 6  are electrically connected to the selecting microchip  50  and respectively output SATA signal S 24 , S 25 , and S 26  to the selecting microchip  50 . 
         [0013]    The standby server S 3  includes a group of SATA signal output terminals S 3 - 1 , S 3 - 2 , S 3 - 3  and a triggering terminal PRE 3 . When the standby server S 3  forms part of the 2U server system, the SATA signal output terminals S 3 - 1 , S 3 - 2 , and S 3 - 3  are electrically connected to the selecting microchip  30  and respectively output SATA signals S 31 , S 32  and S 33  to the selecting microchip  30 , and the triggering terminal PRE 3  is electrically connected to the control microchip  10  through a hard disk bridging plate (not shown) and sends a triggering signal which denotes the standby server S 3  has already formed part of the 2U sever system to the control microchip  10 . 
         [0014]    The structure of the standby server S 4  is substantially similar to the standby server S 3  and includes a group of SATA signal output terminals S 4 - 1 , S 4 - 2 , S 4 - 3  and a triggering terminal PRE 4 . When the standby server S 4  forms part of the 2U server system, The SATA signal output terminals S 4 - 1 , S 4 - 2 , and S 4 - 3  are electrically connected to the selecting microchip  50  and respectively output SATA signals S 51 , S 52 , and S 53  to the selecting microchip  50 , and the triggering terminal PRE 4  is electrically connected to the control microchip  10  through a hard disk bridging plate (not shown) and sends the triggering signal which denotes the standby server S 4  has already formed part of the 2U sever system to the control microchip  10 . 
         [0015]    The control microchip  10  includes two detecting terminals IN 1 , IN 2  and two output terminals O 1 , O 2 . The two detecting terminals Ni, IN 2  are respectively connected to the triggering terminal PRE 3 , PRE 4  to receive the triggering signals. The two output terminals O 1 , O 2  are respectively connected to the selecting microchips  30 ,  50 . 
         [0016]    When the detecting terminal IN 1  receives the triggering signal from the standby server S 3 , which means the standby server S 3  has already formed part of the 2U server system, the output terminal O 1  outputs a first control signal, which may be a high level signal (i.e. logic 1) to the selecting microchip  30 . Otherwise, the detecting terminal Ni does not receive the triggering signal, that is the standby server S 3  is not installed to the 2U server system, the output terminal O 1  outputs a second control signal, which may be a low level signal (i.e. logic 0) to the selecting microchip  30 . 
         [0017]    Similarly, when the detecting terminal IN 2  receives the triggering signal from the standby server S 4 , which means the standby server S 4  has already formed part of the 2U server system, the output terminal O 2  outputs the first control signal, which may be a high level signal (i.e. logic 1) to the selecting microchip  30 . Otherwise, the detecting terminal IN 2  does not receive the triggering signal, which means the standby server S 4  does not form part of the 2U server system, the output terminal O 2  outputs a second control signal, which may be a low level signal (i.e. logic 0) to the selecting microchip  30 . 
         [0018]    The selecting microchip  30  includes three data receiving terminals TX 0 , TX 1 , and TX 2 , three data input terminals D 0 , D 1 , and D 2 , three data output terminals BPO, BP 1 , and BP 2 , and a selecting terminal SEL. 
         [0019]    The data receiving terminal TX 0 , TX 1 , and TX 2  are respectively connected to the SATA signal output terminals S 1 - 4 , S 1 - 5 , and S 1 - 6  and receive the SATA signals S 14 , S 15 , and S 16 . The three data input terminals D 0 , D 1 , and D 2  are connected to the SATA signal output terminals S 3 - 1 , S 3 - 2 , and S 3 - 3  and receive the SATA signals S 31 , S 33 , and S 33 . The data output terminals BP 0 , BP 1 , and BP 2  are respectively connected to the ports Port 7 -Port 9 . The selecting terminal SEL is electrically connected to the output terminal O 1 . 
         [0020]    When the selecting terminal SEL receives the first control signal, the data input terminals D 0 , D 1 , and D 2  are selected and switched to be connected to the data output terminals BP 0 , BP 1 , and BP 2 . The SATA signals S 31 , S 32 , and S 33  from the standby severs S 3  can be transmitted to the ports Port 7 -Port 9 . When the selecting terminal SEL receives the second control signal, the data receiving terminals TX 0 , TX 1 , TX 3  are selected and switched to connect to the data output terminals BP 0 , BP 1 , and BP 3 , and the SATA signals S 14 , S 15 , and S 16  from the severs S 1  are transmitted to the ports Port 7 -Port 9 . 
         [0021]    The structure of the selecting microchip  50  is substantially similar to the selecting microchip  30  and includes three data receiving terminals TX 0 , TX 1 , and TX 3 , three data input terminals D 0 , D 1 , and D 2 , three data output terminals BP 0 , BP 1  and BP 2  and a selecting terminal SEL. The differences are the data receiving terminals TX 0 , TX 1 , and TX 3  of the selecting microchip  50  are connected to the SATA signal output terminals S 2 - 4 , S 2 - 5 , and S 2 - 6 ; the three data input terminals D 0 , D 1 , and D 2  are connected to the SATA signal output terminals S 4 - 1 , S 4 - 2 , and S 4 - 3 ; the data output terminals BP 0 , BP 1 , and BP 2  are respectively connected to the ports Port 10 -Port 12 ; and the selecting terminal SEL is electrically connected to the output terminal O 1 . 
         [0022]    In use, the two servers S 1 , S 2  form part of the 2U server system. The ports Port 1 -Port 3  receive the SATA signals S 11 , S 12 , S 13  from the server S 1 , and the ports Port 4 -Port 6  receive the SATA signals  521 , S 22 , S 23  from the server S 2 . 
         [0023]    When the standby server S 3  forms part of the 2U server system, the triggering terminal PRE 3  outputs the triggering signal to the detecting terminal IN 1 , and the output terminal O 1  outputs the first control signal to the selecting terminal SEL. The data input terminals D 0 , D 1 , and D 2  are switched to connect to the data output terminals BP 0 , BP 1 , and BP 2  and the SATA signals S 31 , S 32 , and S 33  from the standby severs S 3  can be transmitted to the ports Port 7 -Port 9 . 
         [0024]    When the selecting terminal SEL receives the second control signal, the data receiving terminals TX 0 , TX 1 , TX 3  are switched to connect to the data output terminals BP 0 , BP 1 , and BP 3 , and the SATA signals S 14 , S 15 , and S 16  from the severs S 1  are transmitted to the ports Port 7 -Port 9 . Therefore, no matter if the standby server S 3  forms part of the 2U server system or not, the port Port 7 -Port 9  can be used. 
         [0025]    The operation principle of the selecting microchip  50  is substantially similar to the selecting microchip  30 , thus detail description of the selecting microchip  50  is omitted. Similarly, no matter if the standby server S 4  forms part of the 2U server system or not, the port Port 10 -Port 12  can be used. 
         [0026]    In other embodiments, if only one of the standby servers S 3 , S 4  selectively forms part of the 2U server system, one of the selecting microchips  30 ,  50  can be correspondingly omitted. 
         [0027]    In other embodiments, if the port circuit of hard disk backplane  100  is applied to a 3U server system, the number of the standby servers and the number of the selecting microchips can be correspondingly increased. 
         [0028]    It is believed that the exemplary embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the disclosure.