Abstract:
A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention generally relates to nonvolatile ferroelectric memory device, and more specifically, to a technology of controlling read/write operations of a nonvolatile ferroelectric memory cell using a channel resistance of a memory cell which is differentiated by polarity states of a ferroelectric material in a nano scale memory device. 
         [0003]    2. Description of the Related Art 
         [0004]    Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and conserves data even after the power is turned off. 
         [0005]    The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated. 
         [0006]    The technical contents on the above FeRAM are disclosed in the Korean Patent Application No. 2001-57275 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein. 
         [0007]    A unit cell of a conventional nonvolatile FeRAM device comprises a switching element and a nonvolatile ferroelectric capacitor. The switching element performs a switching operation depending on a state of a word line to connect a nonvolatile ferroelectric capacitor to a sub bit line. The nonvolatile ferroelectric capacitor is connected between and a plate line and one terminal of the switching element. 
         [0008]    Here, the switching element of the conventional FeRAM is a NMOS transistor whose switching operation is controlled by a gate control signal. 
         [0009]      FIG. 1  is a cross-sectional diagram illustrating a conventional nonvolatile ferroelectric memory device. 
         [0010]    A conventional 1-T (One-Transistor) FET (Field Effect Transistor) cell comprises a N-type drain region  2  and a N-type source region  3  which are formed on a P-type region substrate  1 . A ferroelectric layer  4  is formed on a channel region, and a word line  5  is formed on the ferroelectric layer  4 . 
         [0011]    The above-described conventional nonvolatile FeRAM device reads and writes data by using a channel resistance of the memory cell which is differentiated depending on polarization states of the ferroelectric layer  4 . That is, when the polarity of the ferroelectric layer  4  induces positive charges to the channel, the memory cell becomes at a high resistance state to be turned off. On the contrary, when the polarity of the ferroelectric layer  4  induces negative charges to the channel, the memory cell becomes at a low resistance state to be turned on. 
         [0012]    However, in the conventional nonvolatile FeRAM device, when the cell size becomes smaller, a data maintaining characteristic is degraded, so that it is difficult to perform the normal operation of the cell. That is, a voltage is applied to an adjacent cell at read/write modes to destroy data of unselected cells, so that interface noise is generated between the cells and it is difficult to perform a random access operation. 
       SUMMARY OF THE INVENTION 
       [0013]    Accordingly, it is an object of the present invention to form a floating channel layer comprising a N-type drain region, a P-type channel region and N-type source region between a word line and a bottom word line, thereby improving a data maintaining characteristic. 
         [0014]    It is another object of the present invention to provide the above-described memory cell so as to control read/write operations of a memory cell array, thereby improving reliability of the cell and reducing the whole size of the cell at the same time. 
         [0015]    In an embodiment, a nonvolatile ferroelectric memory device comprises an insulating layer formed on a bottom word line, a floating channel layer, a ferroelectric layer formed on the channel region of the floating channel layer, and a word line formed on the ferroelectric layer. The floating channel layer comprises a P-type channel region formed on the insulating layer and kept at a floating state, a N-type drain region and a N-type source region which are connected to both sides of the channel region. Here, different channel resistance is induced to the channel region depending on polarity states of the ferroelectric layer, so that data are read and written. 
         [0016]    In another embodiment, a nonvolatile ferroelectric memory device comprising a unit cell array which includes a plurality of bottom word lines, a plurality of insulating layers, a floating channel layer, a plurality of ferroelectric layers, a plurality of word lines. The plurality of insulating layers are formed on the plurality of bottom word lines, respectively. The floating channel layer comprises a plurality of P-type channel regions located on the plurality of insulating layers and a plurality of N-type drain and source regions which are alternately connected in series to the plurality of P-type regions. The plurality of ferroelectric layers are formed respectively on the plurality of P-type channel regions of the floating channel layer. The plurality of word lines are formed on the plurality of ferroelectric layers, respectively. Here, the unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of P-type channel regions depending on polarity states of the plurality of ferroelectric layers. 
         [0017]    In still another embodiment, a nonvolatile ferroelectric memory device comprising a unit cell array which includes a bottom word line, a plurality of insulating layers, a floating channel layer, a plurality of ferroelectric layers, and a plurality of word lines. The plurality of insulating layers are formed on the bottom word line, respectively. The floating channel layer comprises a plurality of P-type channel regions located on the plurality of insulating layers and a plurality of N-type drain and source regions which are alternately connected in series to the plurality of P-type channel regions. The plurality of ferroelectric layers are formed respectively on the plurality of P-type channel regions of the floating channel layer. The plurality of word lines are formed on the plurality of ferroelectric layers, respectively. Here, the unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of P-type channel regions depending on polarity states of the plurality of ferroelectric layers. 
         [0018]    In still another embodiment, a nonvolatile ferroelectric memory device comprises a bottom word line, a floating channel layer formed on the bottom word line and kept at a floating state, a ferroelectric layer, and a word line formed on the ferroelectric layer in parallel with the bottom word line. The ferroelectric layer where data are stored is formed on the floating channel layer. Here a write operation is performed on data corresponding to the ferroelectric layer depending on a state of a voltage level applied to the bottom word line and the word line, and read operation is performed on data by inducing different channel resistance to the floating channel layer depending on polarity states of charges stored in the ferroelectric layer. 
         [0019]    In still another embodiment, a nonvolatile ferroelectric memory device comprises a plurality of memory cells, a first switching element, and a second switching element. Switching operations of the plurality of memory cells are selectively controlled respectively depending on voltages applied to a plurality of word lines and a plurality of bottom word lines, floating channel layers are connected serially in the plurality of memory cells. The first switching element selectively connects the plurality of memory cells to a bit line in response to a first selecting signal. The second switching element selectively connects the plurality of memory cells to a sensing line in response to a second selecting signal. Here, each of the plurality of memory cells comprises an insulating layer formed on the bottom word line, the floating channel layer, a ferroelectric layer formed on the channel region of the floating channel layer, and a word line formed on the ferroelectric layer. The floating channel layer comprises a P-type channel region formed on the insulating layer and kept at a floating state, a N-type drain region and a N-type source region which are connected to both sides of the channel region. 
         [0020]    In still another embodiment, a nonvolatile ferroelectric memory device comprises a plurality of bit lines arranged in a row direction, a plurality of sensing lines arranged perpendicular to the plurality of bit lines, a plurality of memory cells arranged in row and column directions where the plurality of bit lines and the plurality of sensing lines are crossed, and a plurality of sense amplifiers connected one by one to the plurality of bit lines. Here, each of the plurality of memory cells comprises an insulating layer formed on a bottom word line, the floating channel layer comprising a P-type channel region formed on the floating layer and kept at a floating state, a N-type drain region and a N-type source region which are connected to both sides of the channel region, a ferroelectric layer formed on the channel region of the floating channel layer, and a word line formed on the ferroelectric layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    Other aspects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which: 
           [0022]      FIG. 1  is a cross-sectional diagram illustrating a conventional nonvolatile ferroelectric memory device; 
           [0023]      FIGS. 2   a  to  2   c  are diagrams illustrating a cross section of a cell and its symbol of a nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0024]      FIGS. 3   a  and  3   b  are diagrams illustrating write and read operations on high data of the nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0025]      FIGS. 4   a  and  4   b  are diagrams illustrating write and read operation on low data of the nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0026]      FIG. 5  is a layout cross-sectional diagram illustrating the nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0027]      FIGS. 6   a  and  6   b  are cross sectional diagrams illustrating the nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0028]      FIG. 7  is a cross-sectional diagram illustrating a nonvolatile ferroelectric memory device having a multiple layer structure according to an embodiment of the present invention; 
           [0029]      FIG. 8  is a diagram illustrating a nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0030]      FIGS. 9   a  and  9   b  are cross-sectional diagrams illustrating the nonvolatile ferroelectric memory device of  FIG. 8 ; 
           [0031]      FIG. 10  is a cross-sectional diagram illustrating a nonvolatile ferroelectric memory device having a multiple layer structure of  FIG. 8 ; 
           [0032]      FIG. 11  is a diagram illustrating a unit array of the nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0033]      FIG. 12  is a diagram illustrating a nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0034]      FIG. 13  is a diagram illustrating a write operation of the nonvolatile ferroelectric memory according to an embodiment of the present invention; 
           [0035]      FIG. 14  is a timing diagram illustrating a write operation of high data in the nonvolatile ferroelectric memory device according to an embodiment of the present invention; 
           [0036]      FIG. 15  is a timing diagram illustrating a write operation of low data and high data maintenance in the nonvolatile ferroelectric memory device according to an embodiment of the present invention; and 
           [0037]      FIG. 16  is a timing diagram illustrating a sensing operation of cell data in the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0038]    The present invention will be described in detail with reference to the accompanying drawings. 
         [0039]      FIGS. 2   a  to  2   c  are diagrams illustrating a cross section of a cell and its symbol of a nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0040]      FIG. 2   a  is a cross-sectional diagram illustrating a unit cell in a direction in parallel with a word line. 
         [0041]    A bottom word line  10  formed in the bottom layer of the unit cell is arranged in parallel with a word line  17  formed in the top layer of the unit cell. Here, the bottom word line  10  and the word line  17  are selectively driven by the same row address decoder (not shown). An oxide layer is formed on the bottom word line  10 , and a floating channel layer  15  comprising a P-type channel region  12  is formed on the oxide layer  11 . 
         [0042]    A ferroelectric layer  16  is formed on the floating channel layer  15 , and the word line  17  is formed on the ferroelectric layer  16 . 
         [0043]      FIG. 2   b  is a cross-sectional diagram illustrating a unit cell in a direction perpendicular to the word line. 
         [0044]    The oxide layer  11  is formed on the bottom word line  10 . The floating channel layer  15  is formed on the insulating layer  11 . Here, a drain region  13  and a source region  14  are formed with a N-type, and the channel region  12  is formed with a P-type in the floating channel layer  15 , which becomes at a floating state. 
         [0045]    For a semiconductor of the floating channel layer  15 , materials such as a carbon nano tube, silicon and Ge (Germanium) can be used. The ferroelectric layer  16  is formed on the P-type channel region  12  of the floating channel layer  15 , and the word line  17  is formed on the ferroelectric layer  16 . 
         [0046]    As a result, the nonvolatile ferroelectric memory device according to an embodiment of the present invention reads and writes data by using a channel resistance of the floating channel layer  15  which is differentiated by polarization states of the ferroelectric layer  16 . That is, when the polarity of the ferroelectric layer  16  induces positive charges to the channel region  12 , the memory cell becomes at a high resistance state, so that the channel is turned off. On the contrary, when the polarity of the ferroelectric layer  16  induces negative charges to the channel region  12 , the memory cell becomes at a low resistance state, so that the channel is turned on. 
         [0047]    The above-described unit memory cell according to the embodiment of the present invention is represented by a symbol shown in  FIG. 2   c.    
         [0048]      FIGS. 3   a  and  3   b  are diagrams illustrating write and read operations on high data of the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0049]    Referring to  FIG. 3   a , when data “1” is written, a positive voltage &lt;+V&gt; is applied to the bottom word line  10 , and a negative voltage &lt;−V&gt; is applied to the word line  17 . Here, the drain region  13  and the source region  14  are become at a ground voltage &lt;GND&gt; state. 
         [0050]    In this case, a voltage is applied between the ferroelectric layer  16  and the P-type channel region  12  of the floating channel layer  15  by voltage division of a capacitor between the ferroelectric layer  16  and the oxide layer  11 . 
         [0051]    Then, positive charges are induced to the channel region  12  depending on the polarity of the ferroelectric layer  16 , so that the memory cell becomes at the high resistance state. Here, since the positive charges are induced to the channel region  12 , and the drain region  13  and the source region  14  are at the ground state, the channel region  12  is kept off. As a result, the data “1” is written in all memory cells at the write mode. 
         [0052]    Referring to  FIG. 3   b , when the data “1” is read, the ground voltage &lt;GND&gt; is applied to the bottom word line  10  and the word line  17 . Here, since the positive charges are induced to the channel region  12 , and the drain region  13  and the source region  14  are at the ground state, the channel region  12  is kept off. 
         [0053]    As a result, at the read mode, the data “1” stored in the memory cell is read. Here, when a low voltage difference is applied to the drain region  13  and the source region  14 , small current flows because the channel region  12  is turned off. 
         [0054]      FIGS. 4   a  and  4   b  are diagrams illustrating write and read operation on low data of the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0055]    Referring to  FIG. 4   a , when data “0” is written, a positive voltage &lt;+V&gt; is applied to the bottom word line  10  and the word line  17 . Here, the drain region  13  and the source region  14  are become at a ground voltage &lt;GND&gt; state. 
         [0056]    In this case, since negative charges are induced to the channel region  12 , and the drain region  13  and the source region  14  are at the ground state, the channel region  12  is kept on. As a result, the channel region  12  is turned on, so that a ground voltage flows. 
         [0057]    A high voltage is formed between the ground voltage formed in the channel region  12  and the positive voltage &lt;+V&gt; applied from the word line  17 . Then, negative charges are induced to the channel region  12  depending on the polarity of the ferroelectric layer  16 , so that the memory cell becomes at a low resistance state. As a result, the data “0” is written in the memory cell at the write mode. 
         [0058]    Meanwhile, while the data “1” is stored, the positive voltage &lt;+V&gt; is applied to the drain region  13  and the source region  14 . When the positive voltage &lt;+V&gt; is applied to the bottom word line  10  and the word line  17 , the channel region  12  is turned off. As a result, the ground voltage cannot flow in the channel region  12 . 
         [0059]    In this case, a voltage difference is not generated between the positive voltage of the channel region  12  at the floating state and the positive voltage &lt;+V&gt; of the word line  17 . Thus, the polarity change of the ferroelectric layer  16  is not generated but the previous polarity state can be maintained. As a result, the data “0” is written in the cell selected after the data “1” is written. 
         [0060]    Referring to  FIG. 4   b , when the data “0” is read, the ground voltage &lt;GND&gt; is applied to the bottom word line  10  and the word line  17 . Here, since the channel region  12  is turned on even when a low voltage difference is applied between the drain region  13  and the source region  14 , a large amount of current can flow. As a result, the data “0” stored in the memory cell is read at the read mode. 
         [0061]    Therefore, at the read mode, the data maintaining characteristic of the cell can be improved because the word line  17  and the bottom word line  10  are controlled at the ground level so that a voltage stress is not applied to the ferroelectric layer  16 . 
         [0062]      FIG. 5  is a layout cross-sectional diagram illustrating the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0063]    In the embodiment, a plurality of word lines WL are arranged in parallel with a plurality of bottom word lines BWL in a column direction. A plurality of bit lines BL are arranged perpendicular to the plurality of word lines WL. Also, a plurality of unit cells C are located where the plurality of word lines WL, the plurality of bottom word lines BWL and the plurality of bit lines BL are crossed. 
         [0064]      FIGS. 6   a  and  6   b  are cross sectional diagrams illustrating the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0065]      FIG. 6   a  is a diagram illustrating a cross section of the cell array in a direction (A) in parallel with the word line WL of  FIG. 5 . 
         [0066]    In the cell array according to the embodiment of the present invention, a plurality of oxide layers  11  are formed on the bottom word line  10 , and a plurality of P-type channel regions  12  are formed on the plurality of oxide layers  11 . A plurality of ferroelectric layers  16  are formed on the plurality of channel regions  12 , and the word line  17  is formed in parallel with the bottom word line  10  on the plurality of ferroelectric layers  16 . As a result, a plurality of cells are connected between one word line WL_ 1  and one bottom word line BWL_ 1 . 
         [0067]      FIG. 6   b  is a diagram illustrating a cross section of the cell array in a direction (B) perpendicular to the word line WL of  FIG. 5 . 
         [0068]    In the cell array according to the embodiment of the present invention, the oxide layer  11  is formed on each bottom word line BWL_ 1 , BWL_ 2  and BWL_ 3 . The floating channel layer  15  comprising the N-type drain region  13 , the P-type channel region  12  and the N-type source region  14  connected serially is formed on the oxide layer  11 . 
         [0069]    Here, the N-type drain region  13  can be used as a source region in the adjacent cell, and the N-type source region  14  can be used as a drain region in the adjacent cell. That is, the N-type region is used in common as a drain region and a source region in the adjacent cell. 
         [0070]    The ferroelectric layer  16  is formed on each channel region  12  of the floating channel layer  15 , and the word lines WL_ 1 , WL_ 2  and WL_ 3  are formed on the ferroelectric layer  16 . 
         [0071]      FIG. 7  is a cross-sectional diagram illustrating a nonvolatile ferroelectric memory device having a multiple layer structure according to an embodiment of the present invention. 
         [0072]    Referring to  FIG. 7 , the unit cell array shown in  FIG. 6   b  is deposited as a multiple layer structure. Each unit cell array is separated by the oxide layer  18 . 
         [0073]      FIG. 8  is a diagram illustrating a nonvolatile ferroelectric memory device according to another embodiment of the present invention. 
         [0074]    In another embodiment, the bottom word line  10  is used in common in a predetermined cell array. A plurality of word lines WL are arranged in a column direction, and a plurality of bit lines BL are arranged in a row direction. A plurality of unit cells C are located where the plurality of word lines WL and the plurality of BL are crossed. 
         [0075]      FIGS. 9   a  and  9   b  are cross-sectional diagrams illustrating the nonvolatile ferroelectric memory device of  FIG. 8 . 
         [0076]      FIG. 9   a  is a diagram illustrating a cross section of a cell array in a direction (C) in parallel with the word line WL of  FIG. 8 . 
         [0077]    In the cell array according to the embodiment of the present invention, a plurality of oxide layers  11  are formed on the bottom word line  10 , and a plurality of P-type channel regions  12  are formed on the plurality of insulating layers  11 . A plurality of ferroelectric layers  16  are formed on the plurality of channel regions  12 , and the word line  17  is formed in parallel with the bottom word line  10  on the plurality of ferroelectric layers  16 . Thus, a plurality of cells are connected between one word line WL_ 1  and one bottom word line BWL_ 1 . 
         [0078]      FIG. 9   b  is a diagram illustrating a cross section of a cell array in a direction (D) perpendicular to the word line WL of  FIG. 8 . 
         [0079]    In the cell array according to the embodiment of the present invention, the oxide layer  11  is formed on the bottom word lines BWL_ 1 , BWL_ 2  and BWL_ 3  connected in common. The floating channel layer  15  comprising the N-type drain region  13 , the P-type channel region  12  and the N-type source region  14  is formed on the oxide layer  11 . The ferroelectric layer  16  is formed on each channel region  12  of the floating channel layer  15 , and the word lines WL_ 1 , WL_ 2  and WL_ 3  are formed on the ferroelectric layer  16 . 
         [0080]      FIG. 10  is a cross-sectional diagram illustrating a nonvolatile ferroelectric memory device having a multiple layer structure of  FIG. 8 . 
         [0081]    Referring to  FIG. 10 , the unit cell array shown in  FIG. 9   b  is deposited as a multiple layer structure. Each unit cell array is separated by the oxide layer  18 . 
         [0082]      FIG. 11  is a diagram illustrating a unit array of the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0083]    In the embodiment, the unit array of  FIG. 11  comprises switching elements N 1 , N 2  and a plurality of memory cells Q 1 ˜Qm. Here, the switching element N 1 , which is connected between the bit line BL and the memory cell Q 1 , has a gate to receive a selecting signal SEL_ 1 . The switching element N 2 , which is connected between a sensing line S/L and the memory cell Qm, has a gate to receive a selecting signal SEL_ 2 . 
         [0084]    The plurality of memory cells Q 1 ˜Qm, which are connected serially between the switching elements N 1  and N 2 , selectively perform a switching operation by word lines WL_ 1 ˜WL_m and bottom word lines BWL_ 1 ˜BWL m. The detailed structure of each memory cell Q 1 ˜Qm is shown in  FIG. 2   b . Thus, a source of the memory cell Q 1  is connected to the switching element N 1 , and a drain of the memory cell Qm is connected to the switching element N 2 . 
         [0085]      FIG. 12  is a diagram illustrating a nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0086]    In the embodiment, a plurality of unit cell arrays  20 ˜ 23  are arranged where a plurality of bit lines BL_ 1 ˜BL_n and a plurality of sensing lines S/L_ 1 ˜S/L_n are crossed in row and column directions. The structure of each unit cell array  20 ˜ 23  is shown in  FIG. 5 . The plurality of bit lines BL_ 1 ˜BL_n are connected one by one to a plurality of sense amplifiers  30 . 
         [0087]      FIG. 13  is a diagram illustrating a write operation of the nonvolatile ferroelectric memory according to an embodiment of the present invention. 
         [0088]    In the embodiment, a write operation cycle can be divided into two sub operation regions. That is, the data “1” is written in the first sub operation region, and the data “0” is written in the second sub operation region. 
         [0089]    A high voltage is applied to the bit line BL in a predetermined period when the data “1” is required to be preserved. As a result, a value of the data “1” written in the first sub operation region can be preserved in the memory cell. 
         [0090]      FIG. 14  is a timing diagram illustrating a write operation of high data in the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0091]    First, suppose that the memory cell Q 1  shown in  FIG. 5  is selected when the data “1” is written. A period t 0  is defined as a precharge period of the memory cell. 
         [0092]    In a period t 1 , when the selecting signals SEL_ 1  and SEL_ 2  transit to ‘high’, the switching elements N 1  and N 2  are turned on. As a result, the bit line BL is connected to a source of the memory cell Q 1 , and the sensing line S/L is connected to a drain of the memory cell Qm. 
         [0093]    Here, a plurality of word lines WL_ 1 ˜WL_m and a plurality of bottom word lines BWL_ 1 ˜BWL_m are maintained at a low level. Then, the bit line BL_ 1  and the sensing line S/L_ 1  are maintained at a low state. 
         [0094]    In a period t 2 , the rest of the bottom word lines BWL_ 2 ˜BWL_m except the bottom word line BWL_ 1  connected to the selected memory cell Q 1  transit to ‘high’. As a result, the ground voltage &lt;GND&gt; is applied to a drain and a source of the memory cell Q 1 . 
         [0095]    Next, in a period t 3 , a negative voltage VNEG is applied to the word line WL_ 1  connected to the selected memory cell Q 1 . In a period t 4 , the bottom word line BWL_ 1  transits to ‘high’. As shown in  FIG. 3   a , a high voltage is applied to the ferroelectric layer  16  by voltage division of the word line WL_ 1  and the bottom word line BWL_ 1 , so that the data “1” is written. 
         [0096]    In a period t 5 , the word line WL_ 1  and the bottom word line BWL_ 1  are transited to the ground state, again. In a period t 6 , the rest of the bottom word lines BWL_ 2 ˜BWL_m are transited to the ground state, so that the write operation is completed. Thereafter, in a period t 7 , when the selecting signals SEL_ 1  and SEL_ 2  transit to ‘low’, the switching elements N 1  and N 2  are turned off. 
         [0097]      FIG. 15  is a timing diagram illustrating the write operation of the data “0” and the maintenance operation of the data “1” in the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0098]    First, suppose that the memory cell Q 1  shown in  FIG. 5  is selected when the data “0” is written. A period t 0  is defined as a precharge period of the memory cell. 
         [0099]    In a period t 1 , when the selecting signal SEL_ 1  transits to ‘high’, the switching element N 1  is turned on. As a result, the bit line BL is connected to the source of the memory cell Q 1 . 
         [0100]    Here, the selecting signal SEL_ 2 , the plurality of word lines WL_ 1 ˜WL_m and the plurality of bottom word lines BWL_ 1 ˜BWL_m are maintained at the low state. The bit line BL_ 1  and the sensing line S/L_ 1  are maintained at the low state. 
         [0101]    Thereafter, in a period t 2 , all bottom word lines BWL_ 1 ˜BWL_m transit to ‘high’. As a result, all of the memory cells Q 1 ˜Qm are connected to the bit line BL through the bottom word lines BWL_ 1 ˜BWL_m, so that data applied to the bit line BL can be transmitted to all of the cells Q 1 ˜Qm. 
         [0102]    In a period t 3 , when the data to be written in the memory cell Q 1  is “0”, the bit line BL_ 1  is continuously maintained at the ground voltage state. On the other hand, the bit line BL_ 1  transits to ‘high’ when the data “1” stored in the memory cell Q 1  is required to be maintained. 
         [0103]    In a period t 4 , the word line WL_ 1  transits to ‘high’. As shown in  FIG. 4   a , electrons are accumulated in the P-type channel region  12  of the memory cell Q 1  by the word line WL_ 1 . Then, the positive voltage is applied to the word line WL_ 1 , and a threshold voltage difference is generated. Thus, the polarity is formed so that channel electrons may be induced to the ferroelectric layer  16 . As a result, the data “0” is written in the memory cell Q 1 . 
         [0104]    When the data “1” stored in the memory cell Q 1  is required to be maintained, a high voltage is applied to the bit line BL_ 1 , so that a voltage of the bit line BL_ 1  is applied to the memory cell Q 1 . As a result, since the electrons are prevented from being formed in the channel region  12 , the data “1” can be preserved. 
         [0105]    Thereafter, in a period t 5 , the word line WL_ 1  is transited to the ground state. In a period t 6 , all of the bottom word lines BWL_ 1 ˜BWL_m and the bit line BL_ 1  are transited to the ground state, so the write operation is completed. In a period t 7 , when the selecting signal SEL_ 1  transits to ‘low’, the switching element N 1  is turned off. 
         [0106]      FIG. 16  is a timing diagram illustrating a sensing operation of cell data in the nonvolatile ferroelectric memory device according to an embodiment of the present invention. 
         [0107]    First, suppose that the memory cell Q 1  shown in  FIG. 5  is selected when the data is sensed. A period t 0  is defined as a precharge period of the memory cell. 
         [0108]    In a period t 1 , when the selecting signals SEL_ 1  and SEL_ 2  transit to ‘high’, the switching elements N 1  and N 2  are turned on. As a result, the bit line BL is connected to the source of the memory cell Q 1 , and the sensing line S/L is connected to the drain of the memory cell Qm. 
         [0109]    Here, the plurality of word lines WL_ 1 ˜WL_m and the plurality of bottom word lines BWL_ 1 ˜BWL_m are maintained at the low state. The sense amplifier  30 , the bit line BL_ 1  and the sensing line S/L_ 1  are maintained at the low state. 
         [0110]    Thereafter, in a period t 2 , the rest of the bottom word lines BWL_ 2 ˜BWL_m except the bottom word line BWL_ 1  connected to the selected memory cell Q 1  transits to ‘high’. As a result, the rest memory cells Q 2 ˜Qm except the selected memory cell Q 1  are connected to the sensing line S/L_ 1 . 
         [0111]    Here, the plurality of word lines WL_ 1 ˜WL_m are maintained all at the ground state. Thus, the flowing of current between the bit line BL_ 1  and the sensing line S/L is determined depending on the polarity state formed in the memory cell Q 1 . 
         [0112]    In a period t 3 , when the sense amplifier  30  is operated so that a sensing voltage is applied to the bit line BL_ 1 , the flowing of current of the bit line BL_ 1  is determined depending on the state of the memory cell Q 1 . 
         [0113]    As shown in  FIG. 3   b , when current is not applied to the bit line BL_ 1 , it is understood that the data “1” is stored in the memory cell Q 1 . On the other hand, as shown in  FIG. 4   b , when a current over a predetermined value is applied to the bit line BL_ 1 , it is understood that the data “0” is stored in the memory cell Q 1 . 
         [0114]    In a period t 4 , when the operation of the sense amplifier  30  is stopped, the bit line BL_ 1  transits to ‘low’, so that the sensing operation is completed. In a period t 5 , the plurality of bottom word lines BWL_ 2 ˜BWL_m transit to ‘low’. In a period t 6 , when the selecting signals SEL_ 1  and SEL_ 2  transit to ‘low’, the switching elements N 1  and N 2  are turned off. 
         [0115]    Although the floating channel  15  comprising the N-type drain region  13 , the P-type channel region  12  and the N-type source region  14  is exemplified here, the present invention is not limited but the floating channel layer  15  can comprise a P-type drain region, a P-type channel region and a P-type source region. 
         [0116]    As described above, in an embodiment of the present invention, data of a cell are not destroyed at a read mode by using a NDRO (Non Destructive Read Out). As a result, reliability of the cell can be improved at a low voltage of a nano scale ferroelectric cell and a read operation speed can be also improved. Additionally, a plurality of ferroelectric unit cell arrays are deposited to improve integrated capacity of the cell, thereby reducing the whole size of the cell. 
         [0117]    While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.