Abstract:
A circuit for attenuating undesired electrical aberrations associated with digital-to-analog converters is provided. Specifically, the circuit is a non-linear filter for attenuating undesired false or spurious electronic signals superimposed on the output waveform of a digital-to-analog converter when the digital word input signal is changed.

Description:
This is a continuation, of application Ser. No. 786,166 filed Apr. 11, 1977 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     As is well known, several known systems receive a digital word as an input signal and converts such signal to an analog current or analog voltage. Generally, these systems are known as digital-to-analog converters or DAC&#39;s. The analog output, however, contains false or spurious electronic signals caused by unequal propagation delays among the bits arriving at the input of the DAC or by variations in the transient responses of the binary weighted elements within the DAC or by a combination of both. 
     Known prior art for attenuating these undesired spurious signals has been to utilize conventional low pass linear filters. These filters can be used to make the output waveform smoother, but the spurious signals are not really eliminated. Rather, the energy within the spurious signals is only redistributed. In addition to low pass linear filters, the prior art also uses sample and hold circuits when the transition frequencies are low. These type circuits are quite expensive and complicated, but do attenuate the electrical aberrations. 
     SUMMARY OF INVENTION 
     The present invention overcomes the above-described problems associated with attenuating undesired electrical aberrations by providing a non-linear filter which provides a high small-signal, bandwidth amplifier which is slew-rate limited. The derivative of the output is constrained within specific limits, while the small-signal bandwidth of a signal within such limits is high. 
     It is therefore an object of the present invention to provide a filter for a digital-to-analog converter which overcomes the disadvantages of the prior art. 
     It is another object of the present invention to provide a non-linear filter for attenuating undesired false or spurious electronic signals. 
     IT IS YET ANOTHER OBJECT OF THE PRESENT INVENTION TO PROVIDE A NON-LINEAR FILTER FOR ATTENUATING UNDESIRED FALSE OR SPURIOUS ELECTRONIC SIGNALS SUPERIMPOSED ON THE OUTPUT WAVEFORMS OF DIGITAL-TO-ANALOG CONVERTERS. 
     It is still yet another object of the present invention to provide a non-linear filter having a high small-signal bandwidth amplifier which is slew-rate limited. 
     The subject matter of the present invention is particularly pointed out and distinctly claimed in the concluding portion of this specification. The invention, however, both as to organization and method of operation, together with further advantages and objects thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a hybrid block and circuit diagram of the filter for attenuating undesired electrical aberrations in accordance with the present invention; 
     FIG. 2 is a graph of a typical input signal or data word which is to be converted to an analog signal; 
     FIG. 3 is a graph of a typical output analog signal obtained from a digital-to-analog converter; 
     FIG. 4 is a graph of the output signal obtained after filtering in accordance with the present invention; 
     FIG. 5 is a schematic diagram of a conventional current source used in the FIG. 1 embodiment; 
     FIG. 6 is a schematic diagram of a conventional buffer amplifier used in the FIG. 1 embodiment; and 
     FIG. 7 is a schematic diagram of an additional circuit which may be used with the FIG. 1 embodiment to change the characteristics of the filter. 
    
    
     DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, in accordance with the present invention, a digital-to-analog converter, DAC 10, as known from the prior art is connected to an input terminal 12. Applied to input terminal 12 is a digital word such as the input signal shown in FIG. 2. Accordingly, DAC 10 represents a typical digital-to-analog converter for translating or converting the digital word input signal to an analog waveform; the analog waveform being a current waveform in the embodiment shown. It should be understood, however, that DAC 10 may be of the multiplying type. As DAC 10 is of conventional design, no detailed discussion thereof is believed necessary. However, for those who desire more information on digital-to-analog converters, see &#34;Integrated Electronics Analog and Digital Circuits and Systems&#34; by Millman and Halkias, copyright 1972 by McGraw-Hill, Inc. 
     The output of DAC 10 may be the waveform shown in FIG. 3. This typical waveform is, say, a step waveform converted from the input digital word shown in FIG. 2. This DAC output waveform contains electrical spikes or pulses whenever the input digital word is changed. The spikes, again, are normally caused by unequal propagation delays among the bits arriving at the input, or are caused by variations in the transient response of the binary weighted elements within the digital-to-analog converter, or are caused by a combination of both. (See &#34;Computer Logic Design&#34; by M. Mano, copyright 1972 by Prentice-Hall, Inc. for definitions and understanding of &#34;bits&#34; and &#34;binary weighted elements.&#34;) 
     The output of DAC 10 is applied to the inverting input (-) of an amplifier 14 having two output lines 16 and 18. Amplifier 14 has a noninverting input (+) coupled to ground. 
     Output lines 16 and 18 are used to drive the bases of a pair of emitter coupled PNP transistors Q1 and Q2, respectively. This differential transistor pair is biased such that a common emitter current 2I flows through an emitter resistor 20 as indicated in the drawing. The collector of transistor Q1 as well as the collector of ransistor Q2 is coupled to a current mirror 22. As connected, the transistors Q1 and Q2 may have a collector current that ranges from 0 to 2I. It should be mentioned that the resistor 20 and current sink 22 are also coupled to operating potentials which are provided on power supply bus lines 24 and 26 respectively. 
     A capacitor 28 has one terminal thereof grounded whereas the other terminal is coupled to a common line 30 which is disposed between a junction formed by the connection of the collector of transistor Q2 and the current mirror 22, and the input of a buffer amplifier 32. As connected, the capacitor 28 has available current that ranges from -2I to +2I, and the terminal voltage of capacitor 28 changes at a rate limited by ±2I/C volts/sec. Buffer amplifier 32 presents a high impedance to the capacitor and produces a low impedance output at output terminal 34. 
     The circuit is completed or closed through a feedback means such as the resistor 36 disposed between the inverting (-) input of the amplifier 14 and the output terminal 34. The feedback means is, of course, utilized to determine the amplitude of the output signal which may be, for example, the waveform shown in FIG. 4. 
     Basically, the principle of the circuit according to the present invention is to operate as a non-linear filter to provide a high small-signal bandwidth amplifier which is slew-rate limited. The derivative of the output is contrained within specific limits, while the small-signal bandwidth of the output signal within such limits is high. The slew-rate must, of course, be higher than the maximum desired rate of change of the output signal. 
     Reference should now be made to FIG. 5 wherein is shown current mirror 22 in detailed form. The mirror comprises an NPN transistor Q3 whose collector is directly coupled to the collector of transistor Q2 and whose emitter is coupled to the bus 26 via emitter resistor 50. The base of transistor Q3 is biased and stabilized, and made to operate as a current mirror arrangement in a conventional manner via the series connected network comprising resistor 52 and diode connected transistor Q4 disposed between the collector of transistor Q1 and bus 26. (See U.S. Pat. No. 3,939,434 for alternative current mirror.) 
     In FIG. 6 there is shown the buffer amplifier 32. As can be discerned, amplifier 32 comprises an emitter follower NPN transistor Q5 whose collector is coupled, and usually bypassed, to bus 24 whereas its emitter is coupled to the bus 26 via emitter resistor 54. The base is, of course, coupled to the line 30. 
     Before considering the operation of the overall circuit in detail, while the applicants do not wish to be limited to any particular set of values, the following values have proved useful in one embodiment of the subject invention: 
     
         ______________________________________Amplifier 14      Fairchild 733CResistor 20       2.1KΩ, 1/8 Watt, 1%Capacitor 28      0.068 ufd, ceramic 50VResistor 36       2.0KΩ, 1/8 Watt, 1%Q1, Q2            Motorola MPS-H81Q3, Q4, Q5        2N4124Resistors 50, 52  1.07KΩ, 1/8 Watt, 1%Resistor 54       1.5KΩ, 1/8 Watt, 1%Power Supply Bus 24             +15 VoltsPower Supply Bus 26             -15 Volts______________________________________ 
    
     These above-listed values provide a slew rate of about 0.515×10 4  volt/sec or 194 μsec/volt as hereinafter shown. Assume that 2I equals 3.5 mA and that the voltage changes by 10 volts so that: ##EQU1## by taking the reciprocals, about 194 μsec/volt. 
     Operation of the filter in accordance with the subject drawings of the present invention will now be considered. Basically, the output of DAC 10 is coupled via amplifier 14 wherein it is treated to the advantages of high-gain amplification and converted to a double-ended signal. The amplifier must, of course, provide a high gain since the overall filter is an operational amplifier with feedback. 
     The double-ended output signal then drives the transistor pair Q1, Q2 operating as a current switch for steering current into or away from the capacitor 28. The terminal voltage across the capacitor, due to the current therein, is then applied via buffer amplifier 32 to the output terminal 34. As has been previously stated, buffer amplifier 32 provides a high impedance for capacitor 28 and a low impedance to the output. 
     While there has been shown and described one preferred embodiment of the present invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing therefrom in its broader aspects. For example, it may be advantageous to increase the slew rate properties of the filter. Accordingly, in FIG. 7 there is shown an additional circuit for accomplishing this task. 
     As shown, the additional circuit comprises a grounded emitter NPN transistor switch Q6 whose base may be controlled remotely via a line 100. Connected to line 100 may be, for example, a series connected resistor 102 and a two position switch 104. With the switch 104 in the position shown, transistor Q6 is non-conducting. Consequently, there will be no collector current flowing through load resistors 106 and 108 disposed between bus 24 and the collector of transistor Q6. Consequently, a transistor Q7, which is preferrably of the PNP type and whose emitter-base junction is disposed in parallel with the resistor 108, is also non-conductive. 
     However, when switch 104 is switched into a second position, which connects resistor 102 to the bus 24, transistor Q6 turns on. As a result of current through load resistors 106 and 108, transistors Q7 becomes conductive. Collector current of Q7 is therefore available via load resistor 110 for application to the emitters of the already mentioned transistors Q1 and Q2. This additional current, along with the current 2I causes capacitor 28 to be charged and discharged at a much faster rate to thereby increase the slew rate. 
     Again, applicants hereinafter list a set of values which have proved useful in one embodiment of the additional circuit which will change the filter slew rate to about 68 μsec/volt, but do not wish to be limited thereto: 
     
         ______________________________________Q6              2N3904Q7              2N3906R102            39KΩ, 1/4 Watt, 5%R106            47KΩ, 1/4 Watt, 5%R108            100KΩ, 1/4 Watt, 5 %R110            1KΩ, 1/8 Watt, 1%______________________________________ 
    
     It should also be mentioned that in the FIG. 1 embodiment, the amplifier 14 requires power supply connections which are usually bypassed and also requires that a resistor be disposed between each output line and ground for properly interfacing with the transistors Q1 and Q2. Additionally, the grounded input of amplifier 14 may be grounded by way of an impedance means such as, for example, a parallel RC network. These above discussed connections have not been shown as they are believed to be well known techniques. 
     Therefore, the appended claims are intended to cover all changes and modifications as fall within the true spirit and scope of the invention.