Abstract:
Systems for driving displays are provided. In this regard, an representative system for driving a display comprises a signal driving circuit having a first shift register and a second shift register coupled in series to the first shift register. The signal driving circuit is operative to drive a display according to inputs provided by only two clock signals.

Description:
BACKGROUND  
       [0001]     The invention relates to display devices.  
         [0002]     High definition, multicolor display, low power consumption, lower voltage requirements and light weight have made liquid crystal displays (LCDs) a leading display device technology. LCDs have been used for several years as mobile information displays in, for example, personal digital assistants (PDAs), portable computers, mobile phones, and the like.  
         [0003]     Recently, complementary metal oxide semiconductor (CMOS) shift register circuits have been widely applied in low-temperature poly-silicon (LTPS) LCDs. However, at least eight masks typically are required to form a CMOS shift register circuit during fabrication, and thus, costs are increased. For cost reduction, positive metal-oxide semiconductor (PMOS) shift registers, which require fewer masks, are used frequency by LCD makers.  
         [0004]      FIG. 1  shows a conventional signal driving circuit comprising PMOS shift registers. As shown, the signal driving circuit  100  in the panel  10  requires four clock signals provided by an external integrated circuit (IC) to driving the PMOS shift registers via four FPC pins, and four sampling and holding units (L/S) to sample and hold the four clock signals. Because of the increased sampling and holding units (S/L), the power consumption and chip (layout) area are increased no matter they are integrated to the IC or the display panel, and thus cost is increased. Further, due to increase in FPC pins, contact reliability between the IC and panel by FPC becomes an important issue.  
       SUMMARY  
       [0005]     Systems for driving displays are provided. In this regard, an embodiment of such a system comprises a signal driving circuit. The signal driving circuit comprises: a plurality of shift registers connected in series, each comprising a first control terminal, a second control terminal, an input terminal and an output terminal, each being controlled by a first clock signal and a second clock signal and outputting corresponding driving pulses in turn according to a start pulse. The output terminal of an N th  of the shift registers is coupled to the input terminal of an N+1 th  of the shift registers, the output terminal of the N+1 th  shift register is coupled to the second control terminal of the N th  shift register, and the first control terminals of the N th  and the N+1 th  shift registers are coupled to the first clock signal and the second clock signal, respectively.  
         [0006]     Another embodiment of a system for driving a display comprises a signal driving circuit. The signal driving circuit comprises: a first shift register comprising a first control terminal coupled to a first clock signal, an input terminal coupled to a start pulse, a second control terminal, and an output terminal, wherein the first shift register outputs a first driving pulse according to the first clock signal and the start pulse; and a second shift register comprising a first control terminal coupled to a second clock signal, an input terminal coupled to the output terminal of the first shift register, an output terminal coupled to the second control terminal of the first shift register, and a second control terminal, wherein the second shift register is operative to output a second driving pulse according to the first clock signal and the first driving pulse, and the first shift register is disabled by the second driving pulse from the second shifter register.  
         [0007]     Another embodiment of a system for driving a display comprises a signal driving circuit having a first shift register and a second shift register coupled in series to the first shift register. The signal driving circuit is operative to drive a display according to inputs provided by only two clock signals. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     The invention can be more fully understood by the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:  
         [0009]      FIG. 1  shows a conventional signal driving circuit having PMOS shift registers;  
         [0010]      FIG. 2  shows an embodiment of a signal driving circuit;  
         [0011]      FIG. 3  is a timing chart of the embodiment of the signal driving circuit of  FIG. 2 ;  
         [0012]      FIG. 4  shows an embodiment of a shift register;  
         [0013]      FIG. 5  shows another embodiment of a signal driving circuit;  
         [0014]      FIG. 6  shows an embodiment of a pulse generation unit;  
         [0015]      FIG. 7  is a timing chart of the embodiment of the pulse generation unit of  FIG. 6 ;  
         [0016]      FIG. 8  shows an embodiment of a display device incorporating a signal driving circuit; and  
         [0017]      FIG. 9  schematically shows an embodiment of an electronic device incorporating an embodiment of a display device. 
     
    
     DETAILED DESCRIPTION  
       [0018]     Systems are provided that involve the use of signal driving circuits. In this regard,  FIG. 2  shows a first embodiment of a signal driving circuit. As shown, signal driving circuit  200 A comprises  6  shift registers SR 1 ˜SR 6  connected in series. While this embodiment incorporates  6  shift registers, it is to be understood that in other embodiments, other numbers of shift registers can be used. Each shift register SR 1 ˜SR 6  comprises a first control terminal C 1 , a second control terminal C 2 , an input terminal IN and an output terminal OUT. Shift registers SR 1 ˜SR 6  are controlled by a first clock signal CLK 1  and a second clock signal CLK 2  to output corresponding driving pulses in turn, according to a start pulse STP. It is to be noted that the first clock signal CLK 1  and the second clock signal CLK 2  are not inverse to each other, but have a phase difference therebetween.  
         [0019]     The shift register SR 1  comprises a first control terminal C 1  coupled to the first clock signal CLK 1 , a second control terminal C 2  coupled to the output terminal of the shift register SR 2 , an input terminal coupled to the start pulse STP and an output terminal outputting a corresponding driving pulse out 1 . The shift register SR 2  comprises a first control terminal C 1  coupled to the second clock signal CLK 2 , a second control terminal C 2  coupled to the output terminal of the shift register SR 3 , an input terminal coupled to the output terminal of the shift register SR 1  and an output terminal outputting a corresponding driving pulse out 2 . The shift register SR 3  comprises a first control terminal C 1  coupled to the first clock signal CLK 1 , a second control terminal C 2  coupled to the output terminal of the shift register SR 4 , an input terminal coupled to the output terminal of the shift register SR 2  and an output terminal outputting a corresponding driving pulse out 3 .  
         [0020]     The shift register SR 4  comprises a first control terminal C 1  coupled to the second clock signal CLK 2 , a second control terminal C 2  coupled to the output terminal of the shift register SR 5 , an input terminal coupled to the output terminal of the shift register SR 3  and an output terminal outputting a corresponding driving pulse out 4 . The shift register SR 5  comprises a first control terminal C 1  coupled to the first clock signal CLK 1 , a second control terminal C 2  coupled to the output terminal of the shift register SR 6 , an input terminal coupled to the output terminal of the shift register SR 4  and an output terminal outputting a corresponding driving pulse out 5 . The shift register SR 6  comprises a first control terminal C 1  coupled to the second clock signal CLK 2 , a second control terminal C 2  coupled to the first clock signal CLK 1 , an input terminal coupled to the output terminal of the shift register SR 5  and an output terminal outputting a corresponding driving pulse out 6 .  
         [0021]      FIG. 3  is a timing chart of the embodiment of the driving signal circuit of  FIG. 2 . The shift register SR 1  generates corresponding driving pulse out 1  for output to the input terminal of the shift register SR 2 , according to the first clock signal CLK 1  and the start pulse STP. For example, after receiving the start pulse STP at time t 0 , the shift register SR 1  can output the corresponding driving pulse out 1  when the clock signal CLK 1  goes low at time t 1 .  
         [0022]     The shift register SR 2  generates corresponding driving pulse out 2  for output to the input terminal of the shift register SR 3 , according to the second clock signal CLK 2  and the driving pulse out 1  from the shift register SR 1 . For example, after receiving the driving pulse out 1  from the shift register SR 1 , the shift register SR 2  can output the corresponding driving pulse out 2  when the clock signal CLK 2  goes low at time t 2 . Similarly, shift registers SR 3 ˜SR 6  generate and output corresponding driving pulses out 3 -out 6 , according to the driving pulse from the previous stage and the corresponding clock signal CLK 1  or CLK 2 . Namely, the shift registers SR˜SR 6  are controlled by the clock signals CLK 1  and CLK 2  and output corresponding driving pulses out 1 ˜out 6  after receiving the start pulse STP. Further, the corresponding driving pulse out 2  serves not only as a start pulse for the shift register SR 3  but also as a disabling pulse to turn off the shift register SR 1 . Similarly, corresponding driving pulses out 3 ˜out 5  serve not only as a start pulse for the shift registers SR 4 ˜SR 6 , respectively, but also as a disabling pulse to turn off the shift registers SR 2 ˜SR 4 , respectively. In this embodiment, the corresponding driving pulse out 6  serves only as a disabling pulse to turn off the shift register SR 5 . Namely, the previous shift (N th ) register is turned off by the corresponding driving pulse output from the next (N+1 th ) shift register. Note, that in this embodiment shift registers SR 1 ˜SR 6  have the same structure, and are formed solely by PMOS transistors.  
         [0023]      FIG. 4  shows an embodiment of a shift register SRn , in which shift register SRn comprises 18 PMOS transistors. As shown in  FIG. 4 , the transistor M 11  comprises a first terminal coupled to power voltage VDD, a second terminal coupled to transistor M 12 , and a control terminal serving as a input terminal IN. The transistor M 12  comprises a first terminal coupled to the second terminal of the transistor M 11 , a second terminal coupled to a node N 1 , and a control terminal coupled to the input terminal IN.  
         [0024]     The transistor M 21  comprises a first terminal coupled to the node N 1 , a second terminal and a control terminal coupled to the transistor M 22 . The transistor M 22  comprises a first terminal coupled to the second terminal of the transistor M 21 , a second terminal serving as a second control terminal C 2 , and a control terminal coupled to the second control terminal C 2  and the control terminal of the transistor M 21 . The transistor M 31  comprises a first terminal coupled to power voltage VDD, a control terminal coupled to the node N 1  and a second terminal coupled to transistor M 32 . The transistor M 32  comprises a first terminal coupled to the second terminal of the transistor M 31 , a second terminal coupled to a node N 2 , and a control terminal coupled to the node N 1 .  
         [0025]     The transistor M 41  comprises a first terminal coupled to the node N 2 , a control terminal coupled to the input terminal IN and a second terminal coupled to the transistor M 42 . The transistor M 42  comprises a first terminal coupled to the second terminal of the transistor M 41 , a second terminal coupled to the input terminal IN, and a control terminal coupled to the input terminal IN. The transistor M 51  comprises a first terminal coupled to the power voltage VDD, a second terminal coupled to the transistor M 52 , and a control terminal coupled to the node N 2 . The transistor M 52  comprises a first terminal coupled to the second terminal of the transistor M 51 , a second terminal coupled to the transistor M 61 , and a control terminal coupled to the node N 2 . The transistor M 61  comprises a first terminal coupled to the second terminal of the transistor M 52 , a second terminal coupled to the transistor M 62  and a control terminal coupled a first control terminal C 1 . The transistor M 62  comprises a first terminal coupled to the second terminal of the transistor M 61 , a second terminal coupled to the node N 1 , and a control terminal coupled to the first control terminal C 1 .  
         [0026]     The transistor M 71  comprises a first terminal coupled to the node N 2 , a second terminal coupled to the transistor M 72  and a control terminal coupled a ground voltage VSS. The transistor M 72  comprises a first terminal coupled to the second terminal of the transistor M 71 , a second terminal coupled to the transistor M 91 , and a control terminal coupled to the ground voltage VSS. The transistor M 81  comprises a first terminal coupled to the power voltage VDD, a second terminal coupled to the transistor M 82 , and a control terminal coupled to the node N 1 . The transistor M 82  comprises a first terminal coupled to the second terminal of the transistor M 81 , a second terminal serving as an output terminal OUT, and a control terminal coupled to the node N 1 . The transistor M 91  comprises a first terminal coupled to the output terminal OUT, a second terminal coupled to the transistor M 92  and a control terminal coupled the second terminal of the transistor M 72 . The transistor M 92  comprises a first terminal coupled to the second terminal of the transistor M 91 , a second terminal coupled to the first control terminal C 1 , and a control terminal coupled to the second terminal of the transistor M 72 .  
         [0027]     When the input terminal IN receives a start pulse STP (or corresponding driving pulse from a previous stage), the clock signal CLK 2  stays high and the clock signal CLK 1  goes low, transistors M 21 , M 22 , M 31 , M 32 , M 81  and M 82  are turned off and transistors M 11 , M 12 , M 41 , M 42 , M 51 , M 52 , M 61 , M 62 , M 71 , M 72 , M 91  and M 92  are turned on. Since the voltage level of N 2  is low and N 1  is high, voltage level at output terminal will go low following the CLK 1  signal due to M 91  and M 92  turn on (the shift register SRn generates a corresponding driving pulse). When the clock signal CLK 2  stays high and the clock signal CLK 1  goes high, the output point will go high with CLK 1 , node N 2  will remain at low level and N 1  will remain at high level.  
         [0028]     When the clock signal CLK 1  stays high and the clock signal CLK 2  goes low, the transistors M 11 , M 12 , M 41 , M 42 , M 51 , M 52 , M 61 , M 62 , M 91  and M 92  are turned off and the transistors M 21 , M 22 , M 31 , M 32 , M 71 , M 72 , M 81  and M 82  are turned on. Thus, the voltage level at the output terminal OUT goes high due to node N 2  going high and node N 1  goes low. This shift register SRn is disabled.  
         [0029]     Because the signal driving circuit of this embodiment requires only two clock signals and is formed by PMOS shift registers, it potentially provides lower cost solution than conventional signal driving circuits with CMOS shift registers and/or those requiring four clock signals.  
         [0030]      FIG. 5  shows another embodiment of a signal driving circuit. The signal driving circuit  200 B of  FIG. 5  comprises  6  shift registers SR 1 ˜SR 6  and a pulse generation unit  220 . The signal driving circuit  200 B is similar to the circuit  200  shown in  FIG. 2A  expect that an additional pulse generation unit  220  is coupled to the last shift register SR 6 . The pulse generation unit  220  is coupled to the first and second clock signals CLK 1  and CLK 2  and the corresponding driving pulse out 6  from the last shift register SR 6 . For example, the pulse generation unit  220  comprises control terminals A and B coupled to the clock signal CLK 2  and CLK 1  respectively, and an input terminal IN coupled to the output terminal of the last shift register SR 6  and an output terminal OUT coupled to the second terminal of the last shift register SR 6 . The pulse generation unit  220  outputs a disable pulse SF to disable the last shift register SR 6  according to the corresponding driving pulse out 6  and the first and second clock signals.  
         [0031]      FIG. 6  shows an embodiment of the pulse generation unit  220 . In this embodiment, the pulse generation unit  220  is coupled to the shift register SR 6  and comprises 6 PMOS transistors. The transistor M 01  comprises a first terminal coupled to the power voltage VDD, a second terminal coupled to the transistor M 02 , and control terminal coupled to the second control terminal C 2  of the shift register SR 6 . The transistor M 02  comprises a first terminal coupled to the second terminal of the transistor M 01 , a second terminal coupled to a node N 3 , and a control terminal coupled to the second clock signal CLK 2 . The transistor M 03  comprises a first terminal coupled to the node N 3 , a second terminal coupled to the first terminal of the transistor M 04 , and a control terminal coupled to the ground voltage VSS.  
         [0032]     The transistor M 04  comprises a first terminal coupled to the second terminal of the transistor M 03 , a second terminal and a control terminal coupled to the output terminal OUT of shift register SR 6 . The transistor M 05  comprises a first terminal coupled to the second control terminal C 2  of the shift register SR 6 , a second terminal coupled to the transistor M 06  and a control terminal coupled to the clock signal CLK 1 . The transistor M 06  comprises a first terminal coupled to the second terminal of the transistor M 05 , a second terminal coupled to the ground voltage VSS, and a control terminal coupled to the node N 3 .  
         [0033]     When the shift register SR 6  outputs a corresponding driving pulse out at time t 6 , the transistors M 03  and M 04  are turned on such that the voltage level V 3  at the node N 3  goes low, and the transistor M 06  is turned on.  
         [0034]      FIG. 7  is a timing chart of the embodiment of the driving signal circuit of  FIG. 5 . As shown, description of the driving circuit  200 B before time t 7  is similar to that of the driving circuit  200 A shown in  FIG. 2 , and thus is omitted for simplification. Operation of the driving circuit  200 B after time t 7  is disclosed hereinafter with reference to  FIGS. 5, 6  and  7 .  
         [0035]     At time t 7 , the clock signal CLK 1  goes low such that the transistor M 05  is turned on. As transistors M 05  and M 06  are turned on, the second control terminal C 2  of the shift register SR 6  is pulled low, serving as a disabling signal SF to turn off the shift register SR 6 . Even if the clock signal CLK 1  goes high, the voltage level at the second control terminal C 2  of the shift register SR 6  stays low such that the transistor M 01  stays on.  
         [0036]     At time t 8 , the clock signal CLK 2  goes low such that the transistor M 02  is turned on. As transistors M 01  and M 02  are turned on, the voltage level V 3  at the node N 3  is pulled high, and the pulse generation unit  220  is reset and disabled accordingly.  
         [0037]     Pulse generation unit  220  in the signal driving circuit and the connection of the shift registers SR 1 ˜SR 6  further ensure that all shift registers can be disabled by the driving pulse from the next stage and there is no current leakage to the previous stage from the next stage. Thus, output driving pulses output by the shift register SR 1 ˜SR 6  can reach a desired voltage level.  
         [0038]     As shown in  FIG. 8 , an embodiment of a signal circuit can be incorporated into a display device. In particular, display device  400  incorporates a display element  410 , such as an LCD element, and is operatively coupled to a signal driving circuit  412 , such as signal driving circuit  200 A or  200 B, for example. The signal driving circuit outputs a plurality of driving pulses in turn to drive display element  410 . Note that display element  410  can be a plasma display element, an organic light emitting display element, a field emission display (FED) systems, or a cathode ray tube display element in other embodiments.  
         [0039]      FIG. 9  schematically shows an electronic device  500  employing display device  400 . The electronic device  500  may be a portable device such as a PDA, notebook computer, tablet computer, cellular phone, or a display monitor device, for example. Generally, the electronic device  500  includes a housing  510 , the display device  400  and, a DC/DC converter  520 . Further, the DC/DC converter  520  is operatively coupled to the display device  400  and provides an output voltage powering the display device  400  to display images.  
         [0040]     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.