Abstract:
An apparatus determines if a bit of a word is stuck or unchanging. The apparatus inputs test words to be tested, a zero word indicating that all bits have been turned off and a ones word to indicate that all bits have been turned on. A series of logical AND and logical OR operation with the zero word and the ones word and an exclusive OR operation determines if the bit is unchanging.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to a method and apparatus for determining or identifying particular bits which have been stuck or produce the same reading over an extended period of time, despite that these bits have been instructed to change. More particularly, the present invention relates to a method and apparatus for determining whether bits have been stuck or remain the same over an extended period of time for use associated with a high resolution measurement systems, for example a Time Measurement Unit (TMU). 
     BACKGROUND OF THE INVENTION 
     Time Measurement Units are used to measure the time between two waveform signals. The time between two waveform signals are useful in that this information can be used in various ways. In U.S. Pat. No. 4,432,243 to Lowell, for example, a Time Measurement Unit measures the timing of signals transmitted by a transmitter and received by a receiver, and the Time Measurement Unit in turn converts the signals to flow measurements by a processing unit. 
     It can be appreciated that as the requirements for increased accuracy in these types of timing signals with the Time Measurement Unit is increased, the need for more accurate information relating to the time between waveform signals is required. 
     A problem arises particularly in the area of digital signal processing in that the bits of words which are used for the readings of the time measurement unit are important. As the need for accuracy increases, the need for each bit of the word, particularly the low order bits, used to obtain the readings is becoming increasingly important. 
     In digital processing, the magnitude of the signal is usually represented in either a word or double word of computer memory, register bits or the like. These signals may initially be input as an analog signal and subsequently converted to digital signals as they are represented in the word or double word by a series of bits where each bit represents a number. The bit differs from an adjacent bit in the number that the bit represents is different; the bits usually differ by a power of a convenient base, usually two. 
     In most circumstances, the digital value of the waveform signal has sufficient number of bits so that the desired accuracy in the representation of waveform signal can be achieved. In these cases, the high order bits correspond approximately to the magnitude of the signal waveform while the low order bits provide a relatively smaller contribution to the magnitude of the waveform. Consequently, if the high order bits of the word or double word used for the digital value are stuck and not responding to changing readings for the digital, it is very apparent that these bits are stuck since these bits provide a major contribution to the magnitude of the signal waveform. Consequently, it is relatively easy to determine which of these high order bits are stuck or not responding to the changing digital values of the waveform signal. 
     In contrast, while the low order bits may provide little relative contribution to the total magnitude of the waveform signal, these low order bits are becoming increasingly important as the accuracy of the magnitude of the digital waveform of the signal waveform is increased. However, it is increasingly difficult to detect a stuck or non-responding bit to changing readings of the low order bits of the signal waveform since these bits provide a relatively small contribution to the magnitude of the waveform. Thus, when these bits are stuck, little change in magnitude is observed. 
     SUMMARY OF THE INVENTION 
     The present invention provides an apparatus and method to detect and identify which bit or bits that are not responding to an input reading of the signal waveform. 
     The present invention provides through either hardware or software which may or may not be performed on a CPU, an apparatus and method for determining if bits particularly a low order or least significant bits are stuck or do not respond to a changing reading. 
     The present invention also includes an apparatus for determining if a bit of a word is unchanging, including an input device to input a plurality of test words to be tested and to input a zero word to indicate that no bits in the zero word have been turned on and an ones word to indicate that all bits in the ones word have been turned on; coupled to the input device an OR device to perform logical OR operation on a test word of the test words to be tested and the zero word having no bits in the zero word turned on and to output an ORed word as a result of the logical OR operation; an AND device coupled to the input device to perform a logical AND operation on the test word to be tested and the ones word having all bits in the ones word turned on and to output an ANDed word as a result of the logical AND operation; coupled to the OR device and the AND device an XOR device to perform a logical exclusive OR operation on the ORed word and the ANDed word and to form an indication of the unchanging bit. 
     The present invention also includes an additional OR device coupled to the OR device to perform logical OR operation on another test word of the test words and the ORed word and to output another ORed word as a result of the logical OR operation. 
     The present invention includes a further OR device coupled to the additional OR device to perform OR operation on a further test word of the test words and the another ORed word to output a further ORed word as a result of the logical OR operation. 
     The present invention also includes an additional AND device coupled to the AND device to perform AND operation on another test word of the test words and the ANDed word and to output another ANDed word as a result of the logical AND operation. 
     The present invention also includes a further AND device coupled to the additional AND device to perform AND operation on a further test word of the test words and the other ANDed word and to output a further ANDed word as a result of said logical AND operation. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a circuit diagram of the present invention; and 
     FIG. 2 illustrates a flowchart of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Although the present invention has been described in terms of detecting low order bits which may have been stuck, it is to be understood that the present invention can be applied equally to either the high order bits or the low order bits. The detection of the low order bits is used as an example since the low order bits, which may be stuck or do not respond to the readings of the waveform signal, are not easily detected since the relative contribution of these low order bits with respect to the high order bits to the representation of the waveform signal is normally small. The present invention attains successive readings from the input waveform signal and concurrently performs logical &#34;OR&#34; &#34;AND&#34; operations and then performs an XOR operation of the output of the last &#34;OR&#34; &#34;AND&#34; operation. The logical &#34;OR&#34; and logical &#34;AND&#34; operations may be performed in parallel or may be performed one after sequentially. 
     FIG. 1 illustrates a reading device 103 to obtain digital readings of a waveform signal. The first reading from a reading device 103 and hexadecimal F are input to AND gate 102. The output of AND gate 102 is input to AND gate 104 with a second reading output from reading device 103. The output of the AND gate 104 is input with a third reading output from reading device 103 to AND gate 105. The output of AND gate 105 is input with a fourth reading output from the reading device 103 to AND gate 106. The output of the AND gate 106 is input to the exclusive OR gate 302. The first reading is additionally input to the OR gate 202 with the hexadecimal 0. The output of the OR gate 202 is input with the second reading to the OR gate 204. The output of the OR gate 204 is input with the third reading to the OR gate 206. The output of the OR gate 206 is input with the fourth reading to the OR gate 208. The output of the OR gate 208 is input to the exclusive OR gate 302. 
     The following example illustrates the results of the above apparatus and procedure. 
     EXAMPLE: Five 4-bit binary readings are taken. (hex 5,1,8,4) ##STR1## 
     Example 1 illustrates the operation of the logical OR gates and logical AND gates. The four successive readings are hexadecimal 5, hexadecimal 1, and hexadecimal 8, and hexadecimal 4. 
     In operation, a hexadecimal 5 output from the reading device 103 and a hexadecimal F is input to the AND gate 102 outputting a hexadecimal 5 to be input to AND gate 104. A hexadecimal 1 output from the reading device is additionally input into AND gate 104, which outputs a hexadecimal 1. The hexadecimal 1 output from AND gate 104 and a hexadecimal 8 output from the reading device 103 is input to the AND gate 105 to output a hexadecimal 0. A hexadecimal 4 output from the reading device 103 and the hexadecimal 0 output from the AND gate 105 are input to AND gate 106 to output a hexadecimal 0. 
     Correspondingly, a hexadecimal 5 output from the reading device 103 and a hexadecimal 0 is input to OR gate 202 to output a hexadecimal 5. The hexadecimal 5 output from the OR gate 202 is input with a hexadecimal 1 output from the reading device 103 to the OR gate 204. A hexadecimal 5 is output from OR gate 204 with a hexadecimal 8 output from the reading device 103 to OR gate 206 to output a hexadecimal D. The hexadecimal D output from the OR gate 206 and hexadecimal 4 output from the reading device 103 is input to the OR gate 208. The output of the OR gate 208 is a hexadecimal D. A hexadecimal D output from the OR gate 208 and hexadecimal 0 output from the AND gate 106 is input XOR gate 302 which exclusively ORed the inputs to output a hexadecimal 0 which is a binary 1101. This indicates that a second to the lowest bit is stuck at 0. As the number of readings increase of the above-mentioned process, the statistical confidence that a bit is in fact stuck increases. For example, with one reading, the statistical confidence is 50/50 that a bit is stuck and correctly detected as stuck. With two readings, the statistical confidence is 0.5×0.5 or 0.25. Thus, as it can be very clearly seen with only two readings, the statistical confidence decreases to 0.25. Correspondingly, increasing the number of readings, correspondingly increases the probability that the bit is in fact stuck assuming random probability without biasing the input readings. 
     FIG. 2 illustrates a flowchart of a present invention. These steps may be executed by software such as enclosed in the appendix on a computer, a minicomputer or microprocessor in order to obtain the same results. 
     In block 502, the variable save --  and is set to all binary ones. In block 504, the variable save --  or is set to all binary zeros. In block 506, the variable count is set to 0. In block 508, the TMU is read to determine a read value. Blocks 510 and 512 may be either determined sequentially or in parallel. The read value from the TMU is ORed with the save --  or and the save --  or variable is updated with the result of the operation of Block 512. In block 510 the variable save --  and is ANDed with the read value from the TMU and the save --  and is updated with the result of the AND operation of the program. 
     In block 514, the count is tested to determine if it exceeds 128, an arbitrary predetermined limit. If it does, the save --  or variable is exclusively ORed with the save --  and variable in block 520. If the count is less than 128, the predetermined limit, the save --  or is compared with a constant of all logical ones. If they are equal, block 518 is executed. In block 518, the save --  and is compared with a constant of all binary zeros. If they are not equal, block 508 is executed, otherwise block 520 is executed. The result from block 520 provides an indication of the bit which has been stuck or does not respond to the change in readings of the waveform signal. 
     The following is an example of code to perform the above functions. 
     
         __________________________________________________________________________********************************************************************************SUBROUTINE ANA.sub.-- BITS * check bits on analog ramp 1 lower 8 bits are random check, * and &amp; or then xor to see what bits changed * LET ANA1.sub.-- SAVE.sub.-- OR = 0 LET ANA1.sub.-- SAVE.sub.-- AND = &gt;FF LET ANA2.sub.-- SAVE.sub.-- OR = 0 LET ANA2.sub.-- SAVE.sub.-- AND = &gt;FF * GOSUB PRINT.sub.-- MENU(4) PRINT .CR(14) PRINT .CURSOR(8,5), `TAKE TMU MEASUREMENTS AND .OR &amp; .ANDTHE READINGS`,.NCR PRINT .CURSOR(9,5), `TOGETHER TO DETERMINE NON CHANGINGBITS.`, .NCR PRINT .CURSOR(12,5), `RAMP`, .TAB(15),`ORed VALUE`, .NCR PRINT .TAB(30), `ANDed VALUE`, .TAB(46), `BITS`, .NCR PRINT .TAB(60), `STATUS`, .NCR * LET LOOP = 0 CALL READ.sub.-- KEY(K$)                   ; flush keyboard buffer REPEAT  LET .pic(TMU.sub.-- ADDR,TMU.sub.-- CAL1.sub.-- LT.sub.-- ADDR) = 127 -LOOP TMU (&gt;50,6,0)     ; setup matrix to clk.sub.-- tmu * LET READ1 = .pic(TMU.sub.-- ADDR,RD.sub.-- TMU1.sub.-- ANA.sub.-- ADDR).AND &gt;FF LET ANA1.sub.-- SAVE.sub.-- OR = ANA1.sub.-- SAVE.sub.-- OR .OR READ1 LET ANA1.sub.-- SAVE.sub.-- AND = ANA1.sub.-- SAVE.sub.-- AND .ANDREAD1 * PRINT .CURSOR(13,5), `1`, .TAB(15), .HEX(1,4), ANA1.sub.-- SAVE.sub.--or, .NCR PRINT .TAB(30), .HEX(1,4), ANA1.sub.-- SAVE.sub.-- and, .NCR LET LOOP = LOOP + 1 LET EXIT.sub.-- LOOP = 0 IF (ANA1.sub.-- SAVE.sub.-- AND .EQ &gt;0) .AND (ANA1.sub.-- SAVE.sub.-- OR.EQ &gt;FF)  LET EXIT.sub.-- LOOP = 1 ENDIF LET CHG.sub.-- TEST = 0 IF (K$ .EQ `RN`) .OR (K$ .EQ `P`) .OR (.ESC .EQ 1)  LET CHG.sub.-- TEST = 1 ENDIFUNTIL (LOOP .GE 128) .OR CHG.sub.-- TEST .OR EXIT.sub.-- LOOPLET LOOP = 0CALL READ.sub.-- KEY(K$)                   ; flush keyboard bufferREPEAT LET .pic(TMU.sub.-- ADDR,TMU.sub.-- CAL2.sub.-- LT.sub.-- ADDR) = (127 -LOOP) * &gt;100 TMU (&gt;50,6,0)     ; setup matrix to clk.sub.-- tmu * LET READ2 = .pic(TMU.sub.-- ADDR,RD.sub.-- TMU2.sub.-- ANA.sub.-- ADDR).AND &gt;FF LET ANA2.sub.-- SAVE.sub.-- OR = ANA2.sub.-- SAVE.sub.-- OR .OR READ2 LET ANA2.sub.-- SAVE.sub.-- AND = ANA2.sub.-- SAVE.sub.-- AND .ANDREAD2 * PRINT .CURSOR(15,5), `2`, .TAB(15), .HEX(1,4), ANA2.sub.-- SAVE.sub.--or, .NCR PRINT .TAB(30), .HEX(1,4), ANA2.sub.-- SAVE.sub.-- and, .NCR LET LOOP = LOOP + 1 LET EXIT.sub.-- LOOP = 0 IF (ANA2.sub.-- SAVE.sub.-- AND .EQ &gt;0) .AND (ANA2.sub.-- SAVE.sub.-- OR.EQ &gt;FF)  LET EXIT.sub.-- LOOP = 1 ENDIF LET CHG.sub.-- TEST = 0 IF (K$ .EQ `RN`) .OR (K$ .EQ `P`) .OR (.ESC .EQ 1)  LET CHG.sub.-- TEST = 1 ENDIFUNTIL (LOOP .GE 128) .OR CHG.sub.-- TEST .OR EXIT.sub.-- LOOP*LET ANA1.sub.-- SAVE = ANA1.sub.-- SAVE.sub.-- OR .XOR ANA1.sub.--SAVE.sub.-- ANDLET ANA2.sub.-- SAVE = ANA2.sub.-- SAVE.sub.-- OR .XOR ANA2.sub.--SAVE.sub.-- ANDIF ANA1.sub.-- SAVE .EQ &gt;FF LET STR$(1) = `TMU1 ALL BITS CHANGED` LET STR$(3) = &#34;ELSE LET STR$(1) = `THIS BIT DID NOT CHANGE ` LET STR$(3) = `TMU1 RANDOM TEST MAY NOT BE CONCLUSIVE BUT,`ENDIFIF ANA2.sub.-- SAVE .EQ &gt;FF LET STR$(2) = `TMU2 ALL BITS CHANGED` LET STR$(4) = &#34;ELSE LET STR$(2) = `THIS BIT DID NOT CHANGE ` LET STR$(4) = `TMU2 RANDOM TEST MAY NOT BE CONCLUSIVE BUT,`ENDIFPRINT .CURSOR(13,45), .HEX(1,4), ANA1.sub.-- SAVE, .TAB(55), STR$(1),.NCRPRINT .CURSOR(15,45), .HEX(1,4), ANA2.sub.-- SAVE, .TAB(55), STR$(2),.NCRPRINT .CURSOR(20,20), STR$(3), .NCRPRINT .CURSOR(21,20), STR$(4), .NCRPRINT .CURSOR(24,1), .NCR*GOSUB PRINT.sub.-- MENU(2)REPEAT CALL READ.sub.-- KEY(K$)UNTIL (K$ .EQ `RN`) .OR (K$ .EQ `P`) .OR (.ESC .EQ 1)*RETURN*********************************************************************************__________________________________________________________________________ 
    
     OTHER EMBODIMENTS 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.