Abstract:
A program for causing an information processing apparatus to execute a process of a virtual calculator, the process including judging, when a switching of a virtual address space being a processing target of a virtual calculation apparatus occurs, whether or not a there exits physical calculation apparatus in which cache information of a physical address space corresponding to a virtual address space of a switching destination is accumulated; selecting the physical calculation apparatus when there exists a physical calculation apparatus in which the cache information of the physical address space is accumulated, and selecting the physical calculation apparatus in which cache information itself is not accumulated when there exists no physical calculation apparatus in which the cache information is accumulated; and assigning the selected physical calculation apparatus to the virtual calculation apparatus in which the switching of the virtual address space being a processing target has occurred.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application of International Application PCT/JP2010/064969 filed on Sep. 1, 2010 and designed the U.S., the entire contents of which are incorporated herein by reference. 
     
    
     FIELD 
       [0002]    The present invention relates to a technique to assign a physical CPU to a virtual CPU of a virtual machine set up in an information processing apparatus. 
       BACKGROUND 
       [0003]    In an information apparatus to which the technique of the VM: Virtual machine is applied, a guest OS being a virtual OS (Operating System) operates on a hypervisor. The guest OS performs the processing of a program using a virtual CPU to which a physical CPU (Central Processing Unit) is virtually assigned. 
         [0004]    As an example of the technique to assign a physical CPU to a virtual CPU, a technique to use an address conversion table that determines the correspondence between a logic processor (virtual CPU) and a physical processor (physical CPU) has been proposed. Specifically, in the proposed technique, a table representing the correspondence between the logic partition address space that the logic processor is able to access and the logical address space, and a table representing the correspondence between the virtual address space that the guest OS included in the logic partition and the physical address space, is able to use directly are set. Then, the control OS (hypervisor) updates these tables arbitrarily according to the situation, making possible to realize the switching of the correspondence between the logic processor and the physical processor without making the guest OS recognize the switching of the physical processor. 
         [0005]    Meanwhile, as another technique, a technique that enables, in a time sharing an access from the guest OS to MMIO (memory mapped IO) register information even in a condition in which no physical processor is assigned to a logic processor has been proposed. Specifically, in this technique, copy information of the MMIO register corresponding to the logic processor is held in the memory in both the condition in which a physical processor is assigned to the logic processor corresponding to the guest OS and the condition in which no physical processor is assigned to the logic processor. Accordingly, the guest OS is always able to access to the information of the MMIO register, making it possible to avoid processing delay. 
         [0006]    Here, in the technique to assign a physical CPU to a virtual CPU to realize the program processing in the guest OS, when a switching of the virtual address space being the processing target of the virtual CPU, the hypervisor has performed the following process. That is, the hypervisor has switched the physical address space of the processing target of the physical CPU assigned currently to the virtual CPU in tandem with the switching of the virtual address space being the processing target of the virtual CPU. 
         [0007]    Patent Document 1: Japanese Laid-open Patent Publication No. 2006-127462 
         [0008]    Patent Document 2: Japanese Laid-open Patent Publication No. 2006-350531 
       SUMMARY 
       [0009]    The present technique includes a computer readable recording medium having stored therein a program for causing an information processing apparatus including a plurality of physical calculation apparatuses to execute a process of a virtual calculator assigning the plurality of physical calculation apparatuses to one or more virtual calculation apparatuses, the process including judging, when a switching of a virtual address space being a processing target of a virtual calculation apparatus occurs, whether or not a there exits physical calculation apparatus in which cache information of a physical address space corresponding to a virtual address space of a switching destination is accumulated, among the plurality of physical calculation apparatuses; when there exists a physical calculation apparatus in which the cache information of the physical address space is accumulated, selecting the physical calculation apparatus, and when there exists no physical calculation apparatus in which the cache information of the physical address space is accumulated, selecting a physical calculation apparatus in which cache information itself is not accumulated; and assigning the selected physical calculation apparatus to the virtual calculation apparatus in which the switching of the virtual address space being a processing target has occurred. 
         [0010]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0011]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0012]      FIG. 1  is an illustration diagram of an example of the hardware configuration of an information processing apparatus. 
           [0013]      FIG. 2  is an example of a function block diagram related to the CPU assigning process. 
           [0014]      FIG. 3  is an illustration diagram of an example of a management table. 
           [0015]      FIG. 4  is a flowchart of an example of the process of a shadow page table managing unit. 
           [0016]      FIG. 5  is a flowchart of an example of a process of a physical CPU switching unit. 
           [0017]      FIG. 6A-FIG .  6 C are illustration diagrams of the contents of a management table in a specific example. 
           [0018]      FIG. 7A  and  FIG. 7B  are illustration diagrams representing the transition of the process condition of a physical CPU in a specific example. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0019]    However, when the switching of the physical address space is repeated while the same physical CPU is assigned to the virtual CPU, there is a problem as below. For example, even when the physical address space after the switching is a physical address space that the physical CPU has processed before, if processing of another physical address space is performed in the physical CPU after that, cache information of the physical address space after the switching is obviously not left. For this reason, there has been a problem that, until at least the cache information of the physical address space after the switching is accumulated in the physical CPU again, the memory access efficiency decreases. 
         [0020]    In view of the above problem, an objective of the present technique is to reduce the decrease in the memory access efficiency in the physical CPU by performing the assignment of the physical CPU appropriately when switching the virtual address space that becomes the processing target of the virtual CPU. 
         [0021]    The technique described herein is for improving the processing efficiency by devising the assignment of the physical CPU to the virtual CPU on a virtual calculator, in an information processing apparatus in which a plurality of physical CPU are provided and the virtual calculator where a guest OS operates on a hypervisor is established. According to the present technique, it becomes possible to reduce the decrease in the memory access efficiency in the physical CPU. 
         [0022]    When the guest OS switches the virtual address space that is processed by the virtual CPU, conventionally, the hypervisor has performed the following process in tandem with the switching process. That is, the hyper visor has switched the physical address space (assumed as a first physical address space) being the processing target of the physical CPU (assumed as the first physical CPU) that has been assigned to the virtual CPU so far in tandem with the switching of the virtual address space. For this reason, even when the first physical address space becomes the processing target again with a further switching of the virtual address space, cache information of the first physical address space accumulated in the first physical CPU has already been lost. 
         [0023]    However, in the technique described here, the hypervisor performs the following process. That is, the hypervisor does not simply switch the physical address space being the processing target of the first physical CPU, but selects another physical CPU (assumed as a second physical CPU) in which no cache information is accumulated in the cache and TLB and assign it to the virtual CPU. For this reason, in the first physical CPU, the cache information of the first physical address space is kept. Then, when the virtual address space corresponding to the first physical address space becomes the processing target of the virtual CPU again, the hypervisor selects the first physical CPU in which the cache information of the first physical address space is accumulated, and assigns it to the virtual CPU. Accordingly, it becomes possible to reuse the cache information of the physical address space accumulated in the cache and TLB of the first physical CPU. For this reason, after the switching of the virtual address space, it becomes possible to reduce memory access delay of the physical CPU generated before the cache information of the physical address corresponding to the virtual address space is accumulated in the physical CPU as a whole. 
         [0024]      FIG. 1  illustrates an example of the hardware configuration of an information processing apparatus in which such a technology is materialized. The information processing apparatus in  FIG. 1  includes a plurality of physical CPUs (Central Processing Unit)  10   1-n , a memory  2 , storage  3 , a portable storage medium drive apparatus  4 , an input/output apparatus  5  and a communication interface  6 . Meanwhile, in the explanation below, a description physical CPU  10 , for example, represents any one element of the physical CPU  10   1-n , as an example (the same explanation may be applied to other elements of the physical CPU  10   1-n ). The same applies to other constituent elements. 
         [0025]    The physical CPU  10  includes a control unit, a calculation unit and an instruction decoder and the like, and an execution unit executes arithmetic/logic calculation using the calculation unit, according to a control signal output from the control unit in accordance with an instruction of a program decoded in the instruction decoder. The physical CPU  10  includes a control register  11  in which various information used for control is stored, a cache  12  that is able to temporarily store contents of the memory  2  and the like, and a TLB  13  that functions as a cache of the page table. Meanwhile, an address space refers to a memory area that is represented by a series of memory addresses. Then, the virtual address space represents a virtual address space that the virtual CPU accesses, and the physical address space represents an address space that the physical CPU accesses, being a physical address space corresponding to the virtual address. Meanwhile, cache information herein refers to information related to the address space, stored in the cache  12 , the TLB  13  and the like. The physical CPU  10  is able to realize high-speed processing by using cache information stored in the cache  12  and the TLB  13  being able to be accessed at a higher speed than directly accessing the memory itself. Meanwhile, while in this embodiment, the explanation is made using an example in which a plurality of physical CPUs themselves are provided independently from each other, a plurality of CPU cores may also be provided as the configuration. A description that a plurality of CPU are provided herein is assumed to include a meaning that a plurality of CPU cores are provided. 
         [0026]    The memory  2  is a RAM (Random Access Memory) and the like for example, being a main memory on which a program executed in the physical CPU  10  is loaded and stores data used for the processes in the physical CPU  10 . Meanwhile, the storage  3  is an HDD (Hard Disk Drive) and a flash memory and the like, that stores a program and various data. The portable storage medium drive apparatus  4  is an apparatus that reads out data and programs stored in a portable storage medium  7 . The portable storage medium  7  is for example a magnetic disk, an optical disk, a magneto-optical disk, or a flash memory and the like. Meanwhile, the physical CPU  10  executes the program stored in the storage  3  and the portable storage medium  7  while cooperating with the memory  2  and the storage  3 . Meanwhile, the program that the physical  10  executes and the data being the access target may also be stored in another apparatus that is able to communicate with the information processing apparatus. 
         [0027]    The input/output apparatus  5  is for example a keyboard and a display and the like, that receives operation instructions by user manipulation and the like, while outputting a processing result by the information processing apparatus. The communication interface  6  is a LAN (Local Area Network) card and the like that enables external data communication. The respective constituent elements of the information processing apparatus described above are connected by a bus  8 . 
         [0028]      FIG. 2  is a function block diagram related to the CPU assignment function realized in such an information processing apparatus. 
         [0029]    In the information processing apparatus, the virtual calculator  22  is established on the hypervisor  23 . In other words, the guest OS  24  operates under the control of the hypervisor  23 . Meanwhile, while  FIG. 2  illustrates a case in which the number of the guest OS  24  is one, there may be a plurality of guest OS  24 . The hypervisor  23  operates on the physical CPU  10   1-n  as a lower layer of the guest OS  24 . 
         [0030]    The virtual calculator  22  includes one or more virtual CPUs  20   1-n  that executes the respective processes above on the guest OS  24 . As well as the physical CPU  10 , the virtual CPU  20  also includes a control register  21 . On the guest OS  24 , a plurality of programs (processes)  40   1-n  are executed, and the plurality of programs  40   1-n  are executed while sharing one virtual CPU from the virtual CPUs  20   1-n  with a time-sharing and so on. Furthermore, the combination of the plurality of programs  40   1-n  may be processed in parallel at the same time in respectively separate virtual CPUs. In addition, page tables  50   1-n  exist corresponding respectively to the  40   1-n . The page table  50  associates and holds the logical address of the virtual address space in which data used when executing the program  40  is stored and the pseudo physical address. 
         [0031]    Furthermore, the guest OS  24  includes a space managing unit  25  that manages the virtual address space being the processing target of the virtual CPUs  20   1-n . The space managing unit  25  performs a process to update the page tables  50   1-n  according to the update instruction of the space configuration of the virtual address space due to a memory acquisition event, a memory release event and the like. Meanwhile, when the update of the space configuration of the virtual address space is performed, it follows that the space configuration of the physical address space corresponding to the virtual address space is also updated, and the corresponding shadow page tables  50   1-n  are also updated. 
         [0032]    Meanwhile, the space managing unit  25  includes a space switching unit  26  that switches the virtual address space to be the processing target of the virtual CPUs  20   1-n . When switching the virtual address space to be the processing target of the virtual CPUs  20 , the space switching unit  26  substitutes the address of the page table  50  representing the switching target virtual address space into the control register  21  of the virtual CPU  20 . Such a process occurs in a case in which, for example, the virtual CPU  20  is executing a plurality of programs by time sharing, when the processing target program is switched by dispatch or when the execution of a new program is started. At this time, the space switching unit  26  substitute the address of the page table  50  corresponding to the program  40  executed after the switching into the control register  21  of the virtual CPU  20 . 
         [0033]    The hypervisor  23  assigns the physical CPU  10  to the virtual CPU  20  as needed. Here, the hypervisor  23  includes shadow page tables  60   1-n  that respectively correspond to the page tables  50   1-n  and represents the physical address spaces that respectively correspond to the virtual address spaces that the page tables  50   1-n  represent. In the shadow page table  60 , the logical address and the physical address (the machine address that the physical CPU  10  is able to recognize) of the physical address are associated and stored. Meanwhile, the hypervisor  23  is obviously able to refer to information for identifying the shadow page table  60  corresponds to the page table  50  (not illustrated in the drawing). In addition, to the shadow page tables  60   1-n , respectively, update counters  70   1-n  in which the number of updates of the shadow page table  60  (that is, the corresponding page table  50 ) is set is associated. 
         [0034]    Meanwhile, the hypervisor  23  includes an instruction capturing unit  27  that captures the update instruction of the page table  50  in the guest OS and the substitution instruction of the address of the page table  50  into the control register  21  of the virtual CPU  20 . Then, the instruction capturing unit  27  includes a shadow page table managing unit  28  and a physical CPU switching unit  29 . 
         [0035]    When an update instruction for the page table  50  is captured, the shadow page table managing unit  28  makes the update contents reflected on the shadow page table  60  corresponding to the page table  50  being the update target. In addition, the shadow page table managing unit  28  counts up the update counter  70  corresponding to the shadow page table  60  at the time of reflecting the update contents. 
         [0036]    When a substitution instruction of the address of the page table  50  into the control register  21  of the virtual CPU  20  is captured (that is, when a switching of the address space being the processing target of the virtual CPU  20  occurs), the physical CPU switching unit  29  performs the following process. That is, the physical CPU switching unit  29  selects the physical CPU  10  from the physical CPUs  10   1-n  to assign to the virtual CPU  20 , and assigns the selected physical CPU  10  to the virtual CPU  20 . At this time, the physical CPU switching unit  29  substitutes the address of the shadow page table  60  corresponding to the page table  50  related to the substitution instruction into the control register  11  of the physical CPU  10  when needed. Meanwhile, the physical CPU switching unit  29  is an example of the embodiment of selection means and assignment means. 
         [0037]    Here, the physical CPU switching unit  29  refers to a management table  30  in which data including information (in this embodiment, the address of the shadow page table set in the control register of the physical CPU) representing the physical address space related to cache information accumulated in the physical CPUs  10   1-n . The management table  30  includes, as illustrated in  FIG. 3 , items including the physical CPU, the address of the shadow page table set in the control register of the physical CPU, the update counter of the shadow page table, the usage condition of the physical CPU. The management table  30  is stored in storage means such as the memory  2  or the storage  3  for example. 
         [0038]    Here, the usage condition of the physical CPU set in the management table  30  is explained. As the usage condition of the physical CPU, the following three conditions are assumed. 
         [0039]    “Assigned”: the condition in which the CPU is assigned to a specific virtual CPU, and the condition in which the address of the shadow page table is set to the control register (that is, the condition in which the physical CPU is executing the processing of one of the programs and the cache information of the physical address space of the program is accumulated in the cache and TLB) 
         [0040]    “Used”: the condition in which the physical CPU is not assigned to any specific virtual CPU but the address of the shadow page table is set to the control register (that is, the physical CPU is not executing the processing of a program currently, but has at least executed the processing of one of the programs after the latest startup of the information processing apparatus, and the cache information of the physical address space of the program is accumulated in the cache and the TLB). 
         [0041]    “Unused”: the condition in which the physical CPU is not assigned to any virtual CPU, and the address of the shadow page table is not set to the control register (that is, the physical CPU has not executed any program yet at least after the latest startup of the information processing apparatus, and cache information itself of the physical address space is not accumulated in the cache and the TLB) 
         [0042]    Next, in the respective constituent elements described above, especially the process executed by the shadow page table managing unit  28  and the physical CPU switching unit  29  of the instruction capturing unit  27  or the hypervisor  23  is explained in detail. 
         [0043]    The flowchart in  FIG. 4  illustrates the process of the shadow page table managing unit  28 . The process in  FIG. 4  is executed when the instruction capturing unit  27  captures an update instruction for the page table  50 . 
         [0044]    In step  1  (indicated as S 1  in the drawing. The same applies below), the shadow page table managing unit  28  identifies the address of the shadow page table  60  corresponding to the page table  50  updated by the update instruction. 
         [0045]    In step  2 , the shadow page table managing unit  28  makes the contents of the update done for the page table  50  reflected on the shadow page table  60  identified in step  1 . 
         [0046]    In step  3 , the shadow page table managing unit  28  counts up the update counter  70  provided corresponding to the updated shadow page table  60 . 
         [0047]    Meanwhile, such counting up of the update counter  70  is done for the following purpose. That is, in a case of the physical CPU of the x86 architecture and the like for example, when the space configuration of the physical address space is updated according to the update of the space configuration of the virtual address space, a process to substitute the address of the shadow page table into the control register of the physical CPU, and the to purge the TLB of the physical CPU is performed. In other words, when the space structure of the physical address space is updated, it is impossible to the cache information of the physical address space accumulated before the update in the cache and the TLB of the physical CPU. In this embodiment, the shadow page table managing unit  28  holds the number of updates of the shadow page table  60  by counting up the update counter  70  every time when the contents of the shadow page table  60  is updated (that is, the space structure of the physical address space is updated). Meanwhile, the physical CPU switching unit  20  identifies the presence/absence of the update of the shadow page table  60  based on the value of the update counter  70 , in the physical CPU selection process described later. Then, the physical CPU switching unit  29  judges whether or not the cache information of the physical CPU holding the cache information of the address space represented by the shadow page table  60  is available. Meanwhile, such a process is not required when using a CPU of an architecture in which the case where the purging of the TLB of the physical CPU is performed with the change of the space configuration is not assumed. 
         [0048]    Next, using the flowchart in  FIG. 5 , the process of the physical CPU switching unit  29  is explained. The process in  FIG. 5  is executed when the instruction capturing unit  27  captures a substitution instruction of the address of the page table  50  into the control register  21  of the virtual CPU  20 . In other words, the process in  FIG. 5  is executed when the switching of the virtual address space processed in the virtual CPU  20  occurs. 
         [0049]    In step  11 , the physical CPU switching unit  29  identifies the address of the shadow page table  60  corresponding to the address of the page table  50  related to the substitution instruction. 
         [0050]    In step  12 , the physical CPU switching unit  29  judges whether or not the address of the shadow page table  60  related to the substitution instruction is the same as the address of the shadow page table  60  substituted into the control register  11  of the physical CPU  10  to which the process is currently assigned. The physical CPU switching unit  29  moves the process forward to step  13  when they are not the same (No), and moves the process forward to step  19  when they are the same (Yes). Meanwhile, as the case in which they are the same, a case in which, for example, when a physical CPU of the x86 architecture is used, a substitution instruction of a page table simply to purge the TLB and the like is assumed. 
         [0051]    In step  13 , the physical CPU switching unit  29  refers to the management table  30  and judges whether or not there is a physical CPU  10  that satisfies the following conditions among the physical CPUs  10   1-n . 
         [0000]    (1) The usage condition of the management table is “Used”
 
(2) The shadow page table address of the management table is the same as the address of the shadow page table address related to the substitution instruction
 
(3) The update counter of the management table is the same as the update counter of the shadow page table related to the substitution instruction
 
         [0052]    The physical CPU  10  that satisfies these conditions (1)-(3) is in other words, a physical CPU  10  that satisfies the conditions (1) not assigned to any of the virtual CPUs  20   1-n  currently, (2) the cache information of the physical address space corresponding to the virtual address space after switching is accumulated in cache  12  or the TLB  13 , and (3) the space configuration of the physical address space is not updated since the point of time when the physical CPU processed the physical address space. 
         [0053]    The physical CPU switching unit  29  moves the process forward to step  14  when there is a physical CPU that satisfies the conditions (1)-(3) above (Yes), while it moves the process forward to step  16  when there is no such physical CPU (No). 
         [0054]    In step  14 , the physical CPU switching unit  29  selects the physical CPU  10  that satisfies all the conditions (1)-(3) above. Then, the physical CPU switching unit  29  assigns the selected physical CPU  10  to the virtual CPU  20 . 
         [0055]    In step  15 , the physical CPU switching unit  29  updates the management table  30 . Specifically, the physical CPU switching unit  29  changes the usage condition of the record corresponding to the physical CPU  10  selected in step  14  among the records in the management table  30  from “Used” to “Assigned”. Meanwhile, the physical CPU switching unit  29  changes the usage condition of the record corresponding to the physical CPU  10  assigned to the virtual CPU  20  before the assignment process in S 14  among the records in the management table  30  from “Assigned” to “Used”. Furthermore, the physical CPU switching unit  29  changes the update counter of the changed record to the current value of the update counter  70  corresponding to the shadow page table  60  that was the processing target before the assignment process in step  14  (before the switching of the address space). 
         [0056]    In step  16 , the physical CPU switching unit  29  refers to the management table  30 , and judges whether or not there is a physical CPU  10  whose usage condition is “Unused”. When there is a physical CPU  10  whose usage condition is “Unused”, the physical CPU switching unit  29  moves the process forward to step  17  (Yes), while when there is no physical CPU  10  whose usage condition is “Unused”, moves the process forward to step  19  (No). 
         [0057]    In step  17 , the physical CPU switching unit  29  selects the physical CPU  10  whose usage condition is “Unused”. In other words, the physical CPU switching unit  29  selects the physical CPU  10  in which the address itself of the shadow page table  60  is not set to the control register  11  (that is, the cache information itself is not accumulated). Then, the physical CPU switching unit  29  assigns the selected physical CPU  10  to the virtual CPU  20 . At this time, the physical CPU switching unit  29  substitutes the address of the shadow page table  60  related to the substitution instruction into the control register  11  of the physical CPU  10 . In other words, when there is no physical CPU  10  that satisfies all the conditions (1)-(3) above, the physical CPU switching unit  20  assigns the physical CPU  10  in which the cache information is not accumulated with a higher priority than the physical CPU  10  that has been assigned to the virtual CPU  20  so far. 
         [0058]    In step  18 , the physical CPU switching unit  29  updates the management table  30 . Specifically, the physical CPU switching unit  29  changes the address of the shadow page table  60  of the physical CPU  10  selected in step  17  among the records in the management table  30  into the address of the shadow page table  60 . In addition, the physical CPU switching unit  29  changes the usage condition of the record in which the address of the shadow page table  60  has been changed from “Unused” to “Assigned”. In addition, the physical CPU switching unit  29  changes the update counter of the record in which the address of the shadow page table  60  into the current value of the update counter  70  corresponding to the shadow page table  60  related to the substitution instruction. Meanwhile, the physical CPU switching unit  29  change the usage condition of the record corresponding to the physical CPU  10  that was assigned to the virtual CPU  20  before the assignment process in S 17  among the records in the management table  30  from “Assigned” to “Used”. In addition, the update counter of the record in which the address of the shadow page table  60  has been changed is changed to the current value of the update counter  70  corresponding to the shadow page table  60  that was the processing target before the assignment process in S 17  (before the switching of the address space). 
         [0059]    In step  19 , the physical CPU switching unit  29  substitutes the address of the shadow page table  60  related to the substitution instruction into the control register  11  of the physical CPU  10  that has been assigned to the virtual CPU  20  so far. That is, the physical CPU switching unit  29  assigns the physical CPU  10  that has been assigned to the virtual CPU  20  so far continuously to the virtual CPU  20 . 
         [0060]    In step  20 , the physical CPU switching unit  29  updates the management table  30 . Specifically, the physical CPU switching unit  29  changes the address of the shadow page table of the physical CPU  10  to be assigned continuously to the virtual CPU  20  in step  19  among the records in the management table  30  to the address of the shadow pate table  60  related to the substitution instruction. In addition, the update counter of the record in which the address of the shadow page table  60  is changed to the current value of the update counter  70  corresponding to the shadow page table related to the substitution instruction. 
         [0061]    According to such a process, when the switching of the virtual address space processed by the virtual CPU occurs, the assignment of the physical CPU is performed as follows. That is, when there is a physical CPU in which the address of the shadow page table of the physical address space corresponding to the virtual address space of the switching destination is substituted into the control register, the physical CPU is assigned to the virtual CPU. Here, the physical CPU in which the address of the shadow page table of the physical address space corresponding to the virtual address space of the switching destination is substituted into the control register is, in other words, the physical CPU in which the cache information of the physical address space corresponding to the virtual address of the switching destination is accumulated in the cache or the TLB. For this reason, it becomes possible to use the cache information accumulated in the physical CPU in the process after the virtual address space switching, making it possible to reduce delay in the memory access process of the physical CPU after the virtual address space switching. 
         [0062]    Meanwhile, on the other hand, in the record in the management table corresponding to the physical CPU that has been assigned to the virtual CPU so far, the address of the shadow page table before the switching is stored, and its usage condition is not unused by used. Therefore, a physical CPU that has been assigned to the virtual CPU is not selected to be assigned for the processing of another physical address space. For this reason, the cache information accumulated in the physical CPU is held without being rewritten with the cache information of another physical address space. Then, when the physical address space becomes the processing target next, as described above, the physical CPU is selected and assigned to the virtual CPU. For this reason, when the same physical address space becomes the processing target, the cache information accumulated in the physical CPU is utilized, making it possible to reduce the delay in the memory access process. 
         [0063]    Furthermore, when there is no physical CPU in which the address of the shadow page table of the physical address space of the switching target is substituted into the control register, an unused physical CPU is assigned to the virtual CPU. Immediately after the assignment process, no cache information is accumulated of the physical address of the switching destination is accumulated in the cache or the TLB of the physical CPU assigned to the virtual CPU. However, once the physical CPU is assigned to the virtual CPU and cache information is accumulated, when the same physical address space becomes the processing target, the cache information accumulated in the physical CPU is utilized. As described above, as a result, the delay in the memory access may be reduced as a whole, while using a plurality of physical CPUs effectively. 
         [0064]    Meanwhile, as described above, even when the hypervisor switches the physical CPU assigned to the virtual CPU according to the switching of the address space, it is recognized in the same manner as the switching of the address space so far on the guest OS side. Then, with the plurality of physical CPUs used for the process performed in one virtual CPU, even when there is an upper limit for the number of virtual CPUs available in the guest OS, the plurality of CPUs are utilized regardless of the upper limit. 
         [0065]    Here, in the processes of the example described above, the assignment process of the physical CPU  10  to the virtual CPU  20  in a case in which a substitution instruction of the address space into the control register  21  of the virtual CPU  20  is executed, presenting a specific example. 
         [0066]      FIG. 7A  is an illustration diagram illustrating the transition of the processing condition of the physical CPU  10   1-n  and the physical CPU  10   2  according to the elapse of the time (t) in the specific example. 
         [0067]    &lt;1&gt; In this specific example, it is assumed that, on the guest OS  24  operating in the virtual calculator  22  illustrated in  FIG. 2 , the program  40   1  and the  40   2  are executed alternatingly while sharing the virtual CPU  20   1 . At the current point of time, the processing target of the virtual CPU  20   1  is the virtual address space of the program  40   1 , and into the control register  21   1  of the virtual CPU  20   1 , the address of the page table  50   1  is substituted. Meanwhile, to the virtual CPU  20   1 , the physical CPU  10   1  is assigned, and to the control register  11   1  of the physical CPU  10   1 , the address (0x0DD0F000) of the shadow page table  60   1  corresponding to the page table  50   1 . At this time, the contents of the management table  30  are in the condition illustrated in  FIG. 6A . 
         [0068]    &lt;2&gt; Then, when the dispatch is performed from the program  40   1  to the program  40   2 , the space switching unit  26  in the guest OS  24  performs the switching of the virtual address space being the processing target of the virtual CPU  20   1 . Specifically, the space switching unit  26  executes a substitution instruction to substitute the address of the page table  50   2  that represents the address space of the program  40   2  into the control register  21   1  of the virtual CPU  20   1 . 
         [0069]    Meanwhile, the instruction capturing unit  27  in the hypervisor  23  captures a substitution instruction of the address of the page table  50   2  to the control register  21   1  of such virtual CPU  20   1 . Then, the physical CPU switching unit  29  refers to the management table  30 , and searches for the physical CPU  10 , among the physical CPUs  10   1-n , whose (1) usage condition is “Used”, (2) shadow page table address is the address (0x0DF00000) of the shadow pate table  60   2  corresponding to the page table  50   2  representing the virtual address space of the program  40   2  executed in the virtual CPU  20   1  after the dispatch, and (3) update counter is the same as the update counter  70   2  of the shadow page table  60   2 . Meanwhile, at this stage, it is assumed that the update counter  70   2  is 0. Here, in the condition of the management table  30  illustrated in  FIG. 6A , there is no physical CPU  10  that satisfies all the conditions (1)-(3). Therefore, the physical CPU switching unit  29  assigns the physical CPU  10   2  whose usage condition is “Unused” to the virtual CPU  20   1 , to the control register  11   2  of the physical CPU  10   2 , substitutes the address (0x0DF00000) of the shadow pate table  60   2 . Then, the physical CPU switching unit  29  changes the shadow page table address of the record of the physical CPU  10   2  among the records in the management table  30  to the address (0x0DF00000) of the shadow pate table  60   2 , and changes its usage condition from “Unused” to “Assigned”. Furthermore, the physical CPU switching unit  29  changes the usage condition of the record of the physical CPU  10   1  to from “Assigned” to “Used”.  FIG. 6B  illustrates the contents of the management table  30  after such update is performed. 
         [0070]    &lt;3&gt; As a result of such a process, the physical CPU  10   2  is assigned to the virtual CPU  20   1 , and the processing of the physical address space represented by the shadow page table  60   2 , that is, the processing of the program  40   2  is executed. During the execution of the process, as described above, in the management table  30 , the address (0x0DD0F000) of the shadow page table  60   1  corresponding to the physical CPU  10   1  is set in the shadow page table address of the record corresponding to the physical CPU  10   1 , and its usage condition is “Used”. Therefore, the physical CPU  10   1  is not assigned to the processing of other physical address space. Therefore, the cache  12   1  or the TLB  13   1  of the physical CPU  10   1  keep holding the cache information of the address space of the shadow page table  60   1 . 
         [0071]    &lt;4&gt; Then, when the dispatch from program  40   2  to the program  40   1  is performed again, the space switching unit  26  performs the switching of the virtual address space of the processing target of the virtual CPU  20   1 . Specifically, the space switching unit  26  substitutes the address of the page table  50   1  representing the virtual address space of the program  40   1  into the control register  21   1  of the virtual CPU  20   1 . 
         [0072]    Meanwhile, the instruction capturing unit  27  of the hypervisor  23  captures a substation instruction of the address into the control register  21   1  of such virtual CPU  20   1 . Then, the physical CPU switching unit  29  refers to the management table  30 , and searches for the physical CPU  10 , among the physical CPUs  10   1-n , whose (1) usage condition is “Used”, (2) shadow page table address is the address (0x0DD0F000) of the shadow page table  60   1  corresponding to the page table  50   1  representing the virtual address space of the program  40   1  executed in the virtual CPU  20   1  after the dispatch, and (3) update counter is the same as the update counter  70   1  of the shadow page table  60   1 . Meanwhile, at this stage, it is assumed that the update counter  70   1  is 3. Here, based on the management table  30  illustrated in  FIG. 6B , the physical CPU  10   1  satisfies these conditions. Therefore, the physical CPU switching unit  29  assigns the physical CPU  10   1  to the virtual CPU  20   1 , and changes the usage condition of the record of the physical CPU  10   2  from “Assigned” to “Used” in records of the management table  30 , while changing the usage condition of the record of the physical CPU  10   1  from “Used” to “Assigned”.  FIG. 6C  illustrates the contents of the management table  30  after such update is performed. 
         [0073]    &lt;5&gt; As a result of such a process, the physical CPU  10   1  is assigned to the virtual CPU  20   1 , and the processing of the physical address represented by the shadow page table  60   1 , that is, the processing of the program  40   1  is performed again. 
         [0074]    Here,  FIG. 7B  illustrates the processing condition of the physical CPU  10   1  in a case in which the processing is performed using the physical CPU  10   1  by the conventional CPU assignment method. According to the conventional CPU assignment method, after the dispatch from the program  40   1  to the program  40   2  occurs, when the dispatch to the program  40   1  occurs again, the cache  12   1  and TLB  13   1  have already been rewritten to the cache information of the physical address space of the program  40   2 . Therefore, immediately after the dispatch to the program  40   1 , the cache information of the address space of the program  40   1  is not accumulated in the cache  12   1  and the TLB  13   1 , leading to the risk of delay in the memory access process. 
         [0075]    On the other hand, returning to the explanation of &lt;5&gt; of  FIG. 7A , when the physical CPU  10   1  is assigned to the virtual CPU  20   1  again, in the cache  12   1  and the TLB  13   1  of the physical CPU  10   1 , the cache information of the physical address space represented by the shadow page table  60   1  is still kept. 
         [0076]    For this reason, even immediately after the switching of the virtual address space, the physical CPU  10   1  is able to the program  40   1  using the cache information accumulated in the cache  12   1  and the TLB  13   1 . Therefore, even immediately after the dispatch to the program  40   1 , the delay in the memory access is reduced. 
         [0077]    Here, in each of the examples above, the physical CPU to be assigned to the virtual CPU is selected referring to the address of the shadow page table substituted into the control register and the usage condition of each physical CPU. However, the process to refer to the usage condition does not necessarily have to be performed. That is, when a physical CPU in the condition in which the address of the shadow page table of the physical address space corresponding to the virtual address space of the switching destination is set to the control register is successfully identified, depending on the structure of the guest OS, it may be possible to judge that the physical CPU is not being assigned to another virtual CPU. Therefore, without necessarily referring to the usage condition of the physical CPU, the physical CPU may be selected on a condition that the address of the shadow page table of the physical address space corresponding to the virtual address space of the switching destination to the control register. Meanwhile, when the address of the shadow page table is not set to the control register of the physical CPU, it is necessarily identified that the physical CPU is in the unused condition. Thus, even if the physical CPU is selected based on the address of the shadow page table without referring to the usage condition, it is possible to select the physical CPU appropriately. 
         [0078]    Furthermore, in the example above, the hypervisor uses the management table to manage the address of the shadow page table substituted into the control register and the usage condition of each physical CPU. Then, the hypervisor is able to check the cache information and the like of the physical CPU and select the physical CPU promptly at the time of the switching of the virtual address space, by referring to the data of such a management table. However, such management data does not necessarily have to be held in the format of a table. Furthermore, it is possible for the hypervisor to select the physical CPU by generating an interruption to each physical CPU to check the contents and the like of the control register of the physical CPU directly, and does not necessarily have to use the management data. 
         [0079]    The functional configuration and the physical configuration of the information processing apparatus are not limited to the embodiment described above, and for example, and it is possible for the respective functions and physical sources to be integrated and implemented, or in an opposite manner, further dispersed and implemented. 
         [0080]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a depicting of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.