Abstract:
An circuit and method are provided for amplifying RF input signal to produce RF output signals with third-order intermodulation distortion products. The circuit and method use a feedback signal to control the bias voltage of the amplifier, such that the output third-order intermodulation distortion product increases monotonically with the RF input signal power. Specifically, the third-order intermodulation distortion product responds over a predetermined output power range by increasing three decibels in response to each one-decibel increase in input power.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to radio-frequency (RF) power amplifiers. More particularly, the invention relates to an RF power amplifier circuit that includes a bias adjustment circuit that causes the output signal of the amplifier to contain an amount of intermodulation distortion that increases linearly (on a log scale) as the output power increases.  
         BACKGROUND OF THE INVENTION  
         [0002]    An RF power amplifier is a circuit that is capable of receiving an RF input signal and amplifying it to produce an RF output signal. RF power amplifiers are frequently used in communications systems, such as cable-television systems (CATV). They normally include bipolar junction transistors or field-effect transistors as amplifying elements, and, if so, they also invariably include a bias circuit that sets the quiescent operating point of the transistor. (The quiescent operating point of a transistor is the “point on the family of characteristic curves . . . that corresponds to the average electrode voltages or currents in the absence of a signal.” JOHN MARKUS, ELECTRONICS DICTIONARY 445 (4th ed. 1979). The quiescent operating point of a bipolar junction transistor includes such parameters as quiescent base-emitter current, quiescent base-emitter voltage, quiescent collector-emitter current, and quiescent collector-emitter voltage.)  
           [0003]    In such transistor-based power amplifiers, there are tradeoffs between maximizing efficiency and ensuring that the desired amplification characteristics are maintained. The efficiency of an amplifier, or output circuit efficiency, is the amplifier&#39;s signal output power divided by the power supplied to the amplifier by the power supply. The former quantity—the signal output power—is determined by the gain of the amplifier and the input drive level (or signal input power). The latter quantity—the power supplied to the amplifier by the power supply—is largely determined by the quiescent operating point of the amplifier. An amplifier with a high quiescent operating point will draw a large amount of power from the power supply, and the amplifier will have a low efficiency. Conversely, an amplifier with a low quiescent operating point will draw a small amount of power from the power supply, and the amplifier will have a high efficiency. In summary, the relationship among efficiency, signal output power, and quiescent operating point is this: the lower the quiescent operating point and the higher the signal output power, the higher the efficiency of the amplifier.  
           [0004]    But an amplifier with a low quiescent operating point and a high signal output power will produce (in addition to an amplified RF signal) large intermodulation and harmonic distortion signals. Harmonics, or noise signals having frequencies that are integer multiples of the signal frequency f (i.e., 2f, 3f, etc.) are generated when a pure sinusoidal waveform is clipped. If clipping occurs when more than one signal is simultaneously applied to an amplifier, then intermodulation distortion (hereinafter, “IMD”) occurs in addition to harmonic generation.  
           [0005]    For amplifiers with less than a one-octave bandwidth, the dominant IMD term is the third-order component. The theoretical power of such third-order IMD products resulting from waveform clipping increases by about three decibels for every one-decibel increase in signal input power, provided that the highest-order term in the nonlinearity of the amplifier is cubic. In other words, if the theoretical power (in decibels) of the third-order IMD is graphed against the signal input power (in decibels), the result is a straight line having a slope of about 3:1. This graph of the third-order IMD versus input power level is referred to hereinafter as the theoretical 3:1 curve.  
           [0006]    In practice, however, real amplifiers contain nonlinear processes that cause the third-order IMD produced to deviate from the theoretically-calculated amount. The power of the IMD caused by these nonlinear processes is determined by the vector addition of the components generated by each nonlinear process. Such terms may partially cancel or add, depending on the frequency and phase of the components. As a consequence, the actual third-order IMD does not follow the theoretical 3:1 curve. As the output power increases, rather, the third-order IMD tends to deviate more and more from the theoretically-predicted 3:1 curve, and the rate of increase of IMD with input power may become 4:1, 5:1 or even worse.  
           [0007]    The inventor of the present invention has recognized that this unpredictable variation in IMD from the theoretically-predicted 3:1 curve causes problems to designers of CATV systems, who must be able to calculate signal power and distortion power at each point in a cascaded CATV system. The calculations are normally performed using large spreadsheet programs making use of the assumption that the IMD produced by each amplifier follows the theoretical 3:1 curve. But the calculations are inaccurate if the third-order IMD produced is greater or less than the amount that is theoretically predicted. Thus, it would be desirable to have an RF amplifier that produces a predictable amount of IMD, in accordance with the theoretical 3:1 curve.  
           [0008]    Existing techniques for compensating for excessive IMD are not adequate to this task. A first known technique is to decrease or attenuate the power level of the amplifier input signal. A decrease in input power causes a corresponding decrease in the output power of the amplifier, so that the third-order intermodulation and harmonic distortion is reduced to acceptable levels. The useful output power range over which the amplifier can be used is therefore limited, in order to avoid excessive IMD. This limitation in output power range is highly undesirable.  
           [0009]    A second technique that has been used to compensate for excessive distortion is described in U.S. Pat. No. 5,712,593 (hereinafter, the &#39;593 patent). According to this technique, there is selected a power level of total distortion (including both harmonic and intermodulation distortion) that is acceptable in the output of the amplifier. An adjustable bias circuit is then employed to continually adjust the operating point of the amplifier, depending on the power of the distortion in the output of the amplifier, so that the power level of distortion that is acceptable is maintained. If the power of the distortion is too high, the operating point of the amplifier is raised to a point at which the amplifier operates more linearly and produces less distortion. Conversely, if the power of the distortion is lower than the acceptable amount, the operating point of the amplifier is lowered, thereby improving the efficiency of the amplifier but increasing the distortion produced by the amplifier.  
           [0010]    Although the system of the &#39;593 patent successfully maintains the total distortion in the output of an amplifier at a predetermined power level, however, it does not accomplish the desired objective of causing the third-order IMD to increase at the 3:1 rate. Rather, in the system of the &#39;593 patent, the power level of the third-order IMD in the output of the amplifier remains at approximately the same level as the power of the input signal increases, because the amplifier bias voltage is continually adjusted to maintain the level of distortion constant. Thus, the technique of the &#39;593 patent does not fulfill the need for predictability in amplifier performance.  
         OBJECT OF THE INVENTION  
         [0011]    It is accordingly an object of the invention to provide an amplifier bias adjustment that maintains the theoretically-expected 3:1 third-order IMD slope for output power.  
         SUMMARY OF THE INVENTION  
         [0012]    The invention is directed to a circuit for amplifying an input RF signal. The circuit comprises the following elements: (1) an RF amplifier circuit that amplifies the input RF signal and produces an output RF signal that comprises a third-order IMD product signal; (2) a power divider circuit that divides a signal output from the RF amplifier circuit into the output RF signal and a feedback signal; (3) a feedback circuit comprising an RF detector that detects the feedback signal and produces a DC voltage proportional to the power of the feedback signal that is used to bias the RF amplifier circuit. With this circuit, the third-order IMD product signal responds, over a predetermined range of power of the output RF signal, by increasing substantially three decibels in response to each one-decibel increase in the level of the input RF signal. Preferably, the feedback circuit further comprises a DC level shifter and a DC amplifier to amplify and shift the level of the DC voltage before it is used to bias the RF amplifier circuit.  
           [0013]    In one embodiment, the power divider circuit produces the RF output signal and the feedback signal with equal strength. Preferably, though, the power divider circuit produces the RF output signal and the feedback signal with unequal strength. In a preferred embodiment, the feedback signal has a strength at least ten decibels less than the RF output signal. The power divider circuit may comprise a coupler with a ferrite core. Alternatively, it may comprise a resistor or any other circuitry that divides power. The RF amplifier circuit preferably comprises a monolithic gallium arsenide (GaAs) metal-semiconductor field-effect transistor (MESFET). The detector circuit preferably comprises a DC blocking capacitor, a detector diode, a DC bias inductor, a DC bias resistor, and an RF bypass capacitor.  
           [0014]    The invention is also directed to a method for amplifying an input RF signal to produce an output RF signal that comprises a third-order IMD product signal, where the third-order IMD product signal responds over a predetermined range of power of the output RF signal by increasing substantially three decibels in response to each one-decibel increase in the level of the input RF signal. The method comprises the following steps: (1) amplifying the input RF signal in an amplifier to produce an amplified signal; (2) dividing the amplified signal into an output RF signal and a feedback signal; (3) generating a DC signal with a DC voltage proportional to the power of the feedback signal; and (4) biasing the amplifier based on the DC signal. Preferably, the method further comprises the steps of amplifying the DC signal and level-shifting the DC voltage before using it to bias the amplifier.  
           [0015]    In one embodiment, the step of dividing produces the RF output signal and the feedback signal with equal strength. Preferably, though, this step produces the RF output signal and the feedback signal with unequal strength. In a preferred embodiment, the feedback signal has a strength at least ten decibels less than the RF output signal. The step of dividing may be performed with a circuit that comprises a coupler with a ferrite core. Alternatively, it may be performed with a circuit that comprises a resistor or any other circuitry that divides power. The amplifier preferably comprises a monolithic GaAs MESFET. The step of generating a DC signal is preferably performed with a circuit that comprises a DC blocking capacitor, a detector diode, a DC bias inductor, a DC bias resistor, and an RF bypass capacitor. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 is a block diagram illustrating the feedback circuit of the invention used to maintain the theoretically-expected 3:1 third-order IMD slope for output power.  
         [0017]    [0017]FIG. 2 is a schematic circuit diagram for the RF detector, DC amplifier, and level shifter blocks shown in FIG. 1.  
         [0018]    [0018]FIG. 3 is a flowchart of the method of the invention for maintaining the theoretically-expected 3:1 third-order distortion slope for output power. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    The invention relates to an amplifier device wherein the theoretical 3:1 third-order IMD power slope is maintained. This is achieved by using a feedback mechanism that adjusts the bias current, increasing it as a function of output power, to keep the third-order IMD on this theoretical slope.  
         [0020]    The feedback circuit is illustrated in FIG. 1. RF input signal  10  is amplified by the circuit, producting RF output signal  40 . RF input signal  10  is first amplified by RF amplifier  20 . The amplified signal is then fed into a power divider  30 . In one embodiment, the RF amplifier  20  is a monolithic GaAs metal-semiconductor field-effect transistor (“MESFET”) circuit, although alternative amplifiers are also within the scope of the invention. Such alternative amplifiers include, but are not limited- to, amplifiers formed from different types of transistors, including other field-effect transistors as well as bipolar junction transistors.  
         [0021]    Power divider  30  samples the power of the amplified signal and feeds it into RF detector  50 . In one embodiment, power divider  30  is a simple power divider with an equal power split. In a preferred embodiment, however, power divider  30  provides an unequal split, with the signal fed to RF detector  50  having a strength less than that for RF output signal  40 . This is to minimize the through loss of the RF signal. Preferably, the strength of the signal fed to RF detector  50  is at least 10 dB less than the strength of RF output signal  40 . In one embodiment, the power divider  30  is a coupler fabricated using a ferrite core. In an alternative embodiment, the power divider 30 comprises a resistor or other circuitry that divides power.  
         [0022]    RF detector  50  produces a DC voltage that is proportional to the RF signal power input from RF power divider  30 . This DC signal is fed back to RF amplifier  20 , preferably through a DC amplifier  60  and a level shifter  70 . The function of DC amplifier  60  and level shifter  70  are to ensure that the DC signal that is fed back into RF amplifier  20  increases the DC bias in the RF amplifier  20  as a function of the RF output power such that the third-order IMD remains on the 3:1 slope.  
         [0023]    [0023]FIG. 2 is a schematic circuit diagram illustrating an embodiment of RF detector  50 , DC amplifier  60 , and level shifter  70 . In FIG. 2, the RF output from power divider  30  passes through DC blocking capacitor C 1 . Detector diode D 1 , given a small forward-bias current (about 20 microamperes for a typical Schottky diode detector) by resistor R 1  and inductor L 1 , rectifies the RF signal by conducting current only when the voltage at node  200  is less than the voltage at node  210  minus the diode cut-in voltage (normally 0.6 V for a silicon diode). Diode D 1  does not conduct when the voltage at node  200  is greater than the voltage at node  210  minus the diode cut-in voltage. The current through diode D 1  accordingly follows the negative peaks of the input signal waveform with an inversely proportional linear relationship between the diode current and the input voltage.  
         [0024]    The voltage at node  210  behaves as follows. When diode D 1  is forward biased by a negative voltage at node  200 , the voltage at node  210  tracks the voltage at node  200  (plus the voltage developed across diode D 1 , which is approximately 0.7 V for a silicon diode or 1.3 V for a GaAs diode. When diode D 1  is reverse biased, however, the voltage at node  210  is held fixed by bypass capacitor C 2 . This capacitor should be sufficiently large that the voltage at node  210  tracks slow changes in the average output power of the RF amplifier rather than instantaneous changes in output power or in the modulation of the carrier. In the preferred embodiment, the size of bypass capacitor is selected to cause the video bandwidth of the detector to be about 1 Hz.  
         [0025]    Thus, the output of the detector (the voltage at node  210 ) is a DC signal that is inversely proportional to the RF power output from power divider  30 . When the RF power is small, the DC signal is large (more positive or less negative); when the RF power is large, the DC signal is small (less positive or more negative).  
         [0026]    This DC signal then passes to DC amplifier  60 , formed by resistors R 2 , R 3 , R 4 , and R 5  and transistors Q 1  and Q 2 . The transistors may be field-effect or bipolar-type transistors. Resistors R 4  and R 5 , connected in series between positive voltage supply +V and ground, create a reference voltage at node  220  through voltage division. This voltage at node  220  (V 220 ) is determined by the ratio of the values of R 4  and R 5 :  
         V   220     =       +   V     *     R5     R4   +   R5                               
 
         [0027]    Transistors Q 1  and Q 2  and resistors R 3  and R 2  form a conventional differential amplifier. Resistor R 2  sets the gain of the differential amplifier, while resistor R 3  sets the current through transistors Q 1  and Q 2 . In a preferred embodiment, resistor R 3  is quite large in relation to resistor R 2 .  
         [0028]    The output of DC amplifier  60  is the voltage at node  230  (V 230 ), which is proportional to the difference between the voltage V 210  at the gate of transistor Q 1  and the reference voltage V 220 . V 230  is thus proportional to, and inverted to, V 210 . For example, an increase in the RF detector  50  output voltage at node  210  would cause a decrease in the voltage at node  230 , and vice versa. The magnitude of V 230  is, of course, determined by the gain of the differential amplifier.  
         [0029]    The voltage at node  230  (V 230 ) is then input to level shifter  70 , which in one embodiment comprises a buffering transistor Q 3  and resistors R 6  and R 7 , which provide the DC voltage level-shifting. Resistors R 6  and R 7  are selected to provide an appropriate range for the bias control voltage V CONTROL . The magnitude of this voltage is dependent on the RF amplifier design and, in a preferred embodiment, varies about 100 mV over the full range of RF output power.  
         [0030]    To summarize, when an input signal is present at the input of capacitor C 1 , detector  50  causes a proportional inverted signal to appear at node  210 . The DC amplifier  60  then inverts the inverted signal to a non-inverted, amplified signal, and level shifter  70  shifts the amplified signal to a range appropriate for biasing RF amplifier  20 . When the input signal power is small, the RF amplifier bias voltage will be small, and when the input signal is large, the RF amplifier bias voltage will be large. Thus, the quiescent operating point of RF amplifier  20  is continuously adjusted so that RF amplifier  20  operates in a more linear range on its I-V curve, and the third order IMD is maintained on the theoretically-expected curve even at high RF output power.  
         [0031]    [0031]FIG. 3 is a flowchart illustrating the method of the invention for maintaining third-order IMD products on the theoretical 3:1 slope. While it is preferred that the steps be performed by a circuit configuration similar to the one shown in FIG. 1 and described above, alternative configurations may also be used.  
         [0032]    In step  110 , the RF signal to be amplified is input. This signal is amplified in step  120 . The amplified signal is then divided at step  130 . Preferably, division of the amplified signal is unequal, with the signal fed along path  132  having a strength less than that fed along path  134 . This is to minimize the through loss of the RF signal. It is preferred that the strength of the signal fed along path  132  be at least 10 dB less than the strength of the signal fed along path  134 . The portion of the divided signal fed along path  132  is then used at step  150  to generate a DC signal with a voltage proportional to the RF signal input along path  132 . This DC signal is preferably amplified at step  160  and level-shifted at step  170  so that it can be fed back to step  120 .  
         [0033]    The portion of the divided signal fed along path  134  is output as the amplified RF signal at step  140 . The steps of amplifying  160  and level-shifting  170  the DC signal have the effect of increasing the DC bias used at the RF amplification step  120  at such a rate that the third-order IMD remains on the theoretical 3:1 slope.  
         [0034]    While the invention has been described with reference to a specific embodiment, it will be appreciated by those of ordinary skill in the art that modifications can be made to the structure and form of the invention without departing from its spirit and scope, which is defined in the following claims.