Abstract:
A semiconductor substrate for forming a pixel area provided surfacially with a plurality of pixels for photoelectric conversion, the semiconductor substrate, including a polysilicon film of a thickness of 0.5-2.0, on a rear surface of the pixel area-bearing surface, and having an oxygen concentration of 1.3-1.5E+18 atom/cm 3  (old ASTM).

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a gettering substrate for reducing a pixel defect generated by a heavy metal impurity in a solid-state image pickup device such as a CMOS image pickup device, a semiconductor substrate for a solid-state image pickup device, and a producing method therefor.  
         [0003]     2. Related Background Art  
         [0004]     It is already known that, in a semiconductor device manufacturing process, characteristics of the device are deteriorated when a crystalline defect, generated by a contamination by a heavy metal such as Fe, Ni, Cr etc. present in a semiconductor substrate, is formed on a surface of the semiconductor substrate on which a device is to be formed.  
         [0005]     In particular, in a CMS image pickup device, a crystalline defect generated in a photoelectric converting device generates a weak current in a dark state, causing a white dot defect in the image pickup device.  
         [0006]     For reducing such white dot defect, there has been employed an IG (intrinsic gettering) method or a PBS (polysilicon back seal) method.  
         [0007]     The IG method is described for example in Japanese Patent Application Laid-open No. H11-021200, and the PBS is described for example in Japanese Patent Application Laid-open No. H07-022429 (corresponding to U.S. Pat. No. 5,419,786).  
         [0008]     Also in order to avoid a drawback of excessive BMD (bulk micro defect) generation in the PBS method, Japanese Patent Application Laid-open No. H08-045944 describes a temperature defining prior to a polysilicon film formation on the rear surface, and Japanese Patent Application Laid-open Nos. H08-104592 and H11-103042 describe that an impurity introduction leads to a dark current generation and a white dot defect in the semiconductor image pickup apparatus.  
         [0009]     It is also known that an output of the white dot defect in the image pickup apparatus depends on a type of heavy metal constituting the cause thereof.  
         [0010]     For gettering of such various heavy metals, the IG method and the PBS method are useful.  
         [0011]     However, a single gettering technology is insufficient for achieving a gettering effect for plural heavy metals.  
         [0012]     This is because each heavy metal has a matching gettering technology.  FIG. 5  briefly shows an example.  
         [0013]     It is shown that the PBS method is more effective than the IG method for a certain output, and the IG method is more effective for other output.  
         [0014]     Therefore, for reducing the number of white dot defects thereby improving the image obtained by the image pickup apparatus, there is desired a gettering technology effective for various heavy metals constituting the cause of such defects.  
       SUMMARY OF THE INVENTION  
       [0015]     The above-mentioned objective can be attained, according to the present invention, by a semiconductor substrate for forming a pixel area provided at a surface thereof with a plurality of pixels for photoelectric conversion, the semiconductor substrate including, on a rear surface of the pixel area-bearing surface, a polysilicon film of a thickness T within a range of 0.5≦T≦2.0 μm, and the semiconductor substrate having an oxygen concentration D within a range of 1.3E18≦D≦1.5E18 atom/cm 3  told ASTM).  
         [0016]     The present invention also provides a semiconductor substrate for forming a pixel area provided at a surface thereof with a plurality of pixels for photoelectric conversion, the semiconductor substrate including, on a rear surface of the pixel area-bearing surface, a polysilicon film of a thickness T within a range of 0.5≦T≦2.0 μm, also including a non-defective area in a part of the semiconductor substrate, and having a bulk micro defect density of 1E5/cm 2  or higher in the semiconductor substrate.  
         [0017]     The present invention further provides a producing method for a semiconductor substrate for forming a pixel area provided at a surface thereof with a plurality of pixels for photoelectric conversion, the method including a step of forming a polysilicon film of a thickness T within a range of 0.5≦T≦2.0 μm on a rear surface of the pixel area-bearing surface, and a step of obtaining an oxygen concentration D within a range of 1.3E18≦D≦1.5E18 atom/cm 3  (old ASTM) by a thermal process in the semiconductor substrate, and further including a step of executing a thermal process for 1 hour or longer at a temperature H within a range of 450≦H≦7.50° C. prior to a step of forming a wiring on the semiconductor substrate.  
         [0018]     The present invention further provides a producing method for a semiconductor substrate for forming a pixel portion provided at a surface thereof with a plurality of pixels for photoelectric conversion, the method including a step of forming a polysilicon film of a thickness T within a range of 0.5≦T≦2.0 μm on a rear surface of the pixel area-bearing surface, a step of forming a non-defective area in a part of the semiconductor substrate, and a step of realizing a bulk micro defect density of 1E5/cm 2  or higher in the semiconductor substrate, and further including a step of executing a thermal process for 1 hour or longer at a temperature H within a range of 450≦H≦750° C. prior to a step of forming a wiring on the semiconductor substrate.  
         [0019]     Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]      FIG. 1  is an equivalent circuit diagram of a semiconductor image pickup apparatus in a first embodiment of the present invention;  
         [0021]      FIG. 2  is a cross sectional view of a pixel portion in the first embodiment of the present invention;  
         [0022]      FIGS. 3A, 3B ,  3 C,  3 D,  3 E and  3 F are cross sectional views showing a substrate preparation process in a third embodiment of the present invention;  
         [0023]      FIG. 4  is a chart showing experimental results on white dot defects in embodiments of the present invention and comparative examples; and  
         [0024]      FIG. 5  is a chart showing an effect of a gettering technology. 
     
    
       [0025]     The accompanying drawings, which are incorporated in and constitutes a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]     The present inventors have noticed a relation between a type of heavy metal inducing a white dot defect in the solid-state image pickup device and an optimum gettering technology for reducing each heavy metal. More specifically, in a configuration having a PBS on a rear surface of the semiconductor substrate opposite to a surface thereof on which a light receiving portion is to be formed, at least either of an oxygen concentration and a BMD in the substrate is controlled in a range so as to reduce a white dot defect to a level substantially not causing a problem in the characteristics of the image pickup device.  
         [0027]     For the oxygen concentration in the semiconductor substrate with PBS, a concentration sufficient for a spontaneous BMD formation in the thermal process is defined as a lower limit, and a concentration for preventing remaining defects is defined as an upper limit.  
         [0028]     Such limit definitions allows the white dot defects to remain within a range not constituting a problem in the solid-state image pickup device.  
         [0029]     Also for the BMD density in the semiconductor substrate with PBS, a lower limit is so selected as to advantageously capture heavy metals.  
         [0030]     Preparation of a substrate equipped with such two gettering layers can be realized as follows.  
         [0031]     A PBS formation on a semiconductor substrate developed by a CZ method involves a thermal process at 550-650° C., which tends to develop BMD.  
         [0032]     Thus BMD remains on the substrate surface on which a device is to be formed, thereby resulting in drawbacks such as white dot defect.  
         [0033]     For avoiding such drawbacks, it is commonly executed to lower the oxygen concentration in the substrate, constituting the cause for BMD, or to apply an appropriate thermal process prior to the PBS formation thereby setting BMD in the substrate at 1E+5/cm 2  or less even in a PBS substrate.  
         [0034]     In contrast, the present inventors having found to provide the substrate with a non-defective area (denuded zone) by an IG method prior to PBS formation, also to positively form BMD in the substrate and to thereafter form PBS.  
         [0035]     In this manner there can be realized preparation of a semiconductor substrate in which surface defects do not remain by the PBS and which effectively reduces the white dot damage in the image pickup device.  
         [0036]     Also it is furthermore effective, as described in the foregoing, to apply, to such substrate, a final low-temperature thermal processing at 450-750° C. for 1 hour or longer prior to a step of forming a wiring.  
         [0037]     In the following, the present invention will be clarified further by embodiments thereof.  
         [0038]     [First Embodiment] 
         [0039]      FIG. 1  is an equivalent circuit diagram of a solid-state image pickup device of the present embodiment.  
         [0040]     The present embodiment will be explained by so-called CMOS image pickup device having an amplifying element in a light-receiving portion.  
         [0041]     There are provided a photodiode (PD)  301 , a transfer MOS transistor  302  for transferring a signal charge generated in the PD, a floating diffusion area (FD)  303  for temporarily storing the transferred signal charge, a resetting MOS transistor  304  for resetting the FD  303 , a selecting MOS transistor  305  for selecting an arbitrary row in an array, a source follower MOS transistor  306  for converting the signal charge of the FD  3  into a voltage and amplifying it, a signal readout line  307  for reading a pixel voltage signal commonly for a row, and a constant current source  308 .  
         [0042]     However the configuration of a pixel is not limited to the foregoing, and thereby may also be adopted a configuration in which the transfer MOS transistor is omitted, a configuration in which the selecting MOS transistor is omitted, or a configuration sharing a specified MOS transistor for a pixel.  
         [0043]      FIG. 2  is a cross-sectional view of a pixel portion of the present embodiment, illustrating a photodiode portion  1  and a transfer MOS transistor portion  2 .  
         [0044]     There are shown an n-type silicon substrate  3 , and a P-type well  4  formed by plural layers, having a 4-layered structure with layers  4 A- 4 D in the present embodiment.  
         [0045]     Between the layers  4 A- 4 D of the well, N-type semiconductor layers  4 E- 4 G are provided.  
         [0046]     There are also shown a gate electrode  7  of the transfer MOS transistor, an N-type charge accumulation area  8  of the photodiode, a surface P-type area (constituting a surface charge recombination area) for obtaining PD of an embedded structure, a field oxide film  5  for device isolation, and an N-type high concentration area  10  constituting the FD to which a charge is transferred from the N-type charge accumulation area  8 .  
         [0047]     There are further shown a silicon oxide film  11  for insulating the gate electrode and a first metal layer, a contact plug  12 , a first metal layer  13 , an interlayer insulation film  14  for insulating the first metal layer and a second metal layer, a second metal layer  15 , an interlayer insulation film  16  for insulating the second metal layer and a third metal layer, a third metal layer  17 , and a passivation film  18 .  
         [0048]     On the passivation film  18 , there are formed a color filter layer and a microlens for sensitivity increase, which are not illustrated.  
         [0049]     In the present embodiment, the wiring layer has a three-layered structure, but the wiring layer of one- or two-layered structure, for securing the optical characteristics according the specification of the sensor, is not against the principle of the present invention.  
         [0050]     A reduction of the white dot defect in the semiconductor image pickup apparatus can be achieved by a metal gettering on a gettering site to induce a redistribution of a metal impurity in the direction of depth, thereby eliminating the metal from the N-type charge accumulation area  8  of the depleted PD.  
         [0051]     In the following, a producing process will be explained with reference to a cross-sectional view shown in  FIG. 2 .  
         [0052]     At first an n-substrate ( 100 ) is prepared.  
         [0053]     A polysilicon  20  constituting PBS is formed on the rear surface of the substrate, and, as BMD is spontaneously formed by a thermal processing in the process, the oxygen concentration D in the substrate is made 1.3E18 atom/cm 3  (old ASTM) or higher, and is made 1.5E18 atom/cm 3  (old ASTM) or lower in order to prevent residual defects.  
         [0054]     More preferably, a value of 1.4E18 atom/cm 3  (old ASTM) or higher allows to bring the BMD density to a more preferred range.  
         [0055]     Conditions of thermal processing may be so selected as to obtain an oxygen concentration as described above.  
         [0056]     The polysilicon  20  preferably has a film thickness T of 0.5 μm or more for obtaining a gettering effect, and 2.0 μm or less in consideration of productivity.  
         [0057]     The old ASTM means old standards of the American Society for Testing and Materials.  
         [0058]     Then a field oxide film  5  is formed on the silicon substrate  3  by an ordinary LOCOS method or a recessed LOCOS method.  
         [0059]     After a channel stop layer  6  is formed under the field oxide film  5 , a plural-layered P-well is formed by executing ion plantations of four times in the present embodiment with a P-type impurity (such as boron) in succession from the deepest layer with a high energy ion implantation apparatus, and by not executing a high-temperature thermal process such as drive-in thereafter.  
         [0060]     The thermal process executed thereafter is at about 950° C. at maximum.  
         [0061]     Then, after formation of a polysilicon electrode  7 , an N-type charge accumulation area  8  of the photodiode, a P-surface layer  9  and an N-type high concentration layer  10  are formed by ion implantation.  
         [0062]     The producing process after a contact hole opening step is same as that in a prior CMOS area sensor and will not, therefore, be explained further.  
         [0063]     A PBS formation on a rear surface of the substrate opposite to the pixel area-bearing surface and a defining of thee oxygen concentration in the substrate as in the present embodiment allow to reduce the white dot defects in comparison with a substrate not subjected to such gettering process.  
         [0064]     [Second Embodiment] 
         [0065]     The present embodiment is different from the first embodiment in that, in order to further increase BMD by a thermal processing in the production process, a low-temperature thermal process at a temperature H within a range of 450 to 750° C. for 1 hour or longer is added prior to a step of forming a wiring.  
         [0066]     Other conditions are same as in the first embodiment.  
         [0067]     [Third Embodiment] 
         [0068]     The present embodiment is different from the first embodiment in that an IG process is applied to the PBS substrate thereby positively forming BMD in the substrate. The substrate producing process of the present embodiment will be explained with reference to  FIGS. 3A-3F .  
         [0069]     At first an n-type ( 100 ) silicon substrate  501  obtained by a CZ (Czochralki) process is prepared ( FIG. 3A ).  
         [0070]     An oxygen concentration in the substrate is preferably 1.4E18 atom/cm 3  or higher in order to increase the BMD density.  
         [0071]     Such substrate  501  is subjected to a mirror polishing on the top surface or on the top and rear surfaces, and is then subjected to a high-temperature thermal process at 1100° C. or higher to externally diffuse oxygen on the substrate surface, thereby forming a denuded zone (DZ)  502  constituting a defect-free area on the substrate surface on which a device is to be formed ( FIG. 3B ).  
         [0072]     Then a low-temperature thermal process is executed at about 550-650° C. to form oxygen precipitation nuclei in the substrate, and a thermal process is executed at 900° C. or higher to form BMD by such oxygen precipitation nuclei ( FIG. 3C ).  
         [0073]     Thereafter an epitaxial layer may be or may not be formed, and there is not change in the gettering effect to be obtained.  
         [0074]     Then the substrate surfaces are oxidized by several tens of nanometers in an oxygen atmosphere ( FIG. 3C ), thereby forming silicon oxide films  504  on the top and rear surfaces.  
         [0075]     Thereafter, the silicon oxide film  504  on the rear surface is etched off ( FIG. 3D ), and a polysilicon layers  505  are formed ( FIG. 3E ).  
         [0076]     Such polysilicon layer is to constitute PBS, and preferably has a thickness of 0.5 μm or more in order to obtain a gettering effect and 2.0 μm or less in consideration of the productivity.  
         [0077]     Then the polysilicon layer  505  and the silicon oxide film  504  on the top surface are etched off, thereby obtaining two gettering layers of IG and PBS ( FIG. 3F ).  
         [0078]     The process conditions thereafter are same as in the first and second embodiments.  
         [0079]     As explained in the second embodiment, the white dot defects can be further reduced by adding a low-temperature thermal process at 450-750° C. for 1 hour or longer prior to the step of forming a wiring.  
         [0080]      FIG. 4  is a chart showing experimental results of the foregoing embodiments and comparative examples.  
         [0081]     In  FIG. 4 , DZ-IG indicates an example in which DZ alone is formed by the IG method, and PBS (low oxygen concentration) indicates an example in which PBS is formed on the rear surface of the pixel area-bearing surface, but the oxygen concentration is lower than that specified in the first embodiment. These two constitute comparative examples.  
         [0082]     On the other hand, the first embodiment of the present invention has a PBS and specifies the oxygen concentration in the substrate (high oxygen concentration). The second embodiment utilizes a low-temperature process for example in a wiring step (PBS (high oxygen concentration &amp; low-temperature process)). The third embodiment has a PBS and a DZ formed on the substrate top surface by IG method (PBS &amp; DZ-IG), or further has a low-temperature thermal process (PBS &amp; DZ-IG (low-temperature process)). These embodiments of the invention are capable of reducing the white dot defects.  
         [0083]     More specifically, the case “PBS (high oxygen concentration)” showed defects reduced by about 10% in comparison with the case “DZ-IG”, and the case “PBS (high oxygen concentration &amp; low-temperature process)” showed defects reduced by about 20% in comparison with the case “DZ-IG”. Further, the case “PBS &amp; DZ-IG” showed defects reduced by about 40% in comparison with the case “DZ-IG”, and the case “PBS &amp; DZ-IG (low-temperature process)” showed defects reduced by about 20% in comparison with the case “DZ-IG”.  
         [0084]     This application claims priority from Japanese Patent Application No. 2004-358343 filed on Dec. 10, 2004, which is hereby incorporated by reference herein.