Abstract:
One embodiment of the present invention provides a method for fabricating solar cells. During operation, an anti-reflection layer is deposited on top of a semiconductor structure to form a photovoltaic structure, and a front-side electrode grid comprising a metal stack is formed on top of the photovoltaic structure. The metal stack comprises a metal-adhesive layer comprising Ti or Ta, and a conducting layer comprising Cu or Ag situated above the metal-adhesive layer.

Description:
RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 61/381,659, entitled “SOLAR CELL WITH METAL GRIDS FABRICATED BY USING ELECTROPLATING,” by inventors Jianming Fu, Zheng Xu, Chentao Yu, and Jiunn Benjamin Heng, filed 10 Sep. 2010. 
    
    
     BACKGROUND 
     Field 
     This disclosure is generally related to designing of solar cells. More specifically, this disclosure is related to a solar cell that includes a metal grid fabricated by an electroplating technique. 
     Related Art 
     The negative environmental impact caused by the use of fossil fuels and their rising cost have resulted in a dire need for cleaner, cheaper alternative energy sources. Among different forms of alternative energy sources, solar power has been favored for its cleanness and wide availability. 
     A solar cell converts light into electricity using the photovoltaic effect. There are several basic solar cell structures, including a single p-n junction solar cell, a p-i-n/n-i-p solar cell, and a multi junction solar cell. A typical single p-n junction structure includes a p-type doped layer and an n-type doped layer. Solar cells with a single p-n junction can be homojunction solar cells or heterojunction solar cells. If both the p-doped and n-doped layers are made of similar materials (materials with equal bandgaps), the solar cell is called a homojunction solar cell. In contrast, a heterojunction solar cell includes at least two layers of materials of different bandgaps. A p-i-n/n-i-p structure includes a p-type doped layer, an n-type doped layer, and an intrinsic (undoped) semiconductor layer (the i-layer) sandwiched between the p-layer and the n-layer. A multi junction structure includes multiple single junction structures of different bandgaps stacked on top of one another. 
     In a solar cell, light is absorbed near the p-n junction, generating carriers. The carriers diffuse into the p-n junction and are separated by the built-in electric field, thus producing an electrical current across the device and external circuitry. An important metric in determining a solar cell&#39;s quality is its energy-conversion efficiency, which is defined as the ratio between power converted (from absorbed light to electrical energy) and power collected when the solar cell is connected to an electrical circuit. 
       FIG. 1  presents a diagram illustrating an exemplary homojunction solar cell based on a crystalline-Si (c-Si) substrate (prior art). Solar cell  100  includes a front-side Ag electrode grid  102 , an anti-reflection layer  104 , an emitter layer  106 , a substrate  108 , and an aluminum (Al) back-side electrode  110 . Arrows in  FIG. 1  indicate incident sunlight. 
     In conventional c-Si based solar cells, the current is collected by front-side Ag grid  102 . To form Ag grid  102 , conventional methods involve printing Ag paste (which often includes Ag particle, organic binder, and glass frit) onto the wafers and then firing the Ag paste at a temperature between 700° C. and 800° C. The high-temperature firing of the Ag paste ensures good contact between Ag and Si, and lowers the resistivity of the Ag lines. The resistivity of the fired Ag paste is typically between 5×10 −6  and 8×10 −6  ohm-cm, which is much higher than the resistivity of bulk silver. 
     In addition to the high series resistance, the electrode grid obtained by screen-printing Ag paste also has other disadvantages, including higher material cost, wider line width, and limited line height. As the price of silver rises, the material cost of the silver electrode has exceeded half of the processing cost for manufacturing solar cells. With the state-of-the-art printing technology, the Ag lines typically have a line width between 100 and 120 microns, and it is difficult to reduce the line width further. Although inkjet printing can result in narrower lines, inkjet printing suffers other problems, such as low productivity. The height of the Ag lines is also limited by the printing method. One print can produce Ag lines with a height that is less than 25 microns. Although multiple printing can produce lines with increased height, it also increases line width, which is undesirable for high-efficiency solar cells. Similarly, electroplating of Ag or Cu onto the printed Ag lines can increase line height at the expense of increased line width. In addition, the resistance of such Ag lines is still too high to meet the requirement of high-efficiency solar cells. 
     Another solution is to electroplate a Ni/Cu/Sn metal stack directly on the Si emitter. This method can produce a metal grid with lower resistance (the resistivity of plated Cu is typically between 2×10 −6  and 3×10 −6  ohm-cm). However, the adhesion of Ni to Si is less than ideal, and stress from the metal stack may result in peeling of the whole metal lines. 
     SUMMARY 
     One embodiment of the present invention provides a method for fabricating solar cells. During operation, an anti-reflection layer is deposited on top of a photovoltaic structure, and a front-side electrode grid comprising a metal stack is formed on top of the anti-reflection layer. The metal stack comprises a metal-adhesive layer comprising Ti or Ta, and a conducting layer comprising Cu or Ag situated above the metal-adhesive layer. 
     In a variation on the embodiment, the metal-adhesive layer further comprises one or more of: TiN, TiW, TiSi, TaN, and Co. 
     In a variation on the embodiment, the metal-adhesive layer is formed using a physical vapor deposition (PVD) technique including one of: evaporation and sputtering deposition. 
     In a variation on the embodiment, a soldering layer comprising Sn or Ag is formed on top of the conducting layer. 
     In a variation on the embodiment, the metal-adhesive layer has a thickness between 1 nm and 1000 nm. 
     In a further variation, the metal-adhesive layer has a thickness between 5 nm and 50 nm. 
     In a variation on the embodiment, the conducting layer is formed by depositing a metal seed layer above the metal-adhesive layer, and depositing a bulk-metal layer above the metal seed layer. 
     In a further variation, the metal seed layer is formed using a physical vapor deposition (PVD) technique including one of: evaporation and sputtering deposition. 
     In a further variation, the bulk-metal layer is formed by depositing a patterned masking layer on the metal seed layer and plating a layer of metal over the patterned masking layer. Openings of the masking layer correspond to positions of the front-side electrode grid, and the plated metal has a similar material makeup as that of the metal seed layer. 
     In a further variation, the method comprises removing the masking layer and performing an etching process to remove portions of the metal seed layer and the metal-adhesive layer that are not covered by the plated metal. 
     In a further variation, the bulk-metal layer is formed by depositing a patterned masking layer on the metal seed layer, performing an etching process to remove portions of the metal seed layer and the metal-adhesive layer that are not covered by the patterned masking layer, removing the patterned masking layer to expose un-etched portions of the metal seed layer, and plating a layer of metal over the un-etched portions of the metal seed layer. Areas covered by the patterned masking layer correspond to positions of the front-side electrode grid, and the plated metal has a similar material makeup as that of the metal seed layer. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIG. 1  presents a diagram illustrating an exemplary solar cell (prior art). 
         FIG. 2  presents a diagram illustrating an exemplary process of fabricating a solar cell in accordance with an embodiment of the present invention. 
         FIG. 3  presents a diagram illustrating an exemplary process of fabricating a solar cell in accordance with an embodiment of the present invention. 
     
    
    
     In the figures, like reference numerals refer to the same figure elements. 
     DETAILED DESCRIPTION 
     The following description is presented to enable any person skilled in the art to make and use the embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     Overview 
     Embodiments of the present invention provide a solar cell that includes a metal grid formed by electroplating. The solar cell includes a crystalline-Si (c-Si) substrate, an emitter layer, a passivation layer, a metal-adhesion layer, and front- and back-side electrode metal grids. The metal-adhesion layer is formed using a physical vapor deposition (PVD) technique, such as sputtering or evaporation. The front-side metal grid is formed by selectively electroplating a metal stack, which can be a single-layer or a multi-layer structure, on the metal-adhesion layer. The back-side electrode is formed by screen-printing, electroplating, or aerosol-jet printing of a metal grid. 
     Fabrication Process 
       FIG. 2  presents a diagram illustrating an exemplary process of fabricating a solar cell in accordance with an embodiment of the present invention. 
     In operation  2 A, a Si substrate  200  is prepared. In one embodiment, Si substrate  200  can be a p-type crystalline-Si (c-Si) wafer. In a further embodiment, preparing Si substrate  200  includes standard saw damage etch (which removes the damaged outer layer of Si) and surface texturing. 
     In operation  2 B, a lightly doped emitter layer  202  is formed on top of Si substrate  200 . Depending on the doping type of Si substrate  200 , emitter layer  202  can be either n-type doped or p-type doped. In one embodiment, emitter layer  202  is lightly doped with n-type dopant. In a further embodiment, emitter layer  202  is formed by diffusing phosphorous. Note that if phosphorus diffusion is used for forming emitter layer  202 , phosphosilicate glass (PSG) etch and edge isolation is needed. 
     In operation  2 C, an anti-reflection layer  204  is formed on top of emitter layer  202 . In one embodiment, anti-reflection layer  204  includes, but not limited to: silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), aluminum oxide (Al 2 O 3 ), and their combinations. In one embodiment, anti-reflection layer  204  includes a layer of a transparent conducting oxide (TCO) material, such as indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), tungsten doped indium oxide (IWO), and their combinations. 
     In operation  2 D, back-side electrode  206  is formed on the back side of Si substrate  200 . In one embodiment, forming back-side electrode  206  includes printing a full Al layer and subsequent allying through firing. In one embodiment, forming back-side electrode  206  includes printing an Ag/Al grid and subsequent furnace firing. 
     In operation  2 E, a number of contact windows, including windows  208  and  210 , are formed in anti-reflection layer  204 . In one embodiment, heavily doped regions, such as regions  212  and  214  are formed in emitter layer  202 , directly beneath contact windows  208  and  210 , respectively. In a further embodiment, contact windows  208  and  210  and heavily doped regions  212  and  214  are formed by spraying phosphorous on anti-reflection layer  204 , followed by a laser-groove local-diffusion process. Note that operation  2 E is optional, and is needed when anti-reflection layer is electrically insulating. If anti-reflection layer  204  is electrically conducting (e.g., when anti-reflection layer  204  is formed using TCO material), there is no need to form the contact windows. 
     In operation  2 F, an adhesive layer  216  is formed on anti-reflection layer  204 . In one embodiment, materials used to form adhesive layer  216  include, but are not limited to: Ti, titanium nitride (TiN x ), titanium tungsten (TiW x ), titanium silicide (TiSi x ), titanium silicon nitride (TiSiN), Ta, tantalum nitride (TaN x ), tantalum silicon nitride (TaSiN x ), nickel vanadium (NiV), tungsten nitride WN x ), Co, W, Cr, Mo, Ni, and their combinations. In a further embodiment, adhesive layer  216  is formed using a physical vapor deposition (PVD) technique, such as sputtering or evaporation. The thickness of adhesive layer  216  can range from a few nanometers up to 100 nm. Note that Ti and its alloys tend to form very good adhesion with Si material, and they can form good ohmic contact with heavily doped regions  212  and  214 . 
     In operation  2 G, a metal seed layer  218  is formed on adhesive layer  216 . Metal seed layer  218  can include Cu or Ag. The thickness of metal seed layer  218  can be between 5 nm and 500 nm. In one embodiment, metal seed layer  218  has a thickness of 100 nm. Similarly to adhesive layer  216 , metal seed layer  218  can be formed using a PVD technique. 
     In operation  2 H, a patterned masking layer  220  is deposited on top of metal seed layer  218 . The openings of masking layer  220 , such as openings  222  and  224 , correspond to the locations of contact windows  208  and  210 , and thus are located above heavily doped regions  212  and  214 . Note that openings  222  and  224  are slightly larger than contact windows  208  and  210 . Masking layer  220  can include a patterned photoresist layer, which can be formed using a photolithography technique. In one embodiment, the photoresist layer is formed by screen-printing photoresist on top of the wafer. The photoresist is then baked to remove solvent. A mask is laid on the photoresist, and the wafer is exposed to UV light. After the UV exposure, the mask is removed, and the photoresist is developed in a photoresist developer. Openings  222  and  224  are formed after developing. The photoresist can also be applied by spraying, dip coating, or curtain coating. Dry film photoresist can also be used. Alternatively, masking layer  220  can include a layer of patterned silicon oxide (SiO 2 ). In one embodiment, masking layer  220  is formed by first depositing a layer of SiO 2  using a low-temperature plasma-enhanced chemical-vapor-deposition (PECVD) technique. In a further embodiment, masking layer  220  is formed by dip-coating the front surface of the wafer using silica slurry, followed by screen-printing an etchant that includes hydrofluoric acid or fluorides. Other masking materials are also possible, as long as the masking material is electrically insulating. 
     In operation  2 I, one or more layers of metal are deposited at the openings of masking layer  220  to form a front-side metal grid  226 . Front-side metal grid  226  can be formed using an electroplating technique, which can include electrodeposition, light-induced plating, and/or electroless deposition. In one embodiment, metal seed layer  218  and/or adhesive layer  216  are coupled to the cathode of the plating power supply, which can be a direct current (DC) power supply, via an electrode. Metal seed layer  218  and masking layer  220 , which includes the openings, are submerged in an electrolyte solution which permits the flow of electricity. Note that, because only the openings within masking layer  220  are electrically conductive, metals will be selectively deposited into the openings, thus forming a metal grid with a pattern corresponding to that of the previously formed contact windows on anti-reflection layer  204 . Depending on the material forming metal seed layer  218 , front-side metal grid  226  can be formed using Cu or Ag. For example, if metal seed layer  218  is formed using Cu, front-side metal grid  226  is also formed using Cu. In addition, front-side metal grid  226  can include a multilayer structure, such as a Cu/Sn bi-layer structure, or a Cu/Ag bi-layer structure. The Sn or Ag top layer is deposited to assist a subsequent soldering process. When depositing Cu, a Cu plate is used at the anode, and the solar cell is submerged in the electrolyte suitable for Cu plating. The current used for Cu plating is between 0.1 ampere and 2 amperes for a wafer with a dimension of 125 mm×125 mm, and the thickness of the Cu layer is approximately tens of microns. 
     In operation  2 J, masking layer  220  is removed. 
     In operation  2 K, portions of adhesive layer  216  and metal seed layer  218  that are originally covered by masking layer  220  are etched away, leaving only the portions that are beneath front-side metal grid  226 . In one embodiment, wet chemical etching process is used. Note that, because front-side metal grid  226  is much thicker (by several magnitudes) than adhesive layer  216  and metal seed layer  218 , the etching has a negligible effect on front-side metal grid  226 . 
       FIG. 3  presents a diagram illustrating another exemplary process of fabricating a solar cell in accordance with an embodiment of the present invention. 
     In operation  3 A, a Si substrate  300  is prepared using a process similar to the one used in operation  2 A. 
     In operation  3 B, a lightly doped emitter layer  302  is formed on top of Si substrate  300 , using a process similar to the one used in operation  2 B. 
     In operation  3 C, an anti-reflection layer  304  is formed on top of emitter layer  302 , using a process similar to the one used in operation  2 C. 
     In operation  3 D, back-side electrode  306  is formed on the back side of Si substrate  300 , using a process similar to the one used in operation  2 D. 
     In operation  3 E, a number of contact windows, including windows  308  and  310 , are formed, using a process similar to the one used in operation  2 E. 
     In one embodiment, heavily doped regions  312  and  314  are formed in emitter layer  302 . 
     In operation  3 F, an adhesive layer  316  is formed on anti-reflection layer  304 , using a process similar to the one used in operation  2 F. 
     In operation  3 G, a metal seed layer  318  is formed on adhesive layer  316 , using a process similar to the one used in operation  2 G. 
     In operation  3 H, a patterned masking layer  320  is deposited on top of metal seed layer  318  using a process similar to the one used in operation  2 H. However, unlike patterned masking layer  220 , patterned masking layer  320  covers areas that correspond to the locations of contact windows  308  and  310 , while still being located above heavily doped regions  312  and  314 . Note that the covered areas are slightly larger than contact windows  308  and  310 . 
     In operation  3 I, portions of adhesive layer  316  and metal seed layer  318  that are not covered by masking layer  320  are etched away using a process similar to the one used in operation  2 K. 
     In operation  3 J, masking layer  320  is removed to expose the leftover portions of metal seed layer  318 . 
     In operation  3 K, one or more layers of metal are deposited on the leftover portions of metal seed layer  318  to form a front-side metal grid  326 , using a process similar to the one used in operation  2 I. Note that, because only the leftover portions of metal seed layer  318  are electrically conductive, a plating process can selectively deposit metal on top of the leftover portions of metal seed layer  318 . 
     The foregoing descriptions of various embodiments have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention.