Abstract:
A method and a circuit detect the presence of a high-speed signal, such as a high-speed differential signal, based on a software-programmable signal amplitude threshold. In one embodiment, when the amplitude threshold is exceeded, a current is generated to charge a capacitor. The voltage on the capacitor is compared to a second pre-set voltage in a low-speed comparator, which provides an output voltage indicating detection of the high-speed signal.

Description:
BACKGROUND 
     The present invention relates to circuits and methods for detecting high-speed signals. 
     SUMMARY 
     The present invention provides a method and a circuit that detect the presence of a high-speed signal, such as a high-speed differential signal, based on a software-programmable signal amplitude threshold. In one embodiment, when the amplitude threshold is exceeded, a current is generated to charge a capacitor. The voltage on the capacitor is compared to a second pre-set voltage in a low-speed comparator, which provides an output voltage indicating detection of the high-speed signal. In one embodiment, a high-speed differential signal operating at 3.125 Gbits per second can be detected. 
     According to one embodiment of the present invention, a high-speed signal detection circuit includes a capacitor, and a detection circuit receiving a high-speed signal and a threshold voltage. The detection circuit charges the capacitor when the high-speed signal has an amplitude exceeding the threshold voltage by a predetermined amount. In one embodiment, the high-speed signal detection circuit further includes a comparator receiving a reference voltage and coupled to the capacitor. The comparator provides an output signal having two binary states, the output signal transitioning between the binary states when a voltage on the capacitor exceeds the reference voltage. The high-speed signal can be a differential signal. 
     In one embodiment of the present invention, the high-speed signal detection circuit includes first and second transistors each having a source terminal and a drain terminal being coupled respectively to a terminal of the capacitor and a predetermined voltage, and a gate terminal coupled to one end of the differential signal. 
     In one embodiment of the present invention, the high-speed signal detection circuit generates the reference voltage by tapping a string of resistors. 
     In one embodiment of the present invention, the high-speed signal detection circuit generates a second reference voltage from the string of resistors. The reference voltage is selected by activating one of a number of switches, each switch being coupled to receive one of the first and second reference signals. In one implementation, the switches can be made software programmable. 
    
    
     The present invention is better understood upon consideration of the detailed description below and the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows signal detector circuit  100 , according to one embodiment of the present invention. 
     FIG. 2 shows generating a programmable voltage V x  in programmable voltage generation circuit  200 . 
     FIG. 3 shows the time-dependent voltage curves at terminals  130  and  136  in response to incoming data received at the differential signal across terminals  134  and  135 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides a method and a circuit that detects the presence of a high-speed differential signal, based on a software programmable signal amplitude threshold. 
     One embodiment of the present invention is shown in FIG.  1 . As shown in FIG. 1, signal detector circuit  100  includes bias generation circuit  101 , detection circuit  102 , and comparator circuit  103 . Bias generation circuit  101  includes NMOS transistor  112 , which receives a voltage V bias  at its gate and drain terminals. Voltage V bias  is selected such that NMOS transistor  112  acts as a current source that provides a current of 100 micro-Amp (uA). The current in NMOS transistor  112  is mirrored in NMOS transistor  113  and PMOS transistor  114 . The width of NMOS transistor  113  is selected to be ⅕ of the width of NMOS transistor  112 , such that the current in transistors  113  and  114  is 20 uA. This current in PMOS transistor  114  is, in turn, mirrored in PMOS transistors  115  and  116 . PMOS transistors  115  and  116  are sized to apt as 10 uA and 100 uA current sources, respectively. The current in NMOS transistor  117 , i.e., the 10 uA current in PMOS transistor  115 , is mirrored in NMOS transistor  118 . The relative sizes of NMOS transistors  117  and  118  result in 2 uA current being drawn from output node  130  of detection circuit  102 . 
     In bias generation circuit  101 , the voltage (“V p-bias ”) at gate terminal  131  of PMOS transistor  114  is provided to the gate terminal of PMOS transistor  119  of detection circuit  102 . The relative sizes of PMOS transistors  114  and  119  provide a 100 uA current in PMOS transistor  119 . The 100 uA current in PMOS transistor  116  flows in 2 KΩ resistors  171  and  172 , so that a reference voltage of 400 millivolts (mV) is provided at gate terminal  132  of PMOS transistor  123  in comparator  103 . Capacitors  161 ,  162 ,  163  and  164  are MOS capacitors provided as filtering capacitors. 
     Referring now to detection circuit  102 . In detection circuit  102 , a programmable voltage V x  is provided at gate terminal  133  of PMOS transistor  120 . Programmable voltage V x  is provided by programmable voltage generation circuit  200  of FIG. 2, described in further detail below. PMOS transistor  121  and  122 , each {fraction (1/10)} the size of PMOS transistor  120  in this embodiment, receive a differential input signal V inp  and V inn  at their respective gate terminals  134  and  135 . When there is no signal across gate terminals  134  and  135 , the common mode voltage in differential signal V inp  and V inn  is set to 500 mV. At this common mode voltage, PMOS transistors  121  and  122  are not conducting, and since a 2 uA current is drawn from output node  130  of detection circuit  102 , MOS capacitor  165  is discharged, so that the voltage at output node  130  is substantially at ground. The voltage V xx  at terminal  139  is thus given by: 
     
       
           V   xx   =V   d-sat   +V   tp   +V   x   (1) 
       
     
     Where voltage V d-sat  is the overdrive voltage at the drain terminal of transistor  120 , V tp  is the threshold voltage of a PMOS transistor and V x  is the programmable voltage received from voltage generation circuit  200 . Thus, when voltage V xx  exceeds source-to-gate voltage V sg  of either PMOS transistors  121  and  122  by PMOS threshold voltage V tp  (i.e., either inequality V xx −V inp &gt;V tp  or inequality V xx −V inn &gt;V tp  holds), the corresponding one of PMOS transistors  121  and  122  conducts, thereby charging MOS capacitor  165 . Substituting equation (1) into either inequality, we obtain: 
     
       
           V   d-sat   +V   x   &gt;V   inp   (2) 
       
     
     
       
           V   d-sat   +V   x   &gt;V   inn   (3) 
       
     
     That is, the signal levels at which incoming data is deemed received are determined by appropriately setting voltage V x . The charging current due to conduction in PMOS transistors  121  and  122  exceeds the 2 uA current of PMOS transistor  118 . Consequently, the voltage in terminal  130  of MOS capacitor  165  rises, which is amplified by comparator  103  to provide a corresponding rising output voltage at terminal  136 . FIG. 3 shows the time-dependent voltage curves  301  and  302  at terminals  130  and  136 , respectively, in response to incoming data received at the differential signal across terminals  134  and  135 . As shown in FIG. 3, the output voltage at terminal  136  of comparator  103  rapidly rises from zero volts to approximately 1 volt after 1 microsecond (us) of data activity. This rapid rise in voltage indicates detection of the high-speed differential signal. In one implementation, the differential signal at terminals  134  and  135  are received from the receiver pins of a 3.125 GHz high-speed transceiver integrated circuit. 
     FIG. 2 shows generating a programmable voltage V x  for terminal  133  in programmable voltage generation circuit  200 . As shown in FIG. 2, serially connected resistors  201  to  210  provide predetermined voltages between 274 mV to 354 mV at 20 mV intervals at terminals  230 - 234 , respectively, which can be individually selected by pass transistors  240 - 244  as the bias voltage at terminal  133  of FIG.  1 . 
     The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.