Abstract:
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation of pending U.S. patent application Ser. No. 13/243,917, filed Sep. 23, 2011, which is a continuation of U.S. patent application Ser. No. 11/893,593, filed Aug. 15, 2007 and issued as U.S. Pat. No. 8,055,852 on Nov. 8, 2011. These applications and patent are incorporated herein by reference in their entirety, for any purpose. 
     
    
     TECHNICAL FIELD 
       [0002]    This invention relates generally to memory devices, and, more particularly, to a memory device and method that facilitates access by multiple memory access devices, as well as memory systems and computer systems using the memory devices. 
       BACKGROUND 
       [0003]    As computer and computer system architecture continues to evolve, the number of processing cores and threads within cores is increasing geometrically. This geometric increase is expected to continue, even for simple, relatively inexpensive computer systems. For server systems, system sizes measured in the number of processors are increasing at an even faster rate. 
         [0004]    Although this rapid increase in the number of cores and threads enhances the performance of computer systems, it also has the effect of making it difficult to apply the increasing parallelism to single applications. This limitation exists even for high-end processing tasks that naturally lend themselves to parallel processing, such as, for example, weather prediction. One of the major reasons for this limitation is that the number of communication paths between processors, cores, and threads increases disproportionately to the number of times the task is divided into smaller and smaller pieces. Conceptually, this problem can be analogized to the size of a processing being represented by the volume of a 3D cube. Each time this volume is divided into smaller cubes, the total surface area of the cubes, which represents data that must be communicated between the processors working on sub-cubes, increases. Every time that the number of processors goes up by a factor of eight the total amount of information to be communicated between the greater number of processors doubles. 
         [0005]    One reason for these problems caused by increasing parallelism is that most systems communicate by sending messages between processors, rather than sharing memory. This approach results in high latencies and high software overheads, although it may simplify some complex system architecture, operating system, and compiler issues. Unfortunately, as the level of parallelism increases, the processors in the system reach the point where all they are doing is managing message traffic rather than actually doing useful work. 
         [0006]    There is therefore a need for a system and method that can reduce software overhead and eliminate or at least reduce performance bottlenecks thereby improving system performance and architectural scalability at relatively low cost. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a block diagram of a computer system according to one embodiment. 
           [0008]      FIG. 2  is block diagram of a portion of a system memory device containing processing logic according to one embodiment that may be used in the computer system of  FIG. 1  to allow operations to be carried out in the memory device in an indivisible manner. 
           [0009]      FIG. 3  is a block diagram of a memory device according to one embodiment that may be used in the computer system of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    A computer system  10  according to one embodiment is shown in  FIG. 1 . The computer system  10  includes several parallel processors  14   1-N  connected to a common processor bus  16 . Also connected to the processor bus  16  are a system controller  20  and a level 2 (“L2”) cache  24 . As is well known in the art, each of the processors  14   1-N  may include a level 1 (“L1”) cache. 
         [0011]    The system controller  20  drives a display  26  through a graphics accelerator  28 , which may include a graphics processor and graphics memory of conventional design. Also connected to the system controller  20  is an input/output (“I/O”) bus  30 , such as a peripheral component interconnect (“PCI”) bus, to which are connected a keyboard  32 , a mass storage device  34 , such as a hard disk drive, and other peripheral devices  36 . Of course there can also be systems such as servers that do not have directly connected keyboard, graphics or display capabilities, for example. 
         [0012]    The computer system  10  also includes system memory  40 , which may be a dynamic random access memory (“DRAM”) device or sets of such devices. The system memory  40  is controlled by memory controller circuitry  44  in the system controller  20  through a memory bus  46 , which normally includes a command/status bus, an address bus and a data bus. There are also systems in which the system and memory controller is implemented directly within a processor IC. As described so far, the computer system  10  is conventional. However, the system memory  40  departs from conventional systems by including in the system memory  40  a processing system  50  that enhancers the ability of the parallel processors  14   1-N  to access the system memory  40  in an efficient manner. It should also be understood that the system  50  may be used in memory devices in a computer or other processor-based systems that differ from the computer system  10  shown in  FIG. 1 . For example, servers and other high-end systems will generally not include the graphics accelerator  28 , the display  26 , the keyboard  32 , etc., but will have disk systems or simply connect to a network of other similar processors with attached memory. 
         [0013]    The processing system  50  includes circuitry that allows the system memory  40  to be naturally coherent by carrying out operations in the memory device an indivisible manner. The system reduces or eliminates coherency issues and may improve communication for all levels in the computer system  10 . The processing system  50  or a processing system according to some other embodiment can be implemented in the system memory  40  while keeping the internal organization of the memory system substantially the same as in conventional system memories. For example, bank timing and memory data rates can be substantially the same. Further, the system  50  need not be particularly fast as the operations needed are generally simple and fit with current and anticipated memory clock rates. 
         [0014]    In general, it is preferable for the processing to be initiated and to be performed as a single indivisible operation. An example is where a byte in a 32-bit word is updated (read and then written) while preventing access to the word while the update is being executed. Functions like these, which are sometime referred to as “atomic,” are desired when parallel processes access and update shared data. The processing system  50  allows the system memory  40  to be naturally coherent by performing operations as an indivisible whole with a single access. The coherency circuitry reduces or eliminates coherency issues and may improve communication for all levels in the computer system  10 . The coherency circuitry operates most advantageously when used with other extensions to the functionality of memory devices, such as that provided by a cache system. 
         [0015]    One embodiment of a processing system  50  is shown in  FIG. 2 . The system  50  includes a select circuit  54 , which may be a multiplexer, that routes write data to a column of a Memory Bank  58  through a set of write drivers  56 . The write data are routed to the column from either a data bus of the memory device  40  or Boolean Logic  60 . The Boolean Logic  60  receives read data from a set of sense amplifiers and page registers  56 . The read data are also applied to the data bus of the memory device  40 . 
         [0016]    In operation, the select circuit  54  normally couples write data directly to the write drivers  56  of the Bank  58 . However, in response to a command from the memory controller  44 , the select circuit  54  routes data from the Boolean Logic  60  to the write drivers  56 . In response to a read command, the read data are applied to the Boolean Logic  60 , and the Boolean Logic  60  then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank  58  where the data was read. If the memory device  40  includes a cache memory, the Boolean Logic  60  can instead perform an operation on data read from the cache memory before writing the result data back to the same location in the cache memory. 
         [0017]    Although the system  50  shown in  FIG. 2  uses Boolean Logic  60 , other embodiments may use circuits or logic that perform other increased functions. In general, this increased functionality may be logic functions, such as AND, OR, etc. functions, arithmetic operations, such as ADD and SUB, and similar operations that can update and change the contents of memory. Arithmetic functions would be very useful to multiple different kinds of software. However, as indicated above, the system  150  performs Boolean logic operations since they are also very useful functions to implement as flags and for general communication between computation threads, cores, and clusters. A Boolean operation is a standalone bit-operation since no communication between bits participating in the operation is generally required, and can be implemented efficiently on a memory die. As each Boolean operation is simple, the logic implementing the functions does not have to be fast compared to the memory clock. These functions provide coherency directly as memory is modified in the memory device. These functions, in conjunction with the protection capability described previously, enable system implementation of a set of easy to use but novel memory functions. 
         [0018]    Typical logical functions that may be implemented by the Boolean Logic  60  are shown in Table 1, below. The increased functionality can provide solutions to many of the issues that surround the increased parallelism of new computer implementations. 
         [0019]    The basic operation that is performed to implement the logic functions is: WriteData .OP. MemData→MemData where “.OP.” is a value designating a specified Boolean logic function. Memory data is modified by data contained in what is basically a Write operation, with the result returned to the same place in memory that sourced the data. An on- chip data cache can be source and/or sink of the data that is operated on by the Boolean Logic  160 . If the data source is a memory bank rather than a cache memory, an Activate to a bank specified in the command should also be issued, with the page data loaded into the normal row buffer. Write data accompanying the command is then applied to the row buffer at the specified column addresses. The result is written back to memory, though this could be under control of a Precharge bit in the Boolean logic  60 . The operation is thus a Write, but with memory data itself modifying what is written back to memory. If the data source is a cache memory, then a cache row is fetched, such as by using tag bits as described previously. After the data read from the cache memory is transformed by the logic operation, the result data are stored at the same location in the cache memory. 
         [0020]    In operation, there may be multiple different kinds of OPs, so as to enable memory bits to be set, cleared and complemented. As detailed below, this write-up shows eight different operations. A particular set of command bits are not shown here to encode the particular Boolean logic function because the implementation can be independent of the cache memory operations described previously. If combined with the use of a cache memory, a cache reference command as described above may be used. This cache reference command may be encoded using a respective set of RAS, CAS, WE, DM command signals. A set of commands is shown in Table 1, below. The manner in which those command bits map to DRAM command bits my be defined in a variety of manners. However, one embodiment of a set of instructions and an instruction mapping is shown in Table 1 in which “W” designates a write bit received by the memory device, “M” designates a bit of data read from either a bank of memory cells or the cache memory, “·” is an AND function, “+” is an OR function, and “s” is an exclusive OR function. 
         [0021]      FIG. 3  shows one embodiment of a memory device  80 . The memory device  80  includes at least one bank of memory cells  84  coupled to an addressing circuit  86  that is coupled between external terminals  88  and the at least one bank of memory cells  84 . The memory device  80  also includes a data path  90  coupled between  92  external terminals and the at least one bank of memory cells  84 . Also included in the memory device  80  is a command decoder  94  coupled to external terminals  96 . The command decoder  94  is operable to generate control signals to control the operation of the memory device  80 . Finally, the memory device  80  includes a processing system  98  coupled to the at least one bank of memory cells  84 . The processing system is operable to perform a processing function on data read from the at least one bank of memory cells  84  to provide results data and to write the results data to the at least one bank of memory cells  84 . The processing system  50  shown in  FIG. 2  may be used as the processing system  98 , or some other embodiment of a processing system may be used as the processing system  98 . 
         [0000]    
       
         
               
             
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Boolean Functions 
               
             
          
           
               
                 OP Code 
                 Primary 
                 Alternate 
                 Common 
                   
               
               
                 (octal) 
                 Equation 
                 Equation 
                 Name 
                 Operation 
               
               
                   
               
               
                 0 
                 W • M 
                   
                 AND 
                 Clear on 0&#39;s 
               
               
                 1 
                   W  • M 
                   
                   
                 Clear on 1&#39;s 
               
               
                 2 
                 W ⊕ M 
                   
                 XOR 
                 Complement on 1&#39;s 
               
               
                 3 
                   W  •  M   
                 
                   W + M 
                 
                 NOR 
                 NOR 
               
               
                 4 
                 
                   W • M 
                 
                   W  +  M   
                 NAND 
                 NAND 
               
               
                 5 
                 
                   W ⊕ M 
                 
                   
                 EQV 
                 Complement on 0&#39;s 
               
               
                 6 
                 
                   W •  
                   M 
                 
                   W  + M 
                   
                 Set on 0&#39;s 
               
               
                 7 
                 
                   W 
                    •  
                   M 
                 
                 W + M 
                 OR 
                 Set on 1&#39;s 
               
               
                   
               
               
                 Notes: 
               
               
                 1 “W” is a write bit coming from the input pins. 
               
               
                 2 “M” is a memory bit 
               
               
                 3 “•” is AND 
               
               
                 4 “+” is OR 
               
               
                 5 “⊕” is Exclusive OR 
               
             
          
         
       
     
         [0022]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.