Abstract:
The present invention provides a method of patterning a substrate, the method including, inter alia, forming a multi-layered structure on the substrate formed from first, second and third materials. The first, second and third materials are exposed to an etch chemistry, with the first and second materials having a common etch rate along a first direction, defining a first etch rate, and the first and third materials having a similar etch rate along a second direction, transversely extending to the first direction, defining a second etch rate. Typically, the etch rate is selected to be different in furtherance of facilitating control of the dimensions of features formed during the etching process.

Description:
BACKGROUND OF THE INVENTION 
   The field of the invention relates generally to semiconductor processing. More particularly, the present invention is directed to a method of controlling the critical dimension of structures formed on a substrate. 
   Micro-fabrication involves the fabrication of very small structures, e.g., having features on the order of micro-meters or smaller. One area in which micro-fabrication has had a sizeable impact is in the processing of integrated circuits. As the semiconductor processing industry continues to strive for larger production yields while increasing the circuits per unit area formed on a substrate, micro-fabrication becomes increasingly important. Micro-fabrication provides greater process control while allowing increased reduction of the critical dimension of the structures formed. Other areas of development in which micro-fabrication has been employed include biotechnology, optical technology, mechanical systems, and the like. 
   As the critical dimension of structures formed on substrates is reduced, there is an increasing desire to control the same. A method of controlling the critical dimension of semiconductor devices is described in U.S. Pat. No. 6,245,581 to Bonser et al. Bonser et al. describes a method and an apparatus for controlling critical dimensions. More specifically, a run of semiconductor devices is processed, a critical dimension measurement is performed upon at least one of the processed semiconductor devices, an analysis of the critical dimension is performed, and a second process upon the semiconductor devices in response to the critical dimension analysis is performed. 
   Another method of controlling the critical dimension of semiconductor devices is described in U.S. Pat. No. 5,926,690 to Toprac et al. Toprac et al. describes a control method employing a control system using photoresist etch time as a manipulated variable in either a feed-forward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. 
   It is desired, therefore, to provide an improved method of controlling the critical dimension of structures formed on a substrate. 
   SUMMARY OF THE INVENTION 
   The present invention provides a method of patterning a substrate, the method including, inter alia, forming a multi-layered structure on the substrate formed from first, second and third materials. The first, second and third materials are exposed to an etch chemistry, with the first and second materials having a common etch rate along a first direction, defining a first etch rate, and the first and third materials having a similar etch rate along a second direction, transversely extending to the first direction, defining a second etch rate. Typically, the etch rate is selected to be different in furtherance of facilitating control of the dimensions of features formed during the etching process. These embodiments and others are described more fully below. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a cross-sectional view of a prior art bi-layer structure; 
       FIG. 2  is a cross-sectional view of the bi-layer structure, shown in  FIG. 1 , having a planarization layer disposed thereon to form a multi-layered structure; 
       FIG. 3  is a cross-sectional view of the multi-layered structure, shown in  FIG. 2 , after being subjected to a blanket etch, forming etched structure, in accordance with the prior art; 
       FIG. 4  is a cross-sectional view of the etched structure, shown in  FIG. 3 , after being subjected to an anisotropic etch process, in accordance with the prior art; 
       FIG. 5  is a cross-sectional view of the etched structure, shown in  FIG. 3 , demonstrating critical-dimension control characteristics that were recognized and attenuated, in accordance with the present invention; 
       FIG. 6  is a cross-sectional view of a multi-layered structure formed in accordance with the present invention; 
       FIG. 7  is a cross-sectional view of the multi-layered structure, shown in  FIG. 6 , after being subjected to a blanket etch process, in accordance with the present invention; 
       FIG. 8  is a simplified plan view of an etch chamber that may be employed to practice the present invention; 
       FIG. 9  cross-sectional view of the multi-layered structure, shown in  FIG. 7 , after being subjected to an anisotropic etch process, in accordance with the prior art; and 
       FIG. 10  is a cross-sectional view of the multi-layered structure, shown in  FIG. 9 , after subjecting the same to etch processes to expose areas of the underlying substrate. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Referring to  FIG. 1 , a multi-layered structure  10  is shown. Multi-layered structure  10  comprises a substrate  12 , having one or more existing layers thereon, shown as a layer  14 , and a patterned layer  16 . Layer  14  is disposed between substrate  12  and patterned layer  16 . Substrate  12  may be formed from materials including, but not limited to, silicon, gallium arsenide, quartz, fused-silica, sapphire, organic polymers, siloxane polymers, borosilicate glass, fluorocarbon polymers or a combination thereof. 
   Primer layer  14  may be formed from any known material, such as aluminum, silicon nitride, a native oxide and the like. In the present example, layer  14  functions to provide a standard interface between substrate  12  and patterned layer  16 , thereby reducing the need to customize each process to the material upon which patterned layer  16  is to be deposited upon. In addition, layer  14  may be formed from a material with the same etch characteristics as patterned layer  16 . Layer  14  is fabricated in such a manner so as to possess a continuous, smooth, if not planar, relatively defect-free surface that may exhibit excellent adhesion to patterned layer  16 . Additionally, layer  14  has a substantially uniform thickness. An exemplary composition for layer  14  is available from Brewer Science, Inc. of Rolla, Mo. under the trade name DUV30J-6. Layer  14  may be deposited upon substrate  12  using any suitable method including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputter deposition, spin-coating, and dispensing of a liquid. 
   Patterned layer  16  may comprise protrusions  18  and recessions  20  forming a pattern on a surface  22  of patterned layer  16 , with recessions  20  extending along a direction parallel to protrusions  18  providing a cross-section of patterned layer  16  with a shape of a battlement. However, protrusions  18  and recessions  20  may correspond to virtually any feature required to create an integrated circuit and may be as small as a few nanometers. The pattern on surface  22  of patterned layer  16  may be formed by such techniques including, but not limited to, photolithography, e-beam lithography, x-ray lithography, ion beam lithography, and imprint lithography. Imprint lithography is described in detail in numerous publications, such as U.S. published patent application 2004/0065976, entitled, “Method and a Mold to Arrange Features on a Substrate to Replicate Features having Minimal Dimensional Variability”; 2004/0065252, entitled “Method of Forming a Layer on a Substrate to Facilitate Fabrication of Metrology Standards”; and 2004/0046271, entitled “Method and a Mold to Arrange Features on a Substrate to Replicate Features having Minimal Dimensional Variability”, all of which are assigned to the assignee of the present invention. An exemplary lithographic system utilized in imprint lithography is available under the trade name IMPRIO 250™ from Molecular Imprints, Inc., having a place of business at 1807-C Braker Lane, Suite 100, Austin, Tex. 78758. The system description for the IMPRIO 250™ is available at www.molecularimprints.com and is incorporated herein by reference. 
   Referring to  FIG. 2 , a planarization layer  24  is formed upon patterned layer  16 , forming multi-layered structure  110 . Planarization layer  24  may be formed upon patterned layer  16  in any of the methods mentioned above with respect to primer layer  14 . In a first embodiment, planarization layer  26  may comprise an organic polymerizable resist. However, in a further embodiment, planarization layer  24  may be formed from a silicon-containing polymerizable material. Exemplary materials from which patterned layer  16  and planarization layer  24  may be formed are disclosed in U.S. patent application Ser. No. 10/789,319, entitled “Composition for an Etching Mask Comprising a Silicon-Containing Material,” having Frank Xu, Michael N. Miller and Michael P. C. Watts listed as inventors and which is incorporated by reference herein. For example, patterned layer  16  may be formed from a silicon-free materials and consists of the following: 
   COMPOSITION 1 
   isobornyl acrylate n-hexyl acrylate ethylene glycol diacrylate 2-hydroxy-2-methyl-1-phenyl-propan-1-one. 
   In COMPOSITION 1, isobornyl acrylate comprises approximately 55% of the composition, n-hexyl acrylate comprises approximately 27%, ethylene glycol diacrylate comprises approximately 15% and the initiator 2-hydroxy-2-methyl-1-phenyl-propan-1-one comprises approximately 3%. The initiator is sold under the trade name DAROCUR® 1173 by CIBA® of Tarrytown, N.Y. The above-identified composition also includes stabilizers that are well known in the chemical art to increase the operational life of the composition. 
   Release properties of COMPOSITION 1 may be improved by including a surfactant. For purposes of this invention a surfactant is defined as any molecule, one tail of which is hydrophobic. Surfactants may be either fluorine containing, e.g., include a fluorine chain, or may not include any fluorine in the surfactant molecule structure. An exemplary surfactant is available under the trade name ZONYL® FSO-100 from DUPONT that has a general structure of R 1 R 2  where R 1 =F(CF 2 CF 2 ) Y , with y being in a range of 1 to 7, inclusive and R 2 =CH 2 CH 2 O(CH 2 CH 2 O) X H, where X is in a range of 0 to 15, inclusive. This provides material  40  with the following composition: 
   COMPOSITION 2 
   isobornyl acrylate n-hexyl acrylate ethylene glycol diacrylate 2-hydroxy-2-methyl-1-phenyl-propan-1-one R f CH 2 CH 2 O(CH 2 CH 2 O) X H, 
   The ZONYL® FSO-100 additive comprises less than 1% of the composition, with the relative amounts of the remaining components being as discussed above with respect to COMPOSITION 1. However, the percentage of ZONYL® FSO-100 may be greater than 1%. 
   Planarization layer  24  may be formed from a silicon-containing material that is suitable for deposition upon patterned layer  16  employing spin-coating technique. Exemplary compositions from which to form planarization layer  24  are as follows: 
   COMPOSITION 3 
   hydroxyl-functional polysiloxane hexamethoxymethylmelamine toluenesulfonic acid methyl amyl ketone 
   COMPOSITION 4 
   hydroxyl-functional polysiloxane hexamethoxymethylmelamine gamma-glycidoxypropyltrimethoxysilane toluenesulfonic acid methyl amyl ketone 
   In COMPOSITION 3, hydroxyl-functional polysiloxane comprises approximately 4% of the composition, hexamethoxymethylmelamine comprises approximately 0.95%, toluenesulfonic acid comprises approximately 0.05% and methyl amyl ketone comprises approximately 95%. In COMPOSITION 4, hydroxyl-functional polysiloxane comprises approximately 4% of the composition, hexamethoxymethylmelamine comprises approximately 0.7%, gamma-glycidoxypropyltrimethoxysilane comprises approximately 0.25%, toluenesulfonic acid comprises approximately 0.05%, and methyl amyl ketone comprises approximately 95%. 
   Both COMPOSITIONS 3 and 4 are made up of at least 4% of the silicone resin. Upon curing, however, the quantity of silicon present in conformal layer  58  is at least 5% by weight and typically in a range of 20% or greater. Specifically, the quantity and composition of the solvent present in COMPOSITIONS 3 and 4 is selected so that a substantial portion of the solvent evaporates during spin-coating application of the COMPOSITION 3 or 4 on solidified imprinting layer  134 . In the present exemplary silicon-containing material, approximately 90% of the solvent evaporates during spin-coating. Upon exposing the silicon-containing material to thermal energy, the remaining 10% of the solvent evaporates, leaving conformal layer  58  with approximately 20% silicon by weight. 
   Referring to  FIGS. 1 and 2 , planarization layer  24  includes first and second opposed sides. First side  26  faces patterned layer  16  and has a profile complementary to the profile of patterned layer  16 . Second side  28  faces away from patterned layer  16 . As shown in  FIG. 2 , second side  28  has a substantially normalized profile. To provide second side  28  with a substantially normalized profile, distances k 1 , k 3 , k 5 , k 7 , k 9 , and k 11  between protrusions  18  and second side  28  are substantially the same and the distances k 2 , k 4 , k 6 , k 8 , and k 10  between recessions  20  and second side  28  are substantially the same. One manner in which to provide second side  28  with a normalized profile is to contact planarization layer  24  with a planarizing mold (not shown) having a smooth, if not planar, surface. Planarization layer  24  is exposed to actinic energy to polymerize and, therefore, to solidify the same. Exemplary actinic energy includes ultraviolet, thermal, electromagnetic, visible light, heat, and the like. The selection of actinic energy depends on the materials from which planarization layer  24  is formed. After solidification of planarization layer, planarizing mold (not shown) is separated therefrom. To ensure that planarization layer  24  does not adhere to the planarizing mold (not shown), a low surface energy coating, such as a diamond-like layer, may be deposited upon the planarizing mold (not shown) or the planarization mold (not shown) may be formed from a material having a low surface energy, e.g., diamond. Alternatively, release properties of planarization layer  24  may be improved by including in the material from which the same is fabricated the aforementioned surfactant. The surfactant provides the desired release properties to reduce adherence of planarization layer  24  to the planarizing mold (not shown). It should be understood that the surfactant may be used in conjunction with, or in lieu of, the low surface energy coating that may be applied to the planarizing mold (not shown). 
   Referring to  FIGS. 2 and 3 , multi-layered structure  110  is subjected to an isotropic or anisotropic etch to remove portions of planarization layer  24  to provide multi-layered structure  110  with a crown surface  30  of etched structure  111 . Crown surface  30  is defined by an exposed surface  32  of each of protrusions  18  and surface  34  of areas  35  of planarization layer  24  that remain after certain etch processes. Surfaces  34  have a width ‘w 1 ’. 
   Referring to  FIGS. 3 and 4 , etched structure  111  is subjected to an anisotropic etch. The etch chemistry of the anisotropic etch is selected to maximize etching of protrusions  18  and the segments of patterned layer  16  in superimposition therewith, while minimizing etching of the areas  35 . As a result, regions  36  of substrate  12  in superimposition with protrusions  18  are exposed forming a multi-layered structure  210 . Multi-layered structure  210  comprises protrusions  38 , each of which has an upper region  31  and a nadir region  33 . Upper region  31  is fabricated from portions of areas  35  that remain. Nadir regions  33  comprise patterned layer  16  and primer layer  14  in superimposition with areas  35 . Protrusions  38  have a width ‘w 2 ’. Ideally, width ‘w 2 ’ is substantially the same as width ‘w 1 ’ of portions  34 . 
   Referring to  FIGS. 4 and 5 , obtaining ideal dimensions of widths w 1  and w 2  is often problematic. For example, it has often been found that upper region  131  has a width ‘w 3 ’ that differs from the width ‘w 4 ’ of nadir region  133 . As shown in  FIG. 5 , width ‘w 3 ’ is greater than width ‘w 4 ,’ however; width ‘w 3 ’ may be smaller than width ‘w 4 ’. The variation of width ‘w 3 ’ as compared to width ‘w 4 ’ may be as a result of subjecting crown surface  30 , shown in  FIG. 3 , to the aforementioned anisotropic etch. The difference in width may be due to any one or more of several factors, including swelling of upper region  131  in response to the etch chemistry employed to form protrusions  138 . Alternatively, or in addition to the aforementioned swelling, undercutting, and/or sputtering of nadir region  133  may occur during formation of protrusions  138 . Nonetheless, it is desired to have width ‘w 3 ’ be substantially the same as width ‘w 4 ,’ and thus, width ‘w 3 ’ substantially the same as width ‘w 1 ,’ shown in  FIG. 3 . To that end, a liner layer is employed to substantially surround exposed sides of the segments of upper region  131 . A liner layer for purposes of the present invention is to be defined as a layer that substantially conforms to the shape of the surface upon which it is disposed and substantially insulates the material from desired processes. Typically, the liner layer is thinner than the layer upon which it is disposed. 
   Referring to  FIG. 6 , a liner layer  40  is formed so that same may be present between patterned layer  16  and planarization layer  24 , forming multi-layered structure  310 . To that end, liner layer  40  is deposited on patterned layer  16 . An exemplary liner layer  40  would have a relative thickness and etch rate differential, compared to patterned layer  16  and/or planarization layer  24 , which enables formation of a desired pattern in primer layer  14  and/or substrate  12 . Typically, the pattern formed therein corresponds to the pattern in patterned layer  16 . In the present example, liner layer  40  has a thickness in a range of 5 nm to 100 nm, inclusive and provides an etch rate differential of no less than 10:1. For example, the etch rate of the liner layer  40 , for a given etch chemistry, may be ten times faster than the etch rate of patterned layer  16  and/or planarization layer  24 . Alternatively, the etch rate of liner layer  40 , for a given etch chemistry, may be ten times slower than the etch rate of patterned layer  16  and/or planarization layer  24 . In this manner, liner layer  40  functions as a hard mask. To that end, exemplary material from which to form liner layer  40  includes silicon dioxide (SiO 2 ), silicon nitride (SiN) and silicon oxynitride (SiON). It is desired that liner layer  40  be formed from processes that would not compromise the structural integrity of patterned layer  16  and/or planarization layer  24 . For example, were patterned layer  16  formed from COMPOSITION 1 or COMPOSITION 2, it would be desired that the process employed to deposit liner layer  40  employs temperatures no greater than 150 degrees Celsius. An exemplary process by which to deposit liner layer  40  formed from SiO 2  is discussed by J. W. Klaus and S. M. George in the article entitled “SiO 2  Chemical Vapor Deposition at Room Temperatures Using SiCl 4  and H 2 O with an NH 3  Catalyst,” Journal of the Electrochemical Society, 147(7) 2658-2664 (2000). An exemplary process by which to deposit liner layer  40  formed from SiN is discussed by G. P. Li and Human Guan in an article entitled “Exploring Low Temperature High Density Inductive Coupled Plasma Chemical Vapor Deposition (HDICPCVD) Dielectric Films for MMICs,” project Report 2002-03 for MICRO Project 02-241, Department of Electrical &amp; Computer Engineering, University of California, Irvine, Calif. After formation of liner layer  40 , planarization layer  24  is disposed atop thereof, as discussed above. 
   Referring to  FIGS. 6 and 7 , multi-layered structure  310  is subjected to an etch process to remove portions of planarization layer  24  to provide a multi-layered structure  410  with a crown surface  230 , wherein the isotropic etch may be an O 2  etch. To that end, multi-layered structure  310  may be deposited in an inductively coupled plasma etch reactor  330 , shown in  FIG. 8 . 
   Referring to  FIG. 8 , reactor  330  includes upper  332  and lower  333  bodies and a cover  334 , which defines a chamber  336 . Cover  334  includes a dielectric window  338  and a coil  340  disposed proximate to dielectric window  338 . Multi-layered structure  310  is supported within chamber  336  by a pedestal  342  or chuck, with dielectric window  338  disposed between structure  310  and coil  340 . Coil  334  typically includes multiple windings and is connected to a radio frequency (RF) power generator  344  through an impedance matching network  346  to provide RF power into chamber  336 . In addition, a bias RF power generator  348  and associated impedance matching circuit  350  is connected to pedestal  342  and used to impose a bias on multi-layer structure  310 . Upper body  332  is composed of dielectric material, typically quartz or ceramic, so as to minimize attenuation of the RF power coupled into chamber  336 . Lower body  333  surrounds pedestal  342  and is formed from electrically conductive material. Lower body  333  coupled to ground functions as the ground for the RF power supplied to pedestal  342 . Also included are cooling channels  352  formed within the lower body  333  and pedestal  342 . A supply of coolant fluid  353  may be pumped through channels  352  to transfer heat away from the interior of chamber  336  and/or pedestal  342  to control the temperature thereof. The temperature of upper body  332  may be controlled by forced air convection/conduction methods. A source  354  of etchant gases is in fluid communication with chamber  336  through gas injection ports  356 . A vacuum pump  358  is in fluid communication with chamber  336  to control the pressure of the atmosphere therein. An exemplary reactor that may be employed is available from Oxford Instruments America, Inc. 130 Baker Avenue, Concord, Mass. 01742 under the product name PLASMALAB 80 PLUS. 
   Referring to  FIGS. 6 ,  7  and  8 , assuming planarization layer  24  is formed from one of COMPOSITIONS 3 and 4, crown surface  230  is formed by exposing multi-layered structure  310  to an etch chemistry that includes oxygen flowed into chamber  336  at a rate of approximately 30 standard cubic centimeters per minute (sccm), CHF 3  flowed into chamber  336  at a rate of approximately 12 sccm. RF power  344  is established to be at 45 Watts at 13.56 MHz, and DC bias  350  is set at −185 volts. Pump  358  establishes a chamber pressure of approximately 20 Torr, and pedestal  342  is maintained at a temperature of approximately −8° C. With these parameters, crown surface  230  is formed in approximately 4 minutes and 40 seconds. Were planarization layer formed from one of COMPOSITIONS 1 and 2, i.e., without any silicon being present, the same etch parameters mentioned above may be employed excepting that CHF 3  is not introduced into chamber  336 . 
   As a result of etching planarization layer  24 , crown surface  230  is defined by exposed regions of liner layer  40  and regions  233  that remain of planarization layer  24  after being exposed to the isotropic O 2  etch. Exposed regions of liner layer  40  include surfaces of first portions  232 , which are in superimposition with protrusions  18  and surfaces of second portions  235 . Second portions  235  are disposed on opposed ends of first portion  232  and in superimposition with recession  20 . Extending between subsets of adjacent second portions  235  are nadir portions  237 . 
   Referring to  FIGS. 7-9 , an anisotropic etch is employed to substantially remove first portion  232  and surfaces of second portions  235 . To that end, multi-layered structure  410  is subjected to an etching environment in chamber  336  by establishing RF power  344  to be approximately 50 Watts at 13.56 MHz, DC bias  350  to be approximately −196 volts, chamber pressure at approximately 30 Torr, with the oxygen flow being terminated. Pedestal  342  is maintained at a temperature of approximately −8° C. With these parameters a multi-layered structure  510  having a surface with a shape of a battlement is formed by exposure of multi-layered structure  410  to this etching environment for approximately 1 minute and ten seconds. The battlement surface is defined by exposed surfaces  342  in regions of patterned layer  16  that were in superimposition with protrusions  18 , as well as surfaces  334  of remaining portions of regions  233  and surfaces  336  of the remaining areas of second portions  235 . An extent of second portions  235 , extending between surface  336  and surface  342  define sidewalls  344 . 
   Referring to  FIGS. 9 and 10 , an anisotropic etch is employed to remove portions of multi-layered structure  510  in superimposition with exposed surfaces  342 , forming multi-layered structure  610 . To that end, multi-layered structure  510  is subjected to an etching environment in chamber  336  by establishing RF power  344  to be approximately 130 Watts at 13.56 MHz, DC bias  350  to be approximately −380 volts, chamber pressure at approximately 6 Torr, with the CHF 3  being replaced by a flow of argon and oxygen. The argon is flowed into chamber  336  at a rate of approximately 30 sccm and the oxygen at a rate of approximately 3 sccm. Pedestal  342  is maintained at a temperature of approximately −8° C. With these parameters a multi-layered structure  610  is formed by exposure of multi-layered structure  510  to this etching environment for approximately 6 minutes. More specifically, portions of primer layer  14  and patterned layer  16  in superimposition with exposed surfaces  342  are removed. As a result, areas  548  of substrate  12  in superimposition with exposed surfaces  342  are exposed, leaving spaced-apart protrusions  650 . Each protrusion  650  includes a sub-portion  614  of planarization layer  14 , a sub-portion  616  of patterned layer  16  and an upper portion  610 . Upper portion  610  includes a sub-portion  612  of sidewall  344 , nadir portion  237  and the remaining portions of region  233  in superimposition with nadir portion  237 . A width ‘w 5 ’ of upper portion  610  is substantially equal to a width ‘w 6 ’ of lower portion. Specifically, sub-portions  612  ensures that width ‘w 5 ’ is substantially the same as width ‘w 6 ,’ as desired. In this manner, width ‘w 5 ’ and, therefore, width ‘w 6 ’ may be substantially the same as width ‘w 1 ,’ shown in  FIG. 3 . 
   In a further embodiment, planarization layer  24  may be formed from a silicon-containing polymerizable material. More specifically, planarization layer  24  may be formed from a silicon-containing spin-on material. Therefore, the aforementioned isotropic etch to remove portions of planarization layer  24  to provide multi-layered structure  410  may be a halogen etch. Also, multi-layered structure  610  may be utilized in a lift-off process. 
   The embodiments of the present invention described above are exemplary. Many changes and modification may be made to the disclosure recited above, while remaining within the scope of the invention. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.