Abstract:
The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor package and the method of making the same, and more particularly to a stacked semiconductor package and the method of making the same. 
         [0003]    2. Description of the Related Art 
         [0004]      FIGS. 1 to 7  are schematic views of each step of the method of making a conventional stacked semiconductor package. First, referring to  FIG. 1 , a first substrate  10  is provided. The first substrate  10  has a first surface  101  and a second surface  102 . Afterward, a first chip  11  is mounted onto the first surface  101  of the first substrate  10 , and is electrically connected to the first substrate  10  via a plurality of first wires  12 . 
         [0005]    In  FIG. 2 , a mold  13  is used to cover the first surface  101  of the first substrate  10 . The mold  13  has a cavity  131  for accommodating the first chip  11  and the first wires  12 . 
         [0006]    As shown in  FIG. 3 , a molding process is performed to encapsulate the first chip  11  and the first wires  12  by injecting a first molding compound  14  into the cavity  131 . Afterward, the mold  13  is removed. 
         [0007]    In  FIG. 4 , a ball-mounting process is performed to form a plurality of first solder balls  15  on the first surface  101  of the first substrate  10 , which is not covered by the first molding compound  14 . 
         [0008]    In  FIG. 5 , a second package  16  is provided. The second package comprises a second substrate  17 , a second chip  18 , a plurality of second wires  19 , a second molding compound  20  and a plurality of third solder balls  21 . The second substrate  17  has a first surface  171  and a second surface  172 . The second chip  18  is electrically connected to the first surface  171  of the second substrate  17  via the second wires  19 . The third solder balls  21  are disposed on the second surface  172  of the second substrate  17 . 
         [0009]    In  FIG. 6 , the third solder balls  21  are stacked on the first solder balls  15 , and a reflow process is performed to form a plurality of fourth solder balls  22  by melting the third solder balls  21  and the first solder balls  15 . 
         [0010]    In  FIG. 7 , a plurality of second solder balls  23  is formed on the second surface  102  of the first substrate  10  to form a stacked package. 
         [0011]    The conventional stacked package has the following disadvantages. In the above-mentioned molding process, the mold flush occurs easily, that is, the first molding compound  14  easily flush out of the cavity  131 , and enters the space between the mold  13  and the first surface  101  of the first substrate  10 . Therefore, the area for mounting the first solder balls  15  is polluted, causing the failure of the ball-mounting process and defects in the package. Moreover, the rigidity of the first substrate  10  is relatively low. After the third solder balls  171  and the first solder balls  15  are melted to form a plurality of fourth solder balls  22 , a stress is produced on the first substrate  10 . Therefore, the first substrate  10  is pulled so that warpage occurs. 
         [0012]    Therefore, it is necessary to provide an innovative and advanced semiconductor package to solve the above problems. 
       SUMMARY OF THE INVENTION 
       [0013]    The present invention is mainly directed to a method of making a semiconductor package which comprises the following steps: (a) providing a first substrate having a first surface and a second surface; (b) mounting a first chip onto the first surface of the first substrate, the first chip being electrically connected to the first substrate; (c) forming a plurality of conductive elements on the first surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities corresponding to top ends of the conductive elements; and (e) forming a first molding compound for encapsulating the first surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. 
         [0014]    The present invention is further directed to a semiconductor package, which comprises a first substrate, a first chip, a second substrate, a second chip, a plurality of fourth solder balls and a first molding compound. The first substrate has a first surface and a second surface. The first chip is mounted onto the first surface of the first substrate, and is electrically connected to the first substrate. The second substrate has a first surface and a second surface. The second chip is mounted onto the first surface of the second substrate, and is electrically connected to the second substrate. The fourth solder balls connect the second surface of the second substrate and the first surface of the first substrate. The first molding compound encapsulates the first surface of the first substrate, the chip and parts of the fourth solder balls, and the height of the first molding compound is smaller than the height of each of the fourth solder balls. Thus, in the present invention, the first molding compound encapsulates the entire first surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIGS. 1 to 7  are schematic views of each step of the method of making the conventional stacked semiconductor package; 
           [0016]      FIGS. 8 to 13  are schematic views of each step of the method of making a semiconductor package according to the first embodiment of the present invention; and 
           [0017]      FIGS. 14 to 19  are schematic views of each step of the method of making a semiconductor package according to the second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]      FIGS. 8 to 13  are schematic views of each step of the method of making a semiconductor package according to the first embodiment of the present invention. In  FIG. 8 , a first substrate  30  having a first surface  301  and a second surface  302  is provided. Afterward, a first chip  31  is mounted onto the first surface  301  of the first substrate  30 , and is electrically connected to the first substrate  30 . In the embodiment, the first chip  31  is electrically connected to the first substrate  30  via a plurality of first wires  32 . Afterward, a plurality of conductive elements  33  is formed on the first surface  301  of the first substrate  30 . In the embodiment, the conductive elements  33  are a plurality of first solder balls, which are spherical. 
         [0019]    In  FIG. 9 , a mold  34  is used to cover the conductive elements  33 . The mold  34  has a plurality of cavities  341 . Each of the cavities  341  accommodates top ends of each of the conductive elements  33 , and top ends of the conductive elements  33  contact with the cavities  341 . 
         [0020]    In  FIG. 10 , a molding process is performed to encapsulate the first surface  301  of the first substrate  30 , the first chip  31 , the first wires  32  and parts of the conductive elements  33  by forming a first molding compound  35 , wherein the height of the first molding compound  35  is smaller than the height of each of the conductive elements  33 , so as to expose top ends of the conductive elements  33  out of the first molding compound  35 . After the first molding compound  35  is solidified, the mold  34  is removed to form a first semiconductor package  36 . 
         [0021]    Also in  FIG. 10 , the first semiconductor package  36  comprises a first substrate  30 , a first chip  31 , a plurality of conductive elements  33  and a first molding compound  35 . The first substrate  30  has a first surface  301  and a second surface  302 . The first chip  31  is mounted onto the first surface  301  of the first substrate  30 , and is electrically connected to the first substrate  30 . In the embodiment, the first chip  31  is electrically connected to the first substrate  30  via a plurality of first wires  32 . 
         [0022]    The conductive elements  33  are disposed on the first surface  301  of the first substrate  30 . In the embodiment, the conductive elements  33  are a plurality of first solder balls. The first molding compound  35  encapsulates the first surface  301  of the first substrate  30 , the first chip  31  and parts of the conductive elements  33 , wherein the height of the first molding compound  35  is smaller than the height of each of the conductive elements  33 , that is, top ends of the conductive elements  33  protrude out of the first molding compound  35 . 
         [0023]    In the semiconductor package  36 , the first molding compound  35  encapsulates the entire first surface  301  of the first substrate  30 , so that the mold flush of the first molding compound  35  will not occur, and the rigidity of the first substrate  30  is increased. The semiconductor package  36  may further perform the following processes. 
         [0024]    In  FIG. 11 , a plurality of second solder balls  37  is formed on the second surface  302  of the first substrate  30 . 
         [0025]    In  FIG. 12 , a second package  38  is provided. The second package  38  comprises a second substrate  39 , a second chip  40 , a plurality of third solder balls  42  and a second molding compound  43 . The second substrate  39  has a first surface  391  and a second surface  392 . The second chip  40  is electrically connected to the first surface  391  of the second substrate  39 . In the embodiment, the second chip  40  is electrically connected to the first surface  391  of the second substrate  39  via a plurality of second wires  41 . The third solder balls  42  are disposed on the second surface  392  of the second substrate  39 . The second molding compound  43  encapsulates the second chip  40 , the first surface  391  of the second substrate  39  and the second wires  41 . 
         [0026]    In  FIG. 13 , the third solder balls  42  are stacked on the conductive elements  33 . Afterward, a reflow process is performed to form a plurality of fourth solder balls  44  by melting the third solder balls  42  and the conductive elements  33 . Thus, a semiconductor package  45  is formed, and the semiconductor package  45  is a stacked semiconductor package. 
         [0027]    In the embodiment, the second solder balls  37  ( FIG. 11 ) are formed first, and the stacking process and the reflow process ( FIGS. 12 and 13 ) are performed later. It is understood that the stacking process and the reflow process may be performed first, and the second solder balls  37  may be formed later on the second surface  302  of the substrate  30 . 
         [0028]    Again in  FIG. 13 , the semiconductor package  45  comprises a first substrate  30 , a first chip  31 , a second substrate  39 , a second chip  40 , a second molding compound  43 , a plurality of fourth solder balls  44  and a first molding compound  35 . The first substrate  30  has a first surface  301  and a second surface  302 . The first chip  31  is mounted onto the first surface  301  of the first substrate  30 , and is electrically connected to the first substrate  30  via a plurality of first wires  32 . The second substrate  39  has a first surface  391  and a second surface  392 . The second chip  40  is mounted onto the first surface  391  of the second substrate  39 , and is electrically connected to the second substrate  39  via a plurality of second wires  41 . The second molding compound  43  encapsulates the second chip  40 , the first surface  391  of the second substrate  39  and the second wires  41 . 
         [0029]    The fourth solder balls  44  connect the second surface  392  of the second substrate  39  and the first surface  301  of the first substrate  30 . The molding compound  36  encapsulates the first surface  301  of the first substrate  30 , the first chip  31 , the first wires  32  and parts of the fourth solder balls  44 , and the height of the molding compound  35  is smaller than the height of each of the fourth solder balls  44 , that is, the fourth solder balls  44  protrude out of the first molding compound  35 . 
         [0030]    Preferably, the semiconductor package  45  further comprises a plurality of second solder balls  37  disposed on the second surface  302  of the first substrate  30 . 
         [0031]      FIGS. 14 to 19  are schematic views of each step of the method of making a semiconductor package according to the second embodiment of the present invention. In  FIG. 14 , a first substrate  50  is provided. The first substrate  50  has a first surface  501  and a second surface  502 . A first chip  51  is mounted onto the first surface  501  of the first substrate  50 , and is electrically connected to the first substrate  50 . In the embodiment, the first chip  51  is electrically connected to the first substrate  50  via a plurality of first wires  52 . Afterward, a plurality of conductive elements  53  is formed on the first surface  501  of the first substrate  50 . In the embodiment, the conductive elements  53  are a plurality of first solder balls, which are spherical. 
         [0032]    In  FIG. 15 , a mold  54  is used to cover the conductive elements  53 . The mold  54  has a plurality of protrusions  541 , and each of the protrusions  541  contacts top ends of each of the conductive elements  53 . 
         [0033]    In  FIG. 16 , a molding process is performed to encapsulate the first surface  501  of the first substrate  50 , the chip  51 , the first wires  52  and parts of the conductive elements  53  by forming a first molding compound  55 , and the height of the first molding compound  55  is greater than the height of each of the conductive elements  53 . The first molding compound  55  has a plurality of cavities  551  to expose top ends of the conductive elements  53 , and the shape of the cavities  551  corresponds to that of the protrusions  541 . After the first molding compound  55  is solidified, the mold  54  is removed to form a first semiconductor package  56 . 
         [0034]    Also in  FIG. 16 , the first semiconductor package  56  comprises a first substrate  50 , a first chip  51 , a plurality of conductive elements  53  and a first molding compound  55 . The first substrate  50  has a first surface  501  and a second surface  502 . The first chip  51  is mounted onto the first surface  501  of the first substrate  50 , and is electrically connected to the first substrate  50 . In the embodiment, the first chip  51  is electrically connected to the first substrate  50  via a plurality of first wires  52 . 
         [0035]    The conductive elements  53  are disposed on the first surface  501  of the first substrate  50 . In the embodiment, the conductive elements  53  are a plurality of first solder balls. The first molding compound  55  encapsulates the first surface  501  of the first substrate  50 , the first chip  51  and parts of the conductive elements  53 , wherein the height of the first molding compound  55  is greater than the height of each of the conductive elements  53 , and the first molding compound  55  has a plurality of cavities  551  to expose top ends of the conductive elements  53 . 
         [0036]    The following processes may be further performed for the first semiconductor package  56 . 
         [0037]    In  FIG. 17 , a plurality of second solder balls  57  is formed on the second surface  502  of the first substrate  50 . 
         [0038]    In  FIG. 18 , a second package  58  is provided. The second package  58  comprises a second substrate  59 , a second chip  60 , a plurality of third solder balls  62  and a second molding compound  63 . The second substrate  59  has a first surface  591  and a second surface  592 . The second chip  60  is electrically connected to the first surface  591  of the second substrate  59 . The second chip  60  is electrically connected to the first surface  591  of the second substrate  59  via a plurality of second wires  61 . The third solder balls  62  are disposed on the second surface  592  of the second substrate  59 . The second molding compound  63  encapsulates the second chip  60 , the first surface  591  of the second substrate  59  and the second wires  61 . 
         [0039]    Also in  FIG. 19 , the third solder balls  62  are stacked on the conductive elements  53 . Afterward, a reflow process is performed to form a plurality of fourth solder balls  64  by melting the third solder balls  62  and the conductive elements  53 . Thus, a semiconductor package  65  is formed, and the semiconductor package  65  is a stacked semiconductor package. 
         [0040]    In the embodiment, the second solder balls  57  ( FIG. 17 ) are formed first, and the stacking process and the reflow process ( FIGS. 18 and 19 ) are performed later. It is understood that the stacking process and the reflow process may be performed first, and the second solder balls  57  may be formed later on the second surface  502  of the first substrate  50 . 
         [0041]    In  FIG. 19 , the semiconductor package  65  comprises a first substrate  50 , a first chip  51 , a second substrate  59 , a second chip  60 , a second molding compound  63 , a plurality of fourth solder balls  64  and a first molding compound  55 . The first substrate  50  has a first surface  501  and a second surface  502 . The first chip  51  is mounted onto the first surface  501  of the first substrate  50 , and is electrically connected to the first substrate  50  via a plurality of first wires  52 . The second substrate  59  has a first surface  591  and a second surface  592 . The second chip  60  is mounted onto the first surface  591  of the second substrate  59 , and is electrically connected to the second substrate  59  via a plurality of second wires  61 . The second molding compound  63  encapsulates the second chip  60 , the first surface  591  of the second substrate  59  and the second wires  61 . 
         [0042]    The fourth solder balls  64  connect the second surface  592  of the second substrate  59  with the first surface  501  of the first substrate  50 . The first molding compound  55  encapsulates the first surface  501  of the first substrate  50 , the chip  51 , the first wires  52  and parts of the fourth solder balls  64 , wherein the height of the first molding compound  55  is smaller than the height of each of the fourth solder balls  64 , that is, the fourth solder balls  64  protrude out of the first molding compound  55 . 
         [0043]    Preferably, the semiconductor package  65  further comprises a plurality of second solder balls  57  disposed on the second surface  502  of the first substrate  50 . 
         [0044]    While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined in the appended claims.