Abstract:
A semiconductor logic circuit utilizing level shifting of input transistors away from a reference voltage level but shifting the output toward the reference voltage level to increase noise margin. The input signals may switch both the input transistors and the output transistors.

Description:
The present invention relates to semiconductor logic circuits, and more particularly to such circuits using diodes to provide integral level shifting. 
     BACKGROUND OF THE INVENTION 
     A problem which arises in the development of semiconductor digital integrated circuits, relates to the noise margin of the individual gates in such a circuit. As more gates are added to such circuits the cumulative noise of the gates may rapidly exceed the available noise margin. This problem is compounded when a circuit must be able to operate over a wide temperature range, such as the military temperature range of -55° C. to +125° C. Problems related to such limited noise margins have been largely overcome in the area of silicon integrated circuits, but still are significant in circuits based on gallium arsenide or other more recently developed semiconductor materials. Thus a semiconductor logic family having improved noise margins would be very useful in allowing such newer semiconductor materials extended temperature operating range, and permitting a higher level of integration. 
     SUMMARY OF THE INVENTION 
     The present invention utilizes level shifting means to shift the switchpoint of the switching transistors in a logic gate further from ground potential. By thus moving the switchpoint of the transistors away from ground potential a higher voltage is required to switch the transistors from the on state to the off state or vice versa. Thus there is a larger range between the system low voltage level, or logic &#34;0&#34; and the switchpoint above which the signal will be interpreted as the system high voltage level or logic &#34;1&#34;. In the preferred embodiment the level shifting means includes Schottky diodes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a two input NOR gate according to the invention; and 
     FIG. 2 is a drawing of a two input NOR gate including an output buffer state for a stronger output signal. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 illustrates a two input NOR gate according to the invention. The circuit of FIG. 1 includes a depletion mode field effect transistor 11 (FET) which has a drain terminal 11A which is designed to be electrically connected to the system V DD , a gate terminal 11B, and a source terminal 11C. Gate terminal 11B and source terminal 11C are electrically connected to one another, so that transistor 11 will function as a current source. Source 11C of transistor 11 is electrically connected to drain 12A of transistor 12 and 13A of transistor 13. Input signals to the gate are provided to gates 12B and 13B of transistors 12 and 13 respectively. Sources 12C and 13C of transistors 12 and 13 respectively are electrically connected to one another and to level shifting diode 14. Level shifting diode 14 is in turn electrically connected to a source of electrical ground potential. 
     Source 11C of transistor 11 is further electrically connected to level shifting diode 15. Level shifting diode 15 is electrically connected to the system output and to drain 16A of transistor 16. Gate 16B and source 16C of transistor 16 are electrically connected to one another and to a source of electrical ground potential. 
     The function of diode 14 in the circuit of FIG. 1 is to shift the switching level of transistors 12 and 13 to a voltage farther from ground potential than would be the case if diode 14 were not present. In so doing the switchpoint of the transistors, and hence the voltage level which is detected as a system high voltage signal is moved away from the nominal system low voltage level. Thus a greater noise margin is provided, i.e. the system is able to tolerate greater electrical noise while still functioning properly. 
     Level shifting diode 15 and transistor 16 provide output level shifting to insure that the output low voltage remains at or near ground potential, in order to allow subsequent gates to correctly interpret the output signals from the gate of FIG. 1. 
     FIG. 2 shows a second gate according to the invention. In the gate of FIG. 2, however, an output stage has been added to provide greater output drive. This acts as an amplifier to allow the circuit to drive more subsequent gates than would be possible with the circuit of FIG. 1, or to operate better if the system is to drive a transmission line having a larger capacitance. In the circuit of FIG. 2 transistor 11 functions as did transistor 11 of FIG. 1. Transistors 12 and 13 are connected similarly to the corresponding transistors of FIG. 1 except that level shifting diode 15&#39; is electrically connected to source region 17C of transistor 17 rather than source region 11A of transistor 11. 
     The output stage further includes diode 18 and transistor 19. These devices shift the input signal level to a transistor 16&#39; such that it is switched at the same voltage as transistor 13 for push-pull operation. 
     Gate region 12B of transistor 12 is further electrically connected to diode 20 which is in turn electrically connected to drain region 21A of transistor 21. Gate region 21B of transistor 21 is electrically connected to source region 21C which is electrically connected to a source of electrical ground. Those skilled in the art will readily perceive that diode 20 and transistor 21 provide a function for inputs to transistor 22 similar to the function provided by diode 18, and transistor 19 for inputs to transistor 16&#39;. Diodes 18 and 20 are electrically connected to gate regions 16&#39;B and 22B of transistors 16&#39; and 22 respectively. Source regions 19C and 22C of transistors 19 and 22 are electrically connected to a source of electrical ground potential while drain regions 16&#39;A and 22A of transistors 19 and 22 respectively are electrically connected to one another and to the gate output. The circuit of FIG. 2 will provide similar advantages to that of FIG. 1 with the additional advantage of providing an enhanced output signal. 
     In the preferred embodiments of the invention all FETs in the circuit are metal semiconductor field effect transistors (MESFETs). Those skilled in the art will readily perceive, however, that the invention is not limited to MESFETs. Other type of transistors, such as insulated gate field effect transistors could be utilized. Those skilled in the art will further perceive that other output stages could be effectively utilized, depending upon the requirements in a particular application.