Abstract:
A current drive circuit according to the present invention includes: a first current source and a second current source (I 101 , I 102 ); a first current mirror (CM 103 ) for generating a first mirror current of a current (I 2 ) generated by the second current source (I 102 ); a second current mirror (CM 106 ) for generating a second mirror current of the current (I 2 ) generated by the second current source (I 102 ); and a third current mirror (CM 101 ) for generating a mirror current (I OUT1 ) of a current which is generated by the first current source (I 101 ) and which is corrected according to a difference between the first mirror current and the second mirror current, to supply the current to a load (LD 101 ).

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a current drive circuit. For example, the present invention relates to a current drive circuit suitable for driving a current driving element such as a laser diode that is mounted in an optical disk device and is required to be supplied with a stable drive current. 
         [0003]    2. Description of Related Art 
         [0004]    In an optical information processor, a laser diode (hereinafter, referred to also as “LD”) is widely used as a light source. For example, a laser diode is used as a light source for an optical head in an optical disk device. The laser diode is driven by a current drive circuit. Accordingly, it is necessary to supply a stable drive current to the laser diode regardless of a power supply voltage variation. As a current drive circuit of this type, a current-mirror type circuit is widely employed. 
         [0005]    In general, a ratio of the magnitude of currents flowing through two metal-oxide-semiconductor field-effect transistors (MOSFETs) constituting a current mirror, that is, a mirror ratio is determined based on a ratio of the size (channel width W/channel length L) of two MOSFETs. However, it is known that a current flowing through the MOSFETs is affected by a source-drain voltage V DS  due to a channel length modulation effect. Accordingly, if the effect is not taken into account, there is a fear that, even when the W/L ratio is correctly set, a stable drive current cannot be obtained because of the power supply voltage variation due to noise or the like. 
         [0006]    Japanese Unexamined Patent Application Publication No. 2005-101154 and Japanese Unexamined Patent Application Publication No. 2006-114895, which is filed as a divisional application thereof, each discloses a circuit configuration for stabilizing the drive current against the power supply voltage variation.  FIG. 4  is a circuit diagram shown in FIG. 1 of Japanese Unexamined Patent Application Publication No. 2005-101154. 
         [0007]    The circuit shown in  FIG. 4  includes a laser diode LD 1 , an output current setting current source IS, an LD output terminal T 1 , an output MOSFET M 1 , a MOSFET M 2 , an output switch SW 1 , a MOSFET M 3 , a MOSFET M 4 , a first dummy LD LD 2 , a MOSFET M 5 , a MOSFET M 6 , an output switch for the first dummy LD SW 2 , a MOSFET M 7 , a MOSFET M 8 , a second dummy LD LD 3 , a MOSFET M 9 , a MOSFET M 10 , a MOSFET MN 1 , a MOSFET M 12 , a MOSFET M 13 , a MOSFET M 14 , and a correction amount detection amplifier AMP. 
         [0008]    In this case, the MOSFET M 1  and the MOSFET M 2  constitute a current mirror CM 1 . 
         [0009]    The MOSFET M 5  and the MOSFET M 6  constitute a current mirror CM 2 . 
         [0010]    The MOSFET M 9 , the MOSFET M 10 , the MOSFET MN 1 , and the MOSFET M 12  constitute a cascode current mirror CM 3 . 
         [0011]    The MOSFET M 14  and the MOSFET M 13  constitute a current mirror CM 4 . 
         [0012]    The MOSFET M 14  and the MOSFET M 8  constitute a current mirror CM 5 . 
         [0013]    Further, the MOSFET M 14  and the MOSFET M 4  constitute a current mirror CM 6 . 
         [0014]    Next, a description is given of operations of the circuit shown in  FIG. 4 . 
         [0015]    First, a current I 1  proportional to a desired current I OUT1 , which is caused to flow through the laser diode LD 1 , flows from the output current setting current source IS. When the output ON/OFF switch SW 1  is turned on, the current is supplied as the current I OUT1  to the laser diode LD 1  via the current mirror CM 6 , the current mirror CM 1 , and the LD output terminal T 1 , whereby the laser diode LD 1  emits light. In this case, it is assumed that no current flows through the MOSFET M 3 . 
         [0016]    Assuming that the power supply voltage varies due to an effect of noise or the like, a terminal voltage V LD  of the laser diode LD 1  is substantially constant, while a voltage V of the power supply VDD varies. In other words, a voltage V DS1  applied between a drain and a source of the MOSFET M 1  varies. As a result, owing to the channel length modulation effect of the MOSFET, a current flowing through the MOSFET M 1  fluctuates, which causes a problem. In this case, it is necessary to supply a large current to the current mirror CM 1 , which is formed of the MOSFET M 1  and the MOSFET M 2 , in a state where a sufficient amount of the voltage V DS1  cannot be supplied. As a result, the current mirror CM 1  cannot be implemented with a cascode configuration. 
         [0017]    Next, a description is given of a circuit operation for suppressing the current fluctuation. 
         [0018]    First, a current proportional to the current I 1 , which flows through the MOSFET M 14 , flows through the MOSFET M 13  that constitutes the current mirror CM 4  with the MOSFET M 14 . The current is supplied as a current I 3  to the second dummy LD LD 3  via the cascode current mirror CM 3 . 
         [0019]    On the other hand, the current proportional to the current I 1 , which flows through the MOSFET M 14 , also flows through the MOSFET M 8  that constitutes the current mirror CM 5  with the MOSFET M 14 . The current is supplied as a current I 4  to the first dummy LD LD 2  via the switch SW 2 , which is constantly turned on, and the current mirror CM 2 . 
         [0020]    In this case, it is assumed that the first dummy LD LD 2  and the second dummy LD LD 3  have the same characteristics. In a case where the power supply voltage is constant at the voltage V, when the current flowing through the current mirrors CM 2 , CM 3 , CM 4 , and CM 5  and the MOSFET M 7  is set so as to satisfy I 3 =I 4 , an anode voltage of the first dummy LD LD 2  becomes equal to an anode voltage of the second dummy LD LD 3 . As a result, a potential difference between an inverting input terminal and a non-inverting input terminal of the correction amount detection amplifier AMP is eliminated. 
         [0021]    Consideration is made of a case where the power supply voltage varies under the set conditions, for example, a case where the voltage of the power supply VDD increases. The current I 3  supplied to the second dummy LD LD 3  is substantially constant because the current mirror CM 3  has a cascode configuration. On the other hand, since the current mirror CM 2  is not implemented with the cascode configuration and a voltage V D33  applied between a drain and a source of the MOSFET M 5  is high, the current I 4  supplied to the first dummy LD LD 2  has a large current value owing to the channel length modulation effect, whereby I 3 &lt;I 4 . 
         [0022]    Accordingly, the anode voltage of the first dummy LD LD 2  becomes higher than the anode voltage of the second dummy LD LD 3 , and an output voltage of the correction amount detection amplifier AMP decreases. Thus, the current flowing through the MOSFET M 7  becomes smaller, with the result that I 3 =I 4 . Therefore, the current flowing through the first dummy LD LD 2  remains constant regardless of power supply variations. 
         [0023]    In contrast, when the power supply voltage decreases, the anode voltage of the first dummy LD LD 2  becomes lower than the anode voltage of the second dummy LD LD 3 , and the output voltage of the correction amount detection amplifier AMP increases. Thus, the current flowing through the MOSFET M 7  becomes larger, with the result that I 3 =I 4 . Accordingly, the current flowing through the first dummy LD LD 2  remains constant regardless of power supply variations. 
         [0024]    A correction current flowing through the MOSFET M 7  is also caused to flow through the MOSFET M 3  in a similar manner, whereby the current flowing through the laser diode LD 1  can be set constant regardless of power supply variations. 
         [0025]    However, in the circuit configuration disclosed in each of Japanese Unexamined Patent Application Publication No. 2005-101154 and Japanese Unexamined Patent Application Publication No. 2006-114895, the correction amount detection amplifier, the dummy laser diode, and the like are necessary. Accordingly, there arises a problem in that the circuit is complicated and the chip size is increased, which leads to an increase in costs. 
       SUMMARY 
       [0026]    In one embodiment of the present invention, there is provided a current drive circuit including: a first current source and a second current source; a first current mirror to generate a first mirror current of a current generated by the second current source; a second current mirror to generate a second mirror current of the current generated by the second current source; and a third current mirror to generate a mirror current of a current which is generated by the first current source and which is corrected according to a difference between the first mirror current and the second mirror current, to supply the mirror current to a load. 
         [0027]    According to the present invention, it is possible to provide a current drive circuit capable of suppressing current fluctuation due to power supply voltage variation, with a simpler circuit configuration than that of the prior art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0029]      FIG. 1  is a circuit diagram showing a semiconductor circuit according to a first embodiment of the present invention; 
           [0030]      FIG. 2  is a circuit diagram showing a semiconductor circuit according to a second embodiment of the present invention; 
           [0031]      FIG. 3  is a circuit diagram showing a semiconductor circuit according to a third embodiment of the present invention; and 
           [0032]      FIG. 4  is a circuit diagram showing a semiconductor circuit of a related art. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0033]    The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
         [0034]    Hereinafter, embodiments of the present invention will be described. Note that the present invention is not limited to the embodiments described below. To make the description clear, the following description and drawings are simplified as appropriate. 
       First Embodiment 
       [0035]    Hereinafter, embodiments of the present invention will be described with reference to the drawings.  FIG. 1  shows a circuit diagram of a current drive circuit according to a first embodiment of the present invention. As shown in  FIG. 1 , the current drive circuit according to the first embodiment includes a laser diode LD 101 , an output current setting current source I 101 , an LD output terminal T 101 , an output MOSFET M 101 , a MOSFET M 102 , an output ON/OFF switch SW 101 , and a correction circuit B 101 . 
         [0036]    The correction circuit B 101  includes a current source for setting correction current I 102 , a MOSFET M 103 , a MOSFET M 104 , a MOSFET M 105 , a MOSFET M 106 , a MOSFET M 107 , a MOSFET M 108 , a MOSFET M 109 , a MOSFET M 110 , a MOSFET M 111 , a MOSFET M 112 , a MOSFET M 113 , a MOSFET M 114 , a MOSFET M 115 , a MOSFET M 116 , a MOSFET M 117 , a MOSFET M 118 , a MOSFET M 119 , and a MOSFET M 120 . 
         [0037]    The MOSFET M 101 , which is a P-channel MOSFET, has a source connected to a power supply VDD and a drain connected to one end of the laser diode LD 101  via the LD output terminal T 101 . The other end of the laser diode LD 101  is connected to a ground GND. 
         [0038]    The MOSFET M 102 , which is a P-channel MOSFET, has a source connected to the power supply VDD and a drain connected to one end of the output current setting current source I 101  via the output ON/OFF switch SW 101 . The other end of the output current setting current source I 101  is connected to the ground GND. Further, a gate and the drain of the MOSFET M 102  are connected together. 
         [0039]    In this case, a gate of the MOSFET M 101  and the gate of the MOSFET M 102  are connected together. In other words, the MOSFET M 101  and the MOSFET M 102  constitute a current mirror CM 101 . As described above, it is necessary to supply a large current to the current mirror CM 101  in a state where a sufficient amount of the voltage V DS1  cannot be supplied. As a result, the current mirror CM 101  cannot be implemented with a cascode configuration. 
         [0040]    Both the MOSFET M 103  and the MOSFET M 104  are N-channel MOSFETs. The MOSFET M 103  has a source connected to the ground GND, and a drain connected to a source of the MOSFET M 104 . That is, both the MOSFETs are connected in series. 
         [0041]    Both the MOSFET M 105  and the MOSFET M 106  are N-channel MOSFETs. The MOSFET M 105  has a source connected to the ground GND, and a drain connected to a source of the MOSFET M 106 . That is, both the MOSFETs are connected in series. Further, a gate and the drain of the MOSFET M 105  are connected together, and a gate and a drain of the MOSFET M 106  are connected together. 
         [0042]    In this case, a gate of the MOSFET M 103  is connected to the gate of the MOSFET M 105 . Further, a gate of the MOSFET M 104  is connected to a gate of the MOSFET M 106 . That is, the MOSFET M 103 , the MOSFET M 104 , the MOSFET M 105 , and the MOSFET M 106  constitute a cascode current mirror CM 102 . 
         [0043]    Both the MOSFET M 107  and the MOSFET M 108  are P-channel MOSFETs. The MOSFET M 107  has a source connected to the power supply VDD, and a drain connected to a source of the MOSFET M 108 . That is, both the MOSFETs are connected in series. A drain of the MOSFET M 108  and the drain of the MOSFET M 106  are connected in series. 
         [0044]    Both the MOSFET M 109  and the MOSFET M 110  are P-channel MOSFETs. The MOSFET M 109  has a source connected to the power supply VDD, and a drain connected to a source of the MOSFET M 110 . That is, both the MOSFETs are connected in series. A drain of the MOSFET M 110  and a drain of the MOSFET M 104  are connected in series. Further, a node between the MOSFET M 110  and the MOSFET M 104  is connected to a node between the switch SW 101  and the current source I 101 . As a result, a correction current generated by the correction circuit B 101  is supplied to the current drive circuit. 
         [0045]    Both the MOSFET M 111  and the MOSFET M 112  are P-channel MOSFETs. The MOSFET M 111  has a source connected to the power supply VDD, and a drain connected to a source of the MOSFET M 112 . That is, both the MOSFETs are connected in series. Further, a gate and the drain of the MOSFET M 111  are connected together, and a gate and a drain of the MOSFET M 112  are connected together. 
         [0046]    In this case, a gate of the MOSFET M 109  is connected to the gate of the MOSFET M 111 . Further, a gate of the MOSFET M 110  is connected to the gate of the MOSFET M 112 . That is, the MOSFET M 109 , the MOSFET M 110 , the MOSFET M 111 , and the MOSFET M 112  constitute a cascode current mirror CM 104 . 
         [0047]    Both the MOSFET M 113  and the MOSFET M 114  are N-channel MOSFETs. The MOSFET M 113  has a source connected to the ground GND, and a drain connected to a source of the MOSFET M 114 . That is, both the MOSFETs are connected in series. A drain of the MOSFET M 114  and the drain of the MOSFET M 112  are connected in series. 
         [0048]    Both the MOSFET M 115  and the MOSFET M 116  are N-channel MOSFETs. The MOSFET M 115  has a source connected to the ground GND, and a drain connected to a source of the MOSFET M 116 . That is, both the MOSFETs are connected in series. Further, a gate and the drain of the MOSFET M 115  are connected together, and a gate and a drain of the MOSFET M 116  are connected together. 
         [0049]    In this case, a gate of the MOSFET M 113  is connected to the gate of the MOSFET M 115 . Further, a gate of the MOSFET M 114  is connected to the gate of the MOSFET M 116 . That is, the MOSFET M 113 , the MOSFET M 114 , the MOSFET M 115 , and the MOSFET M 116  constitute a cascode current mirror CM 105 . 
         [0050]    Both the MOSFET M 117  and the MOSFET M 118  are P-channel MOSFETs. The MOSFET M 117  has a source connected to the power supply VDD, and a drain connected to a source of the MOSFET M 118 . That is, both the MOSFETs are connected in series. A gate of the MOSFET M 118  is applied with a constant reference voltage V REF . Further, a drain of the MOSFET M 118  and the drain of the MOSFET M 116  are connected in series. 
         [0051]    Both the MOSFET M 119  and the MOSFET M 120  are P-channel MOSFETs. The MOSFET M 119  has a source connected to power supply VDD, and a drain connected to a source of the MOSFET M 120 . That is, both the MOSFETs are connected in series. A drain of the MOSFET M 120  is connected to one end of the current source I 102 . The other end of the current source I 102  is connected to the ground GND. Further, a gate and the drain of the MOSFET M 119  are connected together, and a gate and the drain of the MOSFET M 120  are connected together. 
         [0052]    In this case, a gate of the MOSFET M 107  is connected to the gate of the MOSFET M 119 . Further, a gate of the MOSFET M 108  is connected to the gate of the MOSFET M 120 . That is, the MOSFET M 107 , the MOSFET M 108 , the MOSFET M 119 , and the MOSFET M 120  constitute a cascode current mirror CM 103 . 
         [0053]    Further, a gate of the MOSFET M 117  is connected to the gate of the MOSFET M 119 . Both the MOSFETs constitute a current mirror CM 106 . 
         [0054]    Next, a description is given of a method of operating the current drive circuit shown in  FIG. 1 . Note that the description is made assuming that a mirror ratio of each of the current mirrors CM 101  to CM 106  is set to 1:1. First, a description is given of an operation of the current drive circuit in a case where the correction circuit B 101  is not provided. 
         [0055]    A current I 1  proportional to a desired current I OUT1  that is caused to flow through the laser diode LD 101  flows from the output current setting current source I 101 . When the output ON/OFF switch SW 101  is turned on, the current is supplied as the current I OUT1  to the laser diode LD 101  via the current mirror CM 101  and the LD output terminal T 101 , whereby the laser diode LD 101  emits light. 
         [0056]    The current I OUT1  flowing through the laser diode LD 101  when a voltage of the power supply VDD is V is represented by I OUT1 =I 1 . Accordingly, a current I OUT1 ′ obtained when the power supply voltage is shifted from the voltage V by ΔV DS  is represented by the following formula (1) 
         [0000]        I   OUT1   ′=I   1 ×(1+αΔ V   DS )  (1) 
         [0000]    where α represents a channel length modulation effect coefficient. 
         [0057]    Next, a description is given of operations of the correction circuit B 101 . A current I 2  proportional to the current I 1  flows from the correction current setting current source I 102 . The current flows as a current I N  through the MOSFET M 103  and the MOSFET M 104  via the current mirrors CM 103  and CM 102 . Since the current mirrors CM 103  and CM 102  have the cascode configuration, the current I N  can be set constant regardless of the power supply voltage, whereby I N =I 2  is satisfied. 
         [0058]    On the other hand, the current I 2  also flows through the MOSFET M 117  via the current mirror CM 106 . A current obtained when the power supply voltage is V is represented as a correction current I C . The current flows as a current I P  through the MOSFET M 109  and the MOSFET M 110  via the current mirrors CM 105  and CM 104 . Since the current mirrors CM 105  and CM 104  have the cascode configuration, a relation between a current I C  and the current I P  is set so as to satisfy I P =I C  regardless of the power supply voltage. The correction current output from the correction circuit B 101  is represented by I P −I N . Accordingly, the correction current is represented by I C −I 2  as apparent from the above description. 
         [0059]    In this case, when the power supply voltage is V, the MOSFET M 118  and the voltage V REF  to be applied to the gate thereof are set so as to satisfy I C =I 2 , that is, I P =I N . As a result, an output current of the correction circuit B 101  becomes 0 when the power supply voltage is V, whereby I OUT1 =I 1  is satisfied. 
         [0060]    Next, consideration is made of the output current of the correction circuit B 101  in a case where the power supply voltage is shifted from the voltage V. Assuming that the current I C  flowing through the MOSFET M 117  when the power supply voltage is shifted from the voltage V by ΔV DS  is represented as I C ′, I C ′=I 2 ×(1+αΔV DS )=I P ′ is satisfied. Accordingly, when the power supply voltage is shifted by ΔV DS , the current: I OUT1 ′ output to the laser diode LD 101  is represented by the following formula (2). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
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         [0061]    When the following formula (3) is satisfied in the formula (2), the current I OUT1 ′ output to the laser diode LD 101  when the power supply voltage is shifted from the voltage V by ΔV DS , becomes I 1  regardless of power supply variations. 
         [0000]      0=α I   1   ΔV   DS   −αI   2   ΔV   DS −α 2   I   2   ΔV   DS   (3) 
         [0062]    Assuming that I 2 =aI 1 , where “a” is a constant, because the current I 2  is proportional to the current I 1 , 
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         [0000]    is established. 
         [0063]    As a result, a=1/(1+αΔV DS ) is satisfied. In this case, since αΔV DS  is about 0.05 under the condition of a power supply voltage variation of 10% in actual use, when a 0.95 is satisfied, the power supply variation in the current I OUT1  can be suppressed. 
         [0064]    Assuming that αΔV DS =0.05, a current fluctuation amount in a case where the correction circuit B 101  is not provided is calculated according to the formula (1), 
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         [0000]    is established. 
         [0065]    On the other hand, in the case of employing the correction circuit B 101 , when the mount of current fluctuation is calculated according to the formula (2) by substituting a=0.95, 
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                                
                               
                                   
                               
                                
                               1 
                             
                           
                         
                         ) 
                       
                       
                         I 
                         
                           OUT 
                            
                           
                               
                           
                            
                           1 
                         
                       
                     
                     × 
                     100 
                   
                   = 
                   
                     
                       ( 
                       
                         0.05 
                         - 
                         
                           0.95 
                           × 
                           0.05 
                         
                         - 
                         
                           
                             0.05 
                             2 
                           
                           × 
                           0.95 
                         
                       
                       ) 
                     
                     × 
                     100 
                   
                 
               
             
             
               
                 
                   = 
                   
                     0.0125 
                      
                     % 
                   
                 
               
             
           
         
       
     
         [0000]    is established. Thus, the current fluctuation amount is one four-hundredth of that in the case where the correction circuit is not provided. According to the present invention, the current fluctuation amount can be drastically reduced. Further, there is no need to provide a complicated circuit such as an amplifier as a correction circuit and the number of elements can be reduced, whereby a chip area of an IC can be reduced. The present invention is more effective particularly when a device having a plurality of laser diodes is used and when the current correction circuit has to be provided for each laser diode. Further, the present invention can be attained only with MOSFETs having the same size, and is capable of suppressing the fluctuation in the output current I OUT1  due to variations in a manufacturing process. 
       Second Embodiment 
       [0066]    Next, another embodiment of the present invention will be described.  FIG. 2  shows a circuit diagram of a current drive circuit according to a second embodiment of the present invention. Circuit components identical with those of the first embodiment are denoted by the same reference symbols, and descriptions thereof are omitted as appropriate. 
         [0067]    The current drive circuit shown in  FIG. 2  includes a correction circuit B 201 . As compared with the correction circuit B 101  shown in  FIG. 1 , the correction circuit B 201  has a configuration in which the current mirrors CM 102  and CM 104  are omitted. Accordingly, I P =I 2  and I N =I C  are satisfied, and the correction current output from the correction circuit B 201  is represented by I P −I N =I 2 −I C . That is, a polarity of the correction current output from the correction circuit B 201  is inverted from that of the correction current output from the correction circuit B 101  shown in  FIG. 1 . 
         [0068]    Therefore, the output current setting current source I 101  is also disposed on the side of the power supply VDD. A current similar to that of the first embodiment is supplied to the laser diode LD 101  via a cascode current mirror CM 202  and the current mirror CM 101 . In the circuit of the second embodiment, the number of elements can be reduced and the number of loops in the current mirror is reduced as compared with the circuit of the first embodiment, with the result that a current error generated by the current mirror can be reduced, and the current correction against power supply variations can be performed with higher accuracy. 
       Third Embodiment 
       [0069]    Next, still another embodiment of the present invention will be described.  FIG. 3  shows a circuit diagram of a current drive circuit according to a third embodiment of the present invention. Circuit components identical with those of the first embodiment are denoted by the same reference symbols, and descriptions thereof are omitted as appropriate. 
         [0070]    The current drive circuit shown in  FIG. 3  includes a correction circuit B 301 . In the correction circuit B 301 , the current mirror CM 202  is further omitted as compared with the correction circuit B 201  shown in  FIG. 2 . Accordingly, I P =I C  and I N =I 2  are satisfied, and a correction current output from the correction circuit B 301  is represented by I P −I N =I C −I 2 . In other words, the correction current output from the correction circuit B 301  becomes equal to the correction current output from the correction circuit B 101  shown in  FIG. 1 . 
         [0071]    Therefore, the MOSFET M 109  and the MOSFET M 117  are replaced with each other, and the MOSFET M 110  and the MOSFET M 118  are replaced with each other. As in the correction circuit B 101  shown in  FIG. 1 , the output current setting current source I 101  is disposed on the side of the ground GND. A current similar to that of the first embodiment is supplied to the laser diode LD 101  via the current mirror CM 101 . In the circuit of the third embodiment, the number of elements can be further reduced and the number of loops in the current mirror is reduced as compared with the circuit of the second embodiment, with the result that a current error generated by the current mirror can be reduced, and the current correction against power supply variations can be performed with higher accuracy. 
         [0072]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.