Abstract:
Embodiments of an apparatus and methods for controlling power of a processor having a plurality of cores can independently control individual or selected cores and power supply circuits corresponding to the cores based on, for example, an operation state of the processor or a power mode. Embodiments of an apparatus for controlling power of a processor having a plurality of cores can include a plurality of power supply units each capable of independently supplying a supply power to a plurality of cores provided in one processor, a unit for checking at least one among a use state, a use amount and a power mode of each core and for turning on/off each checked core, and a unit that contacts with the unit for checking for controlling the power supply units in response to an on/off operation of each core.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to an apparatus for controlling the power of a processor and a control method of the same, and in particular to an apparatus for controlling the power of a processor having a plurality of cores and a control method of the same.  
         [0003]     2. Background of the Related Art  
         [0004]     Generally, a portable computer such as a notebook computer, etc. has been widely used. The portable computer uses a battery power having a limited capacity as a system power. As shown in  FIG. 1 , a DC supply power converted and outputted by a DC/DC converter  10  is supplied to a core  21  through a power input unit  20  provided in a processor  200 . The core  21  operates using the DC supply power.  
         [0005]     Recently, a process having a plurality of different cores has been developed and commercially used. As shown in  FIG. 2 , a processor  210  having a plurality of cores includes a first core  21  and a second core  22 . The first and second cores  21  and  22  are operated using the DC supply power supplied from the power input unit  20 .  
         [0006]     Since the first and second cores  21  and  22  are designed to use a lot of the power, the first and second cores  21  and  22  use a first DC/DC converter  10  and a second DC/DC converter  11 . Here, the first and second DC/DC converters  10  and  11  are alternately turned on/off, so that the power corresponding to 50% of the total power consumption is stably supplied to each element in the system.  
         [0007]     However, when one of the first core  21  and the second core  22  in the processor  210  is not used, for example, when only the first core  21  is used, since the first and second DC/DC converters  10  and  11  are alternately turned on/off, an unnecessary leakage current occurs by the second core  22  that is not currently used. Accordingly, the battery power having a limited capacity is inefficiently used.  
         [0008]     As described above, the related art portable computers and processor have various disadvantages. For example, since the power is applied irrespective of the using state (error state, use amount, etc.) of each core and the power management mode set in the processor, leakage current occurs, and the power is inefficiently used.  
         [0009]     The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.  
       SUMMARY OF THE INVENTION  
       [0010]     An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.  
         [0011]     Another object of the present invention to provide an apparatus for controlling the power of a processor having a plurality of cores and a method for controlling a supply power supplied to a processor having a plurality of cores based on a use amount or an operation state of each core.  
         [0012]     Another object of the present invention to provide an apparatus for controlling the power of a processor having a plurality of cores and a control method of the same capable of controlling cores and supply power based on a power mode.  
         [0013]     Another object of the present invention to provide an apparatus for controlling the power of a processor having a plurality of cores and a method for controlling a supply power supplied to a processor having a plurality of cores that independently supplies power to each of the plurality of cores.  
         [0014]     In order to achieve at least the above objects in a whole or in part, there is provided an apparatus for controlling power of a processor having a plurality of cores that includes a plurality of power supply devices each for independently supplying power to one of a plurality of cores provided in one processor, a first device for checking at least one among a core use state, a core power mode or a core use amount of each core and for turning on/off said each core and a second device for controlling the plurality of power supply devices according to said on/off operation of said each core.  
         [0015]     To further achieve at least the above objects in a whole or in part, there is provided a method for controlling power of a processor having a plurality of cores that includes checking a use state of each of a plurality of cores provided in one processor and independently disconnecting power supplied to at least one core that is not being currently used as a result of the checking.  
         [0016]     To further achieve at least the above objects in a whole or in part, there is provided a method for controlling power of a processor having a plurality of cores that includes checking a power management mode of a processor having a plurality of cores and selectively turning on each core of said plurality of cores based on the checked management mode and the use amount of the processor.  
         [0017]     To further achieve at least the above objects in a whole or in part, there is provided a portable computer that includes a first circuit configured to determine a use state of a plurality of cores of a single processor and a second circuit configured to independently provide power to at least two cores based on the corresponding use state of the core.  
         [0018]     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:  
         [0020]      FIG. 1  is a diagram illustrating the construction of a conventional power control apparatus of a processor having one core;  
         [0021]      FIG. 2  is a diagram illustrating the construction of a related art power control apparatus of a processor having a plurality of cores;  
         [0022]      FIG. 3  is a diagram illustrating construction of a preferred embodiment of a power control apparatus of a processor having a plurality of cores according to the present invention;  
         [0023]      FIG. 4  is a flow chart of a preferred embodiment of a power control method based on the use of a core in a processor having a plurality of cores according to the present invention; and  
         [0024]      FIGS. 5 and 6  are flow charts of a preferred embodiment of a power control method based on the use of a plurality of cores and a power mode according to the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0025]     Embodiments of a power control apparatus and method of a processor having a plurality of cores according to the present invention will now be described. The processor can be in a portable computer or the like. First, a power management mode will be described.  
         [0026]     In the case of a conventional processor, the maximum clock frequency is a prescribed frequency such as 1.7 GHz. Further, the clock frequency is variably controlled.  
         [0027]     For example, the clock frequency could be classified into a plurality of steps or speeds ranging from 600 MHz to a maximum 1.7 GHz, so that the processor can be properly operated. The input voltage could be varied, corresponding to the operation frequency of the processor, to thereby control the speed and power consumption of the processor.  
         [0028]     In the case of the battery mode, it is possible to reduce the clock frequency of the processor to 600 MHz. At this time, the input voltage is reduced, so that the use amount of the battery or battery life is extended.  
         [0029]     The above-described function can be implemented in a process called SpeedStep. Namely, the operation mode of the process could be changed by changing the input power. The above operation mode could be classified into the following categories.  
         [0030]     1. The maximum battery mode is operated at a minimum frequency and voltage. As the use of the power is increased, it is needed to control the clock frequency. It is called Degrade Mode.  
         [0031]     2. The battery optimized mode is operated at a minimum frequency and voltage. According to embodiments of the present invention, it means that one core of the processor is operated. It is called Constant Mode.  
         [0032]     3. The automatic mode is directed to changing the frequency and voltage based on the use of the processor. It is called Adaptive Mode.  
         [0033]     4. The maximum performance mode is operated at a maximum frequency and maximum voltage. According to embodiments of the present invention, it means that a plurality of cores of a processor are operated. It is called None Mode.  
         [0034]      FIG. 3  is a diagram illustrating construction of a power control apparatus of a processor having a plurality of cores according to an embodiment of the present invention. For example, a processor  300  can include a plurality of cores such as a first core  31  and a second core  33 . The processor  300  can further include a first power input unit  30  for applying power to the first core  31 , and a second power input unit  32  for applying power to the second core  33 .  
         [0035]     A first DC/DC converter  100  is preferably connected with the first power input unit  30  for applying a DC component to the first core  31 . A second DC/DC converter  110  is preferably connected with the second power supply unit  32  for applying a DC power to the second core  33 .  
         [0036]     As shown in  FIG. 3 , the DC/DC converters  100  and  110 , the power input parts  30  and  32  and the cores  31  and  33  can be correspondingly be coupled to each other. However, the present invention is not intended to be so limited. A device driver  50  in an operating system OS can check the state of use (e.g., normal operation states of used core or non-used core) of the first and second cores  31  and  33  provided in the processor  300 . When a prescribed or certain error occurs in a certain core, the power management mode of the processor can be automatically changed to the constant mode for thereby independently turning off a corresponding core.  
         [0037]     In addition, an embedded controller  40  can turn on/off the first and second DC/DC converters  100  and  110 . For example, a DC/DC converter that supplies power to the core having an error can be independently turned off based on an embedded controller  40  interface with the device driver  50 .  
         [0038]     When an error does not occur in the first and second cores, the device driver  50  preferably checks the power management mode set in the processor  300 . For example, in the case that the none mode is set, both the first and second cores can be turned on, and both the first and second DC/DC converters  100  and  110  can be turned on based on an interface with the embedded controlled  40 .  
         [0039]     When the power management mode of the processor  300  is set to the adaptive mode that is first implemented in an embodiment of the present invention, one core between the first and second cores (or additional ones), for example, only the first core  31  can be turned on, and only the first DC/DC converter  100  can be turned on based on an interface with the embedded controller  40 .  
         [0040]     The amount of use of the first core can be checked. For example, when the amount of the use of the first core reaches 100%, both the first and second cores  31  and  33  are turned on, and both the first and second DC/DC converters  100  and  110  are turned on based on an interface with the embedded controller  40 .  
         [0041]     According to one embodiment of the present invention, an ON/OFF control signal can be performed in a device driver of the OS (Operating System), a BIOS (Basic Input Output System) of the system or an EC (embedded controller). However, the present invention is not intended to be so limited.  
         [0042]     The amount of the use of the first and second cores, (e.g., the entire amount of the use of the processor) can be checked. For example, when the entire amount of the use of the processor is below 50%, only the first core  31  preferably is turned on, and only the first DC/DC converter  100  is turned on based on an interface with the embedded controller  40 . The ON/OFF operations can be optimally performed or performed in combination based on the use state of each core and various power management modes, so that battery power consumption because of current leakage can be reduced or prevented. The performance of the processor can be maintained in a selected or an optimum state.  
         [0043]     Operations according to embodiments of the present invention will now be described.  FIG. 4  is a flow chart of an embodiment of a power control method based on the use of a core in a processor having a plurality of cores according to the present invention. The embodiment of a power control method can be applied to and will be described using the apparatus of  FIG. 3 . However, the present invention is not intended to be so limited.  
         [0044]     For example, in the portable computer such as a notebook computer, etc., when a power supply and a system booting sequence are performed (block S 40 ), the embedded controller  40  can allow the first and second DC/DC converters  100  and  110  to be turned on. Further, the device driver  50  can allow the first and second cores  31  and  33  provided in the processor  300  to be turned on (block S 41 ).  
         [0045]     In addition, the device driver  50  can check the use state (e.g., status) of the first and second cores  31  and  33  provided in the processor (block S 42 ). As a result of the check, in the case that a non-use core is detected (block S 43 ), for example, when the first core is being used, and the second core is not used, the device driver  50  can allow the first core  31  to maintain a turned on state and allows the second core  33  to be turned off (block S 45 ).  
         [0046]     The device driver  50  can provide the use state of the plurality of cores based on an interface with the embedded controller  40 . For example, the device driver can inform the embedded controller  40  of a state that the first core is being used, and the second core is not used. The embedded controller  40  can allow the first DC/DC converter  100  to maintain a turned on state where the first DC/DC converter  100  supplies the DC power to the first core that is currently being used and can allow the second DC/DC converter  110  to be turned off where the second DC/DC converter  110  applies the DC power to the second core (block S 46 ).  
         [0047]     Thereafter, it can be checked whether the system is completed (e.g., enabled) or not (block S 47 ). When the system is not intended to be turned off, it is preferably operated based on the constant mode by the core that is not turned off (block S 48 ). From block S 48 , control can jump to block S 42 .  
         [0048]     The disconnection of the power supply with respect to the core can be designated by a user (e.g., block S 44 ). For example, the user can designate a certain process for disconnecting the power supply supplied to the second core  33 , and the embedded controller  40  can allow the second DC/DC converter  100  to be turned off where the second DC/DC converter  110  applies the power to the second core  33  and can allow the second core  33  to be turned off based on an interface with the device driver  50 .  
         [0049]     As described above, the power control method of  FIG. 4  can control each unnecessary (e.g., unused) core and DC/DC converter to be independently turned off based on the use state of each core provided in the processor or a user&#39;s selection. Thus, it is possible to efficiently reduce or prevent the leakage of current and over consumption of battery power.  
         [0050]      FIGS. 5 and 6  are flow charts illustrating another embodiment of a power control method based on the use of a plurality of cores and a power mode according to the present invention. The embodiment of a power control method can be applied to and will be described using the apparatus of  FIG. 3 . However, the present invention is not intended to be so limited.  
         [0051]     As shown in  FIGS. 5 and 6 , the device driver  50  can check the user state of at least two cores (e.g., first and second cores  31  and  33 ) provided in the interior of the processor (block S 50 ). As a result of the check, when a certain error occurs in one core, for example, an error occurs in the first core  31  (block S 51 ), the device driver  50  can allow the power management mode of the processor  300  to be automatically set to a selected mode (e.g., the constant mode). Then, the first core  31  can be turned off and the corresponding first DC/DC converter  100  can be turned off (block S 52 ).  
         [0052]     As described above, the current leakage does not occur by the first core  31  which has an error, and the first DC/DC converter  100  adapted to apply the power responsive to the first core. Further, a normal operation can be achieved by additional cores, e.g., the second core  33 , that does not have any error.  
         [0053]     Then, a check can be performed for an error in each of the at least two cores (block S 53 ). As a result of the check, for example in the case that the error occurs in both the cores (e.g., all processor cores), the error occurs in both the first and second cores  31  and  33  (block S 53 ), it can be judged as the system fail (block S 54 ).  
         [0054]     As a result of the check, when the error does not occur in the cores, the device driver  50  can confirm a selected (block S 53 ) power management mode (e.g., set in the processor  300 ). For example, the power management mode could be set to none mode, constant mode or adaptive mode or the like, for example, based on the user&#39;s selection.  
         [0055]     The confirmed power management mode can be (e.g., set) the none mode (block S 55 ), where the device driver can  50  allow the first and second cores  31  and  33  to be turned on and allow the first and second DC/DC converters  100  and  110  to be turned on based on an interface with the embedded controller  40 . Therefore, both the first and second cores  31  and  33  (e.g., all cores) are operated to achieve a higher or the maximum performance in the processor (block S 56 ). In this case, over power consumption can occur.  
         [0056]     The confirmed power management mode can be (e.g., set) the adaptive mode (block S 58 ), where the device driver can  50  allow a certain preset core/subset of cores, for example, the first core  31  to be turned on and allow the first DC/DC converter  100  to be turned on based on an interface with the embedded controller  40  (block S 59 ).  
         [0057]     Further, the use amount of the preset core can be checked (blocks S 60 , S 62 ). For example, when the use amount of the first core reaches 100% (block S 60 ), the additional core/cores (e.g., second core  33 ) that was turned off, can be turned on so that both the first and second cores (e.g., additional) are turned on. The second DC/DC converter  110  that was turned off, can be turned on based on an interface with the embedded controller  40 , so that both the first and second DC/DC converters  100  and  110  are turned on.  
         [0058]     When multiple cores (e.g. both the first and second cores  31  and  33 ) are turned on, the device driver  50  checks the use amounts of the cores (e.g., first and second cores), respectively, for thereby checking the entire use amount of the processor. For example, as a result of the check, when the entire use amount of the processor is below a prescribed amount (e.g., 50%) (block S 62 ), the second core  33  can be turned off, and the second DC/DC converter  110  can be turned off based on an interface with the embedded controller  40  (block S 63 ).  
         [0059]     In the none mode or adaptive mode, when an error occurs in one of two cores, the device driver  50  can allow the power management mode to be automatically set to the constant mode for thereby turning off the core that has an error, and the DC/DC converter that applies the power to the core is turned off. The above operations can be repeatedly performed (block S 57 ).  
         [0060]     Therefore, when the power management mode of the processor is set in the adaptive mode, the device driver  50  can allow the first and second cores (e.g., a plurality of cores) to be selectively turned on/off based on the use amount of a core being used or the entire use amount of the processor. The embedded controller  40  can allow the first and second DC/DC converters to be selectively turned on/off to reduce or minimize the power consumption of the battery by the leakage current. Therefore, the performance of the processor can be improved or optimized.  
         [0061]     Embodiments according to the present invention relate to a power control apparatus and methods of a processor having a plurality of cores. In the processor having a plurality of cores according to embodiments of the present invention, power applied to the cores can be controlled based on at least one member chosen from of the use amount and the operation state of the cores. The cores can also be controlled based on the power mode. However, the present invention is not intended to be so limited as other user selected or system criteria can be used to independently control operations of each of a plurality of cores.  
         [0062]     Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments. Furthermore, for ease of understanding, certain method procedures may have been delineated as separate procedures; however, these separately delineated procedures should not be construed as necessarily order dependent in their performance. That is, some procedures may be able to be performed in an alternative ordering, simultaneously, etc.  
         [0063]     As described above, embodiments of the present invention have various advantages. In embodiments according to the present invention, the usage states with respect to the cores provided in one processor can be checked, so that it is possible to uncouple the power supply to the cores that are not currently used. In addition, it is possible to independently disconnect the power supply applied to a prescribed core that a user designates. The states of uses of the cores provided in one processor can be checked, and the core having an error is directly disabled and power supply devices that apply a corresponding power to the disabled core can be disabled (e.g., off). Cores could be turned on/off based on the power management mode set in the processor. Cores can be selectively turned on/off based on the use amount of the processor while a DC/DC converter corresponding thereto is turned on/off In addition, the leakage current occurring because of at least one unnecessary core and power supply device can be reduced or prevented, and the processor is efficiently used. Thus, according to embodiments it is possible to efficiently use the power based on the use of the power matching with the operation state of the processor and the power mode.  
         [0064]     The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.