Abstract:
A digital color image signal processing apparatus includes a signal generator that generates a plurality of color component signals and converting circuitry that converts each of the color component signals into a plurality of output signals. A discriminator circuit determines which of the color component signals has minimum value. The minimum value color component signal is used as a basis for selecting at least one of the plurality of output signals which is utilized to obtain each final color signal used for image formation. This apparatus may include a density converter for converting color component signals to density signals, wherein at least one of the density signals is selected for use in image formation in response to the determination by the discriminator circuit of which of the color component signals has a minimum value. Accordingly, this apparatus improves image gradation in low density level areas without requiring large scale processing circuits.

Description:
This application is a continuation of application Ser. No. 201,871 filed June 3, 1988, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital color image signal processing apparatus. 
     2. Brief Description of the Related Art 
     One exmaple of conventional color image signal processing circuts for a digital color copier is shown in FIG. 8. As shown there, three digital color luminance signals R (red), G (Green), B (Blue) produced by a CCD (charge coupled device) 301 are converted into three digital color density signals D R , D G , D B  by a density conversion circuit 302. Then the three digital color density signals D R , D G , D B  are input to a black processing circuit 303 which comprises a black component generation circuit for generating a black component BK, and an UCR (Under Color Removal) for respectively removing the black component from the three digital color density signals D R , D G , D B  to obtain digital signals D R , D G , D B  exlcuding the black component. A masking circuit 304 is provided for correcting color signals or removing asymmetrical components, and outputs C (cyan), M (magenta), Y (yellow) signals of the masking circuit 304 and the black component BK from the black processing circuit 303 are supplied to a color printer 305. The color printer 305 reproduces a color image in accordance with supplied signals C, M, Y, BK. 
     FIG. 9 shows a conventional block diagram in greater detail of the a main part of color image signal processing circuits shown in FIG. 8. As can be seen there, the three digital color luminance signals R, G, B from the CCD 301 (FIG. 8) are respectively input to three look-up tables (LUT) 204, 205, 206 which comprise random access memories (RAM). The LUTs 204, 205, 206 convert the input color luminance signals R, G, B into the three digital color density signals D R , D G , D B . FIG. 10 shows a characteristic for conversion of the luminance signals R, G, B into the density signals D R , D G , D B . In this case, each of the luminance signals R, G, B is an 8-bit signal, namely each luminance signal has 256 steps of halftone gradation. Each characteristic of the LUTs 204, 205, 206 is able to be expressed by the following relations: ##EQU1## where F R , R G , F B  respectively are functions of three characteristics of the LUTs 204, 205, 206. 
     A minimum value determining circuit 207 detects and outputs a minimum value from among the density signals D R , D G , D B  and a multiplier 208 multiplies the minimum of the density signals, MIN (D R , D G , D B ), by a constant K (O&lt;K≦1) in order to obtain the black component signal BK. That is: 
     
         BK=K×MIN (D.sub.R, D.sub.G, D.sub.b)                 (2) 
    
     Three subtractors 209, 210, 211 are also provided for respectively subtracting the black component signal BK frome ach of the three density signals D R , D G , D B  in accordance with he following relation: ##EQU2## A masking processing circuit 212 comprises multipliers and adders, and performs the operation of the following relation. ##EQU3## where {A IJ  } is a linear 3×3 matrix, and C, M and Y respectively represent the resulting cyan signal, magenta signal and yellow signal. 
     Then signals C, M, Y and BK are supplied to the digital color ptiner 213 which i capable of reproducing color gradation. 
     In the above mentioned conventional processing circuit, however, output color signals C, M, Y are obtained from input color signals R, G, B, by being processed through a series of adders, subtractors and multipliers. Therefore, the signals C, M, Y may have digital operational errors. In order to reduce the digital operational errors, each processing circuit should increase the number of bits used in the processing. However, this causes the size of the processing circuit nessarily to become large. 
     As shown in FIG. 10 and FIG. 11, the characteristic of conversion is very similar to a logarithmic function. Thus, if a simple LUT is provided as a convertor for converting from a luminance signal to a density signal, gradation loss occurs especially in the low density level area (highlight area). 
     In order to prevent the gradation loss in the low density level are, the number of output bits of the LUT is set greater than a number of input bits as shown in FIG. 12 and FIG. 13. FIG. 12 shows a characteristic of a LUT 130 in FIG. 13. However, in FIG. 9, if the number of bits of each density signal D R , D G , D B  is increased, other processing circuits in FIG. 9 must be specified appropriately to properly operate on such additional bits. Therefore, the scale of each processing circuit also becomes very large. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the above described problems by providing a digital color image signal processing circuit that can improve the gradation in the low density level area without using large scale processing circuits. 
     In one aspect the present invention converts each input signal to a plurality of output signals, selects some of the output signals, and adds together the selected output signals to obtain each final color signal. 
     In another aspect, the invention comprises a density converter for converting a plurality of digital color signals to a plurality of density signals, a minimum value discriminator for disciminating the digital signal having minimum value from among the plurality of digital color signals, and a selector for selecting density signals from the converter in response to the result of the discrimination by the discriminator. 
     The foregoing summary of certain more important features of the invention is provided in order that the detailed description of the preferred embodiment thereof that follows may be better understood, and in order that the present contribution to the art may be better appreciated. There are, of course, additional features of the invention that will be described in that detailed description with reference to the accompanying drawings. Those skilled in the art will appreciate that the conception upon which this disclosure is based may readily be utilized as a basis for designing other structures or methods for carrying out the purposes of the invention. It will be understood what the claims are to be regarded as including such other constructions and methods as do not depart from the spirit and scope of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating one embodiment of the present invention. 
     FIG. 2 is a flow chart illustrating a color printing process. 
     FIG. 3A is a flow chart illustrating the setting of LUTs for processing a magenta signal M. 
     FIG. 3B is a flow chart illustrating control of a lens selector. 
     FIGS. 4, 5 and 6 are flow charts respectively illustrating the setting of LUTs for processing a cyan signal C, a yellow signal Y and a black component signal BK respectively. 
     FIG. 7 is a block diagram illustrating a minimum value discriminating circuit. 
     FIG. 8 is a block diagram illustrating a conventional color image processing circuit. 
     FIG. 9 is a detailed block diagram of a part of the circuit shown in FIG. 8. 
     FIG. 10 and FIG. 11 are graphs showing characteristics of density conversion. 
     FIG. 12 is a graph showing a characteristic of LUT 130. 
     FIG. 13 is a block diagram illustrating a density conversion. 
     FIG. 14 is a block diagram of circuitry for determining the minimum value from among the R, G and B signals. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Before explaining the circuit in accordance with a preferred embodiment, the basic principle of the present invention will be described below. 
     The prescribed equations (1) through (4) can be rewritten as follows. ##EQU4## 
     Therefore, the following three cases I, II, III can be considered. 
     (I) In the case where MIN (D R , D G , D B )=D R . ##EQU5## 
     (II) In the case where MIN (D R , D G , D B )=D G  ##EQU6## 
     (III) In the case where MIN (D R , D G , D B )=D B  ##EQU7## 
     Now, the cyan signal C can be expressed as follows: ##EQU8## where C R  is the cyan signal C in the case (I), i.e., MIN (D R , D G , D B )=D R . 
     C G  is the cyan signal in the case (II), i.e., MIN (D R , D G , D B )=D G . 
     C B  is the cyan signal C in the case (III), i.e., MIN (D R , D G , D B )=D B . 
     As shown in the equation (9), in order to obtain the cyan signal C, operation of the processing circuits for each input color signal is necessary. 
     FIG. 14 shows two circuits 1 and 2 for the input color signal R, two circuits 3 and 4 for the input color signal G, and two circuits 5 and 6 for the input color signal B. 
     In the equation (9), all elements or coefficients of the 3×3 matrix are constants, so that the operation circuits 1 through 6 in FIG. 14 can be structured merely by conventional look-up tables. 
     Further, the coefficients of the matrix are limited as follows: ##EQU9## 
     And the constant K is limited as follows; 
     
         0&lt;K≦1                                               (11) 
    
     Therefore, the following equations are derived from the equations (10) and (11). ##EQU10## 
     Based on the equation (12), an increase of three bits in each of the operation circuits 126 is sufficient, with these three bits including a polarity bit, to remove the operational error in the circuits 126. 
     The above discussion is only of processing the cyan signal. 
     The same explanation applies to the magenta signal M and the yellow signal Y. For example, referring to the magenta signal M: ##EQU11## where M R  is the magenta signal M in the case (I), i.e., MIN (D R , D G , D B )=D R . 
     M G  is the magenta signal M in the case (II), i.e., MIN (D R , D G , D B )=D G . 
     M B  is the magenta signal M in the case (III), i.e., MIN (D R , D G , D B )=D B . 
     Referring to the yellow signal Y: ##EQU12## where Y R  is the yellow signal Y in the case (I), i.e., MIN (D R , D G , D B )=D R . 
     Y G  is the yellow signal Y in the case (II), i.e., MIN (D R , D G , D B )=D G . 
     Y B  is the yellow signal Y in the case (III), i.e., MIN (D R , D G , D B )=D B . 
     The black signal component signal BK can also be described as below. ##EQU13## where 
     
         BK.sub.R is the black signal BK in the case (I), i.e., MIN (D.sub.R, D.sub.G, D.sub.B)=D.sub.R. 
    
     
         BK.sub.G is the black signal BK in the case (II), i.e., MIN (D.sub.R, D.sub.G, D.sub.B)=D.sub.G. 
    
     
         BK.sub.B is the black signal BK in the case (III), i.e., MIN (D.sub.R, D.sub.G, D.sub.B)=D.sub.B. 
    
     
                                                                    (16) 
    
     The black component signal BK also can be obtained by using a conventional look-up table for the input color signals R, G, B. 
     As described above, it will be understood that the final output signals C, M, Y can be obtained by using a pair of operational circuits for each input color signal, a selecting circuit for selecting one of the outputs of the pair of operational circuits in response to the input signal that has minimum value, and an adder circuit for adding the selected signals. 
     These structures provide the same result provided by the conventional color processing circuit shown in FIG. 9, but the increase in the number of bits, which must be processed by the look-up table in order to operate, is only three bits. 
     The detailed description of the preferred embodiment of the present invention will now be provided with reference to the Figures. 
     Referring first to FIG. 1, a red signal input part 101 is provided for inputting a digital red luminance signal R which has 8 bits. Similarly, a green signal input part 102 and a blue signal input part 103 are provided for respectively inputting a digital green luminance signal and a digital blue luminance signal each having 8 bits. 
     Look-up tables (LUT) 104 to 109 are provided for converting the density level of the input luminance signals and comprise random access memories (RAM). The LUTs 104 to 109 each have 8 bit inputs and 13 bit outputs in this embodiment. A central processing unit (CPU) 110 is provided for calculating the coefficients set in the LUTs 104 to 109 and for writing the coefficients set in the LUTs 104 to 109. A bus selector 111 is provided for selecting a bus line for the color digital signals in response to a signal from a minimum value discriminating circuit 112. The minimum value discriminating circuit 112 discriminates the signal which has the minimum density value from among the color luminance signals R, G, B, and controls the bus selector 111. 
     An adder 113 is provided for adding the outputs from the bus selector 111, and the adder 113 outputs 10 bits to a color printer 115. The color printer 115 prints a color image in response to outputs of the adder 113. 
     FIG. 2 is a flow chart illustrating a color print process. In this embodiment, the color printer 115 prints a magenta image first, then prints a cyan image, then prints a yellow image, and finally prints a black image. The color printer 115 doesn&#39;t start printing a succeeding color before it finishes printing the preceding color. 
     In a step S901, the CPU 110 performs multiplications on each of the coefficients of the matrix in the equation (13) and each of F R  (R), F G  (G), F B  (B) in the CPU 110, and sets and stores the resulting values of the multiplications in he LUTs 104 to 109. 
     FIG. 3A is a concise flow chart illustrating setting the magenta signal into the LUTs. 
     In a step S31, the CPU 110 performs A21×F R  (R), and stores the value of the operation in the LUT 104 for every value of the input color signal (R). Similarly, in the step S32, the CPU 110 calculates {A 31  -(A 21  +A 22  +A 23 )×K}×F R  (R), and stores the value of the operation in the LUT 105 for every value of (R). 
     Further, in a step S33, the CPU 110 performs A 22  ×F G  (G), and stores the results in the LUT 106 for every value of the input color signal (G). In a step S34, the CPU 110 performs {A 22  -(A 21  +A 22  +A 23 )×K}×F G  (G) for every value of the input color signal (G) and stores the results in the LUT 107. 
     In a step S35, the CPU 110 performs A 23  ×F B  (B) for every value of the input color signal (B), and stores the results in the LUT 108. 
     In a Step S36, the CPU 110 performs {A 23  -(A 21  +A 22  +A 23 )×K}×F B  (B) for every value of the input color signal (B), and stores the results in the LUT 109. Namely the odd numbered LUTs 105, 107, 109 respectively store the results when the corresponding color signal is the minimum value, and the even numbered LUTs 104, 106, 108 respectively store the results when the corresponding color signal is not the minimum value. 
     The bus selector 111, which comprises conventional multiplexers, selects the lower signal when the corresponding color signal has the minimum value, and selects the upper signal when the corresponding color signal does not have the minimum value. 
     The bus selector 111 can be controlled by a microcomputer using a program shown in FIG. 3B. 
     In a step S902 (FIG. 2), the color printer 115 prints the magenta image in response to the magenta signal M. Similarly, in a step S903, the CPU 110 multiplies each of the coefficients of the matrix in equation (14) and each of F R  (R), F G  (G), F B  (B) stored in the CPU 110, and sets and stores the resulting values of the multiplications in the LUTs 104 to 109 for the cyan signal. These operations are shown steps S41 through S46 in FIG. 4. 
     Then, in a step S904, the bus selector 111 operates as described above and the color printer 115 prints the cyan image in response to the cyan signal C. 
     Similar to the processing for the magenta and cyan images, in a step S905, the CPU 110 multiplies each of the coefficients of the matrix in the equation (14) and each of F R  (R), F G  (G), F B  (B) stored in the CPU 110, and sets or stores the resulting values of the multiplications in the LUTs 104 to 109 for the yellow signal. These operations are shown as steps S51 in S56 in FIG. 5. 
     In a step S906, the bus selector 111 operates as described above, and the color printer 115 prints the yellow image in response to the yellow signal Y obtained from the adder 113. 
     Then, in a step S907, the CPU 110 multiplies the constant K and each of F R  (R), F G  (G), F B  (B) stored in the CPU 110, and sets or stores the resulting values of the mulitplications in the LUTs 105, 107, 109 for the black component signal. On the other hand, the CPU 110 sets &#34;0&#34; in the LUTs 104, 106, 108. These operations are shown in steps S61 to S66 in FIG. 6. 
     Then in a step S908, the bus selector 111 operates the same as described above, and the color printer 115 prints the black image in response to the black componetn signal BK obtained from the adder 113. 
     The values of F R  (R), F G  (G), F B  (B) stored in the CPU have 10 bits output versus 8 bits input, as shown in FIG. 12 which shows a characteristic of the LUT in FIG. 13. 
     A characteristic of the LUT in FIG. 13 is that it has a number of output bits greater than the number of input bits. 
     Therefore the gradation loss in the low density level should be reduced. 
     By the way, the adder 113 shown in FIG. 1 has thirteen input bits and ten output bits in this embodiment. 
     FIG. 7 is a block diagram illustrating an example of the minimum value discriminating circuit 112. As shown there, LUTs 1401, 1402, 1403, which comprie read only memories (ROMs), are provided for storing converted density values corresponding to the input luminance signals R, G, B obtained from the CCDs. The conversion characteristics of these LUTs are shown by the equation (1). 
     A comparative operation circuit 1404, which has 3 input terminals and one 2-bit output terminal, discriminates which signal has the minimum value, and outputs the result of the discriminating to the bus selector 111. 
     In this above-mentioned embodiment, the number of bits of the output color signal is set to be greater than that of the input color signa lin order to improve the gradation characteristic in the low density level area. However, if the number of bits of the output color signal is set to be smaller than that of the input color signals, a structure of a processing circuit is simplified. 
     In the above-described embodiment, the color printer prints each color M, C, Y, BK individually and sequentially. 
     However, if the circuit of FIG. 1 is provided for each color, specifically if the LUTs 104 to 109, the bus selector 111, and the adder 113 are provided in parallel for all colors Y, M, C, Bk, then the color image processing for all colors proceeds simultaneously and the color image of all colors can be printed simultaneously. 
     As mentioned above, the present invention, which includes the selector for selecting the calculated or converted signal values and the adder for adding the selected values, enables the color image processing circuit to be simplified. Further if the number of bits of the output color signal is set greater than that of the input color signals, the gradation characteristic, especially that of the low density level area can be improved. 
     Although particular embodiments of the present invention are herein described in detial for purposes of explanation, various modifications thereof, after study of this specification, will be apparent to those skilled in the art to which the invention pertains.