Abstract:
In order to improve the robustness against electrostatic discharge, when power source terminal and ground terminal are open, of a semiconductor device having a first, a second and a third inverter that are connected in a cascade arrangement, the semiconductor device is provided not only with a first input protection circuit for guiding positive electrostatic discharges, that are applied from outside to a signal input terminal, to a power source line, and a second input protection circuit for guiding negative electrostatic discharges, that are applied from outside to the signal input terminal, to a ground line, but also an internal protection circuit for guiding electrostatic discharges that have been guided by the first input protection circuit to the power source line and flow from a P-channel MOS transistor in the second inverter towards the third inverter, to the ground line.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to circuit technology for preventing electrostatic damage of semiconductor devices.  
           [0002]    Semiconductor devices (semiconductor integrated circuits) are known that have a first input protection circuit for guiding positive electrostatic discharges, that are applied from the outside, to a signal input terminal to a power source line, and a second input protection circuit for guiding negative electrostatic discharges, that are applied from the outside to that signal input terminal, to a ground line. The first and the second input protection circuit are respectively made of diodes, MOS transistors or bipolar transistors (see JP H09-139466A).  
           [0003]    It is possible to configure a delay circuit with a plurality of cascaded inverters. The inverters may be configured by P-channel MOS transistors and N-channel MOS transistors. If the above-noted first and second input protection circuits are used for a semiconductor device having such a delay circuit, then the first-stage inverter, which is directly connected to the signal input terminal, can be protected from gate insulation damage when electrostatic discharges are applied to the signal input terminal. However, when positive electrostatic discharges are applied to the signal input terminal while the power source terminal and the ground terminal are open (no-voltage state), for example in the assembly line for the appliance in which the semiconductor device is to be mounted, then the internal inverters may suffer gate insulation damage.  
         SUMMARY OF THE INVENTION  
         [0004]    It is an object of the present invention to improve the robustness against electrostatic discharge of semiconductor devices.  
           [0005]    In order to attain this object, a semiconductor device in accordance with the present invention includes a first, a second and a third logic circuit each having a function of inverting a respective input and being directly or indirectly connected in a cascade arrangement; a signal input means for supplying a signal applied from outside through a signal input terminal to the first logic circuit; a power source line capable of supplying a positive power source voltage applied from outside through a power source terminal to the first, second and third logic circuits; a ground line capable of supplying a ground voltage applied from outside through a ground terminal to the first, second and third logic circuits; and furthermore an internal protection circuit interposed on a connection between an output portion of the second logic circuit and an input portion of the third logic circuit and having a path for guiding charges on the connection, that are caused from positive electrostatic discharges on the power source line, to the ground line. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    [0006]FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device in accordance with the present invention.  
         [0007]    [0007]FIG. 2 is a partial cross-sectional view of the semiconductor device in FIG. 1.  
         [0008]    [0008]FIG. 3 is a circuit diagram showing another configuration example of a semiconductor device in accordance with the present invention.  
         [0009]    [0009]FIG. 4 is a partial cross-sectional view of the semiconductor device in FIG. 3.  
         [0010]    [0010]FIG. 5 is a circuit diagram showing yet another configuration example of a semiconductor device in accordance with the present invention.  
         [0011]    [0011]FIG. 6 is a partial cross-sectional view of the semiconductor device in FIG. 5.  
         [0012]    [0012]FIG. 7 is a circuit diagram showing an example of a modified configuration of FIGS. 1, 3 and  5 .  
         [0013]    [0013]FIG. 8 is a circuit diagram showing another example of a modified configuration of FIGS. 1, 3 and  5 .  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]    [0014]FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device in accordance with the present invention. The semiconductor device in FIG. 1 includes a signal input terminal  10 , a power source terminal  20 , a ground terminal  30 , a signal input line  11 , a power source line  21 , a ground line  31 , a first input protection circuit  50 , a second input protection circuit  60 , a first inverter  100 , a second inverter  200 , an internal protection circuit  250 , and a third inverter  300 .  
         [0015]    The first, second and third inverters  100 ,  200  and  300  are cascaded. The first inverter  100  is a CMOS inverter made of a P-channel MOS transistor  101  and an N-channel MOS transistor  102 . Numeral  103  denotes the output line of the first inverter  100 . Also the second inverter  200  is a CMOS inverter made of a P-channel MOS transistor  201  and an N-channel MOS transistor  202 . Numeral  203  denotes the output line of the second inverter  200 . Also the third inverter  300  is a CMOS inverter made of a P-channel MOS transistor  301  and an N-channel MOS transistor  302 . Numeral  303  denotes the output line of the third inverter  300 .  
         [0016]    The signal input line  11  supplies signals applied from the outside via the signal input terminal  10  to the first inverter  100 . The power source line  20  supplies a positive power source voltage applied from the outside via the power source terminal  20  to the first, second and third inverters  100 ,  200  and  300 . The ground line  31  supplies a ground voltage applied from the outside via the ground terminal  30  to the first, second and third inverters  100 ,  200  and  300 .  
         [0017]    The first input protection circuit  50  is made of a diode  51  that guides positive electrostatic discharges, that are applied from the outside to the signal input terminal  10 , to the power source line  21 . The second input protection circuit  60  is made of a diode  61  that guides negative electrostatic discharges, that are applied from the outside to the signal input terminal  10 , to the ground line  31 . The internal protection circuit  250  is a circuit for guiding positive electrostatic discharges, that are guided by the first input protection circuit  50  to the power source line  21  and then flow from the P-channel MOS transistor  201  of the second inverter  200  to the third inverter  300 , to the ground line  31 . The internal protection circuit  250  includes a diffusion resistor  251  formed on the semiconductor substrate and interposed on a connection between an output portion of the second inverter  200  and an input portion of the third inverter  300 . Numeral  252  denotes the input line of the third inverter  300 .  
         [0018]    [0018]FIG. 2 is a partial cross-sectional view of the semiconductor device in FIG. 1. The second inverter  200 , the internal protection circuit  250  and the third inverter  300  are formed on a P-type substrate  70 . Numerals  71  and  72  both denote P-type isolation regions. The P-channel MOS transistor  201  is made of a P-type diffusion source region  212  and a P-type diffusion drain region  213  respectively formed in an N-type well region  211 , and a polysilicon gate electrode  214 . The N-channel MOS transistor  202  is made of an N-type diffusion source region  222  and an N-type diffusion drain region  223  respectively formed in a P-type well region  221 , and a polysilicon gate electrode  224 . The P-type diffusion resistor  251  is made of a P-type diffusion resistance region  262  formed in an N-type epitaxial region  261 . Consequently, a parasitic PNP transistor is formed with the P-type diffusion resistance region  262  serving as the emitter, the N-type epitaxial region  261  as the base and the P-type substrate  70  as the collector. Moreover, the P-type substrate  70  and the P-type isolation region  72  are connected to the ground line  31 . The P-channel MOS transistor  301  is made of a P-type diffusion source region  312  and a P-type diffusion drain region  313  respectively formed in an N-type well region  311 , and a polysilicon gate electrode  314 . The N-channel MOS transistor  302  is made of an N-type diffusion source region  322  and an N-type diffusion drain region  323  respectively formed in a P-type well region  321 , and a polysilicon gate electrode  324 .  
         [0019]    With a semiconductor device having the configuration as shown in FIGS. 1 and 2, when positive electrostatic discharges are applied to the signal input terminal  10  while the power source terminal  20  and the ground terminal  30  are open, the first input protection circuit  50  guides these electrostatic discharges to the power source line  21 . Thus, the gate insulation of the first inverter  100  is protected. However, by letting the positive electrostatic discharges flow into the power source line  21 , the same situation is attained as if a power source voltage were applied from outside to the power source terminal  20 . Consequently, the first and second inverters  100  and  200  perform the operation of inverting their input. Here, the signal input line  11 , which is connected to the signal input terminal  10 , is at H (high) level, so that the first inverter output line  103  becomes L (low) level and the second inverter output line  203  becomes H (high) level. That is to say, the P-channel MOS transistor  201  in the second inverter  200  becomes conductive. As a result, the positive electrostatic discharges from the power source line  21  flow through the P-channel MOS transistor  201  into the second inverter output line  203 . Here, when BVCEO (base circuit is open) is taken to be the breakdown voltage between collector and emitter of the parasitic PNP transistor formed by the P-type diffusion resistance region  262 , the N-type epitaxial region  261  and the P-type substrate  70 , then the parasitic PNP transistor breaks down at the time when the potential of the P-type diffusion resistance region  262  connected to the second inverter output line  203  exceeds BVCEO, and as a result, the electrostatic discharges are diverted to the ground line  31 . Thus, the gate insulation of the third inverter  300  is protected.  
         [0020]    If negative electrostatic discharges are applied to the signal input terminal  10  while the power source terminal  20  and the ground terminal  30  are open, then the second input protection circuit  60  guides these electrostatic discharges to the ground line  31 . Thus, the gate insulation of the first inverter  100  is protected. Moreover, the first and second inverters  100  and  200  do not perform the operation of inverting their input, so that the problem of gate insulating damage in the third inverter  300  does not occur.  
         [0021]    It should be noted that it is also possible to use an N-type diffusion resistor instead of the P-type diffusion resistor  251 .  
         [0022]    [0022]FIG. 3 is a circuit diagram showing another configuration example of the semiconductor device in accordance with the present invention. The internal protection circuit  250  in FIG. 3 includes an NPN transistor  253  interposed on a connection between an output portion of the second inverter  200  and the ground line  31 . The collector of this NPN transistor  253  is connected to the second inverter output line  203 , its emitter is connected directly to the ground line  31 , and its base is connected via a P-type diffusion resistor  254  to the ground line  31 .  
         [0023]    [0023]FIG. 4 is a partial cross-sectional view of the semiconductor device in FIG. 3. The NPN transistor  253  and the P-type diffusion transistor  254  are formed on the P-type substrate  70 . Numeral  271  denotes a P-type isolation region. The NPN transistor  253  is made of an N-type diffusion collector region  273 , a P-type diffusion base region  274  and an N-type diffusion emitter region  275 , all of which are formed in an N-type epitaxial region  272 . The P-type diffusion resistor  254  is made by forming a P-type diffusion resistance region  277  in an N-type epitaxial region  276 . Numeral  278  denotes a base line.  
         [0024]    Also with a semiconductor device having the configuration shown in FIGS. 3 and 4, when positive electrostatic discharges are applied to the signal input terminal  10  while the power source terminal  20  and the ground terminal  30  are open, these electrostatic discharges flow via the first input protection circuit  50  to the power source line  21 , and then the positive electrostatic discharges flow from the power source line  21  through the P-channel MOS transistor  201  into the second inverter output line  203 . Here, when BVCER (base circuit grounded by resistor) is taken to be the breakdown voltage between collector and emitter of the NPN transistor  253 , then the NPN transistor  253  breaks down at the time when the potential of the N-type diffusion collector region  273  connected to the second inverter output line  203  exceeds BVCER, and as a result, the electrostatic discharges are diverted to the ground line  31 . Thus, the gate insulation of the third inverter  300  is protected.  
         [0025]    It should be noted that it is also possible to use a PNP transistor instead of the NPN transistor  253 .  
         [0026]    [0026]FIG. 5 is a circuit diagram showing yet another configuration example of the semiconductor device in accordance with the present invention. The internal protection circuit  250  in FIG. 5 includes an N-channel MOS transistor  255  interposed on a connection between an output portion of the second inverter  200  and the ground line  31 . The drain of this N-channel MOS transistor  255  is connected to the second inverter output line  203 , and the gate and source are both connected to the ground line  31 .  
         [0027]    [0027]FIG. 6 shows a partial cross-sectional view of the semiconductor device in FIG. 5. The N-channel MOS transistor  255  is made of an N-type diffusion source region  282  and an N-type diffusion drain region  283  respectively formed in a P-type well region  281 , and a polysilicon gate electrode  284 .  
         [0028]    Also with a semiconductor device having the configuration shown in FIGS. 5 and 6, when positive electrostatic discharges are applied to the signal input terminal  10  while the power source terminal  20  and the ground terminal  30  are open, these electrostatic discharges flow via the first input protection circuit  50  to the power source line  21 , and then the positive electrostatic discharges flow from the power source line  21  through the P-channel MOS transistor  201  into the second inverter output line  203 . Here, when BVDS is taken to be the breakdown voltage between drain and source of the N-channel MOS transistor  255 , then the N-channel MOS transistor  255  breaks down at the time when the potential of the N-type diffusion drain region  283  connected to the second inverter output line  203  exceeds BVDS, and as a result, the electrostatic discharges are diverted to the ground line  31 . Thus, the gate insulation of the third inverter  300  is protected.  
         [0029]    It should be noted that it is also possible to use a P-channel MOS transistor instead of the N-channel MOS transistor  255 .  
         [0030]    Needless to say, the first and second input protection circuits  50  and  60  in FIGS. 1, 3 and  5  are not limited to diode structures. As shown in FIG. 7, the first input protection circuit  50  can also be configured by a P-channel MOS transistor  52 , and the second input protection circuit  60  can be configured by an N-channel MOS transistor  62 . Moreover, as shown in FIG. 8, the first input protection circuit  50  can also be configured by an NPN transistor  53 , and the second input protection circuit  60  can be configured by another NPN transistor  63 . It is also possible to replace at least one of these NPN transistors  53  and  63  by a PNP transistor.  
         [0031]    In the above explanations, the internal protection circuit  250  was inserted between the output portion of the second inverter  200  and the input portion of the third inverter  300 , but if necessary, it is also possible to provide similar internal protection circuits at the respective input portions of any odd-numbered inverters of later stages. The invention is not limited to the inverters  100 ,  200  and  300 , but can be applied to any semiconductor device in which a plurality of logic circuits having the function to invert their input, such as NAND gates or NOR gates, are cascaded.  
         [0032]    The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.