Abstract:
According to some embodiments, at speed application of test patterns associated with a wide tester interface are enabled on a low pin count tester.

Description:
BACKGROUND  
         [0001]    A device may be evaluated to ensure that is operates properly. For example, a processor might be tested to ensure that it receives, processes, and provides information properly. FIG. 1 is a diagram of a known functional testing system  100  in which a device under test  110  is evaluated by a functional tester  150 . In particular, the functional tester  150  has a wide tester interface. That is, the function tester  150  exchanges information with the device under test  110  via all (or substantially all) of the input and output paths (e.g., pins) that comprise the device&#39;s bus  120 .  
           [0002]    There are a number of disadvantages, however, associated with a functional tester  150 . For example, the bus  120  may include a large number of input and output paths. Moreover, the functional tester  150  may need to provide and/or receive information via each of the paths at the full speed of the bus  120 . As a result, the design and construction of the functional tester  150  can be costly and time consuming. For example, a functional tester  150  that evaluates a processor might need to exchange information via a 300-pin bus at 533 Mega Hertz (MHz). As a result, a large number of ultra-high speed components (e.g., GaAs components) may need to be incorporated in the functional tester  150 .  
           [0003]    As another approach, FIG. 2 is a diagram of a known structural testing system  200  in which a device under test  210  is evaluated by a structural tester  250 . In this case, the structural tester  250  exchanges information with the device under test  210  via a test bus  260  that includes only a subset of the paths in the bus  220 . For example, a 128-pin test bus  260  might be used exchange information with a processor that has a 300-pin bus. Moreover, the structural tester  250  (e.g., a low pin count tester) may exchange information via the test bus  260  at a speed less than the full speed of the bus  220 . Although the design and construction of a structural tester  250  can be less expensive and time consuming as compared to a functional tester  150 , the evaluation of the device under test  210  may be less thorough. For example, because not all of the paths in the bus  220  are used, some logic paths in the device under test  210  may not be fully evaluated.  
           [0004]    As still another approach, it is known that the structural tester  250  can use the test bus  260  to load a set of instructions into a local memory of the device under test  210  (e.g., in a cache structure). The device under test  210  then executes the instructions when the test is performed. Defining an appropriate set of instructions, however, can be difficult (e.g., because a system trace of the entire bus  220  is not easily translated into a set of appropriate instructions). Moreover, it might not be possible to evaluate some portions of the device under test  210  in this way (e.g., portions associated with input and output paths that comprise the entire bus  220 ). 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    [0005]FIG. 1 is a diagram including a known functional tester.  
         [0006]    [0006]FIG. 2 is a diagram including a known structural tester.  
         [0007]    [0007]FIG. 3 is a block diagram of a device under test according to some embodiments.  
         [0008]    [0008]FIG. 4 is a flow chart of a method according to some embodiments.  
         [0009]    [0009]FIG. 5 is an information flow diagram in accordance with an example of the present invention.  
         [0010]    [0010]FIG. 6 is a diagram including a device under test and a structural tester according to some embodiments.  
         [0011]    [0011]FIG. 7 is a flow chart of a structural tester method according to some embodiments.  
         [0012]    [0012]FIGS. 8 and 9 are flow charts illustrating methods of generating test information according to some embodiments.  
     
    
     DETAILED DESCRIPTION  
       [0013]    Some embodiments described herein are associated with a “device under test.” As used herein, the phrase “device under test” may refer to, for example, a processor such as a network processor or a general purpose processor.  
         [0014]    Device Under Test  
         [0015]    [0015]FIG. 3 is a block diagram of a device under test  300  according to some embodiments. In particular, the device under test  300  includes a processor core  310  that may be used to process information. The device under test  300  also includes a cache structure  320  or a local memory located on the same die as the processor core  310 . The cache structure  320  includes a first portion  322  that is available for use by the processor core  310  when a test is performed (i.e., to store and retrieve information).  
         [0016]    According to some embodiments, the cache structure  320  also includes a second portion  324  that is used to store test information. The test information may, for example, be loaded into the second portion  324  from a structural test device.  
         [0017]    In addition, Design For Test (DFT) logic  400  may be provided (e.g., on the same die as the processor core  310  and the cache structure  320 ) to facilitate the evaluation of the device under test  300 . In particular, the DFT logic  400  may include a sequencer  330  that transfers test information from the cache structure  320  to the processor core  310  via paths associated with the device&#39;s interface or “bus.” As used herein, the term “bus” may refer to, for example, a number of input paths (i.e., associated with pins through which the device under test  300  receives information) and a number of output paths (i.e., associated with pins through which the device under test  300  provides information). By way of example, a bus may comprise a Front Side Bus (FSB) that is used to exchange information between the device under test  300  and other system components (e.g., a chipset).  
         [0018]    According to some embodiments, the sequencer  300  transfers test information from the cache structure  320  to the processor core  310  via a multiplexer  340 . The multiplexer  340  may also be adapted to transfer actual bus information from an Input Output (IO) pad  350  to the processor core  310  (i.e., when the device under test  300  is used in normal operation and not in test mode). Note that the processor core  310  may also provide information to the bus via the IO pad  350 .  
         [0019]    The DFT logic  400  may further include a result accumulator  360  that receives information from the processor core  310  (e.g., through the output paths of the bus). The result accumulator may also receive from the sequencer  330  mask information indicating which output paths currently have valid information (e.g., information that should be accumulated). By way of example, the result accumulator  360  may comprise a Multi-Input Signature Register (MISR) adapted to store test result information (e.g., a signature associated with a test). According to other embodiments, the DFT logic  400  instead includes a comparator that evaluates the functionality and/or performance of the device under test  300 .  
         [0020]    Test Method  
         [0021]    [0021]FIG. 4 is a flow chart of a test method according to some embodiments. The flow charts described herein do not imply a fixed order to the actions, and embodiments may be practiced in any order that is practicable. The method may be associated with, for example, the device under test  300  illustrated in FIG. 3.  
         [0022]    At  402 , test information is sequenced from the cache structure  320  to the processor core  310  via input paths associated with the bus. For example, the sequencer  300  may receive test information from a particular address in the cache structure  320  and use the received information to drive the input paths via the multiplexer  340 . The test information may comprise, for example, test pattern information or test stimuli associated with a system bus trace. The test information may also include mask information indicating which output paths will contain valid information.  
         [0023]    The processor core  310  would then process the information received via the input paths (perhaps using the first portion  322  of the cache structure  320 ) and generate information that is provided via the output paths.  
         [0024]    At  404 , information from the processor core  310  is accumulated via output paths associated with the bus. For example, the result accumulator  360  may receive the information from the processor core  310  along with mask information from the sequencer  330 . Based on the received information, the result accumulator may update a locally stored value (e.g., a signature associated with a test result).  
         [0025]    The process illustrated in FIG. 4 may be repeated for additional lines of information in the cache structure  320  (with the result accumulator  360  continuing to update the signature). When the evaluation is complete, the value in the result accumulator  360  may be compared to a pre-determined value (e.g., after being read by a structural tester) to determine if the device under test  300  is operating properly. Note that the input paths and the output paths used by the DFT logic may represent substantially the entire bus. Also note that during the evaluation information may be exchanged over the input and output paths at substantially the full speed of the bus (although the loading of test information into the cache structure  320  and the reading of test result information from the result accumulator  360  may be performed using less than the entire bus and at a slower speed).  
       EXAMPLE  
       [0026]    [0026]FIG. 5 is an information flow diagram  500  in accordance with an example of the present invention. At (A), the Test RAM (TRAM)  324  is loaded with test information. For example, a structural tester might load test information into the TRAM via a test bus that comprises substantially fewer pins as compared to a processor&#39;s entire FSB (e.g., a processor having a 300-pin FSB might be tested using a 128-pin or 32-pin test bus). Note that the test information may be loaded in a mode at a speed less than the full speed of the FSB.  
         [0027]    The information stored in the TRAM  324  may include, for example, input pin information (e.g., associated with a system bus trace) and strobe information that indicates whether or not each output pin will contain valid information. By way of example, consider a FSB having four pins: P 1  (output), P 2  (input), P 3  (input), and P 4  (output). In this case, a line of cache information in the TRAM  324  might indicate “N01S” where: “N” (no strobe) indicates that the value of P 1  should ignored; “01” indicates that P 2  and P 3  should be driven to “0” and “1” respectively; and “S” (strobe) indicates that the value of P 4  should be accumulated. Note that the expected value of output pin P 4  might not be stored in the TRAM  324 . Also note that “S” or “N” may be stored using a binary value.  
         [0028]    At (B), the sequencer  330  provides address information to select a line of information in the TRAM  324  (e.g., the sequencer  330  may drive TRAM  324  address lines to sequentially select successive lines from the TRAM  324 ).  
         [0029]    The selected line of information is then sent from the TRAM  324  to the sequencer  330  at (C). The information sent from the TRAM  324  to the sequencer  330  may include, for example, input pin information that the sequencer  330  routes to the multiplexer  340  at (D). In the previous example, “N01S” might be sent from the TRAM  324  to the sequencer  330 . In this case, the sequencer  330  would route “01” to the multiplexer  340  (for eventual delivery to the processor core  310  via input paths associated with P 2  and P 3 ).  
         [0030]    At (E), the sequencer  330  provides the strobe information to the result accumulator  360  (e.g., so that only valid information will be accumulated). In this example, the sequencer  330  would route “N” and “S” to the result accumulator  360  to indicate that valid test information should be captured and accumulated via an output path associated with P 4 .  
         [0031]    The multiplexer  340  routes the input pin information (e.g., “01”) to the processor core  310  at (F). The processor core  310  may then execute instructions and process information accordingly. As a result, the processor core  310  generates and provides output pin information to the result accumulator  360  at (G). Based on the output pin information and the strobe information, the result accumulator updates a test signature as appropriate. For example, the result accumulator  360  might AND m strobe bits (e.g., each representing “S” or “N”) with associated output pin information and update a test signature via a MISR.  
         [0032]    The process may be repeated for additional lines of information in the cache structure  320  (with the result accumulator  360  continuing to update the test signature). When the evaluation is complete, the value in the result accumulator  360  may be read by the structural tester (e.g., via the test bus) to determine if the device under test is operating properly.  
         [0033]    Structural Tester  
         [0034]    [0034]FIG. 6 is a diagram including a device under test  300  and a structural tester  600  according to some embodiments. The structural tester  600  may comprise, for example, an Automated Test Equipment (ATE) device. Note that the structural tester  600  exchanges information with the device under test  300  via a test bus  610  having paths (i.e., input and output paths) that represent substantially less than the total number of paths that comprise the bus  370  of the device under test  300 .  
         [0035]    According to some embodiments, the structural tester  600  includes a test information portion  620  that provides test information adapted to be stored in a cache structure  320  of the device under test  300 . For example, the test information portion  620  may store input test information (e.g., associated with input paths) adapted to be stored in lines of the cache structure  320 . The test information portion  620  may also store mask information (e.g., strobe information indicating which output paths will contain valid information) and/or address sequencing information.  
         [0036]    The structural tester  600  may also include a test result portion  630  that receives from the device under test  300  information associated with a test result. For example, the test result portion  630  may receive a test signature from the device under test  300 . The test result portion  630  may also compare the test signature to a pre-determined signature to determine whether or not the device under test  300  is operating properly. According to other embodiments, the device under test  300  performs this comparison instead (e.g., and reports a simple pass or fail indication to the structural tester  600 ).  
         [0037]    [0037]FIG. 7 is a flow chart of a structural tester method according to some embodiments. The method may be performed, for example, by the structural tester  600  illustrated in FIG. 6. At  702 , test information is provided to a device under test  300 , the test information being adapted to be stored in a cache structure  320  located in the device under test  300 . For example, the test information portion  620  of the structural tester  600  may transmit the test information via the test bus  610 .  
         [0038]    At  704 , information associated with a test result is received from the device under test  300 . For example, the test result portion  630  of the structural tester  600  may receive a test signature via the test bus  610 .  
         [0039]    Test Information Generation  
         [0040]    [0040]FIGS. 8 and 9 are flow charts illustrating methods of generating test information according to some embodiments. The methods may be performed, for example, by the structural tester  600  illustrated in FIG. 6 or some other device.  
         [0041]    Referring now to FIG. 8, trace information associated with a bus is determined at  802 . For example, system trace information may be captured from a processor&#39;s FSB during normal operation. At  804 , the trace information is converted into test input information (e.g., information associated with input paths of the FSB) that is adapted to be stored in a cache structure  320  located in a device under test  300 . For example, the trace information may be re-formatted so as to represent lines in the cache structure  320 .  
         [0042]    At  806 , mask information is generated based on the trace information. Note that the test input information and the mask information might be combined (e.g., and both may be stored in a line in the cache structure  320 ).  
         [0043]    According to some embodiments, address sequencing information is also generated. For example, it might be that the test input information and mask information are not stored in sequential lines of the cache structure  320 . In this case, the address sequencing information may indicate an address of the cache structure  320  that should be accessed (e.g., by the sequencer  330 ).  
         [0044]    [0044]FIG. 9 is another illustration of a method of generating test information according to some embodiments. In particular, a functional test is performed at  902 . Note that the functional test may be associated with logic and instructions that are designed to ensure that a device under test  300  is operating properly, and may include, for example, interrupts, snoops, cache misses, and cache flushes.  
         [0045]    At  904 , a trace for a virtual Functional Test (FT) ATE device is generated (e.g., including full or substantially full pin access). That is, the appropriate value of each input path and certain output paths may be determined. By way of example, each functional test vector might have at least one bit associated with each pin of the processor. For an input pin, the bit value would be set to the input value to be driven during the test. For an output pin, one bit may represent an expected value and another bit may represent a strobe value (e.g., a value that indicates whether or not that output pin should be observed in that clock cycle).  
         [0046]    At  906 , the functional test trace is converted to a TRAM trace and sequencer RAM and control information. For example, a software application may convert a functional test vector so that information can be stored appropriately in on-die memory.  
         [0047]    Consider a TRAM that has N bytes in each cache line. In this case, the N bytes may be split into k bytes of input pin information and m bytes of strobe information. As a result, each TRAM cache line can represent 8*k FSB input pins and 8*m FSB output pins to be observed. The sequencer RAM and control information may be associated with address sequencing information.  
         [0048]    A TRAM cache image  908  and a sequencer RAM and control image  910  are then generated and a trace generator for a Structural Tester (ST) ATE device accesses the images at  912  to create a structural tester trace  914 . The structural tester trace  914  may then be loaded into and used by a structural tester  600  in accordance with embodiments of the present invention.  
         [0049]    Additional Embodiments  
         [0050]    The following illustrates various additional embodiments. These do not constitute a definition of all possible embodiments, and those skilled in the art will understand that many other embodiments are possible. Further, although the following embodiments are briefly described for clarity, those skilled in the art will understand how to make any changes, if necessary, to the above description to accommodate these and other embodiments and applications.  
         [0051]    For example, some embodiments have been described wherein an on-die cache structure stores test information. According to other embodiments, however, an off-die memory structure instead stores the test information. Consider, for example, a Multi-Chip Module (MCM). In this case, a memory structure on one chip may store test information that can be used to evaluate the performance of another chip (or the entire MCM).  
         [0052]    In addition, although software or hardware may have been described as performing particular functions herein, such functions could be performed using either software or hardware—or a combination of software and hardware (e.g., a medium may store instructions adapted to be executed by a processor to perform a method of facilitating an evaluation of a device under test).  
         [0053]    The several embodiments described herein are solely for the purpose of illustration. Persons skilled in the art will recognize from this description other embodiments may be practiced with modifications and alterations limited only by the claims.