Abstract:
In a computer simulation method for a semiconductor device, temporal changes in internal physical quantities such as electrostatic potential, electron density, and hole density in a semiconductor device upon application of a pulse voltage are obtained by transient analysis. AC signal analysis is performed by inputting a small RF AC voltage, assuming various physical quantities obtained at each time are in a pseudo steady state. The junction capacitance in the semiconductor device is calculated. These steps are repeatedly performed until a predetermined analysis time is reached to obtain transient temporal changes in junction capacitance.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of copending application Ser. No. 09/108,406, filed Jul. 1, 1998 abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a computer simulation method for the electrical characteristics of semiconductor devices and, more particularly, to a numerical simulation method for the transient response characteristics of junction capacitance. 
     2. Description of the Related Art 
     According to a conventional computer simulation method for the electrical characteristics of semiconductor devices, as described in Ryo Dan, ed., “Techniques for Process Device Simulations”, pp. 91-134, the region to be analyzed is divided into a mesh pattern, and the Poisson equation, electron current continuity equation, and hole current continuity equation are discretized at the respective mesh points. Further, these equations are linearized to obtain simultaneous linear equations by, e.g., the Newton method. These simultaneous linear equations are calculated to obtain solutions. 
     In addition to this general device simulation, there are methods of calculating PN junction capacitance and Schottky junction capacitance in a device by a numerical simulation, such as small-AC-signal analysis described in, e.g., Section “Sinusoidal Steady-State Analysis (S 3 A) ”, p. 2,032 in Steven E. Laux, “Techniques for Small-Signal Analysis of Semiconductor Devices”, IEEE Trans. Electron Devices, Vol. 32, No. 10, pp. 2,028-2,037. This analysis will be explained briefly. In the small-AC-signal analysis, junction capacitance or the like is calculated to obtain a DC solution at a desired operating point. More specifically, equations (1) to (3) below are equivalent to equations (3.41)-(3.43) in “Techniques for Process Device Simulations”, pp. 105-106 cited earlier: 
     
       
           F (ψ, n,p )=0  (1) 
       
     
     
       
           G (ψ, n,p )=0  (2) 
       
     
     
       
           H (ψ, n,p )=0  (3) 
       
     
     where 
     
       
           F (ψ, n,p )=∇(ε·∇ψ)+ q ( p−n+N   D   −N   A )  (4) 
       
     
                     G        (     ψ   ,   n   ,   p     )       =         ∂   n       ∂   t       +       G   0          (     ψ   ,   n   ,   p     )                 (   5   )                                G   0 (ψ, n,p )=∇(μ n   n∇ψ−D   n   ∇n )− GR ( n,p )  (6) 
                     H        (     ψ   ,   n   ,   p     )       =         ∂   p       ∂   t       +       H   0          (     ψ   ,   n   ,   p     )                 (   7   )                                H   0 (ψ, n,p )=−∇(μ p   p∇ψ+D   p   ∇p )− GR ( n,p )  (8) 
     are solved for                  ∂   n       ∂   t       =   0           (   9   )                   ∂   p       ∂   t       =   0           (   10   )                                
     to calculate the potential, electron density, and hole density by 
     
       
         ξ 0 =(ψ 0   ,n   0   ,p   0 )  (11) 
       
     
     where ψ is the electrostatic potential, n is the electron density, p is the hole density, ε is the permittivity, q is the unit charge, N D  is the donor density, N A  is the acceptor density, μ n  and μ p  are the electron and hole mobilities, D n  and D p  are the electron and hole diffusion constants, and GR is the generation/recombination term of an electron/hole. Assume that a small AC bias with an angular frequency ω and an amplitude {tilde over (V)} is superposed on a DC bias V at the operating point, and the potential, electron density, and hole density in this state respond in a manner given by 
     
       
         ξ=ξ 0 +{tilde over (ξ)} exp  jωt   (12) 
       
     
     
       
         {tilde over (ξ)}=({tilde over (ψ)},ñ,{tilde over (p)})  (13) 
       
     
     Substituting the response in equation (12) into equations (1) to (8) and Taylor-expanding each term using 
     
       
         ∥{tilde over (ξ)}∥&lt;∥ξ 0 ξ 
       
     
     and 
     
       
           F (ψ 0   ,n   0   ,p   0 )=0  (14) 
       
     
     
       
           G   0 (ψ 0   ,n   0   ,p   0 )=0  (15) 
       
     
     
       
           H   0 (ψ 0   ,n   0   ,p   0 )=0  (16) 
       
     
     yields equations (17) below equivalent to equation (10) in “Techniques for Small-Signal Analysis of Semiconductor Devices”, p. 2,032                 (             ∂   F       ∂   ψ               ∂   F       ∂   n               ∂   F       ∂   p                   ∂     G   0         ∂   ψ               j                 ω                 t     +       ∂     G   0         ∂   n                 ∂     G   0         ∂   p                   ∂     H   0         ∂   ψ               ∂     H   0         ∂   n               j                 ω                 t     +       ∂     H   0         ∂   p               )                     (           ψ   ~               n   ~               p   ~           )       =     (           V   ~             0           0         )             (   17   )                                
     By solving equation (17), the complex amplitude {tilde over (ξ)} of potential, electron density, and hole density is obtained. Assuming that each element of the coefficient matrix is an equivalent conductance, the conductance current component of a response AC current at a device electrode is obtained by the product of the equivalent conductance coupled to the device electrode and defined on a mesh branch, and the complex amplitude across the mesh points on the ends of the branch. By adding the displacement current component        ɛ          ∂     (     ∇   φ     )         ∂   t                              
     to the conductance current component, the total response AC current Ĩ is obtained. Using this, the capacitance component viewed from the device electrode is given by              C   =       I   ~       ω                   V   ~                 (   18   )                                
     FIG. 1 is a flow chart showing the processing procedure of this method. In step  301 , a DC bias to be applied to a device is set. In step  302 , internal physical quantities such as potential, electron density, and hole density at the current operating point are calculated by steady-state analysis. In step  303 , the frequency of a small RF voltage to be applied to the device is set. In step  304 , a perturbation equation for a small RF AC component is solved to obtain the complex amplitude of a small AC response component of the internal physical quantity. In step  305 , the small AC component of an electrode current is calculated from the complex amplitude obtained in step  304 , and the junction capacitance viewed from the electrode is calculated using the result. Instep  306 , whether AC analysis is complete for all frequencies set in advance is checked. In step  307 , whether analysis is complete for all DC bias voltages set in advance is checked. 
     The above description concerns simulation for junction capacitance in a steady state. In addition, there is an experimental method of measuring transient changes in junction capacitance, such as DLTS described in, e.g., Takashi Katoda, ed., “Evaluation Techniques for Semiconductors”, pp. 245-247. According to this method, after a step voltage pulse is applied to a device electrode, a small RF voltage of about 1 MHz is applied to the device, and the phase difference with an RF current flowing at that time is continuously observed to measure temporal changes in junction capacitance. No concrete conventional technique has been proposed about this experimental numerical simulation. However, transient changes in capacitance can be numerically simulated by applying the Fourier analysis of transient analysis results which is described in Section “Fourier Decomposition of Transient Excitations (FD)”, pp. 2,029-2,030 in Steven E. Laux, “Techniques for Small-Signal Analysis of Semiconductor Devices”, IEEE Trans. Electron Devices, Vol. 32, No. 10, pp. 2,028-2,037. More specifically, similar to an actual experiment, an input waveform prepared by superposing a step voltage pulse on a small RF voltage is applied to a device electrode, and transient changes in capacitance are calculated using the transient response current waveform by transient analysis of the device simulation. In transient analysis, an equation describing changes in charged state of a deep impurity level that cause transient changes in junction capacitance is added to equations (1) to (7). These equations are discretized including the time differential terms. The response waveform is divided by time windows using the reciprocal of the frequency of the small RF voltage. Fourier analysis is performed in each window to obtain the average capacitance component in each window. The average capacitance components are combined to obtain final temporal changes in capacitance. 
     FIG. 2 is a schematic view showing the outline of this method. FIG. 2 schematically shows the case wherein a voltage waveform  402  prepared by superposing a small RF AC voltage on a pulse voltage is directly input and subjected to transient analysis, and a junction capacitance  405  of a device  401  is obtained by Fourier analysis  404  of a response current waveform  403  and the input waveform  402 . 
     The above method of numerically simulating the transient response of capacitance by transient analysis and subsequent Fourier analysis has a problem of a large calculation amount. In general, the transient response time constant of capacitance that is processed by DLTS measurement and the like falls within the range of several msec to several sec. To the contrary, capacitance measurement is generally performed by an RF voltage of 1 MHz. To perform Fourier analysis with satisfactory precision using a time window of about 10 −6  sec, transient analysis must be performed at a time step width of about 10 −7  sec. Therefore, simulating all transient responses requires about 10 4  to 10 7  analysis points, resulting in a long calculation time. 
     SUMMARY OF THE INVENTION. 
     The present invention has been made to solve the conventional drawbacks, and has as its object to provide a computer simulation method for semiconductor devices in which the transient response of junction capacitance in a semiconductor device can be numerically simulated with a small calculation amount at a high speed. 
     To achieve the above object, according to the main aspect of the present invention, there is provided a computer simulation method for a semiconductor device, comprising the steps of (a) obtaining, by transient analysis, a temporal change in internal physical quantity including an electrostatic potential, an electron density, and a hole density in a semiconductor device upon application of a pulse voltage, (b) performing AC signal analysis by inputting a small RF AC voltage, assuming various physical quantities obtained at each time are in a pseudo steady state, and (c) calculating junction capacitance in the semiconductor device, the steps (a), (b), and (c) being repeatedly performed until a predetermined analysis time is reached to obtain a transient temporal change in junction capacitance. 
     According to the method of the present invention, after changes in physical quantities in a device upon application of a pulse voltage are obtained by transient analysis, small-AC-signal analysis is performed assuming the physical quantities are in a pseudo steady state at each analysis time. In the conventional method, a small RF voltage waveform is actually input to perform transient analysis. Accordingly, 10 4  to 10 7  analysis points are necessary to obtain a transient response with a time constant of 10 −3  to 1 sec. In the present invention, however, since the capacitance value can be obtained by one AC analysis for each time, the total number of analysis points can be suppressed to such a degree as to express the transient response of capacitance, e.g., to 10 points per transient response time constant, which is two to three orders of magnitude smaller than the conventional case. Assumption of a pseudo steady state in the present invention gives a good approximation as far as the response time constant of junction capacitance is much larger than the reciprocal of the frequency of the small RF voltage, and no problem occurs under normal experimental conditions. 
    
    
     The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principles of the present invention are shown by way of illustrative example. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a flow chart showing the processing procedure in conventional AC analysis; 
     FIG. 2 is a schematic view showing a method of calculating the transient response characteristics of a junction capacitance using the conventional method; 
     FIG. 3 is a flow chart showing the processing procedure of a computer simulation method for semiconductor devices according to the first embodiment of the present invention; and 
     FIG. 4 is a flow chart showing the processing procedure of a computer simulation method for semiconductor devices according to the second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Several preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. 
     FIG. 3 is a flow chart showing the processing procedure of a computer simulation method for semiconductor devices according to the first embodiment of the present invention. 
     In step  101 , a pulse voltage to be applied to a device is set. In step  102 , the transient analysis time is updated. As described earlier, the time step width is set to a fraction of the transient response time constant of capacitance. In step  103 , internal physical quantities such as potential, electron density, and hole density at the current operating point are calculated by transient analysis. In step  104 , the frequency of a small RF voltage to be applied to the device is set. In step  105 , assuming that the system is in a pseudo steady state, small-AC-signal analysis is performed by inputting a small RF AC voltage, thereby obtaining the complex amplitude of a small AC response component of the internal physical quantity. Instep  106 , the small AC component of an electrode current is calculated from the complex amplitude obtained in step  105 , and the junction capacitance viewed from the electrode is calculated using the result. In step  107 , whether AC analysis is complete for all frequencies set in advance is checked. If YES in step  107 , the flow advances to step  108 ; otherwise, to step  104 . 
     In step  108 , whether transient analysis is complete is checked. If NO in step  108 , the flow returns to step  102 ; otherwise, the entire processing ends. 
     In transient analysis of step  103 , 
     
       
           F   TR (ψ i   ,n   i   ,p   i   ,f   i )=0  (19) 
       
     
     
       
           G   TR (ψ i   ,n   i   ,p   i   ,f   i   ,n   i−1 )=0  (20) 
       
     
     
       
           H   TR (ψ i   ,n   i   ,p   i   ,f   i   ,p   i−1 )=0  (21) 
       
     
     
       
           I   TR ( n   i   ,p   i   ,f   i   ,f   i−1 )=0  (22) 
       
     
     where 
     
       
           F   TR (ψ i   ,n   i   ,p   i   ,f   i )=∇(ε·∇ψ i )+ q[p   i   −n   i   +N   D   −N   A   +N   T (1 −f   i )]  (23) 
       
     
                       G   TR          (       ψ   i     ,     n   i     ,     p   i     ,     f   i     ,     n     i   -   1         )       =           n   i     -     n     i   -   1           Δ                 t       +       G   S          (       ψ   i     ,     n   i     ,     p   i     ,     f   i       )                 (   24   )                                G   s (ψ i   ,n   i   ,p   i   ,f   i )=∇(μ n   n   i ∇ψ i   −D   n   ∇n   i )− GR ( n   i   ,p   i )− N   T   [e   n   f   i   −n   i   C   n (1 −f   i )]  (25) 
                       H   TR          (       ψ   i     ,     n   i     ,     p   i     ,     f   i     ,     p     i   -   1         )       =           p   i     -     p     i   -   1           Δ                 t       +       H   S          (       ψ   i     ,     n   i     ,     p   i     ,     f   i       )                 (   26   )                                H   s (ψ i   ,n   i   ,p   i   ,f   i )=−∇(μ p   p   i ∇ψ i   +D   p   ∇p   i )− GR ( n   i   ,p   i )− N   T   [e   p (1 −f   i )− p   i   C   p   f   i ]  (27) 
                       I   TR          (       n   i     ,     p   i     ,     f   i     ,     f     i   -   1         )       =           f   i     -     f     i   -   1           Δ                 t       +       I   S          (       n   i     ,     p   i     ,     f   i       )                 (   28   )                                I   s ( n   i   ,p   i   ,f   i )= e   n   f   i   −n   i   C   n (1 −f   i )− e   p (1 −f   i )+ p   i   C   p   f   i   (29) 
     (where suffix i is the physical quantity at the current time, suffix (i−1) is the physical quantity at the immediately preceding time, N T  is the density of a deep impurity level which causes transient changes in junction capacitance, and f is the electron occupation probability) are solved. The equation I is a rate equation which describes temporal changes in charged state of the deep impurity level, where e n  and e p  are the electron and hole emission rates, and C n  and C p  are the electron and hole trapping coefficients. 
     In the first embodiment, the entire integration on the time axis is performed using the backward Euler method. Instead, the Crank-Nicholson method or the like can also be employed. In AC analysis of step  105 , by solving                ξ   ~     =     (       ψ   ~     ,                n   ~     ,                p   ~       )                                 (             ∂   F       ∂   ψ               ∂   F       ∂   n               ∂   F       ∂   p               ∂   F       ∂   f                   ∂     G   S         ∂   ψ               j                 ω                 t     +       ∂     G   S         ∂   n                 ∂     G   S         ∂   p               ∂     G   S         ∂   f                   ∂     H   S         ∂   ψ               ∂     H   S         ∂   n               j                 ω                 t     +       ∂     H   S         ∂   p                 ∂     G   S         ∂   f                               ∂     I   S         ∂   n               ∂     I   S         ∂   p                                ω                 t     +       ∂     I   S         ∂   f               )                     (           ψ   ~               n   ~               p   ~             f         )       =     (           V   ~             0           0           0         )             (   30   )                                
     the complex amplitude of the internal physical quantity is obtained. 
     If the frequency of the small AC voltage is too high to follow changes in charged state of the deep impurity level, eliminating the equation for f from equation (30) and solving                  (             ∂   F       ∂   ψ               ∂   F       ∂   n               ∂   F       ∂   p                   ∂     G   S         ∂   ψ               j                 ω                 t     +       ∂     G   S         ∂   n                 ∂     G   S         ∂   p                   ∂     H   S         ∂   ψ               ∂     H   S         ∂   n               j                 ω                 t     +       ∂     H   S         ∂   p               )                     (           ψ   ~               n   ~               p   ~           )       =     (           V   ~             0           0         )             (   31   )                                
     yields the results we wanted. 
     The second embodiment of the present invention will be described with reference to the accompanying drawings by exemplifying numerical simulation of actual DLTS measurement. FIG. 4 is a flowchart of a transient response simulation method for junction capacitance according to the second embodiment of the present invention. 
     In step  201 , a pulse voltage to be applied to a device is set. Instep  202 , the analysis temperature is updated. In DLTS, the temperature is swept normally within the range of 77 K to 300 K. In general, since the initial state such as the initial electron occupation probability of a deep impurity level depends on temperature, this loop cannot be set in the time update loop of transient analysis. In step  203 , the transient analysis time is updated. In step  204 , internal physical quantities such as potential, electron density, and hole density at the current operating point are calculated by transient analysis. In step  205 , the frequency of a small RF voltage to be applied to the device is set. In step  206 , postulating the system is in a pseudo steady state, small-AC-signal analysis is performed by inputting a small RF AC voltage, thereby obtaining the complex amplitude of a small AC response component of the internal physical quantity. In step  207 , the small AC component of an electrode current is calculated from the complex amplitude obtained in step  206 , and the junction capacitance viewed from the electrode is calculated using the result. In step  208 , whether AC analysis is complete for all frequencies set in advance is checked. If YES in step  208 , the flow advances to step  209 ; otherwise, to step  205 . In step  209 , whether transient analysis is complete is checked. If NO in step  209 , the flow returns to step  203 ; otherwise, to step  210 . In step  210 , whether analysis is complete for the entire temperature range set in advance is checked. If NO in step  210 , the flow shifts to step  202 ; otherwise, the entire processing ends. 
     The capacitance difference between two sampling times is extracted from temporal changes in junction capacitance obtained by the second embodiment. The changes in temperature are used to write a graph to obtain DLTS spectrum calculation values.