Abstract:
Single-phase full bridge boost converter systems and methods are provided. One system includes a direct-quatrature (D-Q) control system configured to generate a control voltage (v con ) including direct-phase and quadrature-phase voltage components. The system also includes a comparator configured to compare v con  to a carrier waveform voltage, generate switching commands based on the comparison, and transmit the switching commands to a current switch. Another system includes a boost converter including multiple switches coupled to a load and an AC voltage source. The switches are configured to provide charging current to the load in response to receiving switching commands. A D-Q control system configured to receive and delay an i a  value, and issue switching commands based on the i a  and delayed i a  value is also included. A method includes performing a D-Q conversion to generate DC current including direct-phase and quadrature-phase current components, and issuing switching commands based on the current components.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention generally relates to AC-to-DC power converters, and more particularly relates to single-phase full bridge boost converters and methods for charging a load coupled to a single-phase AC voltage source. 
       BACKGROUND OF THE INVENTION 
       [0002]    In the vector control approach for multi-phase converters, variables that vary with time (e.g., AC voltage and AC current) are transferred to the synchronous rotating direct-quatrature (D-Q) reference frame to enable the converter system to work with constant values instead of time varying values. D-Q transformations have been defined for multi-phase converter systems (e.g., two-phase and three-phase systems), but have not been defined for a single-phase system. 
         [0003]    Accordingly, it is desirable to provide single-phase full bridge boost converter systems. It is also desirable to provide methods for charging a load coupled to a single-phase AC voltage source. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention. 
       BRIEF SUMMARY OF THE INVENTION 
       [0004]    Systems are provided for issuing a switching to a single-phase full boost converter comprising a voltage sensor for detecting voltage in the DC side of the single-phase full bridge boost converter, a current sensor for detecting alternating current in the AC side of the single-phase full bridge boost converter, and a plurality of switches configured to control the alternating current. One exemplary system comprises a direct-quatrature (D-Q) control system configured to be coupled to the voltage sensor and the current sensor, and further configured to generate a control voltage (v con ) comprising a direct-phase voltage component and a quadrature-phase voltage component. The system also comprises a comparator coupled to the D-Q control system and configured to be coupled to the switch and to a waveform reference voltage (v tri ) source. In this embodiment, the comparator further configured to compare v con  to v tri , generate the switching command based on the comparison of v con  and v tri , and transmit the switching command to the switch. 
         [0005]    Systems for charging a load are also provided. An exemplary system comprises a single-phase full bridge boost converter comprising a plurality of switches coupled to a load and an AC voltage source. The switches are configured to provide charging current to the load in response to receiving switching commands. The system also comprises a direct-quadrature (D-Q) control system coupled to the single-phase full bridge boost converter, wherein the D-Q control system is configured to receive a first AC current (i a ) value from the single-phase full bridge boost converter; delay the i a  value to generate a second AC current (i b ) value; and issue the switching commands based on the i a  and i b  values. 
         [0006]    Methods for charging a load in a single-phase full bridge boost converter comprising a plurality of switches coupled to the load, alternating current (i a ), and a voltage (v) are also provided. One exemplary method comprises the steps of performing a direct-quadrature conversion to the i a  to generate a direct current including a direct-phase current (i d ) component and a quadrature-phase current (i q ) component, and issuing a switching command to the switch based on the i d  component and the i q  component. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and 
           [0008]      FIG. 1  is a block diagram of a prior art single-phase full bridge boost converter; 
           [0009]      FIG. 2  is a schematic diagram of a prior art two-phase full bridge boost converter connected to a direct-quadrature (D-Q) control system; 
           [0010]      FIG. 3  is a diagram of one exemplary embodiment of a D-Q control system for use with the single-phase full bridge boost converter of  FIG. 1 ; 
           [0011]      FIG. 4  is a schematic diagram representing a “real” phase and an “imaginary” phase in a two-phase balance system; 
           [0012]      FIG. 5  is a diagram representative of the transformation between a two-phase reference frame and a D-Q reference frame; 
           [0013]      FIG. 6  is a diagram representative of the voltage and current vectors of the converter of  FIG. 1  in the D-Q reference frame of  FIG. 5 ; and 
           [0014]      FIG. 7  is a block diagram of one exemplary embodiment of a system for charging a load comprising the single-phase full bridge boost converter of  FIG. 1  and the D-Q control system of  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention. 
         [0016]      FIG. 1  is a schematic diagram of a prior art single-phase full bridge boost converter (hereinafter “converter”)  100  connected to an AC voltage source  110 . Converter  100  includes a node  122  connected to the negative terminal of AC voltage source  110  and an inductor  115  connected to the positive terminal of AC voltage source  110  and to a node  124 . 
         [0017]    Converter  100  also includes diodes  140 ,  145 ,  150 , and  155 . Diode  140  includes an anode connected to node  124  and a cathode connected to a node  126 . Diode  145  includes a cathode connected to node  126  and an anode connected to a node  128 , which is also connected to node  122 . Diode  150  includes a cathode connected to node  128  and an anode connected to a node  130 , which is also connected to a node  132  and to ground. Diode  155  includes a cathode connected to a node  136  connected to node  124 , and an anode connected to node  132 , which is connected to a node  134 . 
         [0018]    Also included in converter  100  are switches (e.g., semiconductor switches)  160  and  165 . Switch  160  is coupled to nodes  134  and  136 , which is antiparallel with diode  155 . Likewise, switch  165  is coupled to nodes  122  and  130 , which is antiparallel with diode  150 . 
         [0019]    Converter  100  further includes a capacitor  170  coupled in parallel with a load (e.g., a battery)  175 . Specifically, the negative terminal of both capacitor  170  and load  175  are connected to a node  139  that is also connected to node  134 . The positive terminal of both capacitor  170  and load  175  are connected to a node  138  that is also connected to node  126 . 
         [0020]    During operation, converter  100  uses four modes of operation to charge load  175 . That is, converter  100  provides current to load  175  from AC voltage source  110  or from capacitor  170  depending on the mode of operation. Specifically, mode  1  occurs when the AC voltage from AC voltage source  110  is positive and switches  160 ,  165  are both OFF. When operating in mode  1 , current flows through inductor  115 , diode  140 , capacitor  170 , load  175 , and returns back through diode  150 . 
         [0021]    Mode  2  occurs when the AC voltage is positive and switches  160 ,  165  are both ON. When operating in mode  2 , current flows through switch  160  and back through diode  150 . At the same time, capacitor  170  discharges and supplies current to load  175 . 
         [0022]    Mode  3  occurs when the input AC voltage is negative and switches  160 ,  165  are both OFF. When operating in mode  3 , current flows through diode  145 , capacitor  170 , load  175 , and back through diode  155  and inductor  115 . 
         [0023]    Mode  4  occurs when the input AC voltage is negative and switches  160 ,  165  are both ON. When operating in mode  4 , current flows through switch  165  and back through diode  155  and inductor  115 . At the same time, capacitor  170  discharges and supplies current to load  175 . 
         [0024]      FIG. 2  is a diagram of a prior art two-phase full bridge boost converter (hereinafter “converter”)  200  connected to a D-Q control system (hereinafter “system”)  300 . Converter  200  includes an A-phase and a B-phase that are each similar to converter  100  discussed above with reference to  FIG. 1 . 
         [0025]    System  300  is configured to issue switching commands to the plurality of switches in converter  200 . That is, system  300  is based on transforming a two-phase balance system from a time-varying frame to a synchronous frame. 
         [0026]    As illustrated in  FIG. 2 , system  300  includes a phase-locked loop (PLL)  103  coupled to a sine function  105  and a cosine function  107 . PLL  103  may be any hardware and/or device capable of maintaining a phase angle (θ). Sine function  105  is configured to determine the sine function value of θ (i.e., the sin θ value), and cosine function  107  is configured to determine the cosine function value of θ (i.e., the cos θ value). 
         [0027]    System  300  also includes comparators (e.g., operational amplifiers)  112 ,  114 ,  116 ,  118 , and  178 , controllers  143 ,  146 , and  149 , multipliers  120 ,  121 ,  123 ,  125 ,  127 ,  129 ,  173 , and  175 , adders  131  and  133 , and subtractors  171  and  180 . Specifically, comparator  112  is coupled to controller  143  and to a voltage sensor  293  configured to detect a DC voltage (v dc ) in converter  200 , and to a DC reference voltage source (not shown) that is configured to supply a constant (or substantially constant) DC reference voltage (v dc-ref ). Comparator  112  is configured to compare the difference between v dc  and v dc-ref  to determine a voltage error in converter  200  and transmit the determined voltage error to controller  143 . 
         [0028]    Controller  143  may be any hardware and/or device (e.g., a PI controller) capable of generating a signal representing a reference quadrature-phase current (i q-ref ) value from the determined voltage error. In one embodiment, controller  143  is configured to receive the voltage error from comparator  112  and determine an i q-ref  value that, if applied to converter  200 , would cause v dc  to equal v dc-ref . Controller  143  is coupled to comparator  114  and is configured to transmit determined i q-ref  values to comparator  114 . 
         [0029]    Comparator  114  is also coupled to subtractor  180  (discussed below), which supplies a quadrature-phase current (i q ) value to comparator  114 . Comparator  114  is configured to compare the i q  value with the i q-ref  value to determine a quadrature-phase current error. Comparator  114  is further coupled to controller  146  and is configured to transmit the determined quadrature-phase current error to controller  146 . 
         [0030]    Controller  146  may be any hardware and/or device (e.g., a PI controller) capable of generating a quadrature-phase voltage (v q ) value based on the quadrature-phase current error. Controller  146  is also coupled to multipliers  120  and  173 , and is configured to transmit the generated v q  value to multipliers  120  and  173 . 
         [0031]    Multiplier  120 , in addition to being coupled to controller  146 , is coupled to sine function  105  and is configured to multiply the v q  value supplied by controller  146  and the sin θ value supplied by sine function  105  to generate a v q  sin θ value. Multiplier  120  is also coupled to adder  133  (discussed below) and is configured to transmit the v q  sin θ value to adder  133 . 
         [0032]    Multiplier  173  is also coupled to cosine function  107  and is configured to multiply the v q  value supplied by controller  146  and the cos θ value supplied by cosine function  107  to generate a v q  cos θ value. Multiplier  173  is also coupled to subtractor  171  (discussed below) and is configured to transmit the v q  cos θ value to subtractor  171 . 
         [0033]    Subtractor  180  is coupled to multipliers  121 ,  123  and is configured to receive values from multipliers  121 ,  123  and to subtract the value received from multiplier  123  from the value received from multiplier  121  to generate the i q  value. Specifically, subtractor  180  is configured to subtract an i b  cos θ value received from multiplier  123  from an i a  sin θ value received from multiplier  121  to generate an (i a  sin θ−i b  cos θ) value, which is the i q  value. 
         [0034]    Multiplier  121  is coupled to sine function  105  and a current sensor  290  that detects AC current (i a ) in the a-phase of converter  200 . Multiplier  121  is further configured to receive the sin θ value from sine function  105  and an i a  value from current sensor  290 , and multiply the sin θ value and the i a  value to generate the i a  sin θ value that is supplied to subtractor  180 . 
         [0035]    Multiplier  123  is coupled to cosine function  107  and a current sensor  295  that detects AC current (i b ) in the b-phase of converter  200 . Multiplier  123  is configured to receive a cos  0  value from cosine function  107  and an i b  value from current sensor  295 , and multiply the cos θ value and the i b  value to generate the i b  cos θ value that is supplied to subtractor  180 . 
         [0036]    Multiplier  125  is coupled to sine function  105  and current sensor  295 , and is configured to receive the i b  value from current sensor  295  and the sin θ value from sine function  105 . Multiplier  125  is further configured to multiply the i b  value and the sin θ value to generate an i b  sin θ component. Multiplier  125  is further coupled to adder  131  and is further configured to transmit the i b  sin θ component to adder  131 . 
         [0037]    Adder  131  is also coupled to multiplier  127  and is configured to receive an i a  cos θ component from multiplier  127  and the i b  sin θ component from multiplier  125 . Multiplier  127  is coupled to and configured to receive the cos θ value from cosine function  107 . Multiplier  127  is also coupled to current sensor  290  and is configured to receive the i a  value from the current sensor and multiply the cos θ value and the i a  value to generate an i a  cos θ component. 
         [0038]    Adder  131  is also configured to sum the i a  cos θ component and the i b  sin θ component to generate an (i a  cos θ+i b  sin θ) value, which is a direct-phase current (i d ) value. Adder  131  is further coupled to comparator  116  and is further configured to transmit the i d  value to comparator  116 . 
         [0039]    Comparator  116  is coupled to a direct-phase reference current source (not shown) and is configured to receive a direct-phase reference current (i d-ref ) value from the direct-phase reference current source. Comparator  116  is also configured to compare the i d  value supplied from adder  131  to the i d-ref  value to determine a direct-phase current error, and to transmit the determined direct-phase current error to controller  149 . 
         [0040]    Controller  149  is coupled to comparator  116  and is configured to receive the direct-phase current error from comparator  116 . Controller  149  is also configured to generate a direct-phase voltage (v d ) value based on the direct-phase current error. Controller  149  is also coupled to multipliers  129  and  175 , and is configured to transmit the generated v d  value to multipliers  129  and  175 . 
         [0041]    Multiplier  129  is also coupled to cosine function  107  and adder  133 , and is configured to receive the v d  value and the cos θ value from controller  149  and cosine function  107 , respectively. Multiplier  129  is further configured to multiply the v d  value and the cos θ value to generate a v d  cos θ value and transmit the v d  cos θ value to adder  133 . 
         [0042]    Adder  133  is coupled to multipliers  120 ,  129  and is configured to receive the v q  sin θ value and the v d  cos θ value from multipliers  120  and  129 , respectively. Adder  133  is further configured to sum the v q  sin θ value and the v d  cos θ value (v q  sin θ+v d  cos θ) to generate an A-phase control voltage (v conA ), and to transmit v conA  to comparator  118 . 
         [0043]    Multiplier  175  is coupled to sine function  105  and subtractor  171 , and is configured to receive the v d  value and the sin θ value from controller  149  and sine function  105 , respectively. Multiplier  175  is further configured to multiply the v d  value and the sin θ value to generate a v d  sin θ value and transmit the v d  sin θ value to subtractor  171 . 
         [0044]    Subtractor  171  is coupled to multipliers  175  and  173 , and is configured to receive the v d  sin θ value and the v q  cos θ value from multipliers  175  and  173 , respectively. Subtractor  171  is further configured to subtract the v d  sin θ value from the v q  cos θ value (v d  sin θ−v q  cos θ) to generate a B-phase control voltage (v conB ), and to transmit v conB  to comparator  178 . 
         [0045]    Comparator  118  is coupled to adder  133 , a triangular waveform reference voltage source (not shown), and to the plurality of switches in the A-phase of converter  200 . Comparator  118  is configured to receive v conA  from adder  133  and a triangular waveform reference voltage (v tri ) value from the triangular waveform reference voltage source, and compare v conA  and v tri  to generate switching commands for the plurality of switches in the A-phase based on the comparison (e.g., v conA &lt;v tri  or v conA &gt;v tri ). 
         [0046]    Similarly, comparator  178  is coupled to subtractor  171 , the triangular waveform reference voltage source, and to the plurality of switches in the B-phase of converter  200 . Comparator  178  is configured to receive v conB  from subtractor  171  and the v tri  value from the triangular waveform reference voltage source, and compare v conB  and v tri  to generate switching commands for the plurality of B-phase switches based on the comparison (e.g., v conB &lt;v tri  or v conB &gt;v tri ). The switching commands transmitted to the A-phase and B-phase switches are such that the switches in converter  200  turn ON/OFF such that i a  and i b  vary in a manner to properly charge a load (not shown) connected to converter  200 . 
         [0047]      FIG. 3  is a diagram of one exemplary embodiment of a D-Q control system (hereinafter “system”)  400  for use with converter  100  (see  FIG. 1 ). In the illustrated embodiment, system  400  comprises PLL  103 , sine function  105 , cosine function  107 , comparators  112 ,  114 ,  116 , and  118 , controllers  143 ,  146 , and  149 , multipliers  120 ,  121 ,  127 , and  129 , adders  131  and  133 , and subtractor  180  configured similar to system  300  discussed above with reference to  FIG. 2 . 
         [0048]    System  400  also comprises a delay function  785  coupled to multipliers  123  and  125  that is capable of being coupled to a current sensor (see current sensor  591  in  FIG. 7 ) in converter  100 . Delay function  785  may be any hardware and/or device capable of receiving a detected i a  value from the current sensor and applying a phase delay to the i a  value to generate the i b  value. In one embodiment, delay function  785  is configured to apply a 90 degree delay to i a  such that i b  is substantially orthogonal to the i a  detected by the current sensor. Delay function  785  is also configured to transmit the i b  value to multipliers  123  and  125  such that system  400  operates to provide switching commands to switches  160  and  165  in a manner similar to system  300  discussed above. 
         [0049]      FIG. 4  is a diagram representing a “real” phase and an “imaginary” phase in a two-phase balance system, wherein the imaginary phase is orthogonal to the real phase. Here, the imaginary phase includes reference numeral  785  similar to delay function  785  discussed above with reference to  FIG. 3 . Though delay function  785  is not the equivalent of the imaginary phase, the i b  value that delay function  785  generates (based in the i a  value) and provides to system  400  is the equivalent of the i b  value that system  300  receives from the b-phase of converter  200  via current sensor  295 . That is, because the two-phases in converter  200  are separated by  90  degrees, by delaying (via delay function  785 ) the i a  value in converter  100 , a single-phase full bridge boost converter is capable of functioning similar to a two-phase full bridge boost converter. The following discussion presents a mathematical explanation of system  400 . 
         [0050]      FIG. 5  represents the transformation between the two-phase and D-Q phase reference frames of converter  100  and system  400 , which reference frames are represented by the trigonometric relations given in equations (1) and (2). In addition, the voltage and current vectors of converter  100  in the D-Q reference frame are depicted in  FIG. 6 . 
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         [0051]    In equations (1) and (2), the variable “f′ can be defined as a set of voltages or currents in converter  100 . Based on  FIG. 6 , active and reactive power equations in the synchronous frame can be written as follows: 
         [0000]        P=v   d   i   d   +v   q   i   q    (3) 
         [0000]        Q=v   d   i   q   −v   q   i   d    (4) 
         [0052]    The q-axis is chosen to be aligned with the phase voltage vector of converter  100  or the “real” circuit, which means that the direct-phase voltage (v d ) is equal to zero (v d =0) and the quadrature-phase voltage (v q ) is equal to the magnitude of the grid voltage (v) in converter  100  (v q =|v|). With these v d  and v q  values, the equations for the active and reactive power can be simplified as: 
         [0000]        P=|v|i   q    (5) 
         [0000]        Q=−|v|i   d    (6) 
         [0053]    Since the grid voltage, |v|, is a constant, active and reactive power can be controlled by controlling the quadrature-phase current (i q ) and the direct-phase current (i d ), respectively. 
         [0054]    Using Kirchhoff&#39;s voltage law, the voltage equations in  FIG. 5  can be written as: 
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         [0055]    Transforming the voltage equations into the synchronous reference frame using equations (1) and (2), and considering that v d =0 and v q =|v|, equation (7) results in: 
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         [0056]    To provide decoupled control of active power or i q , and reactive power or i d , based on equation (8), the output voltages of converter  100  in the synchronous reference frame should be chosen as: 
         [0000]        e   q   =L ( x   1   −ωi   d )+| v|   (9) 
         [0000]        e   d   =L ( x   2   +ωi   q )   (10) 
         [0057]    By substituting equations (9) and (10) into equation (8), the decoupled equations of system  400  can be rewritten as follows: 
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         [0058]    As can be seen from equations (5) and (6), the active and reactive power may be controlled through i q  and i d , respectively. Therefore, the control rules of equations (9) and (10) can be completed by defining the current feedback loops as follows: 
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         [0000]    That is, system  400  is configured to issue switching commands to converter  100  consistent with equations (12) and (13). 
         [0059]      FIG. 7  is a block diagram of one exemplary embodiment of a system  500  for charging a load  175  (e.g., a battery). The various embodiments of system  500  enable active and reactive power in system  500  to be independently controlled by a V-Q transformation. 
         [0060]    As illustrated in  FIG. 7 , system  500 , at least in this embodiment, comprises system  400  integrated with converter  100 . In doing such, system  500  comprises a current sensor  591 , a voltage sensor  593 , a DC reference voltage source  595 , a direct-phase reference current source  597 , and a triangular waveform reference voltage source  599 . 
         [0061]    Current sensor  591  is coupled between AC voltage source  110  and inductor  115  of converter  100 , and is also coupled to multiplier  121 , multiplier  127 , and delay function  785  of system  400 . Current sensor  591  is configured to detect i a  in converter  100  and transmit the detected i a  value to each of delay function  785 , multiplier  121 , and multiplier  127 . 
         [0062]    Voltage sensor  593  is coupled in parallel with capacitor  170  via nodes  521  and  523 , and is coupled to comparator  112 . Voltage sensor  593  is configured to detect v dc  in converter  100  and transmit the detected v dc  value to comparator  112 . 
         [0063]    DC reference voltage source  595  is also coupled to comparator  112 . DC reference voltage source  595  is configured to provide the DC reference voltage (v dc-ref ) to comparator  112 , wherein v dc-ref  is a predetermined or desired voltage value within converter  100 . 
         [0064]    Direct-phase reference current source  597  is coupled to comparator  116  and is configured to transmit the direct-phase reference current (i d-ref ) value to comparator  116 . In one embodiment, i d-ref  includes a value of zero amps for unity power factor operation, although other embodiments may include a different value for i d-ref . 
         [0065]    Triangular waveform reference voltage source  599  is coupled to comparator  118  and is configured to provide the triangular waveform reference voltage (v tri ) to comparator  118 . The v tri  is a threshold voltage that, when compared to v con , dictates whether the switching commands issued to switches  160  and  165  turn switches  160  and  165  ON or OFF. 
         [0066]    It should be noted that when implementing system  400  with converter  100 , the reference currents (i d-ref  and i q-ref ) in system  400  should be chosen as two times the desired values. The reference currents should be doubled because system  400  does not deliver any active or reactive power to, or absorb any active or reactive power from AC voltage source  110 . 
         [0067]    During operation of system  500 , comparator  112  receives v dc  (i.e., the voltage value detected between node  521  and node  523 ) from voltage sensor  593  and v dc-ref  from DC reference voltage source  595 . At substantially the same time, delay function  785 , multiplier  121 , and multiplier  127  receive i a  (i.e., the current value detected between AC voltage source  110  and inductor  115 ) from current sensor  591 . 
         [0068]    Comparator  112  compares v dc  to v dc-ref  to determine the voltage error in converter  100  and transmits the voltage error to controller  143 . Controller  143  determines the i q-ref  value needed to offset the voltage error and transmits the determined i q-ref  value to comparator  114 . 
         [0069]    Comparator  114  also receives an i q  value from subtractor  180  and compares the i q  value to the i q-ref  value to determine a quadrature-phase current error. Comparator  114  then transmits the quadrature-phase current error to controller  146 . 
         [0070]    Controller  146  receives the quadrature-phase current error and determines a v q  value that would properly control switches  160 ,  165  based on the detected i a  and v dc  values in converter  100 . Controller  146  then transmits the determined v q  value to multiplier  120 . 
         [0071]    Multiplier  120  receives the v q  value from controller  146  and a sin θ value from sine function  105 , wherein sine function  105  receives a phase angle (θ) from PLL  103 . Multiplier  120  multiplies the v q  value and the sin θ value to generate a v q  sin θ component of v con , and transmits the v q  sin θ component to adder  133  (described below). 
         [0072]    As noted above, the current value i a  detected by current sensor  591  is supplied to delay function  785 , multiplier  121 , and multiplier  125 . Delay function  785  provides a 90 degree delay to i a  to generate an i b  value (that is the equivalent of an i b  value generated by the b-phase of a two-phase full bridge boost converter). Delay function  785  then transmits the i b  (i.e., the i a  value+90°) value to multipliers  123  and  125 . Multiplier  123  multiplies the i b  value and a cos θvalue received from cosine function  107  to generate an i b  cos θ value, wherein cosine function  107  received the phase angle (θ) from PLL  103 . Multiplier  123  then transmits the i b  cos θ value to subtractor  180 . Multiplier  125  multiplies the i b  value and the sin θ value received from sine function  105  to generate an i b  sin θ value. Multiplier  125  then transmits the i b  sin θ value to adder  131 . 
         [0073]    Multiplier  121  multiplies the i a  value and the sin θ value received from sine function  105  to generate an i a  sin θ value. Multiplier  121  then transmits the i a  sin θ value to subtractor  180  so that subtractor  180  may subtract the i b  cos θ value supplied from multiplier  123  from the i a  sin θ value to generate an (i a  sin θ−i b  cos θ) value or the i q  value. 
         [0074]    Multiplier  127  multiplies the i a  value and the cos θ value received from cosine function  107  to generate an i a  cos θ value. Multiplier  127  then transmits the i a  cos θ value to adder  131 . Adder  131  sums the i a  cos θ value and the i b  sin θ value supplied from multiplier  125  to generate an (i a  cos θ+i b  sin θ) value or i d  value. Adder  131  then transmits the i d  value to comparator  116 . 
         [0075]    Comparator  116  receives the i d  value from adder  131  and an i d-ref  value from direct-phase reference current source  597 . Comparator  116  then compares i d  to i d-ref  and generates a direct-phase current error based on the comparison. The direct-phase current error is then transmitted to controller  149 . 
         [0076]    Controller  149  receives the direct-phase current error and determines a v d  value that would properly control switches  160 ,  165  based on the detected i a  and v dc  values. Controller  149  then transmits the determined v d  value to multiplier  129 . 
         [0077]    Multiplier  129  receives the v d  value from controller  149  and the cos θ value from cosine function  107 . Multiplier  129  then multiplies the v d  value and the cos θ value to generate a v d  cos θ component of v con , and transmits the v d  cos θ component to adder  133 . 
         [0078]    Adder  133  receives the v q  sin θ component from multiplier  120  and the v d  cos θ component from multiplier  129  and sums the v q  sin θ component and the v d  cos θ component to generate a (v q  sin θ+v d  cos θ) value or v con  value. Adder  133  then transmits the v con  value to comparator  118 . 
         [0079]    Comparator  118  receives the v con  value from adder  133  and a v tri  value from waveform reference voltage source  599  and compares v con  to v tri . Comparator  118  then transmits switching commands to switches  160 ,  165  based on the comparison of v con  and v tri . For example, if v con  is greater than v tri  (i.e., v con &gt;v tri ), the switching commands turn switches  160 ,  165  ON, whereas if v con  is less than v tri  (i.e., v con &lt;v tri ), the switching commands turn switches  160  and  165  OFF so that converter  100  operates similar to the discussion above with reference to  FIG. 1 . 
         [0080]    Notably, setting i d -ref to zero volts yields unity power factor operation in system  500 . Furthermore, i d -ref set to zero volts yields a low total harmonic distortion and exceptional “zero crossing” characteristics. 
         [0081]    As one skilled in the art will recognize, system  400  may be implemented using computing hardware (and software), a computing device, and/or a computing system. That is, various embodiments of the invention contemplate that system  400  may be implemented via a processor, and specifically, a digital signal processor. 
         [0082]    While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.