Abstract:
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Description:
CROSS-REFERENCE AND INCORPORATION BY REFERENCE OF RELATED APPLICATION  
       [0001]    This disclosure relates to and incorporates by reference TI patent specification “Low Power Testing of Very Large Circuits”, application Ser. No. 09/339,734, Attorney Docket No. TI-28085, and TI patent specification “Adapting Scan-BIST Architectures for Low Power Operation”, application Ser. No. 60/188,109, Attorney Docket No. TI-30726. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.  
           [0004]    2. Description of the Related Art  
           [0005]    [0005]FIG. 1 illustrates a conventional scan architecture that a circuit  100  can be configured into during test. In the normal functional configuration, circuit  100  may be a functional circuit within IC, but in test configuration it appears as shown in FIG. 1. Scan architectures can be applied at various circuit levels. For example, the scan architecture of FIG. 1 may represent the testing of a complete IC, or it may represent the testing of an embedded intellectual property core sub-circuit within an IC, such as a DSP or CPU core sub-circuit. The scan architecture includes a scan path circuit  104 , logic circuitry to be tested  108 , and connection paths  112 - 120  to a tester  110 . Tester  110  operates to: (1) output control to operate scan path  104  via control path  114 ; (2) output serial test stimulus patterns to scan path  104  via scan input path  118 ; (3) input serial test response patterns from scan path  104  via scan output path  120 ; (4) output parallel test stimulus patterns to logic  108  via primary input path  112 ; and (5) input parallel test response patterns from logic  108  via primary output path  116 . Scan path  104  operates, in addition to its scan input and scan output modes to tester  110 , to output parallel test stimulus patterns to logic  108  via path  122 , and input parallel response patterns from logic  108  via path  124 .  
           [0006]    Typically tester  110  is interfaced to the scan architecture by probing the die pads at wafer level, or by contacting package pins after the die is assembled into a package. While tester  110  connections to the primary inputs  112  and primary outputs  116  of logic  108  are shown, the primary input and output connections could be achieved by augmentation of scan path  104 . For example, scan path  104  could be lengthened to include boundary scan cells located on each primary input and primary output of logic  108 . The boundary scan cells would provide primary inputs to and primary outputs from logic  108 , via widened stimulus and response busses  122  and  124 , respectively. In some instances, logic  108  may be sufficiently tested by scan path  104  such that it is not necessary to provide primary inputs to and outputs from logic  108  via the tester or via the above described augmentation of scan path  104 . For example, if the amount of logic  108  circuitry made testable by the use of scan path  104  in combination with the primary inputs and outputs is very small compared to the amount of logic  108  circuitry made testable by the scan path  104  alone, then the primary input and output connections to logic  108  may removed without significantly effecting the test of logic circuitry  108 . To simplify the description of the prior art and following description of the present invention, it will be assumed that logic circuit  108  is sufficiently tested using only scan path  104 , i.e. the primary inputs  112  and primary outputs  116  are not required. However, it is clear that primary input and output connections to the tester or to an augmented scan path  104 , as described above, could be used as well.  
           [0007]    [0007]FIG. 2 illustrates an example of a conventional scan cell that could be used in scan path  104 . (Note: The optional scan cell multiplexer  218  and connection paths  220  and  224 , shown in dotted line, will not be discussed at this time, but will be discussed later in regard to FIG. 7.) The scan cell consists of a D-FF  204  and a multiplexer  202 . During normal configuration of the circuit  100 , multiplexer  202  and D-FF  204  receive control inputs SCANENA  210  and SCANCK  212  to input functional data from logic  108  via path  206  and output functional data via path  216 . In the normal configuration, the SCANCK to D-FF  204  is typically a functional clock, and the SCANENA signal is set such that the D-FF always clocks in functional data from logic  108  via path  206 . During the test configuration of FIG. 2, multiplexer  202  and D-FF  204  receive control inputs SCANENA  210  and SCANCK  212  to capture test response data from logic  108  via path  206 , shift data from scan input path  208  to scan output path  214 , and apply test stimulus data to logic  108  via path  216 . In the test configuration, the SCANCK to D-FF  204  is the test clock and the SCANENA signal is operated to allow capturing of response data from logic  108  and shifting of data from scan input  208  to scan output  214 . During test configuration, SCANENA is controlled by tester  110  via path  114 . SCANCK may also be controlled by the tester, or it may be controlled by another source, for example a functional clock source. For the purpose of simplifying the operational description, it will be assumed that the SCANCK is controlled by the tester.  
           [0008]    The scan inputs  208  and scan outputs  214  of multiple scan cells are connected to form the serial scan path  104 . The stimulus path  216  and response path  206  of multiple scan cells in scan path  104  form the stimulus bussing path  122  and response bussing path  124 , respectively, between scan path  104  and logic  108 . From this scan cell description, it is seen that the D-FF is shared between being used in the normal functional configuration and the test configuration. During scan operations through scan path  104 , the stimulus outputs  216  from each scan cell ripple, since the stimulus  216  path is connected to the scan output path  214 . This ripple causes all the inputs to logic  108  to actively change state during scan operations. Rippling the inputs to logic  108  causes power to be consumed by the interconnect and gating capacitance in logic  108 .  
           [0009]    [0009]FIG. 3 illustrates a simplified example of how tester  110  operates, in states  300 , the scan architecture during test. Initially the tester will output control on path  114  to place the scan architecture in an idle state  302 . Next, the tester outputs control on path  114  to place the scan architecture in an operate scan path state  304 . In the operate scan path state, the tester outputs control to cause the scan path to accept stimulus data from the tester via path  118  and to output response data to the tester via path  120 . The tester maintains the operate scan path state until the scan path has been filled with stimulus data and emptied of response data. From the operate scan path state, the tester outputs control on path  114  to place the scan architecture in a capture response data state  306 . In the capture response data state, the tester outputs control to cause the scan path to load response data from logic  108  via path  124 . From the capture response data state  306 , the tester outputs control on path  114  to cause the scan architecture to re-enter the operate scan path state  302 . The process of entering the operate scan path state  304  to load stimulus into the scan path and empty response from the scan path, and then passing through the capture response state  306  to load new response data from logic  108  repeats until the end of test. At the end of test the tester outputs control to cause the scan architecture to re-enter the idle state  302 .  
           [0010]    [0010]FIG. 4 illustrates a timing example of how tester  110  outputs SCANENA and SCANCK signals to scan path  104  during scan operations. In this example, a high to low transition on SCANENA, at time  406 , in combination with SCANCKs occurring during time interval  402 , causes stimulus data from the tester to be input to the scan path via path  118  while response data is output from the scan path to the tester via path  120 . A low to high transition on SCANENA, at time  408 , in combination with a SCANCK at time  404 , causes response data from logic  108  to be loaded into the scan path. Time interval  402  relates to state  304  of operating the scan path, and time interval  404  relates to state  306  of capturing a response, in FIG. 3. As seen in the timing and operation diagrams of FIGS. 3 and 4, the time interval sequences  404  (i.e. state  306 ) and  402  (i.e. state  304 ) cycle a sufficient number of times during test to input all stimulus to and obtain all response from logic  108 .  
           [0011]    From the scan architecture described in regard to FIGS. 1, 2,  3 , and  4  it is seen that the stimulus  122  outputs ripple the inputs to logic  108  as data shifts through the scan path  104  during scan operations. Rippling the inputs of logic  108  causes simultaneous charging and discharging of capacitances associated with the interconnects and gates of logic  108 . For example, each scan cell stimulus output  216  to logic  108  charges and discharges a certain amount of capacitance within logic  108  at a frequency related to the data bits being scanned through the scan cell. While each scan cell stimulus output may only be directly input to a few gates within logic  108 , each of the gates in logic  108  have outputs that fanout to inputs of other gates in logic  108 , and the outputs of the other gates in logic  108  again fanout to inputs of still further gates, and so on. Thus a transition on the stimulus output of a single scan cell may initiate hundreds of transitions within logic  108  as a result of the above mentioned signal transition fanout. Each of the transitions charge or discharge a portion of the total capacitance with logic  108  and therefore contribute to power consumption within logic  108 .  
           [0012]    The individual power (Pi) consumed by the rippling of a given scan cell output  216  can be approximated by CV 2 F, where C is the capacitance being charged or discharged by the scan cell output (i.e. the capacitance of the above mentioned signal transition fanout), V is the switching voltage level, and F is the switching frequency of the scan cell output. The total power (Pt) consumed by simultaneously scanning all the scan cells in scan path  104  is approximately the sum of the individual scan cell powers, i.e. Pt=Pi i +Pi 2 + . . . Pi N . The total power consumed by circuit  100 , when it is configured into the scan architecture of FIG. 1, can exceed the power consumed by circuit  100  when it is configured into its normal functional mode. This can be understood from the fact that, during normal functional mode of circuit  100 , not all the D-FFs  204  simultaneously operate, as they do during scan operations occurring during the above described scan test operation. Further if an IC contained multiple circuits  100 , the test of the IC may require testing each circuit  100  individually due to the above described test power consumption restriction. This lengthens the test time of the IC, which increases the cost to manufacture the IC.  
           [0013]    A first known method of reducing power consumption during test operation is to insert blocking circuitry, such as a gate, into the stimulus paths  216  of each scan cell, such that during scan operations the inputs to logic  108  are blocked from the effect of the scan ripple. The problem with the first method is that it adds an undesirable delay (i.e. the blocking circuit delay) in the stimulus paths  216  between D-FFs  204  and logic  108 . This delay can negatively effect the performance of circuit  100  when it is configured into its normal functional mode. A second known method is to reduce the scan clock rate, such that the ripple frequency (F) is reduced. The problem with the second method is that it increases the test time since scan operations are performed at the reduced scan clock rate.  
           [0014]    Today, there are a number of test synthesis vendor tools that can synthesize and insert scan architectures into ICs, similar in structure to the scan architecture shown in FIG. 1. The use of such “push-button” scan insertion tools is an attractive alternative to customized scan designs since it is an automated process. As will be described, the present invention provides a method of adapting these synthesized scan architectures such that they may operate in a desired low power mode. The process of adapting scan architectures for low power operation is also easily automated.  
           [0015]    The present invention described below provides a method of adapting synthesized scan architectures to achieve a low power mode of operation. The process of adapting scan architectures for low power operation is achieved without the aforementioned problems of; (1) having to insert blocking circuitry in the stimulus paths which adds signal delays, and (2) having to decrease the scan clock rate which increases test time. Furthermore, as will be described in more detail later, the process of adapting scan architectures for low power operation is achieved without having to modify the stimulus and response test patterns which are automatically produced by scan architecture synthesis tools.  
         BRIEF SUMMARY OF THE INVENTION  
         [0016]    The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.  
           [0017]    Adapting a known scan path into a scan path of the present invention involves reorganizing the known scan path from being a single scan path containing all the scan cells (M), into a scan path having a desired number of selectable separate scan paths.  
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0018]    [0018]FIG. 1 is a block diagram of a circuit having a single scan path.  
         [0019]    [0019]FIG. 2 is a block diagram of a scan cell.  
         [0020]    [0020]FIG. 3 is a flow diagram of the operation of the circuit of FIG. 1.  
         [0021]    [0021]FIG. 4 is a timing diagram.  
         [0022]    [0022]FIG. 5 is a block diagram of a circuit having a scan path arranged according to the present invention.  
         [0023]    [0023]FIG. 6 is a flow diagram of the operation of the circuit of FIG. 5.  
         [0024]    [0024]FIG. 7 is a block diagram of the adaptor of FIG. 5.  
         [0025]    [0025]FIG. 8 is a timing diagram for the operation of the adaptor of FIG. 7.  
         [0026]    [0026]FIG. 9 is a block diagram of the scan paths arranged according to the present invention.  
         [0027]    [0027]FIG. 10 is a block diagram of a circuit using a conventional parallel scan architecture.  
         [0028]    [0028]FIG. 11 is a flow chart for the operation of the parallel scan path of FIG. 10.  
         [0029]    [0029]FIG. 12 is a block diagram of a parallel scan path arranged according to the present invention.  
         [0030]    [0030]FIG. 13 is a flow chart of the operation of the circuit of FIG. 12.  
         [0031]    [0031]FIG. 14 is a block diagram of another conventional parallel scan path circuit.  
         [0032]    [0032]FIG. 15 is a flow chart of the operation of the circuit of FIG. 14.  
         [0033]    [0033]FIG. 16 is a block diagram of the circuit of FIG. 14 according to the present invention.  
         [0034]    [0034]FIG. 17 is a flow chart of the operation of the circuit of FIG. 16.  
         [0035]    [0035]FIG. 18 is a block diagram of an integrated circuit having three core circuits and conventional scan paths.  
         [0036]    [0036]FIG. 19 is a block diagram of another integrated circuit having three cores and unequal conventional scan paths.  
         [0037]    [0037]FIG. 20 is a block diagram of the circuit of FIG. 18 with scan paths according to the present invention.  
         [0038]    [0038]FIG. 21 is a block diagram of the circuit of FIG. 19 with scan paths according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0039]    [0039]FIG. 5 illustrates the scan architecture of FIG. 1 after it has been adapted into the low power scan architecture of the present invention. The changes between the FIG. 1 scan architecture and the FIG. 5 low power scan architecture involve modification of scan path  104  into scan path  502 , and the insertion of an adaptor circuit  504  in the control path  114  between tester  110  and scan path  502 .  
         [0040]    Adapting scan path  104  into scan path  502  involves reorganizing scan path  104  from being a single scan path containing all the scan cells (M), into a scan path having a desired number of selectable separate scan paths. In FIG. 5, scan path  502  is shown after having been reorganized into three separate scan paths A  506 , B  508 , and C  510 . It is assumed at this point in the description that the number of scan cells (M) in scan path  104  is divisible by three such that each of the three separate scan paths A, B, and C contains an equal number of scan cells (M/3). The case where scan path  104  contains a number of scan cells (M) which, when divided by the number of desired separate scan paths, does not produce an equal number of scan cells in each separate scan path will be discussed later in regard to FIG. 9.  
         [0041]    Scan paths A, B, and C are configured as follows inside scan path  502 . The serial input of each scan path A, B, and C is commonly connected to tester  110  via connection path  118 . The serial output of scan path A is connected to the input of a 3-state buffer  512 , the serial output of scan path B is connected to the input of a 3-state buffer  514 , and the serial output of scan path C is connected to the input of a 3-state buffer  516 . The outputs of the 3-state buffers  512 - 516  are commonly connected to tester  110  via connection path  120 . Scan paths A, B, and C each output an equal number of parallel stimulus inputs  526 ,  530 ,  534  to logic  108 , and each input an equal number of parallel response outputs  524 ,  528 ,  532  from logic  108 . The number of stimulus output signals to logic  108  in FIGS. 1 and 5 is the same. The number of response input signals from logic  108  in FIGS. 1 and 5 is the same. Scan path A and buffer  512  receive control input from adaptor  504  via bus  518 , scan path B and buffer  514  receive control input from adaptor  504  via bus  520 , and scan path C and buffer  516  receive control input from adaptor  504  via bus  522 .  
         [0042]    Adaptor  504  is connected to scan paths A, B, C via busses  518 - 522  and to tester  110  via bus  114 . The purpose of the adaptor is to intercept the scan control output  114  from tester  110  and translate it into a sequence of separate scan control outputs  518 - 522  to scan paths A, B, and C, respectively. Each of the separate scan control outputs  518 - 522  are used to operate one of the scan paths A, B, and C.  
         [0043]    [0043]FIG. 6 illustrates a simplified example of the combined operation states  600  of the tester  110  and adaptor  504  during test. The operation of tester  110  is the same as previously described in regard to FIG. 3. When the tester transitions to the operate scan path state  304 , it begins outputting control to adaptor  504  via path  114 . The adaptor responds to the tester control input by translating it into a sequence of separate control outputs  518 ,  520 , and  522  to scan paths A, B, and C. As indicated in adaptor operation block  602 , the adaptor first responds to control  114  during adaptor operate state  604  to output control  518 , which enables buffer  512  and operates scan path A to input stimulus data from tester  110  via path  118  and output response data to tester  110  via path  120 . After scan path A is filled with stimulus and emptied of response, adaptor  504  responds to control  114  during operation state  606  to output control  520 , which enables buffer  514  and operates scan path B to input stimulus data from tester  110  via path  118  and output response data to tester  110  via path  120 . After scan path B is filled with stimulus and emptied of response, adaptor  504  responds to control  114  during operation state  608  to output control  522 , which enables buffer  516  and operates scan path C to input stimulus data from tester  110  via path  118  and output response data to tester  110  via path  120 . After scan paths A, B, and C have been filled and emptied, the tester  110  transitions from the operate state  304 , through the capture state  306 , and back to the operate state  304 . During this transition, the adaptor is idle during the capture state  306 , but resumes its scan control sequencing operation when the operate state  304  is re-entered. This process of sequentially scanning scan paths A, B, and C, then performing a capture operation to load response data repeats until the test has been performed and tester  110  enters the idle state  302 .  
         [0044]    During the sequencing of the operation states  604 - 608 , only one of the buffers  512 - 516  are enabled at a time to output response data to tester  110 . Also, the sequencing of the adaptor operation states  604 - 608  occurs in a seamless manner such that the stimulus data from the tester  110  is input to scan path  502  as it was input to scan path  104 , and the response data to tester  110  is output from scan path  502  as it was output from scan path  104 . To the tester, the behavior of the scan path  502  and adaptor  504  combination is indistinguishable from the behavior of the scan path  104  in FIG. 1. Thus the test time of the logic  108  in FIG. 5 is the same as the test time of logic  108  in FIG. 1.  
         [0045]    From the above description, it is seen that only a subset (i.e. subset A  526 , B  530 , or C  534 ) of the stimulus input bus  122  to logic  108  is allowed to ripple at any given time during the adaptor operated scan operation of FIGS. 5 and 6. In contrast, the entire stimulus input bus  122  to logic  108  ripples during the tester operated scan operation of FIGS. 1 and 3. Since, using the present invention, only a subset of the stimulus inputs to logic  108  are allowed to ripple at any one time, less of the aforementioned interconnect and gating capacitance of logic  108  is simultaneously charged and discharged during scan operations. By reducing the amount of logic  108  capacitance being simultaneously charged and discharged during scan operations, the power consumed by logic  108  is advantageously reduced by the present invention.  
         [0046]    Example Adaptor Circuit  
         [0047]    [0047]FIG. 7 illustrates an example adaptor circuit  504  implementation. Adaptor  504  inputs the SCANCK  212  and SCANENA  210  signals from tester  110 , via bus  114 . Adaptor  504  outputs SCANCK-A signal  712 , SCANCK-B signal  714 , SCANCK-C signal  716 , ENABUF-A signal  718 , ENABUF-B signal  720 , ENABUF-C signal  722 , and the SCANENA signal  210 . The SCANENA signal  210  is connected to all scan cell  200  multiplexers  202  as shown in FIG. 2. The SCANCK-A signal  712  is connected, in substitution of SCANCK signal  212 , to all scan cell  200  D-FF  204  clock inputs of scan path A. The SCANCK-B signal  714  is connected, in substitution of SCANCK signal  212 , to all scan cell  200  D-FF  204  clock inputs of scan path B. The SCANCK-C signal  716  is connected, in substitution of SCANCK signal  212 , to all scan cell  200  D-FF  204  clock inputs of scan path C. The ENABUF-A signal  718  is connected to the enable input of buffer  512 . The ENABUF-B signal  720  is connected to the enable input of buffer  514 . The ENABUF-C signal  722  is connected to the enable input of buffer  516 .  
         [0048]    Referring also to FIG. 8, adaptor  504  includes a state machine  702 , counter  704 , and gates  706 - 710 . During the functional mode of circuit  500 , SCANENA is high as indicated at time  810  in the adaptor timing diagram of FIG. 8. While SCANENA is high, state machine  702  outputs control signals  724 - 728  that enable SCANCK to pass through gates  706 - 710  to functionally clock all D-FFs  204  of scan paths A, B, and C, via SCANCK-A, SCANCK-B, and SCANCK-C. In this example, the SCANCK is assumed to be the functional clock during the functional mode of circuit  500 , and the test clock during test mode of circuit  500 . While SCANENA is high, state machine  702  outputs control signals  718 - 722  to disable buffers  512 - 516 . The scan operation mode is entered by SCANENA going low as indicated at time  812  in FIG. 8. SCANENA goes low when tester  110  transitions from the idle state  302  to the operate state  304  as seen in FIG. 6.  
         [0049]    At the beginning of the scan operation mode, the state machine initializes counter  704  via control (CTL) signals  730  and disables scan access to scan paths B and C by disabling SCANCK gates  708  and  710  via signals  726  and  728 , and enables scan access to scan path A by; (1) enabling SCANCK gate  706  via signal  724 , and (2) enabling buffer  512  via signal  718 . Scan access of scan path A occurs over time interval  802  of FIG. 8. During time interval  802 , scan path A is accessed to load stimulus data from tester  110  via path  118  and unload response to tester  110  via path  120 . While scan path A is being accessed, the state machine operates counter  704  via control signals  730  to determine the number (M/3) of SCANCK-A&#39;s to output to scan path A. When the counter reaches a count, indicative of scan path A receiving the correct number (M/3) SCANCK-A inputs, it outputs a first count complete 1 (CC 1 ) signal  732  to state machine  702 .  
         [0050]    In response to the first CC 1  signal, the state machine initializes counter  704  via control signals  730  and disables scan access to scan path A and C, and enables scan access to scan path B over time interval  804 . The state machine enables scan access to scan path B by; (1) enabling SCANCK gate  708  via signal  726 , and (2) enabling buffer  514  via signal  720 . While scan path B is being accessed, the state machine operates counter  704  via control signals  730  to determine the number of SCANCK-B&#39;s to output to scan path B. When the counter reaches a count, indicative of scan path B receiving the correct number (M/3) SCANCK-B inputs it outputs a second count complete  1  (CC 1 ) signal  732  to state machine  702 .  
         [0051]    In response to the second CC 1  signal, the state machine initializes counter  704  via control signals  730  and disables scan access to scan path A and B, and enables scan access to scan path C over time interval  806 . The state machine enables scan access to scan path C by; (1) enabling SCANCK gate  710  via signal  728 , and (2) enabling buffer  516  via signal  722 . While scan path C is being accessed, the state machine operates counter  704  via control signals  730  to determine the number of SCANCK-C&#39;s to output to scan path C. When the counter reaches a count, indicative of scan path C receiving the correct number (M/3) SCANCK-C inputs, it outputs a third count complete 1 (CC1) signal  732  to state machine  702 .  
         [0052]    In response to the third CC1 signal, the state machine disables all buffers  512 - 516  via signals  718 - 722  and enables gates  706 - 710  to pass the SCANCK to all scan cells of scan paths A, B, and C. Since scan paths A, B, and C were assumed to contain equal numbers of scan cells (M/3) with the sum of the scan cells in scan paths A, B, and C being equal to the number of scan cells (M) in scan path  104 , the third CCI signal occurs one SCANCK prior to tester  110  setting the SCANENA signal high, at time  814 , during its transition from the operate state  304  to the capture state  306  in FIG. 6. While SCANENA is high, at time  808 , all scan paths A, B, and C receive a SCANCK, causing them to load response data from logic  108  of FIG. 5. Following the response data load operation at time  808 , SCANENA, from tester  110 , returns low at time  812  and the above described sequence of separately accessing scan paths A, B, and C repeats until the test completes and tester  110  transitions back to idle state  302  of FIG. 6.  
         [0053]    Contrasting the scan timing diagrams of FIGS. 4 and 8, it is seen that tester  110  provides the same SCANENA timing for both diagrams. For example, (1) the SCANENA high to low transition at time  406  in FIG. 4 is the same SCANENA high to low transition at time  812  in FIG. 8, (2) the SCANENA low to high transition at time  408  in FIG. 4 is the same SCANENA low to high transition at time  814  in FIG. 8, (3) the same number of SCANCKs occur between time  406 / 812  and time  408 / 814  in both diagrams, and (4) the same response load SCANCK occurs at time  404  in FIG. 4 and at time  808  in FIG. 8. The difference between the two timing diagrams is seen in the way the adaptor  504  sequentially applies a burst of M/3 SCANCKs to scan paths A, B, and C during time intervals  802 ,  804 , and  806 , respectively, such that only one of the scan paths is accessed at a time.  
         [0054]    While the example adaptor circuit of FIG. 7 has been described using a gated clocking scheme to control access to the scan cells  200  of scan paths A, B, and C, other example designs of adaptor  504  may be used to control access to other types of scan cells used in scan paths A, B, and C as well. For example, the scan cells  200  of FIG. 2 could be designed to include a state hold multiplexer  218  between the output of multiplexer  202  and input to D-FF  204 . The state hold multiplexer  218  could be controlled, via a connection  220  to the ENACK-A  724 , ENACKB  726 , and ENACK-C  728  signals from state machine  702 , such that it provides a connection  222  between the output of multiplexer  202  and the D-FF input, or it provides a state hold connection  224  between the output of DFF  204  and the input to D-FF  204 . If this type of scan cell  200  were used in scan paths A, B, and C, the SCANCK  212  could be directly routed to all the D-FF  204  clock inputs instead of being gated to the D-FF  204  clock inputs via the SCANCK-A, SCANCK-B, and SCANCK-C signals as described for adaptor  504  of FIG. 7. The adaptor  504  would be modified to operate the state holding scan cells by eliminating the gates  706 - 710  and the SCANCK-A, SCANCK-B, and SCANCK-C outputs, and providing as outputs the ENACK-A  724 , ENACK-B  726 , and ENACK-C  728  signals from state machine  702 . The ENACK-A output would be connected as control input  220  to the state hold multiplexers  218  in the scan cells of scan path A. The ENACK-B output would be connected as control input  220  to the state hold multiplexers  218  in the scan cells of scan path B. The ENACK-C output would be connected as control input  220  to the state hold multiplexers  218  in the scan cells of scan path C.  
         [0055]    During functional and response capture operations, the ENACK-A, ENACK-B, and ENACK-C outputs from the modified adaptor  504  would be set to enable a connection between the response signal  206  and input to D-FF  204  of each scan cell, via multiplexer  202  and the state hold multiplexer  218 . During scan operations to scan path A (timing interval  802 ), the ENACK-B and ENACK-C outputs would be set to place the scan cells of scan paths B and C in their state hold connection configuration, and ENACK-A would be set to form a connection between the scan input  208  and input to D-FF  204  of the scan cells in scan paths A, to allow scan access of scan path A. During scan operations to scan path B (timing interval  804 ), the ENACK-A and ENACK-C outputs would be set to place the scan cells of scan paths A and C in their state hold connection configuration, and ENACK-B would be set to form a connection between the scan input  208  and input to D-FF  204  of the scan cells in scan paths B, to allow scan access of scan path B. During scan operations to scan path C (timing interval  806 ), the ENACK-A and ENACK-B outputs would be set to place the scan cells of scan paths A and B in their state hold connection configuration, and ENACK-C would be set to form a connection between the scan input  208  and input to D-FF  204  of the scan cells in scan paths C, to allow scan access of scan path C.  
         [0056]    The modified adaptor  504  and state hold type scan cells described above operate to achieve the low power mode of scan access to scan paths A, B, and C as previously described with the original adaptor  504  and scan cell  200 . The difference between the two adaptor/scan cell combinations described above is that the original adaptor/scan cell combination operates in a gated clock mode (i.e. uses gated clocks SCANCK-A, SCANCK-B, and SCANCK-C) and the modified adaptor/scan cell combination operates in a synchronous clock mode C (i.e. uses the SCANCK).  
         [0057]    Scan Path Adaptation  
         [0058]    As mentioned previously, test synthesis tools exist that are capable of automatically instantiating scan architectures similar to the one shown in FIG. 1. These tools are capable of analyzing logic  108  and its stimulus and response interface to scan path  104  To Whom It May Concern: determine what stimulus test pattern data needs to input from tester  110  to logic  108  via scan path  104  and what response test patterns data is expected to be output to tester  110  from logic  108  via scan path  104 . To reduce the effort required to adapt the synthesized scan architecture of FIG. 1 into the low power scan architecture of FIG. 5, the scan path adaptation process described below is preferably performed.  
         [0059]    In FIG. 9, scan path  104  is shown receiving stimulus frames  920  from tester  110  via connection  118  and outputting response frames  922  to tester  110  via connection  120 . The term “frame” simply indicates the number of scan bits (M) required to fill the scan path  104  with stimulus data from tester  110  and empty the scan path  104  of response data to tester  110  during the operate state  304  of FIG. 3. The test may require a large number of stimulus and response frame communications to test logic  108 . To achieve the low power mode of operation of the present invention, it is desired to reorganize scan path  104  into a plurality of separate scan paths. In this example, the reorganization of scan path  104  results in the previously described scan path  502 , which contains three separate scan paths  506 - 510 . It is also desired to adapt scan path  104  into scan path  502  in such a way as to avoid having to make any modifications to the stimulus and response test pattern frames  920  and  922 .  
         [0060]    As previously mentioned in regard to FIG. 5, the number (M) of scan cells in scan path  104 , is assumed divisible by three such that scan path  104  can be seen to comprise three separate scan segments A, B, and C, each scan segment containing a third (M/3) of the scan cells (M) in scan path  104 . Scan segment A of  104  contains a subset  912  of the stimulus and response signals of the overall stimulus and response busses  122  and  124  respectively. Scan segment B of  104  contains a subset  910  of the stimulus and response signals of the overall stimulus and response busses  122  and  124  respectively. Scan segment C of  104  contains a subset  912  of the stimulus and response signals of the overall stimulus and response busses  122  and  124  respectively.  
         [0061]    Each stimulus scan frame  920  scanned into scan path  104  from tester  110  can be viewed as having bit position fields [CBA] that fill scan segments C, B, and A, respectively. For example, following a scan operation, bit position field A is loaded into segment A, bit position field B is loaded into segment B, and bit position field C is loaded into segment C. Likewise, each response scan frame  922  scanned from scan path  104  to tester  110  can be viewed as having bit position fields [CBA] that empty scan segments C, B, and A, respectively. For example, following a scan operation, bit position field A is unloaded from segment A, bit position field B is unloaded from segment B, and bit position field C is unloaded from segment C. To insure that the stimulus  920  and response  922  frames are reusable when scan path  104  is reorganized into the low power configuration, the reorganization process occurs as described below.  
         [0062]    Scan path  104  segment A is configured as a separate scan path A  506 , as indicated by the dotted line  914 . Scan path  104  segment B is configured as a separate scan path B  508 , as indicated by the dotted line  916 . Scan path  104  segment C is configured as a separate scan path C  510 , as indicated by the dotted line  918 . The scan inputs to scan paths A, B, and C  506 - 510  are connected to tester  110  via connection  118 . The scan outputs from scan paths A, B, and C  506 - 510  are connected, via the previously described 3-state buffers  512 - 516 , to tester  110  via connection  120 . Each separate scan path  506 - 510  maintains the same stimulus and response bussing connections  908 - 912  to logic  108 .  
         [0063]    Operating the reorganized scan path  502  using the tester  110  used to operate scan path  104  results in the following behavior. This behavior assumes adaptor  504  has been inserted between the tester  110  and scan path  502 , to control scan path  502  as described in FIGS. 5, 6,  7 , and  8 . During input and output of stimulus and response frames [CBA]  920  and  922  respectively, (1) stimulus bit field A is directly loaded into scan path A from tester  110  via path  118  as response bit field A is directly unloaded from scan path A to tester  110  via path  120 , (2) stimulus bit field B is directly loaded into scan path B from tester  110  via path  118  as response bit field B is directly unloaded from scan path B to tester  110  via path  120 , and (3) stimulus bit field C is directly loaded into scan path C from tester  110  via path  118  as response bit field C is directly unloaded from scan path C to tester  110  via path  120 . As seen from this description, when scan path  104  is reorganized into scan path  502  as described, scan path  502  can use the same stimulus and response frames originally intended for use by scan path  104 . Thus no modifications are necessary to the stimulus and response test pattern frames produced by the test synthesis tool.  
         [0064]    In the case where scan path  104  contains a number of scan cells (M) that is not equally divisible by the desired number of separate scan paths (N) in scan path  502 , the length of one of the separate scan paths can be adjusted to compensate scan path  502  for proper input and output of the scan frames  920 - 922 . For example, if the number of scan cells (M) in scan path  104  is not equally divisible by the number of separate scan paths (N) required to achieve a desired low power mode of operation, M can be increased by adding a value (Y) such that M+Y is equally divisible by N. Once this is done, N separate scan paths may be formed. N−1 of the separate scan paths will have a length (M+Y)/N and one of the separate scan paths will have a length of ((M+Y)/N)−Y. For example, if scan path  104  had  97  scan cells (M), scan path A and B of  502  would each be configured to contain  33  scan cells [(M+Y)/N=(97+2)/3=33], while scan path C would be configured to contain 31 scan cells [(M+Y)/N)−Y=((97+2)/3)−2=31]. In this example, the scan frame  920 - 922  [CBA] segments would be seen as; segment A=33 bits, segment B=33 bits, and segment C=31 bits.  
         [0065]    When scan path  502  is formed to include the scan frame compensation technique described above, the operation of adaptor  504  is adjusted so it can properly control the compensated scan path  502 . In FIGS. 7 and 8, the adaptor  504  circuit and operation was described in detail. Assuming the adaptor timing diagram in FIG. 8 is being used to communicate scan frames to a scan path  502  consisting of the above mentioned 33-bit scan path A, 33-bit scan path B, and 31-bit scan path C, the following changes are required to adaptor  504 . Adaptor state machine  702  continues to monitor the CC1  732  output from counter  704 , as previously described, to determine when to stop 33-bit scan operations to scan paths A and B at timing intervals  802  and  804 , respectively, in FIG. 8. However, since the scan timing interval  806  to scan path C is different from the scan timing intervals  802  and  804 , the state machine operation is altered to where it monitors the count complete 2 (CC2) output  734  from counter  704  to stop the 31-bit scan operation to scan path C. The CC2  734  output is designed to indicate when the 31-bit scan operation to scan path C should be stopped, whereas the CC1  732  is designed to indicate when the 33-bit scan operation to scan paths A and B should be stopped.  
         [0066]    Parallel Scan Architectures  
         [0067]    [0067]FIG. 10 illustrates circuit  1000  that has been configured for testing using a conventional parallel scan architecture. As with the previous single scan architecture of FIG. 1, parallel scan architectures may be synthesized and automatically inserted into ICs to serve as embedded testing mechanisms. The parallel scan architecture includes separate scan paths 1−N  1010 - 1016  and an interface to tester  1008 . During the functional mode of circuit  1000 , the D-FFs  204  of scan paths 1−N are configured to operate with logic  1006  to provide the circuit  1000  functionality. During test mode, the D-FFs  204  of scan path 1−N are configured to operate with tester  1008  to provide testing of logic  1006 . Scan paths 1−N receive response from logic  1006  via paths  1040 - 1046 , and output stimulus to logic  1006  via paths  1048 - 1054 . Scan paths 1−N receive serial stimulus from tester  1008  via paths  1010 - 1024 , and output serial response to tester  1008  via paths  1026 - 1032 . Scan paths 1−N receive control input from tester  1008  via path  1034 .  
         [0068]    When circuit  1000  is first placed in the test configuration of FIG. 10, the parallel scan architecture will be controlled, by tester  1008 , to be in the idle state  1102  of the test operation diagram  1100  in FIG. 11. From the idle state  1102 , tester  1008  will transition the parallel scan architecture into the operate scan paths 1−N state  1104 . During the operate state  1104 , tester  1008  outputs control to scan paths 1−N causing the scan paths to input stimulus from tester  1008  via paths  1018 - 1024  and output response to tester  1008  via paths  1026 - 1032 . After the scan paths 1−N are filled with stimulus and emptied of response, tester  1008  transitions to the capture state  1106  to load the next response data, then returns to the operate state  1104  to input the next stimulus data and empty the next response data. After all stimulus and response data patterns have been applied, by repeating transitions between the operate and capture states, the test is complete and the tester returns to the idle state  1102 .  
         [0069]    The structure and operation of the parallel scan architecture of FIG. 10 is very similar to the structure and operation of the single scan architecture of FIG. 1. Some notable differences exist between the scan architectures of FIGS. 1 and 10. (1) In FIG. 10, multiple parallel scan paths 1−N are formed during the test configuration, as opposed to the single scan path  104  formed during the FIG. 1 test configuration. (2) In FIG. 10, tester  1008  outputs multiple parallel stimulus outputs  1018 - 1024  to scan paths 1−N, as opposed to tester  110  outputting a single stimulus output  118  to scan path  104 . (3) In FIG. 10, tester  1008  inputs multiple parallel response outputs  1026 - 1032  from scan paths 1−N, as opposed to tester  110  inputting a single response output  120  from scan path  104 .  
         [0070]    The parallel scan architecture of FIG. 10 suffers from the same power consumption problem described in the scan architecture of FIG. 1, since during scan operations, logic  1006  receives simultaneous rippling stimulus inputs from scan paths 1−N. Thus, the parallel scan architecture of FIG. 10 can be improved to where it consumes less power during test by adapting it into a low power parallel scan architecture as described below.  
         [0071]    Low Power Parallel Scan Architecture  
         [0072]    [0072]FIG. 12 illustrates the FIG. 10 parallel scan architecture after it has been adapted for low power operation. The adaptation process, as previously described in the low power adaptation of the FIG. 1 scan architecture, involves the following steps. Step one includes reconfiguring scan paths 1−N  1010 - 1016  of FIG. 10 into scan paths 1−N  1202 - 1208  of FIG. 12, wherein each scan path 1−N  1202 - 1208  contains multiple separate scan paths between their respective inputs  1018 - 1024  and outputs  1026 - 1032 . In this example, it is assumed that each scan path 1−N  1202 - 1208  has been reconfigured into separate scan paths A, B, and C, as scan path  104  of FIG. 1 was reconfigured into scan path  502  of FIG. 5. Step two includes inserting adaptor  1210  between tester  1008  and scan paths 1−N  1202 - 1208 . In this example, it is assumed that adaptor  1210  is very similar to adaptor  504  in the way it operates the separate scan paths A, B, and C in each of the scan paths 1−N  1202 - 1208 , so only the brief operation description of adaptor  1210  is given below.  
         [0073]    As seen in the operation diagram of FIG. 13, adaptor  1210  responds to tester  1008  entering the operate state  1104  to: (1) simultaneously operate the scan paths A of scan paths  1202 - 1208 , via control bus  1212 , to input stimulus from tester  1008  and output response to tester  1008 , then (2) simultaneously operate the scan paths B of scan paths  1202 - 1208 , via control bus  1212 , to input stimulus from tester  1008  and output response to tester  1008 , then (3) simultaneously operate the scan paths C of scan paths  1202 - 1208 , via control bus  1212 , to input stimulus from tester  1008  and output response to tester  1008 . Adaptor  1210  suspends scan operations to scan paths  1202 - 1208  when tester  1008  enters the capture state  1106 , and resumes the above described scan operation sequence to the scan paths A, B, and C of scan paths  1202 - 1208  when tester  1008  re-enters the operate state  1104 . After the test completes, tester  1008  enters the idle state  1102  and the adaptor  1210  is disabled. From this description, the operation of adaptor  1210  is seen to mirror the operation of adaptor  504  with the exception that adaptor  1210  controls multiple scan paths A, multiple scan paths B, and multiple scan paths C during its control state diagram sequence  1302 . In contrast, adaptor  504  controlled only one scan path A, one scan path B, and one scan path C during its control state diagram sequence  602 .  
         [0074]    Direct Synthesis of Low Power Scan Architectures  
         [0075]    While the process of adapting pre-existing scan architectures for low power operation has been described, it is anticipated that, once the low power benefit of the present invention is understood, test synthesis tools will be improved to provide direct synthesis of low power scan architectures. Direct synthesis of low power scan architectures will eliminate the need to perform the adaptation steps previously described, since the steps will be incorporated into the synthesis process. A direct synthesis of a single scan path low power scan architecture would result in the direct instantiation of a low power scan architecture similar to the one described and shown in regard to FIG. 5. A direct synthesis of a parallel scan path low power scan architecture would result in the direct instantiation of a low power scan architecture similar to one described and shown in regard to FIG. 12.  
         [0076]    Adapting Scan Controller Architectures for Low Power Operation  
         [0077]    [0077]FIG. 14 illustrates a circuit  1400  configured into a conventional scan controller based scan architecture. The scan architecture consists of logic  1410 , scan paths  1412 - 1418 , and scan controller  1402 . The scan paths are coupled to logic  1410  via stimulus and response paths  1424 , to scan controller  1402  via path  1404 , and to tester  1408  via scan inputs  1420  and scan outputs  1422 . The scan controller is coupled to tester  1408  via path  1406 . While the scan controller based architecture of FIG. 14 uses parallel scan paths  1412 - 1418 , a single scan path architecture, such as the one shown in FIG. 1, could be used as well. The scan architecture operates to test logic  1410  as previously described in regard to the scan architecture of FIG. 10, with the exception that the tester  1408  inputs control to scan controller  1402  instead of directly to the scan paths. In response to tester control input, the scan controller outputs scan control  1404  to scan paths  1412 - 1418  to execute the test. An example control diagram for the scan controller is shown in FIG. 15. While various different control diagrams for various different scan controllers could be shown, the diagram of FIG. 15 reflects the basic scan operations typically required by any scan controller circuit  1402 . Those operations being, an idle state  1502 , an operate scan state  1504 , and a capture response state  1506 . It is understood that various other scan operation states could exist in the control diagram.  
         [0078]    The scan controller of FIG. 14 could be anyone of many types of scan controller circuits. Two examples of some of the types of scan controllers that could be represented by scan controller  1402  are listed below.  
         [0079]    In one realization, scan controller  1402  could represent the test access port (TAP) controller circuit of IEEE standard 1149.1, A Standard Test Access Port and Boundary Scan Architecture. A description of the IEEE TAP being used to control scan access to parallel scan paths is described in regard to FIG. 14a of U.S. Pat. No. 5,526,365 by Whetsel and is incorporated herein by reference. The TAP operation states differ from the operation state diagram of FIG. 15, but in general it contains the fundamental scan  1504  and capture  1506  states.  
         [0080]    In another realization, scan controller  1402  could represent the boundary input/output serializer (BIOS) circuit, described in regard to FIG. 17 of the above mentioned U.S. Pat. No. 5,526,365, being used to control scan access to parallel scan paths. The BIOS description in U.S. Pat. No. 5,526,365 is incorporated herein by reference. The BIOS operation also differs from the operation state diagram of FIG. 15, but in general it contains the fundamental scan  1504  and capture  1506  states.  
         [0081]    In still another realization, scan controller  1402  could represent the addressable test port (ATP) circuit, described in TI patent application TI-28058, being used to control scan access to parallel scan paths. The TI-28058 patent application is incorporated herein by reference. As with the TAP and BIOS, the ATP operation differs from the operation state diagram of FIG. 15, but in general it contains the fundamental scan  1504  and capture  1506  states.  
         [0082]    [0082]FIG. 16 illustrates the two modification steps to the scan controller based scan architecture of FIG. 15 to achieve the desired low power mode of operation. In the first modification step, as with the previously described modification of the FIG. 10 scan architecture into the FIG. 12 low power scan architecture, each of the scan paths  1412 - 1418  of FIG. 14 are converted into low power scan paths  1602 - 1608 . Each of the low power scan paths  1602 - 1608  of FIG. 16 contain separate scan path segments A, B, and C arranged as shown and described previously in regard to FIG. 5.  
         [0083]    In the second modification step, an adaptor  1610  is inserted between the scan controller  1402  and scan paths  1602 - 1608 . Adaptor  1610  inputs control from scan controller  1402  via path  1404  and outputs control to scan paths  1602 - 1608  via path  1612 . From the general control state diagram example shown in FIG. 17, adaptor  1610  responds to scan controller  1402  output states (idle state  1502 , operate scan paths 1−N state  1504 , and capture response data state  1506 ) to output control state sequences  1702  (operate scan paths A  1704 , operate scan paths B  1706 , and operate scan paths C  1708 ) to scan paths  1602 - 1608 . As with previous adaptor descriptions, the control output from adaptor  1610  to scan paths  1602 - 1608  operates the scan paths  1602 - 1608  such that only one of the scan path segment groups (i.e. segment group A, B, or C) of scan paths  1602 - 1608  are enabled to shift data at a time.  
         [0084]    Since the adaptor&#39;s  1610  control input  1404  may come from any type of scan controller, such as the TAP, BIOS, or ATP mentioned above, the adaptor  1610  design will need to be customized to interface with the specific scan controller  1402  being used. In general, an adaptor  1610  can interface to any given scan controller by simply sensing when the scan controller starts a scan operation and sensing when the scan controller stops a scan operation. For example, when a scan controller starts a scan operation the adaptor starts executing its operate scan paths A, B, and C state sequence, and when the scan controller stops a scan operation the adaptor stops executing its operate scan paths A, B, and C state sequence.  
         [0085]    While FIG. 16 illustrates the adaptor  1610  as being a circuit separate from scan controller circuit  1402 , the two circuits can be designed as one circuit. For example, if it is desired to provide the low power scan mode of the present invention in a scan controller based architecture, the scan controller and the adaptor circuit functions may be integrated into a single circuit realization. The previously mentioned IEEE 1149.1 TAP scan controller may indeed be designed to include the adaptor&#39;s  1610  scan path segment A, B, and C sequencing functionality. Likewise, the previously mentioned BIOS or ATP scan controllers may indeed be designed to include the adaptor&#39;s  1610  scan path segment A, B, and C sequencing functionality.  
         [0086]    Daisy-chained Low Power Scan Paths  
         [0087]    [0087]FIG. 18 illustrates an IC  1800  having three intellectual property core circuits (core1, core2, core3)  1802 - 1806  configured into a daisy-chained arrangement for simultaneous parallel scan testing. Cores 1-3 could each be a DSP, CPU, or other circuit type. In the scan test configuration, each core includes a logic circuit to be tested, and N scan paths for communicating stimulus and response test patterns to the logic circuit. The scan paths 1−N of cores 1-3 are assumed to have the same length. The scan inputs of the core 1 scan paths are connected to a tester, such as tester  1008  of FIG. 10, via scan input paths  1808 . The scan outputs of the scan paths of core 1 are connected to the scan inputs of the core 2 scan paths via connections  1814 . The scan outputs of the scan paths of core 2 are connected to the scan inputs of the core 3 scan paths via connections  1816 . The scan outputs of the core 3 scan paths are connected to a tester, such as tester  1008  of FIG. 10, via scan output paths  1812 . The scan paths of cores 1-3 are connected to a control bus  1810  to synchronize their daisy-chained scan test operation. Control bus  1810  could be the control bus  1034  of tester  1008  of FIG. 10, or it could be the control bus  1404  of scan controller  1402  of FIG. 14.  
         [0088]    During test operation, the scan paths of cores 1-3 are controlled to repeat the steps of: (1) performing a capture operation to load response data from their respective logic circuits, and (2) performing a shift operation to unload response data to the tester via path  1812  and load the next stimulus data from the tester via path  1808 . The duration of the shift operation is such that all the daisy-chained scan paths are emptied of their captured response data and filled with their next stimulus data. From inspection of FIG. 18 it is seen that during the shift operation, the logic circuits of cores 1-3 receive rippling stimulus inputs which consumes power in the logic circuits.  
         [0089]    [0089]FIG. 19 illustrates an IC  1900  having three intellectual property core circuits (core1, core2, core3)  1902 - 1906  configured into a daisy-chained arrangement for simultaneous parallel scan testing. This example is provided to demonstrate that cores 1-3 could each have a different number of scan paths when configured into the test mode. For example, core 1 has two scan paths, core 2 has three scan paths, and core 3 has N scan paths. Scan paths 1 and 2 of cores 1-3 are serially connected between the tester scan outputs  1914  and  1916  of connection  1908  and the tester scan inputs  1922  and  1924  of connection  1912 . Scan paths 3 of core 2 and core 3 are serially connected between the tester scan output  1918  of connection  1908  and the tester scan input  1926  of connection  1912 . Scan paths 4−N of core 3 are serially connected between the tester scan outputs  1920  of connection  1908  and the tester scan inputs  1928  of connection  1912 .  
         [0090]    As in the FIG. 18 example, each core 1-3 of FIG. 19 includes a logic circuit to be tested, and stimulus and response connections between the logic circuits and the respective scan paths of each core. As in FIG. 18, the scan paths of cores 1-3 are assumed to have the same length. The scan paths of cores 1-3 are connected to a control bus  1910  to synchronize their daisy-chained scan test operation. As mentioned in regard to FIG. 18, control bus  1910  could come from a tester, such as tester  1008  or from a scan controller, such as scan controller  1402 .  
         [0091]    During test operation, the scan paths of cores 1-3 are controlled to repeat the steps of: (1) performing a capture operation to load response data from their respective logic circuits, and (2) performing a shift operation to unload response data to the tester via path  1912  and load the next stimulus data from the tester via path  1908 . The duration of the shift operation is such that the longest daisy-chained scan path arrangement (i.e. the daisy-chain arrangement of scan paths 1 and 2 of cores 1-3) is emptied of captured response data and filled with next stimulus data. The scan patterns communicated to the daisy-chained scan paths 3 between tester connections  1918  and  1926  will be padded with bit positions to balance their bit length to the bit length of the scan patterns communicated to the daisy-chained scan paths 1 and 2 between tester connections  1914 ,  1916 ,  1922 , and  1924 . Likewise, the scan patterns communicated to scan paths 4−N between tester connections  1920  and  1928  will be padded with additional bit positions to balance their length to the bit length of the scan patterns communicated to the daisy-chained scan paths 1 and 2 between connections  1914 ,  1916 ,  1922 , and  1924 . From inspection of FIG. 19 it is seen that during the shift operation, the logic circuits of cores-1-3 receive rippling stimulus inputs which consumes power in the logic circuits.  
         [0092]    Adapting Daisy-chained Scan Paths for Low Power Operation  
         [0093]    [0093]FIG. 20 illustrates IC  2000 , which is the IC  1800  after the scan paths 1−N of cores 1-3 of IC  1800  have been converted into low power scan paths 1−N. Besides the conversion of the conventional scan paths 1−N into low power scan paths 1−N, the IC  2000  is the same as that of IC  1800 . The cores 1-3 of FIG. 20 are the cores 1-3 of FIG. 18. The logic circuits of the cores 1-3 of FIG. 20 are the logic circuits of cores 1-3 of FIG. 18. The scan input connections  2008  of FIG. 20 are the scan input connections  1808  from the tester of FIG. 18. The scan output connections  2012  of FIG. 20 are the scan output connections  1812  to the tester of FIG. 18. The scan path connections  2014  and  2016  of FIG. 20 are the scan path connections  1814  and  1816  of FIG. 18. The low power scan paths of FIG. 20 are assumed to each be partitioned into separate scan path segments A, B, and C, as previously described in regard to the partitioning of scan path  104  of FIG. 1 into low power scan path  502  of FIG. 5. The scan paths of cores 1-3 of FIG. 20 are connected to a control bus  2010  to synchronize their daisy-chained scan test operation. The control bus  2010  of FIG. 20 differs from the control bus of FIG. 18 in that it comes from an adaptor, such as from adaptor  504  of FIG. 5, adaptor  1210  of FIG. 12, or adaptor  1610  of FIG. 16.  
         [0094]    During test operation, the low power scan paths of cores 1-3 are controlled to repeat the steps of: (1) performing a capture operation to load response data from their respective logic circuits, and (2) performing an adaptor controlled shift operation to unload response data to the tester via path  2012  and load the next stimulus data from the tester via path  2008 . The adaptor control sequences through the operate scan paths A, B, and C states as previously described in regard to state diagram  1302  of FIG. 13. The duration of the adaptor controlled shift operation is such that all the daisy-chained low power scan paths are emptied of their captured response data and filled with their next stimulus data. From inspection of FIG. 20 it is seen that during the adaptor controlled shift operation, the logic circuits of cores-1-3 receive rippling stimulus inputs only from the currently shifting scan paths A, B, or C of each low power scan path. Thus the power consumed by the core 1-3 logic circuits in FIG. 20 during shift operations is reduced from the power consumed by the core 1-3 logic circuits of FIG. 18 during shift operations.  
         [0095]    [0095]FIG. 21 illustrates IC  2100 , which is the IC  1900  after the scan paths of cores 1-3 of IC  1900  have been converted into low power scan paths 1−N. Besides the conversion of the conventional scan paths into low power scan paths, the IC  2100  is the same as that of IC  1900 , including the scan path connections to each other and to the tester as described in regard FIGS. 18 and 20 above. The low power scan paths of FIG. 21 are assumed to each be partitioned into separate scan path segments A, B, and C, as previously described in regard to the partitioning of scan path  104  of FIG. 1 into low power scan path  502  of FIG. 5. The scan paths of cores 1-3 of FIG. 21 are connected to a control bus  2110  to synchronize their daisy-chained scan test operation. The control bus  2110  of FIG. 21 differs from the control bus of FIG. 19 in that it comes from an adaptor, such as from adaptor  504  of FIG. 5, adaptor  1210  of FIG. 12, or adaptor  1610  of FIG. 16.  
         [0096]    During test operation, the low power scan paths of cores 1-3 are controlled to repeat the steps of: (1) performing a capture operation to load response data from their respective logic circuits, and (2) performing an adaptor controlled shift operation to unload response data to the tester via path  2112  and load the next stimulus data from the tester via path  2108 . The adaptor control sequences through the operate scan paths A, B, and C states as previously described in regard to state diagram  1302  of FIG. 13. The duration of the adaptor controlled shift operation is such that the longest daisy-chained low power scan path connection (i.e. the scan path 1 and 2 connections between cores 1-3) are emptied of their captured response data and filled with their next stimulus data. From inspection of FIG. 21 it is seen that during the adaptor controlled shift operation, the logic circuits of cores-1-3 receive rippling stimulus inputs only from the currently shifting scan paths A, B, or C of each low power scan path. Thus the power consumed by the core 1-3 logic circuits in FIG. 21 during shift operations is reduced from the power consumed by the core 1-3 logic circuits of FIG. 19 during shift operations.  
         [0097]    As previously described in regard to the test times of using scan paths  104  and  502  to test logic  108  of FIGS. 1 and 5, the test times of using the scan paths of FIGS. 18 and 20 to test the logic circuits of cores 1-3 are the same, as are the test times of using scan paths of FIGS. 19 and 21 to test the logic circuits of cores 1-3. Also, as previously described in regard to FIG. 9, the tester scan input and scan output pattern frames used for testing the FIG. 18 cores can be directly reused to test the FIG. 20 cores. Likewise, the test patterns used for testing the FIG. 19 cores can be reused to test the FIG. 21 cores.  
         [0098]    As mentioned, the scan paths of the FIGS. 18 and 19 circuits were assumed to be of equal length (M). Also, the corresponding low power scan paths of FIGS. 20 and 21 were assumed to be modified from the M length scan paths FIGS. 18 and 19 such that the scan path segments A, B, and C of each low power scan path are of equal length (M/3). With these assumptions made, a single adaptor circuit can be used to operate all the low power scan paths of cores 1-3 of FIGS. 20 and 21 during scan operations. The single adaptor circuit would sequence through three cycles of scan burst time intervals  802 ,  804 , and  806  of FIG. 8 during each scan operation. For example, using the scan operation timing diagram of FIG. 8 modified as described below, the scan operation of the FIGS. 20 and 21 scan paths can be understood. In FIG. 8, when SCANENA goes low at time  812  to start the scan operation, a first cycle of scan burst intervals  802 - 806  occurs, followed by SCANENA remaining low while a second cycle of scan burst intervals  802 - 806  occurs, followed by SCANENA remaining low while a third cycle of scan burst intervals  802 - 806  occurs. Following the third cycle of scan burst intervals  802 - 806  SCANENA returns high to end the scan operation.  
         [0099]    While the adaptor may be designed to operate the low power scan paths different from the operation described above, the above described operation maintains the ability to reuse the test pattern frames of the original scan paths of FIGS. 18 and 19. For example, each of the existing scan test pattern frames (stimulus and response) for the FIGS. 18 and 19 circuit can be viewed in the format of “[core1] [core2] [core3]”, where [core1] indicates the scan frame bit positions targeted for the core 1 scan paths, [core2] indicates the scan frame bit positions targeted for the core 2 scan paths, and [core3] indicates the scan frame bit positions targeted for the core 3 scan paths. It follows from the previous description given for FIG. 9 that; [core1] can be further viewed in a format of [C 1 B 1 A 1 ], [core2] can be further viewed in a format of [C 2 B 2 A 2 ], and [core3] can be further viewed in a format of [C 3 B 3 A 3 ], where the C 1,2,3 , B 1,2,3 , and A 1,2,3  subset bit positions are targeted for each low power scan path segment C, B, and A of cores 1-3 of FIG. 22 and  21 . The above described adaptor scan operation would operate to load and unload each subset C 1,2,3 , B 1,2,3 , A 1,2,   3  scan frame bit positions into the respective C, B, and A scan path segments of each low power scan path of FIGS. 20 and 21. The advantage to this, as mentioned in regard to FIG. 9, is that test pattern frames originally provided for the scan path arrangement of FIGS. 18 and 19 do not have to modified for use with the low power scan path arrangement of FIGS. 20 and 21.  
         [0100]    As mentioned in regard to the FIG. 19 daisy-chain arrangement, length compensating pad bit positions are included in the test pattern frames communicated to the daisy-chained scan paths 3 of cores 2 and 3, and in the test pattern frames communicated to scan paths 4−N of core 3. During the adaptor operated scan operation of the FIG. 21 circuit, these pad bit positions are communicated during the above mentioned cycles of scan burst timing intervals  802 - 806 , such that at the end of each adaptor controlled scan operation, all scan path segments A,B,C of all low power scan paths properly filled with stimulus and emptied of response.  
         [0101]    In FIG. 20, if the A,B,C segments of the low power scan paths of core 1 have the same length, the A,B,C segments of the low power scan paths of core 2 have the same length, and the A,B,C segments of the low power scan paths of core 3 have the same length, but the lengths of the A,B,C segments of the low power scan paths of cores 1-3 are not the same, separate adaptor interfaces will be needed to control the low power scan paths of each core 1-3. A first adaptor interface will be connected to the control input  2018  of core 1 to provide control of the core 1 A,B,C segments, a second adaptor interface will be connected to the control input  2020  of core 2 to provide control of the core 2 A,B,C segments, and a third adaptor interface will be connected to the control input  2022  of core 3 to provide control of the core 3 A,B,C segments. The use of separate adaptor interfaces allows each of the core 1-3 low power scan paths to be operated according to the scan burst timing intervals ( 802 - 806 ) required to communicate to each of the different length low power scan path A,B,C segments of cores 1-3. For example, if the A,B,C segment lengths of cores 1, 2, and 3 were 100, 300, and 900 respectively, the scan burst intervals ( 802 - 806 ) of core 1 would be set at 100 each, the scan burst timing intervals ( 802 - 806 ) of core 2 would be set at 300 each, and the burst timing intervals ( 802 - 806 ) of core 3 would be set at 900 each. A single adaptor circuit may be equipped with multiple separate interfaces for connection to control inputs  2018 - 2022 , or separate adaptor circuits may be interfaced to control inputs  2018 - 2022 . In a daisy-chained arrangement, as in FIG. 20, each core may have different A,B,C scan segment lengths. However for proper daisy-chain operation, each of the different core A,B,C scan lengths should be set to positive integer multiples of one another such that the adpator interfaces to each core can operate together during each scan operation cycle (i.e. from SCANENA going low at  812  to SCANENA going high at  814  in FIG. 8) to modulate the test patterns through all daisy-chained cores without loosing any of the stimulus and response pattern bits. For example, the 100, 300, and 900 A,B,C core scan segment lengths mentioned above have been set to where, during each scan operation cycle, the adpator of core 1 modulates test patterns through core 1 using multiple cycles of 100 bit scan burst intervals ( 802 - 806 ), the adpator of core 2 modulates test patterns through core 2 using multiple cycles of 300 bit scan burst intervals ( 802 - 806 ), and the adaptor of core 3 modulates test patterns through core 3 using multiple cycles of 900 bit scan burst intervals ( 802 - 806 ). Since 900 is a multiple of 300 and 300 is a multiple of 100, all A,B,C scan paths of cores 1-3 will be properly filled and emptied during each scan operation cycle.  
         [0102]    Scalable Scan Architecture Power Consumption  
         [0103]    As can be anticipated from the description given for the present invention, the power consumption of logic circuitry being tested by the low power scan architecture decreases as the number separate scan paths within the low power scan paths increases. For example, configuring a given conventional scan path into a low power scan path comprising two separate scan paths may reduce power consumption by up to 50%, since, during operation, each of the two separate scan paths separately charge and discharge one half, potentially, of the logic circuitry capacitance charged and discharged by the convention scan path. Further, configuring the same conventional scan path into a low power scan path comprising three separate scan paths may reduce power consumption by up to 66%, since, during operation, each of the three separate scan paths separately charge and discharge one third, potentially, of the logic capacitance charged and discharged by the convention scan path. Still further, configuring the same conventional scan path into a low power scan path comprising four separate scan paths may reduce power consumption by up to 75%, since, during operation, each of the four separate scan paths separately charge and discharge one fourth, potentially, the logic capacitance charged and discharged by the convention scan path. From this it is seen that the present invention allows a synthesis tool to be provided with the capability of scaling the power consumption of a given synthesized scan architecture to meet a desired low power mode of test operation of a circuit.  
         [0104]    Scalable Scan Architecture Noise Reduction  
         [0105]    As can be anticipated from the description given for the present invention, the noise generated by logic circuitry being tested by the low power scan architecture decreases as the number of separate scan paths within the low power scan paths increases. For example, configuring a given conventional scan path into a low power scan path comprising two separate scan paths may reduce noise generation by up to 50%, since, during operation, each of the two separate scan paths separately activate only one half, potentially, of the logic circuitry activated by the conventional scan path. Further, configuring the same conventional scan path into a low power scan path comprising three separate scan paths may reduce noise generation by up to 66%, since, during operation, each of the three separate scan paths separately activate only one third, potentially, of the logic circuitry activated by the convention scan path. Still further, configuring the same conventional scan path into a low power scan path comprising four separate scan paths may reduce noise generation by up to 75%, since, during operation, each of the four separate scan paths separately activate one fourth, potentially, of the logic circuitry activated by the convention scan path. From this it is seen that the present invention allows a synthesis tool to be provided with the capability of scaling the noise generation of a given synthesized scan architecture to meet a desired low noise mode of test operation of a circuit.  
         [0106]    Although the present invention has been described in accordance to the embodiments shown in the figures, one of ordinary skill in the art will recognize there could be variations to these embodiments and those variations should be within the spirit and scope of the present invention. Accordingly, modifications may be made by one ordinarily skilled in the art without departing from the spirit and scope of the appended claims.