Abstract:
A digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes a pulse width modulator to output a signal into a LC filter that generates a DC supply voltage. The width of the pulses output by the pulse width modulator are defined by an encoder that generates width information in response to a propagation delay detector that measures the propagation delay of a first clock signal when clocked by a second clock signal.

Description:
This is a divisional application of application Ser. No. 10/272,035 filed on Oct. 15, 2002 now U.S. Pat. No. 6,744,288. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to drivers and, more particularly, to a driver with a bulk switching MOS power transistor. 
   2. Description of the Related Art 
   A MOS transistor is a well-known circuit device that controllably varies the current that flows between a source region and a drain region. A MOS power transistor is a larger MOS transistor that is capable of handling much larger magnitudes of current. A driver is another well-known circuit device that utilizes a PMOS power transistor and an NMOS power transistor. 
   The PMOS transistor has a source connected to a voltage source, and a drain connected to an output node. In addition, the PMOS transistor has a gate, and an n-bulk that is connected to the voltage source. The NMOS transistor has a source connected to ground, and a drain connected to the output node. Further, the NMOS transistor has a gate, and a p-bulk that is connected to ground. 
   In operation, when an input signal transitions from a logic low to a logic high, the PMOS transistor turns off and the NMOS transistor turns on. As a result, the NMOS transistor pulls the output node to ground. On the other hand, when the input signal transitions from a logic high to a logic low, the NMOS transistor turns off and the PMOS transistor turns on. As a result, the PMOS transistor pulls the output node up to approximately the voltage source. 
   One of the advantages of the above-described driver is that only one transistor is on when the input logic state is either a logic high or a logic low. To minimize leakage current when the PMOS and NMOS transistors are turned off, the n-bulk and p-bulk, respectively, are held at the voltage source and ground, respectively. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram illustrating an example of a driver stage  100  in accordance with the present invention. 
       FIGS. 2A–2B  are timing diagrams illustrating the operation of gate signal generator  110  in accordance with the present invention. 
       FIG. 3  is a circuit diagram illustrating an example of a gate signal generator  110  in accordance with the present invention. 
       FIGS. 4A and 4B  are circuit diagrams illustrating examples of switches SW 1  and SW 2 , respectively, in accordance with the present invention. 
       FIG. 5  is a circuit diagram illustrating an output stage  500  in accordance with an alternate embodiment of the present invention. 
       FIGS. 6A–6B  are two views illustrating a layout  600  of PMOS transistor M 0  after the metal- 1  layer has been formed and patterned in accordance with the present invention. 
       FIGS. 7A–7B  are two views illustrating a layout  700  of PMOS transistor M 0  after the metal- 2  layer has been formed and patterned in accordance with the present invention.  FIG. 7A  is a plan view, while  FIG. 7B  is a cross-sectional view taken along lines  7 B— 7 B of  FIG. 7A . 
       FIGS. 8A–8B  are two views illustrating a layout  800  of PMOS transistor M 0  after the metal- 4  layer has been formed and patterned in accordance with the present invention.  FIG. 8A  is a plan view, while  FIG. 8B  is a cross-sectional view taken along lines  8 B— 8 B of  FIG. 8A . 
       FIG. 9  is a cross-sectional view taken along lines  8 B— 8 B of  FIG. 8A  illustrating a layout  900  after the formation of solder balls in accordance with the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows a block diagram that illustrates an example of a driver stage  100  in accordance with the present invention. As shown in  FIG. 1 , driver stage  100  includes a p-channel MOS transistor M 0  that has a p+ source connected to a supply voltage VDD, and a p+ drain connected to a first node N 1 . In addition, PMOS transistor M 0  has a gate, and an n-well connected to a second node N 2 . 
   Driver stage  100  also has an n-channel MOS transistor M 5  that has an n+ source connected to ground VSS, and an n+ drain connected to first node N 1 . In addition, NMOS transistor M 5  has a gate, and a p-substrate connected to a bulk voltage VBULK. PMOS transistor M 0  is a large driver transistor that sources a large current to first node N 1 , while NMOS transistor M 5  a large driver transistor that sinks a large current from first node N 1 . 
   As further shown in  FIG. 1 , driver stage  100  includes a gate signal generator  110  that outputs a PMOS gate signal G 1  to transistor M 0 , an NMOS gate signal G 2  to transistor M 5 , and a control signal CS. Gate signals G 1  and G 2  are non-overlapping, while control signal CS can be implemented as the inverse of gate signal G 1 . 
     FIGS. 2A–2B  show timing diagrams that illustrate the operation of gate signal generator  110  in accordance with the present invention. As shown in  FIGS. 2A–2B , gate signal generator  110  outputs the gate signals G 1  and G 2  so that the voltage on gate signal G 2  is equal to or less than a turn off voltage TF 1  (that turns off transistor M 5 ) before the voltage on gate signal G 1  is equal to a turn on voltage TN 1  (that turns on transistor M 0 ). Similarly, the voltage on gate signal G 1  is equal to or greater than a turn off voltage TF 2  (that turns off transistor M 0 ) before the voltage on gate signal G 2  is equal to a turn on voltage TN 2  (that turns on transistor M 5 ). 
   The turn off voltages TF 1  and TF 2  turn off transistors M 5  and M 0 , respectively, such that no current flows out of the drains of the transistors (other than a very small leakage current). The turn on voltages TN 1  and TN 2  turn on transistors M 0  and M 5 , respectively, such that a current in excess of a leakage current flows out of the drains of the transistors. 
   Thus, as shown in  FIGS. 2A–2B , gate signal generator  110  prevents transistors M 0  and M 5  from being turned on at the same time. By preventing transistors M 0  and M 5  from being turned on at the same time, gate signal generator  110  saves the power that would be wasted if transistor M 5  sunk current directly from transistor M 0 . 
     FIG. 3  shows a circuit diagram that illustrates an example of a gate signal generator  300  in accordance with the present invention. As shown in  FIG. 3 , gate signal generator  300  has a p-channel delay path  310  that includes a p-path inverter  312 , and an n-channel delay path  314  that includes an n-path inverter  316 . 
   P-path inverter  312  includes a PMOS transistor M 8  and a NMOS transistor M 7  that have gates connected to a gate node NG 1  and drains that are connected to the gate of transistor M 0 . In addition, in this example, the control signal CS is taken from the p-path  310  and output from the gate node NG 1 . 
   Further, as shown in  FIG. 3 , p-path  310  can include additional inverters that are connected in series. For example, p-path  310  can include inverter IV 1 , which is formed from transistors M 9 /M 10 , that has an input IN 1  and an output OT 1  that is connected to the gate node NG 1 . In addition, path  310  can include an inverter IV 2 , which is formed from transistors M 11 /M 12 , that has an input IN 2  and an output OT 2  that is connected to input IN 1 . 
   N-path inverter  316  includes a PMOS transistor M 18  and an NMOS transistor M 15  that have gates connected to a gate node NG 2  and drains that are connected to the gate of transistor M 5 . Further, as shown in  FIG. 3 , n-path  314  can include additional inverters that are connected in series. 
   For example, n-path  314  can include inverter IV 3 , which is formed from transistors M 14 /M 17 , that has an input IN 3  and an output OT 3  that is connected to the gate node GN 2 . In addition, path  314  can include an inverter IV 4 , which is formed from transistors M 13 /M 16 , that has an input IN 4  and an output OT 4  that is connected to input IN 3 . 
   The transistors in the p-channel and n-channel delay paths  310  and  314  are sized to provide the required edge timing shown in  FIG. 2 . For example, in the  FIG. 3  embodiment, p-channel transistor M 8  is 3× larger than p-channel transistor M 18 . As a result, transistor M 8  sources 3× more current than transistor M 18  which, in turn, allows transistor M 8  to raise the voltage on the gate of transistor M 0  faster than transistor M 18  can raise the voltage on the gate of transistor M 5 . 
   Returning again to  FIG. 1 , driver stage  100  additionally includes a first switch SW 1  that is connected to the control signal CS, and the well of transistor M 0  via node N 2 ; and a second switch SW 2  that is connected to ground VSS and the control signal CS. In addition, driver stage  100  includes a resistor R 46  that is connected to the well of transistor M 0  via node N 2  and to switch SW 2 . 
   As shown in  FIG. 4B , switch SW 2  can be implemented as an n-channel MOS transistor M 27  that has an n+ source connected to ground VSS and an n+ drain connected to resistor R. In addition, transistor M 27  has a gate connected to the control signal CS, and a substrate connected to a p bulk voltage PBULK. 
   As shown in  FIG. 4B , switch SW 2  can be implemented as a n-channel MOS transistor M 27  that has an n+ source connected to ground VSS and an n+ drain connected to resistor R. In addition, transistor M 27  has a gate connected to the control signal CS, and a substrate connected to a p bulk voltage PBULK. 
   In operation, driver stage  100  sinks current from node N 1  when transistor M 0  is turned off and transistor M 5  is turned on. Transistor M 5  turns on when the voltage of gate signal G 2  rises such that the gate-to-source voltage is greater than the threshold voltage of transistor M 5 . 
   The voltage of gate signal G 1  also rises to turn off transistor M 0 . At the same time, the control signal CS, which is the inverse of the gate signal G 1 , falls. The falling control signal CS, in turn, closes switch SW 1  and opens switch SW 2 . When switch SW 1  closes, the voltage on the well of transistor M 0  is pulled up to approximately the supply voltage VDD. 
   In addition, driver stage  100  sources current into node N 1  when transistor M 0  is turned on and transistor M 5  is turned off. Transistor M 0  turns on when the voltage on gate signal G 1  falls such that the gate-to-source voltage is less than the threshold voltage of transistor M 0 . 
   At the same time, the control signal CS, which is the inverse of the gate signal G 1 , rises. The rising control signal CS opens switch SW 1  and closes switch SW 2 . When switch SW 2  closes, the voltage on the well of transistor M 0  is pulled down towards ground via a trickle of current that flows through resistor R 46 . 
   With respect to the examples shown in  FIGS. 3 ,  4 A, and  4 B, the control signal CS goes low when the gate signal G 1  goes high to turn off transistor M 0 , thereby turning off transistor M 27  and turning on transistor M 31 . When transistor M 31  turns on, the voltage on the well of transistor M 0  is pulled up to approximately the supply voltage VDD. 
   On the other hand, the control signal CS goes high when the gate signal G 1  goes low to turn on transistor M 0 , thereby turning off transistor M 31  and turning on transistor M 27 . When transistor M 27  turns on, the voltage on the well of transistor M 0  is pulled down towards ground via a trickle of current that flows through resistor R 46 . 
   Thus, the present invention provides a bulk switching that pulls down the voltage on the n bulk of PMOS transistor M 0  when transistor M 0  is turned on, and pulls up the voltage on the n bulk of transistor M 0  when transistor M 0  is turned off. By pulling the n bulk down during the on state, the threshold voltage of transistor M 0  can be increased by several hundred millivolts. 
   Since the threshold voltage of transistor M 0  can be reduced, driver stage  100  can operate at a lower supply voltage and, therefore, requires less power to operate. In addition, by pulling the n bulk up during the off state, the lower leakage current associated with a high n bulk can be realized. 
   Further, since PMOS transistor M 0  is a driver transistor, transistor M 0  is a high-voltage transistor that has a threshold voltage of about −1V. For a low-voltage supply, e.g., 2.6V, a 0.3V or 0.4V improvement in the threshold voltage provides about a 10% total improvement in the drain-to-source turn on resistance of PMOS transistor M 0 . This, in turn, reduces the silicon area that is required by PMOS transistor M 0  by about 10% since the transconductance is a linear function of the gate voltage in the linear and subthreshold region. 
     FIG. 5  shows a circuit diagram that illustrates a driver stage  500  in accordance with an alternate embodiment of the present invention. Stage  500  is similar to stage  100  and, as a result, utilizes the same reference numerals to designate the structures which are common to both stages. 
   As shown in  FIG. 5 , stage  500  differs from stage  100  in that stage  500  includes a third switch SW 3  that is connected to and between the well of PMOS transistor M 0  and the supply voltage VDD, and controlled by an enable signal EN. Switch SW 3  can be implemented with, for example, PMOS transistor M 31 . In this case, the source and well of transistor M 31  are connected to the supply voltage, the drain to node N 2 , and the gate to the enable signal EN. 
   As further shown in  FIG. 5 , stage  500  additionally includes a fourth switch SW 4  that is connected to and between resistor R and switch SW 2 , and controlled by the enable signal EN. Switch SW 4  can be implemented with, for example, NMOS transistor M 27 . In this case, the source is connected to switch SW 2 , the drain is connected to resistor R 46 , and the gate is connected to the enable signal EN. 
   In operation when the enable signal EN is a logic low, switch SW 3  is open while switch SW 4  is closed. When switch SW 4  is closed, the voltage on the well of PMOS transistor M 0  is pulled up to about the supply voltage VDD and held there as transistor M 0  is turned on and off. 
   On the other hand, when the enable signal EN is a logic high, switch SW 3  is closed, while switch SW 4  is open. When switch SW 3  is closed and switch SW 4  is open, stage  500  operates the same as stage  100 . Thus, stage  500  provides an enable capability that allows the voltage on the n-well of PMOS transistor M 0  to be held high rather than be switched low when transistor M 0  turns on. 
   The enable signal EN can be used in a number of different ways. For example, the enable signal EN can be used to form a driver with an adjustable PMOS threshold voltage. When the enable signal EN is deasserted and the n bulk is held high, PMOS transistor M 0  has a first threshold voltage, e.g., −1V. 
   On the other hand, when the enable signal EN is asserted and the bulk switching is enabled, PMOS transistor M 0  has a second threshold voltage, e.g., −0.8V, that is higher than the first threshold voltage. In addition, the enable signal EN allows the bulk switching to be disabled for use in high voltage applications, and can be used with a clock signal to turn the bulk switching on and off. 
   In addition, rather than connecting switch SW 1  to the supply voltage VDD, switch SW 1  can alternately be connected to a voltage source that is higher than the supply voltage VDD. In this embodiment, the threshold voltage of PMOS transistor M 0  can be lowered even further when the bulk switching is enabled. 
     FIGS. 6A–6B  show two views that illustrate a layout  600  of PMOS transistor M 0  after the metal- 1  layer has been formed and patterned in accordance with the present invention.  FIG. 6A  shows a plan view, while  FIG. 6B  shows a cross-sectional view taken along lines  6 B— 6 B of  FIG. 6A . As shown in  FIGS. 6A–6B , layout  600  includes an n-well  610 , and a strip of a p+ source region  612  that is formed in an n-well  610 . 
   Layout  600  also includes a strip of a p+ drain region  614  that is formed in an n-well  610  a distance apart from source region  612 , and a channel region  616  that is located between source and drain regions  612  and  614 . Layout  600  further includes a strip of a p+ source region  620  that is formed in an n-well  610  a distance apart from drain region  614 , and a channel region  622  that is located between source and drain regions  620  and  614 . 
   Further, layout  600  includes a strip of a p+ drain region  624  that is formed in an n-well  610  a distance apart from source region  620 , and a channel region  626  that is located between source and drain regions  620  and  624 . Additional strips of p+ source and drain regions can be used to increase the size of transistor M 0 . 
   As shown in  FIGS. 6A–6B , layout  600  further includes a layer of gate oxide  630  that is formed over channel region  616 , and a polysilicon gate strip  632  that is formed on oxide layer  630  over channel region  616 . In addition, both ends of polysilicon gate strip  632  extend out over a field oxide region FOX. 
   A layer of gate oxide  634  is also formed over channel region  622 , and a polysilicon gate strip  636  is formed on oxide layer  634  over channel region  622 . Both ends of polysilicon gate strip  636  also extend out over the field oxide region FOX. A layer of gate oxide  640  is further formed over channel region  626 , and a polysilicon gate strip  642  is formed on oxide layer  640  over channel region  626 . Both ends of polysilicon gate strip  642  extend out over the field oxide region FOX. As further shown in  FIG. 6A , polysilicon gate strips  632 ,  636 , and  642  on both ends are connected together via a polysilicon interconnect line PL. 
   Gate strip  632  has a number of segments  632 -SG, and a number of linking sections  632 -LS that connect together adjacent segments  632 -SG. Similarly, gate strip  636  has a number of segments  636 -SG, and a number of linking sections  636 -LS that connect together adjacent segments  632 -SG. Gate strip  642  also has a number of segments  642 -SG, and a number of linking sections  642 -LS that connect together adjacent segments  642 -SG. 
   In addition, the segments  632 -SG of gate strip  632 , the segments  636 -SG of gate strip  636 , and the segments  642 -SG of gate strip  642  are substantially parallel. Each segment  632 -SG of gate strip  632  also has a corresponding segment  636 -SG of gate strip  636 . 
   Each segment  632 -SG and the corresponding segment  636 -SG form a segment pair  650  that has a width measured substantially normal to both segments  632 -SG and  636 -SG. Further, the width of each adjacent segment pair  650  alternates between a first width W 1  and a second width W 2  that is wider than first width W 1 . 
   In addition, each segment  636 -SG of gate strip  636  has a corresponding segment  642 -SG that lies a distance apart. Each segment  636 -SG and the corresponding segment  642 -SG form a segment pair  652  that has a width measured substantially normal to both segments  636 -SG and  642 -SG. 
   Further, the width of each adjacent segment pair  652  alternates between a third width W 3  and a fourth width W 4  that is wider than third width W 3 . In addition, each segment pair  650  has a corresponding and adjoining segment pair  652 . When a segment pair  650  has the second width, the corresponding segment pair  652  has the third width. Similarly, when a segment pair  650  has the first width, the corresponding segment pair  652  has the fourth width. 
   As shown in  FIG. 6A , a number of adjacent segment pairs  650  forms an alternating series of wide and narrow regions  660  and  662 , respectively, while a number of adjacent segment pairs  652  forms an alternating series of wide and narrow regions  664  and  666 , respectively. 
   In addition to the above, layout  600  also includes a layer of isolation material  670 , and a number of contacts  672  that are formed through isolation material  670  to make an electrical connection with source strip  612 , drain strip  614 , source strip  620 , drain strip  624 , and interconnect line PL. The contacts  672 , in turn, are formed generally in the middle of each wide region  660  and  664 , and periodically on interconnect line PL. 
   Further, layout  600  includes a plurality of strips of metal- 1  that include a source strip  680 , a drain strip  682 , a source strip  684 , a drain strip  686 , and an interconnect strip  688 . Source strip  680  is formed on isolation material  670  to make electrical contact with the contacts  672  that make an electrical connection with p+ source strip  612 . 
   Drain strip  682  is formed on isolation material  670  to make electrical contact with the contacts  672  that make an electrical connection with p+ drain strip  614 . Source strip  684  is formed on isolation material  670  to make electrical contact with the contacts  672  that make an electrical connection with p+ source strip  620 . 
   Drain strip  686  is formed on isolation material  670  to make electrical contact with the contacts  672  that make an electrical connection with p+ drain strip  624 . Interconnect strip  688  is formed on isolation material  670  to make electrical contact with the contacts  672  that make an electrical connection with polysilicon interconnect line PL which, in turn, is connected to gate strips  632 ,  636 , and  642 . 
   Thus, in accordance with the present invention, a layout has been described that utilizes a plurality of serrated gate structures that allow the source and drain regions to contacted frequently. The result is a 25% savings in space over conventional layouts. 
   In addition, picking up the gate strips on both ends with a layer of interconnect polysilicon and a metal- 1  strip reduces the distributed RC delay associated with the gate strips (the resistance of the polysilicon strips and the capacitance under the gate strips) by a factor of two to three times. 
     FIGS. 7A–7B  show two views that illustrate a layout  700  of PMOS transistor M 0  after the metal- 2  layer has been formed and patterned in accordance with the present invention.  FIG. 7A  shows a plan view, while  FIG. 7B  shows a cross-sectional view taken along lines  7 B— 7 B of  FIG. 7A . As shown in  FIGS. 7A–7B , layout  700  is the same as layout  600  except that layout  700  shows the additional formation of a layer of isolation material  710 , vias  712  that are formed through isolation layer  710 , and a plurality of strips of metal- 2 . 
   The metal- 2  strips include a source strip  714 , a drain strip  716 , a source strip  720 , and a drain strip  722 . Source strip  714  is formed on isolation material  710  to make electrical contact with the vias  712  that make an electrical connection with source strip  780 . 
   Drain strip  716  is formed on isolation material  710  to make electrical contact with the contacts  712  that make an electrical connection with drain strip  682 . Source strip  720  is formed on isolation material  710  to make electrical contact with the contacts  712  that make an electrical connection with p+ source strip  684 . 
   Drain strip  722  is formed on isolation material  712  to make electrical contact with the contacts  712  that make an electrical connection with drain strip  686 . (Although not shown, a metal- 2  interconnect strip is formed over the metal- 1  interconnect strip  688  and electrically connected by vias.) 
     FIGS. 8A–8B  show two views that illustrate a layout  800  of PMOS transistor M 0  after the metal- 4  layer has been formed and patterned in accordance with the present invention.  FIG. 8A  shows a plan view, while  FIG. 8B  shows a cross-sectional view taken along lines  8 B— 8 B of  FIG. 8A . As shown in  FIGS. 8A–8B , layout  800  is the same as layout  700  except that layout  800  shows the additional formation of a layer of isolation material  810 , vias  812  that are formed through isolation layer  810 , and a plurality of strips of metal- 3 . 
   The metal- 3  strips include a source strip  814 , a drain strip  816 , a source strip  820 , and a drain strip  822 . Source strip  814  is formed on isolation material  810  to make electrical contact with the vias  812  that make an electrical connection with source strip  714 . Drain strip  816  is formed on isolation material  810  to make electrical contact with the vias  812  that make an electrical connection with drain strip  716 . 
   Source strip  820  is formed on isolation material  810  to make electrical contact with the contacts  812  that make an electrical connection with p+ source strip  720 . Drain strip  822  is formed on isolation material  810  to make electrical contact with the vias  812  that make an electrical connection with drain strip  722 . (Although not shown, a metal- 3  interconnect strip is formed over the metal- 2  interconnect strip and electrically connected by vias.) 
   Layout  800  shows the additional formation of a layer of isolation material  830 , vias  832  that are formed through isolation layer  830 , and two triangles of metal- 4 . The metal- 4  triangles include a source triangle  834  and a drain triangle  836 . Source triangle  834  is formed on isolation material  830  to make electrical contact with all of the vias  812  that make an electrical connection with metal- 3  source strips, including source strips  814  and  820 . Drain triangle  836  is formed on isolation material  830  to make electrical contact with all of the vias  832  that make an electrical connection with metal- 3  drain strips, including drain strips  816  and  822 . 
     FIG. 9  shows a cross-sectional view taken along lines  8 B— 8 B of  FIG. 8A  that illustrates a layout  900  after the formation of solder balls in accordance with the present invention. As shown in  FIG. 9 , layout  900  is the same as layout  800  except that layout  900  shows the additional formation of a layer of isolation material  910 , vias  912  that are formed through isolation layer  910 , and a plurality of solder balls  914 . Solder balls  914  are formed as big balls to minimize parasitic contributions to the source-to-drain turn on resistance of PMOS transistor M 0 . 
   Other than differing conductivity types (e.g., n+ source and drain regions in lieu of p+ source and drain regions), the layout of transistor M 5  of  FIG. 1  is the same as the layout of transistor M 0  of  FIG. 1 . In accordance with an alternate embodiment of the present invention, the contacts and vias used in PMOS transistor M 0  are larger (wider) than the contacts and vias used in NMOS transistor M 5 . 
   As a result, the larger contacts used on PMOS transistor M 0  reduce the resistance associated with the contacts. (Larger contacts are not used on the NMOS transistor M 5  because the p+ source, n-channel region, and p+ drain form a parasitic bipolar transistor which, in response to transients, can exhibit snapback characteristics if the transients exceed the rail or falls below ground.) 
   In accordance with a further embodiment of the present invention, the source regions (which correspond with the emitter of the parasitic bipolar transistor) of NMOS transistor M 5  are wider than the drain regions of NMOS transistor M 5  (while the source and drain regions both have the same length and depth). In this embodiment, the contacts and vias of PMOS transistor M 0  are the same size as the contacts and vias of NMOS transistor M 5 , however, NMOS transistor has more gate strips than PMOS transistor M 0 . 
   Increasing the width of the source regions effectively increases the resistance. Since the source regions function as the emitter regions of the parasitic bipolar transistor, increasing the widths of the source regions is equivalent to adding resistance to the emitter of a bipolar transistor. 
   By ballasting, adding resistance to the emitter, a large number of bipolar transistors can be placed in parallel without one transistor, usually the center one, heating up and hogging the current. Thus, the wider source regions more evenly distribute the current and reduce the likelihood that the parasitic bipolar transistors in NMOS transistor M 5  will enter snapback and fail. 
   Thus, an output driver stage, including the layout of the PMOS driver transistor of the output stage, has been described. The present invention utilizes both circuit techniques (pulling down the well) and layout techniques, (serrated gate structures) to obtain approximately a 25%–35% improvement in the source-to-drain turn on resistance of PMOS transistor M 0 . 
   It should be understood that the above descriptions are examples of the present invention, and various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.