Abstract:
A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current.

Description:
TECHNICAL FIELD 
     This subject matter is generally related to electronics, and more particularly to low power sense amplifiers for reading memory. 
     BACKGROUND 
     Low power devices like Radio Frequency Identification (RFID) tags need low read currents in their embedded non-volatile memory (NVM) to maximize reading distance from an RFID transmitter. One known approach to sensing the state of a NVM cell is to set up read conditions on the memory cell and compare a cell current to a reference current that is generated in a sense amplifier. There are several known circuit designs to produce the reference current. A drawback of these designs, however, is that direct current is consumed by each sense amplifier. The direct current consumption can be in the order of 10s of microamperes to 100s of microamperes per sense amplifier depending on the read speed desired. The direct current consumed is multiplied by the number of sense amplifiers in the circuit. This total current adversely affects the read range of the RFID tag. The direct current can be reduced somewhat by slowing the sense amplifier, but it cannot be reduced beyond a certain point because there is a maximum read time allowed in the system. 
     SUMMARY 
     A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current. 
     The low power sense amplifier may include one or more of the following advantages: 1) reducing the average and instantaneous power requirements of the low power sense amplifier to approximately 1 microampere per sense amplifier or less, when operated at 500 KHz; 2) eliminating the need for a reference current; and 3) eliminating the need for direct current (dc) consumed in the low power sense amplifier when reading or not reading memory. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic diagram of a low power sense amplifier. 
         FIG. 2  is a timing diagram illustrating a read “0” memory transaction performed by the low power sense amplifier of  FIG. 1 . 
         FIG. 3  is a timing diagram illustrating a read “1” memory transaction performed by the low power sense amplifier of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary Circuit Design 
       FIG. 1  is a schematic diagram of a low power sense amplifier  100 . In some implementations, the power sense amplifier  100  can include pre-charge circuit  103 , sense capacitor circuit  105 , voltage detection circuit  107 , delay path  109  and output latch circuit  120 . 
     Pre-charge circuit  103  can include transistor  102  (e.g., a p-channel transistor) and optionally current limiting resistor  104 . The gate terminal of transistor  102  is coupled to a read sense input (read_sense). The source terminal of transistor  102  is coupled to a reference voltage (vdd), and the drain terminal of transistor  102  is coupled to resistor  104 . Alternatively, resistor  104  can be omitted and the drain terminal of transistor  102  can be coupled to the drain terminal of transistor  108  (e.g., p-channel transistor). 
     Sense capacitor circuit  105  can include sense capacitor  106  and transistor  108 . The gate terminal of transistor  108  is coupled to delay path  109 . The source terminal of transistor  108  is coupled to a first terminal of sense capacitor  106 . A second terminal of sense capacitor  106  can be coupled to ground (gnd). The drain terminal of transistor  108  is coupled to the drain terminal of transistor  102  (or optionally resistor  104 ) and voltage detection circuit  107 . The drain terminals of transistors  102 ,  108  are coupled to a memory output line (oline), which can be coupled to a memory cell through a y-decoding path (not shown). 
     Voltage detection circuit  107  can include Schmitt trigger  114  and series inverters  116 ,  118 . The input of the Schmitt trigger  114  is coupled to the memory output line (oline). The output of the Schmitt trigger  114  is coupled to the input of inverter  116 . The output of inverter  116  is coupled to the input of inverter  118 . The output of inverter  118  is coupled to the gate terminal of transistor  112  (e.g., n-channel transistor). 
     Delay path  109  can include series inverters  110   a - 110   c  and transistor  112 . The three series inverters can optionally be replaced with an odd number of inverters. The input of inverter  110   a  is coupled to the gate terminal of transistor  108  and the gate terminal of transistor  112 . The output of inverter  110   c  is coupled to the source terminal of transistor  112 . The drain terminal of transistor  112  is coupled to output latch  120 . 
     Output latch circuit  120  can include inverter  122 , NAND gate  126  and resistor  124 . The input of inverter  122  is coupled to the drain of transistor  112  and a first terminal of resistor  124 . The output of inverter  122  is coupled to a first input of NAND gate  126  and the input of inverter  128 . A second terminal of resistor  124  is coupled to the output of NAND gate  126 . A second input of NAND gate  126  is a sense amplifier reset input (sa_resetb). The output of inverter  128  is a data output line (dout). In some implementations, resistor  124  is optional and can be omitted. In such a configuration, the output of NAND gate  126  can be directly coupled to the input of inverter  122 . 
     Having now described an exemplary implementation of low power sense amplifier  100 .  FIGS. 2 and 3  (with reference to  FIG. 1 ), will now be described to illustrate the operation of sense amplifier  100  during read “0” and read “1” memory transactions. 
     Exemplary Read “0” Transaction 
       FIG. 2  is a timing diagram illustrating a read “0” memory transaction performed by the power sense amplifier  100  of  FIG. 1 . During a pre-charge phase (from time t 0  to time t 1 ), read_sense input (a timed signal) is low, causing sense capacitor  106  to be charged slowly to the reference voltage (vdd) using transistor  102  through optional resistor  104 . During the pre-charge phase, the voltage on the gate terminal of transistor  108  is low, allowing sense capacitor  106  to be charged to a voltage (ncap) equal to the voltage reference (vdd). While read_sense input is low, sa_resetb input is pulsed low (at time t 0 ) to set the output of NAND gate  126  high, and thus the data output line (dout) is also set high (at time t 2 ) by virtue of series inverters  122 ,  128 . 
     When read_sense input is high during a sensing phase (e.g., during time t 1 -t 3 ), the pre-charge path through transistor  102  is cut off. The memory output line (oline) is at the reference voltage (vdd) and its voltage might dip slightly due to charge sharing. The size of sense capacitor  106  can be selected to be significantly larger than the capacitance on the memory output line (oline) to avoid a large dip in voltage due to charge sharing. The voltage (ncap) stored on sense capacitor  106  starts discharging due to the memory cell current. The slope of the voltage on the memory output line (oline) depends on the memory cell current. Once the voltage on the memory output line (oline) voltage reaches a threshold voltage level of Schmitt trigger  114  (at time t 2 ), the output terminal of Schmitt trigger  114  goes high, causing the output of inverter  116  to go low and the voltage on the gate terminal of transistor  108  to go high. The high voltage on the gate terminal of transistor  108  causes transistor  108  to be turned off due to the connection of the gate terminal of transistor  108  to the output of inverter  118 . Sense capacitor  106  is disconnected from the memory output line (oline). At this time the memory output line (oline) may continue to discharge (e.g., discharge to ground) due to the memory cell current, as illustrated in  FIG. 2 , or the discharge may end earlier, depending on the timing of the read. However, the voltage on the sense capacitor  106  remains at the threshold of the voltage detection circuit  107 . The sense capacitor  106  does not need to be pre-charged from ground potential, thus resulting in a lower current operation of the circuit. 
     When the voltage on the gate terminal of transistor  108  is high, the gate terminal of transistor  112  is also high and transistor  112  is open. With transistor  112  open, inverters  110   a - 110   c  will invert and delay the voltage on the gate terminal of transistor  108 . A low voltage on the source terminal of transistor  112  (output of inverter  110   c ) overpowers output latch  120  at the output of inverter  122  and pulls the voltage at the input of inverter  122  low. The output of inverter  128  or data output line (dout) will go low as a result (at time t 2 ). 
     Exemplary Read “1” Transaction 
       FIG. 3  is a timing diagram illustrating a read “1” memory transaction performed by the low power sense amplifier  100  of  FIG. 1 . If a memory cell has a higher threshold and negligible cell current, the memory output line (oline) will not discharge enough so as to trip Schmitt trigger  114 . The data output line (dout) remains high. The memory output line (oline) is disconnected from the memory cell when the read_sense input goes low (at time t 2 ). This starts a pre-charge of the memory output line (oline) and the voltage on the gate terminal of transistor  108  goes low, thus opening transistor  108 . While sense capacitor  106  charges back to the reference voltage (vdd) for the next read, sa_resetb input (a timed signal) is pulsed low (at time t 3 ) to set the data output line (dout) back to high for all sense amplifiers in the circuit, including the sense amplifiers that read a “0.” 
     While this document contains many specific implementation details, these should not be construed as limitations on the scope what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination.