Abstract:
An A/D conversion system for an image sensor. The image sensor acquires image signals, and outputs them to a plurality of sample and hold circuits. The sample and hold circuits are grouped and are commonly actuated, in order to simplify the control circuit. Once the signals are in the sample and hold circuits, the next clock cycle commonly actuates a plurality of A/D converters which commonly convert all of those signals. During that same clock cycle, another set of sample and hold circuits may be actuated.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims priority from provisional application number 60/253,430, filed Nov. 27, 2000. 
     
    
     
       BACKGROUND OF INVENTION  
         [0002]    Image sensors often use high-speed A/D converters. These converters must strike a balance between speed and power consumption. Faster converters will allow faster image acquisition. However, these often consume much more power than other, slower, converters.  
           [0003]    A successive approximation A/D converter may represent a good trade-off between speed and power consumption. It has been suggested to use multiple successive approximation A/D converters in a pipeline type architecture. The conversion of the multiple pixels is thus pipelined, thereby increasing the overall conversion speed, while maintaining the advantageous power consumption characteristics of the successive approximation converter.  
           [0004]    Generation of multiple timing and control signals for such a pipelined system may be complicated.  
         SUMMARY OF INVENTION  
         [0005]    The present application teaches a new architecture which enables high speed A/D conversion, with multiple successive approximation cells in the conversion system.  
           [0006]    According to an embodiment, groups of sample and hold circuits, and groups of A/D converters are controlled using a clocking scheme. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0007]    These and other aspects will now be described in detail with reference to the accompanying drawings, wherein:  
         [0008]    [0008]FIGS. 1A and 1B show a system using two clocks;  
         [0009]    [0009]FIGS. 2A and 2 b  show a 3 clock system; and FIG. 3 illustrates system latency. 
     
    
     DETAILED DESCRIPTION  
       [0010]    It has been suggested to generate multiple timing and control signals for multiple successive approximation A/D converters using a number of different techniques. One technique has suggested using a single clock generator, and N×K delay units, in order to obtain N sets of control signals. While this may be practical, it also represents a relatively complex circuit that needs to be implemented on the silicon substrate.  
         [0011]    Another technique allows using N individual clock generators, to obtain N sets of control signals. This also takes a relatively larger silicon area.  
         [0012]    The present system discloses techniques of a new architecture for forming and controlling control signals of this type. Since these techniques facilitate controlling multiple A/D converters, they effectively may increase the number of A/D converters which can be used.  
         [0013]    The two different architecture embodiments are respectively shown in FIGS. 1 and 2.  
         [0014]    [0014]FIGS. 1A and 1B show an embodiment using two separate clock generators for two different groups of converters. This embodiment uses an image sensor  99  which includes an array of pixel based photoreceptors. Each photoreceptor receives information indicative of incoming radiation for specific pixels and produces an output signal indicative thereof. The image sensors may have any number of pixels in the array. For example, arrays of 640 by 480 are quite common.  
         [0015]    The image sensor may be of any type, including photodiodes, photogates or any other standard type. A particularly preferred type is an active pixel sensor of a type known in the art, which is formed using MOS technology and which allows other MOS and/or CMOS circuitry to be located on the same substrate as the photoreceptor. In a preferred embodiment, all of the associated conversion circuits, clock generation circuits, and controlling circuits are located on the same semiconductor substrate as the image sensor.  
         [0016]    In this embodiment, there are N of the successive approximation A/D converters, where N can be any number, preferably an even number, and preferably greater than 2. This system may have maximum advantages when used with N&gt;=4, although its simplicity advantages may obtain even more advantages when used with higher numbers of A/D converters.  
         [0017]    Each A/D converter is associated with a respective M bit digital buffer. The digital buffers can be conceptualized as sample and hold circuits.  
         [0018]    [0018]FIG. 1A shows the flow of the conversion, with FIG. 1B showing the hardware that is used to carry out the specific conversion. In general, the N units, where units include both A/D converters and sample and hold circuits, are divided into groups of N/2 in this embodiment. FIG. 1B shows a top group  150 , and the bottom group  152 . Each of the elements in these respective groups are controlled commonly by clock signals. The two different clock generation units  190 ,  192  are actuated  180  degrees out of phase as described herein.  
         [0019]    During the time period T 1 , an N/2 group of the signals are sampled and held by the first group of sample and hold units  160 ; shown as  105  in FIG. 1 a.    
         [0020]    During the next time period T 2 , the first N/   2   signals which were sampled and held at  105 , are subsequently coupled to a respective group of A/D converters  170 . At  110 , the top group of A/D converters  170  converts each of the signals from the group of sample and hold circuits  160 .  
         [0021]    During this same period T 2 , a group of pixel signals are respectively applied to the bottom set of sample and hold circuits  162 , at  115 .  
         [0022]    During time period T 3 , the cycle continues. New signals are sent to the top group  160  of sample and hold circuits at  118 . Substantially simultaneously, at  120 , the bottom group of A/D converters  172  convert the signals that were sampled and held by circuits  162 , at  115 .  
         [0023]    This same technique may repeat indefinitely. In general, during each of a plurality of clock cycles, one set of sample and hold signals receive their signals, while another set of A/D converters carry out a conversion. This may have the effect of speeding up the conversion speed by N/2, where N is the number of A/D converters and sample and hold circuits. However, this is done requiring only two separate clock generators. As shown, the clock generator  190  is connected in common to both the first set of sample and hold circuits  160 , and to the second set of A/D converters  172 . Analogously, the second clock generator  192  is connected to the second set of sample and hold circuits  162 , and to the first set of A/D converters  170 .  
         [0024]    This first embodiment may speed up conversion by a factor of N/2.  
         [0025]    A similar technique may be used with three separate clock generators. This technique, like the technique in FIG. 1, uses N successive approximation cells, and N of the M bit buffers or sample and hold circuits. In this system, however, the operation is divided into three offset clock cycles. During the different clock cycles, the information is successively gathered, (into the sample and hold circuits) and then converted. This is done in three separate cycles. This embodiment may speed up the operation by a value of 2N/3.  
         [0026]    In this embodiment, the total N devices are divided into three different groups, each having N/3 of the components. That is, there is a first group  250  of N/3 sample and hold circuits. A second group  252 , and a third group  254  similarly each have N/3 sample and hold circuits. Each of the sample and hold circuits is coupled to a respective A/D converter. The A/D converters are similarly divided into first, second and third groups  260 ,  262 ,  264  of the A/D converters.  
         [0027]    [0027]FIG. 2A shows the first time period S 1  representing the cycle  200 . During this cycle, at  200 , the top N/3 sample and hold circuits  250  receives their signals.  
         [0028]    Note that in this embodiment, the conversion cycles need not be equal in length. For example, the A/D converters may require more time to convert then the sample and hold circuits.  
         [0029]    In this embodiment, the three clock generation units  270 ,  271 ,  272  may be actuated 120 degrees out of phase from one another.  
         [0030]    During the next clock cycle S 2 , the middle set of sample and hold circuits  252  may receive their signals at  205 . At the same time, the top bank of A/D converters  260  begin their conversion at  210 .  
         [0031]    The next clock cycle is shown as S 3 , the bottom sample and hold circuits  254  receive their signals at  215 . The top A/D converters are still converting as part of cycle  210 . During the cycle S 3 , also, the sample and hold carried out at  205  is complete. Hence, the signals from sample and hold block  252  are received at  205  and then coupled to the A/D converter block  262 , the mid N/3 of the A/D converters. These begin their conversion at  220 .  
         [0032]    The cycle continues during clock pulse S 4 , in which the top sample and hold circuits  250  receive new signals at  221 , the mid A/D converters are still converting as part of cycle  220 , and the bottom A/D converter block  264  begins converting at  222 .  
         [0033]    In the above embodiments, the structure may be simplified, because fewer clock generators may be necessary. For example, FIGS. 1A, 1B,  2 A and  2 B, require only two or three clock generators. Signal routing is also simplified, because the groups of cells, such as the successive approximation cells, share the same control signals.  
         [0034]    In the FIG. 1A/ 1 B embodiment, all of the N/2 successive approximation cells share the same control signals. That is, the top group of cells  170  share the common control signals.  
         [0035]    A timing diagram for the FIG. 1A/ 1 B embodiment is shown in FIG. 3. During a first time interval i 1 , the data is assembled for a number of the signals, such as 11 and 12. Each cycle of assembling data comprises obtaining the signal value and obtaining the reset value.  
         [0036]    During a subsequent cycle i 2 , the two values 11 and 12 are converted. This is the time during which the A/D converter converts these values. The data is successively output during i 2 . FIG. 3 shows outputting 11 followed by outputting 12. Hence, the time interval i 1 +i 2  corresponds to a measure of latency in the system.  
         [0037]    For a master clock of 40 MHz, and an A/D converter output of 40 megasamples per second, successive approximation cells may carry out conversion at 2 megasamples per second, assuming 40 cells. In this system, two clock generator blocks are used for the FIG. 1 technique, or three clock generator blocks are used for the FIG. 2 technique. Improved results may be obtained from this system.  
         [0038]    Although only a few embodiments have been disclosed in detail above, it should be understood as the other modifications are possible. For example, using the same general technique, the conversions may be separated into any number of divisions may be possible. Each additional clock generator may add additional complexity to the system, but has the advantage of speeding up the system. However, this may also speed up the system. Therefore, more generally there may be N total ADCs, and N total buffers. There are x groups of ADCs and buffers, and x of the clock generators, where x can be any number greater than or equal to 2. The clock generators are actuated 360/x degrees out of phase with one another. The speed increase is proportional to the number x.