Abstract:
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The technical field of this invention is high speed memory testing, and more particularly a built-in self-test (BIST) system for embedded memories. 
     BACKGROUND OF THE INVENTION 
     Testing fabricated integrated circuits to determine proper operation has always been a challenging task, particularly with regard to on-board memory functions. There are two major types of device malfunctions caused by design defects. A design defect arises when the integrated circuit was manufactured to a design specification that did not provide proper function for the intended use purpose. Such a defect affects any manufactured integrated circuit until the design defect is corrected. The integrated circuit manufacturer must detect and correct such defects before shipping large number of devices to customers to avoid a costly recall. In contrast to a design defect, a manufacturing defect involves some fault in the manufacture of the integrated circuit. A manufacturing defect will generally affect less than all parts manufactured. Such defects are corrected by identification and correction of the manufacturing fault. 
     Most integrated circuit manufacturers test integrated circuits for proper operation before shipment to customers. Increasing integrated circuit complexity makes this testing increasingly difficult. Rather than rely on increasingly expensive external testing devices, many manufacturers test integrated circuits using a built-in self-test (BIST). BIST uses circuits on the integrated circuit designed solely to test the integrated circuit. When triggered either automatically in circuit operation or by an external test device, the BIST circuits produce a set of test conditions run on the ordinary circuit hardware. Comparison of the state of the integrated circuit following test to an expected state indicates whether the integrated circuit passed. An example of such a test is writing to a read/write memory and recalling the data written. A match between the data written and the data read passes the test. BIST typically involves other more complex tests. 
     A subset of BIST is programmable built-in self test (pBIST) that uses a general purpose test engine programmed by a set of instructions. This set of test instructions is typically stored on the integrated circuit in a read only memory (ROM) and includes instructions particularly developed for that integrated circuit. pBIST enables re-use of hardware and test instructions to cover a family of similar but not identical integrated circuits. 
     U.S. Pat. No. 7,324,392 entitled ROM-Based Memory Testing includes a description of an exemplary set of instructions for use in a pBIST. This patent is incorporated by reference in its entirety. 
     In conventional VLSI systems memory testing is done in three steps. In the first step hardwired logic (often available through third-party vendors, examples are memBIST (MBIST) use algorithms developed before the device is committed to tape-out. Determining the detailed make-up of hardwired logic is not feasible at this time. It is impossible to predict the appropriate hardware circuits because the necessary information comes from process model drivers during the process qualification window. Secondly, conventional memory testing attempts to close testing gaps using CPU based techniques. These techniques have a number of limitations. A major limitation is the CPU interface with largely inaccessible memory functions. The inability to do back-to-back accesses to all memories is another severe limitation. Thirdly, during memory testing while the device is in wafer form direct memory access (DMA) external memory accesses cannot be accomplished at full processor speed. This may result in a significant number of failures not being observable. 
     SUMMARY OF THE INVENTION 
     An SOC (System On Chip) usually contains a plurality of sub chips performing embedded memory system testing and data logging functions. 
     This invention describes an embedded memory test system wherein a single pBIST engine is employed that is capable of asynchronously interfacing to a plurality of sub chips with a Distributed Data Logger (DDL) incorporated in each sub chip. 
     Memory test data is collected by each DDL and failures are detected locally by each DDL. Actual and expected memory data is compared and in case of a failure a failure signature is generated and communicated to the controlling pBIST. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other aspects of this invention are illustrated in the drawings, in which: 
         FIG. 1  is a block diagram of a programmable BIST (pBist) unit built into a CPU/memory function of the prior art); 
         FIG. 2  is a detailed block diagram of a pBist controller of the prior art; 
         FIG. 3  is a diagram illustrating a prior art example two-block memory addressed by three address components: column address; row address; and block address. 
         FIG. 4  shows the pBIST architecture with Distributed Data Logging; 
         FIG. 5  shows an example of the data compression; 
         FIG. 6  shows the serial bus timing diagram; 
         FIG. 7  illustrates the block diagram of the Distributed Data Logger. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     SRAM/memory structures of different devices vary by technology, design and implementation. To test memories effectively the address access pattern sequence of the memory testing algorithm should follow a particular pattern that sensitizes and tests the electrical structure within the memory. 
     In a simple memory structure the physical addresses and logical addresses are contiguous and are matched. Effective testing can be preformed with simple algorithms that linearly increment or decrement addresses. In these memories any possible address scrambling automatically matches the input to the output. Namely bit &lt;0&gt; of the input goes to bit &lt;0&gt; of the output and so on. 
       FIG. 1  illustrates a representative prior art integrated circuit (IC), a system-on-chip (SOC) device  100  that includes programmable built-in self-test (pBIST)  130 . 
     The SOC device  100  includes multiple modules that can be highly complex to test. SOC  100  includes central processing unit (CPU)  110  and memories  111  and  112  through  119  coupled by bus  120 . Other SOC devices may include multiple processors, complex assemblages of memory and cache subsystems, peripheral devices and interfaces, various types of memory storage such as random access memory (RAM), read only memory (ROM) and possibly various types of alterable memory or flash ROM. 
     The programmable built-in self-test unit pBIST  130  includes a pBIST controller  129 , pBIST ROM  131 , an ID Value interface  132 , ID Compare unit  128  and external interface  133 . pBIST controller  129  controls SOC tests in much the same fashion as CPU  110  controls the normal operation of integrated circuit  100 . pBIST unit  130  is controlled by test instructions stored in pBIST ROM  131 . pBIST unit  130  may couple to circuits outside integrated circuit  100  via external interface  133 . Addresses enter and exit pBist unit  130  via Address I/O  134 . 
     pBIST controller  129  selects a particular pBIST controller within a group of pBIST controllers by using a pBIST ID (identification) value interface  132 . The pBIST ID value is typically a five-bit value that allows selection of up to thirty-one pBIST controllers. 
       FIG. 2  is a block diagram of functional units included in prior art pBist  130 . pBIST unit  130  includes pBIST controller  129 , registers  221  through  228 , dual address register  230 , match unit  232  and multiple input signature register (MISR) unit  233 . Addr[15:0] I/O  134  allows for input or output of pBist addresses. 
     Configuration registers  221  through  228  are memory mapped within the address space of CPU  110 . Thus CPU  110  can read from or write to any register  221  through  228  by a memory operation to the corresponding address. Configuration registers  221  through  228  control the configuration and the operational mode of pBIST unit  130 . Data registers  222  store test data recalled from pBIST ROM  131 . Program registers  223  store test program instructions recalled from pBIST ROM  131 . Other registers  224  include miscellaneous general-purpose registers. Configuration registers  221  includes four additional registers algorithm register  225 , upper RAM information (RINFOL) register  226 , lower RAM information (RINFOU) register  227  and pBIST ID register  228  which will be more fully discussed below. 
     Algorithm register  225  is actually an algorithm mask register. Bit [0] of this register indicates whether the first algorithm stored in pBIST ROM  131  would be executed. Bit [1] indicates whether the second algorithm is executed and so on. A total of 32 algorithms stored in pBist ROM  131  can be controlled the 32-bit word width of algorithm register  225 . For an algorithm to be executed, both the corresponding bit of algorithm register  225  and a valid bit in the previous algorithm header must be set. 
     RINFOL register  226  and RINFOU register  227  are group mask registers similar to algorithm register  225 . RINFOL register  226  and RINFOU register  227  indicate whether a particular RAM group is tested. This capability is provided because not all algorithms can be run on all memories. For a particular RAM group to be tested the corresponding bit in RINFOL register  226  or RINFOU register  227  and the valid bit in the previous RAM group header must both be set. RINFOL register  226  indicates the validity of RAM groups 0 to 31 and RINFOU register  227  indicates the validity of RAM groups 32 to 63. 
     pBIST ID register  228  is a memory mapped register that is loaded with a pBIST ID at the beginning of a programming sequence to specify which of a multiple of pBIST controllers  129  is being programmed by an external tester or by the local CPU  110 . Upon being reset, pBIST register assumes a value of 0x0000. Each pBIST controller  129  is assigned a unique ID value input via ID value interface  132  when the SOC integrated circuit is designed. This may be embodied by simply tying off the five-bit field to either a high or to a low reference voltage to form a five-bit ID value. Dual Address registers  230  are used in accessing memory, such as memories  111 ,  112 , through  119 . 
       FIG. 3  illustrates memory read portion of a prior art device included here as an example of how address scrambling may be used. In the example  FIG. 3 , the memory has N blocks, each block has M columns and each column has R rows. Output data from two memory blocks (block — 0  300  and block — 1  301 _ are selected by multiplexers  302 ,  303  and  304 . Each of the thirty-two vertical units of block — 0  300  and block — 1  301  contain thirty-two rows of data, each row containing four eight-bit bytes labeled bytes 0 through 3. 
     Row address &lt;R-1:0&gt; supplies the row address input of block — 0  300  and block — 1  301  and selects one row out of rows 2 R −1 to 0 in each block. Data from column 2 M −1 to column 0 are output from block — 0  300  to multiplexer  302 . Column address &lt;M-1:0&gt; supplied to the control input of multiplexer  302  selects the data for the corresponding column. Similarly, data from column 2 M −1 to column 0 are output from block — 1  301  to multiplexer  303 . Column address &lt;M-1:0&gt; supplied to the control input of multiplexer  303  selects the data for the corresponding column. The outputs of multiplexers  302  and  303  are supplied as inputs to multiplexer  304 . Block address &lt;N-1:0&gt; supplied to the control input of multiplexer  304  selects data from the corresponding block for output as data  231 . 
     In the memory of  FIG. 3 : a column address &lt;(M-1):0&gt; bits wide selects between M columns; a block address &lt;(N-1):0&gt; bits wide selects between N blocks of memory banks; and a row address &lt;(R-1):0&gt; bits wide selects between R rows of logical addresses inside each bank of memory. 
       FIG. 3  illustrates a partitioning of the example memory blocks. The example memory of  FIG. 3  requires that the SRAM addresses have two-bit column addresses &lt;0&gt; and &lt;1&gt;, two-bit row A addresses &lt;2&gt; and &lt;3&gt;, a single-bit block address &lt;4&gt; and a three-bit row B address &lt;5&gt;, &lt;6&gt; and &lt;7&gt;. The address supplied to the memory is divided into these three sections. The positions of the above regions may vary from design to design. 
     The prior pBIST  130  illustrated in  FIGS. 1 and 2  is designed for straightforward linear addressing. Row addresses are the address least significant bits (LSBs) &lt;0&gt; through &lt;4&gt;. Column addresses are bits &lt;5&gt; and &lt;6&gt;. The block address is bit &lt;7&gt;. Incrementing through these addresses would fetch data from row 0 through row 31 in sequential order in block — 0  300  and then data from row 32 through 63 in sequential order in block — 1  301 . 
     The first pass of this linear addressing would address block — 0  300  and proceed through all row addresses sequentially fetching all column 0 data first, and all column 1 data next, followed by column 2 data and finally column 3 data. The second pass of this linear addressing would address block — 1  301  and proceed through all row addresses sequentially fetching all column 0 data first, and all column 1 data next, followed by column 2 data and finally column 3 data. 
     The prior art shown in  FIGS. 1-3  employs an architecture where the pBIST and the data logger are integrated. The architecture demonstrated in  FIG. 4  consists of a single pBIST, with a Distributed Data Logger system. Each sub chip incorporates a data logger that communicates with the controlling pBIST. 
     Data is input from the tester (VLCT) to combiner  401  to format the data, then to pBIST block  402 , with pBIST memory  403 . pBIST  402  communicates with the applicable sub chips via the compressed data bus, and receives fail and log information from each sub chip. The log information is presented in a serial manner to reduce the number of connections. 
     The sub chips may contain an asynchronous bridge  405  if they operate in a different voltage and/or clock domain from the pBIST. Asynchronous bridge  405  connects to distributed data logger  406  which communicates to control block  407 . Block  407  expands the compressed data before writing the test pattern to memory  408 , and then reads the result from  408 . The comparison of the expected and actual memory data is performed in DDL  406 . Since the comparison is done locally in each sub chip, there is no need to return the read data to the pBIST thus reducing the number of connections. 
       FIG. 5  shows an example of the expander operation. Expander  501  receives 4 bit data  502  and configuration data  504 , generating 32 bit output  503 . the expansion is done as follows:
 
 w data[7:4]=˜( w data[3:0]) when (ctl[0]=1) else  w data[3:0]
 
 w data[15:8]=˜( w data[7:0]) when (ctl[1]=1) else  w data[7:0]
 
 w data[31:16]=˜( w data[=15:0]) when (ctl[2]=1) else  w data[15:0]
 
     The timing diagram of the serial data bus is shown on  FIG. 6  where  601  is the pBIST clock,  602  control scan enable,  603  is the scan data,  604  pBIST run signal and  605  is the pBIST done signal.  606  shows the scanned data. the following control signals are communicated through the serial interface: 
     
       
         
               
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 CSR, RGS 
                 MDP control signals 
               
               
                   
                 WCTL 
                 expander control signals 
               
               
                   
                 PLAT 
                 pipeline latency 
               
               
                   
                 MISR, CMISR, 
                 testing mode control 
               
               
                   
                 DW 
                 data width 
               
               
                   
                   
               
             
          
         
       
     
       FIG. 7  shows an implementation of the Distributed Data Logger  700 . Serial control signals are received from pBIST  402  by CTL_SCAN_IN register  709 . Expander and control unit  701  receives it&#39;s input from pBIST  402 . This input comprises of the following signals: 
     
       
         
               
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 addr/16 
                 16 address lines 
               
               
                   
                 wdata/4 
                 4 data lines 
               
               
                   
                 wren/4 
                 4 write enable lines 
               
               
                   
                 mems 
                 memory select 
               
               
                   
                 readi 
                 read ignore signal 
               
               
                   
                 iddq 
                 enable IDDQ test mode 
               
               
                   
                   
               
             
          
         
       
     
       701  generates outputs to memory data path  407  comprising of the following signals: 
     
       
         
               
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 addr/16 
                 16 address lines 
               
               
                   
                 wdata/32 
                 32 expanded data lines 
               
               
                   
                 wren/4 
                 4 write enable lines 
               
               
                   
                 mems 
                 memory select 
               
               
                   
                   
               
             
          
         
       
     
       701  further outputs the 4 wdata signals to register block  702 .  702  is organized as a pipeline, with the number of pipeline stages defined by the PLAT signal communicated by the pBIST. The purpose of block  702  is to synchronize the data that will be compared to the actual memory read data during test. This block is needed as the read return data from memory is pipelined and may take several cycles to return to the DDL. The output of pipeline register block  702  is connected to expander  705 , where the 4 bit wide wdata is expanded to 32 bits wide. The 32 bit output of block  705  is connected to one input of comparator  707 . 
     The 32 bit wide memory read data is returned from memory data path block  407 , and is connected to signature generator  704  for MISR and CMISR testing modes, and to return data register  706 . The output of  706  is connected to the second input of comparator  707 . 
     Comparator  707  communicates the comparison results to first input of multiplexer  708 , and the output of signature generator  704  is connected to second input of multiplexer  708 . The output of multiplexer  708  is connected to serial out shift register  711 , and to fail state machine  710 . In case of a comparison failure detected by  707 , block  710  inserts a time stamp generated by  703  into the comparison results and communicates the data to shift register  711 . Block  710  also generates FAIL and a STALL signal. The FAIL and STALL signals, together with the output of shift register  711  are communicated to pBIST  402 . Upon receipt of a STALL signal, pBIST  402  will suspend outputting new data to allow the DDL to consume data already in the pipeline registers.