Abstract:
A video signal processing apparatus receives a video signal containing at least a luminance signal and a color difference signal. A trap filter attenuates a frequency band of the color difference signal to separate the luminance signal from the video signal. A bandpass filter attenuates a frequency band of the luminance signal to separate the color difference signal from the video signal. The trap filter is constituted by a switched capacitor filter that outputs the luminance signal with a delay time equivalent to a time difference between a delay time of the processing performed in a succeeding luminance signal processing circuit and a delay time of the processing performed in a color difference signal processing circuit. With this arrangement, the circuit scale of a filter circuit can be reduced and frequency characteristics of the filter can be stabilized.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     The entire disclosure of Japanese Patent Application No. 2004-376825 filed Dec. 27, 2004 including specification, claims, drawings, and abstract is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a video signal processing apparatus including a switched capacitor filter used for processing video signals.  
         [0004]     2. Description of the Related Art  
         [0005]     Video signal processing apparatuses are widely used to convert composite signals, i.e., video signals each including a luminance signal (Y), a color difference signal (C), and a sync signal (Sync), into RGB signals.  FIG. 6  shows the arrangement of a conventional video signal processing apparatus. An antenna  10  receives radio waves. A tuner  12  selects video signals of a desired channel. A SAW filter  14  and intermediate-frequency conversion circuit  16  process the selected signals. Then, a Y/C separation circuit  18  separates the signal into two signals: i.e., a combination of luminance signal(Y)+sync signal (Sync) and a color difference signal (C). A signal processing circuit  20  executes processing including contour correction, and a CRT (cathode ray tube)  22  then displays an image.  
         [0006]      FIG. 7  shows the circuit arrangement of the Y/C separation circuit  18  and succeeding circuit components.  
         [0007]     A video signal produced from the intermediate-frequency conversion circuit  16  is entered into the trap filter  30  and the bandpass filter  32 . The trap filter  30  and bandpass filter  32  are generally constructed from CR filters each including a resistor, a capacitor and an operational amplifier. Trap filter  30  has center frequencies of 3.58 MHz and 4.43 MHz and exclusively attenuates corresponding signals whose frequency bands are equal to or near the center frequencies. Trap filter  30  separates, from the video signal, a luminance signal (Y) and a sync signal (Sync) and outputs the separated signals. The bandpass filter  32  has center frequencies of 3.58 MHz and 4.43 MHz and exclusively passes corresponding signals whose frequency bands are equal to or near the center frequencies. The bandpass filter  32  separates, from the video signal, a color difference signal (C) and outputs the separated signal. The luminance signal (Y) is sent from the trap filter  30  to the luminance signal processing circuit  34  in which the signal is subjected to predetermined processing. Then, the luminance signal (Y) is entered into the matrix circuit  38 . The color difference signal (C) is sent from the bandpass filter  32  to the chroma signal processing circuit  36  in which the signal is subjected to predetermined processing. Then, the color difference signal (C) is entered into the matrix circuit  38 .  
         [0008]     The matrix circuit  38  performs matrix transformation processing for each of the luminance signal (Y) and the color difference signal (C) to convert the signals into an RGB color space or other color space. Then, converted signals are output to a post-processing circuit  40 . The post-processing circuit  40  performs various corrections for the signals converted into the color space. The signals are sent to the CRT  22 .  
         [0009]     The matrix circuit  38 , before executing transformation processing into the color space, reconstructs (i.e., again composes) the luminance signal (Y) and the color difference signal (C) that have been temporarily separated as described above. Thus, the matrix circuit  38  must synchronously process both the luminance signal (Y) and the color difference signal (C).  
         [0010]     However, processing the luminance signal (Y) in the luminance signal processing circuit  34  takes less time compared with processing the color difference signal (C) in the chroma signal processing circuit  36 . Thus, compared with the luminance signal (Y), the color difference signal (C) has a delay of several hundred ns when it is produced. Accordingly, the matrix circuit  38  cannot execute synchronous processing for transforming the luminance signal (Y) and the color difference signal (C). This is the reason why deterioration is recognized in an image.  
         [0011]     To avoid the above drawbacks, as shown in  FIG. 8 , an all-pass filter  42  can be disposed between the trap filter  30  and the luminance signal processing circuit  34 . According to this arrangement, the all-pass filter  42  can correct a delay time between the color difference signal (C) and the luminance signal (Y). The all-pass filter  42  is generally constructed from a CR filter including a resistor, a capacitor, and an operational amplifier.  
         [0012]     The CR filters used as the trap filter  30 , bandpass filter  32 , and all-pass filter  42  have frequency characteristics varying depending on mutual conductance gm of the operational amplifiers. The frequency characteristics of a CR filter thus change when gm of an operational amplifier is changed. Furthermore, gm of the operational amplifier cannot be constant over a wide range, when the change of input voltage is taken into consideration. Thus, any change occurring in the input voltage possibly changes the frequency characteristics of a CR filter. In other words, with respect to a video signal or a luminance signal (Y), performing filtering while maintaining constant frequency characteristics is only feasible in a limited narrow range of the input voltage.  
         [0013]     In particular, according to the circuit including a serial connection of the trap filter  30  and the all-pass filter  42 , a dynamic range for processing an input signal while maintaining desired frequency characteristics is extremely narrow and the circuit scale is large.  
         [0014]     Furthermore, frequency characteristics of a CR filter vary in response to variation in a resistor or a capacitor of the CR filter. Thus, optimizing individual filtering characteristics is difficult.  
       SUMMARY OF THE INVENTION  
       [0015]     A video signal processing apparatus according to the present invention receives a video signal containing at least a luminance signal and a color difference signal. The video signal processing apparatus includes a trap filter, a bandpass filter, a luminance signal processing circuit, and a color difference signal processing circuit. The trap filter attenuates a frequency band of the color difference signal to separate the luminance signal from the video signal. The bandpass filter attenuates a frequency band of the luminance signal to separate the color difference signal from the video signal. The luminance signal processing circuit performs predetermined processing for the luminance signal produced from the trap filter. Also, the color difference signal processing circuit performs predetermined processing for the color difference signal produced from the bandpass filter. The trap filter is constituted by a switched capacitor filter that outputs the luminance signal with a delay time equivalent to a time difference between a delay time of processing performed in the luminance signal processing circuit and a delay time of processing performed in the color difference signal processing circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and, together with the description, serve to explain the principles of the invention, in which:  
         [0017]      FIG. 1  is a block diagram showing the arrangement of a video signal processing apparatus in accordance with one embodiment of the present invention;  
         [0018]      FIG. 2  is a circuit diagram showing the arrangement of a comb filter in accordance with one embodiment of the present invention;  
         [0019]      FIG. 3  is a waveform diagram showing functions of the comb filter in accordance with one embodiment of the present invention;  
         [0020]      FIG. 4  is a circuit diagram showing a tap filter contained in a Y/C separation circuit in accordance with one embodiment of the present invention;  
         [0021]      FIG. 5  is a timing chart showing functions of the tap filter provided in a Y/C separation circuit in accordance with one embodiment of the present invention;  
         [0022]      FIG. 6  is a block diagram showing a conventional video signal processing apparatus;  
         [0023]      FIG. 7  is a block diagram showing a Y/C separation circuit and succeeding circuit components in accordance with the conventional video signal processing apparatus; and  
         [0024]      FIG. 8  is a block diagram showing a Y/C separation circuit including an all-pass filter in accordance with the conventional video signal processing apparatus. 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENT  
       [0025]     A video signal processing circuit according to one embodiment of the present invention, as shown in  FIG. 1 , includes an antenna  10 , SAW filter  14 , intermediate-frequency conversion circuit  16 , Y/C separation circuit  50 , signal processing circuit  20 , and CRT  22 .  
         [0026]     According to the video signal processing circuit of the present embodiment, like the above-described conventional processing circuit, the antenna  10  receives radio waves. The tuner  12  selects video signals of a desired channel. The SAW filter  14  removes signals of unnecessary frequency bands. The intermediate-frequency conversion circuit  16  converts the signal into an intermediate-frequency band signal whose frequency band is lower than that of the received signal. The Y/C separation circuit  50  separates the intermediate-frequency band signal into two signals; i.e., a combination of luminance signal (Y)+sync signal (Sync) and a color difference signal (C). The signal processing circuit  20  executes processing including contour correction. CRT  22  displays an image.  
         [0027]     The Y/C separation circuit  50  of the embodiment has the following characteristics.  
         [0028]     A trap filter provided in the Y/C separation circuit  50  is a comb filter constructed from a switched capacitor filter (i.e., an SC filter). The comb filter, as shown in  FIG. 2 , includes a delay circuit  52  and an adder  54 . In the comb filter, delay circuit  52  receives an input signal (i.e., a frequency signal to be attenuated) and delays the signal by a half period. The adder  54  adds a delayed signal with the original signal to output a composite signal. Thus, as shown in  FIG. 3 , signals in a frequency band including or in the vicinity of a center frequency cancel each other out.  
         [0029]      FIG. 4  shows the detailed arrangement of the SC filter (i.e., the trap filter) provided in the Y/C separation circuit  50 . The SC filter includes two delay circuits  60  and  62  and a shift register  64 . The delay circuit  60  includes operational amplifiers OP 1  and OP 2 , capacitors C 1  to C 4 , and transistors Tri 1 -Tri 4  and Tro 1 -Tro 4 . Delay circuit  62  includes operational amplifiers OP 3  and OP 4 , capacitors C 5  to C 8 , and transistors Tri 5 -Tri 8  and Tro 5 -Tro 8 . Shift register  64  includes D-flip flop circuits FF 1  to FF 4  which are serially connected with each other.  
         [0030]     A clock signal and a reset signal enter from a clock terminal C and a reset terminal R of respective flip flop circuits FF 1  to FF 4 . A pointer signal enters from an input terminal D of a first-stage flip flop circuit FF 1 . An output terminal Q of the first-stage flip flop circuit FF 1  is connected to an input terminal D of a second-stage flip flop circuit FF 2 . Similarly, output terminals Q of respective flip flop circuits FF 2  and FF 3  are connected to input terminals D of succeeding flip flop circuits FF 3  and FF 4 . Furthermore, transistors Tri 1 -Tri 8  and Tro 1 -Tro 8  of the delay circuits  60  and  62  have gates connected to one of the output terminals Q of respective flip flop circuits FF 1  to FF 4 .  
         [0031]     The delay circuit  60  receives an input signal via the operational amplifier OP 1  functioning as a buffer. An input signal of the Y/C separation circuit  50  is a video signal including a luminance signal (Y) and a color difference signal (C) combined with each other. An output terminal of the operational amplifier OP 1  is grounded via a first serial circuit including a drain-source of transistor Tri 1  and a capacitor C 1 , or a second serial circuit including a drain-source of transistor Tri 2  and a capacitor C 2 , or a third serial circuit including a drain-source of transistor Tri 3  and a capacitor C 3 , or a fourth serial circuit including a drain-source of transistor Tri 4  and a capacitor C 4 . With this arrangement, when any one of the transistors Tri 1  to Tri 4  is turned on, a corresponding capacitor (i.e., any one of the capacitors C 1  to C 4 ) associated with the transistor in an ON state is charged with the voltage of the input signal.  
         [0032]     A connecting point of transistor Tri 1  and capacitor C 1  is connected to an input terminal of the operational amplifier OP 2  via a source-drain of transistor Tro 1 . A connecting point of transistor Tri 2  and capacitor C 2  is connected to the input terminal of the operational amplifier OP 2  via a source-drain of transistor Tro 2 . A connecting point of transistor Tri 3  and capacitor C 3  is connected to the input terminal of the operational amplifier OP 2  via a source-drain of transistor Tro 3 . Also, a connecting point of transistor Tri 4  and capacitor C 4  is connected to the input terminal of the operational amplifier OP 2  via a source-drain of transistor Tro 4 . The operational amplifier OP 2  functions as a buffer. With this arrangement, when any one of transistors Tr 01  to Tr 04  is turned on, the charged voltage of a corresponding capacitor (i.e., any one of the capacitors C 1  to C 4 ) associated with the transistor in an ON state is output to an adder circuit via the operational amplifier OP 2 .  
         [0033]     Output terminal Q of the first-stage flip flop circuit FF 1  is connected to a common gate of transistors Tri 1  and Tro 2 . Output terminal Q of the second-state flip flop circuit FF 2  is connected to a common gate of transistors Tri 2  and Tro 3 . Output terminal Q of the third-stage flip flop circuit FF 3  is connected to a common gate of transistors Tri 3  and Tro 4 , and output terminal Q of the fourth-stage flip flop circuit FF 4  is connected to a common gate of transistors Tri 4  and Tro 1 . In the shift register  64 , a pointer shifts in synchronism with cycles of a clock signal so that the output terminals Q of respective flip flop circuits FF 1  to FF 4  are sequentially turned into Hi-level. When transistors Tri 1  and Tro 2  are both in an ON state, capacitor C 1  is charged with the voltage of input signal while the charged voltage of the capacitor C 2  is output to the operational amplifier OP 2 . Subsequently, when transistors Tri 2  and Tro 3  become ON state, capacitor C 2  is charged with the voltage of input signal while the charged voltage of the capacitor C 3  is output to the operational amplifier OP 2 . In this manner, charging and discharging operations of respective capacitors C 1  to C 4  are sequentially repeated.  
         [0034]     The delay circuit  62  is substantially similar to the delay circuit  60  in circuit arrangement. The delay circuit  62  receives an input signal via the operational amplifier OP 3  functioning as a buffer. An output terminal of the operational amplifier OP 3  is grounded via a fifth serial circuit including a drain-source of transistor Tri 5  and a capacitor C 5 , or a sixth serial circuit including a drain-source of transistor Tri 6  and a capacitor C 6 , or a seventh serial circuit including a drain-source of transistor Tri 7  and a capacitor C 7 , or an eighth serial circuit including a drain-source of transistor Tri 8  and a capacitor C 8 . With this arrangement, when any one of the transistors Tri 5  to Tri 8  is turned on, a corresponding capacitor (i.e., any one of the capacitors C 5  to C 8 ) associated with the transistor of ON state is charged with the voltage of input signal.  
         [0035]     A connecting point of transistor Tri 5  and capacitor C 5  is connected to an input terminal of the operational amplifier OP 4  via a source-drain of transistor Tro 5 . A connecting point of transistor Tri 6  and capacitor C 6  is connected to the input terminal of the operational amplifier OP 4  via a source-drain of transistor Tro 6 . A connecting point of transistor Tri 7  and capacitor C 7  is connected to the input terminal of the operational amplifier OP 4  via a source-drain of transistor Tro 7 . Also, a connecting point of transistor Tri 8  and capacitor C 8  is connected to the input terminal of the operational amplifier OP 4  via a source-drain of transistor Tro 8 . With this arrangement, when any one of the transistors Tr 05  to Tr 08  is turned on, the charged voltage of a corresponding capacitor (i.e., any one of the capacitors C 5  to C 8 ) associated with the transistor in an ON state is output to the adder circuit via the operational amplifier OP 4 .  
         [0036]     Output terminal Q of the first-stage flip flop circuit FF 1  is connected to a common gate of transistors Tri 5  and Tro 7 . Output terminal Q of the second-stage flip flop circuit FF 2  is connected to a common gate of transistors Tri 6  and Tro 8 . Output terminal Q of the third-stage flip flop circuit FF 3  is connected to a common gate of transistors Tri 7  and Tro 5 . Output terminal Q of the fourth-stage flip flop circuit FF 4  is connected to a common gate of transistors Tri 8  and Tro 6 . In the shift register  64 , a pointer shifts in synchronism with cycles of a clock signal so that the output terminals Q of respective flip flop circuits FF 1  to FF 4  are sequentially turned into Hi-level. When transistors Tri 5  and Tro 7  are both in an ON state, capacitor C 5  is charged with the voltage of input signal while the charged voltage of the capacitor C 7  is output to the operational amplifier OP 4 . Subsequently, when transistors Tri 6  and Tro 8  become ON state, capacitor C 6  is charged with the voltage of input signal while the charged voltage of the capacitor C 8  is output to the operational amplifier OP 4 . In this manner, charging and discharging operations for respective capacitors C 5  to C 8  are sequentially repeated.  
         [0037]     An output of the operational amplifier OP 2  in the delay circuit  60  and an output of the operational amplifier OP 4  in the delay circuit  62  are composed and sent as an output signal to the signal processing circuit  20 .  
         [0038]     Operations of the video signal processing circuit according to the present embodiment will be described with reference to  FIG. 5  in the following. A clock signal includes pulses rising up periodically at times T 1 , T 2 , T 3 , - - - . A pointer signal includes pulses rising up periodically at intervals of a period “A” that is equal to a multiplication of a period of the clock signal by a total number (i.e., 4) of the flip flop circuits in the shift register  64 .  
         [0039]     In response to inputs of the clock signal and the pointer signal, flip flop circuits FF 1  to FF 4  of the shift register  64  sequentially output pulses from the output terminals Q. The output pulses are transmitted to the gates of transistors Tri 1 -Tri 8  and Tro 1 -Tro 8  to perform charging and discharging operations for respective capacitors C 1  to C 8 .  
         [0040]     As shown in  FIG. 5 , output Q of the flip flop circuit FF 1  rises up at time T 1 . In response to the rise-up, the capacitor C 1  is charged in accordance with the voltage of the input signal while the charged voltage of the capacitor C 2  is discharged to the operational amplifier OP 2 . Simultaneously, the capacitor C 5  is charged in accordance with the voltage of input signal while the charged voltage of the capacitor C 7  is discharged to the operational amplifier OP 4 . Output Q of the flip flop circuit FF 2  rises up at time T 2 . In response to the rise-up, the capacitor C 2  is recharged in accordance with the voltage of input signal while the charged voltage of the capacitor C 3  is discharged to the operational amplifier OP 2 . Simultaneously, the capacitor C 6  is charged in accordance with the voltage of input signal while the charged voltage of the capacitor C 8  is discharged to the operational amplifier OP 4 . Output Q of the flip flop circuit FF 3  rises up at time T 3 . In response to the rise-up, the capacitor C 3  is recharged in accordance with the voltage of input signal while the charged voltage of the capacitor C 4  is discharged to the operational amplifier OP 2 . Simultaneously, the capacitor C 7  is charged in accordance with the voltage of input signal while the charged voltage of the capacitor C 5  is discharged to the operational amplifier OP 4 . Also, output Q of the flip flop circuit FF 4  rises up at time T 4 . In response to the rise-up, the capacitor C 4  is recharged in accordance with the voltage of input signal while the charged voltage of the capacitor C 1  is discharged to the operational amplifier OP 2 . Simultaneously, the capacitor C 8  is charged in accordance with the voltage of input signal while the charged voltage of the capacitor C 6  is discharged to the operational amplifier OP 4 .  
         [0041]     In this manner, charging different capacitors at the same time in accordance with the voltage of an input signal while outputting the charged voltage of respective capacitors after mutually different delay times have passed makes it possible to arrange a comb filter capable of canceling the signals whose frequency bands are equal to or near the center frequencies.  
         [0042]     More specifically, the delay circuit  60  outputs the voltage value of an input signal having been entered 4 clocks before. On the other hand, the delay circuit  62  outputs the voltage value of an input signal having been entered 2 clocks before. Accordingly, when a time period corresponding to 2 clocks of the clock signal agrees with a half period of the signal having a center frequency to be attenuated, signals whose frequency bands are equal to or near the center frequencies can be attenuated. The center frequency can be changed by adjusting a period of the clock signal or a stage difference of flip flop circuits.  
         [0043]     Furthermore, an overall delay time common to the delay circuits  60  and  62  is equivalent to the time of 2 clocks. The overall delay time can be changed by increasing the number of circuit stages contained in respective delay circuits  60  and  62  by the same number. Thus, the stage number of a trap filter with respect to the luminance signal (Y) should be adjusted so as to cancel a difference in delay time between the processing of the color difference signal (C) in the chroma signal processing circuit  36  and the processing of the luminance signal (Y) in the luminance signal processing circuit  34 . With such an adjustment, the overall delay time can be equalized with a delay time difference between the processing of the color difference signal (C) in the chroma signal processing circuit  36  and the processing of the luminance signal (Y) in the luminance signal processing circuit  34 .  
         [0044]     Therefore, without providing an all-pass filter (constructed from a CR filter) in addition to a trap filter, the time difference between the luminance signal (Y) and the color difference signal (C) can be eliminated when the signals are entered into the matrix circuit  38 . Accordingly, deterioration in image quality can be reduced.  
         [0045]     Although the present embodiment discloses the delay circuits  60  and  62  respectively using four stages of capacitors C 1  to C 4  or capacitors C 5  to C 8 , an overall delay time of the tap filter and a delay difference between the delay circuit  60  and the delay circuit  62  can be appropriately changed by adjusting the stage number of shift registers and capacitors or by adjusting the clock pulse period.  
         [0046]     While the present invention has been described with reference to an exemplary embodiment, it is to be understood that the invention is not limited to the disclosed exemplary embodiment. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all modifications, equivalent structures and functions.