Abstract:
An output buffer, particularly for non-volatile memories, includes a push-pull output stage, a first data latch circuit receiving as an input data from an external data bus which connects at least one memory to the first data latch circuit, first and second activation paths for the activation of the push-pull stage, first and second circuits for enabling the push-pull stage, first and second circuits for disabling the push-pull stage, and second and third data latch circuits connected to the push-pull stage. More specifically, the first and second activation paths may be connected to the first data latch circuit. Furthermore, the first and second circuits for enabling the push-pull stage may be connected between the first data latch circuit and the push-pull stage. The first and second circuits for disabling the push-pull stage may be respectively connected between the first and second activation paths and the first data latch circuit and may receive as inputs an output enable signal and a data updating signal. Additionally, the second and third data latch circuits may be connected between the push-pull stage and, respectively, the first and second activation paths for the activation of the push-pull stage.

Description:
FIELD OF THE INVENTION 
     The present invention relates to electronic memory devices, and, more particularly, to synchronous output buffers, especially for non-volatile memories. 
     BACKGROUND OF THE INVENTION 
     It is known in the art that the buffers of a non-volatile memory generally display the data stored in the memory. The buffers also provide a high-impedance (tristate) condition of the memory when it is necessary to transfer to other memory units the control of an external buffer which interfaces with the memory. The networks that are generally used provide the buffer function by logic chains on multiple levels. The length of the implemented chains include transit times which, despite being modest in standard power supply conditions (e.g., 5 V), become significant at lower voltages (e.g., 3 V). 
     Moreover, conventional buffers immediately display the data after it is received. This causes difficulties in deferring switching of the output stages to provide appropriate protocol synchronizations (burst-type reading). The need for high speeds (even at low power supply voltages) and for easy adaptation (even to synchronous protocols) may render conventional output buffer structures inefficient. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an output buffer which has a minimal data transit time. 
     Another object of the present invention is to provide an output buffer in which data item updating is performed by an appropriate pulse that can be synchronized with external controls. 
     A further object of the present invention is to provide an output buffer in which it is possible to defer updating an external display of a new data item in the buffer. 
     Yet another object of the present invention is to provide an output buffer that allows a last read data item to be kept in the memory. 
     Still another object of the present invention is to provide an output buffer that allows limiting the switching noise of the output stage. 
     An additional object of the present invention is to provide an output buffer that is highly reliable and relatively easy to manufacture at competitive costs. 
     These and other objects which will become more apparent hereinafter are provided by an output buffer, particularly for non-volatile memories, including a push-pull output stage, a first data latch circuit receiving as an input data from an external data bus which connects at least one memory to the first data latch circuit, first and second activation paths for the activation of the push-pull stage, first and second circuits for enabling the push-pull stage, first and second circuits for disabling the push-pull stage, and second and third data latch circuits connected to the push-pull stage. 
     More specifically, the first and second activation paths may be connected to the first data latch circuit. Furthermore, the first and second circuits for enabling the push-pull stage may be connected between the first data latch circuit and the push-pull stage. The first and second circuits for disabling the push-pull stage may be respectively connected between the first and second activation paths and the first data latch circuit and may receive as inputs an output enable signal and a data updating signal. Additionally, the second and third data latch circuits may be connected between the push-pull stage and, respectively, the first and second activation paths for the activation of the push-pull stage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further characteristics and advantages of the present invention will become more apparent from the following detailed description of a preferred but not exclusive embodiment of an output buffer illustrated by way of non-limitative example in the accompanying drawings, wherein: 
     FIG. 1 is a schematic block diagram of an output buffer according to the present invention; 
     FIG. 2 is a schematic diagram showing portions of FIG. 1 in further detail; 
     FIG. 3 is a chart which plots transitions of the output buffer shown in FIGS. 1 and 2; and 
     FIG. 4 is a timing diagram of signals used in the buffer according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The output buffer according to the present invention includes a data bus DATA-BUS which receives data from at least one memory bank and preferably also from a data register. As shown in FIG. 1, a structure of the tristate type  1  is connected between the data bus and a sense amplifier of a memory bank or multiple memory banks (not shown). Data from the memory bank(s) are designated SA-DATA. A structure  2  of the tristate type provides a connection between the data bus and a data register. This may be used, for example, for testing purposes and the data received therefrom is designated REG-DATA. The tristate structure  1  is driven by a signal SA-TRI, while the tristate structure  2  is driven by a signal REG-TRI. 
     The data bus DATA-BUS is bidirectionally connected to a first data latch circuit  3  and to first and second modulated circuits  6 ,  7  for activating a pair of push-pull transistors  4 ,  5 . The transistor  4  is a P-channel MOS transistor in which the source terminal is connected to the supply voltage Vdd and the drain terminal is connected to the drain terminal of the transistor  5 . The transistor  5  is an N-channel MOS transistor in which the source terminal is connected to ground. The gate terminals of the transistors  4 ,  5  are respectively connected to the first and second modulated activation circuits  6 ,  7 . 
     The first data latch circuit  3  is also connected to a circuit or means  10  for disabling the P-channel transistor  4  and to a circuit or means  11  for disabling the N-channel  5 . The means  10  for disabling the transistor  4  receives as an input an inverted output enable signal OEn and a data loading signal LOAD, and is connected at its output to a P-channel MOS transistor  12 . A source terminal of the transistor  12  is connected to the supply voltage Vdd, and a drain terminal thereof is connected to the modulated activation path  6 . 
     Similarly, the means  11  for disabling the transistor  5  receives as an input the output enable signal OE and the inverted data load signal LOADn. The means  11  is connected at its output to the gate terminal of an N-channel MOS transistor  13 . A source terminal of the transistor  13  is connected to ground and a drain terminal thereof is connected to the second modulated activation path  7 . 
     The output buffer according to the invention further includes second and third data latch circuits  15 ,  16  dedicated respectively to the P-channel MOS transistor  4  and to the N-channel MOS transistor  5 . The second and third data latch circuits  15  and  16  are connected to the gate terminals of the transistors  4 ,  5 , respectively. 
     Moreover, the output buffer according to the invention includes a respective circuit or means  17 ,  18  for enabling the transistors  5 ,  4 . That is, the enable means  17  enables the N-channel transistor  5 , while the enable means  18  enables the P-channel transistor  4 . The enable means  17  receives as an input the signal input to the gate terminal of the MOS transistor  4 , the signal LOAD, and the signal output from the first data latch circuit  3 . Similarly, the second enable means  18  receives as an input the signal LOADn, the signal sent to the gate terminal of the N-channel MOS transistor  5 , and the signal output by the first data latch circuit  3 . The means  18  for enabling the P-channel transistor  4  may be a NOR gate, and the means  17  for enabling the N-channel MOS transistor  5  may be a NAND gate, as shown in FIG.  2 . 
     FIG. 2 provides a more detailed view of the output buffer of FIG.  1 . As shown in FIG. 2, the means  10  for disabling the P-channel transistor  4  includes a pair of logic gates, respectively a NOR gate  20  connected to an output of an AND gate  21 . Likewise, the means  11  for disabling the N-channel MOS transistor is formed by a NOR gate  22  having an output connected to an input of a NAND gate  23 . The NAND gate  23  also receives as an input the signal OE. 
     The data latch circuit  3  includes a pair of inverters  27  and  28  which are mutually parallel-connected. The modulated activation paths  6  of the transistor  4  is formed by a pair of N-channel MOS transistors  30 ,  31 . The transistors  30 ,  31  have common-connected drain and source terminals. Also, the transistor  31  is connected to the drain terminal of the MOS transistor  12 . 
     The circuit branch formed by the transistors  30  and  31  provides a “fast” branch of the modulated activation path of the N-channel MOS transistor. On the other hand, a circuit branch formed by two MOS transistors, respectively a P-channel transistor  32  and an N-channel transistor  33 , provides a “slow” branch for the activation of the P-channel MOS transistor  4 . The MOS transistors  32  and  33  have respective common-connected drain terminals, and the MOS transistor  33  is connected to ground. 
     The MOS transistor  32  is connected by its gate terminal to the output of the data latch circuit  3  and by its source terminal to a pair of inverters  35  and  36  arranged in a cascade configuration. The output of the inverter  36  is connected to the gate terminal of the P-channel MOS transistor  4 . Similarly, the second modulation path  7  of the N-channel MOS transistor  5  includes two transistors  37 ,  38  that provide the “fast” circuit branch of the modulation path. The transistors  37 ,  38  may be P-channel MOS transistors in which the drain terminals and source terminals are respectively common-connected. 
     The second circuit branch of the second modulated path  7  includes a P-channel MOS transistor  39  and an N-channel MOS transistor  40  which have common-connected drain terminals. The source terminal of the MOS transistor  39  is connected to the supply voltage Vdd, and the gate terminal of the MOS transistor  40  is connected to the output of the data latch circuit  3 . 
     In the first modulated activation path, the source terminal of the MOS transistor  32  is connected to the source terminal of the MOS transistor  31  and, similarly, the drain terminal of the MOS transistor  40  is connected to the drain terminal of the MOS transistor  38 . The drain terminal of the MOS transistor  40  is further connected to a pair of inverters  41 ,  42  arranged in a cascade configuration, like the inverters  35 ,  36 . The inverter  42  is also connected to the gate terminal of the N-channel MOS transistor  5 . 
     The output buffer according to the present invention is capable of independently retaining in memory, using the three data latch circuits  3 ,  15  and  16 , the configuration of the gate terminals of the transistors  4  and  5 . This includes the push-pull and the information of the data item related to the last read cycle. While the buffer is being updated, the three data latch circuits  3 ,  15  and  16  have the same configuration, i.e., “0” or “1” (deferred in time). Yet, this condition is such that the tristate condition (circuit  15 =1 and circuit  16 =0) is interposed between the two states (1 or 0). 
     Moreover, the buffer according to the invention is capable of modifying the output state only in the domain of the “load” phase. It may also allow different configurations between the latch circuit  3  and the pair of latch circuits  15  and  16  when buffer updating is disabled (LOAD=0). Furthermore, it may prevent symmetrical activation of the transistors  4 ,  5 . 
     When the buffer is deactivated (tristate condition), the latch circuits of the transistors  4  and  5  (i.e., the circuits  15  and  16 ) have the configurations “0” and “1” respectively for the N-channel transistor  5  and for the P-channel transistor  4 . The data latch circuit  3  may be either “0” or “1” according to the last updated data item. The disable means  10  and  11  are activated exclusively and oversee the disabling of the corresponding controlled active transistor, if any (i.e., the transistors  4 ,  5  respectively). 
     The disable means  10 ,  11  are activated in a pulsed manner, are synchronous with the “LOAD” update signal, and functionally precede each propagation within the buffer. This places the buffer in a temporary tristate configuration. The enable means  17  and  18  also are activated exclusively at the end of the achieved tristate condition, are synchronous with the update pulse LOAD, and functionally follow the deactivation of the disable means  10 ,  11 . This allows activation of the paths of the transistors  4 ,  5 . 
     The paths for the activation of the transistors  4 ,  5  (i.e., the modulated circuits  6 ,  7 ) are separated into two circuit branches. The branch formed by the pair of transistors  30 ,  31  of the path  6  and  37 ,  38  for the path  7  allows complete development of the signal. The branch formed by the transistors  32  and  33  for the path  6  and  39 ,  40  for the path  7  allows only partial development. This allows the activation of the transistors  4 ,  5  to have two dynamic behaviors. First, a fast dynamic behavior in the initial part, with simultaneous activation of the branches formed by the transistors  30 ,  31  and  32 ,  33  for the path  6  and  37 ,  38  and  39 ,  40  for the path  7 . Secondly, a slow dynamic behavior in the second part, with activation only of the branch formed by the transistors  30 ,  31  for the path  6  and  37 ,  38  for the path  7 . 
     This allows controlling (i.e., by limiting) the maximum current pulse of the stage formed by the transistors  4 ,  5 . Therefore, the noise caused by stage switching is thus reduced. The tristate condition is forced directly by both disable means  10 ,  11  by forcing the signal OE (OEn). Upon activation of the output buffer (OE=1), the tristate condition persists until the first updating pulse LOAD arrives. This is the case even if the data item to be displayed externally is already present in the latch circuit  3 . This provides a natural synchronization of the transitions with real requests made by the external system to the output buffer. 
     The updating of the data latch circuit  3  therefore does not necessarily require external visibility of the data. This allows the transitions of the MOS transistors  4 ,  5 , which are also synchronous with external timing (e.g., external updates timed by CLOCK pulses). The internal data bus DATA-BUS is kept in the configuration of the last reading performed by the data latch circuit  3 . The control signal LOAD, which oversees the updating of the data toward the outside, can be of the pulsed type or of the continuous and unlimited type. It can even be masked out if necessary to maintain unchanged the output state of the buffer according to the invention, or to update the data item without making it externally visible. 
     As shown by the circuit diagrams of FIGS. 1 and 2, the output OUT of the buffer according to the present invention is taken directly at the common node between the drain terminals of the MOS transistors  4 ,  5 . If the data item on the data bus DATA-BUS is 1 and therefore the node A of FIG. 2 is high, the node B output to the data latch circuit  3  is low. Also, the node C, taken at the gate terminal of the MOS transistor  13 , is high, and so is the node D at the gate terminal of the MOS transistor  12 . Therefore, the N-channel MOS transistor  5  is off, the node E (i.e., the output of the NOR gate  18 ) is high, and the modulation path  6  is enabled with both branches formed by the transistors  30 ,  31  and  32 ,  33  (i.e., the modulation path  7  is enabled). In this case, the P-channel MOS transistor  4  receives a low signal at its gate terminal. Thus, the transistor  4  is on and the output OUT is equal to 1. The complementary case of the above is the one in which a low signal “0” appears on the data bus DATA-BUS. 
     FIG. 4 is a timing diagram of the signals in different conditions of the buffer according to the invention. One can recognize tristate conditions, transition conditions designated by TRANS, and memorization conditions designated by MEMORY. FIG. 3 is a chart of the state transitions that occur in the output buffer according to the invention. 
     With reference to FIG. 3, assuming a tristate starting condition in which the MOS channel transistors  4 ,  5  are both disabled and that the data input to a buffer DATA is equal to  1 , the N-channel transistor  5  and P-channel transistor  4  are respectively off. This condition is designated by the reference numeral  50 . From this condition, the system reaches a tristate condition in which the P-channel transistor is enabled (step  60 ). 
     The system then advances to a step  70  in which the output OUT is equal to 1, the P-channel transistor is enabled, the data item DATA=1, and the P-channel MOS transistor  4  and the N-channel MOS transistor  5  respectively have a low signal at their gate terminals. From the step  70 , the system advances to a step  80  in which the output OUT=1, the P-channel and N-channel transistors are disabled, the data item DATA=1, and the N-channel transistor is off while the P-channel is on (low value on its gate terminal). 
     If the data item remains “1,” then the system returns from step  80  to step  70 . Otherwise, the system can pass from step  80  to tristate conditions, and therefore from the step  50 . It is also possible to reach tristate conditions by disabling the P-channel and N-channel transistors with the data item DATA=0 and where the N-channel and P-channel transistors are both off. From this last step  90 , the system can pass to the step  100 , which is complementary to the step  60 . Likewise, the step  90  is complementary with respect to the step  50 . 
     In step  100 , therefore, there is a tristate condition with enabling of the N-channel transistor  5 . The system passes from step  100  to step  110 , which is complementary to the step  70  and in which the output of the buffer OUT=0, the N-channel transistor is enabled, the data item DATA=0, and the P-channel transistor is off. The system passes from step  110  to a step  120  in which the data item is held at zero, and therefore the output OUT=0. The P-channel and N-channel transistors  4 ,  5  are disabled. 
     From step  120 , the system can enter a tristate condition entered by advancing to step  90 . The step  120  is complementary with respect to the step  80 . From step  120 , if the data item DATA remains “1,” the system passes to step  110 , which is complementary with respect to the step  70 . The state transition is completed with the transition from step  120  to the above described step  50 . 
     In practice, it has been observed that the buffer according to the invention allows storing the last read data item while keeping its visibility masked until it is necessary to transfer the data item externally. That is, there is independence between the data updating activity and the visibility of the data item outside the buffer. Moreover, the structure thus conceived substantially eliminates the noise caused by transitions as well as “crowbar” currents. 
     The updating step is in fact characterized by a direct connection between the latch circuits  3 ,  15  and  16  only for the time for which the LOAD pulse is valid. The pulse is advantageously generated so that it is very short to prevent the effects of noise from altering the freshly displayed data item. 
     The buffer according to the present invention is subject to numerous modifications and variations, all of which are within the scope of the inventive concept. Furthermore, the elements of the buffer may also be replaced with other technically equivalent elements, as will be appreciated by those of skill in the art. 
     Italian Patent Application No. MI99A002480, from which this application claims priority, is hereby incorporated herein in its entirety by reference.