Abstract:
A delay circuit with adjustable delay employs a switching flip-flop which includes a differential amplifier (A) having two outputs each one feedback-looped respectively onto two inputs, so as to produce the said switching. The looping is produced by a first (AD1) and a second (AD2) adder, each having a first, a second and a third input. The first inputs are connected to corresponding outputs of the differential amplifier to produce the feedback looping. The second inputs are intended to be connected respectively to a first and a second terminal delivering a signal to be delayed (V 1   + , V 1   - ) and the third inputs receive respectively a first and a second control voltage (V 3   + , V 3   - ). The delay is a function of the difference between the first and the second control voltage. The outputs of the adders are connected respectively to corresponding inputs of the differential amplifier.

Description:
BACKGROUND OF THE INVENTION 
     The subject of the present invention is a delay circuit with adjustable delay employing a switching flip-flop. 
     According to the prior art, such a circuit employs a D-type flip-flop associated with a clock. The delay is determined by a resistance-capacitance product RC, which makes it difficult to obtain a variable delay in an integrated circuit. 
     The patents U.S. Pat. Nos. 4,795,923 and  4,862,020 describe integratable delay circuits whose delay is continuously adjustable with the aid of a variable voltage. These circuits require several differential stages, the outputs of which are coupled, hence resulting in relatively complicated circuits. The subject of the present invention is a circuit of the type mentioned in the first paragraph and whose delay is continuously adjustable as well as being simple to employ. 
     SUMMARY OF THE INVENTION 
     The circuit according to the invention is thus characterized in that it comprises a differential amplifier (A) having a first and a second input and a first and a second output. The first and second output are feedback-looped respectively onto the first and the second input in such a way as to produce the said switching flip-flop, the looping includes a first (AD1) and a second (AD2) adder, each adder having a first, a second and a third input as well as an output. The first inputs of the first and second adder are connected to the first and second output, respectively, of the differential amplifier to produce the said feedback looping. The second inputs are connected respectively to a first and a second terminal to receive a signal to be delayed (V 1   + , V 1   - ) and the third inputs receive a respective first and a second control voltage (V 3   + , V 3   - ). The delay is a function of the difference between the first and the second control voltage (V 3   + , V 3   - ). The outputs of the first and second adders (AD1, AD2) are connected respectively to the first and second inputs of the differential amplifier (A). 
     According to a preferred embodiment, at least one of the said adders comprises a first and a second transistor whose base electrodes are connected respectively to the corresponding signal terminal and to the corresponding output of the differential amplifier. The main current path of each transistor is arranged in series with, in succession, respectively, a first resistor and a first current source for the first transistor and a second resistor and a second current source for the second transistor. The adder further comprises a serial branch comprising a third and a fourth resistor which are connected, on the one hand, to the point common to the first resistor and to the first current source and, on the other hand, to the point common to the second resistor and to the second current source. The first and second resistors may have the same value. The first and the second current source may have the same value of current. 
     The first and the second control voltage advantageously have the value V 0  +ΔV and V 0  -ΔV, respectively, ΔV being a variable whose absolute value is less than that of the constant V 0 . 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be better understood from the following description which is given by way of non-limiting example with reference to the accompanying drawings, in which: 
     FIG. 1 shows a delay circuit according to the invention; 
     FIG. 2 shows an illustration of the delay function of the circuit according to the invention, and 
     FIGS. 3a, 3b and 4 show embodiments of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     According to FIG. 1, a differential amplifier A has two inputs and two outputs delivering signals V 2   -  and V 2   +  respectively. These two outputs are feedback-looped onto corresponding inputs through two multi-input adders AD1 and AD2 respectively. This feedback looping thus produces a switching flip-flop. 
     Besides the feedback input receiving the signal V 2   +  , the adder AD1 has a signal input receiving a signal V 1   +  and a control input receiving a d.c. voltage level V 3   +  which can be varied. 
     Besides the feedback input receiving the signal V 2   - , the adder AD2 has a signal input receiving a signal V 1   -  and a control input receiving a d.c. voltage level V 3   -  which can be varied. 
     The signals V 1   -  and V 1   -  are representative of the two polarities of the input signal to be delayed. The signals V 3   +  and V 3   -  are employed to obtain the offset operation of the switching flip-flop and their value influences the value of the delay Δt. FIG. 2 illustrates the delay value Δt for squarewave signals. 
     It is possible, for example, to set: 
     
         V.sub.3.sup.+ =V.sub.0 +ΔV 
    
     
         V.sub.3.sup.- =V.sub.0 -ΔV 
    
     V 0  =constant voltage. 
     ΔV=variable voltage (positive, negative or zero) of absolute value less than that of V 0 . 
     The control signals may be direct control voltages inserted at the third inputs of voltage adders. 
     FIGS. 3a and 3b represent a preferred embodiment of the adders AD1 and AD2, for which the voltages V 3   +  and V 3   -  come in by way of current sources. The control signals are then, for example, voltages controlling the intensity of the current sources. 
     According to FIG. 3a, the adder AD1 comprises two npn transistors T 1  and T 2  whose collectors are connected to a voltage supply source V cc , whose bases receive the signals V 1   +  and V 2   +  respectively, and each of whose emitter is connected to a branch comprising, in series, for the transistor T 1 , a resistor R 1  and a variable current source I 1 , and for the transistor T 2 , a resistor R 4  in series with a variable current source I 2 . 
     Between the point A common to the resistor R 1  and to the variable current source I 1 , and the point B common to the resistor R 4  and to the variable current source I 2 , are arranged two resistors in series R 2  and R 3  whose common point C, which delivers the signal V in   +  is connected to one input of the amplifier A. 
     The current from the current sources I 1  and I 2  may be controlled by a voltage, preferably the same voltage. This enables production in integrated circuit form. 
     According to FIG. 3b, the adder AD2 comprises two npn transistors T 3  and T 4  whose collectors are connected to the voltage supply source V cc , whose base receives the signals V 2   -  and V 1   -  , respectively and each of whose emitter is connected to a branch comprising, in series, for the transistor T 3 , a resistor R 5  and a variable current source I 3 , and for the transistor T 4 , a resistor R 8  and a variable current source I 4 . 
     Between the point D common to the resistor R 5  and to the variable current source I 3 , and the point E common to the resistor R 8  and to the variable current source I 4 , are arranged two resistors in series R 6  and R 7  whose common point F, which delivers the signal V in   -  is connected to the other input of the amplifier A. The current from the current sources I 3  and I 4  may be controlled by one and the same voltage. 
     FIG. 4 shows a preferred embodiment in which the adders AD1 and AD2 both conform to the deployments of FIGS. 3a and 3b (with the same reference labels) and in which the amplifier A consists of a differential stage including two transistors T 10  and T 11  whose coupled emitters are connected to a current source I. The collectors of the transistors T 10  and T 11  are connected to the voltage supply source V cc  through resistors R 10  and R 11  respectively, and their bases are connected to the points C and F, respectively. The collector of the transistor T 10 , which delivers the output signal V 2   -  , is connected to the base of the transistor T 3 , and the collector of the transistor T 11  which delivers the output signal V 2   +  , is connected to the base of the transistor T 2 . 
     The basic idea of the invention consists in varying the quiescent point of the inputs of the differential amplifier in order to vary the delay Δt. In other words, the points C and F are brought to d.c. potentials which can be varied, and the delay depends, as will now be shown, on the difference between these potentials. 
     Let I a  (FIG. 3a) be the current flowing in the resistor R 1 . 
     Let V BE1  be the base-emitter voltage of the transistor T 1  and V BE2  that of the transistor T 2 . Neglecting the base resistances and the base currents, we have: 
     
         V.sub.1.sup.+ -V.sub.BE1 -R.sub.1 I.sub.a -(I.sub.a -I.sub.1) (R.sub.2 +R.sub.3)=V.sub.2.sup.+ -V.sub.BE2 -R.sub.4 (I.sub.1 +I.sub.2 -I.sub.1) 
    
     and 
     
         V.sub.BE1 -V.sub.BE2 =V.sub.T LOG {I.sub.a /(I.sub.1 +I.sub.2 -I.sub.a)}V.sub.T =26 mV 
    
     whence 
     
         V.sub.BE1 ≃V.sub.BE2 if I.sub.a ≃(I.sub.1 +I.sub.2)/2 
    
     this condition will be explained further on. By assumption, we choose: 
     
         R.sub.1 =R.sub.4 R.sub.2 =R.sub.3 I.sub.1 =I.sub.2 =I.sub.0 +ΔI 
    
     We then have: ##EQU1## which corresponds to a value of V 3   +   
     
         V.sub.3.sup.+ =2R.sub.1 (I.sub.0 +ΔI) 
    
     (the adder AD1 has a gain of 0.5) 
     
         V.sub.BE1 ≃V.sub.BE2 if I.sub.a ≃I.sub.1 that is (V.sub.1.sup.+ -V.sub.2.sup.+)&lt;&lt;2(R.sub.1 +R.sub.2)I.sub.1 
    
     In the same way, for the diagram of FIG. 3b and with the assumptions R 5  =R 8  and R 6  =R 7 , I 3  =I 4  =I 0  -ΔI, we obtain: ##EQU2## whence 
     
         V.sub.3.sup.- =-2R.sub.5 (I.sub.0 -ΔI). (adder of gain 0.5). 
    
     
         V.sub.BE3 V.sub.BE4 if (V.sub.1.sup.- -V.sub.2.sup.-) &lt;&lt;2 (R.sub.5 +R.sub.6) I.sub.3 
    
     V BE3  and V BE4  designating the base-emitter voltages of the transistors T 3  and T 4 . 
     The equations (1) and (2) then give (on choosing R 1  =R 5 ) ##EQU3## ΔV in  represents the offset of the operating point of the switching flip-flop. It varies linearly as a function of ΔI. 
     In accordance with the equations governing the differential stages, we have: ##EQU4## with R 10  =R 11 , th=hyperbolic tangent function. On equilibrium of the differential stage (V in   +  =V in   - ), V 1   +  is not equal to V 1   + . 
     In fact, we then have: 
     
         V.sub.1.sup.+ -V.sub.1.sup.- =4R.sub.1 ΔI+2V.sub.T LOG {(I.sub.0 +ΔI)/ I.sub.0 -ΔI)} 
    
     The difference between V 1   +  and V 1   -  at equilibrium of the differential stage depends only on ΔI, that is to say on the difference between the currents in the adders of FIG. 3a and 3b. 
     The formula giving the response time at 50%, denoted t 50 , of the amplitude is as follows: t 50  =4V T  /R 10  Iτ Log (2+R 10  I/4V T  +R 10  I/VT .ΔI/ΔV 1 ) t 50  may be taken as the characteristic value of the delay, with V 1  -peak-to-peak amplitude of the signal to be delayed, and τ=intrinsic response time of the differential stage, ##EQU5## C=capacitance of the differential stage in its equivalent diagram. (one capacitance C for each of the collectors of T 10  and T 11 ). 
     The above calculations were performed with certain assumptions (R l  =R 4  =R 5  =R 8 , R 2  =R 3  and R 6  =R 7 ), but of course this did not involve necessary conditions. In particular, the ratios between R 1  and R 4 , R 5  and R 8 , on the one hand, and between R 2  and R 3 , and R 6  and R 7  on the other hand, influence the symmetry of the waveform, that is to say enable the obtainment of a rise time equal to or different from the fall time. Different response times can in fact be obtained on each input, if AD1 and AD2 are different. 
     For R 2  &lt;R 3 , a phase advance is obtained for the corresponding input and a phase delay for R 2  &gt;R 3 . 
     For R 1  &lt;R 4 , a phase advance is obtained for the corresponding input and a phase delay for R 1  &gt;R 4 . 
     Similar reasoning applies to the ratios between R 5  and R 8  on the one hand, and R 6  and R 7  on the other hand. 
     In fact, the values of the said resistors influence the value of the difference between V in   +  and V in   -  on the one hand and on the value of τ on the other hand. 
     Under the assumption that the two devices AD1 and AD2 are structurally identical, we have in fact: ##EQU6## 
      On inverting the formula cited earlier and giving V 2   +  -V 2   -  as a function of V in   +  -V in   -  we have: 
     
         V.sub.in.sup.+ -V.sub.in.sup.- =2V.sub.T arc th {2(V.sub.2.sup.+ -V.sub.2.sup.-) / R.sub.10 I } 
    
     arc th=inverse hyperbolic tangent function. whence: ##EQU7## The hysteresis condition may be written: ##EQU8## whence the operating condition