Abstract:
A write current circuit ( 300, 400 ) adapted to drive a thin film write head ( 202 ) of a mass media information storage device. The write current circuit ( 300, 400 ) further includes programming circuitry ( 311, 411 ) driven such that parameters of the write current waveform can be varied, including the write current overshoot amplitude and/or overshoot duration. The present invention achieves technical advantages by providing the ability to program out or adjust for system introduced asymmetries in the write current waveform.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to media information storage and, more particularly, to a programmable write current overshoot amplitude and duration asymmetry correction technique.  
       BACKGROUND OF THE INVENTION  
       [0002]     Hard disk drives are mass storage devices that include a magnetic storage media, e.g. rotating disks or platters, a spindle motor, read/write heads, an actuator, a pre-amplifier, a read channel, a write channel, a servo circuit, and control circuitry to control the operation of hard disk drive and to properly interface the hard disk drive to a host system or bus.  FIG. 1  shows an example of a prior art disk drive mass storage system  10 . Disk drive system  10  interfaces with and exchanges data with a host  32  during read and write operations. Disk drive system  10  includes a number of rotating platters  12  mounted on a base  14 . The platters  12  are used to store data that is represented as magnetic transitions on the magnetic platters, with each platter  12  coupleable to a head  16  which transfers data to and from a preamplifier  26 . The preamp  26  is coupled to a synchronously sampled data (SSD) channel  28  comprising a read channel and a write channel, and a control circuit  30 . SSD channel  28  and control circuit  30  are used to process data being read from and written to platters  12 , and to control the various operations of disk drive mass storage system  10 . Host  32  exchanges digital data with control circuit  30 .  
         [0003]     Data is stored and retrieved from each side of the magnetic platters  12  by the arm and interconnect  16  which comprise a read head  18  and a write head  20  at the tip thereof. The conventional read head  18  and write head  20  comprise magneto-resistive read head and thin-film inductive write head adapted to read or write data from/to platters  12  when current is passed through them. Arm and interconnect  16  are coupled to preamplifier  26  that serves as an interface between read/write heads  18 / 20  of disk/head assembly  10  and SSD channel  28 . The preamp  26  provides amplification to the waveform data signals as needed for both read and write operations. A preamp  26  may comprise a single chip or may comprise separate components rather than residing on a single chip.  
         [0004]     The magnetic flux transitions on the magnetic platter  12  are created by switching the write current polarity through the write head  20 . The faster the write current switches polarity, the faster the change of the magnetic flux, and consequently more bits per inch can be stored in the media. To decrease the transition time of the media, an overshoot current is employed with the write driver signal.  
         [0005]     Further, write signals are designed with a symmetrical differential voltage swing during the write current reversal period. Symmetrical common-mode voltage swing is also desirable but not required. Symmetrical differential voltage swings create a symmetric current response in the inductive load if there are no imbalances in the interconnect leading to the write head. However, in a real system the read head interconnect is adjacent to the write head interconnect on the arm  16  thus creating an imbalanced interconnect due to one of the differential write traces being physically close to one of the differential reader traces. When symmetrical differential voltage swings are driven from the preamp an asymmetrical write current waveform appears at the write head  18  load due to the interconnect imbalance.  
         [0006]     Particular areas for improvements of write driver current circuits used to drive a thin film head include addressing the system induced imbalances of the write current, and providing the ability to change the write currents waveform shape so that these positive and negative amplitude and duration signal aspects can be customized. Accordingly, there is desired an improved write driver current circuit which can provide a symmetrical write current in an environment with induced imbalances, and positive and negative signal aspects selectively customized for optimizing disk drive performance.  
       SUMMARY  
       [0007]     The present invention achieves technical advantages as a system and method for correcting the inherent imbalance associated with the read/write head interconnect which causes unbalanced loading on the write data path in which this unbalanced loading induces an asymmetry in the write current waveform. A write current circuit adapted to drive a thin film write head of a mass media information storage device further including programming circuitry driven such that parameters of the write current waveform can be varied, including the write current overshoot amplitude and/or overshoot duration.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     For a more complete understanding of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawings wherein:  
         [0009]      FIG. 1  illustrates a conventional disk drive system;  
         [0010]      FIG. 2A  illustrates a conventional write driver circuit;  
         [0011]      FIG. 2B  shows a graphical representation of a write signal with symmetrical positive and negative write current overshoot as well as the equal amplitude write current pulsing signals  211 / 221  as seen at node X and node Y on  FIG. 2A ;  
         [0012]      FIG. 2C  shows a graphical representation of equally delayed positive and negative write current overshoot duration signals for a symmetrical positive and negative write current overshoot duration signal;  
         [0013]      FIG. 3A  illustrates a write drive circuit with a individual positive and negative programmable write current overshoot AMPLITUDE correction DAC in accordance with exemplary embodiments of the present invention;  
         [0014]      FIG. 3B  shows a graphical representation of the write current pulsing signals  331 / 333  for asymmetrical positive and negative write current overshoot;  
         [0015]      FIG. 3C  shows a graphical representation of a corrected and uncorrected write current signal with write current overshoot AMPLITUDE asymmetry;  
         [0016]      FIG. 4A  illustrates a write drive circuit with a individual positive and negative programmable write current overshoot DURATION correction DAC in accordance with exemplary embodiments of the present invention;  
         [0017]      FIG. 4B  shows a graphical representation of individually delayed positive and negative write current overshoot duration signals for a write current signal with asymmetrical positive and negative write current overshoot duration; and  
         [0018]      FIG. 4C  shows a graphical representation of a corrected and uncorrected write current signal with write current overshoot DURATION asymmetry.  
     
    
     DETAILED DESCRIPTION  
       [0019]     The numerous innovative teachings of the present application will be described with particular reference to the presently preferred exemplary embodiments. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses and innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features, but not to others. Throughout the drawings, it is noted that the same reference numerals or letters will be used to designate like or equivalent elements having the same function. Detailed descriptions of known functions and constructions unnecessarily obscuring the subject matter of the present invention have been omitted for clarity.  
         [0020]     Referring now to  FIG. 2A  there is illustrated a simplified H-bridge type circuit typically used for driving current through a write head  202  in a hard disk drive system. The purpose of the H-bridge is to enable current to be driven through the write head in either direction in which the H-bridge includes both a positive  204  and negative  206  side as is known in the art. The simplified circuit also includes an write current overshoot amplitude DAC  212  coupled to the conventional write driver circuitry  208 ,  210  for controlling the write current overshoot amplitude equally for each of the positive  204  and negative  206  portions of the H-bridge. Also included is a write current overshoot duration DAC  214  coupled to the conventional write driver circuitry  208 ,  210  for controlling the write current overshoot duration equally for each of the positive  204  and negative  206  portions of the H-bridge.  
         [0021]     Referring now to  FIG. 2B  there is shown the write current overshoot amplitude pulsing signals, seen at node X and Node Y on  FIG. 2A , typically used with the circuit shown in  FIG. 2A  to equally generate the positive and negative write current overshoots amplitudes. As shown and described above, separate signals  211  and  221  are used to generate the positive edge and the negative edge write current overshoot amplitude. Conventionally, the amplitudes of the signals are designed to be equal in order to create a nice symmetrical write current overshoot amplitude.  
         [0022]     Referring now to  FIG. 2C  there is shown positive edge and negative edge write current overshoot duration control signals that are internal signals to block  208  and  210  on  FIG. 2A , used to equally generate the positive and negative write current overshoot durations. As shown and described above, separate signals  243  and  245  are equally delayed versions of the reference signal  241  and used to generate the positive edge and the negative edge write current overshoot duration. Conventionally, the delay of the duration control signals are designed to be equal in order to create a nice symmetrical write current overshoot durations.  
         [0023]     An exemplary embodiment of the present invention comprises an individually positive edge and negative edge adjustable write current overshoot amplitude which enables a user to program out or adjust for system introduced asymmetries in the amplitude of the write current overshoot waveform. And, a further embodiment includes an individually positive and negative edge adjustable duration circuit enabling write current overshoot duration asymmetry adjustments which further improves overall system performance.  
         [0024]     Referring now to  FIG. 3A  there is shown a drive circuit  300  with an individual programmable positive and negative write current overshoot amplitude correction DAC  311  in accordance with exemplary embodiments of the present invention. Further, components of the circuit  300  include items  202 ,  204 ,  206 ,  208 ,  210 ,  212  and  214  which are the same as those shown in  FIG. 2A . The addition of the individually programmable positive and negative amplitude correction DAC  311  enables the resultant positive edge and negative edge write current overshoot amplitude signals to be individually compensated for. That is, block  311  enables selective programming of the write current overshoot amplitude providing separate tuning for the positive and negative peak write current overshoot amplitude value. Referring now to  FIG. 3B  there is shown the write current overshoot amplitude pulsing signals, seen at node X and Node Y on  FIG. 3A , used with the circuit shown in  FIG. 3A  to individually adjust the positive and negative write current overshoots amplitudes. As shown and described above, separate signals  331  and  333  are used to generate the positive edge and the negative edge write current overshoot amplitude. As shown on  FIG. 3B , the write current amplitude pulsing signals are no longer equal in amplitude thus purposefully introducing a non-symmetrical write current overshoot amplitude allowing the user to compensate for system induced write current overshoot asymmetries, for example.  
         [0025]      FIG. 3C  illustrates a simulated write current having a waveform  341  with a +6 mA asymmetry on the positive edge write current overshoot and a resultant waveform  343  in which the positive edge amplitude of the positive write current overshoot signal has been adjusted via the individual programmable positive and negative amplitude correction DAC  311  of the present invention until the asymmetry was removed. Range for individual amplitude programmability is determined by the system requirements but typically +/−20% of the programmed equal amplitude is enough to compensate for system induced asymmetries.  
         [0026]     Referring now to  FIG. 4A  there is shown another exemplary embodiment including the addition of an individual programmable positive and negative write current overshoot duration correction DAC  411 . Further, components of the circuit  400  include items  202 ,  204 ,  206 ,  208 ,  210 ,  212 ,  214  and  311  which are the same as those shown in  FIG. 3A . The addition of the individually programmable positive and negative duration correction DAC  411  is added to enable the resultant positive edge and negative edge write current overshoot duration signals to be individually compensated for. That is, block  411  enables selective programming of the write current overshoot duration providing separate tuning for the positive and negative peak write current overshoot duration value. This enables a user to not only selectively program the amplitude separately for each of the positive and negative amplitudes of the write current overshoot signal but also selectively program the duration separately for each of the positive and negative durations of the write current overshoot signal.  
         [0027]     Referring now to  FIG. 4B  there is shown positive edge and negative edge write current overshoot duration control signals that are internal signals to block  208  and  210  on  FIG. 4A , used to generate the positive and negative write current overshoot durations. As shown and described above, separate signals  433  and  435  are individually delayed versions of the reference signal  431  and used to generate the positive edge and the negative edge write current overshoot duration. As shown on  FIG. 4B , the write current duration control signals are no longer equal in amplitude thus purposefully introducing a non-symmetrical write current overshoot duration allowing the user to compensate for system induced write current overshoot duration asymmetries, for example.  
         [0028]      FIG. 4C  illustrates a simulated write current having a waveform  441  with a 45 pS write current overshoot duration asymmetry and a resultant waveform  443  in which the duration of the positive write current overshoot signal has been adjusted via the individual duration control circuit  411  of the present invention until the asymmetry was removed. Range for individual duration programmability is determined by the system requirements but typically +/−20% of the equally programmed duration is enough to compensate for system induced asymmetries.  
         [0029]     To summarize, a system and/or method is provided for correcting the inherent imbalance associated with the read/write head interconnects which cause unbalanced loading on the differential write data path in which this unbalanced loading induces an asymmetry in the write current overshoot signal amplitude and duration. An asymmetrical write current introduces unwanted jitter into the write data and ultimately degrades the bit error rate of the signal. The write driver overshoot current signal is programmed to counter-act system induced imbalances in the write signal.  
         [0030]     Although exemplary embodiments of the invention are described above in detail, this does not limit the scope of the invention, which can be practiced in a variety of embodiments.