Abstract:
A semiconductor device comprises at least one first semiconductor component being located in a first plane and comprising an active area which has a first contact region and at least one second semiconductor component being located in a second plane and comprising a second active area which has a second contact region. The second semiconductor component is located at a distance vertically to the first semiconductor component and is orientated relative to the first semiconductor component, so that the first active area faces away from the second semiconductor component and the second active area faces away from the first semiconductor component. An adhesive layer is arranged between the first and the second semiconductor components and a frame region adjoins laterally the first semiconductor component and the second semiconductor component on at least one side. The frame region comprises a first surface and a second surface which is located opposite to the second surface. A wiring device is introduced in the frame region and connects the first contact region to the second contact region.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to a semiconductor device having stacked semiconductor components and a method for producing a semiconductor device having stacked semiconductor components.  
         [0003]     2. Description of the Related Art  
         [0004]     Although applicable, in principle, to any desired integrated circuits, the present invention and the problems on which it is based will be explained with reference to integrated memory circuits.  
         [0005]     In memory circuit technology, preference is given to arrangements of memory components which allow extremely short rewirings between the individual components. This is expedient in order to achieve short signal propagation times between the memory components and, in this manner, to enable short latencies and a high data transfer rate. The power losses in the rewirings as well as the capacitance of the rewiring are also reduced.  
         [0006]     As the integration density of present-day semiconductor technology increases, a more and more compact design in one plane is enabled. The integration density can be increased further by stacking the memory components one above the other in a plurality of planes. One common method is to populate circuit boards on two sides. This makes it possible for at least two semiconductor components to be arranged one above the other. A plurality of such populated circuit boards may also be stacked and vertically contact-connected using cables or plug connections. However, this results in high costs for contact-connecting and installing the circuit boards. It is not possible to considerably reduce the wiring lengths and the parasitic capacitances either.  
         [0007]     Other methods provide for the memory components to be placed directly on top of one another. In one arrangement, two semiconductor housings (TSOP housings) are stacked on top of one another and the external contact connections (pins) are soldered to one another. Another variant provides for two unhoused semiconductor components (dies) to be placed on top of one another and for a respective contact of the two unhoused semiconductor components to be internally wired (bonded) internally to the same external contact of a housing. However, the structural height of such a stack is too great for many applications and, in addition, only a few (two to three) components can be stacked. The rewirings also have a capacitance and inductance which are too high, on account of their length and the large number of contact connections, for such a stack to be suitable for radiofrequency applications. Moreover, the impedance of the rewirings is not matched.  
         [0008]     Another device places a semiconductor component in a prefabricated housing. This housing has external contacts toward its underside and external contacts toward its top side, which contacts are respectively connected to one another. During the production method, the contacts are internally wired to an unhoused semiconductor component. A plurality of semiconductor components can thus be vertically integrated by stacking the housings.  
         [0009]     The disadvantage is that the prefabricated housings must be made and stocked in accordance with the functionality of the semiconductor components. Given changing dimensions of the semiconductor components on account of an increased integration density and/or extended range of functions, new housing shapes with new internal dimensions are required. In addition, their structural height is too great for many applications which is why only a few devices can be stacked. The internal rewiring also has an inductance and capacitance which are too high for the device to be suitable for radiofrequency applications.  
       SUMMARY OF THE INVENTION  
       [0010]     It is an object of the present invention to provide a semiconductor device, which makes it possible to stack semiconductor components with an improved rewiring. It is also an object of the present invention to specify a method, which can be used to produce the inventive semiconductor device.  
         [0011]     The object is achieved in accordance with the invention by means of a semiconductor device having a plurality of stacked semiconductor components. A first semiconductor component is arranged in a first plane and a second semiconductor component is arranged in a second plane. In this case, the semiconductor components are oriented in such a manner that a respective inactive side of a semiconductor component faces the other semiconductor component. An adhesive layer is introduced between the semiconductor components. A stack formed in this manner is at least partially surrounded by a frame region, in which a rewiring device that connects the first and second semiconductor components is provided.  
         [0012]     The object is also achieved in accordance with the invention by means of a method for producing a semiconductor device having the following steps: providing a temporary substrate, to which at least one stack having the above-described geometry and comprising a first semiconductor component, an adhesive layer and a second semiconductor component is gradually applied. Edge regions between stacks which have been formed in this manner are filled with a curable potting compound and the temporary substrate is then removed from the self-supporting structure. In the following steps, a rewiring device is formed in the frame region and the rewiring device is connected to the contact regions. Once the individual semiconductor devices have been fabricated, the self-supporting structure is divided into the individual semiconductor devices.  
         [0013]     The advantages of the inventive device reside, in particular, in the fact that the internal rewiring of individual semiconductor components in a semiconductor device can be produced in a cost-effective manner using thin-film and/or thick-film technology. In addition, the inventive method enables production in a highly parallel assembly.  
         [0014]     In accordance with a particularly preferred development of the present invention, the rewiring device in the frame region is formed from a first and a second rewiring. To this end, depressions are introduced into the frame region from both sides in such a manner that the two rewirings touch. Another development provides for the depression to be introduced only from one side and for the other depression to be configured in such a manner that it has the total height of the stack. A preferred development provides for these depressions to be introduced into the frame using a laser.  
         [0015]     In order to improve the mechanical properties of the semiconductor device, further developments provide for a buffer layer to be introduced in addition to the semiconductor components. The adhesive layer may additionally have a core substrate having increased rigidity.  
         [0016]     Further developments of the invention result from arranging more than one semiconductor component in one or both planes.  
         [0017]     A plurality of exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the following description. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0018]      FIGS. 1-14  are diagrammatic illustrations of successive stages of one embodiment during a production method;  
         [0019]      FIG. 15  is a diagrammatic illustration of a plan view of the embodiment;  
         [0020]      FIGS. 16-21  are diagrammatic illustrations of further embodiments; and  
         [0021]      FIG. 22  is a diagrammatic illustration of installation of a stack of one embodiment on a printed circuit board. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]     In the figures, identical reference symbols denote identical or functionally identical components. In the figures, not all of the reference symbols are shown at the same time for reasons of clarity. In this case, each figure is to be compared with the preceding figures and the reference symbols are to be adopted analogously.  
         [0023]      FIG. 1  shows a diagrammatic illustration of a first stage of one embodiment during a production method. Part of a temporary substrate  1  having a first surface  901  is shown. The temporary substrate  1  is preferably a film. A subdivision into device regions A, B is laterally provided. The edges  900   a ,  900   b  of the device regions A, B prescribe the dimensions of the semiconductor devices produced by means of the embodiment of the method. In each device region A, B, a first semiconductor component  10   a ,  10   b  is placed onto the surface  901 . The first semiconductor components  10   a ,  10   b  have a substrate region  11  having an active side  15  and an inactive side  16 . A contact-connection region  18   a ,  18   b  of the first semiconductor components  10   a ,  10   b  is situated on the active side  15 , the chip connection regions  13  being situated in said contact-connection region. The active side  15 , except for a depression  14 , is covered by a passivation layer  12  over the chip connection regions  13 . The first semiconductor components  10   a ,  10   b  are applied such that the active side  15  is oriented toward the substrate. An edge region  40  that is unoccupied for the time being is situated between the edge  900   a ,  900   b  of the device regions A, B and the first semiconductor components  10   a ,  10   b . This edge region  40  may, on the one hand, enclose each first semiconductor component  10   a ,  10   b  or may occupy at least one side of the first semiconductor component  10   a ,  10   b.    
         [0024]     In  FIG. 2 , an adhesive layer  30  is first of all applied to the inactive side of the semiconductor components  10   a ,  10   b  by means of a further production step. Second semiconductor components  20   a ,  20   b  are applied to this adhesive layer  30 . In this embodiment, the first and second semiconductor components  10   a ,  20   a  are of identical design. However, this is not to be regarded as being restrictive. Rather, it is envisaged to also integrate functionally different semiconductor components within a housing. The active areas  26 , and the contact regions  28   a ,  28   b  situated thereon, of the second semiconductor components  20   a ,  20   b  are oriented such that they face away from the first semiconductor components  10   a ,  10   b . The first and second semiconductor components  10   a ,  10   b ,  20   a ,  20   b  form two stacks, the first and second semiconductor components being arranged with their backs to one another (back-to-back). The second semiconductor components  20   a ,  20   b  are at a distance from the edge  900   a ,  900   b  of the device regions A, B. However, this distance does not necessarily correspond to the distance between the first semiconductor components  10   a ,  10   b  and the edge  900   a ,  900   b , as illustrated in  FIG. 2 .  
         [0025]     The edge region  40  is filled with a potting compound (see  FIG. 3  in this respect). In this case, inter alia, further steps (which have not been carried out) are needed to ensure that the potting compound terminates flush with the second semiconductor components  20   a ,  20   b  with a planar second surface  902 . The potting compound forms a self-supporting structure  2 . The temporary substrate  1  can therefore be removed from the first surface  901  in a subsequent step.  FIG. 4  illustrates the self-supporting structure with the planar first and second surfaces  901  and  902 .  
         [0026]      FIGS. 5-13  which are described below explain the production of a rewiring device  61   a ,  61   b ,  62   a ,  62   b  by means of contact vias in the edge region  40  and the rewiring of the first and second semiconductor components  10   a ,  10   b ,  20   a ,  20   b  using the rewiring device  61   a ,  61   b ,  62   a ,  62   b . In this case, it is particularly important that the rewiring device  61   a ,  61   b ,  62   a ,  62   b  is used to achieve a rewiring between the first and second semiconductor components  10   a ,  10   b ,  20   a ,  20   b.    
         [0027]     In a first step, a dielectric  51  is applied to the first surface  901 . The dielectric  51  is patterned using a known technique, for example a lithographic method, in such a manner that the contact-connection regions  18   a ,  18   b  of the first semiconductor components  10   a ,  10   b  are not covered by the dielectric  51  ( FIG. 5 ). The dielectric  51  is also removed in the opening regions  131  above the frame region  40 . First depression  101   a ,  101   b  are produced in the potting compound in the frame region  40  beneath the exposed opening regions  131 . A depression  101   a ,  101   b  has a bottom region  111  and side walls  121 . The bottom region  111  is preferably flat. This may be effected, for example, using powerful lasers. The depth of the depression  101   a ,  101   b  is illustrated in  FIG. 6  as half the height of the stack. However, this is only one possible embodiment and there is no restriction in terms of the depth of the first depression.  
         [0028]     In a subsequent step ( FIG. 7 ), a conductive layer is deposited onto the first surface  901  that has just been patterned. In this case, the conductive layer is deposited on the bottom region  111 , the side walls  121 , the dielectric layer  51  and the first contact regions  18   a ,  18   b . In this manner, the bottom regions  111  and the first contact-connection regions  18   a ,  18   b  are electrically connected. Lithographic patterning steps before and/or after the conductive layer is applied are used to produce a rewiring on the first surface  901 . The conductive layer preferably comprises aluminum or copper. In order to protect the rewiring, a covering layer  71 , for example a protective lacquer, is applied. However, this does not cover the depression  101   a ,  101   b  ( FIG. 8 ). A plug  81  comprising a conductive material is introduced into the depression  101   a ,  101   b  ( FIG. 9 ). The plug  81  is used to externally contact-connect the stack comprising the semiconductor components  10   a ,  20   a.    
         [0029]     A dielectric  52  that is patterned analogously to the dielectric  51  on the first surface is first of all applied to the second surface  902  ( FIG. 10 ). Second depression  102   a ,  102   b  are introduced into the frame region  40  through second opening regions  132  above the frame region  40 . The second opening regions  132  and the second depression  102   a ,  102   b  are arranged in such a manner that they are opposite the first depression  101   a ,  101   b . The depth of the second depression  102   a ,  102   b  is selected in such a manner that the bottom of the second depression  102   a ,  102   b  touches the bottom of the first depression  101   a ,  101   b . As a result of the previous application of the conductive film to the first depression  101   a ,  101   b , the underside of this conductive film is now exposed as a result of the second depression  102   a ,  102   b  (cf.  FIG. 11  in this respect).  
         [0030]     Subsequent application of a second conductive film to the patterned second surface  902  ( FIG. 12 ) achieves, on the one hand, a second rewiring  52  of the contact region  28   a ,  28   b  of the second semiconductor component  20   a ,  20   b  to the bottom region  112  of the second depressions  102   a ,  102   b . At the same time, this also achieves a rewiring between the first and second semiconductor components  10   a ,  20   a  since the two rewirings  51 ,  52  are in contact in the region of the two bottom regions  111 ,  112 .  
         [0031]     Subsequent steps comprise passivating the second rewiring  52  with a covering layer  72  and introducing second plugs  82  into the second depression  102   a ,  102   b  ( FIG. 13 ).  
         [0032]     In one of the final steps, the self-supporting structure  2  is divided into individual semiconductor devices  3 . Division is effected along the edges  900   a ,  900   b  of the device regions A, B.  FIG. 14  illustrates one individual semiconductor device  3 . The reference symbols have been shortened to the digits since it is not necessary to distinguish between first and second device regions A, B.  
         [0033]      FIG. 15  diagrammatically illustrates a plan view of the embodiment along the line  910 . The plugs  81  are arranged in the frame region  40  of the semiconductor device. The large distances between the plugs  81  as a result of their arrangement in the external frame region  40  advantageously facilitates the installation and contact-connection of the housing on a circuit board. The positioning of the plugs  81  is prescribed only by the steps which produce the depressions  101   a ,  101   b . The other steps are not affected thereby. The housing can therefore be advantageously adapted to the external rewiring solely by changing these steps. In this case, the positioning of the second plugs  82  is to be adapted, if appropriate. It should be noted that, advantageously, not all of the first and second depressions are arranged one above the other since, for example, not all of the pins of a first semiconductor component  10   a  are intended to be connected to a second semiconductor component  20   a  but rather external connections to a surface are desired.  
         [0034]     In other embodiments (not illustrated), shielding areas are deposited in a parallel manner parallel to the rewirings  51 ,  52 . Said shielding areas are applied in a preceding and/or subsequent step. In this case, a dielectric layer is additionally applied between the shielding areas and the rewirings  51 ,  52 . The impedance of the rewirings  51 ,  52  can be matched by means of these additional layers. To this end, provision is made of conductive ground layers or ground wirings which run parallel to the rewirings  61 ,  62  and are set to a fixed potential, preferably ground potential. The conductive layers preferably comprise aluminum and/or copper. An insulation layer comprising a dielectric having a pre-scribed wall thickness insulates the ground layers from the rewiring  61 ,  62 . The wall thickness is to be selected in such a manner that, with the geometrical requirements of the rewirings and of the dielectric constant, the desired impedance, typically 50 ohms, are achieved at the signal frequencies of the semiconductor components. The stacks are therefore suitable for radiofrequency applications. Since the rewiring does not need any further connecting elements in order to connect the first semiconductor components to the second semiconductor components, the inductance and capacitance are very low. This is, in turn, advantageous, inter alia, for radiofrequency applications.  
         [0035]      FIG. 16  diagrammatically illustrates another embodiment of the present invention. In this case, the depressions  103  through the first surface  901  are so deep that they pierce through the entire potting compound. The bottom  113  of the depression  103  coincides with the second surface  902 . As usual, the rewiring  61  on the first surface touches the rewiring  62  on the second surface. In this case, it is advantageously not necessary to introduce second depressions through the second surface  902 .  
         [0036]      FIG. 17  diagrammatically illustrates another embodiment of the present invention. A buffer layer  90  is introduced such that it directly laterally adjoins the first and second semiconductor components  10 ,  20 . The buffer layer  30  is soft and advantageously reduces mechanical stress within the housing, which stress is produced, inter alia, as a result of different expansions of the housing and the semiconductor components  10 ,  20  in the event of temperature changes.  
         [0037]      FIG. 18  diagrammatically illustrates another embodiment of the present invention. In this case, two third semiconductor components  30 ,  40  are arranged in one plane. A rewiring  63  between the two third semiconductor components and a rewiring  62  with the contact vias connect the first and third semiconductor components  10 ,  30 ,  40 . The interspace  41  between the third semiconductor components  30 ,  40  is advantageously filled with a potting compound. Any desired combination possibilities of one or more semiconductor components in the two planes are conceivable.  
         [0038]      FIG. 19  diagrammatically illustrates another embodiment of the present invention. Solder deposit elevations  84  are applied to the plugs  81 ,  82  in order to facilitate external contact-connection. In another embodiment, the solder deposit elevations are applied only on one surface in order to stack the housings in a simpler manner. Heating a stack of a plurality of housings in a soldering furnace then results in vertical rewirings of the housings to each other and also between the semiconductor components of one housing and further semiconductor elements in other housings.  
         [0039]     Compatibility with existing housing standards and/or customary contact-connection patterns of printed circuit boards is ensured by introducing the depression in the frame in accordance with the standards. In accordance with the embodiment described, the solder deposit elevations  84  are then situated at the desired positions.  
         [0040]      FIG. 20  diagrammatically illustrates another embodiment of the present invention. Higher mechanical strength of the housing is achieved by virtue of a core substrate  33 . To this end, rigid materials are preferred for the core substrate. The core substrate is integrated in the adhesive layer  30 . The opposite sides of the core substrate  33  are covered by two adhesive materials  32 ,  34 , with the result that the core substrate is permanently connected to the first and second semiconductor components  10   a ,  20   a . In the illustration, the core substrate  33  is a continuous layer and the depression is also to be introduced into the core substrate  33  in this embodiment.  
         [0041]      FIG. 21  diagrammatically illustrates another embodiment of the present invention. In this case, a prefabricated frame is used. The latter is constructed, in the form of a grid, from struts  91 . The cavities between the struts are large enough for the semiconductor components  10 ,  20 . The edge region is, for the most part, occupied by the frame. A gap between the struts  91  and the semiconductor components  10 ,  20  is filled with potting compound. The semiconductor components are thus fastened to the frame  10 ,  20 . Holes  106  are drilled into the struts  91  and are filled with metal in order to achieve a contact via.  
         [0042]      FIG. 22  illustrates the installation of an embodiment on a printed circuit board. A lower semiconductor device  3  uses solder deposit elevations  84  to contact-connect to contact regions  5  of a printed circuit board  4 . An upper semiconductor device  3  is stacked on the lower semiconductor device  3  and is electrically connected to a plug  82  of the lower semiconductor device  3  via solder deposit elevations  84 . A possible adhesive layer  140  between the semiconductor devices  3  ensures mechanical stability of the stack. The number of stacked semiconductor devices  3  is not restricted.  
         [0043]     Although modifications and changes may be suggested by those skilled in the art, it is the intention of the inventors to embody within the patent warranted hereon all changes and modifications as reasonably and properly come within the scope of their contribution to the art.  
         [0044]     In particular, the production method is not restricted to beginning with the patterning of the first surface. Nor do the individual steps have to follow one another in the manner illustrated.