Abstract:
A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This patent application is a continuation of U.S. application Ser. No. 13/995,133, filed Jun. 17, 2013, which is a U.S. National Phase Application under 35 U.S.C. §371 of International Application No. PCT/US2011/067764, filed Dec. 29, 2011, entitled AVD HARDMASK FOR DAMASCENE PATTERNING. 
     
    
     BACKGROUND 
       [0002]    Field 
         [0003]    Integrated circuit processing. 
         [0004]    Description of Related Art 
         [0005]    Modern integrated circuits use conductive interconnections to connect the individual devices on a chip and/or to send and/or receive signals external to the device(s). Common types of interconnections include copper and copper alloy interconnections (lines) coupled to individual devices, including other interconnections (lines) by interconnections through vias. It is not uncommon for integrated circuit to have multiple levels of interconnections (e.g., five or six levels) separated by dielectric materials. In prior integrated circuit structures, a popular dielectric material for use as an interlayer dielectric (ILD) was silicon dioxide (SiO 2 ). Currently, efforts are focused on minimizing the effective dielectric constant of an ILD so materials having a dielectric constant lower than SiO 2  (low k dielectric material) have garnered significant consideration. Many of these materials, such as carbon, silicon, oxygen based materials are porous. 
         [0006]    Developing and implementing low k ILD based integrated circuits may utilize complementary and compatible photolithography and etching processes to pattern devices that will not attack underlying layers critical to device performance. Representatively, contacts made out of tungsten are used, for example, as vertical interconnects between the source/drain junction of transistor devices and the first level interconnect, which typically consists of a dual damascene metal and a via used to connect to the contact layer in multilevel interconnect schemes. Current post patterning cleaning schemes as applied to a first dual damascene metal layer (M1/V0) deposited on a contact have a generally narrow process window due to the requirements of being able to remove both the metal hard mask (e.g., titanium or titanium nitride), photoresist, and residual etch polymer while simultaneously not etching tungsten (in the contact exposed thru the V0), copper or the low k ILD. 
         [0007]    One process to form a first dual damascene metal level (M1) on an integrated circuit structure uses a titanium nitride hard mask to create a dual damascene M1V0 about a tungsten plug. The titanium nitride hard mask is conductive and therefore must be removed to avoid line-to-line shorting. Wet clean chemistries have not been identified that can strip titanium nitride without also damaging the tungsten contact layer. To address this issue, one solution is that after the W1V0 patterning and prior to titanium nitride removal, a sacrificial light absorbing material (SLAM) is deposited and dry etched for use as a layer to protect the underlying tungsten during the titanium nitride wet clean. This method can be costly and tends to increase the M1V0 critical dimensions due to multiple process steps which can lead to VO to wrong contact shorting. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  shows a schematic cross-sectional side view of a portion of a circuit structure including a contact point, an etch stop layer over the contact point followed by an interlayer dielectric (ILD) and two hard masks. 
           [0009]      FIG. 2  shows a structure of  FIG. 1  with the introduction of a photoresist material to trench pattern the hard masks. 
           [0010]      FIG. 3  shows the structure of  FIG. 2  following the formation of trenches and the removal of the photoresist material and the optional removal of one hard mask. 
           [0011]      FIG. 4  shows the structure of  FIG. 3  following the introduction of a sacrificial material over the structure and the introduction of a photoresist material patterned to define one or more vias. 
           [0012]      FIG. 5  shows the structure of  FIG. 4  following the opening of vias to underlying contact points. 
           [0013]      FIG. 6  shows the structure of  FIG. 5  following the removal of the sacrificial light absorbing material and the photoresist material and the introduction of a conductive material in the trenches and vias. 
           [0014]      FIG. 7  shows a top view of the structure of  FIG. 6 . 
           [0015]      FIG. 8  illustrates a schematic illustration of a computing device. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]      FIG. 1  shows a cross-sectional side view of a portion of an integrated circuit structure, such as a portion of a microprocessor chip on a silicon die at a point in the process of forming interconnection to a device, including possibly to other interconnections. A typical integrated circuit structure such as a microprocessor chip may have, for example, multiple interconnection layers or levels separated from one another by interlayer dielectric (ILD) material. Referring to  FIG. 1 , structure  100  includes substrate  110  which may be the wafer substrate (e.g., a portion of a silicon wafer) having circuit devices, including transistors, thereon as well as one or more levels of interconnection to devices.  FIG. 1  shows contact point  120  that may be a circuit device formed in or on a substrate (e.g., a silicon substrate) or an interconnection line formed above the wafer to devices on the wafer. It is appreciated that the techniques described herein may be used for various interconnections within an integrated circuit including to devices that include circuit devices and other interconnections. In this sense, contact point  120  represents such devices or interconnections where an interconnection contact may be made. 
         [0017]    Overlying substrate  110  in  FIG. 1  is etch stop layer  130  of a material such as silicon nitride (Si x N y ) or silicon carbon nitride (SiCN). Overlying etch stop layer  130  is dielectric layer  140  which is, for example, an ILD. A representative material for dielectric layer  140  is a material having, for example, a dielectric constant (k) less than the dielectric constant of silicon dioxide (SiO 2 ) (e.g., a “low k” material). Representative low k material includes materials containing silicon, carbon and oxygen which may be referred to as polymers and that are known in the art. In one embodiment, dielectric layer  140  is porous. 
         [0018]    Overlying dielectric layer  140  in  FIG. 1  is first hard mask  150 . In one embodiment, first hard mask  150  is a dielectric material. Suitable dielectric materials for hard mask  150  include materials having, for example, a dielectric constant (k) greater than a dielectric constant of SiO 2  (e.g., a “high k” material). Suitable materials are also those materials that have a density greater than a material for dielectric material  140  and have a etch selectivity relative to a material for dielectric layer  140  (e.g., can be etched at a different rate than or exclusive of a material for dielectric layer  140 ). Representative materials include silicon oxynitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, lanthanum oxide, aluminum oxide and similar high dielectric constant materials. In one embodiment, hard mask  150  is deposited, for example, by a plasma deposition process, to a thickness to serve as a mask to underlying dielectric layer  140  (e.g., to protect from undesired modification of the dielectric material from energy used in subsequent mask registration). In one embodiment, a representative thickness is a thickness that will not significantly effect an overall dielectric constant of the ILD (dielectric layer plus hard mask  150 ) but at most will marginally effect such overall dielectric constant. In one embodiment, a representative thickness is on the order of 30 angstroms (Å)±20 Å. In another embodiment, a representative thickness is on the order of two to five nanometers (nm). 
         [0019]    Overlying hard mask  150  in structure  100  of  FIG. 1  is optional hard mask  160 . Hard mask  160 , in one embodiment, is a conductive material such as silicon nitride, titanium nitride or titanium. It is appreciated that, as it is optional, second hard mask  160  need not be present. If present, a representative thickness of second hard mask  160  is on the order of 20 nanometers. 
         [0020]      FIG. 2  shows the structure of  FIG. 1  following the deposition and patterning of photoresist material  170 . In this embodiment, photoresist  170  is patterned to define opening  175  over second hard mask  160  to allow patterning of hard mask  160  and hard mask  150  for exposure to dielectric layer  140  for a trench opening. 
         [0021]      FIG. 3  shows the structure of  FIG. 2  following the opening of trenches through dielectric layer  140  and the removal of photoresist material  170 .  FIG. 3  also shows structure  100  following the removal of optional hard mask  160 . In one embodiment, a hard mask of silicon nitride may be removed with a wet clean chemistry. 
         [0022]      FIG. 4  shows the structure of  FIG. 3  following the deposition of a sacrificial material (e.g., SLAM, BARC) on the structure and over hard mask  150  and into trench  200 . Sacrificial material  210  is deposited to a thickness greater than the depth of trench  200  to provide a planar surface. Following the deposition of sacrificial material  210 , photoresist material  220  is deposited and patterned to include opening  230  for via formation. Referring to  FIG. 4 , it is noted that the patterning of photoresist  220  to define opening  230  does not need to be precise. The presence of hard mask  150  will inhibit etching into dielectric layer  140  in areas protected by the hard mask. In this manner, a self-aligned process for forming vias  250  is described. 
         [0023]      FIG. 5  shows via  250  formed through dielectric layer  140  and etch stop layer  130  to contact points  120 . 
         [0024]      FIG. 6  shows the structure of  FIG. 5  following the removal of photoresist layer  220  and sacrificial material  210  and the deposition of a conductive material such as copper in trench  200  and via  250 . A suitable conductive material for trench  200  and via  250  is copper or a copper alloy deposited by an electroplating process. It is appreciated that the via and trench may be lined with a barrier layer or an adhesion layer. Suitable materials for barrier layer include but are not limited to a refractory material such titanium nitride, tungsten nitride, tantalum or tantalum nitride. Suitable materials for an adhesion layer include but are not limited to titanium, tantalum and ruthenium. Further, a suitable seed material may be deposited prior to the introduction of the copper or copper alloy conductive material. Suitable seed materials for a deposition of copper interconnection material include copper, nickel, cobalt and ruthenium.  FIG. 6  also shows that hard mask  150  remains after the formation of via  250  and trench  200  and may optionally be retained as a permanent part of structure  110 . In another embodiment, hard mask  150  is removed after via  250  is formed.  FIG. 7  shows a top view of structure  100  and illustrates trench  200  and via  250  each filled with a conductive material. Adjacent trench  200  and via  250  is a corresponding trench of conductive material. It is appreciated that additional interconnection layers may be formed on the interconnection layer shown in structure  100  to other contact points including, but not limited to, underlying devices, including interconnection lines. 
         [0025]    In the above embodiment, full trench depths were formed, followed by removal of the optional hard mask of a conductive material (hard mask  160 ), and full via depth to a contact point. In another embodiment, this process may be modified by, for example, forming the via to a partial depth prior to removing the optional hard mask of conductive material. In this manner, the remaining dielectric material beyond the partial via depth will protect the contact point (e.g., contact point  120 ) from possible damage during removal of the optional hard mask of conductive material. Another modification that may be combined with the described partial via depth modification process is a partial trench depth modification where the trench is formed to a partial depth, the via is formed to a partial depth, the optional hard mask of conductive material is removed, and the via and trench depths are completed. 
         [0026]      FIG. 8  illustrates computing device  300  in accordance with one implementation. Computing device  300  houses board  302 . Board  302  may include a number of components, including but not limited to a processor  304  and at least one communication chip  306 . Processor  304  is physically and electrically connected to board  302 . In some implementations the at least one communication chip  306  is also physically and electrically connected to board  302 . In further implementations, the communication chip  306  is part of processor  304 . 
         [0027]    Depending on its applications, computing device  300  may include other components that may or may not be physically and electrically coupled to board  302 . These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). 
         [0028]    Communication chip  306  enables wireless communications for the transfer of data to and from computing device  300 . The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip  306  may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device  300  may include a plurality of communication chips  306 . For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. 
         [0029]    Processor  304  of computing device  300  includes an integrated circuit die packaged within processor  304 . In some implementations, the integrated circuit die of the processor includes one or more devices, such as transistors or interconnectors, that are formed in accordance with implementations described above where one or more dielectric layers (ILD) are covered with a dielectric hard mask that may be retained in the final circuit die structure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. 
         [0030]    The communication chip  306  also includes an integrated circuit die packaged within the communication chip  306 . In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as transistors or interconnectors, that are formed in accordance with implementations described above incorporating a dielectric hard mask on one or more dielectric layers. 
         [0031]    In further implementations, another component housed within the computing device  300  may contain an integrated circuit die that includes one or more devices, such as transistors or interconnectors, that are formed in accordance with implementations described above incorporating a dielectric hard mask on one or more dielectric layers. 
         [0032]    In various implementations, computing device  300  may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device  300  may be any other electronic device that processes data. 
         [0033]    In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. The particular embodiments described are not provided to limit the invention but to illustrate it. The scope of the invention is not to be determined by the specific examples provided above but only by the claims below. In other instances, well-known structures, devices, and operations have been shown in block diagram form or without detail in order to avoid obscuring the understanding of the description. Where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics. 
         [0034]    It should also be appreciated that reference throughout this specification to “one embodiment”, “an embodiment”, “one or more embodiments”, or “different embodiments”, for example, means that a particular feature may be included in the practice of the invention. Similarly, it should be appreciated that in the description various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects may lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of the invention.