Abstract:
A hybrid Direct Current (DC) to DC converter is disclosed for efficiently converting an input voltage from one level to another. In a preferred embodiment, a dual phase charge pump is combined with a buck converter and a switch controller to provide a converted voltage that is useable to cellular handset circuits based on power amplifier (PA) technology.

Description:
PRIORITY CLAIM 
     This application claims the benefit of Provisional Patent Application Ser. No. 61/100,197, filed Sep. 25, 2008, the disclosure of which is hereby incorporated herein by reference in its entirety and is hereby made part of this specification. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure relates to converting power required by electronic systems from one voltage level to another. In particular, the present disclosure relates to a Direct Current (DC) to DC converter having a charge pump converter followed by a buck converter. 
     BACKGROUND 
     The amount of time a cellular handset can operate on a fully charged battery is in conflict with the increasing consumer demand for more features and smaller handsets. In an attempt to keep up with the power requirements brought about by these consumer demands, the cellular handset industry has turned to advanced higher capacity lithium ion battery technology. However, a trade-off exists in that an advanced lithium ion battery can be discharged to a lower operating voltage than typical lithium ion batteries. The lower operating voltage is incompatible with existing power amplifier (PA) technology that is used in some of the basic building blocks of cellular handset circuitry. In order to solve this lower voltage incompatibility issue, the cellular handset industry has turned to Direct Current (DC) to DC converter technology to boost the voltage of advanced lithium ion batteries to a level that is compatible with existing PA technology. Moreover, it is widely recognized that DC to DC converter technology is generally much more efficient at regulating output voltage than typical linear voltage regulator technology. Thus, DC to DC converters offer increased efficiency that can provide longer handset operation time or smaller handsets while stepping up the voltage for compatibility with existing PA technology. 
     Low current voltage boosting is commonly accomplished with a range of charge pump architectures that gradually charge a holding capacitor to twice the input voltage from a source such as a lithium-ion battery. More evolved versions of charge pump architecture can regulate output voltages. However, these evolved versions of charge pump architecture are generally less efficient. 
     When higher load currents are needed, conventional boost converters that include a power inductor can be used. Inductor based boost converters can produce output voltages that are either equal to or greater than the input voltage. Some architectures, referred to as buck-boost, can generate output voltages that can either be smaller or greater than the input battery voltage. However, the level of ripple or Alternating Current (AC) variation present on the output DC voltage is always too large and causes spectral splatter at the output of the power amplifier. To reduce the level of such ripple beyond what can be done with filtering, the more conventional inductor based boost converter is followed by either an inefficient linear voltage regulator or by a buck regulator. However, even when an inductor based boost regulator is followed by a buck regulator, the overall efficiency is poor because the combined or cascaded efficiency is equal to a multiplication of both the boost and buck efficiencies. Moreover, two power inductors are needed in such architectures, which results in increased design complexity and added expense. As a result, there remains a need for a low cost, small footprint, high efficiency DC to DC converter having an excellent low ripple output voltage. 
     SUMMARY 
     The present application discloses a novel hybrid Direct Current (DC) to DC power converter that is constructed from a charge pump circuit and a buck circuit. For the purposes of this disclosure, the novel hybrid DC to DC converter will be referred to as a Charge-Pump Buck (CPB) converter. In its most basic form, the CPB converter has an input node, a charge transfer node, an output node, and a fixed voltage node such as a power or a ground node. A load powered by the CPB converter is connectable between the output node and the ground node. A DC power source such as an electrochemical battery provides electrical energy for powering the load. The DC power source is connectable between the input node and the ground node. 
     The charge pump circuit of the CPB converter comprises one or more flying capacitors that are selectably connectable to the input node, the charge transfer node, and the ground node by a plurality of electronic switches that are controlled by a switch controller. The buck circuit of the CPB converter comprises a low-pass filter made up of an inductor connected between the charge transfer node and the output node, and a filter capacitor connected between the output node and a fixed voltage node such as power node or a ground node. An electronic switch such as an N Channel Field Effect Transistor (NFET) selectably connects the charge transfer node to the fixed voltage node under the control of the switch controller in order to provide a voltage bucking effect. 
     In operation of the CPB converter, the charge pump circuit receives an input voltage at the input node and generates a stepped up voltage at the charge transfer node during a connected phase of a charge pump cycle. The connected phase occurs when a flying capacitor is selectably connected to the charge transfer node. A pumping coincides with the connected phase. The pumping phase transfers charge from the flying capacitor to the inductor, the filter capacitor and the load via the charge transfer node. During a floating phase, the flying capacitor is selectably disconnected from the charge transfer node such that the charge pump circuit is substantially isolated from the charge transfer node. The switch controller operationally coupled to the electronic switch between the transfer node and ground closes the switch during at least a portion of the floating phase. Once the switch is closed a magnetic field built up around the inductor during the pumping phase collapses to maintain the voltage level at the output node. A charging phase for charging the flying capacitor commences just after or is coincidental with the floating phase. During the charging phase, the flying capacitor is selectably connected to the input node. Once the flying capacitor is recharged, the flying capacitor is reconnected to the charge transfer node during the connected phase, which repeats a charge pump cycle. 
     Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the invention in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a prior art single phase charge pump. 
         FIG. 2  is a schematic diagram of a prior art dual phase charge pump. 
         FIG. 3  is schematic diagram of a dual phase charge pump switchably interfaced with a buck converter. 
         FIG. 4  is a schematic diagram of a Charge-Pump Buck (CPB) converter according to the present disclosure. 
         FIG. 5  is a schematic diagram of a logic circuit useable for generating timing signals for a switch controller according to the present disclosure. 
         FIG. 6  is a timing diagram showing the relationship between the switch phases while the CPB converter is driven by a 25% duty cycle. 
         FIG. 7  is a timing diagram showing the relationship between the switch phases while the CPB converter is driven by a 75% duty cycle. 
         FIG. 8  is a timing diagram that illustrates critical timing transitions. 
         FIG. 9  is a graph of efficiency versus output voltage for three different input voltage levels. 
         FIG. 10  is a schematic diagram of the CPB converter including a bypass switch controller and bypass switches that are usable to pre-charge the flying capacitors. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and accompanying claims. 
     A Charge Pump Buck (CPB) converter according to the present disclosure is a hybrid architecture that can boost an input voltage while being very efficient. The CPB converter combines features from both a dual phase charge pump and a classical synchronous buck converter. This approach is more efficient and requires only one power inductor when compared to a conventional Direct Current (DC) to DC converter that includes an inductor-based boost converter that is followed by a buck converter. Also, the present CPB converter&#39;s design is far simpler than a conventional design since only one closed loop is required, only one power inductor (two flying capacitors are needed), and the output ripple is very close to that of a classical buck converter. The CPB will achieve an overall conversion efficiency of between 85% and 95% under the conditions of typical handset operation. 
     Before delving into the present embodiments, a discussion of charge pumps and their operation is provided for context.  FIG. 1  depicts a prior art single phase charge pump  10  that has an input node  12 , a charge transfer node  14 , and a ground node  16 . A power source such as a battery  18  is connected between the input node  12  and the ground node  16 . A load  20  is connected between the charge transfer node  14  and the ground node  16 . A holding capacitor  22  is connected in parallel with the load  20 . A flying capacitor  24  has a positive terminal  26  that is alternately switchable between the input node  12  and the charge transfer node  14  by the switches S 1  and S 2  that are controllable by a switch controller  28 . The flying capacitor  24  also has a negative terminal  30  that is alternately switchable between the input node  12  and the ground node  16  by the switches S 3  and S 4  that are controllable by the switch controller  28 . 
     During a charging phase for the flying capacitor  24 , the switch S 1  connects the positive terminal  26  of the flying capacitor  24  to the input node  12  while the switch S 4  connects the negative terminal  30  of the flying capacitor  24  to the ground node  16 . The switches S 2  and S 3  are open during the charging phase. The flying capacitor  24  is practically charged to the voltage of the battery  18 , provided that the charging phase is significantly long. 
     During a pumping phase, the switches S 1  and S 4  are opened, and the switches S 2  and S 3  are closed to connect the negative terminal  30  of the flying capacitor  24  to the input node  12  and the positive terminal  26  of the flying capacitor  24  to the charge transfer node  14 . While in the pumping phase, the fully charged flying capacitor  24  and battery  18  combine in series to initially provide the holding capacitor  22  and the load  20  with twice the voltage of the battery  18 . The switch controller  28  switches the flying capacitor  24  back to the charging phase after a relatively small charge transfer in order to limit the amount of output ripple voltage present in the output voltage. The switch controller  28  continues to generate switching phase cycles as described above as long as there is a need for the charge pump  10  to transfer charge to the load  20 . 
       FIG. 2  depicts a prior art dual phase charge pump  32  that is designed to reduce the output ripple voltage by half in comparison with the single phase charge pump  10  of  FIG. 1 . The dual phase charge pump  32  includes a second flying capacitor  34  that has a positive terminal  36  that is alternately switchable between the input node  12  and the charge transfer node  14  by switches S 5  and S 6  that are controllable by a switch controller  38 . The second flying capacitor  34  also has a negative terminal  40  that is alternately switchable between the input node  12  and the ground node  16  by the switches S 7  and S 8  that are also controllable by the switch controller  38 . This dual phase structure allows for the second flying capacitor  34  to be recharged while the flying capacitor  24  is transferring charge to the holding capacitor  22  and the load  20 , and vice versa. As a result of their shared pumping duty, the flying capacitors  24  and  34  continuously maintain a nearly constant load voltage that is practically double that of the voltage of the battery  18 . 
     The operation mode of the charge pump  32  as described above is often called the 2× mode because the output voltage of charge pump  32  is practically twice that of the input voltage. Charge pumps can be operated in modes that convert the input voltage to an output voltage that is less than twice the input voltage. However, the 2× mode yields the maximum conversion efficiency for a charge pump. Therefore, if an output voltage is needed that is less than twice the input voltage while maintaining the efficiency of a 2× mode operated charge pump, an alternate DC to DC converter architecture is needed. 
       FIG. 3  depicts one embodiment of a hybrid DC to DC converter  42  according to the present disclosure. This embodiment adds a buck circuit  44  between the holding capacitor  22  and the load  20 . The buck circuit  44  comprises an inductor  46  that is selectably connectable between the charge transfer node  14  and an output node  48  by a switch S 9 . A filter capacitor  50  is connected between the output node  48  and the ground node  16 . A switch S 10  selectably connects the charge transfer node  14  to the ground node  16  under the control of a buck controller  52 , which alternately closes and opens the switches S 9  and S 10  to provide a voltage bucking effect. The inductor  46  and the filter capacitor  50  make a low-pass filter that passes a converted DC voltage to the load  20 . The level of DC voltage at the output node  48  is proportional to the amount of time the switch S 9  is closed. The maximum level of DC voltage available at the output node  48  occurs when the switch S 9  is continuously closed. In contrast, the minimum level of DC voltage available at the output node  48  is zero when the switch S 9  is continuously open. The switches S 9  and S 10  must be opened and closed 180° out of phase with each other in order to prevent shunting the holding capacitor  22  to the ground node  16 . It is also important to note that the size of the output ripple voltage is primarily dependent upon the selection of the values of inductance and capacitance for the inductor  46  and the filter capacitor  50 , along with the selection of the switching rate for the switches S 9  and S 10 . 
     The hybrid DC to DC converter  42  of  FIG. 3  is a cascade of two independent converter systems, which are the dual phase charge pump  32  followed by the buck circuit  44 . The conversion efficiency of the dual phase charge pump  32  is less than 100%, but can exceed 95%. On the other hand, an optimized buck circuit  44  can have conversion efficiencies between 90% and 95%. However, the overall conversion efficiency of the combined converter systems is less than that of either converter system alone. For example, the resulting combined conversion efficiency for the hybrid DC to DC converter  42  of  FIG. 3  can be around 85% if the conversion efficiencies of the dual phase charge pump  32  and the buck circuit  44  are 95% and 90%, respectively. While the overall conversion efficiency of the hybrid DC to DC converter  42  of  FIG. 3  is good, the overall circuit complexity is less than ideal because it requires two independent controllers, the switch controller  38  for the switches S 1 -S 8  and the buck controller  52  for switches S 9  and S 10 . Moreover, the holding capacitor  22  would be prohibitively large in both capacitance value and physical size. Further still, if voltage regulation is required, a closed feedback loop  54  for the dual phase charge pump  32 , and a closed feedback loop  56  for the buck circuit  44  would be necessary. 
     As a result of the complexity of the hybrid DC to DC converter  42  of  FIG. 3 , a less complex and even more efficient converter is desirable.  FIG. 4  is a schematic diagram of a preferred hybrid DC to DC converter according to the present disclosure, which will be referred to hereinafter as a CPB converter  58 . In this preferred embodiment, the switch S 9  and the holding capacitor  22  are not necessary. Moreover, the inductor  46  is continuously connected between the charge transfer node  14  and the output node  48 . The need for the holding capacitor  22  and the switch S 9  is eliminated by adjusting the phase timing between the charge-pump switches S 1 -S 8  and the switch S 10  such that all the charge-pump switches S 1 -S 8  are open during the floating phase while the buck circuit switch S 10  is closed to short the charge transfer node  14  to the ground node  16 . Only a single switch controller  60  is used with the CPB converter  58  as a result of eliminating the switch S 9 . Moreover, since there is only one switch controller  60 , only one closed feedback loop  62  is needed, if voltage regulation is required. In order to control the level of the output voltage in accordance with a desired output set point, the closed feedback loop  62  varies the duty cycle of switch closures by way of pulse width modulation signals, which are shown as PWM and PWM/2 in the closed feedback loop  62 . The signal PWM/2 runs at half the frequency of the PWM signal. Further still, the elimination of the switch S 9  simplifies the construction of the CPB converter  58  while at the same time increasing the overall conversion efficiency to around 90%. 
     The switches S 1 -S 8  and S 10  are preferably Complementary Metal Oxide Semiconductor (CMOS) switches. The switches S 3 , S 4 , S 7 , S 8  and S 10  are preferably driven by gate drivers. Drivers are not needed for the switches S 1 , S 2 , S 5 , and S 6  because the higher voltage needed to drive these switches is available at the positive terminals  26  and  36  of the flying capacitors  24  and  34 . For example, the switches S 1  and S 2  are driven by the voltage available at the positive terminal  36  of flying capacitor  34 , wherein the voltage is transmitted by a jumper  64 . Similarly, the switches S 5  and S 6  are driven by the voltage available at the positive terminal  26  of flying capacitor  24 , wherein the voltage is transmitted by a jumper  66 . 
       FIG. 5  is a schematic of a logic circuit  68  that is useable to generate switch timing signals NFET, Ø 2   a , Ø 2   b , Ø 3   a , and Ø 3   b , all of which are useable to control the on and off switching of the switches S 1 -S 10 . The logic circuit  68  comprises a logic section  70 , a delay elements section  72 , and a gate drivers section  74 . The logic section  70  accepts the PWM and PWM/2 signals from the closed feedback loop  56  shown in  FIG. 4 . The PWM and PWM/2 signals are processed by the logic circuit  68  to generate the switch timing signals NFET, Ø 2   a , Ø 2   b , Ø 3   a , and Ø 3   b . The delay elements section  72  insures that the switches S 1 -S 10  are synchronized to prevent inadvertently shorting the battery  18  to the ground node  16 . Gate drivers in the gate drivers section  74  provide the higher control voltage needed to activate the switches S 3 , S 4 , S 7 , S 8 , and S 10 . 
     Also, turning now to  FIG. 6 , a timing diagram is shown representing the timing relationships between the signals depicted in  FIG. 5 . In this case, a 25% PWM duty cycle results in an output voltage at the load  20  that is about one-half the voltage of the battery  18  of  FIG. 4 . The timing diagram&#39;s crossed out areas for the Ca_N and Cb_N signals ( FIG. 4 ) represent times at which the positive terminals  26  and  36  of the flying capacitors  24  and  34  are floating during the floating phase. An arrow  76  on the timing diagram points to a time when the switch timing signal Ø 3   a  is driven high to close the switch S 4  so that the flying capacitor  24  is charged by the voltage of the battery  18  during the charging phase. An arrow  78  points to a time when the switch timing signal Ø 3   b  is driven high to close the switch S 8  so that the second flying capacitor  34  is recharged by the voltage of the battery  18 . Arrows  80  and  82  indicate that when the switch timing signals Ø 2   a  and Ø 2   b  are low to establish the connected phase, charge is delivered to the charge transfer node  14  during the corresponding pumping phase. At the time indicated by the arrow  80 , the switch timing signal Ø 2   b  signal is low, which causes the second flying capacitor  34  to be placed in series with the battery  18 , which results in the load  20  having a total applied voltage of the second charged flying capacitor  34  plus the voltage of the battery  18 . Similarly, at the time indicated by the arrow  82 , the switching timing signal Ø 2   a  is low, which causes the flying capacitor  24  to be placed in series with the battery  18 , which results in the load  20  having a total applied voltage of the charged flying capacitor  24  plus the voltage of the battery  18 . 
     Turning now to  FIG. 7 , a timing diagram is shown representing the timing relationships between the signals depicted in  FIG. 5  for a 75% PWM duty cycle. The timing diagram&#39;s crossed out areas of the Ca_N and Cb_N signals ( FIG. 4 ) represent times at which the positive terminals  26  and  36  of the flying capacitors  24  and  34 , respectively, are floating during the floating phase. An arrow  84  on the timing diagram of  FIG. 7  indicates that when the switch timing signal Ø 3   a  is high, the flying capacitor  24  is being charged by the voltage of the battery  18  ( FIG. 4 ). An arrow  86  indicates that when the switch timing signal Ø 3   b  is high, the flying capacitor  34  is being recharged by the voltage of the battery  18 . Arrows  88  and  90  indicate that when the switch timing signals Ø 2   a  and Ø 2   b  are low, charge is delivered to the charge transfer node  14 . At either of these times indicated by the arrows  88  and  90 , the flying capacitors  24  and  34  are placed in series with the battery  18 , which results in the load  20  having a total applied voltage of a charged flying capacitor plus the voltage of the battery  18 . 
       FIG. 8  is an expanded timing diagram that illustrates the critical timing transitions between the switch S 10  (NFET) and the switch timing signals Ø 2   a , Ø 2   b , Ø 3   a , and Ø 3   b . The dashed vertical transition lines indicate that the switch timing signals Ø 2   a  and Ø 2   b  should be high when the NFET drive signal for the switch S 10  goes high. Moreover, the switch timing signals Ø 2   a  and Ø 2   b  should go low before the NFET drive signal goes low. Fortunately, the timing of the switch timing signals Ø 3   a  and Ø 3   b  signals is not so critical because the switch timing signals Ø a  and Ø 2   b  are already high at this time. This ensures that the switches S 3  and S 7  are open, which in turn forces the positive terminals  26  and  36  of the flying capacitors  24  and  34  ( FIG. 4 ), respectively, to float during the floating phase. 
     Other timing signals can be generated, but careful timing of the switch timing signals Ø 3   a  and Ø 3   b  would be required. Such careful attention to timing always complicates the design of the CPB converter  58  ( FIG. 4 ) and can affect the overall conversion efficiency, especially if a timing alignment shift occurs because of manufacturing process variations or due to environmental factors such as voltage and temperature. 
     As illustrated by the timing diagrams of  FIGS. 6 and 7 , the time allowed to recharge either of the flying capacitors  24  and  34  is about the same time the NFET signal for the switch S 10  is high. This means that at a high duty cycle, when higher output voltage is delivered, more charge can be transferred into and out of the flying capacitors  24  and  34 . At a low duty cycle there is less time to transfer charge into and out of the flying capacitors  24  and  34 . As a result, less current is available to the load  20  when the CPB converter  58  is operated at a low duty cycle. Alternatively, the switch drivers can be re-organized in such a way as to allow higher load current or charge transfers at low output voltage. 
       FIG. 9  illustrates the expected efficiency of the CPB converter  58  with the load  20  ( FIG. 4 ) having a resistance of 3.8 ohms. For this particular example, the flying capacitors  24  and  34  and the filter capacitor  50  all have capacitance values of 1 microfarad. The inductor  46  has an inductance value of 1 microhenry with 60 milliohms of effective series resistance. The switches S 1 -S 10  are 55 milliohm power FETs, and the switch controller  60  ( FIG. 4 ) drives the switches S 1 -S 10  at a 2 megahertz switching rate. As shown in  FIG. 9 , the efficiency is expected to hit 90% at the 4.8 volt output with a 3.6 volt input, which compares to about 70% to 75% for typical cascaded boost and buck converters operated under the same conditions and ripple requirement. 
       FIG. 10  is a schematic of the CPB converter  58  including bypass switches  92 ,  94 ,  96 , and  98  for pre-charging the flying capacitors  24  and  34 . A bypass switch controller  100  closes the bypass switches  92 ,  94 ,  96 , and  98  when the CPB converter  58  is not supplying power to the load  20 . It is preferred that the bypass switches  92 ,  94 ,  96 , and  98  be FET switches that are sized to minimize the space they need on an integrated circuit die that holds the integrated components of the CPB converter  58 . The remaining components preferred for integration are the switches S 1 -S 10  and the switch controller  60 , which includes the logic circuit  68 . The flying capacitors  24  and  34 , the filter capacitor  50 , and the inductor  46  are preferably external to the integrated circuit die due to their physical size. 
     Those skilled in the art will recognize improvements and modifications to the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein.