Abstract:
An amplifier circuit includes an amplifier stage and a balun stage. The amplifier stage includes a common node connected to an external ground. An inductance is located between the common node and the external ground. The balun stage is connected to the amplifier stage. The balun stage includes a balun tail. The balun tail is directly connected to the common node of the amplifier stage so that a resulting connection between the balun tail and the common node bypasses the inductance between the common node and the external ground.

Description:
BACKGROUND 
     The present invention pertains to amplifiers and pertains particularly to a common device node balun grounded balanced amplifier. 
     A common drain amplifier with an ideally grounded drain can be designed that is unconditionally stable. However, in a practical implementation, the length of a bond wire, package lead and so on can result in nonzero drain inductance. The drain inductance introduces instability at various frequencies. The resistance values of the amplifier can be adjusted to re-acquire unconditional stability. However, this adjustment of resistance values can result in a loss of gain and decreased noise performance. 
     An output balun may take the form of a transformer or, more usually in integrated circuits, a lumped element inductance-capacitance (L-C) ladder structure. In the case of a transformer, the secondary winding has a center tap that is usually grounded. For the ladder type balun, there is a tail node, which is used to ground all of the shunt elements. Herein, the term “balun tail” is used to refer both to the center tap of the transformer and to the tail node of the ladder type balun. 
     When a balun has an ideal tail ground, amplitude and phase performance is maximized. However, in a practical implementation, the length of a bond wire, package lead and so on can result in nonzero tail inductance. The tail inductance deteriorates the amplitude and phase. The element values of the balun can be adjusted to compensate for tail inductance; however, this results in reduction of useful bandwidth of the balun and costly design iteration. 
     When an amplifier with drain inductance is integrated with a balun with tail inductance, the effects of the inductances are compounded. The drain inductance can cause the amplifier to be unstable at certain frequencies. In addition there is amplitude and phase deterioration caused by the tail inductance of the balun. 
     Correction of the stability problem can be accomplished by reducing the gain of the amplifier with additional resistance, resulting in a concomitant increase in noise. Further steps can be taken to improve the drain grounding by use of multiple bond wires and package pins. Additionally, multiple high-grade capacitors are required to bypass the drain node to ground. Phase and amplitude irregularities can be addressed by absorbing the tail inductance into the other component values of the balun, resulting in reduced bandwidth and costly design iteration. 
     SUMMARY OF THE INVENTION 
     In accordance with the preferred embodiment of the present invention, an amplifier circuit includes an amplifier stage and a balun stage. The amplifier stage includes a common node connected to an external ground. An inductance is located between the common node and the external ground. The balun stage is connected to the amplifier stage. The balun stage includes a balun tail. The balun tail is directly connected to the common node of the amplifier stage so that a resulting connection between the balun tail and the common node bypasses the inductance between the common node and the external ground. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a schematic representation of a common drain balanced output amplifier in accordance with a preferred embodiment of the present invention. 
     FIG. 2 shows a schematic representation of a common drain balanced output amplifier circuit with an alternate output termination in accordance with an alternative preferred embodiment of the present invention. 
     FIG. 3 shows a schematic representation of a common source balanced output amplifier circuit with output termination in accordance with an alternative preferred embodiment of the present invention. 
     FIG. 4 shows a schematic representation of a common gate balanced output amplifier circuit with output termination in accordance with an alternative preferred embodiment of the present invention. 
     FIG. 5 shows a schematic representation of a common drain balanced output amplifier circuit in accordance with an alternative preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In preferred embodiments of the present invention, within a balanced amplifier circuit, a balun tail is connected directly to a common node of the amplifier circuit. The result is a dramatic reduction of the sensitivity of the amplifier circuit to the presence of grounding inductance. This allows construction of an amplifier stage having unconditional stability, higher gain, lower noise and reduced ground circuit complexity. Connecting the balun tail directly to the common node of the amplifier also provides for maximum balun performance without iteration. 
     The particular embodiments of the present invention described herein are meant to be illustrative. For example, in each of the embodiments disclosed in the figures, a field-effect transistor (FET) is used within the amplifier circuit; however, as will be understood by persons of ordinary skill in the art, a bipolar transistor, a tube amplifier or some other form of amplifier can be used instead of an FET. Likewise, the illustrated embodiments shown in the figures show the balun being implemented by a lumped element LC circuit; however, as will be understood by persons of ordinary skill in the art, a transformer or other type of balun may be used. In each case, however, connecting the balun tail directly to the common node of the amplifier results in increased circuit performance and stability. 
     FIG. 1 shows a schematic representation of a common drain balanced output amplifier circuit. The schematic is for an alternating current (AC) simulation so that DC biasing circuitry is omitted. 
     An amplifier stage of the amplifier circuit includes an FET  11 , a resistance  17  and a resistance  18 . Resistance  17  and resistance  18  represent stabilizing and impedance matching elements for FET  11 . As will be understood by persons of ordinary skill in the art, many other combinations may be used to accomplish the same purpose. For example, in some embodiments, resistance  17  and resistance  18  can be eliminated entirely. In other embodiments resistance  17  and resistance  18  can be replaced by a suitable combination of reactive elements. 
     An output stage (balun) of the amplifier circuit includes an inductance  14 , an inductance  15 , an inductance  16 , a capacitance  19 , a capacitance  20 , and a capacitance  21 , connected as shown. Also shown are an input port terminator  23  connected to a ground  10 , an input inductance  12 , a common node inductance  13 , and an output port terminator  24 . For example common node inductance  13  results, at least partially, from a bond wire and/or a package lead. A line  22  connects the tail of the balun to the common node of the amplifier. In this case, the common node of the amplifier is the drain of FET  11 . 
     As will be understood by persons of ordinary skill in the art, implementation of a balun does not require all the elements shown in FIG.  1 . For example, inductance  16  and capacitance  21  are optional elements that serve to enhance performance in particular circumstances. Of course, elimination of these elements would generally require adjustment of the values of other elements. 
     For example, the amplifier circuit has a start frequency of 0.8 Gigahertz (GHz), a stop frequency of 1.2 GHz and a step frequency of 0.01 GHz. Input port terminator  23  has an impedance of 350 Ohms. Inductance  12  has a value of 20 nanohenries (nH). Resistance  17  has a resistance of 90 Ohms. Resistance  18  has a resistance of 50 Ohms. FET  11  has a width of 1000 micrometers, a gate-to-source voltage (V GS ) equal to 0.5 volts and a drain-to-source voltage (V DS ) equal to 3 volts. Common node inductance  13  has a value of 2 nH. Inductance  14  has a value of 6.2 nH. Inductance  16  has a value of 0.83 nH. Inductance  15  has a value of 6.3 nH. Capacitance  20  has a value of 4.2 picofarads (pF). Capacitance  19  has a value of 4.2 pF. Capacitance  21  has a value of 19.5 pF. Output port terminator  24  has an impedance of 50 Ohms. 
     FIG. 2 shows a schematic representation of the common drain balanced output amplifier circuit shown in FIG. 1, modified to replace output port terminator  24  with an output port terminator  25  connected to ground  10  and an output port terminator  26  connected to ground. For example, output port terminator  25  has an impedance of 25 Ohms. Output port terminator  26  has an impedance of 25 Ohms. No other changes have been made to the amplifier circuit and all the element values remain the same. 
     FIG. 3 shows a schematic representation of a common source balanced output amplifier circuit. The schematic is for an alternating current (AC) simulation so that DC biasing circuitry is omitted. 
     An amplifier stage of the amplifier circuit includes an FET  31 , a resistance  37  and a resistance  38 . As will be understood by persons of ordinary skill in the art, many other combinations may be used to accomplish the same purpose. For example, in some embodiments, resistance  37  and resistance  38  can be eliminated entirely. In other embodiments resistance  37  and resistance  38  can be replaced by a suitable combination of reactive elements. 
     An output stage (balun) of the amplifier circuit includes an inductance  34 , an inductance  35 , an inductance  36 , a capacitance  39 , a capacitance  40 , and a capacitance  41 , connected as shown. Also shown are an input port terminator  43  connected to a ground  30 , an input inductance  32 , a common node inductance  33 , an output port terminator  45  and an output port terminator  46 . A line  42  connects the tail of the balun to the common node of the amplifier. In this case, the common node of the amplifier is the source of FET  31 . 
     For example, the amplifier circuit has a start frequency of 0.8 Gigahertz (GHz), a stop frequency of 1.2 GHz and a step frequency of 0.01 GHz. Input port terminator  43  has an impedance of 350 Ohms. Inductance  32  has a value of 20 nH. Resistance  37  has a resistance of 90 Ohms. Resistance  38  has a resistance of 50 Ohms. FET  31  has a width of 1000 micrometers, a gate-to-source voltage (V GS ) equal to 0.5 volts and a drain-to-source voltage (V DS ) equal to 3 volts. Common node inductance  33  has a value of 2 nH. Inductance  34  has a value of 6.2 nH. Inductance  36  has a value of 0.83 nH. Inductance  35  has a value of 6.3 nH. Capacitance  40  has a value of 4.2 pF. Capacitance  39  has a value of 4.2 pF. Capacitance  41  has a value of 19.5 pF. Output port terminator  45  has an impedance of 25 Ohms. Output port terminator  46  has an impedance of 25 Ohms. 
     FIG. 4 shows a schematic representation of a common gate balanced output amplifier circuit. The schematic is for an alternating current (AC) simulation so that DC biasing circuitry is omitted. 
     An amplifier stage of the amplifier circuit includes an FET  51 , a resistance  57  and a resistance  58 . As will be understood by persons of ordinary skill in the art, many other combinations may be used to accomplish the same purpose. For example, in some embodiments, resistance  57  and resistance  58  can be eliminated entirely. In other embodiments resistance  57  and resistance  58  can be replaced by a suitable combination of reactive elements. 
     An output stage (balun) of the amplifier circuit includes an inductance  54 , an inductance  55 , an inductance  56 , a capacitance  59 , a capacitance  60 , and a capacitance  61 , connected as shown. Also shown are an input port terminator  63  connected to a ground  50 , an input inductance  52 , a common node inductance  53 , an output port terminator  65  and an output port terminator  66 . A line  62  connects the tail of the balun to the common node of the amplifier. In this case, the common node of the amplifier is the gate of FET  51 . 
     For example, the amplifier circuit has a start frequency of 0.8 Gigahertz (GHz), a stop frequency of 1.2 GHz and a step frequency of 0.01 GHz. Input port terminator  63  has an impedance of 350 Ohms. Inductance  52  has a value of 20 nH. Resistance  57  has a resistance of 90 Ohms. Resistance  58  has a resistance of 50 Ohms. FET  51  has a width of 1000 micrometers, a gate-to-source voltage (V GS ) equal to 0.5 volts and a drain-to-source voltage (V DS ) equal to 3 volts. Common node inductance  53  has a value of 2 nH. Inductance  54  has a value of 6.2 nH. Inductance  56  has a value of 0.83 nH. Inductance  55  has a value of 6.3 nH. Capacitance  60  has a value of 4.2 pF. Capacitance  59  has a value of 4.2 pF. Capacitance  61  has a value of 19.5 pF. Output port terminator  65  has an impedance of 25 Ohms. Output port terminator  66  has an impedance of 25 Ohms. 
     FIG. 5 shows a schematic representation of a common drain output amplifier circuit with a transformer balun. The schematic is for an alternating current (AC) simulation so that DC biasing circuitry is omitted. 
     An amplifier stage of the amplifier circuit includes an FET  71 , a resistance  77  and a resistance  78 . As will be understood by persons of ordinary skill in the art, many other combinations may be used to accomplish the same purpose. For example, in some embodiments, resistance  77  and resistance  78  can be eliminated entirely. In other embodiments resistance  77  and resistance  78  can be replaced by a suitable combination of reactive elements. 
     An output stage (balun) of the amplifier circuit includes a transformer having a primary coil  76  and secondary coil sections  80  and  81 . Also shown are an input port terminator  83  connected to a ground  70 , an input inductance  72 , a common node inductance  73 , an inductance  75 , an output port terminator  85  and an output port terminator  86 . A line  82  connects the tail of the balun to the common node of the amplifier. In this case, the common node of the amplifier is the drain of FET  71 . The tail of the balun is located at a center tap of the secondary coil of the transformer. 
     For example, the amplifier circuit has a start frequency of 0.8 Gigahertz (GHz), a stop frequency of 1.2 GHz and a step frequency of 0.01 GHz. Input port terminator  83  has an impedance of 350 Ohms. Inductance  72  has a value of 20 nH. Resistance  77  has a resistance of 90 Ohms. Resistance  78  has a resistance of 50 Ohms. FET  71  has a width of 1000 micrometers, a gate-to-source voltage (V GS ) equal to 0.5 volts and a drain-to-source voltage (V DS ) equal to 3 volts. Common node inductance  73  has a value of 2 nH. Inductance  75  has a value of 2 nH. Output port terminator  85  has an impedance of 25 Ohms. Output port terminator  86  has an impedance of 25 Ohms. 
     While FIG. 5 shows a common drain amplifier topology, as will be understood by persons of ordinary skill in the art, a transformer balun may be used with a common source amplifier topology, a common gate amplifier topology, a bipolar transistor amplifier topology, a tube amplifier topology or some other form of amplifier topology. 
     The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.