Abstract:
A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 13/074,785, filed Mar. 29, 2011, U.S. Pat. No. 8,207,768 which is a divisional of U.S. patent application Ser. No. 12/361,320, filed Jan. 28, 2009, U.S. Pat. No. 7,928,782. These applications and patents are incorporated by reference herein in their entirety and for all purposes. 
    
    
     TECHNICAL FIELD 
     This invention relates to locked loops, such as delay lock loops (“DLLs”) and phase lock loops (“PLLs”), and, more particularly, to locked loops having operating parameters that may be configured. 
     BACKGROUND OF THE INVENTION 
     A variety of components are included in integrated circuits that affect the rate at which power is consumed. For example, delay lock loops are often found in memory devices to perform such functions as synchronizing one signal, such as a data strobe signal DQS, to another signal, such as an external clock signal. The DQS signal can then be used to latch data at a time that is synchronized with the external clock signal. 
     A typical prior art DLL  10  is shown in  FIG. 1 . The DLL  10  includes a delay line  14 , which typically uses a large number of gates and/or inverters that are coupled to each other in series. At least some of the gates and/or inverters in the delay line  14  switch at each transition of a reference clock signal CLK REF  that is applied to the input of the delay line  14 . Each time the gates and/or inverters switch, they consume power. The DLL  10  also includes a phase detector  16  and control circuitry  18  coupled to the output of the phase detector  16  for adjusting the delay of the delay line  14 . The phase detector  16  compares the phase of the reference clock signal CLK REF  to the phase of an output clock signal CLK OUT  generated by delay line  14  to determine a phase error. The CLK OUT  signal is thus used as a feedback clock signal, although other signals derived from the CLK OUT  signal may instead be used as the feedback clock signal. If the phase detector  16  is a digital phase detector, it typically generates an UP signal if the phase of the CLK OUT  signal leads the phase of the CLK REF  signal by more than a first value. The control circuitry  18  responds to the UP signal by increasing the delay of the delay line  14  to reduce the phase error. Similarly, the phase detector  16  generates a DN signal if the phase of the CLK OUT  signal lags the phase of the CLK REF  signal by more than a second value. In that case, the control circuitry  18  responds to the DN signal by decreasing the delay of the delay line  14  to reduce the phase error. The phase detector  16  generates neither an UP signal or a DN signal if the magnitude of the phase error is between the first value and the second value. The first and second values thus establish a hysteresis for the DLL  10 . 
     The amount of hysteresis provided by the phase detector  16  has several effects on the operating performance of the DLL  10 . Reducing the hysteresis results in a “tighter” loop that causes the phase of the CLK OUT  signal to more closely follow the phase of the CLK REF  signal. On the other hand, increasing the hysteresis allows the phase of the CLK OUT  signal to drift farther from the phase of the CLK REF  signal. However, the power consumed by the DLL  10  is also affected by the hysteresis since power is consumed each time the phase detector  16  generates an UP or DN signal and the control circuitry  18  and delay line  14  respond accordingly. Thus, a smaller hysteresis generally results in more frequent delay line adjustments because the permissible phase error tolerance is correspondingly smaller. Thus, the power consumed by the DLL  10  can be reduced by increasing the size of the hysteresis provided by the phase detector  16 . Also, a smaller hysteresis makes the DLL  10  more susceptible to noise since noise imparted to the CLK REF  signal and/or the CLK OUT  signal can momentarily increase the difference in phase between the CLK REF  and the CLK OUT  signals beyond the phase error tolerance. 
     Another operating parameter of the DLL  10  that can effect power consumption is the tracking speed of the DLL  10 , i.e., how frequently the phase detector  16  compares the phase of the reference clock signal CLK REF  to the phase of an output clock signal CLK OUT . A high tracking speed in which the phase detector  16  compares the phase of the reference clock signal CLK REF  to the phase of an output clock signal CLK OUT  every cycle of the reference clock signal CLK REF  causes a relatively high power consumption since power is consumed each time the phase comparison is made and the control circuitry  18  and delay line  14  respond to a phase error. However, a longer interval between phase comparisons resulting in a relatively slow tracking speed may allow a phase error to drift well outside the error tolerance set by the hysteresis. 
     The size of the hysteresis provided by a phase detector as well as the tracking speed and other operating parameters of DLLs are determined by the design of the DLLs. Designers of DLLs normally select circuit components to provide a specific set of performance parameters. However, these performance parameters may not be optimum for a specific application in which a DLL is used. For example, as mentioned above, a DLL may be used in an integrated circuit memory device. One purchaser of the memory device may install it in a laptop computer or other portable device. For this application, a large hysteresis and/or a slow tracking speed providing low power consumption may be more important than the accuracy at which the phase of a clock signal generated by the DLL corresponds to the phase of a reference clock signal. Another purchaser of the memory device may install it in a high-speed desktop computer where the memory device operates at a very high clock speed. For this application, the ability of the memory device to correctly latch data may depend on a DQS signal generated by the DLL closely tracking the phase of a reference clock signal. As a result, a small hysteresis and a high tracking speed may be desired. Unfortunately, the operating parameters of conventional DLLs used in memory devices and other integrated circuits cannot be easily adjusted by users or other circuits, thus potentially resulting in performance limitations in electronic devices containing such integrated circuits. 
     Although the problem of operating parameter adjustment inflexibility has been discussed in the context of DLLs, the problem also exists in other types of locked loops, such as phase lock loops. 
     There is therefore a need for a locked loop and method in which the operating parameters can be easily adjusted for optimal performance in different applications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a conventional delay lock loop. 
         FIG. 2  is a block diagram of a delay lock loop according to an embodiment of the invention. 
         FIG. 3  is a block diagram of an embodiment of a phase detector that may be used in the delay lock loop of  FIG. 2 . 
         FIGS. 4A-C  are timing diagrams showing various phase relationships between a reference clock signal and an output clock signal. 
         FIG. 5  is a block diagram of a delay lock loop system according to an embodiment of the invention. 
         FIG. 6  is a block diagram of a delay lock loop system according to another embodiment of the invention. 
         FIG. 7  is a block diagram of a delay lock loop system according to still another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     An embodiment of a DLL  50  according to an embodiment of the invention is shown in  FIG. 2 . The DLL  50  may use the same delay line  14  and control circuit  18  that is used in the DLL  10  of  FIG. 1 . However, a phase detector  54  used in the DLL  50  differs from the phase detector  16  used in the DLL  10  of  FIG. 1 . The phase detector  54  includes an input for receiving a hysteresis control signal that adjusts the hysteresis provided by the phase detector  54 . As explained in greater detail below, the hysteresis of the phase detector  54  may be adjusted by a user or other circuit when the DLL  50  or a device containing the DLL  50  is placed in operation. Thus, the user or other circuit may select a large hysteresis to conserve power or the user or other circuit may select a small hysteresis for good noise immunity and/or where it is important for the output of the DLL  50  to closely follow the phase of a reference clock signal. 
     With further reference to  FIG. 2 , the DLL  50  also includes a frequency divider  60  positioned between the input of the delay line  14  and one of the inputs of the phase detector  54 . Similarly, a second frequency divider  64  is positioned between the output of the delay line  14  and the other input of the phase detector  54 . When enabled by a DividerEnable signal, the frequency dividers  60 ,  64  divide the frequency of the reference clock signal CLK REF  and the output clock signal CLK OUT , respectively, by a divisor N to generate respective CLK R  and CLK O  signals. As a result, the rate at which the phase detector  54  compares the phase of the reference clock signal CLK REF  to the phase of the output clock signal CLK OUT  is also reduced by N, thereby reducing the tracking speed of the DLL  50 . However, as explained above, power is consumed each time the phase detector  54  generates an UP or DN signal and the control circuitry  18  and delay line  14  respond accordingly. Therefore, the power consumed by the DLL  50  can be reduced by enabling the frequency dividers  60 ,  64  to divide the respective clock signals by N. One the other hand, if it is important for the output clock signal CLK OUT  to closely follow the phase of a reference clock signal CLK REF , particularly if the phase of the reference clock signal or the output clock signal varies at a high rate, the frequency dividers  60 ,  64  can be disabled so that they simply couple the reference clock signal CLK REF  and the output clock signal CLK OUT  to the respective inputs of the phase detector  54 . 
     In the embodiment shown in  FIG. 2 , the frequency dividers  60 ,  64  operate in a binary manner by either dividing the reference clock signal CLK REF  and the output clock signal CLK OUT  by N or not. However, in another embodiment, the value of N can be selected among a plurality of choices depending upon the desired tradeoff between high phase accuracy and good noise immunity on one hand and low power consumption on the other. 
     An embodiment of the phase detector  54  used in the DLL of  FIG. 2  is shown in  FIG. 3 . The phase detector includes a pair of delay lines  74 ,  76  that delay the clock signal CLK R  from the divider  60  and the clock signal CLK O  from the divider  64 , respectively, by a delay value T VD . The output of the delay line  74  is applied to the data input D of, a first flip-flop  84 , and the output of the delay line  76  is applied to the data input D of, a second flip-flop  86 . The first flip-flop  84  is clocked by the clock signal CLK O , and the second flip-flop  86  is clocked by the clock signal CLK R . As a result, the first flip-flop  84  outputs the level of delayed clock signal CLK R  at the rising edge of the clock signal CLK O . Therefore, with reference to  FIG. 4A , the first flip-flop  84  compares the time t O  to the time t DR . As long as t O  is not later than t DR , the output of the delay line  74  will be low when the flip-flop  84  is clocked so that the flip-flop  84  will output an inactive low DN signal. On the other hand, if t O  is later than t DR  as shown in  FIG. 4B , the output of the delay line  74  will be high when the flip-flop  84  is clocked. The flip-flop  84  will therefore output an active high DN signal to cause the control circuit  18  ( FIG. 2 ) to apply a signal to the delay line  14  to reduce the delay of the delay line  14 . As a result, the delay of the CLK O  signal relative to the CLK R  signal will be reduced toward the phase relationship shown in  FIG. 4A . 
     As mentioned above, the second flip-flop  86  is clocked by the clock signal CLK R  so that the second flip-flop  86  outputs the level of delayed clock signal CLK O  at the rising edge of the clock signal CLK R . Returning to  FIG. 4A , the second flip-flop  86  therefore compares the time t DO  to the time t R . As long as t DO  is not earlier than t R , the output of the delay line  76  will be low when the flip-flop  86  is clocked so that the flip-flop  86  will output an inactive low UP signal. If t DO  is earlier than t R  as shown in  FIG. 4C , the output of the delay line  76  will be high when the flip-flop  86  is clocked. The flip-flop  86  will therefore output an active high UP signal to increase the delay of the delay line  14 . As a result, the delay of the CLK O  signal relative to the CLK R  signal will be increased toward the phase relationship shown in  FIG. 4A . Insofar as each of the delay lines  74 ,  76  delay the respective clock signals CLK R  and CLK O  by a delay of t VD , the size of the hysteresis is 2t VD . However, in other embodiments the delay of the delay line  74  is different from the delay of the delay line  76 . 
       FIG. 5  is a block diagram of a delay lock loop system  80  according to an embodiment of the invention. The system  80  uses the DLL  50  of  FIG. 2  or a DLL according to some other embodiment of the invention. The DLL  50  is coupled to a temperature sensor  84  that generates the hysteresis control signal and the DividerEnable signal as a function of the temperature, and hence the power consumed by, an electronic device (not shown) containing the system  80 . However, in other embodiments the power consumed by an electronic device (not shown) containing the DLL  50  is sensed by other means. 
     A delay lock loop system  90  according to another embodiment of the invention is shown in  FIG. 6 . The system  90  again uses the DLL  50  of  FIG. 2  or a DLL according to some other embodiment of the invention. The DLL  50  is coupled to a command decoder  94  used in a memory device, such as a dynamic random access memory device or a flash memory device. The command decoder  94  generates the hysteresis control signal and the DividerEnable signal as a function of the operation being performed by the memory device containing the command decoder  94 . For example, when data are not being read from or written to the memory device, the command decoder  94  may generate a DividerEnable signal and a hysteresis control signal that causes the DLL  50  to remain locked, but allows the phase of the output clock signal CLK OUT  to deviate substantially from the phase of the reference clock signal. On the other hand, when data are, being written to the memory device at a high rate of speed, the command decoder  94  may generate a DividerEnable signal that disables the frequency dividers  60 ,  64  and a hysteresis control signal that provides only a small amount of hysteresis. The phases error tolerance during a read operation may be greater than that of a write, so that the command decoder  94  may generate a hysteresis control signal that provides a larger amount of hysteresis, although it may still generate a DividerEnable signal that enables the frequency dividers  60 ,  64 . 
     A delay lock loop system  100  according to still another embodiment of the invention is shown in  FIG. 7 . The system  100  also uses the DLL  50  of  FIG. 2  or a DLL according to some other embodiment of the invention, and the DLL  50  is coupled to a mode register  104  of the type frequently used in memory devices. The mode register  104  may be programmed to generate a hysteresis control signal and a DividerEnable signal appropriate to a particular application in which the memory device is used. 
     Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the invention. For example, although the embodiments are primarily disclosed in the context of delay lock loops, it will be understood that other embodiments may include other types of locked loops, such as phase lock loops. Also, although the disclosed embodiments of the invention use both a phase detector having a variable hysteresis and frequency dividers dividing the reference clock signal CLK REF  and the output clock signal CLK OUT  by a divisor, it should be understood that either of these features may be used alone. Thus, a locked loop may include a phase detector having a fixed hysteresis and frequency dividers dividing the reference clock signal CLK REF  and the output clock signal CLK OUT  by a divisor. A locked loop may also include a phase detector having a variable hysteresis but no frequency dividers. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.