Abstract:
A video signal transfer system including an imaging apparatus for capturing an object to be imaged and generating a consecutive plurality of picture data forming a moving image, selecting from the plurality of picture data picture data positioned in advance at predetermined intervals to generate a plurality of lines (series) of video signals, and transmitting the plurality of systems of video signal, and a signal processing apparatus having a plurality of signal processing circuits, outputting the plurality of lines of video signals received from the imaging apparatus to the plurality of signal processing circuits, and making them process the signals in parallel.

Description:
CROSS REFERENCES TO RELATED APPLICATION 
       [0001]    This application is a continuation of U.S. application Ser. No. 11/461,882 filed Aug. 2, 2006, which contains subject matter related to Japanese Patent Application No. 2005-261066 filed in the Japan Patent Office on Sep. 8, 2005, and Japanese Patent Application No. 2005-330533 filed in the Japan Patent Office on Nov. 15, 2005, the entire contents of each of which are being incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a video signal transfer system for transmitting video signals captured by a video camera for example to a later signal processing system and to an imaging apparatus, a signal processing apparatus, and a video signal transfer method used for that. 
         [0004]    2. Description of the Related Art 
         [0005]    For example, there is a video signal transfer system which performs high speed imaging at a high resolution by an imaging apparatus and transmits that video signal from the imaging apparatus to a signal processing apparatus. 
         [0006]    Such a video signal transfer system performs control, in accordance with what speed the signal processing apparatus outputs the video signal, to transmit a video signal of that speed from the imaging apparatus to the signal processing apparatus. 
         [0007]    Further, the imaging apparatus processes the video signal for gain control and auto alias level detection or other feedback processing, knee processing, and gamma correction. (refer to Japanese Patent Publication (A) No. 2000-188703). 
         [0008]    Further, the signal processing apparatus serially processes the video signal captured at a high speed imaging for color correction etc. 
         [0009]    However, in the above-mentioned video signal transfer system, since the speed of the video signal transmitted from the imaging apparatus to the signal processing apparatus is controlled in accordance with the speed of the video signal outputted by the signal processing apparatus, it suffers from the disadvantages that the amount of processing of the imaging apparatus is large, reduction of size is difficult, and the small size is complicated, and the power consumption is large. 
         [0010]    Further, the signal processing apparatus adds the plurality of video signals obtained by the high speed imaging to generates a standard speed video signals, but in this case, in the imaging apparatus, the video signals shown in  FIG. 9A  deform as shown in  FIG. 9B  due to the gamma processing and knee processing, so if combining these to generate a standard speed video signal, as shown in  FIG. 9C , it suffers from the disadvantages that the standard speed video signal will suffer from unnatural edges or tones and the picture quality will become lower. 
       SUMMARY OF THE INVENTION 
       [0011]    It is therefore desirable in the present invention to provide a video signal transfer system, imaging apparatus, signal processing apparatus, and video signal transfer method enabling reduction of the amount of processing of the imaging apparatus when transferring a video signal generated by the imaging apparatus to the signal processing apparatus. 
         [0012]    It is also desirable in, the present invention to provide a video signal transfer system, imaging apparatus, signal processing apparatus, and video signal transfer method able to suppress a drop in quality of the video signal output by the above signal processing apparatus. 
         [0013]    A video signal transfer system of a first aspect of the invention has an imaging apparatus for capturing an object to be imaged and generating a consecutive plurality of picture data forming a moving image, selecting from the plurality of picture data picture data positioned in advance at predetermined intervals to generate a plurality of lines (series) of video signals, and transmitting the plurality of lines of video signal, and a signal processing apparatus having a plurality of lines processing circuits, outputting the plurality of systems of video signals received from the imaging apparatus to the plurality of signal processing circuits, and making them process the signals in parallel. 
         [0014]    An imaging apparatus of a second aspect of the invention is an imaging apparatus transmitting imaging results to a signal processing apparatus having an imaging unit for capturing an object to be imaged and generating a consecutive plurality of picture data forming a moving image, a signal processing circuit for selecting from the plurality of picture data generated by the imaging unit the picture data positioned at predetermined intervals in advance to generate a plurality of lines (series) of video signals, and a transfer circuit for transmitting the plurality of lines of video signals generated by the signal processing circuit to the signal processing apparatus. 
         [0015]    A signal processing apparatus of a third aspect of the invention is a signal processing apparatus for processing a plurality of lines (series) of video signals received from an imaging apparatus capturing an object to be imaged to generate a consecutive plurality of picture data forming a moving image, selecting from the plurality of picture data the picture data positioned at predetermined intervals in advance to generate N (≧2) lines (series) of video signals, having N number of signal processing circuits, a separating unit for outputting the N systems of video signals received from the imaging apparatus to the N number of signal processing circuits and making them process the signals in parallel, and an external apparatus outputting 1/N picture time&#39;s worth of picture data of the N number of video signals input from the N number of the signal processing circuits in one picture time. 
         [0016]    A video signal transfer method of a fourth aspect of the invention is a video signal transfer method transmitting imaging results of an imaging apparatus to a signal processing apparatus, having a first step of having the imaging apparatus configured to capture an object to be imaged and generate a consecutive plurality of picture data forming a moving image, a second step of having the imaging apparatus select from the plurality of picture data generated at the first step the picture data positioned at predetermined intervals in advance to generate a plurality of lines (series) of video signals and transmit the plurality of lines of video signals to the signal processing apparatus, and a third step of having the signal processing apparatus output the plurality of lines of video signals received from the imaging apparatus at the second step to the plurality of signal processing circuits and make them process the signals in parallel. 
         [0017]    According to the present invention, it is achieved a video signal transfer system, imaging apparatus, signal processing apparatus, and video signal transfer method enabling reduction of the amount of processing of the imaging apparatus when transferring a video signal generated by an imaging apparatus to a signal processing system. 
         [0018]    Further, the present invention can provide a video signal transfer system, imaging apparatus, signal processing apparatus, and video signal transfer method able to suppress a drop in quality of the video signal output by the above signal processing apparatus. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the attached drawings, wherein: 
           [0020]      FIG. 1  is a view of the configuration of a video signal capturing, video signal processing, and transferring system of a first embodiment of the present invention; 
           [0021]      FIG. 2  is a view of the configuration of a video camera and a video signal processing and control unit shown in  FIG. 1 ; 
           [0022]      FIG. 3  is a diagram showing the configuration of an image signal processor circuit in the video camera shown in  FIG. 2 ; 
           [0023]      FIGS. 4A to 4B  are diagrams showing the image signal transferred by the image signal processor circuit shown in  FIG. 3 ; 
           [0024]      FIG. 5  is a diagram showing the configuration of a normal speed image signal generator circuit shown in  FIG. 2 ; 
           [0025]      FIGS. 6A to 6C  are diagrams for explaining a switching operation of the video signal processing and control unit shown in  FIG. 2 ; 
           [0026]      FIGS. 7A to 7D  are diagrams showing processing results of the image signal according to a first embodiment of the present invention; 
           [0027]      FIGS. 8A to 8B  are diagrams for explaining the image signal according to a second embodiment of the present invention; and 
           [0028]      FIGS. 9A to 9C  are diagrams for explaining the problem in a conventional signal transferring system. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0029]    Below, the camera system according to embodiments of the present invention will be explained. 
       First Embodiment 
       [0030]    First, the correspondence between the components of the present embodiment and the components of the present invention will be explained. 
         [0031]    The video camera  10  is one example of an imaging apparatus of the present invention, and a camera control unit  12  is one example of a signal processing apparatus of the present invention. 
         [0032]    Further, the field pictures or frame pictures of the present embodiment are examples of the picture data of the present invention. 
         [0033]    Further, the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  of the present embodiment are examples of the plurality of lines (series) of video signals of the present invention. 
         [0034]    Further, the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  of the present embodiment are examples of the plurality of signal processing circuits of the present invention. 
         [0035]    Further, the buffer memory  32  is an example of the memory of the present invention, the viewfinder  33  is an example of the display of the present invention, and the signal processing circuit  34  is an example of the signal processing unit of the present invention. 
         [0036]    Further, the preprocessing circuit  42  is an example of the separating unit of the present invention, and the addition circuit  71  is an example of the addition circuit of the present invention. 
         [0037]      FIG. 1  is a view of the overall configuration of a camera system  1  of the present embodiment. 
         [0038]    As shown in  FIG. 1 , the camera system  1  has, for example, a video camera  10 , camera control unit  12 , and VTR or switcher (herein after VTR/switcher)  14 . An external apparatus  20  is connected to the VTR/switcher  14 . 
         [0039]    The video camera  10  generates a video signal in accordance with the imaging results and outputs it through an optical fiber cable  16  to the control unit  12 . 
         [0040]    The camera control unit  12  processes the video signal inputted from the video camera  10  to generate an SDI (serial digital interface) type of video signal based on the SMPTE and outputs this through a cable  18  to the VTR/switcher  14 . 
         [0041]    The VTR/switcher  14  records or transmits the video signal inputted from the camera control unit  12 . 
         [0042]    The optical fiber cable  16 , for example, is a composite optical fiber cable made up of optical fiber for transmitting and receiving and metacables for power line and control use. 
         [0043]    In the camera system  1 , for example, the video camera  10  is arranged in a studio, and the camera control unit  12  and VTR/switcher  14  are arranged in a secondary adjustment room. 
         [0044]    Due to this, when recording a program by the video camera  10  in the studio, this video signal and audio signal are outputted through the optical fiber cable  16  to the camera control unit  12  of the secondary adjustment room. 
         [0045]    Further, the processed video signal and audio signal from the camera control unit  12  is outputted through the cable  18  to the VTR/switcher  14 . 
         [0046]    Further, the VTR/switcher  14  performs signal processing for recording, editing, and transmitting the video signal and audio signal. 
         [0047]    Below, the video camera  10  and camera control unit  12  will be explained in detail. 
         [0048]      FIG. 2  is a view of the configuration of the video camera  10  and the camera control unit  12 . 
         [0049]    [Video Camera  10 ] 
         [0050]    The video camera  10 , as shown in  FIG. 2 , has, for example, an imaging device  31 , buffer memory  32 , viewfinder  33 , signal processing circuit  34 , and transfer circuit  35 . 
         [0051]    The imaging device  31  is, for example, a CMOS (Complementary Metal Oxide Semiconductor), CCD (Charge-Coupled Device), or other imaging device and outputs a video signal  31  in accordance with the imaging results to the signal processing circuit  34 . 
         [0052]    The imaging device  31 , for example, performs high speed imaging at 3× (three times worth) speed of the standard (normal) speed and generates an interlace format video signal S 31 . 
         [0053]    Note that light is focused on the imaging device  31  adjusted by a focusing mechanism. Further, the imaging results of the imaging device  31  are output as the video signal S 31  after gain control. 
         [0054]    The buffer memory  32  stores the video signal processed in the signal processing circuit  34 . 
         [0055]    The viewfinder  33  reads out and displays the video signal S 31  stored in the buffer memory  32  under the control of the signal processing circuit  34 . 
         [0056]      FIG. 3  is a view of the configuration of the signal processing circuit shown in  FIG. 2 . 
         [0057]    As shown in  FIG. 3 , the signal processing circuit  34  has, for example, an A/D conversion circuit  61 , signal processing circuit  62 , memory access circuit  63 , and rearrangement circuit  64 . 
         [0058]    The A/D conversion circuit  61  converts an analog video signal S 31  inputted from the imaging device  31  to a digital video signal and outputs it to the signal processing circuit  62 . 
         [0059]    The signal processing circuit  62  processes the digital video signal inputted from the A/D conversion circuit  61  relating to feedback control so as to generate the video signal S 34   a  and outputs it to the memory access circuit  63 . The memory access circuit  63  writes the video signal S 34   a  in the buffer memory  32 . 
         [0060]    In the present embodiment, the signal processing relating to the above feedback control, for example, includes gain control processing and auto alias level detection processing etc. 
         [0061]    The memory access circuit  63  writes the video signal S 34   a  inputted from the signal processing circuit  62  in the buffer memory  32 . 
         [0062]    Further, the memory access circuit  63  reads out one of the fields for each consecutive 3 fields in the video signal S 34   a  from the buffer memory  32  and outputs it to the viewfinder  33 . 
         [0063]    The rearrangement circuit  64  receives as input the video signal S 34   a  read by the memory access circuit  63  from the buffer memory  32 . When the video signal S 31  is of an interlace format, it rearranges the video signal S 34   a,  as shown in  FIG. 4 , so that the former 3 fields  1 T,  1 B,  2 T of 6 fields forming one group match in time (become parallel) and outputs them as the video signal S 34  to the transfer circuit  35 . 
         [0064]    In  FIG. 4 , “T” indicates a top field, and “B” indicates a bottom field. 
         [0065]    Further, the rearrangement circuit  64 , as shown in  FIG. 4 , rearranges, after the above former 3 fields  1 T,  1 B,  2 T, the latter 3 fields  2 B,  3 T, and  3 B of the above 6 fields so as to match in time (become parallel) and outputs them as the video signal S 34  to the transfer circuit  35 . 
         [0066]    That is, the rearrangement circuit  64 , as shown in  FIG. 4B , generates a video signal comprised of three lines (series) of video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3 . 
         [0067]    In the camera system  1 , by the signal processing circuit  34  of the video camera  10  rearranging field pictures in groups of 6 field pictures as explained using  FIG. 4 , the latter camera control unit  12  can realize the processing for adding the 3× speed captured field pictures and displaying of a standard speed image by a simple addition circuit. 
         [0068]    The transfer circuit  35  transmits the video signal S 34  inputted from the rearrangement circuit  64  in parallel or by time division through the optical fiber cable  16  to the camera control unit  12 . 
         [0069]    For example, the transfer circuit  35  transmits one 10.692 GHz video signal S 34  comprised of R, G, B 12-bit signals mapped to a serial signal to the optical fiber cable  16 . 
         [0070]    Further, in the case of 3× (three times worth) speed transmission, the transfer circuit  35  may transmit the video signal S 34  as six 1.485 GHz serial SDI signals through a BNC cable to the control unit  12 . Note that the 3× speed (three times worth speed to a normal speed) is an example. The present embodiment may also be applied to high speed transfer (N× (N times worth) speed transmission) other than 3× speed. 
         [0071]    As explained above, the video camera  10  transmits the video signal S 34  of the format shown in  FIG. 4  to the camera control unit  12  regardless of the speed of the video signal S 12  outputted by the camera control unit. 
         [0072]    Further, in camera system  1 , as explained above, the video signal is processed relating to feedback control, but Knee processing or gamma correction processing or other predetermined processing for improvement of quality, compression, etc. are not performed. 
         [0073]    Due to this, the processing load of the video camera  10  can be reduced more than before. 
         [0074]    [Camera Control Unit  12 ] 
         [0075]    The camera control unit  12  has, as shown in  FIG. 2 , a transfer circuit  41 , preprocessing circuit  42 , signal processing circuit  43 _ 1 ,  43 _ 2 ,  43 _ 3 ,  45 , and format conversion circuit  47 . 
         [0076]    The transfer circuit  41  performs reverse format conversion from the transfer circuit  35  on the video signal S 34  received through the optical fiber cable  16  from the video camera  10  and outputs the result to the preprocessing circuit  42 . 
         [0077]      FIG. 5  is a view of the configuration of the preprocessing circuit  42  as shown in  FIG. 2 . 
         [0078]    The preprocessing circuit  42 , as shown in  FIG. 5 , outputs the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  forming the video signal S 34  inputted from the transfer circuit  41  to the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3 . 
         [0079]    Further, the preprocessing circuit  42 , as shown in  FIG. 5 , is provided with an addition circuit  71 . 
         [0080]    The addition circuit  71  adds the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  forming the video signal S 34  inputted from the transfer circuit  41  to generate the standard speed video signal S 42  and outputs it to the signal processing circuit  45 . 
         [0081]    In the present embodiment, the video signal S 34 , as shown in  FIG. 4(B) , includes three lines (series) of video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  stored in parallel, so there is no need to provide a memory for storing a large amounts of video signals before addition by the addition circuit  71 . 
         [0082]    The signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  process the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  for predetermined improvement of the quality, compression, etc. so as to generate the video signals S 43 _ 1 , S 43 _ 2 , S 43  and outputs these as the video signal S 12  to the VTR/switcher shown in  FIG. 1 . 
         [0083]    The above signal processing performed by the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  include, for example, Knee processing (processing to compress multi-bits of pixel data to reduce load of color processing), gamma correction functions (processing to maximize input value to ideal output value in order to give vivid color), detail processing, etc. 
         [0084]    Further, the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3 , for example, when reading out and replaying video signals stored in the VTR/switcher  14 , perform processing to expand the read compressed video signals. The expanded video signals are outputted through the transfer circuit  41  to the video camera  10 . 
         [0085]    The signal processing circuit  45  processes the standard speed video signal imputed from the preprocessing circuit  42  for predetermined improvement of quality, compression, etc. to generate the video signal S 45  and outputs this as the video signal S 12  to the VTR/switcher shown in  FIG. 1 . 
         [0086]    The format conversion circuit  47  receives as input the video signal S 45  from the signal processing circuit  45 , converts it to a video signal  47  of a predetermined format, and outputs it as the video signal S 12  to the VTR/switcher  14  shown in  FIG. 1 . This conversion, for example, is conversion that down converts an HD (High Definition) video signal to an SD (Standard Definition) video signal (NTSC system etc.). 
         [0087]    [VTR/Switcher  14 ] 
         [0088]    The VTR/switcher  14 , in the case of 3× speed video output, as shown in  FIG. 6(B) , switches the video signals S 43 _ 1 , S 43 _ 2 , S 43 _ 3  inputted from the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  and outputs the 3× speed video signal S 14 . 
         [0089]    On the other hand, the switch  48 , in the case of standard speed video output, as shown in  FIG. 6(C) , outputs the video signal S 45 , obtained by adding the video signals S 43 _ 1 , S 43 _ 2 , S 43 _ 3  inputted from the signal processing circuit, as the standard speed video signal S 14 . 
         [0090]    In this way, the camera control unit  12  can output the 3× speed or standard speed video signal S 14  by just processing for switching the video signals S 14  inputted from the camera control unit  12 . 
         [0091]    Further, the VTR/switcher  14 , for example, also has the function of writing the video signal S 12  inputted from the camera control unit  12  on to a disk or other recording unit and rearranging it for output when reading it. 
         [0092]    Below, an example of the operation of the camera system  1  of the present embodiment will be explained. 
         [0093]    First, the imaging device of the video camera  10  generates a video signal S 31  in accordance with the imaging results of the imaging subject. 
         [0094]    Next, the A/D conversion circuit  61  of the signal processing circuit  34  shown in  FIG. 3  converts the video signal S 31  to a digital format and writes the processed video signal S 31   a  through the memory access circuit  63  in the buffer memory  32 . 
         [0095]    Next, the rearrangement circuit  64  receives as input the video signal S 34   a  read from the buffer memory  32  through the memory access circuit  63 . When the video signal S 31  is of an interlace format, it rearranges the video signal S 34   a,  as shown in  FIG. 4 , so that the former 3 field pictures  1 T,  1 B,  2 T of the 6 fields forming a group match in time (become parallel) and outputs them as the video signal S 34  comprised of the three lines of standard speed video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3 . 
         [0096]    The transfer circuit  35  transmits the video signal S 34  inputted from the rearrangement circuit  64  in parallel or by time division through the optical fiber cable  16  to the camera control unit  12 . 
         [0097]    The transfer circuit  41  of the camera control unit  12  performs reverse format conversion from the transfer circuit  35  on the video signal S 34  received through the optical fiber cable  16  from the video camera  10  and outputs the result to the preprocessing circuit  42 . 
         [0098]    Next, the preprocessing circuit  42  of the camera control unit  12 , as shown in  FIG. 5 , outputs the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  forming the video signal S 34  inputted from the transfer circuit  41  to the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3 . 
         [0099]    Further, the addition circuit  71  adds the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  forming the video signal S 34  inputted from the transfer circuit to generate the standard speed video signal S 42  and outputs it to the signal processing circuit  45 . 
         [0100]    Further, the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  process the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  for predetermined improvement of quality, compression, etc. to generate the video signals S 43 _ 1 , S 43 _ 2 , S 43 _ 3  and outputs them as the video signal S 12  to the VTR/switcher  14 . 
         [0101]    In parallel with this, the signal processing circuit  45  has processes the standard speed video signal inputted from the preprocessing circuit  42  for predetermined improvement of quality, compression, etc. to generate the video signal S 45  and outputs it as the video signal S 12  to the VTR/switcher  14 . 
         [0102]    Next, the VTR/switcher  14 , in the case of 3× speed video output, as shown in  FIG. 6B , switches from the video signals S 43 _ 1 , S 43 _ 2 , S 43 _ 3  inputted from the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  and outputs the 3× speed video signal S_ 14 . 
         [0103]    On the other hand, the VTR/switcher  14 , in the case of standard speed video output, as shown in  FIG. 6C , outputs the video signal S 45 , obtained by adding the video signals S 43 _ 1 , S 43 _ 2 , S 43 _ 3  inputted from the signal processing circuit, as the standard speed video signal S 14 . 
         [0104]    As explained above, in the camera system  1 , as shown in  FIG. 4 , the rearrangement circuit  64  of the video camera  10  shown in  FIG. 3  generates three systems of 1× speed video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  from the video signal S 31  captured at 3× speed shown in  FIG. 4A  and transmits it to the camera control unit  12  in accordance with their timings. 
         [0105]    Further, the camera control unit  12  performs parallel processing on the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  received from the video camera  10  at the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  shown in  FIG. 2 . 
         [0106]    Due to this, the camera control unit  12  can process a video signal captured at 3× speed in a short time. 
         [0107]    Further, in the camera system  1 , the signal processing circuit  62  of the video camera  10  shown in  FIG. 3  processes the digital video signal inputted from the A/D conversion circuit  61  for gain control, auto alias level detection, or other feedback control. 
         [0108]    Further, the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  of the camera control unit  12  process the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  for Knee processing, gamma correction, or other predetermined improvement of quality, compression, etc. 
         [0109]    Due to this, for example, when the addition circuit  71  of the preprocessing circuit  42  shown in  FIG. 5  adds the three systems of video signals to generate a standard speed video signal, as shown in  FIGS. 7B and 7C , it can add them in a state without image processing and can therefore avoid a drop in quality as explained with reference to  FIG. 9 . 
         [0110]    Further, in the camera system  1 , the image processing for improvement of quality is not performed by the video camera  10 , but by the camera control unit  12 , so the amount of processing and power consumption of the video camera  10  can be reduced. This effect is particularly remarkable in the case of using, as a video signal, an HD signal with several times larger an amount of data than SD. 
         [0111]    In the camera system  1 , the video camera  10  temporarily stores the picture data generated at the imaging device  31  in the buffer memory  32 , then reads it out and displays the image on the viewfinder  33 . For this reason, even when no communication link is established between the video camera  10  and the camera control unit  12 , it is still possible to display a captured image on the viewfinder  33 . Due to this, the system setup can be made more efficient. 
         [0112]    Further, the viewfinder  33  can display an image with almost no delay and can track and display an image of an object moving at a high speed. 
         [0113]    In the camera system  1 , it is possible to change the speed of the video signal S 14  in the VTR/switcher  14  without changing the capture speed of the imaging device  31 . Due to this, operation control of the imaging device  31  becomes simple. 
         [0114]    In the camera system  1 , the video camera  10  generates three lines of standard speed video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  from the high speed captured video signal S 31  and transmits them to the camera control unit  12 . Further, the camera control unit  12  processes the three lines of standard speed video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  at the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3  in parallel, then switches and outputs the results so as to output a 3× speed video signal. 
         [0115]    Due to this, the video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3  can be constantly processed at standard speed, and the circuit configuration can be made simple and inexpensive. 
         [0116]    Further, in the camera system  1 , the video camera  10  generates three lines of standard speed video signals S 34 _ 1 , S 34 _ 2 , S 34 _ 3 , so the camera control unit  12  does not need to be provided with a large scale memory. The effect is particularly remarkable in cases where, as the video signal, an HD image with several times the amount of data compared with the SD is used. Further, in the camera system  1 , common signal processing circuits can be used as the signal processing circuits  43 _ 1 ,  43 _ 2 ,  43 _ 3 , so even if the image capture speed is increased to 3× (three times) or more, this can be handled by just increasing the same signal processing circuits. 
         [0117]    Further, in the camera system  1 , the video signal transmitted from the video camera  10  to the camera control unit  12  is not compressed, so high quality video output is possible. 
         [0118]    Further, in the camera system  1 , a standard speed video signal is generated by addition before camera signal processing by the signal processing circuit  45 , so it is possible to output high quality video as standard speed video. In this way, because the standard speed video is high quality, usage as a standard speed imaging camera and not just as a high speed imaging camera is possible. 
         [0119]    In the past, high speed video and standard speed video can be outputted at the same time, so it is possible to combine the two separate lines required for high speed imaging and standard speed imaging into one. 
         [0120]    Further, in the camera system  1 , because there are a plurality of return systems (paths), the types of signals that can be taken by the camera are increased and flexible application as a system is possible. 
         [0121]    Further, the processed signal to be displayed on the viewfinder  33  may be selected from one with an added natural dynamic resolution feel or a high speed video with a shutter effect, so the optimal video (picture) can be displayed on the viewfinder  33  in accordance with the objective. 
         [0122]    Further, the video signal returning from the camera control unit  12  to the video camera  10  for display on the viewfinder  33  may be selected from one system of processed high speed output with a shutter effect or added standard speed video with natural motion. 
         [0123]    In addition to this, as an independent return system is located in the video camera  10 , it is possible to obtain a video signal, other than the video signal displayed on the viewfinder  33 , from the output terminal provided at the camera at the same time as displaying the video of the camera video returned from the camera control unit  12 . 
       Second Embodiment 
       [0124]    In the above-mentioned first embodiment, a case was illustrated where the imaging device  31  generated a video signal  31   a  of an interlaced format, however, in the present embodiment, as shown in  FIG. 8A , the imaging device  31   a  generates a video signal S 31   a  of a progressive format. 
         [0125]    In this case, the rearrangement circuit  64 , as shown in  FIG. 8B , assigns consecutive frames (for example, “1”, “2”, “3”) in groups of three frames to the plurality of different video signals S 34 _ 1   a,  S 34 _ 2   a,  S 34 _ 3   a.    
         [0126]    In this way, when the imaging device  31  generates a video signal S 31   a  of a progressive format, effects similar to the case of the first embodiment can be obtained. 
         [0127]    The present invention is not limited to the above embodiments. 
         [0128]    Namely, those skilled in the art can perform a variety of modifications, combinations, sub-combinations, and substitutions concerning the components of the embodiments mentioned above within the technical range of the present invention or equivalent range to that. 
         [0129]    For example, in the above embodiments, a case was illustrated where “N” is “3” for the present invention, however, it is possible to apply the present invention in a situation of 2 or more. 
         [0130]    Further, in the above embodiments, a case was illustrated where only feedback processing was performed in the video camera  10 , however, even in cases where gamma correction and Knee processing etc., are performed in the video camera  10 , since the processing of the video camera does not need to be altered in accordance with the speed of the video signal outputted from the camera control unit  12 , the effect of enabling the video camera  10  to be realized by a simple configuration can be obtained.