Abstract:
A television signal determination circuit is associated with an automatic tuning system, which automatically tunes a television set to local channels, in order to determine whether received signals are desired television signals. The television signal determination circuit comprises a first counter means for counting received synchronizing signals for a predetermined period of time, a second counter means for counting reference clock signals for the predetermined period of time, and a determination means for determining whether the synchronizing signals are received by a predetermined number within the predetermined period of time by comparing output signals from the first and second counter means.

Description:
BACKGROUND AND SUMMARY OF THE INVENTION 
     The present invention relates to a television signal determination circuit in an automatic tuning system which automatically tunes a television set to local channels. 
     It is customary to perform tuning operation in TV receivers while a viewer manually rotates a tuning knob. However, the tuning operation is bothersome in the case of the continuously varying tuning operation as in UHF reception. Though tuning operation is considerably simpler in the case of TV receivers of the recently developed touch control type or remote control type, it is considerably difficult for a non-skilled person to preset the tuner, or to adjust the tuning frequencies for respective broadcasting stations before starting to watch a TV receiver. 
     Various automatic tuning systems are proposed to simplify the preset tuning operation in TV receivers. However, there is a possibility that the automatic tuning system will erroneously respond to noises rather than desired television signals. 
     Accordingly, an object of the present invention is to stabilize tuning operation of an automatic tuning system. 
     Another object of the present invention is to provide a television signal determination circuit for determining whether the received signals are desired television signals. 
     Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
     To achieve the above objects, pursuant to an embodiment of the present invention, a television signal determination circuit is provided for determining whether received signals are desired television signals. The television signal determination circuit, in a preferred form, comprises a first counter means for counting received synchronizing signals for a predetermined period of time, a second counter means for counting reference clock signals for the predetermined period of time and a determination means for determining whether the synchronizing signals are received by a predetermined number within the predetermined period of time by comparing output signals from the first and second counter means. When the synchronizing signals are received by the predetermined number within the precetermined period of time, the received signals are considered as the desired television signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: 
     FIG. 1 is a schematic block diagram of an automatic tuning system employing a television signal determination circuit of the present invention; 
     FIG. 2 is a block diagram of an embodiment of a television signal determination circuit of the present invention; 
     FIG. 3 is a block diagram of another embodiment of a television signal determination circuit of the present invention; 
     FIG. 4 is a time chart showing various signals occurring within the circuit of FIG. 3; 
     FIG. 5 is a block diagram of still another embodiment of a television signal determination circuit of the present invention; 
     FIG. 6 is a time chart showing various signals occurring within the circuit of FIG. 5; 
     FIG. 7 is a circuit diagram of an embodiment of synchronizing signal waveform shaping circuit for shaping synchronizing signals to be applied to the television signal determination circuit; and 
     FIGS. 8 through 10 are time charts for explaining operation of the synchronizing signal waveform shaping circuit of FIG. 7. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now in detail to the drawings, and to facilitate an understanding of the present invention, a typical construction of an automatic tuning system will be first described with reference to FIG. 1. 
     A TV receiver including the automatic tuning system mainly comprises an antenna 1, a tuner 2, an intermediate frequency (IF) circuit 3, an automatic fine tuning (AFT) circuit 4, a video circuit 5, a synchronizing separator 6, a deflection circuit 7, a picture tube 8, a start/stop circuit 9, a tuning voltage generator 10, and a memory circuit 11. A signal determination circuit 12 of the present invention is further provided to determine whether received signals are desired television signals. 
     It will be noted that the tuner 2 can be implemented with a well known electronic tuning circuit which includes a voltage-sensitive capacitance diode as disclosed in U.S. Pat. No. 3,233,179 entitled &#34;AUTOMATIC FINE TUNING CIRCUIT USING CAPACITANCE DIODES&#34; issued on Feb. 1, 1966. 
     If the start/stop circuit 9 is given a search start command or an automatic tuning instruction prior to effecting of the preset tuning operation, then the start/stop circuit 9 will develop a search start pulse which in turn is supplied to the tuning voltage generator 10. Under this circumstance the tuning voltage generator 10 develops a sweep voltage or staircase voltage which is gradually rising or dropping during the automatic tuning operation. The sweep or staircase voltage is supplied as the tuning voltage to the tuning capacitance diode in the tuner 2 by way of the memory circuit 11. This implies that the reception frequency in the tuner 2 is gradually varied. 
     In this way, when the television signal of a specific broadcasting channel is received, the television video signal is derived from the IF circuit 3 and the synchronizing signal from the synchronizing separator 6. The synchronizing signal is applied to the start/stop circuit 9. Meantime, the AFT detector output is derived from the AFT circuit 4 and supplied to the start/stop circuit 9. 
     More particularly, when the television signal is accurately received, the AFT detector output voltage will change in polarity so that the start/stop circuit 9 is permitted to develop a search stop pulse and the vertical synchronizing signal. In the given example the vertical synchronizing signal may serve as the search stop pulse. The search stop pulse is supplied to the tuning voltage generator 10, barring the generator 10 from developing the sweep or staircase voltage. The voltage then remains constant and is continuously supplied as the tuning voltage to the tuner 2 via the memory circuit 11. 
     The vertical synchronizing signal derived from the start/stop circuit 9 is supplied to the signal determinating circuit 12 to determine as to whether the signal being received is a normal or true television signal. If the affirmative answer is given, then the signal determination circuit 12 will issue a memory instruction which in turn is supplied to the memory circuit 11 so that the instantaneous tuning voltage derived from the generator 10 is stored within the memory circuit 11. 
     Contrarily, if a false synchronizing signal is derived from the start/stop circuit 9, then the signal determination circuit 12 reacts to it so that the circuit 12 issues a search re-start pulse. This is supplied to the start/stop circuit 9 to repeat the same procedure as when executing the first search start pulse. The procedure is repeated in this manner until the start/stop circuit 9 derives a true television vertical synchronizing signal or accurate reception is available by the tuner 2. 
     In other words, the memory instruction is not issued from the signal determination circuit 12 until the optimum reception state is guaranteed. Upon issuance of the memory instruction the instantaneous tuning voltage is stored in the memory circuit 11 and subsequently supplied to the tuner 2. 
     Once the preset tuning operation (i.e., the presetting of the optimum reception frequency) has been completed for the specific broadcasting channel, the tuning voltage stored in the memory circuit 11 will be automatically supplied to the tuner 2 in response to receipt of a tuning instruction from an operational panel of the known touch control type or remote control type. The searching procedure is thus not required. 
     It is obvious that the memory circuit 11 shown in FIG. 1 includes a predetermined number of memory elements the number of which corresponds to the number of serviceable broadcasting stations. The same searching or presetting procedure is repeated when it is desired to search and memorize a predetermined number of discrete tuning voltage prior to use of a TV receiver. 
     FIG. 2 shows an embodiment of the television signal determination circuit 12 of the present invention. 
     When a vertical synchronizing signal is applied to an input terminal 13 from the start/stop circuit 9, an R-S flip-flop 14 is set to develop a signal of logic &#34;H&#34; through an output terminal Q. The &#34;H&#34; output is applied to one input terminals of AND gates 15 and 16, respectively. Accordingly, the AND gate 15 passes the vertical synchronizing signal therethrough. And, the AND gate 16 passes a reference clock pulse therethrough derived from a clock pulse generator 17. More specifically, when the vertical synchronizing signal is applied to the input terminal 13, the vertical synchronizing signal is applied to a frequency divider 18 through the AND gate 15, and the reference clock pulses derived from the clock pulse generator 17 are applied to another frequency divider 19. 
     When the frequency divider 18 has a division ratio 1/m, and the frequency divider 19 has a division ratio 1/n, the frequency divider 18 develops a signal having a pulsewidth T 1  m and the frequency divider 19 develops a signal having a pulsewidth T 2  n, respectively. The vertical synchronizing signal has a period T 1  =16.7 msec. The division ratios 1/m and 1/n, and the reference clock pulse period T 2  are selected so as to satisfy the following relationship. 
     
         T.sub.1 m&lt;T.sub.2 n 
    
     That is, the count operation of the synchronizing signal conducted by the frequency divider 18 is completed before the count operation of the reference clock signal conducted by the frequency divider 19 is completed. When the count operation of the synchronizing signal is completed by the frequency divider 18, an output signal is applied to a mono-stable multivibrator 20 to activate it, whereby a signal having a predetermined pulsewidth is developed toward an output terminal 21. The thus developed signal indicates that normal vertical synchronizing signals are applied to the input terminal 13 and functions as the memory command to be applied to the memory circuit 11. The output signal of the multivibrator 20 is also applied to the reset terminal R of the flip-flop 14, and the frequency dividers 18 and 19 through an OR gate 22. Therefore, the frequency divider 19 does not develop the count completion output. Thus, another mono-stable multivibrator 23 is not activated and, hence, an output signal does not appear at an output terminal 24. 
     In case where the number of the synchronizing signal is less than the desired number, the frequency divider 19 develops an output signal before the frequency divider 18 develops the output signal. The mono-stable multivibrator 23 is activated to develop an output signal having a predetermined pulsewidth toward the output terminal 24. The thus developed signal indicates that the normal synchronizing signals are not applied to the input terminal 13. The signal derived from the output terminal 24 is applied to the start/stop circuit 9 as the search re-start signal. 
     The output signal of the multivibrator 23 is also applied to the reset terminals R of the flip-flop 14, and the frequency dividers 18 and 19 through the OR gate 22. The Q output of the flip-flop 14 becomes the logic &#34;L&#34;. Therefore, the count operation of the frequency dividers 18 and 19 is terminated. 
     When the vertical synchronizing signal is again applied to the input terminal 13, the above-mentioned operation is repeated to determine whether the applied signal is a true television signal. 
     In summary, when the applied signal is the true television signals, the memory command is developed from the output terminal 21. Contrarily, when the false television signals are applied to the input terminal 13, the search re-start signal is developed from the output terminal 24. 
     In a preferred form, the frequency divider 18 has the division ratio 1/30, the frequency divider 19 has the division ratio 1/600, and the clock pulse generator 17 develops the reference clock pulses of a period 1 msec. The pulsewidth of the output signal derived from the frequency divider 18 is as follows: 
     
         0.0167×30=0.501 (sec) 
    
     The pulsewidth of the output signal derived from the frequency divider 19 is as follows: 
     
         0.001×600=0.6 (sec.) 
    
     The synchronizing signal is not necessarily limited to the vertical synchronizing signal. Other television signals such as the horizontal synchronizing signal, color subcarrier signal and sound carrier signal can be used to conduct the above-mentioned operation. 
     In the embodiment of FIG. 2, there is a possibility that the signal determination circuit detects the false signals as the true television signals if the false signals have a frequency higher than that of the synchronizing signals. FIG. 3 shows another embodiment of the television signal determination circuit 12, which minimizes the above-mentioned erroneous operation. Like elements corresponding to those of FIG. 2 are indicated by like numerals. 
     The television signal determination circuit of FIG. 3 comprises a frequency divider 25, mono-stable multivibrators 26 and 29, an R-S flip-flop 27, and an AND gate 28 in addition to the elements of the circuit of FIG. 2. The division ratio of the ferquency divider 25 is selected at 1/n-x, which is slightly larger than that of the frequency divider 19. 
     Operation of the television signal determination circuit of FIG. 3 will be described with reference to FIG. 4. 
     When the synchronizing signal is applied to the input terminal 13 at a time t 0 , the flip-flop 14 is set to develop the output &#34;H&#34; from the Q output terminal. The AND gates 15 and 16 are made conductive. The synchronizing signal is applied to the frequency divider 18 through the AND gate 15, and the reference clock pulses derived from the clock pulse generator 17 are applied to the frequency dividers 19 and 25 through the AND gate 16. Accordingly, the frequency dividers 18, 19 and 25 initiate their count operations. 
     When the frequency divider 25 counts the reference clock pulses by the (n-x) number at a time t 2  (=T 2  (n-x)), the frequency divider 25 develops the output signal  a  as shown in FIG. 4, which is applied to the mono-stable multivibrator 26. Although the output signal has the pulsewidth of T 2  (n-x), the pulsewidth is shortened since the frequency divider 25 is reset at a time t 3 . The mono-stable multivibrator 26 is activated at the leading edge of the output signal of the frequency divider 25, and develops an output signal  b  of a predetermined pulsewidth as shown in FIG. 4. The thus developed output signal  b  of the multivibrator 26 is applied to the set input terminal S of the flip-flop 27. Accordingly, the Q output  c  of the flip-flop 27 takes the logic &#34;H&#34; at the time t 2  as shown in FIG. 4. 
     The reference clock pulses are also applied to the frequency divider 19, which develops an output signal  d  at a time t 4  after the frequency divider 19 counts the reference clock pulses by the n number as shown by broken lines in FIG. 4. Upon development of the output signal  d  from the frequency divider 19, the mono-stable multivibrator 23 develops an output signal  e  of a predetermined pulsewidth as shown by broken lines in FIG. 4. The output signal  e  of the multivibrator 23 is applied to the reset input terminals R of the flip-flops 14 and 27, and the frequency dividers 18, 19 and 25 through the OR gate 22. However, since the frequency divider 19 is previously reset at a time t 3 , the frequency divider 19 does not develop the above-mentioned output signal  d . The above mentioned operation will be described in more detail. When the true television vertical synchronizing signals are applied to the input terminal 13, the frequency divider 18 develops an output signal  f  at a time t 3  (=T 1  m) as shown in FIG. 4. The output signal  f  of the frequency divider 18 is applied to the mono-stable multivibrator 29 to activate it. The output signal of the mono-stable multivibrator 29 is applied to the mono-stable multivibrator 20 through the AND gate 28. That is, the mono-stable multivibrator 20 is activated at the time t 3  to develop an output signal  g  as shown in FIG. 4. 
     The thus developed output signal  g  is applied to the reset input terminals R of the frequency dividers 18, 19 and 25, and the R-S flip-flops 14 and 27. That is, the flip-flops 14 and 27, and the frequency dividers 18, 19 and 25 are instantaneously reset at the time t 3 . Consequently, when the true television signals are applied to the input terminal 13, the memory command is developed from the output terminal 21 at the time t 3 . 
     In case where the signals applied to the input terminal 13 have less number than that of the true vertical synchronizing signal, the frequency divider 19 develops the output signal  d  at the time t 4  before the output signal is developed from the frequency divider 18. Therefore, the search re-start signal is developed from the output terminal 24 at the time t 4 . Contrarily, when the signals applied to the input terminal 13 have a frequency higher than that of the normal vertical synchronizing signals, the frequency divider 18 develops an output signal  f  shown by broken lines in FIG. 4 at a time t 1  before the frequency divicer 25 develops the output signal  a . In response to the output signal  f  of the frequency divider 18, the multivibrator 29 is activated to develop a pulse signal having a predetermined pulsewidth. At this moment, the flip-flop 27 is in the reset state and, therefore, the pulse signal developed from the multivibrator 29 is not applied to the multivibrator 20. Under these conditions, the frequency divider 19 continues its count operation to develop the output signal  d  and the output signal  e  at the time t 4 . 
     In summary, the television signal determination circuit of FIG. 3 mainly comprises the frequency divider 18 which receives the synchronizing signals and develops a first count output when it counts the synchronizing signals by the number m. The circuit further includes the frequency dividers 25 and 19 which receive the reference clock pulses derived from the clock pulse generator 17 and develop second and third count outputs when they count the reference clock pulses to two different predetermined numbers, respectively. The R-S flip-flop 27 is controlled by the second and third count outputs to develop a delayed pulse of a predetermined pulse width. And the circuit determines whether the first count output is developed within a period of time during which the delayed pulse is developed from the R-S flip-flop 27. When the affirmative answer is given, a first detection output is developed from the output terminal 21. Contrarily, when the affirmative answer is not given, a second detection output is developed from the output terminal 24. The count operation of the frequency dividers 18, 19 and 25 is reset by either one of the first and second detection outputs. 
     However, in the circuit of FIG. 3, there is a possibility that an output pulse is erroneously developed from the output terminal 21 when, for example, the received signals have a frequency about three times that of the normal vertical synchronizing signal. This is because the frequency divider 18 develops the count output when the Q output of the R-S flip-flop 27 takes the logic &#34;H&#34;. 
     FIG. 5 shows still another embodiment of the television signal determination circuit 12, which eleminates the above-mentioned erroneous operation. Like elements corresponding to those of FIG. 3 are indicated by like numerals. 
     The television signal determination circuit of FIG. 5 comprises an AND gate 30 and an OR gate 31 in addition to the elements of the circuit of FIG. 3. 
     Operation of the television signal determination circuit of FIG. 5 will be described with reference to FIG. 6. 
     When the true television vertical synchronizing signals are applied to the input terminal 13, the output signal  g  is developed at the output terminal 21 as in the case of the circuit of FIG. 3. When the received signal is less number than that of the true vertical synchronizing signal, the output signal  e  is developed at the output terminal 24 as in the case of the circuit of FIG. 3. 
     When a signal having a frequency higher than that of the normal vertical synchronizing signal is applied to the input terminal 13, an output signal is developed from the frequency divider 18 at, for example, a time t 1 . Therefore, the mono-stable multivibrator 29 develops an output signal  h  as shown by chain lines in FIG. 6. At this moment, the Q output of the R-S flip-flop 27 is logic &#34;H&#34; and, therefore, the AND gate 30 is ON. Accordingly, the output signal  h  of the multivibrator 29 is applied to the mono-stable multivibrator 23 through the AND gate 30 and the OR gate 31 to activate the multivibrator 23. The multivibrator 23 develops an output signal  e  as shown by chain lines in FIG. 6. The thus developed signal  e  is applied to the frequency dividers 18, 19 and 25, and to the R-S flip-flops 14 and 27 to reset them. 
     In summary, in the circuit of FIG. 5, when the output pulse is developed from the frequency divider 18 at a time where the Q output of the R-S flip-flop is logic &#34;H&#34;, the search re-start signal is developed from the output terminal 24 and the circuit is reset. The synchronizing signal is not necessarily limited to the vertical synchronizing signal. Other television signals such as the horizontal synchronizing signal, color subcarrier signal and sound carrier signal can be used to conduct the abovementioned operation. 
     In the foregoing embodiments, the circuit will erroneously count two when the vertical synchronizing signal applied to the determination circuit has a sag as shown in FIG. 9  a . FIG. 7 shows an example of a synchronizing signal waveform shaping circuit for shaping the synchronizing pulses to preclude the above-mentioned erroneous operation. 
     The waveform shaping circuit of FIG. 7 mainly comprises a synchronizing signal amplifier 130, a one-shot pulse generator 140 and a noise detection circuit 150. The synchronizing signal amplifier 130 includes a transistor Q 1 , resistors R 1 , R 2  and R 3 , and capacitors C 1  and C 2 . The one-shot pulse generator 140 includes OR gates OR 1  and OR 2 , resistors R 4  and R 5 , and a capacitor C 3 . The noise detection circuit 150 includes a transistor Q 2 , resistors R 6  and R 7 , an OR gate OR 3 , and an inverter IN 1 . 
     Operation of the waveform shaping circuit of FIG. 7 will be described with reference to FIGS. 8, 9 and 10. 
     When a vertical synchronizing signal  a  as shown in FIG. 8 is applied to the base electrode of the transistor Q 1  of the synchronizing signal amplifier 130 from the start/stop circuit 9, the synchronizing signal is amplified and developed through the collector electrode of the transistor Q 1 , the output waveform being shown as  b  in FIG. 8. The thus developed output signal  b  of the synchronizing signal amplifer 130 is applied to the one-shot pulse generator 140, which shapes the synchronizing signal to have a pulsewidth of about 4 msec as shown in FIG. 8  b . The thus shaped synchronizing signal  c  is applied to the input terminal 13 of the television signal determination circuit 12. 
     On the other hand, when a synchronizing signal  a  having a sag as shown in FIG. 9 is applied to the synchronizing signal amplifier 130, the transistor Q 1  develops two pulses  b  for one synchronizing signal as shown in FIG. 9. The thus developed pulses  b  are applied to the one-shot pulse generator 140, which develops one pulse  c  for each two pulses  b as shown in FIG. 9. Accordingly, the frequency divider 18 (see FIGS. 2, 3 and 5) receivers one pulse for each one cycle of the synchronizing signal. 
     When a noise  a  as shown in FIG. 10 is applied from the start/stop circuit 9, the transistor Q 2  is ON and develops an pulse output  d  as shown in FIG. 10 due to the positive components of the noise  a . The transistor Q 2  is in the cut-off state as long as the normal synchronizing signal is applied from the start/stop circuit 9. The output pulses  c  and  d are applied to the OR gate OR 3  and, therefore, the inverter IN 1  develops a pulse signal  e  as shown in FIG. 10. The thus developed pulse signal  e  is fed back to the start/stop circuit 9 as the search re-start command. 
     In case where the synchronizing signal  a  having a sag as shown in FIG. 9 is applied from the start/stop circuit 9, the transistor Q 2  develops a pulse  d  as shown in FIG. 9 since the synchronizing signal includes the positive component pulse. However, the output  c  of the one-shot pulse generator 140 takes the positive level while the pulse  d  is developed from the transistor Q 2  and, therefore, the search re-start command is not developed. 
     The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.