Abstract:
The present invention is related to microelectronic technologies, and discloses specifically a method of making a dynamic random access memory (DRAM) array. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    The present application is a divisional application of U.S. patent application Ser. No. 13/255,503, filed Sep. 8, 2011, entitled “A Dynamic Random Access Memory Array and Method of Making,” which is incorporated herein by reference in its entirety. 
     
    
     FIELD 
       [0002]    The present invention belongs to the field of microelectronic technologies, and is related to the structures and fabrication methods of semiconductor memories, and more particularly to a method of making a dynamic random access memory (DRAM) array. 
       BACKGROUND 
       [0003]    Random Access Memory (RAM) is a kind of semiconductor memory that randomly reads out or writes in data at a high speed (The speed for read operations can be different from that for write operations). The advantages of RAM include high speed memory accesses and ease of read/write operations. The disadvantages include short data retention time and loss of data after power is turned off. Thus, RAM is mainly used as main memories for computers and other systems that require high-speed memory accesses. Based on the methods of operation, RAM is separated into Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). 
         [0004]    A storage unit of DRAM is typically comprised of an array device made of a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor coupled to the MOSFET. The MOSFET is used to charge and discharge the capacitor, and the amount of charge stored on the capacitor, i.e., the level of a voltage across the capacitor, is used to represent a “1” or “0.” DRAM has relatively high integration, low energy consumption, fast read/write speed, and widespread usage. On the other hand, it has obvious shortcomings. In order to avoid gradual loss of the information stored in the storage units through capacitor leakage, the information is rewritten into the storage units every 2-4 microseconds (refresh). Without these refresh operations, the information stored will be lost. The information will also be lost when power is turned off. 
         [0005]    With the continuing miniaturization and high-speed development of DRAM technologies and products, DRAM storage units are gradually shrinking and the corresponding technologies are becoming more and more challenging. For DRAM array devices, not only the size and area need to shrink, large on-state current and small leakage are also required. Since ordinary two-dimensional devices can no longer satisfy such requirements, three-dimensional devices such as recessed channel array transistors (RCAT) gradually find their use in advanced DRAM technologies and products. As DRAM technologies move into the sub-30 nm sector, in order to continually meet the demands of high speed and high information integrity, there is a need to use new array device structures to replace RCAT and related improvement device structures. 
       SUMMARY 
       [0006]    An objective of the present invention is to provide a new DRAM array and methods of making. The DRAM array can satisfy the requirements of large on-state current and small leakage current, and the requirements of high-speed memory accesses and high information integrity, for DRAM devices. The DRAM array according to the present invention utilizes vertical MOS field-effect-transistors as DRAM array devices, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. The vertical MOS field-effect-transistor array devices include double gate structures using a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The buried metal silicide layer is a contiguous layer in a horizontal direction and is disposed in a semiconductor substrate. The semiconductor substrate can be single-crystal silicon, polysilicon or silicon-on-oxide (SIO). The metal silicide can be titanium silicide, cobalt silicide, nickel silicide, platinum silicide, or a combination of two or more thereof. 
         [0007]    Furthermore, the present invention also provides a method of making a DRAM array. The method includes the following:
       providing a semiconductor substrate doped with a first dopant type;   forming shallow trench isolation structures for the devices;   implanting ions to form doped regions of a second dopant type;   forming a first insulating dielectric layer;   etching the first insulating dielectric layer and the substrate to form opening structures;   forming an etch mask layer;   anisotropically etching the etch mask layer to expose areas of silicon for forming metal silicides;   implanting ions to form doped regions of a third dopant type;   depositing a first metal layer followed by annealing to cause the metal layer to react with the exposed areas of silicon to form metal silicide;   removing remaining metal;   forming a second insulating dielectric layer;   dry etching the second insulating dielectric layer and the remaining etch mask layer, thereby keeping only parts of the second insulating dielectric layer and the etch mask layer near bottoms of the openings;   forming a gate insulator layer;   depositing a second metal layer and performing anisotropic dry etching on the second metal layer to form metal gate electrodes;   depositing a third insulating dielectric layer, and planarizing a surface of the substrate;   removing a remaining portion of the first insulating dielectric layer to expose doped regions of a second dopant type; and   coupling capacitors to the respective doped regions of the second dopant type.       
 
         [0025]    Preferably, the semiconductor substrate is single crystal silicon, polysilicon or SOI. The first insulating dielectric layer and the second insulating dielectric layer are deposited SiO 2  or Si 3 N 4  film, or a multilayer structure formed using SiO 2  or Si 3 N 4  and polysilicon films. The etch mask layer is comprised of SiO2, Si 3 N 4 , or a combination thereof. 
         [0026]    Preferably, the first dopant type is lightly-doped P-type, the second dopant type and the third dopant type are both heavily doped N-type. Or, the first dopant type is lightly doped N-type, the second dopant type and the third dopant type are both heavily doped P-type. The doped region of the first dopant type and the doped regions of the second dopant type form P-N junction structures, and doped region of the first dopant type and the doped regions of the third dopant type form P-N junction structures. 
         [0027]    Preferably, the first metal is titanium, cobalt, nickel, platinum or a combination two or more thereof. The metal silicides expand in different directions while being formed, connecting with each other in a horizontal direction to form a contiguous buried metal silicide layer. The buried metal silicide layer is disposed within the doped regions of the third dopant type and is used as a bit line for the DRAM array. 
         [0028]    Preferably, the gate insulator layer is SiO 2 , HfO 2 , HfSiO, HfSiON, SiON, Al 2 O 3  or a combination of two or more thereof. The metal gate electrodes are used to control the DRAM array devices and as buried word lines for the DRAM array. The buried word lines are perpendicular to the buried bit lines. 
         [0029]    As an advantage of the present invention, the DRAM array provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]      FIGS. 1   b ,  2   b ,  3   b ,  4   b , and  5  to  12  are cross-sectional diagrams of processes for forming N-type vertical MOS field-effect-transistor DRAM array devices provided by embodiments of the present invention. 
           [0031]      FIG. 1   a  is a plan view of illustrated structure in  FIG. 1   a.    
           [0032]      FIG. 1   c  is a cross-sectional diagram taken along line “a-b” in  FIG. 1   a.    
           [0033]      FIG. 2   a  is a plan view of illustrated structure in  FIG. 2   b.    
           [0034]      FIG. 3   a  is a plan view of illustrated structure in  FIG. 3   b.    
           [0035]      FIG. 4   a  is a plan view of illustrated structure in  FIG. 4   b.    
           [0036]      FIG. 13  is a cross-sectional diagram of P-type vertical MOS field-effect-transistor DRAM array devices provided by the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0037]    Following is detailed description of embodiments of the present invention with reference to the drawings. In the drawings, for ease of explanation, the thickness of layers and regions are enlarged or minimized, so the sizes shown in the drawings do not represent actual sizes or their proportions. Although the drawings do not accurately reflect the actual device sizes, they still represent relative positions of regions and structures, especially above/below and neighboring relationships of the structures. 
         [0038]    The drawings illustrate preferred embodiments of the present invention, but the illustrated embodiments are not limited by the specific shapes of the regions illustrated. Instead, the embodiments include different shapes resulted, for example, from variations in actual fabrication processes. For example, surface profiles obtained from etching usually have curving or rounding characteristics, but are instead represented by rectangular shapes. Such illustrations in the drawings are not to limit the scope of the invention. Also, in the following description, the terms “substrate” can be understood as including a semiconductor wafer in the process of fabrication, which may include other thin films formed thereon. 
       Example 1 
     N-Type Vertical MOS Field-Effect-Transistor DRAM Array Devices 
       [0039]      FIG. 1   a  is a plan view of a resulting structure of a semiconductor substrate. A P-type doped semiconductor substrate is provided and shallow trench isolation regions are formed thereon. Illustrated regions  201  are shallow trench isolation (STI) regions, and regions  202  are silicon active regions. STI regions and silicon active regions form alternating stripe structures.  FIG. 1   b  is a cross-sectional diagram taken along dotted line “c-d” in  FIG. 1   a , with dotted line  101  representing a depth of the STI regions.  FIG. 1   c  is a cross-sectional diagram taken along dotted line “a-b” in  FIG. 1   a.    
         [0040]    Subsequently, N-type dopants are implanted, forming first highly-doped N-type regions near a surface of the silicon substrate and P-N junctions in the P-type doped silicon substrate. Then, a thin film  203  is deposited on the silicon substrate. Thin film  203  can be SiO 2 , Si 3 N 4  or a multilayer structure formed using SiO 2  and/or Si 3 N 4  and polysilicon. The resulting substrate structure is illustrated by the plan view in  FIG. 2   a .  FIG. 2   b  is a cross-sectional diagram taken along dotted line “c-d” in  FIG. 2   a . Dotted line  102  in  FIG. 2   b  represents a depth of the P-N junction. 
         [0041]    Subsequently, a photoresist layer is formed, and anisotropic etching is performed on the photoresist layer, the thin film  203  and the semiconductor substrate to form openings. The photoresist layer is then removed, resulting in the device structure illustrated by the plan view in  FIG. 3   a .  FIG. 3   b  is a cross-sectional diagram taken along dotted line “c-d” in  FIG. 3   a.    
         [0042]    Subsequently, a thin film  204  is formed by deposition, and anisotropic etching is performed on the thin film  204  to expose areas of silicon at the bottoms of the openings for forming silicide materials, resulting in the device structure illustrated by the plan view in  FIG. 4   a .  FIG. 4   b  is a cross-sectional diagram taken along dotted line “c-d” in  FIG. 4   a . Thin film  204  can be an insulating material made of SiO 2 , Si 3 N 4  or a combination thereof. 
         [0043]    In the following fabrication processes, only cross-sectional diagrams along line “c-d” in  FIG. 1  are shown, while plan views of the device structures are not shown. 
         [0044]    As shown in  FIG. 5 , N-type ions are implanted into the openings, forming second highly-doped N-type region in the substrate and additional P-N junctions in the p-type doped substrate. Dotted lines  103  and  104  represent depths of the newly formed P-N junctions. An annealing step is generally performed after the N-type dopant implant to activate the N-type dopant ions. While being activated, the implanted N-type dopant ions would diffuse in all directions and form a contiguous highly-doped N-type region by joining each other in a horizontal direction. Note that the implanting of the N-type dopant ions and the subsequent annealing to activate the ions can be performed before thin film  204  is formed. 
         [0045]    As shown in  FIG. 6 , a metal layer  205  is formed by deposition. The metal layer  205  can be titanium, cobalt, nickel, platinum or a combination of two or more thereof. 
         [0046]    Afterwards, an annealing technology is used to cause the metal layer  205  to react with only the exposed areas of the silicon substrate, thereby forming a buried metal silicide layer  206  in the second highly-doped N-type region. The unreacted metal is subsequently removed, as shown in  FIG. 7 . The buried metal silicide layer  206  is used as a buried bit line for the DRAM array to connect multiple consecutive vertical MOS field-effect-transistor array devices. If metal silicides formed at the respective openings are sufficiently thick or the width of the silicon between the openings is sufficiently small, the metal silicides can form a contiguous metal silicide layer in the horizontal direction. The temperature for the annealing technology can be controlled at 300° C. to 900° C. During annealing, the metal react with silicon to form metal silicides but does not react or react weakly with insulator layers. Also, in order to form the contiguous metal silicide layer, the exposed silicon at the bottoms of the openings, as shown in  FIG. 4   b , can be isotropically etched, thereby reducing the width of the exposed silicon between the openings. 
         [0047]    Afterwards, a layer of insulating dielectric thin film  207  is deposited. The insulating dielectric thin film  207  is preferably SiO 2 . The thin film  207  and thin film  204  are dry etched to form the structure shown in  FIG. 8 . Note that the original thin film  203  is generally thinned during the dry etch process. 
         [0048]    Afterwards, a gate insulator layer  208  is formed, as shown in  FIG. 9 . The gate insulator layer  208  can be thermally grown SiO 2  or a SiO 2  or high-k dielectric layer formed by deposition. Note that if the gate insulator layer  208  is a deposited dielectric layer, the dielectric layer would cover all exposed surfaces of the substrate. 
         [0049]    Afterwards, a metal layer  209  is formed by deposition. The metal layer  209  can be TiN, Ti, Ta, TaN or a combination of two or more thereof. Anisotropic dry etch is performed on the metal layer  209  to form the metal gate electrode structures shown in  FIG. 10 . As shown in  FIG. 10 , each vertical field-effect-transistor is controlled by two metal gate electrodes, and the metal gate electrodes form at the same time buried word lines for the DRAM array. These buried word lines are perpendicular to the buried bit line formed by the metal silicide layer  206 . 
         [0050]    Subsequently, a dielectric layer  210  filling the openings is formed. The dielectric layer  210  can be a insulating dielectric layer containing SiO 2 . Then chemical mechanical polishing or etching is performed to planarize the dielectric layer  210 , forming the structure shown in  FIG. 11 . 
         [0051]    Lastly, thin film  203  is removed, as shown in  FIG. 12 . Thus, the vertical MOS field-effect-transistor array devices and buried word lines and bit lines connecting multiple array devices are formed. 
         [0052]    After subsequent processes to form the capacitors (not shown) coupled to the heavily doped N-type regions in the vertical MOS field-effect-transistor array devices, the DRAM array is formed. 
       Example 2 
     P-Type Vertical MOS Field-Effect-Transistor DRAM Array Devices 
       [0053]      FIG. 13  illustrates a structure of P-type vertical MOS field-effect-transistor array devices and buried word lines and a buried bit line connecting multiple array devices. The dopant types for the substrate and vertical field-effect-transistors in this example are opposite to those in Example 1, i.e., the substrate is N-type, while the vertical field-effect-transistors are P-type. As shown in  FIG. 13 , layer  304  is SiO 2 , Si 3 N 4 , or an insulator material of a combination thereof. Layer  306  in  FIG. 13  is a metal silicide layer, which is used as buried lines connecting multiple consecutive vertical MOS field-effect-transistor array devices. Layer  307  in  FIG. 13  is a SiO 2  dielectric layer. Reference numeral  308  represents gate insulator layers, which can be thermally grown SiO 2  or a SiO 2  or high-k dielectric layer formed by deposition. Reference numeral  309  represents metal gate electrodes formed of TiN, Ti, Ta, TaN or a combination two or more thereof. Reference numeral  310  represents a dielectric layer of SiO 2 . Dotted lines  401  represent a depth of a bottom of shallow trench isolation structure regions. Dotted lines  402 ,  403 , and  404  represent depth of formed P-N junctions. 
         [0054]    Detailed discussions regarding the fabrication processes for forming the P-type vertical MOS field-effect-transistor DRAM array devices is omitted here because they are similar to those for forming the N-type vertical MOS field-effect-transistor DRAM array devices. After forming the capacitors coupled to the heavily doped P-type regions in the vertical MOS field-effect-transistor array devices shown in  FIG. 13 , a DRAM array could be formed (illustration omitted). Compared to the N-type vertical MOS field-effect-transistors, P-type vertical MOS field-effect-transistors have smaller transient bipolar gain. By design optimization, this gain can be smaller than 1. Thus, the P-type vertical MOS field-effect-transistors are more advantageous at avoiding the problem of floating body effect that can be associated with vertical DRAM array devices lacking contact with body silicon. 
         [0055]    As discussed above, without departing from the spirit and scope of the present invention, various largely different embodiments can be formed. It is to be understood that, except what is defined by the appended claims, the present invention is not limited by the specific embodiments described in the specification.