Abstract:
It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar.

Description:
RELATED APPLICATIONS 
     Pursuant to 35 U.S.C. §119(e), this application claims the benefit of the filing date of Provisional U.S. Patent Application Ser. No. 61/217,896 filed on Jun. 4, 2009. This application also claims priority under 35 U.S.C. §119(a) to JP2009-109126 filed on Apr. 28, 2009. The entire contents of these applications are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and a production method therefor, and more particularly to a structure and a production method for an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor comprising a pillar-shaped semiconductor layer having a sidewall serving as a channel region, and a gate electrode formed to surround the channel region. 
     2. Background Art 
     With a view to achieving higher integration and higher performance of a semiconductor device, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see, for example, Patent Document 1: JP 2-188966A). In the SGT, a drain, a gate and a source are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor. 
       FIGS. 46(   a ) and  46 ( b ) show an SGT disclosed in the Patent Document 1, wherein  FIG. 46(   a ) and  FIG. 46(   b ) are, respectively, a bird&#39;s-eye view and a sectional view of the SGT. With reference to  FIGS. 46(   a ) and  46 ( b ), a structure of the SGT will be briefly described below. A pillar-shaped silicon layer  1601  is formed on a silicon substrate. A gate dielectric film  1602  is formed to surround the pillar-shaped silicon layer  1601 , and a gate electrode  1603  is formed to surround the gate dielectric film  1602 . A lower diffusion layer  1604  and an upper diffusion layer  1605  are formed underneath and in an upper portion of the pillar-shaped silicon layer  1601 , respectively. The upper diffusion layer  1605  is connected to an interconnection layer  1606  via a contact. 
       FIGS. 47(   a ) to  47 ( c ) show a CMOS inverter using an SGT, wherein  FIG. 47(   a ),  FIG. 47(   b ) and  FIG. 47(   c ) are, respectively, an equivalent circuit of the CMOS inverter, a top plan view of the CMOS inverter, and a sectional view taken along the line B-B′ in  FIG. 47(   b ). Referring to  FIGS. 47(   b ) and  47 ( c ), an N-well  2702  and a P-well  1703  are formed in an upper region of a Si substrate  1701 . A pillar-shaped silicon layer  1705  constituting a PMOS transistor (PMOS pillar-shaped silicon layer  1705 ) and a pillar-shaped silicon layer  1706  constituting an NMOS transistor (NMOS pillar-shaped silicon layer  1706 ) are formed on a surface of the Si substrate, specifically on respective ones of the N-well region and the P-well region, and a gate  1708  is formed to surround the pillar-shaped silicon layers. Each of a P +  drain diffusion layer  1710  formed underneath the PMOS pillar-shaped silicon layer, and a N +  drain diffusion layer  1712  formed underneath the NMOS pillar-shaped silicon layer, is connected to an output terminal Vout  17 . A source diffusion layer  1709  formed in an upper portion of the PMOS pillar-shaped silicon layer is connected to a power supply potential Vcc  17 , and a source diffusion layer  1711  formed in an upper portion of the NMOS pillar-shaped silicon layer is connected to a ground potential GND  17 . Further, the gate  1708  common to the PMOS and NMOS pillar-shaped silicon layers is connected to an input terminal Vin  17 . In this manner, the CMOS inverter is formed. 
     As a prerequisite to enhancing a channel controllability by a gate in an SGT to sufficiently suppress short-channel effects, it is necessary to form a pillar-shaped silicon layer to have a sufficiently-small size relative to a gate length. A size of a pillar-shaped silicon layer can be reduced in a relatively easy manner, for example, by causing dimensional shrinking during dry etching for forming the pillar-shaped silicon layer, or by performing sacrificial oxidation after formation of the pillar-shaped silicon layer. Thus, in many cases, a pillar-shaped silicon layer is formed to have a size less than a minimum fabrication size F, in order to sufficiently suppress the short-channel effects in an SGT.  FIG. 48  shows a structure of an SGT which comprises a pillar-shaped silicon layer  1611  having a size less than the minimum fabrication size F. In this SGT structure, a gate length is sufficiently large relative to the size of the pillar-shaped silicon layer  1611 , so that the short-channel effects can be suppressed. Further, a contact  1616  to be formed on a top of the pillar-shaped silicon layer is formed in a similar size to the minimum fabrication size F, so that it will become structurally larger than the pillar-shaped silicon layer  1611 . 
     However, the SGT structure illustrated in  FIG. 48  has the following problems. Firstly, in terms of a need for forming a silicide layer on each of upper and lower sides of the pillar-shaped silicon layer to reduce a parasitic resistance in an SGT, a reduction in size of a pillar-shaped silicon layer causes difficulty in forming an adequate silicide on top of the pillar-shaped silicon layer due to the so-called “narrow width effect” on the silicide layer. Moreover, even if an adequate silicide can be formed on top of the pillar-shaped silicon layer, an interface area between the silicide and an upper diffusion layer  1615  becomes smaller along with a reduction in diameter of the pillar-shaped silicon layer, so that an interface resistance between the silicide and the upper diffusion layer is increased to cause deterioration in transistor characteristics. 
     Secondly, in view of a reduction in the number of steps in an SGT production process, it is desirable to simultaneously form two contacts on respective ones of the upper diffusion layer  1615  and a lower diffusion layer  1614 . In this case, the contact  1616  to be formed on top of the pillar-shaped silicon layer has to undergo overetching to an extent corresponding to a height dimension of the pillar-shaped silicon layer or more, as compared with the contact to be formed on the lower diffusion layer  1614 . In the SGT structure illustrated in  FIG. 48 , the contact to be formed on top of the pillar-shaped silicon layer is excessively overetched during etching for the contacts, so that a short-circuiting between the gate and the contact becomes more likely to occur. 
     SUMMARY OF THE INVENTION 
     In view of the above circumstances, it is an object of the present invention to, in a vertical transistor, reduce the narrow width effect on a silicide layer on top of a pillar-shaped silicon layer while reducing an interface resistance between the silicide and an upper diffusion layer, to improve transistor characteristics. It is another object of the present invention to achieve a structure free of the occurrence of a short-circuiting between a contact and a gate. 
     In order to achieve the above objects, according to a first aspect of the present invention, there is provided a MOS transistor which comprises: a pillar-shaped semiconductor layer; one of drain and source regions which is formed underneath the pillar-shaped semiconductor layer to serve as a first drain/source region; a gate electrode formed around a sidewall of the pillar-shaped semiconductor layer through a first dielectric film; an epitaxial semiconductor layer formed on top of an upper surface of the pillar-shaped semiconductor layer; and a remaining one of the drain and source regions which is formed so as to be at least partially in the epitaxial semiconductor layer to serve as a second drain/source region, wherein an area of an upper surface of the second drain/source region is greater than an area of the upper surface of the pillar-shaped semiconductor layer. 
     Preferably, the MOS transistor of the present invention further comprises a silicide layer formed on the upper surface of the second drain/source region. 
     More preferably, an interface area between the silicide layer and the second drain/source region is greater than the area of the upper surface of the pillar-shaped semiconductor layer. 
     Preferably, in the MOS transistor of the present invention, the epitaxial semiconductor layer consists of a silicon (Si) layer or a silicon carbide (SiC) layer formed by epitaxial growth, in cases where it is an n-type epitaxial semiconductor layer, or consists of a silicon (Si) layer or a silicon germanium (SiGe) layer formed by epitaxial growth, in cases where it is a p-type epitaxial semiconductor layer. 
     Preferably, in the MOS transistor of the present invention, when the number of the pillar-shaped semiconductor layers is at least two, the epitaxial semiconductor layers formed on tops of respective upper surfaces of the at least two pillar-shaped semiconductor layers are connected to each other to form a single common drain/source region. 
     Preferably, in the MOS transistor of the present invention, the epitaxial semiconductor layer is formed on top of the gate electrode through a second dielectric film. 
     Preferably, the above MOS transistor further comprises a contact formed on the silicide layer, wherein an area of the contact is less than an area of an upper surface of the silicide layer. 
     Preferably, the above MOS transistor further comprises at least one contact formed on the epitaxial semiconductor layers on tops of the upper surfaces of the at least two pillar-shaped semiconductor layers, wherein the number of the contacts is less than the number of the pillar-shaped semiconductor layers. 
     Preferably, the above MOS transistor further comprises at least one contact formed on the connected epitaxial semiconductor layers, wherein the at least one contact includes a contact formed on the connected epitaxial semiconductor layers at a position corresponding to a position between adjacent two of the at least two pillar-shaped semiconductor layers. 
     Preferably, the above MOS transistor further comprises a plurality of contacts at least one of which is formed on the connected epitaxial semiconductor layers, wherein an area of the at least one contact in cross-section parallel to a principal surface of the substrate is greater than that of each of the remaining contacts. 
     According to a second aspect of the present invention, there is provided a method of producing a semiconductor device having a MOS transistor. The method comprises the steps of: providing a substrate having a plurality of pillar-shaped semiconductor layers formed thereover; forming one of drain and source regions underneath the pillar-shaped semiconductor layers to serve as a first drain/source region; forming a first dielectric film on a surface of the obtained product; forming a conductive film on the first dielectric film; etching back the first dielectric film and the conductive film to form each of the first dielectric film and the conductive film to have a height dimension equal to a gate length along a sidewall of each of the pillar-shaped semiconductor layers; removing a part of the conductive film and the first dielectric film by selective etching to form a gate electrode around the pillar-shaped semiconductor layers, and a gate line extending from the gate electrode; forming an epitaxial layer on top of an upper surface of at least one of the pillar-shaped semiconductor layers by epitaxial growth, in such a manner that an area of an upper surface of the epitaxial layer becomes greater than that an area of the upper surface of the at least one pillar-shaped semiconductor layer; and forming a remaining one of the drain and source regions in the epitaxial layer and each of the pillar-shaped semiconductor layers to serve as a second drain/source region having a same conductive type as that of the first drain/source region formed on the substrate. 
     Preferably, the method of the present invention further comprises the step of forming a silicide layer in a surface of the epitaxial layer. 
     Preferably, in the method of the present invention, the epitaxial semiconductor layer consists of a silicon (Si) layer or a silicon carbide (SiC) layer formed by epitaxial growth, in cases where it is an n-type epitaxial semiconductor layer, or consists of a silicon (Si) layer or a silicon germanium (SiGe) layer formed by epitaxial growth, in cases where it is a p-type epitaxial semiconductor layer. 
     Preferably, in the method of the present invention, when at least two of the pillar-shaped semiconductor layers are arranged adjacent to each other with a given distance or less therebetween to constitute a MOS transistor, conditions for film formation by epitaxial growth are adjusted in such a manner that only the epitaxial layers formed on tops of respective upper surfaces of the at least two of the pillar-shaped semiconductor layers constituting the MOS transistor are self-alignedly connected together to allow a single common drain/source region to be formed therein. 
     Preferably, the method of the present invention further comprises, as a pretreatment for the step of forming an epitaxial layer, the step of forming a second dielectric film for isolating between the gate electrode and the epitaxial semiconductor layer. 
     More preferably, the step of forming a second dielectric film includes the sub-steps of: forming a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, on a surface of the product obtained from the step of removing a part of the conductive film and the first dielectric film; and etching back the silicon nitride film or the laminated film to cover a sidewall of each of the pillar-shaped semiconductor layers, a sidewall of the gate electrode and a sidewall of the gate line by the etched silicon nitride film or laminated film, while allowing the etched silicon nitride film or laminated film to remain on top of the gate electrode, and allowing the first drain/source region and an upper surface of each of the pillar-shaped semiconductor layers to be exposed. 
     Preferably, in the method of the present invention, the step of providing a substrate having a plurality of pillar-shaped semiconductor layers formed thereover, and the step of forming one of drain and source regions underneath the pillar-shaped semiconductor layers to serve as a first drain/source region, comprise the sub-steps of: forming a plurality of pillar-shaped semiconductor layers on a substrate; forming an element isolation region on the substrate; and forming one of drain and source regions on the substrate to serve as a first drain/source region. 
     Preferably, in the method of the present invention, the step of providing a substrate having a plurality of pillar-shaped semiconductor layers formed thereover, and the step of forming one of drain and source regions underneath the pillar-shaped semiconductor layers to serve as a first drain/source region, comprise the sub-steps of: forming a planar semiconductor layer, on a dielectric film on a substrate, and then forming a plurality of pillar-shaped semiconductor layers on the planar semiconductor layer substrate; isolating the planar semiconductor layer on an element-by-element basis; and forming one of drain and source regions in the isolated planar semiconductor layer to serve as a first drain/source region. 
     In the present invention, the term “over a substrate” means a position on the substrate or a position located upwardly of the substrate through a certain layer formed on the substrate. 
     In a vertical transistor, the present invention makes it possible to reduce the narrow width effect on a silicide layer on top of a pillar-shaped silicon layer while reducing an interface resistance between the silicide and an upper diffusion layer, to improve transistor characteristics. The present invention also makes it possible to achieve a structure free of the occurrence of a short-circuiting between a contact and a gate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1(   a ) and  1 ( b ) are, respectively, a top plan view and a sectional view showing a transistor according to a first embodiment of the present invention. 
         FIGS. 2(   a ) and  2 ( b ) are, respectively, a top plan view and a sectional view showing one example of modification of the transistor according to the first embodiment. 
         FIGS. 3(   a ) and  3 ( b ) are, respectively, a top plan view and a sectional view showing another example of modification of the transistor according to the first embodiment. 
         FIGS. 4(   a ) and  4 ( b ) are, respectively, a top plan view and a sectional view showing yet another example of modification of the transistor according to the first embodiment. 
         FIGS. 5(   a ) and  5 ( b ) are, respectively, a top plan view and a sectional view showing still another example of modification of the transistor according to the first embodiment. 
         FIGS. 6(   a ) and  6 ( b ) are process diagrams showing one example of a production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 7(   a ) and  7 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 8(   a ) and  8 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 9(   a ) and  9 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 10(   a ) and  10 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 11(   a ) and  11 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 12(   a ) and  12 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 13(   a ) and  13 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 14(   a ) and  14 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 15(   a ) and  15 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 16(   a ) and  16 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 17(   a ) and  17 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 18(   a ) and  18 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 19(   a ) and  19 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 20(   a ) and  20 ( b ) are process diagrams showing the example of the production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ), in order of process sequence. 
         FIGS. 21(   a ) and  21 ( b ) are, respectively, a top plan view and a sectional view showing a transistor according to a second embodiment of the present invention. 
         FIGS. 22(   a ) and  22 ( b ) are, respectively, a top plan view and a sectional view showing one example of modification of the transistor according to the second embodiment. 
         FIGS. 23(   a ) and  23 ( b ) are, respectively, a top plan view and a sectional view showing a CMOS inverter according to a third embodiment of the present invention. 
         FIGS. 24(   a ) and  24 ( b ) are, respectively, a top plan view and a sectional view showing one example of modification of the CMOS inverter according to the third embodiment. 
         FIGS. 25(   a ) and  25 ( b ) are, respectively, a top plan view and a sectional view showing a transistor formed on an SOI substrate (SOI transistor), according to a fourth embodiment of the present invention. 
         FIGS. 26(   a ) and  26 ( b ) are, respectively, a top plan view and a sectional view showing one example of modification of the SOI transistor according to the fourth embodiment. 
         FIGS. 27(   a ) and  27 ( b ) are process diagrams showing one example of a production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 28(   a ) and  28 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 29(   a ) and  29 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 30(   a ) and  30 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 31(   a ) and  31 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 32(   a ) and  32 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 33(   a ) and  33 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 34(   a ) and  34 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 35(   a ) and  35 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 36(   a ) and  36 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 37(   a ) and  37 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 38(   a ) and  38 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 39(   a ) and  39 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 40(   a ) and  40 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 41(   a ) and  41 ( b ) are process diagrams showing the example of the production method for the SOI transistor illustrated in  FIGS. 26(   a ) and  26 ( b ), in order of process sequence. 
         FIGS. 42(   a ) and  42 ( b ) are, respectively, a top plan view and a sectional view showing an SOI transistor according to a fifth embodiment of the present invention. 
         FIGS. 43(   a ) and  43 ( b ) are, respectively, a top plan view and a sectional view showing a CMOS inverter formed on an SOI substrate (SOI CMOS inverter), according to a sixth embodiment of the present invention. 
         FIGS. 44(   a ) and  44 ( b ) are, respectively, a top plan view and a sectional view showing a transistor according to a seventh embodiment of the present invention. 
         FIGS. 45(   a ) and  45 ( b ) are, respectively, a top plan view and a sectional view showing a transistor according to an eighth embodiment of the present invention. 
         FIGS. 46(   a ) and  46 ( b ) are, respectively, a bird&#39;s-eye view and a sectional view showing a conventional SGT. 
         FIGS. 47(   a ),  47 ( b ) and  47 ( c ) are, respectively, an equivalent circuit diagram, a top plan view and a sectional view showing a conventional SGT-based inverter. 
         FIG. 48  shows a structure of an SGT comprising a pillar-shaped semiconductor layer having a small size. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       FIG. 1(   a ) is a top plan view showing a transistor according to a first embodiment of the present invention, and  FIG. 1(   b ) is a sectional view taken along the line A-A′ in  FIG. 1(   a ). With reference to  FIGS. 1(   a ) and  1 ( b ), a structure of the transistor according to the first embodiment will be described below. 
     A silicon substrate  101  is isolated on an element-by-element basis by an element isolation region  102 , and two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  105   a ,  105   b  are formed on the silicon substrate. A gate dielectric film (first dielectric film)  107  and a gate electrode ( 108   a ,  108   b ) are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the first embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a metal film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film), and a polysilicon film may be used as the gate electrode. A lower N +  diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions)  103  is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers), and a lower silicide layer  111   a  is formed on a surface of the lower N +  diffusion layer (first drain/source diffusion region)  103 , to reduce a parasitic resistance. An upper N +  diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions) ( 109   a ,  109   b ) is formed on top of each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers), in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the pillar-shaped silicon layer. In the first embodiment, the upper N +  diffusion layer (second drain/source diffusion region) ( 109   a ,  109   b ) having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper N +  diffusion layer (second drain/source diffusion region) ( 109   a ,  109   b ) may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode ( 108   a ,  108   b ) by a second dielectric film  112 , such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. An upper silicide layer ( 111   b ,  111   c ) is formed on the upper diffusion layer (second drain/source diffusion region) ( 109   a ,  109   b ). The upper silicide layer is formed on the epitaxial silicon layer (semiconductor epitaxial layer) having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the upper N +  diffusion layer can be set largely, so that an interface resistance between the upper silicide layer and the upper N +  diffusion layer can be reduced. Further, the upper silicide layer ( 111   b ,  111   c ) may be formed on an upper surface of the upper N +  diffusion layer (second drain/source diffusion region) to have a diameter greater than that of a contact ( 115 ,  116 ) to be formed on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The contact ( 115 ,  116 ) formed on the upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to one of drain and source terminals through an interconnection layer  120 . A contact  118  formed on a lower side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to a remaining one of the drain and source terminals through an interconnection layer  122 , and a contact  117  formed on a gate line  108  extending from the gate electrode is connected to a gate terminal through an interconnection layer  121 . 
     As shown in  FIGS. 2(   a ) and  2 ( b ), in cases where a distance between two adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers)  205   a ,  205   b  is less than a given value, a thickness of a film to be epitaxially grown can be adjusted in such a manner that the silicon epitaxial layers (semiconductor epitaxial layers on respective ones of the adjacent pillar-shaped semiconductor layers are self-alignedly connected together. In this case, an interface area between an upper silicide layer  211   b  on an upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) and an integral set of upper N +  diffusion layers (second drain/source diffusion regions)  209   a ,  209   b  becomes larger, so that an interface resistance between the an upper silicide layer and the integral set of upper N +  diffusion layers (second drain/source diffusion regions) can be further reduced. In addition, an area of the upper silicide layer on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) becomes larger, so that the narrow width effect on the upper silicide layer can be significantly reduced to facilitate adequate formation of the upper silicide layer. 
     Further, as shown in  FIGS. 3(   a ) and  3 ( b ), as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers. 
     Further, as shown in  FIGS. 4(   a ) and  4 ( b ), a contact  415  may be formed on an integral set of upper N +  diffusion layers (second drain/source diffusion regions)  409   a ,  409   b  at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). In this case, an axis of the contact  415  may be located to intersect with a line segment connecting respective axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) or may be located in a region between the axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This arrangement makes it possible to largely set a space between an interconnection line  420  and other interconnection line ( 421 ,  422 ) so as to facilitate interconnection layout. 
     Further, as shown in  FIGS. 5(   a ) and  5 ( b ), a contact  515  having an area greater than that of other contact ( 517 ,  518 ) in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers. This makes it possible to reduce a resistance of a contact, and stably form a contact. 
     With reference to  FIGS. 6(   a ) to  20 ( b ), one example of a production method for the transistor illustrated in  FIGS. 2(   a ) and  2 ( b ) will be described below. In  FIGS. 6(   a ) and  6 ( b ) to  FIGS. 20(   a ) and  20 ( b ), the figure suffixed with (a) is a top plan view, and the figure suffixed with (b) is a sectional view taken along the line A-A′ in the figure suffixed with (a). 
     As shown in  FIGS. 6(   a ) and  6 ( b ), two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  205   a ,  205   b  each having a hard mask layer  204   a , such as a silicon nitride film, on top thereof, are formed on a substrate  201  by lithography and etching. 
     As shown in  FIGS. 7(   a ) and  7 ( b ), an element isolation  202  is formed in the substrate. The element isolation is formed by etching the substrate to form a trench pattern, filling an oxide film in the trench pattern through chemical vapor deposition (CVD) or silica coating or the like, and removing an excess part of the oxide film on the substrate through dry etching or wet etching. 
     As shown in  FIGS. 8(   a ) and  8 ( b ), after formation of the element isolation  202 , a lower N +  diffusion layer  203  is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers) by ion implantation or the like. In this step, the pillar-shaped silicon layer (pillar-shaped semiconductor layer) ( 205   a ,  205   b ) is kept from impurity implantation by the hard mask layer  204   a  on top of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). 
     As shown in  FIGS. 9(   a ) and  9 ( b ), a gate dielectric film (first dielectric film)  207  and a gate conductive film  208   c  are formed. The gate dielectric film (first dielectric film)  207  is formed of an oxide film, a High-k film or the like. The gate conductive film  208   c  is formed of a polysilicon film, a metal film or the like. 
     As shown in  FIGS. 10(   a ) and  10 ( b ), the gate conductive film  208   c  is flattened by chemical mechanical polishing (CMP) or the like. 
     As shown in  FIGS. 11(   a ) and  11 ( b ), the gate dielectric film (first dielectric film)  207  and the gate conductive film  208   c  are etched back to allow a height dimension of each of the gate dielectric film (first dielectric film)  207  and the gate conductive film  208   c  along a sidewall of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) ( 205   a ,  205   b ) to be set to a desired gate length. 
     As shown in  FIGS. 12(   a ) and  12 ( b ), a nitride film or the like is formed and then etched back to form a sidewall spacer  204   b.    
     As shown in  FIGS. 13(   a ) and  13 ( b ), a gate line pattern is formed using a resist  210  by lithography or the like. 
     As shown in  FIGS. 14(   a ) and  14 ( b ), the gate conductive film  208   c  and the gate dielectric film (first dielectric film)  207  are selectively etched by anisotropic etching or the like, using the resist  210  as a mask, to integrally form a gate electrode ( 208   a ,  208   b ) around the pillar-shaped silicon layer (pillar-shaped semiconductor layer) ( 205   a ,  205   b ) and a gate line  208  extending from the gate electrode ( 208   a ,  208   b ). Subsequently, the resist  210  is removed. 
     As shown in  FIGS. 15(   a ) and  15 ( b ), the hard mask layer  204   a  and the sidewall spacer  204   b  are removed by wet etching or the like. 
     As shown in  FIGS. 16(   a ) and  16 ( b ), a dielectric film, such as a nitride film or a laminated film comprised of a nitride film and an oxide film, is formed, and then etched back to form a second dielectric film  212 . 
     As shown in  FIGS. 17(   a ) and  17 ( b ), silicon or the like is selectively epitaxially grown on top of an upper surface of each of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) and on the lower N +  diffusion layer  203  to form an upper epitaxial silicon layer (semiconductor epitaxial layer)  210   b  and a lower epitaxial silicon layer, in such a manner that epitaxial layers formed on tops of respective upper surfaces of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) arranged adjacent to each other with a given distance or less therebetween are self-alignedly connected together. The upper epitaxial silicon layer (semiconductor epitaxial layer) may be formed to have a diameter greater than that of a contact to be formed on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) in a subsequent step. This makes it possible to provide a structure free of a short-circuiting between the contact and the gate electrode. 
     As shown in  FIGS. 18(   a ) and  18 ( b ), an upper N +  diffusion layer (second drain/source diffusion region) ( 209   a ,  209   b ) is formed in the upper epitaxial silicon layer (semiconductor epitaxial layer)  210   b  and an upper portion of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) ( 205   a ,  205   b ) by ion implantation or the like. Alternatively, a region to be formed as the upper N +  diffusion layer (second drain/source diffusion region) may be a part or an entirety of the upper epitaxial silicon layer (semiconductor epitaxial layer)  210   b.    
     As shown in  FIGS. 19(   a ) and  19 ( b ), a metal, such as Co or Ni, is sputtered, and then a heat treatment is performed to selectively silicide respective upper surfaces of the lower epitaxial silicon layer on the lower N +  diffusion layer (first drain/source diffusion region)  203  and the integral set of upper N +  diffusion layers (second drain/source diffusion regions) to form a lower silicide layer  211   a  and an upper silicide layer  211   b . The upper silicide layer  211   b  is formed to have a size greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer), so that the narrow width effect on the upper silicide layer can be suppressed. Further, the entire surface of the epitaxial silicon layer (semiconductor epitaxial layer) may be silicided. In this case, an interface area between the upper silicide layer  211   b  and the integral set of upper N +  diffusion layers (second drain/source diffusion regions)  209   a ,  209   b  is increased, so that an interface resistance therebetween can be reduced to reduce a source/drain parasitic resistance. 
     As shown in  FIGS. 20(   a ) and  20 ( b ), a silicon oxide film is formed to serve as an interlayer film, and then a contact ( 215  to  218 ) is formed. The epitaxial silicon layer (semiconductor epitaxial layer) is formed to allow the contact ( 215 ,  216 ) on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) to be entirely formed on the upper silicide layer  211   b , as shown in  FIGS. 20(   a ) and  20 ( b ). This makes it possible to provide a structure free of a short-circuiting between the contact and the gate electrode. 
     The first embodiment shows one example where an epitaxial silicon layer (semiconductor epitaxial layer) is formed. Specifically, an epitaxial silicon carbide (SiC) layer may be formed for an NMOS transistor, and an epitaxial silicon germanium (SiGe) layer may be formed for a PMOS transistor. In this case, a stress can be applied to a channel region to enhance carrier mobility. 
     Second Embodiment 
     A second embodiment shows one example where the present invention is applied to a transistor formed by connecting in series two transistors.  FIG. 21(   a ) is a top plan view showing a transistor according to the second embodiment, and  FIG. 21(   b ) is a sectional view taken along the line A-A′ in  FIG. 21(   a ). With reference to  FIGS. 21(   a ) and  21 ( b ), a structure of the transistor according to the second embodiment will be described below. A silicon substrate  601  is isolated on an element-by-element basis by an element isolation  602 . Two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  605   a ,  605   b  constituting a first transistor, and two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  605   c ,  605   d  constituting a second transistor, are formed on the silicon substrate. A gate dielectric film (first dielectric film)  607  and a gate electrode ( 609   a  to  609   d ) are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the second embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a metal film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film), and a polysilicon film may be used as the gate electrode. A lower N +  diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions)  603  is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers), and a lower silicide layer  611   a  is formed on a surface of the lower N +  diffusion layer (first drain/source diffusion region)  603 , to reduce a parasitic resistance. An upper N +  diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions) ( 609   a  to  609   d ) is formed on top of each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers), in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the pillar-shaped silicon layer. In the second embodiment, the upper N +  diffusion layer (second drain/source diffusion region) having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper N +  diffusion layer (second drain/source diffusion region) may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode ( 608   a  to  608   d ) by a second dielectric film  612 , such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. The two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  605   a ,  605   b  constituting the first transistor are arranged adjacent to each other, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed on tops of respective upper surfaces of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) are self-alignedly connected together. The two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  605   c ,  605   d  constituting the second transistor are also arranged adjacent to each other, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed on tops of respective upper surfaces of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) are self-alignedly connected together in the same manner. In contrast, the two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  605   b ,  605   c  each constituting a different transistor are arranged with a distance greater than a given value therebetween, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed thereon are separated from each other. 
     Two upper silicide layers  611   b ,  611   c  are formed, respectively, on the integral set of upper N +  diffusion layers (second drain/source diffusion regions)  609   a ,  609   b  and the integral set of upper N +  diffusion layers (second drain/source diffusion regions)  609   c ,  609   d . Each of the upper silicide layers is formed on the connected epitaxial silicon layers (semiconductor epitaxial layers) each having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the integral set of upper N +  diffusion layers ( 609   a ,  609   b ;  609   c ,  609   d ) can be set largely, so that an interface resistance between the upper silicide layer and the integral set of upper N +  diffusion layers can be reduced. Further, the upper silicide layer ( 611   b ,  611   c ) may be formed in an upper surface of the integral set of the upper N +  diffusion layers (second drain/source diffusion regions) to have a diameter greater than a total diameter of two contacts ( 615   a ,  615   b ;  616   a ,  616   b ) to be formed on an upper side of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The two contacts  615   a ,  615   b  formed on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) constituting the first transistor are connected to one of drain and source terminals through an interconnection layer  620   a , and the two contacts  616   a ,  616   b  formed on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) constituting the second transistor are connected to a remaining one of the drain and source terminals through an interconnection layer  620   b . Further, the first transistor and the second transistor are connected in series through the lower N +  diffusion layer (first drain/source diffusion region)  603 . A contact  617  formed on a gate line  608  extending from the gate electrode is connected to a gate terminal through an interconnection layer  621 . 
     As shown in  FIGS. 22(   a ) and  22 ( b ), as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers. 
     For example, as shown in  FIGS. 22(   a ) and  22 ( b ), a contact ( 715 ,  716 ) may be formed on an integral set of upper diffusion layers (second drain/source diffusion regions)  409   a ,  409   b  at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). In this case, an axis of the contact ( 715 ,  716 ) may be located to intersect with a line segment connecting respective axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) or may be located in a region between the axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This arrangement makes it possible to largely set a space between adjacent ones of a plurality of interconnection lines  720   a ,  720   b ,  721  so as to facilitate interconnection layout. 
     Further, in the same manner as that in  FIGS. 5(   a ) and  5 ( b ), a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers. This makes it possible to reduce a resistance of a contact, and stably form a contact. 
     Third Embodiment 
     A third embodiment shows one example where the present invention is applied to a CMOS inverter.  FIG. 23(   a ) is a top plan view showing a CMOS inverter according to the third embodiment, and  FIG. 23(   b ) is a sectional view taken along the line A-A′ in  FIG. 23(   a ). In  FIGS. 23(   a ) and  23 ( b ), an interconnection layer  820   a  connected to an NMOS transistor is connected to GND, and an interconnection layer  820   b  connected to a PMOS transistor is connected to Vcc. An input signal Vin is input into a gate interconnection layer  808  from an interconnection layer  822 , and two interconnection lines  821   a ,  821   b  connected from respective upper sides of the NMOS and PMOS transistors are connected to each other through an interconnection layer to output an output signal Vout therefrom. In this manner, a CMOS inverter is formed. 
     With reference to  FIGS. 23(   a ) and  23 ( b ), a structure of the CMOS inverter according to the third embodiment will be described below. A silicon substrate  801  is isolated on an element-by-element basis by an element isolation  802 . Two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  805   a  constituting an NMOS transistor (NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers)  805   a ), and four pillar-shaped silicon layers (pillar-shaped semiconductor layers)  805   b  constituting a PMOS transistor (PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers)  805   b ), are formed on the silicon substrate. A gate dielectric film (first dielectric film)  807  and a gate electrode ( 808   a ,  808   b ) are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the third embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a metal film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film), and a polysilicon film may be used as the gate electrode. A lower N +  diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions)  803   a  surrounded by a P-well  801   a  is formed underneath the NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers)  805   a , and a lower P +  diffusion layer (first drain/source diffusion region)  803   b  surrounded by an N-well  801   b  is formed underneath the PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers)  805   b . A lower silicide layer ( 811   a ,  811   b ) is formed on a surface of each of the lower N +  and P +  diffusion layers (first drain/source diffusion regions) to reduce a parasitic resistance. An upper N +  diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions)  809   a  is formed on top of each of the NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers)  805   a  in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the NMOS pillar-shaped silicon layer. An upper P +  diffusion layer (second drain/source diffusion region)  809   b  is formed on top of each the PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers)  805   b  in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the PMOS pillar-shaped silicon layer. In the third embodiment, the upper diffusion layer having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper diffusion layer may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode ( 808   a ,  808   b ) by a second dielectric film  812 , such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. The two NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers)  805   a  are arranged adjacent to each other, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed on tops of respective upper surfaces of the NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers) are self-alignedly connected together. The four PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers)  805   b  are also arranged adjacent to each other, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed on tops of respective upper surfaces of the PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers) are self-alignedly connected together in the same manner. 
     Two upper silicide layers  811   c ,  811   d  are formed, respectively, on the integral set of upper N +  diffusion layers  809   a  and the integral set of upper P +  diffusion layers (second drain/source diffusion regions)  809   b . Each of the upper silicide layers is formed on the connected epitaxial silicon layers (semiconductor epitaxial layers) each having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the integral set of upper diffusion layers ( 809   a ,  809   b ) can be set largely, so that an interface resistance between the upper silicide layer and the integral set of upper diffusion layers can be reduced. Further, the upper silicide layer ( 811   c ,  811   d ) may be formed in an upper surface of the integral set of the upper diffusion layers (second drain/source diffusion regions) to have a diameter greater than a total diameter of a plurality of contacts ( 815 ,  816 ) to be formed on an upper side of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. As shown in  FIGS. 24(   a ) and  24 ( b ), as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers. 
     Further, for example, in an NMOS transistor illustrated in  FIGS. 24(   a ) and  24 ( b ), a contact  915  may be formed on an integral set of upper N +  diffusion layers (second drain/source diffusion regions)  909   a  at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). In this case, an axis of the contact  915  may be located to intersect with a line segment connecting respective axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) or may be located in a region between the axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). The number of contacts can be reduced by this arrangement or an arrangement in a PMOS transistor illustrated in  FIGS. 24(   a ) and  24 ( b ). This makes it possible to largely set a space between adjacent ones of a plurality of interconnection lines  920   a ,  920   b ,  921   a ,  921   b ,  922  so as to facilitate interconnection layout. 
     Further, in the same manner as that in  FIGS. 5(   a ) and  5 ( b ), a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers. This makes it possible to reduce a resistance of a contact, and stably form a contact. 
     Fourth Embodiment 
       FIG. 25(   a ) is a top plan view showing a transistor using an SOI substrate according to a fourth embodiment of the present invention, and  FIG. 25(   b ) is a sectional view taken along the line A-A′ in  FIG. 25(   a ). With reference to  FIGS. 25(   a ) and  25 ( b ), an SOI transistor according to the fourth embodiment will be described below. A silicon layer  1002  on an SOI (silicon on insulator) substrate is isolated on an element-by-element basis, and two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1005   a ,  1005   b  are formed on the silicon layer  1002 . A gate dielectric film (first dielectric film)  1007  and a gate electrode ( 1008   a ,  1008   b ) are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the fourth embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a metal film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film), and a polysilicon film may be used as the gate electrode. A lower N +  diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions)  1003  is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers), and a lower silicide layer  1011   a  is formed on a surface of the lower N +  diffusion layer (first drain/source diffusion region)  1003 , to reduce a parasitic resistance. An upper N +  diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions) ( 1009   a ,  1009   b ) is formed on top of each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers), in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the pillar-shaped silicon layer. In the fourth embodiment, the upper N +  diffusion layer (second drain/source diffusion region) having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper N +  diffusion layer (second drain/source diffusion region) may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode ( 1008   a ,  1008   b ) by a second dielectric film  1012 , such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. An upper silicide layer ( 1011   b ,  1011   c ) is formed on the upper N +  diffusion layer (second drain/source diffusion region) ( 1009   a ,  1009   b ). The upper silicide layer is formed on the epitaxial silicon layer (semiconductor epitaxial layer) having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the upper N +  diffusion layer can be set largely, so that an interface resistance between the upper silicide layer and the upper N +  diffusion layer can be reduced. Further, the upper silicide layer ( 1011   b ,  1011   c ) may be formed in an upper surface of the upper N +  diffusion layer (second drain/source diffusion region) to have a diameter greater than that of a contact ( 1015 ,  1016 ) to be formed on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The contact ( 1015 ,  1016 ) formed on the upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to one of drain and source terminals through an interconnection layer  1020 . A contact  1018  formed on a lower side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to a remaining one of the drain and source terminals through an interconnection layer  1022 , and a contact  1017  formed on a gate line  1008  extending from the gate electrode is connected to a gate terminal through an interconnection layer  1021 . 
     As shown in  FIGS. 26(   a ) and  26 ( b ), in cases where a distance between two adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1105   a ,  1105   b  is less than a given value, a thickness of a film to be epitaxially grown can be adjusted in such a manner that the epitaxial silicon layers (semiconductor epitaxial layers) on respective ones of the adjacent pillar-shaped semiconductor layers are self-alignedly connected together. In this case, an interface area between an upper silicide layer  1111   b  on an upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) and an integral set of upper N +  diffusion layers (second drain/source diffusion regions)  1109   a ,  1109   b  formed in the connected semiconductor epitaxial layers becomes larger, so that an interface resistance between the an upper silicide layer and the integral set of upper N +  diffusion layers (second drain/source diffusion regions) can be further reduced. In addition, an area of the upper silicide layer  1111   a  on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) becomes larger, so that the narrow width effect on the upper silicide layer can be significantly reduced to facilitate adequate formation of the upper silicide layer. 
     Further, in the fourth embodiment using an SOI substrate, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with  FIGS. 3(   a ) and  3 ( b ). 
     Further, a contact may be formed on an integral set of upper N +  diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers), as described in connection with  FIGS. 4(   a ) and  4 ( b ). In this case, an axis of the contact may be located to intersect with a line segment connecting respective axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) or may be located in a region between the axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This arrangement makes it possible to largely set a space between adjacent ones of a plurality of interconnection lines so as to facilitate interconnection layout. 
     Further, a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers, as described in connection with  FIGS. 5(   a ) and  5 ( b ). This makes it possible to reduce a resistance of a contact, and stably form a contact. 
     With reference to  FIGS. 27(   a ) to  41 ( b ), one example of a production method for the transistor illustrated in  FIGS. 26(   a ) and  26 ( b ) will be described below. In  FIGS. 27(   a ) and  27 ( b ) to  FIGS. 41(   a ) and  41 ( b ), the figure suffixed with (a) is a top plan view, and the figure suffixed with (b) is a sectional view taken along the line A-A′ in the figure suffixed with (a). 
     As shown in  FIGS. 27(   a ) and  27 ( b ), two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1105   a ,  1105   b  having a hard mask layer  1104   a , such as a silicon nitride film, on top thereof, are formed on a silicon layer  1102  on an SOI substrate by lithography and etching. 
     As shown in  FIGS. 28(   a ) and  28 ( b ), the silicon layer  1102  on the SOI substrate is isolated on an element-by-element basis. 
     As shown in  FIGS. 29(   a ) and  29 ( b ), after the element isolation, a lower N +  diffusion layer  1103  is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers) by ion implantation or the like. In this step, the pillar-shaped silicon layer (pillar-shaped semiconductor layer) ( 1105   a ,  1105   b ) is kept from impurity implantation by the hard mask layer  1104   a  on top of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). 
     As shown in  FIGS. 30(   a ) and  30 ( b ), a gate dielectric film (first dielectric film)  1107  and a gate conductive film  1108   c  are formed. The gate dielectric film (first dielectric film)  1107  is formed of an oxide film, a High-k film or the like. The gate conductive film  1108   c  is formed of a polysilicon film, a metal film or the like. 
     As shown in  FIGS. 31(   a ) and  31 ( b ), the gate conductive film  1108   c  is flattened by chemical mechanical polishing (CMP) or the like. 
     As shown in  FIGS. 32(   a ) and  32 ( b ), the gate dielectric film (first dielectric film)  1107  and the gate conductive film  1108   c  are etched back to allow a height dimension of each of the gate dielectric film (first dielectric film)  1107  and the gate conductive film  1108   c  along a sidewall of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) ( 1105   a ,  1105   b ) to be set to a desired gate length. 
     As shown in  FIGS. 33(   a ) and  33 ( b ), a nitride film or the like is formed and then etched back to form a sidewall spacer  1104   b.    
     As shown in  FIGS. 34(   a ) and  34 ( b ), a gate line pattern is formed using a resist  1110  by lithography or the like. 
     As shown in  FIGS. 35(   a ) and  35 ( b ), the gate conductive film  1108   c  and the gate dielectric film (first dielectric film)  1107  are selectively etched by anisotropic etching or the like, using the resist  1110  as a mask, to integrally form a gate electrode ( 1108   a ,  1108   b ) around the pillar-shaped silicon layer (pillar-shaped semiconductor layer) ( 1105   a ,  1105   b ) and a gate line  1108  extending from the gate electrode ( 1108   a ,  1108   b ). Subsequently, the resist  1110  is removed. 
     As shown in  FIGS. 36(   a ) and  36 ( b ), the hard mask layer  1104   a  and the sidewall spacer  1104   b  are removed by wet etching or the like. 
     As shown in  FIGS. 37(   a ) and  37 ( b ), a dielectric film, such as a nitride film or a laminated film comprised of a nitride film and an oxide film, is formed, and then etched back to form a second dielectric film  1112 . 
     As shown in  FIGS. 38(   a ) and  38 ( b ), silicon or the like is selectively epitaxially grown on top of an upper surface of each of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) and on the lower N +  diffusion layer  1103  to form an upper epitaxial silicon layer (semiconductor epitaxial layer)  1110   b  and a lower epitaxial silicon layer, in such a manner that epitaxial layers formed on tops of respective upper surfaces of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) arranged adjacent to each other with a given distance or less therebetween are self-alignedly connected together. The upper epitaxial silicon layer (semiconductor epitaxial layer) may be formed to have a diameter greater than that of a contact to be formed on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) in a subsequent step. This makes it possible to provide a structure free of a short-circuiting between the contact and the gate electrode. 
     As shown in  FIGS. 39(   a ) and  39 ( b ), an upper N +  diffusion layer (second drain/source diffusion region) ( 1109   a ,  1109   b ) is formed in the upper epitaxial silicon layer (semiconductor epitaxial layer)  1110   b  and an upper portion of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) ( 1105   a ,  1105   b ) by ion implantation or the like. 
     As shown in  FIGS. 40(   a ) and  40 ( b ), a metal, such as Co or Ni, is sputtered, and then a heat treatment is performed to selectively silicide respective upper surfaces of the lower epitaxial silicon layer on the lower N +  diffusion layer (first drain/source diffusion region)  1103  and the integral set of upper N +  diffusion layers (second drain/source diffusion regions)  1109   a ,  1109   b  to form a lower silicide layer  1111   a  and an upper silicide layer  1111   b . The upper silicide layer  1111   b  is formed to have a size greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer), so that the narrow width effect on the upper silicide layer can be suppressed. Further, the entire surface of the epitaxial silicon layer (semiconductor epitaxial layer) may be silicided. In this case, an interface area between the upper silicide layer  1111   b  and the integral set of upper N +  diffusion layers (second drain/source diffusion regions)  1109   a ,  1109   b  is increased, so that an interface resistance therebetween can be reduced to reduce a source/drain parasitic resistance. 
     As shown in  FIGS. 41(   a ) and  41 ( b ), a silicon oxide film is formed to serve as an interlayer film, and then a contact ( 1115  to  1118 ) is formed. The epitaxial silicon layer (semiconductor epitaxial layer) is formed to allow the contact ( 1115 ,  1116 ) on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) to be entirely formed on the upper silicide layer  1111   b , as shown in  FIGS. 41(   a ) and  41 ( b ). This makes it possible to provide a structure free of a short-circuiting between the contact and the gate electrode. 
     The fourth embodiment shows one example where an epitaxial silicon layer (semiconductor epitaxial layer) is formed. Specifically, an epitaxial silicon carbide (SiC) layer may be formed for an NMOS transistor, and an epitaxial silicon germanium (SiGe) layer may be formed for a PMOS transistor. In this case, a stress can be applied to a channel region to enhance carrier mobility. 
     Fifth Embodiment 
     A fifth embodiment shows one example where the present invention is applied to a set of transistors formed by connecting in series two transistors.  FIG. 42(   a ) is a top plan view showing a transistor according to the fifth embodiment, and  FIG. 42(   b ) is a sectional view taken along the line A-A′ in  FIG. 42(   a ). With reference to  FIGS. 42(   a ) and  42 ( b ), a structure of the transistor according to the fifth embodiment will be described below. A silicon layer  1202  on an SOI substrate is isolated on an element-by-element basis. Two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1205   a ,  1205   b  constituting a first transistor, and two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1205   c ,  1205   d  constituting a second transistor, are formed on the silicon layer  1202 . A gate dielectric film (first dielectric film)  1207  and a gate electrode  1208   a  to  1208   d  are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the fifth embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a metal film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film), and a polysilicon film may be used as the gate electrode. A lower N +  diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions)  1203  is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers), and a lower silicide layer  1211   a  is formed on a surface of the lower N +  diffusion layer (first drain/source diffusion region)  1203 , to reduce a parasitic resistance. An upper N +  diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions) ( 1209   a  to  1209   d ) is formed on top of each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers), in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the pillar-shaped silicon layer. In the fifth embodiment, the upper N +  diffusion layer (second drain/source diffusion region) having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper N +  diffusion layer (second drain/source diffusion region) may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode  1208   a  to  1208   d  by a second dielectric film  1212 , such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. The two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1205   a ,  1205   b  constituting the first transistor are arranged adjacent to each other, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed on tops of respective upper surfaces of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) are self-alignedly connected together. The two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1205   c ,  1205   d  constituting the second transistor are also arranged adjacent to each other, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed on tops of respective upper surfaces of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) are self-alignedly connected together in the same manner. In contrast, the two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1205   b ,  1205   c  each constituting a different transistor are arranged with a distance greater than a given value therebetween, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed thereon are separated from each other. 
     Two upper silicide layers  1211   b ,  1211   c  are formed, respectively, on the integral set of upper N +  diffusion layers (second drain/source diffusion regions)  1209   a ,  1209   b  and the integral set of upper N +  diffusion layers (second drain/source diffusion regions)  1209   c ,  1209   d . Each of the upper silicide layers is formed on the connected epitaxial silicon layers (semiconductor epitaxial layers) each having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the integral set of upper N +  diffusion layers ( 1209   a  to  1209   d ) can be set largely, so that an interface resistance between the upper silicide layer and the integral set of upper N +  diffusion layers can be reduced. Further, the upper silicide layer ( 1211   b ,  1211   c ) may be formed in an upper surface of the integral set of the upper N +  diffusion layers (second drain/source diffusion regions) to have a diameter greater than a total diameter of two contacts ( 1215   a ,  1215   b ;  1216   a ,  1216   b ) to be formed on an upper side of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The two contacts  1215   a ,  1215   b  formed on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) constituting the first transistor are connected to one of drain and source terminals through an interconnection layer  1220   a , and the two contacts  1216   a ,  1216   b  formed on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) constituting the second transistor are connected to a remaining one of the drain and source terminals through an interconnection layer  1220   b . Further, the first transistor and the second transistor are connected in series through the lower N +  diffusion layer (first drain/source diffusion region)  1203 . A contact  1217  formed on a gate line  1208  extending from the gate electrode is connected to a gate terminal through an interconnection layer  1221 . 
     In the fifth embodiment using an SOI substrate, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with  FIGS. 22(   a ) and  22 ( b ). 
     Further, in the same manner as that in  FIGS. 22(   a ) and  22 ( b ), a contact may be formed on an integral set of upper N +  diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). In this case, an axis of the contact may be located to intersect with a line segment connecting respective axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) or may be located in a region between the axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This arrangement makes it possible to largely set a space between adjacent ones of a plurality of interconnection lines so as to facilitate interconnection layout. 
     Further, in the same manner as that in  FIGS. 5(   a ) and  5 ( b ), a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers. This makes it possible to reduce a resistance of a contact, and stably form a contact. 
     Sixth Embodiment 
     A sixth embodiment shows one example where the present invention is applied to a CMOS inverter using an SOI substrate.  FIG. 43(   a ) is a top plan view showing a CMOS inverter according to the sixth embodiment, and  FIG. 43(   b ) is a sectional view taken along the line A-A′ in  FIG. 43(   a ). In  FIGS. 43(   a ) and  43 ( b ), an interconnection layer  1320   a  connected to an NMOS transistor is connected to GND, and an interconnection layer  1320   b  connected to a PMOS transistor is connected to Vcc. An input signal Vin is input into a gate interconnection layer  1308  from an interconnection layer  1322 , and two interconnection lines  1321   a ,  1321   b  connected from respective upper sides of the NMOS and PMOS transistors are connected to each other through an interconnection layer to output an output signal Vout therefrom. In this manner, a CMOS inverter is formed. 
     With reference to  FIGS. 43(   a ) and  43 ( b ), a structure of the CMOS inverter according to the sixth embodiment will be described below. Each of two silicon layers  1302   a ,  1302   b  on an SOI substrate is electrically isolated on an element-by-element basis. Two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1305   a  constituting an NMOS transistor (NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers)  1305   a ), and four pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1305   b  constituting a PMOS transistor (PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers)  1305   b ), are formed on the silicon layer  1302   a  and silicon layer  1302   b , respectively. A gate dielectric film (first dielectric film)  1307  and a gate electrode ( 1308   a ,  1308   b ) are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the sixth embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a metal film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film), and a polysilicon film may be used as the gate electrode. A lower N +  diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions)  1303   a  is formed underneath the NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers)  1305   a , and a lower P +  diffusion layer (first drain/source diffusion region)  1303   b  is formed underneath the PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers)  1305   b . A lower silicide layer ( 1311   a ,  1311   b ) is formed on a surface of each of the lower N +  and N +  diffusion layers (first drain/source diffusion regions) to reduce a parasitic resistance. An upper N +  diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions)  1309   a  is formed on top of each of the NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers)  1305   a  in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the NMOS pillar-shaped silicon layer. An upper N +  diffusion layer (second drain/source diffusion region)  1309   b  is formed on top of each the PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers)  1305   b  in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the PMOS pillar-shaped silicon layer. In the sixth embodiment, the upper diffusion layer having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper diffusion layer may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode ( 1308   a ,  1308   b ) by a second dielectric film  1312 , such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. The two NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers)  1305   a  are arranged adjacent to each other, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed on tops of respective upper surfaces of the NMOS pillar-shaped silicon layers (NMOS pillar-shaped semiconductor layers) are self-alignedly connected together. The four PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers)  1305   b  are also arranged adjacent to each other, so that epitaxial silicon layers (semiconductor epitaxial layers) to be formed on tops of respective upper surfaces of the PMOS pillar-shaped silicon layers (PMOS pillar-shaped semiconductor layers) are self-alignedly connected together in the same manner. 
     Two upper silicide layers  1311   c ,  1311   d  are formed, respectively, on the integral set of upper N +  diffusion layers  1309   a  and the integral set of upper P +  diffusion layers (second drain/source diffusion regions)  1309   b . Each of the upper silicide layers is formed on the connected epitaxial silicon layers (semiconductor epitaxial layers) each having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the integral set of upper diffusion layers ( 1309   a ,  1309   b ) can be set largely, so that an interface resistance between the upper silicide layer and the integral set of upper diffusion layers can be reduced. Further, the upper silicide layer ( 1311   c ,  1311   d ) may be formed in an upper surface of the integral set of the upper diffusion layers (second drain/source diffusion regions) to have a diameter greater than a total diameter of a plurality of contacts ( 1315 ,  1316 ) to be formed on an upper side of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. 
     In the sixth embodiment using an SOI substrate, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with  FIGS. 24(   a ) and  24 ( b ). 
     Further, a contact may be formed on an integral set of upper N +  diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers), as described in connection with  FIGS. 24(   a ) and  24 ( b ). In this case, an axis of the contact may be located to intersect with a line segment connecting respective axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) or may be located in a region between the axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). The number of contacts can be reduced by this arrangement or an arrangement in a PMOS transistor illustrated in  FIGS. 24(   a ) and  24 ( b ). This makes it possible to largely set a space between adjacent ones of a plurality of interconnection lines  1320   a ,  1320   b ,  1321   a ,  1321   b ,  1322  so as to facilitate interconnection layout. 
     Further, in the same manner as that in  FIGS. 5(   a ) and  5 ( b ), a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers. This makes it possible to reduce a resistance of a contact, and stably form a contact. 
     Seventh Embodiment 
       FIG. 44(   a ) is a top plan view showing a transistor using a polysilicon layer as a gate electrode, according to a seventh embodiment of the present invention, and  FIG. 44(   b ) is a sectional view taken along the line A-A′ in  FIG. 44(   a ). With reference to  FIGS. 44(   a ) and  44 ( b ), a structure of the transistor according to the seventh embodiment will be described below. A silicon substrate  1401  is isolated on an element-by-element basis by an element isolation  1402 , and two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1405   a ,  1405   b  are formed on the silicon substrate. A gate dielectric film (first dielectric film)  1407  and a gate electrode ( 1408   a ,  1408   b ) are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the seventh embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a polysilicon film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film). In view of the gate electrode formed of a polysilicon film, a silicide layer  1411   c  is formed on a surface of the gate electrode, in addition to silicide layers on respective surfaces of after-mentioned diffusion layers. A lower N+ diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions)  1403  is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers), and a lower silicide layer  1411   a  is formed on a surface of the lower N +  diffusion layer (first drain/source diffusion region)  1403 , to reduce a parasitic resistance. An upper N +  diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions) ( 1409   a ,  1409   b ) is formed on top of each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers), in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the pillar-shaped silicon layer. In the seventh embodiment, the upper N +  diffusion layer (second drain/source diffusion region) ( 1409   a ,  1409   b ) having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper N +  diffusion layer (second drain/source diffusion region) may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode ( 1408   a ,  1408   b ) by a second dielectric film  1412 , such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. A distance between the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1405   a ,  1405   b  is less than a given value. Thus, a thickness of a film to be epitaxially grown is adjusted in such a manner that the upper N +  diffusion layers (second drain/source diffusion regions) on respective ones of the adjacent pillar-shaped semiconductor layers are self-alignedly connected together. An upper silicide layer  1411   b  is formed on the upper N +  diffusion layer (second drain/source diffusion region) ( 1409   a ,  1409   b ). The upper silicide layer is formed on the epitaxial silicon layer (semiconductor epitaxial layer) having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the upper N+ diffusion layer can be set largely, so that an interface resistance between the upper silicide layer and the upper N +  diffusion layer can be reduced. Further, the upper silicide layer ( 1411   b ) may be formed in an upper surface of the upper N+ diffusion layer (second drain/source diffusion region) to have a diameter greater than that of a contact ( 1415 ,  1416 ) to be formed on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The contact ( 1415 ,  1416 ) formed on the upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to one of drain and source terminals through an interconnection layer  1420 . A contact  1418  formed on a lower side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to a remaining one of the drain and source terminals through an interconnection layer  1422 , and a contact  1417  formed on a gate line  1408  extending from the gate electrode is connected to a gate terminal through an interconnection layer  1421 . A production method for the transistor according to the seventh embodiment is the same as that for the transistor according to the first embodiment. Further, in cases where the transistor according to the seventh embodiment uses an SOI substrate, the same production method as that for the transistor according to the fourth embodiment may be used. 
     In the seventh embodiment using a polysilicon film as a gate electrode, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with  FIGS. 3(   a ) and  3 ( b ). 
     Further, a contact may be formed on an integral set of upper N +  diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers), as described in connection with  FIGS. 4(   a ) and  4 ( b ). In this case, an axis of the contact may be located to intersect with a line segment connecting respective axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) or may be located in a region between the axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This arrangement makes it possible to largely set a space between adjacent ones of a plurality of interconnection lines so as to facilitate interconnection layout. 
     Further, a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers, as described in connection with  FIGS. 5(   a ) and  5 ( b ). This makes it possible to reduce a resistance of a contact, and stably form a contact. 
     Eighth Embodiment 
       FIG. 45(   a ) is a top plan view showing a transistor having a gate electrode formed of a fully-silicided polysilicon layer, according to an eighth embodiment of the present invention, and  FIG. 45(   b ) is a sectional view taken along the line A-A′ in  FIG. 45(   a ). With reference to  FIGS. 45(   a ) and  45 ( b ), a structure of the transistor according to the eighth embodiment will be described below. A silicon substrate  1501  is isolated on an element-by-element basis by an element isolation  1502 , and two pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1505   a ,  1505   b  are formed on the silicon substrate. A gate dielectric film (first dielectric film)  1507  and a gate electrode ( 1508   a ,  1508   b ) are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the eighth embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a fully-silicided polysilicon film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film). The polysilicon gate electrode is fully silicided by optimizing a thickness of a sputtered film made of a silicide material or by adjusting siliciding conditions. A lower N +  diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions)  1503  is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers), and a lower silicide layer  1511   a  is formed on a surface of the lower N +  diffusion layer (first drain/source diffusion region)  1503 , to reduce a parasitic resistance. An upper N +  diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions) ( 1509   a ,  1509   b ) is formed on top of each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers), in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the pillar-shaped silicon layer. In the eighth embodiment, the upper N +  diffusion layer (second drain/source diffusion region) ( 1509   a ,  1509   b ) having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper N +  diffusion layer (second drain/source diffusion region) may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode ( 1508   a ,  1508   b ) by a second dielectric film  1512 , such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. A distance between the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers)  1505   a ,  1505   b  is less than a given value. Thus, a thickness of a film to be epitaxially grown is adjusted in such a manner that the upper N +  diffusion layers (second drain/source diffusion regions) on respective ones of the adjacent pillar-shaped semiconductor layers are self-alignedly connected together. An upper silicide layer  1511   b  is formed on the upper N +  diffusion layer (second drain/source diffusion region) ( 1509   a ,  1509   b ). The upper silicide layer is formed on the epitaxial silicon layer (semiconductor epitaxial layer) having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the upper N +  diffusion layer can be set largely, so that an interface resistance between the upper silicide layer and the upper N +  diffusion layer can be reduced. Further, the upper silicide layer ( 1511   b ) may be formed in an upper surface of the upper N +  diffusion layer (second drain/source diffusion region) to have a diameter greater than that of a contact ( 1515 ,  1516 ) to be formed on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The contact ( 1515 ,  1516 ) formed on the upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to one of drain and source terminals through an interconnection layer  1520 . A contact  1518  formed on a lower side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to a remaining one of the drain and source terminals through an interconnection layer  1522 , and a contact  1517  formed on a gate line  1508  extending from the gate electrode is connected to a gate terminal through an interconnection layer  1521 . A production method for the transistor according to the eighth embodiment is the same as that for the transistor according to the first embodiment. Further, in cases where the transistor according to the seventh embodiment uses an SOI substrate, the same production method as that for the transistor according to the fourth embodiment may be used. 
     In the eighth embodiment using a fully-silicided polysilicon film as a gate electrode, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with  FIGS. 3(   a ) and  3 ( b ). 
     Further, a contact may be formed on an integral set of upper N +  diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers), as described in connection with  FIGS. 4(   a ) and  4 ( b ). In this case, an axis of the contact may be located to intersect with a line segment connecting respective axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers) or may be located in a region between the axes of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This arrangement makes it possible to largely set a space between adjacent ones of a plurality of interconnection lines so as to facilitate interconnection layout. 
     Further, a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers, as described in connection with  FIGS. 5(   a ) and  5 ( b ). This makes it possible to reduce a resistance of a contact, and stably form a contact.