Abstract:
A multi-stage analog bi-directional selector which has a low input impedance and cost. The multi-stage analog bi-directional selector includes a plurality of analog switches including first and second bi-polar transistors coupled together at first and second connection points, a primary channel coupled to the first connection points, a plurality of data channels coupled to the second connection points, and an address circuit which causes a single one of the analog switches to form a bi-directional analog data connection between a corresponding single one of the data channels and the primary channel.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to communication switching circuitry, and more specifically to a multi-stage analog bi-directional selector. 
     Multiplexers and de-multiplexers perform data path selection, but do not support asynchronous bi-directional communication. 
     Analog switches control bi-directional communication, but do not support data path selection. They also have input impedances which are too high (about 200 ohms maximum). This impedance requires a proportional increase in the voltage of the circuit which drives such a switch. 
     Presently, there are no low impedance devices which combine the data path selection of a multiplexer with the asynchronous bi-directional communication of an analog switch. Such a combination would be desirable, particularly for passing bi-directional TTL logic signals on a wire-or bus typical of what is found in the PC-AT keyboard, namely clock and data signals. Thus, two keyboards may be more easily connected to a single keyboard controller 49 within a computer. The computer may then choose which keyboard to communicate with. 
     Another application for this invention is in keyboard wedge devices, in which communication with the wedged device would occur through the keyboard&#39;s communication interface. The invention would be used in the keyboard to control placement of data from the wedged device onto the keyboard&#39;s communication channel. 
     Therefore, it would be desirable to provide a multi-stage analog bi-directional selector with low impedance and with low cost. 
     SUMMARY OF THE INVENTION 
     In accordance with the teachings of the present invention, a multi-stage analog bi-directional selector is provided. 
     The multi-stage analog bi-directional selector includes a plurality of analog switches including first and second bi-polar transistors coupled together at first and second connection points, a primary channel coupled to the first connection points, a plurality of data channels coupled to the second connection points, and an address circuit which causes a single one of the analog switches to form a bi-directional analog data connection between a corresponding single one of the data channels and the primary channel. 
     It is accordingly an object of the present invention to provide a multi-stage analog bi-directional selector. 
     It is another object of the present invention to provide a multi-stage analog bi-directional selector that has a low impedance. 
     It is another object of the present invention to provide a multi-stage analog bi-directional selector that is low in cost. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Additional benefits and advantages of the present invention will become apparent to those skilled in the art to which this invention relates from the subsequent description of the preferred embodiments and the appended claims, taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of the multi-stage analog bi-directional selector; 
     FIG. 2 is a circuit diagram of a two-stage analog bi-directional selector within a computer system including first and second keyboards; and 
     FIG. 3 is a circuit diagram of a four-stage analog bi-directional selector. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Turning now to FIG. 1, multi-stage analog bi-directional selector circuit 10 includes N-stage selector 12 and addressing logic 14. 
     N-stage selector 12 provides bi-directional analog communication between a primary channel 16 and one of a number N of data channels 18 N . 
     Addressing logic 14 determines which one of the data channels 18 N  is connected to the primary channel 16 through N-stage selector 12. Addressing logic 14 includes address input 17. 
     The relationship between the number of channels N and the number of address bits B required may be defined by the equation 
     
         N&lt;2.sup.B 
    
     For example, two address bits B will support up to four data channels. 
     Referring now to FIG. 2, a two-stage version of multi-stage analog bi-directional selector 10 is shown. 
     Two-stage selector 20 primarily includes two analog switches 22 and 24 which control bi-directional flow of TTL signals between keyboards 46 and 47 and a keyboard controller 49 within computer 48. 
     Switch 22 includes bi-polar transistors 26 and 28 in which the collector of one is connected to the emitter of the other. Connection 34 is coupled to computer 48 through primary channel 16, while connection 36 is connected to keyboard 47 through data channel 18 2 . The base of each transistor is connected to a bias voltage V cc  through pull-up resistors R 1 , R 2 , and R 3 . 
     Similarly, switch 24 includes bi-polar transistors 30 and 32 in which the collector of one is connected to the emitter of the other. Connection 38 is coupled to computer 48 primary channel 16, while connection 40 is connected to keyboard 46 through data channel 18 1 . The base of each transistor is connected to a bias voltage V cc  through pull-up resistors R 4 , R 5 , and R 6 . 
     A nominal value for resistors R 1 , R 2 , R 4 , and R 5 , is 10K ohms. A nominal value for resistors R 3  and R 6  is 4.7K ohms. 
     In both switches 22 and 24, bi-polar transistors are employed because they require only a nominal bias voltage V cc  of five volts. Bi-polar transistors 26, 28, 30, and 32 have a model number of 2N3904. 
     Field effect transistors (FETs) are not employed because they present many challenges that would ultimately increase the cost of selector 10 to solve them. N-type FETs are less expensive than P-type and also offer lower resistance than corresponding P-types. However, n-type FETs are still relatively expensive and require a more expensive control circuit since they require voltage in excess of five volts (typically a V cc  of 7 to 10 volts) to assure the minimum turn-on resistance. 
     All FETs have an intrinsic diode that provides a signal path in one direction through the diode, even though the FET is off. To prevent the diode path operation, it is necessary to connect two FETs in series such that the intrinsic diodes face opposite directions and hence do not provide a conduction path in either direction. Using two FETs connected like this works well, allowing the FET&#39;s on state to control the connection of the bi-directional signal path. However, using two FETs in series doubles the channel resistance so that lower channel resistance devices must be selected to limit voltage drop across the FET switch. 
     Bipolar transistors are typically almost half the cost of a corresponding FET, and do not require a high voltage supply to control them. Furthermore, bipolar transistors contain no intrinsic diode so they can be connected in parallel, with one device offering a conduction path for each polarity of signal. If the bipolar devices are driven to saturation in the &#34;on&#34; state, there is a predictable voltage drop of typically less than 0.2 volts. 
     An important advantage associated with the design of selector 10 is that the variation of pull-up resistors from different keyboard vendors does not materially affect the operation of the selector 10, since the voltage drop can be predicted. This is unlike the FET solution in which the channel resistance of both devices is added and the current supplied by the keyboard pull-up resistor causes a voltage drop that is predictable, but varies widely with different keyboards. 
     Since bipolar devices are involved, the control impedance is lower than a FET, however in this circuit, the control voltage is relatively high, because the β of the transistor multiplies the control current supplied by the on control circuit. Hence a relatively small control current (0.1 ma) can control a fairly large signal current (10 ma with a β of 100). 
     Addressing logic 14 includes two inverters 42 and 44 which determine which of data channels 18 1  and 18 2  is connected to computer 48 through primary channel 16. The keyboard controller 49 within computer 48 determines which of keyboards 46 and 47 is connected by producing an address input signal at address input 17. 
     Operation requires only a single-digit address. When address input 17 is high, inverter 42 produces a low output which causes transistors 26 and 28 of switch 22 to turn off and data channel 18 2  to be deselected. Inverter 44 produces a high output which causes transistors 30 and 32 of switch 24 to turn on and data channel 18 1  to be selected. 
     Similarly, when address input 17 is low, inverter 42 produces a high output which causes transistors 26 and 28 of switch 22 to turn on and data channel 18 2  to be selected. Inverter 44 produces a low output which causes transistors 30 and 32 of switch 24 to turn off and data channel 18 1  to be deselected. 
     Referring now to FIG. 3, a four-stage version of multi-stage analog bi-directional selector 10 is shown. 
     Four-stage selector 50 primarily includes four analog switches 52, 54, 56, and 58. Switch 52 includes bi-polar transistors 60 and 62 in which the collector of one is connected to the emitter of the other. Connection 76 is coupled to primary channel 16, while connection 78 is connected to data channel 18 4 . The base of each transistor is connected to a bias voltage V cc  through pull-up resistors R 7 , R 8 , and R 9 . 
     Switch 54 includes bi-polar transistors 64 and 66 in which the collector of one is connected to the emitter of the other. Connection 80 is coupled to primary channel 16, while connection 82 is connected to data channel 18 3 . The base of each transistor is connected to a bias voltage V cc  through pull-up resistors R 10 , R 11 , and R 12 . 
     Switch 56 includes bi-polar transistors 68 and 70 in which the collector of one is connected to the emitter of the other. Connection 84 is coupled to primary channel 16, while connection 86 is connected to data channel 18 2 . The base of each transistor is connected to a bias voltage V cc  through pull-up resistors R 13 , R 14 , and R 15 . 
     Finally, switch 58 includes bi-polar transistors 72 and 74 in which the collector of one is connected to the emitter of the other. Connection 88 is coupled to primary channel 16, while connection 90 is connected to data channel 18 1 . The base of each transistor is connected to a bias voltage V cc  through pull-up resistors R 16 , R 17 , and R 18 . 
     Similar to the two-stage embodiment of FIG. 2, bi-polar transistors are employed because they require only a nominal bias voltage V cc  of five volts. 
     A nominal value for resistors R 7 , R 8 , R 10 , R 11 , R 13 , R 14 , R 16 , and R 17  is 10K ohms. A nominal value for resistors R 9 , R 12 , R 15 , and R 18  is 4.7K ohms. 
     Addressing logic 14 includes two inverters 100 and 102 and four AND gates which determine which of data channels 18 1 , 18 2 , 18 3 , or 18 4  is connected to primary channel 16. 
     Operation requires a two-digit address and is illustrated by Table I: 
     
                       TABLE I______________________________________Address 17A   Address 17B                   Data Channel______________________________________Low           Low       18.sub.1Low           High      18.sub.2High          Low       18.sub.3High          High      18.sub.4______________________________________ 
    
     Although the present invention has been described with particular reference to certain preferred embodiments thereof, variations and modifications of the present invention can be effected within the spirit and scope of the following claims.