Abstract:
A semiconductor wafer of the present invention is provided with a substrate having a semiconductor element formation layer, a lowermost metal layer formed on the semiconductor element formation layer and an uppermost layer formed on the lowermost metal layer, and the semiconductor wafer also has plural chip regions and an evaluation element region that is that is defined as a region between the plurality of chip regions and that has a cutaway region that is subjected to dicing when separating an individual chip and a remnant region that is not subjected to dicing when separating the chip, and a lowermost layer electrode pad and an uppermost layer electrode pad that are formed at the remnant region and at a pad region are configured by a combination of metals having a line width of less than or equal to a predetermined value.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority under 35 USC 119 from Japanese Patent Application No. 2006-262529, the disclosure of which is incorporated by reference herein. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor wafer that has a chip region and an evaluation element region and to a semiconductor chip individually separated from the semiconductor wafer. Further, the present invention relates to a method of manufacturing a semiconductor chip from a semiconductor wafer that has a chip region and an evaluation element region. 
         [0004]    2. Description of Related Art 
         [0005]    Conventionally, in the manufacture of semiconductor chips, evaluation elements known as a Test Element Group (TEG) are disposed between chip regions of a semiconductor wafer (on scribe lines), and the characteristics of the evaluation elements are observed prior to performing separation of individual semiconductor chips. It is known that by observing the characteristics of the TEG, which was formed by an identical process to the process for forming semiconductor chips, a similar effect can be obtained to observing the characteristics of semiconductor chip elements themselves. 
         [0006]    In recent years, the prevailing direction of technological development has aimed at reducing the width of the scribe line in order that a larger number of semiconductor chips can be obtained from a single semiconductor wafer. As with the invention disclosed in Japanese Patent Application (JP-A) No. 07-302773, this involves severing, by dicing, an electrode pad used for evaluation element measurement. As disclosed in JP-A No. 2003-234312, when a soft material such as aluminum is used as the material of the electrode pad for evaluation element measurement, burrs (metal peeling) are generated by dicing. When semiconductor devices or semiconductor chips are packaged by Tape Automated Bonding (TAB) techniques such as Tape Carrier Package (TCP) or Chip Size Package (CSP) techniques, or Chip on Glass (COG) techniques that directly mount semiconductor chips onto a glass substrate, there is a risk that adjacent inner leads or wiring will short-circuit due to the burrs (metal peeling). Further to JP-A No. 2003-234312, the invention of JP-A No. 2004-140157 is another example of an invention that addresses this kind of problem. 
         [0007]    However, in recent years, despite the fact that TEG electrode pads have also come to be arranged in multiple layers, respective wiring layers have become extremely thin. In the midst of these trends in technological development, the inventors of the present application noticed that the occurrence of burrs (metal peeling) could not be effectively reduced even by using techniques such as those disclosed in the above patent documents. Further, even if a certain degree of reduction is achieved, inner leads and wiring adjacent to burrs (metal peeling) that do occur are not prevented from short-circuiting. The present invention was completed in view of the foregoing circumstances and provides a semiconductor wafer that enables effective reduction in the occurrence of burrs (metal peeling) and in the event, for example, that burrs (metal peeling) do occur, enables reduction in the probability of short-circuiting of adjacent inner leads and wiring and, consequently, that enables production of a large number of high quality semiconductor chips from a single semiconductor wafer. 
       SUMMARY OF THE INVENTION 
       [0008]    The semiconductor wafer of the present invention includes a substrate, a semiconductor element formation layer formed on the substrate, a lowermost metal layer formed on the semiconductor element formation layer, and an uppermost metal layer formed on the lowermost metal layer, and further includes multiple chip regions, an evaluation element region that is defined as a region between the plurality of chip regions and that has a cutaway region that is subjected to dicing when separating an individual chip and a remnant region that is not subjected to dicing when separating the chip, an evaluation element formed at the evaluation element region, a lowermost layer electrode pad that is formed at a pad region defined as extending from the remnant region over the cutaway region within the evaluation element region, and that is formed at the lowermost metal layer so as to be electrically connected to the evaluation element, and an uppermost layer electrode pad that is formed at the pad region and that is electrically connected to the lowermost layer electrode pad, and the lowermost layer electrode pad and the uppermost layer electrode pad that are formed at the remnant region and the pad region are configured by a combination of metals having a line width of less than or equal to a predetermined value. 
         [0009]    The configuration of the semiconductor wafer of the present invention reduces the probability of short-circuiting of inner leads or wiring adjacent to burrs (metal peeling) that have been generated in a semiconductor chip that has been separated and, consequently, enables production of a large number of high quality semiconductor chips from a single semiconductor wafer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    Preferred exemplary embodiments of the present invention will be described in detail based on the following figures, wherein: 
           [0011]      FIG. 1  is a top view of a semiconductor wafer according to a first embodiment of the present invention; 
           [0012]      FIG. 2  is an enlarged view of portion A of  FIG. 1 ; 
           [0013]      FIG. 3A  is an enlarged view of a measurement pad in portion B of  FIG. 2 ; 
           [0014]      FIG. 3B  is an enlarged view of a measurement pad in portion B of  FIG. 2 ; 
           [0015]      FIG. 3C  is an enlarged view of a measurement pad in portion B of  FIG. 2 ; 
           [0016]      FIG. 3D  is an enlarged view of a measurement pad in portion B of  FIG. 2 ; 
           [0017]      FIG. 4  is a perspective view of portion C of a measurement pad of  FIG. 3D ; and 
           [0018]      FIG. 5  is a sectional view of a second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    In the following, embodiments of the present invention will be explained in detail based on the drawings. Further, in the following explanation and in the attached drawings, structural elements having substantially identical functions and configurations are provided with the same reference numerals and explanation thereof is not repeated. 
       First Embodiment 
       [0020]    First, a semiconductor wafer according to a first embodiment of the present invention is explained using  FIGS. 1 ,  2 , and  3 A- 3 D.  FIG. 1  is a top view of semiconductor wafer  100  according to a first embodiment of the present invention. As illustrated in the drawing, semiconductor wafer  100  is formed of semiconductor chips  10  and evaluation elements  30 .  FIG. 2  is an enlarged view of portion A of  FIG. 1 . As shown in  FIG. 2 , semiconductor chips  10  are regions on a substrate that has a semiconductor element layer, and represent a plurality of chip regions  20  on a substrate at which functional circuits are formed, which become semiconductor chips  10  after a subsequent separation process. Further, evaluation elements  30  are elements formed on the substrate in regions other than chip regions  20  described above. In the following, the regions in which evaluation elements  30  are formed are referred to as evaluation element formation regions  40 . In addition, evaluation element formation regions  40  consist of cutaway regions  50  that are subjected to dicing in the separation process described above, and remnant regions  60  that are not subjected to dicing in the separation process. 
         [0021]    At evaluation element formation regions  40 , in addition to the formation of evaluation elements  30 , measurement pads  70  are formed on the surface of semiconductor wafer  100  so as to be electrically connected to evaluation elements  30 . 
         [0022]    The configuration of measurement pads  70  and the configuration of wiring positioned at a bottom layer of measurement pads  70  are shown in  FIGS. 3A-3D . Further,  FIG. 4  relates to a measurement pad and wiring positioned at the bottom layer of a measurement pad having a multilayer structure. In the following, measurement pads  70  and the wiring positioned at the bottom layer of the measurement pads are collectively designated metal  310 . The configuration of metal  310  as shown in  FIG. 3A  has a short side of width a and a long side of length b. For width a and length b, for example, a=60 μm and b=90 μm. Further, metal  310  has width c at a central portion in the direction of the short side, and has central portion  311  that extends in the direction of the long side and multiple extending parts  312 , each having width d, that extend from central portion  311  in the direction of the short side. The central portion at which central portion  311  is formed is within cutaway region  50 . Further, extending parts  312  are formed integrally with central portion  311  and are formed to extend from cutaway region  50  into remnant region  60 . For widths c and d, for example, c=10 μm and d=1-5 μm. The multiple extending parts  312  are respectively formed with intervals e provided therebetween. For interval e, for example, e=1-3 μm. 
         [0023]    The configuration of metal  320  as shown in  FIG. 3B  has a short side of width a and a long side of length b, similarly to  FIG. 3A . Metal  320  has central portion  321  of width c and multiple slits  322  extending in the direction of the long side aligned with central portion  321 . Slits  322  each have width f. Slits  322  are respectively formed with intervals g provided therebetween. For width f and interval g, for example, f=1-5 and g=1-5 μm. 
         [0024]    The configuration of metal  330  as shown in  FIG. 3C  has a short side of width a and a long side of length b, similarly to  FIG. 3A . Metal  330  has central portion  331  of width c, multiple extending parts  332  that extend in the direction of the short side and multiple extending parts  333  that extend in the direction of the long side. Central portion  331  and extending parts  332 ,  333  of metal  330  are formed integrally. In other words, metal  330  is formed in a reticulated arrangement whereby central portion  331  and extending parts  332 ,  333  are interlinked in a network. Extending parts  332 ,  333  each have width h where, for example, h=1-5 μm. 
         [0025]    The configuration of metal  340  as shown in  FIG. 3D  is a variation of that shown in  FIG. 3A . The configuration of extending parts  312  of  FIG. 3A  is modified. Extending parts  342  shown in  FIG. 3D  have differing widths i and j. In other words, each extending part  342  has multiple wide and thin portions. For i and j, for example, i=2-5 μm, j=1-2.5 μm and i&gt;j. To sum up the metals shown in  FIGS. 3A-3D , the metals formed at the remnant regions are formed in combinations of metals having a width of 5 μm or less. 
         [0026]      FIG. 4  is an enlarged perspective view of portion C shown in  FIG. 3D . Portion C is disposed at evaluation element formation region  40  of semiconductor wafer  100 . Uppermost layer metal  33  corresponds to measurement pad  70  shown in  FIG. 3D . While not shown, lowermost layer metal  31  is formed on evaluation element  30 , which is formed at evaluation element formation region  40 , via an insulating film. Lowermost layer metal  31  is electrically connected to evaluation element  30 . Intermediate metal  32  is formed on lowermost layer metal  31  via an insulating film that is not shown. Intermediate metal  32  is electrically connected to lowermost layer metal  31  via contacts  44  or the like. Uppermost layer metal  33  is formed on intermediate metal  32  via an insulating film that is not shown. Uppermost layer metal  33  is electrically connected to intermediate metal  32  via contacts  45  or the like. Accordingly, lowermost layer metal  31 , intermediate metal  32 , and uppermost layer metal  33  are respectively electrically connected. 
         [0027]    Further, any of the metals shown in  FIGS. 3A-3D  may be used as lowermost layer metal  31 , intermediate metal  32 , and uppermost layer metal  33 , however as described in the explanation of  FIGS. 3A-3D , it is important that the metal formed on the remnant region is formed at a width of 5 μm or less. The fact that the structures shown in  FIGS. 3A-3D  are used in the metal layers in all of lowermost layer metal  31 , intermediate metal  32 , and uppermost layer metal  33  is the principal feature of the present invention. In addition, the present invention is particularly effective when measurement pads  70  are left as residue when dicing is performed in the separation process when the distance between adjacent chip regions  20 , that is, the width of evaluation element formation regions  40 , is 100 μm or less; in other words, when a dicing blade that is thinner than the length of the short side of measurement pads  70  is used. Accordingly, adopting the structure of the first embodiment of the present invention enables the occurrence of burrs (metal peeling) to be effectively reduced when the width of the evaluation element formation regions  40  is reduced and measurement pads  70  are left as residue after dicing. 
       Second Embodiment 
       [0028]    A semiconductor wafer according to a second embodiment of the present invention is explained using  FIG. 5 .  FIG. 5  is a sectional view of an evaluation element formation region  40  of the first embodiment. The second embodiment is configured with variations applied to evaluation element formation regions  40  of the first embodiment. Accordingly, explanation is limited to evaluation element formation regions  40 . As shown in  FIG. 5 , semiconductor wafer  500  according to the second embodiment has evaluation element  30  formed on an evaluation element formation region. Lowermost layer metal  31  is formed on evaluation element  30  via interlayer insulating film  501 . Intermediate metal  32  is formed on lowermost layer metal  31  via interlayer insulating film  502 . Interlayer insulating film  503  is formed on interlayer insulating film  502  and intermediate metal  32 . Further, while not shown, a protective film or the like is formed as needed on interlayer insulating film  503 . 
         [0029]    The surface of evaluation element formation region  40  of semiconductor wafer  500  corresponds to the upper surface of interlayer insulating film  503  or, in some cases, to the upper layer of the protective film. The upper surface of intermediate metal  32  is located at a lower position than the surface of evaluation element formation region  40  of semiconductor wafer  500 . In the second embodiment, there is no metal that corresponds to uppermost layer metal  33  in the first embodiment. In addition, uppermost layer metal  33  formed in the first embodiment is positioned upward of interlayer insulating film  503 . The principal feature of the second embodiment is the fact that intermediate metal  32  is exposed through interlayer insulating film  503 . Exposure of intermediate metal  32  is achieved by etching of interlayer insulating film  503 . Accordingly, intermediate metal  32  corresponds to measurement pad  70  of the first embodiment. Since intermediate metal  32 , which corresponds to measurement pad  70 , is located at a lower position with respect to the surface of semiconductor wafer  500 , it is possible to reduce the likelihood, compared to the first embodiment, of inner leads or wiring short-circuiting even when burrs (metal peeling) are generated. Further, by combination with the structure of the first embodiment, it is possible to manufacture semiconductor chips having a reduced incidence of burrs (metal peeling) and that are of good quality even in the uncommon event of burrs (metal peeling) occurring. 
         [0030]    In addition, a configuration in which lowermost layer metal  31  is exposed is conceivable as an alternative example of the second embodiment. Lowermost layer metal  31  is formed on evaluation element  30  via interlayer insulating film  501 , and interlayer insulating films  502 ,  503  are formed on interlayer insulating film  501  and lowermost layer metal  31 . Lowermost layer metal  31  is exposed through interlayer insulating films  502 ,  503 . Lowermost layer metal  31  thus corresponds to measurement pad  70 . The upper surface of lowermost layer  31  is located at a lower position than the surface of evaluation element formation region  40  of semiconductor wafer  500 . Since the distance from the upper surface of lowermost layer  31  to the surface of semiconductor wafer  500  is lengthened, it becomes possible to further reduce the likelihood of inner leads or wiring short-circuiting.