Abstract:
Design data including circuit data on a test point and information about a test mode, which has been attached to the test point, is inputted to an apparatus for designing a semiconductor integrated circuit. A design data code analysis unit in a data input unit performs the code analysis of the design data and, after the code analysis, the resulting design data is stored by a database storage unit in a storage device. A test point deletion unit receives the test mode specified from the outside and deletes data on an unnecessary test point from the design data stored in the storage device. The design data which does not include the unnecessary test point is outputted from a data output unit. Accordingly, even when the test mode is changed, there is no need to calculate the test efficiency again in response to each change or add the step of inserting a new test point.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This Non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2005-222479 filed in Japan on Aug. 1, 2005, the entire contents of which are hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a design data structure for improving test efficiency in design for testability for a semiconductor integrated circuit and to an apparatus and method for design.  
         [0003]     In design for testability for a semiconductor integrated circuit, a method has been known which improves test efficiency by adding a test point.  
         [0004]     For example, a method for improving testability comprises the steps of calculating the controllability, monitorability, and fault detection probability of each node, selecting the fault of a specified node, and adding a flip-flop as a test point when each of the respective values of the controllability, monitorability, and fault detectability does not fall within a prescribed range so that the testability has not reached a prescribed level. The technology is disclosed in, e.g., Japanese Laid-Open Patent Publication No. HEI 6-331709.  
         [0005]     In the case of using a logic BIST approach as a test mode which performs a scan test by using a random pattern, a flip-flop as a test point is added to a portion with a low probability of becoming 0 or 1 by assuming a random application of the test pattern, thereby increasing the probability of becoming 0 or 1 and compensating for a demerit resulting from the characteristic of the random pattern. Thus, the method which adds the test point to improve the transition probability has been reported. The technology is disclosed in, e.g., the document entitled “LOW OVERHEAD TEST POINT INSERTION FOR SCAN-BASED BIST”, ITC (INTERNATIONAL TEST CONFERENCE 1999), which is written by Michinobu Nakao and the other four persons.  
         [0006]     Thus, a test point is added for a purpose which differs according to a test mode.  
         [0007]     In the test point design disclosed in the patent publication or document shown above, every time the test mode changes in actual design, a transition should be made to a design flow which adds a test point as necessary. In the present situation where design resource diversion and IP design distribution have been incorporated in normal design, the repetitive transitions partly account for useless design steps.  
         [0008]      FIG. 25  shows a conventional test point design flow in which an RTL design data D 001  is inputted and logically synthesized in Logic Synthesis Step S 001  so that a net list is generated. Then, to enhance the test efficiency of a test mode D 002  specified by a computer to the net list, the test efficiency is calculated in Test Efficiency Calculation Step S 002 . From the result of calculating the test efficiency, a test-point-insertion node as a target of test point insertion necessary for enhancing the test efficiency is determined. Subsequently, in Test Point Insertion Step S 003 , insertion of a test point is performed with respect to the test-point-insertion node determined in Test Effect Calculation Step S 002 , whereby a net list D 003  including the test point is generated.  
         [0009]     In the design flow, even though the content of the input RTL design data D 001  is not changed at all or is changed only slightly, it is necessary to perform Test Efficiency Calculation Step S 002 . In IP and core design used for a plurality of semiconductor integrated circuits, after test point insertion has thus been accomplished, Step S 002  mentioned above is a step which can be omitted through design resource diversion and it can be considered that a reduction in design TAT is achievable.  
       SUMMARY OF THE INVENTION  
       [0010]     It is therefore an object of the present invention to implement design in which, even when a test mode is changed, the change is compensated for without calculating again the test efficiency in response to each change in the test mode or without adding the step of inserting a new test point based on the result of calculating the test efficiency and thereby reduce the number of design steps.  
         [0011]     To attain the object, the present invention preliminarily adds circuit data on test points applied to design for testability to data on a semiconductor integrated circuit included in input design data and also adds various information about a test mode thereto in association with the circuit data on the test points such that, when the necessity arises to change the test mode in actual design, the change in the test mode is compensated for by leaving only the test point at which given information included in the information about the test mode used thereat satisfies a specified condition and deleting an unnecessary test point at which the specified condition is not satisfied.  
         [0012]     Specifically, a design data structure for a semiconductor integrated circuit according to the present invention is a design data structure for use in design of a semiconductor integrated circuit using a computer, the design data structure comprising: circuit data on at least one test point added to a specified node in the semiconductor integrated circuit as a target of design for testability; and information about at least one test mode associated with the circuit data on the test point to validate the test point, wherein when the computer specifies the test mode which satisfies a specified condition for given information included in the information about the test mode, an unnecessary test point which does not have the given information satisfying the specified condition is invalidated.  
         [0013]     An apparatus for designing a semiconductor integrated circuit according to the present invention is an apparatus for designing a semiconductor integrated circuit using the design data structure mentioned above, the apparatus comprising: a data input unit comprising a design data code analysis unit for reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode and a database storage unit for storing a result of the analysis by the design data code analysis unit in a database; a test point deletion unit for deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from the result of the analysis stored in the database; and a circuit data output unit for outputting circuit data on the test point remaining as a result of the deletion of the unnecessary test point by the test point deletion unit and on the semiconductor integrated circuit.  
         [0014]     An apparatus for designing a semiconductor integrated circuit according to the present invention is an apparatus for designing a semiconductor integrated circuit using the design data structure mentioned above, the apparatus comprising: a data input unit comprising a design code analysis unit for reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode, a test point deletion unit for deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from a result of the analysis by the design data code analysis unit, and a database storage unit for storing a result of the deletion in a database; and a circuit data output unit for outputting the circuit data on the test point remaining as the result of the deletion of the unnecessary test point by the test point deletion unit and on the semiconductor integrated circuit which has been stored in the database by the database storage unit.  
         [0015]     An embodiment of the apparatus for designing a semiconductor integrated circuit according to the present invention further comprises: a logic synthesis unit for performing a logic synthesis process with respect to the circuit data on the semiconductor integrated circuit and on the test point which has been stored in the database and storing a result of the logic synthesis process in the database.  
         [0016]     An embodiment of the apparatus for designing a semiconductor integrated circuit according to the present invention further comprises: a logic synthesis unit for performing a logic synthesis process with respect to the circuit data on the semiconductor integrated circuit and on the test point which has been stored in the database and storing a result of the logic synthesis process in the database.  
         [0017]     A method for designing a semiconductor integrated circuit according to the present invention is a method for designing a semiconductor integrated circuit using the design data structure mentioned above, the method comprising: a circuit data read step including a design data code analysis step of reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode and a database storage step of storing a result of the analysis by the design data code analysis step in a database; a test point deletion step of deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from the result of the analysis stored in the database; and a circuit data output step of outputting circuit data on the test point remaining as a result of the deletion of the unnecessary test point by the test point deletion step and on the semiconductor integrated circuit.  
         [0018]     A method for designing a semiconductor integrated circuit according to the present invention is a method for designing a semiconductor integrated circuit using the design data structure described above, the method comprising: a circuit data read step including a design code analysis step of reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode, a test point deletion step of deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from a result of the analysis by the design data code analysis step, and a database storage step of storing a result of the deletion in a database; and a circuit data output step of outputting the circuit data on the test point remaining as the result of the deletion of the unnecessary test point in the test point deletion step and on the semiconductor integrated circuit which has been stored in the database in the database storage step.  
         [0019]     A method for designing a semiconductor integrated circuit according to the present invention is a method for designing a semiconductor integrated circuit using the design data structure mentioned above, the method comprising: a circuit data read step including a design data code analysis step of reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode and a database storage step of storing a result of the analysis by the design data code analysis step in a database; a test point deletion step of deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from the result of the analysis stored in the database; a logic synthesis step of performing a logic synthesis process with respect to circuit data on the test point remaining as a result of the deletion of the unnecessary test point in the test point deletion step and on the semiconductor integrated circuit; and a circuit data output step of outputting the circuit data on the remaining test point and on the semiconductor integrated circuit to which the logic synthesis process has been performed in the logic synthesis step.  
         [0020]     A method for designing a semiconductor integrated circuit according to the present invention is a method for designing a semiconductor integrated circuit using the design data structure mentioned above, the method comprising: a circuit data read step including a design code analysis step of reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode, a test point deletion step of deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from a result of the analysis in the design data code analysis step, and a database storage step of storing a result of the deletion in a database; a logic synthesis step of performing a logic synthesis process with respect to circuit data on the test point remaining as a result of the deletion of the unnecessary test point in the test point deletion step and stored in the database in the database storage step and on the semiconductor integrated circuit; and a circuit data output step of outputting the circuit data on the remaining test point and on the semiconductor integrated circuit to which the logic synthesis process has been performed in the logic synthesis step.  
         [0021]     In an embodiment of the design data structure for a semiconductor integrated circuit according to the present invention, the information about the test mode includes type information indicative of a type of the test mode associated with the circuit data on the test point and the computer specifies the test mode of a specified type in respect of the type information included in the information about the test mode and invalidates the unnecessary test point which does not correspond to the test mode having the type information of the specified type.  
         [0022]     In an embodiment of the method for designing a semiconductor integrated circuit according to the present invention, the information about the test mode includes type information indicative of a type of the test mode associated with the circuit data on the test point and the test point deletion step includes deleting, when the computer specifies the test mode showing a specified type in respect of the type information, the unnecessary test point for the test mode which does not include the type information of the specified type that has been specified by the computer.  
         [0023]     In an embodiment of the design data structure for a semiconductor integrated circuit according to the present invention, the information about the test mode includes effect information indicative of an effect associated with the circuit data on the test point and suited to a use purpose of the test mode and the computer specifies the test mode having a specified effect in respect of the effect information included in the information about the test mode and invalidates the unnecessary test point which does not correspond to the test mode having the effect information showing the specified effect.  
         [0024]     In an embodiment of the method for designing a semiconductor integrated circuit according to the present invention, the test point deletion step includes deleting the test point having a small effect compared with an area increase based on effect information included in the test point.  
         [0025]     In an embodiment of the design data structure for a semiconductor integrated circuit according to the present invention, the information about the test mode includes indication information associated with the circuit data on the test point and indicative of whether or not the test point may be automatically deleted and when the computer specifies indication information permitting the automatic deletion in respect of the indication information included in the information about the test mode, the unnecessary test point corresponding to the test mode including the specified indication information is invalidated.  
         [0026]     In an embodiment of the method for designing a semiconductor integrated circuit according to the present invention, the test point deletion step includes deleting the test point having a small effect compared with an area increase based on the indication information on whether or not the test point may be automatically deleted.  
         [0027]     In an embodiment of the design data structure for a semiconductor integrated circuit according to the present invention, the information about the test mode includes weighting information which is information associated with the circuit data on the test point and related to the plurality of test points in each of which it is included and when the computer specifies the test mode which does not include given weighting information in respect of the weighting information included in the information about the test mode, the unnecessary test point corresponding to the specified test mode is invalidated.  
         [0028]     In an embodiment of the method for designing a semiconductor integrated circuit according to the present invention, the information about the test mode includes weighting information which is information associated with the circuit data on the test point and related to the plurality of test points in each of which it is included and the test point deletion step includes deleting the test point corresponding to the test mode of which the weighting information does not include given weighting information specified by the computer.  
         [0029]     In an embodiment of the design data structure for a semiconductor integrated circuit according to the present invention, the computer optimizes the test point corresponding to the test mode having the given information which satisfies the specified condition indicated thereby.  
         [0030]     An apparatus for designing a semiconductor integrated circuit according to the present invention is an apparatus for designing a semiconductor integrated circuit using the design data structure mentioned above, the apparatus comprising: a data input unit comprising a design data code analysis unit for reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode and a database storage unit for storing a result of the analysis by the design data code analysis unit in a database; a test point deletion unit for deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from the result of the analysis stored in the database; a logic synthesis unit for performing a logic synthesis process involving optimization of the test point corresponding to the test mode having the given information which satisfies the specified condition indicated by the computer and storing a result of the logic synthesis process in the database; and a circuit data output unit for outputting, from the database, the circuit data on the test point remaining as a result of the deletion of the unnecessary test point by the test point deletion unit and on the semiconductor integrated circuit.  
         [0031]     An apparatus for designing a semiconductor integrated circuit according to the present invention is an apparatus for designing a semiconductor integrated circuit using the design data structure mentioned above, the apparatus comprising: a data input unit comprising a design code analysis unit for reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode, a test point deletion unit for deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from a result of the analysis by the design data code analysis unit, and a database storage unit for storing a result of the deletion in a database; a logic synthesis unit for performing a logic synthesis process involving optimization of the test point corresponding to the test mode having the given information which satisfies the specified condition indicated by the computer and storing a result of the logic synthesis process in the database; and a circuit data output unit for outputting, from the database, the circuit data on the test point remaining as the result of the deletion of the unnecessary test point by the test point deletion unit and on the semiconductor integrated circuit which has been stored in the database by the database storage unit.  
         [0032]     A method for designing a semiconductor integrated circuit according to the present invention is a method for designing a semiconductor integrated circuit using the design data structure mentioned above, the method comprising: a circuit data read step including a design data code analysis step of reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode and a database storage step of storing a result of the analysis by the design data code analysis step in a database; a test point deletion step of deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from the result of the analysis stored in the database; a logic synthesis step of performing a logic synthesis process involving optimization of the test point corresponding to the test mode having the given information which satisfies the specified condition indicated by the computer and storing a result of the logic synthesis process in the database; and a circuit data output step of outputting, from the database, the circuit data on the test point remaining as a result of the deletion of the unnecessary test point by the test point deletion step and on the semiconductor integrated circuit.  
         [0033]     A method for designing a semiconductor integrated circuit according to the present invention is a method for designing a semiconductor integrated circuit using the design data structure mentioned above, the method comprising: a circuit data read step including a design code analysis step of reading the design data structure and analyzing a code of design data included in the design data structure and composed of the circuit data on the semiconductor integrated circuit and on the test point and of the information about the test mode, a test point deletion step of deleting the unnecessary test point at which the specified condition indicated by the computer is not satisfied from a result of the analysis in the design data code analysis step, and a database storage step of storing a result of the deletion in a database; a logic synthesis step of performing a logic synthesis process involving optimization of the test point corresponding to the test mode having the given information which satisfies the specified condition indicated by the computer and storing a result of the logic synthesis process in the database; and a circuit data output step of outputting, from the database, the circuit data on the test point remaining as the result of the deletion of the unnecessary test point by the test point deletion step and on the semiconductor integrated circuit which has been stored in the database by the database storage step.  
         [0034]     An embodiment of the design data structure for a semiconductor integrated circuit according to the present invention includes positional information associated with the circuit data on the test point and showing a position of the test point, wherein the computer performs optimization of the test point corresponding to the test mode having the given information which satisfies the specified condition by using the positional information on the test point.  
         [0035]     An embodiment of the method for designing a semiconductor integrated circuit according to the present invention includes positional information associated with the circuit data on the test point and showing a position of the test point, wherein the logic synthesis step includes performing the logic synthesis process involving optimization through merging of the test point corresponding to the test mode having the given information which satisfies the specified condition by using the positional information on the test point.  
         [0036]     In an embodiment of the design data structure for a semiconductor integrated circuit according to the present invention, the information about the test mode includes clock frequency information associated with the circuit data on the test point and the computer performs optimization of the test point based on the clock frequency information.  
         [0037]     In an embodiment of the method for designing a semiconductor integrated circuit according to the present invention, the information about the test mode includes clock frequency information associated with the circuit data on the test point and the logic synthesis step includes performing the logic synthesis process involving optimization through sharing of a clock source based on the clock frequency information.  
         [0038]     In an embodiment of the method for designing a semiconductor integrated circuit according to the present invention, the information about the test mode includes logic synthesis constraint information associated with the circuit data on the test point and the computer performs optimization of the test point based on the logic synthesis constraint information.  
         [0039]     In an embodiment of the method for designing a semiconductor integrated circuit according to the present invention, the information about the test mode is associated with the circuit data on the test point and includes logic synthesis constraint information on the test point and the logic synthesis step includes performing the logic synthesis process involving optimization of timing based on the logic synthesis constraint information.  
         [0040]     Thus, one aspect of the invention is the design data structure for a semiconductor integrated circuit which includes not only the circuit data on the semiconductor integrated circuit but also the circuit data on the test point and the information about the test mode in association with the test point. This obviates the necessity to perform the step of calculating the test efficiency and insert a necessary test point every time the test mode is changed, allows compensation for the change only by judging and deleting an unnecessary test point based on a specified condition for given information in the information about the test mode which is included in the test point, and thereby allows a reduction in the number of design steps.  
         [0041]     Another aspect of the invention is the apparatus for designing a semiconductor integrated circuit which receives the design data on a semiconductor integrated circuit and a specified test mode from the outside such that the design data code analysis unit of the data input unit performs the code analysis of the design code and the data storage unit stores the result of the analysis in the storage device. In the test point deletion unit, an unnecessary test point is deleted based on the test mode received from the outside so that the design data from which the unnecessary test point has been deleted is outputted from the data output unit.  
         [0042]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which is implemented by using the apparatus for designing a semiconductor integrated circuit.  
         [0043]     In accordance with the present aspects of the invention, it becomes possible to generate the design data for a semiconductor integrated circuit which includes only a necessary test point by omitting the step of calculating test efficiency calculation and inserting a test point and thereby reduce the number of design steps.  
         [0044]     Yet another aspect of the invention is the apparatus for designing a semiconductor integrated circuit which has the test point deletion unit provided in the data input unit so that the design data from which the unnecessary test point has been deleted by the test point deletion unit is stored in the storage device.  
         [0045]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which implements the storage of the design data in the storage device after deleting the unnecessary test point by using the apparatus for designing a semiconductor integrated circuit.  
         [0046]     In contrast to the above-mentioned aspects of the invention, the apparatus and method for designing a semiconductor integrated circuit according to the present aspects of the invention delete the unnecessary test point before storing the information in the storage device. Accordingly, the test point once deleted cannot be recovered any more but the advantage is offered that a used space in the memory is reduced.  
         [0047]     Yet another aspect of the invention is the apparatus for designing a semiconductor integrated circuit in which the logic synthesis is performed in the logic synthesis unit after the process in the test point deletion unit.  
         [0048]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which implements the logic synthesis process after the deletion of the unnecessary test point by using the apparatus for designing a semiconductor integrated circuit.  
         [0049]     In accordance with the present aspects of the invention, it becomes possible to omit the step of calculating the test efficiency and inserting the test point and thereby generate gate-level design data for a semiconductor integrated circuit which includes only a necessary test point by using the design data structure.  
         [0050]     Yet another aspect of the invention is the apparatus for designing a semiconductor integrated circuit in which logic synthesis is performed in the logic synthesis unit after the process in the database storage unit.  
         [0051]     Still another aspect of the present is the method for designing a semiconductor integrated circuit which is implemented by using the apparatus for designing a semiconductor integrated circuit.  
         [0052]     In contrast to the above-mentioned aspect of the invention, the apparatus and method for designing a semiconductor integrated circuit according to the present aspects of the invention delete the unnecessary test point before storing the information in the storage device. Accordingly, the test point once deleted cannot be recovered any more but the advantage is offered that a used space in the memory is reduced.  
         [0053]     Yet another aspect of the invention is the design data structure for a semiconductor integrated circuit which has type information on the test mode for validating the test point as information for invalidating an unnecessary test point for the specified test mode or rendering it deletable.  
         [0054]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which deletes the unnecessary test point by using the type information on the test mode for validating the test point included in the design data structure for a semiconductor integrated circuit.  
         [0055]     In accordance with the present aspects of the invention, it becomes possible to delete the test point which is valid for a test mode other than the specified one.  
         [0056]     Yet another aspect of the invention is the design data structure for a semiconductor integrated circuit which has the effect information on the test point as information for invalidating the unnecessary test point for the specified test mode or rendering it deletable.  
         [0057]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which deletes the unnecessary test point by using the effect information on the test point included in the design data structure for a semiconductor integrated circuit.  
         [0058]     Since the present aspect of the invention allows the deletion of the test point having a small effect even though it is valid for the specified test mode, it becomes possible to reduce the circuit area compared with the method for designing a semiconductor integrated circuit according to the above-mentioned aspect.  
         [0059]     Yet another aspect of the invention is the design data structure for a semiconductor integrated circuit which has automatic deletion prohibition information on the test point as information for invalidating the unnecessary test point for the specified test mode or rendering it deletable.  
         [0060]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which can prevent the deletion of the test point even when it is judged to be unnecessary by using the automatic deletion prohibition information included in the test point.  
         [0061]     Even when the test point inserted to improve the test quality is less effective as the test point, the present aspects of the invention allow the test point to be left without deleting it.  
         [0062]     Yet another aspect of the invention is the design data structure for a semiconductor integrated circuit which has the weighting information related to the plurality of test points in each of which it is included as information for invalidating the unnecessary test point for the specified test mode or rendering it deletable.  
         [0063]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which deletes the unnecessary test point by using the weighting information related to the plurality of test points in each of which it is included.  
         [0064]     In accordance with the present aspects of the invention, it becomes possible to evaluate the effect of the plurality of test points which is achievable when they are used in combination and thereby efficiently leave the test points.  
         [0065]     Yet another aspect of the invention is the design data structure for a semiconductor integrated circuit which comprises a test point for one or a plurality of test modes for the semiconductor integrated circuit to allow effective use thereof and circuit optimization therefor, wherein the test point includes information for invalidating the unnecessary test point for a specified test mode or rendering it deletable and information for optimizing the test point. This provides the design data structure for a semiconductor integrated circuit which has the optimization function for invalidating the unnecessary test point in accordance with the specified test mode. This allows further circuit optimization compared with the design data structure according to the above-mentioned aspect.  
         [0066]     Still another aspect of the invention is the apparatus for designing a semiconductor integrated circuit comprising the process of optimizing a test point circuit as the process in the logic synthesis unit.  
         [0067]     Yet another aspect of the invention is the method for designing a semiconductor integrated circuit which is implemented by using the apparatus for designing a semiconductor integrated circuit.  
         [0068]     In accordance with the present aspects of the invention, it becomes possible to allow the method for designing a semiconductor integrated circuit using the apparatus for designing a semiconductor integrated circuit to perform the process of optimizing the test point circuit.  
         [0069]     Still another aspect of the invention is the apparatus for designing a semiconductor integrated circuit which performs the process of optimizing the test point circuit as the process in the logic synthesis unit.  
         [0070]     Yet another aspect of the invention is the method for designing a semiconductor integrated circuit which is implemented by using the apparatus for designing a semiconductor integrated circuit.  
         [0071]     The present aspect of the invention allows the method for designing a semiconductor integrated circuit using the apparatus for designing a semiconductor integrated circuit to perform the process of optimizing the test point circuit by using the design data structure for a semiconductor integrated circuit.  
         [0072]     Yet another aspect of the invention is the design data structure for a semiconductor integrated circuit which has positional information on the test point as information for optimizing the test point in accordance with the specified test mode.  
         [0073]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which allows a mergeable test point to be merged by using the positional information on the test point included in the designing data structure for a semiconductor integrated circuit.  
         [0074]     In accordance with the present aspects of the invention, it becomes possible to reduce the circuit area without reducing the effect of the test point.  
         [0075]     Yet another aspect of the invention is the design data structure for a semiconductor integrated circuit which has clock frequency information on the test point as information for optimizing the test point in accordance with the specified test mode.  
         [0076]     Still another aspect of the invention is the method for designing a semiconductor integrated circuit which allows a sharable clock source to be shared by using the clock frequency information for controlling the test point included in the design data structure for a semiconductor integrated circuit.  
         [0077]     In accordance with the present aspects of the invention, it becomes possible to simplify the test point control circuit and perform easy timing adjustment of the clock connected to the test point.  
         [0078]     Yet another aspect of the invention is the design data structure for a semiconductor integrated circuit which has timing constraint information on the test point as information for optimizing the test point in accordance with the specified test mode.  
         [0079]     The present aspect of the invention also allows timing optimization of the test point circuit by using the timing constraint information on the test point included in the design data structure for a semiconductor integrated circuit.  
         [0080]     In accordance with the present aspect of the invention, it becomes possible to perform easy timing optimization of the entire circuit including the test point. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0081]      FIG. 1  is a circuit diagram showing circuit data on a semiconductor integrated circuit including test points for one or a plurality of test modes according to a first embodiment of the present invention;  
         [0082]      FIG. 2  is a view showing information on the test points for the semiconductor integrated circuit including the test points for the one or plurality of test modes according to the first embodiment;  
         [0083]      FIG. 3  is a view showing the information on the test points for the semiconductor integrated circuit including the test points for the one or plurality of test modes according to the first embodiment;  
         [0084]      FIG. 4  is a view showing an apparatus for designing the semiconductor integrated circuit according to the first embodiment;  
         [0085]      FIG. 5  is a view showing an apparatus for designing a semiconductor integrated circuit according to a second embodiment of the present invention;  
         [0086]      FIG. 6  is a view showing an apparatus for designing a semiconductor integrated circuit according to a third embodiment of the present invention;  
         [0087]      FIG. 7  is a view showing an apparatus for designing a semiconductor integrated circuit according to a fourth embodiment of the present invention;  
         [0088]      FIG. 8  is a flow chart diagram showing a method for designing the semiconductor integrated circuit according to the first embodiment;  
         [0089]      FIG. 9  is a flow chart diagram showing a method for designing a semiconductor integrated circuit according to the second embodiment;  
         [0090]      FIG. 10  is a flow chart diagram showing a method for designing a semiconductor integrated circuit according to the third embodiment;  
         [0091]      FIG. 11  is a flow chart diagram showing a method for designing a semiconductor integrated circuit according to the fourth embodiment;  
         [0092]      FIG. 12  is a circuit diagram showing data on a semiconductor integrated circuit obtained by deleting an unneeded one of the test points from the semiconductor integrated circuit of  FIG. 1 ;  
         [0093]      FIG. 13  is a circuit diagram showing data for a semiconductor integrated circuit obtained by deleting an unneeded one of the test points from the semiconductor integrated circuit of  FIG. 1 ;  
         [0094]      FIG. 14  is a view showing an apparatus for designing a semiconductor integrated circuit according to a fifth embodiment of the present invention;  
         [0095]      FIG. 15  is a view showing an apparatus for designing a semiconductor integrated circuit according to a sixth embodiment of the present invention;  
         [0096]      FIG. 16  is a flow chart diagram showing a method for designing a semiconductor integrated circuit according to the fifth embodiment;  
         [0097]      FIG. 17  is a flow chart diagram showing a method for designing a semiconductor integrated circuit according to the sixth embodiment;  
         [0098]      FIG. 18  is a circuit diagram showing circuit data on a semiconductor integrated circuit including test points for one or a plurality of test modes according to the fifth embodiment;  
         [0099]      FIG. 19  is a view showing information on the test points in the semiconductor integrated circuit including the test points for the one or plurality of test modes according to the fifth embodiment;  
         [0100]      FIG. 20  is a view showing information on the test points in the semiconductor integrated circuit including the test points for the one or plurality of test modes according to the fifth embodiment;  
         [0101]      FIG. 21  is a view showing coordinates in positional information on the test points in the semiconductor integrated circuit including the test points for the one or plurality of test modes according to the fifth embodiment;  
         [0102]      FIG. 22  is a circuit diagram showing data on a semiconductor integrated circuit resulting from the merging of a mergeable one of the test points in the semiconductor integrated circuit of  FIG. 18 ;  
         [0103]      FIG. 23  is a circuit diagram showing circuit data for a semiconductor integrated circuit resulting from the sharing of a sharable clock input among the test points in the semiconductor integrated circuit of  FIG. 18 ;  
         [0104]      FIG. 24  is a circuit diagram showing data on a semiconductor integrated circuit obtained by deleting the unneeded one of the test points from the semiconductor integrated circuit of  FIG. 1 ; and  
         [0105]      FIG. 25  is a flow chart diagram of conventional test point design. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0106]     Referring to the drawings, the embodiments of the present invention will be described herein below in detail.  
       Embodiment 1  
       [0107]      FIG. 1  shows circuit data on a semiconductor integrated circuit including test points for implementing a test mode for design for testability (hereinafter simply referred to as circuit data) according to the first embodiment of the present invention.  FIGS. 2 and 3  show information (information about the test mode) attached to circuit data on the test points (hereinafter simply referred to as the test points) that has been added to the circuit data on the semiconductor integrated circuit. As shown in  FIG. 1 , at least one test point is added to a specified node of which design for testability is required in the semiconductor integrated circuit.  
         [0108]      FIG. 4  shows an apparatus for designing the semiconductor integrated circuit according to the first embodiment.  FIG. 8  is a flow chart diagram showing a method for designing the semiconductor integrated circuit by using the apparatus for designing the semiconductor integrated circuit. The circuit data, the test points in the circuit data, and the information attached to the test points are combined to provide design data.  
         [0109]     The group of combinational circuits shown in  FIG. 1  include: six combinational circuits cc 1  to cc 6 ; two OR circuits or 2  and or 4 ; eleven AND circuits and 1  to and 11 ; a selector sel 1 ; four flip-flops ff 1  to ff 4 ; and six input terminals in 1 , in 2 , and clk 1  to clk 4 .  
         [0110]     A description will be given first to the circuit structure between the combinational circuits cc 1  and cc 2  in the semiconductor integrated circuit shown in  FIG. 1 . To each of the inputs of the AND circuits and 1  to and 3 , the output of the combinational circuit cc 1  is connected. To the inputs of the AND circuit and 4 , the respective outputs of the AND circuits and 2  and and 3  are connected. To the clock input of the flip-flop ff 1 , the input terminal clk 1  is connected. To the inputs of the OR circuit or 2 , the output of the AND circuit and 4 , the output of the flip-flop ff 1 , and the output of the flip-flop ff 4  are connected.  
         [0111]     To the inputs of the AND circuit and 5 , the output of the AND circuit and 1  and the output of the OR circuit or 2  are connected. To the node between the output of the AND circuit and 4  and one of the inputs of the AND circuit and 5 , a test point tp 1  composed of the flip-flop ff 1 , the OR circuit or 2 , and the input terminal clk 1  is added. A test point tp 4  composed of the flip-flop ff 4 , the OR circuit or 2 , and the input terminal clk 4  is also added to the same node.  
         [0112]     A description will be given next to the circuit structure between the combinational circuits cc 3  and cc 4 . The selector sel 1  is controlled by the input terminal in 1  such that, when the input value of the input terminal in 1  is 1, the input terminal in 2  is selected and that, when the input value thereof is 0, the output value of the combinational circuit cc 3  is selected. To the clock input of the flip-flop ff 2 , the input terminal clk 2  is connected. To the input of the combinational circuit cc 4 , the output of the selector sel 1  is connected. To the node between the output of the combinational circuit cc 3  and the 0-input of the selector sel 1 , a test point tp 2  composed of the flip-flop ff 2  and the input terminal clk 2  is added.  
         [0113]     Subsequently, a description will be given to the circuit structure between the combinational circuits cc 5  and cc 6 . To each of the respective inputs of the AND circuits and 6 , and 7 , and and 8 , the output of the combinational circuit cc 5  is connected. To the inputs of the AND circuit and 9 , the respective outputs of the AND circuits and 7  and and 8  are connected. To the clock input of the flip-flop ff 3 , the input terminal clk 3  is connected.  
         [0114]     To the inputs of the OR circuit or 4 , the output of the AND circuit and 9  and the output of the flip-flop ff 3  are connected. To the inputs of the AND circuits and 10 , the output of the AND circuit and 6  and the output of the OR circuit or 4  are connected. To the inputs of the AND circuit and 11 , the output of the combinational circuit cc 5  and the output of the AND circuit and 10  are connected. To the input of the combinational circuit cc 6 , the output of the AND circuit and 11  is connected. To the node between the output of the AND circuit and 9  and one of the inputs of the AND circuit and 10 , a test point tp 3  composed of the flip-flop ff 3 , the input terminal clk 3 , and the OR circuit or 4  is added.  
         [0115]      FIG. 2  shows information attached to the test points tp 1  and tp 2  added to the circuit data.  FIG. 3  shows information attached to the test points tp 3  and tp 4  added to the circuit data. Each of the test points tp 1  to tp 4  holds “Test Mode” and “Positional Information” as information (information about a test mode) associated therewith. For each “Test Mode”, information composed of the “Type”, “Use Purpose”, “Effect”, “Clock Frequency”, “Logic Synthesis Constraint”, “Deletable/Undeletable”, “Effect at Test Points”, and “List of Test Points” is also held.  
         [0116]     A description will be given next to the test points tp 1  to tp 4  in the circuit data shown in  FIG. 1 . The type of the test mode which validates the test point tp 1  is “Logic BIST” and no “Positional Information” is held. In “Logic BIST” as the test mode for the test point tp 1 , “Use Purpose” is “Improvement in Transition Probability” and “Effect” is “0.117% Improvement in Transition Probability”. In “Logic BIST” as the test mode for the test point tp 1 , “Clock Frequency” is 200 MHz, “Logic Synthesis Constraint” is “None”, “Deletable/Undeletable” is “Deletable”, “Effect at Test Points” is “0.191% Improvement in Transition Probability”, and “List of Test Points” related thereto is “{tp4}”. In the information shown in  FIG. 2 , “Effect at Test Points” indicates test efficiency improved by combining a plurality of test points and the “0.191% Improvement in Transition Probability” mentioned above improves the test efficiency. The test point related to the present test point tp 1  for the improved test efficiency is the test point tp 4  shown above in “List of Test Points”. “Effect at Test Points” shown herein is “Weighting Information Related to Test Points” 
         [0117]     The types of the test modes which validate the test point tp 2  are “Scan Test” and “Logic BIST” and no “Positional Information” is held. In “Scan Test” as one of the test modes for the test point tp 2 , “Use Purpose” is “Improvement in Monitorability” and “Effect” is “10 Nodes”. In “Scan Test” as the test mode for the test point tp 2 , “Clock Frequency” is “30 MHz”, “Logic Synthesis Constraint” is “False Path”, “Deletable/Undeletable” is “Undeletable”, “Effect at Test Points” is “None”, and “List of Test Points” related thereto is not held. In “Logic BIST” as the other test mode for the test point tp 2 , “Use Purpose” is “Improvement in Monitorability” and “Effect” is “10 Nodes”. In “Logic BIST” as the test mode for the test point tp 2 , “Clock Frequency” is “200 MHz”, “Logic Synthesis Constraint” is “None”, “Deletable/Undeletable” is “Undeletable”, “Effect at Test Points” is “None”, and “List of Test Points” related thereto is not held.  
         [0118]     The type of the test mode which validates the test point tp 3  is “Scan Test” and no “Positional Information” is held. In “Scan Test” as the test mode for the test point tp 3 , “Use Purpose” is “Reduction in Test Pattern” and “Effect” is “30 Pattern Reduction”. In “Scan Test” as the test mode for the test point tp 3 , “Clock Frequency” is “30 MHz”, “Logic Synthesis Constraint” is “False Path”, “Deletable/Undeletable” is “Deletable”, “Effect at Test Points” is “None”, and “List of Test Points” related thereto is not held.  
         [0119]     The type of the test mode which validates the test point tp 4  is “Logic BIST” and no “Positional Information” is held. In “Logic BIST” as the test mode for the test point tp 4 , “Use Purpose” is “Improvement in Transition Probability” and “Effect” is “0.117% Improvement in Transition Probability”. In “Logic BIST” as the test mode for the test point tp 4 , “Clock Frequency” is “200 MHz”, “Logic Synthesis Constraint” is “None”, “Deletable/Undeletable” is “Deletable”, “Effect at Test Points” is “0.191% Improvement in Transition Probability”, and “List of Test Points” related thereto is “{tp1}”.  
         [0120]     As shown in  FIG. 4 , the apparatus for designing the semiconductor integrated circuit device is composed of: a data input unit K 101  for reading design data D 101  as input data; a storage device  700  for storing the read data; a test point deletion unit K 104  for deleting an unnecessary test point corresponding only to an unspecified test mode for a test mode D 102  as input data about a test mode specified by a computer; and a data output unit K 105  for retrieving the design data from the storage device  700  and outputting it. The data input unit K 101  is composed of: a code analysis unit K 102  for analyzing the code of the design data; and a database storage unit K 103  for storing the result of the analysis in the storage device  700 . The input data about the test mode specified by the computer indicates data showing specified conditions for given information included in the information about the test mode shown above. Specifically, the given information includes “Positional Information” and information composed of “Type”, “Use Purpose”, “Effect”, “Clock Frequency”, “Logic Synthesis Constraint”, “Deletable/Undeletable”, “Effect at Test Points”, and “List of Test Points” which is included in “Test Mode” of the information about the test mode. The specified conditions indicate “Improvement in Transition Probability” as “Use Purpose”, “0.117% Improvement in Transition Probability” as “Effect” and the like shown in  FIGS. 2 and 3  and also include “Logic BIST” as “Type”.  
         [0121]      FIG. 8  is a flow chart diagram showing a procedure for test point design according to the first embodiment.  
         [0122]     First, in the flow chart, the design data D 101  (design data structure) composed of the circuit data on the semiconductor integrated circuit including the test points for the one or plurality of test modes and the information (information about the test mode) attached to the test points in the circuit data is inputted. In Data Read Step S 101 , the reading of the design data D 101  is performed. The reading in Data Read Step S 101  is performed in such a manner that the code analysis of the design data D 101  is performed first in Code Analysis Step S 102  and the result of the analysis is stored in a database in Database Storage Step S 103 . At this time, the information on the circuit data and the information attached to the test points are entirely analyzed and stored in the database.  
         [0123]     When “Logic BIST” (specified type) indicative of the type is specified as the test mode D 102  by the computer, any test point for which “Logic BIST” is not written as “Test Mode” in the information attached to the test point in the circuit data stored in the database is deleted in Test Point Deletion Step S 104  so that the test point tp 3  is deleted in the present embodiment. Consequently, the flip-flop ff 3 , the OR circuit or 4 , and the input terminal clk 3  are deleted from the circuit data and the output of the AND circuit and 9  is connected to each of the inputs of the AND circuit and 10  so that the design data D 104  outputted in Data Output Step S 105  becomes the circuit shown in  FIG. 12 .  
         [0124]     When “Logic BIST” is specified in the test mode D 102  and a specified condition such that that “Effect at 1 Test Point” is “0.15%-or-More Improvement in Transition Probability” (Specified Effect) is inputted, any test point for which “Logic BIST” is not written as “Test Mode” in the information attached to the test point is deleted in Test Point Deletion Step S 104  so that the test point tp 3  is deleted. Even when the type of “Test Mode” is “Logic BIST”, any test point of which “Effect” in the information attached to the test point is a less-than-0.15% improvement in transition probability is deleted so that the test points tp 1  and tp 4  are deleted and the output design data D 103  becomes the circuit shown in  FIG. 13 . What results is a structure in which, in contrast to the circuit data in the input design data D 101 , each of the inputs of the AND circuit and 5  is connected to the output of the AND circuit and 4  and each of the inputs of the AND circuit and 10  is connected to the output of the AND circuit and 9 .  
         [0125]     When “Scan Test” is specified as the test mode D 102  mentioned above and when “Number of Monitorable Nodes is 15 or More” is specified, any test point of which “Test Mode” is other than “Scan Test” is deleted so that the test points tp 1  and tp 4  are deleted. Of the test points tp 2  and tp 3  of each of which “Test Mode” is “Scan Test”, the test point tp 2  of which “Use Purpose” is “Number of Monitorable Nodes is 15 or Less” is supposed to be deleted but its “Deletable/Undeletable” as indication information on whether or not the test point may be automatically deletable is “Undeletable” so that the test point tp 2  remains without being deleted. As a result, the output design data D 103  has a structure as shown in  FIG. 24  in which, in contrast to the circuit data in the input design data D 101 , each of the inputs of the AND circuit and 5  is connected to the output of the AND circuit and 4 .  
         [0126]     When “Logic BIST” is specified as the test mode D 102  mentioned above and a specified condition such that “Effect at Test Points” is “0.18%-or-More Improvement in Transition Probability” (specified effect) is inputted, any test point for which “Logic BIST” is not written as “Test Mode” in the information attached to the test point is deleted so that the test point tp 3  is deleted. Even when “Test Mode” is “Logic BIST”, any test point of which “Effect at Test Points” is a 0.18-or-less improvement in transition probability in the information attached to the test point is deleted. Since “Effect at Test Points” in the information held by each of the test points tp 1  and tp 3  remaining without being deleted is 0.191, the test points tp 1  and tp 3  remain without being deleted and the circuit data in the output design data becomes the circuit design shown in  FIG. 11 .  
         [0127]     When “Logic BIST” is specified as the test mode D 102  mentioned above and a specified condition such that “Effect at Test Points” is “0.20%-or-More Improvement in Transition Probability” is inputted, the test points tp 1  and tp 3  are deleted since “Effect at Test Points” in the information held by each of the test points tp 1  and tp 3  is 0.191. As a result, the circuit data in the output design data becomes the circuit data shown in  FIG. 13 .  
       Embodiment 2  
       [0128]      FIG. 5  shows an apparatus for designing a semiconductor integrated circuit according to the second embodiment of the present invention.  FIG. 9  is a flow chart diagram showing a procedure for designing a semiconductor integrated circuit by using the apparatus for designing a semiconductor integrated circuit.  
         [0129]     As shown in  FIG. 5 , the apparatus for designing a semiconductor integrated circuit device is composed of: a data input unit K 101  for reading design data D 101  as input data; a storage device  700  for storing the read data; and a data output unit K 105  for outputting design data D 103 . The data input unit K 101  is composed of: a code analysis unit K 102  for analyzing the code of the design data; a test point deletion unit K 104  for deleting an unnecessary test point for the test mode inputted as a test mode D 102 ; and a database storage unit K 103  for storing design data after the deletion of the test point in the storage device  700 .  
         [0130]      FIG. 9  is a flow chart diagram showing a procedure for test point design according to the second embodiment.  
         [0131]     First, in the flow chart, circuit data on a semiconductor integrated circuit including test points for one or a plurality of test modes is inputted as the design data D 101  and information attached to the test points in the circuit data is inputted as the test mode D 102 . In Data Read Step S 101 , the reading of the design data D 101  is performed. The reading is performed in such a manner that the code analysis of the design data D 101  is performed first in Code Analysis Step S 102 . When “Logic BIST”, e.g., is specified as the test mode D 102 , any test point for which “Logic BIST” is not written as “Test Mode” in the information attached to the test point in the circuit data is deleted in Test Point Deletion Step S 104 . As a result, circuit data obtained by deleting the test point tp 3  from the circuit data is stored in a database in Database Storage Step S 103 . Then, in Data Output Step S 105 , the circuit data on the circuit shown in  FIG. 12  is outputted as the design data D 103 .  
         [0132]     The second embodiment is different from the first embodiment in that Test Point Deletion Step S 104  is provided before Database Storage Step S 103 . As a result, the test point deleted in Test Point Deletion Step S 104  is not stored in the database and therefore cannot be recovered. However, a used space in the memory of the storage device can be reduced.  
       Embodiment 3  
       [0133]      FIG. 6  shows an apparatus for designing a semiconductor integrated circuit according to the third embodiment of the present invention.  FIG. 10  is a flow chart diagram showing a procedure for designing a semiconductor integrated circuit by using the apparatus for designing a semiconductor integrated circuit of  FIG. 6 . The apparatus for designing a semiconductor integrated circuit and the flow chart diagram showing the design procedure according to the present embodiment are basically the same as those described in the first embodiment so that a description will be given to portions different from those in the apparatus for designing the semiconductor integrated circuit and the flow chart diagram showing the design procedure described in the first embodiment.  
         [0134]     The apparatus for designing a semiconductor integrated circuit shown in  FIG. 6  is different from that described in the first embodiment in that a logic synthesis unit K 106  is provided therein. The provision of the logic synthesis unit K 106  allows the logic synthesis of the design data stored in the storage device  700  to be performed in Logic Synthesis Step S 106 . When the input design data D 101  is on the RT level, therefore, it becomes possible to output the design data D 104  as a net list on the gate level.  
       Embodiment 4  
       [0135]      FIG. 7  shows an apparatus for designing a semiconductor integrated circuit according to the fourth embodiment of the present invention.  FIG. 11  is a flow chart diagram showing a procedure for designing a semiconductor integrated circuit by using the apparatus for designing a semiconductor integrated circuit. The apparatus for designing a semiconductor integrated circuit and the flow chart diagram showing the design procedure according to the present embodiment are basically the same as those described in the second embodiment so that a description will be given to portions different from those in the apparatus for designing a semiconductor integrated circuit and the flow chart diagram showing the design procedure described in the second embodiment.  
         [0136]     The apparatus for designing a semiconductor integrated circuit shown in  FIG. 7  is different from that described in the second embodiment in that a logic synthesis unit K 106  is provided therein. The provision of the logic synthesis unit K 106  allows logic synthesis to be performed in Logic Synthesis Step S 106 . When the input design data D 101  is on the RT level, therefore, it becomes possible to output the design data D 104  as a net list on the gate level.  
       Embodiment 5  
       [0137]      FIG. 14  shows an apparatus for designing a semiconductor integrated circuit according to the fifth embodiment of the present invention.  FIG. 16  is a flow chart diagram showing a procedure for designing a semiconductor integrated circuit using the apparatus for designing a semiconductor integrated circuit. The apparatus for designing a semiconductor integrated circuit and the flow chart diagram showing the design procedure according to the present embodiment are basically the same as those described in the third embodiment so that a description will be given to portions different from those in the apparatus for designing a semiconductor integrated circuit and the flow chart diagram showing the design procedure described in the third embodiment.  
         [0138]     The apparatus for designing a semiconductor integrated circuit shown in  FIG. 14  is different from that described in the third embodiment in that, in contrast to the apparatus for designing a semiconductor integrated circuit described in the third embodiment which has the logic synthesis unit K 106 , the apparatus for designing a semiconductor integrated circuit according to the present embodiment has a logic synthesis unit K 107  including a test point optimization process for performing the optimization of the test points during the logic synthesis process. As shown in  FIG. 16 , the provision of the logic synthesis unit K 107  including the test point optimization process allows the circuit area optimization and timing optimization of a test point circuit to be performed in Logic Synthesis Step S 107  including the test point optimization process and thereby allows the design data D 104  as a net list on the multi-gate level to be outputted.  
         [0139]      FIG. 18  shows circuit data on a semiconductor integrated circuit including test points for one or a plurality of test modes according to the fifth embodiment.  FIG. 19  shows information attached to the test points in the circuit data.  
         [0140]     The group of combinational circuits shown in  FIG. 18  include eight combinational circuits cc 7  to cc 14 , four selectors sel 2  to sel 5 , four flip-flops ff 5  to ff 8 , and twelve input terminals in 3  to in 10  and clk 5  to clk 8 .  
         [0141]     A description will be given first to the circuit structure between the combinational circuits cc 7  and cc 8  in the semiconductor integrated circuit shown in  FIG. 18 . The selector sel 2  is controlled by the input terminal in 3  such that, when the input value of the input terminal in 3  is 1, the input terminal in 4  is selected and that, when the input value thereof is 0, the output value of the combinational circuit cc 7  is selected. To the clock input of the flip-flop ff 5 , the input terminal clk 5  is connected. To the node between the output of the combinational circuit cc 7  and the 0-input of the selector sel 2 , a test point tp 5  composed of the flip-flop ff 5  and the input terminal clk 5  has been added.  
         [0142]     A description will be given next to the circuit structure between the combinational circuits cc 9  and cc 10 . The selector sel 3  is controlled by the input terminal in 5  such that, when the input value of the input terminal in 5  is 1, the input terminal in 6  is selected and that, when the input value thereof is 0, the output value of the combinational circuit cc 9  is selected. To the clock input of the flip-flop of the flip-flop ff 6 , the input terminal clk 6  is connected. To the node between the output of the combinational circuit cc 9  and the 0-input of the selector sel 3 , a test point tp 6  composed of the flip-flop ff 6  and the input terminal clk 6  has been added.  
         [0143]     A description will be given next to the circuit structure between the combinational circuits cc 11  and cc 12 . The selector sel 4  is controlled by the input terminal in 7  such that, when the input value of the input terminal in 7  is 1, the input terminal in 8  is selected and that, when the input value thereof is 0, the output value of the combinational circuit cc 1  is selected. To the clock input of the flip-flop ff 7 , the input terminal clk 7  is connected. To the node between the output of the combinational circuit cc 11  and the 0-input of the selector sel 4 , a test point tp 7  composed of the flip-flop ff 7  and the input terminal clk 7  has been added.  
         [0144]     Subsequently, a description will be given to the circuit structure between the combinational circuits cc 13  and cc 14 . The selector sel 5  is controlled by the input terminal in 9  such that, when the input value of the input terminal in 9  is 1, the input terminal in 10  is selected and that, when the input value thereof is 0, the output value of the combinational circuit cc 13  is selected. To the clock input of the flip-flop ff 8 , the input terminal clk 8  is connected. To the node between the output of the combinational circuit cc 13  and the 0-input of the selector sel 5 , a test point tp 8  composed of the flip-flop ff 8  and the input terminal clk 8  has been added.  
         [0145]      FIG. 19  shows information attached to the test points tp 5  and tp 6  added to the circuit data.  FIG. 20  shows information attached to the test points tp 7  and tp 8  added to the circuit data. Each of the test points tp 5  to tp 8  holds “Test Mode” and “Positional Information” as information (information about the test mode) associated therewith. Each “Test Mode” holds information composed of “Use Purpose”, “Effect”, “Clock Frequency”, “Logic Synthesis Constraint”, “Deletable/Undeletable”, “Effect at Test Points”, and “List of Test Points”.  
         [0146]     The test mode for the test point tp 5  is “Scan Test” and holds the coordinates (2,1) as “Positional Information”. In “Scan Test” as the test mode for the test point tp 5 , “Use Purpose” is “Improvement in Monitorability” and “Effect” is “10 Nodes”. In “Scan Test” as the test mode for the test point tp 5 , “Clock Frequency” is “30 MHz”, “Logic Synthesis Constraint” is “None”, “Deletable/Undeletable” is “Deletable”, and “Effect at Test Points” is “None”.  
         [0147]     The test mode for the test point tp 6  is “Scan Test” and holds the coordinates (3,2) as “Positional Information”. In “Scan Test” as the test mode for the test point tp 6 , “Use Purpose” is “Improvement in Monitorability” and “Effect” is “11 Nodes”. In “Scan Test” as the test mode for the test point tp 6 , “Clock Frequency” is “30 MHz”, “Logic Synthesis Constraint” is “False Path”, “Deletable/Undeletable” is “Deletable”, and “Effect at Test Points” is “None”.  
         [0148]     The test mode for the test point tp 7  is “Scan Test” and holds the coordinates (5,6) as “Positional Information”. In “Scan Test” as the test mode for the test point tp 7 , “Use Purpose” is “Improvement in Monitorability” and “Effect” is “11 Nodes”. In “Scan Test” as the test mode for the test point tp 7 , “Clock Frequency” is “30 MHz”, “Logic Synthesis Constraint” is “None”, “Deletable/Undeletable” is “Deletable”, and “Effect at Test Points” is “None”.  
         [0149]     The test mode for the test point tp 8  is “Scan Test” and holds the coordinates (2,2) as “Positional Information”. In “Scan Test” as the test mode for the test point tp 8 , “Use Purpose” is “Improvement in Monitorability” and “Effect” is “10 Nodes”. In “Scan Test” as the test mode for the test point tp 8 , “Clock Frequency” is “200 MHz”, “Logic Synthesis Constraint” is “None”, “Deletable/Undeletable” is “Deletable”, and “Effect at Test Points” is “None”.  
         [0150]      FIG. 16  is a flow chart diagram showing a procedure for test point design according to the fifth embodiment.  
         [0151]     First, the circuit data on the semiconductor integrated circuit including the test points for the one or plurality of test modes shown in  FIG. 18  and the information attached to the test points in the circuit data shown in  FIGS. 19 and 20  are inputted as the design data D 101 .  FIG. 21  is the coordinate representation of “Positional Information” included in the information attached to the test points in the circuit data. In Data Read Step D 102 , the reading of the design data D 101  is performed. When conditions such that the type of the test mode is “Scan Test” and “Test Point Merging Distance is 5 or Less in Manhattan Distance” are specified in the test mode D 102 , any test point for which “Scan Test” is not written as “Test Mode” in the information attached to the test point in the circuit data stored in the database is deleted in Test Point Deletion Step S 102 . However, since the design data D 101  has no test point for which “Test Mode” is other than “Scan Test”, no test point is deleted in Test Point Deletion Step S 104 . Then, in Logic Synthesis Step S 105  as the next step including a test point optimization process, timing optimization is performed based on the logic synthesis constraints included in “Logic Synthesis Constraints” in the information attached to the test points in the circuit data, while test point merging is performed under the condition that “Test Point Merging Distance is 5 or Less in Manhattan Distance” specified as the test mode D 102 . A list of candidate test points which can be merged include the test points {tp 5 , tp 6 , and tp 7 } of which the input clocks have the same frequency. When the Manhattan distance between a combination of each two of the mergeable test points in the list is determined, the Manhattan distance |tp 5 -tp 6 | between the test points tp 5  and tp 6  is 2, the Manhattan distance |tp 5 -tp 7 | between the test points tp 5  and tp 7  is 8, and the Manhattan distance |tp 6 -tp 7 | between the test points tp 6  and tp 7  is 6. Since the condition specified in the test mode D 102  is “Test Point Merging Distance is 5 or Less in Manhattan Distance”, the test points tp 5  and tp 6  which satisfy the condition are judged to be mergeable so that they are merged. Since the design data D 104  outputted in Data Output Step S 105  assigns the function of “Improvement in Monitorability” that has been performed by the flip-flop ff 5  to the flip-flop ff 6  as shown in  FIG. 22 , a circuit is provided from which the test point tp 5  composed of the flip-flop ff 5  and the input terminal clk 5  has been deleted, to which an XOR circuit xor 1  has been added, and in which the outputs of the combinational circuits cc 7  and cc 9  are connected to the inputs of the XOR circuit xor 1 , and the output of the XOR circuit xor 1  is connected to the input of the flip-flop ff 6 .  
         [0152]     When “Scan Test” is specified as the test mode D 102  and “Clock Source Sharing” is inputted, clocks having the same use purpose and the same frequency are shared. In the case with the design data D 101 , a list of the test points which can share a clock source are {tp 5 , tp 6 , and tp 7 }. In the design data D 104  outputted in Data Output Step S 105 , the input terminals clk 6  and clk 7  are deleted and each of the clock inputs of the flip-flops ff 6  and ff 7  is connected to the input terminal clk 5 , as shown in  FIG. 23 .  
         [0153]     The Manhattan distance described herein can be measured between any two nodes as follows. The differences between the values of the same coordinate components of the two nodes are determined individually and the absolute values of the differences between the same coordinate components are added up on a component-by-component basis. The sum of the absolute values of the differences therebetween is the Manhattan distance.  
       Embodiment 6  
       [0154]      FIG. 15  shows an apparatus for designing a semiconductor integrated circuit according to a sixth embodiment of the present invention.  FIG. 17  is a flow chart diagram showing a procedure for designing a semiconductor integrated circuit by using the apparatus for designing a semiconductor integrated circuit. The apparatus for designing a semiconductor integrated circuit and the flow chart diagram showing the design procedure according to the present embodiment are basically the same as those described in the fifth embodiment so that a description will be given to portions different from those in the apparatus for designing a semiconductor integrated circuit and the flow chart diagram showing the design procedure described in the fifth embodiment.  
         [0155]     The apparatus for designing a semiconductor integrated circuit shown in  FIG. 15  is different from that described in the fifth embodiment in that the test point deletion unit K 104  is provided within the data input unit. By using the apparatus for designing a semiconductor integrated circuit to delete a test point in Test Point Deletion Step S 104  in a stage previous to Database Storage Step S 103 , a used space in the memory of the storage device can further be reduced than in the fifth embodiment.