Abstract:
An apparatus for coupling to capacitors to form a charge pump includes first and second sets of switch elements, and a controller. Switches in the first set couple terminals of capacitors to permit charge transfer between them. Switches in the second set couple terminals of at least some of the capacitors to either a high-voltage or a low-voltage terminal. The controller causes the switches to cycle through a sequence of states, each defining a corresponding configuration of the switch elements. At least three of the states define different configurations permitting charge transfer either between a first capacitor and a second capacitor, or between a first capacitor and one of the terminals. The configured cycle of states causes voltage conversion between the two terminals.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of the Mar. 14, 2014 priority date of U.S. Provisional Application 61/953,270, the contents of which are herein incorporated by reference. 
     
    
     FIELD OF INVENTION 
       [0002]    This invention relates to control for charge pumps to balance charge. 
       BACKGROUND 
       [0003]    Patent Publication WO 2012/151466, published on Nov. 8, 2012, and incorporated herein by reference, describes configurations of charge pumps, also known as switched capacitor converters, in which the source and/or load comprise regulating/regulator circuits. In some examples, the load can effectively comprise a current source and/or load rather than present a constant voltage in an example of what is referred to as “adiabatic” operation of a charge pump. Regulating/regulator circuits, such as switch-mode power converters, behave as current loads/sources. Therefore, current loads/sources and regulating/regulator circuits are interchangeable for the purpose of this disclosure. 
         [0004]    Although use of a current-based load (and/or source) may improve efficiency as compared to a purely or substantially voltage-based load (and/or source), internal energy losses may remain, for example, due to redistribution of charges within the charge pump. 
       SUMMARY 
       [0005]    One effect of using a current-based load (and/or source) with a charge pump is that there may be situations in which a conventional switch timing used with voltage-based loads and/or sources results in charge imbalance across capacitors, which can result in loss of efficiency, for example, due to charge redistribution immediately after switching between configurations in the charge pump. 
         [0006]    In one aspect, in general, an approach to improving efficiency of a charge pump using adiabatic charge transfer makes use of three or more states, each corresponding to a configuration of switches coupling capacitors to one another and/or the input and output terminals of the charge pump. By introducing an appropriate sequence of more than two states in which charge is transferred to or from capacitors, and selecting the duration those states are occupied in each operating cycle of the charge pump, charge transfer in and out of each capacitor is balanced over the operating cycle, thereby avoiding or greatly reducing charge redistribution at state transitions and its associated power losses that lead to inefficiency. 
         [0007]    In one aspect, the invention features an apparatus for coupling to capacitors to form a charge pump circuit. Such an apparatus includes a first and second set of switch elements and a controller circuit. The first set of switch elements comprises switch elements that are configured to couple terminals of capacitor elements to permit charge transfer between the capacitors. The second set of switch elements comprises switch elements that are configured to couple terminals of at least some of the capacitor elements to a first terminal, which is either a high voltage terminal or a low voltage terminal. The controller circuit is coupled to the switch elements and configured to cycle the switch elements through a sequence of states. Each state defines a corresponding configuration of the switch elements. At least three of the states define different configurations of the switch elements permitting charge transfer between a pair of elements. The pair of elements is either a pair of capacitors, or a capacitor and a terminal. The configured cycle of states provides a voltage conversion between the high voltage terminal and the low voltage terminal. 
         [0008]    In some embodiments, there are terminals for coupling the switch elements to the capacitors. 
         [0009]    Other embodiments include the capacitors themselves. In these embodiments, the capacitors, when coupled to the switch elements, define a charge pump circuit. 
         [0010]    Some embodiments comprise an integrated circuit. In these embodiments, at least part of the charge pump circuit and at least part of the controller circuit are formed in a single integrated circuit. 
         [0011]    Also among the embodiments are those that include a regulator circuit. In these embodiments, the regulator circuit is coupled to at least one of the high voltage terminal and the low voltage terminal of the charge pump circuit. In some of these embodiments, the regulator circuit is configured to provide a current load at the low voltage terminal of the charge pump circuit. In others, the regulator circuit is configured to operate as a current source at the low voltage terminal of the charge pump circuit. In yet others, the regulator circuit is configured to provide a current load at the high voltage terminal of the charge pump circuit, or to operate as a current source at the high voltage terminal of the charge pump circuit, or to cause a pulsed current to pass between the regulator circuit and the charge pump circuit. In the latter case, the charge pump operates in a pulse cycle having a first fraction, during which the pulsed current is a first constant current, and a second fraction, during which the pulsed current is greater in magnitude than the second constant current. In many cases, the second constant current is substantially zero or even equal to zero. Typically, the first constant current is substantially larger than the second constant current. 
         [0012]    In some embodiments, a regulator circuit is configured to control an average current passing between the regulator circuit and the charge pump circuit. 
         [0013]    In those embodiments that feature a regulator, a great many regulator types can be used. These include regulators that are switch-mode power converters, or buck converters, or even magnetic filters. 
         [0014]    In some embodiments, the controller is configured to maintain each state for a corresponding duration of a fraction of a charge pump cycle time. The durations of these states are selected to maintain a balanced charging and discharging of each of the capacitors through the sequence of states of each cycle. 
         [0015]    In other embodiments, the controller is configured to select durations of the states to reduce redistribution of charge among the capacitors upon state transitions. 
         [0016]    When coupled to the terminals of the capacitor elements, the switch elements define any of a variety of charge pump circuits. Examples include a multi-phase charge pump, a single-phase charge pump, a multi-stage charge pump, and a cascade multiplier. 
         [0017]    Also among the embodiments are those in which the controller is configured to receive sensor signals from at least one of the first and second sets of switch elements and to adaptively adjust cycling of the switch elements through the sequence of states based at least in part on the sensor signals. 
         [0018]    In some embodiments, there are two regulator circuits. A regulator circuit is coupled to the high voltage terminal of the charge pump circuit. Meanwhile, a second regulator circuit is coupled to the low voltage terminal of the charge pump circuit. Either the first or second regulator can be a magnetic filter. Among these embodiments are those in which the controller is configured to receive sensor signals from at least one of the first and second sets of switch elements and to adaptively adjust cycling of the switch elements through the sequence of states based at least in part on the sensor signals. 
         [0019]    In another aspect, the invention features a method for operating a charge pump in which switch elements from a first set of switch elements are configured to couple terminals of capacitor elements to permit charge transfer between the capacitors, and in which switch elements from a second set of switch elements are configured to couple terminals of capacitor elements to either a high voltage terminal or a low voltage terminal. Such a method includes causing a voltage conversion between the high voltage terminal and the low voltage terminal. Causing this voltage conversion includes cycling the switch elements through a sequence of states. Each state defines a corresponding configuration of the switch elements. At least three of the states define different configurations of the switch elements permitting charge transfer between a pair of elements. The pair of elements is either a pair of capacitors or a capacitor and a one of the terminals. 
         [0020]    Some practices of the invention include maintaining an average current passing between a regulator circuit and the charge pump circuit. Others include regulating a current at the first terminal, thereby maintaining an average current passing between a regulator circuit and the charge pump circuit. 
         [0021]    In other practices, cycling the switch elements through a sequence of states includes maintaining each state for a corresponding duration of a fraction of a charge pump cycle time. This can also include selecting the durations of the states are selected to maintain a balanced charging and discharging of each of the capacitors through the sequence of states of each cycle. 
         [0022]    Some practices of the invention include controlling an average current between a regulator circuit and the charge pump circuit. 
         [0023]    Other practices include coupling a regulator circuit to the first terminal. Among these are practices that include causing the regulator circuit to provide a current load at the low voltage terminal of the charge pump circuit, causing the regulator circuit to provide a current load at the high voltage terminal of the charge pump circuit, causing the regulator circuit to operate as a current source at the low voltage terminal of the charge pump circuit, causing the regulator circuit to operate as a current source at the high voltage terminal of the charge pump circuit, and causing a pulsed current to pass between a regulator circuit and the charge pump circuit. 
         [0024]    Some practices include coupling the switch elements from the first and second sets of switch elements to the terminals of the capacitor elements. This can result in forming a multi-phase charge pump, a single-phase charge pump, a multi-stage charge pump, or a cascade multiplier. 
         [0025]    Those practices that involve a regulator include selecting the type of regulator. This can include selecting the regulator to be a switch-mode power converter, selecting the regulator to be a buck converter, or selecting the regulator to be a magnetic filter. 
         [0026]    Some practices also include receiving sensor signals from at least one of the first and second sets of switch elements and adaptively adjusting the cycling of the switch elements through the sequence of states based at least in part on the sensor signals. 
         [0027]    Some practices involve the use of two regulators. These practices further include coupling a first regulator to the high voltage terminal, and coupling a second regulator to the low voltage terminal. One of the regulators can be a magnetic filter while the other is a converter. Among these practices are those that also include controlling least one of the first and second sets of switch elements and adaptively adjusting the cycling of the switch elements through the sequence of states based at least in part on sensor signals received from at least one of said first and second sets of switch elements. 
         [0028]    Other features and advantages of the invention are apparent from the following description, and from the claims. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0029]      FIG. 1  is a schematic diagram of a single-phase 5:1 charge pump with a voltage source and a current load. 
           [0030]      FIGS. 2A-2B  are schematic diagrams of the circuit of  FIG. 1  in states 1 and 2, respectively, of the switch configuration. 
           [0031]      FIGS. 3A-3C  are schematic diagrams of the circuit of  FIG. 1  in states 1a, 1b, and 2, respectively. 
           [0032]      FIG. 3D  is a set of waveforms showing the voltage across each capacitor in  FIGS. 3A-3C  during the operation of the charge pump. 
           [0033]      FIGS. 4A-4C  are schematic diagrams of the circuit of  FIG. 1  in alternative definitions of states 1a, 1b, and 2, respectively. 
           [0034]      FIG. 4D  is a set of waveforms showing the voltage across each capacitor in  FIGS. 4A-4C  during the operation of the charge pump. 
           [0035]      FIG. 5  is a schematic diagram of a single-phase 6:1 charge pump with a voltage source and a current load. 
           [0036]      FIGS. 6A-6D  are schematic diagrams of the circuit of  FIG. 5  in states 1a, 1b, 2a, and 2b, respectively. 
           [0037]      FIG. 7  is a schematic diagram of a two-phase 5:1 charge pump with a voltage source and a current load. 
           [0038]      FIGS. 8A-8B  are schematic diagrams of the circuit of  FIG. 7  in states 1a and 1b, respectively. 
           [0039]      FIG. 9  is a schematic of a two-phase 3:1 series-parallel charge pump with a voltage source and a current load. 
           [0040]      FIGS. 10A-10D  are schematic diagrams of the circuit of  FIG. 9  in states 1a, 1b, 2a, and 2b, respectively. 
           [0041]      FIGS. 11A-11B  are schematic diagrams of the circuit of  FIG. 7  in states 1a and 1b, respectively with current skew. 
           [0042]      FIGS. 12-14  are block diagrams of power converters. 
       
    
    
     DETAILED DESCRIPTION 
       [0043]    A first example charge pump  110  is shown in  FIG. 1  to illustrate a source of charge imbalance in the operation of such a charge pump. The charge pump  110  is a cascade multiplier configured to nominally provide a 5:1 (i.e., M=5) step-down in voltage such that an output voltage V OUT  (volts) is one-fifth of an input voltage V IN  (volts). Four capacitors (labeled C 1  to C 4 ) are used with switches (labeled S 1  to S 9 ) on both terminals of each capacitor to store a fraction of the input voltage V IN  and transfer charge from one capacitor to the next. The capacitors closest to the V IN  and V OUT  terminals are labeled C 1  and C 4 , respectively, and are referred to below as the “outer” capacitors, while the remaining capacitors labeled C 2  and C 3  are referred to below as the “inner” capacitors. As further notation, the voltage and charge on a capacitor C k  are denoted V k  and Q k , respectively. Unless otherwise indicated, the capacitors are treated as ideally having identical capacitance C (Farads). 
         [0044]    The charge pump  110  is operated by controlling a set of switches (S 1  through S 9 ) that cause charge to pass between the capacitors and between the terminals and the capacitors. The control of the switches of the charge pump  110  can be represented as a cycle through a series of states, where each state is associated with a particular configuration of the set of switches (i.e., a particular setting of open-circuit (non-conducting) and closed-circuit (conducting) configuration of each of the switches). 
         [0045]    One mode of operation of the charge pump  110  shown in  FIG. 1  uses a cycle of two states. In a state 1, the switches labeled “1” (i.e., S 1 , S 3 , S 5 , S 7 , S 8 ) are closed and the switches labeled “2” (i.e., S 2 , S 4 , S 6 , S 9 ) are open. In a state 2, the switches labeled “1” are open and the switches labeled “2” are closed. These configurations of switches are shown in tabular form (“1” indicating the switch is closed and “0” indicating that the switch is open) as follows: 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Switch 
               
             
          
           
               
                 State 
                 S 1   
                 S 2   
                 S 3   
                 S 4   
                 S 5   
                 S 6   
                 S 7   
                 S 8   
                 S 9   
               
               
                   
               
               
                 State 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
               
               
                 State 2 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                   
               
             
          
         
       
     
         [0046]    Note that in practice, additional states may be needed in which all or a sufficient set of switches are open such that charge is not passing to or from the capacitors without affecting the overall function of the charge pump  110 , for example, in a “break before make” approach to avoid the necessity of truly instantaneous switching. However, for the analysis of the ideal behavior below, such additional states are not generally considered because these additional states do not involve a transfer of charge and will not affect the outcome of the analysis. 
         [0047]    A complete cycle of the charge pump  110  has a sequence of two states, state 1 followed by state 2. A first phase node P i  couples with the negative terminal of the capacitors C 1 , C 3 , and a second phase node P 2  couples with the negative terminal of the capacitors C 2 , C 4 . The voltage at the first phase node P 1  alternates between ground and the output voltage V OUT , and the voltage at the second phase node P 2  is out of phase with the first phase node P 1 . 
         [0048]    In steady-state operation, the capacitors C 1  to C 4  have nominal voltages across their terminals that are multiples of the nominal output voltage: 
         [0000]        V   1   (nom) =4 *V   OUT   (nom) =(4/5)* V   IN    
         [0000]        V   2   (nom) =3 *V   OUT   (nom) =(3/5)* V   IN    
         [0000]        V   3   (nom) =2 *V   OUT   (nom) =(2/5)* V   IN    
         [0000]        V   4   (non) =1 *V   OUT   (nom) =(1/5)* V   IN    
         [0049]    For example, when the input voltage V IN  equal to 25.0 (volts), the nominal voltages across the capacitors C 1 -C 4  are 20.0, 15.0, 10.0, and 5.0 (volts), respectively, and the nominal output voltage V OUT  is 5.0 (volts). The actual voltages across the capacitors vary around these nominal values (i.e., the voltage exhibits “ripple”) during a cycle of the successive states of operation of the charge pump  110 , denoted as 
         [0000]        V   k   =V   k   (nom)   +v   k . 
         [0050]    In this example, the output terminal of the charge pump  110  is treated as being coupled to a current load, with current I OUT . In some examples, this current is assumed constant. More generally, as discussed further below, the current may be pulsed with a constant average Ī OUT =D*I OUT   (peak) , where D is the duty cycle (a fraction between zero and one) of the pulsed current load; this is a good representation of the behavior of a buck converter. In general, the frequency of the current load switching is a multiple times the frequency of the charge pump  110  switching (e.g., 2×, 3×, 10×, 100×). In some examples, the current may be constant during each state, but have different values during each state. Furthermore, state transition instants are preferably chosen to occur during the zero-current part of the output current duty cycle, thereby reducing switching losses with non-ideal (e.g., transistor) switches. But for the sake of discussion of this first example, only the constant current case is considered. 
         [0051]    Referring to  FIGS. 2A-2B , the equivalent circuits of the charge pump  110  in  FIG. 1  are shown for state 1 and state 2, respectively. Generally, in state 1, energy is transferred from the V IN  terminal to the outer capacitor C 1 , between the inner capacitors C 2 , C 3 , and from the outer capacitor C 4  to the V OUT  terminal. In state 2, energy is transferred between the capacitors and to the load at the V OUT  terminal. 
         [0052]    During state 1, the outer capacitors C 1 , C 4  carry a current of 0.4*I OUT  while the inner capacitors C 2 , C 3  each carry a current of 0.2*I OUT , which is half the current through the outer capacitors C 1 , C 4 . Therefore, if state 1 has a state duration time t 1 , then the change in charge on the outer capacitors C 1 , C 4 , denoted ΔQ k,j  as the change in charge on capacitor C k  during state j, satisfy 
         [0000]      +Δ Q   1,1   =−ΔQ   4,1   =t   1 *0.4 *Ī   OUT  
 
         [0000]    while the change in charge on the inner capacitors C 2 , C 3  during state 1 satisfy 
         [0000]      −Δ Q   2,1   =+ΔQ   3,1   =t   1 *0.2 *Ī   OUT .
 
         [0000]    Note that the inner capacitors C 2 , C 3  are connected in series while the outer capacitors C 1 , C 4  are the only elements in their respective paths, causing the current to divide accordingly by the number of series capacitors. 
         [0053]    During state 2, every capacitor carries a current of 0.5*I OUT . The inner capacitors C 2 , C 3  are always in a series connection with another capacitor in either state while the outer capacitors C 1 , C 4  have a similar series connection only during state 2. The current flow polarity through each capacitor changes back and forth from one state to the next state as needed to charge and discharge the capacitor and maintain a constant average voltage across the capacitor. 
         [0054]    If the charge pump  110  were controlled at a 50% duty cycle with t 1 =t 2 =0.5*T SW , where T SW  is the total duration of the switching cycle, the net charge across each cycle of two states on each capacitor C k , ΔQ k =ΔQ k,1 +ΔQ k,2  is not zero. A consequence of this is that the net charge and average voltage on the capacitors may drift over successive cycles, and/or may cause a sizeable redistribution of charge at each state transition, neither of which may be desirable. 
         [0055]    An alternative three-state control of the charge pump  110  shown in  FIG. 1  uses states labeled “la”, “lb”, and “2”. The configuration of the switches in these states is shown in tabular form as follows: 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Switch 
               
             
          
           
               
                 State 
                 S 1   
                 S 2   
                 S 3   
                 S 4   
                 S 5   
                 S 6   
                 S 7   
                 S 8   
                 S 9   
               
               
                   
               
               
                 State 1a 
                 1 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
               
               
                 State 1b 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
               
               
                 State 2 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                   
               
             
          
         
       
     
         [0056]    The equivalent circuits in each of these states are shown in  FIGS. 3A-3C , respectively. Note that in state 1a, a current of 0.5*I OUT  passes through each of the capacitors C 1 , C 4  (with opposite voltage polarities), in state 1b, a current of 1.0*I OUT  passes through the capacitors C 2 , C 3 , and in state 2, a current of 0.5*I OUT  passes through all four capacitors. A suitable selection of state durations times t 1a , t 1b , t 2  to balance the total change in charge in each cycle must satisfy the set of equations: 
         [0000]      Δ Q   1 =0=+0.5 t   1a −0.5 t   2  
 
         [0000]      Δ Q   2 =0=−1.0 t   1b +0.5 t   2  
 
         [0000]      Δ Q   3 =0=+1.0 t   1b −0.5 t   2  
 
         [0000]      Δ Q   4 =0=−0.5 t   1a +0.5 t   2  
 
         [0000]        T   SW =+1.0 t   1a +1.0 t   1b +1.0 t   2    
         [0000]    where the set of equations are satisfied with 
         [0000]        t   1a =0.4* T   SW    
         [0000]        t   1b =0.2* T   SW    
         [0000]        t   2 =0.4* T   SW    
         [0057]    Assuming the state duration times above,  FIG. 3D  illustrates the voltages V 1 -V 4  across the capacitors C 1 -C 4  in  FIGS. 3A-3C  when the charge pump  110  has an input voltage V IN  equal to 25.0 volts. This yields an output voltage V OUT  with average voltage of approximately 5.0 volts as shown in the  FIG. 3D . 
         [0058]    Another three-state approach to controlling the charge pump  110  of  FIG. 1  uses a different sequence of states with switch configurations and corresponding equivalent circuits shown in  FIGS. 4A-4C , respectively. The configuration of switches in the three states is shown in tabular form as: 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Switch 
               
             
          
           
               
                 State 
                 S 1   
                 S 2   
                 S 3   
                 S 4   
                 S 5   
                 S 6   
                 S 7   
                 S 8   
                 S 9   
               
               
                   
               
               
                 State 1a 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
               
               
                 State 1b 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
               
               
                 State 2 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                   
               
             
          
         
       
     
         [0059]    An analysis as presented above applied to this definition of the states yields state duration times that satisfy the charge balance equations of 
         [0000]        t   1a =0.5* T   SW    
         [0000]        t   1b =0.1* T   SW    
         [0000]        t   2 =0.4* T   SW    
         [0060]    Assuming the state duration times above,  FIG. 4D  illustrates the voltages V 1 -V 4  across the capacitors C 1 -C 4  in  FIGS. 4A-4C  when the charge pump  110  has an input voltage V IN  equal to 25.0 volts. This yields an output voltage V OUT  with average voltage of approximately 5.0 volts as shown in  FIG. 4D . Notice how the shape of the waveforms in  FIG. 4D  differ from those in  FIG. 3D . 
         [0061]    A consideration of the sum of the RMS (root mean squared) currents through the capacitors shows that these state definitions yield a lower value than that of the previously described three-state configuration ( FIGS. 3A-3C ). In a non-ideal implementation of the charge pump  110 , in which resistances including resistances in series with the capacitors cause power loss, a lower RMS current is associated with smaller power loss. Therefore, these state configurations may be preferable. 
         [0062]    Note that different sequences of states can still result in charge balance over the repeating cycle. For example, the state sequence 1a-1b-2-1a-1b-2 . . . can be replaced with the sequence 1b-1a-2-1b-1a-2 . . . using the same state duration times as determined above. 
         [0063]    Other state definitions and timing also follow the approach outlined above. For instance, two additional approaches for the M=5 case are shown below in tabular form: 
         [0000]                                                                                          Switch                State   S 1     S 2     S 3     S 4     S 5     S 6     S 7     S 8     S 9     Duration               State 1a   0   0   1   0   1   0   1   1   0   0.3 * T SW         State 1b   1   0   1   0   0   0   1   1   0   0.3 * T SW         State 2   0   1   0   1   0   1   0   0   1   0.4 * T SW                      
and
 
         [0000]                                                                                          Switch                State   S 1     S 2     S 3     S 4     S 5     S 6     S 7     S 8     S 9     Duration               State 1a   1   0   0   0   0   0   1   X   0   0.2 * T SW         State 1b   0   0   0   0   1   0   X   1   0   0.2 * T SW         State 1c   0   0   1   0   0   0   1   1   0   0.2 * T SW         State 2   0   1   0   1   0   1   0   0   1   0.4 * T SW                      
where X indicates that the switch can either be open or closed.
 
         [0064]    The multi-state approach presented above for the M=5 circuit of  FIG. 1  may be extended directly to other odd values of M. Generally, in state 1a, capacitor C 1  is in parallel with capacitor C M-1 , and when M≧5 in parallel with series connections of C 2  and C 3 , through C M-3  and C M-2 . State 1b has the parallel connection of the series of C 2  and C 3 , through C M-3  and C M-2 , and state 2 has the parallel connection of the series C 1  and C 2  through C M-2  and C M-1 . A closed form of the state duration times for general odd M can then be expressed as 
         [0000]        t   1a =( M+ 5)/(4 M )* T   SW    
         [0000]        t   1b =( M− 3)/(4 M )* T   SW    
         [0000]        t   2 =( M− 1)/(2 M )* T   SW    
         [0065]    A similar approach can be applied to situations where M is even. Referring to  FIG. 5 , a 6:1 (M=6) cascade multiplier type charge pump  110  is shown that includes ten switches labeled S 1  to S 10  and five capacitors labeled C 1  to C 5 . The configurations for the switches in each of four states: 1a, 1b, 2a, and 2b, are shown in the table below. The equivalent circuits in each of these states are shown in  FIGS. 6A-6D , respectively. 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Switch 
               
             
          
           
               
                 State 
                 S 1   
                 S 2   
                 S 3   
                 S 4   
                 S 5   
                 S 6   
                 S 7   
                 S 8   
                 S 9   
                 S 10   
               
               
                   
               
               
                 State 1a 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
               
               
                 State 1b 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
               
               
                 State 2a 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
               
               
                 State 2b 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                   
               
             
          
         
       
     
         [0066]    Applying the type of analysis described above, the state duration times to achieve a balancing of charge transfer through the cycle of states yields: 
         [0000]      t 1a =1/3* T   SW    
         [0000]        t   1b =1/6* T   SW    
         [0000]        t   2a =1/3* T   SW    
         [0000]        t   2b =1/6* T   SW    
         [0067]    As with M being an odd case, a general solution for arbitrary M being even yields the solution: 
         [0000]        t   1a =( M− 2)/(2 M )* T   SW    
         [0000]        t   1b =1 /M*T   SW    
         [0000]        t   2a =( M− 2)/(2 M )* T   SW    
         [0000]        t   2b =1/ M*T   SW    
         [0068]    The approach described above is applicable to multi-phase charge pumps as well. For example,  FIG. 7  shows a two-phase M=5 cascade multiplier type charge pump  110  that includes fourteen switches labeled S 1a  to S 7b  and eight capacitors labeled C 1a  to C 4b . The configurations for the switches in one possible four-state approach (with states labeled 1a, 1b, 2a, 2b) are shown in the table below: 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Switch 
               
             
          
           
               
                 State 
                 S 1a   
                 S 1b   
                 S 2a   
                 S 2b   
                 S 3a   
                 S 3b   
                 S 4a   
                 S 4b   
                 S 5a   
                 S 5b   
                 S 6a   
                 S 6b   
                 S 7a   
                 S 7b   
               
               
                   
               
               
                 State 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
               
               
                 1a 
               
               
                 State 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
               
               
                 1b 
               
               
                 State 
                 0 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                 2a 
               
               
                 State 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                 2b 
               
               
                   
               
             
          
         
       
     
         [0069]      FIGS. 8A-8B  show the equivalent circuits for states 1a and 1b, respectively. The circuits for states 2a and 2b are equivalent (i.e., interchanging the “a” and “b” elements of the circuit). Applying the charge balance constraints for this circuit yields the state duration times of 0.25*T SW  for each of the four states as shown below: 
         [0000]        t   1a =1 2a =0.25* T   SW    
         [0000]        t   1b   =t   2b =0.25* T   SW    
         [0070]    Note that in this example, the input current from the V IN  terminal is zero during states 1b and 2b while non-zero during states 1a and 2a at a current of 0.4*I OUT , yielding an average input current of 0.2*Ī OUT =Ī OUT /M as expected. 
         [0071]    Referring to  FIG. 7 , a parallel arrangement of two sections as shown in  FIG. 1 ; the timing of each section is 90° out of phase, such that one section has the switch configuration of state la while the other section has the switch configuration of state 1b, and so forth. Note that in this parallel arrangement, the average input current is 0.2*Ī OUT =Ī OUT /M in each cycle of operation. 
         [0072]    The approaches described above are applicable to a wide range of charge pump topologies. As a further example, an  FIG. 9  shows a M=3 two-phase series-parallel charge pump  110  that includes fourteen switches labeled S 1a  to S 7b  and four capacitors labeled C 1a  to C 2b . The configuration of switches in the four states is shown in tabular form as: 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Switch 
               
             
          
           
               
                 State 
                 S 1a   
                 S 1b   
                 S 2a   
                 S 2b   
                 S 3a   
                 S 3b   
                 S 4a   
                 S 4b   
                 S 5a   
                 S 5b   
                 S 6a   
                 S 6b   
                 S 7a   
                 S 7b   
               
               
                   
               
               
                 State 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
               
               
                 1a 
               
               
                 State 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
               
               
                 1b 
               
               
                 State 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 2a 
               
               
                 State 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
               
               
                 2b 
               
               
                   
               
             
          
         
       
     
         [0073]    Equivalent circuits for the four states are shown in  FIGS. 10A-10D . Charge balance is achieved with a state duration time of 0.25*T SW  for each state, yielding an average input current from V IN  in each state and cycle of (1/3)*Ī OUT . 
         [0074]    In the analysis above, the average current Ī OUT  is assumed to be the same during all state duration times, therefore, the charge transfers are proportional to t j *Ī OUT . In an alternative approach, the average output current may be controlled to be different for different states so that the charge transfers in state j are proportional to t j *Ī OUT,j  where both the state duration time t j  and the average current Ī OUT,j  are determined according to the constraint equations. In some examples, the state duration times may be further (fully or partially) constrained for other considerations, for example, to avoid short state duration times which might cause EMI (electro-magnetic interference). An example, where such variable and periodic control of output current may be effective is when driving one or more LEDs (light emitting diode) in series or in parallel, where the variation in current does not appreciably cause perceptible variation in light output. 
         [0075]    The approach described above can be applied to the two-phase M=5 cascade multiplier type charge pump  110  of  FIG. 7 . One possible four-state approach (with states labeled 1a, 1b, 2a, 2b) has equivalent circuits as shown in  FIGS. 11A-11B  for states 1a and 1b, respectively. The circuits for states 2a and 2b are equivalent (i.e. interchanging the “a” and “b” elements of the circuit). The configuration of switches in the four states is shown in tabular form as: 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Switch 
               
             
          
           
               
                 State 
                 S 1a   
                 S 1b   
                 S 2a   
                 S 2b   
                 S 3a   
                 S 3b   
                 S 4a   
                 S 4b   
                 S 5a   
                 S 5b   
                 S 6a   
                 S 6b   
                 S 7a   
                 S 7b   
               
               
                   
               
               
                 State 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
               
               
                 1a 
               
               
                 State 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
               
               
                 1b 
               
               
                 State 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                 2a 
               
               
                 State 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                 2b 
               
               
                   
               
             
          
         
       
     
         [0076]    With state duration times of 0.25*T SW  for each of the four states, it becomes necessary to apply a current skew, I SKEW , to the output load in each state to achieve charge balance over a cycle of the four states. In this example, a negative current skew of 0.2*I OUT  during states la and 2a, and a positive current skew of 0.2*I OUT  during states 1b and 2b will achieve charge balance in all capacitors over a cycle, where the average output current across each cycle of four states is I OUT . In other words, the output load current during states 1a and 2a is 0.8*I OUT  and the output load current during states 1b and 2b is 1.2*I OUT . The magnitude of the applied current skew is the same in all four states, but the polarity of the current skew changes back and forth between positive and negative from one state to the next. For a two-phase charge pump with this four-state approach and 0.25*T SW  state duration times, a general solution for arbitrary M yields the following solution for the magnitude of the applied current skew, I SKEW : 
         [0000]    
       
         
           
             
               I 
               SKEW 
             
             = 
             
               
                  
                 
                   
                     4 
                     - 
                     M 
                   
                   M 
                 
                  
               
                
               
                 I 
                 OUT 
               
             
           
         
       
     
         [0077]    It should be understood that the description above focuses on analysis of idealized circuits with ideal switches, ideal current, voltage sources, and resistance-free circuit paths. In practice, switches are implemented, for instance, with transistors, which generally exhibit internal resistance and capacitive characteristics. The output current load may be implemented using an inductor such that during the part of the duty cycle modeled as a constant current, the current in fact fluctuates as energy is transferred from the charge pump to the inductor. Physical capacitors may have slightly different capacitances, and therefore the ideal analysis for charge balancing may not be exactly correct. Nevertheless, the approach presented above is applicable to non-ideal implementations of the approach, either exactly, or accounting for the non-ideal nature of the circuit for example, determining the state durations to achieve charge balance in a real rather than an ideal circuit, for example, using numerical circuit simulation techniques. 
         [0078]    Implementations of a charge pump controlled according to one or more of the approaches described above may use a controller that is configured to follow a state sequence as described and to set the switches accordingly. Referring to  FIG. 12 , an example of a power converter  100  includes a charge pump  110  coupled to a controller  120  providing control signals on path  132  and receiving sensor signals on path  134 . The charge pump  110  includes capacitors  112  and switches  114 . A terminal  116  (e.g., a high voltage terminal) couples the charge pump  110  to a power source  150 , for example, to a voltage source (e.g., at 25 volts). Another terminal  118  couples the charge pump  110  to a first regulator circuit  130 , which is coupled to a load  140 . A controller  120  includes a programmable processor  122  configured with configuration data  124  (and/or processor instructions), which impart functionality on the controller  120 . 
         [0079]    In some examples, the controller  120  also controls the first regulator circuit  130 , for example, to maintain a common underlying clocking rate for both the charge pump  110  and the first regulator circuit  130  (e.g., switching the first regulator circuit  130  at a multiple 2×, 4×, 10×, 100×, etc. of the cycle frequency of the charge pump  110 ). In some implementations, the controller  120  is integrated in whole or in part in an integrated device that includes at least some of the switches  114  (e.g., transistors). 
         [0080]    An alternative power converter  101  is illustrated in  FIG. 13 , where a second regulator circuit  160  is coupled between the power source  150  and the charge pump  110  instead of between the load  140  and the charge pump  110  as in  FIG. 12 . In some examples, the controller  120  controls the load  140  to facilitate charge balancing of the capacitors  112  within the charge pump  110 . In other examples, the controller  120  controls the second regulator circuit  160  and in even other examples, the controller  120  controls both the load  140  and the second regulator circuit  160 . 
         [0081]    One more alternative power converter  102  is illustrated in  FIG. 14 . This example is a combination of the power converters  100 ,  101 . In this implementation, there is a first regulator circuit  130  coupled between the load  140  and the charge pump  110 ; and a second regulator circuit  160  coupled between the power source  150  and the charge pump  110 . In some examples the controller  120  controls at least the first regulator circuit  130  or the second regulator circuit  160 , to maintain a common underlying clocking 
         [0082]    In other examples, either the first regulator circuit  130  or the second regulator circuit  160  is a magnetic filter, such as an LC filter, instead of a converter. If the first regulator circuit  130  is a magnetic filter, then the regulation capability of the power converter  102  is only accomplished by the second regulator circuit  160  and adiabatic operation is in part possible due to the first regulator circuit  130  acting as a current load. Similarly, if the second regulator circuit  160  is a magnetic filter, then the regulation capability of the power converter  102  is only accomplished by the first regulator circuit  130  and adiabatic operation is in part possible due to the second regulator circuit  160  acting as a current source. 
         [0083]    It should be understood that in practice, the devices are not ideal, for example, with the capacitors  112  not necessarily having identical capacitances, and with non-zero resistances in circuit paths and through the switches  114  in the charge pump  110 . In some examples, the controller  120  controls the switches  114  according to the idealized analysis. In other examples, the effect of non-idealized characteristics are taken into account in determining the state durations, for example, by explicit circuit analysis (e.g., simulation) or adaptively by adjusting the relative state durations to achieve charge balance during state cycles based upon sensor signals on path  134 . In some examples, the controller  120  is software configurable, for example, allowing specific state timing to be configured after the device is fabricated. In some examples, the controller  120  is fully or at least partially implemented in application-specific logic that is specified with the other circuit components of the device. 
         [0084]    The charge pump  110  can be implemented using many different charge pump topologies such as Ladder, Dickson, Series-Parallel, Fibonacci, and Doubler. Similarly, suitable converters for the regulator circuits  130 ,  160  include Buck converters, Boost converters, Buck-Boost converters, non-inverting Buck-Boost converters, Cuk converters, SEPIC converters, resonant converters, multi-level converters, Flyback converters, Forward converters, and Full Bridge converters. 
         [0085]    It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims. Other embodiments are within the scope of the following claims.