Abstract:
A semiconductor device. The semiconductor device includes a substrate includes: a substrate having a first gate stack on a surface of the substrate, wherein the first gate stack has a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack; a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate; an insulative layer on a second portion of the surface of the substrate; and a conductive layer on the top surface of the first gate stack.

Description:
[0001]     This application is a divisional of Ser. No. 11/369,409, filed, Mar. 7, 2006; which is a divisional of Ser. No. 10/713,227, U.S. Pat. No. 7,064,027. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field  
         [0003]     The present invention relates generally to semiconductor devices and the fabrication thereof, and more particularly, to the design of a semiconductor device using an etch resistant liner on a transistor gate and/or a resistor gate.  
         [0004]     2. Related Art  
         [0005]     Spacers are conventionally used to protect the sidewalls of a gate stack during the processes required to form silicide on a top surface of the gate stack and within the source/drain region of a transistor. Prior to the formation of silicide the wafer undergoes a conventional preclean process to prepare the top surface of the gate stack and the source/drain region for silicide formation. Unfortunately, the spacers are not resistant enough to withstand the proclean process, and portions of the spacer may become inadvertently removed. As a result, portions of the gate stack sidewall become exposed. The exposed portions of the gate stack sidewall are then susceptible to silicide formation. Silicide formed on the sidewalls of the gate stack can lead to electrical shorts between the silicide on the top of the gate stack and the silicide within the source/drain region at the base of the gate stack. As semiconductor devices are continually being scaled down, and the distance between the top of the gate stack and the source/drain region is being reduced, the likelihood of electrical shorts due to the silicide formed on the sidewalls of the gate stack increases.  
         [0006]     The preclean process mentioned above also tends to affect resistors formed adjacent to the transistors. In order to maintain the designed resistance it is desirable to prevent silicide formation within or around the resistor gate stack. Portions of the spacers protecting the sidewalls of the resistor gate stack may become removed during the preclean process. As with the transistor, the exposed portions of the resistor gate stack are susceptible to silicide formation, which tends to decrease resistance.  
         [0007]     Therefore, there is a need in the industry for a method of forming a transistor and/or resistor gate that overcomes the above problems.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention provides an etch resistant liner formed over a transistor gate stack and a resistor gate stack that solves the above-stated problems.  
         [0009]     A first aspect of the invention provides a method of forming a semiconductor device, comprising: providing a substrate having a gate stack on the surface of the substrate; forming an etch resistant liner over the gate stack; forming a spacer over the liner along sidewalls of the gate stack; removing the liner from regions of the substrate and gate stack not covered by the spacer, and leaving the liner in regions of the substrate and gate stack covered by the spacer; and forming a conductive material in the regions of the substrate and gate stack not covered by the liner.  
         [0010]     A second aspect of the invention provides a method of forming a semiconductor device, comprising: providing a substrate having a first gate stack and a second gate stack on the surface of the substrate; forming a liner over the first and second gate stacks; forming a spacer over the liner and along the sidewalls of the first and second gate stacks; removing the liner from regions of the substrate and gate stacks not covered by the spacer; forming a protective layer over the second gate stack; and forming a conductive material in the regions not covered by the liner.  
         [0011]     A third aspect of the invention provides a semiconductor device, comprising: a gate stack formed on a substrate; an etch resistant liner covering sidewalls of the gate stack and a portion of the substrate adjacent the gate stack; a spacer on the liner along the sidewalls of the gate stack; and a conductive material within a top region of the gate stack and within source and drain regions of the substrate, wherein the source and drain regions are located where the liner ends on the substrate.  
         [0012]     A fourth aspect of the invention provides a semiconductor device, comprising: a transistor gate stack and a resistor gate stack formed on a substrate; a first spacer along sidewalls of the transistor and resistor gate stacks; a liner over the first spacer of the transistor and resistor gate stacks, and along a portion of the substrate at a base of the transistor and resistor gate stacks, wherein the liner extends along the substrate to a designated location of transistor source and drain regions; a spacer on the liner along the sidewalls of at least the transistor gate stack; and a conductive material within a top surface of the transistor gate stack and within the transistor source and drain regions.  
         [0013]     The foregoing and other features and advantages of the invention will be apparent from the following more particular description of the embodiments of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:  
         [0015]      FIG. 1  depicts a portion of a semiconductor device in accordance with a first embodiment having a first and a second gate stack formed on a substrate;  
         [0016]      FIG. 2  depicts the substrate of  FIG. 1  having a first spacer formed along sidewalls of the gate stacks;  
         [0017]      FIG. 3  depicts the substrate of  FIG. 2  having a liner formed over the surface of the substrate;  
         [0018]      FIG. 4  depicts the substrate of  FIG. 3  having a second spacer formed over the liner and along the gate stack sidewalls, and an ion implant performed on the surface of the substrate;  
         [0019]      FIG. 5  depicts the substrate of  FIG. 4  having portions of the liner removed from the surface of the substrate;  
         [0020]      FIG. 6  depicts the substrate of  FIG. 5  having a protective layer deposited over the surface of the substrate, and a photoresist layer formed over the second gate stack region;  
         [0021]      FIG. 7  depicts the substrate of  FIG. 6  after the protective layer is removed from the surface of the substrate in the first gate stack region;  
         [0022]      FIG. 8   a  depicts the substrate of  FIG. 7  following a preclean process;  
         [0023]      FIG. 8   b  depicts the first gate stack of  FIG. 7  before the preclean process;  
         [0024]      FIG. 8   c  depicts the first gate stack of  FIG. 8   a  after the preclean process;  
         [0025]      FIG. 9  depicts the substrate of  FIG. 8   a  having a conductive material formed in select regions of the substrate;  
         [0026]      FIG. 10  depicts a portion of a semiconductor device in accordance with a second embodiment having a first and a second gate stack formed on a substrate, and a photoresist layer formed over the second gate stack region during an ion implant;  
         [0027]      FIG. 11  depicts the substrate of  FIG. 10  having portions of the liner removed from the surface of the substrate in the first gate stack region;  
         [0028]      FIG. 12  depicts the substrate of  FIG. 11  having a protective layer deposited over the surface of the substrate, and a photoresist layer formed over the second gate stack region;  
         [0029]      FIG. 13  depicts the substrate of  FIG. 12  after the protective layer is removed from the surface of the substrate in the first gate stack region;  
         [0030]      FIG. 14  depicts the substrate of  FIG. 13  following a preclean process;  
         [0031]      FIG. 15  depicts the substrate of  FIG. 14  having a conductive material formed in select regions of the substrate;  
         [0032]      FIG. 16  depicts a portion of a semiconductor device in accordance with a third embodiment having a first and a second gate stack formed on a substrate, and a liner formed over the surface of the substrate;  
         [0033]      FIG. 17  depicts the substrate of  FIG. 16  during ion implantation;  
         [0034]      FIG. 18  depicts the substrate of  FIG. 17  having portions of the liner removed from the surface of the substrate;  
         [0035]      FIG. 19  depicts the substrate of  FIG. 18  having a protective layer deposited over the surface of the substrate, and a photoresist layer formed over the second gate stack region;  
         [0036]      FIG. 20  depicts the substrate of  FIG. 19  after the protective layer is removed from the surface of the substrate in the first gate stack region;  
         [0037]      FIG. 21  depicts the substrate of  FIG. 20  following a preclean process;  
         [0038]      FIG. 22  depicts the substrate of  FIG. 21  having a conductive material formed in select regions of the substrate;  
         [0039]      FIG. 23  depicts a portion of a semiconductor device in accordance with a fourth embodiment having a first and a second gate stack formed on a substrate, a liner formed over the surface of the substrate, and a first spacer formed over the liner along sidewalls of the gate stack;  
         [0040]      FIG. 24  depicts the substrate of  FIG. 23  having a photoresist layer covering the second gate stack region during ion implantation;  
         [0041]      FIG. 25  depicts the substrate of  FIG. 24  having portions of the liner removed from the surface of the substrate;  
         [0042]      FIG. 26  depicts the substrate of  FIG. 25  having a protective layer deposited over the surface of the substrate, and a photoresist layer formed over the second gate stack region;  
         [0043]      FIG. 27  depicts the substrate of  FIG. 26  after the protective layer is removed from the surface of the substrate in the first gate stack region;  
         [0044]      FIG. 28  depicts the substrate of  FIG. 27  following a preclean process; and  
         [0045]      FIG. 29  depicts the substrate of  FIG. 28  having a conductive material formed in select regions of the substrate. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0046]     Although certain embodiments of the present invention will be shown and described in detail, it should be understood that various changes and modifications might be made without departing from the scope of the appended claims. The scope of the present invention will in no way be limited to the number of constituting components, the materials thereof, the shapes thereof, the relative arrangement thereof, etc. Although the drawings are intended to illustrate the present invention, the drawings are not necessarily drawn to scale.  
         [0047]      FIG. 1  shows a semiconductor substrate  10  having an STI  12  formed within the substrate  10  as is known in the art. The substrate  10  may comprise silicon, or other similarly used material. Active regions  14 ,  16  will be formed on each side of the STI  12 . In particular, a transistor will be formed in the first active region  14 , and a resistor will be formed in the second active region  16 . Each active region  14 ,  16  has a gate dielectric layer  18  separating the substrate  10  from a gate stack  20 ,  22 . The gate stacks  20 ,  22  may be formed using conventional processes, and comprise polysilicon, or other similarly used material.  
         [0048]     As illustrated in  FIG. 2 , a first spacer  24  is formed along sidewalls  26  of the gate stacks  20 ,  22 . The first spacer  24  may comprise an oxide material, or other similarly used material. The first spacer  24  may be formed using an oxidation process wherein oxide is deposited on the sidewalls  26  using chemical-vapor deposition (CVD), plasma-enhanced chemical-vapor deposition (PECVD), or other similar process. The oxide is then etched using a reactive ion etch (RIE), or other similar process. The first spacer  24  may be formed having a thickness of about 50 Å-200 Å.  
         [0049]     As illustrated in  FIG. 3 , a liner  28  is formed over the surface of the substrate  10  conformally covering the gate stacks  20 ,  22  and first spacer  24 . The liner  28  comprises an etch resistant material, e.g., a material having a high dielectric constant, (wherein “high” refers to a dielectric constant (K) of at least 7, and may be in the range of about 7-150). For example, the liner  28  may comprise a high K material such as Al 2 O 3 , HfO 2 , Ta 2 O 3 , or other similar material. Alternatively, the liner  28  may comprise an etch resistant material other than a high K material such as SiC. The liner  28  may be formed having a thickness in the range of about 25 Å-250 Å. The liner  28  may be conformally deposited using CVD, atomic layer deposition (ALD), plasma-assisted CVD, sputtering, or other similar process.  
         [0050]     As illustrated in  FIG. 4 , a second spacer  30  is formed on the liner  28  along the sidewalls  26  of the gate stacks  20 ,  22 . The second spacer  30  may comprise an insulative material, such as a nitride, e.g., Si 3 N 4 , or other similarly used insulative material. The material for the second spacer  30  may be deposited using CVD, PECVD, or other similar process. Thereafter, a RIE, or other similar process, may be used to remove the excess material thereby forming the second spacer  30 . The second spacer  30  may be formed having a thickness of about 200 Å-800 Å.  
         [0051]     Ions  32 , such as Ge, Xe, Si, etc., are then implanted into the surface of the substrate  10  in order to damage exposed regions  34 ,  36  of the liner  28 , or the regions  34 ,  36  not covered by the second spacer  30 . Specifically, the exposed region  34  of the liner  28  on top of the gate stacks  20 ,  22 , and the exposed regions  36  of the liner  28  on the substrate  10  adjacent the gate stacks  20 ,  22  are intentionally damaged by the ion implant. Thereafter, the damaged portions of the liner  28  in regions  34  and  36  are chemically removed using a wet etch, as illustrated in  FIG. 5 .  
         [0052]     As illustrated in  FIG. 6 , an insulative layer  38  is conformally deposited over the surface of the substrate  10 . A photoresist  40  is then deposited, patterned and etched, using conventional processes, in order to cover the resistor region  16  of the substrate  10  and leave the transistor region  14  of the substrate  10  uncovered. An etch process, such as a RIE, or other similar process, may be performed to remove the insulative layer  38  from the surface of the substrate  10  in the transistor region  14 . The remaining photoresist  40  is removed leaving a protective layer  38  over the resistor region  16  of the substrate  10 , as illustrated in  FIG. 7 .  
         [0053]     The surface of the substrate  10  is cleaned, using a “preclean” process, to prepare the surface of the substrate  10  in the transistor region  14  for the formation of a conductive material. For example, a hydro-fluoride (HF) chemical proclean process may be performed. During the preclean process the second spacer  30  is unintentionally etched due to a lack of etch resistance. As a result, the thickness of the second spacer  30  is decreased, as illustrated in  FIGS. 8   a - c . Specifically,  FIG. 8   b  shows the thickness  42  of the second spacer  30  before the preclean process is performed. At that time the thickness  42  of the second spacer  30  is such that it extends to about an end  44  of the liner  28  that is adjacent to, or along a portion of the substrate  10  at, the base of the gate stack  20 . After the preclean process the thickness  46  ( FIG. 8   c ) of the second spacer  30  is reduced, such that the second spacer  30  does not extend to the end  44  of the liner  28  adjacent to, or along a portion of the substrate at, the base of the gate stack  20 . In this embodiment, the second spacer  30  on the resistor gate stack  22  is not affected by the preclean because the gate stack  22  and spacers  24 ,  30  are protected by layer  38 .  
         [0054]     As illustrated in  FIG. 9 , a conductive material  48 , e.g., silicide, or other similar material, is formed on the top region  34  of the transistor gate stack  20  and in source/drain regions  50  of the transistor. The conductive material  48  may be formed by uniformly depositing a layer of a refractory metal, such as cobalt or titanium, over the surface of the substrate  10 , using PVD, CVD, sputtering, or other similar process. The metal is then annealed, for example, exposed to 700° C. for about 30 seconds. During the annealing process the metal diffuses into the exposed regions of silicon to form silicide. Thereafter, non-reacted cobalt metal is chemically removed.  
         [0055]     It should be noted that the liner  28  defines, or determines, where the conductive material  48  is formed in relation to the transistor gate stack  20 . If the liner  28  had not been used the conductive material  48  within the source/drain region  50  would have formed much closer to the base of the gate stack  20 , because the preclean process performed before the conductive material  48  is formed reduces the thickness  46  of the second spacer  30  (refer to  FIG. 8   c ). The liner  28  covers the silicon within the substrate  10  in region  52 , (the region that was originally covered by the second spacer  30  prior to the preclean process), thereby preventing conductive material  48  from forming in that region  52 . Had the conductive material  48  formed too close to the base of the gate stack  20  there would be a greater likelihood of electrical shorts between the conductive material  48  on the top region  34  of the transistor gate stack  20  and the conductive material  48  within the source/drain region  50  of the transistor gate stack  20 .  
         [0056]     Additionally, the liner  28  prevents the removal of the first spacer  24  from the sidewalls  26  of the gate stacks  20 ,  22  during the preclean process. Since there are no breaches formed within the first spacer  24 , the sidewalls of the gate stacks  20 ,  22  are not susceptible to formation of the conductive material  48 . As described in the related art, conductive material  48  formed on the sidewalls  26  of the transistor gate stack  20  increases the occurrence of electrical shorting between the conductive material  48  on the top region of the gate stack  20  and the conductive material  48  within the source/drain region  50 . Also, conductive material  48  formed on the sidewalls  26  of the resistor gate stack  22  decreases resistance of the resistor.  
         [0057]     A second embodiment is illustrated in  FIGS. 10-15 . In this embodiment the liner  28  on the top region  34  of the resistor gate stack  22 , and the liner  28  in the region  36  adjacent the resistor gate stack  22  are not removed. In particular, following formation of the second spacer  30  on the liner  28  along the sidewalls  26  of the transistor and resistor gate stacks  20 ,  22 , in accordance with the first embodiment ( FIGS. 1-4 ), a masking layer, or photoresist layer  54  is deposited over the substrate  10 . As illustrated in  FIG. 10 , the photoresist layer  54  is patterned and etched to expose the transistor region  14  of the substrate  10 . The ions  32  implanted, as described above, will damage the exposed regions  34 ,  36  of the liner  28  in the transistor region  14  only, but the liner  28  in the resistor region  16  will not be damaged.  
         [0058]     Thereafter, the wet etch is performed to remove the damaged portions of the liner  28  in regions  34  and  36 , and the photoresist  54  is removed, as illustrated in  FIG. 11 . As described in connection with the first embodiment, the protective layer  38  is conformally deposited over the surface of the substrate  10  ( FIG. 12 ). A photoresist  40  is then deposited, patterned and etched, using conventional processes, to cover the resistor region  16  of the substrate  10  and leave the transistor region  14  of the substrate  10  uncovered ( FIG. 12 ). An etch process, such as a RIE, or other similar process, is performed to remove the protective layer  38  from the surface of the substrate  10  in the transistor region  14 , as illustrated in  FIG. 13 . The remaining photoresist  40  is also removed leaving the protective layer  38  over the resistor region  16  of the substrate  10  ( FIG. 13 ).  
         [0059]     Thereafter, the preclean process is performed to prepare the surface of the substrate  10  in the transistor region  14  for the formation of the conductive material  48 . As described above, the thickness of the second spacer  30  decreases during the preclean process ( FIG. 14 ). The second spacer  30  along the sidewalls of the resistor gate stack  22  is protected by layer  38  during the preclean process. In addition, the first spacer  24  and the resistor gate stack  22  are not affected by the preclean because the gate stack  22  and the first spacer  24  are protected by liner  28 .  
         [0060]     Conductive material  48  is then formed on the top region  34  of the transistor gate stack  20  and in the source/drain regions  50  of the transistor ( FIG. 15 ). The resistor region  16 , however, forms no conductive material  48  because the liner  28  covering the entire surface of the resistor region  16  ensures that there are no breaches in the spacers  24 ,  30  or protective layer  38  during the conductive material  48  preclean process.  
         [0061]     A third embodiment is illustrated in  FIGS. 16-22 . Instead of forming the first spacer  24  along the sidewalls  26  of the transistor gate stack  20  and the resistor gate stack  22 , the liner  28  is formed directly on the gate stacks  20 ,  22 , as illustrated in  FIG. 16 . Thereafter, spacer  30  is formed on the liner  28  along the sidewalls  26  of the gate stacks  20 ,  22 , as illustrated in  FIG. 17 .  
         [0062]     Ions  32  may then be implanted into the surface of the substrate  10  to damage exposed regions of the liner  30 , as illustrated in  FIG. 17 . As described in the first embodiment, the exposed regions of the liner  28  are intentionally damaged by the ion implantation. The damaged portions of the liner  28  are then chemically removed using a wet etch, as illustrated in  FIG. 18 .  
         [0063]     As illustrated in  FIG. 19 , layer  38  is conformally deposited over the surface of the substrate  10 . A photoresist  40  is then deposited, patterned and etched, using conventional processes, to cover the resistor region  16  of the substrate  10  and leave the transistor region  14  of the substrate  10  uncovered. An etch process removes layer  38  from the surface of the substrate  10  in the transistor region  14 . The remaining photoresist  40  is removed leaving a protective layer  38  over the resistor region  16  of the substrate  10 , as illustrated in  FIG. 20 .  
         [0064]     The preclean process is performed to prepare the surface of the substrate  10  in the transistor region  14  for the formation of the conductive material  48 . As described in the first embodiment, the second spacer  30  is etched during the preclean process, thereby decreasing the thickness of the second spacer  30 , as illustrated in  FIG. 21 . As described in the first embodiment, and illustrated in  FIG. 22 , the conductive material  48  is formed on the top region  34  of the transistor gate stack  20  and in the source/drain regions  50  of the transistor.  
         [0065]     A fourth embodiment combines portions of the second and third embodiments, and is illustrated in  FIGS. 16 and 23 - 29 . As with the third embodiment above, the liner  28  is formed directly on the gate stacks  20 ,  22 , without forming the first spacer  24 , as illustrated in  FIG. 16 . Thereafter, spacer  30  is formed on the liner  28  along the sidewalls  26  of the gate stacks  20 ,  22 , as illustrated in  FIG. 23 . Photoresist layer  54  is then deposited, patterned and etched, as described in the second embodiment, in order to protect the resistor region  16  of the substrate  10  and expose the transistor region  14  of the substrate  10 , as illustrated in  FIG. 24 .  
         [0066]     Ions  32  may then be implanted into the surface of the substrate  10  to damage exposed regions  34 ,  36  of the liner  28 , as illustrated in  FIG. 24 . As described in the first embodiment, the exposed regions  34 ,  36  of the liner  28  are intentionally damaged by the ion implantation. The photoresist layer  54 , however, prevents the resistor region  16  from exposure to the ions  32 , thereby protecting the liner  28  in the resistor region  16  from damage, and ultimately from removal. Following implantation of the ions  32 , the photoresist layer  54  is removed, and the damaged portions of the liner  28  are then chemically removed using a wet etch, as illustrated in  FIG. 25 .  
         [0067]     As illustrated in  FIG. 26 , layer  38  is conformally deposited over the surface of the substrate  10 . Photoresist  40  is then deposited, patterned and etched to cover the resistor region  16  of the substrate  10  and leave the transistor region  14  of the substrate  10  uncovered. An etch process removes layer  38  from the surface of the substrate  10  in the transistor region  14 . The remaining photoresist  40  is removed leaving a protective layer  38  over the resistor region  16  of the substrate  10 , as illustrated in  FIG. 27 .  
         [0068]     The preclean process is performed to prepare the surface of the substrate  10  in the transistor region  14  for the formation of the conductive material  48 . As described in the first embodiment, spacer  30  is etched during the preclean process, thereby decreasing the thickness of the spacer  30  ( FIG. 28 ). As described in the first embodiment, and illustrated in  FIG. 29 , the conductive material  48  is formed on the top region  34  of the transistor gate stack  20  and in the source/drain regions  50  of the transistor.