Abstract:
The invention is an electronic device including a ferroelectric random access memory (FRAM), a first supply voltage domain, a second supply voltage domain and a low drop output voltage regulator (LDO) receive a first supply voltage of the first supply voltage domain and providing a second supply voltage of the second supply voltage domain. The second supply voltage domain supplies the FRAM. The LDO switches between a first state providing and maintaining the second supply voltage of the second supply voltage domain and a second state providing a high impedance output to the second supply voltage domain. The electronic device switches the LDO from the first state to the second state in response to a failure of the first supply voltage domain.

Description:
CLAIM OF PRIORITY 
       [0001]    This application claims priority under 35 U.S.C. 119(a) to German Patent Application No. 10 2010 011 749.8 filed Mar. 17, 2010. 
       TECHNICAL FIELD OF THE INVENTION 
       [0002]    The technical field of this invention is an electronic device and a method for FRAM power supply management and more specifically to an electronic device and a method for providing a safe operation of an FRAM with respect to the power supply. 
       BACKGROUND OF THE INVENTION 
       [0003]    One of the disadvantages of the FRAM memory technology is that each read access to the memory contents destroys the stored information in the memory cells. Therefore, the data that is read from memory cells needs to be written back into memory cells after each read access in order to restore their original content. This write operation is referred to as write-back. It is to be ensured under all circumstances, as for examples shorts on the supply pins of the FRAM memory device, that a complete write-back operation can be performed. Otherwise, the integrity of the FRAM memory is affected. However, in order to perform a complete write-back operation, the power supply system has to maintain a required supply voltage level for the FRAM memory during the event of power failure until the write-back operation is finished. 
       SUMMARY OF THE INVENTION 
       [0004]    It is an object of the invention to provide an electronic device and a method for FRAM power supply management which are resistant to errors and failures due to power supply variations. 
         [0005]    According to an aspect of the invention, an electronic device is provided which comprises a ferroelectric random access memory (FRAM). There is a first supply voltage domain, a second supply voltage domain and a low drop out voltage regulator (LDO) which is coupled to receive a supply voltage of the first supply voltage domain and to provide a supply voltage of the second supply voltage domain. This means that the LDO is coupled between the first and the second supply voltage domain and provides the supply voltage of the second supply voltage domain as an output voltage. The second supply voltage domain is advantageously confined to supply the FRAM. The LDO may then be configured to be switched into a first state for providing and maintaining the supply voltage of the second supply voltage domain and into a second state for providing a high impedance output to the second supply voltage domain. The electronic device may further be configured to switch the LDO from the first state to the second state in response to a failure condition of the first supply voltage domain. According to this aspect of the invention, the supply voltage for the FRAM memory is provided from an integrated voltage regulator (LDO) the output voltage of which is not available on any external device pin. The LDO is configured to drive the FRAM memory by providing the required supply voltage. If a failure on the LDO input (first supply voltage domain) is detected, the LDO output can be switched into a high impedance state. Furthermore, the failure condition can be flagged, stored and indicated or communicated to other stages of the electronic device. 
         [0006]    A capacitor may be coupled between the output of the LDO and the power supply of the FRAM. The capacitor may be configured to provide sufficient charge for a complete FRAM access cycle after the LDO is switched into the second state. A complete FRAM access cycle includes a read cycle and a write-back cycle for the data. The capacitor may then advantageously be configured to provide just sufficient charge for a complete access cycle (read and write-back cycle) to the FRAM after the LDO is switched into the second state. This aspect of the invention provides that at least a complete access cycle (read and write-back cycle) can be performed even if the external power supply, the power supply of the first supply voltage domain or any other power supply drops out of the valid voltage range. 
         [0007]    The capacitor may then be configured as a function of the supply voltage required for an access cycle of the FRAM. This may be defined as: 
         [0000]      CAP= f (POWFRAM), 
         [0000]    where: CAP is the capacitance of the buffer capacitor coupled between the output of the LDO and the power supply of the FRAM; and POWFRAM is the power required for a complete access cycle of the specific FRAM used in the application. 
         [0008]    In an aspect of the invention, the access cycle (read and write-back cycle) can be performed self-timed. The access cycle in the second state can then be performed independently of any external clock or other control signals. 
         [0009]    In another aspect of the invention, the electronic device may comprise a third supply voltage domain. This third supply voltage domain may then be configured to be available when either the supply voltage of the first supply voltage domain or the supply voltage of the second supply voltage domain is within a valid voltage range. Accordingly, important stages or important functions of the electronic device may be supplied by a supply voltage of the third voltage domain which can operate if either the first or the second supply voltage domain still has enough power. A buffer capacitance may be coupled so as to maintain the second supply voltage for a limited time. The second supply voltage in the second supply voltage domain may then be greater than the first supply voltage in the first supply voltage domain even if the second supply voltage is derived from the first supply voltage. The electronic device may further comprise a control stage which can be supplied by a supply voltage of the third voltage domain and be configured to hold the LDO in the second state. This provides that even in case of a failure of the first supply voltage in the first supply voltage domain, the LDO is held in the second state in order to make sure that the output of the LDO is in a high impedance condition so as to decouple the second supply voltage domain from the first supply voltage domain in the second state. 
         [0010]    There may be a failure detector for detecting a failure of the voltage level in the first supply voltage domain that may be supplied by a supply voltage of the first supply voltage domain, the second supply voltage domain or the third supply voltage domain. The failure detector may be level sensitive and/or transient sensitive. 
         [0011]    There may be an interface logic configured to generate isolation control signals for the FRAM memory. The interface logic may further be configured to stop any controller, logic or CPU (central processing unit) activities in response to a change from the first state to the second state. Accordingly, all inputs and outputs of the FRAM can be configured to be isolated and decoupled from other stages of the electronic device when the LDO is switched into the second state so as to prevent any further access to the FRAM. 
         [0012]    Furthermore, the second supply voltage domain may be decoupled from any external pins of the electronic device. This aspect of the invention provides that the risk to cause any failure or variations of the supply voltage of the second supply voltage domain for the FRAM is minimized. 
         [0013]    The invention also provides a method of supplying power to a ferroelectric random access memory (FRAM). According to this method, a low drop output voltage regulator (LDO) may receive a supply voltage of a first supply voltage domain. The LDO may then provide a supply voltage of a second supply voltage domain at an output. The second supply voltage domain can be confined to supply only the FRAM. The LDO may then be switched from a first state of providing and maintaining the supply voltage of the second supply voltage domain into a second state in which the output of the LDO is in a high impedance state in response to a failure condition of the first supply voltage domain. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0015]      FIG. 1  is a simplified circuit diagram of an embodiment of the invention, 
           [0016]      FIG. 2  shows waveforms of signals of the embodiment shown in  FIG. 1  during a power up sequence, 
           [0017]      FIG. 3  shows waveforms of signals of the embodiment of  FIG. 1  relating to low power modes, and 
           [0018]      FIG. 4  shows waveforms of signals of  FIG. 1  relating to a power failure or reset sequence. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0019]      FIG. 1  shows a simplified circuit diagram of an electronic device  100  according to an embodiment of the invention. There is an FRAM memory core  1  comprising ferroelectric random access memory cells. The FRAM memory core  1  is configured through a reset signal FRAMPORZ, a write enable signal WEZI and a core enable signal CEZI. There are further input signals INX for writing to the FRAM memory core and output signals OUTX to read data from the FRAM memory core  1 . There are various buffers IBUF 1 F, IBUF 2 F, IBUFXF for input signals IN 1 , IN 2  and INX as well as output buffers OBUF 1 F for output signals OUTX. Each buffer can represent numerous buffers of a respective input bus (IN 1  to INX) or an output bus (OUTX). The input buffers IBUF 1 F, IBUF 2 F and IBUFXF are configured through an FRAM isolation signal FRAMISO and the output buffers OBUF 1 F are configured through an output isolation signal FRAMLPMISO 1 P 5 V. The memory core and the input buffers can be supplied by a supply voltage VDDF of a second voltage domain. The output buffers OBUF 1 F are supplied by a supply voltage VDDC of another supply voltage domain. The supply voltage domains VDDC and VDDF are both supply voltage domains which may have a supply voltage level of about 1.5 V. Outside of the supply domains VDDF and VDDC there might be another supply voltage domain that can be an analog input/output supply voltage domain of 3.3 V. This supply voltage domain may always be switched on. 
         [0020]    There is further a power management stage  4  including various input and output buffers IBUF 1 P, OBUF 1 P, IBUF 2 P, IBUF 3 P, logic gates OR 1 , OR 2 , OR 3 , OR 4 , AND 1 , RSFF and delay stages DEL 1 , DEL 2 . There is further a supply voltage failure detector DVCCFAIL  5 . There is also a low drop output voltage regulator FRLDO  6  which can be switched from a first state to a second state. In the first state, the LDO  6  provides and maintains as an output the supply voltage level VDDF for the second supply voltage domain for the FRAM memory core  1  and the input buffers. The output voltage of the LDO  6  is buffered by a capacitor C. The LDO receives a supply voltage of a first domain DVCC and derives the supply voltage of the second supply voltage domain VDDF from the first supply voltage domain DVCC. The capacitor C is configured to store sufficient charge in order to supply the FRAM memory core  1  and the input buffers IBUF 1 F, IBUF 2 F and IBUFXF, i.e. the voltage domain VDDF in order to perform at least one access cycle for the FRAM. 
         [0021]    The buffers IBUF 1 P, IBUF 2 P, IBUF 3 P, IBUF 4 P and OBUF 1 P may be configured as level shifters in order to pass signals from the second voltage domain VDDF to the first voltage domain DVCC. The buffers may then be supplied by both voltage domains. The signals ENFRLDO 3 P 3 V, VCCFAIL 1 P 5 LV, SETFAIL 3 P 3 V and FRAMLPMISO 3 P 3  are received or sent to a power management module PMM  9 . This power management module may be configured to provide additional supply voltage monitoring and managing features. The power management module PMM  9  may then be coupled to the first supply voltage domain DVCC (for example a 3.3 V voltage domain and to the supply voltage VDDC which may be a 1.5 V supply voltage domain. The logic gates OR 2 , AND 1 , RSFF, OR 3 , OR 4 , DEL 2  as well as the voltage failure detector DVCCFAIL  5  are supplied with the supply voltage VDDF of the second supply voltage domain. Only the logic gate OR 1  may be supplied with the maximum supply VMAX, which is the maximum of the first supply voltage DVCC and the second supply voltage VDDF. The capacitor C may also be integrated into the electronic device  100 . Supplying the logic gate OR 1  with the maximum of the first and the second supply voltages (VMAX=max [DVCC, VDDF]) it can be prevented that the isolation of the FRAM due to a supply voltage failure is affected if either of the two supply voltage levels (DVCC or VDDF) suddenly drops. 
         [0022]      FIG. 2  shows waveforms of signals relating to a power up sequence of the embodiment shown in  FIG. 1 . The normal power up sequence starts with signal BOH changing from low to high. The LDO is then turned on by changing ENFRLDO from low to high and the voltage supply VDDF of the second domain rises. If the supply voltage level VDDF of the second supply voltage domain has reached the target value, signal FRAMLDOOK changes from low to high to indicate that signal FRAMLMPISO can be changed from high to low. This means that the output buffers (OBUF 1 F shown in  FIG. 1 ) can be switched on. The FRAM memory core is then changed from an isolated state to a state where it can communicate with other stages, or processing units. Signals like SETFAIL or VCCFAIL remain unasserted as no error occurred. The FRAM can be changed from a reset state into a state where it is not reset. Finally, after a predefined period of time which is due to the delays shown in  FIG. 1 , signal FRAMISO changes from high to low in order to activate the input buffers IBUF 1 F, IBUF 2 F to IBUFXF (i.e. changing from high impedance or tristate to normal operation). 
         [0023]      FIG. 3  shows most of the signals already shown and explained with respect to  FIG. 1  and  FIG. 2  for a sequence where the system is switched into a low power mode. The FRAM power supply VDDF is turned off. The enable signal ENFRLDO is switched from high to low. The LDO is switched into high impedance state and the second power supply domain for the FRAM is isolated. The FRAM isolation signal FRAMLPMISO is switched on in order to isolate the output buffers OBUF 1 F. The FRAM is reset by changing FRAMPORZ from high to low. However, the minimum pulse width for signal CEZ and WEZ (select and write signal for the write back cycle) is preserved and the signals CEZ and WEZ are maintained in order to assure that one single access cycle (read and write back cycle) can be performed. Additional digital logic ensures that FRAMLPM is only asserted as long as no FRAM access occurs. All power supply levels supplied by VDDF decrease. 
         [0024]      FIG. 4  shows waveforms of the signals shown in  FIG. 1  relating to a power failure and reset sequence. A reset may be issued by the power management module PMM  9  or by a software signal, which is indicated by signal SETFAIL switching to high. There may also be a DVCC detector (shown in  FIG. 1 ) that issues a signal VCCFAIL indicating that the voltage level of the first voltage domain dropped below a valid level. Regardless of the failure type (RESET, software, DVVC fail detected etc.), the handling can always be the same. Both alternatives are indicated by a signal VCCFAIL which can be a flag indicating a failure of a supply voltage. The FRAM is isolated before other stages are switched off. The chip level reset signal may therefore be delayed. All interfaces of the FRAM are isolated by asserting signals FRAMISO and FRAMLPMISO. The VCCFAIL flag is cleared after a delay time which is greater than TPCE, i.e. the minimum time for the access cycle (read and write back cycle). Any potential FRAM cycle may then be completed. At time t 2 , the VDDF is still above 1.35 V (in this embodiment). The FRAM reset signal FRAMPORZ is then (time t 2 ) changed from high to low. CEZ and WEZ are again asserted during time TPCE to ensure that a complete cycle of operation for the FRAM can be finished. 
         [0025]    Although the invention has been described hereinabove with reference to a specific embodiment, it is not limited to this embodiment and no doubt further alternatives will occur to the skilled person that lie within the scope of the invention as claimed.