Abstract:
A computer system includes a triggering device; and a motherboard, connected to the triggering device, further comprising: a memory stored with a setting parameter of a basic-input-output-system; and a counter connected between the triggering device and the memory; wherein an erasing signal, for erasing the memory, is outputted to the memory from the counter according to a triggering signal outputted from the triggering device while a boosting procedure cannot be successfully executed by the computer system.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a computer system with BIOS parameter stored in CMOS (Complementary Metal Oxide Semiconductor), and more particularly to a BIOS parameter erasing method and apparatus applied to the computer system. 
       BACKGROUND OF THE INVENTION 
       [0002]    The main function of BIOS (Basic Input Output System) is to initialize the hardware of a computer system while a user power on the computer system. That is, the boosting procedure is first executed by the computer system based on a plurality of parameters of the BIOS while the user pushing the power button of the computer system. Basically, the BIOS parameters are stored in a CMOS (Complementary Metal Oxide Semiconductor) that is arranged on a motherboard of the computer system, where CMOS is a RAM (Random-Access Memory) and requires less power than other types of memories. 
         [0003]    After the power button of the computer system is pushed, a POST (Power-On-Self-Test) program is executed. The user can set the BIOS parameters during the process of executing the POST. That is, a BIOS-SETUP interface is brought after the user pressing some specific functional keys, such as “Del” or “Alt+Ctrl+Esc” while the POST is executing, and the user can set the BIOS parameters via the BIOS-SETUP interface. The BIOS parameters, stored in the CMOS RAM, are some essential date or information about the computer system, such as the types and specifications of IDE, the operation frequency of CPU, or the type and capacity of the memory. Because these BIOS parameters are so important, the computer system cannot be successfully boosted without these BIOS parameters. To guarantee all these BIOS parameters will not be lost after a shutdown of the computer system, the CMOS RAM stored with the BIOS parameters must be powered by a RTC (Real-Time Clock) battery, where the RTC battery is also arranged on the motherboard but is independent of the power source of the other parts in the computer system. In other words, the RTC battery can always provide power to the CMOS RAM even the computer system is shutdown, so as the BIOS parameters stored in the CMOS RAM can be always kept. 
         [0004]    As described above, the BIOS parameters can be set by the user via the BIOS-SETUP interface. Once the BIOS parameters are set again, the computer system will start to process the boosting procedures based on the updated BIOS parameters after the user pushing the power button of the computer system next time. However, the user may set wrong parameters. Once the user sets wrong some important BIOS parameters, such as the operation frequency of CPU, a boost failure of the computer system or a startup failure of the monitor may be happened. 
         [0005]    Once the startup failure of monitor is occurred, the user has no way to correct the BIOS parameters, because the monitor cannot display messages on the screen. However, the user still can restore the initial BIOS parameters back to the computer system via erasing the CMOS RAM, and then the computer system will start to process the boosting procedures based on the initial BIOS parameters after the user pushing the power button of the computer system next time. 
         [0006]      FIG. 1  is a block diagram of a conventional motherboard of a computer system. The motherboard  10  comprises a CPU (Central Processing Unit)  101 , a north bridge  103 , a south bridge  105 , a CMOS RAM  107 , a RTC battery  109 , and a pin set  111 , where the BIOS parameters are stored in the CMOS RAM  107 ; the CMOS RAM  107  is powered by the RTC battery  109 ; and the pin set  111  includes three pins (# 1 , # 2 , # 3 ). 
         [0007]    The initial BIOS parameters can be restored back to the computer system via changing connection of the three pins (# 1 , # 2 , # 3 )  111 . Firstly, the user must enforce to shutdown the computer system. Because the computer system cannot enter to the operation system (OS) due to the failure of the execution of BIOS, user can enforcedly shutdown the computer system via continuously pressing the power button of the computer system over four seconds (4-second shutdown) or directly plugging out the power line of the computer system. After the shutdown of the computer system, the user then changes connection of the jumper to pins (# 2 , # 3 ) from pins (# 1 , # 2 ). Several seconds later, the user again changes the connection of the jumper back to pins (# 1 , # 2 ) from pins (# 2 , # 3 ). The object of shortly moving the jumper to pins (# 2 , # 3 ) is to make a short circuit between the pins (# 2 , # 3 ), and once the pins (# 2 , # 3 ) are short circuit, a CMOS-erasing signal (RTCRST#) is pulled down to a low level and is transmitted to CMOS RAM  107  from the south bridge  105 . After the CMOS-erasing signal (RTCRST#) with a low level is transmitted to the CMOS RAM  107 , the CMOS RAM  107  is erased, so as the initial parameters (data, time, system parameters) are restored back to computer system. Then, the user can press the power button of the computer system; accordingly the computer system will start to process the boosting procedures based on the initial BIOS parameters. 
         [0008]    Or, the initial BIOS parameters can be restored back to the computer system via temporarily removing the RTC battery  109  from the motherboard  10 . Firstly, the user can enforcedly shutdown the computer system via continuously pressing the power button of the computer system over four seconds (4-second shutdown) or directly plugging out the power line of the computer system. Afterwards, the user removes the RTC battery  109  from the motherboard  10  for several seconds, and then attaches the RTC battery  109  back to motherboard  10  again. Because the CMOS RAM  107  is directly powered by the RTC battery  109 , the CMOS RAM  107  will be erased while the RTC battery  109  is temporarily removed from the motherboard  10  for several seconds, so as the initial BIOS parameters are restored back to the computer system. Then, the user can press the power button of the computer system; accordingly the computer system will start to process the boosting procedures based on the initial BIOS parameters. 
         [0009]    However, no matter restoring the initial BIOS parameters back to the computer system via the pin set  111  or via temporarily removing the RTC battery  109  from motherboard  10 , the user must dismantle and reassemble the case of the computer system and thus is inconvenient. 
       SUMMARY OF THE INVENTION 
       [0010]    Therefore, the object invention is to provide BIOS parameter erasing method and apparatus for user to conveniently erase BIOS parameter. 
         [0011]    The present invention provides a computer system including a triggering device; and a motherboard, connected to the triggering device, further comprising: a memory stored with a setting parameter of a basic-input-output-system; and a counter connected between the triggering device and the memory; wherein an erasing signal, for erasing the memory, is outputted to the memory from the counter according to a triggering signal outputted from the triggering device while a boosting procedure cannot be successfully executed by the computer system. 
         [0012]    Furthermore, the present invention provides a BIOS parameter erasing method of a computer system including a triggering device and a counter, comprising steps of: activating the triggering device to generate a triggering signal while parameters stored in a memory of the BIOS is failed to process a boosting procedure; and outputting an erasing signal, for erasing the memory, to the memory from the counter based on the triggering signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
           [0014]      FIG. 1  is a block diagram illustrating a conventional motherboard of a computer system; 
           [0015]      FIG. 2  is a block diagram illustrating the computer system of the present invention capable of erasing the CMOS RAM via multi pressing the power button; 
           [0016]      FIG. 3A  is a circuit diagram illustrating the counter adopted in the present invention; and 
           [0017]      FIG. 3B  is a true table derived from the four D-Type Flip Flops arranged in the counter depicted in  FIG. 3A . 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0018]    An erasing of CMOS RAM can be done without dismantling and reassembling the case of the computer system according to the present invention. When a user presses the power button arranged on the case of the computer system several times (say, four times), a signal for erasing the CMOS RAM is then automatically generated. Because the power button is arranged on the case of the computer system, the erasing of the CMOS RAM can be done without the work of dismantling and reassembling the case of the computer system. 
         [0019]      FIG. 2  is a block diagram illustrating the computer system of the present invention capable of erasing the CMOS RAM via pressing the power button several times. The computer system of the present invention mainly comprises a motherboard  20  and a power button  22 , where the power button  22  is arranged on a case (not shown) of the computer system. The motherboard  20  further comprises a CPU  201 , a north bridge  203 , a south bridge  205 , a CMOS RAM  207 , and a counter  209  connected to the power button  22 , the CMOS RAM  207 , and the south bridge  205 . 
         [0020]    As mentioned above, the boosting procedures is executed by the computer system of the present invention based on the parameters of BIOS stored on the CMOS RAM  207  after the user pressing the power button  22 . 
         [0021]    Once a boost failure of the computer system is occurred as a result of a wrong setting of the BIOS parameters and then the CMOS RAM is accordingly needed to be erased, the user can continuously press the power button  22  several times (e.g., 4 times). In the embodiment, a power-button-press signal (PWRBTN#) is outputted from the power button  22  followed with each press of the power button  22 . There will be four power-button-press signals (PWRBTN#) outputted from the power button  22  after the user continuously pressing the power button  22  four times. In the embodiment, a converting signal for converting the level of the CMOS-erasing signal (RTCRST#) is outputted from the counter  209  once four power-button-press signals (PWRBTN#) are detected by the counter  209 , so as the CMOS RAM  207  is erased. In other words, the CMOS-erasing signal (RTCRST#) is pulled down to a low level by the converting signal which is outputted from the counter  209  as a result of four power-button-press signals (PWRBTN#) are detected. 
         [0022]    It is to be understood that the duration of the each press of the power button  22  must be controlled to less than four seconds when the user plans to erase the CMOS RAM  207  via continuously pressing the power button  22  four times, so as the computer system will not be shutdown enforcedly. 
         [0023]      FIG. 3A  is a circuit diagram illustrating the counter adopted in the present invention, where the counter can be implemented by four D-Type Flip Flops coupled in series in the embodiment.  FIG. 3B  is a true table derived from the four D-Type Flip Flops arranged in the counter depicted in  FIG. 3A . The counter  209  comprises a first-stage D-Type Flip Flop (D 1 ), a second-stage D-Type Flip Flop (D 2 ), a third-stage D-Type Flip Flop (D 3 ), and a fourth-stage D-Type Flip Flop (D 4 ). The signal-input terminal (D) of the first-stage D-Type Flip Flop (D 1 ) is connected to a voltage-power source (+3V) via a resistor (R 1 ). The signal-input terminals (D) of the second-stage D-Type Flip Flop (D 2 ), the third-stage D-Type Flip Flop (D 3 ), and the fourth-stage D-Type Flip Flop (D 4 ) are respectively connected to the signal-output terminals (Q 1 , Q 2 , and Q 3 ) of the first-stage D-Type Flip Flop (D 1 ), the second-stage D-Type Flip Flop (D 2 ), and the third-stage D-Type Flip Flop (D 3 ). The power-button-press signal (PWRBTN#) which is outputted from the power button  22  ( FIG. 2 ) is transmitted to the clock terminals (CK) of the first-stage D-Type Flip Flop (D 1 ), the second-stage D-Type Flip Flop (D 2 ), the third-stage D-Type Flip Flop (D 3 ), and the fourth-stage D-Type Flip Flop (D 4 ) via a resistor (R 2 ). The preset terminals (PR) of the first-stage D-Type Flip Flop (D 1 ), the second-stage D-Type Flip Flop (D 2 ), the third-stage D-Type Flip Flop (D 3 ), and the fourth-stage D-Type Flip Flop (D 4 ) are connected to the voltage-power source (+3V) via a resistor (R 3 ). The clear terminals (CLR) of the first-stage D-Type Flip Flop (D 1 ), the second-stage D-Type Flip Flop (D 2 ), the third-stage D-Type Flip Flop (D 3 ), and the fourth-stage D-Type Flip Flop (D 4 ) are connected to the voltage-power source (+3V) via a resistor (R 4 ). The clear terminals (CLR) of the first-stage D-Type Flip Flop (D 1 ), the second-stage D-Type Flip Flop (D 2 ), the third-stage D-Type Flip Flop (D 3 ), and the fourth-stage D-Type Flip Flop (D 4 ) are connected to ground (GND) via a capacitor (C). The complementary-signal-output terminal (Q 4 #) of the fourth-stage D-Type Flip Flop (D 4 ) is connected to the CMOS RAM  207  ( FIG. 2 ) and from which the CMOS-erasing signal (RTCRST#) is outputted. Moreover, a power-button-press signal (PWRBTN#) with a high-low-high level is generated followed with each press of the power button  22  ( FIG. 2 ). In other words, a clock is formed in the power-button-press signal (PWRBTN#) followed with each press of the power button  22 . 
         [0024]    When the user first time presses the power button  22  ( FIG. 2 ) to boost the computer system, a first clock (Clock 1 ) is formed in the power-button-press signal (PWRBTN#). At the meanwhile of the first-time press of the power button  22 , the preset terminals (PR) and the clear terminals (CLR) of the four D-Type Flip Flops (D 1 , D 2 , D 3 , D 4 ) are started to pull up to a high level by the voltage-power source (+3V). In the initial state, the signal-output terminals (Q) of the four D-Type Flip Flops (D 1 , D 2 , D 3 , D 4 ) are at a low level. That is, the signal-output terminals (Q 1 , Q 2 , Q 3 , Q 4 ) of the four D-Type Flip Flops (D 1 , D 2 , D 3 , D 4 ) are at a low level while the user first time pressing the power button  22  to boost the computer system. 
         [0025]    When the boost failure of the computer system is occurred as a result of wrong setting of the BIOS, the user must continuously presses the power button  22  ( FIG. 2 ) four times to erase the CMOS RAM  207  ( FIG. 2 ). When the user first time presses the power button  22  after the BIOS is failed to execute by the computer system, a second clock (Clock 2 ) is formed in the power-button-press signal (PWRBTN#). Then, the high-level signal at the signal-input terminal (D) of the first-stage D-Type Flip Flop (D 1 ) originally pulled up by the voltage-power source (+3V) is transmitted to the signal-output terminal (Q 1 ) of the first-stage D-Type Flip Flop (D 1 ) after the user first time pressing the power button  22  while the BIOS is failed to execute by the computer system. To sum up, the logic configuration at the signal-output terminals (Q 1 , Q 2 , Q 3 , Q 4 ) of the four D-Type Flip Flops (D 1 , D 2 , D 3 , D 4 ) is (High, Low, Low, Low) while the user first time pressing the power button  22  after the BIOS is failed to execute by the computer system. 
         [0026]    Similarly, when the user second time presses the power button  22  after the BIOS is failed to execute by the computer system, a third clock (Clock 3 ) is formed in the power-button-press signal (PWRBTN#). Then, the high-level signal at the signal-input terminal (D) of the second-stage D-Type Flip Flop (D 2 ) is transmitted to the signal-output terminal (Q 2 ) of the second-stage D-Type Flip Flop (D 2 ). To sum up, the logic configuration at the signal-output terminals (Q 1 , Q 2 , Q 3 , Q 4 ) of the four D-Type Flip Flops (D 1 , D 2 , D 3 , D 4 ) is (High, High, Low, Low) while the user second time pressing the power button  22  after the BIOS is failed to execute by the computer system. 
         [0027]    Similarly, when the user third time presses the power button  22  after the BIOS is failed to execute by the computer system, a fourth clock (Clock 4 ) is formed in the power-button-press signal (PWRBTN#). Then, the high-level signal at the signal-input terminal (D) of the third-stage D-Type Flip Flop (D 3 ) is transmitted to the signal-output terminal (Q 3 ) of the third-stage D-Type Flip Flop (D 3 ). To sum up, the logic configuration at the signal-output terminals (Q 1 , Q 2 , Q 3 , Q 4 ) of the four D-Type Flip Flops (D 1 , D 2 , D 3 , D 4 ) is (High, High, High, Low) while the user third time pressing the power button  22  after the BIOS is failed to execute by the computer system. 
         [0028]    Similarly, when the user fourth time presses the power button  22  after the BIOS is failed to execute by the computer system, a fifth clock (Clock 5 ) is formed in the power-button-press signal (PWRBTN#). Then, the high-level signal at the signal-input terminal (D) of the fourth-stage D-Type Flip Flop (D 4 ) is transmitted to the signal-output terminal (Q 4 ) of the fourth-stage D-Type Flip Flop (D 4 ). To sum up, the logic configuration at the signal-output terminals (Q 1 , Q 2 , Q 3 , Q 4 ) of the four D-Type Flip Flops (D 1 , D 2 , D 3 , D 4 ) is (High, High, High, High) while the user fourth time pressing the power button  22  after the BIOS is failed to execute by the computer system. 
         [0029]    Moreover, to avoid the CMOS RAM  207  is mistakenly erased by the user via continuously pressing the power button  22  four times after the BIOS is already successfully executed by the computer system, a GPIO (general-purpose I/O) signal is further inputted to the signal-input terminal (D) of the first-stage D-Type Flip Flop (D 1 ) via a resistor (R 5 ) in the embodiment, where the signal-output terminal (D) of the first-stage D-Type Flip Flop (D 1 ) is pulled down to a low level by the GPIO signal while the BIOS is successfully executed by the computer system. That is, once the BIOS is successfully executed by the computer system, the complementary-signal-output terminal (Q 4 #) of the fourth-stage D-Type Flip Flop (D 4 ) is still maintained at a high level even the user continuously pressing the power button  22  four times, so as the erasing of the CMOS RAM  207  will not be executed. 
         [0030]    Moreover, it is to be understood that the invention needs not be limited to erase the CMOS RAM via continuously pressing the power button four times. The erasing of the CMOS RAM in the present invention can be achieved via continuously pressing the power button N times, accordingly, the counter adopted in the present invention must be implemented by N numbers of D-Type Flip Flops coupled in series. 
         [0031]    Moreover, it is to be understood that the invention needs not be limited to adopt the power button as a triggering device to generate triggering signal. Any device arranged on the case of the computer system, such as the reset button, the fingerprint identifying device, a specific key or multi keys on a keyboard, can be adopted as the triggering device for generating trigging signal to the counter. 
         [0032]    Moreover, the counter adopted in the present invention can be integrated in the south bridge. 
         [0033]    While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.