Abstract:
A memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit. The two slots are able to efficiently process different memory types. The control circuit receives memory identification signals from the two slots. The control circuit administers the output voltage of the voltage conversion circuit according to the memory identification signals. The memory identification signals determine whether the switch circuit is to be turned on or off. This will control whether the output voltage of the voltage conversion circuit will go to the first or the second slot.

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention relates to control circuits, and particularly to a memory voltage control circuit. 
   2. Description of Related Art 
   Currently, a typical personal computer is comprised of a motherboard, interface cards, and peripheral accessories. The motherboard is the heart of the personal computer. In addition to the central processing unit (CPU), the chip set and slots for installing the interface cards, the motherboard also includes slots for installing memory modules. 
   Due to constant changes in the computer industry, memories that are typically used in computers have changed from DDR2 (Double Data Ram II) to higher speed memory chips such as DDR3 (Double Data Ram III). 
   Because DDR2s are cheaper than DDR3s, DDR2s are still in demand in the market to be used on the main board. The difference in operating DDR2 versus DDR3 includes the following: DDR2 utilizes 1.8V VDD and 0.9V VTT, while DDR3 utilizes 1.5V VDD and 0.75V VTT. Currently, no motherboard is compatible with both DDR3 and DDR2. 
   What is desired, therefore, is a memory voltage control circuit that can simultaneously support different types of computer memory. 
   SUMMARY 
   An exemplary memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit. The two slots are able to efficiently process different memory types. The control circuit receives memory identification signals from the two slots. The control circuit administers the output voltage of the voltage conversion circuit according to the memory identification signals. The memory identification signals determine whether the switch circuit is to be turned on or off. This will control whether the output voltage of the voltage conversion circuit will go to the first or the second slot. 
   Other advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiment when taken in conjunction with the accompanying drawings, in which: 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a memory voltage control circuit in accordance with an exemplary embodiment of the present invention; and 
       FIG. 2  is a circuit diagram of  FIG. 1 . 
   

   DETAILED DESCRIPTION 
   Referring to  FIG. 1 , a memory voltage control circuit in accordance with an exemplary embodiment of the present invention includes a control circuit  10 , a voltage conversion circuit  20 , a switch circuit  30 , a first slot  40  (for receiving a DDR2 memory for example), and a second slot  50  (for receiving a DDR3 memory for example). The control circuit  10  receives memory identification signals from the two slots  40 ,  50  and controls the output of the voltage conversion circuit  20  based on the memory identification signals. The memory identification signal of the second slot  50  determines whether the switch circuit  30  is to be turned on or off. This will control whether the output of the voltage conversion circuit  20  will go to the first slot  40  or the second slot  50 . 
   Referring to  FIG. 2 , the control circuit  10  includes five resistors R 1 -R 5  and two field effect transistors (FETs) Q 1  and Q 2 . The gate of the FET Q 1  is connected to a memory identification pin GNDDET of the first slot  40 , and connected to the system standby power source 5V_SB_SYS via the resistor R 1 . The source of the FET Q 1  is grounded. The drain of the FET Q 1  is connected to the system standby power source 5V_SB_SYS via the resistor R 2 . A memory identification pin GNDDET of the second slot  50  is connected to the drain of the FET Q 1  and the gate of the FET Q 2 . The source of the FET Q 2  is grounded. The drain of the FET Q 2  is grounded via the resistors R 3  and R 4  connected in series. A node between the resistors R 3  and R 4  is connected to an output N of the voltage conversion circuit  20  via the resistor R 5 . 
   The voltage conversion circuit  20  includes four FETs Q 3 ˜Q 6 , three resistors R 6 ˜R 8 , three capacitors C 1 ˜C 3 , and two inductances L 1  and L 2 . The gate of the FET Q 3  is connected to the gate of the FET Q 4 , as well as a gating pin VRAM_UGATE of a power regulator (not shown) via the resistor R 6 . A node between the drain of the FET Q 3  and the drain of the FET Q 4  is grounded via the capacitor C 1 , and is also connected to a dual power source 5V_DUAL via the inductance L 1 . A node between the source of the FET Q 3  and the drain of the FET Q 5  is connected to a node between the source of the FET Q 4  and the drain of the FET Q 6 , and grounded via the resistor R 8  and the capacitor C 2  connected in series, and connected to the output N via the inductance L 2 . The output N is grounded via the capacitor C 3 . The gate of the FET Q 5  is connected to the gate of the FET Q 6 , and is also connected to a gating pin VRAM_LGATE of the power regulator via the resistor R 7 . The sources of the FETs Q 5  and Q 6  are grounded. The gating pins VRAM_UGATE and VRAM_LGATE of the power regulator respectively receive control signals to the voltage conversion circuit  20 . 
   The switch circuit  30  includes three FETs Q 7 ˜Q 9 , three resistors R 9 ˜R 11 , and two diodes D 1  and D 2 . The gate of the FET Q 7  is connected to a memory identification pin GNDDET of the second slot  50 . The sources of the FETs Q 7  and Q 8  are grounded. The drain of the FET Q 7  is connected to the gate of the FET Q 8 , and connected to the anode of the diode D 1  via the resistor R 9 . The anode of the diode D 1  is connected to the system standby power source 5V_SB_SYS. The anode of the diode D 2  is connected to a system power source 12V_SYS. A node between the cathode of the diode D 1  and the cathode of the diode D 2  is connected to a node between the drain of the FET Q 8  and the gate of the FET Q 9  via the resistor R 10 . The drain of the FET Q 9  is connected to the power input pin P of the second slot  50  and the output N. The source of the FET Q 9  is connected to the power input pin P of the first slot  40 , and grounded via the resistor R 11 . 
   When only the DDR3 memory is plugged into the second slot  50 , the memory identification pin GNDDET of the second slot  50  outputs a low level memory identification signal. The FET Q 1  is turned on. The FET Q 2  is turned off. The FETs Q 7  and Q 9  are turned off. The FET Q 8  is turned on. The voltage conversion circuit  20  outputs a 1.5V voltage to the power input pin P of the second slot  50  via the voltage divider resistors R 4  and R 5 . 
   When only the DDR2 memory is plugged into the first slot  40 , the memory identification pin GNDDET of the first slot  40  outputs a low level memory identification signal. The FET Q 1  is turned off. The FET Q 2  is turned on. The FETs Q 7  and Q 9  are turned on. The FET Q 8  is turned off. The voltage conversion circuit  20  outputs a 1.8V voltage to the power input pin P of the first slot  40  via the voltage divider resistors R 3 , R 4 , and R 5 . 
   When the DDR3 memory is plugged into the second slot  50 , and the DDR2 memory is plugged into the first slot  40 , the memory identification pin GNDDET of both slots  40 ,  50  output a low level memory identification signal. The FETs Q 1  and Q 2  are turned off. The FETs Q 7  and Q 9  are turned off. The FET Q 8  is turned on. The voltage conversion circuit  20  outputs a 1.5V voltage to the power input pin P of the second slot  50 . The motherboard functions normally. 
   The control circuit  10  of the memory voltage control circuit receives memory identification signals from the two slots  40 ,  50  and controls the output voltage of the voltage conversion circuit  20  accordingly based on the memory identification signals. At the same time, the memory identification signals determine whether the switch circuit  30  is to be turned on or off. In turn, this governs whether the output voltage of the voltage conversion circuit  20  goes to slot  40  or slot  50 . 
   It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.