Abstract:
The invention describes structures and a process for providing ESD semiconductor protection with reduced input capacitance that has special advantages for high frequency analog pin I/O applications. The structures consist of a first and second NMOS serial pair whose capacitance is shielded from the I/O pins by a serial diode. The first serial pair provides an ESD voltage clamp between the I/O pin and the Vcc voltage source. The second pair provides an ESD voltage clamp between the I/O pin and Vss, or ground voltage source. A NMOS device whose gate is dynamically coupled to the ESD energy through capacitance and a RC network enhances the triggering of both pairs. The serial pairs can be used separately to match specific application requirements or used together.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to the structure and process for an ESD protection arrangement for high voltage tolerant ESD protection for analog applications requiring low capacitance such as radio frequency and high speed analog transceivers. 
   DESCRIPTION OF PRIOR ART 
   Because of high input impedance and thin oxide gate structures, the problem of electrostatic discharge damage (ESD) with field effect transistor (FET) devices can be severe. Therefore the input/output (I/O) circuit locations or pins usually have a protective device connected between the I/O pin and the internal circuits which allows the ESD current to be shunted to an alternative voltage source, typically ground, protecting the active internal circuits from damage. 
   There can be several different types of device structures used for these protective devices, such as single diodes, stacked diodes, field effect transistor devices, and silicon controlled rectifiers (SCR). 
   With prior art devices, the capacitance associated with the ESD protection device on the active circuit input pin can be a concern as circuit speeds increase. A typical prior art protection circuit scheme is represented in  FIG. 1 . The active circuit input-output ( 110 ) terminal or pin  10  is connected to a current limiting resistor R and then to the secondary ESD clamp or protection circuit device NMOS Mn 12 . A complimentary MOS (CMOS) inverter buffer  14  with Mp and Mn precede the input to the internal active logic circuits  16 . 
   The secondary ESD clamp  12 , is typically a gate-grounded short channel NMOS shown in  FIG. 1  as Mn 12 . This clamps the ESD overstress voltage represented by the generator element  20  to a safe voltage for the internal circuits  16 . To provide a high ESD protection level, a robust device such as a SCR, field thick-oxide device, or long channel NMOS is used as the primary ESD clamp  18  to bypass ESD current Iesd to a secondary voltage source, Vss or ground. 
   The primary clamp element  18  must be triggered on before the secondary clamping device  12  is damaged by the overstress Iesd current. The resistor R is required to limit the ESD current flowing in the secondary clamp  12 . This resistor can be in the order of thousands of ohms. 
   The large junction capacitance of the clamp devices connected in an electrical parallel configuration together with the resistor R can cause a long RC delay. For current mode input signal applications, high frequency applications and analog applications this RC input loading cannot be tolerated. For this application a configuration is required that minimizes the input capacitance and eliminates the series resistor R. 
   The invention provides a unique structure and method, which minimizes the capacitance on the I/O pin while still providing appropriate high voltage tolerant (HVT) ESD protection without the need for current limiting resistance. 
   The following patents and reports pertain to ESD protection. 
   U.S. Pat. No. 6,606,752 (Williams) shows an ESD circuit for RF and analog applications. 
   U.S. Pat. No. 6,284,616B1 (Smith) Discusses an ESD circuit with a high voltage tolerance. 
   U.S. Pat. No. 5,477,414 (Li et al.) shows an ESD protection circuit. 
   U.S. Pat. No. 6,008,970 (Maloney et al.) reveals a power supply clamp circuit for ESD protection. 
   The following technical reports discuss ESD protection methods. 
   Richier et al., “Investigation on Different ESD Protection Strategies Devoted to 3.3 V RF Applications (2 Ghz) in a 0.18 um CMOS Process.” EOS/ESD Symposium 2000, PP 252 to 259. 
   Paul Leroux, et al., “A 0.8 dB NF ESD Protected 9 Mw CMOS LNA”. Proceedings of the 2001 ISSC PP 410 to 411. 
   Ming-Dou Ker, et al., “ESD Protection Design on Analog Pin with Very Low Input Capacitance for High Frequency or Current-Mode Applications” IEEE Journal of Solid-State Circuits, Volume 35; Issue 8; August 2000, PP 1194 to 1199. 
   Ming-Dou Ker, et al, “Dynamic-Floating-Gate Design for Output ESD Protection in a 0.35 um CMOS cell library”, Proceedings of the 1998 ISCAS Volume 2; 1998, PP 216 to 219. 
   SUMMARY OF THE INVENTION 
   Accordingly, it is the primary objective of the invention to provide an effective structure and manufacturable method for providing an effective ESD clamping protection element while at the same time reducing the capacitive loading on the I/O circuits. 
   It is a further objective of the invention to improve ESD protection for high frequency and analog applications by providing a low input capacitance structure that will have minimum impact on device performance while maintaining robust ESD protection levels. 
   A still additional objective of the invention is to provide the ESD protection with reduced capacitance without changing the characteristics of the internal circuits being protected and by using a process compatible with the process of integrated MOS device manufacturing. 
   The above objectives are achieved in accordance with the methods of the invention that describes a structure and a manufacturing process for semiconductor ESD protection devices with reduced input capacitance. 
   One embodiment of the invention utilizes two NMOS series devices as a ESD energy clamp from I/O pin to Vcc, shielded from the I/O pin by a diode. The source of the second or top NMOS comprising the clamp is connected to Vcc while its gate is connected to the drain of an ESD trigger enhancing NMOS. The gate of the trigger enhancing NMOS is connected to the midpoint of an RC string between Vcc and ground. The drain of the second series NMOS is connected to the drain of the first series NMOS whose gate is connected to Vcc and whose source is connected to the cathode of the top or second diode of a series diode string. 
   The second diode anode is connected to the cathode of the first or bottom diode in the string and also connected to the I/O pin. The configuration protects against ESD charge flow from pin to Vcc. The relatively small second diode capacitance is stacked in series with the larger capacitance of the NMOS pair which provides an effective reduced capacitance from pin to Vcc of approximately the junction capacitance of the diode. 
   Another embodiment of the invention utilizes two series NMOS devices as a ESD clamp from I/O pin to Vss or ground. The clamp is shielded from the input pin by a series diode and with the source of the top or second NMOS connected to ground. This embodiment protects against any ESD charge from pin to ground. Because of the parasitic junction diode between the first NMOS source and substrate, the capacitance between pin and ground is essentially that of the two small diodes in parallel, which is smaller than that of the NMOS pair. 
   Yet another embodiment of the invention incorporates both the series NMOS device clamp to Vcc and the series NMOS device clamp to Vss or ground. Both pairs of devices are shielded from the I/O pin by a diode to reduce the capacitance seen by the I/O pin. This embodiment protects against ESD charge energy both from pin to Vcc and from pin to ground. 
   All embodiments utilize a a trigger enhancing NMOS whose gate is dynamically coupled to the ESD energy and to a RC circuit. The source of the trigger enhancing NMOS is typically connected to a gate of an NMOS in the clamp circuits to control the conduction duration. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a schematic representation of a prior art ESD protection scheme. 
       FIGS. 2A through 2D  shows the configurations for ESD testing on Analog Input/Output Pins.  FIGS. 2A and 2C  illustrates the test case of positive voltage to Vss/Gnd. (PS Mode),  FIGS. 2B and 2D  is negative voltage to Vss/Gnd. (NS Mode). 
       FIG. 3A  shows the test configuration for “Positive Mode” differential ESD voltage and  FIG. 3B  shows the test configuration for “Negative Mode” ESD differential voltage. 
       FIG. 4A  shows a simplified schematic of one embodiment of the invention for ESD protection for I/O Pin to Vcc while  FIG. 4B  shows the detailed schematic. 
       FIG. 5A  shows a simplified schematic of one embodiment of the invention for ESD protection for I/O Pin to Vss or ground while  FIG. 5B  shows the detailed schematic. ESD protection for Pin to Vss Or ground. 
       FIG. 6A  shows a simplified schematic of one embodiment of the invention for ESD protection for I/O Pin to Vcc and I/O pin protection to Vss or ground.  FIG. 6B  shows the detailed schematic. 
       FIG. 7  is a flow chart of the process of forming the protection devices for ESD protection from I/O pin to Vcc and I/O pin to Vss or ground. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4A  shows a simplified schematic of the invention embodiment for ESD protection from I/O pin to Vcc. The ESD energy is clamped to Vcc by the NMOS string  120 . Since capacitance elements in series add like resistors in parallel, the diode D 2  shields the NMOS ESD clamp string  120  capacitance from the I/O pin  110  and internal active circuits. The capacitance of the diode is much less than the capacitance of the NMOS series string ESD clamp  120 , and therefore the capacitance seen by the I/O pin  110  is essentially the relatively small capacitance of the diode D 2 . 
   The detailed schematic is shown in  FIG. 4B . The cathode of the first diode D 1  is connected to the I/O pin  10  while the anode is connected to a second voltage source, Vss, typically ground. 
   Diode D 1  provides a shunt path for negative ESD energy to ground. 
   The cathode of the second diode D 2  is connected to the source of NMOS Mn 1  while the anode of D 2  is connected to the I/O pin  110  and the cathode of diode D 1 . Diode D 2  shields the I/O pin  110  from the relatively large capacitance of the series NMOS ESD clamp string  120 . The gate of Mn 1  is tied to a first voltage source Vcc while the drain is connected to the drain of Mn 2 . The gate of Mn 2  is connected to the drain of a trigger enhancing NMOS Mn 0  while the source of Mn 2  is connected to Vcc. 
   The source of the trigger enhancing NMOS Mn 0  is connected to the second voltage source, Vss, typically ground, as is the channel substrate for all the NMOS devices. The gate of Mn 0  is connected to the first end of a resistor R whose second end is connected to a first voltage source, Vcc. The first end of resistor R and the gate of Mn 0  are also connected to the first end of a capacitor whose other end is connected to a second voltage source, Vss or ground. 
   When a positive ESD event takes place at the I/O pin  110  with respect to Vcc, the energy is transferred through diode D 2  and through the parasitic drain to gate capacitance of Mn 1  turning it on. The energy then appears on Vcc which enables Mn 0  to turn on after a time delay determined by the RC time constant. This grounds the gate of Mn 2  after a suitable delay turning it off to complete the discharge cycle. 
     FIG. 5A  is a simplified schematic of the embodiment of the invention clamping ESD energy to the second voltage source, Vss, or ground by means of the ESD clamping element  130 . The clamp is again shielded from the input pin by diode D 2 . 
     FIG. 5B  illustrates the schematic details of this embodiment of the invention. The I/O pin  110  is connected to the anode of D 2  and cathode of D 1  with the anode of D 1  connected to a second voltage source, Vss, typically ground. The cathode of diode D 2  is connected to the source of NMOS Mn 3 . The gate of Mn 3  is connected to the first voltage source, Vcc, and the drain to the drain of the NMOS Mn 4 . The gate of Mn 4  is connected to the drain of NMOS Mn 0  and the source is connected to the second voltage source, or ground. 
   The source of Mn 0  is connected to the second voltage source, Vss or ground, while the gate is again connected to the first end of a resistor R and the first end of a capacitor C. The second end of the resistor R is connected to the first voltage source, Vcc, and the second end of the capacitor is connected to the second voltage source Vss, typically ground. 
   Since the device substrate is grounded, the parasitic Mn 3  source to substrate diode D 3  is noticed effectively in electrical parallel with diodes D 1  and D 2  as shown in  FIG. 5B . The combined diode effect on I/O pin loading is still substantially lower than for the ESD clamp  130  if it were unshielded. 
   The circuit turn on is similar to that described above, but with the ESD energy being shunted to Vss or ground through Mn 3  and Mn 4  until Mn 4  is turned off by the dynamic gate action of Mn 0 . 
   Another embodiment of the invention is shown in  FIGS. 6A and 6B .  FIG. 6A  shows the ESD clamp  120  to the first voltage source, Vcc, and the ESD clamp  130  to the second voltage source or ground. This embodiment incorporates the protection elements of ESD energy from I/O pin  110  to Vcc and from the I/O pin  110  to the second voltage source, Vss or ground. Both ESD clamps are shielded from the I/O pin  110  by diode D 2  which essentially reduces the capacitance seen at the I/O pin  110 . 
   The schematic details are shown in  FIG. 6B . This embodiment has the anode of D 2  connected to the I/O pin  110  and to the cathode of diode D 1 . The anode of diode D 1  is connected to a second voltage source, Vss, typically ground. The cathode of diode D 2  is connected to the source of NMOS Mn 1  and the source of NMOS Mn 3 . 
   Since the device substrate is tied to the second voltage source, Vss or ground, the parasitic junction diode D 3  of the source to substrate junction of NMOS Mn 3  is essentially in parallel with diodes D 1  and D 2 . The cathode of parasitic diode D 3  is essentially connected to the cathode of D 2 , and the anode of D 3  is essentially connected to the second voltage source or ground. 
   The drain of NMOS Mn 1  is connected to the drain of NMOS Mn 2 , the second NMOS in the series string of the ESD clamp  120 . The gate of Mn 1  is tied to the first voltage source Vcc, as is the drain of Mn 2 , and the gate of NMOS Mn 2  is tied to the drain of NMOS Mn 0 . The gate of NMOS Mn 0  is tied to the junction of R and C elements with the second side of the resistor R tied to Vcc and the second side of the capacitor C is tied to the second voltage source Vss or ground. 
   The ESD clamp  130  consists of an NMOS series string Mn 3  and Mn 4 . As previously mentioned, the source of Mn 3  is connected to the cathode of diode D 2  and the source of NMOS Mn 1 . The gate of Mn 3  is tied to the first voltage source, Vcc, and the drain of Mn 3  is connected to the drain of NMOS Mn 4 . The source of Mn 4  is connected to the second voltage source, Vss or ground. The gate of NMOS Mn 4  is connected to the gate of NMOS Mn 0 . 
   The process for creating the embodiment of the invention with clamps to both the first voltage source, Vcc, and to the second voltage source, Vss or ground, is illustrated in  FIG. 7 . 
   Element  60  of the process flow chart of  FIG. 7  illustrates the initiation of the process by creating on a semiconductor substrate the first series pair Mn 1  and Mn 2  and the second series pair Mn 3  and Mn 4 . It also describes the creation of diodes D 1 , D 2 , and D 3 . The diode D 3  is created from the parasitic elements of the third NMOS, Mn 3 , source to substrate junction.  FIG. 7  element  60  also describes the creation of the resistor R and capacitor C components of the RC network, and the trigger enhancing NMOS device Mn 0 , on the same substrate. 
   Continuing with element  62  of  FIG. 7 , the diode network is formed by connecting the anode of the second diode D 2  to the cathode of the first diode D 1  and to the semiconductor I/O circuit  110 . The cathodes of the second and third diodes are connected together and to the source elements of the first and third NMOS elements, Mn 1  and Mn 3 . The process continues by connecting the anodes of the first and third diodes to a second voltage source, Vss, typically ground. 
   Element  64  describes the connection of the source of the special trigger enhancing NMOS Mn 0  as well as the substrate to a second voltage source, Vss or ground, and the gate of Mn 0  to the first ends of the resistor and capacitor. 
   The process continues by connecting the first side of the resistor R to the first side of the capacitor C as well as to the gate of the trigger enhancing NMOS Mn 0  as indicated in  FIG. 7  element  66 . The second side of the resistor R is connected to a first voltage source Vcc and connecting the second side of the capacitor C to a second voltage source Vss or ground completes the RC circuit. 
   Element  68  describes the connecting of the drain of NMOS Mn 1  to the drain of the second NMOS, Mn 2 , and the gate of Mn 1  and source of Mn 2  to a first voltage source, Vcc. The gate of NMOS Mn 2  is connected to the source trigger enhancing NMOS Mn 0 . 
     FIG. 7  element  70  illustrates the formation of the second ESD clamp element  130  by connecting the gate of the third NMOS Mn 3  to a first voltage source, Vcc, connecting the drain of the third NMOS Mn 3  to the drain of the fourth NMOS Mn 4 , connecting the source of the fourth NMOS device Mn 4  to the second voltage source, Vss, typically ground, and connecting the gate of NMOS Mn 4  to the gate of the trigger enhancing NMOS Mn 0 . 
   The test results of the high voltage capability device are shown in table 1 which compares the normal protection device to the invention device. The test conditions are shown in schematic form in  FIGS. 2A through 2C  and  FIGS. 3A and 3B . 
   As can be seen from table 1, the invention device affords the same degree of protection from ESD as indicated by the machine model (MM) and human body model (HBM) test results. The invention provides the additional advantage of shielding the relatively high capacitance of the clamp circuits from the I/O circuits. This enables the invention to be beneficial in applications requiring reduced capacitance such as radio frequency applications and analog transceivers. 
   
     
       
             
           
             
             
             
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Table 1: Measured Body Model (HBM) and Machine Model (MM) 
             
             
               protection for Traditional Analog Pin versus Invention High 
             
             
               Voltage Tolerance (HVT) Analog Pin 
             
           
        
         
             
                 
                 
                 
                 
                 
               Positive 
                 
             
             
                 
                 
                 
                 
                 
               Pin to 
               Negative 
             
             
                 
               PS 
               NS 
               PD 
               ND 
               Pin 
               Pin to Pin 
             
             
                 
               Mode 
               Mode 
               Mode 
               Mode 
               Mode 
               Mode 
             
             
                 
             
             
               Non- 
                 7 KV 
                6 KV 
                7 KV 
                6 KV 
                 7 KV 
                6 KV 
             
             
               HVT 
             
             
               pin 
             
             
               HBM 
             
             
               HVT 
                6.5 KV 
                6 KV 
                7 KV 
                7 KV 
                7.5 KV 
                6 KV 
             
             
               pin 
             
             
               HBM 
             
             
               Non- 
                600 V 
               550 V 
               600 V 
               500 V 
                600 V 
               550 V 
             
             
               HVT 
             
             
               pin MM 
             
             
               HVT 
                550 V 
               550 V 
               600 V 
               650 V 
                650 V 
               550 V 
             
             
               pin 
             
             
               MM 
             
             
                 
             
           
        
       
     
   
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.