Abstract:
A transmission power control device is for use in a radio communication apparatus. The transmission power control device comprises a processing section for processing an input transmission signal into a processed transmission signal in accordance with a control signal. A power amplifier circuit has a first transistor for amplifying the processed transmission signal into a power amplified transmission signal. The transmission power control device further comprises a detecting circuit for detecting a current flowing through the first transistor to produce a current detection signal. A converting circuit converts the control signal into a reference value signal corresponding to a level of the processed transmission signal. A bias current section compares the current detection signal with the reference value signal to produce a comparison result signal. The bias current section controls a bias current for the amplifier circuit in accordance with the comparison result signal.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This Invention relates to a transmission power control device for controlling a transmission power in a radio communication apparatus such as a portable telephone.  
           [0002]    In general, a portable telephone cannot operate without a battery which is used as a power source. In order to lengthen a talk time of the portable telephone, it is necessary to reduce a current consumption as little as possible in the portable telephone. During a transmission (conversation), the current is mostly consumed in a transmission power amplifier (high frequency power IC) in the portable telephone. Therefore, it is necessary to reduce the current consumption as little as possible in the transmission power amplifier. The portable telephone may be called a mobile terminal.  
           [0003]    It is known that the portable telephone has a conventional transmission power control device for controlling a transmission power, in order to decrease the current consumption in the portable telephone.  
           [0004]    On the other hand, it is required to vary a transmission power over a range of 80 dB in the portable telephone in order to avoid the near-far problem caused by a distance between a base station and the portable telephone in a CDMA mobile communication system such as IS  95 . When a portable telephone is far from the base station, the portable telephone is inevitably subjected to interference by another portable telephone located near the base station.  
           [0005]    In case where the conventional transmission power control device is used in the portable telephone of the CDMA system, it is difficult to widely vary the transmission power. As a result, it is impossible to lengthen the talk time of the portable telephone as will be described later.  
         SUMMARY OF THE INVENTION  
         [0006]    It is therefore an object of this invention to provide a transmission power control device capable of widely varying a transmission power in a portable telephone of CDMA system, in order to lengthen a talk time of the portable telephone.  
           [0007]    Other objects of this invention will become clear as the description proceeds.  
           [0008]    On describing the gist of this invention, it is possible to understand that a transmission power control device is for use in a radio communication apparatus.  
           [0009]    According to this invention, the transmission power control device comprises (A) processing means for processing an input transmission signal into a processed transmission signal in accordance with a control signal, (B) power amplifying means having a first transistor for amplifying the processed transmission signal into a power amplified transmission signal, (C) detecting means for detecting a current flowing through the first transistor to produce a current detection signal, (D) converting means for converting the control signal into a reference value signal corresponding to a level of the processed transmission signal, (E) bias current means for comparing the current detection signal with the reference value signal to produce a comparison result signal, the bias current means controlling a bias current for the amplifying means in accordance with the comparison result signal.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a block diagram of a conventional transmission power control device in a portable telephone:  
         [0011]    [0011]FIG. 2 is a block diagram of a transmission power control device according to a preferred embodiment of this invention;  
         [0012]    [0012]FIG. 3 shows a view for describing a characteristic of the power amplifier.  
         [0013]    [0013]FIG. 4 is a circuit diagram for illustrating a power amplifier and a bias current detecting circuit of the transmission power control device illustrated in FIG. 2;  
         [0014]    [0014]FIG. 5 is another circuit diagram for illustrating a power amplifier and a bias current detecting circuit of the transmission power control device illustrated in FIG. 2; and  
         [0015]    [0015]FIG. 6 is a circuit diagram for illustrating a converting circuit of the transmission power control device illustrated in FIG. 2.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0016]    Referring to FIG. 1, a conventional transmission power control device will be described at first in order to facilitate an understanding of this invention. In the example being illustrated, the illustrated transmission power control device is for use in a mobile station or terminal such as a portable telephone. The transmission power control device comprises an HPA saturation output control circuit  3  in FIG. 1. The portable telephone uses a multi-valued digital modulation such as 16-value QAM. Supplied with an analog multi-level signal having inphase (I) and quadrature (Q) components as an input transmission signal, a multi-valued QAM modulator  1  modulates the input transmission signal into modulated transmission signal. The modulated transmission signal is amplified into an amplified signal by a power amplifier (HPA)  2  to be transmitted as an output transmission signal through an antenna ANT by a transmission power.  
         [0017]    The input transmission signal is further supplied to the HPA saturation output control circuit  3 . The HPA saturation output control circuit  3  comprises a recognition circuit  3   a  and a bias control circuit  3   b . Supplied with the input transmission signal, the recognition circuit  3   a  identifies where input symbols of the input transmission signal are located on a phase plane, in order to produce a recognition signal representative of locations of the input symbols. In accordance with the recognition signal, the recognition circuit  3   a  determines a peak level or value of each input symbol to supply the bias control circuit  3   b  to a peak level signal representative of the peak level of each input symbol. On the basis of the peak signal, the bias control circuit  3   b  supplies an optimum bias value to the power amplifier  2 .  
         [0018]    As readily understood from the above description, the HPA saturation output control circuit  3  controls the bias of the power amplifier  2  in accordance with the input transmission signal. As a result, an average current consumption is diminished in the power amplifier  2  on transmitting the multi-level digital signal.  
         [0019]    However, it is impossible to widely vary a transmission power of the portable telephone over 80 dB in CDMA system inasmuch as the transmission power control device controls the bias of the power amplifier  2  in accordance with the peak level of each input symbol. As a result, it is difficult to lengthen a talk time of the portable telephone in case where the portable telephone has the transmission power control device illustrated in FIG. 1.  
         [0020]    Referring to FIG. 2, description will proceed to a transmission power control device according to a preferred embodiment of this invention.  
         [0021]    The illustrated transmission power control device comprises a variable gain intermediate frequency (IF) amplifier  11 . The variable gain IF amplifier  11  is supplied with an input IF signal Sa to variably amplify the input IF signal Sa into an amplified IF signal in accordance with a gain control signal Sb. The amplified IF signal is supplied to a mixer  12 . The mixer  12  is connected to a local oscillator  13  to be supplied with a local oscillation signal. The mixer  12  mixes the local oscillation signal in the amplified IF signal to produce a high frequency signal having a predetermined frequency.  
         [0022]    The high frequency signal is supplied to band-pass filter (BPF)  14 . The BPF  14  filters the high frequency signal into a filtered signal in order to remove undesired frequencies from the high frequency signal. The filtered signal is delivered to a step-attenuator (ATT)  15 . The step-attenuator (ATT)  15  attenuates the filtered signal into an attenuated signal on the basis of an attenuator control signal Sc. More particularly, the step-attenuator  15  is put into an on-state or an off-state in accordance with the attenuator control signal Sc to produce the attenuated signal. The attenuated signal is inputted to a power amplifier  16  which outputs a transmission power Se in accordance with a bias voltage Sn as will be described later.  
         [0023]    The power amplifier  16  is connected to the power source Vcc through a bias current detecting circuit  17 . As will be described later, a bias current is supplied to the power amplifier  16  through the bias current detecting circuit  17 . Furthermore, the bias current detecting circuit  17  detects the bias current based on the power source Vcc to produce a bias current detection signal Sd representative of the value of the bias current.  
         [0024]    The gain control signal Sb and the attenuator control signal Sc are supplied to a converter circuit  18 . Responsive to the gain control signal Sb and the attenuator control signal Sc, the converter circuit  18  produces a reference value signal Sv representative of a level of the IF signal Sa. In other words, the reference value signal Sv is representative of a reference value of the bias current each time transmission power is varied. The reference value signal is supplied to a subtracter  19 . The subtracter  19  is further supplied with the above-mentioned bias current detection signal Sd. The subtracter  19  subtracts the bias current detection signal Sd from the reference value signal Sv to produce a subtracted signal which is supplied to an integrator  20 . The integrator  20  integrates the subtracted signal during a predetermined time duration to supply the power amplifier  16  with a integrated signal as the bias voltage Sn. The integrated signal is supplied to the power amplifier  16  as the bias voltage Sn shown in FIG. 3. The power amplifier  16  put into operation in a characteristic illustrated in FIG. 3.  
         [0025]    Referring to FIG. 4, description will proceed to an example of the power amplifier  16  and the bias current detecting circuit  17  illustrated in FIG. 2. The bias current detecting circuit  17  comprises a resistor L 1  and a first capacitor C 1 . The power amplifier  16  comprises first and second matching circuits  24  and  15 , first and second coils or inductors L 1  and L 2 , a second capacitor C 2 , and a field effect transistor (FET) Q 1 . More particularly, the matching circuit  24  is composed of a tuning circuit (LC) for supplying the attenuated signal to the gate of the FET Q 1  which amplifies the attenuated signal into the amplified signal. The matching circuit  24  is for matching the input impedance. The matching circuit  25  is connected to the drain of the FET Q 1  in order to match an output impedance. The source of the FET Q 1  is grounded. The drain of the FET Q 1  is connected to coil L 1  which is for preventing the attenuated signal from leakage to the bias current detecting circuit  17 . The coil L 1  may be provided in the bias current detecting circuit  17 . The gate of the FET Q 1  is connected to the coil L 2  and the capacitor C 2 . The coil L 2  is for preventing the attenuated signal from leakage to a bias voltage line. The capacitor C 2  is for bypassing the attenuated signal.  
         [0026]    In the bias current detecting circuit  17 , the resistor R 1  is connected to the power source Vcc and the coil L 1 . The capacitor C 1  is a by-pass capacitor and is connected to a connection point between the resistor R 1  and the coil L 1 . Furthermore, the capacitor C 1  is grounded. A voltage drop based on the resistor R 1  is supplied as the bias current detection signal Sd to the subtracter  19  illustrated in FIG. 2.  
         [0027]    Referring to FIG. 4 in addition to FIG. 2, the attenuated signal is supplied to the power amplifier  16 . In the power amplifier  16 , the attenuated signal is supplied to the gate of FET Q 1  through the matching circuit  24 . Furthermore, the gate of the FET Q 1  is supplied with the bias voltage Sn through the coil L 2  and the capacitor C 2 . The FET Q 1  amplifies the attenuated signal into the amplified signal in accordance with bias voltage Sn to output the amplified signal as the transmission power Se through the matching circuit  25 .  
         [0028]    As described above, the bias current detecting circuit  17  supplies the subtracter  19  with the bias current detection signal Sd which is representative of the drop voltage of the resistor R 1 . The subtracter  19  subtracts the bias current detection signal Sd from the reference value signal Sv to produce the subtracted signal. The integrator  20  produces the bias voltage Sn on the basis of the subtracted signal to supply the bias voltage Sn to the gate of the FET Q 1 .  
         [0029]    In FIG. 4, a large current flows in the resistor R 1  from the FET Q 1 . As a result, it is necessary to make the resistance of the resistor R 1  be very small. When the resistance of the resistor R 1  becomes very small, it is difficult to neglect the resistance of wirings in the power amplifier  16  and the bias current detecting circuit  17 . As a result, the bias current detection signal Sd may have an error. In addition, the characteristic such as a linearity of amplification may be degraded in the power amplifier  16  inasmuch as the source voltage (Vcc) is reduced into a reduced voltage on the basis of the drop voltage of the resistor R 1 .  
         [0030]    Referring to FIG. 5, description will proceed to another example of the power amplifier  16  and the bias current detecting circuit  17  illustrated in FIG. 2.  
         [0031]    In FIG. 5, the power amplifier and the bias current detecting circuit are designated by reference numerals  16 A and  17 A, respectively. The power amplifier  16 A and the bias current detecting circuit  17 A comprise similar parts which are designated by like reference numerals. The power amplifier  16 A comprises a first transistor Q 11  which is for use in power amplification. The first transistor Q 11  may be, for example, an FET. The bias current detection circuit  17 A comprises a second transistor FET Q 12  which is used as an auxiliary transistor. The second transistor Q 12  may be, for example, an FET. In the example being illustrated, the gate width of the second transistor Q 12  is proportionately reduced from that of the first transistor FET Q 11 . The gate width of the second transistor Q 12  is defined to one tenth of that of the first transistor Q 11 . The second transistor Q 12  and the first transistor Q 11  are built on the same semiconductor chip  26 , in order to hold a precisely proportional relationship between the first and the second transistors Q 11  and Q 12 . In other words, a DC bias current passing in the second transistor Q 12  becomes about one tenth of a DC bias current passing in the first transistor Q 11  when a condition of the DC biasing in second transistor Q 12  is same as a condition of the DC biasing current in the first transistor Q 11 .  
         [0032]    The power amplifier  16 A comprises the matching circuit  24  on the input side, the matching circuit on the output side, the first transistor Q 11 , the coil L 1 , the coil L 2 , and a capacitor C 2 . In the power amplifier  16 A, the source of the first transistor Q 11  is grounded and the drain of the first transistor Q 11  is connected to the power line (Vcc) through the coil L 1 . The power amplifier  16 A comprises the capacitor C 4  which is used as a bypass capacitor for a high frequency signal. In the bias current detecting circuit  17 A, the source of the second transistor Q 12  is grounded. The resistor R 1  and the capacitor C 1  are located between the drain of the second transistor Q 12  and the power line (Vcc). The capacitor C 1  is used as a bypass capacitor for a high frequency signal. The drop voltage of the resistor R 1  is supplied as the bias current detection signal Sd to the subtracter  19  illustrated in FIG. 2.  
         [0033]    Referring to FIG. 5 in addition to FIG. 2, the power amplifier  16 A is supplied with the attenuated signal. In the power amplifier  16 A, the attenuated signal is supplied to the gate of the first transistor Q 11  through the matching circuit  24 . Furthermore, the bias voltage Sn is supplied to the gate of the first transistor Q 11  through the coil L 2  and a capacitor C 2 . The first transistor Q 11  amplifies the attenuated signal into the amplified signal in accordance with the bias voltage Sn to output the amplified signal as the transmission power Se through the matching circuit  25 .  
         [0034]    As described above, the gate width of second transistor Q 12  is defined to one tenth of FET Q 11 . As a result, the DC bias current passing in the second transistor Q 12  becomes about one tenth of the DC bias current passing in the first transistor Q 11  when the condition of the DC biasing in second transistor Q 12  is same as a condition of the DC biasing in the first transistor Q 11 .  
         [0035]    In accordance with the bias voltage Sn, the current flows to the drain of the second transistor Q 12  through the resistor R 1 . The voltage drop occurs in the resistor R 1 . The drop voltage is supplied as the bias current detection signal Sd to the subtracter  19  illustrated in FIG. 2. As described above, the subtracter  19  subtracts the bias current detection signal Sd from the reference value signal Sv to produce subtracted signal. The integrator  20  supplies the bias voltage Sn to the gate of the first transistor Q 11  in accordance with the subtracted signal.  
         [0036]    In FIG. 5, a current flows to the resistor R 1  from the second transistor Q 12 . As described above, the current flowing in the second transistor Q 12  is equal to one tenth of the current flowing in the first transistor Q 11 . As a result, it is possible to make the resistance of the resistor R 1  be large. It is possible to neglect the resistance of wirings in the power amplifier  16 A and the bias current detecting circuit  17 A. The bias current detecting signal seldom has the error. In addition, the characteristic such as the linearity of amplification is not degraded in the power amplifier  16  inasmuch as the resistor R 1  is not connected to the drain of the first transistor Q 11 .  
         [0037]    Referring to FIG. 6, description will proceed to an example of the converting circuit  18  illustrated in FIG. 2. The converting circuit  18  comprises a read-only-memory (ROM)  27  and an analog-digital (A/D) converter  28 . The converting circuit  18  is supplied with the gain control signal Sb and the attenuator control signal Sc as addresses. In the example being illustrated, each of the the gain control signal Sb and the attenuator control signal Sc has a digital signal form. The ROM  17  has a conversion table for producing the reference value signal Sv in response to the gain control signal Sb and the attenuator control signal Sc. More particularly, the ROM  27  has the conversion table containing data of the reference value signal Sv as reference data of bias current points. The bias current points are representative of levels of the input IF signal. The reference data in the conversion table corresponds to the characteristic of the power amplifier  16  that is illustrated in FIG. 3. As described above, the reference value signal Sv is representative of the reference value of the bias current of the FET Q 1  (Q 11 ). The A/D converter  28  converts the reference value signal Sv into a analog reference value signal which is supplied to the subtracter  19  illustrated in FIG. 2.  
         [0038]    As readily understood from the above-mentioned description, the bias current point of the power amplifier  16  ( 16 A) varies in accordance with the attenuated signal. Therefore, the current consumption decreases in the power amplifier in correspondence to the bias current point on decreasing the transmission power Se. As a result, the power amplifier  16  ( 16 A) always operates in the bias voltage Sn which is most appropriate to the transmission output power Se.  
         [0039]    Although the amplified IF signal Sa is converted into the high frequency signal by the mixer  12  and the local oscillator  13  in the above-mentioned embodiment, the mixer  12  and the local oscillator  13  may be unnecessary. In addition, either one of the variable gain amplifier  11  and the attenuator  15  may be unnecessary. In case where the variable gain amplifier  11  is unnecessary, the converting circuit  18  produces the reference value signal Sv in accordance with only the attenuator control signal Sc. In case where the attenuator  15  is unnecessary, the converting circuit  18  produces the reference value signal Sv in accordance with only the gain control signal Sb.  
         [0040]    Although the transmission power control device has the subtracter  19  for subtracting the bias current detection signal from the reference value signal in the above-mentioned embodiment, the transmission power control device may have an adder instead of the subtracter  19  for carrying a sum of the bias current detection signal and the reference value signal, in order to compensate the reference value signal in accordance with the current flowing in the FET Q 1 (Q 11 ). In addition, the transmission power control device may have a comparator circuit and a voltage variable amplifier instead of the subtracter  19 . The comparator circuit comparates the reference value signal with the bias current detection signal to produce a comparison result. The voltage variable amplifier amplifies the reference value signal in accordance with the comparison result. Furthermore, an EEPROM) is used instead of the ROM.  
         [0041]    While this invention has thus far been described in conjunction with the preferred embodiments thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners.