Abstract:
A frequency offset compensation method has the steps of raising the detected signal to the M-th power to remove a modulation factor from the received signal, and accumulating the M-th power signals for N (N is an integer) symbols to derive a phase component of the accumulated M-th power signals. Then, the derived phase component is divided into M so as to obtain an estimation value with respect to phase shift due to frequency offset which represents frequency deviation from a true carrier frequency contained in the received signal, and the received signal is multiplied by the obtained estimation value in a form of conjugate complex number to remove the phase shift due to the frequency offset from the received signal.

Description:
This application is a continuation-in-part of application Ser. No. 08/066,242 filed May 25, 1993 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method of compensating frequency offset of a received phase shift keyed signal which may occur in any of digital mobile radio communication systems such as a digital car telephone system, a digital portable telephone system and a digital cordless telephone system. 
     2. Description of the Related Art 
     In a generic phase shift keying system, termed &#34;M-ary Phase Shift Keying&#34; (MPSK), M indicates the number of information phases. Thus, in the case of a Binary Phase Shift Keying System (BPSK) M=2, and in the case of a π/4 Quadrature Phase Shift Keying System (QPSK) and a π/4 Differential Quadrature Phase Shift System (DQPSK), M=4. M is defined as M=2 N , where N is an integer larger than zero (N&gt;0). 
     Recently, various new digital radio techniques have been studied, developed and put to practical use, for the promotion of digitizing land mobile communication systems such as a car telephone system and a cordless telephone system. For example, a π/4 shift QPSK technique, which is one of several phase shift keying methods having high efficiency of frequency usage, will be adopted for use in a digital car telephone system, a cordless telephone system and a portable telephone system of the next generation. 
     In the case of a land mobile communication system, since its transmission path will be a Rayleigh fading communication path in which the amplitude and phase of the signals change substantially with respect to time, it is quite difficult to carry out a coherent detection, which includes determination of a reference carrier and a phase-shifted and information signal recovered from the received signal. 
     For the Rayleigh fading communication path, therefore a differential detection (delay detection) method which does not need the recovered reference carrier but detects the phase difference between two symbols may be advantageously used. However, even in this differential detection method, the bit error rate performance will be deteriorated by phase shift due to frequency offset. Such frequency offset might be caused by instability of an oscillator installed in a transmitter/receiver in mobile stations or in base stations. Many studies and developments with respect to compensation of the frequency offset have been carried out. However, according to the conventional art, the construction of the compensation circuit would become complicated and also the compensable amount of frequency offset would be limited to a frequency offset which corresponds to a phase shift of 2π due to phase ambiguity. 
     In order to suppress the generation of frequency offset itself in a small value, it is necessary to make frequency oscillators in the base stations and in the mobile stations with high accuracy, causing the manufacturing cost of the oscillators to increase. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a frequency offset compensation method for phase shift keying which uses a differential detection scheme. 
     Another object of the present invention is to provide a frequency offset compensation method which can eliminate the upper limitation of the compensable amount of the frequency offset. 
     According to the present invention, a frequency offset compensation method is provided. This method will be adopted in a digital mobile communication system employing a differential detection scheme as a demodulation method. The method has the steps of raising the detected signal to M-th power to produce an unmodulated signal, accumulating such unmodulated signals for a period of N (N is an integer) symbols to derive a phase component of the accumulated signal raised to the M-th power, dividing the derived phase component into M so as to obtain an estimation value with respect to phase shift due to the frequency offset which represents frequency deviation from a true carrier frequency contained in the received signal, and multiplying the received signal by the obtained estimation value in the form of a conjugate complex number to remove from the received signal the phase shift due to the frequency offset. 
     Accordingly, the frequency offset can be easily compensated which may mostly decrease the bit error rate performance. 
     However, this compensation method is effective only when the phase shift due to the frequency offset is within a range from -π/M to π/M and thus uncertainty may occur if the phase shift exceeds this range. In other words, since the estimation value of the phase shift is calculated as a value between -π and π, a phase shift larger than π/M contained in the received signal prior to the M-th power operation cannot be detected by this M-th power operation. 
     Therefore, it is preferred that, at a transmitting side, information phase data sequence to be transmitted is differentially encoded twice. Thus, the phase ambiguity problem of the estimated phase shift can be easily removed without adding complex circuitry. 
     In the case of a π/4 shift QPSK system, it is preferred that the method has, at a transmitting side, the steps of differentially encoding the information phase data sequence to be transmitted in the form of QPSK to produce a first encoded data sequence, adding π/4 to the first encoded data sequence to produce a π/4 shifted data sequence, and differentially encoding the π/4 shifted data sequence to produce a transmission signal. 
     Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a demodulator at a receiving side as a preferred embodiment according to the present invention; 
     FIG. 2 shows an example of a double differential encoding system at the transmitting side; 
     FIG. 3 shows another example of a double differential encoding system at the transmitting side; 
     FIG. 4 is a flowchart representing the method performed by a combination of an M-ary double differentially coded transmission as shown in FIG. 2 used with the receiving method of the apparatus shown in FIG. 1; and 
     FIG. 5 is a flow chart representing the method performed by a combination of a QPSK transmission used with the receiving method of the apparatus shown in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows, as a preferred embodiment of the present invention, a demodulator for demodulating an MPSK (M-Phase Shift Keying) signal wave which has information in the phase difference between two symbols. This demodulator has functions of not only delay detection and differential decoding but also of frequency offset compensation. 
     In FIG. 1, reference numeral 10 denotes an intermediate frequency (IF) band pass filter, 11 is a multiplier with one input connected to the output of the IF filter 10, and 12 is a one-symbol delay circuit inserted between the output of the IF filter 10 and the other input of the multiplier 11. 
     A low pass filter 13 is connected to the output of the multiplier 11. To the output of the low pass filter 13, an A/D converter 14 and a clock regenerator 15 are connected in series. A first output of the clock regenerator 15 is connected to a phase compensation circuit 16, whereas a second output of the regenerator 15 is connected to an N-symbols delay circuit 17. The output of the phase compensation circuit 16 is connected to one input of a multiplier 18, and the output of the delay circuit 17 is connected to the other input of the multiplier 18. To the output of the multiplier 18, a decision circuit 19, a differential decoder 20 and a parallel-serial converter 21 are connected in series. 
     Hereinafter, operation of the device shown in FIG. 1 will be described in detail. 
     Received signal S r  is applied to the IF filter 10, and then the output signal S 10  from the filter 10 is multiplied, at the multiplier 11, by a signal S 12  from the delay circuit 12, which is delayed for one symbol period. Then the multiplied signal S 11  from the multiplier 11 is applied to the low pass filter 13. By this filter 13, harmonic wave components will be removed from the multiplied signal S 11  and thus only the baseband component thereof will be outputted as a signal S 13 . 
     The output signal S 13  from the filter 13 is applied to the A/D converter 14 which samples the input signal S 13  a number of times Ns per one symbol period. The output signal from the A/D converter 14 is applied to the clock regenerator 15 so that an optimum sampled value will be detected. The signal S 15  detected at the optimum sampling point is then applied to the phase compensation circuit 16. 
     The phase compensation circuit 16 raises the sampled value to M-th power and then accumulates the M-th power values for an N number of N symbols so as to derive the phase component therefrom. Then the phase compensation circuit 16 obtains an estimation value with respect to phase shift amount owing to the frequency offset by dividing the derived phase component by M. 
     Since the phase compensation circuit 16 uses N symbols for estimating phase shift due to the frequency offset, the output signal S 15  including information is delayed for N symbol periods by the delay circuit 17 and then applied to the multiplier 18 as a signal S 17 . At the multiplier 18, the signal S 17  and the output signal S 16  from the phase compensation circuit 16 are multiplied with each other to produce a multiplied signal S 18  which will not include any phase shift due to the frequency offset. The signal S 18  is then applied to the decision circuit 19 and thus precise phase difference information can be obtained. 
     Hereinafter, the above-mentioned operation with respect to the frequency offset compensation will be theorized. 
     If r(i) represents a sampled value of the delay detection output r(t) of the received signal at a sampling point t=iT s  (this sampling point is estimated by the clock regenerator 15) and s(i) represents the M-th power of r(i), the sampled value s(i) at the sampling point t=iT s  is given as follows: 
     
         s(i)=r(i).sup.M                                            (1) 
    
     wherein Ts is the length of time necessary for transmitting one symbol (Ts=1/(symbol rate), and i is an optional integer identifying an arbitrary sampling time (for example r (i) represents a differentially detected output signal at i-th sampling time). Since r(i) is raised to the M-th power the information phase component in the MPSK signal wave can be removed so as to derive a value of the phase shift due to frequency offset. 
     If S(f) represents a frequency response of s(i), S(kf) is given as a discrete Fourier transformation of s(i). ##EQU1## where N represents the number of the symbols expanded by the discrete Fourier transformation (DFT) and k represents the degree of the harmonic wave. 
     Since the phase shift due to the frequency offset is considered to kept constant for N symbols, it will be appear as a direct current component f=0 Hz on the frequency axis. As the direct current component S(0) of S(f) is given by the next equation (3), an estimation value Δω&#39;T s  of the phase shift due to the frequency offset can be obtained by the following equation (4). ##EQU2## 
     The phase shift due to the frequency offset contained in the received signal can be eliminated by carrying out the following calculation using this estimation value. ##EQU3## where R(i) represents the amplitude component of the differential detection output r(i), θ(i) represents phase difference information at the sampling point t=iT s , and Δf=Δω/2π represents a true frequency offset amount, respectively. 
     As will be apparent from the formula (5), if this estimated offset amount Δω&#39; is substantially equal to the true frequency offset amount Δω, the following relationship will be formed. 
     
         z(i)≅R(i)exp{jθ(i)}                        (6) 
    
     From the equation (6), the phase difference information θ(i) can be precisely detected. 
     If an estimation value of the phase shift is calculated from the above-mentioned method, ambiguity of the estimated value caused by the M-th power operation may become an issue. In other words, in a case that frequency offset Δω of the received signal is greater than π/MT s , there will be an ambiguity α (α is an optional variable satisfying the value π/M&gt;α&gt;0) in the estimated phase shift. If the phase shift αωT s  is represented as 
     
         ΔωT.sub.s =α+π/M                      (7) 
    
     the M-th power value thereof is expressed as follows. 
     
         MαωT.sub.s =Mα+π                      (8) 
    
     From the equation (4), an estimation value αω&#39;T s  of the phase shift is restricted as -π/M&lt;αω&#39;T s  &lt;π/M. Thus, this estimation value will be practically calculated, from the equation (7), as αω&#39;T s  =α-π/M. Therefore, the differential detection output of which phase shift due to the frequency offset has been modified by using the equation (5) will have a phase error of (αω-αω&#39;)T s  =2π/M, causing the error rate to increase to about 1/2. 
     In order to prevent such phase ambiguity in the estimated value of the phase shift owing to the frequency offset from being issued, it is preferred that double differential encoding are performed against the information phase data sequence at the transmitting side. 
     FIG. 2 shows an example of a double differential encoding system at the transmitting side. This system is substantially constituted by a first differential encoder 22 and a second differential encoder 23 connected in series. Each of the differential encoders 22 and 23 consists of a multiplier with two inputs and an output, and a one-symbol delay circuit with an input connected to the output of the multiplier and with an output connected to one of the inputs of the multiplier. In each of the encoders, differential encoding is effected by adding a current phase information to a differentially encoded signal prior to one-symbol. It should be noted that if an input signal applied to the differential encoder is represented by e j φ(t), the multiplier thereof will operate as an adder with respect to its phase component. 
     Such double differential encoding system is known and, for example, described in &#34;On the Implementation and Performance of Single and Double Differential Detection Schemes&#34;, by Marvin K. Simon and Dariush Divsalar, IEEE Transaction on Communication, Vol. 40, No. 2, pages 278-291, February 1992. 
     Phase information data sequence θ={θ 0 , θ 1 , θ 2 , . . . θ i  } is applied to the first differential encoder 22 to produce a differentially encoded phase information sequence φ={φ 0 , φ 1 , φ 2  . . . φ i  } (Signal S 22 ) represented in an equation (9) which will be described later. Then the signal S 22  is inputted into the second differential encoder 23 to produce a differentially double encoded phase information sequence Ψ={Ψ 0 , Ψ 1  Ψ 2 , . . . Ψ i  } (signal S 23 ) represented in an equation (10) which will be described later, and a signal S i  (t) shown in an equation (11), which will also be described later, is transmitted to the receiving side. 
     At the receiving side, an output signal S 19  from the aforementioned decision circuit 19 shown in FIG. 1 will be applied to the differential decoder 20 as a differential encoded information phase signal. In the decoder 20, decoding operation as shown in an equation (20) which will be described later is executed and thus the differentially decoded signal S 20  is outputted as a parallel information data sequence. Finally, the decoded output S 20  from the decoder 20 is applied to the parallel-serial converter 21 to produce a converted serial information data sequence S 21 . 
     Hereinafter, the above-mentioned operation with respect to elimination of phase ambiguity will be theorized. 
     If input information phase data sequence is represented by θ={θ 0 , θ 1 , θ 2 , . . . , θ i  }, information phase φ i  after first differential encoding and information phase Ψ i  after second differential encoding are respectively expressed as follows. 
     
         φ.sub.i =φ.sub.i-1 &gt;θ.sub.i                  (9) 
    
     
         Ψ.sub.i =Ψ.sub.i-1 &gt;φ.sub.i                    (10) 
    
     If the transmission signal S i  (t) is represented as 
     
         S.sub.i (t)=A cos (ω.sub.c t+Ψ.sub.i)            (11) 
    
     wherein A is an arbitrary factor, a differential detection baseband output B i  (t) which does not contain a harmonic wave component will be represented as follows. It should be noted that this output B i  (t) corresponds to the signal S 13  from the low pass filter 13 shown in FIG. 1. ##EQU4## In order to clarify the equation (12), noise components are ignored. 
     In the differential detection system, in general, ω c  and T s  are determined as ω c  T s  =2nπ. However, if a frequency offset of ΔωT s  is generated due to instability of the frequency oscillator, the equation (12) will be represented as the following equation (13). 
     
         B.sub.i (t)=A.sup.2 /2·cos (ΔωT.sub.s +Ψ.sub.i -Ψ.sub.i-1)                                           (13) 
    
     This equation can be expressed, by using the equation (10), as follows. 
     
         B.sub.i (t)=A.sup.2 /2·cos (ΔωT.sub.s +φ.sub.i)(14) 
    
     Then ΔωT s  is estimated by multiplying B i  (t) of the equation (14) by M. Since Mφ i  becomes equal to 2nπ, the estimation value will be obtained with respect to MαωT s . If Δω&#39;T s  is given as 
     
         Δω&#39;T.sub.s =α+π/M                     (15) 
    
     estimation value MB i  (+) will be MΔω&#39;T s  =Mα+π, and will be represented, by using the modulo 2π, as follows. 
     
         Mαω&#39;T.sub.s =-(π-Mα)                  (16) 
    
     Dividing the equation (16) by M, the estimation value D of phase shift due to the frequency offset is obtained as follows. 
     
         D=-(π-Mα)/M                                       (17) 
    
     Using this estimated value D, the equation (14) is compensated as follows. ##EQU5## 
     The output phase after the differential detection will be represented as follows. 
     
         φ&#39;.sub.i =φ.sub.i +2π/M                         (19) 
    
     The decision output of the information phase data sequence θ i  after the decoding operation which is opposite to the first differential encoding of the equation (9) will be expressed as follows. ##EQU6## 
     Accordingly, the frequency offset can be precisely compensated without producing ambiguity of the estimated phase. 
     Although the above-mentioned double differential encoding method will be utilized in a general phase shift keying (MPSK) system, the present invention can be used also in a π/4 shift QPSK system as follows. 
     FIG. 3 shows another example of a double differential encoding system at the transmitting side. Although the above-mentioned double differential encoding system of FIG. 2 will be utilized in a general M-ary Phase Shift Keying (MPSK) system, this system of FIG. 3 can be used in a π/4 shift Quadrature Phase Shift Keying (QPSK) system. 
     The double differential encoding system shown in FIG. 3 is constituted by a parallel-serial converter 24, an information phase mapping circuit 25, a first differential encoder 26 and a second differential encoder 27, connected in series. 
     In the parallel-serial converter 24, input binary information data sequence is serial-parallel converted so as to assign two bits for each symbol, as shown in a part of FIG. 3. Then, in the phase mapping circuit 25, phase information 0, π, and ±π/2 are mapped to each of the symbol as follows: 
     
         ______________________________________X.sub.i        Y.sub.i                θ.sub.i______________________________________1              1     π0              1     π/20              0     01              0     -π/2______________________________________ 
    
     Thereafter, the information phase data sequence θ i  is differentially encoded in the first differential encoder 26 which has the same constitution as that of the differential encoder 22 or 23 in FIG. 2, as follows: 
     
         φ.sub.i =φ.sub.i-1 ×θ.sub.i            (21) 
    
     The constitution of the second differential encoder 27 itself is known for example by &#34;Timing Recovery Techniques for Digital Cellular Radio with π/4-DQPSK Modulation&#34;, by Ging-shing Liu and Che-Ho Wei, IEEE Int. Conf. Commun. pages 319-323, 1992. In this second differential encoder 27, differential phase φ i  of the equation (21) is substituted into the next equations, so as to obtain a differentially double encoded π/4 shift QPSK signal. ##EQU7## 
     Such double differentially encoded QPSK signal is transmitted to the receiving side. At the receiving side, the same phase shift compensating operation is performed, and then differential decoding of an equation (23) which is the same as the equation (20) is performed. 
     
         θ.sub.i =φ.sub.i -φ.sub.i-1                  (23) 
    
     FIGS. 4 and 5 are flow charts which show methods performed by communication systems employing, respectively, a general M-ary coded transmission as shown in FIG. 2 and a QPSK transmission shown in FIG. 3. 
     Thus, the frequency offset can be precisely compensated without producing ambiguity of the estimated phase shift. In other words, the transmitted data sequence can be correctly detected. 
     Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.