Abstract:
This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.

Description:
BACKGROUND 
       [0001]    The technical field relates to devices having both a capacitive and resistive functions, and methods of incorporating such devices in organic dielectric laminates and printed wiring boards. 
         [0002]    Capacitors and resistors may be used in series for transmission line termination of signal traces extending between integrated circuit (IC) devices. The capacitors and resistors are used to match the impedance of an IC device to a line, or to reduce or eliminate signal reflection. Some circuits are continuous load and use a resistor in parallel with the line. Non-continuous load circuits have a resistor and capacitor in series and are useful for low power ICs.  FIG. 1  schematically illustrates a non-continuous load termination of IC devices  10  and  20 . 
         [0003]    In  FIG. 1 , the distance from a to b is typically short. The value of the resistor R is chosen to match the line impedance and is typically about 45-80 ohms. The value of the capacitor C is chosen so that the RC time constant of the resistor R and the capacitor C in series is greater than the rise time of a signal and less than the total time of the signal pulse. Typical capacitance values are on the order of 30 picoFarads. 
         [0004]    Conventional RC terminations are typically constructed of a surface mount technology (SMT) resistor and capacitor.  FIG. 2  is a cross section view of a portion of a printed circuit board  25  having a SMT resistor  40  and a SMT capacitor  50  connected to an IC device  30  to form a conventional SMT RC transmission line termination for the IC  30 . The signal line carrying the signal to the IC  30  is connected to a circuit trace  60  connecting the IC device  30  to the resistor  40 . The capacitor  50  is coupled to a circuit trace  70  by one of a pair of solder pads  52  and solder joints  58 . The resistor  40  is coupled to the circuit trace  70  by a solder pad  42  and a solder joint  48 . The capacitor  50  is coupled to a via hole  80  by the other solder pad  58  and a circuit trace  59 . This arrangement places the resistor  40  and the capacitor  50  in series with the signal line and connected to ground through a plated through-hole via  80 . This conventional surface mount approach requires use of valuable surface real estate. Further, the requirement for solder joints reduces reliability and increases costs of fabrication. 
       SUMMARY OF THE INVENTION 
       [0005]    According to a first embodiment, a capacitive/resistive device comprises a first electrode, a dielectric disposed over the first electrode, a resistor element disposed over a second electrode and adjacent to the dielectric wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0. The capacitive/resistive device can be embedded in organic dielectric laminates, and incorporated in printed wiring boards. 
         [0006]    According to the above embodiment, both the resistor and the capacitor functions may be integrated into a single buried laminate, reducing the cost and difficulty in creating the resistor and capacitor functions. When the capacitive/resistive device is incorporated in a printed wiring board, embedding the capacitive/resistive device also frees up valuable real estate. Further, solder joints associated with SMT devices may be eliminated, thereby improving reliability. The capacitive/resistive device can be processed using conventional etching processes, further reducing production costs. 
         [0007]    Those skilled in the art will appreciate the above stated advantages and other advantages and benefits of various additional embodiments of the invention upon reading the following detailed description of the embodiments. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The detailed description will refer to the following drawings, wherein like numerals refer to like elements, and wherein: 
           [0009]      FIG. 1  is a schematic illustration of a conventional (prior art) non-continuous load termination having a resistor and capacitor in series. 
           [0010]      FIG. 2  is a cross section view of a printed wiring board having a conventional (prior art) SMT RC transmission line termination for an integrated circuit device. 
           [0011]      FIG. 3  is a section view of a portion of a printed wiring board having an embedded capacitive/resistive device. 
           [0012]      FIGS. 4A-4F  illustrate a method of making a laminate structure including the capacitive/resistive device illustrated in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Embodiments of the present invention are addressed to capacitive/resistive devices that may be buried in the substrate of a printed wiring board (PWB). Providing the capacitive and resistive functions within the PWB substrate conserves valuable surface real estate on the printed wiring board. The embodiments of the present invention also require fewer solder joints than conventional SMT termination arrangements. 
         [0014]      FIG. 3  is a section view of a portion of a printed wiring board  2000 . The printed wiring board section  2000  includes an RC transmission line termination in which the resistor function and the capacitor function are integrated into a single capacitive/resistive device  200 . The device  200  comprises a bottom electrode  210 , a dielectric  220 , a resistor element  230 , a top electrode or top plate  240 , and a conductive trace  245 . The device  200  provides a resistive and a capacitive function in a single laminate structure, generally indicated by the bracket  201 . The device  200  is coupled to an IC device  270  by the conductive circuit trace  245 , a plated through hole via  250  extending through a dielectric layer  280 , and a conductive circuit trace  260 . The IC device  270  may be connected to the conductive circuit trace  260  by a solder pad  272  and a solder joint  274 . A conductive circuit trace  211  may extend from the bottom electrode  210  for connection to other circuitry. 
         [0015]      FIGS. 4A-4F  illustrate a method of making a laminate including the device  200 .  FIG. 4A  is a section view in front elevation of a first stage of manufacture in which first and second metallic foils  212 ,  242  are provided. The second metallic foil  242  is provided with a layer of resistor material  232 . The resistor material  232  can be, for example, NiP, CrSi, NiCr or other electrically resistive materials that can be plated or sputtered over the surface of the second metallic foil  242 . The first and second metallic foils  212 ,  242  can be made from, for example, copper, copper-based materials, and other metals. 
         [0016]    A polymer solution may be cast or coated onto the first foil  212  and cured, forming a first dielectric layer  222 . A similar, second dielectric layer  226  may be formed in a similar manner on the second foil  242 , over the surface of the layer of resistor material  232 . The polymer solution may be formed from, for example, epoxy, polyimide or other resins in a suitable solvent. 
         [0017]    A thin adhesive layer  227  may be applied to one or both surfaces of either of the dielectric layers  222 ,  226  (shown in  FIG. 4A  on the layer  222 ). The adhesive layer  227  may be formed from, for example, a thermoplastic polymer. The two structures are then laminated together in the direction of the arrows shown in  FIG. 4A . 
         [0018]    Referring to  FIG. 4B , lamination forms a single dielectric  220  from the layers  222 ,  226  and  227 . The adhesive layer  227  facilitates joining of the dielectric layers  222  and  226  during the lamination process. The adhesive layer  227 , however, may be dispensed with if the dielectric layers  222  and  226  are only partially cured prior to lamination, or, are of a thermoplastic nature so that upon lamination a suitable temperature and pressure will sufficiently soften the resin so that the layers  224  and  226  bond without adhesive. The structure shown in  FIG. 4B  may also be formed by casting a polymer solution onto only one of the foils  212 ,  242  and laminating the other foil to the cast polymer solution. Yet another alternative method would be to form a free-standing film of the polymer  220  and laminate foils  212  and  242  to both sides of the polymer film  220 . 
         [0019]    A photoresist (not shown in  FIG. 4B ) is applied to the foil  212  and the photoresist is imaged and developed. The foil  212  is then etched, and the remaining photoresist stripped using standard printing wiring board processing conditions.  FIG. 4C  is a bottom section view of the resulting article, taken on line  4 C- 4 C in  FIG. 4D . Referring to  FIG. 4C , the etching produces the bottom electrode  210  of the device  200  and the conductive circuit trace  211 . 
         [0020]      FIG. 4D  is a section view in front elevation taken on line  4 D- 4 D in  FIG. 4C . Referring to  FIG. 4D , the bottom electrode  210  side of the resulting article is laminated to a laminate material  282 . The lamination can be performed, for example, using FR4 prepreg, or other prepregs, in standard printing wiring board processes. 
         [0021]    A photoresist (not shown in  FIG. 4D ) is applied to the foil  242  and the photoresist is imaged and developed. The foil  242  is etched, then the resistor layer  232  is etched and the remaining photoresist stripped.  FIG. 4E  is a top section view of the resulting article, taken on line  4 E- 4 E in  FIG. 4F .  FIG. 4F  is a section view in front elevation, taken on line  4 F- 4 F in  FIG. 4E . Referring to  FIGS. 4E and 4F , the etching produces the top electrode  240  of the device  200  and the conductive circuit trace  245 . Etching images the foil  242  and the resistor layer  232 . 
         [0022]    A photoresist (not shown in  FIGS. 4E and 4F ) may be applied to the imaged foil and resistor. The photoresist is imaged and developed and the foil  242  is then etched using etching solutions that remove foil, but not resistor material. The remaining photoresist is then stripped. In this way, the layer of resistor material  232  can be selectively imaged to form a resistor element  230  having any desired shape and dimensions. The resultant resistor element  230  bridges the gap  248  and extends between the top conductor  240  and the conductive trace  245 . 
         [0023]    Referring to  FIG. 4F , a dielectric layer  280  is laminated to the component side of the dielectric layer  282 , forming a laminate structure  201 . The laminate structure  201  can then be incorporated into, for example, a printed wiring board using conventional lamination and via formation processes. 
       EXAMPLE 
       [0024]    This example of the device  200  is discussed with reference to  FIG. 3 . In this example, the electrodes  210 ,  240  are formed from copper foils. Resistive material  230  is a plated nickel phosphorus alloy of sheet resistivity 50 ohms per square. The dielectric  220  is an unfilled polyimide dielectric (INTERRA™ HK 04, available from DuPont Electronic Technologies, Wilmington, Del.) of 25 microns thickness having a dielectric constant of 3.5 thereby giving a capacitance density of 800 picoFarads per square inch. 
         [0025]    The size (when viewed from a top plan perspective) of the capacitor needed for a transmission line termination of 30 picoFarad is 24.2 square mm, which corresponds to slightly less than 5 mm by 5 mm. 
         [0026]    The size of the resistor in this example for a nominal 60 ohm resistance can be varied, as long as the length to width ratio is maintained at 1.2 to 1.0. The above capacitor is easy to make to relatively high tolerances. 
         [0027]    According to the above embodiment, thin capacitor laminate structures in combination with resistors may be used to effectively bury RC transmission line terminations. Embedding the capacitor and resistor functions frees up valuable board surface real estate and eliminates solder joints associated with SMT devices, thereby improving reliability. Further, the laminates combining resistance and capacitance within the laminate can be processed using conventional etching processes, which reduces production costs. 
         [0028]    The above embodiments also provide other options for circuit designers and PWB fabricators. For example, one piece of laminate can be used to embed many discrete resistors and many discrete capacitors, which reduces the inductance associated with connecting resistors and capacitors. 
         [0029]    The shapes of the capacitor embodiments in top plan view are generally rectangular. However, the capacitor electrodes, dielectrics, and other components and layers can have other regular or irregular surface area shapes, such as, for example, round, oblong, oval or polygonal shapes. 
         [0030]    A single capacitive/resistive device  200  is formed in the laminate structures  201  described above. However, panel structures and printed wiring boards can include a large number of individual capacitive/resistive devices of differing type and arrangement. 
         [0031]    In the above embodiments, resistance, capacitance and inductance combine to create a specific circuit impedance, typically identified by the capital letter Z. The resistance and capacitance may be structured to achieve a specific impedance. Changing the resistance, capacitance, or both will change the inductance. All three changes can be controlled to define the final impedance. In other words, the impedance of the laminate is ‘tunable. 
         [0032]    The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only selected preferred embodiments of the invention, but it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, and/or within the skill or knowledge of the relevant art. 
         [0033]    The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments, not explicitly defined in the detailed description.