Abstract:
In a method for producing a semiconductor structure a substrate is provided, a dielectric layer comprising at least one metal oxide is formed on the substrate, and a nitrided layer is formed from the dielectric layer. The nitrided layer comprises either at least one metal nitride corresponding to the metal oxide or a metal oxynitride. The nitrided layer is removed selectively with respect to the dielectric layer in a predetermined etching medium.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to a process for producing a semiconductor structure.  
         [0002]     Thin liner layers are very frequently used in the production of microelectronic devices. They are used either as dielectric or as interlayers.  
       BRIEF SUMMARY OF THE INVENTION  
       [0003]     A method for producing a semiconductor structure, comprises the steps of: 
        providing a substrate;     forming a dielectric layer of at least one metal oxide on the substrate;     forming a nitrided layer from the dielectric layer of at least one metal oxide, the nitrided layer including either at least one metal nitride corresponding to the metal oxide or a metal oxynitride; and     removing the corresponding nitrided layer selectively with respect to the dielectric layer in a predetermined etching medium.        
 
         [0008]     The idea on which the present invention is based consists in completely or partially nitriding a layer of a metal oxide in a predetermined region, so that the etching properties of the nitrided region differ from the unnitrided region with respect to a predetermined etching medium. In other words, the nitrided region can be etched more easily using the predetermined etching medium than the unnitrided region, and can therefore be removed selectively with respect to the unnitrided region.  
         [0009]     According to an embodiment of the inventive method, the dielectric layer is partially masked, and the corresponding nitrided layer is formed by converting the unmasked region of the dielectric layer in a nitrogen-containing atmosphere.  
         [0010]     The corresponding nitrided layer may partially be masked by means of a mask, then the dielectric layer may be formed by converting the unmasked region of the corresponding nitrided layer in an oxygen-containing atmosphere, and then the mask may be removed.  
         [0011]     The removal step may take place in SC12, phosphoric acid or hydrofluoric acid. The removal step in particular may take place in an aqueous solution, for example by immersion in the acids.  
         [0012]     The metal oxide may be selected from the following group: Al 2 O 3 , HfO, TiO 2 , Ta 3 O 5 , ZrO, ScO and rare earth oxides.  
         [0013]     The metal nitride may be selected from the following group: AlN, HfN and SiN.  
         [0014]     The metal oxynitride may be selected from the following group: Al—O—N, Hf—O—N, Ti—O—N, Ta—O—N, Zr—O—N, Sc—O—N, rare earth oxides.  
         [0015]     The conversion may take place at a temperature between 700° C. and 1200° C., preferably in the range between 950° C. and 1050° C.  
         [0016]     The production of the nitrided layer (nitriding) may be effected by a plasma process using nitrogen radicals.  
         [0017]     According to one embodiment of the inventive method, the dielectric layer is provided as capacitor dielectric on the walls of a trench. Then, the trench is partially filled with a conducting filling as inner capacitor electrode, and then the dielectric layer above the top side of the conducting filling is converted into the corresponding nitrided layer in a nitrogen-containing atmosphere, the conducting filling serving as a mask for that part of the dielectric layer which is located below the top side of the conducting filling.  
         [0018]     In another embodiment of the inventive method, the dielectric layer is provided as gate dielectric on the substrate. Then, a gate is provided and patterned on the dielectric layer, and then the dielectric layer next to the gate is converted into the corresponding nitrided layer in a nitrogen-containing atmosphere, the gate serving as a mask for that part of the dielectric layer which is located beneath the gate. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0019]     Exemplary embodiments of the invention are illustrated in the drawings and explained in more detail in the following description. In the drawings:  
         [0020]      FIG. 1A -C are diagrammatic illustrations of successive process stages of a process for producing a semiconductor structure as a first embodiment of the present invention,  
         [0021]      FIG. 2A -F are diagrammatic illustrations of successive process stages in a process for producing a semiconductor structure.  
         [0022]      FIG. 3A -C are diagrammatic illustrations of successive process stages in a process for producing a further semiconductor structure. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]     In the figures, identical reference designations denote identical or functionally equivalent components.  
         [0024]      FIG. 1A -C show diagrammatic illustrations of successive process stages of a process for producing a semiconductor structure as a first embodiment of the present invention.  
         [0025]     In  FIG. 1 , reference designation  1  denotes a silicon semiconductor substrate in which there is a trench  5 , for example a deep trench for the capacitor of a semiconductor memory cell. A thin dielectric layer  10  of Al 2 O 3 , which in the case of the capacitor for a semiconductor memory cell represents the capacitor dielectric, is provided at the walls of the trench  5 . Furthermore, a filling  14  of polysilicon, which in the case of the said capacitor for a memory cell forms the inner capacitor electrode, is provided in the interior of the trench  5 . The filling  14  is recessed into the trench  5  with respect to the top side O of the semiconductor substrate  1 .  
         [0026]     Continuing with reference to  FIG. 1B , a nitriding step then takes place in an NH 3  atmosphere at a temperature of approximately 900° C. In this nitriding step, the uncovered part of the layer  10  of Al 2 O 3  is converted into a layer  10   a  of Al—O—N or Al—N, i.e. is nitrided. The dielectric layer  10   a  has different etching properties from the dielectric layer  10  with respect to certain etching media, such as for example SC12 (H 2 SO 4 /H 2 O 2 /NH 4 OH), phosphoric acid, hydrofluoric acid. These etching media etch the dielectric layer  10   a  with a high selectivity compared to the dielectric layer  10  and also the substrate  1  and the filling  14 , so that the dielectric layer  10   a  can be removed selectively with respect to the dielectric layer  10  and the substrate  1  and the filling  14  in the upper region of the trench, leading to the process state shown in  FIG. 1C .  
         [0027]     FIGS.  2 A-E show diagrammatic illustrations of successive process stages of a process for producing a semiconductor structure as a second embodiment of the present invention.  
         [0028]     In  FIG. 2A , reference numeral  1  again denotes a silicon semiconductor substrate. A first dielectric layer  25 , preferably a layer of SiO 2  or HfSiO x , has been applied to the semiconductor substrate  1 , and a second dielectric layer  15  of a metal oxide, for example of Al 2 O 3 , has been applied to the first dielectric layer  25 . A hard mask  30 , for example of polysilicon or silicon oxide, has been deposited on the dielectric layers  15 ,  25 . A photoresist  31  is arranged on the hard mask  30  and patterned in such a manner that a first region P is covered by the photoresist  31  and a second region N is uncovered. By way of example, PMOS transistors are to be produced in the first region P by subsequent patterning steps, and NMOS transistors are to be produced in the second region N.  
         [0029]     A first patterning step provides for the pattern of the patterned photoresist layer  31  to be transferred into the hard mask  30  ( FIG. 2B ). This can be done by etching back the hard mask  30 , in which case the Al 2 O 3  layer  15  can be used as a stop layer.  
         [0030]     Thereafter, the Al 2 O 3  layer, which is now uncovered, can be exposed to an ammonia atmosphere NH 3  or another nitrogen-containing atmosphere. The nitrogen radicals convert the Al 2 O 3  layer into an Al—N layer or an Al—O—N layer, i.e. nitrided layer  15   a  ( FIG. 2C ).  
         [0031]     The nitrided layer  15   a  is then removed by a wet-etching step. The etching solutions listed in the first exemplary embodiment can be used for this step ( FIG. 2D ).  
         [0032]     Finally, the photoresist  31  and the hard mask  30  are removed in the first region P. The removal of these masking layers can also take place in an appropriate way before one of the above-described steps. It is preferable for the photoresist layer  31  to be removed prior to the nitriding of the Al 2 O 3  layer  15 , since otherwise the layers  15 ,  25  could be contaminated by the photoresist layer  31 . The result is the layer structure illustrated in  FIG. 2E .  
         [0033]     Gate stacks  20  are subsequently arranged in the region P and in the region N. Therefore, a dielectric layer of a metal oxide  15  and a silicon oxide layer  25  is provided for PMOS transistors in the region P. The NMOS transistors in the region N include only a gate dielectric layer comprising a simple silicon oxide layer  25  ( FIG. 2F ). The corresponding drain/source regions are not illustrated. The exemplary embodiment described therefore allows NMOS and PMOS with different dielectric layers to be processed in parallel.  
         [0034]      FIG. 3A -C show diagrammatic illustrations of successive process stages of a process for producing a semiconductor structure as a third embodiment of the present invention.  
         [0035]     In the third embodiment shown in FIGS.  3 A-C, reference numeral  1  likewise denotes a silicon semiconductor substrate. A nitrided liner layer  30 A of Al—O—N or AlN has been applied to the semiconductor substrate  1 . Also provided is a hard mask, for example of SiO 2 , which masks part of the liner layer  30 A as shown in  FIG. 3A . Referring now to  FIG. 3B , an oxidation step is carried out in an O 2  atmosphere at a temperature of 800° C., during which the uncovered part of the liner layer  30 A is converted into a liner layer  30  of Al 2 O 3 . Then, the hard mask  50  is removed and a selective etch takes place in SC12, with the result that the nitrided liner layer  30 A is removed selectively with respect to the liner layer  30 .  
         [0036]     Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted to these embodiments, but rather can be modified in numerous ways.  
         [0037]     Although the above examples have cited Al 2 O 3  as the dielectric layer, the present invention is not restricted to Al 2 O 3 , but rather can in principle be applied to all metal oxides which can be nitrided or to all corresponding metal nitrides which can be oxidized.  
         [0038]     In addition to Al 2 O 3 , the oxides HfO, TiO 2 , Ta 3 O 5 , ZrO, ScO, rare earth oxides, all metal and transition metal oxides and mixtures thereof appear to be particularly suitable.  
         [0039]     Preferred nitrides are AlN, HfN, SiN and other nitrides of metals and transition metals and mixtures thereof. The same applies to oxynitrides.  
         [0040]     Although in the above example an oxidation was carried out in O 2  atmosphere and a nitriding was carried out in NH 3 , the present invention is not restricted to these particular details. It is also conceivable to use oxygen-containing or nitrogen-containing plasmas or NO-containing or O-containing gas mixtures.  
         [0041]     The present invention can in principle be applied to all microelectronic regions, but a preferred application is for memory component technology with feature sizes of less than 70 nm.