Abstract:
Variable capacitance circuitry includes a fine tuning bank and a medium tuning bank. The fine tuning bank includes a plurality of varactors of progressively increasing size (e.g., width). Only one of these varactors is turned on at any one time. The medium tuning bank includes a plurality of similarly sized varactor circuits. These are turned on selectively in thermometer fashion (e.g., more are turned on (or off) as more (or less) overall capacitance is needed). The medium tuning bank increment is matched to the fine tuning bank range, so that when the fine tuning bank reaches an end of its range, another medium increment can be added or subtracted while the fine tuning bank is reset to the other end of its range. A uniform progression of small, incremental, capacitance changes is therefore provided over the relatively wide tuning range of the medium bank.

Description:
BACKGROUND OF THE INVENTION 
   This invention relates to variable-frequency oscillator circuits, and more particularly to digitally controlled oscillator (DCO) circuits. 
   Voltage controlled oscillator (VCO) circuits are widely used in frequency synthesizers, clock and data recovery (CDR) circuits, and so on. The output frequency of a VCO is tuned by its analog input voltage, and the main parameters for a VCO are center frequency, frequency tuning range, VCO gain, and phase noise. Due to the nature of the frequency tuning, any noise in the control signal will modulate the VCO, resulting in more undesirable noise output. This effect can be reduced by reducing the VCO gain, but the frequency tuning range will be reduced as well because of the limited range of tuning voltage. By employing both coarse tuning and fine tuning, the gain of the fine tuning can be reduced while a large tuning range relies on the coarse tuning (which still has a very large gain). 
   Recently there has been increasing interest in digitally controlled oscillators (DCOs). DCOs normally have small analog gain, but the frequency resolution is typically limited. In Staszewski et al., “A First Multigigahertz Digitally Controlled Oscillator for Wireless Applications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 51, No. 11, November 2003, pp. 2154-64, a sigma-delta modulator is used to enhance the frequency resolution. However, this results in a complex digital circuit. 
   SUMMARY OF THE INVENTION 
   The present invention employs a capacitance tuning scheme for LC-tank-based DCOs with incremental varactors and matched varactor banks, which can achieve both high frequency resolution (i.e., small frequency steps) and large frequency tuning range with small differential nonlinearity. (LC means inductor/capacitor.) 
   Further features of the invention, its nature and various advantages, will be more apparent from the accompanying drawings and the following detailed description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a simplified plot of typical capacitance vs. control voltage for PMOS varactors. 
       FIG. 2  is a simplified schematic block diagram of an illustrative embodiment of a portion of variable capacitance circuitry in accordance with the invention. 
       FIG. 3  is a simplified schematic block diagram of an illustrative embodiment of another portion of variable capacitance circuitry in accordance with the invention. 
       FIG. 4  is a further simplified schematic block diagram of illustrative variable capacitance circuitry in accordance with the invention. 
   

   DETAILED DESCRIPTION 
   A MOS varactor is a well-known type of circuit element that normally has two flat regions in its V-C (voltage-capacitance) characteristic curve. These two flat regions are at approximately 0V and 1V as shown in  FIG. 1 .  FIG. 1  shows V-C curves for varactors of three different relative widths (i.e., relative width 0.5, bottom curve; relative width 1.0, middle curve; and relative width 1.5, top curve). The two flat regions referred to above can be used as two levels of a digital switch, so that analog gain is almost zero. However, simply using a set of such varactors would mean that the minimum capacitance step would be the same as the capacitance difference between two flat regions for a MOS varactor having a minimum size. This capacitance resolution is normally not enough for a DCO. To enhance the capacitance resolution, the present invention employs MOS varactors incrementally sized for fine frequency tuning, and unit sized for medium frequency tuning. The varactor sizes are physically matched (small differential nonlinearity) and combined together directly so that both large range and small step size are achieved. The above-mentioned two types of frequency tuning are detailed below. 
     FIG. 2  illustrates fine capacitance tuning circuitry  10  in accordance with the invention. In this fine frequency tuning bank, 2 n  MOS varactors with the same channel length are used, and their widths are determined as W i =W 0 +i*W s , where i=0, 1, 2, . . . , 2 n −1; W 0  is the width of the first varactor; and W s  is the varactor width step. These varactors are respectively represented by the lines  30 - 0  through  30 - 2   n −1 in  FIG. 2 . (The first hyphen in each of these identifiers is merely a hyphen; any second hyphen in an identifier is a minus sign.) The length of each line  30  is at least schematically indicative of the width of the corresponding varactor. A capacitance increase is achieved by turning on a larger (i.e., wider) varactor  30  and turning off the previously selected smaller (i.e., narrower) varactor  30 . In other words, only one of varactors  30  is turned on at any one time. All other varactors are turned off. “Turned on” means (in the context of varactors with behavior like that shown in  FIG. 1 ) that 1V is applied to the varactor. “Turned off” means (in this context) that 0V is applied to the varactor. 
   Assuming that the amount of capacitance desired from bank  10  is indicated by n binary-coded control signals  18  applied to decoder  20 , the above-described preferred scheme of having only one of varactors  30  on at any one time can be achieved by making decoder  20  a “one-hot” decoder. In other words, decoder  20  has 2 n  outputs  22 , one for applying either 0V or 1V to each of varactors  30 , respectively. These 2 n  outputs may be thought of as being “numbered” in the same order as the varactors to which they are connected increase in size. Decoder  20  decodes what number its inputs  18  correspond to, and then outputs 1V on only its output lead  22  having that number. Decoder  20  applies 0V to all of its other output leads  22 . For example, if inputs  18  represent the number  5 , decoder  20  applies 1V to its output lead numbered  5  (connected to varactor  30 - 5 ). Decoder  20  applies 0V to all of its output leads numbered  0  through  4  and  6  through  2   n −1. 
   By way of a specific example, for 1.8V PMOS varactors  30  in 90 nm CMOS technology, if the varactor length is 0.2 um, a width step of 0.05 um corresponds to a capacitance step of approximately 32 aF. However, the smaller the step size, the larger the number of varactors for a given capacitance tuning range. To avoid an excessive number of varactors  30 , a medium tuning bank  50  is preferably used and matched with fine tuning bank  10  as will now be described. 
   An illustrative embodiment of medium tuning bank  40  is shown in  FIG. 3 . This bank includes decoder  50  and 2 m  instances  60  of pairs of two MOS varactors A and B. Each varactor A may have the same length as fine tuning bank varactors  30  in the fine tuning bank. The width of each varactor A may be W 0  (the same parameter referred to by that designation in connection with  FIG. 2 ). The length of each varactor B may again be the same as the length of varactors A and  30 . The width of each varactor B may be 2 n *W s  (where again these parameters have the same meanings and values referred to in connection with  FIG. 1 ). Decoder  50  receives m binary-coded input signals  48  for controlling how the varactor pairs  60  in medium tuning bank  40  are used. In particular, decoder  50  decodes input signals  48  to convert the numerical value represented by those signals to “thermometer level” values on the 2 m  output leads  52  of the decoder. This means that all of the leads  52  below the current thermometer level are enabled (e.g., logic 1), while all the output leads  52  at or above the current thermometer level are disabled (e.g., logic 0). For example, if the input binary value on leads  48  is 0, none of output leads  52  is on. If the input binary value on leads  48  is 1, only the output lead  52  to varactor pair  60 - 0  is enabled. If the input binary value on leads  48  is 5, only the output leads to varactor pairs  60 - 0  through  60 - 4  are enabled. 
     FIG. 3  shows the effect of turning on (enabling) the output lead  52  to a representative one of varactor pairs  60 . When the control signal  52  to a pair  60  is enabled, the smaller varactor A in that pair is turned off and the larger varactor B in that pair is turned on. When the control signal  52  to a pair  60  is disabled (off), the smaller varactor A in that pair is turned on and the larger varactor B in that pair is turned off. 
   From the foregoing it will be appreciated that the amount of capacitance added each time one more varactor pair  60  is enabled is exactly matched with the tuning range of fine tuning bank  10 . The inputs  18  to the fine tuning bank and the inputs  48  to the medium tuning bank can be respectively the less- and more-significant bits of one binary-coded control word (which can, or course, vary in value over time if desired). Assume, for example, that n is initially 0, and m is initially 3. Varactor  30 - 0  will be on and pairs  60 - 0  through  60 - 2  will be enabled (each varactor A in those pairs off and each varactor B in those pairs on). Now assume that n+m begins to increase, with the increase appearing first in less significant bits n. Varactor  30 - 0  will be turned off and increasingly wide varactors  30  in the series will be turned on as each previously-on varactor  30  is turned off. Eventually, fine tuning bank  10  will reach the end of its tuning range (varactor  30 - 2   n −1 on). Assume that control word n+m then increases by one more of its smallest increments. This will turn off varactor  30 - 2   n −1 and turn on varactor  30 - 0 . It will also enable one more pair  60  (pair  60 - 3 ) in medium tuning bank  40 . This means turning off varactor A in pair  60 - 3  and turning on varactor B in that pair. The amount of capacitance thus added in the medium bank is 2 n *W s , which is one more W s  than was subtracted by concurrently switching the fine bank back from varactor  30 - 2   n −1 enabled to varactor  30 - 0  enabled. There is thus a continuous succession of small incremental increases (or decreases) in capacitance available from fine and medium tuning banks  10  and  40  operating together as control n+m increases (or decreases) in value. Moreover, these small incremental changes are uniformly available over a very wide tuning range (basically the tuning range of medium tuning bank  40 ). 
     FIG. 4  shows that fine tuning bank  10  and medium tuning bank  40  are connected in parallel with one another and a pair of capacitance output terminals (Cap_out). In this way the capacitance provided by overall circuit  100  is the sum of the capacitances provided by tuning bank  10  and tuning bank  40 . (Within bank  10  all of varactors  30  are connected in parallel, but only one is providing capacitance at any one time, as described earlier. Similarly, within bank  40  all of varactors A and B are connected in parallel, but only those varactors that are then “on” (in the terms employed in  FIG. 3 ) are providing capacitance at any given time.) 
   To briefly recapitulate, by combining the fine tuning and the medium tuning, capacitance tuning can be achieved as shown in  FIG. 4 . The control word has a width of m+n. It is split into two parts: m bits for medium capacitance tuning and n bits for fine capacitance tuning. The outputs of the two tuning banks are directly connected in parallel. 
   It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, any desired number of varactors  30  can be used in bank  10 . Similarly, bank  40  can include any desired number of varactor pairs  60 .