Abstract:
Operation apparatus for deriving an error position polynomial Γ(x) and a Forney syndrome polynomial T(x) of a Galois field capable of reducing the required number of Galois field multipliers to one, irrespective of the maximum error correction capacity in a Galois field operation, thereby reducing the chip area and achieving a correct operation. The operation apparatus comprises a storing register for storing result values sequentially inputted therein, a multiplexor for receiving outputs from the storing register and selecting a necessary coefficient therefrom, a first register and a second register for storing a coefficient currently selected by the multiplexor and a coefficient previously selected by the multiplexor, respectively, a multiplier for multiplying a value corresponding to an input erasure position and the coefficient stored in the second register, and an adder for adding a value outputted from the multiplier to the coefficient stored in the first register and inputting the resultant value to the storing register.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to error correction, and more particularly to an operation apparatus with multipliers for deriving an error position polynomial Γ(x) and a Forney syndrome polynomial Γ(x) of a Galois field. 
     2. Description of the Prior Art, 
     Generally, an erasure is known in terms of position, even though unknown in terms of size, as compared with an error whose position and size are unknown. Accordingly, when information indicative of an erasure of some symbol is applied to a decoder, he erasure corresponding to two times the same number of parity errors can be corrected. 
     Referring to FIG. 1, here is illustrated a general erasure position power operation apparatus. The operation apparatus comprises an AND gate 1 having one input for receiving information about erasure, namely, erasure positions of binary values. To the other input of the AND gate 1, register 2 and a multiplier 3 are connected. In the AND gate 1, the erasure position is AND-combined with a value obtained through the register 2 and the multiplier 4. To an output of the AND gate 1, a non-zero detector 4 is connected, which receives an output signal from the AND gate 1 and generates a control signal C 1 . The control signal C 1  is applied to a 2t symbol latch 5 via a switch SW a . According to the control signal C 1 , the 2t symbol latch 5 outputs powers for the erasure positions, namely, values α j1 , α j2 , . . . corresponding to respective erasure positions. Here, the value α j1  represents the value corresponding to the first erasure position and the value α j2  represents the value corresponding to the second erasure position. 
     Since the erasure positions are already known, they can be expressed by the following polynomial: ##EQU1## wherein, e represents the number of erasures. 
     FIG, 2 is a block diagram of a conventional operation apparatus utilizing the polynomial for erasure positions. 
     As shown in FIG. 2, the operation apparatus comprises a non-zero detector 10 for receiving an erasure position value α j (i) and detecting whether the received erasure position value is zero or not, and a multi-stage operation unit including a plurality of operation circuits 20 0  to 20 2t-1 . The operation unit comprises a plurality of adders A 0  to A 2t-1  and a plurality of registers R 0  to R 2t-1  connected with the adders A 0  to A 2t-1  via a plurality of switches SW 0  to SW 2t-1 , respectively. Each of the switches SW 0  to SW 2t-1  are controlled by an output signal from the non-zero detector 10, to be switched on or off. According to the switching operations of the switches SW 0  to SW 2t-1 , the registers R 0  to R 2t-1  store temporally output values from the adders A 0  to A 2t-1 , respectively. The operation unit also comprises a plurality of multipliers M 0  to M 2t-1  each for multiplying each value stored in each corresponding one of the registers R 0  to R 2t-1  and each corresponding erasure position value α j (i) and sending the resultant value to each corresponding one of the adders A 0  to A 2t-1 . 
     In the operation apparatus with the above-mentioned construction, the register R 0  is initially loaded with the value of 1, while the remaining registers R 1  to R 2t-1  are initially loaded with the value of 0. 
     When a value α j (1) corresponding to the first erasure position is received in the operation apparatus, it is applied to the non-zero detector 10 and respective multipliers M 0  to M 2t-1  of the operation circuits 20 0  to 20 2t-1 . 
     The non-zero detector 10 detects whether the received erasure position value is zero or not and outputs a detect signal, so as to control respective switches SW 0  to SW 2t-1  of the operation circuits 20 0  to 20 2t-1  . The control of each switch is carried out such that the switch is switched to its closed state when the input value of non-zero detector 10 is not zero and to its opened state when the input value is zero. 
     This procedure will be described in detail. 
     Where the first register R 0  has an initial value of 1 while the remaining registers R 1  to R 2t-1  have initial values of 0 at a state that the input value of non-zero detector 10 is not zero; the register R 0  is loaded with the first erasure position value α j (1), whereas the register R 1  is loaded with the value of 1. In this case, the remaining registers R 2  to R 2t-1  are still maintained as being loaded with the value of 0. 
     As the above procedure is repeated, the register R 0  is sequentially loaded with values in the order of 0→1→α j1  →α j1  ·α j2  →α j1  ·α j2  ·α j3  →αj1·α j2  α j3 . . . The register R 1  is sequentially loaded with values in the order of 0→1→α j1  →α 1  +α j2  →(α j1+  α j2 )α j3  →αj1·α j2  . . . On the other hand, the register R 2  is sequentially loaded with values in the order of 0→0→1→α j1  +α j2  +α j3  . . . . 
     The sequential value storing procedures executed in the registers are shown in FIG. 3. 
     FIG. 5 is a block diagram of a conventional operation apparatus for deriving a Forney syndrome. 
     As shown in FIG. 5, the operation apparatus comprises a non-zero detector 10a for receiving an erasure position value α j (i) and detecting whether the received erasure position value is zero or not, and a multi-stage operation unit including a plurality of operation circuits 20a 0  to 20a 2t-1 . The operation unit comprises a plurality of adders A 0  to A 2t-1  and a plurality of registers S 0  to S 2t-l  connected with the adders A 0  to A 2t-1  via a plurality of first switches SW b , respectively. Each of the first switches SW b  are controlled by an output signal from the non-zero detector 10a, to be switched on or off. According to the switching operations of the first switches SW b , the registers S 0  to S 2t-1  store temporally output values from the adders A 0  to A 2t-1 , respectively. The operation unit also comprises a plurality of multipliers M 0  to M 2t-1  each for multiplying each value loaded in each corresponding one of the registers S 0  to S 2t-1  and each corresponding erasure position value α j (i) and sending the resultant value to each corresponding one of the adders A 0  to A 2t-1 . The operation apparatus also comprises an output unit 30 including a plurality of registers T 0  to T 2t-1  each connected to each corresponding one of the registers S 0   to S 2t-1  via a second switch SW c . 
     In the operation apparatus with the above-mentioned construction, the registers S 0  to S 2t-1  of the operation circuits 20 a0  to 20a 2t-1  are initially loaded with the values of S 0 , S 1 , . . . , and S 2t-1  which are coefficients of the polynomial of the syndrome, respectively. 
     In similar manner to the case of FIG. 2, this operation apparatus receives sequentially values α k (i) corresponding to erasure positions and controls the switches SW b  via the non-zero detector 10a so that the values α j (i) are applied to the multipliers M 0  to M 2t-1 , respectively. 
     At the first clock, thereafter, the register S 0  is loaded with the value of S 0 , whereas the register S 1  is loaded with the value of S 1  +S 0  ·α j (i). On the other hand, the register S 2  is loaded with the value of S 2  +S 1  ·α k (1). In such a manner, the register S j  is loaded with the value of S j  +S j  ·α j (i). 
     As the above procedure is repeated according to inputting of erasure position values α j (i), the registers S 0  to S 2t-1  are loaded with coefficients of the polynomial. 
     At this time, the second switches SW c  are switched to its closed state by the control signal C 2 , so that the coefficients loaded in the registers S 0  to S 2t-1  are transferred to the registers T 0  to T 2t-1  of the output unit 30, respectively. 
     FIG. 4 is a circuit diagram of Galois field (GF) multipliers M 0  to M 2t-1  used in both the operation apparatus of FIG. 3 and the operation apparatus of FIG. 5. Each adder is an GF(2 4 ) adder for operating one byte comprised of four bits. The GF(2 4 ) adder comprises an AND gate and an exclusive 0R gate. 
     First, a source polynomial P(X) having the degree of 4 is needed for expanding GF(2) up to GF(2 4 ). 
     That is, assuming the source polynomial P(X)=X 4  +X+1, elements of all fields are expressed by a cubic-nomials a 3  X 3  +a 2  X 2  +a 1  X+a 0  =a(X). In this case, a i  represents elements of GF(2). 
     When the cubic-nomial is expressed for τ and β indicative of input values of each AND gate, and Θ indicative of one input value of each exclusive OR gate, the following cubic-nomials are obtained: 
     τ(X)=τ 3  X 3  +τ 2  X 2  +τ 1  X+τ 0   
     β(X)=β 3  X 3  +β 2  X 2  +β 1  X+β 0   
     Θ(X)=Θ 3  X 3  +Θ 2  X 2  +Θ 1  X+Θ 0   
     Also, τ·β indicative of the output value of each AND gate is expressed by the following equation: 
     
         τ·β=τ(X) β(X) mod P(X) 
    
     Assuming τ·β=K 3  X 3  +K 2  X 2  +K 1  X+K 0  the output value τ·β+Θ of each exclusive OR gate is expressed by the following cubic-nomial: 
     
         τ·β=(K.sub.3 +Θ.sub.3)X.sup.3 +(K.sub.2 +Θ.sub.2)X.sup.2 +(K.sub.1 +Θ.sub.1)X+(K.sub.0 +Θ.sub.0)=W.sub.3 X.sup.3 +W.sub.2 X.sup.2 +W.sub.1 X+W.sub.0 
    
     The operation of the first row is carried out as follows: 
     τ.sup.(1) (X)=τ(X) 
     Θ.sup.(1) (X)=Θ(X)+β 0  τ(X) 
     The operation of the i-th row is carried out as follows: 
     τ.sup.(i+1) (X)=Xτ.sup.(i) (X) mod P(X) 
     Θ.sup.(i+1) (X)=Θ.sup.(i) (X)+β i  τ.sup.(i+1) (X) 
     Each cell performs the following two functions: 
     
         τ.sub.j.sup.(i+1)=τ.sub.j.sup.(i)+τ.sub.3.sup.(i) P.sub.j 
    
     
         Θ.sub.j.sup.(i+1)=Θ.sub.j-1.sup.(i) +β.sub.i τ.sub.j.sup.(i+1) 
    
     wherein, Θ j .sup.(i+1) represents the i-th row ·j-th column. 
     For example, in the first cell of the second row, τ 3  and β 1  are ANDed in the AND gate AD 2 .1 and then exclusively ORed in the exclusive OR gate XOR 2 .1, so as to be outputted as Θ 0 .sup.(2). In the second cell, τ 3 .sup.(0) and τ 0  are exclusively ORed in the exclusive OR gate XOR 2 .2, so as to be provided as one input of AND gate AD 2 .3. 
     The output from the exclusive OR gate XOR 2 .2 is ANDed with β 1  in the AND gate AD 2 .3 and then exclusively ORed in the exclusive OR gate XOR 2 .3, so as to be outputted as Θ 1 .sup.(1). In such a manner, the operation is repeated up to the final row. 
     As a result, the following results are obtained: 
     
         Θ.sub.0.sup.(4) =W.sub.0 .sup.(4) =W.sub.1, Θ.sub.2.sup.(4) =Θ.sub.2, Θ.sub.3.sup.(4) =W.sub.3. 
    
     In the conventional circuit, however, the content of registers based on the polynomial for erasure positions includes the initial value of 1 only for the register R 0  and the initial value of 0 for the remaining registers R 1  to R 2t-1 . 
     For each input α j (i) only one of such registers is used while the remaining registers are unnecessary. Accordingly, the multipliers for deriving values for the remaining registers are also unnecessary. 
     That is, for the operation of the polynomial for erasure positions, 2t GF multipliers and 2t adders are needed. In GF multipliers, the larger the symbol field, the more the number of exclusive OR gates. 
     As a result, where a Reed Solomon decoder is realized by using very large size integrated circuit chips, the area occupied by the multipliers is increased due to the increased number of exclusive OR gates. Furthermore, when symbol fields of codes are very large and the erasure correction capacity is large, the chip area becomes relatively large. The flow of signals is also vague, so that a correct operation can not be carried out. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the invention is to provide an operation apparatus capable of reducing the number of Galois field multipliers to one, irrespective of the maximum error correction capacity in a Galois field operation, thereby reducing the chip area and achieving a correct operation, 
     In accordance with the present invention, this object can be accomplished by providing an operation apparatus comprising: a storing register for storing result values sequentially inputted therein; a multiplexor for receiving outputs from the storing register and selecting a necessary coefficient therefrom; a first register and a second register for storing a coefficient currently selected by the multiplexor and a coefficient previously selected by the multiplexor, respectively; a multiplier for multiplying a value corresponding to an input erasure position and the coefficient loaded in the second register; and an adder for adding a value outputted from the multiplier to the coefficient loaded in the first register and inputting the resultant value to the storing register. 
     The adder logically operates multiplication outputs (W 0 , W 1 , W 2  and W 3 ) for 4-bit input data (τ 0 , τ 1 , τ 2  and τ 3 ) and 4-bit input data (β 0 , β 1  , β 2  and β 3  ), in the following order: 
     
         W.sub.0 =(τ.sub.0 ·β.sub.0)+(τ.sub.1 ·β.sub.3)+(τ.sub.3 ·β.sub.1)+(τ.sub.2 ·β.sub.2) 
    
     
         W.sub.1 =(τ.sub.1 ·β.sub.0)+(τ.sub.3 ·β.sub.1)+(τ.sub.0 ·β.sub.1)+((τ.sub.3 ·β.sub.2)+(τ.sub.2 ·β.sub.2))+(τ.sub.1 ·β.sub.3) 
    
     
         W.sub.2 =(τ.sub.2 ·β.sub.0)+(τ.sub.2 ·β.sub.1)+((τ.sub.3 β.sub.2)+(τ.sub.0 ·β.sub.2))+((τ.sub.2 ·β.sub.3)+(τ.sub.3 ·β.sub.3)) 
    
     
         W.sub.3 =(τ.sub.3 ·β.sub.0)+(τ.sub.2 ·β.sub.1)+(τ.sub.1 ·β.sub.2)+((τ.sub.0 ·β.sub.3)+(τ.sub.3 ·β.sub.3). 
    
     Upon receiving a power corresponding to one erasure position, the operation apparatus derives coefficients of a polynomial for the erasure position while increasing the degree of the erasure position polynomial one by one. The derived coefficients are loaded. Accordingly, it is possible to derive the erasure position polynomial by using one multiplier and one adder, irrespective of the error correction capacity. As a result, the chip area can be greatly reduced. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and aspects of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings in which: 
     FIG. 1 is a block diagram of a general erasure position power operation apparatus; 
     FIG. 2 is a block diagram of a conventional operation apparatus utilizing a polynomial for erasure positions; 
     FIG. 3 is a table illustrating variations in register values in the operation apparatus of FIG. 2; 
     FIG. 4 is a circuit diagram of the multiplier of FIG. 2; 
     FIG. 5 is a block diagram of a conventional operation apparatus for deriving a Fourney syndrome; 
     FIG. 6 is a block diagram of an apparatus for operating a polynomial for erasure positions in accordance with a first embodiment of the present invention; 
     FIG. 7 is a circuit diagram of a multiplier in the operation apparatus of FIG. 6; 
     FIG. 8 is a circuit diagram of a circuit substituted for exclusive OR gates of FIG. 7; 
     FIG. 9 is a table illustrating variations in register values in the operation apparatus of FIG. 6; and 
     FIG. 10 is a block diagram of a Fourney syndrome operation apparatus according to a second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 6, there is illustrated an apparatus for operating a polynomial for erasure positions in accordance with a first embodiment of the present invention. 
     As shown in FIG. 6, the operation apparatus comprises a storing register 51 for storing results sequentially inputted therein and a multiplexor 52 for receiving outputs from the storing register 51 and selecting a necessary coefficient. To the multiplexor 52, a first register 53 and a second register 54 are connected, which receive the coefficient currently selected by the multiplexor 52 and the coefficient just previously selected by the multiplexor 52, respectively. The operation apparatus also comprises a multiplier 55 for multiplying a value corresponding to an input erasure position and the coefficient loaded in the second register 54, and an adder 56 for adding a value outputted from the multiplier 55 to the coefficient loaded in the first register 53. 
     FIG. 7 is a circuit diagram of the multiplier of FIG. 6. As shown in FIG. 6, the multiplier comprises a plurality of AND gates AD 1 .1, AD 1 .3, AD 1 .5, AD 1 .7, AD 3 .1, AD 3 .3, AD 3 .5, AD 3 .7, AD 5 .1, AD 5 .3, AD 5 .5, AD 5 .7, AD 7 .1, AD 7 .3, AD 7 .5 and AD 7 .7 each for AND-combining a selected one of 4-bit input data τ 0 , τ 1 , τ 2  and τ 3  and a selected one of 4-bit input data β 0 , β 1 , β 2  and β 3 . A plurality of exclusive OR gates XOR 4 .4, XOR 6 .4, XOR 6 .6, XOR 8 .4, XOR 8 .6 and XOR 8 .8 are also provided for exclusively ORing outputs from the AND gates AD 3 .1 and AD 3 .7, outputs from the AND gates AD 5 .5 and AD 5 .7, outputs from the AND gates AD 5 .1 and AD 5 .7, outputs from the AND gates AD 7 .1 and AD 7 .3, outputs from the AND gates AD 7 .5 and AD 7 .7, and outputs from the AND gates AD 7 .1 and AD 7 .7, respectively. The multiplier also comprises an exclusive OR gate XOR 9 .2 for exclusively ORing outputs from the AND gates AD 1 .1, AD 3 .7, AD 5 .5 and AD 7 .3, an exclusive OR gate XOR 9 .4 for exclusively ORing an output from the AND gate AD 1 .3 and outputs from the exclusive OR gates XOR 4 .4, XOR 6 .4 and XOR 8 .4, an exclusive OR gate XOR 9 .6 for exclusively ORing outputs from the AND gates AD 1 .5 and AD 3 .3 and outputs from the exclusive 0R gates XOR 6 .6 and XOR 8 .6, and an exclusive OR gate XOR 9 .8 for exclusively ORing outputs from the AND gates AD 1 .7, AD 3 .5 and AD 5 .3 and an output from the exclusive OR gate XOR 8 .8. 
     In the AND gates AD i .j and the exclusive OR gates XOR i .j, i and j represent row and column, respectively. Data outputted from the exclusive OR gates XOR 9 .2, XOR 9 .4, XOR 9 .6 and XOR 9 .8 are values W 0 , W 1 , W 2  and W 3  obtained by multiplying input data τ 0 , τ 1 , τ 2  and τ 3  and input data β 0 , β 1 , β 2  and β 3 , respectively. 
     In operating the erasure position polynomial, since the erasure is known in terms of position, even though unknown in terms of size, the erasure position polynomial can be derived by using the following equation: ##EQU2## wherein, e represents the number of erasures. 
     Accordingly, coefficients of the polynomial are sequentially outputted while increasing the degree of polynomial one by one in the order of  1  (X) of the first degree,   2  (X) of the second degree, . . . , and   8  (X) of the e-th degree. Outputted coefficients of the polynomial  (X) are loaded in the storing register 51 of FIG. 5. 
     The first and second registers 53 and 54 are initialized to 1 and 0 for every clock, respectively. The multiplexor 52 is also initialized to 0. 
     As 0 is outputted from the multiplexor 52, the first and second registers 53 and 54 receives 0 which is the current coefficient of the polynomial (  i  (X)=0) and 1 which is the previous coefficient of the polynomial  i-1  (X)=1). Accordingly, 1 is inputted at the storing register 51. 
     Next, as α j1  corresponding to the first erasure position is inputted, α j1  is applied to the storing register 51 (X)=α j1 ). 
     At this time, the first register 53 adapted to store the current input value therein is loaded with  (X)=1. On the other hand, the second register 54 adapted to store the previous input value therein is loaded with   0  (X)=α j1 . Thus the operation for n=1 is completed. 
     Thereafter, an operation for n=2 is carried out. 
     That is, as α j2  corresponding to the second erasure position is inputted, the multiplexor 52 selects α j1 . At this time, 1 is loaded in the storing register 51, since the first and second registers 53 and 54 have been set to 1 and 0, respectively. 
     Then, the first and second registers 53 and 54 are loaded with   i  (X)=α j1  and   i-1  (X)=1, respectively. The multiplier 55 then multiplies the value   i-1  (X)=1 loaded in the second register 54 and the value α j2  corresponding to the power value of the second erasure position received from the erasure position power value input and thus outputs the value α j2 . The output value α j2  from the multiplier 55 is applied to the adder 56, so that it is added with the value α j1  loaded in the first register 53. 
     Accordingly, the storing register 51 receives the output value α j1  +α J2  from the adder 56 and stores it therein. 
     At this time, the multiplexor 52 selects 0, 
     Since the values   i  (X) and   i-1  (X) of the first and second registers 53 and 54 are 0 and 1 (  i  (X)=0 and   i-1  (X)=1), respectively, the value α j1  α J2  subsequently operated through the multiplier 55 and the adder 56 is applied to the storing register 51. Thus, the operation for n=2 is completed. 
     At this time, the content loaded in the storing register 51 includes  0  (X)=α j1  +α j2 ,   2  (X)=α j1  α j2 ,   2  (X)=1,   3  (X)=α j1  and   4  (X)=1. 
     As the operation is repeated up to n=e, in such a manner, coefficients of the erasure position polynomial are sequentially stored in the storing register 51. 
     Referring to FIG. 9, there is illustrated variations in values   i  and  i-1  stored in the first and second registers 53 and 54 and in value (X) loaded in the storing register 51. 
     Now, a procedure that the value corresponding to the input erasure position and the value loaded in the second register 54 are multiplied in the multiplier 55 will be described, in conjunction with FIGS. 7 and 8. 
     The AND gates AD 1 .1, AD 1 .3, AD 1 .5 and AD 1 .7 for AND-combining 4-bit input data τ 0 , τ 1 , τ 2  and τ 3  and 4-bit input data β 0 , β 1 , β 2  and β 3  output values τ 0  ·β 0 , τ 1  ·β 0 , τ 2  ·β 0  and τ 3  ·β 0 , respectively. The AND gates AD 3 .1, AD 3 .3, AD 3 .5 and AD 3 .7 output values τ 0  ·β 1 , τ 1  ·β 1 , τ 2  ·β 1  and τ 3  ·β 1 , respectively. The exclusive OR gate XOR 4 .4 outputs a value ((τ 0  ·β 1 )+(τ 1  ·β 1 )X+(τ 2  ·β 1 )X 2  +(τ 3  ·β 1 )X 3 )X. 
     On the other hand, the AND gates AD 5 .1, AD 5 .3, AD 5 .5 and AD 5 .7 output values τ 0  ·β 2 , τ 1  ·β 2 , τ 2 ·β 2  and τ 3  ·β 2 , respectively. The exclusive OR gates XOR 6 .4 and XOR 6 .6 output a value ((τ 0  ·β 2 )+(τ 1  ·β 2 )X+(τ 2  ·β 2 )X 2  +(τ 3  ·β 2 )X 3 )X. The AND gates AD 7 .1, AD 7 .3, AD 7 .5 and AD 7 .7 output values τ 0  ·β 3 , τ 1  ·β 3 , τ 2  ·β 3  and τ 3  ·β 3  respectively. 
     The values outputted from the AND gates AD 7 .1, AD 7 .3, AD 7 .5 and AD 7 .7 are applied to the exclusive OR gates XOR 8 .4, XOR 8 .6 and XOR 8 .8 which, in turn, perform exclusive ORing operations and thus output a value ((τ 0  ·β 3 )+(τ 1  ·β 3 )X+(τ 2  ·β 3 )X 2  +(τ 3  ·β 3 )X 3 )X 2 . 
     As mentioned above, the AND gates AD 1 .1, AD 1 .3, AD 1 .5, AD 1 .7, AD 3 .1, AD 3 .3, AD 3 .5, AD 3 .7, AD 5 .1, AD 5 .3, AD 5 .5, AD 5 .7, AD 7 .1, AD 7 .3, AD 7 .5 and AD 7 .7 are always fixed, irrespective of the source polynomial P(X). However, the exclusive OR gates XOR 6 .4, XOR 6 .6, XOR 8 .4, XOR 8 .6 and XOR 8 .8 are determined by the source polynomial P(X). 
     In a calculation with respect to an optional source polynomial P(X)=P 3  X 3  +P 2  X 2  +P 1  X+P 0 , a circuit of FIG. 8 may be used. 
     The exclusive OR gate XOR 9 .2 receives outputs from the AND gates AD 1 .1, AD 3 .7, AD 5 .5 and AD 7 .3 and exclusively ORs them, to output a final value W 0 . The exclusive OR gate XOR 9 .4 receives an output from the AND gate AD 1 .3 and outputs from the exclusive OR gates XOR 4 .4, XOR 6 .4 and XOR 8 .4 and exclusively ORs them, to output a final value W 1 . 
     On the other hand, the exclusive OR gate XOR 9 .6 receives outputs from the AND gates AD 1 .5 and AD 3 .3 and outputs from the exclusive OR gates XOR 6 .6 and XOR 8 .6 and exclusively ORs them, to output a final value W 2 . The exclusive OR gate XOR 9 .8 receives outputs from the AND gates AD 1 .7, AD 3 .5 and AD 5 .3 and an output from the exclusive OR gate XOR 8 .8 and exclusively ORs them, to output a final value W 3 . 
     The calculation procedures are summarized by the following equation: ##EQU3## 
     The value W is applied to the adder 56 of FIG. 6 and added with the value stored in the first register 53. 
     That is, when the value (τ·β)+Θ is required to be derived, which corresponds to a value obtained by adding the value Θ stored in the first register 53 to the value τ·β inputted at the adder 56, input data Θ 0 , Θ 1 , Θ 2  and Θ 3  are applied to inputs of the exclusive OR gates XOR 9 .2, XOR 9 .4, XOR 9 .6 and XOR 9 .8, respectively. 
     For an operation in GF(2 m ) other than GF(2 4 ), it can be achieved by an expansion design up to 2M+1 rows and 2M columns. 
     FIG. 10 is a block diagram of a Forney syndrome operation apparatus according to a second embodiment of the present invention. 
     As shown in FIG. 10, the operation apparatus comprises a storing register 61 for storing results sequentially inputted therein, a multiplexor 62 for receiving outputs from the storing register 61 and selecting a necessary coefficient, and a switch SW for selecting one of an output value of the multiplexor 62 and a syndrome S(X). To the multiplexor 62, a first register 63 and a second register 64 are connected via the switch SW. The registers 53 and 64 receive the coefficient currently selected by the multiplexor 52 and the coefficient just previously selected by the multiplexor 52, respectively. The operation apparatus also comprises a multiplier 65 for multiplying a power value α jk  corresponding to an input erasure position and the coefficient loaded in the second register 64, and an adder 66 for adding a value outputted from the multiplier 65 to the coefficient loaded in the first register 63 and outputting the resultant value to the storing register 61. 
     The Forney syndrome is expressed by the following equation: ##EQU4## wherein, e represents the number of erasures. 
     Accordingly, the syndrome S(X), can be calculated in the order of T 1  (X)→T 2  (X) . . . →T e  (X), in similar manner to the erasure position polynomial. 
     In this case, the i-th coefficient of T n  (X) is expressed as follows: 
     
         T(i)=T.sub.n (i)-T.sub.n-1 (i-1)α.sup.j(n) 
    
     
         T.sub.n (O)=S.sub.0 
    
     The above procedure will be described in detail. 
     Initially, the switch SW is connected at its movable terminal c to its fixed terminal a so that S 0  to S 2t-1  of the syndrome S(X) are sequentially inputted. 
     When a calculation through the first and second registers and 64, the multiplier 65 and tile adder 66 is completed, the storing register 61 is loaded with S 2t-1 α j1 , S 2t-1 α j1  +S 2t-1 , . . . , S 1  α j1  +S 0  and S 0 α j1  +S 0 , in this order, 
     Thereafter, the switch SW is switched such that the movable terminal c is connected to the fixed terminal b. At this time, the first and second registers 63 and 64 are set to 0. Then, the multiplexor 62 selects S 0 α j1  +S 1 . Accordingly, the values T i  and T i-1  stored in the first and second registers 63 and 64 become S 0 α j1  +S 1  and S 0 , respectively, so that the storing register 61 receives S 0 α j2  +S 0  α j1  +S 1  as its input The multiplexor 62 selects S 1  α j1  +S 2 . 
     After the operation is carried out up to S 2t-1  α j2 , the calculation for n=2 is completed. 
     That is, the calculation is repeated 2t+1 times, for calculating T 2  (X). For n=3, calculations of 2t+1 times are repeatedly carried out, so as to complete the calculation for T 3  (X) 
     After the polynomial T(X) with the degree of 2t-1+e is calculated by repeating the above procedures, it is applied to the storing register 61. 
     The switch SW may be omitted. In this case, the syndrome S(X) is directly inputted at the storing register 6. 
     The storing registers 51 and 61 are capable of storing the maximum length, namely, 2t+e coefficients. Preferably, they are last-in first-out registers. 
     As apparent from the above description, the present invention makes it possible to derive an erasure position polynomial by using a single multiplier and a single adder, irrespective of an error correction capacity, upon sequentially deriving coefficients of the erasure position polynomial while increasing the degree of the erasure position polynomial one by one. Accordingly, an integration of the operation apparatus can be possible. Also, the present invention provides effects of simplifying the design of the adder and achieving a correct operation. 
     Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.