Abstract:
A carrier frame and semiconductor package including a carrier frame provide improved thermal performance and mechanical stability for semiconductor packages using thin substrate materials. A metal carrier frame is attached to a substrate to provide support during and after the manufacturing process. A semiconductor die is mounted through an aperture in the center of the carrier frame and electrically connected to the substrate via wire bonding. The assembly is then encapsulated and singulated and a portion of the carrier frame remains in the package, improving thermal transfer from the semiconductor die. The assembly may further include a header for covering the aperture after the semiconductor die is wire bonded. The header/carrier combination may include means for improving encapsulant flow to the region under the header and surrounding the semiconductor die, which may include cut portions in the carrier frame or aligned holes through the carrier frame and header. The connection of header and carrier frame may be made self-aligning via protrusions on the header and depressions in the carrier frame or other mechanical alignment means.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to integrated circuit packaging and more specifically, to a semiconductor package assembly that includes a carrier frame for mounting a semiconductor die.  
         BACKGROUND OF THE INVENTION  
         [0002]    Semiconductor packages are generally constructed by mounting and electrically connecting a semiconductor die (which may contain any of a variety of electrical circuits and distributing connections) to a substrate. The substrate and semiconductor die are typically sealed by an encapsulant, to protect the semiconductor die and circuits from external environments such as dust, moisture and electrical and mechanical shock. A printed circuit board, circuit tape, circuit film or lead frame are generally used as the substrate.  
           [0003]    Typical semiconductor packages are manufactured in a variety of ways. Recently, in order to meet demands for low weight, small and thin packages as well as simplicity of manufacture and assembly, circuit tape and similar thin structures having a high interconnect density are used as substrates. In the above-mentioned type of semiconductor package, since the substrate easily bends during the manufacturing process, most manufacturing processes are performed using a metal carrier frame is attached to the top surface of the substrate. The carrier frame is removed from the substrate after the completion of the manufacturing process.  
           [0004]    However, the above-described conventional semiconductor package provides poor heat discharge, since the package is not provided with a heat sink. Recently, with a trend toward an increase in operating frequency of semiconductor dies, an inevitable increase in heat generation has occurred. Therefore, the above-described conventional semiconductor package is inappropriate for packaging semiconductor dies that generate high heat. If a high heat semiconductor die is packaged in the above described semiconductor package, warping can occur, resulting in cracking of the semiconductor die or separation of the semiconductor package from external electrical connections.  
           [0005]    The above separation problem occurs when the semiconductor package is bends in its cross-section, that is, the substrate becomes concave or convex in shape. The result is that the semiconductor die cracks and/or the semiconductor package becomes disconnected external connections, due to a difference in the coefficient of thermal expansion among the elements of the semiconductor package and the absence of a means for preventing warping.  
           [0006]    Therefore, it would be desirable to provide a semiconductor package having a thin profile and low weight that will not severely warp or crack the semiconductor die when heat is generated within the semiconductor package.  
         SUMMARY OF THE INVENTION  
         [0007]    The above stated objectives are achieved in various assemblies and methods for packaging a semiconductor die that include a carrier frame within the completed semiconductor package assembly. The assemblies include a carrier frame, a substrate, a semiconductor die and an encapsulation. The carrier frame provides support for thin substrates during and after the manufacturing process and may further provide a heat sink after manufacture of the semiconductor package. The carrier frame defines an aperture through a center portion that is raised above the plane of the carrier frame for accommodating a semiconductor die underneath. The aperture may be covered by a header that is attached to the carrier frame after the semiconductor die is attached and wire bonded to the substrate.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    [0008]FIG. 1A is a perspective view of a carrier frame in accordance with an embodiment of the present invention;  
         [0009]    [0009]FIG. 1B is a cross-sectional view of the carrier frame of FIG. 1A;  
         [0010]    [0010]FIG. 2A is a perspective view of a carrier frame in accordance with another embodiment of the present invention;  
         [0011]    [0011]FIG. 2B is a cross-sectional view of the carrier frame of FIG. 2A;  
         [0012]    [0012]FIG. 3A is a perspective view of a carrier frame in accordance with another embodiment of the present invention;  
         [0013]    [0013]FIG. 3B is a cross-sectional view of the carrier frame of FIG. 3A;  
         [0014]    [0014]FIG. 4A is a perspective view of a carrier frame in accordance with another embodiment of the present invention;  
         [0015]    [0015]FIG. 4B is a cross-sectional view of the carrier frame of FIG. 3A;  
         [0016]    [0016]FIG. 5 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention;  
         [0017]    [0017]FIG. 6 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention;  
         [0018]    [0018]FIG. 7A is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention;  
         [0019]    [0019]FIG. 7B is a plan view of the semiconductor package of FIG. 7A before an encapsulant is applied;  
         [0020]    FIGS.  8 A- 8 E are cross-sectional views illustrating a method for manufacturing a semiconductor package in accordance with an embodiment of the present invention;  
         [0021]    FIGS.  9 A- 9 G are cross-sectional views illustrating a method for manufacturing a semiconductor package in accordance with another embodiment of the present invention; and  
         [0022]    FIGS.  10 A- 10 B are cross-sectional views illustrating a method for manufacturing a semiconductor package in accordance with another embodiment of the present invention. 
     
    
       [0023]    The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout.  
       DETAILED DESCRIPTION  
       [0024]    Referring to both FIGS. 1A and 1B, a perspective and cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention is illustrated.  
         [0025]    A substantially rectangular carrier frame  11  including a substantially planar outer frame  2  is provided for integration within a semiconductor package by attachment to s substrate (not shown). Carrier frame  11  includes a raised portion defined by an inclined surface  4  having a predetermined within outer frame  2 . An inner frame  6  is formed at an area within the boundary defined by the inside of inclined surface  4 . Inner frame  6  is substantially planar and parallel to outer frame  2  and defines an aperture  7  formed at the center of inner frame  6  for mounting a semiconductor die to a substrate underneath aperture  7 .  
         [0026]    A plurality of inclined surfaces  4  and inner frames  6  are formed on carrier frame  11  and are arranged in a line. The structures formed by inclined surfaces  4  and inner frames  6  are bounded between by a slot  3  formed in outer frame  2  to provide a strip type carrier frame  11 . Aperture  7  can be formed in a rectangular or square shape, depending on semiconductor die mounting requirements. Outer frame  2 , inclined surface  4  and inner frame  6  may be any metal material having high thermal conductivity, such as aluminum (Al), copper (Cu) or iron (Fe). In an alternative embodiment, inner frame  6  of the carrier frame  11  is subjected to an oxidation process on the surface of inner frame  6 , or may include a plurality of holes or depressions (not shown) in order improve bonding an encapsulant at those surfaces when an encapsulant is applied.  
         [0027]    Referring now to FIGS. 2A and 2B a perspective and a cross-sectional view of another embodiment of the present invention are illustrated. A plurality of cut portions  8  having a predetermined breadth can formed at each of the corners of inner frame  6  of a carrier frame  12  around aperture  7 , to provide a improved flow of encapsulant during manufacture of the semiconductor package.  
         [0028]    An auxiliary frame  14  can be provided for coupling to the top surface of inner frame  6  of carrier frame  12 . Auxiliary frame  14  includes a flange  15  parallel to the plane of the inner frame  6  and chamfers  16  formed at the corners, an inclined surface  17  extending from flange  15 , and a cover  18  extending from inclined surface  17  for covering aperture  7 . A plurality of protrusions  19  can be formed on the bottom surface of the flange  15  and a plurality of holes  9  can be further formed at the inner frame  6  of the carrier frame  12  corresponding to the locations of protrusions  19 .  
         [0029]    Auxiliary frame  14  is coupled with the top surface of inner frame  6  of carrier frame  12 , after a semiconductor die is connected to a substrate by conductive wires. Protrusions  19  on flange  15  of auxiliary frame  14  are coupled with holes  9  of inner frame  6 , providing a self-alignment mechanism. In an alternative embodiment, auxiliary frame  14  and inner frame  6  can be connected together by an attach material and without forming protrusions  19  and holes  9  in the components.  
         [0030]    Auxiliary frame  14  is used as a heat sink in the semiconductor package and the material may be any metal material having high thermal conductivity, such as aluminum (Al), copper (Cu) or iron (Fe), improving thermal performance of the semiconductor package. In an alternative embodiment, inner frame  6  of carrier frame  11  is subjected to an oxidation process or similar process on its surface, and inner frame  6  may include a plurality of holes or depressions (not shown). The above-described oxidation, holes or depressions can be equally applied to all carrier auxiliary frames described below.  
         [0031]    Referring now to both FIGS. 3A and 3B, a perspective and a cross-sectional view of another embodiment of the present invention is illustrated. In FIGS. 3A and 3B, elements respectively corresponding to those in FIGS. 2A and 2B are denoted by the same reference numerals. A flange  15  of an auxiliary frame  14 ′ located at the top surface of carrier frame  12  can further include a plurality of holes  20  having the same diameter as holes  9  of the inner frame  6  and corresponding in location to holes  9  of inner frame  6 . Holes  20  of auxiliary frame  14 ′ provide for ready flow of an encapsulant during manufacture of the semiconductor package. The operation of holes  9  and holes  20  will be described in detail in the description of the method of manufacturing the semiconductor package.  
         [0032]    Referring now to FIGS. 4A and 4B, a perspective and a cross-sectional view of another embodiment of the present invention is illustrated. A carrier frame  13  includes a plurality of inner frames  6  having a plurality of apertures  7 , arrayed in rows and columns. Carrier frame  13  is adapter for attachment a matrix-type substrate. Generally, the present embodiment is used in tape array ball grid array (TABGA) manufacture.  
         [0033]    Referring now to FIG. 5, a cross-sectional view of one embodiment of the present invention is illustrated. A semiconductor package  101  includes a semiconductor die  40  that includes a plurality of bond pads  42  at a top surface thereof. A Substrate  30 , which has an area larger than semiconductor die  40  area, is attached to the bottom surface of semiconductor die  40  by a die attach material  38 . Die attach material  38  may be an epoxy adhesive, epoxy film or an equivalent. Substrate  30  includes an insulating layer  32  and a conductive layer  34  having a plurality of bond fingers  35  and a plurality of lands  36  formed on a top surface. Lands  36  are exposed to the bottom of substrate  30  through a plurality of holes  37  formed through insulating layer  32 . As is well known in the art, it is a circuit tape or a circuit film is desirable for implementing substrate  30 .  
         [0034]    Bond pads  42  of semiconductor die  40  and bond fingers  35  of conductive layer  34  of substrate  30  are electrically connected together by a plurality of wires  44 . Wires  44  may be made from any conductive material such as gold (Au), Aluminum (Al) or an equivalent. An inner frame  6  is located at the top surface of the substrate  30 . Inner frame  6  includes an aperture  7  having sufficient size such that semiconductor die  40  will not obstruct the inner frame  6 . Inner frame  6  is separated by a predetermined distance from the substrate  30  and wire  44  is also separated from inner frame  6  in order to prevent electrical contact. Semiconductor die  40 , the top surface of substrate  30 , wires  44  and inner frame  6  are all encapsulated by an encapsulant  46 . A plurality of solder balls  48  are fused to lands  36  of conductive layer  34  of substrate  30  for mechanical and electrical connection to an external device.  
         [0035]    Referring now to FIG. 6, a cross-sectional view of another embodiment of the present invention is illustrated. Since the illustration depicts a semiconductor package  102  similar to the semiconductor package  101  of FIG. 5, only those differences existing between the embodiments will be described in detail below. An auxiliary frame  14  (see FIGS. 2A and 2B) is located at the top surface of carrier frame  12  improve the thermal transfer from semiconductor package  102  and thereby prevent warping of substrate  30 .  
         [0036]    Auxiliary frame  14  includes flange  15 , which is substantially planar and coupled to the top surface of inner frame  6 . Auxiliary frame  14  further includes an inclined surface  17  that extends upward to from the inside of flange  15  to a cover  18  formed in the center of auxiliary frame  14  cover aperture  7  of inner frame  6 . A plurality of holes  9  are formed through inner frame  6  and a plurality of protrusions  19  are further formed on the bottom surface of the flange  15  at locations corresponding to the locations of holes  9 , so that auxiliary frame  14  and inner frame  6  are coupled together. The top surface of cover  18  is exposed to the outside of encapsulation  46 , thereby further improving thermal performance.  
         [0037]    Referring next to FIGS. 7A and 7B, a semiconductor package  103  similar to semiconductor packages  102  of FIG. 6 is depicted and therefore only differences existing there between will be described in detail below. Flange  15  includes a plurality of holes  20  having the same diameter as holes  9  through inner frame  6 . Encapsulation  46  is formed in part by encapsulant passing through holes  9  of inner frame  6  and holes  20  of auxiliary frame  14 ′, thereby improving the bond between the encapsulant  46 , inner frame  6  and auxiliary frame  14 ′.  
         [0038]    Holes  9  and  20  of inner frame  6  and auxiliary frame  14 ′ serve to improve flow of the encapsulant during manufacture of the semiconductor package. Encapsulant flows easily around semiconductor die  40  through cut portions  8 , holes  20  of auxiliary frame  14 ′ and holes  9  of inner frame  6 . If holes  20  are not formed through auxiliary frame  14 ′, encapsulant will only flow around semiconductor die  40  only through cut portion  8 . Thus holes  20  of auxiliary frame  14 ′ provide a means for permitting additional flow as described above, as well as the cut portions  8 , thereby providing improved flow in the formation of encapsulation  46 .  
         [0039]    FIGS.  8 A through FIG. 8E illustrate cross-sectional views for illustrating one method for manufacturing a semiconductor package in accordance with an embodiment of the present invention. Referring now to FIG. 8A, the semiconductor package is depicted after a carrier frame  11  is attached to a substrate. Carrier frame  11  includes an outer frame  2  that is substantially planar, an inclined surface  4  extending upward to the inside of outer frame  2 , and inner frame  6  extending to the inside of inclined surface  4 , having a planar surface parallel to outer frame  2 . Aperture  7  for mounting a semiconductor die is disposed in the center of inner frame  6 .  
         [0040]    Substrate  30 , on which conductive layer  34  including bond fingers  35  as well lands  36  is disposed, is attached to the bottom surface of outer frame  2  of carrier frame  11  by attach material  39  disposed between carrier frame  11  and substrate  30 . Lands  36  are exposed through the bottom surface of substrate  30  through holes  37  formed through insulating layer  32 .  
         [0041]    Referring next to FIG. 8B, a semiconductor package is depicted after a semiconductor die attach and a wire bonding step are performed. Semiconductor die  40  having bond pads  42  is attached to the top surface of substrate  30 , which is exposed through carrier frame  11  via aperture  7 . Then, bond pads  42  of semiconductor die  40  and bond fingers  35  of conductive layer  34  of substrate  30  are electrically connected by wires  44 .  
         [0042]    Now referring to FIG. 8C, after encapsulation, carrier frame  11 , semiconductor die  40  and wires  44 , are covered by an encapsulation  46  formed from an encapsulant such as an epoxy molding compound or equivalent. Next, referring to FIG. 8D, the semiconductor package is shown after a solder ball fusing step is performed. Solder balls  48  are fused to each land  36  exposed to the bottom surface of substrate  30 . The solder balls  48  provide for mechanical and electrical connection of the semiconductor package to an external device after manufacture.  
         [0043]    Finally, referring to FIG. 8E, the semiconductor package is, completed by a singulation step, wherein carrier frame  11  is sawn SO that inner frame  6  remains inside of encapsulant  46 , but the semiconductor package is separate from the rest of carrier frame  11  and a portion of substrate  30 .  
         [0044]    [0044]FIG. 9A through FIG. 9G are cross-sectional views illustrating another method for manufacturing a semiconductor package in accordance with an embodiment of the present invention. Referring first to FIG. 9A, a semiconductor package is depicted after a carrier frame  12  is attached to a substrate  30 . Carrier frame  12  includes a substantially planar outer frame  2  and an inclined surface  4  extending upward to the inside of an inner frame  6 . An aperture  7  of a predetermined size is formed in the center of carrier frame  12 .  
         [0045]    A substrate  30 , on which a conductive layer  34  having bond fingers  35  and lands  36  is disposed, is attached to the bottom surface of outer frame  2  of carrier frame  11  by an attach material  39 . In addition, cut portions  8  (see FIG. 2A) can be formed at each corner of inner frame  6 . Inner frame  6  further includes holes  9 , which pass through inner frame  6  vertically. Substrate  30  includes an insulating layer  32  and a conductive layer  34  Lands  36  are exposed to the bottom surface of substrate  30  through holes  37  formed through insulating layer  32 .  
         [0046]    Referring now to FIG. 9B, a semiconductor package is depicted after a die attach and a wire bonding step. Semiconductor die  40  including the bond pads  42  is attached to the top surface of substrate  30 . The upper surface of semiconductor die  40  is exposed through aperture  7 . Bond pads  42  of semiconductor die  40  and bond fingers  35  of conductive layer  34  of substrate  30  are electrically connected by wires  44 .  
         [0047]    Now referring to both FIGS. 9C and 9D, the semiconductor package is depicted after an auxiliary frame  14  is attached. Auxiliary frame  14  is mounted on the top surface of inner frame  6 . Auxiliary frame  14  includes a substantially planar flange  15  having chamfers  16  formed at each corner and coupled with the top surface of inner frame  6 . Auxiliary frame  14  further includes inclined surface  17  extending upward from flange  15  to a cover  18  in the inside of inclined surface  17  for covering aperture  7  of inner frame  6 . Protrusions  19  further formed on the bottom surface of flange  15  and having locations corresponding to the locations of holes  9  of inner frame  6  align with holes  9  so that the auxiliary frame  14  is easily aligned with and coupled to inner frame  6 .  
         [0048]    Referring next to FIG. 9E, the semiconductor package is depicted after an encapsulant has been applied. The encapsulant fills the volume around semiconductor die  40  through cut portions  8  formed in inner frame  6  to form encapsulation  46 . In an alternative embodiment, it is preferable that the top surface of the cover  18  is exposed through the top surface of encapsulation  46 , to improve thermal transfer.  
         [0049]    Referring next to FIG. 9F, the semiconductor package is depicted after solder balls  48  are fused to each land  36  exposed through the bottom surface of substrate  30  by holes  37 . The solder balls  48  provide for electrical and mechanical connection of the semiconductor package to an external device after manufacture.  
         [0050]    Referring last to FIG. 9G, the semiconductor package is shown after singulation. Carrier frame  12  is sawn so that inner frame  6  and auxiliary frame  14  are retained within encapsulant  46 , but separating the semiconductor package from carrier frame  12  and a portion of substrate  30 .  
         [0051]    [0051]FIGS. 10A and 10B are cross-sectional views illustrating another method for manufacturing a semiconductor package in accordance with an embodiment of the present invention. As the manufacturing method for producing semiconductor package  103  is similar to that for producing semiconductor package  102  as described above, only those differences between the methods will be described in detail below. In semiconductor package  102  as described above, encapsulant flows around semiconductor die  40  through only cut portions  8  formed in inner frame  6  to form encapsulant  46 . But, in the semiconductor package  103  as shown in FIG. 7A, since holes  9  of inner frame  6  and holes  20  of auxiliary frame  14 ′ provide a vertical flow path through inner frame  6  and auxiliary frame  14 , an encapsulant may flow around semiconductor die  40  through holes  9  and holes  20  as well as through cut portion  8 , providing improved flow of encapsulant during formation of encapsulation  46 .  
         [0052]    Holes  9  of and holes  20  of the auxiliary frame  14 ′ are coupled together after encapsulation is complete, improving the bond between encapsulant  46 , inner frame  6  and auxiliary frame  14 ′. Top mold  51  and bottom mold  52  are shown surrounding semiconductor package to depict the encapsulation process.  
         [0053]    This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.