Abstract:
A light emitting diode (LED) chip includes an N-type semiconductor layer, a compensation layer arranged on the N-type semiconductor layer, an active layer arranged on the compensation layer; and a P-type semiconductor layer arranged on the active layer. During growth of the compensation layer, atoms of an element (i.e., Al) of the compensation layer move to fill epitaxial defects in the N-type semiconductor layer, wherein the epitaxial defects are formed due to lattice mismatch when growing the N-type semiconductor. A method for manufacturing the chip is also disclosed. The compensation layer is made of a compound having a composition of Al x Ga 1-x N.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure generally relates to solid state light emitting devices and, more particularly, to a light emitting diode (LED) chip with high reverse voltage and a manufacturing method thereof. 
     2. Description of the Related Art 
     LEDs have many advantages, such as high luminosity, low operational voltage, low power consumption, compatibility with integrated circuits, easy driving, long term reliability, and environmental friendliness, which have promoted the wide use of LEDs as a light source. 
     Generally, an LED chip includes a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer arranged on the substrate in sequence. The active layer may be a multiple-quantum-wells (MQWs) layer. Referring to  FIG. 1 , a plurality of defect energy levels  10  may be distributed in the active layer of the LED chip. When applying a small reverse current for the LED chip, the electrons are easily to move from the P-type semiconductor layer to the N-type semiconductor layer through the defect energy levels  10  in the active layer; therefore, the reverse voltage of the LED is low, which is unfavorable for an LED. 
     Therefore, what is needed is a light emitting diode chip and a manufacturing method thereof which can overcome the described limitations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a distribution graph of energy levels of an LED chip in accordance with related art. 
         FIG. 2  is a schematic, isometric of an LED chip, according to an exemplary embodiment of the present disclosure. 
         FIG. 3  is a distribution graph of energy levels of the LED chip of  FIG. 2 . 
         FIG. 4  is a distribution graph of a reverse voltage of the LED chip of  FIG. 2  compared with a reverse voltage of the LED chip in accordance with the related art. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Referring to  FIG. 2 , an LED chip  20 , in accordance with an embodiment, is provided. The LED chip  20  includes a substrate  30 , and a buffer layer  40 , a semiconductor layer  41 , an N-type semiconductor layer  50 , a compensation layer  60 , an active layer  70  which can be a multiple-quantum-wells (MQWs) layer, a confinement layer  80  and a P-type semiconductor layer  90  arranged on the substrate  30  in sequence. 
     In the present embodiment, the substrate  30  is made of a Al 2 O 3 , and a patterning structure is formed on a top surface of the substrate  30  via etching. The patterning structure includes a plurality of protrusions  32  evenly formed on the top surface of the substrate  30 . In the present embodiment, each of the protrusions  32  has a peak, and the peaks of the convex protrusions  32  are coplanar. The protrusions  32  can reduce the lattice mismatch between the substrate  30  and the semiconductor layer formed on the substrate  30 . 
     The buffer layer  40  is grown on the substrate  30 . The undoped GaN layer  41  is grown on the substrate  30 . The buffer layer  40  has a patterning structure at a bottom surface thereof. A top surface of the buffer layer  40  is planar. Since the top surface of the substrate  30  has the patterning structure matching with the patterning structure formed on the bottom surface of the buffer layer  40 , the lattice mismatch between the substrate  11  and the buffer layer  40  is reduced. The buffer layer  40  is made of low temperature undoped GaN. The semiconductor layer  41  is made of high temperature undoped GaN. 
     The N-type semiconductor layer  50  is grown on the semiconductor layer  41  by epitaxy. The N-type semiconductor layer  50  is an N-type GaN layer, and can be doped with SiH 4 . The N-type semiconductor layer  50  defines a recess  52  at a lateral side thereof. The recess  52  extends through an upper portion of the N-type semiconductor layer  50  at the lateral side thereof, along a direction from a top surface of the N-type semiconductor layer  50  towards to a bottom surface thereof. An N-type electrode  22  is formed in the recess  52  and electrically connected to the N-type semiconductor layer  50 . The N-type semiconductor layer  50  provides electrons for the LED chip  20 . 
     The compensation layer  60  is grown on the N-type semiconductor layer  50 . In the present embodiment, the compensation layer  60  is made of undoped Al x Ga 1-x N (0&lt;x&lt;1). The content of Al of compensation layer  60  is about 0.1 to 10 percent (0.1-10%) by weight of the compound, and a thickness of the compensation layer  60  is in the range from 1 nm to 50 nm. In the present embodiment, the content of Al of compensation layer  60  is about 1 to 2 percent (1-2%) by weight of the compound, and the thickness of the compensation layer  60  is in the range from 15 nm to 25 nm. During growth of the compensation layer  60 , atoms of Al the compensation layer  60  will move downwardly to fill the few epitaxial defects which may occur over the peaks of the convex protrusions  32 ; therefore, the epitaxial defects due to the lattice mismatch between the substrate  30  and the buffer layer  40  is further blocked by the Al atoms of the compensation layer  60  in the N-type semiconductor layer  50 , and cannot extend to the active layer  70 , the confinement layer  80  and the P-type semiconductor layer  90 . Furthermore, a top surface of the N-type semiconductor layer  50  can be treated by trimethylaluminum (TMAl) gas before the compensation layer  60  is grown, whereby the Al atoms of the compensation layer  60  can fill the epitaxial defects in the N-type semiconductor layer  50  and over the peaks of the convex protrusions  32  due to lattice mismatch more quickly. The epitaxial defects can be dangling bonds. Generally, the trimethylaluminum gas is applied to the N-type semiconductor layer  50  for a period less than ten seconds before the compensation layer  60  is grown on the N-type semiconductor layer  50 . 
     In the present embodiment, the active layer  70  is grown on the compensation layer  60  directly and includes a multiple quantum well structure. In the present embodiment, the active layer  70  includes a plurality of AlyInxGa1−x−yN (x&gt;0, y&gt;0, x+y&lt;1) layers, a plurality of InxGa1−xN (0&lt;x&lt;1) and a plurality of InxAl1−xN (0&lt;x&lt;1) layers alternatively stacked together over the compensation layer  60 . The energy level of the active layer  70  is lower than that of the compensation layer  60 . 
     The confinement layer  80  is grown on the active layer  70 , and can be made of P-type AlGaN. The energy level of the confinement layer  80  is higher than that of the active layer  70 . The confinement layer  80  is used to guide cavities entering into the active layer  70  and enhance the combination efficiency of the electrons and the cavities; therefore, the light extraction efficiency can be improved. 
     The P-type semiconductor layer  90  is grown on the confinement layer  80 , and can be made of P-type GaN. Alternatively, the P-type semiconductor layer  90  is made of P-type Cp 2 Mg. The P-type semiconductor layer  90  provides cavities for the LED chip  20 . The cavities combine with the electrons provided by the N-type semiconductor layer  50  to generate photons. A P-type electrode  24  is formed on a top surface of the P-type semiconductor layer  90 . 
     Referring to  FIG. 3 , the energy level of the compensation layer  60  is higher than that of the active layer  70 , and the compensation layer  60  acts as a higher energy barrier  62  for the LED chip  20 ; therefore, when the LED chip  20  is applied with a small reverse current, the high energy barrier  62  of the compensation layer  60  can prevent the electrons from moving from the P-type semiconductor layer  90  to the N-type semiconductor layer  50  via the active layer  70 . Thus, the LED chip  20  has a high reverse voltage to obtain a high quality thereof. 
     Referring to  FIG. 4 , line  20   a  indicates a relation of reverse voltage and reverse current of the LED chip  20  having the compensation layer  60 , and line  20   b  indicates a relation of reverse voltage and reverse current of the LED chip without the compensation layer  60 . It can be seen from  FIG. 4  that, when applied with a current such as 0.01 mA, the reverse voltage of the LED chip  20  having the compensation layer  60  is 21V, and the reverse voltage of the LED chip without the compensation layer is 16V. Therefore, the LED chip  20  having the compensation layer  60  in accordance with the present disclosure has a higher reverse voltage than that of the LED chip which does not have the compensation layer. 
     It can be understood that the buffer layer  40 , the semiconductor layer  41 , the N-type semiconductor layer  50 , the compensation layer  60 , the active layer  70 , the confinement layer  80  and the P-type semiconductor layer  90  may be grown on the substrate  30  via Metal-Organic Chemical Vapor Deposition, Molecular Beam Epitaxy, Liquid Phase Epitaxy, Vapor Phase Epitaxy, or Physical Vapor Deposition and so on. 
     It is to be further understood that even though numerous characteristics and advantages have been set forth in the foregoing description of embodiments, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.