Abstract:
A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to the forming of capacitors of metal-insulator-metal type (MIM) in metallization levels of interconnection of semiconductor circuits. 
         [0003]    2. Discussion of the Related Art 
         [0004]    Capacitors having a capacitance on the order of from 5 to 50 fF/μm2 are more and more often directly formed in the metallization interconnect levels of the semiconductor circuits with which they are associated, rather than outside of such circuits. Such capacitors are intended to filter a signal with respect to a power supply, to form filters, to form an analog-to-digital converter, to form a voltage-controlled oscillator, or in radio-frequency applications. Such MIM capacitors may also be used as a memory point of memory devices. 
         [0005]      FIGS. 1 ,  2 ,  3 , and  4  illustrate different steps of manufacturing of a capacitor according to a known method.  FIG. 1  is a cross-section view.  FIG. 2  is a top view.  FIG. 3  is an enlarged view of a portion of  FIG. 1 .  FIG. 4  is a cross-section view at a step subsequent to those illustrated in  FIG. 1 . 
         [0006]    As illustrated in  FIG. 1 , the capacitor-forming method starts with the forming, in a first thick interlevel dielectric layer  1 , of a metal electrode  3 . A second thick interlevel dielectric layer  5  is deposited over layer  1  and electrode  3  altogether. Layer  5  is generally formed of a first relatively thin insulating sub-layer  51  and of a thick layer  52  of an insulator that may be selectively etched with respect to first sub-layer  51 . Sub-layer  51  is itself selectively etchable with respect to underlying layer  1 . Typically, sub-layer  51  is a silicon nitride sub-layer (Si3N4) while layer  1  and sub-layer  52  are made of silicon oxide (SiO2). Then, layer  5  is selectively opened to expose first electrode  3  according to a predetermined pattern. For example, as illustrated in the top view of  FIG. 2 , parallel trenches  21  are dug into layer  5 , five trenches of which are shown in cross-section view in  FIG. 1  and in top view in  FIG. 2 . Trenches  21  are interconnected by a common perpendicular trench  22 . Then, trenches  21 ,  22  are filled by successive conformal depositions of a thin metal layer  7 , of an interelectrode insulator  8 , of another thin metal layer  9 . A conductive layer  11  fills trenches  21  and  22 . Thin layer  7  is intended to increase the surface area of electrode  3  across the thickness of interlevel layer  5 . Layer  11  is generally formed of polysilicon, of copper, of a copper-based alloy or any other conductive material. 
         [0007]      FIG. 3  illustrates an enlarged cross-section view of  FIG. 1  at the level of a trench  21  ( FIG. 2 ). Conductive layers  7  and  9  are generally formed of respective sub-layers  71 ,  72  and  91 ,  92 . Sub-layers  71  and  92  are generally identical and are intended to ensure a proper adherence between electrode sub-layers  72  and  91  and conductive layer  3  or  11 , generally made of copper. Sub-layers  72  and  91 , which are on either side of insulator  8  interposed between the electrodes, are also generally identical and are selected to ensure optimal electric performances. In particular, sub-layers  72  and  91  are selected to minimize the migration of the species forming them in the dielectric forming insulator  8 . In addition, sub-layers  72  and  91  are selected to minimize the migration of the species forming insulator  8  in sub-layers  72  and  91 . Typically, sub-layers  71 ,  72 ,  91 , and  92  have a respective thickness of approximately 10 nm. Electrode sub-layers  71  and  92  are typically made of tantalum nitride (TaN). Sub-layers  72  and  91  are typically made of titanium nitride (TiN). Interelectrode dielectric  8  has an approximate thickness from 15 to 50 nm, for example, 30 nm, and is typically made of silicon nitride. 
         [0008]    After the depositions of layers  7 ,  8 ,  9 , and  11 , these layers are removed from the surface of layer  5  to only be kept in trenches  21  and  22  of  FIG. 2 . For this purpose, a chem.-mech. polishing, CMP, is generally performed. 
         [0009]    At the next steps, as illustrated in the cross-section view of  FIG. 4 , a new interlevel dielectric layer  15  generally formed of a first thin sub-layer  151  typically made of silicon nitride and of a second thick sub-layer  152  typically made of silicon oxide is deposited over the entire structure. 
         [0010]    The method then carries on with steps, not shown, aiming at completing the structure by the forming of contacts with lower electrode  3 - 7  and with upper electrode  9 - 11 . It should be noted that an upper mechanical electrode  60  illustrated in dotted lines in  FIG. 2  is frequently formed in layer  15 . 
         [0011]    A disadvantage of the above-described method lies in the fact that the resulting capacitors have relatively high leakage currents and this, randomly, between electrodes  9 - 11  and  7 - 3 . Thus, the leakage currents for a 5-V voltage difference are greater than 10-6 A/cm2. Further, the capacitors have breakdown voltages randomly distributed across a wide range between 10 and 25 volts. Such variations are said to be random since these intervals not only appear between two capacitors formed in different wafers, but also between capacitors formed in a same wafer. 
       SUMMARY OF THE INVENTION 
       [0012]    The present invention aims at providing a method for manufacturing MIM capacitors which overcomes the disadvantages of known methods. 
         [0013]    The present invention also features providing such a method which provides MIM capacitors which exhibit breakdown voltages with a reduced distribution. 
         [0014]    The present invention features providing such a method which provides MIM capacitors which exhibit leakage currents having a substantially stable value lower than 10-6 A/cm2. 
         [0015]    The present invention also features providing such a method which provides MIM capacitors which exhibit a surface capacitance greater than that of known capacitors. 
         [0016]    The present invention also features providing such a method which is simple to implement. 
         [0017]    To achieve all or part of these objects, as well as others, the present invention provides a method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor comprising on either side of a thin vertical insulating layer at least one conductive layer of same nature, comprising the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them. 
         [0018]    According to an embodiment of the present invention, the lowering is performed after complete filling of a cavity intended to receive the capacitor with the materials intended to form the electrodes with the possible exception of a metal plate intended to form a contact portion of an electrode. 
         [0019]    According to an embodiment of the present invention, the lowering is followed by a conformal deposition of a layer of an insulating material. 
         [0020]    According to an embodiment of the present invention, the insulating material is of same nature as the thin vertical insulating layer separating the vertical extensions of the electrodes. 
         [0021]    The present invention also provides a MIM-type capacitor, two electrodes of the capacitor comprising on either side of a thin vertical insulating layer at least one conductive layer of same nature, the level of the conductive layers being lowered with respect to the level of the insulating layer separating them. 
         [0022]    According to an embodiment of the present invention, the level difference between the conductive layers and the insulating layer is totally or partially compensated for by an insulating material. 
         [0023]    According to an embodiment of the present invention, the insulating material is of same nature as the insulating layer. 
         [0024]    The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]      FIG. 1 , previously described, illustrates in cross-section view a MIM capacitor at an intermediary step of its manufacturing according to a known method; 
           [0026]      FIG. 2 , previously described, illustrates in top view another step of manufacturing of a capacitor according to the known method; 
           [0027]      FIG. 3 , previously described, is an enlarged cross-section view of a portion of  FIG. 1 ; 
           [0028]      FIG. 4 , previously described, illustrates another intermediary step of the manufacturing of a capacitor according to the known method; 
           [0029]      FIG. 5  illustrates, in cross-section view, a step of a method for manufacturing a MIM capacitor according to the present invention; and 
           [0030]      FIG. 6  illustrates, in cross-section view, another step of the method for manufacturing a MIM capacitor according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]    For clarity, the same elements have been designated with the same reference numerals in the different drawings. Further, as usual in the representation of semiconductor circuits, the various drawings are not to scale. 
         [0032]    The present invention advantageously takes advantage of the studies made by the present inventors on the behavior of MIM capacitors obtained by the known method described in relation with  FIGS. 1 to 4 . In particular, the present inventors have succeeded in determining that current leakages originate from the perimeter of the capacitors, at the surface of the filled trenches. 
         [0033]    By more precisely studying the structure, they have reached the conclusion that, in the chem.-mech. polishing, residues of the metallic materials of layers  72  and  91  located on either side of interelectrode insulator  8  come into contact and form a short-circuit. 
         [0034]    A method according to the present invention starts with capacitor-forming steps similar to those previously described in relation with  FIGS. 1 ,  2 , and  3  comprising the filling of trenches  21 - 22  by means of successive metallic and insulating materials  7 ,  8 ,  9 , and  11 , followed by a chem.-mech. polishing. 
         [0035]      FIG. 5  illustrates steps implemented according to a method according to the present invention after the CMP polishing, the result of which is illustrated in  FIG. 3 . For clarity, only the differences between  FIG. 3  and  FIG. 5  are described hereafter. 
         [0036]    After implementation of the CMP polishing, a specific etch step is implemented. This etch is capable of etching the sole conductive sub-layers  72  and  91  located on either side of the interelectrode insulator  8 , left intact. The etch is preferably capable of leaving intact the sub-layers of same nature  92  and  71  of the first and second electrodes as well as interlevel and interelectrode insulators  5  and  8 . Openings  17  and  19  respectively delimited by the sub-layer  71  and  92  left in place are thus formed on either side of insulator  8 . 
         [0037]    Then, as illustrated in  FIG. 6 , interlevel layer  15  is deposited. On deposition of layer  15 , first sub-layer  151  deposits on either side of interelectrode insulator  8  and partially or totally fills openings  17  and  19 . 
         [0038]    The method carries on with any appropriate step of forming of the capacitors and of the interconnects of the underlying semiconductor circuits, not shown. 
         [0039]    Thus, for a total height of interlevel layer  5  of approximately 650 nm, after having removed a height h from 40 to 100 nm of sub-layers  91  and  72 , for a 5-V voltage applied between electrodes  3 - 7  and  11 - 9 , leakage current densities lower than 10-8 A/cm2 can be observed. Such a leakage level is negligible and is lower by a at least a factor  100  with respect to known devices. Further, when the dimensions, in particular width w ( FIG. 2 ) of trenches  21  and width s of the space separating two neighboring trenches, are decreased, this value remains substantially steady. Further, the distribution of the breakdown voltages of the obtained capacitors is narrowed with respect to that of known capacitors. Thus, the breakdown voltage variation range extends from 15 to 25 V. Further, the breakdown voltage is substantially homogeneous for a same height h of removal of sub-layers  72  and  91 . 
         [0040]    Such improvements of the electric performances with respect to those of known capacitors are further obtained with no notable complication of the manufacturing process. In particular, they are obtained without use of an additional mask. Such improvements are indeed obtained by only implementing simultaneous etch steps of layers  72  and  91 . Such steps are self-aligned. Further, cavities  17  and  19  are partially or totally filled without implementing specific steps but by using the deposition of the superposed interlevel insulator  15 . 
         [0041]    As an example, the partial removal of titanium nitride sub-layers  72  and  91  is performed by chemical etching by means of a water, hydrogen peroxide (H2O2), and ammonia (ammonium hydroxide NH4OH) solution. Such an etching may be followed by a cleaning with hydrofluoric acid (HF). It should be noted that during this last cleaning, the interelectrode insulator  8  generally formed of silicon nitride can be etched. However, such an etching is light, only occurs in cavities  17  and  19  and is compensated for by the deposition of insulating sub-layer  151 . Such an etching thus has no effect upon the performance of the obtained capacitor. 
         [0042]    Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, only those steps necessary to the understanding of the present invention have been described. Thus, it will be within the abilities of those skilled in the art to form, if necessary, contacts with electrodes  3 - 7  and/or  9 - 11  and possibly form these contacts simultaneously to the forming of the capacitors or other interconnects. 
         [0043]    Further, the implementation of the present invention is not limited to a given capacitor shape. Thus, the electrodes may be formed simultaneously, each of them being comb-shaped and the teeth of such combs being interdigited. For this purpose, separate trenches having the desired shape may for example be formed, before deposition of the electrode layers simultaneously in all the trenches, a CMP polishing may be implemented to individualize each electrode in a respective trench and the removal according to the present invention may be performed before depositing an insulating layer intended to fill the cavities formed by the removal. 
         [0044]    Moreover, the removal according to the present invention is not limited to the sole sub-layers  72  and  91 , but may also be implemented for sub-layers  71  and  92 . 
         [0045]    Besides, it will be within the abilities of those skilled in the art to bring any material and thickness modification necessary in a given technological process. Thus, the interelectrode insulating material of layer  8  will be adapted to the etch selectivity constraints of sub-layers  72  and  91  and to the desired electric performance. Similarly, it will be within the abilities of those skilled in the art to adapt the used conductive materials to the used technological process, in particular the material of sub-layers  72  and  91  to the previously-described etch selectivity constraints. 
         [0046]    It should be noted by those skilled in the art that the nature of the semiconductor circuits in the metallization levels of which the capacitors are formed has not been described in detail and that it may be of any type. 
         [0047]    Further, although the present invention has been described in the context of a silicon process, it applies to any semiconductor circuit manufacturing process. 
         [0048]    Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.