Abstract:
An RF system comprising of outputs to an electronically scanning antenna for radiating electromagnetic energy; at least one waveform generator; two multiphase phase-locked loops integrated with the waveform generator, the phase locked loops operating to provide multiple shifted phases to a waveform. Optionally, the two multiphase phase-locked loops may each be divided down by a bank of frequency dividers to further increase the number of phase shifts. The phases generated from each multiphase phase-locked loops are selected with multiplexers then mixed together. These upper or lower sidebands are then mixed with the up converted waveform which results in a phase shift for the waveform associated with each antenna element.

Description:
STATEMENT OF GOVERNMENT INTEREST 
     The embodiments herein may be manufactured, used, and/or licensed by or for the United States Government without the payment of royalties thereon. 
    
    
     BACKGROUND OF THE INVENTION 
     Currently, state of the art RF systems that support phased array antennas use a non-integrated phase shifter. This results in power losses, while increasing weight, size, and cost. Advances have been made developing RF systems with integrated phase shifters. However, to support large phased array antennas, new techniques are needed to generate many precise phase shifts. Integrating the phase shifters with the RF transceiver will improve the performance and lower the cost these systems. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to integrated radar architecture, such as a Wide Band Phased Array Antenna, wherein the RF phase shifters are integrated with the RF transmitter/receiver (TR) module. A novel multi-phase voltage controlled oscillator (VCO) generates the phase shifts that are integrated with the radar system. The phase shifts are generated in the narrow band, thus low phase noise, LC-based ring oscillator inside a phase locked loop, then selected through a multiplexer. To generate a larger number of phase shifts with wide bandwidth, the outputs of multiple multi-phase voltage controlled oscillator can be up- or down-converted using balanced image-rejection mixers. The accuracy and sensitivity of these phase shifters should be greater than traditional phase shifters based upon delay lines or ferroelectric devices. In addition, the architecture supports fast beam steering. 
     Although the invention is demonstrated with the application of this technique to radar applications, the sampling and reconstruction technique of the present invention also works with other communication systems, especially ones that employ ultra high-frequency modulation schemes. 
     These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The embodiments herein will be better understood from the following detailed description with reference to the drawings, in which: 
         FIG. 1  is a diagrammatic illustration of the architecture of the preferred embodiment electronically scanning antenna with integrated phase shifter using dual loop multi-phase PLLs. 
         FIG. 2  is a schematic illustration of a multi-phase VCO based dual-loop phase locked loops with image rejection mixers for fine phase generation. 
         FIG. 3  is a multi-phase VCO based dual-loop phase locked loops with dividers and image rejection mixers for fine phase generation. 
         FIG. 4  is a diagrammatic illustration of a serially coupled quadrature VCO (S-QVCO) circuit schematics using NPN for oscillation and NMOS for coupling. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the full scope of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     It will be understood that when an element such as an object, layer, or region is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. For example, when referring first and second photons in a photon pair, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. 
     Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element&#39;s relationship to other elements in the frequency domain as illustrated in the Figures. The exemplary term “lower” or “upper”, can therefore, encompass either “lower” or “upper,” depending on the spectral relationship of the generated signals. Furthermore, the term “outer” may be used to refer to a surface and/or layer that are farthest away from a substrate. 
     Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. Embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     It will also be appreciated by those of skill in the art that references to a structure or feature that is disposed “adjacent” another feature may have portions that overlap or underlie the adjacent feature. 
     A preferred embodiment of the present invention relates to architecture for an electronically scanning antenna (ESA) with integrated phase shifters with high gain, low cost, low power, compact size and reconfigurability. The architecture would be connected to an array of power amplifiers which drive each antenna element to form a phase array antenna. The antenna elements could be an array of patches, dipoles, horns, etc. The invention uses mixed signal processing technology to combine analog and digital components that traditionally are implemented separately. The phase shifters for the antenna are generated using a novel dual phase locked-loop (PLL) architecture with multi-phase voltage controlled oscillators (VCO), mixers and/or frequency dividers. This is implemented using a ring configuration of multiple LC-tuned VCOs. Phases are selected using high-speed multiplexers.  FIG. 1  shows a block diagram of a realization of the proposed antenna system. The number of phase elements and operation frequency in  FIG. 1  is for illustration purpose and can be generalized to any number of phase elements and frequency bands under the current invention. Configurations of the proposed phase array antenna architecture includes, but is not limited to, (I) multi-phase generation using a single loop PLL with a multi-phase VCO; (2) multi-phase generation using frequency dividers; (3) multi-phase generation using dual loop PLLs with multi-phase VCOs and image rejection mixers; (3) multiphase generation using dual loop PLLs with multi-phase VCOs and frequency dividers followed by image rejection mixers. An amplitude weighting can be added to each antenna element output with variable gain amplifiers on or off the chip. 
       FIG. 1  is an architecture of the proposed electronically scanning antenna with integrated phase shifter using dual loop multi-phase phase lock loops  11  and  12  as shown in  FIG. 1 . Each phase lock loop  11 ,  12  comprise a voltage controlled oscillator  13 ,  14 . These multiphase voltage controlled oscillator create a local oscillation (LO) frequency that can be used to perform up- and down-conversions. The phase locked loops  11  and  12  operate to compare the phase and frequency of the divided VCO signal with the reference signal. When the loops are in lock, the VCO output frequency is M times the reference frequency, where M is the loop division ration, and its phase is locked with the reference phase. Also shown in  FIG. 1  is a reference oscillator  21 , which may for example comprise a crystal for generating a stable and low noise tone. The phase lock loops  11 ,  12  may thriller comprise dividers  15 ,  16 , phase frequency detectors  17 ,  18 , and loop filters  19 ,  20  which function in a well known manner. 
     In accordance with the principles of the present invention, the number of phase selections can be increased by inserting dividers  22 ,  23  between the VCO outputs and phase selection multiplexers  24 ,  25 . Frequency dividers  22 ,  23  divide the VCO output frequency to lower frequency and meanwhile generate multiple phases at the divided frequency. For an m-phase VCO followed by dividers with divider ratio of I=2 k , the number of available phases after the dividers can be increased to m*I. The number of phase selections can be further increased by using both frequency dividers and mixers  26 ,  27 . The total available phases can thus be increased as m*n*I*J. Note there may be redundant phases that can be covered by different combinations of m, n, I, J values. Nevertheless, the proposed multi-phase generation scheme can generate phase shifts with very line step size. 
     As shown in  FIG. 1 , the outputs of the voltage controlled oscillators  13 ,  14  are fed into frequency dividers  22  and  23 , which divide signal in frequency by 2 k . The outputs of frequency dividers  22  and  23  enter into phase selection multiplexers  24 ,  25 . As shown in  FIG. 1 , an output of each phase selection multiplexers  24 ,  25  enters mixers  26  and  27 , and the outputs of mixers  26  and  27  are inputted added and subtracted as shown in  FIG. 1  to produce an upper and lower sidebands. The mixers  26  and  27  each produce the difference and sum of the signal inputted therein. Adder  28  and subtractor  29  operate to add and subtract the inputted signals to produce the sidebands as depicted in  FIG. 2 . The sidebands become the series of oscillator input signals  30  as shown in  FIG. 1 . Oscillator inputs are inputted into mixers  33 . A transmission signal T x , which could be produced by a waveform generator such as a direct digital synthesizer (DDS) (not shown) is inputted into a series of low pass filters-variable gain amplifiers  32  to remove the unwanted bands and to adjust its magnitude to the level that the following stage can handle. The output of the low pass filters-variable gain amplifiers  32  is inputted into the mixers  33 , which up-converts the output of the low pass filters-variable gain amplifiers  32  to the desired carrier frequency bands. The mixer output  33  is fed into image filters  34  which filter out the unwanted image bands. Power amplifiers  35  further amplify the transmitting signals and output them into antenna elements  36 . 
     To increase the number of available phase shifts, the outputs of two multi-phase quadrature VCOs (QVCOs) with M and N phase shifts inside the dual PLLs can be mixed to their upper and lower sidebands using image-rejection mixers. The number of phase shifts in the revised circuit shown in  FIG. 2  is thus increased to M*N. Since the dual PLLs are driven by the same reference frequency, their outputs can be synchronized to the same reference with deterministic phase relationship. Mixing the outputs of two PLLs also provides more frequency selectivity with wideband tuning. This circuit can thus be used to support a large phased array antenna. 
       FIG. 3  is a schematic illustration of a multi-phase VCO based dual-loop phase locked loops with dividers and image rejection mixers for fine phase generation. As shown in  FIG. 3 , the number of phase selections can be further increased by inserting dividers between the multi-phase VCO outputs and the phase selection multiplexers. Frequency dividers divide the VCO output frequency to lower frequency and meanwhile multiple phases are available at the divided frequency. For instance, a divided-by-4 divider generates 4 phases (0°, 90°, 180°, 270°) through the division process. For an m-phase VCO followed by dividers with divider ratio of I=2 k , the number of available phases after the dividers can be increased to m*I theoretically. According to  FIG. 3  using multi-phase VCOs and dividers, the total available phases become m*n*I*J. Note there may be redundant phases that can be covered by different combinations of m, n, I, J values. Nevertheless, the proposed multiphase generation scheme can generate phase shifts with very fine step size. 
     Configurations of the proposed phase array antenna architecture includes, but not limited to, (1) multi-phase generation using a single loop PLL with a multi-phase VCO; (2) multi-phase generation using frequency dividers; (3) multi-phase generation using dual loop PLLs with multi-phase VCOs and image rejection mixers; (3) multi-phase generation using dual loop PLLs with multi-phase VCOs and frequency dividers followed by image rejection mixers. 
     The advantages of the proposed phase-array architecture are low loss, low cost, low power, compact size, reconfigurability and most important environmental insensitive, compared to traditional antenna designs. The antenna architecture supports a wide frequency range for narrow band waveforms. The architecture also supports wider bandwidth waveforms such as chirps using intrapulse phase shifting techniques. ESA are typically implemented with discrete phase shifters that are large, expensive, and have several dB of loss. Phase shifters using integrated passive components are subject to large loss, large area and have limited bandwidth and tunability. The phase shifters based upon multi-phase VCOs are implemented on the same chip as other building blocks of the radar TR module such as the direct digital synthesizer, up-converters and power amplifiers, so there are no losses in transmit power due to connector or conductive losses and they are inexpensive. The multi-phase VCO is low power and low phase noise, and produces phase shifts that are locked to the input stable reference frequency and are thus stable against process, voltage and temperature (PVT) variations. The multi-phase can also be generated using an integrated high-frequency VCO followed by programmable frequency dividers. The outputs of the multi-phase VCO are selected with a multiplexer, and then mixed with the waveforms. The large number of phase shifts allows phase discrepancies in the amplifiers and variations in the delay-line lengths to be removed or reduced by digital calibration techniques. 
     Many applications require communicating between fixed nodes. Most antennas for communication systems do not have an ESA capability due to their large size and high cost. An ESA antenna will reduce power requirements and increase channel capacity compared to an omni-directional antenna. An ESA has faster switch times and is more reliable compared to mechanically scanning antennas. This invention will reduce the size, cost, weight, and power requirements for a high performance ESA. It eliminates the need for phase shifters on the ESA. Instead, the phase shifters are integrated onto a chip, which is a much simpler architecture. Third, this architecture supports narrow band waveforms operating over a large frequency range. 
     The problems which the invention solves (or intended application uses) include applications that require communicating between fixed nodes. Most antennas for communication systems do not have an ESA capability due to their large size and high cost. An ESA antenna will reduce power requirements and increase channel capacity compared to an omni-directional antenna. An ESA has faster switch times and is more reliable compared to mechanically scanning antennas. This invention will reduce the size, cost, weight, and power requirements for a high performance ESA. It eliminates the need for phase shifters on the ESA. Instead, the phase shifters are integrated onto a chip, which is a much simpler architecture. Third, this architecture supports narrow band waveforms operating over a large frequency range. 
     A preferred embodiment of the present invention can be used as an antenna for line of sight communication and radar systems. The antenna will improve performance in communication and radar systems by increasing the signal-to-noise ratio (SNR) and reduce interference from other sources. 
     The invention develops new techniques to combine analog and digital processing on a chip for designing an ESA; including a new circuit for a multi-phase VCO. Signal coupling between the VCO cores is critical for multi-phase VCO design. Taking a quadrature VCO (QVCO) as an example, there are various ways to couple the two VCOs and lock their output phases. The most common QVCO topology utilizes the parallel coupling. The parallel QVCO (P-QVCO) delivers quadrature signals with low phase and amplitude errors, yet it consumes large current to bias both the oscillation and coupling transistors. QVCOs can also be serially coupled by placing the coupling transistors in series with the oscillation transistors. By connecting the coupling transistors in series with current reuse topology, the serially coupled QVCO (S-QVCO) provides better isolation between the VCO outputs and its current sources, while the noise from the cascode devices has ignorable contribution. In the P-QVCO and S-QVCO reported so far, the same type of transistors has been used for oscillation and coupling. The new QVCO topology is a serially coupled LC-VCO using high-speed HBTs for oscillation and MOSFETs for coupling. As shown in  FIG. 4 , the oscillation NPN transistors Q 1 , Q 2 , Q 3 , and Q 4  achieve high oscillation frequency and low phase noise, while the NMOS coupling transistors M 1  through M 4  allow more headroom, better isolation and increased tuning range. For the proposed S-QVCO circuit shown in  FIG. 4 , the NPN transistors Q 1  and Q 2  form a cross-coupled negative transconductance LC-tuned VCO and Q 3  and Q 4  form another identical LC-tuned VCO. 
     As shown in  FIG. 4 , the coupling between the two VCOs can be realized using four NMOS transistors M 1 , M 2 , M 3  and M 4 . Thus, the proposed S-QVCO utilizes different types of transistors for oscillation and coupling. Compared to a P-QVCO, the S-QVCO achieves lower current consumption, since the coupling and oscillation transistors share the same bias current. In a P-QVCO, the coupling pair of transistors usually consumes an additional 30-40% of the core oscillator current for reasonable compromise between phase noise and phase error. In an S-QVCO, the coupling transistors are in series with the oscillation transistors. Additional bias currents are not required for biasing the coupling transistors, resulting in considerable power saving. Also, the coupling and oscillation transistors are connected in a cascode manner such that the noise coming from the coupling transistors and current sources are isolated from the LC-tank that is connected to the VCO outputs. The phase noise and phase error are relatively independent of each other in this topology. However, for the same voltage supply, the S-QVCO has less voltage headroom for output swing due to the insertion of the coupling transistors. 
     As is known NPN transistors can achieve higher oscillation frequency due to enhanced unit-power-gain-bandwidth-product, f max , of the devices. On the other hand, MOS transistors have reduced voltage headroom requirements between the drain and source, and thus leads to relaxed bias scheme compared to their BJT counterparts. Since both types of transistors are available in a BiCMOS technology, one can combine the advantages of both types of transistors and achieve better QVCO performance. By using NPN transistors for oscillation, high oscillation frequency can be achieved. By using MOS transistors for coupling, higher output swing can be provided due to the reduced headroom required by the MOS transistors. The larger swing for the VCO output leads to lowered phase noise. In the proposed S-QVCO, the MOS coupling transistors are directly connected to the VCO output nodes, providing a much easier biasing scheme. This coupling scheme can be adopted to form not only a QVCO, but also a multi-phase VCO with multiple LC-based VCO cores. 
     Next, the outputs of multiple multi-phase voltage controlled oscillator were combined using image-rejection mixers as shown in  FIG. 2  to increase the number of phase shifts. This architecture can be generalized to include two or more PLLs operate at the same or different output frequencies. As illustrated in  FIG. 2 , the dual loop PLLs are driven by the same reference source, thus their output frequencies are synchronized with deterministic phase relationship. Without losing the generality, one can assume the first PLL contains m-multiple output phases, while the 2 nd  one has n-multiple output phases. The multi-phase VCOs used in this configuration can be implemented using the circuits similar to the quadrature VCOs (QVCO) discussed above. Thus, the outputs of two PLLs can be mixed using image rejection mixers (IRM). IRMs allow the single-side band mixing without unwanted spurs. The upper sideband mixer provides an output at sin ((ω 1 +ω 2 )t+φ i +φ j ), while the lower sideband mixer provides an output at sin ((ω 1 −ω 2 )t+φ i −φ j ). Both outputs have total m·n phase selections, which not only increases the phases available for phase array application, but also provide more frequency selections since the dual loops can be programmed to different output frequencies. Assuming the first loop can be programmed with M frequencies and the 2 nd  one can be programmed with N frequencies, the resultant upper and lower sideband mixed outputs will have total 2M·N carrier frequencies available for channel programming. The proposed dual loop PLL configuration can be further generalized to include multiple PLLs with multi-phase VCOs to provide fine frequency and phase programming. 
     These circuits allow the removal of the phase shifters from an external device to a chip. In addition, having the phase shifters on a chip allows the antenna to switch beam positions in a clock cycle. 
     The foregoing description of the specific embodiments are intended to reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.