Abstract:
An encoder includes a DC tracking device that generates a flip signal as a function of a statistical measure of portions of a communication signal. The flip signal has a flip state and a nonflip state. A flip device selectively flips the portions based on the flip signal to reduce an average DC value of the communication signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 10/155,777, filed on May 24, 2002 is now a U.S. Pat. No. 6,917,313. This application claims the benefit of the filing date of U.S. provisional applications No. 60/349,895 filed Jan. 16, 2002, and No. 60/352,776 filed Jan. 28, 2002, the content of each of which is herein incorporated by reference in its entirety. 

   TECHNICAL FIELD 
   This invention relates to block coding for communication signals. 
   BACKGROUND 
   Communication systems generally employ modulation coding to convert data bits into symbols that are optimized for transmission through the communication channel. Modulation coding can be used to ensure the presence of sufficient information for timing recovery, gain control, and adaptive equalization. Some communication channels such as perpendicular recording channels may inherently include a DC component in the read back signal. The DC component may complicate and degrade the decoding of the signal requiring tracking of the DC offset. In some cases, the performance of DC offset tracking circuits may degrade by as much as two dB in comparison to the average case. 
   SUMMARY 
   In one aspect, a modulation code is presented that minimizes data patterns that may inhibit the performance of a DC offset tracking loop. An encoder for encoding a communication signal with the modulation code includes a first precoder to precode the communication signal. A signal buffer buffers a first signal associated with the communication signal. A DC tracking block generates a flip signal as a function of a statistical measure of the precoded communication signal. The flip signal has a flip state and a nonflip state. A flip unit, responsive to the flip signal, flips an output of the signal buffer such that an average DC value of the precoded communication signal approaches zero. 
   The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 

   
     DESCRIPTION OF DRAWINGS 
       FIG. 1  is a block diagram of a harddisk assembly. 
       FIG. 2  is a block diagram of an encoder. 
       FIG. 3  is a block diagram of a decoder 
       FIG. 4  is a block diagram of an encoder. 
       FIG. 5  is a block diagram of a DC tracking block. 
       FIG. 6  is a block diagram of an encoder. 
       FIG. 7  is a block diagram of a 30/31 RLL encoder. 
       FIG. 8  is a block diagram of an encoder. 
       FIG. 9  is a block diagram of a DC tracking block. 
       FIG. 10  is a block diagram of a DC tracking block. 
       FIG. 11  is a block diagram of a DC tracking block. 
       FIG. 12  is a flow diagram of an encoding scheme. 
   

   Like reference symbols in the various drawings indicate like elements. 
   DETAILED DESCRIPTION 
     FIG. 1  shows a storage assembly  10  for storing data. The storage assembly  10  includes media  12  to which data may be written and read. Perpendicular recording is preferably employed to write and read data to the media  12  and may be included in any known storage device such as hard drives and optical disks. In a writing operation, a signal processor  14  may apply compression and error correction schemes to an input signal. An RLL encoder  17  converts the processed input signal to a format suitable for storage by the storage unit  12 . A DC-free encoder  16  employs an encoding scheme to control DC offset in the read back signal when perpendicular recording is used for writing the signal to the media  12 . The DC-free code implemented by the encoder  16  may locally limit the average DC level over an interval extending beyond one codeword, one sector, or any portion of the communication over which the code is applied. The code rate may be L/(L+1) and the error propagation due to a DC free decoder  22  is about 1 bit for some aspects. The code may preserve an RLL constraint. A preamp  18  amplifies and writes the encoded signal to the media  12 . A readhead amplifier  20  detects and generates the read back signal by reading data from the media  12 . The readhead amplifier  20  may include a read equalizer and detector for equalizing and detecting the data. The read back signal may be decoded by the DC-free decoder  22  that is suitable for decoding signals that are encoded by the DC-free encoder  16 . An RLL decoder  21  may decompress the decoded signal. The signal processor  14  may apply error correction to the decompressed signal to generate an output signal representing the recovered data. 
     FIG. 2  shows an encoder  30  to apply dc-free modulation code to a communication signal. The communication signal may be any signal that communicates information between two assemblies, although the invention is particularly suitable when applied to communication signals that inherently have a DC component such as signals associated with perpendicular recording of storage devices. The encoder  30  may include a multiplexer  32  to insert a zero bit into the first position of the communication signal to form a codeword c(0:L). A precoder  34  precodes the codeword with 1/(1+D). A buffer  36  stores the precoded output from the precoder  34 . The buffer  36  may be a first-in-first-out (FIFO) buffer. A DC tracking block  38  computes the DC component associated with the first half of the codeword and generates a flip signal based on the computation and the DC component of the second half of the previous codeword. A flip unit  40 , in response to the flip signal, may flip the output of the buffer  36  or output the buffer output unflipped. The DC tracking block  38  may also generate a state signal to cause the precoder  34  to flip state before processing the second half of the codeword. The state signal may be active in response to the flip signal causing the buffer output to be flipped. 
     FIG. 3  shows a DC-free decoder  50  to decode a communication signal that is encoded with DC-free code. The DC-free decoder  50  includes a postcoder  52  to postcode the communication signal. The postcoder  52  preferably postcodes the signal with “1+D”. A demultiplexer  54  strips off the first bit of each codeword that is postcoded to recover the data that was encoded. 
     FIG. 4  shows another DC-free encoder  60  for encoding a communication signal. The communication signal preferably includes Run Length Limited (RLL) encoding although RLL encoding is not required. A multiplexer  62  and buffer  68  both receive the RLL encoded signal. The multiplexer  62  inserts a zero bit into the communication signal to form a codeword. A first precoder  64  precodes the codeword with 1/(1+D). A DC tracking block  66  computes the DC component associated with the first half of the codeword and generates a flip signal based on the computation and the DC-level in the second half of the previous codeword. The buffer  68  stores the received communication signal. The buffer  68  may be a FIFO buffer. A flip unit  70  receives the output of the buffer  68  and, in response to the flip signal, inserts a 1 or 0 into the buffer output to form a codeword. A second precoder  72  precodes the codeword with 1/(1+D). 
     FIG. 5  shows a DC tracking block  80  for computing the DC component of a communication signal. The DC tracking block  80  may compute the DC component over any portion of the communication signal including a half codeword, a full codeword, and a sector. The output of a feed back loop, dc(t), is sampled at time t k =k*(L+1)/2, k=1,2 . . . and the sign, sgn(2*dc(t k )−(L+1)/2)=t k , is stored in a register  84 . The sampling times may correspond to the middle and end of each dc free codeword. An accumulator  82  of a feed back filter may be reset to zero following each sampling time. A decision unit  86  may determine whether to flip the n-th code-word n=1,2,3 . . . after sdc(t 2(n-1)+1 ) becomes available. In that instance the decision to flip is made if sdc(t 2(n-1)+1 )=sdc(t 2(n-1) ); otherwise we do not flip. If the decision to flip is made, then the state signal is generated to flip the precoder state and sdc(t 2(n-1)+1 ) is reset to sdc(t 2(n-1)+1 ). 
     FIG. 6  shows a communication system  90  including a 33/34 DC-free encoder  92  for encoding a communication signal. The input bits of the communication system  90  may first be passed through a 32/33 RLL encoder  94 . Since 32/33 code is typically designed in the interleaved non-return to zero invert (INRZI) domain, the data may then be passed through a 1/(1+D) precoder  96  to convert the codeword into non-return to zero invert (NRZI) domain. Finally, the 33/34 dc-free encoder  92  is used to limit the DC fluctuations of the coded data. The RLL constraint of the code may be (0, 23/15). 
     FIGS. 7 and 8  show another communication system  100  including a 30/31 dc-free encoder  102  to encode a communication signal. The DC limited code implemented in the 30/31 dc-free encoder  102  may be used with 30/31 non-return to zero (NRZ) RLL code. Since 30/31 code is typically constructed in NRZ domain, the construct for the DC limited code shown in  FIGS. 2–6  may not be preferable since the dc-free code shown in  FIGS. 2–6  operates in NRZI. Using the code construct shown in  FIGS. 2–6  with 30/31 NRZ RLL code may cause error propagation. Therefore, the construct shown in  FIGS. 7 and 8  may be advantageous when employed with RLL code designed in the NRZ domain. 
   30/31 RLL code generally is designed in NRZ domain and does not have error propagation across 10-bit ECC byte boundaries. An RLL encoder  104  takes in three 10-bit symbols  106  and encodes the middle one with 10/11 RLL code  107 , where the encoding depends on the last two bits of the first symbol (however these bits are not altered by the encoder). 
   The 30/31 dc-free encoder  102  may include a multiplexer  108  to take in 30 bits, w(0:29), and form a 31-bit codeword c=(0,w) by inserting a 0 at the beginning. A buffer  110  stores a portion of the codeword. A comparator  112  may then compare the dc content of the last 10 bits of the previous codeword with the dc content of the first 11 bits of the current one. If these quantities have the same sign, a flip unit  114  may flip the first 11 bits of the current codeword. Next, c(1 :30) is sent to the 30/31 RLL encoder  104  to be encoded. The 30/31 dc-free code has no error propagation across error correction circuit (ECC) symbol boundaries while preserving the RLL constraint of the 30/31 code. In addition, the DC content in 2 bytes spanning the last byte of previous codeword and the first byte of current codeword is controlled. The DC content of the middle byte may also be controlled by RLL constraints imposed by the 10/11 RLL code. 
     FIG. 9  shows an aspect of a DC tracking block  130  that takes the DC level of a current code-word and compares it with the accumulated DC-level of the n last codewords. 
     FIG. 10  shows another aspect of a DC tracking block  140  that uses a weighted average of the DC level of previous codewords and compares that to the DC level of a current codeword. The weighting may be exponentially decreasing for older codewords. For example, when codeword i is the current codeword, then the weighting for codeword k, k&lt;i, will be a i−k ,for a&lt;1. The extension to individual weights for codewords j codewords prior to the current is straightforward, up to a predetermined number of codewords. 
     FIG. 11  shows another aspect of a DC tracking block  150  that uses a weighted average of bits, rather than codewords. The DC level of the current codewords is compared to a weighted average of previous codesymbols, using weights that may be exponentially decreasing. 
     FIG. 12  shows a process of encoding a communication signal. Beginning at block  170 , a codeword c(0:L) is formed by inserting a zero bit, c=(0,w), into an input w(0:L−1). Continuing at block  172 , the codeword may be precoded with a 1/(1+D) precoder. At block  174 , the precoded codeword may be stored in a buffer. At block  176 , the DC component of a portion of the precoded codeword may be computed. Based on the computed portion, a determination is made whether to flip the codeword and whether all or a portion of the codeword should be flipped, block  178 . Continuing to blocks  180  and  182 , if all or a portion of the codeword is to be flipped, then the precoder state is flipped. Alternatively continuing to block  180 , if the codeword is not flipped, then control passes to block  184  at which the remaining portion of the codeword is processed. 
   A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.