Abstract:
A voltage sharing circuit which allows use of low voltage semiconductor devices to obtain higher output voltages is made up of a series stack of the low voltage devices with diode limiters provided to bias the low voltage devices such that the maximum voltage across any one of the low voltage devices is limited to a predetermined value.

Description:
This is a continuation of Ser. No. 047,791, filed 5/6/87, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to high voltage, high speed circuits and, more particularly, to such circuits in which the required voltage swings exceed the voltage rating of semiconductor devices which can operate at the required high speed. 
     Many applications require high speed semiconductor devices for amplification or switching where the required voltage swings exceed the rating of the available devices. For example, a need arose for a video amplifier to drive the cathode ray tube (CRT) of a high resolution raster scan display. The CRT needed to be driven with a 50 volt signal at 360 MHz (1.2 ns rise and fall time) rate. Frustration with bipolar (conventional) transistors led to the investigation of Gallium Arsenide FET devices which are superior to bipolar devices in some very important areas (high current with low capacitance primarily). FETs, however, are low voltage devices and would not accommodate the required 50 volt swing. 
     Accordingly, it was decided to investigate the sharing of voltage by using multiple FETs in the manner shown in FIG. 1. In this arrangement a plurality of FETs 10, 12 and 14 are connected in series and a conventional resistive voltage divider 16 employed. This arrangement did allow sharing of output voltage such that each device shared 1/n of the output voltage where n equals the number of FETs used. However, the resistive divider caused oscillations. The oscillations were caused by phase shifts that occurred in the feedback of the resistive divider in conjunction with the parasitic capacitances of the devices. A similar resistive divider network as tried with selected bipolar devices but impedence problems arose due to the large base currents. Also the Miller effect became a problem when using a resistive divider network. 
     Accordingly, it is an object of this invention to provide a high speed, high voltage circuit. 
     It is another object of this invention to provide a high speed, high voltage circuit using low voltage devices. 
     SUMMARY OF THE INVENTION 
     Briefly, in one embodiment of the invention, a voltage sharing circuit is provided which allows the use of low voltage FETs to obtain high voltage outputs. A stack of FET devices is connected in series with the drain electrode of one FET connected to the source electrode of the next FET in the stack. An input signal is applied to the gate electrode of the first FET at one end of the stack and the output signal is derived at the drain electrode at the nth FET at the other end of the stack. 
     Diodes are connected between reference voltages and the gate electrodes of each of the FETs except for the first or input FET. The reference voltages are selected in order to limit the maximum voltage which can be developed across all of the FETs except for the nth FET. The gate bias is provided by a resistor from drain to gate and is, then, limited 
     In order to limit the maximum power consumed by the FETs, the reference voltages can be tapered so that the lower the FET is in the stack the less the maximum voltage which is permitted to develop across the FET. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a schematic of a voltage sharing circuit employing a resistive divider network; 
     FIG. 2 is a schematic of a voltage sharing circuit employing diode limiters in accordance with the principles of this invention; 
     FIG. 3 is a series of waveforms illustrating the signals taken at various points of the schematic of FIG. 2; 
     FIG. 4 is a schematic of a voltage sharing circuit like that of FIG. 2 with the addition of a common cascode device. 
     FIG. 5 is a schematic diagram of another voltage sharing circuit employing diode limiters in accordance with the principles of this invention; and 
     FIG. 6 is a schematic diagram of yet another voltage sharing circuit employing diode limiters in accordance with the principles of this invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring now to FIG. 2 of the drawings there is illustrated a voltage sharing amplifier 20 configured in accordance with the principles of this invention. The amplifier includes a grounded source FET 22 having a second FET 24 and a third FET 26 connected in series therewith. The signal to be amplified is applied to the gate electrode 28 of FET 22 and the output from the amplifier is taken at the drain 30 of FET 26. The supply voltage V S  for the circuit is connected to drain 30 via a resistor 32. 
     Reference voltages V 1  and V 2  are coupled to the gates 34 and 36 of FETs 24 and 26, respectively, through diodes 38 and 40. A resistor 42 is connected between gate 34 and the drain 44 of FET 24 and another resistor 46 is connected between gate 36 and drain 30 of FET 26. Although three FETs are shown, this is exemplary only. The number of devices required depends upon the required voltage swing and the rating of the devices. Thus, the circuit may employ only two devices or more than two devices. 
     The individual FET devices of FIG. 2 are protected from excessive voltages while the output voltage (V 0 ) is beyond the rating of any one of the devices. Thus, large voltage swings are achieved with low voltage devices. The output voltage may exceed the ratings of any one of the devices by many times. 
     The reference voltage V 1  is equal to the magnitude of V DSmax  (the maximum drain to source voltage less the magnitude of V p  (pinch off voltage) or |V|. V 2  is equal to V 1  +|V DSmax  |. If additional devices were stacked then V 3  would be made equal to V 2  +|V DSmax  |, etc.. 
     When the output voltage V 0  is nominally less than V 1  +|V p  | all of the output is across FET 22 and FETs 24 and 26 act as short circuits. When V 0  nominally increases beyond V 1  +|V p  | but less than V 2  +|V p  | then a portion of the output voltage is across FET 24 and FET 26 acts as a short circuit. When V 0  nominally exceeds V 2  +|V p  | then the remainder of the output voltage is across FET 26 as well, that is, all of the FET devices share the output voltage. This occurs because the gate voltage for FET 24 can never exceed V 1  (except for diode drop) and the gate voltage for FET 26 can never exceed V 2  (except for diode drop). The pinch off voltage is a worst case value. In most designs the reference voltage will be selected so that, for example, the second FET in the stack will start sharing voltage before it reaches V 1  +|V p  |. Note magnitudes of V p  are used since in the example shown depletion mode, n-channel JFETs are used and, therefore, V is negative. Of course, when p-channel and n-channel enhancement mode devices are used the signs shown above would be incorrect. 
     FIG. 3 illustrates the signals taken at various points in FIG. 2 and clearly shows the result of stacking FETs to obtain large voltage swings with low voltage devices. Waveforms A, B, C and D are taken at points A, B, C and D in FIG. 2. 
     Stacked FET devices using a diode divider are very stable. The circuit has two states or modes of operation. When the voltage across the device is above the reference voltage, the diode will limit the gate voltage at the nominal reference voltage. Thus, in this mode the gate voltage is fixed and the circuit is a conventional cascode which is well known to be stable and desirable at high speeds. In the mode where the voltage drops below the reference voltage the diode is reverse biased and essentially does not exist. Therefore, the device is simply biased on by the resistor connecting the drain to the gate (resistors 42 and 46) and, thus, very stable in this state because the particular device is not acting as a linear element. 
     Although this embodiment is illustrated using FET devices, bipolar devices could be used instead. In fact the principles are applicable to any active electronic device including vacuum tubes. Preferably the diodes are Schottky diodes because of their low capacitance and speed characteristics. While separate reference voltages are indicated, preferably the reference voltages are derived from a single source and divided with zener diodes which precisely define the reference voltage values. 
     One drawback to this arrangement is that the lower devices in the stack bear more of the voltage load (statistically) because they would be limited at full voltage unless the output dropped quite low. As the current fluctuated up and down with the signal then, the lower devices in the stack would dissipate more power because the lower the device in the stack, the more often it would be at full voltage. One solution to this problem is to &#34;taper&#34; the voltages, giving the lower devices in the stack a lower voltage stress to equalize power dissipation. 
     Therefore, for example, in FIG. 2, reference voltage V 1  would be less than |V DSmax  |-|V p  | in order to reduce the power in FET 22. Likewise V 2  may be made less than V 1  +|V DSmax  |. Note, however, that additional FETs may be required in the stack to accommodate the full output voltage when using tapered reference voltages. 
     In some instances where a single device can tolerate the required output voltage swing, it is still desirable to stack multiple devices for power sharing. This is preferred to paralleling in some cases. 
     FIG. 4 illustrates another embodiment of the invention. It is like the embodiment of FIG. 2 with the addition of another FET 50 as a cascode. This optional cascode is added to alleviate Miller effect on the input. When the output voltage is nominally less than V 1  +|V p  |, the drain of FET 22 does not have its voltage fixed and, therefore, the Miller effect can be a problem in that range. The cure for this is to insert a cascode above it. Additional cascodes are not needed for the upper devices since they become cascodes inherently above some level and are short circuits otherwise. 
     In FIG. 5 of the drawings there is illustrates a voltage sharing amplifier 52 configured in accordance with the principles of this invention. FETs 22, 24 and 26 of FIG. 2 are replaced in FIG. 5 with bipolar devices 54, 56 and 58, each including a respective base electrode 60, 62 or 64. Bipolar device 58 includes collector electrode 66. Bipolar device 56 includes collector electrode 68. 
     In FIG. 6 of the drawings there is illustrates a voltage sharing amplifier 70 configured in accordance with the principles of this invention. FETs 22, 24 and 26 of FIG. 2 are replaced in FIG. 6 with vacuum tubes 72, 74 and 76, each including a respective grid electrode 78, 80 or 82. Vacuum tube 76 includes plate electrode 84. Vacuum tube 74 includes plate electrode 86. 
     Although the circuit describing the invention is an amplifier, the principles of the invention are applicable to other types of circuitry where the output voltage exceeds the individual ratings of the semiconductors, such as switching circuits. Thus, it is to be understood that the embodiments described are illustrative only and that many variations and modifications can be made without departing from the principles of the invention herein disclosed and defined by the appended claims.