Abstract:
A ringing generator testing arrangement for a digital telephone network is shown comprising a zero crossing detector connected to the ring lead of a line circuit under test. The zero crossing detector gates a clock signal into a counter circuit during the negative to positive transition of the ringing generator signal positive half cycle. The counter circuit advances until the next positive to negative transition of the ringing generator signal. At this time, the zero crossing detector cuts off the clock signal and the counter circuit transmits to a central control complex a count representing a measured interval of the ringing generator positive half cycle.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates in general to ringing generator testing arrangements and more particularly to an arrangement for determining the presence and frequency of ringing generator in a digital telephone network. 
     Line ringing tests verify the performance of line circuits, ringing control circuitry as well as the performance of the telephone networks ringing plant. 
     Typically these tests are performed by accessing the line circuits under test and configuring the line circuits accessed for ringing. A ringing generator signal is then applied to the line, sensed and measured under closed loop conditions verifying the presence of ringing signal as well as its frequency. 
     In digital telephone networks these testing procedures function under program control of a central control complex. The central control complex via an administrative input/output interface can configure the line circuits to be tested and apply the ringing generator signal. 
     In the past the performance of the ringing circuitry and ringing plant were measured by analog devices monitored by telephone network personnel. In program controlled testing systems however, it becomes advantageous to read the results of such tests directly into the central control complex. The program thus would interpret and determine the results of the test. In order to accomplish this end, a means of converting the analog frequency and waveform voltages of the ringing generator into a digital value is normally required in order to input these values into the central control complex. 
     It is therefore the object of the present invention to provide an arrangement under program control for verifying the presence and frequency of ringing generator in line circuits under test and to sense and report the results of these tests to a central control complex. 
     SUMMARY OF THE INVENTION 
     The present invention is an arrangement used to verify the presence and frequency of a ringing generator used in a digital telephone system. The arrangement of the present invention is connected to a line circuit having a tip and ring lead and a source of alternating ringing generator signals under control of a central control complex. 
     The present invention comprises a zero crossing detector means connected to the ring lead of a line circuit. The zero crossing detector means produces a first output signal responsive to the negative to positive transition of the ringing generator signal and a second output signal responsive to the first positive to negative transition of the ringing generator signal. A clock signal generating means develops and produces a continuous output of clock signals which are applied to counting means. The counting means are further connected to the zero crossing detector means and responsive to the zero crossing detector means first output signal counts the clock signals for a period until the zero crossing detector outputs the second output signal. 
     At this time the counting means transmits to the central control complex a count representing the measured interval of the positive half cycle of the ringing generator signal. Through a counting algorithm, the frequency of the generator is calculated using the measured interval of the positive half cycle. 
     The arrangement further includes a ring detector means connected to the ring lead of the line circuit and arranged to produce an output signal to the central control complex responsive to the presence of the ringing generator signal. The ring detector means is used to verify that ringing signal generator is present on the line and also in combination with the zero crossing detector second output signal, to develop a reset signal resetting the counting means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram showing the arrangement of the present invention. 
     FIG. 2 is a detailed schematic illustrating the ring detector and zero crossing detector of the present invention. 
     FIG. 3 is a detailed schematic illustrating the frequency counter of the present invention. 
     FIG. 4A is a timing diagram showing the relative timing relationships between the ringing generator input signal and the output signals developed by the ring detector and zero crossing detector. 
     FIG. 4B is a representation of the AC ringing generator input showing the measured interval which the arrangement of the present invention uses to measure the frequency of the ringing generator signal. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Turning now to FIG. 1, a block diagram of the elements of the present invention is illustrated. These elements comprise a ring detector 10, a zero crossing detector 20 and a frequency counter 50. A ringing signal is applied to detector 10 and detector 20 via a line test bus 60. The test bus includes tip (T) and ring (R) leads connected on one side to the line circuit under test and on the opposite side via leads TL and RL to other test devices. Ring detector 10 and zero crossing detector 20 are connected to the test bus 60 via relay R. Relay RV allows the present invention to test line side selections, i.e. multi-party lines using divided ringing which require that the ringing generator be applied to either the ring or the tip conductor depending upon the party to be alerted. 
     Ring detector 10 outputs a ring generator sense signal and frequency counter 50 a ring frequency measurement which under program control, is output to a central control complex. 
     Turning now to FIG. 2, a detailed schematic of ring detector 10 and zero crossing detector 20 is illustrated. Ring detector 10 is comprised of resistors R1 and R2, diode bridge 11, diode CR5 and optical coupler OC1. The balance of the circuit is comprised of capacitor C1, resistors R3 and R4, diode CR6 and line driver 16. 
     The zero crossing detector 20 is comprised of optical couplers OC2 and OC3. NAND gates 21 and 22 which are configured as a flip-flop, NAND gate 25 and a NOR gate 28. Resistors R6, R7 and R8 are pull-up resistors. 
     With additional reference to FIG. 4A a detailed description of the operation of ring detector 10 and zero crossing detector 20 will now be explained in detail. Ring generator voltage is input via relay R when made. Relay R can be made and broken under program control of the central control complex. The voltage received is periodically high enough so that the drop across resistors R2 exceeds drops across two of the bridge diodes in diode bridge 11, diode CR5 and the diode section of optical coupler OC1. At this time OC1 conducts turning on the photo Darlington pair and allowing current to flow through the network comprised of capacitors C1, resistors R4, R3 and diode CR6. This signal produced by the network is integrated by capacitor C1 developing signal -GP (-GP). The negative cycles of signal -GP occur at the most positive and most negative portion of the ring generator sine wave. Signal -GP is output via a driver 16 to the central control complex indicating that ringing generator is present. Normally this indicator should follow the ring cycle of two seconds on and four seconds off. 
     Zero crossing of the ring generator input is determined by optical couplers OC2 and OC3. Optical coupler OC2 develops signal -PZC (-PZC) during the positive half cycle of the ringing generator input. Optical coupler OC3 develops signal -NZC (-NZC) during the negative half cycle of the ring generator input voltage. With reference to FIG. 4B, at the beginning of the positive voltage half cycle, -PZC is input into NAND gate 21 which sets and develops output signal PZC. Signal PZC is active until reset by signal -NZC applied to NAND gate 22 at the beginning of the negative half cycle. Therefore, signal PZC is active for the positive half cycle of the ring generator input. 
     The signal output of flip-flop gate 22 is applied to gate 25 which develops a latch enable signal (LEN). As the negative half cycle advances, signal -GP developed by the ring detector optical coupler OC1 is logically combined with -NZC at NOR gate 28 developing a reset signal (CTR R). Signals PZC, LEN and CTR R are output from the zero crossing detector to frequency counter 50. 
     Turning now to FIG. 3, a detailed schematic of frequency counter 50 is illustrated. Frequency counter 50 is comprised of a 100 kHz clock 51 having a crystal 54 and a resistive network 56 providing a stable frequency source for the clock. Clock signals output by clock 51 are applied to an input of a NAND gate 52 whose output is connected to a 14-bit binary counter 53. The outputs of counter 53 are connected to two 4-bit latches 58a and 58b via drivers 55a-55h. The output of latches 58a and 58b output an 8-bit data word representative of the measured interval of the ring generator input to the central control complex. 
     During the negative half cycle of the ring generator input signals -GP and -NZC via NOR gate 28 produce reset signal CTR R which is applied to the clear input of counter 53. At this time the counter is reset in preparation for another measurement on the next positive half cycle. After the zero crossing of the positive half cycle, signal PZC is output from the flip-flop of FIG. 2, gating the 100 kHz clock via gate 52 to the counter 53. The counter advances until the beginning of the negative half cycle where -NZC resets the flip-flop opening the clock input. Thus during the measured interval the contents of the counter represent the time interval of a half cycle of the received ring generator waveform. At this time the outputs of counter 53 apply the data gathered during the measured interval to latches 58a and 58b via drivers 55a and 55h. When -NZC reset the flip-flop the output signal from gate 22 was combined with a positive logic signal at the input of gate 25 developing a latch enable signal (LEN). LEN is used to capture into latches 58a and 58b the output of counter 53 at the end of the measured interval. At this time latch 58a outputs B0-B3 and latch 58b outputs B4-B7 contain the measured interval of the ring generator positive half cycle. 
     A logic 1 contained in B0 would represent an elapsed time of 0.16 milliseconds. The 0.16 millisecond time doubles for each successive bit until B7 which will indicate an interval of 20.48 milliseconds. Therefore, the half cycle measurement is obtained by summing the weighted values for each bit that is at a logic 1. The translation of measured interval to ring frequency would be accomplished in the central control complex using an algorithm to translate the time measurement to a frequency output. For example, the expected value of a measured interval of 30 milliseconds could indicate a ringer frequency of 16.67 hertz or a measured interval of 7.5 milliseconds would indicate a ringer frequency of 66.67 hertz. 
     At the most negative point of the ring generator waveform, -GP and -NZC are logically combined by NOR gate 28 to form the reset signal CTR R which clears counter 53 for the next measurement before the next positive half cycle. 
     The present invention has been described with reference to a specific embodiment thereof for the purposes of illustrating the manner in which the invention may be used to advantage. It will be appreciated by those skilled in the art that the invention is not limited thereto. Accordingly, any and all modifications, variations or equivalent arrangements which may occur to those skilled in the art should be considered to be within the scope of the invention.