Abstract:
A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to semiconductor fabrication and more specifically to formation of devices having different channel lengths/critical dimension (CD) bias.  
         BACKGROUND OF THE INVENTION  
         [0002]    Applying different logic operations in different patterns is the current approach for system-on-chip (SOC) applications to achieve different poly critical dimension (CD) biases between after-etch inspection (AEI) CD and drawing CD (the layout dimension) within the wafer which are required for multiple devices to achieve both high performance and low leakage devices within the wafer.  
           [0003]    U.S. Pat. No. 6,191,044 B1 to Yu et al. describes hard mask trimming.  
           [0004]    U.S. Pat. No. 6,013,570 to Yu et al. describes a gate trim process.  
           [0005]    U.S. Pat. No. 5,834,817 to Satoh et al. describes another gate trim process.  
           [0006]    U.S. Pat. No. 6,110,785 to Spikes, Jr. et al. describes a gate trim etch process.  
         SUMMARY OF THE INVENTION  
         [0007]    Accordingly, it is an object of one or more embodiments of the present invention to provide a method of achieving different critical dimension (CD) bias within a wafer for SOC application.  
           [0008]    Other objects will appear hereinafter.  
           [0009]    It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:  
         [0011]    FIGS.  1  to  9  schematically illustrates a preferred embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0012]    Initial Structure—FIG. 1  
         [0013]    As shown in FIG. 1, structure  10  includes two or more active areas  12 ,  14  separated by isolation structures  16 ,  18 ,  20 .  
         [0014]    Structure  10  is preferably a silicon or germanium substrate, is more preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate.  
         [0015]    Isolation structures  16 ,  18 ,  20  are preferably shallow trench isolation (STI) structures or local-oxidation-of-silicon (LOCOS) and are more preferably STI structures, as will be used hereafter for purposes of illustration, comprised of silicon oxide.  
         [0016]    Gate dielectric portions  22 ,  24  are formed over structure  10  within each of the two or more active areas  12 ,  14 . Gate dielectric portions  22 ,  24  each have a thickness of preferably from about 3 to 300 Å and are preferably comprised of silicon oxide or germanium oxide and are more preferably silicon oxide as will be used for illustrative purposes hereafter.  
         [0017]    A gate electrode layer  26  is then formed over the gate oxide portions  22 ,  24  and the STI&#39;s  16 ,  18 ,  20  to a thickness of preferably from about 500 to 3000 Å. Gate electrode layer  26  is preferably comprised of polysilicon (poly).  
         [0018]    A hard mask layer  28  is then formed over the gate electrode layer  26  to a thickness of preferably from about 50 to 1000 Å. Hard mask layer  28  is preferably comprised of silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON) or silicon oxide (SiO 2 ).  
         [0019]    Formation of Patterned First Masking Layer Portions  27 ,  29 —FIG. 2  
         [0020]    As shown in FIG. 2, respective patterned first masking layer portions  27 ,  29  are formed over the hard mask layer  28  within each respective two or more active areas  12 ,  14  roughly between the STI&#39;s  16 ,  18 ,  20  separating the two or more active areas  12 ,  14 .  
         [0021]    As shown in the FIG. 2, patterned first masking layer portions  27 ,  29  are preferably comprised of photoresist (PR).  
         [0022]    Patterning of Hard Mask Layer  28 —FIG. 3  
         [0023]    As shown in FIG. 3, hard mask layer  28  is patterned using the overlying patterned PR layer portions  27 ,  29  as masks to form respective hard mask layer portions  30 ,  32  overlying the gate electrode layer  26  within each respective two or more active areas  12 ,  14 .  
         [0024]    Each hard mask layer portion  30 ,  32  have a width of preferably from about 300 to 100,000 Å.  
         [0025]    Removal of Patterned First PR Portions  27 ,  29 —FIG. 4  
         [0026]    As shown in FIG. 4, the patterned first PR portions  27 ,  29  are removed from over the hard mask layer portion  30 ,  32  and the structure is cleaned as necessary.  
         [0027]    Formation of Patterned Second Masking Layer Portion  33 —FIG. 5  
         [0028]    As shown in FIG. 5, a patterned second masking layer portion  33  is formed at least over active area  14  containing the at least one hard mask layer portion  32  determined to eventually form a gate electrode with the wider/widest channel length(s), leaving exposed the hard mask layer portion  30  determined to eventually form a gate electrode with the smaller/smallest channel length.  
         [0029]    It is noted that if three or more respective hard mask layer portions  30 ,  32  are formed within three or more respective active areas  12 ,  14 , then one or more second masking layer portion(s)  33  is/are formed over at least the active areas containing the respective hard mask layer portions determined to not have the smallest channel length.  
         [0030]    Trimming of Exposed Hard Mask Layer Portion  30 —FIG. 6  
         [0031]    As shown in FIG. 6, the exposed hard mask layer portion  30  determined to eventually form a gate electrode having the smallest channel length is subjected to a trimming process which erodes the exposed hard mask layer portion  30  to a first trimmed hard mask layer portion  30 ′ having at least a narrower width than the hard mask layer portion  30 . The trimming process is preferably the same process used to pattern the hard mask layer  28  to form the hard mask layer portions  30 ,  32 .  
         [0032]    Removal of the Patterned Second Masking Layer Portion  33 —FIG. 7  
         [0033]    As shown in FIG. 7, the patterned second masking layer portion  33  is removed and the structure is cleaned as necessary.  
         [0034]    It is noted that if there are three or more active areas  13 ,  14  with respective hard mask layer portions  30 ,  32 , and it is desired to have three or more different CD bias devices/channel lengths, a patterned third masking layer portion(s) is/are formed over at least the active area within which the larger CD bias devices/channel lengths are to be formed leaving the active areas having the smaller CD bias devices/channel lengths exposed so that an additional trimming process is performed on the exposed first trimmed hard mask layer portion  30 ′ and the now exposed hard mask layer portion to form a first and second trimmed hard mask layer portion  30 ″ having even a smaller width and a second trimmed hard mask layer portion have a width smaller than the patterned third masking layer portion(s) covered hard mask layer portion(s). The patterned third masking layer portion(s) is/are removed and this may be repeated again using a patterned fourth masking layer portion(s), a patterned fifth masking layer portion(s), etc. until the desired range of CD bias devices/channel lengths may be subsequently formed.  
         [0035]    As one skilled in the art would recognize, first trimming mask and second, third, etc. trimming mask(s) covering different active regions to achieve different etch biases is allowed within the teachings of the present invention. That is, etch biases mean forming respective hard mask layer portions ( 30 ,  32 , e.g.) having differing widths within respective different active regions to thus form corresponding gate electrode layer portions ( 34 ,  36 , e.g.) as described below.  
         [0036]    Patterning of Gate Electrode Layer  26 —FIG. 8  
         [0037]    As shown in FIG. 8, the gate electrode layer  26  is patterned using the first trimmed hard mask layer portion  30 ′ (or any first and second trimmed hard mask layer portion  30 ″, second trimmed hard mask layer portion, etc.) and the (untrimmed, or least trimmed) hard mask layer portion  32  to form a first gate electrode layer portion  34  having the smallest width (that may be partially trimmed many times) (or a first gate electrode layer portion  32  having the smallest width, second gate electrode layer portion having a width wider than the smallest width and narrower than the largest width, etc.) and a last gate electrode layer portion  36  generally having the largest width.  
         [0038]    The width of the smallest width trimmed hard mask layer portion  34  may be as narrow as from about 100 to 95,000 Å.  
         [0039]    Removal of the First Trimmed Hard Mask Layer Portion  30 ′ (and any Intermediate Trimmed Hard Mask Layer Portion(s)) and the Untrimmed Hard Mask Layer Portion  32 —FIG. 9  
         [0040]    As shown in FIG. 9, the first trimmed hard mask layer portion  30 ′ (or any first and second trimmed hard mask layer portion  30 ″, second trimmed hard mask layer portion, etc.) and the (untrimmed, or the least trimmed) hard mask layer portion  32  are removed from over the respective first gate electrode layer portion  34  having the smallest width (or a first gate electrode layer portion  32  having the smallest width, second gate electrode layer portion having a width wider than the smallest width and narrower than the largest width, etc.) and a last gate electrode layer portion  36  generally having the largest width and the structure is cleaned as necessary.  
         [0041]    Further processing may then proceed to form semiconductor devices using the respective first gate electrode layer portion  34  having the smallest width (or a first gate electrode layer portion  32  having the smallest width, second gate electrode layer portion having a width wider than the smallest width and narrower than the largest width, etc.) and a last gate electrode layer portion  36  generally having the largest width.  
         [0042]    Advantages of the Present Invention  
         [0043]    The advantages of one or more embodiments of the present invention include:  
         [0044]    1. different poly CD bias within a wafer for SOC application is achieved without any logic operation;  
         [0045]    2. different poly CD bias within a wafer for SOC application is achieved without a relaxation of the design rule;  
         [0046]    3. a high performance device a and low leakage device exist simultaneously within a wafer for SOC application without any logic operation and without relaxing the design rule is achieved; and  
         [0047]    4. minimum polysilicon trimming in memory cell array is used to achieve minimum cell size without endcap window issue.  
         [0048]    Advantages 2 and 4 above are due to wider poly (like low leakage and SRAM cell) having separate etch bias with the smallest poly (core device). Thus, the least trimming bias is allowed in the wider poly device.  
         [0049]    While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.