Abstract:
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

Description:
PRIORITY APPLICATION 
   This application is a divisional of U.S. patent application Ser. No. 11/491,461 (filed 21 Jul. 2006), which is a divisional of U.S. patent application Ser. No. 11/036,163 (filed 14 Jan. 2005). The entire disclosure of both of these priority applications is hereby incorporated by reference herein. 

   FIELD OF THE INVENTION 
   The present invention relates to the field of integrated circuit fabrication, specifically to the formation of memory arrays. 
   DESCRIPTION OF THE RELATED ART 
   Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of data. Conventional semiconductor electronic storage devices, such as Dynamic Random Access Memory (DRAM), typically incorporate capacitor and transistor structures in which the capacitors temporarily store data based on the charged state of the capacitor structure. In general, this type of semiconductor Random Access Memory (RAM) often requires densely packed capacitor structures that are easily accessible for electrical interconnection. 
   The capacitor and transistor structures are generally known as memory cells. The memory cells are arranged into memory arrays. The memory cells are addressed via a word line and a digit line, one of which addresses a “column” of memory cells while the other addresses a “row” of memory cells. 
   In many DRAM devices, the digit line is buried below the upper level of the substrate. One example of this is burying the digit line within the isolation trench. However, this can often involve several complicated steps. Furthermore, as integrated circuit designs become more dense, it becomes more difficult to isolate a buried digit line within its trench and to make contact with individual transistors in the array. 
   Thus, simpler and more reliable methods for forming, isolating and contacting buried digit lines are desired. 
   SUMMARY OF THE INVENTION 
   In accordance with one aspect of the invention, a method is provided for forming an integrated circuit. The method includes forming an elongated trench between a first transistor active region and a second transistor active region. An isolation element is deposited asymmetrically within the trench in contact with the second transistor active region. A bit line structure is deposited within the trench in direct contact with the active region and the isolation element, wherein the isolation element is positioned between the bit line structure and the second transistor active region. 
   In accordance with another aspect of the invention, a method is provided for forming a buried digit line. The method includes forming a trench in a substrate with a base and side walls. A first spacer is formed along a first trench side wall and a second spacer along a second trench side wall. The trench is filled with a first sacrificial material after forming the first spacer and the second spacer. The second spacer is removed to expose a portion of a base of the trench after filling the trench with the first sacrificial material. The exposed first portion of the base of the trench is etched to form an isolation window having a first depth. A first insulating liner is deposited along the first trench wall and the second insulating liner is deposited along the second trench side wall into the isolation window. A recess is formed in the substrate by etching a second exposed portion of the base of the trench between the first liner and the second liner to a second depth. A digit line is then formed in the recess. 
   In accordance with another aspect of the invention, a method of forming a memory array is provided. The method includes forming an elongated trench having first and second sides in a substrate. An asymmetric isolation window is formed in the trench using sacrificial spacers, where the asymmetric isolation window is formed along the second side of the trench. Insulating spacers are deposited along the sides of the trench and fill the insulation window. A digit line recess is formed between the insulating spacers in the substrate beneath the trench. A digit line is formed in the digit line recess. The digit line electrically connects to a first memory cell on the first side and is electrically isolated by the asymmetric isolation window from a second memory cell on the second side. 
   In accordance with another aspect of the invention, a computer memory structure is provided. The structure includes a plurality of active regions in a substrate, where the active regions are arranged in a plurality of columns. A trench in the substrate separates a first column from a second column. A digit line in the trench directly contacts the first column. A filled asymmetric isolation window within the trench separates the digit line from the second column. 
   In accordance with another aspect of the invention, an integrated circuit is provided, including a first elongated semiconductor ridge and a second elongated semiconductor ridge parallel to and spaced from the first ridge. The first and second ridges separated by a trench. Each of the first and second ridges serve as active areas for a plurality of transistors along the lengths of the ridges. The trench includes a conductive line in continuous electrical contact with the first ridge. An insulating element within the trench separates the conductive line from the second ridge. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other aspects of the invention will be better understood from the detailed description below and the appended drawings, which are meant to illustrate and not to limit the invention, and in which: 
       FIG. 1  is a schematic, cross-sectional side view of a substrate with trenches with a thin “pad oxide” grown over the surface of the substrate, a thicker layer of silicon nitride (Si 3 N 4 ), and a photoresist mask in accordance with a starting point for preferred embodiments of the present invention. 
       FIG. 2  is a schematic, cross-sectional side view of the substrate of  FIG. 1  after spacers have been formed and the trench has been filled with a sacrificial material. 
       FIG. 3  is a schematic, cross-sectional side view of the substrate of  FIG. 2  after one of the spacers has been removed and an etch into the substrate has been performed. 
       FIG. 4  is a schematic, cross-sectional side view of the substrate of  FIG. 3  with the remaining spacer and sacrificial material removed. 
       FIG. 5  is a schematic, cross-sectional side view of the substrate of  FIG. 4  after depositing insulating liners. 
       FIG. 6  is a schematic, cross-sectional side view of the substrate of  FIG. 5  after etching the substrate using the liners as a mask. 
       FIG. 7  is a schematic, cross-sectional side view of the substrate of  FIG. 6  after depositing an insulating material in the trench. 
       FIG. 8  is a schematic, cross-sectional side view of the substrate of  FIG. 7  after depositing and recessing a digit line material in the trench. 
       FIG. 9  is a schematic, cross-sectional side view of the substrate of  FIG. 8  after depositing an insulating material in the trench and etching back the insulating material. 
       FIG. 10  is a schematic, cross-sectional side view of the substrate of  FIG. 9  after forming transistor pillars and cell capacitors. 
       FIG. 11  is a schematic, cross-sectional side view of an array of memory cells formed in accordance with another embodiment of the invention. 
       FIG. 12  is a schematic, cross-sectional plan view of the array of memory cells taken along lines  12 - 12  of  FIG. 10  or  11 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   In a preferred embodiment, a buried digit line is formed in a trench between rows of transistors. After forming trenches, spacers are formed within each trench. A sacrificial material is deposited within the trenches. One of the spacers is then removed from the trench, and the substrate below the removed spacer is etched to form an isolation window. After the isolation window is formed, the spacers and sacrificial material are removed. An insulating liner is formed conformally over the memory array. A spacer etch is then performed to preferentially etch horizontal surfaces. This exposes a portion of the trench. The exposed bottom of the trench is preferably etched at this stage to provide a recess in the substrate. If the insulating liner reaches the bottom of this recess, then the digit line can be deposited directly into the recess. Otherwise, an insulating layer is preferably deposited into the trench before forming the digit line. An insulator is formed within the trench, and then etched back. Transistors and capacitors are completed at positions between and above the trenches to form the memory cell. 
   Referring now to an embodiment illustrated in  FIG. 1 , a semiconductor substrate  10 , such as bulk silicon, like a silicon wafer, is provided. A cap layer  15  may be formed over the substrate  10  in order to protect the substrate  10  from damage that could be caused during processing. The cap layer is preferably silicon nitride, but other insulating materials can also be used. Preferably, the trenches are then masked using photoresist  20  although other masking techniques can also be used. 
   In a first step, trenches are formed in the substrate  10 . The trench can be formed in a variety of methods. Preferably, an anisotropic dry etch process, such as a reactive ion etch process, is used to etch the trenches. In a preferred embodiment the trench has a depth of between about 1500 Å and 6000 Å, more preferably between about 2000 Å and 3000 Å. The width of the trenches is preferably between about 100 {acute over (Å)} and 2000 {acute over (Å)}, more preferably between about 350 {acute over (Å)} (using a 0.04 μm process) and 1000 {acute over (Å)} (using a 0.100 μm process). An oxidation of the walls and base of the trench followed by an oxide etch step may also be performed in order to smooth trench walls. Skilled practitioners will appreciate that trenches can be formed in a variety of ways. 
   As seen in  FIG. 2 , after the trench is formed, a first set of spacers  22  is formed on the walls of the trench. Preferably, a conformal liner of spacer material is deposited over the array. The spacer material is preferably silicon dioxide, but can also be other materials which can be selectively etched relative to the surrounding materials. A spacer etch, which preferentially removes horizontal layers relative to vertical layers, is then performed to expose a portion of the base of the trench and leaving the spacers  22  along the sidewalls of the trench. The spacers  22  preferably have a thickness of between about 50 Å and 600 Å, more preferably between about 100 Å and 300 Å, representing about ⅓ of the trench width. 
   After forming the spacers  22 , a sacrificial material  25  is deposited over the array, filling the trenches. In a preferred embodiment, the sacrificial material  25  is polysilicon, but the sacrificial material can be any material that can be selectively etched to the material of the spacer  22 . 
   Referring now to  FIG. 3 , one of the spacers  22  along the sidewalls of the trench is removed. In a preferred embodiment, a photoresist mask  30  is used during an etch of the sacrificial material  25  and one of the spacers  22 . However, skilled practitioners will appreciate other masking techniques can be used. The exposed sacrificial material  25  is etched through the mask before the spacer  22  is removed. This etch process can be performed in distinct steps or in one etch step. 
   After one spacer  22  is removed, a portion of the trench floor is left exposed. An etch process which will etch the substrate  10  selectively to the sacrificial material  25  is then performed to form an isolation window or slot  35 . Preferably, the isolation window  35  is asymmetric in that it will contact one side of the digit line, but not the other. In a preferred embodiment, the isolation window extends between about 500 Å and 3000 Å below the trench floor, more preferably between about 1000 Å and 2000 Å. 
   As seen in  FIG. 4 , the mask and remaining sacrificial material and spacer material are preferably removed after forming the isolation window  35 . 
   In  FIG. 5 , a second set of spacers is formed. First, an insulating layer  40  is conformally deposited over the array and the cap layer  15 . The insulating layer  40  is preferably silicon nitride, but other electrically insulating materials can also be used. The insulating layer preferably fills the isolation window  35  with a lower insulating layer. Preferably the insulating layer  40  has a thickness along the sidewalls of between about 60 Å and 600 Å, more preferably between about 100 Å and 200 Å. 
   After the conformal insulating layer is deposited, another spacer etch is performed to preferentially etch the horizontal surfaces of the insulating layer  40  and expose a second portion of the trench floor. This etch leaves remaining portions of the insulating layer  40  on the trench side walls in the form of insulating spacers that extend into the isolation window  35 . 
   An etch process selectively etches the substrate material relative to the materials selected for the cap layer  15  and the insulating layer  40  to recess the exposed portion of the trench floor to form a lower recess  45  in the substrate  10 . In a preferred embodiment, this etch process etches between about 10 Å and 3000 Å of the substrate  10 , more preferably between about 200 Å and 2500 Å. The insulating layer  40  along the sidewalls and the lower insulating layer in the isolation window  35  insulate the surrounding substrate. As can be seen from  FIG. 6 , one entire side of the lower recess  45  is exposed to the substrate  10 , while the other side of the lower recess  45  is partially bounded by the isolation window  35 . 
   In  FIG. 7 , an insulating material  50  is deposited into and recessed back in the lower recess  45  so that only one sidewall of the recess is electrically exposed to the digit line which will be formed within the lower recess  45 . In a preferred embodiment, the insulating material  50  has a thickness of between about 100 Å and 2000 Å, more preferably between about 500 Å and 800 Å. In order to fully isolate the selected side of the lower recess, the thickness of the insulating material  50  is greater than the distance between the bottom of the lower recess and the bottom of the isolation window  33 . In other words, the insulating material  50  overlaps with the insulating lay  40  to completely isolate the right side of each trench. 
   As illustrated in  FIG. 8 , once one side of the lower recess  45  is completely electrically isolated, a conductive digit line  55  is formed within the lower recess  45 . Preferred materials for the digit line  55  include metals and metal alloys. Exemplary materials include titanium nitride, titanium, and tungsten. Preferably, the digit line  55  has a vertical thickness of between about 100 Å and 2000 Å, more preferably between about 300 Å and 600 Å. 
   In one embodiment, a multi-level digit line  55  is formed with layers of several materials. In a preferred embodiment, a lower layer of titanium is first deposited, serving as an adhesion layer, followed by a middle layer of titanium nitride, serving as a conductive barrier, and an upper layer of tungsten fills the remainder of the trench. The thickness of the middle barrier layer is preferably between about 20 Å and 500 Å, more preferably between about 40 Å and 80 Å. The thickness of the lower adhesion layer is preferably between about 10 Å and 600 Å, more preferably between about 100 Å and 300 Å. The thickness of the upper layer is preferably between about 100 Å and 1500 Å, more preferably between about 300 Å and 600 Å. Each such deposition can line the lower recess  45 , thus extending over the trench sidewalls. 
   As seen in  FIG. 9 , after depositing and recessing the digit line  55 , the trench is filled with an insulating material  60 . In a preferred embodiment the insulating material is an oxide, such as a tetraethyl orthosilicide (TEOS) oxide or a spin-on oxide. The insulating material is then preferably etched back or planarized, through a process such as chemical mechanical polishing (CMP). In a preferred embodiment, the insulating material fills the trench, and is typically overflows by between about 50 Å and 2000 Å, more preferably between about 300 Å and 600 Å, before CMP or other etch back. 
   In a preferred embodiment, the buried digit lines  55  are then used to form a DRAM array. An exemplary array is seen after several stages of processing in  FIG. 10 . Several DRAM process can be used to form the memory array. One example process is found in U.S. patent application Ser. No. 10/934,621 of Tang, et. al, the disclosure of which is hereby incorporated herein by reference. 
   In the illustrated embodiment of  FIG. 10 , a transistor pillar  65  is formed on the substrate between the trenches. In a preferred embodiment, the pillars are epitaxial silicon, though in other arrangements the pillars can be etched from a substrate. A gate oxide  70  is then formed on the sides of the transistor pillars  65 . In a preferred embodiment, a source region is formed along ridges between the trenches, preferably contacting the transistor pillar. In preferred embodiments, the drain is formed at the top of the transistor pillar  65  and the body of the pillar defines the transistor channel. A word line  75  is formed between neighboring cells. In a preferred embodiment, the word line  75  is a conductive polysilicon and may include strapping self-aligned silicide. While not apparent from the illustrated cross-section, a plurality of word lines are formed in a crossing pattern with the bit lines. In a preferred arrangement, each word line surrounds a row of transistors and serves as a gate electrode for each of the transistors in the row. An insulating layer  80  is deposited over the word lines  75 . The top of the transistor pillar  65  is then exposed to form electrical contact to an overlying stacked capacitor. In a preferred embodiment, the capacitor electrode is a container capacitor. A bottom electrode  90  is formed electrically connected to the transistor pillar  65 . It will be understood that as intermediate contact plug can be employed between the pillar  65  and the bottom electrode  90 . In a preferred embodiment, the bottom electrode  90  comprises a conductive metal or metal alloy. A capacitor dielectric (not pictured) is then formed over the bottom electrode. A top electrode is then formed the dielectric. In a preferred embodiment the top electrode is a common reference electrode for the whole array. 
   An exemplary process flow for the illustrated vertical surround gate (VSG) transistor is disclosed in U.S. application Ser. No. 10/934,621, filed Sep. 2, 2004, the disclosure of which is incorporated by reference herein. The skilled artisan will readily appreciate, however, that the buried bit line processes and structures disclosed herein are useful for a number of different transistor and memory array designs. 
   Thus, in a preferred embodiment illustrated in  FIG. 10 , the digit line  55  is electrically connected to the substrate  10 , and particularly to the transistor sources, on one side of the trench, and isolated by the isolation liner  40  on the other side (right side in  FIG. 10 ). Preferably, the bottom of the insulating liner  40  in the isolation window  35  extends below or even with the bottom of the digit line  55 . In the illustrated embodiment, an insulator  50  is formed beneath the digit line  55  within the lower recess  45 . The digit line  55  is preferably isolated from above by an insulating material  60 . 
   In a preferred embodiment, vertical transistors are formed between the trenches. The vertical transistors include transistor pillars  65  over the substrate  10 . Preferably, a plurality of transistor pillars  65  are formed on a ridge running parallel between the trenches in the dimension into and out of the paper. A gate oxide  71  surrounds the sidewalls of the transistor pillar  65 . Preferably, a word line  75  serves as the gate electrode for each of a plurality of transistors in a row. An insulating layer  80  is formed over the word line  75 . A bottom container capacitor electrode  90  is formed over each transistor pillar. A capacitor dielectric and top electrode is preferably formed over each of the electrodes. These structures are arranged in a memory array. The number of cells, trenches, and digit lines may vary based upon the desired capacity of the memory array. 
   With reference to  FIG. 11 , in another embodiment, the isolation window  35   a  formed using the spacers as is extended deeper into the substrate  10  than in the embodiment of  FIG. 4 . Preferably, the isolation window is extended below the bottom of the subsequently formed lower recess  45   a . As described above, the isolation window  35   a  is filled with the insulating layer  40   a . The subsequent lower recess  45   a  extends to approximately the same depth or less deep than the isolation window  35   a . Preferably the bottom of the isolation window  35   a  is 100 Å to 2000 Å below the bottom of the digit line  55   a , more preferably the bottom of the isolation window  35   a  is 500 Å to 800 Å below the bottom of the digit line  55   a . The lower insulating material  50  of  FIG. 7  can thus be omitted, saving the deposition and recess steps therefor. Accordingly, the digit line  55   a  is deposited directly into the lower recess  45   a.    
   In the resulting structure, the bottom of the insulating material  40   a  in the isolation window  35   a  preferably extends below the digit line  55   a  or is co-extensive with the bottom of the digit line  55   a . On the other side of the trench, the top edge of the digit line  55   a  is isolated from the transistor channel by the isolation liner  40   a.    
   As best seen from the cross-sectional plan of  FIG. 12 , the resultant buried digit line  55  or  55   a  directly contacts the ridge of the substrate  10  along which a column of source regions  95  are formed. The bit digit line  55  or  55   a  is in continuous contact with the ridge of substrate material  10 , such that no independent bit line contact structure is required. Rather, the digit line  55  or  55   a  intermittently contacts source regions along its length. It will be understood that the source regions extend upwards to the surface of the substrate  10 , where epitaxial pillars extend upwards and form the channel regions of the transistors. Orthogonal to the digit lines  55  or  55   a  are a plurality of word lines  75 , shown in dotted lines in  FIG. 12 , overlapping a row of transistors and surrounding the pillar channel regions to define vertical surround gate (VSG) transistors. On one side of the digit line structures  55  or  55   a , the insulating layer  40  or  40   a  electrically separates the digit line  55  or  55   a  from the next adjacent ridge of substrate material  10 . 
   Advantageously, because the digit line  55  or  55   a  directly contacts the substrate ridge  10  in the source regions, no separate contact structure is required. Not only does this save the additional process steps for forming a contact structure, but also save the additional space that would be otherwise required for making separate bit line contacts. 
   It will be appreciated by those skilled in the art that various omissions, additions and modifications may be made to the methods and structures described above without departing from the scope of the invention. All such modifications and changes are intended to fall within the scope of the invention, as defined by the appended claims.