Abstract:
A method of fabricating an array substrate for a liquid crystal display device can include forming a gate line and a gate electrode, and a gate insulating layer; forming an active layer on the gate insulating layer and an ohmic contact layer on the active layer; forming a data line and source and drain electrodes; forming a passivation layer on the source and drain electrodes; and forming a pixel electrode on the passivation layer, in which the ohmic contact layer covers an entire top surface of the active layer between the source and drain electrodes; forming a metallic layer on the gate insulating layer and the ohmic contact layer; etching the metallic layer to faun the data line, and the source drain electrodes, in which a silicide layer is formed on the ohmic contact layer only in the space between the source and drain electrodes; and removing the silicide layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a Divisional of co-pending U.S. application Ser. No. 14/276,903, filed on May 13, 2014, which is a Continuation-in-Part of U.S. application Ser. No. 12/196,786, filed on Aug. 22, 2008, which claims the priority benefit of Korean Patent Application No. 10-2008-0014141, filed on Feb. 15, 2008. The entire contents of all these applications are hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Disclosure 
         [0003]    The present invention relates to an array substrate for a liquid crystal display (LCD) device and more particularly to an array substrate for an LCD device having improved properties and being capable of preventing a photo leakage current problem, and a method of fabrication the array substrate. 
         [0004]    2. Description of the Related Art 
         [0005]    A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. In other words, as the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity. 
         [0006]    Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used. 
         [0007]      FIG. 1  is a plan view of a pixel region of the related art array substrate for the LCD device. In  FIG. 1 , a gate line  20  and a data line  30  are formed on a substrate  10 . The gate and data lines  20  and  30  cross each other to define a pixel region “P”. A thin film transistor (TFT) “T” is formed at a crossing portion of the gate and data lines  20  and  30 . The TFT “T” includes a gate electrode  25 , a semiconductor layer (not shown), a source electrode  32  and a drain electrode  34 . The gate electrode  25  extends from the gate line  20 , and the semiconductor layer is formed over the gate electrode  25  to overlap the gate electrode  25 . The source electrode  32  extends from the data line  30  and is spaced apart from the drain electrode  34 . The source and drain electrodes  32  and  34  contact the semiconductor layer. Although not shown, the semiconductor layer includes an active layer of intrinsic amorphous silicon and an ohmic contact layer of impurity-doped amorphous silicon. In addition, a pixel electrode  70  contacting the drain electrode  34  through a drain contact hole “CH 1 ”, which exposes a portion of the drain electrode  34 , is formed in the pixel region “P”. 
         [0008]    Referring to  FIGS. 2A to 2G , a method of fabricating the related art array substrate is explained.  FIGS. 2A to 2G  are cross-sectional views showing a fabricating process of a portion taken along the line II-II′ in  FIG. 1 . A region, where the TFT is formed, is defined as a switching region “S(T)”. 
         [0009]      FIG. 2A  shows a first mask process. In  FIG. 2A , a first metal layer (not shown) is formed on the substrate  10  by depositing a conductive metallic material. The conductive metallic material includes copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) and chrome (Cr). The first metal layer is patterned using a first mask (not shown) to form the gate line  20  (of  FIG. 1 ) and the gate electrode  25 . The gate electrode  25  extends from the gate line  20  (of  FIG. 1 ) and is disposed in the switching region “S(T)”. Next, a gate insulating layer  45  is formed on the substrate  10 , where the gate line  20  (of  FIG. 1 ) and the gate electrode  25  are formed, by depositing an inorganic insulating material. The inorganic insulating material includes silicon oxide (SiO 2 ) and silicon nitride (SiNx). 
         [0010]      FIGS. 2B and 2C  show a second mask process. In  FIG. 2B , an intrinsic amorphous silicon layer  40   a  of intrinsic amorphous silicon and an impurity-doped amorphous silicon layer  41   a  of impurity-doped amorphous silicon are sequentially formed on the gate insulating layer  45 . The intrinsic amorphous silicon layer  40   a  and the impurity-doped amorphous silicon layer  41  a have first and second thickness, respectively. For example, the first thickness of the intrinsic amorphous silicon layer  40   a  may be about 1500 angstroms to about 2000 angstroms, and the second thickness of the impurity-doped amorphous silicon layer  41   a  may be about 500 angstroms to about 1000 angstroms. Namely, the intrinsic amorphous silicon layer  40   a  has a greater thickness than the impurity-doped amorphous silicon layer  41   a . For example, a thickness of the intrinsic amorphous silicon layer  40   a  may be nearly five times as much as that of the impurity-doped amorphous silicon layer  41   a.    
         [0011]    In  FIG. 2C , the intrinsic amorphous silicon layer  40   a  (of  FIG. 2B ) and the intrinsic amorphous silicon layer  40   a  (of  FIG. 2B ) are patterned using a second mask (not shown) to form an active layer  40  and an ohmic contact layer  41 . The active layer  40  overlaps the gate electrode  25 , and the ohmic contact layer  41  is disposed on the active layer  40 . The active layer  40  and the ohmic contact layer  41  have the same plane area as each other. The active layer  40  and the ohmic contact layer  41  constitute a semiconductor layer  42 . 
         [0012]      FIGS. 2D and 2E  show a third mask process. In  FIG. 2D , a second metal layer (not shown) is formed on the semiconductor layer  42  by depositing a conductive metallic material. The conductive metallic material includes copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) and chrome (Cr). The second metal layer is patterned using a third mask (not shown) to form the data line  30 , the source electrode  32  and the drain electrode  34 . The data line  30  crosses the gate line  20  (of  FIG. 1 ) to define the pixel region “P”. The source electrode  32  extends from the data line  30  and is spaced apart from the drain electrode  34 . As a result, a portion of the ohmic contact layer  41  is exposed between the source and drain electrodes  32  and  34 . 
         [0013]    Next, in  FIG. 2E , the exposed portion of the ohmic contact layer  41  is etched by a dry-etching process using the source and drain electrodes  32  and  34  as an etching mask to expose a portion of the active layer  40 . The portion of the active layer  40  is over-etched to form a back-etch type channel “ch”. The gate electrode  25 , the gate insulating layer  45 , the semiconductor layer  42 , which includes the active layer  40  and the ohmic contact layer  41 , the source electrode  32  and the drain electrode  34  constitute the TFT “T” (of  FIG. 1 ) in the switching region “S(T)”. 
         [0014]      FIG. 2F  shows a fourth mask process. In  FIG. 2F , a passivation layer  55  is formed on the data line  30 , the source electrode  32  and the drain electrode  34 . The passivation layer  55  includes one of an inorganic insulating material, such as silicon nitride and silicon oxide, and an organic insulating material, such as acryl-based resin and benzocyclobutene (BCB). The passivation layer  55  is patterned using a fourth mask (not shown) to form a drain contact hole “CH 1 ” exposing a portion of the drain electrode  34 . 
         [0015]      FIG. 2G  shows a fifth mask process. In  FIG. 2G , a transparent conductive metal layer (not shown) is formed on the passivation layer  55  including the drain contact hole “CH 1 ”. The transparent conductive metal layer includes a transparent conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The transparent conductive metal layer is patterned using a fifth mask (not shown) to form the pixel electrode  70  in the pixel region “P”. The pixel electrode  70  contacts the drain electrode  34  through the drain contact hole “CH 1 ”. 
         [0016]    The related art array substrate for the LCD device is fabricated by the above-mentioned five mask process. In the related art array substrate, the active layer  40  has a greater thickness than the ohmic contact layer  41  to obtain the back-etch type channel “ch”. As mentioned above, a thickness of the intrinsic amorphous silicon layer  40   a  may be nearly five times as much as that of the impurity-doped amorphous silicon layer  41   a . When there is a process error in etching the exposed ohmic contact layer  41  and the active layer  40  to form the back-etch type channel “ch”, not only the active layer  40  but also the gate insulating layer  45  may have an damage such that properties of the TFT are degraded. To prevent these problems, the active layer  40  has a greater thickness than the ohmic contact layer  41 . 
         [0017]    However, the active layer  40  having the relatively high thickness causes resistance between the source electrode  32  and the channel “ch” or/and between drain electrode  34  and the channel “ch” to be increased. As a result, properties of the TFT “T” are degraded. Particularly, the greater thickness the active layer  40  has, the much photo leakage current there is. The photo leakage current is generated when the active layer  40  is exposed to the light from a backlight unit or the ambient light. The photo leakage current causes the properties of the TFT “T” to be degraded. Moreover, the photo leakage current causes a cross-talk problem such that a displaying image quality in the LCD device is also degraded. Furthermore, the great thickness of the active layer  40  requires the production time and the initial investment for the machine to be increased. Namely, productivity is decreased. 
       SUMMARY OF THE INVENTION 
       [0018]    Accordingly, the present invention is directed to an array substrate for an LCD device and a method of fabrication the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
         [0019]    Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
         [0020]    To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, an array substrate for a liquid crystal display device includes a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode; an active layer of intrinsic amorphous silicon on the gate insulating layer and corresponding to the gate electrode; an ohmic contact layer of impurity-doped amorphous silicon on the active layer; a data line crossing the gate line; a source electrode on the ohmic contact layer and connected to the data line; a drain electrode on the ohmic contact layer and spaced apart from the source electrode; a passivation layer on the source and drain electrodes and including a drain contact hole exposing a portion of the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the drain contact hole, wherein the ohmic contact layer covers the active layer in a space between the source and drain electrodes. 
         [0021]    In another aspect of the present invention, a method of fabricating an array substrate for a liquid crystal display device includes forming a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate electrode; forming an active layer of intrinsic amorphous silicon on the gate insulating layer and an ohmic contact layer of impurity-doped amorphous silicon on the active layer, the active layer corresponding to the gate electrode; forming a data line, a source electrode and a drain electrode, the data line crossing the gate line, the source electrode on the ohmic contact layer and connected to the data line, and the drain electrode on the ohmic contact layer and spaced apart from the source electrode; forming a passivation layer on the source and drain electrodes and including a drain contact hole exposing a portion of the drain electrode; and forming a pixel electrode on the passivation layer and connected to the drain electrode through the drain contact hole, wherein the ohmic contact layer covers the active layer in a space between the source and drain electrodes. 
         [0022]    In another aspect of the present invention, a liquid crystal display module includes a liquid crystal panel including an array substrate and a color filter substrate, the array substrate including: a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode; an active layer of intrinsic amorphous silicon on the gate insulating layer and corresponding to the gate electrode; an ohmic contact layer of impurity-doped amorphous silicon on the active layer; a data line crossing the gate line; a source electrode on the ohmic contact layer and connected to the data line; a drain electrode on the ohmic contact layer and spaced apart from the source electrode; a passivation layer on the source and drain electrodes and including a drain contact hole exposing a portion of the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the drain contact hole, wherein the ohmic contact layer covers the active layer in a space between the source and drain electrodes; and a backlight unit for projecting light on the liquid crystal panel and disposed under the array substrate. 
         [0023]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. 
           [0025]      FIG. 1  is a plan view of a pixel region of the related art array substrate for the LCD device; 
           [0026]      FIGS. 2A to 2G  are cross-sectional views showing a fabricating process of a portion taken along the line in  FIG. 1 ; 
           [0027]      FIG. 3  is a plan view of a pixel region of an array substrate for an LCD device according to a first embodiment of the present invention; 
           [0028]      FIG. 4  is a cross-sectional view of a portion taken along the line IV-IV′ in  FIG. 3 ; 
           [0029]      FIGS. 5A to 5I  are cross-sectional views showing a fabricating process of a portion taken along the line IV-IV′ in  FIG. 3 ; 
           [0030]      FIG. 6  is a plan view of a pixel region of an array substrate for an LCD device according to a second embodiment of the present invention; 
           [0031]      FIG. 7  is a graph showing an I-V transfer curve in a TFT of an array substrate according to an embodiment of the present invention; 
           [0032]      FIG. 8  is a graph showing mobility of an electric charge depending on a gate voltage in a TFT of an array substrate according to an embodiment of the present invention; 
           [0033]      FIG. 9  is a graph showing a drain-source current depending on a gate-source voltage in a TFT of an array substrate according to an embodiment of the present invention; and 
           [0034]      FIGS. 10A and 10B  are cross-sectional views showing a fabricating process of a portion taken along the line IV-IV′ in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0035]    Reference will now be made in detail to the preferred embodiments, examples of which are illustrated in the accompanying drawings. 
         [0036]    In an array substrate for an LCD device according to a first embodiment of the present invention, an ohmic contact layer and an active layer is not etched such that it is possible to form the active layer having a less thickness than the active layer in the related art array substrate. A flow of a free electron in a channel is efficient 1 y controlled by an voltage of negative or positive applied to a gate electrode such that a driving property of the TFT is improved. 
         [0037]      FIG. 3  is a plan view of a pixel region of an array substrate for an LCD device according to a first embodiment of the present invention, and  FIG. 4  is a cross-sectional view of a portion taken along the line IV-IV′ in  FIG. 3 . 
         [0038]    In  FIGS. 3 and 4 , a gate line  120  is formed on a substrate  110 , and a data line  130  crosses the gate line  120  to define a pixel region “P”. The data line  130  may be perpendicular or inclined to the gate line  120 . A thin film transistor (TFT) “T” as a switching element is formed at a crossing portion of the gate and data lines  120  and  130 . The TFT “T” includes a gate electrode  125 , a gate insulating layer  145 , a semiconductor layer  142  including an active layer  140  and an ohmic contact layer  141 , a source electrode  132  and a drain electrode  134 . The gate electrode  125  extends from the gate line  120 , and the gate insulating layer  145  is formed on the gate line  120  and the gate electrode  125 . The semiconductor layer  142  is formed on the gate insulating layer  145  and overlaps the gate electrode  125 . The ohmic contact layer  141  is disposed on the active layer  140  and has the same plane area as the active layer  140 . The source electrode  132  extends from the data line  130  and is spaced apart from the drain electrode  134 . The source and drain electrodes  132  and  134  contact the ohmic contact layer  141 . The TFT “T” is connected to the gate line  120  and the data line  130  through the gate electrode  125  and the source electrode  132 , respectively. 
         [0039]    The active layer  140  of intrinsic amorphous silicon has a first thickness “t 1 ”, and the ohmic contact layer  141  of impurity-doped amorphous silicon has a second thickness “t 2 ”. For example, the first thickness “t 1 ”of the active layer  140  may be about 100 angstroms to about 700 angstroms, and the second thickness “t 2 ” of the ohmic contact layer  141  may be about 50 angstroms to about 500 angstroms. The active layer  140  may have substantially the same thickness as the ohmic contact layer  141 . A portion of the ohmic contact layer  141  is exposed between the source and drain electrodes  132  and  134 . 
         [0040]    In addition, a passivation layer  155  including a drain contact hole “CH 2 ” is formed on the TFT “T”. The drain contact hole “CH 2 ” exposes a portion of the drain electrode  134 . A pixel electrode  170 , which is formed on the passivation layer  155  and in the pixel region “P”, contacts the drain electrode  134  through the drain contact hole “CH 2 ”. The pixel electrode  170  extends to a previous gate line  120  to overlap a portion of the gate line  120 . The overlapped portion of the gate line  120  functions as a first electrode, the overlapped portion of the pixel electrode  170  functions as a second electrode, and the gate insulating layer  145  and the passivation layer  155  function as a dielectric material layer. The first electrode, the second electrode and the dielectric material layer constitute a storage capacitor “Cst”. On the other hand, although not shown, a metal pattern (not shown), which is disposed on the gate insulating layer  145 , may be disposed between the first and second electrodes. The metal pattern is connected to one of the first and second electrodes. In this case, only one of the gate insulating layer and the passivation layer functions as the dielectric material layer. 
         [0041]    In the array substrate of the first embodiment, the active layer  140  may have substantially the same thickness as the ohmic contact layer  141 . As a result, a production time or the initial investment for the machine can be reduced. In addition, since the ohmic contact layer  141  is not separated, there is an advantage in an electric charge mobility through the channel. 
         [0042]    On the other hand, although not shown, the TFT “T” in  FIGS. 3 and 4  can be available for an in-plane switching (IPS) mode LCD device where a pixel electrode and a common electrode are alternately arranged in a single substrate. 
         [0043]    Referring to  FIGS. 5A to 5I , a method of fabricating an array substrate for an LCD device according to the first embodiment of the present invention is explained.  FIGS. 5A to 5I  are cross-sectional views showing a fabricating process of a portion taken along the line IV-IV′ in  FIG. 3 . A switching region “S(T)”, where a TFT is formed, a pixel region “P” and a data region “D”, where a data line is formed, are defined on a substrate. 
         [0044]      FIG. 5A  shows a first mask process. In  FIG. 5A , a first metal layer (not shown) is formed on the substrate  110  by depositing a conductive metallic material. The conductive metallic material includes copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) and chrome (Cr). The first metal layer is patterned using a first mask (not shown) to form the gate line  120  (of  FIG. 3 ) and the gate electrode  125 . The gate electrode  125  extends from the gate line  120  (of  FIG. 3 ) and is disposed in the switching region “S(T)”. Next, a gate insulating layer  145  is formed on the substrate  110 , where the gate line  120  (of  FIG. 3 ) and the gate electrode  125  are formed, by depositing an inorganic insulating material. The inorganic insulating material includes silicon oxide (SiO 2 ) and silicon nitride (SiNx). 
         [0045]      FIGS. 5B and 5C  show a second mask process. In  FIG. 5B , an intrinsic amorphous silicon layer  140   a  of intrinsic amorphous silicon and an impurity-doped amorphous silicon layer  141   a  of impurity-doped amorphous silicon are sequentially formed on the gate insulating layer  145 . The intrinsic amorphous silicon layer  140   a  and the impurity-doped amorphous silicon layer  141   a  have first and second thickness “t 1 ” and “t 2 ”, respectively. A ratio of the first thickness “t 1 ” to the second thickness “t 2 ” may be 1˜1.5:1. For example, the first thickness “t 1 ” of the intrinsic amorphous silicon layer  140   a  may be about 100 angstroms to about 700 angstroms, and the second thickness “t 2 ” of the impurity-doped amorphous silicon layer  141   a  may be about 50 angstroms to about 500 angstroms. The active layer  140   a  may have substantially the same thickness as the ohmic contact layer  141   a.    
         [0046]    In  FIG. 5C , the intrinsic amorphous silicon layer  140   a  (of  FIG. 5B ) and the intrinsic amorphous silicon layer  140   a  (of  FIG. 5B ) are patterned using a second mask (not shown) to form an active layer  140  and an ohmic contact layer  141 . The active layer  140  overlaps the gate electrode  125 , and the ohmic contact layer  141  is disposed on the active layer  140 . Each of the active layer  140  and the ohmic contact layer  141  has an island shape. Since the active layer  140  and the ohmic contact layer  141  are patterned using a single mask, the active layer  140  and the ohmic contact layer  141  have the same plane area as each other. The active layer  140  and the ohmic contact layer  141  constitute a semiconductor layer  142 . With compared to the active layer in the related art array substrate, the array substrate  140  in the array substrate according to the present invention has a relatively small thickness. 
         [0047]    As mentioned above, the active layer  140  and the ohmic contact layer  141  constitute a semiconductor layer  142  to function as a semiconductor channel between the source electrode  132  and the drain electrode  134 . To this end, the semiconductive layer  142  may be formed of suitable materials that may, for example, be doped with an appropriate amount of impurities to be a semiconductor having an appropriate level threshold voltage. Therefore, the semiconductive layer  142  does not short-circuit the source and drain electrodes  132  and  134  when there is no gate voltage, whereas the semiconductive layer  142  does connect the source and drain electrodes  132  and  134  when a gate voltage is applied to the gate electrode  125 . In accordance with one embodiment, when the voltage to be applied between the source and drain electrodes  132  and  134  is, for example, 1 volt (V), the semiconductive layer  142  (i.e., the active layer  140  and/or the ohmic contact layer  141 ) can be doped with an appropriate amount of p-type or n-type impurities so that the semiconductive layer  142  can have a threshold voltage higher than 1 V, for example, 1.2 V. In accordance with one embodiment, the ohmic contact layer  141  may be doped to have a threshold voltage higher than 1V, while no or litt 1 e dopant is added to the active layer  140 . In another example, opposite types of impurities may be added to the active layer  140  and the ohmic contact layer  141 . 
         [0048]      FIGS. 5D, 5E and 5F  show a third mask process. In  FIG. 5D , a second metal layer  175  is formed on the substrate  110  including the semiconductor layer  142  by depositing a conductive metallic material. The conductive metallic material includes copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) and chrome (Cr). A photosensitive material layer  180  is formed on the second metal layer  175  by coating a photosensitive material such as photoresist (PR). 
         [0049]    A third mask “M” including a blocking area “T 1 ” and a transmitting area “T 2 ” is disposed on the photosensitive material layer  180 . The transmitting area “T 2 ” has transmittance greater than that of the blocking area “T 1 ”. The blocking area “T 1 ” shields light completely. The transmitting area “T 2 ” has a relatively high transmittance, for example, about 100%, so that light through the transmitting area “T 2 ” can completely change the photosensitive material layer  180  chemically. In the switching region “S(T)”, the third mask “M” includes the transmitting area “T 2 ” between the blocking area “T 1 ”. Namely, the transmitting area “T 2 ” corresponds to a center of the gate electrode  125 . The blocking area “T 1 ” also corresponds to the data region “D”. The transmitting area “T 2 ” corresponds to other regions. 
         [0050]    In  FIG. 5E , the photosensitive material layer  180  (of  FIG. 5D ) is exposed through the mask “M” (of  FIG. 5D ) and then developed to form first, second and third photosensitive material patterns  182 ,  184  and  186 . The first and second photosensitive material patterns  182  and  184  correspond to sides of the gate electrode  125  to expose a portion of the second metal layer  175 . The exposed portion of the second metal layer  175  between the first and second photosensitive material patterns  182  and  184  corresponds to the center of the gate electrode  125 . The third photosensitive material pattern  186  corresponds to the data region “D”. By the exposing and developing processes on the photosensitive material layer  180  (of  FIG. 5D ), the photosensitive material layer  180  (of  FIG. 5D ) corresponding to the transmitting area “T 2 ” (of  FIG. 5D ) of the third mask (of  FIG. 5D ) is removed to exposed the second metal layer  175 . 
         [0051]    In  FIG. 5F , the exposed second metal layer  175  (of  FIG. 5E ) is patterned using the first, second and third the photosensitive material patterns  182 ,  184  and  186  as a patterning mask to form the data line  130 , the source electrode  132  and the drain electrode  134 . The data line  130  is positioned in the data region “D” and crosses the gate line  120  (of  FIG. 3 ) to defined the pixel region “P”. The source electrode  132  extends from the data line  130  and is spaced apart from the drain electrode  134 . A portion of the ohmic contact layer  141  is exposed between the source and drain electrodes  132  and  134 . 
         [0052]    The second metal layer  175  (of  FIG. 5E ) is patterned by a wet-etching process or a dry-etching process. In the wet-etching process or the dry-etching process, a material of the ohmic contact layer  141  reacts with a material of the source and drain electrodes  132  and  134  such that a silicide layer  190  is formed on a surface of the ohmic contact layer  141  between the source and drain electrode  132  and  134 . The active layer  140  and the ohmic contact layer  141  between the source and drain electrodes  132  and  134  function as a channel “ch”. The silicide layer  190  on the ohmic contact layer  141  in the channel “ch” functions as a trap for an electron, which obstruct a flow of a free electron in the channel “ch”, to increase a resistance. Accordingly, the silicide layer  190  is removed to improved properties of the TFT “T”. The silicide layer  190  is removed by a dry-etching process using a reaction gas, for example, a hydrogen chloride (HCl) gas, a chlorine (Cl 2 ) gas, a sulfur hexafluoride gas (SF 6 ) or a carbon fluoride gas (CF 4 ), or a wet-etching process using an etchant, for example, a fluoric acid (HF) solution. 
         [0053]    On the other hand, as shown in  FIGS. 10A and 10B , a metal oxide layer  191  may be formed on the silicide layer  190  instead of removing the silicide layer  190  to improve mobility of a free electron in the channel “ch”. The metal oxide layer  191  may be formed by an oxygen (O 2 ) plasma processing. 
         [0054]    In  FIG. 5G , the silicide layer  190  (of  FIG. 5F ) is removed such that a portion of the ohmic contact layer  141  is exposed between the source and drain electrodes  132  and  134 . The first, second and third photosensitive material patterns  182 ,  184  and  186  are removed. The gate electrode  125 , the gate insulating layer  145 , the semiconductor layer  142 , the source electrode  132  and the drain electrode  134  constitute the TFT in the switching region “S(T)”. 
         [0055]      FIG. 5H  shows a fourth mask process. In  FIG. 5H , a passivation layer  155  is formed on the substrate  110  including the data line  130  and the TFT. The passivation layer  155  includes one of an inorganic insulating material, such as silicon nitride and silicon oxide, and an organic insulating material, such as acryl-based resin and benzocyclobutene (BCB). The passivation layer  155  is patterned using a fourth mask (not shown) to form a drain contact hole “CH 2 ” exposing a portion of the drain electrode  134 . 
         [0056]      FIG. 5I  shows a fifth mask process. In  FIG. 5I , a transparent conductive metal layer (not shown) is formed on the passivation layer  155  including the drain contact hole “CH 2 ”. The transparent conductive metal layer includes a transparent conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The transparent conductive metal layer is patterned using a fifth mask (not shown) to form the pixel electrode  170  in the pixel region “P”. The pixel electrode  170  contacts the drain electrode  134  through the drain contact hole “CH 2 ”. 
         [0057]    Although not shown, the pixel electrode  170  extends to a previous gate line  120  (of  FIG. 3 ) to overlap a portion of the gate line  120 . The overlapped portion of the gate line  120  functions as a first electrode, the overlapped portion of the pixel electrode  120  functions as a second electrode, and the gate insulating layer  145  and the passivation layer  155  function as a dielectric material layer. The first electrode, the second electrode and the dielectric material layer constitute a storage capacitor “Cst” (of  FIG. 3 ). On the other hand, although not shown, a metal pattern (not shown), which is disposed on the gate insulating layer  145 , may be disposed between the first and second electrodes. The metal pattern is connected to one of the first and second electrodes. In this case, only one of the gate insulating layer and the passivation layer functions as the dielectric material layer. 
         [0058]    When a negative voltage is applied into the gate electrode  125 , there is no free electron in the channel “ch” including the active layer  140  and the ohmic contact layer  141  such that the TFT “T” is driven in an Off state. On the other hand, when a positive voltage is applied into the gate electrode  125 , a free electron is accumulated on the channel “ch” such that the TFT “T” is driven in an On state. In the On state of the TFT “T”, a data signal in the data line  130  is supplied into the pixel electrode  170  through the TFT “T”. As a result, the liquid crystal layer (not shown) is driven by an electric field induced between the pixel electrode  170  and a common electrode (not shown) on a color filter substrate facing the array substrate such that the LCD device display images. 
         [0059]    In the array substrate according to the present invention, since the active layer  140  has a relatively small thickness with compared to the active layer of the related art array substrate, a distance between the gate electrode  125  and the ohmic contact layer  141  is reduced. Accordingly, even if the exposed portion of the ohmic contact layer  141  between the source and drain electrodes  132  and  134  is not removed, the active layer  140  and the ohmic contact layer  141  function as a channel “ch”. 
         [0060]    In more detail, in the related art array substrate, since the active layer is thicker than the ohmic contact layer, a distance between the gate electrode and the ohmic contact layer is relatively far. Accordingly, if the exposed portion of the ohmic contact layer between the source and drain electrodes and is not removed, it is impossible to control the On or Off state of the TFT by applying a negative or positive voltage into the gate electrode. However, since the distance between the gate electrode  125  and the ohmic contact layer  141  is close due to the reduced thickness of the active layer  140 , the TFT “T” has an On or Off state by applying a negative or positive voltage into the gate electrode  125 . Namely, not only the active layer  140  but also the ohmic contact layer  141  functions as a channel “ch”. 
         [0061]    Moreover, a photo leakage current is relieved due to the active layer  140  having the reduced thickness. Accordingly, the TFT “T” has improved properties and the LCD can display high quality images. Furthermore, since a process for removing a portion of the ohmic contact layer can be omitted, the fabricating process is simplified and the production time is reduced. Accordingly, productivity is improved. 
         [0062]      FIG. 6  is a plan view of a pixel region of an array substrate for an LCD device according to a second embodiment of the present invention. In the second embodiment, a number of mask processes can be reduced. 
         [0063]    In  FIG. 6 , a gate line  220  is formed on a substrate  210 , and a data line  230  crosses the gate line  220  to define a pixel region “P”. The data line  230  may be perpendicular or inclined to the gate line  220 . A thin film transistor (TFT) “T” as a switching element is formed at a crossing portion of the gate and data lines  220  and  230 . The TFT “T” includes a gate electrode  225 , a gate insulating layer (not shown), a semiconductor layer (not shown) including an active layer (not shown) and an ohmic contact layer (not shown), a source electrode  232  and a drain electrode  234 . The gate electrode  225  extends from the gate line  220 , and the gate insulating layer (not shown) is formed on the gate line  220  and the gate electrode  225 . The semiconductor layer (not shown) is formed on the gate insulating layer (not shown) and overlaps the gate electrode  225 . The ohmic contact layer (not shown) is disposed on the active layer (not shown) and has the same plane area as the active layer (not shown). The source electrode  232  extends from the data line  230  and is spaced apart from the drain electrode  234 . The source and drain electrodes  232  and  234  contact the ohmic contact layer (not shown). In accordance with one embodiment, the active layer and the ohmic contact layer may constitute a semiconductor layer to function as a semiconductor channel between the source electrode  232  and the drain electrode  234 . To this end, the semiconductive layer may be formed of suitable materials that may, for example, be doped with an appropriate amount of impurities to be a semiconductor having an appropriate level threshold voltage. Therefore, the semiconductive layer does not short-circuit the source and drain electrodes  232  and  234  when there is no gate voltage, whereas the semiconductive layer does connect the source and drain electrodes  232  and  234  when a gate voltage is applied to the gate electrode  225 . By way of example, when the voltage to be applied between the source and drain electrodes  232  and  234  is, for instance, 1 V, the semiconductive layer may be doped with an appropriate amount of p-type or n-type impurities so that the semiconductive layer can have a threshold voltage higher than 1 V, for example, 1.2-1.5 V. 
         [0064]    The active layer (not shown) of intrinsic amorphous silicon has a first thickness, and the ohmic contact layer (not shown) of impurity-doped amorphous silicon has a second thickness. For example, the first thickness of the active layer (not shown) may be about 100 angstroms to about 700 angstroms, and the second thickness of the ohmic contact layer (not shown) may be about 50 angstroms to about 500 angstroms. The active layer (not shown) may have substantially the same thickness as the ohmic contact layer (not shown). A portion of the ohmic contact layer (not shown) is exposed between the source and drain electrodes  132  and  134 . A semiconductor pattern  274  extends from the semiconductor layer (not shown) in the TFT “T” into the data line  130 . As a result, the semiconductor pattern  274  is disposed under the data line  130 . 
         [0065]    In addition, a passivation layer (not shown) including a drain contact hole “CH 3 ” is formed on the TFT “T”. The drain contact hole “CH 3 ” exposes a portion of the drain electrode  234 . A pixel electrode  270 , which is formed on the passivation layer (not shown) and in the pixel region “P”, contacts the drain electrode  234  through the drain contact hole “CH 3 ”. The pixel electrode  270  extends to a previous gate line  220  to overlap a portion of the gate line  220 . The overlapped portion of the gate line  220  functions as a first electrode, the overlapped portion of the pixel electrode  270  functions as a second electrode, and the gate insulating layer (not shown) and the passivation layer (not shown) function as a dielectric material layer. The first electrode, the second electrode and the dielectric material layer constitute a storage capacitor “Cst”. On the other hand, although not shown, a metal pattern (not shown), which is disposed on the gate insulating layer (not shown), may be disposed between the first and second electrodes. The metal pattern is connected to one of the first and second electrodes. In this case, only one of the gate insulating layer and the passivation layer functions as the dielectric material layer. 
         [0066]    The array substrate according to the second embodiment of the present invention is fabricated by a four mask process. In a first mask process, the gate line  220  and the gate electrode  225  are formed on the substrate  210 . In addition, the gate insulating layer is formed on the gate line  220  and the gate electrode  225 . In a second mask process, the active layer, the ohmic contact layer, the source electrode  232 , the drain electrode  234  and the data line  230  are formed. In more detail, an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer and a metal layer is sequentially formed on the gate insulating layer. Then, the metal layer, the impurity-doped amorphous silicon layer and the intrinsic amorphous silicon layer are patterned using a half-tone mask including a transmitting area, a blocking area and a half-transmitting area. A transmittance of the half-transmitting area is smaller than that of the transmitting area and greater than that of the blocking area. Due to the half-tone mask, there are first and second photosensitive material patterns having a difference in a height. As a result, the active layer, the ohmic contact layer, the source electrode  232 , the drain electrode  234  and the data line  230  are formed by a single mask process. In a third mask process, the passivation layer including the drain contact hole “CH 3 ” is fornied on the data line  130  and the TFT “T”. In a fourth mask process, the pixel electrode  170  is formed on the passivation layer. 
         [0067]    In the array substrate according to the present invention, since the active layer has a relatively small thickness with compared to the active layer of the related art array substrate, a distance between the gate electrode and the ohmic contact layer is reduced. Accordingly, even if the exposed portion of the ohmic contact layer between the source and drain electrodes and is not removed, the active layer and the ohmic contact layer function as a channel. The TFT has an On or Off state by applying a negative or positive voltage into the gate electrode. 
         [0068]    Moreover, a photo leakage current is relieved due to the active layer having the reduced thickness. A wavy noisy problem, which results from the semiconductor pattern under the data line, is relieved due to the active layer having the reduced thickness. Accordingly, the TFT has improved properties and the LCD can display high quality images. Furthermore, since a process for removing a portion of the ohmic contact layer can be omitted, the fabricating process is simplified and the production time is reduced. Accordingly, productivity is improved. 
         [0069]      FIG. 7  is a graph showing an I-V transfer curve in a TFT of an array substrate according to an embodiment of the present invention. In  FIG. 7 , the reference number (1) shows an I-V transfer curve in the TFT of the related art array substrate, and the reference numbers (2) to (5) show an I-V transfer curve in the TFT of the array substrate according to the present invention. The active layer and the ohmic contact layer have a thickness of about 300 angstroms and about 100 angstroms, respectively, in the curve (2), and the active layer and the ohmic contact layer have a thickness of about 300 angstroms and about 200 angstroms, respectively, in the curve (3). The active layer and the ohmic contact layer have a thickness of about 500 angstroms and about 100 angstroms, respectively, in the curve (4), and the active layer and the ohmic contact layer have a thickness of about 500 angstroms and about 200 angstroms, respectively, in the curve (5). When a drain-source voltage (Vds) of about 1 V is applied and the gate-source voltage (Vgs) is varied within a range of −10V to 20V, a drain -source current (Ids) is measured. The drain-source current (Ids) in the curves (2) to (5) is increased with compared to the curve (1). Namely,  FIG. 7  shows the TFT in the array substrate according to the present invention has an improved property. 
         [0070]      FIG. 8  is a graph showing mobility of an electric charge depending on a gate voltage in a TFT of an array substrate according to an embodiment of the present invention. In  FIG. 8 , the reference number (1) shows mobility of an electric charge in the TFT of the related art array substrate, and the reference number (2) shows mobility of an electric charge in the TFT of the array substrate according to the present invention. When a source-drain voltage (Vds) of about 1 V is applied and the gate-source voltage (Vgs) is varied within a range of −5V to 20V, the mobility of the electric charge in the TFT is measured. When the TFT turns on by applying the gate-source voltage (Vgs) of about 10V to 15V, the mobility of the electric charge in the related art TFT is about 0.4 cm 2 /Vs (curve (1)), while the mobility of the electric charge in the TFT according to the present invention is over 1.1 cm 2 /Vs (curve (2)). Accordingly, the mobility of the electric charge in the TFT according to the present invention is improved. 
         [0071]      FIG. 9  is a graph showing a drain-source current depending on a gate-source voltage in a TFT of an array substrate according to an embodiment of the present invention. In  FIG. 9 , the curve (1) and (2) show a drain-source current (Ids) in a TFT of the related art array substrate measured in a light irradiating condition and a light non-irradiating condition, respectively. The intensity of the light is about 400 lux. The curve (3) and (4) show a drain-source current (Ids) in a TFT of the array substrate according to the present invention measured in a light irradiating condition and a light non-irradiating condition, respectively. In the TFT of the array substrate according to the present invention, the active layer has a thickness of about 300 angstroms and the ohmic contact layer has a thickness of about 100 angstroms. When a drain-source voltage (Vds) of about 1 V is applied and the gate-source voltage (Vgs) is varied within a range of −20V to 20V, the drain-source current (Ids) in the curve (3) and (4) is smaller than that in the curve (1) and (2). Namely, a photo leakage current problem in the TFT of the array substrate according to the present invention is relieved. 
         [0072]    It will be apparent to those skilled in the art that various modifications and variations can be made in the array substrate for the LCD device and the method of fabricating the same of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.