Abstract:
A voltage level shifter. The voltage level shifter comprises a shifter unit and a controller. The shifter unit outputs a third signal according to a first signal and a second signal. When the first signal remains at a first level a current path is formed in the shifter unit. The controller is coupled to the shifter unit and stops the current path when the first signal remains at the first level.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a voltage level shifter, and in particular to a voltage level shifter for a liquid crystal display to reduce power consumption when the level of an input signal is switched.  
         [0003]     2. Description of the Related Art  
         [0004]      FIG. 1  shows a schematic diagram of a conventional liquid crystal display system (hereinafter, referred to as an “LCD system”). The LCD system comprises a display area  10 , a gate driver  11 , a data driver  12 , a voltage level shifter  13 , and a timing controller  14 . The voltage level shifter  13  receives low-level timing signals from the timing controller  14 . In order to allow back-end components to correctly read the timing signals, the voltage level shifter  13  raises levels of the timing signals. Then, the raised timing signals are output from the voltage level shifter  13 . According to the raised timing signals, the gate driver  11  and the scan driver  12  are driven to display images in the display area  10 .  
         [0005]     Generally, there are two circuit types for voltage level shifters as shown in  FIG. 2  and  FIG. 3 . The major distinction is the location at which an input signal is input into each of the two circuit types for level shifters. Referring to the voltage level shifter  20  of  FIG. 2 , an input signal Vin 20  is input to a gate of a NMOS transistor N 20 , and an input signal XVin 20 , inverse to the input signal Vin 20 , is input to a gate of a NMOS transistor N 21 . Since a operational time of the voltage level shifter  20  exceeds that of the voltage level shifter  30 , the voltage level shifter  30  is always used to shift levels of signals.  
         [0006]     Referring to the voltage level shifter  30  of  FIG. 3 , an input signal Vin 30  is input to a source of a NMOS transistor N 30 , and an input signal XVin 30 , inverse to the input signal Vin 30 , is input to a source of a NMOS transistor N 31 . In the level shifter  3 , sources of the PMOS transistors P 30  and P 31  are coupled to a voltage source VDD 30  having a high voltage level. Since gates of the transistors N 30  and N 31  are both coupled to the voltage source VDD 30 , the transistors N 30  and N 31  remain turned on. When the input signal Vin 30  remains at a low voltage level while input signal XVin 30  remains at a high voltage level, a PMOS transistor P 30  is turned off and a PMOS transistor P 31  is turned on.  
         [0007]     At this time, because a voltage level of the voltage source VDD 30  is not equal to that of the input signal XVin 30 , a direct current path is formed between the sources of the PMOS transistor P 31  and the NMOS transistor N 31 . The direct current path increases power consumption of the LCD system and reduces thin film transistors within the display area  10 .  
       SUMMARY OF THE INVENTION  
       [0008]     Accordingly, an object of the present invention is to provide a voltage level shifter for liquid crystal display to reduce power consumption when the voltage level shifter switches a level of an input signal.  
         [0009]     According to the object described above, the present invention provides a voltage level shifter comprising a shifter unit and a controller. The shifter unit outputs a third signal according to a first signal and a second signal. When the first signal remains at a first level a current path is formed in the shifter unit. The controller is coupled to the shifter unit and stops the current path when the first signal remains at the first level.  
         [0010]     According to the object described above, the present invention further provides a voltage level shifter. The voltage level shifter comprises a shifting unit and a control unit. The shifting unit has a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor. The first NMOS transistor is coupled to the first transistor between a first voltage source and a first node. The second NMOS transistor is coupled to the second PMOS transistor between the first voltage and a second node. In addition, the first node and the second node are respectively coupled to a gate of the second PMOS transistor and a gate of the first PMOS transistor, and a gate of the first NMOS transistor and a gate of the NMOS second transistor are coupled to the first voltage source.  
         [0011]     The control unit has a first switch, a second switch, and a third switch. The first switch has a first control terminal, a first input terminal coupled to a noninverting input terminal, and a first output terminal coupled to the first node. The second switch has a second control terminal, a second input terminal coupled to an inverting input terminal, and a second output terminal coupled to the second node. The third switch has a third control terminal, a third input terminal coupled to the first voltage source, and a third output coupled the first node and the second node. The first control terminal, the second control terminal, and the third control terminal receive an enable signal. When the enable signal is at a first level, the first switch and the second switch are turned on, and the third switch turned off. Then a first signal and a second signal, complementary to each other and inputted from the noninverting input terminal and the inverting terminal, are correspondingly transmitted to the first node and the second node to be transferred in voltage by the shifting unit.  
         [0012]     When the enable signal is at a second level, the first switch and the second switch are turned off, and the third switch turned on. Then a voltage of the first voltage source is transmitted to the first node and the second node. Thus, after the first signal is switched form a third level to a fourth level, there is no direct current path between the first voltage source and the noninverting input terminal or between the first voltage source and the inverting input terminal.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0014]      FIG. 1  shows a schematic diagram of a conventional liquid crystal display system.  
         [0015]      FIGS. 2 and 3  show a conventional voltage level shifter.  
         [0016]      FIG. 4  shows one operating example of a voltage level shifter according to the present invention.  
         [0017]      FIG. 5  is a block diagram of a voltage level shifter and a pulse generator within a gate driver in the conventional liquid crystal display system.  
         [0018]      FIG. 6  is a timing chart of pulse signals generated by the pulse generator of  FIG. 5 .  
         [0019]      FIG. 7  shows an other operating example of the voltage level shifter according to the present invention.  
         [0020]      FIG. 8  is a timing chart of the voltage level shifter of  FIG. 7 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]      FIG. 4  shows one operating example of a voltage level shifter according to the present invention. The voltage level shifter comprises a level shifting unit  40  and a control unit  41 . The level shifting unit  40  comprises NMOS transistors N 40  and N 41 , PMOS transistors P 40  and P 41 , and an inverter T 40 . A gate of the NMOS transistor N 40  is coupled to a voltage source VDD 40  having a high-level voltage, and a source of the NMOS transistor N 40  is coupled to a node NO 1 . A gate of the NMOS transistor N 41  is coupled to the voltage source VDD 40 , and a source of the NMOS transistor N 41  is coupled to a node NO 2 . A gate of the PMOS transistor P 40  is coupled to the node NO 2 , a source of the transistor P 40  is coupled to the voltage source VDD 40 , and a drain of the transistor P 40  is coupled to a drain of the NMOS transistor N 40 . A gate of the PMOS transistor P 41  is coupled to the node NO 1 , a source of the transistor P 41  is coupled to the voltage source VDD 40 , and a drain of the transistor P 41  is coupled to a drain of the NMOS transistor N 41 . An input terminal of the inverter T 40  is coupled to the drains of the NMOS transistor N 41  and the PMOS transistor P 41 .  
         [0022]     The control unit  41  has NMOS transistors N 42  and N 43 , and PMOS transistor P 42  and P 43 . A gate of the NMOS transistor N 42  receives an enabling signal SB 40 , a drain of the NMOS transistor N 42  is coupled to the node NO 01 , and a source of the NMOS transistor N 42  receives an input signal Vin 40 . A gate of the NMOS transistor N 43  receives the enabling signal SB 40 , a drain of the NMOS transistor N 43  is coupled to the node NO 2 , and a source of the NMOS transistor N 43  receives an input signal XVin 40 . A gate of the PMOS transistor P 42  receives the enabling signal SB 40 , a source of the PMOS transistor P 42  is coupled to the node NO 01 , and a drain of the PMOS transistor P 42  is coupled to the voltage source VDD 40 . A gate of the PMOS transistor P 43  receives the enabling signal SB 40 , a source of the PMOS transistor P 43  is coupled to the node NO 02 , and a drain of the PMOS transistor P 43  is coupled to the voltage source VDD 40 . In addition, the input signal Vin 40  and the input signal XVin 40  are opposite to each other.  
         [0023]     When the input signal Vout 41  remains at a high voltage level, a voltage level of the enabling signal SB 40  is high. The PMOS transistors P 42  and P 43  are turned off, and the NMOS transistors N 42  and N 43  are turned on. At this time, the input signal Vin 40  is input to the source of the NMOS transistor N 40  when the input signal XVin 40  is input to the source of the NMOS transistor N 41 . Moreover, the PMOS transistor P 40  is turned on, and the PMOS transistor P 41  turned off. Because gates of the NMOS transistors N 40  and N 41  are coupled to the voltage source VDD 40 , the NMOS transistors N 40  and N 41  remain turned on. According to the above operations of the transistors, a voltage level of the input terminal of the inverter T 40  is low. Then, the inverter T 40  outputs an output signal Vout 40  whose voltage level is high. When that the input signal Vout 40  remains at the high voltage level, the shifting unit  40  performs normal operation.  
         [0024]     When the input signal Vin 40  remains at a low voltage level, the voltage level of the enabling signal SB 40  is low. The PMOS transistors P 42  and P 43  are turned on, and the NMOS transistors N 42  and N 43  are turned off. At this time, voltage levels of sources of the NMOS transistors N 40  and N 41  are same as those of the voltage source VDD 40 . That is, voltage levels of sources of the NMOS transistors N 40  and N 41  are high. The PMOS transistors P 40  and P 41  are turned off. According to the above operations of the transistors, the voltage level of the input terminal of the inverter T 40  is high. Then, the inverter T 40  outputs the output signal Vout 40  whose voltage level is low. When the input signal Vin 40  remains at the low voltage level, the NMOS transistor N 41  remains turned on; however, the PMOS transistor P 40  is turned off to cut off the direct current path, for decreasing power consumption according to the control of the enable signal VS 40 . In addition, since a signal of the input terminal of the inverter T 40  is high voltage level, the output signal Vout 40  having low voltage level is output from the output terminal of the inverter T 40 . The voltage level of the output signal Vout 40  is adjusted by the inverter T 40  to carry out the operation of the voltage level shifter.  
         [0025]     In the embodiment of the present invention, the enabling signal can be generated according to a pulse generating unit. Referring to  FIG. 5 , a conventional gate driver comprises the pulse generating unit  50 . The pulse generating unit  50  generates a plurality of pulses, when a voltage level shifter  51  outputs a driving signal to the pulse generating unit  50  according to an input signal Vin 50 .  FIG. 6  is a timing chart for generating pulses by the pulse generating unit  50 . When a voltage level of the input signal Vin 50  is high, the pulse generating unit  50  starts to sequentially generate N pulses P 5   1  to P 5 N. When pulses P 5   1  to P 5 N are generated, the voltage level of the input signal is changed from high to low. The voltage level of the input signal Vin 50  remains low and is changed to high until the pulse P 5 N is generated. Then the pulse generating unit  50  generates N pulses again.  
         [0026]      FIG. 7  shows an other operating example of the voltage level shifter according to the present invention. The voltage level shifter comprises an enable signal generating unit  72  and a pulse generating unit  73  in addition to a shifting unit  70  and a control unit  71 . Circuit structures of the shifting unit  70  and the control unit  71  are shown in  FIG. 4 . The enable signal generating unit  72  receives the 1st pulse and the M-th pulse from the pulse generating unit  73 . After an input signal Vin 70 , whose voltage level is high, is transformed to a output signal Vout 70 , for driving the pulse generating unit  73  to generate the first pulse, the voltage of the input signal Vin 70  becomes low. The voltage level of the input signal Vin 70  remains low and is changed to high when the M-th pulse is generated. Therefore, according to the 1st pulse and the M-th pulse, the enable signal generating unit  72  can detect the voltage level of the input signal Vin 70  and determines a voltage level of the enabling signal VB 70 .  
         [0027]     Referring to the  FIG. 8 , the voltage level of the input signal Vin 70  is high, driving the pulse generating unit  73  to generate M pulses P 7   1  to P 7 M. Then, after driving the pulse generating unit  73 , the voltage level of the input signal Vin 70  is immediately changed to low. For the enabling signal VB 70 , when a voltage level of the pulse P 7   1  is changed from high to low, the level of the enabling signal VB 70  is changed to low. The voltage level of the enabling signal VB 70  remains low, and is changed to high when a voltage level of the pulse P 7 M is changed from low to high.  
         [0028]     As described above, when the voltage level of the input signal Vin 70  is low, the enabling signal generator  72  outputs the enabling signal VB 70 , at the low voltage level according to the pulse P 7   1 . After the control unit  71  receives the enabling signal VB 70 , the operation of the control unit  71  is the same as the described above. Thus, when the input signal remains on the low voltage level, the direct current path in the conventional technology is cut off to decrease power consumption.  
         [0029]     In addition, when the voltage level of the input signal Vin 70  is low, the enable signal generating unit  72  outputs the enabling signal VB 70 , at the low voltage level according to the pulse P 7 M. When receiving the enabling signal VB 70 , the control unit  71  operates normally.  
         [0030]     In the embodiment of the present invention, while the voltage level of the voltage of the enabling signal is changed according to the falling edges of the pulses P 7   1  and P 7 M, the application is not limited thereto. The voltage of the enabling signal can be changed according to the rising edges of the pulses P 7   1  and P 7 M. The number of pulses generated by the pulse generator  73  is determined according to requirements of the system.  
         [0031]     Moreover, in some applications, the enable signal VB 70  can be provided from external circuits instead of the enabling signal generator  72 . In others, the enabling signal generator  72  can directly generates the enable signal VB 70  without generating the enable signal VB 70  according to the pulses P 7   1  and P 7 M.  
         [0032]     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.