Abstract:
A method and circuit is presented for generating a random bit stream based on thermal noise of a Complementary Metal Oxide Semiconductor (CMOS) device. A circuit implementing the invention preferably includes at least a pair of identically implemented thermal noise generators whose outputs feed a differential amplifier. The differential amplifier measures and amplifies the difference between the noise signals. A sampling circuit compares the difference with a threshold value that is selected to track with process/voltage/temperature variations of the noise generator circuits to output a binary bit having a bit value determined according to the polarity of the noise difference signal relative to the threshold value. The sampling circuit may be clocked to generate a random bit stream.

Description:
FIELD OF THE INVENTION 
     The present invention pertains generally to random number generation, and more particularly to a method and circuit for generating a random bit stream by amplification of thermal noise in a CMOS process. 
     BACKGROUND OF THE INVENTION 
     Random number generation is an important aspect of many digital and electronic applications. For example, in the field of cryptography, random number generation is key to encryption algorithms. A random bit stream is a sequence of binary signals lacking discernible patterns or repetition over time. 
     In electrical circuitry, a random bit stream may be generated from a source that naturally exhibits random characteristics. For example, thermal noise on a CMOS device in the frequency range between 100 MHz and 1 GHz is generally known to be efficiently random. 
     However, generating a purely random bit stream based on a physical random phenomenon can be problematic. As known in the art, the mere act of sampling may interfere with the actual randomness of the random physical phenomenon being measured. For example, in order to ensure true randomness, the measurement circuitry cannot introduce any bias into the probability that the measured value will be translated to a binary 0 or a binary 1. For example, if a sampling circuit measures a voltage level of noise at a given moment in time and compares it to a known threshold generated by the sampling circuitry, process/voltage/temperature variations may cause a drift in the threshold value over time, which may skew the sampling circuitry to translate more sampled values to one bit value or the other. Thus, the process is no longer random since there is no longer an equal chance of sampling a “1” or a “0”. 
     Accordingly, a need exists for a technique for generating a purely random bit stream from a physical process. In particular, it would be convenient to generate the purely random bit stream from a naturally occurring randomness source within the circuitry itself. In addition, a need exists for preventing drift from pure randomness over time and across different manufactured circuits due to process/voltage/temperature variation. 
     SUMMARY OF THE INVENTION 
     The present invention is a method and circuit for generating a random bit stream by amplification of thermal noise in a CMOS process. In a preferred embodiment of the invention, the random bit generator is immune to drift from true randomness due to process/voltage/temperature variations. 
     In a preferred embodiment of the invention, a random bit generator circuit includes a pair of identically implemented thermal noise generators whose outputs feed a differential amplifier. The differential amplifier measures and amplifies the difference between the noise signals. A sampling circuit compares the difference with a threshold value that is selected to track with process/voltage/temperature variations of the noise generator circuits to output a binary bit having a bit value determined according to the polarity of the noise difference signal relative to the threshold value. The sampling circuit may be clocked to generate a random bit stream. 
     In a preferred embodiment, differential techniques are applied to ensure that all the signals in the circuit track one another with respect to process/voltage/temperature variation. These techniques prevent signal bias from being introduced into the measurement circuitry to thereby ensure a purely random bit stream. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       The invention will be better understood from a reading of the following detailed description taken in conjunction with the drawing in which like reference designators are used to designate like elements, and in which: 
         FIG. 1  is a block diagram of a random bit generator in accordance with the principles of the invention; 
         FIG. 2  is a schematic block diagram of one embodiment of a random bit generator implemented in accordance with the principles of the invention; 
         FIG. 3  is a schematic diagram of a preferred embodiment of a random bit generator implemented in accordance with the principles of the invention; 
         FIG. 4  is a timing diagram illustrating several example signals of the random bit generator of  FIG. 3 ; and 
         FIG. 5  is an operational flow diagram illustrating the method of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     A novel method and circuit for generating a random bit stream based on thermal noise in a CMOS process is described in detail hereinafter. Although the invention is described in terms of specific illustrative embodiments, it is to be understood that the embodiments described herein are by way of example only and that the scope of the invention is not intended to be limited thereby. 
     Turning now to the invention,  FIG. 1  is a block diagram of a random bit generator  1  implemented in accordance with the principles of the invention. As illustrated, the random bit generator  1  includes a thermal noise generator  10 , an amplifier  20 , and a sampler  30 . The noise generator  10  preferably generates a noise signal NOISE representative of thermal noise on a CMOS device. Because thermal noise is generally on the order of several millivolts, the noise signal NOISE must be amplified by amplifier  20  in order to accurately sample it. The sampler  30  samples the amplified signal DIFF and generates a bit stream based on the voltage level of the sampled signal. 
       FIG. 2  is a schematic block diagram of one embodiment of the invention. It will be appreciated by those skilled in the art that variations in manufacturing process may cause the DC bias point of the noise generator circuit  10   a  to drift from its optimal level—that is, the DC bias point may vary to be somewhere between VDD/2+/−Δ. As known in the art, introducing bias above or below the optimal operating point of the inverter will ultimately interfere with the randomness of the random bit stream data. Accordingly, in the preferred embodiment of the invention, the bias is eliminated by sampling the difference of two identical noise generator circuits. Thus, in the embodiment of  FIG. 2 , the random bit generator includes at least a pair of identical noise generator circuits  10   a ,  10   b . Each noise generator  10   a  comprises an inverter  11   a  with a conducting feedback transistor  16   a  connected between the inverter output  15   a  and the inverter input  14   a.    
     Each inverter  11   a ,  11   b  comprises a PFET  12   a ,  12   b  and an NFET  13   a ,  13   b . Each PFET  12   a ,  12   b  is source-coupled to a high voltage source VDD, gate-coupled to the inverter input  14   a ,  14   b , and drain coupled to the inverter output  15   a ,  15   b . Likewise, each NFET  13   a ,  13   b  is source-coupled to a low voltage source (ground), gate-coupled to the inverter input  14   a ,  14   b , and drain coupled to the inverter output  15   a ,  15   b . Since the identical noise generator circuits  10   a ,  10   b  are manufactured in the same process, they will have identical DC bias points (VDD/2+/−Δ); however, since the thermal noise generated on each feedback FETs  16   a ,  16   b  is independent, the feedback FET  16   a ,  16   b  will generate different AC (noise) components on the output signal NOISEa, NOISEb. 
     In this embodiment, the amplifier  20  comprises a differential amplifier  22  which measures and amplifies the difference of the AC noise components of the output signal NOISEa, NOISEb. Thus, the output DIFF of the differential amplifier  22  represents the amplified difference of the noise components of noise generator output signals NOISEa, NOISEb. 
     The sampling circuit  30  receives the amplified signal DIFF, a DC threshold voltage VREF, and a clock signal CK. On the rising edge of the clock signal CK, the sampling circuit  30  compares the amplifier output signal DIFF to the DC threshold VREF, and outputs either a logical 0 or a logical 1 depending on whether the amplifier output signal DIFF is greater than or less than the DC threshold VREF. The comparison is performed by a comparator  32  on every rising edge of the clock signal CK and the output of the sampling circuit  30  is held it until next rising edge. 
     As known in the art, CMOS processes are subject to manufacturing process variation. Manufacturing process variation results in size variation between PFETs and NFETs, which results in variance in performance characteristics of the devices. Performance variation between the PFETs and NFETs in a CMOS circuit can be problematic in the realm of random bit generation because even a small variance away from the optimal value of a signal can bias the circuit such that there is a higher chance of generating one bit value than the other (e.g., more logical 1s than logical 0s, or vice versa). 
       FIG. 3  illustrates a preferred embodiment of a random bit generator  100  constructed in accordance with the principles of the invention and which minimizes signal bias as much as possible. As illustrated, the random bit generator  100  includes two pairs of noise generator circuits  110   a ,  110   b ,  110   c , and  110   d . Each noise generator circuit  110   a ,  110   b ,  110   c , and  110   d  comprises a complementary CMOS inverter  111   a ,  111   b ,  111   c , and  111   d  and a feedback FET  116   a ,  116   b ,  116   c ,  116   d  providing conductance between the output  115   a ,  115   b ,  115   c ,  115   d , and input  114   a ,  114   b ,  114   c ,  114   d  of the inverter  111   a ,  111   b ,  111   c , and  111   d . In particular, each inverter  111   a ,  111   b ,  111   c , and  111   d  is formed with a PFET  112   a ,  112   b ,  112   c , and  112   d  source-coupled to a high voltage source, drain-coupled to an inverter output node  115   a ,  115   b ,  115   c , and  115   d , and gate-coupled to an inverter input node  114   a ,  114   b ,  114   c ,  114   d , and an NFET  113   a ,  113   b ,  113   c ,  113   d  source-coupled to a low voltage source, drain-coupled to the inverter output node  115   a ,  115   b ,  115   c ,  115   d , and gate coupled to the inverter input node  114   a ,  114   b ,  114   c ,  114   d . In the illustrative embodiment, the feedback FET  116   a ,  116   b ,  116   c ,  116   d  comprises a PFET source-connected to the inverter output node  1115   a ,  115   b ,  115   c ,  115   d , drain-connected to the inverter input node  114   a ,  114   b ,  114   c ,  114   d , and gate-connected to the low voltage source. 
     In the ideal case, the output  115   a ,  115   b ,  115   c ,  115   d  and input  114   a ,  114   b ,  114   c ,  114   d  of the inverter  111   a ,  111   b ,  111   c , and  111   d  are both driven to a DC voltage level of VDD/2. However, thermal noise generated in the feedback FET  116   a ,  116   b ,  116   c ,  116   d  causes current fluctuation between the output  115   a ,  115   b ,  115   c ,  115   d  and input  114   a ,  114   b ,  114   c ,  114   d . The noise signal NOISEa, NOISEb, NOISEc, NOISEd may be measured on the output  115   a ,  115   b ,  115   c ,  115   d  of the inverter  111   a ,  111   b ,  111   c , and  111   d.    
     The output signal NOISEa, NOISEb, NOISEc, NOISEd on output  115   a ,  115   b ,  115   c ,  115   d  comprises a DC component having a DC bias level of approximately VDD/2, as just described, and an AC component representing the thermal noise of the feedback FET  116   a ,  116   b ,  116   c ,  116   d.    FIG. 4  illustrates example noise signals NOISEa, NOISEb, NOISEc, NOISEd. 
     It will be appreciated by those skilled in the art that variations in manufacturing process may cause the DC bias point of the noise generator circuits  110   a ,  110   b ,  110   c ,  110   d  to vary. In other words, the DC bias point may be biased to VDD/2+/−Δ. As known in the art, introducing bias above or below the optimal operating point of the inverter  111   a ,  111   b ,  111   c ,  111   d  will interfere with the randomness of the data. Accordingly, in the preferred embodiment of the invention, the randomness is achieved by sampling the difference of two identical noise generator circuits. Thus, the random bit generator of the invention includes at least a pair of identical noise generator circuits  110   a ,  110   b . Since the identical noise generator circuits  110   a ,  110   b  are manufactured in the same process, they will have identical DC bias points (VDD/2+/−Δ); however, since the thermal noise generated on each feedback FET  116   a ,  116   b  is independent, the feedback FETs  116   a ,  116   b  will generate different AC (noise) components on the respective output signal NOISEa, NOISEb. 
     Typical thermal noise will generate an AC noise signal on the order of 1 to 2 millivolts. The noise signal is therefore very small with respect to the level of the power supply of VDD (typically 3–5 volts). Because thermal noise is efficiently chaotic, the variation of the noise signal NOISEa, NOISEb, NOISEc, NOISEd on the output  115   a ,  115   b ,  115   c ,  115   d  of the inverter  111   a ,  111   b ,  111   c , and  111   d  is, for all practical purposes, random. 
     As just described the output signal NOISEa, NOISEb, NOISEc, NOISEd comprises a large DC voltage component (approximately VDD/2) with a very small AC oscillation around the DC bias level. Because the AC noise component of the output signal NOISEa, NOISEb, NOISEc, NOISEd is so small, it must be measured and amplified to provide a useful measure of randomness. Accordingly, the preferred embodiment of the invention includes a pair of differential amplifiers  120   a ,  120   b  which each receive the output signal NOISEa, NOISEb, NOISEc, NOISEd from the noise generator circuit  110   a ,  110   b ,  110   c , and  110   d  at respective differential amplifier input nodes  121   a ,  121   a′ ,  121   b ,  121   b′.    
     Each differential amplifier  120   a ,  120   b  is formed using a pair of PFETs  122   a ,  122   a′ , and  122   b ,  122   b′  source-coupled to a biased node  128   a ,  128   b  and drain-coupled to differential output nodes  125   a ,  125   a′ , and  125   b ,  125   b′ , and a pair of complementary NFETs  126   a ,  126   a′  and  126   b ,  126   b′  source-coupled to a low voltage source (e.g., ground) and drain-coupled to the differential output nodes  125   a ,  125   a′ , and  125   b ,  125   b′ . The gates of PFETs  122   a ,  122   a′ ,  122   b ,  122   b′  are driven by the output signal NOISEa, NOISEb, NOISEc, NOISEd from respective noise generator circuits  110   a ,  110   b ,  110   c ,  110   d . Since the output signal NOISEa, NOISEb, NOISEc, NOISEd is DC-biased at approximately VDD/2, the PFETs  122   a ,  122   a′ , and  122   b ,  122   b′  are conducting but not saturated. Accordingly, the AC noise component of the output signal NOISEa, NOISEb, NOISEc, NOISEd causes more or less current to flow to the respective differential amplifier output nodes  125   a ,  125   a′ , and  125   b ,  125   b′  depending on whether the AC noise component of the output signal NOISEa, NOISEb, NOISEc, NOISEd is below or above the DC bias point (i.e., VDD/2±Δ). At the same time, one leg of the differential amplifier  120   a ,  120   b  has its differential amplifier output node  125   a ,  125   b′  connected to drive the gates of NFETs  126   a ,  126   a′ ,  126   b,    126   b′ . Accordingly, the AC noise component of the output signal NOISEa, NOISEb, NOISEc, NOISEd causes more or less current to flow through NFETs  126   a ,  126   a′ ,  126   b ,  126   b′  to the respective differential amplifier output nodes  125   a ,  125   a′ ,  125   b ,  125   b′  depending on whether the AC noise component of the output signal NOISEa, NOISEb, NOISEc, NOISEd is above or below the DC bias point (i.e., VDD/2+/−Δ). 
     Thus, the differential amplifier  120   a ,  120   b  generates on output node  125   a′ ,  125   b  a signal DIFFa, DIFFb which represents the amplified difference of the noise components of noise generator output signals NOISEa, NOISEb, and NOISEc, NOISEd. In the preferred embodiment, the gain of each differential amplifier  120   a ,  120   b  is approximately 20. This provides a variation on the order of a couple of hundred millivolts on the differential amplifier output signal DIFFa, DIFFb, which is large enough to sample. 
     The random bit generator  100  also includes a sampling circuit  130 . The sampling circuit  130  receives a clock signal CK. On the rising edge of the clock signal CK, the sampling circuit  130  compares the differential amplifier output signal DIFFa, DIFFb to a DC threshold (VDD/2+/−Δ) and generates a signal indicating whether the differential amplifier output signal DIFFa, DIFFb is greater than or less than the threshold. The comparison is performed on every rising edge of the clock signal CK and the result is held it until next rising edge. 
     In order to ensure pure randomness in the process, it is important to ensure that the threshold value is unbiased such that the differential amplifier output signal DIFFa, DIFFb will on average spend half the time greater and half the time less than the DC threshold. Stated another way, the circuit must be constructed such that there is an equal chance that on rising edge of clock signal CK the differential amplifier output signal DIFFa, DIFFb will be greater and less than the chosen DC threshold value. 
     In one embodiment, for example in  FIG. 2 , the DC threshold value VREF for the comparator  32  is generated by passing the differential amplifier output signal DIFF through a low pass filter to extract the DC component of the signal. In this embodiment, only the first half of the circuit need be implemented—that is, the random bit generator is implemented with dual noise generator circuits  10   a ,  10   b , differential amplifier  22 , and a sampler  30  which filters out the DC component of the differential amplifier output signal DIFF and uses the extracted DC component as the threshold value VREF input to the sampling circuit  30 . 
     Alternatively, as shown in the embodiment of  FIG. 3 , the random bit generator  100  mirrors the noise generator circuits  110   a ,  110   b  and differential amplifier  120   a  with noise generator circuits  110   c ,  110   d  and differential amplifier  120   b  to generate a second differential amplifier output signal DIFFb. In theory, if implemented identically, the second differential amplifier output signal DIFFb will have same DC component value as the first differential amplifier output signal DIFFa. However, since the noise difference component of the second differential amplifier output signal DIFFb is independent of the noise difference component of the first differential amplifier output signal DIFFa, the amplitude of the difference between the two noise components of the differential amplifier output signals DIFFa and DIFFb is potentially twice as large as compared to measuring a single differential amplifier output signal DIFFa against a DC reference threshold (as in the embodiment of  FIG. 2 ). This allows simpler measurement using smaller amplifier gains. 
     In the preferred embodiment, the sampling circuit  130  is a clocked comparator circuit formed using a pair of PFETs  132   a ,  132   b  each source-coupled to the high voltage source VDD and drain-coupled to respective comparator output nodes  133   a ,  133   b , and a pair of NFETs  134   a ,  134   b  each source-coupled to the low voltage source (ground) and drain-coupled to the respective comparator output nodes  133   a ,  133   b . The gate of each PFET  132   a ,  132   b  is cross-coupled to the opposite comparator output node  133   b,    133   a , and the gate of each NFET  134   a ,  134   b  is connected to receive respective differential amplifier output signals DIFFa, DIFFb. A PFET  136  is coupled between the comparator output nodes  133   a ,  133   b  to provide either conductive coupling or isolation between the comparator output nodes  133   a ,  133   b . The gate of the PFET  136  is driven by a clock signal CK. 
     In operation, when the clock signal CK is low, PFET  136  conducts in the non-saturated region such that the comparator output nodes  133   a ,  133   b  have identical voltage levels (approximately VDD). When the clock signal goes high, PFET  136  is placed in the cutoff region, thereby isolating the comparator output nodes  133   a ,  133   b  from one another. Simultaneously, NFET  137  turns on to pull the source of NFETs  134   a ,  134   b  to ground. When this happens, charge beings to be pulled off of both comparator output nodes  133   a  and  133   b . If the differential amplifier output signal DIFFa at the gate of NFET  134   a  has a higher voltage than the differential amplifier output signal DIFFb at the gate of NFET  134   b  on the rising edge of the clock signal CK, comparator output node  133   a  will be pulled down faster than comparator output node  133   b , which eventually will turn on PFET  132   b  first, which pulls comparator output node  133   a  high and prevents comparator output node  133   b  from being pulled low. If instead the differential amplifier output signal DIFFb at the gate of NFET  134   b  has a higher voltage than the differential amplifier output signal DIFFa at the gate of NFET  134   a  on the rising edge of the clock signal CK, comparator output node  133   b  will be pulled down faster than comparator output node  133   a , which eventually will turn on PFET  132   a  first, which pulls comparator output node  133   b  high and prevents comparator output node  133   a  from being pulled low. 
     Accordingly, the sampling circuit  130  samples the difference between DIFFa and DIFFb on the rising edge of the clock signal CK and turns the polarity of the difference into a logical value. The logical value is then latched and buffered to the outputs by a latching and buffering circuit  140 . Latching and buffering circuit  140  comprises a pair of NOR gates  141   a ,  141   b , electrically connected to the output of a respective one of a pair of inverters  142   a ,  142   b . The output of each NOR gate  141   a ,  141   b , is cross-coupled to one of the inputs of the other NOR gate  141   b ,  141   a . The comparator output node  133   a  feeds inverter  142   a , and the comparator output node  133   b  feeds inverter  142   b.    
     Even in the face of using the differential amplifier circuits  120   a  and  120   b , local process variations may cause a bias on the DC component of the differential amplifier output signal so as to not generate a statistically random bit stream. In other words, if the DC component of the differential amplifier output signals DIFFa and DIFFb are slightly skewed from one another due to local manufacturing process variations in the CMOS components, the random bit stream might not be evenly weighted such that there exists an equal chance of the amplified noise difference falling above or below the threshold. 
     Accordingly, in the preferred embodiment, the random bit generator  100  includes a DC bias point optimization circuit  150 . DC bias point optimization circuit  150  includes a PFET  151  and an NFET  152  which generate a reference bias voltage V_REF on reference bias node  153  (to VDD/2 approximately). A pair of transfer PFETs  154   a ,  154   b  operate as high impedance resistors that transfer the reference voltage VREF to the comparator input nodes  131  a,  131   b . Capacitors  155   a  and  155   b  are preferably metal coupling capacitors formed from interconnect metal. The FETs  151 ,  152 ,  154   a ,  154   b  establish an identical non-skewed DC signal component (at VREF) at the input of comparator input nodes  131   a ,  131   b.  The coupling capacitors  155   a ,  155   b  operate as a high pass filter to pass the noise (AC) component and filter the DC component of the differential amplifier output signals DIFFa, DIFFb. Accordingly, the inputs to  131   a ,  131   b  the sampling circuit  130  are driven by the non-skewed DC signal component (at VREF) combined with the noise (AC) components of the differential amplifier output signals DIFFa, DIFFb. This ensures that no skew exists between the DC components of the differential amplifier output signals DIFFa, DIFFb. Accordingly, the AC noise components of the differential amplifier output signals DIFFa, DIFFb reach the inputs  131   a ,  131   b  of the sampling circuit  130  virtually undiminished, while the DC bias is determined by one source VREF. 
     It will be appreciated by those skilled in the art that symmetry plays an important part in removing signal biases within the circuit which may interfere with the generation of a truly random bit stream from a CMOS process. In the preferred embodiment, all components are therefore laid out symmetrically and call for differential techniques. 
     Thermal noise has a frequency spectrum that is not perfectly ideal for generating random numbers. The low frequency components are too large relative to the high frequency components. In order to ensure the prevention of long streams of 1s and 0s (which would result from excessive low frequency components), the circuit should roll off the frequency response of the noise source (i.e., run it through a high pass filter) such that the frequency components of the noise source are significantly higher than the sampling clock (or strobe). In the preferred embodiment, this is accomplished by carefully sizing the feedback transistor  116   a ,  116   b ,  116   c ,  116   d  relative to the size of the inverter ( 111   a ,  111   b ,  111   c ,  111   d ) that it is biasing. Most of the noise energy is between 100 MHz and 1 GHz. The low frequency noise (often called “shot noise”) is filtered out by sizing the inverter FETs with relatively low-impedance transistors, which are preferably sized to filter out noise below approximately 100 MHz. 
     The determining the sizing of the FETs in the noise generator circuits  110   a ,  110   b ,  110   c ,  110   d , the feedback transistor  116   a ,  116   b ,  116   c ,  116   d  must be sized long enough so that there is a slight delay before the inverter input  114   a ,  114   b ,  114   c ,  114   d  responds to noise on the inverter output  115   a ,  115   b ,  115   c ,  115   d , thereby filtering out low frequency components. 
     Table 1 lists the FET component sizes for a 0.13 micron process implementation of the preferred embodiment of  FIG. 3 . 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                 Length 
                 Width 
                 Capacitance 
               
               
                   
                 Component 
                 (in microns) 
                 (in microns) 
                 (in picoFarads) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 112a 
                 1 
                 .24 
                   
               
               
                   
                 112b 
                 1 
                 .24 
               
               
                   
                 112c 
                 1 
                 .24 
               
               
                   
                 112d 
                 1 
                 .24 
               
               
                   
                 113a 
                 1 
                 .24 
               
               
                   
                 113b 
                 1 
                 .24 
               
               
                   
                 113c 
                 1 
                 .24 
               
               
                   
                 113d 
                 1 
                 .24 
               
               
                   
                 116a 
                 .22 
                 .24 
               
               
                   
                 116b 
                 .22 
                 .24 
               
               
                   
                 116c 
                 .22 
                 .24 
               
               
                   
                 116d 
                 .22 
                 .24 
               
               
                   
                 122a 
                 1 
                 16 
               
               
                   
                 122a′ 
                 1 
                 16 
               
               
                   
                 122b 
                 1 
                 16 
               
               
                   
                 122b′ 
                 1 
                 16 
               
               
                   
                 126a 
                 1 
                 8 
               
               
                   
                 126a′ 
                 1 
                 8 
               
               
                   
                 126b 
                 1 
                 8 
               
               
                   
                 126b′ 
                 1 
                 8 
               
               
                   
                 124a 
                 16 
                 .24 
               
               
                   
                 124b 
                 16 
                 .24 
               
               
                   
                 132a 
                 1 
                 2 
               
               
                   
                 132b 
                 1 
                 2 
               
               
                   
                 134a 
                 1 
                 2 
               
               
                   
                 134b 
                 1 
                 2 
               
               
                   
                 136 
                 1 
                 4 
               
               
                   
                 151 
                 .22 
                 .24 
               
               
                   
                 152 
                 .22 
                 .24 
               
               
                   
                 154a 
                 .22 
                 .24 
               
               
                   
                 154b 
                 .22 
                 .24 
               
               
                   
                 155a 
                   
                   
                 &lt;20 
               
               
                   
                 156b 
                   
                   
                 &lt;20 
               
               
                   
                   
               
             
          
         
       
     
       FIG. 4  shows a timing diagram illustrating various signals in the random bit generator of  FIG. 3  which ultimately generate a random bit stream. 
       FIG. 5  is an operational flowchart illustrating the method  200  of the invention. As illustrated, the method of the invention includes: generating  201  a first noise signal representing thermal noise on a first CMOS device, generating  202  a second noise signal representing thermal noise on a second CMOS device, measuring  203  a difference between the first and second noise signals, amplifying  204  the measured difference to generate an amplified difference signal, sampling  205  the amplified difference signal; and generating  206  an output bit having a bit value based on the value of the amplified difference signal. 
     While illustrative and presently preferred embodiments of the invention have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed and that the appended claims are intended to be construed to include such variations except insofar as limited by the prior art.