Abstract:
Embodiments of radio frequency switching systems, modules, and methods with improved high frequency performance are described generally herein where the switching module may include a first switch module coupled in series to a second switch module, and a third switch module coupled between the first and the second module and ground. A controllable element of the second module may have a lower off capacitance than a controllable element of the first module. Other embodiments may be described and claimed.

Description:
CROSS-REFERENCE TO RELATED UTILITY AND PROVISIONAL APPLICATIONS—CLAIMS OF PRIORITY 
     The present application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 61/481,188, filed Apr. 30, 2011. The present application is related to the application set forth above. The application set forth above is hereby incorporated by reference herein as if set forth in full. 
    
    
     TECHNICAL FIELD 
     Various embodiments described herein relate generally to radio frequency switching systems, modules, and methods and particularly with high breakdown voltages. 
     BACKGROUND INFORMATION 
     It may be desirable to switch RF signals having high voltage levels while not distorting high frequencies at a load; the present invention provides a system, method, and apparatus for same. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a signal processing system according to various embodiments. 
         FIG. 2A  is a block diagram of an RF switching module according to various embodiments. 
         FIG. 2B  is a block diagram of another RF switching module according to various embodiments. 
         FIG. 2C  is a block diagram of a further RF switching module according to various embodiments. 
         FIG. 2D  is a block diagram of another RF switching module according to various embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a signal processing system  10  according to various embodiments. As shown in  FIG. 1 , the system  10  includes multiple signal processing modules  20 A,  20 B,  20 C coupled to a common node  50  and an antenna  52 . The antenna  52  may be coupled to the common node  50  and transceive signals with the common node  50 . Each signal processing module  20 A,  20 B,  20 C may receive and process a signal  22 A,  22 B,  22 C to generate the signals  24 A,  24 B, and  24 C, respectively. The processed signals  24 A,  24 B,  24 C may be coupled to the antenna  52  via the common node  50 . 
     In an embodiment each signal processing module  20 A,  20 B, and  20 C may include a radio frequency (RF) switching module  40 A,  40 B,  40 C, respectively. The switching module  40 A,  40 B,  40 C may switch the signal  22 A,  22 B,  22 C to generate the signal  24 A,  24 B,  24 C based on a control signal  28 A,  28 B,  28 C, respectively. 
     A control or bias signal  28 A,  28 B,  28 C may be coupled to a RF switching module  40 A,  40 B,  40 C, respectively. An RF switching module  40 A,  40 B,  40 C may process the signal  22 A,  22 B,  22 C based on the signal  28 A,  28 B,  28 C, respectively. In an embodiment the signal processing modules  20 A,  20 B,  20 C may form a multiple pole switch and each module  20 A,  20 B,  20 C may be a single pole (switch). Further only a single pole of the effective multiple pole switch network or module  10  may be active at any given time to prevent or limit interference between signals  24 A,  24 B,  24 C at the common node  50 . Accordingly when a switching module  40 A,  40 B,  40 C is active, the other two switching modules may be inactive. The inactive switches  40 A,  40 B, or  40 C may produce an off-state capacitance that may result in an increased switch attenuation limiting the switch band width. 
     The inactive switches  40 A,  40 B,  40 C may need to withstand the present of a high voltage signal on their ports (from the input signals  22 A,  22 B, and  22 C) and from the common node  50 . Accordingly the switches  40 A,  40 B,  40 C may be required to have sufficient loading capability. Further the modules or switches  40 A,  40 B,  40 C insertion loss for an input signal  22 A,  22 B,  22 C should be low in an embodiment.  FIG. 2A  is a block diagram of an RF switching module  40 D according to various embodiments. As shown in  FIG. 2A  a switching module  40 D may include one or more controllable elements or modules such as multiple n-type or p-type complementary metal-oxide-semiconductor N-CMOS transistors  42 A to  42 D. Each transistor  42 A to  42 D may be coupled to a control signal  28 A via a resistor  44 A to  44 D. 
     The module  40 A may include multiple transistors to handle large voltage or loads from a signal  26 A,  24 A given each transistor has a breakdown voltage and series coupled transistors may process voltage equal to the sum of the breakdown voltage of each of the series coupled transistors  42 A to  42 D as described in the commonly assigned U.S. Pat. No. 6,804,502 entitled Switch Circuit and Method of Switching Radio Frequency Signals to Mark Burgener et al., which is hereby incorporated by reference for its teachings. The switching module  40 A may introduce capacitance into a node  50  when the switch  40 A is inactive. The capacitance may vary as a function of the transistors  42 A to  42 D. 
       FIG. 2B  is a block diagram of an RF switching module  40 E according to various embodiments. The RF switching module  40 E may include a first switched module  41 A, a second switched module  41 B, and a shunt module  41 C. The first and second switched module  41 A,  41 B may be coupled in series to communicate a signal on port  26 A to port  24 A as a function of a control signal on port  28 A. The shunt module  41 C may be coupled between the first and second switched modules  41 A,  41 B at a node  41 D and to a ground. The shunt module may direct a signal at the node  41 D to ground based on a control signal on the port  29 A. 
     In an embodiment, modules  41 A and  41 B may be active when module  41 C is inactive and module  41 C may be active when modules  41 A and  41 B are inactive. When modules  41 A and  41 B are active and module  41 C is inactive a signal on port  26 A may be communicated to port  24 A (to be communicated to a common node  50  as shown in  FIG. 1 ) and be subject to insertion loss as a function of modules  41 A,  41 B configuration. When the shunt module  41 C is active and switch modules  41 A,  41 B are inactive any signal on node  41 D may be shunted to ground. The switch module  41 B may be required to handle the load of a signal present at port  24 A when inactive. Similarly, the switch module  41 A may be required to handle the load of a signal present at port  26 A when inactive. 
     Any capacitance present in the switch module  41 B due to the transition from an active to inactive state may be communicated on the port or node  24 A. In an embodiment the switch module  41 B may include one or more elements (transistors)  42 A,  42 B where the transistors may be coupled in series (transistor  42 A drain to transistor  42 B source in an embodiment) and their gates coupled to the control port or node  28 A via a resistor  44 A,  44 B, respectively (in an embodiment). In an embodiment the switch element  41 A may include one or more transistors  42 E where the transistor  42 E gate may be coupled to the control port or node  28 A via a resistor  44 C, in an embodiment. 
     In an embodiment the effective off state capacitance of the elements  42 A,  42 B of the switch module  41 B may be configured to be lower than the off state capacitance of the element  42 E of the switch module  41 A. As a consequence the voltage loading of the elements  42 A,  42 B of the switch module  41 B may be lower than the voltage loading of the element  42 E of the switch module  41 A. In an embodiment the modules  41 A,  41 B, and  41 C may be configured to have the same total voltage loading capacity. 
     In an embodiment the on or active resistance of the combined elements  42 A and  42 B of the switch module  41 B may be configured to be higher than the on resistance of the element  42 E of the switch module  41 A. The increased combined on resistance of the elements  42 A,  42 B of module  41 B with lower combined off state capacitance of these elements in conjunction with the lower on resistance of the element  42 E of module  41 A may reduce the insertion loss of a signal communicated from port  26 A to port  24 A when the modules  41 A,  41 B are active. The reduction in insertion loss is the result of a lower total loading capacitance at the common port (node  50  on  FIG. 1 ) from the off state capacitance of multiple switch modules  40 G connected to this common node or antenna port. 
     In an embodiment the shunt module  41 C may also include one or more elements (transistors)  52 A,  52 B where the transistors may be coupled in series (transistor  52 A drain to transistor  52 B source in an embodiment) and their gates coupled to the control port or node  29 A via a resistor  54 A,  54 B, respectively (in an embodiment). In an embodiment the module  41 C and its respective elements  52 A,  52 B may be configured to have a total voltage capacity about equal to the total voltage capacity of the module  41 A and the module  41 B. 
       FIG. 2C  is a block diagram of an RF switching module  40 F according to various embodiments. The RF switching module  40 F may include a first switched module  41 A, a second switched module  41 B, a first shunt module  41 C, and a second shunt module  41 D. Similar to module  40 E the first and the second switched module  41 A,  41 B may be coupled in series to communicate a signal on port  26 A to port  24 A as a function of a control signal on port  28 A. The first shunt module  41 C may be coupled between the first and second switched modules  41 A,  41 B at a node  41 D and to a ground. The first shunt module  41 C may direct a signal at the node  41 D to ground based on a control signal on the port  29 A. The second shunt module  41 D may be coupled between the node  26 A and to a ground. The second shunt module  41 D may direct a signal at the node  26 A to ground based on a control signal on the port  29 B. 
     In an embodiment the first and second shunt modules  41 C,  41 D may be made inactive when the modules  41 A,  41 B are active and made active when the modules  41 A,  41 B are inactive. The second shunt module  41 D may help isolate the switch module  41 A when the module  41 A is inactive. In an embodiment the shunt module  41 D may also include one or more elements (transistors)  62 A,  62 B where the transistors may be coupled in series (transistor  62 A drain to transistor  62 B source in an embodiment) and their gates coupled to the control port or node  29 B via a resistor  64 A,  64 B, respectively. In an embodiment the module  41 D and its respective elements  62 A,  62 B may be configured to have a total voltage capacity about equal to the total voltage capacity of the module  41 A. 
       FIG. 2D  is a block diagram of an RF switching module  40 G according to various embodiments. The RF switching module  40 G may include a first switched module  43 A, a second switched module  43 B, a first shunt module  43 C, and a second shunt module  43 D. Similar to the switch module  40 F the first and the second switched module  43 A,  43 B may be coupled in series to communicate a signal on port  26 A to port  24 A as a function of a control signal on port  28 A. The first shunt module  43 C may be coupled between the first and second switched modules  43 A,  43 B at a node  43 D and to a ground. The first shunt module  43 C may direct a signal at the node  43 D to ground based on a control signal on the port  29 A. The second shunt module  43 D may be coupled between the node  26 A and to a ground. The second shunt module  43 D may direct a signal at the node  26 A to ground based on a control signal on the port  29 B. 
     In an embodiment the first and second shunt modules  43 C,  43 D may be made inactive when the modules  43 A,  43 B are active and made active when the modules  43 A,  43 B are inactive. As shown in  FIG. 2D  the first switch module  43 A may include two transistors  42 E,  42 F coupled in series where their gates are coupled to the control port  28 A via the resistors  44 E,  44 F, respectively. The second switch module  43 B may include four transistors  42 A,  42 B,  42 C,  42 D coupled in series where their gates are coupled to the control port  28 A via the resistors  44 A,  44 B,  44 C,  44 D respectively. The first shunt module  43 C may include four transistors  52 A,  52 B,  52 C,  52 D coupled in series where their gates are coupled to the control port  29 A via the resistors  54 A,  54 B,  54 C,  54 D respectively. Similarly, the second shunt module  43 D may include four transistors  62 A,  62 B,  62 C,  62 D coupled in series where their gates are coupled to the control port  29 B via the resistors  64 A,  64 B,  64 C,  64 D respectively. 
     In an embodiment the effective capacitance of the elements  42 A,  42 B,  42 C,  42 D of the switch module  43 B may be configured to be lower than the capacitance of the elements  42 E,  42 F of the switch module  43 A. As a consequence the voltage loading of the elements  42 A,  42 B,  42 C,  42 D of the switch module  43 B may be lower than the voltage loading of the elements  42 E,  42 F of the switch module  43 A. In an embodiment the modules  43 A,  43 B,  43 C, and  43 D may be configured to have the same total voltage loading capacity 
     In an embodiment the combined on or active resistance of the elements  42 A,  42 B,  42 C,  42 D of the switch module  43 B may be configured to be higher than the combined on resistance of the elements  42 E,  42 F of the switch module  43 A. The increased combined on resistance of the elements  42 A,  42 B,  42 C,  42 D of module  43 B with decreased combined off state capacitance of these elements in conjunction with the lower combined on resistance of the elements  42 E,  42 F of module  43 A y may reduce the insertion loss of a signal communicated from port  26 A to port  24 A when the modules  43 A,  43 B are active. The reduction in insertion loss is the result of a lower total loading capacitance at the common port (node  50  on  FIG. 1 ) from the off state capacitance of the multiple switch modules  40 G connected to this common node or antenna port. 
     In an embodiment the transistors  62 A to  62 D of the shunt module  43 D and  62 A,  62 B of shunt module  41 D may have a width, length of about 18 microns, 0.4 microns and 22 fingers and a resistance of about 40.91 Kohms. The transistors  52 A to  52 D of the shunt module  43 C and transistors  52 A,  52 B of shunt module  41 C may have a width, length of 17.8 microns, 0.4 microns and 56 fingers and a resistance of about 51.65 Kohms. The first switch module  43 A elements  42 E,  42 F and  41 A elements  42 E may have a width, length of 31.2 microns, 0.4 microns and 77 fingers and a resistance of about 58.0 Kohms. The second switch module  43 B elements  42 A,  42 B,  42 C,  42 D and switch module  41 B elements  42 A,  42 B may have a width, length of 17.8 microns, 0.4 microns and 56 fingers and a resistance of about 40.91 Kohms. The resistors  44 A to  44 D,  54 A to  54 D,  64 A to  64 D may have a nominal resistance of about 2.65 K-ohms. 
     The accompanying drawings that form a part hereof show, by way of illustration and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived there-from, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. 
     Such embodiments of the inventive subject matter may be referred to herein individually or collectively by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept, if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. 
     The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted to require more features than are expressly recited in each claim. Rather, inventive subject matter may be found in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.