Abstract:
A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention generally relates to semiconductor devices and methods of fabricating semiconductor devices. More particularly, the present invention relates to a fin-type field effect transistor (FinFET) device, and to a method of making a FinFET device. 
     The down-scaling of semiconductor devices can be observed in various types of field effect transistors. As the miniaturization of such devices has led to electrical and process limitations, techniques have been developed for maintaining and/or achieving desired performance. Among other things, a FinFET device has been developed to maintain and/or achieve improved performance with a gate of reduced dimensions. A FinFET device is described, for example, in U.S. Pat. No. 9,123,744 (Liao et al.). The entire disclosure of Liao et al. is incorporated herein by reference. 
     A major problem with modern electronic devices, including FinFET devices, is current leakage. It is known to incorporate a silicon-on-insulator (SOI) configuration into a semiconductor device to reduce current leakage. A known SOI-configuration device is described, for example, in U.S. Pat. No. 8,395,217 (Cheng et al.). SOI configurations may be costly, however, and they are not readily compatible with the bulk substrate configurations that are now in widespread use. 
     The deficiencies of the prior art devices and methods are overcome to a great extent by the inventions described herein. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, a fin structure for a semiconductor device includes a first semiconductor material, an air gap, and a second semiconductor material. The semiconductor device may be, for example, a FinFET device. The first semiconductor material may be, for example, an epitaxial material grown within a fin recess. The second semiconductor material may be, for example, a substrate material, and the air gap may be located between the first and second semiconductor materials. 
     According to another aspect of the invention, the air gap may have a tubular configuration, with a central axis that is parallel to a direction from a source region to a drain region of the fin structure. The air gap may reduce current leakage associated with the fin structure. The cross-sectional configuration of the air gap may be, if desired, like that of a lemon with two tips, or an oval. 
     According to another aspect of the invention, the first semiconductor material may be located in a lower recess portion, and the lower recess portion has an upwardly-opening angle in the range of from about 10° to about 55°. 
     According to another aspect of the invention, one or more of the fin structures may be incorporated into a FinFET device, especially a FinFET device that does not have an SOI configuration, and especially a FinFET device that is manufactured according to a process in which one or more source/drain fins are first recessed and then epitaxially re-grown. 
     According to another aspect of the invention, the first semiconductor material includes an SiP buffer layer, located over the air gap, and an SiP bulk layer is grown on the SiP buffer layer. If desired, a symmetrical shovel-shape element may be formed as part of the SiP bulk layer. 
     Additional features and embodiments, as well as additional aspects, of the present invention may be set forth or apparent from consideration of the detailed description and drawings. Moreover, it is to be understood that both the foregoing summary of the disclosure and the following detailed description are exemplary and intended to provide further explanation without limiting the scope of the present invention. 
     Process steps, method steps, or the like, that are described in a sequential order herein may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of the processes or methods described herein may be performed in any practical order. Further, some steps may be performed simultaneously, except where explained otherwise. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic (simplified for clarity of description) perspective view of a FinFET device constructed in accordance with one aspect of the present invention; 
         FIG. 2  is a detailed, cross-sectional view of two adjacent fins of the FinFET device of  FIG. 1 , at an intermediate stage of manufacture, taken along line  2 - 2  of  FIG. 1 ; and 
         FIG. 3  is a cross-sectional view of the fins of  FIG. 2 , at a subsequent stage of manufacture, take along the same line  2 - 2  of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     Referring now to the drawings, where like elements are designated by like reference numerals and characters, there is shown in  FIG. 1  a FinFET device  10  constructed in accordance with one aspect of the present invention. The device  10  has a silicon substrate  12 , a gate  14 , and three fins  16 , each extending through the gate  14  and having respective source and drain regions  20 ,  22 . The present invention is not limited to the illustrated configuration. A FinFET device constructed in accordance with the invention, may have, for example, one, two, or more than three fins  16 . 
     If desired, the substrate  12  may be formed of a single-crystal silicon material or an epitaxial silicon material. If desired, the substrate  12  may be formed of one or more other materials, including but not limited to SiGe, SiC, and GaAs. The lower portions of the fins  16  are separated from each other by shallow trench isolation (STI) regions  26 . The cross-sectional configuration of the surface of each STI region  26  is bowl-shaped, as shown in  FIGS. 2 and 3 , or V-shaped. The fin pitch  65  in the direction of line  2 - 2  may be, for example, 480 Å. 
       FIG. 2  shows two of the fins  16  at an intermediate stage of manufacture. At the illustrated stage, each fin  16  has already been subjected to processes including, preferably, but not necessarily, in this order: a silicon vertical etch process, a silicon lateral etch process, and an extra O 2  plasma process. 
     For each fin  16 , a substantially-rectilinear recess portion  40  is created during the vertical etch process. A lower recess portion  42  is created during the lateral etch process. The bottom  68  of the lower recess portion  42  should be far deeper than the spacer  44 ,  46 /STI regions  26  interface  67 . The bottom  68  may be, for example, in the range of from about sixty to about one-hundred forty angstroms deeper than the interface  67 . The recess portions  40 ,  42  are bounded by dielectric spacer walls  44 ,  46 . Each wall  44 ,  46  may have, for example, a SiN layer  48  (a hard mask), a SiCN layer  50  (a hard mask), and a second SiCN layer  52  (a seal layer). The recess portions  40 ,  42  operate as, and are an example of, a source/drain recess for the FinFET device  10  of  FIG. 1 . 
     The purpose of the extra O 2  plasma process, which may involve the use of high temperature plasma, is to remove impurities from the recess portions  40 ,  42 . Such impurities may include, but are not limited to, photoresist, C—H—F—Br—N—Si type polymer from a main etch process, C—H type polymer from a deposition process, C—H—F—N—Si type polymer from an over-etch process, C—H—Br—Si type polymer from the vertical etch process, and C—H—Cl—F—Si type polymer from the lateral etch process. 
     The extra O 2  plasma process is preferred over an in-situ O 2 -strip process. The latter process, which would be conducted during the vertical and/or lateral etch processes, would tend to excessively oxidize and thereby excessively degrade the upper edges  60 ,  62  (especially the SiN spacer material  48 ) of the spacer walls  44 ,  46 . In particular, the in-situ O 2 -strip process would tend to reduce, to a non-uniform extent, the constrain spacer heights (CSH)  64  of the walls  44 ,  46 . Different fins  16  would experience unpredictably non-uniform loss of CSH  64 . The irregular height reductions (Δ CSH) could lead to abnormal (asymmetric) epitaxial growth of SiP, dislocation, and stacking faults, which could lead to device degradation and undesirable drain-induced barrier lowering (DIBL), bulk leakage (Isb), and incomplete or poorly-formed self-aligned contacts (SAC). 
     According to the present invention, the epitaxial growth  74  ( FIG. 3 ) of SiP above the walls  44 ,  46  of each fin  16  should preferably be symmetrical. The growth  74  may be shovel-shaped, hexagonal, octagonal, or another shape, in cross section. In the example illustrated In  FIG. 3 , the shovel-shaped portions  74  are not merged with each other. In an alternative embodiment, the shovel-shaped portions may be merged with each other. 
     The extra O 2  plasma process, which occurs after the lateral etch process, does not tend to excessively degrade the upper edges  60 ,  62  ( FIG. 2 ) of the spacer walls  44 ,  46 . The upper edges  60 ,  62  are not subjected to as much oxidation during the extra O 2  plasma process as would be the case during the in-situ O 2 -strip process. Consequently, use of the extra O 2  plasma process results in more uniform and greater CSH  64  for the fin walls  44 ,  46 . 
     Moreover, use of the extra O 2  plasma process provides sufficient cleaning efficiency to maintain an acceptable relationship between (1) the upwardly-opening angle θ of the lower recess portion  42  and (2) ensuring that abnormal (such as asymmetrical) buffer growth is avoided. In a preferred embodiment of the invention, the upwardly-opening angle θ of the lower recess portion  42  is in the range of from about 10° to about 55°. Thus, the lower portion of the recess portion  42 , in the cross-section shown in  FIG. 2 , is V-shaped with a rounded, not sharp, tip at the bottom surface  68 . 
     On the other hand, the extra O 2  plasma process, which occurs after the lower recess portion  42  is created, may create a weakened oxidation region at the bottom surface  68  of the lower recess portion  42 . 
     Turning now to  FIG. 3 , in subsequent stages of manufacture, an SiP buffer layer  70  is grown within the lower recess portion  42 , and then an SiP bulk layer  72  is grown (from the bottom up) on the SiP buffer layer  70 . The growth of the SiP bulk layer  72  culminates in the formation of a shovel-shape portion  74 . If desired, a SiCoNi cleaning process may be performed, before initiating growth of the SiP buffer layer  70 , to remove native oxide from the surface of the lower recess portion  42 . 
     To prevent leakage from the fin  16  through the bottom  68  of the lower recess portion  42 , the SiP buffer layer  70  is grown laterally inwardly from the sidewalls  80 ,  82  of the lower recess portion  42  to form an air gap  100 . The SiP buffer layer  70  is separated to a large extent, though not completely, from the silicon substrate  12  by the air gap  100 . The air gap  100  is located between the SiP buffer layer  70  and the silicon substrate  12 . Although no SiP growth occurs on the fin recess bottom surface  68 , small portions of the SiP buffer layer  70  on opposite sides of the air gap  100  may be, if desired, in contact with the silicon substrate  12 . For the stage of manufacture illustrated in  FIG. 2  through the stage of manufacture illustrated in  FIG. 3 , bottom-up SiP epitaxy growth within and above the recess  40 ,  42  proceeds without any SiP growth on the fin recess bottom surface  68 . 
     As shown in  FIG. 3 , the air gap  100  is located underneath the SiP buffer layer  70 . The air gap  100  may have a tubular configuration, with a central axis  102 . The air gap  100  may extend along the entire lengths of the fins  16  except where the fins  16  are covered by the walls of the gate  14 . For each fin  16 , the air-gap central axis  102  is parallel to the direction in which the fin  16  extends from the source region  20  of the fin  16  to the drain region  22  of the fin  16 . As viewed in  FIG. 3 , the air gap  100  may have a cross-sectional configuration like that of a lemon with two tips, or an oval shape. 
     In operation, the air gap  100  separates the SiP buffer layer  70  (an example of a first semiconductor material) and the silicon substrate  12  (an example of a second semiconductor material). In the illustrated embodiment of the invention, the air gap  100  occupies from about twenty percent to about eighty percent of the boundary between the first and second semiconductor materials  70 ,  12 , and is below the lowest level of the surfaces of the STI regions  26 . The air gap  100  may reduce bulk leak (Isb) within the device  10 , among other things. 
     A known process for generating an air gap by controlling epitaxial growth within a semiconductor device is described in U.S. Pat. No. 8,395,217 (Cheng et al.). According to Cheng et al., however, the air gap is formed on a buried dielectric (BOX) layer, according to an SOI configuration. The air gap according to Cheng et al. does not separate first and second semiconductor materials. 
     In contrast to Cheng et al., the present invention may be implemented, if desired, without an SOI configuration. The FinFET  10  shown in  FIG. 1  of the present application does not have an SOI configuration, does not have a buried dielectric layer operatively associated with the fins  16 , but does have first and second semiconductor materials  70 ,  12  that are separated from each other by an air gap  100 . 
     The present invention is not limited to NFET processes and devices. The present invention may be applied, if desired, to PFET (SiGe:B) processes and devices as well. 
     Those skilled in the art will readily observe that numerous modifications and alterations of a semiconductor device and a method of fabricating the same may be made while retaining the teachings of the various aspects of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.