Abstract:
A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.

Description:
TECHNICAL FIELD 
     The technical field is in communication between different parts of an integrated data logic circuit. 
     BACKGROUND 
     Data logic circuits often require signals to travel relatively long distances on a chip or on a given circuit fabric. Faster architecture and chip requirements increase the need for faster processing between points on the given circuit or chip. In addition, as the relative distances that signals travel increase, there is a greater need to avoid latency or signal degradation. 
     One possible approach to solving such problems is to make use of registers along a long distance signal data path. In this approach, an input register first transmits the long distance signal to an intermediate register where the long distance signal is stored temporarily and then transmitted again to a final output register. Although using registers preserves integrity and signal strength, relaying data using registers requires an additional clock cycle to store the data into the intermediate register. This additional clock cycle causes an additional delay in transmitting the long distance signal from the input register to the output register. 
     Another potential solution is to route all of the signals from different parts of a given chip or circuit fabric to a single multiplexer (or mux), and then to multiplex the signals from the mux to appropriate destination points on the chip or circuit fabric. Multiplexing the signals would allow for a topologically simple way of transmitting the long distance signal, but at the expense of requiring more routing and more data combinations. The increased amount of routing and data combinations would both delay the long distance signal as the long distance signal is transmitted from the input register to the output register. 
     SUMMARY 
     A series of logic “clouds” that are connected to each other are used to provide logical functions and to propagate a long distance signal along a circuit fabric or chip. An initial logic cloud reads the signal from an input register, then buffers and repeats the signal before transmission through a series of “middle” logic clouds. The middle logic clouds may include any number of circuit connections, but every logic cloud passes the signal through a NAND-inverter combination before transmitting the signal through a connector circuit to the next logic cloud. The long distance signal passing through from the input cloud will be logically NANDed with at least one other signal, with the NANDed signal feeding into an inverter. The inverted long distance signal then feeds into the connector circuit and passes to the next logic cloud. The long-distance signal may be delayed arriving at the logic cloud and may not have reached a steady state as quickly as the other signals that are being NANDed with the long distance signal. 
     The NAND-inverter combination effectively performs a logical AND operation on the long distance signal and also performs a repeating operation on the long distance signal. The repeating arises from the combination of the NAND and the inverter gates. After passing through the logic clouds, the signal is passed through an end logic cloud and a destination logic cloud in which the signal is repeated and buffered before being driven into an output register. 
     Each chip or circuit fabric may contain a multiple number of logic clouds and different data pathways that use logic clouds. In addition, each logic cloud may include other logic gates and branches from the main circuit path, but all may have a NAND-inverter combination for propagating the signal between logic clouds. 
     A corresponding method is disclosed in which an input signal is propagated with both logical combination and repeating. An input signal, which is the long distance signal, is read from an input register and first buffered. The buffered signal is then repeated before the buffered signal is transmitted to the first NAND-inverter combination, where the signal is NANDed with a local signal that has reached a steady state and then inverted. The long distance signal has now become a pathway input signal to a path of one or more NAND-inverter combinations. 
     The method for propagation across a long distance begins when the pathway input signal, which is often the long distance signal, is first NANDed with at least one local signal that has reached a steady state. The pathway input signal is then inverted to form an intermediate output signal, which has higher drive strength than the pathway input signal. The intermediate output signal may be fed back as the pathway input signal for other NAND-inverter combinations that in turn would use the subsequent intermediate output signal as the pathway input signal for the next NAND-inverter combination. A first final intermediate output signal is produced once the long distance signal is fed through all of the given NAND-inverter combinations on a given intermediate block. The long distance signal may be combined with a number of other circuit elements as it is NANDed and inverted along the long distance signal&#39;s logical path. 
     Once the long distance signal has completed the journey across the intermediate block, a final series of logical combinations occur. The long distance signal is first electronically repeated to boost the signal strength and is then buffered to condition the long distance signal. The long distance signal is then transmitted into the output register, where it may be retrieved. 
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     FIG. 1A illustrates a sample long distance signal path between different data blocks on a given chip. 
     FIG. 1B illustrates a prior art method of transmitting data between the different data blocks on the chip of FIG.  1 A. 
     FIG. 2A illustrates one embodiment of logic clouds that are used to transmit a signal across the circuit path from source block A through intermediate block B to destination block C. 
     FIG. 2B illustrates a second embodiment of the invention where logic clouds are used to transmit a signal through a different circuit path than that shown in FIG.  2 A. 
     FIG. 3 is a schematic representation of the different logic clouds found in the long distance signal data path in FIG.  2 A. 
     FIG. 4 is a schematic representation of an alternate set of logic clouds for the same data path found in FIG.  2 A. 
     FIG. 5A is a flowchart illustrating a method of transmitting the signal through the circuit path using logic clouds. 
     FIG. 5B is a flowchart illustrating a method for processing and conditioning the signal prior to being transmitted through the circuit path. 
     FIG. 5C is a flowchart illustrating a method of processing the signal after being transmitted through the circuit path. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1A illustrates a sample data circuit layout  10 . The data circuit layout  10  is divided into three major sections, including a source data block (or source block)  20 , an intermediate data block (or intermediate block)  30  and a destination data block (or destination block)  40 . Each data block may include a multiplicity of logical devices and circuits. The data circuit layout  10  may also include a number of other similar data blocks in addition to the source data block  20 , the intermediate data block  30  and the destination data block  40 , which are provided for illustrating the invention. The data circuit layout  10  of FIG. 1A includes auxiliary “north side” blocks  25  in addition to the destination data block  40  and auxiliary “south side” blocks  35  in addition to the source data block  20 . A long distance signal  15  traveling the data path as shown between the source data block  20  to destination data block  40  as shown exemplifies a longest path between a north side block and a south side block through the intermediate block  12 . 
     Referring to FIG. 1B, one prior art method for propagating the long distance signal  15  is to use a system of registers as discussed above. In this prior art system, the long-distance signal  15  emerges from an input register  16  in source block  20 . The long-distance signal  15  may then be transmitted to an intermediate register  18  on intermediate block  30 , where the long distance signal  15  is then transmitted a second time to an output register  17  on destination block  40 . For the reasons given above, this prior art data path requires an additional clock cycle to store the data in the intermediate register  18  and thus delays the transmission of data from source block  20  to destination block  40 . 
     To speed up the data transmission of a long distance signal, a series of logic “clouds” may be employed to facilitate data transfer from source block  20  to destination block  40 . Referring to FIG. 2A, a long distance signal  75  originates from source logic cloud  100  on a source block A and passes through five other logic clouds  110 ,  140 ,  150 ,  160 ,  170  on an intermediate block B. A destination block C includes a destination logic cloud  180  that incorporates an output register  90 . (See FIG.  3 ). Each of these logic clouds  100 ,  110 ,  140 ,  150 ,  160 ,  170 ,  180  may contain one or more logic gates or other circuit components that in tandem allow for amplification and a signal integrity along the data path. Moreover there is no need for an additional clock cycle to store the data in an intermediate register. 
     FIG. 3 illustrates the logic clouds  100 ,  110 ,  140 ,  150 ,  160 ,  170 ,  180  in greater detail. The source logic cloud  100  includes the input register  70  from which the long distance signal  75  originates and which is connected to an input buffer  102 . The input buffer  102  subsequently connects into an input repeater  104 . The input repeater  104  may then feed into a connector section  106 , which is represented in the diagrams as an RC (resistor-capacitor) circuit to illustrate a delay that will naturally occur in the connector section  106 . The connector section  106  may be any type of wire conductor and may include one or more RC circuits. However, the RC circuits are merely illustrative of the delay that may occur in the connector section  106 . 
     The initial logic cloud  110  includes a logic subcloud  125 . The logic subcloud  125  features a logic subcloud repeater  112  that is connected to a first connector section  114  and in turn connected to a drive strength  9  (“ — 9”) inverter  116  (e.g., an inverter with a drive strength of 9). (The drive strength of the logic gates are illustrated with an underbar symbol (“_”) followed by the drive strength number, such as  — 1 representing a drive strength of 1. The drive strength increases with an increasing drive strength number, so that a drive strength of 1 is weak while a drive strength of 9 is strong. A second connector section  118  connects to the  — 9 inverter  116  and feeds into a  — 1 NAND gate  124 . The  — 1 NAND gate  124  reads a steady-state signal, represented by “VDD”, in addition to the output of the  — 9 inverter  116 . 
     A  — 3 NAND gate  126  reads the output of the  — 1 NAND gate  124  as an input, along with a plurality of steady state signals labeled as VDD. (In all of these drawings, NAND gates are illustrated as being connected with an n-number, such as n3, n5, n9 and n13, which represents the data path of the long distance signal  75 . VDD signals represent signals that travel a shorter distance and that have theoretically reached a steady-state before the long-distance signal. The  — 3 NAND gate  126  in subcloud  125  feeds into a  — 4 inverter  128 . The output of the  — 4 inverter  128  then serves as the output of the logic subcloud  125 . The logic subcloud  125  connects into an  — 6 NAND gate  130  that subsequently connects into a s — 8 inverter (i.e. an S-inverter with a drive strength of 8)  132 . (An S-inverter is a symmetric inverter, where output rise and fall times for the S-inverter are more balanced than for a non-symmetric inverter. A non-symmetric inverter may be used in the invention as well). The s — 8 inverter  132  then feeds into a connector section  134  that completes the initial logic cloud  110  and that connects initial logic cloud  110  to logic cloud  140 . 
     The “middle” logic clouds  140 ,  150 ,  160  illustrated in FIG. 3 may include some or all of the same circuit elements found in initial logic cloud  110 , but all of the middle logic clouds  140 ,  150 ,  160  have at least one NAND-inverter combination. For example, the middle logic cloud  140  includes a NAND  142  connected to an inverter  144  that is subsequently connected to a connector circuit  146  that connects to the next middle logic cloud  150 . Likewise, middle logic cloud  150  includes a NAND gate  152  that is connected to an inverter  154 , which is further connected to another connector circuit  156  for transmitting the signal from middle logic cloud  150  to middle logic cloud  160 . Middle logic cloud  160  has a similar structure. All of the middle logic clouds  140 ,  150 ,  160  may have any number of different circuit elements in addition to the circuits explicitly illustrated in FIG. 3, but all of the logic clouds  140 ,  150 ,  160  have NAND-inverter combinations that at their respective junction points to their connector circuits  146 ,  156 ,  166 . 
     The end cloud  170  represents the last logic cloud on intermediate block B that the long distance signal  75  passes through before entering the destination block C. The end cloud  170  differs somewhat from the middle logic clouds  140 ,  150 , or  160 . The end cloud  170  includes a NAND gate  172  connected to a repeater  174 . The repeater  174  connects to another connector section  176  that is connected to destination cloud  180 . 
     The destination logic cloud  180  includes a final repeater  182  connected to a connector section  184  and a destination buffer  186 . The destination buffer  186  connects to the output register  90 , where data may be stored for later retrieval. 
     Referring to FIGS. 2A,  3  and  5 B, the long distance signal  75  originates from the source logic cloud  100 . A method  351  for pre-processing the long distance signal begins when the long distance signal  75  originates from the input register  70  as an input register signal (step  350 ). Referring to FIG. 5B, the long distance signal  75  is first buffered (step  355 ) and then repeated (step  360 ) as the long distance signal  75  emerges from source logic cloud  100 . The long distance signal  75  then passes through the initial logic cloud  110  and logic subcloud  125 . Within the logic subcloud  125 , the long distance signal  75  passes through two different NAND gates in which the long distance signal  75  is NANDed with other shorter-distance stable signals that emerge from either the intermediate block B, one of the north side blocks  50  or one of the south side blocks  60 . The long distance signal  75  may be NANDed with these shorter distance and other stable data signals (step  370 ) and then inverted (step  375 ) before exiting the logic subcloud  125 . 
     The NAND-inverter combinations provide a method  301  for both logically combining the long distance signal  75  and repeating the resulting signal. Referring to FIG. 5A, the long distance signal  75  is read in as a pathway input signal (step  310 ). The pathway input signal is then NANDed with at least one other signal (VDD), which will generally be a shorter distance or local signal that has reached a stable state signal (step  315 ). The long distance signal  75 , which has now been NANDed, is then inverted to produce an intermediate output signal (step  320 ). The combination of NANDing and inverting allows for both logically combining the long distance signal  75  with shorter distance signals (VDD) as well as repeating the long distance signal  75 , which is now an intermediate output signal. 
     The long distance signal may be NANDed and inverted multiple times in succession. For example, the method may check to see whether this first NAND-inverter combination is the final combination (step  325 ). If this first NAND-inverter combination is not the final combination, the method may proceed to feed in the intermediate output signal as the next pathway input signal (step  330 ) and repeat the process. A first final intermediate output signal is produced once the final NAND-inverter combination has been reached (step  325 ). This first final intermediate output signal is the long distance signal  75  after the long distance signal  75  has undergone a series of logical combination and repeating on the intermediate block B. 
     The long distance signal  75  may pass through other circuit elements in middle logic clouds  140 ,  150 ,  160  other than NAND-inverter combinations. The NAND-inverter combinations, though, serve as the common element between the different logic clouds  140 ,  150 ,  160 . 
     The long distance signal  75  passes through one final NAND operation after reaching end logic cloud  170  (step  327 ), which is still on the intermediate block B. After the final NAND operation, the long distance signal  75  passes through a repeater  174  (step  333 ) to form a second intermediate output signal. The long distance signal  75  has now undergone all logical operations and is ready to be sent to the signal&#39;s final destination off of the intermediate block B. The long distance signal  75  (at this point equivalent to the second final intermediate output signal) is then transmitted to the destination logic cloud  180  (step  335 ), ending the method  301 . 
     Referring to FIGS. 2A and 3, the long distance signal  75  reaches the destination logic cloud  180  on destination block C after exiting block B. At this point, the long distance signal  75  undergoes a final signal conditioning  401  (See FIG.  5 C). The long distance signal  75  is first repeated (step  410 ) through the final repeater  182  to boost the signal strength prior to feeding into a final connector section  184 . The long distance signal  75  is then buffered (step  415 ). The final buffered long distance signal is then transmitted or driven into the output register  90  (step  420 ), ending the journey of the long distance signal  75 . The output register  90  may hold data from the long distance signal  75  for retrieval at a later time. In this way, the long distance signal  75  may be transmitted from source block A to destination block C without needing to store the signal  75  in an intermediate register. 
     The long distance signal  75  illustrated in FIG. 2A used one possible data path with NAND-inverter combinations to pass data through long distances on the data circuit layout  10  that may be found on a given circuit fabric, chip, or data architecture. A data circuit layout  10  could include a plurality of long distance signals  75  traveling through a number of different paths of logic clouds. Referring to FIG. 2B, different combinations may be used, and different logic clouds  185  may be used for data paths that are not necessarily the longest path between points on a given data circuit layout. 
     Furthermore, different logic may be used in each of the logic clouds  100 ,  110 ,  140 ,  150 ,  160 ,  170  and  180 , as is required by different types of architectures and different logic specifications. For example, in FIG. 4 a different “second” cloud  210  includes a repeater  212  and a connector section  214  but a NOR gate  218  that feeds a different n5. The rest of the circuitry illustrated in FIG. 4 is essentially identical to that illustrated in FIG.  3 . As in the circuitry of FIG. 3, an NAND gate plus an inverter provides both repeating of the signal and logical functions without requiring the use of standalone repeaters or buffers. 
     The terms and descriptions used herein are set forth by way of illustration only and are not meant as limitations. Those skilled in the art will understand that numerous variations are possible within the spirit and scope of the invention as defined in the following claims—and their equivalents—in which all terms are to be understood in the broadest reasonable sense.