Abstract:
Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a divisional application claiming priority to U.S. patent application Ser. No. 11/495,143 filed on Jul. 27, 2006 and entitled “Apparatus and Method for Wafer Level Fabrication of High Value Inductors on Semiconductor Integrated Circuits,” which is incorporated herein by reference in its entirety for all purposes. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to semiconductor integrated circuits, and more particularly, to an apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. 
     2. Background of the Invention 
     Inductors are commonly used in the electronics industry for storing magnetic energy. An inductor is typically created by providing an electric current though a metal conductor, such as a metal plate or bar. The current passing though the metal conductor creates a magnet field or flux around the conductor. The amount of inductance is measured in terms of Henries. In the semiconductor industry, it is known to form inductors on integrated circuits. The inductors are typically created by fabricating what is commonly called an “air coil” inductor on the chip. The air coil inductor is usually either aluminum or some other metal patterned in a helical, toroidal or a “watch spring” coil shape. By applying a current through the inductor, the magnetic flux is created. 
     Inductors are used on chips for a number of applications. Perhaps the most common application is direct current to direct current or DC to DC switching regulators. In many situations, however, on chip inductors do not generate enough flux or energy for a particular application. When this occurs, very often an off-chip discrete inductor is used. 
     There are a number of problems in using off-chip inductors. Foremost, they tend to be expensive. With advances in semiconductor process technology, millions upon millions of transistors can be fabricated onto a single chip. With all these transistors, designers have been able to cram a tremendous amount of functionality onto a single chip and an entire system on just one or a handful of chips. Providing an off-chip inductor can therefore be relatively expensive. Off-chip inductors can also be problematic in situations where space is at a premium. In a cell phone or personal digital assistant (PDA) for example, it may be difficult to squeeze a discrete inductor into a compact package. As a result, the consumer product may not be as small or compact as desired. 
     An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits is therefore needed. 
     SUMMARY OF THE INVENTION 
     Methods for forming multiple inductors on a semiconductor wafer are described. In one embodiment, a plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Metal is electroplated into the recess regions to form inductor coils. Optionally, a magnetic paste can be applied over the inductor coils. In another embodiment, one or more inductors are formed on an integrated circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross section of a semiconductor integrated circuit die with power circuitry fabricated and an inductor fabricated thereon according to the present invention. 
         FIG. 2  is a semiconductor wafer including a plurality of dice with power circuitry fabricated thereon according to the present invention. 
         FIGS. 3A through 3E  are a series of cross sections illustrating the fabrication of the inductors fabricated on the wafer according to the present invention. 
         FIGS. 4A and 4B  illustrate various pattern arrangements of magnetic core inductors and inductor coils of the inductors fabricated onto the wafer according to the present invention. 
     
    
    
     Like elements are designated by like reference numbers in the Figures. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to  FIG. 1 , a cross section of a semiconductor integrated circuit die with power circuitry and an inductor fabricated directly thereon according to the present invention is shown. The die  10  includes a silicon substrate  12  with power circuitry fabricated thereon in accordance with well known semiconductor manufacturing techniques (for the sake of simplicity, the circuitry is not visible in the figure), metal interconnect layer(s)  14  including one or more levels of metal interconnect, and an interconnect dielectric layer  16  formed over the metal interconnect layers  14 . An inductor  18  is fabricated directly on a plating layer  44  formed over the interconnect dielectric layer  16 . The inductor  18  includes a plurality of magnetic core inductor members  20  provided between resists spacers  22 , a planarization surface  24  formed over the inductor members  20  and spacers  22 , an insulating layer  25 , a plating layer  27 , an inductor coil  26  formed within another resist layer  29 , and a magnetic paste  30  formed over the inductor coil  26 . An electrical contact  32  is provided between the coil  26  and a switching node (not shown) provided in one of the metal layers of interconnect  14 . 
     The present invention is directed to the wafer level fabrication of the inductor  18  directly onto the die  10  in wafer form.  FIGS. 2 and 3A  through  3 E illustrate the fabrication sequence. 
     Referring to  FIG. 2 , a semiconductor wafer  40  including a plurality of dice  10  is shown. Each die  10  includes power regulation circuitry fabricated thereon, including a switching node  42 . For the sake of simplicity, the power regulation circuitry is not shown or described herein. The switching node  42  is typically a metal contact of one of the metal interconnect layers  14 . The switching node  42  is in electrical contact with the underlying transistors forming the power regulation circuitry on the device. In the subsequent discussion with regard to  FIGS. 3A through 3E , the wafer level fabrication process for forming the inductor  18  on top of the die  10  is described in detail. 
     Referring to  FIG. 3A , a cross section of the wafer  40  is shown. The wafer includes the silicon substrate  12  having the power regulation circuitry fabricated thereon, metal interconnect layers  14 , and the interconnect dielectric layer  16  formed over the metal layers  14 . The fabrication of the design and fabrication of the power circuitry and metal interconnect levels  14  are well known and therefore are not described in detail herein. 
     The initial step in the fabrication of the inductor  18  involves the forming of a plating layer  44  across the top surface of the wafer  40 . The plating layer  44  actually includes three layers, including an underlying oxide protection layer, a middle seed layer, and an upper adhesion layer. In one embodiment, the plating layer  44  is formed by sputtering 300 Angstroms of titanium, 3000 Angstroms of copper, and 300 Angstroms of titanium on the wafer surface to form the protection, seed, and adhesion layers respectively. It should be noted that specific embodiment disclosed herein in merely exemplary, and that a plating layer  44  can be formed using any one of a number of well known techniques and materials and the invention should not be construed as limited to the metals and thicknesses disclosed herein. 
     In the next step as illustrated in  FIG. 3B , the photo resist layer  22  is formed over the plating layer  44 . In various embodiments, the photo resist layer  22  can be a spin-on BCB or SU8 layer approximately 30 microns thick. Once the resist layer  22  is formed, it is patterned to form a set of recess regions  46  that expose the underlying plating layer  44 . The recess regions  44  are formed using well known photolithography techniques including masking, exposing and etching of the resist layer  22 . The recess regions  46  form what are in essence “molds” which will be later used to form the magnetic core inductor members  22 . 
     As illustrated in  FIG. 3C , the magnetic core inductor members  20  are formed within the molds or recess regions  46  by electroplating. The upper adhesion layer of titanium is stripped away, exposing the underlying copper seed layer of the plating layer  44 . A negative bias or voltage is then applied to the wafer  40  while submerged in a NiFe plating bath. During the plating, the recess regions  46  are filed with NiFe, forming the magnetic core inductor members  20 . The recess regions  46  thus define the shape and location of the inductor members  20  on each die on the wafer  30 . 
     A illustrated in  FIG. 3D , the inductor coils  26  are next formed on the wafer surface. After the inductor members  20  are formed, the planarization layer  24  is created across the top surface of the wafer. In one embodiment, the planarization layer  24  is a spin-on layer such as BCB or SU8. Once the layer is formed, it is planarized or smoothed using chemical mechanical polishing (CMP), as is well known in the semiconductor fabrication art. A dielectric insulating layer  25  is next formed across the wafer surface. In various embodiments, the insulating layer  25  is formed by performing a plasma enhanced chemical vapor deposit of a material such as oxide, spinning on a polymer such as BCB or SU8, or a chemical vapor deposition of a polymer such as Paralyne. 
     The inductor coils  26  are formed is a manner similar to that described above with regard to the inductor members  20 . Specifically, another plating layer  27  including an underlying oxide protection layer, a middle seed layer, and an upper adhesion layer, is formed across the wafer surface. Thereafter, a photo resist layer  29  is formed and patterned, forming recess regions which expose the top adhesive of the plating layer  27 . The top adhesion layer is then stripped away, and the wafer  40  undergoes a plating operation in a copper bath. The inductor coils  26  are formed by the plating of copper in the bath onto the exposed seed layer within the recess regions. For the sake of brevity, the aforementioned steps are not illustrated in detail in the figure. The process, however, is essentially the same as that described above, and is therefore not repeated herein. 
     In the next step, the electrical contacts  32  are provided between the coils  26  and the underlying switching nodes (not shown) provided one of the metal layers of interconnect  14 . The electrical contacts are formed by etching vias into the top surface of the wafer down to the switching node contact of each die  10 . The vias are then filled with an electrically conductive material such as aluminum or copper. For the sake of simplicity, only one electrical contact  32  is illustrated in the Figures. 
     In the final step, as illustrated in  FIG. 3E , a “blob” of magnetic paste  30  is extruded over the top surface of the wafer  40 . The magnetic paste  30 , according to various embodiments, can be either a non-conductive epoxy or a polymer filled with magnetic particles. An example of the type of magnetic particles could be MnZn ferrite, although many other types of magnetic particles could be used. In another specific embodiment, the particles are of various sizes ranging from 1 to 10 microns. The size variation is useful in increasing the fill factor of the magnetic particles. In one embodiment, the fill factor is between 80 to 90 percent. 
       FIGS. 4A and 4B  illustrate various pattern arrangements of magnetic core inductors  20  and inductor coils  26  of the inductors fabricated onto the wafer according to the present invention. It should be noted that these two embodiments are exemplary and in no way should they be construed as limiting. In  FIG. 4A , the magnetic core inductors  20  are arranged in a chevron pattern in the four corners of the die  10  while the coil  26  is a multi-turn coil formed thereon. In  FIG. 4   b , the magnetic core inductors  20  are positioned around the periphery of the die  10 , which the coil  26  makes a single turn. In each example, the magnetic core inductor members  20  are laminations perpendicular to the direction of current flow through the inductor coil  26 . 
     In accordance with the present invention, the layout of the inductors  20  and coils  26  is arbitrary and can be done in any desirable manner. It should be made clear that the patterns shown in  FIGS. 4A and 4B  are arbitrary and should not be construed as limiting the invention. 
     While this invention has been described in terms of several preferred embodiments, there are alteration, permutations, and equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. For example, the steps of the present invention may be used to form a plurality of high value inductors  10  across many die on a semiconductor wafer. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.