Abstract:
An improved amplifier includes an input stage differential amplifier ( 100 ) with an output forming a gain node ( 102 ), an output stage buffer ( 104 ) having an input connected to the gain node ( 102 ), a compensation capacitor ( 106 ) connected from the gain node ( 102 ) to ground, and a correction amplifier ( 200 ) with a first input connected to the output of the output stage buffer ( 104 ), a second input connected to the input of the output stage buffer ( 104 ), and having an output connected to the gain node ( 102 ), the correction amplifier further including a correction capacitor ( 304 ) connected between the input and output of the output stage buffer ( 104 ). The correction capacitor ( 304 ) preferably has a capacitance value (C′) set equal to the capacitance (Ccomp) of the compensation capacitor ( 106 ).

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to circuitry for controlling distortion due to current variations in output stage driver transistors of an amplifier. 
     2. Background 
     Several factors can produce distortion in amplifiers. One of many is the output stage. Because the output stage must provide widely varying output load currents but only draw modest quiescent currents, the output and driver transistors undergo decades of current variation throughout the output drive range. The decades of current variation causes the output and driver transistor V BE S to change according to logarithmic law, causing distortion when superimposed on linear signals. 
     A typical amplifier block diagram is shown in FIG.  1 . In the amplifier of FIG. 1, an input differential voltage is applied across input stage amplifier  100  to drive a gain node  102 . The gain node  102  is buffered by an output stage buffer  104  forming an output buffer for the overall amplifier of FIG.  1 . The output buffer  104  has a nominal gain of +1. The frequency response is set by setting the capacitance Ccomp of capacitor  106 . 
     Distortion created by the output buffer  104  can be modeled as a voltage source V DISTO    107  in series with the input of the output buffer  104 . To correct for V DISTO , some type of feedback is typically employed to adjust the differential input voltage. 
     FIG. 2 shows a block diagram of an amplifier with circuitry including correction amplifier  200  to correct for V DISTO  by creating an error current which is injected into the gain node  102 . The gain of the correction amplifier  200 , Gm′, allows the error from the gain node to the final output to be observed. The gain of the amplifier  200  is typically set using an internal resistor. Previous designs employed the resistor with a value set so that the magnitude of Gm′ was less than the input differential Gm for stability. The Gm′ values of previous designs were also generally flat with frequency due to the resistor R controlling Gm′. Note that components carried over from FIG. 1 to FIG. 2 are similarly labeled, as will be components carried over in subsequent figures. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention an improved amplifier is provided with circuitry to correct for V DISTO  by creating an error current from a correction amplifier which is injected into the gain node, similar to FIG.  2 . The circuit in accordance with the present invention includes components as in FIG. 2, with the correction amplifier including a correction capacitor to correct for V DISTO . Unlike typical circuits which included a resistor, with the correction capacitor the effective correction value will not be flat with frequency. The correction capacitor has a capacitance value C′ preferably set equal to the capacitance of the compensation capacitor Ccomp. With the value for C′ so set, Gm′≡sComp and the feedback current provided will be exactly the amount the differential input to amplifier  100  would have to be adjusted in feedback to supply the correct current to compensate for V DISTO . Thus, no input differential voltage is needed to cancel V DISTO , and the distortion is effectively cancelled. Another benefit of using the correction capacitor is that output impedance is reduced over frequency. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described with respect to particular embodiments thereof, and references will be made to the drawings in which: 
     FIG. 1 shows a block diagram of a typical amplifier; 
     FIG. 2 shows a block diagram illustrating modifications to the amplifier circuit of FIG. 1 to correct the distortion modeled as V DISTO ; 
     FIG. 3 shows circuitry in accordance with the present invention with components implementing the block diagram of FIG. 2, but with a correction capacitor used to set Gm′; 
     FIG. 4 shows details of components for implementation of the circuit of FIG. 3; 
     FIG. 5 shows yet another embodiment of components for implementation of the circuit of FIG. 3; 
     FIG. 6 shows an embodiment to implement the block diagram of FIG. 3 with amplification provided without a differential stage connected to the correction capacitor; and 
     FIG. 7 shows circuitry added to FIG. 6 to improve overall performance. 
    
    
     DETAILED DESCRIPTION 
     One realization of circuitry for the block diagram shown in FIG. 2 where Gm′ can be controlled to be approximately equal to sComp is shown in block diagram FIG.  3 . In FIG. 3, the two PNP transistors  300  and  302  form a differential amplifier with a Gm′ of sC′, where C′ is the capacitance of capacitor  304 . A current mirror  310  is used to convert the differential output from the collectors of transistors  300  and  302  to a single-ended output to apply to the gain node  102 . The emitters of transistors  300  and  302  are fed by respective current sources  305  and  306 . 
     Details of components which may be used for the block diagram of FIG. 3 are shown in FIG.  4 . In FIG. 4, the circuitry for the current mirror  310  of FIG. 3 includes transistors  400 - 403 , current sinks  406  and  407  and a voltage source  410 . The transistors  400  and  401  are connected in a current mirror configuration with bases connected together and the collector of transistor  401  connected to its base. The gain node  102  is connected at the collector of transistor  400 . Emitters of transistors  400  and  401  are connected from the power supply pin connection shown as Vcc. Cascode transistor  403  connects the collector of transistor  401  to a current sink  406 , while cascade transistor  404  connects the collector of transistor  400  to current sink  407 . A cascode transistor indicates the transistor is configured to vary the current at its collector by changing the emitter current, as opposed to controlling collector current by varying base voltage in a more standard biasing scheme. The current sinks  406  and  407  sink current to a power supply pin connection shown connected to ground (GND). A voltage supply  410  is connected to the bases of transistors  402  and  403 . The collector of differential stage transistor  300  is connected to the emitter of transistor  403 , while the collector of transistor  302  is connected to the emitter of transistor  402 . 
     In FIG. 4, the circuitry for the amplifier  100  of FIG. 3 includes differential transistors  412  and  416 , current sinks  420  and  422  and resistor  426 . The noninverting amplifier input (+) is connected to the base of transistor  412 , while the inverting amplifier input (−) is connected to the base of transistor  416 . Current is provided from current sink  420  from Vcc to the emitter of transistor  412 , while current is provided from current sink  422  to the emitter of transistor  416 . The emitters of transistors  412  and  416  are further connected together by resistor  426 . The collector of transistor  412  is connected to the collector of transistor  300 , while the collector of transistor  416  is connected to the collector of transistor  302 . 
     FIG. 5 shows another embodiment of detailed components which may be used for the circuit of FIG.  3 . The circuit of FIG. 5 varies from FIG. 4 first by configuring current sinks  305  and  306  to sink current from the emitters of respective transistors  300  and  302  to GND, as opposed to sourcing current from Vcc to the emitters of transistors  305  and  306 . The collectors of transistors  300  and  302  are rearranged from the connection in FIG. 4 to be connected to the emitters of respective transistors  401  and  400 . The bases of transistors  400  and  401  are connected together to the collector of transistor  400 . The emitters of transistors  400  and  401  are separated from Vcc by respective resistors  500  and  501 . A transistor  504  is further added to separate the collector of transistor  400  from transistor  402 . The base of transistor  504  is connected to the collector of transistor  401 . The gain node  102  is connected to the common collectors of transistors  504  and  402 . The transistor  504  serves to limit the effect of variations in Vcc on the output of the amplifier. The remaining components are connected as in FIG.  5 . 
     In the circuitry of FIG. 3, FIG. 4, or FIG. 5, a resistor is preferably placed in series with C′  304 . The value of the resistor in series with capacitor C′ should be greater than 1/Gm to ensure high-frequency stability by limiting the maximum amount of positive feedback through the capacitor  304  providing C′ that Gm must overcome. 
     The circuits in FIGS. 3-5 use a differential amplifier stage formed using transistors  300  and  302  connected to capacitor  304 . Another circuit is shown in FIG. 6 which realizes the block diagram of FIG. 2 without a differential stage connected to a capacitor  304  providing C′. 
     In the circuit of FIG. 6, transistors  601 - 604  replicate the voltage at the gain node  102 , so capacitor  304  providing C′ has a voltage Vgain of the gain node  102  on one terminal of the emitters of transistors  601  and  602 , and Vgain-V DISTO  at its other terminal (output). A current sV DISTO C′ is developed by capacitor  304  at the emitters of transistors  601  and  602  and routed through transistors  601  and  602 . These currents rejoin at the gain node  102  to cancel V DISTO  via the upper current mirror transistors  400 - 401  and the lower cascode transistors  402  and  403 . 
     The circuit of FIG. 6 modifies FIG. 5 by adding the new transistors  603  and  604  both having a base connected to the gain node  102 . The emitter of transistor  603  is driven by a current source  606 , while its collector is connected to GND. The emitter of transistor  604  is connected to a current sink  610 , while is collector is connected directly to Vcc. The base of newly added transistor  601  is connected to the emitter of transistor  603 , while the base of new transistor  602  is connected to the emitter of transistor  604 . The collector of transistor  602  is connected to the emitter of transistor  403 . The collector of transistor  601  is connected to the emitter of transistor  401 . Alternatively, the collector of transistor  601  can be connected to the collector of transistor  401  as shown by the dashed lines. The remaining components of FIG. 6 which form the input amplifier and current mirror have components connected as in FIG.  5 . 
     An advantage of the circuit of FIG. 6 is that the substrate capacitance  608  connected to the terminal of capacitor  304  at the output of the amplifier can be driven by the output and its current not upset the correct SC′V VISTO  current. A disadvantage is that the collector currents of transistors  601  and  602  upset the DC balance of the cascode transistors  402 - 403  and current-mirror transistors  400 - 401 . 
     The circuit of FIG. 7 corrects for the problems with DC balance from the circuit of FIG.  6 . In FIG. 7, transistors  705  and  706  provide DC currents equal to transistors  601  and  602  so as to not upset the balance of associated circuitry. No C′ correction current flows through transistors  705  and  706 , and the effects of CjC of transistors  601  and  602  is cancelled by the transistors  705  and  706  connections, assuming the transistor sizes are the same respectively. 
     The circuit of FIG. 7 includes the components of FIG. 6, with newly added transistors  705  and  706 . Similar to transistors  601  and  602 , transistors  705  and  706  have common emitters. The base of transistor  705  is connected with the base of transistor  601  to the emitter of transistor  603 , while the base of transistor  706  is connected with the base of transistor  602  to the emitter of transistor  604 . The collector of transistor  705  is connected to the emitter of transistor  400 . The collector of transistor  706  is connected to the emitter of transistor  402 . 
     Although transistors are shown as one preferable type, such as transistors  400  and  401  which are PNP and transistors  402  and  403  which are NPN, transistor types may be as interchanged and the invention still function for its intended purpose. Further, although the pin connections are labeled as Vcc and GND, various voltage potentials could be applied to these power supply rails, such as +5 volts to Vcc and −5 volts to GND, or +5 volts to Vcc and 0 volts to ground. 
     Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many other modifications will fall within the scope of the invention, as that scope is defined by the claims provided below.