Abstract:
A dynamic random access memory (DRAM) having a plurality of word lines and a plurality of bit line pairs comprises circuitry for applying an equalizing potential to either one or the other bit line of the paired bit lines to equalize (1) a first difference between a first potential and a second potential and (2) a second difference between the first potential and a third potential, for balanced read out of the paired bit lines. The first potential appears on a reference bit line paired with a bit line connected to a memory cell selected by an external address prior to sensing thereof, the second potential appears on the bit line when the selected memory cell contains &#34;H&#34; level data and the third potential appears on the bit line when the selected memory cell contains &#34;L&#34; level data. Each bit line pair has circuitry for adjusting bit line potentials consisting of a pair of capacitors having their electrodes connected to respective bit lines of an associated bit line pair in a corresponding column, and a pair of dummy word lines running parallel to the plurality of word lines, connected to respective other electrodes of the pair of capacitors. When a memory cell, connected to a bit line in a bit line pair, is selected, the potential of a dummy word line capacitively coupled to the other bit line in the bit line pair is rendered active before a sense amplifier is made active for a sensing operation.

Description:
This application is a continuation of application Ser. No. 07/564,519 filed Aug. 9, 1990, now abandoned which is a divisional application of application Ser. No. 07/192,575, filed May 11, 1988, now U.S. Pat. No. 4,982,367. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to dynamic random access memories (DRAM), and more particularly, to a method of and circuitry for reading data from a DRAM, wherein the magnitude of difference of potential imparted to a bit line pair, as a result of &#34;H&#34; or &#34;L&#34; data on a selected memory cell when the cell is connected to the bit line pair, is equalized. 
     2. Description of the Prior Art 
     Recently, in a dynamic random access memory, from a view point of low power dissipation and fast read operation, peripheral circuitry consisting of complementary metal oxide semiconductor (CMOS) transistors and precharging of a bit line to half of an operating power-supply voltage Vcc or 1/2 Vcc have been a major trend, which is described in, for example, an article by Nicky Chau-Chun Lu et al., entitled &#34;Half-V DD  Bit-Line Sensing Scheme in CMOS DRAM&#39;s&#34;, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 4, August 1980, pp. 451-454. 
     FIG. 1 is a diagram showing schematically the whole structure of a conventional half-Vcc precharging DRAM. 
     Referring to FIG. 1, the conventional DRAM comprises a memory cell array 1 in which a plurality of memory cells each having digital information of an &#34;H&#34; or &#34;L&#34; level stored in the form of charges are arranged in a matrix of rows and columns. A row address buffer 2 receiving a row address (A0 to A9) externally applied for generating an internal row address, and a row decoder 3 responsive to an internal row address from the row address buffer 2 for generating a signal for selecting one row in the memory cell array 1, are provided for selecting a word line. A column address buffer 4 receiving a column address externally applied for generating an internal column address and a column decoder 5 responsive to an internal column address from the column address buffer 4 for generating a signal for selecting one column in the memory cell array 1, are also provided with the DRAM for selecting a column or a bit line pair. For communicating data signals with external circuitry, in the DRAM, further provided are a (sense amplifier+I/O (input/output)) block 6 comprising sense amplifiers for sensing and amplifying information on each column (bit line) in the memory cell array 1 and I/O gates responsive to an output of the column decoder 5 for connecting the selected column to a read/write amplifier 7, an input buffer 8 receiving input data D IN  externally applied for applying the same to the read/write amplifier 7, and an output buffer 9 receiving the data from the read/write amplifier 7 for applying output data D OUT  to the exterior. The read/write amplifier 7 amplifies an applied signal and applies the same to a circuit in the subsequent stage. 
     As peripheral circuits, there are provided row clock generator 10 responsive to a signal RAS (row address strobe) externally applied for generating signals defining timing operations associated with row selection, a write control circuit 12 responsive to a write enable signal WE externally applied for generating a signal designating a read/write operation of the DRAM, and a V BB  generator 13 for generating a voltage V BB  for supplying a precharge voltage of bit lines in the memory cell array 1. 
     FIG. 1 shows an address multiplexing scheme in which a row address and a column address are applied in a time divisional manner. Operation timing of the row address buffer 2 is provided by the signal RAS, and operation timing of the column address buffer 4 is defined by a signal CAS. 
     FIG. 2 shows an example of a structure of the memory cell array in the conventional DRAM, showing the structure of a block 100 represented by a broken line shown in FIG. 1. In FIG. 2, only the structure associated with a pair of bit lines BL and BL and two word lines WL i  and WL i+1  is typically shown. 
     Referring to FIG. 2, a memory cell 6 for storing digital information of &#34;H&#34; or &#34;L&#34; level in the form of charges comprises a single transistor Tr and a single capacitor C. The memory capacitor C has one electrode (a cell plate) connected to a predetermined potential Vcp and another electrode (a storage node) connected to a drain of the transistor Tr. The transistor Tr has its source connected to the bit line BL and its gate connected to the word line WLi. 
     In order to differentially amplify a signal voltage on the pair of bit lines BL and BL, the bit line pair is provided with a sense amplifier SA. The sense amplifier SA comprises a pMOS sense amplifier responsive to a sense amplifier activating signal S for boosting a potential on a bit line of a higher potential to a power-supply potential Vcc level and an nMOS sense amplifier responsive to a sense amplifier activating signal S for discharging a potential on a bit line of a lower potential to a ground potential. The pMOS sense amplifier comprises two pMOS transistors P1 and P2 having their gates and drains cross-coupled. The nMOS sense amplifier comprises two nMOS transistors N1 and N2 having their gates and drains cross-coupled. 
     In order to maintain each of the bit lines BL and BL at a precharge potential V BB  after activation of a word line selected by an external address is completed (or in stand-by state), a precharge/equalize block 30 is provided. The precharge/equalize block 30 comprises an equalizing transistor T1 responsive to an equalize signal EQL for electrically connecting the paired bit lines BL and BL, a precharging transistor T2 responsive to the equalize signal EQL for transmitting to the bit line BL a precharge voltage V BB  from the V BB  generator (see FIG. 1), and a precharging transistor T3 responsive to the equalize signal EQL for transmitting to the bit line BL the precharge potential V BB  from the V BB  generator. The bit lines BL and BL are connected, respectively, to data input/output buses I/O and I/O through transfer gate transistors T4 and T5 which are in turn responsive to a column selecting signal (column decode signal) CD from the column decoder (see FIG. 1) to be turned on. 
     The sense amplifier activating signals S and S and the equalize signal EQL are generated in response to the signal RAS which is a basic operation timing signal of the DRAM. 
     Furthermore, the precharge voltage V BB  is generally set to half of the operating power-supply voltage Vcc. 
     FIGS. 3A to 3C are diagrams showing cross-sectional structure of a memory cell, an electron potential under each portion and a read-out waveform which appears on a bit line, in the conventional dynamic RAM. FIG. 3A shows cross-sectional structure of the memory cell. In FIG. 3A, a memory cell 6 comprises an N +   type impurity diffusion layer 2 constituting a bit line BL (or BL) formed in a predetermined region on a P type semiconductor substrate 3 and an N +   type diffusion layer 1 constituting a storage node SN of the memory cell. A transistor portion of the memory cell comprises a gate 5, constituting a word line WL, and the N +   type impurity diffusion layers 1 and 2. Storage capacitance C of the memory cell comprises a cell plate 4 coupled to a cell plate potential Vcp, an insulating film 9 and the storage node SN. FIG. 3B is a diagram showing electron potentials under the storage node SN, the word line WL and the bit line BL. The electron potential under the storage node SN shows electron potentials formed when the memory cell stores information of the &#34;L&#34; and &#34;H&#34; levels, respectively. The electron potential under the word line WL shows electron potentials formed under the word line when a ground potential GND and Vcc/2+V TH  (where V TH  is a threshold voltage of the transistor Tr of the memory cell) are applied on the word line, respectively. The electron potential under the bit line BL shows an electron potential formed when the bit line BL is precharged to Vcc/2. 
     FIG. 3C is a diagram showing by an electron potential a read-out waveform generated when information stored in the memory cell is read out to the bit line before sensing (or a sense amplifier is activated). When the memory cell having information of the &#34;L&#34; level is accessed, the electron potential under the bit line is increased by ΔV LR , with respect to the precharge level. On the other hand, when the memory cell having information of the &#34;H&#34; level is accessed, the electron potential under the bit line is decreased by ΔV HR , relative to the precharge level. 
     FIG. 4 is a waveform diagram showing an operation in reading out information of the &#34;H&#34; level in the conventional dynamic RAM shown in FIGS. 1 and 2. Referring now to FIGS. 1 to 4, description is made on an operation for reading out the information of the &#34;H&#34; level in the conventional dynamic RAM. When a signal RAS is rendered active in synchronization with the fall of the external RAS signal which is a basic timing signal of the DRAM, an external address is accepted in the dynamic RAM. When the memory cell stores the information of the &#34;L&#34;  level, charges of a ground potential level are stored in the storage node SN. On the other hand, when the memory cell stores the information of the &#34;H&#34; level, charges of a Vcc level are stored therein. 
     After the RAS signal falls, a single word line is selected in response to the accepted external address and a potential on the selected word line WLi rises by word line driving means included in an output portion of the row decoder. In the case where the memory cell stores the information of the &#34;L&#34; level, electrons start to flow from the memory cell to the bit line BL (it is assumed that BL represents a bit line connected to the selected memory cell) when the potential on the selected word line WLi exceeds V TH . When the potential on the word line WLi attains Vcc/2+V TH , all charges stored in the memory cell flow out on the bit line BL, so that the electron potential under the bit line BL is increased by a very small voltage ΔV LR . On the other hand, as shown in FIG. 4, in the case where the memory cell stores information of the &#34;H&#34; level, electrons start to flow from the bit line BL to the memory cell when the potential on the selected word line WLi exceeds Vcc/2+ V TH . Since the capacitance of a bit line is sufficiently larger than storage capacitance of a memory cell, the memory cell is filled with electrons. As a result, the electron potential under the bit line BL is decreased by a very small voltage ΔV HR . On the other hand, a potential on a reference bit line BL paired with the bit line BL does not change at all and remains at a precharge level Vcc/2 because the transistor in the memory cell connected to the reference bit line remains in an off state. The potential Vcc/2 on the reference bit line BL and the potential on the bit line BL to which data is read out are compared by the sense amplifier SA which is activated in response to the rise of the sense amplifier activating signal S (and the fall of the signal S), so that a potential on the bit line of a lower level, of the pair of bit lines BL and BL is amplified to a ground potential GND level and a potential on the bit line of a higher level is amplified to a Vcc level. When the precharge potential on bit lines is Vcc/2, an &#34;L&#34; read-out voltage ΔV LR  and an &#34;H&#34; read-out voltage ΔV HR  are equal to each other. 
     When an RAS active cycle (the time period during which the signal RAS is at a low level) is completed, information on the bit line, amplified by the sense amplifier SA and then latched thereat, is written to the selected memory cell. Then, a word line driving signal and the sense amplifier activating signals S and S are made inactive, and the equalize signal EQL rises, so that the bit lines are equalized and precharged. 
     In the foregoing description, the &#34;L&#34; read-out voltage indicates the magnitude of change in potential, utilizing as a reference a precharge level, which appears on the bit line connected to the selected memory cell after the potential on the word line rises and before a sensing operation by activation of the sense amplifier starts, when the selected memory cell stores information of the &#34;L&#34; level. Similarly, the &#34;H&#34; read-out voltage indicates the magnitude of change in potential, utilizing as a reference a precharge level, which appears on the bit line connected to the selected memory cell after the potential on the word line rises and before the sensing operation by activation of the sense amplifier starts, when the selected memory cell has information of the &#34;H&#34; level. 
     In restoring information in the selected memory cell, writing information in a normal write mode and refreshing information stored in the memory cell in a refresh cycle, information of a full Vcc level can be written to the memory cell by boosting the potential on the word line WLi to more than Vcc+V TH . In FIG. 4, a broken line represents an example in which the potential on the word line WLi is boosted up to more than Vcc+V TH  and &#34;H&#34; information of the full Vcc level is restored at the end at an RAS active cycle (the time period during which the RAS signal is at the &#34;L&#34; level). 
     As capacity of the dynamic RAM is increased, the cell structure is being made smaller. At the same time, a junction breakdown voltage, a source/drain breakdown voltage of a transistor, a dielectric breakdown voltage of a gate oxide film or the like are decreased. Thus, in a large capacity DRAM, it becomes difficult to boost the potential on the word line up to more than Vcc+V TH . Assuming that a voltage of a high level of the word line is a power-supply voltage Vcc, the following problem occurs. 
     FIGS. 5A and 5B are a diagram showing an electron potential in a memory cell and a diagram showing by an electron potential a read-out waveform, respectively, assuming that the voltage of a high level of the word line is Vcc, in a conventional dynamic RAM. As shown in FIG. 5A, if the level of the word line is boosted only to the Vcc level, only charges of the (Vcc-V TH ) level are stored in the storage node SN in the memory cell when writing &#34;H&#34; information. Thus, the change in electron potential which appears on the bit line when information stored in the memory cell is read out to the bit line is to be as shown in FIG. 5B. More specifically, the &#34;L&#34; read-out voltage ΔV LR  and the &#34;H&#34; read-out voltage ΔV HR  have a relation ΔV LR  &gt;ΔV HR . As a result an operating margin of the sense amplifier is unbalanced, so that a malfunction of the sense amplifier occurs. For example, the sense amplifier does not correctly amplify a signal voltage on the bit line at the time of sensing operation. 
     The prior art similar to the structure of the present invention is described in an article by S. Saito et al. entitled &#34;A 1MB CMOS DRAM with Fast Page and Static Column Modes&#34;, IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 1985, PP. 252-253. This prior art discloses a &#34;complementary capacitor coupled dummy cell&#34; coupled to a dummy word line and a bit line so as to set a reference bit line to a correct midpoint of Vcc in an active cycle. However, in the prior art, a voltage bootstrapped to more than Vcc is applied to the word line. Consequently, the prior art does not consider a problem of imbalance between the &#34;H&#34; read-out voltage and the &#34;L&#34; read-out voltage to occur when a voltage applied to the word line is a power-supply voltage Vcc level. 
     SUMMARY OF THE INVENTION 
     One object of the present invention is to provide, for a DRAM, a method of and circuitry for improving the stability of data read out therefrom. 
     Another object of the present invention is to provide, for a DRAM, a method of and circuitry for equalizing the magnitude of difference of potential on a bit line pair, as a result of &#34;H&#34; or &#34;L&#34; data on a selected memory cell, as the cell is connected to bit line pair. 
     A further object of the present invention is to provide a DRAM in which &#34;H&#34; and &#34;L&#34; read out voltages on the bit lines have the same magnitude, without word line boosting. 
     A DRAM according to the present invention comprises circuitry for applying an equalizing potential to either one or the other bit line of paired bit lines to equalize (1) a first difference between a first potential and a second potential and (2) a second difference between the first potential and a third potential, for balanced read out of the paired bit lines, wherein the first potential appears on a reference bit line paired with a bit line connected to a memory cell selected by an external address prior to sensing thereof, the second potential appears on the bit line when the selected memory cell contains &#34;H&#34; level data and the third potential appears on the bit line when the selected memory cell contains &#34;L&#34; level data. 
     More specifically when a memory cell comprises an n channel MOS transistor, the dynamic RAM according to the present invention comprises a read-out voltage equalizer by which a potential on a bit line connected to a selected memory cell appearing before sensing operation is increased or a potential on a reference bit line paired with the selected bit line is decreased so that an &#34;L&#34; read-out voltage and an &#34;H&#34; read-out voltage can be equalized. On the other hand, when the memory cell comprises a p channel MOS transistor, the dynamic RAM of the present invention comprises a read-out voltage equalizer by which a potential on a bit line connected to a selected memory cell appearing before sensing operation is decreased or a potential on a reference bit line paired with the selected bit line is increased, thereby reducing an &#34;L&#34; read-out voltage or increasing an &#34;H&#34; read-out voltage, so that an &#34;L&#34; read-out voltage and an &#34;H&#34; read-out voltage can be equalized. 
     The operating method for a DRAM according to the present invention comprises the step of applying an equalizing potential to one or the other of the paired bit lines to equalize (1) a first difference between the above described first potential and the above described second potential and (2) a second difference of potential between the first potential and the above described third potential, for balanced read out of the paired bit lines. 
     In the dynamic RAM according to the present invention, the magnitude of a differential potential signal appearing on paired bit lines is equalized in reading &#34;H&#34; level data and in reading &#34;L&#34; level data, and therefore, well balanced read out voltage is supplied to a sense amplifier to improve sensing margin thereof and to ensure stable reading operation. 
     More specifically in the dynamic RAM according to the present invention, since the potential on the bit line connected to the selected memory cell is increased (, or decreased in p type memory cell) or the potential on the reference bit line paired with the bit line is decreased (, or increased in p type memory cell) so that the &#34;L&#34; read-out voltage and the &#34;H&#34; read-out voltage can be equalized, the operating margin of a sense amplifier is balanced and a stable read operation is ensured even in the case where the word line is not boosted up to more than a power-supply voltage. 
    
    
     These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing schematically the whole structure of a conventional DRAM having a half-Vcc precharge scheme; 
     FIG. 2 is a diagram showing structure of a pair of bit lines in a memory cell array in the conventional DRAM and portions associated therewith; 
     FIG. 3A is a diagram showing a cross-sectional structure of a memory cell; 
     FIG. 3B is a diagram showing electron potentials under portions of a memory cell; 
     FIG. 3C is a diagram showing electron potentials under a bit line in reading out &#34;L&#34; information and &#34;H&#34; information stored in the memory cell; 
     FIG. 4 is a waveform diagram of signals showing a read operation of the conventional DRAM; 
     FIG. 5A is a typical diagram showing electron potentials under portions of the memory cell formed when a voltage applied to a word line is at an operating voltage level; 
     FIG. 5B is a diagram showing an electron potential on a bit line formed when information stored in the memory cell having the electron potentials shown in FIG. 5A is read out; 
     FIG. 6 is a diagram showing structure of main portions of a memory cell array in a DRAM according to an embodiment of the present invention, showing structure of a pair of bit lines and portions associated therewith; 
     FIG. 7 is a waveform diagram of signals showing a read operation in the DRAM according to an embodiment of the present invention; 
     FIG. 8 is a diagram showing schematically structure of a memory cell array in a DRAM according to another embodiment of the present invention; and 
     FIG. 9 is a diagram showing structure of main portions of a memory cell array in a DRAM employing a dummy reversal technique according to another embodiment of the present invention, showing a pair of bit lines and portions associated therewith. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIGS. 5A and 5B, electron potentials on a bit line at the time of reading out &#34;L&#34; information and &#34;H&#34; information before sensing are shown. It is assumed that a memory cell comprises an n channel MOS transistor and a potential on a reference bit line is decreased by ΔV B . Assuming that capacitance of a bit line is represented by C B  and storage capacitance of a memory cell is represented by C S , the potential on the bit line at the time of reading out the &#34;L&#34; information is given by the following equation; 
     
         V.sub.LR =Vcc/2-(C.sub.S ·Vcc/2)/(C.sub.B +C.sub.S) 
    
     and the potential on the bit line at the time of reading out the &#34;H&#34; information is given by the following equation: 
     
         V.sub.HR =Vcc/2+C.sub.S ·(Vcc/2-V.sub.TH)/(C.sub.B +C.sub.S) 
    
     Thus, a middle potential therebetween is as follows: ##EQU1## 
     Thus, when ΔV B , which is the amount of decrease in potential on the reference bit line, is defined as follows; 
     
         ΔV.sub.B =C.sub.S ·V.sub.TH /2(C.sub.B +C.sub.S)(2), 
    
     an &#34;L&#34; read-out voltage and an &#34;H&#34; read-out voltage are equalized. The &#34;L&#34; read-out voltage and the &#34;H&#34; read-out voltage indicate the difference in the potential between a bit line (BL) and a reference bit line (BL), respectively, before a sense amplifier is activated for performing sensing operation. 
     FIG. 6 is a diagram showing a structure of a dynamic RAM according to an embodiment of the present invention, including a structure for decreasing a potential on a reference bit line. In the structure shown in FIG. 6, a dummy word line 11 coupled to a bit line BL through a capacitance 20 and a dummy word line 10 coupled to a reference bit line BL through a capacitance 21 are additionally provided, in addition to the structure of the conventional dynamic RAM shown in FIG. 2. Both capacitance values of the capacitances 20 and 21 are represented by Ca. The dummy word lines 10 and 11 are driven by signals DWL0 and DWL1 which are responsive to an external address for rendering active (or at an &#34;L&#34; level) a dummy word line which is capacitor-coupled to a reference bit line paired with a bit line connected to a selected memory cell. More specifically, if and when a read-out voltage appears on the bit line BL, and the bit line BL provides a reference level, the signal DWL0 on the dummy word line 10 is rendered active (or at a low level). The dummy word line driving signals DWL1 and DWL0 are generated by a dummy word line selector 40 which is responsive to a row address signal Ai for rendering one of the signals DWL1 and DWL0 active. 
     When a row address designates the word line WLi, it is necessary that the signal DWL0 on the dummy word line 10 is rendered active. On the other hand, when a row address designates the word line WL i+1 , it is necessary that the signal DWL1 is rendered active. The dummy word line selector 40 can be easily implemented by a structure in which the signals DWL0 and DWL1 are selectively rendered active in response to &#34;H&#34; and &#34;L&#34; levels of 1-bit of the row address, for example. 
     Similarly to the conventional example, the pair of bit lines BL and BL is provided with a sense amplifier SA responsive to sense amplifier activating signals S and S being rendered active for differentially amplifying the potential difference between the bit lines BL and BL, and a precharge/equalize circuit 30 responsive to an equalize signal EQL for maintaining potentials on the bit lines BL and BL at a Vcc/2 level after an RAS active cycle is completed. 
     FIG. 7 is a waveform diagram showing an operation at the time of reading out &#34;H&#34; information in the dynamic RAM shown in FIG. 6 according to an embodiment of the present invention. Referring now to FIGS. 6 and 7, description is made on the principle of the operation of the dynamic RAM according to an embodiment of the present invention. During a precharge time period, an equalize signal EQL is at the &#34;H&#34; level. Consequently, both the bit lines BL and BL are short-circuited by the precharge/equalize circuit 30 and held at a precharge level of Vcc/2. Then, when an RAS signal enters an active state or a low level in synchronization with an external RAS signal, an external address is accepted in the dynamic RAM. Then, an equalize signal EQL falls, so that each of the bit lines is rendered electrically floating. 
     It is assumed that the accepted external address designates a memory cell 6 connected to the bit line BL. In this case, the dummy word line selector 40 is responsive to the accepted external address for changing to an active state, i.e., to the &#34;L&#34; level the dummy word line activating signal DWL0 applied to the dummy word line 10 capacitor-coupled to the reference bit line BL providing a reference level with respect to the bit line BL by the capacitance 21. The dummy word line activating signal DWL1 applied to the other dummy word line 11 remains in an inactive state, i.e., at the &#34;H&#34; level. Since the dummy word line 10 at the &#34;L&#34; level and the reference bit line BL are capacitor-coupled through the capacitance 21, a potential on the reference bit line BL is decreased from the precharge level Vcc/2 to the level of (Vcc/2)-ΔV B , where ΔV B  is a value obtained by the equation (2). 
     Then, a single word line is selected in response to the external address and potential on the selected word line WLi rises to be at a power-supply voltage Vcc level, so that the change in potential responsive to information stored in a memory cell connected to the selected word line WL appears on the bit line BL. In FIG. 7, a case is shown in which the selected memory cell stores information of the &#34;H&#34; level. Then, the sense amplifier activating signal S rises (the signal S falls) and the sense amplifier SA is activated, so that sensing operation (detection and amplification of the potential difference between the pair of bit lines BL and BL) starts. 
     As described above, the potential on the reference bit line BL is decreased from Vcc/2 by ΔV B  so that the &#34;L&#34; read-out voltage and the &#34;H&#34; read-out voltage are equalized, so that stable operation is obtained even if the word line WLi is not boosted up to more than the power-supply voltage Vcc. 
     Although in the present embodiment, an example was shown in which the potential on the selected dummy word line falls before the potential on the selected word line WLi rises, any timing after completion of the equalize cycle and before the sensing operation by which the sense amplifier is activated may be used, in which case the same effect can be obtained. Description is now made on capacitance values Ca of the capacitances 20 and 21. 
     If and when the amplitudes of the dummy word line activating signals DWL0 and DWL1 applied to the dummy word lines 10 and 11 are the power-supply voltage Vcc, the magnitude ΔV B  of decrease in potential on the reference bit line capacitor-coupled to an activated dummy word line is obtained by the following equation, assuming that capacitance of the bit line (including Ca) is represented by C B  : 
     
         ΔV.sub.B =Ca·Vcc/C.sub.B 
    
     Thus, from the equation (2), the following equation is obtained: ##EQU2## An aspect of an MOS transistor is that a threshold voltage V TH  of the transistor Tr of the memory cell is increased when the voltage Vcc applied to the gate thereof is increased. The ratio V TH  /Vcc is almost constant, i.e., about 0.2 in the normal operating range of Vcc. 
     When the voltage Vcc applied to the gate is increased, the threshold voltage V TH  of the MOS transistor is increased for the following reason. In a semiconductor device such as a memory, a bias potential is generally applied to a substrate so as to stabilize operation of transistors by, for example, preventing the change in threshold voltage of the transistor and preventing the back gate effect. The substrate bias potential is generated from a power-supply voltage Vcc using a charge pump or the like. Accordingly, the value of the bias potential is changed such that the higher the power-supply voltage Vcc (the voltage applied to the gate) is, the deeper bias is. When the substrate bias becomes deep, the threshold voltage of the MOS transistor formed on the substrate is increased. Thus, when the power-supply voltage Vcc, i.e., the voltage applied to the gate is increased, the threshold voltage of the MOS transistor is also increased. 
     As described above, since V TH  /Vcc=0.2 in the normal operating range of the power-supply voltage Vcc, the capacitance value Ca is as follows: ##EQU3## 
     In addition, if C B  &gt;&gt;C S  (this relation is generally satisfied in a large capacity DRAM), 
     
         Ca=C.sub.S /10 
    
     Thus, if a coupling capacitance of about 1/10 of the storage capacitance of the memory cell is provided, an operation without any loss of stable operating margin is ensured. Furthermore, since the amount of ΔV B  of change in potential on the reference bit line is as small as 10 mV (C B  ≈0.5 pF, C S  ≈50 fF), a low power consumption characteristic which is an advantage of a Vcc/2 bit line precharge technique is maintained. 
     In a scheme in which a potential on the bit line connected to the selected memory cell is increased, a potential on the bit line is increased by the same magnitude as that of decrease in the potential of the reference bit line in the above described embodiment. This scheme is easily achieved if the same structure as that shown in FIG. 6 is used and dummy word lines are provided which attain a high level in an active state before sensing operation in which the sense amplifier SA is activated. More specifically, it is necessary that in the structure as shown in FIG. 8, the signals DWL0 and DWL1 in which the active state is the &#34;H&#34; level, are used as dummy word line activating signals, and a dummy word line, capacitor-coupled to the (selected) bit line connected to the selected memory cell, is selected as the dummy word line to increase a potential on the selected bit line. For example, when the bit line connected to the selected memory cell is a bit line BL in FIG. 8, the dummy word line 11 is selected to change the dummy word line driving signal DWL1 from a low level to a high level. As a result, the bit line BL, in a floating state, is capacitor-coupled to the dummy word line 11 of a high level through the capacitance 20, and the potential of the selected bit line is increased by ΔV B . A dummy word line can be selected by using the same structure as that of the dummy word line selector 40 shown in FIG. 6 with the signal levels or conductivity types of transistors thereof reversed. Such a structure may be employed in which a potential on the bit line connected to the selected memory cell is increased to obtain the same effect as the above described embodiment. In other words, with such a structure, the &#34;H&#34; read-out voltage and &#34;L&#34; read-out voltage can be equalized, so that operating margin of the sense amplifier can be improved. 
     FIG. 9 is a diagram showing an example of structure of a memory cell array comprising dummy word lines WL0 and WL1, which has been conventionally often used. A memory cell 6 and a dummy cell 6&#39; have the same structure and are connected to the same bit line. In a dummy reversal technique, a potential on only the dummy word line WL0 falls immediately before a single word line WLi is selected in response to an external address. Selection of word line WLi raises potential on the selected word line WLi. Thereafter, information is read out. Precharging of a bit line is performed when accessing to a memory begins. The dummy word lines WL0 and WL1 are at an &#34;H&#34; level at the precharge time and at the standby time. By employing the dummy reversal technique, it is intended that coupling noise between the word line and the bit line through gate capacitance of a transistor Tr in a selected memory cell is cancelled. A dynamic RAM of the dummy reversal technique is described in, for example, an article by Suzuki et al., entitled &#34;A 128K Word×8 Bit Dynamic RAM&#34;, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, Oct. 1984, PP. 624-626. In the case of the dynamic RAM of the dummy reversal technique having such structure, if the size of the MOS transistor 5 included in the dummy cell 6&#39; is appropriately adjusted, a potential on the bit line connected to the selected memory cell can be increased. The size of the transistor 5 (for example, the width, the length or the area of a gate of the transistor) in the dummy cell 6&#39; is adjusted such that the difference between the increase of the potential on the bit line due to the gate capacitance of the transistor Tr of the memory cell 6 and the magnitude of decrease in potential on the bit line due to the gate capacitance of the transistor 5 in the dummy cell 6&#39; provides the increased potential on the bit line by the above described ΔV B . Alternately, if, in the DRAM of the dummy reversal technique, a potential of a signal applied to the dummy word line is reversed and the gate capacitance of the transistor in the dummy cell may be the above described value Ca, the same effect as the above described embodiments can be obtained. 
     Although in the above described embodiments, cases were described in which a memory cell comprises an n channel MOS transistor, the same problem occurs if the memory cell comprises a p channel MOS transistor. In this case, polarity of each signal is only reversed. Consequently, a precharge potential on a bit line connected to a selected memory cell may be decreased or a precharge potential on a reference bit line paired with the bit line may be increased, on the basis of the same principle, in which case the same effect as the above described embodiment can be obtained. 
     As described in the foregoing, according to the present invention, since a precharge potential on a bit line connected to a selected memory cell is increased (, or decreased in p type memory cell) or a precharge potential on a reference bit line paired with the bit line is decreased (or increased in p type memory cell) so that an &#34;L&#34; read-out voltage and an &#34;H&#34; read-out voltage are equalized to each other, a stable reading out operation can be ensured without losing operating margin of a sense amplifier even if a word line is not boosted up to more than a power-supply voltage Vcc. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.