Abstract:
Systems and methods to achieve a digital audio interface having automatic rate detection and tracking of digital audio streams have been achieved. The system comprises a digital controller working in conjunction with an analog phase-locked loop (PLL). It removes the need to know or communicate in advance the rate at which the interface will be operating, so allowing asynchronous switching between different audio streams. The digital controller acts as a phase-lock loop by modifying the feedback divide ratio of the PLL in order to minimize the phase error between the device clock and an arbitrary audio interface clock.

Description:
[0001]    This application claims benefit to U.S. Provisional Application Ser. No. 61/278,645, filed on Oct. 8, 2009, which is commonly owned, and is incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates generally to digital audio COder-DECoders (CODECs) and relates more specifically to synchronization of a master clock with digital audio signals coming from separate clock domains. 
         [0004]    2. Description of the Prior Art 
         [0005]    Digital audio CODECs typically use a stable master clock as a reference and a phase-locked loop (PLL) to generate the frequencies required for processing the audio data. When used in slave mode, these devices may also be required to maintain synchronization with digital audio signals coming from a separate clock domain, These signals will not be synchronous to the master clock and they may also drift with respect to the master clock. In a complex system with a multiplicity of data sources, the signal frequencies may also change depending on the source. The slave device must therefore be capable of tracking a range of incoming data streams so that audio signal samples are not lost. 
         [0006]    Current systems require knowledge of the incoming audio data rate so that an appropriate “gearing ratio” can be selected. This requires some form of handover protocol when switching between audio sources and precludes either switching between audio sources on the fly or switching to an unknown audio source. 
         [0007]    It is a challenge for the designers of CODECs to achieve systems capable to automatically detecting a change in data-rate, selecting the correct gearing ratio, and re-establishing synchronization with the new audio source, 
         [0008]    There are known patents or patent publications dealing with synchronization with digital audio/video sources. 
         [0009]    U.S. Patent Publication (US 2008/0198958 to Shin) proposes an apparatus and method for compensating for a phase jump of a reference signal in a digital Phase-Locked Loop (PLL)/Frequency-Locked Loop (FLL). The apparatus includes a phase discriminator for comparing a phase of an external clock signal (i.e., the reference signal) with a phase of an internal clock signal to determine a phase difference between the two signals, a phase jump compensator, and for correcting the phase difference by using a phase jump correction value obtained in the estimation process, and a Low Pass Filter (LPF) for filtering a high-frequency component of the corrected phase difference. 
         [0010]    U.S. Pat. No. 7,499,106 to Gudmunson et al. discloses a method and system for synchronizing video information derived from an asynchronously sampled video signal providing a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC. 
         [0011]    U.S. Pat. No. 5,790,615 to Beale et al. describes a digital phase-lock loop network that provides input and output clock signals to a digital data receiving system generally, and particularly to a data buffer contained therein. The digital phase-lock loop network provides bit-clock synchronization using a fixed input clock and an output clock having a variable frequency that is adjusted to correspond to the average input rate of the data samples into the data buffer. The digital phase-lock loop network allows the data buffer to be operated as a temporary storage device maintaining a nominal number of data samples therein at all times by avoiding any overflow and underflow data handling conditions that may otherwise cause loss of data. The digital phase-lock loop network of the present invention is particularly suited for the Eureka-147 system, which has become a worldwide standard for digital audio broadcasting (DAB) technology. 
         [0012]    Furthermore U.S. Patent Publication (US 2008/0075152 to Melanson) teaches a hybrid analog/digital phase-lock loop with high-level event synchronization providing a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and synchronizing the output clock to high-level events. A numerically-controlled analog oscillator provides a clock output and a counter divides the frequency of the clock output to provide input to a digital phase-frequency detector for detecting an on-going phase-frequency difference between the timing reference and the output of the counter. A synchronization circuit detects or receives a high-level event signal, and resets the on-going phase-frequency difference and optionally the counter to synchronize the clock output with the events. 
       SUMMARY OF THE INVENTION 
       [0013]    A principal object of the present invention is to achieve systems and methods capable to automatically detecting a change in data-rate, selecting the correct gearing ratio, and re-establishing synchronization with the new audio source, 
         [0014]    A further object of the invention is to remove the need for a handover procedure when switching between audio sources 
         [0015]    A further object of the invention is to enabling a system to switch between audio data sources of unknown rates. 
         [0016]    A further object of the invention is to achieve a system for the automatic rate detection and tracking of digital data streams. 
         [0017]    A further object of the invention is to achieve a system, which applies in particular to a digital audio interface that operates at a number of well-defined and well-spaced rates, but could be applied to other similar systems. 
         [0018]    A further object of the invention is to remove the need to know or communicate in advance the rate at which the interface will be operating, so allowing asynchronous switching between different audio data streams. 
         [0019]    Moreover an object of the invention is to track deviations and drift between actual and ideal rate of date streams. 
         [0020]    In accordance with the objects of this invention a method for a digital audio interface, which doesn&#39;t require a handover procedure when switching between audio sources and allowing to switch between audio data sources of unknown rates, has been achieved. The method invented comprises the steps of: (1) providing a digital controller that works in conjunction with a first PLL, (2) using a I2S protocol comprising a data signal and at least two clock signals, wherein a first clock is used as a sampling clock for a data signal and a second clock is used to define word boundaries, and (3) detecting automatically an incoming I2S rate by completely determining a correct group of rates. Furthermore the method invented comprises the steps of (4) synchronizing both clocks by the digital controller by computing an offset deltax that is applied to a nominal feedback divide ratio of the first PLL, wherein said deltax is computed based on a current phase error and its derivative, and (5) minimizing a phase error between the first clock and the second clock by deploying the digital controller as another phase-lock loop that modifies a feedback divide ratio of the first PLL. 
         [0021]    In accordance with the objects of this invention a digital audio interface, using an I2S protocol, without the need for a handover procedure when switching between audio sources, has been achieved. The audio interface invented comprises a fractional-N loop PLL, used to derive a device clock from a master clock, and a digital tracking controller, acting itself as a phase-lock loop by modifying a feedback divide ratio of the fractional-N loop PLL in order to minimize a phase error between the device clock and an arbitrary audio interface clock, having inputs and an output, wherein a first input is a nominal divide ratio, a second input is a I2S word clock, a third input is a lock detect signal from the fractional-N loop PLL, and a fourth input is a fractional-N signal from the fractional-N loop PLL, and the output is an offset deltax signal applied to a nominal feedback divide ratio of the fractional-N loop PLL in order to achieve a lock between the device clock and the I2S word clock. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0022]    In the accompanying drawings forming a material part of this description, there is shown: 
           [0023]      FIG. 1  illustrates an overall block diagram of a digital I2S tracking controller and analog phase-lock loop. 
           [0024]      FIG. 2  shows an internal block diagram of the I2S tracking controller 
           [0025]      FIG. 3  shows in a table DIFFERENCE register values used to automatically detect and decode an I2S rate change. 
           [0026]      FIG. 4  illustrates in a table PLL clock prescaler values for I2S settings. 
           [0027]      FIG. 5  illustrates a flowchart of a method invented for a digital audio interface, which doesn&#39;t require a handover procedure when switching between audio sources and allowing to switch between audio data sources of unknown rates. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0028]    Systems and methods for a digital controller for automatic rate detection and tracking of audio interface clocks are disclosed. 
         [0029]    A digital audio interface uses a protocol known as Inter-IC Sound (I2S, which consists of (at a minimum)) two clock signals and a data signal. The first clock (“bit” clock) is used as a sampling clock for the data signal. The second clock (“word” clock) or “LR” clock) is used to define the word boundaries and can also be used to split the data between left and right audio channels. All that is significant here is that the I2S word clock runs at the sample rate of the audio data, e.g. for 44.1 kilo samples per second (ksps) CD audio data the I2S word clock runs at 44.1 kHz. The I2S word clock is simply referred to as the I2S clock in the remainder of the description. 
         [0030]    The present invention comprises a digital controller that works with a phase-lock loop (PLL). The PLL is a fractional-N loop, used to derive the device clock from the master clock. The digital controller itself acts as a phase-lock loop by modifying the feedback divide ratio of the PLL in order to minimize the phase error between the device clock and an arbitrary audio interface clock. 
         [0031]      FIG. 1  illustrates an overall block diagram of a digital I2S tracking controller and analog phase-lock loop. The PLL comprises a phase frequency detector/charge pump unit (PFD/CP)  1 , a loop filter  2 , a voltage controlled oscillator (VCO)  3 , a feedback divider  4 , a Sigma-Delta Modulator  5 , a Lock-Detect Unit  6 , and the I2S tracking controller  7 . The PLL clock frequency  12  is part of the inputs to the I2S tracking controller  7 . 
         [0032]    The PLL is a fractional-N loop and the frequency of the VCO  3  is reduced by a division by a factor N in a first frequency reduction block  8 . In a second frequency reduction block  9  the frequency of the VCO  3 , which has already reduced been in block  8 , is further been reduced by factor M to accommodate to the frequency required by the device clock. In the preferred embodiment N=4 and M=8 since the I2S tracking controller requires a faster clock than the device clock. Other values of N and M could be chosen for this and other systems. 
         [0033]    When the system is in lock, the VCO clock  3  is phase locked to the master clock  10  and is also phase-locked to the I2S clock  11 . In order to keep the overall system stable, the I2S tracking controller  7  operates with a much lower bandwidth than the analog PLL. 
         [0034]      FIG. 2  shows an internal block diagram of the I2S tracking controller  7 . The clock from the analog PLL is divided by a prescaler  20 , to reduce the high frequency PLL signal  12  to a lower frequency by integer division, and used to increment the COUNTER register  21  by 1. The I2S clock  11  is used to transfer the COUNTER  21  contents to the CAPTURE  22  block and to increment the COMPARE register  23  by 256 (0×100). COMPARE register  23  is subtracted from CAPTURE  22  by unit  24  to calculate the phase error (PE)  27 , and this together with its derivative PE′  26 , gained from block PREVIOUS PE  25 , is fed into the CONTROL block  28 . Once every update cycle, the CONTROL block  28  computes the offset “deltax”, as shown in  FIG. 1  the X+ΔX input to the Sigma-Delta Modulator  5 , that should be applied to the nominal feedback divide ratio of the analog PLL. When the I2S tracking controller  7  is locked, the update cycle runs at approximately 10 Hz to avoid producing audible artifacts. 
         [0035]    When the system has achieved synchronization with the I2S clock  11 , the phase error will be zero, which implies that there are exactly 256 (prescaled) PLL clock  12  cycles per I2S clock  11  cycles. The Controller  28  could also be designed alternatively for other numbers of PLL clock cycles per I2S clock cycles, e.g., 128, 512, or others. A PLL clock cycle per I2S clock cycles of 256 is a preferred number of cycles as a good compromise between frequency resolution and power consumption. 
         [0036]    The automatic detection of the I2S rate exploits the fact that there are only a limited number of valid I2S rates, e.g. 8 kHz, 44.1 kHz, etc. On each I2S cycle the DIFFERENCE register  28  records by how much the CAPTURE register  22  has changed. When the system is in synchronization the DIFFERENCE register  28  should always contain the value 256. If this value does not equal 256, it can indicate that the incoming I2S rate has changed and, together with the current I2S rate, it can be used to compute the new I2S rate. 
         [0037]    The DIFFERENCE register  28  values used to automatically detect and decode an I2S rate change are shown in the table of  FIG. 3 . Once the new I2S rate has been decoded, the PLL clock prescaler  20  can be updated according to the table of  FIG. 4 , showing PLL clock prescaler values for I2S rate settings. 
         [0038]    As the table of  FIG. 3  shows, the I2S tracking controller  7  is unable to distinguish between (for example) 44.1 kHz and 48.0 kHz, and it uses the same internal settings for both. However the analog PLL should lock to one VCO  3  frequency for all 48.0 kHz rates (8.0, 12.0, 16.0, 24.0, 32.0, 48.0 and 96.0 kHz) and another VCO frequency for all 44.1 kHz rates (11.025, 22.05, 44.1 and 88.2 kHz). By setting the nominal divide ratio (see  FIG. 1 ) such that the nominal VCO frequency is mid-way between the 48.0 kHz and 44.1 kHz settings, the sign of the “deltax” correction applied by the I2S tracking controller  7  to the sigma-delta modulator  7  can be used to distinguish between the two groups of rates. This allows the controller to completely determine the incoming I2S rate, and this information can be used by the rest of the system to select appropriate settings. 
         [0039]    It is obvious that the digital controller can not only distinguish between 44.1 kHz and 48.0 kHz as shown above but also for other different I2S rates, having the same internal settings, such as 11.025 kHz and 12.0 kHz, or 22.05 kHz and 24.0 kHz, etc as shown in the table of  FIG. 3 . In summary, the correct group of I2S rates is determined by the digital controller by setting a nominal divide ratio such that a nominal frequency of a VCO of the first PLL is set mid-way between an upper and a lower end of a determined I2S rate group, having both common internal settings, and a sign of a correction applied to the first PLL is used to distinguish between both groups of rates. The PLL only ever locks the VCO to one of two frequencies, one for the 44.1 kHz group of rates (11.025, 22.05, 44.1, 88.2 kHz) and one for the 48 kHz group of rates (8, 12, 16, 24, 32, 48, 96 kHz). So the nominal mid-way divide ratio is the same for all I2S rates—it is only determined by the master clock frequency  10 . 
         [0040]      FIG. 5  illustrates a flowchart of a method invented for a digital audio interface, which doesn&#39;t require a handover procedure when switching between audio sources and allowing to switch between audio data sources of unknown rates. A first step  50  describes the provision of a digital controller that works in conjunction with a first phase-lock loop. A next step  51  illustrates using an I2S protocol comprising a data signal and at least two clock signals, wherein a first clock is used as a sampling clock for a data signal and a second clock is used to define word boundaries. Step  52  describes detecting automatically an incoming I2S rate by completely determining a correct group of rates. Step  53  teaches synchronizing both clocks by the digital controller by computing an offset deltax that is applied to a nominal feedback divide ratio of the first PLL, wherein said deltax is computed based on a current phase error and its derivative. Step  54  discloses minimizing a phase error between the first clock and the second clock by deploying the digital controller as another phase-lock loop that modifies a feedback divide ratio of the first PLL. 
         [0041]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.