Abstract:
A system and method for providing, among other things, wideband phase modulation is described. Several embodiments include a scaling network for scaling an input modulation signal in accordance with a scaling parameter and thereby generating a scaled modulation signal that is applied to a voltage-controlled oscillator of a phase-locked loop. A sensing network may also be included for detecting changes in one or more parameters characterizing the voltage-controlled oscillator. A calibration adjustment network may additionally be included for adjusting the scaling parameter in accordance with the changes in the one or more parameters.

Description:
PRIORITY 
     The present application claims priority under 35 U.S.C. 119(e) to U.S. provisional application No. 60/848,604 entitled “K fm  Adjustment,” filed on Sep. 28, 2006. 
     CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application relates to and incorporates by reference U.S. Pat. No. 6,985,703, entitled, “Direct Synthesis Transmitter,” issued on Jan. 10, 2006, U.S. Pat. No. 6,774,740, entitled, “System for Highly Linear Phase Modulation,” issued on Aug. 10, 2004, U.S. Pat. No. 7,061,341, entitled, “System for Highly Linear Phase Modulation,” issued on Jun. 13, 2006, U.S. patent application Ser. No. 11/369,897, entitled, “Linear Wideband Phase Modulation System,” filed on Mar. 5, 2006, and U.S. patent application Ser. No. 11/337,965 “System for Digital Calibration of Phase-Locked Loops,” filed on Jan. 23, 2006. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to phase/frequency modulators, and more particularly, to an architecture for direct phase/frequency modulation of a phase-locked loop. 
     BACKGROUND OF THE INVENTION 
     Phase modulation schemes are very effective and are therefore widely used in communication systems. A simple example of a phase modulation scheme is quaternary phase shift keying (QPSK).  FIG. 1  shows a constellation diagram that illustrates how QPSK maps two-bit digital data to one of four phase offsets.  FIG. 2  shows a typical QPSK (or in-phase (I)/quadrature (Q)) modulator used to generate a phase-modulated signal. This technique relies on orthogonal signal vectors to realize the phase offsets—an inherently linear technique, since it depends solely on the matching of these orthogonal signals. 
     The I/Q modulator provides a straightforward approach to generating phase-modulated signals that is also suitable for more complex schemes such as wideband Code-Division Multiple Access (CDMA) and Orthogonal Frequency Division Multiplexing (OFDM) systems. It is also possible to generate the phase-modulated signals using a phase-locked loop (PLL). This approach offers reduced circuitry and lower power consumption and, as a result, finds widespread use in narrowband systems. A variation of this approach, known as two-point modulation, introduces direct modulation of the VCO to support wideband phase modulation, which unfortunately requires an accurate VCO gain. This requirement is a difficult task since the VCO gain depends on multiple factors. It would therefore be advantageous to accurately set the gain of the VCO. 
     SUMMARY OF THE INVENTION 
     A very efficient system for wideband phase modulation is provided. The system includes circuitry for periodically adjusting the gain of a voltage-controlled oscillator (VCO) used in a phase-locked loop (PLL) to synthesize the radio frequency modulated signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein: 
         FIG. 1  shows a constellation diagram that illustrates how QPSK maps two-bit digital data to one of four offsets; 
         FIG. 2  shows a diagram of a typical I/Q modulator; 
         FIG. 3  shows a PLL that is used to synthesize a radio frequency carrier signal; 
         FIG. 4  shows a mathematical model of the PLL shown in  FIG. 3 ; 
         FIG. 5  shows an integration filter; 
         FIG. 6  shows one embodiment of a fractional-N PLL using a ΔΣ modulator; 
         FIG. 7  illustrates one embodiment of a fractional-N PLL that supports direct frequency or phase modulation; 
         FIG. 8   a  shows a detailed view of a voltage-controlled oscillator; 
         FIG. 8   b  shows one embodiment of a VCO tank circuit that includes an auxiliary port to support linear phase/frequency modulation; 
         FIG. 9  shows the capacitance-voltage relationship for an accumulation-mode MOSFET device; 
         FIG. 10  shows the linear capacitance-voltage response from back to back MOSFET devices; 
         FIG. 11  shows the capacitance-voltage relationship for an accumulation-mode MOSFET device at different temperatures; 
         FIG. 12  illustrates a phase/frequency modulator with an adjustable VCO gain K FM ; 
         FIG. 13  shows a system for measuring the VCO gain K FM ; 
         FIG. 14  illustrates a phase/frequency modulator with accurate and constant VCO gain K FM  in accordance with the present invention; 
         FIG. 15   a  shows circuitry associated with a peak detector circuit;\ 
         FIG. 15   b  shows circuitry associated with a peak detector circuit that minimizes temperature effects; 
         FIG. 15   c  shows an output signal used by a peak detector circuit; 
         FIG. 16  shows a circuit for measuring the swept capacitance of the accumulation-mode MOSFET in accordance with the present invention; and 
         FIG. 17   a  details the control logic used in the VCO gain K FM  adjustment system of  FIG. 14  in accordance with the present invention; and 
         FIG. 17   b  shows a timing diagram for the control logic of  FIG. 14  in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  depicts a phase-locked loop (PLL)  305 . The PLL  305  includes a voltage-controlled oscillator (VCO)  310 , a feedback counter  320 , a phase/frequency detector (P/FD)  330 , a charge pump (CP)  340 , and an integration filter (LPF)  350 . Elements of the PLL  305  of  FIG. 3  are described by the mathematical model shown in  FIG. 4 . 
     The PLL  305  uses feedback to minimize the phase difference between a very accurate reference signal and its output (RF) signal. As such, it produces an output signal at a frequency given by
 
f VCO =Nf REF  
 
where f vco  is the frequency of the VCO  310  output signal, N is the value of the feedback counter  320 , and f REF  is the frequency of the reference signal.
 
     The VCO  310  produces an output signal at a frequency set by the control voltage v ctrl  according to
 
 v   out ( t )= A  cos(ω o   t+K   vco   ∫v   ctrl ( t ) dt ),
 
where ω o  is the free-running frequency of the VCO  310  and K vco  is the gain of the VCO  310 . The gain K vco  describes the relationship between the excess phase of the carrier Φ out  and the control voltage v ctrl  with
 
                     Φ   out     ⁡     (   S   )           v   ctrl     ⁡     (   S   )         =       K   vco     s       ,         
where K vco  is in rads/V. The VCO  310  drives the feedback counter  320 , which simply divides the output phase Φ out  by N.
 
     When the PLL  305  is locked, the phase detector  330  and charge pump  340  generate an output signal i CP  that is proportional to the phase difference Δθ between the two signals applied to the phase detector  330 . The output signal i CP  can therefore be expressed as 
                   i   CP     ⁡     (   s   )       =       K   pd     ⁢       Δ   ⁢           ⁢     θ   ⁡     (   s   )           2   ⁢           ⁢   π           ,         
where K pd  is in A/radians and Δθ is in radians.
 
       FIG. 5  depicts an integration filter  350  comprising a resistor R 1    510  and capacitors C 1    520  and C 2    530 . As shown, the integration filter  350  transforms the output signal i CP  to the control voltage v ctrl  as follows 
                   v   ctrl     ⁡     (   s   )       =         i   out     ⁡     (   s   )       ⁢     (           sR   1     ⁢     C   1       +   1           s   2     ⁢     R   1     ⁢     C   1     ⁢     C   2       +     s   ⁡     (       C   1     +     C   2       )           )         ,         
where a zero (e.g., at 1/R 1 C 1 ) has been added to stabilize the second order system and the capacitor C 2    530  has been included to reduce any ripple on the control voltage v ctrl . Combining the above relations yields the closed-loop response of the system to an input signal
 
     
       
         
           
             
               
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             = 
             
               
                 
                   
                     NK 
                     PD 
                   
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                     K 
                     VCO 
                   
                   ⁢ 
                   
                     Z 
                     ⁡ 
                     
                       ( 
                       s 
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     The value N of the feedback counter  320  sets the output frequency of the PLL  305 . Its digital structure restricts N to integer numbers. As a result, the frequency resolution (or frequency step size) of the integer-N PLL  305  is nominally set by f REF . Fortunately, it&#39;s possible to dramatically decrease the effective frequency step by manipulating the value of N to yield a non-integer average value. This is the concept of a fractional-N PLL. 
       FIG. 6  depicts a fractional-N PLL  605  that uses a ΔΣ modulator  660  to develop non-integer values of N. The ΔΣ modulator  660  advantageously pushes spurious energy (created by the changing values of the feedback counter  620 ) to higher frequencies to be more effectively attenuated by the integration filter  650 . It can be shown that the effective value of N is simply the average value described by 
               N   =         ∑     x   =   1     P     ⁢           ⁢     N   ⁡     [   x   ]         P       ,         
where N[x] is the sequence of values of the feedback counter  620 . This expands to
 
 N[x]=N   int   +n[x],  
 
where N int  is the integer part and n[x] is the fractional part of N[x]. The ΔΣ modulator  660  generates the sequence n[x], that satisfies
 
     
       
         
           
             
               
                 
                   
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     where k is the input to the ΔΣ modulator  660  with resolution M. In practice, the order of the ΔΣ modulator  660  dictates the range of n[x]. 
     The ΔΣ modulator  660  introduces quantization noise that appears at the PLL  605  output. The pseudo-random sequence n[x] possessing a quantization error approximately equal to ±½ N or 
             Δ   =       1   N     .           
It follows that the quantization noise spectral density for this error, assuming a uniform distribution, is expressed by
 
                 e   rms   2     ⁡     (   f   )       =       1     6   ⁢     N   2     ⁢     f   REF         .           
over the frequency range of dc to f REF /2. This quantization noise is advantageously shaped by an L th  order ΔΣ modulator  660  according to
 
 DS ( z )=(1 −z   −1 ) L .
 
     In the PLL  605 , the feedback counter  620  acts as a digital accumulator and reduces the effects of the ΔΣ modulator  660 . That is, the output phase from the feedback counter  620  depends on its previous output phase. The transfer function for the feedback counter  620  is therefore 
               P   ⁡     (   z   )       =     2   ⁢   π   ⁢         z     -   1         1   -     z     -   1           .             
Combining these terms shows that the output noise of the feedback counter  620  is equal to
 
 n   2 ( f )= e   rms   2 ( f )[ DS ( f )] 2   [P ( f )] 2 ,
 
which yields
 
     
       
         
           
             
               
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     This noise seen at the output of the feedback counter  620  is in turn shaped by the transfer function T 1 (s) of the PLL  605  presented above. 
       FIG. 7  depicts a fractional-N PLL  705  configured for very efficient phase/frequency modulation. The signals applied to the input control of the ΔΣ modulator  760  modulate the frequency of the VCO  710  according to
 
 f   VCO   =f   c   +Δf ( t )=( N   int   n[x ]) f   REF ,
 
where Δf(t) is the frequency modulation equal to
 
                 Δ   ⁢           ⁢     f   ⁡     (   t   )         =         (       n   ⁡     [   x   ]       -     k   M       )     ⁢     f   REF       =     FM   ⁢           ⁢     f   REF           ,         
and FM is the applied modulation signal. In practice, the modulation is shaped by the response of the PLL  705  described by transfer function T 1 (s) described above. The response generally limits the bandwidth of the PLL  705  so as to attenuate the quantization noise of the ΔΣ modulator  760 . Consequently, this phase/frequency modulation approach supports only narrowband signals.
 
     To overcome the narrow bandwidth limitation, a second high-frequency modulation path is added to the PLL  705  and the VCO  710 . The resulting two-point frequency modulation system of  FIG. 7  displays a second and complimentary transfer function given by 
                   T   2     ⁡     (   s   )       =         sNK   FM       sN   +       K   PD     ⁢     K   VCO     ⁢     Z   ⁡     (   s   )             ⁢     v   FM         ,         
where K FM  is the gain of the FM port of the VCO  710  at which the v FM  modulating signal is applied. Ideally, the T 1 (s) and T 2 (s) expressions combine to yield a constant response, which occurs when
 
FMf REF =K FM v FM .
 
     The challenge with two-point modulation, and more-specifically direct VCO modulation, is that it requires near-exact control of both the frequency of the VCO  710  and consequently the product K FM v FM  because frequency errors produce phase deviations that accumulate with time. Fortunately, the feedback of the PLL  705  reduces frequency errors because the output of the VCO  710  is driven by the feedback of the PLL  705  to
 
 f   vco   =Nf   REF +FM f   REF  
 
which is also equal to
 
 f   VCO   =K   VCO   v   ctrl   +K   FM   v   FM ,
 
where v ctrl  is an error signal produced by the P/F D  730  and v FM  is an FM signal applied to the VCO  710 . The error signal v ctrl  compensates for any gain errors of the VCO  710  within the bandwidth of the integration filter  750 . Outside the bandwidth of the PLL  705  the effect of the feedback decreases, which makes setting the gain K FM  of the VCO  710  (“VCO gain K FM ”) to its designed value a critical operation. Additionally, setting the gain K FM  to its designed value ensures that a wider bandwidth can achieve better modulation accuracy. The VCO gain K FM  depends heavily on the circuit structure of the VCO  710 , which is described in more detail below.
 
     A detailed view of the VCO  710  is shown in  FIG. 8   a . The VCO  710  oscillates at a frequency 
                 f   osc     =     1     2   ⁢   π   ⁢         (       L   1     +     L   2       )     ⁢     C   eq               ,         
which is set by the resonance of a VCO tank circuit shown in  FIG. 8   a , where C eq  is the equivalent shunt capacitance (comprised of capacitor C 1  and varactors C 2a −C 2b  plus any parasitic capacitance). The equivalent capacitance C eq  may also include coarse-tuning capacitors (not shown) to subdivide the tuning range. The varactor C 2  (shown as C 2a  and C 2b ) allows the VCO  710 , by way of the control signal v ctrl , to be tuned to different radio frequencies.
 
     A VCO tank circuit shown in  FIG. 8   b  includes an auxiliary port to support linear phase/frequency modulation. The circuit uses the capacitance of accumulation-mode MOSFET devices to achieve linear behavior even though these devices display an abrupt response as illustrated in chart  900  of  FIG. 9 . The accumulation-mode MOSFET devices present a low capacitance C min  at applied gate-to-bulk voltages V GB  below the threshold voltage V T , and the MOSFET devices display a high capacitance C max  at applied voltages above V T . Capacitors C 4a  and C 4b  block the dc level present at the output of the VCO  710 . Resistors Z 1 -Z 3  provide some isolation between the gates of MOSFET devices N 3  and N 4 . 
     The gate-to-bulk voltage V GB  applied to each MOSFET device depends on the output signal A sin ωt of the VCO  710 , the FM signal v FM , and the common-mode voltage v cm . The symmetric structure of the VCO  710  provides that signals V LO+  and V LO−  are differential with
 
 V   LO+   =A  sin ω t  &amp;  V   LO−   =−A  sin ωt,
 
where A is the peak signal of each sinusoidal output and ω is the oscillation frequency. It follows then that
 
 V   C3   =A  sin ω t+v   FM   −v   cm  &amp;  V   C4   =−A  sin ω t+v   FM   −v   cm ,
 
which describe the gate-to-bulk voltages V GB  applied to MOSFET devices N 3  and N 4 . The two MOSFET devices N 3  and N 4  connect back-to-back in the VCO  710 , so their individual capacitances behave oppositely.
 
     The modulation signal v FM  affects the MOSFET devices N 3  and N 4  as follows. The devices nominally present a capacitance equal to 
               C   mid     =         C   FM     ⁡     (       v   FM     =   0     )       =           C   min     ⁢     C   max           C   min     +     C   max         .             
As the FM signal v FM  moves positive, both MOSFET devices N 3  and N 4  reach their maximum capacitance values C max , so that for a period of time of approximately
 
               t   =       1   ω     ⁢       sin     -   1       ⁡     (     -       v   FM     A       )           ,         
the VCO structure in  FIG. 8   b  presents a capacitance equal to C max /2. A similar response occurs as the FM signal moves negative, which results in the VCO structure in  FIG. 8   b  presenting a capacitance equal to C min /2. It is worth noting that the VCO structure in  FIG. 8   b  linearizes the overall response of the accumulation-mode MOSFET devices N 3  and N 4  to yield the behavior shown in capacitance curve  1000  of  FIG. 10 .
 
     The capacitance curve  1000  shifts with the amplitude of signal A of the VCO  710  because this signal dynamically biases each accumulation-mode MOSFET device N 3  and N 4  and sweeps each MOSFET device N 3  and N 4  through a range of capacitance values. As the amplitude of signal A increases, the sensitivity of the back-to-back MOSFET devices N 3  and N 4  (e.g., ΔC/Δv FM ) decreases. 
     In practice, the capacitance curve  1000  for each MOSFET device N 3  and N 4  shifts with temperature as shown in chart  1100  of  FIG. 11 . This affects C min  and C max  as well as the transition region between C min  and C max . It follows that the effective capacitance and the sensitivity of the back-to-back MOSFET devices N 3  and N 4  (e.g., ΔC/Δv FM ) also changes. 
     Even if the sensitivity of the back-to-back MOSFET devices N 3  and N 4  remains constant, the VCO gain K FM  may still change, as explained in the following. The VCO  710  oscillates at the resonant frequency of the VCO tank circuit shown in  FIG. 8   b . This resonant frequency is given by 
                 f   osc     =       1     2   ⁢   π   ⁢         (       L   1     +     L   2       )     ⁢     (       C   T     +     Δ   ⁢           ⁢   C       )             =       f   c     +     Δ   ⁢           ⁢   f           ,         
where C T  is the total tank capacitance less the variable capacitance ΔC. The frequency step Δf due to a change in a MOSFET device capacitance ΔC is approximately equal to
 
               Δ   ⁢           ⁢   f     =       f   C     ⁡     [     1   -       1   2     ⁢       Δ   ⁢           ⁢   C       C   T         +       3   8     ⁢       (       Δ   ⁢           ⁢   C       C   T       )     2         ]             
for small values of ΔC. The frequency step Δf simplifies to
 
                 Δ   ⁢           ⁢   f     =       f   C     ⁡     (       -     1   2       ⁢       Δ   ⁢           ⁢   c       C   T         )         ,         
which can then be rewritten as
 
Δf=2π 2 Lf C   3 ΔC,
 
showing that Δf changes as the third power of f C . Consequently, setting the VCO gain K FM  accurately is a challenging task.
 
       FIG. 12  depicts a phase/frequency modulator  1270  that can accurately set the VCO gain K FM . The system of  FIG. 12  scales the FM signal v FM  by α to compensate for variations in the VCO gain K FM  and thereby stabilizes the K FM v FM  product such that
 
FMf REF =αK FM v FM .
 
     The value of α is calculated using a calibration system  1380  shown in  FIG. 13 . The gain K FM  of the VCO  1310  is represented by the expression 
     
       
         
           
             
               
                 K 
                 FM 
               
               = 
               
                 
                   Δ 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     f 
                     OUT 
                   
                 
                 
                   Δ 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     v 
                     FM 
                   
                 
               
             
             , 
           
         
       
     
     where Δf OUT  is the difference between output frequencies f VCO1  and f VCO2  at two v FM  inputs. Each of the output frequencies f VCO1  and f VCO2  is measured by 
                 f   VCO     =       N   R     ⁢     f   REF         ,         
where N is the number of cycles of the VCO  1310  during a fixed measurement period and R is the number of cycles of the reference signal. During operation of the calibration system  1380 , a zero-phase restart signal initiates the R counter  1381  and N counter  1385  at the same time. Since the VCO  1310  operates independently of and at a higher frequency than the reference signal, the operation of the restart signal introduces an error in the frequency measurement of the output frequencies f VCO1  and f VCO2  equal to
 
                 Δ   ⁢           ⁢     f   VCO       =         Δ   ⁢           ⁢   N     R     ⁢     f   REF         ,         
where ΔN represents an uncertainty associated with the N counter  1385  and the VCO  1310 . The error Δf VCO  is also compounded by the read operation of the N counter  1385  at the end of the measurement period, because at least a portion of the N counter  1385  is integrated with the PLL  1305  and is therefore not designed to stop instantly, nor is it designed to transfer its contents readily. Consequently, the uncertainty ΔN and the measurement error Δf VCO  increases.
 
     The accuracy of the above technique described with respect to  FIG. 13  can be improved by increasing the length of the measurement period, which is accomplished by extending the measurement periods of the R counter  1381  and the N counter  1385  beyond the normal requirements of the PLL  1305 . As a result of such an extension, it is possible to reduce the measurement error Δf VCO  to less than a few tenths of a percent. 
     The calibration approach described above operates off-line (e.g., with a transmitter powered off), and occurs regularly in half duplex systems, but occurs infrequently in full duplex systems. Consequently, another calibration approach is needed to measure K FM  and adjust a accordingly. 
       FIG. 14  depicts a K FM  adjustment system  1490  that is configured to adjust a in order to keep αK FM v FM  constant. The adjustment system  1490  tracks key parameters to predict K FM  changes, and adjusts α accordingly. The adjustment system  1490  includes both a peak detector  1491  that measures the amplitude of the output signal of the VCO  1410 , and a novel swept capacitance circuit (SCC)  1493  that characterizes the capacitance curve of an accumulation-mode MOSFET capacitor. The adjustment system  1490  translates the measurements received from the peak detector  1491  and the SCC  1493  to a digital format using an A/D converter  1495 , and processes the data (via a logic device  1497 ) to determine the appropriate α value using 
                 α   2     =         α   1     ⁡     (       A   2       A   1       )       ⁢       (       f   1       f   2       )     3     ⁢     (     β   +       V     C   ⁢           ⁢   1         V     C   ⁢           ⁢   2           )         ,         
where β is a scaling factor that depends on the measurement from the SCC  1493 .
 
       FIGS. 15   a - b  depict circuitry associated with the peak detector  1491 . The peak detector  1491  is associated with an RF detector circuit shown in  FIG. 15   a  and a reference network shown in  FIG. 15   b  that reduces temperature sensitivity. The output signal of the VCO  1410  (“VCO output signal”) couples to the detector input v IN , and drives transistor N 1 . Transistor N 1  rectifies the input signal according to 
                 i     D   ⁢           ⁢   1       =         μ   ⁢           ⁢     C   ox       2     ⁢     W   L     ⁢       (       v   IN     +     V   B     -     V   T     -     v   det       )     2         ,         
where i D1 , μ, C OX , W, L, and V T  are all well-known parameters associated with the transistor N 1 , V B  is the gate bias voltage, v det  is the output voltage developed across capacitor C 1 , and v IN  has an amplitude κA, where κ is a fixed coupling factor.
 
     The peak detector  1491  is configured to achieve equilibrium, where the average current flowing through transistor N 1  is I B . Achieving equilibrium requires that the voltage held by capacitor C 1  tracks the positive peaks of the coupled VCO output signal which is shown in the graph provided by  FIG. 15   c . As a result, the amplitude of the VCO output signal is held by capacitor C 1 . Transistor N 2  replicates the dc operation of the RF detector and provides a temperature compensated reference V REF . The difference,
 
 V   OUT   =v   det   −V   REF ,
 
corresponds to κA and changes proportional to A.
 
     In several embodiments, the peak detector  1491  can be eliminated if a feedback loop (not shown) exists to control the amplitude of the VCO output signal. Nevertheless, in several embodiments the VCO  1410  is designed to minimize amplitude changes of the VCO output signal. 
       FIG. 16  shows circuitry of the SCC  1493 . As shown, the SCC  1493  forces a constant current I B  through an accumulation-mode MOSFET device N 5 , thus charging the nonlinear capacitance of the MOSFET device N 5 . It follows that the developed voltage V C  relates to the capacitance curve of the MOSFET device N 5  since 
                 V   C     =         ∫   T     ⁢         I   B         C   MOS     ⁡     (     V   C     )         ⁢           ⁢     ⅆ   t         +     V   initial         ,         
where T corresponds to the period of time that the constant bias current I B  charges C MOS , the voltage-dependent capacitance of the MOSFET device, from an initial voltage V initial . As a result, the voltage developed across the MOSFET device sweeps from V initial  to V C  similar to the way the VCO signal develops across the MOSFET device in the VCO circuit shown in  FIG. 8   b . It follows that V C  represents a swept capacitance of the MOSFET device N 5 . As such, with I B  and T fixed, any differences in the MOSFET capacitance curve produce a new V C  voltage.
 
       FIG. 17  depicts logic circuitry of the K FM  adjustment system  1490 . As shown, the logic device  1797  strobes the A/D converter  1795  and samples the analog results from both the peak detector  1791  and the SCC  1793 . The logic device  1797  includes a computing device  1798  that applies mathematical functions to determine the adjusted value of α. The logic device  1797  also includes a timing network  1799  to control the timing of the measurements from the peak detector  1791  and the SCC  1793 , which occur based on the expected rate of change for K FM . For example,  FIG. 17   b  illustrates a timing diagram representative of operation of the timing network  1798  in one embodiment of the invention. 
     The innovative system described herein addresses a critical issue associated with two-point phase/frequency modulation systems. It advantageously ensures that the gain of the direct VCO modulation path is set properly and constant. 
     Those skilled in the art can readily recognize that numerous variations and substitutions may be made in the invention, its use and its configuration to achieve substantially the same results as achieved by the embodiments described herein. Accordingly, there is no intention to limit the invention to the disclosed exemplary forms. Many variations, modifications and alternative constructions fall within the scope and spirit of the disclosed invention as expressed in the claims.