Abstract:
A RF device includes a RF integrated circuit having a RF input and a RF output. The RF integrated circuit has an NMOS transistor having a gate terminal coupled to the RF input, a drain terminal coupled to a first power supply node and a source terminal coupled to a second power supply node. The RF integrated circuit is vulnerable to damage from an ESD event. A primary ESD protection circuit is coupled to the RF input and between the first and second power supply nodes. A secondary ESD protection circuit is coupled between the RF input and the second power supply node. The secondary ESD protection circuit includes a secondary ESD protection diode coupled between the gate and source terminals of the NMOS transistor.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to integrated circuit (IC) designs having ESD protection, and more specifically to IC designs having charge device model (CDM) ESD protection. 
       BACKGROUND OF THE INVENTION 
       [0002]    Field induced charge device model (CDM) damage from an electrostatic field occurs when a charged item it brought into close proximity to an electrostatic discharge (ESD) sensitive device and the device is then grounded while in the presence of the field. Effective ESD control programs ensure that process-required insulators will not induce damaging voltage levels onto the devices being handled. 
         [0003]    CDM emulates an integrated circuit that becomes charged during handling and discharges to a grounded metallic surface. The capacitance is the capacitance of the integrated circuit to its surroundings and the discharge path is a pin of the IC directly to a grounded surface. The test method for CDM must have a capacitance that scales with the device under test&#39;s (DUT) capacitance and a discharge path with very little impedance other than the DUT&#39;s own pin impedance. The peak current for CDM ESD is larger than other ESD models, e.g., human body model (HBM). 
         [0004]    Existing conventional ESD protection schemes for internal logic circuits degrade RF circuit performance. This occurs because the ESD-induced parasitic capacitance negatively impacts an input matching network in RF front-end circuits such as a low-noise amplifiers, especially for millimeter wave IC applications. 
         [0005]      FIG. 1  portrays a prior art RFIC design  10  having a conventional ESD protection circuit (primary ESD protection) and secondary ESD protection for CDM. In the illustrated design  10 , the ESD protection circuit includes a dual-diode rectifier circuit  14  with a power clamp  16  serving as primary ESD protection element for a RFIC, for example a low-noise amplifier (LNA)  12  as shown. More specifically, LNA  12  is configured as a source-degenerated CMOS cascode LNA. LNAs typically form the first stage of RF front-end circuits. With the double-diode configuration, one diode element is forward-biased and the other is reverse-biased during an ESD event, which can compensate for the voltage dependence of the diode parasitic capacitance and lessen the impact of the DC voltage swing. The power clamp is placed as closed as possible to the RF input pins to reduce the interconnect resistance and the associated voltage drop. The secondary ESD protection is provided by a gate-grounded NMOS (GGNMOS) device  18  in close proximity to the NMOS (M 1 ) of the LNA  12 . This GGNMOS secondary ESD protection approach has its deficiencies. For example, the large induced parasitic capacitance from the GGNMOS device  18  negatively impacts the RF performance, such as the noise figure. Moreover, the presence of the GGNMOS significantly impacts the impedance match along the signal path of the RF circuit. 
         [0006]    The RF circuit of  FIG. 1  also includes a capacitor  22  coupled between the gate and source of the NMOS transistor M 1 . The capacitor is provided for noise optimization under power-constrained simultaneous noise and input matching (PCINM). This design balances the contribution of the transistor noise and the noise due to the parasitic gate-circuit resistances. The extra gate-source capacitor gives an additional degree of freedom while taking the integrated inductor losses into account. Details of the use of this capacitor are provided in Belostotski, “Noise Figure Optimization of Inductively Degenerated CMOS LNAs with Integrated Gate Inductors”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 53, No. 7 (July 2006), the entirety of which is hereby incorporated by reference herein. 
         [0007]      FIG. 2  shows a prior art multi-stage RF circuit  50 . Specifically, the RF circuit has cascaded amplifier stages  12  and  12 ′. Directly adding conventional CDM ESD protection in the form of the GGNMOS  18 ′ impacts the input matching network and the inter-stage matching network, which significantly affects the RF performance. 
       SUMMARY OF THE INVENTION 
       [0008]    A RF device includes a RF integrated circuit having a RF input and a RF output. The RF integrated circuit has an NMOS transistor having a gate terminal coupled to the RF input, a drain terminal coupled to a first power supply node and a source terminal coupled to a second power supply node. The RF integrated circuit is vulnerable to damage from an ESD event. A primary ESD protection circuit is coupled to the RF input and between the first and second power supply nodes. A secondary ESD protection circuit is coupled between the RF input and the second power supply node. The secondary ESD protection circuit includes a secondary ESD protection diode coupled between the gate and source terminals of the NMOS transistor. 
         [0009]    The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The accompanying drawings illustrate preferred embodiments of the invention, as well as other information pertinent to the disclosure, in which: 
           [0011]      FIG. 1  is a circuit diagram of a prior art front-end RF circuit having primary ESD protection and secondary CDM ESD protection. 
           [0012]      FIG. 2  is a circuit diagram of a prior art front-end multi-stage RF circuit having primary ESD protection and secondary CDM ESD protection. 
           [0013]      FIG. 3  is a circuit diagram of a front-end RF circuit having primary ESD protection and improved secondary CDM ESD protection according to an embodiment of the present invention. 
           [0014]      FIG. 4  is a circuit diagram of an alternative embodiment of the circuit of  FIG. 3 . 
           [0015]      FIG. 5  is a circuit diagram of a multi-stage front-end RF circuit having primary ESD protection and improved secondary CDM ESD protection according to an embodiment of the present invention. 
           [0016]      FIG. 6  is a circuit diagram of an alternative embodiment of the circuit of  FIG. 5 . 
           [0017]      FIG. 7  is a graph depicting noise figures for a RF front-end circuit using conventional CDM ESD protection and CDM ESD protection according to an embodiment of the present invention. 
           [0018]      FIG. 8  is a graph showing results of ESD TLP (transmission line pulse) testing results. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. Relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling, electrical communication and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured, attached or communicate to or with one another either directly or indirectly through intervening structures, unless expressly described otherwise. 
         [0020]    An ESD protection circuit for RF circuits is described below. In embodiments, the ESD protection circuit is designed to provide both noise optimization and secondary ESD protection for CDM. In certain embodiments, the ESD protection circuit provides both part of the primary ESD protection and secondary ESD protection for CDM. 
         [0021]      FIG. 3  is a circuit diagram illustrating an exemplary embodiment of an ESD protection circuit in connection with a RF front end circuit  100 , for example a LNA as described above. The RF circuit  100  includes a LNA  112  and a primary ESD protection circuit having a power clamp circuit  116  and a dual-diode circuit  114 , which may be identical to or similar to circuits  12 ,  14  and  16  described above. In comparison to prior art RF circuit  10 , the circuit  100  does not include GGNMOS transistor  18  or noise reducing capacitor  20 . In one embodiment, these devices are replaced by a single diode  130  coupled between the source and gate terminals of NMOS M 1 . Specifically, the anode of the diode  130  is directly coupled to the source terminal of NMOS M 1  above the source inductor Ls, and the cathode of the diode  130  is directly coupled to the gate terminal of the NMOS M 1  between gate inductor Lg and the gate of NMOS M 1 . The single diode provides both CDM ESD protection and provides for noise optimization performance akin to that of prior art capacitor  20  and as described in Belostotski, which is incorporated by reference as discussed above. When operating in the reverse bias mode in the absence of an ESD event, the diode  130  has an inherent capacitance (Cgs). This capacitance provides the desired noise optimization discussed above during normal RF operation. During a CDM ESD event, the diode  130  is forward biased to provide ESD protection. 
         [0022]    With the prior art circuit  10  of  FIG. 1 , inductor Ls was not in the current path for CDM ESD discharge. However, as can be seen with the embodiment illustrated in  FIG. 3 , there is now a current path from ground (VSS) to the RF input (RFIN) through inductor Ls, the diode  130  and inductor Lg. As such, both inductors Ls and Lg should be designed to survive the ESD event. For example, the inductors can be designed with sufficient metal width to withstand (i.e., not be burned out by) an expected ESD level. In embodiments, the inductors Ls and Lg have metal widths of at least 6 μm, and preferably of at 7 μm, so as to prevent burnout of the inductors by the ESD current flowing through the discharge path. 
         [0023]      FIG. 4  is a circuit diagram illustrating an alternative embodiment of a RF front end circuit  100 A having ESD protection. RF circuit  100 A is identical in all respects to the RF circuit  100  of  FIG. 3  except that the bottom diode D 1  of the dual diode circuit has been removed. This alternative diode circuit is labeled as  114 A. In this embodiment, aspects of the primary ESD protection are provided by the diode  130 . When forward biased, the diode  130  provides both primary ESD protection, in cooperation with diode D 2  of circuit  114 A, and secondary ESD protection. When reverse biased, the diode  130  acts as a capacitor to provide for noise optimization during normal operation of the RF circuit. Moreover, diode D 1  ( FIG. 2 ) has an intrinsic capacitance and its metal routing has an intrinsic resistance, which result in a degraded noise figure and power loss in the RF circuit. Eliminating diode D 1  and its metal routing can reduce this parasitic capacitance effect and power loss. 
         [0024]      FIG. 5  is a circuit diagram of a multi-stage RF amplifier circuit  100 B with built-in primary and secondary ESD protection. The circuit  100 B includes power clamp circuit  116 , first and second dual diode ESD protection circuits  114  and  114 ′, cascaded amplifier circuits  112 ,  112 ′ and first and second secondary ESD protection diodes  130 . The second dual diode ESD protection circuit  114 ′ includes a diode D 2  connected between the input of amplifier  112 ′ and the gate of NMOS M 1  of amplifier  112 ′, and a diode D 1  connected between the input of amplifier  112 ′ and ground. The second secondary ESD protection diode  130  of amplifier  112 ′ is connected in the same manner as the first diode  130  directly to and across the gate and source of NMOS M 1  of amplifier  112 ′. The dual diode circuit  114 ′ provides primary ESD protection for the LNA  112 ′, and the diode  130  provides secondary ESD protection (when forward biased) and noise optimization (when reversed biased) as described above. 
         [0025]      FIG. 6  is a circuit diagram of an alternative embodiment of a multi-stage RF amplifier circuit  100 C with built-in primary and secondary ESD protection. The circuit is identical to the circuit  100 B of  FIG. 5  only diode D 2  has been removed from the dual diode ESD protection circuits  114 A and  114 A′ to reduce the parasitic capacitance effect as described above in connection with  FIG. 4 . 
         [0026]    Though second LNA  112 ′ is shown as having a gate inductor Lg, it should be realized that this second gate inductor is optional. 
         [0027]      FIG. 7  is a graph of simulation results comparing the noise figures for a LNA circuit having conventional GGNMOS secondary ESD protection as described above and for a LNA circuit as shown in  FIG. 3  having ESD secondary protection in the form of a diode  130 . When compared with circuits using conventional GGNMOS secondary ESD protection for CDM, the RF performance, illustrated by the noise figures of  FIG. 7 , can be greatly improved. The approach for secondary ESD protection described herein allows the circuit designer to optimize ESD and RF performance simultaneously by reducing parasitic capacitance. The diode  130  is designed for both RF performance and secondary ESD protection and can be treated as a matching network device during the design phase. Standard simulations can be used to optimize this single device&#39;s parameters for optimal RF performance. As shown in  FIG. 7 , the simulation confirmed the improved performance. At 5.8 GHz, the noise figure was reduced almost 70% from 10.3 dB to 3.24 dB. 
         [0028]      FIG. 8  is a graph of ESD transmission line pulse (TLP) testing results. As those familiar with ESD tests will understand, TLP corresponds to an HBM ESD event and is not a specific test of performance under CDM. Nonetheless, the test is indicative of how a circuit will fair under CDM ESD events and demonstrates that the device can withstand ESD events with a high current (in the order of amperes). The graph depicts the I-V behavior of the disclosed device. The It2 current, i.e., the secondary breakdown current corresponding to the device fail point, is about 1.42 A, illustrating an ability to pass the required 2.0 kV of ESD (1.333 A×1.5 kohm). 
         [0029]    The provision of secondary ESD protection has become very important for large die-size system-on-chip (SOC) applications used in today&#39;s RF application. These devices are particularly susceptible to CDM due to their large die sizes. As described above, the disclosed secondary ESD protection circuit provides for both CDM protection during ESD events and for noise optimization during normal operation while allowing for designs that reduce the effect of parasitic capacitances on RF performance and allow for improved matching of multi-stage designs. The ESD protection design is disclosed herein in connected with protection for RF front-end LNAs, it should be understood that the concepts described herein have broader application than simply LNAs and can be used to provide ESD protection for other RF devices having CDM ESD considerations, such as mixers, voltage controlled oscillators (VCOs), power amplifiers. Normally, ESD and RF performance is a trade-off. The secondary ESD protection diode can be added as an additional ESD clamp block to these RF device. The ESD protection scheme can be utilized in any number of applications, including, by way of example only, 2.4 GHz blue-tooth, Global Positioning Systems (GPS), wireless communications, 24 GHz ISM vehicle radar, 3-10.6 GHz UWB, 60 GHz UWB, and the like. 
         [0030]    Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly to include other variants and embodiments of the invention that may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.