Abstract:
An optical receiver circuit is disclosed. This receiver included in receiver optical sub-assembly (ROSA) adjusts bandwidth based on a voltage level detection at a receiver signal strength indication (RSSI) pin, or rate-adaptively adjusts the bandwidth of optical receiver circuit based on operation data rate.

Description:
FIELD OF THE INVENTION 
   The present invention relates to fiber optic communication; more particularly, the present invention relates to optical receivers. 
   BACKGROUND 
   More frequently, optical input/output (I/O) is being used in computer systems to transmit data between system components. Optical I/O is able to attain higher system bandwidth with lower electromagnetic interference than conventional I/O methods. In order to implement optical I/O, optical transceivers transmit and receive radiant energy to/from a waveguide, such as optical fibers. 
   However, in an optical transceiver circuit, the most encountered problem is the selection of preamplifier bandwidth. If the preamplifier (e.g., trans-impedance amplifier (TIA)) has too much bandwidth, the optical sensitivity and gain on the jitter performance will be degraded. Nevertheless, the optical sensitivity can be improved by reduce the bandwidth of TIA. Therefore, most designers pursue optimizing the bandwidth according to the different data rates. Typically, the TIA is designed to have a bandwidth of 0.7*bit rate. 
   Current ROSA (Receiver optical sub assembly) typically have five output pins (Vcc, GND, out+, out− and RSSI (receiver signal strength indication)). The RSSI pin is designed to generate the current output proportional to the received optical signal. Thus, there is no pin to select the bandwidth in the TIA inside the ROSA. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only. 
       FIG. 1  illustrates one embodiment of a system; 
       FIG. 2  illustrates one embodiment of a receiver circuit; 
       FIG. 3  illustrates another embodiment of a receiver circuit; 
       FIG. 4  illustrates one embodiment of a rate selection circuit; 
       FIG. 5  illustrates one embodiment of waveforms for various data rates; and 
       FIG. 6  illustrates one embodiment of a ROSA circuit. 
   

   DETAILED DESCRIPTION 
   According to one embodiment, a fiber optic communication mechanism is disclosed. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. 
   In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. 
     FIG. 1  is a block diagram of one embodiment of a computer system  100 . Computer system  100  is a notebook computer that includes a notebook base  110  attached to a display panel  120  via a hinge  112 . System  100  also includes a back light inverter  130  coupled to panel  120  for lighting display  120 . 
   According to one embodiment, base  110  and display panel  120  are also coupled via a waveguide  105 . Waveguide  105  transmits radiant energy between base  110  and display panel  120  via receivers  115 . Receivers  115  are implemented to receive data from waveguide  105 . In one embodiment, waveguide  105  includes one or more optical fibers. However, other embodiments may feature other types of waveguides. 
     FIG. 2  illustrates one embodiment of a receiver  115 . Receiver  115  includes a ROSA circuit  210  and a bandwidth adjustment circuit  250 . ROSA circuit  210  includes active components that are implemented to receive an optical input. Particularly, circuit  210  includes a diode  212 , a trans-impedance amplifier (TIA)  214 , a comparator  216 , switches S 1  and S 2 , and feedback resistors Rf 1  and Rf 2  coupled to S 1  and S 2 , respectively. 
   Diode  212  converts a received optical input signal into an electrical signal. In one embodiment, diode  212  is a positive, intrinsic, negative (PIN) diode. However, in other embodiments, diode  212  may be implemented with an Avalanche Photodiode (APD). TIA  214  receives the converted signal from diode  212  and amplifies the signal. 
   According to one embodiment, the bandwidth of TIA  214  may be adjusted to optimize the signal based on the system data rate. Accordingly, comparator  216  within circuit  210 , and bandwidth adjustment circuit  250  are implemented to optimize the TIA  214  bandwidth. In one embodiment, comparator  216  receives a reference voltage (Vref) from bandwidth adjustment circuit  250  and compares the voltage to a voltage corresponding to a voltage received from the RSSI pin. As discussed above, the RSSI pin is designed to generate a current output proportional to the received optical signal. 
   In one embodiment, if the RSSI pin voltage is greater than Vref comparator  216  closes S 1 , and if the RSSI pin voltage is less than Vref, S 2  is closed. Thus, TIA  214  will have one feedback resistance if the RSSI pin voltage is greater, and another resistance if the RSSI pin voltage is less than Vref. 
   Bandwidth adjustment circuit  250  indicates to ROSA circuit  210  which data rate is to be used. For example, bandwidth adjustment circuit  250  indicates whether the data rate is 2 Gb/sec or 4 Gb/sec. Circuit  250  includes NMOS transistors N 1 -N 3 . In one embodiment, each of the transistors has the same characteristics. Transistors N 1  and N 2  are coupled to a switch S 5 , while transistor N 3  is coupled to a switch S 4 . Both switches are coupled to the RSSI pin to receive current. 
   According to one embodiment, switch S 4  is closed if the system is to operate at a 2 Gb/sec. As a result, the voltage buildup at the RSSI pin will be approximately equivalent to the voltage threshold (Vt) plus the source-drain voltage (Vds) if S 4  is closed. Similarly, switch S 5  is closed if the system is to operate at a 4 Gb/sec. Thus, the voltage buildup at the RSSI pin will be approximately equivalent to the voltage threshold 2*(Vt+Vds) if S 5  is closed. 
   In operation, the system user would close (turn on) either switch S 4  or S 5  prior to operation of receiver  115  since the system data rate is known. For instance, if S 1  is turned on it is known that the incoming data rate is 2 Gb/s data. Therefore, the RSSI voltage will be Vt+Vds above ground. If the data stream is 4 Gb/s, S 2  is turned on, while S 1  is off. Thus, the RSSI voltage will be 2*(Vt+Vds). At ROSA circuit  210  comparator  216  controls S 1  and S 2  by telling whether the voltage is higher or lower than Vref. In one embodiment, Vref is equal to 2*Vt. 
   If the RSSI voltage is higher than 2 Vt, the bandwidth can be selected by adjusting the feedback resistor of TIA  214 . The feedback resistor is selected in effect by closing S 1  or S 2 , depending upon which has the optimized resistance. In one embodiment, Rf 1  has a lower resistance. Thus, S 1  is closed by comparator  216  for 4 Gb/s data stream. 
   If the RSSI voltage is lower than 2 Vt, 2 Gb/s data rate operation occurs. Accordingly, resistor Rf 2  is selected by closing S 2 . By using this technique, no additional pin is required at receiver  115  for optimization of TIA bandwidth selection. 
   Although described with respect to 2 Gb/sec and 4 Gb/sec, one of ordinary skill will appreciate that other data rates may be implemented (e.g., 1 Gb/sec and 2 Gb/sec) in other embodiments. Also, in other embodiments, the NMOS transistors may be replaced with PMOS transistors. 
   According to a further embodiment, receiver  115  may implement automatic TIA data rate selection.  FIG. 3  illustrates another embodiment of a receiver  115 . In this embodiment, a rate selection circuit  320  is coupled to a ROSA circuit  340  to select the data rate at ROSA circuit  340 .  FIG. 4  illustrates one embodiment of rate selection circuit  320 . 
   Selection circuit  320  includes three D flip flops (DFF 1 , DFF 2  and DFF 4 ) that receive data. Each DFF has a corresponding output. According to one embodiment, each DFF has an input coupled to the output of a comparator. For example, comparators  1 ,  2  and  4  are coupled to DFFs  1 ,  2  and  4 , respectively. Further, each of the comparators is coupled to a node Va, which is coupled to a capacitor C 1  and a transistor, via resistor R 1 . 
   Assuming the input data has a high pulse (logic 1), the nodal voltage Va will be charged to a fixed voltage Vhigh-V BE . The charge is stored in capacitor C 1 . Subsequently, when the data input is switched to low (logic 0), the voltage on C 1  starts to drop at a fixed rate by Qc1/Ic. Thus, the nodal voltage drops to different voltage levels based upon the data rate. 
     FIG. 5  illustrates one embodiment of waveforms for various data rates. As shown in  FIG. 5 , the shortest wave pulse for a 1 Gb/sec signal is twice as long as that for a 2 Gb/sec signal, and four times that of a 4 Gb/sec signal. Similarly, the wave pulse for a 2 Gb/sec signal is twice as long as that for a 4 Gb/sec signal. Therefore, the voltage drop for shortest wave pulse for a 4 Gb/sec signal is two times slower than for 2 Gb/sec and twice that of 1 Gb/sec. 
   Since the approximate time constants are known, the threshold voltage for each comparator may be set accordingly. For example, if the highest data rate is at 4 Gb/sec, the node voltage after the 0 pulse will drop above Vth — 4G causing the D flip flop coupled to each comparator to have an output of logic 1. Thus the logic values of comparators  4 ,  2  and  1  are (1,1,1). 
   Similarly, if the data rate is at 2 Gb/sec, comparator  4  would be off and comparator  2 , and comparator  1  would be on. Thus, the logic state of the three comparators would be (0,1,1). If the data rate is at 1 Gb/sec, the nodal voltage Va would only be higher than Vth — 1G thus only comparator  1  would be high. Therefore, the logic state is (0,0,1). If the data rate is slower than 1 Gb/sec, all of these three comparators are off and the logic state is (0,0,0). Table 1 table below summarizes the above results. 
   
     
       
             
             
             
             
           
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
               Data rate 
               Comparator 4 
               Comparator 2 
               Comparator 1 
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               4 
               Gb/s 
               1 
               1 
               1 
             
             
               2 
               Gb/s 
               0 
               1 
               1 
             
             
               1 
               Gb/s 
               0 
               0 
               1 
             
             
               &lt;1 
               Gb/s 
               0 
               0 
               0 
             
             
                 
             
           
        
       
     
   
     FIG. 6  illustrates one embodiment of ROSA circuit  340 . Circuit  340  includes diode  212  and TIA  214 . In addition, feedback switches SW 1 G, SW 2 G and SW 4 G are included, each being coupled to respective feedback resistors Rf 1 G, Rf 2 G and Rf 4 G, respectively. 
   By using Table 1, logic is generated to control the selection of the feedback resistor at TIA  214 . For instance, if the logic state is (111), switch SW 4 G is closed. If the logic state from the three comparators is (011), switch SW 2 G is turned on. Thus, the TIA bandwidth is selected for 2 Gb/s operation. Similarly, if all the logic state is (001), switch SW 1 G is closed to optimize the bandwidth of TIA  214  for a 1 Gb/s data stream. The beauty of this design is that it can automatically adjust the bandwidth without external pin selection. 
   Although described above with respect to a notebook computer implementation, receivers  115  may be used in various applications. For instance, system  100  may include printed circuit boards (PCBs). In one embodiment, receivers  115  may be used at one PCB to couple optical I/O from another PCB. The two PCBs may be included within the same computer system, or may be located at different systems and coupled via a network. 
   Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention.