Abstract:
A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This Application claims rights under 35 USC §119(e) from U.S. Application Ser. No. 61/532,204 filed Sep. 8, 2011, the contents of which are incorporated herein by reference. 
     
    
     STATEMENT OF GOVERNMENT INTEREST 
       [0002]    The invention was made with United States Government assistance under contract no. 08-C-0295, CLIN 0002 awarded by the Department of Defense National Reconnaissance Office. The United States Government has certain rights in the invention. 
     
    
     TECHNICAL FIELD 
       [0003]    Embodiments are generally related to Pulse Width Modulators (PWM). Embodiments are particularly related to Digital Pulse Width Modulator (DPWM) for controlling pulse width in electronic devices. Embodiments are additionally related to digital pulse width modulators with continuous real time calibration. 
       BACKGROUND OF THE INVENTION 
       [0004]    Power management, to improve the power efficiency of Micro Processing Unit (MPUs), Field Programmable Gate Array (FPGAs) and Digital Signal Processor (DSPs) and the like, has become a vital element in digital system design. The power management system includes a full operation mode, standby mode, and sleep mode. The clock frequency, core voltage and/or core current are changed in each mode accordingly. As a result, the output current of the Point-Of-Load (POL) DC-DC converters is intermittent and has a high slew rate. A low output voltage, a large output current and a high speed response are required for the POL. In such a condition, control circuits with high accuracy and high-speed are required as the tolerance of the output voltage becomes internally severe for speed and lower voltage of the Micro Processor Units (MPUs), Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs). A general control method is pulse width modulation (PWM) control with Proportional Integral Derivative (PID). Generally, such control circuits are composed with analog circuits and/or simple combination digital circuits. 
         [0005]    Robustness or flexible controls for versatile conditions are demanded which cannot be accomplished with analog control circuits. For the control purpose, DPWM control is a one of appropriate technique. Also current analog comparator methods for pulse width modulation are not programmable and may not be calibrated. 
         [0006]    DPWM have technical limitations mainly associated with delay related with the sampling process and discrete-time computation. There is generally a tradeoff between the sampling and computation frequency, and the controller power use. Thus, it is beneficial to develop specialized analog-to-digital converter (ADC) architectures which can meet the voltage regulation requirements without excessive power consumption. Importantly, applications requiring very high speed of response (of order of 100 ns) tend to be high-power applications such as servers, where the power overhead of a fast, high-resolution ADC&#39;s is negligible. 
         [0007]    DPWM requires high resolution to produce tightly regulated output voltages, and for elimination of undesirable limit-cycle oscillations of output voltage and inductor current, thus may not be able to provide real time calibration. 
         [0008]    A need therefore exists for a high resolution DPWM with continuous real time calibration. 
       BRIEF SUMMARY 
       [0009]    The following summary is provided to facilitate an understanding of some of the innovative features unique to the disclosed embodiment and is not intended to be a full description. A full appreciation of the various aspects of the embodiments disclosed herein can be gained by taking the entire specification, claims, drawings, and abstract as a whole. 
         [0010]    It is, therefore, one aspect of the disclosed embodiments to provide for Pulse Width Modulators (PWM). 
         [0011]    It is another aspect of the disclosed embodiments to provide Digital Pulse Width Modulator (DPWM) for controlling pulse width in electronic devices. 
         [0012]    It is a further aspect of the disclosed embodiments to provide digital pulse width modulators with continuous real time calibration. 
         [0013]    It is another aspect of the disclosed embodiments to provide a low power digitally controlled pulse modulator that utilizes various sized delay lines and allows digital filtering and programmable resolution. 
         [0014]    It is yet, another aspect of the disclosed embodiments to provide a digitally controlled pulse modulator that performs digital pulse width modulation with real time calibration to compensate environmental variations due to radiation, aging, temperature, and voltage changes. 
         [0015]    The aforementioned aspects and other objectives and advantages can now be achieved as described herein. A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit modulates the pulse width for fractional clock cycle delay. The delay line circuit comprises a multiplexer delay line with built in decoders. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The accompanying figures, in which like reference numerals refer to identical or functionally-similar elements throughout the separate views and which are incorporated in and form a part of the specification, further illustrate the disclosed embodiments and, together with the detailed description of the invention, serve to explain the principles of the disclosed embodiments. 
           [0017]      FIG. 1  illustrates a schematic diagram of a DPWM connected to gate drivers, in accordance with the disclosed embodiments; 
           [0018]      FIG. 2  illustrates a top level block diagram of the DPWM without phase delay circuitry depicted in  FIG. 1 , in accordance with the disclosed embodiments; 
           [0019]      FIGS. 3A-3B  illustrate timing diagrams of signals utilized in  FIG. 2 , showing the duty cycle output for given input clock, pulse width modulator frequency, and duty cycle value, in accordance with the disclosed embodiments; 
           [0020]      FIG. 4  illustrates a second top level block diagram of the DPWM with phase delay circuitry depicted in  FIG. 1 , in accordance with the disclosed embodiments; 
           [0021]      FIG. 5  illustrates timing diagram of signals utilized in  FIG. 4  showing the duty cycle output for given input clock, pulse width modulator frequency, and duty cycle value, in accordance with the disclosed embodiments; 
           [0022]      FIG. 6  illustrates a block diagram of a programmable high resolution delay line circuit depicted in  FIG. 2  and  FIG. 4 , in accordance with the disclosed embodiments; 
           [0023]      FIG. 7  illustrates a schematic diagram of delay lines with MSB and LSB decoders, in accordance with the disclosed embodiments; 
           [0024]      FIG. 8  illustrates a block diagram of a real time calibration unit, accordance with the disclosed embodiment; and 
           [0025]      FIG. 9  illustrates delay chain calibration algorithm, in accordance with the disclosed embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0026]    The particular values and configurations discussed in these non-limiting examples can be varied and are cited merely to illustrate at least one embodiment and are not intended to limit the scope thereof. 
         [0027]    Referring to  FIG. 1 , a schematic diagram of a DPWM system  100  connected to gate drivers  240  is disclosed. The input voltage  104  in the range of 2.97 Volts to 3.6 Volts is applied to a power MOSFET  160 . The input voltage  104  is monitored by utilizing a telemetry unit  108 . The power MOSFET  160  is driven by the gate drivers  240  which are controlled by a DPWM  116 . The DPWM  116  receives control signals  132  and  134  from Over Voltage Protection (OVP) circuit  110  and Over Current Protection (OCP) circuit  112 . 
         [0028]    A voltage scaler  118  receives the output voltage  152  and generates a voltage  146  depending on the signal  148  from a calibration unit  124 . The voltage  146  is converted to a digital signal  142  by utilizing an Analog to Digital Converter (ADC)  122 . The digital signal  142  from ADC  122  and reference signal  144  from reference circuit  128  are compared in a comparator  141 . The error signal  140  is given to Proportional Integral Derivative (PID) controller  120  to generate a control signal  136  for the DPWM  116 . The DPWM  116  generates a duty cycle pulse  130  based on the control signal  136  which drives the gate drivers  240 . The DPWM  116  provides dead time control between the high-side and low-side of the device for the internal gate driver  240  with power MOSFET  160 . The dead time control can also be provided to an external gate driver and FETs. The digital control unit  114  provides necessary control and status signal  138  to various devices in Point of Common Coupling (PCC)  180 . The house keeping supply  126  provide necessary voltage to reference circuit  128 . Point-Of-Load (POL)  182  is shown. 
         [0029]    Referring to  FIG. 2 , a top level block diagram of the DPWM  116  is shown. Fifty percent duty cycle clock  220  is generated by fifty percent duty cycle clock generation block  208  by utilizing PWM rate  202  and clock  204 , such that the duty cycle clock  220  be multiple for twice clock period. A delay is calculated based on duty cycle  206  by utilizing a delay calculator  210 . The delay calculation is based on the desired duty cycle and decision on how much to delay the fifty percent clock  220 . Delay block  205  consists of a cycle delay unit  212  which provides delay by amount of clock periods and fractional delay unit  216  which provides delay by amount of fractions of clock period. The fifty percent duty cycle clock  220  is fed to delay block  205  and fed directly without delay to “OR” gate  240  as well to “AND” gate  230 . Delay information  214  from delay calculator  210  is fed to cycle delay unit  212 . Fractional delay calculation  215  from delay calculator  210  is fed to fractional delay unit  216 . The output  219  of delay block  205  is fed to “AND” gate  230  as well to “OR” gate  240 . The output  259  of “AND” gate  230  and output  241  of “OR” gate  240  is fed to multiplexer unit  250 . Based on the information  249  from delay calculator  210 , if desired duty cycle is greater than fifty percent signal, then output path  241  is selected, otherwise output path  259  is selected by the multiplexer unit  250 . The output of multiplexer unit  250  is desired duty out  260  with course delay or fine delay depending on output path selected. 
         [0030]    Referring to  FIGS. 3A-3B , timing diagrams  280  and  285  for duty cycle greater than fifty percent and less than fifty percent are shown. For duty cycle greater than fifty percent, the graphs  272 ,  274  and  276  represents the timing diagrams of the outputs  220 ,  219  and  260  depicted in  FIG. 2 . For duty cycle less than fifty percent, the graphs  272 ,  274  and  282  represents the timing diagrams of the signals  220 ,  219  and  260  depicted in  FIG. 2 . 
         [0031]    Referring to  FIG. 4 , a second top level block diagram of the DPWM  116  is shown. The block diagram is with cycle delay unit  330  in addition to the delay elements referred in  FIG. 2 . For generation of Fifty percent duty cycle clock  320 , in addition to the PWM rate  202  and clock  204 , PWM synchronization signal  302  which specifies beginning of PWM cycle is also provided and generated fifty percent duty cycle clock  320  is fed to cycle delay unit  330 . Using PWM rate  202  and reference phase delay  304 , amount by which phase of PWM output to be delayed is calculated by phase delay calculator  308 . The cycle delay unit  330  is used to provide phase delay of cycle portion to the fifty percent duty cycle clock  320  by utilizing phase delay calculation  321  obtained from phase delay calculator  308 . The information  341  from phase delay calculator  308  is also utilized for providing percentage of cycle portion phase delay  306  to the selected output  350  of multiplexer  250 . 
         [0032]    Referring to  FIG. 5 , the timing diagram  380  for duty cycle less than fifty percent is shown. For duty cycle less than fifty percent, the graphs  382 ,  384 , 386 ,  388 ,  390  and  392  represents the timing diagrams of the signals  302 ,  320 ,  220 ,  219 ,  350  and  260  depicted in  FIG. 4 . 
         [0033]    Referring to  FIGS. 6-7 , the programmable high resolution delay line circuit of  FIGS. 2 and 4  is shown. The programmable high resolution delay line circuit is also referred as the delay block  205  in  FIGS. 2 and 4 . Fifty percent duty cycle clock output  220  is given as input  602  to a delay block  205  depicted in  FIG. 2  which provides delay out  622 . Fifty percent duty cycle clock output  320  after phase delay is given as input  602  to a delay block  205  depicted in  FIG. 4  which provides delay out  622 . The delay block  205  allows for the modulation of the pulse width for fractional clock cycle delay For larger delay, the upper delay section  610  is selected by utilizing upper delay select block  604 . For medium delay, the lower delay section  612  is selected by utilizing lower delay select block  606 . For very fine resolution delay, the fine delay section  614  is selected by utilizing fine delay select block  608 . The upper delay section  610  comprises of multiplexers  618 , each of them typically provides delay in order of one nano seconds. The lower delay section  612  comprises of multiplexers  620 , each of them typically provides delay in order of 100 pica seconds. The fine delay section  614  comprises of transistor switches  624 , each of them typically provides fine amount of delay.  FIG. 7  shows a schematic block diagram of a set of multiplexer delay lines  750  with built in Most Significant Bit) MSB and (Least Significant Bit) LSB decoders  752  and  754 . 
         [0034]    Referring to  FIG. 8 , a real time calibration unit  124  depicted in  FIG. 1  is shown. A reset counter  702  is utilized to count the system clock  204  to generate a reference time  704 . The reference time  704  is fed to a state machine calculator  714 . The ring oscillator  710  generates a clock signal based on the reference time  704  and compares the generated clock with the system clock  204 . The compared clock is counted by utilizing a counter  708  which is fed to the state machine calculator  714 . The state machine calculator  714  determines delay characterization data  712  by running a ring oscillator  710  with different delays. The delay characterization data  712  is used as unit delays in DPWM. This delay chain calibration used to ensure that proper fractional delay is applied to yield correct duty cycle of the output of the Digital Pulse Width Modulator. 
         [0035]    Referring to  FIG. 9  a delay chain calibration algorithm  800  is shown. The algorithm selects appropriate delay code for necessary delay. Also the algorithm ensures that at real time, the device corrects for any given voltage, temperature, radiation, and aging conditions. Delay line is used as oscillator and calibration is performed in background/parallel with normal POC PCC operation. 
         [0036]    The algorithm is used in conjunction with the existing circuitry and the fractional high precision delay line to calibrate the delay line across the environmental conditions so that proper delay is applied to the pulse output. Without this real-time calibration, the fractional delay would vary with temperature, voltage, radiation, and aging conditions. 
         [0037]    While the present invention has been described in connection with the preferred embodiments of the various figures, it is to be understood that other similar embodiments may be used or modifications and additions may be made to the described embodiment for performing the same function of the present invention without deviating therefrom. Therefore, the present invention should not be limited to any single embodiment, but rather construed in breadth and scope in accordance with the recitation of the appended claims.