Abstract:
A method of forming a semiconductor device. A first and a second semiconductor structures are formed. A semiconductor layer is provided. A first masking layer over a first region of the semiconductor layer is provided. The first masking layer comprises a material that provides a permeable barrier to dopant. The semiconductor layer, including the first region covered by the first masking layer, is exposed to a first dopant. The first region covered by the first masking layer is lightly doped with the first dopant in comparison to a second region not covered by the first masking layer.

Description:
RELATED APPLICATION  
       [0001]     This application is a continuation-in-part of U.S. patent application Ser. No. 10/833,487, filed Apr. 27, 2004, Self-Aligned LDD Thin-Film Transistor and Method of Fabricating the Same, which is incorporated by reference herein, as if fully set forth herein. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The invention relates to a thin film transistor (TFT) device, and more particularly to a lightly doped drain (LDD) structure for a TFT device. Two LDD structures are provided for two TFT devices working at different driving voltages, and a LDD structure with two lateral lengths is provided for a TFT device.  
         [0004]     2. Description of the Related Art  
         [0005]     Active matrix liquid crystal displays (LCDs) typically employs thin film transistors (TFTs) as pixel switching elements. TFTs are classified as amorphous silicon (a-Si) TFTs and polysilicon TFTs according to the materials used for an active layer. Compared with a-Si TFTs, polysilicon TFTs have the advantages of high carrier mobility, high driving-circuit integration and low leakage current, and are often applied to high-speed operation applications, such as static random access memory (SPAM). One of the major drawbacks of these TFTs is OFF-state leakage current, which causes charge loss in LCDs and high standby power dissipation in SRAMs. Seeking to address this issue, conventional lightly doped drain (LDD) structures have been used to reduce the drain junction field, thereby reducing the leakage current. In current semiconductor integrated circuit methods, lithography is employed to define the location and size of the LDD structure. Process tolerance of photo misalignment and critical length deviation, however, become more restricted as TFT size is continuously reduced.  
         [0006]     In conventional LDD processing, a photoresist layer is used as a mask for a heavily-doped ion implantation to form a heavily-doped region in a polysilicon layer. A gate electrode is then formed on the polysilicon layer and used as a mask for a lightly-doped ion implantation to form a lightly-doped region on the exposed area of the polysilicon layer. Thus, the heavily-doped region serves as a source/drain region, the lightly-doped region serves as an LDD structure, and the undoped area of the polysilicon layer serves as a channel region. The pattern of the gate electrode, however, must be accurately controlled to ensure proper placement. The exposure technique is additionally limited by potential photo misalignment, which results in shifting of the gate electrode and the LDD structure. Moreover, because the ion implantation process is performed twice, the LDD structure is subjected to further shifting. Additionally, the procedure of the conventional method is complex, has a low production yield rate, lacks accurate control over the lateral length of the LDD structure, and cannot fabricate two LDD structures with different lateral lengths for different driving-voltage devices simultaneously. Thus, scale reducibility and device operating speed are not reliable.  
       SUMMARY OF THE INVENTION  
       [0007]     Accordingly, the present invention provides two self-aligned LDD structures for two TFT devices working at different driving voltages.  
         [0008]     The present invention provides a self-aligned LDD structure with two lateral lengths for a TFT device.  
         [0009]     According to embodiments of the present invention, a method of forming a semiconductor device comprises forming a first and a second semiconductor structures. Each semiconductor structure comprises providing a semiconductor layer, providing a first masking layer over a first region of the semiconductor layer, said first masking layer comprising a material that provides a permeable barrier to dopant, and exposing the semiconductor layer, including the first region covered by the first masking layer, to a first dopant, wherein the first region covered by the first masking layer is lightly doped with the first dopant in comparison to a second region not covered by the first masking layer, wherein the first region of the first semiconductor structure is of a different lateral length that the first region of the second semiconductor structure.  
         [0010]     According to embodiments of the present invention, a method of forming a semiconductor device comprises providing a semiconductor layer, providing a first masking layer over a first region of the semiconductor layer, said first masking layer comprising a material that provides a permeable barrier to dopant, exposing the semiconductor layer, including the first region covered by the first masking layer, to a first dopant, wherein the first region covered by the first masking layer is lightly doped with the first dopant in comparison to a second region not covered by the first masking layer, and providing a second masking layer over the second region of the semiconductor layer, said second masking layer comprising a material that provides a permeable barrier to dopant, wherein the second masking layer is thinner than the first masking layer.  
         [0011]     According to embodiments of the present invention, a method of forming a semiconductor device comprises providing a semiconductor layer, providing a first masking layer over a first region of the semiconductor layer, said first masking layer comprising a material that provides a permeable barrier to dopant, and exposing the semiconductor layer, including the first region covered by the first masking layer, to a first dopant, wherein the first region covered by the first masking layer is lightly doped with the first dopant in comparison to a second region not covered by the first masking layer, wherein the first region comprises first and second sections, wherein the first section is of a different lateral length that the second section. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0012]     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.  
         [0013]      FIG. 1  is a cross-section of two self-aligned LDD structures according to the first embodiment of the present invention.  
         [0014]      FIGS. 2A  to  2 G are cross-sections of a fabrication method for the self-aligned LDD structures shown in  FIG. 1 .  
         [0015]      FIG. 3  is a cross-section of two self-aligned LDD structures according to the second embodiment of the present invention.  
         [0016]      FIG. 4  is a cross-section of self-aligned LDD structures according to the third embodiment of the present invention.  
         [0017]      FIG. 5  is a cross-section of a self-aligned LDD structure according to the fourth embodiment of the present invention.  
         [0018]      FIGS. 6A-6C  are schematic diagrams of a fabrication method for the self-aligned LDD structure shown in  FIG. 5 .  
         [0019]      FIG. 7  is a cross-section of a self-aligned LDD structure according to the fifth embodiment of the present invention.  
         [0020]      FIG. 8  is a cross-section of a self-aligned LDD structure according to the sixth embodiment of the present invention.  
         [0021]      FIG. 9  is a cross-section of a self-aligned LDD structure according to the seventh embodiment of the present invention.  
         [0022]      FIGS. 10A-10C  are schematic diagrams of a fabrication method for the self-aligned LDD structure shown in  FIG. 9 .  
         [0023]      FIG. 11  is a cross-section of a self-aligned LDD structure according to the eighth embodiment of the present invention.  
         [0024]      FIG. 12  is a cross-section of a self-aligned LDD structure according to the ninth embodiment of the present invention.  
         [0025]      FIGS. 13A  to  13 E are cross-sections of a photolithography process with an attenuated phase shifting mask for a self-aligned LDD structure according to the tenth embodiment of the present invention.  
         [0026]      FIG. 14  is a schematic diagram of a display device comprising the self-aligned LDD structures in accordance with embodiments of the present invention.  
         [0027]      FIG. 15  is a schematic diagram of an electronic device comprising the display device in accordance with embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
     FIRST EMBODIMENT  
       [0028]     The present invention provides two LDD structures for two TFT devices working at different driving voltages. Particularly, a gate insulating layer formed underneath a gate electrode layer has two shielding regions exposed laterally adjacent to the gate electrode layer. The shielding regions are used as a mask for performing an ion implantation process, thus obtaining a self-aligned LDD structure and a source/drain diffusion region simultaneously. The TFT devices are used in N-MOS TFT applications or P-MOS TFT applications. The TFT devices are used in a pixel array area, a peripheral driving-circuit area or a combination thereof.  
         [0029]      FIG. 1  is a cross-section of two self-aligned LDD structures according to the first embodiment of the present invention. A substrate  10  comprises a first TFT area I and a second TFT area II, and a buffer layer  12  is deposited on the substrate  10 . In the first TFT area I, a first active layer  14 , a first gate insulating layer  20  and a first gate electrode layer  25  are formed on the buffer layer  12  successively. In the second TFT area II, a second active layer  16 , a second gate insulating layer  22  and a second gate electrode layer  27  are formed on the buffer layer  12  successively.  
         [0030]     The substrate  10  is a transparent insulating substrate, such as a glass substrate. Either the first TFT area I or the second TFT area II is a peripheral driving-circuit area or a pixel array area. The buffer layer  12  is a dielectric layer, such as a silicon oxide layer, for improving the formation of the active layers  14  and  16  overlying the substrate  10 . Each first active layer  14  and second active layer  16  is a semiconductor silicon layer, such as a polysilicon layer. Each first gate insulating layer  20  and second gate insulating layer  22  may be a silicon oxide layer, a silicon nitride layer, a SiON layer or a combination thereof. Each first gate electrode layer  25  and second gate electrode layer  27  may be a metallic layer or a polysilicon layer.  
         [0031]     The structural characteristics of the first TFT area I are described in the following. The first active layer  14  comprises an undoped region  14   a , two lightly-doped regions  14   b   1  and  14   b   2 , and two heavily-doped regions  14   c   1  and  14   c   2 . The undoped region  14   a  serves as a channel region. The first lightly-doped region  14   b   1  and the second lightly-doped region  14   b   2  extend laterally away from the undoped region  14   a , respectively, to serve as an LDD structure. The first heavily-doped region  14   c   1  and the second heavily-doped region  14   c   2  extend laterally away from the two lightly-doped regions  14   b   1  and  14   b   2 , respectively, to serve as a source/drain diffusion region. The LDD structure has a doping concentration less than 2×10 18  atom/cm 3 , and the source/drain diffusion region has a doping concentration of 2×10 19 ˜2×10 21  atom/cm 3 .  
         [0032]     The first gate insulating layer  20  comprises a central region  20   a  and two shielding regions  20   b , and  20   b   2 . The central region  20   a  covers the undoped region  14   a  and is covered by the bottom of the first gate electrode layer  25 . The two shielding regions  20   b   1  and  20   b   2  extend laterally away from the central region  20   a , respectively, without being covered by the first gate electrode layer  25 . The first shielding region  20   b   1  also covers the first lightly-doped region  14   b   1 , and the second shielding region  20   b   2  covers the second lightly-doped region  14   b   2 . Thus, using the shielding regions  20   b   1  and  20   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0033]     The first shielding region  20   b   1  has a lateral length W 1  corresponding to a lateral length of the first lightly-doped region  14   b   1 , and the second shielding region  20   b   2  has a lateral length W 2  corresponding to a lateral length of the second lightly-doped region  14   b   2 . Preferably, W 1 =0.1 μm˜2.0 μm, and W 2 =0.1 μm˜2.0 μm. Depending on requirements for circuit designs, the size and symmetry of the lateral lengths W 1  and W 2  may be adequately modified, for example W l =W 2 .  
         [0034]     The structural characteristics of the second TFT area II are described in the following. The second active layer  16  comprises an undoped region  16   a , two lightly-doped regions  16   b   1  and  16   b   2 , and two heavily-doped regions  16   c   1  and  16   c   2 . The undoped region  16   a  serves as a channel region. The first lightly-doped region  16   b   1  and the second lightly-doped region  16   b   2  extend laterally away from the undoped region  16   a , respectively, to serve as an LDD structure. The first heavily-doped region  16   c   1  and the second heavily-doped region  16   c   2  extend laterally away from the two lightly-doped regions  16   b   1  and  16   b   2 , respectively, to serve as a source/drain diffusion region. The LDD structure has a doping concentration less than 2×10 18  atom/cm 3 , and the source/drain diffusion region has a doping concentration of 2×10 19 ˜2×10 21  atom/cm 3 .  
         [0035]     The second gate insulating layer  22  comprises a central region  22   a  and two shielding regions  22   b   1  and  22   b   2 . The central region  22   a  covers the undoped region  16   a  and is covered by the bottom of the second gate electrode layer  27 . The first shielding region  22   b   1  and the second shielding region  22   b   2  extend laterally away from the central region  22   a , respectively, without being covered by the second gate electrode layer  27 . Also, the first shielding region  22   b   1  covers the first lightly-doped region  16   b   1 , and the second shielding region  22   b   2  covers the second lightly-doped region  16   b   2 . Thus, using the two shielding regions  22   b   1  and  22   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0036]     The first shielding region  22   b   1  has a lateral length D 1  corresponding to a lateral length of the first lightly-doped region  16   b   1 , and the second shielding region  22   b   2  has a lateral length D 2  corresponding to a lateral length of the second lightly-doped region  16   b   2 . Preferably, D 1 =0.1 μm˜2.0 μm, and D 2 =0.1 μm˜2.0 μm. Depending on requirements for circuit designs, the size and symmetry of the lateral lengths D 1  and D 2  may be adequately modified, for example D 1 =D 2 . In addition, according to requirements for reliability and current designs, the relationship between W 1 , W 2 , D 1  and D 2  may be adequately modified. For example, W 1  (or W 2 ) is not equal to D 1  (or D 2 ). Preferably, when the first TFT area I is a pixel array area and the second TFT area II is a peripheral driving-circuit are a , W 1 , W 2 , D 1  and D 2  satisfy the formula: W 1  (or W 2 )&gt;D 1 (or D 2 ).  
         [0037]     The fabrication method for the self-aligned LDD structure is described in the following.  FIGS. 2A  to  2 G are cross-sections of a fabrication method for the self-aligned LDD structures shown in  FIG. 1 .  
         [0038]     In  FIG. 2A , the substrate  10  comprises a first TFT area I and a second TFT area II, and a buffer layer  12  is deposited on the substrate  10 . Then, a first active layer  14  and a second active layer  16  are formed on the buffer layer  12  of the first TFT area I and the second TFT area II, respectively. The thickness and fabrication method of the active layers  14  and  16  are not limited. For example, low temperature polycrystalline silicon (LTPS) process is employed to form an amorphous silicon layer on a glass substrate, and then heat treatment or excimer laser annealing (ELA) is used to transform the amorphous silicon layer into a polysilicon layer.  
         [0039]     In  FIG. 2B , an insulating layer  18  and a conductive layer  24  are successively deposited on the active layers  14  and  16  and the buffer layer  12 . The insulating layer  18  may be a silicon oxide layer, a silicon nitride layer, a SiON layer or a combination thereof. The conductive layer  24  may be a metallic layer or a polysilicon layer.  
         [0040]     In  FIG. 2C , a first patterned photoresist layer  26  is formed on the conductive layer  24  to cover a predetermined gate pattern of the first TFT area I, and cover the entire second TFT area II. Then, in  FIG. 2D , the first patterned photoresist layer  26  is used as a mask and an etching process is performed to remove the exposed regions of the conductive layer  24  and the insulating layer  18 . Thus, in the first TFT area I, the conductive layer  24  is patterned as a first gate electrode layer  25 , and the insulating layer  18  is patterned as a first gate insulating layer  20 . Next, the first patterned photoresist layer  26  is removed. Preferably, the first gate electrode layer  25  has a trapezoid profile with an upper base shorter than a lower base, thus the first gate insulating layer  20  covered by the bottom of the first gate electrode layer  25  serves as a central region  20   a . The first gate insulating layer  20  exposed laterally adjacent to the first gate electrode layer  25  also becomes two shielding regions  20   b   1  and  20   b   2 . Moreover, the first gate insulating layer  20  exposes a predetermined source/drain diffusion region of the first active layer  14 . Preferably, the first shielding region  20   b   1  , has a lateral length W 1  of 0.1 μm˜2.0 μm, and the second shielding region  20   b   2  has a lateral length W 2  of 0.1 μm˜2.0 μm. Depending on requirements for circuit designs, the size and symmetry of the lateral lengths W 1  and W 2  may be adequately modified, for example W 1 =W 2 .  
         [0041]     An effective etching method employed to obtain the patterned structures in  FIG. 2D  may be plasma etching or reactive ion etching. Preferably, the etching method uses a reactive gas mixture of an oxygen-containing gas and a chlorine-containing gas, and adjusts the individual flow of the oxygen-containing gas or the chlorine-containing gas in a timely manner. For example, during the etching process for the first gate electrode layer  25 , the flow of the chlorine-containing gas is gradually tuned to reach a maximum, even if chlorine-containing gas is the only gas used, resulting in a rectangular profile of the first gate electrode layer  25 . During the etching process for the first gate insulating layer  20 , the flow of the oxygen-containing gas is gradually increased to reach a maximum, thus a part of the first patterned photoresist layer  26  is removed and the first gate electrode layer  25  exposed again by the first photoresist layer  25  is etched simultaneously. This results in a trapezoid profile of the first gate electrode layer  25 , and completes the two shielding regions  20   b , and  20   b   2 .  
         [0042]     In  FIG. 2E , a second patterned photoresist layer  28  is formed to cover the entire first TFT area I, and cover a predetermined gate pattern of the second TFT area II. Then, in  FIG. 2F , the second patterned photoresist layer  28  is used as a mask and an etching process is performed to remove the exposed regions of the conductive layer  24  and the insulating layer  18 . Thus, in the second TFT area II, the conductive layer  24  is patterned as a second gate electrode layer  27 , and the insulating layer  18  is patterned as a second gate insulating layer  22 . Next, the second patterned photoresist layer  28  is removed. Preferably, the second gate electrode layer  27  has a trapezoid profile with an upper base shorter than a lower base, thus the second gate insulating layer  22  covered by the bottom of the second gate electrode layer  27  serves as a central region  22   a . The second gate insulating layer  22  exposed laterally adjacent to the second gate electrode layer  27  also becomes two shielding regions  22   b   1  and  22   b   2 . Moreover, the second gate insulating layer  22  exposes a predetermined source/drain diffusion region of the second active layer  16 . Preferably, the first shielding region  22   b   1  has a lateral length D 1  of 0.1 μm˜2.0 μm, and the second shielding region  22   b   2  has a lateral length D 2  of 0.1 μm˜2.0 μm. Depending on requirements for circuit designs, the size and symmetry of the lateral lengths D 1  and D 2  may be adequately modified, for example D 1 =D 2 . In addition, according to requirements for reliability and current designs, the relationship between W 1 , W 2 , D 1  and D 2  may be adequately modified. For example, W 1  (or W 2 ) is not equal to D 1  (or D 2 ). Preferably, a lateral length of an LDD structure for a pixel array area is greater than a lateral length of an LDD structure for a peripheral driving-circuit area. An effective etching method, such as plasma etching or reactive ion etching, employed to obtain the patterned structures in  FIG. 2F  is substantially similar to that described in  FIG. 2D , with the similar portions omitted herein.  
         [0043]     Finally, in  FIG. 2G , the first gate electrode layer  25 , and the shielding regions  20   b   1  and  20   b   2  are used as a mask, and an ion implantation process  29  is performed to form an undoped region  14   a , two lightly-doped regions  14   b , and  14   b   2 , and two heavily-doped regions  14   c   1  and  14   c   2  in the first active layer  14 . The two lightly-doped regions  14   b   1  and  14   b   2  underlying the two shielding regions  20   b   1  and  20   b   2  serve as an LDD structure. The two heavily-doped regions  14   c   1  and  14   c   2  exposed laterally adjacent to the first gate electrode layer  25  serve as a source/drain diffusion region. The undoped region  14   a  underlying the central region  20   a  serves as a channel region. Since the two shielding regions  20   b   1  and  20   b   2  are used as an ion-implantation mask for the LDD structure, a lateral length of the first lightly-doped region  14   b   1  corresponds to the lateral length W 1  of the first shielding region  20   b   1  and a lateral length of the second lightly-doped region  14   b   2  corresponds to the lateral length W 2  of the second shielding region  20   b   2 .  
         [0044]     Simultaneously when the ion implantation process  29  is performed, the second gate electrode layer  27  and the shielding regions  22   b   1  and  22   b   2  are used as a mask, two lightly-doped regions  16   b   1  and  16   b   2 , and two heavily-doped regions  16   c   1  and  16   c   2  are formed in the second active layer  16 . The two lightly-doped regions  16   b   1  and  16   b   2  underlying the two shielding regions  22   b , and  22   b   2  serve as an LDD structure. The two heavily-doped regions  16   c   1  and  16   c   2  exposed laterally adjacent to the second gate electrode layer  27  serve as a source/drain diffusion region. The undoped region  16   a  underlying the central region  22   a  serves as a channel region. Since the two shielding regions  22   b   1  and  22   b   2  are used as an ion-implantation mask for the LDD structure, a lateral length of the first lightly-doped region  16   b   1  corresponds to the lateral length D 1  of the first shielding region  22   b   1 , and a lateral length of the second lightly-doped region  16   b   2  corresponds to the lateral length D 2  of the second shielding region  22   b   2 .  
         [0045]     For the first TFT area I, the lateral length W 1  or W 2  of the shielding region  20   b   1  or  20   b   2  is 0.1˜2.0 μm, the doping energy is 10˜100 KeV, and a doping concentration of the lightly-doped region  14   b   1  or  14   b   2  is less than 2×10 18  atom/cm 3 , and a doping concentration of the heavily-doped region  14   c   1  and  14   c   2  is 2×10 19 ˜2×10 21  atom/cm 3 . For the second TFT area II, the lateral length D 1  or D 2  of the shielding region  22   b   1  or  22   b   2  is 0.1˜2.0 μm, the doping energy is 10˜100 KeV, and a doping concentration of the lightly-doped region  16   b   1  or  16   b   2  is less than 2×10 18  atom/cm 3 , and a doping concentration of the heavily-doped region  16   c   1  and  16   c   2  is 2×10 19  ˜2×10 21  atom/cm 3 . The thin film transistor is used in an N-MOS TFT, thus the LDD structure is an N − -doped region, and the source/drain diffusion region is an N + -doped region. Alternatively, the thin film transistor is used in a P-MOS TFT, thus the LDD structure is a P − -doped region, and the source/drain diffusion region is a P + -doped region. Subsequent interconnect process including formation of inter-dielectric layers, contact vias and interconnects overlying the thin film transistor is omitted herein.  
         [0046]     The self-aligned LDD structure and the fabrication method thereof have the following advantages.  
         [0047]     First, by adjusting parameters of the etching process, the lateral lengths W 1 , W 2 , D 1  and D 2  of the shielding regions  20   b   1 ,  20   b   2 ,  22   b   1  and  22   b   2  can be accurately controlled, thus ensuring proper positioning of the LDD structure and electric performance of the thin film transistor.  
         [0048]     Second, since an extra photomask or a spacer structure for defining the LDD structure are omitted, shifting of the LDD structure due to photo misalignment in exposure technique is prevented, further improving accuracy in positioning the LDD structure.  
         [0049]     Third, compared with the conventional method, the present invention eliminates one photomask and one step of the ion implantation process, thus simplifying the procedure, decreasing process costs, increasing product yield and production rate. Additionally, the method is highly applicable to mass production.  
         [0050]     Fourth, the ion implantation process can be performed simultaneously in the first TFT area I and the second TFT area II to modulate electric characteristics, and the lateral lengths W 1 , W 2 , D 1  and D 2  of the shielding regions  20   b   1 ,  20   b   2 ,  22   b   1  and  22   b   2  can modify the lateral lengths of the lightly-doped regions  14   b   1 ,  14   b   2 ,  16   b   1  and  16   b   2 , thus two LDD structures with different lateral lengths can be simultaneously achieved on two TFT areas with different driving voltages. Thus, ensuring reliability and operating speed of two driving-voltage devices simultaneously.  
         [0051]     In addition, the above-described steps for patterning the gate electrode layers  25  and  27  and the gate insulating layers  20  and  22  shown in  FIGS. 2C-2F  may be replaced by one step of photolithography with an attenuated phase shifting mask, in which two protrusion-shaped photoresist layers are used as a mask and an etching method is performed to complete the gate electrode layers  25  and  27  and the gate insulating layers  20  and  22  simultaneously.  
         [0052]      FIG. 2H  is a cross-section of a step of photolithography with an attenuated phase shifting mask for the gate electrode layers  25  and  27  and the gate insulating layers  20  and  22  shown in  FIG. 1 . After completing the steps shown in  FIGS. 2A and 2B , an attenuated phase shifting mask  6  is provided and a lithography process is performed on a photoresist layer  26  to form a first protrusion-shaped photoresist layer  26 I in the first TFT area I and a second protrusion-shaped photoresist layer  26 II in the second TFT area II, simultaneously. For example, the attenuated phase shifting mask  6  comprises a first partial exposure area  2  and a second partial exposure area  4 . The first partial exposure area  2  is disposed overlying the first TFT area I, and comprises an opaque area  2   a  of approximately 0% transparency, two phase-shifting areas  2   b  extending laterally away from the opaque area  2   a  respectively, and two transparent areas  2   c  extending laterally away from the two phase-shifting areas  2   b  respectively. The opaque area  2   a  corresponds to the first gate electrode layer  25 , the two phase-shifting areas  2   b  correspond to two lightly-doped regions  14   b   1  and  14   b   2  respectively, and the two transparent areas  2   c  correspond to two heavily-doped regions  14   c   1  and  14   c   2  respectively. Generally, the transparency of the phase-shifting area  2   b  is different from the transparency of the transparent area  2   c , and the transparency difference can be adequately modified in accordance with requirements for product and process designs. Similarly, the second partial exposure area  4  is disposed overlying the second TFT area II, and comprises an opaque area  4   a  of approximately 0% transparency, two phase-shifting areas  4   b  extending laterally away from the opaque area  4   a  respectively, and two transparent areas  4   c  extending laterally away from the two phase-shifting areas  4   b  respectively. The opaque area  4   a  corresponds to the second gate electrode layer  27 , the two phase-shifting areas  4   b  correspond to two lightly-doped regions  16   b   1  and  16   b   2  respectively, and the two transparent areas  4   c  correspond to two heavily-doped regions  16   c   1  and  16   c   2  respectively. Generally, the transparency of the phase-shifting area  4   b  is different from the transparency of the transparent area  4   c , and the transparency difference can be adequately modified in accordance with requirements for product and process designs. When the attenuated phase shifting mask  6  is utilized to perform the photolithography process on a positive-type photoresist, the areas  2   a ˜ 2   c  and  4   a ˜ 4   c  having different transparencies make corresponding areas on the photoresist respectively receive different light intensity to achieve an incomplete exposure result. Therefore, each developed depth of the corresponding areas on the photoresist layer  26  is different, and the protrusion-shaped photoresist layers  26 I and  26 II are formed in the first TFT area I and the second TFT area II, simultaneously. Preferably, the first protrusion-shaped photoresist layer  26 I has a first region  26 I a  thicker than a second region  26 I b , and the second protrusion-shaped photoresist layer  26 II has a first region  26 II a  thicker than a second region  26 II b . The lateral lengths of the second regions  26 I b  and  26 II b  can be modified depending on the lateral lengths of the LDD structures of the TFT areas I and II.  
         [0053]     Next, the two protrusion-shaped photoresist layers  26 I and  26 II are used as a mask and an etching method is employed to remove the exposed regions of the conductive layer  24  and the insulating layer  18 . Then, the two protrusion-shaped photoresist layers  26 I and  26 II are continuously thinned until the second regions  26 I b  and  26 II b  and the conductive layer  24  underlying the second regions  26 I b  and  26 II b  are completely removed, thus completing the gate electrode layer  25  and  27  and the gate insulating layers  20  and  22  shown in  FIG. 2F . The two protrusion-shaped photoresist layers  26 I and  26 II are then removed.  
       SECOND EMBODIMENT  
       [0054]      FIG. 3  is a cross-section of two self-aligned LDD structures according to the second embodiment of the present invention. Elements in the second embodiment are substantially similar to those in the first embodiment, with the similar portions omitted herein.  
         [0055]     In the first TFT area I, the first gate insulating layer  20  further comprises a first extending region  20   c , and a second extending region  20   c   2 . The first extending region  20   c   1  extends laterally away from the first shielding region  20   b   1  and covers the first heavily-doped region  14   c   1 . The second extending region  20   c   2  extends laterally away from the second shielding region  20   b   2  and covers the second heavily-doped region  14   c   2 . The first extending region  20   c   1  has a thickness T 1  less than a thickness T 2  of the first shielding region  20   b   1 . Preferably, the thickness T 1  is far less than the thickness T 2 . Alternatively, the thickness T 1  is close to a minimum. Similarly, the second extending region  20   c   2  has a thickness T 1  less than a thickness T 2  of the second shielding region  20   b   2 , in which the thickness T 1  is far less than the thickness T 2 , alternatively, the thickness T 1  is close to a minimum. The first extending region  20   c   1  and the second extending region  20   c   2  are employed to protect the underlying polysilicon layer without affecting the concentration of the heavily-doped regions  14   c   1  and  14   c   2 . Thus, using the thicker shielding regions  20   b   1  and  20   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0056]     In the second TFT area II, the second gate insulating layer  22  further comprises a first extending region  22   c   1  and a second extending region  22   c   2 . The first extending region  22   c   1  extends laterally away from the first shielding region  22   b   1  and covers the first heavily-doped region  16   c   1 . The second extending region  22   c   2  extends laterally away from the second shielding region  22   b   2  and covers the second heavily-doped region  16   c   2 . The first extending region  22   c   1  has a thickness T 1  less than a thickness T 2  of the first shielding region  22   b   1 . Preferably, the thickness T 1  is far less than the thickness T 2 . Alternatively, the thickness T 1  is close to a minimum. Similarly, the second extending region  22   c   2  has a thickness T 1  less than a thickness T 2  of the second shielding region  22   b   2 , in which the thickness T 1  is far less than the thickness T 2 , alternatively, the thickness T 1  is close to a minimum. The first extending region  22   c   1  and the second extending region  22   c   2  are employed to protect the underlying polysilicon layer without affecting the concentration of the heavily-doped regions  16   c   1  and  16   c   2 . Thus, using the thicker shielding regions  22   b   1  and  22   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0057]     The fabrication method for the self-aligned LDD structures in the second embodiment is substantially similar to that of the first embodiment, with similar portions omitted herein. By modulating parameters of the photolithography and etching processes for the formation of the gate insulating layers  20  and  22 , the etched thickness of the gate insulating layers  20  and  22  must be adequately modulated until the extending regions  20   c   1 ,  20   c   2 ,  22   c , and  22   c   2  outside the gate electrode layers  25  and  27  are retained and reach a preferred thickness T 1 .  
       THIRD EMBODIMENT  
       [0058]      FIG. 4  is a cross-section of self-aligned LDD structures according to the third embodiment of the present invention. Elements in the third embodiment are substantially similar to that of the second embodiment, with the similar portions omitted below.  
         [0059]     In the first TFT area I, the first gate insulating layer  20  is composed of a first insulating layer  20 I and a second insulating layer  20 II. Preferably, the first insulating layer  20 I is a silicon oxide layer, a silicon nitride layer, a silicon-oxide-nitride layer or a combination thereof. Preferably, the second insulating layer  20 II is a silicon oxide layer, a silicon nitride layer, a silicon-oxide-nitride layer, or a combination thereof. The first gate insulating layer  20  has a central region  20   a , two shielding regions  20   b   1  and  20   b   2 , and two extending regions  20   c   1  and  20   c   2 . In the central region  20   a , a double-layer structure composed of the first insulating layer  20 I and the second insulating layer  20 II covers the channel region  14   a . In each of the shielding regions  20   b , and  20   b   2 , a double-layer structure composed of the first insulating layer  20 I and the second insulating layer  20 II covers the LDD structure and is exposed laterally adjacent to the first gate electrode layer  25 . In each of the extending regions  20   c   1  and  20   c   2 , a single-layer structure composed of the first insulating layer  20 I covers the source/drain diffusion region. Thus, a thickness T 1  of the extending regions  20   c   1  and  20   c   2  (the single-layer structure) is less than a thickness T 2  of the shielding regions  20   b   1  and  20   b   2  (the double-layer structure). Thus, using the thicker shielding regions  20   b   1  and  20   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0060]     In the second TFT area II, the second gate insulating layer  22  is composed of a first insulating layer  22 I and a second insulating layer  22 II. Preferably, the first insulating layer  22 I is a silicon oxide layer, a silicon nitride layer, a silicon-oxide-nitride layer or a combination thereof. Preferably, the second insulating layer  22 II is a silicon oxide layer, a silicon nitride layer, a silicon-oxide-nitride layer, or a combination thereof. The second gate insulating layer  22  has a central region  22   a , two shielding regions  22   b   1  and  22   b   2 , and two extending regions  22   c   1  and  22   c   2 . In the central region  22   a , a double-layer structure composed of the first insulating layer  22 I and the second insulating layer  22 II covers the channel region  16   a . In each of the shielding regions  22   b   1  and  22   b   2 , a double-layer structure composed of the first insulating layer  22 I and the second insulating layer  22 II covers the LDD structure and is exposed laterally adjacent to the second gate electrode layer  27 . In each of the extending regions  22   c   1  and  22   c   2 , a single-layer structure composed of the first insulating layer  22 I covers the source/drain diffusion region. Thus, a thickness T 1  of the extending regions  22   c   1  and  22   c   2  (the single-layer structure) is less than a thickness T 2  of the shielding regions  22   b   1  and  22   b   2  (the double-layer structure). Thus, using the thicker shielding regions  22   b   1  and  22   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0061]     The fabrication method for the self-aligned LDD structures in the third embodiment is substantially similar to that of the first embodiment, with similar portions omitted herein. By modulating parameters of the photolithography and etching processes for the formation of the gate insulating layers  20  and  22 , the etched thickness of the gate insulating layers  20  and  22  must be adequately modulated until the extending regions  20   c   1 ,  20   c   2 ,  22   c   1  and  22   c   2  outside the gate electrode layers  25  and  27  are retained and reach a preferred thickness T 1 .  
       FOURTH EMBODIMENT  
       [0062]     The present invention provides a TFT device with a LDD structure having a single lightly-doped region laterally adjacent to a single sidewall of a gate electrode layer. Particularly, a gate insulating layer formed underneath the gate electrode layer has one shielding region exposed laterally adjacent to the single sidewall of the gate electrode layer. The shielding region is then used as a mask to perform one ion implantation process, thus obtaining a self-aligned LDD structure and a source/drain diffusion region simultaneously. The TFT device may be used in N-MOS TFT applications or P-MOS TFT applications. The TFT device may be used in a pixel array area, a peripheral driving-circuit area or a combination thereof.  
         [0063]      FIG. 5  is a cross-section of a self-aligned LDD structure according to the fourth embodiment of the present invention. A substrate  30  comprises a buffer layer  32 , an active layer  34 , a gate insulating layer  38  and a gate electrode layer  42  successively formed thereon. The substrate  30  is a transparent insulating substrate, such as a glass substrate. The buffer layer  32  is a dielectric layer, such as a silicon oxide layer. The active layer  34  is a semiconductor silicon layer, such as a polysilicon layer. The gate insulating layer  38  may be a silicon oxide layer, a silicon nitride layer, a SiON layer or a combination thereof. The gate electrode layer  42  may be a metallic layer or a polysilicon layer.  
         [0064]     The active layer  34  comprises an undoped region  34   a , a lightly-doped region  34   b  and two heavily-doped regions  34   c , and  34   c   2 . The undoped region  34   a  serves as a channel region. The lightly-doped region  34   b  extends laterally away from the right side of the undoped region  34   a  and serves as an LDD structure. The first heavily-doped region  34   c , extends laterally away from the left side of the undoped region  34   a , and the second heavily-doped regions extends laterally away from the right side of the lightly-doped region  34   b , resulting in a source/drain diffusion region. The lightly-doped region  34   b  has a doping concentration less than 2×10 18  atom/cm 3 , and the heavily-doped region  34   c   1  or  34   c   2  has a doping concentration of 2×10 19 ˜2×10 21  atom/cm 3 .  
         [0065]     The gate insulating layer  38  comprises a central region  38   a  and a shielding region  38   b . The central region  38   a  covers the undoped region  34   a , and is covered by the bottom of the gate electrode layer  42 . The shielding region  38   b  extends laterally away from the right side of the central region  38   a , and covers the lightly-doped region  34   b , thus exposing the heavily-doped regions  34   c   1  and  34   c   2 . Thus, using the shielding regions  38   b  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage. The shielding region  38   b  has a lateral length W corresponding to a lateral length of the lightly-doped region  34   b . Preferably, W=0.1 μm˜2.0 μm.  
         [0066]     The fabrication method for the self-aligned LDD structure is described in  FIGS. 6A-6C .  FIG. 6B  is a plane view of a photoresist layer and an active layer.  FIG. 6A  is a cross-section along line  6 A- 6 A in  FIG. 6B .  FIG. 6C  is a cross-section of the LDD structure.  
         [0067]     In  FIGS. 6A and 6B , a buffer layer  32  is deposited on the substrate  30 , and then an active layer  34  is patterned on the buffer layer  32 . Next, an insulating layer  36 , a conductive layer  40  and a patterned photoresist layer  44  are successively deposited on the active layer  34  and the buffer layer  32 . The insulating layer  36  may be a silicon oxide layer, a silicon nitride layer, a SiON layer or a combination thereof. The conductive layer  40  may be a metallic layer or a polysilicon layer. The patterned photoresist layer  44  corresponds to a predetermined gate pattern.  
         [0068]     In  FIG. 6C , the patterned photoresist layer  44  is used as a mask and an etching method is employed to pattern the conductive layer  40  as a gate electrode layer  42 , and pattern the insulating layer  36  as a gate insulating layer  38 . Then, the patterned photoresist layer  44  is removed. The gate insulating layer  38  comprises a central region  38   a  and a shielding region  38   b . The central region  38   a  is covered by the bottom of the gate electrode layer  42 . The shielding region  38   b  extends laterally away from the right side of the central region  38   a , and covers a predetermined LDD pattern of the active layer  34 , and exposes a predetermined source/drain pattern of the active layer  34 . Preferably, the shielding region  38   b  has a lateral length W of 0.1˜2.0 μm. An effective etching method, such as plasma etching or reactive ion etching, may be employed to obtain the patterned structures as shown. The etching method also uses a reactive gas mixture of an oxygen-containing gas and a chlorine-containing gas, and adjusts the individual flow of the oxygen-containing gas or the chlorine-containing gas in a timely manner.  
         [0069]     Finally, the gate electrode layer  42  and the shielding region  38   b  are used as a mask and an ion implantation process  46  is performed on the active layer  34  to form an undoped region  34   a , a lightly-doped region  34   b  and two heavily-doped regions  34   c   1  and  34   c   2 . The undoped region  34   a  is covered by the central region  38   a  to serve as a channel region. The lightly-doped region  34   b  extends laterally away from the right side of the undoped region  34   a  and is covered by the shielding region  38   b  to serve as an LDD structure. The lateral length of the lightly-doped region  34   b  also corresponds to the lateral length W of the shielding region  38   b . The first heavily-doped region  34   c   1  extends laterally away from the left side of the undoped region  34   a , and the second heavily-doped regions  34   c   2  extends laterally away from the right side of the lightly-doped region  34   b , thus serving as a source/drain diffusion region.  
         [0070]     The lateral length W of the shielding region  38   b  is 0.1˜2.0 μm, the doping energy is 10˜100 KeV, and a doping concentration of the lightly-doped region  34   b  is less than 2×10 18  atom/cm 3 , and a doping concentration of the heavily-doped region  34   c   1  and  34   c   2  is 2×10 19 ˜2×10 21  atom/cm 3 . The thin film transistor is used in an N-MOS TFT, thus the LDD structure is an N − -doped region, and the source/drain diffusion region is an N + -doped region. Alternatively, the thin film transistor is used in a P-MOS TFT, thus the LDD structure is a P − -doped region, and the source/drain diffusion region is a P + -doped region. Subsequent interconnect processes including formation of inter-dielectric layers, contact vias and interconnects overlying the thin film transistor are omitted herein.  
         [0071]     The self-aligned LDD structure and the fabrication method thereof have the following advantages.  
         [0072]     First, by adjusting parameters of the etching process, the lateral length W of the shielding region  38   b  can be accurately controlled, thus ensuring proper positioning of the LDD structure and electric performance of the thin film transistor.  
         [0073]     Second, since an extra photomask or a spacer structure for defining the LDD structure are omitted, shifting of the LDD structure due to photo misalignment in exposure technique is prevented, further improving accuracy in positioning the LDD structure.  
         [0074]     Third, compared with the conventional method, the present invention can reduce one step of the ion implantation process, thus simplifying the procedure, decreasing process costs, increasing product yield and production rate. Additionally, the method is highly applicable to mass production.  
         [0075]     Fourth, the single shielding region  38   b  can be the ion-implantation mask to form the LDD structure with single lightly-doped region. Thus, ensuring reliability and operating speed of two driving-voltage devices simultaneously.  
       FIFTH EMBODIMENT  
       [0076]      FIG. 7  is a cross-section of a self-aligned LDD structure according to the fifth embodiment of the present invention. The self-aligned LDD structure in the fifth embodiment is substantially similar to those of the fourth embodiment, with the similar portions omitted herein.  
         [0077]     The gate insulating layer  38  further comprises an extending region  38   c  which extends laterally away from the right side of the shielding region  38   b  and covers the second heavily-doped region  34   c   2 . The extending region  38   c  has a thickness T 1  less than a thickness T 2  of the shielding region  38   b . Preferably, the thickness T 1  is far less than the thickness T 2 . Alternatively, the thickness T 1  is close to a minimum. Thus, using the thicker shielding region  38 b as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0078]     The fabrication method for the self-aligned LDD structure in the fifth embodiment is substantially similar to that of the fourth embodiment, with similar portions omitted herein. By modulating parameters of the photolithography and etching processes for the formation of the gate insulating layer  38 , the etched thickness of the gate insulating layer  38  must be adequately modulated until the extending region  38   c  outside the gate electrode layer  42  is retained and reaches a preferred thickness T 1 .  
       SIXTH EMBODIMENT  
       [0079]      FIG. 8  is a cross-section of a self-aligned LDD structure according to the sixth embodiment of the present invention. Elements in the sixth embodiment are substantially similar to that of the fifth embodiment, with the similar portions omitted below.  
         [0080]     The gate insulating layer  38  is composed of a first insulating layer  38 I and a second insulating layer  38 II. Preferably, the first insulating layer  38 I is a silicon oxide layer, a silicon nitride layer, a silicon-oxide-nitride layer or a combination thereof. Preferably, the second insulating layer  38 II is a silicon oxide layer, a silicon nitride layer, a silicon-oxide-nitride layer, or a combination thereof. The gate insulating layer  38  has a central region  20   a , a shielding region  38   b  and an extending region  38   c . In the central region  38   a , a double-layer structure composed of the first insulating layer  38 I and the second insulating layer  38 II covers the channel region  34   a . In the shielding region  38   b , a double-layer structure composed of the first insulating layer  38 I and the second insulating layer  38 II covers the LDD structure. In the extending region  38   c , a single-layer structure composed of the first insulating layer  38 I covers the source/drain diffusion region. Thus, a thickness T 1  of the extending region  38   c  (the single-layer structure) is less than a thickness T 2  of the shielding region  38   b  (the double-layer structure). Thus, using the thicker shielding region  38   b  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0081]     The fabrication method for the self-aligned LDD structure in the fifth embodiment is substantially similar to that of the fourth embodiment, with similar portions omitted herein. By modulating parameters of the photolithography and etching processes for the formation of the gate insulating layer  38 , the etched thickness of the gate insulating layer  38  must be adequately modulated until the extending regions  38   c  outside the gate electrode layer  42  is retained and reaches a preferred thickness T 1 .  
       SEVENTH EMBODIMENT  
       [0082]     The present invention provides a TFT device with a LDD structure having two lightly-doped regions with asymmetric lateral lengths. Particularly, a gate insulating layer formed underneath the gate electrode layer has two shielding regions, which are exposed laterally adjacent to the gate electrode layer and have different lateral lengths. The shielding regions are then used as a mask to perform one ion implantation process, thus obtaining a self-aligned LDD structure and a source/drain diffusion region simultaneously. The TFT device may be used in N-MOS TFT applications or P-MOS TFT applications. The TFT device may be used in a pixel array area, a peripheral driving-circuit area or a combination thereof.  
         [0083]      FIG. 9  is a cross-section of a self-aligned LDD structure according to the seventh embodiment of the present invention. A substrate  50  comprises a buffer layer  52 , an active layer  54 , a gate insulating layer  58  and a gate electrode layer  62  successively formed thereon. The substrate  50  is a transparent insulating substrate, such as a glass substrate. The buffer layer  52  is a dielectric layer, such as a silicon oxide layer. The active layer  54  is a semiconductor silicon layer, such as a polysilicon layer. The gate insulating layer  58  may be a silicon oxide layer, a silicon nitride layer, a SiON layer or a combination thereof. The gate electrode layer  62  may be a metallic layer or a polysilicon layer.  
         [0084]     The active layer  54  comprises an undoped region  54   a , two lightly-doped regions  54   b   1  and  54   b   2 , and two heavily-doped regions  54   c   1  and  54   c   2 . The undoped region  54   a  serves as a channel region. The two lightly-doped regions  54   b   1  and  54   b   2  extend laterally away from the undoped region  34   a , respectively, to serve as an LDD structure. The two heavily-doped regions  54   c   1  and  54   c   2  extend laterally away from the two lightly-doped regions  54   b   1  and  54   b   2 , respectively, to serve as a source/drain diffusion region. The lightly-doped region  54   b   1  or  54   b   2  has a doping concentration less than 2×10 18  atom/cm 3 , and the heavily-doped region  54   c   1  or  54   c   2  has a doping concentration of 2×10 19 ˜2×10 21  atom/cm 3 .  
         [0085]     The gate insulating layer  58  comprises a central region  58   a  and two shielding regions  58   b   1  and  58   b   2 . The central region  58   a  covers the undoped region  54   a , and is covered by the bottom of the gate electrode layer  62 . The two shielding regions  58   b   1  and  58   b   2  extend laterally away from the central region  58   a , respectively, and cover the two lightly-doped regions  54   b   1  and  54   b   2 , without covering the two heavily-doped regions  54   c   1  and  54   c   2 . Thus, using the shielding regions  58   b   1  and  58   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage. The first shielding region  58   b   1  has a lateral length W 1  corresponding to a lateral length of the first lightly-doped region  54   b   1 , and the second shielding region  58   b   2  has a lateral length W 2  corresponding to a lateral length of the second lightly-doped region  54   b   2 . Preferably, W 1 =0.1˜2.0 μm, and W 2 =0.1˜2.0 μm. Depending on requirements for circuit designs, the size and asymmetry of the lateral lengths W 1  and W 2  may be adequately modified. For example, W 1 ≠W 2 , alternatively, W 1 &lt;W 2 .  
         [0086]     The fabrication method for the self-aligned LDD structure is described in FIGS.  10 A˜ 10 C.  FIG. 10B  is a plane view of a photoresist layer and an active layer.  FIG. 10A  is a cross-section along line  10 A- 10 A in  FIG. 10B .  FIG. 10C  is a cross-section of the LDD structure.  
         [0087]     In  FIGS. 10A and 10B , a buffer layer  52  is deposited on the substrate  50 , and then an active layer  54  is patterned on the buffer layer  52 . Next, an insulating layer  56 , a conductive layer  60  and a patterned photoresist layer  64  are successively deposited on the active layer  54  and the buffer layer  52 . The insulating layer  56  may be a silicon oxide layer, a silicon nitride layer, a SiON layer or a combination thereof. The conductive layer  60  may be a metallic layer or a polysilicon layer. The patterned photoresist layer  64  corresponds to a predetermined gate pattern.  
         [0088]     In  FIG. 10C , the patterned photoresist layer  64  is used as a mask and an etching method is employed to pattern the conductive layer  60  as a gate electrode layer  62 , and pattern the insulating layer  56  as a gate insulating layer  58 . Then, the patterned photoresist layer  64  is removed. The gate insulating layer  58  comprises a central region  58   a  and two shielding regions  58   b , and  58   b   2 . The central region  58   a  is covered by the bottom of the gate electrode layer  62 . The two shielding regions  58   b , and  58   b   2  extend laterally away from the central region  58   a , respectively, and cover a predetermined LDD pattern of the active layer  54 , and expose a predetermined source/drain pattern of the active layer  54 . Preferably, the first shielding region  58   b   1  has a lateral length W 1  of 0.1˜2.0 μm, and the second shielding region  58   b   2  has a lateral length W 2  of 0.1˜2.0 μm. Preferably, W 1 ≠W 2 . An effective etching method, such as plasma etching or reactive ion etching, may be employed to obtain the patterned structures as shown. Also, the etching method uses a reactive gas mixture of an oxygen-containing gas and a chlorine-containing gas, and adjusts the individual flow of the oxygen-containing gas or the chlorine-containing gas in a timely manner.  
         [0089]     Finally, the gate electrode layer  62  and the shielding regions  58   b   1  and  58   b   2  are used as a mask and an ion implantation process  66  is performed on the active layer  54  to form an undoped region  54   a , two lightly-doped regions  54   b   1  and  54   b   2 , and two heavily-doped regions  54   c   1  and  54   c   2 . The undoped region  54   a  is covered by the central region  58   a  to serve as a channel region. The lightly-doped regions  54   b   1  and  54   b   2  extend laterally away from the undoped region  54   a , respectively, and are covered by the shielding regions  58   b   1  and  58   b   2  to serve as an LDD structure. The lateral length of the first lightly-doped region  54   b   1  also corresponds to the lateral length W 1  of the first shielding region  58   b   1 , and the lateral length of the second lightly-doped region  54   b   2  corresponds to the lateral length W 2  of the second shielding region  58   b   2 . The first heavily-doped region  54   c   1  extends laterally away from the first lightly-doped region  54   b   1 , and the second heavily-doped region  54   c   2  extends laterally away from the second lightly-doped region  54   b   2 , thus serving as a source/drain diffusion region.  
         [0090]     The doping energy is 10˜100 KeV, and a doping concentration of the lightly-doped region  54   b   1  or  54   b   2  is less than 2×10 18  atom/cm 3 , and a doping concentration of the heavily-doped region  54   c   1  or  54   c   2  is 2×10 19 ˜2×10 21  atom/cm 3 . The thin film transistor is used in an N-MOS TFT, thus the LDD structure is an N − -doped region, and the source/drain diffusion region is an N + -doped region. Alternatively, the thin film transistor is used in a P-MOS TFT, thus the LDD structure is a P − -doped region, and the source/drain diffusion region is a P + -doped region. Subsequent interconnect process including formation of inter-dielectric layers, contact vias and interconnects overlying the thin film transistor is omitted herein.  
         [0091]     The self-aligned LDD structure and the fabrication method thereof have the same advantages described in the fourth embodiment. Moreover, the two shielding regions  58   b   1  and  58   b   2  having different lateral lengths can be the ion-implantation mask to form the LDD structure with two lightly-doped regions  54   b   1  and  54   b   2  with different lateral lengths. Thus, the asymmetric structure ensures reliability and operating speed of a specific driving-voltage device.  
       EIGHTH EMBODIMENT  
       [0092]      FIG. 11  is a cross-section of a self-aligned LDD structure according to the eighth embodiment of the present invention. The self-aligned LDD structure in the eighth embodiment is substantially similar to those of the seventh embodiment, with the similar portions omitted herein.  
         [0093]     The gate insulating layer  58  further comprises a first extending region  58   c   1  and a second extending region  58   c   2 . The first extending region  58   c   1  extends laterally away from the first shielding region  58   b   1  and covers the first heavily-doped region  54   c   1 . The second extending region  58   c   2  extends laterally away from the second shielding region  58   b   2  and covers the second heavily-doped region  54   c   2 . The first extending region  58   c   1  has a thickness T 1  less than a thickness T 2  of the first shielding region  58   b   1 . Preferably, the thickness T 1  is far less than the thickness T 2 . Alternatively, the thickness T 1  is close to a minimum. Similarly, the second extending region  58   c   2  has a thickness T 1  less than a thickness T 2  of the second shielding region  58   b   2 , in which the thickness T 1  is far less than the thickness T 2 , alternatively, the thickness T 1  is close to a minimum. Thus, using the thicker shielding regions  58   b   1  and  58   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0094]     The fabrication method for the self-aligned LDD structures in the eighth embodiment is substantially similar to that of the seventh embodiment, with similar portions omitted herein. By modulating parameters of the photolithography and etching processes for the formation of the gate insulating layer  58 , the etched thickness of the gate insulating layer  58  must be adequately modulated until the extending regions  58   c   1 ,  58   c   2  outside the gate electrode layers  62  are retained and reaches a preferred thickness T 1 .  
       NINTH EMBODIMENT  
       [0095]      FIG. 12  is a cross-section of a self-aligned LDD structure according to the ninth embodiment of the present invention. Elements in the ninth embodiment are substantially similar to that of the eighth embodiment, with the similar portions omitted below.  
         [0096]     The gate insulating layer  58  is composed of a first insulating layer  58 I and a second insulating layer  58 II. Preferably, the first insulating layer  58 I is a silicon oxide layer, a silicon nitride layer, a silicon-oxide-nitride layer or a combination thereof. Preferably, the second insulating layer  58 II is a silicon oxide layer, a silicon nitride layer, a silicon-oxide-nitride layer, or a combination thereof. The gate insulating layer  58  has a central region  58   a , two shielding regions  58   b , and  58   b   2 , and two extending regions  58   c   1  and  58   c   2 . In the central region  58   a , a double-layer structure composed of the first insulating layer  58 I and the second insulating layer  58 II covers the channel region  54   a . In each of the shielding regions  58   b   1  and  58   b   2 , a double-layer structure composed of the first insulating layer  58 I and the second insulating layer  58 II covers the LDD structure and is exposed laterally adjacent to the gate electrode layer  25 . In each of the extending regions  58   c   1  and  58   c   2 , a single-layer structure composed of the first insulating layer  58 I covers the source/drain diffusion region. Thus, a thickness T 1  of the extending regions  58   c   1  and  58   c   2  (the single-layer structure) is less than a thickness T 2  of the shielding regions  58   b   1  and  58   b   2  (the double-layer structure). Thus, using the thicker shielding regions  58   b   1  and  58   b   2  as an ion-implantation mask, the LDD structure and the source/drain diffusion region can be achieved simultaneously with only one ion implantation process of adequate doping energy and dosage.  
         [0097]     The fabrication method for the self-aligned LDD structure in the ninth embodiment is substantially similar to that of the seventh embodiment, with similar portions omitted herein. By modulating parameters of the photolithography and etching processes for the formation of the gate insulating layer  58 , the etched thickness of the gate insulating layer  58  must be adequately modulated until the extending regions  58   c   1  and  58   c   2  outside the gate electrode layer  62  are retained and reaches a preferred thickness T 1 .  
       TENTH EMBODIMENT  
       [0098]     The present invention provides an attenuated phase shifting mask cooperating with a photolithography process for the shielding regions and extending regions of a gate insulating layer. Then, the shielding regions are used as a mask to perform one ion implantation process, thus obtaining a self-aligned LDD structure and a source/drain diffusion region simultaneously. Preferably, the fabrication method is used for a TFT device with a LDD structure having two lightly-doped regions with asymmetric lateral lengths. The TFT device may be used in N-MOS TFT applications or P-MOS TFT applications. The TFT device may be used in a pixel array area, a peripheral driving-circuit area or a combination thereof.  
         [0099]      FIGS. 13A  to  13 E are cross-sections of a photolithography process with an attenuated phase shifting mask for a self-aligned LDD structure according to the tenth embodiment of the present invention.  
         [0100]     In  FIG. 13A , a substrate  70  comprises a buffer layer  72 , on which an active layer  74 , an insulating layer  76 , a conductive layer  80  and a photoresist layer  84  are successively formed. The substrate  70  is a transparent insulating substrate or a glass substrate. The buffer layer  72  is a dielectric layer or a silicon oxide layer. The insulating layer  76  may be a silicon oxide layer, a silicon nitride layer, a SiON layer or a combination thereof. The conductive layer  80  may be a metallic layer or a polysilicon layer.  
         [0101]     In  FIG. 13B , an attenuated phase shifting mask  87  is used and exposure and development processes are performed to pattern the photoresist layer  84  as a protrusion-shaped photoresist layer  85 . For example, the attenuated phase shifting mask  87  comprises an opaque area  87   a  of approximately 0% transparency, two phase-shifting areas  87   b   1  and  87   b   2  extending laterally away from the opaque area  87   a  respectively, and two transparent areas  87   c   1  and  87   c   2  extending laterally away from the two phase-shifting areas  87   b   1  and  87   b   2  respectively. The opaque area  87   a  corresponds to a predetermined gate pattern, the two phase-shifting areas  87   b   1  and  87   b   2  correspond to a predetermined LDD structure of the active layer  74 , and the two transparent areas  87   c   1  and  87   c   2  correspond to a predetermined source/drain diffusion region of the active layer  74 . Generally, the transparency of the phase-shifting area  87   b   1  or  87   b   2  is different from the transparency of the transparent area  87   c   1  or  87   c   2 , and the transparency difference can be adequately modified in accordance with requirements for product and process designs. When the attenuated phase shifting mask  87  is utilized to perform the photolithography, process on a positive-type photoresist, the areas  87   a ,  87   b   1 ,  87   b   2    87   c   1  and  87   c   2  having different transparencies make corresponding areas on the photoresist respectively receive different light intensity to achieve an incomplete exposure result. Therefore, each developed depth of the corresponding areas on the photoresist layer  84  is different, resulting in the protrusion-shaped photoresist layer  85 . Preferably, the protrusion-shaped photoresist layer  85  has a first region  85   a  thicker than each of two second regions  85   b   1  and  85   b   2 . In addition, by rearranging the areas  87   a ,  87   b   1 ,  87   b   2    87   c   1  and  87   c   2 , the attenuated phase shifting mask  87  can be utilized to perform the photolithography process on a negative-type photoresist to achieve the protrusion-shaped photoresist layer  85 .  
         [0102]     Next, in  FIG. 13C , the protrusion-shaped photoresist layer  85  is used as a mask and an etching method is employed to remove the exposed regions of the conductive layer  80  and the insulating layer  76 , a part of the insulating layer  76  is retained to cover the active layer  74  and the buffer layer  72 . Then, in  FIG. 13D , the protrusion-shaped photoresist layer  85  is continuously thinned until the two second regions  85   b   1  and  85   b   2  and the conductive layer  80  underlying the second regions  85   b   1  and  85   b   2  are completely removed. Thus, the conductive layer  80  is patterned as a gate electrode layer  82 , and the insulating layer  76  is patterned as a gate insulating layer  78 . The photoresist layer  85  is then removed. An effective etching method, such as plasma etching or reactive ion etching, may be employed to obtain the patterned structures as shown. The etching method also uses a reactive gas mixture of an oxygen-containing gas and a chlorine-containing gas, and adjusts the individual flow of the oxygen-containing gas or the chlorine-containing gas in a timely manner.  
         [0103]     The gate insulating layer  78  comprises a central region  78   a , two shielding regions  78   b   1  and  78   b   2  and two extending regions  78   c   1  and  78   c   2 . The central region  78   a  is covered by the bottom of the gate electrode layer  82 . The two shielding regions  78   b   1  and  78   b   2  extend laterally away from the central region  78   a , respectively, and cover a predetermined LDD structure of the active layer  74 . The two extending regions  78   c   1  and  78   c   2  extend laterally away from the two shielding regions  78   b   1  and  78   b   2 , respectively, and cover a predetermined source/drain diffusion region of the active layer  74 . The first shielding region  78   b   1  has a lateral length W 1 , and the second shielding region  78   b   2  has a lateral length W 2 . Preferably, W 1 =0.1˜2.0 μm, and W 2 =0.1˜2.0 μm. Depending on requirements for circuit designs, the size and asymmetry of the lateral lengths W 1  and W 2  may be adequately modified. For example, W 1 ≠W 2 , alternatively, W 1 &lt;W 2 . The first extending region  78   c   1  has a thickness T, less than a thickness T 2  of the first shielding region  78   b   1 . Preferably, the thickness T 1  is far less than the thickness T 2 . Alternatively, the thickness T 1  is close to a minimum. Similarly, the second extending region  78   c   2  has a thickness T 1  less than a thickness T 2  of the second shielding region  78   b   2 , in which the thickness T 1  is far less than the thickness T 2 , alternatively, the thickness T 1  is close to a minimum.  
         [0104]     Finally, in  FIG. 13E , the gate electrode layer  82  and the shielding regions  78   b   1  and  78   b   2  are used as a mask and an ion implantation process  86  is performed on the active layer  74  to form an undoped region  74   a , two lightly-doped regions  74   b   1  and  74   b   2 , and two heavily-doped regions  74   c   1  and  74   c   2 . The undoped region  74   a  is covered by the central region  78   a  to serve as a channel region. The lightly-doped regions  74   b   1  and  74   b   2  extend laterally away from the undoped region  74   a , respectively, and are covered by the shielding regions  78   b   1  and  78   b   2  to serve as an LDD structure. The lateral length of the first lightly-doped region  74   b   1  also corresponds to the lateral length W 1  of the first shielding region  78   b   1 , and the lateral length of the second lightly-doped region  74   b   2  corresponds to the lateral length W 2  of the second shielding region  78   b   2 . The two heavily-doped regions  74   c   1  and  74   c   2  extend laterally away from the two lightly-doped regions  74   b   1  and  74   b   2  to serve as a source/drain diffusion region.  
         [0105]     The doping energy is 10˜100 KeV, and a doping concentration of the lightly-doped region  74   b   1  or  74   b   2  is less than 2×10 18  atom/cm 3 , and a doping concentration of the heavily-doped region  74   c   1  or  74   c   2  is 2×10 19 ˜2×10 21  atom/cm 3 . The thin film transistor is used in an N-MOS TFT, thus the LDD structure is an N − -doped region, and the source/drain diffusion region is an N + -doped region. Alternatively, the thin film transistor is used in a P-MOS TFT, thus the LDD structure is a P − -doped region, and the source/drain diffusion region is a P + -doped region.  
         [0106]     Subsequent interconnect process including formation of inter-dielectric layers, contact vias and interconnects overlying the thin film transistor is omitted herein. Also, the fabrication method described in the tenth embodiment can be utilized for the TFT devices shown in  FIGS. 9 and 12 .  
         [0107]      FIG. 14  is a schematic diagram of a display device  3  comprising the self-aligned LDD TFT structures in accordance with embodiments of the present invention. The display panel  1  can be couple to a controller  2 , forming a display device  3  as shown in  FIG. 14 . The controller  3  can comprise a source and a gate driving circuits (not shown) to control the display panel  1  to render image in accordance with an input.  
         [0108]      FIG. 15  is a schematic diagram of an electronic device  5 , incorporating a display comprising the self-aligned LDD TFT structures in accordance with one embodiment of the present invention. An input device  4  is coupled to the controller  2  of the display device  3  shown in  FIG. 4  can include a processor or the like to input data to the controller  2  to render an image. The electronic device  5  may be a portable device such as a PDA, notebook computer, tablet computer, cellular phone, or a desktop computer.  
         [0109]     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.