Abstract:
Progressive cancellation of electromagnetic interference (EMI) is achieved by establishing a canceller stage processing order in a receiver feed circuit. Such a processing order may be one that progressively narrows an interference analysis bandwidth around desired target signal and optimizes gain-bandwidth characteristics of a cancellation loop in each canceller stage accordingly. A cancellation signal generated by each canceller stage is adaptively controlled without disturbing the stability of the cancellation loop. By doing so, the residual interference-to-noise ratio at each adaptive canceller stage is optimized independently from the closed cancellation loop control of the other canceller stages resulting in improved interference cancellation in the receiver feed circuit.

Description:
FIELD OF THE INVENTION 
     The present general inventive concept relates to interference cancellation by which unwanted signals are minimized or eliminated in radio receivers. 
     BACKGROUND 
     Electromagnetic interference (EMI) in radio-frequency (RF) signals occurs where an RF receiver operating to receive a target signal is within range of an RF transmitter transmitting signals that overlap in frequency with the target signal. In certain cases, such overlap is intentional, such as when radio jamming equipment is deployed to hinder normal radio operations. Such radio jammers may also be integrated in a single receiving system as part of a security strategy. For example, jamming equipment may be installed with other radio equipment on a single platform, such as an aircraft, to prevent unauthorized parties within radio range of the aircraft from intercepting secure communications. Cancelling or otherwise ameliorating EMI is thus essential in many RF receiving scenarios. Accordingly, there is an ongoing pursuit of EMI cancellation techniques that provide greater interference rejection. 
     SUMMARY 
     The present general inventive concept enhances the degree of EMI cancellation by way of ordered cancellation processing. One such ordering progressively narrows the interference detection bandwidth over multiple processing stages around a desired signal. 
     Certain aspects of the present general inventive concept make available an interference reference circuit to provide an interference reference signal indicative of the EMI. A plurality of canceller stages generate cancellation signals from respective reference signals provided thereto. The canceller stages are configured to evaluate the reference signals over respective analysis bandwidths that encompass a frequency band of the target signal by an amount other than that of other canceller stages. A receiver feed circuit is coupled to the canceller stages to apply the cancellation signals to an incoming RF signal in a prescribed processing order, where the incoming signal is a combination of the target signal and an impinging EMI signal. The application of the cancellation signals in the receiver processing path generates residue signals, each of which is provided from one canceller stage to another in accordance with the processing order. The canceller stages are coupled to the receiver feed circuit such that an initial one of the reference signals evaluated in the processing order is the interference reference signal. A receiver is coupled to the receiver feed circuit to generate a data signal from a final one of the residue signals in the processing order. 
     These and other objects, features and advantages of the present general inventive concept will be apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram of an interference cancellation system by which the present general inventive concept can be embodied. 
         FIG. 2  is a schematic block diagram of a progressively narrowing interference and noise cancelling system by which the present general inventive concept can be embodied. 
         FIG. 3  is a schematic block diagram of an adaptive processor system by which the present general inventive concept can be embodied. 
         FIG. 4  is a schematic block diagram of another progressively narrowing interference and noise cancelling system by which the present general inventive concept can be embodied. 
         FIG. 5  is a flow diagram of an adaptive signal cancellation process by which the present general inventive concept can be embodied. 
     
    
    
     DETAILED DESCRIPTION 
     The present general inventive concept is best described through certain embodiments thereof, which are described in detail herein with reference to the accompanying drawings, wherein like reference numerals refer to like features throughout. It is to be understood that the term invention, when used herein, is intended to connote the inventive concept underlying the embodiments described below and not merely the embodiments themselves. It is to be understood further that the general inventive concept is not limited to the illustrative embodiments described below and the following descriptions should be read in such light. 
     Additionally, the word exemplary, when used herein, is intended to mean “serving as an example, instance or illustration.” Any embodiment of construction, process, design, technique, etc., designated herein as exemplary is not necessarily to be construed as preferred or advantageous over other such embodiments. Particular quality or fitness of the examples indicated herein as exemplary is neither intended nor should be inferred. 
       FIG. 1  is a simplified schematic block diagram of an exemplary interference cancelling system (ICS)  100  by which the present invention may be embodied. ICS  100  may include a reference antenna  110  to intercept a signal, referred to herein as interference signal  103 , from an interference signal source  105 , such as a radio transmitter. Reference antenna  110  may be positioned in close proximity to the interference source transmitting antenna or a sample of interference signal  103  may be acquired by way of a direct tap in the interference source transmitter antenna feed circuit on the same platform as ICS  100  (not illustrated). Reference antenna  110  may be coupled to an interference reference circuit  120  comprising a signal conduit  127 , a plurality of signal tap couplers  125   a - 125   n , representatively referred to herein as signal tap coupler(s)  125 , and, optionally, a terminator  127 . Reference circuit  120  may be configured to provide interference reference signals  153   a - 153   n , representatively referred to herein as reference signal(s)  153 , from interference signal  103  for purposes of cancelling or otherwise attenuating interference in signals of interest. 
     ICS  100  includes a receiver antenna  115  to intercept a signal, referred to herein as a target signal  109 , from a remote transmitter  107 . Receiver antenna  115  may be coupled to a receiver feed circuit  130  to provide target signal  109  to receiver  140 . However, because target signal  109  may be corrupted by interference signal  103 , target signal  109  must be extracted from an incoming signal  101 , i.e., the combination of target signal  109  and interference signal  103 . 
     Receiver feed circuit  130  may include a signal conduit  137  and one or more signal injection couplers  132   a - 132   n , representatively referred to herein as injection coupler(s)  132 , by which cancellation signals  155   a - 155   n , representatively referred to herein as cancellation signal(s)  155 , are introduced into the receiver feed circuit  130 . Additionally, receiver feed circuit  130  may include one or more signal tap couplers  134   a - 134   n , representatively referred to herein as signal tap coupler(s)  134 , coupled to signal conduit  137 , by which residual signals  157   a - 157   n , representatively referred to herein as residual signal(s)  157 , are extracted from receiver feed circuit  130 . Receiver feed circuit  130  may be terminated in a receiver circuit  140  that generates a data signal  142  from target signal  109  as obtained from incoming signal  101 . 
     ICS  100  may include a plurality of canceller stages  150   a - 150   n , representatively referred to herein as canceller stage(s)  150 , coupled to interference reference circuit  120  and receiver feed circuit  130 . Each canceller stage  150  may be configured to analyze signals provided thereto, e.g., reference signal  153  and residue signal  157 , and to generate cancellation signal  155  in accordance with the analysis. The cancellation signal  155  of one canceller stage  150  is applied to incoming signal  101  through a signal injection coupler  132  and the remaining signal, i.e., residue signal  157 , is passed onto subsequent canceller stages  150 . Such sequential processing over receiver feed circuit  130  defines therein a receiver processing path  135 . Through receiver processing path  135 , interference may be cancelled in stages, each canceller stage  150  removing an assigned portion of interference such that, at the terminal end of receiver processing path  135 , interference signal  103  is significantly removed from incoming signal  101  thereby leaving a substantially clear target signal  109  from which receiver  140  can generate data signal  142 . 
     Each canceller stage  150  may include an adaptive processor  158  to perform signal analysis and to generate cancellation signal  155 . Adaptive processor  158  may examine characteristics of reference signal  153  and residue signal  157 , such as by correlation between the two signals within an assigned band of frequencies, referred to as an analysis band. In certain embodiments, the analysis band of each canceller stage  150  encompasses target signal  109  by an analysis bandwidth BW that is other than the analysis bandwidth BW of other canceller stages  150 . When so embodied, each canceller stage  150  generates a cancellation signal  155  that removes a portion of interference that corresponds to the analysis bandwidth BW. Canceller stages  150  are coupled to receiver feed circuit  130  to define the analysis bandwidth BW processing order in the receiver processing path  135 , i.e., BW 1  followed by BW 2 , etc., through which the interference signal is removed. 
     Adaptive processor  158  may dynamically adjust processing variables to account for fluctuations in interference signal  103  and/or incoming signal  101 . That is, as conditions external to ICS  100  change in a manner that affects one or more of interference reference signal  153  and residue signal  157 , adaptive processor  158  detects such change and modifies cancellation signal  155  to maintain maximum cancellation. Such may be achieved by constructing a feedback loop, referred to herein as a cancellation loop  160 , in each canceller stage  150 . That is, cancellation signal  155  may be provided to signal injection coupler  132  resulting in a corresponding portion of interference being cancelled from incoming signal  101 . The effect of such cancellation is carried in residue signal  157 , which is fed back to adaptive processor  158  through signal tap coupler  134 . Processing variables in adaptive processor  158  from which cancellation signal  155  is generated can be dynamically altered based on characteristics of residue signal  157  to achieve optimal interference cancellation by canceller stage  150 . Each canceller stage  150  may operate in accordance with its own processing variables and each canceller stage  150  may operate independently in accordance with its own cancellation loop  160 . However, operational stability in each feedback loop must be maintained, as discussed further below. 
     The ordinarily skilled artisan will recognize various applications in which the present invention can be embodied. As such, the signal sources illustrated and described as interference source  105  and corresponding reference antenna  110 , and target signal source  107  and receiver antenna  115  may be replaced by equipment suitable to the application. The adaptive signal processing in each canceller stage  150  and the order in which canceller stages  150  are provided in receiver processing path  135  may modified accordingly. 
       FIG. 2  is a schematic block diagram of a progressively narrowing bandwidth cancellation (PNBC) system  200  embodiment of the present invention. PNBC system  200  includes an interference reference circuit  220  including a reference antenna  210 , transmission line  222  and terminator  227 . Transmission line  222  may include a plurality of signal tap couplers  225   a - 225   n , representatively referred to herein as signal tap coupler(s)  225 , by which interference reference signals  253   a - 253   n , representatively referred to herein as reference signal(s)  253 , are provided to adaptive canceller stages  250   a - 250   n , representatively referred to herein canceller stage(s)  250 . PNBC system  200  includes further receiver feed circuit  230  including a receiver antenna  215  to intercept an incoming signal, a transmission line  224  and receiver circuit  240  that generates data signal  242 . Receiver feed circuit  230  may include one or more signal injection couplers  232   a - 232   n , representatively referred to herein as signal injection coupler(s)  232 , by which cancellation signals  255   a - 255   n , representatively referred to herein as cancellation signal(s)  255 , are introduced into receiver processing path  235 . Additionally, receiver feed circuit  230  may include one or more signal tap couplers  234   a - 234   n , representatively referred to herein as signal tap coupler(s)  234 , by which residual signals  257   a - 257   n , representatively referred to herein as residual signal(s)  257 , are extracted from transmission line  224 . 
     Canceller stages  250  may be configured to generate cancellation signals  255  in accordance with analysis of respective bands of frequencies BW 1 -BW N , representatively referred to herein as analysis bandwidth(s) BW. Accordingly, each canceller stage  250  may include a set of filters  287   a ,  287   b , representatively referred to herein as filter(s)  287 , to limit the content of reference signal  253  and residue signal  257 , and therewith the generation of cancellation signal  255 , to a predetermined analysis band. The PNBC architecture defines receiver processor path  235  in a progressively narrowing analysis bandwidth processing order BW 1 &gt;BW 2 &gt; . . . &gt;BW N  around the target signal. 
     Each of the canceller stages  250  may include an adaptive processor comprising a synchronous detector  286 , an integrator  284  having a variable gain g and variable bandwidth bw coupled to the outputs of the synchronous detector  286 , and a signal controller  282  coupled to the output of the integrator  284 . The signal tap coupler  234 , synchronous detector  286 , integrator  284 , signal processor  282  and signal injection coupler  232  form a cancellation loop  260  in which the gain g and bandwidth bw comprise the process variables by which cancellation signals  255  are optimized. Constraints on cancellation loop  260  must be met that maintain operational stability in the loop. In certain embodiments of the present invention, the gain-bandwidth product (GBP) of integrator  284  is constrained to a particular value in each canceller stage  250  that establishes such stability. When so embodied, the gain g of integrator  284  can be altered to meet some optimization criterion and as long as a corresponding modification to the bandwidth bw of integrator  284  is made, stability is maintained. 
     Synchronous detector  286  cross-correlates reference signal  253  with residue signal  257  and provides detector output signals that vary in accordance how well reference signal  253  and residue signal  257  are correlated. In certain embodiments, synchronous detector  286  is a quadrature phase detector having in-phase (I) and quadrature (Q) outputs, although only one output signal, i.e., error signal  285 , is illustrated. It is to be understood that the term error is used solely to connote an indication of the extent to which processing variables in cancellation loop  260  are to be modified to meet the optimization criterion; the term is not meant to limit the present invention to the determination of errors, per se. Error signal  285  may be provided to adaptive integrator  284 , which integrates the error signal  285  over a time interval or, equivalently, over a series of numerical sample sets, to increase the signal-to-noise ratio of the correlated signal. 
     As indicated above, gain g and bandwidth bw in integrator  284  are variable within the stability constraints of the GBP thereof. Thus, integration is performed on the incoming error signal  285  within analysis bandwidth BW at gain g and with resolution and dynamic range defined by bandwidth bw. The two variables bw and g are adaptively and dynamically modified as necessary to meet the optimization criterion, such as, for example, a minimum level of residue signal  257 . 
     Integrator  284  generates an integrated error signal  283  and provides such to signal processor  282 . Signal processor  282  is configured through hardware or a combination of hardware and software to generate cancellation signal  255  in accordance with a signal generation function H(t). In one implementation, H(t) inverts the reference signal  253  in accordance with characteristics of integrated error signal  283  to produce cancellation signal  255 . Accordingly, cancellation signal  255  destructively interferes with the interference signal present in receiver feed circuit  230  at each canceller stage  250 . 
     In certain embodiments of the present invention, additional components may be added to accommodate a frequency-tunable receiver  240 . For example, tunable filters  270  and  275  may be introduced into the reference circuit  220  and receiver feed circuit  230 , respectively. Tunable filters  270  and  275  may track a tuner (not illustrated) in receiver  240  to encompass a signal of interest, e.g., the target signal, by a frequency band that excludes neighboring signals. Additionally, each canceller stage  250  may include a set of frequency converters  283   a - 283   b  by which the target signal being sought by the tuned receiver is shifted as necessary into the analysis bandwidth BW of the canceller stage  250 . Thus, the process variables in cancellation loop  260  and the corresponding stability criteria are unaffected by the receiver tuning. 
       FIG. 3  is a schematic block diagram of an adaptive processor system  300  by which the present invention may be embodied. System  300  includes digital integrators  384   a - 384   n , representatively referred to herein as digital integrator(s)  384 . Each digital integrator  384  has associated therewith a corresponding analog-to-digital converter (ADC)  345   a - 345   n , representatively referred to herein ADC(s)  345 , and a corresponding digital-to-analog converter (DAC)  347   a - 347   n , representatively referred to herein as DAC(s)  347 . Each ADC  345  is communicatively coupled to a corresponding synchronous detector  286  and receives a corresponding error signal  385   a - 385   n , representatively referred to herein as error signal(s)  385 , therefrom. Each DAC  347  is communicatively coupled to a corresponding signal processor  282  to provide a corresponding integrated error signal  383   a - 383   n , representatively referred to herein as integrated error signal(s)  383 , thereto. Accordingly, each error signal  385  is converted into a digital signal, is integrated by integrator  384  and the digitally integrated error signal is converted into an analog signal. The ordinarily skilled artisan will recognize other system configurations that may be used in conjunction with the present invention without departing from the spirit and intended scope thereof. 
     Adaptive processor system  300  may include a processor  310 , which may be realized by a suitable microprocessor, microcontroller, or the like. Processor  310  may be communicatively coupled to memory  320  in which, among other things, various control parameters  325  may be stored. Such parameters may include a GBP constant for each canceller  250  and default values for loop gain g and loop bandwidth bw for each canceller stage  250 . Memory  320  may further store various sample values, as needed, for purposes of system control and signal processing. Additionally, memory may have stored therein processor instructions that, when executed by processor  310 , implements such system control and signal processing. 
     Processor  310  may provide control signals  312   a - 312   n , representatively referred to herein as control signal(s)  312 , to respective integrators  384 . Control signals  312  may establish the loop gain g in loop gain controller  342  and loop bandwidth bw in bandwidth controller  344 . Digital signal samples from ADC  345  may be integrated over a number of sample cycles, e.g., by summation, as multiplied by gain g through gain controller  342  and as band-limited by bandwidth controller  344 . 
     As illustrated in  FIG. 3 , residue signals  357   a - 357   n , representatively referred to herein as residue signal(s)  357 , are provided to residue signal sensor  330 . Residue sensor  330  may convert residue signal  357  into a numerical value suitable for analysis and/or processing by processor  310 . Such numerical residue values may be tracked, e.g., stored in memory  320  as successive data sets over several sampling cycles. Processor  310  may determine from such data sets whether a minimum value thereof has been obtained. If such a minimum value has been reached, indicating that maximum cancellation has been achieved, integration continues unchanged, i.e., with current gain g and bandwidth bw values in force. However, if residue signal  357  is not at a minimum value, new values for gain g and bandwidth bw may be calculated by processor  310  and continually altered until residue signal  357  is minimized. 
       FIG. 4  is a schematic block diagram of an embodiment of a PNBC system  400 . Like reference numerals in  FIG. 4  as those in  FIG. 2  refer to like components and repeated descriptions thereof will be omitted. Each canceller stage  450  in PNBC system  400  includes an additional signal tap coupler  490  by which cancellation signal  255  may be sampled. Cancellation signal  255  includes artifacts caused by, among other things, hardware components that carry out the processing in canceller stage  450 . Providing the cancellation signal  255  from one canceller stage  450  as the reference signal to another canceller stage  450 , such as via signal conduits  495   a - 495   n , allows subsequent stages in the receiver processing path to account for the signal artifacts produced by earlier stages in the receiver processing path in the formation of later cancellation signals  255 . 
       FIG. 5  is a flow diagram of an exemplary adaptive control process  500  by which the present invention may be embodied. In operation  505 , an index k is initialized and, in operation  510 , the k-th GBP constant is retrieved from, for example, memory  320 . In operation  515 , stored values of the k-th default loop gain g and default loop bandwidth bw is retrieved from memory  320  and assigned to corresponding control variables g and bw in operation  520 . In operation  525 , the k-th residue signal is obtained, and, in operation  520 , it is determined whether the residue signal is minimized, such as through residue signal sensor  330 . If the residue signal is at minimum, loop gain g and loop bandwidth bw is stored as the k-th gain g and k-th bandwidth bw in memory  320 . In operations  540 , index k is incremented and it is determined in operation  545  whether all canceller stages have been assessed. If not, process  500  is repeated at operation  510 . 
     If, at operation  530 , it is determined that the k-th residue signal is not at a minimum value, then the loop gain g is modified, i.e., increased or decreased, so as to minimize the residue signal. In operation  555 , the loop bandwidth bw is set to GBP k /g so as to maintain stability in the cancellation loop, i.e., by way of the constant GBP for canceller k. Process  500  then repeats at operation  520 , where the values of bw k  and g k  are set into the control loop. 
     The descriptions above are intended to illustrate possible implementations of the present inventive concept and are not restrictive. Many variations, modifications and alternatives will become apparent to the skilled artisan upon review of this disclosure. For example, components equivalent to those shown and described may be substituted therefore, elements and methods individually described may be combined, and elements described as discrete may be distributed across many components. The scope of the invention should therefore be determined not with reference to the description above, but with reference to the appended claims, along with their full range of equivalents.