Abstract:
A method is provided. A first CMOS switch is deactivated while activating a second CMOS switch to cause the portion of the write signal to transition from a first direct current (DC) voltage to a first peak voltage. After a first interval, the second CMOS switch is deactivated while activating a third CMOS switch to cause the portion of the write signal to transition from the first peak voltage to a second DC voltage. After a second interval, the third CMOS switch is deactivated while activating a fourth CMOS switch to cause the portion of the write signal to transition from the second DC voltage to a second peak voltage After a third interval, the fourth CMOS switch is deactivated while activating the first CMOS switch to cause the portion of the write signal to transition from the second peak voltage to the first DC voltage.

Description:
TECHNICAL FIELD 
       [0001]    The invention relates generally to a voltage-mode driver and, more particularly, to a preamplifier having a voltage-mode driver. 
       BACKGROUND 
       [0002]    Within hard disk drives (HDDs), a preamplifier or preamp is generally used to perform read and write operations with a magnetic head. Typically, for write operations, the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for losses within the head. Turning to  FIG. 1 , an example of a conventional preamplifier or preamp  100  can be seen. Preamp  100  is commonly employed in hard disc drive (HDD) applications for providing write signals to a magnetic head (which is typically an inductive load). This preamp  100  is generally comprised of input buffers  102 - 1  and  102 - 2  and digital logic  104  (which includes duration generators  106 - 1  and  106 - 2 , logic circuits  108 - 1  and  108 - 2 , and an H-bridge). While this preamp  100  effectively drives the magnetic head, there are some issues. Namely, this type of preamp  100  can be costly because it is usually produced in a silicon-germanium (SiGe) process. This preamp  100  can consume a large amount of power and can require large supply voltages (i.e., 8V or 10V). Therefore, there is a need for an improved preamplifier. 
         [0003]    Some other examples of conventional systems are: U.S. Pat. No. 6,285,221; U.S. Pat. No. 7,408,313; U.S. Pat. No. 7,656,111; U.S. Pat. No. 7,880,989. 
       SUMMARY 
       [0004]    An embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises an input buffer; digital logic that is coupled to the input buffer, wherein the digital logic has at least one duration generator and at least one level shifter; a matching circuit that is configured to drive an inductive load; a first half H-bridge having: a first CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit, and that is configured to receive a first voltage; a second CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit and that is configured to receive a second voltage; a third CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit, and that is configured to receive a third voltage; and a fourth CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit and that is configured to receive a fourth voltage; and a second half H-bridge having: a fifth CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit, and that is configured to receive the first voltage; a sixth CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit and that is configured to receive the second voltage; a seventh CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit, and that is configured to receive the third voltage; and an eighth CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit and that is configured to receive the fourth voltage. 
         [0005]    In accordance with the present invention, the digital logic further comprises: a first level shifter that is coupled to the duration generator and that is coupled to control the first, second, third, and fourth CMOS switches; and a second level shifter that is coupled to the duration generator and that is coupled to control the fifth, sixth, seventh, and eighth CMOS switches. 
         [0006]    In accordance with the present invention, the first voltage is greater than the second voltage, and wherein the second voltage is greater than a common mode voltage, and wherein the common mode voltage is greater than the third voltage, and wherein the third voltage is greater than the fourth voltage. 
         [0007]    In accordance with the present invention, the matching circuit further comprises: a first resistor that is configured to receive the common mode voltage and that is coupled to the first and fourth CMOS switches; a second resistor that is configured to receive the common mode voltage and that is coupled to the second and third CMOS switches; a third resistor that is coupled to the first and fourth CMOS switches; a fourth resistor that is coupled to the second and third CMOS switches; and a fifth resistor that is coupled to the third and fourth resistors. 
         [0008]    In accordance with the present invention, the resistance of the first and second resistors is substantially the same, and wherein the resistance of the first and second resistors is greater than the resistances of the third, fourth, and fifth resistors. 
         [0009]    In accordance with the present invention, each of the first, second, third, fourth, fifth, sixth, seventh, and eighth CMOS switches further comprises: a plurality of biased MOS transistors coupled together in a cascode arrangement; and a switching MOS transistor that is coupled to at least one of the biased MOS transistors and that is coupled to its level shifter at its gate and the matching circuit at its drain. 
         [0010]    In accordance with the present invention, the matching network further comprises an inductor that is coupled to the fifth resistor. 
         [0011]    In accordance with the present invention, the duration generator further comprises: an inverter that is coupled to the input buffer; a slewing circuit that is coupled to the inverter; a first stage that is coupled to the inverter and the slewing circuit; and a second stage having: a first logic circuit that is coupled to the first stage; and a second logic circuit that is coupled to the first stage. 
         [0012]    In accordance with the present invention, the first logic circuit is a NAND gate, and wherein the second logic circuit is a NOR gate. 
         [0013]    In accordance with the present invention, a method is provided. The method comprises receiving an input signal indicating a write event; generating a boost pulse and a write pulse corresponding with the write event; and generating a portion of a write signal with a half H-bridge using the boost pulse and the write pulse by: deactivating a first CMOS switch while activating a second CMOS switch to cause the portion of the write signal to transition from a first direct current (DC) voltage to a first peak voltage; after a first interval, deactivating the second CMOS switch while activating a third CMOS switch to cause the portion of the write signal to transition from the first peak voltage to a second DC voltage; after a second interval, deactivating the third CMOS switch while activating a fourth CMOS switch to cause the portion of the write signal to transition from the second DC voltage to a second peak voltage; and after a third interval, deactivating the fourth CMOS switch while activating the first CMOS switch to cause the portion of the write signal to transition from the second peak voltage to the first DC voltage. 
         [0014]    In accordance with the present invention, the step of generating the boost pulse and the write pulse further comprises: inverting the input signal; applying the inverted input signal to a slewing circuit to generate a slewed signal; logically combining the slewed signal with a delayed input signal to generate the boost pulse; and logically combining the slewed signal with a delayed inverse of the input signal to generate the write pulse. 
         [0015]    In accordance with the present invention, the step of logically combining the slewed signal with the delayed input signal further comprises NANDing the slewed signal with the delayed input signal. 
         [0016]    In accordance with the present invention, the step of logically combining the slewed signal with the a delayed inverse of the input signal further comprises NORing the slewed signal with the delayed inverse of the input signal. 
         [0017]    In accordance with the present invention, an apparatus is provided. The apparatus comprises a magnetic head; and a preamplifier having: an input buffer; a duration generator that is coupled to the input buffer; a first level shifter that is coupled to the duration generator; a second level shifter that is coupled to the duration generator; a matching circuit that is coupled to the magnetic head; a first half H-bridge having: a first CMOS switch that is coupled to be controlled by the first level shifter, that is coupled to the matching circuit, and that is configured to receive a first voltage; a second CMOS switch that is coupled to be controlled by the first level shifter, that is coupled to the matching circuit and that is configured to receive a second voltage; a third CMOS switch that is coupled to be controlled by the first level shifter, that is coupled to the matching circuit, and that is configured to receive a third voltage; and a fourth CMOS switch that is coupled to be controlled by the first level shifter, that is coupled to the matching circuit and that is configured to receive a fourth voltage, wherein the first voltage is greater than the second voltage, and wherein the second voltage is greater than a common mode voltage, and wherein the common mode voltage is greater than the third voltage, and wherein the third voltage is greater than the fourth voltage; and a second half H-bridge having: a fifth CMOS switch that is coupled to be controlled by the second level shifter, that is coupled to the matching circuit, and that is configured to receive the first voltage; a sixth CMOS switch that is coupled to be controlled by the second level shifter, that is coupled to the matching circuit and that is configured to receive the second voltage; a seventh CMOS switch that is coupled to be controlled by the second level shifter, that is coupled to the matching circuit, and that is configured to receive the third voltage; and an eighth CMOS switch that is coupled to be controlled by the second level shifter, that is coupled to the matching circuit and that is configured to receive the fourth voltage. 
         [0018]    In accordance with the present invention, the matching circuit further comprises: a first resistor that is configured to receive the common mode voltage and that is coupled to the first and fourth CMOS switches; a second resistor that is configured to receive the common mode voltage and that is coupled to the second and third CMOS switches; a third resistor that is coupled to the first and fourth CMOS switches; a fourth resistor that is coupled to the second and third CMOS switches; a fifth resistor that is coupled to the third and fourth resistors; a sixth resistor that is configured to receive the common mode voltage and that is coupled to the fifth and eighth CMOS switches; a seventh resistor that is configured to receive the common mode voltage and that is coupled to the sixth and seventh CMOS switches; an eighth resistor that is coupled to the fifth and eighth CMOS switches; a ninth resistor that is coupled to the sixth and seventh CMOS switches; and a tenth resistor that is coupled to the eighth and ninth resistors. 
         [0019]    In accordance with the present invention, the resistance of the first, second, sixth, and seventh resistors is substantially the same. 
         [0020]    In accordance with the present invention, each of the first, second, third, fourth, fifth, sixth, seventh, and eighth CMOS switches further comprises: a plurality of biased MOS transistors coupled together in a cascode arrangement; and a switching MOS transistor that is coupled to at least one of the biased MOS transistors and that is coupled to its level shifter at its gate and the matching circuit at its drain. 
         [0021]    In accordance with the present invention, the matching network further comprises: a first inductor that is coupled to the fifth resistor; and a second inductor that is coupled to the tenth resistor. 
         [0022]    In accordance with the present invention, the duration generator further comprises: an inverter that is coupled to the input buffer; a slewing circuit that is coupled to the inverter; a first stage that is coupled to the inverter and the slewing circuit; and a second stage having: a first logic circuit that is coupled to the first stage; and a second logic circuit that is coupled to the first stage. 
         [0023]    In accordance with the present invention, the first logic circuit is a NAND gate, and wherein the second logic circuit is a NOR gate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0025]      FIG. 1  is a diagram of an example of a conventional preamplifier; 
           [0026]      FIG. 2  is a diagram of an example of a preamplifier in accordance with the present invention; 
           [0027]      FIG. 3  is a diagram depicting an example of the half H-bridges and matching circuit of  FIG. 2 ; 
           [0028]      FIG. 4  is a diagram depicting an example of a portion of the duration generator of  FIG. 2 ; 
           [0029]      FIG. 5  is a timing diagram depicting an example operation of the portion of the duration generator shown in  FIG. 3 ; 
           [0030]      FIG. 6  is a timing diagram depicting the generation of a write signal for the preamplifier of  FIG. 2 ; and 
           [0031]      FIGS. 7 and 8  are diagrams depicting an example of the function of the matching circuit of  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0032]    Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
         [0033]    Turning to  FIGS. 2-4 , an example of a preamplifier  200  in accordance with the present invention can be seen. Similar to preamplifier  100 , preamplifier  200  is able to generate a current waveform reflecting write events for magnetic head  216 , driven at a peak current (for example) of about 100 mA over an interconnect having an impedance of (for example) about 50Ω. The current waveform uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for losses. One difference, however, is that the preamplifier  200  is formed using conventional CMOS process technologies and has low rail or supply voltages (i.e., about 4.5V and about 0V). 
         [0034]    In order to be able to generate the current waveform that is similarly produced by preamplifier  100 , preamplifier  200  employs a voltage-mode driver. This voltage-mode driver is generally comprised of half H-bridges  210 - 1  and  210 - 2  (which can generate the positive and negative portions of the differential write signal applied to head  216 ) and a matching circuit  214 . As shown in  FIG. 3 , the half-H-bridges  210 - 1  and  210 - 2  employ switches S 1  to S 8 , which are coupled to voltage sources  212 - 1  to  212 - 4 . The voltage sources  212 - 1  to  212 - 4  generate voltages VTPEAK, VTDC, VBPEAK, and VBDC (respectively) that can be within a range that extends beyond the rail or supply voltages (i.e., about 4.5V and about 0V). For example, the voltages VTPEAK, VTDC, VBPEAK, and VBDC can be about 5V, about 3.2V, about −1.2V, and about −3V, respectively. Conventional above-the-rail/below-the-rail techniques (such as those employing charge pumps) may be employed to generate theses voltages VTPEAK, VTDC, VBPEAK, and VBDC. By controlling the switching of switches S 1  to S 8  with level shifters  208 - 1  and  208 - 2 , the appropriate voltage levels can be selected to generate the current waveform for the head  216 . 
         [0035]    In order to perform the switching of switches S 1  to S 8 , it is desirable to allow a small voltage swing (with a small current) to change the state of switches S 1  to S 8  from the digital logic  204 . To accomplish this, each of the switches S 1  to S 8  are arranged as bias transistors (i.e., transistors Q 1 , Q 2 , Q 4 , Q 5 , Q 7 , Q 8 , Q 10 , Q 11 , Q 13 , Q 14 , Q 16 , Q 17 , Q 19 , Q 20 , Q 22 , and Q 23 ), that are biased with bias voltages (i.e., voltages VB 1  to VB 8 ) and that are cascoded with a switching transistor (i.e., transistors Q 3 , Q 6 , Q 9 , Q 12 , Q 15 , Q 18 , Q 21 , and Q 24 ). As shown, these transistors Q 1  to Q 24  are MOS transistors (i.e., PMOS or NMOS transistors). Looking, for example, to switch S 2 , PMOS transistor Q 4  is coupled to voltage source  212 - 1  so as to receive voltage VTPEAK at its source. This transistor Q 4  is also biased by voltage VB 2  (which can, for example, be about 2.4V) and is cascoded with PMOS transistor Q 5 . Transistor Q 5  is also biased by voltage VB 3  (which can, for example, be about 1.2V) and is cascoded with switching transistor Q 6  (which can, for example, be activated and deactivated by with a voltage swing between about 0V and about 1.2V). Fewer or more bias transistors (i.e., transistors Q 4  and Q 5 ) may be employed in switches, and the bias transistors (i.e., transistors Q 4  and Q 5 ) can be, for example, about 2 to 3 times larger than the switching transistors (i.e., transistor Q 6 ). 
         [0036]    Turning to  FIG. 5 , an example of the generation of the current waveform, corresponding to a write event (or portion of the write signal) can be seen. For this example, control signals TPC, TDC, BDC, and BTC are shown with respect to switches S 1  to S 4  of half H-bridge  210 - 1 , while complementary signals for half H-bridge have been omitted for the sake of clarity of illustration. Initially, at time T 1 , when the waveform corresponding to the write event is initiated, switch S 2  is activated while switch S 3  is deactivated. This allows the write signal to transition from the voltage VBDC to voltage VTPEAK to allow for an overshoot in the interval between times T 1  and T 2 . At time T 2 , signal TPC deactivates switch S 2  while signal TDC activates switch S 1 , causing the write signal to transition from voltage VTPEAK to VTDC. The write signal remains as voltage VTDC for the interval between times T 2  and T 3 . At time T 3 , switch S 4  is activated by signal BPC while switch S 1  is deactivated. This allows for an overshoot at voltage VBPEAK for the interval between times T 3  and T 4 . Then, at time T 4 , signals BPC and BDC, respectively, deactivate switch S 4  and activate switch S 3  to return the write signal to voltage VBDC. 
         [0037]    With this configuration, any capacitance at the output node (namely where the preamplifier  200  is coupled to the interconnect or head  216 ) modifies the output impedance long into the preamplifier  200 . Because CMOS transistors are employed (i.e., transistor Q 3 ), there is a disadvantage in terms of matching since the drain capacitance of CMOS transistors is usually much larger than collector capacitance of bipolar transistors, and because electrostatic discharge (ESD) structures (which tend to be capacitive) are usually coupled to the output nodes of the preamplifier  200 , matching can be further complicated. These mismatches can cause reflections, which may degrade the write signal. So, to combat these mismatch issues, matching circuit  214  (as shown in  FIGS. 2 and 3 ) can be employed. As shown, resistors R 1 , R 2 , R 7 , and R 8  receives a common mode voltage VCM and are coupled to switches S 1  to S 8 . Additionally, resistors R 3  to R 6 , R 9 , and R 10  are provided. Typically, resistors R 3  to R 6 , R 9 , and R 10  can be on the order of about 30Ω to about 50Ω, while resistors R 1 , R 2 , R 7 , and R 8  are usually ten times larger (or greater), having, for example, a values of about 2 kΩ. Matching inductors L 1  and L 2  may also be included. Because the inductors L 1  and L 2  (which, typically, are not magnetically coupled) are in series with the matching resistances R 1  to R 10 , the inductors L 1  and L 2  can tolerate a low Q, and a large variation in the inductance of inductors L 1  and L 2  and/or the matching capacitance of capacitors C 1  and C 2  can be tolerated. As a result of employing this, matching circuit  214  can be substantially reduced (as shown in  FIGS. 6 and 7 ). 
         [0038]    One other advantage the preamplifier  200  has over preamplifier  100  is the reduction in redundant logic. As shown in  FIG. 1 , preamplifier  100  includes duration generators  106 - 1  and  106 - 2 , whereas preamplifier  200  employs duration generator  206  (which is shown in greater detail in  FIGS. 3 and 4 ). The outputs from duration generator  206  are used by level shifter  208 - 1  and  208 - 2 . In operation, an input signal IN is provided to inverter  302 - 1 , and the inverted input signal XIN is provided to the slewing circuit (which is generally comprised of NMOS transistor Q 25 , current source  306 , and capacitor C 3 ), inverter  302 - 3  (of stage  312 ) and transmission gate  304 - 1  (of stage  312 ). When the inverter input signal XIN is provided to the slewing circuit, signal A begins to slew. Once signal A begins to slew, NAND gate  308  begins to output a boost pulse (as part of the boost signal BST) through transmission gate  304 - 2  and inverter  302 - 5 , while an inverse of the boost pulse (as part of the inverted boost signal XBST) is output through inverters  302 - 4  and  302 - 6 . Once signal A becomes sufficiently large, it causes inverter  302 - 2  (and, thus, the inverted signal AX) to change state, triggering the end of the boost pulse. Additionally, when the signal AX changes state, the NOR gate  310  is able to output a write pulse (as part of the write signal WD) through inverters  302 - 7  and  302 - 9  and an inverted write pulse (as part of the inverted write signal XWD) through transmission gate  304 - 3  and inverter  302 - 8 . Moreover, to be able to achieve a proper alignment of these signals, the components within each of stages  312 ,  314 ,  316 , and  318  have substantially matched delays. For example, an additional NOR gate (which receives a “0” as one of its inputs) and an NAND gate (which receives a “1” as one of its inputs) can be included so as to provide for delay matching. Also, alternatively, multiple durations generators may be employed with a level shifter in digital logic  204 . 
         [0039]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.