Abstract:
A digital-to-analog converter employs current drive circuits connected to an output voltage terminal. At least one of the current drive circuits includes a current division circuit that splits current from a first power source into a plurality of current paths in response to at least a first bias voltage. A current dissipation circuit is between one of the paths and a second power supply source, and a current switching circuit selectably connects another of the paths to the voltage terminal, which is connected to the second power source through a voltage establishing device. The switching circuit responds to one of the digital bits.

Description:
FIELD OF THE INVENTION 
     The present invention is in the field of digital-to-analog converters and is more specifically related to a digital-to-analog converter establishing an output voltage by adjusting current. 
     BACKGROUND OF THE INVENTION 
     Many electronic circuits use digital-to-analog converters (DACs) for converting digital signals to corresponding analog signals. For example, cellular base stations, wireless communication systems, direct digital frequency synthesizers, signal reconstruction circuits, test equipment, high resolution imaging systems, and arbitrary waveform generators often require high resolution, high speed DACs. 
     A DAC (or ADC) is an important component for processing video signals and displaying still and sub pictures in imaging systems such as televisions, video tape recorders, digital cameras, and various multi-media apparatuses. More particularly, digitized video signals are common in interpolating, compressing, expanding, and displaying images in multi-media technology such as with computer systems, as well as in the televisions and digital cameras, and such digitized video signals often need to be converted to analog form after digital processing. Accordingly, enhancing the resolution of digital-to-analog converters in the video and multi-media imaging systems is desirable. 
     FIG. 1 shows the construction of a DAC system having buffer circuits  10  and  40 , a decoder  20 , a delay circuit  30 , a bias voltage supply circuit  50 , and a DAC core circuit  60 . The buffer circuit  10 , which includes two buffers  11  and  12 , receives digital signals (bits) D 1  through D 10 . The decoder  20  receives the four most significant bits D 7  through D 10  and generates a 15-bit digital signal having between zero and fifteen bits in a logic low state, depending on the value represented by the 4-bit input signal to decoder  30 . The delay circuit  30  delays the 6-bit digital signal from the buffer  12  of the buffer circuit  10  and applies a delayed 6-bit digital signal to buffer  42  of the buffer circuit  40  when decoder  20  applies the 15-bit signal to buffer  41  of buffer circuit  40 . DAC core circuit  60  receives the 15-bit and 6-bit digital signals from the buffer circuit  40  at the same time. The bias voltage supply circuit  50  generates bias voltages VBa and VBb to control the DAC core circuit  60  for generation of an appropriate output voltage Vdac for a display apparatus such as electron gun  70 . 
     The DAC core circuit  60 , as shown in FIG. 2, has twenty-one current drive circuits CURI through CUR 21 , each assigned to a corresponding one of the twenty-one digital signals (15 bits+6 bits). The bias voltages VBa and VBb and the digital signals D 1  ′ through D 21 ′ (and their complements D 1 B′ through D 21  B′) control currents I 1  through I 21  that the current drive circuits conduct to an output summing node N 1  at which output voltage Vdac is generated. When activated each of current drive circuits CUR 2  to CUR 6  provides about twice the current of the preceding one of circuits CUR 1  to CUR 5 . Current drive circuits CUR 7  to CUR 21  all provide about the same current when respective digital signals D 1 ′ to D 21 ′ are in the logic low state. Output voltage Vdac results from a total current Isum flowing from the node N 1  to a substrate voltage VSS through a resistor R. 
     FIG. 3 illustrates a situation where the output voltage Vdac from the DAC core circuit  60  is intended to match the shape of an analog wave. Unfortunately, when the output voltage Vdac is near a maximum voltage Vmax, drain-to-source voltages of PMOS transistors PM 1  and PM 2  in current drive circuits CUR 1  and CUR 2  are less than when output voltage is near a minimum voltage Vmin. Accordingly, currents I 1  and I 2  that respectively flow through current drive circuits CUR 1  and CUR 2  to the node N 1  decrease as shown with curve C of FIG. 4 because variation in the output voltage Vdac at the node N 1  affects the drain-to-source voltages of PMOS transistors PM 1  and PM 2 . For example, current I 2  from current drive circuit CUR 1  is ideally one quarter (¼) of a current I that flows into the common source node of transistors PM 1  and PM 1 ′, and current I 4  from current drive circuit CUR 2  is ideally one half (½) of the current I that flows in the common source node of transistors PM 2  and PM 2 ′. Correspondingly, as shown in the curve D, currents I 1 ′ (ideally ¾ of current I) and I 2 ′ (ideally ½ of current I), which flow to reference voltage VSS through respective PMOS transistors PM 1 ′ and PM 2 ′, increase as output voltage Vdac increases. The drain-to-source current Ids (of PMOS transistors PM 1  and PM 2 ) declines, as shown with curve E of FIG. 5 (curve F is an ideal form), in the saturation region so that the drain-to-source current is influenced by a λ-effect (i.e., channel length modulation effect) induced from node N 1 . Such a decline of the current, as shown in FIG. 3, lowers levels of output voltage Vdac to levels B, which are lower than the desired levels A when output voltage Vdac is near maximum voltage Vmax. This can degrade the resolution of a display apparatus using the analog output voltage from the DAC. 
     SUMMARY OF THE INVENTION 
     A digital-to-analog converter in accordance with an embodiment of the invention employs a plurality of current drive circuits connected to an output voltage terminal. At least one of the current drive circuits includes: a current division circuit that splits a current from a first power source (e.g., a supply voltage terminal) among a plurality of current paths in response to at least one bias voltage; a current dissipation circuit connected between one of the current paths and a second power source (e.g., a reference voltage terminal); and a current switching circuit for selectably connecting another of the current paths to the voltage terminal. A voltage establishing device connects to the output voltage terminal. The switching circuit transfers a shared current to the voltage terminal in response to corresponding one of the digital bits. The current division circuit can determine the magnitude of the current output to the output voltage terminal, while the current switching circuit determines whether the current drive circuit outputs the current to the voltage output terminal. The current switching circuit also shields the current division circuit from the effects of high output voltage so that the current remains constant and accurate even when the output voltage approaches its maximum. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: 
     FIG. 1 is a block diagram of a digital-to-analog converter; 
     FIG. 2 shows a circuit diagram of a core circuit in the converter of FIG. 1; 
     FIG. 3 shows an output voltage generated from the core circuit of FIG. 2 to generate an analog waveform; 
     FIG. 4 shows plots of the current through different transistors in a current supply circuit of FIG. 2; 
     FIG. 5 shows the current-voltage characteristics of a MOS transistor; 
     FIG. 6 is a circuit diagram of a core circuit employed in a digital-to-analog converter in accordance with an embodiment of the invention; 
     FIG. 7 shows an output voltage generated from the core circuit of FIG. 5 to generate an analog waveform; 
     FIG. 8A shows current from a current drive circuit of FIG. 6 as a function of the output voltage of the core circuit; and 
     FIG. 8B shows a comparison between current in the circuit core of FIG.  2  and the circuit core of FIG.  6 . 
     In the figures, like reference numerals denote like or corresponding parts. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 6 shows an embodiment of a DAC core circuit according to the invention. The DAC core circuit of FIG. 6 may be used as DAC core  60  in the arrangement of the digital-to-analog converter of FIG.  1 . Referring to FIG. 6, twenty-one current drive circuits CDR 1  through CDR 21  are connected in parallel between the power supply voltage Vcc and output voltage terminal N 60 . A resistor R 60  connects output voltage terminal N 60  to a reference (or ground) voltage VSS. Current drive circuits CDR 1  through CDR 6  respectively receive digital signals D 1 ′ through D 6 ′ from buffer  41 , and current drive circuits CDR 7  through CDR 21  respectively receive digital signals D 7 ′ through D 21 ′ from buffer  42 . 
     Current drive circuits CDR 1  and CDR 2 , which provide the smallest currents, differ in construction from the current drive circuits CDR 3  through CDR 21 , even when the sizes of transistors are ignored. Alternative embodiments of the invention further employ the principles and construction of the current drive circuits CDR 1  and CDR 2  in one or more of current drive circuits CDR 3  to CDR 21 . The current drive circuits CDR 1  and CDR 2 , also differ from the current drive circuits CUR 1  and CUR 2  (FIG. 2) and as a result improve the accuracy and resolution of output voltage Vdac*. More particularly, current drive circuits CDR 1  and CDR 2  maintain a more constant output current to avoid non-linearity in the digital-to-analog conversion and provide an output voltage that can more nearly match an original analog waveform. The other current drive circuits CDR 3  through CDR 21  operate within a narrower range of output voltage Vdac* and are therefore less affected by changes in the output voltage Vdac*. Accordingly, current drive circuits CDR 3  through CDR 21  can use the same construction as corresponding current drive circuits CUR 3  to CUR 21  of FIG.  2 . 
     The current drive circuits CDR 1  and CDR 2  are substantially the same but have transistors sized differently so that current drive circuit CDR 1  has half the output current of current drive circuit CDR 2 . The current drive circuit CDR 1  (or CDR 2 ) includes a current division part  1 A (or  2 A), a discharging part  1 B (or  2 B), and a switching part  1 C (or  2 C). The division part  1 A includes: a PMOS transistor PM 1  connected between supply voltage Vcc and a node N 11 ; a PMOS transistor PM 12  having source connected to the node N 11 , and a PMOS transistor PM 13  connected between the node N 11  and a node N 12 . The gates of transistors PM 11  and PM 12  receive the respective bias voltages VBa and VBb from the bias voltage supply circuit  50  of FIG.  1 . The gate of transistor PM 13  also receives the bias voltage VBb. The discharging part  1 B includes a PMOS transistor PM 14  connected between the drain of PMOS transistor PM 12  and ground voltage VSS, and the gate of PMOS transistor PM 14  is also connected to ground voltage VSS. The switching part  1 C includes: a PMOS transistor PM 15  connected between the node N 12  and ground voltage VSS; and a PMOS transistor PM 16  connected between the node N 12  and the output voltage terminal N 60 . The gate of PMOS transistor PM 16  receives digital signal D 1 ′ while the gate of PMOS transistor PM 15  receives digital signal D 1 B′, which is the complement of signal D 1 ′. 
     In the same manner, in current drive circuit CDR 2 , a division part  2 A includes a PMOS transistor PM 21  connected between supply voltage Vcc and a node N 21 , a PMOS transistor PM 22  having a source connected to node N 21 , and a PMOS transistor PM 23  connected between nodes N 21  and N 22 . The gates of transistors PM 21  and PM 22  are respectively coupled to bias voltages VBa and VBb from bias voltage supply circuit  50  of FIG.  1 . The discharging part  2 B is a diode-connected PMOS transistor PM 24  connected between the drain of PMOS transistor PM 12  and ground voltage VSS to which the gate of PMOS transistor PM 24  also connects. The switching part  2 C includes a PMOS transistor PM 25  connected between node N 22  and ground voltage VSS, and a PMOS transistor PM 26  connected between node N 22  and output voltage terminal N 60 . The gate of transistor PM 26  receives digital signal D 2 ′, and the gate of transistor PM 25  receives digital signal D 2 B′, which is the complement of signal D 2 ′. 
     In current drive circuit CDR 1 , which corresponds to the least significant bit D 1 ′ and provides the finest current adjusting factor for a high resolution, the current division ratio between PMOS transistors PM 12  and PM 13  is 3:1, so that three quarters (¾) of the current I that flows into node N 11  passes through PMOS transistor PM 12  and one quarter (¼) of the current I passes through PMOS transistor PM 13 . In current drive circuit CDR 2 , which corresponds to the second least significant bit D 2 ′and provides the secondly finest current adjusting factor for a high resolution, the current division ratio between PMOS transistors PM 22  and PM 23  is 1:1, so that one half (½) of the current I passes through PMOS transistor PM 22  and the other half (½) of the current I passes through PMOS transistor PM 23 . The current passing through PMOS transistor PM 12  of current drive circuit CDR 1  passes through diode-connected PMOS transistor PM 14  of discharging part  1 B and dissipates into ground voltage VSS. Similarly, the current passing through PMOS transistor PM 22  of current drive circuit CDR 2  passes through diode-connected PMOS transistor PM 24  and dissipates into ground voltage VSS. On the other hand, the current passing through PMOS transistor PM 13  flows into terminal N 60  through switching transistor PM 16 , which is on when the digital signal D 1 ′ is at the logic low voltage level, and the current passing through PMOS transistor PM 23  flows into terminal N 60  through switching transistor PM 26 , which is on when the digital signal D 2 ′ is at the logic low level. 
     Referring to FIG. 7, with the lapse of time, the output voltage Vdac* rises from a minimum voltage level Vmin to the maximum voltage level Vmax. When all of the digital signals D 1 ′ to D 21 ′ are activate (i.e., in the logic low voltage state), the output voltage Vdac* is at the maximum voltage Vmax. In this case, the total current Isum flowing from the output terminal N 60  to ground voltage VSS through the resistor R 60  is 255×I+(½)I+(¼)I, where 255×I is the summation of the currents flowing out of CDR 3  through CDR 21  for data signals D 3 ′ to D 21 ′ resulting from input data bits D 3  to D 10 , and (½)I and (¼)I are the currents out of current drive circuits CDR 2  and CDR 1  corresponding to data bits D 1  and D 2 . The output voltage Vmax is the product Isum×R, where R is the resistance or the resistor R 60 . The output voltage Vdac* moves from voltage Vmax toward voltage Vmin, as the digital signals D 1 ′ to D 21  are deactivated to high levels. Such rising and falling of output voltage Vdac* is repeatedly performed to generate the oscillation of an analog wave such as shown in FIG.  7 . 
     When output voltage Vdac* is near the maximum voltage Vmax, the high level of output voltage Vdac* does not significantly affect the drain-to-source voltage of the PMOS transistor PM 13  even though the high output voltage Vdac* reduces the drain-to-source voltage of the PMOS transistor PM 16 . Accordingly, the amount of the current supplied into the source of PMOS transistor PM 16  remains constant (¼ of I). Hence, PMOS transistor PM 16  can be large enough to transfer the predetermined and constant amount of current (¼ I) to the terminal N 60 . Similarly, in current drive circuit CDR 2 , the currently high output voltage Vdac* does not significantly affect the drain-to-source voltage of PMOS transistor PM 23  even though the high output voltage Vdac* reduces the drain-to-source voltage of PMOS transistor PM 26 . Accordingly, the amount of the current supplied into and transferred through PMOS transistor PM 26  remains ½ of I. As shown in FIG. 7, the stepped (or digitized) levels of output voltage Vdac* accord with the corresponding values of the analog wave without the shortfall shown in FIG. 3 near maximum voltage Vmax. 
     FIG. 8A shows the results of simulating with the currents flowing through the current drive circuit CDR 1 . As shown by plot J, the current passing through PM 12  and PM 14  increases logarithmically, while the current passing through transistors PM 13  and PM 16  decreases as shown by curve K. Considering that a typical DAC has a maximum voltage Vmax of about 1 V, the difference between the currents of plots J and K is under about 1 microampere at the maximum output voltage. As shown in FIG. 8B, this difference is insignificant when compared to current drop arising with the circuit of FIG.  2 . 
     As described above, the present invention offers significant advantages over conventional DACs in that the linearity of the output voltage is improved by maintaining a more constant current. Accordingly, the output voltage of the DAC core circuit better matches the desired analog signals, particularly around the maximum voltage level. Therefore, the output voltage of the DAC core circuit of the invention can contribute to enhancing resolution of a display apparatus. 
     While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, the invention is not limited to the disclosed embodiment, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the invention.