Abstract:
An amplifier with power supply switching is arranged so that the levels of the power supply voltages to be supplied to the amplifying elements of the output stage are switched over in accordance with the level and the rise time of a signal corresponding to an input signal of the amplifier, thereby, to enhance the power efficiency and to prevent an increase of distortion, as well as to reduce switching noises which tend to occur during the switching of the power supply voltages.

Description:
BACKGROUND OF THE INVENTION 
     (a) Field of the Invention: 
     The present invention relates to an amplifier with power supply switching, and more particularly to an amplifier of the type described which is arranged to effect switching of the levels of the power supply voltages to be supplied to the amplifying elements of the output stage in accordance with the level of a signal corresponding to an input signal. 
     (b) Description of the Prior Art: 
     There is known a power amplifier intended to improve the power efficiency thereof, arranged so that in case the level of an input signal is low, a power supply having a low level of voltage is connected to the output stage of the amplifier, and that in case the level of an input signal is high, the output stage is connected to a power supply having a high level of voltage. For example, FIG. 1 shows an example of such known power amplifier utilizing a single ended push-pull (SEPP) circuit of the balanced power supply type. In the Figure, reference numerals 1 and 2 represent transistors of the output stage which are arranged so that one 1 of the transistors is adapted to be connected to either a dc power supply 4 or to power supplies 3 and 4, whereas the other transistor 2 is adapted to be connected to either a dc power supply 5 or power supplies 5 and 6. In this example, in case the level of an input signal which is applied to an input terminal 7 is low, the transistors 1 and 2 are connected to the dc power supplies 4 and 5, respectively, whereas in case the level of an input signal is high, switching circuits 8 and 9 are both rendered to the conductive state, so that the transistors 1 and 2 are connected to the dc power supplies 3 and 4, and the dc supplies 5 and 6, respectively. The switching circuits 8 and 9 are adapted to be driven by a comparator circuit 11 which is to receive an output of an absolute value circuit 10. More specifically, the absolute value circuit 10 is a circuit intended to seek the absolute value of an output signal derived at an output terminal 13. The level of an output of this absolute value circuit 10 is compared with the level of a reference voltage V a  in the comparator circuit 11, so that the on-off actions of the switching circuits 8 and 9 are controlled by the result of the comparison. This known power amplifier is so arranged that the level of an output signal is detected in place of direct detection of the level of an input signal. Also, a resistor 14 in the cirucitry is a load resistor. 
     In the known power amplifier having the foregoing circuit arrangement, the timing of switching of the switching circuits 8 and 9 provides problems. More particularly, if the level of the reference voltage V a  is set substantially equal to the level of the voltage of either the dc power supply 4 or 5, there will occur such inconvenience that, when the input terminal 7 is applied with a high level input signal having a quick build-up, the timing of power supply from either the dc power supply 3 or 6 fails to follow the quick variations of the level of the input signal due to the delay of operation of the switching circuits 8 and 9, so that the resulting output signal will become distorted. Also, if the level of the reference voltage V a  is set low to prevent the development of such distortion, there could occur an instance wherein, even when the input signal is of such level that can be covered sufficiently by the dc power supplies 4 and 5, the transistors 1 and 2 are supplied with voltages of a level representing the voltages of these dc power supplies 4 and 5 added with the voltage of the dc power supplies 3 and 6, respectively. For this reason, there arises the problem of an increased power loss and a lowered power efficiency in the transistors 1 and 2. 
     SUMMARY OF THE INVENTION 
     It is, therefore, a primary object of the present invention to provide an amplifier which is able to attain, at the same time, both the prevention of development of signal distortion and an enhanced power efficiency. 
     Another object of the present invention is to provide an amplifier of the type described, wherein the control of switching circuit is performed based on the level and the build-up time or speed of a signal corresponding to an input signal. 
     Still another object of the present invention is to provide an amplifier of the type described, which develops reduced switching noises during the switching of power supply voltages by the switching circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing a known power amplifier with means for switching power supply voltages. 
     FIG. 2 is a block diagram showing the basic structure of power amplifier according to the present invention. 
     FIG. 3 is a chart for explaining the operation of the power amplifier shown in FIG. 2 in case an input signal is a low frequency signal. 
     FIG. 4 is a chart for explaining the operation of the power amplifier shown in FIG. 2 in case an input signal is a high frequency signal. 
     FIG. 5 is a circuit diagram showing a concrete embodiment of the power amplifier according to the present invention. 
     FIGS. 6A to 6E are timing charts for explaining the operation of the power amplifier shown in FIG. 5 
     FIG. 7 is a circuit diagram showing another concrete example of the power amplifier according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will hereunder be described of some preferred embodiments of the present invention by referring to the accompanying drawings. 
     FIG. 2 is a block diagram showing the basic structure of the power amplifier according to the present invention. In the Figure, an input terminal 20 is connected to a base of a transistor 22 via a dc power supply 21, and also to the base of a transistor 24 via a dc power supply 23. In this embodiment, the dc power supplies 21 and 23 are intended for biasing the transistors 22 and 24, respectively. The collector of the transistor 22 is connected to a positive voltage terminal of a dc power supply 26 via a reverse-current preventing diode 25, and also to a positive voltage terminal of a dc power supply 28 via a switching circuit 27. Also, a negative voltage terminal of said dc power supply 28 is connected to the positive voltage terminal of the dc power supply 26. The collector of the transistor 24 is connected to a negative voltage terminal of a dc power supply 30 via a reverse-current preventing diode 29, and also to a negative voltage terminal of a dc power supply 32 via a switching circuit 31. Also, the positive voltage terminal of the dc power supply 32 is connected to the negative voltage terminal of the dc power supply 30. The emitters of the transistors 22 and 24 are connected to an output terminal 35 via resistors 33 and 34, respectively. The negative voltage terminal of the dc power supply 26 and the positive voltage terminal of the dc power supply 30 are both grounded. Also, a load resistor 36 is inserted between the output terminal 35 and the ground. 
     The diodes 25 and 29 are assigned to supply to the collectors of the transistors 22 and 24 a positive voltage +V 1  of the dc power supply 26 and a negative voltage -V 1  of the dc power supply 30, in case the switching circuits 27 and 31 are in their &#34;off&#34; state. Also, the switching circuits 27 and 31 are arranged to be controlled of their on-off actions by an output of a controlling circuit 37. In case these two switching circuits 27 and 31 are both in their &#34;on&#34; state, there is supplied to the collector of the transistor 22 a voltage +V 2  which is the sum of the respective output voltages of the dc power supplies 26 and 28, and also there is supplied to the collector of the transistor 24 a voltage -V 2  which is the sum of the respective output voltages of the dc power supplies 30 and 32. 
     Along therewith, an output signal derived at the output terminal 35 is supplied to one of the input terminals of a comparator circuit 38 (first detecting means) via an absolute value circuit 44, and also to one of the input terminals of a comparator circuit 40 via a differentiator circuit 39. To the other ones of the input terminals of the comparator circuits 38 and 40 are supplied reference voltages V b  and V c  from dc power supplies 41 and 42, respectively. Also, the outputs of the comparator circuits 38 and 40 are adapted to be supplied to the controlling circuit 37. The comparator circuit 38 is assigned to compare the level of the output of the absolute value circuit 44 with the level of the reference voltage V b , and in case the level of the output of the absolute value circuit 44 is higher than the level of the reference voltage V b , this comparator circuit 38 outputs an &#34;0&#34; signal of binary logic level, and in case it is lower than the reference voltage, it outputs a &#34;1&#34; signal of binary logic level. It should be understood here that the level of the reference voltage V b  is set at a value slightly lower than the level of the output voltages V 1  of the dc power supplies 26 and 30. Also, the level of the reference voltage V c  is set at a value substantially lower than that of said reference voltage V b , or at zero. Typically, it is set at a value about 1/3 of the level of the reference voltage V b . The differentiator circuit 39 and the comparator cirucit 40 jointly constitute a means 43 (second detecting means) for detecting an input signal of quick build-up, i.e. high frequency input signal. In case the absolute value circuit 44 outputs a signal whose rise time is shorter than a predetermined rise time, the comparator circuit 40 outputs a signal of &#34;0&#34; level. Also, in case the absolute value circuit 44 outputs a signal having a rise time longer than the predetermined rise time, this comparator circuit 40 outputs a signal of &#34;1&#34; level. Said predetermined rise time or build-up time means a period of time determined by the reference voltage V c  and by a time constant which is defined by the differentiator circuit 39. Also, the controlling circuit 37 is a circuit which will output a controlling signal S to render the switching circuits 27 and 31 conductive in case either one of the output signals of the comparator circuits 38 and 40 has become a &#34;0&#34; signal. 
     Next, description will hereunder be made of the operation of the power amplifier having the foregoing arrangement. Firstly, when there is applied to the input terminal 20 an input signal of a low frequency and of a relatively low level, i.e. when an input signal such that the peak value of an output signal corresponding to said input signal is lower than the level of the reference voltage V b  is applied, the outputs of the comparator circuits 38 and 40 both will become a &#34;1&#34; signal, and accordingly no controlling signal S is outputted from the controlling circuit 37, so that both switching circuits 27 and 31 are rendered non-conductive. Thus, a voltage +V 1  and a voltage -V 1  of the dc power supplies 26 and 30 are supplied to the transistors 22 and 24, respectively. 
     In case there is applied to the input terminal 20 an input signal of a low frequency and of a relatively high level, i.e. a signal such that the peak value of an output signal corresponding to this input signal is higher than the level of the reference voltage V b , the output of the comparator circuit 38 becomes a &#34;0&#34; signal at the point of time when the level of the output of the absolute value circuit 44 has exceeded the level of the reference voltage V b . As a result, there is outputted a controlling signal S from the controlling circuit 37, so that the switching circuits 27 and 31 are both rendered conductive. Thus, a voltage +V 2  and a voltage -V 2  are supplied to the transistors 22 and 24, respectively. And, at the point of time when the level of the output of the absolute value circuit 44 has become lower than the level of the reference voltage V b , the output of the comparator circuit 38 is switched back to the &#34;1&#34; level signal, and as a result no controlling signal S is allowed to be outputted. Accordingly, the switching circuits 27 and 31 are both switched back to their non-conductive state. During the foregoing operation, the output of the comparator circuit 40 holds the &#34;1&#34; level signal because the input signal has a low frequency. 
     In connection with the foregoing operation, the relationship between the output signal derived at the output terminal 35 and the collector potential of the transistor 22 is illustrated in FIG. 3. In this Figure, the square-pulse like line indicated at symbol A represents the collector potential of the transistor 22, and the curved line indicated at symbol B represents the output signal derived at the output terminal 35. As will be understood clearly from this Figure, it takes a length of time t 1  before the level of the output signal arrives at the level of the voltage V 1  afer gaining the level of the reference voltage V b  even where the level of the reference voltage V b  is set at a level slightly low in the vicinity of the voltage V 1 . Accordingly, if the total of the switching time of the switching circuit 27 and the operation delay time of such circuits as the comparator circuit 38 and the controlling circuit 37 is smaller than the time t 1 , no distortion will appear in the output signal. However, in case the output signal has a high frequency, i.e. in case the rise or build-up of the output signal is quick, the time t 1  will become smaller or shorter than the total of the switching time of the switching circuit 27 and the delay time in such circuits as the comparator circuit 38, so that the variation of the collector voltage of the transistor 22 will no longer become able to follow the output signal. Thus, the output signal will be distorted. It is the circuit, i.e. the build-up speed detecting means 43, that is inserted to prevent such undesirable condition to take place. 
     Next, description will be made-of the instance wherein this detecting means 43 is operated. 
     In case there is applied to the input terminal 20 an input signal of a high frequency and of a relatively high level, it should be understood that, because of the output signal builds up quickly, the differentiator circuit 39 generates an output voltage of a certain level. In case the level of this output voltage is above the reference voltage V c , the output of the comparator circuit 40 becomes a &#34;0&#34; signal, so that a controlling signal S is outputted from the controlling circuit 37. More specifically, in such instance, a controlling signal S is outputted at the timing T 1  shown in FIG. 4. It should be noted here that the period of time in which the output of said comparator circuit 40 becomes &#34;0&#34; signal is only a trifle length of time, but that the controlling signal S is adapted to be outputted successively for a certain period of time by the action of a holding circuit provided within the controlling circuit 37. If, during the period of time in which this controlling signal S is outputted successively, the level of the output signal indicated at symbol B in FIG. 4 reaches the reference voltage V b , i.e. at time T 3  in FIG. 4, the output of the comparator circuit 38 becomes an &#34;0&#34; signal. As a result, the controlling signal S continues to be outputted successively. And, when the level of the output signal becomes lower than the reference voltage V b , i.e. at timing T 2  in FIG. 4, the output of the controlling signal S is ceased. As a result, the collector potential of the transistor 22 will vary in such manner as shown by symbol A in FIG. 4. It should be noted here that the time scale on the horizontal axis in the chart of FIG. 4 is exaggerated than the time scale on the horizontal axis in FIG. 3. 
     In case the frequency of the input signal is high as in the instance mentioned above, a controlling signal S is outputted at build-up timing T 1  of the output waveshape. Accordingly, as compared with such instance wherein a controlling signal S is outputted by being based only on the level of the output signal, i.e. in case the input signal is of a low frequency as stated above, it is possible to output a controlling signal S earlier by the period of time t 2  shown in FIG. 4. As a result, even where there is a time delay in the switching time of the switching circuits 27 and 31 and in the controlling circuit 37 or like circuit, the variation of the collector potential of the transistor 22 is able to follow the variation of the output signal, so that it becomes possible to prevent the development of distortion. Not only that, but also it becomes possible to set the reference voltage V b  at a value quite close to the voltage V 1 , so that it is possible to enhance the power efficiency of this power amplifier. 
     Hereunder will be explained a couple of concrete embodiments of the present invention. FIGS. 5 and 7 are circuit diagrams showing concrete embodiments of the present invention. In these Figures, those parts corresponding to the respective regions of the circuitry shown in FIG. 2 are given like reference numerals and symbols. 
     The power amplifier shown in FIG. 5 is arranged so that, in place of the provision of the absolute value circuit 44 employed in the embodiment shown in FIG. 2 which gives the basic idea of the present invention, there are provided two systems each comprising a comparator circuit 38, a signal build-up speed detecting means 43 and a controlling circuit 37, so as to control the switching circuits 27 and 31 by these circuits in the two systems, respectively. In FIG. 5, the suffix &#34;a&#34; which is given to reference numerals is assigned to the respective parts of the positive side system which is intended to control the switching circuit 27, whereas the suffix &#34;b&#34; is assigned to the respective parts of the negative side system assigned to control the switching circuit 31. More particularly, in FIG. 5, the switching circuit 27 is controlled by a controlling signal S 1  which is an output signal of a controlling circuit 37a. On the other hand, the switching circuit 31 is controlled by a controlling signal S 2  which is an output signal of a controlling circuit 37b. The controlling circuit 37a is comprised of diodes 50a and 51a, a capacitor 52a, resistors 53a and 54a, and a transistor 55a. In this controlling circuit 37a, the diodes 50a and 51a serve as an OR circuit for deriving output signals of comparator circuits 38a and 40a, respectively. The output of this OR circuit is amplified by the transistor 55a, and supplied, as controlling signal S 1 , to the switching circuit 27. Also, the capacitor 52a is intended to hold the controlling signal S 1  for a certain period of time. More particularly, in case an input signal of a high frequency is applied to the input terminal 20, and in case an output signal shown by FIG. 6A is derived at the output terminal 35, the output of the comparator circuit 38a will have such waveshape as shown in FIG. 6B. Also, the output of the comparator circuit 40a will have a waveshape as shown in FIG. 6C. Let us here assume that the circuit is not provided with the capacitor 52a. Then, the controlling signal S 1  will not be outputted for a period of time t 3  shown in FIG. 6B to cause a cut-off period. Since, however, the controlling signal S 1  is held for a certain period of time by the capacitor 52a, the controlling signal S 1  will have a waveshape as shown in FIG. 6D, so that such cut-off period is prevented from taking place. It should be noted here that in the chart of FIG. 6, the time t 4  also is one which is obtained from the holding action by the capacitor 52a. 
     The switching circuit 27 is comprised of resistors 60a-62a, capacitors 63a-65a, a transistor 66a, and a diode 67a. In this arrangement, the transistor 66a is a switching transistor. Also, the time constant circuit which is formed by the resistors 60a-62a and the capacitors 63a-65a is intended to prevent the development of switching noises of the transistor 66a. More particularly, in case a control signal S 1  shown in FIG. 6D is applied to the switching circuit 27, the collector potential of the transistor 22 will rise with a time constant which is determined by the resistors 60a and 61a and the capacitors 63a-65 a, and will decay with the time constant determined by the capacitors 63a-65 a and the resistor 62a. As a result, the collector potential of the transistor 22 will assume a waveshape having a smooth rise and fall pattern as shown by simbol C in FIG. 6E, so that the generation of switching noises in the transistor 66a can be prevented. The waveshape shown by symbol D in FIG. 6E is identical with the waveshape of the output signal shown in FIG. 6A. Also, the arrangement and the operation of the controlling circuit 37b and the switching circuit 31 are similar to those of the abovesaid controlling circuit 37a and the switching circuit 27. Therefore, their explanation is omitted. 
     As stated above, the provision of the build-up speed detecting means 43a and 43b permits the performance that, in case an output or input signal is one which rises quickly, the power supply can be switched over to one having a high voltage level at a point of time sufficiently before said signal gains a certain level V b . Accordingly, the switching-over of connection to power supply can be made just in time before generation of switching noises even when this switching is done relatively slowly with a certain time constant. It sould be noted here that the comparator circuits 38a, 38b and 40a,40b deal with a very small current, so that they are free of noise generation. Whereas, the transistors 66a and 66b deal with a large current, and hence the switching noises become a problem. 
     As stated above, the power amplifier shown in FIG. 5 is such that the switching circuits 27 and 31 are arranged so that the collector potentials of the transistors 22 and 24 will vary smoothly, to prevent the generation of switching noises in the transistors 66a and 66b. The reason that the amplifier can be arranged as stated above is because that the amplifier includes the abovesaid detecting means 43a and 43b, whereby controlling signals S 1  and S 2  can be outputted at a point of time earlier than the timing in the instance of detection of merely a signal level alone, and because thereby a sufficient margin of time is allowed for the timing of switching between the power supplies. 
     Description will next be made of another concrete embodiment shown in FIG. 7. The power amplifier illustrated is arranged so that both the positive and negative power supplies can be switched over simultaneously by the use of an absolute value circuit 44. This absolute circuit 44 is a known full-wave rectifying circuit comprised of a phase-inverting amplifier 70, resistors 71 and 72 and diodes 73 and 74. Also, the controlling circuit 37 is arranged by members such as diodes 75 and 76, transistors 77-79 and a capacitor 80. In this circuitry, the diodes 75 and 76 form an OR circuit. The output of this OR circuit is amplified by the transistors 77-79, and then applied, as controlling signals S 1  and S 2 , to the respective bases of switching transistors 81 and 82, so that these transistors 81 and 82 can be controlled simultaneously by an output signal regardless of whether this is a positive or a negative signal. The capacitor 80 is intended to hold the controlling signals S 1  and S 2  for a certain period of time in much the same way as by the capacitors 52a and 52b in FIG. 5. 
     In the power amplifier circuitries shown in FIGS. 2, 5 and 7, the detection of the level and the rise time input or output signal are carried out invariably by an output signal derived at the output terminal 35. Such detection may be performed, with similar effects, by an input signal derived at the input terminal 20.