Abstract:
A DC/DC converter circuit to be used in the field of MPPT for solar inverters, for step-up DC/DC conversion for high output voltages, and for chargers in electrical vehicles. The circuit comprises a first DC terminal and a second DC terminal, a first DC voltage being defined there between. It further comprises a positive split DC terminal and a midpoint terminal, a positive split DC voltage being defined there between. A negative split DC terminal is provided, a negative split DC voltage being defined between said negative split DC terminal and said midpoint terminal. A first switch and a second switch are provided, and a converter inductance is storing electric energy therein. A first diode is connected between a first terminal of said first switch and said positive split DC terminal, and a second diode is coupled between an internal midpoint and said midpoint terminal.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention generally relates to converter circuits and, in particular, to a DC/DC converter circuit which can be used, for instance, in the field of maximum power point tracking, MPPT, for solar inverters, for step-up DC/DC converters with output voltages of more than 500 V, and for chargers in electrical vehicles. 
         [0002]    In particular for solar cells, boosting converters are needed for boosting the voltage generated by the solar cells to an output voltage of, for instance, 700 V to 1000 V. In order to further provide a safety margin, the components for switching these voltages usually have to be produced with a voltage rating of about 900 V up to 1200 V. These components, however, are expensive and/or have severe limitations in their performance. 
         [0003]    Presently, several topologies are used for performing the DC/DC boost conversion in the field of solar modules. Examples for recently developed inverter topologies can be found in the following documents by Michael Frisch and Ernö Temesi, all available from http://www.vincotech.com/en/products/power/documents.php:
   “Advantages of NPC Inverter Topologies with Power Modules”, July 2009.   “Design Concept for a Transformerless Solar Inverter”, December 2009.   “Symmetrical Boost Concept for Solar Applications up to 1000V”, January 2009.   
 
         [0007]    When employing such a conventional boost circuit, it is firstly known to use 900 V rated CoolMOS™ transistors as the required power switches. The advantage of these components can be seen in the fact that their switching losses are comparatively low. However, the voltage may not exceed said 900 V rated value. A further disadvantage of CoolMOS™ switches can be seen in the fact that they have comparatively high static losses and, moreover, are rather expensive. 
         [0008]    On the other hand, when higher voltages have to be generated, conventional boost circuits also use insulted gate bipolar transistors, IGBT, as switches. These transistors have the advantage that they exhibit rather low static losses, but, on the other hand, have the drawback of high switching losses. 
         [0009]    Finally, it is further known to use silicon carbide junction field-effect transistors, SiC J-FET, or silicon carbide metal oxide field-effect transistors, SiC MOSFET, with a rated voltage of 1200 V. This arrangement offers the best performance, low switching losses and a high voltage rating, but has the severe drawback of being very expensive. 
       SUMMARY OF THE INVENTION 
       [0010]    The object underlying the present invention is to provide a DC/DC converter circuit which firstly can be operated to convert from or into high voltages as they occur in connection with solar cells, and secondly is highly efficient and involves low component costs. 
         [0011]    This object is solved by the subject matter of the independent claims. Advantageous embodiments of the present invention are the subject matter of the dependent claims. 
         [0012]    The present innovation is based on the idea that a DC/DC converter circuit has two switches which are connected between a positive and a negative split voltage and are connected to each other at an internal midpoint node. This internal midpoint node according to the present invention is connected via a diode to the midpoint terminal between the positive and the negative split voltage. A converter inductance is provided for storing electric energy therein. 
         [0013]    At the beginning of each switching cycle, both switches are switched on, so that current is flowing through both switches and the converter inductance. According to the present invention, one of the two switches is switched off earlier than the second one and the current flows through said diode to the midpoint terminal. After a predefined time period, for instance, 100 nanoseconds, the second switch is also turned off, so that now the current flows through a further diode to the output and the diode which is provided between the internal midpoint and the midpoint terminal clamps the voltage towards ground. Consequently, the two switches have a balanced share of the output voltage. 
         [0014]    The circuit is most efficient with split DC potentials as this is, for instance, the case for neutral point clamped, NPC, inverter designs. Here, the symmetry of the split voltage can be managed by the output circuit. The advantage of the present invention can be seen in the fact that the switches have to be rated only for half the voltage which the converter circuit outputs or receives. Thus, components such as MOSFETs or punch-through insulated gate bipolar transistors, PT-IGBT, can be employed for highly efficient parallel switching, which are available in a larger variety with a voltage rating of 600 V, but not as 1200 V components. 
         [0015]    Highly efficient topologies such as the ones described in the Article Frisch, M., Temesi, E.: “High Efficient Topologies for Next Generation Solar Inverter”, Bodo&#39;s Power Electronics in Motion and Conversion, August 2008, which up to now needed expensive components such as silicon carbide MOSFETS or J-FETS, may now be realised with standard silicon MOSFETS or IGBTs when applying the principles of the present invention. Furthermore, high voltage boosters with an output voltage of up to 2000 V may be realised with components that are only rated for up to 1200 V. 
         [0016]    A further advantage of the inventive DC/DC converter topology can be seen in the fact that it may be used for positive and negative booster circuits, and also for positive and negative buck circuits for down converting applications. 
         [0017]    According to an advantageous embodiment, the idea of assigning a balanced share of the total voltage to each of two serially connected switches can also be employed for driving a bipolar junction transistor, BJT, or an emitter switched bipolar transistor, ESBT, coupled between the positive and negative split voltage terminals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    For a better understanding of the present invention, same will be explained in the following based on the embodiments shown in the Figures. Corresponding parts are given corresponding reference numerals and terms. Furthermore, those features or combinations of features which show or describe different embodiments may form separate inventive solutions in themselves. The invention will now be described by way of example with reference to the drawings, wherein: 
           [0019]      FIG. 1  is a circuit diagram of a DC/DC converter circuit configured as a positive voltage boosting converter; 
           [0020]      FIG. 2  is a timing diagram of the control voltages for the switches in  FIG. 1 ; 
           [0021]      FIG. 3  is a timing diagram of the voltages across the two switches and the input voltage; 
           [0022]      FIG. 4  is a timing diagram of the currents for the switches and through the diode of  FIG. 1 , respectively; 
           [0023]      FIG. 5  is a schematic diagram of a DC/DC converter circuit according to a first topology; 
           [0024]      FIG. 6  is a schematic circuit diagram of a DC/DC converter circuit according to a second topology; 
           [0025]      FIG. 7  is a schematic diagram of a buck converter circuit according to a first topology; 
           [0026]      FIG. 8  is a circuit diagram of buck converter circuit according to a second topology; 
           [0027]      FIG. 9  is a circuit diagram of a positive booster using a bipolar junction transistor, BJT; 
           [0028]      FIG. 10  is circuit diagram of a positive booster using an emitter switched bipolar transistor, ESBT; 
           [0029]      FIG. 11  is a circuit diagram of a negative booster using a bipolar junction transistor, BJT. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    In  FIG. 1 , a DC/DC converter according to a first embodiment of the present invention is depicted. Generally, this DC/DC converter  100  is an element of a power conversion apparatus that converts DC power into AC power, for instance, in connection with solar systems. Conventionally, in such an inverter circuit the voltage from the power source, for instance, a solar battery, is boosted by using a DC/DC converter, and a pulse width modulation, PWM, controlled inverter is connected thereto at a subsequent stage, thus generating an output AC voltage which can, for instance, be fed into the power grid. 
         [0031]    In particular, the DC power output from a solar battery drives an internal control power source of the power conditioner and thus enables an internal circuit to operate. The internal circuit comprises a booster circuit and an inverter unit. The booster circuit, often also called chopper circuit, boosts the voltage of the solar cell to a voltage that is required for linking to the system. 
         [0032]    The inverter unit includes, for instance, four switches and carries out PWM switching to form an output current having a phase synchronous with the system or grid voltage. A strip-like wave form is output in this manner and the time ratio for output is changed to control the average voltage of the output. The output voltage is further averaged by a smoothing filter provided on the output side and the AC power is output to the system, for instance, a national grid. 
         [0033]      FIG. 1  shows a DC/DC converter circuit  100  which is particularly suitable for neutral point clamped, NPC, topologies. An overview of such NPC topologies can be derived, for instance, from Rodriguez et al.: “Multi Level Inverters: “A Survey of Topologies, Controls, and Applications”, IEEE Transactions on Industrial Electronics, Vol. 49, No. 4, August 2002. 
         [0034]    The DC/DC converter circuit  100  has first and second DC terminals  102 ,  104  which are connected to the output of a solar cell. A boosting inductor L 0  is connected with the first DC terminal  102  and further connected to a first terminal of a first switch MOS 3 . The first terminal of the first switch MOS 3  is connected via a first diode SiC 3  to a positive split DC voltage output DC_plus. The first diode SiC 3  is connected to the first switch MOS 3  in a way that its anode is connected to the switch and its cathode is connected to the terminal DC_plus. 
         [0035]    The second terminal of the first switch MOS 3  is connected to an internal midpoint node  106  to which the first terminal of a second switch MOS 4  is also connected. The second switch MOS 4  is further connected to the negative split DC terminal DC_return. 
         [0036]    A midpoint terminal DC_split which can be connected to neutral potential is provided between two capacitors C 1  and C 2  which are coupled between the positive and negative split DC terminals DC_plus and DC_return, respectively. 
         [0037]    According to the present invention, this midpoint terminal DC_split is connected via a second diode to the internal midpoint node  106 . In the circuit shown in  FIG. 1 , the second diode SiC 4  is connected with its anode to the internal midpoint node  106  and with its cathode to the midpoint terminal DC split. Optionally, a bypass diode may be provided between the positive DC split terminal DC_plus and the DC input terminal  102 . In the shown configuration, the first diode SiC 3  is a silicon carbide diode which is rated for 1200 V. The second diode SiC 4  is also a silicon carbide diode which is however rated only for 600 V. The two switches MOS 3  and MOS 4  are two MOSFETS each rated for 600 V. 
         [0038]    At the beginning of each switching cycle, the two switches MOS 3  and MOS 4  are either switched on simultaneously or with a certain time delay, switching on the second switch MOS 4  later than the first switch MOS 3 . When both switches are conductive, current flows through the boost inductor L 0  and the two switches MOS 3  and MOS 4 . According to the present invention, the second switch MOS 4  is switched off, while the first switch MOS 3  is still conducting. Then, the current flows via the second diode SiC 4  to the midpoint terminal which can be connected to neutral (ground). After a predetermined time delay of, for instance, 100 nanoseconds, the first switch MOS 3  is also switched off and the current will then flow through the first diode SiC 3  to the positive split DC terminal DC_plus. 
         [0039]    According to the present invention, the diode between the internal midpoint node  106  and the midpoint terminal DC_split, SiC 4 , clamps the voltage to ground, so that the first and second switches MOS 3 , MOS 4  have a balanced share of the output voltage. 
         [0040]    Consequently, an output voltage of 800 V can be provided by using components which are rated only for half of this voltage. 
         [0041]      FIG. 2  shows the control signals Vg for the first and second switches MOS 3 , MOS 4  as a function of the time. In the embodiment shown in  FIG. 2 , the two switches are controlled to be switched on with a time delay. However, also a simultaneous switching would be feasible for turning on the switches. As shown in  FIG. 2 , the first switch MOS 3  is turned on before the second switch MOS 4  is turned on. This time delay may, for instance, amount to 100 nanoseconds, but can also have any other suitable value. After a predetermined time, the second switch MOS 4  is switched off while the first switch MOS 3  is still controlled to be conductive. MOS 3  is switched off after a time delay of, for instance, 100 nanoseconds. These control signals Vg of course do not have to be symmetric as shown in  FIG. 2 , but can also have different values for the two time delays between switching on the two switches and switching same off. 
         [0042]      FIG. 3  shows the resulting voltages across the two switches and between the positive split DC terminal DC_plus and the midpoint terminal DC_split, referred to as V(MOS 3 ), V(MOS 4 ), and Vout, respectively. 
         [0043]    As can be seen in  FIG. 3 , both switches MOS 3  and MOS 4  are only stressed by the voltage of 400 V whereas the output Vout voltage of the boost converter reaches 800 V. Thus, the switches MOS 3  and MOS 4  have only to be rated to allow, for instance, 600 V. 
         [0044]      FIG. 4  shows the currents flowing through the two switches MOS 3  and MOS 4  and through the two diodes SiC 3  and SiC 4 . As may be derived from this figure, the diodes carry the current only during short intervals during the time shifted switching process. 
         [0045]    As will be explained with reference to  FIGS. 5 to 8 , the basic principles of the circuit shown in  FIG. 1  and basically represented also in  FIG. 5 , can be used not only for the positive boosting circuit of  FIGS. 1 and 5 , but also for a negative boosting circuit (shown in  FIG. 6 ) and down converting buck converters (shown in  FIGS. 7 and 8 ). 
         [0046]    When directly comparing the positive boosting circuit of  FIG. 5  to the negative boosting circuit of  FIG. 6 , the boost inductor L 0  is placed between the second terminal of the second switch and the second DC terminal  104 . As the output voltage is a negative voltage, the second diode SiC 4  has to be arranged with its cathode connected to the internal midpoint node  106 . The first diode is arranged between the negative DC split terminal DC_return and the second terminal of the second switch MOS 4 . The control timing of the switches is performed analogously to the timing sequences explained above with respect to  FIGS. 2 to 4 . 
         [0047]    The inventive idea of a diode between the midpoint terminal DC split and an internal midpoint node  106  between the two switches MOS 3  and MOS 4  may also be applied for designing a buck converter, as well for a positive buck converter as for a negative buck converter. These two topologies are depicted in  FIGS. 7 and 8 . 
         [0048]    In comparison to  FIGS. 5 and 6 , input and output terminals are interchanged. Also in these embodiments, by providing a diode SiC 4  between the internal midpoint node  106  and the DC split neutral terminal, and by switching the two switches MOS 3  and MOS 4  in a delayed manner with respect to each other, it is feasible to convert high voltages down to lower output voltages by using switches that need to be voltage rated only for half the input voltage value. 
         [0049]    The converter inductance L 0  here is located at the output DC terminals  102 ,  104  as this is generally characteristic of a buck converter. 
         [0050]    The inventive circuit is able to provide boost or buck DC converters which are able to convert between high voltage differences and on the other hand, can be designed with standard cost effective semiconductor components. 
         [0051]    An advantageous application of the principle of assigning a balanced voltage share to two serially connected switches will be explained with reference to  FIGS. 9 to 11 . Here, the circuit as described before is used for driving a bipolar junction transistor, BJT, or an emitter switched bipolar transistor, ESBT,  108  connected between the positive and negative split voltage terminals DC_plus and DC_return, respectively. 
         [0052]    As this is generally known, the Emitter-Switching Bipolar Transistor, ESBT, is a combination of a NPN bipolar transistor, BJT, and a MOSFET. The BJT has an enhanced voltage blocking characteristic. The fast switching low voltage n-channel power MOSFET is realized inside the emitter of the BJT. An equivalent circuit is shown in  FIG. 10 . In order to drive the BJT and MOSFET independently, two separate terminals, gate and base, are required. Thus four terminals are necessary for the cascaded structure. The driving according to the present invention is performed by two MOSFETs connected in series, wherein their internal midpoint node  106  is coupled via a diode SiC 4  to the midpoint terminal DC_split. 
         [0053]    According to the present invention, the two MOSFETs MOS 3  and MOS 4  need to be voltage rated only for half the value that is needed for driving the BJT or ESBT  108 . 
         [0054]      FIGS. 9 and 10  show the arrangement of a positive booster using a BJT or ESBT  108 , respectively, whereas  FIG. 11  represents a negative booster topology. In this case, for switching off the BJT or ESBT  108  a third MOSFET MOS 5  having a smaller block voltage is provided. The block voltage may for instance be 50 V. 
         [0055]    The switching sequence of the circuit shown in  FIG. 11  for switching on the BJT or ESBT  108  may for instance be as follows: 
         [0056]    turn off the switch off transistor MOS 5 ; 
         [0057]    turn on the second switch MOS 4 , thus switching on the BJT or ESBT  108 ; 
         [0058]    turn on the first switch MOS 3 . 
         [0059]    On the other hand, when turning off the BJT or ESBT  108 , the following steps have to be performed:
       firstly, the switch off transistor MOS 5  is turned on, thus the BJT or ESBT  108  starts turning off, and the three MOSFETS take over the current;   in a second step, the first MOSFET MOS 3  is turned off;   finally, the second switch MOS 4  is turned off.       
 
         [0063]    The use of the ESBT generally offers the advantages that storage and switch off times are much shorter than those of traditional BJT, that the tail current characteristic of IGBT is not present, that there is no second breakthrough, which enhances the robustness, and that the safe operating area is much larger. With known driver circuits, high voltage MOSFETs are employed for driving the ESBT. According to the present invention, two serially connected MOSFETs having only half the rated voltage can be used by assigning a balanced share of the total voltage to each of them.