Abstract:
A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit. Further, current consumption of a fuse latch circuit of the present invention is reduced by adopting NMOS transistors to which a lower voltage level may be applied.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a fuse latch for a memory circuit, and more particularly to multiplexer employed within the fuse latch having a reduced size and reduced current consumption.  
         BACKGROUND OF THE INVENTION  
         [0002]    In manufacturing high volume, low margin products, like memory chips, manufacturing cost and performance of the products are important factors to be considered. There have been efforts in the manufacturing industry of memory chips to reduce the manufacturing cost of memory chips, while maintaining or improving their performance. One of the factors determining the manufacturing cost is a size of a memory chip, that is, typically, the smaller a size of a memory chip, the lower the manufacturing cost of the memory chip.  
           [0003]    One of the components having an effect on a size of a memory chip is fuse latches in the memory chip. Generally, a memory chip has a significant number of fuse latches. For example, there are about 30,000 fuse latches in a typical memory chip of 1G-bit SDRAM (synchronous dynamic random access memory). Thus, a size of the fuse latch is one factor in determining the size of a memory chip.  
           [0004]    Referring to FIG. 1, a conventional fuse latch is illustrated for a memory circuit. A conventional fuse latch has a complementary metal oxide semiconductor (CMOS) multiplexer  10  receiving input address data ADD and ADD′ and a latch control signal CONT. The input address data ADD and ADD′ have a certain level (i.e., CMOS level) of voltage, and the latch control signal CONT is dependent on a status of a fuse (not shown) of the fuse latch. The CMOS multiplexer  10  includes, for example, a first CMOS transistor  12  and a second CMOS transistor  14 . The CMOS multiplexer  10  also has a latch input terminal  16  through which the control signal CONT is provided to the first and second CMOS transistors  12  and  14 , and a latch output terminal  18  for generating a multiplexed signal to a decoder  19 . The first CMOS transistor  12  receives true address data ADD and the second CMOS transistor  14  receives complement address data ADD′. The control signal CONT is provided to the first CMOS transistor  12  through an inverter  17  and to the second CMOS transistor  14  to enable/disable the first and second CMOS transistors  12  and  14  depending on the status of the fuse. The CMOS multiplexer  10  multiplexes the true and the complement  address data ADD and ADD′ in response to the control signal CONT. In other words, depending on whether the fuse has been blown or is intact, either true address data ADD or complement address data ADD′ propagates through the CMOS multiplexer  10  to the decoder  19 .    
           [0005]    Referring to FIG. 2, a cross-sectional view of a typical CMOS transistor used in a conventional fuse latch in FIG. 1 is illustrated. A typical CMOS transistor  20  has a serial combination of a p-channel transistor  22  and an n-channel transistor  24 . A typical CMOS transistor  20  uses a dopant which is diffused into the surface of substrate  26  to form, for example, an n-well  28  as well as drain and source regions of the p-channel transistor  22  and the n-channel transistor  24 . Since the diffusion of the dopant occupies some space to form the n-well  28 , the p-channel transistor  22  is larger than the n-channel transistor  24 . In a conventional fuse latch (referring to FIG. 1), the size of p-channel transistors is, for example, nearly twice the size of n-channel transistors Thus, a CMOS multiplexer including the p-channel transistors contributes to an increase in the size of a conventional fuse latch, or a memory chip.  
           [0006]    Accordingly, a need exists for a fuse latch having a reduced size, thereby reducing the size of a memory chip.  
         SUMMARY OF THE INVENTION  
         [0007]    The present invention relates to a fuse latch circuit having a reduced size and a reduced current consumption. A fuse latch of the present invention includes a plurality of address lines, an input terminal for receiving a control signal varying dependent on status of a fuse, a multiplexer having single type transistors for multiplexing the plurality of address lines in response to the control signal, and an output terminal for providing a multiplexed signal from the multiplexer to a decoder. All the transistors of the multiplexer may be either only n-channel metal oxide semiconductor (NMOS) transistors or only p-channel metal oxide semiconductor (PMOS) transistors. The decoder may be a dynamic decoder for eliminating a voltage drop due to threshold voltages of the transistors In case of NMOS transistors, the dynamic decoder may include an NMOS logic circuit having a NMOS transistor enabled in response to the multiplexed signal from the multiplexer. In case of PMOS transistors, the dynamic decoder may include a PMOS logic circuit having a PMOS transistor enabled in response to the multiplexed signal.  
           [0008]    The plurality of address lines may be applied with address signals with a voltage lower than a source voltage of the decoder. The address lines may include, for example, a first address line for providing true address data and a second address line for providing complement address data. The multiplexer may have, for example, a first transistor for receiving the true address data and a second transistor for receiving the complement address data. The first and second transistors may be enabled or disabled in response to the control signal, and share either a drain region or a source region.  
           [0009]    For eliminating the voltage drop, the fuse latch may include a voltage supply unit for providing a boost voltage to the first and the second transistors. The voltage supply unit may be connected to a wordline boost voltage supply for a wordline driver, where the fuse latch is used for a decoupling capacitance of the wordline boost voltage. The boost voltage may be equal to or higher than a source voltage provided to the decoder, preferably, is equal to a sum of the source voltage provided to the decoder and a threshold voltage of the transistors in the multiplexer. The fuse latch may further include a first inverter for inverting the control signal and a second inverter for inverting an output signal of the first inverter and for providing an inverted signal to the input terminal The first inverter may be coupled between the input terminal and the first transistor and may receive the boost voltage from the voltage supply unit. The second inverter may be coupled between the output of the first inverter and the input terminal and also receive the boost voltage from the voltage supply unit.  
           [0010]    The size of a multiplexer having single type transistors, preferably only n-channel transistors, may be substantially smaller than that of a conventional multiplexer having CMOS transistors. The multiplexer may include only NMOS transistors which also reduces the current consumption.  
           [0011]    These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein:  
         [0013]    [0013]FIG. 1 is a schematic diagram illustrating a conventional fuse latch including a CMOS multiplexer;  
         [0014]    [0014]FIG. 2 is a cross-sectional view of a typical CMOS transistor used in a conventional CMOS multiplexer;  
         [0015]    [0015]FIG. 3 is a schematic diagram of one embodiment of a fuse latch according to the present invention;  
         [0016]    [0016]FIG. 4 is a schematic diagram of another embodiment of a fuse latch according to the present invention;  
         [0017]    [0017]FIG. 5A is a cross-sectional view of an NMOS multiplexer used in the embodiment shown in FIG. 3 according to the present invention; and  
         [0018]    [0018]FIG. 5B is a cross-sectional view of a PMOS multiplexer used in the embodiment shown in FIG. 4 according to the present invention 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0019]    The present invention relates to fuse latches in memory chips. Since memory chip sizes are one factor having an effect on manufacturing cost of memory chips, it is desirable to reduce memory chip sizes. Reduction in a size of a memory chip may be accomplished by reducing a size of fuse latches in a memory chip. In a way to reduce the size of fuse latches may include reducing a size of multiplexers in the fuse latches.  
         [0020]    [0020]FIG. 3 shows one embodiment of a fuse latch according to the present invention. A fuse latch of the present invention includes an n-channel metal oxide semiconductor (NMOS) multiplexer  30  which has, for example, a first NMOS transistor  32  and a second NMOS transistor  34 . The first NMOS transistor  32  receives true address data ADD L ′, and the second NMOS transistor  34  receives complement address data ADD L ′. A latch control signal CONT is provided to the NMOS multiplexer  30  through a latch input terminal  36 . The latch control signal CONT is dependent on a status of a fuse  53 . The NMOS multiplexer  30  multiplexes the true address data ADD L  and the complement address data ADD L ′ in response to the control signal CONT, and generates a multiplexed output signal S OUT  to a decoder  39  though a latch output terminal  38 .  
         [0021]    In the NMOS multiplexer  30 , the first and the second NMOS transistors  32  and  34  are coupled to each other in parallel The first NMOS transistor  32  has a conduction path with a source receiving the true address data ADD L  and a drain connecting to the latch output terminal  38 . The first NMOS transistor  32  also has a gate connecting to the latch input terminal  36  via a first inverter  37 , and controls the true address data ADD L  provided to the conduction path in response to the inverted control signal CONT′ provided to the gate. The second NMOS transistor  34  has a conduction path with a source receiving the complement address data ADD L ′ and a drain connecting to the latch output terminal  38 , and a gate connecting to the latch input terminal  36 . The second NMOS transistor  34  controls the complement address data ADD L ′ provided to the conduction path in response to the control signal CONT provided to the gate. Thus, the first and the second NMOS transistors  32  and  34  multiplex the true address data ADD L  and the complement address data ADD L ′ in response to the control signal CONT.  
         [0022]    During a fuse latch initialization phase, the control signal CONT is determined depending on a condition (i.e., blown or unblown) of the fuse  53 . The latch input terminal  36  is precharged by enabling a PMOS transistor  51  while disabling a third NMOS transistor  52 . The PMOS transistor  51  is then disabled, and the third NMOS transistor  52  is periodically turned on. Thus, the control signal CONT is discharged (i.e., ground) when the fuse  53  is not blown, and maintains ‘high’ if the fuse  53  is blown. A second inverter  50  keeps the state of the control signal CONT as it is.  
         [0023]    Referring to FIG. 3, when the fuse  53  is not blown, the control signal CONT discharging ‘low’ is provided to the NMOS multiplexer  30 . The first NMOS transistor  32  then receives the inverted control signal CONT′ (i.e., ‘high’ signal) via the inverter  37 , and the second NMOS transistor  34  receives the control signal CONT (i.e., ‘low’ signal). Since the second NMOS transistor  34  is turned off by applying the ‘low’ signal to the gate, the complement address data ADD L ′ is not transferred to the latch output terminal  38 . On the contrary, the first NMOS transistor  32  is turned on by applying the ‘high’ signal to the gate, so that the true address data ADD L  is transferred to the latch output terminal  38 . On the other hand, when the fuse  53  is blown so that the control signal CONT maintains ‘high’, the first and the second NMOS transistors  32  and  34  receive the inverted control signal CONT′ (i.e., ‘low’ signal) via the inverter  37  and the control signal CONT (i.e., ‘high’ signal), respectively. Thus, the second NMOS transistor  34  is turned on so that the complement address data ADD L ′ is transferred to the latch output terminal  38 , and the first NMOS transistor  32  is turned off so that the true address data ADD L  is not transferred to the latch output terminal  38 .  
         [0024]    Therefore, the NMOS multiplexer  30  multiplexes the address data ADD L  and ADDL′ in such a way that the true address data ADD L  is selected and transferred to the decoder  39  when the fuse  53  is not blown, and that the complement address data ADD L ′ is selected and transferred to the decoder  39  when the fuse  53  is blown.  
         [0025]    In case of the NMOS multiplexer  30  having only NMOS transistors, the NMOS multiplexer causes a voltage drop due to threshold voltages of the NMOS transistors. Referring to FIG. 3, in a fuse latch of the present invention, a high supply voltage V H  may be applied to boost the input nodes of the NMOS multiplexer  30 . That is, the first and second NMOS transistors  32  and  34  are coupled to the high supply voltage V H  via the first and second inverters  37  and  50 , respectively. The high supply voltage V H  is equal to or larger than a source voltage V o  applied to the decoder  39  by at least the threshold voltage of the NMOS transistors  32  and  34 , The high supply voltage V H  may be provided by a wordline boost voltage (V pp ) generator  66  outside the fuse latch connected to a wordline driver  62 . By coupling a source of the fuse latch to a node of the wordline boost voltage V pp , the fuse latch acts as a huge decoupling capacitor for minimizing a noise of the node of the wordline boost voltage V pp . Thus, there is no need of any additional decoupling capacitor for the node. The high supply voltage V H  is equal to or higher than the sum of the source voltage V o  and the threshold voltage V T  of the NMOS transistors  32  and  34 , i.e., V H =V o +V T .  
         [0026]    When the fuse latch uses a non-boosted voltage, i.e., the source voltage V o , a dynamic decoder  40  is preferably used for the decoder  39  to accept the voltage drop of the latch output terminal  38 . Referring to FIG. 3, a preferred embodiment of a dynamic decoder  40  is shown for accepting a voltage drop due to the threshold voltages of the NMOS transistors  32  and  34 . The dynamic decoder  40  precharges an output terminal  58  by turning on a PMOS transistor  54  with a precharge signal while disabling an NMOS transistor  55  with an evaluation signal. That is, at a precharge stage the dynamic decoder  40  outputs the source voltage V o . An NMOS logic circuit  56  is coupled between the evaluation NMOS transistor  55  and the output terminal  58  and receives the multiplexed output signal S OUT  from the NMOS multiplexer  30 . An example of the NMOS logic circuit  56  may be an NMOS transistor  59 . The NMOS transistor  59  has a gate receiving the multiplexed output signal S OUT  and a conduction path coupling the evaluation NMOS transistor  55  and the output terminal  58 .  
         [0027]    Since the multiplexed signal S OUT  has a voltage drop by the amount of the threshold voltage of the NMOS transistors  32  and  34 , a conventional static logic circuit (not shown) causes a leakage current if an input voltage of the logic (here, the multiplexed signal S OUT ) is smaller than a voltage applied to a source of a PMOS in the static logic circuit. However, the NMOS logic circuit  56  of the dynamic decoder  40  does not cause a leakage current as long as the evaluation NMOS transistor  55  is off. The output terminal  58  is precharged at the source voltage V o  (i.e., ‘high’), and then the evaluation NMOS transistor  55  is periodically on, allowing a determination of the state of the output according to the result of the NMOS logic  56 . As an example of the NMOS logic  56 , when the multiplexed signal S OUT  is ‘high’, the output terminal  58  generates a ‘low’ signal. When the multiplexed signal S OUT  is ‘low’, the output terminal  58  maintains ‘high’ signal (i.e., the source voltage V o ).  
         [0028]    [0028]FIG. 5A illustrates a cross-sectional view of the NMOS multiplexer  30  in FIG. 3. Since the NMOS multiplexer  30  has only NMOS transistors  32  and  34  instead of CMOS transistors, the NMOS multiplexer  30  does not need p-well dopant implantation. Thus, the NMOS multiplexer  30  has substantially smaller size than a CMOS multiplexer used in a conventional fuse latch by at least about 50% per multiplexer. In addition, the two NMOS transistors  32  and  34  of the NMOS multiplexer  30  preferably share a drain region  33 , so that the size of the NMOS multiplexer  30  may be further reduced. It is also possible that the two NMOS transistors  32  and  34  share a source region instead of the drain region  33 .  
         [0029]    The NMOS multiplexer  30  of the present invention also has lower power consumption than that of a conventional CMOS multiplexer if a lower voltage signaling is used. More specifically, the true and the complement address data ADD L  and ADD L ′ provided to the NMOS multiplexer  30  may have a lower voltage level than that of the address data ADD and ADD′ provided to a CMOS multiplexer (referring to FIG. 1) of a conventional fuse latch. Thus, the current consumption in the NMOS multiplexer  30  may be reduced by the reduction of the voltage swing of the address data ADD and ADD′. Although the lower voltage level is preferably used for the address data of the NMOS multiplexer  30  to enjoy the benefit of lower power consumption, the same voltage level as used for the address data of a CMOS multiplexer may still be used in the present invention.  
         [0030]    Referring to FIG. 4, there is provided another embodiment of a fuse latch of the present invention using a PMOS multiplexer  70  having only PMOS transistors  72  and  74 . Parts equivalent to those in FIG. 3 are represented with like reference numbers and description thereof is omitted to avoid duplication. The PMOS multiplexer  70  includes a first PMOS transistor  72  and a second PMOS transistor  74  which, unlike the NMOS multiplexer  30  in FIG. 3, receives the complement address data ADD L ′ and the true address data ADD L , respectively. The PMOS multiplexer  70  multiplexes the address data ADD L ′ and ADD L  in response to the latch control signal CONT and generates the multiplexed output signal S OUT  to the decoder  39 .  
         [0031]    For the same reasons mentioned above, the decoder  39  may be a dynamic decoder  75 . The dynamic decoder  75  includes a PMOS logic circuit  76  between an evaluation NMOS transistor  61  and a PMOS transistor  63 . The PMOS logic circuit  76  may be a PMOS transistor  78  having a gate receiving the multiplexed output signal S OUT  from the PMOS multiplexer  70  and a conduction path coupling the evaluation transistor  61  and an output terminal  79 . The output terminal  79  is initially discharged. When the evaluation transistor  61  is off, signals from the output terminal  79  follow states of the PMOS logic circuit  76 .  
         [0032]    Referring to FIG. 5B, a cross-sectional view of the PMOS multiplexer  70  in FIG. 4 is shown. Compared with a CMOS multiplexer used in a conventional fuse latch, the PMOS multiplexer  70  has substantially smaller size because the first and the second PMOS transistors  72  and  74  share a drain region  73 . Although not shown, the two PMOS transistors may also share a source region instead of the drain region  73 .  
         [0033]    Therefore, the reduction of a memory chip size may be accomplished by using a fuse latch of the present invention of which size is reduced by adopting the NMOS multiplexer or the PMOS multiplexer instead of a conventional CMOS multiplexer by as large as 50% per multiplexer. Current consumption of driving address in a memory chip is also reduced by using a fuse latch of the present invention to which the address data with a lower voltage signaling of the address data ADD and ADD′ is applied. Optionally, the gates of the NMOS transistors of the NMOS multiplexer are boosted by the threshold voltage to avoid a voltage drop.  
         [0034]    It is understood that various other modifications can be readily made by those skilled in the art without departing from the scope and spirit of the present invention. For example, although having been described in terms of an NMOS multiplexer  30  having two NMOS transistors  32  and  34 , the present invention is applicable to an NMOS multiplexer having more than two NMOS transistors, and also applicable to a PMOS multiplexer having more than two PMOS transistors.  
         [0035]    Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the present invention can be practiced in a manner other than as specifically described herein.