Abstract:
The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention&#39;s use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

Description:
FIELD OF THE INVENTION 
   The present invention relates to clock delay adjustment circuitry. In particular, the present invention relates to the generation of a uniformly distributed multiphase clock. 
   BACKGROUND OF THE INVENTION 
   Various signal processing applications require the use of a multiphase clock in which clock signals are uniformly distributed in phase.  FIG. 1  illustrates an example of the use of such a clock in a Clock Data Recovery (CDR) circuit. Contained in the overall CDR circuitry are essentially two loops, a first loop  130  in which phase locking to data occurs and a second loop  140  in which a multiphase clock is used to provide proper alignment of clock phases between 0° and 360°. 
   As depicted in  FIG. 1 , a reference clock signal  110  is supplied to a Voltage Controlled Delay Loop (VCDL) component  120 . An internally available clock, derived from the reference clock  110 , is used by a data sampling component  160  to oversample incoming data  150 . Based on the results of this oversampled data, the internal clock is delayed so that it provides data sampling adjusted to the center of the “eye” pattern of the received serial data  150 .  FIG. 2  illustrates an example of sampling of a received digital data signal wherein S 0  and S 1  depict sampling times corresponding to the center of the eye pattern. Times T 0  and T 1 , are transition points which are used by the system to determine these proper sampling times. In a VCDL system, phase of the sampling clock is constantly adjusted to keep up with phase deviations of incoming data. 
   One well-known problem in the prior art is the timing variations that occur within the second loop  140  itself that must be properly resolved before accurate data sampling is attained. There exist two components of these timing variations: 
   1. Static Variations:
         Static variations are due to static phase offsets resulting from clock edge placement errors. These errors are caused by fixed error sources such as (a) semiconductor device fabrication variations, (b) circuit mismatches and (c) layout asymmetries.       

   2. Dynamic Variations:
         The dynamic variations are due to deterministic jitter, random jitter, or periodic jitter.       

   Static variations are due to physical mismatches. Such variations are a significant source of timing errors that are conventionally addressed with a calibration process. The position of the clock edges are measured with averaged phase timing measurements using histogram counters. The resulting histogram of these count values indicates the variation of the clock phases. The mitigation of these variations, or clock phase trimming, is performed by equalizing the histogram count values. In particular, this mitigation is typically performed by tuning adjustable tail currents within the clock buffers. 
   One example of such a histogram technique is described in a November 2001 Stanford dissertation thesis entitled “PRECISION CMOS RECEIVERS FOR VLSI TESTING APPLICATIONS” by Daniel K. Weinlader, said thesis hereby incorporated by reference in its entirety. In Weinlader&#39;s process, as in other conventional techniques, the trimming process has to be performed in real time and accordingly, the following components are typically required:
         (a) a controlled ppm (part per million) generator,   (b) a high speed phase comparator,   (c) a high speed counter and   (d) complex histogram processor.
 
As a result, this solution is expensive and can not be practically implemented in many commercial products.
       

   SUMMARY OF THE INVENTION 
   The present invention relates to the generation of a statically controlled clock source for use in trimming VCDL delay line output clocks. This controlled clock source replaces the need for an expensive ppm generator as required with previous trimming methods. Further, the static nature of the clock source eliminates the previous requirement of having to perform this trimming process in real time. 
   The present invention uses a clock source whose phase is adjusted in a controlled fashion. One embodiment of the present invention uses an array of flip-flops (FF), one FF for each phase of the multiphase clock to be trimmed. In particular, each of the phases is supplied to the CK input of one of these FFs. The controlled clock is supplied to the D input of each FF. The phase of the controlled clock source can be moved earlier or later in a controlled manner using an interpolator. In this manner the invention creates a static input that can be varied. 
   The phase of the controlled clock source is varied until it crosses one of the CLK phases of the multiphase clock generator. The phase of the controlled clock source at this instant is recorded. This process occurs for each of the other phases of the multiphase clock generator. Adjustments are then performed to evenly distribute the phases of the multiphase clock. 
   Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description which follows below. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Various embodiments of the present invention will now be described in detail in conjunction with the annexed drawings, in which: 
       FIG. 1  is a block diagram of a CDR circuit; 
       FIG. 2  depicts sampling times corresponding to the center of the eye pattern of a received serial data signal; 
       FIG. 3  is a block diagram illustrating an embodiment of the invention having two major components, a controlled clock source and a multiphase clock generator; 
       FIGS. 4A  is a block diagram &amp;  4 B is a timing diagram illustrating a further embodiment of the invention by which a series of FFs are combined with a controlled clock signal to perform clock trimming of the multiphase clock generator; and, 
       FIG. 5  illustrates an exemplary multiphase clock whose four phases have been measured relative to the controlled clock signal by an embodiment of the invention. 
   

   DETAILED DESCRIPTION 
     FIG. 3  illustrates a simple example of a multiphase clock generator in which 16 phases are generated: TE 0 , T 0 , TL 0 , S 0 , . . . TL 3  and S 3 . The present invention performs adjustments for static variations that occur in this generator process so that the phases of the resulting clocks are evenly distributed. That is, each Delay i  is essentially equal. This adjustment process shall be referred to throughout this application as clock trimming. 
     FIG. 3  illustrates an embodiment of the invention in which a Reference CLK signal  410  is supplied to both a controlled multicycle clock source component  420  and a multiphase clock generator  430 . The controlled clock source  420  component comprises a series of delay elements (D 0 , D 1 , D 2  and D 3 ). Each of these delay elements yields a 90° phase shift. The Reference CLK signal  410 , as well as the outputs of the delay elements, is connected to a variable interpolator  415  which, as is well-known in the industry, results in creating smaller incremental phase shifts. In an embodiment of the invention, 64 such incremental shifts are provided by the variable interpolator for each 90° quadrant, yielding a total of 256 phase shifts. Each of these potential phase shifts is assigned an interpolation code of the form Quadrant (Q 0 -Q 3 )/Interpolator Number ( 0 - 63 ), corresponding to the delay element and incremental shift involved. One of these 256 clock signals is determined and outputted from the controlled clock source  420  on line  425 . 
   As illustrated in  FIG. 3 , the multiphase clock generator contains a multiplexer  460  and a delay element  470  associated with each of the clock phases that are generated. The injection point of the reference clock signal  410  is supplied through  440  to the appropriate multiplexer, as is well known in the art. 
   A feature of the present invention is the use of a FF arrangement to evenly distribute the clock phases.  FIGS. 4A &amp; 4B  illustrate this principle where each phase of the multiphase clock  430  is supplied to the CK input of a FF ( 510 ,  520 ,  530  . . . ). The D input to each FF is supplied from the controlled clock source  420 . In a situation where the controlled clock phase lags behind the multiphase clock supplied to a particular FF, the latch will register 0 when the clock signal triggers that FF. By supplying that FF with a series of controlled clock timing signals, each advancing slightly in phase, at some point the output of that FF will change from a 0 to a 1. At this point the controlled clock source is in phase with the particular phase of the multiphase clock supplied to that FF. 
   By way of example, T 0  is depicted as being connected to the CK input of FF  510 . As illustrated in  FIG. 4B , the phase of T 0  is such that its rising edge occurs at t 2 . In this illustrated example, the rising edge of the controlled clock signal initially occurs at t 1 . In the process of trimming multiphase clock  430 , incrementally advancing controlled clock source outputs are supplied to the D input of FF  510 . When the output of the FF changes from a 0 to a 1 at time t 2 , T 0  is in phase with the controlled clock signal  420 . The interpolation code of the controlled clock associated with time t 2  is then recorded for T 0 . In this manner the phase shift of T 0  relative to the reference clock  410  is quantified by the interpolation code at t 2  (i.e. the delay elements employed and the incremental delay used in generating the controlled clock signal at t 2 ). 
   In an alternative situation the phase of clock signal may initially lag behind the controlled clock signal  420  at time t 1 . This is illustrated as signal T 0 ′ in  FIG. 4B . In this example FF  510  would output a 1 at time t 1  due to the phase of T 0 ′ relative to the controlled clock signal  420 . In this situation, the phase of the controlled clock would be incrementally moved in the direction of t 3 , at which time the output of FF  530  would change from a 1 to a 0. As before, the interpolation code of the controlled clock signal  420  at time t 3  would be recorded. 
   In this manner the phase of each of the 16 generated sample clocks of the multiphase clock generator  430  is determined relative to the controlled clock signal and the corresponding interpolation codes are noted. Once an interpolation code has been assigned for each of the phases of the multiphase clock, the delays associated with these phases are then adjusted in an effort to make them evenly distributed.  FIG. 5  illustrates an example in which only four phases are illustrated to simplify the following explanation. As depicted, phase clocks T 0 , T 1 , T 2  and T 3  were evaluated using the procedure depicted in  FIGS. 4A &amp; 4B , yielding interpolation codes Q 0 / 13 , Q 1 / 20 , Q 2 / 10  and Q 3 / 13 , respectively. Each of the sampling clocks contains a buffer (e.g., B 1  and B 2 ; such buffers having previously been illustrated as item  540  in  FIG. 4A ). These buffers are now adjusted in an effort to set each of these clock phases an equal distance apart (i.e., 90° in this example having 4 clock phases). 
   Various algorithms are contemplated by the invention to perform this buffer trimming. In one embodiment, one clock phase may be held fixed and the others adjusted to it. Using the specific numbers of the example above, this may be implemented by T 0  being fixed. As T 1  was determined to be greater than 90° (Q 1 / 13  would be exactly 90°), the delay associated with T 1 &#39;s buffer B 1  needs to be decreased. This adjustment to buffer B 1  is done in an effort to have the next iteration of the FF procedure result in the T 1 &#39;s interpolation code being “reduced” to Q 1 / 13 ). Correspondingly, the delay of buffer B 2  (corresponding to clock T 2 ) would be increased. As T 3 &#39;s phase already has a 90° separation from T 0 , no adjustments are required to its buffer. Various mechanisms for adjusting buffer delays are well known in the art (e.g., changing buffer gain factors and/or adjusting threshold values). 
   In a further embodiment of the invention, once the buffer adjustments are performed, the procedure is repeated. Further adjustments are then performed if warranted. Iterations are performed in this manner until the multiphase clock generator&#39;s phases are trimmed so that they are equally spaced apart. Additional embodiments of this procedure may terminate the iterative procedure when required tolerances are met (e.g. 5 ps) and/or the minimum phase step adjustment yields no further improvement. 
   As noted above, alternative embodiments of the invention permit alternative trimming algorithms once the interpolation codes have been determined. An additional example would be one in which a “numerical average” of interpolation codes is derived and each phase clock is adjusted in an effort to attain that average value. This algorithm first sets one of the determined codes as a base or 0 value, determines code values for the remaining phases relative to that base value, and then computes and uses the average value to perform the trimming adjustments. Again using the numerical interpolation codes of  FIG. 5  as an example, letting T 0  be the base value, T 1  would then correspond to +7, T 2  would be a −3, and T 3  would be a 0. The numerical average of these values would yield 4/4 or 1. Each of the phase clock buffers would be adjusted accordingly. That is, buffers for T 0  and T 3  would be increased slightly (in an effort to attain a +1 interpolation code change in the next iteration). Similarly, clock phase T 1  would need to be decreased by 6 and clock phase T 2  would need to be increased by 4 (to be properly adjusted relative to reference T 0 &#39;s “new Q 0 / 14 ” interpolator code). It is clear that in this algorithm, the use of an average has the advantage in that the maximum trimming required for any one phase clock is reduced. 
   It should be noted that in alternative embodiments of the invention, the trimming process can be performed by adjustments to the delay element  470  associated with the clock phase rather than to buffer  540 . In still further embodiments, adjustments to both the appropriate buffer  540  and the delay element  470  are made in performing the trimming process. 
   As noted above, one embodiment of the invention mitigates static timing variations (e.g. those caused by semiconductor device fabrication variations, circuit mismatches and layout asymmetries). Accordingly, phase trimming adjustments to compensate for these variations need not occur continuously. By way of example, the invention&#39;s trimming process may be performed at the time the multiphase clock generator is powered up. Additionally, such trimming may occur as a periodically scheduled event. 
   While the invention has been described with reference to the preferred embodiment thereof, it will be appreciated by those of ordinary skill in the art that modifications can be made to the structure and elements of the invention without departing from the spirit and scope of the invention as a whole. In particular, it should be noted that while the invention has been described above with respect to a VCDL circuit, it is applicable to the trimming of any multiple clock device having phase separations and appropriate phase adjustment controls.