Abstract:
To raise the integration level of a video recorder, and to provide a uniform circuit concept suitable for all three color-television standard (PAL, NTSC, SECAM) which, in particular, requires only slight modifications for adaptation to the respective standard, signal processing is performed by fast digital circuits whose signals are stored on the recording medium not in digital form, but after digital-to-analog conversion. The composite color signal is converted into digital form by a fast analog-to-digital converter (aw) whose sampling signal (fc) has a fixed frequency (Fc) for all three color-television standards. Digital signal processing in the chroma channel is performed at a fixed subcarrier frequency (zt) for all three color-television standards which is an integral subharmonic of the sampling frequency (Fc).

Description:
BACKGROUND OF THE INVENTION 
     The invention pertains to a video recorder. In particular, the invention pertains to a video recorder using magnetic tape as the recording medium. 
     In video recorders of the three systems commonly used at present, i.e., VHS, Video 2000, and Betamax, the chroma signal, after being separated from the demodulated composite color signal, is changed to a carrier signal having a frequency lower than the standard chrominance-subcarrier frequency. The composite video signal is subjected to a frequency modulation, and the sum of the chroma signal of reduced carrier frequency and the frequency-modulated composite video signal is stored on the recording medium by means of a head system. The stored signal is read from the tape by means of the head system during playback, and is then transformed back into the composite color signal. 
     For the VHS system, the &#34;lower&#34; chrominance-subcarrier frequency is 627 kHz in the case of the PAL standard and 629 kHz in the case of the NTSC standard, the two frequencies being 40.125 and 40 times the horizontal scanning frequencies of PAL and NTSC, respectively. During playback, the coupling of these carrier frequencies with the respective horizontal scanning frequency makes it possible to compensate for variations in tape speed so precisely that in-phase regeneration of the original chrominance subcarrier frequency can be achieved. 
     Hence it is obvious that, beyond the circuits commonly used in television sets, additional circuits are necessary in video recorders. In conventional video recorders, these additional circuits are implemented predominantly with discrete components and only to a small extent with monolithic integrated circuits performing selected analog-signal-processing functions. 
     SUMMARY OF THE INVENTION 
     The general object of the invention is to raise the integration level, i.e., to increase the extent of the use of monolithic integrated circuits, using a novel uniform circuit concept suitable for all three color-television standards, viz., PAL, NTSC, and SECAM, i.e., a circuit concept which requires only slight modifications for adaptation to the respective standard. In particular, these modifications are to have only a slight effect on the over-all circuit concept, thus giving an optimum circuit concept for all three color-television standards. 
     In accordance with the invention the signal processing required in the respective video-recorder system is performed by means of fast digital circuits, but, instead of storing the output signals of these digital circuits in digital form on the magnetic tape, these signals are converted back into corresponding analog signals prior to the storage. According to the invention, a first analog-to-digital converter is therefore provided whose sampling signal has a fixed frequency for all three color-television standards. 
     Further in accordance with the invention the digital signal processing is performed in the chroma channel at a fixed subcarrier frequency for all three color-television standards which is an integral subharmonic of the sampling frequency. 
     In accordance with the invention the signal processing both during the record mode and during the playback mode is performed by digital circuits, which permits a considerably higher integration level for video recorders. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will be better understood from a reading of the following detailed description in conjunction with the drawings in which: 
     FIG. 1 is a block diagram of a general embodiment of the circuit in accordance with the invention; 
     FIG. 2 is a block diagram of an embodiment of a chroma circuit in accordance with the invention; 
     FIG. 3 is a block diagram of an embodiment of a video-signal-processing circuit in accordance with the invention; 
     FIG. 4 is a block diagram of a preferred embodiment of the digital frequency detector needed in the circuit of FIG. 3; 
     FIG. 5 is a block diagram of the additional subcircuits required in the circuit of FIG. 3 to process of SECAM signal; 
     FIG. 6 shows a block diagram and the frequency-response curve of a preferred first standard-band-pass filter; 
     FIG. 7 shows a block diagram and the frequency-response curve of a preferred signal-forming band-pass filter; 
     FIG. 8 shows a block diagram and the frequency-response curve of a preferred first interpolator; and 
     FIG. 9 is a block diagram of a preferred sine-wave generator. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows a general embodiment of the invention in a block diagram. The analog input of the fast analog-to-digital converter aw is connected via the first changeover switch ul either to the composite-color signal input fse during the record mode R or to the output of the bidirectional amplifier arrangement zv for the head system ks during the playback mode P. Of the head system ks, two heads are shown schematically. As the analog-to-digital converter aw is to be a fast one, it is preferably a so-called flash converter whose output provides a multibit, parallel digital word at the pulse-repetition frequency Fc of the sampling signal fc. The latter is generated by the sampling oscillator os, which oscillates at a fixed frequency for all three color-television standards, PAL, NTSC, and SECAM. In a preferred embodiment, this frequency is in the range from about 18 to 20 MHz, e.g., 18 MHz. 
     During the record mode R, the digital words appearing at the output of the analog-to-digital converter aw thus represent the digitized composite color signal fs&#39;. This signal is processed in three fast digital circuits db, dc, dm which communicate with each other and handle the signals at least partly in parallel. The digital circuit db processes essentially the composite video signal and separates the synchronizing signals from the video signal, so that its output provides pure digital luminance signals ls. It also separates the chroma signal cs from the composite color signal fs&#39;. The chroma signal cs is processed in the digital circuit dc in accordance with the standard. The digital circuit dm produces control signals sm for the motors of the head and tape drives and is fed with correction signals cr. The three fast digital circuits db, dc, dm, too, are clocked by the sampling signal fc of fixed frequency. 
     FIG. 1 also shows that the control unit se, which is clocked by the sampling signal fc, is connected to the controls tt of the video recorder and transfers the signals or commands coming from there to the fast digital circuits db, dc, dm. 
     The outputs of the two digital circuits dc and db are connected to the first and second digital-to-analog converters dw1 and dw2, respectively, whose output signals are added by the analog adder aa to form the above-mentioned analog signal to be stored on the magnetic recording medium. In the record mode R, the output of the analog adder aa is thus connected via the second changeover switch u2 to the amplifier zv, whose gain characteristics are controllable from the digital circuit db over the line v1 depending on whether the recorder is in the record or playback mode. In the playback mode P, the input of the analog-to-digital converter aw is connected to the amplifier zv via the first changeover switch u1, and the output of the analog adder aa to the composite-color-signal output fsa via the second changeover switch u2. 
     In the representation of FIG. 1, a distinction is made between lines for transferring analog signals and lines for transferring digital signals. While the former are drawn as the usual solid lines, the latter are shown in the form of stripes representing buses which consist of at least as many parallel conductors as there are bits in the digital words to be processed. 
     FIG. 2 shows an embodiment of the chrominance-signal-processing circuit in a block diagram. for the sake of completeness and clarity, the signal path in the circuit diagram begins with the analog-to-digital converter aw, to which a signal is applied from the changeover switch u1. The circuit of FIG. 2 is used both in the record mode and in the playback mode; only individual operating parameters are switched over, not the direction of signal flow. 
     The output of the analog-to-digital converter aw is coupled to the first inputs of the first and second digital multipliers m1 and m2, whose second inputs are connected to the cosine output ca and the sine outputs sa, respectively, of the first frequency-settable and -controllable digital sine-wave generator sg1. The output of the first multiplier m1 is coupled through the first digital delay element v1, which provides a delay equal to that of the first digital 90° phase shifter h1, to the first input of the first digital adder a1, and the output of the second multiplier m1 is coupled through the first 90° phase shifter h1 to the second input of the first digital adder a1. For the VHS system, the frequency-setting input fe of the first sine-wave generator sg1 is presented in the record mode R with the first digital signal ds1, which is equal to the difference between one-quarter of the sampling frequency Fc and the respective chrominance-subcarrier frequency, and during playback P with the second digital signal ds2, which is equal to the sum of one-quarter of the sampling frequency Fc and 40 times the horizontal frequency in the case of the NTSC standard or 40.125 times the horizontal frequency in the case of the PAL and SECAM standards. Thus, depending on the television signal transmitted by one of the three color-television standards, the associated chrominance-subcarrier frequency or the horizontal frequency is entered into the first sine-wave generator sg1. This is indicated in FIG. 2 by the two registers r1, r2, which contain or calculate the digital signals ds1, ds2 and deliver them according to the standard selected, as is indicated at the input marked with the three standard designations PAL, NTSC, SECAM. The second register r2 is also presented with the horizontal synchronizing pulse ss. The different application of the digital signals ds1, ds2 to the sine-wave generators sg1, sg2 during record and playback is accomplished with the third and fourth electronic changeover switches u3, u4. 
     In the Video-2000 and Betamax systems, the digital signals ds1, ds2 must be chosen according to the frequency of the respective &#34;lower&#34; chrominance subcarrier. 
     The subcircuit consisting of the two multipliers m1, m2, the delay element v1, the 90° phase shifter h1, the adder a1, and the digital sine-wave generator sg1 represents a digital quadrature mixer which shifts the chrominance-subcarrier frequency of the composite color signal in the case of all three color-television standards to exactly one-fourth of the sampling frequency Fc. In the embodiment of FIG. 2, this sampling frequency Fc is the subcarrier frequency zt. 
     The output of the adder a1 is coupled to the input of the standard-band-pass filter nb1, whose passband is set according to the respective color-television standard. Like the two registers r1, r2, the standard-band-pass filter nb1 thus has a setting input, which is not shown in FIG. 2 for simplicity. The output of the standard-band-pass filter nb1 is connected to the first input of the third multiplier m3 through the digital decimator dz, whose sampling frequency f1 is equal to one-third of the sampling frequency Fc. The output of the third multiplier m3 is coupled to the input of the digital signal-forming band-pass filter fb, whose output is connected via the digital comb filter kf to the input of the first digital interpolator ip1, which is clocked by the clock signal fc. The switch es is closed in the record mode R, so that the digital comb filter kf is active only during the playback mode P. 
     The function of the decimator dz and the first interpolator ip1 is to enable the chroma-signal-processing subcircuits to operate not at the high sampling frequency Fc, but at a more favorable, lower clock frequency F1. As a result, sufficient time is available for these processing operations, and the amount of circuitry required for the comb filter kf is reduced considerably. 
     The output of the interpolator ip1 is coupled through the second digital standard-band-pass filter nb2 and the second digital delay element v2, whose delay is equal to that introduced by the second 90° phase shifter h2, to the first input of the fourth digital multiplier m4, and through the second standard-band-pass filter nb2 to the input of the second 90° phase shifter h2, which has its output connected to the first input of the fifth digital multiplier m5. The second inputs of the fourth and fifth multipliers m4 and m5 are connected to the cosine output ca and the sine output sa, respectively, of the second frequency-settable digital sine-wave generator sg2, while the outputs of these multipliers are fed through the second adder a2 to the input of the first digital-to-analog converter dw1. 
     The frequency-setting input fe of the second sine-wave generator sg2 is fed with the second digital word ds2 in the record mode R and with the first digital word ds1 in the playback mode P. The delay element v2, the 90° phase shifter h2, the two multipliers m4, m5, the adder a2, and the sine-wave generator sg2, like the corresponding sub-circuits v1, h1, m1, m2, a1, and sg1 behind the analog-to-digital converter aw, form a quadrature mixer. The two quadrature mixers differ in that the arrangement of the subcircuits of the first-explained mixer is a mirror image of the arrangement of the subcircuits of the second mixer, so to speak, which is an essential feature of the invention. This simplifies the overall circuit for the chroma channel considerably, because otherwise, switchable and, thus, complicated filters would be necessary. Thus, while in the second quadrature mixer with the subcircuits v2, h2, m4, m5, a2, and sg2, which is of conventional design, the two signals to be mixed, which are separated in phase by exactly 90°, are produced, then mixed with the cosine wave and the sine wave, respectively, from the sine-wave oscillator sg2, and finally added, the first quadrature mixer first mixes the input signal with the sine wave and the cosine wave, respectively, from the sine-wave oscillator and only then produces the quadrature signal from the cosine-multiplied signal. 
     Besides the frequency-setting input fe, the first sine-wave generator sg1 has the phase-control input fr, which is connected to the output of the digital phase-locked loop pr. The latter compares the digital horizontal synchronizing signal ss with the signal from the digital horizontal deflection oscillator ho. The sine-wave generator sg1 is thus comparable to an analog PLL oscillator, and its frequency stability corresponds to that of a conventional crystal oscillator. 
     The second input of the third multiplier m3 is connected to the output of the digital automatic color-control stage ac, whose signal input is connected to the output of the comb filter kf, and whose clock input is presented with the horizontal synchronizing pulses ss. 
     The color-control stage ac maintains the amplitude of the color-burst signal at a constant value to achieve optimum level control during recording and compensate for amplitude variations caused, for example, by varying tape properties during playback. It also increases and reduces the amplitude of the color-burst signal in accordance with the standard. 
     Recorders usually have two heads which are alternately in contact with the recording medium. In the color-control stage ac, the controlled variables for the two heads are then determined separately to compensate for systematic differences between the two channels. To this end, the color-control stage is presented with an additional signal (not shown) which designates the head being in tape contact. 
     The signal-forming band-pass filter fb, which operates at the reduced sampling frequency f1, establishes the exact, standard-pass-band characteristic in the chroma branch; the band-pass filter nb1 performs only a coarse preselection and is, therefore, easy to implement. 
     The comb filter kf increases the crosstalk attenuation between adjacent tracks of the recording medium during playback, using the usual line-by-line phase changes of the chroma signal during recording. Depending on the standard, the phase of the chroma signal is changed line by line in such a way that during playback, the crosstalk components just cancel each other in a suitable comb filter. In FIG. 2, these phase changes are caused during recording by suitable signals at the frequency-setting input fe of the sine-wave generator sg2, and cancelled during playback by corresponding signals at the frequency-setting input of the sine-wave generator sg1. 
     FIG. 3 shows a block diagram of an embodiment of the video-signal-processing circuit. Here, unlike in the chroma-signal-processing circuit, it is impossible to manage with a single channel for recording and playback. The first subchannel r serves for recording, R, and the second subchannel p for playback, P. The sampling signal is again the signal fc, whose fixed frequency Fc preferably lies in the range from about 18 to 20 MHz, i.e., the analog-to-digital converter aw is again located at the beginning of the signal path. In addition to controlling the multipliers m1, m2 of FIG. 2, its output signal is fed to the fifth electronic changeover switch u5, which, depending on the mode selected, R or P, routes the signal either to the subchannel r or to the subchannel p. 
     In the subchannel r, the output signal of the analog-to-digital converter aw is applied to the input of the low-pass filter tp, whose upper cutoff frequency is about 3 MHz, and whose output feeds the digital sync separator stage ha and is connected via the digital preemphasis and limiter stage pb to the input of the digital voltage-controlled oscillator vo, which serves as a frequency modulator. The digital voltage-controlled oscillator vo is fed with the third digital word ds3, which determines the oscillator&#39;s carrier frequency depending on the television standard. The output of the oscillator vo is connected to the input of the second digital-to-analog converter dw2 through the first digital high-pass filter hp1, whose lower cutoff frequency is about 1.5 MHz, and the sixth electronic changeover switch u6. 
     In the second subchannel p, the output signal of the analog-to-digital converter aw is applied through the changeover switch u5 to the second digital high-pass filter hp2, whose lower cutoff frequency is about 1.5 MHz, and whose output is coupled to the input of the second digital-to-analog converter dw2. In the special embodiment shown in FIG. 3, this coupling is accomplished as follows. The output of the frequency detector fd is connected to the input of the digital decimating low-pass filter dt, whose upper cutoff frequency is about 3 MHz, and to which the clock signal f2 with half the sampling frequency, Fc/2, is applied, so that the digital words appear at the output of this filter at this clock rate F2. The decimating low-pass filter dt is followed by the digital deemphasis and noise-reduction stage du, whose output is connected to the first input of the third adder a3 via the first input-output path of the seventh electronic changeover switch u7, and to the first input of the digital correlator k1 via the second input-output path of the changeover switch u7. The second input of the digital correlator k1 is connected to the output of the third adder a3, and its output is coupled to the output of the second input of this adder a3. The output of the changeover switch u7 is also connected to the input of the delay stage vs, which provides a delay equal to one line period of the television system. Connected to the output of the third adder a3 is the second digital interpolator ip2, which is clocked by the sampling signal fc and has its output connected via the sixth electronic changeover switch u6 to the input of the second digital-to-analog converter dw2. The control input of the changeover switch u7 is connected to the output of the dropout detector dk, whose input is energized by the output of the second high-pass filter hp2. 
     The dropout detector dk is a comparator circuit which, when the input level falls below a predetermined value, operates the changeover switch u7, so that the weak and, consequently, very noisy signal from the recording medium is replaced by the signal of the preceding scanning line from the delay stage vs. 
     Noise reduction is also accomplished by the correlator k1. In this conventional circuit, noise is suppressed by filtering in case of slight deviations of the signals of successive scanning lines, while in case of larger deviations, the filter is switched off (&#34;motion detector&#34;) to avoid disturbances caused by fast vertical image changes. 
     FIG. 4 shows a block diagram of a preferred embodiment of the frequency detector fd of FIG. 3. The input of the detector is connected to the subtrahend input s of the subtracter st and to the first signal input of the electronic multiple intermediate switch kr through the third delay element v3, producing a delay equal to that of the third digital 90° phase shifter h3, and the first digital absolute-value stage bb1. The third 90° phase shifter h3 is located between the input of the frequency detector and the input of the second digital absolute-value stage bb2, which has its output connected to the minuend input m of the subtracter st and to the second signal input of the mulitple intermediate switch kr. The control input of the latter is connected to the sign-signal output va of the subtracter st, and its two signal outputs are coupled, respectively, to the dividend input dd and the divisor input dr of the digital divider d, whose output is connected to the address input of the read-only memory rm, which holds the arc-tangent values of the first half-quadrant. 
     The most significant bit of the output signal of the third delay element v3 and that of the output signal of the third 90° phase shifter h3 are fed to the first and second inputs, respectively, of the first exclusive-OR element ex1, whose output is applied to the first input of the second exclusive-OR element ex2, and whose second input is connected to the sign output of the subtracter st. 
     Each output of the read-only memory rm is followed by one of the inverters of the first multiple inverter vi1, whose inputs are connected to the first inputs of the individual switches of the first multiple switch vu1. The second inputs of these switches are connected to the outputs of the inverters of the multiple inverter vi1, and the common control input of the switches is connected to the output of the second exclusive-OR gate ex2, while the output of the first multiple switch vu1 is followed by the digital differentiator dg. 
     The bits of the output signal of the multiple switch vu1 are supplemented on the high-order side by the output of the second exclusive-OR element ex2 as the next higher-order bit, the output of the first exclusive-OR element ex1 as the next to the highest-order bit, and the sign bit of the output signal of the third delay element v3 as the highest-order bit. The output of the multiple switch vu1 is followed by the digital differentiator dg. 
     The intermediate switch kr is controlled from the sign output va of the subtracter st in such a way that a signal smaller than, or at most equal to, that at the divisor input dr is constantly applied to the dividend input dd of the divider d, so that the latter can have a fixed number of output bits, which would be impossible in the reverse cases, i.e., if division of a larger number by a smaller one were permitted, because the result in a limiting case could then approach infinity. By means of the two absolute-value stages bb1, bb2, the output signals of the delay element v3 and the 90° phase shifter h3 are freed from their signs. As a result of this and the measure just described for the divider d, the read-only memory rm needs to contain only those arc-tangent values which lie in the first half-quadrant, i.e., between 0° and 45°. The size of this read-only memory is thus reduced to a minimum. 
     By means of the two exclusive-OR elements ex1, ex2, the number of bits required to make up an angle of 360° is added to the output signals of the read-only memory rm again. The output of the multiple switch vu1 thus provides the phase-detected signal of the input signal to be frequency-detected, and from this phase-detected signal, the frequency-detected signal is derived by means of the differentiator dg. 
     Instead of generating the two signals in phase quadrature by means of the subcircuits v3, h3, these signals can be derived by means of an odd-order transversal filter. The odd order is important because such filters have an especially small amplitude error in their frequency-response characteristics in a frequency band symmetrical with respect to a quarter of the clock frequency of the transversal filter if the order of the filter is given. 
     For eight bits at the inputs of the subcircuits v3 and h3, seven bits behind the intermediate switch kr, and ten output bits, the chip area required by an MOS integrated circuit for a frequency detector as shown in FIG. 4 is estimated at about 6 mm 2 . 
     FIG. 5 shows an embodiment of the arrangement of FIG. 2 which contains additional subcircuits for SECAM operation. Connected to the output of the first standard-band-pass filter nb1 is the first digital filter df1, whose characteristic is switchable from bell-shaped in record to inverse bell-shaped in playback; this feature is not shown in FIG. 5 for simplicity. Connected to the output of the first digital filter df1 is the additional digital frequency detector fd&#39;, which is followed by the digital frequency modulator fm, whose frequency deviation is switchable from a first value in record to a second value in playback, and which is activated by means of the horizontal synchronizing pulse ss only during the times that a chroma signal is present. The frequency modulator fm is followed by the second digital filter df2, whose characteristic is switchable from bell-shaped in playback to inverse bell-shaped in record (switchover feature not shown), and whose output is connected in the SECAM mode to the input of the second standard-band-pass filter nb2 via the first input-output path of the eighth electronic changeover switch u8. In the PAL/NTSC mode, the second input-output path of the changeover switch u8 connects the output of the first interpolator ip1 to the input of the second standard-band-pass filter nb2. 
     In the SECAM mode, instead of the subcircuits d1, n3, fb, kf, ip1, the subcircuits just mentioned, i.e., df1, fd&#39;, fm, df2, are thus in operation. The other subcircuits in the circuit diagram of FIG. 5 are the same as those in FIG. 2. 
     FIG. 6 shows a block diagram and the frequency-response characteristic of the preferred design of the first standard-band-pass filter nb1. Compared with the digital filters that could be used for this band-pass filter, the digital filter of FIG. 6 has quite an advantageous structure in regard to the number of adders ad and subtracters sb used. Its transfer function is ##EQU1## 
     As can be seen, the digital filter of FIG. 6 is composed of the adders ad, the subtracter sb, and delay elements v, each of which provides a delay equal to a multiple of the period of the filter&#39;s sampling signal, this multiple being equal to the positive value of the respective exponent of the base z. 
     As can also be seen in the block diagram of FIG. 6, the subcircuit for implementing the term (1+z -6 ) is located behind the decimator dz, whose sampling signal f1 has a frequency F1 equal to one-third of the frequency Fc of the sampling signal fc. At a frequency Fc of 18 MHz, this subcircuit is thus operated at a frequency Fc/3 of 6 MHz. Accordingly, the delay element of the subcircuit behind the decimator dz, with the symbol z x  and the exponent -2, gives a delay of 2Fc/3, which is equal to 6Fc. 
     The frequency-response curve shown in FIG. 6 gives the normalized attenuation g in dB as a function of the frequency F in MHz. The maximum of the curve is located at 4.5 MHz, which is equal to the above-mentioned subcarrier frequency zt. 
     FIG. 7 shows a block diagram and the frequency-response curve of the preferred design of the signal-forming band-pass filter fb of FIG. 2 or 5. In addition to the above-mentioned basic units ad, sb, and v, this digital filter contains multipliers mp, which cause the constant decimal factor 0.375 of the transfer function H(z) to become effective. The transfer function is 
     
         H(z)=(1-z.sup.-2).sup.5 (0.375+z.sup.-2)(1+0.375z.sup.-2). 
    
     This digital filter, too, has an advantageous structure in terms of the number of adders and subtracters required. Its characteristic is symmetrical with respect to 1.5 MHz, which follows from the fact that this filter is clocked with the sampling signal f1 at the frequency Fc/3, so that the 4.5-MHz subcarrier frequency is shifted to one-third, too. 
     FIG. 8 shows a block diagram and the frequency-response curve of the preferred design of the first interpolator ip1, whose transfer function is ##EQU2## 
     The digital multiplexer mx at the input of the digital filter of FIG. 8 converts each digital input word e into the three-element sequence e, 0, -e. This three-element sequence corresponds to the realization of the term (1-z -2 ). 
     The graphical representation of the frequency-response curve of the digital filter of FIG. 8 is interrupted i.e., compressed, between 3.0 MHz and 4.0 MHz. This digital filter is clocked with the sampling signal fc, so that the attenuation minimum (0 dB) is at 4.5 MHz if a sampling frequency Fc of 18 MHz is used. 
     FIG. 9 shows a block diagram of a preferred embodiment of the two sine-wave generators sg1 and sg2 with the associated multipliers m2 and m5, respectively, of FIGS. 2 and 5. Such a generator contains the j-bit digital accumulator ak; in the embodiment of FIG. 9, j=14. Accumulators, as is well known, are clocked summing circuits which, on receipt of each clock pulse, add the same number to the result obtained with the preceding clock pulse. The frequency-setting input fe is thus presented with one of the two digital words ds1, ds2 from one of the two registers r1, r2 of FIG. 2 or 5. The clock signal applied to the accumulator ak is the sampling signal fc. 
     Of the bits less significant than the (j-2)th bit, q bits of the output signal of the accumulator ak, where q is smaller than or equal to j-2, are fed through the individual inverters of the second multiple inverter vi2. In the embodiment of FIG. 9, q=6, so that the bits with the weights 2 6  to 2 11  are covered (assuming that the straight binary code is used). 
     The inputs of the individual inverters are connected to the first inputs of the individual switches of the second multiple switch vu2, while the second inputs of these switches are connected to the outputs of the individual inverters, and the common control input of the switches is connected to the output for the (j-1)th bit. The output of the second multiple switch vu2 is coupled to the address input of the additional read-only memory rm&#39;, which holds the sine values of the first quadrant and has its output connected to the first input of the multiplier m2 or m5. The second input of the multiplier is the signal input, and its output is connected to the inverters of the third multiple inverter vi3. The inputs of these inverters are connected to the first inputs of the individual switches of the third multiple switch vu3, while the second inputs of these switches are connected to the output of the inverters. The common control input of the switches of the third multiple switch vu3 is connected to the output for the jth bit of the accumulator ak, and the output of the third multiple switch vu3 delivers the input signal multipled by the sine-wave signal. 
     The two multiple inverters vi2, vi3 and the two multiple switches vu2, vu3 also serve to derive the sine values of the second to the fourth quadrants from the sine values of the first quadrant which are contained in the read-only memory rm&#39;. In a similar and analogous manner, (not shown in FIG. 9), the cosine values at the cosine outputs ca of the sine-wave generators sg1, sg2 can be derived. For this purpose, one additional read-only memory, two additional multiple inverters, and two additional multiple switches may be provided, for example. However, it is also possible to take advantage of the relation between a sine function and a cosine function, namely that one follows from the other by a 90° phase shift, so that only the additional read-only memory rm&#39; of FIG. 9, holding the sine values of the first quadrant, is required. 
     In FIGS. 2 to 9, all connections between the individual circuits are drawn as single-wire lines. This was done for clarity. Since, according to the principle underlying the invention, the subcircuits contained in FIGS. 2 to 9 are subcircuits processing digital signals in parallel, the interconnecting leads between the individual subcircuits must be thought of as buses, with a few exceptions, such as the control lines for the various changeover and multiple switches. In FIG. 9, the numbers of conductors of the buses are indicated by the numbers at the oblique strokes. 
     The invention can be implemented with monolithic integrated circuits, as was mentioned at the beginning. The overall circuit can be constructed as a single monolithic integrated circuit or divided among several integrated circuits, as required. Since all subcircuits are digital circuits, implementation with insulated-gate field-effect transistors, i.e., with so-called MOS technology, is particularly advantageous, but fast bipolar digital-circuit techniques may also be suitable for circuit implementation. 
     The principle used in the chroma channel--shifting the digital processing to a subharmonic of the clock frequency by the quadrature mixing regardless of the standard-dependent chrominance-subcarrier frequency and, thus, being able to use a fixed sampling frequency for all color-television standards--has the big advantage that only a single clock generator with a fixed frequency is required for the sampling signal. As this clock generator is usually a crystal oscillator, only a single crystal is necessary, while, if the clock frequency were &#34;tied&#34; to the standard-dependent fourfold chrominance-subcarrier frequency, three crystal oscillators (one each for PAL, NTSC, and SECAM) and one oscillator with three switchable crystals would be required. Therefore, the application of this principle is not limited to video recorders, but the principle can be used with success wherever color-television signals of several standards are to be processed in digitized form.