Abstract:
A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.

Description:
[0001]    This application claims priority to Taiwan Patent Application No. 097109739 filed on Mar. 19, 2008, the disclosures of which are incorporated herein by reference in their entirety. 
       CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0002]    Not applicable. 
       BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    The present invention provides a package conductive structure of a chip and a method for manufacturing the same. In particular, the package conductive structure has an under bump metal formed through an electroless plating process. 
         [0005]    2. Descriptions of the Related Art 
         [0006]    In modern advanced semiconductor manufacturing processes, semiconductor devices have been minimized to the nano-scale in mass production. Nano-scale packaging technologies applicable to such semiconductor devices have also emerged to accommodate the need of different products. Because the integrated circuit (IC) industry develops at a fast pace, ICs have become increasingly complex in design and are developing towards the system-on-chip (SOC) in which various functions are integrated on a single chip. Furthermore, SOCs are designed with an ever higher operating frequency and devices therein are shrunk increasingly in size. Hence, once the fabrication of an IC is completed on a wafer, the wafer has to be transferred to a packaging facility for subsequent dicing and packaging. The efficiency of the packaging process impacts the production cost and operational performance of the packaged chip. Accordingly, the package structure and material thereof have become more important. 
         [0007]    As shown in  FIGS. 1A to 1G , the chip package conductive structure of the prior art and a method for manufacturing the same are depicted therein. As depicted in  FIG. 1A , the chip  11  is formed with a pad  131  and a first passivation layer  13  that partially exposes the pad  131  therethrough. Then, depending on the design requirements, a first under bump metal (UBM)  133  is formed on the partially exposed pad  131  through a photolithographic process, as shown in  FIG. 1B . The first UBM  133  is made of Cr, Ti, Ni, Cu, or alloys thereof. Next, as shown in  FIG. 1C , a redistribution layer (RDL)  15  is formed through a photolithographic process to overlay the first UBM  133  and the first passivation layer  13 . The redistribution layer  15  is conventionally made of a conductive material selected from Al or Cu. With the redistribution layer  15 , bumps that are subsequently formed may be electrically connected to the pad  131  without restricted by the location of the pad  131 . The bumps may be re-arranged according to the actual requirements with enhanced flexibility in use. Subsequently, as shown in FIG  1 D, a second passivation layer  17  is extensively formed to overlay the redistribution layer  15  and the first passivation layer  13  and then patterned through a lithographic process to partially expose the redistribution layer  15  at appropriate locations. 
         [0008]    Next, as shown in  FIG. 1E , a second UBM  135  is formed on the partially exposed redistribution layer  15 . Then, as shown in FIG  1 F, a bump  19  is solder plated or a solder ball is implanted onto the second UBM  135  to electrically connect with the second UBM  135 . Finally, the bump  19  shown in  FIG. 1F  may be reflowed to obtain a ball bump  19  as shown in  FIG. 1G . However, the package conductive structure of the chip  11  of the prior art and the method of forming the same still have the following disadvantages. Usually, a first UBM  133  is needed between the pad  131  and the redistribution layer  15  and a second UBM  135  is needed between the bump  19  and the redistribution layer  15  to provide a better adhesion effect and prevent the diffusion of conductive metal materials. However, the formation of the first UBM  133  and the second UBM  135  conventionally involves photolithographic processes which use expensive photomasks. The use of more photomasks leads to a higher production cost and renders the actual manufacturing process more complex, making it difficult to improve the yield of the process. 
         [0009]    In view of this, it is important to simplify the chip package conductive structure and the manufacturing process thereof, thereby to save the use of photomasks and consequently reduce the cost. 
       SUMMARY OF THE INVENTION 
       [0010]    One objective of this invention is to provide a conductive structure of a chip, comprising a redistribution layer, a UBM and a bump. The redistribution layer is formed on the chip and has a first conductive area and a second conductive area, in which the first conductive area is electrically connected to the chip. The UBM is formed on the second conductive area of the redistribution layer and electrically connected to the redistribution layer. The UBM is an electroless plating layer. The bump is formed on and electrically connected to the UBM. Since the UBM of this invention is formed through an electroless plating process, the resulting UBM is more uniform in thickness compared to the structures of the prior art. 
         [0011]    Another objective of this invention is to provide a method for manufacturing a conductive structure of a chip, comprising: forming a redistribution layer on a chip, wherein the redistribution layer has a first conductive area to electrically connect to the chip therethrough; forming an under bump metal (UBM) through an electroless plating process to electrically connect the redistribution layer through a second conductive area thereof; and forming a bump electrically connected to the UBM. Because the UBM of this invention is formed through an electroless plating process instead of a photolithographic process, the manufacturing method of this invention may not only save use of photomasks, but also simplify the process steps to improve the yield of chip packages, and thus reducing the production cost. 
         [0012]    The detailed technology and preferred embodiments implemented for the subject invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIGS. 1A to 1G  are schematic views of a chip package conductive structure of the prior art; and 
           [0014]      FIGS. 2A to 2F  are schematic views of a chip package conductive structure of this invention and a method for manufacturing the same. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0015]      FIGS. 2E and 2F  are schematic views of a conductive structure  2  for packaging a chip  21  according to this invention. The conductive structure  2  comprises a redistribution layer  25 , a UBM  28  and a bump  29 . 
         [0016]    To explain the structure and the method of this invention more clearly, descriptions will be made with reference to the attached drawings according to the process sequence. In reference to  FIG. 2A , the chip  21  comprises a first passivation layer  23  and a pad  231 , in which the pad  231  is made of Al or Cu. More specifically, the first passivation layer  23  partially overlays the pad  231  and has the pad  231  partially exposed therethrough, so that the first passivation layer  23  and the pad  231  together define an active surface. The pad  231  is exposed on the active surface. 
         [0017]    Next, as shown in  FIG. 2B , a redistribution layer  25  is then formed on the active surface of the chip  21 . More specifically, the redistribution layer  25  is formed on the first passivation layer  23  of the chip  21  and electrically connected to the pad  231  through a first conductive area  251  thereof. The redistribution layer  25  are formed as the following steps. Initially, a barrier layer  252  is sputtered to overlay the first passivation layer  23  and the pad  231 . Next, a conductive layer  254  is sputtered on the barrier layer  252 . Finally, the barrier layer  252  and the conductive layer  254  are patterned through a photolithographic process to form a conductive structure for electrical connection. The barrier layer  252  should be a Ti/W metal layer, while the conductive layer  254  is formed by sputtering Au, Al, or Cu. However, the materials of the layers are not merely limited thereto, and any conductive material may be used as the material of the conductive layer  254 . Accordingly, a combination of materials of the barrier layer  252  and the conductive layer  254  may be selected depending on practical requirements. For example, TiW—Au, Ti—Cu, TiW—Cu, Ti—Al, Ti—NiV—Cu, Ti(W)—Ni or the like. Besides preventing the metal materials of the conductive layer  254  (e.g., Au) and the pad  231  (Al or Cu) from diffusing into each other, the barrier layer  252  may also enhance the adhesion between these materials. 
         [0018]    Next, in reference to  FIG. 2C , a second passivation layer  27  is formed to overlay the redistribution layer  25  and patterned through a photolithographic process to partially expose the second conductive area  253  of the redistribution layer  25 . 
         [0019]    Subsequently, as shown in  FIG. 2D , a UBM  28  is formed on the second conductive area  253  to be electrically connected to the redistribution layer  25 . This invention is unique in that the UBM  28  is an electroless plating layer. In other words, the patterning step of the photolithographic process in the prior art method is eliminated, and thus saving use of photomasks and the associated lithographic process. The UBM  28  should be formed by forming an Ni layer  281  and an Au layer  283  in sequence through the electroless plating process, in which the Ni layer  281  is formed directly on the second conductive area  253  and the Au layer  283  is subsequently formed on the Ni layer  281 . It should be noted that the material of the UBM  28  is not merely limited to Ni/Au and other materials may also be used instead by those of ordinary skill in the art, so no limitation is made herein. 
         [0020]    Finally, as shown in  FIG. 2E , the bump  29  is formed on the UBM  28  to be electrically connected thereto. More specifically, the bump  29  is electrically connected to the Au layer  283  of the UBM  28 . The bump  29  may be made of Sn or a terne metal, but it is not merely limited thereto. The bump  29  may be reflowed to form a ball bump, as shown in  FIG. 2F . 
         [0021]    In the manufacturing process and the structure thus formed of this invention, the UBM is formed through an electroless plating process. This, apart from advantageously providing the UBM with a uniform thickness, may further save the use of at least one photomask and the associated photolithographic process to simplify the manufacturing process, thus increasing the production output, reducing the cost and ensuring a higher yield. 
         [0022]    The above disclosure is related to the detailed technical contents and inventive features thereof. People skilled in this field may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the following claims as appended.