Abstract:
A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

Description:
TECHNICAL FIELD  
       [0001]     The present invention relates in general to integrated circuitry, and in particular, to register files.  
       BACKGROUND INFORMATION  
       [0002]     Register files are memory units that are commonly used in modern day state-of-the art processors, and other integrated circuitry. Register files are valuable for temporarily storing data for subsequent use by other processing circuitry. Often a need arises for the output to be multiplexed with another signal before it enters a latch. Such a common usage is when the latched output data needs to be retained to avoid a conflict created by any kind of stall operation. In such a scenario, a hold multiplex (MUX) is used where the latch output is fed back to the MUX with a stall signal as the select signal. The conventional approach of adding this MUX in the output data path adds some extra delay, which can cause the access time to increase. Such an added delay may be detrimental in high-performance processors and other integrated circuitry, which may be in the middle of a calculation of data, and need the data from the register file immediately.  
         [0003]     Therefore, there is a need in the art for an improved register file that minimizes the extra delay caused by the multiplexor circuit.  
       SUMMARY OF THE INVENTION  
       [0004]     The present invention addresses the foregoing need by providing a register file that does not utilize a multiplexor directly within the data path from the register file to the output of the array. By removing this extra multiplexor, the previously incurred delay through the MUX is merely replaced with some extra loading on the global bit line of the register file, which causes almost no additional delay in the data access time. Thus, where a data multiplexing is required, the present invention provides a register file that is faster and more efficient in terms of performance.  
         [0005]     In an embodiment of the present invention, local bit lines are coupled together and to a tri-state inverter, whose output is the global bit line of the register array. Depending upon the number of entries in the register file, there could be a number of tri-stated inverters whose outputs are wired-ORed. In a conventional approach, this wired-ORed signal would proceed through a 2:1 MUX before the output latch. In an embodiment of the present invention, the 2:1 MUX is removed and replaced with a tri-state inverter whose output is coupled to the global bit line.  
         [0006]     In another embodiment, the 2:1 MUX is replaced with a transmission gate multiplexer whose output is coupled to the global bit line.  
         [0007]     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:  
         [0009]      FIG. 1  illustrates a typical memory cell used within register files;  
         [0010]      FIG. 2  illustrates a prior art register file;  
         [0011]      FIG. 3  illustrates a register file in accordance with an embodiment of the present invention;  
         [0012]      FIG. 4  illustrates a data processing system configured in accordance with the present invention;  
         [0013]      FIG. 5  illustrates a prior art register file; and  
         [0014]      FIG. 6  illustrates a register file in accordance with another embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0015]     In the following description, numerous specific details are set forth such as specific configurations, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.  
         [0016]     Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.  
         [0017]      FIG. 1  illustrates a single register file cell  100 . The cell can be single ported (one read and one write) or could have multiple read and write ports. With respect to a description of the present invention hereinafter, a single read port register file cell will be utilized and referred to, but the present invention is equally applicable to using multiple read ports.  
         [0018]      FIG. 2  illustrates a prior art register file  200 , which could be configured as a 16-entry by 64 register file, meaning there are sixteen unique word lines with sixty-four columns. Register file  200  makes use of the cells  100 . The read bit lines of each cell  100  are coupled with a plurality of similar cells. There are then a plurality of unique local bit lines (LBLs)  201 , with each local bit line  201  coupled to an input of a tri-state inverter  202  whose outputs are coupled to form a global bit line (GBL)  203 . Local Select signals  0  . . .  3  are used to control the tri-state inverters  202 . The global bit line  203  is coupled to an input of an inverter  204 , which has its output coupled to one of the inputs of a multiplexor  205 . An output of the multiplexor  205  is coupled to a latch  207 , whose output may be coupled to other circuitry (not shown). The output of the latch  207  is fed back to the other input of the multiplexor  205 . Control of the multiplexor  205  is from a Hold MUX Select signal  206 . When it is desired to temporarily hold the data output from the register file  200  in the latch  207 , circuitry (not shown) will send the Hold MUX Select signal  206  to the multiplexor  205 .  
         [0019]      FIG. 3  illustrates an embodiment of the present invention where the multiplexor  205  is essentially replaced with a tri-state inverter  305 . The register file cells and their local bit line circuitry  200  can be as similarly described above with respect to  FIG. 2 . Note, however, that the description of the present invention following could use any other size register file. The global bit line  303  is coupled to an input of an inverter  304  whose output is coupled to an input of latch  307 . The output of latch  307  is the output of the register file of this embodiment of the present invention, and is also fed back to an input of the tri-state inverter  305 , whose output is coupled to the global bit line  303 . The Hold MUX Select signal  306 , which can be similarly generated as above as with Hold MUX Select signal  206  is coupled to inverter  305 . In this case, the Hold MUX Select signal  306  may be an active low signal. Logically, the register file of  FIG. 3  performs the same operation as that of  FIG. 2 , but does not have the delay associated with the multiplexor  205 .  
         [0020]     The tri-state inverters  202  for each local bit line group will have a separate local select signal, which are generated from read addresses. This is to ensure that when a local bit line group (e.g., in this example, a group of four) is not selected, then the tri-state inverter selected puts its output into a high-impedance state. Therefore, the only local bit line group which is selected forwards the local bit line value onto the global bit line  303 . In case of a stall operation or any other bit line multiplexing, the Hold MUX Select signal  306  will be used as the tri-state inverter select and also as part of the decoding which generates local bit line select signals. This will ensure that when a stall is needed, then all local bit line groups will generate high-impedance states on the global bit line  303 , such that only the hold tri-state inverter  305  dictates the value on the global bit line  303 .  
         [0021]      FIG. 5  illustrates another prior art register file, similar to the register file illustrated in  FIG. 2  except that the tri-state inverter  202  is replaced with a transmission gate multiplexor circuit comprising transmission gate  220  and inverter  221 . As shown in  FIG. 6 , the mutiplexor  205  is replaced in this embodiment by a transmission gate multiplexor circuit comprising transmission gate  330  and inverter  331 . The advantages described above with respect to  FIG. 3  are also enjoyed by the register file shown in  FIG. 6 .  
         [0022]     A representative hardware environment for practicing the present invention is depicted in  FIG. 4 , which illustrates an exemplary hardware configuration of data processing system  413  in accordance with the subject invention having central processing unit (CPU)  410 , such as a conventional microprocessor, and a number of other units interconnected via system bus  412 . Data processing system  413  includes random access memory (RAM)  414 , read only memory (ROM)  416 , and input/output (I/O) adapter  418  for connecting peripheral devices such as disk units  420  and tape drives  440  to bus  412 , user interface adapter  422  for connecting keyboard  424 , mouse  426 , and/or other user interface devices such as a touch screen device (not shown) to bus  412 , communication adapter  434  for connecting data processing system  413  to a data processing network, and display adapter  436  for connecting bus  412  to display device  438 . CPU  410  may include other circuitry not shown herein, which will include circuitry commonly found within a microprocessor, e.g., execution unit, bus interface unit, arithmetic logic unit, etc. CPU  410  may also reside on a single integrated circuit. The register array described with respect to  FIGS. 3 and 6  may be used in various portions of system  413 .  
         [0023]     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.