Abstract:
In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an arbitration method for a bus use requests in a system in which plural master apparatus are connected to a slave apparatus through a bus. 
   2. Related Background Art 
   In the known art, a master apparatus connected to a bus, in case of a need for using the bus, immediately issues a request signal requesting a bus use right. The arbitration of the priority for the bus use rights is executed by an arbiter. 
   However, it is difficult to achieve a fine adjustment in the arbitration of the priority of the bus use rights by the arbiter, and to dynamically change the priority. Also the logic required for such arbiter is very complicated. 
   SUMMARY OF THE INVENTION 
   In consideration of the foregoing, an object of the present invention is to provide a method capable of a fine adjustment of the priority of the bus use rights, and a system for such method. 
   Another object of the present invention is to provide a method capable of dynamically changing the priority of the bus use right and a system for such method. 
   According to one aspect, the present invention which achieves these objectives relates to a master apparatus constituting a system including plural master apparatus which are connected to a slave apparatus through a common path and an arbiter for arbitrating requests for the use of such path, the master apparatus including timer means for measuring a predetermined interval from a time when the use of the path becomes necessary, and issuing means for issuing a request signal for requesting the use of the path to the arbiter after the lapse of the above-mentioned interval. 
   According to another aspect, the present invention which achieves these objectives relates to an arbitration method in a system including plural master apparatus which are connected to a slave apparatus through a common path and an arbiter for arbitrating requests for the use of such path, the method including a step of measuring a predetermined interval from a time when the use of the path becomes necessary in at least one of the plural master apparatus, a step of issuing a request signal for requesting the use of the path after the lapse of the predetermined interval and a step that the arbiter equally handles the request signals from the plural master apparatus to arbitrate the request for the use of the path. 
   Other objectives and advantages besides those discussed above shall be apparent to those skilled in the art from the description of a preferred embodiment of the invention which follows. In the description, reference is made to accompanying drawings, which form a part thereof, and which illustrate an example of the invention. Such example, however, is not exhaustive of the various embodiments of the invention, and therefore reference is made to the claims which follow the description for determining the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a system of a first embodiment; 
       FIG. 2  is a diagram showing the details of a bus interface in a master apparatus of the first embodiment; 
       FIG. 3  is a chart showing an example of signal wave forms of the first embodiment; 
       FIG. 4  is a block diagram of a system of a second embodiment; 
       FIG. 5  is a block diagram of a system of a third embodiment; 
       FIG. 6  is a diagram showing the details of a bus interface in a master apparatus of the third embodiment; and 
       FIG. 7  is a diagram showing the details of a bus interface in a master apparatus of a fourth embodiment. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   In the following, the present invention will be further clarified by preferred embodiments thereof, with reference to accompanying drawings. 
   (First Embodiment) 
   In the following there will be given an explanation on a first embodiment of the present invention, with reference to the accompanying drawings. 
     FIG. 1  is a block diagram of a system in the first embodiment of the present invention. A master apparatus A 101 , a master apparatus B 102  and a slave apparatus  103  are connected through a system bus  105 , and an arbiter  104  executes arbitration of requests for a bus use right from the master apparatus A 101  and the master apparatus B 102 . 
   The master apparatus A 101  asserts a request signal A 106  at requesting a bus use right, and the arbiter  104  asserts a grant signal A 107  at giving a bus use right to the master apparatus A 101 . Similarly, the master apparatus B 102  asserts a request signal B 108  at requesting a bus use right, and the arbiter  104  asserts a grant signal B 109  at giving a bus use right to the master apparatus B 102 . Also the arbiter  104  informs, by a no-request signal  110 , that neither the request signal from the master apparatus A 101  nor that from the master apparatus B 102  is asserted. 
   The arbiter  104  deals with all the requests equally, in such a manner that the priority for the bus use right is same for all the master apparatus. Also the method of arbitration will be an ordinary round robin method. 
     FIG. 2  is a block diagram around a bus interface of the master apparatus A 101 . An interval timer A 202  is connected to a bus interface A 201 . A transaction start signal A 203  transmits a command to start a transaction using a bus, from an internal logic of the master apparatus A 101  to the bus interface A 201 . 
   The interval timer A 202  counts an interval from a time when the transaction start signal A 203  is asserted to a time when the request signal A 106  is actually asserted. In the interval timer A 202 , an interval set value A 206  is loaded according to a load signal A 204 . Such value can be changed for example by a register setting. An expiration signal A 205  informs that the interval timer A 202  has expired as a result of a count-down operation. 
   Let it be assumed that a transaction start signal A 203  is asserted by the internal logic of the master apparatus A 101 . In case the no-request signal  110  is not asserted, a load signal A 204  is transmitted to the interval timer A 202  in order to insert an interval. The interval timer A 202  executes loading of the interval set value A 206  and initiates a count-down operation. When the interval timer A 202  reaches 0, the expiration signal A 205  is asserted. In response thereto, the bus interface A 201  asserts the request signal A 106  to the arbiter A 104 . 
   In case the no-request signal  110  is asserted, the interval is not inserted, so that the request signal A 106  is asserted as soon as the transaction start signal A 203  is asserted. 
   The arbiter  104  executes arbitration, and then asserts the grant signal A 107  when the bus use right becomes ready to be given to the master apparatus A 101 . In response thereto, the bus interface A 201  initiates a transaction on the system bus  105 . 
     FIG. 3  shows an example of signal wave forms in case two master apparatus, namely the master apparatus A 101  and the master apparatus B 102 , request the use of bus in succession. 
   It is assumed that the master apparatus A 101  is provided with an interval inserting function, with a set value of 15 cycles. 
   Each master apparatus indicates a request for starting a transaction, by a transaction start signal from the internal logic. The master apparatus B 102  immediately asserts the request signal B to the arbiter  104 . On the other hand, the master apparatus A 101  asserts the request signal A after a lapse of 15 cycles. In the beginning, since the request signal is only asserted from the master apparatus B 102 , the arbiter  104  asserts a grant signal B thereby giving the bus use right to the master apparatus B 102 . In response, the master apparatus B 102  initiates the transaction. It is assumed that the transaction requires 10 cycles. During the transaction, a bus busy signal B is asserted. Upon completion of the transaction, the internal logic of the master apparatus B 102  again requests the start of a transaction, and requests the bus use right again by a request signal B. As the request signal A from the master apparatus A 101  is not yet asserted even at this point, the master apparatus B is enabled again to use the bus. 
   Thereafter, the request signal A from the master apparatus A 101  is finally asserted. When the master apparatus B completes the second transaction, the arbiter  104  then asserts the grant signal A, thereby giving the bus use right to the master apparatus A 101 . Now the master apparatus A 101  initiates the transaction. 
   After the transaction is terminated, the internal logic of the master apparatus A again request the start of a transaction, but asserts the request signal A again after a lapse of 15 cycles. Therefore, the master apparatus B 102  is again enabled to executes two transactions in succession. 
   As explained in the foregoing, by setting an interval of 15 cycles in the master apparatus A, the frequency of the use of bus becomes once for the master apparatus A 101  whereas twice for the master apparatus B 102 . Thus, the priority for the bus use right can be adjusted by such interval setting. For example, the priority for the bus use right for the master apparatus B 102  can be made even higher by increasing the set value of the interval for the master apparatus A 101 . 
   With an increase in the number of the master apparatus, the priority for the bus use right can be set more finely by setting an interval for each master apparatus. 
   (Second Embodiment) 
   The present invention is applicable not only to the master apparatus connected to the bus as shown in  FIG. 1 , but also to master apparatus connected to a multiplex switch as shown in FIG.  4 . Referring to  FIG. 4 , a multiplex switch  401  connects a master apparatus A 101  and a master apparatus B 102  to a slave apparatus  103 . An arbiter  402  receives requests from the master apparatus A 101  and the master apparatus B 102 , executes arbitration, sends a grant signal to each master apparatus, and controls switching operation of the multiplex switch  401 . A control signal  403  from the arbiter  402  controls the switching of the multiplex switch  401 . The function of the master apparatus is same as a case of connection by a bus. 
   (Third Embodiment) 
     FIG. 5  is a block diagram of a system of a third embodiment. A master apparatus A 501 , a master apparatus B 502 , a slave apparatus A 503 , and a slave apparatus B 504  are connected to a multiplex switch  505 . The multiplex switch  505  connects the master apparatus A 501  to the slave apparatus A 503  or the slave apparatus B 504 , and connects the master apparatus B 502  to the slave apparatus A 503  or the slave apparatus B 504 . 
   The master apparatus A 501  asserts a slave A request signal A 520  in case of requesting a connection to the slave apparatus A 503 , and asserts a slave B request signal B 521  in case of requesting a connection to the slave apparatus B 504 . The master apparatus B 502  asserts a slave A request signal B 522  in case of requesting a connection to the slave apparatus A 503 , and asserts a slave B request signal B 523  in case of requesting a connection to the slave apparatus B 504 . 
   An arbiter  506 , receiving the request signals from the master apparatus A 501  and the master apparatus B 502 , controls the multiplex switch  505  to a connection with the slave apparatus A 503  or the slave apparatus B 504 . The arbiter  506  asserts a grant signal A 524  in case of giving a slave connecting right to the master apparatus A 501 , and asserts a grant signal B 525  in case of giving a slave connecting right to the master apparatus B 502 . The arbiter  506  controls the multiplex switch  505  by a switch control signal  510 . A slave A idle signal  526  indicates that neither the master apparatus A 501  nor the master apparatus A 502  is connected to the slave apparatus A 503 . 
   In the present embodiment, the master apparatus A 501  and the master apparatus B 502  assert a request signal with the insertion of an interval in case of requesting a transaction to the slave apparatus A 503 , but assert a request signal without inserting the interval in case of requesting a transaction to the slave apparatus B 504 . Each master apparatus determines, based on addresses, whether the transaction is to be executed with the slave apparatus A 503  or the slave apparatus B 504 . 
     FIG. 6  is a block diagram around a bus interface of the master apparatus A 501 . An address decoder A 601  and an interval timer A 603  are connected to a bus interface A 602 . A transaction start signal A 610  and a target address A 611  of the transaction are entered into the address decoder A 601 . The transaction start signal A 610  transmits a command to start the transaction utilizing the bus, from an internal logic of the master apparatus A 501 . The interval timer A 603  counts an interval from a time when the transaction start signal A 610  is asserted to a time when the request signal A 520  is actually asserted. In the interval timer A 603 , an interval set value A 616  is loaded according to a load signal A 614 . Such value can be changed for example by a register setting. An expiration signal A 615  informs that the interval timer A 603  has expired as a result of a count-down operation. 
   A slave A transaction start signal A 612  is asserted in case the transaction request from the internal logic is for the slave A 503 , while a slave B transaction signal A 613  is asserted in case the transaction request from the internal logic is for the slave B 504 . 
   Now, let it be assumed that the transaction start signal A 610  is asserted by the internal logic of the master apparatus A 501 . In case the target address A 611  is an address of the slave apparatus A 503 , the address decoder A 601  decodes the target address A 611  and asserts the slave A transaction start signal A 612 . The bus interface A 602  transmits a load signal A 614  to the interval timer A 603  in order to insert an interval. The interval timer A 603  loads the interval set value A 616  and initiates a count-down operation. When the interval timer A 603  reaches 0, an expiration signal A 615  is asserted. In response, the bus interface A 602  asserts the slave A request signal A 520  to the arbiter  506 . 
   On the other hand, in case the target address A 611  is an address of the slave B and the slave B transaction start signal A 613  is asserted, the bus interface A 602  immediately asserts the slave B request signal A 521  without inserting the interval. 
   In case a slave A idle signal  526 , indicating the absence of the master apparatus connected to the slave apparatus A 503 , is asserted by the arbiter  506 , even if the slave A transaction start signal A 612  is asserted, the bus interface A 602  immediately asserts the slave A request signal A 520 . 
   (Fourth Embodiment) 
   In a further application of the present invention, an interval different for each slave can be inserted by providing the master apparatus with a mechanism capable of varying the set value of the interval timer for each target slave.  FIG. 7  is a block diagram around a bus interface in such application. 
   In case of a transaction to a slave apparatus A 503 , a slave A load signal A 701  is asserted, while, in case of a transaction to a slave apparatus B 504 , a slave B load signal A 702  is asserted. In case the slave A load signal A 701  is asserted, a slave A interval set value A 703  is loaded in an interval timer  603 , but, in case the slave B load signal A 702  is asserted, a slave B interval set value A 704  is loaded in the interval timer  603 . Such configuration enables to load an interval set value different for each target. 
   As explained in the foregoing embodiments, it is rendered possible to achieve detailed adjustment of the priority of the bus use right despite of the use of a simple arbiter, by inserting an interval of a predetermined length when a master apparatus connected to a bus or a multiplex switch requests a start of a transaction. Also the priority can be changed dynamically, by adjusting the length of the interval. It is also possible to prevent a decrease in the latency in a low traffic situation, by not inserting the interval when the bus is not in use. 
   Also in case the slave apparatus is present in plural units, the interval may be inserted only to a transaction to a specified slave. In this manner the priority can be made different for each slave. 
   Although the present invention has been described in its preferred form with a certain degree of particularity, many apparently widely different embodiments of the invention can be made without departing from the spirit and the scope thereof. It is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.