Abstract:
The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method for fabricating an embedded static random access memory, and more particularly, to a method for fabricating an embedded static random access memory with improved random single bit failure rate. 
         [0003]    2. Description of the Prior Art 
         [0004]    An embedded static random access memory (SRAM) comprises a logic circuit and a static random access memory connected to the logic circuit. SRAM is a kind of volatile memory cell, which means it preserves data only while power is continuously applied. SRAM is built of cross-coupled inverters that store data during the time that power remains applied, unlike dynamic random access memory (DRAM) that needs to be periodically refreshed. Because of its high access speed, SRAM is also used in computer system as a cache memory. 
         [0005]    Please refer to  FIG. 1 , which shows a circuit diagram of typical six-transistors SRAM (6T-SRAM)  10 . The 6T-SRAM cell  10  comprises pull-up transistors  12  and  14 , pull-down transistors  16  and  18 , and access transistors  20  and  22 . These six transistors constitute a set of flip-flops. Pull-up transistors  12 ,  14  and pull-down transistors  16 ,  18  constitute a latch that stores data in the storage node  24 ,  26 . Because the pull-up transistors  12 ,  14  act as power load devices they can be replaced by resistors. At this point, the static random access memory is a four-transistors SRAM (4T-SRAM). 
         [0006]    Generally speaking, the pull-up transistors  12 ,  14  of the 6T-SRAM cell  10  comprise P-type metal oxide semiconductor (PMOS) transistors. The pull-down transistors  16 ,  18  and the access transistors  20 ,  22  comprise N-type metal oxide semiconductor (NMOS) transistor. The pull-up transistor  12  and the pull-down transistor  16  constitute a series circuit  28 . One end of the series circuit  28  is connected to a power supply  32  and the other end of the series circuit  28  is connected to a ground  34 . Equally, the pull-up transistor  14  and the pull-down transistor  18  constitute a series circuit  30 . One end of the series circuit  30  is connected to the power supply  32  and the other end of the series circuit  30  is connected to the ground  34 . 
         [0007]    Additionally, the storage node  24  is connected to the respective gates of the pull-down transistor  18  and the pull-up transistor  14 . The storage node  24  is also connected to the drains of the pull-down transistor  16 , pull-up transistor  12  and the access transistor  20 . Equally, the storage node  26  is connected to the respective gates of the pull-down transistor  16  and the pull-up transistor  12 . The storage node  26  is also connected to the drains of the pull-down transistor  18 , pull-up transistor  14  and the access transistor  22 . The gates of the access transistors  20  and  22  are respectively coupled to a word line  36 , and the sources are coupled to a relative data line  38 . 
         [0008]    The aggressive scaling of MOS transistors faces severe challenges to the effective capacitance, which is usually expressed as dielectric inversion thickness (Tox_INV). When a gate dielectric layer is in an inversion condition, the gate possesses less carrier mobility than metal materials, thus causing lower effective capacitance. There are two primary methods for improving the effective capacitance. One is to improve the property of the gate dielectric layer, such as using high-K materials or decreasing the thickness of the gate dielectric layer. The other one is to decrease the depletion region of the gate, such as doping atoms or implanting ions on the polysilicon gate to improve the carrier mobility. 
         [0009]    U.S. Patent No. 2003/0032231 A1, paragraphs 38 and 47, teaches a most common method used in industry to effectively decrease the Tox_INV by providing a N+ polysilicon doping process to the N type polysilicon of NMOS devices. 
         [0010]    Please refer to  FIG. 2 , which illustrates a schematic plan view of an embedded static random access memory. As shown in  FIG. 2 , a semiconductor substrate  40  is provided. A memory cell area  42  and a logic area  44  are defined on the semiconductor substrate  100 . According to different designs and functional desires for the electrical circuits, a plurality of active areas  46 , N wells  48  and P wells  50  are formed respectively in the memory cell area  42  and the logic area  44  of the semiconductor substrate  100 . 
         [0011]    A patterned silicon layer  52  is deposited on the N well  48 , the P well  50  and the active area  46 . At this point, a 6T-SRAM cell  60  is defined in the memory cell area  42 , and a logic device  80 , which comprises a complementary metal oxide semiconductor (CMOS), is defined in the logic area  44 . 
         [0012]    As shown in  FIG. 2 , the 6T-SRAM cell  60  comprises pull-up transistor  62 ,  64 , pull-down transistors  66 ,  68 , and access transistors  70 ,  72 . The pull-up transistor  62  and the pull-down transistor  66  comprise a common gate  74 . The pull-up transistor  64  and the pull-down transistor  68  comprise a common gate  76 . The access transistors  70  and  72  comprise a common gate  78 . Additionally, the logic device  80  in the logic area  44  comprises a PMOS transistor  82  with a gate  86  and an NMOS transistor  84  with a gate  88 . 
         [0013]    When the method disclosed in U.S. Patent No. 2003/0032231 A1 is performed to reduce the gate depletion region, the gate formed on the P well  50  is doped with N+ dopant. It should be noted that the pull-up transistor  62  and the pull-down transistor  66  comprise a common gate  74 , and the pull-up transistor  64  and the pull-down transistor  68  comprise a common gate  76 . The portion of the common gates  74  and  76  located on the P well  50  are the gates (which belong to the pull-down transistors  66  and  68 ) doped with N+ dopant. Equally, the portion of the common gates  74  and  76  located on the N well are the gates (which belong to the pull-up transistors  62  and  64 ) are the gates doped with no N+ dopant. 
         [0014]    In an ideal condition, the symmetrical common gates  74  and  76  belonging to the pull-down transistors  66  and  68  respectively have the same N+ dosage. According to some manufacturing or non-manufacturing factors such as the misalignment of the active area, the deviation of the critical dimension of gates, the shift of the mask for the N+ polysilicon doping process, however, the symmetrical common gates  74  and  76  usually possess unsymmetrical N+ dosage. This unsymmetrical dosage causes increasing deviations of the relative saturated current of the drain regions in the pull-up transistors  62  and  64 . The current deviation induces the failure to the memory cell, namely the bit data stored in this memory cell fail. Thereby, N+ polysilicon doping process can reduce the Tox_INV, but it also increases the random single bit (RSB) failure rate in the memory array. 
         [0015]    It would thus be highly desirable to provide a method for fabricating an embedded SRAM with improved RSB failure rate. 
       SUMMARY OF THE INVENTION 
       [0016]    The present invention relates to a method for fabricating an embedded static random access memory (SRAM), and more particularly, to a method for fabricating an embedded SRAM with improved random single bit (RSB) failure rate. 
         [0017]    According to the claims, the present invention provides a method for fabricating an embedded SRAM, the method comprising providing a semiconductor substrate, defining a logic area and a memory cell area on the semiconductor substrate, defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask. 
         [0018]    According to the claims, the present invention further provides a method for fabricating an embedded SRAM, the method comprising providing a semiconductor substrate, the semiconductor substrate defining a logic area and a memory cell area; defining at least an NMOS transistor area and at least a PMOS transistor area in the logic area; defining at least a pull-up transistor area and at least a pull-down transistor area in the memory cell area; forming a patterned mask on the pull-up transistor area, pull-down transistor area in the memory cell area and on the PMOS transistor area in the logic area and exposing the NMOS transistor area in the logic area; performing an N type ion implantation process on the exposed NMOS transistor area in the logic area; and removing the patterned mask. 
         [0019]    According to the claims, the present invention further provides a method for fabricating an embedded SRAM, the method comprising providing a semiconductor substrate, the semiconductor substrate defining a logic area and a memory cell area; defining at least an NMOS transistor area and at least a PMOS transistor area in the logic area; defining at least a pull-up transistor area and at least a pull-down transistor area in the memory cell area; forming a patterned mask on the pull-up transistor area, pull-down transistor area in the memory cell area and the NMOS transistor area in the logic area; exposing the PMOS transistor area in the logic area; performing a P type ion implantation process on the exposed PMOS transistor area in the logic area; and removing the patterned mask. 
         [0020]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  shows a circuit diagram of a typical six transistors static random access memory. 
           [0022]      FIG. 2  shows a schematic plan view of an embedded static ransom access memory in accordance with the prior art. 
           [0023]      FIG. 3  shows a schematic plan view of an embedded static ransom access memory in accordance with the present invention. 
           [0024]      FIG. 4  to  FIG. 6  shows cross-sectional diagrams taken along line AA′, BB′ and CC′ in  FIG. 3 , illustrating a fabricating method for an embedded SRAM in accordance with the first preferred embodiment of the present invention. 
           [0025]      FIG. 7  to  FIG. 10  shows cross-sectional diagrams taken along lines AA′, BB′ and CC′ in  FIG. 3 , illustrating a fabricating method for an embedded SRAM in accordance with the second preferred embodiment of the present invention. 
           [0026]      FIG. 11  to  FIG. 13  shows cross-sectional diagrams taken along lines AA′, BB′ and CC′ in  FIG. 3 , illustrating a fabricating method for an embedded SRAM in accordance with the third preferred embodiment of the present invention. 
           [0027]      FIG. 14  to  FIG. 17  shows cross-sectional diagrams taken along lines AA′, BB′ and CC′ in  FIG. 3 , illustrating a fabricating method for an embedded SRAM in accordance with the fourth preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    Please refer to  FIG. 3 , which shows a schematic plan view of an embedded static ransom access memory in accordance with the present invention. A semiconductor substrate  100  is provided. A memory cell area  102  and a logic area  104  are defined on the semiconductor substrate  100 . According to different designs and functional desires for the electrical circuits, a plurality of active areas  106 , N wells  108  and P wells  110  are formed respectively in the memory cell area  102  and the logic area  104  of the semiconductor substrate  100 . Therefore, P type conductive devices are formed on the N well  108  and N type conductive devices are formed on the P well  110 . The N well  108  may comprise a plurality of P type conductive device areas, on which a P type conductive device is formed. Equally, the P well  110  may comprise a plurality of N type conductive device areas, on which an N type conductive device is formed. Subsequently, a patterned silicon layer  112  is deposited on the N well  108 , the P well  110  and the active areas  106 . Thereafter, a corresponding source/drain implantation process is carried out. At this point, a 6T-SRAM cell  120  is defined in the memory cell area  102 , and a logic device  140 , which may comprise a complementary metal oxide semiconductor (CMOS), is defined in the logic area  104 . 
         [0029]    As shown in  FIG. 3 , the 6T-SRAM cell  120  in the memory cell area  102  comprises pull-up transistors  122 ,  124 , pull-down transistors  126 ,  128  and access transistors  130 ,  132 . The pull-up transistor  122  and the pull-down transistor  126  comprise a common gate  134 . The pull-up transistor  124  and the pull-down transistor  128  comprise a common gate  136 . The access transistors  130  and  132  comprise a common gate  135 . Additionally, the logic device  140  in the logic area  104  comprises a PMOS transistor  142  with a gate  146  and a NMOS transistor  144  with a gate  148 . 
         [0030]      FIG. 4  to  FIG. 6  illustrate a fabricating method for the embedded static ransom access memory shown in  FIG. 3  in accordance with the first preferred embodiment of the present invention. For highlighting the characteristic of the present invention and for clarity of illustration,  FIG. 4  to  FIG. 6  merely show the cross-sectional diagrams taken along lines AA′, BB′ and CC′ in  FIG. 3 . Please refer to  FIG. 4 . A semiconductor substrate  100  is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto. The semiconductor substrate  100  comprises at least an N well  108  and at least a P well  110 , wherein the N well  108  and the P well  110  are isolated by a shallow trench isolation (STI)  138 . Subsequently, a conformal dielectric layer  150  such as silicon oxide component, silicon nitride component or any insulating materials is blanket deposited on the surface of the semiconductor substrate  100 . Then, a silicon layer  152  such as polysilicon, metal silicide or any conductive materials is deposited on the dielectric layer  150 . 
         [0031]    As shown in  FIG. 5 , a patterned mask  154  such as a photoresist is coated on the silicon layer  152  in the memory cell area  102 . The patterned mask is also coated on the silicon layer  152  on the N well  108  in the logic area  104 . Only the silicon layer  152  on the P well  110  in the logic area  104  is exposed. Subsequently, a N+ ion implantation process  156  is carried out on the exposed silicon layer  152 . Thereafter, the patterned mask  154  is removed. According to the first preferred embodiment of this invention, the chemical composition of the N+ ion implantation process  156  may be any N type dopant such as phosphorus, with a dose of about 5E15 ions/cm 2 , at an energy of between about 4 KeV to 5 Kev. 
         [0032]    As shown in  FIG. 6 , an etching process (not shown) is carried out to etch the silicon layer  152  and the dielectric layer  150  thereby forming gates  134 ,  135 ,  146  and  148  as shown in  FIG. 3 . The gates  134 ,  135  and  146  are doped without ions, but the gate  148  is doped with N+ ion. The N+ ion implantation process  156  shown in  FIG. 5  may be carried out after the etching process shown in  FIG. 6 . Those skilled in the art will readily observe that numerous modifications and alterations of the method may be made while retaining the teachings of the invention. 
         [0033]    Finally, spacers are formed on sidewalls of the gate  134 ,  135 ,  146  and  148 . A patterned mask is coated on the N well  108  (not shown). Then an N type source/drain implantation process is carried out thereby forming a source/drain region in the P well  110  of the semiconductor substrate  100  (not shown). Thereafter, the patterned mask is removed. Subsequently, a patterned mask is coated on the P well  110 . A P type source/drain implantation process is carried out thereby forming a source/drain region in the N well  108  of the semiconductor substrate  100  (not shown). Thereafter, the patterned mask is removed. According to the first preferred embodiment of this invention, the chemical specie of the N type source/drain implantation process may be any N type dopant such as phosphorus, with a dose of between about 2E15 to 3E15 ions/cm 2 , at an energy of about 3 KeV. It should be noted that the N type source/drain implantation process might also be carried out on the gate of the pull-down transistor  126 ,  128  or the gate of the access transistor  130 ,  132 . The N type source/drain ion may be treated as a complementary ion, which complements skipping a step of the N+ ion implantation process  156  performed on the gate of each transistor in the memory cell area  102 . 
         [0034]    Please refer to  FIG. 7  to  FIG. 10 , which illustrate another fabricating method for the embedded static ransom access memory shown in  FIG. 3  in accordance with the second preferred embodiment of the present invention. For highlighting the characteristics of the present invention and for clarity of illustration,  FIG. 7  to  FIG. 10  merely show the cross-sectional diagrams taken along lines AA′, BB′ and CC′ in  FIG. 3 . As shown in  FIG. 7 , a semiconductor substrate  100  is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto. The semiconductor substrate  100  comprises at least an N well  108  and at least a P well  110 , wherein the N well  108  and the P well  110  are isolated by a shallow trench isolation (STI)  138 . Subsequently, a conformal dielectric layer  150  such as silicon oxide component, silicon nitride component or any insulating material is blanket deposited on the surface of the semiconductor substrate  100 . Then, a silicon layer  152  such as polysilicon, metal silicide or any conductive material is deposited on the dielectric layer  150 . 
         [0035]    As shown in  FIG. 8 , a patterned mask  154  such as a photoresist is coated on the silicon layer  152  in the memory cell area  102 . The patterned mask is also coated on the silicon layer  152  on the N well  108  in the logic area  104 . Namely, only the silicon layer  152  on the P well  110  in the logic area  104  is exposed. Subsequently, an N+ ion implantation process  156  is carried out on the exposed silicon layer  152 . Thereafter, the patterned mask  154  is removed. According to the second preferred embodiment of this invention, the chemical composition of the N+ ion implantation process  156  may be any N type dopant such as phosphorus, with a dose of about 5E15 ions/cm 2 , at an energy of between about 4 KeV to 5 Kev. 
         [0036]    As shown in  FIG. 9 , a patterned mask  158  such as a photoresist is coated on the silicon layer  152  on the P well  110  in the logic area  104 . Namely, the silicon layer  152  in the memory cell area  102  and the silicon layer  152  on the N well  108  in the logic area  104  are exposed. Subsequently, a P+ ion implantation process  160  is carried out to the exposed silicon layer  152 . Then the patterned mask  158  is removed. As known for a person having ordinary skill in the art, the P+ ion implantation process  160  shown in  FIG. 9  may be carried out before the N+ ion implantation process  156  shown in  FIG. 8 . Those skilled in the art will readily observe that numerous modifications and alterations of the method may be made while retaining the teachings of the invention. 
         [0037]    As shown in  FIG. 10 , an etching process (not shown) is carried out to etch the silicon layer  152  and the dielectric layer  150  thereby forming gates  134 ,  135 ,  146  and  148  as shown in  FIG. 3 . The gates  134 ,  135  and  146  are doped with P+ ions, but the gate  148  is doped with N+ ions. The N+ ion implantation process  156  and P+ ion implantation process  160  shown in  FIGS. 8 and 9  may be carried out after the etching process shown in  FIG. 10 . Those skilled in the sequence of process will readily observe that numerous modifications and alterations of the method may be made while retaining the teachings of the invention. 
         [0038]    Finally, spacers are formed on sidewalls of the gate  134 ,  135 ,  146  and  148 . A patterned mask is coated on the N well  108  (not shown). Then, an N type source/drain implantation process is carried out thereby forming a source/drain region in the P well  110  of the semiconductor substrate  100  (not shown). Thereafter, the patterned mask is removed. Subsequently, a patterned mask is coated on the P well  110 . A P type source/drain implantation process is carried out thereby forming a source/drain region in the N well  108  of the semiconductor substrate  100  (not shown). Thereafter, the patterned mask is removed. According to the preferred embodiment of this invention, the chemical composition of the N type source/drain implantation process may be any N type dopant such as phosphorus, with a dose of between about 2E15 to 3E15 ions/cm 2 , at an energy of about 3 KeV. It should be noted that the N type source/drain implantation process might also be carried out on the gate of the pull-down transistor  126 ,  128  or the gate of the access transistor  130 ,  132 . The N type source/drain ion may be treated like a complementary ion, which complements skipping the step of the N+ ion implantation process  156  performed on the gate of each transistor in the memory cell area  102 . 
         [0039]    Please refer to  FIG. 11  to  FIG. 13 , which illustrate another fabricating method for the embedded static ransom access memory shown in  FIG. 3  in accordance with the third preferred embodiment of the present invention. For highlighting the characteristics of the present invention and for clarity of illustration,  FIG. 11  to  FIG. 13  merely show the cross-sectional diagrams taken along lines AA′, BB′ and CC′ in FIG  3 . As shown in  FIG. 11 , a semiconductor substrate  100  is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto. The semiconductor substrate  100  comprises at least an N well  108  and at least a P well  110 , wherein the N well  108  and the P well  110  are isolated by a shallow trench isolation (STI)  138 . Subsequently, a conformal dielectric layer  150  such as silicon oxide component, silicon nitride component or any insulating material is blanket deposited on the surface of the semiconductor substrate  100 . Then, a silicon layer  152  such as polysilicon, metal silicide or any conductive material is deposited on the dielectric layer  150 . 
         [0040]    As shown in  FIG. 12 , a patterned mask  170  such as a photoresist is coated on the silicon layer  152  in the memory cell area  102 . The patterned mask is also coated on the silicon layer  152  on the P well  110  in the logic area  104 . Namely, only the silicon layer  152  on the N well  108  in the logic area  104  is exposed. Subsequently, a P+ ion implantation process  172  is carried out on the exposed silicon layer  152 . Thereafter, the patterned mask  172  is removed. 
         [0041]    As shown in  FIG. 13 , an etching process (not shown) is carried out to etch the silicon layer  152  and the dielectric layer  150  thereby forming gates  134 ,  135 ,  146  and  148  as shown in  FIG. 3 . The gates  134 ,  135  and  148  are doped without ions, but the gate  146  is doped with P+ ions. The P+ ion implantation process  172  shown in  FIG. 12  may be carried out after the etching process shown in  FIG. 13 . Those skilled in the art will readily observe that numerous modifications and alterations of the method may be made while retaining the teachings of the invention. 
         [0042]    Finally, spacers are formed on sidewalls of the gate  134 ,  135 ,  146  and  148 . A patterned mask is coated on the N well  108  (not shown). Then, an N type source/drain implantation process is carried out thereby forming a source/drain region in the P well  110  of the semiconductor substrate  100  (not shown). Thereafter, the patterned mask is removed. Subsequently, a patterned mask is coated on the P well  110 . A P type source/drain implantation process is carried out thereby forming a source/drain region in the N well  108  of the semiconductor substrate  100  (not shown). Thereafter, the patterned mask is removed. It should be noted that the P type source/drain implantation process might also be carried out on the silicon layer  152  of the pull-up transistors  122 ,  124 . The P type source/drain ion may be treated like a complementary ion, which complements the skipping step of the P+ ion implantation process  172  performed on the gate of each transistor in the memory cell area  102 . 
         [0043]    Please refer to  FIG. 14  to  FIG. 17 , which illustrate a fabricating method for the embedded static ransom access memory shown in  FIG. 3  in accordance with the fourth preferred embodiment of the present invention. For highlighting the characteristics of the present invention and for clarity of illustration,  FIG. 14  to  FIG. 17  merely show the cross-sectional diagrams taken along lines AA′, BB′ and CC′ in  FIG. 3 . As shown in  FIG. 14 , a semiconductor substrate  100  is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto. The semiconductor substrate  100  comprises at least an N well  108  and at least a P well  110 , wherein the N well  108  and the P well  110  are isolated by a shallow trench isolation (STI)  138 . Subsequently, a conformal dielectric layer  150  such as silicon oxide component, silicon nitride component or any insulating material is blanket deposited on the surface of the semiconductor substrate  100 . Then, a silicon layer  152  such as polysilicon, metal silicide or any conductive material is deposited on the dielectric layer  150 . 
         [0044]    As shown in  FIG. 15 , a patterned mask  170  such as a photoresist is coated on the silicon layer  152  in the memory cell area  102 . The patterned mask is also coated on the silicon layer  152  on the P well  110  in the logic area  104 . Namely, only the silicon layer  152  on the N well  108  in the logic area  104  is exposed. Subsequently, a P+ ion implantation process  172  is carried out on the exposed silicon layer  152 . Thereafter, the patterned mask  170  is removed. 
         [0045]    As shown in  FIG. 16 , a patterned mask  174  such as a photoresist is coated on the silicon layer  152  on the N well  108  in the logic area  104 . The silicon layer  152  in the memory cell area  102  and the silicon layer  152  on the P well  110  in the logic area  104  are exposed. Subsequently, an N+ ion implantation process  176  is carried out on the exposed silicon layer  152 . Then the patterned mask  174  is removed. As known by a person having ordinary skill in the art, the N+ ion implantation process  176  shown in  FIG. 16  may be carried out before the P+ ion implantation process  172  shown in  FIG. 15 . Those skilled in the art will readily observe that numerous modifications and alterations of the method may be made while retaining the teachings of the invention. 
         [0046]    As shown in  FIG. 17 , an etching process (not shown) is carried out to etch the silicon layer  152  and the dielectric layer  150  thereby forming gates  134 ,  135 ,  146  and  148  as shown in  FIG. 3 . The gates  134 ,  135  and  148  are doped with N+ ions, and the gate  146  is doped with P+ ions. The P+ ion implantation process  172  and the N+ ion implantation process  176  shown in  FIGS. 15 and 16  may be carried out after the etching process shown in  FIG. 17 . Those skilled in the art will readily observe that numerous modifications and alterations of the method may be made while retaining the teachings of the invention. 
         [0047]    Finally, spacers are formed on sidewalls of the gate  134 ,  135 ,  146  and  148 . A patterned mask is coated on the N well  108  (not shown). Then, an N type source/drain implantation process is carried out thereby forming a source/drain region in the P well  110  of the semiconductor substrate  100  (not shown). Thereafter, the patterned mask is removed. Subsequently, a patterned mask is coated on the P well  110 . A P type source/drain implantation process is carried out thereby forming a source/drain region in the N well  108  of the semiconductor substrate  100  (not shown). It should be noted that the P type source/drain implantation process might also be carried out on the gate of the pull-up transistors  122 ,  124 . The P type source/drain ion may be treated like a complementary ion, which complements skipping the step of the P+ ion implantation process  172  performed on the gate of each transistor in the memory cell area  102 . 
         [0048]    Since the present invention provides a method for fabricating an embedded SRAM by preserving the N+ ion implantation process to the transistors in the logic area in accordance with the prior art, but skips the N+ ion implantation process in the memory cell area, the problem of the symmetrical gate having unsymmetrical concentration will not occur. Additionally, the RSB failure rate of SRAM can be reduced, while still keeping a proper Tox_INV for transistors in the logic area. It should be noted that the method for fabricating an embedded static random access memory in accordance with the present invention is not limited to a 6T-SRAM, and may be applied to any semiconductor manufacture such as 4T-SRAM or inverter. 
         [0049]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.