Abstract:
A nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) structure memory device includes a first insulating layer and a second insulating layer stacked on a channel of a substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and a group IV semiconductor layer, silicon quantum dots, or metal quantum dots interposed between the first dielectric layer and the second dielectric layer. The provided SONSNOS structure memory device improves a programming rate and the capacity of the memory.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a nonvolatile memory. More particularly, the present invention is directed to a silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) memory having an improved storage capacity.  
           [0003]    2. Description of the Related Art  
           [0004]    [0004]FIG. 1 illustrates a sectional view of a conventional flash electrically erasable programmable read only memory (EEPROM) cell. The flash EEPROM, as nonvolatile memory, stores data even in a power off state.  
           [0005]    Referring to FIG. 1, a gate electrode  17  is located on a substrate  11  having a source electrode  13  and a drain electrode  15 . A gate oxide  21 , a floating gate  23 , and an insulating layer  25  are sequentially stacked between the gate electrode  17  and the substrate  11 .  
           [0006]    In general, a flash memory is programmed using hot carriers that are injected from a portion of the substrate  11 , in particular, the channel of electrons that is formed between the source electrode  13  and the drain electrode  15 . A hot carrier injection mechanism includes converting the electrons flowing through the channel from the source to the drain into energetic electrons, which are then injected into the floating gate  23 , under proper voltage conditions. The source electrode  13  and a corresponding portion of the substrate  11  are grounded. A relatively high positive voltage is applied to the gate electrode  17  in order to induce an electric field that attracts the electrons. In addition, a proper positive voltage is applied to the drain electrode  15  to generate hot carriers (electrons). The hot carriers are injected into the floating gate  23  by the electric field of the gate electrode  17 . When a sufficient amount of negative charge is accumulated in the floating gate  23 , the negative potential of the floating gate  23  is increased, causing the net gate voltage to go below the threshold voltage of a field effect transistor (FET), in order to obstruct the electrons from flowing through the channel. The amount of read current is used as a factor to determine whether the flash memory is programmed. The discharge of the floating gate is referred to as “erasing.” Here, erasing is performed by a tunneling mechanism between the floating gate and the substrate. An erasing operation of data from a flash memory is performed by applying a high positive voltage to the source electrode and grounding the gate electrode and the substrate, while floating the drain electrode of a memory cell.  
           [0007]    However, since a flash memory has a disadvantages of low retention, a silicon/oxide/nitride/oxide/silicon (SONOS) memory device may only be used for increasing information storage capacity and improving process performance.  
           [0008]    [0008]FIG. 2 illustrates a sectional view of a conventional SONOS memory cell. Referring to FIG. 2, a gate electrode  37  is formed on a substrate  31  having a source electrode  33  and a drain electrode  35 , and silicon oxide layers  41  and  45  as insulating layers are formed between the substrate  31  and the gate electrode  37 . In addition, a non-conductive dielectric layer  43  for trapping electrons is interposed between the silicon oxide layers  41  and  45 .  
           [0009]    When a SONOS memory having two bits per cell is operated, two bits, i.e., a right bit and a left bit, of the SONOS memory cell use a conventional programming method using hot carriers (electrons); however, each bit reads data at a relatively low gate voltage in different directions. For example, the right bit of the SONOS memory is programmed by applying a programming voltage to the gate electrode or to the drain electrode, while grounding or applying a low voltage to the source electrode. Accordingly, hot carriers are sufficiently accelerated and injected into a region of the non-conductive dielectric layer near the drain electrode. However, the SONOS memory is read by applying a reading voltage to the gate electrode and the source electrode in an opposite direction while grounding or applying a low voltage to the drain electrode. Accordingly, the left bit is programmed and read by exchanging the voltages of the source electrode and the drain electrode. When one bit is programmed, the information in the other bit is maintained.  
           [0010]    The SONOS memory reads data in a reverse direction using a relatively low level of gate voltage so that the drop of the potential across the channel is significantly reduced. Accordingly, the effects of the charges trapped in a local trapping region are increased to enable the programming of the SONOS memory at a high rate. In addition, the SONOS memory is able to improve the erasing mechanism by applying a proper erasing voltage to the gate electrode and the drain electrode of the right bit and the source electrode of the left bit. Furthermore, the SONOS memory can improve the lifespan of the device by preventing the SONOS memory from being worn down in a cycling operation.  
           [0011]    However, regardless of the advantages of the SONOS memory, a memory that has a larger storage capacity than the conventional SONOS memory and that can be programmed at a higher rate than the conventional SONOS memory is required.  
         SUMMARY OF THE INVENTION  
         [0012]    The present invention provides a memory device having a high programming operation rate and a high storage capacity using the advantages of a silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) memory structure.  
           [0013]    According to an embodiment of the present invention, there is provided a silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) structure memory device having a semiconductor substrate including a source electrode and a drain electrode that are separated by a predetermined distance and a channel for moving electrons between the source and drain electrodes, and a gate electrode formed on the semiconductor substrate to control the input of the electrons from the channel into traps of the SONSNOS structure, the SONSNOS structure including a first insulating layer and a second insulating layer stacked on the channel of the substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and a group IV semiconductor layer interposed between the first and the second dielectric layers.  
           [0014]    According to another embodiment of the present invention, there is provided a SONSNOS structure memory device having a semiconductor substrate including a source electrode and a drain electrode that are separated by a predetermined distance and a channel for moving electrons between the source and the drain electrodes, and a gate electrode formed on the semiconductor substrate to control the input of the electrons from the channel into traps of the SONSNOS structure, the SONSNOS structure including a first insulating layer and a second insulating layer stacked on the channel of the substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and nano quantum dots that are formed of a group IV semiconductor material interposed between the first and the second dielectric layers.  
           [0015]    According to yet another embodiment of the present invention, there is provided a SONSNOS structure memory device having a semiconductor substrate including a source electrode and a drain electrode that are separated by a predetermined distance and a channel for moving electrons between the source and the drain electrodes, and a gate electrode formed on the semiconductor substrate to control the input of the electrons from the channel into traps of the SONSNOS structure, the SONSNOS structure including a first insulating layer and a second insulating layer stacked on the channel of the substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and nano quantum dots that are formed of a metal and are interposed between the first and the second dielectric layers.  
           [0016]    According to still another embodiment of the present invention, there is provided a multi-layered SONSNOS structure memory device having a semiconductor substrate including a source electrode and a drain electrode that are separated by a predetermined distance and a channel for moving electrons between the source and the drain electrodes, and a gate electrode formed on the semiconductor substrate to control the input of the electrons from the channel into traps of the SONSNOS structure, the SONSNOS structure including a first insulating layer and a second insulating layer stacked on the channel of the substrate, a plurality of dielectric layers formed on the first insulating layer and under the second insulating layer, and a plurality of group IV semiconductor layers, wherein one of the plurality of group IV semiconductor layers is interposed between adjacent dielectric layers.  
           [0017]    According to an embodiment of the present invention, there is provided a multi-layered SONSNOS structure memory device having a semiconductor substrate including a source electrode and a drain electrode that are separated by a predetermined distance and a channel for moving electrons between the source and the drain electrodes, and a gate electrode formed on the semiconductor substrate to control the input of the electrons from the channel into traps of the SONSNOS structure, the SONSNOS structure including a first insulating layer and a second insulating layer stacked on the channel of the substrate, a plurality of dielectric layers formed on the first insulating layer and under the second insulating layer, and nano quantum dots formed of a group IV semiconductor material interposed between adjacent dielectric layers.  
           [0018]    According to yet still another embodiment of the present invention, there is provided a multi-layered SONSNOS structure memory device having a semiconductor substrate including a source electrode and a drain electrode that are separated by a predetermined distance and a channel for moving electrons between the source and the drain electrodes, and a gate electrode formed on the semiconductor substrate to control the input of the electrons from the channel into traps of the SONSNOS structure, the SONSNOS structure including a first insulating layer and a second insulating layer stacked on the channel of the substrate, a plurality of dielectric layers formed on the first insulating layer and under the second insulating layer, and nano quantum dots formed of a metal interposed between adjacent dielectric layers.  
           [0019]    According to a feature of the present invention, each of the first insulating layer and the second insulating layer of the above embodiments may be formed of a material selected from the group consisting of silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), tantalum oxide (TaO 2 ), and titanium oxide (TiO 2 ).  
           [0020]    According to another feature of the present invention, each of the dielectric layers of the above embodiments may be formed of one of silicon nitride (Si 3 N 4 ) and PZT.  
           [0021]    According to yet another feature of the present invention, the group IV semiconductor material or layer of the above embodiments may be formed of one of silicon (Si) and germanium (Ge).  
           [0022]    According to still another feature of the present invention, the nano quantum dots of the above embodiments may be formed by one of a low pressure chemical vapor deposition (LPCVD) method and a physical method. The physical method of the present invention may include a sputtering method, a vacuum synthesis method, a gas-phase synthesis method, a condensed phase synthesis method, a high deposition rate method using an ionized cluster beam, a consolidation method, a high-speed milling method, a mix-alloy processing method, a deposition method, or a sol-gel method.  
           [0023]    According to a feature of the present invention, the nano quantum dots interposed between the dielectric layers may be made of gold (Au) or aluminum (Al).  
           [0024]    The SONSNOS memory according to the present invention increases the number of trap sites for storing the electrons to improve the programming rate and the capacity of the memory. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    The above and other embodiments, features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:  
         [0026]    [0026]FIG. 1 illustrates a sectional view of a conventional flash memory cell;  
         [0027]    [0027]FIG. 2 illustrates a sectional view of a conventional SONOS memory cell;  
         [0028]    [0028]FIG. 3 illustrates a perspective view of a silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) memory cell according to a first embodiment of the present invention;  
         [0029]    [0029]FIG. 4A illustrates a perspective view of a SONSNOS memory cell according to a second embodiment of the present invention;  
         [0030]    [0030]FIG. 4B illustrates an enlarged view of a circular portion ‘A’ of FIG. 4A;  
         [0031]    [0031]FIG. 5 illustrates a sectional view of a multi-layered SONSNOS memory cell according to a third embodiment of the present invention;  
         [0032]    [0032]FIG. 6 illustrates a sectional view of a multi-layered SONSNOS memory cell according to a fourth embodiment of the present invention; and  
         [0033]    [0033]FIG. 7 is a graph showing changes in flat band voltages in a multi-layered SONSNOS memory cell according to the first embodiment of the present invention and in a conventional SONOS memory cell, in response to changes in gate voltages for recording and erasing information in the memory cells. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0034]    Korean Patent Application No. 2002-62482, filed on Oct. 14, 2002, and entitled: “Nonvolatile Silicon/Oxide/Nitride/Silicon/Nitride/Oxide/Silicon Memory,” is incorporated by reference herein in its entirety.  
         [0035]    The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like numbers refer to like elements throughout. In addition, the term “recording” is used to describe the process of inputting the information (that requires being stored) into the memory cell.  
         [0036]    [0036]FIG. 3 illustrates a perspective view of silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) memory according to the first embodiment of the present invention.  
         [0037]    Referring to FIG. 3, a gate electrode  107  is located on a substrate  101  having a source electrode  103  and a drain electrode  105 , and a multi-layered ONSNO layer is interposed between the substrate  101  and the gate electrode  107  to trap electrons. An electron channel is formed between the source and drain electrodes  103  and  105 . Here, the gate electrode  107  may be formed using a semiconductor, such as silicon (Si), or a metal.  
         [0038]    The ONSNO layer includes first and second oxide layers  111   a  and  111   b , respectively, located on the substrate  101  and under the gate electrode  107 ; first and second nitride layers  113   a  and  113   b , respectively, located on the first oxide layer  111   a  and under the second oxide layer  111   b ; and a silicon layer  115  interposed between the first and second nitride layers  113   a  and  113   b.    
         [0039]    The first and second oxide layers  111   a  and  111   b  may be formed of an insulating material, such as silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), tantalum oxide (TaO 2 ), or titanium oxide (TiO 2 ), and the first and second nitride layers  113   a  and  113   b  may be formed of silicon nitride (Si 3 N 4 ) or substituted by a metal, such as PZT, having a trap site to a trap concentration of greater than 10 12 /cm 2 . In addition, the silicon layer  115  can be substituted by a germanium layer.  
         [0040]    In order to fabricate the SONSNOS memory according to the first embodiment of the present invention, the channel region is formed by lightly implanting ions (not shown) into the substrate  101  and the ONSNO layer is formed on the channel region. Thereafter, a semiconductor or metal layer (for forming the gate electrode  107 ) is deposited on the ONSNO layer; the semiconductor or metal layer and the ONSNO layer are patterned by using a photolithography and an etching process to form the gate electrode  107  pattern above a ONSNO pattern. Ions are implanted using the gate electrode  107  as a mask to form the source and drain electrodes  103  and  105  so that the gate electrode  107  is completed.  
         [0041]    In order to record information that requires being stored into the SONSNOS memory cell, a first positive voltage is applied to the drain electrode  105  while grounding the source electrode  103  or applying a low voltage to the source electrode  103 , and a second positive voltage higher than the first positive voltage is applied to the gate electrode  107 . In this case, an electron channel is formed from the source electrode  103  to the drain electrode  105 , and the electrons moving from the source electrode  103  towards the drain electrode  105  which tunnel through the first oxide layer  111   a  due to the favorable electric field formed by the gate electrode  107  are trapped at the interface between the first nitride layer  113   a  and the silicon layer  115 , the defects in the silicon layer  115 , or at the interface between the silicon layer  115  and the second nitride layer  113   b . According to the first embodiment of the present invention, since the SONSNOS memory cell has more trapping sites for electrons compared to the conventional SONOS memory cell, the SONSNOS memory can secure a larger memory capacity.  
         [0042]    In order to read information from the memory, a third positive voltage that is lower than the first positive voltage is applied to the drain electrode  105 , and the voltage of the gate electrode  107  is set at a fourth voltage that is lower than the third voltage. When a current greater than a reference current flows through between the source and the drain electrodes  103  and  105 , data having a value ‘1’ is assigned, and when a current lower than the reference current flows between the source and the drain electrodes  103  and  105 , data having a value ‘0’ is assigned, based on the polarity of the threshold voltage of the memory cell for reading the stored information.  
         [0043]    In order to erase the memory cell, 0 V is applied to the gate electrode  107 , a high voltage is applied to the source region  103 , and the drain electrode  105  is opened. Accordingly, electrons are withdrawn through the source region  103  so that the information in the memory cell is erased.  
         [0044]    [0044]FIG. 4A illustrates a perspective view of an SONSNOS memory cell according to the second embodiment of the present invention.  
         [0045]    Reference numeral  121  denotes a substrate,  123  denotes a source electrode,  125  denotes a drain electrode,  127  denotes a gate electrode,  131   a  denotes a first oxide layer,  131   b  denotes a second oxide layer,  133   a  denotes a first nitride layer,  133   b  denotes a second nitride layer, and  135  denotes silicon quantum dots. The structure of the SONSNOS memory cell according to the second embodiment of the present invention is similar to the structure of the SONSNOS memory cell according to the first embodiment of the present invention, except for the inclusion of the silicon quantum dots  135  in the place of the silicon layer ( 115  of FIG. 3). Alternately, metal quantum dots may be formed of gold (Au) or aluminum (Al) instead of the silicon quantum dots  135 .  
         [0046]    [0046]FIG. 4B illustrates an enlarged view of a circular portion ‘A’ of FIG. 4A.  
         [0047]    The silicon quantum dots  135  can be substituted by metal quantum dots. The silicon quantum dots  135  or the metal quantum dots can be formed by a physical or a chemical method.  
         [0048]    Examples of the physical method of manufacturing the silicon quantum dots  135  or the metal quantum dots include a sputtering method, a vacuum synthesis method, a gas-phase synthesis method, a condensed phase synthesis method, a high deposition rate method using an ionized cluster beam, a consolidation method, a high-speed milling method, a mix-alloy processing method, a deposition method, and a sol-gel method. An example of the chemical method of manufacturing the silicon quantum dots  135  or the metal quantum dots includes a low-pressure chemical vapor deposition (LPCVD) method.  
         [0049]    Referring back to FIG. 4A, in order to fabricate the SONSNOS memory according to the second embodiment of the present invention, ions are lightly implanted into the substrate  121  to form a channel region (not shown). After the first oxide layer  131   a  and the first nitride layer  133   a  are deposited, the silicon quantum dots  135  are formed on the first nitride layer  133   a  using a physical or chemical method. Thereafter, the second nitride layer  133   b , the second oxide layer  131   b , and a semiconductor layer for forming the gate electrode  127  are deposited on the silicon quantum dots  135 , and the layers are patterned and etched as shown in FIG. 4A. Ions are heavily implanted using the semiconductor layer for the gate electrode  127  as a mask to form the source and drain electrodes  123  and  125 . Accordingly, the source and drain electrodes  123  and  125  and the gate electrode  127  are formed.  
         [0050]    The reading, recording, and erasing operations of the SONSNOS memory cell according to the second embodiment of the present invention are the same as those of the SONSNOS memory cell according to the first embodiment of the present invention. However, the SONSNOS memory cell of the second embodiment of the present invention as compared to that of the first embodiment has a higher memory capacity due to a larger number of electron trap sites in the silicon quantum dots  135  or the metal quantum dots than in the silicon layer  115 .  
         [0051]    SONSNOS memory cells according to a third embodiment and a fourth embodiment of the present invention are formed by multi-layered nitride/silicon/nitride/silicon/nitride (NSNSN) structures instead of single-layered nitride/silicon/nitride (NSN) structures in the SONSNOS memory cells of the first and second embodiments of the present invention. Thus, in the multi-layered structure, the nitride and silicon layers are repeated, thereby increasing the memory capacity of the multi-layered structure.  
         [0052]    [0052]FIG. 5 illustrates a sectional view of a multi-layered SONSNOS memory cell according to the third embodiment of the present invention.  
         [0053]    Referring to FIG. 5, an oxide/nitride/silicon/nitride/silicon/nitride/oxide (ONSNSNO) layer is interposed between a substrate  201  and a gate electrode  207 . A source electrode  203  and a drain electrode  205  are formed in the substrate  201 . The ONSNSNO layer includes first and second oxide layers  211   a  and  211   b , located on the substrate  201  and under the gate electrode  207 , respectively; first and second nitride layers  213   a  and  213   b , arranged on the first oxide layer  211   a  and under the second oxide layer  211   b , respectively; first and second silicon layers  215   a  and  215   b , formed on the first nitride layer  213   a  and under the second nitride layer  213   b , respectively; and a third nitride layer  213   c  interposed between the first and second silicon layers  215   a  and  215   b.    
         [0054]    [0054]FIG. 6 illustrates a sectional view of a multi-layered SONSNOS memory cell according to the fourth embodiment of the present invention.  
         [0055]    Referring to FIG. 6, the multi-layered SONSNOS memory according to the fourth embodiment of the present invention has a structure similar to the structure of the multi-layered SONSNOS memory according to the third embodiment of the present invention, except for the inclusion of the first and second silicon quantum dots  235   a  and  235   b  in the place of the first and second silicon layers ( 215   a  and  215   b  of FIG. 5). Here, first and second metal quantum dots can be formed instead of the first and second silicon quantum dots  235   a  and  235   b . The metal quantum dots may be formed of Au or Al. Layers referenced by numerals  231   a ,  231   b ,  233   a ,  233   b ,  233   c  and  227  in FIG. 6 are similar to the layers  211   a ,  211   b ,  213   a ,  213   b ,  213   c  and  207  in FIG. 5, respectively. Reference numeral  221  denotes a substrate.  
         [0056]    According to the third and fourth embodiments of the present invention, the materials used for the oxide layers, nitride layers and gate electrode may be the same as those used for the respective layers in the first and second embodiments of the present invention.  
         [0057]    The multi-layered SONSNOS memory cells according to the third and fourth embodiments of the present invention shown in FIGS. 5 and 6 have multi-layered trap sites storing electrons to increase the memory storage capacity in comparison to the SONSNOS memories according to the first and second embodiments of the present invention shown in FIGS. 3 and 4A. According to the third and the fourth embodiments of the present invention, the number of alternating nitride layers and silicon layers (or silicon quantum dots) formed between the first and the second oxide layers may be greater than what is actually shown in FIGS. 5 and 6.  
         [0058]    [0058]FIG. 7 is a graph showing changes in flat band voltages of the conventional SONOS memory cell and the SONSNOS memory cell according to the first embodiment of the present invention in response to the changes in gate voltages for recording and erasing information in the memory cells.  
         [0059]    Referring to FIG. 7, the graph f 1  illustrates the changes in the flat band voltage V FB  in response to the changes in the gate voltage for recording information in the conventional SONOS memory. The graph f 2  illustrates the changes in the flat band voltage V FB  in response to the changes in the gate voltage for erasing the conventional SONOS memory cell. The graph g 1  illustrates the changes in the flat band voltage V FB  in response to the changes in the gate voltage for recording information in the SONSNOS memory cell. The graph g 2  illustrates the changes in the flat band voltage V FB  in response to the changes in the gate voltage for erasing the SONSNOS memory cell. At gate voltages V G  under 12 V, the difference between the flat band voltage V FB  of the graph f 1  and the flat band voltage V FB  of the graph f 2  is smaller than the difference between the flat band voltage V FB  of the graph g 1  and the flat band voltage V FB  of the graph g 2 . Accordingly, it may be seen that the performance of the SONSNOS memory according to the first embodiment of the present invention is superior to that of the conventional SONOS memory.  
         [0060]    The SONSNOS memory according to the present invention forms multi-nitride layers and multi-silicon layers and has the structure using silicon quantum dots or metal quantum dots to increase the number of trap sites for storing electrons. Accordingly, the SONSNOS memory can be programmed at a high rate while having an improved information recording capacity.  
         [0061]    Preferred embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. For example, nano-sized particles for forming nano-sized quantum dots can be prepared by various methods that can be used in a single electron transistor.