Abstract:
A phase detection circuit for a phase-locked loop clock recovery system is described which detects the phase difference between an incoming data signal and a clock. The phase detection circuit is configured to generate two phase detection signals, the difference of which is indicative of the phase error between the incoming data and the clock. The phase detection circuit provides improved performance at high frequencies as well as increased flexibility in design and fabrication. The phase detection circuit in one embodiment comprises four type-D flip-flops and two exclusive-OR (XOR) gates. An incoming data signal is fed to one D flip-flop which is enabled off of a rising or positive edge of the clock which in turn feeds its output to a second D flip-flop enabled off of the same clock edge. The same incoming data is also fed to a third D flip-flop which is enabled off of a falling or negative clock edge of the same clock signal. The output of which is in turn fed into a fourth D flip-flop which is enabled off of the same negative edge. The incoming data is also fed to a first XOR gate, along with the output of the first D flip-flop to generate the error phase detection signal. The outputs of the second and fourth D flip-flops are fed into a second XOR gate to generate the reference phase detection signal.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to synchronous data detection, and more specifically, relates to a phase detection circuit that operates in multiple capacities of synchronous data detection.  
         BACKGROUND OF THE INVENTION  
         [0002]    In systems for synchronous transmission of digital data, an information signal is sent from a transmitting unit to a receiving unit. This transmission may take place over serial or parallel data channels. In either case the data is sent in synchronism with a clock signal. In order to save bandwidth, the clock signal is normally not transmitted with the data. Hence, the receiving unit receives the signal at the same clock rate at which it is transmitted.  
           [0003]    Two typical methods for transmitting digital data are baseband and carrier-based transmission. In baseband transmission, a signal is sent directly over a communications link. In carrier-based transmission, the signal is first modulated onto a carrier signal. The modulated carrier signal is then sent to the receiving unit. Common modulation techniques include amplitude modulation (AM), frequency modulation (FM) and phase modulation (PM). When a modulated signal reaches the receiving unit, it is demodulated from the carrier signal to its original form by demodulation circuitry.  
           [0004]    The receiving unit then extracts the clock from the baseband or demodulated carrier-based signal in order to generate a reference by which the data can be interpreted. The method for extracting the clock depends on the type of data format used in the binary signal. Some examples of data formats are non-return to zero (NRZ), return to zero (RZ), biphase and delay-modulation.  
           [0005]    Each format has associated advantages and disadvantages. The RZ format, for instance, contains a spectral line at the clock frequency, which makes clock recovery easy. The NRZ format, conversely, does not necessarily contain a spectral line at the clock frequency and requires additional circuitry for extraction. The NRZ format is advantageous in another way, however, in that it uses half the bandwidth as does the RZ format, which increases the amount of data that can be sent. Hence, data formats are chosen primarily by the needs and allowances of the particular application.  
           [0006]    When using a format such as the NRZ format, the clock must be recovered from the signal. This operation is typically performed by a phase-locked loop (PLL). As depicted in FIG. 1, a PLL  100  typically comprises phase offset detection circuitry  102 , loop filter circuitry  104  and a voltage controlled oscillator (VCO). PLL  100  modulates VCO  106  until it is in phase with the incoming data. The signal generated by VCO  106  is then used as the reference clock to interpret the data signal.  
           [0007]    In order to do this, phase detector circuit  102  detects the phase difference between the incoming data signal and the output of VCO  106  and generates phase detection signals  108 . Phase detection signals  108  have a difference in average value that corresponds to the difference in phase between the incoming data signal and the VCO  106  output. Loop filter  104  converts the difference in average value into an analog voltage signal and filters the signal to remove extraneous noise. An example analog voltage signal  200  is shown in FIG. 2A. Signal  200  is fed to VCO  106 , which slows down or speeds up in response, bringing the output of VCO  106  into phase with the incoming data. Once aligned with the incoming data, the output of VCO  106  is used as the clock signal for interpreting incoming data  
           [0008]    A conventional PLL circuit  300  containing a phase detector  330  is depicted in FIG. 3. A description and operating theory behind circuit  300  can be found in “A Self Correcting Clock Recovery Circuit,”  IEEE Journal of Lightwave Technology , vol. LT-3, pp. 1312-1314, December 1985. Circuit  300  provides a basic means for aligning data and clock phase and comprises phase detector  330 , loop filter  328  and VCO  314 .  
           [0009]    Phase detector  330  comprises two D flip flops  302  and  304  connected in series, and two XOR gates  306  and  308  tied to the input and output of, respectively, flip-flops  302  and  304 . Incoming data is supplied to input node  310  of flip-flop  302  and the input of XOR gate  306 . VCO  314  provides a clock signal to flip-flop  302  at its clock input node  316 . D flip-flop  302  enables its output  312  on every rising edge of this clock signal. Output  312  is connected directly to the input of XOR gates  306  and  308 , as well as to the input to D flip-flop  304 . D flip-flop  304  enables its output  318  on the rising edge of the inverted clock signal provided by VCO  314 . Hence, flip-flops  302  and  304  operate one-half clock cycle apart. The output  318  of D flip-flop  304  is connected to the second input of XOR gate  308 .  
           [0010]    Phase detector  330  produces two phase detection signals by which the phase offset is measured. The phase detection signals, commonly referred to as reference signals, are square pulse signals generated for each transition of the incoming data and having a fixed width equal to half the clock period. The first phase detection signal is output  324  of XOR gate  308 . It is a square pulse signal commonly referred to as a reference signal that is generated for every transition of the incoming data and has a fixed width equal to half the clock period.  
           [0011]    The second phase detection signal is provided by the output  322  of XOR gate  306 . The second phase detection signal is a variable width, square pulse signal with a pulse generated for every transition of the incoming data. The width of this square pulse is dependent upon the position of the rising clock edge in relation to each incoming data transition. This signal is commonly referred to as an error signal. When the rising edge of the clock is in phase with the incoming data, the width of the data pulses produced in the error and reference signals are the same. There is no difference in average value between the signals and correspondingly, the frequency of VCO  314  is not modulated.  
           [0012]    When the rising edge of the clock lags behind the incoming data transition, the data pulse in the error signal decreases in width and has an average value less than the fixed width pulse of the reference signal. As a result, a negative error voltage is produced by loop filter  328  and fed to VCO  314 . When the rising edge of the clock arrives before the incoming data transition, the data pulse in the error signal increases in width and has an average value more than the fixed width pulse of the reference signal. As a result, a positive error voltage is produced by loop filter  328  and fed to VCO  314 .  
           [0013]    As data frequencies rise, the delay, hold and setup times associated with circuit  300  become smaller in order to accommodate shorter data pulse widths and to guard against timing violations. However, phase detector  300  will begin to experience difficulty at these higher frequencies. Properly balancing propagation delays and drive strengths of the D flip-flops  302  and  304  becomes very difficult. In order for the flip-flops to be powerful enough to drive their outputs to satisfy shorter hold and setup times, they must be larger in terms of circuit geometry. But as their size increases, the distance the distance that data signal  310  must travel also increases and creates longer propagation delays. The propagation delays will begin to violate the hold and setup times of the various logic gates and the circuit will fail to recognize data pulses. These pulses are generally referred to as “missed pulses.” Missed pulses can translate into a “dead zone” in the analog voltage signal at the phase detector output, resulting in phase jitter. An analog voltage signal  202  with a dead zone  204  is demonstrated in FIG. 2B.  
           [0014]    Phase jitter is a time variation in the clock edge produced by VCO  106 , in which the edge moves back and forth instantaneously and oscillates around the targeted position. This is undesirable because it results in a dynamically varying amount of time available for logic computations. Phase jitter translates to phase noise in the frequency domain, and can prevent PLL  100  from locking on the correct data frequency. This is a serious problem because it prevent the receiving unit from correctly reading the transmitted data.  
         SUMMARY OF THE INVENTION  
         [0015]    The present invention provides an improved error and reference signal generation method in the phase detection circuitry. This improvement permits high frequency signal phase alignment when incorporated into a phase-locked loop. The improvement also facilitates the balancing of flip-flop size, strength, and density, while maintaining a low propensity for phase jitter at higher frequencies. The improved phase detector system may be broadly conceptualized as a system that uses multiple sections and cascades them in order to prevent timing errors such as missed pulses. This allows the system to operate at higher frequencies without the addition of large amounts of complex circuitry and without the need for highly tuned fabrication processes.  
           [0016]    A phase locked loop that implements an improved phase detector circuit in accordance with the present invention comprises a first section configured to generate a first output signal from an input signal on a first clock edge. The first section also generates a second output signal from the input signal on a second clock edge.  
           [0017]    The first section is coupled to a second section configured to generate a third output signal from the first output signal on the first clock edge. The second section also generates a fourth output signal from the second output signal on the second clock edge. By generating the third and fourth output signals on the same clock edge as used in the first section, as opposed to the opposite clock edge, the circuit effectively doubles the time available for correct signal interpretation. This allows for operation at higher frequencies.  
           [0018]    The input signal and the first output signal can also be coupled to a third section, which is configured to compare the two signals and to generate a first phase detection signal based on the comparison. The first phase detection signal comprises a pulse for every input signal pulse. The width of the first phase detection signal pulse is dependent on the phase difference between the clock signal and the input signal.  
           [0019]    The outputs of the first section and the second section can be coupled to a fourth section, configured to compare the two signals and to generate a second phase detection signal based on the comparison. The second phase detection signal comprises a pulse for every input signal pulse. The width of the second phase detection signal pulse is independent of the phase difference between the clock signal and the input signal, and is used as a reference signal.  
           [0020]    Comparison of the average values of the two phase detection signals provides a method for detecting phase offset between the input signal and the clock signal. This information can be fed to a clock generator that can increase or decrease its frequency to bring the input signal and clock signal into phase.  
           [0021]    Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    The present invention will be described with reference to the accompanying drawings, wherein:  
         [0023]    [0023]FIG. 1 is block diagram of the typical elements of a phase-locked loop clock recovery system.  
         [0024]    [0024]FIG. 2A is a typical filtered analog voltage signal as a function of time that is input to a voltage controlled oscillator circuit.  
         [0025]    [0025]FIG. 2B is a typical filtered analog voltage signal as a function of time where the phase-locked loop is operating at higher frequencies resulting in phase jitter.  
         [0026]    [0026]FIG. 3 is a conventional phase detector circuit used in the phase detector capacity as depicted in FIG. 1.  
         [0027]    [0027]FIG. 4 is a schematic diagram of a preferred embodiment of the present invention as implemented in a phase-locked loop clock recovery system.  
         [0028]    [0028]FIG. 5 is a timing diagram depicting waveforms present at various nodes in response to an arbitrary input data sequence to the system of FIG. 4. 
     
    
       [0029]    The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0030]    The problems described above, in relation to conventional phase detection circuits, are solved by the current invention. The invention accomplishes this by passing the incoming data through cascaded flip-flops operated off of the same clock edge instead of opposite clock edges. This doubles the amount of time available for the second flip-flop to recognize retimed data coming from the first. The second flip-flop will not read the data coming from the first flip-flop until an entire clock period has past, as opposed to conventional circuitry which would read the data at the next immediate clock edge, or only one-half clock period later. This allows the circuit to function with setup and hold times that would cause conventional circuitry to miss pulses, and allows for operation at higher frequencies.  
         [0031]    The addition of a second stage of cascaded flip-flops also provides more freedom to adjust circuit geometry. This is because the outputs of the first stage of flip-flops do not have to drive the additional load created by the reference XOR gate as it would in a conventional circuit. As a result, the first stage of flip-flops can be smaller and therefore more receptive to high speed incoming data, while the second stage can be larger and more capable of driving the output loads. Accordingly, the circuit can meet the needs of a host of different individual applications.  
         [0032]    [0032]FIG. 4 depicts an example phase-locked loop circuit  400  in accordance with one embodiment of the invention. Circuit  400  comprises VCO  436 , loop filter  434  and phase detector  440 , shown encompassed by a dashed line. Incoming data is routed to phase detector  440  through node  402 . Node  402  is connected to the inputs of D flip-flop  404 , D flip-flop  406 , and XOR gate  408 . D flip-flop  404  has one clock input supplied at node  410 , and one output at node  412 . D flip-flop  406  has one clock input supplied by inverter  414  at node  416 , and one output at node  418 . D flip-flop  404  is triggered off of a positive or rising clock edge. D flip-flop  406  is triggered off of the opposite clock edge. This opposite edge is equivalent to the negative or falling clock edge in relation to D flip-flop  404 .  
         [0033]    The output of D flip-flop  404  is tied directly to the input of D flip-flop  420 , as well as the second input of XOR gate  408  at node  412 . D flip-flop  420  has one clock input at node  410 , and one output at node  422 . D flip-flop  420  is triggered off of the same clock edge as D flip-flop  404 .  
         [0034]    The output of D flip-flop  406  is tied directly to the input of D flip-flop  424  at node  418 . D flip-flop  424  has one clock input at node  416 , and one output at node  426 . D flip-flop  424  is triggered off of the same clock edge as D flip-flop  406 , which is the opposite edge in relation to D flip-flops  404  and  420 .  
         [0035]    The outputs of D flip-flop  420  at node  422  and D flip-flop  424  at node  426  are tied to the inputs of XOR gate  428 . The output of this gate at node  430  is commonly referred to as the REFERENCE  442  signal. The REFERENCE  442  signal will be a logic high whenever the inputs to XOR gate  428  are complementary, or opposite logic levels. The output of XOR gate  408  at node  432  is commonly referred to as the ERROR  444  signal and it functions in the same manner as XOR gate  428 , producing a logic high signal whenever the inputs are complementary. These two signals are the phase detection signals for the PLL  400  and would be connected directly to a loop filter  434  in the same manner as depicted in FIG. 2. The net difference between these two signals is reflective of the phase offset between the incoming data and the clock provided by VCO  436 .  
         [0036]    [0036]FIG. 5 is a timing diagram showing the operation of the phase detection circuit  440  in FIG. 4. The diagram displays the typical timing of this circuit at an instance when an incoming data signal is out of phase with the clock. This diagram only shows the various responses of the elements in phase detector  440  as supplied by a clock from VCO  436 , it does not show any clock frequency modulations that would result when this circuit is coupled with a charge pump and a loop filter.  
         [0037]    DATA_IN signal  510  is the signal present at node  402  of FIG. 4, where the received data is input into phase detection circuitry  440 , i.e. D flip-flops  404  and  406 , as well as the first input of XOR gate  408 . CLOCK signal  520  is the clock signal supplied to phase detection circuitry  440  at node  410 . Q_ 412  signal  530  is the signal output from D flip-flop  404  at node  412  and supplied to the input of D flip-flop  406  and the second input of XOR gate  408 . Q_ 422  signal  540  is the signal output from D flip-flop  420  at node  422  and supplied to the first input of XOR gate  420 . CLOCK_INV signal  550  is the inverted clock signal supplied to D flip-flop  406  at node  416 . Q_ 418  signal  560  is the signal output from D flip-flop  406  at node  418  and supplied to the input of D flip-flop  424 . Q_ 426  signal  570  is the signal output from D flip-flop  424  at node  426  and supplied to the second input of XOR gate  420 . ERROR signal  580  is the output signal of XOR gate  408  present at node  432 . REFERENCE signal  590  is the signal output from XOR gate  428  at node  430 .  
         [0038]    The timing diagram displays the voltage levels present at time T 0  after DATA_IN signal  510  has been low for an extended period of time. All non-clock signals will remain low during that time. DATA_IN signal  510  is a received data signal originating from a transmitting source and is relationally independent from the other signals in the diagram. DATA_IN signal  510  shown in FIG. 5 is typical of what a received data signal might look like. DATA_IN signal  510  first transitions from a low to a high between time T 2  and time T 3 . At time T 3 , CLOCK signal  520  transitions from low to high and enables D flip-flop  404  to capture the high level present at it&#39;s input  402 . This high level is passed to the D flip-flop  404  output  412  and creates the low to high transition of Q_ 412   530  which occurs after a delay D 1  from time T 3 . Delay D 1  is the time it takes for the internal D flip-flop  404  circuitry to recognize and pass the input data to it&#39;s output. In addition, D 1  includes the rise time associated with this output due to the parasitic loads created by the surrounding circuitry. As a result of delay D 1 , the input to D flip-flop  420  has a logic low level present when CLOCK  520  transitions at time T 3 . Accordingly, D flip-flop  420  output signal Q_ 422   540  remains at a logic low level.  
         [0039]    DATA_IN  510  transitions from high to low shortly after time T 4 . The next rising edge on CLOCK  520  occurs at time T 5 , at which point D flip-flop  404  is enabled to capture the logic low level DATA_IN  510  signal present at it&#39;s input  402 . This low level signal is passed to the D flip-flop  404  output  412  and creates the high to low transition of Q_ 412   530  after a delay D 2  from time T 5 .  
         [0040]    As a result of delay D 2 , the input to D flip-flop  420  has a logic high signal present when CLOCK  520  transitions at time T 5 , which results in the low to high transition of Q_ 422   540 . This is what allows the improved circuit  440  to operate at higher frequencies with little phase jitter. By clocking D flip-flop  420  on the rising clock edge at time T 5 , as opposed to the preceding falling clock edge at time T 4 , the circuit minimizes the chance that delay D 1  could be so large as to cause D flip-flop  420  to miss the DATA_IN pulse. If D flip-flop  420  was clocked at the prior clock edge at time T 4 , and if delay D 1  extended past time T 4 , D flip-flop  420  would miss the DATA_IN pulse, resulting in a dead zone in the analog voltage signal, which would then translate to undesired phase jitter.  
         [0041]    Upon the next rising edge of CLOCK  520  at time T 7 , DATA_IN  510  is low and therefore Q_ 412   530  remains at a logic low level. D flip-flop  420  is enabled with this low logic level present at it&#39;s input  412  at time T 7 , which results in the high to low transition of Q_ 422   540 . Because DATA_IN  510  remains low through time T 10 , signals Q_ 412   530  and Q_ 422   540  remain low as well.  
         [0042]    After DATA_IN  510  first transitions from low to high, the next rising edge on CLOCK_INV  550  occurs at time T 4 . This enables D flip-flop  406  to capture the high level present at it&#39;s input  402 . This high level is passed to the D flip-flop  406  output  418  and creates the low to high transition of Q_ 418   560 . Note that Q_ 418   560  does not transition precisely at time T 3 , but does so after a delay D 3 . Again, this is accounted for by the time it takes for the internal D flip-flop  406  circuitry to recognize and pass the input data to it&#39;s output. In addition, D 3  includes the rise time associated with this output due to the parasitic loads created by the surrounding circuitry. As a result of delay D 3 , the input to D flip-flop  424  has a logic low level present when CLOCK_INV  550  transitions at time T 4 , which results in the corresponding low signal Q_ 426   570  present at the output  426 .  
         [0043]    DATA_IN  510  transitions from high to low shortly after time T 4 . The next rising edge on CLOCK_INV  550  occurs at time T 6 , at which point D flip-flop  406  is enabled to capture the logic low level DATA_IN  510  signal present at it&#39;s input  402 . This low level is passed to the D flip-flop  406  output  418  and creates the high to low transition of Q_ 418   560 . Again, this does not happen precisely at time T 6 , but after a delay D 4 .  
         [0044]    As a result of delay D 4 , the input to D flip-flop  424  has a logic level high signal present when CLOCK_INV  550  transitions, which results in the low to high transition of Q_ 426   570 . Again this demonstrates how the improved circuit  440  can operate at higher frequencies with little phase jitter. By clocking D flip-flop  424  on the rising clock edge at time T 6 , as opposed to the preceding falling clock edge at time T 5 , the circuit minimizes the chance that delay D 3  could be so large as to cause D flip-flop  424  to miss the DATA_IN pulse. If D flip-flop  424  was clocked at the prior clock edge at time T 5 , and if delay D 3  extended past time T 5 , D flip-flop  424  would miss the DATA_IN pulse, resulting in a dead zone in the analog voltage signal, which would then translate to undesired phase jitter.  
         [0045]    Upon the next rising edge of CLOCK_INV  550  at time T 8 , DATA_IN  510  is low and therefore Q_ 418   560  remains at a logic low level. D flip-flop  424  is enabled when CLOCK_INV  550  transitions at time T 8  with this low logic level present at it&#39;s input  418 , which results in the high to low transition of Q_ 426   570 .  
         [0046]    XOR gate  408  presents a low level at its output  432  whenever both of its inputs are at the same logic level. From time T 0  until shortly after time T 2  where DATA_IN  510  transitions from low to high, the inputs DATA_IN  510  and Q_ 412   530  to XOR gate  408  are low. Therefore the output signal ERROR  580  to XOR gate  408  is low. During the time period between the transition from low to high of DATA_IN  560  and when it transitions to low again, DATA_IN  510  is high and Q_ 412   530  is low. Because the logic levels are different, ERROR  580  transitions from low to high. It remains high until Q_ 412   530  becomes high just after T 3 , at which time ERROR  580  transitions back to low. ERROR  580  transitions to high again in response to DATA_IN  510  transitioning to low after T 4 . Finally, ERROR  580  transitions back to low when Q_ 412   530  transitions to low after time T 5 .  
         [0047]    XOR gate  428  presents a logic low level signal REFERENCE  590  at its output  430  whenever both of its inputs are at the same logic level. From time T 0  until shortly after time T 5  where Q_ 422   540  transitions from low to high, the inputs Q_ 422   540  and Q_ 426   570  to XOR gate  428  are low. Therefore the output signal REFERENCE  590  to XOR gate  428  is low. During the time period between when Q_ 422   540  transitions from low to high and when it transitions back to low, Q_ 422   540  is high and Q_ 426   570  is low. Because the logic levels are different, REFERENCE  590  transitions from low to high. It remains high until Q_ 426   570  becomes high at which time REFERENCE  590  transitions back to low. REFERENCE  590  again transitions to high in response to Q_ 422   540  transitioning to low. Then REFERENCE  590  transitions back to low when Q_ 426   570  transitions to low after time T 8 .  
         [0048]    The ERROR  580  signal and the REFERENCE  590  signal produced between time T 2  and time T 9  each have an average value. If the ERROR  580  signal had an average value equal to the average value of the REFERENCE  590  signal, the ERROR  580  signal would be in a state corresponding to no phase difference between the DATA_IN  510  signal and the CLOCK  520  signal. In the example illustrated in FIG. 5, the average value of the ERROR  580  signal is different from the average value of the REFERENCE  690  signal. This is illustrated by the different pulse widths in the two signals. The ERROR  580  signal is in a state corresponding to the DATA_IN  510  signal being out of phase with the CLOCK  520  signal. The difference between the average values of the two signals is representative of the phase difference between DATA_IN  510  and CLOCK  520  produced by VCO  314 .  
         [0049]    ERROR  580  and REFERENCE  590  signals are fed into a loop filter circuit  434 . Loop filter circuitry  434  then performs two functions. The first is to determine the difference in the average values of the ERROR  580  signal and the REFERENCE  590  signal. The second function is to produce an analog voltage corresponding to that difference in value between the two phase detection signals. The analog voltage is then filtered to remove extraneous or unwanted noise by loop filter circuitry  434 . This analog voltage is then supplied to VCO  436 .  
         [0050]    VCO  436  can be a conventional voltage-controlled oscillator that produces a clock signal at its output. The clock signal is a series of square pulses that operates at a frequency which is dependent on the voltage level supplied to the control voltage input terminal. The filtered voltage is supplied to the control voltage input terminal of VCO  436  and modulates the oscillator frequency up or down accordingly. VCO  436 , for example, can increase its frequency when a positive analog voltage signal is supplied and it can decrease its frequency when a negative analog voltage signal is supplied. The relation between frequency modulation and the analog voltage signal polarity can be chosen arbitrarily to suit the individual application. If the frequency of DATA_IN  510  is stable, the CLK  520  signal will be brought closer to synchronization with each successive incoming pulse, until the two signal are in phase.  
         [0051]    While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention.