Abstract:
Synthesizer and calibrating method utilizing same. The frequency synthesizer modulates input signals comprising a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a frequency synthesizer, and more particularly, to a frequency synthesizer with auto loop gain calibration.  
         [0003]     2. Description of the Related Art  
         [0004]     In current wireless transceivers, a phase locked loop circuit generates carrier signals. The phase locked loop circuit comprises a phase frequency detector, a low pass filter, a voltage control oscillator, and a frequency divider. A reference clock signal and a divided signal output from the divider are applied to the phase frequency detector for outputting an error signal. After filtering by the low pass filter, the output signal is input into the voltage control oscillator for generating a corresponding frequency which is then transmitted as feedback to the frequency divider. Thus the output carrier signal from the phase locked loop circuit occupies a determined frequency.  
         [0005]     The output carrier signal is then modulated by a modulator to generate a modulated signal. A conventional method modulates the oscillator directly. When a wanted carrier frequency is locked by the phase locked loop circuit. A feedback path in the phase locked loop circuit is cut off, and the oscillator is modulated directly. The problem here is that the feedback path must be linked back periodically to prevent over frequency shift. The oscillator must additionally be isolated from surrounding noise to prevent interruptions.  
         [0006]     In U.S. Pat. No. 4,965,531; Relay ,et al. describes a modulating method. In U.S. Pat. No. 4,864,257; Vandergraaf ,et al describes another modulating method. Though the carrier frequency of the mentioned two patents do not cause frequency shifts due to the close loop of the synthesizers, the bandwidth, however is limited. Due to filtering of the high frequency, a distorted frequency is filtered so a frequency is generated, resulting in limited signal.  
         [0007]     In U.S. Pat. No. 4,864,257; Vandergraaf ,et al. describes a circuit to compensate for the limited frequency band. The circuit applies an inverse frequency to compensate for the limited frequency of the phase locked loop circuit. Process and the temperature issues, however, affect the mismatch between the compensated frequency and the limited frequency. Therefore, in U.S. Pat. No. 6,008,703; a digital pre-emphasis filter is employed to lessen the effects of process and temperature. If the channel and the bandwidth increase, however, the number of oscillators and the operational range also increase. Thus, frequency mismatching situation still occurs. In U.S. Pat. No. 6,515,553; Norman ,et al. describes a dual-port modulation, employing a high-pass filter for passing the high frequency portion of a signal and adding the high frequency portion of the signal to a control circuit of an oscillator of a phase locked loop circuit. Thus a full-pass filter can be achieved. Process and the temperature issues still exist, however, and the circuit area of the analog circuit is greater than a digital circuit. Thus increasing costs, integrality and reducing efficiency.  
         [0008]      FIG. 1  shows a conventional frequency synthesizer comprising a pre-emphasis filter  15 . The phase locked loop circuit  1  comprises a phase detector  10 , a low pass filter  11 , a voltage control oscillator  12 , an N/N+1 frequency divider  13  and a β−Δ modulator  14 . The phase locked loop circuit  1  comprises low pass filter  11  for filtering the high frequency portion of the transmitted signal. A pre-emphasis filter  15  is installed for overcoming the low pass filter which filters the high frequency portion of the transmitted signal. The frequency response of the pre-emphasis filter  15  is the inverse of the closed loop frequency response of the synthesizer as shown in  FIG. 2A . A flat frequency response is generated by the two frequency responses.  
         [0009]     A synthesizer, however, operates on a wild frequency band, and different frequency bands of various voltage control oscillators are installed in a synthesizer. Due to the limited size of a circuit area, however, only one pre-emphasis filter is employed, and gain mismatch occurs. Thus the frequency response is different, resulting in signal distortion. As shown in  FIG. 2B  and  FIG. 2C , in  FIG. 2B , bandwidth of the pre-emphasis filter  15  is narrower than the phase locked loop circuit  1  (f c −pre(f c −pll). In  FIG. 2C , bandwidth of pre-filter  15  is wilder than the phase locked loop circuit  1  (f c −pre&gt;f c −pll). The frequency mismatch occurs according to the pre-emphasis filter  15  and the phase locked looped circuit  1 , resulting in transmitted signal distortion (f c −pre(f c −pll)  
       SUMMARY OF THE INVENTION  
       [0010]     Accordingly, an object of the present invention is to provide a synthesizer and an auto calibrating method for same.  
         [0011]     In order to achieve this and other objects of the invention, a frequency synthesizer is provided. The frequency synthesizer of the invention is employed to modulate an input signal which comprises a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.  
         [0012]     The invention additionally provides a method, for auto calibrating a gain of a phase locked loop circuit of a frequency synthesizer, wherein the frequency synthesizer comprises a pre-emphasis filter and a low-pass filter. The frequency response of the phase locked loop circuit is inverse to the frequency response of the pre-emphasis filter. The method comprises the steps of: generating a control signal output from a digital controller to the frequency synthesizer. The auto loop calibration circuit then calculates a corresponding current gain according to the voltage of the control signal. Finally, a current corresponding to the current gain of the phase frequency is output, for matching frequency response of the pre-emphasis filter with the frequency synthesizer.  
         [0013]     A detailed description is given in the following with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0015]      FIG. 1  shows a conventional synthesizer with a pre-emphasis filter;  
         [0016]      FIG. 2A  shows a bandwidth of a pre-emphasis filter equal to the bandwidth of a synthesizer;  
         [0017]      FIG. 2B  shows bandwidth of a pre-emphasis filter narrower than the bandwidth of a synthesizer;  
         [0018]      FIG. 2C  shows bandwidth of a pre-emphasis filter wider than the bandwidth of a synthesizer;  
         [0019]      FIG. 3  is a block circuit diagram in accordance with an embodiment of the invention;  
         [0020]      FIG. 4  shows a detailed circuit of the auto loop gain calibration circuit shown in  FIG. 3 ;  
         [0021]      FIG. 5  shows a detailed circuit of the phase frequency detector shown in  FIG. 3 ;  
         [0022]      FIG. 6  shows another embodiment of the invention;  
         [0023]      FIG. 7  shows a flow chart of an auto loop gain calibration method of the invention;  
         [0024]      FIG. 8  shows a flow chart of the invention; and  
         [0025]      FIG. 9  shows a flow chart of the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]      FIG. 3  is a block circuit diagram in according to an embodiment of the invention. A synthesizer comprises a phase frequency detector  10 , a low pass filter  11 , a voltage control oscillator  12 , a frequency divider  13 , a modulator  2  which comprises a Σ−Δ modulator  14  and a frequency selector  16 , a pre-emphasis filter  15  and an auto loop gain calibration circuit  20 .  
         [0027]     A divided signal output from the frequency divider  13  and a reference clock signal fref are input to the phase frequency detector  10  for transforming a first signal with corresponding current.  
         [0028]     The low pass filter  11  is coupled to the phase frequency detector  10  for filtering the high frequency portion of the first signal output from the phase frequency detector  10  and outputting a control signal.  
         [0029]     The voltage control oscillator  12  coupled to the low pass filter  11  receives and transforms the control signal to a signal with a corresponding frequency (first frequency).  
         [0030]     The frequency divider  13  controlled by the Σ−Δ modulator  14  is set in a feedback path for dividing the frequency applied from the voltage control oscillator  12  and outputting the divided signal to the phase frequency detector  10 .  
         [0031]     The pre-emphasis filter  15  receives an input signal such as, a set of digital modulated data, for example, for filtering and transmission to a carrier frequency from a frequency selector  16  to the Σ−Δ modulator  14 .  
         [0032]     The auto loop gain calibration circuit  20  is coupled to the output of the low pass filer circuit  11  for receiving the control signal Vc output from the low pass filter  11 . When the frequency is locked by the phase locked loop circuit  1 , a corresponding current gain is calculated by the auto loop gain calibration circuit  20  according to the voltage of the control signal Vc for compensating the gain of voltage control oscillator  12 . The corresponding current gain is output to the phase frequency detector  10  for controlling the current of the output first signal, such that the frequency response of the pre-filter  15  matches the frequency response of phase locked loop circuit  1 .  
         [0033]     The phase locked loop circuit  1  in  FIG. 3  is a closed loop circuit. The phase frequency detector  10 , low pass filter  11 , the voltage control oscillator  12 , and frequency divider  13  form an open loop circuit. The equation (1) between the close loop and the open loop is given follows:  
               CL   ⁡     (   S   )       =       OL   ⁡     (   S   )         1   +       OL   ⁡     (   S   )       N                 equation   ⁢           ⁢     (   1   )               
 
         [0034]     Wherein function CL(S) represents the closed loop gain. OL(S) represents the open loop gain. N is the divisor of the divider  13 .  
         [0035]     In The equation (1), wherein  
               OL   ⁡     (   S   )       =       K   ⁢           ⁢     Φ   ·     K   VCO     ·     Z   ⁡     (   S   )             N   ·   S               equation   ⁢           ⁢     (   2   )               
 
         [0036]     Wherein kφ is a gain of the phase frequency detector  10 , kvco is a gain of the voltage control oscillator  12 . Z(s) is the impedance of the low pass filter  11 . In the embodiment, z(s) is controlled to be a constant value.  
         [0037]     According to the equation (2), since impedance Z(s) is a constant, the factors which affect the mismatch are the current gain kφ, the gain kvco, and N.  
         [0038]     As described above, because there is only one set of frequency response installed in a pre-emphasis filter  15 , when a voltage control oscillator  12  is switched to a different frequency band, different gain of the voltage control oscillator 12 kvco is generated. Thus mismatch between pre-emphasis filter  15  and the phase locked loop occurs. The compensation method is to change the current gain kφ, as shown in the fallowing equation (3): 
 
 kφ,prexkvco,pre/N,pre=kφ,pll×kvco,pll/N,pll   (3) 
 
         [0039]     In practice, a voltage of a control signal of a low pass filter  11  is picked by the auto loop gain calibration  20 , and then, according to the voltage value, a corresponding gain kvco,pll of a voltage control oscillator  12  is determined by the auto loop gain calibration  20  after the frequency is locked. Then the current gain kφ,pll of the phase frequency detector  10  is calculated by inserting values of a fixed current gain kφ,pre of pre-emphasis filter  15 , and a fixed gain of voltage control oscillator 12 kvco,pre. The current of the phase frequency detector  10  is controlled by the calculated current gain kφ,pll.  
         [0040]      FIG. 4  shows a detailed circuit of the auto loop gain calibration circuit  20  shown in  FIG. 3 . Other components such as phase frequency detector  10 , low pass filter  11 , and voltage control oscillator  12  etc in  FIG. 4  are the same as  FIG. 3 , thus description thereof is omitted.  
         [0041]     The auto loop gain calibration circuit  20  comprises an analog digital converter  200  (ADC), a controller  201  and a gain lookup table  202 . The analog digital converter  200  converts the analog control signal to a corresponding digital signal. The controller  201  is coupled to the analog digital converter  200  for receiving the digital signal. After the digital signal is received, the controller  201  searches the gain lookup table  202  for the gain kvco,pll of the voltage control oscillator  12  according to the digital signal. The current gain kφ, all of the phase frequency detector  10  is then calculated by inserting values of fixed current gain kφ,pre of pre-emphasis filter  15  a fixed gain of voltage control oscillator 12 kvco,pre and the found gain of the voltage control oscillator 12 kvco,pll.  
         [0042]      FIG. 5  shows a detailed circuit of the phase frequency detector  10  shown in  FIG. 3 . The phase frequency detector  10  includes a phase detector  100  and a charge pump  103 . Wherein the reference clock signal fref and the divided signal is applied to the phase detector  100  for outputting an error signal from output terminals  101  or  102 , to control switch S 1  or switch S 2 , each of the switches S c  or S d  are coupled to the current sources 2 0 I 1 ˜2 n I 1  or 2 0 I 2 ˜2 n I 2 , the switches S d  are controlled by the n+1 bit digital signal gain_control_sink[n:0] to be in a on or off state. The switches Sc are controlled by the n+1 bit digital signal gain_control_source[n:0] to be in a on or off state.  
         [0043]     In practice, an error signal is output from output terminal  101  or  102  to turn on switches S 1  or S 2 , the current sum is determined by the number of the turned on switches S c  or S d . The determined current Is is output to the low pass filter  11 .  
         [0044]      FIG. 6  shows another embodiment of the invention, wherein the elements are identical to the previous embodiment and further description is omitted herein. The main difference is that the auto loop gain calibration circuit  20 ′ comprises an analog digital converter  200  and a controller  201 ′, wherein an analog signal is input to the analog/digital converter  200  for converting to a digital signal. A first voltage is acquired by the controller  201 ′ when a signal is locked by the phase loop locked circuit  1 . Then, an offset frequency Δf is input to the adder  18  of the modulator  2  for modulating the input signal. Then a second voltage is acquired by the controller  201 ′. Finally, a corresponding current gain kφ,pll is calculated by the offset frequency Δf and the difference between the second voltage and the first voltage V 2 −V 1 . The gain kvco of the voltage control oscillator  12  is then calculated by inserting values of offset frequency Δf and the difference between the second voltage and the first voltage V 2 −V 1  to the following equation (4). The current gain kφ,pll of the frequency phase detector  10  can then be calculated by inserting the equation (3).  
               k   vco     =       Δ   ⁢           ⁢   f         V   2     -     V   1                 equation   ⁢           ⁢     (   4   )                 
         [0045]     Wherein Δf is the offset frequency, and V 2 −V 1  is the difference between the second voltage and the first voltage V 2 −V 1 . When the offset voltage Δf and the voltage difference V 2 −V 1  is very small, kvco=df/dv.  
         [0046]     An auto loop gain calibration method of the invention is shown in  FIG. 7 , comprises the following steps:  
         [0047]     In step S 1 , a voltage value of a control signal is acquired by an auto loop gain calibration circuit, wherein the control signal is output from the low pass filter. In Step S 2 , a current gain kφ,pll corresponding to the control signal is calculated by the voltage value of the control signal. Finally, in step S 3 , the current of the phase frequency detector is controlled by the controller according to the current gain. The corresponding current is output from the phase frequency detector for matching with the frequency of the pre filter matching the frequency of the frequency divider.  
         [0048]     Step S 2  shown  FIG. 8  further comprises the following steps.  
         [0049]     In step S 2.1 , a voltage value of the control signal is converted to a digital value by the analog/digital converter. In step S 2.2 , a corresponding gain kvco,pll of the voltage control oscillator is searched out in a gain lookup table by a controller. Finally, in S 2.3 , the current gain kφ,pll of the control signal is calculated by inserting values of fixed current gain kφ,pre of pre-emphasis filter  15 , a fixed gain kvco,pre of voltage control oscillator  12  and the found gain kvco,pll of the voltage control oscillator  12  into equation (3).  
         [0050]      FIG. 9  shows another embodiment of the  FIG. 7 , which comprises the following steps.  
         [0051]     First, in step S 2.4 , a first voltage output from the low pass filter is acquired by the controller. Then, in step S 2.5 , an offset frequency Δf is input, and a second voltage is then acquired from the low pass filter. In step S 2.6 , a gain kvco,pll of the voltage control oscillator is calculated by inserting values of offset frequency and the difference between the second voltage and the first voltage V 2 −V 1 . Finally, in step S 2.7 , the current gain kφ,pll of the control signal is calculated by inserting the values of fixed current gain kφ,pre of pre-emphasis filter  15 , a fixed gain kvco,pre of voltage control oscillator  12  and the calculated gain kvco,pll of the voltage control oscillator  12  into equation (3).  
         [0052]     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.