Abstract:
A source line driver for a flash memory includes a plurality of source driving units and a control circuit to drive a plurality of source lines. Each source line is coupled to memory cells in a row. Each source driving unit drives the corresponding source line and is coupled to the control circuit at a common node. The control circuit is coupled between the common node. The control circuit is coupled between the common node and a ground line. When any memory cell is assigned to execute a program operation, the control circuit isolates the common node and the ground. When the memory cells are not assigned to execute the program operation, the control circuit couples the common node to the ground line.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a source line driver, and in particular to a source line driver for a flash memory capable of driving sources lines while occupying a relatively small area of the flash memory. 
   2. Description of the Related Art 
     FIG. 1  is a basic structure diagram of a conventional flash memory. The flash memory is composed of a plurality of memory cells for memorizing and other control components. The memory cells  10   0,0  . . .  10   2n−1,m−1  are disposed in an array and constitute a memory array  10 . Each memory cell (as labeled “ 101 ” in  FIG. 1 ) has a memory transistor to store logic level “ 1 ” or “ 0 ”. In the memory array  10 , each word line selects the memory cells in a column. When receiving a row address signal, a word line decoder  11  enables one word line to select the memory cells in the corresponding row. When receiving a column address signal, a bit line decoder  12  drives one bit line to select the memory cells in the corresponding column. According to the row address signal and the column address signal, a selected memory cell can execute read, program, and erase operations. Moreover, as shown in  FIG. 1 , source lines SL 1   0 . . . SL 1   n−1  are coupled to a source line driver  13  and extend therefrom in the direction of the word line decoder  11 . Each source line applies voltage to the memory cells in two corresponding rows. For example, the memory cells  10   0,0  . . .  10   0,m−1  and  10   1,0  . . .  10   1,m−1  are coupled to the source line SL 1   0  and receive voltage therefrom. In the read, program or erase operations, different states of the source line driver  13 . 
     FIG. 2  shows an equivalent circuit of the memory units of the conventional flash memory, the memory cells  10   0,0  and  10   0,1  are taken as an example. Control gates of memory cells  10   0,0  and  10   0,1  are respectively coupled to the word lines WL 1   0  and WK 1   1 , both drain terminals thereof are coupled to the bit line BL 1   0  and WL 1   1 , both drain terminals thereof terminals thereof are coupled to the source line SL 1   0 . The source line SL 1   0  applies voltage to the memory cells  10   0,0  and  10   0,1 . 
     FIG. 3  is a schematic diagram of the conventional source line driver of the conventional flash memory. As shown in  FIG. 3 , the source line driver  13  comprises a plurality of source line driving units, and one source line driving unit controls one source line. Each source line driving unit comprises three portions. 
   Taking the source line driving unit  13   0  as an example, the source line driving unit  13   0  controls the source line SL 1   0  applying voltage to the memory cells  10   0,0  . . .  10   0,m−1  and  10   1,0  . . .  10   1,m−1 . The source line driving unit  13   0  comprises a first circuit  131   0  having transistor N 13   0 , N 14   0 , and N 15   0 , a second circuit  132   0 , serving as a latch circuit, having inverter I 11   0  and I 12   0 , and a third circuit  133   0  having transistor N 11   0  and N 12   0 . Because a gate of the transistor N 11   0  is coupled to a voltage source VDD 1  having a VDD, the transistor N 11   0  remains turned on. VDD is the operating voltage of the core circuit, which can be 3.3 V, 2.5 V, or 1.8 V in a semiconductor manufacture process. Also VDD is not the program voltage having a value between 10 V to 12 V. 
   In read and erase operations N 13   0  turns off due to P 1  having GND level. When word lines are not selected during program operation, the transistors N 14   0  and N 15   0  are turned off. A gate of the transistor N 12   0  receives a signal PL 1  having a VDD to turn on the transistor N 12   0 . Therefore, the source line SL 1   0  is coupled to a ground GND 1  through the transistors N 11   0  and N 12   0 . In read operation, in order to read data, the gate of the transistor N 12   0  receives the signal PL 1  having a VDD to turn on the transistor N 12   0 , the source line SL 1   0  is coupled to the ground GND 1  through the transistors N 11   0  and N 12   0 . 
   Furthermore, where the memory cell  10   0,0  is assigned to execute program operation, the word line WL 1   0  and the signal P 1  are at a VDD to respectively turn on the transistors N 15   0  and N 13   0 . A voltage level of an inverting source line SLB 1   0  is pulled down to the low voltage level of the ground GND 1  by the transistor N 15   0  and N 13   0  within the first circuit  131   0 . The source line SL 1   0  is latched at a high voltage level of a voltage source VPP 1  through the latch circuit comprising the inverter I 11   0  and I 12   0 . In addition, because the gate of the transistor N 12   0  receives the signal PL 1  having a GND, the turned-off transistor N 12   0  isolates the ground GND 1  and the source line SL 1   0 . Therefore, the source line SL 1   0  is at a high voltage level and the memory cell  10   0,0  can execute program operation. 
   As described above, each third circuit within the source line driving units comprises two transistors for controlling the voltage level of the corresponding source line and further controlling the corresponding memory cells. 
   Generally, the total size of the third circuits is proportional to the number of data input/output ports. That is, the size of the flash memory increases along with the increase of the number of data input/output ports. Recently, flash memory used for Field Programmable Gate Array (FPGA) applications require very wide data input/output buses. The cascade transistor structure of the third circuits within the source line driving units occupies a large area in a conventional flash memory. 
   SUMMARY OF THE INVENTION 
   Accordingly, an object of the present invention is to provide a source line driver for a flash memory. 
   According to the object described above, the present invention provides a source line driver for a flash memory to drive a plurality of source lines. Each source line is coupled to memory cells in a row. The source line driver comprises a plurality of source driving units and a control circuit. Each source driving units drives the corresponding source line and comprises a latch circuit, a first circuit and a second circuit. 
   The latch circuit is coupled between the corresponding source line and a corresponding inverting source line. The first circuit couples the corresponding source line to a common node when any memory cell is assigned to execute a program operation. The second circuit pulls down a voltage level of the corresponding inverting source line to a ground level when any memory cell is assigned to execute the program operation. 
   The control circuit is coupled between the common node and a ground line. When any memory cell is assigned to execute the program operation, the control circuit isolates the common node and the ground line. When none of the memory cells is assigned to execute program operation, the control circuit couples the common node to the ground line. 
   A detailed description is given in the following embodiments with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention can be more fully understood by reading the subsequent detailed description and examples wit references made to the accompanying drawings, wherein: 
       FIG. 1  is a basic structural diagram of a conventional flash memory. 
       FIG. 2  shows an equivalent circuit of the memory units of the conventional flesh memory. 
       FIG. 3  is a schematic diagram of the source line driver of the conventional flash memory. 
       FIG. 4  is a schematic diagram of a flash memory according to one embodiment of the present invention. 
       FIG. 5  is a schematic diagram of the source line driver according to one embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 4  is a schematic diagram of a flash memory of the present invention. The flash memory comprises a memory array  20 , a word line decoder  21 , a bit line decoder  22 , and a source line driver  23 . A plurality of word lines WL 2   0  to WL 2   n−1  and bit lines BL 2   0  to BL 2   m−1  are interlaced forming the memory array  20 . The source line driver  23  controls a plurality of source lines SL 2   0  to SL 2   n−1  and applies voltage to memory cells in two corresponding rows through the corresponding source line. 
     FIG. 5  is a schematic diagram of the source line driver of the present invention. The source line driver  23  comprises a plurality of source line driving units  23   0  to  23   n−1  and a control circuit  231 . The control circuit  231  comprises a transistor N 22  having a drain coupled to a ground GND 2  and a gate receiving a signal PL 2 . Referring to  FIGS. 4 and 5 , one source line driving unit controls one source line and applies voltage to memory cells in two corresponding rows through the corresponding source line. Each source line driving unit comprises three portions. 
   For example, the source line driving unit  23   0  controls the source line SL 2   0  coupled to memory cells  20   0,0  to  20   0,m−1  and  20   1,0  to  20   1,m−1 . In the source line driving unit  23   0 , a second circuit  231   0  comprises transistors N 23   0 , N 24   0  and N 25   0 , a latch circuit  232   0  comprises inverters I 21   0  and I 22   0 , and a first circuit  233   0  comprises transistors N 21   0 . In the second circuit  231   0 , a gate of the transistor N 25   0  is coupled to the word line WL 2   1  and a source thereof is coupled to the ground GND 2 ; a gate of the transistor N 24   0  receives a program signal P 2 , a source thereof is coupled to drains of the transistors N 24   0  and N 25   0 , and a drain thereof is coupled to an inverting source line SLB 2   0 . In the latch circuit  232   0 , the inverters I 21   0  and I 22   0  operate at the voltage applied by voltage sources VPP 2  and ground GND 2 , an input terminal of the inverters I 22   0  are coupled to the inverting source line SLB 2   0 , and an output terminal of the inverters I 21   0  and an input terminal of the inverters I 22   0  are coupled to the source line SL 2   0 . In the first circuit  233   0 , a gate of the transistor N 21   0  receives a signal A 0 , a source thereof is coupled to a drain of the transistor N 22 , and a drain thereof is coupled to the source line SL 2   0 . It is noted that the program signal P 2  and the signal PL 2  are opposite to each other. 
   The source line driving unit  231   1  controls the source line SL 2   1  and applies voltage to the memory cells  20   2,0  to  20   2,m−1  and  20   3,0  to  20   3,m−1  through the source line SL 2   1 . In the source line driving unit  23   1 , a second circuit  231   1  comprises transistors N 23   1 , N 24   1  and N 25   1 , a latch circuit  232   1  comprises inverters I 21   1  and I 22   1 , and a first circuit  233   1  comprises transistors N 21   1 . The structures of the circuits  231   1  to  233   1 . The structures circuits  231   0  to  233   0 . 
   In the embodiment of the present invention, all the transistors within the source line driving units  23   0  to  23   n−1  are N-type MOS transistors. Moreover, the circuitry structures of the source line driving units  23   3  to  23   n−1  are same as that of the source line driving unit  23   1 . 
   The source line driving units  23   0  and  23   1  are taken as an example to describe the embodiment of the present invention. 
   In the read and erase operations, the program signal is at a GND to turn off the transistors N 23   0  and  23   1 , the signal PL 2  is substantially at a VDD to turn on the transistor N 22 . Besides VDD, the voltage of the signal PL 2  can be any value approximate to VDD as long as that value is sufficient to turn on the transistor N 22 . Both the signals A 0  and A 1  are substantially at a VDD to respectively turn on the transistors N 21   0  and N 21   1 . Therefore, the source line is coupled to the ground GND 2  through the transistors N 21   0  and N 22 , and at the same time, any of the memory cells  20   0,0  to  20   0,m−1 ,  20   1,0  to  20   1,m−1 ,  20   2,0  to  20   2,m−1 , and  20   3,0  to  20   3,m−1  can be selected to execute read or erase operations by the word lines WL 2   0  to WL 2   3 . 
   In program operation, the program signal P 2  is substantially at a VDD and the signal PL 2  is at a GND, resulting in the transistors N 23   0  to N 23   n−1  are turned on and the transistor N 22  is turned off. It is assumed that any of the memory cells  20   0,0  to  20   0,m−1  and  20   1,0  to  20   1,m−1 , controlled by the source line driving unit  23   0 , are assigned to execute program operation, such as the memory cells  20   0,0 . The word line WL 2   0  is at a VDD level to turn on the transistor N 25   0 , and the word line WL 2   1  is at a low voltage level to turn off the transistor N 24   0 . A voltage level of the inverting source line SLB 2   0  is pulled down to a low voltage level of the ground GND 2 . The source line SL 2   0  is latched at the high voltage level of the voltage source VPP 2  through the latch circuit  232   0 . Furthermore, because the memory cell  20   0,0  controlled by the source line driving unit  23   0  is assigned to execute program operation, the signal A 0  input to the source line driving unit  23   0  is substantially at a VDD to turn on the transistor N 21   0  applying an appropriate voltage drop to the source line SL 2   0 . 
   However, because the memory cell  20   0,0  is not controlled by the source line driving unit  23   0 , the word lines WL 2   2  and WL 2   3  are at the GND to turn off the transistors N 24   1  and N 25   1  and the signal A 1  is at the GND to turn off the transistor N 21   1 . The source line SL 2   1  is latched at the low voltage level of the ground GND 2  through the latch circuit  232   1 . 
   As described above, the first circuit within each source line driving unit of the present invention comprises one transistor. In read and erase operation, the signals A 0  to A n−1  are substantially at VDD to respectively turn on the transistors N 21   0  to N 21   n−1  and the signal PL 2  is substantially at a VDD to turn on the transistor N 22 . Thus, the source lines SL 2   0  to SL 2   n−1  are coupled to the ground GND 2  through the turned-on transistor N 21   0  to N 21   n−1  and N 22 . 
   In program operation, the signal PL 2  is at a GND to turn off the transistor N 22 . In the source line driving unit corresponding to the memory cell assigned to execute program operation, the transistor, whose gate receives a signal substantially equal to a VDD, within the first circuit is turned on. However, in other source line driving units, the transistors, whose gates receive signals having a GND, within the first circuits are turned off. Thus, the source line corresponding to the memory cell assigned to execute program operation is isolated from the ground GND 2  by the turned-off transistors N 22  and the turned-off transistor within the first circuit. 
   Table 1 shows the voltage levels of the signals A 0  to A n−1 , PL 2 , and P 2  in different operations. A label “ 1 ” substantially represents the VDD and a label “ 0 ” the GND. As shown in Table 1, in read and erase operations, the signals A 0  to A n−1  are substantially at the VDD “ 1 ” and the signal PL 2  is substantially also at the VDD “ 1  ”. Thus, the transistors N 22  and N 21   0  to N 21   n−1  are turned on. In program operation, it is assumed that the memory cell  20   0,0  is assigned to execute program, the signal A 0  is substantially at the VDD “ 1 ” and the signals PL 2  and A 1  to A n−1  are at GND “ 0 ”. Thus, the transistor N 21   0  is turned on, and the transistors N 22  N 21   1  to N 21   n−1  are turned on. 
   It is assumed that size of each transistor within the present invention and the conventional technology is S. Sizes of second circuits of the present invention and the conventional technology are the same, and the size of each latch circuit of the present invention is the same as size of each first circuit of the conventional technology. Considering only the sizes of the first circuits  233   0  to  233   n−1  of the present invention and the sizes of the third circuits  133   0  to  133   n−1  of the conventional technology, size of the source driver  23  of the present invention is (n+1) * S while the size of the source driver  13  of the conventional technology is 2 * n * S. Therefore, the present invention provides a small source line driver reducing occupied space in the flash memory. 
   
     
       
             
             
             
             
             
           
         
             
                 
               TABLE 1 
             
             
                 
                 
             
             
                 
               operation 
                 
                 
                 
             
             
                 
               signal 
               erase 
               read 
               program 
             
             
                 
                 
             
           
           
             
                 
               A 0   
               1 
               1 
               1 
             
             
                 
               A 1   
               1 
               1 
               0 
             
             
                 
               A 2   
               1 
               1 
               0 
             
             
                 
               . 
               . 
               . 
               . 
             
             
                 
               . 
               . 
               . 
               . 
             
             
                 
               . 
               . 
               . 
               . 
             
             
                 
               A 2n−1   
               1 
               1 
               0 
             
             
                 
               PL2 
               1 
               1 
               0 
             
             
                 
               P2 
               0 
               0 
               1 
             
             
                 
                 
             
             
                 
               It is assumed that the memory cell 20 0,0  is assigned to execute program. 
             
           
        
       
     
   
   While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.