Abstract:
A technique to programmably establish a plurality of graphic buffers in a computer system having a banked system memory architecture includes obtaining a first indication representing a performance characteristic of the computer system, obtaining a second indication representing a size of the system memory, selecting a plurality of graphic buffer designations based on the first and second indications, and establishing one graphic buffer for each of the selected graphic buffer designations in system memory, where at least two of the plurality of graphic buffers are located in different banks of the system memory. In some implementations, the performance characteristic may indicate whether the computer system is designated to process and display two-dimensional graphics or three-dimensional graphics.

Description:
RELATED APPLICATIONS 
     This application is related to U.S. Ser. No. 09/239,633, filed on Jan. 29, 1999. 
    
    
     BACKGROUND 
     The invention relates generally to computer system memory architectures and, more particularly, to a programmable memory architecture that incorporates graphic buffer storage within system memory. 
     Referring to FIG. 1, conventional computer system  100  providing graphics capability may include central processing unit (CPU)  102 , bridge circuit  104 , and bridge circuit  106 . Bridge circuit  104  provides host interface (HI)  108 , system bus interface (SBI)  110 , graphics port (GP)  112 , and memory interface (MI)  114 . Bridge circuit  106  couples system bus  116  to secondary bus  118 . 
     Graphics controller (GK)  120  uses graphics memory (G-MEMORY)  122  to control the operation of graphics device  124 . For example, graphics controller  120  may use graphics memory  122  to store data needed to render a three-dimensional (3D) image on graphics device  124 . Graphics memory  122  is often dual port random access memory and is typically incorporated within, or as part of, graphics controller  120 . 
     System memory (SYS-MEMORY)  126 , in contrast to graphics memory  122 , is typically standard dynamic random access memory (DRAM). System memory  126  may be used by CPU  102  during the execution of computer programs (user application programs and system software, for example). 
     In some computer systems, graphics port  112  and graphics controller  120  conform to the accelerated graphics port (AGP) specification. (See the “Accelerated Graphics Port Interface Specification,” Revision 2.0, May 1998.) In such systems, graphics controller  120  may use a portion of system memory  126  (hereinafter, AGP memory) to store an image&#39;s texture information. For example, a fully compliant AGP controller may access system memory  126  directly to obtain an image&#39;s texture information. 
     Notwithstanding AGP memory, computer system  100  generally does not allow graphics controller  120  to use system memory  126 . Nor does computer system  100  generally allow graphics memory  122  to be used for general system needs. Further, system  100  has a relatively high pin count because separate memories are used for system memory  126  and graphics memory  122 . The high pin count, in turn, may make it more difficult to economically manufacture computer system  100 . In addition, the use of separate graphics controller and memory controllers may also result in the duplication of bus interfaces, memory control and so forth. Thus, it would be beneficial to provide a mechanism by which system memory may be effectively used as graphics memory. 
     SUMMARY 
     In one embodiment, the invention provides a program storage device having instructions stored thereon for causing a programmable control device to establish a plurality of graphic buffers in a computer system having a banked system memory architecture. The instructions include instructions to obtain a first indication representing a performance characteristic of the computer system, obtain a second indication representing a size of the system memory, select a plurality of graphic buffer designations based on the first and second indications, and establish one graphic buffer for each of the selected graphic buffer designations in system memory, where at least two of the plurality of graphic buffers are located in different banks of the system memory. 
     In another embodiment, the invention provides a system comprising a graphics controller, a system memory having a plurality of memory banks, and a plurality of graphic buffers accessible by the graphics controller allocated in system memory, where at least two of the plurality of graphic buffers are located in different memory banks. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a conventional computer system having graphics capability. 
     FIG. 2 shows a computer system in accordance with one embodiment of the invention. 
     FIGS. 3 shows a graphic buffer table in accordance with one embodiment of the invention. 
     FIG. 4 shows a flow chart for a system startup sequence in accordance with one embodiment of the invention. 
     FIG. 5 shows a method to establish graphic buffer storage in system memory in accordance with one embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     Techniques to utilize system memory for the storage and retrieval of graphical graphic buffer data are described. The following embodiments, described in terms of an integrated graphics controller and a banked memory architecture computer system are illustrative only and are not to be considered limiting in any respect. 
     Referring to FIG. 2, computer system  200  having an integrated graphics controller  202  that uses system memory  204  in accordance with one embodiment of the invention is shown. Computer system  200  includes host processor  206  coupled to processor bus  208  which, in turn, is coupled to primary bus  210  through bridge circuit  212 . Host processor  206  may be any type of general or special purpose processor including multiple processors. Processor bus  208  may be any type of communication channel suitable for coupling host processor  206  to bridge circuit  212 . 
     Illustrative bridge circuit  212  includes bus interface  214  for communicating with processor bus  208 , bus interface  216  for communicating with primary bus  210 , memory controller  218  for communicating with system memory  204 , graphics controller  202  for communicating with graphics device  220 , and switch  222  for selectively coupling each of  202 ,  214 ,  216 , and  218 . An illustrative primary bus conforms to the Peripheral Component Interface (PCI) specification (see the “Peripheral Component Interface Local Bus Specification,” Revision 2.1, June 1995). System memory  204  may be any type of random access memory (RAM) organized into a plurality of banks, e.g., bank- 1   224  through bank-N  226 . In one embodiment, each bank (e.g., bank- 1   224 ) may include a plurality of memory devices or chips. In another embodiment, system memory  204  comprises double data rate (DDR) synchronous dynamic random access memory (SDRAM). In yet another embodiment, system memory  204  comprises SyncLink dynamic random access memory (SLDRAM) or Rambus dynamic random access memory (RDRAM). A standard defining SyncLink memory has been assigned the tentative designation of IEEE-1596.7 by the Institute of Electrical and Electronics Engineers (IEEE). The Rambus® standard is published by Rambus, Incorporated of Mountain View, Calif. 
     Bridge circuit  228  couples primary bus  210  to secondary bus  230 . Secondary bus  230  provides a mechanism to couple non-volatile random access memory (NVRAM)  232  and a variety of input-output (I/O) devices, through I/O circuit  234 , to computer system  200 . Illustrative secondary buses include those buses conforming to the Low Pin Count (LPC) Interface, Industry Standard Architecture (ISA), and Extended Industry Standard Architecture (EISA) specifications. Illustrative NVRAM  232  include read only memory (ROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, and complementary metal oxide semiconductor (CMOS) memory. 
     In accordance with the invention generally, graphic buffer memory may be allocated from system memory during computer system startup and/or reset operations. During startup, for example, a computer system may determine the amount of system memory available and allocate a portion of that memory for use by a graphics controller—that is, establish graphic buffer storage within system memory. The number of graphic buffers established and the size of each graphic buffer may be a function of the available system memory and the type of computer system (a business machine versus a graphics workstation, for example), and may be modified over time. In a banked memory architecture computer system, each of a plurality of graphic buffers may be located in different memory banks. One advantage of this organization is that an open memory page may be maintained for each graphic buffer, potentially increasing the speed of memory access operations to the graphic buffer. 
     In accordance with one embodiment of the invention, each of graphics controller  202  and memory controller  218  includes a graphic buffer table. Referring to FIG. 3, a graphic buffer table  300  may include one or more entries, where each entry (e.g.,  302  and  304 ) identifies a graphic buffer (e.g., a front buffer, a back buffer, a z-buffer, an alpha buffer, and a texture buffer). As shown, each entry comprises an identification field (e.g.,  306 ) to identify the graphic buffer associated with the entry, a location field (e.g.,  308 ) to indicate where in system memory  204  the identified graphic buffer is located (typically, an address corresponding to the first element in the identified graphic buffer), and a length field (e.g.,  310 ) to indicate the size of the identified graphic buffer. Graphic buffer table  300  may be incorporated within a controller&#39;s (graphics or memory) address translation table, or it may be implemented as a separate table. Graphic buffer table entries (e.g.,  302  and  304 ) may be implemented in special purpose registers or as locations within a memory array. Further, graphic buffer table entries may be logically located in PCI configuration space. For example, a first graphic buffer table may be located in graphic controller  202 &#39;s PCI configuration space while a second graphic buffer table may be located in memory controller  218 &#39;s PCI configuration space. 
     In accordance with one embodiment of the invention, one or more graphic buffers may be established at computer system startup and/or as part of a system reset operation. Referring to FIG. 4 for example, on computer system  200  startup a series of system checks may be performed (block  400 ). System checks are generally performed by basic input-output system (BIOS) instructions and are collectively referred to as power-on self test (POST) routines. Typically, POST processing checks system components such as memory, disk storage units, and any expansion cards for proper functioning. Once BIOS verifies that system components are functioning properly, additional BIOS routines may initialize various components (block  402 ). Following, in conjunction with, or before the acts of block  402 , BIOS may establish one or more graphic buffers by setting graphic buffer table entries (e.g.,  302  and  304 ) to appropriate values (block  404 ). As indicated above, graphic buffer table  300  entries may exist within the configuration space of both graphics controller  202  and memory controller  218  and, as such, may be set via conventional configuration space write operations. Following the acts of blocks  402  and  404 , BIOS typically initiates a boot sequence to load an operating system controlling computer system operations (block  406 ). 
     A method to establish graphic buffers (block  404 ) in accordance with one embodiment of the invention is shown in FIG.  5 . To begin, BIOS determines system memory configuration (block  500 ). For example, BIOS may query memory controller  218  to determine the amount (e.g., the number of megabytes) and the number of banks in system memory  204 . Next, BIOS may determine the type of computer system being initialized (block  502 ). For instance, computer system  200  may be configured as a two dimensional (2D) graphics processor needing only a relatively small amount of graphic buffer memory (e.g., a 1 megabyte front graphic buffer and a 1 megabyte back graphic buffer). Alternatively, computer system  200  may be configured as a high-end three dimensional (3D) graphics workstation needing a larger number of graphic buffers (e.g., front, back, z, alpha, and texture graphic buffers) each using a relatively large amount of memory. Of course, computer system  200  may be initialized at some point (e.g., combination and size of graphic buffers) between these two illustrative extremes. In one embodiment, BIOS may obtain an indication of computer system  200 &#39;s type from BIOS memory (e.g., ROM memory—NVRAM  234 ). In another embodiment, BIOS may obtain an indication of computer system  200 &#39;s type from a user modifiable memory (e.g., CMOS RAM—NVRAM  234 ). 
     Using the information obtained through the acts of blocks  500  ad  502 , BIOS may determine a configuration for computer system  200 &#39;s graphic buffer memory (block  504 ). In one embodiment, BIOS may interrogate a table stored in NVRAM  234  to determine what graphic buffers to establish and how large each graphic buffer should be. Table 1 shows one example table that BIOS may use. In Table 1 “back” refers to a back graphic buffer, “front” refers to a front graphic buffer, “texture” refers to a texture graphic buffer, and “alpha” refers to an alpha or transparency graphic buffer. In addition, the number following each graphic buffer designation in Table 1 indicates the size (in megabytes, MB) of the graphic buffer. It will be understood by those of ordinary skill that Table 1 is not an exhaustive presentation of the possible graphic buffer configurations or types of possible computer systems. Table 1 serves to illustrate one technique by which BIOS may determine an initial graphic buffer configuration only, and should not be considered limiting in any respect. 
     
       
         
               
             
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Example Graphic buffer Parameters 
               
             
          
           
               
                 Type of 
                 System Memory Size (MB) 
               
             
          
           
               
                 System 
                 32 
                 64 
                 128 
                 256 
               
               
                   
               
               
                 Simple 2D 
                 Front(2); 
                 Front(2); 
                 Front(2); 
                 Front(4); 
               
               
                   
                 Back(2) 
                 Back(2) 
                 Back(2) 
                 Back(4) 
               
               
                 Robust 2D 
                 Front(2); 
                 Front(2); 
                 Front(4); 
                 Front(4); 
               
               
                   
                 Back(2); 
                 Back(2); 
                 Back(4); 
                 Back(4); 
               
               
                   
                 Texture(2) 
                 Texture(2) 
                 Texture(4) 
                 Texture(4) 
               
               
                 Simple 3D 
                 Front(2); 
                 Front(4); 
                 Front(4); 
                 Front(8); 
               
               
                   
                 Back(2); 
                 Back(4); 
                 Back(4); 
                 Back(8); 
               
               
                   
                 Z(2); 
                 Z(4); 
                 Z(4); 
                 Z(8); 
               
               
                   
                 Texture(2) 
                 Texture(4) 
                 Texture(4) 
                 Texture(8) 
               
               
                 Robust 3D 
                 Front(2); 
                 Front(4); 
                 Front(8); 
                 Front(16); 
               
               
                   
                 Back(2); 
                 Back(4); 
                 Back(8); 
                 Back(16); 
               
               
                   
                 Z(2); 
                 Z(4); 
                 Z(8); 
                 Z(16); 
               
               
                   
                 Alpha(2); 
                 Alpha(4); 
                 Alpha(8); 
                 Alpha(16); 
               
               
                   
                 Texture(2) 
                 Texture(4) 
                 Texture(8) 
                 Texture(16) 
               
               
                   
               
             
          
         
       
     
     Referring again to FIG. 2, system memory  204  is comprised of a plurality of banks (e.g., bank- 1   224  to bank-N  226 ). Banks represent a physical compartmentalization of memory space, where each bank may correspond to a unit or array of physical memory. A bank may be further divided into pages, where a page is typically defined in terms of a row address. (All those memory locations in a bank having a common row address are said to be on the same page of memory.) One feature of a banked memory architecture is that consecutive memory access operations to a common page (i.e., an “open” page) may be performed faster than consecutive memory access operations directed to different pages within the same bank. Methods in accordance with the invention may take advantage of this feature by establishing, to the extent possible, each graphic buffer in a separate memory bank. In this way, memory controller  218  may reduce the number of bank access conflicts and precharge delays. Of course, if there are fewer memory banks (determined in block  500 ) than desired graphic buffers, more than one graphic buffer may be located in a single bank. The precise location of a graphic buffer within each bank is a design decision. 
     Having determined the number, size, and location of each graphic buffer to be established, BIOS may set the contents of graphic buffer table entries (block  506 ). For example, one entry for each graphic buffer being established (in each of the graphics controller  202  and memory controller  218 ) would be initialized by writing to that entry&#39;s location in the appropriate configuration space: identification field  306  would be set to indicate the graphic buffer (e.g., z-graphic buffer); location field  308  would be set to indicate the graphic buffer&#39;s starting location in system memory  204 ; and length field  310  would be set to indicate the size of the graphic buffer. Next, BIOS may indicate (in a conventional manner) what memory is available to a subsequently loaded operating system (block  508 ). 
     BIOS routines are typically stored in nonvolatile memory  234 . Illustrative nonvolatile memories include ROM, EPROM, EEPROM, and flash memories. Parameters such as the type of computer system may also be stored in a nonvolatile memory. In one embodiment, system type information may be stored in the same nonvolatile memory as BIOS. In another embodiment, a user modifiable nonvolatile memory such as CMOS memory may be used. In the latter case, a user may modify the system type indication through a system setup application. 
     During computer system operations (e.g., after an operating system assumes control following POST processing), memory controller  218  may dynamically allocate memory bandwidth between graphics controller  202  and other memory requesters (e.g., processor  206 ). That is, access to system memory  204  (graphic buffer memory, system memory, or application memory) may be arbitrated and allocated on a demand basis. Alternatively, memory controller  218  may allocate memory access bandwidth based on a priority or time-slot scheme. 
     The ability to programmatically establish graphic buffer storage within system memory allows the design and manufacture of computer systems that do not require a user to purchase and install special purpose graphics hardware. One benefit of this may be to reduce the cost of a graphics capable computer system. Another benefit may be to reduce the system complexity and time required for a user to setup a graphics capable computer system. Yet another benefit may be to reduce the number of components, and therefore the manufacturing cost, of a graphics capable computer system. 
     Various changes in the materials, components, circuit elements, as well as in the details of the illustrated operational methods are possible without departing from the scope of the claims. For instance, BIOS may make different graphic buffers different sizes (in the example shown in Table 1, each graphic buffer was assigned an equal amount of memory). In addition, a computer system in accordance with the invention need not include graphics controller  202  and memory controller  218  in a common component. For example, graphics controller  202  may be in a different component coupled to primary bus  210 . In addition, acts in accordance with FIGS. 4 and 5 may be performed by a programmable control device executing instructions organized into a program module. A programmable control device may be a single computer processor, a plurality of computer processors coupled by a communications link, or a custom designed state machine. Custom designed state machines may be embodied in a hardware device such as a printed circuit board comprising discrete logic, integrated circuits, or specially designed application specific integrated circuits (ASICs). Storage devices suitable for tangibly embodying program instructions include all forms of non-volatile memory including, but not limited to: semiconductor memory devices such as EPROM, EEPROM, and flash devices; magnetic disks (fixed, floppy, and removable); other magnetic media such as tape; and optical media such as CD-ROM disks. 
     While the invention has been disclosed with respect to a limited number of embodiments, numerous modifications and variations will be appreciated by those skilled in the art. It is intended, therefore, that the following claims cover all such modifications and variations that may fall within the true sprit and scope of the invention.