Abstract:
A signal processing circuit capable of improving an S/N ratio of common mode rejection operation at a low power source voltage. In the signal processing circuit, a voltage difference between first and second signals is amplified by a first amplifier circuit and a second amplifier circuit having characteristics opposite to characteristics of the first amplifier circuit, a signal amplified by the first amplifier circuit is converted into a digital signal by a first converter circuit, a signal amplified by the second amplifier circuit is converted into a digital signal by a second converter circuit, and a differential circuit calculates a difference between an output signal from the first converter circuit and an output signal from the second converter circuit, wherein the first amplifier circuit outputs an amplified signal to the first converter circuit by receiving a voltage corresponding to a lower limit value of the input dynamic range of the first converter circuit, and the second amplifier circuit outputs an amplified signal to the second converter circuit by receiving a voltage corresponding to an upper limit value of the input dynamic range of the second converter circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a signal processing apparatus for processing a plurality of signals. 
     2. Related Background Art 
     A signal processing apparatus of one conventional type receives a signal and a black level signal, the signal being output from a photosensor or the like and containing a black level signal and a light signal, and subtracts the black level signal from the signal containing the black signal and the light signal to obtain the light signal with the black signal being eliminated. Such a conventional signal processing circuit will be described. 
     FIG. 1 is a circuit diagram of a conventional signal processing apparatus. The signal processing circuit shown in FIG. 1 has: buffer amplifiers  41  and  42  for receiving a signal output from a sensor or the like at a high input impedance and outputting the signal at a low output impedance; a subtractor amplifier  43  for subtracting one signal from the other respectively output from the buffer amplifiers  41  and  42 ; and an A/D converter (not shown) for converting an analog signal subtracted by the subtractor amplifier  43  into a digital signal. 
     The operation of the signal processing circuit shown in FIG. 1 will be described. A light signal containing a black level signal output from a sensor and another black level signal are input to the buffer amplifiers  41  and  42 . The signals output from the buffer amplifiers  41  and  42  are input via resistors R 3  and R 1  to the subtractor amplifier  43 . 
     The subtractor amplifier  43  subtracts the black level signal from the light signal and amplifiers it, this amplified signal being added to a signal having a predetermined value and output. This predetermined value is set to a lower limit value of a input voltage range (dynamic range) of the A/D converter in order to utilize the maximum dynamic range and improve a resolution. The signal output from the subtractor amplifier  43  is input to the A/D converter to convert the analog signal into a digital signal which is output to the external. 
     FIG. 2 is a circuit diagram showing the internal structure of the buffer amplifiers  41  and  42  and subtractor amplifier  43 . Referring to FIG. 2, reference numeral  51  represents a power source terminal, reference numeral  52  represents a positive input terminal, reference numeral  53  represents a negative input terminal, and reference numeral  54  represents an output terminal. As shown in FIG. 2, for example, a light signal is input to the positive input terminal  52  and amplified by a differential amplifier having as its gate electrodes the positive and negative input terminals  52  and  53 , thereby being output from the output terminal  54  thereof as a single end terminal. 
     Tendency of low power consumption in the field of electronics is changing a supply voltage for most electronic apparatuses and components to a low supply voltage. The power voltage of 5V was used for most integrated circuits (IC) in several years ago. Now, a power voltage of 3 V or lower is used. A lowered power voltage means a narrower dynamic range of the subtractor amplifier  43 , buffer amplifiers  41  and  42  and the like. 
     With conventional techniques, as the power voltage is lowered, the dynamic range becomes narrower and an amount of signal components S is reduced. Even if the dynamic range is narrowed, an amount of noises N such as switching noise and random noises is not reduced because the noise amount is not dependent upon an input signal such as a light signal. As the dynamic range is narrowed, the S/N ratio therefore lowers. 
     In order to retain a desired S/N ratio even if the power voltage is lowered, it is necessary to reduce random noises su h as thermal noises generated in each amplifier as the dynamic range narrows. Of noises generated in a signal processing circuit, most of random noises are generated in buffer amplifiers and a subtractor amplifier. Switching noises are generated in a digital circuit such as an A/D converter. 
     Common power source and ground lines are often used for both a digital circuit such as an A/D converter and an analog circuit such as a buffer amplifier and a sensor. If these power source and ground lines are used in common, the digital circuit and buffer amplifier have the same impedance of the power source and ground lines. Therefore, switching noises generated in the digital circuit appear at the output of the analog circuit such as a subtractor amplifier. 
     In the analog signal substraction circuit shown in FIG. 1, the common mode rejection ratio of the light signal and black level signal in an output signal of the subtractor amplifier becomes low if a ratio R 1 /R 2  is not equal to a ratio R 3 /R 4 , where R 1  is a resistor between the buffer amplifier and the subtractor amplifier at the black level signal side, R 2  is a resistor between a voltage source for supplying a predetermined voltage and the subtractor amplifier, R 3  is a resistor between the light signal side buffer amplifier and the subtractor amplifier, and R 4  is a resistor between the input and output terminals of the subtractor amplifier. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a signal processing apparatus capable of outputting a signal having a high S/N ratio. 
     In order to achieve the above object, according to aspect of the present invention, there is provided a signal processing circuit comprising: first differential means for executing a differential operation between first and second signals to output a third signal; amplifier means for outputting fourth and fifth signals in accordance with the third signal output from the first differential means; converter means for converting the fourth and fifth signals which are analog signals, into digital signals; and second differential means for executing a differential operation between the digital fourth and fifth signals converted by the converter means, wherein the amplifier means outputs the fourth and fifth signals in accordance with a signal level of the third signal, the fourth and fifth signals output from the amplifier means having a signal level between lower and upper limit values of a dynamic range of the converter means. 
     Other objects and features of the present invention will become apparent from the following detailed description of the embodiments when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a signal processing apparatus according to conventional techniques. 
     FIG. 2 is a circuit diagram of buffer amplifiers and a subtractor amplifier shown in FIG.  1 . 
     FIG. 3 is a circuit diagram of a signal processing circuit according to a first embodiment of the invention. 
     FIG. 4 is a diagram showing an output voltage at an output terminal  9 . 
     FIG. 5 is a diagram showing an output voltage at an output terminal  8 . 
     FIGS. 6A and 6B are a schematic diagram and a schematic cross sectional view of an X-ray diagnosis apparatus according to a second embodiment of the invention. 
     FIG. 7 is a diagram of an X-ray diagnosis system using the X-ray diagnosis apparatus shown in FIGS.  6 A and  6 B. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the invention will be described with reference to the accompanying drawings. 
     FIG. 3 is a circuit diagram of a signal processing apparatus according to the first embodiment of the invention. In FIG. 3, reference numeral  1  represents a power source terminal, reference numeral  2  represents a ground terminal, reference numerals  3  and  4  represent a voltage input terminal, and reference numerals  5  and  6  represent an A/D converter. A voltage to be applied to the voltage input terminal  3  is set equal to an upper limit value V tH  of the input dynamic range of the A/D converters  5  and  6 . A voltage to be applied to the voltage input terminal  4  is set equal to a lower limit value V tL  of the input dynamic range of the A/D converters  5  and  6 . 
     Reference numeral  7  represents a digital subtractor, reference numerals  8  and  9  represent an output terminal, and reference numeral  10  represents a differential input voltage source which outputs a voltage V i . If a signal from a photosensor is to be input, the differential input voltage source outputs a difference between a light signal having a black level as its reference level and a black level signal. M 1 , M 2 , M 8  and M 12  represent an NMOS transistor, and M 3  to M 7 , M 9 , M 10 , M 11 , M 13  and M 14  represent a PMOS transistor. Pairs of M 3  and M 6 , M 4  and M 5 , M 9  and M 10 , and M 13  and M 14  each constitute a current mirror circuit. 
     I 1  to I 6  represent a bias current source. The bias current sources I 1  and  12  output a current I, the bias current sources I 4  and I 5  output a current (2×I). The bias current sources I 3  and I 6  output a current I. 
     The operation of the signal processing circuit shown in FIG. 3 will be described. The voltage V i  of the differential input voltage source  10  is applied to the gate terminals of the NMOS transistors M 1  and M 2 . Namely, in the case of a photosensor, a light signal having the black level as its reference level is applied to the gate (control electrode) terminal of M 1 , and a black level signal is applied to the gate terminal of M 2 . In addition to the current I from the bias current sources I 1  and I 2 , a signal current V i /R 1  which is provided by voltage-current conversion by a resistor R 1  connected between the sources (first main electrodes) of the NMOS transistors M 1  and M 2 , flows through the drains (second main electrodes) of M 1  and M 2 . 
     The current flowing through each of the drains of M 1  and M 2  also flows through M 6  and M 5  via current mirror circuits. The drain current of M 5  therefore flows through the source of the NMOS transistor M 8 , and the drain current of M 6  flows through the source of the NMOS transistor M 12 . 
     Since the current sources I 4  and I 5  supplying the current  2 I are connected to the source of the NMOS transistors M 8  and M 12 , a current of [ 2 I−(I+V i /R 1 )]=[I−V i /R 1 ] flows through the source of the NMOS transistor M 8 . 
     The PMOS transistors M 9  and M 10  constitute a current mirror. A negative feedback is realized by a connection of the drain of the PMOS transistor M 10  to the source of the NMOS transistor M 8  via the resistor R 2 . Therefore, of the current [I−V i /R 1 ] applied to the source of the NMOS transistor M 8 , a current [−V i /R 1 ] which is difference between the current [I−V i /R 1 ] and the current I of the constant current source I 3 , flows through the drain of the PMOS transistor M 10  via the resistor R 2 . 
     A voltage approximately same as the voltage V tH  applied to the gate of the PMOS transistor M 7  is applied to the source of the NMOS transistor M 8  and the current flowing through the resistor R 2  is V i /R 2 . Thus, an output voltage at the output terminal  9  is [V tH −(R 2 /R 1 )V i ] when the direction of the current is taken into consideration. 
     Similarly, the PMOS transistors M 13  and M 14  constitute a current mirror. A negative feedback is realized by a connection of the drain of the PMOS transistor M 14  to the source of the NMOS transistor M 12  via the resistor R 3 . Therefore, of the current [I−V i /R 1 ] flowing through the source of the NMOS transistor M 12 , a current [ 2 I−(I−V i /R 1 )]=[I+V i /R 1 ] which is difference betwen the current [I−V i /R 1 ] and the current  2 I of the constant current source I 5 , flows through the drain of the PMOS transistor M 14  via the resistor R 3 . 
     A voltage approximately same as the voltage V tL  applied to the gate of the PMOS transistor M 11  is applied to the source of the NMOS transistor M 12  and the current flowing through the resistor R 3  is V i /R 1 . Thus, an output voltage at the output terminal  8  is [V tL +(R 3 /R 1 )V i].    
     FIG. 4 is a graph showing an output voltage at the output terminal  9 . As shown in FIG. 4, the output voltage at the output terminal  9  can be expressed by a linear function of a gradient [−R 2 /R 1 ]. If the differential input voltage V i  is 0, the output voltage at the output terminal  9  is equal to V tH . As the voltage V i  becomes large, the output voltage becomes small in proportion to the gradient [−R 2 /R 1 ]. 
     If the gradient [−R 2 /R 1 ] is determined so that the output voltage becomes equal to the lower limit V tL  of the input dynamic range of the A/D converters  5  and  6  when a maximum value of a given full scale of the differential input voltage V i  is input, then a maximum resolution of digital conversion by the A/D converter  5  can be obtained. 
     FIG. 5 is a graph showing an output voltage at the output terminal  8 . As shown in FIG. 5, the output voltage at the output terminal  8  can be expressed by a linear function of a gradient [R 3 /R 1 ]. If the differential voltage V i  is 0, the output voltage at the output terminal  8  is equal to V tL . As the voltage V i  becomes large, the output voltage becomes large in proportion to the gradient [R 3 /R 1 ]. 
     If the gradient [R 3 /R 1 ] is determined so that the output voltage becomes equal to the upper limit V tH  of the input dynamic range of the A/D converters  5  and  6  when a maximum value of a given full scale of the differential input voltage V i  is input, then a maximum resolution of digital conversion by the A/D converter  6  can be obtained. As above, it can be understood that a maximum efficiency can be obtained if the resistors R 2  and R 3  have the same value. 
     The voltages at the output terminals  8  and  9  are applied to analog input terminals of the A/D converters  5  and  6  and A/D converted to be input to the digital subtractor  7 . The digital subtractor  7  subtracts the output signal from the A/D converter  5  from the output signal from the A/D converter  6 . 
     The digital output of the digital subtractor  7  therefore corresponds to an analog voltage of: 
     
       
         [ V   tL +( R   3 / R   1 ) V   i   ]−[V   tH −( R   2 / R   1 ) V   i ]=[{( R   2 + R   3 )/ R   1 } V   i −( V   tH   −V   tL )]  (1) 
       
     
     If R 2 =R 3 , the equation (1) becomes [ 2 (R 2 /R 1 )V i −(V tH −V tL )]. The signal components therefore can have a full scale two times as large as that of the digital output of each of the A/D converters  5  and  6 . As seen from the equation (1), the output voltage is not basically dependent upon a voltage having the same phase as the differential input voltage V i . Thus, there is less influence of a variation in common mode voltage to be caused by the potential change at the power source and ground terminals. 
     More specifically, if an amplifier circuit and a digital circuit have the same impedance of the power source lines, switching noises generated in the digital circuit also appear at the power source lines of the amplifier circuit and thus at the output thereof to some extent. 
     However, switching noises leaked from the digital circuit and appeared at the output of the amplifier circuit have the same phase as the differential input voltage source. Therefore, the switching noises are attenuated by the common mode rejection ratio of the differential amplifier circuit whose input is M 1  and M 2  shown in FIG.  3 . Furthermore, most of switching noises superposed upon the input voltages to the A/D converters  5  and  6  have the same phase so that these switching noises are subtracted from each other by the digital subtractor  7 . From these reasons, the influence of switching noises can be suppressed. 
     Still further, since the output signals of the A/D converters  5  and  6  are subtracted from each other, the influence of noises on the ground line upon a single-ended output of the digital subtractor  7  can be alleviated almost completely. In this embodiment, although MOS type transistors are used, the signal processing circuit may be made of bipolar transistors. 
     In this embodiment, the output voltage is independent from a relative precision of a ratio between two resistor values, so that a very large common mode rejection ratio (CMRR) can be obtained. Furthermore, the number of components of the amplifier circuit shown in FIG. 3 can be reduced and the manufacture cost of the signal processing circuit can be lowered. 
     FIGS. 6A and 6B show a schematic diagram and a schematic cross sectional view of an X-ray image sensing apparatus with the signal processing circuit of the first embodiment, according to the second embodiment of the invention. The structure of the X-ray image sensing apparatus will be described first. A plurality of photoelectric conversion elements and transistors are formed on an amorphous silicon (a-Si) sensor substrate  6011 . This substrate  6011  is connected to a flexible connector band  6010  on which shift registers SR 1  and signal detecting ICs are mounted. 
     The flexible connector band  6010  is connected to printed circuit boards PCB 1  and PCB 2  on the other end opposite to the a-Si sensor substrate  6011 . A plurality of a-Si sensor substrates  6011  are adhered to a base board  6012 . On the bottom surface of the base board  6012  constituting a large size photoelectric conversion device, a lead plate  6013  is mounted in order to protect memories  6014  of a processing circuit  6018  from X-rays. 
     A fluorescent member  6030  is formed on the a-Si sensor substrates  6011  to convert X-rays into visual rays. For example, the fluorescent member  6030  is formed by coating or attaching CsI on the upper surfaces of the a-Si sensor substrates  6011 . By using the photoelectric conversion device, X-rays can be detected. In this embodiment, as shown in FIG. 6B, the photoelectric conversion device is covered with a case  6020  made of carbon fibers. 
     FIG. 7 is a diagram showing an X-ray diagnosis system of this embodiment. X-rays  6060  generated by an X-ray tube  6050  transmit through a chest  6062  of a patient or client  6061  and become incident upon a photoelectric conversion device  6040 . The incidence X-rays contain information on the inside of the body of the patient  6061 . A fluorescent member radiates light in correspondence with the incidence X-rays, and the light is photoelectrically converted to obtain electrical information. 
     This information is processed by the signal processing circuit described with the first embodiment to be converted into digital image data which is processed by an image processor  6070 . The processed image can be monitored on a display  6080  installed in a control room. 
     This image data can be transmitted to a remote site via a transmission medium such as a telephone line  6090 . At the remote site such as a doctor room, the transmitted image data may be displayed on a display  6081  to be diagnosed by a remote site doctor or stored in a storage medium such as an optical disk. The image data may be stored on a film  6110  by using a film processor  6100 . 
     In this embodiment, although the photoelectrical conversion device is applied to an X-ray diagnosis system, it may be applied to a radiation ray image sensing system such as a non-destructive inspection apparatus using radiation rays such as α, β, γ rays other than X-rays. 
     As described so far, in the signal processing circuit described with the first and second embodiments, a difference signal between first and second signals is amplified by using as reference potentials the upper and lower limit values of a input dynamic range of conversion units, the amplified analog difference signals are converted into digital signals by the conversion units, and a difference between the converted digital signals is obtained. Accordingly, random noises can be reduced and the influence of switching noises can be alleviated considerably. 
     Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.