Abstract:
Channel-encoding and channel-decoding of a (d, k, m, n) code are disclosed. An m-bit input word is encoded to an (n-d+1)-bit channel word by an encoding table. One or more merge bits are added to each of the encoded channel words so as to form an n-bit channel word. Depending upon detection of violation of d and/or k constraints in the juxtaposition of consecutive channel words in combination with their intervening merge bit(s), certain bits are converted to cause the d and k constraints to both be met, and for the purpose of minimizing the digital sum value (DSV). To decode the channel words thus encoded, n-bit channel words are received and examined as consecutive pairs to determine the states of the merge bit(s) and the identifying bits of each channel word. The identifying bits and/or the last bit of the first channel code and the first bit of the second channel code are converted based on the validity of the d and k constraints. The merge bit(s) are then discarded and the remaining bits of the channel word are decoded into m-bit data using a decoding table.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to channel-encoding and channel-decoding devices and methods, and more particularly, to simplified devices and methods for channel-encoding and channel-decoding of digital data, in which predetermined code constraints are satisfied and the efficiency of an eight-to-fourteen modulation (EFM) code is increased. 
     Channel-encoding of digital data is a technique to overcome limitations inherent in a channel or a recording medium and increases the robustness of a system. In an optical recording device, the channel-encoding itself influences recording density, because the minimum number of running zeroes in a channel code has a direct impact on the size of pits. 
     The most widely known channel-code is the runlength-limited (RLL) code which has a restriction on the minimum number and the maximum number of consecutive 0s between two is in a sequence of code. The number of the consecutive 0s is referred to as runlength. 
     RLL codes are characterized by parameters. Examples of these parameters include (d, k) and (d, k, m, n), where d indicates a minimum runlength, k indicates a maximum runlength, m indicates the number of bits of data which is input in an encoder, and n indicates the number of bits of a code word which is output from the encoder. Here, d is a factor determining a minimum length of a pit for recording data in an optical recording medium, and larger d values are preferred. However, when d increases with a given n, the number of available code words decreases, leading to a decrease in m. As a result, the value of m/n which indicates the efficiency of an encoder decreases, thereby reducing the rate of output from the encoder. 
     An EFM code (2, 10, 8, 17) is used for a compact disk. To produce the code, 256 14-bit code words which satisfy the constraints of d=2 and k=10 are selected. To satisfy the runlength constraints when code words are concatenated, 3 merging bits are inserted between code words. 
     When the d and k constraints are satisfied, the merging bits are inserted to reduce a digital sum variance (DSV) so that the variation of a DC value decreases and recorded signals are reproduced reliably. 
     The k parameter influences a phase-locked loop which extracts timing information included in a signal during playback. Smaller k values are preferred. However, a decrease in k lowers the efficiency of a code. Since k is less influential on the characteristic of a code than d, a small increase or decrease of k has no significant impact on the characteristic of the code. Further, once k is sufficiently large, the efficiency of the code will increase with k. 
     The code efficiency significantly influences the efficiency of a recording medium. Since channel-encoding itself increases redundancy, the efficiency of the recording medium increases in proportion to the code efficiency. 
     Since the EFM code has three merging bits, the code efficiency is 8/17, which is smaller than that of an EFM-plus code or an eight-to-fifteen code. Hence, optical recording devices recently developed adopt codes having a higher code efficiency of 8/16 or 8/15 rather than the EFM code. However, in order to implement such codes, another encoding table, which differs from that used for a compact disk and more complex circuits are required. Thus, the more efficient codes cannot be used in existing recording devices. Further, an interchangeable device capable of playing back a common compact disk format also, must be equipped with one extra decoder to decode these codes. 
     SUMMARY OF THE INVENTION 
     To overcome the above problems, it is an object of the present invention to provide channel-encoding and channel-decoding methods which use an EFM code with a reduced number of merging bits, which are compatible with encoders and decoders for conventional EFM code, and increase code efficiency. 
     It is another object of the present invention to provide devices for encoding and decoding of a highly efficient code by employing simple circuitry. 
     To achieve the above first object, there is provided a method for channel-encoding of digital data into a (d, k, m, n) code where d indicates a minimum runlength, k indicates a maximum runlength, m indicates the bit number of an input word, and n indicates the bit number of a code word. 
     The channel-encoding method according to the present invention includes the preliminary steps of encoding each m-bit input word into a channel word (having a length of more than m, but less than n bits) by means of an encoding table, concatenating together two consecutive channel words with one or more merge bits between the channel words (thereby increasing the overall length of a channel word to n bits), and assigning certain bits in each of the consecutive channel words to be &#34;identifying bits.&#34; The consecutive bit pattern of the two channel words and the merge bit(s) is adjusted depending on the d (minimum run length) constraint and the k (maximum run length) constraint. Specifically, the last bit of the first channel word, the first bit of the second channel word, and the merge bit(s) are converted in the event the d constraint is violated. Further, the identifying bits and the merge bit(s) are converted in the event the k constraint is violated. 
     A method of channel-decoding a digital data code according to the above-described (d, k, m, n) coding model is also provided. According to the channel-decoding method of the present invention, n-bit channel words are received and examined as consecutive pairs to determine the states of the merge bit(s) and the identifying bits of each channel word. The identifying bits and/or the last bit of the first channel code and the first bit of the second channel code are converted based on the validity of the d and k constraints. The merge bit(s) are then discarded and the remaining bits of the channel word are decoded into m-bit data using a decoding table. 
     To achieve the second of the above objects, a device for channel-encoding is provided which encodes digital data by a (d, k, m, n) code. As in the case of the (d, k, m, n) channel-encoding method mentioned above, d indicates a minimum runlength, k indicated a maximum runlength, m indicates the number of bits of an input word, and n indicates the number of bits of a code word. The channel-encoding device according to the present invention has an encoder which encodes an m-bit input word into an (n-d+1)-bit channel code by means of an encoding table. Also included is a first detector which detects a violation of a k constraint by determining a runlength of zeroes in the channel code output from the encoder. Consecutive pairs of code words output by the encoder are held in a first latch and a second latch. A second detector detects a violation of a d constraint from the outputs of the first and second latch means. A converter is controlled by the outputs of the first and second detectors to convert the certain output bits of the first and second latches. 
     A device for channel-decoding a digital data code according to the above-described (d, k, m, n) coding model is also provided. According to the channel-decoder of the present invention, n-bit channel words are received into a first latch. A second latch receives the code word output from the first latch and separates the merge bit(s) from the output of the first latch. Control signals are generated by determining the states of the identifying bits and the merge bit(s). The outputs of each of the first latch and the second latch are converted based on the generated control signals. The converted channel code output by the second latch is decoded into an m-bit data word by means of a decoding table. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects and advantages of the present invention will become more apparent by detailed descriptions of preferred embodiments thereof with reference to the attached drawings in which: 
     FIG. 1 is a block diagram of a digital data channel encoder according to the present invention; and 
     FIG. 2 is a block diagram of a digital data channel decoder according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Constraints and rules required to achieve channel encoding and channel decoding methods suggested in the present invention will be described. 
     Constraint 1 
     Let the leading code word of two concatenated code words of (d, k, m, n) format be Cp and the following codeword be Cn. If both the last bit of Cp and the first bit of Cn are is and a single merging bit is added, then a d parameter of 2 cannot be satisfied even if 0 is assigned as the merging bit. 
     Constraint 2 
     When the number of 0s between the last &#34;1&#34; bit of Cp and the first &#34;1&#34; bit of Cn is larger than k, the merging sequence should include a &#34;1&#34; to satisfy k. 
     When both constraints 1 and 2 are satisfied, the merging bit should be determined to reduce the DSV value. A DSV controlling method for decreasing the DSV value is well known to those skilled in the art. Before being recorded in a recording medium, the signal values between the time points of 1 and the next 1 in the signal are converted to 1 or -1. A DSV value indicates the accumulated values of these signals and is altered by inserting one additional bit in the signal to invert the signal. The decrease of the DSV value by this insertion of a 0 or 1 additional bit depending on the DSV value is referred to as DSV control. It is well known that a 3-bit merging sequence is used to perform the DSV control in a conventional compact disk. 
     Constraint 3 
     To control the DSV value, a &#34;0&#34; or &#34;1&#34; should be added in an intended position without any impact on a code value or code efficiency. When the d and k constraints are satisfied without regard to the value of the merging bit, the merging bits are used to control the DSV value. Though the DSV control differs among the types of devices, it has been determined experimentally that a DSV control at every 20th code word, on average, prevents the DSV value from increasing to 100 or above. In many cases, however, a DSV controlling bit is inserted in a predetermined position of each code word. 
     To satisfy the above three constraints by adding a single merging bit, the following encoding and decoding rules are used. 
     Encoding rules 
     1. Every 8-bit unit of input data is converted into a 14-bit code word by using an EFM encoding table. 
     2. Assuming that the leading code word of two consecutive code words is Cp and the following code word is Cn, when both the last bit of Cp and the first bit of Cn are is, a merging bit is set to 1 and the last bit of Cp and the first bit of Cn are converted into 0s. 
     In other words, if X denotes a bit having an arbitrary value and M denotes the merging bit, the combination of two code words such as ##STR1## 
     3. If the runlength of the combination of two code words Cp and Cn, including the merging bit, is fourteen or more, the merging bit is set to 1 and the twelfth bit of Cp and the third bit of Cn are converted into 1s. 
     Here, the twelfth bit of Cp and third bit of Cn are referred to as identifying bits P. 
     For instance, the combination of two code words of ##STR2## 
     4. If one of the identifying bits of the two concatenated code words Cp and Cn is 0 and all the bits between the identifying bits are also 0s, a 0 or 1 is selected as the merging bit so as to decrease the DSV. 
     For example, this rule is applied to sequences in the form of ##STR3## 
     A sequence encoded according to the above encoding rules is decoded according to the following rules. 
     Decoding rules 
     1. If a merging bit is 1 and both the last bit of Cp and the first bit of cn are 0s, the last bit of Cp and the first bit of Cn are converted into 1s. 
     2. If the merging bit is 1 and both the identifying bits are 1s, the identifying bits are converted into 0s. 
     3. The merging bit is removed and the other fourteen bits are decoded to the original data by using an EFM decoding table. 
     The (2, 13, 8, 15) code which uses the above encoding and decoding rules shows the code efficiency of 8/15 and can share the encoding table with the conventionally known (2, 10, 8, 17) EFM code. 
     The encoding and decoding rules will be described in more detail. 
     When k is thirteen, codes having nine consecutive zeroes such as those which follow, are not used so that a k constraint is satisfied when a code word which starts or ends with a &#34;0&#34; is concatenated. ##STR4## Thus, in case the k constraint is violated, the number of consecutive 0s in the least significant bit portion of Cp or the most significant bit portion of Cn is at least five. 
     Since the conventional EFM code is a (2, 10, 8, 17) code, k should be ten or more. However, a k value of 10, 11 or 12 is not proper for DSV control since it is confusing whether identifying bits serve to perform the DSV control or indicate a violation of k. That is, when concatenated sequences are of the types, ##STR5## one of the identifying bits cannot be converted into a &#34;1.&#34; Hence, after the other identifying bit is converted, the concatenated sequence will have the form of ##STR6## As a result, the identifying and merging bits for indicating a violation of k cannot be differentiated from those for controlling the DSV value. 
     If k is changed to thirteen to solve this problem, the increase of k has no significant impact on the characteristic of the code, as described above. 
     If k is thirteen, the identifying bits of Cp and Cn can always be converted to is when the k constraint is violated. That is, in all the concatenated sequences where the k constraint is violated, at least the last five Cp and the first five Cn are 0s. Thus, unlike the cases described above, the twelfth bit of Cp and the third bit of Cn are converted into is, the d constraint is satisfied. 
     Further, to satisfy the constraint of d=2, if either of the last two bits of Cp is a 1, the twelfth bit of Cp should be 0; and if either of the first two bits of Cn is a 1, the third bit of Cn should be a 0. 
     Accordingly, the merging bit is set to 1 if the d or k constraint is violated. Beyond this, the twelfth bit of Cp and the third bit of Cn are converted into is when k is violated and the last bit of Cp and the first bit of Cn are converted into 0s when d is violated. Thus, when the merging bit is 1, it can be determined which constraint was violated by determining whether the twelfth bit of Cp and the third bit of Cn are 1s or the last bit of Cp and the first bit of Cn are 1s. 
     In these two cases where the k or d constraint is violated, the decoder can use the EFM decoding table to decode the code word if it recovers converted bits according to the decoding rules described above before decoding. 
     In order to control the DSV value, the merging bit should be converted into 1 or 0 depending on the DSV value. When the merging bit is 1, it must be discriminated from the case for satisfying the d and k constraints. The decoder determines that the merging bit is set to 1 for DSV control when either the twelfth bit of Cp or third bit of Cn is a 1. Consequently, when the merging bit is 1, the decoder determines which bit to convert on the basis of the twelfth bit of Cp and the third bit of Cn. This explains why the twelfth bit of Cp and the third bit of Cn are referred to as identifying bits. 
     In addition, when k is satisfied and there are more than five 0s on both sides of the merging bit, for example, 
     
         XXXXXXXXX00000M00000XXXXXXXXX,&#34; 
    
     an additional DSV control can be performed by converting the merging bit, the twelfth bit of Cp and the third bit of Cn into is or leaving them as 0s according to the DSV. 
     These kinds of conversion are possible only when, the twelfth bit of Cp, and the third bit of Cn do not result in a violation of the d and k constraints. 
     Particularly, when they are all converted into 1s, the result is the same as that of a code conversion with a violation of the k constraint. Therefore, there is no need for an additional circuit or to change the decoding rules in recovering the converted bits. 
     In this case, since a runlength of eleven or more is divided into shorter runlengths of about four, the waveform of a signal becomes more stable. 
     When DSV control is not performed, coding parameters can be changed to (2, 11, 8, 15) by modifying the encoding and decoding rules as follows. 
     Encoding rules without DSV control 
     1. Every 8-bit unit of input data is converted into a 14-bit code word by using an EFM encoding table. 
     2. Assuming that the leading code word of two consecutive code words is Cp and the following code word is Cn, when both the last bit of Cp and the first bit of Cn are ones, a merging bit is set to 1 and the last bit of Cp and first bit of Cn are converted into 0s. 
     3. If the runlength of the combination of two code words Cp and Cn including the merging bit is larger than twelve, the merging bit is set to &#34;1&#34; and either the twelfth bit of Cp or the third bit of Cn is converted into a &#34;1&#34; only when such a change does not violate d. 
     Rules for decoding a sequence encoded by the above encoding rules are as follows. 
     Decoding rules without DSV control 
     1. If the merging bit is a 1, and both the last bit of Cp and the first bit of Cn are 0s, the last bit of Cp and the first bit of Cn are converted into 1s. 
     2. If the merging bit is 1 and at least one of the twelfth bit of Cp and third bit of Cn is a 1, both the twelfth bit of Cp and third bit of Cn are converted into 0s. 
     3. The merging bit is removed and the other fourteen bits are decoded to the original data by using an EFM decoding table. 
     The above rules are altered when k is violated. That is, since k is limited to eleven, if the runlength of a concatenated sequence is twelve or thirteen, it is possible that Cp ends with &#34;1000&#34; or &#34;10000&#34; or Cn begins with &#34;0001&#34; or &#34;00001.&#34; Here, some cases occur when neither the twelfth bit of Cp nor third bit of Cn can be converted into 1. 
     Though the EFM code satisfies the constraint of k=10, k is set to eleven to prevent a decoder from making errors. That is, when code words are concatenated as ##STR7## the decoder makes the error of converting all the identifying bits into 0s. Therefore, k is changed into eleven to avoid the above cases. 
     It is clear that when data is encoded as described, decoding should be performed according to the above decoding rules. That is, when there is no need for a DSV control, k can be reduced to eleven. However, the additional DSV control described above is possible in this case, too. 
     The encoding and decoding method according to the above rules can be used in case that d is 2 or more and n is at least two times of d+1 as well as in encoding and decoding devices which can share the encoding table with the EFM encoding. 
     A generalized encoding rule uses the (n-d)th bit of Cp and the (d+1)th bit of Cn as identifying bits. To satisfy the k constraint, the identifying bits and one bit of a merging bit are converted depending on the runlength of a concatenated sequence. To satisfy the d constraint, the identifying bits and the last bit of Cp and first bit of Cn are converted depending on the runlength. Thus, a code can be produced in which a DSV value is controlled and the d and k constraints are satisfied. 
     The positions for the identifying bits were obtained on the basis of the d constraint so that when k is violated due to d, setting identifying bits to 1s would not violate the d constraint. The (d+1)th bits from the merging bit do not violate d constraint when the bits and the merging bit are converted into 1s. Also, when the d constraint is violated, the identifying bit remains 0 even when neither of the adjacent bits to an identifying bit is 1. 
     The k parameter should always be larger than the sum of the number of merging bits and the maximum run length of a code excluding the merging bit. Further, since d should not be violated when the identifying bits and one of the merging bits are converted into is for DSV control, k should be larger than a number which is smaller than Expression 1 by one. 
     
         2d+MBN+1 d+2                                               (1) 
    
     where the first 2d indicates a minimum number of 0s which do not lead to a violation of d in the bits to the left of the identifying bit of a leading code word of a concatenated sequence and the bits to the right of the identifying bit of a following code word when the identifying bits are is; MBN is the number of merging bits; and 2d+2 indicates the number of zeroes which do not lead to a violation of d in the bits between the merging bit and the identifying bits. 
     In the encoding table, the number of 0s from a starting 0 to the first 1 in Cp or Cn, or the number of 0s from the last 1 of Cp or Cn to the ending 0 are termed boundary runlengths or boundary k constraints, and is defined as kb. 
     
         kb+MBN+2d+1                                                (2) 
    
     When the result of Expression 2 is larger than that of Expression 1, k should be larger than a number which is smaller than the result of Expression 2 by one. This is because Expression 2 is a minimum number of 0s which satisfies kb and solves problems inherent in a violation of k without violating d. 
     If the k parameter of the encoding table is kt and kt is larger than the result of Expression 1 or 2, kt becomes k of a final code. In short, the k of a code should be larger than the largest of Expressions 3, 4 and 5. 
     
         (2d+MBN+2d+2)-1                                            (3) 
    
     
         (kb+MBN+2d+1)-1, or                                        (4) 
    
     
         kt                                                         (5) 
    
     A minimum number of merging bits in a merging sequence is a minimum number of 0s which can settle any violation of d, except for &#34;1 M1&#34; in the concatenated sequence, when both the identifying bits are set to 0s. In other words, the minimum number of merging bits in a merging sequence is d-1. 
     A minimum of k when DSV control is not performed is determined to be the largest of Expressions 5, 6 and 7. 
     
         kb+MBN+d                                                   (6) 
    
     
         3d+1+MBN                                                   (7) 
    
     In the (2, 13, 8, 15) code described above which uses the EFM encoding table, k was set to thirteen according to the result of Expression 2. 
     For another example, a (3, 12, 8, 19) code can be constructed. In this case, a merging sequence has two bits. When d is violated, i.e., both the last bit of Cp and the first bit of Cn are is, the first bit of the merging sequence is set to 1 and the last bit of Cp and the first bit of Cn are converted into 0s. When k is violated, the first bit of the merging sequence is set to 1 and the fourth bits from the merging sequence of Cp and Cn, respectively, are converted into 1s. 
     This code is more powerful in DSV control than that of d=2. This is because, if d and k are satisfied regardless of the merging bit, the case where the merging bit is set to 1 for DSV control can be discriminated from other cases by using the second bit of the merging bit as a DSV control flag. Therefore, the DSV value can be controlled more frequently than in the case of d=2. 
     Decoding is performed by recovering the converted bits of a channel code on the basis of the merging bits and the identifying bits as described in connection with the d=2 cases. An encoding table for d=3, m=8 and n=19 has 256×19 bits. 
     Conventionally, a code efficiency is increased by assigning a plurality of data information to a channel code and considering state transition as well since the number of available codes is limited. In contrast, a new method suggested in the present invention is simple in principle and structure and provides a more efficient code. 
     Now, embodiments of devices for encoding and decoding of digital data will be described with reference to FIGS. 1 and 2. 
     In FIG. 1, input data is converted into a 14-bit channel code word by using a conventional EFM encoding table 110. The EFM encoding table 110 is generally stored in a ROM and can be referred to as a real encoder. The output of the EFM encoding table 110 is stored in a Cn register 120. After the conversion of the first and third bits, the output of the Cn register 120 are stored as the previous code word Cp in a Cp register 150. The Cn and Cp registers 120 and 150 are comprised of D flip-flops. Here, the Cp register 150 is fifteen bits long and stores a merging bit M in the fifteenth bit. 
     A runlength detector 130, which detects the runlengths of the channel codes received in the Cp and Cn registers 120 and 150, detects the number of consecutive 0s in the output of the EFM encoding table 110, and determines whether the constraint of k is violated. A general counter can be used as the run-length detector 130, which increments its counted value by one when a &#34;0&#34; is input and is reset when a &#34;1&#34; is input. This is well known to anyone skilled in the art. 
     When the k constraint is violated, the run-length detector 130 outputs a &#34;1&#34; to OR gates 141, 145 and 146. Thus, in the case of the violation of the k constraint, the output of the OR gate 141 is always &#34;1&#34; and input to the fifteenth bit of the Cp register 150. The twelfth bit of Cp is input to the other input of the OR gate 146 and the third bit of Cn is input the other input of the OR gate 145. In this circumstance, outputs of the OR gates 145 and 146 are 1s. 
     When the d constraint is violated, the fourteenth bit of the Cp register 150 and the first bit of the Cn register 120 are 1s, and thus an AND gate 142 outputs 1, which serves as a signal indicating the violation of the d constraint. That is, the AND gate 142 functions to detect the violation of the d constraint. The output of the AND gate 142 is input to the other input of the OR gate 141 thereby changing the merging bit M to 1. The output of the AND gate 142 is inverted in an inverter 143 and input to AND gates 144 and 147 to convert the last bit of the code Cp and the first bit of the code Cn into 0s. The output of the Cp register 150 is converted into a sequence of n-bit code words in a parallel-to-serial converter 160. The converted code word is input to a DSV controller 170 for controlling a DSV value under the aforementioned constraints, and output encoded data. 
     FIG. 2 illustrates a decoder of the present invention. The operation of the decoder will be described referring to the figure. 
     In FIG. 2, coded data is input to a serial-to-parallel converter 210. Here, if data was modulated by non-return-to-zero inverted (NRZI) modulation during recording, the NRZI data is recovered to original nonreturn-to-zero (NZR) data during playback and then input to the serial-to-parallel converter 210. 
     The serial-to-parallel converter 210 converts the serial code word in a 15-bit unit of a parallel data. The parallel code word is stored in a Cn register 220. Then, the output of the Cn register 220 is sequentially converted according to the state of a merging bit M, and input to a Cp register 240. 
     More specifically, the identifying bits, which are the twelfth bit of the Cp register 240 and the third bit of the Cn register 220, and the merging bit serve to determine which channel bits are converted. To implement the determinations based on these bits, the twelfth bit of the Cp register 240 and the third bit of the Cn register 220 are input to an AND gate 232 and a NOR gate 231. Thus, the AND gate 232 outputs 1 when both these identifying bits are is, and the NOR gate 231 outputs 1 when they are both 0s. 
     The output of the AND gate 232 is input to a NAND 234. The last bit of the Cp register 240, i.e., the merging bit M, is input to the other input of the NAND gate 234. When the merging bit is &#34;1&#34; and the output of the AND gate 232 is &#34;1&#34; (that is, when both the twelfth bit of the Cp register 240 and the third bit of the Cn register 220 are is), the NAND gate 234 outputs 0. 
     When the output of the NAND gate 234 is 0, AND gates 236 and 237 convert the twelfth bit of the Cp register 240 and the third bit of the Cn register 220 into 0s. 
     In short, when the identifying bits of the two input codes Cp and Cn and the merging bit are is, which indicates that the k constraint is not satisfied during the decoding, the AND gates 232, 236 and 237 and the NAND gate 234 convert both the identifying bits into 0s. 
     Meanwhile, an AND gate 233 outputs 1 when the merging bit is &#34;1&#34; and both the twelfth bit of the Cp register 240 and the third bit of the Cn register 220 are 0s. When the AND gate 233 outputs 1, OR gates 235 and 238 convert the last bit of the Cp register 240 and the first bit of the Cn register 220, which are 0s, are into 1s. 
     In short, the NOR gate 231, AND gate 233 and OR gates 235 and 238 convert the last bit of the Cp register 240 and the first bit of the Cn register 220 into 1s when the merging bit is &#34;1&#34; and the identifying bits are 0s, which indicates that the d constraint is not satisfied. 
     The output of the Cp register 240, which is converted depending on the states of the twelfth bit of the Cp register 240 and the third bit of the Cn register 220, is decoded to the original data through a conventional EFM decoding table 250. The EFM decoding table 250 is stored in a ROM and can be referred to as a real decoder. 
     In the present invention, the efficiency of the EFM code used in a compact disk is increased. With the EFM code, encoding and decoding devices are constituted more simply than with an EFM-plus code or an 8-15 code having a code efficiency similar to that of the EFM code. Also, the present invention can be used in an optical recording device, which is compatible with a conventional compact disk player and decoder. 
     As described above, since the present invention shares the encoding and decoding tables with an EFM code, required circuitry is reduced in fabrication of an interchangeable device capable of reproducing a compact disk. Further, code efficiency is improved, which makes the present invention suitable for high-density recording.