Abstract:
A constant-on-time power-supply controller includes an adder and a control circuit. The adder generates a sum of a sense voltage and a regulated output voltage generated by a filter inductor. The sense voltage is generated by a sense circuit that sources a current to the filter inductor while the inductor is uncoupled from an input voltage, and the sense voltage is related to the current. The control circuit couples the filter inductor to the input voltage for a predetermined time in response to the sum having a predetermined relationship to a reference voltage. Such a power-supply controller may yield a relatively tight regulation of the output voltage even with a power supply having with a low-ESR filter capacitor, and may do so with little or no additional compensation circuitry as compared to prior controllers and with no additional pin on the power-supply-controller chip.

Description:
CLAIM OF PRIORITY 
     This application claims priority to U.S. Provisional Application Ser. No. 60/687,165, filed on Jun. 3, 2005, which is incorporated by reference. 
    
    
     BACKGROUND 
     A traditional constant-on-time buck-converter regulates an output voltage by using the ripple on the output voltage as a PWM ramp signal to control the turn-on instant of the transistor that couples the input voltage to the filter inductor. 
     A constant-on-time buck converter may have a number of advantages over other types of power supplies. For example, a constant-on-time buck converter typically operates at a constant-frequency for steady-state loads, has high efficiency over a wide load range, requires few of any additional compensation components and responds quickly to changes in the load. Furthermore, such buck converter may transition relatively seamlessly between a pulse-width modulation mode (normal load conditions where switching frequency relatively constant) and a pulse-frequency modulation mode (heavy or light load conditions where the switching frequency increases or decreases, respectively). 
       FIG. 1  is a schematic diagram of a traditional constant-on time buck converter, i.e., power supply  10 , and  FIGS. 2A and 2B  are respective plots of the voltages VOUT, Vref, and Q 1   drive  of  FIG. 1 . 
     Referring to  FIGS. 1-2B , the operation of the power supply  10  is described. 
     During a discharge time Toff, the transistor Q 1  is deactivated and the transistor Q 2  is activated such that the decaying current I L  flowing through the inductor L also flows through the closed transistor Q 2 . As I L  decays, VOUT ramps downward toward Vref as shown in  FIG. 2A . 
     When VOUT ramps below Vref, a comparator  12  activates a one shot  14 , which activates Q 1  and deactivates Q 2  for a predetermined “constant-on” or charge time Ton. During the charge time Ton, an increasing current I L  flows from the input voltage Vin, through the transistor Q 1  and the inductor L, to the filter capacitor Co and load Ro. As I L  increases, VOUT ramps upward as shown in  FIG. 2 . 
     After the elapse of the predetermined charge time Ton, the one shot  14  deactivates Q 1  and activates Q 2  and the above-described cycle repeats. 
     There are two components to the ripple on VOUT. 
     The first component is the in-phase component, which is the voltage generated by current flowing through the equivalent series resistance (ESR) of the output filter capacitor Co. The in-phase component is in phase with the inductor current I L , because the voltage across a resistor is in phase with the current through a resistor. 
     The second component is the out-of-phase component, which is generated by the charging and discharging of the output filter capacitor Co. The out-of-phase component is out of phase with the inductor current I L , because the phase of the voltage across a capacitor lags the phase of the current through the capacitor. 
     Therefore, as discussed below, the value of the ESR affects the stability of the feedback loop of the power supply  10 . 
     Generally, the loop is stable where f ESR ≦f SW /π, where f SW =1/(Ton+Toff)(the switching frequency), and f ESR =1/(2π·ESR·Co). 
     Consequently, as long as both the ESR and output filter capacitor Co are relatively large (e.g. ESR≧40 milliohms (mΩ)) then the in-phase component of the ripple on VOUT is the dominant component, and thus the phase shift of the ripple relative to the inductor current I L  is relatively small. That is, the in-phase component of the ripple caused by the portion of I L  that flows through the ESR “swamps out” the out-of-phase component of the ripple. 
     Therefore, a traditional constant-on-time power supply includes an output filter capacitor Co having an ESR that is large enough to provide a stable feedback loop. 
     Recently, filter capacitors having ESR values of 5 mΩ or less have become available; it is sometimes desirable to use such a low-ESR filter capacitor in a buck-converter power supply with a relatively high steady-state switching frequency to reduce the size and cost of the converter. 
     Unfortunately, using such a low-ESR capacitor may render a traditional constant-on-time power supply unstable. An unstable power supply may have too large of a voltage tolerance VT as described below in conjunction with  FIG. 3 , or may oscillate. 
       FIG. 3  is a plot of VOUT of  FIG. 1  simulated for a 13 Ampere (A) step increase in the load current lo followed by a 13 A step decrease in lo, where VIN=10 Volts (V), Vref=1.76 V, L=1 microhenry (μH), Co=800 microfarads (μF), ESR=0, and f SW ≈300 kilohertz (kH). The low value of ESR decreases the stability margin of the feedback loop, and thus causes transient “ringing” on VOUT in response to the step change in lo. Typically, a customer specifies the maximum voltage tolerance VT, which is the difference between the maximum droop of VOUT in response to a step increase in the load current lo and the maximum peak of VOUT in response to a step decrease in lo. In this example, the transient “ringing” on VOUT results in a VT of approximately 70 millivolts (mV). Because VT is inversely proportional to the value of the output filter capacitor Co, one typically chooses a value of Co large enough to provide the specified value of VT. 
     Some integrated-circuit (IC) manufacturers have developed constant-on-time topologies that allow the use of a low-ESR filter capacitor. But unfortunately, these topologies may require additional feedback and compensation circuitry and that the power-supply controller chip have an additional pin, and may yield a relatively poor regulation of VOUT. 
     SUMMARY 
     An embodiment of the invention is a power-supply controller that includes an adder and a control circuit. The adder generates a sum of a sense voltage and a regulated output voltage generated by a filter inductor. The sense voltage is generated by a sense circuit that sources a current to the filter inductor while the inductor is uncoupled from an input voltage, and the sense voltage is related to the sourced current. The control circuit couples the filter inductor to the input voltage for a predetermined time in response to the sum having a predetermined relationship to a reference voltage. 
     Such a power-supply controller may yield a relatively tight and stable regulation of the output voltage with a low-ESR filter capacitor, with no additional compensation components, and with no additional pin on the power-supply-controller chip. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features and advantages of the invention may best be understood by making reference to the following non-limiting description taken in conjunction with the accompanying drawings, in the several figures of which like references identify like elements. 
         FIG. 1  is a schematic diagram of a traditional constant-on time power supply. 
         FIGS. 2A-2B  are respective plots of some of the voltages of  FIG. 1 . 
         FIG. 3  is a plot of the regulated output voltage of  FIG. 1  simulated for a step increase in the load current followed by a step decrease in the load current. 
         FIG. 4  is a schematic diagram of a constant-on-time power supply according to an embodiment of the invention. 
         FIGS. 5A-5C  are plots of voltages of the power supply of  FIG. 4  according to an embodiment of the invention. 
         FIG. 6  is a plot of the regulated output voltage of  FIG. 4  simulated for a step increase in the load current followed by a step decrease in the load current according to an embodiment of the invention. 
         FIG. 7  is a schematic diagram of a temperature-stable circuit that the power supply of  FIG. 4  can include to sense the inductor current during a discharge time Toff according to an embodiment of the invention. 
         FIG. 8  is a block diagram of a computer system that can incorporate the power supply of  FIG. 4  according to an embodiment of the invention. 
         FIG. 9  is a schematic diagram of a constant-on-time power supply according to another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof. The detailed description and the drawings illustrate specific exemplary embodiments by which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is understood that other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the invention. The following detailed description is therefore not to be taken in a limiting sense. 
       FIG. 4  is a schematic diagram of a constant-on-time power supply  40  according to an embodiment of the invention. As further described below, the power supply  40  allows the use of a filter capacitor Co having an ESR of less than 40 mΩ, for example from approximately 0 mΩ-5 mΩ. Furthermore, the power supply  40  requires no additional pin on the power-supply controller integrated circuit (IC), requires no additional compensation circuitry, and yields a relatively tight regulation of VOUT as compared to prior constant-on-time supplies such as the supply  10  of  FIG. 1 . Moreover, for a given VT, the supply  40  may allow one to use a smaller filter capacitor Co than prior supplies such as the supply  10 . 
     The supply  40  includes a power-supply controller IC  42  and a filter circuit  44 , and provides a regulated output voltage VOUT to a load, which is represented by a resistor Ro. 
     In addition to the transistors Q 1  and Q 2 , the comparator  12 , and the one shot  14 , the IC  42  includes an adder  46 , which adds an inverse of a sense voltage V sense  to VOUT, and which provides the result V sum  to an inverting input node of the comparator  12 . V sense  effectively enhances or replaces the contribution to the feedback signal of the in-phase component of the VOUT ripple generated by ESR, and thus allows the power supply  40  to maintain a tight and stable regulation of VOUT even where ESR is relatively low or even near 0Ω. Furthermore, because the on resistance Rds(on) of the transistor Q 2  generates V sense  at the source of Q 2 , the adder  46  is the only additional circuitry that the IC  42  includes as compared to the power supply  10  of  FIG. 1 . In addition, because Q 2  generates V sense  internally, the IC  42  needs no additional pin to receive V sense . Moreover, in an alternate embodiment where Q 1  and Q 2  are disposed external to the IC  42 , a current-sense pin (not shown in  FIG. 4 ) of the IC is typically connected to the source of Q 2  for current-limiting purposes. Consequently, because the current-sense pin inherently receives V sense , the IC  42  needs no additional pin to receive V sense . 
     The filter circuit  44  includes the filter inductor L having an equivalent series resistance Rcs, and includes the output filter capacitor Co having a relatively low ESR. 
       FIGS. 5A-5C  are respective plots of the voltages V sum  and Vref, Q 1   drive , and Q 2   drive  of  FIG. 4  according to an embodiment of the invention. Although these voltages are shown having an approximately 50% duty cycle, they may have other duty cycles as discussed below. 
     Referring to  FIGS. 4-5C , the operation of the power supply  40  is described according to an embodiment of the invention. 
     During a discharge time Toff, the transistor Q 1  is deactivated and the transistor Q 2  is activated such that the decaying current I L  flowing through the inductor L also flows through the transistor Q 2 . As I L  decays, V sum  ramps downward toward Vref as shown in  FIG. 5A . 
     When V sum  ramps below Vref, the comparator  12  activates the one shot  14 , which activates Q 1  and deactivates Q 2  for a predetermined “constant-on” charge time Ton, the value of which for a steady-state load is Ro given by the following equation 
                   Ton   =           K   ⁡     (   VOUT   )       +         I   L     ·   Q     ⁢           ⁢     2     Rds   ⁡     (   on   )             )     Vin             (   1   )               
where K is a constant that depends on the circuit topology and component values. The dependence of Ton on I L ·Q 2   Rds(on)  allows the switching frequency f sw  to be substantially independent of the load current lo within a predetermined range of lo. That is, by changing Ton, and thus the switching duty cycle, the power supply  40  maintains f sw  at a substantially constant frequency for a steady-state load Ro. Furthermore, because at the beginning of Ton the voltage V sense  changes from a negative to a positive voltage with respect to ground, V sum  “jumps” downward by a DC offset voltage V offsetdown . The adder  46  may be designed to effectively “ignore” a positive V sense  by assigning a predetermined value such as 0V to V sense  when V sense  is positive. For example, one may connect a diode (not shown) between the source of Q 2  (cathode) and the inverting input of the adder  46  (anode) so that the diode blocks V sense  where V sense  is positive. Other current topologies for implementing this function are known, and therefore, are not described in detail.
 
     During Ton, an increasing current I L  flows from the input voltage Vin, through the transistor Q 1  and the inductor L, and to the filter capacitor Co and the load Ro. As I L  increases, VOUT, and thus V sum , ramps upward. 
     After the elapse of the predetermined on time Ton, the one shot  14  deactivates the transistor Q 1  and activates the transistor Q 2  and the above-described cycle repeats. Because at the end of Ton V sense  changes from a positive to a negative voltage, V sum  “jumps” upward by a DC offset voltage V offsetup . Furthermore, because I L  is at a minimum at the beginning of Ton and at a maximum at the end of Ton, V offsetdown  is typically less than V offsetup , assuming that the adder  46  ignores V sense  when V sense  is positive as discussed above. 
     Referring to  FIG. 4 , although the adder  46  is shown inverting V sense , the adder may have two noninverting inputs and the supply  40  may include an inverter or other circuitry to invert V sense . 
       FIG. 6  is a plot of VOUT of  FIG. 4  simulated for a 13 Ampere (A) step increase in the load current lo followed by a 13 A step decrease in lo where Vin=10V, Vref=1.76V, L=1 microhenry (μH), Co=800 microfarads (μF), and ESR=0; these are the same parameters as plotted in  FIG. 3  for the power supply  10  of  FIG. 1 . As compared to the supply  10 , the modified topology of the power supply  40  stabilizes the supply so as to virtually eliminate transient “ringing” on VOUT in response to the step changes in the load current, and lowers VT from about 70 mV to about 35 mV. Because for the same parameters, the VT of the supply  40  is approximately ½ the VT of the supply  10 , if one specifies a VT of 70 mV, then he can reduce the value of Co of the supply  40  to 400 μF, which is half the 800 μF value of Co of the supply  10 . That is, using a Co=400 μF in the power supply  10  yields a VT of approximately 70 mV. This reduction in the value of Co may reduce the size and cost of Co as compared to the Co of the supply  10 , and thus may reduce the size and cost of the supply  40  as compared to the supply  10 . 
       FIG. 7  is a schematic diagram of a sensing circuit  50  and the portion of the power supply  40  of  FIG. 1  to which the sensing circuit is connected according to an embodiment of the invention. The sensing circuit  50  can be included in the power supply  40  of  FIG. 4  to provide a temperature-stable value for V sense . That is, the circuit  50  reduces the sensitivity of V sense  to temperature as compared to V sense  being measured directly across Q 2  as shown in  FIG. 4 . The circuit  50  may be entirely or partially disposed on the IC  42 , or may be totally disposed external to the IC  42 . However, where the sensing circuit  50  is disposed entirely on the IC  42 , the components of the sensing circuit may be more closely matched to each other; therefore, the sensing circuit may provide V sense  with a lower temperature sensitivity than where some or all of the components of the sensing circuit are disposed off chip. 
     In addition to the transistor Q 2 , the sensing circuit  50  includes transistors Q 3  and Q 4 , a differential amplifier  52 , and a resistive sense element  54 , here a sense resistor. The transistors Q 2  and Q 3  have similar dimensions, and the gain G of the amplifier  52  and the value of the sense amplifier  54  are selected such that I sense /I Q2  is small, for example 1/1000. Also, the thermal response of Q 2  closely matches that of Q 3 ; a sufficient matching of the thermal response typically occurs where Q 2  and Q 3  are disposed on the same IC. 
     The operation of the sensing circuit  50  is now described in conjunction with  FIGS. 4 and 7  according to an embodiment of the invention. For purposes of example, the temperature sensitivity of the resistor  54  is ignored, and the gain G of the amplifier and the value of the sense resistor  54  are selected such that I sense /I Q2 ≈1/1000. 
     When the one shot  14  ( FIG. 4 ) deactivates the transistor Q 1  and activates the transistor Q 2  during the discharge time T off  ( FIG. 5B ), the one shot also activates the transistor Q 3 . 
     The amplifier  52  generates an output signal Q 4   drive  that equals G(Vs Q3 −Vs Q2 ), where Vs Q3  is the voltage at the source of the transistor Q 3 , and Vs Q2  is the voltage at the source of the transistor Q 2 . Because Q 2  and Q 3  have similar dimensions and I sense &lt;&lt;I Q2 , Vs Q2 &lt;Vs Q3  for I Q2 &gt;0. 
     The signal Q 4   drive  causes the transistor Q 4  to source to the element  54  the current I sense , which is proportional to Vs Q3 −Vs Q2 ; consequently, V sense  is also proportional to Vs Q3 −Vs Q2 . More specifically, because the transistor Q 4  acts as a voltage follower, I sense ≈[G(Vs Q3 −Vs Q2 )−Vt]/(sense element  54 ), where Vt is the threshold voltage of the transistor Q 4 . Furthermore, because I sense  is relatively small, Vs Q3  remains relatively constant as compared to Vs Q2  such that I sense  varies substantially linearly with Vs Q2 . And because Vs Q2  is the voltage across the Rds(on) of Q 2 , and thus varies substantially linearly with I Q2 , I sense  varies substantially linearly with I Q   2 . Moreover, because I sense &lt;&lt;I Q2 , I Q2  approximately equals I L  (i.e., I Q2 ≈I L ); consequently, I sense  varies substantially linearly with I L , as is desired in this embodiment. 
     Because Q 2  and Q 3  are thermally matched, Vs Q3  and Vs Q2  shift by substantially the same amount in response to a change in temperature. But even with this temperature-induced shift, the difference between Vs Q3  and Vs Q2 , and thus Q 4   drive , I sense , and V sense , remain substantially unchanged with temperature for a given I L . Put another way, the similar temperature-induced shifts in Vs Q3  and Vs Q2  compose a common-mode signal at the input nodes of the differential amplifier  52 , which rejects this common-mode signal, thus rendering V sense  less sensitive to temperature than if V sense  were taken directly across the transistor Q 2  as shown in  FIG. 4 . 
       FIG. 8  is a block diagram of a computer system  60 , which can incorporate the power supply  40  of  FIG. 4  according to an embodiment of the invention. The supply  40  may provide regulated voltage VOUT to a processor  62 , a memory  64 , or another component (not shown) of the computer system  60 . Alternatively, the power supply  40  may be installed in any other type of electronic system. 
     FIG. 9 is a schematic diagram of an alternate embodiment of the supply  40 , where the transistor Q 2  is replaced with a diode D 1  and a resistor or other resistive element R 1 . The voltage V sense  may be taken across the R 1  as shown, or may be taken across the combination of R 1  and D 1 . 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.