Abstract:
An electronic circuit includes a first and a second PLL stage (PLL 1 , PLL 2 ) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL 2 ) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL 1 ) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL 1 ) to the input signal (IN) and, upon locking, sets switches (S 1 , S 2 ) to couple the output of the first PLL circuit (PLL 1 ) to the input of the second PLL circuit (PLL 2 ), and to couple the output of the second PLL circuit (PLL 2 ) to the input of the first PLL circuit (PLL 1 ).

Description:
FIELD OF THE INVENTION  
       [0001]     The invention relates to an electronic circuit including two PLL circuits which can be switched between different configurations. In particular, the invention relates to PLL circuits in which controlled oscillators have to be locked with respect to frequency and phase to an input clock.  
       BACKGROUND OF THE INVENTION  
       [0002]     This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.  
         [0003]     Electronic circuits which are supplied an input signal at a certain clock frequency often need to process the received input signal in further processing stages. Therefore, fixed relationships between the clocks used inside the further processing stages and the input signal are required. A further requirement is that the clocks have a very low jitter, i.e., the very low fluctuations in frequency or phase. To this end the input signal is often supplied to a phase lock loop circuit, or PLL circuit, which synchronises a controllable oscillator with the input signal. One particular type of PLL circuits uses a temperature compensated voltage controlled oscillator (TCXO). TCXOs exhibit excellent temperature and jitter behaviour. Oscillators of this type, however, have a very small frequency pulling range, i.e. the output frequency of this type of oscillator only be changed within a small range around the nominal frequency. As a result, PLL circuits using TCXO oscillators have a very small locking range, i.e. the difference between the input signal frequency and the nominal frequency of the oscillator must not be very large. PLL circuits that have a larger locking range can be built using voltage controlled oscillators (VCXO), which have a larger pulling range. VCXOs, however, are less stable in frequency and phase compared to TCXOs and thus the output signal of a PLL circuit using VCXOs may have a higher amount of clock jitter compared to a PLL circuit using a TCXO.  
       SUMMARY OF THE INVENTION  
       [0004]     It is, therefore, desirable to have a circuit that provides locking to an input signal, producing an output clock signal with low jitter while at the same time exhibiting a large locking range.  
         [0005]     The invention suggests combining two PLL circuits having individual control stages, wherein one of the PLL circuits uses a TCXO and the other one uses a VCXO as an oscillator. The two PLL circuits are either used individually or in a cascaded manner, depending on the operating mode.  
         [0006]     In a first operating mode the two PLL circuits are connected in a first configuration that provides a larger locking range. To this end the input signal is supplied to both, the first and the second PLL circuit. The first PLL circuit has a controllable oscillator that has a relatively small pulling range and attempts to lock onto the input signal in the known way. Controllable oscillators having a relatively small pulling range but good phase frequency and temperature stability are, for example, temperature controlled crystal oscillators, or TCXOs. The controllable oscillator of the first PLL circuit has, however, the capability of oscillating with a nominal frequency in case of the absence of an input signal. In this case the first oscillator acts as a clock master which provides an excellent jitter quality. Further, the controllable oscillator of the first PLL circuit has a very stable phase and frequency behaviour. The second PLL circuit has a controllable oscillator which has a relatively large pulling range compared to the controllable oscillator of the first PLL circuit. The controllable oscillator of the second PLL circuit is, for example, a voltage controlled crystal oscillator, or VCXO. In the following specification the terms VCXO and TCXO are used as synonyms for controllable oscillators having a large as a small pulling range, respectively. The second PLL circuit thus has a large a locking range. In this first operating mode it also attempts to lock onto the input signal. As the second PLL circuit has a larger locking range it is very likely that it will lock onto the input signal at first. A lock detector provides information about the locking state of the first PLL circuit which has a smaller locking range than the second PLL. When the first PLL circuit is locked on to the input signal the two PLL circuits are connected in a second configuration that provides improved jitter behaviour compared to the first configuration, while having a smaller locking range. This operating mode is also referred to in the following as a second operating mode. Whenever the lock detector determines that the first PLL circuit is not locked the two PLL circuits are again connected in the first configuration. In case no input signal is present at all the TCXO oscillator of the first PLL circuit is oscillating freely at its nominal frequency. The output signal of the first PLL circuit is then supplied to the second PLL circuit, which locks onto the output signal of the first PLL circuit. This operating mode is also referred to in the following as a third operating mode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]     The invention will be described in the following with reference to the drawing. In the drawing,  
         [0008]      FIG. 1  shows a block diagram of the inventive circuit;  
         [0009]      FIG. 2  shows a block diagram of the inventive circuit in a first operating mode;  
         [0010]      FIG. 3  shows a block diagram of the inventive circuit in a second operating mode; and  
         [0011]      FIG. 4  shows a block diagram of the inventive circuit in a third operating mode. 
     
    
       [0012]     In the figures, same or similar elements are referenced with the same reference symbol.  
       DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0013]     In  FIG. 1 a  block diagram of the inventive circuit is shown. An input signal IN is supplied via a first divider D 1  to a first input of a first phase comparator PC 1  of a first PLL circuit PLL 1 . To a second input of the first phase comparator PC 1  an output signal of a first controllable oscillator VCO 1  is supplied via a second divider D 2  and a first switch S 1 . The first controllable oscillator VCO 1  is controlled by the output signal of the first phase comparator PC 1  which is supplied to the first controllable oscillator VCO 1  via a first filter LPF 1 . The output signal of the first controllable oscillator VCO 1  is further supplied to a lock detector LD, which also receives the input signal IN after division in the first divider D 1 . The lock detector LD controls the first switch S 1 , which selectively applies the output signal of the first controllable oscillator VCO 1  or the output signal of a second controllable oscillator VCO 2  to the second input of the first phase comparator PC 1 . The second controllable oscillator VCO 2  is part of the second PLL circuit PLL 2  and provides the output signal of the inventive circuit. The second PLL circuit PLL 2  further includes a second phase comparator PC 2  and a second filter LPF 2 . Like described for the first PLL circuit PLL 1  the output signal of the phase comparator PC 2  is applied to the second controllable oscillator VCO 2  and via the second filter LPF 2  for controlling the frequency of the output signal. The output signal is fed back to a first input of the second phase comparator PC 2  via a third divider D 3 . A second switch S 2  selectively applies the input signal IN downstream of the first divider D 1  or the output signal of the first PLL circuit PLL 1  to a second input of the second phase comparator PC 2 .  
         [0014]      FIG. 2  shows a schematic block diagram of the inventive circuit in a first operating mode. Solid lines indicate used connections carrying signals, while dashed lines indicate connections that are not used in this operating mode. An input signal IN is fed to a first input of a first phase comparator PC 1  via a first divider D 1 . The output signal of the first phase comparator PC 1  is filtered in a first filter LPF 1  and controls a first controllable oscillator VCO 1 . The first controllable oscillator preferably is a TCXO. The output signal of the first controllable oscillator VCO 1  is applied to a first selector switch S 1  via a second divider D 2 . The first selector switch S 1  is set to supply this signal to a second input of the first phase comparator PC 1 . The output signal of the first controllable oscillator VCO 1  is also supplied to a lock detector LD which controls the first selector switch S 1 . The frequency-divided input signal IN is also supplied to the lock detector LD as well as to an input of a selector switch S 2  which is set to apply this signal to a first input of a second phase comparator PC 2 . The selector switch S 2  is likewise controlled by the lock detector LD. In this operating mode the two PLL circuits PLL 1  and PLL 2  that are formed by the respective components both try to lock onto the input signal IN. As the locking range of the second PLL circuit PLL 2  is larger than that after first PLL circuit PLL 1  the output signal of the inventive circuit will be locked rather quickly onto the input signal IN, however with a certain amount of jitter due to the properties of the second controllable oscillator VCO 2 . Despite the amount of jitter the output signal OUT of the inventive circuit is locked to the input signal IN. In case the frequency of the input signal IN lies in the locking range of the first PLL circuit PLL 1  locking will occur. The lock detector detects the locking status of the first PLL circuit PLL 1  and, upon detecting locking of the first PLL circuit PLL 1  set the selector switches S 1  and S 2  accordingly to enter the second operating mode.  
         [0015]     In  FIG. 3 a  schematic block diagram of the inventive circuit in the second operating mode is shown. After detecting locking of the first PLL circuit PLL 1  to the input signal IN the lock detector LD set the selector switches S 1  and S 2  to feed the output signal of the first PLL circuit PLL 1  to the second phase comparator PC 2  and the output signal of the second PLL circuit PLL 2  to the first phase comparator PC 1 , respectively. The first PLL circuit PLL 1  locked onto the input signal IN provides a very stable output signal having low jitter. The second PLL circuit PLL 2  locks onto the stable output signal of the first PLL circuit PLL 1 .  
         [0016]     In  FIG. 4 a  schematic block diagram of the inventive circuit in a third operating mode is shown. In this operating mode no input signal IN is present, and the first controllable oscillator VCO 1  oscillates freely at its nominal frequency. The selector switch S 2  is set to supply the output signal of the first controllable oscillator VCO 1  to the second PLL circuit PLL 2 , which locks onto that signal, thereby providing a stable output frequency depending on the frequency of the first controllable oscillator VCO 1 . The output signal of the first controllable oscillator VCO 1  is also supplied to the lock detector LD which also receives the input signal IN, if present. If the lock detector LD detects an input signal IN the selector switches S 1  and S 2  are set to enter the first operating mode. It is to be noted that the switch positions of the selector switches S 1  and S 2  may also be chosen to be similar to those of the second operating mode. In the third operating mode the first controllable oscillator VCO 1  is disconnected from the first filter LPF 1  and will oscillate at its nominal frequency. In one development the control input of the first controllable oscillator VCO 1  is set to a predetermined level, e.g., by a resistor divider network R 1 , R 2  between a supply voltage V+ and ground.  
         [0017]     The divider ratios of the first and the second divider D 1 , D 2 , D 3  are chosen according to the frequencies of the input signal IN and the oscillator frequencies of the first and the second controllable oscillator VCO 1 , VCO 2 .  
         [0018]     It is to be noted that the first and the second divider D 1 , D 2 , D 3  need not necessarily be present in the PLL circuit at all, depending on the input frequency range of the phase comparator. Further, depending on the way the phase comparator is built, the filter LPF 1  need not necessarily be present at all in the PLL circuit.  
         [0019]     In the specifications above the terms VCXO and TCXO have been exemplarily used in order to distinguish between controllable oscillators having different properties. It is to be noted that any of the letter having the respective properties can be used instead of those used in the specification.  
         [0020]     The lock detector LD determines locking of the first PLL circuit PLL 1  by evaluating the temporal distance of corresponding edges of the divided input signal IN and the output signal of the first PLL circuit PLL 1  supplied to it. Corresponding edges are the rising or the falling edges of the two signals, respectively. As long as the temporal distance between the edges of the two signals changes PLL 1  has not locked onto the input signal IN. Only if the temporal distance does not change, or if the change rate is below a predetermined value over a predetermined period of time, e.g. due to temperature drift, the PLL 1  has locked onto the input signal IN and the lock detector changes over to the second operating mode.  
         [0021]     One embodiment of the lock detector provides a counter that is started upon a first slope, either rising or falling, of a first signal out of the two signals applied to the lock detector LD. The counter is stopped in response to the corresponding slope of a second signal out of the two signals applied to the lock detector LD. The count value is stored and compared to subsequent count values. As long as the respective count values do not change, or change only at a predetermined, relatively small rate of change over a predetermined period of time, the status of the first PLL circuit PLL 1  is considered to be locked.  
         [0022]     When switching over between two of the different operating modes described above, the lock detector is, in one embodiment, inhibited for a predetermined period of time. This may be required due to transient behaviour of the oscillators and PLL circuits and the transients of the respective input signals.  
         [0023]     The above the specification, examples and drawings provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims herein after appended.