Abstract:
An adaptive impedance matching module having an adjustable impedance matching network with an input for receiving an RF power source and an output to be connected to an antenna, and first and second voltage measurement device configured to sense a voltage at respective first and second nodes on the impedance matching network. A network adjuster circuit is provided to switch the impedance matching network between a first state where first and second voltages are sensed on the respective first and second nodes and a second state where third and fourth voltages are sensed on the respective first and second nodes. Processing circuitry is provided which determines the matched load impedance based upon the first, second, third and fourth sensed voltages and including matching adjustment circuitry configured to adjust the matching impedance in the event the matched load impedance differs from a target load impedance by more that a predetermined amount.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to RF impedance measurement and in particular to RF impedance measurements using two point voltage sampling without a phase detector. Some embodiments also relate to adjusting an impedance matching network after the measurement. 
     2. Description of Related Art 
     Mobile handsets such as cellular phones are being manufactured using higher levels of integration and use in broader frequency band coverage. As a result, the performance limits of embedded antenna technology are being stretched. Variations in load impedance at the antenna due to environmental changes such as the position at which the phone is held, the frequency band being used and other contributors create a mismatch or increased voltage standing wave ratio (VSWR) at the antenna port. In addition, the body effects of a head or hand near the antenna contribute to capacitive loading which also results in an impedance mismatch. This can lead to a shift in antenna center frequency and an increased VSWR mismatch. In addition to reception problems, any mismatch will further result in a reduction in power radiated from the antenna. 
       FIG. 1  depicts a prior art RF system which includes an adaptive impedance matching network. The system includes an RF power amplifier PA  20  having an output coupled to the input of a duplexer  22 . The duplexer directs the RF signal from amplifier  20  to the system antenna  24  by way of the adaptive impedance matching network  26 . Duplexer  22  further channels RF signals received on the antenna to a system receiver (not depicted). The adaptive impedance matching network includes a tunable impedance matching network  30  which matches the impedance of the antenna to some target value that matches that of the duplexer. Typically, an antenna impedance has a real component Rant ranging from 30 to 100Ω and a reactive component j Xant of 0 to +100 jΩ. The matching network converts the antenna impedance to some target impedance such as an impedance matching that of the coupler  28 . 
     The antenna impedance Zant can change, as previously noted, due to a change in the physical environment surrounding the antenna. The impedance at the input of the tunable matching network  30  is monitored by periodically measuring the amplitude of the RF voltage at the input and output of the directional coupled  28  using respective peak detectors  32 A and  32 B. The phase relationship between the two detected voltages is measured using a phase detector  34 . The peak voltage measurements and the phase measurement are then provided to a processing device  36  such as a digital signal processor to compute the impedance. In the event the measured impedance differs from the target impedance due to a change, by way of example, in the antenna characteristics, the processor adjusts the tunable matching network  30  as needed to return to the target impedance. 
     The above-described approach requires an impedance sensing section which is separate from the impedance matching section. In addition, a phase detector is used. A phase detector having good accuracy and low current is difficult to achieve over the 690 Mhz to 2690 Mhz range of interest in many cell phone applications. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, an RF impedance improved detection scheme is disclosed which does not rely upon a phase detector and which does not require a sensing element separate from the matching network. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a prior art RF system which incorporates an adaptive impedance matching network to compensate for changes in an antenna impedance. 
         FIG. 2  is a diagram of an RF system which includes an adaptive impedance matching network in accordance with one embodiment of the present invention. 
         FIG. 3  is a phasor diagram illustrating part of the operation of the  FIG. 2  embodiment and which does not rely upon the use of a phase detector. 
         FIGS. 4A-4D  are timing diagrams of a simulation further illustrating the operation of the  FIG. 2  embodiment. 
         FIG. 5  is a diagram of showing an alternative embodiment that uses adjustable attenuator circuitry do reduce the dynamic range requirements of the voltage detectors. 
         FIG. 6  is a plot of a complex plane showing the methodology of adjusting the matching network after a change in the antenna impedance is detected. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring again to the drawings,  FIG. 2  shows an adaptive RF matching network module  38  in accordance with one embodiment of the present invention. An RF power amplifier  20  is coupled to a first port of the network module  38  by way of a duplexer  22  followed by an RF switch  40  which switches between various transceiver paths to accommodate various mobile communication standards such as GSM, WCDMA, LTE, etc. Another port of the network module  38  is for connecting to an antenna  24 . Antenna  24  functions to radiate the RF energy from the amplifier  20  and to receive RF signals which are provided to receiver circuitry by way of the duplexer  22 . In many applications such as cellular phones, antenna  24  is a narrow bandwidth miniaturized antenna having a high Q. As a result, the antenna is subject to detuning due to fluctuating body effects and changes in the handset form factor. This detuning has an adverse effect on transmitted radiated power efficiency and over the air receiver sensitivity. 
     The adaptive matching network module  38  initially transforms the impedance of the antenna  24  to a target impedance which may be, by way of example, a 50Ω real impedance. Environmental fluctuations may cause the impedance of antenna  24  to change so that the matching network is no longer optimal. As will be described, the adaptive matching network module  38  monitors the impedance of the matched network and, if the impedance varies from the target value, will adjust the matching network so that the impedance is returned to the target value. 
     The exemplary matching network used in module  38  is a pi type network which includes a series connected inductor Lsense and a pair of shunt connected capacitor arrays C 1  and C 2  disposed on either side of the inductor. The capacitor arrays each include an array  44 A and an array  44 B of RF-MEMS (micro-electromechanical system) capacitive switches Cn to C 1   a . The capacitive switches are preferably disposed in a binary weighted manner, with there being five capacitive switches connected in parallel, with the relative capacitive values being C, 2C, 4C, 8C and 16C. The five capacitive switches are individually enabled and disabled to provide a total capacitance ranging from C to 31C in increments of C. As is well known, high voltage switching circuitry (not depicted) is used to control the state of each of the five switches. Lsense has a typical inductance of 2 to 8 nano-Henries, with the value of C of the capacitive switches being 0.5 to 4.0 pF. Each capacitor bank further includes a small (Co&lt;0.125 pF) switched capacitor which is periodically connected in parallel with each of the MEMS capacitive switches  44 A and  44 B. The smaller the value of Co, the greater the voltage detection accuracy required of the RF detectors employed as peak detectors  52 A and  52 B to be described. A dither clock present on line  50  is used to control the states of switches  48 A and  48 B which operate to switch capacitors Co in circuit and out of circuit. The frequency of the dither clock is determined by the required response time of the RF impedance measurement, which may be as low as a 100 Hz or up to around 1 MHz. Preferably the dither frequency is not so high as to introduce spikes on the RF sensing lines. 
     In addition to forming part of the impedance matching, inductor Lsense also functions as part of the impedance sensor. A pair of peak voltage detectors  52 A and  52 B are connected to detect respective voltages V 1  and V 2  at opposite ends of inductor Lsense. The voltages are periodically sensed when the switched capacitors  46 A and  46 B are connected in circuit by switches  48 A and  48 B and then sensed a second time when the capacitors are switched out of circuit. As will be explained, these four voltage measurements permit the impedance looking into the matching network to be determined. In the event that measured impedance is out of range, the matching network is adjusted by way of capacitor switches  44 A and  44 B to bring the impedance back into range. A control block  54  provides various control functions, including the production of the dither clock on line  50 , control of the peak detectors  52 A and  52 B, the computation of the actual network impedance and the re-adjustment of the adaptive matching network to bring the impedance back into range. 
     Note that  FIG. 2  shows a pair of dither caps  46 A and  46 B having a value CO. Dither cap  46 A can be used to determine some useful information regarding the matching network and antenna  24 . However, the following description and analysis is based upon the use of dither cap  46 B alone. 
       FIG. 3  is a phasor diagram (not to scale) illustrating the manner in which the four measurements can be used to determine the impedance Z L , which is the impedance looking from the node where V 2  is sampled towards the antenna  24  impedance. Thus, Z L  is the parallel combination of the matching network output capacitance C 2  (sum of parallel capacitors  44 B and  46 B) and the antenna impedance Z ant =R ant +j X ant . Impedance Z L  can be expresses as follows:
 
 Z   L   =R   L   +jX   L   (1)
 
     Voltages V 1  and V 2  are measured using respective peak detectors  52 A and  52 B when switch  48 B is opened based upon the polarity of the dither clock on line  50  so that dither capacitor  46 B (Co) is out of circuit. Thus, it can be seen from the  FIG. 3  diagram where V 1  and V 2  can be plotted on the complex plane showing that the difference between the two voltages is X S  which represents the impedance of the sense inductor Lsense. After the first measurements are made, the dither clock then closes switch  48 B so that capacitor  46 B is connected in circuit. Voltages V 12  and V 22 , which correspond to V 1  and V 2  for the previous measurement, are then measured using the respective peak detectors  52 A and  52 B. These two voltages V 12  and V 22  can also be plotted on the complex plane along with V 1  and V 2 . The difference between these voltages is represented by the impedance X S  of the sense inductor Lsense less the impedance Xco of the switching capacitor  46 B. Inspection of the  FIG. 3  diagram indicates that the values R L  and X L  of the impedance Z L  (which includes the antenna impedance Z ant  as one component) can then be ascertained without the use of a phase detector. 
     The value of Z L  is preferably determined using signal processing circuitry disposed within control unit  54 . The phase angle φ is expressed as follows:
 
Cos φ=−0.5[ Xdp   2 ( Vr 1 2   −Vr 2 2 )+ X   S   2 ]/( X   S   *Xdp*Vr 1)  (2)
 
     where,
         Vr 1  is the ratio of V 1 /V 2 ;   Vr 2  is the ratio of V 12 /V 22 ;   Xdp is the impedance of the dither cap  46 B; and   X S  is the impedance of inductor Lsense.       

     Once the phase angle is known, the reactive component X L  and real component R L  of the impedance Z L  can be calculated as follows:
 
 X   L =( X   S /2)[( Vr 1 2 −1)/( Vr 1 2 +1−2 Vr 1 cos φ)−1]  (3)
 
and
 
 R   L   =[X   S   2 /( Vr 1 2 +1−2 Vr 1 cos φ)− X   L   2 ] 1/2   (4)
 
     Assuming that the value of Z L  has moved away from the target value because, for example, of changes in the antenna environment, the signal processor in the control unit  54  will proceed to alter the matching characteristics in the matching network. As will be described in greater detail, this is carried out by changing the value(s) of capacitors  44 A and  44 B. 
       FIGS. 4A-4D  are timing diagrams further illustrating the operation of the subject impedance matching module  38 . Waveform  56  of  FIG. 4A  represents the dither clock which causes the capacitor  46 B (Co) ( FIG. 2 ) to be switched into the matching network and to be switched out of the matching network. As previously described, when capacitor Co is present in the network, the two peak detectors  52 A and  52 B sense the peak voltages on opposite sides of inductor Lsense to determine V 1  and V 2 . The ratio of V 1 /V 2 , value Vr 1 , is then produced. It would also be possible to produce the ratio Vr 1  directly without having to determine the separate values of V 1  and V 2 . When capacitor Co is switched out of the matching network, the peak voltages are sensed to determine the values of V 21  and V 22 . The ratio Vr 2  of V 21 /V 22  is then determined. 
     A change in the antenna load impedance is simulated in the timing diagrams at a time T 1 =25 μs. Prior to that time, it can be seen from  FIG. 4B  that the ratio Vr 1  is approximately 2.6 and the ratio Vr 2  is approximately 2.8. The two ratios are then processed per equations (2), (3) and (4) by control unit  54  to produce a real component R L1  and an imaginary component X L1  of the impedance R L . In this example, the initial impedance Z L1  (which includes the antenna impedance Z ant  as one component as previously noted) is as follows:
 
 Z   L1   =R   L1   +jX   L1 =100− j 35.4 Ω  (5)
 
     The change in antenna impedance could be caused, by way of example, by a change in the antenna environment such as adjusting the manner in which a cell phone is held. As can be seen in  FIG. 4B , the change in antenna impedance at time T 1  is rapidly detected as evidenced by a change in the voltage ratios Vr 1  and Vr 2 . Vr 1  changed from about 2.6 to 2.5 and Vr 2  changed from about 2.8. The control unit  54  then recalculates the new impedance values Z L2 , again using equations (2), (3) and (4), as follows:
 
 Z   L2   =R   L2   +jX   L2 =50 −j 17.7 Ω  (6)
 
     If it is assumed that the target impedance is reflected by equation (5) above, the control unit  54  will then precede to alter the matching network by way of the MEMS  44 A and  44 B so that the matched impedance has returned to the target impedance. One approach for adjusting the matching network will now be described. As will be seen, only the change in matching network capacitance to arrive at the target values is needed and not the actual final value of that capacitance. 
     As was previously shown by equations (3) and (4), the values for R L  and X L  represent the respective real and imaginary components of the measured impedance. Using these values, the needed change in value of matching network capacitances  44 A and  44 B, the MEMS capacitor arrays, is determine using a signal processor or the like. A chart of the complex impedance plane is shown in  FIG. 6  in order to illustrate the manner in which the impedance matching module  38  operates to compensate for changes in the impedance Z ant  of antenna  24 . In order to combine parallel components, it is preferred that the values be in terms of admittance so that values can be simply added together. Similarly, for series components, it is preferred that values be in terms of impedance so that they can also be combined by adding. The chart of  FIG. 6  shows both approaches. When only an imaginary component of an admittance is being changed, the admittance moves along a constant conductance circle, with all of the circles intersecting at the origin  68 . 
     Initially, assume that that the matching network is at the optimum value to transform the present antenna impedance Z ant  to the optimum value in this example of in this example of 50+j0Ω purely real resistance. This condition is represented on the  FIG. 6  chart at point A. As can be seen, point A lies of the real axis at the 50Ω point which falls on a constant conductance circle of 20 milli Siemens. If the antenna impedance Z ant  is changed due to changes in the antenna environment for example, the antenna impedance Z ant  will change. The impedance measured by the matching network module  38  is actually Z L , the parallel combination of Z ant  and impedance Z C2  of capacitor C 2  of the matching network. Thus, when Z ant  changes so does Z L , as indicated by the transition from point A to point B of the  FIG. 6  chart. 
     In order to return the altered impedance to the target impedance at point A, it is usually necessary to adjust both the value of capacitances C 1  and C 2  of the matching network. First, the value of C 2  is changed by ΔC 2  to provide a new value of Z L , referred to here as Z L new. By adding a parallel reactance, the impedance moves along an arc  72 A of a constant admittance circle from point B to point C. The distance and direction of the movement is a function of size of the change ΔC 2  and the polarity. In the present example, the polarity is positive (C 2  is to be increased). The magnitude of ΔC 2  is determined so that point C is at a location in the complex plane such that, when the fixed value inductor Lsense of impedance X S  is added in series, the combined, new value of impedance will fall on the constant admittance circle  69  of 20 milli-Siemens. That value at point D is the sum of Z L new plus X S . At this point, a value of C 1  of the matching network is then produced which provides a reactance X 1  which is of a magnitude sufficient to move the impedance Z L new plus X S  to close to a pure resistance of 50Ω as represented by point A. Since the MEMS cap arrays  44 A and  44 B that make up the majority of respective capacitances C 1  and C 2  have only a finite number of possible values, the final impedance value may differ somewhat from the ideal value of 50Ω. 
     In order to carry out the above transformation, one approach is to first determine the change in capacitance C 2  to move from point B to point C of  FIG. 6 . The needed change in reactance ΔX 2  can be determined as follows:
 
Δ X   2   =−X   S   [X   S   X   L   +R   L   2   +X   L   2 −( R   L (− X   S   R   L 50 R   L   2 +50 X   L   2 )) 1/2 ]/[( X   L   +X   S ) 2   +R   L ( R   L −50)]  (7)
         where   X S  is the impedance of the inductor Isense;   X L  is the measured reactive component of Z L  per equation (3);   R L  is the measured resistive component of Z L  per equation (4); and   the value  50  is target impedance in ohms.       

     Thus, the needed change to the present value of C 2  in order to move from point B to point C of  FIG. 6  is as follows:
 
 ΔC   2 −1/(ωΔ X   2 )  (8)
         where ω is the radial frequency 2nf.       

     The new value of C 1  needed to shift the full combined impedance (matching network+Zant) from point D back to point A is then determined. The equation for calculating the impedance X 1  provided by the new value of C 1  is set forth below. Variables Rn and X n , to be defined later, are used to simplify the following equation for X 1 .
 
 X   1 =5[10 X   n +(−100 R   n   2 +2 R   n   X   n   2 +2 R   n   3 ) 1/2 ]/( R   n −50)  (9)
         where,   R n  is a variable determined by equation (11) below; and   X n  is a variable determined by equation (12) below.       

     The new value of C 1  is then as follows:
 
 C   1 =−1/(ω X   1 )  (10)
         where ω is the radial frequency 2nf.       

     The values of variables R n  and X n  used in equation (9) are as follows:
 
 R   n =(Δ X   2   2   R   L )/[ R   L   2 +(Δ X   2   +X   L ) 2 ]  (11)
 
and
 
 X   n   =X   S   +[R   L   2   ΔX   2   +X   L   2   ΔX   2   +X   L   ΔX   2   2   ]/[R   L   2 +(Δ X   2   +X   L ) 2 ]  (12)
         where   X S  is the reactance of inductor Lsense;   ΔX 2  is the reactance of C 2  per equation (7); and   R L  and X L  are the real and imaginary parts of Z L  per equations (3) and (4).       

     Thus, once the new value of C 1  of the matching network has been provided per equation (10), the impedance looking into the matching network on the C 1  side will have returned to point A of  FIG. 6  which is at or near a pure resistance of 50Ω. Thus, once the actual values of C 1  and C 2  in the  FIG. 2  impedance matching network have been updated, the impedance matching sequence is completed. 
     Note that MEMS switched capacitors  44 A and  44 B if  FIG. 2  could be replaced with voltage controlled capacitances in the form of varactors. In that case, switched capacitors  46 A and  46 B can be eliminated. The impedance network changes in response to the dither clock are carried out by altering the magnitude of the varactor control signals in the form of a specific delta voltage to achieve the required difference in capacitance. That change in varactor capacitance can be used as value Xdp in equation (2) above to calculate X L  and R L . 
       FIG. 5  shows an alternative adaptive matching network module  58  which is similar to that of  FIG. 2  in that a pi type architecture is used which includes a series inductor L 1  flanked by a pair of parallel capacitor banks. A first one of the capacitor banks includes an array of capacitive MEMS switches  44 A as used in the  FIG. 2  embodiment along with three capacitors C A , C B  and C C  connected in series with one another and in parallel with capacitive switches  44 A. The other capacitor bank includes an array of capacitive MEMS switches  44 B as used in the  FIG. 2  embodiment and three capacitors C C , C D  and C E  connected in series with one another and in parallel with capacitive switches  44 B. In this embodiment, the dither cap (not explicitly depicted) is incorporated into the MEMS capacitive switch  44 B. As previously noted, the MEMS switch can selectively connect capacitances C, 2C, 4C, 8C and 16C is parallel. The dither cap is switched in and out by switching the control signal to switch  44 B so that the smallest capacitance value C is either in and out of circuit. Note that the dither cap  46 B of the  FIG. 2  embodiment may be implemented into MEMS capacitor array  44 B and controlled in this same manner. 
     As can be seen in  FIG. 5 , each of the peak detectors  52 A and  52 B has an associated sensing node which can be changed in response to the state of switches  60 A and  60 B. Peak detectors typically have a limited input range over which they provide an accurate measurement. The dynamic range of the ratio V 1 /V 2 , which is value Vr 1  of equation (2), can vary over 30 dB for antenna impedances equivalent of VSWRs of up to 8. Add to this the fact that the antenna output power can range from 0 to 30 dBm, the peak detector  52 A and  52 B sensors can have input dynamic range requirements of 60 dB which can be difficult to achieve. 
       FIG. 5  shows one approach for dealing with such a large input voltage dynamic range. Relatively small value capacitors C A , C B  and C C  form a voltage divider, as do capacitors C D , C E  and C F . Preferably corresponding capacitors C A  and C D  have the same value, and C B  and C E  each have the same value and capacitors C C  and C F . each have the same value. For relatively strong RF signals at the matching network, as determined by an RF detector  65 , respective switches  60 A and  60 B connect nodes  62 B and  64 B as the detector sensing nodes for maximum attenuation. For relatively weaker signals, nodes  62 A and  64 A are selected for reduced attenuation. Thus, in addition to functioning as part of the matching network, capacitors C A , C B , C C , C D , C E  and C F  function together as a pair of adjustable attenuators. Since the attenuators do not include resistances, no loses result. 
     As previously noted, the impedance matching networks of  FIGS. 2 and 5  are each pi type networks that include three primary impedance components including a series inductance flanked by a pair of parallel capacitances. Other types of matching networks can be used, but it is preferred that such networks include at least two primary impedance components (where either similar parallel or similar series components are combined into a primary component) and preferably at least three to provide a sufficiently wide range of impedance matching to cover essentially all possible impedance mismatches. On example of a two primary impedance components network would be the three component network of  FIG. 2  with capacitances  46 A/ 44 A deleted. Although this matching network does not provide the same matching range as that of  FIG. 2 , it is very useful in those instances where a wide range of matching is not needed while still providing an impedance detection capability. 
     The RF detectors are implemented in both the  FIG. 2  and  FIG. 5  embodiments in the form of peak detectors  52 A and  52 B. However, rather than using peak detectors it would be possible to use any other types of detectors including RMS, linear and logarithmic. In addition, the greater the sensitivity of errors of the detected voltages V 1  and V 2  or V 12  and V 22  the greater is the required accuracy of the RF detectors. Conversely, the smaller the sensitivity of errors of the detected voltages the less accuracy is required of the RF detector. 
     Thus, various embodiments of an adaptive impedance network and associated circuitry have been disclosed. Although these embodiments have been described in some detail, certain changes can be made by those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.