Abstract:
A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of memory chips. 
     2. Discussion of Related Art 
     A known integrated memory IC  100  that is a writeable memory of the DRAM type is shown in FIG.  1 . Such a dynamic random access memory (DRAM) chip  100  includes a plurality of memory storage cells  102  in which each cell  102  has a transistor  104  and an intrinsic capacitor  106 . As shown in  FIGS. 2 and 3 , the memory storage cells  102  are arranged in arrays  108 , wherein memory storage cells  102  in each array  108  are interconnected to one another via columns of conductors  110  and rows of conductors  112 . As shown in  FIG. 4 , the transistors  104  are used to access the capacitors  106 , allowing them to charge and discharge to certain voltage levels. The capacitors  106  then store the voltages as binary bits, 1 or 0, representative of the voltage levels. The binary 1 is referred to as a “high” and the binary 0 is referred to as a “low.” The voltage value of the information stored in the capacitor  106  of a memory storage cell  102  is called the logic state of the memory storage cell  102 . 
     As shown in  FIGS. 1 and 2 , the memory chip  100  includes six address input contact pins A 0 , A 1 , A 2 , A 3 , A 4 , A 5  along its edges that are used for both the row and column addresses of the memory storage cells  102 . The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A 0  to A 5  into the row address latches  114 . Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A 0  to A 5  into the column address latches  116 . The memory chip  100  has data pin Din that receives data and data pin Dout that sends data out of the memory chip  100 . The modes of operation of the memory chip  100 , such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention. 
     A variation of a DRAM chip is shown in  FIGS. 5 and 6 . In particular, by adding a synchronous interface between the basic core DRAM operation/circuitry of a second generation DRAM and the control coming from off-chip a synchronous dynamic random access memory (SDRAM) chip  200  is formed. The SDRAM chip  200  includes a bank of memory arrays  208  wherein each array  208  includes memory storage cells  210  interconnected to one another via columns and rows of conductors. 
     As shown in  FIGS. 5 and 6 , the memory chip  200  includes twelve address input contact pins A 0 -A 11  that are used for both the row and column addresses of the memory storage cells of the bank of memory arrays  208 . In SDRAM, RAS/CAS/WE are sampled at the rising edge of the clock, its state defining the command to be executed in the CHIP. During a bank active command the address present on the DRAM address pins A 0  to A 11  are clocked into the bank of row address latches  214 . During a READ or a WRITE command cycle, the address present on the DRAM address pins A 0  to A 11  are clocked into the bank of column address latches  216 . The memory chip  200  has data input/output pins DQ 0 - 15  that receive and send input signals and output signals. The input signals are relayed from the pins DQ 0 - 15  to a data input register  218  and then to a DQM processing component  220  that includes DQM mask logic and write drivers for storing the input data in the bank of memory arrays  208 . The output signals are received from a data output register  222  that received the signals from the DQM processing component  220  that includes read data latches for reading the output data out of the bank of memory arrays  208 . The modes of operation of the memory chip  200 , such as Read and Write, are well known and so there is no need to discuss them for the purpose of describing the present invention. 
     One mode of operation of a SDRAM memory chip is called Self Refresh. In this mode of operation the refreshing of the cells, either one row at a time (usually one row per refresh cycle) or groups of rows at a time, is initiated by refresh circuitry within the SDRAM memory chip that does not require intervention from the CPU or external refresh circuitry. Self-Refresh dramatically reduces power consumption and is often used in portable computers. 
     An example of a known Self-Refresh circuit  300  within SDRAM  200  is shown in FIG.  7 . The circuit  300  includes a low frequency generator/oscillator  302 , a 1:4 frequency divider  304  and a 1:32 frequency divider  306 . In operation, an ENABLE signal EN is decoded by the incoming commands (or sent from the on-chip control logic), which triggers the oscillator  302  to generate a signal  308  that has a period of approximately 1 μs. The signal  308  is then fed to the 1:4 frequency divider  304  that generates a signal  310  that has a period of approximately 4 μs. The signal  310  is fed to the 1:32 frequency divider  306  where a Self-Refresh signal  312  is generated with a period of approximately 125 μs. The frequency of the Self-Refresh signal  312  is monitored on a DQ  314  pad upon entry into a test mode. Such monitoring includes sending a test mode activation signal TMSRF to the transfer gate  313  allowing the Self-Refresh signal to transfer to a DQ-Pad for monitoring. The frequency of the Self-Refresh signal  312  can be fine tuned and adjusted via trim fuses  318  and  320  associated with the oscillator  302  and the frequency divider  306 , respectively. 
     One disadvantage of the circuit  300  is that an external measurement and hence a test mode is required to monitor the frequency of the Self-Refresh signal  312 . Thus, the circuit  300  requires the use of external measuring devices that leads to an increase in costs and an increase in test time. 
     SUMMARY OF THE INVENTION 
     One aspect of the present invention regards a frequency adjustment system that includes an integrated circuit that generates a control signal at an unknown frequency and a frequency adjustment circuit that receives the control signal and automatically adjusts the unknown frequency of the control signal based on the unknown frequency. 
     A second aspect of the present invention regards a method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency. 
     Each of the above aspects of the present invention provides the advantage of saving costs and reducing test time by eliminating the use of external measuring devices for testing the frequency of the Self-Refresh signal of a SDRAM memory chip. 
     The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically shows a top view of an embodiment of a known memory chip; 
         FIG. 2  shows a block diagram of the memory chip of  FIG. 1 ; 
         FIG. 3  schematically shows an embodiment of a memory array to be used with the memory chip of  FIG. 1 ; 
         FIG. 4  schematically shows an embodiment of a memory cell to be used with the memory array of  FIG. 3 ; 
         FIG. 5  schematically shows a top view of a second embodiment of a known memory chip; 
         FIG. 6  shows a block diagram of the memory chip of  FIG. 5 ; 
         FIG. 7  schematically shows a known Self-Refresh circuit  300  that can be used with the memory chip of  FIGS. 5 and 6 ; 
         FIG. 8  schematically shows an embodiment of a memory chip that employs a Self-Refresh frequency adjustment system according to the present invention; 
         FIG. 9  schematically shows an embodiment of a Self-Refresh circuit according to the present invention to be used with the memory chip of  FIG. 8 ; and 
         FIG. 10  shows an embodiment of a timing diagram to be used with the memory chip of FIG.  8  and the Self-Refresh circuit of  FIG. 9  according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As shown in  FIG. 8 , a Self-Refresh frequency adjustment system  401  to be used with the present invention includes an integrated circuit, such as an SDRAM chip  400  that has a structure similar to that of the SDRAM chip  200  described previously with respect to  FIGS. 5 and 6 . The present invention can also be used in normal DRAMs. In the case of normal DRAMS, a reference clock signal must somehow be provided to the chip in order for the present invention to be implemented. 
     In such a Self-Refresh frequency adjustment system  401 , the SDRAM chip  400  includes a bank of memory arrays  408  that include memory storage cells  410  interconnected to one another via columns and rows of conductors in a manner similar to the memory arrays  208  and memory storage cells  210  discussed previously. The memory chip  400  includes twelve address input contact pins A 0 -A 11 , row address strobe (RAS) input pin, column address strobe (CAS) input pin and data input/output pins DQ 0 - 15  that receive and output signals in the same manner as their counterparts in the SDRAM chip  200  discussed previously. It should be noted that the present invention could be used with other types of memory chips, such as other types of semiconductor integrated circuits and other types of memory devices, such as SDRAMS and DDR SDRAMS. 
     The signals associated with the input contact pins A 0 -A 11  are fed to a bank of row address latches  414  and a bank of column address latches  416  that correspond to and operate in the same manner as the latches  214  and  216 , respectively. The signals associated with the data input/output pins DQO- 15  are relayed to or from data input register  418 , data output register  422  and DQM processing component  420  that correspond to and operate in the same manner as registers  218 ,  222  and DQM processing component  220 , respectively. Note that the DQM processing component  420  includes read data latches and write data latches. 
     As shown in  FIG. 9 , the Self-Refresh frequency adjustment system  401  further includes a circuit  500  that includes an low frequency generator/oscillator  502  that is part of the SDRAM chip  400 , a 1:4 frequency divider  504  and a 1:32 frequency divider  506  that are similar to the oscillator  302 , frequency divider  304  and frequency divider  306 , respectively, discussed previously. In operation, an ENABLE signal EN is sent from the on-chip control logic, which triggers the oscillator  502  to generate a control signal  508  of unknown frequency. Note that while the frequency/period of the control signal  508  is unknown, it preferably has a period in the neighborhood of approximately 1 μs. The signal  508  is then fed to the 1:4 frequency divider  504  and a counter  514  of a frequency adjustment circuit  515 . The counter  514  receives two other signals: 1) the TMSRF enable signal for the counter  514  shown in  FIG. 10 and  2) a reference clock signal CLKREF also shown in FIG.  10 . The reference clock signal is periodic, has a known period/frequency and is generated from the system clock of the SDRAM chip  400  that defines all interface timings. The system clock is used as a reference to measure the frequency of the oscillator  502  since the period of the system clock is known. Note that the counter  514  can be any preexisting counter of the SDRAM chip  400 , such as the address counter used in BUILT-IN SELF TEST (BIST) or the counter for the 1:32 frequency divider  506 . 
     The counter  514  counts the maximum number of consecutive clock pulses of the reference clock signal CLKREF that are within a pulse of the signal  508  generated by the oscillator  502  when the Self-Refresh test mode is activated (TMSRF=1). A counter signal CO,  516  representative of the maximum number of consecutive pulses counted by counter  514  is then sent to a decoder  518  of the frequency adjustment circuit  515 , which decodes the signal by multiplying the number of pulses counted by counter  514  by the known period of the reference clock signal to provide an adjustment signal  520  representative of the frequency of the signal  508 . As explained below, the signal  520  is used to automatically adjust the frequency of the signal  508  generated by the oscillator  502 . 
     The signal  520  is sent to electrical fuses  518  that fine tune the oscillator  502  based on signal  520 . The fine-tuned or modified signal of the oscillator  502  is sent to the frequency divider  504  that generates a signal  510  that has a period of approximately 4 μs. The signal  510  is fed to the  1 : 32  frequency divider  506  where a Self-Refresh signal  512  is generated with a period of approximately 125 μs. The frequency of the Self-Refresh signal  512  can be fine tuned and adjusted via laser trim fuses  520  associated with the frequency divider  506 . 
     Note that the purpose of the fine-tuning of the frequency by the oscillator  502  is to get a correct time base. The purpose of the fine-tuning performed by the frequency divider  506  is to adjust the real refresh frequency, which is dependent on the retention time of the memory array. This retention time is a process parameter and can vary from chip to chip. 
     The foregoing description is provided to illustrate the invention, and is not to be construed as a limitation. Numerous additions, substitutions and other changes can be made to the invention without departing from its scope as set forth in the appended claims.