Abstract:
A liquid crystal display apparatus time-divisionally drives data lines of a pixel matrix. The apparatus transfers output signals of at least two data driver integrated circuits to a plurality of data lines using at least two multiplexers. Further, it rearranged the video data before supplying the video data to at least two data driver integrated circuits. Accordingly, it is possible to reduce the number of the data driver integrated circuits required in the liquid crystal display apparatus and to simplify a wiring structure between the pixel matrix and the data driver integrated circuits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a liquid crystal display device employing thin film transistors (“TFTs”), used as a switch matrix, and more particularly to a liquid crystal display device adapted to be driven with digital video data. 
     2. Description of the Prior Art 
     Recently, there has been used a signal transfer system changing of an analog image signal into a digital image signal feasible to the compression of information, in order to provide the high resolution picture with a viewer. A liquid crystal display panel has been developed that may be driven with the digital image signal instead of the existing analog image signal. 
     An digital-type liquid crystal display apparatus based on this development, as shown in FIG. 1, comprises a gate driver  12  for driving gate lines GL of a liquid crystal display panel, and a number of data driver integrated circuit, hereinafter referred simply to as “ID-IC”, for time-divisionally driving data lines DL of the liquid crystal display panel  10 . In the liquid crystal display panel  10 , the TFTs, although not shown, are located at in intersections of the gate lines GL with the data lines DL, and liquid crystal cells are connected to each of these TFTs. The gate driver  12  drives the gate lines GL sequentially for the horizontal scanning interval every frame period through a gate control signal. In other words, the gate driver  12  sequentially drives the TFTs included in the liquid crystal panel  10  for every one line. Further, the D-ICs  14  convert video data into analog data signals every horizontal scanning interval using a data control signal and applies the converted analog video signal to the data lines DL. Specifically, each of the D-ICs  14  input video data corresponding to its input lines and converts the input video data into analog video signals. Also, each of the D-ICs  14  supplies the analog video signals to the data lines DL connected to the output line thereof. Accordingly, liquid crystal cells for a single line connected to the TFTs for that line control the light transmissivity in accordance with a voltage level of that line. 
     In the digital-type liquid crystal display apparatus having a configuration described above, since the D-ICs  14  drive the data lines corresponding to their output terminal, it has a disadvantage in that a great number of D-ICs are required, and that, hence, the circuit configuration and volume becomes large. 
     In order to overcome such a disadvantage in the conventional digital-type liquid crystal display apparatus, there has been suggested a liquid crystal display apparatus using time division demultiplexing. Examples of this liquid crystal display apparatus of time division system include one disclosed, in an article published in the 1993 edition of the IEEE Journal, titled “An LCD Addressed by a-Si:H TFTs with Peripheral poly-Si TFT Circuit” by Tanaka et al., and an article published, through “Euro Display &#39;96”, titled “Ar +  Laser Annealed Poly-Si TFT for Large Area LCDs” by Kato et al. According to these articles, the time divisional liquid crystal display apparatus improves the ON/OFF speed of TFTs by forming the TFTs to have a dual layer of a polycrystalline Si and an amorphous Si. Further, the time divisional liquid crystal display apparatus allows date lines to be time-divisionally driven by inserting a demultiplexer between output terminals of each of D-ICs and the data lines. According, the time divisional liquid crystal display apparatus could reduce a required amount of D-ICs into below half. 
     In the time divisional liquid crystal display apparatus, however, since the demultiplexer switches the data lines, the distance between data lines driven with a single demultiplexer becomes large. This causes a complication in the wiring arrangement of the liquid crystal display panel as well as a distortion of video signal. Also, since D-ICs have to sample video data for one line sequentially, sampling clocks with a frequency corresponding to the number of video data for one line should be supplied to the D-ICs. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a liquid crystal display apparatus which can simplify a circuit configuration and a wiring structure thereof. 
     It is other object of the present invention to provide a liquid crystal display apparatus which can retard a sampling period of video data. 
     In order to obtain said objects of the invention, a liquid crystal display apparatus according to an aspect of the present invention comprises: (1) a liquid crystal panel in which picture element cells are arranged at each of intersections of a plurality of data lines with a plurality of gate lines; (2) a first data driver circuit for supplying a plurality of video signals; (3) a second data driver circuit for supplying a plurality of video signals; and (4) a plurality of demultiplexing circuit each receiving a respective one of the video signals supplied from a respective one of the first and second data driver circuits and selectively outputting the respective video signals to a respective group of said plurality of data lines. 
     Furthermore, a liquid crystal display apparatus according to another aspect of the present invention comprises: (1) a liquid crystal panel in which red, green, and blue picture element cells are arranged at intersections of a plurality of data lines with a plurality of gate lines, the red, green, and blue picture elements being repeated in a horizontal axis thereof; (2) a first data driver circuit for supplying a plurality of video signals; (3) a second data driver circuit for supplying a plurality of video signals; and (4) a plurality of demultiplexing circuits each receiving a respective one of the video signals supplied from a respective one of the first and second data driver circuits and selectively outputting the respective video signal to a respective group of said plurality of data lines. 
     Furthermore, a liquid crystal display apparatus according to still another aspect of the present invention comprises: (1) a liquid crystal panel in which picture element cells are arranged at each of a plurality of intersections of n data lines with m gate lines, where n and m are positive intergers; (2) a plurality of multiplexing means, n divided by p in number, each said multiplexing means for outputting a data signal to p of the n data lines, where p is a positive integer less than n; and (3) data driver circuits, q in number, for time divisionally driving the plurality of demultiplexing means, where q is a positive integer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which: 
     FIG. 1 is a schematic view of a conventional liquid crystal display apparatus; 
     FIG. 2 is a block diagram of a liquid crystal display apparatus according to an embodiment of the present invention; 
     FIGS. 3 and 4 are a waveform diagram representing an operation in each part of the circuit shown in FIG. 2; 
     FIG. 5 is a detailed block diagram of an embodiment of the data rearrangement portion shown in FIG. 2; and 
     FIG. 6 is a detailed block diagram of a second embodiment of the data rearrangement portion shown in FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 2, there is shown a liquid crystal display apparatus according to an embodiment of the present invention comprising a gate driver  22  for driving gate lines GM 1  to GM 600  of a pixel matrix  20 , and D-ICs  24   a  and  24   b  for driving data lines DL 1  to DL 2400  of the pixel matrix  20 . This pixel matrix  20  includes 600×2400 picture elements, each of which is arranged in intersecting points of the gate lines GM 1  to GM 600  with the data lines DL 1  to DL 2400 , to display a picture having 600×800 pixels. Each of the picture elements consists of a single TFT and a single liquid crystal cell. A gate electrode and a data electrode of the TFT included in the picture element are connected to the gate line GM and the data line DL, respectively. The 2400 data lines DL 1  to DL 2400  are assigned 800 groups of three pixel elements each for driving red color R elements, green color G elements, and blue color B elements in each group. These data lines for red R, green G, and blue B are alternately arranged. The gate driver  22  drives the gate lines GL sequentially for a horizontal scanning interval every frame period by using a gate control signal. By means of this gate driver  22 , the TFTs included in the pixel matrix  20  are sequentially turned on to connect the 2400 data lines DL 1  to DL 2400  to the 2400 liquid crystal cells, respectively. In the mean time, each of the D-ICs  24   a  and  24   b  samples video data every horizontal scanning interval and converts the sampled video data into video signals. Further, each of D-ICs  24   a  and  24   b  applies the video signals to the data lines DL. Accordingly, each of the liquid crystal cells connected to the turned-on TFTs controls the light transmissivity in accordance with a voltage level of the video signal from the data line DL. 
     Further, the liquid crystal display apparatus includes multiplexers MUX 1  to MUX 600 , each of which is connected to output terminals LD 1  to LD 600  of the D-ICs  24   a  and  24   b.  Each of these demultiplexers MUX 1  to MUX 600  is connected to four adjacent data lines DLi to DLi+3. Each of these demultiplexers MUX 1  to MUX 600  sequentially applies the video signal from the output terminal of D-IC  24  to the four data lines DLi to DLi+3 by using the first to fourth selection signals SEL 1  to SEL 4 . To this end, each of the demultiplexers MUX 1  to MUX 600  includes four MOS transistors MN 1  to MN 4  connected between the output terminals LD of the D-ICs  24  and the four data lines DLi to DLi+3, respectively. The first to fourth selection signals SEL 1  to SEL 4  each have a frequency equal to the horizontal synchronous signal. Also, the first to fourth selection signals have an enabling region, that is, a high logic of region, which is progressed sequentially and repeatedly with, respect to each other. Accordingly, the four MOS transistors MN 1  to MN 4  included in the demultiplexer MUX are sequentially turned on every horizontal scanning interval, thereby allowing the four data lines DLi to DLi+3 to be sequentially connected to the output terminal LD of the D-IC  24 . These four MOS transistors MN 1  to MN 4  may be replaced by circuit devices with a function of switch. The demultiplexers MUX 1  to MUX 600  is formed on the same glass substrate  28  along with the pixel matrix  20  and the gate driver  22 . Preferably, the demultiplexers MUX 1  to MUX 600  is positioned above the pixel matrix  20 , that is, at the upper edge of the glass substrate  28  while the gate driver  22  is positioned at the edge of the pixel matrix  20 , that is, at the edge of the glass substrate  28 . D-ICs  24   a  and  24   b  may be provided on the same integrated circuit as glass substrate  28  or on a separate integrated circuit. 
     Furthermore, the liquid crystal display apparatus is provided with a data rearrangement portion  26  which rearranges video data and applies the rearranged video data to the D-ICs  24   a  and  24   b.  This data rearrangement portion  26  separates a red data R stream, a green data G stream, and a blue data B stream input via a bus for red MRB, a bus for green MGB and a bus for blue MBB, respectively, into groups. For two D-ICs  24 , two data groups are formed, and then data group is rearranged into four sections, corresponding to the number of output lines of demultiplexer MUX. Data rearrangement portion  26  supplies the rearranged video data to the D-ICs  24   a  and  24   b.  A video data is supplied, via the first to third support buses SB 1 , SB 2  and SB 3 , to the first D-IC  24   a  by the three symbol unit while a video data is supplied, via the fourth to sixth support buses SB 4 , SB 5  and SB 6 , to the second D-IC  24   b,  by the three symbol units. The data rearrangement portion  26  can be designed to input the video data simultaneously or to input the video data alternately. Finally, the data rearrangement portion  26  and the D-ICs  24   a  and  24   b  are controlled by a data control signal including a sampling clock input from a data control bus DCB. 
     FIG. 3 is a timing diagram of an operational waveform of the data control arrangement portion  26 , the D-ICs  24  and the demultiplexers MUX 1  to MUX 600 , in the case where the video data from the data rearrangement portion  26  are alternately output to the first to third support buses SB 1  to SB 3  and the fourth to sixth support buses SB 4  to SB 6 . In FIG. 3, the video data stream is alternately rearranged and the rearranged video data are applied to the D-ICs  24  through the first to sixth support buses SB 1  to SB 6 . Specifically, the rearranged video data of “R 1 , R 5 , R 9 , . . . , R 397 ” (where R 1  represents the red component of the first pixel; R 2  the red component of the second pixel, etc.) are supplied to the first support bus SB 1 , the rearranged video data of “G 2 , G 6 , G 10 , . . . , G 398 ” to the second support bus SB 2 , and the rearranged video data of “B 3 , B 7 , B 11 , . . . , B 399 ” to the third support bus, SB 3 , respectively. After the rearranged video data are supplied to the first to third support buses SB 1  to SB 3 , the rearranged video data of “R 401 , R 405 , R 409 , . . . , R 797 ”, are supplied to the fourth support bus SB 4 , the rearranged video data of “G 402 , G 406 , G 410 , . . . , G 798 ” to the fifth support bus SB 5 , and the rearranged video data of “B 403 , B 407 , B 411 , . . . , B 799 ” to the sixth support bus SB 6 , respectively. 
     In a similar manner, the arranged video data are supplied to the first to sixth support buses SB 1  to SB 6  repeatedly within a constant interval. At this time, the rearranged data of “G 1 , G 5 , G 9 , . . . G 397 ”, “B 1 , B 5 , B 9 , . . . ,  397 ” and “R 2 , R 6 , R 10 , . . . , R 398 ” are sequentially supplied to the first support bus SB 1 , within a constant interval. Also, the rearranged data of “B 2 , B 6 , B 10 , . . . , B 398 ”, “R 3 , R 7 , R 11 , . . . , R 399 ” and “G 3 , G 7 , G 11 , . . . , G 399 ” are sequentially supplied to the second support bus SB 2  and the rearranged data of “R 4 , R 8 , R 12 , . . . , R 400 ”,“G 4 , G 8 , G 12 , . . . , G 400 ” and “B 4 , B 8 , B 12 , . . . ,  400 ” to the third support bus SB 3 , respectively, within a constant interval. Further, the rearranged video data of “G 401 , G 405 , G 409 , . . . , G 797 ”, “B 401 , B 405 , B 409 , . . . , B 797 ” and “R 402 , R 406 , R 410 , . . . , R 798 ”, the rearranged video data of “B 402 , B 406 , B 410 , . . . , B 798 ”, “R 403 , R 407 , R 411 , . . . , R 799 ” and “G 403 , G 407 , G 411  . . . G 799 ”, and the rearranged video data of “R 4 , R 8 , R 12 , . . . , R 400 ”, “G 4 , G 8 , G 12 , . . . , G 400 ” and “B 4 , B 8 , B 12 , . . . , B 400 ” are supplied to the fourth to sixth support buses SB 4  to SB 6 , respectively, which input video data rearranged in such a manner to be alternated with the first to third support buses SB 1  to SB 3 . 
     When the selection signals SEL 1  to SEL 4  are sequentially enabled, that is, have a high logic, four video signals are sequentially output to each of 600 output lines LD 1  to LD 600  of the D-ICs  24   a  and  24   b  during one horizontal scanning interval  1 H. For example, video signals of “R 1 , G 1 , B 1  and R 2 ” are sequentially output to the first output terminal LD 1  of the D-ICs  24   a,  and video signals of “G 2 , B 2 , R 3  and G 3 ” are sequentially outputted to the second output terminal LD 2  opf the D-IC  24   a.  In this manner, video signals of “B 3 , R 4 , G 4  and B 4 ”, video signals of “R 5 , G 5 , B 5  and R 6 ”, video signals of “G 6 , B 6 , R 7  and G 7 ” and video signals of “B 7 , R 8 , G 8  and B 8 ” are supplied to the third to sixth output terminals LD 3  to LD 6  of the D-IC  24   a,  respectively. 
     The 2400 video signals output to the 600 output terminals LD 1  to LD 600  of the D-ICs  24   a  and  24   b  over four selection signal periods are respectively applied to the 2400 data lines DL 1  to DL 2400  through the 600 demultiplexers MUX 1  to MUX 600 , which perform a switching operation in accordance with the first to fourth selection signals SEL 1  to SEL 4 . As a result, the number of D-ICs used for driving the pixel matrix  20  is reduced remarkably, for example, from eight to two. 
     FIG. 4 shows timing diagrams of waveforms of the data rearrangement portion  26 , the D-ICs  24  and the demultiplexers MUX 1  to MUX 600  in the case where the rearranged video data from the data rearrangement portion  26  are output to the first to third support buses SB 1  to SB 3  and the fourth to sixth support buses SB 4  to SB 6  simultaneously. In FIG. 4, the rearranged video data supplied to the first to third support buses SB 1  to SB 3  and the fourth to sixth support buses SB 4  to SB 6 , respectively, so that the rearranged video date are sampled by the D-ICs  24 . Specifically, the rearranged video data of “R 1 , R 5 , R 9 , . . . , R 397 ”, “G 1 , G 5 , G 9 , . . . , G 397 ”, “B 1 , B 5 , B 9 , . . . , B 397 ” and “R 2 , R 6 , R 10 , . . . , R 398 ” are sequentially supplied to the first support bus SB 1 . As shown in FIG. 4, the rearranged video data is similarly applied to the second to sixth support buses SB 2  to SB 6 , respectively. 
     Subsequently, as the selection signals SEL 1  to SEL 4  are sequentially enabled, that is, as SEL 1  to SEL 4  are set to a high logic, four video signals are sequentially output to each of 600 output lines LD 1  to LD 600  of the D-ICs  24   a  and  24   b.  For example, video signals of “R 1 , G 1 , B 1  and R 2 ” are sequentially output to the first output terminal LD 1  of the D-IC  24   a,  and video signals of “G 2 , B 2 , R 3  and G 3 ” are sequentially output to the second output terminal LD 2  of the D-IC  24   a.  In this manner, video signals of “B 3 , R 4 , G 4  and B 4 ”, video signals of “R 5 , G 5 , B 5  and R 6 ”′, video signals of “G 6 , B 6 , R 7  and G 7 ” and video signals of “B 7 , R 8 , G 8  and B 8 ” are supplied to the third to sixth output terminals LD 3  to LD 6  of the D-ICs  24   a,  respectively. 
     The 2400 number of video signals output to the 600 output terminals LD 1  to LD 600  of the D-ICs  24   a  and  24   b  are respectively applied to the 2400 data lines DL 1  to DL 2400  by means of the 600 demultiplexers MUX 1  to MUX 600  performing the switching operation in accordance with the first to fourth selection signal SEL 1  to SEL 4 . As a result, the number of D-ICs used for driving the pixel matrix  20  is reduced, for example, from eight to two. Moreover, the video data are simultaneously supplied, to the D-ICs  24   a  and  24   b,  thereby lowering the frequency of a sampling clock which is supplied to the D-ICs  24   a  and  24   b  for sampling the video data. 
     FIG. 5 is a detailed block diagram of an embodiment of the data rearrangement portion  26  shown in FIG.  2 . Referring to FIG. 5, the data rearrangement portion  26  comprises first to third data multiplexers  30 ,  32  and  34 , connected to buses MRB, MGB and MBB for red, green, and blue data, respectively, and first to 12th first-input-first-output devices FR 1  to FR 12 , hereinafter referred simply as to “FIFO”, connected in parallel to the first to third data multiplexers  30 ,  32  and  34  in groups of four. The first to third data multiplexers  30 ,  32  and  34  are driven when the first division enabling signal ENa remains at a high logic, that is, during a period corresponding to half the horizontal scanning interval. The first data multiplexer  30  sequentially and repeatedly stores 400 red data R 1  to R 400  corresponding to half the red data stream R 1  to R 800  from the bus for red MRB to the first to fourth FIFOs FR 1  to FR 4 , in accordance with logical values of 2 bit of selection signals A and B changing sequentially and repeatedly. As a result, the red data of “R 1 ,R 5 ,R 9  . . . R 397 ”, “R 2 ,R 6 ,R 10  . . . R 398 ”, “R 3 ,R 7 ,R 11  . . . R 399 ” and “R 4 ,R 8 ,R 12  . . . R 400 ” are stored to the first to fourth FIFOs FR 1  to FR 4 , respectively. Similar to the first data multiplexer  30 , the second multiplexer  32  sequentially and repeatedly stores 400 green data G 1  to G 400  corresponding to half the green data stream G 1  to G 800  from the bus for green MGB to the fifth to eighth FIFOs FR 5  to FR 8 , in accordance with logical values of selection signals A and B changing sequentially and repeatedly. As a result, the green data of “G 1 ,G 5 ,G 9  . . . G 397 ”, “G 2 ,G 6 ,G 10  . . . G 398 ”, “G 3 ,G 7 ,G 11  . . . G 399 ” and “G 4 ,G 8 ,G 12  . . . G 400 ” are stored in the fifth to eighth FIFO FR 5  to FR 8 , respectively. Further, similar to the first and second data multiplexers  30  and  32 , the third data multiplexer  34  sequentially and repeatedly stores 400 blue data B 1  to B 400  corresponding to half the blue data stream B 1  to B 800  from the bus for blue MBB to the ninth to 12th FIFOs FR 9  to FR 12 , in accordance with logical values of said two-bit of selection signals A and B changing sequentially and repeatedly. As a result, the blue data of “B 1 ,B 5 ,B 9  . . . B 397 ”, “B 2 ,B 6 ,B 10  . . . B 398 ”, “B 3 ,B 7 ,B 11  . . . B 399 ” and “B 4 ,B 8 ,B 12  . . . B 400 ” are stored in the ninth to twelfth FIFOs FR 9  to FR 12 , respectively. 
     Fourth to sixth data multiplexers  36 ,  38  and  40  are connected to the red, green, and blue buses MRB, MGB and MBB, respectively and, at the same time, to the first to third data multiplexer  30 ,  32  and  34  in parallel, respectively. 13th to 24th FIFOs FR 13  to FR 24  are connected to the fourth to sixth data multiplexers  36 ,  38  and  40 . The fourth to sixth data multiplexers  36 ,  38  and  40  are driven when the second division enabling signal ENb remains at a high logic, that is, during a period corresponding to the second half of the horizontal scanning interval when the first to third data multiplexers  30 ,  32  and  34  are not driven. The fourth data multiplexer  36  sequentially and repeatedly stores 400 red data R 401  to R 800  corresponding to half the red data stream R 1  to R 800  from the red bus MRB to the 13th to 16th FIFOs FR 13  to FR 16 , in accordance with logical values of selection signals A and B. As a result, the red data of “R 401 ,R 405 ,R 409  . . . R 797 ”, “R 402 ,R 406 ,R 410  . . . R 798 ”, “R 403 ,R 407 ,R 411  . . . R 799 ” and “R 404 ,R 40 ,R 412  . . . R 800 ” are stored to the 13th to 16th FIFOs FR 13  to FR 16 , respectively. Further, the fifth multiplexer  38  sequentially and repeatedly stores 400 green data G 401  to G 800  corresponding to half of the green data stream G 1  to G 800  from the green bus MGB to the 17th to 20th FIFOs FR 17  to FR 20 , in accordance with logical values of selection signals A and B. As a result, the green data of “G 401 ,G 405 ,G 409  . . . G 797 ”, “G 40 ,G 406 ,G 410  . . . G 798 ”, “G 403 ,G 407 ,G 411  . . . G 4799 ” and “G 404 ,G 408 ,G 412  . . . G 800 ” and stored to the 17th to 20th FIFOs FR 17  to FR 20 , respectively. Furthermore, the sixth data multiplexer  40  sequentially and repeatedly stores 400 blue data B 1  to B 400  corresponding to half the blue data stream B 1  to B 800  from the blue bus MBB to 21st to 24th FIFOs FR 21  to FR 24 , in accordance with logical values of said selection signals A and B. As a result, the blue data of “B 401 ,B 405 ,B 409  . . . B 797 ”, “B 402 ,B 406 ,B 410  . . . B 798 ”, “B 403 ,B 407 ,B 411  . . . B 799 ” and “B 404 ,B 498 ,B 412  . . . B 800 ” are stored in the 21st to 24th FIFOs FR 21  to FR 24 , respectively. 
     Moreover, the data rearrangement portion  26  further comprises the first demultiplexer  42  for inputting the video data from FIFOs FR 1  to FR 12 , and the second demultiplexer  44  for inputting the video data from FIFOs FR 13  to FR 24 . These first and second demultiplexers  42  and  44  are alternately driven once every interval in which respective selection signals SEL 1  to SEL 4  are enabled. For example, the first demultiplexer  42  is driven in the first half of the enabled interval of the first selection signal SEL 1  while the second demultiplexer  44  is driven in the second half of the enabled interval of the first selection signal SEL 1 . Accordingly, the respective first and second demultiplexers  42  and  44  are alternately driven four times as the first to fourth selection signals are sequentially enabled, to thereby output video data of a signal horizontal line via the first to sixth support buses SB 1  to SB 6 . Further, the respective first and second demultiplexers  42  and  44  select the video data stored in three FIFOs in the 12 FIFOs FR 1  to FR 12  or FR 13  to FR 24 , whenever it is driven, and outputs the selected video data to three support buses SB 1  to SB 3  or SB 4  to SB 6 , respectively. Specifically, the first demultiplexer  42  supplies the red data of “R 1 ,R 5 ,R 9  . . . R 397 ” from the first FIFO FR 1 , the green data of “G 2 ,G 6 ,G 10  . . . G 398 ” from the sixth FIFO FR 6  and the blue data of “B 3 ,B 7 ,B 11  . . . B 399 ” from the 11th FIFO FR 11  to the first to third support buses SB 1  to SB 3 , respectively, when it is driven for the first time. Further, when the first demultiplexer  42  is driven for the second time, it supplies the green data of “G 1 ,G 5 ,G 9  . . . G 397 ” from the fifth FIFO FR 5 , the blue data of “B 2 ,B 6 ,B 10  . . . B 398 ” from the tenth FIFO FR 10  and the red data of “R 4 ,R 8 ,R 12  . . . R 400 ” from the fourth FIFO FR 4  to the first to third support buses SB 1  to SB 3 , respectively. Furthermore, when the first demultiplexer  42  is driven for the third time, it supplies the blue data of “B 1 ,B 5 ,B 9  . . . B 397 ” from the ninth FIFO FR 9 , the red data of “R 3 ,R 7 ,R 11  . . . R 399 ” from the second FIFO FR 2  and the green data of “G 4 ,G 8 ,G 12  . . . G 400 ” from the eighth FIFO FR 8  to the first to third support buses SB 1  to SB 3 , respectively. Furthermore, when the first demultiplexer  42  is driven for the fourth time, it supplies the red data of “R 2 ,R 6 ,R 10  . . . R 398 ” from the second FIFO FR 2 , the green data of “G 3 ,G 7 ,G 11  . . . G 399 ” from the seventh FIFO FR 7  and the blue data of “B 4 ,B 8 ,B 12  . . . B 400 ” from the 12th FIFO FR 12  to the first to third support buses SB 1  to SB 3 , respectively. 
     On the other hand, the second demultiplexer  44  supplies the red data of “R 401 ,R 405 ,R 409  . . . R 797 ” from FIFO FR 13 , the green data of “G 402 ,G 406 ,G 410  . . . G 498 ” from FIFO FR 18  and the blue data of “B 403 ,B 407 ,B 411  . . . B 799 ” from FIFO FR 23  to the fourth to sixth support buses SB 4  to SB 6 , respectively, when it is driven for the first time. Further, when the second demultiplexer  44  is driven for the second time, it supplies the green data of “G 401 ,G 405 ,G 409  . . . G 797 ” from FIFO FR 17 , the blue data of “B 402 ,B 406 ,B 410  . . . B 798 ” from FIFO FR 22  and the red data of “R 404 ,R 408 ,R 412  . . . R 800 ” from FIFO FR 16  to the fourth to sixth support buses SB 4  to SB 6 , respectively. Furthermore, when the second demultiplexer  44  is driven for the third time, it supplies the blue data of “B 401 ,B 405 ,B 409  . . . B 797 ” from FIFO FR 21 , the red data of “R 403 ,R 407 ,R 411  . . . R 799 ” from FIFO FR 14  and the green data of “G 404 ,G 408 ,G 412  . . . G 800 ” from FIFO FR 20  to the fourth to sixth support buses SB 4  to SB 6 , respectively. Furthermore, when the second demultiplexer  44  is driven for the fourth time, it supplies the red data of “R 402 ,R 406 ,R 410  . .. R 798 ” from FIFO FR 14 , the green data of “G 403 ,G 407 ,G 411  . . . G 799 ” from FIFO FR 19  and the blue data of “B 404 ,B 408 ,B 412  . . . B 800 ” from FIFO FR 24  to the fourth to sixth support buses SB 4  to SB 6 , respectively. 
     Herein, the first to third data multiplexers  30 ,  32  and  34  constitute the first group rearrangement means rearranging a portion of the video data stream for one line along with the first to 12th FIFOs FR 1  to FR 12  and the first demultiplexer  42 , and the fourth to sixth data multiplexers  36 ,  38  and  40  constitute the second group rearrangement means rearranging a portion of the video data stream for one line along with the 13th to 24th FIFOs FR 13  to FR 24  and the second demultiplexer  44 . The number of these group rearrangement means requires as many as the number of D-ICs  24  shown in FIG.  2 . The number of FIFOs connected to each of the data multiplexers requires as many as the number of the output lines of multiplexers MUX shown in FIG.  2 . Further, the total storage capacity of FIFOs FR 1  to FR 24  should be at least large enough to store one line of video data, but preferably should be established such that it can store video data for two lines. Also, in the case where the total storage capacity of FIFOs FR 1  to FR 24  is established to store video data for two lines, the first and second demultiplexers  42  and  44  can be simultaneously driven. Accordingly, in order to control data sampling, it becomes possible to lower the frequency of the sampling clock supplied for the D-ICs  24  shown in FIG.  2 . 
     FIG. 6 is a detailed block diagram of other embodiment of the data rearrangement portion  26  shown in FIG.  2 . Referring to FIG. 6, the data rearrangement portion  26  comprises first to ninth control switches SW 1  to SW 9  for multiplexing the video data from the red, green and blue buses MRB, MGB and MBB to the first to 12th memories MR 1  to MR 12 . Each of the first to 12th memories MR 1  to MR 12  has storage capacity to store color data corresponding to half the color data for one line. 
     The first control switch SW 1  delivers the red data stream from the red bus MRB into one side of the fourth control switch SW 4  and the seventh control switch SW 7  in accordance with a logical state of the first switching control signal ENa. The first switching control signal ENa remains at a high logic in a period corresponding to the first half of the horizontal scanning interval while at a low logic in a period corresponding to the second half. By this first switching control signal ENa, the first control switch SW 1  delivers 400 red data R 1  to R 400  in the first half of the red data R 1  to R 800  for one line into the fourth control switch SW 4  while 400 red data R 401  to R 800  in the second half thereof into the seventh control switch SW 7 . Likewise, the second control switch SW 2  delivers 400 green data G 1  to G 400  in the first half of the green data G 1  to G 800  for one line from the green bus MGB into the fifth control switch SW 5  while 400 green data G 401  to G 800  in the second half thereof into the eighth control switch SW 8 , by the first switching control signal ENa. Similar to the first and second control switches SW 1  and SW 2 , the third control switch SW 3  delivers 400 blue data B 1  to B 400  in the first half of the blue data B 1  to B 800  for one line from the blue bus MBB into the sixth control switch SW 6  while 400 blue data B 401  to B 800  in the second half thereof into the ninth control switch SW 9 , by the first switching control signal ENa. 
     The respective fourth to ninth control switches SW 4  to SW 9  deliver color data into any one side of the odd number memories and the even number memories in accordance with a logical state of a horizontal synchronous pulse HP. This horizontal synchronous pulse HP changes from a high logic into a low logic and vice versa every time period of the horizontal synchronous signal. As a result, the respective fourth to ninth control switches SW 4  to SW 9  deliver the color data into the odd number memories during the odd number horizontal synchronous interval, and deliver the color data into the even number memories during the even number horizontal synchronous interval. Specifically, in the course of the odd number horizontal synchronous interval, the fourth control switch SW 4  delivers the red data of “R 1  to R 400 ” into the first memory MR 1 , the fifth control switch SW 5  the green data of “G 1  to G 400 ” into the third memory MR 3 , the switch control switch SW 6  the blue data of “B 1  to B 400 ” into the fifth memory MR 5 , the seventh control switch SW 7  the red data of “R 401  to R 800 ” into the seventh switch MR 7 , the eighth control switch SW 8  the green data of “G 401  to G 800 ” into the ninth memory MR 9 , and the ninth control switch SW 9  the blue data of “B 401  to B 800 ” into the 11th memory MR 11 . On the other hand, in the course of the even number synchronous interval, the fourth control switch SW 4  delivers the red data of “R 1  to R 400  into the second memory MR 2 , the fifth control switch SW 5  the green data of “G 1  to G 400 ” into the fourth memory MR 4 , the sixth control switch SW 6  the blue data of “B 1  to B 400 ” into the sixth memory MR 6 , the seventh control switch SW 7  the red data of “R 401  to R 800 ” into the eighth memory MR 8 , the eighth control switch SW 8  the green data of “G 401  to G 800 ” into the tenth memory MR 10 , and the ninth control switch SW 9  the blue data of “B 401  to B 800 ” into the 12th memory MR 12 . 
     In the mean time, the first to 12th memories MR 1  to MR 12  read out and output the stored color data in a different sequence from the input sequence. Further, the first, third and fifth memories MR 1 , MR 3  and MR 5  perform the read-out operation simultaneously with the seventh, ninth and 11th memories MR 7 , MR 9  and MR 11 , and the second, fourth and sixth memories MR 2 , MR 4  and MR 6  perform the read-out operation simultaneously with the eighth, tenth and 12th memories MR 8 , MR 10  and MR 12 . At the time of reading out data, the first and second memories MR 1  and MR 2  output 400 red data R 1  to R 400  in a sequence of “R 1 ,R 5 ,R 9  . . . R 397 ”, “R 4 ,R 8 ,R 12  . . . R 400 ”, “R 3 ,R 7 ,R 11  . . . R 399 ” and “R 2 ,R 6 ,R 10  . . . R 398 ”. In similarity to the first and second memories MR 1  and MR 2 , the seventh and eighth memories MR 7  and MR 8  output 400 red data R 401  to R 800  in a sequence of “R 401 ,R 405 ,R 409  . . . R 797 ”, “R 404 ,R 408 ,R 412  . . . R 400 ”, “R 403 ,R 407 ,R 411  . . . R 799 ” and “R 402 ,R 406 ,R 410  . . . R 798 ”. Further, at the time of reading out data, the third and fourth memories MR 3  and MR 4  output 400 green data G 1  to G 400  in a sequence of “G 2 ,G 6 ,G 10  . . . G 398 ”, “G 1 ,G 5 ,G 9  . . . G 397 ”, “G 4 ,G 8 ,G 12  . . . G 400 ” and “G 3 ,G 7 ,G 11  . . . G 399 ”. Likewise, the ninth and tenth memories MR 9  and MR 10  output 400 green data G 401  to G 800  in a sequence of “G 402 ,G 406 ,G 410  . . . G 498 ”, “G 401 ,G 405 ,G 409  . . . G 797 ”, “G 404 ,G 408 ,G 412  . . . G 800 ” and “G 403 ,G 407 ,G 411  . . . G 799 ”. At the time of reading out data, the fifth and sixth memories MR 5  and MR 6  output 400 blue data B 1  to B 400  in a sequence of “B 3 ,B 7 ,B 11  . . . B 399 ”, “B 2 ,B 6 ,B 10  . . . B 398 ”, “B 1 ,B 5 ,B 9  . . . B 397 ” and “B 4 ,B 8 ,B 12  . . . B 400 ”. In similarity to the fifth and sixth memories MR 5  and MR 6 , the 11th and 12th memories MR 11  and MR 12  output 400 blue data B 401  to B 800  in a sequence of “B 403 ,B 407 ,B 411  . . . B 799 ”, “B 402 ,B 406 ,B 410  . . . B 798 ”, “B 401 ,B 405 ,B 409  . . . B 797 ” and “B 404 ,B 408 ,B 412  . . . B 800 ”. 
     Furthermore, the data rearrangement portion  26  includes the tenth to 15th control switches SW 10  to SW 15  for selectively outputting color data from the odd number memories MR 1 , MR 3 , MR 5 , MR 7 , MR 9  and MR 11  and color data from the even number memories MR 2 , MR 4 , MR 6 , MR 8 , MR 10  and MR 12 . These tenth to 15th control switches SW 10  to SW 15  select the color data from either the odd number or the even number memories in accordance with a logical state of the horizontal synchronous pulse HP inverted by means of an inverter INV 1 . In other words, the tenth to 15th control switches SW 10  to SW 15  select the color data from the even number memories during odd number horizontal synchronous intervals while the color data from the odd number memories during even number horizontal synchronous intervals. 
     Furthermore, the data rearrangement portion  26  includes the 16th to 18th control switches SW 16  to SW 18  driven with the second to fourth switching control signals ENb, ENc and ENd, respectively. Also, the data rearrangement portion  26  further comprises the 19th to 21st control switches driven with the second to fourth switching control switches ENb, ENc and ENd, respectively. Each of these second to fourth switching control signals ENb, ENc and ENd consists of a two bit logical signal, and the logical value thereof changes four times in the same interval during a single horizontal synchronous period as the first to fourth selection signals SEL 1  to SEL 4  are sequentially enabled. Accordingly, the 16th to 21st control switches SW 16  to SW 21  becomes to be switched four times during one horizontal synchronous interval. Specifically, the 16th control switch SW 16  sequentially selects the tenth control switch SW 10 , the 11th control switch SW 11 , the 12th control switch SW 12  and the tenth control switch SW 10  in accordance with a logical value of the second switching control signal ENb, to thereby output the rearrangement data of “R 1 ,R 5 ,R 9  . . . R 397 ”, “G 1 ,G 5 ,G 9  . . . G 397 ”, “B 1 ,B 5 ,B 9  . . . B 397 ” and “R 2 ,R 6 ,R 10  . . . R 398 ” to the first support bus SB 1 . The 17th control switch SW 17  sequentially selects the 11th control switch SW 11 , the 12th control switch SW 12 , the 10th control switch SW 10  and the 11th control switch SW 11  in accordance with a logical value of the third switching control signal ENc, to thereby output the rearrangement data of “G 2 ,G 6 ,G 10  . . . G 398 ”, “B 2 ,B 6 ,B 10  . . . G 398 ”, “R 3 ,R 7 ,R 11  . . . R 399 ” and “G 5 ,G 7 ,G 11  . . . G 399 ” to the second support bus SB 2 . The eighth control switch SW 18  sequentially selects the 12th control switch SW 12 , the tenth control switch SW 10 , the 11th control switch SW 11  and the 12th control switch SW 12  in accordance with a logical value of the fourth switching control signal ENd, to thereby output the rearrangement data of “B 3 ,B 7 ,B 11  . . . B 399 ”, “R 4 ,R 8 ,R 12  . . . R 400 ”, “G 4 ,G 8 ,G 12  . . . G 400 ” and “B 4 ,B 8 ,B 12  . . . B 400 ” to the third support bus SB 3 . Furthermore, the rearranged video data outputted to the fourth to sixth support buses SB 4  to SB 6  by means of the 19th to 21st control switches SW 19  to SW 21  operating in the same manner as the 16th to 18th control switches SW 16  to SW 18  are as follows. The rearranged video data of“R 401 ,R 405 ,R 409  . . . R 797 ”, “G 401 ,G 405 ,G 409  . . . G 797 ”,“B 401 ,B 405 ,B 409  . . . B 797 ”and“R 402 ,R 406 ,R 410  . . . R 798 ” are supplied to the fourth support bus SB 4 , the rearranged video data of “G 402 ,G 406 ,G 410  . . . G 798 ”, “B 402 ,B 406 ,B 410  . . . B 798 ”,“R 403 ,R 407 ,R 411  . . . R 799 ”and“G 403 ,G 407 ,G 411  . . . G 799 ” to the fifth support bus SB 5 , and the rearranged video data of “B 403 ,B 407 ,B 411  . . . B 499 ”, “R 404 ,R 408 ,R 412  . . . R 800 ”, “G 404 ,G 408 ,G 412  . . . G 800 ” and “B 404 ,B 408 ,B 412  . . . B 800 ” to the sixth support bus SB 6 . 
     As described above, a liquid crystal display apparatus can rearrange video data for one line in such a manner to sequentially drive the adjacent TETs in FETs for one line on the liquid crystal panel and, at the same time, can distribute TFTs driven simultaneously. Accordingly, in the liquid crystal display apparatus, it is possible to simplify a wiring structure between the D-ICs and the pixel matrix. Also, the present invention allows the D-ICs to sample the video data simultaneously so that the D-ICs can use the frequency of the sampling clock with a low frequency. 
     Although the present invention has been explained by the embodiments shown in the drawing hereinbefore, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather than that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.