Abstract:
A circuit comprising an output circuit, an adjustment circuit and a detect circuit. The output circuit may be configured to present a first and second output in response to (i) a first and second control signal and (ii) an input signal. The slew rate adjustor circuit may be configured to present the first and second control signals in response to a third control signal. The detect circuit may be configured to present the third control signal in response to the first and second output signals. The slew rate adjuster circuit may dynamically adjust a slew rate of the first and second output signals to minimize common-mode changes.

Description:
FIELD OF THE INVENTION 
     The present invention relates to output buffers generally and, more particularly, to a dynamic slew rate control output buffer. 
     BACKGROUND OF THE INVENTION 
     Complementary output buffers may be used in devices such as the Universal Serial Bus. Conventional approaches to presenting a complementary differential output include implementing two separate differential output drivers. Referring to FIG. 1, an output driver  10  is shown receiving an input signal IN and an output driver  12  is shown receiving an input signal INB. The output driver  10  presents a signal A and the output driver  12  presents a signal B. The output drivers  10  and  12  provide a complementary differential output. Since the output driver  10  and the output driver  12  operate independently, it is difficult to inherently match the outputs. Additionally, it may be impractical to produce two sets of output buffers that operate over a wide load and signal swing such as a Universal Serial Bus device. 
     The output driver  10  is required to provide rising edge circuitry to present the signal A that matches the falling edge circuitry of the output driver  12  to present the signal B. The implementation of separate circuitry results in poor control of parameters like the crossover voltage of the signal A and the signal B and the rise-time/fall-time ratio. 
     Another solution would be to implement the output drivers  10  and  12  using operational amplifiers. However, operational amplifier drivers are difficult to design to handle large loads with sufficient bandwidth to operate with Universal Serial Bus devices. Additionally, operational amplifier devices may be difficult to design to operate over a wide output swing with a low voltage operation. 
     SUMMARY OF THE INVENTION 
     The present invention concerns a circuit comprising an output circuit, an adjustment circuit and a detect circuit. The output circuit may be configured to present a first and second output in response to (i) a first and second control signal and (ii) an input signal. The slew rate adjustor circuit may be configured to present the first and second control signals in response to a third control signal. The detect circuit may be configured to present the third control signal in response to the first and second output signals. The slew rate adjuster circuit may dynamically adjust a slew rate of the first and second output signals to minimize common-mode changes. 
     The objects, features and advantages of the present invention include providing a common-mode circuit that detects movement in a common-mode point that may be used to indicate that the edges are not matching to provide control of (i) the crossover voltage of the outputs, (ii) the rise-time/fall-time ratio and/or (iii) other important factors to devices such as a Universal Serial Bus device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a block diagram of a conventional approach for generating a differential output signal; 
     FIG. 2 is a block diagram of a preferred embodiment of the present invention; 
     FIG. 3 is a timing diagram illustrating the operation of the circuit of FIG. 2; 
     FIG. 4 is a more detailed block diagram of an embodiment of the present invention; 
     FIG. 5 is a diagram of the common-mode detect and feedback feature; 
     FIG. 6 is a block diagram of the dynamic slew rate adjuster circuit; 
     FIG. 7 is a more detailed diagram of the dynamic slew rate adjuster circuit; and 
     FIG. 8 is a circuit diagram of the present invention shown implemented with a portion of an output driver circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, a block diagram of an output buffer  14  is shown in accordance with a preferred embodiment of the present invention. The output buffer  14  may receive a signal (e.g., IN) at an input  16  and may present a first output signal (e.g., A) and a second output signal (e.g., B) at an output  18  and an output  20 , respectively. In general, the signal B presented at the output  20  is a digital complement of the signal A presented at the output  18 . 
     Referring to FIG. 3, a timing diagram illustrating the output A and output B is shown. The x-axis generally represents a time domain (e.g., t) and the y-axis generally represents a voltage domain (e.g., v). The signal B is shown as a first signal B 1  and a second signal B 2 . The signal B 1  generally crosses the signal A at a crossover (or common-mode) point  22 . The signal B 2  generally crosses the signal A at a crossover (or common-mode) point  24 . Ideally, the crossover points  22  and  24  occur at a point half way between the high and low voltages of the signals A and B. 
     Referring to FIG. 4, a more detailed block diagram of the output buffer  14  is shown. The common-mode detect feedback circuit  36  generally detects movement in the common-mode point, indicating that the edges are not matched. In general, the lagging edge is “boosted” to catch up to the non-lagging edge. The common-mode detect and feedback block  36  may be used to equalize the common-mode point. The output buffer  14  generally comprises a circuit  30 , a circuit  32 , a dynamic slew rate adjuster block (or circuit)  34 , and a common-mode detect and feedback block (or circuit)  36 . The circuit  30  may have an input  38  that may receive the signal IN and an input  40  that may receive a control signal from the dynamic slew rate adjuster block  34 . The circuit  32  has an input  42  that may receive a signal INB (that may be a digital complement of the signal IN) as well as an input  44  that may receive the signal from the dynamic slew rate adjustor block  34 . The common-mode detect and feedback block  36  has an input  46  that may receive the signal A and an input  48  that may receive the signal B. The common-mode detect feedback block  36  has an output  50  that may present a control signal to an input  52  of the dynamic slew rate adjuster circuit  34 . 
     Referring to FIG. 5, a circuit diagram of the common-mode detect and feedback circuit  36  is shown. The circuit  36  comprises a capacitor C 1 , a capacitor C 2 , a resistor R 1  and a resistor R 2 . The capacitor C 1  may receive the signal IN at the input  46  and the signal INB at the input  48 . The capacitor C 1  and the capacitor C 2  are generally coupled together to present an output signal (e.g., a common-mode voltage Vcm). The resistor R 1  is generally coupled between the input  46  and the output  50 . The resistor R 1  is D generally connected in parallel with the capacitor C 1 . The resistor R 2  is generally coupled between the input  48  and the output  50 . The resistor R 2  is generally coupled in parallel with the capacitor C 2 . In general, the resistor R 1  and the resistor R 2  are fabricated to have an equal resistance. Similarly, the capacitor C 1  and the capacitor C 2  are also fabricated to have an equal capacitance. In a preferred embodiment, the resistors R 1  and R 2  may be sized as an infinite resistance so that the capacitors C 1  and C 2  may provide the common mode detection. 
     Referring to FIG. 6, a block diagram of the dynamic slew rate adjuster circuit  34  is shown. The circuit  34  generally comprises an amplifier  60  and an adjust logic block (or circuit)  62 . The amplifier  60  may be implemented as an operational amplifier or other suitable gain circuit. The amplifier  60  generally receives the signal Vcm and may present a signal to an input  64  of the adjust logic block  62 . The adjust logic block  62  may present a first signal at an output  66  and a second signal at an output  68 . The first signal presented at the output  66  may be used to adjust the falling edge of a waveform and the second signal presented at the output  68  may be used to adjust the rising edge of a waveform. 
     Referring to FIG. 7, a more detailed diagram of the dynamic slew rate adjuster circuit  34  is shown. The adjust logic block  62  generally comprises an inverter  70 , an inverter  72  and an inverter  74 . The inverter  70  is generally implemented as a high threshold inverter. In general, the threshold of the inverter  70  should be set so that when the output of the amplifier  60  exceeds the threshold, the inverter  70  may present a signal to the inverter  72 , which may then be presented to the output  66 . The inverter  74  is generally implemented as a low threshold inverter. The threshold of the inverter  74  is generally set so that when the signal presented from the amplifier  60  is below the threshold, the inverter  74  may present a signal at the output  68 . The amplifier  60  is shown having a capacitor  76  and a switch  78 . The capacitor  76  may be implemented as a filter capacitor. The switch  78  generally initializes the signal Vcm received at the input  52 . The switch  78  may be closed before the output transition begins, which may set the input  52  at the threshold bias point of the amplifier  60 . When the switch  78  is opened (which may be at or before the time the outputs begin to transition) the output of amplifier  60  generally moves in response to a shift in the signal Vcm, which may indicate a shift in the common-mode point of the outputs A and B. 
     FIG. 7 also illustrates a rising edge circuit  80  and a falling edge circuit  82 . The rising edge circuit  80  generally comprises a switch  84  and a current source  86 . When a signal is received from the output  66 , the switch  84  generally closes, which adds the current source  86  into the path, which may provide additional bias for a boost to the rising edge of the output signal. The rising edge circuit  80  generally presents such a bias boost at an output  88 . The falling edge circuitry  82  generally comprises a switch  94 , a current source  96  and an output  98 . When the switch  94  receives the signal from the output  68 , the switch  94  generally closes, which adds the current source  96  into the path. By adding the current source  96 , an additional bias current may be presented for a falling edge boost. The additional bias is generally presented at an output  98 . The current source  86  is generally sized to be 10-50% of the size of the current source  102 . The current source  96  is generally sized to be 10-50% of the size of the current source  104 . The rising edge circuit  80 ′, the falling edge circuit  82 ′, the current source  86 ′ and the current source  96 ′ provide similar functions to present the output B. 
     FIG. 7 also illustrates an output section  100 . The output section  100  generally comprises a current source  102  and a current source  104 . An example of the output section  100  may be found in application “LOW SPEED DRIVER FOR USE WITH THE UNIVERSAL SERIAL BUS”, Ser. No. 08/828,537, Filed Mar. 31, 1997, now issued as (U.S. Pat. No. 5,872,473) which is hereby incorporated by reference in its entirety. In general, the circuit  34  does not provide the additional bias currents for either a falling or rising edge until the signal Vcm shifts enough to trip either the positive threshold of the inverter  70  or the negative threshold of the inverter  74 . When the signal Vcm does shift enough to trip the inverter  70  or the inverter  74 , the appropriate edge boost is presented to re-center the voltage Vcm. The output section  100 ′, the current source  102 ′ and the current source  104 ′ generally provide similar functions to present the output signal B. 
     Referring to FIG. 8, a circuit diagram of the various components described in connection with FIGS. 1-7 is shown. The capacitor C 1  and C 2  are shown having exemplary capacitances of 0.5 pF. However, the capacitance values may be adjusted to the design criteria of a particular application. For example, a capacitance value of between 0.25 pF and 1.0 pF may be appropriate. However, smaller capacitances or higher capacitances may be implemented accordingly. The capacitor C 1  should be matched to the capacitor C 2  to provide the proper detection of the signal Vcm. By matching the capacitance C 1  with the capacitance C 2 , the common mode voltage Vcm may be controlled while keeping the rise and fall times of the output signals A and B approximately matched. The matching of the capacitances of the capacitor C 1  and C 2  may be done by implementing the capacitors at the same time and with the same size and shape during the fabrication process. 
     The output buffer  14  may be suitable for applications in both a low-speed and high-speed Universal Serial Bus devices. The output buffer  14  may receive any signal such as an internal data signal, logic block inputs and outputs in the logic device, input registers in the memory device or other such input signals. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.