Abstract:
A method for forming a vertical transistor and a trench capacitor. A semiconductor substrate having a pad stacked layer on the surface and a trench formed therein is provided. A capacitor is formed at the bottom part of the trench and a portion of the upper sidewall of the trench is exposed. A conductive wire is then formed on the capacitor, followed by forming a dielectric layer on the exposed sidewalls of the trench. A trench top dielectric is then formed by liquid phase deposition on the conductive wire. A transistor is then formed on the trench top dielectric, which isolates the transistor from the capacitor.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor process for fabricating memory cells, and in particular to method for forming a vertical transistor and a trench capacitor.  
           [0003]    2. Description of the Related Art  
           [0004]    In the process for fabricating integrated circuits with higher integration density, size reduction for each memory cell and power consumption must be considered and optimized in order to enhance its access speed. Conventional designs for planar transistors tend to decrease the gate lengths in transistors, thus reducing lateral areas of each memory cell. However, leakage resistance of the gate is decreased and the voltage applied on the wordline must be relatively reduced. Consequently, electric charges stored in capacitors decrease. Due to the above, capacitors with greater capacitance must be considered for shortened lateral gate lengths. Methods for increasing capacitance of a capacitor include increasing capacitor area, and reducing effective thickness of the dielectric layer between plates. In practical applications, reduced memory cell areas and increased capacitor areas cannot be satisfied simultaneously. Reduction of the effective thickness of the dielectric layer is also limited.  
           [0005]    Hence, vertical transistor structures are widely applied in the semiconductor industry. By doing so, it is possible to have appropriate gate length for obtaining a low leakage, without reducing the voltage applied on wordlines or increasing the lateral area of memory cells. Moreover, the method also features the formation of a deep trench capacitor directly below the vertical transistor, which greatly reduces the area occupied by memory cells.  
           [0006]    A current process for forming a vertical transistor and a trench capacitor is shown in FIG. 1. After the formation of a deep trench capacitor C (comprising a plate  20 , a capacitor dielectric layer  18  and a buried plate  16 ), a conductive wire (consisting of a collar dielectric layer  21 , a first conductive layer  24  and a second conductive layer  22 ) is formed on the capacitor. Next, high density plasma (HDP) is used to form a trench top oxide (TTO) on the conductive wire for isolation. A transistor (consisting of a gate oxide  28 , a conductive layer (not shown), a spacer (not shown), and a source/drain are then formed to complete the vertical transistor and the trench capacitor.  
           [0007]    However, in the above-mentioned method, the surface of the TTO  26 , formed by HDP, tends to incline from one end to the other, as shown in FIG. 1. An ideal TTO with a planar surface is difficult to obtain due to the restrictions of the HDP process. In addition, if uniformity of the TTO is not satisfactory, one sidewall of the trench is not sufficiently protected by the oxide layer, thus insulation is not satisfactory. Consequently, excess ion diffusion (such as As) under the vertical transistor occurs. This brings adverse effects to the reliability of the gate oxide, and overall performance of the element deteriorates.  
         SUMMARY OF THE INVENTION  
         [0008]    Accordingly, an object of the invention is to provide a method for forming a vertical transistor and a trench capacitor to overcome conventional problems and meet the quality requirements.  
           [0009]    The invention features the formation of the trench top oxide (TTO) by liquid phase deposition (LDP). In a LDP process, a wafer is completely dipped into a chemical solution, thus avoiding the conventional problem of deposition angle associated with the high density plasma process. The trench top oxide is evenly and uniformly formed in the trench to acquire a TTO with a smooth, uniform and planar surface.  
           [0010]    In order to achieve the above object, the invention provides a method for forming a vertical transistor and a trench capacitor. The method includes the steps of: providing a semiconductor substrate having a pad stacked layer on the surface and a trench formed therein is provided; forming a trench capacitor at a bottom part of the trench and partially exposes the sidewall; forming a conductive wire on top of the trench capacitor in the trench; forming a dielectric layer on the exposed sidewall of the trench; forming a trench top dielectric by liquid phase deposition on the conductive wire; and forming a vertical transistor on the trench top dielectric, which isolates the vertical transistor from the trench capacitor.  
           [0011]    According to the method provided, a TTO with a planar surface and a uniform thickness is formed. Therefore, an excellent insulation effect is obtained, and reliability of the gate oxide formed in the follow-up steps is enhanced. Semiconductor elements with excellent characteristics are then obtained.  
           [0012]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0014]    [0014]FIG. 1 is cross section showing a conventional vertical transistor and a trench capacitor.  
         [0015]    FIGS.  2 A˜ 2 F are cross sections illustrating the process of the method provided in the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    FIGS.  2 A˜ 2 F are cross sections illustrating the process of the embodiment of the invention.  
         [0017]    As shown in FIG. 2A, a semiconductor substrate  100  having a pad stacked layer (comprises an oxide layer  114  and a nitride layer  112 ) formed on the surface is provided. Next, a patterned photoresist layer (not shown) is used to define the position of a trench. Reactive ion etching is then used to form a trench  125  in the substrate  100 .  
         [0018]    Next, a capacitor C is formed at the bottom of the trench  125  by sequentially forming a buried plate  126 , a capacitor dielectric layer  118  and a plate  120 . The buried plate is, for example, an N+ doped region, located in the substrate surrounding the bottom of the trench  125 . The plate  120  is preferably doped polysilicon and the capacitor dielectric layer  118  is preferably an oxide-nitride (ON) structure, or oxide-nitride-oxide (ONO). In detail the process for forming the trench capacitor begins with the formation of an N+ doped dielectric layer such as Arsenic doped silicon glass (ASG), covering the sidewall and the bottom of the trench  125 . Photoresist material is then formed in the trench  125  to a certain depth, followed by wet etching to remove the doped dielectric layer not covered by the photoresist material. The photoresist material is then removed, and an insulation layer, such as tetraethylorthosilane, is conformally formed. The insulation layer is formed to prevent diffusion of doped ions out to the substrate around the trench  125  not protected by the doped dielectric layer in the follow-up thermal process. Next, ions doped in the doped dielectric layer are driven to the substrate to form an N+ doped region, on the buried plate  116 . The insulation layer and the doped dielectric layers are then removed, followed by the formation of a dielectric layer on the sidewall and the bottom of the trench to form the capacitor dielectric layer  118 . The plate  120  is then formed by filling the trench with conductive material.  
         [0019]    After the formation of the trench capacitor, as shown in FIG. 2B, an insulation layer, such as oxide, is conformally formed. Etching is then used to remove the insulation  122 , from the pad stacked layer and from the capacitor. A first conductive layer  124  is then formed to fill the trench  125 , followed by etching back to lower its surface to a certain depth. Again, etching back is performed to lower the surface of the insulation layer  122  to a level below the conductive layer  124  to form a collar dielectric layer  122 ′, as shown in FIG. 2C. A second conductive layer, such as undoped polysilicon or amorphous silicon is formed on the collar dielectric layer  122 ′, followed by etching back to a level equal to the first conductive layer  124 . The first conductive layer  124 , the collar dielectric layer,  122 ′ and the second conductive layer  126 , thus form the conductive wire.  
         [0020]    Next, as shown in FIG. 2D, a dielectric layer, such as SiN, is conformally formed to cover the nitride layer  112 , along the sidewall of the trench and the first conductive layer  124 , followed by isotropic etching to remove the nitride on the nitride layer  112  and the first conductive layer  124 . Alternatively, the dielectric layer is oxynitride, or high dielectric constant materials, such as Al 2 O 3 , HfO 2 , Ta 2 O 5  and combinations of above dielectric films. The dielectric layer remaining on the sidewall is referred to as  128 . Liquid phase deposition is then carried out at 0˜80° C. to form a dielectric layer  130 , as the trench top dielectric, to cover the first conductive layer  124 . Preferable thickness of the trench top dielectric is 10˜1000 angstroms. The trench top dielectric is used to isolate the conductive wire and the control gate formed in the follow-up process. In this embodiment, the trench top dielectric is oxide.  
         [0021]    In the liquid phase deposition (LPD) process, the wafer is dipped into an H 2 SiF 6  solution with titration of H 3 BO 3  solution (or H 2 SiF 6  titration with H 2 O). Chemical reactions of the above process are as follows:  
         H 2 SiF 6 +2H 2 O         SiO 2 +6HF  (1)  
         H 3 BO 3 +4HF         BF 4   − +H 3 O + +2H 2 O  (2)  
         [0022]    In reaction (1), SiO 2  is deposited, and the reaction product HF is consumed in reaction (2) to avoid reverse reaction. The deposition rate of SiO 2  is controlled by titration. Since the wafer is completely dipped into the solution, conventional problems associated with deposition angle when using high density plasma is avoided. As a result, the trench top dielectric is formed evenly and uniformly in the trench to obtain a trench top dielectric having a uniform thickness.  
         [0023]    Next, as shown in FIG. 2E, wet etching is used to remove the dielectric layer  128  on the sidewall not covered by the trench top dielectric  130 , and the dielectric layer  128 ′ remains on both sides of the trench top dielectric. A conventional process is then performed to form a gate oxide  132  and a gate conductive layer  140  on the trench top dielectric  130 . The gate conductive layer is preferably polysilicon, WSi, metal or combinations thereof. A preferable method for forming the gate oxide and the gate conductive layer is forming the gate oxide layer  132  on the sidewall of the trench by thermal oxidation, followed by filling the area surrounded by the gate oxide layer with conductive material to form the gate conductive layer  140 . In this embodiment, the gate oxide layer  132  and the gate conductive layer  140 , thus form a control gate. Ion implantation is then performed to form a doped region in the substrate around the top of the control gate to serve as a source  160  of the vertical transistor. Formation of a drain  170  is carried out by thermal diffusion to diffuse the doped ions in the first conductive layer  124  via the second conductive layer  126  into the substrate. An electrical connection between the capacitor to the control gate is then formed.  
         [0024]    Then, an insulation material, such as oxide or nitride, is conformally formed covering the nitride layer  112  and the sidewall and the bottom of the trench. Anisotropic etching is carried out to remove a portion of the insulation layer without removing the insulation material on the sidewall. The insulation layer remaining on the sidewall is the spacer  142 , as shown in FIG. 2F. Finally, a conductive layer, such as doped polysilicon, WSix, or metal, is formed by filling the trench, followed by chemical mechanical polishing to form a smooth surface. A conductive layer  150  is thus obtained, as shown in FIG. 2F.  
         [0025]    According to the method provided in the invention, a trench top dielectric layer with a smooth/uniform surface is obtained by liquid phase deposition at a temperature range from 0 to 80° C. Consequently, the insulating effect is enhanced and the reliability of the overall performance of the semiconductor element is increased.  
         [0026]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.