Abstract:
An integrated circuit may have a clock input pin coupled to a buffer ( 24 ). The buffer may supply a clock signal ( 28 ) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is a continuation of U.S. patent application Ser. No. 13/519,846, filed Aug. 24, 2012, and issued as U.S. Pat. No. 8,824,235 on Sep. 2, 2014, which application is a National Stage Entry of International Application No. PCT/IT09/00592 filed Dec. 30, 2009. The aforementioned applications and patent are incorporated herein by reference, in their entirety for any purpose. 
    
    
     TECHNICAL FIELD 
     This relates generally to clock input buffers. 
     BACKGROUND 
     Typically, clock input buffers are used to control inputs to a variety of circuits. For example, in connection with a low power double data rate 2 (LPDDR2) synchronous dynamic random access memory (LPDDR2-S (SDRAM)) or non-volatile memory (LPDDR2-N), the input buffers of all signals, except the clock, can be disabled using a clock enable (CKE) input signal. The clock input buffer consumes power, even when the clock is stable, because the clock input buffer is implemented with a differential amplifier. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit schematic for one embodiment; 
         FIG. 2  is a more detailed circuit schematic for one embodiment of the present invention; 
         FIG. 3  is a timing diagram for the clock enable signal in accordance with one embodiment; 
         FIG. 4  is a timing diagram for the clock and clock inverse signals in accordance with one embodiment; 
         FIG. 5  is a timing diagram for the CLK_int signal in accordance with one embodiment; 
         FIG. 6  is a timing diagram for the INPUT_ENABLE signal in accordance with one embodiment; 
         FIG. 7  is a timing diagram for the signal CLK_EN_RST in accordance with one embodiment; 
         FIG. 8  is a timing diagram for the CLK_EN_SET signal in accordance with one embodiment; 
         FIG. 9  is a timing diagram for the CLK_BUFF_ENABLE signal in accordance with one embodiment; and 
         FIG. 10  is a flow chart for one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , an integrated circuit package  11  may include contacts  10 ,  12 ,  16 ,  18 , and  20 . Integrated circuit package  11  may enclose an integrated circuit  52  coupled to buffers  14 ,  22 , and  24 . The buffers buffer input signals from contacts  10 ,  12 ,  16 ,  18 , and  20 . An enable circuit  50  may control power consumption of buffers  14  and  24  to disable them to reduce power consumption and then to quickly enable them for integrated circuit operations. 
     In some embodiments, enable circuit  50  powers down the buffer  24  in particular to reduce its power consumption by providing an enable signal to the EN input of that buffer. Then when it is desired to operate the integrated circuit  52 , the buffer  24  can be enabled quickly, in some embodiments. For example, in some embodiments, in response to a given number of toggles of a clock signal, buffer  24  may be quickly enabled. This is particularly advantageous in connection with low power double data rate 2 memories, for example. 
     Contacts  10 ,  12 ,  16 ,  18 , and  20  may be on the outside of an integrated circuit package  11  and circuit  52  may be an integrated circuit chip within package  11 . It may, for example, be a memory circuit and, as one example, the chip  52  may be a low power double data rate 2 memory. 
     Input buffers  14  (only one shown in  FIG. 1 ) may be coupled to contacts  10  and  12 . Contact  10  may be associated with the input signal Vref or reference voltage and contacts  12  may be for other inputs. Thus, contacts  10  and  12  may be associated with various connectors on the outside of an integrated circuit package. These connectors may be lands, pins, solder balls, sockets, or any of a variety of electrical connectors used in integrated circuit packaging. In addition, there may be a contact  16  for the clock enable signal, a contact  18  for the clock signal, and a contact  20  for the clock inverse signal. 
     Referring to  FIG. 2 , clock enable signal from contact  16  goes to a buffer  22  that is, in turn, coupled to the enable circuit  50 , and, particularly, a DQ flipflop  34  in one embodiment. DQ flipflop  34  has a clock input CK, an input D, and an output Q in one embodiment. DQ flipflop  34  may be edge triggered and, in one embodiment, may be positive edge triggered. On the rising edge of the clock (CK), the input D may be sampled and transferred to the output Q. At other times, the input D may be ignored. 
     Clock contact  18  may be coupled to a buffer  24 , that outputs a signal CLK_int  28 , which is the clock (CK) input to DQ flipflop  34 . The negative input to buffer  24  is from clock inverse contact  20 . 
     The clock signal from the contact  18  may also go through a low power consumption complementary metal oxide semiconductor (CMOS) buffer  26  to create CLK_CMOS signal  30 , which becomes the clock input to the clock detector  31  in one embodiment. The clock detector output (CLK_EN _SET)  33  may be provided to the set terminal of an SR latch  32 . The reset terminal may be coupled to the CLK_EN _RST signal  37  from the output of a falling edge detector  35 . The falling edge detector  35  detects the falling edge of the INPUT_ENABLE signal  36  from the DQ flipflop  34 , in one embodiment. 
     The Q output of SR latch  32  is the signal CLK_BUFF_ENABLE  38 , provided to the enable input of the buffer  24  in one embodiment. SR latch  32  output Q may be low when set is pulsed low and reset is high and may be high when set is high and reset is low. Buffer  24  may be enabled when signal  38  from output Q of SR latch  32  is high. When signal  38  is low, buffer  24  may be disabled, resulting in power savings. 
     Clock input buffer  24  may consume power even when the clock CLK is stable, for example, when buffer  24  is implemented with a differential amplifier. Clock differential input buffer  24  may be disabled during power down of clock enable signal to reduce the current consumption. In fact, current consumption may be in the range of standby current in some embodiments. The time needed to enable the clock input buffer  24  at power down exit may be material, in some embodiments, because the clock input is used to latch the command/address bus in a LPDDR2 memory, for example. 
     In the case where circuit  52  is an LPDDR2 memory, the clock may toggle two times before raising the clock enable signal to exit power down in one embodiment. Clock detector  31  may detect clock toggling with dedicated circuitry to enable, in advance, the clock differential input buffer. 
     Clock differential input buffer  24  may be disabled when integrated circuit  52  enters the power down mode and may be enabled when the clock starts to toggle again. Detector  31  may detect clock toggling (e.g. one or two toggles) and may enable clock differential input buffer  24 . 
     Thus, referring to  FIG. 3 , the clock enable (CKE) signal, in this example, may fall during a period of high power consumption to transition to a powered down, lower power consumption mode. The clock (CLK) signal is shown in solid lines and the clock inverse (CLK#) signal is shown in dashed lines in  FIG. 4 . The CLK_int signal  28  is the buffered clock signal, as shown in  FIG. 5 . 
     The falling of the clock enable signal ( FIG. 3 ) followed by a rising edge of the CLK-int signal  28  ( FIG. 5 ) may trigger, as indicated by the arrow A, the INPUT_ENABLE signal  36 , shown in  FIG. 6 . As a result, that signal  36  may fall after a delay from the drop in the clock enable signal. The falling edge of the INPUT_ENABLE signal  36  triggers the falling edge detector  35  ( FIG. 2 ), as indicated by the arrow B, to issue the CLK_EN _RST signal  37 , shown in  FIG. 7 . The signal  37  triggers the SR latch to issue the CLK_BUFF_ENABLE signal  38 , as indicated by arrow C. The falling signal  38  powers down the buffer  24  in one embodiment. The INPUT_ENABLE signal  36  may enable or disable the buffers  14  in  FIG. 2 . 
     Thus, power consumption transitions from high power consumption, due to consumption of power in input buffers, including the buffer  24 , and enters a lower power consumption state where all the input buffers, including the buffer  24 , are powered down. 
     When the CLK signal ( FIG. 4 ) undergoes a couple of cycles, in one embodiment, the clock detector  31  responds, as indicated by arrow F, causing the set input to the latch  32  to invert so that its output signal  38  goes high ( FIG. 9 ), as indicated by the arrow G. This enables the buffer  24 , as indicated by the arrow D and the CLK_int signal  28 . 
     At the first CLK_int rising edge with rising clock enable, the output INPUT_ENABLE signal  36  ( FIG. 6 ) switches to high, as indicated by the arrow E. Thus, the clock input buffer  24  may be powered down to save power consumption and can be powered back up in response to toggling of the clock (CLK) signal. 
     In the embodiments described herein, the clock signal ( FIG. 4 ) rising edge (after a period of inactivity of the clock) generates a pulse of CLK_EN_SET signal  33  ( FIG. 7 ). The output of the clock detector  31  sets the CLK_BUFF_ENABLE signal  38  ( FIGS. 9 ) and enables the CLK/CLK# differential buffer  24 . 
     Referring to  FIG. 10 , the power control sequence  54  may be implemented in software, hardware, or firmware. In a software embodiment, it may be implemented by instructions stored within a computer readable medium such as a semiconductor, optical, or magnetic memory. 
     The instructions are executed by a processor or controller. For example, the instructions may be stored within a storage within the enable circuit  50  and executed by an enable circuit processor in accordance with one embodiment. 
     Initially, a check at diamond  56  determines whether a clock enable signal has gone low. If so, a power down or power reduction is implemented, as indicated in block  58 . Then, at block  60 , when the clock signal starts up again, the clock signal is detected. This detection may include counting the number of clock toggles. When detected (or, for example, with a threshold number of toggles is exceeded), as determined in diamond  62 , then the circuit is powered up, as indicated in block  64 . 
     References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application. 
     While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.