Abstract:
A synthetic-speech calculator includes a keyboard consisting of digit keys and function keys and, if desired, or more mode selectors, a desired number of registers for storing numerical information entered by the depression of selected ones of the digit keys, a read-only-memory for storing a large number of digital codes as sound quantizing information, counter means for specifying the address of the memory so as to take a specific digital code out of the memory, a digital-to-analogue converter for converting the specific digital code taken out of the memory into an audible sound signal, and a loud speaker driven by the audible sound signal and producing an audible sound. There are further provided means for producing audible sounds indicative of not only numerical information but also its associated conditional information having a particular meaning with respect to that numerical information, for example, position information, index information, tabulation information, etc. This numerical information and conditional information is derived in different audible forms.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an improvement in a synthetic-speech calculator. 
     A synthetic-speech calculator is well knwon in the art of calculators. The prior art synthetic-speech calculator was adapted such that respective ones of digit keys and function keys were assigned own unique audible sounds. The operation results or entered information was not easily distinguishable from other information not assigned a unique audible sound, for example, index information and tabulation information. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the present invention to provide an improvement in a synthetic-speech calculator which provides audible sounds indicative of not only numerical information but also conditional information having a particular meaning with respect to that numerical information. 
     In one preferred form of the present invention, a synthetic-speech calculator includes a keyboard consisting of digit keys and function keys, a desired number of registers for storing information entered by the depression of selected ones of the digit keys, a read-only-memory for storing a large number of digital codes as sound quantizing information, counter means for specifying the address of the memory so as to take a specific digital code out of the memory, a digital-to-analog converter for converting the specific digital code taken out of the memory into an audible sound signal, and a loud speaker driven by the audiable sound signal and producing an audible sound. There are provided means for producing audiable sounds indicative of not only numerical information but also conditional information having a particular meaning with respect to that numerical information, such as index information, position information and tabulation information. Sound quantizing digital codes indicative of such conditional information are previously loaded into the read-only-memory. 
     In the case of a law-of-exponent calculator, distinction codes are interposed between the mantissa portion and index portion. When a decision circuit senses the development of the distinction codes, digital codes indicating exponent information are derived from the read-only-memory. Alternatively, in the case of a conventional calculator, a counter is provided to sense the most significant digit of numerical information contained within a piece of a random-access-memory and provide the output thereof for an address counter associated with the read-only-memory, enabling the loud speaker to produce audible sounds indicative of the most significant digit type position information. This makes it easy for the operator to register operation results in a correct position while these are being delivered in an audible form. Further, pursuant to the teachings of the present invention, it is possible to produce audible sounds indicative of, for example previously selected tabulation information as soon as a power switch is thrown or a specific key is manually depressed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and novel features of the present invention are set forth in the appended claims and mode of operation will best be understood from a consideration of the following detailed description of the embodiments taken in conjunction with the accompanying drawings, wherein; 
     FIG. 1 is a perspective view of a synthetic-speech calculator embodying the present invention; 
     FIG. 2 is a block diagram of the synthetic-speech calculator shown in FIG. 1; 
     FIG. 3 shows an example of the contents of a register in case of a law-of-exponent calculator; 
     FIG. 4 is a circuit diagram which is effective in producing audible sounds indicative of exponent information; 
     FIG. 5 is a block diagram showing another preferred form of the present invention; 
     FIG. 6 is a flow chart provided for the purpose of explanation of operation of the embodiment shown in FIG. 5; 
     FIG. 7 shows an example of the contents of a register in the embodiment of FIG. 5; 
     FIG. 8 is an example of audible output forms in the example of FIG. 7. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to FIG. 1 of the drawings, there is illustrated a perspective view of a synthetic-speech calculator embodying the present invention in the first embodiment which includes a body 1, a display 2, a power switch 3, a loud speaker 4, a sound key 5 available for indicating that keyed information or operation results are to be produced in an audible form, and digit keys and function keys 6. The speech synthesis technique is fully disclosed in many of U.S. Patents, for example, U.S. Pat. No. 3,102,165, SPEECH SYNTHESIS SYSTEM to Genung L. Clapper and U.S. Pat. No. 3,398,241, DIGITAL STORAGE VOICE MESSAGE GENERATOR to Lyle H. Lee. 
     FIG. 2 illustrates a block diagram of the synthetic-speech calculator. A keyboard KB contains a family of digit keys 10K, a family of functions keys FK, etc. In response to the depression of a specific key, the corresponding signals are introduced into an encoder EC for code conversion. The outputs of the encoder EC are sent to a calculation circuit or central processor unit CPU and an output register OR. Keyed information and operation results are transferred from the output register OR to an address counter AC via the central processor unit CPU. The address counter AC is coupled with a read-only-memory ROM storing a large number of voice quantizing digital codes in advance. The address counter AC provides access to specific areas of the ROM containing selected ones of the voice quantizing digital codes. By the addressing of the ROM, the digital codes indicative of keyed information and operation results are picked up and converted into an audible form via a digital-to-analog converter D/A, a low-pass filter LPF, a speaker driver D and the loud speaker SP. As noted earlier, the ROM stores the digital codes that sample analog voice information containing vocal sounds, syllables, words etc., and quantize them at preselected amplitude levels. Fidelity of the reproduction from the ROM depends largely upon the number of samples and the number of quantizing levels. Amplitude quantum is a binary code and four-level quantizing requires two bits of binary codes, thereby enhancing fidelity. Sixteen-level quantizing with four bits of binary codes is substantially free of distortion. 
     According to a law-of-exponent calculator, numerical information consists generally of a mantissa and an index as shown in FIG. 3. In a first example (a), the mantissa portion is 1.2345 and the index portion is 10 12  (the twelfth power of 10). Numerical information is stored in the output register OR and distinction codes such as blank codes and negative sign codes are interleaved to establish a distinction between the mantissa portion and index portion. For example, five bits of &#34;01111&#34; are selected for the blank codes and ones of &#34;11111&#34; are selected for the negative sign codes apart from the code representation of numerical information. 
     These distinction code signals are supplied to the address counter AC. The blank codes &#34;01111&#34; specify the digital codes indicative of distinction sounds between the mantissa portion and index portion, followed by addressing the sound quantizing digital codes corresponding to a word &#34;power&#34; in the tenth power. The thus addressed digital codes are sequentically taken out of the ROM, producing audible sounds via the loud speaker beginning with the mantissa portion. Numerical information indicative of the index portion is then derived in the order of &#34;twelfth&#34;, &#34;power&#34;, and &#34;of ten&#34;. For the example of (b), audible sounds &#34;five&#34;, &#34;point&#34;, &#34;three&#34;, &#34;six&#34;, &#34;seven&#34;, &#34;multiply&#34;, &#34;power&#34;, &#34;minus&#34;, &#34;power&#34;, &#34;of&#34;, and &#34;ten&#34; are produced in a sequence. 
     FIG. 4 shows another preferred form of the present invention wherein a way to produce the mantissa portion in an audible form is different from that for the index portion. The components in the embodiment of FIG. 4 are given the same numbers as in FIG. 2 wherever possible in order to point up the close relationship. While the mantissa portion may be produced digit-by-digit in a audible form despite its digit significance, when producing audible sounds of the index portion. As mentioned previously, the register OR stores the blank codes &#34;01111&#34; and the negative sign codes &#34;11111.&#34; Either of these codes are sensed via AND gates g1, g2, an OR gate O 1  and an AND gate g3, placing a flip flop F 1  into the set condition. When the flip flop F 1  is in the set state, the set output a is developed to indicate the next succeeding information relates to the index portion. The set output a of the flip flop F 1  is supplied to the ROM to select information while taking digit significance into consideration. In this instance, the sound &#34;power&#34; is necessarily produced after the delivery of audible sounds of the mantissa portion. It is obvious that the present invention is applicable to power calculations. 
     FIG. 5 shows still another embodiment of the present invention the position of the most significant digit of numerical information is indicated in an audible form in advance to the delivery of that numerical information in the case of a conventional calculator. For example, if the most significant digit of numerical information is in the eighth digit position, then audible sounds &#34;line&#34;, and &#34;eight&#34; are sequentially produced in accordance with the present invention. In FIG. 5, a register X stores numerical information and an address counter R 1  specifies the address of the register X beginning with the most significant digit thereof and ending with the least significant digit. A buffer register DC 1  stores the specific digit position of the register X which is addressed by the address counter R 1 . 
     An address counter VAC sequentially addresses the ROM RV, producing audible sounds indicative of not only numerical information contained within the register X but also position information indicative of the position of the most significant digit position of that numerical information. For the purpose of the invention three decision circuits or latches F B , F C  and K are provided. Mode of operation of the synthetic-speech calculator shown in FIG. 5 will be described referring to a flow chart of FIG. 6. Assume now that numerical information contained within the register X is &#34;123456&#34; as in FIG. 7. 
     Initially, the latches F C , F B  and K are reset for operation in the steps n 1 , n 2  and n 3 . The address counter R 1  is loaded with &#34;8&#34; in the step n 4  (that is, the most significant digit is at the eighth position). The step n 5  permits the contents of the register X specified by the address counter R 1  to be transferred into the buffer register X 0 . Information at the eighth digit position of the register X is φ entered into the buffer register X 0 . Because the latch K is initially in the reset state, the step N 7  is advanced where decision is effected as to whether X 0  =0 to inhibit spurious display of upper &#34;0 S  &#34;. If X 0  is &#34;0&#34;, the address counter R 1  is one reduced in the step n 8 . Therefore, R 1  =7. The step n 5  (X→X 0 ) is returned where information at the seventh digit position of the register S is shifted into the buffer register X 0 . These steps are repeatedly carried through. The seventh-digit information is entered into the buffer register X 0 , proceeding toward the step n 8  because of X 0  =). R 1  -1 is effected with R 1  =6. In the next step n 5  (X→X 0 ) X 0  ≠0 is established for the first time (X 0  receive &#34;1&#34; at this time). The latch K is placed into the set state in the step n 8 , followed by the step n 9 . Under the circumstances the address counter VAC specifies the initial address. The procedure L→VAC in the step n 9  allows the initial address of an area of the ROM containing the sounds &#34;line&#34; to be specified. Thereafter, the flip flop F A  is set in the step n 10 , starting to produce audible sounds &#34;line.&#34; The step n 11  deals with decision as to whether the output of the ROM is an END code, which is usually loaded at the end of each word. The address counter VAC keeps on incrementing in the step n 12  to complete the production of audiable sounds &#34;line&#34; until the END code is reached. Upon the END code sensed the flip flop F A  is reset in the next step n 13  and the address counter VAC is also reset in the step n 14 . The address counter VAC in the reset state does not specify any of the respective areas of the ROM. The latch F C  is reset in the step n 15 , followed by the step n 16  because of F C  =0. The procedure R 1  = 0 means decision as to whether the overall contents of the register X including the least significant digit position or the first digit position have been taken out, and a terminating requirement for the procedure 8→R 1  in the step n 4 . The n 5  step is reverted to effect operation X→X 0  when R 1  ≠0. The address of the register X remains unchanged R 1  =6 with the buffer X 0  loaded with &#34;1&#34;. The latch K is set in the step n 8  to make up a sequence of the events n 16  →n 18  →n 19  →n 20 . After setting the flip flops F B  and F C , R 1  →VAC is achieved in the step n 21 . R 1  =6 specifies an area of the ROM containing voice &#34;SIX&#34;. The chained steps n 10  →n 14  allows sounds &#34;six&#34; to be produced via the loud speaker. The latch F C  in the step n 15  reveals that F C  =1  in the preceding step n 20 , proceeding toward the steps n 15  →n 16 . The procedure ·→VAC in the step n 16  is effected for the reason that a simple sound for example &#34;peep&#34; is to be unterposed between &#34;line six&#34; and &#34;numerical data.&#34; Thus, the initial address of an area containing a sound &#34;peep&#34; is specified. After ·→VAC, the latch F C  is reset in the step n 17  to return back to the step n 15 . A sequence of the steps n 15  →n 16  →n 5  is carried through because F C  in the reset state in the step n 17 . X→X 0  is a data input to the sixth digit position of the X register as ever. The steps n 6  →n 18  →n 22  are effected so that the address counter R 1  for the X register is decremented with R 1  =5. The procedure X 0  →VAC in the step n 23  is to specify the initial address of an area of the ROM containing audible sounds &#34;one&#34; which corresponding to &#34;1&#34; at the sixth digit position. Audible sounds indicative of numerical data are produced in the next succeeding steps n 10  →n 14 . 
     This follows the steps n 15  →n 16  →n 5 . Because R 1  =5 in the procedure X→X 0  the fifth digit position data &#34;2&#34; is introduced into the buffer X 0 . The steps n 18  n 22  results in R 1  -1=4. The step n 23  specifies the initial address of an area of the ROM containing sounds &#34;two&#34;. The sounds &#34;two&#34; are produced in the steps are n 10  -n 14 . The above mentioned procedures are repeated such that the fifth digit data of the X register is introduced into the buffer X 0  in the step n 5 . The development in the steps n 6  →n 18  →n 22  results in R 1  -1=0. The address counter VAC in the step n 23  specifies the initial address of an area containing sounds &#34;six&#34; the first digit position data). Audible sounds of the first digit position data are produced with advance to n 15  →n 16 . R 1  =0 halts all the procedures. FIG. 8 shows the order of the audible sounds produced from the loud speaker SP. 
     Occasionally, a calculator contains one or more mode selectors on the operation panel, for example, a tabulation selector, a normal/constant operation selector and a counting fraction selector. Through the use of the present invention it is possible to produce audible sounds indicative of the operation states of these selector. Furthermore, audible sounds indicative of the operation states of the mode selector may be produced once a power switch is thrown or a specific function key (e.g., a clear key c, is depressed. 
     While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as claimed.