Abstract:
An apparatus for power conversion comprises a voltage transformation element, a regulating element, and a controller; wherein, a period of the voltage transformation element is equal to a product of a coefficient and a period of the regulating circuit, and wherein the coefficient is selected from a group consisting of a positive integer and a reciprocal of said integer.

Description:
RELATED APPLICATIONS 
     Under 35 USC 119, this application claims the benefit of the priority date of U.S. Provisional Application 61/577,271 filed on Dec. 19, 2011, the contents of which are herein incorporated by reference. 
    
    
     FIELD OF DISCLOSURE 
     This disclosure relates to the control of power converters that utilize capacitors to transfer energy. 
     BACKGROUND 
     Power converters may generally include switches and one or more capacitors. Such converters can be used, for example, to power portable electronic devices and consumer electronics. 
     A switch-mode power converter is a specific type of power converter that regulates an output voltage or current by switching energy storage elements (i.e. inductors and capacitors) into different electrical configurations using a switch network. 
     A switched capacitor converter is a type of switch-mode power converter that primarily utilizes capacitors to transfer energy. In such converters, the number of capacitors and switches increases as the transformation ratio increases. 
     Typical power converters perform voltage transformation and output regulation. In many power converters, such as buck converters, both functions take place in a single stage. However, it is also possible to split these two functions into two specialized stages. Such two-stage power converter architectures feature a separate transformation stage and a separate regulation stage. The transformation stage transforms one voltage into another voltage, while the regulation stage ensures that the output voltage and/or output current of the power converter maintains desired characteristics. 
     For example, referring to  FIG. 1 , in one known power converter  10 , a switched capacitor element  12 A is electrically connected, at an input end thereof, to a voltage source  14 . An input of a regulating circuit  16 A is electrically connected to an output of the switched capacitor element  12 A. A load  18 A is then electrically connected to an output of the regulating circuit  16 A. Such a converter is described in US Patent Publication 2009/0278520, filed on May 8, 2009, the contents of which are herein incorporated by reference. 
     Furthermore, a modular multi-stage power converter architecture is described in PCT Application PCT/2012/36455, filed on May 4, 2012, the contents of which are also incorporated herein by reference. The switched capacitor element  12 A and the regulating circuit  16 A can be mixed and matched in a variety of different ways. This provides a transformative integrated power solution (TIPS™) for the assembly of such power converters. As such, the configuration shown in  FIG. 1  represents only one of multiple ways to configure one or more switched capacitor elements  12 A with one or more regulating circuits  16 A. 
       FIG. 2  illustrates a power converter  10 A that receives an input voltage VIN from the voltage source  14  and produces an output voltage VO that is lower than the input voltage VIN. The power converter  10 A is a particular embodiment of the power converter architecture illustrated in  FIG. 1 . The switched capacitor element  12 A features a 2:1 dual-phase series-parallel switched capacitor network that includes power switches S 1 -S 8  and pump capacitors C 1 -C 2 . In contrast, the regulating circuit  16 A features a buck converter that includes a low-side switch SL, a high-side switch SH, a filter inductor L 1 , and a driver stage  51 . 
     In the operation of the switched capacitor element  12 A, the power switches S 1 , S 3 , S 6 , S 8  and the power switches S 2 , S 4 , S 5 , S 7  are always in complementary states. Thus, in a first network state, the power switches S 1 , S 3 , S 6 , S 8  are open and the power switches S 2 , S 4 , S 5 , S 7  are closed. In a second network state, the power switches S 1 , S 3 , S 6 , S 8  are closed and the power switches S 2 , S 4 , S 5 , S 7  are open. The switched capacitor element  12 A cycles through the first network state and the second network state, resulting in an intermediate voltage VX that is one-half of the input voltage VIN. 
     Referring to  FIG. 2 , the switched capacitor element  12 A is in the first network state when a first phase voltage VA is high and a second phase voltage VB is low. In contrast, the switched capacitor element  12 A is in the second network state when the first phase voltage VA is low and the second phase voltage VB is high. The two phase voltages VA, VB are non-overlapping and have approximately a fifty percent duty cycle. 
     In the operation of the regulating circuit  16 A, the low-side switch SL and the high-side switch SH chop the intermediate voltage VX into a switching voltage VLX. A LC filter receives the switching voltage VLX and generates the output voltage VO that is equal to the average of the switching voltage VLX. To ensure the desired output voltage VO, a regulation control voltage VR controls the duty cycle of the low-side switch SL and the high-side switch SH. Additionally, the driver stage  51  provides the energy to open and close the low-side and high-side switches SL, SH. 
     Previous disclosures treat the control of the switched capacitor element  12 A and regulating circuit  16 A separately. This has numerous disadvantages, one of which is that the intermediate voltage VX ripple will feed through to the output voltage VO. A possible solution to this problem is to create a feed-back control loop that is fast enough to attenuate the effect of the intermediate voltage VX ripple on the output voltage VO. To achieve this goal, the frequency of the regulating circuit  16 A must be at a significantly higher frequency than the frequency of the switched capacitor element  12 A. 
     Another possible solution to this problem would be to add a feed-forward control loop to the regulating circuit  16 A. However, as was the case with the fast feed-back solution, the feed-forward solution will only be effective if the frequency of the regulating circuit  16 A is significantly higher than the frequency of the switched capacitor element  12 A. Therefore, both solutions place a severe frequency constraint on the switched capacitor element  12 A and the regulating circuit  16 A. 
     Furthermore, there is typically a dead-time interval DT between the first network state and the second network state of the switched capacitor element  12 A. During the dead-time interval DT, all of the switches in the switched capacitor element  12 A are open. This ensures a clean transition between the first network state and the second network state of the switched capacitor element  12 A, and vice versa. If the regulating circuit  16 A tries to draw current during the dead-time interval DT, a voltage ‘glitch’ will occur at the node between the switched capacitor element  12 A and the regulating circuit  16 A. 
     The voltage ‘glitch’ can be reduced through the use of a glitch capacitor CX. Unfortunately, a portion of energy stored on the glitch capacitor CX is thrown away each time the switched capacitor element  12 A transitions between the first network state and the second network state, and vice versa. The energy loss is a result of the glitch capacitor CX being shorted to capacitors at a different voltage, such as pump capacitors C 1 , C 2 . Therefore, the use of a glitch capacitor CX to supply energy during the dead-time interval DT is an effective solution, but requires one additional capacitor and reduces the efficiency of the power converter  10 A. 
     SUMMARY 
     In a general aspect of the invention, an apparatus for power conversion comprises a voltage transformation element, a regulating element, and a controller; wherein, a period of the voltage transformation element is equal to a product of a coefficient and a period of the regulating circuit, and wherein the coefficient is selected from a group consisting of a positive integer and a reciprocal of said integer. Embodiments of this aspect of the invention may include one or more of the following features. 
     The regulating element is configured to pass continuous current therethrough. Alternatively, the regulating element is configured to pass discontinuous current therethrough. 
     The regulating element is controlled so as to avoid passing current therethrough during a dead-time of the voltage transformation element. 
     The controller is configured to control multiple phases present in the regulating element and the voltage transformation element. The controller is configured to control multiple phases present in said regulating element and said voltage transformation element so as to avoid passing current therethrough during dead-times associated with each of said multiple phases. 
     The apparatus further comprises a data processing unit and a memory unit, at least one of which is configured to consume power provided by the power converter circuit. 
     In other embodiments, the apparatus further comprises a data processing unit, a display, and a wireless transmitter and receiver, at least one of which is configured to consume power provided by said power converter circuit. 
     In another aspect of the invention, an apparatus for power conversion comprises a first element configured to accept an input signal having a first voltage and to output an intermediate signal having a second voltage, a second element configured to receive the intermediate signal from the first element and to output an output signal having a third voltage. The first element is selected from a group consisting of a voltage transformation element and a regulating element, and said second element is a regulating element when the first element is a voltage transformation element and a voltage transformation element otherwise; and a controller configured to control a period of the voltage transformation element and a period of the regulating element, the controller being configured to synchronize the period of the voltage transformation element with a product of a coefficient and the period of the regulating element, wherein the coefficient is selected from a group consisting of a positive integer and a reciprocal of the integer. 
     Embodiments of this aspect of the invention may include one or more of the following features. 
     The coefficient is a positive integer, or alternatively, a reciprocal of the positive integer. 
     The controller is configured to receive the intermediate signal from the first element and the output signal from the second element. The controller is configured to receive the input signal. The controller is configured to generate a first control signal based on the output signal; and to send the first control signal to the regulating element. The controller is configured to generate a second control signal based on the intermediate signal and the first control signal; and to send the second control signal to the voltage transformation element. The controller is configured to provide linear voltage-mode control. The controller is configured to provide peak current-mode control. 
     The regulating element is configured to pass continuous current therethrough or, alternatively, the regulating element is configured to pass discontinuous current therethrough. The regulating element is configured to avoid passage of current therethrough during a dead-time of the voltage transformation element. 
     The voltage transformation element comprises a plurality of voltage transformation sub-elements and the regulating element comprises a plurality of regulating sub-elements, and wherein each voltage transformation sub-element is associated with a corresponding one of the regulating sub-elements. The first element comprises a voltage transformation element or comprises a regulating element. 
    
    
     
       DESCRIPTION OF THE FIGURES 
       The foregoing features of the circuits and techniques described herein, may be more fully understood from the following description of the figures in which: 
         FIG. 1  shows a known power converter architecture; 
         FIG. 2  shows a particular implementation of the power converter architecture in  FIG. 1 ; 
         FIG. 3  shows a controller coupled to the power converter in  FIG. 2 ; 
         FIG. 4  shows a particular implementation of the controller in  FIG. 3 ; 
         FIG. 5  shows a timing diagram of relevant signals from the embodiment in  FIG. 4 . 
         FIG. 6  shows a close-up of selected signals in  FIG. 5 ; 
         FIG. 7  shows a DC model of a switched capacitor element; 
         FIGS. 8A-8B  show the relationship between the load current and the intimidate voltage ripple; 
         FIG. 9  shows a controller that synchronizes a regulating circuit that precedes a switched capacitor element; 
         FIG. 10  shows a three-phase controller that synchronizes a three-phase switched capacitor element that precedes a three-phase regulating circuit; 
         FIG. 11  shows a particular implementation of the three-phase controller in  FIG. 10 ; and 
         FIGS. 12A-12B  show timing diagrams of relevant signals from the embodiment in  FIG. 11 . 
     
    
    
     DETAILED DESCRIPTION 
     The apparatus described herein provides a way to control the switched capacitor element  12 A and the regulating circuit  16 A in a modular multi-stage power converter architecture. 
     Before describing several exemplary embodiments of controllers for power converters that utilize capacitors to transfer energy, it should be appreciated that in an effort to promote clarity in explaining the concepts, references are sometimes made herein to specific controllers for power converters that utilize capacitors to transfer energy. It should be understood that such references are merely exemplary and should not be construed as limiting. After reading the description provided herein, one of ordinary skill in the art will understand how to apply the concepts described herein to provide specific controllers for power converters that utilize capacitors to transfer energy. 
     It should be appreciated that reference is also sometimes made herein to particular frequencies as well as to particular transformation voltage ratios. It should be understood that such references are merely exemplary and should not be construed as limiting. 
     Reference may also sometimes be made herein to particular applications. Such references are intended merely as exemplary and should not be taken as limiting the concepts described herein to the particular application. 
     Thus, although the description provided herein explains the inventive concepts in the context of particular circuits or a particular application or a particular frequency, those of ordinary skill in the art will appreciate that the concepts equally apply to other circuits or applications or frequencies. 
     Embodiments described herein rely at least in part on the recognition that by synchronizing the switched capacitor element  12 A and the regulating circuit  16 A, the intermediate voltage VX ripple effect on the output voltage VO and the voltage “glitch” can be minimized. 
       FIG. 3  illustrates a first generic controller  20  that synchronizes the switched capacitor element  12 A and the regulating circuit  16 A within the power converter  10 A shown in  FIG. 2 . The first generic controller  20  receives five input signals and provides three output signals. The input signals include the input voltage VIN, the output voltage VO, the intermediate voltage VX, a reference voltage VREF, and a clock voltage VCLK. The output signals include the regulation control voltage VR, the first phase voltage VA, and the second phase voltage VB. The clock voltage VCLK sets the period of the regulation control voltage VR and the reference voltage VREF sets the desired output voltage VO. 
     Synchronizing the switched capacitor element  12 A with the regulating circuit  16 A causes the intermediate voltage VX ripple to be in phase with the switching voltage VLX. In this scenario, feed-forward control is effective if the frequency of the regulating circuit  16 A is greater than or equal to the frequency of the switched capacitor element  12 A, thereby relieving the severe frequency constraint of separately controlled stages. 
     Additionally, the glitch capacitor CX, shown in  FIG. 2 , can be removed altogether if the dead-time interval DT of the switch capacitor element  12 A occurs when the regulating circuit  16 A is not drawing input current. Synchronizing the switched capacitor element  12 A and the regulating circuit  16 A ensures the proper timing between the dead-time interval DT and the interval during which the regulating circuit  16 A is not drawing input current. 
     One more benefit of synchronizing the switched capacitor element  12 A and the regulating circuit  16 A is the ability to open and close the power switches S 1 -S 8  in the switched capacitor element  12 A when zero-current is flowing through the power switches S 1 -S 8 . This technique is often referred to as zero-current switching. To achieve zero-current switching, the dead-time interval DT must occur when the regulating circuit  16 A is not drawing input current. 
       FIG. 4  illustrates a controller  20 A that is a preferred embodiment of the first generic controller  20 . The controller  20 A can be separated into a first control section and a second control section. The control circuitry for the regulating circuit  16 A is in the first control section and includes first, second, third, and fourth control blocks  30 ,  31 ,  32 ,  33 . In contrast, the control circuitry for the switched capacitor element  12 A is in the second control section and includes fifth, sixth, and seventh control blocks  34 ,  35 ,  36 . The “link” between the fourth control block  33  and the fifth control block  34  enables synchronization of the first and second control sections. 
     In an effort to promote clarity in explaining the operation of the controller  20 A,  FIG. 5  illustrates some relevant signals generated by the controller  20 A. The relevant signals include the clock voltage VCLK, a saw-tooth voltage VSAW, the regulation control voltage VR, the switching voltage VLX, a filter inductor current IL, the intermediate voltage VX, the first phase voltage VA, and the second phase voltage VB. Furthermore,  FIG. 6  illustrates a close-up of some of the waveforms in  FIG. 5 , where the regulation control voltage period TSW is the inverse of the regulation control voltage VR frequency. 
     Referring back to  FIG. 4 , the first control section within the controller  20 A uses a linear voltage-mode control scheme to control the regulating circuit  16 A. The controller  20 A compares the output voltage VO with the reference voltage VREF, thereby producing a residual voltage that is conditioned by the second control block  31 . A resulting error voltage VERR is then fed into the third control block  32  where it is compared with the saw-tooth voltage VSAW. Lastly, the output of the third control block  32  is further conditioned by the fourth control block  33 , resulting in the regulation control voltage VR. 
     The first control block  30  sets the frequency of the regulation control voltage VR by generating the saw-tooth voltage VSAW from the clock voltage VCLK. Additionally, the first control block  30  provides feed-forward control of the regulating circuit  16 A by adjusting the peak voltage of the saw-tooth voltage VSAW based upon the input voltage VIN. Alternatively, feed-forward control can be implemented by adjusting the error voltage VERR with respect to the input voltage VIN in the second control block  31 . 
     The second control section within the controller  20 A uses a hysteretic control scheme to control the switched capacitor element  12 A. The controller  20 A causes the first and second phase voltages VA, VB to cycle the switched capacitor element  12 A back and forth between the first network state and the second network state based upon a hysteresis band. 
     During operation, the sixth control block  35  continuously compares the intermediate voltage VX with a trigger voltage VXL. When the intermediate voltage VX drops below the trigger voltage VXL, the fifth control block  34  is triggered and then waits for a confirmation signal. Once the fourth control block  33  sends a signal informing the fifth control block  34  that it is acceptable to make a state change, the dead-time interval DT, shown in  FIG. 6 , is initiated. During the dead-time interval DT, the first and second phase voltages VA, VB are set low. Following the dead-time interval DT, either the first phase voltage VA is set high and the second phase voltage VB is left low or the first phase voltage VA is left low and the second phase voltage VB is set high, depending upon the initial state. After the state change, the fifth control block  34  is reset and the sequence repeats. 
     The controller  20 A thus forces the frequency of the switched capacitor element  12 A to be submultiples of the frequency of the regulating circuit  16 A. This constraint is illustrated in  FIG. 5 , where the frequencies of the first phase voltage VA and the second phase voltage VB are much lower than the frequency of the regulation control voltage VR. In some practices, the frequency of the second phase voltage VB is as little as a tenth that of the control voltage VR. 
     Since the switched capacitor element  12 A is loaded down by a non-capacitive regulating circuit  16 A, the voltage ripple on the intermediate voltage VX is a piecewise linear approximation of a saw-tooth waveform. As used herein, an intermediate peak-peak voltage ripple ΔVX is equal to the maximum intermediate voltage minus the minimum intermediate voltage under steady state conditions. Typically, the intermediate voltage VX comprises a high frequency component from the regulating circuit  16 A superimposed on the lower frequency saw-tooth waveform from the switched capacitor element  12 A. 
     Unfortunately, while the fifth control block  34  is waiting to change states, the intermediate voltage VX drops a delta voltage ΔVD below the trigger voltage VXL, as shown by the intermediate voltage VX curve in  FIG. 5 . Typically, the delta voltage ΔVD is small; especially if the frequency of the switched element  12 A is much lower than the frequency of the regulating circuit  16 A. The delta voltage ΔVD at most can be equal to one-half of the intermediate peak-peak voltage ripple ΔVX and this occurs when the frequency of the switched capacitor element  12 A is equal to the frequency of the regulating circuit  16 A. 
       FIG. 7  illustrates a DC model of the switched capacitor element  12 A coupled between the voltage source  14  and the regulating circuit  16 A. The DC model includes a transformer with a finite output resistance RO. Assuming the switched capacitor element  12 A delivers an intermediate current IX, the average of the intermediate voltage VX can be calculated using 
               VX   _     =       VIN   ⁢       N   ⁢           ⁢   1       N   ⁢           ⁢   2         -     IX   ×     RO   .               
The configuration of the switches and capacitors in the switched capacitor element  12 A sets a voltage transformation ratio N 1 :N 2 . Meanwhile, the output resistance RO of the switched capacitor element  12 A accounts for the energy loss in charging/discharging the pump capacitors.
 
     Based upon the waveforms in  FIG. 5 , the average of the intermediate voltage VX can be calculated using
 
   VX =VXL−ΔVD+ΔVX/ 2.
 
By equating the previous two equations, the intermediate peak-peak voltage ripple ΔVX can be expressed as
 
               Δ   ⁢           ⁢   VX     =       2   ⁡     [       VIN   ⁢       N   ⁢           ⁢   1       N   ⁢           ⁢   2         -     IX   ×   RO     -   VXL   +     Δ   ⁢           ⁢   VD       ]       .           
Consequently, the intermediate peak-peak voltage ripple ΔVX is function of operating parameters such as the intermediate current IX and the input voltage VIN.
 
     Additionally, due to the synchronization constraint, the intermediate peak-peak voltage ripple ΔVX is also a function of the delta voltage ΔVD. 
     Unfortunately, large variations in the intermediate peak-peak voltage ripple ΔVX can overstress the regulating circuit  16 A. To minimize variations of the intermediate peak-peak voltage ripple ΔVX, the trigger voltage VXL, shown in  FIG. 4 , can be adjusted on the fly. For example, the seventh control block  36  utilizes the input voltage VIN and the intermediate voltage VX to make a decision on the appropriate value of the trigger voltage VXL. Therefore, when the input voltage VIN rises, the trigger voltage VXL rises in step. 
     One key idea illustrated in  FIG. 6  is that the dead-time interval DT occurs during the off state of the high-side power switch SH in  FIG. 2 . To ensure this outcome, there is an upper bound on the duty cycle of the regulating circuit  16 A, where a maximum duty cycle DMAX is determined using 
             DMAX   =         TSW   -   DT     TSW     .           
As illustrated by the equation above, the dead-time interval DT sets the maximum duty cycle DMAX. It is often desirable to minimize the dead-time interval DT, thereby widening the duty cycle range of the regulating circuit  16 A.
 
     It is not uncommon to have a duty cycle limit, specifically if constant frequency operation of the regulating circuit  16 A is required for electromagnetic compatibility reasons. In these cases, the maximum duty cycle DMAX constraint is not overly burdensome because the feed-back control loop for the regulating circuit  16 A would otherwise have a duty cycle limit. 
       FIG. 8A  illustrates the period of the switched capacitor element  12 A and the intermediate peak-peak voltage ripple ΔVX as a function of the output current. As the output current decreases, the slope of the voltage ripple on the intermediate voltage VX decreases. This reduces the frequency of the first and second phase voltages VA, VB. Due to synchronization, the reduction in frequency occurs abruptly and only at specific output current values. The change in frequency takes place whenever the intermediate peak-peak voltage ripple ΔVX is equal to a maximum peak-peak voltage ripple ΔVMAX divided by two. Consequently, the intermediate peak-peak voltage ripple ΔVX follows a saw-tooth waveform with a fixed valley voltage. Furthermore, as the output current approaches zero, the intermediate peak-peak voltage ripple ΔVX approaches one-half of the maximum peak-peak voltage ripple ΔVMAX. 
     With a few modifications to the controller  20 A, it is also possible to get the intermediate peak-peak voltage ripple ΔVX to follow a saw-tooth waveform with a fixed peak voltage as illustrated in  FIG. 8B . In this scenario, as the output current approaches zero, the intermediate peak-peak voltage ripple ΔVX approaches the maximum peak-peak voltage ripple ΔVMAX. The main difference between the first approach in  FIG. 8A  and second approach in  FIG. 8B  is the distribution of frequencies and intermediate peak-peak voltage ripple ΔVX across the output current range. 
     The controller  20 A depicted in  FIG. 4  and described above is one of many possible implementations of the first generic controller  20  that can synchronize the power converter  10 A or any power converter that includes a switched capacitor element  12 A that precedes a regulating circuit  16 A. In the modular multi-stage power converter architecture, the switched capacitor element  12 A and the regulating circuit  16 A can be mixed and matched in a variety of different ways. For example,  FIG. 9  illustrates an alternative power converter  10 B, wherein a regulating circuit  16 A precedes a switched capacitor element  12 A. 
     In  FIG. 9 , a second generic controller  21  synchronizes the regulating circuit  16 A and the switched capacitor element  12 A. The input and output signals of the second generic controller  21  are the same as that of the first generic controller  20 . In the power converter  10 B, the regulating circuit  16 A may include various types of switch-mode power converters, such as a boost converter, a resonant converter, and a fly-back converter. Similarly, the switched capacitor element  12 A may include various types of switched capacitor converters, such as a series-parallel charge pump, a voltage doubler, and a cascade multiplier. Regardless of the selection of either the regulating circuit  16 A or the switched capacitor element  12 A, if the two stages are synchronized, the frequency of the switched capacitor element  12 A will change in discrete steps as the output current of the power converter  10 B is varied. 
     In addition to alternative modular multi-stage power converter architectures, it is also possible to synchronize multi-phase implementations.  FIG. 10  illustrates a three-phase power converter  10 C and a generic three phase-controller  22  that synchronizes the various stages. The three-phase power converter  10 C includes three regulating sub-elements: a first regulating circuit  16 A, a second regulating circuit  16 B, a third regulating circuit  16 C and three voltage transformation sub-elements: a first switched capacitor element  12 A, a second switched capacitor element  12 B, and a third switched capacitor element  12 C. The first, second, and third switched capacitor elements  12 A,  12 B,  12 C provide first, second, and third intermediate voltages VX 1 , VX 2 , VX 3 , respectively. 
     First, second, and third regulation control voltages VR 1 , VR 2 , VR 3  control the first, second, and third regulating circuits  16 A,  16 B,  16 C, respectively. Furthermore, first and second phase voltages VA 1 , VB 1  control the first switched capacitor element  12 A; third and fourth phase voltages VA 2 , VB 2  control the second switched capacitor element  12 B; and fifth and sixth phase voltages VA 3 , VB 3  control the third switched capacitor element  12 C. Additionally, a regulation control bus BVR includes the first, second, and third regulation control voltages VR 1 , VR 2 , VR 3 . A first phase bus BVA includes the first, third, and fifth phase voltages VA 1 , VA 2 , VA 3 . Lastly, a second phase bus BVB includes the second, fourth, and sixth phase voltages VB 1 , VB 2 , VB 3 . 
       FIG. 11  illustrates a three-phase controller  22 A that is a preferred embodiment of the generic three-phase controller  22 . The three-phase controller  22 A can be separated into a first control section and a second control section. The control circuitry for the first, second, and third regulating circuits  16 A,  16 B,  16 C is in the first control section and includes first, second, third, fourth, fifth, and sixth control blocks  30 ,  31 ,  32 A,  32 B,  32 C,  33 . In contrast, the control circuitry for the first, second, and third switched capacitor elements  12 A,  12 B,  12 C is in the second control section and includes seventh, eighth, ninth, tenth, and eleventh control blocks  34 ,  35 A,  35 B,  35 C,  36 . 
     The three-phase controller  22 A looks very similar to the controller  20 A in  FIG. 4 , but with additional input and output signals. In the three-phase controller  22 A, a linear voltage-mode control scheme is used to control the regulating circuits  16 A- 16 C and a hysteretic control scheme is used to control the switched capacitor elements  12 A- 12 C. Consequently, the operation of the first and second control sections in the three-phase controller  22 A is similar to that described in connection with  FIG. 4 . 
     In the first control section, the first control block  30  sets the frequency and phase of the first, second, and third regulation control voltages VR 1 , VR 2 , VR 3 . The first control block  30  generates first, second, and third saw-tooth voltages VSAW 1 , VSAW 2 , VSAW 3  that are compared to an error voltage VERR by the third, fourth, and fifth control blocks  32 A,  32 B,  32 C, respectively. The resulting three outputs are further conditioned by the sixth control block  33  that produces the regulation control bus BVR. 
     In the second control section, the first, second, and third intermediate voltages VX 1 , VX 2 , VX 3  are compared to a trigger voltage VXL produced by the eleventh control block  36 . The output of the eighth, ninth, tenth control blocks  35 A,  35 B,  35 C are further conditioned by the seventh control block  34  resulting in the first and second phase buses BVA, BVB. The ‘link’ between the sixth control block  33  and the seventh control block  34  enables synchronization of the first and second control sections. 
     In an effort to promote clarity,  FIG. 12A  illustrates some relevant signals generated by the three-phase controller  22 A. The first, second, and third regulation control voltages VR 1 , VR 2 , VR 3  are one hundred and twenty degrees out of phase with each other. Meanwhile, the phase voltages VA 1 , VA 2 , VA 3  are shifted in time with respect to each other the same amount as their corresponding regulation control voltages VR 1 , VR 2 , VR 3  are shifted in time with respect to each other. Furthermore, the second, fourth, and sixth phase voltages VB 1 , VB 2 , VB 3  are one hundred and eighty degrees out of phase with the first, third, and fifth phase voltages VA 1 , VA 2 , VA 3 , respectively. 
     For example, if the frequency of the first, second, and third regulating circuits  16 A,  16 B,  16 C is one megahertz, then the rising and/or falling edges of the first, second, and third regulation control voltages VR 1 , VR 2 , VR 3  are separated by one-third of a microsecond. Consequently, the rising and/or falling edges of the first, third, and fifth phase voltages VA 1 , VA 2 , VA 3  are separated by one-third of a microsecond and the rising and/or falling edges of the second, fourth, and sixth phase voltages VB 1 , VB 2 , VB 3  are separated by one-third of a microsecond. 
     With a few modifications to the three-phase controller  22 A, it is possible to further shift the first, third, and fifth phase voltages VA 1 , VA 2 , VA 3  by one or more whole periods of the regulating circuits  16 A- 16 C as illustrated in  FIG. 12B . 
     For example, if the frequency of each of the regulating circuits  16 A- 16 C is one megahertz, then the period of each of the regulating circuits  16 A- 16 C is one microsecond. Assuming a shift of one period, then the rising and/or falling edges of the first, third, and fifth phase voltages VA 1 , VA 2 , VA 3  are separated by one and one-third of a microsecond and the rising and/or falling edges of the second, fourth, and sixth phase voltages VB 1 , VB 2 , VB 3  are separated by one and one-third of a microsecond. Among other benefits, the more uniform spacing of the first intermediate voltage VX 1  ripple, the second intermediate voltage VX 2  ripple, and the third intermediate voltage VX 3  ripple reduces their effect on the output voltage VO. 
     As in the single-phase case, the glitch capacitor CX can be removed altogether if the dead-time interval DT of each of the switched capacitor elements  12 A,  12 B,  12 C occurs when their corresponding regulating circuits  16 A,  16 B,  16 C are neither sinking nor sourcing current through an inductive element. For example, in a buck converter, the filter inductor is sinking current from the input only a portion of the time, whereas, in a boost converter, the filter inductor is sourcing current to the output only a portion of the time. These power converters have a discontinuous current interval during which current is either sunk or sourced. Therefore, the glitch capacitor CX is unnecessary if the dead-time interval DT of each of the switched capacitor elements  12 A,  12 B,  12 C occurs during the discontinuous input current interval. 
     Both the controller  20 A in  FIG. 4  and the three-phase controller  22 A in  FIG. 11  utilize linear voltage-mode control. However, other control techniques such as non-linear voltage-mode control, peak current-mode control, and average current-mode control are applicable as well. 
     The control circuitry described herein synchronizes the switched capacitor elements  12 A with the regulating circuits  16 A in the modular multi-stage power converter architecture. Among other advantages, the control circuitry described herein provides a way to minimize the effect of the intermediate voltage VX ripple on the output voltage VO and minimize the production of a voltage ‘glitch’ during the dead-time internal DT of the switched capacitor element  12 A. 
     Various features, aspects, and embodiments of control techniques for power converters that utilize capacitors to transfer energy have been described herein. The features, aspects, and numerous embodiments described are susceptible to combination with one another as well as to variation and modification, as will be understood by those having ordinary skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. Additionally, the terms and expression which have been employed herein are used as terms to description and not of limitation, and there is no intention, in the use of such terms and expression, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.