Abstract:
The present invention discloses a lead frame fabrication method, wherein a metallic plate is locally fabricated in double sides to form accurately aligned and closely spaced circuits; the metallic plate is also locally fabricated in single side to form patterned trenches; a filling material is filled into the trenches to provide extra mechanical support and separate the metallic plate into a plurality of conductive regions or regions with special electric properties. The present invention can overcome the conventional problems in lead frame fabrication and has the advantages of a superior heat-dissipating ability, multi-leads and diversified applications.

Description:
[0001]    This application is a divisional application of U.S. patent application Ser. No. 11/462,377, filed on AUG. 4, 2006. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a lead frame fabrication technology, particularly to a lead frame fabrication method, wherein the lead frame has extra mechanical support, and the lead frame also has a plurality of conductive regions or regions with special electric properties. 
         [0004]    2. Description of the Related Art 
         [0005]    The packaging of electronic elements is to transfer signals and power, provide a heat-dissipating path, and provide structural protection and support. In the back-end process of semiconductor fabrication, the lead frame and IC substrate are used to bridge the IC chip and external circuits and transmit the electronic signals between the chip and external systems. 
         [0006]    With the promotion of chip function, the required I/O leads also greatly increase. However, the leads can only extend from four sides of a lead frame, and such a method cannot always provide sufficient leads. Thus, an alternative packaging method was proposed, wherein a PCB (Printed Circuit Board) is used as the chip carrier, and the array of solder balls is arranged on the bottom surface of the chip carrier and used to replace the leads extending from four sides of a lead frame. Such a packaging method is advantaged in that more leads can be arranged in the same area; thus, the dimension of a packaging structure can be reduced. However, with the ever-increasing power consumption, heat dissipation becomes a problem hard to overcome. 
         [0007]    With the simplified circuit design benefiting from the SOC (System On Chip) trend, some CSP (Chip Scale Package) packages turn to utilize a lead frame to meet the requirement of heat dissipation. Such a tendency breeds the requirement for a packaging structure with the circuit complexity between a CSP package and a lead frame, such as the QFN (Quad Flat No lead) package. However, it is not so easy to utilize a traditional lead frame to implement the circuits asymmetrical in the upper and lower surfaces. In such a case, the traditional lead frame will meet the following problems: 1. difficulty in fabricating half-etching circuits, 2. circuit distortion during molding, and 3. overflow resin pollution in leads during molding. Accordingly, the present invention proposes a new lead frame and a fabrication method thereof to overcome the abovementioned problems. 
       SUMMARY OF THE INVENTION 
       [0008]    The primary objective of the present invention is to provide a fabrication method for a lead frame to effectively solve the conventional fabrication and packaging problems in a lead frame, wherein a double-side etching technology, a mechanical depth control technology or a casting technology is used to fabricate circuits with finer spacings and obtain a precise alignment; a localized single-side etching procedure is used to fabricate trenches, and the trenches/through-trenches are filled with a filling material to obtain a structural support; next, circuits are formed in the other sides of the trenches. 
         [0009]    Another objective of the present invention is to provide a fabrication method for a lead frame, wherein the circuits on a lead frame can be diversified with a filling material or a support structure, and the lead frame can thus meet the requirements of various semiconductor packages. 
         [0010]    Further another objective of the present invention is to provide a fabrication method for a lead frame, wherein a column-type conductor interconnecting the upper and lower surfaces can be directly fabricated, and a filling material is filled into the trenches; hole-drilling and through-hole electroplating procedures used in PCB are unnecessary in the method of the present invention; thus, the wire routing procedure can be saved, and the dimension of the chip carrier can be reduced; in the method of the present invention, more available area can be obtained in the same packaging dimension, and the lead installation positions are not limited to the perimeter of the lead frame; thus, the lead frame fabricated according to the present invention is equal to an LGA (Land Grid Array) lead frame. 
         [0011]    The present invention proposes an embodiment of a fabrication method for a lead frame, wherein a metallic plate is provided firstly; next, a plurality of through-trenches and lower/upper trenches are fabricated with an etching procedure, a mechanical depth control procedure or a casting procedure; next, a filling material is selectively filled into the through-trenches and the lower/upper trenches; next, a plurality of conductive layers are formed on the upper and lower surfaces of the metallic plate; and then, a plurality of upper/lower trenches are formed on the surface of the metallic plate. 
         [0012]    The present invention further proposes an embodiment of a fabrication method for a lead frame, wherein a metallic plate is provided firstly; next, a plurality of through-trenches and lower/upper trenches are fabricated with an etching procedure, a mechanical depth control procedure or a casting procedure, and a filling material is selectively filled into the through-trenches and the lower/upper trenches; next, a plurality of through-trenches and upper/lower trenches are formed on the surface of the metallic plate with an etching procedure, a mechanical depth control procedure or a casting procedure, and a filling material is selectively filled into the through-trenches and the upper/lower trenches; and then, a plurality of conductive layers are formed on the upper and lower surfaces of the metallic plate. 
         [0013]    To enable the structural characteristics and accomplishments of the present invention to be easily understood, the preferred embodiments of the present invention are to be described in detail in cooperation with the attached drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1(   a ) to  FIG. 1(   j   2 ) are sectional views schematically showing the steps of the fabrication method according to one embodiment of the present invention; 
           [0015]      FIG. 2(   a ) to  FIG. 2(   c   2 ) are sectional views schematically showing the steps of the fabrication method according to another embodiment of the present invention; 
           [0016]      FIG. 3  is a diagram schematically showing the pattern of the patterned resist layer on the upper surface of a metallic plate; 
           [0017]      FIG. 4  is a diagram schematically showing the pattern of the patterned resist layer on the lower surface of a metallic plate; 
           [0018]      FIG. 5(   a ) to  FIG. 5(   f   4 ) are sectional views schematically showing the steps of the fabrication method according to further another embodiment of the present invention; 
           [0019]      FIG. 6  is a diagram schematically showing the step of forming an accommodation basin is integrated with the step of fabricating upper trenches with an etching method; and 
           [0020]      FIG. 7(   a ) and  FIG. 7(   b ) are diagrams schematically showing the embodiment that a plurality of metallic bumps are formed and used as the interface to connect with external systems. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    The present invention pertains to a lead frame and a fabrication method thereof, wherein a metallic-plate lead frame, which is to be used as a semiconductor carrier, is fabricated via a selective etching technology/a depth control fabrication technology/a casting technology, a double-side etching technology and a material-filling technology; the metallic-plate lead frame has a superior heat-dissipating effect and can apply to a multi-lead semiconductor packaging; thereby, the present invention can overcome the conventional problems in lead frame fabrication and packaging. 
         [0022]    It is to be clarified beforehand: the present invention is characterized in utilizing through-trenches, upper trenches, lower trenches and a filling material to form a metallic lead frame; however, the present invention is not limited by the through-trench, the upper trench and the lower trench exemplified in the specification, and any equivalent modification and variation with respect to the through-trench, the upper trench or the lower trench is to be also included within the scope of the present invention. 
         [0023]    Below, an embodiment, wherein the through-trenches and the lower trenches are firstly formed, is used to exemplify the fabrication method of the present invention. 
         [0024]    Firstly, as shown in  FIG. 1(   a ), a patterned resist layer  12  and a patterned resist layer  14  is respectively formed on the upper surface and the lower surface of a metallic plate  10 . The patterns of the patterned resist layer  12  and the patterned resist layer  14  are respectively shown in  FIG. 3  and  FIG. 4 . 
         [0025]    Next, as shown in  FIG. 1(   b ), the metallic plate  10  is etched to form a through-trench  16  and a lower trench  18  with the patterned resist layer  12  and the patterned resist layer  14  being the masks. The wet etching method is preferred to etch the metallic plate  10 . The wet etching method is more likely to obtain a straighter trench wall, which benefits the formation of a finer and denser circuit and a better alignment. Then, the patterned resist layer  12  and the patterned resist layer  14  are removed. The trench and the through-trench may also be fabricated in cooperation with a depth control technology or a casting technology. 
         [0026]    Next, as shown in  FIG. 1(   c ), a material-filling procedure is undertaken, and a filling material  20 /supporters are filled/pressed into the through-trench  16  and the lower trench  18 . Next, the filling material  20 /supporters are planarized with a polishing procedure lest the filling material  20 /supporters cover the areas where circuits or conductive layers are to be formed. Thereby, an elaborate circuit and a lower surface circuit are obtained. The filling material  20  may be a resin, a silver paste, a copper paste or a carbon paste, which is insulating or can change electric properties. 
         [0027]    Next, as shown in  FIG. 1(   d ), a patterned resist layer  22  and a patterned resist layer  24  are respectively formed on the upper surface and the lower surface of the metallic plate  10 . Next, as shown in  FIG. 1(   e ), the metallic plate  10  is etched to form a plurality of trenches  26  with the patterned resist layers  22  and  24  being the masks, and then, the patterned resist layers  22  and  24  are removed. The etching procedure may be undertaken with a selective etching technology or a depth control technology. 
         [0028]    Next, a filling material  28 /supporters are filled/pressed into the trenches  26 , and then, the filling material  28 /supporters are planarized with a polishing procedure to form the upper surface circuits shown in  FIG. 1(   f   1 ) or  FIG. 1(   f   2 ). 
         [0029]    Next, as shown in  FIG. 1(   g   1 ) or  FIG. 1(   g   2 ), patterned anti-plating layers  30  and  32  or solder masks are respectively formed on the metallic plate  10 , and the patterned anti-plating layers  30  and  32  or solder masks are used to define a plurality of externally-connected conductive layers, which are to be connected to external systems. Next, as shown in  FIG. 1(   h   1 ) or  FIG. 1(   h   2 ), a plurality of externally-connected conductive layers  34 , which are to enhance the conductivity of conductive regions, are formed on the upper and lower surfaces of the metallic plate  10  with the patterned anti-plating layers  30  and  32  or solder masks being masks, and then, the patterned anti-plating layers  30  and  32  are removed. If the solder masks are used, the solder mask will not be removed. The conductive layer may be fabricated via various metallic surface treatment technologies, such as the electroless tin deposition technology, the tin plating technology, the electroless silver deposition technology, the silver electroplating technology, the nickel-gold plating technology, the electroless nickel-palladium-gold deposition technology, and the electroless nickel immersion gold technology. 
         [0030]    After the lead frame is completed, the process proceeds to a chip-attachment procedure. In this embodiment, as shown in  FIG. 1(   i ) and  FIG. 1(   i   2 ), the central region of the metallic plate  10  is predetermined to be the chip-attachment area, and wires  59  are used to interconnect a chip  48  and the externally-connected conductive layers  34 , and then, an encapsulant  52 , which is usually made of an epoxy resin, is applied to the upper surface of the metallic plate  10  to cover the chip  48  and the wires  52  and provide a mechanical protection for them lest they be damaged by external force. Further, as shown in  FIG. 1(   j   1 ) and  FIG. 1(   j   2 ), an accommodation basin  54  may be formed in the central region of the metallic plate  10 , and the chip  48  is arranged inside the accommodation basin  54 ; thereby, the overall thickness of the packaging structure can be reduced. 
         [0031]    In contrast to the abovementioned procedure of filling/pressing the filling material/supporters into all the through-trench  16  and the lower trenches  18 , the filling material/supporters may be selectively filled/pressed according to the conduction requirements of different areas on the metallic plate  10 . As shown in  FIG. 2(   a ), none supporter/filling material  20  exists in the through-trench  16  and a portion of the lower trenches  18 . Next, similarly to the abovementioned procedures, a plurality of upper trenches  26  is formed on the metallic plate  10 , and the filling material  28 /supporters are selectively filled/pressed into the upper trenches  26 , and then, the filling material  28 /supporters are planarized; thus, a plurality of upper surface circuits is obtained, as shown in  FIG. 2(   b ). Next, a plurality of the externally-connected conductive layers  34  is formed on the upper and lower surfaces of the metallic plate  10 , and then, a chip-attachment procedure and an encapsulation procedure are sequentially undertaken to form the structure shown in  FIG. 2(   c   1 ) or  FIG. 2(   c   2 ). 
         [0032]    In addition to the abovementioned embodiment, the present invention also proposes an embodiment, wherein a through-trench or lower/upper trenches are firstly formed; next, a filling material is filled into the through-trench or the trenches and then planarized; next, a plurality of conductive layers is formed on the specified areas of the upper and lower surface of the metallic plate; and then, upper/lower trenches and circuits are sequentially formed. 
         [0033]    Herein, an embodiment is to be described, wherein a through-trench or lower trenches are firstly formed, and then, the material-filling procedure, the conductive layer forming procedure and the upper trench forming procedure are sequentially undertaken. Firstly, according to the abovementioned procedures shown in from  FIG. 1(   a ) to  FIG. 1(   c ), the through-trench  16  and the lower trenches  18  having the filling material thereinside shown in  FIG. 5(   a ) are fabricated. 
         [0034]    Next, as shown in  FIG. 5(   b ), patterned anti-plating layers  36  and  38  are respectively formed on the upper and lower surfaces of the metallic plate  10  and used to define a plurality of externally-connected conductive layers. Next, as shown in  FIG. 5(   c ), a plurality of externally-connected conductive layers  34 , which are to enhance the conductivity of conductive regions, is formed on the upper and lower surfaces of the metallic plate  10  with the anti-plating layers  36  and  38  being masks, and then, the patterned anti-plating layers  36  and  38  are removed. The externally-connected conductive layer  34  may be fabricated via various metallic surface treatment technologies, such as the electroless tin deposition technology, the tin plating technology, the electroless silver deposition technology, the silver electroplating technology, the nickel-gold plating technology, the electroless nickel-palladium-gold deposition technology, and the electroless nickel immersion gold technology. 
         [0035]    Next, as shown in  FIG. 5(   d ), patterned resist layers  42  and  44  are respectively formed on the metallic plate  10  and used to define upper trenches, and the metallic plate  10  is etched to form the upper trenches  26  with the patterned resist layers  42  and  44  and the externally-connected conductive layers  34  being masks; then, the patterned resist layers  42  and  44  are removed. Next, as shown in  FIG. 5(   e   1 ) and  FIG. 5(   e   2 ), a filling material  28 /supporters are selectively filled/pressed into the upper trenches  26  to obtain a lead frame, which integrates the advantages of the conventional PCB and lead frame. 
         [0036]    Next, a chip  48  is attached to the metallic plate  10 , and wires  50  are used to interconnect the chip  48  and the externally-connected conductive layers  34 , and then, an encapsulant  52  is applied to cover the chip  48 , the wires  50  and the externally-connected conductive layers  34 ; thereby, a structure shown in  FIG. 5(   f   1 ) or  FIG. 5(   f   2 ) is obtained. Otherwise, an accommodation basin  54  for the chip  48  may be firstly formed, and then, the chip-attachment, wire connecting and encapsulating procedures are sequentially undertaken to form a structure shown in  FIG. 5(   f   3 ) or  FIG. 5(   f   4 ). 
         [0037]    Further, the fabrication procedure of the accommodation basin  54  may be combined with the fabrication procedure of the upper trenches  26 , wherein the patterned resist layers  42  and  44  are respectively formed on the upper and lower surfaces of the metallic plates  10  and used to define the upper trenches  26  and the accommodation basin  54 , and then, with the patterned resist layers  42  and  44  and the externally-connected conductive layers  34  being masks, the metallic plates  10  is etched to form the upper trenches  26  and the accommodation basin  54  shown in  FIG. 6 . Next, the selective material-filling procedure and the chip attachment procedure are sequentially undertaken. The succeeding procedures are the same as those described above and will not be described repeatedly here. 
         [0038]    Refer to  FIG. 7(   a ) and  FIG. 7(   b ) for another embodiment of the present invention. In this embodiment, none filling is filled into the selected lower trenches, but a plurality of metallic bumps  56  are formed inside those selected lower trenches. The metallic bumps  56  replace the conventional solder bumps and function as the interfaces to connect with external systems; thereby, the problem of joining different metals is less likely to occur, and the reliability of the entire element is promoted. Further, the solder-ball fabrication steps can be decreased, and the cost and defective fraction of the packaging process is thus reduced. 
         [0039]    In summary, the present invention proposes a lead frame and a fabrication method thereof, wherein a double-side etching technology is used to form denser circuits, and a multi-stage etching technology, a depth control technology and a material-filling technology are used to overcome the conventional problems in the fabrication and packaging of lead frames. 
         [0040]    The present invention has the following advantages:
   1. The circuit of the lead frame of the present invention can be diversified via utilizing the filling material/supporters, and the lead frame of the present invention can extensively apply to various semiconductor packages.   2. A plurality of metallic bumps may be fabricated beforehand in the lead frame of the present invention, and the reliability of the packaged element is thus promoted, and the cost and defective fraction of semiconductor packaging is thus reduced.   3. The spaces between leads have been filled with the filling material in the present invention; thus, the overflow resin on SMT (Surface Mount Technology) pads will no more occur in the molding procedure, and the steps and cost of the packaging process can be reduced, and the yield is promoted.   4. The overall thickness of the semiconductor package can be reduced via the accommodation basin formed in the lead frame of the present invention.   
 
         [0045]    Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that other modifications and variation can be made without departing the spirit and scope of the invention as hereafter claimed.