Abstract:
An integrated circuit amplifier comprises: a first planar substrate having an upper surface and a lower surface; a second planar substrate having an upper surface and a lower surface, the lower surface of the second planar substrate physically affixed to the upper surface of the first planar substrate; at least one transistor pair comprising a first and second transistor, formed in the upper surface of the second planar substrate; and a conductor electrically coupling a drain electrode of the first transistor to a source electrode of the second transistor. The first substrate material may have a higher thermal conductivity than the second substrate material. The first material may be Silicon Carbide and may have a thickness of about 10 mils. The second material may be Gallium Arsenide and may have a thickness of about 1 to 2 mils.

Description:
CROSS-REFERENCE TO PRIOR APPLICATIONS 
     This application is a continuation-in-part of prior U.S. patent application Ser. No. 13/082,800 filed Apr. 8, 2011 and claims the benefit thereof pursuant to 35 U.S.C. §120. 
    
    
     FIELD OF THE INVENTION 
     This application relates to semi-conductor devices. More particularly, this application relates to temperature management in semi-conductor devices. 
     BACKGROUND OF THE INVENTION 
     U.S. Pat. No. 7,391,067, issued Jun. 24, 2008 in the name of Kumar, describes temperature problems associated with the use of gallium arsenide (GaAs) substrates for fabrication of planar transistors for radio frequency (RF) use. As noted by Kumar, the term RF encompasses more than the traditional radio frequencies. 
     High transmit power is desired in transmit-receive (TR or T/R) modules associated with radar antennas or sonar projectors. Having the highest possible power in each module tends to reduce the number of modules associated with each array, which is a cost advantage. The high power, long duty cycles, and high voltage experienced by GaAs power amplifiers, especially in view of their relatively poor thermal conductivity, tends to promote thermal runaway or thermal avalanche, which can destroy the device. These conditions are exacerbated by the close packing of the modules required by the dimensions of antenna or projector array elements. 
     Improved or alternative integrated circuits are desired. 
     SUMMARY 
     In an embodiment, an integrated circuit amplifier may comprise: a first planar substrate having an upper surface and a lower surface; a second planar substrate having an upper surface and a lower surface, the lower surface of the second planar substrate physically affixed to the upper surface of the first planar substrate; at least one transistor pair comprising a first and second transistor, formed in the upper surface of the second planar substrate; and a conductor electrically coupling a drain electrode of the first transistor to a source electrode of the second transistor. The first substrate may be comprised of a first material and the second substrate may be comprised of a second material, and the first material may have a higher thermal conductivity than the second material. 
     The integrated circuit amplifier may further comprise a first matching circuit formed on the upper surface of the first planar substrate, wherein the first matching circuit is electrically coupled to a gate electrode of the first transistor. In an embodiment, the first matching circuit is electrically coupled to the gate electrode of the first transistor by a bond wire. The integrated circuit amplifier of claim  2  may further comprise a second matching circuit formed on the upper surface of the first planar substrate, wherein the second matching circuit is electrically coupled to a drain electrode of the second transistor. In an embodiment, the second matching circuit may be electrically coupled to the drain electrode of the second transistor by a bond wire. In an embodiment, the integrated circuit amplifier may further comprise a second matching circuit formed on the upper surface of the first planar substrate, wherein the second matching circuit is electrically coupled to a drain electrode of the second transistor. 
     In an embodiment of the integrated circuit amplifier, the first material is Silicon Carbide. The first planar substrate, which may be Silicon Carbide, may have a thickness of about 10 mils. In an embodiment of the integrated circuit amplifier, the second material is Gallium Arsenide. The second planar substrate, which may be Gallium Arsenide, may have a thickness of about 1 to 2 mils. 
     A microwave amplifier semiconductor structure may comprise: a first substrate having an upper surface and a lower surface, wherein the first substrate is configured to conduct heat from an active surface of the first substrate; a first transistor and a second transistor defined on the upper surface of the first substrate; a second substrate having an upper surface and a lower surface, the upper surface of the second substrate having a first region upon which the lower surface of the first substrate is affixed and in thermal communication with the second substrate; at least one matching circuit formed on a second region of the second substrate; and a bond wire electrically connecting the at least one matching circuit to one of the first transistor or the second transistor. In an embodiment, the microwave amplifier may further comprise a conductor electrically connecting a gate electrode of the first transistor and a source electrode of the second transistor. In an embodiment, the at least one matching circuit may comprise a first matching circuit electrically connected to a gate electrode of the first transistor. In an embodiment, the at least one matching circuit may comprise a second matching circuit electrically connected to a drain electrode of the second transistor. 
     In an embodiment of the microwave amplifier, the first substrate may comprise Gallium Arsenide. The Gallium Arsenide substrate may have a thickness of about 1 mil to 2 mils. In an embodiment, the second substrate comprises Silicon Carbide. The Silicon Carbide substrate may have a thickness of about 10 mils. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a simplified perspective or isometric view of an integrated-circuit amplifier according to an aspect of the disclosure, exploded to show relationship of parts; 
         FIG. 1B  is a simplified cross-sectional view of the arrangement of  FIG. 1A ; and 
         FIG. 1C  is a simplified schematic diagram of a two-transistor cascode circuit which may be used in the arrangements of  FIG. 1A  or  1 B. 
     
    
    
     DETAILED DESCRIPTION 
     In  FIG. 1A , an amplifier  10  includes a silicon carbide (SiC) substrate  12  defining an upper surface  12   us  and a lower surface  12   ls . In one embodiment, SiC substrate  12  has a thickness of 0.010 inch. The upper surface  12   us  of substrate  12  also defines a region  12   a , to which a lower surface  14   ls  of a GaAs substrate  14  may be affixed. The thickness of the GaAs substrate  14  in one embodiment is 0.003 inch. 
     GaAs substrate  14  is processed or “doped” in known fashion to define an electrical circuit  15  including plural planar transistors on its active upper surface  14   us . As illustrated in  FIG. 1A , transistors, are illustrated as  16  and  18 . Those skilled in the art know that the transistors are the result of doping of the GaAs substrate  14  with dopants. According to an aspect of the disclosure, an electrical conductor  20  interconnects transistors  16  and  18  in a cascode arrangement. The cascode arrangement is advantageous because, by comparison with a grounded-source amplifier arrangement, heat generation is distributed between two transistor elements rather than being concentrated in only one element. This, in turn ameliorates the temperature rise of the transistors of the amplifier in a situation in which the same thickness and material of the substrates is involved. 
       FIG. 1A  illustrates a first electrically conductive bond wire  36  extending from transistor  16  via bond pad  37  and conductor  72  to a bond pad  38  on a portion  30  of the upper surface  12   us  of substrate  12 . Bond wire  36  electrically connects transistor  16  with a matching circuit illustrated as  50 , occupying region  30 . Details of matching circuit  50  are not illustrated, but are known in the art, and require no additional explanation. A further bond wire  40  extends from a ground or neutral portion of substrate  14  to a bond pad  42  on matching circuit portion  30 . Bond wires between ground or neutral portions of a substrate and corresponding portions of adjacent substrates for improved matching are known. A further region  32  on the upper surface  12   us  of substrate  12  is provided for a second matching circuit. The provision of two matching circuits makes it possible to impedance match both the input and output ports of each amplifier of substrate  14 . For this purpose, a second matching circuit is illustrated as  52 , and bond pads  68  and  70  are provided for connection to bond wires (not illustrated in  FIG. 1A ) connecting to transistor  18 . Whether the bond wires connect to bonding pads on the GaAs substrate or directly to metallizations or electrodes of transistors  16  and  18 , the electrical connections are established between the matching circuits and the transistors. The GaAs substrate may be affixed to the SiC substrate with high thermal conductive epoxy or with a eutectic attachment. 
       FIG. 1B  is a simplified cross-sectional view of the arrangement of  FIG. 1A . Elements of  FIG. 1A  corresponding to those of  FIG. 1B  are designated by like reference numerals. Bond wires extend from bond or bonding pads on the silicon carbide (SiC) substrate  12  to bonding pads on the gallium arsenide (GaAs) substrate  14 . As shown in  FIG. 1A , the SiC substrate  12  is a planar substrate. The GaAs substrate  14  is supported on SiC substrate  12  along the region identified as  12   a  in  FIG. 1A . More particularly, bond wire  36  is illustrated as extending from a bonding pad  38  on the SiC substrate  12  to a bonding pad  37 , and bond wire  76  is illustrated as extending from a bonding pad  68  on substrate  12  to a bonding pad  78  on substrate  14 . Connections from the bonding pads of substrate  14  to the electrodes of the transistors defined on substrate  14  may be by conductors, such as  72 , defined near or on the surface of substrate  14 , possibly with some additional bond wires. Bonding pad  37  may be considered to be the “gate” pad of transistor  16 , as it is connected thereto by conductors such as  72 . 
       FIG. 1C  is a simplified schematic diagram of amplifier  15  of  FIGS. 1A and 1B  optimized for radio-frequency (RF) amplification. In the past, the term “radio frequencies” was interpreted to mean a limited range of frequencies, such as, for example, the range extending from about 20 KHz to 2 MHz. Those skilled in the art know that “radio” frequencies as now understood extends over the entire frequency spectrum, including those frequencies in the “microwave” and “millimeter-wave” regions, and up to light-wave frequencies. Many of these frequencies are very important for commercial purposes, as they include the frequencies at which radar systems, global positioning systems, satellite cellular communications and ordinary terrestrial cell phone systems operate. 
     In  FIG. 1C , elements corresponding to those of  FIGS. 1A and 1B  are designated by like reference alpha-numerics. As illustrated in  FIG. 1C , amplifier  15  includes a field-effect transistor (FET)  16  which includes source  16   s , drain  16   d , and gate  16   g , and also includes a further FET  18  including source  18   s , drain  18   d , and gate  18   g . FET  16  has its source  16   s  connected to local ground or neutral to thereby establish a common-source configuration. The gate  18   g  of transistor  18  is connected by a low-value resistor  79  to a source of bias having low impedance to ground, as suggested by a capacitor  80 . The drain  18   d  of transistor  18  is connected by surface conductors  72 , bonding pad  78  and bond wire  76  to bonding pad  68  of matching circuit  52 , and matching circuit  52  also has common ground or neutral with amplifier  15  by virtue of a further bonding pad  70  and bond conductor or wire  77 . The gate  16   g  of transistor  16  is connected by way of a resistor  82  to a source of gate bias, and by way of a resistor  84  and bond wire  36  to bonding pad  38  of matching circuit  50 . A connection by way of a bond wire  20  between the drain  16   d  of transistor  16  and the source  18   s  of transistor  18  defines a cascode amplifier in which the input signal is applied to gate  16   g  and the amplified output signal is taken from drain  18   d . It should be noted that bias must be applied to the drain  18   d , and it may be applied to a bias input port  52   b  of matching circuit  52  for coupling to the drain  18   d  by way of a path having relatively high radio-frequency (RF) impedance, as may be provided by a coil or inductor (not illustrated). Thus, amplifier  15  of  FIG. 1C  receives RF input signal from a source (not illustrated) by way of input matching circuit  50 , amplifies the RF signal, and applies the amplified signal through output matching filter  52  to a utilization apparatus, not illustrated. An advantage of the cascode configuration is that the applied bias voltage is divided between the two transistors, with the result that only a fraction of the applied bias is applied to each transistor. At a given current, reduction of the applied bias voltage by half reduces the dissipation in each transistor by half. Put another way, the power dissipation which would normally occur in a common-source amplifier is split in a cascode between the two transistors. This ameliorates the temperature problems associated with the use of GaAs substrates. 
     In an embodiment, the GaAs substrate may be thinned. The thinning of the GaAs substrate reduces the thermal resistance between the transistors and the heat transfer surface of the GaAs substrate. The mounting of the thinned GaAs substrate on SiC makes the transistor arrangement able to withstand handling during fabrication. The cascade structure reduces heat concentration by distributing the heat load among two transistors. The cascode structure allows the amplifier to operate at twice the traditional voltage, thereby allowing four times the RF power. The mounting of the matching networks on the SiC portion of the structure reduces ohmic losses by about 20% by comparison with GaAs, which translates to about a 5% increase in efficiency. 
     An amplifier ( 10 ) according to an aspect of the disclosure comprises a SiC substrate ( 12 ), which may be planar. The amplifier ( 10 ) further comprises a planar GaAs structure ( 14 ), one side ( 14   us ) of which defines a transistor amplifier circuit ( 15 ), and the other side of which ( 14   ls ) is physically and thermally mounted adjacent to, or on a side ( 12   us ,  12   a ) of, the SiC substrate ( 12 ). A matching circuit, which may be an impedance matching circuit ( 30 ), is supported by the side ( 12   us ,  12   a ) of the SiC substrate ( 12 ) and is electrically coupled ( 50 ) to the transistor amplifier circuit ( 15 ). In a preferred embodiment, the amplifier circuit ( 15 ) includes first ( 16 ) and second ( 18 ) transistors in a cascode configuration which may include an electrical coupling ( 20 ) between the drain ( 16   d ) of the first transistor ( 16 ) and the source ( 18   s ) of the second transistor ( 18 ). The amplifier ( 15 ) may include an electrical connection ( 38 ,  36 ,  37 ,  72 ) between the matching circuit ( 30 ) and one of a gate ( 16   g ) of the first transistor ( 16 ) and a drain ( 18   d ) of the second transistor ( 18 ). In a desirable embodiment, the thickness of the planar GaAs structure is less than 0.003 inch and the SiC substrate has a thickness no greater than 0.010 inch. In one embodiment, the GaAs substrate may be affixed to the first portion ( 12   a ) of the surface ( 12   us ) via an adhesive layer ( 13 ), as understood in the art. The layout of the source regions on the side of the planar GaAs structure ( 14 ) may be zig-zag. 
     An integrated-circuit amplifier according to another aspect of the disclosure comprises a generally planar SiC substrate ( 12 ) defining a surface ( 12   us ), and a planar GaAs substrate ( 14 ) defining integrated first ( 16 ) and second ( 18 ) transistors, each including source, gate and drain electrodes, and also defining integrated electrical interconnection ( 20 ) extending between the drain ( 16   d ) of the first transistor ( 16 ) and the source ( 18   s ) of the second transistor ( 18 ). The GaAs substrate ( 14 ) is mounted on a first portion ( 12   a ) of the surface ( 12   us ) of the SiC substrate ( 12 ). In one embodiment, the GaAs substrate may be affixed to the first portion ( 12   a ) of the surface ( 12   us ) via an adhesive layer ( 13 ), as understood in the art. An integrated matching circuit ( 50 ) is defined on a second portion ( 30 ) of the SiC substrate ( 12 ). An electrical interconnection ( 36 ,  76 ) extends between the integrated matching circuit ( 50 ) and one of the gate ( 16   g ) of the first transistor ( 16 ) and the drain ( 18   d ) of the second transistor ( 18 ). In a preferred embodiment of this aspect, a second integrated matching circuit ( 52 ) is defined on a third portion ( 32 ) of the SiC substrate ( 12 ). An electrical interconnection ( 76 ) is provided between the second integrated matching circuit ( 52 ) and the other one of the gate ( 16   g ) of the first transistor ( 16 ) and the drain ( 18   d ) of the second transistor ( 18 ). In one version, the GaAs substrate ( 14 ) has a thickness no greater than 0.004 inch, and the SiC substrate ( 12 ) has a thickness no greater than 0.010 inch. In a particularly advantageous embodiment, the source regions of the first ( 16 ) and second ( 18 ) transistors are laid out on the planar GaAs substrate ( 14 ) in a zig-zag manner.