Abstract:
A video signal processing device rearranges line sequential signals included in a video signal into line simultaneous signals by detecting the kinds of information carried by them, respectively, for horizontal scanning periods; and adequately inhibits the line simultaneous signals from being produced.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a video signal processing device and more particularly to a device for processing a video signal including line sequential color difference signals which are provided with characteristic parts for identification of the kinds of information carried by these signals. 
     2. Description of the Related Art 
     In detecting the presence or absence of color information within a video signal for the purpose of controlling a so-called color killer circuit, it has been practiced in general, to attain that purpose by detecting the carrier wave components of color information signals and by detecting the levels of them. In the case of a video tape recorder or a television receiver or the like, for example, the levels of the subcarriers in the burst signal parts of chrominance signals have been arranged to be detected. Further, in cases where color information is transmitted by means of line sequential color difference signals which are modulated by an FM modulation process or the like before transmission, the levels of the FM carrier signals have been arranged to be detected for this purpose. 
     The conventional method for detecting the presence or absence of color information necessitates detection of extremely slight variations in the FM carrier signal in detecting the FM carrier signal. Besides, the level variations are not only caused by the validity of the color information but also greatly attributable to other factors, for example: In the case of an apparatus for reproducing a video signal recorded on a recording medium, the level of the FM carrier signal greatly varies due due to trailing, head touch, etc., even when the color information is accurate. Therefore, in setting a threshold value for the detection circuit, the value must be very delicately adjusted. It is thus hardly possible to accurately detect the presence or absence of color information. As a result, the apparatus of this kind has often produced meaningless color information to degrade a reproduced picture or failed to produce necessary color information. Further, the color information is sometimes produced for an extremely short period of time. In accordance with the conventional method, it has been thus hardly possible to obtain satisfactorily reproduced pictures even when the color information is valid. 
     SUMMARY OF THE INVENTION 
     This invention is directed to the solution of the above-stated problems of the prior art. It is therefore a general object of this invention to provide a video signal processing device which is capable of accurately detecting the presence or absence of color information carried by the video signal and always adequately produces the video signal. 
     It is a more specific object of this invention to provide a video signal processing device which is capable of detecting the kind, the presence or absence of information carried by line sequential signals without necessitating delicate adjustment of a circuit constant. 
     Under this object, a video signal processing device arranged as an embodiment of this invention for processing video signals including line sequential signals comprises: detecting means for detecting the kinds of information carried by the line sequential signals respectively for every horizontal scanning period; arranging means for rearranging the line sequential signals into line simultaneous signals on the basis of the output signal of the detecting means; and inhibiting means for inhibiting the line simultaneous signals from being produced from the device on the basis of the output signal of the detecting means. 
     It is another specific object of this invention to provide a video signal reproducing apparatus which is capable of producing adequate video signals by satisfactorily processing reproduced line sequential signals even in cases where the S/N ratio of signals reproduced from a recording medium is extremely poor. 
     Under that object, a video signal reproducing apparatus, arranged as another embodiment of this invention for reproducing video signals including line sequential color signals, comprises: reproducing means for reproducing the video signals from a recording medium; separating means for separating the line sequential color signals and luminance signals from the video signals reproduced by the reproducing means; detecting means for detecting the kinds of color information carried by the line sequential color signals for every horizontal scanning period; arranging means for rearranging the line sequential color signals into line simultaneous color signals on the basis of the output signal of the detecting means; color killer means which acts on the line simultaneous color signals on the basis of the output signal of the detecting means; and mixing means for mixing the luminance signals and the line simultaneous color signals. 
     The above and further objects and novel features of the invention will become apparent from the following detailed description of preferred embodiments thereof taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing the arrangement of a still picture signal reproducing apparatus arranged as an embodiment of this invention. 
     FIG. 2 is a diagram showing the arrangement of the essential parts of another embodiment of the invention. 
     FIG. 3 is a timing chart showing the output waveforms of various parts of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the case of the embodiment described in the following, this invention is applied to a still picture reproducing apparatus which is arranged to produce a still picture by repetitively reproducing one field portion of a video signal recorded in a circular recording track. FIG. 1 shows the arrangement of the reproducing apparatus arranged according to this invention as an embodiment thereof. A recording sheet 2 is arranged to be rotated by a motor 1 to make one turn for one field period. A head 3 is arranged to trace the recording track formed on the recording sheet 2. One and the same field portion of a video signal is thus continuously and repetitively reproduced by the head 3. The reproduced video signal is supplied to a reproduction amplifier 4. The output of the amplifier 4 is supplied to a Y-C separating circuit 5 to have a luminance signal and a line sequential color difference signal separated from each other. The two separated signals are supplied respectively to FM demodulation (hereinafter referred to as DEM) circuits 6 and 7. Meanwhile, a horizontal synchronizing signal (hereinafter referred to as HD signal), which is included in the reproduced video signal, is separated by an HD separating circuit 8. A line discrimination circuit 9 is arranged to detect the kind of the demodulated line sequential color difference signal for every horizontal scanning period (hereinafter referred to as H period). For example, in case that the line sequential color difference signal consists of B-Y and R-Y signals each of which is arranged to have a DC offset part at least during a specific period of time, the line discrimination circuit 9 detects this as a characteristic part. The circuit 9 produces a signal for every H period at a high level, for example, when the B-Y signal has the DC offset and at a low level when the R-Y signal has the DC offset. Under a normal condition, the line discrimination circuit 9 signal is of a rectangular waveform having a 2H period. 
     The HD signal is supplied also to a T type flip-flop (hereinafter referred to as TFF) 10. The TFF 10 also produces a rectangular wave signal of a 2H period. The output of the line discrimination circuit 9 and that of the TFF 10 are compared with each other at a comparator 12. If they are found to differ from each other in polarity, the comparator 12 produces a pulse output for every H period. 
     The pulse output of the comparator 12 is counted by a counter 13. The counter 13 is reset every time the sheet 2 makes one turn by means of a rotation detection signal (hereinafter referred to as PG signal) which represents the rotation of the motor 1. The counter 13 is arranged to have its counted value brought back to zero via an OR gate 15 when it produces a Q output after counting, for example, 2 4  pulses or thereabout. The output of this counter 13 is supplied to a flip-flop (FF) 16 to invert thereby the output of an exclusive OR circuit (hereinafter referred to as EXOR) 11. With the embodiment arranged in this manner, if the polarity of the output of the line discrimination circuit 9 and that of the output of the EXOR 11 differ from each other for at least a 2 4  -H period, the output of the EXOR 11 is judged to have its phase inverted relative to the phase of the output of the circuit 9. Then, the embodiment causes their phases to coincide with each other, The output of the EXOR 11 is supplied to a simultaneous rearrangement circuit 17. The circuit 17 then performs a simultaneous rearranging process on the output of the DEM 7 to make it into a chrominance signal. 
     In case that the counter 13 produces the Q output for a second time within one and the same field period, however, the output signal of the line discrimination circuit 9 produced within one field period would become irregular even if the phase of the output of the EXOR 11 is inverted. Therefore, this is detected and can be used in determining the validity or invalidity of the color signal. 
     A counter 18 is arranged, for example, to produce the Q output thereof when the Q output of the other counter 13 is obtained at least twice within one field period. The output of the counter 18 is supplied to a D flip-flop (hereinafter referred to as DFF) 19. A color killer circuit 20 is thus controlled by the output of the DFF 19 for every field. The luminance signal produced from DEM circuit 6 and the chrominance signal, which is obtained via the color killer circuit 20, are added up at an adder 21. In accordance with the above-stated arrangement of this embodiment, the FM carrier of the line sequential color difference signals does not have to be detected. The arrangement of the embodiment, therefore, obviates the necessity for adjustment of the constants of circuit elements and yet the validity of the color signals can be effectively detected. 
     FIG. 2 shows the arrangement of the essential parts of another embodiment of this invention. The illustration includes input terminals 31, 32 and 33 which receive demodulated line sequential color difference signals having DC offsets interposed in between lines, the HD signal and the PG signal respectively. FIG. 3 is a timing chart showing the waveforms of the outputs of various parts of FIG. 2. The embodiment operates as follows: 
     Referring to FIG. 3, when the signal of a wave form as shown at a part A in FIG. 3 is received at the terminal 31, a timing pulse generating circuit 34 produces pulse signals of 2H period as shown at parts C and D of FIG. 3 on the basis the HD signal which is received at the terminal 32 and is of a waveform as shown at a part B of FIG. 3. The pulse signal C turns on an analog switch 35 to short-circuit the input and output terminals of an inverter 36 at every 2H period. Following this, the level of the line sequential color difference signal, obtained during an offset discrimination period X1 indicated in FIG. 3, is retained at a coupling capacitor 37 as a reference voltage. An offset level, which is obtained during a discrimination period X2 (FIG. 3) for a next line, is either higher or lower by a value ΔV than the offset level obtained during the offset discrimination period X1. 
     After the reference voltage is set, a level of difference between the color diffrerence signal and the reference voltage is amplified up to a logical level through inverters 38, 39 and 40 and is then supplied to the D input terminal of a DFF 41. In this instance, since the pulse signal D is generated in synchronism with the discrimination period X2, the DFF 41 produces from its Q output terminal a signal which is obtained by amplifying the level of difference between the levels obtained during the discrimination periods X1 and X2 up to a high or low logical level. 
     Meanwhile, the HD signal is supplied to a TFF 42. The TFF 42 then produces a rectangular wave signal of a 2H period as shown at a part E of FIG. 3. If the line sequential color difference signals received are in accordance with a predetermined order, the Q output of the DFF 41 is always either at a high level or at a low level. An EXOR 46 is arranged to allow the rectangular wave pulse signal E of 2H period to pass therethrough either as it is or by inverting it forming the signal G. The output of the EXOR 46 is supplied as a line discrimination signal to the line simultaneous rearrangement circuit 17 of FIG. 1. 
     In case that the line sequential color difference signals are carrying valid information, the DFF 41 has the D input thereof always at a constant high or low level. If the D input often changes between the high and low levels, the information carried by the line sequential color difference signals can be judged to be invalid. The D input of the DFF 41 is counted by a counter 43, which is arranged to be reset by the PG signal. When the counter 43 counts at least a predetermined number within one field period, it produces the Q output thereof at a high level. This Q output is supplied via a DFF 44 to the color killer circuit 20 in the same manner as in the case of the preceding example of embodiment which is shown in FIG. 1. 
     The arrangement of the embodiment shown in FIG. 2 permits use of CMOS elements for nearly all the circuits. Therefore, in addition to the same advantageous effect as the embodiment shown in FIG. 1, the embodiment shown in FIG. 2 is suited for use of an IC so that circuit arrangement can be further simplified.