Abstract:
A semiconductor device and its fabrication method are provided. A semiconductor device includes first and second trench regions formed in first and second areas of a semiconductor substrate, respectively. A first device isolation layer is formed in the first trench region and includes a first trench oxide layer formed on side walls of the first trench region. A first nitride liner is formed on the side walls of the first trench oxide layer and a first insulation layer pattern is formed on the first nitride liner to fill the first trench region. A second device isolation layer is formed in the second trench region and includes a second trench oxide layer formed on the side walls of the second trench region. A second nitride liner is formed on the side walls of the second trench oxide layer. A second insulation layer pattern is formed on the second nitride liner to fill the second trench region. The first trench oxide layer is substantially thicker than the second trench oxide.

Description:
RELATED APPLICATION  
         [0001]    This application claims priority from Korean Patent Application No. 2001-23458, filed on Apr. 30, 2001, the contents of which are incorporated herein by this reference in their entirety.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a semiconductor device having a trench isolation structure and to a method for fabricating the same.  
           [0004]    2. Description of the Related Art  
           [0005]    As semiconductor devices become more highly integrated, various approaches have been used to further scaling down the semiconductor devices. Specifically, a cell array area of the semiconductor devices can be reduced by employing a shallow trench isolation structure (STI) instead of a local oxidation of silicon (LOCOS) isolation structure. But, the trench isolation structure is employed, various defects that affect various device characteristics can occur, because a semiconductor substrate is etched to form a trench region. Thus, several processing techniques are introduced to cure such defects generated during the formation of the trench region.  
           [0006]    [0006]FIGS. 1 through 3 are process cross-sectional views illustrating a semiconductor device having a conventional trench isolation structure. In the drawings, the reference character “a” corresponds to a cell array region and the reference character “b” corresponds to a peripheral circuit region including PMOS transistors.  
           [0007]    Referring to FIG. 1, a buffer oxide layer  102  and a hard mask layer  104  are formed on a semiconductor substrate  100 . The hard mask layer and the buffer oxide layer are patterned using a photoresist pattern  106  as an etch mask to form the buffer oxide layer pattern  102  and the hard mask pattern  104 , which are sequentially stacked.  
           [0008]    Referring to FIG. 2, the photoresist pattern  106  is removed, and the semiconductor substrate  100  is etched using the hard mask pattern  104  as an etch mask to form a trench region. The trench region in turn defines an active region. Then, a trench oxide layer  108  is formed on the side walls of the trench region, and a nitride layer  110  is conformally formed on the side wall of the trench oxide layer  108 . Continuously, an insulation layer  112  is formed to fill up the region surrounded by the nitride layer  110 .  
           [0009]    Referring to FIG. 3, the insulation layer  112  is planarized using a chemical mechanical polishing (CMP) process. As a result, a nitride liner  110   a  is formed on the trench oxide layer  108 , and an insulation layer pattern  114  is formed in the region surrounded by the nitride liner  110   a.  Then, after recessing a top of the insulation layer pattern  114 , the hard mask pattern  104  is removed using a wet etch of a phosphoric solution to form a device isolation layer.  
           [0010]    As described above, in a conventional technique, trench isolation layers of the cell array region and the peripheral circuit region are formed at the same time. In other words, the thickness of the trench oxide layer in the cell array region is the same as that of the trench oxide layer in the peripheral circuit region. In this case, the thickness of the trench oxide layer directly affects the characteristic of MOS transistors formed in the active region. These problems are further explained through FIGS. 4 and 5.  
           [0011]    [0011]FIG. 4 is a cross-sectional view illustrating a phenomenon where the device characteristics of the MOS transistor degrade if the thickness of the trench oxide layer is relatively thick.  
           [0012]    Specifically, if a trench oxide layer  108   a , that is, a trench thermal oxide layer formed on the side wall of the trench region is relatively thick, the top corner of the trench region develops a sharp recess, as shown in FIG. 4. Further, during the removal of the hard mask pattern  104  of FIGS. 1 and 2 and the buffer oxide layer pattern  102  of FIGS. 1 and 2, the trench oxide layer  108   a  can be over-etched, thereby forming a recessed region  40 . A gate oxide layer  32  is formed on the active region of the resulting structure having the recessed region  40 , and a gate electrode  34  is formed overlying the gate oxide layer  32  and the device isolation layer.  
           [0013]    If recessed regions  40  are formed at the top corners of the trench region, even though a subthreshold voltage, i.e., the lower than a threshold voltage, is applied to the gate electrode  34 , a channel can be formed on the top portions of the sidewalls of the trench region due to an inverse narrow-width effect. Here, the subthreshold voltage is. This is because a strong electric field is locally concentrated on the gate oxide layer  32  overlying the sharp top corners of the trench region. Consequently, undesirable leakage currents flow between the source region and the drain region in the MOS transistor. Further, the reliability of the gate oxide layer  32  degrades and a gate leakage currents increase. Specifically, when the inverse narrow-width effect occurs in a cell transistor of a DRAM, a short refresh period is required to increase power consumption.  
           [0014]    [0014]FIG. 5 is a cross-sectional view illustrating the problem where characteristics of the MOS transistor degrade with a relatively thin trench oxide layer.  
           [0015]    As illustrated in FIG. 5, if the trench oxide layer  108   b  is relatively thin, it is possible to prevent formation of the recessed region  40 . Further, the top corner of the trench region can have a round shape. Thus, it is possible to improve the characteristics of the leakage currents resulting from the inverse narrow-width effect. However, the nitride liner  110   a  that covers the side wall of the trench oxide layer  108   b  is generally known to have a negative charge. Thus, in the case of a thin trench oxide layer  108   b , the positive coupling charge can be induced on the sidewalls of a trench region, thus forming an undesirable P-channel. Consequently, if the trench oxide layer  108   b  is thin, the leakage current characteristic of the PMOS transistor degrades or malfunction thereof can occur.  
         SUMMARY OF THE INVENTION  
         [0016]    Therefore, the present invention provides a semiconductor device having trench oxide layers of each different thickness at the region where an NMOS transistor of a cell array region and a PMOS transistor of a peripheral circuit are formed.  
           [0017]    The present invention also provides a method for fabricating a semiconductor device that can form trench oxide layers of each different thickness at the region where an NMOS transistor of a cell array region and a PMOS transistor of a peripheral circuit are formed.  
           [0018]    In order to approach the object, the present invention includes the first device isolation layer and the second device isolation layer formed in the first area and the second area of a semiconductor substrate, respectively. The first device isolation layer defines an active region of the first area. Likewise, the second device isolation layer defines another active region in the second area. The first device isolation layer consists of the first trench oxide layer, the first nitride liner and the first insulation layer pattern. Here, the first trench oxide layer is formed on the side walls of the first trench region, and the first nitride liner is formed on the side walls of the first trench oxide layer. The first insulation layer pattern fills the region surrounded by the first nitride liner. The second device isolation layer includes the second trench oxide layer, the second nitride liner and the second insulation layer pattern. Here, the second trench oxide layer is thinner than the first trench oxide layer on the side walls of the second trench region. The second nitride liner is formed on the side walls of the second trench oxide layer. The second insulation layer pattern fills the region surrounded by the second nitride liner.  
           [0019]    According to one embodiment of the present invention, the active region between first trench regions corresponds to a peripheral circuit region including PMOS transistors, and the active region between the second trench regions corresponds to a cell array region. The first trench region and the second trench region are formed in the first area and the second area, respectively. Then, a first trench oxide layer is formed on the side walls of the first trench region. The second trench oxide layer is formed on the side walls of the second trench region. The second trench oxide layer is thinner than the first trench oxide layer. Next, the nitride layer is conformally formed on the side walls of the first trench oxide layer and the second trench oxide layer. Then, the first insulation layer pattern is formed in the first trench region to fill the region surrounded by the nitride layer. The second insulation layer pattern is formed in the second trench region to fill the region surrounded by the nitride liner. As a result, the first device isolation layer is formed in the first area, and the second device isolation layer is formed in the second area. Here, the second trench oxide layer is thinner than the first trench oxide layer.  
           [0020]    According to another embodiment of the present invention, to form first and second trench oxide layers, a buffer oxide layer and a hard mask layer are sequentially formed on the semiconductor substrate having the first and the second areas. Then, the hard mask layer, the buffer oxide layer and the semiconductor substrate are sequentially patterned to form the first trench region in the first area. The first thermal oxidation process is performed on the resulting structure where the first trench region is formed. Next, the hard mask layer, the buffer oxide layer and the semiconductor substrate are sequentially patterned to form the second trench region in the second area. The second thermal oxidation process is performed on the resulting structure where the second trench region is formed. Thus, the first trench oxide layer is more thickly formed than the second trench oxide layer.  
           [0021]    In the semiconductor device according to the present invention, the peripheral circuit including PMOS transistors is formed in the active region between the first trench regions. Also, the cell array region including cell transistors and capacitors is formed in the active region between the second trench regions. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    [0022]FIGS. 1 through 3 are cross-sectional views illustrating a conventional process for fabricating a semiconductor device.  
         [0023]    [0023]FIGS. 4 through 5 are cross-sectional views illustrating device isolation structures depending on the thickness of a trench oxide layer.  
         [0024]    [0024]FIG. 6 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.  
         [0025]    [0025]FIGS. 7 through 13 are cross-sectional views illustrating a method of fabricating a semiconductor device according to another embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0026]    The present invention will be now described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In attached figures, the thickness of layers and regions is exaggerated for clarity. Also, when it is mentioned that a layer is on another layer or on a substrate, a layer can be directly formed on another layer or on a substrate, or the third layer can be interposed therebetween. The same reference numbers indicate the same components thorough the whole specifications.  
         [0027]    [0027]FIG. 6 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.  
         [0028]    Referring to FIG. 6, a first device isolation layer  30  includes a first trench oxide layer  22 , a first nitride liner  24   a  and a first insulation layer pattern  26   a.  The first device isolation layer  30  is formed in a peripheral circuit region “b”. A second device isolation layer  31  includes a second trench oxide layer  23 , a second nitride liner  24   a  and a second insulation layer pattern  26   b.  The second device isolation layer  30  is formed in a cell array region “a”. The first device isolation layers  30  define an active region in the peripheral circuit region “b”, and the second device isolation layers  31  define an active region in the cell array region “a”. A peripheral circuit transistor gate  34   c  is formed on the active region between the first device isolation layers  30 , and a gate dielectric layer  33  is interposed between the active region and the peripheral circuit transistor gate  34   c.  A cell transistor gate  34   a  is formed on the active region between the second device isolation layers  31 , and another gate dielectric layer  33  is interposed between the active region and the cell transistor gate  34   a.  The gate dielectric layers  33  each can be formed with different thickness in the cell array region “a” and the peripheral circuit region “b”.  
         [0029]    As illustrated in FIG. 6, the second device isolation layer  31  in the cell array region (a) has the relatively thin trench oxide layer  23  thinner than the trench oxide layer  22  to prevent an inverse narrow-width effect at the cell transistor. On the contrary, the first device isolation layer  30  of the peripheral circuit region “b” has the relatively thick trench oxide layer  22  thicker than the trench oxide layer  23  of the cell array region “a” to prevent a charge effect trapped within a nitride liner. Thus, it is possible to solve conventional leakage current problems in cell and PMOS transistors that occur when device isolation layers in a cell array region and a peripheral circuit region are formed at the same time. Preferably, the first trench oxide layer  22  have a thickness of 100 Å to 200 Å and the second trench oxide layer  23  have a thickness of 50 Å to 100 Å.  
         [0030]    [0030]FIGS. 7 through 13 are cross-sectional views illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.  
         [0031]    Referring to FIG. 7, a buffer oxide layer  11  and a hard mask layer  12  are sequentially formed in the regions of the cell array “a” and the peripheral circuit “b”. A first photoresist pattern  13  is formed on the hard mask layer  12 .  
         [0032]    Preferably, the buffer oxide layer  11  has a thickness of 100 Å to 200 Å so that the buffer oxide layer  11  absorbs the stress applied on the semiconductor substrate  100  due to the presence of the hard mask layer  12 . Ideally, the hard mask layer  12  is a material layer having an etch selectivity with respect to the semiconductor substrate  100 . Thus, it is desired that the hard mask layer is formed by, for example, a silicon nitride layer or by sequentially stacking the silicon nitride layer and an oxide layer. Also, the hard mask layer  12  is preferably formed to a thickness of 500 Å to 2,000 Å.  
         [0033]    Referring to FIG. 8, the hard mask layer  12 , the buffer oxide layer  11  and the semiconductor substrate  100  are sequentially etched using the first photoresist pattern  13  as an etch mask to form a first trench region T 1  in the peripheral circuit region “b”. Then, the first photoresist pattern  13  is removed, and a first thermal oxidation process is performed to form a preliminary oxide layer  21  on the sidewalls and the bottom of the first trench region T 1 .  
         [0034]    The first trench region is preferably formed by etching the semiconductor substrate  100  to a thickness of 2,000 Å to 10,000 Å. The preliminary oxide layer  21  is preferably formed to a thickness of 50 Å to 100 Å.  
         [0035]    Referring to FIG. 9, a second photoresist pattern  14  is formed to cover the first trench region T 1  in the peripheral circuit region “b” and to expose a predetermined region of the cell array region “a”. The hard mask layer  12 , the buffer oxide layer  11  and the semiconductor substrate  100  are sequentially etched using the second photoresist pattern  14  as an etch mask to form a second trench region T 2  in the cell array region “a”.  
         [0036]    The second trench region T 2  can be formed to a thickness different from that of the first trench region T 1 , depending on the application. For example, if the width of the second trench region T 2  is narrower than that of the first trench region T 1 , the second trench region T 2  can be formed shallow to prevent voids during the formation of a device isolation layer.  
         [0037]    Referring to FIG. 10, the second photoresist pattern  14  is removed, and a second thermal oxidation process is performed on the semiconductor substrate  100 . The second thermal oxidation process is performed to cure defects made to the semiconductor substrate occurring while the semiconductor substrate is etched to form the second trench region T 2 . Also, the second thermal oxidation process is performed to form a thermal oxide layer having a thickness of 50 Å to 100 Å on the bottom and the sidewalls of the second trench region T 2 . During the second thermal oxidation process, the first trench region T 1  is also oxidized to add more thermal oxide layer to the preliminary oxide layer  21  that has been formed in the first thermal oxidation process. As a result, the thick first trench oxide layer  23  of a thickness of 100 Å to 200 Å is formed in the first trench region T 1 , and the second trench oxide layer  22  of 50 Å to 100 Å is formed in the second trench region T 2 .  
         [0038]    Referring to FIG. 11, a nitride layer  24  is conformally formed on the surface of the resulting structure where the first trench oxide layer  23  and the second trench oxide layer  22  are formed. The nitride layer  24  is preferably formed to a thickness of 50 Å to 200 Å. Then, an insulation layer  25  is formed on the nitride layer  24  to fill the first and the second trench regions T 1  and T 2 . The insulation layer  25  is preferably formed of one of a high density plasma chemical vapor deposition (HDP CVD) oxide layer, a boro-phosphosilicate glass (BPSG) layer and an O 3 -TEOS layer as a material layer having a superior burial characteristic. If the insulation layer  25  is a HDP CVD layer, a plasma having high energy is used. Thus, in order to prevent etching the nitride liner  24  by plasma of high energy, it is desired that a medium temperature oxide (MTO) layer is conformally formed before forming the HDP CVD layer.  
         [0039]    Referring to FIG. 12, the insulation layer  25  is etched using a chemical mechanical polishing (CMP) process to expose the hard mask layer  12  between the trench regions T 1 , T 2 . At this time, in order to prevent the insulation layer  25  from remaining at the top of the hard mask layer  12 , it is desired that the top of the hard mask layer  12  be partially etched. As a result, a first nitride liner  24   a  is formed on the first trench oxide layer  22 , and a first insulation layer pattern  26   a  is formed in the region surrounded by the first nitride liner  24   a.  Likewise, a second nitride liner  24   b  is formed on the second trench oxide layer  23 , and a second insulation layer pattern  26   b  is formed in the region surrounded by the second nitride liner  24   b.  Then, the top of the first and the second insulation layer patterns  26  are recessed to lower the height of the top surface of the first and the second insulation layer patterns  26 . This reduces a step difference of gate electrodes extending across the top surfaces of the semiconductor substrate and the device isolation layer.  
         [0040]    Referring to FIG. 13, the remaining hard mask layer  12 , the first nitride liner  24   a  and the second nitride liner  24   b  are removed using conventional techniques such as a isotropic wet etching method utilizing a phosphoric acid solution. The buffer oxide layer  11  is removed. As a result, the first device isolation layer  30  including the fist trench oxide layer  22 , the first nitride liner  24   a  and the first insulation layer pattern  26   a  is formed in the peripheral circuit region “b”. Also, the second device isolation layer  31  including the second trench oxide layer  23 , the second nitride liner  24   a  and the second insulation layer pattern  26   b  is formed in the cell array region “a”.  
         [0041]    Subsequently, although not illustrated, the peripheral circuit includes the PMOS transistors having a wide gate width at the region between the first device isolation layers  30 . The cell array includes capacitors and cell transistors having a narrow gate width at the regions between the second device isolation layers  31 .  
         [0042]    As described above, the semiconductor device of the present invention has device isolation layers including trench oxide layers each having a different thickness in the cell array region and in the peripheral circuit region. Consequently, it is possible to reduce the current leakage from the cell capacitor, and to reduce the charge trapped in the PMOS transistors in the peripheral circuit.  
         [0043]    In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purpose of limitation, the scope of the invention being set forth in the following claims.