Abstract:
A GOA circuit for an LCD includes GOA units connected in cascade and the plurality of GOA units at stages formed. The GOA unit at an nth stage corresponds to a scan line. The scan line includes a nth scan line, a (n+1)th scan line, and a (n+2)th scan line. The GOA unit at the an nth stage includes a first pull-down holding circuit, a pull-up circuit, a bootstrap capacitance circuit, a pull-down circuit, and a clock circuit. The improved GOA circuit at one stage corresponds to the output of three gate lines. So a number of the stages of the GOA circuit is reduced. Only ⅓ stage of the conventional GOA circuit is needed. Because of the decrease in the number of the stages, more flexibility of design is given to the GOA circuit at each stage. It is beneficiary for the design in narrow bezels.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of liquid crystal displays (LCDs), and more particularly, to a gate driver on array (GOA) circuit applying to LCDs. 
     2. Description of the Prior Art 
     The design of narrow bezels becomes very popular on the market. On the contrary, the border of the panel is gradually reduced. The height h of wiring layout of the GOA circuit at each stage is consistent with the size of a corresponding pixel for the conventional GOA circuit. Since products using display panels with 4 k or more pixel per inch (PPI) resolution become popular, the size of the pixel gets smaller. In other words, the room for wiring layout of the GOA circuit is decreased as well. The restriction of the height is compensated for the larger width, which is very disadvantageous to the design of the narrow bezel. 
     The tri-gate structure is a common method of reducing cost. With respect to tri-gate structure, the number of scan lines is triple the number of the original design while the number of data lines is one third of the original design. The use of the data lines greatly reduces. In general, a source chip, i.e. source integrated circuit (IC) is more expensive than a gate chip, i.e. gate IC, so the goal to cost saving is achieved. The use of tri-gate structure with the GOA circuit makes it possible that no gate ICs and quite a few source ICs are used in the panel. Therefore, the cost of the panel is reduced, which is quite competitive on the market. 
     However, the space for the GOA circuit at each stage gets smaller since the number of scan lines is triple the number of the original design after the structure of tri-gate is adopted. Based on the structure of the conventional circuit, the width of the GOA area is sacrificed, but it is not disadvantageous to the popular bezel design nowadays. 
     Tri-gate is often used in a low-cost panel. Take a full high definition (FHD) panel for example. A standard panel comprises 1080 gate lines and 5760 data lines. Totally, 6840 signal lines are used. A panel with tri-gate comprises 3240 common gate lines and 1920 data lines. Totally, 5160 signal lines are used. It is obvious that the panel with tri-gate has fewer signals lines than the standard panel does. No gate lines are needed for the structure tri-gate integrated with GOA. Therefore, the cost of panels is reduced to the largest scale. 
     The gate signal node Q(n) is a critical electric potential for the GOA circuit. When the gate signal node Q(n) is at high voltage level, the GOA circuit keeps opening and outputting. On the contrary, the GOA circuit keeps closed when the gate signal node Q(n) is at low voltage level. In the meantime, the gate signal output by the GOA circuit is also at low voltage level. 
     Please refer to  FIG. 1 .  FIG. 1  is a circuit diagram of a conventional GOA circuit  10 . The GOA circuit  10  comprises a plurality of GOA units  15 . The plurality of GOA units  15  are connected in cascade. The GOA unit  15  at the nth stage charges a corresponding scan line G(n). The GOA unit  15  comprises a clock circuit  100 , a pull-down circuit  200 , a bootstrap capacitance circuit  300 , a pull-up circuit  400 , and a pull-down circuit  500 . The basic structure of GOA unit  15  comprises the clock circuit  100 , the pull-down circuit  200 , the bootstrap capacitance circuit  300 , and the pull-up circuit  400 . The GOA unit  15  comprises four thin-film transistors (TFTs) and a capacitor. Because amorphous silicon may be unstable and unreliable, the pull-down circuit  500  is also needed except for the basic structure. The main function of the pull-down circuit  500  is to pull-down voltage of the gate line G(n), that is, to ensure that the output of the GOA circuit and the gate signal node Q(n) keep at low voltage level and that the stability of the GOA circuit in operation is enhanced. 
     Two auxiliary pull-down circuits are usually used in the conventional design. The function of the auxiliary pull-down circuits is pulling voltage of the gate signal node Q(n) down when the GOA circuit is closed so that the gate signal node Q(n) can keeps low voltage level. It ensures the normal working state of the panel and the increasing stability of the panel. The auxiliary pull-down circuit usually comprises more TFTs. These TFTs occupies larger space, which is disadvantageous when the narrow bezel is taken into consideration. With respect to the two auxiliary pull-down circuits, a detailed introduction is provided as follows. Please refer to  FIG. 2  as well. 
     Please refer to  FIG. 2  and  FIG. 3 .  FIG. 2  is a circuit diagram of another conventional GOA circuit  20 .  FIG. 3  shows waveforms of signals applied the GOA circuit  20  as shown in  FIG. 2 . Compared with  FIG. 1 , the pull-down circuit  500  comprises a first auxiliary pull-down circuit  510  and a second auxiliary pull-down circuit  520 . The first auxiliary pull-down circuit  510  and the second auxiliary pull-down circuit  520  are controlled by a low-frequency signal LC 1  and a low-frequency signal LC 2 , respectively. The first auxiliary pull-down circuit  510  and the second auxiliary pull-down circuit  520  operate alternatively at different periods of time to ensure that the output terminal of the GOA circuit and the gate signal node Q(n) keep at low voltage level when the gate line G(n) is closed. The low-frequency signal LC 1  and the low-frequency signal LC 2  are inversed. When the low-frequency signal LC 1  is at high voltage level, the first auxiliary pull-down circuit  510  is used to pull down the voltage of the gate line G(n) while the second auxiliary pull-down circuit  520  is at low voltage level at this time. After a plurality of frames, the low-frequency signal LC 1  becomes at low voltage level and the low-frequency signal LC 2  becomes at high voltage level. The second auxiliary pull-down circuit  520  is used to pull down the voltage of the gate line G(n). Further, the pull-down circuit  500  can have other structures.  FIG. 3  shows that the CK signal at six stages working with the low-frequency signal LC 1  and the low-frequency signal LC 2  switch once about every 100 frames for producing corresponding signals of the gate line G(n). The feature of the circuit shown in  FIG. 2  is that the GOA circuit at every stage corresponds to the output of a gate line G(n). Once the panel adopts tri-gate structure, the number of scan lines is triple the number of the original design while the height of space occupied by the GOA circuit at each stage becomes one third of the original design. The width of the wiring layout has to be enlarged. As a result, the border of the panel needs to be broadened, which is disadvantageous to the popular narrow bezel design. 
     Therefore, it is necessary to propose a GOA circuit applying to LCDs to resolve the problem happening in the conventional technology. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to propose a GOA circuit applying to LCDs. 
     According to the present invention, a gate driver on array (GOA) circuit for a liquid crystal display (LCD) comprises a plurality of GOA units connected in cascade and the plurality of GOA units at stages formed. The GOA unit at an nth stage corresponds to at least one scan line. The at least one scan line comprises a nth scan line, a (n+1)th scan line, and a (n+2)th scan line. The GOA unit at the an nth stage comprises a first pull-down holding circuit, a pull-up circuit, a bootstrap capacitance circuit, a pull-down circuit, and a clock circuit. 
     The first pull-down holding circuit is connected to a gate signal node. The pull-up circuit is connected to the first pull-down holding circuit through the gate signal node. The bootstrap capacitance circuit is connected to the pull-up circuit through the gate signal node. The pull-down circuit is connected to the bootstrap capacitance circuit through the gate signal node. The clock circuit is connected to the bootstrap capacitance circuit through the gate signal node and receiving a first clock signal. 
     The first pull-down holding circuit and the pull-down circuit are connected to a direct current low supply voltage. 
     The clock circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor. 
     The first transistor comprises a first control terminal connected to the gate signal node, a first input terminal connected to the first clock signal, and a first output terminal outputting a start pulse at an nth stage. The second transistor comprises a second control terminal connected to the gate signal node, a second input terminal connected to the first clock signal, and a second output terminal connected to the nth scan line. The third transistor comprises a third control terminal connected to the gate signal node, a third input terminal connected to the first clock signal, and a third output terminal connected to the (n+1)th scan line. The fourth transistor comprises a fourth control terminal connected to the gate signal node, a fourth input terminal connected to the first clock signal, and a fourth output terminal connected to the (n+2)th scan line. 
     According to one preferred embodiment, the bootstrap capacitance circuit comprises a first capacitor which comprises two terminals connected to the gate signal node and the start pulse at the nth stage, respectively. 
     According to one preferred embodiment, the pull-up circuit comprises a fifth transistor. The fifth transistor comprises a fifth control terminal receiving a start pulse at an (n−3)th stage, a fifth input terminal connected to the fifth control terminal, and a fifth output terminal connected to the gate signal node. 
     According to one preferred embodiment, the first pull-down holding circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. 
     The sixth transistor comprises a sixth control terminal receiving a start pulse at the (n+3)th stage, a sixth input terminal connected to the direct current low supply voltage, and a sixth output terminal connected to the gate signal node. The seventh transistor comprises a seventh control terminal connected to the gate signal node, and a seventh input terminal connected to the direct current low supply voltage. The eighth transistor comprises an eighth control terminal connected to a direct current high supply voltage, an eighth output terminal connected to the eighth control terminal, and an eighth input terminal connected to a seventh output terminal. The ninth transistor comprises a ninth control terminal connected to the gate signal node, and a ninth input terminal connected to the direct current low supply voltage. The tenth transistor comprises a tenth control terminal connected to the seventh output terminal, a tenth input terminal connected to the ninth output terminal, and a tenth output terminal connected to the eighth output terminal. The eleventh transistor comprises an eleventh control terminal connected to the tenth input terminal, an eleventh input terminal connected to the direct current low supply voltage, and an eleventh output terminal connected to the gate signal node. The twelfth transistor comprises a twelfth control terminal connected to the tenth input terminal, a twelfth input terminal connected to the direct current low supply voltage, and a twelfth output terminal connected to the start pulse at the nth stage. 
     According to one preferred embodiment, the pull-down circuit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twentieth-first transistor. 
     The thirteenth transistor comprises a thirteenth control terminal connected to the first pull-down holding circuit, a thirteenth input terminal connected to the direct current low supply voltage, and a thirteenth output terminal connected to the nth scan line. The fourteenth transistor comprises a fourteenth control terminal connected to a second clock, a fourteenth input terminal connected to the direct current low supply voltage, and a fourteenth output terminal connected to the nth scan line. The fifteenth transistor comprises a fifteenth control terminal connected to a fourth clock signal, a fifteenth input terminal connected to the direct current low supply voltage, and a fifteenth output terminal connected to the nth scan line. The sixteenth transistor comprises a sixteenth control terminal connected to the first pull-down holding circuit, a sixteenth input terminal connected to the direct current low supply voltage, and a sixteenth output terminal connected to the (n+1)th scan line. The seventeenth transistor comprises a seventeenth control terminal connected to a third clock signal, a seventeenth input terminal connected to the direct current low supply voltage, and a seventeenth output terminal connected to the (n+1)th scan line. The eighteenth transistor comprises an eighteenth control terminal connected to a fifth clock signal, an eighteenth input terminal connected to the direct current low supply voltage, and an eighteenth output terminal connected to the (n+1)th scan line. The nineteenth transistor comprises a nineteenth control terminal connected to the first pull-down holding circuit, a nineteenth input terminal connected to the direct current low supply voltage, and a nineteenth output terminal connected to the (n+2)th scan line. The twentieth transistor comprises a twentieth control terminal connected to the fourth clock signal, a twentieth input terminal connected to the direct current low supply voltage, and a twentieth output terminal connected to the (n+2)th scan line. The twentieth-first transistor comprises a twenty-first control terminal connected to a sixth clock signal, a twenty-first input terminal connected to the direct current low supply voltage, and a twenty-first output terminal connected to the (n+2)th scan line. 
     According to one preferred embodiment, the GOA circuit further comprises a second pull-down holding circuit. The second pull-down holding circuit comprises a twentieth-second transistor and a twentieth-third transistor. The twentieth-second transistor comprises a twenty-second control terminal connected to the fourth clock signal, a twenty-second input terminal connected to a direct current low supply voltage, and a twenty-second output terminal connected to the gate signal node. The twentieth-third transistor comprises a twenty-third control terminal connected to the fourth clock signal, a twenty-third input terminal connected to the direct current low supply voltage, and a twenty-third output terminal connected to the start pulse at the nth stage. 
     According to one preferred embodiment, the cycle of the first clock signal, the cycle of the second clock signal, and the cycle of the third clock signal are the same, and the first clock signal, the second clock signal, and the third clock signal are triggered subsequently based on the difference of a ⅓ cycle. 
     According to one preferred embodiment, the fourth clock signal is inversed to the first clock signal, the fifth clock signal is inversed to the second clock signal, and the sixth clock signal is inversed to the third clock signal. 
     According to the present invention, a gate driver on array (GOA) circuit for a liquid crystal display (LCD) comprises: a plurality of GOA units connected in cascade and the plurality of GOA units at stages formed. The GOA unit at an nth stage corresponds to at least one scan line. The at least one scan line comprise (n+3)th scan line, a (n+4)th scan line, and a (n+5)th scan line. The GOA unit at the an nth stage comprises a first pull-down holding circuit, a pull-up circuit, a bootstrap capacitance circuit, a pull-down circuit, and a clock circuit. 
     The first pull-down holding circuit is connected to a gate signal node. The pull-up circuit is connected to the first pull-down holding circuit through the gate signal node. The bootstrap capacitance circuit is connected to the pull-up circuit through the gate signal node. The pull-down circuit is connected to the bootstrap capacitance circuit through the gate signal node. The clock circuit is connected to the bootstrap capacitance circuit through the gate signal node and receiving a first clock signal. 
     The first pull-down holding circuit and the pull-down circuit are connected to a direct current low supply voltage. 
     The clock circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor. 
     The first transistor comprises a first control terminal connected to the gate signal node, a first input terminal connected to the fourth clock signal, and a first output terminal outputting a start pulse at an (n+3)th stage. The second transistor comprises a second control terminal connected to the gate signal node, a second input terminal connected to the fourth clock signal, and a second output terminal connected to the (n+4)th scan line. The third transistor comprises a third control terminal connected to the gate signal node, a third input terminal connected to the fourth clock signal, and a third output terminal connected to the (n+5)th scan line. The fourth transistor comprises a fourth control terminal connected to the gate signal node, a fourth input terminal connected to the fourth clock signal, and a fourth output terminal connected to the (n+5)th scan line. 
     According to one preferred embodiment, the bootstrap capacitance circuit comprises a first capacitor. The first capacitor comprises two terminals connected to the gate signal node and the start pulse at the (n+3)th stage, respectively. 
     According to one preferred embodiment, the pull-up circuit comprises a fifth transistor. The fifth transistor comprises a fifth control terminal receiving a start pulse at an nth stage, a fifth input terminal connected to the fifth control terminal, and a fifth output terminal connected to the gate signal node. 
     According to one preferred embodiment, the first pull-down holding circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. 
     The sixth transistor comprises a sixth control terminal receiving a start pulse at the (n+6)th stage, a sixth input terminal connected to the direct current low supply voltage, and a sixth output terminal connected to the gate signal node. The seventh transistor comprises a seventh control terminal connected to the gate signal node, and a seventh input terminal connected to the direct current low supply voltage. The eighth transistor comprises an eighth control terminal connected to a direct current high supply voltage, an eighth output terminal connected to the eighth control terminal, and an eighth input terminal connected to a seventh output terminal. The ninth transistor comprises a ninth control terminal connected to the gate signal node, and a ninth input terminal connected to the direct current low supply voltage. The tenth transistor comprises a tenth control terminal connected to the seventh output terminal, a tenth input terminal connected to the ninth output terminal, and a tenth output terminal connected to the eighth output terminal. The eleventh transistor comprises an eleventh control terminal connected to the tenth input terminal, an eleventh input terminal connected to the direct current low supply voltage, and an eleventh output terminal connected to the gate signal node. The twelfth transistor comprises a twelfth control terminal connected to the tenth input terminal, a twelfth input terminal connected to the direct current low supply voltage, and a twelfth output terminal connected to the start pulse at the (n+3)th stage. 
     According to one preferred embodiment, the pull-down circuit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twentieth-first transistor. 
     The thirteenth transistor comprises a thirteenth control terminal connected to the first pull-down holding circuit, a thirteenth input terminal connected to the direct current low supply voltage, and a thirteenth output terminal connected to the (n+3)th scan line. The fourteenth transistor comprises a fourteenth control terminal connected to a first clock, a fourteenth input terminal connected to the direct current low supply voltage, and a fourteenth output terminal connected to the (n+3)th scan line. The fifteenth transistor comprises a fifteenth control terminal connected to a third clock signal, a fifteenth input terminal connected to the direct current low supply voltage, and a fifteenth output terminal connected to the (n+3)th scan line. The sixteenth transistor comprises a sixteenth control terminal connected to the first pull-down holding circuit, a sixteenth input terminal connected to the direct current low supply voltage, and a sixteenth output terminal connected to the (n+4)th scan line. The seventeenth transistor comprises a seventeenth control terminal connected to a second clock signal, a seventeenth input terminal connected to the direct current low supply voltage, and a seventeenth output terminal connected to the (n+4)th scan line. The eighteenth transistor comprises an eighteenth control terminal connected to a fourth clock signal, an eighteenth input terminal connected to the direct current low supply voltage, and an eighteenth output terminal connected to the (n+4)th scan line. The nineteenth transistor comprises a nineteenth control terminal connected to the first pull-down holding circuit, a nineteenth input terminal connected to the direct current low supply voltage, and a nineteenth output terminal connected to the (n+5)th scan line. The twentieth transistor comprises a twentieth control terminal connected to the third clock signal, a twentieth input terminal connected to the direct current low supply voltage, and a twentieth output terminal connected to the (n+5)th scan line. The twentieth-first transistor comprises a twenty-first control terminal connected to a fifth clock signal, a twenty-first input terminal connected to the direct current low supply voltage, and a twenty-first output terminal connected to the (n+5)th scan line. 
     According to one preferred embodiment, the GOA circuit further comprises a second pull-down holding circuit. The second pull-down holding circuit comprises a twentieth-second transistor and a twentieth-third transistor. The twentieth-second transistor comprises a twenty-second control terminal connected to the first clock signal, a twenty-second input terminal connected to a direct current low supply voltage, and a twenty-second output terminal connected to the gate signal node. The twentieth-third transistor comprises a twenty-third control terminal connected to the first clock signal, a twenty-third input terminal connected to the direct current low supply voltage, and a twenty-third output terminal connected to the start pulse at the (n+3)th stage. 
     According to one preferred embodiment, the cycle of the first clock signal, the cycle of the second clock signal, and the cycle of the third clock signal are the same, and the first clock signal, the second clock signal, and the third clock signal are triggered subsequently based on the difference of a ⅓ cycle. 
     According to one preferred embodiment, the fourth clock signal is inversed to the first clock signal, the fifth clock signal is inversed to the second clock signal, and the sixth clock signal is inversed to the third clock signal. 
     With respect to the GOA circuit comprising three gates, the present invention proposes an improved GOA circuit. The improved GOA circuit at one stage corresponds to the output of three gate lines while the conventional GOA circuit at one stage corresponds to the output of one gate line. So a number of the stages of the GOA circuit is reduced. Only ⅓ stage of the conventional GOA circuit is needed. Because of the decrease in the number of the GOA circuit, more flexibility of design is given to the GOA circuit at each stage. It is beneficiary for the design in narrow bezels. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a conventional GOA circuit. 
         FIG. 2  is a circuit diagram of another conventional GOA circuit. 
         FIG. 3  shows waveforms of signals applied the GOA circuit as shown in  FIG. 2 . 
         FIG. 4  is a circuit diagram of a GOA circuit according to a first preferred embodiment of the present invention. 
         FIG. 5  is a circuit diagram of a GOA circuit according to a second preferred embodiment of the present invention. 
         FIG. 6  shows waveforms of signals applied the GOA circuits as shown in  FIGS. 4 and 5 . 
         FIG. 7  is a circuit diagram of a GOA circuit according to a third preferred embodiment of the present invention. 
         FIG. 8  is a circuit diagram of a GOA circuit according to a fourth preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. 
       FIG. 4  is a circuit diagram of the structure of a GOA circuit  30  according to a first preferred embodiment of the present invention. The GOA circuit  30  is used for liquid crystal displays (LCDs). The GOA circuit  30  comprises a plurality of GOA units  35 . The plurality of GOA units  35  connected in cascade to form GOA units  35  at a plurality of stages. The GOA unit  35  at the nth stage corresponds to at least one scan line at one stage. The at least one scan line comprises a scan line G(n) at the nth stage, a scan line G(n+1) at the (n+1)th stage, and a scan line G(n+2) at the (n+2)th stage. The GOA unit  35  at the nth stage comprises a first pull-down holding circuit  500 , a pull-up circuit  400 , a bootstrap capacitance circuit  300 , a pull-down circuit  200 , and a clock circuit  100 . 
     The first pull-down holding circuit  500  is connected to a gate signal node Q(n). The pull-up circuit  400  is connected to the first pull-down holding circuit  500  through the gate signal node Q(n). The bootstrap capacitance circuit  300  is connected to the pull-up circuit  400  through the gate signal node Q(n). The pull-down circuit  200  is connected to the bootstrap capacitance circuit  300  through the gate signal node Q(n). The clock circuit  100  is connected to the bootstrap capacitance circuit  300  through the gate signal node Q(n) and receives a first clock signal CK 1 . 
     The first pull-down holding circuit  500  and the pull-down circuit  200  are connected to a direct current low supply voltage. 
     The clock circuit  100  comprises a first transistor T 11 , a second transistor T 21 , a third transistor T 22 , and a fourth transistor T 23 . 
     The first transistor T 11  comprises a first control terminal, a first input terminal, and a first output terminal. The first control terminal is connected to the gate signal node Q(n). The first input terminal is connected to the first clock signal CK 1 . The first output terminal outputs a start pulse ST(n) at the nth stage. The second transistor T 21  comprises a second control terminal, a second input terminal, and a second output terminal. The second control terminal is connected to the gate signal node Q(n). The second input terminal is connected to the first clock signal CK 1 . The second output terminal is connected to the scan line G(n) at the nth stage. The third transistor T 22  comprises a third control terminal, a third input terminal, and a third output terminal. The third control terminal is connected to the gate signal node Q(n). The third input terminal is connected to the first clock signal CK 1 . The third output terminal is connected to the scan line G(n+1) at the (n+1)th stage. The fourth transistor T 23  comprises a fourth control terminal, a fourth input terminal, and a fourth output terminal. The fourth control terminal is connected to the gate signal node Q(n). The fourth input terminal is connected to the first clock signal CK 1 . The fourth output terminal is connected to the scan line G(n+2) at the (n+2)th stage. 
     The bootstrap capacitance circuit  300  comprises a first capacitor C boost . The first capacitor C boost  comprises two terminals. The terminals are connected to a gate signal node Q(n) and a start pulse at the nth stage ST(n), respectively. 
     The pull-up circuit  400  comprises a fifth transistor T 5 . The fifth transistor T 5  comprises a fifth control terminal, a fifth input terminal, and a fifth output terminal. The fifth control terminal receives a start pulse ST(n−3) at the (n−3)th stage. The fifth input terminal is connected to the fifth control terminal. The fifth output terminal is connected to the gate signal node Q(n). 
     The first pull-down holding circuit  500  comprises a sixth transistor T 6 , a seventh transistor T 7 , an eighth transistor T 8 , a ninth transistor T 9 , a tenth transistor T 10 , an eleventh transistor T 44 , and a twelfth transistor T 41 . 
     The sixth transistor T 6  comprises a sixth control terminal, a sixth input terminal, and a sixth output terminal. The sixth control terminal receives a start pulse ST(n+3) at the (n+3)th stage. The sixth input terminal is connected to the direct current low supply voltage Vss. The sixth output terminal is connected to the gate signal node Q(n). The seventh transistor T 7  comprises a seventh control terminal, a seventh input terminal, and a seventh output terminal. The seventh control terminal is connected to the gate signal node Q(n). The seventh input terminal is connected to the direct current low supply voltage Vss. The eighth transistor T 8  comprises an eighth control terminal, an eighth input terminal, and an eighth output terminal. The eighth control terminal is connected to a direct current high supply voltage VDD. The eighth output terminal is connected to the eighth control terminal. The eighth input terminal is connected to the seventh output terminal. The ninth transistor T 9  comprises a ninth control terminal, a ninth input terminal, and a ninth output terminal. The ninth control terminal is connected to the gate signal node Q(n). The ninth input terminal is connected to the direct current low supply voltage Vss. The tenth transistor T 10  comprises a tenth control terminal, a tenth input terminal, and a tenth output terminal. The tenth control terminal is connected to the seventh output terminal. The tenth input terminal is connected to the ninth output terminal. The tenth output terminal is connected to the eighth output terminal. The eleventh transistor T 44  comprises an eleventh control terminal, an eleventh input terminal, and an eleventh output terminal. The eleventh control terminal is connected to the tenth input terminal. The eleventh input terminal is connected to the direct current low supply voltage Vss. The eleventh output terminal is connected to the gate signal node Q(n). The twelfth transistor T 45  comprises a twelfth control terminal, a twelfth input terminal, and a twelfth output terminal. The twelfth control terminal is connected to the tenth input terminal. The twelfth input terminal is connected to the direct current low supply voltage Vss. The twelfth output terminal outputs the start pulse ST(n) at the nth stage. 
     The pull-down circuit  200  comprises a thirteenth transistor T 41 , a fourteenth transistor T 311 , a fifteenth transistor T 312 , a sixteenth transistor T 42 , a seventeenth transistor T 321 , an eighteenth transistor T 322 , a nineteenth transistor T 43 , a twentieth transistor T 331 , and a twenty-first transistor T 332 . 
     The thirteenth transistor T 41  comprises a thirteenth control terminal, a thirteenth input terminal, and a thirteenth output terminal. The thirteenth control terminal is connected to the first pull-down holding circuit  500 . The thirteenth input terminal is connected to the direct current low supply voltage Vss. The thirteenth output terminal is connected to the nth scan line G(n). The fourteenth transistor T 311  comprises a fourteenth control terminal, a fourteenth input terminal, and a fourteenth output terminal. The fourteenth control terminal is connected to the second clock CK 2 . The fourteenth input terminal is connected to the direct current low supply voltage Vss. The fourteenth output terminal is connected to the nth scan line G(n). The fifteenth transistor T 312  comprises a fifteenth control terminal, a fifteenth input terminal, and a fifteenth output terminal. The fifteenth control terminal is connected to the fourth clock signal CK 4 . The fifteenth input terminal is connected to the direct current low supply voltage Vss. The fifteenth output terminal is connected to the nth scan line G(n). The sixteenth transistor T 42  comprises a sixteenth control terminal, a sixteenth input terminal, and a sixteenth output terminal. The sixteenth control terminal is connected to the first pull-down holding circuit  500 . The sixteenth input terminal is connected to the direct current low supply voltage Vss. The sixteenth output terminal is connected to the scan line G(n+1). The seventeenth transistor T 321  comprises a seventeenth control terminal, a seventeenth input terminal, and a seventeenth output terminal. The seventeenth control terminal is connected to the third clock signal CK 3 . The seventeenth input terminal is connected to the direct current low supply voltage Vss. The seventeenth output terminal is connected to the scan line G(n+1). The eighteenth transistor T 322  comprises an eighteenth control terminal, an eighteenth input terminal, and an eighteenth output terminal. The eighteenth control terminal is connected to the fifth clock signal CK 5 . The eighteenth input terminal is connected to the direct current low supply voltage Vss. The eighteenth output terminal is connected to the scan line G(n+1). The nineteenth transistor T 43  comprises a nineteenth control terminal, a nineteenth input terminal, and a nineteenth output terminal. The nineteenth control terminal is connected to the first pull-down holding circuit  500 . The nineteenth input terminal is connected to the direct current low supply voltage Vss. The nineteenth output terminal is connected to the scan line G(n+2). The twentieth transistor T 331  comprises a twentieth control terminal, a twentieth input terminal, and a twentieth output terminal. The twentieth control terminal is connected to the fourth clock signal CK 4 . The twentieth input terminal is connected to the direct current low supply voltage Vss. The twentieth output terminal is connected to the scan line G(n+2). The twenty-first transistor T 332  comprises a twenty-first control terminal, a twenty-first input terminal, and a twenty-first output terminal. The twenty-first control terminal is connected to the sixth clock signal CK 6 . The twenty-first input terminal is connected to the direct current low supply voltage Vss. The twenty-first output terminal is connected to the scan line G(n+2). 
     The input terminal of the first transistor T 11 , the input terminal of the second transistor T 21 , the input terminal of the third transistor T 22 , and the input terminal of the fourth transistor T 23  are all connected to the first clock signal CK 1 . The control terminal (the gate) of the first transistor T 11 , the control terminal (the gate) of the second transistor T 21 , the control terminal (the gate) of the third transistor T 22 , and the control terminal (the gate) of the fourth transistor T 23  are all connected to the gate signal node Q(n). The first transistor T 11  is used for outputting the start pulse ST(n) at the nth stage for the GOA circuit at the next stage. The second transistor T 21 , the third transistor T 22 , and the fourth transistor T 23  correspond to the output of three gate lines G(n), G(n+1), and G(n+2) at the home stage. As for the nth scan line G(n), the control terminal (the gate) of the fourteenth transistor T 311  and the control terminal (the gate) of the fifteenth transistor T 312  are controlled by the second clock CK 2  and the fourth clock CK 4 , respectively. The fourteenth transistor T 311  and the fifteenth transistor T 312  are used for pulling down the signal at the scanning signal at the nth stage G(n) at different periods of time. After the second transistor T 21 , the third transistor T 22 , and the fourth transistor T 23  are connected to the first clock signal CK 1 , their outputs are the same. Gate pulse signals from the three gate lines G(n), G(n+1), and G(n+2) do not overlap. So the signals output by the second transistor T 21 , the third transistor T 22 , and the fourth transistor T 23  need to be pulled down in an appropriate period of time. The pull-down of the nth scan line G(n) has been detailed above. The pull-down of the scan line G(n+1) is completed with the seventeenth transistor T 321  and the eighteenth transistor T 322 . The seventeenth transistor T 321  and the eighteenth transistor T 322  are controlled by the third clock signal CK 3  and the fifth clock signal CK 5 . The pull-down of the scan line G(n+2) is completed with the twentieth transistor T 331  and the twentieth-first transistor T 332 . The twentieth transistor T 331  and the twentieth-first transistor T 332  are controlled by the fourth clock signal CK 4  and the sixth clock signal CK 6 . The twentieth transistor T 331  and the twentieth-first transistor T 332  work with the second transistor T 21 , the third transistor T 22 , and the fourth transistor T 23 . It ensures that the three gate lines which the GOA circuit at the stage  35  corresponds to output the correct waveforms. The thirteenth transistor T 41 , the sixteenth transistor T 42 , and the nineteenth transistor T 43  are used for pulling down the three gate lines. The function of these transistors is to pull down the signals output through the nth scan line G(n), the scan line G(n+1), and the scan line G(n+2) to ensure that the output at low voltage level when the GOA circuit at the stage  35  does not work, that is, the gate signal node Q(n) at low voltage level. When the GOA circuit at the stage  35  outputs, that is, the gate signal node Q(n) at high voltage level, the control terminals (the gate) of the thirteenth transistor T 41 , the sixteenth transistor T 42 , and the nineteenth transistor T 43  are at low voltage level. The control terminals are closed. There is no influence on the output of the nth scan line G(n), the scan line G(n+1), and the scan line G(n+2). The eleventh transistor T 44  and the thirteenth transistor T 41  are also used for pulling down signals. When the GOA circuit at the stage  35  does not output, the start pulse ST and the gate signal node Q(n) keep at low voltage level. 
     The GOA circuit  35  proposed by this embodiment can output signals from three gate lines, so it is good for increasing the height of layout, narrowing down the width, and designing narrow bezels. In addition, the GOA circuit  35  at each stage comprises twenty-one transistors. On contrast, the conventional GOA circuit  25  as shown in  FIG. 2  comprises fifty-one TFTs since three gate lines needs the GOA circuit  25  at three stages. Therefore, the GOA circuit  35  needs much smaller space than the conventional GOA circuit  25  does. 
       FIG. 5  is a circuit diagram of a GOA circuit  40  according to a second preferred embodiment of the present invention. A clear distinction between the second preferred embodiment and the first preferred embodiment is the use of different signals for connections. The details are as follows: 
     A start pulse ST advances three stages, that is, changing n−3 for n, changing n for n+3, and changing n+3 for n+6. 
     In the second preferred embodiment, the input terminals of a first transistor T 11 , a second transistor T 21 , a third transistor T 22 , and a fourth transistor T 23  are connected to a fourth clock signal CK 4 . The output terminal of the second transistor T 21 , the output terminal of the third transistor T 22 , and the output terminal of the fourth transistor T 23  are connected to a scan line G(n+3), a scan line G(n+4), and a scan line G(n+5), respectively. 
     The control terminal of a fourteenth transistor T 311  is connected to a first clock signal CK 1 . The control terminal of a fifteenth transistor T 312  is connected to a third clock signal CK 3 . The output terminals of the fourteenth transistor T 311  and the fifteenth transistor T 312  are connected to the scan line G(n+3). 
     The control terminal of a seventeenth transistor T 321  is connected to a second clock signal CK 2 . The control terminal of an eighteenth transistor T 322  is connected to a fourth clock signal CK 4 . The output terminals of the seventeenth transistor T 321  and the eighteenth transistor T 322  are connected to the scan line G(n+4). 
     The control terminal of a twenty T 331  is connected to the third clock signal CK 3 . The control terminal of a twenty-first T 332  is connected to a fifth clock signal CK 5 . The output terminals of the twenty T 331  and the twenty-first T 332  are connected to the scan line G(n+5). 
     Compared with the first preferred embodiment where the scan lines at odd stages are driven, the scan lines at even stages are driven in the second preferred embodiment. That&#39;s the difference between the two embodiments. 
       FIG. 6  is a waveform diagram of the GOA circuit shown in  FIG. 4  and  FIG. 5 . The cycle of the first clock signal CK 1 , the cycle of the second clock signal CK 2 , and the cycle of the third clock signal CK 3  are the same. Also, the first clock signal CK 1 , the second clock signal CK 2 , and the third clock signal CK 3  are enabled subsequently based on the difference of a ⅓ cycle. The fourth clock signal CK 4 , the fifth clock signal CK 5 , and the sixth clock signal CK 6  are inverting signals of the first clock signal CK 1 , the second clock signal CK 2 , and the third clock signal CK 3 , respectively. Therefore, signals for enabling the scan lines (from the nth stage to the (n+5)th stage) subsequently are obtained. 
       FIG. 7  is a circuit diagram of the structure of a GOA circuit  50  according to a third preferred embodiment of the present invention. Compared with the first preferred embodiment, a second pull-down holding circuit comprising a twenty-second transistor T 91  and a twenty-three transistor T 92  is added in the third preferred embodiment. That&#39;s the difference between the two embodiments. 
     The twenty-second transistor T 91  comprises a twenty-second control terminal, a twenty-second input terminal, and a twenty-second output terminal. The twenty-second control terminal is connected to a fourth clock signal CK 4 . The twenty-second input terminal is connected to a direct current low supply voltage Vss. The twenty-second output terminal is connected to a gate signal node Q(n). The twenty-third transistor T 92  comprises a twenty-third control terminal, a twenty-third input terminal, and a twenty-third output terminal. The twenty-third control terminal is connected to the fourth clock signal CK 4 . The twenty-third input terminal is connected to the direct current low supply voltage Vss. The twenty-third output terminal is connected to a start pulse ST(n) at the nth stage. 
     The GOA circuit  55  at each stage adopts two pairs of pull-down holding circuit ( 500 , 600 ). The pairs of pull-down holding circuit ( 500 , 600 ) are pulled down at different time slots. In this way, the transistors in the pairs of pull-down holding circuit ( 500 , 600 ) do not need to bear long-time stress. Electrical drift, which may results in ineffectiveness of the GOA circuit  55 , does not occur, either. Accordingly, the stability of the LCD panel is greatly improved. 
     When the GOA circuit  55  performs outputting, i.e., the gate signal node Q(n) at high voltage level, the two pairs of pull-down holding circuit ( 500 , 600 ) do not work, ensuring that correct waveforms are output through the corresponding gate lines. When the GOA circuit  55  does not output, i.e., the gate signal node Q(n) at low voltage level, the two pairs of pull-down holding circuit ( 500 , 600 ) pull down alternatively. When the first clock signal CK 1  is at high voltage level and the fourth clock signal CK 4  is at low voltage level, the first clock signal CK 1  is connected to the nth scan line G(n), the scan line G(n+1), and the scan line G(n+2) through the second transistor T 21 , the third transistor T 22 , and the fourth transistor T 23 , respectively. The nth scan line G(n), the scan line G(n+1), and the scan line G(n+2) are pulled down to enhance the stability of the GOA circuit. In the meantime, the gate signal node Q(n) and the start pulse ST need to be pulled down as well. Such an operation mode is identical to the operation mode of the GOA circuit in the first preferred embodiment. When the first clock signal CK 1  is at low voltage level and the fourth clock signal CK 4  is at high voltage level, the twenty-second transistor T 91  and the twenty-third transistor T 92  are forced to be turned on. The gate signal node Q(n) and the start pulse ST are be pulled down. Meanwhile, the first clock signal CK 1  is at low voltage level so the corresponding nth scan line G(n), the corresponding scan line at the (n+1)th stage G(n+1), and the corresponding scan line at the (n+2)th stage G(n+2) are also at low voltage level even though the second transistor T 21 , the third transistor T 22 , and the fourth transistor T 23  leak electricity. There is no influence on the output of the nth scan line G(n), the scan line G(n+1), and the scan line G(n+2). So the nth scan line G(n), the scan line G(n+1), and the scan line G(n+2) do not need to be pulled down. 
       FIG. 8  is a circuit diagram of the structure of a GOA circuit  60  according to a fourth preferred embodiment of the present invention. A clear distinction between the fourth preferred embodiment and the third preferred embodiment is the use of different signals for connections. The details are as follows: 
     A start pulse ST advances three stages, that is, changing n−3 for n, changing n for n+3, and changing n+3 for n+6. 
     In the fourth preferred embodiment, the input terminals of a first transistor T 11 , a second transistor T 21 , a third transistor T 22 , and a fourth transistor T 23  are connected to a fourth clock signal CK 4 . The output terminal of the second transistor T 21 , the output terminal of the third transistor T 22 , and the output terminal of the fourth transistor T 23  are connected to a scan line G(n+3), a scan line G(n+4), and a scan line G(n+5), respectively. 
     The control terminal of a fourteenth transistor T 311  is connected to a first clock signal CK 1 . The control terminal of a fifteenth transistor T 312  is connected to a third clock signal CK 3 . The output terminals of the fourteenth transistor T 311  and the fifteenth transistor T 312  are connected to the scan line G(n+3). 
     The control terminal of a seventeenth transistor T 321  is connected to a second clock signal CK 2 . The control terminal of an eighteenth transistor T 322  is connected to a fourth clock signal CK 4 . The output terminals of the seventeenth transistor T 321  and the eighteenth transistor T 322  are connected to the scan line G(n+4). 
     The control terminal of a twenty T 331  is connected to the third clock signal CK 3 . The control terminal of a twenty-first T 332  is connected to a fifth clock signal CK 5 . The output terminals of the twenty T 331  and the twenty-first T 332  are connected to the scan line G(n+5). 
     The control terminals of a twenty-second transistor T 91  and a twenty-three transistor T 92  are connected to the first clock signal CK 1 . 
     Compared with the third preferred embodiment where the scan lines at odd stages are driven, the scan lines at even stages are driven in the fourth preferred embodiment. That&#39;s the difference between the two embodiments. 
     While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements made without departing from the scope of the broadest interpretation of the appended claims.