Abstract:
In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material.

Description:
BACKGROUND 
       [0001]    The present disclosure relates generally to the field of semiconductor devices and methods for fabrication, and more particularly to semiconductor via-fuses that have predictable fail locations. Semiconductor device fabrication is a multi-step process involving front-end-of-line (hereinafter “FEOL”) processing wherein the formation of individual devices, such as transistors, directly in a silicon wafer occurs and back end of line (hereinafter “BEOL”) processing wherein individual devices, for example, transistors, with wiring on the silicon wafer. BEOL generally begins when the first layer of metal wiring is deposited on the silicon wafer. 
         [0002]    An electrical fuse (hereinafter “efuse”) is a common one time programmable device. Horizontal efuses are typically formed in the FEOL with a silicided gate polycrystalline silicon electrode material. Vertical efuses are typically formed in the BEOL using the same interconnection materials (lines and vias) as non-fuse areas. Efuses can be programmed to increase their resistance compared to unprogrammed efuses, which remain in a low resistance state. Programming is accomplished by controlling electromigration (hereinafter “EM”) of the fuse link from the anode to the cathode by one time complementary metal-oxide semiconductor activation. Ideally, a vertical e-fuse will blow in the via, however, current vertical efuse structures have unpredictable fail locations, which can affect the repeatability and reliability of BEOL via-fuse structures. 
       SUMMARY 
       [0003]    Embodiments for the present invention provide a semiconductor device and methods for In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0004]      FIG. 1A  illustrates a BEOL having a fuse and non-fuse, in accordance with an embodiment of the present invention. 
           [0005]      FIG. 1B  depicts fabrication steps, in accordance with an embodiment of the present invention. 
           [0006]      FIG. 2  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0007]      FIG. 3  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0008]      FIG. 4  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0009]      FIG. 5  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0010]      FIG. 6A  illustrates a BEOL having a fuse and non-fuse area, in accordance with an embodiment of the present invention. 
           [0011]      FIG. 6B  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0012]      FIG. 7  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0013]      FIG. 8  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0014]      FIG. 9  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0015]      FIG. 10  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0016]      FIG. 11  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
           [0017]      FIG. 12  depicts additional fabrication steps, in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    The present disclosure relates generally to the field of semiconductor devices and methods of fabrication, and more particularly to vertical electrical fuses that have predictable fail locations. The invention described herein is directed to vertical efuses having predictable locations where voids may form. Specifically, the invention described herein utilizes porous dielectric material proximate to the via of the fuse, which leads to at least one of a weak mechanical environment, poor heat dissipation, and weak liner coverage which promotes EM failure and subsequent void formation. 
       Structure 
       [0019]      FIG. 1A  illustrates a BEOL having a fuse and non-fuse area, in accordance with an embodiment of the present invention. Referring to the fuse area, the via portion thereof is partially formed in porous low-K dielectric material that has a lower dielectric constant compared to the low-K dielectric material that the line portion of the efuse is formed in. This is in contrast to typical non-fuse areas in which, if there is a different material in the via and line portions of the fuse, the line portion will have the lower-k material. Here, in the efuse portion of the BEOL, the lower-k of the via portion relative to the line portion has several advantages. First, the lower mechanical strength of the porous low-k material relative to the higher-K material aids in blowing the fuse. Second, the porous lower-k material will likely etch faster than the higher-K material of the line portion, which will result in a bowing out (wider) fuse, which will cause the liner coverage to be poor and aid in the blowing of the fuse. 
         [0020]    Still referring to  FIG. 1A , referring to the non-fuse area, the via portion thereof is formed in dense material that has a higher dielectric constant compared to the dense material that the line portion is formed in. However, the via and line portions can include the same dense material. 
       Method 
       [0021]      FIGS. 1B-5  describe an embodiment for fabricating the vertical efuse of  FIG. 1A .  FIG. 1B  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Referring to  FIG. 1B , capping layer  112  is deposited on substrate  115 , which includes insulator dielectric material, such as organosilicate. Capping layer  112  includes insulator material, such as silicon nitride. First dielectric  110  is deposited on substrate  115  using an appropriate deposition process, such as physical vapor deposition (hereinafter “PVD”), plasma assisted chemical vapor deposition (hereinafter “PACVD), chemical vapor deposition (hereinafter “CVD), electrochemical deposition (hereinafter “ED”), molecular beam epitaxy (hereinafter “MBE), or atomic layer deposition (hereinafter “ALD”). In an embodiment, first dielectric  110  is deposited on substrate  115  with a thickness comparable to the height of the via portion of the via-fuse (discussed below). In another embodiment, first dielectric  110  is a dense dielectric that includes a porogen, such as porous organosilicate, organosilicate or octamethylcyclotetrasiloxane. In certain embodiments, first dielectric  110  has a dielectric constant in the range of about less than 4.0 to about 2.0. Excess first dielectric  110  is removed utilizing an appropriate removal process, such as wet or dry etching and/or chemical-mechanical planarization. 
         [0022]      FIG. 2  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Photoresist  210  is deposited on areas of first dielectric  110 , for example, by a high speed spinning, that are not to have increased porosity undergo porous conversion. Photoresist  210  can be an ultraviolet (hereinafter “UV”) light resistant material. UV radiation is applied to the resulting structure to increase the porosity of exposed areas of first dielectric  110  by interacting with the included porogen. Subsequent to UV application, photoresist  210  is removed, for example, by chemical mechanical polishing, an appropriate chemical solution, or oxygen plasma etching. 
         [0023]      FIG. 3  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Excess first dielectric  110  can be removed, for example, by chemical-mechanical planarization (hereinafter “CMP”). In an embodiment, excess first dielectric  110  is removed such that the UV exposed portion of first dielectric  110  is co-planar with the non-UV exposed portion thereof. In another embodiment, excess first dielectric  110  is removed such that the UV exposed portion of first dielectric  110  is not co-planar with the non-UV exposed portion thereof. Second dielectric  310  is deposited on first dielectric  110  using an appropriate deposition technique (discussed above). Second dielectric  310  is a low-K dielectric material, such as silicon dioxide and polyamide. In an embodiment, first dielectric  110  and second dielectric  310  include the same low-K dielectric material. In another embodiment, first dielectric  110  and second dielectric  310  include different low-K dielectric material. In other embodiments, first dielectric  110  has a lower dielectric constant compared to second dielectric  310 . 
         [0024]      FIG. 4  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Specifically,  FIG. 4  depicts a metal patterning process, for example, a dual damascene patterning, performed by conventional lithography and etching techniques. Dual damascene patterning is characterized by patterning vias and trenches (also referred to as “lines”) in such a way that the metal deposition fills both at the same time. The metal patterning results in damascene trenches  410  and  420 , which both traverse first dielectric  110  and second dielectric  310 . The pattering also results in barrier layers  430 , which include barrier materials, such as tantalum, tantalum-nitride, titanium-nitride, and titanium-tungsten. Barrier layers  430  are deposited using an appropriate deposition process, such as sputter deposition.  FIG. 5  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Metal layers  520  and  530 , which include conductive material, such as copper, is deposited in damascene trenches  410  and  420  using an appropriate deposition technique, such as electroplating. 
         [0025]    Capping layer  510  is deposited on second dielectric  310  using an appropriate deposition technique (discussed above). In an embodiment, capping layer  510  includes insulator material, such as silicone nitride. 
       Structure 
       [0026]      FIG. 6A  illustrates a BEOL having a fuse and non-fuse area according to an embodiment of the present invention. Referring to the fuse area, the via portion thereof is partially formed in low-K dielectric material and porous low-k dielectric material, wherein the porous low-K dielectric material has a lower dielectric constant compared to the low-K dielectric material that the line portion of the efuse is formed in. This is in contrast to typical non-fuse areas in which, if there is a different dielectric material in the via and line portions of the fuse, the line portion will have the lower-K dielectric material. Here, in the efuse portion of the BEOL, the lower-k of the via portion relative to the line portion has several advantages. 
         [0027]    First, the lower mechanical strength of the porous low-K dielectric material relative to the higher-K dielectric material aids in blowing the fuse. Second, the porous lower-K dielectric material will likely etch faster than the higher-K dielectric material of the line portion, which will result in a bowing out (wider) fuse, which will cause the liner coverage to be poor and aid in the blowing of the fuse. Still referring to Fig. B, as per the non-fuse are, the via portion thereof is formed in dense dielectric material that has a higher dielectric constant compared to the dense dielectric material that the line portion is formed in. However, the via and line portions can include the same dense dielectric material. 
       Method 
       [0028]      FIGS. 6B-12  describe an embodiment for fabricating the vertical efuse of  FIG. 6A .  FIG. 6  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Referring to  FIG. 6 , capping layer  612  is deposited on substrate  610  using an appropriate deposition process (discussed above). First dielectric  615  is deposited on capping layer  612  utilizing an appropriate deposition process (discussed above). In an embodiment, first dielectric  615  is deposited on substrate  610  to a thickness comparable to the height of the via of the via-fuse structure (discussed below). In an embodiment, first dielectric  615  is a low-K dielectric material. Hard mask  620  is deposited on first dielectric  615  by an appropriate deposition process. 
         [0029]      FIG. 7  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Photoresist  710  is deposited on non-porous portions of hard mask  620  by, for example, high speed spinning. Areas of hard mask  620  not covered by photoresist  710  correspond to porous areas of the structure that will include a via-fuse (hereinafter “via-fuse area”). The via-fuse area is patterned and/or etched out by, for example, an etch using hydrofluoric acid.  FIG. 8  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Photoresist  710  is removed using an appropriate removal process using, for example, an appropriate chemical solution or an oxygen plasma system. Second dielectric  810  is deposited on hard mask  620  and first dielectric  615  using an appropriate deposition method. In an embodiment, second dielectric  810  includes a porous inter-level dielectric film, such as porous organosilicate. 
         [0030]      FIG. 9  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Hard mask  620  and excess second dielectric  810  are removed using an appropriate removal process, for example, CMP. In certain embodiments, excess second dielectric  810  is removed such that first dielectric  615  is co-planar with second dielectric  810 . In other embodiments, excess second dielectric  810  is removed such that first dielectric  615  is not co-planar with second dielectric  810 .  FIG. 10  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Third dielectric  1010  is deposited on first dielectric  615  and second dielectric  810  to a predetermined thickness using an appropriate deposition technique. Third dielectric  1010  includes a low-K dielectric material. In an embodiment, first dielectric  615  and third dielectric  1010  are comprised of the same low-K dielectric material. 
         [0031]      FIG. 11  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Damascene trenches  1115  are formed in structure  1000  by dual damascene processing. Diffusion layers  1110  are deposited in trenches  1115  using an appropriate deposition process. 
         [0032]      FIG. 12  depicts additional fabrication steps, in accordance with an embodiment of the present invention. Metal layers  1220  are deposited in trenches  1115  using an appropriate deposition process (discussed above). Metal layers  1220  include a conductive material, such as copper and/or aluminum. In an embodiment, excess material is removed from metal layers  1220  by an appropriate polishing method. Capping layer  1210  is deposited on third dielectric  1010  and trenches  1115  using an appropriate deposition technique. In other embodiments, capping layer  1210  includes insulator material, such as silicone nitride.