Abstract:
A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.

Description:
FIELD 
       [0001]    This disclosure relates generally to the field of formation of silicide contacts for semiconductor devices. 
       DESCRIPTION OF RELATED ART 
       [0002]    A semiconductor device, such as a field effect transistor (FET), may comprise one or more contacts that are used to apply electrical voltage to the semiconductor device in order to power the device. As semiconductor devices become smaller and smaller, the contacts also need to be made commensurately thinner in size. Semiconductor devices comprising 3-dimensional structures may also require conformal formation of ultra-thin silicide contacts. 
       SUMMARY 
       [0003]    In one aspect, a method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. 
         [0004]    In one aspect, a semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less. 
         [0005]    Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0006]    Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
           [0007]      FIG. 1  illustrates an embodiment of a method for formation of a silicide contact. 
           [0008]      FIG. 2  illustrates an embodiment of a metal layer deposited on silicon. 
           [0009]      FIG. 3  illustrates an embodiment of the device of  FIG. 2  after formation of a intermixed layer between the metal layer and the silicon. 
           [0010]      FIG. 4  illustrates an embodiment of the device of  FIG. 3  after removal of the unintermixed metal layer from the intermixed layer. 
           [0011]      FIG. 5  illustrates an embodiment of a silicide contact after annealing. 
           [0012]      FIG. 6  illustrates an embodiment of a metal layer deposited on 3-D structured silicon on buried oxide. 
           [0013]      FIG. 7  illustrates an embodiment of the device of  FIG. 6  after formation of a intermixed layer between the metal layer and the silicon. 
           [0014]      FIG. 8  illustrates an embodiment of the device of  FIG. 7  after removal of the unintermixed metal layer from the intermixed layer. 
           [0015]      FIG. 9  illustrates an embodiment of conformal silicide contacts after annealing. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    Embodiments of silicide contacts and methods of forming silicide contacts are provided, with exemplary embodiments being discussed below in detail. A contact for a semiconductor device may comprise a layer of silicide. Semiconductor device scaling requires silicide contact scaling, which calls for formation of extremely thin silicide films for use as contacts. A silicide contact may be formed by sputtering of metal on silicon, annealing to cause the metal and silicon to react, and then removing any unreacted metal. However, it is very difficult to form a conformal silicide due to the poor conformality of the sputtered metal film, especially when the metal thickness is extremely thin. A thin silicide contact having appropriate sheet resistance, composition, phase formation, morphology and thermal stability may be formed by deposition of an appropriate metal on silicon to form an intermixed region between the metal and the silicon, removing any unintermixed metal from the intermixed region, and annealing the intermixed region to form the low resistive phase silicide contact. Formation of the intermixed region is a self-limiting process, and results in a silicide contact having a good conformality and uniformity. 
         [0017]      FIG. 1  illustrates an embodiment of a method of forming a thin silicide contact.  FIG. 1  is discussed with reference to  FIGS. 2-5 . In block  101 , a metal layer  202  is deposited on silicon  201 , as is shown in  FIG. 2 . Silicon  201  may comprise any silicon portion of any type semiconductor device that requires a contact in operation, and may comprise silicon-on-insulator (SOI) in some embodiments. Metal layer  202  may comprise nickel (Ni) or nickel platinum (NiPt) in some embodiments; if metal layer  202  comprises NiPt, the NiPt may comprise about 10% Pt in some embodiments. In block  102 , metal layer  202  and silicon  201  intermix to form intermixed region  301  and unintermixed metal layer  302  on silicon  201 , as shown in  FIG. 3 . The intermixed region  301  forms automatically just after the metal deposition; intermixing of metal layer  202  and silicon  201  is a self-limiting process. In block  103 , the unintermixed metal layer  302  is stripped, leaving intermixed region  301  on silicon  201 , as shown in  FIG. 4 . In block  104 , the intermixed region  301  and silicon  201  of  FIG. 4  are annealed, resulting in silicide contact  501  on silicon  201 , as shown in  FIG. 5 . Silicide contact  501  comprises NiSi or NiPtSi in some embodiments. Silicide contact  501  may be used as an electrical contact for any appropriate semiconductor device, such as a MOSFET. A semiconductor device may comprise any appropriate number of silicide contacts. 
         [0018]      FIGS. 6-9  illustrate another embodiment of application of the method  100  of  FIG. 1  for conformal formation of silicide contacts on a 3-dimensional silicon structure. In block  101 , a metal layer  603  is deposited on 3-dimensional silicon  602 A-C, which is located on buried oxide  601 , as is shown in  FIG. 6 . Metal layer  603  may comprise nickel (Ni) or nickel platinum (NiPt) in some embodiments; if metal layer  603  comprises NiPt, the NiPt may comprise between about 10% Pt in some embodiments. In block  102 , metal layer  603  and silicon  602 A-C intermix to form intermixed regions  701 A-C and unintermixed metal layer  702  on silicon  602 A-C and buried oxide  601 , as shown in  FIG. 7 . The intermixed regions  701 A-C forms automatically just after the metal deposition; intermixing of metal layer  603  and silicon  602 A-C is a self-limiting process. In block  103 , the unintermixed metal layer  702  is stripped, leaving intermixed regions  701 A-C on silicon  602 A-C, as shown in  FIG. 8 . In block  104 , the intermixed regions  701 A-C are annealed, resulting in conformal silicide contacts  901 A-C on 3-dimensional silicon structure  602 A-C, as shown in  FIG. 9 . Silicide contacts  701 A-C comprise NiSi or NiPtSi in some embodiments. Silicide contacts  701 A-C may be used as an electrical contact for any appropriate semiconductor device, such as a MOSFET. A semiconductor device may comprise any appropriate number of silicide contacts. 
         [0019]    The thickness of silicon  201  may have relatively little effect on the qualities (such as thickness and resistance) of silicide contact  501 ; however, the composition and thickness of metal layer  202  may cause wide variation in the thickness and resistance of silicide contact  501 . Use of Ni for metal layer  202  may result in a silicide contact  501  that is epitaxial and has relatively good thermal stability, and also has a relatively uniform thickness. Use of Ni5% Pt for metal layer  202  may result in a silicide contact  501  that is not epitaxial, and may have poor uniformity in thickness. Use of Ni10% Pt may result in a non-epitaxial silicide contact  501  that may have better uniformity of thickness than a contact formed using a metal layer of Ni. 
         [0020]    Table 1 below lists Ni amounts (in thicknesses) in the intermixed region that may result from depositing various thicknesses and compositions of metal layer onto silicon. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Deposited Metal layer 
                 Metal target 
                 Ni amount 
               
               
                 thickness 
                 composition (atm. %) 
                 in the intermix 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 1 
                 nanometer (nm) 
                 Ni 
                 about 10 angstroms (A) 
               
               
                 1 
                 nm 
                 Ni5% Pt 
                 about 11 A 
               
               
                 1 
                 nm 
                 Ni10% Pt 
                 about 11 A 
               
               
                 2 
                 nm 
                 Ni 
                 about 16 A 
               
               
                 2 
                 nm 
                 Ni5% Pt 
                 about 20 A 
               
               
                 2 
                 nm 
                 Ni10% Pt 
                 about 21 A 
               
               
                 4 
                 nm 
                 Ni 
                 about 16 A 
               
               
                 4 
                 nm 
                 Ni5% Pt 
                 about 14 A 
               
               
                 4 
                 nm 
                 Ni10% Pt 
                 about 14 A 
               
               
                 6 
                 nm 
                 Ni 
                 about 16 A 
               
               
                 6 
                 nm 
                 Ni5% Pt 
                 about 14 A 
               
               
                 6 
                 nm 
                 Ni10% Pt 
                 about 14 A 
               
               
                 8 
                 nm 
                 Ni 
                 about 15 A 
               
               
                 8 
                 nm 
                 Ni5% Pt 
                 about 14 A 
               
               
                 8 
                 nm 
                 Ni10% Pt 
                 about 15 A 
               
               
                 10 
                 nm 
                 Ni 
                 about 16 A 
               
               
                 10 
                 nm 
                 Ni5% Pt 
                 about 14 A 
               
               
                 10 
                 nm 
                 Ni10% Pt 
                 about 15 A 
               
               
                 15 
                 nm 
                 Ni 
                 about 17 A 
               
               
                 15 
                 nm 
                 Ni5% Pt 
                 about 13 A 
               
               
                 15 
                 nm 
                 Ni10% Pt 
                 about 15 A 
               
               
                 20 
                 nm 
                 Ni 
                 about 17 A 
               
               
                 20 
                 nm 
                 Ni5% Pt 
                 about 13 A 
               
               
                 20 
                 nm 
                 Ni10% Pt 
                 about 15 A 
               
               
                   
               
             
          
         
       
     
         [0021]    Table 2 below lists percentages of Pt in the intermixed region that may result from various thicknesses and compositions of the metal layer. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 Deposited 
                 Metal target 
                   
               
               
                 Metal layer thickness 
                 composition (atm. %) 
                 Intermixed region % Pt 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 1 
                 nm 
                 Ni5% Pt 
                 about 4.5% 
               
               
                 1 
                 nm 
                 Ni10% Pt 
                 about 7% 
               
               
                 2 
                 nm 
                 Ni5% Pt 
                 about 3.8% 
               
               
                 2 
                 nm 
                 Ni10% Pt 
                 about 7% 
               
               
                 4 
                 nm 
                 Ni5% Pt 
                 about 9% 
               
               
                 4 
                 nm 
                 Ni10% Pt 
                 about 16% 
               
               
                 6 
                 nm 
                 Ni5% Pt 
                 about 11% 
               
               
                 6 
                 nm 
                 Ni10% Pt 
                 about 15.5% 
               
               
                 8 
                 nm 
                 Ni5% Pt 
                 about 9.5% 
               
               
                 8 
                 nm 
                 Ni10% Pt 
                 about 16% 
               
               
                 10 
                 nm 
                 Ni5% Pt 
                 about 11% 
               
               
                 10 
                 nm 
                 Ni10% Pt 
                 about 15.5% 
               
               
                 15 
                 nm 
                 Ni5% Pt 
                 about 11% 
               
               
                 15 
                 nm 
                 Ni10% Pt 
                 about 15.5% 
               
               
                 20 
                 nm 
                 Ni5% Pt 
                 about 9% 
               
               
                 20 
                 nm 
                 Ni10% Pt 
                 about 16% 
               
               
                   
               
             
          
         
       
     
         [0022]    Table 3 below lists sheet resistances of a silicide contact that may result from various thicknesses and compositions of the metal layer. A relatively low resistance for silicide contact is desirable for efficient operation of the semiconductor device comprising the silicide contact. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 Deposited 
                 Metal target  
                 Resistance of contact 
               
               
                 Metal layer thickness 
                 composition (atm. %) 
                 (Ω/□) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 1 
                 nm 
                 Ni 
                 about 250 
               
               
                 1 
                 nm 
                 Ni5% Pt 
                 about 350 
               
               
                 1 
                 nm 
                 Ni10% Pt 
                 about 510 
               
               
                 2 
                 nm 
                 Ni 
                 about 150 
               
               
                 2 
                 nm 
                 Ni5% Pt 
                 about 150 
               
               
                 2 
                 nm 
                 Ni10% Pt 
                 about 260 
               
               
                 4 
                 nm 
                 Ni 
                 about 150 
               
               
                 4 
                 nm 
                 Ni5% Pt 
                 about 225 
               
               
                 4 
                 nm 
                 Ni10% Pt 
                 about 200 
               
               
                 6 
                 nm 
                 Ni 
                 about 150 
               
               
                 6 
                 nm 
                 Ni5% Pt 
                 about 200 
               
               
                 6 
                 nm 
                 Ni10% Pt 
                 about 200 
               
               
                 8 
                 nm 
                 Ni 
                 about 150 
               
               
                 8 
                 nm 
                 Ni5% Pt 
                 about 370 
               
               
                 8 
                 nm 
                 Ni10% Pt 
                 about 200 
               
               
                 10 
                 nm 
                 Ni 
                 about 150 
               
               
                 10 
                 nm 
                 Ni5% Pt 
                 about 200 
               
               
                 10 
                 nm 
                 Ni10% Pt 
                 about 200 
               
               
                 15 
                 nm 
                 Ni 
                 about 150 
               
               
                 15 
                 nm 
                 Ni5% Pt 
                 about 350 
               
               
                 15 
                 nm 
                 Ni10% Pt 
                 about 200 
               
               
                 20 
                 nm 
                 Ni 
                 about 150 
               
               
                 20 
                 nm 
                 Ni5% Pt 
                 about 250 
               
               
                 20 
                 nm 
                 Ni10% Pt 
                 about 200 
               
               
                   
               
             
          
         
       
     
         [0023]    The technical effects and benefits of exemplary embodiments include conformal formation of a relatively thin silicide contact in a self-limiting way for use in a semiconductor device. 
         [0024]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0025]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.