Abstract:
A High-Voltage Stacked Transistor Circuit (HVSTC) includes a stack of power transistors coupled in series between a first terminal and a second terminal. The HVSTC also has a control terminal for turning on an off the power transistors of the stack. All of the power transistors of the stack turn on together, and turn off together, so that the overall stack operates like a single transistor having a higher breakdown voltage. Each power transistor, other than the one most directly coupled to the first terminal, has an associated bipolar transistor. In a static on state of the HVSTC, the bipolar transistors are off. The associated power transistors can therefore be turned on. In a static off state of the HVSTC, the bipolar transistors are conductive (in one example, in the reverse active mode) in such a way that they keep their associated power transistors off.

Description:
TECHNICAL FIELD 
     The described embodiments relate to power semiconductor devices. 
     BACKGROUND INFORMATION 
     In certain circuit applications, a power Field Effect Transistor (FET) switch is needed that can withstand a very high voltage between its drain and source terminals. The high voltage may be a voltage higher than any available power FET can withstand. Several different stacked circuits are known in which multiple power FETs are connected in a “stacked” or “chained” fashion. The drain of a power FET of the stack is coupled to the source of the power FET next higher in the stack. If all the power FETs of the stack are off, then a high voltage present across the entire stack may be shared more or less equally by the various power FETs. Due to this voltage divider effect, each power FET sees a lower V DS  voltage between its drain and source terminals. During switching of the overall circuit, if all the power FETs of the stack are turned on at the same time, then no one of the power FETs during turn on of the overall circuit will experience a V DS  drain-to-source voltage higher than its drain-to-source breakdown voltage (BV DS ). Likewise, during switching of the overall circuit, if all the power FETs are turned off at the same time, then no one of the power FETs during turn off of the overall circuit will experience a drain-to-source voltage higher than its drain-to-source BV DS  breakdown voltage. 
     SUMMARY 
     A High-Voltage Stacked Transistor Circuit (HVSTC) includes a stack of power transistors (for example, power N-channel enhancement-mode field effect transistors) coupled in series between a first terminal S and a second terminal D. The HVSTC also has a control input terminal G for receiving an input control signal. In response to a level of the input control signal on the input terminal G, the transistors of the stack are either turned on or are turned off. All of the power transistors of the stack are controlled to turn on together, and to turn off together, so that the overall stack operates like a single transistor having a higher breakdown voltage between the first and second terminals than any of its constituent power transistors. Each power transistor of the stack, other than the one coupled most directly to the first terminal S, has an associated bipolar transistor. In response to the input control signal being at a high voltage level (for example, ten volts with respect to first terminal S), the bipolar transistors are off and the HVSTC is in a static on state. Because the bipolar transistors are off, the associated power transistors can be turned on in response to the input control signal. In response to the input control signal being at a low voltage level (for example, zero volts with respect to first terminal S), the HVSTC is in a static off state. The bipolar transistors are conductive (in one example in the reverse active mode) in such a way that they keep their associated power transistors off. 
     Further details and embodiments and techniques are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, where like numerals indicate like components, illustrate embodiments of the invention. 
         FIG. 1  is a diagram of a system that employs a novel High-Voltage Stacked Transistor Circuit (HVSTC) in accordance with one novel aspect. 
         FIG. 2  is a circuit diagram of the HVSTC of  FIG. 1 . 
         FIG. 3  is a perspective view of the HVSTC of  FIG. 1 . 
         FIG. 4  illustrates an operation of the HVSTC of  FIG. 2  in a static on state. 
         FIG. 5  illustrates an operation of the HVSTC of  FIG. 2  in a static off state. 
         FIG. 6A  is a waveform diagram that illustrates operation of the HVSTC of  FIG. 2  when the circuit is turning on. 
         FIG. 6B  is a waveform diagram that illustrates operation of the HVSTC of  FIG. 2  when the circuit is turning on. 
         FIG. 7A  is a waveform diagram that illustrates operation of the HVSTC of  FIG. 2  when the circuit is turning off. 
         FIG. 7B  is a waveform diagram that illustrates operation of the HVSTC of  FIG. 2  when the circuit is turning off. 
         FIG. 8  is a diagram of an HVSTC that involves a stack of four power FETs. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to background examples and some embodiments of the invention, examples of which are illustrated in the accompanying drawings. 
       FIG. 1  is a diagram of a system  1  that employs a novel High-Voltage Stacked Transistor Circuit (HVSTC)  2 . System  1  is but one example of an application circuit that requires a switch that can withstand a very high voltage, such as 6500 volts, between its two switching terminals. The novel HVSTC  2  is such a switch. The novel HVSTC  2 , however, also sees use in many other circuits. System  1  of  FIG. 1  is but one example. 
     In system  1 , due to DC voltage source  3 , 24 volts DC is present on a supply voltage conductor  4  with respect to ground potential on a ground conductor  5 . A controller  6  is powered from the DC supply voltage. Based on a plurality of input signals  7  (for example, an air temperature input signal, an air speed input signal, an air pressure input signal, a supply current magnitude input signal, a detected ion flow input signal), the controller  6  supplies a digital on/off signal  8  to a gate driver  9 . Gate driver  9  level shifts the signal and generates a level-shifted on/off control signal  10 . On/off control signal  10  is supplied onto a control input terminal and input signal conductor G  11  of HVSTC  2 . The terminal GR  48  is a gate return terminal to return a reference voltage back to the gate driver  9 . If the on/off control signal  10  is at zero volts, then HVSTC  2  is controlled to be off. When HVSTC  2  is off, there is substantially no current flow from the D terminal and conductor  12 , through the HVSTC, to the S terminal and conductor  13 . If, on the other hand, on/off control signal  10  is at ten volts, then HVSTC  2  is controlled to be on. A current flows from an inductor  15 , through node  14  to D terminal and conductor  12 , through HVSTC  2 , out of S terminal and conductor  13 , and to ground conductor  5 . After inductor  15  has stored adequate energy, HVSTC  2  is turned off. As a result of HVSTC  2  turning off, the voltage on node  14  spikes upward. There is an air gap in an ionizer  16 . When the voltage on node  14  reaches an ionization voltage (for example, 6500 volts), air in the gap is ionized. A burst of current flows from node  14 , through diode  17 , through ionizer  16 , and to ground conductor  5 . HVSTC  2  is repeatedly switched on and off so that the ionizer  16  creates a flow of such ionized air. HVSTC  2  from the outside perspective has the appearance and function of a four-terminal packaged power Field Effect Transistor (FET). The four terminals are the source terminal (S)  13 , the drain terminal (D)  12 , the gate terminal (G)  11 , and the gate return terminal (GR)  48 . Unlike a conventional packaged FET, HVSTC  2  has a very high V DS  breakdown voltage (BV DS ) in excess of 6500 volts. 
       FIG. 2  is a more detailed diagram of HVSTC  2  of  FIG. 1 . HVSTC  2  has a drain-to-source V DS  breakdown voltage (BV DS ) between terminals  12  and  13  in excess of 6500 volts even though it involves a stack of three N-channel enhancement-mode power FETs  18 - 20 , each of which has a drain-to-source V DS  breakdown voltage (BV DS ) that is less than 3000 volts. In this case, each of the three FETs  18 - 20  has a BV DS  of about 2500 volts. 
     HVSTC  2  includes first N-channel enhancement-mode power FET  18 , second N-channel enhancement-mode power FET  19 , third N-channel enhancement-mode power FET  20 , a first PNP 2N2907 bipolar transistor  21 , a second PNP 2N2907 bipolar transistor  22 , 8 kV signal diodes  23 - 26 , 15 volt 1N4744 Zener diodes  27 - 28 , resistors  29 - 39 , and capacitors  40 - 44 . The nodes N 1 -N 16  in the circuit are designated in  FIG. 2  with “N” identifiers. 
       FIG. 3  is a perspective diagram of the HVSTC  2 . The circuitry of  FIG. 2  is disposed on a DCB (Direct Copper Bonded) substrate  50 . Each of the four package leads and terminals  13 ,  48 ,  11  and  12  is ultrasonically bonded to a corresponding metal island (not shown) of the upper metal layer of the DCB. The components of the circuitry are surface mounted to the top of DCB  50 . DCB  50  and the circuitry are then encapsulated in an injection-molded plastic body  51 . After leadtrimming and leadforming, the HVSTC  2  appears as illustrated in  FIG. 3 . The bottom surface of the bottom metal layer of DCB  50  is exposed on the bottom of the body  51  of the package. The package of HVSTC  2 , including its DCB and ultrasonically welded terminal leads, can be made as set forth in published U.S. patent application US20130175704, entitled “Discrete Power Transistor Package Having Solderless DBC To Leadframe Attach”, filed Jan. 5, 2012, by Gi-Young Jeun et al. (the entire subject matter of which is hereby incorporated by reference). 
     STATIC ON STATE: In a “static on state”, the three power transistors  18 - 20  are controlled to be on and conductive. The input signal  10  is at a high voltage level of ten volts. Assume for this explanation that the S lead and terminal  13  is grounded, and that the voltage on the D lead and terminal  12  is approximately zero volts due to conduction through the three power transistors. This situation is illustrated in  FIG. 4 . In this static condition, there is a current flow from node N 2 , through forward biased diode  23  to node N 8 , through resistor  31  to node N 10 , through forward biased diode  25  to node N 12 , and through resistor  32  to ground potential at node N 14 . S terminal and conductor  13  is a part of node N 14 . This current flow is illustrated by heavy arrow  45  in  FIG. 4 . The forward bias voltage drop across diode  23  is approximately 0.7 volts, so about 9.3 volts is present on node N 8 . Resistors  31  and  32  form a resistive voltage divider. Because resistor  31  has a resistance of 100 k ohms and resistor  32  has a much larger resistance of 10M ohms, the 9.3 volts on node N 8  is voltage divided such that far less than 0.7 volts is dropped across resistor  31 . Because resistor  31  is coupled between the base and emitter terminals of PNP bipolar transistor  21 , the low V BE  voltage across transistor  21  keeps transistor  21  off and nonconductive. The 10 volt signal on node N 2  is voltage divided by the resistive voltage divider of resistor  29  and resistor  30 . Accordingly, the voltage on the gate of power FET  18  is higher than the threshold voltage of power FET  18 , so the FET  18  is on and conductive. Because FET  18  is on, a because its source is at zero voltage, the voltage on node N 11  is also approximately zero volts. There is also a current flow from node N 2 , through forward biased diode  24  to node N 3 , through resistor  33  to node N 5 , through forward biased diode  26  to node N 7 , through resistor  34  to the zero voltage at node N 11 . This current flow is illustrated by heavy arrow  46  in  FIG. 4 . The forward bias voltage drop across diode  24  is approximately 0.7 volts, so about 9.3 volts is present on node N 3 . Resistors  33  and  34  form a resistive voltage divider. Because resistor  33  has a resistance of 100 k ohms and resistor  34  has a much larger resistance of 10M ohms, the 9.3 volts on node N 3  is voltage divided such that far less than 0.7 volts is dropped across resistor  33 . Because resistor  33  is coupled between the base and emitter terminals of PNP bipolar transistor  22 , the low V BE  voltage across transistor  22  keeps the transistor  22  off and nonconductive. The 9.3 volts present on node N 8  is voltage divided by the resistive voltage divider of resistors  36  and  37 , thereby supplying the appropriate high voltage that is higher than the threshold voltage of power FET  19 . This high voltage on the gate of power FET  19  keeps power FET  19  on and conductive. Likewise, the 9.3 volts present on node N 3  is voltage divided by the resistive voltage divider of resistors  38  and  39 , thereby supplying the appropriate high voltage that is higher than the threshold voltage of power FET  20 . This high voltage on the gate of power FET  20  keeps power FET  20  on and conductive. 
     STATIC OFF STATE: In a “static off state”, the three power FETs  18 - 20  are controlled to be off and nonconductive. As illustrated  FIG. 5 , the input signal  10  is at a low voltage level of zero volts. Assume for this explanation that the S terminal and conductor  13  is grounded, and that the voltage on the D terminal and conductor  12  is a very high voltage of approximately 6500 volts. In this static off condition, each of the bipolar transistors  21  and  22  is operating in its so-called “reverse active mode”. The “reverse active mode” is denoted ‘RAM” in  FIG. 5 . The PN junction between the base and the collector of the bipolar transistor is forward biased such that current flows into the collector, across the collector-to-base junction, and out of the base. Due to the structure of the bipolar transistor, it has a relatively poor emitter efficiency in this “reverse active mode” as compared to its emitter efficiency when operating in its forward active mode. In bipolar transistor  22 , there is very little emitter current I E(22) . Therefore −I C(22)  is approximately the same as I B(22) . Likewise, in bipolar transistor  21 , there is very little emitter current I E(21) . Therefore −I C(21)  is approximately equal to I B(21) . A steady current can be said to flow from the D terminal and lead  12 , through resistor  35  to node N 6 , across the collector-to-base junction of bipolar transistor  22  to node N 5 , through forward biased diode  26  to node N 7 , through resistor  34  to node N 11 , across the collector-to-base junction of bipolar transistor  21  to node N 10 , through forward biased diode  25  to node N 12 , through resistor  32  to node N 14 . This current flow is illustrated by heavy arrow  47  in  FIG. 5 . The bipolar transistor  22 , which is on and conductive (albeit in the “reverse active mode”), helps hold the gate-to-source voltage V GS(20)  between the gate and source of power FET  20  at about zero volts, and below the threshold voltage of the power FET  20 . Likewise, bipolar transistor  21 , which is on and conductive (albeit in the “reverse active mode”), helps hold the voltage V GS(19)  between the gate and source of power FET  19  at about zero volts, and below the threshold voltage of the power FET  19 . Because zero volts is present both on G terminal  11  and on S terminal  13 , the voltage on the gate of power FET  18  is held at zero volts. The gate-to-source voltage V GS(18)  of power FET  18  is therefore also at about zero volts, and below the threshold voltage of the power FET  18 . All three of the power FETs  18 - 20  are kept off and nonconductive. 
       FIG. 6A  and  FIG. 6B  are waveform diagrams that illustrate operation of HVSTC  2  of  FIG. 2  when the circuit is turning on (going from the static off state to the static on state). Prior to time t 1 , the circuit is operating in the static off state. At time t 1 , the input signal on G terminal  11  is made to transition from zero volts to ten volts. In this example, this signal transition takes about 0.1 microseconds. Starting at time t 2 , the gate-to-source voltages of the power FETs rise as illustrated in  FIG. 6A . At t 3 , the gate-to-source voltages exceed the threshold voltages of the power FETs, so the drain-to-source voltages of the power FETs start decreasing. These decreasing drain-to-source voltages are evidenced by the decreasing waveforms of VN 11 -VN 14 , and VN 6 -VN 14  and VN 1 -VN 14 . At time t 4 , the base currents of the bipolar transistors are negative, which removes stored charge, and this forces the bipolar transistors to be off at about time t 5 . From about time t 5  until about time t 8 , the decreasing of the drain-to-source voltages of the power FETs stop, one by one. For example, when the voltage VN 11 -VN 14  stops decreasing at time t 6 , then the gate-to-source voltage of power FET  18  increases and reaches its final ten volt value. When the voltage VN 11 -VN 14  stops decreasing at time t 7 , then the gate-to-source voltage of power FET  19  increases and reaches its final ten volt value. When the voltage VN 1 -VN 14  stops decreasing at time t 8 , then the gate-to-source voltage of power FET  20  increases and reaches its final ten volt value. From time t 9  onward, the circuit is operating in its static on state. 
       FIG. 7A  and  FIG. 7B  are waveform diagrams that illustrate operation of HVSTC  2  of  FIG. 2  when the circuit is turning off (going from the static on state to the static off state). Prior to time t 10 , the circuit is operating in the static on state. At time t 10 , the input signal on G terminal  11  is made to transition from ten volts to zero volts. In this example, this signal transition takes about 0.1 microseconds. Starting at time t 11 , the gate-to-source voltages on the three power FETs decrease as illustrated. The gate-to-source voltages of the two high side power FETs  19  and  20  bounce up again somewhat around time t 12  due to Miller capacitances. At time t 12 , the bipolar transistors begin to operate in their forward active mode of operation. As indicated by the waveforms IE( 22 ), IC( 22 ), IE( 21 ) and IC( 21 ) of  FIG. 7B , the collector current waveforms and the emitter current waveforms exhibit overshoot between times t 12  and t 13 . The switching is complicated, but in a simplified explanation the bipolar transistors can be described as operating in their forward active modes between times t 13  and t 14 . Between times t 14  and t 15 , the magnitude of the collector current I C(22)  flowing through bipolar transistor  22  becomes small as indicated by the IC( 22 ) waveform, and the magnitude of the base current I B(22)  flowing through bipolar transistor  22  becomes relatively large as indicated by the IB( 22 ) waveform. Likewise, between times t 15  and t 16 , the collector current I C(21)  flowing through bipolar transistor  21  becomes small as indicated by the IC( 21 ) waveform, and the base current I B(21)  flowing through bipolar transistor  21  becomes relatively large as indicated by the IB( 21 ) waveform. By time t 16 , both bipolar transistors  22  and  21  are operating in the reverse active mode (denoted “RAM” in  FIG. 5 ). From time t 16  onward, the HVSTC circuit operates in its static off state. 
     The circuit and technique described above in connection with  FIG. 2  can be extended to include a stack of four or more power FETs. For example,  FIG. 8  is a diagram of an HVSTC  100  that involves a stack of four power FETs  101 - 104 . 
     Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. Although examples are set forth above in which the power transistors are power FETs, in other examples the power transistors are power IGBTs (Insulated Gate Bipolar Transistors). Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.