Abstract:
A method and apparatus are provided for implementing optimized speed sorting of microprocessors at wafer test. A combination of speed-predicting metrics are measured early in the manufacturing process and are applied to a unique algorithm to properly sort parts into appropriate speed bins. The method significantly improves the accuracy of predicting the chip speed over conventional speed-predicting methods.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing optimized speed sorting of microprocessors at wafer test. 
     DESCRIPTION OF THE RELATED ART 
     Many microprocessor chips are required to function at some published and guaranteed speed or frequency. This frequency can usually be measured at the final, completed configuration of the chip and parts can either be divided into different speed bins or discarded if found not to meet the required frequency. 
     Manufacturers can save time and money if it was possible to reliably predict the final speed of the chip at test steps well upstream or before the final configuration of the microprocessor chip. 
     The semiconductor industry uses several different speed-predicting metrics for speed sorting or screening. However, a need exists for an effective method for speed sorting of microprocessors at a wafer level test. 
     SUMMARY OF THE INVENTION 
     A principal aspect of the present invention is to provide a method and apparatus for implementing optimized speed sorting of microprocessors at a wafer level test. Other important aspects of the present invention are to provide such method and apparatus for implementing optimized speed sorting of microprocessors at a wafer level test substantially without negative effect and that overcome many of the disadvantages of prior art arrangements. 
     In brief, a method and apparatus are provided for implementing optimized speed sorting of microprocessors at a wafer level test. A combination of speed-predicting metrics are measured early in the manufacturing process and are applied to a unique algorithm to properly sort parts into appropriate speed bins. 
     In accordance with features of the invention, a period of a ring oscillator test structure (PSRO) and a quiescent current (IDDQ) are measured on the microprocessor chip at a wafer level test. The measured quiescent current (IDDQ) is compared with a first threshold level, where the first threshold level is a predefined value. When the measured quiescent current is greater than the first threshold level, then the chip is discarded. If not, then the measured quiescent current (IDDQ) is compared with a second threshold level, where the second threshold level is a calculated based upon the measured period of a ring oscillator test structure (PSRO). When the measured quiescent current is greater than the second threshold level, then the chip is discarded. If not then the measured quiescent current is compared with a third threshold level, where the third threshold level is another calculated value based upon the measured period of a ring oscillator test structure (PSRO). When the third threshold level is greater than the measure quiescent current, then the microprocessor chip is assigned to a first bin. Otherwise the microprocessor chip is assigned to a second bin. 
     In accordance with features of the invention, the method significantly improves the accuracy of predicting the chip speed over conventional speed-predicting methods. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: 
         FIG. 1  is a block diagram representations illustrating an exemplary computer test system for implementing optimized speed sorting of microprocessors at wafer level test in accordance with the preferred embodiment; 
         FIG. 2  is a flow chart illustrating exemplary steps for implementing optimized speed sorting of microprocessors at wafer level test in accordance with the preferred embodiment; 
         FIG. 3  is a block diagram illustrating a computer program product in accordance with the preferred embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In accordance with features of the invention, a method is provided that implements optimized speed sorting of microprocessors at wafer level test. The method significantly improves the accuracy of predicting the chip speed over conventional speed-predicting methods. 
     Referring now to the drawings, in  FIG. 1  there is shown an exemplary computer test system generally designated by the reference character  100  for implementing optimized speed sorting of microprocessors at wafer test in accordance with the preferred embodiment. Computer system  100  includes a main processor  102  or central processor unit (CPU)  102  coupled by a system bus  106  to a memory management unit (MMU)  108  and system memory including a dynamic random access memory (DRAM)  110 , a nonvolatile random access memory (NVRAM)  112 , and a flash memory  114 . A mass storage interface  116  coupled to the system bus  106  and MMU  108  connects a direct access storage device (DASD)  118  and a CD-ROM drive  120  to the main processor  102 . 
     Computer system  100  includes a display interface  122  connected to a display  124 , and a test interface  126  coupled to the system bus  106 . A system under test  128  is coupled to the test interface  126 . 
     Testing in accordance with the preferred embodiment advantageously is preformed early in the manufacturing process. The system under test  128  includes, for example, a microprocessor chip at a wafer test level. 
     Computer system  100  includes an operating system  130 , a test processing program  132  of the preferred embodiment, and a chip speed sorting algorithm  134  of the preferred embodiment resident in a memory  136 . 
     Computer test system  100  is shown in simplified form sufficient for understanding the present invention. The illustrated computer test system  100  is not intended to imply architectural or functional limitations. The present invention can be used with various hardware implementations and systems and various other internal hardware devices, for example, multiple main processors. 
     Referring now to  FIG. 2 , there are shown exemplary steps for implementing optimized speed sorting of microprocessors at wafer test in accordance with the preferred embodiment starting at a block  200  with measuring a period of a ring oscillator test structure (PSRO) and a quiescent current (IDDQ) are measured on the microprocessor chip at wafer level test. The measured quiescent current (IDDQ) is compared with a first threshold level T 1 , where the first threshold level is a predefined value as indicated at a decision block  202 . For example, the first threshold level is a maximum value for quiescent current (IDDQ), such as 55 Amps for one particular microprocessor chip  128 . When the measured quiescent current is greater than the first threshold level, then the chip is discarded as indicated at a block  204 . If not, then the measured quiescent current (IDDQ) is compared with a second threshold level as indicated at a decision block  206 . The second threshold level is a calculated based upon the measured period of a ring oscillator test structure (PSRO). For example, the second threshold level T 2  is represented by
 
 T 2 =A *exp( B/PSRO )
 
with A=0.08521 and B=3974.444
 
     When the measured quiescent current is greater than the second threshold level, then the chip is discarded as indicated at a block  208 . If not then the measured quiescent current is compared with a third threshold level T 3 , where the third threshold level is another calculated value based upon the measured period of a ring oscillator test structure (PSRO). For example, the second threshold level T 3  is represented by
 
 T 3=( C*PSRO )− D  
 
with C=0.5 and D=287.5
 
     When the third threshold level is greater than the measure quiescent current, then the microprocessor chip is assigned to a first bin, such a slow bin, as indicated at a block  212 . Otherwise the microprocessor chip is assigned to a second bin as indicated at a block  214 , such as a high speed bin for 2.3 GHz operation of the microprocessor chip  128 . 
     Referring now to  FIG. 3 , an article of manufacture or a computer program product  300  of the invention is illustrated. The computer program product  300  includes a recording medium  302 , such as, a floppy disk, a high capacity read only memory in the form of an optically read compact disk or CD-ROM, a tape, or another similar computer program product. Recording medium  302  stores program means or instructions  304 ,  306 ,  308 ,  310  on the medium  302  for carrying out the methods for implementing optimized speed sorting of microprocessors at wafer test of the preferred embodiment in the system  100  of  FIG. 1 . 
     A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means  304 ,  306 ,  308 ,  310 , direct the computer system  100  for implementing optimized speed sorting of microprocessors at wafer test of the preferred embodiment. 
     While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.