Abstract:
A current mirror circuit is disclosed including a reference device and a biased device, each having control, input and output elements, with the control element of the biased device operably connected to the control element of the reference device. A reference current source is connected to the input element of the reference device and produces a reference current flowing through the reference device, wherein a bias current is produced in the biased device as a multiple of the reference current. A compensation network is connected between the biased device and the reference device for maintaining a constant bias current in the biased device regardless of varying operating characteristics in at least one of the biased device and the reference device.

Description:
FIELD OF THE INVENTION 
     The present invention is directed toward a current biasing circuit and, more particularly, a current biasing circuit compensating for changes in device parameters. 
     BACKGROUND OF THE INVENTION 
     Current biasing circuits, or “current mirror” circuits, are generally well known. Current mirrors generally use transistors, FETs (Field-Effect Transistors) or BJTs (Bipolar Junction Transistors), to produce a controlled current in a “biased” device as a multiple of a reference current that flows in a “reference” device. In an ideal case, the multiplying factor depends only upon the geometrical properties of the reference and the biased device. 
     Current mirrors constructed of conventional transistor devices should come close to the ideal case, where the physical geometry of the transistors is the sole factor influencing errors. Transistors typically used in current mirror devices include MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), MESFET (Metal Semiconductor Field-Effect Transistor), HEMT (High-Electron-Mobility Transistor) and PHEMT (Pseudomorphic High-Electron-Mobility Transistor) devices. The operation of these transistors is based upon the strength of an electrical field in a “channel” underneath a “gate” region. In the ideal case, inaccuracies in the current multiplication factor should relate back only to lithographic errors, which are unavoidable in semiconductor device manufacturing. However, the lithographic errors can be minimized. 
     If the electrical device transfer functions are ideal, in the sense that differences in the electrical environment or temperature of the reference device and the biased device do not influence the current multiplication factor, then the geometrical errors of the devices define the accuracy limit that can be achieved. However, this is not generally the case, particularly in advanced transistor devices with very short channel lengths; the channel length being the physical length of the gate contact. Various operational parameters influence the current multiplication factor in traditional current mirror devices. 
     For instance, short channel effects, which result from channel length modulation due to changes in the transistor&#39;s drain-source voltage, effect the current multiplication ratio. Velocity saturation effects, which depend on the transistor&#39;s drain-source voltage and result from the limited drift velocity of charge carriers in the channel region of the transistor substrate, also effect the current multiplication ratio. Threshold voltage modulation effects also influence the current multiplication ratio. The threshold voltage modulation effects generally result from either a barrier lowering effect caused by increasing drain-source voltage in short channel length transistors, or a barrier increasing effect, particular to short channel length silicon MOSFET transistors, caused by increasing source-bulk voltage. Still further, drain-gate reverse leakage current, common to FETs, has an effect on the current multiplication ratio. The drain-gate leakage current typically results from reverse leakage, including tunnelling, in the gate-source Schottky contact in MESFET devices, or tunnelling through the gate oxide region in MOSFET devices. 
     The present invention is directed toward overcoming one or more of the above-mentioned problems. 
     SUMMARY OF THE INVENTION 
     A current mirror circuit is disclosed including a reference device and a biased device, each having control, input and output elements, with the control element of the biased device operably connected to the control element of the reference device. A reference current source is connected to the input element of the reference device and produces a reference current flowing through the reference device, wherein a bias current is produced in the biased device as a multiple of the reference current. A compensation network is connected between the biased device and the reference device for maintaining a constant bias current in the biased device regardless of varying operating characteristics in at least one of the biased device and the reference device. 
     In one form, the reference and biased devices include field effect transistors having gate, drain and source elements corresponding to the control, input and output elements. 
     In another form, the reference and biased currents flow from the drain to source elements in the reference and biased transistors, respectively. The varying operating characteristics include a varying voltage across the drain and source elements of at least one of the biased transistor and the reference transistor. 
     The varying voltage across the drain and source elements of at least one of the biased transistor and the reference transistor results from at least one of threshold voltage modulation, short channel effects and gate leakage current occurring in at least one of the biased transistor and the reference transistor. 
     In another form, the compensation network includes a first resistor connected between the input element of the reference device and the control element of the biased device, and a second resistor connected between the input element of the biased device and the control element of the reference device. 
     The current mirror circuit may further include third and fourth resistors serially connected between the control elements of the reference device and the biased device. A feedback loop is provided between a node common to the third and fourth resistors and the input element of the reference device. Depending upon the types of transistors implemented in the current mirror circuit, the feedback loop may include a unity gain amplifier or a level shifter biasing the reference device to operate in a saturation mode. The first and second resistors may have equal resistance values, and the third and fourth resistors may have equal resistance values. 
     In another form, the compensation network further includes a compensation device having control, input and output elements, with the input element of the compensation device connected to the input element of the biased device, and the control element of the compensation device connected to the control element of the reference device. A fifth resistor is connected between the output element of the compensation device and ground. 
     The compensation device may include a field effect transistor having gate, drain and source elements corresponding to the control, input and output elements. 
     In another form, the compensation network further includes a sixth resistor connecting the second and third resistors to the control element of the reference device, and a seventh resistor connecting the first and fourth resistors to the control element of the biased device. 
     An object of the present invention is to cancel the effects of threshold voltage modulation in a current mirror device. 
     A further object of the present invention is to cancel the influence of short channel effects in a current mirror device. 
     A further object of the present invention is to cancel the influence of gate leakage current related effects in a current mirror device. 
     A further object of the present invention is to maintain a constant output current in a current mirror device regardless of voltage changes in either the reference or biased device. 
     Other aspects, objects and advantages of the present invention can be obtained from a study of the application, the drawings, and the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a prior art current mirror circuit in silicon MOSFET technology using enhancement mode n-channel transistors; 
     FIG. 2 shows a prior art current mirror circuit in GaAs MESFET technology using depletion mode n-channel transistors; 
     FIG. 3 shows a prior art biasing circuit utilized in common source amplifiers; 
     FIG. 4 is a graph illustrating the relationship between drain current and drain-source voltage in a biased transistor of a current mirror circuit due to short channel and threshold voltage modulation effects; 
     FIG. 5 is a graph illustrating the relationship between drain current and drain-source voltage in a biased transistor of a current mirror circuit due to gate leakage current; 
     FIG. 6 shows a biasing circuit for a current mirror according to a first embodiment of the present invention compensating for short channel and threshold voltage modulation effects; 
     FIG. 7 is a graph illustrating the relationship between drain current and drain-source voltage in the biased transistor of the biasing circuit for a current mirror shown in FIG. 6; 
     FIG. 8 shows a biasing circuit for a current mirror according to a second embodiment of the present invention additionally compensating for drain-gate reverse leakage current effects; and 
     FIG. 9 is a graph illustrating the relationship between drain current and drain-source voltage in the biased transistor of the biasing circuit for a current mirror shown in FIG.  8 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A common solution to the problem of providing a controlled current in a biased device is to “mirror” a reference current (typically much smaller than the current in the biased device for DC current efficiency reasons) that flows in a reference device into the biased device. Typically, such circuits are known as “current mirrors”. Current mirrors generally utilize FET devices operating in the saturation region. The DC transfer characteristics of an FET device operation in the saturation region are described in the following equation: 
     
       
         I D =(K/2)(W/L)[V GS −(V to −αV DS )] n (1+λV DS ),  (Eq. 1) 
       
     
     where 
     I D =drain current, 
     K=constant (depends on specific process parameters, e.g., layer thickness, carrier mobility, doping levels, etc.), 
     w=channel width, 
     L=channel length, 
     V GS =gate-source voltage, 
     V to =threshold voltage without threshold voltage modulation (V to &gt;0 for enhancement mode transistors; V to &lt;0 for depletion mode transistors), 
     V DS =drain-source voltage, 
     α=threshold voltage modulation coefficient, 
     n=velocity saturation index (n=2 in a long channel device without velocity saturation; n=1 in an extreme short channel device with velocity saturation); in a typical 0.5 μm hannel length device n≈1.5, and 
     λ=channel length modulation coefficient (or “Early-Voltage” coefficient). 
     FIG. 1 illustrates a typical prior art current mirror, shown generally at 10, in silicon MOSFET technology using enhancement mode n-channel transistors Q 1  and Q 2  operating in the saturation region, each transistor Q 1 ,Q 2  having drain D, source S and gate G contacts. In operation, the gate currents I G1  and I G2  flowing into the gates G 1  and G 2  of transistors Q 1  and Q 2  are zero (or very small compared to the reference current I REF  supplied by current source 12). The drain-source voltage V DSI  of transistor Q 1  is equal to its gate-source voltage V GSI  due to the feedback loop  14 . The feedback loop  14  adjusts the gate-source voltage V GS1  of transistor Q 1  such that the entire reference current I REF  will flow as the drain current of the “reference device” Q 1 . 
     Since the gates G 1 ,G 2  of the two transistors Q 1 ,Q 2  are connected together with their sources S 1 ,S 2  connected to ground, and since there is no gate current flowing that would establish any voltage drop (I GI =I G2 =0), the gate voltages applied to transistors Q 1  and Q 2  will be equal (V GS1 =V GS2 ). Thus, the output current I OUT  will mirror the reference current I REF . The accuracy of the current mirror  10  is limited by the threshold voltage mismatch of the two transistors Q 1  and Q 2 , as well as by short channel effects. 
     In order to achieve current multiplication ratios other than unity, the channel widths W 1 ,W 2  of the transistors Q 1 ,Q 2  must be different. In an ideal case, the channel width W 2  of Q 2  is an integer multiple of the channel width W 1  of Q 1 . This will equalize the influence of short channel effects on the current multiplication ratio. In this case, I OUT  is related to the channel widths W 1 ,W 2  as follows: 
     
       
         I OUT =I REF (W 2 /W 1 ).  (Eq. 2) 
       
     
     FIG. 2 illustrates a conventional current mirror, shown generally at  20 , in GaAs MESFET technology using depletion mode n-channel transistors Q 1  and Q 2 . The operation of the depletion mode current mirror  20  is identical to the operation of the enhancement mode current mirror  10  shown in FIG. 1, with the exception that measures have to be taken to account for the negative threshold voltage (V t &lt;0) of transistors Q 1 ,Q 2  in the depletion mode current mirror  20 . 
     In order to ensure transistor operation in the saturation region, an additional level shift is necessary between the gate G 1  and drain D 1  of the reference transistor Q 1 . This additional level shift is accomplished by a level shifter circuit  22  connected between the gate G 1  and drain D 1  of transistor Q 1  The level shifter  22  generally includes a series of diodes D 1  . . . D M  that are forward biased by a “helper current” I H  and voltage source V ss  (V ss may be any negative voltage), and connected between the drain D 1  and gate G 1  of Q 1  through a “helper source follower” transistor Q H . The voltage gain of the level shifter  22  is unity and its effect on the current mirror  20  is similar to that of the feedback loop  14  as described with respect to FIG.  1 . 
     FIG. 3 illustrates a conventional biasing circuit, shown generally at  30 , utilized in common source amplifiers. A solution to the problem of biasing common source amplifiers is an extension of the current mirrors  10 , 20  shown in FIGS. 1 and 2 by the addition of two resistors R 1  and R 2  serially connected between the gates G 1  and G 2  of transistors Q 1  and Q 2 , and a bypass capacitor C B  connected between a node  32  common to resistors R 1  and R 2  and ground. In the biasing circuit  30  shown in FIG. 3, depending upon the implementation with either enhancement mode (FIG. 1) or depletion mode (FIG. 2) transistors, the unity gain amplifier  34  may be replaced with either the level shifter  22  (with current source I H  and voltage source V SS ) of FIG. 2 or the feedback loop  14  of FIG.  1 . 
     The bypass capacitor C B  accomplishes a low impedance at the center node  32  such that the resistor R 2 , together with the gate input impedance of transistor Q 2 , determine the overall input impedance seen by the signal SOURCE connected to the gate G 2  of transistor Q 2  through capacitor C K . Resistor R 1  should have a resistance equal to R 2 ×(W 2 /W 1 ) to aid in reducing the effects of gate leakage current. In the case of a linear amplifier, such as a low noise amplifier or a linear power amplifier, the reference current I REF  should be chosen such that the gain of the biasing circuit  30  is independent of device tolerances. In the case of a saturated amplifier, the reference current I REF  should be chosen to be constant over temperature variations. Thus, assuming a unity gain amplifier  34 , I REF =I OUT . 
     One disadvantage in the circuits previously described, is that in the presence of short channel effects, the current multiplication ratio will be different from the geometrical value (W 2 /W 1 ) in the case where the drain-source voltages V DS1  and V DS2  on the reference device Q 1  and the biased device Q 2  are different. Generally, it can be found that in MOSFET and MESFET devices, the channel length modulation coefficient λ increases as the channel length of the device decreases. In a common source amplifier case (FIG. 3) the minimum channel length available in the transistor technology in which the circuit is implemented is the most desirable one to use since it allows for the highest frequency of operation of the circuit. Thus, in order to achieve a desired drain current I D2  (I OuT ) operating point for the biased device Q 2  over drain-source voltage V DS2  variations, caused by, for example, supply voltage (V BB ) variations, the influence of λ must be compensated for. 
     Another disadvantage in the previously described circuits is that in the presence of threshold voltage modulation in short channel devices, the drain current I D2  (I OUT ) in the biased device Q 2  will again be affected by changes in the drain-source voltage V DS2 . 
     FIG. 4 illustrates the drain current I D2  (I OUT ) in the biased device Q 2  as a function of its drain-source voltage V DS2  due to short channel and threshold voltage modulation effects. The transistors Q 1  and Q 2  utilized to generate the graph of FIG. 4 are PHEMT transistors having a channel length of 0.5 Am. The geometric channel width ratio (W 2 /W 1 ) is unity, the reference current I REF  is 1 mA, and therefore the desired output current I D2  (I OUT ) is 1 mA. However, as shown in FIG. 4, the output current I D2  (I OUT ) increases as V DS2  increases. The deviation shown in FIG. 4 is entirely due to short channel and threshold voltage modulation effects. 
     Another disadvantage to the general solution, as shown in FIG. 3, for biasing common source amplifiers is that any gate leakage current I GL1 , I GL2  out of the gates G 1 ,G 2  of transistors Q 1  and/or Q 2  will cause voltage drops across the serially connected resistors R 1  and R 2 . Even if the two resistors R 1 ,R 2  are ratioed according to the geometrical channel width ratio such that W 2 /W 1 =R 2 /R 1 , the voltage drops across the resistors R 1  and R 2  will be different since the drain-source voltages V DS1  and V DS2  (and also the drain-gate voltages V DG1  and V DG2 ) are not the same. Thus, the gate leakage currents I GL1  and I GL2  of transistors Q 1  and Q 2  will be different since the gate leakage current I GL1 ,I GL2  depends exponentially on the drain-gate voltages V DG1 ,V DG2  applied. 
     FIG. 5 illustrates the drain current I D2  (I OUT ) in the biased device Q 2  as a function of its drain-source voltage V DS2  due to the effects of gate leakage current. The circuit utilized to generate the graph of FIG. 5 follows the schematic shown in FIG. 3, with transistors Q 1  and Q 2  being PHEMT transistors having a channel length of 0.5 μm. The value of resistor R 2  is 850 Ω, the geometrical channel width ratio (W 2 /W 1 ) is 75, and the desired output current I D2  (I OUT ) is 150 mA. The deviation of the measured current I D2  (I OUT ) from the desired value is due to the gate leakage current I GL2  of Q 2  causing a voltage drop across R 2  that is different from the voltage drop across the ratioed resistor R 1 , which is caused by the gate leakage current I GL1  of Q 1 . 
     FIG. 6 illustrates a current biasing circuit, shown generally at  40 , according to the present invention for minimizing the effects of short channel lengths and threshold voltage modulation generally present in current mirror circuits. The current biasing circuit  40  includes a reference transistor Q 3  and a biased transistor Q 4 , each having drain D, source S and gate G contacts. Resistors R 11  and R 12  are serially connected between the gates G 3  and G 4  of transistors Q 3  and Q 4 , with a unity gain amplifier  42 , or feedback loop, connected between a node  44  common to resistors R 11  and R 12  and the drain D 3  of Q 3 . Depending upon the implementation of the unity gain amplifier  42  as either the level shifter  22  (with current source I H  and voltage source V SS  ) of FIG. 2, or the feedback loop  14  of FIG. 1, the biasing circuit  40  shown in FIG. 6 can be implemented as a current mirror in MOSFET and/or MESFET technologies. The addition of capacitor C B  makes it possible for the current biasing circuit  40  to be utilized in common source amplifiers (the signal SOURCE would be input to the gate G 4  of transistor Q 4 ). 
     The current biasing circuit  40  includes a compensation network  46  connected between transistors Q 3  and Q 4 . The compensation network  46  includes a resistor R 21  connected between the gate G 3  of transistor Q 3  and the drain D 4  of transistor Q 4 , and a resistor R 22  connected between the drain D 3  of the transistor Q 3  and the gate G 4  of transistor Q 4 . 
     The sources S 3 ,S 4  of transistors Q 3 ,Q 4  are connected to ground. The gate currents IG 3 , IG 4  are zero (or negligible with respect to I REF ), and accordingly, there is no voltage drop across resistors R 11  and R 12 . Similarly, the currents through resistors R 21  and R 22  are negligible with respect to I REF . Since the drain D 3  and gate G 3  of transistor Q 3  are connected together, via unity gain amplifier  42 , the bias or output current I OUT  (I D4 ) mirrors a reference current I REF  which flows into the drain D 3  of Q 3  and is supplied by a current source  48 . However, as previously noted, various operational parameters, such as short channel effects, threshold voltage modulation and gate leakage currents, influence the current multiplication factor and thus the output current I OUT  (I D4 ). These operational parameters may result from a changing drain-source voltage V DS4  in transistor Q 4 , resulting from variations in the battery voltage V BB  connected to the drain D 4  of transistor Q 4 . The current biasing circuit  40  of FIG. 6 is designed to minimize the effects of these operational parameters. 
     For simplicity, it is assumed that there is only a threshold voltage (V t ) modulation effect influencing the transfer function of Eq. 1 (λ=0): 
     
       
         I D =(K/2) (W/L) [V GS −V t ] n ,  (Eq. 3) 
       
     
     where 
     
       
         V t =V to −αV DS .  (Eq. 4) 
       
     
     The effective threshold voltage V 3  of transistor Q 3  is V to −αV DS3 , and the effective threshold voltage V t4  of transistor Q 4  is V to −αV DS4 . As the drain-source voltages V DS3 ,V DS4  of transistors Q 3 ,Q 4  change, so does their respective threshold voltage V t3 ,V t4 . As the threshold voltages V t3 ,V t4  of transistors Q 3 ,Q 4  change, so does their respective drain currents I D3 ,I D4 . From Eqs. 3-4, it follows that the difference between the two effective threshold voltages Vt 3  and V t4  is 
     
       
         (V t3 −V t4 )=α(V DS4 −V DS3 ).  (Eq. 5) 
       
     
     Since K, W and L in Eq. 3 are constants, the only way to compensate for a changing threshold voltage V t  (due to threshold voltage modulation effects, i.e., changing V DS ) is to modify V GS  such that V GS −V t , where V t =V to −αV DS  (Eq. 4), remains constant regardless of changes in the drain-source voltages. This is accomplished by the compensation network  46  of FIG. 6 as follows. 
     The output of the unity gain amplifier  42  forces a voltage V CC  on its output at node  44 . Basic circuit analysis reveals that the voltage on the gate G 3  of Q 3  (V GS3 ) is higher than V CC  by the amount (V DS4 −V CC ) [R 11 /(R 11 +R 21 )], and similarly, the voltage on the gate G 4  of Q 4  (V GS4 ) is higher than V CC  by the amount (V DS3 −V CC ) [R 12 /(R 12 +R 22 )]. 
     For symmetry reasons in a unity current gain mirror, R 11  =R 11 =R 1 , and similarly R 21 =R 22 =R 2 . Accordingly, after simple algebraic manipulation, the difference of the two gates voltages V GS3 ,V GS4  is 
     
       
         (V GS3 −V GS4 )=[R 1 /(R 1 +R 2 )](V DS4 −V DS3 ).  (Eq. 6) 
       
     
     Comparing Eq. 5 and Eq. 6, the difference of the gate-source voltages (V GS3 −V GS4 ) of transistors Q 3  and Q 4  can be made equal to the difference of their effective threshold voltages (V t3 −V t4 ) if the following design choice is made: α=R 1 /(R 1 +R 2 ). 
     This is the appropriate design choice for cancellation of the threshold voltage modulation effects, and thus the influence of changing drain-source voltages V DS3 ,V DS4 , on the output current I OUT  (I D4 ). 
     In the presence of short channel effects, the parameter λ in the transfer function of Eq. 1 has a non-zero value and must be taken into account. The effect of λ is similar to the effect of α, in that λ models the dependence of the drain current I D  in transistors operating in the saturation region on their drain-source voltage V DS . This dependence stems from channel length modulation, L→(L−ΔL), with ΔL increasing with increasing V DS . This leads to an additional factor in the drain current I D  equation: I D →I D ×(1+λV DS ). 
     Adding this additional factor to the transfer function of Eq. 1, the drain currents I D3 ,I D4  for the transistors Q 3  and Q 4  in FIG. 6 are: 
     
       
         I D3 =(K/2) (W/L) [V GS3 −(V to −αV DS3 )] n (1+λV DS3 ),  (Eq. 7) 
       
     
     
       
         I D4 =(K/2) (W/L) [V GS4 −(V to −αV DS4 )] n (1+λV DS4 ).  (Eq. 8) 
       
     
     For compensation effects, it is assumed that the current through resistors R 11  and R 12  (R 1 ) and R 12  and R 22  (R 2 ) is negligible with respect to I REF . Thus, I D3  is approximately equal to I REF . 
     Assuming a 1:1 current mirror, if the drain current I D4  (I OUT ) through transistor Q 4  is to remain constant regardless of changes in V DS3  and/or V DS4 , then it follows that:                  ∂     I   D4         ∂     V   DS4         =         ∂     I   D4         ∂     V   DS3         =   0.             (Eq. 9)                                
     Basic circuit analysis of the current biasing circuit  40  of FIG. 6 reveals that 
     
       
         V GS3 =[R 2 /(R 1 +R 2 )]V CC +[R 1 /(R 1 +R 2 )]V DS4 , and  (Eq. 10) 
       
     
     
       
         V GS4 =[R 2 /(R 1 +R 2 )]V CC +[R 1 /(R 1 +R 2 )]V DS3 .  (Eq. 11) 
       
     
     After algebraic elimination of V CC , 
     
       
         V GS4 =V GS3 +[R 1 /(R 1 +R 2 )](V DS3 −V DS4 ).  (Eq. 12) 
       
     
     By virtue of the unity gain amplifier  42 , and the fact that I D3 =I REF , 
     
       
         V GS3 =(V to −αV DS3 )[I REF /((1+λV DS3 )(KW/2L))] 1/n   (Eq. 13) 
       
     
     Eq. 12 and Eq. 13 yield expressions that can be used to evaluate the partial derivatives of I D4  (Eq. 8) with respect to V DS3  and V DS4  (Eq. 9). After calculation of the partial derivatives, a modified value for the appropriate values of the resistors is obtained, namely, 
     
       
         R 1 /(R 1 +R 2 )=α+(λ/n) (V GS3 −V t3 ).  (Eq. 14) 
       
     
     Since Vt 3  will be provided by the manufacturer of the transistor device Q 3 , and V GS3  can be determined by knowledge of I REF  (I D3 ), resistors R 1  (R 11  and R 12 ) and R 2  (R 21  and R 22 ) can be chosen to obtain the appropriate ratio of Eq. 14. This is the appropriate design choice for cancellation of threshold voltage modulation and short channel effects on the output current I OUT  (I D4 ) 
     FIG. 7 illustrates the drain current I D4  (I OUT ) of Q 4  as a function of its drain-source voltage V DS4  for the circuit of FIG.  6 . Transistors Q 3  and Q 4  are PHEMT transistors each having a channel length of 0.5 μm. The geometric channel width ratio (W 2 /W 1 ) is unity, with values for resistors R 11 , R 12 , R 21  and R 22  chosen as follows: R 11 =1 kΩ; R 12 =1 kΩ; R 21 =50 kΩ; and R 22 =50 kΩ. As seen from FIG. 7, the drain current I D4  (I OUT ) through Q 4  remains constant regardless of changes in its drain-source voltage V DS4 . Since a unity gain amplifier was assumed, the drain current I D4  (I OUT ) equals the reference current I REF , which is approximately 1 mA. 
     FIG. 8 illustrates a biasing circuit according to a second embodiment of the present invention, shown generally at  50 , with like elements of FIG. 6 indicated with the same reference numbers and elements that have been modified indicated with a prime (′). In this second embodiment, the compensation network  46 ′ further includes an additional compensation network  52  including transistor Q 5  and resistor R 4 . Devices Q 5  and R 4  are added to minimize the effects of drain-gate reverse leakage currents as previously described. The drain D 5  of transistor Q 5  is connected to the drain D 4  of transistor Q 4 , with the gate G 5  of transistor Q 5  connected to the gate G 3  of transistor Q 3 . The resistor R 4  is connected between the source S 5  of transistor Q 5  and ground. The biasing circuit  50  is of particularly utility for large current multiplication ratios. The reason being that the absolute magnitudes of the drain-gate reverse leakage currents I GL3  and I GL4  of transistors Q 3  and Q 4  differ more for larger multiplication ratios. While this difference could be offset by ratioing the resistor values R 11 /R 12  and R 12 /R 22  according to the current mirror ratio, for large ratios this leads to unreasonably high resistance values for R 11  and R 12 . In addition, this approach does not work for a wide range of drain-source voltages V DS  of the biased transistor Q 4 , but is only valid if the drain-source voltages V DS3  and V DS4  of both transistors Q 3  and Q 4  are equal. 
     Since large resistors generally consume a large amount of chip space and are not economical for monolithic integration, the total amount of chip area consumed by transistor Q 5  and resistor R 4 , can be reduced by the addition of resistors R 31  and R 32 . Resistor R 31  is connected between resistors R 11 -R 21  and the gate G 3  of transistor Q 3 , while resistor R 32  is connected between resistors R 12 -R 22  and the gate G 4  of transistor Q 4 . 
     The addition of resistors R 31  and R 32  permits scaling of resistors R 12  and R 22  by a scaling factor S 2 &lt;1, e.g., R 12 =S 2 R 12  and R 22   32  S 2 R 22 , with resistor R 32  chosen to be R 32 =R 22 (1−S 2 ). The scaling factor S 2  should be made as small as possible in a practical design, but big enough to keep the current I D5  flowing in the compensation network  52  (Q 5  and R 4 ) below 5% to 10% of the reference current I REF . It should be noted that the compensation network  52  (Q 5  and R 4 ) can be equally applied to both sides of the current mirror. 
     Operation of the biasing circuit  50  of FIG. 8 in minimizing drain-gate current leakage is as follows. Assume a large desired current multiplication factor, e.g., 75 as in a typical power amplifier application. Since Q 4  will be sized much larger than Q 3  (75×in the present example), the leakage current I GL3  of the reference transistor Q 3  can be neglected with respect to the leakage current I GL4  in the biased transistor Q 4 . As a practical matter, the gate leakage currents for each transistor are known a priori, as the manufacturer of the device provides this information on the transistor spec sheet. 
     The transistor Q 5  is chosen such that its channel length is the same as the other transistors Q 3  and Q 4  in the biasing circuit  50 . As previously discussed, the gate-source voltage V GS3  of transistor Q 3  is ideally the same as the gate-source voltage V GS4  of transistor Q 4  (I G3 =I G4 =0). It follows then, that the drain-gate voltage V DG5  of transistor Q 5  is equal to the drain-gate voltage V DG4  of the biased transistor Q 4 . This results in the same gate leakage current densities (gate leakage current per area) in both devices Q 4  and Q 5 . From the area ratios of transistors Q 4  and Q 5 , the actual gate leakage current I GL5  flowing out of the gate G 5  of transistor Q 5  can be determined. 
     The leakage current I GL5  flowing out of the gate G 5  of transistor Q 5  creates a voltage drop V GL5  across the resistor series connection R 31  and R 11 . Similarly, the leakage current I GL4  flowing out of the gate G 4  of transistor Q 4  creates a voltage drop V GL4  across the resistor series connection R 32  and R 12 . Resistors R 31 , R 11 , R 32  and R 12  are chosen such that V GL5 =V GL4 . 
     Due to the action of the feedback loop (amplifier  42 ) around the reference device Q 3 , the gate voltage V GS3  of transistor Q 3  is held constant and the voltage at the output (node  44 ) of the unity gain amplifier  42  is lowered. This will then lower the gate voltage V GS4  of transistor Q 4  and thereby reduce the drain current I D4  (I OUT ) of transistor Q 4 . 
     The drain current I D5  through transistor Q 5  is limited to a small value by resistor R 4  which forces the gate-source voltage V GS5  of transistor Q 5  to be close to the gate-source voltages V GS3  and V GS4  of transistors Q 3  and Q 4 . In this manner, it is ensured that the reverse gate leakage current densities are equal for transistors Q 4  and Q 5 . The amount of drain current I D5  in transistor Q 5  does not influence the accuracy of the compensation network  52  (Q 5  and R 4 ), however, it should be kept small. 
     In an ideal case, the channel widths W 3 ,W 5  of the transistors Q 3  and Q 5  are integer multiples of each other with the channel width W 5  of Q 5  smaller than the channel width W 4  of Q 4  (W 4 =NW 5 , with N&gt;&gt;1). Although this is not a requirement for proper operation of the biasing circuit  50 , the chip area consumption due to the addition of the gate leakage compensation network  52  (Q 5  and R 4 ) is kept at a minimum. 
     Resistors R 11  and R 21  can be scaled by a scaling factor S 1  using the requirement that the current through the series connection of S 1 R 21 −S 1 R 11  should be the same as the current through the series connection of S 2 R 22 −S 2 R 12 . This balances the current sum at the output of the unit gain amplifier  42  at node  44 . 
     The scaling factor S 1  is chosen to be S 1 =S 2 (V DS4 /V DS3 ). This leads to values for the resistors as follows: R 11 =S 1 R 11  and R 21 =S 1 R 21 . To balance the gate-source voltage shifts on both sides of the current mirror, and thus ensure a constant drain current I D4  (I OUT ), the resistor R 31  should be scaled accordingly: 
     
       
         R 31 =R 31 [(W 4 /W 3 )/(N+1)−S 1 ]/(1−S 2 ). 
       
     
     FIG. 9 illustrates the drain current I D4  (I OUT ) of transistor Q 4  as a function of its drain-source voltage V DS4  achieved by the biasing circuit  50  of FIG.  8 . Transistors Q 3 , Q 4  and Q 5  are PHEMT transistors each having a channel length of 0.5 cm. The geometric channel width ratio (W 4 /W 3 ) is 75. The reference current I REF  is 2 mA. The resistor values are as follows: R 11 =680 Ω; R 12 =255 Ω; R 21 =31 kΩ; R 22 =11.6 kΩ; R 31 =6.8 kΩ; R 32 =595 Ω; and R 4 =10 kΩ. As illustrated, the desired output current I OUT  (I D4 ) is 150 mA (equal to 75×the reference current I REF ) over a changing drain-source voltage V DS4  in the biased device Q 4 . 
     While the invention has been described with particular reference to the drawings, it should be understood that various modifications could be made without departing from the spirit and scope of the present invention.