Abstract:
There is disclosed a system for designing circuits which involves pre-placing delay elements between circuit components susceptible to shoot-through due to effects of clock skew, each delay element having a physical form and at least one input terminal and at least one output terminal; determining which delay elements are not critical in preventing shoot-through; removing non-critical delay elements from the circuit; and replacing each removed delay element with a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and output of the delay element. This wire cell has the effect of removing the delay element from the circuit without having to reposition the circuit components. This has the result that it is not necessary to re-position circuit components on the removal of delay elements and then to re-evaluate the circuit performance. Circuit design can be significantly improved.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of U.S. Provisional Application No. 60/324,045, filed Sep. 24, 2001, which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to a method and apparatus for designing electronic circuits and to a circuit component.  
       BACKGROUND OF THE INVENTION  
       [0003]     The production of electronic circuits, for example VLSI circuits, involves a design flow where the electronic function is first written in a logic form on a suitable software platform, then converted to logic gates by synthesiser software. Thereafter, the circuit design flow incorporates a physical design phase using an automatic place and route tool. The resulting circuit design is then analysed for performance.  
         [0004]     One of the prime considerations is clock skew effects, caused by slow clock rise times which may cause shoot-through problems if gate switching is too fast. Thus, any circuit which is designed must be tested to ensure that it meets the timing requirements (constraints) at the extremes of operating conditions, that is for both fastest and slowest silicon performance. The paths between state elements of the circuit cannot have too short a delay but also cannot have too long a delay.  
         [0005]     Traditionally, the problem of too short a delay, which could result in shoot-through, has been solved after design of the circuit by placing delay elements between the shoot-through sensitive circuit components and then re-placing and re-routing the circuit components in a further physical design step. The insertion of delay elements into the already designed circuit can be difficult if the circuit is congested.  
         [0006]     An alternative is to pre-place delay cells as the circuit is designed in the physical design phase. This reduces the component placing problems in a complex circuit and therefore congestion because the delay elements are taken into account at the start of the design procedure. Moreover, problems caused by clock skew are substantially eliminated. However, this approach can be detrimental in terms of worst case timing so it is then important to determine which pre-placed delay elements are indeed necessary to prevent shoot-through. Those delay elements which can be removed from the circuit are so removed, with the result that the remaining components must then be re-positioned to take into account the gap left by the removed delay elements. The re-positioning of the components necessitates re-evaluation of the circuit for shoot-through.  
         [0007]     Such re-placing and routing of a complex VLSI design can take many days to complete in computing time and re-analysis of the results.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention seeks to provide improved circuit design.  
         [0009]     According to an aspect of the present invention, there is provided a method of designing a circuit, including the steps of:  
         [0010]     pre-placing delay elements between circuit components susceptible to shoot-through, each delay element representing a physical form, comprising at least one input terminal and at least one output terminal;  
         [0011]     determining which delay elements are not critical in preventing shoot-through;  
         [0012]     removing non-critical delay elements from the circuit; and  
         [0013]     replacing a removed delay element with a conductor located between the positions of the input and output of the delay element.  
         [0014]     The placement of a conductor between the input and output locations of the delay element means that the delay element can be removed from the circuit without having to reposition the other components or to re-evaluate the performance of the circuit.  
         [0015]     The conductor is preferably a wire.  
         [0016]     Advantageously, each removed delay element is replaced by a cell representing a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and output of the delay element.  
         [0017]     The replacement cell, called herein a wire cell, can be handled in automatic assembly in the same manner as the delay cell, with the result that there is no need for extensive reprogramming of the assembly tools.  
         [0018]     Circuit design can be significantly improved by the invention.  
         [0019]     According to another aspect of the present invention, there is provided computer apparatus for designing a circuit, including:  
         [0020]     means for pre-placing delay elements between circuit components susceptible to shoot-through, each delay element representing a physical form and comprising at least one input terminal and at least one output terminal;  
         [0021]     means for determining which delay elements are not critical in preventing shoot-through;  
         [0022]     means for removing non-critical delay elements from the circuit; and  
         [0023]     means for replacing a removed delay element with a conductor located between the positions of the input and output of the delay element.  
         [0024]     The conductor may be a wire.  
         [0025]     Advantageously, the replacing means is operable to replace each removed delay element by a cell representing a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and output of the delay element.  
         [0026]     The means may be in hardware or in software form.  
         [0027]     According to another aspect of the present invention, there is provided a computer program for designing a circuit, including:  
         [0028]     a procedure for placing components in a simulated circuit and designed to pre-place delay elements between circuit components susceptible to shoot-through, each delay element representing a physical form and comprising at least one input terminal and at least one output terminal;  
         [0029]     a procedure for determining which delay elements are not critical in preventing shoot-through;  
         [0030]     a procedure for removing non-critical delay elements from the circuit; and  
         [0031]     a procedure for replacing in the simulated circuit a removed delay element with a conductor located between the positions of the input and output of the delay element.  
         [0032]     The replacing procedure may replace each removed delay element with a wire.  
         [0033]     Advantageously, the replacing procedure replaces each removed delay element with a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and output of the delay element.  
         [0034]     According to another aspect of the present invention, there is provided a wire cell for use as a replacement to a delay cell representing a physical form and comprising at least one input terminal and at least one output terminal, the wire cell representing a physical form equivalent to the physical form of the delay cell and a wire connection between an input and an output of the cell equivalent to an input and output of the delay cell.  
         [0035]     The term circuit component used herein is intended to refer to state elements, logic elements and any other circuit components other than a delay element which are susceptible to shoot-through as a result of clock skew. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0036]     An embodiment of the present invention is described below, by way of example only, with reference to the accompanying drawings, in which:  
         [0037]      FIG. 1  is a schematic diagram of an example of part of an electronic circuit;  
         [0038]      FIG. 2  is a plan view of two state elements coupled together through a delay element;  
         [0039]      FIG. 3  is a schematic diagram of an embodiment of a wire cell;  
         [0040]      FIG. 4  shows the circuit of  FIG. 2  in which the delay element is replaced by the wire cell of  FIG. 3 ;  
         [0041]      FIG. 5  is an exemplary computer system that can perform the circuit design method described herein; and  
         [0042]      FIG. 6  is a flow chart showing the principal circuit design stages of the preferred embodiment. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0043]     Referring to  FIG. 1 , there are shown a few circuit components which may typically be found in a VLSI circuit. In this example, there are two state elements  12 ,  14 , which may be flip-flops, and a logic element  16 . One of the state elements  12  is connected to the input of the logic element  16 , while the other state element  14  is connected to the output of the logic element  16 .  
         [0044]     In order to avoid any shoot-through caused by clock skew, during the physical design phase of the circuit of  FIG. 1 , delay elements  18 ,  20  are pre-placed between those circuit elements which may be susceptible to shoot-through, in this case between the components  12  and  14  and the components  14  and  16 . It is ensured that the delay elements meet worst case conditions so that it is not necessary to introduce any additional delay elements during the design process.  
         [0045]     In some instances, twice the expected necessary delay is introduced such that even if those delay cells were removed they would still meet operating constraints. More specifically, suppose the cycle time of a circuit is c (the maximum time allowed for logic propagation between state elements) and the delay through a delay cell is d. Assuming the delay cells are unnecessary, the time taken in logic element  16  of  FIG. 1  can be between 0 and c. The circuit synthesiser knows of the constraint of cycle time c. However, as the delay cells are present during synthesis, the synthesiser is told that the cycle time is c+2d, so that the time allowed in the logic is c and the time consumed by the two delay cells is 2d. Should the effects of clock skew mean that there cannot be a path of less than 2d (which is always by design a lot less than the cycle time) and the actual time used by the logic is t, the delay cells can be removed on paths where t&gt;2d.  
         [0046]     If there are paths coming either from the external inputs or to the external outputs, these paths will only see one delay element and an external time constraint of e. The synthesiser is the told the time allowed for the path is t+d−e. In other words, the external logic reduced the time allowed.  
         [0047]      FIG. 2  shows an example of a component lay-out suitable for the circuit of  FIG. 1 . This type of layout is determined (and can be manipulated) in the physical design phase of circuit design. In this example, there are provided first and second cells  22 ,  24 , between which there is provided a delay cell  26 . Considering the circuit of  FIG. 1 , the cells  22 ,  24  may constitute, for example, the state element  12  and logic element  16  and the delay cell  26  would constitute the delay element  18 .  
         [0048]     The cell  22  has first and second inputs a,b and an output o which is to be connected to input b of the cell  24 . The design process automatically pre-places delay cell  26  between the two cells  22 , 24 , which is connected between the output o of cell  22  and input b of cell  24 . In practice, the delay cell  26  has a particular physical shape and size and also specific input and output terminals or pins a and o.  
         [0049]      FIG. 2  also shows representations of the metal interconnects which would be provided on the board itself, in this case there being a metal interconnect  28  coupling output o of cell  22  to input a of delay cell  26 , and an interconnect  30  between output o of delay cell  26  and input a of cell  24 .  
         [0050]     It can be seen from  FIG. 2  that the cells  22 - 26  have predetermined physical forms and terminal positions which determine their location on the circuit board.  
         [0051]     The process of determining the component lay-out is typically carried out by computer with suitable simulation software. This then determines the control routine for automatic circuit assembly.  
         [0052]     Once the circuit has been designed and the components placed and routed onto a circuit board in the normal manner, the circuit is analysed using conventional methods and additionally to determine which delay cells are necessary and which can be removed. In practice, simulation software examines each delay in turn to see what the effect is of removing it and of connecting directly together the two cells either side of the delay cell.  
         [0053]     Take for example a case where the delay  26 , having been added speculatively, is determined not to be necessary. In the prior art it would have been necessary to change the positions of the cells  22  and  24  and to change the routing of the interconnects  28 ,  30 . These changes will affect the timing performance of the circuit, which therefore requires re-evaluation. Filler elements used for filling the gap and preserving power lines are known but they do not deal with the problems of re-routing and necessary re-evaluation.  
         [0054]      FIG. 3  shows an embodiment of wire cell  32  for use as a replacement to the delay cell  26  of the example of  FIG. 2 . The wire cell  32  has the same physical form as the delay cell  26 , that is it has the same size and shape of casing as the delay cell  26  and terminals a and o at the same locations as the terminals a and o of the delay cell  26 . The wire cell has a wire  34  therein which connects together its terminals a and o.  
         [0055]     Referring now to  FIG. 4 , the circuit of  FIG. 2  can be seen with the delay cell  26  replaced by the wire cell  32 . The wire cell  32  fits precisely in the location of the delay cell  26  and its wire  34  connects the interconnects  28  and  30  previously provided without the need for any re-routing, in practice shorting them together.  
         [0056]     It will be noticed that the wire cell  32  has the same cell library as the delay cell  26  to ensure that it can be handled during automated assembly in exactly the same manner as the delay cell  26 . There is no need for reprogramming apart from identification of the location of the replacement wire cells in the assembly process, which is simply a text file change.  
         [0057]      FIG. 5  illustrates an example computer system  50 , in which the present invention can be implemented as computer-readable code. Various embodiments of the invention are described in terms of this example computer system  50 . After reading this description, it will become apparent to a person skilled in the relevant art how to implement the invention using other computer systems and/or computer architectures.  
         [0058]     The computer system  50  includes one or more processors, such as processor  51 . Processor  51  can be a special purpose or a general purpose digital signal processor. The processor  51  is connected to a communication infrastructure  52  (for example, a bus or network). Various software implementations are described in terms of this exemplary computer system. After reading this description, it will become apparent to a person skilled in the relevant art how to implement the invention using other computer systems and/or computer architectures.  
         [0059]     Computer system  50  also includes a main memory  53 , preferably random access memory (RAM), and may also include a secondary memory  54 . The secondary memory  54  may include, for example, a hard disk drive  55  and/or a removable storage drive  56 , representing a floppy disk drive, a magnetic tape drive, an optical disk drive, etc. The removable storage drive  56  reads from and/or writes to a removable storage unit  57  in a well known manner. Removable storage unit  57 , represents a floppy disk, magnetic tape, optical disk, etc. which is read by and written to by removable storage drive  56 . As will be appreciated, the removable storage unit  57  includes a computer usable storage medium having stored therein computer software and/or data.  
         [0060]     In alternative implementations, secondary memory  54  may include other similar means for allowing computer programs or other instructions to be loaded into computer system  50 . Such means may include, for example, a removable storage unit  58  and an interface  59 . Examples of such means may include a program cartridge and cartridge interface, a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units  58  and interfaces  59  which allow software and data to be transferred from the removable storage unit  58  to computer system  50 .  
         [0061]     Computer system  50  may also include a communications interface  60 . Communications interface  60  allows software and data to be transferred between the computer system  50  and external devices. Examples of communications interface  60  may include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, etc. Software and data transferred via communications interface  60  are in the form of signals  61  which may be electronic, electromagnetic, optical or other signals capable of being received by communications interface  60 . These signals  61  are provided to communications interface  60  via a communications path  62 . Communications path  62  carries signals  61  and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link and other communications channels.  
         [0062]     In this document, the terms “computer program medium” and “computer usable medium” are used to generally refer to media such as removable storage drive  56 , a hard disk installed in hard disk drive  55 , and signals  61 . Computer program medium and computer usable medium can also refer to memories, such as main memory  53  and secondary memory  54 , that can be memory semiconductors (e.g. DRAMs, etc.) These computer program products are means for providing software to computer system  50 .  
         [0063]     Computer programs (also called computer control logic) are stored in main memory  53  and/or secondary memory  54 . Computer programs may also be received via communications interface  60 . Such computer programs, when executed, enable the computer system  50  to implement embodiments of the present invention as discussed herein. In particular, the computer programs, when executed, enable the processor  51  to implement the processes of the present invention, such as the circuit design method described generally by the flowchart of  FIG. 6 .  
         [0064]     Accordingly, such computer programs represent controllers of the computer system  50 . Where the invention is implemented using software, the software may be stored in a computer program product and loaded into computer system  50  using removable storage drive  56 , hard drive  55  and/or communications interface  61 .  
         [0065]      FIG. 6  shows an example of the principal circuit design steps for the embodiments described herein. As explained above, these design steps are typically carried out by software as part of simulated synthesis.  
         [0066]     At step  60 , delay elements are pre-placed between logic elements of the circuit being designed. At step  62  the system determines which pre-placed delay elements are not critical to circuit operation. These non-critical delay elements are removed from the circuit in step  64  and replaced by their equivalent wire cells in step  66 .  
         [0067]     It will be apparent that in practice a variety of wire cells may be provided suitable for a variety of different delay cells in cases where such a variety is used. The ability to swap cells in this manner without re-routing saves a considerable amount of design time and hence cost.  
         [0068]     Furthermore, the wire cell allows shoot-through problems to be solved without affecting worst case timing. It allows delay cells to be placed on every path at the beginning of the design process and to be easily removed. This ensures all paths are equally affected to ensure that there are no surprises during the design process, such as the inclusion of a delay cell on a critical path affecting worst case timing because the initial guess as to where to place delay cells was incorrect. The latter situation can occur with prior art methods where the temptation is to limit the number of delay cells introduced because of the difficulty of subsequently removing delay cells.  
         [0069]     Moreover, the effect of wire cells is predictable and it is therefore not necessary to analyse timing again on replacement of delay cells with the wire cells.  
         [0070]     In an alternative embodiment, the delay cell  26  can be replaced by a simple wire or by an equivalent interconnect.  
         [0071]     While certain embodiments of the invention have been described it is to be understood that modifications will be readily apparent to the skilled person and that the invention should only be determined by the scope of the attached claims. For example, the advantages of the claimed invention apply to many different types of electronic circuits and preferred method steps can be implemented at any suitable stage in the circuit design flow.