Abstract:
Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

Description:
[0001]    represent a reference clock signal and an adjustable clock signal that is locked to the reference clock signal by operation of the PLL. When the detector&#39;s output signal(s) are generated as a function of the phase difference between the two input signals, the output signals accurately reflect the phase difference between the two input signals only when that difference is within a defined range. Generally, phase detectors used within PLL circuits cannot linearly detect when the phase difference between its two input signals is greater than ±2ρ radians.  
         BRIEF SUMMARY OF THE INVENTION  
         [0002]    The present invention is a system and method for reducing phase detection error in a phase/frequency detector (PFD) arising from cycle slip. The PFD compares arrival time differences between respective clock edges in two input signals and provides control outputs based on the phase difference between these clock edges. When the PFD misses a clock edge in either input signal, cycle slip occurs. Phase-reset circuits couple the two input signals to the PFD and operate as input frequency divider circuits, providing the PFD with a sub-harmonic of each input signal. Each phase-reset circuit normally operates as an up (or down) counter, providing one output clock cycle to the PFD for every N input signal clock cycles. When presented with an indication of cycle slip, however, the phase-reset circuit sets its divide-by counter to a value that causes the next input signal clock cycle to produce an output clock cycle. This action results in the cycle slip causing substantially less than the 2ρ radians per missed cycle of phase error that otherwise manifests itself in the PFD control outputs.  
           [0003]    Generally, the PFD operates as part of a PLL and provides an “up” and a “down” control signal to charge pump circuitry that ultimately increases or decreases the control voltage applied to a voltage controlled oscillator. One of the two input signals to the PFD is derived from the VCO&#39;s output signal, and the other input signal serves as a reference against which the PLL controls the output signal. By including phase-reset circuits on the front-end of the PFD, the up/down control signal error arising from cycle slip can be reduced substantially. In general, the amount of error reduction depends upon the resolution the phase-reset circuit&#39;s digital counter. The reduced cycle slip error allows the PFD to control the associated charge pump circuit such that it remains near its maximum duty cycle for large frequency errors between the two input signals. Operation of the charge pump or pumps within the PLL in this manner tends to reduce the lock time of the PLL, improving overall performance in frequency synthesis functions based on the PLL. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]    [0004]FIG. 1 is a diagram of a phase-locked loop (PLL) including cycle slip compensation in accordance with the present invention.  
         [0005]    [0005]FIG. 2 is a diagram of the phase/frequency (PFD) detector with cycle slip compensation of FIG. 1.  
         [0006]    [0006]FIG. 3 is a diagram of the phase-reset circuits providing cycle slip compensation within the PFD of FIG. 2.  
         [0007]    [0007]FIG. 4 is a diagram of relevant operating waveforms for the PFD of FIG. 2 without benefit of cycle slip compensation.  
         [0008]    [0008]FIG. 5 is a diagram of relevant operating waveforms for the PFD of FIG. 2 illustrating cycle slip compensation.  
         [0009]    [0009]FIG. 6 is a diagram of the cycle slip detection circuitry in FIG. 1.  
         [0010]    [0010]FIG. 7 is a diagram of a mobile terminal incorporating the PLL of FIG. 1.  
         [0011]    [0011]FIG. 8 is a diagram of the frequency synthesizer in the mobile terminal of FIG. 7.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0012]    Turning now to the drawings, FIG. 1 is a diagram of a PLL, generally referred to by the numeral  10 . The PLL  10  comprises a phase/frequency detector (PFD)  12 , a control circuit  14 , a loop filter  16 , a voltage-controlled oscillator (VCO)  18 , and cycle slip detectors  20 A and  20 B.  
         [0013]    The PFD  12  receives two input signals, a reference clock signal and the output signal from the VCO  18 . The output signal from the VCO  18  is made to have a frequency that is a desired multiple or fraction of the reference clock frequency by operation of the PLL  10 . The PFD  12  typically generates two output signals, OUTPUT UP and OUTPUT DOWN, to control the control circuit  14 . The PFD  12  controls the control circuit  14  via the OUTPUT UP/DOWN signals to adjust the control voltage applied to the VCO  18 . The loop filter  16  translates the output from the control circuit  14  into a smoothed, voltage-mode control signal for the VCO  18 . In this manner, the frequency of the output signal from the VCO  18  is locked to the frequency of the reference clock.  
         [0014]    [0014]FIG. 2 illustrates the PFD  12 , with the PFD  12  comprising phase-reset circuits  30 A and  30 B and corresponding input flip-flops  32 A and  32 B, and a PFD reset circuit  33  comprising a logic gate  34  and a delay element  36 . In normal operation, the phase-reset circuit  30 A functions as an input frequency divider, dividing the reference clock signal to produce a reference signal. Likewise, the phase-reset circuit  30 B normally functions as an input signal frequency divider for the VCO output signal, providing a feedback signal to the input flip-flop  32 B at a desired sub-harmonic of the VCO output signal. Typically, phase-reset circuits  30 A and  30 B are digital counters that generate an output pulse once every N input pulses. The phase-reset circuits  30 A and  30 B will likely be configured with different maximum count values to effect the desired relationship between the frequency of the reference signal and that of the VCO output signal from the VCO  18 . For example, the phase-reset circuit  30 A might use a divisor value M, while the phase-reset circuit  30 B uses a different divisor value N.  
         [0015]    During operation, the input flip-flop  32 A latches rising edges, termed clock edges, in the reference signal, and the input flip-flop  32 B latches clock edges in the feedback signal. Once either input flip-flop  32  latches a clock edge, it is unresponsive to subsequent clock edges in its corresponding input signal until it is reset. The PFD reset circuit  33  uses the logic gate  34  to generate a reset signal (RST) that resets both input flip-flops  32 A and  32 B once both of them assert their PLL control signals (OUTPUT UP and OUTPUT DOWN). Absent the delay element  36 , the RST signal would be asserted immediately after the second of the two input flips  32 A or  32 B asserted its output signal. While this would allow the PFD  12  to work with input signal phase differences at or near a full 2ρ radians, it would cause the minimum pulse width of either OUTPUT UP or OUTPUT DOWN to be too narrow for effective control of the control circuit  14  when the reference and feedback signals have very small phase differences.  
         [0016]    Absent the delay element  36 , the wider output pulse in either OUTPUT UP or OUTPUT DOWN would be no wider than the arrival time difference between respective clock edges in the reference and feedback signals. The narrower of the two output pulses would only be as wide as the delay of logic gate  34  and the flip-flop reset delay (either  32 A or  32 B). Which of the two output signals, OUTPUT UP or OUTPUT DOWN, would have this minimum pulse width depends on whether the reference signal leads or lags the feedback signal. By delaying the RST signal a defined period after assertion of the last of the two PFD output signals, the delay element  36  allows the last asserted output signal from the PFD to remain asserted for no less than the delay time of delay element  36 . This operation defines the minimum pulse width of output pulses in either OUTPUT UP or OUTPUT DOWN, depending upon the reference signals leads or lags the feedback signal.  
         [0017]    When, as is typical, the control circuit  14  of FIG. 1 is implemented as a charge pump circuit, it causes current to flow into the loop filter  16  when the OUTPUT UP signal is asserted. This action raises the DC voltage output by the loop filter  16 , causing the VCO  18  to increase the frequency of its output signal. Conversely, the control circuit  14  sinks current from the loop filter  16  when the OUTPUT DOWN signal is asserted, causing the VCO  18  to decrease the frequency of its output signal. Thus, when the reference signal leads the feedback signal, the output pulses in OUTPUT UP are wider than the pulses in OUTPUT DOWN, and the voltage applied to the VCO  18  by the control circuit  14  gradually increases. When the reference signal lags the feedback signal, the pulses in OUTPUT DOWN are wider than the pulses in OUTPUT UP, and the voltage applied to the VCO  18  by the control circuit  14  gradually decreases.  
         [0018]    [0018]FIG. 3 is a diagram of the phase-reset circuits  30 A and  30 B. Each phase-reset circuit  30  comprises a digital counter  38 . Note that the digital counter  38  used in the phase-reset circuit  30 A will likely have a different number of counter states than that of the digital counter  38  used in the phase reset circuit  30 B. This difference arises from the likelihood that the feedback signal is scaled with respect to the output signal differently than the reference signal with respect to the reference clock. Often, the VCO output signal is at a higher frequency than the reference clock signal, so the divisor value N in the phase-reset circuit  30 B will be larger than that used in the phase-reset circuit  30 A.  
         [0019]    In operation, the counter  38  increments or decrements through its N counting states, issuing one output clock pulse for every N input clock pulses in normal operation. Here, normal operation refers to the absence of cycle slips in the PFD  12 . When the cycle slip detectors  20  detect that the PFD  12  has missed a clock cycle in either the reference or feedback signals, they assert either the UP-CYCLE SLIP indicator or the DOWN-CYCLE SLIP indicator. In response to the assertion of its cycle slip indicator input, the digital counter  38  in the appropriate phase-reset circuit  30  advances its internal count value to just before or at the counter rollover value. This causes the next clock edge on the corresponding input signal to clock through the counter  38 . That is, the counter  38  issues an output clock edge on the next input clock edge. In this context, “advance” means to increment or decrement the count value by the required amount, depending upon whether the counter  38  operates as an up- or down-counter.  
         [0020]    [0020]FIG. 4 is a collection of time-aligned waveforms, which occur during a typical phase-locking sequence. The waveforms include, from top to bottom, the reference and feedback signals, the PLL control signals OUTPUT UP and OUTPUT DOWN, and the RST signal. While FIG. 4 depicts the reference and feedback signals as output by the phase-reset circuits  30 A and  30 B, it assumes that the phase-reset circuits  30  operate only as input dividers, rather than as cycle-slip compensators. Thus, FIG. 4 illustrates the problem of cycle slip absent compensation.  
         [0021]    Because of their frequency difference, the reference and feedback signals become increasingly out of phase moving from left to right in the diagram. The reference signal lags the feedback signal, so the pulse width of OUTPUT DOWN is determined by the arrival time difference of respective clock edges in the feedback signal and the reference signal, plus the width of the RST pulse. The width of OUTPUT UP, occurring as the last of the two PLL control signals, is simply the width of the RST pulse. At a point where the phase difference between respective clock edges in the reference and feedback signals is about to reach its maximum, the input flip-flop  32 B receives a clock edge in the feedback signal while the RST pulse is asserted, causing the PFD  12  to miss this clock edge. The PFD  12  thus misses an entire cycle of the feedback signal during the phase-locking sequence.  
         [0022]    The cycle slip error manifests itself in the OUTPUT DOWN signal, which, at the next clock edge of the feedback signal, takes on a very narrow pulse width because the cycle slip causes the phase difference between the reference and feedback signals to falsely appear slight. In other words, if the actual phase difference is 2ρ+x radians, the apparent phase difference after cycle slip is simply x. So, at a time when the PFD  12  should operate the OUTPUT DOWN signal essentially at a 100 % duty cycle, the cycle slip error causes it to reduce OUTPUT DOWN to at or near the minimum pulse width on the next feedback signal clock edge after the cycle slip. This error increases the time required for the PLL  10  to lock the VCO output signal to the reference signal.  
         [0023]    [0023]FIG. 5 illustrates operation of the phase-reset circuit  30 B in the role of cycle-slip compensator. As such, the diagram depicts the same waveforms as above, but adds the DOWN-CYCLE SLIP indicator provided by down-slip detector  20 B. The up-slip detector  20 A monitors for cycle slips in the reference signal, while the down-slip detector  20 B monitors for cycle slip in the feedback signal. In the example, cycle slip occurs with respect to the feedback signal input, which means that the input flip-flop  32 B of PFD  12  misses a clock edge in the feedback signal. The following operational discussion refers to cycle slips with respect to the feedback signal and involves the phase-reset circuit  30 B, the input flip-flop  32 B, and the down-slip detector  20 B. However, it should be understood that the discussion applies equally to up-cycle slips in the reference signal involving the phase-reset circuit  30 A, the input flip-flop  32 A, and the up-slip detector  20 A.  
         [0024]    In the illustrated example, cycle slip occurs because a clock edge in the feedback signal occurs while the RST signal is asserted. The down-slip detector  20 B detects this slip occurrence and asserts its DOWN-CYCLE SLIP indicator. The phase-reset circuit  30 B receives the DOWN-CYCLE SLIP indicator, and sets its internal counter  38  to the value just before the counter&#39;s rollover point. For example, if the phase-reset circuit  30 B operates as a down counter, it may set its internal counter  38  to the minimum value. Likewise, if it operates as an up counter, the phase-reset circuit  30 B may set its internal counter  38  to the maximum value. In either case, this causes the phase-reset circuit  30 B to issue an output clock edge in the reference signal on the next input clock edge in the output signal from the VCO  18 , rather than after counting through another N clock edges in the output signal.  
         [0025]    The effect of issuing a clock edge in the reference signal one clock cycle of the output signal after the missed clock cycle in the feedback signal is a reduction in the time it takes the PFD  12  to reassert its OUTPUT DOWN signal by (N−1) clock cycles of the output signal. Here, N is the number of count states in the counter  38  of the phase-reset circuit  30 B. For example, assume that the counter  38  operates as a divide-by-100 counter. In this configuration, the phase-reset circuit  30 B outputs one feedback signal clock cycle for every 100 output signal clock cycles. Absent cycle slip compensation, if the PFD  12  misses a feedback signal clock edge, it takes another 100 cycles of the output signal for the PFD  12  to receive the next feedback signal clock edge. By operation of the phase-reset circuit  30 B, the PFD  12  receives the next feedback signal clock edge in {fraction (1/100)} th  (or some other reduced count value) of the uncompensated time.  
         [0026]    As noted, the actual number of counter states implemented in the phase-reset circuits  30 A and  30 B varies by application, and depends upon the frequencies of the reference and VCO output signals. Also, it is not necessary to set the phase-reset value of the counter  38  upon occurrence of cycle slip to the absolute minimum or absolute maximum value. Depending upon the clock frequencies involved, it may be desirable to have the counter  38  set to a few counts before its rollover value.  
         [0027]    Note that a typical RST signal pulse width may be on the order of 10 ns, which may result in one or both of the phase-reset circuits  30 A and  30 B re-issuing several output clock edges during the reset period. This causes subsequent clock edge(s) to be reissued until the original cycle slip condition is corrected.  
         [0028]    While the phase-reset circuits  30 A and  30 B provide for compensation of cycle slips in the PFD  12 , such compensation action requires detection of cycle slips as they occur. Given operation of the PFD  12 , it was earlier noted that the PFD  12  experienced cycle slip whenever it received multiple clock edges on one input signal between RST signals, or when it received a clock edge on either input signal during a RST pulse. With this, the detection of cycle slip may be approached in a variety of ways. How cycle slip detection is realized determines the structure of the up-/down slip detectors  20 A and  20 B.  
         [0029]    The co-pending application, entitled “PLL Cycle Slip Detection,” illustrates an exemplary implementation for the up- and down-slip detectors  20 A and  20 B, and is incorporated herein by reference. Note that while shown separately, the cycle slip detectors  20 A and  20 B can be incorporated as part of the PFD  12 , thus providing a circuit capable of detecting and compensating cycle slip occurrences. Also note that the present invention relates to the co-pending application entitled “Slip-Detecting Phase Detector and Method for Improving Phase-Lock Loop Lock Time,” Ser. No. 09/432,987, which was filed on Nov. 2, 1999, and is also incorporated herein by reference.  
         [0030]    [0030]FIG. 6 diagrams an exemplary cycle slip detection structure that may apply to both the up-slip detector  20 A and the down-slip detector  20 B. Each slip detector  20  comprises a logic gate  22 , an output flip-flop  24 , and a delay element  26 . Inputs to the logic gate  22  include the RST pulse from the reset circuit  33 , a delayed version of the RST pulse, derived by passing the RST signal through the delay element  26 , and one of the two PLL control signals, OUTPUT UP or OUTPUT DOWN.  
         [0031]    The logic gate  22  provides an output signal that drives the data input of the output flip-flop  24 . The output flip-flop  24  is clocked by one of the two input signals, either the reference signal or the feedback signal, depending on whether the cycle slip detector  20  is associated with the input flip-flop  32 A or the input flip-flop  32 B. The cycle slip indicator signal, either UP-CYCLE SLIP or DOWN-CYCLE SLIP, is asserted by the output flip-flop  24  whenever it receives a clock edge on its clock input while its data input is asserted. Since the logic gate  22  asserts this data input whenever the RST signal is asserted, or when the corresponding PFD input flip-flop&#39;s output is asserted, this operation detects input signal clock edges missed by the PFD  12 .  
         [0032]    Depending upon the timing characteristics of the input flip-flops  32 A and  32 B, they might not respond to an input signal clock edge if it occurs at or shortly after the falling edge of the RST pulse. Driving one of the inputs to the logic gate  22  with a delayed version of the RST pulse extends the hold time on the falling edge of the reset pulse, which extends the time that the data input of the output flip-flop  24  is asserted. This insures that the clock edge in the input signal that was missed by the input flip-flop  32 A or  32 B just as the RST pulse fell causes the output flip-flop  24  to assert its cycle slip indicator signal.  
         [0033]    [0033]FIG. 7 is a simplified diagram of a mobile terminal used in a wireless communications network, such as a cellular radiotelephone network, and is generally indicated by numeral  100 . The mobile terminal  100  includes a system controller  102  and associated memory  104 , a frequency synthesizer  106 , a receiver  120 , a transmitter  130 , a duplexer/antenna  140 , and a user interface  150 . The frequency synthesizer  106  is implemented in accordance with the present invention.  
         [0034]    In operation, the mobile terminal  100  sends and receives information via radio frequency signaling between it and a remote base station (not shown). The system controller  102  is typically implemented as one or more microcontrollers (MCUs) that manage the user interface  150 , and provide overall control of the mobile terminal  100 . The memory  104  generally includes application software, default values for constants used in operation, and working space for data.  
         [0035]    The user interacts with the mobile terminal  100  via the user interface  150 . The microphone  152  converts user speech signals into a corresponding analog signal, which is provided to the transmitter  130  for subsequent conversion, processing, and transmission to the remote base station via the duplexer/antenna  140 . The receiver  120  received signals from the remote base station and extracts received audio information, e.g., speech from a remote user, and provides an audio signal for driving a speaker  154  included in the user interface  150 . The user interface  150  further includes a keypad  156  for accepting commands and data input from the user, and a display  158  for providing visual information to the user. In short, the user interface  150  allows the user to send and receive speech and other audio information, to dial numbers, and to enter other data as needed.  
         [0036]    The receiver  120  includes a receiver/amplifier  122 , a decoding/data recovery module  124 , and a digital-to-analog converter (DAC)  126 . In operation, signals are received via the antenna  144 , and the duplexer  142  provides signal isolation between received and transmitted signals. Received signals are routed to the receiver amplifier  122 , which provides conditioning, filtering, and down conversion of the received signal. In digital implementations, the receiver/amplifier  122  may use analog-to-digital converters (ADCs) to provide the decoding/data recovery module  124  with successive digital values corresponding to the incoming received signal. The decoding/data recovery module  124  recovers the audio information encoded in the received signal, and provides the DAC  126  with digital values corresponding to the received audio information. In turn, the DAC  126  provides an analog output signal suitable for driving the speaker  154 .  
         [0037]    The transmitter  130  includes an ADC  132 , a baseband processor  134 , a frequency translation module  136 , and a transmit amplifier  138 . In operation, the ADC  132  converts analog speech signals from the microphone  152  to corresponding digital values. The baseband processor  134  processes and encodes these digital values, providing error correction encoding and translation into a format suitable for the frequency translation module  136 . The frequency translation module  136  provides the transmit amplifier  138  with a modulated signal at the desired transmit frequency. In turn, the transmit amplifier  138  generates the RF output signal RF OUT  for transmission to the remote base station via the duplexer/antenna  140 .  
         [0038]    The frequency synthesizer  106  provides one or more frequency signals for use in the mobile terminal  100 . Typically, the frequency synthesizer  106  generates reference frequency signals that are used in down converting received signals, and in modulating or generating the transmit signal. The frequency synthesizer  106  uses one or more PLLs  10  to generate theses signals.  
         [0039]    [0039]FIG. 8 is a diagram of the frequency synthesizer  106 . The frequency synthesizer  106  includes two or more PLLs  10  and a reference clock  40 . At least one of the PLLs  10  incorporates the PFD  12  and cycle slip detectors  20 A and  20 B as discussed above. With regard to that earlier discussion, the upper PLL  10  derives its reference signal from the reference clock  40  and its feedback signal from the OSC OUT  1  output signal. Likewise, the lower PLL  10  derives its reference signal from the reference clock  40 , and its feedback signal from the OSC OUT  2  signal. As noted above, the frequency synthesizer  106  may incorporate additional PLLs  10  to provide multiple reference frequencies for use in received signal processing or transmit signal generation.  
         [0040]    The frequency synthesizer  106  typically operates under control of the MCU  102 , with the MCU  102  setting, for example, the divider ratios used by the frequency divider circuits  30  in both PLLs  10  to control the frequency of the OSC OUT  1  and OSC OUT  2  signals. The cycle slip compensation provided by the phase-reset circuits  30 A and  30 B improves the response time of the frequency synthesizer  106  by reducing the amount of time required to bring the oscillator output signals provided to the transmitter  120  and receiver  130  into lock with the reference signal provided by the reference clock  40 .  
         [0041]    The present invention contemplates usage in a broad range of equipment types. Communication equipment, such as wireless network base stations and associated mobile terminals, might particularly benefit from incorporation of the present invention into their associated PLL circuits. Further, the present invention may, of course, be carried out in other specific ways than those herein set forth without departing from the spirit and essential characteristics of the invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.