Abstract:
The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a Zener diode. 
         [0003]    2. Description of the Related Art 
         [0004]    Zener diodes are commonly used to regulate voltage in a circuit or to supply a stable reference voltage. For this purpose, a Zener diode is reverse-connected in parallel with a voltage source. When the voltage supplied by the voltage source reaches the breakdown voltage of the diode, the latter becomes conducting and then maintains the voltage at this value. 
         [0005]    The present disclosure applies in particular to objects having an autonomous low power supply, to communicating objects and to energy harvesting circuits. In these applications, the breakdown voltage of the Zener diode should be as low as possible. 
         [0006]      FIG. 1  is a cross-section of a conventional Zener diode formed in a substrate made of a semiconductor material of a first conductivity type, for example P. The Zener diode comprises a well NW having a doping of a second conductivity type, for example N, forming an anode region of the Zener diode. The Zener diode comprises a highly doped cathode region CD of the first P+-conductivity type, formed in the well NW. The region CD is formed on a region ZD having a high doping of the second N+-conductivity type. The regions CD and ZD are isolated from the rest of the well NW by a shallow trench isolation STI. The Zener diode comprises a highly doped anode connection region ED of the second N+-conductivity type formed in the well NW and isolated from the cathode region by the trench STI. Furthermore, the substrate SUB comprises a highly doped region SP of the first P+-conductivity type, forming a bias region of the substrate SUB. The substrate bias region SP is isolated from the regions CD, ZD by the shallow trench isolation STI. 
         [0007]      FIG. 2  represents a curve C 11  of variation of the current passing through the Zener diode according to the reverse voltage applied between the regions CD and ED. The curve C 11  shows the operation of a conventional reverse-biased Zener diode. Between 0 and approximately 2.5V, the current passing through the diode remains low (lower than 10 −12  A). From approximately 2.5V and up to approximately 5.2V, the current passing through the diode increases linearly (according to a logarithmic scale) up to approximately 10 −8  A. This operating zone which results from a so-called “band to band” phenomenon cannot be used to supply a reference voltage or to perform a voltage regulation. Above approximately 5.2V, a breakdown phenomenon appears, the diode becoming highly conducting, by avalanche effect, while reaching a maximum voltage BV called “breakdown voltage” of approximately 5.5V. The diode keeps this voltage constant irrespective of the intensity of the current, provided that the latter remains between approximately 10 −8  A and 10 −6  A. Zener diodes are generally used in this operating zone, to supply a stable reference voltage or to perform a voltage regulation. 
         [0008]    One proposal already made consists in lowering the breakdown voltage of a Zener diode by thinning the region ZD so as to obtain a transition between the two conductivity types of the regions CD and ZD that is as sudden as possible. However, this solution reaches a limit due to the very low thickness of the region ZD. This solution enables a current to be obtained which increases more rapidly at low voltage values than on the curve C 11 . The breakdown phenomenon also occurs at a lower voltage than on the curve C 11 , but the voltage continues to increase according to the current. The “band to band” phenomenon tends to extend over broader ranges of voltage and current values. In these conditions, the Zener diode cannot be used to supply a reference voltage or to perform a voltage regulation. 
       BRIEF SUMMARY 
       [0009]    Some embodiments are directed to a Zener diode having a low breakdown voltage, lower than 1.5V. Some embodiments produce such a diode in an integrated circuit, by implementing manufacturing steps commonly used to produce CMOS transistors. Some embodiments produce a Zener diode of which the breakdown voltage can be adjusted. 
         [0010]    Some embodiments relate to a Zener diode comprising: a cathode region having a first conductivity type, formed on the surface in a semiconductor substrate having a second conductivity type, an anode region having the second conductivity type, formed beneath the cathode region, the cathode and anode regions being isolated from the rest of the substrate by trench isolations, and first conducting regions configured, when they are subjected to adequate voltages, to generate a first electric field perpendicular to an interface between the cathode and anode regions. According to one embodiment, the Zener diode includes second conducting regions configured, when they are subjected to adequate voltages, to generate a second electric field parallel to an interface between the cathode and anode regions. 
         [0011]    According to one embodiment, the second conducting regions include an embedded gate, separated from the anode region only by a dielectric layer of the gate. 
         [0012]    According to one embodiment, the Zener diode includes: a well having the first conductivity type, formed in the substrate, the cathode region being formed on the surface of the well, and the anode region being formed in the well beneath the cathode region, and an anode connection region of the first conductivity type, formed on the surface of the well and isolated from the cathode region. 
         [0013]    According to one embodiment, the well is isolated from the substrate by a shallow trench. 
         [0014]    According to one embodiment, the gate is formed between the cathode region and an anode connection region. 
         [0015]    According to one embodiment, the gate surrounds the cathode and anode regions. 
         [0016]    According to one embodiment, the gate is formed in the cathode and anode regions. 
         [0017]    According to one embodiment, the gate has an octagonal or rectangular shape. 
         [0018]    According to one embodiment, the first and second conducting regions are interconnected. 
         [0019]    Some embodiments may also relate to a circuit comprising a Zener diode as disclosed herein. 
         [0020]    Some embodiments may also relate to a method for controlling a Zener diode as disclosed herein, the process comprising: applying a first voltage to the cathode region, applying to the anode region a second voltage to reverse-bias the Zener diode, the difference between the first voltage and the second voltage being greater than or equal to a breakdown voltage of the Zener diode. According to one embodiment, the method includes applying a third voltage to the second conducting regions to generate an electric field parallel to the interface between the cathode and anode regions. 
         [0021]    According to one embodiment, the second conducting regions include an embedded gate, separated from the anode region only by a dielectric layer of the gate, the method comprising a step of applying the third voltage to the gate. 
         [0022]    According to one embodiment, the third voltage is set equal to the first voltage. 
         [0023]    According to one embodiment, the method includes adjusting the third voltage according to a breakdown voltage to be reached by the Zener diode. 
         [0024]    According to one embodiment, the breakdown voltage is adjustable between 1.2 and 5V by causing the third voltage to vary between the first voltage and the second voltage. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0025]    Some examples of embodiments of the present disclosure will be described below in relation with, but not limited to, the appended figures, in which: 
           [0026]      FIG. 1  is a cross-section of a conventional Zener diode, 
           [0027]      FIG. 2  represents a characteristic curve of current according to the voltage at the terminals of a conventional Zener diode, 
           [0028]      FIG. 3  is a cross-section of a Zener diode according to one embodiment, 
           [0029]      FIG. 4  is a detailed partial cross-section of the Zener diode of  FIG. 3 , 
           [0030]      FIG. 5  represents characteristic curves of the current according to the voltage at the terminals of the Zener diode of  FIG. 3 , 
           [0031]      FIG. 6  is a cross-section of a Zener diode according to another embodiment, 
           [0032]      FIG. 6A  represents a characteristic curve of the current according to the voltage at the terminals of the Zener diode of  FIG. 6 , 
           [0033]      FIG. 7  is a top view of the Zener diode, according to one embodiment, 
           [0034]      FIGS. 8 and 9  are a cross-section and a top view of a Zener diode, according to another embodiment, 
           [0035]      FIG. 10  is a top view of a diode according to another embodiment, 
           [0036]      FIGS. 11 and 12  are a cross-section and a top view of a Zener diode, according to another embodiment, 
           [0037]      FIG. 13  is a top view of a Zener diode, according to another embodiment, 
           [0038]      FIG. 14  is a cross-section of a Zener diode, according to another embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0039]      FIG. 3  represents a Zener diode ZR according to one embodiment. The Zener diode is formed in a substrate SUB 1  made of a semiconductor material having a doping of a first conductivity type, for example P. The Zener diode ZR includes a cathode region CD 1  having a high doping of a second conductivity type, for example N+, superimposed on an anode region AD 1  having a doping of the first conductivity type (P). The regions CD 1 , AD 1  are formed in a well NW 1  having a doping of the first conductivity type (N in the example considered), which is formed in the substrate SUB 1 . Thus, the Zener diode ZR includes a junction zone NPN formed by the region AD 1  and in particular by the interfaces between the region AD 1  and the region DC 1  and between the region AD 1  and the well NW 1 . The well NW 1  is isolated from the rest of the substrate SUB 1  by a shallow trench isolation STI 1 . The Zener diode ZR also includes a highly doped region ED 1  of the second conductivity type (N+), forming a region for biasing the well NW 1  and for connecting the anode of the diode ZR. Furthermore, the substrate SUB 1  includes one or more highly doped regions SP 1 , of the first conductivity type (P+), forming bias regions of the substrate SUB 1 . The Zener diode ZR also includes a cathode contact pad CDC formed on the region CD 1 , and an anode contact pad EDC formed on the region ED 1 . One or more bias contacts SPC of the substrate are formed on the substrate SUB 1  bias regions SPP. 
         [0040]    According to one embodiment, the Zener diode ZR includes a vertical embedded gate GT 1 , formed in the well NW 1 , so as to be separated from the regions CD 1 , AD 1  and ED 1 , and from the well NW 1 , only by a dielectric layer GTD. The gate GT 1  is provided to receive a bias voltage GV through a gate contact pad GTC. The voltage GV can be supplied by a circuit CMD also supplying the cathode contact pad CDC with a cathode voltage CV and the anode contact pad EDC with an anode voltage AV. The dielectric layer GTD can have a thickness between 5 and 15 nm, depending on the manufacturing technology used and the voltages to be implemented. Thus, the layer GTD can have a thickness in the order of 10 nm. 
         [0041]    The gate GT 1  can be produced by etching a hole or a trench in the substrate SUB 1 , by forming on the walls and the bottom of the trench the dielectric layer GTD, for example by oxidation, and then by filling the trench with a conducting material such as a metal or polycrystalline silicon. These manufacturing steps, and those enabling the different doped regions and the trench STI 1  to be formed, are commonly implemented to produce CMOS transistor-based circuits. 
         [0042]      FIG. 4  represents in greater detail the junction zone NPN of the Zener diode ZR made up of the region AD 1  in contact with the well NW 1  and the region CD 1 , and in particular, the portion of the junction zone NPN in the vicinity of the gate GT 1 . When the Zener diode ZR is reverse-biased, the cathode contact pad CDC receives a voltage lower than the voltage applied to the well bias contact pad EDC. In these conditions, an electric field Ez directed from the region AD 1  towards the region CD 1  appears in the region AD 1 . If the gate GT 1  receives a positive voltage, an electric field Ex directed towards the gate GT 1  also appears in the region AD 1 , parallel to the interface plane between the regions CD 1  and AD 1 . The simultaneous presence of the electric fields Ez and Ex forms a resulting field Er directed in the angular sector between the directions of the fields Ez and Ex. It can be seen that the amplitude of the field Er is higher than that of the field Ez. In addition to this effect of increasing the electric field, there is a proximity effect, as the gate GT 1  is directly in contact with the junction zone NPN. The result is that the charges present in the junction zone NPN undergo a higher electric field and thus become mobile under the effect of a lower voltage applied to the region CD 1 , this mobility resulting in a breakdown phenomenon by avalanche effect. Thus, the gate GT 1  is used here as an electrically conducting element to bring a voltage in the vicinity of the junction zone NPN, so as to generate the electric field Ex. 
         [0043]      FIG. 5  represents curves C 12 , C 13  of variation of the current passing through the Zener diode ZR according to the voltage CV applied to the cathode region CD 1 , the voltage AV applied to the anode connection region ED 1  being zero and the voltage applied to the region SPC being zero too. In the case of the curve C 12 , the gate GT 1  receives a voltage equal to the anode voltage AV applied to the contact pad EDC, for example set to 0V. In the case of the curve C 13 , the gate GT 1  receives a voltage GV of approximately 1.3V. Between 0 and approximately 2.7V for the curve C 12 , and approximately 1.1V for the curve C 13 , the current passing through the diode ZR linearly increases according to a logarithmic scale, while remaining very low (lower than 10 −13  A). Above 1.1V for the curve C 12  and 2.7V for the curve C 13 , a breakdown phenomenon appears, the diode ZR becoming highly conducting at a breakdown voltage BV of approximately 2.9V for the curve C 12 , and a breakdown voltage BV 1  of approximately 1.3V for the curve C 13 . The diode ZR keeps this voltage constant irrespective of the intensity of the current, provided that the latter remains greater than approximately 5.10 −12  A. The curve C 13  can also be obtained by setting the voltage GV applied to the gate GT 1  to a voltage equal to or greater than the breakdown voltage BV 1 , for example to a value between 1.3 and 1.5V. 
         [0044]    If the voltage of the gate GT 1  is increased from the anode voltage AV for example set to 0V (curve C 12 ), a curve having substantially the same shape as the curves C 12  and C 13 , situated between the latter, is obtained. The comparison of the curves C 12  and C 13  shows that the application on the gate GT 1  of a voltage which switches from the anode voltage AV (i.e., 0V) to the voltage BV 1  enables the breakdown voltage of the diode ZR to be decreased from the voltage BV to the voltage BV 1 . 
         [0045]    According to one embodiment, the breakdown voltage BV, BV 1  of the diode ZR is controlled, for example by the circuit CMD, by adjusting the voltage GV applied to the gate GT 1  between the anode voltage AV and the cathode voltage CV. In this way, the Zener diode ZR can be used to produce an adjustable reference voltage source or a voltage regulator having an adjustable setpoint voltage. 
         [0046]      FIG. 6  represents a Zener diode ZR′ having a low breakdown voltage, according to another embodiment. The diode ZR′ differs from the Zener diode ZR in that it comprises not three connection terminals formed by the contact pads CDC, EDC, GTC, but only two connection terminals formed by the cathode CDC and anode EDC contact pads, the gate contact pad GTC being coupled to the cathode contact pad CDC. 
         [0047]      FIG. 6A  represents a curve C 14  of variation of the current passing through the Zener diode ZR′ according to the voltage CV applied to the cathode region CD 1 , the voltage AV applied to the anode connection region ED 1  being zero and the voltage applied to the region SPC being zero too. The curve C 14  substantially corresponds to the curve C 13  of  FIG. 5 , the Zener diode ZR′ having the breakdown voltage BV 1 . The connection between the contact pads CDC and GTC can be achieved for example by a single contact pad covering the cathode regions CD 1  and the gate GT 1 . 
         [0048]      FIG. 7  is a top view of the Zener diode ZR according to one embodiment. In the embodiment shown in  FIG. 7 , the gate GT 1  isolates the regions CD 1 , AD 1  from the bias region ED 1 . The trench STI 1  surrounds a zone comprising the regions CD 1 , AD 1 , the gate GT 1  and the region ED 1 . One or more regions SP 1  for biasing the substrate SUB 1  can be formed around the diode ZR delimited by the trench STI 1 . 
         [0049]      FIGS. 8 and 9  illustrate a cross-section and top view, respectively, of a Zener diode ZR 1  according to another embodiment. The diode ZR 1  includes a cathode region CD 2  having a high doping of the second conductivity type (N+), superimposed on an anode region AD 2  having a doping of the first conductivity type (P). The regions CD 2 , AD 2  are formed in a well NW 2  having a doping of the second conductivity type (N), which is formed in the substrate SUB 2 . 
         [0050]    According to one embodiment, an embedded gate GT 2  is formed in the regions CD 2 , AD 2 , so as to be in contact with the junction zone NPN of the diode ZR 1 . The regions CD 2 , AD 2  including the gate GT 2 , are isolated from the rest of the well NW 2  by a shallow trench isolation STI 2 . The Zener diode ZR 1  also includes in the well NW 2 , a highly doped region ED 2  of the second conductivity type (N+), forming a region for biasing the well NW 2  and for connecting the anode of the diode ZR 1 . The well NW 2  is isolated from the rest of the substrate SUB 2  by a shallow trench isolation STI 3 . Furthermore, the substrate SUB 2  includes one or more highly doped regions SP 2 , of the first conductivity type (P+), forming bias regions of the substrate SUB 2 . The Zener diode ZR 1  also includes a cathode contact pad CDC formed on the region CD 2 , an anode contact pad EDC formed on the region ED 2 , and a gate contact pad GTC formed on the gate GT 2 . One or more bias contacts SPC are formed on the substrate SUB 2  bias regions SP 2 . 
         [0051]    As can be seen from  FIG. 9 , the trench isolations STI 2 , STI 3  isolate three regions, i.e., a central region and two lateral regions including the anode connection regions ED 2 , on either side of the central region. The central region includes the gate GT 2  and on either side of the gate, the cathode regions CD 2 . 
         [0052]      FIG. 10  represents a top view of a Zener diode ZR 2  having a cross-section configuration which can be similar to that of  FIG. 8 , according to another embodiment. The diode ZR 2  includes a cathode region CD 3  superimposed on an anode region, surrounding an embedded gate GT 3 , the cathode region CD 3  being surrounded by a trench isolation STI 4 . The diode ZR 2  also includes an anode connection region ED 3  surrounding the trench isolation STI 4  and which is isolated from the substrate SUB 3  by a trench isolation STI 5 . The cathode CD 3  and anode connection ED 3  regions, and the trenches STI 4 , STI 5  have an octagonal shape. The gate GT 3  may have a square shape or more generally a rectangular, or even octagonal, shape. 
         [0053]      FIGS. 11 and 12  represent a cross-section and top view, respectively, of a Zener diode ZR 3  including a cathode region CD 4  having a high doping of the second conductivity type (N+), superimposed on an anode region AD 4  having a doping of the first conductivity type (P). The regions CD 4 , AD 4  are formed in the well NW 4  and isolated from the rest of the well NW 4  by an embedded gate GT 4  formed in a trench surrounding the regions CD 4 , AD 4 . Anode connection regions ED 4  are formed in the well NW 4  along external edges of the gate GT 4 . The well NW 4  is isolated from the substrate SUB 4  by a trench isolation STI 6  surrounding the gate GT 4  and the anode connection regions ED 4 . 
         [0054]      FIG. 13  represents a top view of a Zener diode ZR 4  having a cross-section configuration which can be similar to that of  FIG. 11 , according to another embodiment. The diode ZR 4  includes a cathode region CD 5  superimposed on an anode region, and surrounded by an embedded gate GT 5 , the gate GT 5  being surrounded by an anode connection region ED 5 . The diode ZR 4  also includes a shallow trench isolation STI 7  isolating the anode connection region ED 5  and the well (e.g., the well NW 4  shown in  FIG. 11 ) from the substrate SUBS. The cathode CD 5  and anode connection ED 5  regions, and the gate GT 5  and the trenches STI 7  have an octagonal shape. 
         [0055]    It will be understood by those skilled in the art that the present disclosure is susceptible of various alternative embodiments and various applications. In particular, the disclosure is not limited to the shapes of the different regions of the Zener diodes presented. Shapes other than the rectangular and octagonal shapes described can be considered for the different regions of the Zener diode. Thus, circular and square shapes and other polygonal shapes can be considered for these regions. 
         [0056]    Furthermore, in all the embodiments described above, the conductivity types of the doping of the different regions forming the Zener diode can be inverted. Thus,  FIG. 14  represents a Zener diode ZR 5  having the shape of the diode ZR (shown, for example, in  FIG. 3 ), formed in a well PW having a doping of the first conductivity type (P), the well PW being formed in a well NO formed by deeply implanting dopants of the second conductivity type (N) in the substrate SUB 6 . As above, the well PW is isolated from the well NO by a trench isolation STI 8 . The well NO may be isolated from the substrate SUB 6  by shallow trench isolations STI 9 . The diode ZR 5  includes a vertical gate GT 6  embedded in the well PW. In the example of  FIG. 14 , the gate GT 6  delimits on one side with the trench isolation STI 8  a highly doped cathode region CD 6  of the first conductivity type (P+), superimposed on an anode region AD 6  of the second conductivity type (N). The gate GT 6  delimits on another side with the trench isolation STI 8  a highly doped anode connection region ED 6  of the first conductivity type (P+). The regions CD 6  and ED 6  are topped by respective contact pads CDC and EDC. The well NO is biased (grounded) through highly doped bias regions SNC of the second conductivity type (N+), each topped by a bias contact pad SNC. It shall be noted that the Zener diode ZR 5  is reverse-biased by applying to the cathode contact pad CDC a voltage lower than the voltage applied to the bias contact pad EDC for biasing the well PW. 
         [0057]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.