Abstract:
In one embodiment, the present invention includes a method for depositing lead-free bumps on a package substrate, depositing an alloy material on the lead-free bumps, attaching a semiconductor die including conductive bumps to the package substrate so that the conductive bumps contact the alloy material, and heating attached components to reflow the alloy material to form a joint therebetween. Other embodiments are described and claimed.

Description:
BACKGROUND 
       [0001]    Many of today&#39;s semiconductor packages are formed using so-called flip-chip technology. In such packaging, a semiconductor die is coupled to an underlying package substrate using a solder to connect a bump on the die with a bump on the package substrate. 
         [0002]    As process technologies move away from lead-based solders to lead-free solders, after elevated temperatures at which reflow is performed, sufficient stress can be present in the package to cause delamination of dielectric layers such as a carbon doped oxide (CDO) layer of the semiconductor die. Such stress can occur as a result of coefficient terminal expansion (CTE) mismatches. While one solution to this problem implements a so-called no-flow under film (NUF) process, where an underflow material is allowed to gel and distribute stress to an entire die surface before cooling of the resulting joined package and die to room temperature, excessive costs and time is required and furthermore, expensive tooling is needed for each such die size to enable this process. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]      FIGS. 1A-1D  are cross-sectional views of process steps in accordance with an embodiment of the present invention. 
           [0004]      FIG. 2  is a solder reflow profile in accordance with one embodiment of the present invention. 
           [0005]      FIGS. 3A-3B  are cross-section views of further process steps in accordance with an embodiment of the present invention. 
           [0006]      FIG. 4  is a gel, curing and solder reflow profile in accordance with one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0007]    In various embodiments, a flip chip package may be formed using lead-free materials for chip attach, while avoiding delamination such as CDO delamination. To enable such a package, a low melting point alloy may be applied to metal bumps on a die or corresponding substrate. A chip attach process may then be performed at a low temperature to reflow the alloy, soldering the die to the substrate. The stress due to CTE mismatch between die and substrate may be reduced due to a relatively small delta in temperature between reflow process and ambient temperature. 
         [0008]    After such reflow, an epoxy underfill material may be applied using, for example, a capillary underfill process. This underfill material may then be gelled below a melting point of the solder to contain the solder after final cure. After the gel process is completed, the final cure temperature may be applied to thus redistribute package stress across die and bumps after cure, reducing stress on the individual bumps. After the cure process, the package temperature may be raised above the point of the solder bumps on the substrate, causing melting and dissolution of the material. The final composition of the joint may be in proportion to the percentage of materials within the joint materials. In various embodiments, the proportions of these materials may be chosen to have a resulting alloy with a high melting point (e.g., greater than approximately 200 degrees Celsius (C)) and mechanical properties to enable high reliability under stress conditions. 
         [0009]    Referring now to  FIGS. 1A-1D , shown are cross-sectional views of process steps in accordance with an embodiment of the present invention. As shown in  FIG. 1A , a chip attach process may begin by receiving an incoming substrate, i.e., a package substrate  100  including a metal bump  110  which, in some embodiments, may be a tin silver copper (SnAgCu) bump, above which an alloy material  120 , which in one embodiment may be indium tin (InSn) may be located. In one embodiment, metal bump  110  may be a lead-free solder bump, e.g., 95.5 Sn/3.8 Ag/0.7 Cu or another such material. To form metal bumps  110  on substrate  100 , a lead-free solder paste may be applied to substrate  100  and reflowed to form the primary bumps, which may then be flattened to form a flat surface to support an additional layer of alloy  120 . In one embodiment, alloy  120  may be a low melting point alloy having good wetting characteristics, e.g., indium tin (InSn), such as a composition having 52 In/48 Sn, 118 degrees C. eutectic or equivalent. While shown as being applied to metal bump  110  on substrate  100 , in other implementations the alloy material may be adapted to a metal bump on a die. 
         [0010]    Referring now to  FIG. 1B , then a flux material  130  may be dispensed. After flux  130  is dispensed, a chip attach process may be performed as shown in  FIG. 1C , in which a die  140  having a metal bump  145  such as a copper bump may be located above alloy material  120 . Note that die  140  may include dielectric layers that may be formed of a CDO, which could suffer from delamination, depending on chip attach process used. Embodiments may avoid such delamination. 
         [0011]    After fluxing, a chip alignment and placement process may thus be performed. The resulting chip/substrate assembly may be placed in a reflow furnace with a temperature profile such as that shown in  FIG. 2 . Alloy  120  may thus become a liquid, forming the joint between die  140  and substrate  100 . The chip joint may be formed by reflowing alloy  120 , soldering die  140  to substrate  100 . In this process, the stress due to CTE mismatch between die  140  and substrate  100  may be reduced because of a relatively small delta between reflow temperature and ambient temperature. 
         [0012]    Thus as shown in  FIG. 2 , which is solder reflow profile, a peak temperature during which solder reflow occurs is approximately 122° C. This solder reflow process thus results in the chip joint shown in  FIG. 1D  in which alloy material  120  is reflowed to result in material  125 . While the scope of the present invention is not limited in this regard, the time for temperature elevation to occur for solder melting may be between approximately 200 and 300 seconds. Then a peak temperature of the reflow process may occur for approximately between 30 and 90 seconds at temperatures between approximately 117° C. and 122° C. Finally, the solder reflow process is allowed to cool to form the joint. Such solder solidification process may occur for between 90 and 120 seconds. 
         [0013]    Referring now to  FIGS. 3A-3B , shown are cross-section views of further process steps in accordance with an embodiment of the present invention. As shown in  FIG. 3A , next an underfill process may be performed in which an underfill material  150  such as an epoxy underfill may be applied, e.g., using a capillary underfill method. This underfill material may then be gelled below the melting point of the low melting point solder, e.g., at 112° C., as shown in the thermal profile of  FIG. 4 . As shown further in  FIG. 4 , after gelling, the temperature may be elevated, e.g., to 165° C. for a cure process during which package stress across the die and bumps may be redistributed. After curing, the temperature may be raised to enable joint formation, as shown in  FIG. 3B  in which an alloy material  160  with a new composition is realized after the high temperature reflow process which, in the embodiment of  FIG. 4  may occur at approximately 225° C. As described above, the final composition of the alloy may be based on the percentage of materials within the joint. For example, in some embodiments the combined volumes of the alloy and substrate bumps may be such that results in alloy of approximate composition 87 Sn/9.2 In/3.2 Ag/0.6Cu. Thus this resulting alloy may be realized with a high melting point and mechanical properties to enable stress-free conditions. 
         [0014]    While shown with this particular implementation in the embodiments of  FIGS. 1-4 , the scope of the present invention is not limited in this regard. For example, in addition to a process such as the flip chip process described above for formation of a semiconductor package, such as a package including a semiconductor die such as a microprocessor, chipset or other such component, other embodiments may be used to form solder joints for lead-free capacitors and so forth. 
         [0015]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.