Abstract:
A fin type storage node electrode projects from an inter-level insulating layer so as to use the top, side and back surfaces thereof for accumulation of electric charge, and testing elements for evaluating properties of the layers of the storage node electrode are concurrently formed directly on the inter-level insulating layer, thereby preventing the testing elements from undesirable breakage.

Description:
This is a divisional application of Ser. No. 08/805,973, filed Feb. 26, 1997, now U.S. Pat. No. 5,969,381. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to a semiconductor device and, more particularly, to a semiconductor device accompanied with testing elements for evaluating components of the semiconductor device and a process of fabrication thereof. 
     DESCRIPTION OF THE RELATED ART 
     A typical dynamic random access memory cell is implemented by a series combination of a single field effect transistor and a single storage capacitor. The semiconductor dynamic random access memory device has increased the dynamic random access memory cells, and, accordingly, a real estate occupied by each memory cell is getting narrower and narrower. On the other hand, if the capacitance of the storage capacitor is too small, the data bit stored therein tends to be lost due to the presence of an alpha-particle. For this reason, the manufacturer is required to decrease the occupation area assigned to each dynamic random access memory cell without reduction of the capacitance of the storage capacitor. 
     One of the approaches is to give a complicated three-dimensional configuration to the storage electrode. This results in increase of the surface area of the storage electrode opposed to the cell plate electrode, and, accordingly, the capacitance is increased without a wide occupation area. 
     A typical example of the complicated three-dimensional configuration is disclosed in Japanese Patent Publication of Unexamined Application No. 1-270344. The configuration of the storage node electrode is called a “fin structure” or “fin storage node electrode”, and the fin storage node electrode opposes not only the top surface and the side surface but also the back surface to the cell plate, and widely increases the capacitance of the storage capacitor. The fin storage node electrode is located over the associated field effect transistor, and a bit line passes through an inter-level insulating layer between the field effect transistor and the fin storage node electrode. This feature is called a COB (Capacitor-Over-Bit line) structure. 
     Testing elements are usually incorporated in a semiconductor device, and are used for evaluating components of the semiconductor device. Of course, various testing elements are incorporated in the semiconductor dynamic random access memory device, and some testing elements are used for evaluating the storage node electrode. The manufacturer evaluates a mis-alignment between a node contact hole and a storage node electrode by using one of the testing elements, and measures a sheet resistance of the conductive material for the storage node electrode through another testing element. The manufacturer further checks yet another testing element to see whether or not a short-circuit takes place between adjacent two storage node electrodes. 
     FIG. 1 illustrates the layout of a typical example of the semiconductor dynamic random access memory device. The prior art semiconductor dynamic random access memory device is fabricated on a p-type silicon substrate  1 . The prior art semiconductor dynamic random access memory device comprises a memory cell array  2 , peripheral circuits such as a row address decoder  3   a  and a column address decoder  3   b  and testing elements  4   a ,  4   b  and  4   c.  A plurality of memory cells  2   a  form the memory cell array  2 , and are arranged in rows and columns. The row address decoder  3   a  selects a row of memory cells  2   a  from the memory cell array  2 , and the column address decoder  3   b  selects a memory cell  2   a  from the selected row of memory cells  2   a.    
     The memory cell array  2  occupies a central area of the semiconductor substrate  1 , and the peripheral circuits are located in an inner peripheral area around the memory cell array  2 . In this instance, the row address decoder  3   a  extends along one edge of the central area, and the column address decoder  3   b  is provided along another edge of the central area perpendicular to the edge. The testing elements  4   a  to  4   c  are assigned to an outer peripheral area around the inner peripheral area, and are located outside of the peripheral circuits. Thus, the memory cell array  2 , the peripheral circuits  3   a / 3   b  and the testing elements  4   a / 4   b / 4   c  are assigned the central area, the inner peripheral area and the outer peripheral area, respectively. 
     FIG. 2 illustrates the layout of the memory cell array. A dielectric film and a cell plate electrode are deleted from the layout for the sake of simplicity. One of the memory cells  2   a  is enclosed with broken line BKN, and includes a switching transistor  5  and a stacked type storage capacitor  6 . 
     An n-type impurity region  1   a  is shaped between two switching transistors  5  of adjacent two memory cells  2   a,  and is electrically connected to a bit line  7   a  through a bit line contact hole  8   a.  The bit line contact holes  8   a  are marked with “x” in FIG. 2 so as to be easily discriminated. 
     The half of the n-type impurity region  1   a  on the right side is assigned to the switching transistor  5  for the memory cell  2   a  enclosed with broken line BKN, and a word line  7   b  extends over the half of the n-type impurity region  1   a.  A part of the n-type impurity region  1   a  on the left side of the word line  7   b  and another part of the n-type impurity region  1   a  on the right side of the word line  7   b  serve as a drain region  5   a  and a source region  5   b  of the switching transistor  5 . 
     The source region  5   b  is electrically connected to a storage node electrode  6   b  through a node contact hole  8   b  also marked with “x”, and the storage node electrode  6   b  is opposed through a dielectric film (not shown in FIG. 2) to the cell plate (also not shown in FIG.  2 ). The storage node electrode  6   b  is elongated in a direction parallel to the bit line  7   a,  and occupies an area over two word lines  7   b.  The rows  2   b  of memory cells are alternated with the bit lines  7   a,  and the bit lines  7   a  extend in an inter-level insulating layer (not shown in FIG. 2) between the word lines  7   b  and the storage node electrodes  6   b  in a perpendicular direction to the word lines  7   b.  The word lines  7   b  are connected to the row address decoder  3   a,  and the bit lines  7   a  are connected to the column address decoder  3   b.    
     FIGS. 3A to  3 C illustrate the layouts of the testing elements  4   a,    4   b  and  4   c,  respectively. The manufacturer uses the testing element  4   a  to evaluate the alignment between the node contact holes  8   b  and the stem portions of the storage node electrodes  6   b,  and includes contact holes  4   d  marked with “x” and a polysilicon pattern  4   e  as shown in FIG.  3 A. The contact holes  4   d  are formed in an inter-level insulating layer (not shown in FIGS. 2 and 3A) concurrently with the node contact holes  8   b,  and are spaced from each other at predetermined intervals. On the other hand, the polysilicon pattern  4   e  is constituted by a plurality of polysilicon strips  4   f  spaced at the predetermined intervals, and the polysilicon strips  4   f  are patterned from a polysilicon layer concurrently with the storage node electrodes  6   b.  The contact holes  4   d  have a width equal to the width of the storage node electrodes  6   b,  and the length of the contact holes  4   d  is much longer than the length of the storage node electrodes  6   b.  The polysilicon strips  4   f  have a width equal to the width of the storage node electrodes  6   b,  and the length of the polysilicon strips  4   f  is equal to the length of the contact holes  4   d.  Therefore, a mis-alignment between the node contact holes  8   b  and the stems of the storage node electrodes  6   b  is transferred to the alignment between the contact holes  4   d  and the polysilicon strips  4   f.    
     The manufacturer uses the testing element  4   b  so as to measure the sheet resistance of the polysilicon for the storage node electrodes  6   b.  The testing element  4   b  is implemented by a polysilicon test pattern  4   g,  and a plurality of polysilicon strips  4   h  form in combination the polysilicon test pattern  4   g.  The polysilicon strips  4   h  are patterned from the polysilicon layer for the storage node electrodes  6   b,  and are broken down into three groups. All of the polysilicon strips  4   h  have respective pad portions  4   i  of ten microns square, and the pad portions  4   i  are wide enough to allow a probe (not shown) to come into contact therewith. Narrow portions  4   j,    4   k  and  4   m  project from the pad portions  4   i,  and are different in width from one another. The narrow portions  4   j  are equal to the width of the storage node electrodes  6   b.  However, the narrow portions  4   k  are, by way of example, twice as wide as the storage node electrodes  6   b,  and the narrow portions  4   m  are, by way of example, four times as wide as the storage node electrodes  6   b.  The sheet resistance is usually measured before the formation of the dielectric films on the storage node electrodes  6   b.    
     The manufacturer checks the testing element  4   c  to determine whether or not the storage node electrodes  6   b  are short circuited. The testing element  4   c  has n-type impurity regions (not shown in FIG. 3C) concurrently formed together with the source and drain regions  5   a / 5   b,  a plurality of contact holes  4   p,  which are marked with “x”, formed in the inter-level insulating layer concurrently with the node contact holes  8   b  and a plurality of polysilicon strips  4   qa,    4   qb  . . . formed from the polysilicon layer concurrently with the storage node electrodes  6   b.  The polysilicon strips  4   qa  and  4   qb  are wider than the storage node electrodes  6   b,  and are spaced from each other by a gap equal to that between the adjacent storage node electrodes  6   b.  The polysilicon strips  4   qa  and  4   qb  are much longer than the storage node electrodes  6   b,  and are of the order of 1 millimeter. The contact holes  4   p  are equal in dimensions to the note contact holes  8   b.  Although the polysilicon strip  4   qa  is electrically connected through the contact holes  4   p  to the impurity region, no contact hole is formed beneath the polysilicon strip  4   qb,  because the manufacturer does not expect the testing element  4   c  to detect a short-circuit between the impurity regions. The manufacturer checks the testing element  4   c  before the deposition of the dielectric films. 
     The structure of the prior art semiconductor dynamic random access memory device will now be described with reference to FIGS. 4 and 5A to  5 D. FIG. 4 shows the cross section taken along line IV—IV, and the structure of the memory cell and the structure of testing element  4   a  are seen in the cross section. Although two memory cells  2   a  are shown in FIG. 4, description is focused on one of the memory cells  2   a;  however, the components of the other memory cell  2   a  are labeled with the same references. 
     A thick field oxide layer  1   b  is selectively grown on the major surface of the p-type silicon substrate  1 , and defines an active area assigned to the two memory cells  2   a  in the central area. A channel region between the source and drain regions  5   a  and  5   b  is covered with a thin gate oxide layer  5   c,  and the word line  7   b  extends over the thin gate oxide layer  5   c.  A part of the word line  7   b  on the thin gate oxide layer  5   c  serves as a gate electrode, and the gate electrode, the thin gate oxide layer, the channel region and the source and drain regions  5   a / 5   b  as a whole constitute the switching transistor  5 . 
     A silicon oxide layer  8   c  covers the word lines  7   b  and exposed major surface, and is overlain by a first inter-level insulating layer  8   d.  The first inter-level insulating layer  8   d  is further overlain by a second inter-level insulating layer  8   e,  and the upper surface of the second inter-level insulating layer  8   e  is formed with a silicon nitride layer. The second inter-level insulating layer  8   e  is covered with a dielectric film  8   f  concurrently deposited together with the dielectric film  6   c.    
     The storage capacitor  6  is formed on the second inter-level insulating layer  8   e.  The node contact hole  8   b  passes through the dielectric film  8   f,  the first and second inter-level insulating layers  8   d / 8   e  and the silicon oxide layer  8   c,  and the source/drain region  5   b  is exposed to the node contact hole  8   b.  The stem of the storage node electrode  6   b  is held in contact through the node contact hole  8   b  with the source/drain region  5   b,  and an accumulating portion of the storage node electrode  6   b  projects from the dielectric film  8   f  because of the fin structure. The gap between the dielectric film  8   f  and the accumulating portion is narrower than the gap between the accumulating portions of the adjacent storage node electrodes  6   b.  The storage node electrode  6   b  over the dielectric film  8   f  is covered with the dielectric film  6   c,  and the dielectric film  6   c  is covered with the cell plate electrode  6   d.  The storage node electrode  6   b  and the cell plate electrode  6   d  are formed of n-type polysilicon. The storage node electrode  6   b,  the dielectric film  6   c  and the cell plate electrode  6   d  form in combination the storage capacitor  6 . 
     FIG. 5A illustrates the bit line  7   a.  The bit lines  7   a  extend over the first inter-level insulating layer  8   e,  and are held in contact through the bit contact hole  8   a  with the source/drain region  5   a.  The bit contact holes  8   a  are formed in the lamination of the silicon oxide layer  8   c  and the first inter-level insulating layer  8   d,  and reach the source/drain regions  5   a.    
     The COB structure is seen in FIG.  5 B. The word line  7   b  extends over the thick field oxide layer  1   b  and the gate oxide layer  5   c,  and the bit lines  7   a  extend on the first inter-level insulating layer  8   d  over the word line  7   b.  The storage capacitors  6  are formed on the dielectric film  8   f  over the bit lines  7   a.  Thus, the bit lines  7   a  are formed between the switching transistors  5  and the storage capacitors  6 . 
     Turning back to FIG. 4 of the drawings, the contact hole  4   d  of the testing element  4   a  is formed in the lamination of the silicon oxide layer  8   c,  the first and second inter-level insulating layers  8   d / 8   e  and the thick field oxide layer  1   b,  and reaches the p-type silicon substrate  1 . The bottom end of the contact hole  4   d  may be terminated at the inside of the thick field oxide layer  1   b.  The polysilicon strip  4   f  is partially provided over the lamination and partially in the contact hole  4   d  so as to be held in contact with the p-type silicon substrate  1 . 
     The structure of the testing element  4   b  is illustrated in FIG.  5 C. The polysilicon strips  4   m  are formed on residual phosphosilicate glass  9   a  over the second inter-level insulating layer  8   e,  and a gap takes place between the dielectric film  8   f  and the polysilicon strips  4   m.  The polysilicon strips  4   k / 4   j  are spaced from the dielectric film  8   f,  and some polysilicon strips  4   j  are broken as indicated by a broken line. The polysilicon strips  4   k / 4   m  are covered with dielectric films  4   r  deposited concurrently with the dielectric film  6   c,  and the residual n-type polysilicon fills the gap between the dielectric film  8   f  and the dielectric film  4   r.  The dielectric film  4   r  and the residual n-type polysilicon  4   s  are also observed in the structure of the testing element  4   a  (see FIG.  4 ). 
     The structure of the testing element  4   c  is illustrated in FIG.  5 D. The polysilicon strips  4   qa  and  4   qb  are patterned on the residual phosphosilicate glass  9   c  over the second inter-level insulating layer  8   e,  and a gap takes place between the dielectric film  8   f  and the polysilicon strips  4   qa / 4   qb.  The polysilicon strips  4   qa / 4   qb  are covered with the dielectric films  4   r,  and the residual n-type polysilicon  4   s  fills the gap between the dielectric films  4   r  and the dielectric film  8   f.  As described hereinbefore, the polysilicon strip  4   qa  is held in contact through the contact hole  4   p  with the n-type impurity region, and the n-type impurity region is labeled with reference  4   n.    
     The prior art semiconductor dynamic random access memory device is fabricated as follows. FIGS. 6A to  6 E illustrate the prior art process sequence, and show the cross section taken along line VI—VI of FIG.  1 . 
     First, the p-type silicon substrate  1  is prepared. The thick field oxide layer  1   b  is selectively grown on the major surface of the p-type silicon substrate  1 , and defines the active area assigned to two memory cells  2   a.    
     The thin gate oxide layers  5   c  are grown on the active area, and polysilicon is deposited over the entire surface of the structure. A photo-resist etching mask (not shown) is formed on the polysilicon layer by using lithographic techniques, and the polysilicon layer is patterned into the word lines  7   b.  N-type dopant impurity is ion implanted into the active area, and forms the n-type source/drain regions  5   a / 5   b  in a self-aligned manner with the word lines  7   b  on the gate oxide layers  5   c.  The n-type dopant impurity further forms the n-type impurity regions  4   n  of the testing element  4   c.  Thus, the switching transistors  5  are fabricated on the p-type silicon substrate  1 . 
     Subsequently, silicon oxide is deposited over the entire surface of the resultant structure by using a low-pressure chemical vapor deposition, and the thick field oxide layer  1   b,  the word lines  7   b  and the n-type source/drain regions  5   a / 5   b  are covered with the silicon oxide layer  8   c.  Boro-phosphosilicate glass is deposited over the silicon oxide layer, and the boro-phosphosilicate glass layer is reflowed. Silicon oxide is deposited over the boro-phosphosilicate glass layer, and the boro-phosphosilicate glass layer and the silicon oxide layer form in combination the first inter-level insulating layer  8   d.    
     A photo-resist etching mask (not shown) is formed on the first inter-level insulating layer  8   d,  and the first inter-level insulating layer  8   d  and the silicon oxide layer  8   c  are selectively etched away so as to form the bit contact holes  8   a  (not shown in FIGS. 6A to  6 E). Conductive material is deposited over the first inter-level insulating layer. The conductive material fills the bit contact holes  8   a,  and swells into a conductive material layer. A photo-resist etching mask (not shown) is formed on the conductive material layer, and is patterned into the bit lines  7   a  (not shown in FIGS. 6A to  6 E). 
     Boro-phosphosilicate glass is deposited over the bit lines  7   a  on the first inter-level insulating layer  8   d,  and the boro-phosphosilicate glass layer is reflowed. Silicon nitride is deposited over the boro-phosphosilicate glass layer, and the boro-phosphosilicate glass layer and the silicon nitride layer form in combination the second inter-level insulating layer  8   e.  On the silicon nitride layer of the second inter-level insulating layer is deposited phosphosilicate glass which forms a spacing layer  9   a  as shown in FIG.  6 A. 
     A photo-resist etching mask (not shown) is formed on the spacing layer  9   a,  and the spacing layer  9   a,  the first and second inter-level insulating layers  8   d / 8   e  and the silicon oxide layer  8   c  are selectively removed so as to form the node contact holes  8   b  and the contact holes  4   p  of the testing element  4   c.  The photo-resist etching mask allows the etchant to further selectively remove the spacing layer  9   a,  the first and second inter-level insulating layers  8   d / 8   e,  the silicon oxide layer  8   c  and the thick field oxide layer  1   b  so as to form the contact holes  4   d  of the testing element  4   a.  The node contact holes  8   b  reach the n-type source/drain regions  5   b,  and, accordingly, the n-type source/drain regions  5   b  are exposed to the node contact holes  8   b  as shown in FIG.  6 B. The n-type impurity region  4   n  is exposed to the contact hole  4   p,  and the p-type silicon substrate  1  is exposed to the contact holes  4   d.    
     Subsequently, n-type polysilicon is deposited over the entire surface of the spacing layer  9   a.  The n-type polysilicon fills the node contact holes  8   b  and the contact holes  4   d / 4   p,  and swells into an n-type polysilicon layer  9   b  as shown in FIG.  6 C. 
     A photo-resist etching mask (not shown) is formed on the n-type polysilicon layer  9   b,  and the n-type polysilicon layer  9   b  is patterned into the storage node electrodes  6   b  and the polysilicon strips  4   f,    4   h,    4   qa  and  4   qb  as shown in FIG.  6 D. 
     Using dilute hydrofluoric acid, the spacing layer  9   a  is isotropically etched away, and a gap takes place between the storage node electrodes/ the narrow polysilicon strips  6   b / 4   f / 4   j / 4   k  and the second inter-level insulating layer  8   e  as shown in FIG.  6 E. However, the phosphosilicate glass  9   c  is left under the wide polysilicon strips  4   h  and  4   m  (see FIGS.  5 C and  5 D). The dielectric film is formed on the storage node electrodes  6   b,  and, accordingly, the polysilicon strips  4   f,    4   h,    4   qa,    4   qb  and the second inter-level insulating layer  8   e  are covered with the same dielectric films  8   f  and  4   r.  Finally, the n-type polysilicon is deposited over the entire surface of the structure, and the n-type polysilicon layer is patterned into the cell plate electrodes  6   d.    
     However, the prior art semiconductor dynamic random access memory device encounters a problem in that the testing elements are broken before the evaluation. This means that the manufacturer can not reliability evaluate the components by using the testing elements  4   a  to  4   c,  and the measured values are not matched with the actual properties of the components. In fact, some measured sheet resistances obtained from the testing elements  4   b  are larger in value than the sheet resistance of the storage node electrode  6   c.  Although the testing element  4   c  does not inform the manufacturer of a short-circuit, the storage node electrodes  6   b  are actually short-circuited. 
     SUMMARY OF THE INVENTION 
     It is therefore an important object of the present invention to provide a semiconductor device which has unbreakable testing elements. 
     It is also an important object of the present invention to provide a process of fabricating the semiconductor device with the unbreakable testing elements. 
     The present inventor contemplated the problem of the prior art semiconductor dynamic random access memory device, and noticed that the broken testing elements were narrow polysilicon strips  4   j  and  4   k.  The polysilicon strips  4   j  were much more likely to be broken rather than the polysilicon strips  4   k.  On the other hand, although some peripheries of the wide polysilicon strips such as  4   f,    4   i,    4   m  and  4   qa / 4   qb  were chipped off, no wide polysilicon strips  4   f,    4   i,    4   m  and  4   qa / 4   qb  were completely broken. The polysilicon strips  4   f  were supported by the p-type silicon substrate  1 , and the polysilicon strips  4   m  and  4   qa / 4   qb  were supported by the residual phosphosilicate glass  9   c.  However, there was no support beneath the polysilicon strips  4   k / 4   j.  The present inventor concluded that the narrow polysilicon strips  4   k  and  4   m  were too small in strength to withstand the pressing force of the probe. The polysilicon strips that were chipped indicated an increased sheet resistance, and the broken pieces short circuited the storage node electrodes  6   b.    
     To accomplish the object, the present invention proposes to provide testing elements directly on an inter-level insulating layer. 
     In accordance with one aspect of the present invention, there is provided a semiconductor device fabricated on a semiconductor substrate, comprising: an inter-level insulating structure formed over a major surface of the semiconductor substrate; at least one circuit component formed on a first area of an upper surface of the inter-level insulating structure, and having a first member projecting from the first area of the inter-level insulating structure; and at least one testing element having at least one second member held in contact with a second area of the upper surface of the inter-level insulating structure and used for evaluating the first member of the at least one circuit component. 
     In accordance with another aspect of the present invention, there is provided a process of fabricating a semiconductor device, comprising the steps of: a) preparing a semiconductor substrate having a major surface containing a first area and a second area; b) forming an inter-level insulating structure over the major surface of the semiconductor substrate; c) forming a spacing layer on the inter-level insulating structure; d) removing a part of the spacing layer from a part of the inter-level insulating layer over the second area; e) forming a certain layer extending over a remaining part of the spacing layer over the first area and the part of the inter-level insulating layer; f) patterning the certain layer into a first member of at least one circuit component on the remaining part of the spacing layer and at least one second member of a testing element on the part of the inter-level insulating layer; g) removing the remaining part of the spacing layer so that the first member projects from the remaining part of the spacing layer; h) evaluating the first member by measuring a predetermined physical quantity of the at least one second member; and i) completing the at least one circuit component. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the semiconductor memory device and the process according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a plan view showing the layout of the prior art semiconductor dynamic random access memory device; 
     FIG. 2 is a plan view showing the layout of the memory cell array incorporated in the prior art semiconductor dynamic random access memory device; 
     FIGS. 3A to  3 C are plan views showing the layouts of the testing elements incorporated in the prior art semiconductor dynamic random access memory device; 
     FIG. 4 is a cross sectional views taken along line IV—IV of FIG.  1  and showing the structure of the memory cell and the testing element; 
     FIGS. 5A to  5 D are cross sectional views taken along lines V.A—V.A, V.B—V.B, V.C 13  V.C and V.D—V.D of FIGS. 2,  3 B and  3 C and showing the structures of the testing elements; 
     FIGS. 6A to  6 E are cross sectional views showing the process sequence of fabricating the prior art semiconductor dynamic random access memory device; 
     FIG. 7 is a plan view showing the layout of a semiconductor dynamic random access memory device according to the present invention; 
     FIG. 8 is a plan view showing the layout of the memory cell array incorporated in the semiconductor dynamic random access memory device; 
     FIGS. 9A to  9 C are plan views showing the layouts of the testing elements incorporated in the semiconductor dynamic random access memory device; 
     FIG. 10 is a cross sectional views taken along line X—X of FIG.  7  and showing the structure of the memory cell and the testing element; 
     FIGS. 11A to  11 D are cross sectional views taken along lines H—H, I—I, J—J and K—K of FIGS. 8,  9 B and  9 C and showing the structures of the testing elements; 
     FIGS. 12A to  12 E are cross sectional views showing a process sequence of fabricating the semiconductor dynamic random access memory device; 
     FIGS. 13A to  13 C are cross sectional view showing another process sequence of fabricating the semiconductor dynamic random access memory device; 
     FIG. 14 is a plan view showing the layout of another semiconductor dynamic random access memory device according to the present invention; 
     FIG. 15 is a plan view showing the layout of a memory cell array incorporated in the semiconductor dynamic random access memory device; 
     FIGS. 16A to  16 C are cross sectional views taken along lines M—M, N—N and O—O of FIG.  15  and showing the structure of the semiconductor dynamic random access memory device; and 
     FIGS. 17A to  17 F are cross sectional views taken along line XVII—XVII of FIG.  14  and showing a process of fabricating the semiconductor dynamic random access memory device. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
     Referring first to FIG. 7, a semiconductor device largely comprises a dynamic random access memory  10   a  and a testing facility  10   b,  and the dynamic random access memory  10   a  and the testing facility  10   b  are fabricated on a p-type silicon substrate  11 . 
     The prior art semiconductor dynamic random access memory device includes a memory cell array  12  and peripheral circuits such as a row address decoder  13   a  and a column address decoder  13   b,  and testing elements  14   a,    14   b  and  14   c  are incorporated in the testing facility  10   b.    
     A plurality of memory cells  12   a  form the memory cell array  12 , and are arranged in rows and columns. The row address decoder  13   a  selects a row of memory cells  12   a  from the memory cell array  12 , and the column address decoder  13   b  selects a memory cell  12   a  from the selected row of memory cells  12   a.    
     The memory cell array  12  occupies a central area of the semiconductor substrate  11 , and each memory cell  12   a  occupies an area of 0.9 micron by 1.8 microns. The peripheral circuits are located in an inner peripheral area around the memory cell array  12 . In this instance, the row address decoder  13   a  extends along one edge of the central area, and the column address decoder  13   b  is provided along another edge of the central area perpendicular to the edge. The testing elements  14   a  to  14   c  are assigned to an outer peripheral area around the inner peripheral area, and are located outside of the peripheral circuits. Thus, the memory cell array  12 , the peripheral circuits  13   a / 13   b  and the testing elements  14   a / 14   b / 14   c  are assigned the central area, the inner peripheral area and the outer peripheral area, respectively. 
     FIG. 8 illustrates the layout of the memory cell array  12 . A dielectric film and a cell plate electrode are deleted from the layout of the memory cell array  12  for the sake of simplicity. Adjacent two of the memory cells  12   a  are enclosed with broken lines BKN, and are assigned to an active area. The memory cell  12   a  includes an n-channel enhancement type switching transistor  15  and a stacked type storage capacitor  16 , and the n-channel enhancement type switching transistor  15  is electrically connected in series to the storage capacitor  16 . 
     An n-type impurity region  11   a  is shaped between the n-channel enhancement type switching transistors  15  of the adjacent two memory cells  12   a,  and is electrically connected to one of bit lines  17   a  through a bit line contact hole  18   a.  The bit line contact holes  18   a  are marked with “x” in FIG. 8 so as to be easily discriminated. 
     The half of the n-type impurity region  11   a  on the right side is assigned to the switching transistor  15  for the memory cell  12   a  enclosed with right broken line BKN, and one of word lines  17   b  extends over the half of the n-type impurity region  11   a.  A part of the n-type impurity region  11   a  on the left side of the word line  17   b  and another part of the n-type impurity region  11   a  on the right side of the word line  17   b  serve as a drain region  15   a  and a source region  15   b  of the switching transistor  15 . 
     A part of the n-type impurity region  11   a  between the drain region  15   a  and the source region  15   b  serves as a channel region, and the channel region is overlapped with a part of the word line  17   b  serving as a gate electrode. The gate electrode is 0.5 micron in gate length and 0.5 micron in gate width. 
     The source region  15   b  is electrically connected to a storage node electrode  16   b  through a node contact hole  18   b  also marked with “x”, and the storage node electrode  16   b  is opposed through the dielectric film (not shown in FIG. 8) to the cell plate (also not shown in FIG.  8 ). The storage node electrode  16   b  measures 0.4 micron in width and 1.3 micron in length, and adjacent two storage node electrodes  16   b  are spaced by 0.5 micron. The storage node electrode  16   b  is elongated in a direction parallel to the bit line  17   a,  and two word lines  17   b  are overlapped with the storage node electrode  16   b.  The rows  12   b  of memory cells  12   a  are alternated with the bit lines  17   a,  and the bit lines  17   a  extend in an inter-level insulating layer (not shown in FIG. 8) between the word lines  17   b  and the storage node electrodes  16   b  in a perpendicular direction to the word lines  17   b.  The word lines  17   b  are connected to the row address decoder  13   a,  and the bit lines  17   a  are connected to the column address decoder  13   b.    
     FIGS. 9A to  9 C illustrate the layouts of the testing elements  14   a,    14   b  and  14   c,  respectively. The manufacturer uses the testing element  14   a  so as to evaluate the alignment between the node contact holes  18   b  and the stem portions of the storage node electrodes  16   b,  and includes contact holes  14   d  marked with “x” and a pattern of polysilicon strips  14   f  (see FIG.  9 A). The contact holes  14   d  are formed in an inter-level insulating layer (not shown in FIG. 9A) concurrently with the node contact holes  18   b,  and are spaced from each other at predetermined intervals. On the other hand, the polysilicon strips  14   f  are patterned from an n-type polysilicon layer concurrently with the storage node electrodes  16   b.    
     The contact holes  14   d  have a width equal to the width of the storage node electrodes  16   b  to be designed, i.e., 0.4 micron, and the length of the contact holes  14   d  is much longer than the length of the storage node electrodes  16   b,  i..e, 1.3 microns. The polysilicon strips  14   f  have a width equal to the width of the storage node electrodes  16   b,  and the length of the polysilicon strips  14   f  is equal to the length of the contact holes  14   d.  Therefore, a mis-alignment between the node contact holes  18   b  and the storage node electrodes  16   b  is transferred to the alignment between the contact holes  14   d  and the polysilicon strips  14   f.    
     The manufacturer uses the testing element  14   b  so as to measure the sheet resistance of the n-type polysilicon for the storage node electrodes  16   b.  The testing element  14   b  is implemented by a polysilicon test pattern  14   g  as shown in FIG. 9B, and a plurality of polysilicon strips  14   h  form in combination the polysilicon test pattern  14   g.  The polysilicon strips  14   h  are also patterned from the n-type polysilicon layer for the storage node electrodes  16   b,  and are broken down into three groups. All of the polysilicon strips  14   h  have respective pad portions  14   i  of ten microns square, and the pad portions  14   i  are wide enough to allow a probe (not shown) to come into contact therewith. Narrow portions  14   j,    14   k  and  14   m  project from the pad portions  14   i,  and are different in width from one another. The narrow portions  14   j  are equal to the width of the storage node electrodes  16   b.  However, the narrow portions  14   k  are, by way of example, twice as wide as the storage node electrodes  16   b,  and the narrow portions  14   m  are, by way of example, four times as wide as the storage node electrodes  16   b.  The sheet resistance is usually measured before the formation of the dielectric films on the storage node electrodes  16   b.    
     The manufacturer checks the testing element  14   c  to determine whether or not the storage node electrodes  16   b  are short circuited. As shown in FIG. 9C, the testing element  14   c  has n-type impurity regions (not shown in FIG. 9C) concurrently formed together with the n-type drain and source regions  15   a / 15   b,  a plurality of contact holes  14   p,  which are marked with “x”, formed in the inter-level insulating layer concurrently with the node contact holes  18   b  and a plurality of polysilicon strips  14   qa,    14   qb,  . . . formed from the n-type polysilicon layer concurrently with the storage node electrodes  16   b.  The polysilicon strips  14   qa  and  14   qb  are wider than the storage node electrodes  16   b,  and are spaced from each other by a gap equal to that between the adjacent storage node electrodes  16   b.  The polysilicon strips  14   qa  and  14   qb  are much longer than the storage node electrodes  6   b,  and are of the order of 1 millimeter. The contact holes  14   p  are equal in dimensions to the note contact holes  18   b.  Although the polysilicon strip  14   qa  is electrically connected through the contact holes  14   p  to the n-type impurity region, no contact hole is formed beneath the polysilicon strip  14   qb,  because the manufacturer does not expect the testing element  14   c  to detect a short-circuit between the impurity regions. The manufacturer checks the testing element  14   c  before the deposition of the dielectric films. 
     The structure of the semiconductor device will now be described with reference to FIGS. 10 and 11A to  11 D. FIG. 10 shows the cross section taken along line X—X, and the structure of the memory cell  12   a  and the structure of testing element  14   a  are seen in the cross section. Although two memory cells  12   a  are shown in FIG. 10, description is focused on one of the memory cells  12   a;  however, the components of the other memory cell  12   a  are labeled with the same references. 
     A thick field oxide layer  11   b  is selectively grown on the major surface of the p-type silicon substrate  11 , and defines the active area assigned to the two memory cells  12   a  in the central area. The thick field oxide layer  11   b  is of the order of 300 nanometers thick. 
     The drain region  15   a  and the source region  15   b  have an LDD (Lightly-Doped Drain) structure, and form p-n junctions at 0.15 micron deep from the major surface of the p-type silicon substrate  11 . The channel region between the source region  15   b  and the drain regions  15   a  is covered with a thin gate oxide layer  15   c  of 10 nanometers thick, and the word line  17   b  extends over the thin gate oxide layer  15   c.  The thin gate oxide layer  15   c  is overlain by the gate electrode, and the gate electrode, the thin gate oxide layer  15   c,  the channel region and the source region  15   b  and the drain region  15   a  as a whole constitute the switching transistor  15 . 
     The word line  17   b  and, accordingly, the gate electrode have a multi-layer structure of an n-type polysilicon strip of 100 nanometers thick and a tungsten silicide strip of 100 nanometers thick. 
     A silicon oxide layer  18   c  covers the word lines  17   b  and exposed major surface, and is or the order of 100 nanometers thick. The silicon oxide layer  18   c  prevents the n-type drain region  15   a  and the n-type source region  15   b  from boron diffused from a first inter-level insulating layer  18   d  described hereinbelow. 
     The silicon oxide layer  18   c  is overlain by the first inter-level insulating layer  18   d,  and the first inter-level insulating layer  18   d  is formed of boro-phosphosilicate glass. The first inter-level insulating layer  18   d  is of the order of 300 nanometers thick, and has been reflowed. 
     Turning to FIG. 11A of the drawings, the bit contact hole  18   a  passes through the first inter-level insulating layer  18   d  and the silicon oxide layer  18   c,  and the n-type drain region  15   a  is exposed to the bit contact hole  18   a.  Although the bit contact hole  18   a  is designated to be 0.4 micron square, the bit contact hole  18   a  is as narrow as 0.2 micron square in the actual product. The bit lines  17   a  extend on the first inter-level insulating layer  17   a,  and is 0.4 micron in width. The bit lines  17   a  have a multi-layer structure formed from an n-type polysilicon strip of 150 nanometers thick and a tungsten silicide strip of 100 nanometers thick. 
     Turning back to FIG. 10 of the drawings, the first inter-level insulating layer  18   d  is further overlain by a second inter-level insulating layer  18   e,  and the second inter-level insulating layer  18   e  is formed from a boro-phosphosilicate glass layer of 400 nanometers thick and a silicon nitride layer of 100 nanometers thick on the boro-phosphosilicate glass layer. The boro-phosphosilicate glass layer has been reflowed. The second inter-level insulating layer  18   e  is covered with a dielectric film  18   f  concurrently deposited together with the dielectric film of the storage node electrodes  16   b.    
     The storage capacitor  16  is formed on the second inter-level insulating layer  18   e.  The node contact hole  18   b  passes through the dielectric film  18   f,  the first and second inter-level insulating layers  18   d / 18   e  and the silicon oxide layer  18   c,  and the source region  15   b  is exposed to the node contact hole  18   b.  The node contact hole  18   b  is designed to be 0.4 micron square; however, the actual node contact hole  18   b  is 0.2 micron square. 
     The storage node electrodes  16   b  are formed of n-type polysilicon, and are 600 nanometers thick. The storage node electrode  16   b  is broken down into a stem and an accumulating portion, and has the fin structure. The stem passes through the node contact hole  18   b,  and is held in contact with the source region  15   b.  The accumulating portion of the storage node electrode  16   b  projects over the dielectric film  18   f,  and the gap between the accumulating portion and the second inter-level insulating layer  18   e  is of the order of 0.4 micron, and is narrower than the gap between the adjacent storage node electrodes  16   b.    
     The storage node electrode  16   b  over the second inter-level insulating layer  18   e  is covered with the dielectric film  16   c,  and the dielectric film  16   c  is covered with the cell plate electrode  16   d.  The cell plate electrodes  16   d  are formed of n-type polysilicon, and are of the order of 200 nanometers thick. The gap between the dielectric films  18   f  and  16   c  is filled with the cell plate electrode  16   d.  The storage node electrode  16   b,  the dielectric film  16   c  and the cell plate electrode  16   d  form in combination the storage capacitor  16 . 
     The COB structure is seen in FIG.  11 B. The word line  17   b  extends over the thick field oxide layer  11   b  and the gate oxide layer  15   c,  and the bit lines  17   a  extend on the first inter-level insulating layer  18   d  over the word line  17   b.  The storage capacitors  16  are formed on the dielectric film  18   f  over the bit lines  17   a.  Thus, the bit lines  17   a  are formed between the switching transistors  15  and the storage capacitors  16 . 
     Turning back to FIG. 10 of the drawings, the contact hole  14   d  of the testing element  14   a  is formed in the lamination of the silicon oxide layer  18   c,  the first and second inter-level insulating layers  18   d / 18   e  and the thick field oxide layer  11   b,  and reaches the p-type silicon substrate  11 . The bottom end of the contact hole  14   d  may be terminated at the inside of the thick field oxide layer  11   b  in another embodiment. 
     The polysilicon strip  14   f  is partially provided on the second inter-level insulating layer  18   e  and partially in the contact hole  14   d  so as to be held in contact with the p-type silicon substrate  1 . There is no gap between the second inter-level insulating layer  18   e  and the polysilicon strip  14   f,  and, accordingly, residual n-type polysilicon is not left between the second inter-level insulating layer  18   e  and the polysilicon strip  14   f.    
     The structure of the testing element  14   b  is illustrated in FIG.  11 C. The polysilicon strips  14   j,    14   k  and  14   m  are formed on the second inter-level insulating layer  18   e.  Any gap does not occur between the second inter-level insulating layer  18   e  and the polysilicon strips  14   j / 14   k / 14   m,  and, accordingly, no residual phosphosilicate glass and no residual polysilicon is inserted between the second inter-level insulating layer  18   e  and the polysilicon strips  4   j / 4   k / 4   m.  The polysilicon strips  4   k / 4   m  are covered with a dielectric film  14   r  deposited concurrently with the dielectric film  16   c.    
     The structure of the testing element  14   c  is illustrated in FIG.  11 D. The polysilicon strips  14   qa  and  14   qb  are directly patterned on the second inter-level insulating layer  18   e,  and no gap occurs between the second inter-level insulating layer  18   e  and the polysilicon strips  14   qa / 14   qb.  The polysilicon strips  14   qa / 14   qb  are covered with the dielectric films  14   r.  As described hereinbefore, the polysilicon strip  14   qa  is held in contact through the contact holes  14   p  with the n-type impurity region, and the n-type impurity region is labeled with reference  14   n.    
     The semiconductor device according to the present invention is fabricated as follows. FIGS. 12A to  12 E illustrate a process sequence, and show the cross section taken along line XII—XII of FIG.  7 . 
     First, the p-type silicon substrate  11  is prepared. The thick field oxide layer  11   b  is selectively grown to 300 nanometers thick on the major surface of the p-type silicon substrate  11  by using the LOCOS (local oxidation of silicon) technology, and defines the active area assigned to two memory cells  12   a.    
     The active areas are thermally oxidized, and the thin gate oxide layers  15   c  are grown to 10 nanometers thick on the active area. N-type polysilicon is deposited to 100 nanometers thick over the entire surface of the structure, and tungsten silicide is further deposited to 100 nanometers thick over the n-type polysilicon layer. A photo-resist etching mask (not shown) is formed on the tungsten silicide layer by using lithographic techniques, and the tungsten silicide layer and the polysilicon layer are patterned into the word lines  17   b.  Phosphorous is ion implanted into the active area, and side wall spacers are formed on the side surfaces of the word lines  17   b.  Arsenic is ion implanted into the active area, and the phosphorous and the arsenic forms the n-type drain and source regions  15   a / 15   b  of the LDD structure in a self-aligned manner with the word lines  17   b  The n-type dopant impurities further form the n-type impurity regions  14   n  of the testing element  14   c.  In this way, the switching transistors  15  are fabricated on the p-type silicon substrate  11 . 
     Subsequently, the semiconductor substrate  11  is placed in a reactor of a low-pressure chemical vapor deposition system (not shown), and gaseous mixture containing silane (SiH 4 ) and dinitrogen monoxide (N 2 O) is introduced into the reactor. Then, silicon oxide is deposited to 100 nanometers thick over the entire surface of the resultant structure at 800 degrees in centigrade, and the silicon oxide forms a good step-coverage. The thick field oxide layer  11   b,  the word lines  17   b  and the n-type drain/source regions  15   a / 15   b  are covered with the silicon oxide layer  18   c.  The silicon oxide thus produced is hereinbelow called as “HTO”. 
     Boro-phosphosilicate glass is deposited over the silicon oxide layer  18   c,  and the boro-phosphosilicate glass layer is reflowed at 750 degrees to 900 degrees in centigrade. The boro-phosphosilicate glass forms the first inter-level insulating layer  18   d.  The boro-phosphosilicate glass is produced by decomposing gaseous mixture of TEOS (tetraethylorthosilicate), PH 3 ), B(OCH 3 ) 3  and O 2  in the reactor of the low-pressure chemical vapor deposition system. The boro-phosphosilicate glass may be produced from gaseous mixture containing TEOS, P(OCH 3 ) 3 , B(OCH 3 ) 3  or B(OC 2 H 5 ) 3  and O 3  in a reactor of an atmospheric pressure chemical vapor deposition system. The first inter-level insulating layer  18   d  may be formed of phosphosilicate glass. 
     A photo-resist etching mask (not shown) is formed on the first inter-level insulating layer  18   d,  and the first inter-level insulating layer  18   d  and the silicon oxide layer  18   c  are selectively removed by using a reactive ion etching technique so as to form the bit contact holes  18   a  (not shown in FIGS. 12A to  12 E). CF 4  is available for the reactive ion etching. Though not shown in FIG. 11A, an HTO layer is deposited over the entire surface of the structure, and the HTO layer is anisotropically etched so as to form a spacer on the inner surface defining the bit contact holes  18   a.    
     N-type polysilicon is deposited to 150 nanometers thick over the first inter-level insulating layer. The n-type polysilicon fills the bit contact holes  18   a,  and swells into an n-type polysilicon layer. Tungsten silicide is further deposited to 100 nanometers thick on the n-type polysilicon layer. A photo-resist etching mask (not shown) is formed on the tungsten silicide layer, and the n-type polysilicon layer and the tungsten silicide layer are patterned into the bit lines  17   a  (not shown in FIGS. 12A to  12 E). 
     Boro-phosphosilicate glass is deposited to 400 nanometers thick over the bit lines  17   a  on the first inter-level insulating layer  18   d,  and the boro-phosphosilicate glass layer is reflowed. Silicon nitride is deposited to 100 nanometers thick over the boro-phosphosilicate glass layer, and the boro-phosphosilicate glass layer and the silicon nitride layer form in combination the second inter-level insulating layer  18   e.  The silicon nitride is produced from gaseous mixture containing SiH 2 Cl 2  and NH 3  by using a low pressure chemical vapor deposition. The silicon nitride layer may be replaced with a silicon oxide layer or an NSG layer deposited by using an atmospheric pressure chemical vapor deposition. 
     On the silicon nitride layer of the second inter-level insulating layer  18   e  is deposited phosphosilicate glass which forms a spacing layer  19   a  as shown in FIG.  12 A. The spacing layer  19   a  is 400 nanometers thick. The spacing layer  19   a  may be formed of boro-phosphosilicate glass. 
     A photo-resist etching mask (not shown) is formed on the spacing layer  19   a,  and has an opening exposing the outer peripheral area. Using the photo-resist etching mask, the spacing layer  19   a  is selectively removed over the outer peripheral area by using etching gas containing C 4 F 8  and CO, and the second inter-level insulating layer  18   e  is partially exposed. The etching gas may contain CHF 3  and CO. Thus, the spacing layer  19   a  is removed from the outer peripheral area, and still covers at least the central area assigned to the memory cell array  12 . In case where the silicon layer or the NSG layer forms the upper surface of the second inter-level insulating layer  18   e,  the phosphosilicate glass layer  19   a  is selectively etched away by using buffered hydrofluoric acid. HF and NH 4 F are preferably regulated to 1:30. 
     Subsequently, a photo-resist etching mask (not shown) is provided for the node contact holes  18   b,  the contact holes  14   d  and the contact holes  14   p,  and has openings over the n-type source regions  15   b  and the outer peripheral area. Using the photo-resist etching mask, the spacer layer  19   a,  the second inter-level insulating layer  18   e,  the first inter-level insulating layer  18   d  and the silicon oxide layer  18   c  are selectively etched away so as to form the node contact holes  18   b  as shown in FIG. 12B, and the n-type source regions  15   b  are exposed to the node contact holes  18   b.  The photo-resist etching mask further allows the etchant to remove the first and second inter-level insulating layers  18   d / 18   e,  the silicon oxide layer  18   c  and the thick field oxide layer  11   b  so as to form the contact holes  14   d  of the testing element  14   a  and to remove the first and second inter-level insulating layers  18   d / 18   e  and the silicon oxide layer  18   c  for forming the contact holes  18   p  of the testing elements  14   c.  The p-type silicon substrate  11  is exposed to the contact holes  14   d,  and the n-type impurity region  14   n  is exposed to the contact holes  14   p.  Side wall spacers are formed on the inner surfaces defining the node contact holes  18   b,  the contact holes  14   d  and the contact holes  14   p  as similar to the bit contact holes  18   a.    
     Subsequently, the p-type silicon substrate  11  is placed in a reactor of a low-pressure chemical vapor deposition system, and gaseous mixture containing silane/disilane and phosphine is introduced into the reactor. N-type polysilicon is deposited over the entire surface of the spacing layer  19   a  over the at least central area and the second inter-level insulating layer  18   e  over the outer peripheral area, and the dopant concentration of the n-type polysilicon is of the order of 1.5×10 20  cm 31 3 . The n-type polysilicon fills the node contact holes  18   b  and the contact holes  14   d / 14   p,  and swells into an n-type polysilicon layer  19   b  of 600 nanometers thick as shown in FIG.  12 C. 
     Amorphous silicon may be deposited, and n-type dopant impurity may be introduced into the amorphous silicon through in-situ doping. In this instance, it is advantageous to convert the amorphous silicon to polysilicon before a deposition of the dielectric film  16   c,  because the sheet resistance is too high. 
     A photo-resist etching mask (not shown) is formed on the n-type polysilicon layer  19   b,  and selectively exposes the n-type polysilicon layer  19   b  to gaseous etchant of a reactive ion etching such as, for example, HBr. Thus, the n-type polysilicon layer  19   b  is patterned into the storage node electrodes  16   b  and the polysilicon strips  14   f,    14   h,    14   qa  and  14   qb  as shown in FIG.  12 D. 
     Using dilute hydrofluoric acid, the spacing layer  19   a  is isotropically etched away, and a gap takes place between the storage node electrodes  16   b  and the second inter-level insulating layer  18   e.  The polysilicon strips  14   f,    14   h,    14   qa  and  14   qb  are directly formed on the second inter-level insulating layer  18   e  as shown in FIG. 12E, and no gap takes place under the polysilicon strips  14   f,    14   h,    14   qa  and  14   qb  (see FIGS. 10,  11 C,  11 D and  12 E). 
     The dielectric films  16   c,    18   f  and  14   r  cover the storage node electrodes  16   b,  the second inter-level insulating layer  18   e  and the polysilicon strips  14   f,    14   h,    14   qa,    14   qb.  In this instance, silicon nitride is deposited to 7 nanometers thick over the entire surface of the structure, and a surface portion of the silicon nitride layer is converted to silicon oxide by using pyrogenic oxidation in wet ambience at 800 degrees in centigrade. Thus, the dielectric film is implemented by the lamination of silicon nitride layer and silicon oxide layer, and is equivalent to a silicon oxide film of 5 nanometers thick. 
     Finally, n-type polysilicon is deposited to 200 nanometers thick over the entire surface of the structure as similar to the n-type polysilicon for the storage node electrodes  16   b,  and the n-type polysilicon layer is patterned into the cell plate electrodes  16   d.  The storage node electrode  16   b,  the dielectric film  16   c  and the cell plate electrode  16   d  as a whole constitute the storage capacitor  16 . 
     Thereafter, steps well know to a person skilled in the art are carried out, and the semiconductor device is completed. 
     As will be appreciated from the foregoing description, the polysilicon strips  14   d,    14   h,    14   qa  and  14   qb  are directly held in contact with the second inter-level insulating layer  18   e,  and are never broken nor chipped off during the patterning step of the n-type polysilicon layer  19   b.  For this reason, the manufacturer can evaluate the properties of the storage node electrode  16   b,  and the semiconductor device is improved in reliability. Moreover, any broken polysilicon piece does not short circuit the storage node electrodes  16   b,  and the production yield is enhanced. 
     In this instance, the silicon oxide layer  18   c,  the first inter-level insulating layer  18   d  and the second inter-level insulating layer  18   e  as a whole constitute an inter-level insulating structure, and the storage node electrode  16   b  of the storage capacitor  16  serves as a first member of at least one circuit component. One of the polysilicon strips  14   d / 14   h / 14   qa / 14   qb  serves as at least one second member. The n-type polysilicon layer  19   b  serves as a first layer. 
     The process sequence described hereinbefore may be modified as follows. FIGS. 13A to  13 C illustrates another process of fabricating the semiconductor device shown in FIGS. 10 and 11A to  11 D. The modified process sequence is similar to that of the process shown in FIGS. 12A to  12 E until the formation of the bit lines  17   a.  For this reason, layers, regions and contact holes in the modified process are labeled with the references designating the corresponding layers, regions and contact holes of the structure shown in FIGS. 12A to  12 E without detailed description for avoiding repetition. 
     Upon completion of the bit lines  17   a,  the phosphosilicate glass is deposited over the bit lines  17   a  and the first-inter-level insulating layer  18   d,  and silicon oxide is deposited over the phosphosilicate glass layer for forming the NSG layer. The phosphosilicate glass layer and the NSG layer form in combination the second inter-level insulating layer  28   e.  The second inter-level insulating layer  28   e  is overlain by a spacing layer (not shown in FIGS. 13A to  13 C) corresponding to the spacing layer  19   a.    
     The spacing layer is etched away from the second inter-level insulating layer over at least the outer peripheral area, and the spacing layer remains on the second inter-level insulating layer  28   e  over at least the central area. The node contact holes  18   b  and the contact holes  14   d  and  14   p  (not shown in FIGS. 13A to  13 C) are formed as similar to the process described hereinbefore, and polysilicon is deposited over the second inter-level insulating layer  28   e.  The polysilicon fills the node contact holes  18   b  and the contact holes  14   d / 14   p,  and swells into the polysilicon layer. The polysilicon layer is patterned into the storage node electrodes  16   b  and the polysilicon strips  14   d / 14   h / 14   qa / 14   qb.  Silicon nitride is deposited to 7 nanometers thick over the entire surface of the structure, and a silicon nitride layer  29   a  topographically extends over the surfaces of the storage node electrodes  16   b  and the second inter-level insulating layer  28   e  as shown in FIG.  13 A. 
     A photo-resist etching mask (not shown) is provided over the silicon nitride layer  29   a,  and exposes the silicon nitride layer  29   a  over the outer peripheral area to etching gas containing CF 4  and O 2  for a reactive ion etching. Then, the silicon nitride layer  29   a  over the outer peripheral area is etched away, and the second inter-level insulating layer  28   e  over the outer peripheral area is exposed again as shown in FIG.  13 B. However, the silicon nitride layer  29   a  still covers the sources of the storage node electrodes  16   b  and the second inter-level insulating layer  28   e  over the at least central area. 
     The silicon nitride layer  29   a  and the polysilicon strips  14   d / 14   h / 14   qa / 14   qb  are subjected to the pyrogenic oxidation. The silicon nitride layer  29   a  and the silicon oxide form in combination the dielectric film  16   c,  and the polysilicon strips  14   d / 14   h / 14   qa / 14   qb  are covered with silicon oxide layers  29   b  of at least 10 nanometers thick as shown in FIG.  13 C. 
     The modified process achieves all the advantages of the process implementing the first embodiment. The modified process is advantageous in wide selection of etching conditions for the cell plate electrode  16   d,  because the polysilicon strips  14   d / 14   h / 14   qa / 14   qb  are covered with the silicon oxide layers thicker than that of the dielectric film  16   c.    
     Second Embodiment 
     FIGS. 14,  15  and  16 A to  16 C illustrate another semiconductor device embodying the present invention. The semiconductor device is fabricated on a p-type silicon substrate  31 , and largely comprises a dynamic random access memory and a testing facility as similar to the first embodiment. 
     The dynamic random access memory device includes a memory cell array  32  and peripheral circuits  33 , and a central area, an inner peripheral area and an outer peripheral area are respectively assigned to the memory cell array  32 , the peripheral circuits  33  and the testing facility  34 . The memory cell array  32  is implemented by a plurality of memory cells  32   a  arranged in rows and columns, and a row address decoder  33   a  and a column address decoder  33   b  are examples of the peripheral circuit  33 . The testing facility includes testing elements  34   a,    34   b  and  34   c,  and the testing elements  34   a  to  34   c  , correspond to the testing elements  14   a  to  14   c,  respectively. For this reason, no further description is made on the testing elements  34   a  to  34   c,  and the components of the testing elements  34   a  to  34   c  are hereinbelow labeled with the references designating the corresponding components of the testing elements  14   a  to  14   c  for the sake of simplicity. 
     A series combination of an n-channel enhancement type switching transistor  35  and a stacked storage capacitor  36  serves as the memory cell  32   a.  The stacked storage capacitor  36  is different in structure from the stacked storage capacitor  16  as will be described hereinlater. 
     As shown in FIG. 15, the layout of the memory cell array  32  is similar to the memory cell array  12 , and one of the memory cells  32   a  is enclosed with broken line BKN. Bit lines, word lines, an n-type drain region, an n-type source region, a storage node electrode, a bit contact hole and a node contact hole are labeled with  37   a,    37   b,    35   a,    35   b,    36   b,    38   a  and  38   b,  respectively. The memory cell  32   a  is equal in size to the memory cell  12   a,  and measures 0.9 micron in width and 1.8 microns in length. 
     The structure of the memory cell  32   a  and the structure of an inter-level insulating structure are shown in FIG.  16 A. Two memory cells  32   a  are assigned an active area defined by a thick field oxide layer  31   b  selectively grown on the major surface of the p-type silicon substrate  31 . A thin gate insulating layer  35   c  of 10 nanometers thick covers a channel region between the n-type drain region  35   a  and the n-type drain region  35   b,  and the n-type drain region  35   a  and the n-type drain region  35   b  have the LDD structure. The n-type drain region  35   a  and the n-type source region  35   b  form p-n junctions around 0.15 micron in depth. 
     The thin gate insulating layer  35   c  is overlain by a part of the word line  37   b,  and the part of the word line  37   b  serve as a gate electrode of the n-channel enhancement type switching transistor  35 . The gate electrode is 0.4 micron in gate length and 0.5 micron in gate width. The word line  37   b  has a laminated structure of an n-type polysilicon strip of 100 nanometers thick and a tungsten silicide strip of 100 nanometers thick. 
     The n-channel enhancement type switching transistors  35  are covered with a silicon oxide layer  38   c  of 100 nanometers thick, and the silicon oxide layer  38   c  in turn is covered with a first inter-level insulating layer  38   d.  A flat surface is created on the first inter-level insulating layer  38   d  through a chemical mechanical polishing. 
     The bit lines  37   a  extend on the first inter-level insulating layer  38   d  in a perpendicular direction to the word line  37   b  (see FIG.  16 B), and passes through the bit contact hole  38   a  formed in the first inter-level insulating layer  38   d  and the silicon oxide layer  38   c  so as to be held in contact with the n-type drain region  35   b  (see FIG.  16 C). The bit contact hole  38   a  is 0.2 micron square, and the bit line is 0.4 micron in width. An n-type polysilicon strip of 150 nanometers thick is overlain by a tungsten silicide strip of 100 nanometers thick, and the n-type polysilicon strip and the tungsten silicide strip form in combination the bit line  37   a.    
     The bit lines  37   a  and the first inter-level insulating layer  38   d  are covered with a second inter-level insulating layer  38   e.  The second inter-level insulating layer  38   e  is formed of boro-phosphosilicate glass or phosphosilicate glass, and is of the order of 600 nanometers thick. The boro-phosphosilicate glass layer or the phosphosilicate glass layer was reflowed, and was subjected to the chemical mechanical polishing so as to create a flat surface. The flat surface is covered with a silicon nitride layer of 100 nanometers thick, and the boro-phosphosilicate glass layer/phosphosilicate glass layer and the silicon nitride layer form in combination the second inter-level insulating layer  38   e.  The silicon nitride layer may be replaced with a silicon oxide layer or an NSG layer. 
     The stacked storage capacitors  36  are fabricated on the second inter-level insulating layer  38   e,  and are electrically connected through the node contact holes  38   b  to the n-type source regions  35   b,  respectively. The node contact holes  38   b  are 0.2 micron square. 
     The stacked storage capacitor  16  includes the fin storage node electrode  36   b,  a dielectric film  36   c  and a cell plate electrode  36   d.  An n-type polysilicon strip  36   ba  and an n-type polysilicon spacer  36   bb  attached to the side surface of the n-type polysilicon strip  36   ba  form in combination the fin storage node electrode  36   b.  The n-type polysilicon strip  36   ba  is of the order of 600 nanometers thick, and the n-type polysilicon spacer  36   bb  is 100 nanometers in width and 900 nanometers in height. Thus, the n-type polysilicon spacer  36   bb  projects over the upper surface of the n-type polysilicon strip  36   ba.    
     The fin storage node electrode  36   b  occupies an area of 0.6 micron by 1.5 microns, and adjacent two storage node electrodes  36   b  are spaced from each other by 0.3 micron. The distance between the adjacent storage node electrodes  36   b  is narrower than that of the first embodiment. The bottom surface of the fin storage node electrode  36   b  is spaced from the upper surface of the second inter-level insulating layer  38   e  by 0.2 micron, and is narrower than the gap between the adjacent two fin storage node electrodes  36   b.  The dielectric film  36   c  and the cell plate electrode  36   d  fills the gap between the bottom surface of the fin storage node electrode  36   b  and the upper surface of the second inter-level insulating layer  38   e.    
     The dielectric film  36   c  perfectly covers all the surface of the n-type polysilicon strip  36   ba  and all the surface of the n-type polysilicon side spacer  36   bb  over the second inter-level insulating layer  38   e,  and the cell plate electrode  36   d  is held in contact with all the surface of the dielectric film  36   c.  The cell plate electrode  36   d  is formed of n-type polysilicon layer of 100 nanometers thick. 
     Subsequently, fabricating the semiconductor device is described with reference to FIGS. 17A to  17 F. FIGS. 17A to  17 F illustrate the cross section taken along line XVII—XVII of FIG.  14 . 
     The process starts with preparation of a p-type silicon substrate  31 . The thick field oxide layer  31   b  is selectively grown to 300 nanometers thick on the major surface of the p-type silicon substrate  11  by using the LOCOS technology, and defines the active area assigned to two memory cells  32   a.    
     The active areas are thermally oxidized, and the thin gate insulating layers  35   c  are grown to 10 nanometers thick on the active area. N-type polysilicon is deposited to 100 nanometers thick over the entire surface of the structure, and tungsten silicide is further deposited to 100 nanometers thick over the n-type polysilicon layer. A photo-resist etching mask (not shown) is formed on the tungsten silicide layer by using the lithographic techniques, and the tungsten silicide layer and the n-type polysilicon layer are patterned into the word lines  37   b.  N-type dopant impurities are ion implanted into the active area so as to form the n-type drain regions  35   a  of the LDD structure and the n-type source regions  35   b  of the LDD structure in a self-aligned manner with the word lines  37   b.  The n-type dopant impurities further form n-type impurity regions  14   n  of the testing element  34   c.  In this way, the n-channel enhancement type switching transistors  35  are fabricated on the p-type silicon substrate  31 . 
     Subsequently, silicon oxide is deposited to 100 nanometers thick over the entire surface of the resultant structure, and the silicon oxide forms the silicon oxide layer or an HTO layer  38   c.  The thick field oxide layer  31   b,  the word lines  37   b  and the n-type drain/source regions  35   a / 35   b  are covered with the silicon oxide layer  38   c.    
     Boro-phosphosilicate glass or phosphosilicate glass is deposited to 600 nanometers thick over the silicon oxide layer  38   c.  The boro-phosphosilicate glass layer/phosphosilicate glass layer is reflowed, and chemically mechanically polished. The boro-phosphosilicate glass or phosphosilicate glass forms the first inter-level insulating layer  38   d.  The first inter-level insulating layer  38   d  is minimized over the word line  37   b  on the thick field oxide layer  31   b,  and the thinnest first inter-level insulating layer  38   d  is of the order of 250 nanometers thick. On the other hand, the first inter-level insulating layer  38   d  is maximized over the n-type drain region  35   a  and the n-type source region  35   b,  and is of the order of 600 nanometers thick. The first inter-level insulating layer  38   d  is not limited to the boro-phosphosilicate glass and the phosphosilicate glass, and other technologies are available for the first inter-level insulating layer  38   d.  For example, an NSG layer may be deposited over the boro-phosphosilicate glass layer or the phosphosilicate glass layer after the reflow, and may be chemically mechanically polished. Another alternative inter-level insulating layer may be formed of the NSG layer chemically mechanically polished. 
     A photo-resist etching mask (not shown) is formed on the first inter-level insulating layer  38   d,  and the first inter-level insulating layer  38   d  and the silicon oxide layer  38   c  are selectively etched away so as to form the bit contact holes  38   a  (not shown in FIGS. 17A to  17 E). 
     N-type polysilicon is deposited over the first inter-level insulating layer  38   d.  The n-type polysilicon fills the bit contact holes  38   a,  and swells into an n-type polysilicon layer of 150 nanometers thick. Tungsten silicide is further deposited to 100 nanometers thick on the n-type polysilicon layer. A photo-resist etching mask (not shown) is formed on the tungsten silicide layer, and the n-type polysilicon layer and the tungsten silicide layer are patterned into the bit lines  37   a  (not shown in FIGS. 17A to  17 F). 
     Boro-phosphosilicate glass or phosphosilicate glass is deposited to 600 nanometers thick over the bit lines  37   a  on the first inter-level insulating layer  38   d.  The boro-phosphosilicate glass/phosphosilicate glass layer is reflowed, and is chemically mechanically polished. Silicon nitride is deposited to 100 nanometers thick over the boro-phosphosilicate glass/phosphosilicate glass layer, and the boro-phosphosilicate glass/phosphosilicate glass layer and the silicon nitride layer form in combination the second inter-level insulating layer  38   e.  The second inter-level insulating layer  38   e  over the bit lines  37   a  is of the order of 400 nanometers thick, and is of the order of 650 nanometers thick on both sides of the bit lines  37   a.  The second inter-level insulating layer  38   e  is not limited to the materials and the deposition/flattening technologies described above. For example, an HTO layer is deposited to 100 nanometers thick, an NSG layer is further deposited to 500 nanometers thick, and the NSG layer is chemically mechanically polished, and a silicon nitride layer/NSG layer is deposited to 100 nanometers thick. 
     On the silicon nitride layer of the second inter-level insulating layer  38   e  is deposited phosphosilicate glass which forms a first spacing layer  39   a  as shown in FIG.  17 A. The first spacing layer  39   a  is 200 nanometers thick. The first spacing layer  39   a  may be formed of boro-phosphosilicate glass. 
     A photo-resist etching mask (not shown) is formed on the first spacing layer  39   a,  and has an opening exposing the outer peripheral area. Using the photo-resist etching mask, the first spacing layer  39   a  is selectively removed over the outer peripheral area by using the etching technique, and the second inter-level insulating layer  38   e  is partially exposed. Thus, the first spacing layer  39   a  is removed from the outer peripheral area, and still covers at least the central area assigned to the memory cell array  32 . 
     Subsequently, a photo-resist etching mask (not shown) is provided for the node contact holes  38   b,  the contact holes  14   d  and the contact holes  14   p,  and has openings over the n-type source regions  35 and the outer peripheral area. Using the photo-resist etching mask, the first spacer layer  39   a,  the second inter-level insulating layer  38   e,  the first inter-level insulating layer  38   d  and the silicon oxide layer  38   c  are selectively etched away so as to form the node contact holes  38   b  as shown in FIG. 17B, and the n-type source regions  35   b  are exposed to the node contact holes  38   b.  The photo-resist etching mask further allows the etchant to remove the first and second inter-level insulating layers  38   d / 38   e,  the silicon oxide layer  38   c  and the thick field oxide layer  31   b  so as to form the contact holes  14   d  of the testing element  34   a  and to remove the first and second inter-level insulating layers  38   d / 38   e  and the silicon oxide layer  38   c  for forming the contact holes  18   p  of the testing elements  34   c.  The p-type silicon substrate  31  is exposed to the contact holes  14   d,  and the n-type impurity region  14   n  is exposed to the contact holes  14   p.    
     Subsequently, n-type polysilicon is deposited over the upper surface of the first spacing layer  39   a  over the at least central area and the second inter-level insulating layer  38   e  over the outer peripheral area. The n-type polysilicon fills the node contact holes  38   b  and the contact holes  14   d / 14   p,  and swells into an n-type polysilicon layer  39   b  of 600 nanometers thick. Phosphosilicate glass or boro-phosphosilicate glass is deposited to 300 nanometers thick over the n-type polysilicon layer, and forms a second spacing layer  39   c  as shown in FIG.  17 C. 
     A photo-resist etching mask (not shown) is formed on the second spacing layer  39   c,  and selectively exposes the second spacing layer  39   c  and the n-type polysilicon layer  39   b  to anisotropic etchants. The etchants pattern the second spacing layer  39   c  and the n-type polysilicon layer  39   b  into the polysilicon strips  36   ba,    39   ba,    39   bb  . . . and spacing strips  39   ca,    39   cb,    39   cc  . . . N-type polysilicon is deposited to 100 nanometers thick over the entire surface of the structure, and the polysilicon strips  39   ba / 39   bb / 39   bc  . . . and the spacing strips  39   ca / 39   cb / 39   cc  . . . are covered with the n-type polysilicon layer  39   d  as shown in FIG.  17 D. 
     Subsequently, the n-type polysilicon layer  39   d  is exposed to the etchant of a reactive ion etching used for the patterning stage of the n-type polysilicon layer  39   b,  and the polysilicon spacers  36   bb  and  39   da / 39   db  are left on the side surfaces of the polysilicon strips  36   ba  and  39   ba / 39   bb  as shown in FIG.  17 E. 
     Using dilute hydrofluoric acid, the first spacing layer  39   a  and the spacing strips  39   ca / 39   cb / 39   cc  . . . are isotropically etched away, and a gap takes place between the polysilicon strip  36   ba  and the second inter-level insulating layer  38   e.  However, the polysilicon strips  14   d,    14   h,    39   ba,    39   bb  . . . are directly formed on the second inter-level insulating layer  38   e  as shown in FIG.  17 F. The polysilicon strip  36   ba  and the polysilicon spacer  36   bb  form the fin storage node electrode  36   b,  and the polysilicon strips  39   ba / 39   bb  and the polysilicon spacers  39   da / 39   db  form the polysilicon strips  14   qa / 14   qb.    
     Amorphous silicon is available for the storage node electrode and the polysilicon strips, and the n-type dopant impurity is introduced into the amorphous silicon through in-situ doping. It is advantageous to convert the amorphous silicon to polysilicon between the patterning stage and a formation of the dielectric films  36   c,  because the amorphous silicon is too high in sheet resistance. The storage node electrode  37   b  and the testing elements  34   a - 34   c  may be formed of refractory metal such as, for example, tungsten or refractory metal silicide such as, for example, tungsten silicide or titanium nitride. 
     Subsequently, the dielectric films  36   c,    38   f  and  34   r  cover the storage node electrodes  36   b,  the second inter-level insulating layer  38   e  and the polysilicon strips  14   f,    14   h,    14   qa,    14   qb.  In this instance, silicon nitride is deposited to 7 nanometers thick over the entire surface of the structure, and a surface portion of the silicon nitride layer is converted to silicon oxide by using pyrogenic oxidation in wet ambience at 800 degrees centigrade. Thus, the dielectric film is implemented by the lamination of silicon nitride layer and silicon oxide layer, and is equivalent to a silicon oxide film of 5 nanometers thick. 
     The dielectric film  36   c  is not limited to the lamination of the silicon nitride layer and the silicon oxide layer. The dielectric film  36   c  may be formed of tantalum oxide. 
     Finally, n-type polysilicon is deposited to 100 nanometers thick over the entire surface of the structure as similar to the n-type polysilicon for the storage node electrodes  36   b,  and the n-type polysilicon layer is patterned into the cell plate electrodes  36   d.  The storage node electrode  36   b,  the dielectric film  36   c  and the cell plate electrode  36   d  as a whole constitute the storage capacitor  36 . The cell plate electrode  36   d  may be formed of in-situ n-type amorphous silicon or titanium nitride. 
     Thereafter, steps well known to a person skilled in the art are carried out, and the semiconductor device is completed. The storage node electrodes  36   b  is larger in capacitance than the storage node electrode  16   b  by virtue of the polysilicon spacer  36   bb,  and the chemical mechanical polishing makes the formation of the contact holes easy. 
     The second embodiment achieves all the advantages of the first embodiment. Namely, the polysilicon strips  14   d,    14   h,    14   qa  and  14   qb  are directly held in contact with the second inter-level insulating layer  38   e,  and are never broken nor chipped off during the patterning step of the n-type polysilicon layer  39   b.  For this reason, the manufacturer can evaluate the properties of the storage node electrode  36   b,  and the semiconductor device is improved in reliability. Moreover, any broken polysilicon piece does not short circuit the storage node electrodes  36   b,  and the production yield is enhanced. 
     Although particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. 
     For example, the present invention is available for a semiconductor device having a circuit component projecting from an insulating layer and a testing element used for it. The memory cell may be incorporated in an ultra large scale integration together with another function block. 
     The storage node electrode may be formed of refractory metal such as, for example, tungsten or refractory metal silicide such as, for example, tungsten silicide. 
     The dielectric film may be formed of tantalum oxide (Ta 2 O 5 ). The cell plate electrode  16   d  may be formed of in-situ n-type amorphous silicon or titanium nitride which create a good step coverage. However, if the tantalum oxide is used for the dielectric film, it is preferable to form the storage node electrode and the cell plate electrode from a refractory metal layer/a titanium nitride layer and a titanium nitride layer. 
     The configuration of the storage node electrode is not limited to those of the first and second embodiments. A storage node electrode may have more than one polysilicon spacer, and the surface may be roughened.