Abstract:
A method to write data with error checking and correction overlap ranges is disclosed. The method generally includes the steps of (A) receiving plurality of input numbers in a plurality of input signals, (B) generating a plurality of error correction codes by separately operating on each of a plurality of unique pairs of the input numbers, wherein each of the error correction codes is configured to correct at least one error in a corresponding one of the unique pairs and (C) storing the input numbers and the error correction codes in a memory.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to error correction codes generally and, more particularly, to a method and/or apparatus for implementing error checking and correction overlap ranges. 
       BACKGROUND OF THE INVENTION 
       [0002]    Memory chips are small, sensitive and consume small amounts of electrical power to perform on/off switching functions in individual bit cells. Bit cell switching and state retention operations can be disrupted by particles from outer space passing through the memory at the speed of light. Error checking and correction is technology that allows computers to correct memory errors. A popular type of error checking and correction commonly used in memory modules is single bit error correction, often referred to as check bits or error correction codes (ECC). The check bits enables detection and correction of single-bit errors. The check bits also enables detection of two-bit and some multiple bit errors, but is unable to correct such multi-bit errors. 
         [0003]    For each data item sent across the memory bus, check bits are generated according to a correction technique. The check bits are then stored in the memory with the original data. The system uses the check bits to determine if the data is correct, and if not, locate and correct the single-bit error. The check bits are transferred with the original data. Therefore, an error checking and correction memory is wider then the non-error checking and correction memory. The number of check bits depends on a size of the data for correction. Table I illustrates the number of check bits as a function of the number of original data bits. 
         [0000]                            TABLE I               Original data width       Number of check bits       (bits)   Number of check bits   per data bits                   X   Y(X) = log(X) + 2   X/Y(X)        8   5   0.625       16   6   0.375       32   7   0.21875       64   8   0.125       128    9   0.0703125                    
As shown in the table, as the number data bits increases, the number of check bits increases while the ratio of check bits per data bits decreases.
 
         [0004]    Referring to  FIG. 1 , a functional block diagram  10  of a convention memory write using check bits is shown. A conventional memory  12  is enlarged to store both the data bits  14  and an appropriate number of check bits  16  according to a data size that should be protected from errors. For example, if an error rate demands protecting the data from 1 bit error in every 8 bits (1 byte), error checking and correction processes  18   a - 18   d  operate on each byte of write data (i.e., 32 bits total). In the example, 5 check bits are added to every 8 bits of write data prior to storage in the memory  12 . 
         [0005]    Referring to  FIG. 2 , a functional block diagram  20  of a convention memory read using check bits is shown. Both the original data and the associated check bits are read from the memory  12  and presented to the error checking and correction processes  18   a - 18   d . The error checking and correction processes  18   a - 18   d  determine if any errors are present in the received byte, and if so, correct the errors. A disadvantage of the conventional reads  20  and writes  10  is that a relatively large amount of the memory  12  is consumed by the check bits. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention concerns a method to write data with error checking and correction overlap ranges. The method generally includes the steps of (A) receiving plurality of input numbers in a plurality of input signals, (B) generating a plurality of error correction codes by separately operating on each of a plurality of unique pairs of the input numbers, wherein each of the error correction codes is configured to correct at least one error in a corresponding one of the unique pairs and (C) storing the input numbers and the error correction codes in a memory. 
         [0007]    The objects, features and advantages of the present invention include providing a method and/or apparatus for implementing error checking and correction overlap ranges that may (i) reduce redundancy bits by using overlap regions, (ii) reduce memory consumption compared with conventional techniques by reducing the total number of check bits in use, (iii) provide error coding delays similar to conventional coding delays and/or (iv) provide error detection and correction delays proximate to conventional error detection and correction delays. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
           [0009]      FIG. 1  is a functional block diagram of a convention memory write using check bits; 
           [0010]      FIG. 2  is a functional block diagram of a convention memory read using check bits; 
           [0011]      FIG. 3  is a functional block diagram of an example apparatus implementing error checking and correction overlapping ranges for a memory write in accordance with a preferred embodiment of the present invention; 
           [0012]      FIG. 4  is a functional block diagram of an example apparatus implementing error checking and correction overlapping ranges for a memory read; 
           [0013]      FIG. 5  is a functional block diagram of an example implementation of a write system; 
           [0014]      FIG. 6  is a functional block diagram of an example implementation of a read system; and 
           [0015]      FIG. 7  is a flow diagram of an example implementation of a method to shorten correction delays. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0016]    When reading or writing several data items at a time to and from a memory, error checking and correction may be made more efficient by using fewer error correction codes (ECCs) to protect wider ranges of the data items. In some embodiments, four ECC ranges each of a size X may be replaced by three ECC ranges each of a size 2×. For example, instead of protecting four 8-bit data items with four respective 5-bit error correction codes, two 16-bit data items may be protected with three 6-bit error correction codes. Table II generally illustrates the number of error correction codes as a function of the number of original data bits. 
         [0000]                                    TABLE II                               Number       Original       Number of   Number of   of ECC       data       ECC bits   ECC bits of   bits of three       width   Number of ECC   per data   four data   double-data       (bits)   bits   bit   blocks   blocks                   X   Y(X) = log(X) + 2   X/Y(X)   4 * Y(X)   3 * Y(2X)        8   5   0.625   20   18       16   6   0.375   24   21       32   7   0.21875   28   24       64   8   0.125   32   27       128    9   0.0703125   36   30                    
For all of the illustrated data widths, the number of ECC bits is generally reduced compared with the common approaches. Furthermore, the error detection and correction capabilities are generally maintained similar to the common approaches since the ECC ranges are overlapping.
 
         [0017]    Referring to  FIG. 3 , a functional block diagram of an example apparatus  100  implementing ECC overlapping ranges for a memory write is shown in accordance with a preferred embodiment of the present invention. The apparatus (or unit)  100  generally comprises multiple circuits (or modules)  102   a - 102   c.    
         [0018]    A data signal (e.g., D 1 ) may be received by the circuit  102   a . A data signal (e.g., D 2 ) may be received by the circuit  102   a  and the circuit  102   b . A data signal (e.g., D 3 ) may be received by the circuit  102   b  and the circuit  102   c . The circuit  102   c  may also receive a data signal (e.g., D 3 ). The circuit  102   a  may generate and present a data signal (e.g., M 12 ) and an ECC signal (e.g., C 12 ). The circuit  102   b  may generate and present an ECC signal (e.g., C 23 ). The circuit  102   c  may generate and present a data signal (e.g., M 34 ) and an ECC signal (e.g., C 34 ). 
         [0019]    Each of the signals D 1 , D 2 , D 3  and D 4  may convey a multi-bit (e.g., X-bit) binary number. The binary numbers may each represent 2 x  unique values. Pairs of the adjoining signals D 1 , D 2 , D 3  and D 4  may be appended together to form three larger signals. For example, the signals D 1  and D 2  may be appended together to create a first combined signal of 2X bits. The signals D 2  and D 3  may be appended to create a second combined signal of 2X bits. The signals D 3  and D 4  may be appended to create a third combined signal of 2X bits. The binary number established by the combined signals generally represents 2 2X  unique values. 
         [0020]    Each combined signal is generally received at a respective circuit  102   a - 102   c . The circuits  102   a - 102   c  may be implemented as error coding circuits. The circuits  102   a - 102   c  may be operational to perform an error coding of the received combined signals. In some embodiments, the circuits  102   a - 102   c  may also be operational to perform error checking and correction. 
         [0021]    The error coding generally creates the signals C 12 , C 23  and C 34 , one signal for each respective one of the combined signals. Each of the signals C 12 , C 23  and C 34  may have Y-bits. A relationship between the Y-bits and the 2X-bits of the combined input data is generally expressed equation 1 as follows: 
         [0000]        Y ( X )=log(2 X )+2  Eq. (1) 
         [0022]    An example implementation of the circuits  102   a - 102   c  is generally disclosed in a datasheet “DW_ecc”, release DWF — 0206, March 2007, published by Synopsys, Inc., Mountain View, Calif. The DW_ecc datasheet is hereby incorporated by reference in its entirety. Other designs of the circuits  102   a - 102   c  may be implemented to meet the criteria of a particular application. 
         [0023]    In general, every four ECC ranges (e.g., range # 1 , range # 2 , range # 3 , range # 4 ) may be checked by the three ECC circuits  102   a - 102   c  instead of four ECC circuits. The use of fewer ECC circuits generally reduces the number of redundant bits generated by the error coding process and thus reduces a correction level. For example, the error correction code generated in the signal C 12  by the circuit  102   a  may correct a single bit in the double-range value (e.g., range # 1 # 2 ) carried by the signal M 12 . Likewise, the error correction code generated in the signal C 34  by the circuit  102   c  may correct a single bit in the double-range value (e.g., range # 3 # 4 ) carried by the signal M 34 . Therefore, the ECC circuit  102   b  may be included in the apparatus  100  to generate an error correction code for the double-range value (e.g., range # 2 # 3 ) created by the combination of the signals D 2  and D 3 . If no multiple errors exist in the range # 2  and the range # 3 , the corrected data created by the circuit  102   b  may be used by the other two circuits  102   a  and  102   c  on a read. As such, a single error in the combined range # 2 # 3  may be fixed before checking (i) the combined range # 1 # 2  and (ii) the combined range # 3 # 4  for other errors. 
         [0024]    The resulting structure generally enables correction of (i) a single error in a single range and (ii) two errors in two ranges. Multiple errors in one range are generally uncorrectable, but may be detected as in the existing solutions. In a few specific cases, the above approach may not correct three errors in three ranges. However, the probability of such cases is generally much less than seeing two errors in one range, which also cannot be corrected by the existing solution. 
         [0025]    The specific cases generally have a low probability of occurrence. Consider a probability (e.g., 1/p) of a single error in one range. The probability of two errors in one range is generally 1/p 2  and probability of three errors in three ranges may be 8/p 3 . Since p&gt;&gt;8, the probability of three errors in three ranges may be considered negligible. 
         [0026]    Referring to  FIG. 4 , a functional block diagram of an example apparatus  120  implementing ECC overlapping ranges for a memory read is shown. The apparatus (or unit)  120  generally comprises multiple circuits (or modules)  122   a - 122   c  and multiple circuits (or modules)  124   a - 124   b . The circuit  122   a  may receive a signal (e.g., M 1 ′), a signal (e.g., C 12 ′) and an intermediate signal (e.g., J). The circuit  122   b  may receive a signal (e.g., M 2 ′), a signal (e.g., C 23 ′) and a signal (e.g., M 3 ′). The circuit  122   c  may receive an intermediate signal (e.g., K), a signal (e.g., C 34 ′) and a signal (e.g., M 4 ′). A signal (e.g., D 12 ′) may be generated by the circuit  122   a . A signal (e.g., G) may be generated by the circuit  122   b  and presented to the circuit  124   a . A signal (e.g., H) may also be generated by the circuit  122   b  and presented to the circuit  124   b . A signal (e.g., D 34 ′) may be generated by the circuit  122   c . The circuit  124   a  may receive the signals G and M 2 ′. The signal J may be generated by the circuit  124   a . The circuit  124   b  may receive the signals H and M 3 ′. The signal K may be generated by the circuit  124   b . A multi-error signal (e.g., ME 23 ′) may be generated by the circuit  122   b  and presented to each of the circuits  124   a - 124   b . Another multi-error signal (e.g., ME 12 ′) may be generated by the circuit  122   a . A multi-error signal (e.g., ME 34 ′) may be generated by the circuit  122   c . An error-detected signal (e.g., ED 12 ′) may be generated by the circuit  122   a . Another error-detected signal (e.g., ED 34 ′) may be generated by the circuit  122   c.    
         [0027]    The circuits  122   a - 122   c  may be implemented as error checking and correction circuits. The circuits  122   a - 122   c  may be operational to check for errors among values received in inputs signals and correct at least one bit-error when discovered. In some embodiments, the circuits  122   a - 122   c  may also be operational to perform error coding functions (e.g., same as the circuits  102   a - 102   c ). An example implementation of the circuits  122   a - 122   c  may be according to the datasheet “DW_ecc”. Other designs of the error detection and correction functions may be implemented to meet the criteria of a particular application. 
         [0028]    The circuits  124   a - 124   b  may be implemented as multiplexers. The circuit  124   a  may be operational to multiplex the signal M 2 ′ and the signal G into the signal J, as controlled by the signal ME 23 ′. The circuit  124   b  may be operational to multiplex the signal M 3 ′ and the signal H into the signal K, as controlled by the signal ME 23 ′. 
         [0029]    If no errors have occurred during the storage and/or transmission of the signals M 12 , M 34 , C 12 , C 23  and C 34 , the values within the signals M 12 , M 34 , C 12 , C 23  and C 34  will generally match the respective values in the signals M 12 ′, M 34 ′, C 12 ′, C 23 ′ and C 34 ′. If one or more errors are created during the storage and/or transmission of the signals M 12 , M 34 , C 12 , C 23  and C 34 , the values within the corresponding signals M 12 ′, M 34 ′, C 12 ′, C 23 ′ and C 34 ′ may be different. 
         [0030]    The signal G generally carries a corrected value or an original error-free value of the signal M 2 ′. The signal H generally carries a corrected value or an original error-free value of the signal M 3 ′. The signal ME 23 ′ may be asserted (e.g., a logical one state) to indicate an uncorrectable mode where one or more uncorrectable errors (e.g., multi-bit errors) are detected among the signals M 2 ′, M 3 ′ and C 23 ′. The uncorrectable errors may be in any one of the signals M 2 ′, M 3 ′ and C 23 ′ or distributed among two signals or all three of the signals M 2 ′, M 3 ′ and C 23 ′. The signal ME 23 ′ may be deasserted (e.g., a logical zero state) to indicate a correctable mode where only correctable errors (e.g., no errors or a single bit error) are detected among the signals M 2 ′, M 3 ′ and C 12 ′. As such, the signal ME 23 ′ may be referred to as a mode signal. 
         [0031]    The circuit  122   b  may receive the signals M 2 ′ and M 3 ′ as a double-range appended signal. The signals M 2 ′ and M 3 ′ may convey values of range # 2  and range # 3  to the circuit  122   b . If no errors are detected, the circuit  122   b  may pass the values of range # 2  and range # 3  through to the signals G and H (e.g., G=M 2 ′ and H=M 3 ′). With the signal ME 23 ′ deasserted (e.g., second mode), the circuits  124   a  and  124   b  may pass the values within the signals G and H through to the signals J and K respectively. If correctable errors are detected, the circuit  122   b  may correct the errors and present the corrected values in the signals G and H. Since the signal ME 23 ′ may remain deasserted (e.g., correctable mode) because all errors were corrected, the corrected values in the signals G and H may be routed by the circuits  124   a  and  124   b  into the signals J and K respectively. 
         [0032]    If one or more non-correctable errors are discovered among the signals M 2 ′, M 3 ′ and C 23 ′, the circuit  122   b  may assert the signal ME 23 ′ (e.g., uncorrectable mode). Because the circuit  122   b  has detected uncorrectable errors, the values presented in one or both of the signals G and H may be corrupted. As such, the asserted signal ME 23 ′ may cause the circuits  124   a  and  124   b  to route the original signals M 2 ′ and M 3 ′ through to the signals J and K respectively. If the signal M 2 ′ is error free or contains only correctable errors (e.g., all of the uncorrectable errors are in the signal M 3 ′), passing the signal M 2 ′ through the circuit  124   a  may enable the circuit  122   a  to recover the original data items in the signals M 1 ′ and M 2 ′. Likewise, if the signal M 3 ′ is error free or contains only correctable errors (e.g., all of the uncorrectable errors are in the signal M 2 ′), passing the signal M 3 ′ through the circuit  124   b  may enable the circuit  122   c  to recover the original data items in the signals M 3 ′ and M 4 ′. In some embodiments where the circuit  122   b  is guaranteed not to corrupt the signals G and H in the presence of uncorrectable errors, the circuits  124   a  and  124   b  may be eliminated. 
         [0033]    The circuit  122   a  is generally operational to perform error detection and correction of the values received in the signals M 1 ′, C 12 ′ and J. The values in the signals M 1 ′ and J may be appended to create a double-range input to the circuit  122   a . The corrected double-range values or the original error-free values in the signal D 12 ′ may be parsed at an output of the circuit  122   a  to recreate the two original single-range values. 
         [0034]    The signals ME 12 ′ and ED 12 ′ may be asserted (e.g., the logical one state) to indicate the uncorrectable mode where one or more uncorrectable errors (e.g., multi-bit errors) are detected among the signals M 1 ′, C 12 ′ and J. The uncorrectable errors may be in any one of the signals M 1 ′, C 12 ′ and J or distributed among two signals or all three of the signals M 1 ′, C 12 ′ and J. The signal ME 12 ′ may be deasserted (e.g., the logical zero state) to indicate the correctable mode where only correctable errors (e.g., no errors or a single bit error) are detected among the signals M 1 ′, C 12 ′ and J. The signal ED 12 ′ may be asserted where correctable errors are detected and deasserted where no errors are detected. 
         [0035]    The circuit  122   c  is generally operational to perform error detection and correction of the values received in the signals M 4 ′, C 34 ′ and K. The values in the signals M 4 ′ and K may be appended to create a double-range input to the circuit  122   c . The corrected double-range values or the original error-free values in the signal D 34 ′ may be parsed at an output of the circuit  122   c  to recreate the two original single-range values. 
         [0036]    The signals ME 34 ′ and ED 34 ′ may be asserted (e.g., the logical one state) to indicate the uncorrectable mode where one or more uncorrectable errors (e.g., multi-bit errors) are detected among the signals M 4 ′, C 34 ′ and K. The uncorrectable errors may be in any one of the signals M 4 ′, C 34 ′ and K or distributed among two signals or all three of the signals M 4 ′, C 34 ′ and K. The signal ME 34 ′ may be deasserted (e.g., the logical zero state) to indicate the correctable mode where only correctable errors (e.g., no errors or a single bit error) are detected among the signals M 4 ′, C 34 ′ and K. The signal ED 34 ′ may be asserted where correctable errors are detected and deasserted where no errors are detected. 
         [0037]    Referring to  FIG. 5 , a functional block diagram of an example implementation of a write system  140  is shown. The system (or device)  140  generally comprises an apparatus (or unit)  100 ′ and a circuit (or module)  142 . The signals D 1 , D 2 , D 3  and D 4  may be received by the apparatus  100 ′ from other parts of the system  140 . The signals M 12 , C 12 , C 23 , M 34  and C 34  may be generated by the apparatus  100 ′ and presented to the circuit  142 . The apparatus  100 ′ may be a specific embodiment of the apparatus  100  configured to operate at a specific data width. The circuit  142  may be implemented as a memory. 
         [0038]    Consider a specified error rate that may protect data in the circuit  142  from a single bit error in every eight bits (1 byte). The specified protection may be achieved by using two 6-bit ECC values to protect the two 16-bit combined data items and another 6-bit ECC value to increase the overall error detection and correction capability. Therefore, the above technique generally results in adding an average of 4.5 bits for every 8 bits of data. 
         [0039]    Each of the single-range signals D 1 , D 2 , D 3  and D 4  may convey an 8-bit value. Each of the double-range signals M 12  and M 34  may convey a 16-bit value. Each of the signals C 12 , C 23  and C 34  may convey a 6-bit value. 
         [0040]    The apparatus  100 ′ generally performs multiple (e.g., three) parallel error coding operations on multiple (e.g., three) double-range appended inputs. The original data items may be presented by the apparatus  100 ′ in pairs within the signals M 12  and M 34  (e.g., M 12 =M 1  appended to M 2 , M 34 =M 3  appended to M 4 ). The ECC signals C 12 , C 23  and C 34  may be created to provide error detection of one or more bit-errors and correction of at least one bit-error per the 16-bit combined inputs. 
         [0041]    The circuit  142  may be configured to store the values received in the signals M 12 , C 12 , C 23 , M 34  and C 34 . The circuit  142  may be sized to the store 32-bit data values and the 18-bit ECC values. By comparison, a common approach to error coding the four 8-bits input values would generate 20 ECC bits (see TABLE I). As such, the technique of some embodiments of the present invention may save an appreciable amount of storage capacity of the circuit  142 . 
         [0042]    Referring to  FIG. 6 , a functional block diagram of an example implementation of a read system  160  is shown. The system (or device)  160  generally comprises an apparatus (or unit)  120 ′, the circuit  142  and a circuit (or module)  162 . The signals M 1 ′, M 2 ′, M 3 ′ and M 4 ′ may be received by the apparatus  120 ′ from the circuit  142 . The signals D 12 ′, D 341 , ED 12 ′ ED 34 ′, ME 12 ′ and ME 34 ′ may be generated by the apparatus  120 ′ and presented to the circuit  162  and/or other parts of the system  160 . The apparatus  120 ′ may be a specific embodiment of the apparatus  120  configured to operate at a specific data width. 
         [0043]    Each of the single-range signals M 1 ′, M 2 ′, M 3 ′ and M 4 ′ may convey an 8-bit value. Each of the signals D 12 ′ and D 34 ′ may convey an 16-bit value, where (i) D 12 ′ parsed becomes D 1 ′ and D 2 ′ and (ii) D 34 ′ parsed becomes D 3 ′ and D 4 ′. Each of the signals D 1 ′, D 2 ′, D 3 ′ and D 4 ′ may carry an 8-bit value. Each of the signals C 12 ′, C 23 ′ and C 34 ′ may convey a 6-bit value. 
         [0044]    The apparatus  120 ′ generally performs multiple (e.g., three) error checking and correction operations on multiple (e.g., three) double-range appended inputs based on the ECC signals C 12 ′, C 23 ′ and C 34 ′. The data items processed by the error checking and correction operations may be presented by the apparatus  120 ′ within the signals D 1 ’, D 2 ′, D 3 ′ and D 4 ′ to the circuit  162 . 
         [0045]    In some embodiments, the circuit  162  may be implemented as a processor that consumes the data items in the signals D 1 ′, D 2 ′, D 3 ′ and D 4 ′. The circuit  162  may also inspect the signals ED 12 ′, ED 34 ′, ME 12 ′ and ME 34 ′ to determine the validity of the data items within the signals D 1 ′, D 2 ′, D 3 ′ and D 4 ′. In other embodiments, the circuit  162  may be implemented as other circuits, such as an encoding circuit, a transmission circuit, a storage circuit or the like. 
         [0046]    The above example using the ECC structure may save approximately 6.25% of the memory capacity of the circuit  142  normally reserved for ECC data. For example, in a memory of 256 kilobytes, the above techniques may save approximately 128 kilobits. In general, an access size to the circuit  142  may be at least four times wider than the ECC-data width. As such, at least four data items may be written into the circuit  142  at a time. Likewise, at least four data items may be read from the circuit  142  at a time. To write individual portions (e.g., bytes) of the data into the circuit  142 , a read-modify-write cycle may be used to obtain the neighboring portions. To read individual portions, a read cycle may be used to obtain a particular portion and the associated neighbors. The associated neighbors may then be ignored. 
         [0047]    In some implementations, the delay caused by the sequential delays through the circuit  122   b  first and then the circuits  122   a  and  122   c  second may create a timing issue. To speed up the timing, the data items may be presented from the circuit  142  directly to the circuit  162  while the error checking and correction are performed in the background. 
         [0048]    Referring to  FIG. 7 , a flow diagram of an example implementation of a method  180  to shorten correction delays is shown. The method (or process)  180  generally comprises a step (or block)  182 , a step (or block)  184 , a step (or block)  186 , a step (or block)  188 , a step (or block)  190 , a step (or block)  192 , a step (or block)  194 , a step (or block)  196  and a step (or block)  198 . The method  180  may be implemented by the system  160 . 
         [0049]    In the step  182 , data items may be read from the memory  142  into the apparatus  120 ′. The circuit  162  may receive the data items in the step  184  and subsequently begin processing in the step  186 . The apparatus  120 ′ may perform error detection and correction in the step  188 . The step  188  may be performed in parallel (substantially simultaneously) with the steps  184  and  186 . 
         [0050]    In the step  190 , the apparatus  120 ′ may correct any correctable errors found in the data items read from the circuit  142 . If correctable errors were detected, the apparatus  120 ′ may raise a flag to the circuit  162  by asserting the corresponding signals ED 12 ′ and/or ED 34 ′ in the step  192 . When ready, the corrected data items may be presented to the circuit  162  in the step  194 . Thereafter, the circuit  162  may flush the corrupted data from a current task and restart the current task with the corrected data items in the step  196 . 
         [0051]    If the apparatus  120 ′ detects uncorrectable errors in the data items received from the circuit  142 , the apparatus  120 ′ may raise a flag to the circuit  162  by asserting the corresponding signals ME 12 ′ and/or ME 34 ′ in the step  198 . The asserted signals ME 12 ′ or ME 34 ′ generally indicates that the circuit  142  received corrupt data items in the step  184 . In some embodiments, the signals ED 12 ′ and/or ED 34 ′ may also be asserted in the step  198 . Proceeding forward in the presence of the corrupted data may be implementation specific. 
         [0052]    The functions performed by the diagrams of  FIGS. 3-7  may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). 
         [0053]    The present invention may also be implemented by the preparation of ASICs, FPGAS, or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
         [0054]    The present invention thus may also include a computer product which may be a storage medium including instructions which can be used to program a computer to perform a process in accordance with the present invention. The storage medium can include, but is not limited to, any type of disk including floppy disk, optical disk, CD-ROM, magneto-optical disks, ROMs, RAMs, EPROMS, EEPROMS, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions. As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration. 
         [0055]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.