Abstract:
An object of the present invention is to provide a highly accurate delta sigma A/D converter. Disclosed is a delta sigma A/D converter including: a first integration circuit to generate a first signal on the basis of an input signal and a first feedback signal from an output side; a first signal conversion circuit to convert the first signal into a first converted signal; a loop delay compensation circuit to generate a compensation signal and then to output the compensation signal in response to a second feedback signal fed back from the output side at a timing earlier than that of the first feedback signal; an adder circuit to add the first converted signal and the compensation signal; and a comparator to generate a digital signal on the basis of an output signal from the adder circuit. The loop delay compensation circuit includes a compensation signal conversion circuit to generate the compensation signal. The compensation signal conversion circuit and the first signal conversion circuit have the approximately same rate of change in conversion coefficient depending on a temperature.

Description:
TECHNICAL FIELD 
     The present invention relates to a delta-sigma A/D converter, and more particularly, to a continuous-time delta-sigma A/D converter. 
     BACKGROUND ART 
     Having complicated circuits and a large number of component parts, a highly accurate analog/digital (A/D) converter requires increases in circuit area and power consumption. In recent years, a delta sigma (ΔΣ) A/D converter achieving high accuracy by an over sampling technique in spite of a small number of component parts has been actively developed, and thus various circuit systems have been studied. Generally a ΔΣ A/D converter feeds back a converted digital output signal to an analog input signal and then modulates frequency characteristics thereby to secure a desired conversion band and accuracy. The ΔΣ A/D converter requires a high speed clock rate dozens of times as high as the converted signal bandwidth, and thereby requires circuits to operate at such a high speed. In this regard, such high speed circuits have been put in practical use thanks to speed-up of MOS transistors. 
     A configuration example of a ΔΣ A/D converter is disclosed in FIG. 1 of Patent Literature 1. In the ΔΣ A/D converter, a quantizer is connected to an output of a filter circuit constituted of multiple integration circuits. An output signal of the quantizer is outputted via an encoder and is also fed back to the filter circuit via a D/A converter. 
     Here, the ΔΣ A/D converter disclosed in Patent Literature 1 is a discrete-time type. Meanwhile, attention has been attracted to a continuous-time type which achieves lower power consumption than the discrete-time type, and which is also suitable for a high-speed high-frequency signal. The continuous-time ΔΣ A/D converter is configured based on the assumption that an excess loop delay (ELD) from the sampling of the output signal of the quantizer until the feedback of the signal to the filter circuit is almost zero. However, when the sampling clock rate is high, the ELD can be no longer ignored. 
     A configuration in which the ELD is compensated is disclosed in FIG. 2 of Non-patent Literature 1.  FIG. 6  attached hereto is a block diagram of a continuous-time ΔΣ A/D converter disclosed in FIG. 2 of Non-patent Literature 1. The continuous-time ΔΣ A/D converter includes adder circuits  1  to  3 , integration circuits  4  to  6 , voltage-current conversion circuits K 4  to K 7  and Kz, an internal A/D converter (ADC), two D/A converters (DACs) -A and -B, and two D-latches (D-LATCHes). 
     In the continuous-time ΔΣ converter, an analog input signal IN and output signals of the integration circuits  4  to  6  are converted into current signals by the voltage-current conversion circuits K 4  to K 7 , respectively, and the currents are added in the adder circuit  3  positioned at a prior stage of the internal ADC. In other words, this continuous-time ΔΣ converter is a feedforward type. 
     The internal ADC, which is a quantizer, converts an output signal of the adder circuit  3  into a 5-bit digital value and outputs a digital output signal OUT. The DAC-A feed backs an analog current in response to the digital output signal OUT to the adder circuit  1 . In addition, the DAC-B feed backs an analog current in response to the digital output signal OUT to the adder circuit  3 . Thereby, delay compensation of the internal ADC is performed. 
     Here, a delay time of the output signal OUT of the internal A/D converter ADC largely fluctuates due to the amplitude or the like of a signal inputted from the adder circuit  3 . In order to reduce the amount of fluctuation, the output signal OUT of the internal ADC is fed back to the DAC-A via the two D-LATCHes. 
     Meanwhile, the feedback from the output signal OUT to the input signal IN is constantly delayed by one clock cycle, and the feedback is not performed during a period from a sampling timing to the next sampling timing. The DAC-B is provided to compensate this problem. The DAC-B receives the output signal OUT only a half clock cycle earlier than the DAC-A, and performs feedback to the adder circuit  3  immediately before the internal ADC. 
     Unlike the signal from the DAC-A, the signal from the DAC-B is not inputted to the integration circuits  3  to  6 . Thus, the influence of the feedback by the DAC-B is limited in the period from the sampling timing to the next sampling timing at which the feedback of the DAC-A is not performed. Accordingly, even when the DAC-A and DAC-B are used in a combination, the system operates without any problem. Here, the feedback coefficient of the DAC-B can be calculated by using an impulse response equalization method. 
     [Citation List] 
     [Patent Literatures] 
     
         
         [Patent Literature 1] Japanese Patent Application Publication No. 2006-41992 
         [Non-patent Literature 1] Yan, S. and one other, “A continuous-time ΣΔ modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth,” IEEE Journal of Solid-State Circuits, January 2004, Vol. 39, No. 1, p. 75-86 
       
    
     SUMMARY 
     [Technical Problems] 
     In Non-patent Literature 1, a current switch circuit similar to the DAC-A is used as the DAC-B. Here, the addition coefficients of the voltage-current conversion circuits K 4  to K 7  change with a change in the temperature. However, in Non-patent Literature 1, the output current from the DAC-B is not changed according to conversion characteristics of the voltage-current conversion circuits K 4  to K 7 . Thus, the compensation coefficient deviates from the design value, and there arises a problem that the accuracy as the entire continuous-time ΔΣ A/D converter is rather degraded. 
     [Solution to Problem] 
     A delta sigma A/D converter according to the present invention includes: a first integration circuit to generate a first signal on the basis of an input signal and a first feedback signal from an output side; a first signal conversion circuit to convert the first signal into a first converted signal; a loop delay compensation circuit to generate a compensation signal and to output the compensation signal in response to a second feedback signal fed back from the output side at a timing earlier than that of the first feedback signal; an adder circuit to add the first converted signal and the compensation signal; and a comparator to generate a digital signal on the basis of an output signal from the adder circuit. In the delta sigma A/D converter, the loop delay compensation circuit includes a compensation signal conversion circuit that generates the compensation signal, and the compensation signal conversion circuit and the first signal conversion circuit have the approximately same rate of change in conversion coefficient depending on a temperature. 
     A highly accurate delta sigma A/D converter can be provided because the compensation signal conversion circuit and the first signal conversion circuit have the approximately same rate of change in conversion coefficient depending on a temperature. 
     [Advantageous Effect of Invention] 
     According to the present invention, a highly accurate delta sigma A/D converter can be provided. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram of a delta sigma A/D converter according to a first embodiment. 
         FIG. 2  is a circuit diagram of an ELD compensation D/A converter DAC  1  according to the first embodiment and a periphery thereof. 
         FIG. 3  is a timing chart showing an operation of the delta sigma A/D converter according to the first embodiment. 
         FIG. 4  is an example of a specific circuit configuration using transistors of the ELD compensation D/A converter DAC  1  according to the first embodiment. 
         FIG. 5  is an example of a specific circuit configuration using transistors of an ELD compensation D/A converter DAC  1  according to a second embodiment. 
         FIG. 6  is a block diagram of a continuous-time ΔΣ A/D converter disclosed in FIG. 2 of Non-patent Literature 1. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Hereinafter, with reference to the drawings, a description will be given in detail of specific embodiments to which the present invention is applied. However, the present invention is not limited to the embodiments below. Further, for the purpose of clarifying the description, the description and drawings below are simplified as appropriate. 
     First Embodiment 
       FIG. 1  is a block diagram of a continuous-time ΔΣ A/D converter according to a first embodiment of the present invention. The continuous-time ΔΣ A/D converter includes two integration circuits ITF 1  and ITF 2 , two adder circuits ADD 1  and ADD 2 , two voltage-current conversion circuits VIC 1  and VIC 2 , a comparator CMP, an ELD compensation D/A converter DAC 1 , a feedback D/A converter DAC 2  and two D latches DL 1  and DL 2 . Note that, although the description is given of a case where two integration circuits are employed as an example, the number of integration circuits, adder circuits or the like is optional. 
     The adder circuit ADD 1  adds an input signal IN and a feedback signal (first feedback signal) converted by the feedback D/A converter DAC 2  into an analog signal from an output signal OUT. 
     The integration circuit ITF 1  (first integration circuit) integrates a signal outputted from the adder circuit ADD 1  and then outputs an input voltage signal Vin 1  (first signal). The input voltage signal Vin 1  is converted into a current (first converted current) via the voltage-current conversion circuit VIC 1  (first signal conversion circuit) and is then feed forwarded to the adder circuit ADD 2 . 
     The integration circuit ITF 2  (second integration circuit) integrates the input voltage signal Vin 1  outputted from the integration circuit ITF 1  and then outputs an input voltage signal Vin 2  (second signal). The input voltage signal Vin 2  is converted into a current (second converted signal) via the voltage-current conversion circuit VIC 2  (second signal conversion circuit) and is then inputted to the adder circuit ADD 2 . 
     The adder circuit ADD 2  adds the currents outputted from the aforementioned voltage-current conversion circuits VIC 1  and VIC 2 , respectively, and an ELD compensation current I ELD  (compensation signal) fed back from the ELD compensation D/A converter DAC 1  and then outputs an output voltage signal Vout. 
     The comparator CMP quantizes the output voltage signal Vout outputted from the adder circuit ADD 2 . Here, the comparator CMP according to the present embodiment performs sampling at a rising edge of a clock signal CLK. 
     The D latch DL 1  latches data at a clock edge reversal to the comparator CMP. In addition, the D latch DL 2  latches data at the same clock edge as the comparator does. An output signal OUT is outputted from the D latch DL 2 . 
     The ELD compensation D/A converter (loop delay compensation circuit) DAC 1  generates the ELD compensation current I ELD  on the basis of a digital signal (second feedback signal) fed back from the D latch DL 1  and then outputs the ELD compensation current I ELD  to the adder circuit ADD 2 . 
     The feedback D/A converter DAC 2  generates a feedback signal on the basis of the output signal OUT and then outputs the feedback signal to the adder circuit ADD 1 . 
       FIG. 2  is a circuit diagram of the voltage-current conversion circuits VIC 1  and VIC 2 , the adder circuit ADD 2  and the ELD compensation D/A converter DAC 1  which are shown in  FIG. 1 . Here, the ELD compensation D/A converter DAC 1  includes a differential switch circuit SW 1  and a voltage-current conversion circuit VIC 3  (compensation signal conversion circuit). 
     As shown in  FIG. 2 , both (+) and (−) output terminals of the voltage-current conversion circuit VIC 1  are connected to a power supply VDD via load resistances R L , respectively. Likewise, both (+) and (−) output terminals of the voltage-current conversion circuit VIC 2  are connected to the power supply VDD via the load resistances R L , respectively. In addition, the (+) output terminals of the voltage-current conversion circuits VIC 1  and VIC 2  are connected to each other, and the (−) output terminals thereof are connected to each other as well. Then, a differential output voltage signal Vout (+) is outputted from a node between the (−) output terminals of the voltage-current conversion circuits VIC 1  and VIC 2  and the load resistance R L . In addition, a differential output voltage signal Vout (−) is outputted from a node between the (+) output terminals of the voltage-current conversion circuits VIC 1  and VIC 2  and the load resistance R L . 
     Here, the differential input voltage signals Vin 1  and Vin 2  outputted from the integration circuits ITF 1  and ITF 2  are converted into differential current signals by the voltage-current conversion circuits VIC 1  and VIC 2 , respectively. Then, the currents of the (−) output terminals are added to each other, and the currents of the (+) output terminals are added to each other. Each of the added currents is converted into a voltage signal by a corresponding one of the load resistances R L . Then, the voltage signals are outputted as the differential output voltage signals Vout (+) and Vout (−), respectively. 
     In a case where the voltage of the (+) input terminal is higher than the voltage of the (−) input terminal, a current is outputted from the (−) output terminal in the voltage-current conversion circuits VIC 1  and VIC 2  and then is absorbed into the (+) output terminal of the adder circuit ADD 2 . Specifically, when the differential input voltage signal Vin 1  of the voltage-current conversion circuit VIC 1  is positive, the output voltage signal Vout (+) increases, and the output voltage signal Vout (−) decreases. 
     The voltage-current conversion circuit VIC 3  has the same configuration as those of the voltage-current conversion circuits VIC 1  and VIC 2 . An ELD reference voltage Vref for ELD compensation is inputted to the input terminal of the voltage-current conversion circuit VIC 3 . The value of the reference voltage Vref is set in order that impulse responses of the filters in the ΔΣ A/D converter can be equal, and is uniquely determined from the range of the input signal IN. In other words, the reference voltage Vref is not related to the characteristic values of the voltage-current conversion circuits VIC 1  to VIC 3 . 
     The ELD reference voltage Vref (reference signal) is converted into a differential current signal by the voltage-current conversion circuit VIC 3 . Here, a current of the (+) output terminal and a current of the (−) output terminal are added, and an ELD compensation current I ELD  is generated. Here, the differential switch circuit SW 1  switches a connection destination of the ELD compensation current I ELD  in accordance with an output signal S ELD  of the D latch DL 1 . Thus, the ELD compensation current I ELD  is added to the added current of the (−) output terminals of the voltage-current conversion circuits VIC 1  and VIC 2 , or the added current of the (+) output terminals thereof. Thereby, the output voltage signal Vout is corrected. Specifically, the comparator CMP outputs “1” when the differential output voltage signal Vout of the adder circuit ADD 2  is positive, and outputs “0” when the differential output voltage signal Vout thereof is negative. Then, when the output signal S ELD  of the D latch DL 1 =1, the ELD compensation D/A converter DAC 1  operates to draw the ELD compensation current I ELD  from the output voltage signal Vout (+) side and thereby to lower the output voltage signal Vout (+). On the other hand, when the output signal S ELD  of the D latch DL 1 =0, the ELD compensation D/A converter DAC 1  operates to draw the ELD compensation current I ELD  from the output voltage signal Vout (−) side and thereby to lower the output voltage signal Vout (−). In other words, the ELD compensation D/A converter DAC 1  performs negative feedback in the negative direction when the output voltage signal Vout of the adder circuit ADD 2  is positive, and performs negative feedback in the positive direction when the output voltage signal Vout of the adder circuit ADD 2  is negative on the other hand. Here, the amount of feedback is determined by the ELD compensation current I ELD . 
     Next, a description will be given of the principle of the present embodiment by using mathematical formulas. In a case where the ELD compensation D/A converter DAC 1  of  FIG. 1  is provided, the adder circuit ADD 2  satisfies the following formula (1).
 
 V out= a 1 ·V in1 +a 2 ·V in2 −A   ELD   ·s   (1)
 
     In the formula (1), a 1  and a 2  are the output addition coefficients of the integration circuits ITF 1  and ITF 2 , respectively; and A ELD  is the ELD compensation coefficient. Moreover, s is the value in accordance with the output signal S ELD  of the D latch DL 1  and is either 1 or −1. Specifically, when the output voltage signal Vout of the adder circuit ADD 2  is positive, that is, when S ELD =1, s=1, and when the output voltage signal Vout of the adder circuit ADD 2  is negative, that is, when S ELD =0, S=−1. 
     Further, as shown in  FIG. 3 , the output voltage signal Vout of the adder circuit ADD 2  is subjected to sampling at a rising edge of the clock signal CLK by the comparator CMP. Then, the output signal S ELD  of the D latch DL 1  is outputted after time τ passes from this sampling. The values of the output addition coefficients a 1  and a 2 , and the ELD compensation coefficient A ELD  are determined by the time τ. Here, the value of the time τ is often set to be a half clock cycle for the purpose of easier implementation as the circuit. 
     Next, the following formula (2) is obtained when the formula (1) is applied to  FIG. 2 .
 
 V out= R   L ·( g   m1 ·( V in1 p−V in1 n )+ g   m2 ·( V in2 p−V in2 n )−g m3 ·( V ref p−V ref n )· s )  (2)
 
     Here, the Vin 1   p  and Vin 1   n  are the voltages given to the (+) input terminal and the (−) input terminal of the voltage-current conversion circuit VIC 1 , respectively. Voltages are given to the Vin 2   p , Vin 2   n , Vrefp and Vrefn in the same manner. Here, the followings are true: Vin 1 =Vin 1   p −Vin 1   n , Vin 2 =Vin 2   p −Vin 2   n , and Vref=Vrefp−Vrefn. In addition, as compared with the formula (1), the followings are true: a 1 =g m1 ·R L , a 2 =g m2 ·R L , and A ELD =g m3 ·R L ·Vref. Accordingly, the values of the conversion coefficients g m1 , g m2  and g m3  of the voltage-current conversion circuits VIC 1 , VIC 2  and VIC 3  and the ELD reference voltage Vref may be set to appropriate values, respectively. 
     Here, the conversion coefficients g m1  and g m2  of the voltage-current conversion circuits VIC 1  and VIC 2  are determined by the characteristics of transistors and are changed by the temperature or characteristic variations of the transistors. Thus, the amount of compensation of the ELD compensation D/A converter DAC 1  by the ELD reference voltage Vref needs to be changed in accordance with the characteristic variations of the conversion coefficients g m1  and g m2 . 
     In this embodiment, the voltage-current conversion circuit VIC 3  has the same circuit configuration as those of the voltage-current conversion circuits VIC 1  and VIC 2 , so that the conversion coefficient g m3  in the formula (2) changes in the same manner as the conversion coefficients g m1  and g m2 . In other words, even when the temperature changes, the ratio among the conversion coefficients g m1 , g m2  and g m3  is constant. Hereinafter, a description will be given in detail of this point. 
     The ratio among the conversion coefficients g m1 , g m2  and g m3  of the voltage-current conversion circuits VIC 1 , VIC 2  and VIC 3  is determined by a ratio among gate widths of gate terminals of MOS transistors to which voltage signals are inputted in the respective voltage-current conversion circuits VIC 1 , VIC 2  and VIC 3 . 
     In addition, provided that the values of the conversion coefficients g m1 , g m2  and g m3  at a temperature T 0  are set to g m10 , gm 20  and g m30 , respectively, and the values of the conversion coefficients g m1 , g m2  and g m3  at a temperature T 1  are set to g m11 , g m21  and g m31 , respectively, the following formula (3) is established.
 
g m11 =α 1 g m10  
 
g m21 =α 2 g m20  
 
g m31 =α 3 g m30   (3)
 
     Here, α 1 , α 2  and α 3  are change rates of the conversion coefficients g m1 , g m2  and g m3  due to the temperature and are positive real numbers. 
     Here, the change rates α 1 , α 2  and α 3  in the voltage-current conversion circuits VIC 1 , VIC 2  and VIC 3  are designed so that the change rates can be values substantially equal to each other. Specifically, α 1 =α 2 =α 3 =α is true. Accordingly, the ratio among the conversion coefficients g m1 , g m2  and g m3  can be kept constant even when the temperature changes. Note that, in this embodiment, the MOS transistors to which voltage signals are inputted in the respective voltage-current conversion circuits VIC 1 , VIC 2  and VIC 3  have only the different gate widths of the gate terminals thereof. 
     Here, when the output voltage signal Vout at the temperature T 0  is set to Vout 0 , and the output voltage signal Vout at the temperature T 1  is set to Vout 1 , the following formula (4) is obtained from the formulas (2) and (3).
 
Vout 1 =αVout 0   (4)
 
     The output voltage signal Vout of the adder circuit ADD 2  is the input signal of the comparator CMP and only matters if the value thereof is positive or negative. In the formula (4), α is a positive real number, and there is no change between positive and negative of the Vout 0  and Vout 1 . Thus, a change of the temperature has no influence on the accuracy of the ΔΣ A/D converter. As described above, according to the present embodiment, the ELD compensation can be performed while a high accuracy as the ΔΣ A/D converter can be maintained against a change of the temperature. 
       FIG. 4  shows an example of a specific circuit configuration using transistors of the ELD compensation D/A converter DAC 1  according to the first embodiment. The ELD compensation D/A converter DAC 1  includes: the voltage-current conversion circuit VIC 3  having the same configuration as those of the voltage-current conversion circuits VIC 1  and VIC 2 ; current mirrors CM 1 , CM 2  and CM 3 ; and a differential switch circuit SW 1   a.    
     As shown in  FIG. 4 , the voltage-current conversion circuit VIC 3  includes current sources CS 1  and CS 2 , NMOS transistors N 1  and N 2 , and a resistance R 1 . One ends of the current sources CS 1  and CS 2  are both grounded. The other ends of the current sources CS 1  and CS 2  are connected to sources of the NMOS transistors N 1  and N 2 , respectively, and are also connected to each other via the resistance R 1 . Drains of the NMOS transistors N 1  and N 2  are connected to drains of PMOS transistors P 1  and P 2 , respectively, the PMOS transistors P 1  and P 2  constituting the current mirror CM 1 . The ELD reference voltages Vrefn and Vrefp are given to gates of the NMOS transistors N 1  and N 2 , respectively. 
     The current mirror CM 1  is constituted of the PMOS transistors P 1  and P 2 . Sources of the PMOS transistors P 1  and P 2  are both connected to a power supply VDD. Gates of the PMOS transistors P 1  and P 2  are connected to each other and also connected to the drain of the PMOS transistor P 1 . 
     The current mirror CM 2  is constituted of PMOS transistors P 3  and P 4 . Sources of the PMOS transistors P 3  and P 4  are both connected to the power supply VDD. Gates of the PMOS transistors P 3  and P 4  are connected to each other and also connected to a drain of the PMOS transistor P 3  and to the drain of the PMOS transistor P 2 , which is one of the constituent elements of the current mirror CM 1 . A drain of the PMOS transistor P 4  is connected to a drain of an NMOS transistor N 3 , which is one of the constituent elements of the current mirror CM 3 . 
     The current mirror CM 3  is constituted of the NMOS transistor N 3  and a transistor N 4 . Sources of the NMOS transistors N 3  and N 4  are both grounded. Gates of the NMOS transistors N 3  and N 4  are connected to each other and also connected to the drain of the NMOS transistor N 3 . Drain of the NMOS transistor N 4  is connected commonly to sources of NMOS transistors N 5  and N 6 , which form the differential switch circuit SW 1   a.    
     The differential switch circuit SW 1   a  is constituted of the NMOS transistors N 5  and N 6  and an inverter INV 1 . Drains of the NMOS transistors N 5  and N 6  are connected to the outputs OUT (−) and OUT (+) of the ELD compensation D/A converter DAC 1 , respectively. An inverted signal of the output signal S ELD  of the D latch DL 1  by the inverter INV 1  is inputted to a gate of the NMOS transistor N 5 . The output signal S ELD  of the D latch DL 1  is inputted to a gate of the NMOS transistor N 6 . 
     Specifically, when the output signal S ELD  of the D latch DL 1 =1, the NMOS transistor N 5  is turned off, and the NMOS transistor N 6  is turned on. On the other hand, when the output signal S ELD  of the D latch DL 1 =0, the NMOS transistor N 5  is turned on, and the NMOS transistor N 6  is turned off. 
     Next, a description will be given of an operation. A current difference due to the ELD reference voltages Vref (Vrefp, Vrefn) occurs in the differential output of the voltage-current conversion circuit VIC 3 . The current difference in the differential is inputted to the current mirror CM 2  via the current mirror CM 1 . The output current of the current mirror CM 2  is further replicated by the current mirror CM 3 . Then, the output destination of the output current of the current mirror CM 3  is switched to any one of the output OUT (+) and the output OUT (−) of the ELD compensation D/A converter DAC 1  by the differential switch circuit SW 1   a.    
     In this embodiment, the voltage-current conversion circuit VIC 3  has the same configuration as those of the voltage-current conversion circuits VIC 1  and VIC 2 . Accordingly, the conversion coefficient g m3  of the voltage-current conversion circuit VIC 3  fluctuates, as the conversion coefficients g m1  and g m2  of the voltage-current conversion circuits VIC 1  and VIC 2  fluctuate. Thus, the value of current flowing through each of the current mirrors CM 1  to CM 3  fluctuates along with the aforementioned fluctuation. This current is fed back to the adder circuit ADD 2 , thereby enabling the ELD compensation for a stable operation. In this configuration, the number of stages of vertically stacked transistors is small, which is only three stages including the current sources CS 1  and CS 2 . Thus, this configuration can be said to be suitable for a circuit for low voltage operation. 
     Embodiment 2 
     Next, a description will be given of a second embodiment with reference to  FIG. 5 . 
       FIG. 5  is an example of a specific circuit configuration using transistors of an ELD compensation D/A converter DAC 1  according to the second embodiment. The ELD compensation D/A converter DAC 1  includes a voltage-current conversion circuit VIC 3  and a differential switch circuit SWlb. As shown in  FIG. 5 , the voltage-current conversion circuit VIC 3  has the same configuration as that of the voltage-current conversion circuit VIC 3  shown in  FIG. 4 . Accordingly, the description of the voltage-current conversion circuit VIC 3  is omitted. 
     The differential switch circuit SW 1   b  is constituted of four PMOS transistors P 5  to P 8  and an inverter INV 1 . Drains of the PMOS transistors P 5  and P 6  are commonly connected to a drain of the NMOS transistor N 1 . Sources of the PMOS transistors P 5  and P 6  are connected to the output OUT (−) and the output OUT (+), respectively. An inverted signal of the output signal S ELD  of the D latch DL 1  by the inverter INV 1  is inputted to a gate of the PMOS transistor P 5 . The output signal S ELD  of the D latch DL 1  is inputted to a gate of the PMOS transistor P 6 . 
     Specifically, when the output signal S ELD  of the D latch DL 1 =1, the PMOS transistors P 6  and P 7  are turned off and the PMOS transistors P 5  and P 8  are turned on. On the other hand, when the output signal S ELD  of the D latch DL 1 =0, the PMOS transistors P 6  and P 7  are turned on and the PMOS transistors P 5  and P 8  are turned off. 
     Drains of the PMOS transistors P 7  and P 8  are connected commonly to a drain of the NMOS transistor N 2 . Sources of the PMOS transistors P 7  and P 8  are connected to the output OUT (−) and the output OUT (+), respectively. The output signal S ELD  of the D latch DL 1  is inputted to a gate of the PMOS transistor P 7 . An inverted signal of the output signal S ELD  of the D latch DL 1  by the inverter INV 1  is inputted to a gate of the PMOS transistor P 8 . 
     The voltage-current conversion circuit VIC 3  according to the second embodiment also has the same configuration as those of the voltage-current conversion circuits VIC 1  and VIC 2 . The differential output currents generated by the ELD reference voltages Vrefp and Vrefn are outputted from the output OUT (−) and the output OUT (+) of the ELD compensation D/A converter DAC 1 , respectively, by the output signal S ELD  of the D latch DL 1  without any change, or the differential output currents intersecting with each other are outputted from the output OUT (+) and the output OUT (−), respectively. 
     In the second embodiment as well, the conversion coefficient g m3  of the voltage-current conversion circuit VIC 3  fluctuates as the conversion coefficient g m1  and g m2  of the voltage-current conversion circuits VIC 1  and VIC 2  fluctuate. Thus, the output current difference of the voltage-current conversion circuit VIC 1  fluctuates along with the aforementioned fluctuation. This output current difference is fed back to the adder circuit ADD 2 , thereby enabling the ELD compensation for a stable operation. The number of current paths in this configuration is reduced as compared with the configuration of  FIG. 4 , hence resulting in a low current. Meanwhile, in addition to the fact that the number of stages of vertically stacked transistors is three, a voltage drop due to the load resistances R L  needs to be taken into consideration. Thus, as compared with the circuit configuration of  FIG. 4 , this configuration can be said to be suitable for a high voltage circuit. 
     Note that, in principle, the voltage-current conversion circuits VIC 1  to VIC 3  in the aforementioned first and second embodiments can be replaced with conversion circuits for converting voltage signals into voltage signals, or conversion circuits for converting current signals into current signals. 
     [Reference Signs List] 
     
         
         ADD 1 , ADD 2  ADDER CIRCUITS 
         CM 1  to CM 3  CURRENT MIRRORS 
         CMP COMPARATOR 
         CS 1 , CS 2  CURRENT SOURCES 
         DAC 1  ELD COMPENSATION D/A CONVERTER 
         DAC 2  FEEDBACK D/A CONVERTER 
         DL 1 , DL 2  D LATCHES 
         INV 1  INVERTER 
         N 1  to N 6  NMOS TRANSISTORS 
         P 1  to P 8  PMOS TRANSISTORS 
         R 1  RESISTANCE 
         R L  LOAD RESISTANCE 
         SW 1 , SW 1   a , SW 1   b  DIFFERENTIAL SWITCH CIRCUITS 
         VIC 1 , VIC 2 , VIC 3  VOLTAGE-CURRENT CONVERSION CIRCUITS