Abstract:
An output driver calibration circuit includes a programmable drive strength output pullup driver including a strongest transistor and a number of other transistors, a programmable drive strength output pulldown driver including a strongest transistor and a number of other transistors, and a calibration circuit for generating a number of control signals for controlling the transistors in the output pullup driver and the transistors in the output pulldown driver, wherein the control signals are generated simultaneously, except for two the strongest driver transistors.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention is related to integrated circuit devices having an output driver section, and more particularly to a circuit and method for calibrating the output drivers thereof. 
         [0002]    In many cases, the calibration circuit of an integrated circuit is continually running and updating at a given frequency in the background not specified by the user. Ideally, the calibration circuit of the integrated circuit would only determine if the impedance of the output driver is correct when the power supplies are quiet. But, given that the output drivers are on a chip that executes other commands that can create noise on the power supplies, it is difficult to time exactly the best time to calibrate. It is possible the user might have asked the part to execute a command that creates noise, yet the calibration circuit has been internally requested to execute. So, there is conflict. Does the part calibrate, or execute the user&#39;s requested command, or both? 
         [0003]    Therefore, instead of continually running the calibration circuit in the background, it is desirable to leave it up to the user to indicate when to calibrate. As such, this creates a unique environment for the calibration circuit; there is now a need for quick calibration so as to not impede other operations of the chip the output drivers are involved in. Furthermore, because of this need for a quick calibration and because with speed typically comes undesirable noise causing calibration error, sometimes noted as Ldi/dt noise, a system that is also noise tolerant is desirable. 
         [0004]    In a typical application of a calibration circuit, the user supplies a known resistance to a pad which interfaces the outside world to the internals of the chip—specifically interfacing a calibration circuit to output drivers used for reading data in a normal operation of a chip. A typical calibration circuit  102  is shown in  FIG. 1  and described in further detail below. When connecting to the outside world, there are some unknowns; specifically, how much interconnect and parasitic capacitance is added to the pad. And because the circuit interfaces to the outside world, will there be Electrostatic Discharge (ESD) into the pad that could harm some of the internal circuits? 
         [0005]    Since capacitance will undoubtedly be added with the addition of the user&#39;s resistor and interconnect, it is desirable to have a calibration system that can tolerate a relatively large capacitance yet still calibrate quickly. The prior art calibration circuit shown in  FIG. 2  lacks this quality. Since it first calibrates the P-channel transistors by turning on and off gates PON-&lt;N: 0 &gt; until the voltage at node ZQ is ½ VCC, and then calibrates the N-channel transistors to a replicated copy of the P channel drivers by turning on and off gates NON&lt;N: 0 &gt; until the voltage at node DQOUT is ½ VCCE, there is time lost by calibrating the P-channel driver transistors first, then the N-channel driver transistors. Furthermore, because there is potentially a relatively large amount of capacitance on ZQ, Czq  223 , the calibrator circuit  200  will have to wait an amount of time for VZQ to settle each time PON-&lt;N: 0 &gt; changes proportional to Czq. This is because there is a fixed amount of current available to charge the ZQ node. Therefore circuit  200  does not provide a fast method of calibration. Due to the parasitic capacitance on node ZQ, each calibration step must be followed by a pre-determined delay time to allow node ZQ to reach its near steady state value before the next calibration step can be initiated, as is shown in waveform  232 . 
         [0006]    Although the prior art circuit  200  in  FIG. 2  cannot achieve a high speed of calibration, a past design, such as U.S. Pat. No. 6,919,738 B2 entitled “System and Method for Controlling the Drive Strength of Output Drivers in Integrated Circuit Devices”, has the strength of placing emphasis on making the nodes internal that need to toggle quickly. This makes the capacitance during switching of strengths a known and manageable entity. Specifically, since the switching nodes are internal, a low internal node capacitance can be designed. Thus, the overall speed of calibration can be increased. The &#39;738B2 circuit also helps speed calibration, and appears to calibrate both N- &amp; P-channel drivers simultaneously. This however does lead to more noise due to both devices being switched in and out simultaneously. Since minimizing power during non-operational times is also critical, it is desirable to be able to enable/disenable the calibration. Because of this need for enabling/disabling, the &#39;738B2 appears to be lacking a quick method for initialization if there was a large amount of parasitic capacitance on the ZQ node (shown in  FIG. 3 ). 
         [0007]    Integrated circuit  100  according to the prior art includes a calibrator circuit  102  coupled to “N” number of pullup drivers  112  and “N” number of pulldown drivers  114 . These drivers can be calibrated for internal chip purposes as well as offchip drivers. Calibrator  102  includes a calibrate state generator block  104 , a sample and hold circuit  106 , pullup driver  108 , and pulldown driver  110 . Bondpad  120  associated with the calibrator circuit  102  is coupled to output impedance ZQ  122 . Bondpad(s)  124  are coupled to the output of drivers contained in  112  and  114 . The input of pullup driver  108  receives the PON-&lt;N: 0 &gt; input signal, and the input of pulldown driver  110  receives the NON&lt;N: 0 &gt; input signal. The input of pullup drivers  112  receives the PONL-&lt;N: 0 &gt; input signals, and the input of pulldown drivers  114  receives the NONL&lt;N: 0 &gt; input signals. These signals are latched versions of the corresponding signals from sample and hold  106 . 
         [0008]    Referring now to  FIG. 3 , a basic calibration circuit  300  includes a first driver circuit  302  including P-channel transistors M 14 , and M 15  through M 16 . The gates of the transistors  328  in  FIG. 3  are controlled by a pullup counter  356 . Similarly, the gates of transistors  333  are controlled by a pulldown counter  354 . Driver circuit  300  also includes resistors R 1 , R 2 , and R 3 , also designated  303 ,  304 , and  322 , respectively. Resistor  322  is coupled to the ZQ bondpad, which in turn is coupled to operational amplifier OP 1 . A pullup driver circuit  328  includes a plurality of P-channel transistors M 6  through M 7 . A pulldown driver circuit  333  includes a plurality of N-channel transistors M 17  through M 19 . Operational amplifier OP 2  is coupled between the voltage divider R 1 /R 2 , the drain of transistor M 15  and the current mirror  350 / 352 . Operational amplifier OP 3  is coupled between the drain of transistor M 15 , the drain of transistor M 7 , and the pullup counter  356 . Operational amplifier OP 4  is coupled between VZQ, the drain of transistor M 16 , and the pulldown counter  354 . 
         [0009]    Calibration circuit  300  adjusts the gate voltage of transistor M 14  until VZQ is equal to VCCE/2. Then, the gates of the transistors in driver circuits  328  and  333  are switched on and off until the voltages VP and VN equal VCCE/2. The method of calibration used by circuit  300  calibrates both the P-channel transistors in driver  328  and the N-channel transistors in driver  333  simultaneously since the same clock goes into both drivers. This leads to an undesirable noise effect generated by turning on and off the strongest drivers at the same time. 
         [0010]    In both cases of the prior art shown in  FIGS. 2 and 3 , if the calibration circuit must interface with the outside world, ESD has been neglected. Certainly it is possible that the resistor to be calibrated to is internal to the chip, and therefore the ESD protection for the calibration circuit is not needed. However, within the scope of this invention, it is assumed it must be able to but is not required to interface with the outside world. Neither calibration circuit shown in  FIG. 1  or  FIG. 3  is able to quickly calibrate with noise tolerance the output driver section when there is a great deal of parasitic capacitance on the external bondpad node associated with the external reference impedance. 
         [0011]    What is desired, therefore, is a calibration circuit for calibrating the output driver section of an integrated circuit that is able to operate quickly with noise tolerance and accurately, even if there is a large capacitance associated with the bondpad coupled to the external reference impedance. 
       SUMMARY OF THE INVENTION 
       [0012]    According to the present invention, a calibration circuit for an output driver section of an integrated circuit is able to effectively tolerate a relatively large parasitic capacitance on the bondpad coupled to an external reference impedance (the “ZQ” pad). To accommodate this, the circuit and method of the present invention incorporates the prior art approach of making the nodes internal that need to charge or discharge during calibration. However, the circuit and method of the present invention further improves this basic technique. For speed, the circuit and method of the present invention includes transistor devices to bring the voltage on the ZQ bondpad to its final steady-state value very quickly. The calibration circuit of the present invention also shares parts of the P-channel and N-channel calibration. In order to alleviate noise generated on the supplies and hence to a more accurate calibration, the circuit and method of the present invention time shifts the calibration of the strongest P-channel and N-channel drivers. In other words, the circuit and method of the present invention calibrates the strongest N-channel driver transistor, waits for a predetermined delay time, then calibrates the strongest P-channel driver transistor, waits, then calibrates the remaining P-channel and N-channel drivers simultaneously. This approach maximizes performance for both speed and noise. According to the present invention, it is certainly possible to time shift the other tunable legs in the output driver as well. Also, in order to fully make the calibration circuit interface with the outside world, the present invention includes several key ESD protection devices. 
         [0013]    The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a block diagram of an integrated circuit including an output driver block and a calibration circuit having P-channel and N-channel transistors calibrated in parallel and an external resistor coupled to ground according to the prior art; 
           [0015]      FIG. 2  is a circuit schematic of a calibration circuit that first calibrates P channels and then calibrates N channels to P channels according to the prior art; 
           [0016]      FIG. 3  is a circuit schematic of an embodiment of a calibration circuit shown in  FIG. 1  according to the prior art; 
           [0017]      FIG. 4  is a block diagram of a calibration circuit according to a first embodiment of the present invention; 
           [0018]      FIG. 5  is a circuit schematic of a calibration circuit according to a first embodiment of the present invention; 
           [0019]      FIG. 6  is a block diagram of a calibration circuit according to a second embodiment of the present invention; 
           [0020]      FIG. 7 . is a circuit schematic of a calibration circuit according to a second embodiment of the present invention; 
           [0021]      FIG. 8 . is a timing diagram associated with the calibration circuit of the present invention shown in  FIGS. 4 and 5 ; and 
           [0022]      FIG. 9  is a timing diagram associated with the calibration circuit of the present invention shown in  FIGS. 6 and 7 . 
       
    
    
     DETAILED DESCRIPTION  
       [0023]    Referring now to  FIG. 4 , a block diagram of a calibration circuit  400  according to a first embodiment of the present invention is shown. At the block diagram level,  FIGS. 1 and 4  are very similar, except for the EN enable signal shown in  FIG. 4 . All of the other blocks correspond to blocks shown in  FIG. 1 . For example blocks  102 ,  104 ,  106 ,  108 ,  110 ,  112 , and  114  shown in  FIG. 1  correspond to blocks  402 ,  404 ,  406 ,  408 ,  410 ,  412 , and  414  shown in  FIG. 4 . Bondpads  120  and  124  correspond to bondpads  420  and  424  shown in  FIG. 4 . Resistor  122  shown in  FIG. 1  corresponds to resistor  422  shown in  FIG. 4 . While at the block diagram level,  FIGS. 1 and 4  are similar, there are numerous differences at the transistor level and in the method of operation, as is explained below with respect to  FIG. 5 . 
         [0024]    Referring now to  FIG. 5 , a schematic diagram of a first embodiment  500  of a calibration circuit is shown according to the present invention. The user will attach a known resistance  522  to the ZQ pad. Upon initial powerup of the chip, the user will issue a calibrate command. However, this command may not be necessary since the calibration could respond to either a) a power-on detect circuit, or b) an external reset signal, or c) internal calibrate command. 
         [0025]    After the chip has received a calibrate command either by the user, a power-on detect, reset signal, or some other internally generated calibrate command, for speed considerations, VZQ (the voltage on the ZQ pad) is brought up initially via P-channel transistor mm 0  to a voltage higher than ground (VSS). Also, VCCE/2 is starting to develop via capacitor divider C 1 /C 0  and resistor divider R 9 /R 10 . It is of notable mention, that U.S. Pat. No. 6,919,738 does not take into account, at least for speed in calibration, that Opamp 1  takes time to settle, charge its internal nodes, and react to its inputs. Therefore, it cannot reliably pullup node VZQ to VCCQ/2 until its internal nodes have settled. Here, P-channel transistor mm 0  is available quicker than the operational amplifier controlled P-channel transistor mo 1  to provide pullup current. As shown in timing diagram of  FIG. 8 , also, upon receiving the calibrate command, signals NAON as well as NON&lt;N: 0 &gt; are forced high and PAON- and PON-&lt;N: 0 &gt; are forced low. This is done early before actually toggling the digital switches of the drivers so as to minimize noise on the power supplies during the actual calibration comparison of each driver to the reference resistor  522 . (Any time there is a change in current versus time, and there is inductance present whether intentional or parasitic, a voltage of LdI/dT is generated, and introduces noise in the system; therefore, it is desirable to minimize dI/dT during the actual calibration of the output driver with the reference.) Some time after receiving the calibrate command, Opamp 1  is ready and starts controlling the gate of P-channel transistor mo 1  to force the condition VZQ=VCCE/2. In order to protect the gate of the positive input to Opamp 1 , an ESD resistor is placed in series with VZQ. It is crucial that VZQ, the external pad not go directly to a gate in any of the operational amplifiers. Instead voltage VOP is used. Otherwise, excessive voltage on the pad can couple and destroy the internal operational amplifier devices. 
         [0026]    At the same time of VZQ development, the current of P-channel transistors mm 0  and mo 1  is mirrored respectively to P-channel transistors mm 2  and mo 3 , as well as mm 1  and mo 2 . Initially, the current may not be the same due to a difference in VDS of transistors mm 0  and mm 2 , and transistors mo 1  and mo 3 . Due to a non-perfect Rout as a result of drain-induced barrier lowering (DIBL), channel length modulation, and other parasitic effects, defined as Rout=dVds/dIds, Rout is not infinite in saturation. In other words, even if two devices are perfectly matched (same IV curves), if there is a change in VDS of two devices that have the same gate and source voltage, the current is not the same. Because of this non-ideal Rout, it is preferable to guarantee devices that are to have the same current to have not only the same VGS, but also the same VDS. As such, Opamp 2  has been added to create a nearly ideal current mirror of N-channel transistors moa 0  and moa 1 . Gate currents are assumed to be nearly zero. 
         [0027]    Since Opamp 2  forces the condition Vchalf=VCCE/2 and Opamp 1  forces the condition VZQ=VCCE/2, then assuming the devices mm 0 , mo 1  are matched to devices mm 2 , mo 3  respectively and resistor XNWN_ 0  is matched to resistor XNWNmatch 2 _with_ 0 , then the same VDS will be generated across transistors mm 0 , mo 1 , mm 2  and mo 3 . Here it is of mention that resistor XNWN_ 0  is placed in series with VZQ to the drain of transistor mm 0  in order to protect the drain junction of transistor mm 0  from ESD. And in order to create the aforementioned condition, VDS of transistors mm 0 , mm 2 , mo 1 , and mo 3  is to be the same. Resistor XNWNmatch 2 _with_ 0  is placed in series with Vchalf, and the drain of transistor mm 2  and resistor XNWNmatch_with_ 0  is placed in series with the drain of transistor mm 1  and DQOUT. 
         [0028]    Depending on process requirements, this device, XNWN_ 0 , XNWNmatch_with_ 0 , and XNWNmatch 2 _with_ 0  may not be necessary if the drain of a P-channel transistor, particularly the junction of transistor mm 0  is strong enough to sustain a suitable level of ESD protection. Also, it is possible the resistance, XNWN_ 0 , is intentionally combined, not a separate entity, with the drain of transistor mm 0  by increasing drain length (resistance) and therefore increasing the source-to-drain resistance of transistor mm 0 . It is of mention that XNWN_ 0  and XNWNmatch_with_ 0 , XNWNmatch 2 _with_ 0  are not only resistors but also diodes. The device is comprised of including but not limited to N-type over P-type doped silicon. Effectively, XNWN_ 0  can be included in transistor mm 0 , or can be a separate device. Or, if using minimum design rules, if the drain junction of transistor mm 0  can sustain enough ESD, XNWN_ 0  and hence XNWNmatch_with_ 0  and XNWNmatch 2 _with_ 0  need not be added. However, if XNWN_ 0  is added, XNWNmatch_with_ 0  AND XNWNmatch 2 _with_ 0  must be added, or else the VDS of transistors mm 0 , mm 1 , mm 2 , mo 1 , mo 2  and mo 3  will not be the same and hence the devices will not work as well as a current mirror. 
         [0029]    After VZQ has been brought to VCCE/2, or close to VCCE/2, NON&lt;N&gt; goes low (turns off transistor mnn), and then V(DQOUT) is compared via Opamp 3 . The corresponding timing sequence is shown in  FIG. 8 . One and a half clock cycles (1.5 clks) later Opamp 3  provides a signal as to whether V(DQOUT) is higher or lower than a voltage VCCE/2 (this time can be &lt;1.5 clks assuming Opamp 3  is fast enough, or &gt;1.5 clks, but 1.5 clks was chosen for ease in design). If V(DQOUT) is lower, NON&lt;N&gt; is kept off, or else it turns back on (goes high). It is of notable mention that the control signals, NON &lt;N: 0 &gt; and PON-&lt;N: 0 &gt; and NAON, PAON- should be of equal voltage level to that of the real output buffers contained on the chip. Also, VCCE/2 is a theoretical voltage assuming perfect operational amplifiers and components. Operational amplifiers  3  and  4  can use a node different than VCCE/2 as noted in  FIG. 5 . 
         [0030]    Then, four clocks after the start of NON&lt;n&gt; falling PON-&lt;N&gt;goes high (turns off transistor mpn), and V(DQOUT 2 ) is compared via Opamp 4  as to whether V(DQOUT 2 ) is higher or lower than a voltage VCCE/2. If 1.5 clock cycles later, V(DQOUT 2 ) is higher than VCCE/2, then transistor mpn stays off (PON-&lt;N&gt; stays high). Otherwise, if V(DQOUT 2 ) is lower than VCCE/2, then transistor mpn turns back on. 
         [0031]    Then, two clock cycles after the start of PON-&lt;N&gt; going high, NON&lt;n- 1 &gt; goes low and PON-&lt;n- 1 &gt; goes high. And 1.5 clks later V(DQOUT) and V(DQOUT 2 ) are sampled by Operational amplifiers  3  and  4  respectively. If V(DQOUT) is &gt;VCCE/2, then NON&lt;n- 1 &gt; goes back high, otherwise it stays low. Similarly, if V(DQOUT 2 ) is &gt;VCCE/2 then PON-&lt;N- 1 &gt; stays high, otherwise it goes back low. This sequence repeats until the last driver transistors mp 0  and mn 0  are turned off and the results compared via Operational amplifiers  3  and  4 . At the end, a code of PON-&lt;N: 0 &gt; and NON&lt;n: 0 &gt; has developed and represents the required devices to be turned on and off to achieve a match within a certain tolerance of the output driver impedance to the user&#39;s applied resistance. 
         [0032]    These codes are latched and so named PONL-&lt;N: 0 &gt;, NONL&lt;N: 0 &gt; during the calibration process and sent off to a copy of the buffers that were used in calibration, namely POUT_DVR and NOUT_DVR. It is of note that the driver transistor mnn is intended to be 2̂n times as strong as transistor mn 0  but could be slightly off due to process variation. Also, transistor mpn is 2̂n times as strong as transistor mp 0 , and it too can be slightly off due to processing errors. 
         [0033]    It should be noted that P-channel and N-channel calibration can be performed simultaneously, or can be time-shifted for optimizing noise and speed. In  FIG. 5 , the ESD resistor is placed near the gate of the positive terminal of Opamp 1 . Due to channel length modulation, DIBL, and other parasitic effects, for good current matching, the VDS of transistors mo 1 , mo 2 , mo 3 , mo 0 , moa 1  are set to be equal via Operational amplifiers  1  and  2 . The output of Opamp 1  switches to VCCE when disabling transistors m 01 , mo 2 , and mo 3 . The AC compensation circuits for the operational amplifiers in  FIG. 5  are left out for simplicity, but can be used in an actual design. AC compensation circuits are well known to those skilled in the art and vary with according to the actual operational amplifiers used, component selection, and component values in the design of the calibration circuit  500  of  FIG. 5 . The PASSGATE used in  FIG. 5  is to limit the capacitance on bondpad ZQ when the calibration circuit is turned off. It is of note, multiple calibrators could share the same ZQ resistor, and therefore it is desirable to limit the capacitance by including the PASSGATE. The pullup and pulldown circuits can include binary-weighted transistors if desired, although this is difficult to achieve in an actual implementation. The pullup and pulldown circuits NOUT_DVR and POUT_DVR each have N control signals (six control signals are used in an embodiment of the present invention) for a total of thirty-two ZOUT steps per P-driver/N-driver (one control signal of the six, not changed by the calibrator, but could be controller by the calibrator as well, if desired). The VOP voltage shown in  FIG. 5  is associated with Opamp 1 . Preferably, VOP is not used with respects to Operational amplifiers  2 ,  3 , and  4  so as to not unnecessarily slow the settling of VZQ on the ZQ bond pad by adding extra capacitance to the VOP node. 
         [0034]    Successive approximation is used in capturing the NTOOWEAK and PTOOSTRONG signals. This allows for five unique clock cycles need for P-calibration and five unique cycles for N-calibration. The P-calibration and N-calibration can be done at the same time, but for noise alleviation, they can be time shifted. For example, the strongest N device (NON&lt;N&gt;) can be calibrated first then the strongest P device (PON-&lt;N&gt;) then the second strongest P(PON-&lt;N- 1 &gt;) and N(NON&lt;N- 1 &gt;) can be done simultaneously. 
         [0035]    The successive approximation algorithm according to the present invention starts with all devices on (either P-channel or N-channel). Every two clock cycles, turn off the highest order devices. For example, for five devices, mp 5  is turned off first, then sample PTOOSTRONG. If PTOOSTRONG is asserted (equal to a logic one), keep device mp 5  off. Otherwise turn device mp 5  back on, then turn off device mp 4 , then sample PTOOSTRONG. If PTOOSTRONG is equal to one, keep mp 4  off. Otherwise turn device mp 4  back on, until mp 0  is turned off and sampled. At the end a code of PON-&lt; 4 : 0 &gt; will have developed. That code will be the calibration code for P-channel devices. The same sequence occurs for N-channel transistors and can occur at the same time as P-calibration, or shifted in time for noise purposes. 
         [0036]    Capacitor divider C 0 /C 1  is used for quick, low power VCCE/2 generation. Transistor mm 0  is used for quick ZQ initialization, since operational amplifiers are slower to respond than current mirrors. Transistors mm 1  and mm 2  are used for mirroring the current of transistor mm 0 . 
         [0037]    Referring now to  FIG. 6 , a block diagram of a calibration circuit  600  according to a second embodiment of the present invention is shown. At the block diagram level,  FIGS. 4 and 6  are very similar, except that resistor  622  in  FIG. 6  is coupled to VCCE and not to ground as is shown for resistor  422  in  FIG. 4 . All of the other blocks correspond to blocks shown in  FIG. 4 . For example blocks  402 ,  404 ,  406 ,  408 ,  410 ,  412 , and  414  shown in  FIG. 4  correspond to blocks  602 ,  604 ,  606 ,  608 ,  610 ,  612 , and  614  shown in  FIG. 6 . Bondpads  420  and  424  correspond to bondpads  620  and  624  shown in  FIG. 6 . Resistor  422  shown in  FIG. 4  corresponds to resistor  622  shown in  FIG. 6 . 
         [0038]      FIG. 7  is a circuit schematic of a calibration circuit according to the second embodiment of the present invention. While circuit  700  is substantially the same as described in  FIG. 5 , the external resistor  722  is coupled to VCCE, and not to ground as is shown in circuit  500  of  FIG. 5 . 
         [0039]    The timing diagram of  FIG. 9  is substantially the same as the timing diagram of  FIG. 8 . However, note that the ZQ voltage waveform is different since external resistor  722  is coupled between the ZQ bonding pad and VCCE, and not ground as is the case with the timing diagram of  FIG. 8 . 
         [0040]    Having described and illustrated the principle of the invention in a preferred embodiment thereof, it is appreciated by those having skill in the art that the invention can be modified in arrangement and detail without departing from such principles. Although a preferred method and circuit has been shown, the exact details of the preferred method and circuit can be changed as desired as required for a particular application. For example, removing XNWN resistors/diodes, having more tuning devices for finer resolution in the driver circuits, using an internal resistor instead of an external calibration resistor, removing operational amplifiers and just using traditional current mirrors whereby the VDS is not necessarily guaranteed to be the same for all devices, and using control signals that are generated simultaneously for at least one set of drivers but not for all drivers can all be used individually or in combination if acceptable in a particular application. We therefore claim all modifications and variations coming within the spirit and scope of the following claims.