Abstract:
Disclosed is a test pattern for a reliability measurement of a copper interconnection line having a moisture window and a method for manufacturing the same. The method includes the steps of: a first inter-layer insulation layer formed on the substrate; a plurality of bottom copper interconnection lines buried in the first inter-layer insulation layer; a second inter-layer insulation layer on the plurality of bottom copper interconnection lines and the first inter-layer insulation layer; a plurality of top copper interconnection lines filled in the second inter-layer insulation layer and connected to the plurality of bottom copper interconnection lines through the plurality of via contacts; and a passivation layer covering the plurality of top copper interconnection lines and having a plurality of moisture windows in which moistures are flown during an electro migration (EM) test.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a method for a test pattern; and more particularly to a test pattern capable of measuring an electro migration.  
       DESCRIPTION OF RELATED ARTS  
       [0002]     A method for measuring an electro migration (EM) is used for testing a reliability of an interconnection line of a semiconductor device. In general, an EM phenomenon metal atoms move is taken place between the semiconductor devices, and more particularly between metal interconnection lines within the semiconductor devices. The EM phenomenon deteriorates the semiconductor devices and causes a mis-operation of the semiconductor devices. Therefore, it is required to understand reasons resulting in the above problems through precisely measuring the EM phenomenon generated between the metal interconnection lines during manufacturing the semiconductor devices, thereby making a proper countermeasure to solve the problems.  
         [0003]     As for a typical method for measuring the EM phenomenon, there is a method for measuring a package level EM. However, the method needs a high expense for a package, a high investment for measuring equipment, and a long running time for measuring the EM phenomenon. Recently it is very competitive to develop the semiconductor devices, thus the test requiring not only a high expense for research and development but also a long developing time can cause a very critical problem.  
         [0004]     In order to overcome this problem, a method for measuring a wafer level EM is suggested. The method for measuring a wafer level EM is a method performed before a package process has not been finished. The above method has an advantage to reduce a required time and expense compared to the method for measuring a wafer level EM.  
         [0005]      FIG. 1A  is a top view illustrating a conventional copper interconnection line structure for measuring an EM.  FIG. 1B  is a cross-sectional view of the conventional copper interconnection line structure taken along a direction of a line A-A′ shown in  FIG. 1A .  FIG. 1C  is a cross-sectional view of the conventional copper interconnection line structure taken along a direction of line B-B′ shown in  FIG. 1A .  
         [0006]     Referring to  FIG. 1A , a plurality of bottom metal patterns  10  are connected to a plurality of top metal patterns  20  through a plurality of via contacts  30  in a chain structure. Each of the top metal patterns  20  is connected to a plurality of corresponding aluminum pads  40 .  
         [0007]     Referring to  FIG. 1B , the plurality of copper interconnection lines  10  is formed on a bottom layer  11 , i.e., an insulation layer formed on a semiconductor substrate (not shown). Although not shown, the plurality of bottom copper interconnection lines  10  are connected to a reacted region or another region of the substrate through the plurality of contacts formed through the bottom layer  11 . And the plurality of the bottom copper interconnection lines  10  are formed on the bottom layer  11  in a same distance.  
         [0008]     Next, a first inter-layer insulation layer  12  is formed for insulation between the plurality of bottom copper interconnection lines  10 . Then, an inter-metal insulation layer  13  is formed on the plurality of bottom copper interconnection lines  10  and the first inter-layer insulation layer  12 . The plurality of top copper interconnection lines  20  are formed on the inter-metal insulation layer  13  in a same distance. Herein, the plurality of bottom copper interconnection lines  10  and the plurality of top copper interconnection lines  20  are interconnected through the plurality of the via contact  30 .  
         [0009]     The plurality of top copper interconnection lines  20  are insulated by the second inter-layer insulation layer  14  and a passivation layer  15  completely covering the plurality of bottom copper interconnection lines  20  and the second inter-layer insulation layer  14  is formed.  
         [0010]     Referring to  FIG. 1C , one of the plurality of bottom copper interconnection lines  10  is electrically connected to two of the plurality of top copper interconnection lines  20  by passing the inter-metal insulation layer  13  through the plurality of via contacts  30 . Therefore, a chain contact structure is formed.  
         [0011]     Although not shown, the passivation layer is formed on the plurality of top copper interconnection lines  20  through proceeding an etching process.  
         [0012]     However, a final interpretation of a method for measuring the wafer level EM having the above copper interconnection line structure can be changed depending on a condition provided by each test. There may be a mis interpretation of a data due to a phenomenon that probe slides from the aluminum pad while measuring. Also, a failure of wiring produced by a failure of a passivation layer process may be misinterpreted.  
       SUMMARY OF THE INVENTION  
       [0013]     It is, therefore, an object of the present invention to provide a test pattern for a reliability measurement of a copper interconnection line having a moisture window and a method for manufacturing the same capable of measuring an EM under a more severe condition than an actual measuring condition by making moisture flow in through forming a window that makes the moisture possible to penetrate an inter-layer insulation layer.  
         [0014]     In accordance with an aspect of the present invention, there is provided a test pattern for a reliability measurement of a copper interconnection line, including: a semiconductor substrate; a first inter-layer insulation layer formed on the substrate; a plurality of bottom copper interconnection lines filled in the first inter-layer insulation layer; a second inter-layer insulation layer on the plurality of bottom copper interconnection lines and the first inter-layer insulation layer; a plurality of top copper interconnection lines filled in the second inter-layer insulation layer and connected to the plurality of bottom copper interconnection lines through the plurality of via contacts; and a passivation layer covering the plurality of top copper interconnection lines and having a plurality of moisture windows in which the moisture is flown during an electro migration test.  
         [0015]     In accordance with another aspect of the present invention, there is provided a method for fabricating a test pattern for reliability measurement of a copper interconnection line with a moisture window, including the steps of: forming a trench inside of the first inter-layer insulation layer on the substrate; forming the second inter-layer insulation layer on the plurality of bottom copper interconnection lines and the first inter-layer insulation layer; forming the plurality of top copper interconnection lines buried in the second inter-layer insulation layer through a dual damascene process and connected to the plurality of bottom copper interconnection lines through a plurality of via contacts; and forming a passivation layer provided with the plurality of moisture windows allowing the moisture to flow in while testing the EM and covering the second inter-layer insulation layer and the plurality of top copper interconnection lines.  
         [0016]     In accordance with further aspect of the present invention, there is provided a method for fabricating a test pattern for reliability measurement of a copper interconnection line with a moisture window, including the steps of: forming the plurality of bottom copper interconnection lines connected to the plurality of top copper interconnection lines through the plurality of the via contacts; forming the passivation layer provided with the moisture window allowing the moisture to flow in the top portion of the plurality of top copper interconnection lines during the reliability measurement; measuring a degree of resistance of the plurality of top copper interconnection lines and the plurality of bottom copper interconnection lines in the air; measuring again the degree of resistance of the plurality of top copper interconnection lines and the plurality of bottom copper interconnection lines on a hot plate by applying a heat process; and finishing the reliability measurement at a point where the resistance change of the bottom copper interconnection line and the top copper interconnection line is great. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0018]      FIG. 1A  is a top view illustrating a conventional copper interconnection line structure for an EM measurement;  
         [0019]      FIG. 1B  is a cross-sectional view of the conventional copper interconnection line structure taken along a direction of a line A-A′ shown in  FIG. 1A ;  
         [0020]      FIG. 1C  is a cross-sectional view of the conventional copper interconnection line structure taken along a direction of a line B-B′ shown in  FIG. 1A ;  
         [0021]      FIG. 2A  is a layout illustrating a test pattern for a reliability measurement of a copper interconnection line having a moisture window in accordance with a preferred embodiment of the present invention;  
         [0022]      FIG. 2B  is a cross-sectional view taken along a direction of a line C-C′ shown in  FIG. 2A ;  
         [0023]      FIGS. 3A  to  3 D are cross-sectional views illustrating a method for manufacturing a test pattern for a reliability measurement of a copper interconnection line according to a line C-C′ shown in  FIG. 2A ; and  
         [0024]      FIG. 4  is a result of an EM test on a wafer including both a test pattern with and without a moisture window. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0025]     A method for a test pattern for measuring a reliability of a copper interconnection line having a moisture window and a method for manufacturing the same in accordance with a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.  
         [0026]     The present invention relates to a method of an EM test using a diffusion phenomenon of a copper atom due to moisture. In general, there happens a diffusion phenomenon that copper atoms of a copper interconnection line flows out into an inter-layer insulation layer due to the moisture flown in from outside or the moisture remaining in an inter-layer insulation layer surrounding the copper interconnection line.  
         [0027]     For instance, the present invention uses the diffusion phenomenon of the copper atoms due to the moisture; and more particularly uses a theory that a possibility of failing during the actual EM test of the copper interconnection line apparently decreases if failing is not taken place for a test of a diffusion barrier layer by testing a reliability of the diffusion barrier layer by compulsorily promoting the diffusion phenomenon of the copper atoms.  
         [0028]     For reducing the possibility of failing during the EM measurement, the EM test is proceeded under the more severe condition than the actual EM test by forming the moisture window to flow in the moisture.  
         [0029]     If a result of the EM test performed under the more severe condition than an actual EM test shows good, a property of the EM of an actual copper interconnection line is good.  
         [0030]     In accordance with a preferred embodiment of the present invention, a test pattern for a reliability measurement of a copper interconnection line having a moisture window and a method of manufacturing the same is explained in more detail.  
         [0031]      FIG. 2A  is a layout illustrating a test pattern for a reliability measurement of a copper interconnection line having a moisture window in accordance with a preferred embodiment of the present invention.  
         [0032]     Referring to  FIG. 2A , a plurality of test pattern groups TP 1  and TP 2  connected in a chain shape through a plurality of via contacts  112  is a combination body of segments having two of a plurality of bottom copper interconnection lines  105  are connected to one of a plurality of top copper interconnection lines  113 , i.e., a structure connecting two of the plurality of bottom copper interconnection lines  105  to one of the plurality of top copper interconnection lines  113  through the plurality of via contacts  112  placed at two ending points of the plurality of bottom copper interconnection lines  105 . The top copper interconnection line  113  of each segment is connected to each corresponding aluminum pad  116 . Therefore, one segment includes one top copper interconnection line  113  and one bottom copper interconnection line connected to one aluminum pad  116 . A structure of the test pattern group explained in the above is same as that shown in  FIG. 1A .  
         [0033]     The present invention forms a plurality of moisture windows  118 A and  118 B to make the moisture flow in during the test. The moisture windows  118 A and  118 B are formed between the plurality of top copper interconnection lines  113  of each segment consisting one test pattern group or between the plurality of test pattern groups. Herein, a reference numeral  118 A denotes the moisture window which is relatively short compared to the moisture window  118 B formed between the plurality of test pattern groups.  
         [0034]      FIG. 2B  is a cross-sectional view taken along a direction of line C-C′ shown in  FIG. 2A .  
         [0035]     Referring to  FIG. 2B , a first inter-layer insulation layer  101  and a first etch barrier layer  102  is stacked on the substrate (not shown) having devices such as a transistor. Then, a first trench  103  in which the bottom copper interconnection line is formed is formed on the first inter-layer insulation layer  101  and the first etch barrier layer  102 . A first diffusion barrier layer  104  is formed inside of the first trench  103  and the bottom copper interconnection line  105  is formed filling a space surrounded by the first diffusion barrier layer  104  within the first trench  103 .  
         [0036]     An inter-metal insulation layer  106 , a second etch barrier layer  107  and a second inter-layer insulation layer  108  are stacked on the bottom copper interconnection line  105  and the first etch barrier layer  102 . A plurality of via holes  110  are formed inside of a layer stacking the inter-metal insulation layer  106  and the second etch barrier layer  107 . A plurality of second trenches  109  are formed inside of the second inter-layer insulation layer  108 . The plurality of second trenches  109  and the plurality of via holes  110  are dual damascene patterns typically formed by a dual damascene process. The plurality of second trenches  109  are line patterns and the plurality of via holes  110  are hole patterns.  
         [0037]     Next, a second diffusion barrier layer  111  is formed inside of the plurality of second trenches  109  and the plurality of via holes  110 . A plurality of bottom interconnection lines  113  and the plurality of via contacts  112  are formed to fill a space surrounded by the second diffusion barrier layer  111  within the plurality of second trenches  109  and the plurality of via holes  110 . Herein, the plurality of top copper interconnection lines  113  and the plurality of via contacts  112  have the same structures. After being formed with use of a plating method, the plurality of top copper interconnection lines  113  and the plurality of via contacts have flat surfaces through a chemical and mechanical polishing (CMP) process.  
         [0038]     Next, a third etch barrier layer  114  and a passivation layer  115  are stacked on the plurality of top copper interconnection lines  113  and the second inter-layer insulation layer  108 . The moisture window  118 A is formed inside of the third etch barrier layer  114  and the passivation layer  115 . Herein, the moisture window  118 A is not formed in a shape to expose the plurality of top copper interconnection lines  113 . Therefore, the passivation layer  115  and the third etch barrier layer  114  providing the plurality of moisture windows  118 A covers the plurality of top copper interconnection lines  113 . A reason that the moisture window  118 A is not formed to directly expose the plurality of top copper interconnection lines  113  is to prevent oxidation of the plurality of top copper interconnection lines  113  caused by that the moisture flown in through the moisture window  118 A directly touches the plurality of top copper interconnection lines  113 .  
         [0039]     Referring to  FIGS. 2A  to  2 B, the first etch barrier layer  102 , the second etch barrier layer  107  and third etch barrier layer  114  are made up of a silicon nitride layer (Si 3 N 4 ). The first diffusion barrier layer  104  and the second diffusion barrier layer  111  for preventing that the copper atoms of the plurality of bottom copper interconnection lines  105  and the plurality of top copper interconnection lines  113  diffuses into the fist inter-layer insulation  101 , second inter-layer insulation layer  108  and the inter-metal insulation layer  106  as oxides may be stacked with TiN, Ti, and Ti/TiN.  
         [0040]     Referring to  FIG. 3A , the first inter-layer insulation layer  101  and the first etch barrier layer  102  are formed on the substrate (not shown) having devices such as transistors formed on a surface of the substrate. Then, the first trench  103  is formed by etching the first etch barrier layer  102  and the first inter-layer insulation layer  101  simultaneously.  
         [0041]     Next, the first diffusion barrier layer  104  and the copper layer are formed on the substrate to fill the first trench  103 . Then the plurality of bottom copper interconnection lines  105  are formed through the CMP process to remain the whole copper layer on the first etch barrier layer  102  only in the first trench  103 . Herein, the plurality of bottom copper interconnection lines  105  serve a role for filling a space surrounded by the first diffusion barrier layer  104  within the first trench  103  and the first diffusion barrier layer  104  serves a role for preventing that the copper atoms of the plurality of bottom copper interconnection lines  105  diffuse into the first inter-layer insulation layer  101  as oxides.  
         [0042]     Next, the inter-metal insulation layer  106 , the second etch barrier layer  107  and the second inter-layer insulation layer  108  are stacked on the first etch barrier layer  102  including the plurality of bottom copper interconnection lines  105 . Then, through the dual damascene process, the plurality of via holes  110  exposing a part of the plurality of bottom copper interconnection lines  105  formed under the plurality of second trenches having line shapes.  
         [0043]     Referring to  FIG. 3B , to fill the plurality of second trenches  109  and the plurality of via holes  110 , the second diffusion barrier layer  111  and the copper layer are formed on all sides of the second trench  109 . Then, the plurality of via contacts  112  and the plurality of top copper interconnection lines  113  are formed at once filling a space surrounded by the second diffusion barrier  111  within the plurality of second trenches  109 . The second diffusion barrier layer  111  serves a role to prevent the copper atoms of the plurality of top copper interconnection lines  113  and the plurality of via contacts  112  from diffusing into the inter-metal insulation layer  106  and the second inter-layer insulation layer  108  which are oxides.  
         [0044]     Referring to  FIG. 3C , the third etch barrier layer  114  and passivation layer  115  are sequentially stacked on the second inter-layer insulation layer  108  including the plurality of top copper interconnection lines  113 . Herein, the third etch barrier layer  114  serves a role to prevent the second inter-layer insulation  108  from being etched back while the etching process is applied to the passivation layer for forming the aluminum pad and the moisture window performed during subsequent processes.  
         [0045]     Next, a pad mask (not shown) is formed through a mask using a photosensitive layer on the passivation layer and the etching process. Afterwards, the passivation layer  115  and the third etch barrier layer  114  are sequentially subjected to a pad etching process with use of the pad mask as an etch mask. An opening unit exposing an end point of the plurality of top copper interconnection lines  113  is formed. Then, the plurality of aluminum pads  116  as shown in  FIG. 2A  is formed by depositing the plurality of aluminum pads on all sides of the plurality of top copper interconnection lines  113  including the opening unit and applying the etching process to the plurality of top copper interconnection lines  113  including the opening unit. Herein, the plurality of aluminum pads  116  as shown in  FIG. 2A  connects to each corresponding top copper interconnection line  113  to make it possible to find out the plurality of top copper interconnection lines showing failing results.  
         [0046]     Next, the photosensitive layer is formed again on the passivation layer  115  and a plurality of moisture window mask  117  is formed for forming the moisture window through an additional mask and the etching process. Then, the moisture window  118 A is formed by applying the etching process to a part of the passivation layers  115  and the third etch barrier layer  114  with use of the moisture window mask  115  as the etch mask. Herein, the reference numeral  118 A denotes the plurality of moisture windows having relatively short lengths compared to the moisture window shown in  FIG. 2A .  
         [0047]     Referring to  FIG. 3D , the moisture window mask is removed. The second inter-layer insulation layer  108  is a portion exposed under the moisture window  118 A formed through a series of processes illustrated in the above. That is, the plurality of moisture windows  118 A having a line shape is located on the second inter-layer insulation layer  108  between the top copper interconnection lines  113 .  
         [0048]     The plurality of moisture windows  118 A shown in  FIG. 2A , are formed between each segment of the test pattern groups forming a chain structure connected by the plurality of via contacts. The other moisture window denoting the reference numeral  118 B is a window having a long length formed between the test pattern groups.  
         [0049]     As illustrate in the above, after forming the moisture window  118 A and  118 B, the moisture in the air flows into the second inter-layer insulation layer  108  through the plurality of moisture windows  118 A and  118 B. And the moisture flown into the second inter-layer insulation layer diffuses into a sidewall of the plurality of top copper interconnection lines  113  while the EM test and finally deteriorates a condition of the EM test.  
         [0050]     Next, an explanation about the method of the EM test of the copper interconnection line in accordance with the present invention is following.  
         [0051]     In order to observe the EM phenomenon, a resistance of the test pattern in the air is measured. Then, the wafer is put on a hot plate and is subjected to a heat treatment performed at a temperature of 350° C. Afterwards, the resistance is measured again and then, results of the each test are compared.  
         [0052]     When comparing the results, the EM measurement is finished at a point where the resistance greatly changes. Herein, the point where the resistance greatly changes represents a moment when the moisture in the air is flown in through the moisture window. Then, the moisture flown in is applied to a heat treatment. While applying the heat treatment to the moisture flown in, a diffusion of the copper atoms of the plurality of bottom copper interconnection lines  105  and the plurality of top copper interconnection lines  113  is compulsorily promoted. Therefore, a change in the resistance of the plurality of copper interconnection lines is great.  
         [0053]     If the result of the EM test shows good, which means there is almost no change in the resistance, a property of the EM of the plurality of the copper interconnection lines is good. If the result of the EM test shows failing, which means there is a great change in the resistance, the property of the EM of the plurality of copper interconnection lines is poor.  
         [0054]      FIG. 4  is the result of the EM test on the wafer including both test patterns with and without the moisture window. Referring to  FIG. 4 , a mark G represents ‘good’, a mark F represents ‘fail’, and a mark X represents ‘die’ generating failing before a heat treatment. And a white rectangular represents the test pattern without the moisture window and a hatched rectangular represents the test pattern with the moisture window. All of the results shown in  FIG. 4  are obtained after applying the heat treatment to the moisture flown in through the moisture window for 1 hour.  
         [0055]     Referring to  FIG. 4 , in case of performing the EM test by applying the heat treatment for 1 hour, the test pattern with the moisture window has more possibility of having F than the test pattern without the moisture window. For instance, as for the test pattern without the moisture window, no dies produce F after the heat treatment. However, as for the test pattern with the moisture window, only 2 dies out of 17 dies do not produce F except for the 3 dies marked by X shown in  FIG. 4  which is failed before applying the heat treatment after forming the moisture window formed after the heat treatment.  
         [0056]     In accordance with a preferred embodiment of the present invention, the plurality of bottom copper interconnection lines  105  and the plurality of top copper interconnection lines  113  are made up of pure copper layers. However, a copper compound metal can be used to form the plurality of bottom and top copper interconnection lines. Also, instead of using the plating method for forming the copper layer, a sputtering method can be used. Furthermore, instead of the CMP process for planarizing the surface of the copper layer, the etching process can be applied.  
         [0057]     The present invention compulsorily promotes the diffusion of the copper atoms by forming the plurality of moisture windows on the test pattern structure for the EM measurement.  
         [0058]     Furthermore, the present invention uses the test pattern capable of accelerating the diffusion of the copper atoms, thereby obtaining a very fast feed back. Therefore, it enables to fabricate the semiconductor device timely.  
         [0059]     The present application contains subject matter related to the Korean patent application No. KR 2003-0081395, filed in the Korean Patent Office on Nov., 18, 2003 the entire contents of which being incorporated herein by reference.  
         [0060]     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.