Abstract:
An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the driver circuit in the active or high impedance modes. A feedback signal generated by the driver output and the driver enable signals controls an inverter circuit within the driver circuit to provide proper biasing conditions at the gate of the pull up transistor. This feed back provides fast switching times for the driver circuit and prevents gate oxide of all the transistors from being overstressed by the external high voltage signal.

Description:
RELATED APPLICATIONS 
   This patent application claims the benefit of the earlier-filed U.S. Provisional Patent Application entitled “High Voltage Tolerant Off Chip Driver Circuit” having Ser. No. 60/578,370 which was filed on Jun. 9, 2004. 

   FIELD OF THE INVENTION 
   The invention relates to off chip driver circuits used in semiconductor components, and in particular, the manner is which such off chip driver circuits relate to CMOS off chip driver circuits. 
   BACKGROUND 
   ASIC (Application Specific Integrated Circuit) components fabricated in older semiconductor processes were designed to operate at higher power supply voltage (5 volts was the standard power supply voltage for many years). However, ASIC components designed for use in newer semiconductor processes can only support lower operating power supply voltages (3.3 volts or lower). In a large number of system applications, components in the older and newer processes communicate with each other. Consequently, ASICs that are in systems that can only support lower power supply voltages need high voltage tolerant input and/or output driver circuits. In the prior art, high voltage tolerant off chip driver circuits have drawbacks such as high leakage from output pad to ground or power supply, over-stressing of transistor junctions because of high voltage external signal levels, and increased transition delays and excessive power dissipation. 
   An example of a prior art off chip driver circuit is disclosed in U.S. Pat. No. 5,151,617. A circuit diagram from that patent is reproduced herein as  FIG. 1 . This design operates at 3.3 volts power supply (Vdd), and it communicates with another design, which produces a 0 to 5 Volt signal level at the common node (Output Pad) of the two drivers. While this design protects all the transistors in the circuit from being over stressed by an external 5 volt signal, it has its shortcomings. 
   In active mode when the driver input switches from high to low level, outputs of the pre-driver circuit, nodes  1  and  2 , switch from low to high. Initially the transmission transistor Tp 1  is ‘Off’ and transistor Tn 1  is ‘On’. Tn 1  produces a voltage (Vdd−Vtn) at the gate of the p-channel pull-up transistor Tp 3 , which stays partially ‘On’ until driver output reaches well below (Vdd−Vtp). Vtn and Vtp are the threshold voltages of the n-channel and p-channel transistors respectively. This condition results in longer high to low transition time. During high to low transition, n-channel pull down transistor Tn 3  turns on faster and p-channel pull up transistor Tp 3  takes a longer time to turn ‘Off’ completely, which results in high short circuit or flush through current from Vdd to ground through the pull-up and pull-down transistors for a longer time. This short circuit current causes higher power dissipation. This power dissipation is due to higher current drawn by the circuit in its operation and will require a larger power supply and produce a higher module and circuit board temperature. 
   When the driver circuit in  FIG. 1  is in a high impedance mode and its output is higher than Vdd due to an external signal, Tp 2  turns on and provides higher voltage at the gate of transistor Tp 3  and turns Tp 3  off so that no current flows through Tp 3  to Vdd from the external source. Since transistor Tn 2  is in series with transistor Tn 3 , the external high voltage is reduced to below (Vdd−Vtn) across Tn 3 . Transistor Tp 4  generates bias for the Nwell region in which transistors Tp 1 , Tp 2 , and Tp 3  are formed. 
   The art would therefore benefit from an off chip driver circuit that has high performance and low power dissipation. 
   SUMMARY OF AN EMBODIMENT 
   An embodiment of the invention is an off chip driver circuit that includes pre-driver and driver circuits. Data and enable inputs to the off chip driver are decoded in the pre-driver to provide independent inputs to the pull up and pull down transistors of the driver. A feedback signal is generated by the driver output and its enable input signals. This feedback signal controls the inverter circuit that provides proper biasing conditions at the gate of a p-channel pull up transistor. This method of biasing the gate of the pull up transistor turns the pull up transistor completely off during high to low transition at the driver input. This reduces the transition time and flush through current through the pull up and pull down transistors. When the present off chip driver is in the high impedance mode and its output is switched between ground and high voltage (5.5 volts) by an external signal, an inverter circuit isolates the pre-driver circuit from the driver circuit and protects gate oxides of all the transistors from over voltage stress. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic of an off chip driver circuit of the prior art. 
       FIG. 2  is a schematic of an embodiment of a pre-driver circuit of the invention. 
       FIG. 3  is a schematic of an embodiment of a driver circuit of the invention. 
   

   DETAILED DESCRIPTION 
   In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views. 
   In an embodiment of the invention, an off chip driver circuit has a pre-driver circuit  200  and a driver circuit  300  which are illustrated in  FIGS. 2 and 3  respectively. The driver data input  210  and the driver enable input  220  are decoded in the pre-driver circuit  200 , which through NAND circuit  260 , NOR circuit  270 , and inverters  230 ,  240 , and  250 , generates proper logic levels for the driver circuit  300 . The driver circuit  300  has two operating modes, an active switching mode in which the driver is enabled, and an high impedance or tri-state mode in which the driver is disabled (and the circuit is in the non-switching mode). The enable and disable modes are controlled by the driver enable input E ( 220 ) shown in  FIG. 2 . The logic levels generated by the pre-driver circuit  200  at its output nodes  7 ,  8 , and  9  are given below: 
   
     
       
             
             
             
             
             
             
           
         
             
                 
             
             
               Driver Mode 
               Driver Enable 
               Driver Input 
               Node 7 
               Node 8 
               Node 9 
             
             
                 
             
           
           
             
               Active 
               high 
               high 
               high 
               high 
               low 
             
             
               Active 
               high 
               low 
               low 
               low 
               low 
             
             
               High 
               low 
               high or low 
               low 
               high 
               high 
             
             
               Impedance 
             
             
                 
             
           
        
       
     
   
   Pre-driver circuit output nodes  7 ,  8 , and  9  are connected to the driver circuit input nodes  7 ,  8 , and  9  shown in  FIG. 3 . The driver circuit  300  includes an isolation inverter circuit  310  configured with transistors Tp 11 , Tp 12 , Tn 11 , and Tn 12 . The isolation inverter circuit  310  prevents an external high voltage signal, at the driver output  320  from being transmitted to pre-driver circuit transistors used to configure the NAND, NOR, and inverter circuits shown in  FIG. 2 . The output stage  330  of the driver  300  includes a p-channel pull up transistor Tp 13  and n-channel pull down transistors Tn 13  and Tn 14 . Transistors Tn 13  and Tn 14  are stacked to avoid punch through when the external signal at the driver output  320  is a high voltage signal (5 volts). The gate of the transistor Tn 13  is connected to the driver power supply (Vdd=3.3 Volts). Transistor Tn 13  stays ‘On’, providing a voltage level at node  372  equal to (Vdd−Vtn) when output is high (Vdd) in active mode or output is at high voltage in the high impedance mode. 
   Node  372  is at low logic level or ground when the driver output  320  is at logic low level in active or high impedance mode. A two input NAND circuit  340  is controlled by the driver enable signal E ( 220 ) and the driver output signal reflected at node  372 . Depending on the active or high impedance mode of the driver  300 , the NAND circuit  340  generates the proper logic level at node  350  and at the gate terminal of transistor Tp 12 , which in turn controls the operation of the isolation inverter circuit  310  configured with Tp 11 , Tp 12 , Tn 11 , and Tn 12 . This will be explained in detail later. Transistor Tn 15  is stacked with transistor Tn 16  to avoid punch through of Tn 16  when the external signal at the driver output  320  is high voltage (5 Volts). 
   P-channel Transistor Tp 15  generates the bias for the floating Nwell in which p-channel transistors Tp 12  through Tp 16  are formed. 
   Operation of an Embodiment of the Off Chip Driver Circuit in the Active Mode 
   When the driver circuit  300  is in the active or enabled mode, driver enable input E ( 220 ) is high and node  9  will be at low level. Node  374 , the output of the circuit NAND  340  will be at a high level, transistors Tn 15  and Tn 16  will be ‘On’, and node  350  will be at low or ground level, thereby providing a low level at the gate of transistor Tp 12 . In the isolation circuit  310 , Tp 12  and Tn 11  will be ‘On’ and the isolation circuit will function like an inverter circuit. Nodes  7  and  8  will be at the same logic level as that of the driver data input  210 . Nodes  360  and  370  will be at the complement of the driver data input level  210 . So when the driver input  210  is high, node  360  will be low, pull up transistor Tp 13  will be ‘On’, node  370  will be low, transistor Tn 14  will be ‘Off’, and the driver output  320  will be high or at the same voltage level as power supply (Vdd). P-channel Transistor Tp 16  will be ‘Off’, preventing any leakage current from the driver output  320  to node  350  and to ground through Tn 15  and Tn 16 . 
   Operation of an Embodiment of the Off Chip Driver Circuit in High Impedance Mode 
   When the driver circuit  300  switches from active mode when its data input was at a low level to high impedance mode, the driver input enable  220  will be at low level, node  7  will be low, node  8  will be high, and node  9  will be high. Since the driver output  320  was at low level before switching to high impedance mode, node  372  will stay at a low level and node  374  will be high, Tn 15  and Tn 16  will be ‘On’, node  350  and the gate of transistor Tp 12  will be at a low level. The isolation circuit  310  again will function as an inverter circuit. Transistor Tn 12  will be completely ‘Off’, preventing any leakage current from Vdd to ground in the isolation inverter circuit. A low level at node  7  will provide a high level equal to the power supply (Vdd) at the gate of the p-channel pull up transistor Tp 13 , keeping it completely ‘Off’. A high level at node  8  will provide a low level at the gate of the pull down transistor Tn 14 , keeping it ‘Off’. 
   When the driver circuit  300  switches from active mode when its data input was at a high level to high impedance mode, the driver enable  220  will be low, node  7  will be low, node  8  will be high, and node  9  will be high. Node  374  will switch to low level, tuning off the transistor Tn 16 . Since node  350  was low before the driver  300  switched to high impedance mode, node  350  may charge to a small voltage level due to the gate to node  350  capacitance coupling of transistors Tn 15  and Tp 16 , a potential displacement effect across a capacitor. This voltage level at node  350  still will be low enough to keep transistor Tp 12  ‘On’ and the isolation circuit  310  functioning like an inverter. Node  7  will be low, transistor Tn 12  will be completely ‘Off’, there will be no leakage current from Vdd to ground in the isolation circuit  310 , and again node  360  or the gate of the pull up transistor Tp 13  will be biased to Vdd level keeping it completely ‘Off’. 
   The driver  300  is in the high impedance mode and its output is switched between ground and high voltage by the external signal. When the external signal is low, node  372  will be low, node  374  will be high, and transistors Tn 15  and Tn 16  will be ‘On’. The gate of Tp 12  will be at a low level, and the isolation circuit  310  will act like an inverter providing an up level equal to Vdd at the gate of transistor Tp 13  and keeping it completely ‘Off’. A high level at node  8  will provide a low level equal to ground at the gate of transistor Tn 14  and keeping it ‘Off’ as well. When the external signal is high (5 volts), node  372  will be high, node  9  will be high, node  374  will be low and transistor Tn 16  will be ‘Off’. A level of 5 volts at output will turn ‘On’ transistor Tp 16  with its gate voltage at Vdd and node  350  will be at 5 volts. Since node  7  was low, transistor Tp 11  will be ‘On’ and node  380  will be at Vdd or 3.3 Volts. A level of 5 volts at the driver output  320  will also turn ‘On’ the transistor Tp 14 , connected across the gate and the drain of pull up transistor Tp 13 , providing 5 volts at the gate of Tp 13  and keeping it ‘Off’. Voltage across all the p-channel transistor junctions, gate to source, gate to drain, gate to substrate, and gate to Nwell is at Vdd or below Vdd levels. The high voltage (5 volts) external signal at the output  320  of the driver circuit will not over stress any of the transistors. 
   When the driver  300  switches from high impedance mode to active mode, driver enable  220  switches from low to high level. Node  374  switches to high level, which turns on the transistor Tn 16 , bringing node  350  and the gate of the transistor Tp 12  to low level, conditioning the isolation circuit  310  into an inverter function before node  7  responds to the change in the driver&#39;s mode from high impedance to active. 
   Other Applications of an Embodiment of the Off Chip Driver Circuit 
   Embodiments of an off-chip driver circuit of the invention can be used to meet cold spare requirements. In cold spare mode, power supply applied to the off chip driver is zero volts, and the output is dotted with other active components which may be switches between ground and power supply (Vdd). This condition will not cause any over stress condition for this circuit and no damage to this off chip driver circuit. 
   In many applications, core circuits of ASICs are operated at still lower power supply voltage. For example, if the power supply voltage for the core circuit is 2.5 volts, the off chip driver circuit provides a 3.3 volt signal at its output pad, and it interfaces with another component which provides a 5 volt signal. In the pre-driver circuit  200  embodiment, inverters  230 ,  240  and  250  may be replaced with level converter circuits which will convert 2.5 volt signals to 3.3 volt signals at nodes  7 ,  8 , and  9 . The operation of the off chip driver circuit will be the same as described earlier. 
   In newer technologies power supply voltages are being reduced still further. Embodiments of an off chip driver circuit configuration as described herein are applicable to lower voltage levels. Persons of skill in the art will realize that the selection of transistor sizes will achieve certain performance requirements. 
   In the foregoing detailed description of embodiments of the invention, various features are grouped together in one or more embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description of embodiments of the invention, with each claim standing on its own as a separate embodiment. It is understood that the above description is intended to be illustrative, and not restrictive. It is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined in the appended claims. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” and “third,” etc., are used merely as labels, and are not intended to impose numerical requirements on their objects.