Abstract:
A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

Description:
[0001]    This application is a divisional to U.S. patent application Ser. No. 10/198,924, filed Jul. 19, 2002, which is a divisional to U.S. Pat. No. 6,448,129 B1, filed Jan. 24, 2000. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    This invention relates to semiconductor fabrication processing and, more particularly, to a method for forming active devices for semiconductor structures, such as field effect transistors used in random access memories.  
         BACKGROUND OF THE INVENTION  
         [0003]    Conventional fabrication techniques used to form the active transistors in memory devices have led to several undesirable results. It has become common practice to form active transistors with spacers on the vertical walls of the transistor gates by first forming disposable spacers and having the oxide spacers in place during conductive doping implantation steps to form the source/drain regions of the transistors. The disposable oxide spacers are eventually removed and replaced with final spacers that possess a desired spacer thickness.  
           [0004]    However, during the final spacer etch, when nitride is used as the spacer material, it is difficult to etch the nitride spacer with high selectivity to silicon and oxide and yet insure that all of the nitride is cleared from the source/drain regions of the active transistors. Because of this difficulty, a portion of the field oxide may be removed along with a portion of the silicon substrate that has been implanted with conductive dopants to form the transistor&#39;s source/drain regions. Etching into the field oxide can lead to transistor junction current leakage, while etching into the silicon source/drain region can lead to high source/drain resistance or even open circuits. If either of these conditions occur, they will adversely affect transistor operation.  
           [0005]    The present invention discloses a method to form active transistors in a semiconductor memory device that will protect the source/drain region of the active transistors during a spacer etch sequence so as to substantially reduce high source/drain resistance and leakage that may occur in the transistor junction.  
         SUMMARY OF THE INVENTION  
         [0006]    Exemplary implementations of the present invention comprise processes for forming active transistors for a semiconductor memory device.  
           [0007]    A first exemplary implementation of the present invention utilizes the process steps of forming transistor gates having generally vertical sidewalls in a memory array section and in periphery sections. Conductive dopants are implanted into exposed silicon defined as active area regions of the transistor gates. Disposable (temporary) spacers are formed on the generally vertical sidewalls of the transistor gates. Epitaxial silicon is grown over exposed silicon regions. After the epitaxial silicon is grown, conductive dopants are implanted into the exposed silicon regions to form source/drain regions of the active transistors. The temporary spacers are removed and permanent insulative spacers are formed on the generally vertical sidewalls of the transistor gates.  
           [0008]    A second exemplary implementation of the present invention utilizes the process steps listed above, but more specifically, the temporary spacers are formed of oxide and the permanent spacers are formed of nitride.  
           [0009]    A third exemplary implementation of the present invention utilizes the process steps of the first exemplary implementation except that the source/drain regions of the active transistor are formed prior to the formation of the epitaxial silicon.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1A is a cross-sectional view depicting a semiconductor substrate after the formation of active transistors in the array and periphery of a semiconductor memory device, including a Light Drain Doping (LDD) implant and a source/drain doping implant of both n-channel and p-channel transistors.  
         [0011]    [0011]FIG. 1B is a cross-sectional view of the structure of FIG. 1A taken after the removal of the temporary oxide spacers and the growth of epitaxial silicon or epitaxial silicon germanium at the exposed diffusion regions of the active transistors.  
         [0012]    [0012]FIG. 1C is a cross-sectional view of the structure of FIG. 1B taken after the formation of silicon nitride spacers along the substantially vertical walls of each transistor gate.  
         [0013]    [0013]FIG. 2A is a cross-sectional view depicting a semiconductor substrate after the formation of active transistors in the array and periphery of a semiconductor memory device, including a Light Drain Doping (LDD) implant of both n-channel and p-channel transistors.  
         [0014]    [0014]FIG. 2B is a cross-sectional view of the structure of FIG. 2A taken after the growth of epitaxial silicon or epitaxial silicon germanium at the exposed diffusion regions of the active transistors, followed by a source/drain doping implant of both n-channel and p-channel transistors.  
         [0015]    [0015]FIG. 2C is a cross-sectional view of the structure of FIG. 2B taken after the removal of temporary oxide spacers and the formation of permanent silicon nitride spacers along the substantially vertical walls of each transistor gate.  
         [0016]    [0016]FIG. 3A is a cross-sectional view depicting a semiconductor substrate after the formation of active transistors in the array and periphery of a semiconductor memory device, including a Light Drain Doping (LDD) implant of both n-channel and p-channel transistors.  
         [0017]    [0017]FIG. 3B is a cross-sectional view of the structure of FIG. 3A taken after the growth of epitaxial silicon or epitaxial silicon germanium at the exposed diffusion regions of the active transistors, followed by a source/drain doping implant of both n-channel and p-channel transistors.  
         [0018]    [0018]FIG. 3C is a cross-sectional view of the structure of FIG. 3B taken after the removal of temporary oxide spacers and the formation of permanent silicon nitride spacers along the substantially vertical walls of each transistor gate. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    Exemplary implementations of the present invention directed to processes for forming active transistors, in a semiconductor device, are depicted in FIGS. 1A-3C.  
         [0020]    A first exemplary implementation of the present invention is depicted in FIGS. 1A-1C. In the drawings of FIGS. 1A-1C, the semiconductor assembly represents a memory device partitioned into three main sections: memory array section  10 A, n-channel periphery section  10 B and p-channel periphery section  10 C. FIG. 1A depicts a semiconductor assembly  11 , such as a silicon wafer, that has been processed to a particular point.  
         [0021]    Referring to FIG. 1A, processing steps comprising transistor gate stack deposition, followed by patterning and etching of the gate stack are used to form transistor gates  13 A in memory array section  10 A, transistor gates  13 B in n-channel periphery section  10 B, and transistor gates  13 C in p-channel periphery section  10 C. Following the formation of the transistor gates, a lightly doped drain (LDD) phosphorus implant is performed to form lightly doped p-type regions  14 A,  14 B, and  14 C into silicon substrate  11 , except where field oxide  12  is present. Following the LDD phosphorus implant, a nitride layer is deposited over transistor gates  13 A,  13 B and  13 C, over exposed portions of silicon substrate  11  and over field oxide  12 . After the deposition of the nitride layer, oxide having a thickness that is greater than one half the width of the spacing between transistor gates  13 A (in the memory section  10 A), is deposited over the nitride layer. An oxide spacer etch is performed to form temporary oxide spacers  16 A,  16 B, and  16 C. Due to the thickness of the oxide layer and to the length of the oxide etch, oxide spacers  16 A seal off the underlying silicon between memory transistor gates  13 A. The oxide etch will also clear the nitride underlying the oxide and stop once silicon substrate  11  is reached. The oxide etch will also remove the thin nitride layer from the surface of the transistor gates  13 B. Since the transistor gate stack typically includes nitride as the top material, each transistor gate remains coated with nitride. The oxide etch also forms nitride liners  15 A,  15 B and  15 C, in memory section  10 A, periphery n-channel section  10 B, and in periphery p-channel section  10 C, respectively. Memory section  10 A and n-channel periphery section  10 B are masked off and a p-channel source/drain implant is performed to form p-channel source/drain regions  17 C. The mask over memory section  10 A and n-channel periphery section  10 B is stripped and p-channel periphery section  10 C is then masked off. Next, an n-channel source/drain implant is performed to form source/drain regions  17 B.  
         [0022]    Referring now to FIG. 1B, after the n-channel source/drain implant, the mask over p-channel periphery section  10 C is stripped and an oxide wet etch is performed to remove temporary oxide spacers  16 A,  16 B, and  16 C shown in FIG. 1A. Using the exposed portions of silicon substrate  11 , at source/drain regions  17 B and  17 C, an epitaxial silicon or silicon germanium material is grown to form epitaxial extension regions  18 B and  18 C. At epitaxial extension regions  18 B and  18 C, the epitaxial material will not only grow upward, but outward as well, resulting in a portion of epitaxial material to grow beyond the boundaries of the exposed silicon surface.  
         [0023]    Referring now to FIG. 1C, a nitride layer is deposited over the semiconductor assembly using conventional nitride deposition techniques. Next, a nitride spacer etch is performed to form permanent nitride spacers  19 A,  19 B and  19 C. During the nitride spacer etch, epitaxial material  18 B and  18 C is reduced according to the length of time the nitride etch is performed. During the nitride spacer etch, it is critical that the nitride is removed from the surface of the epitaxial material and yet sufficient nitride material remains to seal off the surface of silicon substrate  11  at the base of nitride spacers  19 A,  19 B and  19 C.  
         [0024]    For example, if the space between transistor gatesl 3 A, in memory array section  10   a  is 0.2 microns, a 0.12 microns thick temporary spacer ( 16 A) can be deposited to fill the space. A wet etch can be used to remove 0.04 microns of the temporary spacer so that the final spacer thickness of temporary spacers  16 B and  16 C is 0.08 microns. After the source/drain implant and a second wet etch is performed to remove the disposable oxide (spacers  16 A,  16 B and  16 C), an epitaxial material ( 18 B and  18 C) is grown to a thickness of 0.06 microns. Following epitaxial material growth, the nitride layer used to form nitride spacers  19 A,  19 B and  19 C is deposited to a thickness of 0.04 microns. Next, by using a nonselective etch, the epitaxial material and the nitride material are removed at the same rate. To ensure the 0.04 micron thick nitride overlying the epitaxial material is completely removed, a 50% over etch is used that will not only remove the 0.04 microns nitride layer, but also remove 0.02 microns of the epitaxial material. This etch will result in the formation of nitride spacer thickness of 0.04 microns and an epitaxial material thickness of 0.04 microns, which guarantees the that the silicon surface of source/drain diffusion regions  17 B and  17 C will not be etched.  
         [0025]    Thus, the epitaxial material protecting the source/drain diffusion regions  17 B and  17 C from the above mentioned nitride spacer etch helps to prevent high source/drain resistance that can occur when a portion of the silicon containing the source/drain region is removed. The presence of the epitaxial material also allows for the formation of shallow transistor junctions. Another function of the epitaxial material is to protect the field oxide  12  during the nitride spacer etch to prevent transistor junction leakage (current) that can result. The process flow of the present invention improves transistor isolation and provides a process flow that that is highly scalable for geometrically smaller devices. The semiconductor device is then completed in accordance with fabrication processes known to those skilled in the art.  
         [0026]    A second exemplary implementation of the present invention is depicted in FIGS. 2A-2C. In the drawings of FIGS. 2A-2C, the semiconductor assembly represents a memory device partitioned into three main sections: memory array section  20 A, n-channel periphery section  20 B and p-channel periphery section  20 C. As in the first exemplary implementation, FIG. 2A depicts a semiconductor assembly  21 , such as a silicon wafer, that has been processed to a particular point.  
         [0027]    Referring to FIG. 2A, processing steps described in the first exemplary implementation are used to form transistor gates  23 A in memory array section  20 A, transistor gates  23 B in n-channel periphery section  20 B, and transistor gates  23 C in p-channel periphery section  20 C. Following the formation of the transistor gates, a lightly doped drain (LDD) phosphorus implant is performed to form lightly doped p-type regions  24 A,  24 B, and  24 C into silicon substrate  11 , except where field oxide  22  is present. Following the LDD phosphorus implant, a nitride layer is deposited over transistor gates  23 A,  23 B and  23 C, over exposed portions of silicon substrate  21  and over field oxide  22 . After deposition of the nitride layer, oxide having a thickness that is greater than one half the width of the spacing between transistor gates  23 A (in the memory section  20 A), is deposited over the nitride layer. An oxide spacer etch is performed to form temporary oxide spacers  26 A,  26 B, and  26 C. Due to the thickness of the oxide layer and to the length of the oxide etch, oxide spacers  26 A seal off the underlying silicon between memory transistor gates  23 A. The oxide etch will also clear the nitride underlying the oxide and stop once silicon substrate  21  is reached. The oxide etch also forms nitride liners  25 A,  25 B and  25 C, in memory section  20 A, periphery n-channel section  20 B, and in periphery p-channel section  20 C.  
         [0028]    Referring now to FIG. 2B, using the exposed portions of silicon substrate  21 , an epitaxial silicon or silicon germanium material is grown to form epitaxial extension regions  27 B and  27 C. At epitaxial extension regions  27 B and  27 C, the epitaxial material will not only grow upward, but outward as well, resulting in a portion of epitaxial material to grow beyond the boundaries of the exposed silicon surface. Memory section  20 A and n-channel periphery section  20 B are masked off and a p-channel source/drain implant is performed to form p-channel source/drain regions  28 C, which include epitaxial extension regions  27 C. The mask over memory section  20 A and n-channel periphery section  20 B is stripped and p-channel periphery section  20 C is then masked off. Next, an n-channel source/drain implant is performed to form source/drain regions  28 B, which includes epitaxial extension regions  27 B. The presence of epitaxial extension regions  27 B and  27 C, become important as is discussed later in the process.  
         [0029]    Referring to FIG. 2C, after the n-channel source/drain implant, the mask over p-channel periphery section  20 C is stripped and an oxide wet etch is performed to remove temporary oxide spacers  26 A,  26 B, and  26 C, shown in FIG. 2B. Following the oxide etch, a nitride layer is deposited over the semiconductor assembly using conventional nitride deposition techniques and a nitride spacer etch is performed to form permanent nitride spacers  29 A,  29 B and  29 C. During the nitride spacer etch, epitaxial material  27 B and  27 C is reduced according to the length of time the nitride etch is performed. The ideal etch is timed so that the entire nitride material is removed from the surface of the epitaxial material and yet none of the silicon from the silicon surface (i.e., silicon substrate  21 ) of source/drain diffusion regions  28 B and  28 C is removed. The epitaxial material protecting the source/drain diffusion regions  28 B and  28 C from the above mentioned nitride spacer etch helps to prevent high source/drain resistance that can occur when a portion of the silicon containing the source/drain region is removed. The presence of the epitaxial material also allows for the formation of shallow transistor junctions. Another function of the epitaxial material is to protect the field oxide  22  during the nitride spacer etch to prevent transistor junction leakage (current) that can result. The process flow of the present invention improves transistor isolation and provides a process flow that that is highly scalable for geometrically smaller devices. The semiconductor device is then completed in accordance with fabrication processes known to those skilled in the art.  
         [0030]    A third exemplary implementation of the present invention is depicted in FIGS. 3A-3C. In the drawings of FIGS. 3A-3C, the semiconductor assembly represents a memory device partitioned into three main sections: memory array section  30 A, n-channel periphery section  30 B and p-channel periphery section  30 C. As in the second exemplary implementation, FIG. 3A depicts a semiconductor assembly  31 , such as a silicon wafer, that has been processed to a particular point. The processing steps of the second exemplary implementation are used to develop memory section  30 A, n-channel periphery section  30 B and p-channel periphery section  30 C. However, there is a variation in the development of these sections and in particular with memory section  30 A, which is described later. As shown in FIGS. 3A-3C, field oxide  32  is formed in silicon substrate  31 , transistor gates  33 A,  33 B and  33 C, vertically surrounded by oxide spacers  36 A,  36 B and  36 C, are formed on top of silicon substrate  31 , and diffusion regions, including lightly doped regions  34 A,  34 B and  34 C, epitaxial extension regions  37 A,  37 B and  37 C and source/drain regions  38 A,  38 B and  38 C, are formed as well.  
         [0031]    As mentioned above, a variation in the process changes the resulting semiconductor assembly. Instead of depositing oxide to the thickness described in the second exemplary implementation of the present invention, the oxide layer used to form oxide spacers  36 A,  36 B and  36 C is deposited to a thickness that is less than one half the width of the spacing between transistor gates  33 A (in the memory section  30 A). Once the oxide spacer etch is performed, oxide spacers  36 A will have a gap between them that will allow the formation of epitaxial region  37 A, shown in FIG. 3B.  
         [0032]    Referring to FIG. 3C, a nitride layer is deposited over the semiconductor assembly using conventional nitride deposition techniques. A nitride spacer etch is performed to form permanent nitride spacers  39 A,  39 B and  39 C, which are present on the vertical edges of epitaxial growth  38 A,  38 B and  38 C, as well as on the vertical walls of transistor gates  33 A,  33 B and  33 C. During the nitride spacer etch, epitaxial material  37 A,  37 B and  37 C is reduced according to the length of time the nitride etch is performed. The ideal etch is timed so that nitride material is removed from the surface of the entire epitaxial material and yet none of the silicon from the silicon surface (i.e., silicon substrate  31 ) of source/drain diffusion regions  38 A,  38 B and  38 C is removed. The semiconductor device is then completed in accordance with fabrication processes known to those skilled in the art.  
         [0033]    In the above exemplary implementations of the present invention, desired conditions to form an epitaxial silicon material comprise presenting a gas flow of 5 slm of hydrogen (H 2 ), 50 sccm of dichlorosilane (DCS) and 15 sccm of hydrochloric acid (HCI) to the surface of silicon assembly  11 , with the processing chamber temperature at 825° C. and the pressure set at 133 Pa. Desired conditions to form an epitaxial silicon germanium material comprise presenting a gas flow of 5 slm of H 2 , 100 sccm of DCS, 20 sccm of GeH 4  (10% H 2 ) and 20 sccm of HCl to the surface of silicon assembly  11 , with the processing chamber temperature at 750° C. and the pressure set at 400 Pa.  
         [0034]    It is to be understood that although the present invention has been described with reference to several preferred embodiments, various modifications, known to those skilled in the art, may be made to the process steps presented herein without departing from the invention as recited in the several claims appended hereto.