Abstract:
A differential amplifier avoids gain fluctuations due to process differences and changes in temperature and allows adjustability of the gain and associated frequency characteristics to desired gain values. The amplifier comprises a pair of load transistors coupled to a pair of differential input transistors. A pair of biased current source transistors assure a constant current through the differential transistors, and a pair of bias transistors supply a constant bias to the source of the load transistors. The gain is varied by varying the voltage supplied to the gates of the two load transistors. The voltage supplied to the load transistors is varied by varying the current supplied through a second pair of bias transistors. A number of current source transistors coupled in parallel vary the voltage through the second pair of bias transistors.

Description:
This application is a continuation of prior application Ser. No. 07/696,064, filed May 6, 1991, and now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates, in general, to adjustable gain differential amplifiers, and more specifically, to an adjustable gain differential amplifier which supplies high gain having high stability over a wide bandwidth. 
     Designers of differential amplifiers recognize that the gain of the amplifiers is not readily adjusted to a fixed value. To obtain a fixed gain and preferred frequency characteristics, the differential amplifier is commonly coupled to a feedback circuit, or to another device which supplies the desired gain. For example, U.S. Pat. No. 4,881,044 issued Nov. 14, 1991 to Kinoshita, et al., teaches a device having a current source supplying a current bias coupled in parallel with a load resistor of a differential amplifier. The gain is set by increasing the transconductance of the current source. 
     Even with the device taught in the &#39;044 patent, the gain is not readily altered, and cannot independently be set at a desired gain. Since each current source and load resistor posses different temperature characteristics (i.e. coefficients of expansion) and are process dependent, temperature changes and process changes can result in gain fluctuations. 
     SUMMARY OF THE INVENTION 
     A differential amplifier, according to the present invention, avoids gain fluctuations due to process differences and changes in temperature and allows adjustability of the gain and associated frequency characteristics to desired gain values. The amplifier comprises a pair of load transistors coupled to a pair of differential input transistors. A pair of biased current source transistors assure a constant current through the differential transistors, and a pair of bias transistors supply a constant bias to the source of the load transistors. The gain is varied by varying the voltage supplied to the gates of the two load transistors. The voltage supplied to the load transistors is varied by varying the current supplied through a second pair of bias transistors. A number of current source transistors coupled in parallel vary the voltage through the second pair of bias transistors. 
     The above and other objects, features, and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a diagram of a basic circuit according to the present invention. 
     FIG. 2 is a simplified diagram of the circuit of FIG. 1 showing the relationship between the variable resistance of the circuit and the current. 
     FIG. 3 is a simplified diagram of FIG. 1 showing the relationship between the input voltage and the current. 
     FIG. 4 is a diagram of the present invention in its preferred embodiment. 
     Table 1 shows the results of a simulation of the circuit of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     One having ordinary skill in the art of circuit design will recognize that the gain of a differential comparator or differential amplifier is given by g m  =i out  /Δv. Change in either i or v will result in a change in gain g m . The present invention maintains a constant i while varying the voltage v to change gain. 
     FIG. 1 shows the basic diagram of a gain control differential amplifier 10 according to the present invention. Differential amplifier 10 generally comprises differential transistors Q4A and Q4B (N channel), load transistors Q1A and Q1B (P channel), first bias transistors Q3A and Q3B (P channel), first current source transistors Q5A and Q5B (N channel), second bias transistors Q2A and Q2B, and second current source transistor Q6. 
     The gates of Q3A and Q3B are coupled to node D common to transistors Q1A and Q1B, and Q3A and Q3B are further coupled in parallel to a power source V DD . Q3A, Q1A, and the drain of Q4A are coupled to node B, whereas Q3B, Q1B, and the drain of Q4B are coupled to node C. A first output (OUT 1) is coupled to node B, and a second output (OUT 2) is coupled to node C. The gate of Q4A is coupled to a first input (IN1) and the gate of Q4B is coupled to a second input (IN2). 
     Transistors Q5A and Q5B operate as voltage controlled current sources and are common to node A. The sources of Q4A and Q4B are coupled to node A. Transistors Q5A and Q5B are controlled by bias V B  (a fixed bias) which maintains a constant current I N  through Q4A and Q4B. Transistors Q5A and Q5B are coupled to ground or V SS . 
     Second bias transistors Q2A and Q2B are coup;ed in series between V DD  and transistor Q6. Transistor Q6 is coupled to ground or V SS . Transistors Q1A and Q1B are coupled in parallel to second bias transistor Q2B at node E. 
     As shown in FIG. 1, a current I P  flows through transistors Q2A and Q2B to transistor Q6. Transistor Q6 is the current source of I P . The gate of transistor Q6 is also coupled to bias V B   
     Current I N  controlled by voltage controlled current source transistors Q5A and Q5B flows from V DD , is split between Q3A and Q3B, through Q4A and Q4B, and on through Q5A and Q5B. Because of bias V B , I N  remains constant. 
     Current I P  generates a voltage, or control voltage, in Q2A and Q2B which is supplied to the gates of Q1A and Q1B from node E. It should be recognized that due to the constant current I N  through Q3A and Q3B, the voltage at node D remains a constant as determined by V DD  less losses through Q3A and Q3B. Therefore, gain generated by amplifier 10 is realized by the voltage difference between node D and the gates of Q1A and Q1B, which gain is output at OUT1 and OUT2 respectively. 
     The gain characteristics and generation are further understood by the following discussion relating to FIGS. 2 and 3. 
     FIG. 2 shows a schematic of the gain generation. A transistor Q1 of FIG. 2 represents Q1A and/or Q1B of FIG. 1 and has a resistance of R. Q1 has a channel width W1 and a channel length L1. Transistor Q2 represents Q2A and Q2B of FIG. 1 and has a channe width W2 and channel length L2. Current source IS1 corresponds with transistor Q6 of FIG. 1. 
     In FIG. 2, Q1 functions in a linear region where resistance R can be represented by 
     
         R={1/(μ.sub.p C.sub.ox)}{L1/W1}{1/(V.sub.GS -V.sub.T)}  (1). 
    
     In Eq. 1, μ p  is the mobility of the P channel, C ox  is the gate capacity, V GS  is the voltage between the gate and source, and V T  is the threshold voltage. 
     The current I D  is represented by 
     
         I.sub.D ={μ.sub.p C.sub.ox /2}{W2/L2}{(V.sub.GS -V.sub.T).sup.2 }(2). 
    
     A variation of equation (2) is 
     
         {L2/W2}{2/μ.sub.p C.sub.ox }I.sub.D ={(V.sub.GS -V.sub.T).sup.2 {(3). 
    
     Deriving R 2  from Eq. 1 and 2 yields 
     
         R.sup.2 ={1/(μ.sub.p C.sub.ox)}.sup.2 (L1/W1).sup.2 (W2/L2){(μ.sub.p C.sub.ox /2)}(1/I.sub.D)                                  (4) 
    
     
         or 
    
     
         R.sup.2 ={1/(2μ.sub.p C.sub.ox)}(L1.sup.2 W2/L2W1.sup.2)(1/I.sub.D)(5). 
    
     The first clause in the brackets of Eq. 5 is affected by the manufacturing process of the circuit as well as changes in temperature. The second clause is fixed and unaffected, and the third clause is variable with respect to current flow. 
     FIG. 3 shows a common amplifier having a load R representing Q1 of FIG. 2, and a transistor Q n . R and Q n  are coupled in series between V CC  and ground. The voltage gain A v  of FIG. 3 can be represented as 
     
         A.sub.v =V.sub.0 /V.sub.IN =g.sub.m R                      (6) 
    
     where g m  is the transconductance of Q n  expressed as 
     
         g.sub.m ={2μ.sub.N C.sub.ox (W/L)I.sub.D }.sup.1/2      (7). 
    
     In Eq. 7, I D  is the drain current that flows to transistor Q n . Accordingly, 
     
         g.sub.m.sup.2 =2μ.sub.N C.sub.ox (W/L)I.sub.D           (8). 
    
     By applying equations 5, 6, and 8, gain can be defined as 
     
         A.sub.v.sup.2 =g.sub.m.sup.2 R.sup.2 =2μ.sub.N C.sub.ox (W/L)I.sub.N {1/(2μ.sub.p C.sub.ox)}{L1.sup.2 W2/L2W1.sup.2 }{1/I.sub.p }(9). 
    
     In Equ. 9, current I D  from current source IS1 in FIG. 2 is represented by  I  p, and I D  from the drain of Q2 of FIG. 3 is represented by  I  N. Simplifying Eq. 9 yields 
     
         A.sub.v.sup.2 ={(W/L)(L.sub.1.sup.2 /W.sub.1.sup.2)}(W2/L2)(μ.sub.N /μ.sub.p)(I.sub.N /I.sub.p)                            (10). 
    
     The first bracketed portion of Eq. 10 is not affected by temperature or processing. The second clause composed of the mobility quotient may appear to be dependent upon temperature and processing. In actuality, the mobility of N and P type transistors have a tendency to charge at a similar rate when exposed to changes in temperature and changes in the thickness of the gate oxidation membrane. Therefore, the second clause is also a stable value. The current ratio I N  /I p  then determines the gain. This ratio can be readily set to a preferred value from the transconductance ratio of each transistor, or from the size and shape of the transistor. Adjusting I N  /I p  adjusts the gain. 
     The analysis of FIG. 3 can be applied to FIG. 1. Since Q4A and Q4B correspond to Q n , Q1A and Q1B correspond to Q1 of FIG. 2, and Q2A and Q2B correspond to Q2 of FIG. 2, the gain of circuit 10 in FIG. 1 will closely approximate the gain of Eq. 10. 
     By adjusting the current ratio I N  /I p , or in other words, by keeping I N  a constant and adjusting I p , the gain can be adjusted to a desired level. Since the ratio I N  /I p  is the ratio of g m  in transistors Q5A, Q5B, and Q6, changes in gain can be facilitated by adjusting the size and shape ratio of transistor Q6 (assuming I N  remains constant). 
     FIG. 4 shows circuit 10 in its preferred embodiment. As can be seen, circuit 10 in FIG. 4 utilizes a plurality of transistors Q6, or Q61 through Q6n. The source of each Q61 through Q6N is coupled to ground, the gate to V B , and the drains are all common at node E. Interrupt components S1 through Sn are coupled between Q61-Q6n and node E. 
     Each of Q61-Q6n are constructed with a different size and shape ratio. This allows different amounts of current to flow through each of Q61-Q6n. 
     Interrupt components S1-Sn can be alternately turned on or off. In this manner, one of Q61-Q6n, or any plurality thereof, may be activated while the other Q61-Q6n are inactivated. As a result, the current I p  flows through only that/those selected Q61-Q6n. Since each of Q61-Q6n allows a different amount of current to flow, S1-Sn can be used to control I p , and therefore the total gain of circuit 10. 
     In FIG. 4, the drain of each Q61-Q6n is coupled to the respective interrupt component S1-Sn and then to node E. However, other ways of coupling S1-Sn to Q61-Q6n are contemplated by the present invention. 
     Since an additional current path is provided by Q3A and Q3B, and the drain current of Q4Q and Q4B can be supplied without changing the direct current of nodes B and C, a highly favorable common node rejection ratio is achieved. Node D will attain an average value of the voltage at nodes B and C as a result of the division of transistors Q3A and Q3B, and this relationship will be maintained despite a change in the input voltages IN1 and IN2. 
     The load of Q4A and Q4B represents a completely balanced circuit. Therefore, transistors Q1A and Q1B operate completely in the linear region, and direct current will not flow into Q1A and Q1B. The balanced circuit further provides very low levels of distortion and low offset voltages. 
     From Eq. 10 it is apparent that only I p  changes the gain in circuit 10. Further, since the expressions on the right side of Eq. 10 are configured in accordance with the ratio of identical parameters, the current ratio I N  /I p  of the transistors for the P channel and the N channel are configured to not affect the gain. With gain in circuit 10 not dependent upon temperature and processing, circuit 10 becomes extremely stable. 
     As an additional advantage, there is no fluctuation in the gain by utilizing a method to control the current of each component in the saturated region, such as the power source voltage. 
     As a result of the adjustable gain taught by the present invention, the optimum gain and frequency band characteristics of amplifier 10 can be obtained. 
     Table 1 shows the results of a simulation of circuit 10 of FIG. 4. The designations in the process column of Table 1 as relates to P channel and N channel are as follows 
     
         ______________________________________      P channel              N channel______________________________________TYP          typical   typicalBCS          maximum   maximumVOH          minimum   maximumVOL          maximum   minimumWCS          minimum   minimum______________________________________ 
    
     Specifically, the designation for TYP is for instances where the mobility of the P channel transistor and N channel transistor both have typical values; BCS is for instance where the mobility of the P and N channels both are at their maximum values; VOH is for instances where the mobility of the P channel is at its smallest and the N channel is at its largest, and so on. Further, V dd  is the power source voltage, V com  (V) is the in-phase input voltage, and V dif. (mV) is the differential input voltage. 
     Table 1 shows that amplifier 10 has a small margin of variation and is very stable in spite of changes in temperature or current voltage. Also shown in Table 1, last line, amplifier 10 has reached a state of saturation because of the significant amount of differential input voltage V dif, and the gain Gv has become very small. 
     As mentioned above, adjustable gain differential amplifier 10 provides stable adjustable gain over a broad band-width with very slight changes in gain due to dispersions in processing, temperature changes, changes in power source voltage, and so on. With the completely balanced circuit configuration, the common mode rejection ratio is enlarged and the signal distortion is reduced. With the offset voltage lowered, a very high capacity circuit is achieved. 
     Thus there has been provided, in accordance with the present invention, a gain control differential amplifier that fully satisfies the objects, aims, and advantages set forth above. While the invention has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations as fall within the spirit and broad scope of the appended claims. 
     
                       TABLE 1______________________________________           Vdd    Vcom  VdifProcess Temp.   (v)    (v)   (mv)  Bw(MHz) Gv(db)______________________________________TYP      25     5.0    4.0   4.0   22.5    12.0TYP      25     5.0    2.0   4.0   22.5    10.9BCS      0      5.5    2.0   4.0   31.6    10.3BCS      0      5.5    4.0   4.0   31.6    11.7VOH     125     5.0    2.0   4.0   18.0    12.5VOH     125     5.0    4.0   4.0   19.95   13.5VOL     125     5.0    2.0   4.0   19.95   9.98VOL     125     5.0    4.0   4.0   19.95   9.15WCS     125     4.5    4.0   4.0   12.59   12.2WCS     125     4.5    2.0   4.0   15.85   11.4WCS     125     4.5    4.0   0.01  12.59   12.2WCS     125     4.5    4.0   0.1   12.59   12.2WCS     125     4.5    4.0   1.0   12.59   12.2WCS     125     4.5    4.0   10.0  12.59   12.2WCS     125     4.5    4.0   100.0 22.50   4.93______________________________________