Abstract:
Embodiments of the present invention address deficiencies of the art in respect to memory management and provide a method, system and computer program product for dynamic optimization of DRAM controller page policy. In one embodiment of the invention, a memory module can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to the field of dynamic random access memory (DRAM) control and more particularly to DRAM paging. 
         [0003]    2. Description of the Related Art 
         [0004]    The memory controller provides the control logic to orchestrate the movement of data to and from dynamic random access memory (DRAM). In operation, a read command can be issued to a DRAM in order to move a fixed amount of data from the DRAM to a requesting device such as a processor cache in a central processing unit (CPU). In response, a sequence of control signals can move the requested data from the DRAM device to the memory controller and eventually to the requesting hardware. In the course of retrieving the requested data, a chip select signal can select an appropriate DRAM from amongst a set of DRAMs, the selected DRAM being referred to as a “rank”. 
         [0005]    Thereafter, a bank address signal can select the correct array in the selected DRAM, known as a “bank”, as required to satisfy the data request. Finally, an activate signal also referred to as a row access strobe or RAS signal can select a row in the appropriate bank. Notably, the activate signal connects the correct row of bits in the bank to sense amplifiers. The sense amplifiers, in turn, can latch an entire row of bits from the analog domain in the bank into the digital domain. This resulting row of bits is referred to as a “page” of physical memory. 
         [0006]    After a threshold number of DRAM cycles the memory controller can send “read”, “write”, “read with auto pre-charge” or “write with auto pre-charge” signals to the DRAM. These signals either read from a certain portion of the sense amplifiers or write to a certain portion of the sense amplifiers, usually filling a cache line worth of bytes. The auto pre-charge signal, if specified with the read or write command can cause the sense amplifiers to lose latched data after the read or the write operation completes. This has been referred to in the art as “closing” the page or “pre-charging” the bank. In the event that the auto pre-charge signal has not been implicitly requested at the time of the read or the write command, then the pre-charge signal must be explicitly sent by the memory controller to the DRAM devices. Otherwise, the page will remain “open” until the next refresh cycle which will cause the bank to become pre-charged. 
         [0007]    Refreshes are known to be relatively infrequent compared to the request rate, and therefore leaving the page open can be beneficial if there is reason to believe that the next access to the same bank will also be to the same page. Leaving the page open necessarily requires maintaining the charge on the sense amplifiers until explicitly removed by a pre-charge signal at a later time. A pre-charge signal eventually will be required if a different row in the DRAM array is to be read. In this circumstance, the content of the different row must be moved to the sense amplifiers, prior to which a pre-charge operation will be required. 
         [0008]    Micro-architecture designers at design time select one of two modes of computing for a memory controller in a microprocessor system depending upon the nature of the applications expected for operation in the system. Specifically, the modes include an open page mode and a closed page mode. In the open page mode, the memory controller leaves data brought into the sense amplifiers as is after an initial read or write operation. This allows a faster access to the same “page” of data, the next time a read or a write request to the same page is received in the memory controller. Referred to as a “page hit”, such reuse of data in a page is usually expected when there is only one thread of execution running in the CPU at a given time and the data accesses made by that thread are relatively sequential in nature. 
         [0009]    In the closed page mode, by comparison, the memory controller can close the page after handling a read or write command. Consequently, there can never be a “page miss” arising where a page in a bank is open, when a different page in the same bank is required to be opened. A page miss causes a longer delay than a permissible “page idle” condition where no page was open at the outset. In the page miss condition, the open page first must be closed, e.g. pre-charged. Only then can the correct page be opened or activated and a read or write can initiate. While a “page miss” can occur in a memory controller operating in an open page mode, in the closed page mode only “page idles” can occur. As such, memory latency can be better predicted. Accordingly, a closed page mode can be effective in supporting applications having a highly random access pattern with multiple threads of execution sharing a memory controller. 
         [0010]    Notwithstanding, processors exist that intend to support both applications with highly randomized access and applications with sequential access to data in memory. The anticipated applications can run under both types of thread scenarios, sometimes running only one thread of execution and sometimes running multiple threads from multiple users. In the past, memory controller designs allowed moving the memory controller from open page mode to closed page mode depending upon an observed memory access pattern. When detecting changes in access patterns, the memory controller can switch to a closed page mode to reduce page misses or to an open page mode to capitalize upon page hits. 
         [0011]    There are, however, applications that experience both access patterns during different program phases. In search applications, for instance, the same thread of execution jumps seemingly randomly across a large database based upon a search key, and upon locating the key, the execution changes in character to a sequential access pattern for a significant number of accesses. After some time, the execution of the application again changes to random access and so on. With many threads of such an application running, a properly configured memory controller must identify or designate the overall system access as sequential or random, even at a given instant in time. 
       BRIEF SUMMARY OF THE INVENTION 
       [0012]    Embodiments of the present invention address deficiencies of the art in respect to memory management and provide a novel and non-obvious method, system and computer program product for dynamic optimization of DRAM controller page policy. In one embodiment of the invention, a memory module can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. 
         [0013]    The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank. In this regard, the program code can perform a memory management method including identifying a locality tendency state for an existing memory page in a memory bank for a memory array, receiving a memory request for the memory bank, transitioning the locality tendency state responsive to determining either a page hit or a page miss for the memory request, storing the transitioned locality tendency state in association with the existing memory page in the memory array, and closing the memory page in response to a page miss, but leaving open the memory page in response to a page hit. 
         [0014]    The method additionally can include further receiving a memory request for a memory page in the memory array, loading the memory page and an associated locality tendency state for the memory page in the memory bank and accessing the memory page in the memory bank. In response to determining the associated locality tendency state to be a closed state, the memory page can be closed subsequent to accessing the memory page, but otherwise the memory page can be left open in the memory bank and the locality tendency state can be transitioned to a weakly opened state if another request for the memory page is pending, or if the memory page had immediately previously been opened and then closed in the memory bank. By comparison, in response to determining the locality tendency state to be a weakly opened state, the locality tendency state can be transitioned to an open state and leaving the existing memory page open in the memory bank. Finally, in response to determining the locality tendency state to be an open state, the locality tendency state can be transitioned to a strongly opened state and leaving the existing memory page open in the memory bank. 
         [0015]    Additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The aspects of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0016]    The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. The embodiments illustrated herein are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown, wherein: 
           [0017]      FIG. 1  is a schematic illustration of a memory management data processing system configured for dynamic optimization of DRAM controller page policy; and, 
           [0018]      FIG. 2  is a state diagram illustrating a process for dynamic optimization of DRAM controller page policy. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    Embodiments of the present invention provide a method, system and computer program product for dynamic optimization of DRAM controller page policy. In accordance with an embodiment of the present invention, a state can be assigned to each page opened in a bank managed by a memory controller in a memory module. The state can change for each page depending upon whether a page hit or page miss condition arises in the managing memory controller. Thereafter, the state can transition and the page can be closed or remain open as dictated by the state and rules for leaving open or closing pages having particular ones of the states. In this way, the controller page policy can be granularly tuned according to dynamic conditions sensed for the pages of the bank. 
         [0020]    In further illustration,  FIG. 1  is a schematic illustration of a memory management data processing system configured for dynamic optimization of DRAM controller page policy. The memory management data processing system can include a memory module  100  including one or more memories  110 , such as DRAMs. Each of the memories  110  can include a set of memory arrays  160  and corresponding sense amplifiers  170 . Address decoding logic  150  further can be provided to receive a row select instruction  150 A and a column select instruction  150 B to retrieve a page of data from a specified one of the memory arrays  160  into a corresponding one of sense amplifiers  170 . 
         [0021]    A memory controller  120  can be configured to manage the movement of data to and from the memory  110  of the memory module  100 . In this regard, data latched in the sense amplifiers  170  further can be shepherded into a data-in buffer  140 A by the memory controller  120  for processing a read operation from the memory module  100 , or into a data-out buffer  140 B by the memory controller  120  for processing a write operation in the memory module  100 . Importantly, whether or not a pre-charge signal is provided subsequent to latching a page in the sense amplifiers  170  and the choice of address hashing scheme utilized during read and write operations can depend on the page policy applied by the memory controller  120 . 
         [0022]    In this regard, open page policy manager  130  can be coupled to the memory controller  120  and can alternately provide for degrees of an open page mode in performing read operations, and write operations in the memory  110  depending upon a tendency of locality detected for a given page of memory. The tendency can be recorded in a locality tendency state  180 B applied to a page  180 A in a bank  180  latched by a corresponding one of the sense amplifiers  170 . Specifically, the locality tendency state state  180 B can range from an open state, a weakly open state, a strongly open state and a closed state, and the locality tendency state state  180 B can transition from state to state depending upon the occurrence of a page hit or a page miss. In addition, a last page record  180 C can be provided for the bank to indicate a last page opened and then closed in the bank  180 . Notably, when the a page  180 A is written back to a respective one of the memory arrays  160 , the locality tendency state state  180 B also can be written back in association with the page  180 A. Consequently, pages  190  in each of the memory arrays  160  can include not only individual pages  190 A of memory, but also corresponding locality tendency states  190 B. 
         [0023]    In operation, when a data request is received in the memory controller  120 , both the requested page  190 A and its corresponding locality tendency state  190 B can be latched into bank  180  as page  180 A and locality tendency state  180 B by a corresponding one of the sense amplifiers  170 . The locality tendency state  180 B can be updated depending upon whether a page hit or page miss has occurred. The locality tendency state  180 B can range from open, to strongly open, to weakly open, to closed. In the open state, if a page hit is generated on an open page  180 A, a strongly open state will result indicating a potential locality of access within the page  180 A that could be exploited by leaving the page  180 A in an open state. In contrast, in the open state if a page miss is generated, a weakly open state can result and the page  180 A can be closed. In the strongly open state, a page hit does not change the locality tendency state  180 B, though a page miss reduces the locality tendency state  180 B to an open state while the page  180 A is closed. 
         [0024]    By comparison, in a weakly open state—the default locality tendency state for a page  180 A—the page  180 A remains open until a page request is received for the bank  180 . Thereafter, a page hit results in a transition to the open state while a page miss results in a transition to the closed state and the closing of the page  180 A. Finally, in a closed state, a page  180 A will be closed immediately after the first access to the page  180 A. In the unlikely event of a page miss, the locality tendency state  180 B of the page  180 A will remain closed, while a page hit will result in a transition to the weakly open state only if additional requests to the request are detected by the open page policy manager  130  in a request queue, or if the page  180 A had previously been opened as indicated by the last page record  180 C for the bank  180 . 
         [0025]    In yet further illustration,  FIG. 2  is a state diagram illustrating a process for dynamic optimization of DRAM controller page policy. As shown in  FIG. 2 , an initial state of weakly opened  230  can be assigned to a page latched in a memory bank. A page hit promotes the latched page to a state of open  220 , while a page miss demotes the page into a state of closed  240 . In the former circumstance, the page can remain open while in the latter circumstance the page can be closed. When in the state of open  220 , a page hit results in a transition to the state of strongly opened  210 , while a page miss results in a demotion to a state of weakly opened  230 . In the former circumstance, the page can remain open, while in the latter circumstance the page can be closed. 
         [0026]    In the state of strongly opened  210 , a page hit results in no transition and a page miss results in a transition to the state of open  220 . In the former circumstance, the page can remain open, while in the latter circumstance the page can be closed. Finally, in the state of closed  240 , a page miss results in no state transition. However, a page hit unto itself also results in no state transition. Rather, a state transition to the state of weakly opened  230  only arises where a page hit occurs whilst an additional page request for the page exists in a request cache for the memory controller. Alternatively, a state transition to the state of weakly opened  230  can arise where a page hit occurs on a page that had immediately previously been opened. 
         [0027]    The persistence of an indication of locality tendency for each page provides the ability for the memory controller to granularly control the open page policy for memory paging. Whereas conventional memory controllers are configured statically as open page mode controllers or closed page mode controllers, the consideration of locality tendency and the support of the state machine transitioning to different states of locality tendency permit a finer management of open page mode memory control. 
         [0028]    Embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, and the like. Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. 
         [0029]    For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD. 
         [0030]    A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.