Abstract:
A method that allows effective removal of a silicon-containing antireflective coating (SiARC) layer in a block mask after defining an unblock area in a sidewall image transfer (SIT) patterning process without causing a height loss of the SIT spacers is provided. The method includes first modifying the SiARC layer with a dry etch utilizing an etching gas comprising a nitrogen gas followed by treating the modified SiARC layer with a wet chemical etch utilizing an aqueous solution including dilute hydrofluoric acid and citric acid.

Description:
BACKGROUND 
       [0001]    The present application relates to the fabrication of semiconductor structures and, more particularly to a method of removing a silicon-containing antireflective coating (SiARC) layer in a sidewall image transfer (SIT) patterning process without causing a height loss of spacers. 
         [0002]    Sidewall Image Transfer (SIT) is a process that doubles the density of a line pattern and is thereby very important to continued silicon technology scaling. The SIT process conventionally involves a conformal deposition of a spacer material layer over a previously patterned SIT mandrel followed by etching back the spacer material layer to form spacers on the sidewalls of the mandrels. The mandrels are then removed, leaving behind only the spacers. In certain applications, a block mask including a stack of an organic planarization layer (OPL), a silicon-containing antireflective coating (SiARC) layer, and a photoresist layer is applied over the SIT spacers. The block mask is then patterned to form a blocked area and an unblocked area. The unblock area corresponds to a region where the spacer defined pattern is transferred to an underlying metal nitride hard mask layer and eventually to the substrate. Once the block mask is patterned to expose spacers in the unblocked region, the patterned SiARC layer needs to be removed before patterning the metal nitride hard mask layer using the exposed spacers as an etch mask. 
         [0003]    However, etching the SiARC layer selective to the spacers exposed in the unblocked area can be a challenge. For example, silicon oxide formed by a low temperature in-situ radical assisted deposition (iRAD) is commonly employed as the spacer material. In such a situation, dry etches employing fluorine-based chemistry that are suitable for SiARC removal also etch the spacers because iRAD silicon oxide and SiARC have similar material properties and are etched at similar rates. This inadvertent etching of the oxide-based spacers can reduce the spacer heights. The relatively short spacers results in a poor metal hard mask etching profile, which leads to a non-uniformity during the trench and via pattering subsequently performed. As such, there remains a need to develop a novel approach that allows removal of the SiARC layer with enhanced etch selectivity relative to the silicon oxide-based spacers. 
       SUMMARY 
       [0004]    The present application provides a method that allows effective removal of a SiARC layer in a block mask after defining an unblock area in a SIT patterning process without causing a height loss of the SIT spacers. The method includes first modifying the SiARC layer with a dry etch utilizing an etching gas comprising a nitrogen gas followed by treating the modified SiARC layer with a wet chemical etch utilizing an aqueous solution including dilute hydrofluoric acid and citric acid. 
         [0005]    In one aspect of the present application, a method of forming a semiconductor structure is provided. In one embodiment, the method includes first forming a plurality of sidewall image transfer (SIT) spacers over a metal nitride hard mask layer located over at least one underlying material layer. Next, a patterned stack that includes a patterned silicon-containing antireflective coating (SiARC) layer overlying a patterned organic planarization layer (OPL) is formed over the SIT spacers and the metal nitride hard mask layer. The patterned stack exposes at least one portion of the plurality of SIT spacers. After exposing the patterned SiARC layer to an etching gas including a nitrogen gas to modify the patterned SiARC layer, the modified patterned SiARC layer is treated with an aqueous solution including dilute hydrofluoric acid to remove the modified patterned SiARC layer from a top surface of the patterned OPL. 
         [0006]    In another embodiment, the method includes first forming a plurality of sidewall image transfer (SIT) spacers over a metal nitride hard mask layer, wherein the metal nitride hard mask layer is located over a dielectric hard mask layer overlying at least one underlying material layer. A patterned stack that comprises a patterned silicon-containing antireflective coating (SiARC) layer overlying a patterned organic planarization layer (OPL) is formed over the SIT spacers and the metal nitride hard mask layer. The patterned stack exposes at least one portion of the plurality of SIT spacers. Next, the metal nitride hard mask layer is patterned employing the exposed portion of the plurality of SIT spacers as an etch mask. After exposing the patterned SiARC layer to an etching gas comprising a nitrogen gas to modify the patterned SiARC layer, the modified patterned SiARC layer is treated with an aqueous solution comprising dilute hydrofluoric acid to remove the modified patterned SiARC layer from a top surface of the patterned OPL. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a cross-sectional view of an exemplary semiconductor structure after forming a material stack including, from bottom to top, a dielectric cap layer, a dielectric material layer, a dielectric hard mask layer, a metal nitride hard mask layer, a mandrel material layer, a mandrel cap layer, a first organic planarization layer (OPL), a first silicon-containing antireflective (SiARC) layer and a first photoresist layer containing a first pattern therein over a substrate according to an embodiment of present application. 
           [0008]      FIG. 2  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 1  after transferring the first pattern into the first SiARC layer and the first OPL to provide a patterned first SiARC layer and a patterned first OPL. 
           [0009]      FIG. 3  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 2  after forming vertical stacks of mandrel caps and mandrel structures. 
           [0010]      FIG. 4  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 3  after conformally depositing a spacer material layer over the vertical stacks of mandrel caps and mandrel structures and the metal nitride hard mask layer. 
           [0011]      FIG. 5  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 4  after forming spacers. 
           [0012]      FIG. 6  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 5  after forming a second OPL over the spacers and the metal nitride hard mask layer, a second SiARC layer over the second OPL and a second photoresist layer containing a second pattern therein over the second SiARC. 
           [0013]      FIG. 7  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 6  after transferring the second pattern in the second photoresist layer into the second SiARC layer and the second OPL to provide a patterned second SiARC layer and a patterned second OPL. 
           [0014]      FIG. 8  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 7  after removing the patterned second SiARC layer utilizing a combination of a dry etch and a wet chemical etch. 
           [0015]      FIG. 9A  is a scanning electron microscope (SEM) image illustrating a dimension of a SIT spacer before applying the combination of the dry etch and the wet chemical etch to the patterned second SiARC layer. 
           [0016]      FIG. 9B  is a SEM image illustrating the dimension of the SIT spacer after applying the combination of the dry etch and the wet chemical etch to partially remove the patterned second SiARC layer. 
           [0017]      FIG. 9C  is a SEM image illustrating the dimension of the SIT spacer after completely removing the patterned second SiARC layer employing the combination of the dry etch and the wet chemical etch of the present application. 
           [0018]      FIG. 10  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 8  after etching the metal nitride hard mask layer using the spacers as an etch mask. 
           [0019]      FIG. 11A  is a SEM image illustrating a metal hard mask pattern obtained by using spacers of the present application as an etch mask, wherein the combination of the dry etch and the wet chemical etch of the present application employed to remove the SiARC material does not reduce the heights of the spacers. 
           [0020]      FIG. 11B  is a SEM image illustrating a metal hard mask pattern profile obtained by using spacers of the prior art as an etch mask, wherein the dry etch employed in the conventional process to remove the SiARC material reduces the heights of the spacers. 
           [0021]      FIG. 12  is a cross-sectional view of the exemplary semiconductor structure of  FIG. 10  after forming line trenches in the dielectric material layer. 
           [0022]      FIG. 13  is a cross-sectional view of a variation of the exemplary semiconductor structure of  FIG. 7  after pattering the metal nitride hard mask layer using the spacers as an etch mask. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals. 
         [0024]    In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application. 
         [0025]    Referring to  FIG. 1 , an exemplary semiconductor structure according to an embodiment of the present application includes a substrate  10  and a stack of material layers formed thereupon. In one embodiment, the substrate  10  may include a semiconductor substrate having semiconductor devices (not shown) therein. The semiconductor devices can include, for example, field effect transistors, junction transistors, diodes, resistors, capacitors, inductors, or any other semiconductor device known in the art. In another embodiment, the substrate  10  may include contact-level dielectric material layers (not shown) and/or interconnect level dielectric material layers (not shown) as well as embedded contact via structures (not shown) and/or embedded wiring level metal interconnect structures. Alternately, the topmost portion of the substrate  10  can include a semiconductor material such as single crystalline silicon. 
         [0026]    The material layer stack formed on the substrate  10  may include, for example, an optional dielectric cap layer  20 L, a dielectric material layer  30 L, a dielectric hard mask layer  40 L, a metal nitride hard mask layer  50 L, a mandrel material layer  60 L, an optional mandrel cap layer  62 L, a first organic planarizing layer (OPL)  72 L, and a first silicon-containing antireflective coating (ARC) layer. 
         [0027]    The optional dielectric cap layer  20 L, if present, can protect an underlying structure from impurities that may diffuse down from upper levels, and can function as a diffusion barrier layer that prevents vertical diffusion of metallic impurities, moisture, or other gaseous impurities. The optional dielectric cap layer  20 L may include, for example, silicon nitride, silicon oxynitride, silicon carbide, nitrogen and hydrogen doped silicon carbide (SiCNH), or a combination thereof. The optional dielectric cap layer  20 L may be formed, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the optional dielectric cap layer  20 L can be from 10 nm to 30 nm, although lesser and greater thicknesses can also be employed. 
         [0028]    The dielectric material layer  30 L may include a low-k dielectric material. The term “low-k” denotes a dielectric material having a dielectric constant that 4.0 or less. Exemplary low-k dielectric materials include, but are not limited to, silicon oxide, organosilicates, silsequioxanes, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and hydrogenated carbon doped silicon oxide (SiCOH). The dielectric material layer  30 L may be formed by CVD, plasma enhanced chemical vapor deposition (PECVD) or spin coating. The thickness of the dielectric material layer  30 L can be from 100 nm to 1,000 nm, although lesser and greater thicknesses can also be employed. 
         [0029]    The dielectric hard mask layer  40 L may include a dielectric material, which can be silicon oxide, silicon nitride, silicon oxynitride, organosilicate, or a combination thereof. The dielectric hard mask layer  40 L may be formed, for example, by PECVD, CVD or ALD. The thickness of the dielectric hard mask layer  40 L can be from 15 nm to 50 nm, although lesser and greater thicknesses can also be employed. 
         [0030]    The metal nitride hard mask layer  50 L may include TiN, TiON, TaN, WN, BN, a combination thereof, or a stack thereof. In one embodiment, the metal nitride hard mask layer  50 L is composed of TiN. The metal nitride hard mask layer  50 L may be formed, for example, by CVD, physical vapor deposition (PVD), ALD, or a combination thereof. The thickness of the metal nitride hard mask layer  50 L can be from 10 nm to 60 nm, although lesser and greater thicknesses can also be employed. 
         [0031]    The mandrel material layer  60 L may include any material that can be removed selective to the materials of the metal nitride hard mask layer  50 L and a spacer material layer subsequently formed. In one embodiment, the mandrel material layer  60  includes spin-on carbon (SOC), diamond-like carbon, polyarylene ether, or polyimide, amorphous carbon. The mandrel material layer  60 L may be deposited, for example, by CVD or spin coating. The thickness of the mandrel material layer  60 L can be from 30 nm to 300 nm, although lesser and greater thicknesses can also be employed. 
         [0032]    The optional mandrel cap layer  62 L may include a dielectric material such as, for example, silicon nitride, silicon oxide, or silicon oxynitride and may be formed by CVD or PVD. The thickness of the mandrel cap layer  62 L can be from 10 nm to 50 nm, although lesser and greater thicknesses can also be employed. 
         [0033]    The first OPL  72 L may include a self-planarizing organic planarization material, which can be a polymer layer with sufficiently low viscosity so that the top surface of the first OPL  72 L is a planar horizontal surface. The self-planarizing organic planarization material can be any material employed for an organic planarization layer in trilayer lithography methods known in the art, such as, for example, spin-on carbon (SOC), diamond-like carbon, polyarylene ether, or polyimide. The first OPL  72 L may be formed, for example, by spin coating. The thickness of the first OPL  72 L can be from 10 nm to 200 nm, although lesser and greater thicknesses can also be employed. 
         [0034]    The first SiARC layer  74 L may include a silicon-containing polymer. In one embodiment, the first SiARC layer  74 L comprises silicon at an atomic concentration from 1% to 50%. The first SiARC layer  74 L may be applied, for example, by spin coating. The thickness of the first SiARC layer  74 L can be from 10 nm to 150 nm, although lesser and greater thicknesses can also be employed. 
         [0035]    A first photoresist layer containing a first pattern (herein referred to as a patterned first photoresist layer  76 ) is formed on the top surface of the first SiARC layer  74 L. The first photoresist layer (not shown) may be formed, for example, by spin coating. The thickness of the first photoresist layer can be from 200 nm to 600 nm, although lesser and greater thicknesses can also be employed. The first photoresist layer can be a layer of a photoresist sensitive to deep-ultraviolet (DUV) radiation, extreme ultraviolet (EUV), or mid-ultraviolet (MUV) radiation as known in the art, or can be an e-beam resist that is sensitive to radiation of energetic electrons. 
         [0036]    The first photoresist layer is lithographically patterned to form the first pattern therein. The first pattern can be a line pattern including multiple parallel lines that define mandrel structures subsequently formed. In one embodiment, the multiple parallel lines can have the same width and the same pitch. The width of the multiple parallel lines can be from 10 nm to 50 nm, although lesser and greater widths can also be employed. The pitch of the multiple parallel lines is a lithographic pitch, i.e., a pitch that can be printed by a single lithographic exposure employing a commercially available lithography tool and photoresist. In one embodiment, the pitch of the multiple parallel lines can be from 50 nm to 200 nm, although lesser and greater pitches can also be employed. 
         [0037]    Referring to  FIG. 2 , the first pattern in the first photoresist layer is transferred through the first SiARC layer  74 L and the first OPL  72 L by a pattern transfer etch, which can be an anisotropic etch. In one embodiment, the pattern transfer etch can be a reactive ion etch (RIE) that removes the materials of the first SiARC layer  74 L and the first OPL  72 L selective to the material of the mandrel cap layer  62 L, if present, or the mandrel material layer  60 . The remaining portions of the first SiARC layer  74 L constitute the patterned first SiARC layer  74 . The remaining portions of the first OPL  72 L constitute the patterned first OPL layer  72 . After transferring the first pattern into the first SiARC layer  74 L and the first OPL  72 L, the patterned first photoresist layer  76  may be removed by a conventional strip process such as, for example, ashing. 
         [0038]    Referring to  FIG. 3 , mandrel structures  60  are formed by employed the patterned first SiARC layer  74  and the patterned first OPL  72  as an etch mask. In some embodiments of the present application, each mandrel structure  60  may have a mandrel cap  62  located atop the mandrel structure  60  if the mandrel cap layer  62 L is present in the structure. 
         [0039]    The mandrel structures  60  and the mandrel cap  62 , if present, may be formed by removing portions of the mandrel material layer  60 L and the mandrel cap layer  62 L, if present, that are not covered by the patterned first SiARC layer  74  and the patterned first OPL  72  by at least one etch, which can be a dry etch or a wet chemical etch. In one embodiment, RIE may be employed to remove the exposed portions of the mandrel cap layer  62 L, if present, or the mandrel material layer  60 L selective to the metal nitride hard mask layer  50 L. Remaining portions of the mandrel material layer  60 L constitute the mandrel structures  60 . Remaining portions of the mandrel cap layer  62 L constitute the mandrel caps  62 . After forming the mandrel structures  60 , the patterned first SiARC layer  74  and the patterned first OPL  72  may be removed by a dry etch or a wet chemical etch. 
         [0040]    Referring to  FIG. 4 , a spacer material layer  80 L is conformally deposited over vertical stacks of mandrel structures  60  and the mandrel cap  62 , if present, and exposed surfaces of the metal nitride hard mask layer  50 L. The spacer material layer  80 L may include a iRAD material such as, for example a iRAD silicon oxide and may be formed by a conformal deposition process, such as, for example, ALD or CVD. The thickness of the spacer material layer  80 L may vary depending upon the desired width of final structures to be formed, and can be from 5 nm to 50 nm, although lesser and greater thicknesses can also be employed. 
         [0041]    Referring to  FIG. 5 , horizontal portions of the spacer material layer  80 L are removed to provide spacers  80  (also referred to as SIT spacers). Each spacer  80  comprises a remaining portion of the spacer material layer  80 L on each sidewall of vertical stacks of mandrel structures  60  and the mandrel cap  62 , if present. The removal of the horizontal portions of the spacer material layer  80 L can be achieved utilizing an anisotropic dry etch, such as, for example, RIE. 
         [0042]    After removal of the horizontal portions of the spacer material layer  80 L, the topmost surface of each vertical stack of mandrel structure  60  and the mandrel cap  62 , if present is exposed and is coplanar with a topmost surface of each spacer  80 . A width of each spacer  80 , as measured at its base, can be from 5 nm to 50 nm, although lesser and greater thicknesses can also be employed. 
         [0043]    Referring to  FIG. 5 , the mandrel structures  60  and the mandrel cap  62  are removed from the structure, thus leaving spacers  80  protruding from the top surface of the metal nitride hard mask layer  50 L. The mandrel structures  60  and the mandrel caps  62  may be removed by at least one etch, which can be a dry etch or a wet chemical wet, selective to the materials of the spacers  80  and the metal nitride hard mask layer  50 L. The at least one etching process can be an anisotropic or an isotropic etch. 
         [0044]    Referring to  FIG. 6 , a block mask including, from bottom to top, a second OPL  92 L, a second SiARC layer  94 L and a second photoresist layer (not shown) is applied over the metal nitride hard mask layer  50 L and the SIT spacers  80  by spin coating. The second photoresist layer is lithographically patterned to form a second pattern therein. The remaining portions of the second photoresist layer constitute the patterned second photoresist layer. The second pattern includes at least one opening. The at least one opening defines an unblocked area. The spacers  80  underlying the unblocked area are employed as an etch mask for the subsequent etching of the metal nitride hard mask layer  50 L. The area that is covered by the remaining portions of the second photoresist layer (herein referred to as the patterned second photoresist layer  96 ) after lithographic exposure and development is referred to as the blocked area. 
         [0045]    Referring to  FIG. 7 , the second pattern is transferred into the second SiARC layer  94 L and the OPL  92 L. The second SiARC layer  94 L and the OPL  92 L may be etched by an anisotropic etch that employs the patterned second photoresist layer  96  as an etch mask. The anisotropic etch can be a dry etch such as, for example, RIE. Portions of the second SiARC layer  94 L and the underlying OPL  92 L that are exposed in the unblocked area are thus removed selective to the materials of the spacers  80  and the metal nitride hard mask layer  50 L. The remaining portions of the second SiARC layer  94 L constitute the patterned second SiARC layer  94 . The remaining portions of the second OPL  92 L constitute the patterned second OPL  92 . If not consumed during the etching of the second SiARC layer  94 L and the OPL  92 L, after transferring the second pattern into the second SiARC layer  94 L and the OPL  92 L, the patterned second photoresist layer  96  may be removed by ashing. 
         [0046]    Referring to  FIG. 8 , the patterned second SiARC layer  94  is removed employing a combination of a dry etch and a wet chemical etch. First, a dry etch is performed to modify the patterned second SiARC layer  94  by exposing the patterned second SiARC layer  94  to an etching gas containing a nitrogen gas or a mixture of nitrogen and hydrogen gases. The etching gas incorporates nitrogen into the patterned second SiARC layer  94  to deplete carbon therein. Because the etching gas employed in the present application does not include a fluorine-containing gas, such as, for example, a fluorocarbon gas that is used in the conventional SiARC removal process, the nitrogen-based dry etch chemistry employed in the present application does not etch the patterned second SiARC layer  94  and spacers  80  as in the case of the conventional SiARC removal process; rather it only modifies the SiARC material so the patterned second SiARC layer  94  can be removed with a wet chemistry subsequently performed. Such wet chemistry removes the patterned second SiARC layer  94  selective to the spacers  80 . 
         [0047]    Next, the modified patterned second SiARC layer  94  is removed selective to the metal nitride hard mask layer  50 L, the patterned second OPL  92  and the spacers  80  by a wet chemical etch employing an aqueous solution of dilute hydrofluoric (HF) acid and citric acid. In some embodiments of the present application, ultra-dilute HF acid is used. As used herein, the term “ultra-dilute” means 1 part hydrofluoric acid mixed with at least 100 parts of deionized water. The ratio between the HF acid and the deionized water can be in the range of 1:50 to 1:10000. The citric acid concentration can be from 0.1 wt % to 2 wt %. In one embodiment, the ultra dilute HF acid is about one part of HF to 1300 parts water, and the aqueous solution includes 1 wt % of citric acid. The temperature of the aqueous solution during the wet chemical etch can be from 20° C. to 70° C. The combined dry and wet etch chemistries of the present application do not attack the spacers  80  exposed in the unblocked area, thus preventing the dimension change of the spacers encountered in the conventional SiARC removal process. 
         [0048]      FIG. 9A  is a SEM image showing a dimension of a spacer  80  before removing the patterned second SiARC layer  94 .  FIG. 9B  is a SEM image showing the dimension of the spacer  80  after partial removal of the patterned second SiARC layer  94  employing the combination of the dry etch and the wet chemical etch of the present application.  FIG. 9C  is a SEM image showing the dimension of the spacer  80  after complete removal of the patterned second SiARC layer  94  employing the combination of the dry etch and the wet chemical etch of the present application. As shown in  FIGS. 9A, 9B and 9C , the dimensions of the spacer  80  remain the same before, and after, the SiARC removal process. Thus, the combined etch chemistries of the present application can remove the SiARC material without causing any spacer oxide loss. 
         [0049]    Referring to  FIG. 10 , the metal nitride hard mask layer  50 L is etched by an anisotropic etch using the spacers  80  exposed in the unblocked area as an etch mask. The anisotropic etch can be a dry etch or a wet chemical etch that removes the material of the metal nitride hard mask layer  50 L selective to the dielectric hard mask layer  40 L. In one embodiment, a chlorine-containing gas can be employed to etch the metal nitride hard mask layer  50 L. The remaining portions of the metal nitride hard mask layer  50 L constitute the patterned metal nitride hard mask layer  50 . After transferring the spacer pattern into the metal nitride hard mask layer  50 L, the patterned OPL  92  and the spacers  80  may be removed, for example, by a dry etch or a wet chemical etch. 
         [0050]    Referring to  FIGS. 11A and 11B , SEM images are provided to compare the metal hard mask pattern profile ( FIG. 11A ) of the present application in which the SiARC material is removed by a combination of a dry etch and a wet chemical etch to that of the metal hard mask pattern profile ( FIG. 11B ) of the conventional SIT patterning process in which the SiARC material is removed by a fluorine-based dry etch. The SEM image of  FIG. 11A  shows that the pattern that is formed in the metal nitride hard mask layer  50 L has the desired profile due to the better preservation of the spacers  80  in the unblocked area. In comparison and as shown in  FIG. 11B , the conventional fluorine-based dry etch simultaneously etch the spacers exposed in the unblocked areas when removing the SiARC material, thus the heights of the spacers exposed in the unblocked areas are reduced. This leads to the overetch of the metal nitride hard mask layer. As a result, a poor pattern profile is obtained in the metal nitride hard mask layer. 
         [0051]    Referring to  FIG. 12 , the pattern in the metal nitride hard mask layer  50 L is transferred into the underlying dielectric layers, i.e., the dielectric hard mask layer  40 L and the dielectric material layer  30 L by at least one etch that employs the patterned metal nitride hard mask layer  50  as an etch mask. The remaining portions of the dielectric hard mask layer  40 L constitute the patterned dielectric hard mask layer  40 . The remaining portions of the dielectric material layer  30 L constitute the patterned dielectric material layer  30 . After transferring the pattern into the underlying dielectric layers, the patterned metal nitride hard mask layer  50  and the patterned dielectric hard mask layer  40  may be removed by a recess etch or a planarization process such as, for example, by chemical mechanical polishing (CMP). Line trenches  98  are thus formed in the dielectric material layer  30 L. 
         [0052]    Subsequently, a conductive material layer (not shown) may be deposited in the line trenches  98  and planarized to provide interconnect structures (not shown). 
         [0053]    Referring to  FIG. 13 , a variation of the exemplary semiconductor structure can be derived from the exemplary semiconductor structure of  FIG. 7  by patterning the metal nitride hard mask layer  50 L prior to the removal of the patterned second SiARC layer  94  by performing the processing steps of  FIG. 10 . The patterning of the metal nitride hard mask layer  50 L exposes portions of the dielectric material hard mask layer  40 L. Subsequently, processing steps of  FIGS. 8 and 12  can be performed to remove the patterned second SiARC layer  94  and to etch the dielectric material hard mask layer  40 L and the dielectric material layer  30 L, thus forming line trenches  98  in the dielectric material layer  30 L. The combined dry and wet etch chemistries of the present application can remove the SiARC material without attacking the exposed portions of the dielectric hard mask layer  40 L. 
         [0054]    It should be noted that although the above description and drawings illustrate employing the combination of a dry etch and a wet chemical etch to remove the SiARC material in a SIT process, such combined etching approach can also be used in a SiARC rework process. 
         [0055]    While the present application has been particularly shown and described with respect to various embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.