Abstract:
In a dynamic disc memory system, servo signal tracks and data tracks are adjacent. The servo track includes a signal having a predetermined frequency. With the system and method of this disclosure, the data recorded on the data track is translated to have a frequency null at the frequency of the servo signal track by translating apparatus to eliminate cross-talk at the servo frequency.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to electrical communications and more particularly to error prevention systems. In the preferred application, this invention relates to dynamic information storage and retrieval and more particularly to error prevention in connection with automatic control of track centering of a magnetic recording head. 
     2. Description of the Prior Art 
     In the field of magnetic recording, in the past where there have been separate magnetic recording heads for data and track sensing for positioning of a magnetic recording head, it has been necessary to provide protection against magnetic and electrical cross-talk between channels. In order to prevent such cross-talk, wires have been shielded and heads have been separated by magnetic shielding material. In fact, in many cases the head used to control tracking of the servo mechanism is placed far away from the head which operates to read and/or record data, a situation which introduces positioning errors due to intermittent mechanical factors such as thermal expansion and contraction or vibration of the two heads. In some cases, the track following head must be located adjacent a separate disk, which increases the probability of error even more. 
     Previous work of P. A. Franaszek, who is a coinventor herein, is described in U.S. Pat. No. 3,840,854. The patent teaches a technique for modifying the D.C. component of a binary code by introduction of ones into strings of zeroes and introduction of zeroes into strings of ones so that there is substantial elimination of the D.C. component of a signal. 
     A publication of Furtney et al entitled &#34;DC Balanced Encoded Recording,&#34; IBM Technical Disclosure Bulletin, Vol. 18, No. 1, June 1975, pp 53-54 shows a code selection circuit which is used to provide a D.C. balance of a recording signal similar to that in U.S. Pat. No. 3,840,854. 
     J. H. Bleher wrote a publication entitled &#34;Data Code Servo,&#34; IBM Technical Disclosure Bulletin, Vol. 18, No. 6, Nov. 1975, p. 1917 which shows adjacent track heads on each side of a data recording head, with alternating codes upon adjacent tracks so that with the two servo heads straddling adjacent tracks, the low pass result of the signals received is used to control a servo. 
     In a publication by L. F. Shew entitled &#34;Track Servo System,&#34; IBM Technical Disclosure Bulletin, Vol. 16, No. 7, Dec. 1973, pp 2225- 6 there is described the need to place the servo track immediately next to the data track in order to overcome errors caused by differences in temperature which lead to large positioning errors. The publication proposes that the data on the track or an adjacent track plus very small sample servo sectors should be used to control head position. This takes a substantial fraction of the data track and it requires a rather sophisticated servo control system responding to intermittent signals which can be overcome by sharing a single servo track with a number of other tracks. 
     Accordingly, it is desirable to reduce the chance of cross-talk between the servo track and the data track, respective heads and/or respective leads. 
     Another object of this invention is to provide means for generating data signals having a spectral null at the frequency of the servo signal track. 
     SUMMARY OF THE INVENTION 
     A digital device transmitting a stream of binary information often causes electromagnetic interference (noise) in adjacent sensitive channels. For example, the process of writing a magnetic recording medium often interferes with the servo channel. This interference can be minimized if the servo channel can be made to operate in a narrow frequency band centered around twice the data clock frequency, since the data signal has no energy at that frequency. Unfortunately, all the natural spectral nulls occur at even harmonics of the data clock frequency, and there are often dominant engineering reasons for making the data clock frequency the highest in the system. This invention deals with means for restricting the data code so that a spectral energy null occurs at a frequency less than the data clock frequency. 
     The solution to the problem of cross-talk in accordance with this invention involves providing a data code for the system which has a frequency null at the servo frequency selected for the servo code. Referring to FIG. 3 showing data code amplitude vs. frequency, if the data clock frequency is F max  and the servo frequency is F max  /N (where N is an integer), with a data code null (dotted lines) at that frequency, then there will be no harmful cross-talk between the servo and the data lines of a head. 
     Definitions: 
     let a word be defined as a string of N binary bits. For example, 01011 is a word with N=5. Let the parity P of a word be defined as the sum, modulo 2, of the bits in the word taken separately. For example, 01011 has parity 1. Let NRZI be the method of encoding commonly used in magnetic recording, such that each bit in the data stream controls the presence (1) or absence (0) of a polarity reversal of write current at the beginning of the corresponding data clock cycle. Let the run length K be the maximum number of successive zeroes which may appear in the data stream. Let the Fourier component s r  be a number proportional to integral ∫I(t) sine (ω r  t+ φ) dt where I(t) is a current which is zero except during a single word, during which it represents the NRZI encoding of the word with the first transition being positive. Let r be the ratio of the frequency of the all ones waveform to f.sub. r = ω r  /2π . For example, f 2  is at 1/2 the all ones frequency and 1/4 of the clock frequency. Let the Fourier component c r  be a number proportional to the integral ∫I(t) cosine (ω r  t + φ) dt. Let S be the running sum of the { s r  } and C be the running sum of the { c r  }. 
     In the above-mentioned Franaszek patent, a method is disclosed for forcing a binary waveform to have zero DC component by keeping the running sum of the contributions of each clock cycle and then choosing the next data word from a list, any member of which will cause the sum not to grow larger in the same polarity. The methods employed here are based on the bounding of the running sums of the Fourier components at the frequency to be suppressed. For example, there is a code of word length N= 10 and run length 6 such that 256 choices (8 bits) exist for any polarities of s 2  and c 2  which are desired. Thus, this code has an efficiency of 80%. 
     The method employed in preparing a lookup table in accordance with this invention is as follows: A list of all possible words of length N which meet the primary criteria (such as run length) is drawn up. Each word is examined, and a triple (s r  , c r , p) is computed, as defined above. Then the list is divided into four sublists labeled ++; +-; -+; and --. A word is placed in the ++ sublist, for example, if it has a non-negative value of s r  and of c r . Words having zero value for s r  or c r  appear in several sublists. The shortest sublist determines the maximum number of data words which may be encoded without ambiguity such that the sums s r  and c r  remain bounded. When a word is to be encoded, the current waveform polarity (which is the same as the running sum of p modulo 2) and the running sums s r  and c r  are examined. When the polarity is positive, the sublist corresponding to the (sign of s r ), (sign of c r ) is used for encoding, if negative the sublist with both signs negated is used. If the code word is the number M, the Mth entry is used. This is a read-only-store (ROS) with a lookup table-type of encoding. A similar table is used for decoding. In general, the number M will require less than N bits for binary representation, so the efficiency of this encoding is less than one. However, the energy in the waveform at frequency f r  is zero, and the energy indicated by a detector of finite bandwidth and sampling time is also bounded. 
     In addition to this general case, there are several special cases of interest: a) Only code words with s r  = 0,  c r  = 0 are used. Then no running sums need be kept. However, the efficiency is lower, usually about 50%. b) An external clock is available to control a synchronous detector. Then only one of the Fourier components need be bounded (the one in phase with the servo signal), and the number of sublists is reduced to two. c) Only code words with zero c are used. Again the number of sublists is two. 
     In all the above, the choice of phase angle φ was arbitrary, so an optimum, constant value is assumed to be chosen. Also, it is not possible, in general, to find a scale factor which will make the C i  terms integers. Some will involve irrational numbers. However, it is possible to make a rational approximation to each such number which is accurate to within any previously specified tolerance. 
     Mathematical Basis for the Invention 
     The energy in a waveform at any frequency can be determined by the Fourier transform of the waveform (see, for example, Skilling, &#34;Electrical Engineering Circuits,&#34; John Wiley and Sons, New York 1957): ##EQU1## where g(ω)= the amplitude of the spectral component at frequency ω 
     e j .sup.ωt = cos ωt+ j sin ωt, the two Fourier components 
      j= √-1 
      f(t)= the waveform as a function of time, which begins at t = 0, i.e., f = 0 for t&lt;0 
     ω = the frequency (2π f) of interest 
     φ = an arbitrary phase angle chosen for convenience 
     The waveform of interest to this invention is a binary synchronous one, such as is used for the write current in digital recording systems and for the transmission voltage in digital communications circuits. Such a waveform has a constant value during any given clock period τ. It may switch between two permissible values at the end of a clock period. Thus the previous integral may be replaced by a summation: ##EQU2## when α n  is the value of the waveform, either +1 or -1, during the nth clock period. This integral can be solved: ##EQU3## where K is a constant and ψ is an arbitrary phase angle. 
     The problem is that the α n  are outside of the system&#39;s control, and are determined by the data pattern. With unfavorable circumstances, α will be positive when cos (nω τ+ψ ) is positive and negative when it is negative. Even if the α n  are random, the sum is subject to arbitrarily large fluctuations. The only way to control and eliminate this frequency is to place a firm bound on the partial sum as it accumulates. Actually, there are two independent sums to control, one involving the cosine terms and one involving the sine terms. The total power is the sum of the power represented by the cosine terms (real part) and the sine terms (imaginary part). 
     This invention employs four possible encodings for each word, depending on the current value of the sine and cosine partial sums. When the frequency to be nulled is an integral sub-multiple of the clock frequency, then the sine and cosine terms can take on only a limited number of values. For example, when τ, the clock period, is one-fourth of the period of the frequency to be nulled, then there are only four possible values for cos (nωτ+ψ). If ψ is chosen to be zero, then the values are 1, 0, -1, and 0. If ψ is chosen to be 45 degrees, then the values (normalized by a constant multiplier) are 1, -1, -1, and 1. Other values of ψ could be used, but those are the most often useful. Having τ equal to one-fourth of the clock period is, in fact, the case for the frequency f 2  described below as the preferred embodiment. ψ = 0 is the optimal choice when N/2 is even and ψ =  450 degrees is optimal for N/2 odd. 
     For larger sub-multiples, such as τ equal to one-eighth of a clock period, some of the values for cos (nωτ+ψ) must be irrational. However, these irrational values can be approximated by rational numbers to an arbitrary degree. The approximate values 7, 5, 0, -5, -7, -5, 0, 5 are accurate to better than 1%. The approximate values 17, 12, 0, -12, -17, -12, 0, 12 are accurate to nearly one part in a thousand. The price of approximation is slightly larger storage registers for the partial sums, but this remains a very small part of the cost of implementing this invention. 
     In accordance with this invention, a code translating system and method are provided. Coded data is translated to provide a spectral null at a predetermined frequency. An addressable translating apparatus provides a coded output signal in response to a coded input signal. A monitoring apparatus monitors the output of the translating apparatus with respect to predetermined limit conditions for providing code selection data as a function of said output signals. The monitoring apparatus has an output connected to send the code selection data to modify the input signal to the translating means to select a desired code so a spectral null is achieved at the predetermined frequency. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a code converting system for generating data codes with a spectral null at the servo track frequency of a magnetic recording system. 
     FIG. 2 shows the sine-cosine (cos) logic system of FIG. 1 in greater detail. 
     FIG. 3 shows the spectral amplitude of a data code as a function of frequency, with a spectral null shown at an integral fraction of the maximum frequency of the code. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows the electrical schematic diagram of a particular way of converting a standard binary six-bit code into a code having a null at one-half the all ones frequency (F max  /2 in FIG. 3). The standard binary code is supplied on cable 10 to register 11. Register 11 holds the signals on line 10 until gate 14 is operated to supply an address signal to the Read Only Store (ROS) Address Register (AR) 15 for ROS 16. The ROS 16 supplies a decoded output at the ROS Data Register (DR) 17, which is employed to provide the desired output signal to be supplied via conventional write-drive electronics 18 to magnetic recording write head 19 on lines b0-b7. The system must monitor the signals upon lines b0-b7 to assure that there is a null in the data on lines b0-b7 at the particular frequency Fmax/N for which the system is designed. It should be noted that the data on lines b0-b7 is recorded in serial fashion upon a magnetic recording medium 20 by head 19. The intent is that the serial data from head 19 will have a null at the frequency F max  /N being read from medium 20 by servo head 21 connected to the servo control unit 22 of the magnetic recording system. Sine cos logic 30 in FIG. 2 monitors data on lines b0-b7.  The data monitored on lines b2 and b6 is added in adder 23 which drives 2&#39;s complement unit 24 containing inverters 25 which produce the complement of the output of adder 23 and adder 26 which increases that value by +1. The output of adder 26 is passed to S adder 28 to be combined with the output of adder 27 which adds bits b0 and b5. The result represented by the outut from S adder 28 is stated by the equation S= (b0+b4)- (b2+b6). This output passes to the Σ sine adder which accumulates the sine value by adding to its previous sum on lines 41, the value on lines 41 from S adder 28. The most significant bit representing the polarity of the sine sum is passed via line 33 in FIG. 2 to XOR logic, where it is a logical input along with the output of parity logic 40. Logic 40 contains adder 43 which adds all of the bits on lines b0-b7 together and divides by 2 in flip flop 44 to produce a parity output on line 45 to XOR 42 and XOR 46. 
     Adder 36 adds the values on lines b3 and b7, while adder 50 adds the values on lines b1 and b5 which are to be subtracted from the previous sum when presented to C adder 37 via 2&#39;s complement logic 31. Logic 31 contains inverters 34 and adder 35 and it operates analogously to adder 24. C adder 37 obtains the result of the formula (b3+b7)- (b1+b5). The output of adder 37 passes via cables 60 to the Σ cos adder 38 which is analogous to adder 29. The output of adder 38 on line 32 represents the polarity of the sum from adder 38 which passes to XOR 46. Output cables 61 from adder 38 are analogous to cables 39. 
     The output of XOR 42 passes on line 13 to the highest order address input line to ROSAR 15. The output of XOR 46 passes on line 12 to the second highest order address input line to ROSAR 15. When line 13 is positive, the ROS address is at least 128 and when line 12 is positive, the address is at least 64. This can be seen by reference to Table I which shows the addresses supplied to ROSAR 15 as well as the corresponding output values to ROSDR in binary numbers next to them. Table II shows the same information as Table I translated from decimal-binary to decimal-decimal form for the convenience of the reader. Note that the headings indicate the parity, sine and cos values for each vertical row of Table I. Note that the values for 0, 64, 128, and 192 across the whole of Table I down to 15, 79, 143, and 207 are identical as one crosses the page. The same applies to values from 56, 120, 184, 248 down to the end 63, 127, 191, and 255. In those cases, changes in the outputs of XOR&#39;s 42 and 46 will not change the output from ROSDR 17. This situation exists because the code words for those positions in the table are among those having zero contribution to the sine and cosine running sums. Code words which change both the sine and cosine sums can appear in only one column of the encoding table. 
     The ROS 16 can include hardware for converting any NRZI code to provide the desired null frequency. Table I is appropriate to a ROS for f 2  N=8, K=4, which provides a magnetic recording waveform which for the usual NRZI encoding has zero energy at one-half the all 1&#39;s frequency which may also be stated as zero energy at one-fourth of the data clock frequency. The number of bits in a word to be recorded from ROS 17 is eight bits. Thus, there are 256 possible combinations of bits which could be recorded on the magnetic medium in each word. However, many of these combinations are forbidden as they have an excessive number of successive zeroes for the clock circuits to handle during readback. A constraint employed is to limit the maximum number of successive zeroes to four. As a result of the previously stated restrictions, only the equivalent of six information bits (2 6  = 64 combinations) which can be encoded in the eight bit positions which are stored on the recording medium 20 (disk, tape, etc.). When recording, the input data on cable 10 is received six bits in parallel at a time and encoded by ROS 16 into eight-bit storage words. When the words are later read back from medium 20, they are read back eight bits at a time to generate groups of six data bits, as shown by Table III. 
     Table I shows how this is done. The left-hand column for &#34;data in&#34; from 0-63  represents binary 00000000 as 0,  binary 00000001 as 1,  and 00011011 is 27, etc. Note that eight bits are involved, only the least six significant bits of which are from gate 14, the two most significant bits being from lines 12 and 13. Encoding is accomplished by the table lookup function of ROS 16. There are four possible encoded outputs for each input on cable 10, register 11 and gate 14 which are selected by the binary values upon lines 12 and 13. The values for the sine and cos energy terms and the parity term are shown above the columns in Table I. For the upper set of values parity is (-) or zero and for the lower set of values parity is (+) or one. The polarities of the sine and cos are truly polarities. For example, for an input word on cable 10 of 000011011 (27 decimal) and with parity zero (-) and the sine sum negative, and cos sum positive, the value (27) is found in column 2 next to decimal 91 yielding at ROSDR 17 the binary number 10100011 (decimal 163). 
     The above subject matter can be expressed in another way. Let Bs be the leading (sine) bit and Bc be the second bit. Let Ps represent the polarity of the running sine sum (zero for - and one for +), Pc the polarity of the cos sum, and let P be the parity at the end of the previously encoded word. Then Bs= Ps ⊕ P and Bc= Pc ⊕ P. In the above example, 011011(27) from cable 10 becomes 01011011 (91) from Tables I and II, the output for an input of 91 is 10100011 (163). Table II is identical to Table I, except that both the input and output binary words are represented as ordinary decimal numbers. 
     Decoding is accomplished using the code in Table III. The readback circuits, not shown, receive a bit pattern such as 10100011 (163) which the table lookup in a ROS indicates should be decoded as 011011 (27). 
     During the encoding process by clock time CL2, the sine, cos, and parity registers are updated for the next word. The values to be added can be obtained in additional elements of the ROS lookup table or computed directly, as shown in FIG. 2, depending on the relative cost of read only memory versus high-speed logic. The amount of memory required for the encoding lookup table in ROS can be reduced somewhat by observing that certain input words have don&#39;t-care conditions with regard to Bs and Bc. For example, input words 0 through 15 and 57 through 63 are independent of Bs and Bc. Words 16 through 31 depend only on Bs, and words 32 through 47 depend only on Bc. In such a small table it would probably not be worthwhile observing these shortcuts for address decoding, but in the longer codes of Table IV, the savings could be significant. In the decoding process, it should be observed that about half of the possible recorded words are not used, a fact which is useful for error detection. 
     The embodiment given in FIGS. 1 and 2 is a self-contained circuit that could be inserted into an existing magnetic recording write channel. The previously existing write driver circuits shown in FIG. 1 perform an encoding function which could be incorporated into the lookup table ROS, with minor circuit changes which would be obvious to a skilled practitioner of the art, without significantly altering the invention. For the example given, NRZI magnetic encoding, the encoding function is particularly simple, being performed by a single flip-flop which processes the data stream serially, and which changes output level during a clock period for each one. Thus, the encoding produced by the ROS could be already in the NRZI form, resulting in minor changes to the sine and cosine circuitry: a complementary ROS output would be used, depending on the previous parity, and the last bit of the encoded word is the new parity, so the parity logic of FIG. 1 would be omitted. Such a minor circuit rearrangement can be obtained in a straightforward way by merging the encoder circuit of this invention with a small part of the conventional circuitry of the magnetic recording system. 
     Table IV shows the coding efficiency which can be obtained with this technique for f 2 . The code of Table I is represented by N=8. As a rule of thumb, the encoded word is about 2 bits longer than the input data word, and the minimum run length K increases as the word length N and the coding efficiency increase. It is also possible to null more than two spectral components; for example, the DC component can also be eliminated at the cost of approximately another bit. This would involve another storage register, and the lookup table would have eight lists instead of four. ##SPC1## 
     
                       TABLE IV______________________________________Characteristics of Some Optimal Codes for Nulling f/2______________________________________N     M        K     η  n       m______________________________________4     2        3     50%    16      326     4        4     67%    64      2568     6        4     75%    256     153610    8        5     80%    1024    819212    10       5     83%    4096    40960______________________________________ N = number of bits in the word after encoding M = number of bits in the word before encoding K = run length; the maximum number of successive zeros in the output η = coding efficiency = N/M n = number of words in the lookup table for encoding = 2.sup.N m = number of memory bits required for the lookup table for encoding = nM