Abstract:
A programmable logic device (PLD) includes a transceiver, configurable phase-locked loop (PLL) circuits, and programmable logic circuits. The logic circuits and PLL circuits are programmed to enable the transceiver to flexibly respond to various types of input serial data signals, and to flexibly generate various types of output serial data signals, such as Serial Digital Interface (SDI) signals and High Definition SDI (HD-SDI) signals. This allows the PLD to be used in a wide variety of systems without requiring custom external components.

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates to programmable logic devices (PLDs). More particularly, the present invention relates to a PLD with a transceiver and a reconfigurable phase-locked loop (PLL) circuit. 
   A PLD is a flexible device that includes programmable function blocks (also called IP blocks in the industry) programmably connected via a programmable interconnect structure. Typical function blocks include logic blocks, processor blocks, signal processor blocks, PLL blocks, memory blocks, input/output blocks, etc. A user can select which blocks to connect, and the functionality of each block, depending on the particular job the PLD is to perform. In this manner, a PLD is a low-cost and flexible solution to a wide variety of system requirements. 
   Exemplary PLDs include field programmable gate arrays (FPGAs) such as STRATIX™ devices, APEX™ devices, and FLEX® devices; complex programmable-logic devices (CPLDs) such as MAX® devices; and embedded processors such as EXCALIBUR™ devices, all from Altera Corp., San Jose, Calif. 
   A PLL circuit is a circuit that generates an output signal based on an input signal. A typical PLL circuit includes a reference divider, a feedback divider, a comparator, a charge pump, a loop filter, and an oscillator. The output signal is then a function of the input signal and a ratio between the reference divider and the feedback divider. In a reconfigurable PLL, the values in the dividers are programmable, which allows the PLL to generate a very wide variety of output signal frequencies that can be changed during normal system operation. 
   One type of function performed by some PLDs is a transceiver function. A transceiver refers to a circuit element that receives and input signal and/or generates an output signal. For the wide variety of potential systems that use PLDs, a correspondingly wide variety of input signal types are provided as inputs to the transceiver. In many instances, numerous external components must be provisioned so that the input signal to the PLD conforms to a particular type of signal. Similarly, a correspondingly wide variety of output signal types may need to be provided as inputs to other system components from the output signals from the PLD, which in many existing systems may also require numerous components between the PLD and the other system components. 
   There is a need for a PLD that more flexibly responds to the wide variety of potential input signals, and that more flexibly generates a wide variety of potential output signals, without requiring dependence upon external components. 
   BRIEF SUMMARY OF THE INVENTION 
   Embodiments of the present invention are directed toward using elements of the PLD to allow the transceiver to be used with a wider variety of input signals, and to generate a wider variety of output signals, without requiring the use of external components. 
   According to one embodiment, an apparatus includes a PLD. The PLD includes a first PLL circuit and a transceiver control block. The first PLL circuit generates a first PLL output signal. The first PLL output signal is one of a first plurality of configurable output signals. The transceiver control block is coupled to the first PLL circuit. The transceiver control block receives an input serial data signal and the first PLL output signal, samples the input serial data signal using the first PLL output signal, and generates a parallel data signal from the input serial data signal having been sampled. 
   According to another embodiment, an apparatus includes a PLD. The PLD includes a control circuit, a PLL circuit, and a transceiver circuit. The control circuit receives a first reference signal and an input serial data signal, and selectively generates a second reference signal based on a selected one of the input serial data signal and the first reference signal. The PLL circuit is coupled to the control circuit. The PLL circuit receives the second reference signal and generates a PLL output signal based on the second reference signal. The transceiver circuit is coupled to the PLL circuit. The transceiver circuit receives the input serial data signal and the PLL output signal, samples the input serial data signal using the PLL output signal, and generates a parallel data signal from the input serial data signal having been sampled. The control circuit trains the PLL circuit by selecting the first reference signal, then selects the input serial data signal once the PLL circuit has been trained. 
   The PLDs discussed above may further include a second PLL circuit and a second transceiver control block. The second PLL circuit generates a second PLL output signal. The second transceiver control block receives a second parallel data signal and the second PLL output signal, samples the second parallel data signal using the second PLL output signal, and generates an output serial data signal from the second parallel data signal having been sampled. 
   The PLDs discussed above may also include a plurality of programmable function blocks and an interconnect. The function blocks perform a variety of programmable functions and include the first PLL circuit and the transceiver control block. The interconnect programmably interconnects the plurality of programmable function blocks. 
   According to another embodiment, a method operates a PLD. The method includes generating a first PLL output signal. The first PLL output signal is one of a first plurality of configurable output signals. The method further includes receiving the first PLL output signal and an input serial data signal, and selectively generating a reference signal based on a selected one of the input serial data signal and the first PLL output signal. The first PLL output signal is selected to train a PLL circuit of the PLD, and the input serial data signal is selected once the PLL circuit has been trained. The method further includes receiving the reference signal and generating a second PLL output signal based on the reference signal. The method further includes receiving the input serial data signal and the second PLL output signal, sampling the input serial data signal using the second PLL output signal, and generating a parallel data signal from the input serial data signal having been sampled. 
   A more refined understanding of the embodiments of the present invention may be gained with reference to the following drawings and accompanying detailed description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a transceiver in a PLD according to an embodiment of the present invention. 
       FIG. 2  is a block diagram of a transceiver in a PLD according to another embodiment of the present invention. 
       FIG. 3  is a flowchart of a method of operating a transceiver in a PLD according to an embodiment of the present invention. 
       FIG. 4  is a block diagram of a transceiver in a PLD according to another embodiment of the present invention. 
       FIG. 5  is a block diagram of a transceiver in a PLD according to another embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  is a block diagram of a PLD  100  according to an embodiment of the present invention. The PLD  100  includes an interconnect  102  and various function blocks  104 . Specific elements of note in the function blocks  104  include a transceiver control block  106 , a PLL circuit  108 , and an optional oscillator  110 . Signals of note include an input serial data signal  120 , a parallel data signal  122 , and an external clock signal  124 , and a PLL output signal (clk 1 )  126 . In general, the function of note is the conversion of the input serial data signal  120  into the parallel data signal  122 . 
   The PLL  108  may be configured to output a wide variety of output signal frequencies based upon the configuration of its reference divider and feedback divider. The PLL  108  according to one embodiment uses an external clock  124  as its input. The external clock  124  may be provided to a pin on the package of the PLD  100 . According to another embodiment, an oscillator  110  generates the input signal to the PLL  108 . The oscillator  110  may be a crystal oscillator. 
   The transceiver control block  106  receives the PLL output signal  126  and the input serial data signal  120 , and generates the parallel data signal  122 . In effect, the transceiver control block  106  uses the PLL output signal  126  to sample the input serial data signal  120 . 
   The transceiver control block  106  may selectively operate in one of two modes, or a combination thereof. The two modes are “locktorefclk” mode and “locktodata” mode. 
   In “locktodata” mode, the transceiver control block  106  locks to the input serial data signal  120  for performing the conversion to the parallel data signal  122 . “Locktodata” mode is further described with reference to  FIG. 2  below. 
   In “locktorefclk” mode, the transceiver control block  106  performs a fixed-frequency serial-to-parallel conversion of the input serial data  120 . The rate at which the input serial data  120  is sampled is a fixed multiple of the frequency of a reference clock. For example, when the transceiver control block  106  is configured to provide a 10-bit parallel word, and the reference clock may be 135 MHz, the serial data may be sampled at 1350 Mbps (regardless of the actual data rate of the input serial data signal  120 ). 
   As one example of “locktorefclk” mode, assuming an external clock input of 27 MHz, the PLL  108  may be configured to provide a multiple of 5 as the output frequency, resulting in the PLL output signal  126  having a frequency of 135 MHz. The PLL  108  may be reconfigured to provide a multiple of 24/5 as the output frequency, resulting in the PLL output signal  126  having a frequency of 129.6 MHz. 
   The transceiver control block  106  is then driven by the PLL output signal  126 . By using the reconfigurability of the PLL  108 , the sample rate of the transceiver control block  106  can be dynamically changed. 
   Serial Digital Interface (SDI) is a serial interface that typically runs at 270 Mbps. There are variants of SDI that run at other frequencies, such as 259.2 Mbps. (Note that 259.2 Mbps is the ratio 24/25 times 270 Mbps.) 
   The transceiver control block  106  may oversample the input serial data signal  120 . Logic circuitry in the transceiver control block  106  then extracts the original 270 Mbps data. For example, if a 5× oversample is used, the sampling rate is 1350 Mbps for 270 Mbps data. In such a case, the PLL  108  provides the PLL output signal  126  having a frequency of 135 MHz to the transceiver control block  106 . 
   Continuing the example, to also support 259.2 Mbps SDI, the PLL  108  may be reconfigured to change the PLL output signal  126  to have a frequency of 129.6 MHz. 
   In both cases, the same input clock signal of 27 MHz may be provided to the PLL  108  (for example, via the external clock signal  124 ). 
     FIG. 2  is a block diagram of one embodiment of the transceiver control block  106 . The transceiver control block  106  includes a control circuit  202 , a PLL circuit  204 , and a transceiver and sampler  206 . Signals of note include a reference signal  210  and a PLL output signal (clk 2 )  212 . As with  FIG. 1 , these components may be implemented using the function blocks of the PLD  100 . 
   The control circuit  202  receives the PLL output signal  126  (see  FIG. 1 ) and the input serial data signal  120 , and generates the reference signal  210 . Initially, the control circuit  202  uses the PLL output signal  126  to generate the reference signal  210 . (This is also referred to as “locktorefclk” mode.) At a later point, the control circuit switches over to the input serial data signal  120  and uses the input serial data signal  120  to generate the reference signal  210 . (This is also referred to as “locktodata” mode.) The control circuit may include frequency multipliers and dividers that are used to adjust the particular signal used as the input to generate the output reference signal  210 . 
   The PLL  204  receives the reference signal  210  and generates the PLL output signal  212 . Thus, depending upon whether the reference signal  210  corresponds to the input serial data signal  120  or the PLL output signal  126 , the PLL  204  controls the phase-locked loop in either “locktodata” mode or “locktorefclk” mode, respectively. 
   The transceiver and sampler  206  receives the input serial data signal  120  and the PLL output signal  212 , and generates the parallel data signal  122 . In effect, the transceiver and sampler  206  uses the PLL output signal  212  to sample the input serial data signal  120 . The transceiver and sampler  206  may oversample the input serial data signal. The transceiver and sampler  206  may include frequency multipliers and dividers that are used to adjust the PLL output signal  212  to achieve a desired sampling or oversampling frequency. 
   Initially, the control block  202  directs the transceiver and sampler  206  to use the PLL output signal  126  to track the data rate of the input serial data signal  120 . The PLL  204  is trained with the PLL output signal  126  so that it is approximately centered on the frequency of the input serial data signal  120 . 
   As an example, when the transceiver and sampler  206  is configured to provide a 20-bit parallel word, and the PLL output signal  126  is 74.25 MHz, the PLL  204  may be trained to sample the input serial data signal  120  at 1485 Mbps (regardless of the actual data rate of the input serial data signal  120 ). Once the PLL  204  has been trained, the control block  202  allows the PLL  204  to track the actual data rate of the input serial data signal  120 , which is typically within a small part per million (ppm) of the trained frequency. 
   The control block  202  may use various criteria in deciding when to switch from “locktorefclk” mode to “locktodata” mode. As one option, the control block  202  may be programmed with an adjustable time period that has been calculated as a reasonable training period. As another option, the control block  202  may monitor the PLL  204  and may switch to “locktodata” modes once the PLL output signal  212  is within a defined tolerance, such as a frequency tolerance. As another option, the control block  202  may monitor the input serial data signal  120  and may begin training when a signal is detected. As another option, the control block  202  may monitor the PLL  204  and/or the input serial data signal  120  and may switch back to “locktorefclk” mode if instability or other undesirable signal properties arise in the PLL output signal  212 , in the input serial data signal  120 , and/or in other signals internal to the PLL  204 . 
   As described above with reference to  FIG. 1 , the PLL  108  may be reconfigured to change the frequency of the PLL output signal  126 , thereby changing the training frequency used on the PLL  204 . Thus, the training frequency of the PLL  204  may be dynamically changed. 
   For example, the PLL  108  may initially be configured to provide a frequency multiplier of 11/4. With a 27 MHz input clock, this results in the PLL output signal  126  having a frequency of 74.25 MHz. The PLL  108  may be reconfigured to provide a frequency multiplier of 250/91. This then results in the PLL output signal  126  having a frequency of 74.175 MHz. 
   High Definition Serial Digital Interface (HD-SDI) is a serial interface that typically runs at 1485 Mbps or 1435 Mbps. The transceiver control block  106  supports 1485 Mbps HD-SDI by using a 74.25 MHz reference signal (PLL output signal  126 ), and 1435 Mbps HD-SDI by using a 74.175 Mbps reference signal (PLL output signal  126 ). To support both these HD-SDI rates, the PLL  108  may be dynamically reconfigured. 
     FIG. 3  is a flowchart of a method  300  of operating a transceiver and related circuitry in the PLD  100  according to an embodiment of the present invention. In step  302 , the PLL  108  generates the PLL output signal  126 . 
   In step  304 , the control block  202  receives the PLL output signal  126  and the input serial data signal  120 . The control block  202  selectively generates the reference signal  210  based on a selected one of the input serial data signal  120  and the PLL output signal  126 . The control block  202  initially selects the PLL output signal  126  to train the PLL  204 . The control block  202  later selects the input serial data signal  120  once the PLL  204  has been trained. 
   In step  306 , the PLL  204  receives the reference signal  210 . Based on this signal, the PLL  204  generates the PLL output signal  212 . 
   In step  308 , the transceiver and sampler  206  receives the input serial data signal  120  and the PLL output signal  212 . The transceiver and sampler  206  samples the input serial data signal  120  using the PLL output signal  212 . The transceiver and sampler  206  generates the parallel data signal from the input serial data signal  120  having been sampled. 
     FIG. 4  is a block diagram showing further features of the PLD  100 .  FIG. 4  is similar to  FIG. 1 , except in  FIG. 4  the transceiver generates an output of the PLD  100  (that is, the transceiver is configured as a transmitter). These features shown in  FIG. 4  may be implemented along with the features shown in  FIG. 1 , or may be implemented separately. 
   In most cases, the elements of  FIG. 4  are similar to the elements of  FIG. 1 . The interconnect  102  and function blocks  104  perform essentially the same function. The transceiver control block  406  receives a parallel data signal  420  as an input and generates a serial data signal  422  as an output. The transceiver control block  406  is clocked by the clk 1  signal  426 . 
   The PLL 1   408  receives an input signal (either an external clock signal  424  or a signal from an optional oscillator  410 ) and generates the clk 1  signal  426 . The PLL 1   408  otherwise may be similar to the PLL  108  of  FIG. 1 . The external clock signal  424  may correspond to the external clock signal  124  (see  FIG. 1 ), for example by being connected to the same pin. The oscillator  410  may be the same as the oscillator  110 ; for example, a single oscillator may provide the same reference signal to the PLL 1   108  and the PLL 1   408 . 
   The parallel data signal  420  may correspond to the parallel data signal  122  (see  FIG. 1 ), or it may correspond to a different parallel data signal. For example, in some configurations, the PLD  100  may be configured to receive an SDI signal, process the SDI signal, convert the processed SDI signal to an HD-SDI signal, and then output the converted HD-SDI signal. 
   Given the similarity of the components between  FIGS. 1 and 4 , it can be seen that a given transceiver may be easily configured as a receiver (see  FIG. 1 ) or as a transmitter (see  FIG. 4 ) according to the particular desired use of the PLD  100 . 
     FIG. 5  is a block diagram of one embodiment of the transceiver control block  406 . The transceiver control block  406  is similar to the transceiver control block  106  (see  FIG. 2 ) and includes a PLL 2   504  and a transceiver and sampler  506 . The control block  202  (see  FIG. 2 ) is unnecessary to the function of  FIG. 5 . In particular, in the embodiment shown in  FIG. 5 , the “locktorefclk” mode is used, and the “locktodata” mode is not used. In other embodiments, the “locktodata” mode may be used, in which case the structure and functionality is more similar to that of  FIG. 2 . 
   The transceiver and sampler  506  receives the parallel data signal  420  and generates the serial data signal  422 . The transceiver and sampler  506  is otherwise similar to the transceiver and sampler  206  (see  FIG. 2 ). The transceiver and sampler  506  is clocked by the clk 2  signal  512  from the PLL 2   504 . The PLL 2   504  generates the clk 2  signal  512  based on the clk 1  signal  426  in a manner similar to that described above with reference to the PLL 2   204  (see  FIG. 2 ). 
   Given the similarity of the components between  FIGS. 2 and 5 , it can be seen that a given transceiver and sampler may be easily configured as a receiver (see  FIG. 2 ) or as a transmitter (see  FIG. 5 ) according to the particular desired use of the PLD  100 . In such a case, an unnecessary component may be present in the transceiver control block  406  (such as the control block  202 ), but may be disabled or bypassed according to the particular configuration. 
   Although the above description has focused on the use of phase-locked loops, it is recognized that similar functionality may be gained from the use of other types of feedback circuits, such as delay-locked loop (DLL) circuits. The choice of loop circuit may be made depending upon other design constraints and considerations. 
   Although the above description has focused on serial-to-parallel and parallel-to-serial conversions generally, and SD/HD-SDI specifically, it is recognized that similar principles may be applied to other types of signal conversions. 
   Although the above description has focused on specific embodiments, various modifications and their equivalents are to be considered within the scope of the present invention, which is defined by the following claims.