Abstract:
A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to semiconductor integrated circuits in general, and, more particularly, to semiconductor integrated circuits applicable to LSI&#39;S, such as general purpose processors, digital signal processors, graphics processors and various control processors.  
           [0002]    To achieve high performance design automation, gate array and cell-based IC&#39;s are currently in wide use. In particular, one type of a logic circuit referred to as a pass-transistor logic circuit, is known in this field. It is published that the pass-transistor logic circuit has a higher density, lower power consumption and smaller delay time than the CMOS logic circuits that are commonly used as the logic circuits.  
           [0003]    So far, pass-transistor logic circuits have been introduced as a Differential Pass-Transistor Logic in the IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 2, April 1987, pp216-pp222 (hereinafter referred to as a first conventional technology); as a Complementary Pass-Transistor Logic in the IEEE Journal of Solid-State Circuits, Vol. sc-25, No. 2, April 1990, pp388-pp395 (hereinafter referred to as a second conventional technology); and as a 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic in the IEEE Journal of Solid State Circuits, Vol. 28, No. 11, November 1993, pp1145-pp1151 (hereinafter referred to as a third conventional technology).  
           [0004]    Further, a Low-Power Logic Style: CMOS Versus Pass-Transistor Logic has been introduced in the IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, July 1997, pp1079-pp1090 (hereinafter referred to as a fourth conventional technology). An example layout of a pass-transistor logic circuit is introduced in the Principles of CMOS VLSI Design—A Systems Perspective (by H. E. Weste &amp; Kamran Eshraghian, translated by T. Tomisawa and Y. Matsuyama), published on Aug. 30, 1998, Maruzen Co., Ltd., p. 173 (hereinafter referred to as a fifth conventional technology). A circuit design technique that combines a pass-transistor circuit and the abovementioned standard-cell-based design is introduced in the IEEE 1994 Custom Integrated Circuits Conference, pp603-pp606 (hereinafter referred to as a sixth conventional technology)  
           [0005]    Further, a circuit design technique that combines a-pass-transistor circuit and the standard-cell-based design by using a logic representation method called a binary decision diagram is introduced in the Institute of Electronics, Information and Communication Engineering, Proceedings of the 1994 IEICE Fall Conference (hereinafter referred to as a seventh conventional technology). A logic circuit cell using a pass-transistor circuit is shown in JPA-7-130856 (laid-open on May 19, 1995, and corresponding to U.S. Pat. No. 5,581,202) (hereinafter referred to as an eighth conventional technology). A transmission gate multiplexer is disclosed in U.S. Pat. No. 5,162,666 (hereinafter referred to as a ninth conventional technology). A “Pass Transistor Network in MOS Technology”is introduced in IEEE 1983 International Symposium on Circuit and Systems, pp509-pp512 (hereinafter referred to as a tenth conventional technology).  
         SUMMARY OF THE INVENTION  
         [0006]    [0006]FIGS. 4 a  and  4   b  show, as an example to be compared, the layout of a cell of a CMOS logic circuit developed by the inventors of this invention. To the knowledge of the present inventors, this layout is not known to the public. In this layout, gate terminals of PMOS and NMOS are arranged in line with each other to reduce the layout area. The inventors conducted a preliminary study on the cell layout based on the above design philosophy to realize an integrated circuit with a small layout area by using pass-transistor circuits.  
           [0007]    [0007]FIGS. 5 a  and  5   b  show the result of a study by the present inventors. In these figures, the source (drain) diffusion layers at the same voltage cannot be used commonly to arrange the gate terminals closer together. Hence, the diffusion layers that cannot be used commonly need to be connected by upper-layer metal wires, giving rise to a problem of increased layout area and wire length. The longer total wire length as well as the increased layout area, in turn, increase the delay time. The object of the present invention is to provide a pass-transistor logic circuit that has a small layout area.  
           [0008]    The conventional pass-transistor logic circuit has a problem that because the source (drain) terminal acts as an input terminal, the input signal waveform degrades. Further, because the input capacitance changes depending on the operating conditions, the delay calculation is difficult. To solve these problems, an inverter has been known to be provided to an input terminal of source (drain) terminal (as in the ninth and tenth conventional technology). However, the preliminary study by the inventors has found that this method increases the delay time by as much as the inverters added. Another object of the invention is to provide a pass-transistor logic circuit which is fast and allows easy delay calculation.  
           [0009]    The present invention proposes a selector portion layout method to be used during the process of laying out the pass-transistor logic circuit cells of the above construction.  
           [0010]    According to one aspect of the present invention, a cell is used that has at least one selector. To fabricate cells with small areas by using only polysilicon wires, or wires of the same material as gate terminals, and first-layer metal wires, the semiconductor circuit of the present invention is laid out according to the following design philosophy.  
           [0011]    That is, in the pass-transistor circuit, pMOS&#39;s and nMOS&#39;s that are applied the same signals receive complementary gate signals. The MOS&#39;s with the same drain outputs are arranged to share their diffusion layers.  
           [0012]    Further, according to another aspect of the present invention, when there is a plurality of selectors, output buffers are arranged at the ends of the cell, and the selectors are arranged in a direction in which the first power supply line and the second power supply line extend. With this arrangement, if there is a plurality of selectors, the number of the selectors can be increased flexibly in the direction of expansion, thus assuring a systematic layout. This in turn reduces the time required to design the layout of the selectors.  
           [0013]    According to a further aspect of the present invention, a signal buffer is connected to the input side of the selector. As a result, all signals entering the pass-transistor circuit become gate signals, which in turn reduce the input capacitance, thus solving the problem of degraded input waveform. This arrangement can also prevent the input capacitance from varying depending on the operation conditions, making it easy to estimate the input capacitance and the delay calculation. This can be expected to shorten the design time.  
           [0014]    Further, in this circuit which has the signal buffers connected to the source and drain terminals, because the signal path passing through the gate terminal of the pass-transistor circuit does not pass through the signal buffer, the high speed operation is possible.  
           [0015]    According to a further aspect of the present invention, the integrated circuit including the circuit of this invention has power supply lines, of which power supply lines  1 ,  3 ,  5 , . . . ,  2   n + 1 , . . . (n is a natural number) are at the same voltage, and power supply lines  2 ,  4 ,  6 , . . .  2   n , . . . (n is a natural number) are at the same voltage. Thus, this integrated circuit can coexist with other circuits represented by CMOS circuits.  
           [0016]    According to a further aspect of the present invention, the integrated circuit including the circuit of this invention has a latch. Because a signal passing through the gate terminal of the selector does not pass through the signal buffer, a high speed signal transmission between the latches is possible. The circuit of the invention therefore is an important factor in determining the specification of the integrated circuit.  
           [0017]    According to a further aspect of the present invention, a signal that has passed through the input buffer now passes through the selector, from which it is transmitted to a plurality of input terminals. This enables the whole integrated circuit to be formed compactly.  
           [0018]    According to one embodiment of the circuit of  15  the present invention, the integrated circuit includes a selector  1  and logic gates  1 ,  2  and also power supply lines  1 ,  2 ,  3 ,  4 ,  5  and  6  arranged in parallel. Of these power supply lines  1 ,  3 ,  5  are virtually at the same voltage and power supply lines  2 ,  4 ,  6  are virtually at the same voltage. The selector  1  has PMOS 1 ,  2 , and NMOS 1 ,  2 ,  3 ,  4 ; a gate of PMOS 1  is controlled by an input signal  1 ; and a source-drain path of PMOS 1  is connected between an operation voltage point  1  and a node  1 . A gate of PMOS 2  is controlled by an input signal  2 ; and a source-drain path of PMOS 2  is connected between the operation voltage point  1  and a node  2 . A gate of NMO@L is controlled by the input signal  1 , and a source drain path of NMOS 1  is connected between an operation voltage point  2  and the node  1 . A gate of NMOS 2  is controlled by the input signal  2 , and a source-drain path of NMOS 2  is connected between the operation voltage point  2  and the node  2 . A gate of NMOS 3  is controlled by an input signal  3 , and a source-drain path of NMOS 3  is connected between the node  1  and a node  3 . A gate of NMOS 4  is controlled by an input signal  4 , and a source-drain path of NMOS 4  is connected between the node  2  and the node  3 . The node  3  is connected to input terminals of the logic gate  1  and the logic gate  2 .  
           [0019]    Further, if the circuit is formed as a sequential circuit, it is characterized as follows. It has first and second temporary memory circuit; a first power supply line is formed in a horizontal direction; and a second power  15  supply line is formed parallel to the first power supply line. The second temporary memory circuit is controlled by the same clock signal as is used for the first temporary memory circuit. A data output node  01  of the first temporary memory circuit controls the gate terminals of NMOS 1  and PMOS 2 . The source-drain path of NMOS 1  is connected between nodes n 1  and n 2 ; the source-drain path of PMOS 2  is connected between nodes n 2  and n 3 ; the source-drain path of PMOS 3  is connected between the first power supply line and the node n 1 ; the source-drain path of NMOS 3  is connected between the second power supply line and the node n 1 ; a signal of node n 4  controls the gate terminals of PMOS 3  and NMOS 3 ; the source drain path of PMOS 4  is connected between the first power supply line and the node n 3 ; the source-drain path of NMOS 4  is connected between the second power supply line and the node n 3 ; a signal of node n 5  controls the gate terminals of PMOS 4  and NMOS  4 ; the source-drain path of NMOS 2  is connected to the nodes n 2  and n 3 ; the source-drain path of PMOS 1  is connected between the nodes n 1  and n 2 ; a signal of node n 6  controls the gate terminals of PMOS 1  and NMOS 2 ; a signal of node n 2  controls the gate terminals of PMOS 5  and NMOS 5  and is applied to input the terminals of other logic gates; a source-drain path of PMOS 5  is connected between the first power supply line and node n 7 ; a source-drain path of NMOS 5  is connected between the second power supply line and the node n 7 ; a source-drain path of NMOS 8  is connected between nodes n 7  and n 9 ; a source-drain path of NMOS 8  is connected between node n 7  and n 9 ; a source-drain path of PMOS 9  is connected between nodes n 9  and n 11 ; a source-drain path of NMOS 9  is connected between nodes n 9  and n 11 ; a signal of node n 8  controls the gate terminals of PMOS 9  and NMOS 8 ; a signal of node n 10  controls the gate terminals of PMOS 8  and NMOS 9 ; a signal of node n 12  controls the gate terminals of PMOS 8  and NMOS 8 ; a source-drain path of PMOS 8  is connected between the first power supply line and node n 11 ; a source-drain path of NMOS  8  is connected between the second power supply line and node n 11 ; a signal of node n 15  controls the gate terminals of PMOS 9  and NMOS 9 ; a source-drain path of PMOS 9  is connected between the first power supply line and node h 14 ; a source-drain path of NMOS 9  is connected between the second power supply line and node n 14 ; a source-drain path of PMOS 10  is connected between nodes n 14  and n 17 ; a source-drain path of NMOS 10  is connected between nodes n 14  and n 17 ; a source-drain path of PMOS 11  is connected between nodes n 9  and n 17 ; a source-drain path of NMOS 11  is connected between nodes n 9  and n 17 ; a signal of node n 13  controls the gate terminals of PMOS 10  and NMOS 11 ; a signal of node n 16  controls the gate terminals of PMOS 11  and NMOS 10 ; a signal of node n 18  controls the gate terminals of PMOS 15  and NMOS 15 ; a source-drain path of PMOS 15  is connected between the first power supply line and node n 18 ; a source-drain path of NMOS 15  is connected between the second power supply line and node nl 8 ; a source-drain path of PMOS 13  is connected between nodes n 20  and n 22 ; a source-drain path of NMOS 13  is connected between nodes n 20  and n 22 ; a source-drain path of PMOS 14  is connected between nodes n 18  and n 20 ; a source-drain path of NMOS 14  is connected between nodes n 18  and n 20 ; a signal of node n 17  controls the gate terminals of PMOS 13  and NMOS 14 ; a signal of node n 21  controls the gate terminals of PMOS 14  and NMOS 13 ; a signal of node n 23  controls the gate terminals of PMOS 12  and NMOS 12 ; a source-drain path of PMOS 12  is connected between the first power supply line and node n 22 ; a source-drain path of NMOS 12  is connected between the second power supply line and node n 22 ; and a signal of node n 20  is connected between the inputs of the second temporary memory circuit.  
           [0020]    [0020]FIGS. 7 a - 7   c  are circuit diagrams of logic circuits to which the present invention is applicable. FIG. 7 a  shows a circuit in which a signal is amplified after it has passed through the selector. FIG. 7 c  shows a circuit in which a signal is amplified before it passes through the selector. As a result, in the circuit of FIG. 7 c , the input capacitance produced when the circuit receives drain inputs is only that of the gates of the input buffers, thus significantly reducing the input capacitance. FIG. 7 b  shows a circuit with a plurality of selectors. The layouts suited for these circuits will be described in detail. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    [0021]FIGS. 1 a - 1   d  are layout and circuit diagrams of pass-transistor logic circuits according to one embodiment of the invention.  
         [0022]    [0022]FIGS. 2 a - 2   b  are layout and circuit diagrams of a pass-transistor logic circuit according to one embodiment of the invention.  
         [0023]    [0023]FIGS. 3 a - 3   b  are layout and circuit diagrams of a pass-transistor logic circuit according to one embodiment of the invention.  
         [0024]    [0024]FIGS. 4 a - 4   b  are layout and circuit diagrams of a CMOS logic circuit ( 4 -input AND) devised by the inventors prior to the present invention.  
         [0025]    [0025]FIGS. 5 a - 5   b  are layout and circuit diagrams of a logic circuit cell shown as an example for a comparison that does not use an embodiment of the invention, and which was devised by the inventors prior to the present invention.  
         [0026]    [0026]FIGS. 6 a - 6   c  are layout and circuit diagrams of a logic circuit shown as an example for a comparison which was devised by the inventors prior to the present invention.  
         [0027]    [0027]FIGS. 7 a - 7   c  are circuit diagrams of logic circuits according to one embodiment of the present invention.  
         [0028]    [0028]FIG. 8 is a layout diagram of a pass-transistor  5  logic circuit according to one embodiment of the present invention.  
         [0029]    [0029]FIG. 9 is a circuit diagram of a pass-transistor logic circuit according to one embodiment of the present invention.  
         [0030]    [0030]FIG. 10 is a layout diagram of a pass-transistor logic circuit according to one embodiment of the present invention.  
         [0031]    [0031]FIG. 11 is an array configuration of a pass-ransistor logic circuit according to one embodiment of the 15 present invention.  
         [0032]    [0032]FIG. 12 is an array configuration of a passtransistor logic circuit according to one embodiment of the present invention.  
         [0033]    [0033]FIGS. 13 a - 13   b ,  14   a - 14   b ,  15   a - 15   b ,  16   a - 16   b ,  17   a - 17   b ,  18   a - 18   b ,  19   a - 19   b ,  20   a - 20   b ,  21   a - 21   b ,  22   a - 22   b ,  23   a - 23   b ,  24   a - 24   b ,  25   a - 25   b ,  26   a - 26   b , and  27   a - 27   b  are each layout and circuit diagrams of pass-transistor logic circuits according to embodiments of the present invention.  
         [0034]    [0034]FIGS. 28 a - 28   b  are layout and circuit diagrams of a latch according to one embodiment of the invention  
         [0035]    [0035]FIG. 29 is a circuit diagram of a chip accordingly to one embodiment of the present invention.  
         [0036]    [0036]FIG. 30 is a layout diagram of a chip according to one embodiment of the present invention.  
         [0037]    [0037]FIG. 31 is a layout diagram of a chip according to one embodiment of the present invention (double threshold 5 value).  
         [0038]    [0038]FIGS. 32 a - 32   b  are a layout diagram of a pass-transistor logic circuit according to one embodiment of the present invention and a cross section of a device. 
     
    
     DETAILED DESCRIPTION OF EMBODIMENTS  
       [0039]    Embodiments of the present invention will be described by referring to the accompanying drawings. FIGS. 1 a - 1   d  are layout and circuit diagrams of one embodiment of the invention. In FIGS. 1 a - 1   d , p 101 -p 107  and n 101 -n 107  represent transistors, and In 101 -In 108  represent input signals from outside. Node 101 -node 103  denote inputs and outputs of a selector; Out 101  and Out 102  denote outputs of a pass-transistor logic circuit; BC 101  denotes an output buffer; IB 101 ,  102  denote input buffers; cp 101 ,  102  denote body bias contacts; and cn 101 ,  102  denote well bias contacts.  
         [0040]    In the pass-transistor logic circuit of this invention, PMOS and NMOS that receive the same signal at their sources are applied with complementary gate signals. The circuit is arranged so that a pair of MOS&#39;s with the same drain outputs share their diffusion layers.  
         [0041]    In FIGS. 1 a - 1   d , p 102  and p 103 , and n 102  and n 103  are paired to share their diffusion layers. Further, p 102  and n 103  are arranged and connected so that their gates are in line in a direction perpendicular to the power supply line. With this arrangement, a wire connecting the drains of PMOS and NMOS, and a wire connecting the sources of PMOS and NMOS do not cross each other, so that they can be wired with only a polysilicon wire and a metal wire of a first layer. Further, the gate input signals In 101 , In 102  do not cross each other, and thus can be wired with only a polysilicon wire.  
         [0042]    Further, the unused MOS areas by the side of p 102   10  and n 103 , that are created by arranging the p 102  and n 103  so that their gates are in line in a direction perpendicular to the power supply line, may be utilized for placing the gate terminals, thus eliminating dead space.  
         [0043]    When laying out a semiconductor integrated circuit having at least one selector, if a direction parallel to a first power supply line and a second power supply line is set in a horizontal or lateral direction, output buffers are arranged at the left and right ends of the cell, with the selector connecting to the inputs of the output buffers placed between them. This arrangement is made to avoid a situation in which, because the input of the output buffer formed by wiring the gates of PMOS and NMOS with a polysilicon wire, and the output formed by wiring the drains of pMOS And nMOS with the first wiring layer are lead out in a direction perpendicular to the power supply line, internal wiros-in the cell must use the second wiring layer in order to pass-over the output buffer. This arrangement allows the output of the selector and the output&#39;s inverted signal to be sent smoothly to the output buffer, reducing the layout area. That is, in this embodiment, because the output buffers are arranged on both sides of the selector, with respect to the direction of the power supply line, if two or more selectors exist, the output buffers do not interfere with the lines running between the selectors, making it possible to reduce the layout area with ease.  
         [0044]    An example shown in FIGS. 2 a - 2   b  will be explained as follows. In FIGS. 2 a - 2   b , p 201 -p 206  and n 201 -n 206  designate transistors, and In 201 -In 206  input signals from outside. NPC 201  is a selector circuit, node 201  and node 202  are outputs of the selector circuit, Out 201  and out 202  outputs of pass-transistor logic circuits, BC 201  and BC 202  are output buffers, cp 201  is a body bias contact, and cn 201  is a well bias contact.  
         [0045]    The selector circuit which has different gate signals for pMOS and nMOS, is laid out so that MOSS with the same drain outputs share their diffusion layers. The MOSS that are paired to share their diffusion layers are p 203  and p 204 ; p 205  and p 206 ; n 203  and n 204 ; and n 205  and n 206  in FIGS. 2 a - 2   b . Further, the pair of p 203  and p 204  and the pair of p 205  and p 206  are arranged with a minimum interval, and the pair of n 203  and n 204  and the pair of n 205  and n 206  are also arranged with a minimum interval. Further, p 203  and n 204 , and p 205  and n 206  are arranged in line and wired. A wire connecting the drains of pMOS and nMOS, and a wire connecting the sources of pMOS and nMOS do not cross each other, so they can be wired with only a first layer&#39;s metal wire. Further, the gate input signals In 201 , In 202  do not cross each other and thus can be wired with only a polysilicon wire. Further, the unused MOS areas above n 203  and below p 206 , which are created by arranging p 203  and n 204  and also p 205  and n 206  in line, may be used for leading out the gate input terminals to eliminate a dead space.  
         [0046]    As described later, in the above semiconductor integrated circuit of this embodiment, when there is a plurality of selector circuits (for example, NPC 901 , NPC 902  and NPC 903  in FIG. 9), they are arranged in the direction of the first power supply line and the second power supply line. In FIG. 8, NPC 801 , NPC 802  and NPC 803  are arranged in that order.  
         [0047]    In the above semiconductor integrated circuit of this embodiment, the output buffers are arranged at the ends of the cell (p 801 , p 802 , n 801  and n 802  in FIG. 8). If two or more selector circuits (for example, NPC 901 , NPC 902  and NPC 903  in FIG. 9) exist, they can be laid out in a systematic manner because the number of selector circuits can be increased flexibly in the expansion direction. This can reduce the time required for the layout design.  
         [0048]    In FIGS. 3 a  and  3   b , p 301 -p 306  and n 301 -n 306  denote transistors, and In 301 -In 306  denote input signals from outside. NPC 301  represents a selector, node 301  and node 302  represent outputs of the selector, Out 301  and Out 302  represent outputs of pass-transistor logic circuits, BC 301  and BC 302  represent output buffers, cp 301  represents a body bias contact, and cn 301  represents a well bias contact.  
         [0049]    In FIGS. 4 a  and  4   b , p 401 -p 405  and n 401 -n 405  denote transistors, In 401 -In 404  denote input signals from outside, Out 491  denotes an output signal, cp 401  denotes a base bias contact, and cn 401  denotes a well bias contact.  
         [0050]    In FIGS. 5 a  and  5   b , p 501 -p 506  and n 501 -n 506  denote transistors, In 501 -In 506  denote input signals from outside. NPC 501  represents a selector, node  501  and node  502  represent outputs of the selector, out 501  and Out 502  represent outputs of pass-transistor logic circuits, BC 501  and BC 502  represent output buffers, cp 501  represents a body bias contact, and cn 501  a well bias contact.  
         [0051]    In FIGS. 6 a - 6   c , p 601 -p 602  and n 601 -n 602  represent transistors, In 601 -In 604  represent input signals from outside, and Out 601  represents an output of the circuit.  
         [0052]    In FIGS. 7 a - 7   c , p 701 -p 703 , n 701 -n 703 , p 711 -p 716 , n 711 -n 716 , p 721 -p 724  and n 721 -n 724  denote transistors, and In 701 -In 704 , In 711 -In 716  and In 721 -In 724  denote input signals from outside. NPC 711  denotes a selector; node 701 -node 702 , node 711 -node 712  and node 721 -node 722  denote outputs of the selector; Out 701 , Out 711 -Out 712  and Out 721  denote outputs of pass-transistor logic circuits; BC 711 -BC 712  denote output buffers; and IB 721 -IB 722  denote input buffers.  
         [0053]    In FIG. 8, p 801 -p 814  and n 801 -n 814  indicate transistors, and NPC 801 -NPC 803  indicate selectors. In the embodiment shown in FIG. 8, the output buffers (p 801 , p 802 , n 801  and n 802 ) are arranged near the cell boundary along the direction in which the power supply line extends (in the horizontal direction in FIG. 8), so that if two or more selector circuits exist, the output buffers do not interfere with the connections between the selectors, and, therefore cells can be laid out in a small area without difficulty  
         [0054]    [0054]FIG. 9 shows an example circuitry that applies the layout of FIG. 8. When a plurality of selector circuits (NPC 901 , NPC 902 , NPC 903 ) exist, they are arranged in the direction in which the first and second power supply lines extend. In FIG. 9, p 901 -p 914  and n 901 -n 914  denote transistors and In 901 -In 914  denote input signals from outside. NPC 901 -NPC 903  represent selectors, Out 901 -Out 902  represent outputs of pass-transistor logic circuits, and BC 901 -BC 902  represent output buffers. When the layout concept of FIG. 8 is applied, because the output buffers (p 801 , pB 02 , n 801 , n 802  in FIG. 8) are arranged close to the cell boundary in the direction in which the power supply line extends (in the horizontal 15direction in FIG. 8), if two or more selector circuits exist as described above, the output buffers do not interfere with the connections between the selectors, and, therefore, cells can be laid out in a small area without difficulty.  
         [0055]    In FIG. 10, In 1001 -In 1014  denote input signals from outside, and Out 1001 -Out 1002  denote outputs of pass-transistor logic circuits.  
         [0056]    [0056]FIGS. 11 and 12 show example layouts applying the present invention, in which the pass-transistor logic circuits and CMOS,s are mixed together. It is seen in the figures that the cells can be arranged with minimum intervals, whatever the adjoining cells. When a transistor at the cell end adjoining another cell connects to the power supply line, and if a transistor at the end of the adjoining cell similarly connects to the power supply line, their diffusion layers can be shared, further reducing the chip area.  
         [0057]    [0057]FIGS. 13 a - 13   b  show a circuit constructed by using the present invention. FIGS. 13 a - 13   b  are, respectively, a layout diagram ( 13   a ) and a circuit diagram ( 13   b ) using two selector circuits. The output of one selector circuit connects to the drain input of the other selector circuit In this case, as well, the use of this invention can provide a layout with no dead space. In FIG. 13, In 1301 -In 1307  represent input signals from outside, Out 1301  represents an output of a pass-transistor logic circuit, cp 1301  represents a base bias contact, and cn 1301  represents a well bias contact.  
         [0058]    [0058]FIGS. 14 a - 14   b  show a circuit using the present invention. FIGS. 14 a  and  14   b  are, respectively, a layout diagram ( 14   a ) and a circuit diagram ( 14   b ) in which two selector circuits are used. The output of one selector circuit connects to the input gate of the other selector circuit to generate an inverted signal of the gate of the selector by an internal inverter. In this case, as well, the use of the present invention can generate a layout with no dead space. In FIGS. 14 a - 14   b , In 1401 -In 1405  indicate input signals from outside, Out 1401  indicates an output of a pass-transistor logic circuit, cp 1401  indicates a base bias contact, and cn 1401  indicates a well bias contact.  
         [0059]    [0059]FIGS. 15 a - 15   b  show a circuit using the present invention. FIGS. 15 a  and  15   b  are, respectively, a layout diagram ( 15   a ) and a circuit diagram ( 15   b ) in which three selector circuits are used. The outputs of selectors near the inputs of another selector connect to drain inputs of the other selector which are close to the corresponding outputs. In this case, as well, the use of the present invention can generate a layout with no dead space. In FIGS. 15 a - 15   b , In 1501 -In 1510  denote input signals from outside, Outl 501  denotes an output of a pass-transistor logic circuit, cp 1501  denotes a base bias contact, and cn 1501  denotes a well bias contact.  
         [0060]    [0060]FIGS. 16 a - 16   b  show a circuit using the present invention. FIGS. 16 a  and  16   b  are, respectively, a layout diagram ( 16   a ) and a circuit diagram ( 16   b ) in which three selector circuits are used, and the inverted signal of the gate of the selector is generated by an internal inverter. The outputs of selectors near the inputs of another selector, connect to a drain input add a gate input of the other selector which are close to the corresponding outputs. In this case, as well, the use of the present invention can produce a layout with no dead space. In FIGS. 16 a - 16   b , Inl 601 -Inl 607  denote input signals from outside, Out 1601  denotes an output of a pass-transistor logic circuit, cpl 601  denotes a base bias contact, and cn 1601  denotes a well bias contact.  
         [0061]    [0061]FIGS. 17 a - 17   b  show a circuit using the present invention. FIGS. 17 a  and  17   b  are, respectively, a layout diagram ( 17   a ) and a circuit diagram ( 17   b ) in which four selector circuits are used, and the inverted signal of the gate of the selector is generated by an internal inverter. The outputs of selectors near the inputs of another selector, connect to drain inputs and a gate input of the other selector which are close to the corresponding outputs. In this case, as well, the use of the present invention can produce a layout with no dead space. In FIGS. 17 a - 17   b , In 1701 -In 1709  denote input signals from outside, Out 1701  denotes an output of a pass-transistor logic circuit, cp 1701  denotes a base bias contact, and cn 1701  denotes a well bias contact.  
         [0062]    [0062]FIGS. 18 a - 18   b  show a circuit using the present invention. FIGS. 18 a  and  18   b  are, respectively, a layout diagram ( 18   a ) and a circuit diagram ( 18   b ) in which when four selector circuits are used. The outputs of one selector connect to the drain inputs of the other selector. In this case, as well, the use of the present invention can produce a layout with no dead space. In FIGS. 18 a - 18   b , NPC 1801 -NPC 1802  denote selectors, BC 1801 -BC 1802  denote output buffers, cp 1801  denotes a base bias contact, and cn 1801  denotes a well bias contact.  
         [0063]    [0063]FIGS. 19 a - 19   b  show a circuit using the present invention. FIGS. 19 a  and  19   b  are, respectively, a layout diagram ( 19   a ) and a circuit diagram ( 19   b ) in which four selector circuits are used. The outputs of one selector connects to the gate inputs of the other selector. In this case, as well, the use of the present invention can produce a layout with no dead space. In FIGS. 19 a - 19   b , NPC 1901 -NPC 1902  denote selectors, BC 1901 -BC 1902  denote output buffers, cp 1901  denotes a base bias contact, and cn 1901  denotes a well bias contact.  
         [0064]    [0064]FIGS. 20 a - 20   b  show a circuit using the present invention. FIGS. 20 a  and  20   b  are, respectively, a layout diagram ( 20   a ) and a circuit diagram ( 20   b ) in which six selector circuits are used. The outputs of selectors near the inputs of another selector connect to drain inputs of the other selector, which are close to the corresponding outputs. In this case, as well, the use of the present invention can produce a layout with no dead space. In FIGS. 20 a - 20   b , NPC 2001 -NPC 2003  denote selectors, BC 2001 -BC 2002  denote output buffers, cp 2001  denotes a base bias contact, and cn 2001  denotes a well bias contact.  
         [0065]    [0065]FIGS. 21 a - 21   b  show a circuit using the present invention. FIGS. 21 a  and  21   b  are, respectively, a layout diagram ( 21   a ) and a circuit diagram ( 21   b ) in which six selector circuits are used. The outputs of selectors near the inputs of another selector connect to drain inputs and gate inputs of the other selector, which are close to the corresponding outputs. In this case, as well, the use of the present invention can produce a layout with no dead space. In FIGS. 21 a - 21   b , NPC 2101 -NPC 2103  denote selectors, BC 2101 -BC 2102  denote output buffers, cp 2101  denotes a base bias contact, and cn 2101  denotes a well bias contact.  
         [0066]    [0066]FIGS. 22 a - 22   b  show a circuit using the present invention. FIGS. 22 a  and  22   b  are, respectively, a layout diagram ( 22   a ) and a circuit diagram ( 22   b ) in which eight selector circuits are used. The outputs of selectors near the inputs of another selector connect to drain inputs and gate inputs of the other selector, which are close to the corresponding outputs. In this case, as well, the use of the present invention can produce a layout with no dead space. In FIGS. 22 a - 22   b  , NPC 2201 -NPC 2204  denote selectors, BC 2201 -BC 2202  denote output buffers, cp 2201  denotes a base bias contact, and cn 2201  denotes a well bias contact.  
         [0067]    [0067]FIGS. 23 a - 23   b  show a circuit using the present invention. FIGS. 23 a  and  23   b  are, respectively, a layout diagram ( 23   a ) and a circuit diagram ( 23   b ) showing a selector circuit having signal amplifying devices at its inputs. This circuit reduces an input capacitance of the drain and the use of the present invention results in a layout with no dead space. In FIGS. 23 a - 23   b , p 2301 -p 2304  and n 2301 -n 2304  denote transistors, and In 2301 -In 2304  denote input signals from outside. IB 2301 -IB 2302  are input buffers, node 2301 -node 2302  are outputs of the input buffers, Out 2301  is an output of a pass-transistor logic circuit, cp 2301  is a base bias contact, and cn 2301  is a well supply contact.  
         [0068]    [0068]FIGS. 24 a - 24   b  show a circuit using the present invention. FIGS. 24 a  and  24   b  are, respectively, a layout diagram ( 24   a ) and a circuit diagram ( 24   b ) showing a selector circuit which has signal amplifying devices at its inputs, and in which there is one selector and an inverted signal of the gate of the selector, is generated by an internal inverter. This circuit reduces an input capacitance of the drain and the use of the present invention results in a layout with no dead space. In FIGS. 24 a - 24   b , p 2401 -p 2405  and n 2401 -n 2405  denote transistors, and In 2401 -In 2403  denote input signals from outside. IB 2401 -IB 2402  are input buffers, node 2401 -node 2402  are outputs of the input buffers, Out 2401  is an output of a pass-transistor logic circuit, cp 2401  is a base bias contact, and cn 2401  is a well supply contact.  
         [0069]    [0069]FIGS. 25 a - 25   b  show a circuit using the present invention. FIGS. 25 a  and  25   b  are, respectively, a layout diagram ( 25   a ) and a circuit diagram ( 25   b ) showing a selector circuit which has signal amplifying devices at its inputs and in which there are two selectors. This circuit reduces an input capacitance of the drain and the application of the present invention can produce a layout with no dead space by sharing the diffusion layers. In FIGS. 25 a - 25   b , p 2501 -p 2508  and n 2501 -n 2508  denote transistors, and In 2501 -In 2506  denote input signals from outside. IB 2501 -IB 2504  are input buffers, Out 2501 -Out 2502  are outputs of pass-transistor logic circuits, cp 2501  is a base bias contact, and cn 2501  is a well supply contact.  
         [0070]    [0070]FIGS. 26 a - 26   b  show a circuit using the present invention. FIGS. 26 a  and  26   b  are, respectively, a layout diagram ( 26   a ) and a circuit diagram ( 26   b ) showing a selector circuit which has signal amplifying devices at its inputs and in which there are three selectors, and an inverted signal of the gate of each selector is generated by an internal inverter. This circuit reduces an input capacitance of the drain, and the application of the present invention can produce a layout with no dead space by sharing the diffusion layers.  
         [0071]    In FIGS. 26 a - 26   b , p 2601 -p 2611  and n 2601 -n 2611  denote transistors, and In 2601 -In 2607  denote input signals from outside. IB 2601 -IB 2605  are input buffers, Out 2601  is an output of a pass-transistor logic circuit, cp 2601  a base bias contact, and cn 2601  a well supply contact.  
         [0072]    [0072]FIGS. 27 a - 27   b  show a circuit using the present invention. FIGS. 27 a  and  27   b  are, respectively, a layout diagram ( 27   a ) and a circuit diagram ( 27   b ) showing a selector circuit which has signal amplifying devices at its inputs and in which there are six selectors. This circuit reduces an input capacitance of the drain and the application of the present invention can produce a layout with no dead space by sharing the diffusion layers. In FIGS. 27 a - 27   b , p 2701 -p 2722  and n 2701 -n 2722  denote transistors, and In 2701 -In 2714  denote input signals from outside. Out 2701 -Out 2702  are outputs of pass-transistor logic circuit, cp 2701  is a base bias contact, and cn 2701  a well supply contact.  
         [0073]    [0073]FIGS. 28 a - 28   b  show a circuit using the present invention. FIG. 28 a  is a latch layout and FIG. 27 b  is a circuit diagram ( 27   b ). The application of the present invention can produce a layout with no dead space by sharing the diffusion layers. In FIGS. 28 a - 28   b , p 2801 -p 2809  and n 2801 -n 2809  denote transistors, and In 2801 -In 2802  denote input signals from outside. out 2801  is an output of a pass-transistor logic circuit, cp 2801  is a base bias contact, and cn 2801  is a well supply contact.  
         [0074]    [0074]FIG. 29 shows a circuitry inside the chip of this invention. L 2901  and L 2902  are latches that are supplied with the same clock signal. A 2901 , A 2902  and A 2903  are pass-transistor logic circuit cells constructed by using the present invention. B 2901  is a CMOS circuit. A 2901 , A 2902  and A 2903  are arranged between a first power supply line (VCC in this embodiment) and a second power supply line (GND in this embodiment), and these circuits are interconnected with signal lines. A signal that has passed through the selector of A 2901  is connected to a plurality of terminals that use this signal.  
         [0075]    [0075]FIG. 30 is a layout diagram inside the chip of this invention. L 3001  and L 3002  are latches that are supplied with the same clock signal. A 3001 , A 3002  and A 3003  are pass-transistor logic circuit cells constructed by using the present invention, and B 3001  and B 3002  are CMOS circuit cells. A 3001 , A 3002  and A 3003  are arranged between a first power supply line (VCC in this embodiment) and a second power supply line (GND in this embodiment), and these circuits are interconnected with signal lines. A signal that has passed through the selector of A 3001  is connected to a plurality of terminals that use this signal. This circuit of the present invention can coexist with conventional CMOS circuits in a chip without a problem.  
         [0076]    [0076]FIG. 31 is a layout diagram inside the chip of this invention. L 3101  and L 3102  are latches that are supplied with the same clock signal. A 3101 , A 3102  and A 3103  are pass-transistor logic circuit cells constructed by using the present invention, and B 3101  and B 3102  are CMOS circuit cells. A 3101 , A 3102  and A 3103  are arranged between a first power supply line (VCC in this embodiment) and a second power supply line (GND in this embodiment), and these circuits are interconnected with signal lines. In a system of L 3101 -A 3101 -A 3102 -A 3103 -L 3102  when a faster signal transmission is required, circuits using low-threshold-voltage transistors are prepared. The circuits using low-threshold-voltage transistors can be constructed by this invention and the circuit performance can be improved by the invention.  
         [0077]    [0077]FIG. 32 b  shows a cross-sectional structure of circuit using this invention.  
         [0078]    With the above embodiments, it is possible to 10 provide semiconductor integrated circuits having pass-transistor logic circuit cells with a small area which can reduce power consumption, delay time and also design time.