Abstract:
An image sensor includes a unit cell having a plurality of pixels; the unit cell comprising an amplifier input transistor that is shared by the plurality of pixels; a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor; and an interconnect layer which forms an output signal wire which shields the floating diffusion interconnect layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     Reference is made to and priority claimed from U.S. Provisional Application Ser. No. 60/686,715, filed Jun. 2, 2005, entitled CMOS ACTIVE PIXEL SENSOR SHARED AMPLIFIER PIXEL WITH REDUCED SENSE NODE CAPACITANCE. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The invention relates generally to the field of CMOS image sensors and, more particularly, to such image sensors where multiple photodetectors share an amplifier.  
       BACKGROUND OF THE INVENTION  
       [0003]     In  FIG. 1 , the 2 shared pixel schematic of a prior art image sensor includes two photodetectors (PD 1  and PD 2 ) each having an associated transfer gate (TG 1  and TG 2 ) that transfer charge to a common floating diffusion sense node. A row select transistor (RSEL) selects the row for readout, and a reset transistor with a reset gate (RG) resets the common floating diffusion sense node (n+) to a predetermined voltage. A source follower input transistor (SF) senses the voltage on the common floating diffusion sense node (n+) and amplifies the signal. The prior art image sensor in  FIG. 2  is a similar concept except that four photodiodes (PD 1 -PD 4 ) and TGs (TG 1 -TG 4 ) share common components.  
         [0004]     These shared amplifier pixels were intended to produce small pixels with high fill factor with less scaled CMOS processes. With a small pixel, the photodiode can have low charge capacity. Shared amplifier pixels inherently have higher floating diffusion capacitance than un-shared amplifier pixels, due to having multiple floating diffusions connected together. The larger capacitance is a consequence of multiple floating diffusion regions comprising a single charge to voltage conversion node, and due to the parasitic capacitance of the interconnect layers connecting the multiple floating diffusion regions. As a result, it is desired to reduce the floating diffusion capacitance so that an adequate voltage signal swing can be achieved at the sense node.  
         [0005]     Consequently, the present invention describes ways to reduce the floating diffusion capacitance in shared amplifier CMOS Active Pixel Sensor (APS) designs.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the present invention resides in an image sensor comprising a unit cell having a plurality of pixels; the unit cell comprising (a) an amplifier input transistor that is shared by the plurality of pixels; (b) a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor; and (c) an interconnect layer which forms an output signal wire which shields the floating diffusion interconnect layer.  
         [0007]     These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.  
         [0000]     Advantageous Effect of the Invention  
         [0008]     The present invention has the following advantage of reducing the charge to voltage conversion region also referred to as a sense node capacitance in shared amplifier CMOS Active Pixel Sensor (APS) designs. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a schematic diagram of a prior art image sensor having two photodiodes sharing an amplifier;  3   FIG. 2  is a schematic diagram of a prior art image sensor having four photodiodes sharing an amplifier;  
         [0010]      FIG. 3   a  is a schematic diagram of the image sensor of the present invention having two photodiodes sharing a common sense node which uses the output bus to shield the floating diffusion interconnect layer;  
         [0011]      FIG. 3   b  is a side view in cross section along line  3   b - 3   b  of  FIG. 3   a;    
         [0012]      FIG. 4   a  is a schematic diagram of a prior art pixel having the floating diffusion in a P-Well;  
         [0013]      FIG. 4   b  is a schematic diagram of a pixel of the present invention having the floating diffusion in a deeper and more lightly doped n-type implant and with the NMOS P-Well implant masked from the floating diffusion region;  
         [0014]      FIG. 4   c  is a schematic diagram of a pixel of the present invention and a more specific embodiment of  FIG. 4   b  wherein the deeper and more lightly doped n-type implant is formed with an implant that is also used in the photodetector; and  
         [0015]      FIG. 5  is an illustration of a digital camera of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]     Before discussing the present invention in detail, it is instructive to note that the present invention is preferably used in, but not limited to, a CMOS active pixel sensor. Active pixel sensor refers to active electrical elements within the pixel such as the reset transistor and row select transistor, and CMOS refers to complementary metal oxide silicon type electrical components such as transistors which are associated with the pixel, but typically not in the pixel, and which are formed when the source/drain of a transistor is of one dopant type and the opposite dopant type encloses it. CMOS devices typically consume less power.  
         [0017]     Referring to  FIG. 3   a , there is shown a schematic diagram of a unit cell  10  having a plurality of pixels  20   a  and  20   b . The image sensor  30  of the present invention includes a plurality of unit cells  10  that form the pixel array. Each unit cell  10  includes two or more photosensitive regions (PD 1  and PD 2 ) that accumulate charge in response to incident light. Preferably, photodiodes are used as the photosensitive region (PD 1  and PD 2 ) and preferably two pixels form a unit cell  10 . A row select transistor RSEL selects the row for output. Each photosensitive region (PD 1  and PD 2 ) respectively includes a transfer gate (TG 1  and TG 2 ) for transferring the charge to their respective shared sense node (n+), preferably a floating diffusion, which converts the charge to a voltage. The sense nodes (n+) are electrically connected together by a floating diffusion interconnect layer  40 . A reset gate (RG) resets the voltage on the sense node (n+) to a predetermined voltage prior to the transfer of charge from the photosensitive region (PD 1  and PD 2 ) to the sense node (n+). An amplifier, preferably a source follower (SF), senses the voltage on electrically connected sense nodes (n+) for output on an output bus or output wire  50 .  
         [0018]     Referring to  FIGS. 3   a  and  3   b , it is instructive to note that the output wire  50  is physically placed so that it shields the floating diffusion interconnect layer  40 . This reduces the capacitance of the electrically connected floating diffusions (n+). The floating diffusion interconnect layer  40  is routed in a metal interconnect layer that is preferably physically above or higher than that of the output wire  50 . By shielding the floating diffusion interconnect layer or wire  40  with a routing of the output wire  50  below it, the parasitic capacitance of the floating diffusion interconnect layer  40  is reduced. Typically, the output wire  50  would be wider than the floating diffusion interconnect layer  40  to produce more effective shielding.  
         [0019]     Although the preceding embodiments are shown having two photodiodes sharing an amplifier, the present invention is applicable to any number of photodiodes sharing an amplifier. For example, there may be 3 or more photodiodes sharing an amplifier.  
         [0020]     Referring to  FIGS. 4   b  and  4   c , an alternative method for reducing the floating diffusion capacitance for shared pixel designs is by use of a deeper and more lightly doped implant for the n+active area regions of the floating diffusion, and removal or modification of the P-Well from the floating diffusion region. This reduces the junction capacitance of the floating diffusion sense node. Typically in the prior art (shown in  FIG. 4   a ), the floating diffusion active area region (n+) is implanted with the n+ source/drain of the complementary metal oxide semiconductor (CMOS) process and is enclosed by the P-Well  60  used to form n-type metal oxide semiconductor field effect transistors (MOSFETs). This n+ source/drain implant is typically higher than 1e14 cm 2  and results in a junction depth of less than 0.20 um. The P-Well  60  is also a high dose implant yielding effective p-type background concentrations of greater than 1e16 cm-3. The present invention shown in  FIGS. 4   b  and  4   c  uses an additional n-type implant  70  in the floating diffusion active area region (n+) to increase the depletion region width. This is done separately or in conjunction with elimination of the P-Well implant from all or part of the floating diffusion region, or modification of the P-Well implant to have a lower background concentration. The additional n-type implant  70  would typically be Phosphorous at an energy of greater than or equal to 50 KeV, and a dose of less than 1e14 cm 2 . This implant is preferred to be the photodiode implant used to form the photodetector  20 .  
         [0021]     Referring to  FIG. 5 , there is shown a digital camera  80  having the image sensor  30  disposed therein for illustrating a typical commercial embodiment to which the ordinary consumer is accustomed.  
         [0022]     The invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention.  
       Parts List  
       [0000]    
       
           10  unit cell  
           20  photodetector  
           20   a  pixel  
           20   b  pixel  
           30  image sensor  
           40  floating diffusion interconnect layer or wire  
           50  output bus or output wire  
           60  P-Well  
           70  n-type implant  
           80  digital camera