Abstract:
A liquid crystal display driving circuit comprises a plurality of transfer gates having their one end connected in common to a source line of a liquid crystal display panel and their other end connected to a plurality of driving voltages, respectively, for supplying a different voltage to the source line. A control circuit receives an image input data for selectively turning on the transfer gates, for the purpose of realizing a multiple gray scale display. The control circuit is configured to turn on one transfer gate selected from the plurality of transfer gates during a first period of one display period, and then, to maintain the turned-on condition of the selected transfer gate during the remaining period of one display period, or to simultaneously turn on two transfer gates which are selected from the plurality of transfer gates and which include the selected transfer gate during the remaining period of one display period.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a liquid crystal device driving circuit, and more specifically, to a circuit for driving a liquid crystal display panel capable of displaying an image with a multiple tone level. 
     2. Description of Related Art 
     As a liquid crystal device driving circuit for generating a source voltage driving a liquid crystal display panel typified by an active matrix type, a circuit for enabling a multiple tone or gray scale image on the order of eight gray scale levels has been implemented in the form of a LSI (large scale integrated circuit) and is now under mass production and widely used. 
     FIG. 1 is a block diagram showing one example of a conventional liquid crystal device driving circuit. In order to display a multiple gray scale image in a liquid crystal display panel, it is required to supply a drive voltage corresponding to a required luminance, from drive voltage output terminals T1 to Tk of a transistor switch circuit 3 to corresponding source lines of the liquid crystal display panel. 
     For this purpose, the drive circuit includes &#34;k&#34; stages of &#34;n&#34;-bit shift registers 15a to 15k receiving an image input data Vi from an image data input terminal, a corresponding number of &#34;n&#34;-bit latches 16a to 16k  each for latching the &#34;n&#34;-bit data of a corresponding one of the &#34;n&#34;-bit shift registers 15a to 15k, and a corresponding number of selector circuits 14a to 14k for selectively turning on output transistors Q11 to Qmk included in the transistor switch circuit 3 on the basis of an output of the latches 16a to 16k. 
     Namely, an &#34;n&#34;-bit digital image input data Vi indicative of &#34;m&#34; gray scale levels is supplied from the image data input terminal 7, and shifted and stored in the &#34;n&#34;-bit shift registers 15a to 15k in response to a clock pulse Vc applied to a clock input terminal 1. In response to a latch pulse Vr applied to a latch pulse input terminal 2, the data stored in each of the registers is transferred to a corresponding one of the &#34;n&#34;-bit latches 16a to 16k. 
     The &#34;n&#34;-bit data latched in each latch is decoded by a corresponding one of the selector circuits 14a to 14k to the effect that one transistor of the first &#34;m&#34; output stage transistors Q11 to Qm1 connected to the drive output terminal T1 of the transistor switch circuit 3 is turned on, and one transistor of the &#34;k&#34;th &#34;m&#34; output stage transistors Q1k to Qmk connected to the drive output terminal Tk is turned on. With this arrangement, voltages V1, V2, . . . , V m  corresponding to drain voltage terminals 8a to 8m of &#34;m&#34; gray scale levels are supplied, so that voltages of &#34;m&#34; gray scale levels are supplied to an external liquid crystal display. 
     For example, assuming that the image input data Vi is composed of digital signals D 0 , D 1 , . . . , D n-1 , the voltage Vo appearing on the drive output terminal T1 is as shown in FIG. 2. 
     In this conventional liquid crystal device driving circuit, if the number of gray scale levels is increased, it is required to connect low-impedance large-current-capacity, external voltage supplies, and therefore, when the driving circuit is assembled in the liquid crystal display panel, wiring conductors must be thickened and the overall assembly of the liquid crystal display panel correspondingly becomes Large. In addition, with an increase in the number of pixels in the liquid crystal display panel, the driving circuit is required to have a low impedance. 
     Furthermore, if the number of gray scale levels is increased, when a buffer circuit having a low impedance and a large output capacity is implemented on the same semiconductor substrate, the chip size becomes extremely large, and therefore, the driving circuit becomes costly. Because of this reason, most of this type of liquid crystal display driver is on the order of 8 gray scale levels to 16 gray scale levels. For a full-color display, however, the liquid crystal display panel required to have a gray scale of 64 levels or more is going to be marketed. 
     Under this circumstance, in order to increase the number of gray scale levels, the present applicant has proposed one approach, which is disclosed in the specification of Japanese Patent Application No. Hei 4-80176. This approach is featured, not only by turning on only one of the transistors Q 11  to Q m1  of the transistor switch circuit as in the circuit shown in FIG. 1, but also by simultaneously turning on a plurality of transistors of the transistors Q 11  to Q m1 , so that the voltage outputted from the drive voltage output terminal T1 has a multiple voltage level. 
     FIG. 3 is a block diagram of this liquid crystal display driving circuit, and in FIG. 3, the elements similar to those shown in FIG. 1 are given the same Reference Numerals. 
     For this purpose, the drive circuit includes &#34;k&#34; stages of &#34;(n+1)&#34;-bit shift registers 5a to 5k receiving an image input data from an image data input terminal 7, a corresponding number of &#34;(n+1)&#34;-bit latches 6a to 6k each for latching the &#34;(n+1)&#34;-bit data of a corresponding one of the &#34;(n+1)&#34;-bit shift registers 5a to 5k, and a corresponding number of selector circuits 4a to 4k for selectively turning on output transistors Q11 to Qmk included in the transistor switch circuit 3 by decoding the data outputted from the latches 5a to 6k. With a selective turning-on control of the transistors Q11 to Qmk in the transistor switch circuit 3, a drive output voltage Vo is generated on each of the drive voltage output terminals T 1  to T k . 
     Namely, a digital image input data Vi formed of &#34;(n+1)&#34; bits (D 0 , D 1 , . . . , D n ) is supplied from the input terminal 7, and sequentially shifted and stored in the &#34;(n+1)&#34;-bit shift registers 5a to 5k in response to a clock pulse Vc. In response to a latch pulse Vr, the data stored in each of the registers is transferred to a corresponding one of the &#34;(n+1)&#34;-bit latches 6a to 6k. The &#34;(n+1)&#34;-bit data latched in each latch is decoded by a corresponding one of the selector circuits 4a to 4k to the effect that either one transistor or two transistors of the first &#34;m&#34; output stage transistors Q11 to Qm1 connected to the drive output terminal T1 of the transistor switch circuit 3 is simultaneously turned on, and either one transistor or two transistors of the &#34;k&#34;th &#34;m&#34; output stage transistors Q1k to Qmk connected to the drive output terminal Tk is simultaneously turned on. With this arrangement, voltages V1, V2, . . . , V m  corresponding to drain voltage terminals 8a to 8m of &#34;m&#34; gray scale levels or their combined voltages are generated. 
     For example, assuming that the &#34;(n+1)&#34;-bit image input data Vi is composed of digital signals D 0 , D 1 , . . . , D n , the voltage Vo appearing on the drive output terminal T1 is as shown in FIG. 4. 
     Here, when the digital signals (D 0 , D 1 , . . . , D n )=(0, 0, . . . , 0), only the output transistor Q 11  is turned on by the associated selector circuit 4a, so that the output voltage V 1  is outputted. When the digital signals (D 0 , D 1 , . . . , D n )=(0, 0, . . . , 1), the output transistors Q 11  and Q 21  are simultaneously turned on by the associated selector circuit 4a. At this time, assuming that all the output transistors Q 11  to Q mk  have the same current driving capacity, the output voltage Vo becomes Vo=(V 1  +V 2 )/2. 
     Namely, the output transistors are equally formed on the same silicon substrate, the characteristics of the output transistors Q 11  to Q mk  have only a little variation in a relative small zone within the same chip, even if it greatly varies from one manufacturing lot to another and from one wafer to another. Namely, the variation of the transistors is on the order of 10% at maximum. Therefore, it becomes Vo≈(V 1  +V 2 )/2, depending on a ratio in on-resistance ratio of the output transistors Q 11  and Q 21 . Furthermore, in order to realize a multiple gray scale level in the liquid crystal display panel, the intervals of voltage steps are obtained by dividing the voltage of about 3 V to 4 V applied to the liquid crystal display, by the number of required gray scale levels. 
     For example, if 16 gray scale levels are required, the voltage steps having the voltage intervals on the order of 0.25 V (=4 V/16) are applied to the liquid crystal display panel. Accordingly, assuming that when the output transistors Q 11  and Q 21  are simultaneously turned on, a relative variation between the output transistors Q 11  and Q 21  is 10%, if (V 1  -V 2 )=0.25 V, the variation of the output voltage Vo is on the order of 25 mV. This is not so significant in an image displayed on the liquid crystal display panel. 
     Similarly, either one or two of each &#34;m&#34; transistors of the output transistors Q 1k  to Q mk  are simultaneously turned on by the associated selector circuit 4k. Thus, (2m-1) different output drive voltages can be obtained from the &#34;m&#34; different voltages Vm supplied from the voltage supply terminals 8a to 8m. 
     Incidentally, for convenience, the switching elements of the transistor switch circuit 3 have been composed of the transistors Q 11  to Q mk . However, even if the transistors are replaced with transfer gates, the same effect can be obtained. 
     In the above mentioned liquid crystal device driving circuit, when the output transistors Q 11  and Q 21  are simultaneously turned on, since the output impedance of the output transistors Q 11  and Q mk  is on the order of about 10KΩ to about 5KΩ, the current flowing through each output becomes on the order of about 50 μA to about 25 μA (=0.25 V/10KΩ to 0.25 V/5KΩ. In an LCD driver LSI in which a driving circuit for the liquid crystal display panel is formed on a silicon substrate, in the case of the output number &#34;k&#34;=192, the current becomes 4.8 mA to 9.6 mA, and therefore, the consumed electric power correspondingly becomes 1.2 mW to 2.4 mW (=(4.8 mA to 9.6 mA)×0.25 V). This value is almost no problem as the LCD driver LSI. 
     However, the liquid crystal panel uses at least 10 LCD driver LSIs each having the 192 outputs, and therefore:, a voltage supply for the liquid crystal device driving circuit requires at least a current corresponding to the 10 LCD driver LSIs, namely, a current supplying capacity of 48 mA to 96 mA. If the voltage supply is 20 V, there is required a large consumed electric power of 0.96 W to 1.92 W (=(48 mA to 96 mA)×20 V). 
     Furthermore, the conventional liquid crystal device driving circuit can realize the (2m-1) gray scale levels, by simultaneously turning on any two transistors of each &#34;m&#34; transistors of the output transistors Q 1k  to Q mk  by action of the selector circuit 4k. However, if the potential difference between the simultaneously turned-on transistors is large, a very large current is required for the conventional liquid crystal device driving circuit, and therefore, the consumed electric power correspondingly becomes large. This is not practical. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a liquid crystal device driving circuit which has overcome the above mentioned defect of the conventional ones. 
     Another object of the present invention is to provide a driving circuit for a multiple gray scale liquid crystal device, with a reduced number of external voltage supplies and with a reduced consumed electric power. 
     The above and other objects of the present invention are achieved in accordance with the present invention by a liquid crystal display driving circuit comprising a plurality of switching means having their one end connected in common to a source line of a liquid crystal display panel and their other end connected to a plurality of driving voltages, respectively, for supplying a different voltage to the source line, and a control means receiving an image input data for selectively turning on the switching means, for the purpose of realizing a multiple gray scale display, the control means including means for turning on one switching means selected from the plurality of switching means during a first period of one display period, and for simultaneously turning on the one switching means or a plurality of switching means selected from the plurality of switching means during a second period of one display period. 
     The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing one example of a conventional liquid crystal device driving circuit; 
     FIG. 2 is a table showing the relation between the image input data, the driving output voltage and the switching transistors in the circuit shown in FIG. 1; 
     FIG. 3 is a block diagram of another liquid crystal display driving circuit, 
     FIG. 4 is a table showing the relation between the image input data, the driving output voltage and the switching transistors in the circuit shown in FIG. 3; 
     FIG. 5 is a block diagram of one embodiment of the liquid crystal device driving circuit in accordance with the present invention; 
     FIG. 6 is a detailed circuit diagram of the output circuit shown in the liquid crystal device driving circuit shown in FIG. 5; 
     FIG. 7 is a table showing the relation between the input image data and the output voltage in the liquid crystal device driving circuit shown in FIG. 5; 
     FIG. 8 is a timing chart illustrating an operation of the liquid crystal device driving circuit shown in FIG. 5; 
     FIG. 9 is a block diagram of a second embodiment of the liquid crystal device driving circuit in accordance with the present invention; 
     FIG. 10 is a detailed circuit diagram of the output circuit included in the liquid crystal device driving circuit shown in FIG. 9; 
     FIG. 11 is a circuit diagram illustrating one example of a transfer gate; 
     FIG. 12 is a detailed block diagram showing the selector circuit in the liquid crystal device driving circuit shown in FIG. 9; 
     FIG. 13 is a logic diagram showing a specific circuit of the control circuit included in the selector circuit shown in FIG. 12; 
     FIG. 14 is a truth table showing the relation between the inputs and the outputs of the control circuit shown in FIG. 13; 
     FIGS. 15, 16, 17 and 18 are equivalent circuits showing various conditions of the output circuit included in the liquid crystal device driving circuit shown in FIG. 9; and 
     FIGS. 19 and 20 are tables for illustrating operation of the liquid crystal device driving circuit shown in FIG. 9. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Now, embodiments of the present invention will be described with reference to the drawings. 
     Referring to FIG. 5, there is shown a block diagram of one embodiment of the liquid crystal device driving circuit in accordance with the present invention. As one example, the shown embodiment is configured to receive image data of 5 bits (D M3 , D M2 , D M1 , D M0 , D H0 ) and to generate driving voltages of 2 5  =32 gray scale levels. In addition, the most significant bit of the 5-bit image data is labelled &#34;D M3  &#34;, and the least significant bit of the 8-bit image data is labelled &#34;D H0  &#34;. For convenience of description, the bits &#34;D M3  &#34; to &#34;D M0  &#34; of the 5-bit image data are called &#34;main bits&#34;, and the bit &#34;D H0  &#34; of the 5-bit image data is called a &#34;sub (interpolating) bit&#34;. 
     The shown drive circuit includes &#34;k&#34; stages of 5-bit shift registers 20a to 20k receiving an image input data from an image data input terminal 7, a corresponding number of 5-bit latches 21a to 21k each for latching the 5-bit data of a corresponding one of the 5-bit shift registers 20a to 20k, external gray scale level voltages V R0 , V R1 , . . . , V R16  corresponding to 16 gray scale levels, a corresponding number of output circuits 22a to 22k each generating an intermediate voltage between each pair of adjacent voltages of the gray scale level voltages V R0 , V R1 , . . . , V R16  on the basis of the interpolating bit &#34;D H0  &#34;, and a corresponding number of AND gates ANDa to ANDk for controlling the output of the interpolating bit &#34;D H0  &#34; from the 5-bit latches 21a to 21k to the output circuits 22a to 22k on the basis of an output voltage interpolating input Vh. 
     FIG. 6 shows a circuit diagram of the output circuits 22a to 22k. Each of the output circuits 22a to 22k includes a decoder 24 receiving the main bits &#34;D M3  &#34; to &#34;D M0  &#34; of 4 bits for activating one selection signal, transfer gates TG 0  to TG 16  connected to the external gray scale level voltages V R0 , VR 1 , . . . , V R16 , respectively, and control circuits SE 0  to SE 16  each receiving the interpolating bit &#34;D H0  &#34; and a corresponding one of outputs O M0  to O M16  of the decoder 24 for controlling a corresponding one of the transfer gates. Each of the control circuits SE 0  to SE 16  is formed of one AND gate and one OR gate connected as shown. 
     The 5-bit image input data D M3  to D M0  and D H0  is supplied through the image input terminal 7, and transferred through the 5-bit shift registers 20a to 20k in response to the clock pulse Vc. In response to the latch pulse Vr, the image input data in the 5-bit shift registers 20a to 20k is transferred and latched in the 5-bit latches 21a to 21k. The main bits D M3  to D M0  of the data latched in each latch are supplied to the decoder 24 of a corresponding output circuit 22a to 22k, so that an active selection pulse is outputted from one of the outputs O M0  to O M16  of the decoder in accordance with the content of the main bits D M3  m D M0 , as shown in FIG. 7. In FIG. 7, the label &#34;ON&#34; shows an active condition, and the label &#34;OFF&#34; indicates an inactive condition. 
     Namely, if (D M3 , . . . , D M0 )=(0, 0, 0, 0), the output O M0  is &#34;ON&#34; (active), and if (D M3 , . . . , D M0 )=(0, 0, 0, 1), the output O M1  is &#34;ON&#34; (active). If (D M3 , . . . , D M0 .sub.)=(1, 1, 1, 1), the output O M15  is &#34;ON&#34; (active). 
     In addition, the sub bit D H0  of the data latched in each latch is supplied through the AND gates ANDa to ANDk to the control circuits SE 0  to SE 16  of each output circuit 22a to 22k when the output voltage interpolating input Vh is &#34;1&#34; (high level). When the sub bit D H0  is &#34;0&#34;, the control circuits SE 0  to SE 16  output the signals received from the outputs O M0  to O M16  of the decoder, without modification. Namely, only any one of the transfer gates TG 0  to TG 16  is turned on in accordance with the content of the main bits D M3  to D M0 , so that one of the gray scale level voltages V R0  to V R16  connected to the transfer gates TG 0  to TG 16  , respectively, is selected and outputted to an output terminals OUT (T 1  to T k ). 
     On the other hand, when the sub bit D H0  is &#34;1&#34;, the control circuits SEn and SE(n+1) are selected by an active output signal OMn of the decoder 24, so that the transfer gates TGn and TG(n+1) are simultaneously selected. As a result, an intermediate voltage between the gray scale level voltage V Rn  connected to the transfer gates TG n  and the gray scale level voltages V R (n+1) connected to the transfer gate TG.sub.(n+1) is generated at the output terminal T 1  to T k  of the output circuits 22a to 22k. 
     Here, assuming that the all the transfer gates TG 0  to TG 16  are constructed to have the same structure and the same on-resistance, the output voltage becomes {V Rn  +V R (n+1) }/2. The function explained until here is completely the same as that of the conventional liquid crystal device driving circuit. Here, the relation between the input image data and the output voltage is as shown in FIG. 7. 
     Here, when the output voltage interpolating input Vh is &#34;0&#34;, the output of the AND gates ANDa to ANDk becomes &#34;0&#34;, and therefore, only one transfer gate is selected in accordance with the content of the main bits D M3  m D M0 . On the other hand, when the output voltage interpolating input Vh is &#34;1&#34;, if the sub bit D H0  is &#34;0&#34;, one transfer gate is selected in accordance with the content of the main bits D M3  to D M0 , similarly to the case of Vh=&#34;0&#34;. However, if the sub bit D H0  is &#34;1&#34;, a gray scale voltage near to an intermediate voltage between a pair of adjacent gray scale voltage supply voltages is selected as mentioned above. 
     Furthermore, an operation of the embodiment of the liquid crystal device driving circuit will be described with reference to the timing chart of FIG. 8. In an active matrix type liquid crystal display panel, a voltage supplied from a source side liquid crystal device driving circuit is charged through a wiring conductor on the liquid crystal display panel, to a thin film transistor associated with a corresponding pixel on the liquid crystal display panel, during one horizontal scan period T 0 . 
     For example, if the data latched in the 5-bit latches 21a to 21k in response to the latch pulse Vr is (D M3 , D M2 , D M1 , D M0 , D H0 )=(0, 0, 0, 0, 1), when the output voltage interpolating input Vh is &#34;0&#34;, the transfer gate TG 0  is selected in accordance with FIG. 7, so that V 0  is outputted, and the display panel is charged V 0  during a first partial period T 1  of the horizontal scan period T 0 . 
     Next, when the output voltage interpolating input Vh becomes &#34;1&#34;, the transfer gates TG 0  and TG 1  are selected in accordance with FIG. 7, so that the voltage of (V 0  +V 1 )/2 is outputted, and the display panel is charged from V 0  to (V 0  +V 1 )/2 during a second and final partial period T 2  of the horizontal scan period T 0 . In this case, assuming that the voltage before the charging is V 16 , the voltage is required to change over a full swing range between V 0  and V 16 , and therefore, a sufficient time period T 1  is required to change over the full swing range. During the time period T 2 , it is sufficient if the voltage changes only from V 0  to (V 0  +V 1 )/2, namely, over 1/32 of the full swing range. Accordingly, the time period T 2  can be sufficiently shortened in comparison with the times T 0  and T 1 . 
     For example, it is assumed that the time constant for charging the liquid crystal display panel is T 0  /6. Also assuming that the full swing range is 5 V, an error rate of the charged voltage in the charging over the period T 0  is about 0.3%, namely 15 mV. Here, if the voltage interval of one gray scale level, namely 5 V/32 (=0.15 V) is charged during a period T 0  /3 under the same charging time constant, the error rate of the charged voltage is about 13%, namely, about 20 mV. Accordingly, the time period T 1  and T 2  can be made to 2T 0  /3 and T 0  /3, respectively. 
     In the above mentioned operation, the period in which two transfer gates of the transfer gates TG 0  to TG 16  are simultaneously in the on condition, is the period T 2 . Accordingly, the time period in which the two transfer gates are simultaneously turned on so that the current flows through the gray scale level voltage supplies and therefore the electric power is consumed, is shortened to 1/3. If the time constant for charging the liquid crystal display panel is extremely smaller than the time period T 0 , or if the number of gray scale levels is increased so as to make the voltage interval of each one gray scale level further small, the period of T2 can be further made small, and therefore, the averaged current of the gray scale level voltage supplies can correspondingly further be reduced. 
     Incidentally, it is a matter of course that when the sub bit D H0  is &#34;0&#34;, no current flows through the gray scale level voltage supplies. It is sufficient if the output voltage interpolating input Vh is optimized in correspondence with the characteristics of the liquid crystal display panel. 
     Now, referring to FIG. 9, explanation will be made on a second embodiment of the liquid crystal device driving circuit in accordance with the present invention, which is configured to reduce the current of the gray scale level voltage supplies in accordance with the principle of the tint embodiment, and which can obtain a multiple gray scale increased by one bit, with the same number of external gray scale level voltage supplies. Namely, the image input data is increased from 5 bits to 6 bits, and the gray scale levels of 2 6  =64 are generated with the same number (17) of external gray scale level voltage supplies. 
     Similarly to the first embodiment, the four most significant bits D M3  to D M0  of the 6-bit image input data are called the &#34;main bits&#34;, and the two least significant bits D H1  to D H0  of the 6-bit image input data are called the &#34;sub bits&#34;. 
     The shown drive circuit includes &#34;k&#34; stages of 6-bit shift registers 28a to 28k receiving an image input data from an image data input terminal 7, a corresponding number of 6-bit latches 29a to 29k each for latching the 6-bit data of a corresponding one of the 6-bit shift registers 28a to 28k, and a number of AND gates AND1a to AND1k and AND0a to AND0k for controlling the output of the interpolating bits on the basis of an output voltage interpolating input Vh, and a number of output circuits 26a to 26k each receiving external gray scale level voltages V R0 . V R1 , . . . , V R16  for generating voltages of 64 gray scale levels. 
     Each of the output circuits 26a to 26k has a construction as shown in FIG. 10. Each gray scale level voltages V Rn  is connected to one end of a main transfer gate TGMn and one end of a sub transfer gate TGHn in parallel, and the other end of all the transfer gates are connected in common to an output terminal OUT (T 1  to T k ). FIG. 11 shows an detailed logic circuit of the transfer gate used as the main transfer gate TGMn and the sub transfer gate TGHn. One N-channel transistor NMOS and a P-channel transistor PMOS are connected in parallel to each other between an input &#34;I&#34; and an output &#34;O&#34;, and a gate signal G is supplied to a gate of the N-channel transistor NMOS and through an inverter INV to a gate of the P-channel transistor PMOS. Thus, when the gate signal G is at a high level, both of the N-channel transistor NMOS and the P-channel transistor PMOS are turned on, namely, the transfer gate is turned on. When the gate signal G is at a low level, both of the N-channel transistor NMOS and the P-channel transistor PMOS are turned off, namely, the transfer gate is turned off. 
     The main transfer gates TGM 0  to TGM 16  and the sub transfer gates TGH 0  to TGH 16  are on-off controlled by a selector circuit 25. FIG. 12 shows a detailed block diagram of the selector circuit 25. The selector circuit 25 includes a decoder 24 receiving the main bits D M3  to D M0  for generating 16 selection signals OM 15  to OM 0 , similarly to the first embodiment, and control circuits SEL 0  to SEL 16  which correspond To the control circuits SE 0  to SE 16  of the first embodiment, but which receive the sub bits D H1  and D H0 . A specific circuit of each of the control circuits SEL 0  to SEL 16  which is shown in FIG. 13, and its truth table is shown in FIG. 14. Each of the control circuits SEL 0  to SEL 16  includes three OR gates OR 1 , OR 2  and OR 3 , three AND gates AND 1 , AND 2  and AND 3  and one NAND gate NAND 1 , connected as shown in FIG. 13. 
     First, operation of the output circuits 26a to 26k will be described. All the main transfer gates TGM 0  to TGM 16  and all the sub transfer gates TGH 0  to TGH 16  have the same on-resistance, respectively. For example, this can be realized if all the transfer gates have the same construction and the same size when the liquid crystal device driving circuit is implemented on a silicon substrate. 
     A ratio between the on-resistance of the main transfer gates TGM 0  to TGM 16  and the on-resistance of the sub transfer gates TGH 0  to TGH 16  is set to be 1:2. At this time, if the sub bits (D H1 , D H0 )=(0, 0), the output TGHn of the control circuits SEL 0  to SEL 16  are &#34;0&#34;, and the output TGMn is Mn, as will be understood from the truth table of FIG. 14. Therefore, only one transfer gate TGMn selected in accordance with the content of the main bits D M3  to D M0  is selected, so that Vn is outputted from the output OUT. An equivalent circuit of the output circuit in this condition is shown in FIG. 15. In FIG. 15 and in succeeding FIGS. 16 to 18, the resistance value &#34;R&#34; shows the on-resistance of the main transfer gates TGM 0  to TG M16  and the resistance value &#34;2R&#34; shows the on-resistance of the sub transfer gates TGH 0  to TGH 16 . 
     Next, function of the sub bits D H1  and D H0  will be described. Firstly, assume that the output OMn of the decoder 24 is selected or activated in accordance with the content of the main bits D M3  to D M0 . At this time, if the sub bits (D H1 , D H0 )=(0, 1), the outputs TGMn and TGHn of the control circuit SEL n  are selected, and also, the output TGH.sub.(n+1) of the control circuit SEL.sub.(n+1) is selected, as will be understood from the truth table of FIG. 14. At this time, an equivalent circuit of the output circuit becomes as shown in FIG. 16. Namely, the output voltage of {3 V n  +V.sub.(n+1) }/4 is outputted. 
     If the sub bits (D H1 , D H0 )=(1, 0), the outputs TGMn and TGHn of the control circuit SEL n  are selected, and also, the outputs TGM.sub.(n+1) and TGH.sub.(n+1) of the control circuit SEL.sub.(n+1) are selected, as will be understood from the truth table of FIG. 14. In this condition, an equivalent circuit of the output circuit becomes as shown in FIG. 17. Namely, the output voltage of {V n  +V.sub.(n+1) }/2 is outputted. 
     If the sub bits (D H1 , D H0 )=(1, 1), the output TGHn of the control circuit SEL n  is selected, and also, the outputs TGM.sub.(n+1) and TGH.sub.(n+1) of the control circuit SEL.sub.(n+1) are selected, as will be understood from the truth table of FIG. 14. At this time, an equivalent circuit of the output circuit becomes as shown in FIG. 18. Namely, the output voltage of {V n  +3 V.sub.(n+1) }/4 is outputted. 
     As mentioned above, a multiple of different voltages can be generated by connecting the main transfer gates TGM 0  to TGM 16  and the sub transfer gates TGH 0  to TGH 16  in parallel to the gray scale level voltage supplies, and by turning on these transfer gates in various different combinations. 
     Now, the overall operation of the second embodiment of the liquid crystal device driving circuit will be described. Similarly to the first embodiment, the image input data D M3  to D M0  and D H1  and D H0  are transferred through the 6-bit shift registers 28a to 28k, and then latched into the 6-bit latches 29a to 29k in response to the latch pulse Vr. In addition, the AND gates AND 0a  to AND 0k  and AND 1a  to AND 1k  are controlled by the output voltage interpolating input Vh, so as to control application of the sub bits D H1  and D H0  to the output circuit. Thus, the relation between the image data and the output voltage as shown in the tables of FIGS. 19 and 20 can be obtained. Accordingly, operation similarly to the first embodiment can be performed, and the average current flowing through the gray scale level voltage supplied can be effectively reduced. On the other hand, if the number of the transfer gates is increased, it is possible to increase the number of gray scale level voltages. 
     The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.