Abstract:
In a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and connected to the well, so as to fix a voltage at the well.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor device such as a CMOS-type static random access memory (SRAM) device.  
           [0003]    2. Description of the Related Art  
           [0004]    Generally, one SRAM cell uses a flip-flop constructed by two cross-coupled inverters and two transfer transistors. In this case, each of the inverters has a load element and a drive transistor.  
           [0005]    In view of the power consumption, a CMOS-type SRAM cell has been developed where the above-mentioned load element is constructed by a P-channel MOS transistor, while the above-mentioned drive transistor is constructed by an N-channel MOS transistor. This will be explained later in detail.  
           [0006]    In the prior art CMOS-type SRAM cell, however, since the voltage -at a well is not surely fixed to a definite voltage within the cell, a latch-up phenomenon may occur. In order to suppress or avoid such a latch-up phenomenon, the P-type impurity regions of an N-type well have to be sufficiently separated from the N-type impurity regions of a P-type well, which would reduce the integration density.  
         SUMMARY OF THE INVENTION  
         [0007]    It is an object of the present invention to provide a semiconductor device such as a CMOS-type SRAM device capable of suppressing or avoiding a latch-up phenomenon.  
           [0008]    According to the present invention, in a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and is connected to the well, so as to fix a voltage at the well. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:  
         [0010]    [0010]FIG. 1 is an equivalent circuit diagram illustrating a prior art CMOS-type SRAM cell;  
         [0011]    [0011]FIG. 2A is a plan view of the CMOS-type SRAM cell of FIG.  
         [0012]    [0012]FIG. 2B is a cross-sectional view taken along the line II-II of FIG. 2A;  
         [0013]    [0013]FIGS. 3A through 9A are plan views for explaining an embodiment of the method for manufacturing a CMOS-type SRAM cell according to the present invention;  
         [0014]    [0014]FIGS. 3B through 9B are cross-sectional views of FIGS. 3A through 9A, respectively; and  
         [0015]    [0015]FIGS. 10A and 10B are plan and cross-sectional views illustrating modifications of FIGS. 8A and 8B, respectively. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0016]    Before the description of the preferred embodiment, a prior art CMOS-type SRAM cell will be explained with reference to FIGS. 1, 2A and  2 B.  
         [0017]    In FIG. 1, which is an equivalent circuit diagram illustrating the prior art CMOS-type SRAM cell, one SRAM cell is provided at each intersection between a word line WL and complementary bit lines BL 1  and BL 2 . The SRAM cell is constructed by a flip-flop formed by two cross-coupled inverters and transfer N-channel MOS transistors Q t1  and Q t2  connected between nodes N 1  and N 2  Of the flip-flop and the bit lines BL 1  and BL 2 . The transfer transistors Q t1  and Q t2  are controlled by the voltage at the word line WL.  
         [0018]    Each of the inverters is constructed by a load P-channel MOS transistor Q p1 (Q p2 ) and a drive N-channel MOS transistor Q n1 (Q n2 ) between a high power supply line V dd  and a low power supply line V ss . The node N 2  is connected to the gates of the transistors Q p1  and Q n1 , so that the inverter formed by the transistors Q p1  and Q n1  is driven by the voltage at the node N 2 . Similarly, the node N 1  is connected to the gates of the transistors Q p2  and Q n2 , so that the inverter formed by the transistors Q p2  and Q n2  is driven by the voltage at the node N 1 .  
         [0019]    [0019]FIG. 2A is a plan view of the two CMOS-type SRAM cells of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line II-II of FIG. 2A in which two CMOS-type SRAM cells are illustrated by solid-dotted lines.  
         [0020]    In FIGS. 2A and 2B, reference numeral  1  designates a monocrystalline silicon substrate on which a P-type well  3  and an N-type well  4  are formed.  
         [0021]    Also, a thick field silicon oxide layer  2  is formed on the P-type well  3  and the N-type well  4  to isolate active areas where MOS transistors will be formed.  
         [0022]    Further, a gate electrode layer  5  serving as gates of the transistors Q t1 , Q t2 , Q p1 , Q p2 , Q n1  and Q n2  as well as the word line WL of FIG. 1 is formed.  
         [0023]    Additionally, N + -type impurity diffusion regions  6  are formed in the active areas of the P-type well  3 , and P + -type impurity diffusion regions  7  are formed in the active areas of the N-type well  4 . Also, an insulating layer  8  is formed on the entire surface.  
         [0024]    Also, contact holes CONT 1  are perforated in the insulating layer  8 , and metal plugs  91  are buried in the contact holes CONT 1 .  
         [0025]    Further, conductive layers  10   a ,  10   b ,  10   c ,  10   d ,  10   e  and  10   f  are formed. In this case, the conductive layers  10   a  and  10   b  are connected to the low power supply line V ss  and the high power supply line V dd , respectively, of FIG. 1, and the conductive layers  10   c  and  10   d  serve as the nodes N 1  and N 2 , respectively, of FIG. 1. Also, the conductive layers  10   e  and  10   f  are connected to the bit lines BL 1  and BL 2 , respectively, of FIG. 1. Further, an insulating layer  11  is formed on the entire surface.  
         [0026]    In the CMOS-type SRAM cell of FIGS. 2A and 2B, however, since the P-type well  2  is not connected to a region of the low power supply line V ss  within the SRAM cell, the voltage at the P-type well  2  is not surely fixed to the low power supply voltage, so that the resistance of the P-type well  2  would increase the voltage at the P-type well  2 , thus inviting a latch-up phenomenon.  
         [0027]    An embodiment of the method for manufacturing a CMOS-type SRAM cell according to the present invention will be explained next with reference to FIGS. 3A, 3B,  4 A,  4 B,  5 A,  5 B,  6 A,  6 B,  7 A,  7 B,  8 A,  8 B,  9 A and  9 B in which two CMOS-type SRAM cells are illustrated by solid-dotted lines.  
         [0028]    First, referring to FIGS.  3 A and FIG. 3B which is a cross-sectional view taken along the line III-III of FIG. 3A, a thick field silicon oxide layer  2  is formed on a P-type or N-typemonocrystalline silicon substrate  1  by a shallow trench isolation (STI) process. Note that the STI process includes the steps of forming a silicon nitride pattern, etching the silicon substrate  1  using the silicon nitride pattern as a mask, depositing a silicon oxide layer on the entire surface by a chemical vapor deposition (CVD) process, and performing a chemical mechanical polishing (CMP) process upon the silicon oxide layer and the silicon nitride layer to obtain the thick field silicon oxide layer  2 . However, the thick field silicon oxide layer  2  can be formed by a local oxidation of silicon (LOCOS) process or an improved LOCOS process. Thus, active areas indicated by shaded portions are surrounded, i.e., isolated by the thick field silicon oxide layer  2 .  
         [0029]    Next, referring to FIG. 4A and FIG. 4B which is a cross-sectional view taken along the line IV-IV of FIG. 4A, a P-type well  3  and an N-type well  4  are formed by implanting impurities into the monocrystalline silicon substrate  1 . Then, an about 1 to 20 nm thick gate insulating layer (not shown) made of silicon oxide or silicon nitride oxide is deposited on the active areas.  
         [0030]    Next, referring to FIG. 5A and FIG. 5B which is a cross-sectional view taken along the line V-V of FIG. 5A, a gate electrode layer  5  made of polycrystalline silicon or polycide (refractory metal/polycrystalline silicon) is formed by a CVD or sputtering process and a photolithography and etching process. The gate electrode layer  5  serves as gates of the transistors Q t1 , Q t2 , Q p1 , Q p2 , Q n1  and Q n2  as well as the word line WL of FIG. 1.  
         [0031]    Next, referring to FIG. 6A and FIG. 6B which is a cross-sectional view taken along the line VI-VI of FIG. 6A, N-type impurities such as arsenic ions are implanted into the P-type well  3  by using the gate electrode layer  5  as a mask, to form N + -type impurity diffusion regions  6  within the P-type well  3 . Thus, N-channel MOS transistors Q +1 , Q +2 , Q n1  and Q n2  are formed. Similarly, P-type impurities such as boron ions are implanted into the N-type well  4  by using the gate electrode layer  5  as a mask, to form P + -type impurity diffusion regions  7  within the N-type well  4 . Thus, P-channel MOS transistors Q p1  and Q p2  are formed. Then, an insulating layer  8  is formed on the entire surface by a CVD process.  
         [0032]    Next, referring to FIG. 7A and FIG. 7B which is a cross-sectional view taken along the line VII-VII of FIG. 7A, contact holes CONT 1  are perforated in the insulating layer  8 , and contact holes CONT 2  are perforated in the insulating layer  8  as well as the thick field silicon oxide layer  4 . Note that the contact holes CONT 1  and CONT 2  are formed individually or simultaneously. Then, metal plugs  91  and  92  are buried in the contact holes CONT 1  and CONT 2 , respectively.  
         [0033]    Next, referring to FIG. 8A and FIG. 8B which is a cross-sectional view taken along the line IIX-IIX of FIG. 8A, conductive layers  10   a ,  10   b ,  10   c  and  10   d  made of aluminum alloy, refractory metal such as W and W/Ti, or metal/refractory metal such as Cu/Ti are formed by a sputtering process and a photolithography and etching process. In this case, the conductive layers  10   a  and  10   b  are connected to the low power supply line V ss  and the high power supply line V dd , respectively (see FIG. 1). Also, the conductive layers  10   c  and  10   d  serve as the nodes N 1  and N 2 , respectively (see FIG. 1). Further, the conductive layers  10   e  and  10   f  are connected to the bit lines BL 1  and BL 2 , respectively (see FIG. 1). Then, an insulating layer  11  is formed on the entire surface by a CVD process.  
         [0034]    Finally, referring to FIG. 9A and FIG. 9B which is a cross-sectional view taken along the line IX-IX of FIG. 9A, via holes VH are perforated in the insulating layer  12 . Then, metal plugs  12  are buried in the via holes VH. Then, conductive layers  13   a ,  13   b ,  13   c  and  13   d  made of aluminum alloy, refractory metal such as W and W/Ti, or metal/refractory metal such as Cu/Ti are formed by a sputtering process and a photolithography and etching process. In this case, the conductive layers  13   a  and  13   b  serve as the low power supply line V ss  and the high power supply line V dd , respectively (see FIG. 1). Also, the conductive layers  13   c  and  13   d  serve as the bit lines BL 1  and BL 2 , respectively (see FIG. 1). Then, a passivation layer (not shown) is formed on the entire surface, thus completing the SRAM cells.  
         [0035]    In the above-described embodiment, since the P-type well  3  is connected via the metal plug  92  through the thick field insulating layer  2  as well as the insulating layer  8  to the conductive layer  10   a  having a low power supply voltage, the voltage at the P-type well  3  is surely fixed to the low power supply voltage, so that the fluctuation of the voltage at the P-type well can be suppressed, which would avoid the latch-up phenomenon.  
         [0036]    In the above-described embodiment, although the metal plugs  92  buried in the contact hole CONT 2  are provided between the two word lines WL, the metal plugs  92  (the contact holes CONT 2 ) can be provided between the word line WL and the N + -type impurity diffusion region  6  as illustrated in FIGS. 10A and 10B.  
         [0037]    In the above-described embodiment, since use is made of the same photomask for the contact holes CONT 1  and CONT 2 , the additional manufacturing cost is unnecessary.  
         [0038]    As explained hereinabove, the latch-up phenomenon can be suppressed or avoided. Also, since the suppression of the latch-up phenomenon can reduce the spacing between the N + -type impurity diffusion regions and the P + -type diffusion regions, the integration density can be enhanced.