Abstract:
A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Description:
This application is a divisional of Ser. No. 09/638,326, filed Aug. 14, 2000 and claims priority of Provisional Application No. 60/151,244, filed Aug. 27, 1999. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     This invention is related in general to the field of electrical and electronic circuits, and more particularly, to a supply voltage reference circuit. 
     BACKGROUND OF THE INVENTION 
     V DD  reference circuits supply a reference voltage to other circuits in a system. A V DD  reference circuit is sometimes required to be overvoltage tolerant and have minimum I off  current. Overvoltage is a condition that occurs when the output pin of the V DD  reference circuit is pulled a threshold voltage (V DD ) above the V DD . I off  refers to the maximum leakage current that flows into or out of the input or output nodes when the input or output is forced to a given DC voltage when V DD  is zero. However, conventional V DD  reference circuits, although satisfying these requirements, suffer from the disadvantage of always supplying a smaller V DD  voltage during normal circuit operations. The decreased V DD  is caused by the large voltage drop across the blocking diode. As the voltage level of V DD  becomes smaller, the voltage drop across the blocking diode becomes a more significant factor leading to reduced speed of circuit devices. Conventional V DD  reference circuits are also disadvantageous due to the use of a schottky diode that is typically coupled in parallel with the blocking diode. Schottky diodes are undesirable because they are typically leaky by nature. 
     SUMMARY OF THE INVENTION 
     It has been recognized that it is desirable to provide a supply reference voltage circuit that satisfies I off  and overvoltage tolerance requirements, as well as bypasses the current blocking diode during normal operations. 
     In one aspect of the invention, a supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node. 
     In another aspect of the invention, a supply reference voltage circuit generates a stable supply reference voltage from a supply voltage. The circuit includes a blocking diode coupled between the supply voltage and the supply reference voltage, and an output node. The circuit further includes a first circuit coupled to the output node, the supply voltage and the supply reference voltage and operable to prevent current flow through an output device coupled to the output node in response to sensing a low supply voltage level and a non-zero output voltage level. The first circuit further operable to connect the output node to the supply reference voltage in response to the voltage at the output node being a threshold voltage above the supply voltage level. The circuit further includes a second circuit coupled to the supply voltage and the supply reference voltage operable to connect the supply reference voltage to the supply voltage and bypass the blocking diode in response to sensing a high supply voltage level. 
     In yet another aspect of the invention, a method of providing a supply reference voltage includes the steps of turning off an output transistor in response to sensing a non-zero voltage level at the output node and a zero supply voltage level, connecting the supply reference voltage to the voltage at an output node coupled to the output transistor in response to sensing the voltage at the output node being a threshold voltage above the supply voltage level, and also providing a path from a supply voltage to the supply reference voltage and thereby bypassing a current blocking diode coupled between the supply voltage and the supply reference voltage. 
     One technical advantage of the invention is the reduction of I off , satisfying overvoltage tolerance requirements, as well as bypassing the blocking diode to provide the full potential of V DD . 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the present invention, reference may be made to the accompanying drawings, in which: 
     The FIGURE is a circuit diagram of an embodiment of a V DD  reference circuit  10  with a conventional pre-driver and output circuit  12 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to the FIGURE, a circuit diagram of an embodiment of a V DD  reference circuit  10  with a conventional pre-driver and output circuit  12  is shown. V DD  reference circuit includes a blocking diode  16  coupled between a supply voltage, such as V DD , and the V DD  reference voltage node (V DDREF ). A p-channel field effect transistor  18  is coupled in parallel with blocking diode  16  with its backgate and drain coupled to the V DD  reference voltage, and its gate coupled to the source of a p-channel field effect transistor  28  and the source of an n-channel field effect transistor  22  (node  24 ). The gate of p-channel field effect transistor  28  is coupled to the supply voltage and its backgate and drain are both coupled to the V DD  reference voltage. The gate of n-channel field effect transistor  22  is coupled to the output of an inverter  20 , which has its input coupled to the source of an n-channel field effect transistor  32 . The drain of n-channel field effect transistor  22  is coupled to the output (node  27 ) of another inverter  26 , the input of which is coupled to the supply voltage. 
     N-channel field effect transistor  32  is coupled in parallel with a p-channel field effect transistor  34  between node  30  at the input of inverter  20  and an output node  38 . The gate terminals of both transistors  32  and  34  are coupled to the supply voltage. The backgate of transistor  34  is coupled to the V DD  reference voltage. A p-channel field effect transistor  36  is further coupled between node  24  and output node  38  with its backgate coupled to the V DD  reference voltage. 
     Pre-driver and output circuit  12  is shown with V DD  reference circuit  10  of the present invention, so that its operations may be described in detail. Pre-driver and output circuit  12  is a conventional circuit commonly used in combination with V DD  reference circuits. Pre-driver and output circuit  12  includes a NAND gate comprised of parallel p-channel field effect transistors  42  and  44  coupled in series with n-channel field effect transistors  48  and  50 . The source terminals of transistors  42  and  44  are coupled to the V DD  reference voltage node. The gate terminals of transistors  44  and  48  are both coupled to an input node  14 , and the gate terminals of transistors  42  and  50  are coupled to node  40 . Node  40  is at the output of an inverter  52 , which receives a tri-state input  53  at its input. The output from the NAND gate is coupled to the gate terminal of an UOP (upper output) p-channel field effect transistor  46 . The source of UOP transistor  46  is coupled to the supply voltage and its drain is coupled to output node  38 . The backgate of UOP transistor  46  is coupled to the V DD  reference voltage node. 
     Pre-driver and output circuit  12  further includes a NOR gate comprised of series p-channel field effect transistors  54  and  56  coupled to parallel n-channel field effect transistors  58  and  60 . The gate terminals of p-channel field effect transistor  54  and n-channel field effect transistor  60  are coupled to tri-state input node  53 , and the gate terminals of p-channel field effect transistor  56  and n-channel field effect transistor  58  are coupled to input node  14 . The output of the NOR gate is coupled to the gate of an LOP (lower output) n-channel field effect transistor  62 . A ballast or resistive element  64  is coupled between the drain of UOP transistor  46  and the drain of LOP transistor  62 . This resistive element  64  is used to protect the LOP (transistor  62 ) from a electro-static discharge (ESD). 
     In operation, V DD  reference circuit of the present invention reduces I off , satisfies overvoltage tolerance specifications, and bypasses the blocking diode. 
     I off  is the maximum leakage current into or out of the input and output transistors when the input or output is forced to a given DC voltage, such as 5 V, when the V DD  voltage level is zero. For example, the I off  condition may occur when a circuit card is inserted into an already powered up backplane or if a card is powered down. When V DD  voltage is zero, n-channel field effect transistor  32  is in the “OFF” condition, and p-channel field effect transistors  34  and  36  are in the “ON” condition. With transistor  34  “ON”, output node  38  is shorted to node  30 . With transistor  36  “ON”, output node  38  is also shorted to node  24 . When a given DC voltage is applied to output node  38 , node  30  is forced “HIGH.” This “HIGH” voltage level is inverted by inverter  20 , and shows up as a “LOW” voltage level at the gate of n-channel field effect transistor  22 . n-channel field effect transistor  22  is therefore “OFF.” With node  24  “HIGH,” p-channel field effect transistor  18  is in the “OFF” condition. P-channel field effect transistor  28  is in the “ON” condition because of the “LOW” voltage level at its gate terminal. In this manner, the voltage level at node  24  is transmitted to the V DD  reference voltage node. Therefore, the V DD  reference voltage tracks the given DC voltage applied to output node  38 . The “HIGH” signal applied at output node  38  is thus supplied to the gate of p-channel UOP transistor  46  and to the backgate thereof through p-channel transistor  44  to ensure that it is in the “OFF” condition. In this manner, I off  current through UOP transistor  46  is substantially reduced. 
     The overvoltage condition occurs when the voltage level on the disabled output node is pulled a threshold voltage (V DD ) above V DD . When this happens, p-channel field effect transistors  34  and  36  are in the “ON” condition. P-channel field effect transistor  34  thus shorts node  30  with the “HIGH” output node voltage. With node  30  “HIGH,” the voltage level at the gate of n-channel field effect transistor  22  is “LOW,” thus turning it off. Control of node  24  is therefore given to output node  38  via p-channel field effect transistor  36 , which is “ON”. The “HIGH” voltage level at output node  38  ensures that p-channel field effect transistor  18  is in the “OFF” condition so that the risk of current sink to the V DD  reference node through transistor  18  is eliminated. Further, with the voltage level at output node  38  at V DD +V t , p-channel field effect transistor  28  is in the “ON” condition and the voltage level at the V DD  reference node will therefore track the voltage at output node  38 . Both p-channel field effect transistors  28  and  36  supply the output node voltage to the backgate of UOP transistor  46  and clamp the backgate-drain thereof. P-channel field effect transistors  28  and  36  also supply the output node voltage level to the backgate and source terminals of p-channel field effect transistors  42  and  44 , which help to clamp the gate-drain of UOP transistor  46  before it can turn on and sink current into the V DD  reference voltage node. 
     During normal circuit operations, blocking diode  16  is bypassed to supply a stable V DD  reference voltage at the backgate of UOP transistor  46  and the backgates and sources of pre-driver p-channel field effect transistors  42  and  44 . The advantage is increased circuit speed because the V DD  reference voltage is not decreased by the voltage drop across block diode  16 . Under normal operations, transistors  34 ,  36  and  28  are in the “OFF” condition. Inverter  26  applies a “LOW” voltage level to the gate of p-channel field effect transistor  18  through n-channel field effect transistor  22 . Thus, V DD  is supplied to the V DD  reference voltage node through p-channel field effect transistor  18  and bypassing current blocking diode  16 . 
     The present invention provides a V DD  reference circuit that satisfies I off  and overvoltage operating requirements and further bypasses the current blocking diode to supply the full potential of V DD  to the V DD  reference voltage node. The speed of the circuit devices are therefore improved. 
     Modifications to the circuit provided herein are possible without departing from the scope of the present invention. For example, the use of n-channel and p-channel field effect devices may be interchanged provided that the gate voltages are accordingly modified. Other circuit components or transistor technologies may be used according to circuit applications. The presentation of the specific embodiment shown in the FIGURE is solely for the purpose of teaching important technical advantages of the present invention and should not be construed to limit the scope of the present invention. 
     Although several embodiments of the present, invention and its advantages have been described in detail, it should be understood that mutations, changes, substitutions, transformations, modifications, variations, and alterations can be made therein without departing from the teachings of the present invention, the spirit and scope of the invention being set forth by the appended claims.