Abstract:
The present invention is an isolation trench with an insulator, and a method of forming the same using self-aligned processing techniques. The method is implemented with a single mask. A shallow trench is first formed with the mask. Subsequently, the deep trench is formed in self-alignment to the shallow trench. The shallow and deep trenches are filled with insulators. The deep trench diminishes the effects of undesirable inter-device affects, such as leakage current and latch-up. As a result, substrates can be fabricated with high device density.

Description:
This application is a Div of Ser. No. 08/918,566 filed Aug. 22, 1997. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to isolating devices on an integrated circuit, and more specifically to isolating the devices with isolation trenches. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits are often fabricated with multiple devices, such as transistors. To minimize integrated circuit size, and hence integrated circuit cost, these devices are often positioned in close proximity to one another. As a result, undesirable inter-device effects can arise. For example, undesired current can leak between devices. Alternatively, a device such as a transistor can switch on as a result of positive feedback between proximate devices. This effect is known as latch-up. Leakage current and latch-up are understood by persons skilled in the art. 
     To diminish these unwanted inter-device effects, it is desirable to adequately isolate proximate devices. Conventionally, inter-device isolation is accomplished by creating a field oxide between the devices. The field oxide is an electrical insulator. Thus, proximate devices are substantially electrically isolated if the field oxide has adequate dimensions including height, length, and width. However, if the field oxide dimensions are too small, leakage current and latch-up may result. 
     For example, the undesired inter-device effects may arise if a parasitic metal-oxide-semiconductor field effect transistor (MOSFET) is created between two adjacent devices. FIG. 1 illustrates one embodiment of a parasitic MOSFET  10  on an integrated circuit formed by a conductor  12 , active areas  14 , and a field oxide  16 . The integrated circuit may be a memory, which contains memory cells and complementary MOSFETS. The active areas may be the source and the drain of memory cells or MOSFETs. The conductor  12  may be a wordline of the flash memory. The design and operation of flash memory are known by persons skilled in the art. 
     The structure of the parasitic MOSFET  10  is now described. The parasitic MOSFET  10  is unintentionally formed by elements of surrounding devices. The conductor  12  and the field oxide  16  function as a gate of the parasitic MOSFET  10 . The active areas  14  serve as the source and drain of the parasitic MOSFET  10 . Although it is not constructed like a conventional transistor, the parasitic MOSFET  10 , nevertheless, may function like one if the field oxide  16  has sufficiently small dimensions. As a result, operation of the parasitic MOSFET  10  may cause undesirable leakage current and latch-up in surrounding devices. Therefore, it is necessary to maintain adequate field oxide  16  dimensions. 
     Methods of improving device isolation by enhancing field oxide  16  dimensions have been previously disclosed. U.S. Pat. Nos. 5,358,894 and 5,438,016 teach processes for reducing the thinning of the field oxide  16  thickness by respectively applying an impurity and using protective structures. However, these patents do not recite methods or structures that increase the depth that the field oxide  16  penetrates the substrate  18 , while keeping the lateral encroachment to a minimum to maximize the area available for device fabrication. Many of these approaches also require multiple masking steps which increase processing costs. A process that minimizes the number of processing steps or masking steps is highly desirable. 
     In ULSI, devices will be positioned in closer proximity to one another than is done in very large scale integrated circuits (VLSI). However, with current technology, the field oxide  16  may be insufficiently deep, or in other words, does not penetrate sufficiently far into the substrate  18 , to isolate the devices. Thus, undesirable leakage current and latch-up may occur in the devices. Therefore, a process and structure for isolating high density devices is necessary. 
     Furthermore, integrated circuits are fabricated with devices having microscopic, such as sub-micron, features that can only be manufactured with critical processing steps. The critical processing steps entail carefully aligning the substrate  18  to equipment used to build the devices. This requires that most processes leave the substrate  18  in a relatively planar configuration. Therefore, an integrated circuit fabrication process that is less sensitive to process variations is desirable. Such a process would permit successful fabrication of integrated circuits, despite minor misalignments. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, there is provided an isolation trench in an integrated circuit, and a method of forming the same using self-aligned processing techniques. The isolation trench is created by first forming a shallow trench defined by a mask. The shallow trench is filled with an insulator, such as an oxide. Then some of the insulator is removed. Next, a deep trench is formed in self alignment between the remaining insulator. 
     In one embodiment, a second oxide is then formed on the integrated circuit. The second oxide is later removed from the shallow trench. Polysilicon is then deposited in the shallow trench. The polysilicon is oxidized and annealed to form field oxide. As a result, the present invention, particularly the deep trench, facilitates enhanced inter-device isolation in high density integrated circuits. Hence, unwanted inter-device effects, such as leakage current and latch-up, are diminished while creating minimal variations in topography. This is desirable for device processing. 
     In another embodiment, nitride is formed on the walls of the shallow trench. As a result, the field oxide will not significantly encroach neighboring active areas. Reduced encroachment increases the amount of area available for fabrication of devices. 
     It is also a feature of the present invention that the field oxide may be formed on the integrated circuit with a flat topography without using planarization techniques, such as chemical-mechanical processing or resist etchback. Furthermore, it is an advantage of the present invention that ion implantation is not required to provide inter-device isolation. 
     Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawings in which the reference number first appears. 
     FIG. 1 is a cross-sectional view of one embodiment of a parasitic metal-oxide-semiconductor field effect transistor; 
     FIG. 2 is a block diagram of one embodiment of an integrated circuit coupled to an external system; 
     FIG. 3 is a block diagram of one embodiment of a memory; 
     FIG.  4 ( a ) is a schematic diagram of one embodiment of a metal-oxide-semiconductor field effect transistor; 
     FIG.  4 ( b ) is a view of one embodiment of a mask; 
     FIG. 5 is a cross-sectional view of one embodiment of an integrated circuit having two adjacent metal-oxide-semiconductor field effect transistors; 
     FIG. 6 is a cross-sectional view of one embodiment of an integrated circuit after the formation of a first insulator on a base layer; 
     FIG.  7 ( a ) is a cross-sectional view of one embodiment of an integrated circuit after patterning masking layer; 
     FIG.  7 ( b ) is a cross-sectional view of one embodiment of an integrated circuit after patterning the first insulator; 
     FIG.  7 ( c ) is a cross-sectional view of a second embodiment of an integrated circuit after patterning masking; 
     FIG. 8 is a cross-sectional view of one embodiment of an integrated circuit after forming a shallow trench and removing the masking layer; 
     FIG. 9 is a cross-sectional view of one embodiment of an integrated circuit after forming second and third insulators; 
     FIG. 10 is a cross-sectional view of one embodiment of an integrated circuit after removing some third insulator; 
     FIG. 11 is a cross-sectional view of one embodiment of the integrated circuit after forming a deep trench; 
     FIG. 12 is a cross-sectional view of one embodiment of the integrated circuit after forming a fourth insulator; 
     FIG. 13 is a cross-sectional view of one embodiment of the integrated circuit after removing some second and fourth insulator; 
     FIG. 14 is a cross-sectional view of one embodiment of the integrated circuit after filling a shallow trench with a semiconductor; 
     FIG. 15 is a cross-sectional view of one embodiment of the integrated circuit after oxidizing the semiconductor; and 
     FIG. 16 is a cross-sectional view of one embodiment of the integrated circuit having deep and shallow isolation trenches. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable persons skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present inventions is defined only by the appended claims. 
     The present invention is directed towards a trench for enhanced inter-device isolation in an integrated circuit, and a method for fabricating the same. The isolation trench is formed by a shallow trench and a deep trench. This goal is achieved by using self-aligned processing techniques which reduce process sensitivity and the number of masks used to fabricate the integrated circuit. In one embodiment, the present invention is used to fabricate an integrated circuit. The integrated circuit  22  may be coupled to an external system  24  as illustrated in FIG.  2 . The integrated circuit  22  and the external system  24  may be, respectively, memory and a microprocessor which, for example, form a computer. Alternatively, the external system  24  may be a microcomputer, cellular telephone, or another form of electronic equipment. Also, the integrated circuit  22  may be a communications transceiver. 
     As stated above, the integrated circuit  22  may be a memory. FIG. 3 illustrates one embodiment of a memory  30 . The memory includes a memory array  38 , control logic  34 , and address logic  36 . The address logic  36  receives an address from the external system  24 . The control logic  34  receives external commands to store and/or retrieve data to or from the memory array  38  at cell location(s) provided to the address logic  36  by the external system  24 . Subsequently, the data associated with the cell location(s) is respectively transmitted to or received from the external system  24 . The memory  30  may be implemented with metal-oxide-semiconductor field effect transistors (MOSFETs)  40 , as shown in FIG.  4 ( a ). A MOSFET  40  includes a gate  42 , a drain  44 , and a source  46 . MOSFETs  40  are often formed in close proximity to one another as illustrated in FIG.  5 . 
     The present invention is used to fabricate an integrated circuit  22 , such as a memory  30 , with a variety of materials and processing steps. The materials and processing steps are known to persons skilled in the art. The following process steps are typically accomplished with only one mask. An exemplary mask  48  is shown in FIG.  4 ( b ). 
     Integrated circuit  22  fabrication may be commenced with the formation of a first insulator  62  on a base layer  64 , such as a substrate, (step  60 ) as shown in FIG.  6 . The first insulator  62  may be nitride, such as silicon nitride. The base layer  64  may be a semiconductor, such as silicon. The use of the first insulator  62  is optional in the present invention. 
     Next, a cross-section of a shallow trench is defined. The cross-section can be defined by patterning a masking layer  72 , such as resist, on the first insulator  62  (step  70 ), as shown in FIG.  7 ( a ). Also, the cross-section can be defined by patterning the first insulator  62  (step  76 ), as shown in FIG.  7 ( b ), with conventional masking and removal techniques. 
     Alternatively, as discussed above, the first insulator  62  may not be formed on the base layer  64 . Thus, the cross section can be defined by patterning the masking layer  72  directly on the base layer  64  (step  78 ), as shown in FIG.  7 ( c ). 
     Next, as illustrated in FIG. 8, a first portion of the integrated circuit  22  is removed to form a shallow trench  82  (step  80 ). The masking layer  72  is then subsequently removed. The first portion may comprise the uncovered base layer  64 . Additionally, the first portion may include the first insulator  62  if a masking layer is patterned on the first insulator  62  (step  70 ). 
     Removal in this step and other succeeding steps is performed by etching, such as wet or dry etching, which is known to persons skilled in the art. If the first insulator  62  is patterned (step  76 ), then the removal step is preferably implemented with a selective etch that does not significantly remove the first insulator  62 . 
     FIG. 8 is illustrative of one embodiment of shallow trench  82  formation when the first insulator  62  is formed on the base layer  64 . The remaining figures also include the optional first insulator  62  for illustrative purposes. Subsequently, as shown in FIG. 9, a second insulator  92  and then a third insulator  94  are formed on the integrated circuit  22  (step  90 ). The second insulator  92  may be a nitride, such as silicon nitride. The second insulator  92  diminishes the encroachment by field oxide into a neighboring active area  14  in the base layer  64 . The use of the second insulator  92  is optional in the present invention. The remaining figures also include the optional second insulator  92  for illustrative purposes. The third insulator  94  may be an oxide, such as silicon dioxide. However, the third insulator  94  can also be polysilicon if desired. 
     Next, as shown in FIG. 10, some third insulator  94  is removed, or faceted, such as by etching (step  100 ) to define a deep trench. The remaining third insulator  94  in the shallow trench  82  permits the deep trench  112  to be formed by removing a second portion of the integrated circuit  22  in self alignment with the shallow trench  82  (step  110 ), as shown in FIG.  11 . Thus, a second mask is not required to create the isolation trench. The deep trench  112  may be formed in the center of the shallow trench  82 . A portion of the base layer  64  and second insulator  92  may be removed to form the shallow trench  82  (step  110 ). 
     A fourth insulator  122  is then formed on the integrated circuit  22  (step  120 ), as shown in FIG.  12 . The fourth insulator  122  may be an oxide such as silicon dioxide. The fourth insulator  122  may include some third insulator  94 . Next, as illustrated in FIG. 13, some fourth insulator  122  and then some second insulator  92  may be removed, such as by etching, from the shallow trench  82  (step  130 ). The portion of the second insulator  92  that is removed is located at the bottom surface of the shallow trench  82  and adjacent to the deep trench  112  (step  130 ). Thus, the second insulator  92  may only remain on the sidewalls of the shallow trench  82 . 
     Next, as shown in FIG. 14, a semiconductor  142 , such as polysilicon, is formed in the shallow trench  82  (step  140 ). The semiconductor  142  may contact the bottom surface of the shallow trench  82 . The semiconductor  142  can partially or completely fill the shallow trench  82 . The semiconductor  142  is then oxidized and converted to a fifth insulator  152 , such as oxidized polysilicon, (step  150 ) as shown in FIG.  15 ( a ). During oxidation (step  150 ), the fifth insulator  152  may also be annealed to improve its isolation properties. After oxidation (step  150 ), the first and second insulators  62 ,  92  on the exposed base layer  64  surface can be optionally removed. 
     The present invention may be incorporated with conventional isolation techniques, such as local oxidation of silicon (LOCOS), which may form shallower trenches. Furthermore, the present invention can be used to implement trenches of varying depths  1602 ,  1604 , as shown in FIG. 16 (step  160 ). 
     Fabrication of the integrated circuit  22  is completed with conventional process steps. These conventional process steps are known by persons skilled in the art. 
     CONCLUSION 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This patent is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.