Abstract:
The present invention discloses a level shift circuit which comprises: a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node; and an output circuit for outputting a signal of one of the second operational voltage levels according to a voltage level switching at the first node.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a level shift circuit, and in particular to a level shift circuit with faster output level switching, and a method for the same. 
         [0003]    2. Description of the Related Art 
         [0004]    A power control circuit chip often requires a level shift circuit to convert one DC voltage level to another. The conversion may increase the voltage difference between the high and low levels, decrease the voltage difference between the high and low levels, or shift the high and low levels to different voltages without changing the voltage difference between them.  FIGS. 1-3  respectively show three examples: 
         [0005]    The circuit of  FIG. 1  converts VS 1 /0V (high/low level of an input signal) to VS 2 /0V (high/low level of an output signal), and usually VS 2 &gt;VS 1 . VS 1  and VS 2  for example may be 1.5V and 3.3V, respectively. Sometimes the circuit is also used in the case where VS 2 &lt;VS 1 . The low level of the input signal and that of the output signal are the same in this circuit. 
         [0006]    The circuit of  FIG. 2  converts VS 1 /0V (high/low level of an input signal) to VS 1 /VG 2  (high/low level of an output signal), wherein 0V&gt;VG 2 , VG 2  being −3.3V, for example. The high level of the input signal and that of the output signal are the same in this circuit. 
         [0007]    The circuit of  FIG. 3  converts VS 1 /0V (high/low level of an input signal) to VS 2 /VG 2  (high/low level of an output signal), wherein VS 2 &gt;VS 1 , and VS 2 &gt;VG 2 . This circuit shifts both the high and low levels, and it can increase or decrease the voltage difference between the high and low levels. VS 1 , VS 2  and VG 2  are, e.g., 1.5V, 3.3V and 1.8V, respectively. The high and low levels of the output signal are both different from that of the input signal in this circuit. 
         [0008]    All the above-mentioned prior art circuits have a common drawback: their output level switching speed is slow. Taking the circuit of  FIG. 1  for example and referring to  FIGS. 4 and 5 , in order to ensure that the driving strength of the NMOS transistors M 3  and M 4  is larger than the driving strength of the corresponding PMOS transistors M 1  and M 2 , in particular when the NMOS transistors M 3  and M 4  are in their worse case and the PMOS transistors M 1  and M 2  in their best case, the width of the NMOS transistors M 3  and M 4  is typically enlarged to increase their driving strength. However, this makes the driving strength of the PMOS transistor M 1  weaker than that of the NMOS transistors M 3 , and the driving strength of the PMOS transistor M 2  weaker than that of the NMOS transistors M 4 , resulting in the waveforms as shown in  FIG. 5 , wherein the time required for the output signal of the level shift circuit to switch from low to high is much slower than the time required to switch from high to low, as referring to the time points T 1 , T 2 , T 3 , and T 4 . 
         [0009]    In the circuit of  FIG. 2 , the input signal IN controls the gates of the upper transistors M 1  and M 2 , and likely, the width of the transistors M 1  and M 2  will also be enlarged to increase their driving strength. As a result, in this level shift circuit, the time required for the output signal to switch from high to low is much slower than the time required to switch from low to high. 
         [0010]    In view of the foregoing drawback, the present invention proposes a level shift circuit, which is capable of speeding up the switching time of the output signal. 
       SUMMARY OF THE INVENTION 
       [0011]    A first objective of the present invention is to provide a level shift circuit with faster output level switching, in which a pulse generator generates a pulse according to the level switching at a node, and the pulse drives a latch circuit to generate the desired output. 
         [0012]    A second objective of the present invention is to provide a level shift circuit which speeds up the output level switching by speeding up the level switching at a node. 
         [0013]    A third objective of the present invention is to provide a method to achieve faster output level switching in a level shift circuit. 
         [0014]    To achieve the foregoing objectives, according to an aspect of the present invention, a level shift circuit comprises: a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node; and an output circuit for outputting a signal of one of the second operational voltage levels according to a voltage level switching at the first node. 
         [0015]    Preferably, the output circuit includes a first pulse generator which generates a first pulse according to the voltage level switching at the first node; and a latch circuit which generates an output according to the generated first pulse. 
         [0016]    According to another aspect of the present invention, a level shift circuit comprises: a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node, and outputs of second high and low operational voltage levels at a second node; a first circuit device electrically connected between a voltage supply of the second high operational voltage and the second node; and a control circuit controlling the first circuit device according to a voltage level switching at the first node, such that current flows from the voltage supply of the second high operational voltage to the second node. 
         [0017]    Preferably, the control circuit includes a first pulse generator for generating a first pulse according to the voltage level switching at the first node; the pulse controls the first circuit device such that current flows from the voltage supply of the second high operational voltage to the second node. 
         [0018]    From yet another aspect of the present invention, a method to achieve faster output level switching in a level shift circuit comprises: providing a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node; generating a pulse according to a voltage level switching at the first node; and generating a signal of one of the second operational voltage levels according to the pulse. 
         [0019]    From a further other aspect of the present invention, a method to achieve faster output level switching in a level shift circuit comprises: providing a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node, and outputs of second high and low operational voltage levels at a second node; generating a pulse according to a voltage level switching at the first node; and increasing current from a voltage supply of the second high operational voltage to the second node according to the pulse. 
         [0020]    For better understanding the objects, characteristics, and effects of the present invention, the present invention will be described below in detail by illustrative embodiments with reference to the attached drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIGS. 1-4  show conventional level shift circuits. 
           [0022]      FIG. 5  shows the waveforms of the conventional level shift circuit of  FIG. 1  during input and output voltage level switching. 
           [0023]      FIG. 6  is a circuit diagram schematically showing a level shift circuit according to an embodiment of the present invention. 
           [0024]      FIG. 7  is a circuit diagram schematically showing a level shift circuit according to another embodiment of the present invention. 
           [0025]      FIG. 8  shows yet another embodiment of the present invention. 
           [0026]      FIG. 9  shows a still other embodiment of the present invention. 
           [0027]      FIG. 10  shows a further other embodiment of the present invention. 
           [0028]      FIG. 9  shows another embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0029]      FIG. 6  schematically shows a first embodiment according to the present invention. As shown in the figure, a level shift circuit comprises a pair of PMOS transistors M 1  and M 2 , and a pair of NMOS transistors M 3  and M 4  (the PMOS and NMOS pairs constituting a basic level shift circuit  10 ). In addition to the above, the level shift circuit according to this embodiment further comprises an output circuit  30 . The output circuit  30  includes pulse generators  31  and  32 , and a latch circuit  33 . The pulse generator  31  generates a pulse according to the falling edge of the signal at the node A. The pulse is received by the set input S of the latch circuit  33  so that the latch circuit  33  outputs a signal of high level. Likely, the pulse generator  32  generates a pulse according to the falling edge of the signal at the node B; the pulse is received by the reset input R of the latch circuit  33  so that the latch circuit  33  outputs a signal of low level. The output circuit  30  operates between a high level which is the second high operational voltage VS 2  and a low level which is 0V, so its output signal has a high level of VS 2  and a low level of 0V, which are exactly the desired signal levels to be shifted to by the level shift circuit. 
         [0030]    Because the high level of the output signal OUT is generated according to the falling edge of the signal at the node A, not according to the rising edge of the signal at the node B, the level switching speed of the present invention is much faster then that in the prior art. According to the simulation by the inventor, the level switching time is reduced to ⅓ or lower. 
         [0031]      FIG. 7  shows a second embodiment of the present invention. As shown in the figure, besides the basic level shift circuit  20 , the level shift circuit further includes an output circuit  40 . The output circuit  40  includes pulse generators  41  and  42 , and a latch circuit  43 . The pulse generator  41  generates a pulse according to the rising edge of the signal at the node A; the pulse is received by the set input S of the latch circuit  43  so that the latch circuit  43  outputs a signal of high level. Likely, the pulse generator  42  generates a pulse according to the rising edge of the signal at the node B; the pulse is received by the reset input R of the latch circuit  43  so that the latch circuit  43  outputs a signal of low level. The output circuit  40  operates between a high level which is the first high operational voltage VS 1  and a low level which is VG 2 , so its output signal has a high level of VS 1  and a low level of VG 2 , which are exactly the desired signal levels to be shifted to by the level shift circuit. 
         [0032]    Similar to the previous embodiment, because the low level of the output signal OUT is generated according to the rising edge of the signal at the node B, not according to the rising edge of the signal at the node A, the level switching speed of the present invention is much faster then that in the prior art. 
         [0033]      FIG. 8  shows a third embodiment of the present invention. The purpose of this circuit is to shift the signal levels from VS 1 /0V to VS 2 /VG 2 . Note that in this embodiment, it does not require two basic level shift circuits (eight transistors) as that shown in  FIG. 3 , but only requires one basic level shift circuit with four transistors (either one of the basic level shift circuits  10  and  20 , shown to be the basic level shift circuit  10  in the figure). The output circuit  50  operates between a high level which is VS 2  and a low level which is VG 2 , so that its output signal has a high level of VS 2  and a low level of VG 2 , which are exactly the desired signal levels to be shifted to by the level shift circuit. 
         [0034]    The embodiments of  FIGS. 6-8  explain the first concept of the present invention, i.e., by the level switching of the voltage signal at a critical node, which is much faster, a pulse is generated to drive a latch circuit, so that an output signal is capable of switching its levels in a much shorter time. 
         [0035]      FIG. 9  shows a fourth embodiment of the present invention. As shown in the figure, the level shift circuit of this embodiment further comprises two PMOS transistors M 11  and M 12  in addition to the basic level shift circuit  10 , and the control circuit  60  includes pulse generators  61  and  62 , but does not include a latch circuit. The pulse generator  61  generates a pulse according to the falling edge of the signal at the node A; the pulse is a negative pulse which controls the gate of the PMOS transistor M 12  so that the PMOS transistor M 12  turns ON. The width of the pulse determines the ON time of the PMOS transistor M 12 , which can be determined according to circuit requirement. The conduction of the transistor M 12  provides a parallel path to the path through the transistor M 2 , so that the current from the second high operational voltage VS 2  to the node B increases, speeding up the level rising of the output node OUT. Similarly, the pulse generator  62  generates a negative pulse according to the falling edge of the signal at the node B; the pulse controls the gate of the PMOS transistor M 11  so that the PMOS transistor M 11  turns ON, to increase the current from the second high operational voltage VS 2  to the node A. In general case, the node A is required for providing an inverse output, so it is preferred that its switching speed is also increased. However, in a certain exception that the inverse output from the node A is not required in the circuit, the transistor M 11  can be omitted. In this embodiment, the node B provides the output OUT, so the high and low operational levels of the control circuit  60  need not be VS 1  and VG 2 ; they are shown as an example. 
         [0036]      FIG. 10  shows a fifth embodiment of the present invention, which is different from the first embodiment in that there are resistors R 1  and R 2  provided above the transistors M 1  and M 2 . The resistors R 1  and R 2  provide voltage drops between the second high operational voltage VS 2  and the transistors M 1  and M 2 , respectively, so that the gate-to-source voltage difference V GS  of the transistors M 1  and M 2  is decreased to reduce the conduction of the transistors M 1  and M 2 . When the current amount increases, the voltage drops generated by the resistors R 1  and R 2  correspondingly increase so that the conduction of the transistors M 1  and M 2  is even weaker, and thus the voltage at the node A (or node B) can be pulled low by the transistors M 3  (or M 4 ) even faster. 
         [0037]      FIG. 10  shows a sixth embodiment of the present invention, which is similar to the previous embodiment; resistors R 3  and R 4  are provided below the transistors M 3  and M 4 , to the gate-to-source voltage difference V GS  of the transistors M 3  and M 4 , so that the voltage at the node A (or node B) can be pulled high even faster. 
         [0038]    The features, characteristics and effects of the present invention have been described with reference to certain embodiments, which are illustrative of the invention and not for limiting of the invention. Various other substitutions and modifications will occur to those skilled in the art, without departing from the spirit of the present invention. For example, in each of the described embodiments, the latch circuit may be replaced by another type of latch circuit, instead of the SR latch. In the embodiment of  FIG. 9 , the negative pulses driving the PMOS transistors M 11  and M 12  may be replaced by positive pulses driving the NMOS transistors. In the embodiments of  FIG. 10-11 , the voltage drop can be achieved by circuit devices other than resistors. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.