Abstract:
A master-slave circuit that includes a master circuit having input data stored therein, a storage unit for receiving the input data in response to receiving a sleep mode setting signal that sets a sleep mode, and for storing the input data, and a first control unit for interrupting the supply of a power supply voltage to the master circuit after the input data is stored in the storage unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of priority from Japanese Patent Application No. 2007-228556 filed on Sep. 4, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The application relates to a master-slave circuit and a method of controlling the master-slave circuit. 
         [0004]    2. Description of the Related Art 
         [0005]    In a D flip-flop circuit, when a power supply voltage is interrupted to achieve low power consumption in order to save power, this power supply voltage interruption causes an inverter in a D flip-flop circuit to become inoperative, causing the data latched in the D flip-flop circuit to be deleted. Therefore, the problem with the D flip-flop circuit is that the latched data has been deleted when the D flip-flop recovers to a non-power-saving state from a power-saving state. 
         [0006]    Japanese Patent Laid-Open Publication No. 1996-191234 discloses a D flip-flop circuit having the following capability. When the D flip-flop circuit becomes inoperative by turning off the power supply, the D flip-flop circuit stores an internal state before turning off the power supply, and then, when the D flip-flop circuit becomes operative by turning on the power supply, the D flip-flop circuit restores the internal state before turning off the power supply. 
         [0007]    The D flip-flop circuit includes a memory circuit equipped with a positive terminal and a negative terminal. In addition, another power supply that is different from a power supply used for master and slave units supplies power to the memory circuit. 
         [0008]    The D flip-flop circuit disconnects a path between the negative terminal in the memory circuit and an input terminal in the master unit and a path between the positive terminal in the memory circuit and the input terminal in the slave unit when the D flip-flop circuit is in a power-saving state. The D flip-flop circuit, on the other hand, disconnects the path between the negative terminal in the memory circuit and the input terminal in the master unit when the master unit and the slave unit are disconnected. 
         [0009]    In a typical master-slave circuit such as the D flip-flop circuit, it is advantageous to interrupt a power supply to a deactivated circuit to achieve low power consumption. However, the master-slave circuit is generally used for storing data. Consequently, when the power supply to the master-slave circuit is interrupted, a voltage that is needed to store data is not supplied to the D flip-flop circuit. For the above reason, it is difficult for the master-slave circuit to satisfy both the low power consumption and data storing capability. 
       SUMMARY OF THE INVENTION 
       [0010]    According to one aspect of an embodiment, a master-slave circuit is provided that includes a master circuit having input data stored therein, a storage unit for receiving the input data in response to receiving a sleep mode setting signal that sets a sleep mode, and for storing the input data, and a first control unit for interrupting the supply of a power supply voltage to the master circuit after the input data is stored in the storage unit. 
         [0011]    Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning by practice of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  shows a circuit diagram of a flip-flop circuit in accordance with a first embodiment; 
           [0013]      FIG. 2  shows a detailed circuit diagram of the flip-flop circuit in accordance with the first embodiment; 
           [0014]      FIG. 3  shows a circuit diagram of a delay control circuit in accordance with the first embodiment; 
           [0015]      FIG. 4  shows a timing chart of the flip-flop circuit in a normal mode in accordance with the first embodiment; 
           [0016]      FIG. 5  shows a timing chart of the flip-flop circuit in a sleep mode in accordance with the first embodiment; 
           [0017]      FIG. 6  shows a circuit diagram of a flip-flop circuit in accordance with a second embodiment; 
           [0018]      FIG. 7  shows a detailed circuit diagram of a part of the flip-flop circuit in accordance with the second embodiment; 
           [0019]      FIG. 8  shows a circuit diagram of a flip-flop circuit in accordance with a third embodiment; 
           [0020]      FIG. 9  shows a block diagram of a flip-flop circuit in accordance with a fourth embodiment; 
           [0021]      FIG. 10  shows a detailed circuit diagram of a part of the flip-flop circuit in accordance with the fourth embodiment; 
           [0022]      FIG. 11  shows a circuit diagram of a slave-side clock generation circuit in accordance with the fourth embodiment; 
           [0023]      FIG. 12  shows a circuit diagram of a scan-side clock generation circuit in accordance with the fourth embodiment; 
           [0024]      FIG. 13  shows a circuit diagram of a master circuit-slave circuit supply voltage control circuit in accordance with the fourth embodiment; 
           [0025]      FIG. 14  shows a timing chart of the flip-flop circuit when the flip-flop circuit shifts to a sleep mode from a normal mode in accordance with the fourth embodiment; 
           [0026]      FIG. 15  shows a timing chart of the flip-flop circuit when the flip-flip circuit shifts to the normal mode from the sleep mode in accordance with the fourth embodiment; 
           [0027]      FIG. 16  shows a circuit diagram of a flip-flop circuit in accordance with a fifth embodiment; 
           [0028]      FIG. 17  shows a circuit diagram of a flip-flop circuit in accordance with a sixth embodiment; and 
           [0029]      FIG. 18  shows a circuit diagram of a flip-flop circuit in accordance with a seventh embodiment invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    A first embodiment will be described with reference to  FIGS. 1 through 5 . A master-slave circuit will be described with reference to a flip-flop circuit  10 .  FIG. 1  shows a circuit diagram of the flip-flop circuit  10 . The flip-flop circuit  10  includes a master circuit  20  and a slave circuit  30 . The master circuit  20  further includes a clock generation circuit  21 , a master circuit supply voltage control circuit  22  and a master latch circuit  23 . The slave circuit  30  includes a signal transfer circuit  31  and a slave latch circuit  32 . 
         [0031]    As shown in  FIG. 2 , the clock generation circuit  21  includes an inverter  21 A, an inverter  21 B, an n-channel transistor M 1 , and a p-channel transistor M 2 . A VDD shown in  FIG. 2  is a power supply line. 
         [0032]    The inverter  21 A includes a p-channel transistor M 11  and an n-channel transistor M 12 . A source of the n-channel transistor M 12  is coupled to a drain of the n-channel transistor M 1 . A ground potential VSS is supplied to a source of the n-channel transistor M 1 . An output A 2  of the inverter  21 A is coupled to an input B 1  of the inverter  21 B. A reference symbol “A1” in  FIG. 2  indicates an input of the inverter  21 A and a reference symbol “B2” indicates an output of the inverter  21 B. 
         [0033]    A drain of the p-channel transistor M 2  is coupled to the input B 1  of the inverter  21 B. The inverter  21 B includes a p-channel transistor M 21  and an n-channel transistor M 22 . 
         [0034]    The master circuit supply voltage control circuit  22  includes a delay control circuit  22 A and a p-channel transistor M 31 . An output of the delay control circuit  22 A is coupled to a gate of the p-channel transistor M 31 . A power supply voltage is supplied to a source of the p-channel transistor M 31  via the power supply line VDD. As shown in  FIG. 3 , in the first embodiment, the delay control circuit  22 A includes an inverter  22 B and an inverter  22 C, which are coupled in a multi-stage manner. 
         [0035]    Returning to  FIG. 2 , the master latch circuit  23  of  FIG. 2  includes an inverter  23 A, an inverter  23 B, a transfer gate  23 C and a transfer gate  23 D. The transfer gate  23 C is coupled to an input C 1  of the inverter  23 A. The inverter  23 A includes a p-channel transistor M 41  and an N type channel transistor M 42 . 
         [0036]    An output C 2  of the inverter  23 A of  FIG. 2  is coupled to an input D 1  of the inverter  23 B. The inverter  23 B of  FIG. 2  includes a p-channel transistor M 51  and an n-channel transistor M 52 . An output D 2  of the inverter  23  B is coupled to an input C 1  of the inverter  23 A via the transfer gate  23 D. 
         [0037]    As shown in  FIG. 2 , the signal transfer circuit  31  in the slave circuit  30  includes a transfer gate  31 A. 
         [0038]    The slave latch circuit  32  of  FIG. 2  includes an inverter  32 A, an inverter  32 B, and a transfer gate  32 C. An input E 1  of the inverter  32 A is coupled to the output C 2  of the inverter  23 A via the signal transfer circuit  31 . The signal transfer circuit  31  is coupled to an output line L 1 . The inverter  32 A includes a p-channel transistor M 61  and an n-channel transistor M 62 . The output line L 1  corresponds to an input data transfer path in the first embodiment. 
         [0039]    An input E 2  of the inverter  32 A of  FIG. 2  is coupled to an output line L 2  and an input F 1  of the inverter  32 B of  FIG. 2 . The inverter  32 B includes a p-channel transistor M 71  and an n-channel transistor M 72 . An output F 2  of the inverter  32 B is coupled to the input E 1  of the inverter  32 A via the transfer gate  32 C. 
         [0040]    Next, operation of the flip-flop circuit  10  according to the first embodiment will be described. One of a normal mode and a sleep mode can be set to the flip-flop circuit  10 . In the sleep mode, the flip-flop circuit  10  steps down a power supply voltage from a power supply voltage in the normal mode without receiving an external signal in order to reduce the power consumption. 
         [0041]    As shown in  FIG. 1 , a clock signal CLK is input to the clock generation circuit  21  in the normal mode. As shown in  FIG. 2 , the clock signal CLK is input to each gate of the transistors M 11  and M 12  of the clock generation circuit  21  via the input A 1  of the inverter  21 A. 
         [0042]    Supplying the clock signal CLK having a low level to each gate of the transistors M 11  and  12  causes the p-channel transistor M 11  to switch to an ‘ON’ state and causes the n-channel transistor M 12  to switch to an ‘OFF’ state. Consequently, the level of an output from the inverter  21 A shifts to a high level, so that the level of a control signal ICKX shifts to a high level in an interval until time T 0  in  FIG. 4 . 
         [0043]    The signal having a high level, which is output from the inverter  21 A of  FIG. 2 , is supplied to each gate in the transistors M 21  and M 22  via the input B 1  of the inverter  21 B of  FIG. 2 . Supplying the output signal having a high level to each gate of the transistors M 21  and M 22  causes the p-channel transistor M 21  to switch to an ‘OFF’ state and causes the n-channel transistor M 22  to switch to an ‘ON’ state. Consequently, the level of a signal output from the inverter  21 B of  FIG. 2  shifts to a low level, so that the level of a control signal ICKZ shifts to a low level in the interval until the time T 0  in  FIG. 4 . 
         [0044]    As shown in  FIG. 4 , a power down signal PDS used for setting the sleep mode is set to a low level in the normal mode. The power down signal PDS corresponds to a sleep mode setting signal in the first embodiment. An inverted power down signal PDR having a high level is supplied to each gate of the transistors M 1  and M 2  of  FIG. 2 . As shown in  FIG. 3 , the inverted power down signal PDR is obtained by inverting the power down signal PDS with the inverter  22 B. Supplying the inverted power down signal PDR having a high level to each gate of the transistors M 1  and M 2  of  FIG. 2  causes the n-channel transistor M 1  to switch to an ‘ON’ state and causes to the p-channel transistor to switch to an ‘OFF’ state. 
         [0045]    The respective control signals ICKX and ICKZ of  FIG. 2  are supplied to the transfer gate  23 C in the master latch circuit  23  of  FIG. 2 , so that the transfer gate  23 C becomes conductive in order to pass an input signal IS to the inverter  23 A. The inverter  23 A of  FIG. 2  outputs an inverted signal IS 1  obtained by inverting the input signal IS. The inverter  23 B of  FIG. 2  outputs an inverted signal obtained by inverting the inverted signal IS 1 . 
         [0046]    Subsequently, at the time T 0  in  FIG. 4 , supplying the clock signal CLK having a high level to each gate of the transistors M 11  and M 12  of  FIG. 2  causes the p-channel transistor M 11  to switch to an ‘OFF’ state and causes the n-channel transistor M 12  to switch to an ‘ON’ state. Consequently, the level of the signal output from the inverter  21 A of  FIG. 2  shifts to a low level, so that the level of the control signal ICKX shifts to a low level. 
         [0047]    The low level signal output from the inverter  21 A of  FIG. 2  is supplied to each gate of the transistors M 21  and M 22  via the input B 1  of the inverter  21 B of  FIG. 2 . Supplying the output signal having a low level to each gate of the transistors M 21  and M 22  causes the p-channel transistor M 21  to switch to an ‘ON’ state and causes the n-channel transistor M 22  to switch to an ‘OFF’ state. Consequently, the level of the signal output from the inverter  21 B of  FIG. 2  shifts to a high level. As a result, as shown in  FIG. 4 , the level of the control signal ICKZ shifts to a high level. 
         [0048]    The control signal ICKX having a low level and the control signal ICKZ having a high level are supplied to the transfer gate  23 D of the master latch circuit  23  of  FIG. 2  and a transfer gate  31 A of the signal transfer circuit  31  in the slave circuit  30 , respectively. This causes the transfer gates  23 D and  31 A to become conductive. Consequently, the inverted IS 1  is latched and the inverted signal IS 1  is fed, as a transfer signal IS 2 , to the slave latch circuit  32  of  FIG. 2  at time T 1  in  FIG. 4 . 
         [0049]    The inverter  32 A in the slave latch circuit  32  of  FIG. 2  inverts the transfer signal IS 2  and an output signal OS (See  FIG. 1 ) is generated. The output signal OS is output via the output line L 2  at time T 2  in  FIG. 4 . 
         [0050]    Subsequently, when the level of the clock signal CLK shifts to a low level from a high level, the control signal ICLX shifts to a low level, on the other hand, the control signal ICKZ shifts to a low level. The above shift causes the transfer gate  32 C in the slave latch circuit  32  of  FIG. 2  to become conductive and the output signal OS is latched and output. 
         [0051]    Such an operation, as shown in  FIG. 4 , wherein the input signal IS is finally converted to the output signal OS responsive to changes in the levels of clock signal CLK while being converted to the inverted signal IS 1  and the transferred signal IS 2  intermediately, is repeated in the normal mode. 
         [0052]    In addition, the flip-flop circuit according to the first embodiment operates in the following manner in the sleep mode. As shown in  FIGS. 1 and 5 , the power down signal PDS having a high level is input to the master circuit supply voltage control circuit  22  of  FIG. 2  at time T 5 , as shown in  FIG. 5 , in the sleep mode. The level of the clock signal CLK at the time T 5  is a low level. 
         [0053]    As shown in  FIGS. 2 and 5 , after the time T 5  has elapsed, the inverted power down signal PDR having a low level is supplied to the respective gates of the n-channel transistor M 1  and the p-channel transistor M 2  of  FIG. 2 . 
         [0054]    Supplying the inverted power down signal PDR having a low level to each gate of the transistors M 1  and M 2  of  FIG. 2  causes the n-channel transistor M 1  to switch to an ‘OFF’ state and causes the p-channel transistor M 2  to switch to an ‘ON’ state. Consequently, as shown in  FIG. 5 , the level of the control signal ICKX is kept at a high level. 
         [0055]    Switching the p-channel transistor M 2  to the ‘ON’ state results in the p-type channel transistor M 21  to switch to the ‘OFF’ state and results in the n-channel transistor M 22  to switch to the ‘ON’ state. Consequently, the level of the signal output from the inverter  21 B of  FIG. 2  shifts to a low level, and as shown in  FIG. 5 , the level of the control signal ICKZ is kept at the low level. 
         [0056]    As shown in  FIG. 2 , the control signal ICKX having a high level and the control signal ICKZ having a low level are supplied to the transfer gate  23 C of the master latch circuit  23  of  FIG. 2 , the transfer gate  31 A of the signal transfer circuit  31  and the transfer gate  32 C of the slave latch circuit  32  of  FIG. 2 , respectively, via a signal transfer line L 3  and a signal transfer line L 4 . 
         [0057]    The transfer gate  31 A of  FIG. 2  becomes non-conductive responsive to the control signal ICKX having a high level and the control signal ICKZ having a low level. Consequently, even if the transfer gate  23 C of  FIG. 2  becomes conductive responsive to the control signal ICKX having a high level and the control signal ICKZ having a low level, the inverted signal IS 1  is unable to pass through the transfer gate  31 A, which remains non-conductive. As a result, as shown in  FIG. 5 , the slave latch circuit  32  of  FIG. 2  stops latching the inverted signal IS 1  to itself. 
         [0058]    In the sleep mode, the slave latch circuit  32  of  FIG. 2  latches the transfer signal IS 1  at the time T 1  before the time T 5 , as well as the normal mode shown in  FIG. 4 . 
         [0059]    In the sleep mode, the power down signal PDS having a high level is supplied to the master circuit supply voltage circuit  22  of  FIG. 2  at the time T 5  following the time T 1 . Subsequently, a delay signal DS having a high level, which is obtained by delaying the power down signal PDS, is supplied to the gate of the p-channel transistor M 31  in the master circuit supply voltage control circuit  22  of  FIG. 2 . 
         [0060]    This results in the p-channel transistor M 31 , which is coupled to the power supply line VDD, to switch to the ‘OFF’ state after the time T 5 . Consequently, the connection between the power supply line and the master latch circuit  23  is disconnected, and the supply of a power supply voltage VFF to the respective inverters  23 A and  23 B in the master latch circuit  23  of  FIG. 2  is interrupted. Then, the p-channel transistor M 31  switches to an ‘OFF’ state, and a power supply voltage VFF drops, as shown in  FIG. 5 . 
         [0061]    On the other hand, the transfer gate C 32  becomes conductive responsive to the control signal ICKX having a high level and the control signal ICKZ having a low level. This causes the output signal OS to be latched and output. 
         [0062]    In the first embodiment, the control signals ICKX and ICKZ, which are obtained from the power down signal PDS, control the respective transfer gates  31 A and  32 C of  FIG. 2  to become conductive or non-conductive, so that the output signal OS is latched and output. The delay signal DS is supplied to the gate of the p-channel M 31  transistor of  FIG. 2  after the control signal ICKX having a high level and the control signal ICKZ having a low level are supplied to the respective transfer gates  31 A and  32 C, so that the p-channel transistor M 31  coupled to the power supply line VDD is switched to the ‘OFF’ state. 
         [0063]    In the first embodiment, the control signals ICKX and ICKZ control the transfer gate  31 A of  FIG. 2 , which is coupled to the output line L 1 , to become conductive or non-conductive. In the first embodiment, the delay signal DS having a high level is generated by delaying the power down signal PDS having a high level. Furthermore, the delay signal DS having a high level causes the p-channel transistor M 31  of  FIG. 2  to switch to the ‘OFF’ state to disconnect the connection between the power supply line VDD and the master latch circuit  23 , in the first embodiment. 
         [0064]    In the flip-flop circuit  10  in the first embodiment, the inverted power down signal PDR having a low level, which is generated based on the power down signal PDS having a high level for setting the sleep mode, is supplied to the gate of the n-channel transistor M 1  and the gate of the p-channel transistor M 2  in the clock generation circuit  21  of  FIG. 2  and the control signal ICKX having a high level and the control signal ICKZ having a low level are generated. As described above, in the flip-flop circuit  10  in the first embodiment, the transfer signal IS 2  was supplied to the slave latch circuit  32  in the slave circuit  30  and the output signal OS is latched and output. 
         [0065]    In the flip-flop circuit  10  in the first embodiment, the inverted signal IS 1 , which is output from the master latch circuit  23  in the master circuit  20  of  FIG. 2  based on the power down signal PDS having a high level, is supplied to the slave latch circuit  32  as the transfer signal IS 2  so that the loss of the inverted signal IS 1  is prevented. Furthermore, in the flip-flop circuit  10  in the first embodiment, the control signals ICKX having a high level and ICKZ having a low level are supplied to the gate of the transfer gate  31 A in the signal transfer circuit  31  and the gate of the transfer gate  32  in the slave latch circuit  32 . This supplies the transfer signal IS 2  to the slave latch circuit  32  and supplies the delay signal DS having a high level to the gate of the p-channel transistor M 31  in the master circuit supply voltage control circuit  22 . 
         [0066]    In the flip-flop circuit  10  in the first embodiment, after the transfer signal IS 2  is supplied to the slave latch circuit  32 , the p-channel transistor M 31 , which is coupled between the power supply line VDD and the master latch circuit  23 , switches to the ‘OFF’ state by the delay signal DS having a high level, so that the supply of the power supply voltage VFF to the respective inverters  23 A and  23 B in the master latch circuit  23  is interrupted. 
         [0067]    The flip-flop circuit  10  in the first embodiment can reduce power consumption due to the master latch circuit  23  by interrupting the supply of the power supply voltage VFF to the operation of the master latch circuit  23 . In addition, the flip-flop circuit  10  in the first embodiment can prevent loss of the inverted signal IS 1  by feeding the transfer signal IS 2  to the slave latch circuit  32 . 
         [0068]    Since the inverted signal IS 1  output from the master latch circuit  23  is supplied to the slave latch circuit  32  as the transfer signal IS 2 , the flip-flop circuit  10  according to the first embodiment requires no additional circuit used for latching the transfer signal IS 2  other than the circuit in the flip-flop circuit  10 . In consequence, since there is no need for adding a new circuit to the flip-flop circuit  10  in the first embodiment, the area occupied by the flip-flop circuit  10  can be reduced. 
         [0069]    In the flip-flop circuit  10  according to the first embodiment, the transfer gate  31 A of  FIG. 2  is coupled to the output line L 1  which couples the master latch circuit  23  and the slave latch circuit  32 . The transfer gate  31 A is set to be conductive or non-conductive based on the levels of control signals ICKX and ICKZ. In the first embodiment, when the transfer gate  31 A is set to be conductive or non-conductive based on the levels of control signals ICKX and ICKZ, the inverted signal IS 1  output from the master latch circuit  23  passes through the transfer gate  31 A responsive to the levels of the respective control signals ICKX and ICKZ, and the inverted signal IS 1  is latched, as the transfer signal IS 2 , to the slave latch circuit  32 . 
         [0070]    In the flip-flop circuit  10  according to the first embodiment, the transfer signal IS 2  of  FIG. 2  is used for supplying the inverted signal IS 1 , which is output from the master latch circuit  32  of  FIG. 2 , to the slave latch circuit  32  as the transfer signal IS 2 . The use of the operation characteristics of the transfer gate  31 A can achieve a high-speed switching operation and a reduction in power consumption due to the high-speed switching operation. 
         [0071]    In the method of controlling the flip-flop circuit  10  according to the first embodiment, by fixing the gate voltage of the transfer gate  31 A to a high voltage level or a low voltage level responsive to the levels of the control signals ICKX and ICKZ, the transfer gate  31 A can be set to be conductive or non-conductive. The use of the operation characteristics of the transfer gate  31 A can achieve a high-speed switching operation and a reduction in power consumption due to the high-speed switching operation. 
         [0072]    In the flip-flop circuit  10  according to the first embodiment, the delay control circuit  22 A generates the delay signal DS by delaying the power down signal PDS. The p-channel transistor M 31  coupled between the power supply line VDD and the master latch circuit  23  is switched to an ‘OFF’ state responsive to the delay signal DS. Note that the delay signal DS is generated by delaying the power down signal PDS. In the flip-flop circuit  10  according to the first embodiment, the control signals ICKX and ICKZ, which are generated based on the power down signal PDS, cause the transfer gate  31 A to become non-conductive and cause the transfer gate  32 C to become conductive. According to this operation, the inverted signal IS 1  is supplied to the slave latch circuit  32  as the transfer signal IS 2  and, subsequently, the p-channel transistor M 31 , which is coupled between the power supply line VDD  32  and the master latch circuit  23 , switches to the ‘OFF’ state by the delay signal DS, which is generated by delaying the power down signal PDS, so that the supply of the power supply voltage VFF to the master-latch circuit  23  is interrupted. The flip-flop circuit  10  according to the first embodiment can thereby prevent the loss of the inverted signal IS 1  without interrupting the power supply voltage VFF to the master latch circuit  23 , before feeding the transfer signal IS 2  to the slave latch circuit  32 . 
         [0073]    In the flip-flop circuit  10  according to the first embodiment, since the p-channel transistor M 31  of  FIG. 2  is coupled between the power supply line VDD and the master latch circuit  23 , an ‘ON’ state or the ‘OFF’ state of the p-channel transistor M 31  can be controlled responsive to the signal level of the delay signal DS. The use of the operation characteristics of the p-channel transistor can achieve a reduction in power consumption. 
         [0074]    A second embodiment of the present invention will be described with reference to  FIGS. 6 and 7 . The same elements as in the foregoing first embodiment are designated by the same reference numbers, and thus, their description is omitted. A flip-flop circuit  10 A shown in  FIG. 6  includes a slave circuit  30 A instead of the slave circuit  30  in the first embodiment. The slave circuit  30 A further includes a signal transfer circuit  31 , a slave latch circuit  32  and a transfer signal processing circuit  33 . 
         [0075]    The transfer signal processing circuit  33  includes an n-channel transistor M 33 A as shown in  FIG. 7 . A drain of the n-channel transistor M 33 A is coupled to an output line L 2 . A source of the N-type transistor  33 A is coupled to a ground. A gate of the n-channel transistor  33 A is coupled to a signal transfer line L 5 . 
         [0076]    Next, operation of the flip-flop circuit  10 A according to the second embodiment will be described. Certain aspects of the operation of the flip-flop circuit  10 A will be omitted as they correspond to those of the flip-flop circuit  10 . The flip-flop circuit  10 A operates in a sleep mode in the following manner. 
         [0077]    In the sleep mode, a power down signal PDS having a high level is supplied to the gate of the n-channel transistor M 33 A via the signal transfer line L 5 . Supplying the power down signal PDS to the gate of the n-channel transistor M 33 A causes the n-channel transistor M 33 A to switch to an ‘ON’ state. Therefore, the output line L 2  is coupled to ground via the n-channel transistor M 33 A having a conductive state. After coupling, a level of an output signal OS on the output line L 2  becomes a low level. In the second embodiment, the output signal OS having a low level is output to a load which operates according to positive logic. 
         [0078]    In the flip-flop circuit  10 A according to the second embodiment, the transfer signal processing circuit  33  in the slave circuit  30 A causes the p-channel transistor M 33 A, which is coupled between the output line L 2  and the ground, to switch to the ‘ON’ state based on the power down signal PDS having a high level and causes the level of the output signal OS on the output line L 2  to shift to a low level. 
         [0079]    In the flip-flop circuit  10 A according to the second embodiment, when the sleep mode is set responsive to the power down signal PDS having a high level, the level of the output signal OS is set to a low level. This prevents the output signal OS having a high level from being transmitted to the load, which operates according to the positive logic. 
         [0080]    Consequently, the flip-flop circuit  10 A can prevent the load, which operates according to positive logic, from being operated by the output signal OS having a high level in the sleep mode. 
         [0081]    A third embodiment of the present invention will be described with reference to  FIG. 8 . The same elements as in the foregoing first and the second embodiments are designated by the same reference numerals to reduce or omit their corresponding description. A flip-flop circuit  10 B shown in  FIG. 8  includes a slave circuit  30 B instead of the slave circuit  30 A. The slave circuit  30 B includes a signal transfer circuit  31 , a slave latch circuit  32  and a slave circuit supply voltage control circuit  34 . The slave circuit supply voltage control circuit  34  further includes a power supply control regulator  34 A. 
         [0082]    Next, operation of the flip-flop circuit  10 B according to the second embodiment will be described. Certain aspects of the operation of the flip-flop circuit  10 B will be omitted as they correspond to those of the flip-flop circuit  10  and  10 A. The flip-flop circuit  10 B operates in the following manner in a sleep mode. 
         [0083]    In the sleep mode, a power down signal PDS having a high level is supplied to the power supply control regulator  34 A via a signal transfer line L 6 . When the power down signal PDS having a high level is supplied to the power supply control regulator  34 A, the power supply control regulator  34 A supplies a power supply voltage VFF 1  to the slave latch circuit  32 . A value of the power supply voltage VFF 1  is set so that it is enough to latch an output signal OS to an output. 
         [0084]    A voltage value necessary for latching the output signal OS to the output is lower than a voltage value of the power supply voltage, which the slave circuit supply voltage control circuit  34  supplies to the slave latch circuit  32 , in a normal mode. 
         [0085]    In the flip-flop circuit  10 B in the third embodiment, the slave circuit supply voltage control circuit  34  supplies, responsive to the power down signal PDS having the high level, the power supply voltage VFF 1  sufficient for the slave latch circuit  32  to latch the output signal OS. This allows the value of the power supply voltage VFF to be set to a value lower than a voltage value which the slave latch circuit  32  requires in the normal mode. 
         [0086]    In the flip-flop circuit  10 B in the third embodiment, the power supply voltage VFF 1 , which the slave circuit supply voltage control circuit  34  supplies to the slave latch circuit  32 , is set to the value lower than the voltage value which is required by the slave latch circuit  32  in the normal mode. This reduces power consumption of the slave circuit supply voltage control circuit  34  in the sleep mode compared with the power consumption of the slave circuit supply voltage control circuit  34  in the normal mode. 
         [0087]    Consequently, the flip-flop circuit  10 B in the third embodiment can reduce the power consumption in the sleep mode compared with the power consumption in the normal mode, while on the other hand, it allows the slave latch circuit  32  to latch the output signal OS. 
         [0088]    A fourth embodiment of the present invention will be described with reference to  FIGS. 9 through 15 . The same elements as in the foregoing first through third embodiments are designated by the same reference numbers to reduce or omit the description. A flip-flop circuit  10 C shown in  FIG. 9  includes a master circuit  20 A, a slave circuit  30 C, a scan test circuit  40 , an input signal latch circuit  50 , a slave-side clock generation circuit  60 , a scan-side clock generation circuit  70  and a master circuit-slave circuit supply voltage control circuit  80 . 
         [0089]    In addition, the master circuit  20 A includes the clock generation circuit  21  and the master latch circuit  23 . The clock generation circuit  21  is not shown in  FIG. 10 . 
         [0090]    The slave circuit  30 C includes a signal transfer circuit  31  and a slave latch circuit  39 . The signal transfer circuit  31  includes a transfer gate  31 A 1  as shown in  FIG. 10 . 
         [0091]    The slave latch circuit  39  includes an inverter  32 B 1  instead of the inverter  32 B provided in the slave latch circuit  32  of  FIG. 2 . As shown in  FIG. 10 , the inverter  32 B 1  includes a plurality of p-channel transistors M 71  and M 73  and a plurality of n-channel transistors M 72  and M 74 . 
         [0092]    A drain of the p-channel transistor M 73  is coupled to a source of the p-channel transistor M 71 . A drain of the p-channel transistor M 71  is coupled to a drain of the n-channel transistor M 72 . A source of the n-channel transistor M 72  is coupled to a drain of the n-channel transistor M 74 . A ground potential VSS is supplied to a source of the n-channel transistor M 74 . 
         [0093]    The scan test circuit  40  includes a signal transfer circuit  41  and a scan latch circuit  42 . As shown in  FIG. 10 , a signal transfer circuit  41  includes a transfer gate  41 A. 
         [0094]    The scan test circuit  42  includes an inverter  42 A, an inverter  42 B and a transfer gate  42 C. An input G 1  of the inverter  42 A is coupled to an output C 2  of the inverter  23 A via the signal transfer circuit  41  coupled to an output line L 8 . As shown in  FIG. 10 , the output line L 8  is coupled in parallel to the output line L 1 . 
         [0095]    An output G 2  of the inverter  42 A is coupled to an output line L 9  and an input H 1  of the inverter  42 B. The inverter  42 B includes a p-channel transistor M 91  and an n-channel transistor M 92 . An output H 2  of the inverter  42 B is coupled to the input G 1  of the inverter  42 A. 
         [0096]    The input signal latch circuit  50  includes a plurality of p-channel transistors M 95  and M 96  and a plurality of N-type transistors M 97  and M 98 . A source of the p-channel transistor M 95  is coupled to a power supply line VDD. A drain of the p-channel transistor M 95  is coupled to a source of the p-channel transistor M 96 . 
         [0097]    A drain of the p-channel transistor M 96  is coupled to a drain of the n-channel transistor M 97 . A source of the n-channel transistor M 97  is coupled to a drain of the n-channel transistor M 98 . A ground potential VSS is supplied to a source of the n-channel transistor M 98 . 
         [0098]    An input I 1  of the input signal latch circuit  50  is coupled to the output line L 9  through an input line L 9 A. The input I 1  of the input signal latch circuit  50  is also coupled to gates of the p-channel transistor M 96  and the n-channel transistor M 97 , respectively. 
         [0099]    A connection node of the drain of the p-channel transistor M 96  and the drain of the n-channel transistor M 97  is coupled to an output I 2  of the input signal latch circuit  50 . The output I 2  of the input signal latch circuit  50  is coupled to an input E 1  of the inverter  32 A in the slave latch circuit  39  via the transfer gate  32 C 1 . 
         [0100]    As shown in  FIG. 11 , the slave-side clock generation circuit  60  includes an inverter  61 A, an inverter  61 B, a plurality of n-channel transistors M 67  and M 68  and a plurality of p-channel transistors M 69  and M 70 . 
         [0101]    The inverter  61 A includes a p-channel transistor M 63  and an n-channel transistor M 64 . A source of the n-channel transistor M 64  is coupled to a drain of the N-type transistor M 67 . A source of the n-channel transistor M 67  is coupled to a drain of the n-channel transistor M 68 . The ground potential VSS is supplied to a source of the n-channel transistor M 68 . In  FIG. 11 , a reference symbol J 1  indicates an input to the inverter  61 A and a reference symbol J 2  indicates an output from the inverter  61 A. 
         [0102]    The output J 2  from the inverter  61 A is coupled to an input K 1  to the inverter  61 B. The inverter  61 B includes a p-channel transistor M 65  and an n-channel transistor M 66 . A reference symbol K 2  indicates an output from the inverter  61 B. 
         [0103]    The output J 2  from the inverter  61 A is coupled to the input K 1  to the inverter  61 B via a signal transfer line L 11 . A drain of p-channel transistor M 69  and a drain the p-channel transistor M 70  are coupled to the signal transfer line L 11 , respectively. As shown in  FIG. 11 , the signal transfer line L 11  is coupled to an output line L 12 . 
         [0104]    As shown in  FIG. 12 , the scan-side clock generation circuit  70  includes an inverter  61 A 1 , an inverter  61 B 1 , a plurality of n-channel transistors M 671  and M 681 , and a plurality of n-channel transistor M 691  and M 701 . As shown in  FIG. 12 , a signal transfer line L 111  is coupled to an output line L 13 . 
         [0105]    As shown in  FIG. 13 , the master circuit-slave circuit supply voltage control circuit  80  includes a delay control circuit  81  and a p-channel transistor M 85 . An output of the delay control circuit  81  is coupled to a gate of the p-channel transistor M 85 . A power supply voltage is supplied to a source of the p-channel transistor M 85  via the power supply line VDD. The delay control circuit  81  includes two inverters  82  and  83  coupled in a multistage manner. 
         [0106]    Next, operation of the flip-flop circuit  10 C in the fourth embodiment will be described. The flip-flop circuit  10 C operates in such a manner that prevents a loss of an input signal IS when the flip-flop circuit  10 C is switched to a sleep mode from a normal mode. 
         [0107]    In the normal mode, as shown in  FIG. 14 , a level of a power down signal PDS is set to a low level which is the same as the case of the first embodiment. The level of the power down signal PDS is set to a low level in an interval between time T 11  to time T 12 , so that an inverted power down signal PDR having a high level is supplied to a gate of the n-channel transistor M 1  (see  FIG. 2 ) and the above-described gate of a p-channel transistor M 2  (see  FIG. 2 ). Consequently, the n-channel transistor M 1  switches to an ‘ON’ state and the p-channel transistor M 2  switches to an ‘OFF’ state. 
         [0108]    As described in the first embodiment, when a level of a clock signal CLK is a low level, a level of a control signal ICKX shifts to a high level and a level of a control signal ICKZ  9  shifts to a low level in the interval between the time T 11  and the time T 12 . 
         [0109]    On the other hand, similar to the first embodiment, when the level of the clock signal CLK is a high level, the level of the control signal ICKX shifts to a low level and the level of the control signal ICKZ shifts to a high level, in the interval between the time T 11  and the time T 12 . 
         [0110]    A scan test signal SMS used for setting a scan mode is set to a low level in the normal mode. Note that a scan test is conducted for the purpose of checking an interconnection after circuit board implementation or for the purpose of checking a circuit operation. As shown in  FIG. 14 , in the interval between the time T 11  and the time T 12 , a level of the scan test signal SMS is set to a low level, and a level of a first inverted scan test signal SMX is set to a high level. Note that the first scan test signal SMX is obtained by inverting the scan test signal SMS having a low level by an inverter (not shown). 
         [0111]    As shown in  FIG. 11 , the first inverted scan test signal SMX having the high level is supplied to a gate of the n-channel transistor M 68  and a gate of the p-channel transistor M 70 . Therefore, the n-channel transistor M 68  is switched to an ‘ON’ state and the p-channel transistor M 70  is switched to an ‘OFF’ state. 
         [0112]    In addition, as shown in  FIG. 11 , the inverted power down signal PRD having a high level is supplied to a gate of n-channel transistor M 67  and a gate of the p-channel transistor M 69  in the interval between the time T 11  and the time T 12  of  FIG. 14 . Therefore the n-channel transistor M 67  is switched to an ‘ON’ state and the p-channel transistor M 69  is switched to an ‘OFF’ state. 
         [0113]    As shown in  FIGS. 11 and 14 , the clock signal CLK having a low level from the input J 1  of the inverter M 61 A in the slave-side clock generation circuit  60  is input in the interval between the time T 11  and the time T 12 . Therefore, the p-channel transistor M 63  switches to an ‘ON’ state, a level of a control signal ICKSLX shifts to a high level and a level of a control signal ICKSLZ shifts to a low level. Note that, the n-channel transistor M 64  switches to an ‘OFF’ state by receiving the clock signal CLK having a low level. 
         [0114]    On the other hand, inputting the clock signal CLK having a high level from the input J 1  of the inverter  61 A in the slave-side clock signal generation circuit  60 , the p-channel transistor M 63  switches to an ‘OFF’ state, the level of the control signal ICKSLX shifts to a low level, and the level of the control signal ICKSLZ shifts to a high level. Note that the n-channel transistor M 64  switches to an ‘ON’ state by receiving the clock signal CLK having a high level. 
         [0115]    An inverter (not shown) in the flip-flop circuit  10 C of  FIG. 10  inverts the first inverted scan test signal SMX to generate a second inverted scan test signal SMZ. The above-described inverter inverts the first inverted scan test signal SMX having a high level to generate a second inverted scan test signal SMZ having a low level in the interval between the time T 11  and the time T 12  of  FIG. 14 . 
         [0116]    As shown in  FIG. 12 , the second scan test signal SMZ having a low level is supplied to a gate of the n-channel transistor M 681  and a gate of the p-channel transistor M 701 , respectively. In consequence, the n-channel transistor M 681  switches to an ‘OFF’ state and the p-channel transistor M 701  switches to an ‘ON’ state. 
         [0117]    Each gate voltage of the transistors M 671  and M 691  in  FIG. 12  is fixed at a high voltage level. In consequence, like as shown in  FIG. 11  n-channel transistor M 671  switches to an ‘ON’ state and the p-channel transistor M 691  switches to an ‘OFF’ state. 
         [0118]    A drain of the p-channel transistor M 701  with the ‘ON’ state is coupled to the signal transfer line L 111 , in the interval between the time T 11  and the time T 12  of  FIG. 14 , in the scan-side clock generation circuit  70  shown in  FIG. 12 . In consequence, as shown in  FIG. 14 , a control signal ICKSX output from the output line L 13  is kept at a high level regardless of changes of the clock signal CLK in the interval between the time T 11  and the time T 12 . The inverter  61 B 1 , on the other hand, inverts the control signal ICKSX having a high level to generate a control signal ICKSZ having a low level in the interval between the time T 1  and the time T 12 . 
         [0119]    In the flip-flop circuit  10 C of  FIG. 10 , in the same manner as the first embodiment, when the clock signal CLK shift from a low level to a high level, the transfer gate  23 D in a master latch circuit  23  and the signal transfer circuit  31  in the slave circuit  30 C become conductive responsive to the control signals ICKX, ICKZ, ICKSLX, and ICKSLZ, in the interval between the time T 11  and the time T 12  of  FIG. 14 . The inverter  23 A in master latch circuit  23  thereby outputs an inverted signal IS 1  to the slave latch circuit  39 . The inverted signal IS 1  is latched to the slave latch circuit  32  as a transfer signal IS 2 . 
         [0120]    As shown in  FIG. 14 , in the fourth embodiment, the level of the scan test signal SMS is set to a high level at the time T 12  to switch a mode to the normal mode from the scan mode. When the level of the scan test signal SMS is set to a high level, the level of the first inverted scan test signal SMX is set to a low level. 
         [0121]    As shown in  FIG. 11 , when the first inverted scan test signal SMX having a low level is supplied to the transistor M 70 , the p-channel transistor M 70  switches to an ‘ON’ state. 
         [0122]    The drain of the p-channel transistor M 70  that is in the ‘ON’ state is coupled to the signal transfer line L 11 . As shown in  FIG. 14 , the control signal ICKSLX output from the signal transfer line L 12  is kept at a high level regardless of the changes of the clock signal CLK after the time T 12 . On the other hand, the inverter  61 B inverts the control signal ICKSLX having a high level to generate the control signal ICKSLZ having a low level. 
         [0123]    The control signal ICKSLX having a high level and the control signal ICSKLZ having a low level cause the transfer gate  31 A 1  of the signal transfer circuit  31  in the slave circuit  30 C to become non-conductive. Therefore, the inverted signal IS 1  is not latched to the slave latch circuit  32 . 
         [0124]    The flip-flop circuit  10 C operates in the following manner in an interval between the time T 12  and time T 13  in  FIG. 14 . In the interval between the time T 12  and the time T 13 , the inverted power down signal PDR having a high level is supplied to the gates of the n-channel transistor M 671  and p-channel transistor M 691  shown in  FIG. 12 , and the second inverted scan test signal SMZ having a high level is supplied to the n-channel transistor M 681  and the p-channel transistor M 701 . This causes the transistors M 691  and M 701  coupled to the signal transfer line L 111  to switch to the ‘OFF’ state. 
         [0125]    In the scan-side clock generation circuit  70  of  FIG. 12 , in the interval between the time T 12  and the time T 13 , when the clock signal CLK having a high level is input from the input J 11  of the inverter  61 A 1 , the inverted clock signal having a low level is output from the output J 21  of the inverter  61 A 1  to the signal transfer line L 111 . This causes the level of the control signal ICKSX output from the input line L 13  to shift to a low level. At this time, the inverter  61 B 1  inverts the control signal ICKSX having a low level to generate the control signal ICKSZ having a high level. 
         [0126]    The control signals ICKSX having a low level and ICSKZ having a high level cause the transfer gate  41 A of the signal transfer circuit  41  in the scan test circuit  40  of  FIG. 10  to become conductive. As a result, the input signal IS 1  is fed, as a transfer signal IS 3 , to the scan test circuit  40 , at time T 12   a  (see  FIG. 14 ). The time T 12   a  indicates a point of time after a given interval has elapsed from a point of time when the level of the clock signal CLK shifts to the high level after the time T 12 . As shown in  FIG. 14 , the master latch circuit  23  latches scan test data to the output at the time T 12   a.    
         [0127]    In the scan test circuit  40  of  FIG. 10 , the inverter  42 A inverts the transfer signal IS 3  to generate a transfer signal IS 4 . The transfer signal IS 4  is input to the input signal latch circuit  50  via the output line L 9  and the input lines L 9 A. 
         [0128]    As shown in  FIG. 14 , in the forth embodiment, the mode is switched from the scan mode to the sleep mode by setting the power down signal PDS to a high level at the time T 13 . 
         [0129]    As shown in  FIG. 13 , after the power down signal PDS having a high level is input to the master circuit-slave circuit supply voltage control circuit  80 , a delay signal DS 1  having a high level, which is generated by delaying the power down signal PDS, is supplied to the gate of the p-channel transistor M 85  in the master circuit slave circuit supply voltage control circuit  80  at the time T 13 . Therefore, the p-channel transistor M 85  coupled to the power supply line VDD switches to an ‘OFF’ state, after the time T 13 . 
         [0130]    As a result of the above operation, a connection between the power supply line VDD and the master latch circuit  23  of  FIG. 10  and a connection between power supply line VDD and the slave latch circuit  39  of  FIG. 10  are disconnected. As shown in  FIG. 10 , according to the above operation, the supply of the power supply voltage VFF to the respective inverters  23 A and  23 B and the supply of the power supply voltage VFF to the respective inverters  32 A and  32 B 1  are interrupted. Therefore, as shown in  FIG. 14 , the input signal IS and the transfer signal IS 2  disappear because the power supply voltage VFF cannot be kept at the voltage which is required to latch signals. 
         [0131]    When the level of power down signal PDS is set to a high level, the scan-side clock generation circuit  70  of  FIG. 12  generates the control signal ICLSX having a high level and the control signal ICKSZ having a low level, as shown in  FIG. 14 . The transfer gate  42 C becomes conductive by the control signal ICLSX having a high level and the control signal ICKSZ having a low level and the transfer signal IS 4  is latched and output. 
         [0132]    At this point in time, the inverted power down signal PDR having a low level is supplied to a gate of the p-channel transistor M 95  in the input signal latch circuit  50  of  FIG. 10 . On the other hand, the delay signal DS 1  having a high level is supplied to a gate of the n-channel transistor M 98  in the input signal latch circuit  50  of  FIG. 10 . The p-channel transistor M 95  is switched to an ‘ON’ state. The n-channel transistor M 95  is also switched to an ‘ON’ state. The input signal latch circuit  50  of  FIG. 10  latches the transfer signal IS 4  in the sleep mode. 
         [0133]    When the inverted power down signal PDR having a low level is supplied to a gate of the p-channel transistor M 2  in the clock generation circuit  21  of  FIG. 9 , the clock generation circuit  21  generates the control signal ICKX having a high level and the control signal ICKZ having a low level shown in  FIG. 14 . In addition, when the inverted power down signal PDR having a low level is supplied to the gate of the n-channel transistor M 67  in the slave-side clock generation circuit  60  of  FIG. 11 , the slave-side clock generation circuit  60  generates the control signal ICKSLX having a high level and the control signal ICKSLZ having a low level shown in  FIG. 14 . 
         [0134]      FIG. 15  is a timing chart of the flip-flop circuit  10 C of  FIG. 10  when changing the mode of the flip-flop circuit to the normal mode from the sleep mode. In the flip-flop circuit, the level of the power down signal PDS is set to a low level and the level of the scan test signal SMS is set to a low level at time T 21 . The mode is switched to the normal mode from the sleep mode. 
         [0135]    The control signal ICKSLX having a high level and the control signal ICKSLZ having a low level are supplied to the transfer gate  32 C 1  in the slave latch circuit  39  of  FIG. 10  at time T 22  following the time T 21 . Therefore, the transfer gate  32 C 1  becomes conductive. 
         [0136]    In the slave latch circuit  39  of  FIG. 10 , the inverter  32 B 1  inverts an inverted transfer signal IS 5 , which is generated by inverting the transfer signal IS 4 , to generate an inverted transfer signal IS 6 . Then, the inverter  32 A further inverts the inverted transfer signal IS 6  to generate an inverted transfer signal IS 7 . The inverted transfer signal IS 7  is output from the output line L 2 . 
         [0137]    In addition, the control signal ICKX having a high level and the control signal ICKZ having a low level low are supplied to a transfer gate  23 C in the master latch circuit  23  of  FIG. 10  at the time T 22 . Therefore, the transfer gate  23 C becomes conductive and the input signal IS is latched to the master latch circuit  23 . 
         [0138]    Then, similar to the operation in the normal mode as shown in  FIG. 14 , the input signal IS is converted to the transfer signal IS 2  after the input signal IS is inverted to the inverted signal IS 1  and the transfer signal IS  2  is latched to the slave circuit  32 . In the flip-flop circuit  10 C according to the fourth embodiment, as shown in  FIG. 15 , the slave circuit  32  repeatedly latches the input signal IS as the transfer signal IS 2 , responsive to the change of the clock signal CLK from a low level to a high level. 
         [0139]    In the flip-flop circuit  10 C according to the fourth embodiment, the output line L 8 , which is coupled in parallel to the output line L 1 , is coupled between the master latch circuit  23  of  FIG. 10  and the scan latch circuit  42  of  FIG. 10 . The transfer gate  41 A coupled to the output line L 8  is configured so that the transfer gate  41 A is set to a conductive or non-conductive state responsive to the levels of the control signals ICKSX and ICKSZ. The levels of the control signals ICKSX and ICKSZ are changed responsive to the levels of the second inverted scan test signal SMZ supplied to the scan-side clock generation circuit  70  of  FIG. 12 . 
         [0140]    In the fourth embodiment, when setting the transfer gate  41 A to a conductive or non-conductive state responsive to the levels of the control signals ICKSX and ICKSZ, the inverted signal IS 1  output from the master latch circuit  23  of  FIG. 10  passes through the transfer gate  41 A of  FIG. 10  and can be latched into the scan latch circuit  42  of  FIG. 2 . 
         [0141]    Consequently, the flip-flop circuit  10 C according to the fourth embodiment can use the scan latch circuit  42  as a latch circuit for latching the transfer signal IS 3 , which is different from the scan test data. 
         [0142]    In the flip-flop circuit  10 C according to the fourth embodiment, after the scan latch circuit  42  of  FIG. 9  latches the input signal IS 1 , as the transfer signal IS 3 , the master circuit-slave circuit supply voltage control circuit  80  of  FIG. 9  interrupts the supply of the power supply voltage VFF to the master latch circuit  23  of  FIG. 9  and the slave latch circuit  39  of  FIG. 9 , responsive to the power down signal PDS having the high level. 
         [0143]    In the flip-flop circuit  10 C according to the fourth embodiment, the master circuit-slave circuit supply voltage control circuit  80  interrupts the supply of the power supply voltage VFF to the master latch circuit  23  and the slave latch circuit  39  after the input signal IS latched to the master latch circuit  23  is latched to the scan latch circuit  42 . 
         [0144]    Consequently, the flip-flop circuit  10 C according to the fourth embodiment can prevent the loss of input signal IS while the flip-flop circuit  10 C reduces the power consumption of the slave latch circuit  39  and the master latch circuit  23 . 
         [0145]    In the flip-flop circuit  10 C according to the fourth embodiment, the input line L 9 A of  FIG. 10  is coupled between the output line L 9 , which is coupled to the scan latch circuit  42 , and the slave latch circuit  39 . The input line L 9 A of  FIG. 10  is coupled to the input signal latch circuit  50 . 
         [0146]    The input signal latch circuit  50  of  FIG. 10  latches the transfer signal IS 4  responsive to the inverted power down signal PDR having the low level, which is obtained from the power down signal PDS having the high level, and the delay signal DS 1  having the high level, which is obtained from the power down signal PDS having the high level. 
         [0147]    In the flip-flop circuit  10 C according to the fourth embodiment, since the input signal latch circuit  50  of  FIG. 10  latches the transfer signal IS 4  responsive to the power down signal PDS for setting the sleep mode, the transfer signal IS 4  can be transferred to the slave latch circuit  39  without the loss of transfer signal IS 4  in the sleep mode. 
         [0148]    In the flip-flop circuit  10 C according to the fourth embodiment, the delay control circuit  81  of  FIG. 13  generates the delay signal DS 1  obtained by delaying the power down signal PDS to switch the p-channel transistor M 85  of  FIG. 13 , which couples the power supply line VDD to the master latch circuit  23  and the slave latch circuit  39 , to the ‘OFF’ state responsive to the delay signal DS 1 . 
         [0149]    In the flip-flop circuit  10 C according to the fourth embodiment, the flip-flop circuit  10 C can simultaneously interrupt the supply of the power supply voltage to the master latch circuit  23  of  FIG. 9  and the slave latch circuit  39  of  FIG. 9  by switching the p-channel transistor M 85  of  FIG. 13 , which couples the power supply line VDD to the master latch circuit  23  and the slave latch circuit  39 , responsive to the power down signal PDS. 
         [0150]    The present invention is not limited to the details of the embodiments described above, and various modifications and improvements can be applied without departing from the spirit and scope of the invention. For example, as shown in  FIG. 16 , in a flip-flop circuit in a fifth embodiment, a plurality of (e.g., four) master-slave circuits  10 E, each of which has a master circuit  20 A and a slave circuit  30 , are provided and the plurality of master-slave circuits  10 E are commonly coupled to a master circuit supply voltage control circuit  22 . Note that the same elements as in the foregoing first through fourth variations are designated by the same reference numbers to reduce or omit the description in  FIG. 16 . 
         [0151]    In the fifth embodiment shown in  FIG. 16 , no additional master circuit supply voltage control circuit is required with respect to each master-slave circuit  10 E because the master-slave circuits  10 E are commonly coupled to the master circuit supply voltage control circuit  22 . The fifth embodiment shown in  FIG. 16  is different from a case where the discrete master circuit supply voltage control circuits are provided with respect to each of the master-slave circuits  10 E. That is, according to the fifth embodiment, an area, which is occupied by the master circuit supply voltage control circuit  22 , can be reduced by sharing the master circuit supply voltage control circuit  22  coupled to the respective master-slave circuits  10 E. 
         [0152]    In a sixth embodiment as shown in  FIG. 17 , a plurality of (e.g., four) master-slave circuits  10 F, each of which includes a master circuit  20 A and a slave circuit  30 A, are provided and the plurality of master-slave circuits  10 F are commonly coupled to a master circuit supply voltage control circuit  22 . Note that the same elements as in the foregoing first through fifth embodiments are designated by the same reference numbers to reduce or omit the description in  FIG. 17 . 
         [0153]    Moreover, in a seventh embodiment as shown in  FIG. 18 , a plurality of (e.g., three) master-slave circuits  10 G, each of which a master circuit  20  and a slave circuit  30 , and the plurality of master-slave circuits  10 G are commonly coupled to a master circuit supply voltage control circuit  34 . Note that the same elements as in the foregoing first and third embodiments are designated with the same reference numbers to reduce or omit the description in  FIG. 18   
         [0154]    In the seventh embodiment shown in  FIG. 18 , since a slave circuit supply voltage control circuit  34  is commonly coupled to master-slave circuits  10 G, no additional slave circuit supply voltage control circuit  34  is necessary with respect to each master-slave circuit  10 . The seventh embodiment shown in  FIG. 18  is different from a case where the discrete slave circuit voltage supply control circuits are provided with respect to each master-slave circuit  10 . 
         [0155]    That is, in the flip-flop circuit according to the seventh embodiment, an area, which is occupied by the slave circuit supply voltage control circuit  34 , can be reduced by sharing the slave circuit supply voltage control circuit  34  coupled to the respective master-slave circuits  10 E. 
         [0156]    Exemplary embodiments of the present invention have now been described in accordance with the above advantages. It will be appreciated that these examples are merely illustrative of the invention. Many variations and modifications will be apparent to those skilled in the art.