Abstract:
A test setup is provided to test differential signals outputs from the I/O block (IOB) pairs in an integrated circuit (IC). The test setup allows elimination of the external 100 Ohm resistors provided across the differential outputs on a device under test (DUT) test board containing the IC by taking advantage of a 100 Ohm resistor built into the IC between a portion of the IOB pairs. An IOB pair being tested may have its differential output terminal pair shorted to the differential output terminal pair of the IOBs having the internal 100 Ohm resistor.

Description:
BACKGROUND 
   1. Technical Field 
   Embodiments of the present invention relates to a 100 Ohm resistor used between two Input/Output (I/O) Block (IOB) output differential pair terminals for differential signal testing of the output terminals of the IOBs in an integrated circuit device. 
   2. Related Art 
   Testing differential signal standards typically requires placing a 100 Ohm resistor on a device under test (DUT) board containing a chip for each differential I/O pair. With complex chips, such as programmable logic devices (PLDs) including complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs), microprocessors or other circuits, the chip can have 500 or more pin pairs. With 500 pin pairs, 500 resistors must be added to a DUT test board. This makes the DUT board expensive, difficult to manufacture, and increases its size. In addition, the extra components increase the amount of maintenance required to keep the DUT board ready for use in manufacturing. 
   For reference,  FIG. 1  shows typical components found on an FPGA. Although an FPGA is shown, it is understood that similar chips with differential I/Os may be used with embodiments of the present invention. The FPGA shown includes programmable or configurable logic blocks (CLBs)  104 , input/output blocks (IOBs)  106 , and programmable interconnects  108 , as well as configuration memory  116  for determining the functionality of the FPGA  102 . The FPGA  102  may also include an embedded processor block  114 , as well as various other dedicated circuitry such as blocks of random access memory (“BRAM  110 ”), and digital clock managers (DCM) blocks  112 . Those skilled in the art will appreciate that the FPGA  102  may include other types of logic blocks and circuits in addition to those described herein. 
   The IOBs  106 , the CLBs  104 , and the programmable interconnect  108  may be configured to perform a variety of functions. The CLBs  104  are programmably connectable to each other, and to the IOBs  106 , via the programmable interconnect  108 . Each CLB slice in turn includes various circuits, such as flip-flops, function generators (e.g., look-up tables (LUTs)), logic gates, and memory. The IOBs  106  are configured to link signals from the pins on the chip to and from the CLBs  104 , or to and from other IOBs. A pair of IOBs can provide a differential output over a pair of terminals connected to pads that are wire bonded to pins of a chip. The IOBs  106  can also include transceiver circuitry configured for communication between a connection pad and a variety of media, such as wired, wireless, optical, and photonic, whether analog or digital. Configuration information for the CLBs  104 , the IOBs  106 , and the programmable interconnect  108  is stored in the configuration memory  116 . The configuration memory  116  may include static random access memory (SRAM) cells. The DCM blocks  112  provide well-known clock management circuits for managing clock signals within the FPGA  102 , such as delay lock loop (DLL) circuits and multiply/divide/de-skew clock circuits. The processor block  114  includes a microprocessor core, as well as associated control logic. 
     FIG. 2  illustrates the conventional external resistor method of differential testing of an IOB pair. The differential output buffer  200  receives an input signal (I) from components internal to the integrated circuit, such as a CLB, or from another IOB. The IOBs provide a first signal (O)  206  and a second signal (OB)  208  complementary to the first. The IOB pair  206  and  208  are labeled IO_P and IO_N, respectively, to represent P type and N type differential output contacts, and may be connection points to pins of a chip connected to the buffer  200 . An input buffer  202  likewise receives a differential input from terminals  206  and  208 . The differential input includes a first signal (I) and a second signal (IB) complementary to the first. 
   A 100 Ohm resistor  204  is provided across the terminals  206  and  208  to accommodate differential testing standards. The 100 Ohm resistor  204  is provided on a test board separate from a chip containing the buffers  200  and  202 . The differential test standards that use the resistor  204  include for example, low-voltage differential signaling (LVDS) standard, output differential voltage, (VOD), and output common mode (VOCM.) The current test methods require a 100 Ohm resistor for each differential I/O pair. 
   During testing, the input signal (I) is applied to the output buffer  200 . Differential output signals (O) and (OB) are measured from the terminals  206  and  208 . When a logic 1 is applied to input (I), the outputs (O) and (OB) are expected to be a high and a low respectively. When a logic 0 is applied to input I, outputs (O) and (OB) are expected to provide a low and a high respectively. 
     FIG. 3  shows a block diagram of components of an FPGA  300  illustrating how an external 100 Ohm resistor is connected for differential testing. As shown, the resistor  204  is connected across two IOBs  106   1  and  106   2 . The IOB  106   1  provides the IO_P differential output, while the IOB  106   2  provides the IO_N differential output. A CLB, such as  104  can be connected in the FPGA  300  by internal routing lines to provide the differential signal to the IOBs  106   1  and  106   2 . Although only one resistor  204  is shown, other resistors will be required on a printed circuit test board where the FPGA  300  is mounted to test the differential outputs IOBs other than the differential output provided by IOBs  106   1  and  106   2 . 
   It is desirable to provide further test configurations that allow testing differential signal standards without requiring a large number of resistors on a DUT test board. 
   SUMMARY 
   According to embodiments of the present invention, a test setup is provided to test differential signals standards that do not require external 100 Ohm resistors on a DUT test board across the IOB differential outputs by taking advantage of built-in or internal 100 Ohm resistors. 
   According to embodiments of the present invention, the 100 Ohm resistor across an IOB pair is used during testing by connecting its internal resistor across the differential IOB pair being tested. In one embodiment, some IOB pairs in the system are provided with a differential termination (DT) that includes a built in 100 Ohm resistor. Thus, the DT IOB pair in the system is the IOB pair with terminals shorted to differential terminals of the IOB pair being tested. 
   In some embodiments, entire columns of IOBs can be tested at one time. To test an entire column, a second column of IOB pairs with internal resistors have differential outputs shorted to the differential outputs of IOB pairs in the column to be tested. In this manner, the 100 Ohm resistors in the second column take the place of 100 Ohm resistors normally mounted externally on the DUT test board for each IOB pair in the column being tested. 
   In an alternative embodiment, one column of IOBs is tested by sequentially connecting the differential output of one IOB pair at a time to an IOB pair with an internal resistor. In this embodiment, registers are connected to form a shift register to apply tri-state signals to buffers providing differential output signals driving the IOB pairs in the column being tested. Only one buffer is enabled, or not tri-stated, at a time. All the IOB pairs in the column tested have their differential output terminals shorted to the terminals of a given IOB pair with the internal 100 Ohm resistor. In this manner, each buffer in the column is sequentially tested using the 100 Ohm resistor of the given IOB pair. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further details of the present invention are explained with the help of the attached drawings in which: 
       FIG. 1  is a block diagram depicting typical components of an FPGA; 
       FIG. 2  shows a conventional test configuration for differential testing of the outputs of IOBs using a 100 Ohm external resistors; 
       FIG. 3  shows a block diagram of components of an FPGA illustrating how an external 100 Ohm resistor is connected for differential testing; 
       FIG. 4  shows a block diagram of components of an FPGA illustrating how an internal 100 Ohm resistor can be used for differential testing according to embodiments of the present invention; 
       FIG. 5  shows a test configuration for differential testing of IOBs according to embodiments of the present invention; 
       FIG. 6  illustrates connection of a test controller to receive test signals from differential terminals of IOBs of an IC to perform differential signal testing according to embodiments of the present invention; and 
       FIG. 7  illustrates a connection of registers and IOBs to sequentially connect and test IOBs one at a time according to embodiments of the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 4  shows a block diagram of components of an FPGA  400  illustrating how an internal 100 Ohm resistor  402  can be used for differential testing according to embodiments of the present invention. As shown, the resistor  402  is connected internal to the FPGA  400  across two IOBs  106   3  and  106   4 . A differential signal to be tested is provided from a pair of IOBs  106   1  and  106   2 . The IOB  106   1  provides an IO_P differential output connected through IOB  106   3  to a first terminal of resistor  402 , while IOB  106   2  provides an IO_N differential output connected through IOB  106   4  to a second terminal of resistor  402 . A CLB, such as  104 , can be connected by internal routing lines to provide the differential signal to the IOBs  106   1  and  106   2 . 
     FIG. 5  shows how the resistor  402  of  FIG. 4  can be the internal resistor of a buffer  510  that provides a differential signal that is otherwise available in an FPGA. That is, in some embodiments a buffer may include an internal resistor, for example to support a differential standard, and that internal resistor may be used during testing. This has a benefit of not requiring extra area to support testing features. In other embodiments, an internal resistor can be added. The test configuration shown, thus, includes a first buffer  500  to be tested and a second buffer  510 . The second buffer  510  includes the internal resistor  402  that is used in place of the external resistor  204  of  FIG. 2 . 
   Connection of differential outputs of the first buffer  500  is provided to the IOB pair  106   1  and  106   2 . The connection of differential outputs of the second buffer  510  is then provided to the IOB pair  106   3  and  106   4 . The IOB IO_P contact  106   1  is connected (or shorted) to the IOB IO_P contact  106   3 . The IOB IO_N contact  106   2  is connected (or shorted) to the IOB IO_N contact  106   4 . The internal resistor  402  of buffer  510  is, thus, effectively connected across the differential outputs IO_P  106   3  and IO_N  106   4  of buffer  500 . The regions labeled IO_P  106   3  and IO_N  106   4 , respectively, can represent pad regions on a die that can be wire bonded to pins of a chip. Alternatively, IO_P  106   3  and IO_N  106   4  terminal can connect to an RF link or other terminal connection. Interconnection of the regions  106   3 - 106   4  can be accomplished, for example, in a programmable logic device, such as an FPGA, by programming interconnect points by loading a test configuration program into the configuration memory of the FPGA. 
   Similar to the buffers  200  and  202  of  FIG. 2 , the circuit of  FIG. 5  includes the output buffer  500  and a corresponding input buffer  502 . The buffer  500  receives an input signal (I) from components internal to the integrated circuit, such as a CLB or IOB, or components external to the chip. The output buffer  500  then provides a differential output to the pair of terminals  106   1  and  106   2 , the differential output including a first signal (O) and a second signal (OB) complementary to the first. The input buffer  502  likewise receives a differential input from terminals  106   1  and  106   2 . The differential input includes a first signal (I) and a second signal (IB) complementary to the first. The input buffer  502  can provide a feedback signal from the output of buffer  500 , or provide a signal from an external device that is provided to terminals  106   1  and  106   2 . 
   The input buffer  510  includes the internal resistor  402 . In some embodiments of the present invention, the resistor  402  is built-in only in IOBs of an IC with a special differential termination (DT). Thus, the buffer  500  is not shown with such a resistor. The DT type IOBs, thus, serve to test other IOBs in the IC. 
   During testing, the input signal (I) is applied to the buffer  500 . The input signal I can come from an internal component of an IC, such as a CLB or an IOB, or external signal applied to a pin of the IC. Differential output signals (O) and (OB) are measured from the terminals  106   1  and  106   2 . The IC is internally programmed to interconnect or short the differential IO_P terminals  106   1  and  106   3 , as well as to short the differential IO_N terminals  106   2  and  106   4 . The resistor  402 , thus, provides the differential connection across terminals  106   1  and  106   2 . When a logic 1 is applied to input I, the outputs O and OB are expected to be a high and a low respectively. When a logic 0 is applied to input I, outputs O and OB are expected to provide a low and a high respectively. 
     FIG. 6  illustrates connection of a test controller  600  to receive test signals from differential outputs of IOBs of an IC to perform differential signal testing according to embodiments of the present invention. Only the N Pin and P Pin connections are shown, with other components of the IOBs being illustrated in  FIG. 5 . One N Pin/P Pin pair  620  connected to the controller  600  includes an internal resistor to function similar to the resistor  402  of buffer  510  of  FIG. 5 . The remaining N Pin/P Pin pairs  622 ,  624 ,  626 ,  630 ,  632 ,  634 ,  640 ,  642  and  644  are connected to the test controller  600  and can function to test buffers like the IOBs  106   1  and  106   2  used to test buffer  500  in  FIG. 5 . With the test controller  600  connected to only one P Pin/N Pin pair  620  that has an internal resistor, a test signal must be applied to each of the IOB pairs  622 ,  624 ,  626 ,  630 ,  632 ,  634 ,  640 ,  642  and  644  individually with the others tri-stated (or otherwise disconnected) to perform testing. 
   In an alternative test configuration, other P Pin/N Pin pairs than  620  with internal resistors, such as pair  628 , are utilized to enable testing of more than one IOB at a time. In this manner, separate P and N connections are provided from the test controller  600  for each IOB pair that is tested. In one embodiment, with the IOBs divided into columns, entire columns can be tested by connecting each column of IOB pairs with separate IOB pairs having 100 Ohm internal resistors, and receiving a separate signal from each pair using the test controller. 
     FIG. 7  illustrates a connection of registers and IOBs to sequentially connect and test IOB pairs one at a time according to embodiments of the present invention. The system of  FIG. 7  includes a buffer  708  with a built in resistor  709 , similar to the resistor  402  of  FIG. 5 . Further, the test system includes buffers  704   0 - 704   N  with differential outputs that are to be tested sequentially, one at a time. Test signals can be measured from the buffers  704   0 - 704   N  via the pads of respective IOB pairs  706   0 - 706   N . An input test signal to the buffers  704   0 - 704   N  is shown provided from a pad through buffer  702 . 
   The test system of  FIG. 7  further includes a series of interconnected registers  710   0 - 710   N  that form a shift register to supply tri-state signals to the buffers  704   0 - 704   N  being tested. The tri-state signals are shown to be a 1 for all but one buffer in the buffers  704   0 - 704   N , enabling only one buffer differential output to be connected to the resistor  709  for testing at a time with the test signal from buffer  702 . The differential outputs from buffers  704   0 - 704   N  are tested each cycle of the clock signal (Ck) applied to the registers  710   0 - 710   N . 
   Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many additional modifications will fall within the scope of the invention, as that scope is defined by the following claims.