Abstract:
A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2007-314729 filed on Dec. 5, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    An aspect of the embodiments discussed herein is directed to a semiconductor device having a multilayer wiring structure and a method of manufacturing such a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    Semiconductor integrated circuits manufactured today each contain vast numbers of semiconductor elements on the common board thereof and employ a multilayer wiring structure to connect such semiconductor elements with each other. 
         [0006]    In a multilayer wiring structure, interlayer insulating films, in each of which wiring patterns are embedded to form a wiring layer, are laminated, and via contacts formed inside the interlayer insulating films connect the upper wiring layer and the lower wiring layer. 
         [0007]    In particular, in current ultrafine and ultrahigh-speed semiconductor devices, low-dielectric-constant films (so-called low-k films) are used as such interlayer insulating films to reduce the problem of signal delay, for example RC delay, that occurs in a multilayer wiring structure, as well as low-resistance copper (Cu) patterns used as wiring patterns. 
         [0008]    In this type of multilayer wiring structure, in which Cu wiring patterns are embedded in interlayer insulating films with a low dielectric constant, it is desirable to pattern the Cu layer by dry etching. A method often used to pattern the Cu layer by dry etching is a so-called damascene or dual damascene process, wherein wiring trenches or via holes are carved through interlayer insulating films in advance. These wiring trenches or via holes are filled with a Cu layer and then unnecessary portions of the Cu layer remaining on the interlayer insulating films are removed by chemical mechanical polishing (CMP). 
         [0009]    Any direct contact of a Cu wiring pattern with an interlayer insulating film in this process would cause Cu atoms to diffuse into the interlayer insulating film, thereby leading to short circuits or other defects. These short circuits or other defects are generally avoided by covering the side walls and bottoms of wiring trenches or via holes used to form Cu wiring patterns with conductive diffusion barriers, also known as barrier metal films, and then coating the barrier metal films with a Cu layer. Examples of materials used for such a barrier metal film may include a high-melting-point metal such as tantalum (Ta), titanium (Ti), and tungsten (W) as well as conductive nitrides thereof. 
         [0010]    However, in ultrafine and ultrahigh-speed semiconductor device based on current 45-nm technology or newer technologies, the size of wiring trenches or via holes carved through interlayer insulating films is significantly reduced along with miniaturization. To achieve desirable reduction in the resistance of wiring while using such a high-dielectric-constant barrier metal film, it is accordingly necessary that each of barrier metal films covering such ultrafine wiring trenches or via holes is as thin as possible while seamlessly covering the side walls and bottoms of the wiring trenches or via holes. 
         [0011]    A technique that has been proposed to address this situation is direct covering of wiring trenches or via holes carved through interlayer insulating films with a copper-manganese alloy layer (Cu—Mn alloy layer). In this technique, Mn atoms contained in a Cu—Mn alloy layer react with Si and oxygen atoms contained in an interlayer insulating film and thus a manganese-silicon oxide layer having a thickness in the range of 2 nm to 3 nm and a composition of MnSi x O y  is formed inside the Cu—Mn alloy layer as a diffusion barrier film. 
         [0012]    However, it is known that in this technique the internally formed manganese-silicon oxide layer contains manganese (Mn) at a too low concentration and thus the adhesion of that layer to a Cu film is problematically weak. 
         [0013]    Consequently, another structure of a barrier metal film in which a Cu—Mn alloy layer is combined with a barrier metal film based on a high-melting-point metal such as Ta or Ti has been proposed. 
         [0014]    Such a barrier metal structure combining a Cu—Mn alloy layer with a barrier metal film based on a high-melting-point metal such as Ta or Ti provides preferable characteristics with improved resistance to oxidation through the sequence described below. 
         [0015]    Recently, use of low-dielectric-constant porous films as a low-dielectric-constant material constituting interlayer insulating films has been proposed to prevent signal delay, for example RC delay. However, unfortunately, such a low-dielectric-constant porous material has a low density and thus is likely to be damaged by plasma during the manufacturing process, and a damaged film often retains moisture on the surface and inside thereof. Accordingly, a barrier metal film formed on such a low-dielectric-constant porous film would be likely to be oxidized by moisture retained inside and this often results in deteriorated characteristics of the barrier metal film and poor adhesion thereof to a Cu wiring layer or a via plug. 
         [0016]    On the other hand, the Cu—Mn alloy layer described above contains Mn atoms, and if the layer is used as a seed layer, these Mn atoms react with oxidized portions of a barrier metal film, thereby ensuring characteristics of the barrier metal film necessary for its use as a diffusion barrier and maintaining high adhesion thereof to a Cu wiring layer or a via plug. 
         [0017]    Related information may be found in the following patent documents: 
       Patent Document 1: Japanese Laid-open Patent Publication No. 2007-142236; 
     Patent Document 2: Japanese Laid-open Patent Publication No. 2005-277390. 
     SUMMARY 
       [0018]    According to an aspect of an embodiment, a semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring containing carbon. 
         [0019]    These together with other aspects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIGS. 1A-1F  are diagrams for explanation of the conventional art; 
           [0021]      FIG. 2  is a diagram for explanation of a problem in the conventional art; 
           [0022]      FIGS. 3A-3F  are diagrams for explanation of another conventional art; 
           [0023]      FIG. 4  is a diagram illustrating a configuration of a semiconductor device according to Embodiment 1; 
           [0024]      FIGS. 5A-5L  are diagrams illustrating a manufacturing process of the semiconductor device according to Embodiment 1; 
           [0025]      FIG. 6  is a diagram for explanation of reaction that occurs in a process according to Embodiment 1; 
           [0026]      FIG. 7  is a diagram for explanation of the advantageous effect of Embodiments 1 and 2; 
           [0027]      FIG. 8A  is a diagram illustrating a configuration of a standard device tested as a control to demonstrate the advantageous effect of Embodiment 1; 
           [0028]      FIG. 8B  is a diagram illustrating a configuration of a device used to demonstrate the advantageous effect of Embodiment 1; 
           [0029]      FIGS. 9A-9K  are diagrams illustrating a manufacturing process of a semiconductor device according to Embodiment 2; 
           [0030]      FIG. 10  is a diagram illustrating a configuration of a device used to demonstrate the advantageous effect of Embodiment 2; 
           [0031]      FIG. 11  is an additional diagram demonstrating the advantageous effect of Embodiment 2; and 
           [0032]      FIG. 12  is a diagram illustrating a configuration of a device used to demonstrate the advantageous effect of Embodiment 2. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0033]      FIGS. 1A to 1F  are diagrams representing the process of forming a Cu wiring pattern. 
         [0034]    In  FIG. 1A , a silicon dioxide film  12  consisting of a methyl silsesquioxane (MSQ) film covers an insulating film  11  formed on a silicon substrate not shown in the drawing. 
         [0035]    Then, as shown in  FIG. 1B , a wiring trench  12 T corresponding to a desired wiring pattern is carved through the silicon dioxide film  12 . 
         [0036]    After that, as shown in  FIG. 1C , a barrier metal film  13 BM consisting of a high-melting-point metal, such as Ta, or a conductive nitride thereof, such as TaN, TiN, or WN, is formed so as to coat the top of the silicon dioxide film  12  and the side walls and bottom of the wiring trench  12 T. 
         [0037]    In this structure shown in  FIG. 1C , a Cu—Mn alloy layer  13 CM is also formed on the barrier metal film  13 BM so as to have the cross-sectional shape fitting the barrier metal film  13 BM. 
         [0038]    Furthermore, a Cu layer  13  is formed on the Cu—Mn alloy layer  13 CM so as to fill the wiring trench  12 T as shown in  FIG. 1C . 
         [0039]    Then, CMP is applied to shave the Cu layer  13 , the Cu—Mn alloy layer  13 CM and the barrier metal film  13 BM existing therebeneath until the surface of the silicon dioxide film  12  is exposed. This step results in the structure shown in  FIG. 1D , wherein the wiring trench  12 T is filled with a Cu wiring pattern  13 P. 
         [0040]    After that, as shown in  FIG. 1E , another silicon dioxide film  14  consisting of an MSQ film is formed on the structure shown in  FIG. 1D , and the structure shown in  FIG. 1E  is then heated at a given temperature, for example, 400° C. to provide the structure shown in  FIG. 1F . As a result, Ms atoms contained in the Cu—Mn alloy layer  13 CM are transported to the surface of the Cu wiring pattern  13 P, and the transported Mn atoms react with oxygen and Si atoms existing in the silicon dioxide film  14 , thereby forming a manganese oxide film  13 MOx having a composition of MnSi x O y  on the surface of the Cu wiring pattern  13 P. 
         [0041]    This process may exclude the use of a SiN film or other kinds of etching stopper films with a high dielectric constant, which is placed between the insulating films  12  and  14  in a known method, and is expected to further reduce the parasitic capacitance of the Cu wiring pattern  13 P. 
         [0042]    It should be noted that the Cu—Mn alloy layer  13 CM existing between the Cu wiring pattern  13 P and the barrier metal film  13 BM releases Mn atoms and this transportation of Mn atoms completely blurs the boundary between the Cu—Mn alloy layer  13 CM and the Cu wiring pattern  13 P. 
         [0043]    The wiring structure containing the Cu wiring pattern  13 P shown in  FIG. 1F  may have an insufficient performance of the manganese oxide film  13 MOx as a diffusion barrier. For example, Cu wiring patterns  13 P formed side-by-side as shown in  FIG. 2  could possibly generate a potential difference between themselves so that Cu ions released from one Cu wiring pattern  13 P 1  would diffuse into the other Cu wiring pattern  13 P 2 , thereby leading to a short circuit. 
         [0044]    However, surfaces of the Cu wiring patterns  13 P 1  and  13 P 2  other than the top surfaces are coated with a barrier metal film  13 BM and thus diffusion of Cu atoms therefrom may be prevented. 
         [0045]    In addition, These discusses a technique to make up for the insufficient performance of the above-mentioned manganese oxide film  13 MOx as a diffusion barrier by covering the manganese oxide film  13 MOx with a barrier film such as a SiCN film as shown in  FIGS. 3A to 3D . It should be noted that the components in  FIGS. 3A to 3D  that have already been described above are numbered with the reference numerals used in the previous explanation to avoid repetition. 
         [0046]    The structure illustrated in  FIG. 3A  is equivalent to that shown in  FIG. 1D  and thus formed through the steps described by  FIGS. 1A to 1C . In  FIG. 3B , a silicon dioxide film  15  having a composition identical or similar to that of the silicon dioxide film  12  described earlier is formed on the structure shown in  FIG. 3A . Then, this structure is heated at a temperature of approximately 400° C. to form a manganese oxide film  13 MOx covering the surface of the Cu wiring pattern  13 P described earlier in the same manner as shown in  FIG. 1F . 
         [0047]    After that, as shown in  FIG. 3C , the silicon dioxide film  15  and a portion of the silicon dioxide film  12  lying therebeneath are removed by wet etching or plasma etching until the manganese oxide film  13 MOx is exposed. 
         [0048]    In this step, it is difficult to stop the wet etching or plasma etching just at the time of the exposure of the manganese dioxide film  13 MOx. Exposing the entire surface of the manganese oxide film  13 MOx requires excessive etching. Therefore, in the structure shown in  FIG. 3C , the upper part of the Cu wiring pattern  13 P supporting the manganese oxide film  13 MOx is also exposed so as to protrude from the insulating film  12 . 
         [0049]    Then, as shown in  FIG. 3D , a diffusion barrier film  16  consisting of a SiCN film is formed on the silicon dioxide film  12  so as to cover the protruding upper part of the Cu wiring pattern  13 P in  FIG. 3C . Thereafter, the next insulating film  17  is formed on this diffusion barrier film  16  as shown in  FIG. 3E . 
         [0050]    It should be noted that the upper part of the Cu wiring pattern  13 P protrudes from the surface of the insulating film  12  as shown in  FIG. 3D  and accordingly the diffusion barrier film  16  has a protrusion  16 P. This causes the insulating film  17  to have a protrusion  17 P as shown in  FIG. 3E . 
         [0051]    After that, the damascene process is applied to the inside of the insulating film  17  in the same manner as described earlier to form a Cu wiring pattern  18 P that is supported by a barrier metal film  18 BM and is coated with a manganese oxide film  19  as shown in  FIG. 3F . 
         [0052]    However, in such a structure, each upper Cu wiring pattern  18 P extends so as to cross over the bumps made by the lower Cu wiring patterns  13 P. This makes it likely that the upper Cu wiring patterns  18 P and the lower Cu wiring patterns  13 P become short-circuited. 
         [0053]      FIG. 4  is a diagram illustrating a configuration of a semiconductor device according to Embodiment 1, and  FIGS. 5A to 5M  and  FIG. 6  are diagrams illustrating a manufacturing process of the semiconductor device. 
         [0054]    In  FIG. 4 , element regions  41 A and  41 B are defined on a silicon substrate  41  by element-isolating structures  41 I. On the element region  41 A, a gate insulating film  42 A is positioned on the silicon substrate  41  and a gate electrode  43 A made of polysilicon or the like is formed thereon, whereas on the element region  41 B, a gate insulating film  42 B is positioned on the silicon substrate  41  and a gate electrode  43 B made of polysilicon or the like is formed thereon. 
         [0055]    The gate electrode  43 A has side walls coated with insulating films and, at both sides of this gate electrode  43 A, diffusion regions  41   a  and  41   b  are formed by ion implantation in the element region  41 A of the silicon substrate  41 . Similarly, the gate electrode  43 B also has side walls coated with insulating films and, at both sides of this gate electrode  43 B, diffusion regions  41   c  and  41   d  are formed by ion implantation in the element region  41 B of the silicon substrate  41 . As a result, transistors Tr 1  and Tr 2  are formed in the element regions  41 A and  41 B, respectively. 
         [0056]    The gate electrodes  43 A and  43 B are covered with an insulating film  43  formed on the silicon substrate  41 , and a multilayer wiring structure  20  is formed on this insulating film  43 . This multilayer wiring structure  20  will be detailed below. 
         [0057]    As shown in  FIG. 4 , the multilayer wiring structure  20  has a so-called low-k interlayer insulating film  22  formed on the insulating film  43 . Examples of this low-k interlayer insulating film  22  may include an MSQ film with a dielectric constant of 2.6, a hydrocarbon polymer film such as SiLK or Porous SiLK (registered trademarks of The Dow Chemical Company), and a SiOC film produced by plasma chemical vapor deposition (CVD). 
         [0058]    The interlayer insulating film  22  is coated with a carbon-including insulating film  24  that contains carbon (C) and silicon (Si), has a thickness in the range of 15 nm to 30 nm, and preferably consisting of a SiC film or a SiCN film. As described later, this carbon-including insulating film  24  further includes oxygen (O). 
         [0059]    On the carbon-including insulating film  24 , a low-k interlayer insulating film equivalent to the above-mentioned low-k interlayer insulating film  22  is formed so as to have a thickness, for example, in the range of 250 nm to 300 nm. This low-k interlayer insulating film  25  is coated with a carbon (as well as silicon and oxygen)—including insulating film  27  that is equivalent to the above-mentioned carbon-including insulating film  24  and has a thickness in the range of 15 nm to nm. 
         [0060]    Furthermore, on the carbon-including insulating film  27 , a low-k interlayer insulating film  28  equivalent to the above-mentioned low-k interlayer insulating films  22  and  25  is formed so as to have a thickness, for example, in the range of 250 nm to 300 nm. This low-k interlayer insulating film  28  is also coated with a carbon (as well as silicon and oxygen)—including insulating film  30  that is equivalent to the above-mentioned carbon-including insulating films  24  and  27  and has a thickness in the range of 15 nm to 30 nm. 
         [0061]    Through the interlayer insulating film  22 , wiring trenches  22 T 1  and  22 T 2  are carved, which are filled with Cu wiring patterns  23 P and  23 Q, respectively. Side walls of these wiring trenches  22 T 1  and  22 T 2  are each coated with a barrier metal film  23 BM consisting of a high-melting-point metal such as Ta, Ti, or W, or a conductive nitride thereof such as TaN, TiN, or WN. Strictly speaking, the adjective “metal” may not be used to describe a barrier metal film  23 BM consisting of a conductive nitride. However, in the present embodiment, such a barrier film is also referred to as “a barrier metal film” in accordance with established practice. Meanwhile, the top of the Cu wiring pattern  23 P is covered with a manganese oxide film  23 MOx that includes carbon, has a composition of MnSi x O y C z  (x=0.3 to 1.0; y=0.75 to 3.0; z=0.2 to 0.7), and formed along the carbon-including insulating film  24  so as to have a thickness approximately in the range of 1 nm to 5 nm. Such a manganese oxide film  23 MOx is also formed on the top of the Cu wiring pattern  23 Q. A more detailed description of this manganese oxide film  23 MOx will be provided later. 
         [0062]    As described later, the boundary between the Cu wiring pattern  23 P and the barrier metal film  23 BM consists of a manganese oxide film  23 MOy formed so as to have a thickness in the range of 1 nm to 5-nm and a composition different from that of the manganese oxide film  23 MOx. This manganese oxide film  23 MOy includes no or little carbon and Si, and the concentrations of these elements included therein are substantially lower than those in the manganese oxide film  23 MOx, if any. For example, the manganese oxide film  23 MOy has a composition of MnO p C q  (p=0.5 to 1.5; q=0.01 to 0.05; q&lt;z). 
         [0063]    Through the interlayer insulating film  25 , wiring trenches  25 T 1 ,  25 T 2 , and  25 T 3  are carved, and these wiring trenches  25 T 1 ,  2 ST 2 , and  2 ST 3  are filled with Cu wiring patterns  26 P,  26 Q, and  26 R, respectively. The lower part of the Cu wiring pattern  26 P forms a Cu via plug  26 V, which extends through the manganese oxide film  23 MOx to make an electrical contact with the Cu wiring pattern  23 P. 
         [0064]    The side walls of the wiring trenches  25 T 1 ,  25 T 2 , and  2 ST 3  are each coated with a barrier metal film  26 BM equivalent to the barrier metal film  23 BM. On the top of the Cu wiring pattern  26 P, a manganese oxide film  26 MOx equivalent to the manganese oxide film  23 MOx is formed along the carbon-including insulating film  27  so as to have a thickness approximately in the range of 1 nm to 5 nm. Such a manganese oxide film  26 MOx is also formed on the top of the Cu wiring patterns  26 Q and  26 R. 
         [0065]    The boundary between the Cu wiring pattern  26 P and the barrier metal film  26 BM consists of a manganese oxide film  26 MOy that is equivalent to the manganese oxide film  23 MOy and formed so as to have a thickness in the range of 1 nm to 5 nm. 
         [0066]    Through the interlayer insulating film  28 , wiring trenches  28 T 1  and  28 T 2  are carved, and these wiring trenches  28 T 1  and  28 T 2  are filled with Cu wiring patterns  29 P and  29 Q, respectively. The lower part of the Cu wiring pattern  29 P forms a Cu via plug  29 V, which extends through the manganese oxide film  26 MOx to make an electrical contact with the Cu wiring pattern  26 P. 
         [0067]    The side walls of the wiring trenches  28 T 1  and  28 T 2  are each coated with a barrier metal film  29 BM equivalent to the barrier metal films  23 BM and  26 BM. On the top of the CU wiring pattern  29 P, a manganese oxide film  29 MOx equivalent to the manganese oxide films  23 MOx and  26 MOx is formed along the carbon-including insulating film  30  so as to have a thickness approximately in the range of 1 nm to 5 nm. Such a manganese oxide film  29 MOx is also formed on the top of the Cu wiring pattern  29 Q. 
         [0068]    The boundary between the Cu wiring pattern  29 P and the barrier metal film  29 BM consists of a manganese oxide film  29 MOy that is equivalent to the manganese oxide films  23 MOy and  26 MOy and formed so as to have a thickness in the range of 1 nm to 5 nm. 
         [0069]    In a semiconductor device  40  having the multilayer wiring structure  20  configured as above, each of the insulating films  23 MOx,  26 MOx, and  29 MOx formed on the Cu wiring patterns  23 P and  23 Q,  26 P to  26 R, and  29 P and  29 Q, respectively, includes a substantial amount of carbon as described above, and this reduces interatomic distances inside the films, thereby providing stronger chemical bonds. As a result, these insulating films act as excellent diffusion barriers and effectively prevent diffusion of Cu atoms constituting wiring patterns into low-dielectric-constant interlayer insulating films, thereby avoiding short circuits and other defects. 
         [0070]    Next, a manufacturing process of the semiconductor device  40 , in particular, a process of forming the multilayer wiring structure, is described with reference to  FIGS. 5A to 5L  and  FIG. 6 . 
         [0071]    In  FIG. 5A , the insulating film  43  is formed on the silicon substrate  41  so as to cover the transistors Tr 1  and Tr 2 , and then the interlayer insulating film  22  is formed on the insulating film  43 . Examples of this interlayer insulating film  22  may include an MSQ film or other SiO 2 -based low-dielectric-constant films formed by a coating method, a hydrocarbon polymer film such as SiLK or Porous SiLK (registered trademarks of The Dow Chemical Company), and a SiOC film produced by plasma CVD. 
         [0072]    In the next step, the wiring trench  22 T 1  is carved through the interlayer insulating film  22  as shown in  FIG. 5B . Although not shown in the drawing, the wiring trench  22 T 2  is also carved through the interlayer insulating film  22 . 
         [0073]    Then, as shown in  FIG. 5C , the barrier metal film  23 BM is formed on the interlayer insulating film  22  by sputtering of a Ta film, Ti film, or W film at room temperature so as to have the cross-sectional shape fitting the wiring trench  22 T 1  and have a thickness in the range of 2 nm to 5 nm. To form this barrier metal film  23 BM, reactive sputtering of a conductive nitride film such as a TaN film, TiN film, or WN film under nitrogen atmosphere may be used. The temperature of the substrate required for sputtering is approximately 400° C. Although not shown in the drawing, such a barrier metal film  23 BM is also formed on the wiring trench  22 T 2 . 
         [0074]    In the step shown in  FIG. 5C , a Cu—Mn alloy layer  23 CM is also formed on the barrier metal film  23 BM by sputtering of Cu—Mn alloy at room temperature. This Cu—Mn alloy layer  23 CM includes Mn atoms at a concentration in the range of 0.2 to 1.0 atomic percent or preferably at a concentration equal to or less than 0.5 atomic percent, has the cross-sectional shape fitting the wiring trench  22 T 1 , and has a thickness in the range of 5 nm to 30 nm. Although not shown in the drawing, such a Cu—Mn alloy layer  23 CM is also formed on the wiring trench  22 T 2 . 
         [0075]      FIG. 5C  also includes a Cu layer  23 , which is formed on the Cu—Mn alloy layer  23 CM by seed layer formation and electrolytic plating so as to fill the wiring trench  22 T 1  and, although not shown in the drawing, the wiring trench  22 T 2  as well. 
         [0076]    Thereafter, as shown in  FIG. 5D , the Cu layer  23 , and the Cu—Mn alloy layer  23 CM and the barrier metal films  23 BM formed therebeneath are shaved by CMP until the surface of the interlayer insulating film  22  is exposed. This results in the formation of the Cu wiring pattern  23 P in the wiring trench  22 T 1  and, although not shown in the drawing, the Cu wiring pattern  23 Q in the wiring trench  22 T 2 . 
         [0077]    In this embodiment, the structure obtained in  FIG. 5D  is then coated with the carbon-including insulating film  24  having a thickness in the range of 15 nm to 30 nm as shown in  FIG. 5E . The carbon-including insulating film  24  used in this embodiment is a SiCN film, which is formed by plasma CVD of a material including Si and C such as trimethylsilane (SiH(CH 3 ) 3 ) and a different material including nitrogen such as NH 3  with the substrate temperature being, for example, in the range of 350 to 400° C. Oxygen is added in the course of forming the carbon-including insulating film  24  so that the entire film includes oxygen at a concentration in the range of 3 to 18 atomic percent. 
         [0078]    During this step shown in  FIG. 5E , heat generated by the formation of the carbon-including insulating film  24  transports Mn atoms existing in the Cu—Mn alloy layer  23 CM to the surface of the Cu wiring pattern  23 P as shown in  FIG. 6 . The transported Mn atoms react with Si, carbon, and oxygen atoms supplied by the carbon-including insulating film  24 . As a result, a manganese oxide film  23 MOx is formed on the surface of the Cu wiring pattern  23 P while spreading along the carbon-including insulating film  24 . The manganese oxide film  23 MOx formed in this way has a composition of MnSi x O y C z  including composition parameters x, y, and z. 
         [0079]    A manganese oxide film  23 MOx was actually prepared in the same way and analyzed by energy dispersive X-ray spectroscopy (EDX). This analysis found that the composition parameter x was in the range of 0.3 to 1.0, y was in the range of 0.75 to 3.0, and z was in the range of 0.2 to 0.7. Furthermore, secondary ion mass spectroscopy (SIMS) of a sample structure wherein a flat Cu—Mn film was coated with a Cu film and the Cu film was then coated with a SiCN film and the entire structure was heated at a temperature of 400° C. also demonstrated that this method, wherein a SiCN film is formed in contact with a Cu—Mn film, may be used to provide a manganese oxide film that has a composition of MnSi x O y C z  and spreads between the SiCN and Cu—Mn films. 
         [0080]    The step represented by  FIG. 5E  also involves transportation of a small number of oxygen atoms from the interlayer insulating film  22  through the barrier metal film  23 BM to the Cu wiring pattern  23 P during heat treatment associated with the formation of the carbon-including insulating film  24 . As shown in  FIG. 6 , such oxygen atoms react with some of Mn atoms initially included in the Cu—Mn alloy layer  23 CM, thereby producing another manganese oxide film  23 MOy between the barrier metal film  23 BM and the Cu wiring pattern  23 P. This manganese oxide film  23 MOy includes no or little carbon and Si, and the concentrations of these elements included therein are lower than those in the manganese oxide film  23 MOx, if any. Therefore, the manganese oxide film  23 MOy produced in this way has a composition of MnO p C q  wherein the composition parameter p is in the range of 0.5 to 1.5 and q is in the range of 0.01 to 0.05, as described earlier. It should be noted that q is smaller than z. 
         [0081]    The original Cu—Mn alloy layer  23 CM is reduced as such manganese oxide films  23 MOx and  23 MOy are formed and finally disappears at the end of the step represented by  FIG. 5E  due to replacement with a Cu layer serving as a part of the Cu wiring pattern  23 P. 
         [0082]    In the next step shown in  FIG. 5F , the structure illustrated by  FIG. 5E  is covered with the interlayer insulating film  25  formed in the same manner as the interlayer insulating film  22 . After that, as shown in  FIG. 5G , a wiring trench  2 ST 1  and a via hole  25 V 1  are carved in preparation for the formation of the Cu wiring pattern  26 P, and this exposes the Cu wiring pattern  23 P under the wiring trench  25 T 1  and the via hole  25 V 1 . At the same time, the wiring trenches  25 T 2  and  25 T 3  are carved through the interlayer insulating film  25  in preparation for the formation of the Cu wiring patterns  26 Q and  26 R, respectively. 
         [0083]    Then, as shown in  FIG. 5H , the barrier metal film  26 BM is formed on the interlayer insulating film  25 , which is illustrated in  FIG. 5G , by sputtering of a Ta film, Ti film, or W film at room temperature so as to have the cross-sectional shape fitting the wiring trench  25 T 1  and has a thickness in the range of 2 nm to 5 nm. To form this barrier metal film  26 BM, reactive sputtering of a conductive nitride film such as a TaN film, TiN film, or WN film under nitrogen atmosphere may be used. The temperature of the substrate required for sputtering is approximately 400° C. Although not shown in the drawing, such a barrier metal film  26 BM is also formed on the wiring trenches  25 T 2  and  25 T 3 . 
         [0084]    In the step shown in  FIG. 5H , a Cu—Mn alloy layer  26 CM is also formed on the barrier metal film  26 BM by sputtering of Cu—Mn alloy at room temperature. This Cu—Mn alloy layer  26 CM includes Mn atoms at a concentration in the range of 0.2 to 1.0 atomic percent, has the cross-sectional shape fitting the wiring trench  25 T 1 , and has a thickness in the range of 5 nm to 30 nm. Although not shown in the drawing, such a Cu—Mn alloy layer  26 CM is also formed on the wiring trenches  25 T 2  and  25 T 3 . 
         [0085]      FIG. 5H  also includes a Cu layer  26 , which is formed on the Cu—Mn alloy layer  26 CM by seed layer formation and electrolytic plating so as to fill the wiring trench  25 T 1  and, although not shown in the drawing, the wiring trenches  25 T 2  and  25 T 3  as well. 
         [0086]    Thereafter, as shown in  FIG. 5I , the Cu layer  26 , and the Cu—Mn alloy layer  26 CM and the barrier metal film  26 BM formed therebeneath are shaved by CMP until the surface of the interlayer insulating film  25  is exposed. This results in the formation of the Cu wiring pattern  26 P in the wiring trench  25 T 1  and, although not shown in the drawing, the Cu wiring patterns  26 Q and  26 R in the wiring trenches  25 T 2  and  25 T 3 , respectively. 
         [0087]    In this embodiment, the structure obtained in  FIG. 5I  is then coated with the carbon-including insulating film  27  having a thickness in the range of 15 nm to 30 nm as shown in  FIG. 53 . The carbon-including insulating film  27  used in this embodiment is a SiCN film, which is formed by plasma CVD of a material including Si and C such as trimethylsilane (SiH(CH 3 ) 3 ) and a different material including nitrogen such as NH 3  with the substrate temperature being, for example, in the range of 350 to 400° C. Oxygen is added in the course of forming the carbon-including insulating film  27  so that the entire film includes oxygen at a concentration in the range of 3 to 18 atomic percent. 
         [0088]    During this step shown in  FIG. 53 , heat generated by the formation of the carbon-including insulating film  27  transports Mn atoms existing in the Cu—Mn alloy layer  26 CM to the surface of the Cu wiring pattern  26 P as described earlier using  FIG. 6 . The transported Mn atoms react with Si, carbon, and oxygen atoms supplied by the carbon-including insulating film  27 . As a result, a manganese oxide film  26 MOx having a composition of MnSi x O y C z  is formed on the surface of the Cu wiring pattern  26 P while spreading along the carbon-including insulating film  27 , in the same manner as the manganese oxide film  23 MOx. 
         [0089]    The step represented by  FIG. 5J  also involves transportation of a small number of oxygen atoms from the interlayer insulating film  25  through the barrier metal film  26 BM to the Cu wiring pattern  26 P during heat treatment associated with the formation of the carbon-including insulating film  27 . As described earlier using  FIG. 6 , such oxygen atoms react with some of Mn atoms initially included in the Cu—Mn alloy layer  26 CM, thereby producing another manganese oxide film  26 MOy between the barrier metal film  26 BM and the Cu wiring pattern  26 P (via plug  26 V) in the same manner as the manganese oxide film  23 MOy. This manganese oxide film  26 MOy includes no or little carbon and Si, and the concentrations of these elements included therein are lower than those in the manganese oxide film  26 MOx, if any. 
         [0090]    Also in this case, the original Cu—Mn alloy layer  26 CM is reduced as such manganese oxide films  26 MOx and  26 MOy are formed and finally disappears at the end of the step represented by  FIG. 53 . 
         [0091]    In the next step shown in  FIG. 5K , the structure illustrated by  FIG. 53  is covered with the interlayer insulating film  28  formed in the same manner as the interlayer insulating films  22  and  25 . Then, the steps shown in  FIGS. 5G to 51  are repeated to carve the wiring trench  28 T 1  through the interlayer insulating film  28 , to cover the wiring trench  28 T 1  with the barrier metal film  29 BM, and then to fill the wiring trench  28 T 1  with the Cu wiring pattern  29 P. After that, in the upper part of the Cu wiring pattern  29 P, the manganese oxide film  29 MOx is formed in the same manner as the manganese oxide films  23 MOx and  26 MOx along a carbon-including insulating film  30  formed as with the carbon-including insulating film  27 . In the boundary between the Cu wiring pattern  29 P and the barrier metal film  29 BM, the manganese oxide film  29 MOy is formed in the same manner as the manganese oxide films  23 MOy and  26 MOy. 
         [0092]      FIG. 7  shows the result of a time-dependent dielectric breakdown test (TDDB test) conducted using a semiconductor device  40  having the multilayer wiring structure  20  configured as above. 
         [0093]    In  FIG. 7 , “(d) CONVENTIONAL ART” indicates the result obtained using a standard device that was tested as a control of the present embodiment and corresponds to the structure described earlier using  FIG. 2 . This standard device was configured as follows: the Cu wiring patterns  13 P each having a width of 70 nm were arranged at intervals of 70 nm; the barrier metal film  13 BM had a thickness of 2 nm; and the manganese oxide film  13 MOx had a thickness of 20 nm and a composition of MnSi x O y  wherein the composition parameter x is 0.3 and y is 0.5. 
         [0094]    “(c) WITHOUT Mn” in  FIG. 7  indicates the result obtained using another standard device tested as a control, which was prepared excluding the formation of the Cu—Mn alloy layer  23 CM in the steps shown in  FIGS. 5A to 5E  and thus had no manganese oxide film  23 MOx on the top of Cu wiring patterns  23 P 1  and  23 P 2  as shown in  FIG. 8A . In this standard device, the formation of the manganese oxide films  23 MOy, which would have been formed on the side walls and the bottom of the Cu patterns, was accordingly omitted. It should be noted that the components in  FIG. 8A  that have already been described above are numbered with the reference numerals used in the previous explanation to avoid repetition. For comparison, this standard device included the interlayer insulating films  22  and  25  having the same composition and the same thickness as those of the interlayer insulating films  12  and  14  shown in  FIG. 2  as well as a barrier metal film  23 BM having the same composition and the same thickness as the barrier metal film  13 BM shown in  FIG. 2 . The width and intervals of the Cu wiring patterns  23 P 1  and  23 P 2  were the same as those used in the standard device illustrated in  FIG. 2 . 
         [0095]    “(a) EMBODIMENT 1” in  FIG. 7  indicates the result obtained using the device that corresponds to Embodiment 1 described earlier and thus Cu wiring patterns  23 P 1  and  23 P 2  thereof were formed in the steps described using  FIGS. 5A to 5F , as illustrated in  FIG. 8B . It should be noted that the components in  FIG. 8B  that have already been described above are numbered with the reference numerals used in the previous explanation to avoid repetition. For comparison, this device included the interlayer insulating films  22  and  25  having the same composition and the same thickness as those of the interlayer insulating films  12  and  14  shown in  FIG. 2  as well as a barrier metal film  23 BM having the same composition and the same thickness as the barrier metal film  13 BM shown in  FIG. 2 . The width and interval of the Cu wiring patterns  23 P 1  and  23 P 2  were the same as those used in the standard device illustrated in  FIG. 2 . 
         [0096]    “(b) EMBODIMENT 2” in  FIG. 7  indicates the result obtained using Embodiment 2, which will be described later. 
         [0097]    In this test summarized in  FIG. 7 , a voltage of 30 V was applied between adjacent Cu wiring patterns of each device at a temperature of 150° C. and the time to dielectric breakdown was measured. 
         [0098]    The TDDB values on the vertical axis of  FIG. 7  have been normalized with respect to the value for the standard device shown in “(d) CONVENTIONAL ART.” As is obvious from the graph, the TDDB value of the other standard device shown on “(c) WITHOUT Mn” is almost equal to that shown in “(d) CONVENTIONAL ART.” This means that the carbon-including film  24  itself has little or no ability to prevent diffusion of Cu atoms. 
         [0099]    On the other hand, the TDDB value of the device corresponding to Embodiment 1 and shown in “(a) EMBODIMENT 1” is more than 12 times higher than that of the standard device tested as a control. 
         [0100]    Therefore, it may be said that, among others, the manganese oxide film  23 MOx including carbon exhibits especially high performance in preventing diffusion of Cu atoms and that the semiconductor device  40  configured according to Embodiment 1 so as to have such a manganese oxide film  23 MOx and the equivalents thereof, i.e., manganese oxide films  26 MOx and  29 MOx, acquires a long service life. 
         [0101]      FIGS. 9A to 9K  are diagrams illustrating a manufacturing process of a semiconductor device according to Embodiment 2. It should be noted that the components in  FIGS. 9A to 9K  that have already been described above are numbered with the reference numerals used in the previous explanation to avoid repetition. 
         [0102]      FIG. 9A  corresponds to the structure shown in  FIG. 5D  with the exception that the interlayer insulating film  22  is a low-dielectric-constant SiO 2  film resistant to etching of a hydrocarbon polymer film, such as an MSQ film. 
         [0103]    In Embodiment 2, as shown in  FIG. 9B , a carbon-including film  31  is formed on the structure illustrated by  FIG. 9A  so as to cover the top of the interlayer insulating film  22  and that of the Cu wiring pattern  23 P. This carbon-including film  31  is, for example, a hydrocarbon polymer film commercially available under the name of SiLK (registered trademarks of The Dow Chemical Company) or a similar film that includes carbon (C) and oxygen, is resistant to heat treatment at a temperature in the range of 350 to 400° C., and allows selective etching of the interlayer insulating film  22  existing therebeneath. 
         [0104]    Then, the structure shown in  FIG. 9B  is heated at a temperature in the range of 350 to 400° C. under inert atmosphere or, more typically, nitrogen atmosphere. Thereafter, a manganese oxide film  33 MOx whose composition is represented using composition parameters s and t (MnO s C t ) is formed so as to cover the top of the Cu wiring pattern  23 P while spreading along the hydrocarbon polymer film  31 . More specifically, the manganese oxide film  33 MOx is formed from Mn atoms initially included in the Cu—Mn alloy layer  23 CM and oxygen and carbon atoms supplied by the hydrocarbon polymer film  31  through the reaction thereof so as to have a thickness in the range of 1 nm to 5 nm. The composition parameters s and t of the manganese oxide film  33 MOx formed in this way are 0.75 to 3.0 and 0.2 to 0.7, respectively. 
         [0105]    Furthermore, oxygen atoms that are released from the interlayer insulating film  22  penetrate through the barrier metal film  23 BM into the Cu wiring pattern  23 P and then react with Mn atoms existing in the Cu—Mn alloy layer  23 CM, thereby producing a manganese oxide film  33 MOy spreading between the Cu wiring pattern  23 P and the barrier metal film  23 BM. This manganese oxide film  33 MOy has a composition represented using composition parameters u and v (MnO u C v ) wherein the composition parameter v is zero or any number less than t (v&lt;t). 
         [0106]    Embodiment 2 further involves the step shown in  FIG. 9D , wherein the carbon-including film  31  was removed through the process of selective etching or ashing so as to expose the interlayer insulating film  22  and the manganese oxide film  33 MOx preferentially. 
         [0107]    Subsequently, as shown in  FIG. 9E , the structure illustrated by  FIG. 9D  is covered with the next interlayer insulating film  25  consisting of an MSQ film or a similar silicon oxide film. After that, a wiring trench  25 T 1  and a via hole  25 V 1  are carved through the interlayer insulating film  25  so that the Cu wiring pattern  23 P is exposed, as shown in  FIG. 9F . 
         [0108]    Furthermore, as shown in  FIG. 9G , the interlayer insulating film  25  seen in  FIG. 9F  is coated with the barrier metal film  26 BM and then with the Cu—Mn alloy film  26 CM in the same manner as the step described using  FIG. 5H  so that the coating layers have the cross-sectional shape fitting the wiring trench  2 ST 1 . 
         [0109]      FIG. 9G  also includes a Cu layer  26 , which is formed on the Cu—Mn alloy layer  26 CM by seed layer formation and electrolytic plating so as to fill the wiring trench  25 T 1  and the via hole  25 V 1 . 
         [0110]    Thereafter, as shown in  FIG. 9H , the Cu layer  26 , and the Cu—Mn alloy layer  26 CM and the barrier metal layer  26 BM formed therebeneath are shaved by CMP until the surface of the interlayer insulating film  25  is exposed. This results in the formation of the Cu wiring pattern  26 P in the wiring trench  25 T 1  and, although not shown in the drawing, the Cu wiring patterns  26 Q and  26 R in the wiring trenches  25 T 2  and  25 T 3 , respectively. 
         [0111]    In this embodiment, the structure obtained in  FIG. 9H  is then coated with the carbon-including film  32  having the same composition as the carbon-including film  31  and a thickness in the range of 15 nm to 30 nm as shown in  FIG. 9I , and then this structure is heated at a temperature in the range of 350 to 400° C. This heat treatment makes Mn atoms existing in the Cu—Mn alloy layer  26 CM move to the surface of the Cu wiring pattern  26 P and react with carbon and oxygen atoms supplied by the carbon-including film  32  there as described earlier using  FIG. 6 . As a result, a manganese oxide film  36 MOx having a composition of MnO s C t  described earlier is formed on the surface of the Cu wiring pattern  26 P while spreading along the carbon-including film  32 , in the same manner as the manganese oxide film  33 MOx. 
         [0112]    The step represented by  FIG. 9I  also involves transportation of a small number of oxygen atoms from the interlayer insulating film  25  through the barrier metal film  26 BM to the Cu wiring pattern  26 P during the heat treatment. As described earlier using  FIG. 6 , such oxygen atoms react with some of Mn atoms initially included in the Cu—Mn alloy layer  26 CM, thereby producing another manganese oxide film  36 MOy between the barrier metal film  26 BM and the Cu wiring pattern  26 P (via plug  26 V) in the same manner as the manganese oxide film  33 MOy. This manganese oxide film  36 MOy includes no carbon or carbon at any concentration lower than that in the manganese oxide film  36 MOx. 
         [0113]    Also in this case, the original Cu—Mn alloy layer  26 CM is reduced as such manganese oxide films  36 MOx and  36 MOy are formed and finally disappears at the end of the step represented by  FIG. 9I . 
         [0114]    In the next step shown in  FIG. 9J , the structure illustrated by  FIG. 9I  is covered with the interlayer insulating film  28  formed in the same manner as the interlayer insulating films  22  and  25 . Then, the steps shown in  FIGS. 9E to 9I  are repeated to carve the wiring trench  28 T 1  through the interlayer insulating film  28 , to cover the wiring trench  28 T 1  with the barrier metal film  29 BM, and then to fill the wiring trench  28 T 1  with the Cu wiring pattern  29 P. After that, in the upper part of the Cu wiring pattern  29 P, an additional carbon-including insulating film is formed in the same manner as the carbon-including film  30 , and the manganese oxide film  39 MOx is formed in the same manner as the manganese oxide films  33 MOx and  36 MOx along the additional carbon-including film. Between the Cu wiring pattern  29 P and the barrier metal film  29 BM, the manganese oxide film  39 MOy is formed in the same manner as the manganese oxide films  33 MOy and  36 MOy. It should be noted that  FIG. 9K  represents the structure obtained by removing the additional carbon-including insulating film after the process described above. 
         [0115]    The result of the TDDB test conducted using the multilayer wiring structure prepared in accordance with Embodiment 2 is also shown in  FIG. 7  as “(b) EMBODIMENT 2.” This test involved a semiconductor device equivalent to that shown in  FIG. 8B  with exceptions that the interlayer insulating film  25  was formed directly on the interlayer insulating film  22  and that the manganese oxide films  33 MOx and  33 MOy were used instead of the manganese oxide films  23 MOx and  23 MOy as shown in  FIG. 10 . This device also employed an interval of 70 nm between adjacent Cu wiring patterns as well as the other tested devices. 
         [0116]    As clearly seen in  FIG. 7 , the TDDB value of the device corresponding to Embodiment 2 is also more than 12 times higher than that of the standard device tested as a control. 
         [0117]    Meanwhile,  FIG. 11  represents the result of short-circuit study, wherein a test structure in which upper Cu wiring patterns  18 P extend while crossing over the lower Cu wiring patterns  13 P, like one described earlier using  FIG. 3F , was prepared through the steps shown in  FIGS. 9A to 9K  and then occurrences of short circuits between the upper and lower Cu wiring patterns were monitored. As shown in  FIG. 12 , this test structure includes the lower Cu wiring patterns  13 P and the upper Cu wiring patterns  18 P arranged so as to be perpendicular to each other, and the interval between adjacent Cu wiring patterns was set at 70 nm for both upper and lower patterns. In addition, the structure used in this test was configured without the via plugs  26 V and  29 V. 
         [0118]    As seen in  FIG. 11 , the occurrence rate of short circuits was approximately in the range of 2 to 3% in the semiconductor device prepared in accordance with Embodiment 2, whereas the occurrence rate of short circuits was higher than 85% in the standard device as a control prepared in the steps shown in  FIGS. 3A to 3F . In this standard device prepared in the steps shown in  FIGS. 3A to 3F , the diffusion barrier film  16  had a bump with a height of 30 nm due to the Cu wiring pattern  13 P and the height of the interlayer insulating film  17  was 300 nm. 
         [0119]    The result shown in  FIG. 11  probably reflects the fact that the present embodiment employs a lower interlayer insulating film  22  and a manganese oxide film  33 MOx both resistant to etching and thus no bump is formed after the hydrocarbon polymer film  31  is removed by dry etching or ashing in the step shown in  FIG. 9D . 
         [0120]    Meanwhile, in the present embodiment, the interlayer insulating films  22 ,  25 , and  28  do not always have to consist of an MSQ film. Although having a higher dielectric constant, a silicon oxide film produced by plasma CVD of tetraethoxysilane (TEOS) may also be used depending on the intended application. 
         [0121]    The many features and advantages of the embodiments are apparent from the detailed specification and, thus, it is intended by the appended claims to cover all such features and advantages of the embodiments that fall within the true spirit and scope thereof. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the inventive embodiments to the exact construction and operation illustrated and described, and accordingly all suitable modification and equivalents may be resorted to, falling within the scope thereof.