Abstract:
A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires.

Description:
RELATED APPLICATIONS 
     This application is a Division of U.S. patent application Ser. No. 13/670,711 filed on Nov. 7, 2012. 
    
    
     TECHNICAL FIELD 
     The present invention relates to the field of integrated circuit technology; more specifically, it relates to copper interconnect structures and methods of making copper interconnect structures. 
     BACKGROUND 
     Copper interconnects are used to interconnect semiconductor devices into circuits. However, current flow in through the interconnect can result in copper migration from the anode end to the cathode end of the interconnect which depletes copper at the anode end of the interconnect resulting in an increase in resistance which will cause the circuit to fail. Accordingly, there exists a need in the art to eliminate the deficiencies and limitations described hereinabove. 
     BRIEF SUMMARY 
     A first aspect of the present invention is a structure, comprising: a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first wire and the second wire. 
     A second aspect of the present invention is a method, comprising: forming a dielectric layer on a substrate; simultaneously forming a first trench and a second trench in the dielectric layer; simultaneously forming a first liner on sidewalls and a bottom of the first trench and a second liner on sidewalls and a bottom of the second trench; simultaneously filling all remaining space in the first trench with a first copper layer to form a first wire in the dielectric layer and filling all remaining space in the second trench with a second copper layer to form a second wire in the dielectric layer; forming a third trench in the dielectric layer; forming a third liner on sidewalls and a bottom of the third trench; and filling all remaining space in the third trench with a third copper layer to form an electromigration stop in the dielectric layer, the electromigration stop between and abutting respective ends of the first wire and the second wire. 
     These and other aspects of the invention are described below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
         FIGS. 1A ,  2 A,  3 A,  4 A,  5 A,  6 A,  7 A,  8 A,  9 A, and  10 A. are top views and  FIGS. 1B ,  2 B,  3 B,  4 B,  5 B,  6 B,  7 B,  8 B,  9 B and  10 B are corresponding cross-sectional views illustrating fabrication of a copper interconnect structure according to embodiments of the present invention; 
       FIGS.  10 B 1  and  10 B 2  are alternative cross-sections through line  10 B- 10 B of  FIG. 10A ; and 
         FIGS. 11A ,  11 B,  12 ,  13 A,  13 B,  14 ,  15 A,  15 B and  16  illustrate exemplary copper interconnect structure layouts according to embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Interconnect structures according to embodiments of the present invention are formed of at least two copper damascene wires connected by a copper damascene electromigration stop. The at least two copper damascene wires and the copper damascene electromigration stop are formed in the same interlevel dielectric layer. The at least two copper damascene wires and the copper damascene electromigration stop include respective copper cores and copper diffusion barrier liners. In a preferred embodiment, here are two copper diffusion barrier liners between the copper cores of the two or more damascene wires and the copper core of the copper damascene electromigration stop. The electromigration stops effectively limit the reservoir of copper available for electromigration. The electromigration stops are placed at the intersection of two, three or four wires or formed periodically between short wire segments to make a longer wire comprising the short wire segments and the electromigration stops. The same damascene process is used to form both the copper damascene wires and the copper damascene electromigration stops. The copper diffusion barrier liners are electrically conductive. 
     A damascene process is one in which wire trenches or via openings are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is formed in the trenches and on a top surface of the dielectric. A chemical-mechanical-polish (CMP) process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the dielectric layer to form damascene wires (or damascene vias). When only a trench and a wire (or a via opening and a via) is formed the process is called single-damascene. 
     A via first dual-damascene process is one in which via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. A trench first dual-damascene process is one in which trenches are formed part way through the thickness of a dielectric layer followed by formation of vias inside the trenches the rest of the way through the dielectric layer in any given cross-sectional view. All via openings are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is formed on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planar with the surface of the dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias. 
     The term damascene wire is intended to include single-damascene wires and dual-damascene wires. Interconnects are comprised of damascene wires embedded in interlevel dielectric (ILD) layers. A wiring level is comprised of its ILD layer and damascene wire and there are usually multiple wiring levels stacked one upon the other and interconnected by the via or via bar portions of dual-damascene wires. 
       FIGS. 1A ,  2 A,  3 A,  4 A,  5 A,  6 A,  7 A,  8 A,  9 A, and  10 A. are top views and  FIGS. 1B ,  2 B,  3 B,  4 B,  5 B,  6 B,  7 B,  8 B,  9 B and  10 B are corresponding cross-sectional views illustrating fabrication of a copper interconnect structure according to embodiments of the present invention.  FIG. 1A  is a top view and  FIG. 1B  is a cross-section view through line  1 B- 1 B of  FIG. 1A . In  FIGS. 1A and 1B  an ILD layer  100  is formed on substrate  105 . Dielectric layer  100  may be formed of one or more layers selected from the group consisting of silicon nitride (Si 3 N 4 ), silicon carbide (SiC), and NBLok (SiC(N,H)) and low K (dielectric constant) materials having a relative permittivity of about  4  or less, examples of which include but are not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), polyphenylene oligomer, methyl doped silica or SiO x (CH 3 ) y  or SiC x O y H y  or SiOCH, organosilicate glass (SiCOH), and porous SiCOH. Other examples include porous or nonporous silicon dioxide (SiO 2 ), fluorinated SiO 2  (FSG), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC) plasma-enhanced silicon nitride (PSiN x ) or NBLock (SiC(N,H)). 
       FIG. 2A  is a top view and  FIG. 2B  is a cross-section view through line  2 B- 2 B of  FIG. 2A . In  FIGS. 2A and 2B  trenches  110 A and  110 B are etched into but not completely through ILD layer  100 . A full thickness region of ILD layer  100  intervenes between ends  112 A and  112 B of respective trenches  110 A and  110 B. In one example, trenches  110 A and  110 B are formed using a photolithographic process to form a patterned photoresist layer, a reactive ion etch (RIE) of ILD layer  100 , and subsequent removal of the patterned photoresist layer. 
       FIG. 3A  is a top view and  FIG. 3B  is a cross-section view through line  3 B- 3 B of  FIG. 3A . In  FIGS. 3A and 3B  an electrically conductive layer  115 A is deposited on the bottom  116 A and  116 B and sidewalls  117 A and  117 B of respective trenches  110 A and  110 B and also on the top surface  118  of ILD layer  100 . Because layer  115 A follows (i.e., conforms to) the contours of trenches  110 A and  110 B it is a conformal layer. In one example, layer  115 A is a diffusion barrier to copper. Layer  115 A may comprise one or more layers. In one example, layer  115 A is comprised of a layer of tantalum TaN contacting ILD layer  100  and a layer of Ta on the TaN layer. In one example, layer  115 A is comprised of a layer of titanium TiN contacting ILD layer  100  and a layer of Ti on the TiN layer. In one example, layer  115 A is comprised of a layer of tungsten nitride WN contacting ILD layer  100  and a layer of W on the W layer. Other layer  115 A materials include cobalt tungsten phosphide (CoWP) and cobalt silicide (CoSi). Other layer  115 A materials include dual layers of cobalt silicide (CoSi 2 )/Co, cobalt nitride (CoN)/Co, cobalt phosphide (CoP)/Co, colbalt boride (CoB)/Co, ruthenium nitride (RuN)/Ru, ruthenium phosphide (Ru 3 P 4 )/Ru and ruthenium boride (RuB)/Ru. 
       FIG. 4A  is a top view and  FIG. 4B  is a cross-section view through line  4 B- 4 B of  FIG. 4A . In  FIGS. 4A and 4B  an electrically conductive copper layer  120 A is formed on the top surface  122  of layer  115 A. In one example, copper layer  120 A is formed by depositing (e.g., evaporating or sputtering) a thin seed copper layer on layer  115 A followed by electroplating a copper layer on the seed layer of sufficient thickness to overfill trenches  110 A and  110 B. 
       FIG. 5A  is a top view and  FIG. 5B  is a cross-section view through line  5 B- 5 B of  FIG. 5A . In  FIGS. 5A and 5B  a CMP is performed to form damascene wires  125 A and  125 B each comprising a liner  115  and a copper core  120  and having respective top surface  127 A and  127 B. After the CMP, respective top surfaces  127 A and  127 B of wires  125 A and  125 B are coplanar with a top surface  128  of ILD layer  100 . 
       FIG. 6A  is a top view and  FIG. 6B  is a cross-section view through line  6 B- 6 B of  FIG. 6A . In  FIGS. 6A and 6B  a cap layer  130  is selectively deposited on the copper cores  120  of wires  125 A and  125 B. While cap layer  130  may overlap liners  115  of wires  125 A and  125 B, it is not deposited on liners  115 . Cap layer  130  is not deposited on ILD layer  100 . Exemplary materials for cap layer  130  include, but are not limited to Co, Ru, W rhodium (Rh) and platinum (Pt). 
       FIG. 7A  is a plan view and  FIG. 7B  is a cross-section view through line  7 B- 7 B of  FIG. 7A . In  FIGS. 7A and 7B  a patterned block mask  135  is formed over capping layer  130 , any exposed edges of liner  115  and top surfaces of ILD layer  100 . Patterned block mask  135  has an opening  140 . Opposing ends  142 A and  142 B of respective wires of wires  125 A and  125 B are exposed in opening  140 . A region of top surface  128  of ILD layer  100  between ends  142 A and  142 B is also exposed in opening. In one example, patterned block mask is photoresist and opening  140  is formed photolithographically. 
       FIG. 8A  is a plan view and  FIG. 8B  is a cross-section view through line  8 B- 8 B of  FIG. 8A . In  FIGS. 8A and 8B  a trench  145  is formed in ILD layer  100  where the ILD layer is not protected by block mask  135  or wires  125 A and  125 B. Capping layer  130  protects wires  125 A and  125 B during the etching process used to form trench  145 . In one example, trench  145  is formed by a RIE process. In  FIG. 8B , a bottom surface  147  of trench  145  is coplanar with respective bottom surfaces  148 A and  148 B of wires  125 A and  125 B. In other words, trench  145  extends into ILD layer  100  the same distance as wires  125 A and  125 B. Alternatively, trench  145  may extend into ILD layer  100  a lesser or greater distance as wires  125 A and  125 B. 
       FIG. 9A  is a plan view and  FIG. 9B  is a cross-section view through line  9 B- 9 B of  FIG. 9A . In  FIGS. 9A and 9B  an electrically conductive layer  150 A is deposited on the exposed surfaces of capping layer  130 , wires  125 A and  125 B and ILD layer  100 . Because layer  150 A follows (i.e., conforms to) the contours of trench  145  it is a conformal layer. Next, an electrically conductive copper layer  155 A is formed on the top surface  157  of layer  150 A. In one example, copper layer  155 A is formed by depositing a thin seed copper layer on layer  150 A followed by electroplating a copper layer on the seed layer of sufficient thickness to overfill trench  145 . In one example, layer  150 A is a diffusion barrier to copper. Layer  150 A may comprise one or more layers. Exemplary materials for layer  150 A are the same as for layer  115 A described supra. 
       FIG. 10A  is a top view and  FIG. 10B  is a cross-section view through line  10 B- 10 B of  FIG. 10A . In  FIGS. 10A and 10B  a CMP is performed to form electromigration stop  160  comprising a liner  150  and a copper core  155  and having a top surface  162 . After the CMP, top surface  162  of electromigration stop  160  is coplanar with respective top surfaces  127 A and  127 B of wires  125 A and  125 B (as well as the top surface of ILD layer  100 ). Electromigration stop  160  is in direct physical and electrical contact with ends  142 A and  142 B of respective wires  125 A and  125 B. Electromigration stop  160  stops copper migration from wire  125 A to wire  125 B and from wire  125 B to wire  125 A. In  FIG. 10B , a bottom surface  163  of electromigration stop  160  is coplanar with respective bottom surfaces  148 A and  148 B of wires  125 A and  125 B. In other words, electromigration stop  160  extends into ILD layer  100  the same distance as wires  125 A and  125 B. Alternatively, electromigration stop  160  may extend into ILD layer  100  a lesser or greater distance than wires  125 A and  125 B extend into ILD layer  100  as illustrated in FIGS.  10 B 1  and  10 B 2 . 
     FIGS.  10 B 1  and  10 B 2  are alternative cross-sections through line  10 B- 10 B of  FIG. 10A . In FIG.  10 B 1 , bottom surface  163  of electromigration stop  160  extends into ILD layer  100  a lesser distance than wires  125 A and  125 B extend into ILD layer  100 . In FIG.  10 B 2 , bottom surface  163  of electromigration stop  160  extends into ILD layer  100  a greater distance than wires  125 A and  125 B extend into ILD layer  100 . 
       FIGS. 11A and 11B  illustrate exemplary copper interconnect structure layouts according to embodiments of the present invention. In  FIG. 11A , a series of wires  200 A,  200 B,  200 C and  200 D (comprised of copper cores  205  and copper diffusion barrier liners  210 ) are interconnected electrically and physically by electromigration stops  215 A,  215 B and  215 C (comprised of copper cores  220  and copper diffusion barrier liners  225 ). The materials of liners  210  and  225  may be the same or different. Wire  200 B has a length L 1  measured between electromigration stops  215 A and  125 B and wire  200 C has a length L 2  measured between electromigration stops  215 B and  125 C. In one example, L 1  and L 2  are less than the Blech length. A wire having a length below the Blech length will not fail by electromigration because mechanical stress buildup causes an atom back flow which reduces or compensates for the electromigration atom flow towards the anode.  FIG. 11B  illustrates that electromigration stops can be used in place of a corner region of a single contiguous wire. In one example, copper diffusion barrier liners  210  and  225  are electrically conductive. Liners  210  and  225  may comprise one or more layers. Exemplary materials for liners  210  and  225  are the same as for layer  115 A described supra. 
       FIG. 12  illustrates an exemplary copper interconnect structure layout according to embodiments of the present invention. In  FIG. 12 , three wires  200 E,  200 F and  200 G (comprised of copper cores  205  and copper diffusion barrier liners  210 ) are interconnected electrically and physically by an electromigration stop  215 D (comprised of copper core  220  and copper diffusion barrier liner  225 ). Wire  200 E is on the opposite side of electromigration stop  215 D from wires  200 F and  200 G. The materials of liners  210  and  225  may be the same or different. The number of wires (three) should be considered exemplary and there can be few as three wires or more than three wires as long as there is at least one wire on a first side of the electromigration stop and are least two wires on a different side (in one example on an opposite side) of the electromigration stop. 
       FIGS. 13A and 13B  illustrate an exemplary copper interconnect structure layout according to embodiments of the present invention.  FIG. 13A  illustrates four mutually orthogonal wires  125 H,  125 I,  125 J and  125 K that are to be interconnected by an electromigration stop. Dashed line  255  indicates the opening in the patterned photoresist layer that defines the topological extents of the electromigration stop (see, for example,  FIG. 7A ) of  FIG. 13B  (and also  FIG. 14 ). In  FIG. 13B , the four wires  125 H,  125 I,  125 J and  125 K (comprised of copper cores  120  and copper diffusion barrier liners  115 ) are interconnected by electromigration stop  235  (comprised of copper core  155  and copper diffusion barrier liner  150 ). Liner  115  and  150  may be the same or different. Wires  125 H and  125 J have a common first longitudinal axis  227  and wires  125 I and  125 K have a common second longitudinal axis  228 . First axis  227  is perpendicular to second axis  228 . Electromigration stop  235  is thus formed at the cardinal intersection of the axes of wires  125 H,  125 I,  125 J and  125 K. 
       FIG. 14  is similar to  FIG. 13B  except only three wires  125 H,  125 I and  125 J are interconnected by an electromigration stop  240  (comprised of copper core  155  and copper diffusion barrier liner  150 ). 
       FIGS. 15A and 15B  illustrate an exemplary copper interconnect structure layout according to embodiments of the present invention.  FIG. 15A  illustrates the same four mutually orthogonal wires  125 H,  125 I,  125 J and  125 K of  FIG. 13A  that are to be interconnected by an electromigration stop except that they are spaced further apart. Dashed line  260  indicates the opening in the patterned photoresist layer that defines the topological extents of the electromigration stop (see, for example,  FIG. 7A ) of  FIG. 15B . In  FIG. 15B , the four wires  125 H,  125 I,  125 J and  125 K (comprised of copper cores  120  and copper diffusion barrier liners  115 ) are interconnected by electromigration stop  250 . Electromigration stop  250  is thus formed at the cardinal intersection of the axes of wires  125 H,  125 I,  125 J and  125 K. Electromigration stop  250  differs from electromigration stop  235  of  FIG. 13  in that electromigration stop  250  includes a body  255  (comprised of copper core  150  and copper diffusion barrier liner  155 ) and corner projections  265 A,  265 B,  265 C and  265 D comprised of copper cores  150  and copper diffusion barrier liners  155 . The liners ( 115 ) of corner projections  265 A,  265 B,  265 C and  265 D are simultaneously formed with and contiguous with the liner ( 115 ) of electromigration stop  250 , but the copper cores ( 120 ) of corner projections  265 A,  265 B,  265 C and  265 D though simultaneously formed with the copper core ( 120 ) of electromigration stop  250  are not contiguous with the copper core ( 120 ) of electromigration stop  250 . Also, only the three wires  125 H,  125 I and  125 J may be formed as in  FIG. 14  in which case corner regions  265 A and  265 D would merge. 
       FIG. 16  is similar to  FIG. 15  except the copper cores ( 120 ) of corner projections  265 A,  265 B,  265 C and  265 D are contiguous with the copper core ( 120 ) of body  255 . 
     Thus, the embodiments of the present invention provide copper interconnect structures that are resistant to and can prevent electromigration fails dependent upon the geometry of the interconnect structures. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.