Abstract:
A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a polysilicon film and fabrication methods thereof, and in particular relates to directly fabricating a polysilicon film at a low temperature and a plasma chemical vapor deposition apparatus utilized. 
         [0003]    2. Description of the Related Art 
         [0004]    Currently, Solid Phase Crystallization or Excimer Laser Annealing (ELA) methods are utilized to form a polysilicon thin-film, such that the amorphous silicon on a thin film is crystallized into polysilicon by high temperature annealing. However, both processes have disadvantage. 
         [0005]    For Solid Phase Crystallization, a silicon wafer or Quartz (SiO3) must be utilized as a substrate due to requirement for a high crystallization temperature. Because the required materials are relatively expensive, they are not suitable for mass production. 
         [0006]    As for Excimer Laser Annealing, although crystallization temperature may be reduced, the cost of required apparatuses is relatively high. In addition, time required for the procedure is less to be desired. 
         [0007]    Additionally, in recent years, Plasma Enhanced Chemical Vapor Deposition (PE-CVD) and Hot Wire Chemical Vapor Deposition (HW-CVD) have been developed as direct deposition methods for forming polysilicon thin film. Nevertheless, during the preliminary stage of polysilicon thin film deposition, the nucleation density is relatively low, requiring several thousands Armstrong (&gt;1000 Å) to be deposited to form polysilicon thin film of desired crystallization. Specifically, disorder arrangement of silicon atoms takes place at the interface. 
         [0008]    In addition to the direct deposition methods, Metal-Induced Lateral Crystallization (MILC) has been developed to deposit a relatively thinner layer of polysilicon at a slower speed, to be used as a seed layer for subsequent deposition of amorphous silicon. The speed of gas flow utilized in depositing the polysilicon is slower than that normally used in depositing the amorphous silicon by several folds. After the polysilicon has been deposited, amorphous silicon is deposited on the polysilicon to an appropriate thickness and is annealed in a furnace at 600° C., so that the amorphous silicon is crystallized into polysilicon. Since the seed layer already exists, the amorphous silicon can be transformed into polysilicon in a relatively short period of time. However, since it takes a long time to form the seed layer at a slower speed, there is relatively little time savings for the anneal process. Furthermore, the method does not suit mass production due to process challenges involved given the overly high co-melting point of metal and silicon and problems of contamination of the thin film by the metal. In addition, outcome of an overly high temperature of the substrate due to seed layer application may lead to additional processing problems and challenges. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    An embodiment of a method for directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first sub-layer of polysilicon on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second sub-layer of polysilicon on the first sub-layer. The first and second sub-layers constitute the polysilicon film. Specifically, the first bias voltage differs from the second bias voltage. 
         [0010]    An embodiment of a low temperature polysilicon thin film transistor (TFT) electronic device is also disclosed. The electronic device comprises a substrate, a gate electrode on the substrate, and a polysilicon thin film which is formed by the described method and overlies the gate electrode. 
         [0011]    An embodiment of a plasma chemical vapor deposition apparatus is also disclosed. The vapor deposition apparatus is used to deposit a low temperature polysilicon thin film on a substrate, and comprises a vacuum chamber used to accommodate more than one type of injected gases. The vacuum chamber is provided with a support stand used to place the substrate, and the injected gas contains a silicon material. The vapor deposition apparatus also comprises an induction coil disposed outside the vacuum chamber. The induction coil is used to generate an induction-coupled electrical field in the vacuum chamber, so that the gas in the vacuum chamber is reacted and transformed into plasma, which is deposed on the substrate. The vapor deposition apparatus comprises an integrated bias system including a direct current (DC) bias voltage supply and an radiation frequency (RF) bias voltage supply, electrically connected to the support stand. The integrated bias system is used to alternatively supply a bias voltage to the substrate that is on the support stand. 
         [0012]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0014]      FIG. 1  is a schematic view showing a comparative example of a direct current (DC) bias system with high density plasma. 
           [0015]      FIG. 2   a  is a schematic view showing a motion mode of charged particles in a DC bias field. 
           [0016]      FIG. 2   b  is a schematic view showing a motion mode of charged particles in an RF bias field. 
           [0017]      FIG. 3  is a schematic view showing an embodiment of a DC bias system with high density plasma. 
           [0018]      FIG. 4  shows the polysilicon film formed by the system in  FIG. 3 . 
           [0019]      FIG. 5  shows a low temperature silicon thin film transistor  5000  including the polysilicon film shown in  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0021]    Hereinafter, the term “integrated bias system” refers to an integrated bias system combining a direct current (DC) bias voltage supply and a radio frequency (RF) voltage supply. 
       EXEMPLARY EXAMPLE 
       [0022]    Referring to  FIG. 1 , in this example, high density plasma chemical vapor deposition is utilized to directly fabricate a polysilicon film at a low temperature. 
         [0023]    Firstly, a substrate  102  is disposed on the support stand  100 , and an induction layer  104  is deposited on the substrate  102 . A gas including silicon (not shown) to generate plasma  110  is introduced, in the meantime,  1   a  bias system  112  is utilized to apply a DC bias voltage to the substrate  102 , thereby a polysilicon layer is formed through induction of induction layer  104  coupled with plasma chemical vapor deposition. Ions  108  from plasma  110  are influenced by the DC bias voltage, thus bombarding the substrate  102  in the direction  106  and depositing on the substrate  102 . In this example, the formation method for the induction layer can be chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and materials thereof can be aluminum nitride. Formation methods of the polysilicon layer can be inductively-coupled plasma chemical vapor deposition or very high frequency chemical vapor deposition. 
         [0024]    As described, this example features the direct deposition of polysilicon (thin) film at a low temperature by inductively-coupled plasma chemical vapor deposition coupled with a DC bias voltage. During the deposition process, however, issues such as a loose structure and bad crystalline usually occur because of ion or atom bombardment of the underlying layer. 
       First Embodiment 
       [0025]    In this embodiment, the issues described in the exemplary example are addressed through application of RF bias voltage, specifically, via appropriate switching of DC and RF bias voltages during the early process stage (or so-called nuclear formation stage). The application allows avoidance of over bombardment effects during the nuclear formation stage, resulting in obtainment of stable high density plasma. Next, in the propagation stage, DC bias voltage is applied, effectively enhancing the deposition rate and stability of crystalline. It is important to note, that compared to the exemplary example in which only DC bias voltage is employed in the entire process, this embodiment utilizes an integrated bias system to apply different bias voltages at different processing stages. In doing so, the electrical field reversal property of RF bias voltage not only results in extension of mean free path of charged particles in the plasma region, but also reduces bombarding effects of plasma to the substrate. Accordingly, plasma density is increased, and bombarding effects to the substrate can be avoided, resulting in a denser polysilicon film and enhanced crystalline. Thereafter, in the propagation stage, DC bias voltage is applied, effectively enhancing the deposition rate and stability of crystalline. In another embodiment, an additional deposition step is further performed after the previously described sequential deposition steps. In the additional deposition step, RF bias voltage is applied to the substrate again, and a plasma chemical vapor deposition is utilized to sequentially deposit polysilicon materials on the substrate up to a preferred thickness, resulting in a polysilicon film. A silicon nitride layer is then formed on the polysilicon film. 
         [0026]    Referring to  FIGS. 2-4 ,  FIG. 2   a  is a schematic view showing a motion mode of charged particles  250  in a DC bias field;  FIG. 2   b  is a schematic view showing a motion mode of charged particles  250  in an RF bias field;  FIG. 3  is a schematic view showing an embodiment of a DC bias system accompanying with high density plasma; and  FIG. 4  shows the polysilicon film formed by the system in  FIG. 3 . 
         [0027]    As shown in  FIG. 2   a,  the electric field generated by DC bias voltage forces charged particles  250  to strike the substrate at high speeds with conversion of kinetic energy to potential energy, thus facilitating reaction. As shown in  FIG. 2   b,  by using RF bias voltage, the electrical field reversal property of RF bias voltage alters the motion mode of charged particles  250 , thus increasing collision probability and duration of charged particles  250  in the plasma system. Resulting in increased plasma density so that reaction takes place faster. 
         [0028]    As shown in  FIG. 3 , this embodiment discloses an inductively-coupled plasma chemical vapor deposition apparatus  2000  for deposition of a low temperature polysilicon thin film  202  on a substrate  200 . The inductively-coupled plasma chemical vapor deposition apparatus  2000  mainly includes a vacuum chamber  204 , an induction coil  212 , an integrated bias system  208 , an RF power  214 , and a cooling gas  206 . 
         [0029]    The vacuum chamber  204  allows introduction of one or more gases (such as silane and argon), and possesses a support stand (not shown) for holding the substrate. The cooling gas  206 , such as nitrogen, is utilized to control temperature of the substrate  200 . 
         [0030]    The induction coil  212  is disposed outside the vacuum chamber  204 , and is connected to an RF power  214 . The induction coil  212  is used to generate inductively-coupled electric field in the vacuum chamber  204 , so that the gas in the vacuum chamber  204  forms plasma  210  and bombards the substrate  200 , to finally deposit on the substrate  200 . 
         [0031]    Integrated bias system  208  simultaneously includes a DC bias voltage supply and an RF voltage supply, electrically connected to the support stand, for applying a bias voltage on the substrate  200  in turn. 
         [0032]    Referring to  FIGS. 3 and 4 , in this embodiment, the inductively-coupled plasma chemical vapor deposition apparatus  2000  is employed to perform sequential deposition on the substrate  200  at a low temperature. Firstly, the induction coil  212  and RF power  214  are used to generate an inductively-coupled electric field and a high density plasma source (typically, argon), allowing the processing gas such as silane (not shown) form ion beams. Next, an RF bias voltage is applied to the substrate  200  using the integrated bias system  208 , allowing the ion beams to deposit a seed layer  202   a  of a preferred thickness on the substrate  200 . Subsequently, a DC bias voltage is applied to the substrate  200  via switching the integrated bias system  208 , thus the deposition rate is increased to form a portion  202   b.  Accordingly, a polysilicon thin film  202  serving as an active layer is obtained. Although the resultant polysilicon thin film  202  includes the seed layer  202   a  (also called RF bias seed layer) formed during the nuclear formation stage and the portion  202   b  (also called DC bias crystalline layer) formed during the propagation stage, there is no obvious interface between the seed layer  202   a  and portion  202   b  because the sequential deposition processes is performed in the same reaction chamber. In other embodiments, after portion  202   b  achieves a certain thickness; the integrated bias system  208  can be switched again for various purposes. Alternatively, other deposition methods such as very high frequency plasma-enhanced chemical vapor deposition or electron cyclotron resonance plasma-enhanced chemical vapor deposition may be used. 
         [0033]    Compared to the method that only uses DC bias voltage during the entire process, the method used in this embodiment results in a denser polysilicon film and more enhanced crystalline. The method used in this embodiment is also appropriate in formation of TFT devices. 
       Second Embodiment 
       [0034]    Referring to  FIG. 5 , the TFT process of this embodiment features direct formation of a micro-silicon active layer  506  and a micro-silicon doped layer  508  on a substrate with a gate electrode  502  and a gate dielectric layer  504  thereon by method of the previous described first embodiment. Subsequent conventional processes are then performed. Finally, a low temperature polysilicon TFT is obtained. 
         [0035]    In the integrated bias system of this embodiment, energy generated from bombarding of ions is transmitted to atoms on the surface, resulting in diffusion of the atoms on the surface with sufficient energy to active sites. The diffused atoms sequentially form the insulating layer  504 , micro-silicon active layer  506  and micro-silicon doped layer  508 . When the micro-silicon doped layer  508  is formed on the active layer, a lightly doped junction (not shown) is formed on the interface, without additional ion implantation or thermal processes. In doing so, performance of devices is enhanced, and manufacturing costs are reduced. 
         [0036]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.