Abstract:
A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a divisional application of application Ser. No. 12/776,485, filed May 10, 2010 now U.S. Pat. No. 8,361,907. 
    
    
     FIELD OF INVENTION 
     The present invention relates to semiconductor nanowire field effect transistors and to methods that allow the fabrication of nanowire field effect transistors in a dense array. 
     DESCRIPTION OF RELATED ART 
     The fabrication of a nanowire field effect transistor (FET) with a gate conductor surrounding the nanowire channel (also known as a gate-all-around nanowire FET) includes suspension of the nanowires. Suspension of the nanowires allows for the gate conductor to cover all surfaces of the nanowires. 
     The fabrication of a gate-all-around nanowire FET typically includes the following steps: (1) Definition of the nanowires between source and drain regions by patterning a silicon-on-insulator (SOI) layer. (2) Suspension of the nanowires by isotropic etching that undercuts the insulator on which the nanowires are resting. This etching step also undercuts the insulator at the edge of the source and drain region. The overhang/undercut that forms may not be a desirable outcome. (3) A blanket and conformal deposition of the gate conductor. The gate conductor warps around the suspended nanowires but also fills the undercut at the edge of the source and drain regions. (4) Definition of the gate line which includes the etching of the gate line and removal of gate conductor material from all regions outside the gate line, including gate material deposited in the cavities at the edge of the source and drain regions. 
     BRIEF SUMMARY 
     In one aspect of the present invention, a nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. 
     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIGS. 1A-8B  illustrate an exemplary method for forming field effect transistor (FET) devices. 
     
    
    
     DETAILED DESCRIPTION 
     The formation of the undercut (in step 3; described in the Description of Related Art section above) imposes a limitation on the density of circuits built with gate-all-around nanowire FET. The undercut size should be at least half of the width of the nanowires, or the nanowires may not be fully suspended by the etching. The undercut under the source (or drain) region should be smaller than half of the source (or drain) region width. If the source width is made narrower than two times the undercut size, the source (and drain) may not provide the anchoring for the suspended nanowires. The minimum width of the source and the drain dictates the area the device occupies. In addition to the circuit density limitation the presence of the undercut may lead to fabrication issues. The definition of the gate line (step 4) includes the removal of all the gate conductor material that was deposited in the cavity formed by the undercut. This is typically performed by an isotropic etch, which also etches the gate line. As a result, control of the gate line dimensions may be difficult to obtain. 
       FIG. 1A  illustrates a cross-sectional view along the line  1 A (of  FIG. 1B ) and  FIG. 1B  illustrates a top down view of an exemplary method for forming a field effect transistor (FET) device.  FIG. 1A  includes a substrate  100  (for example a silicon substrate); a buried oxide (BOX) layer  102  disposed on the substrate  100 ; a silicon on insulator (SOI) layer  104  disposed on the BOX layer  102 ; a crystalline layer  106  such as, for example, a crystalline silicon germanium layer (SiGe) disposed on the SOI layer  104 ; and a second silicon layer  108  disposed on the crystalline layer  106 . 
       FIGS. 2A and 2B  illustrate the resultant structure including anchor portions  202  and nanowire portions  204  that are patterned in the films stack formed by layers  104 ,  106 , and  108 . The anchor portions  202  and nanowire portions  204  may be patterned by the use of lithography followed by an etching process such as, for example, reactive ion etching (RIE). The etching process removes portions of the crystalline layer  108 ,  106 , and the SOI layer  104  to expose portions of the BOX layer  102 . The etched structure of  FIG. 2B  forms a ladder-like structure in which the rungs  204  have sidewalls parallel to the {100} crystal planes, and the anchors  202 , which are connected by the rungs, have sidewalls parallel to the {110} crystal planes. In the example shown in  FIG. 2B  the rungs and the anchors forms a right angle (90°), the top surface of layer  108  is therefore parallel to the {110} crystal planes. The specification for crystal planes directions follows the Miller indices convention which is described in, e.g., Ashcroft and Mermin, Solid State Physics, chapter 5 (1976), the contents of which are incorporated herein by reference. Following this convention a family of crystal planes, i.e. planes that are equivalent by the virtue of the symmetry of the crystal is typically referenced by a pair of { } parentheses. For example, the planes (100), (010) and (001) are all equivalent in a cubic crystal. One refers to them collectively as {100} planes. In yet another example the {110} planes refer collectively to the (110), (101), (011), planes. 
       FIGS. 3A and 3B  illustrate the resultant structure following an anisotropic etching process that selectively removes portions of the crystalline layer  106  resulting in pedestal portions  302  that are defined in the crystalline layer  106  that support the anchor portions  202 . The anisotropic etching process removes the portions of the crystalline layer  106  that are orientated along the lattice plane {100} at a faster rate than the portions of the crystalline layer  106  that are orientated along the lattice plane {110}, resulting in the removal of the crystalline layer  106  that is below the nanowire portions  204 , and the suspension of the nanowire portions  204  by the anchor portions  202 .  FIG. 3B  illustrates the top-down profile of the pedestal portions  302  (illustrated by the dotted lines  301 ) that support the anchor portions  202 . The width (w) of the pedestal portions  302  is less than the width (w′) of the anchor portions  202 , resulting in longitudinal overhang regions  304 . The length (L) of the pedestal portions  302  is less than the length (L′) of the anchor portions  202  resulting in transverse overhang regions  306 . The anisotropic etching process results in the longitudinal overhang regions  304  having a smaller overhang length (W′−W)/2 than the transverse overhang (L′−L)/2 regions  306  due to the {100} planes etching faster than {110} planes in crystalline layer  106 . The anisotropic etch exhibits chemical selectivity. The etch chemistry mainly removes the crystalline material  106  but does not substantively etch the crystalline material  108 . For example, when layer  108  is silicon and layer  106  is SiGe, hot (gaseous) HCL can be used to selectively etch SiGe with little removal of Si. Additionally, HCL provides an anisotropic etching process as it etches faster the SiGe in the (100) orientation than in the (110) orientation. The etching is typically done when the wafer is kept a temperature of about 800° C. 
       FIGS. 4A and 4B  illustrate the resultant structure following the formation of a thermal oxide layer  402  and  402 A on the exposed anchor portions  202 , nanowire portions  204 , SOI layer  104 , and pedestal portions  302 . The oxidation process can be dry (with O 2 ) or wet (with H 2 O vapor), with typical oxidation temperature from 750° C. to about 1000° C. The thermal oxidation process completely oxidizes the SOI layer  104  due to the thin thickness of the SOI layer  104  relative to the thicknesses of the anchor portions  202 , nanowire portions  204 , and pedestal portions  302 . 
       FIGS. 5A and 5B  illustrate the resultant structure following the formation of polysilicon gates  502  and hardmask layers  504  such as, for example, silicon nitride (Si 3 N 4 ) on the polysilicon gates  502 . The polysilicon  502  and the hardmask layer  504  may be formed by depositing polysilicon material over channel regions of the nanowire portions  204 , depositing the hardmask material over the polysilicon material, and etching by RIE to form the polysilicon gates  502  and the hardmask layers  504 . The etching of the polysilicon gates  502  may be performed by directional etching that results in straight sidewalls of the gate  502 . Following the directional etching, polysilicon  502  remains under the nanowire portions  204  and outside the region encapsulated by the gate  502 . Isotropic etching may be performed to remove polysilicon  502  from under the nanowire portions  204 . 
       FIGS. 6A and 6B  illustrate spacer portions  602  formed along opposing sides of the polysilicon gates  502 . The spacers  602  are formed by depositing a blanket dielectric film such as silicon nitride and etching the dielectric film from horizontal surfaces by RIE.  FIGS. 6A and 6B  include spacer portions  602  that are formed under the nanowire portions  204 , and below the overhang regions  304  and  306 . 
       FIGS. 7A and 7B  illustrate the resultant structures following a chemical etching process (such as etching with diluted HF) to remove the exposed portions of the thermal oxide layer  402  and a selective epitaxially grown silicon (epi-silicon)  702  that is grown on the exposed silicon of the anchor portions  202  and the nanowire portions  204 . The epitaxy may include, for example, the deposition of in-situ doped silicon (Si) or silicon germanium (SiGe) that may be either n-type or p-type doped. The in-situ doped epitaxy process forms the source region and the drain region of the nanowire FET. As an example, a chemical vapor deposition (CVD) reactor may be used to perform the epitaxial growth. Precursors for silicon epitaxy include SiCl 4 , SiH 4  combined with HCL. The use of chlorine allows selective deposition of silicon only on exposed silicon surfaces. A precursor for SiGe may include a mixture of SiCl 4  and GeH 4 . For pure Ge epitaxy only GeH 4  is used, and deposition selectivity is typically obtained without HCL. Precursors for dopants may include PH 3  or AsH 3  for n-type doping and B 2 H 6  for p-type doping. Deposition temperatures may range from 550° C. to 1000° C. for pure silicon deposition, and as low as 300° C. for pure Ge deposition. 
       FIGS. 8A and 8B  illustrate a resultant structure following silicidation where a silicide  802  is formed on the epi-silicon  702  of the anchor and the epi-thickened nanowire portions  202  and  204 . Examples of silicide forming metals include Ni, Pt, Co, and alloys such as NiPt. When Ni is used the NiSi phase is typically formed due to its low resistivity. For example, formation temperatures include 400-600° C. Once the silicidation process is performed, capping layers and vias for connectivity (not shown) may be formed in the source (S), drain (D), and gate (G) regions of the device. 
     In an alternate exemplary method, high-K/metal gates may be formed on the nanowire portions  204 . Referring to  FIGS. 4A and 4B , the thermal oxide  402  around the nanowire portions  204  and along the sides of the pedestal portions  302  may be removed by an etching process. A chemical oxide material may be grown on the exposed silicon material, and high-K and gate metal layers are deposited conformally prior to the deposition and etching to form the polysilicon portions  502  and hardmask layers  504  (of  FIGS. 5A and 5B ). Once the polysilicon  502  and hardmask layers  504  are formed, etching may be performed to remove exposed metal gate material that is not covered by the polysilicon  502 . Once the exposed metal gate material is removed, the method may continue as described in  FIGS. 6A-8B  above. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one ore more other features, integers, steps, operations, element components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
     The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
     While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.