Abstract:
For particularly flexible and space-saving information storage, in the case of a floating gate memory cell and a corresponding semiconductor memory device, the invention includes providing a floating gate configuration with a plurality of floating gates. Each of the floating gates is configured for substantially independent information storage. As a result, a plurality of information units can be stored independently of one another in the memory cell.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    Field of the Invention  
           [0002]    The invention relates to a floating gate memory cell for nonvolatile information storage, a semiconductor memory device having a plurality of memory cells for nonvolatile information storage, and a method for fabricating a floating gate memory cell for nonvolatile information storage.  
           [0003]    In the further development of semiconductor memory devices based upon nonvolatile memory mechanisms, the principle of the so-called nonvolatile floating gate memory cell has also been developed. Such a floating gate memory cell for nonvolatile information storage has a floating gate configuration, a source/drain configuration, and a control gate configuration. The floating gate configuration serves for the actual information storage, while the source/drain configuration is configured for access to the floating gate configuration and, thus, for access to the respective information. The control gate configuration is configured for controlling such access to the floating gate configuration and to the information.  
           [0004]    What is disadvantageous in the case of existing semiconductor memory devices, memory cells contained therein, and corresponding fabrication methods for semiconductor memory devices or memory cells is that their fundamental concept, from a structural and production engineering standpoint, is based on the provision of a single binary information unit in each individual memory cell. Each memory cell and, thus, each memory location are, thus, occupied only singularly with information and configured accordingly.  
         SUMMARY OF THE INVENTION  
         [0005]    It is accordingly an object of the invention to provide a floating gate memory cell, method for fabricating it and semiconductor memory device that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that, in a particularly simple manner, obtains a particularly high information density and, in a particularly reliable manner, modifies and retrieves such information.  
           [0006]    With the foregoing and other objects in view, there is provided, in accordance with the invention, a floating gate memory cell for nonvolatile storage of information including at least one of information units and binary bits, including a floating gate configuration for storing the information, the floating gate configuration having floating gates each independently storing the information and, as a result, storing a corresponding plurality of one of the information units and the binary bits independently of one another in the memory cell, a source/drain configuration accessing the floating gate configuration, a control gate configuration controlling access to the floating gate configuration, the control gate configuration having control gates each associated with a respective one of the floating gates, access to the respective one of the floating gates being controlled by each respective one of the control gates, and the source/drain configuration having two source/drain regions jointly provided for the floating gates and the control gates to permit access of all of the floating gates through the two common source/drain regions.  
           [0007]    The invention&#39;s floating gate memory cell for nonvolatile information storage is characterized in that the floating gate configuration has a plurality of floating gates, in that each of the floating gates is configured for substantially independent information storage, and in that, as a result a corresponding plurality of information units, in particular, binary bits, can be stored independently in the memory cell.  
           [0008]    Thus, in contrast to the prior art, the invention departs from the one-bit concept and, consequently, the floating gate memory cell according to the invention is configured for storing a plurality of information units, in particular, binary bits or the like. Such a characteristic is realized by virtue of the fact that, in contrast to the floating gate memory cell according to the prior art, the floating gate configuration is configured with a plurality of floating gates. In such a case, each of the floating gates is configured for separate and independent information storage independently of the other floating gates. Consequently, by way of example, a respective bit can be written and retrieved, in accordance with an impressed potential state, in each of the floating gates.  
           [0009]    Each floating gate can also be configured for taking up more than two charge and/or potential states, thereby, further increasing the information density per floating gate memory cell.  
           [0010]    The structure of the floating gate memory cell according to the invention is configured particularly flexibly if, in accordance with another feature of the invention, the control gate configuration has a plurality of control gates, a respective control gate is assigned to a respective floating gate and the access to the assigned floating gate and the information state contained therein is controllable by each control gate. The initially organizational assignment of a respective control gate of the control gate configuration with a respective floating gate of the floating gate configuration results in a particularly flexible control of the access to the information to be stored in the floating gate. The initially organizational and sequence-technical assignment between floating gate and control gate will, advantageously, also be represented in a structural or spatial assignment, in particular, in a particular spatial proximity of the assigned floating gates and control gates with respect to one another.  
           [0011]    A further simplification of the floating gate memory cell according to the invention results if the source/drain configuration has two source/drain regions, the source/drain regions are provided jointly for the plurality of floating gates and/or for the plurality of control gates, and all the floating gates can be accessed by the two common source/drain regions.  
           [0012]    With regard to a particularly simple fabrication procedure and also with regard to a corresponding functional reliability, the floating gates are configured substantially identically with regard to their geometrical and/or material properties.  
           [0013]    For the reliability of the floating gate memory cell according to the invention, on the other hand, the floating gates are disposed and configured in a manner substantially electrically insulated from one another, from the control gates and from the source/drain regions, and in that, in particular, each floating gate in the floating gate memory cell is configured and disposed in a substantially capacitively coupled manner.  
           [0014]    Furthermore, it is advantageous that the floating gates are configured substantially identically with regard to their geometrical and/or material properties.  
           [0015]    It is further preferred that the control gates are disposed and configured in a manner substantially electrically insulated from one another, from the floating gates, and from the source/drain regions.  
           [0016]    In accordance with a further feature of the invention, the floating gates and/or the control gates are composed of a polysilicon material, polycide, metal, and/or the like.  
           [0017]    In accordance with an added feature of the invention, the floating gates and the control gates are composed substantially of the same material.  
           [0018]    To realize the assignment between the floating gates and the control gates, in accordance with an additional feature of the invention, the mutually assigned floating gates and control gates are in each case configured in direct spatial proximity to one another, and that, in particular, respective intermediate insulation regions are provided in such a case, in particular, in each case an intermediate dielectric between the respectively assigned floating gates and the control gate.  
           [0019]    The intermediate dielectric is also referred to as interpoly dielectric and may be, e.g., an NO or ONO structure, i.e., a structure with a configuration including nitride/oxide or oxide/nitride/oxide, respectively.  
           [0020]    It is, furthermore, preferred that each floating gate has a first end region and a second end region. The respective first end region is configured and disposed in direct spatial proximity to the first source/drain region and the respective second end region is configured and disposed in direct spatial proximity to the second source/drain region. As a result, in particular, a spatial and/or areal overlap is formed between the floating gates, in particular, between the respective end regions thereof, and the source/drain regions.  
           [0021]    In accordance with yet another feature of the invention, there is provided an insulation region, in particular, in the form of a silicon dioxide material, is provided between the respective floating gate, in particular, the end regions thereof and the source/drain regions.  
           [0022]    In accordance with yet a further feature of the invention, a main region of the floating gate cell is formed, to be precise as an elevated region, in particular, as a lamella, a web, a burr, or the like, of a semiconductor material region.  
           [0023]    In such a case, the main region, in particular, the lamella, advantageously has side regions. Furthermore, in such a case the, in particular, two, floating gates are provided in the region of the side regions, in particular, in a manner lying opposite one another with the main region in between, in particular, in direct spatial proximity thereto with provision in each case of an insulation region toward the main region.  
           [0024]    The provision of such a lamellar region with side regions results practically automatically in an electrical insulation and spatial separation between the floating gates to be formed, on one hand, and between the control gates to be formed, on the other hand.  
           [0025]    In accordance with yet an added feature of the invention, the source/drain regions are configured as—in particular n + -doped—regions of the main region, isolated, in particular, by a channel region as part of the main region. Although n-channel transistors are preferred, p-channel transistors are, nevertheless, possible and provided. In such a case, source/drain regions are, then, configured to be p + -doped.  
           [0026]    Such a procedure with the configuration as lamella, thus, additionally automatically enables the formation of source/drain regions that are spatially separate from one another and substantially electrically insulated from one another.  
           [0027]    Furthermore, by virtue of its linear extent and by virtue of the possibility of disposing a plurality of such lamellae parallel to one another, the lamellar structure enables a particularly simple procedure when configuring a semiconductor memory device with a plurality or multiplicity of floating gate memory cells according to the invention.  
           [0028]    Thus, in the case of the invention&#39;s semiconductor memory device having a plurality of memory cells for nonvolatile information storage, the memory cells are configured as floating gate memory cells according to the invention.  
           [0029]    In accordance with yet an additional feature of the invention, adjacent memory cells use at least some of the control gates as common control gates.  
           [0030]    In accordance with again another feature of the invention, the plurality of memory cells is configured and disposed in a matrix-like manner and on a plurality of substantially identical main regions, in particular, in the form of lamellae, webs, burrs, or the like.  
           [0031]    The design and structure of the semiconductor memory device according to the invention is configured particularly advantageously if the main regions are configured and disposed in a manner extending linearly and substantially equidistantly with respect to one another.  
           [0032]    In such a case, the main regions, in particular, the lamellae, are provided substantially as columns and/or as rows of the matrix-like configuration of memory cells.  
           [0033]    The invention&#39;s method for fabricating a floating gate memory cell for nonvolatile information storage is presented below. A fabrication method of the generic type is used as a basis in this case. In the case of the method of the generic type, a floating gate configuration, a source/drain configuration, and a control gate configuration are provided. The floating gate configuration is configured for the actual information storage. The source/drain configuration is configured for access to the floating gate configuration. The control gate configuration is configured for controlling the access to the floating gate configuration and to the information contained therein.  
           [0034]    With the objects of the invention in view, there is also provided a method for fabricating a floating gate memory cell for nonvolatile information storage, including the steps of providing a floating gate configuration for storing information, the floating gate configuration having floating gates each storing the information substantially independently of one another in the memory cell, accessing the floating gate configuration with a source/drain configuration, controlling the access to the floating gate configuration with a control gate configuration having a plurality of control gates, a respective one of the control gates being associated with a respective one of the floating gates, controlling access to the associated one of the floating gates with each respective one of the control gates, providing the source/drain configuration with two source/drain regions jointly associated with the floating gates and the control gates, and making accessible all of the floating gates through the two common source/drain regions.  
           [0035]    The invention&#39;s method for fabricating a floating gate memory cell is characterized by configuring the floating gate configuration with a plurality of floating gates, each of the floating gates being configured for substantially independent information storage, and, as a result, a corresponding plurality of information units, in particular, binary bits or the like, can be stored independently of one another in the memory cell.  
           [0036]    In accordance with again a further mode of the invention, the control gate configuration is provided having a plurality of control gates, a respective control gate is assigned to a respective floating gate, and the access to the assigned floating gate is configured to be controllable by each control gate.  
           [0037]    On the other hand, the source/drain configuration is provided having two source/drain regions, the source/drain regions are provided jointly for the plurality of floating gates and/or for the plurality of control gates, and, as a result, all the floating gates are accessible through the two common source/drain regions.  
           [0038]    In accordance with again an added mode of the invention, in each case the floating gates and/or in each case the control gates are configured substantially identically with regard to their geometrical and/or material properties.  
           [0039]    It is, furthermore, preferred for the floating gates and/or the control gates to be disposed and configured in a manner substantially electrically insulated from one another from the control gates and/or from the floating gates and from the source/drain regions.  
           [0040]    In the case of the floating gates, it is, furthermore, preferred that they are configured and disposed in a substantially capacitively coupled manner in the floating gate memory cell by virtue of these measures.  
           [0041]    The floating gates and/or the control gates are preferably formed from a polysilicon material, polycide, metal, and/or the like. In particular, they are formed from the same material.  
           [0042]    It is advantageous to configure the control gate in each case with low impedance. By contrast, the floating gates can also have high impedance.  
           [0043]    To realize the assignment between the respective floating gates and the respective control gates, the floating gates and control gates that are respectively assigned to one another are provided in direct spatial proximity to one another, and, in such a case, in particular, an intermediate insulation region, in particular, an intermediate dielectric is provided in each case.  
           [0044]    Preferably, each floating gate is configured with a first end region and a second end region. The respective first end region is configured and disposed in direct spatial proximity to the first source/drain region and the respective second end region is configured and disposed in direct spatial proximity to the second source/drain region. As a result, in particular, a spatial or areal overlap is formed between the floating gates, in particular, between the respective end regions thereof, and the source/drain regions. Preferably, an insulation region, in particular, in the form of a silicon dioxide material, is, furthermore, formed between the respective floating gates, in particular, the end regions thereof, and the respective source/drain region.  
           [0045]    It is particularly preferred that in each case an elevated region, in particular, a lamella, a web, a burr, or the like of a semiconductor material region is formed as main region of the floating gate cell. In such a case, the main region, in particular, the lamella or the like, is formed with side regions. Furthermore, floating gates—in particular two—are provided in the region of the side regions, in particular, in a manner lying opposite one another with the main region in between, in particular, in direct spatial proximity thereto with provision in each case of an insulation region toward the main region.  
           [0046]    It is particularly advantageous that the source/drain regions are configured as in particular, n + -doped or p + -doped—regions of the main region, isolated, in particular, by a channel region as part of the main region.  
           [0047]    The previous characterizing features of the fabrication method according to the invention represent, in part, the structural features of the floating gate memory cell to be formed according to the invention. However, different configurations are, furthermore, conceivable during the fabrication.  
           [0048]    In accordance with again an additional mode of the invention, first, a semiconductor substrate region, in particular, in the form of p-doped silicon, is provided. Local doping regions, in particular, in n + -doped form, are, then, formed for the source/drain regions to be formed, in particular, by implantation. Afterward, the main region for the memory cell is, then, formed by etching back the surroundings in the semiconductor material region, in particular, using a masking process or the like.  
           [0049]    It is also possible to use n-doped silicon, in which case p + -doped source/drain regions are to be provided.  
           [0050]    The last two steps mentioned can also be carried out with their order reversed so that, first, the main regions, that is to say, in particular, the lamellar structure, is formed by etching back the surroundings in the semiconductor material region, in particular, using a masking process or the like, and, then, doping regions in local form are formed subsequently, in particular, by implantation.  
           [0051]    Advantageously, the local doping regions are formed in a first strip form, and the etching back is effected in a second strip form, transversely with respect to the first strip form.  
           [0052]    Particularly advantageous structures result if, in accordance with still another mode of the invention, the main region is configured to be linear and/or approximately parallelepipedal. Such a configuration can be effected by skillful process control during etching back.  
           [0053]    Then, an insulation layer is formed or deposited substantially conformally, in particular, made of a silicon dioxide material and/or, in particular, for the insulation region between the main region and the floating gates to be formed.  
           [0054]    Furthermore, the insulation layer is formed by being grown.  
           [0055]    Afterward, a material region is, then, formed, in particular, deposited, for the floating gates to be formed. In such a case, in particular, polysilicon material or the like is used.  
           [0056]    Afterward, the floating gates are, then, patterned, in particular, by etching columns into the material region for the floating gates. In such a case, the columns are formed such that they run perpendicularly to the direction of extent of the main region, that is to say, for example, of the lamella. Such a formation is followed by removal or etching back of the material region for the floating gates to a point below the level of a surface region of the main region, for example, of the lamella so that the material region or the material for the floating gates remains only in the region of the side regions of the main region.  
           [0057]    Afterward, a material region is formed or deposited substantially over the whole area and/or conformally, in particular, for the intermediate insulation region to be formed between assigned floating gates and control gates.  
           [0058]    Afterward, a material region is formed or deposited substantially over the whole area and/or conformally, in particular, for the control gates to be formed.  
           [0059]    Afterward, the control gates are patterned, in particular, by etching columns that run substantially perpendicularly to the extent of the main region, and by subsequent removal or etching back of the material region for the control gates to a point below the level of the surface region of the material region for the intermediate insulation region so that the material region for the control gates remains only in the region of the side regions of the main region, in particular, the material region for the intermediate insulation region not being removed.  
           [0060]    Preferably, the structure so obtained is embedded in an insulation region and subsequently formed with a contact connection to the source/drain regions and/or the control gates.  
           [0061]    The above-described and further aspects of the present invention are also explained based upon the remarks in the following text:  
           [0062]    In flash memory cells, it is possible to store a plurality of bits per cell by storing different charge states or by storing a respective bit at spatially separate locations. However, the last-mentioned possibility has, hitherto, necessitated the use of a so-called charge-trapping device. This means, for example, that the charge is stored in a nitride layer.  
           [0063]    The present invention presents a different approach, in which a floating gate cell can be realized for storing two or more bits in one cell.  
           [0064]    The storage of two bits in one flash cell has been realized, heretofore, either by the use of an Si 3 N 4  layer (NROM concept). Floating gate cells have, heretofore, used exclusively the storage of a plurality of charge states in a floating gate for storing a plurality of bits in one cell.  
           [0065]    By fabricating Si lamellae, it is possible to realize a floating gate cell that has two floating gates but is supplied through the same source and drain regions. As a result, one or even a plurality of bits can be stored in each of the two floating gates.  
           [0066]    A core idea is that the channel of the transistor is shifted from the Si surface to the surface of an Si lamella. Such shifting makes it possible to provide a respective floating gate at two locations of the lamella and, thus, to store two or more bits in the cell.  
           [0067]    The function of the memory cell is explained in the following text.  
           [0068]    If the component, that is to say, the floating gate memory cell, is processed in the manner described below, then an inversion channel can be produced at the left-hand and right-hand sides of the component both with the first control gate and with the second control gate. Each of these channels can be utilized as a separate memory cell area because the gate voltage can be set separately for each side of the component during programming and erasure.  
           [0069]    During programming, the methods are possible by hot electrons or by Fowler-Nordheim tunneling. During erasure, it is possible to have recourse substantially to Fowler-Nordheim tunneling from the floating gate either to source, drain, or channel (or a combination). The programming by hot electrons can be carried out either jointly for both bits or separately for each bit.  
           [0070]    It is an important innovation in the case of such a component that, although two gate regions are available for storage and driving, they are supplied only by in each case a common source/drain region.  
           [0071]    The fabrication of a memory cell according to the invention is described in the following text.  
           [0072]    The incorporation of a memory cell into an array is possible in a plurality of architectures (common ground NOR, virtual Ground NOR etc.). The latter differ in each case by the extent to which one of the source/drain regions is additionally utilized by further cells and, therefore, if appropriate, need not be separately contact-connected. The incorporation into different array architectures is effected analogously to conventional flash cells. Equally, the contact connection of the control gates is not described below. Such a contact connection is effected, in principle, at the array edge, and both control gates can be contact-connected on one side, or the control gates can be contact-connected on respectively opposite sides of the array.  
           [0073]    Other features that are considered as characteristic for the invention are set forth in the appended claims.  
           [0074]    Although the invention is illustrated and described herein as embodied in a floating gate memory cell, method for fabricating it and semiconductor memory device, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.  
           [0075]    The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0076]    [0076]FIG. 1A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 1C;  
         [0077]    [0077]FIG. 1B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 1C;  
         [0078]    [0078]FIG. 1C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 1A and 1B;  
         [0079]    [0079]FIG. 2A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 2C;  
         [0080]    [0080]FIG. 2B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 2C;  
         [0081]    [0081]FIG. 2C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 2A and 2B;  
         [0082]    [0082]FIG. 3A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 3C;  
         [0083]    [0083]FIG. 3B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 3C;  
         [0084]    [0084]FIG. 3C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 3A and 3B;  
         [0085]    [0085]FIG. 4A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 4C;  
         [0086]    [0086]FIG. 4B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 4C;  
         [0087]    [0087]FIG. 4C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 4A and 4B;  
         [0088]    [0088]FIG. 5A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 5C;  
         [0089]    [0089]FIG. 5B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 5C;  
         [0090]    [0090]FIG. 5C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 5A and 5B;  
         [0091]    [0091]FIG. 6A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 6C;  
         [0092]    [0092]FIG. 6B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 6C;  
         [0093]    [0093]FIG. 6C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 6A and 6B;  
         [0094]    [0094]FIG. 7A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 7C;  
         [0095]    [0095]FIG. 7B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 7C;  
         [0096]    [0096]FIG. 7C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 7A and 7B;  
         [0097]    [0097]FIG. 8A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 8C;  
         [0098]    [0098]FIG. 8B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 8C;  
         [0099]    [0099]FIG. 8C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 8A and 8B;  
         [0100]    [0100]FIG. 9A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 9C;  
         [0101]    [0101]FIG. 9B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 9C;  
         [0102]    [0102]FIG. 9C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 9A and 9B;  
         [0103]    [0103]FIG. 10A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 10C;  
         [0104]    [0104]FIG. 10B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 10C;  
         [0105]    [0105]FIG. 10C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 10A and 10B;  
         [0106]    [0106]FIG. 11A is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane A-A of FIG. 11C;  
         [0107]    [0107]FIG. 11B is a cross-sectional side view of an intermediate state reached in the fabrication method according to the invention along the sectional plane B-B of FIG. 11C;  
         [0108]    [0108]FIG. 11C is a cross-sectional plan view of an intermediate state reached in the fabrication method according to the invention along the sectional plane C-C of FIGS. 11A and 11B;  
         [0109]    [0109]FIG. 12A is a cross-sectional side view of an alternative embodiment of the contact connection process according to the invention along the sectional plane A-A of FIG. 12C;  
         [0110]    [0110]FIG. 12B is a cross-sectional side view of the alternative embodiment of the contact connection process according to the invention along the sectional plane B-B of FIG. 12C;  
         [0111]    [0111]FIG. 12C is a cross-sectional plan view of the alternative embodiment of the contact connection process according to the invention along the sectional plane C-C of FIGS. 12A and 12B;  
         [0112]    [0112]FIG. 13A is a cross-sectional side view of the alternative embodiment of the contact connection process according to the invention along the sectional plane A-A of FIG. 13C;  
         [0113]    [0113]FIG. 13B is a cross-sectional side view of the alternative embodiment of the contact connection process according to the invention along the sectional plane B-B of FIG. 13C;  
         [0114]    [0114]FIG. 13C is a cross-sectional plan view of the alternative embodiment of the contact connection process according to the invention along the sectional plane C-C of FIGS. 13A and 13B;  
         [0115]    [0115]FIG. 14A is a cross-sectional side view of a third alternative embodiment of the contact connection process according to the invention along the sectional plane A-A of FIG. 14C;  
         [0116]    [0116]FIG. 14B is a cross-sectional side view of the third alternative embodiment of the contact connection process according to the invention along the sectional plane B-B of FIG. 14C;  
         [0117]    [0117]FIG. 14C is a cross-sectional plan view of the third alternative embodiment of the contact connection process according to the invention along the sectional plane C-C of FIGS. 14A and 14B;  
         [0118]    [0118]FIG. 15A is a cross-sectional side view of the third alternative embodiment of the contact connection process according to the invention along the sectional plane A-A of FIG. 15C;  
         [0119]    [0119]FIG. 15B is a cross-sectional side view of the third alternative embodiment of the contact connection process according to the invention along the sectional plane B-B of FIG. 15C; and  
         [0120]    [0120]FIG. 15C is a cross-sectional plan view of the third alternative embodiment of the contact connection process according to the invention along the sectional plane C-C of FIGS. 15A and 15B. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0121]    In the figures of the drawings, unless stated otherwise, identical reference symbols denote identical parts.  
         [0122]    Referring now to the figures of the drawings in detail and first, particularly to FIGS. 1A to  2 C thereof, there is shown, in lateral cross-sectional view and in plan view, a first intermediate state of an embodiment of the fabrication method according to the invention. A semiconductor substrate region  20  with a substantially planar surface  20   a  is provided. The semiconductor substrate region or material region  20  may be a p-doped (or n-doped) silicon material or the like. The latter may already be processed and provided, e.g., with suitable wells. Mask regions  100 , which serve to form corresponding doping regions  21  (see FIGS. 2A to  2 C), are applied in strip form. This is done by implantation in the arrow direction.  
         [0123]    In the transition to the intermediate state shown in FIGS. 2A to  2 C, a doping region  21  is formed locally in the surface region  20   a  of the semiconductor material region  20  and to a certain depth underneath, for example, in the form of an n + -doped (or p + -doped) silicon material region, by a corresponding implantation technique. The doping regions  21  formed have a substantially planar surface  21   a . FIG. 2C shows a plan view of the locally doped semiconductor material  20 , and FIGS. 2A and 2B show corresponding cross-sectional side views along the sectional planes A-A and B-B, respectively. The formation of the doping regions  21  results in the creation, by implantation, of a precursor of the source/drain regions SD 1  and SD 2  (see FIG. 3C) to be formed for each of the floating gate memory cells  10  (see FIGS. 11A to  11 C).  
         [0124]    Afterward, the semiconductor material  20  with the corresponding doping regions  21  is patterned, thereby producing corresponding silicon lamellae L as main regions L for the floating gate memory cells  10  to be formed. As emerges from the plan view of FIG. 3C and the sectional side views  3 A and  3 B, the lamella L has, as main region L, a substantially linearly extended parallelepiped structure with side regions Lb and a surface region La, which is configured to be substantially planar. By the etching process, in the transition to the intermediate state shown in FIGS. 3A to  3 C, the surface region  20   a  of the semiconductor substrate region  20  is etched back to a surface region  20   a ′, thereby uncovering the corresponding structure of the lamella L.  
         [0125]    In principle, in the context of such an etching step, it is possible to form a multiplicity of lamellae that are spaced apart parallel and equidistantly in the manner of a bar grating on the surface region  20   a  or  20   a ′ of the semiconductor substrate region  20 , for example, in the context of a fabrication method for simultaneously producing a multiplicity of floating gate memory cells of a semiconductor memory device.  
         [0126]    As emerges from FIG. 3B, the semiconductor material region or semiconductor substrate region  20  is etched back to form the main regions or lamellae L by a depth that approximately corresponds to the depth of the doping or implantation in the doping regions  21 . If appropriate, an overetching may also take place to better separate the doped regions from one another.  
         [0127]    The remaining regions SD 1 , SD 2  of the doping regions  21  serve as source/drain regions SD 1 , SD 2  of the source/drain configuration SD. In between lies the region  22 , the channel region K.  
         [0128]    In the transition to the state of FIGS. 4A to  4 C, an insulation layer  31  is, then, formed over the whole area and/or conformally, for example, by growth or deposition. In such a case, at the side regions Lb of the lamellae L, insulation regions  30  are produced as part of the insulation layer  31 , which substantially extend vertically there and serve for insulating the floating gates to be formed from the channel region  22  and from the doping regions  21 .  
         [0129]    The insulation layer  31  can be formed strictly conformally or else, as revealed in the comparison of FIGS. 4A to  4 C, be formed with a larger layer thickness D in the region of the doping regions  21  compared with the otherwise thinner layer thickness d. The larger layer thickness D results quite automatically in the case of high dopings, for example, in the case of n + -type silicon, and has the advantage that a lower capacitance is, thus, present between control gate G 1 , G 2  (see FIGS. 9A to  9 C) and respective source/drain region SD 1  or SD 2 .  
         [0130]    A material layer  40  for the floating gates F 1 , F 2  (see FIGS. 7A to  7 C) of the floating gate configuration F that are to be formed is applied in a manner directly adjoining the insulation layer  30 ,  31 , in particular, by deposition. In such a case, a polysilicon material  40  was used in the intermediate state of the fabrication method according to the invention as shown in FIGS. 5A to  5 C. The deposition or formation of such polysilicon for the floating gates F 1 , F 2  is effected over the whole area.  
         [0131]    As is shown in FIGS. 6A to  6 C, the floating gates F 1  and F 2  are, then, formed by patterning the material region  40  for the floating gates F 1 , F 2 . To that end, columns  42  or recesses  42  are formed by etching, which run substantially perpendicularly to the direction of extent of the main regions L of the memory cells  10  to be formed. In such a case, in this first patterning step, as is shown in FIGS. 1A through 6C, the material region  40  for the floating gates F 1 , F 2  remains only in the overlap region with respect to the channel region K,  22  to be formed and in a column containing the channel region  22 , K perpendicularly to the direction of extent of the main region L. In such a case, the material region  40  for the floating gates F 1 , F 2  can significantly overlap the source/drain regions SD 1 , SD 2  to be formed, that is to say, the doping regions  21 .  
         [0132]    In the transition to the intermediate state shown in FIGS. 7A to  7 C, the material region  40  for the floating gates to be formed is, then, etched back over the whole area. The etching back is effected to a point below the level of the surface regions La and  20   a ′ of the lamella L and of the drawn-back semiconductor substrate region  20 , respectively, so that the material  40  for the floating gates F 1  and F 2  to be formed remains only in the region of the side regions Lb of the main region L. Thus, the two floating gates F 1 , F 2  are formed precisely in the side regions Lb of the lamellae L in a form insulated from the doping regions  21  and from the semiconductor substrate region  20  by the insulation regions  30 ,  31 .  
         [0133]    In the transition to the intermediate state shown in FIGS. 8A to  8 C, a material region  50  for the intermediate insulation region Z to be formed is, then, formed conformally in a whole-area manner, in particular, by a deposition process. Such an intermediate insulation region is also referred to as an interpoly dielectric.  
         [0134]    The formation is followed directly afterward by the deposition of a material region  60  for the control gates G 1  and G 2  to be formed. The intermediate state in FIGS. 9A to  9 C is a whole-area polysilicon deposition. If appropriate, a deposition of polycide, metal, and/or the like is conceivable.  
         [0135]    In the transition to the intermediate state in FIGS. 10A to  10 C, the control gates G 1  and G 2  are, then, patterned. The patterning is performed by whole-area anisotropic etching back so that the material  60  for the control gates G 1  and G 2  remains only at the edge of the lamella L adjacent to the floating gates F 1  and F 2 . A significant overetching is provided in a manner similar to that when forming the floating gates F 1  and F 2 . This is not necessary, however, with the use of source/drain contacts.  
         [0136]    In the edge region, a masked etching is additionally necessary—as in the case of the floating gates F 1 , F 2 —in order to isolate the control gates G 1 , G 2 . These processes are not explicitly illustrated here.  
         [0137]    In the transition to the intermediate state shown in FIGS. 11A to  11 C, embedding in a further insulation region  70 , for example, in the form of a silicon dioxide, is, then, effected.  
         [0138]    The above-described patterning has, thus, produced a floating gate memory cell  10  in which a floating gate region F has two floating gates F 1  and F 2  that are spatially separate from one another, in which a control gate region G has control gates G 1  and G 2  that are spatially separate from one another and face the respective floating gates F 1  and F 2 , and in which the source/drain region SD has common first and second source/drain regions SD 1 , SD 2  for both gate structures.  
         [0139]    As a rule, such a procedure does not produce a single floating gate memory cell  10  locally, but rather, in a spatially extended semiconductor substrate region  20 , a multiplicity of floating gate memory cells  10  disposed in matrix form for forming a semiconductor memory device according to the invention for nonvolatile information storage.  
         [0140]    In principle, two different process implementations are conceivable for the respective contact connection of the source/drain regions SD 1  and SD 2 .  
         [0141]    To obtain a cell area that is as small as possible, a lithographic definition of contact holes is dispensed with. The removal of the insulation layers  70 ,  50 ,  31  above the source/drain regions SD 1  and SD 2  is effected either by chemical mechanical polishing or CMP with a stop on the surfaces of the source/drain regions or by etching. Such a procedure is illustrated in FIGS. 12A to  13 C.  
         [0142]    With the use of contactless architecture, metal interconnects can be completely dispensed with. Then, exclusively the buried bit and source lines are used.  
         [0143]    In the last-mentioned case, the lamella is not etched out to a depth such that the doping regions/diffusion regions for the source/drain regions would, thereby, be electrically isolated.  
         [0144]    As is shown in the state of FIGS. 12A to  12 C, strip-like etching free is effected by a mask configuration for the bit lines or source/drain line devices.  
         [0145]    In the transition to the intermediate state shown in FIGS. 13A to  13 C, a whole-area metal deposition is, then, effected for the purpose of contact connection, the recesses  92  in the insulation regions  70 ,  50 ,  30 ,  31  to the source/drain regions SD 1 , SD 2  being filled with a corresponding metal  95 . Electrical-insulations of these fillings  95  are, then, isolated from one another by etching back or polishing with a stop on the surface  70   a  of the embedding insulation region  70 .  
         [0146]    In a different contact connection process, to obtain a large process window and to avoid major overetching of the floating gates F 1  and F 2  and of the control gates G 1  and G 2 , a contact connection to the source/drain regions SD 1  and SD 2  is provided. Such a procedure is illustrated in FIGS. 14A to  15 B.  
         [0147]    [0147]FIGS. 14A to  14 C thereof firstly illustrate the formation of contact holes with a corresponding metallic filling  94  of the contact holes. A significant overetching of the floating gates F 1  and F 2  or of the control gates G 1  and G 2  is not necessary in this case. In the transition to the intermediate state shown in FIGS. 15A to  15 C, a metal deposition  95  is, then, once again carried out to form bit lines and source lines. The metal layer can be patterned jointly with the contacts using a dual damascene technique.