Abstract:
A method is described that level shifts a differential signal to produce a first signal and level shifts the logical inverse of the differential signal to produce a second signal that is the logical inverse of the first signal. The method then inverts the first signal and inverts the second signal. The method then inverts the first signal and the inverted second signal together and inverts the second signal and the inverted first signal together.

Description:
CLAIM FOR PRIORITY OF EARLIER FILING DATE 
     The present application hereby claims the benefit of a U.S. Provisional Application filed on Apr. 5, 2001 and provided Application No. 60/282,213. 
    
    
     FIELD OF THE INVENTION 
     The field of invention relates to signal processing generally; and, more specifically, to a method and apparatus for a level shifter with a symmetrical output waveform. 
     BACKGROUND 
     FIG. 1 a  shows an embodiment of a differential to single ended level shifter  101 . A level shifter  101  changes an electronic signal&#39;s voltage level(s). Differential to single ended means the input signal is differential and the output signal is single ended. FIG. 1 b  shows an embodiment of a transistor level design for the level shifter  101  of FIG. 1 a . FIG. 1 c  shows an exemplary differential input signal (IN+, IN−)  102   c ,  103   c  and an exemplary single ended output signal (LS OUT) 104   c  for the level shifter embodiment  101  of FIG. 1 b.    
     As observed with respect to the exemplary waveforms of FIG. 1 c , the level shifter  101  output signal  104   c  provides the same logical information as the differential input signal  102   c ,  103   c  (IN+, IN−) but with different voltage levels. That is, the input signals  102   c  and  103   c  (IN+ and IN−) swing over a voltage range of “A” volts while the output signal  104   c  (LS OUT), in response, swings over a voltage range of “Vcc” volts−where Vcc&gt;A (noting that GND corresponds to 0.0 volts). 
     Different voltage swings (as between the input and output signals) correspond to the changing or “shifting” of at least one input voltage level to a new output voltage level. The particular level shifter  101  that is shown in FIGS. 1 a  and  1   b  (and whose operation is demonstrated in FIG. 1 c ) may be referred to as a “rail-to-rail” level shifter because the output signal  104   c  (LS OUT) swings between the shifter&#39;s supply rails of Vcc and GND. Rail-to-rail level shifters are often used for changing the levels of an electronic signal to better conform to those expected by digital circuitry (e.g., that is coupled to output  104   a,b ). 
     A problem with differential to single ended level shifters (including those of the rail-to-rail type) is the lack of symmetry between the rise times and fall times of the output signal waveform  104   c  (LS OUT). For example, referring to the exemplary output signal waveform  104   c  of FIG. 1 c , note that the signal rise time T 1  is less than the signal fall time T 2 . The asymmetry between rise and fall times arises from the asymmetry in the design of the level shifter. 
     That is, the conversion of a differential signal into a single ended signal involves asymmetrical processing. For example, referring to the exemplary transistor level embodiment of FIG. 1 b  and the exemplary waveforms  102   c ,  103   c  and  104   c  of FIG. 1 c , note that a logic low IN−  103   c  signal value corresponds to logic high LS OUT  104   c  signal value of Vcc. According to the design of FIG. 1 b , the above described relationship between IN− and LS OUT is achieved by transistor Q 2 . Specifically, when IN− is a logic low Q 2  turns “on” which, in turn, effectively shorts the output node  104   b  to the Vcc rail. 
     Note also that a logic low IN+  102   c  signal value corresponds to a logic low LS OUT  104   c  signal value. According to the design of FIG. 1 b , the above described relationship between IN+ and LS OUT is achieved by transistors Q 1 , Q 3  and Q 4 . Specifically, when IN+ is a logic low Q 1  turns “on” which results in the driving of current through Q 3 . The driving of current through Q 3  raises the drain-to-source voltage across Q 3  which, correspondingly, also raises the gate voltage on Q 4 . Raising the gate voltage on Q 4  eventually turns “on” Q 4  which, in turn, effectively shorts the output node  104   b  to the GND rail. 
     Comparing the dynamics of how the output voltage rails of Vcc or GND are formed at the level shifter output node  104   b , note that one transistor (Q 2 ) is mostly involved with the raising of the output  104   b  LS OUT voltage to Vcc; while three transistors (Q 1 , Q 3 , Q 4 ) are mostly involved with the lowering of the output  104  LS OUT voltage to GND. Because less transistors are involved with the raising of the output  104   b  LS OUT voltage than its lowering, the output  104   b  LS OUT voltage rises faster than it falls. 
     Hence, as mentioned above, the rise time T 1  of the output signal waveform  104   c  LS OUT (of FIG. 1 c ) is less than its fall time T 2 . Problems may arise if a signal having an asymmetry (such as the level shifter output signal  104   c  LS OUT having the aforementioned difference between its rise and fall times) is processed or otherwise used. For example, data may be incorrectly interpreted. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example, and not limitation, in the Figures of the accompanying drawings in which: 
     FIG. 1 a  shows a differential to single ended level shifter; 
     FIG. 1 b  shows an embodiment of a transistor level design for the level shifter of FIG. 1 a;    
     FIG. 1 c  shows exemplary input and output signal waveforms for the level shifter embodiment of FIG. 1 b.    
     FIG. 2 a  shows a differential to single ended level shifting approach having improved rise and fall times as compared to the level shifter of FIG. 1 a ; 
     FIG. 2 b  shows an embodiment of a transistor level design for the level shifting approach of FIG. 2 a;    
     FIG. 2 c  shows exemplary input and output signal waveforms for the level shifting embodiment of FIG. 2 b.    
     FIG. 3 a  shows a differential to differential level shifting approach having rise and fall times that are comparable to the level shifting approach of FIG. 2 a;    
     FIG. 3 b  shows an embodiment of a transistor level design for the level shifting approach of FIG. 3 a;    
     FIG. 3 c  shows exemplary input and output signal waveforms for the level shifting embodiment of FIG. 3 b;    
     FIG. 4 a  shows a differential to differential level shifting approach having less duty cycle distortion and rise/fall time misalignment as compared to the level shifting approach of FIG. 3 a;    
     FIG. 4 b  shows an embodiment of a transistor level design for the level shifting approach of FIG. 4 a;    
     FIG. 4 c  shows exemplary input and output signal waveforms for the level shifting embodiment of FIG. 4 b.    
    
    
     DETAILED DESCRIPTION 
     As described in the background, problems may arise if a signal having an asymmetry (such as the level shifter output signal  104   c  LS OUT of FIG. 1 c  having a difference between its rise and fall times) is processed or otherwise used. The following discussion will develop an approach for an improved level shifter that provides a symmetrical output signal. The improved approach will be demonstrated by first discussing the effect of some modifications that may be made to the basic level shifter of FIGS. 1 a  through  1   c.    
     For example, FIGS. 2 a  through  2   c  relate to a technique that may be used to reduce the rise and fall times of the level shifter output signal. That is, comparing the level shifter output signal  104   c  LS OUT of FIG. 1 c  with the output signal  207   c  OUT of FIG. 2 c , note that the rise and falls times of signal  207   c  are substantially less than the rise and fall times T 1  and T 2  of signal  104   c . The reduction in rise and fall times, referring to FIG. 2 a , are obtained by the introduction of a pair of cascade inverters  205   a  and  206   a  that follow the differential-to-single ended to level shifter  201   a  (as described in more detail below). 
     For simplicity, in one embodiment, the differential-to-single ended level shifter  201   a  of FIG. 2 a  may be viewed as corresponding to the differential-to-single ended level shifter  101   a  of FIG. 1 a . As such, referring to FIGS. 2 c  and  1   c , the IN+ signal  202   c , IN− signal  203   c  and LS OUT signal  204   c  of FIG. 2 c  correspond to the IN+ signal  102   c , IN− signal  103   c  and LS OUT signal  104   c  of FIG. 1 c . Note that the aforementioned asymmetry between the rise and fall times of the LS OUT signal  204   c  are observed in FIG. 2 c.    
     The first inverter  205   a  provides the logical inverse of the LS OUT signal  204   c . That is, if the LS OUT signal  204   c  corresponds to a logical “high”, the first inverter  205   a  will present a logical “low”; and, if the LS OUT signal  204   c  corresponds to a logical “low”, the first inverter  205   a  will present a logical “high”. The decision made by the first inverter  205   a  (as to whether to not the LS OUT signal  204   c  corresponds to a logical high or logical low) may be effectively made against a threshold level. 
     For example, with respect to the particular embodiment of FIGS. 2 b  and  2   c , the decision made by the first inverter  205  is effectively made against a threshold level of Vcc/2 (which is drawn super-imposed upon the LS OUT signal  204   c  of FIG. 2 c ). As such, as observed from the first inverter output signal  205   c , if the LS OUT signal  204   c  rises above Vcc/2 the first inverter  205   a  provides a logical “low”; and, if the LS OUT signal  204   c  falls below Vcc/2, the first inverter  205   a  provides a logical “high”. 
     Recall from above that the level shifter architecture of FIG. 2 a  allows for an output signal OUT  207   c  having smaller rise and fall times than the level shifter output signal LS OUT  104   c  of FIG. 1 c . The rise and fall times of the first inverter output signal  205   c  may be made small by designing the first inverter  205   a,b  to supply enough current to rapidly charge the parasitic capacitance(s) and inductance(s) that reside between the first  205   a ,  205   b  and second  206   a ,  206   b  inverters. 
     FIG. 2 b  corresponds to an embodiment of a transistor level design for the level shifting approach of FIG. 2 a . Referring to FIG. 2 b , note that a higher transistor gain corresponds to larger transistor current magnitude (e.g., where transistor gain corresponds to transistor transconductance as measured by output IDS current per input VGS voltage). As such, in order to achieve small rise and fall times at the first inverter  205   a ,  205   b  output, the transistors Q 5  and Q 6  that drive the first inverter  205   b  output may be designed with a larger gain (e.g., transconductance) than that associated with the transistors Q 2  and Q 4  within the level shifter  201   a,b.    
     The second inverter  206   a,b  provides the logical inverse of the first inverter output signal  205   c ; and, in so doing, effectively provides the logical values originally presented by the level shifter output signal  204   c . That is, the logical inversion provided by the first inverter  205   a,b  is effectively reversed so that the output signal OUT  207   c  corresponds to a level shifted version of the non inverted input signal IN+  202   c.    
     The small rise and fall times achieved with the first inverter  205   a,b  may be rippled through to the output signal OUT  207   c  of the second inverter  206   a,b  by designing the transistors Q 7  and Q 8  of the second inverter  206   a,b  with high transconductance as described above. In alternate embodiments, only the second inverter  206   a,b  (or only the first inverter  205   a,b ) is designed with transistors having large transconductance. 
     Note that, if the rise and fall times of the output signal OUT  207   c  are designed to be small and an asymmetry exists as between the rise and fall times of the level shifter output signal  204   c  LS OUT (as observed in FIG. 2 c ), the output signal  207   c  has duty cycle distortion. That is, within output signal OUT  207   c , the width T 3  of a logical high value is noticeably different than the width T 4  of a logical low value. In a sense, the asymmetry as between the rise and fall times T 1 , T 2  of the level shifter output signal  204   c  LS OUT is converted into an asymmetry as between the logical high and logical low widths T 3 , T 4  of the output signal  207   c  OUT. 
     As described in the background, problems may arise if a signal having an asymmetry is processed or otherwise used. As such, additional circuitry may be added to the approach outlined in FIGS. 2 a  through  2   c  that help correct for the asymmetry. FIGS. 3 a  through  3   c  relate to a differential-to-differential level shifting approach that may be used, with some modification (as described in more detail with respect to FIGS. 4 a  through  4   c ), to correct for the level shifting asymmetries discussed so far. 
     A differential-to-differential level shifting approach accepts (as an input) a differential signal and provides (as an output) a differential, level shifted version of the input signal. FIG. 3 a  shows a differential-to-differential level shifting approach having rise and fall times that are comparable to the level shifting approach of FIG. 2 a . FIG. 3 b  shows an embodiment of a transistor level design for the approach of FIG. 3 a.    
     In one respect, the differential-to-differential level shifting approach of FIG. 3 a  may be viewed as a pair of differential-to-single ended circuits that each level shift one component of the differential input signal. That is, level shifter  301   a  and inverters  305   a  and  306   a  may be viewed as corresponding to level shifting circuitry for positive input IN+  302   a ; and level shifter  311   a  and inverters  315   a  and  316   a  may be viewed as corresponding to level shifting circuitry for negative input IN−  303   a . As such, referring to FIGS. 3 a  and  3   c , the level shifter  301   a  output signal  304   c  LS OUT+ and the inverter  305   a ,  306   a  output signals  305   c ,  307   c  are similar to the level shifter  201   a  output signal  204   c  LS OUT and the inverter  205   a ,  206   a  output signals  205   c ,  207   c  of FIGS. 2 a  and  2   c.    
     Furthermore, note that level shifter  311   a  may be viewed as corresponding to level shifter  301   a  with reversed inputs. As such, level shifter  311   a  “level shifts” the IN− input signal  303   c  whereas level shifter  301   a  “level shifts” the IN+ input signal  302   c . Because IN−  302   a,c  is the logical inverse of IN+  303   a,c , the level shifter  311   a  output signal  314   c  LS OUT− and the inverter  315   a ,  316   a  output signals  315   c ,  317   c  may be viewed as corresponding to the logical inverse of, respectively: the level shifter  301   a  output signal  304   c  LS OUT+ and the inverter  305   a ,  306   a  output signals  305   c ,  307   c.    
     Note, however, that the rise/fall time asymmetries observed within the level shifter  301   a ,  311   a  output signals  301   c  LS OUT+,  311   c  LS OUT− not only cause duty cycle distortion but also cause rise/fall time misalignment as between the  307   c  OUT+ signal and the  317   c  OUT− signal. That is, both output signals  307   c  OUT+ and  317   c  OUT− posses duty cycle distortion (as discussed above with respect to signal  207   c  OUT of FIG. 2 c ). 
     Furthermore, the rise times T 5 , T 7 , T 9  of the OUT− signal  317   c  are not aligned with the fall times of the OUT+ signal  307   c ; and, similarly, the fall times T 6 , T 8 , T 10  of the OUT− signal  317   c  are not aligned with the rise times of the OUT+ signal  307   c . The misalignment of the rise/fall times results from the logically inverted relationship that level shifter  301   a  performs with respect to level shifter  311   a  (combined with the rise and fall time asymmetry that exists in the LS OUT+ signal  304   c  and the LS OUT− signal  314   c ). 
     That is, an LS OUT+ signal  304   c  rise time and an LS OUT− signal  314   c  fall time both correspond to the transition from a logical low to a logical high. As these transitions occur at different rates (because the LS OUT+ signal  304   c  rise time is less than the LS OUT− signal  314   c  fall time), they cross the Vcc/2 threshold at different times. The crossing of the Vcc/2 threshold at different times results directly in the rise/fall time misalignment just described. An analogous situation exists with respect to the LS OUT+ signal  304   c  fall time and the LS OUT− signal  314   c  rise time. 
     The duty cycle distortion of the OUT+  307   c  and OUT−  317   c  signals, as well as the misalignment of their rise/fall times, may be viewed (once again) as asymmetries that should be corrected for. FIGS. 4 a  through  4   c  correspond to a differential-to-differential level shifting approach having less duty cycle distortion and rise/fall time misalignment than the level shifting approach just discussed with respect to FIGS. 3 a  through  3   c.    
     Note that the approach of FIG. 4 a  corresponds to the approach of FIG. 3 a  having a pair of cross coupling lines  450   a ,  451   a . That is, cross coupling line  450   a  couples the output  414   a  of the level shifter  411   a  that “level shifts” the IN− input  403   a,c  to the input of the inverter  406   a  that provides the OUT+ output signal  407   a . Similarly, cross coupling line  451   a  couples the output  404   a  of the level shifter  401   a  that “level shifts” the IN+ input  402   a,c  to the input of the inverter  416   a  that provides the OUT− output signal  417   a.    
     The cross coupling lines  450   a ,  451   a  effectively eliminate (or at least reduce) the duty cycle distortion and rise/fall time misalignments described above with respect to the approach of FIGS. 3 a  through  3   c . That is, referring to FIG. 4 c , note that the OUT+ signal  407   c  and the OUT− signal  417   c  each have an approximately 50—50 duty cycle (i.e., width T 11  is about the same as width T 12 ); and, the rise times of the OUT+ signal  407   c  occur at approximately the same time as the fall times of the OUT− signal  417   c  (and, the fall times of the OUT+ signal  407   c  occur at approximately the same time as the rise times of the OUT− signal  417   c ). 
     The cross coupling lines  450   a ,  451   a  allow the asymmetrical rise time and fall time associated with the output signal of each level shifter  401   a ,  411   a  to effectively correct for itself. That is, symmetrical rise and fall times are formed at each level shifter output LS OUT+  404   a,c  and LS OUT−  414   a,c . Referring briefly back to FIGS. 3 a  and  3   c , recall that the LS OUT+  304   a,c  signal has a slow fall time from a logical high to a logical low; and that, the LS OUT−  314   a,c  signal has a slow fall time from a logical low to a logical high. 
     With respect to the approach of FIGS. 4 a  through  4   c , in a sense, because a signal processing path exists from the level shifter  411   a  output LS OUT−  414   a  to the OUT+ node  407   a  (via inverter  405   a  and coupling line  450   a ) and because a signal processing path exists from the level shifter  401   a  output LS OUT+  404   a  to the OUT− node  417   a  (via inverter  415   a  and coupling line  451   a ), the circuitry of FIG. 4 a  processes the differential input signal as cooperative whole rather than (as with the circuitry of FIG. 3 a ) individually process different components of the differential input signal in an isolated fashion. This results in the small rise times and long fall times normally associated with the level shifter output signals automatically offsetting one another. 
     That is, via cross coupling signal lines  450   a  and  451   a , the “faster” rise time of level shifter  411   a  (associated with the transition from a logical high to a logical low) acts to quicken the “slower” fall time of the LS OUT+  404   a,c  signal; and, the “faster” rise time of level shifter  401   a  (associated with the transition from a logical low to a logical high) acts to quicken the “slower” fall time of the LS OUT−  414   a,c  signal. As such, the circuit operates in a balanced fashion that produces balanced output signals OUT+  407   c , OUT−  417   c  as represented by their 50—50 duty cycle and their aligned rise/fall times with respect to one another. 
     FIG. 4 b  represents a transistor level embodiment for the approach presented in FIG. 4 a . In order to enhance the balancing described above, the PMOS transistors Q 1 , Q 2 , Q 5 , Q 7 , Q 9 , Q 10 , Q 13 , Q 15  may be designed with larger gate widths (as compared to their corresponding NMOS transistors Q 3 , Q 4 , Q 6 , Q 8 , Q 11 , Q 12 , Q 14 , Q 16 ) so that push/pull transistor pairs (e.g., Q 1  and Q 3 , Q 2  and Q 4 , etc.) have approximately equal gain with respect to each other. 
     It is important to point out that, because level shifting circuits are varied and well known in the art, other level shifter transistor level designs may be substituted for those illustrated in the Figures and discussed above. Furthermore, level shifters may be rail-to-rail or non rail-to-rail; and, the rail voltages may vary from embodiment. For example, in one embodiment a first rail may be a positive voltage and the second rail may be a negative voltage; and, in other embodiments a first rail may be a ground reference and a second rail may be fixed at either a positive or negative voltage. 
     Note also that embodiments of the present description may be implemented not only within a semiconductor chip but also within machine readable media. For example, the designs discussed above may be stored upon and/or embedded within machine readable media associated with a design tool used for designing semiconductor devices. Examples include a netlist formatted in the VHSIC Hardware Description Language (VHDL) language, Verilog language or SPICE language. Some netlist examples include: a behaviorial level netlist, a register transfer level (RTL) netlist, a gate level netlist and a transistor level netlist. Machine readable media also include media having layout information such as a GDS-II file. Furthermore, netlist files or other machine readable media for semiconductor chip design may be used in a simulation environment to perform the methods of the teachings described above. 
     Thus, it is also to be understood that embodiments of this invention may be used as or to support a software program executed upon some form of processing core (such as the CPU of a computer) or otherwise implemented or realized upon or within a machine readable medium. A machine readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc. 
     In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.