Abstract:
An operational amplifier ( 1 B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier ( 1 C) including a first amplifier stage ( 2 ) receiving the input signal, a second amplifier stage ( 3 ) driven by the first amplifier stage ( 2 ), and a third amplifier stage ( 4 ) driven by the second amplifier stage to produce the output signal. A slew detection current (Idetect) is generated when the input signal (Vin) exceeds a certain magnitude, and is converted to a control signal ( 41 ) that operates a switch (MN0) to short-circuit output conductors of the first amplifier stage to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage during slewing. The three stage amplifier can be a chopper-stabilized, notch-filtered amplifier.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates generally to slew rate and settling time improvement circuitry and methods for three-stage amplifiers, including chopper-stabilized three-stage amplifiers with notch filtering, chopper-stabilized three-stage amplifiers without notch filtering, and traditional three-stage amplifiers without chopper stabilization and notch filtering. 
         [0002]    The closest prior art is believed to include the assignee&#39;s U.S. Pat. No. 7,292,095 Entitled “Notch Filter for Ripple Reduction in Chopper Stabilized Amplifiers” issued November  6 ,  2007  to Rodney T. Burt and Joy Y. Zhang, and incorporated herein by reference. The closest prior art is believed to also include the article “A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter with Synchronous Integration Inside the Continuous-Time Signal Path” by Rod Burt and present inventor Joy Zhang, IEEE Journal of Solid-State Circuits, volume 41, Number 12, December 2006, pages 2729-2736. 
         [0003]      FIG. 1  shows a “traditional” basic three-stage amplifier  1 A with multipath nested Miller compensation. This circuit configuration can be thought of as including a three-stage high gain signal path including three sequentially coupled stages  2 ,  3  and  4  having transconductances of gm 1 , gm 2 , and gm 3 , respectively, coupled in parallel with a wider bandwidth two stage signal path including two sequentially coupled stages  5  and  4  having transconductances of gm 4  and gm 3 , respectively. The amount of DC precision of the operational amplifier shown in  FIG. 1  is determined by the input stage  2  in the three-stage high gain signal path, while the high frequency response and phase margin are dominated by the two-stage signal path. Proper selection of the transconductances and the compensation capacitances results in the operational amplifier having the bandwidth and settling characteristics of a two-stage Miller compensated operational amplifier with a minimal increase in quiescent supply current Iq being required to achieve a good GBW/Iq (i.e., gain-bandwidth/Iq) ratio. 
         [0004]      FIG. 2  shows the operational amplifier configuration of  FIG. 1  further including basic chopper stabilization circuitry added before and after the input stage  2  in the high gain three-stage DC signal path. The chopper stabilization has the advantage of substantially reducing offset voltage, offset voltage drift with respect to temperature, and flicker noise, but has the disadvantage of shifting the offset voltage of the input stage  2  to the chopping frequency fs and thereby producing a ripple voltage component in the amplifier output Vout. The chopper-stabilized 3-stage amplifier of  FIG. 2  provides excellent DC accuracy and low drift because any low frequency errors are essentially eliminated by the chopping switch. However, the drawback of a chopper-stabilized amplifier is that its output signal includes a ripple component due to the chopping switches. To overcome the output ripple, a switched capacitor notch filter is added after the chopping switch to filter out the ripple, as shown in  FIG. 3 . 
         [0005]      FIG. 3  is a detailed schematic diagram of a three-stage chopper-stabilized amplifier including notch filtering for ripple reduction as described in the assignee&#39;s above-mentioned U.S. Pat. No. 7,292,095. In  FIG. 3 , chopper-stabilized amplifier IC includes operational transconductance amplifier  2  having an input chopper  9  and an output chopper  10 . Choppers  9  and  10  operate in response to clock signals Phase  1  and Phase  2 , as shown. Switched capacitor notch filter  15  filters the chopped output of operational transconductance amplifier  2  synchronously with the chopping frequency of output chopper  10  to filter ripple voltage component of operational transconductance amplifier  2 . Operational transconductance amplifier  3  amplifies the output of notch filter  15 , which operates in response to clock signals Phase  3  and Phase  4 . Vin, after being amplified by operational transconductance amplifier  2  and chopped by choppers  9  and  10 , and is fed forward into the input of the second operational transconductance amplifier  3 , the output of which is applied to the input of operational transconductance amplifier  4 . 
         [0006]    Notch filter  15  operates to average out the error at the output of the input transimpedance stage  2  during each ½ chopping clock cycle, then transfers the averaged signal to the next transimpedance stage  3 . Although notch filter  15  works fairly well with the chopping technique (it reduces the output ripple to a level that is not even visible on an oscilloscope), its averaging function increases the settling time during a large signal slewing operation because notch filter  15  treats the fast changing, large-magnitude Vin signal as an error signal and averages it, as subsequently explained in detail with reference to  FIG. 4 . The result of the averaging process is that it takes several clock cycles for Vout to reach its final ideal value after a large-signal stewing. Therefore, the settling time of Vout is limited by the number of clock cycles needed to average the error signal to within a specified tolerance. (Even though the chopping clock frequency can be increased to reduce the settling time, a very high chopping frequency will cause many other problems due to parasitic capacitance in the circuitry and will increase the difficulty of implementing the amplifier of  FIG. 3 .) 
         [0007]    There is an unmet need for a three-stage amplifier having fast output stewing rate and fast output settling time. 
         [0008]    There also is an unmet need for a three-stage chopper-stabilized amplifier having fast output stewing rate and fast output settling time. 
         [0009]    There also is an unmet need for a three-stage chopper-stabilized, notch-filtered amplifier having fast output stewing rate and fast output settling time. 
         [0010]    There also is an unmet need for a chopper-stabilized amplifier having extremely low output ripple noise and also having fast output slewing rate and fast output settling time. 
         [0011]    There also is an unmet need for a chopper-stabilized operational amplifier having extremely low output ripple noise, very low offset voltage, fast output slewing rate, and fast output settling time. 
       SUMMARY OF THE INVENTION 
       [0012]    It is an object of the invention to provide a three-stage amplifier having fast output slewing rate and fast output settling time. 
         [0013]    It is another object of the invention to provide a three-stage chopper-stabilized amplifier having fast output slewing rate and fast output settling time. 
         [0014]    It is another object of the invention to provide a three-stage chopper-stabilized, notch-filtered amplifier having fast output slewing rate and fast output settling time. 
         [0015]    It is another object of the invention to provide a chopper-stabilized amplifier having extremely low output ripple noise and also having fast output slewing rate and fast output settling time. 
         [0016]    It is another object of the invention to provide a chopper-stabilized operational amplifier having extremely low output ripple noise, very low offset voltage, fast output slewing rate, and fast output settling time. 
         [0017]    Briefly described, and in accordance with one embodiment, the present invention provides an operational amplifier ( 1 B) which amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (IC) including a first amplifier stage ( 2 ) receiving the input signal, a second amplifier stage ( 3 ) driven by the first amplifier stage ( 2 ), and a third amplifier stage ( 4 ) driven by the second amplifier stage to produce the output signal: A slew detection current (Idetect) is generated when the input signal (Vin) exceeds a certain magnitude, and is converted to a control signal ( 41 ) that operates a switch (MN 0 ) to short-circuit output conductors of the first amplifier stage to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage during slewing. 
         [0018]    In one embodiment, the invention provides an operational amplifier ( 1 E, 1 D) including a 3-stage amplifier ( 1 A, 1 B, or  1 C) having first ( 7 A) and second ( 7 B) input conductors conducting a differential input signal (Vin) and an output ( 25 ) conducting an output signal (Vout). The 3-stage amplifier ( 1 A, 1 B, or  1 C) includes a first amplifier stage ( 2 ) having an input coupled to the input signal (Vin), a second amplifier stage ( 3 ) having an input coupled to an output of the first amplifier stage ( 2 ), and a third amplifier stage ( 4 ) having an input coupled to an output of the second amplifier stage ( 3 ) and an output ( 25 ) conducting the output signal (Vout) of the 3-stage amplifier ( 1 A, 1 B or  1 C). A slew rate and settling time improvement circuit ( 40 / 40 A) includes an input coupled to the input signal (Vin) and an output ( 41 ), and also includes first circuitry (MN 1 , 2 ) coupled to the input signal (Vin) for producing a slew detection current (Idetect) when the magnitude of the input signal (Vin) exceeds a predetermined level. The slew rate and settling time improvement circuit ( 40 / 40 A) includes second circuitry (MP 0 ,MP 2 ,MP 4 ,MN 3 ,MP 5 ,MN 5 ) for converting the slew detection current (Idetect) to a control signal ( 41 ) on the output ( 41 ) of the slew rate and settling time improvement circuit ( 40 / 40 A), and also includes a first switch (MN 0 ) controlled by the control signal ( 41 ) coupled to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage ( 2 ) during slewing of the operational amplifier ( 1 B, 1 D). 
         [0019]    In a described embodiment, the 3-stage amplifier includes a feed-forward amplifier stage ( 5 ) having an input coupled to the input signal (Vin) and an output coupled to the input of the third amplifier stage ( 4 ). The first ( 2 ), second ( 3 ) and third ( 3 ) amplifier stages and the feed-forward stage ( 5 ) are operational transconductance amplifiers. 
         [0020]    In one embodiment, a input chopper circuit ( 9 ) couples the input signal (Vin) to the input of the first amplifier stage ( 3 ) and an output chopper circuit ( 10 ) is coupled between the output of the first amplifier stage ( 2 ) and the input of the second amplifier stage ( 3 ). A notch filter ( 15 ) couples an output of the output chopper circuit ( 10 ) to the input of the second amplifier stage ( 3 ). 
         [0021]    In a described embodiment, the first circuitry (MN 1 , 2 ) includes a first transistor (MN 1 ) having a gate coupled to the first input conductor ( 7 A) and a source coupled to the second input conductor ( 7 B) and a second transistor (MN 2 )) having a gate coupled to the second input conductor ( 7 B) and a source coupled to the first input conductor ( 7 A), drains of the first (MN 1 ) and second (MN 2 ) transistors being coupled to a first conductor ( 30 ) to cause the slew detection current (Idetect) to flow in the first conductor ( 30 ) if the magnitude of the input signal (Vin) exceeds the predetermined level. A current mirror (MP 0 ,MP 2 ) has an input ( 30 ) connected to receive the slew detection current (Idetect) and an output ( 31 ) coupled to a resistor (R) and an input of a first inverter (MP 4 ,MN 3 ) which produces a signal ( 32 ) representative of the slew current detection current (Idetect). The first inverter has an output ( 32 ) coupled to an input of a second inverter (MP 5 ,MN 5 ), an output of the second inverter (MP 5 ,MN 5 ) conducting the control signal ( 41 ). 
         [0022]    In one embodiment, a second switch (MN 4 ) is also controlled by the control signal ( 41 ). The first switch (MN 0 ) prevents signal charge from building up on integrate and transfer capacitors (C 5 ,C 6  ( FIG. 3 )) associated with an input of the notch filter ( 15 ) during slewing of the operational amplifier ( 1 D), and the second switch (MN 4 ) prevents signal charge from building up on an additional capacitor (C 4 ) associated with an output of the notch filter ( 15 ) during slewing of the operational amplifier ( 1 D). 
         [0023]    In one embodiment, the invention provides a method of amplifying an input signal (Vin) to produce an output signal (Vout), including providing a 3-stage amplifier ( 1 A, 1 B, or  1 C) having first ( 7 A) and second ( 7 B) input conductors conducting a differential input signal (Vin) and an output ( 25 ) conducting the output signal (Vout), the 3-stage amplifier including a first amplifier stage ( 2 ) having an input coupled to the input signal (Vin), a second amplifier stage ( 3 ) having an input coupled to an output of the first amplifier stage ( 2 ), and a third amplifier stage ( 4 ) having an input coupled to an output of the second amplifier stage ( 3 ) and an output conducting the output signal (Vout). A slew detection current (Idetect) is produced when the magnitude of the input signal (Vin) exceeds a predetermined level. The method includes converting the slew detection current (Idetect) to a control signal ( 41 ) and short-circuiting conductors used in coupling the output of the first amplifier stage ( 2 ) to the input of the second amplifier stage ( 3 ) by means of a switch (MN 0 ) controlled by the control signal ( 41 ) to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage ( 2 ) during slewing of the 3-stage amplifier ( 1 A, 1 B or  1 C). In one embodiment, the method includes providing a feed-forward amplifier stage ( 5 ) having an input coupled to the input signal (Vin) and an output coupled to the input of the third amplifier stage ( 4 ) and coupling the input signal (Vin) to the input of the first amplifier stage ( 2 ) by means of an input chopper circuit ( 9 ) and coupling the output of the first amplifier stage ( 2 ) to the input of the second amplifier stage ( 3 ) by means of an output chopper circuit ( 10 ). 
         [0024]    In one embodiment, the method includes coupling an output of the output chopper circuit ( 10 ) to the input of the second amplifier stage ( 3 ) by means of a notch filter ( 15 ). In the described embodiment, the method includes coupling a gate of a first transistor (MN 1 ) to a first input conductor ( 7 A) of the 3-stage amplifier, coupling a source of the first transistor (MN 1 ) to a second input conductor ( 7 B) of the 3-stage amplifier, coupling a gate of a second transistor (MN 2 ) to the second input conductor ( 7 B) of the 3-stage amplifier, coupling a source of the second transistor (MN 2 ) to the first input conductor ( 7 A) of the 3-stage amplifier the first circuitry (MN 1 , 2 ), and coupling drains of the first and second transistors together to cause the slew detection current (Idetect) to flow in a conductor ( 30 ) coupled to the drains of the first and second transistors. 
         [0025]    In one embodiment, the invention provides an operational amplifier for amplifying an input signal (Vin) to produce an output signal (Vout), including a 3-stage amplifier ( 1 A, 1 B, or  1 C) having first ( 7 A) and second ( 7 B) input conductors conducting a differential input signal (Vin) and an output ( 25 ) conducting the output signal (Vout). The 3-stage amplifier includes a first amplifier stage ( 2 ) having an input coupled to the input signal (Vin), a second amplifier stage ( 3 ) having an input coupled to an output of the first amplifier stage ( 2 ), and a third amplifier stage ( 4 ) having an input coupled to an output of the second amplifier stage ( 3 ) and an output conducting the output signal (Vout). The operational amplifier includes means (MN 1 ,MN 2 , 30 ) for producing a slew detection current (Idetect) when the magnitude of the input signal (Vin) exceeds a predetermined level, means (MP 0 ,MP 2 ,R) for converting the slew detection current (Idetect) to a control signal ( 41 ), and means (MN 0 ) for short-circuiting conductors used in coupling the output of the first amplifier stage ( 2 ) to the input of the second amplifier stage ( 3 ) by means of a switch (MN 0 ) controlled by the control signal ( 41 ) to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage ( 2 ) during slewing of the 3-stage amplifier ( 1 A, 1 B or  1 C). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]      FIG. 1  is block diagram of a prior art 3-stage operational amplifier with multi-path nested Miller compensation. 
           [0027]      FIG. 2  is a block diagram of a prior art 3-stage chopper-stabilized operational amplifier. 
           [0028]      FIG. 3  is a detailed block diagram and timing diagram for a prior art chopper-stabilized 3-stage operational amplifier including a switched capacitor notch filter with synchronous integration. 
           [0029]      FIG. 4  is a detailed schematic diagram of the 3-stage chopper-stabilized amplifier of  FIG. 3  further including slew rate and settling time improvement circuitry in accordance with the present invention. 
           [0030]      FIG. 5  is a detailed schematic diagram of a 3-stage amplifier without chopper stabilization or notch filtering including slew rate and settling time improvement circuitry of the present invention. 
           [0031]      FIGS. 6-8  are diagrams of 3-stage amplifier output waveforms that are useful in explaining the amount of the slew rate and settling time improvement and settling time improvement resulting from use of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0032]    Referring to  FIG. 4 , operational amplifier  1 D includes a three-stage chopper-stabilized, notch-filtered operational amplifier  1 C that can be identical to operational amplifier  1 C of Prior Art  FIG. 3 . In accordance with the present invention, operational amplifier numeral  1 D also includes a “slew rate and settling time improvement circuit”  40 . 
         [0033]    First, a detailed explanation of prior art operational amplifier  1 C as shown in  FIG. 3  and its slow slew settling problems is set forth because this information will be helpful in understanding the operation and benefits of slew rate and settling time improvement circuit  40 . 
         [0034]    Operational amplifier  1 C includes (−) input conductor  7 A and (+) input conductor  7 B by means of which input signal Vin is applied to input chopping circuitry  9  (also referred to as “chopper  9 ”). Chopping circuitry  9  includes switches  9 - 1  and  9 - 2  connected to (−) input conductor  7 A and switches  9 - 3  and  9 - 4  connected to (+) input conductor  7 B. As shown in Prior Art  FIG. 3 , switches  9 - 1  and  9 - 3  are connected by conductor  12 A to the (+) input of operational transconductance amplifier  2 , and switches  9 - 2  and  9 - 4  are connected by conductor  12 B to the (−) input of operational transconductance amplifier  2 . Output conductors  13 A and  13 B of operational transconductance amplifier  2  are connected to output chopping circuitry  10 , which includes switches  10 - 1  and  10 - 2  connected to conductor  13 A and switches  10 - 3  and  10 - 4  connected to conductor  13 B. Chopper switches  10 - 1  and  10 - 3  are connected to conductor  14 A, and chopper switches  10 - 2  and  10 - 4  are connected to conductor  14 B. The chopped output of operational transconductance amplifier  2  produced between conductors  14 A and  14 B is applied to the differential inputs of a switched capacitor notch filter  15 . Conductor  14 B is also connected to one terminal of a compensation capacitor C 3   b,  the other terminal of which is connected to ground. Conductor  14 A also is connected to one terminal of a compensation capacitor C 2   b,  the other terminal of which is connected to Vout conductor  25 . The output of notch filter  15  is connected to the input of operational transconductance amplifier  3 . 
         [0035]    Switched capacitor notch filter  15  (which is a low pass filter with notches at the chopping frequency fs and its harmonics) includes switch  16 A connected between conductors  14 A and  17 , switch  16 B connected between conductors  14 B and  18 , switch  16 C connected between conductors  14 A and  19 , and switch  16 D connected between conductors  14 B and  20 . An “integrate and transfer” capacitor C 5  is connected between conductors  17  and  18 , and another “integrate and transfer” capacitor C 6  is connected between conductors  19  and  20 . Switched capacitor notch filter  15  also includes switch  21 A connected between conductors  17  and  22 A, switch  21 B connected between conductors  19  and  22 A, switch  21 C connected between conductors  18  and  22 B, and switch  21 D connected between conductors  20  and  22 B. Capacitor C 4  ( FIG. 3 ) of notch filter  15  is connected between output conductors  22 A and  22 B of notch filter  15 . The (+) input conductor  7 B is connected to the (−) input of operational transconductance amplifier  5 , the (+) input of which is connected to the (−) input conductor  7 A of operational amplifier  1 C. 
         [0036]    Capacitor C 2   a  provides feedback from Vout to the input of transconductance operational amplifier  3  and capacitor C 4  and capacitor C 2   a  perform a capacitive dividing function to determine how much of the Vout signal is getting fed back. Thus, capacitor C 4 , in addition to performing a charge redistribution function, also provides further low-pass filtering and contributes to local circuit stability. 
         [0037]    The output of feed-forward operational transconductance amplifier  5 , as shown in  FIG. 4  rather than Prior Art  FIG. 3 , is connected by conductors  27 A and  27 B to a first (−) input and a first (+) input, respectively, of operational transconductance amplifier  4 . Operational transconductance amplifier  4  alternatively can be an ordinary operational amplifier. (Capacitor C 4  might be optional in some cases, but as indicated above it has been found to provide somewhat improved charge transfer, somewhat improved filtering and ripple noise reduction, and/or somewhat improved frequency compensation.) The transconductances of operational transconductance amplifiers  2  and  3 , operational amplifier (or operational transconductance amplifier)  4 , and operational transconductance amplifier  5  are gm 1 , gm 2 , gm 3 , and gm 4 , respectively. 
         [0038]    Notch filter  15  thus includes two parallel signal paths, each with switches operating at the same frequency fs as the chopping signals Phase  1  and Phase  2  shown in Prior Art  FIG. 3  but with a ¼ period delay. The ¼ period delays allow integrating of the amplified signal and the offset of input operational transconductance amplifier  2  in the half cycle of the chopping frequency. (The ¼ period of delay allows capacitors C 5  and C 6  to integrate the signal charge during half of Phase  1  and half of Phase  2 , because when Phase  3  is high and Phase  1  is high, Phase  2  is low for ¼ of the period and then for the next quarter cycle Phase  1  is low and Phase  2  is high. For a DC signal, for example an offset voltage component due to switching, the offset voltage component does not change polarity because integration is in the positive direction during a quarter of a cycle and in the negative direction during the next quarter of a cycle. Therefore the ripple errors are canceled.) However, it should be noted that the switching frequency of notch filter  15  can be different than the chopping frequency fs. For example, the switching frequency of notch filter  15  can be one half of the chopping frequency fs, with no delay, in which case the amplified signal and the offset and ripple components therein are integrated over an entire chopping frequency cycle. 
         [0039]    The (+) and (−) inputs of notch filter  15  are connected to conductors  14 A and  14 B, respectively. Notch filter output conductor  22 A is connected to the (+) input of operational transconductance amplifier  3  and to one terminal of compensation capacitor C 3   a,  the other terminal of which is connected to ground. Notch filter output conductor  22 B is connected to the (−) input of operational transconductance amplifier  3  and to one terminal of compensation capacitor C 2   a,  the other terminal of which is connected to Vout conductor  25 . The (+) and (−) outputs of operational transconductance amplifier  3  are connected by conductors  23 A and  23 B to a second (−) input and a second (+) input, respectively, of operational transconductance amplifier or operational amplifier  4  (hereinafter referred to simply as operational amplifier  4 ), the output of which is connected to Vout conductor  25 . 
         [0040]    Note that in Prior Art  FIG. 3  the outputs of operational transconductance amplifiers  3  and  5  are, for simplicity, illustrated as being single-ended outputs, whereas in  FIG. 4  they are shown as differential outputs which typically would be used. The “front end” circuitry of transconductance amplifier gm 3  preferably includes a conventional differential folded-cascode stage. The differential output of feed-forward operational transconductance amplifier  5  typically is produced by a pair of PMOS transistors and is coupled to a pair of resistors in a lower voltage section of the folded-cascode stage. The differential output signal of operational transconductance amplifier  3  typically is produced between conductors  23 A and  23 B which are connected, respectively, to each resistor of a pair of resistors in a higher voltage section of the folded-cascode stage of operational transconductance amplifier and  4 . 
         [0041]    The timing diagram shown along with operational amplifier  1 C in Prior Art  FIG. 3  illustrates four synchronized clock signals Phase 1 , Phase 2 , Phase 3 , and Phase 4  which can be used to control the various chopping switches and filter switches in chopper circuits  9  and  10  and notch filter  15  in both  FIGS. 3 and 4 . Phase 1  controls chopping switches  9 - 1 ,  9 - 4 ,  10 - 1 , and  10 - 4 , and Phase 2  controls chopping switches  9 - 2 ,  9 - 3 ,  10 - 2 , and  10 - 3 . Phase 3  controls notch filter switches  16 A,  16 B,  21 B, and  21 D, and Phase 4  controls switches  16 C,  16 D,  21 A and  21 C. The Phase 3  and Phase 4  notch filter clocking signals operate at the same frequency fs as the chopping signals Phase 1  and Phase 2  but are 90 degrees out of phase with them. Alternatively, the Phase 3  and Phase 4  notch filter clocking signals could operate at half the chopping frequency, i.e. at fs/ 2 , as the chopping signals Phase  1  and Phase 2  but in phase with them. 
         [0042]    Operational amplifier  1 D has two signal paths, including a three-stage high gain signal path through operational transconductance amplifiers  2 ,  3  and  4  and a two-stage wideband width signal path through operational transconductance amplifiers  5  and  4 . 
         [0043]    Input conductors  14 A and  14 B of notch filter  15  conduct output currents from transconductance stage  2 , and the net current through conductors  14 A and  14 B is integrated during one of Phase 1  and Phase 2  onto integrate and transfer capacitor C 5 , and during the other phase the net current is integrated onto the other integrate and transfer capacitor C 6 . This results in all of the signal charge being available on integrate and transfer capacitors CS and C 6 , and all of the signal charge is available for redistribution to the next stage, i.e. to the capacitance coupled to notch filter output conductors  22 A and  22 B. This is advantageous because any loss of signal charge may result in loss of signal information and cause signal distortion. 
         [0044]    For example, the net input current into notch filter input conductors  14 A and  14 B is integrated onto integrate and transfer capacitor C 5  during Phase 1 , and then during Phase 2  the net notch filter input current is integrated onto integrate and transfer capacitor C 6  while the charge on integrate and transfer capacitor C 5  is simultaneously redistributed onto capacitance (including capacitor C 4 ) coupled to notch filter output conductors  22 A and  22 B. With integrate and transfer capacitor C 5  coupled to capacitor C 4 , a redistribution (rather than a complete voltage transfer) of the integrated signal charge is achieved, and over multiple cycles the capacitance (including capacitor C 4 ) coupled to notch filter output conductors  22 A and  22 B is charged to the correct signal voltage. 
         [0045]    In the operation of notch filter  15 , one signal path integrates the amplified and chopped signal (including the ripple current resulting from the offset voltage) from operational transconductance amplifier  2  on the integrate and transfer capacitor C 5  during one half of the notch filter switching cycle. During the same interval the other signal path “transfers” the amplified signal (including the ripple current resulting from the offset voltage) from integrate and transfer capacitor C 6  to operational transconductance amplifier  3 . During the next half cycle of operation of notch filter  15 , the integrate and transfer functions of the two signal paths are reversed. The frequency response of notch filter  15  includes notches at the chopping frequency spectrum values of fs and its harmonics, so the notches suppress the ripple voltages that usually occur in a conventional chopper-stabilized amplifier. 
         [0046]    As previously indicated, chopper-stabilized amplifier  1 C of Prior Art  FIG. 3  has the problem that the averaging function of notch filter  15  treats a large, fast changing signal as an error signal and averages it, and this requires a number of clock cycles for the amplifier output  1 C to reach its final value and thus increases its output settling time during a large signal slewing operation. During the first half of a cycle switches  16 A and  16 B are on, i.e., closed, and then the signal charge corresponding to the value of Vin, is charged into integrate and transfer capacitor C 5 . Then during the next half cycle, switches  16 A and  16 B are off and the charge on capacitor C 5  is transferred to C 4  because switches  21 A and  21 C are closed. In the meantime, switches  16 C and  16 D are closed, so during the second half cycle, the signal charge is charged into integrate and transfer capacitor C 6 . 
         [0047]    During slewing, Vin changes very fast, so during the first half cycle and the second half cycle the values of Vin and hence the corresponding signal input to notch filter  15  charge will be very different in the first and second half-cycles. Therefore the voltage to which C 5  is charged is much different than the voltage to which C 6  is charged. So during one cycle an amount of charge is transferred from capacitor C 5  to capacitor C 4  and during the next cycle a substantially different amount of signal charge is transferred from C 6  to C 4 . Therefore there will be substantially different signal charge redistribution between C 5  and C 4  and between C 6  and C 4 . Since the amount of signal charge changes rapidly and substantially during slewing, several additional cycles are required for the signal charge difference to be redistributed or rebalanced between capacitors C 5  and C 4  and between capacitors C 6  and C 4  before Vout is able to achieve a steady value. 
         [0048]    Slew improvement circuitry  40  is provided in operational amplifier  1 D of  FIG. 4  to solve the foregoing slewing and settling problem by first detecting when operational amplifier  1 D goes into slewing operation and, in response, short-circuiting capacitors C 5 , C 6 , and C 4  in notch filter  15  to prevent charge from being held on them during slewing operation. 
         [0049]    In  FIG. 4 , slew rate and settling time improvement circuitry  40  includes N-channel slew-detecting transistor MN 1  having its gate connected to input conductor  7 A and its source connected to input conductor  7 B. Similarly, N-channel slew-detecting transistor MN 2  has its gate connected to input conductor  7 B and its source connected to input conductor  7 A. The drains of slew-detecting transistors MN 1  and MN 2  are connected to the drain and gate of a P-channel current mirror input transistor MP 0  and the gate of a P-channel current mirror output transistor MP 2 . The sources of current mirror transistors MP 0  and MP 2  are connected to VDD. The drain of current mirror output transistor MP 2  is connected by conductor  31  to one terminal of a resistor R, one terminal of capacitor C, and to the gates of a P-channel transistor MP 4  and a N-channel transistor MN 3 , the drains of which are connected together by conductor  32  and to the gates of a P-channel transistor MP 5  and a N-channel transistor MN 5 . The other terminal of resistor R, the other terminal of capacitor C, and the sources of transistors MN 3  and MN 5  are connected to ground. 
         [0050]    Transistors MP 4  and MN 3  form a CMOS inverter, and transistors MP 5  and MN 5  form another CMOS inverter. The sources of transistors MP 4  and MP 5  are connected to a suitable reference voltage VDC, which for example can be VDD. The drains of transistors MP 5  and MN 5  are connected by conductor  41  to the gates of N-channel switch transistors MN 0  and MN 4 . The source of switch transistor MN 0  is connected by conductor  14 B to the (−) input of notch filter  15  and the drain of switch transistor MN 0  is connected by conductor  14 A to the (+) input of notch filter  15 . Similarly, the source of switch transistor MN 4  is connected by conductor  22 A to the (+) input of notch filter  15  and the drain of switch transistor MN 4  is connected by conductor  22 B to the (−) input of notch filter  15 . 
         [0051]    During slewing there will be a large voltage difference between conductors  7 A and  7 B. When the magnitude of Vin is sufficiently large, i.e. greater than the threshold voltage of transistors MN 1  and MN 2 , one or the other of slew-detecting transistors MN 1  and MN 2  turns on, depending on the polarity of Vin, and the other slew-detecting transistor remains off. If either of slew-detecting transistors MN 1  and MN 2  is turned on, that indicates the beginning of a slewing operation, and a current Idetect flows through current mirror input transistor MP 0  and therefore is mirrored through the current mirror output transistor MP 2  into resistor R. This increases the voltage on resistor R, i.e., the voltage on conductor  31 , and turns off MP 4  and turns on transistor MN 3 . Capacitor C performs the function of slowing down the discharge of the voltage which occurs on conductor  31  when both of transistors MN 1  and MN 2  are off. The inverter formed by transistors MP 4  and MN 3  inverts the voltage signal on conductor  31 . The resulting inverted signal on conductor  32  is inverted again by the inverter formed by transistors MP 5  and MN 5  to produce a control signal on conductor  41  that turns on N-channel switch transistor MN 0 , which then short-circuits conductors  14 A and  14 B. This prevents signal charge from accumulating in integrate and transfer capacitors C 5  and C 6  during slewing. The control signal on conductor  41  also turns on a N-channel switch transistor MN 4 , which short-circuits conductors  22 A and  22 B. 
         [0052]    Thus, inside notch filter  15 , the turning on of switch transistors MN 0  and MN 4  during slewing eliminates any charge on both of integrate and transfer capacitors C 5  and C 6 . This does not cause any problems because no charge is needed on either of capacitors C 5  and C 6  during slewing. 
         [0053]    Since switch MN 0  short-circuits conductors  14 A and  14 B together during the slewing, transconductance operational amplifier  2  does not need to supply any differential charge to the capacitances coupled to conductors  14 A and  14 B. That causes the slew rate or rise time to be somewhat faster. More important, since transconductance operational amplifier  2  does not have to supply differential charges to the capacitances on conductors  14 A and  14 B after it comes out of stewing operation, conductors  14 A and  14 B are still at their common mode voltages and therefore do not need to settle from a differential voltage between them. (This is especially true since during stewing there is a large magnitude of the Vin signal that would otherwise cause transconductance amplifier  2  to attempt to generate a large voltage difference between conductors  14 A and  14 B and accordingly charge up the separate capacitive loads on those two conductors.) The closing of switch MN 0  during slewing therefore substantially reduces the settling time of Vout after slewing. Furthermore, the simultaneous closing of switch MN 4  during slewing (so as to prevent charge from building up on integrate and transfer capacitors C 5  and C 6  during the slewing) results in a substantial reduction of the settling time of Vout immediately after slewing. Similarly, switch MN 4  keeps conductors  22 A and  22 B at their common mode voltage during slewing. 
         [0054]    Since there is no charge on either of capacitors C 5  and C 6  when the operational amplifier  1 D is finished slewing, no time needs to be allowed for the voltage on either of capacitors C 5  and C 6  to settle. The same is true for capacitor C 4 . Therefore no time needs to be allowed for Vout to settle. During normal operation with no slewing and conductor  41  is at a low voltage and switch transistors MN 0  and MN 4  are off, and slew improvement circuit  40  does not affect normal operation of chopper-stabilized notch-filtered operational amplifier  1 C. 
         [0055]    The capacitance of capacitor C in slew rate and settling time improvement circuit  40  is chosen to provide a suitable delay between the time at which current mirror output transistor MP 2  turns off at the end of a slewing value of Vin and the time at which switch transistors MN 0  and MN 4  are turned off by the voltage on conductor  41 . Specifically, capacitor C and resistor R determine how long it takes for the voltage on conductor  31  to discharge. That amount of time determines how much longer switch transistors MN 0  and MN 4  remain turned on after the magnitude of Vin falls below the value required to initiate slewing. 
         [0056]    Thus, as soon as operational amplifier  1 D begins slewing operation, switch transistors MN 0  and MN 4  effectively short-circuit the capacitors C 5 , C 6  and C 4  inside notch filter  15  so that no error signal will build up charge on capacitors C 5  and C 6 . Since there is no charge built up on the capacitors when operational amplifier  1 C of  FIG. 4  comes out of slewing operation, no time is required for the voltage between conductors  23 A and  23 B to settle, and therefore no time is required for Vout to settle either. 
         [0057]    Referring to  FIG. 5 , operational amplifier  1 E includes traditional 3-stage amplifier  1 A of Prior Art  FIG. 1  further including slew rate improvement circuitry  40 A, which is the same as the slew rate improvement circuitry shown in  FIG. 4  except that only a single switch transistor MN 0  is included. The source and drain of switch transistor MN 0  is connected to the (+) and (−) inputs, respectively, of operational transconductance amplifier  3 . Switch transistor MN 0  is turned on during slewing operation of operational amplifier  1 E. This prevents compensation capacitors C 2  and C 3  from being charged up during slewing, and therefore no additional time needs to be provided after the end of slewing in order to allow settling of the voltage difference between the (+) and (−) inputs of operational transconductance amplifier  3 . Consequently, no additional time needs to be allowed for corresponding settling of Vout, either. (Slew rate and settling time improvement circuit  40 A would be connected to prior art chopper-stabilized operational amplifier  1 B of  FIG. 2  in exactly the same manner shown in  FIG. 5 .) 
         [0058]      FIGS. 6 ,  7  and  8  show representations of the simulated performance of three different operational amplifiers including the slew detection in the slew rate and settling time improvement circuitry of the present invention. 
         [0059]    The waveform of  FIG. 6  shows the results for a particular implementation of three-stage chopper-stabilized notch-filtered operational amplifier  1 D of  FIG. 4 . In this case, the Vout waveform in  FIG. 6  shows that for the rising edge of Vout from a low level of 0.5 volts to within 0.1% of a high level of 4.5 volts, the rise time is 0.6 microseconds less than if the slew rate and settling time improvement circuitry  40  is omitted. (The same computer simulation showed an improvement of 0.9 microseconds in the rise time to within 0.01% of the 4.5 volt level and 0.2 microseconds in the rise time to within 0.001% of the 4.5 volt level.) The Vout waveform in  FIG. 6  also shows that for the falling edge of Vout from a low level of 4.5 volts to within 0.1% of a high level of 0.5 volts, the fall time is 1.2 microseconds less than if the slew rate and settling time improvement circuitry  40  is omitted. (The same computer simulation showed an improvement of 1.2 microseconds in the fall time to within 0.01% of the 4.5 volt level and 0.6 microseconds in the fall time to within 0.001% of the 4.5 volt level.). Note that the time required for Vout to settle to within, e.g., 0.1% of the final high value or low value at the end of a rising edge or falling edge of Vout, respectively, may include a few cycles of ringing. 
         [0060]    Similarly, the waveform of  FIG. 7  shows the results for a particular implementation of conventional three-stage chopper-stabilized notch-filtered operational amplifier  1 B (with no notch filtering) of Prior Art  FIG. 2  with and without the slew rate and settling time improvement circuitry  40 . In this case, the Vout waveform in  FIG. 7  shows that for the rising edge of Vout from a low level of 0.5 volts to within 0.1% of a high level of 4.5 volts, the rise time is 0.4 microseconds less than if the slew rate and settling time improvement circuitry  40  is omitted. (The same computer simulation showed an improvement of 0.4 microseconds in the rise time to within 0.01% of the 4.5 volt level and an increase of 0.8 microseconds in the rise time to within 0.001% of the 4.5 volt level.) The Vout waveform in  FIG. 7  also shows that for the falling edge of Vout from a high level of 4.5 volts to within 0.1% of a low level of 0.5 volts, the fall time is 1.2 microseconds less than if the slew rate and settling time improvement circuitry  40  is omitted. (The same computer simulation showed an improvement of 1.0 microseconds in the fall time to within 0.01% of the 4.5 volt level and 0.7 microseconds in the fall time to within 0.001% of the 4.5 volt level.). 
         [0061]    The waveform of  FIG. 8  shows the simulation results (but with the slew rate and settling time improvement circuitry  40  is still optimized for use with a chopper-stabilized, notch-filtered amplifier) for a particular implementation of the traditional three-stage operational amplifier  1 A (no chopper stabilization or notch filtering) of Prior Art  FIG. 1 . In this case, the Vout waveform in  FIG. 8  shows that for the rising edge of Vout from a low level of 0.5 volts to within 0.1% of a high level of 4.5 volts, the rise time is 0.8 microseconds less than if the slew rate and settling time improvement circuitry  40  is omitted. (The same computer simulation showed an improvement of 1.2 microseconds in the rise time to within 0.01% of the 4.5 volt level and 0.4 microseconds in the rise time to within 0.001% of the 4.5 volt level.) The Vout waveform in  FIG. 8  also shows that for the falling edge of Vout from a high level of 4.5 volts to within 0.1% of a low level of 0.5 volts, the fall time is 1.4 microseconds less than if the slew rate and settling time improvement circuitry  40  is omitted. (The same computer simulation showed an improvement of 1.2 microseconds in the fall time to within 0.01% of the 4.5 volt level and 0.1 microseconds in the fall time to within 0.001% of the 4.5 volt level.) Note that foregoing rise times and fall times of Vout on were obtained for simulations of the slew rate and settling time improvement circuitry  40  which was optimized for 3-stage chopper-stabilized notch-filtered operational amplifier  1 D of  FIG. 4 . It should be appreciated that the same slew rate and settling time improvement circuitry  40  can be used with some optimization to achieve the best rise and fall times for various other 3-stage amplifiers without chopping, notch filtering, and/or different inherent slew rates. 
         [0062]    The above described embodiments of the invention provide various three-stage amplifiers with slew rate and settling time improvement circuitry without creating substantial difficulties in design and implementation. Specifically, the present invention allows such a three stage chopper stabilized amplifier to settle faster to its final value after slewing without increasing chopping frequency. Further more, it also improves settling time of a traditional 3-stage amplifier even without chopping technique being used. 
         [0063]    While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. For example, the invention is applicable to multi-stage operational amplifiers having more than 3 stages (not counting feed-forward stages).