Abstract:
The disclosure is a semiconductor memory device cooperated with row repair circuitry by which defective wordlines are substituted with redundant wordlines regardless of locations of cell array blocks, the redundant wordlines being arranged in a specific cell array block. The semiconductor memory device includes a plurality of memory blocks at least one of which includes a plurality of redundant wordlines; a plurality of row repair fuse boxes the number of which is the same with the number of the redundant wordlines, the fuse boxes being divisionally arranged with the same number respective in the memory blocks; and repair means to repair a defective wordline with the redundant wordline, the redundant wordlines corresponding to the row repair fuse boxes each by each.

Description:
[0001]    This application relies for priority upon Korean Patent Application No. 2000-36158, filed on Jun. 28, 2000 and No. 2001-24263, filed on May 4, 2001, the contents of which are herein incorporated by reference in their entirety.  
         FIELD OF THE INVENTION  
         [0002]    The present invention generally relates to a semiconductor memory device having a capacity of redundancy, and more particularly to a semiconductor memory device with row repair circuitry by which defective wordlines are substituted with redundant wordlines regardless of locations of cell array blocks, the redundant wordlines being arranged in a specific cell array block.  
         BACKGROUND OF THE INVENTION  
         [0003]    It is usually occasional that various kinds of defects are generated throughout a manufacturing process for a semiconductor memory device (e.g., a DRAM), causing the memory device to be in a malfunction and reducing a yield thereof. Even one defect over a cell array in the semiconductor memory device may easily turn it out of normal operations such as data read-out and write-in. For this reason, it is recommended to substitute defective memory cells with additionally prepared memory cells (i.e., redundant or spare memory cells) in correspondence with their addresses, i.e., “redundancy”, increasing a product yield and reliability of the memory device. When one or more defective memory cells are detected by a test operation, the defective memory cells are substituted with the redundant memory cells that are arranged in the unit of row or column in a memory cell array of the memory device, without abandoning the memory device even though it has the defective cells.  
           [0004]    In a conventional 64 M (64 megabits; M=2 20 ) DRAM constructed of four memory banks, each bank has the storage capacity of 16 M with being formed of a plurality of memory blocks, as shown in FIG. 1, and peripheral block PBL in which input/output pads are arranged includes input/output buffers and multiplexers assigned to the input/output pads. The peripheral block PBL in which pads for address and control signals are positioned includes control signal buffers and address buffers being coupled to their corresponding pads, and further a control logic unit and a command state machine. Column control logic blocks CCL 0 ˜CCL 3  each assigned to their corresponding memory banks have Y-decoders (or column decoders), drivers and data bus sense amplifiers to write data in memory cells or to read data from memory cells. Row control logic blocks RCL 0 ˜RCL 3  each assigned to their corresponding memory banks include X-decoders (or row decoders) and logic circuits for driving wordlines.  
           [0005]    And, each of the memory blocks has a predetermined number of redundant wordlines being assigned thereto exclusively. According to the fashion of redundancy in this manner, since defective wordlines yet repairable is limited by the predetermined number of redundant wordlines, the device shown in FIG. 1 may come up with a limitation to enhance the efficiency of repairing the defective wordlines (or memory cells). For instance, when the number of defective memory cells is greater than that of redundant wordlines in the memory bank MB 1 , it is impossible to repair the defective wordlines in excess of the capacity of the redundant wordlines therein.  
         SUMMARY OF THE INVENTION  
         [0006]    It is, therefore, an object of the present invention to provide a semiconductor memory device capable of enhancing the efficiency of repairing defective memory cells.  
           [0007]    It is another object of the present invention to provide a semiconductor memory device capable of repairing defective wordlines without positional restriction of defective wordlines.  
           [0008]    In order to attain the above objects, according to an aspect of the present invention, there is provided a semiconductor memory device having a function of row repair, including a plurality of memory blocks where at least one of them includes a predetermined number of redundant wordlines, the predetermined number of row repair fuse boxes being divisionally arranged to be the same with the number of the memory blocks, and repair means to replace defective wordlines with the redundant wordlines, each redundant wordline corresponds to one of the row repair fuse boxes respectively.  
           [0009]    The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    A more complete appreciation of the present invention, and many of the attendant advantages thereof, will become readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:  
         [0011]    [0011]FIG. 1 is a block diagram illustrating architecture of a general 64 M synchronous DRAM;  
         [0012]    [0012]FIG. 2 is a block diagram showing a disposition of row repair fuse boxes in a memory bank according to a preferred embodiment of the invention;  
         [0013]    [0013]FIG. 3 is a schematic block diagram of a semiconductor memory device including row repair fuse boxes and the peripheral thereof, according to the preferred embodiment of the invention;  
         [0014]    [0014]FIG. 4 is a circuit diagram of the row repair fuse box shown in FIG. 3;  
         [0015]    [0015]FIG. 5 is a circuit diagram of a fuse summation circuit shown in FIG. 3;  
         [0016]    [0016]FIG. 6 is a circuit diagram of a redundant block selection circuit shown in FIG. 3;  
         [0017]    [0017]FIG. 7 is a circuit diagram of a normal block selection circuit shown in FIG. 3;  
         [0018]    [0018]FIG. 8 is a circuit diagram of a sub wordline driver selection circuit shown in FIG. 3;  
         [0019]    [0019]FIG. 9 is a circuit diagram of a sub wordline driver for the redundant block;  
         [0020]    [0020]FIG. 10 is a circuit diagram of a sub wordline driver for the normal block;  
         [0021]    [0021]FIG. 11 is a circuit diagram of a redundant main wordline enable signal generator;  
         [0022]    [0022]FIG. 12 is a circuit diagram of a normal main wordline enable generator; and  
         [0023]    [0023]FIG. 13 is a circuit diagram of a redundant main wordline driver. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0024]    It should be understood that the description of the preferred embodiment is merely illustrative and it should not be taken in a limiting sense. In the following detailed description, several specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details.  
         [0025]    Referring to FIG. 2, a memory bank (e.g., MB 1 ) is constructed of eight memory blocks UB 0 ˜UB 7  each having the capacity of 2 M, and sixteen row repair fuse boxes RF 00 ˜RF 15 . Each memory block is constituted of 512 rows and 4 K (K=2 10 =1024), or, in other words, 512 wordlines and 4 K bitlines. The address for designating the eight memory blocks is composed of three address bits axB, axA, and ax 9  (three bits can select eight blocks; 2 3 =8). The external address bit axB is the most significant bit (MSB).  
         [0026]    Each memory block has a unit of the row control logic block, and the unit includes two row repair fuse boxes. That is, two row repair fuse boxes are allocated into each memory block. And, redundant wordlines RWLs are disposed in the first memory block UBO and the eighth memory block UB 7 , each by eight. Thus, two groups of the memory blocks are differentiated by the MSB (i.e., axB) “0” and “1” of the block address, UB 0 ˜UB 3  and UB 4 ˜UB 7 , and each group is assigned to eight redundant wordlines arranged in the UB 0  or UB 7 , respectively. As each redundant wordline RWL corresponds to one of the fuse boxes respectively, the row repair fuse boxes RF 00 ˜RF 15  can drive the sixteen redundant wordlines RWLs at a maximum of sixteen normal wordlines that are defective in each bank. If a specific wordline is detected as being defective, the first one of the redundant wordlines located at the topside become conductive in a repair operation.  
         [0027]    While the aforementioned redundancy constitution which is flexible with the unit of the 2 M memory block, is to shorten an enable time of the wordlines, it is possible to modify the elastic range in constructing the redundancy architecture such as with the unit of 8 M memory block if there is no considerable burden of the wordline enable time. Referring to  2 , the eight redundant wordlines arranged in the memory block UB 0  corresponding to the axB (i.e., MSB “0”) are driven into the repair operation by means of the row repair fuse boxes RF 00 ˜RF 07  disposed in UB 0 ˜UB 3 . And, other eight redundant wordlines in UB 7  corresponding to the axB (i.e., MSB “1”) are utilized in the repair operation by means of the row repair fuse boxes RF 08 ˜RF 15 .  
         [0028]    [0028]FIG. 3 shows a construction of row repair circuitry embodied in a semiconductor memory device, only including eight row repair fuse boxes RF 00 ˜RF 07  and four memory blocks UB 0 ˜UB 3 , corresponding to the block address bit axB “0”. It can be understood that the other half corresponding to the axB “1” has the same constitution with that shown in FIG. 3, in consideration with that a unit of the flexible scope of redundancy practiced in the invention is eight redundant wordlines and fuse boxes for four 2 M memory blocks as aforementioned. Hereinafter, the overall constitution of FIG. 3 is referred to as a repair unit.  
         [0029]    The repair unit consists of four memory blocks UB 0 ˜UB 3 , block  100  of the row repair fuse boxes RF 00 ˜RF 07 , fuse summation circuit  200 , block selection circuits group  300 , sub wordline driver selection circuit  400 , sub wordline drivers group  500 , wordline enable signal generators group  600 , and main wordline drivers group  700 .  
         [0030]    The four memory blocks include the first memory block UBO in which the eight redundant wordlines are arranged. The row repair fuse boxes RF 00 ˜RF 07  in the block  100  receive row addresses BAX 01 &lt;0:3&gt;, BAX 23 &lt;0:3&gt;, BAX 45 &lt;0:3&gt;, BAX 67 &lt;0:3&gt;, and BAX 8 &lt;0:1&gt;, and block addresses BAX 9 &lt;0:1&gt; and BAXAB&lt;0:3&gt;, and then generate fuse decoding signals NRDb&lt;0:7&gt;. The row and block addresses are generated from a pre-decoder (not shown). The fuse summation circuit  200  combines the fuse decoding signals NRDb&lt;0:7&gt; with logic gates, and then generates summation signals NRDb 4 &lt;0:1&gt;, a repair information signal pair XSUM/XSUMb (XSUMb is a complementary signal of XSUM). XSUMb and XSUM will be referred to as the first and second repair information signals, respectively. The block selection circuits group  300  includes redundant block selection circuit  310  and three normal block selection circuits  320   s , all those receiving the block selection addresses BAX 9 &lt;0:1&gt; and BAXAB&lt;0:3&gt;, and block selection enable signal BSENb, and then generating block selection signals BSb&lt;0:3&gt;. The sub wordline driver selection circuit  400  inputs the block selection signal BSb&lt;0:3&gt; and then generates sub wordline driver selection signal PX_SEL&lt;0:1&gt;.  
         [0031]    The sub wordline drivers group  500  includes four redundant sub wordline drivers  510   s  and  520   s , and four normal sub wordline drivers  530   s  and  540   s . The selection signal PX_SEL&lt;0&gt; is applied to the redundant sub wordline drivers  510   s  and  520   s  in common, while PX_SEL&lt;1&gt; is applied to the normal sub wordline drivers  530   s  and  540   s . While the pre-decoded row address signals BAX 01 &lt;0:3&gt; are applied to all of the drivers, the first repair information signal XSUMb and the fuse decoding signals NRDb&lt;0:7&gt; are applied to the redundant sub wordline drivers  310   s  and  320   s . Then, the eight sub wordline drivers generate eight sub wordline drive signals PXb&lt;0:7&gt; to activate their corresponding sub wordlines.  
         [0032]    Wordline enable signal generators group  600  includes redundant wordline enable signal generator  610  and three normal wordline enable signal generators  620   s  which, respectively, receives block selection signals BSb&lt;0:3&gt; and then generates normal main wordline enable signals BS&lt;0:3&gt;. The redundant wordline enable signal generator  610  inputs the first repair information signal XSUMb and further generates redundant main wordline enable signal RMWLEN. The redundant main wordline drivers group  700  includes two redundant main wordline drivers  710  and  720  which generate redundant main wordline drive signals RMWL&lt;0:1&gt;, respectively, in response to driver precharge signal WLC_XDEC and the redundant main wordline enable signal RMWLEN in common, and the summation signals NRb 4 &lt;0:1&gt;. The eight redundant wordlines RWLs will be conductive by decoding the sub wordline drive signals PXb&lt;0:7&gt; and the redundant main wordline drive signals RMWL&lt;0:1&gt;.  
         [0033]    All of the fuse boxes have the same constructions. The row repair fuse box (e.g., any one of RF 00 ˜RF 07 ), referring to FIG. 4, is formed of fuse decoder  120  generating fuse decoding signal NRDb&lt;i&gt; (i is one of 0˜7) in response to a state at sensing node SN 1  that is dependent upon parallel fusing loops responding to the predecoded row and block addresses, BAX 01 &lt;0:3&gt;˜BAX 8 &lt;0:1&gt;, BAX 9 &lt;0:1&gt;, and BAXAB&lt;0:3&gt;, PMOS transistor P 0  connected between power supply voltage Vcc and the sensing node SN 1 , inverter I 0  reversing a logic state of the sensing node SN 1 , and PMOS transistor P 1  connected between Vcc and SN 1 . Gates of the PMOS transistors, P 0  and P 1 , are coupled to precharge signal WLCb and output of the inverter I 0 . The PMOS transistor P 1  and the inverter I 0  constitutes a latch circuit to hold a current signal level of the fuse decoding signal NRDb&lt;i&gt; before new address information relevant to defective wordlines is introduced thereto.  
         [0034]    The fuse decoder  120  is constructed of a plurality of fuses F 0 ˜F 23  whose ends are connected to the sensing node SN 1 , and NMOS transistors N 0 ˜N 23  connected between other ends of the fuses F 0 ˜F 23  and substrate voltage Vss (or ground voltage). Gates of the NMOS transistors N 0 ˜N 15  are coupled to the row address signals BAX 01 &lt;0:3&gt;, BAX 23 &lt;0:3&gt;, BAX 45 &lt;0:3&gt;, and BAX 67 &lt;0:3&gt;, by four in this order. Gates of the NMOS transistors N 16  and N 17  are coupled to row address signals BAX 8 &lt;0:1&gt;, respectively. Gates of the NMOS transistors N 18  and N 19  are coupled to block address signals BAX 9 &lt;0:1&gt;, and gates of the NMOS transistors N 20 ˜N 23  are coupled to block address signals BAXAB&lt;0:3&gt;, respectively.  
         [0035]    The precharge signal WLCb is a negative logic signal that is active with a low level to charge SN 1  by turning the PMOS transistor P 0  on and inactive with a high level. The fuse decoding signal NRDb&lt;i&gt; goes to a low level when a repair operation needs to be carried out, while maintains a high level (i.e., a precharge level at SN 1 ) when there is no occurrence of repairing. The pre-decoded row address signals BAX 01 &lt;0:3&gt;˜BAX 8 &lt;0:1&gt; are internal address signals made by a pre-decoder that generates the signals from external address signals which are supplied into the semiconductor device in response to an activation of a row address strobe signal.  
         [0036]    In an operation of the row repair fuse box shown in FIG. 4, first, the fuses F 0 ˜F 23  are prepared to be adaptable to the row address for defective wordlines after a test operation that detects which addresses are assigned to memory cells having read/write fails. When the precharge signal WLCb is set on a low level, the PMOS transistor P 0  is turned on and thereby the sensing node SN 1  is charged up to a high voltage level according to the power supply voltage Vcc. The PMOS transistor P 1  and the inverter I 0  hold the sensing node SN 1  at the precharge voltage of a high level. In a row active state, as WLCb maintains a high level, the PMOS transistor P 0  is turned off. And then, the sensing node maintains the precharge level when the row address signals BAX 01 &lt;0:3&gt;˜BAX 8 &lt;0:1&gt; and the block address signals BAX 9 &lt;0:1&gt; and BAXAB&lt;0:3&gt; agree to those of a defective wordline. On the contrary, the row and block address signals different from the defective address signals make the sensing node SN 1  fall down to a low level, and thereby the fuse decoding signal NRDb is established to a high level.  
         [0037]    The fuse summation circuit  200 , referring to FIG. 5, for combining the fuse decoding signals NRDb&lt;0:7&gt; into logic loops to make the summation signals NRDb 4 &lt;0:1&gt; and the repair information signals XSUM/XSUMb, is constructed of NAND gate NDO receiving the fuse decoding signals NRDb&lt;0:1&gt; generated respectively from the fuse boxes RF 00  and RF 01 , NAND gate ND 1  receiving NRDb&lt;2:3&gt;, NAND gate ND 2  receiving NRDb&lt;4:5&gt;, NAND gate ND 3  receiving NRDb&lt;6:7&gt;, NOR gate NRO receiving output signal XFOUT_SUM 0  from the NAND gate NDO and output signal XFOUT_SUM 1  from the NAND gate ND 1  and then generating the summation signal NRDb 4 &lt;0&gt;, NOR gate NR 1  receiving output signal XFOUT_SUM 2  from the NAND gate ND 2  and output signal XFOUT_SUM 3  from the NAND gate ND 3  and then generating the summation signal NRDb 4 &lt;1&gt;, NAND gate ND 4  receiving output signals from the NOR gates NR 0  and NR 1  and then generating the second repair information signal XSUM, and inverter I 1  converting output signal of the NAND gate ND 4  into the first repair information signal XSUMb.  
         [0038]    The summation signal NRDb 4 &lt;0&gt; is made from logic combination with the four fuse decoding signals NRDb&lt;0:3&gt; each generated from the four row repair fuse boxes RF 00 ˜RF 03 , and the summation signal NRDb 4 &lt;1&gt; is made from logic combination with the four fuse decoding signals NRDb&lt;4:7&gt; each generated from the four row repair fuse boxes RF 04 ˜RF 07 . Therefore, if any of the fuse decoding signals NRDb&lt;0:7&gt; is a low level that informs of repairing, the summation signals NRDb 4 &lt;0:1&gt; are changed to the low levels. While, if there is no repair when all of the fuses decoding signals are at the high levels, the summation signals are lain on the high levels. The second repair information signal XSUM has contrary phases from those of the first repair information signal XSUMb.  
         [0039]    Referring to FIG. 6, the redundant block selection circuit  310 , is included in the block  300  together with the three normal block selection circuits  320   s , and it determines whether to receive or not the block address signals BAX 9 i and BAXABi from monitoring the summation result with the fuse decoding signals NRDb&lt;i&gt;.  
         [0040]    The block selection operation in this embodiment is to select an alternative one of the eight memory blocks belonging to a memory bank by means of the predecoded block address signals BAX 9 i and BAXABi which are introduced in the memory device in response to the row activation where a row address strobe signal is enabled. The present embodiment employs the flexible row repair operation in which the memory block including the redundant wordlines is forced to be activated whenever there is a need of repair.  
         [0041]    The redundant block selection circuit  310  shown in FIG. 6 activates a memory block corresponding to the block address signals BAX 9 i/BAXABi by using the first repair information signal XSUMb of a high level when there is no need of repair after monitoring the summation result with the fuse decoding signal NRDb&lt;i&gt;. On the other hand, if the the first repair information signal XSUMb becomes a low level while the second repair information signal XSUM is at a high level when there is need of repair, responding to a transition of the fuse decoding signal NRDb&lt;i&gt;, the second repair information signal XSUM makes the selection circuit  310  not be affected from the block address signals BAX 9 i/BAXABi and then activates the memory block (e.g., UB 0 ) including the redundant wordlines.  
         [0042]    The redundant block selection circuit  310 , as shown in FIG. 6, is constructed of inverter I 2  converting the block selection enable signal BSENb into its reverse signal, PMOS transistor P 2  connected between Vcc and node NODI and having its gate coupled to an output signal of the inverter I 1 , NMOS transistor N 24  connected between the nodes NOD 1  and node NOD 2  and having its gate coupled to the output of the inverter I 1 , NMOS transistor N 25  connected between the node NOD 2  and Vss and having its gate coupled to the first repair information signal XSUMb, NAND gate ND 5  receiving the block address signals BAX 9 i/BAXABi, inverter I 3  converting an output signal of the NAND gate ND 5  into its reverse signal, NMOS transistor N 26  connected between the NMOS transistor N 25  and Vss and having its gate coupled to the output signal of the inverter I 3 , NMOS transistor N 27  connected between the node NOD 2  and Vss and a gate coupled to the second repair information signal XSUM, latch circuit L 1  formed of two inverters  14  and  15  and connected between the node NOD 1  and node NOD 3 , and inverter I 6  converting an output signal of the latch circuit LI into redundant block selection signal BSb&lt;0&gt;.  
         [0043]    With respect to an operation in the redundant block selection circuit  310 , the block selection enable signal BSENb is set up to a low level when a corresponding memory bank is conductive, while maintaining a high level to precharge the block selection signal BSb&lt;0&gt; during a precharge mode.  
         [0044]    In a normal active mode, the block selection enable signal BSENb of a low level turns the NMOS transistor N 24  on. At this time, the first repair information signal XSUMb and the block address signals BAX 9 i/BAXABi go to high levels, so that the NMOS transistors N 25  and N 26  are turned on and thereby the redundant block selection signal BSb&lt;0&gt; goes to a low level to select the memory block of the redundant wordlines. While, the second repair information signal XSUM is laid on a low level to turn the NMOS transistor N 27  off.  
         [0045]    Next, in a repair mode, the first repair information signal XSUMb is a low level to prevent an incoming of the block address signals BAX 9 i/BAXABi thereto, and a high transition of the second repair information signal XSUM causes the redundant block selection signal BSb&lt;0&gt; to be a low level.  
         [0046]    The normal block selection circuit  320 , referring to FIG. 7, has the same construction with that of the redundant block selection circuit  310  except that the second repair information signal XSUM is not applied thereto (e.g., through the NMOS transistor N 27  of FIG. 6). The first repair information signal XSUMb, being applied to NMOS transistor N 29  connected between node NOD 1 ′ (corresponding to the node NOD 1  in FIG. 6) and NMOS transistor N 30  (corresponding to the NMOS transistor N 26  in FIG. 6), determines whether or not the block address signals BAX 9 i/BAXABi are permitted to be introduced thereto. Other operating features are identical to those of the redundant block selection circuit  310  shown in FIG. 6.  
         [0047]    The sub wordline driver selection circuit  400  shown in FIG. 3 includes NAND gates for the normal and memory blocks, respectively. Each NAND gate forms a unit of the sub wordline driver selection circuit. Referring to FIG. 8, the NAND gate ND 27  as the sub wordline selection unit receives two block selection signals BSb&lt;i&gt; and BSb&lt;j&gt;, and then generates sub wordline driver selection signal PX_SEL&lt;i&gt;.  
         [0048]    It is assumed that the block selection signal for the memory block UB 0  is BSb&lt;0&gt;, and the block selection signal for the memory block UB 1  is BSb&lt;1&gt;. As the block selection signals BSb&lt;0&gt; and BSb&lt;1&gt; are negative logic signals (i.e., active with low levels), the sub wordline driver selection signal PX_SEL&lt;0&gt; becomes a high level.  
         [0049]    The sub wordline drivers are assigned to a memory block by two as shown in FIG. 3. For example, two redundant sub wordline drivers  510  and  520  are associated with the memory block UB 0 , as well as with the memory block UB 1 . Two normal sub wordline drivers  530  and  540  are assigned to the memory blocks UB 2  and UB 3 , respectively. The sub wordline drive signal PXb&lt;i&gt;(i is one of 0˜7) will be utilized to operate the redundant wordline together with the redundant main wordline drive signals RWLb&lt;0&gt; and RWLb&lt;1&gt;.  
         [0050]    Referring to FIG. 9, the redundant sub wordline driver  510  is constructed of NAND gate ND 8  receiving the pre-decoded row address signal BAX 01 i and the first repair information signal XSUMb, NAND gate ND 9  receiving signals NRDb 02  and NRDb 46  which are created from coding the fuse decoding signals, inverter I 12  receiving an output signal from the NAND gate ND 9 , NAND gate ND 10  receiving output signals from the NAND gate ND 8  and the inverter I 12 , NAND gate ND 11  receiving an output signal from the NAND gate ND 10  and the sub wordline driver selection signal PX_SEL&lt;i&gt;(e.g., PX_SEL&lt;0&gt; in FIG. 3), level shifter  511  receiving an output of the NAND gate ND 11 , and inverter I 14  converting an output signal from the level shifter  511  into the sun wordline drive signal PXb&lt;i&gt;.  
         [0051]    Another redundant sub wordline driver  520  has the same circuit architecture with that of the redundant sub wordline driver ( 510 ), except the orders of the coded signals. That is, the driver  520  receives BAXO 1 j, NRDb 13 , and NEDb 57  while the driver  510  receives BAX 01 i, NRDb 02 , and NRDb 46 .  
         [0052]    The conduct of the redundant sub wordline driver  510 , which generates the drive signal PXb&lt;i&gt; to control the redundant wordline RWL, is dependent on a logic state of the row address signal BAX 01 i. When the row address signal BAX 01 i is selected for activation, the sub wordline drive signal PXbi is enabled. When the row address signal BAX 01 j is selected for activation, the sub wordline drive signal PXbj is enabled.  
         [0053]    The coding mechanisms for the sub wordline drive signals PXb&lt;0&gt; through PXb&lt;3&gt; are figured out in a condition that the row repair fuse boxes designate corresponding sub wordline drivers by correlating the redundant sub wordline drivers to the fuse decoding signals NRDb&lt;0&gt;˜NRDb&lt;7&gt;, as follows:  
         [0054]    NRDb&lt;0&gt;/NRDb&lt;4&gt;→&lt;PXb&lt;0&gt;, NRDb&lt;1&gt;/NRDb&lt;5&gt;→PXb&lt;1&gt; NRDb&lt;2&gt;/NRDb&lt;6&gt;→PXb&lt;2&gt;, NRDb&lt;3&gt;/NRDb&lt;7&gt;→PXb&lt;3&gt; 
         [0055]    The first repair information signal XSUMb and the signals NRDb 02 ˜NRDb 57  (i.e., NRDb 02 , NRDb 13 , NEDb 46 , and NEDb 57 ) coded from the fuse decoding signals NRDb&lt;i&gt;are employed to determine whether or not there is an occurrence of need for repairing. The reason of that is because the number of the row repair fuse boxes is identical to that of the redundant wordlines. In addition, in the embodied coding configurations, repair information about the memory blocks UB 2  and UB 3  does not appear because their corresponding block selection signals BSb&lt;2&gt; and BSb&lt;3&gt; are disabled and thereby the sub wordline driver selection signal PX_SEL&lt;1&gt; is disabled.  
         [0056]    In a normal operation, the redundant sub wordline drivers  510  and  520  generate the sub wordline drive signals PXb&lt;i&gt; and PXb&lt;j&gt; (e.g., PXb&lt;0&gt; and PXb&lt;1&gt;, respectively) in response to the row address signals BAX 01 i and BAX 01 j. In a repair operation, as the first repair information signal XSUMb is at a low level, the row address signals BAX 01 i and BAX 01 j are situated in an ineffective state and the sub wordline drive signal PXb&lt;i&gt; and PXb&lt;j&gt; are generated in response to the coded signals NRDb 02 ˜NRDb 57 .  
         [0057]    The sub wordline driver selection signals PX_SEL&lt;i&gt; are master signals to determine turn-on or turn-off of the redundant sub wordline drivers  510  and  520 , going to a high level when the block selection signal BSb&lt;0&gt; (shown in FIG. 3) for the memory block UBO or the block selection signal BSb&lt;1&gt; for the memory block UB 1  is active at a low level.  
         [0058]    Now, it will be explained about a more detail procedure for generating the sub wordline drive signals PXb&lt;i&gt; and PXb&lt;j&gt; (e.g., PXb&lt;0&gt; and PXb&lt;1&gt;, respectively) First, in the normal operation mode, as the first repair information signal XSUMb is at a high level, the output signal from the NAND gate ND 8  becomes a low level in response to the pre-decoded row address signal BAX 01 i. At this time, according to the coded signals NRDb 02  and NRDb 46  of a high levels, the output signal of the inverter I 12  is set on a high level to make a signal path through node NOD 4  be exclusively effective to the output signal of the NAND gate ND 10  that is at a high level. When the sub wordline driver selection signal PX_SEL&lt;i&gt; maintains a high level, the NAND gate ND 11  applies a low-leveled output signal thereof to the level shifter  511  in response to the high-leveled output signal from the NAND gate ND 10  and PX_SEL&lt;i&gt; of a high level. The level shifter  511  pulls a voltage level up to a high level at output node NOD 10  in response to the output signal of a low level from the NAND gate ND 11 . Thereby, the sub wordline drive signal PXb&lt;i&gt; is established on a low level through the inverter I 14 .  
         [0059]    In the repair operation mode, as the first repair information signal XSUMb is at a low level to set the node NOD 4  on normally a high level, the output signal of the NAND gate ND 10  completely responds to the coded signals NRDb 02  and NRDb 46  regardless of the row address signal BAX 01 i. When one of the coded signals NRDb 02  and NRDb 46  falls down to a low level, the nodes NOD 5 , NOD 6 , and NOD 7  are at high, low, and high levels, in sequence. As a result, the high-leveled NOD 7  and PX_SEL&lt;i&gt; makes the node NOD 8  become a low level, and thereby, as is in the normal mode, the sub wordline drive signal PXb&lt;i&gt; is set on a low level.  
         [0060]    [0060]FIG. 10 illustrates circuits of the normal sub wordline drivers  530  and  540 . The drivers  530  and  540  have the same construction, where the driver  530  is formed of NAND gate ND 16  receiving the row address signal BAX 01 i and the sub wordline driver selection signal PX_SEL&lt;j&gt; (e.g., PX_SEL&lt;1&gt; in FIG. 3), level shifter  531  converting an output signal of the NAND gate ND 16  into a signal of high voltage (Vpp) or a low level, and inverter I 19  converting an output signal into the sub wordline drive signal PXb&lt;i&gt; (i is 4 or 6 in FIG. 3).  
         [0061]    As shown in FIG. 10, the normal sub wordline driver  530  (or  540 ) generates the drive signal PXb&lt;i&gt; (or PXb&lt;j&gt;; j is 5 or 7 in FIG. 3) in response to the predecoded row address signals BAX 01 i (or BAX 01 j) and the sub wordline driver selection signal PX_SEL&lt;j&gt; (i.e., PX_SEL&lt;1&gt; in FIG. 3).  
         [0062]    The wordline enable signal generator block  600  shown in FIG. 3 includes redundant main wordline enable signal generator  610  and normal main wordline enable signal generators  620   s . Referring to FIG. 11, the redundant main wordline enable signal generator  610  is constructed of inverter I 24  converting the first repair information signal XSUMb into its reverse signal, NOR gate NR 2  receiving the block selection signal BSb&lt;0&gt; and the output signal of the inverter I 24 , inverter I 25  reversing the output signal from the inverter I 24 , NOR gate NR 3  receiving the block selection signal BSb&lt;0&gt; and an output signal of the inverter I 25 , inverters I 22  and I 23  converting an output signal of the NOR gate NR 2  into the normal main wordline enable signal BS&lt;0&gt;, and inverters I 26 ˜I 29  converting an output signal of the NOR gate NR 3  into the redundant main wordline enable signal RMWLEN.  
         [0063]    The redundant main wordline enable signal RMWLEN is made by responding to the first repair information signal XSUMb and the block selection signal BSb&lt;0&gt; that is assigned to a memory block (e.g., UBO) including the redundant wordline RWL.  
         [0064]    With respect to an operation in the redundant main wordline enable signal generator  610 , during a normal mode where there is no occurrence of repair, as the block selection signal BSb&lt;0&gt; is at a low level and the first repair information signal XSUMb is at a high level, the normal main wordline enable signal BS&lt;0&gt; is enabled with a high level to make the X-decoder (i.e., row decoder) be active while the redundant main wordline enable signal RMWLEN is disabled with a low level. During a repair mode, the first repair information signal XSUMb is set on a low level, and thereby the normal main wordline enable signal BS&lt;0&gt; is turned off with a low level while the redundant main wordline enable signal RMWLEN is enabled with a high level.  
         [0065]    [0065]FIG. 12 shows the normal main wordline enable signal generator  620  that is associated with the normal memory block (e.g., UB 1 , UB 2 , or UB 3  in FIG. 3).  
         [0066]    The normal main wordline enable signal generator  620  is formed of three inverters  130 ,  131 , and  132 , connected in serial, for converting the block selection signal BSb&lt;i&gt; (i is one of 13) into the normal main wordline enable signal BS&lt;i&gt; (i is one of 1˜3).  
         [0067]    When the block selection signal BSb&lt;i&gt; becomes active, regardless of the redundant main wordline enable signal RMWLEN, the normal main wordline enable signal BS&lt;i&gt; is generated with a high level that is an inverted signal from the block selection signal BSb&lt;i&gt; after a delay time by the three inverters. In a repair operation mode, since the block selection signal BSb&lt;i&gt; itself is established at a disable state, the normal main wordline enable signal BS&lt;i&gt; is not activated.  
         [0068]    Next, the redundant main wordline drivers group  700  shown in FIG. 3, referring to FIG. 13, includes two units of the redundant main wordline drivers,  710  and  720 , to control the redundant wordline RWL that is enabled by decoding the redundant main wordline drive signal RMWLb and the sub wordline drive signal PXb&lt;i&gt;. One of the drivers, e.g.,  710 , is constructed of PMOS transistor P 12  connected between the high voltage Vpp and node XX 0 , having its gate coupled to precharge signal WLC_XDEC, NMOS transistor N 39  connected between the node XX 0  and Vss, having its gate coupled to the summation signal NRDb 4 &lt;0&gt; through three inverters I 33 ˜I 35  connected in serial from each other, NMOS transistor N 41  connected between the NMOS transistor N 39  and Vss, having its gate coupled to the redundant main wordlines enable signal RMWLEN, PMOS transistor P 13  connected between Vpp and the node XX 0 , having a gate coupled to an output signal of inverter I 39  that reverses a logic state at the node XX 0 , and inverter I 40  converting the output signal of the inverter I 39  into the redundant main wordline drive signal RMWLb&lt;0&gt;. The other one, i.e.,  720 , has the same constitution with that of the driver  710 , except that its corresponding signal RMWLb&lt;1&gt; is made by responding the summation signal NRDb&lt;1&gt;. The PMOS transistor P 13  (or P 15 ) and the inverter I 39  (or I 41 ) form a latch circuit to hold a logic state at the node XX 0  (or XX 2 ) until a new valid summation signal NRDb 4 &lt;0&gt; (or NRDb 4 &lt;1&gt;) is applied thereto.  
         [0069]    The signals RX_DET&lt;0&gt; and RX_DET&lt;1&gt; are generated from inverting the summation signals NRDb 4 &lt;0&gt; and NRDb&lt;1&gt;, respectively, supplied from the fuse summation circuit  200 , and, in a repair mode, go to high levels, each in response to the summation signals NRDb 4 &lt;0&gt; and NRDb&lt;1&gt; of a low levels. The precharge signal WLC_XDEC is provided to the driver  710  in order to charge the node XX 0  up to a predetermined voltage level in advance, being also applied to a main X-decoder (not shown). When the precharge signal WLC_XDEC is at a low level, the nodes XX 0  and XX 2  are charged up to high levels and thereby the redundant main wordline drive signals RMWLb&lt;0&gt; and RMWLb&lt;1&gt; are precharged with high levels.  
         [0070]    During a repair operation mode, as the redundant main wordline enable signal RMWLEN is at a high level, the NMOS transistor N 41  is turned on and thereby the redundant main wordline drive signal RMWLb&lt;0&gt; or RMWLb&lt;1&gt; is enabled.  
         [0071]    The two redundant main wordline drive signals RMWLb&lt;0:1&gt; (RMWLb&lt;0&gt; and RMWLb&lt;1&gt;) are employed to operate the eight redundant wordlines RWL&lt;0:7&gt; arranged in the memory block UBO after being decoded with the four sub wordline drive signals PXb&lt;0:3&gt; supplied from the redundant sub wordline drivers  510   s  and  520   s.    
         [0072]    While the aforementioned configurations for performing normal and repair operations are involved in the unit of four memory blocks UB 0 ˜UB 4  (the upper half in a memory bank, as shown in FIG. 2) in which the memory block UBO has the eight redundant wordlines, it is easy to understand that the other memory blocks UB 4 ˜UB 7  (in this case, the eight redundant wordlines are arranged in UB 7 ) are also operable with the same manner as the above constructions of the circuits and procedures thereof.  
         [0073]    As seen in the drawings and description above, the present invention provides advanced constructions for repairing to be able to enhance efficiency of a repair operation by disposing the redundant wordlines in a specific memory block. The memory block including the redundant wordlines is conductive whenever there is a need of repairing, regardless of a location of a memory block having a defective wordline (or a defective memory cell). Such enhancement of the repair efficiency with flexible substitution architecture increases the product yield of semiconductor memory devices, and also contributes to reduce the cost per chip (or the cost per bit) and to ensure a competitive price of a semiconductor memory device in a market.  
         [0074]    Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as described in the accompanying claims