Abstract:
An inverter circuit including: first to third transistors; first and second switches; and a first capacitive element. The first and second transistors are connected in series between a first voltage line and a second voltage line. The third transistor is connected between the second voltage line and a gate of the second transistor. The first and second switches are connected in series between a voltage supply line and a gate of the third transistor, and are turned on/off alternately to prevent the first and second switches from simultaneously turning ON. One end of the first capacitive element is connected to a node between the first and second switches. Off-state of the first transistor allows a predetermined fixed voltage to be supplied from the voltage supply line to the gate of the second transistor, via the first switch, the one end of the first capacitive element and the second switch.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an inverter circuit that is suitably applicable to, for example, a display device using an organic EL (Electro Luminescence) element. The present invention also relates to a display device provided with the above-mentioned inverter circuit. 
     2. Description of the Related Art 
     In recent years, in the field of display devices that display images, a display device that uses, as a light emitting element for a pixel, an optical element of current-driven type whose light emission luminance changes according to the value of a flowing current, e.g. an organic EL element, has been developed, and its commercialization is proceeding. In contrast to a liquid crystal device and the like, the organic EL element is a self-luminous element. Therefore, in the display device using the organic EL element (organic EL display device), gradation of coloring is achieved by controlling the value of a current flowing in the organic EL element. 
     As a drive system in the organic EL display device, like a liquid crystal display, there are a simple (passive) matrix system and an active matrix system. The former is simple in structure, but has, for example, such a disadvantage that it is difficult to realize a large and high-resolution display device. Therefore, currently, development of the active matrix system is brisk. In this system, the current flowing in a light emitting element arranged for each pixel is controlled by a drive transistor. 
     In the above-mentioned drive transistor, there is a case in which a threshold voltage V th  or a mobility μ changes over time, or varies from pixel to pixel due to variations in production process. When the threshold voltage V th  or the mobility μ varies from pixel to pixel, the value of the current flowing in the drive transistor varies from pixel to pixel and therefore, even when the same voltage is applied to the gate of the drive transistor, the light emission luminance of the organic EL element varies and uniformity of a screen is impaired. Thus, there has been developed a display device in which a correction function to address a change in the threshold voltage V th  or the mobility μ is incorporated (see, for example, Japanese Unexamined Patent Application Publication No. 2008-083272). 
     A correction to address the change in the threshold voltage V th  or the mobility μ is performed by a pixel circuit provided for each pixel. As illustrated in, for example,  FIG. 16 , this pixel circuit includes: a drive transistor Tr 100  that controls a current flowing in an organic EL element  111 , a write transistor Tr 200  that writes a voltage of a signal line DTL into the drive transistor Tr 100 , and a retention capacitor C s , and therefore, the pixel circuit has a 2Tr1C circuit configuration. The drive transistor Tr 100  and the write transistor Tr 200  are each formed by, for example, an n-channel MOS Thin Film Transistor (TFT). 
       FIG. 15  illustrates an example of the waveform of a voltage applied to the pixel circuit and an example of a change in each of the gate voltage V g  and the source voltage V s  of the drive transistor Tr 100 . In Part (A) of  FIG. 15 , there is illustrated a state in which a signal voltage V sig  and an offset voltage V ofs  are applied to the signal line DTL. In Part (B) of  FIG. 15 , there is illustrated a state in which a voltage V dd  for turning on the write transistor Tr 200  and a voltage V ss  for turning off the write transistor Tr 200  are applied to a write line WSL. In Part (C) of  FIG. 15 , there is illustrated a state in which a high voltage V ccH  and a low voltage V ccL  are applied to a power-source line PSL. Further, in Part (D) and (E) of  FIG. 15 , there is illustrated a state in which the gate voltage V g  and the source voltage V s  of the drive transistor Tr 100  change over time in response to the application of the voltages to the power-source line PSL, the signal line DTL and the write line WSL. 
     From  FIG. 15 , it is found that a WS pulse P is applied to the write line WSL twice within 1 H, a threshold correction is performed by the first WS pulse P, and a mobility correction and signal writing are performed by the second WS pulse P. In other words, in  FIG. 15 , the WS pulse P is used for not only the signal writing but also the threshold correction and the mobility correction of the drive transistor Tr 100 . 
     SUMMARY OF THE INVENTION 
     Incidentally, in the display device employing the active matrix system, each of a horizontal drive circuit (not illustrated) that drives the signal line DTL and a write scan circuit (not illustrated) that selects each pixel  113  sequentially is configured to basically include a shift resister (not illustrated), and has a buffer circuit (not illustrated) for each stage, corresponding to each column or each row of pixels  113 . For example, the buffer circuit within the write scan circuit is typically configured such that two inverter circuits are connected in series. Here the inverter circuit has, as illustrated in  FIG. 17 , for example, a single channel type of circuit configuration in which two n-channel MOS transistors Tr 1  and Tr 2  are connected in series. An inverter circuit  200  illustrated in  FIG. 17  is inserted between high voltage wiring L H  to which a high-level voltage is applied and low voltage wiring L L  to which a low-level voltage is applied. The gate of the transistor Tr 2  on the high voltage wiring L H  side is connected to the high voltage wiring L H , and the gate of the transistor Tr 1  on the low voltage wiring L L  side is connected to an input terminal IN. Further, a connection point C between the transistor Tr 1  and the transistor Tr 2  is connected to an output terminal OUT. 
     In the inverter circuit  200 , as illustrated in  FIG. 18 , for example, when a voltage V in  of the input terminal IN is V ss , a voltage V out  of the output terminal OUT is not V dd , and instead is V dd -V th . In other words, the threshold voltage V th  of the transistor Tr 2  is included in the voltage V out  of the output terminal OUT, and the voltage V out  of the output terminal OUT is largely affected by variations in the threshold voltage V th  of the transistor Tr 2 . 
     Thus, for example, as illustrated by an inverter circuit  300  in  FIG. 19 , it is conceivable that the gate and the drain of the transistor Tr 2  may be electrically separated from each other, and the gate may be connected to high voltage wiring L H2  to which a voltage V dd2  (≧V dd  V th ) that is higher than the voltage V dd  of the drain is applied. In addition, for example, a bootstrap type of circuit configuration as illustrated by an inverter circuit  400  in  FIG. 20  is conceivable. Specifically, it is conceivable to provide a circuit configuration in which a transistor Tr 12  is inserted between the gate of the transistor Tr 2  and the high voltage wiring L H , the gate of the transistor Tr 12  is connected to the high voltage wiring L H , and a capacitive element C 10  is inserted between: a connection point D between the gate of the transistor Tr 2  and the source of the transistor Tr 12 ; and the connection point C. 
     However, in the circuit in any of  FIG. 17 ,  FIG. 19  and  FIG. 20 , until the time when the input voltage V in  becomes high, namely when the output voltage V out  becomes low, a current (through current) flows from the high voltage wiring L H  side to the low voltage wiring L L  side via the transistors Tr 1  and Tr 2 . As a result, power consumption in the inverter circuit also becomes large. In addition, in the circuits of  FIG. 17 ,  FIG. 19  and  FIG. 20 , when, for example, the input voltage V in  is V dd  as indicated with a point surrounded by a broken line in Part (B) of  FIG. 18 , the output voltage V out  is not V ss , and the peak value of the output voltage V out  varies. As a result, there has been such a shortcoming that the threshold corrections and the mobility corrections of the drive transistors Tr 100  in pixel circuits  112  vary among the pixel circuits  112 , and such variations result in variations in luminance. 
     Incidentally, the above-described shortcoming not only occurs in the scan circuit of the display device, but may take place similarly in any other devices. 
     In view of the foregoing, it is desirable to provide an inverter circuit capable of setting the peak value of an output voltage at a desired value while suppressing power consumption, and a display device having this inverter circuit. 
     According to an embodiment of the present invention, there is provided a first inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type; a first capacitive element; and an input terminal and an output terminal. The first transistor makes or breaks electric connection between the output terminal and a first voltage line, in response to a potential difference between a voltage of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electric connection between a second voltage line and the output terminal, in response to a potential difference between a voltage of a first terminal that is a source or a drain of the seventh transistor and a voltage of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electric connection between a gate of the seventh transistor and the third voltage line, in response to a potential difference between the voltage of the input terminal and a voltage of a third voltage line or a potential difference corresponding thereto. The fourth transistor makes or breaks electric connection between the first capacitive element and the gate of the seventh transistor, in response to a first control signal inputted into a gate of the fourth transistor. The fifth transistor makes or breaks electric connection between the first capacitive element and a fourth voltage line, in response to a second control signal inputted into a gate of the fifth transistor. The sixth transistor makes or breaks electric connection between the first terminal and the fifth voltage line, in response to a potential difference between the voltage of the input terminal and a voltage of a fifth voltage line or a potential difference corresponding thereto. The seventh transistor makes or breaks electric connection between the first terminal and a sixth voltage line, in response to a potential difference between a gate voltage of the seventh transistor and a gate voltage of the second transistor or a potential difference corresponding thereto. The first capacitive element is inserted between a drain or a source of the fifth transistor and a seventh voltage line. 
     According to an embodiment of the present invention, there is provided a first display device having a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns and a plurality of pixels arranged in rows and columns, and the drive section including a plurality of inverter circuits each provided for each of the scanning lines to drive each of the pixels. Each of the inverter circuits in the drive section includes the same elements as those of the above-described first inverter circuit. 
     In the first inverter circuit and the first display device according to the above embodiments of the present invention, between the gate of the seventh transistor and the first voltage line, between the gate of the second transistor and the first voltage line, between the source of the second transistor and the first voltage line, there are provided the first transistor, the third transistor and the sixth transistor, respectively, which perform on-off operation according to a potential difference between the input voltage and the voltage of the first voltage line. As a result, for example, when the input voltage falls, on-resistance of each of the first transistor, the third transistor and the sixth transistor gradually becomes large, and the time necessary to charge the gates and the sources of the second transistor and the seventh transistor to the voltage of the first voltage line becomes longer. Further, for example, when the input voltage rises, the on-resistance of each of the first transistor, the third transistor and the sixth transistor gradually becomes small, and the time necessary to charge the gate and the source of the second transistor to the voltage of the first voltage line becomes short. In addition, in the above embodiments of the present invention, when the input voltage falls, the gate of the seventh transistor is charged to a voltage equal to or higher than an on-voltage of the seventh transistor. As a result, for example, when a falling voltage is input into the input terminal, the first transistor, the third transistor and the sixth transistor are turned off, and immediately after that, the seventh transistor is turned on and further, the second transistor is turned on and therefore, the output voltage becomes the voltage on the second voltage line side. Moreover, for example, when the input voltage rises, the first transistor, the third transistor and the sixth transistor are turned on and immediately after that, the second transistor is turned off. As a result, the output voltage becomes the voltage on the first voltage line side. 
     According to an embodiment of the present invention, there is provided a second inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type; a first capacitive element; and an input terminal and an output terminal. A gate of the first transistor is electrically connected to the input terminal, one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal. One terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal. A gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the second transistor. A gate of the fourth transistor is supplied with a first control signal, and one terminal of a drain and a source of the fourth transistor is electrically connected to a gate of the seventh transistor. A gate of the fifth transistor is supplied with a second control signal, one terminal of a drain and a source of the fifth transistor is electrically connected to a fourth voltage line, and the other terminal of the fifth transistor is electrically connected to the other terminal of the fourth transistor. A gate of the sixth transistor is electrically connected to the input terminal, one terminal of a drain and a source of the sixth transistor is electrically connected to a fifth voltage line, and the other terminal of the sixth transistor is electrically connected to the gate of the second transistor. One terminal of a drain and a source of the seventh transistor is electrically connected to a sixth voltage line, and the other terminal of the seventh transistor is electrically connected to the gate of the second transistor. The first capacitive element is inserted between the other terminal of the fifth transistor and a seventh voltage line. 
     According to an embodiment of the present invention, there is provided a second display device having a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns and a plurality of pixels arranged in rows and columns, and the drive section including a plurality of inverter circuits each provided for each of the scanning lines to drive each of the pixels. Each of the inverter circuits in the drive section includes the same elements as those of the above-described second inverter circuit. 
     In the second inverter circuit and the second display device according to the above embodiments of the present invention, between the gate of the seventh transistor and the first voltage line, between the gate of the second transistor and the first voltage line, between the source of the second transistor and the first voltage line, there are provided the first transistor, the third transistor and the sixth transistor, respectively, whose gates are connected to the input terminal. As a result, for example, when the input voltage falls, on-resistance of each of the first transistor, the third transistor and the sixth transistor gradually becomes large, and the time necessary to charge the gates and the sources of the second transistor and the seventh transistor to the voltage of the first voltage line becomes longer. Further, for example, when the input voltage rises, the on-resistance of each of the first transistor, the third transistor and the sixth transistor gradually becomes small, and the time necessary to charge the gate and the source of the second transistor to the voltage of the first voltage line becomes short. In addition, in the above embodiments of the present invention, when the input voltage falls, the gate of the seventh transistor is charged to a voltage equal to or higher than an on-voltage of the seventh transistor. As a result, for example, when a falling voltage is input into the input terminal, the first transistor, the third transistor and the sixth transistor are turned off, and immediately after that, the seventh transistor is turned on and further, the second transistor is turned on and therefore, the output voltage becomes the voltage on the second voltage line side. Moreover, for example, when the input voltage rises, the first transistor, the third transistor and the sixth transistor are turned on and immediately after that, the second transistor is turned off. As a result, the output voltage becomes the voltage on the first voltage line side. 
     In the first and second inverter circuits and the first and second display devices according to the above-described embodiments of the present invention, a second capacitive element may be inserted between the gate and the source of the second transistor. In this case, a capacity of the second capacitive element is desired to be smaller than a capacity of the first capacitive element. 
     According to the first and second inverter circuits and the first and second display devices in the above-described embodiments of the present invention, there is no time period over which the first transistor and the second transistor are turned on at the same time, and the fourth transistor and the seventh transistor are turned on at the same time, and the third transistor, the fourth transistor and the fifth transistor are turned on at the same time. This makes it possible to suppress power consumption, because almost no current (through current) flows between the voltage lines, via these transistors. In addition, when the gate of the first transistor changes from high to low, the output voltage becomes a voltage on the second voltage line side or a voltage on the first voltage line side, and when the gate of the first transistor changes from low to high, the output voltage becomes a voltage on the reverse side of the above-mentioned side. This makes it possible to reduce a shift of the peak value of the output voltage from a desired value. As a result, for example, it is possible to reduce variations in the threshold correction and the mobility correction of the drive transistor in the pixel circuit, among the pixel circuits, and further, variations in the luminance among the pixels may be reduced. 
     Moreover, in the above-described embodiments of the present invention, on either of the low voltage side and the high voltage side, voltage lines may be provided as a single common voltage line. Therefore, in this case, there is no need to increase the withstand voltage of the inverter circuit. 
     Other and further objects, features and advantages of the invention will appear more fully from the following description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram illustrating an example of an inverter circuit according to an embodiment of the present invention; 
         FIG. 2  is a waveform diagram illustrating an example of input-output signal waveforms of the inverter circuit in  FIG. 1 ; 
         FIG. 3  is a waveform diagram illustrating an example of the operation of the inverter circuit in  FIG. 1 ; 
         FIG. 4  is a circuit diagram for explaining an example of the operation of the inverter circuit in  FIG. 1 ; 
         FIG. 5  is a circuit diagram for explaining an example of the operation following  FIG. 4 ; 
         FIG. 6  is a circuit diagram for explaining an example of the operation following  FIG. 5 ; 
         FIG. 7  is a circuit diagram for explaining an example of the operation following  FIG. 6 ; 
         FIG. 8  is a circuit diagram for explaining an example of the operation following  FIG. 7 ; 
         FIG. 9  is a circuit diagram for explaining an example of the operation following  FIG. 8 ; 
         FIG. 10  is a circuit diagram for explaining an example of the operation following  FIG. 9 ; 
         FIG. 11  is a waveform diagram illustrating another example of the input-output signal waveforms of the inverter circuit in  FIG. 1 ; 
         FIG. 12  is a waveform diagram illustrating another example of the operation of the inverter circuit in  FIG. 1 ; 
         FIG. 13  is a schematic configuration diagram of a display device that is one of application examples of the inverter circuit in the present embodiment and its modification; 
         FIG. 14  is a circuit diagram illustrating an example of a write-line driving circuit and an example of a pixel circuit in  FIG. 13 ; 
         FIG. 15  is a waveform diagram illustrating an example of the operation of the display device in  FIG. 13 ; 
         FIG. 16  is a circuit diagram illustrating an example of a pixel circuit in a display device in related art; 
         FIG. 17  is a circuit diagram illustrating an example of an inverter circuit in related art; 
         FIG. 18  is a waveform diagram illustrating an example of input-output signal waveforms of the inverter circuit in  FIG. 17 ; 
         FIG. 19  is a circuit diagram illustrating another example of the inverter circuit in related art; 
         FIG. 20  is a circuit diagram illustrating another example of the inverter circuit in related art; 
         FIG. 21  is a circuit diagram illustrating an example of an inverter circuit according to a reference example; and 
         FIG. 22  is a waveform diagram illustrating an example of input-output signal waveforms of the inverter circuit in  FIG. 21 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention will be described below in detail with reference to the drawings. The description will be provided in the following order. 
     1. Embodiment ( FIG. 1  through  FIG. 10 ) 
     2. Modification ( FIG. 11  and  FIG. 12 ) 
     3. Application example ( FIG. 13  through  FIG. 15 ) 
     4. Description of related art ( FIG. 16  through  FIG. 20 ) 
     5. Description of reference technique ( FIG. 21  and  FIG. 22 ) 
     Embodiment 
     Configuration 
       FIG. 1  illustrates an example of the entire configuration of an inverter circuit  1  according to an embodiment of the present invention. The inverter circuit  1  outputs, from an output terminal OUT, a pulse signal (e.g., Part (B) of  FIG. 2 ) whose waveform is approximately the inverse of the signal waveform of a pulse signal (e.g., Part (A) of  FIG. 2 ) input into an input terminal IN. The inverter circuit  1  is suitably formed on an amorphous silicon or amorphous oxide semiconductor and has, for example, seven transistors Tr 1  to Tr 7  of the same channel type. In addition to the seven transistors Tr 1  to Tr 7 , the inverter circuit  1  includes two capacitive elements C 1  and C 2 , the input terminal IN and the output terminal OUT, and has a 7Tr2C circuit configuration. 
     The transistor Tr 1  is equivalent to a specific example of “the first transistor” according to the embodiment of the present invention, and the transistor Tr 2  is equivalent to a specific example of “the second transistor” according to the embodiment of the present invention, and the transistor Tr 1  is equivalent to a specific example of “the third transistor” according to the embodiment of the present invention. Further, the transistor Tr 4  is equivalent to a specific example of “the fourth transistor” according to the embodiment of the present invention, and the transistor Tr 5  is equivalent to a specific example of “the fifth transistor” according to the embodiment of the present invention. Furthermore, the transistor Tr 6  is equivalent to a specific example of “the sixth transistor” according to the embodiment of the present invention, and the transistor Tr 7  is equivalent to a specific example of “the seventh transistor” according to the embodiment of the present invention. Moreover, the capacitive element C 1  is equivalent to a specific example of “the first capacitive element” according to the embodiment of the present invention, and the capacitive element C 2  is equivalent to a specific example of “the second capacitive element” according to the embodiment of the present invention. 
     The transistors Tr 1  to Tr 7  are thin-film transistors (TFTs) of the same channel type and are, for example, n-channel MOS (Metal Oxide Film Semiconductor) type of thin-film transistors (TFTs). The transistor Tr 1  is, for example, configured to establish and cut off electric connection between the output terminal OUT and the low voltage line L L , according to a potential difference V gs1  (or a potential difference corresponding thereto) between a voltage (input voltage V in ) of the input terminal IN and a voltage V L  of a low voltage line L L . The gate of the transistor Tr 1  is electrically connected to the input terminal IN, and the source or the drain of the transistor Tr 1  is electrically connected to the low voltage line L L . Of the source and the drain of the transistor Tr 1 , one that is a terminal unconnected with the low voltage line L L  is electrically connected to the output terminal OUT. The transistor Tr 2  is configured to establish and cut off electric connection between a high voltage line L H  and the output terminal OUT, according to a potential difference V gs2  (or a potential difference corresponding to thereto) between a voltage V s7  of a terminal (terminal A) unconnected with the high voltage line L H  and the voltage (output voltage V out ) of the output terminal OUT. The terminal A is one of the source and the drain of the transistor Tr 7 . The gate of the transistor Tr 2  is electrically connected to the terminal A of the transistor Tr 7 . The source or the drain of the transistor Tr 2  is electrically connected to the output terminal OUT, and of the source and the drain of the transistor Tr 2 , one that is a terminal unconnected with the output terminal OUT is electrically connected to the high voltage line L H . 
     The transistor Tr 3  is configured to establish and cut off electric connection between the gate of the transistor Tr 7  and the low voltage line L L , according to a potential difference V gs3  (or a potential difference corresponding thereto) between the input voltage V in  and the voltage V L  of the low voltage line L L . The gate of the transistor Tr 3  is electrically connected to the input terminal IN. The source or the drain of the transistor Tr 3  is electrically connected to the low voltage line L L , and of the source and the drain of the transistor Tr 3 , one that is a terminal unconnected with the low voltage line L L  is electrically connected to the gate of the transistor Tr 7 . The transistor Tr 4  is configured to establish and cut off electric connection between the capacitive element C 1  and the gate of the transistor Tr 7 , according to a control signal input into a control terminal AZ 1 . The gate of the transistor Tr 4  is electrically connected to the control terminal AZ 1 . The source or the drain of the transistor Tr 4  is electrically connected to the capacitive element C 1 , and of the source and the drain of the transistor Tr 4 , one that is a terminal unconnected with the capacitive element C 1  is electrically connected to the gate of the transistor Tr 7 . The transistor Tr 5  is configured to establish and cut off electric connection between the high voltage line L H  and the capacitive element C 1 , according to a control signal input into a control terminal AZ 2 . The gate of the transistor Tr 5  is electrically connected to the control terminal AZ 2 . The source or the drain of the transistor Tr 5  is electrically connected to the high voltage line L H . Of the source and the drain of the transistor Tr 5 , one that is a terminal unconnected with the high voltage line L H  is electrically connected to the capacitive element C 1 . 
     The transistor Tr 6  is configured to establish and cut off electric connection between the terminal A of the transistor Tr 7  and the low voltage line L L , according to a potential difference V gs6  (or a potential difference corresponding thereto) between the input voltage V in , and the voltage V L  of the low voltage line L L . The gate of the transistor Tr 6  is electrically connected to the input terminal IN. The source or the drain of the transistor Tr 6  is electrically connected to the low voltage line L L , and of the source and the drain of the transistor Tr 6 , one that is a terminal unconnected with the low voltage line L L  is electrically connected to the terminal A of the transistor Tr 7 . In other words, the transistors Tr 1 , Tr 3  and Tr 6  are connected to the same voltage line (the low voltage line L L ). Therefore, the terminal on the low voltage line L L  side of the transistor Tr 1 , the terminal on the low voltage line L L  side of the transistor Tr 3  and the terminal on the low voltage line L L  side of the transistor Tr 6  are at the same potential. The transistor Tr 7  is configured to establish and cut off electric connection between the high voltage line L H  and one, which is a terminal unconnected with the low voltage line L L , of the source and the drain of the transistor Tr 6 , according to a potential difference V gs7  (or a potential difference corresponding thereto) between the voltage V s7  of the terminal unconnected with the capacitive element C 1  of the source and the drain of the transistor Tr 4  and a gate voltage V g2  (the voltage V s7  of the terminal A) of the transistor Tr 2 . The gate of the transistor Tr 7  is electrically connected to the terminal unconnected with the capacitive element C 1 , which terminal is one of the source and the drain of the transistor Tr 4 . The source or the drain of the transistor Tr 7  is electrically connected to the high voltage line L H , and of the source and the drain of the transistor Tr 7 , one that is the terminal (the terminal A) unconnected with the high voltage line L H  is electrically connected to the terminal unconnected with the low voltage line L L , which terminal is one of the source and the drain of the transistor Tr 6 . In other words, the transistors Tr 2 , Tr 5  and Tr 7  are connected to the same voltage line (high voltage line L H ). Therefore, the terminal on the high voltage line L H  side of the transistor Tr 2 , the terminal on the high voltage line L H  side of the transistor Tr 5  and the terminal on the high voltage line L H  side of the transistor Tr 7  are at the same potential. 
     The low voltage line L L  is equivalent to a specific example of “the first voltage line” according to the embodiment of the present invention. The high voltage line L H  is equivalent to a specific example of “the second voltage line” according to the embodiment of the present invention. 
     The high voltage line L H  is connected to a power source (not illustrated) that outputs a voltage (constant voltage) higher than the voltage V L  of the low voltage line L L . The voltage of the high voltage line L H  is V dd  at the time of driving the inverter circuit  1 . On the other hand, the low voltage line L L  is connected to a power source (not illustrated) that outputs a voltage (constant voltage) lower than a voltage V H  of the high voltage line L H , and the voltage V L  of the low voltage line L L  is a voltage V ss  (&lt;V dd ) at the time of driving the inverter circuit  1 . 
     The control terminal AZ 1  is connected to a power source S 1  (not illustrated) that outputs a predetermined pulse signal. The control terminal AZ 2  is connected to a power source S 2  (not illustrated) that outputs a predetermined pulse signal. The power source S 1  is, for example, configured to output a high while a low is applied to the control terminal AZ 2 , as illustrated in Part (C) of  FIG. 2 . On the other hand, the power source S 2  is, for example, configured to output a high while a low is applied to the control terminal AZ 1 , as illustrated in Part (B) of  FIG. 2 . In other words, the power source S 1  and the power source S 2  are configured to alternately output highs so that the transistors Tr 4  and Tr 5  are not in an ON state at the same time (namely, the transistors Tr 4  and Tr 5  are turned on and off alternately). The power source S 1  is configured such that the output voltage of the power source S 1  changes from low to high (in other words, the transistor Tr 4  is turned on), in timing different from the timing in which the input voltage V in  rises. The power source S 1  is, for example, configured such that the output voltage of the power source S 1  changes from low to high immediately before the input voltage V in  drops. 
     The capacitive element C 1  is inserted between the terminal unconnected with the high voltage line L H , which is one of the source and the drain of the transistor Tr 5 , and the low voltage line L L . The capacitive element C 2  is inserted between the gate of the transistor Tr 2  and the source of the transistor Tr 2 . The value of each of the capacitive element C 1  and the capacitive element C 2  is sufficiently larger than parasitic capacitances of the transistors Tr 1  to Tr 7 . The value of the capacity of the capacitive element C 1  is larger than the capacity of the capacitive element C 2 . When a falling voltage is input into the input terminal IN, and the transistor Tr 3  is turned off, the value of the capacity of the capacitive element C 1  becomes a value that makes it possible to charge the gate of the transistor Tr 7  to a voltage of V ss +V th7  or more. In addition, the V th7  is a threshold voltage of the transistor Tr 7 . 
     Incidentally, in a relation with an inverter circuit in related art (the inverter circuit  200  in  FIG. 17 ), the inverter circuit  1  is equivalent to a circuit in which a control element  10  and the capacitive element C 2  are inserted between the transistors Tr 1  and Tr 2  in an output stage and the input terminal IN. Here, for example, as illustrated in  FIG. 1 , the control element  10  includes a terminal P 1  electrically connected to the input terminal IN, a terminal P 2  electrically connected to the low voltage line L L , a terminal P 3  electrically connected to the gate of the transistor Tr 2  and a terminal P 4  electrically connected to a high voltage line L H2 . The control element  10  further includes, for example, as illustrated in  FIG. 1 , the transistors Tr 3  to Tr 7  and the capacitive element C 1 . 
     The control element  10  is, for example, configured to charge the gate of the transistor Tr 2  electrically connected to the terminal P 3  to a voltage of V ss +V th2  or more when a falling voltage is input into the terminal P 1 . Further, for example, the control element  10  is configured to cause the gate voltage V g2  of the transistor Tr 2  electrically connected to the terminal P 3  to be a voltage of less than V ss +V th2  when a rising voltage is input into the terminal P 1 . Incidentally, the description of the operation of the control element  10  will be provided with the following description of the operation of the inverter circuit  1 . 
     [Operation] 
     Next, there will be described an example of the operation of the inverter circuit  1  with reference to  FIG. 3  to  FIG. 10 .  FIG. 3  is a waveform diagram illustrating an example of the operation of the inverter circuit  1 .  FIG. 4  through  FIG. 10  are circuit diagrams illustrating an example of a series of operation of the inverter circuit  1 . 
     First, as illustrated in  FIG. 4 , it is assumed that the input voltage V in  is low (V ss ), the transistor Tr 5  is on, and the transistor Tr 4  is off. At the time, the transistors Tr 1  and Tr 3  are off, the capacitive element C 1  is charged with V dd , and a source voltage V s5  of the transistor Tr 5  is V dd . Further, the gate voltage V g2  of the transistor Tr 2  is V dd +ΔV. Here, ΔV is a value equal to or higher than the threshold voltage V th2  of the transistor Tr 2 , and the transistor Tr 2  is on. Therefore, at the time, in the output terminal OUT, V dd  is output as the output voltage V out . 
     Subsequently, as illustrated in  FIG. 5 , in a state in which the input voltage V in  is low (V ss ), the transistor Tr 4  is turned on after the transistor Tr 5  is turned off. In other words, the transistor Tr 4  is turned on before the input voltage V in  changes from low (V ss ) to high (V dd ). The gate voltage V g2  of the transistor Tr 2  is V dd +ΔV before the transistor Tr 4  is turned on. Therefore, even when the transistor Tr 4  changes from OFF to ON, the transistor Tr 2  maintains the ON state, and V dd  is maintained for the output voltage V out  as well. 
     Next, in a state in which the input voltage V in  is low (V ss ), the transistor Tr 5  is turned on after the transistor Tr 4  is turned off. Similarly, when the transistor Tr 4  is turned on (when the transistor Tr 5  is turned off) after the transistors Tr 4  and Tr 5  repeat ON and OFF, the input voltage V in  changes from low (V ss ) to high (V dd ) ( FIG. 6 ). Then, the transistors Tr 1 , Tr 3  and Tr 6  are turned on, and the gates and the sources of the transistors Tr 2  and Tr 7  are charged to the voltage V L  (=V ss ) of the low voltage line L L . As a result, the transistor Tr 2  is turned off, and in the output terminal OUT, V ss  is output as the output voltage V out . Further, when the transistor Tr 4  is turned on, the capacitive element C 1  charged with V dd  is connected to the low voltage line L L  via the transistor Tr 4 . As a result, the voltage of the terminal (terminal B) on the transistor Tr 5  side of the capacitive element C 1  gradually decreases from V dd  and eventually becomes V ss . 
     Subsequently, in a state in which the input voltage V in  is high (V dd ), the transistor Tr 5  is turned on after the transistor Tr 4  is turned off. Similarly, when the transistor Tr 4  is turned on (when the transistor Tr 5  is off) after the transistors Tr 4  and Tr 5  repeat ON and OFF, the input voltage V in  changes from high (V dd ) to low (V ss ). Then, the transistors Tr 1 , Tr 3  and Tr 6  are turned off. 
     Here, when the transistor Tr 4  is turned on, the voltage (the voltage of the terminal B) of the capacitive element C 1  gradually decreases from V dd2  as described above ( FIG. 7 ). Incidentally, V X  in  FIG. 7  is the voltage (the voltage of the terminal B) of the capacitive element C 1  in a state immediately before the input voltage V in  changes from high (V dd ) to low (V ss ). However, after the transistor Tr 4  is turned on, the input voltage V in  changes from high (V dd ) to low (V ss ), and the transistor Tr 3  is turned off ( FIG. 8 ). Therefore, the capacitive element C 1  is connected to the gate of the transistor Tr 7  via the transistor Tr 4  and thus, the capacitive element C 1  charges the gate of the transistor Tr 7 . As a result, each of the voltage of the capacitive element C 1  and the gate voltage V g2  of the transistor Tr 2  becomes a voltage V y . 
     At the time, in a case in which V y  is a value equal to or larger than the sum of the voltage (=V ss ) of the low voltage line L L  and the threshold voltage V th7  of the transistor Tr 7  (that is, V ss +V th7 ), the transistor Tr 7  is turned on, and a current flows in the transistor Tr 7 . 
     Here, the voltage V y  will be considered. It is assumed that parasitic capacitances of the transistors Tr 1  through Tr 7  are small enough to be ignored as compared with the capacitive element C 1 . At the time, V y  is expressed by an equation (1) using V.
 
V y =V X   (1)
 
     It is apparent from the equation (1) that V y  is determined without relying on the capacity of the capacitive element C 1 , and V y  always becomes V X . 
     The source of the transistor Tr 7  and the gate of the transistor Tr 2  are electrically connected to each other. Therefore, when a current flows in the transistor Tr 7 , the gate voltage V g2  of the transistor Tr 2  starts rising. After a lapse of a predetermined period of time, when the gate voltage V g2  of the transistor Tr 2  becomes V s , +V th2  or more, the transistor Tr 2  is turned on and the output voltage V out  begins increasing gradually. 
     Between the gate and the source of the transistor Tr 2 , the capacitive element C 2  is connected. Therefore, due to bootstrap operation by the capacitive element C 2 , the gate voltage V g2  of the transistor Tr 2  also changes as a source voltage V s2  of the transistor Tr 2  changes. Here, when attention is paid to the gate and the source of the transistor Tr 2 , it is found that the gate voltage V g2  of the transistor Tr 2  rises due to the current of the transistor Tr 7  and the rise in the source of the transistor Tr 2 . Therefore, because its transient is faster than that in a case of a rise only due to the current of the transistor Tr 2 , the voltage V gs2  between the gate and the source of the transistor Tr 2  gradually rises. 
     Here, a gate voltage V g7  of the transistor Tr 7  is V y , and the transistor Tr 4  between the gate of the transistor Tr 7  and the low voltage line L L  is on. Therefore, the capacitive element C 1  is connected to the gate of the transistor Tr 7  and thus, the gate voltage V g7  of the transistor Tr 7  hardly follows the change of the source voltage V s7 , and is approximately a value of V y . As a result, the current from the transistor Tr 7  becomes small as the gate voltage V g2  of the transistor Tr 2  rises. Eventually, when the voltage V gs7  between the gate and the source of the transistor Tr 7  becomes the threshold voltage V th7  of the transistor Tr 7 , the current from the transistor Tr 7  becomes considerably small, and due to the current from the transistor Tr 7 , the gate voltage V g2  of the transistor Tr 2  hardly increases. However, at the time, the transistor Tr 2  is on, and the source voltage V s2  (the output voltage V out ) of the transistor Tr 2  continues rising and thus, the gate voltage V g2  of the transistor Tr 2  also keeps rising due to the bootstrap operation, and the transistor Tr 7  is turned off completely. 
     At the time, when the voltage V gs2  between the gate and the source of the transistor Tr 2  is ΔV, and if ΔV is larger than the threshold voltage V th2  of the transistor Tr 2 , V dd  is output to the outside as the output voltage V out  ( FIG. 9 ). 
     Subsequently, the transistor Tr 4  is turned off. Even if the transistor Tr 4  is turned off, the transistor Tr 7  also is turned off and thus, the gate voltage V g2  of the transistor Tr 2  is not affected. Therefore, the output of V dd  to the outside as the output voltage V out  continues. Further, after the transistor Tr 4  is turned off, the transistor Tr 5  is turned on again, and the source voltage V s5  of the transistor Tr 5  becomes an electric potential of V dd . 
     When the transistor Tr 4  is turned on after the transistor Tr 5  is turned off, capacitive coupling occurs again, and the gate voltage V g7  of the transistor Tr 7  and the source voltage V s5  of and the transistor Tr 5  come to be at the same potential. When the voltage V gs7  of the transistor Tr 7  at the time is assumed to be V a , as illustrated in  FIG. 10 , the gate voltage V g7  between the gate and the source of the transistor Tr 7  is V a −V dd −ΔV, and the transistor Tr 7  still remains off. In addition, the voltage V gs2  between the gate and the source of the transistor Tr 2  continues to be ΔV and thus, V dd  is output to the outside as the output voltage V out . By repeating these operations, the gate voltage V g7  of the transistor Tr 7  eventually becomes V dd . 
     As described above, in the inverter circuit  1  of the present embodiment, the pulse signal (e.g., Part (B) of  FIG. 2 ) whose signal waveform is approximately the inverse of the signal waveform (e.g., Part (A) of  FIG. 2 ) of the pulse signal input into the input terminal IN is output from the output terminal OUT. 
     [Effect] 
     Incidentally, for example, the inverter circuit  200  as illustrated in  FIG. 17  in related art has the single channel type of circuit configuration in which the two n-channel MOS transistors Tr 1  and Tr 2  are connected in series. In the inverter circuit  200 , for example, as illustrated in  FIG. 18 , when the input voltage V in  is V ss , the output voltage V out  is V dd −V th2  without being V dd . In other words, the threshold voltage V th2  of the transistor Tr 2  is included in the output voltage V out , and the output voltage V out  is greatly affected by the variations of the threshold voltage V th2  of the transistor Tr 2 . 
     Thus, for example, as illustrated in the inverter circuit  300  of  FIG. 19 , it is conceivable that the gate and the drain of the transistor. Tr 2  may be electrically isolated from each other, and the gate may be connected to the high voltage wiring L H2  to which the voltage V dd2  (≧V dd +V th2 ) higher than the voltage V dd  of the drain is applied. In addition, for example, it is conceivable to provide the bootstrap type of circuit configuration as indicated by the inverter circuit  400  in  FIG. 20 . 
     However, in the circuit in any of  FIG. 17 ,  FIG. 19  and  FIG. 20 , until the time when the input voltage V in  becomes high, namely when the output voltage V out  becomes low, a current (through current) flows from the high voltage wiring L H  side to the low voltage wiring L L  side via the transistors Tr 1  and Tr 2 . As a result, the power consumption in the inverter circuit also becomes large. In addition, in the circuits of  FIG. 17 ,  FIG. 19  and  FIG. 20 , when, for example, the input voltage V in  is V dd  as indicated with the point surrounded by the broken line in Part (B) of  FIG. 18 , the output voltage V out  is not V ss , and the peak value of the output voltage V out  varies. Therefore, for example, when any of these inverter circuits is applied to a scanner in an organic electroluminescence display device employing an active matrix system, the threshold corrections and the mobility corrections of the drive transistors in the pixel circuits vary among the pixel circuits, and such variations result in variations in luminance. 
     Thus, for example, as indicated by an inverter circuit  500  in  FIG. 21 , it is conceivable that between the transistors Tr 1  and Tr 2  in the output stage and the input terminal IN, the capacitive elements C 1  and C 2  and the transistors Tr 3  through Tr 5  may be provided, and a control signal as illustrated in  FIG. 22  may be input into the transistors Tr 4  and Tr 5 . In the inverter circuit  500 , there is almost no time period over which the transistor Tr 1  and the transistor Tr 2  are turned on at the same time. Therefore, almost no through current flows, and power consumption may be suppressed to a low level. In addition, in response to a fall in the input voltage V in , the output voltage V out  becomes a voltage on a high voltage line V H1  side, and in response to a rise in the input voltage V in , the output voltage V out  becomes a voltage on the low voltage line L L  side. Therefore, there are no variations in the output voltage V out , and variations in luminance from pixel to pixel may be reduced. 
     Incidentally, in the inverter circuit  500  of  FIG. 21 , the newly inserted transistor Tr 5  is connected to a high voltage line L H2  to which a voltage higher than the high voltage line L H1  connected to the transistor Tr 2  is applied. This is to enable turning on of the transistor Tr 2  when the gate of the transistor Tr 2  is charged by the capacitive element C 1  charged with the voltage V dd2 . However, the voltage applied to the high voltage line L H2  is the voltage higher than the input voltage V in . Therefore, when the withstand voltage of the inverter circuit  500  is made equal to the withstand voltage of the inverter circuit  200 , yields may be reduced. Moreover, when the withstand voltage of the inverter circuit  500  is made higher than the withstand voltage of the inverter circuit  200 , manufacturing cost may increase. 
     On the other hand, in the inverter circuit  1  of the present embodiment, between the gate of the transistor Tr 7  and the low voltage line L L , between the gate of the transistor Tr 2  and the low voltage line L L , and between the source of the transistor Tr 2  and the low voltage line L L , the transistors Tr 1 , Tr 3  and Tr 6  that perform on-off operation according to a potential difference between the input voltage V in  and the voltage V L  of the low voltage line L L  are provided, respectively. As a result, when the gate voltage of each of the transistors Tr 1 , Tr 3  and Tr 6  changes (falls) from high (V dd ) to low (V ss ), on-resistance of each of the transistors Tr 1 , Tr 3  and Tr 6  gradually becomes large, and the time necessary to charge the gates and the sources of the transistors Tr 2  and Tr 7  to the voltage V L  of the low voltage line L L  becomes long. Further, when the gate voltage of each of the transistors Tr 1 , Tr 3  and Tr 6  changes (rises) from low (V ss ) to high (V dd ), the on-resistance of each of the transistors Tr 1 , Tr 3  and Tr 6  gradually becomes small, and the time necessary to charge the gates and the sources of the transistors Tr 2  and Tr 7  to the voltage V L  of the low voltage line L L  becomes short. Furthermore, in the inverter circuit  1  of the present embodiment, when the input voltage V in  falls, the gate of the transistor Tr 7  is charged to a voltage equal to or higher than the on-voltage of the transistor Tr 7 . As a result, when the falling voltage is input into the input terminal IN, the transistors Tr 1 , Tr 3  and Tr 6  are turned off, and immediately after that, the transistor Tr 7  is turned on and further, the transistor Tr 2  is turned on and thus, the output voltage V out  becomes the voltage on the high voltage line L H  side. Moreover, when the input voltage V in  rises, the transistors Tr 1 , Tr 3  and Tr 6  are turned on, and immediately after that, the transistors Tr 2  and Tr 7  are turned off. As a result, the output voltage V out  becomes the voltage on the low voltage line L L  side. 
     In this way, the inverter circuit  1  of the present embodiment is configured such that there are no time period over which the transistor Tr 1  and the transistor Tr 2  are turned on at the same time, time period over which the transistor Tr 6  and the transistor Tr 7  are turned on at the same time, and time period over which the transistors Tr 3  to Tr 5  are turned on at the same time. Therefore, there is almost no current (through current) that flows between the high voltage line V H  and the low voltage line L L  via the transistors Tr 1  to Tr 7 . As a result, power consumption is allowed to be suppressed. In addition, in the inverter circuit  1 , only a single voltage line is provided on each of the low voltage side and the high voltage side and thus, there is no need to increase the withstand voltage of the inverter circuit  1 . Based upon the foregoing, in the present embodiment, it is possible to reduce the power consumption without increasing the withstand voltage. 
     &lt;Modification&gt; 
     In the embodiment described above, for example, as illustrated in  FIG. 11  and  FIG. 12 , the transistor Tr 4  may be turned off when the falling voltage is input into the input terminal IN, and the transistor Tr 4  may be turned on after the falling voltage is input into the input terminal IN. In this case, it is possible to prevent the voltage (the source voltage of the transistor Tr 5 ) of the capacitive element C 1  from decreasing from V dd2  by the transistor Tr 3 . As a result, it is possible to cause the inverter circuit  1  to operate at a high speed. 
     In addition, in the embodiment and the modification described above, for example, although not illustrated, it is possible to delete the capacitive element C 2  in the inverter circuit  1 . Even in this case, it is possible to cause the inverter circuit  1  to operate at a higher speed. 
     Further, in the embodiment and the modification described above, the transistors Tr 1  to Tr 7  are formed by the n-channel MOS TFTs, but may be formed by p-channel MOS TFTs, for example. In this case however, the high voltage line V H  is replaced with the low voltage line L L , and the high voltage line V H  is replaced with the low voltage line L L . Furthermore, a transient response when the transistors Tr 1  to Tr 7  change (rise) from low to high and a transient response when the transistors Tr 1  to Tr 7  change (drop) from high to low are reversed. 
     &lt;Application Example&gt; 
       FIG. 13  illustrates an example of the entire configuration of a display device  100  that is one of application examples of the inverter circuit  1  according to each of the above-described embodiment and the modifications. This display device  100  includes, for example, a display panel  110  (display section) and a driving circuit  120  (drive section). 
     (Display Panel  110 ) 
     The display panel  110  includes a display area  110 A in which three kinds of organic EL elements  111 R,  111 G and  111 B emitting mutually different colors are arranged two-dimensionally. The display area  110 A is an area that displays an image by using light emitted from the organic EL elements  111 R,  111 G and  111 B. The organic EL element  111 R is an organic EL element that emits red light, the organic EL element  111 G is an organic EL element that emits green light, and the organic EL element  111 B is an organic EL element that emits blue light. Incidentally, in the following, the organic EL elements  111 R,  111 G and  111 B will be collectively referred to as an organic EL element  111  as appropriate. 
     (Display Area  110 A) 
       FIG. 14  illustrates an example of a circuit configuration within the display area  110 A, together with an example of a write-line driving circuit  124  to be described later. Within the display area  110 A, plural pixel circuits  112  respectively paired with the individual organic EL elements  111  are arranged two-dimensionally. In the present application example, a pair of the organic EL element  111  and the pixel circuit  112  configure one pixel  113 . To be more specific, as illustrated in  FIG. 12 , a pair of the organic EL element  111 R and the pixel circuit  112  configure one pixel  113 R for red, a pair of the organic EL element  111 G and the pixel circuit  112  configure one pixel  113 G for green, and a pair of the organic EL element  111 B and the pixel circuit  112  configure one pixel  113 B for blue. Further, the adjacent three pixels  113 R,  113 G and  113 B configure one display pixel  114 . 
     Each of the pixel circuits  112  includes, for example, a drive transistor Tr 100  that controls a current flowing in the organic EL element  111 , a write transistor Tr 200  that writes a voltage of a signal line DTL into the drive transistor Tr 100 , and a retention capacitor C s , and thus each of the pixel circuits  112  has a 2Tr1C circuit configuration. The drive transistor Tr 100  and the write transistor Tr 200  are each formed by, for example, an n-channel MOS Thin Film Transistor (TFT). The drive transistor Tr 100  or the write transistor Tr 200  may be, for example, a p-channel MOS TFT. 
     In the display area  110 A, plural write lines WSL (scanning line) are arranged in rows and plural signal lines DTL are arranged in columns. In the display area  110 A, further, plural power-source lines PSL (member to which the source voltage is supplied) are arranged in rows along the write lines WSL. Near a cross-point between each signal line DTL and each write line WSL, one organic EL element  111  is provided. Each of the signal lines DTL is connected to an output end (not illustrated) of a signal-line driving circuit  123  to be described later, and to either of the drain electrode and the source electrode (not illustrated) of the write transistor Tr 200 . Each of the write lines WSL is connected to an output end (not illustrated) of the write-line driving circuit  124  to be described later and to the gate electrode (not illustrated) of the write transistor Tr 200 . Each of the power-source lines PSL is connected to an output end (not illustrated) of a power-source-line driving circuit  125  to be described later, and to either of the drain electrode and the source electrode (not illustrated) of the drive transistor Tr 100 . Of the drain electrode and the source electrode of the write transistor Tr 200 , one (not illustrated) that is not connected to the signal line DTL is connected to the gate electrode (not illustrated) of the drive transistor Tr 100  and one end of the retention capacitor C s . Of the drain electrode and the source electrode of the drive transistor Tr 100 , one (not illustrated) that is not connected to the power-source line PSL and the other end of the retention capacitor C s  are connected to an anode electrode (not illustrated) of the organic EL element  111 . A cathode electrode (not illustrated) of the organic EL element  111  is connected to, for example, a ground line GND. 
     (Drive Circuit  120 ) 
     Next, each circuit within the drive circuit  120  will be described with reference to  FIG. 13  and  FIG. 14 . The drive circuit  120  includes a timing generation circuit  121 , a video signal processing circuit  122 , the signal-line driving circuit  123 , the write-line driving circuit  124  and the power-source-line driving circuit  125 . 
     The timing generation circuit  121  performs control so that the video signal processing circuit  122 , the signal-line driving circuit  123 , the write-line driving circuit  124  and the power-source-line driving circuit  125  operate in an interlocking manner. For example, the timing generation circuit  121  is configured to output a control signal  121 A to each of the above-described circuits, according to (in synchronization with) a synchronization signal  120 B input externally. 
     The video signal processing circuit  122  makes a predetermined correction to a video signal  120 A input externally, and outputs to the signal-line driving circuit  123  a video signal  122 A after the correction. As the predetermined correction, there are, for example, a gamma correction and an overdrive correction. 
     The signal-line driving circuit  123  applies, according to (in synchronization with) the input of the control signal  121 A, the video signal  122 A (signal voltage V sig ) input from the video signal processing circuit  122 , to each of the signal lines DTL, thereby performing writing into the pixel  113  targeted for selection. Incidentally, the writing refers to the application of a predetermined voltage to the gate of the drive transistor Tr 100 . 
     The signal-line driving circuit  123  is configured to include, for example, a shift resistor (not illustrated), and includes a buffer circuit (not illustrated) for each stage, corresponding to each column of the pixels  113 . This signal-line driving circuit  123  is able to output two kinds of voltages (V ofs , V sig ) to each of the signal lines DTL, according to (in synchronization with) the input of the control signal  121 A. Specifically, the signal-line driving circuit  123  supplies, via the signal line DTL connected to each of the pixels  113 , the two kinds of voltages (V ofs , V sig ) sequentially to the pixel  113  selected by the write-line driving circuit  124 . 
     Here, the offset voltage V ofs  is a constant value without relying on the signal voltage V sig . Further, the signal voltage V sig  is a value corresponding to the video signal  122 A. A minimum voltage of the signal voltage V sig  is a value lower than the offset voltage V ofs , and a maximum voltage of the signal voltage V sig  is a value higher than the offset voltage V ofs . 
     The write-line driving circuit  124  is configured to include, for example, a shift resistor (not illustrated), and includes a buffer circuit  5  for each stage, corresponding to each row of the pixels  113 . The buffer circuit  5  is configured to include plural inverter circuits  1  described above, and outputs, from an output end, a pulse signal approximately in the same phase as a pulse signal input into an input end. The write-line driving circuit  124  outputs two kinds of voltages (V dd , V ss ) to each of the write lines WSL, according to (in synchronization with) the input of the control signal  121 A. Specifically, the write-line driving circuit  124  supplies, via the write line WSL connected to each of the pixels  113 , the two kinds of voltages (V dd , V ss ) to the pixel  113  targeted for driving, and thereby controls the write transistor Tr 200 . 
     Here, the voltage V dd  is a value equal to or higher than an on-voltage of the write transistor Tr 200 . V dd  is the value of a voltage output from the write-line driving circuit  124  at the time of extinction or at the time of a threshold correction to be described later. V ss  is a value lower than the on-voltage of the write transistor Tr 200 , and also lower than V dd . 
     The power-source-line driving circuit  125  is configured to include, for example, a shift resistor (not illustrated), and includes, for example, a buffer circuit (not illustrated) for each stage, corresponding to each row of the pixels  113 . This power-source-line driving circuit  125  outputs two kinds of voltages (V ccH , V ccL ) according to (in synchronization with) the input of the control signal  121 A. Specifically, the power-source-line driving circuit  125  supplies, via the power-source line PSL connected to each of the pixels  113 , the two kinds of voltages (V ccH , V ccL ) to the pixel  113  targeted for driving, and thereby controls the light emission and extinction of the organic EL element  111 . 
     Here, the voltage V ccL  is a value lower than a voltage (V c1 +V ca ) that is the sum of a threshold voltage V c1  of the organic EL element  111  and a voltage V ca  of the cathode of the organic EL element  111 . Further, the voltage V ccH  is a value equal to or higher than the voltage (V c1 +V ca ). 
     Next, an example of the operation (operation from extinction to light emission) of the display device  100  according to the present application example will be described. In the present application example, in order that even when the threshold voltage V th  and the mobility μ of the drive transistor Tr 100  change over time, light emission luminance of the organic EL element  111  remains constant without being affected by these changes, correction operation for the change of the threshold voltage V th  and the mobility μ is incorporated. 
       FIG. 15  illustrates an example of the waveform of a voltage applied to the pixel circuit  112  and an example of the change in each of the gate voltage V g  and the source voltage V s  of the drive transistor Tr 100 . In Part (A) of  FIG. 15 , there is illustrated a state in which the signal voltage V sig  and the offset voltage V ofs  are applied to the signal line DTL. In Part (B) of  FIG. 15 , there is illustrated a state in which the voltage V dd  for turning on the write transistor Tr 200  and the voltage V ss  for turning off the write transistor Tr 200  are applied to the write line WSL. In Part (C) of  FIG. 15 , there is illustrated a state in which the voltage V ccH  and the voltage V ccL  are applied to the power-source line PSL. Further, in Part (D) and Part (E) of  FIG. 15 , there is illustrated a state in which the gate voltage V g  and the source voltage V s  of the drive transistor Tr 100  change over time in response to the application of the voltages to the power-source line PSL, the signal line DTL and the write line WSL. 
     (V th  Correction Preparation Period) 
     First, a Preparation for the V th  Correction is Made. Specifically, when the voltage of the write line WSL is V off , and the voltage of the power-source line PSL is V ccH  (in other words, when the organic EL element  111  is emitting light), the power-source-line driving circuit  125  reduces the voltage of the power-source line PSL from V ccH  to V ccL  (T 1 ). Then, the source voltage V s  becomes V ccL , and the organic EL element  111  stops emitting the light. Subsequently, when the voltage of the signal line DTL is V ofs , the write-line driving circuit  124  increases the voltage of the write line WSL from V off  to V on , so that the gate of the drive transistor Tr 100  becomes V ofs . 
     (First V th  Correction Period) 
     Next, the correction of V th  is performed. Specifically, while the write transistor Tr 200  is on, and the voltage of the signal line DTL is V ofs , the power-source-line driving circuit  125  increases the voltage of the power-source line PSL from V ccL  to V ccH  (T 2 ). Then, a current I ds  flows between the drain and the source of the drive transistor Tr 100 , and the source voltage V s  rises. Subsequently, before the signal-line driving circuit  123  switches the voltage of the signal line DTL from V ofs  to V sig , the write-line driving circuit  124  reduces the voltage of the write line WSL from V on  to V off (T 3 ). Then, the gate of the drive transistor Tr 100  enters a floating state, and the correction of V th  stops. 
     (First V th  Correction Stop Period) 
     In a period during which the V th  correction is stopped, in, for example, other row (pixel) different from the row (pixel) to which the previous correction is made, the voltage of the signal line DTL is sampled. At the time, in the row (pixel) to which the previous correction is made, the source voltage V s  is lower than V ofs −V th . Therefore, during the V th  correction stop period, in the row (pixel) to which the previous correction is made, the current I ds  flows between the drain and the source of the drive transistor Tr 100 , the source voltage V s  rises, and the gate voltage V g  also rises due to coupling via the retention capacitor C s , as well. 
     (Second V th  Correction Period) 
     Next, the V th  correction is made again. Specifically, when the voltage of the signal line DTL is V ofs  and the V th  correction is possible, the write-line driving circuit  124  increases the voltage of the write line WSL from V off  to V on , thereby causing the gate of the drive transistor Tr 100  to be V ofs  (T 4 ). At the time, when the source voltage V s  is lower than V ofs −V th  (when the V th  correction is not completed yet), the current I ds  flows between the drain and the source of the drive transistor Tr 100 , until the drive transistor Tr 100  is cut off (until a between-gate-and-source voltage V gs  becomes V th ). Subsequently, before the signal-line driving circuit  123  switches the voltage of the signal line DTL from V ofs  to V sig , the write-line driving circuit  124  reduces the voltage of the write line WSL from V on  to V off  (T 5 ). Then, the gate of the drive transistor Tr 100  enters a floating state and thus, it is possible to keep the between-gate-and-source voltage V gs  constant, regardless of the magnitude of the voltage of the signal line DTL. 
     Incidentally, during this V th  correction period, when the retention capacitor C s  is charged to V th , and the between-gate-and-source voltage V gs  becomes V th , the drive circuit  120  finishes the V th  correction. However, when the between-gate-and-source voltage V gs  does not reach V th , the drive circuit  120  repeats the V th  correction and the V th  correction stop, until the between-gate-and-source voltage V gs  reaches V th . 
     (Writing and μ Correction Period) 
     After the V th  correction stop period ends, the writing and the μ correction are performed. Specifically, while the voltage of the signal line DTL is V sig , the write-line driving circuit  124  increases the voltage of the write line WSL from V off  to V on  (T 6 ), and connects the gate of the drive transistor Tr 100  to the signal line DTL. Then, the gate voltage V g  of the drive transistor Tr 100  becomes the voltage V sig  of the signal line DTL. At the time, an anode voltage of the organic EL element  111  is still smaller than the threshold voltage V e1  of the organic EL element  111  at this stage, and the organic EL element  111  is cut off. Therefore, the current I ds  flows in an element capacitance (not illustrated) of the organic EL element  111  and thereby the element capacitance is charged and thus, the source voltage V s  rises by ΔV y , and the between-gate-and-source voltage V g , soon becomes V sig +V th −ΔV y . In this way, the μ correction is performed concurrently with the writing. Here, the larger the mobility μ of the drive transistor Tr 100  is, the larger ΔV y  is. Therefore, by reducing the between-gate-and-source voltage V g , by ΔV y  before light emission, variations in the mobility μ among the pixels  113  are removed. 
     (Light Emission Period) 
     Lastly, the write-line driving circuit  124  reduces the voltage of the write line WSL from V on  to V off  (T 7 ). Then, the gate of the drive transistor Tr 100  enters a floating state, the current I ds  flows between the drain and the source of the drive transistor Tr 100 , and the source voltage V s  rises. As a result, a voltage equal to or higher than the threshold voltage V e1  is applied to the organic EL element  111 , and the organic EL element  111  emits light of desired luminance. 
     In the display device  100  of the present application example, as described above, the pixel circuit  112  is subjected to on-off control in each pixel  113 , and the driving current is fed into the organic EL element  111  of each pixel  113 , so that holes and electrons recombine and thereby emission of light occurs, and this light is extracted to the outside. As a result, an image is displayed in the display area  110 A of the display panel  110 . 
     Incidentally, in the present application example, for example, the buffer circuit  5  in the write-line driving circuit  124  is configured to include the plural inverter circuits  1 . Therefore, there is almost no through current that flows in the buffer circuit  5  and thus, the power consumption of the buffer circuit  5  may be suppressed. In addition, since there are few variations in the output voltages of the buffer circuits  5 , it is possible to reduce the variations among the pixel circuits  112 , in terms of the threshold correction and the mobility correction of the drive transistor Tr 100  within the pixel circuit  112 , and moreover, variations in luminance among the pixels  113  may be reduced. 
     Further, in the inverter circuit  1 , only a single voltage line is provided on each of the low voltage side and the high voltage side and thus, there is no need to increase the withstand voltage of the inverter circuit  1  and also, it is possible to minimize an occupied area and thus, a narrower frame is realized. 
     The present invention has been described by using the embodiment, the modifications and the application example, but the present invention is not limited to the embodiment and like and may be variously modified. 
     For example, in the embodiment and the modifications described above, only a single voltage line is provided on each of the low voltage side and the high voltage side. However, for example, a voltage line connected to at least one of plural transistors on the high voltage side and a voltage line connected to other transistors on the high voltage side may not be a common line. Similarly, for example, a voltage line connected to at least one of plural transistors on the low voltage side and a voltage line connected to other transistors on the low voltage side may not be a common line. 
     For example, in the above-described application example, the inverter circuit  1  according to the above-described embodiment is used in the output stage of the write-line driving circuit  124 . However, this inverter circuit  1  may be used in an output stage of the power-source-line driving circuit  125 , instead of being used in the output stage of the write-line driving circuit  124 , or may be used in the output stage of the power-source-line driving circuit  125  in conjunction with the output stage of the write-line driving circuit  124 . 
     The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-085492 filed in the Japan Patent Office on Apr. 1, 2010, the entire content of which is hereby incorporated by reference. 
     It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.