Abstract:
Display panels capable of eliminating reliability issues due to high switching frequency. The display panel comprises a data driver outputting first, second, third and fourth data signals in sequence through a data line, a scan driver outputting first and second scan signals in sequence through first and second scan lines and an auxiliary driver generates first and second auxiliary signals in sequence, and first and second display cells commonly receives the first scan signal through the first scan line and receives the first and the second data signal through the data line, and a first switch is coupled to the data line and the second display cell, turning on and off in sequence according to the first auxiliary signal when the first scan signal is applied thereto such that the second and the first display cells receive the first and the second data signals in sequence.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to display devices, and in particular to a display panel capable of reducing number of data signal driving IC.  
         [0003]     2. Description of the Related Art  
         [0004]      FIG. 1  is a diagram showing a conventional display driving circuit  10 . It includes two data drivers  121  and  122 , a scan driver  11 , a pixel matrix comprising display cells  13 , and switches  161  and  162  comprising transistors. Each display cell  13  in the odd columns of the pixel matrix receives a data signal through a data line  151  from the data driver  121  or  122 . Each display cell  13  in the even columns of the pixel matrix receives a data signal through a data line  152  from the data driver  121  or  122 . The display cells  13  also receive scan signals through scan lines  14  from the scan driver  11 . To reduce number of the data drivers, data lines  151  and  152  are respectively coupled to the display cells  13  in the odd and even column of the pixel matrix share the same data terminal as the data driver through the switches  161  and  162  controlled by signals SW 1  and SW 2 . When one of the scan signals is applied, the odd and even display cells  13  in the scanned row of the matrix receive the data signal output from the same terminal of the data driver  121  or  122  by turns. In  FIG. 1 , for example, the number of the data drivers is half that when not using the switches to share the data terminals since each data terminal provides the data signals to two columns of display cells of the pixel matrix.  
         [0005]     However, in the conventional display driving circuit, the switching frequency of the switches  161  and  162  is n times the frame rate, wherein n is the number of the columns in the pixel matrix. For example, the switching frequency of the switches in a display having 768 pixel columns and a frame rate of 60 Hz is 46080 Hz. Such a switching frequency is much higher than that of the thin-film transistors (TFTs) used in the display cells  13 . Besides, the high duty ratio and high current stress also degrades the reliability of the circuit.  
       BRIEF SUMMARY OF THE INVENTION  
       [0006]     A detailed description is given in the following embodiments with reference to the accompanying drawings.  
         [0007]     Embodiments of display panels are provided, in which a data driver outputs first, second, third and fourth data signals in sequence through a data line, a scan driver outputs first and second scan signals in sequence through first and second scan lines and an auxiliary driver generates first and second auxiliary signals in sequence. First and second display cells receive the first scan signal through the first scan line simultaneously and receive the first and the second data signals through the data line respectively, and a first switch is coupled to the data line and the second display cell, turning on and off in sequence according to the first auxiliary signal when the first scan signal is applied thereto such that the second display cell receives the first data signal and the first display cell receives the second data signal in sequence.  
         [0008]     The invention also provides embodiments of a display panel, in which a data driver outputs first, second, third and fourth data signals in sequence through a data line, and first and second scan drivers output first and second scan signals in sequence through first and second scan lines. First and second display cells receive the first scan signal through the first scan line and the second scan line respectively and receive the first and the second data signal respectively through the data line simultaneously.  
         [0009]     The invention also provides embodiments of electronic device, in which the disclosed display system is applied and a power supply powers the display system to display images.  
         [0010]     The invention also provides embodiments of a driving method, in which a first auxiliary signal is applied to turn on a first switch such that a first data signal from a data line is transferred to first and second display cells and a first scan signal is applied to enable the first and the second display cells to receive the first data signal, during a first period. The first auxiliary signal is de-asserted to turn off the first switch such that the first display cell is electrically separated from the data line and the second display cell receives a second data signal from the data line according to the first scan signal, during a second period, in which the first switch is turned off until the first scan signal and the first auxiliary signal are applied at the same time again. A second auxiliary signal is applied to turn on a second switch such that a third data signal from the data line is transferred to third and fourth display cells and a second scan signal is applied to enable the third and the fourth display cells to receive the third data signal, during a third period. The second auxiliary signal is de-asserted to turn off the second switch such that the third display cell is electrically separated from the data line and the fourth display cell receives a fourth data signal from the data line according to the second scan signal, during a fourth period, in which the second switch is turned off until the second scan signal and the second auxiliary signal are applied at the same time again. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0012]      FIG. 1  shows a conventional display driving circuit;  
         [0013]      FIG. 2A  shows an embodiment of a display panel of the invention;  
         [0014]      FIG. 2B  is a timing chart of the display panel shown in  FIG. 2A ;  
         [0015]      FIG. 3A  shows another embodiment of display panel of the invention;  
         [0016]      FIG. 3B  is a timing chart of the display panel shown in  FIG. 3A ; and  
         [0017]      FIG. 4  is a schematic view showing an electronic device using display panels shown in  FIGS. 2A and 3A . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.  
         [0019]      FIG. 2A  is a diagram showing a display panel  200 A according to a first embodiment of the invention. It includes a data driver  21 , a scan driver  22 , an auxiliary driver  23 , a timing controller  24 , and a pixel matrix composed of six (for example) display cells P 1 ˜P 6 , and three switches ST 1 , ST 2  and ST 3 . For example, the display panel  200 A can be a liquid crystal display panel, a plasma display panel or an organic light emitting display panel, but is not limited thereto.  
         [0020]     The data driver  21  outputs the desired data signals (not shown) for the six display cells P 1 ˜P 6  through the data line DL. For example, the data driver  21  can be a data driving integrated circuit (IC) formed by single-crystal Si transistors, but is not limited thereto. The scan driver  22  outputs scan signals S 1 ˜S 3  in sequence through the scan lines SL 1 ˜SL 3 . For example, the scan driver  22  can also be a scan driving integrated circuit (IC) formed by single-crystal Si transistors. The auxiliary driver  23  outputs auxiliary signals SW 1 ˜SW 3  through auxiliary signal lines AL 1 ˜AL 3 . In the embodiment, the auxiliary driver  23  is a driving integrated circuit (IC) formed by a-Si transistors on the display panel rather than single-crystal Si transistors, and the data driver  21 , the scan driver  22  and the auxiliary driver  23  are controlled by the timing controller  24 .  
         [0021]     The display cells P 1  and P 2  receive the scan signal S 1  through the scan line SL 1  simultaneously, the display cells P 3  and P 4  receive the scan signal S 2  through the scan line SL 2  simultaneously, and the display cells P 5  and P 6  receive the scan signal S 3  through the scan line SL 3  simultaneously. The display cells P 1 , P 3  and P 5  receive corresponding data signals respectively through the data line DL simultaneously, the display cells P 2 , P 4  and P 6  coupled to the switches ST 1 , ST 2  and ST 3  respectively, receiving corresponding data signals respectively through the data line DL simultaneously. The switches ST 1 , ST 2  and ST 3  are coupled between the data line DL and the display cell P 2 , between the data line DL and the display cell P 4  and between the data line DL and the display cell P 6  respectively.  
         [0022]     As shown, the display cell P 1  comprises a transistor M 1  and a capacitor Cs 1 , the display cell P 2  comprises a transistor M 2  and a capacitor Cs 2 , and the display cells P 3 ˜P 6  are similar to the display cells P 1  and P 2 . Gates of the transistor M 1 , M 3  and M 5  are coupled to the scan lines SL 1 , SL 2  and SL 3  respectively, drains of which are coupled to the data line DL, and sources of which are coupled to capacitors Cs 1 , Cs 3  and Cs 5  respectively. Gates of the transistors M 2 , M 4  and M 6  are coupled to the scan lines SL 1 , SL 2  and SL 3  respectively, drains of which are coupled to the data line DL, and sources of which are coupled to capacitors Cs 2 , Cs 4  and Cs 6  respectively.  
         [0023]     The switches ST 1 ˜ST 3  are formed by transistors M 7 ˜M 9 , gates of the transistors M 7 ˜M 9  are coupled to the auxiliary signals SW 1 ˜SW 3  respectively, drains of which are coupled to the data line DL, sources of which are coupled to the display cells P 2 , P 4  and P 6  respectively. In the embodiment, the transistors M 1 ˜M 9  are a-Si transistors, but are not limited thereto.  
         [0024]      FIG. 2B  is a timing chart of the display panel shown in  FIG. 2A . The scan period when the scan signal S 1  is applied (the scan signal S 1  is asserted and has a logic high level) is divided into two sub-periods T 1  and T 2 . The auxiliary signal SW 1  turns on the transistor M 7  (closes the switch ST 1 ) and turns off the transistor M 7  (the switch ST 1  is opened) in sequence during the sub-periods T 1  and T 2  respectively, when the scan signal S 1  is applied.  
         [0025]     During the sub-period T 1 , during which the transistor M 7  is turned on, the display cell P 2  in the even column of the pixel matrix receives the data signal from the data driver  21  through the data line DL, and the display cell P 1  in the odd column of the pixel matrix receives the data signal from the data driver  21  through the data line DL during the sub-period T 2 , during which the transistor M 7  is turned off. For example, the data signal from the data driver  21  during the sub-period T 1  can be a data signal with a positive polarity, and the data signal from the data driver  21  during the sub-period T 2  can be a data signal with negative polarity, but are not limited thereto.  
         [0026]     It should be noted that the display cell P 1  can also receive the data signal for the display cell P 2  during sub-period T 1 , but the data signal received by the display cell P 1  is updated by the data signal on the data line DL during the sub-period T 2 . Further, during the period (T 1  and T 2 ), during which the scan signal S 1  is applied, the switch ST 1  only turns on and off once according to the auxiliary signal SW 1  until the scan signal S 1  is applied thereto again. Namely, the transistor M 7  is turned off during the sub-period T 2  and on again when the auxiliary signal SW 1  is applied thereto again.  
         [0027]     Next, when the scan signal S 1  is de-asserted and the scan signal S 2  is applied (has a logic high level), the transistors M 1 , M 2  and M 7  are turned off. The scan period when the scan signal S 2  is applied and divided into two sub-periods T 3  and T 4 . The auxiliary signal SW 2  turns on the transistor M 8  (closes the switch ST 2 ) and turns off the transistor M 8  (the switch ST 2  is opened) in sequence during the sub-periods T 3  and T 4  respectively, when the scan signal S 2  is applied.  
         [0028]     During the sub-period T 3 , during which the transistor M 8  is turned on, the display cell P 4  in the even column of the pixel matrix receives the data signal from the data driver  21  through the data line DL, and the display cell P 3  in the odd column of the pixel matrix receives the data signal from the data driver  21  through the data line DL during the sub-period T 4 , during which the transistor M 8  is turned off. For example, the data signal from the data driver  21  during the sub-period T 3  can be a data signal with a positive polarity, and the data signal from the data driver  21  during the sub-period T 4  can be a data signal with negative polarity, but are not limited thereto.  
         [0029]     It should be noted that the display cell P 3  can also receive the data signal for the display cell P 4  during sub-period T 3 , but the data signal received by the display cell P 3  is updated by the data signal on the data line DL during the sub-period T 4 . Further, during the period (T 3  and T 4 ), during which the scan signal S 2  is applied, the switch ST 2  only turns on and off once according to the auxiliary signal SW 2  until the scan signal S 2  is applied thereto again. Namely, the transistor M 8  is turned off during the sub-period T 4  and on again when the auxiliary signal SW 2  is applied thereto again.  
         [0030]     Similarly, when the scan signal S 2  is de-asserted and the scan signal S 3  is applied (has a logic high level), the transistors M 3 , M 4  and M 8  are turned off. The scan period when the scan signal S 3  is applied is divided into two sub-periods T 5  and T 6 . The auxiliary signal SW 3  turns on the transistor M 9  (closes the switch ST 3 ) and turns off the transistor M 9  (the switch ST 3  is opened) in sequence during the sub-periods T 5  and T 6  respectively, when the scan signal S 3  is applied.  
         [0031]     During the sub-period T 5 , during which the transistor M 9  is turned on, the display cell P 6  in the even column of the pixel matrix receives the data signal from the data driver  21  through the data line DL, and the display cell P 5  in the odd column of the pixel matrix receives the data signal from the data driver  21  through the data line DL during the sub-period T 6 , during which the transistor M 9  is turned off. For example, the data signal from the data driver  21  during the sub-period T 5  can be a data signal with a positive polarity, and the data signal from the data driver  21  during the sub-period T 6  can be a data signal with negative polarity, but are not limited thereto.  
         [0032]     It should be noted that the display cell P 5  can also receive the data signal for the display cell P 6  during sub-period T 5 , but the data signal received by the display cell P 5  is updated by the data signal on the data line DL during the sub-period T 6 . Further, during the period (T 5  and T 6 ), during which the scan signal S 3  is applied, the switch ST 3  only turns on and off once according to the auxiliary signal SW 3  until the scan signal S 3  is applied thereto again. Namely, the transistor M 9  is turned off during the sub-period T 6  and would be turned on again when the auxiliary signal SW 3  is applied thereto again.  
         [0033]     Namely, during a frame period, during which all the scan lines are scanned in sequence once, the auxiliary signals SW 1 ˜SW 3  are only applied in sequence once such that switches ST 1 ˜ST 3  are each switched once. Thus, the switching frequency of the switches ST 1 ˜ST 3  is lowered to the frame rate, which eliminates the reliability issue in the conventional display panel.  
         [0034]     The invention also provides a driving method for the display panel shown in  FIG. 2A .  
         [0035]     During a period T 1 , an auxiliary signal SW 1  is applied to turn on a switch ST 1  such that a data signal from a data line DL is transferred to display cells P 1  and P 2  and a scan signal S 1  is applied to enable the display cells P 1  and P 2  to receive the data signal on the data line DL.  
         [0036]     During a period T 2 , the auxiliary signal SW 1  is de-asserted to turn off the switch ST 1  such that the display cell P 2  is electrically separated from the data line DL and the display cell P 1  receives a data signal from the data line DL according to the scan signal S 1 , in which the witch ST 1  is turned off until the scan signal S 1  and the auxiliary signal SW 1  are applied thereto again.  
         [0037]     During a period T 3 , an auxiliary signal SW 2  is applied to turn on a switch ST 2  such that a data signal from the data line DL is transferred to display cells P 3  and P 4  and a scan signal S 2  is applied to enable the display cells P 3  and P 4  to receive the data signal on the data line DL.  10035 ] During a period T 4 , the auxiliary signal SW 2  is de-asserted to turn off the switch ST 2  such that the display cell P 4  is electrically separated from the data line DL and the display cell P 3  receives a data signal from the data line DL according to the scan signal S 2 , in which the switch ST 2  is turned off until the scan signal S 2  and the auxiliary signal SW 2  are applied thereto again.  
         [0038]     During a period T 5 , an auxiliary signal SW 3  is applied to turn on a switch ST 3  such that a data signal from the data line DL is transferred to display cells P 5  and P 6  and a scan signal S 3  is applied to enable the display cells P 5  and P 6  to receive the data signal on the data line DL.  
         [0039]     During a period T 6 , the auxiliary signal SW 3  is de-asserted to turn off the switch ST 3  such that the display cell P 6  is electrically separated from the data line DL and the display cell P 5  receives a data signal from the data line DL according to the scan signal S 3 , in which the switch ST 3  is turned off until the scan signal S 3  and the auxiliary signal SW 3  are applied thereto again.  
         [0040]     Namely, during a frame period, during which all the scan lines are scanned in sequence once, the auxiliary signals SW 1 ˜SW 3  are only applied in sequence once such that the switches are ST 1 ˜ST 3  each switched once. Thus, the switching frequency of the switches ST 1 ˜ST 3  is lowered to the frame rate, which eliminates the reliability issue in the conventional display panel.  
         [0041]      FIG. 3A  shows another embodiment of a display panel  200 B of the invention. It comprises a data driver  41 , two scan driver  42 A and  42 B, a timing controller  43 , and a pixel matrix composed of eight (for example) display cells P 21 ˜P 28 . For example, the display panel  200 B can be a liquid crystal display panel, a plasma display panel or an organic light emitting display panel, but it is not limited thereto.  
         [0042]     The data driver  41  outputs the desired data signals (not shown) for the eight display cells P 21 ˜P 28  through data lines DL 1  and DL 2 . For example, the data driver  41  can be a data driving integrated circuit (IC) formed by single-crystal Si transistors, but it is not limited thereto.  
         [0043]     The data driver  41 , the two scan drivers  42 A and  42 B are controlled by the timing controller  43 . For example, the timing controller  43  provides a first set of control signals such as clock signals CK 1  and /CK 1  and enabling signal DS 1  (as shown in  FIG. 3B ) /CK 2  to the scan driver  42 A and a second set of controls signals such as clock signals CK 2  and and enabling signal DS 2  (as shown in  FIG. 3B ) to the scan driver  42 B.  
         [0044]     The scan drivers  42 A and  42 B generate scan signals S 1 ˜S 4  in sequence according to the first and second sets of control signals, and the scan driver  42 A outputs the scan signals S 1  and S 3  through the scan lines SL 1  and SL 3  respectively and the scan driver  42 B outputs the scan signals S 2  and S 4  through the scan lines SL 2  and SL 4  respectively. Namely, the scan signals S 2  and S 4  are not generated according to the scan signals S 1  and S 3 , but generated by different scan drivers. In the embodiment, the scan driver  42 A and  42 B can also be a driving integrated circuit (IC) formed by a-Si transistors on the display panel rather than single-crystal Si transistors.  
         [0045]     The display cells P 21  and P 22  receive the scan signal S 1  through the scan line SL 1  simultaneously, the display cells P 23  and P 24  receive the scan signal S 2  through the scan line SL 2  simultaneously, the display cells P 25  and P 26  receive the scan signal S 3  through the scan line SL 3  simultaneously, and the display cells P 27  and P 28  receive the scan signal S 4  through the scan line SL 4  simultaneously. The display cells P 21 , P 23 , P 25  and P 27  receive corresponding data signals respectively through the data line DL 1  simultaneously, the display cells P 22 , P 24 , P 26  and P 28  receive corresponding data signals respectively through the data line DL 2  simultaneously.  
         [0046]     As shown, each display cell P 21 ˜P 28  comprises a transistor, a storage capacitor and a liquid element, and the transistors in the display cells P 21 ˜P 28  can be a-Si transistors, but are not limited thereto.  
         [0047]      FIG. 3B  is a timing chart of the display panel shown in  FIG. 3A . During a period T 21 , a scan signal S 1  is applied (the scan signal is asserted and has a logic high level), and the display cells P 21  and P 22  in the odd column of the pixel matrix receives the data signals from the data driver  41  through the data lines DL  1  and DL 2 .  
         [0048]     During a period T 22 , a scan signal S 2  is applied, and the display cells P 23  and P 24  in the even column of the pixel matrix receives the data signals from the data driver  41  through the data lines DL 1  and DL 2 .  
         [0049]     During a period T 23 , a scan signal S 3  is applied, and the display cells P 25  and P 26  in the odd column of the pixel matrix receive the data signals from the data driver  41  through the data lines DL 1  and DL 2 .  
         [0050]     During a period T 24 , a scan signal S 4  is applied, and the display cells P 27  and P 28  in the even column of the pixel matrix receive the data signals from the data driver  41  through the data lines DL 1  and DL 2 . For example, the data signals output from the data driver  41  during the periods T 21  and T 23  can be data signals with a positive polarity and that output from the data driver  41  during the period T 22  and T 24  can be data signals with a negative polarity, but are not limited thereto.  
         [0051]     Namely, all scan lines of the display panel  200 B are scanned in sequence by the scan drivers  42 A and  42 B, and display cells in two columns share one data line to receive data signals from the data driver. As the switching frequency of the switches ST 1 ˜ST 3  is lowered to the frame rate, the reliability issue in the conventional display panel can be eliminated.  
         [0052]      FIG. 4  is a schematic view showing an electronic device using display systems shown in  FIG. 2A and 3A . As shown, the electronic device  300  comprises a housing  210 , the display panel  200 A/ 200 B, and power supply  220 . The power supply  220  is operationally coupled to the display panels  200 A/ 200 B to powers the display panel  200 A/ 200 B to display images. For example, the display panel  200 A/ 200 B can be a liquid crystal display panel, a plasma display panel or an organic light emitting display panel, and the electronic device  300  can be a PDA, a display monitor, a notebook computer, a table computer or a cellular phone.  
         [0053]     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.