Abstract:
An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Description:
[0001]    This is a continuation of U.S. patent application Ser. No. 11/190,956, filed on Jul. 28, 2005, which, in turn, relies for priority on Japanese Patent Application No. 2004-220744 filed Jul. 28, 2004, the contents of both of which are incorporated herein by reference in their entireties. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to an interrupt handling technique of an information processing apparatus such as a personal computer. 
         [0004]    2. Background Art 
         [0005]    In recent years, various types of personal computers such as a desktop personal computer and a notebook personal computer have come into widespread use. In this kid of personal computer, various programs are executed in sequence for each predetermined processing unit; interrupt management is conducted to interrupt the processing being executed and execute processing with higher priority. SMI (system management interrupt) is available as one interrupt management. 
         [0006]    The SMI is an interrupt for causing BIOS (basic input/output system) to perform system proper processing (SMI processing) when a predetermined event (SMI event) occurs in the system; the SMI is started as an SMI signal is supplied to a CPU. (For example, refer to U.S. Pat. No. 6,446,153). 
         [0007]    Accordingly, it is made possible to perform flexible operation control in such a manner that the processing mode is instantly switched from usual processing of an application program to special processing of the system in response to pressing a function key on a keyboard, for example. 
         [0008]    By the way, recently it has been a common practice to install an SMI signal line for supplying an SMI signal to a CPU in a controller for interconnecting system buses (south bridge (SB)) because the controller is provided with a timeout notification function, etc., and the timeout is defined as an SMI event. Therefore, a notification of SMI event occurrence from an embedded controller (EC) is transmitted via the controller to the CPU. 
         [0009]    On the other hand, recently the embedded controller has been a multifunctional device having both a power supply controller function and a keyboard controller function, for example, and each function can become the cause of an SMI. Accordingly, it becomes necessary for a BIOS processing section of BIOS operated when an SMI signal is supplied to the CPU to not only access the south bridge, but also access the embedded controller to determine the SMI cause. The reason is that the south bridge cannot determine the SMI event associated with which function has occurred although the south bridge can determine that a notification is received from the embedded controller. However, the embedded controller is connected to a low-speed system bus at a comparatively low stage with respect to the system and thus the responsivity of SMI processing performed by the BIOS is degraded. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The present invention may be more readily described with reference to the accompanying drawings: 
           [0011]      FIG. 1  is a block diagram to show the schematic configuration of a computer according to an embodiment of the invention; 
           [0012]      FIG. 2  is a block diagram to show the configuration of EC/KBC installed in the computer according to the embodiment of the invention; 
           [0013]      FIG. 3  is a drawing to show SMI event occurrence notification signal lines laid between the EC/KBC and an SB included in the computer according to the embodiment of the invention; and 
           [0014]      FIG. 4  is a flowchart to show the operation principle of SMI processing executed by the computer according to the embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0015]    Referring now to the accompanying drawings, there is shown a preferred embodiment of the invention. 
         [0016]      FIG. 1  is a block diagram to show the schematic configuration of a computer according to an embodiment of the invention. The computer is a notebook personal computer that can be operated with a battery, for example, and a CPU bus  1 , a memory bus  2 , a VGA bus  3 , a hub link  4 , a PCI bus  5 , and an LPC bus  6  are laid as shown in  FIG. 1 . 
         [0017]    An NB (north bridge)  12  is connected to a CPU  11  for controlling the whole computer via the CPU bus  1 . The NB  12  is a controller for connecting the CPU bus  1 , the memory bus  2 , the VGA bus  3 , and the hub link  4 , and controls comparatively high-speed devices such as memory  13  and a VGA controller  14 . 
         [0018]    An SB (south bridge)  15  connected to the NB  12  via the hub link  4  is a controller for connecting the hub link  4 , the PCI bus  5 , and the LPC bus  6  and controls comparatively low-speed devices such as device controllers  16   a  and  16   b , an EC/KBC  18 , and a BIOS-ROM  19 . The SB  15  has a timer function and can send a timeout notification to the CPU  11  every specified time, for example. To make a notification of the timeout as SMI event occurrence, the SB  15  is provided with an SMI signal line to connect to the CPU  11 . The device controller  16   a  controls an incorporated device  17   a  and the device controller  16   b  controls an expansion-type external device  17   b.    
         [0019]    The EC/KBC  18  is a multifunctional device having both a function of transmitting keyboard operation to the CPU  11  and a function of controlling a power supply control circuit and a battery. These two functions can become each the cause of an SMI. Thus, the EC/KBC  18  is provided with a signal line to connect to the SB  15  (to send a notification of SMI event occurrence to the CPU  11  via the SB  15 ). If a notification of SMI event occurrence is sent from the SB  15  to the CPU  11 , the computer of the embodiment is designed to be able to rapidly determine whether or not an SMI event associated with the EC/KBC  18  has occurred as the system. This point will be discussed below in detail: An SMI processing section of BIOS determines the SMI cause. When the computer is started, the BIOS is loaded into the memory  13  from the BIOS-ROM  19  and is controlled by the CPU  11  for execution. 
         [0020]      FIG. 2  is a block diagram to show the configuration of the EC/KBC  18 . As shown in  FIG. 2 , the EC/KBC  18  has a KBC section  181  and an EC section  182 . 
         [0021]    The KBC section  181  provides the function of transmitting user&#39;s operation of a KB (keyboard)  20  to the CPU  11 . When the user presses a special key such as a function key of keys provided on the KB  20 , the KBC section  181  outputs a KBSMI signal indicating occurrence of an SMI event to a dedicated signal line. 
         [0022]    The EC section  182  provides a function of controlling a PSC (power supply control circuit)  21  and a BATT (battery)  22 . For example, if the BATT  22  enters a low battery state, etc., the EC section  182  outputs an ECSMI signal indicating occurrence of an SMI event to a dedicated signal line. 
         [0023]    That is, from the EC/KBC  18 , the signal line for SMI event occurrence notification is derived for each function that can become an SMI cause. These signal lines are introduced into the SB  15  as shown in  FIG. 3 . Upon reception of a notification of SMI event occurrence from at least one signal line, the SB  15  holds information indicating whether or not a KBSMI signal or an ECS signal is received in an internal register, and supplies an SMI signal to the CPU  11  (SMI assert). In the example in  FIG. 3 , the SB  15  holds information indicating the value of GPI013 upon reception of a KBSMI signal and information indicating the value of GPI08 upon reception of an ECS signal (can hold both the values, of course). 
         [0024]    In the CPU  11  to which the SMI signal is supplied, the SMI processing section of the BIOS is started and determines the SMI cause. At this time, the SMI processing section of the BIOS accesses the SB  15  via the hub link  4  and checks whether or not the SB  15  causes an SMI event such as a timeout to occur, and also references the internal register of the SB  15  to check whether or not the KBC section  181  or the EC section  182  of the EC/KBC  18  makes an SMI event occurrence notification (whether or not information indicating the value of GPI013 or GPI08 is held). 
         [0025]    That is, in the computer, whether or not an SMI event of each function of the EC/KBC  18  (multifunctional device) has occurred can be checked by accessing the SB  15  connected to the hub link  4  access to which is complete in about 50 ns without accessing the EC/KBC  18  connected to the LPC bus  6  it takes about 1 μs in accessing. Accessing the SB  15  is essentially required because the SB  15  can become an SMI cause. Thus, from the viewpoint from the SMI processing section of the BIOS, accessing the EC/KBC  18  via the LPC bus  6  is only deleted and additional access does not occur. Addition of a new device, etc., does not occur either from the viewpoint of the hardware. Thus, the computer makes it possible to enhance the responsivity of the SMI processing without the need for adding a new device, etc. 
         [0026]    Checking whether or not an SMI event associated with the EC/KBC  18  has occurred is a necessary item each time an SMI signal is supplied to the CPU  11  regardless of whether or not the EC/KBC  18  is an SMI cause. Thus, if the responsivity of the SMI processing is enhanced, the responsivity of the whole system can be enhanced dramatically. 
         [0027]    Next, the operation principle of the SMI processing executed by the computer will be discussed with reference to  FIG. 4 . 
         [0028]    When an SMI event occurs, an SMI signal is supplied from the SB  15  to the CPU  11  (step S 1 ). Upon reception of the supplied SMI signal, the CPU  11  starts the SMI processing section of the BIOS (step S 2 ). 
         [0029]    On the other hand, the started SMI processing section of the BIOS first accesses the SB  15  via the Hub link  4  of the high-speed bus for checking the SMI cause (step S 3 ). At this time, the SMI processing section of the BIOS also references the internal register of the SB  15  to check whether or not an SMI event of each function of the EC/KBC  18  (multifunctional device) connected to the LPC bus  6  of the low-speed bus has occurred. When the SMI processing section of the BIOS recognizes the SMI cause, it executes processing corresponding to the cause (step S 4 ). 
         [0030]    As described above, in the computer, the SMI event occurrence notification signal lines from the multifunctional device are provided in a one-to-one correspondence with the functions and are connected to the SB and whether or not an SMI event associated with the multifunctional device has occurred can be determined in the SB, so that the responsivity of the SMI processing can be enhanced. 
         [0031]    It is to be understood that the invention is not limited to the specific embodiment described above and that the invention can be embodied with the components modified without departing from the spirit and scope of the invention. The invention can be embodied in various forms according to appropriate combinations of the components disclosed in the embodiment described above. For example, some components may be deleted from all components shown in the embodiment. Further, the components in different embodiments may be used appropriately in combination.