Abstract:
A differential amplifier layout includes a current mirror having a first transistor, a second transistor, and a third transistor. The current mirror receives a first power supply through the first transistor. The second transistor is part of a reference current branch and the third transistor is part of a mirror current branch. The first transistor comprises a first group of fingers disposed adjacent one side of the second transistor and a second group of fingers disposed adjacent one side of the third transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2010-0095727 filed on Oct. 1, 2010, the disclosure of which is incorporated by reference in its entirety herein. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Embodiments of the present inventive concept relate to a differential amplifier, and more particularly, to a layout method for a differential amplifier. 
         [0004]    2. Discussion of Related Art 
         [0005]    A transistor is a semiconductor device that can be used to amplify and switch electronic signals. A transistor typically includes at least three terminals. A voltage or current applied to one pair of the terminals may change the current flowing through another pair of the terminals. 
         [0006]    A gate terminal of a multi-finger transistor includes a plurality of fingers arranged in parallel to one another on an active region. A plurality of source regions and a plurality of drain regions are alternately arranged in the active region among the plurality of fingers. When multi-finger transistors are manufactured, a dummy transistor is inserted to ensure uniform etching of the outermost transistors. 
       SUMMARY 
       [0007]    According to an exemplary embodiment of the present inventive concept, a differential amplifier layout includes a current mirror, which is connected to a first power supply through a first transistor and which includes a second transistor for forming a reference current branch and a third transistor for forming a mirror current branch. A gate of the first transistor may include a plurality of first fingers. A first group of fingers among the plurality of first fingers may be disposed at one side of the second transistor and a second group of fingers among the plurality of first fingers may be disposed at one side of the third transistor. 
         [0008]    The plurality of first fingers may further include a third group of fingers disposed between the first transistor and the second transistor. The number of fingers in the first group may be the same as the number of fingers in the second group. The number of fingers in each of the first through third groups may be an even number. 
         [0009]    The differential amplifier layout may further include a pair of transistors which are connected to a second power supply through a fourth transistor and which include a fifth transistor connected to the reference current branch and a sixth transistor connected to the mirror current branch. A gate of the fourth transistor may include a plurality of second fingers. A third group of fingers among the plurality of second fingers may be disposed at one side of the fifth transistor and a fourth group of fingers among the plurality of second fingers may be disposed at one side of the sixth transistor. 
         [0010]    The plurality of second fingers may further include a fifth group of fingers disposed between the fifth transistor and the sixth transistor. The number of fingers in the third group may be the same as the number of fingers in the fourth group. The number of fingers in each of the third through fifth groups may be an even number. 
         [0011]    According to an exemplary embodiment of the present inventive concept, a layout method for a differential amplifier includes disposing a first transistor and a second transistor which form a current mirror and disposing a third transistor which includes a plurality of first fingers and provides a first voltage to a common node of the first transistor and the second transistor in response to a first control signal. 
         [0012]    The disposing of the third transistor may include disposing a first group of fingers among the plurality of first fingers at one side of the first transistor and disposing a second group of fingers among the plurality of first fingers at one side of the second transistor. The disposing the third transistor may further include disposing a third group of fingers among the plurality of first fingers between the first transistor and the second transistor. 
         [0013]    The number of fingers in the first group may be the same as the number of fingers in the second group. The number of fingers in each of the first through third groups may be an even number. 
         [0014]    The layout method may further include disposing a fourth transistor and a fifth transistor which amplify differential input signals and disposing a sixth transistor which includes a plurality of second fingers and provides a second voltage to a common node of the fourth transistor and the fifth transistor in response to a second control signal. 
         [0015]    The disposing of the sixth transistor may include disposing a third group of fingers among the plurality of second fingers at one side of the fourth transistor and disposing a fourth group of fingers among the plurality of second fingers at one side of the fifth transistor. 
         [0016]    According to an exemplary embodiment of the inventive concept a differential amplifier layout includes a current mirror having a first transistor, a second transistor, and a third transistor. The current mirror receives a first power supply through the first transistor. The second transistor is part of a reference current branch and the third transistor is part of a mirror current branch. A gate region of the first transistor includes a first group of fingers disposed adjacent one side of the second transistor and a second group of fingers disposed adjacent one side of the third transistor. 
         [0017]    According to an exemplary embodiment of the inventive concept, a layout method for a differential amplifier includes forming a first transistor and a second transistor in a layout area, forming a first group of fingers adjacent one side of the first transistor in the layout area, and forming a second group of fingers adjacent one side of the second transistor in the layout area. A third transistor is formed from the first and second group of fingers. The third transistor is configured to provide a first voltage to a common node of the first transistor and the second transistor in response to a first control signal. The first, second, and third transistors form a current mirror. 
         [0018]    According to an exemplary embodiment of the inventive concept, a differential amplifier includes first, second, and third multi-finger transistors. A gate terminal of the first multi-finger transistor receives a first signal of a pair of differential signals. A gate terminal of the second multi-finger transistor receives the other signal of the pair. The third multi-finger transistor is commonly connected to both the first and second multi-finger transistors to provide them a first supply voltage in response to a first control signal. First fingers of the third transistor are disposed to the left of the first transistor, and second other fingers of the third transistor are disposed to the right of the second transistor. 
         [0019]    Third fingers of the third transistor other than the first and second fingers may be disposed between the first and second transistors. The differential amplifier may further include a current mirror connected between a second supply voltage and the first and second multi-finger transistors. The current mirror may include fourth, fifth, and sixth multi-finger transistors. The fourth multi-finger transistor receives the second supply voltage in response to a second control signal. The fourth multi-finger transistor is commonly connected to the fifth and sixth multi-finger transistors. First fingers of the fourth multi-finger transistor may be disposed to the left of the fifth transistor and second other fingers of the fourth multi-finger transistor may be disposed to the right of the sixth transistor. Third fingers of the fourth transistor other than the first and second fingers may be disposed between the fifth and sixth transistors. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
           [0021]      FIG. 1  is a circuit diagram of a differential amplifier according to an exemplary embodiment of the present inventive concept; 
           [0022]      FIG. 2  is a layout of the differential amplifier illustrated in  FIG. 1  according to an exemplary embodiment of the present inventive concept; 
           [0023]      FIG. 3  is a layout of the differential amplifier illustrated in  FIG. 1  according to an exemplary embodiment of the present inventive concept; and 
           [0024]      FIG. 4  is a flowchart of a layout method for a differential amplifier according to an exemplary embodiment of the present inventive concept. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    The present inventive concept now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments thereof are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. 
         [0026]    It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. 
         [0027]      FIG. 1  is a circuit diagram of a differential amplifier  10  according to an exemplary embodiment of the present inventive concept. Referring to  FIG. 1 , the differential amplifier  10  includes a current mirror  20  and an amplifier  30 . 
         [0028]    The current mirror  20  includes a first transistor T 1 , a second transistor T 2 , and a third transistor T 3 . The first transistor T 1  supplies a first power supply VDD to a first node ND 1  (e.g., a common node of the second transistor T 2  and the third transistor T 3 ) in response to a first control signal Vcs 1 . For example, the first control signal Vcs 1  is applied to a gate terminal GP 1  of the first transistor T 1 . The first transistor T 1  that may function as a current source. The first transistor T 1  may be implemented by a P-type metal-oxide-semiconductor (PMOS) transistor, as an example. 
         [0029]    The second transistor T 2  receives the first power supply VDD through the first transistor T 1 , which forms a reference current branch. The third transistor T 3  receives the first power supply VDD through the first transistor T 1 , which forms a mirror current branch. A gate terminal GP 2  of the second transistor T 2  and a gate terminal GP 3  of the third transistor T 3  are connected to a second node ND 2 . 
         [0030]    The amplifier  30  includes a fourth transistor T 4 , a fifth transistor T 5 , and a sixth transistor T 6 . The fourth transistor T 4  supplies a second power supply VSS (e.g., a ground voltage) to a third node ND 3  (e.g., a common node of the fifth transistor T 5  and the sixth transistor T 6 ) in response to a second control signal Vcs 2 . For example, the second control signal Vcs 2  may be applied to a gate terminal GP 4  of the fourth transistor T 4 . The fourth transistor T 4  that may function as a current source. The fourth transistor T 4  may be implemented by an N-type metal-oxide-semiconductor (NMOS) transistor, as an example. 
         [0031]    The fifth transistor T 5  and the sixth transistor T 6  make a pair and amplify a difference between differential input voltages V 1  and V 2  and output an output voltage Vout. The input voltage V 1  may be applied to a gate terminal GP 5  of the fifth transistor T 5  and the input voltage V 2  may be applied to a gate terminal GP 6  of the sixth transistor T 6 . The input voltages V 1  and V 2  may be complementary voltages. A drain of the fifth transistor T 5  and a drain of the second transistor T 2  are connected to the second node ND 2  in common. A drain of the third transistor T 3  and a drain of the sixth transistor T 6  are connected in common to a node through which the output voltage Vout is output. In other words, the drain of the fifth transistor T 5  is connected to the reference current branch and the drain of the sixth transistor T 6  is connected to the mirror current branch. The second and third transistors T 2  and T 3  may be implemented by PMOS transistors and the fifth and sixth transistors T 5  and T 6  may be implemented by NMOS transistors, as an example. 
         [0032]      FIG. 2  is a layout of the differential amplifier  10  illustrated in  FIG. 1  according to an exemplary embodiment of the present inventive concept. Referring to  FIGS. 1 and 2 , according to an exemplary embodiment of the invention, each of the transistors T 1  through T 6  is implemented by a multi-finger transistor. 
         [0033]    In the multi-finger transistor, a plurality of fingers disposed in parallel on an active region AR form gate regions, and a plurality of source regions S and a plurality of drain regions D are alternately disposed in the active region AR among the fingers. The first transistor T 1  among the transistors T 1  through T 6  is formed from a first region T 1  a and a second region T 1   b, which may be separate from one another. The fourth transistor T 4  is formed from a third region T 4   a  and a fourth region T 4   b,  which may be separate from one another. 
         [0034]    According to at least one exemplary embodiment of the inventive concept, the number of fingers within a gate region GP 11  in the first region T 1   a  may be the same as the number of fingers within a gate region GP 12  in the second region T 1   b . In addition, the number of fingers within a gate region GP 41  in the third region T 4   a  may be the same as the number of fingers within a gate region GP 42  in the fourth region T 4   b.  According to an exemplary embodiment of the inventive concept, an even number of fingers is present in each of the gate regions GP 11 , GP 12 , GP 41 , and GP 42 . Fingers included in gate regions GP 11 , GP 12 , GP 2 , GP 3 , GP 41 , GP 42 , GP 5 , and GP 6  are disposed on the active region AR and the source regions S and the drain regions D are formed in the active region AR among the fingers. 
         [0035]    A plurality of drain regions D in the first and second regions T 1   a  and T 1   b , a plurality of source regions S of the second transistor T 2 , and a plurality of source regions S of the third transistor T 3  may be connected to the first node ND 1  through metal contacts MC of a first wiring BP 1 . A plurality of drain regions D and the gate region GP 2  of the second transistor T 2 , the gate region GP 3  of the third transistor T 3 , and a plurality of drain regions D of the fifth transistor T 5  may be connected to the second node ND 2  through metal contacts MC of a second wiring BP 2 . A plurality of drain regions D of the sixth transistor T 6  may be connected to a plurality of drain regions D of the third transistor T 3  through metal contacts MC of a third wiring BP 3 . A plurality of source regions S of the fifth transistor  15 , a plurality of source regions S of the sixth transistor T 6 , and a plurality of drain regions D in the third and fourth regions T 4   a  and T 4   b  may be connected to the third node ND 3  through metal contacts MC of a fourth wiring BP 4 . 
         [0036]    In at least one embodiment of the inventive concept, a region forming the first transistor T 1  is divided into the two separate regions T 1   a  and T 1   b . The first region T 1   a  is disposed to the left of the second transistor T 2  and the second region T 1   b  is disposed to the right of the third transistor T 3 . Since the first transistor T 1  is divided into the first and second regions T 1   a  and T 1   b , dummy transistors are not necessary. A region forming the fourth transistor T 4  is divided into the two regions T 4   a  and T 4   b,  which are respectively disposed to the left of the fifth transistor  15  and to the right of the sixth transistor T 6 . Since the fourth transistor T 4  is divided into the third and fourth regions T 4   a  and T 4   b , dummy transistors are not necessary. Consequently, the differential amplifier  10  having the layout illustrated in  FIG. 2  does not need separate dummy transistors, so that parasitic resistance and the size of the differential amplifier  10  may be reduced. 
         [0037]      FIG. 3  is a layout of the differential amplifier  10  illustrated in  FIG. 1  according to an exemplary embodiment of the present inventive concept. Referring to  FIGS. 1 and 3 , according to an exemplary embodiment of the inventive concept, each of the transistors T 1  through T 6  is implemented by a multi-finger transistor. 
         [0038]    The first transistor T 1  is divided into a fifth region T 1   a , a sixth region T 1   b , and a seventh region T 1   c . The fourth transistor T 4  is divided into an eighth region T 4   a,  a ninth region T 4   b,  and a tenth region T 4   c.  In other words, each of the first and fourth transistors T 1  and T 4  is divided into three regions. 
         [0039]    According to at least one embodiment of the inventive concept, the total number of fingers within a gate region GP 12  in the sixth region T 1   b  may be the same as the total number of fingers within a gate region GP 13  in the seventh region T 1   c . In addition, the total number of fingers within a gate region GP 42  in the ninth region T 4   b  may be the same as the total number of fingers within a gate region GP 43  in the tenth region T 4   c.  According to an exemplary embodiment of the inventive concept, the total number of fingers in each of gate regions GP 11 , GP 12 , GP 13 , GP 41 , GP 42 , and GP 43  may be an even number. 
         [0040]    Each of gate regions GP 11 , GP 12 , GP 13 , GP 2 , GP 3 , GP 41 , GP 42 , GP 43 , GP 5 , and GP 6  are disposed on an active region AR. Source regions S and drain regions D are formed in the active region AR among fingers included in the gate regions GP 11 , GP 12 , GP 13 , GP 2 , GP 3 , GP 41 , GP 42 , GP 43 , GP 5 , and GP 6 . 
         [0041]    A plurality of drain regions D in each of the regions T 1   a , T 1   b , and T 1   c , a plurality of source regions S of the second transistor T 2 , and a plurality of source regions S of the third transistor T 3  may be connected to the first node ND 1  through metal contacts MC of a first wiring BP 1 . A plurality of drain regions D and the gate region GP 2  of the second transistor T 2 , the gate region GP 3  of the third transistor T 3 , and a plurality of drain regions D of the fifth transistor T 5  may be connected to the second node ND 2  through metal contacts MC of a second wiring BP 2 . A plurality of drain regions D of the sixth transistor T 6  are connected to a plurality of drain regions D of the third transistor T 3  through metal contacts MC of a third wiring BP 3 . A plurality of source regions S of the fifth transistor T 5 , a plurality of source regions S of the sixth transistor T 6 , and a plurality of drain regions D in the regions T 4   a,  T 4   b,  and T 4   c  may be connected to the third node ND 3  through metal contacts MC of a fourth wiring BP 4 . 
         [0042]    In at least one embodiment of the inventive concept, a region forming the first transistor T 1  is formed from the three separate regions T 1   a , T 1   b , and T 1   c . The fifth region T 1   a  is disposed between the second transistor T 2  and the third transistor T 3 . The sixth region T 1   b  is disposed to the left of the second transistor T 2  and the seventh region T 1   c  is disposed to the right of the third transistor T 3 . Since the region forming the first transistor T 1  is divided into the first, second and third regions T 1   a , T 1   b , and T 1   c , dummy transistors are not necessary. In addition, a region forming the fourth transistor T 4  is divided into the three regions T 4   a,  T 4   b,  and T 4   c.  The eighth region T 4   a  is disposed between the fifth transistor T 5  and the sixth transistor T 6 . The ninth region T 4   b  is disposed to the left of the fifth transistor T 5  and the tenth region T 4   c  is disposed to the right of the sixth transistor T 6 . Since the region forming the fourth transistor T 4  is divided into the eighth, ninth and tenth regions T 4   a,  T 4   b,  and T 4   c,  dummy transistors are not necessary. 
         [0043]      FIG. 4  is a flowchart of a layout method for a differential amplifier according to an exemplary embodiment of the present inventive concept. The method illustrated in  FIG. 4  may be used to construct the layout of the differential amplifier  10  illustrated in  FIG. 2 . Referring to  FIGS. 1 ,  2 , and  4 , the gate regions GP 2  and GP 3  including a plurality of fingers are disposed on the active region AR to form the second transistor T 2  and the third transistor T 3  in operation S 10 . The first region T 1   a  of the first transistor T 1  is disposed to the left of the second transistor T 2  and the second region T 1   b  of the first transistor T 1  is disposed to the right of the third transistor T 3  in operation S 30 . The gate regions GP 5  and GP 6  including a plurality of fingers are disposed on the active region AR to form the fifth transistor T 5  and the sixth transistor T 6  in operation S 50 . The third region T 4   a  of the fourth transistor T 4  is disposed to the left of the fifth transistor T 5  and the fourth region T 4   b  of the fourth transistor T 4  is disposed to the right of the sixth transistor T 6  in operation S 70 . The operations S 10  through S 70  are separately defined for clarity of the description and may be simultaneously or sequentially performed. 
         [0044]    As described above, according to at least one embodiment of the present inventive concept, a current source transistor is formed in at least two separate regions to function as dummy transistors in the layout of a differential amplifier, so that the insertion of separate dummy transistors is not necessary. 
         [0045]    While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in forms and details may be made therein without departing from the spirit and scope of the present disclosure.