Abstract:
A modular-based, zero-current-switched (ZCS), isolated full-bridge boost converter with multiple inputs is disclosed. Each converter module is used to match the connected input source and control the amount of power drawn from the source. The power from various sources are combined together and delivered to the load through a multiphase transformer. The input inductor of each boost-derived converter module keeps the input current constant and acts as a current source to drive the multiphase transformer through a phase-shifted-controlled full bridge converter. By connecting an auxiliary circuit across the full-bridge input in each module, the transformer leakage inductance and output capacitance of the switching devices are used to create resonant paths for facilitating zero-current-switching of all switching devices.

Description:
FIELD 
     The present disclosure relates to multi-input (and single-input) DC/DC converters with zero-current-switching. 
     BACKGROUND 
     The statements in this section merely provide background information related to the present disclosure and may not constitute prior art. 
     Various DC/DC converters are known in the art for supplying dc power to loads, including multi-input DC/DC converters that can combine energy from multiple dc power input sources. Many of these converters incorporate full bridge converters having switches. Ideally, these switches would be turned on or off under zero-current conditions (so-called zero-current-switching) to minimize switching losses. Many existing converters are, however, incapable of achieving zero-current-switching of the main switches during both switching transitions. As a result, such converters suffer from switching losses that reduce the overall efficiency of the DC/DC converter. 
     SUMMARY 
     According to one example of the present disclosure, a multi-input dc/dc converter includes a plurality of input modules, a transformer, at least one output terminal for supplying dc power to a load, and a rectifier circuit. Each input module includes at least one input terminal for coupling to a dc power source and a full bridge converter having a plurality of main switches. The transformer has a plurality of primary windings and at least one secondary winding. Each primary winding is coupled to one of the full bridge converters. The rectifier circuit is coupled between the secondary winding of the transformer and the output terminal. Each input module further includes an auxiliary circuit coupled to the full bridge converter for achieving substantially zero-current-switching of the main switches during turn-on and turn-off of the main switches. 
     According to another example of the present disclosure, a multi-input DC/DC converter includes a plurality of input modules, a transformer having a plurality of primary windings and at least one secondary winding, at least one output terminal for supplying dc power to a load, and a rectifier circuit coupled between the secondary winding of the transformer and said output terminal. Each input module includes at least one input terminal for coupling to a dc power source, a full bridge converter having a plurality of main switches, and means for achieving substantially zero-current-switching of the main switches during turn-on and turn-off of the main switches. Each primary winding of the transformer is coupled to one of the full bridge converters. 
     According to a further example of the present disclosure, a DC/DC converter includes at least one input terminal for coupling to a dc power source, a full bridge converter having a plurality of main switches, a transformer having at least one primary winding coupled to the full bridge converter and at least one secondary winding, at least one output terminal for supplying dc power to a load, a rectifier circuit coupled between the secondary winding of the transformer and the output terminal, and an auxiliary circuit coupled between the input terminal and the full bridge converter for achieving substantially zero-current-switching of the main switches during turn-on and turn-off of the main switches. 
     Further areas of applicability will become apparent from the description provided herein. It should be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. 
    
    
     
       DRAWINGS 
       The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. 
         FIG. 1  is a block diagram of a multi-input DC/DC converter according to one example of the present disclosure. 
         FIG. 2  is a block diagram of each input module shown in  FIG. 1 . 
         FIG. 3  is a circuit diagram of the ith input module shown in  FIG. 1  according to one specific embodiment of this disclosure. 
         FIG. 4  is a circuit diagram of a two-input DC/DC converter according to another example of the present disclosure. 
         FIGS. 5(   a )- 5 ( l ) illustrate the twelve operating stages of each input module shown in  FIG. 1  and constructed according to the circuit diagram of  FIG. 3 . 
         FIG. 6  is a timing diagram for each input module shown in  FIG. 1  and constructed according to the circuit diagram of  FIG. 3 . 
         FIG. 7  illustrates the waveform of i o,i  for determining a voltage conversion ratio. 
         FIG. 8  illustrates a control circuit for the auxiliary circuit shown in  FIG. 3  according to another example of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following description is merely exemplary in nature and is not intended to limit the present disclosure, application, or uses. 
     A multi-input DC/DC converter according to one example of the present disclosure is illustrated in  FIG. 1  and indicated generally by reference number  100 . As shown in  FIG. 1 , the converter  100  includes N input modules  102 ,  104 ,  106 ,  108 , a transformer  110 , a rectifier circuit  112 , and output terminals  114  for supplying dc power to a load (N represents a positive integer greater than 1). Each input module  102 - 108  includes input terminals for coupling to a dc power source. Additionally, each input module  102 - 108  includes output terminals coupled to a primary winding n 1 -n N  of the transformer  110 . The rectifier circuit  112  is coupled between a secondary winding n 0  of the transformer  110  and the converter output terminals  114 , as shown in  FIG. 1 . In this manner, power from various dc power sources are combined together and delivered to the load through the transformer  110 . 
     In the example of  FIG. 1 , each input module has the same general circuit configuration, which is illustrated in  FIG. 2 . Accordingly, the example of  FIG. 1  is a modular-based multi-input DC/DC converter. As shown in  FIG. 2 , each input module includes an input choke L i , an auxiliary circuit  220 , and a full bridge converter  230 . The auxiliary circuit  220  is coupled between the input choke L i  and the full bridge converter  230 . As further explained below, the auxiliary circuit is configured for achieving substantially zero current switching (ZCS) (also referred to as “soft-switching”) of the converter&#39;s main switches during turn-on and turn-off of such switches. The auxiliary circuit essentially converts the hard-switched isolated boost converter (the main switches of the full bridge converter) into a soft-switched isolated boost converter. The auxiliary circuit does this without significantly affecting the macro-operation of the multi-input converter  100 . As a result, the converter of  FIG. 1  has reduced losses and thus improved efficiency (on the order of 6-8%) as compared to prior art multi-input DC/DC converters. 
       FIG. 3  illustrates one specific embodiment of the auxiliary circuit and full bridge converter shown in  FIG. 2 . More specifically,  FIG. 3  illustrates the equivalent circuit for a specific embodiment of the ith input module  106  shown in  FIG. 1 . In the embodiment of  FIG. 3 , the auxiliary circuit  220  includes an auxiliary inductor L r,i , an auxiliary capacitor C r,i  and an auxiliary switch S Au,i  coupled in series. The auxiliary switch includes a body diode D Au,i  that inhibits current flow from the input choke L i  when the auxiliary switch is off. Further, the full bridge converter  230  is a phase-shift-controlled full bridge converter having four main MOSFET switches S 1,i -S 4,i  each configured for unidirectional operation. In the specific embodiment of  FIG. 3 , the main switches are configured for unidirectional operation by coupling the switch in series with blocking diodes D 1,i -D 4,i . 
     The auxiliary circuit forms a quasi-resonant circuit—with the transformer leakage inductance and the output capacitances of main switches—that facilitates zero-current-switching of the main switches in the full bridge converter. During the stages that power is transferred to the output side of the converter, the resonant time is only three quarters of the resonant period. Therefore, the auxiliary circuit is called a quasi-resonant circuit. 
     The low side switches S 3,i -S 4,i  of the full-bridge converter achieve zero-current switching during turn-off due to the resonance of the auxiliary capacitor and the auxiliary inductor. The current starts from zero, resonates to a peak value and returns to a level equal to the input current. The current then remains at such level until the power transferring stage ends. The low side switches also achieve zero-current switching during turn-on due to the auxiliary capacitor, the auxiliary inductor and the leakage inductance of the transformer. The high side switches S 1,i -S 2,i  of the full-bridge converter also turn-on and turn-off with zero current due to the transformer winding current reset. Accordingly, the switching losses in the full-bridge converter are quite low. 
     Further, the auxiliary switch achieves zero-current switching during turn-on due to the resonance of the auxiliary capacitor and the auxiliary inductor. The auxiliary switch also achieves zero-voltage switching during turn-off due to the resonance of the auxiliary capacitor, the auxiliary inductor and the leakage inductance of the transformer. Thus, soft-switching of the auxiliary switch can be achieved during both switching transitions (turn-on and turn-off). Accordingly, the switching losses in the auxiliary circuit are also quite low. 
     One example of a suitable phase-shift controller for each full-bridge converter is the UC3875 integrated circuit available from Texas Instruments Incorporated. This circuit includes a bi-directional synchronization (CLOCKSYNC) pin. This pin of several ICs (one for each full-bridge converter) can be connected together so that the gate signal will be synchronized by the IC with the fastest local oscillating frequency. In this manner, the gate signals of the high side switches are synchronized for all modules. The phase shift of the low side switches is determined by the feedback circuit of the phase-shift controller. 
     Each auxiliary circuit can be controlled by a control circuit that operates independently in each module. In other words, the control circuits for the auxiliary circuits need not be synchronized. Each control circuit can include a current transformer for sensing the current in the auxiliary circuit. The turn-on time of the auxiliary switch is pre-set depending on the auxiliary capacitor and the auxiliary inductor values. The auxiliary switch can be turned-off any time that its body diode is conducting. 
     Although  FIG. 1  illustrates a DC/DC converter with four input modules, it should be understood that the DC/DC converter can have more or less input modules without departing from the teachings of this disclosure. For example,  FIG. 4  illustrates a multi-input DC/DC converter having only two input modules. Further, while multi-input DC/DC converters are described above, it should be understood that the teachings of present disclosure also apply to single input DC/DC converters (having only one dc power source). For example, the circuit illustrated in  FIG. 3  can be used by itself as a single input DC/DC converter (having only one input module i). 
     The operating principles for one specific embodiment of the converter of FIG.  1 —where each input module includes an auxiliary circuit and a full-bridge converter as shown in FIG.  3 —will now be described. Each module goes through twelve operating stages in one switching cycle. These operating stages are described further below, and are illustrated in  FIGS. 5A-5L .  FIG. 6  illustrates the timing diagram for each module. The switches S 1,i  and S 2,i  are synchronized with the other modules, while the switches S 3,i  and S 4,i  are independently controlled for determining the input-to-output voltage requirement. The auxiliary circuit formed by the switch S Au,i , resonant inductor L r,i , and resonant capacitor C r,i  is used to provide ZCS conditions for all switches. 
     To simplify the analysis below, the following assumptions have been made: (i) the transistors and diodes are perfect; they have zero on-state resistance, infinite off-state resistance, and zero junction capacitance; (ii) all the energy storage components are free of loss without parasitic element; and (iii) the operations of the switch pair S 1,i  and S 2,i , and the switch pair S 3,i  and S 4,i , are similar; the magnitude of the output voltage is controlled by adjusting the phase shift between the two switch pairs. 
     Stage 1 [t 0 -t 1 ] [ FIG. 5(   a )]: Transformer Current Reset Stage 
     A closed path formed by the transformer, transformer leakage inductance L l,i , S 1,i , and S 2,i  is created. The output voltage V out  reflected to the transformer primary side is applied across L l,i  and makes the transformer primary current decrease. S 2,i  is then turned off with zero current at the end of this stage. The input inductor L i  is charged by the supply source v S,i . The equations of this stage are 
                       i     S   ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   12     ,   i           ,       i     Cr   ,   i       =   0     ,           ⁢       i       S   ⁢           ⁢   1     ,   i       =       (           v     S   ,   i       ⁢     L     l   ,   i         +       v     P   ,   i       ⁢     L   i             L   i     ⁢     L     l   ,   i           )     ⁢   t       ,     
     ⁢       i       S   ⁢           ⁢   2     ,   i       =       -     (         v     P   ,   i         L     l   ,   i         ⁢   t     )       +     I       L   ⁢           ⁢   12     ,   i                                       i       S   ⁢           ⁢   3     ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   12     ,   i           ,       i       S   ⁢           ⁢   4     ,   i       =   0             (   2   )                   v     Cr   ,   i       =     V       C   ⁢           ⁢   0     ,   i         ,       v       S   ⁢           ⁢   1     ,   i       =       v       S   ⁢           ⁢   2     ,   i       =       v       S   ⁢           ⁢   3     ,   i       =   0                 (   3   )               
where I L12,i  is the input current at the end of the last cycle,
 
               v     P   ,   i       =         n   i       n   o       ⁢     V   out             
is the output voltage reflected to the primary side of the transformer, and V C0,i  is the voltage across C r,i  at the end of stage 12 and is also equal to the value at the end of stage 11.
 
     The duration of this stage is Δt 1,i =t 1 −t 0 . The gate signals that apply to the two high side switches S 1,i  and S 2,i  are overlapped. The duration of this stage is Δt 1,i =t 1 −t 0 . The gate signals that apply to the two high side switches S 1,i  and S 2,i  are overlapped 
     2) Stage 2 [t 1 -t 2 ] [ FIG. 5(   b )]: Inductor Charging Stage 
     L i  is continually charged by v S,i  through the switches S 1,i  and S 3,i . The equations of this stage are 
                       i     S   ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   1     ,   i           ,       i       S   ⁢           ⁢   1     ,   i       =       i       S   ⁢           ⁢   3     ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   1     ,   i             ,     
     ⁢       i     Cr   ,   i       =   0     ,       i       S   ⁢           ⁢   2     ,   i       =       i       S   ⁢           ⁢   4     ,   i       =   0               (   4   )                   v     Cr   ,   i       =     V       C   ⁢           ⁢   0     ,   i         ,       v       S   ⁢           ⁢   1     ,   i       =       v       S   ⁢           ⁢   3     ,   i       =   0               (   5   )               
where I L1,i  is the value of i S,i  at t 1 .
 
     The duration of this stage is Δt 2,i . It determines the average current through L i  and the magnitude of V out . 
     3) Stage 3 [t 2 -t 3 ] [ FIG. 5(   c )]: Resonant Stage I 
     S Au,i  and S 4,i  are turned on with zero current. C r,i , L r,i , S 1,i , and S 3,i  form a resonant path. The energy stored in C r,i  will generate a resonant current that will make the current through S 1,i  and S 3,i  zero. The stage ends when S 3,i  is turned off with zero current and zero voltage. i Cr,i  will reach to the value equal to i S,i . The equations of this stage are 
     
       
         
           
             
               
                 
                   
                     
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     The duration of this stage, Δt 3,i =t 3 −t 2 , is determined by solving (5) and (6) that 
                         -     V       C   ⁢           ⁢   0     ,   i           Z       o   ⁢           ⁢   3     ,   i         ⁢   sin   ⁢           ⁢     ω     3   ,   i       ⁢   Δ   ⁢           ⁢     t     3   ,   i         =           v     S   ,   i         L   i       ⁢   Δ   ⁢           ⁢     t     3   ,   i         +     I       L   ⁢           ⁢   2     ,   i                 (   8   )               
The voltage of v Cr,i  at t 3  is determined by solving (6) and (7),
 
 v   Cr,i ( t   3 )= V   C1,i   =V   C0,i  cos ω 3,i   Δt   3,i   (9)
 
     4) Stage 4 [t 3 -t 4 ] [ FIG. 5(   d )]: Capacitor Constant Current Charging Stage 
     As the duration of this stage is short and the input current has small variation, L i  is considered as a constant current in this stage. The junction capacitance of S 3,i , C S3,i , and C r,i  undergo constant current charging. This stage ends when the two capacitor voltages increase to the level equal to the output voltage reflected to the primary side of the transformer. The equations of this stage are 
                         i     S   ,   i       =             v     S   ,   i       -     V       C   ⁢           ⁢   1     ,   i           Z       o   ⁢           ⁢   4     ,   i         ⁢   sin   ⁢           ⁢     ω     4   ,   i       ⁢   t     +       I       L   ⁢           ⁢   3     ,   i       ⁢   cos   ⁢           ⁢     ω     4   ,   i       ⁢   t         ,     
     ⁢             i     Cr   ,   i       =       ⁢     i     SAu   ,   i                   =       ⁢         C     r   ,   i           C     r   ,   i       +     C       S   ⁢           ⁢   3     ,   i           ⁡     [             v     S   ,   i       -     V       C   ⁢           ⁢   1     ,   i           Z       o   ⁢           ⁢   4     ,   i         ⁢   sin   ⁢           ⁢     ω     4   ,   i       ⁢   t     +       I       L   ⁢           ⁢   3     ,   i       ⁢   cos   ⁢           ⁢     ω     4   ,   i       ⁢   t       ]                     ≈       ⁢     i     S   ,   i         ,             ⁢     
     ⁢             i       S   ⁢           ⁢   3     ,   i       =       ⁢         C       S   ⁢           ⁢   3     ,   i           C     r   ,   i       +     C       S   ⁢           ⁢   3     ,   i           ⁡     [             v     S   ,   i       -     V       C   ⁢           ⁢   1     ,   i           Z       o   ⁢           ⁢   4     ,   i         ⁢   sin   ⁢           ⁢     ω     4   ,   i       ⁢   t     +       I       L   ⁢           ⁢   3     ,   i       ⁢   cos   ⁢           ⁢     ω     4   ,   i       ⁢   t       ]                     ≈       ⁢   0     ,           ⁢     
     ⁢             i       S   ⁢           ⁢   1     ,   i       =     i       S   ⁢           ⁢   2     ,   i                   =     i       S   ⁢           ⁢   4     ,   i                   =   0                   (   10   )                         v     Cr   ,   i       =       ⁢       v     S   ,   i       -       (       v     S   ,   i       -     V       C   ⁢           ⁢   1     ,   i         )     ⁢   cos   ⁢           ⁢     ω     4   ,   i       ⁢   t     +       Z       o   ⁢           ⁢   4     ,   i       ⁢     I       L   ⁢           ⁢   3     ,   i       ⁢   sin   ⁢           ⁢     ω     4   ,   i       ⁢   t                     ≈       ⁢           i     S   ,   i           C     r   ,   i       +     C       S   ⁢           ⁢   3     ,   i           ⁢   t     +     V       C   ⁢           ⁢   1     ,   i           ,           ⁢     
     ⁢       v       S   ⁢           ⁢   1     ,   i       =       v       S   ⁢           ⁢   4     ,   i       =   0               (   11   )               
where I L3,i  is the input current at t 3 ,
 
     
       
         
           
             
               
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     The duration of this stage, Δt 4,i =t 4 −t 3 , is obtained by using (10) that
 
 v   P,i   −v   S,i =−( v   S,i   −V   C1,i )cos ω 4,i   Δt   4,i   +Z   o4,i   I   L3,i  sin ω 4,i   Δt   4,i   (12)
 
     5) Stage 5 [t 4 -t 5 ] [ FIG. 5(   e )]: Resonant Stage II 
     S 4,i  starts conducting. C r,i , L r,i , S 1,i , S 4,i , the output capacitances of S 2,i  and S 3,i , C S2,i  and C S3,i , and the leakage inductance of the transformer L l,i  form a resonant circuit. S Au,i  will be turned off with zero current and zero voltage, when the diode D Au,i  conducts. This stage ends when D Au,i  turns off with zero current. 
                         i     S   ,   i       =             (       v     S   ,   i       -     v     P   ,   i         )     ⁢     C     r   ,   i       ⁢     L     l   ,   i     2           (       L   i     +     L     l   ,   i         )     ⁢         C     r   ,   i       ⁢       Φ   i     ⁡     (       L   i     +     L     l   ,   i         )               ⁢   sin   ⁢           ⁢     ω     5   ,   i       ⁢   t     +           L     l   ,   i       ⁢     I       L   ⁢           ⁢   4     ,   i             L   i     +     L     l   ,   i           ⁢   cos   ⁢           ⁢     ω     5   ,   i       ⁢   t     -           v     P   ,   i       -     v     S   ,   i             L   i     +     L     l   ,   i           ⁢   t     +         L   i     ⁢     I       L   ⁢           ⁢   4     ,   i             L   i     +     L     l   ,   i               ,     
     ⁢           ⁢       i     Cr   ,   i       =             (       v     S   ,   i       -     v     P   ,   i         )     ⁢     L     l   ,   i       ⁢     C     r   ,   i               C     r   ,   i       ⁢       Φ   i     ⁡     (       L   i     +     L     l   ,   i         )             ⁢   sin   ⁢           ⁢     ω     5   ,   i       ⁢   t     +       I       L   ⁢           ⁢   4     ,   i       ⁢   cos   ⁢           ⁢     ω     5   ,   i       ⁢   t         ,     
     ⁢                   ⁢       i       S   ⁢           ⁢   1     ,   i       =       ⁢     i       S   ⁢           ⁢   4     ,   i                     =       ⁢             (       v     P   ,   i       -     v     S   ,   i         )     ⁢     C     r   ,   i       ⁢     L   i     ⁢     L     l   ,   i             (       L   i     +     L     l   ,   i         )     ⁢         C     r   ,   i       ⁢       Φ   i     ⁡     (       L   i     +     L     l   ,   i         )               ⁢   sin   ⁢           ⁢     ω     5   ,   i       ⁢   t     -                     ⁢               L   i     ⁢     I       L   ⁢           ⁢   4     ,   i             L   i     +     L     l   ,   i           ⁢   cos   ⁢           ⁢     ω     5   ,   i       ⁢   t     -           v     P   ,   i       -     v     S   ,   i             L   i     +     L     l   ,   i           ⁢   t     +         L   i     ⁢     I       L   ⁢           ⁢   4     ,   i             L   i     +     L     l   ,   i             ,               ⁢     
     ⁢           ⁢       i       S   ⁢           ⁢   2     ,   i       =       i       S   ⁢           ⁢   3     ,   i       =   0               (   13   )                   v     Cr   ,   i       =         I       L   ⁢           ⁢   4     ,   i       ⁢     Z       o   ⁢           ⁢   5     ,   i       ⁢   sin   ⁢           ⁢     ω     5   ,   i       ⁢   t     -           (       v     S   ,   i       -     v     P   ,   i         )     ⁢     L     l   ,   i             L   i     +     L     l   ,   i           ⁢   cos   ⁢           ⁢     ω     5   ,   i       ⁢   t     +           L   i     ⁢     v     P   ,   i         +       L     l   ,   i       ⁢     v     S   ,   i               L   i     +     L     l   ,   i               ,     
     ⁢           ⁢       v       S   ⁢           ⁢   1     ,   i       =       v       S   ⁢           ⁢   4     ,   i       =   0       ,     
     ⁢                   ⁢       v       S   ⁢           ⁢   2     ,   i       =       ⁢     v       S   ⁢           ⁢   3     ,   i                     =       ⁢             (       v     P   ,   i       -     v     S   ,   i         )     ⁢     L   i     ⁢     L     l   ,   i     2           (       L   i     +     L     l   ,   i         )     ⁢     Φ   i         ⁢   cos   ⁢           ⁢     ω     5   ,   i       ⁢   t     +                     ⁢             L   i     ⁢     L     l   ,   i       ⁢     I       L   ⁢           ⁢   4     ,   i               C     r   ,   i       ⁢       Φ   i     ⁡     (       L   i     +     L     l   ,   i         )             ⁢   sin   ⁢           ⁢     ω     5   ,   i       ⁢   t     +           v     S   ,   i       ⁢     L     l   ,   i         +       v     P   ,   i       ⁢     L   i             L   i     +     L     l   ,   i                             (   14   )               
where I L4,i  is the input current at t 4 ,
 
                 ω     5   ,   i       =           L   i     +     L     l   ,   i             C     r   ,   i       ⁢     Φ   i             ,       Z       o   ⁢           ⁢   5     ,   i       =         Φ   i         C     r   ,   i       ⁡     (       L   i     +     L     l   ,   i         )                   
and Φ i =L r,i  L i +L r,i  L l,i +L i  L l,i .
 
     The duration of this stage Δt 5,i  is obtained by solving i Cr,i =0 in (13) that 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       t 
                       
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                         t 
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                                     ( 
                                     
                                       
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                                         i 
                                       
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                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
     At the end of this stage, v Cr,i =V C5,i  and is determined by using (14) and (15). 
     
       
         
           
             
               
                 
                   
                     
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                   ( 
                   16 
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     The maximum voltage and current rating of the main switches, v S2(max),i , v S3(max),i , i S1(max),i , and i S4(max),i , can be obtained by solving (13) and (14), respectively. 
     
       
         
           
             
               
                 
                   
                     
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                           i 
                           
                             
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                   ( 
                   18 
                   ) 
                 
               
             
           
         
       
     
     6) Stage 6 [t 5 -t 6 ] [ FIG. 5(   f )]: Inductor Discharging Stage 
     The energy stored in L i  releases to the output together with the input at a relatively constant current. This stage ends when S 2,i  is turned on with zero current. 
                       i     S   ,   i       =             v     S   ,   i       -     v     P   ,   i           L   i       ⁢   t     +     I       L   ⁢           ⁢   5     ,   i           ,     
     ⁢       i     Cr   ,   i       =   0     ,     
     ⁢       i       S   ⁢           ⁢   1     ,   i       =       i       S   ⁢           ⁢   4     ,   i       =             v     S   ,   i       -     v     P   ,   i           L   i       ⁢   t     +     I       L   ⁢           ⁢   5     ,   i             ,     
     ⁢       i       S   ⁢           ⁢   2     ,   i       =       i       S   ⁢           ⁢   3     ,   i       =   0               (   19   )                   v     Cr   ,   i       =     V       C   ⁢           ⁢   0     ,   i         ,       v       S   ⁢           ⁢   1     ,   i       =       v       S   ⁢           ⁢   4     ,   i       =   0               (   20   )               
where I L5,i  is the input current at t 5 .
 
     The duration of this stage Δt 6,i  is equal to 
                     Δ   ⁢           ⁢     t     6   ,   i         =         t   6     -     t   5       =       (       θ   i     ⁢       T   S     2       )     -     (         3   ⁢   π     2     ⁢     1     ω     5   ,   i           )                 (   21   )               
where θ i =t 6 −t 4 .
 
     As shown in  FIG. 6 , θ i  is approximately equal to the phase shift between the switch pairs of S 1,i -S 2,i  and S 3,i -S 4,i , as the duration of stage 4 is short. 
     7) Stage 7 [t 6 -t 7 ] [ FIG. 5(   g )]: Transformer Current Reset Stage 
     This stage is similar to stage 1. The reflected voltage of V out  on the primary side is applied across L l,I  through S 1,i  and S 2,i . This makes the transformer primary current decrease linearly. S 1,i  is turned off with zero current before the end of this stage. The input inductor L i  is charged by the supply source v S,i . The equations of this stage are 
                         i     S   ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   6     ,   i           ,     
     ⁢       i     Cr   ,   i       =   0     ,     
     ⁢       i       S   ⁢           ⁢   1     ,   i       =         -       v     P   ,   i         L     l   ,   i           ⁢   t     +     I       L   ⁢           ⁢   6     ,   i           ,     
     ⁢       i       S   ⁢           ⁢   2     ,   i       =             v     S   ,   i       ⁢     L     l   ,   i         +       v     P   ,   i       ⁢     L   i             L   i     ⁢     L     l   ,   i           ⁢   t         ⁢     
     ⁢         i       S   ⁢           ⁢   3     ,   i       =   0     ,     
     ⁢       i       S   ⁢           ⁢   4     ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   6     ,   i                     (   22   )                   v     Cr   ,   i       =     V       C   ⁢           ⁢   0     ,   i         ,     
     ⁢       v       S   ⁢           ⁢   1     ,   i       =       v       S   ⁢           ⁢   2     ,   i       =       v       S   ⁢           ⁢   4     ,   i       =   0                 (   23   )               
where I L6,i  is the input current at t 6 .
 
     The duration of this stage is Δt 7,i =t 7 −t 6 . The gate signals that apply to the two high side switches S 1,i  and S 2,i  are overlapped. 
     8) Stage 8 [t 7 -t 8 ] [ FIG. 5(   h )]: Inductor Charging Stage 
     L i  is continually charged by v S,i  through the switches S 2,i  and S 4,i . The equations of this stage are 
                       i     S   ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   7     ,   i           ,     
     ⁢       i       S   ⁢           ⁢   1     ,   i       =       i       S   ⁢           ⁢   3     ,   i       =   0       ,     
     ⁢       i       S   ⁢           ⁢   2     ,   i       =       i       S   ⁢           ⁢   4     ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   7     ,   i             ,     
     ⁢       i     Cr   ,   i       =   0             (   24   )                   v     Cr   ,   i       =     V       C   ⁢           ⁢   0     ,   i         ,     
     ⁢       v       S   ⁢           ⁢   1     ,   i       =       v       S   ⁢           ⁢   3     ,   i       =   0               (   25   )               
where I L7,i  is the input current at t 7 .
 
     The duration of this stage is Δt 8,i . Similar to stage 2, it determines the average current through L i  and the magnitude of V out . 
     9) Stage 9 [t 8 -t 9 ] [ FIG. 5(   i )]: Resonant Stage I 
     S Au,i  and S 3,i  are turned on with zero current. C r,i , L r,i , S 2,i , and S 4,i  form a resonant path. The energy stored in C r,i  will generate a resonant current that will make the current through S 2,i  and S 4,i  zero. The stage ends when S 4,i  is turned off with zero current and zero voltage. i Cr,i  will reach to the value equal to i S,i . The equations of this stage are 
                         i     S   ,   i       =           v     S   ,   i         L   i       ⁢   t     +     I       L   ⁢           ⁢   8     ,   i           ,     
     ⁢       i       S   ⁢           ⁢   1     ,   i       =       i       S   ⁢           ⁢   3     ,   i       =   0       ,     
     ⁢       i       S   ⁢           ⁢   2     ,   i       =       i       S   ⁢           ⁢   4     ,   i       =           v     S   ,   i         L   i       ⁢   t     +         V       C   ⁢           ⁢   0     ,   i         Z       o   ⁢           ⁢   9     ,   i         ⁢   sin   ⁢           ⁢     ω     9   ,   i       ⁢   t     +     I       L   ⁢           ⁢   8     ,   i               ⁢     
     ⁢       i     Cr   ,   i       =       -       V       C   ⁢           ⁢   0     ,   i         Z       o   ⁢           ⁢   9     ,   i           ⁢   sin   ⁢           ⁢     ω     9   ,   i       ⁢   t               (   26   )                   v     Cr   ,   i       =       V       C   ⁢           ⁢   0     ,   i       ⁢   cos   ⁢           ⁢     ω     9   ,   i       ⁢   t       ,     
     ⁢       v       S   ⁢           ⁢   2     ,   i       =       v       S   ⁢           ⁢   3     ,   i       =       v       S   ⁢           ⁢   4     ,   i       =   0                 (   27   )               
where I L8,i  is the value of i S,i  at t 1 , ω 9,i =ω 3,i  and Z o9,i =Z o3,i .
 
     The duration of this stage, Δt 9,i =t 9 −t 8 , is determined by solving (26) and (27) that 
                         -     V       C   ⁢           ⁢   0     ,   i           Z       o   ⁢           ⁢   9     ,   i         ⁢   sin   ⁢           ⁢     ω     9   ,   i       ⁢   Δ   ⁢           ⁢     t     9   ,   i         =           v     S   ,   i         L   i       ⁢   Δ   ⁢           ⁢     t     9   ,   i         +     I       L   ⁢           ⁢   8     ,   i                 (   28   )               
The value of Δt 9,i  is equal to Δt 3,i .
 
     10) Stage 10 [t 9 -t 10 ] [ FIG. 5(   j )]: Resonant Capacitor Constant Current Charging Stage 
     Similar to Stage 4, the junction capacitance of S 4,i , C S4,i , and C r,i  undergo constant current charging. This stage ends when the capacitor voltages increase to the level equal to the output voltage reflected to the primary side of the transformer. The equations of this stage are 
                         i     S   ,   i       =             v     S   ,   i       -     V       C   ⁢           ⁢   1     ,   i           Z       o   ⁢           ⁢   10     ,   i         ⁢   sin   ⁢           ⁢     ω     10   ,   i       ⁢   t     +       I       L   ⁢           ⁢   9     ,   i       ⁢   cos   ⁢           ⁢     ω     10   ,   i       ⁢   t         ,     
     ⁢             i     Cr   ,   i       =       ⁢     i     SAu   ,   i                   =       ⁢         C     r   ,   i           C     r   ,   i       +     C       S   ⁢           ⁢   4     ,   i           ⁡     [             v     S   ,   i       -     V       C   ⁢           ⁢   1     ,   i           Z       o   ⁢           ⁢   10     ,   i         ⁢   sin   ⁢           ⁢     ω     10   ,   i       ⁢   t     +       I       L   ⁢           ⁢   9     ,   i       ⁢   cos   ⁢           ⁢     ω     10   ,   i       ⁢   t       ]                     ≈       ⁢     i     S   ,   i         ,             ⁢     
     ⁢         i       S   ⁢           ⁢   1     ,   i       =       i       S   ⁢           ⁢   2     ,   i       =       i       S   ⁢           ⁢   3     ,   i       =   0         ,     
     ⁢       i       S   ⁢           ⁢   4     ,   i       =           C       S   ⁢           ⁢   4     ,   i           C     r   ,   i       +     C       S   ⁢           ⁢   4     ,   i           ⁡     [             v     S   ,   i       -     V       C   ⁢           ⁢   1     ,   i           Z       o   ⁢           ⁢   10     ,   i         ⁢   sin   ⁢           ⁢     ω     10   ,   i       ⁢   t     +       I       L   ⁢           ⁢   9     ,   i       ⁢   cos   ⁢           ⁢     ω     10   ,   i       ⁢   t       ]       ≈   0                 (   29   )                         v     Cr   ,   i       =       ⁢       v     S   ,   i       -       (       v     S   ,   i       -     V       C   ⁢           ⁢   1     ,   i         )     ⁢   cos   ⁢           ⁢     ω     10   ,   i       ⁢   t     +       Z       o   ⁢           ⁢   10     ,   i       ⁢     I       L   ⁢           ⁢   9     ,   i       ⁢   sin   ⁢           ⁢     ω     10   ,   i       ⁢   t                     ≈       ⁢           i     S   ,   i           C     r   ,   i       +     C       S   ⁢           ⁢   4     ,   i           ⁢   t     +     V       C   ⁢           ⁢   1     ,   i           ,           ⁢     
     ⁢       v       S   ⁢           ⁢   2     ,   i       =       v       S   ⁢           ⁢   3     ,   i       =   0               (   30   )               
where I L9,i  is the input current at t 9 , ω 10,i =ω 4,i  and Z o10,i =Z o4,i .
 
     The duration of this stage, Δt 10,i =t 10 −t 9 , is obtained by solving (30) that
 
 v   P,i   −v   S,i =−( v   S,i   −V   C1,i )cos ω 10,i   Δt   10,i   +Z   o10,i   I   L9,i  sin ω 10,i   Δt   10,i   (31)
 
     11) Stage 11 [t 10 -t 11 ] [ FIG. 5(   k )]: Resonant Stage II 
     S 3,i  starts conducting. C r,i , L r,i , S 2,i , S 3,i , the output capacitances of S 1,i  and S 4,i , C S1,i  and C S4,i , and the leakage inductance of the transformer L l,i  form a resonant circuit. S Au,i  will be turned off with zero current and zero voltage, when the diode D Au,i  conducts. This stage ends when D Au,i  turns off with zero current. 
                         i     S   ,   i       =             (       v     S   ,   i       -     v     P   ,   i         )     ⁢     C     r   ,   i       ⁢     L     l   ,   i     2           (       L   i     +     L     l   ,   i         )     ⁢         C     r   ,   i       ⁢       Φ   i     ⁡     (       L   i     +     L     l   ,   i         )               ⁢   sin   ⁢           ⁢     ω     11   ,   i       ⁢   t     +           L     l   ,   i       ⁢     I       L   ⁢           ⁢   10     ,   i             L   i     +     L     l   ,   i           ⁢   cos   ⁢           ⁢     ω     11   ,   i       ⁢   t     -           v     P   ,   i       -     v     S   ,   i             L   i     +     L     l   ,   i           ⁢   t     +         L   i     ⁢     I       L   ⁢           ⁢   10     ,   i             L   i     +     L     l   ,   i               ,     
     ⁢           ⁢       i     Cr   ,   i       =             (       v     S   ,   i       -     v     P   ,   i         )     ⁢     L     l   ,   i       ⁢     C     r   ,   i               C     r   ,   i       ⁢       Φ   i     ⁡     (       L   i     +     L     l   ,   i         )             ⁢   sin   ⁢           ⁢     ω     11   ,   i       ⁢   t     +       I       L   ⁢           ⁢   10     ,   i       ⁢   cos   ⁢           ⁢     ω     11   ,   i       ⁢   t         ,     
     ⁢       i       S   ⁢           ⁢   2     ,   i       =       i       S   ⁢           ⁢   3     ,   i       =             (       v     P   ,   i       -     v     S   ,   i         )     ⁢     C     r   ,   i       ⁢     L   i     ⁢     L     l   ,   i             (       L   i     +     L     l   ,   i         )     ⁢         C     r   ,   i       ⁢       Φ   i     ⁡     (       L   i     +     L     l   ,   i         )               ⁢   sin   ⁢           ⁢     ω     11   ,   i       ⁢   t     -           L   i     ⁢     I       L   ⁢           ⁢   10     ,   i             L   i     +     L     l   ,   i           ⁢   cos   ⁢           ⁢     ω     11   ,   i       ⁢   t     -           v     P   ,   i       -     v     S   ,   i             L   i     +     L     l   ,   i           ⁢   t     +         L   i     ⁢     I       L   ⁢           ⁢   10     ,   i             L   i     +     L     l   ,   i                 ,     
     ⁢           ⁢       i       S   ⁢           ⁢   1     ,   i       =       i       S   ⁢           ⁢   4     ,   i       =   0         ⁢                   (   32   )                   v     Cr   ,   i       =         I       L   ⁢           ⁢   10     ,   i       ⁢     Z       o   ⁢           ⁢   10     ,   i       ⁢   sin   ⁢           ⁢     ω     11   ,   i       ⁢   t     -           (       v     S   ,   i       -     v     P   ,   i         )     ⁢     L     l   ,   i             L   i     +     L     l   ,   i           ⁢   cos   ⁢           ⁢     ω     11   ,   t       ⁢   t     +           L   i     ⁢     v     P   ,   i         +       L     l   ,   i       ⁢     v     S   ,   i               L   i     +     L     l   ,   i               ,     
     ⁢           ⁢       v       S   ⁢           ⁢   2     ,   i       =       v       S   ⁢           ⁢   3     ,   i       =   0               (   33   )               
where I L10,i  is the input current at t 10 , ω 11,i =ω 5,i , Z o11,i =Z o5,i , and Φ i =L r,i  L i +L r,i  L l,i +L i  L l,i .
 
     The duration of this stage Δt 11,i =t 11 −t 10  is equal to Δt 5,i . 
     12) Stage 12 [t 11 -t 12 ] [ FIG. 5(   l )]: Inductor Discharging Stage 
     The energy stored in L i  releases to the output together with the input at a relatively constant current. This stage ends when S 1,i  is turned on with zero current. 
                       i     S   ,   i       =             v     S   ,   i       -     v     P   ,   i           L   i       ⁢   t     +     I       L   ⁢           ⁢   11     ,   i           ,     
     ⁢       i     Cr   ,   i       =   0     ,     
     ⁢       i       S   ⁢           ⁢   2     ,   i       =       i       S   ⁢           ⁢   3     ,   i       =             v     S   ,   i       -     v     P   ,   i           L   i       ⁢   t     +     I       L   ⁢           ⁢   11     ,   i             ,     
     ⁢       i       S   ⁢           ⁢   1     ,   i       =       i       S   ⁢           ⁢   4     ,   i       =   0               (   34   )                   v     Cr   ,   i       =     V       C   ⁢           ⁢   0     ,   i         ,       v       S   ⁢           ⁢   2     ,   i       =       v       S   ⁢           ⁢   3     ,   i       =   0               (   35   )               
where I L11,i  is the input current at t 11 .
 
     The duration of this stage Δt 12,i =t 12 −t 11  is equal to Δt 6,i . This completes a cycle of operation. 
     For the sake of simplicity in the following analysis of steady-state conditions, the input inductor current i S,i  is assumed to be constant throughout the whole period. This is valid because the ripple current is very small, as compared with the average of i S,i . 
     A. Voltage Conversion Ratio 
     The voltage conversion ratio is derived by considering the current i o,i  on the primary side of the transformer.  FIG. 7  shows the waveform of i o,i . The electric energy is transferred from the primary side to the secondary in three main intervals in one-half of the switching period. Consider the first half cycle from t 0  to t 6 . The intervals are as follows:
     1) Stage 5—Based on (13), i o,i  can be expressed as
 
 i   o,i   =i   S,i   −i   S,i  cos ω 5,i   t   (36)
 
The duration of this interval Δt 5  is shown in (15).Δ
   2) Stage 6—i o,i =i S,i . The duration of this interval Δt 6,i  is shown in (20).   3) Stage 7—i o,i  decreases linearly, as expressed in (22),   

                     i     o   ,   i       =         -       v     P   ,   i         L     l   ,   i           ⁢   t     +     i     S   ,   i                 (   37   )               
The duration of this interval Δt 7,i  is determined by solving (37) for i o,i =0. Thus,
 
                     Δ   ⁢           ⁢     t     7   ,   i         =         t   7     -     t   6       =         L     l   ,   i       ⁢     i     S   ,   i           v     P   ,   i                   (   38   )               
Thus, the area under i o,i  is equal to
 
                           A     P   ,   i       =       ⁢         ∫   0     Δ   ⁢           ⁢     t     5   ,   i           ⁢       [       i     S   ,   i       -       i     S   ,   i       ⁢   cos   ⁢           ⁢     ω     5   ,   i       ⁢   t       ]     ⁢     ⅆ   t         +                     ⁢         ∫   0     Δ   ⁢           ⁢     t     6   ,   i           ⁢       i     S   ,   i       ⁢     ⅆ   t         +       ∫   0     Δ   ⁢           ⁢     t     7   ,   i           ⁢       (         -       v     P   ,   i         L     l   ,   i           ⁢   t     +     i     S   ,   i         )     ⁢     ⅆ   t                       =       ⁢         i     S   ,   i       ⁡     (       θ   i     ⁢       T   S     2       )       +       i     S   ,   i       ⁢         C     r   ,   i       ⁡     (       L     r   ,   i       +     L     l   ,   i         )           +       1   2     ⁢     (         L     l   ,   i       ⁢     i     S   ,   i     2         v     P   ,   i         )                       (   39   )               
The average output current I o,i  of the module is equal to
 
                           I     o   ,   i       =       2     T   S       ⁢       n   i       n   o       ⁢     A   P                   =       i     S   ,   i       ⁢         n   i       n   o       ⁡     [       θ   i     +       2     T   S       ⁢         C     r   ,   i       ⁡     (       L     r   ,   i       +     L     l   ,   i         )           +       1     T   S       ⁢     (         L     l   ,   i       ⁢     i     S   ,   i               n   i       n   o       ⁢     V   Out         )         ]                       (   40   )               
For N modules, the total output current I o  is equal to the sum of all module outputs. Thus,
 
                           I   o     =       ∑     i   =   1     N     ⁢     I     o   ,   i                     =       ∑     i   =   1     N     ⁢       i     S   ,   i       ⁢         n   i       n   o       [       θ   i     +       2     T   S       ⁢         C     r   ,   i       ⁡     (       L     r   ,   i       +     L     l   ,   i         )           +       1     T   S       ⁢     (         L     l   ,   i       ⁢     i     S   ,   i               n   i       n   o       ⁢     V   Out         )         ]                       (   41   )               
By using the conservation of energy, the voltage conversion ratio can be shown to be
 
                             i     S   ,   i       ⁢     V     S   ,   i         =       ⁢       i   o     ⁢     V   Out                   ⇒       ⁢       V   Out       V     S   ,   i                     =       ⁢         n   o       n   i       ⁢       1   -         L     l   ,   i       ⁢     i     S   ,   i             T   S     ⁢     v     S   ,   i                 θ   i     +       2     T   S       ⁢         C     r   ,   i       ⁡     (       L     r   ,   i       +     L     l   ,   i         )                               (   42   )               
Thus, the output voltage can be controlled by adjusting the value of θ i , which is the phase shift between the two switch pairs.
 
     B. Selection of L l,i , C r,i , and L r,i    
     1. L l,i    
     L l,i  is used to achieve ZCS of the two high side switches. The maximum value of L l,i , L l(max),i , determines the critical ZCS condition in stages 1 or 7 at the maximum power P max,i . By using (2), it can be shown that 
                     L       l   ⁡     (   max   )       ,   i       =         n   i     ⁢     V   out     ⁢     v     s   ,   i       ⁢   Δ   ⁢           ⁢     t     1   ,   i             n   o     ⁢     P     max   ,   i                   (   43   )               
where i S(max),i  is the maximum value of i S,i .
 
     The duration of Δt 1,i  is an adjustable variable in the circuit implementation. It is practically determined by the controller integrated circuit [10]. Thus, the output power can be increased by increasing Δt 1,i —the overlap time of the two high side switches. 
     2. C r,i  and L r,i    
     The minimum value of C r,i  is determined by ensuring the ZCS conditions for the two low side switches in stages 3 or 9 at the minimum power P min,i . The durations Δt 3,i  or Δt 9,i  are equal to π/2ω 3,i . Thus, by using (7),
 
Δ t   3,i =π/2ω 3,i =π/2√{square root over ( C   r,i   L   r,i )}  (44)
 
By assuming I L4,i =i S(min),i  and using (16) and (6),
 
                           -       V       C   ⁢           ⁢   0     ,   i         Z       o   ⁢           ⁢   3     ,   i           =       ⁢     i     S   ,     (   min   )     ,   i                   ⇒       ⁢     C     r   ,   i                   =       ⁢       [         (           L     l   ,   i       +     L     r   ,   i           -       L     r   ,   i           )     ⁢     i       S   ⁡     (   min   )       ,   i           v     P   ,   i         ]     2                   (   45   )               
where i S(min),i  is the value of i S,i  at the minimum input power.
 
By solving (44) and (45) for C r,i  and L r,i , it can be shown that
 
                       C     r   ,   i       =           n   o     ⁢     P   min           n   i     ⁢     V   out     ⁢     v     s   ,   i           ⁡     [         L     l   ,   i       ⁡     (         n   o     ⁢     P   min           n   i     ⁢     V   out     ⁢     v     s   ,   i           )       -     2   ⁢     (     Δ   ⁢           ⁢     t     3   ,   i       ⁢     2   π       )         ]         ⁢     
     ⁢   and           (   46   )                 L     r   ,   i       =         (           n   i     ⁢     V   out     ⁢     v     s   ,   i             n   o     ⁢     P   min         ⁢   Δ   ⁢           ⁢     t     3   ,   i       ⁢     2   π       )     2         L     l   ,   i       -     2   ⁢         n   i     ⁢     V   out     ⁢     v     s   ,   i             n   o     ⁢     P   min         ⁢     (     Δ   ⁢           ⁢     t     3   ,   i       ⁢     2   π       )                   (   47   )               
According to (45), in order to ensure a positive value of C r,i , the value of L l,i  has to satisfy the following constraint of
 
                       L     l   ,   i       &gt;     L       l   ⁡     (   min   )       ,   i         =     2   ⁢         n   i     ⁢     V   out     ⁢     v     s   ,   i             n   o     ⁢     P   min         ⁢     (     Δ   ⁢           ⁢     t     3   ,   i       ⁢     2   π       )               (   48   )               
As shown in (46), the value of C r,i  increases with the increase in the value of L l,i  for a given power level.
 
     C. Selection of the Transformer Turns-Ratio n o /n i    
     The transformer turns ratio is selected by considering the converter at the minimum power condition P min . By rearranging (45), 
                     P     min   ,   i       =         v     S   ,   i       ⁢     i       S   ⁡     (   min   )       ,   i         =         v     S   ,   i       ⁢     v     P   ,   i             Z       o   ⁢           ⁢   5     ,   i       -     Z       o   ⁢           ⁢   3     ,   i                     (   49   )               
Based on (42), the output power decreases as θ i  increases. By substituting (49) into (42) and eliminating i S(min),i , it can be shown that
 
                         n   i       n   o       ⁡     [       θ     i   ⁡     (   max   )         +       2     T   S       ⁢         C     r   ,   i       ⁡     (       L     r   ,   i       +     L     l   ,   i         )           +       1     T   S       ⁢     (       L     l   ,   i           Z       o   ⁢           ⁢   5     ,   i       -     Z       o   ⁢           ⁢   3     ,   i           )         ]       =       v     S   ,   i         V   Out               (   50   )               
where θ i(max)  is the maximum value of θ i  and is derived as follows.
 
     θ i(max)  occurs when Δt 4,i  is close to zero. Thus, according to  FIG. 6 , 
                       θ     i   ⁡     (   max   )         ⁢       T   S     2       =         T   S     2     -     Δ   ⁢           ⁢     t     1   ,   i         -     Δ   ⁢           ⁢     t     2   ,   i         -     Δ   ⁢           ⁢     t     3   ,   i                   (   51   )               
Δt 1,i , Δt 2,i , and Δt 3,i  are set by the external components in the phase-shift controller, such as UC3875. By substituting (51) into (50), the maximum turns ratio μ max  is equal to
 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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       FIG. 8  illustrates one example of a suitable control circuit  800  for the auxiliary circuit  220  shown in  FIG. 3 . As shown in  FIG. 8 , the control circuit  800  includes a NOR gate U 4,i  for monitoring the overlapping period of switching gate signals v GS3,i  and v GS4,i . An LC filter network R 1,i  and C 1,i , together with a positive DC voltage V DC3,i  and a comparator U 3,i , is used to determine the turn-on time of the auxiliary switch S Au,i  during the overlapping period. 
     A current transformer T C,i  with turns-ratio 1:n is connected in series in the auxiliary circuit, where n is a large integer such as 140. The current transformer is used to step down the current flowing through the auxiliary circuit. Resistor R S,i  is a current sense resistor which is connected in series with the secondary winding of the current transformer. 
     The turn-on signal provided by the comparator U 3,i  cannot be maintained after the overlapping period. Therefore, comparators U 1,i , U 2,i , an RS latch U 5,i , and an OR gate U 6,i  are provided to maintain the turn-on signal v GSAu,i  for the auxiliary switch S Au,i  throughout Stages 3, 4 and 5. 
     The comparator U 1,i , which receives a positive DC voltage V DC1,i , latches the output of the RS latch U 5,i  to Logic “1” when it detects the rising voltage across the current sense resistor R S,i  during Stage 3. The OR gate U 6,i  combines the Logic “1” signals from the comparator U 3,i  and the RS latch U 5,i  to maintain the turn-on signal v GSAu,i  high. When the signal from the comparator U 3,i  changes to a Logic “0” during Stage 4, the output of the RS latch U 5,i  maintains the turn-on signal v GSAu,i  high to keep the auxiliary switch S Au,i  on. 
     The comparator U 2,i , which receives a negative DC voltage−V DC2,i , is used to remove the gate signal v GSAu,i  when the body diode of the auxiliary switch S Au,i  conducts at Stage 5. When the comparator U 2,i  detects the negative voltage across the current sense resistor R S,i , it resets the RS-latch U 5,i  to Logic “0,” which causes the output of the OR gate to become low so that the auxiliary switch S Au,i  is turned off when its body diode is conducting.