Abstract:
A method for forming a silicon on insulator region on a single crystal silicon substrate, comprising the steps of: forming a first dielectric region in a silicon substrate by etching, deposition, and chemical-mechanical polishing; forming a single crystal layer on the substrate by polysilicon deposition and re-growth or epitaxial growth; removing portions of the single crystal layer to produce silicon islands that are fully on the first dielectric region; and filling in the spaces between the silicon islands with a second dielectric, by deposition and chemical-mechanical-polish, that overlaps peripheral portions of the first dielectric. Additional steps subdivide the fully isolated silicon on insulator regions by etching trenches in the islands and backfilling with a third dielectric, by deposition and chemical-mechanical-polish.

Description:
RELATED APPLICATION 
     This application is a divisional of U.S. application Ser. No. 09/167,693, filed Oct. 7, 1998. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of silicon on insulator technology; and, more particularly, it relates to a method for fabricating silicon on insulator regions on a silicon wafer. 
     BACKGROUND OF THE INVENTION 
     Silicon on insulator (SOI) technology offers many advantages over conventional bulk silicon technology. Among these is the ability to build high performance, high speed, low power complementary-metal-oxide-semiconductor (CMOS) devices. 
     Turning to the prior art, one well known method to produce a silicon on insulator substrate is by bonding together two silicon wafers, each having an oxide layer, in a high temperature furnace step. Usually one side of the fused wafer needs to be thinned by chemical-mechanical-polishing. Another well known method is SIMOX (Separation by Implanted Oxygen) technology. In this technique a high dose oxygen ion implantation step is performed to place oxygen atoms in the silicon wafer at a fixed distance from the surface. This is followed by an anneal step, which then forms the buried oxide layer. Both these processes produce whole wafer silicon on insulator wafers. 
     Other techniques for fabricating silicon on insulator substrates use etch and oxidation steps to produce isolated silicon islands in a silicon substrate. For example, U.S. Pat. No. 5,185,286 to Eguchi, describes a process for producing a laminated semiconductor comprising the steps of forming openings in an oxide film on a silicon wafer, forming a silicon nitride island midway between the openings, growing epitaxial silicon, polishing to produce a flat surface, and selectively oxidizing the epitaxial silicon over the original openings in the oxide layer. One concern with this method is that the silicon island which is produced is located between a block of silicon nitride and an area of thermally oxidized silicon, subjecting the island to stresses. 
     U.S. Pat. No. 5,321,298 to Moslehi, describes a method for forming a semiconductor on insulator wafer with a single crystal semiconductor substrate comprising the steps of etching trenches in the substrate, forming oxide on the bottom of the trenches, growing epitaxial silicon to partially fill the trenches, forming a nitride spacer on top of the trenches, growing a second epitaxial silicon to fill the trenches, removing the nitride spacer, etching the epitaxial silicon down to the oxide originally formed at the bottom of the trenches and then filling the new trenches with oxide. Drawbacks with this method are its complexity and the integrity of the silicon crystal structure grown on many epitaxial fronts. 
     U.S. Pat. No. 5,691,230 describes a method of forming silicon on insulator rows and islands in a silicon substrate. Trenches are directionally etched in the silicon substrate. The tops of the rows and bottoms of the trenches are coated with silicon nitride. An isotropic etch is used to partially undercut the silicon rows. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. This method leaves a topology that may be disadvantageous to fabrication of high density circuits. 
     The present invention is directed toward a method of fabricating silicon on insulator regions on a substrate that produces silicon islands that are of good crystal integrity, low stress and coplanar with the rest of the wafer surface, while easily fabricated. 
     SUMMARY OF THE INVENTION 
     The invention provides a method for forming regions of silicon on insulator in bulk silicon wafers. A trench or recess is first formed in the bulk silicon wafer by a first etch process, and it is then filled in with a first dielectric. After a chemical-mechanical-polish step to planarize the surface, dielectric filled trenches or islands are left surrounded by bulk silicon. At this point either polysilicon is deposited and a re-crystallization step performed or epitaxial silicon is grown directly using the exposed bulk silicon as a seed layer. This produces a single crystal silicon layer extending over the dielectric filled trenches or islands. A second silicon etch process is performed to remove all the single crystal silicon except in regions directly over the now buried first dielectric. Care is taken to ensure a lip or peripheral region of first dielectric is left exposed all around the remaining single crystal silicon. The trenches formed by this second etch are then filled with a second dielectric. The second dielectric contacts the lip left exposed on the first dielectric. Therefore, after a chemical-mechanical-polish step, islands of single crystal silicon have been formed which are isolated from each other and the bulk silicon wafer. 
     A particular advantage of the invention is that it is suitable as a pre-fabrication process on dies where both bulk and silicon on insulator devices are to be fabricated, especially if identical CMOS devices are fabricated simultaneously in both the bulk and the silicon on insulator portions of the die. Therefore, it is an object of the present invention to provide a method suitable for both fabricating silicon on insulator wafers and bulk silicon wafers having silicon on insulator regions. 
     The method of forming the single crystal silicon layer described above can leave a seam of mismatched crystal planes and non-perfect crystal structure where the growth edges meet. When the size of the single crystal islands are large enough for many devices to be fabricated, the seam region in the single crystal silicon in each island can be avoided. For example, gates would not be placed in these regions. However, if it is desirable to isolate individual devices in very small silicon islands, the silicon islands should be fabricated larger than required initially, and then subdivided along the seam boundaries. This may be accomplished by etching a trench in each of the silicon islands along the seam boundary and backfilling with a third dielectric fill. Therefore, it is a further object of the present invention to provide a method suitable for silicon on insulator regions having high quality crystal structure. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as preferred modes of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
     FIGS. 1 to  12  are partial cross-sectional views illustrating the steps of an embodiment of a method for forming an SOI structure according to the present invention; 
     FIG. 13 is a plan view of the SOI structure formed by the method shown in FIGS. 1 to  12 ; 
     FIGS. 14 to  17  are partial, cross-sectional views illustrating additional steps of an embodiment of the method for forming an SOI structure according to the present invention; 
     FIG. 18 is a plan view of the SOI structure formed by the method shown in FIGS. 1 to  12  after the additional steps shown in FIGS. 14 through 17 have been performed; 
     FIG. 19 is a partial, cross-sectional view of an alternative embodiment of the present invention; 
     FIG. 20 is a partial, cross-sectional view of an alternative embodiment of the present invention fabricated with additional steps; and 
     FIG. 21 is a partial, cross-sectional view of an alternative embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows single crystal &lt;100&gt; silicon substrate  10  having an upper surface  12 . Silicon substrate  10  is single crystalline as upper surface  12  will later act as a seed layer for epitaxial growth and to control etch characteristics during subsequent processing. In FIG. 2, first masking layer  20  has been formed on top of silicon substrate  10  and trenches  22  etched into layer  20  exposing upper surface  12  of silicon substrate  10 . First masking layer  20  may be formed, for example, by deposition of silicon oxide or silicon nitride. As shown in FIG. 3, trenches  30  have been etched in silicon substrate  10 . Silicon trenches  30  include sidewalls  32  and bottom  34 . Trenches  30  were formed by etching the silicon substrate with an anisotropic basic etch. When etched in strong bases, silicon in the &lt;111&gt; plane is not etched as readily as in the other planes, and sidewalls having an approximate slope of 35° normal to the &lt;100&gt; plane will be formed. One suitable etchant is an aqueous solution of tetramethylammonium hydroxide. A solution of 450 grams of the pentahydrate salt dissolved per liter of water will have a lateral etch rate of 0.4 microns/minute at 65° C. If trench  22  in first masking layer  20  is 4000 angstroms wide and trench  30  etched 4000 angstroms deep, overhang  24  will be 650 angstroms. This overhang  24  allows the same photomask to be used at the next masking step. Other etchants that will produce similar preferential etching include 20% aqueous potassium hydroxide saturated with isopropanol at 80° C. and ethylenediamine/pyrocatechol/water mixtures, both of which are well known to the industry. In FIG. 4, masking layer  20  has been removed, leaving silicon trenches  30  in silicon substrate  10 . 
     In FIG. 5, first dielectric layer  40  has been formed on silicon substrate  10 , filling trenches  30 . First dielectric layer  40  may be comprised, for example, of silicon oxide and if formed by chemical vapor deposition or low pressure chemical vapor deposition or other similar processes, will introduce relatively little stress into the silicon. As shown in FIG. 6, using a chemical-mechanical-polish process, first dielectric layer  40  has been polished so as to be coplanar with upper surface  12  of silicon substrate  10  forming dielectric regions  44  having upper surfaces  42 , in silicon substrate  10 . 
     Referring to FIG. 7, polysilicon layer  50  has been deposited on silicon substrate  10 . This layer will become the silicon in which active devices may be fabricated. In this example, the thickness of polysilicon layer  50  is approximately 2000 angstroms, although the thickness may vary. An annealing step of at least 400° C. is next performed to convert polysilicon layer  50  to a mono-crystalline layer. Conversion starts where regions  52  of polysilicon layer  50  contact upper surface  12  of silicon substrate  10  and progresses to central regions  54  of the polysilicon layer  50 . FIG. 8 shows completed mono-crystalline layer  60  having the same crystal orientation as silicon substrate  10 . An alternative method of creating silicon layer  60 , as shown in FIG. 8, is direct epitaxial growth starting with the structure shown in FIG.  6 . Epitaxial growth will occur starting from exposed upper surface  12  of silicon substrate  10 . A chemical-mechanical-polish may be performed to flatten upper surface  62  of silicon layer  60 . 
     In FIG. 9, second masking layer  70  has been formed on top of silicon layer  60 , and intersecting trenches  72  etched into layer  70  exposing upper surface  62  of silicon layer  60 . Second masking layer  70  may be formed, for example, by deposition of silicon oxide or silicon nitride. In FIG. 10 intersecting trenches  74  have been etched in silicon layer  60  forming silicon region  64  having upper surfaces  62  and sidewalls  66 . Trenches  74  may be etched using a reactive ion etch or other suitable process. A plurality of trenches  74  are etched perpendicular to each other in a grid pattern, although only one trench is shown in the sectional view of FIG. 10, leaving silicon regions  64  of silicon layer  60  exposed as mesas. Silicon regions  64  are fully landed on upper surface  42  of dielectric region  44 , so that outer portion  48  of upper surface  42  of first dielectric region  44  is exposed. It is an important feature of the invention that outer portion  48  of upper surface  42  is exposed all around silicon regions  64  in order that each silicon region  64  be isolated from the others and from silicon substrate  10 . Etching has also proceeded into silicon substrate  10  forming inner trenches  14 , in the same grid pattern as trenches  74 . In silicon substrate  10 , the inner trenches  14  have bottom surfaces  16  and sidewalls  18 . Formation of such inner trenches  14  is desirable but not essential. 
     Referring to FIG. 11, second dielectric layer  80  has been deposited on silicon substrate  10 . Second dielectric layer  80  may be comprised, for example, of silicon oxide and if formed by chemical vapor deposition or low pressure chemical vapor deposition or other similar processes, will introduce relatively little stress into the silicon. In FIG. 12, after a chemical-mechanical-polish process, second dielectric  80  has been polished so as to be coplanar with the upper surfaces  62  of silicon regions  64  forming intersecting dielectric trenches  84 . These dielectric trenches  84  have upper surfaces  82  coplanar with upper surfaces  62  of silicon regions  64 , lower peripheral surfaces  86  which are coextensive with outer portions  48  of upper surfaces  42  of dielectric regions  44 , and bottom surfaces  88 . Thus, silicon regions  64  are isolated from silicon substrate  10  by dielectric regions  44  and from each other by first intersecting dielectric trenches  84 . 
     FIG. 13 is a plan view of a section of substrate  10 . As shown, silicon regions  64  having sidewalls  66  are located on dielectric regions  44 , as discussed above in connection with FIG.  10 . As also shown, the sidewalls  18  of silicon substrate  10  define outer portions  48  of upper surfaces  42  of silicon regions  44 . Silicon regions  64  are surrounded by intersecting dielectric trenches  84 . 
     At this point conventional device formation may proceed by building devices in silicon regions  64 . Alternatively, additional steps may be performed as illustrated in FIGS. 14-17. Since silicon regions  64  were formed either by crystallization or epitaxial growth which started from the outside edges in, the quality of the crystal structure is likely to be poorer in the central portions of the silicon regions where the crystallization fronts or growth fronts meet, forming a plane of poorer crystal structure or mismatched crystal planes. This is illustrated in FIG. 14, which shows a silicon region  64  having edge portions  68  and central portion  66 . 
     As shown in FIG. 15, intersecting pairs of trenches  90  have been etched in central portion  66  of silicon region  64 . Trenches  90  are etched perpendicularly to one another in each silicon region  64  in order to divide the region  64 , in this case, into four sections, although only one is shown in the sectional view of FIG.  15 . Trenches  90  may be etched using a reactive ion etch or other suitable process. Trenches  90  are aligned to the central axes of silicon regions  64 . In FIG. 16, third dielectric layer  100  has been deposited. Third dielectric layer  100  may be comprised, for example, of silicon oxide and if formed by chemical vapor deposition or low pressure chemical vapor deposition or other similar processes, will introduce relatively little stress into the silicon. In FIG. 17, after a chemical-mechanical-polish process, third dielectric layer  100  has been polished so as to be coplanar with upper surfaces  62  of silicon regions  64  and upper surfaces  82  of silicon regions  84 , forming intersecting electric regions  104  having upper surfaces  102  coplanar with top surfaces  62  and  84 . 
     FIG. 18 is a plan view of a section of substrate  10 . As shown, silicon regions  64  having sidewalls  66  are located on dielectric regions  44 . As also shown, the sidewalls  18  of silicon substrate  10  define outer portions  48  of upper surfaces  42  of silicon regions  44 . Intersecting dielectric regions  104  divide silicon region  64  into four smaller silicon sections  68 . 
     At this point, conventional device formation may proceed. The processes described above may be performed over an entire semiconductor die or just a portion of the die, allowing mixed conventional and silicon on insulator devices. 
     In a second embodiment trenches  30  shown in FIG. 3 have been etched using a directional reactive ion etch or other suitable process, producing trench sidewalls  32  having substantially vertical sides as shown in FIG.  19 . The silicon substrate need not have a &lt;100&gt; crystal orientation. Otherwise, the processes are substantially the same as those previously described. The resultant structures are shown in FIG. 20 when the processes shown in FIGS. 1,  2 ,  19 , and  4  through  12  have been performed and in FIG. 21 when the additional process steps shown in FIGS. 14 through 17 have been performed. Two differently sized masks are required in order to ensure silicon regions  64  are fully landed on dielectric regions  44 . 
     The description of the embodiments of the present invention is provided above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.