Abstract:
Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense amplifiers to save layout area. The write drivers for the two ports are used to write into all of the first port&#39;s bitlines. The sense amplifiers for the two ports are used to read from all of the second port&#39;s bitlines. A memory block can to support true dual port (TDP) and simple dual port (SDP) operation using substantially less write drivers and sense amplifiers.

Description:
BACKGROUND OF THE INVENTION 
   This invention relates to dual port memory circuits, and more particularly, to dual port memory circuits that have shared write drivers and sense amplifiers. 
   A configurable memory block in field programmable gate array (FPGA) is usually built to support various read and write operation modes, such as true dual port (TDP), simple dual port (SDP), and single port (SP) modes. The operation mode is configured depending on the user application. A TDP memory supports two write operations, one read and one write operation, or two read operations at one time. 
   A typical dual port memory has two independent input and output data paths and address decoders. A dual port memory block also has two independent write bitline drivers and two independent sense amplifiers that support two simultaneous write or two simultaneous read operations on a single column of memory cells. A SDP memory supports one read and one write operation at the same time. A SDP memory can be built from a TDP memory by using one port to write and the other port to read. 
   The number of input and output paths of a configurable memory block in a FPGA fabric is fixed. The maximum data width that can be supported in different operation mode varies. For example, if the number of the input and output paths for a memory block is 36 each, the maximum data width that can be supported in TDP mode is 18 bits, and the maximum data width that can be supported in SDP mode is 36 bits. Hence, a configurable memory in a FPGA fabric often supports an N-bit data width for TDP mode, and 2N-bit data width for SDP mode to fully utilize the available input/output path resources. 
   A typical configurable memory block that supports N-bit TDP and 2N-bit SDP modes includes an input/output path with input and output registers, and other logics to control the input and output data path. Two independent column decoders, called Port A and Port B column decoders, are used for TDP and SDP mode operation. The Port A column decoder controls which column of memory cells to access through Port A decoded from the Port A column address. The Port B column decoder controls which column of memory cells to access through Port B decoded from the Port B column address. 
   A width decoder decodes the configurable input and output data width to the memory array. Together with the column decoder, the input and output data is mapped to the correct memory column. A sense amplifier block includes precharge circuitry and the actual sense amplifiers. The differential bitlines are pre-charged to a high value before read. During evaluation, one of the differential bitlines starts to discharge. The sense amplifier senses and amplifies the differential voltage. 
   Write driver circuitry includes the tri-state write drivers with other write control logic. Two independent row decoders (for Port A and Port B) are used to control which row of memory cells to access for each port. The memory array is organized as M rows×36 columns of dual port RAM cells. 
   Each column of the RAM cells is accessible through a Port A write driver, a Port B write driver, a Port A sense amplifier, a Port B sense amplifier, and the Port A and Port B column and row decoder. Each port has 36 write drivers and 36 sense amplifiers to access 36 bitlines associated with each port. Hence, there are total of 72 write drivers and 72 sense amplifiers in one memory block. 
   When the memory block is configured in TDP, the maximum data width is 18 bits for each port. 18 out of the 36 input paths are used for the Port A input data, and the other 18 input paths are used for the Port B input data. The 18-bit input data for each port is fed to 18 of the 36 write drivers for each port. Only 18 out of the 36 write drivers for each port are enabled at one time during a write operation. For the output path, 18 out of the 36 outputs are used for Port A output data, and the other 18 outputs are used for Port B output data. Only 18 out of the 36 sense amplifiers are enabled for each port during read. 
   When the memory block is configured in SDP mode, the maximum data width is 36 bits. Port A is always used as the write port, and Port B is always used as the read port. A maximum of 36 bits of data is written to the RAM array through the 36 Port A write drivers. Writing in SDP is only done through the Port A bitlines. Port B write drivers are always disabled in this mode. 36-bit data is read from the array through the 36 Port B sense amplifiers. Reading in SDP is only done through Port B bitlines. Port A sense amplifiers are always disabled in this mode. 
   There are total 72 write drivers and 72 sense amplifiers in this design. The write drivers and sense amplifiers are usually large devices that occupy large layout area that make the bit per area density number larger. The overhead becomes more significant for a chip that is area or cost sensitive. Although there are 72 write drivers and 72 sense amplifiers in this design, only as many as 36 write drivers and 36 sense amplifiers are active at any time during a read or write operation. In TDP mode, up to 18 Port A write drivers, 18 Port B write drivers, 18 Port A sense amplifiers, and 18 Port B sense amplifiers are active. In SDP mode, up to 36 Port A write drivers and 36 Port B sense amplifiers are active. 
   Therefore, there is a need to provide dual port memory blocks that provide TDP and SDP operation that has a reduced layout area overhead. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention provides dual port memory blocks that have a reduced layout area overhead. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense amplifiers to save layout area. 
   The write drivers for the two ports are used to write into all of the first port&#39;s bitlines. The sense amplifiers for the two ports are used to read from all of the second port&#39;s bitlines. The techniques of the present invention allow a memory block to support true dual port (TDP) and simple dual port (SDP) operation using substantially less write drivers and sense amplifiers. 
   Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates an example of a typical SRAM memory cell. 
       FIG. 2  illustrates dual port memory block according to a first embodiment of the present invention. 
       FIG. 3  illustrates sense amplifiers, write drivers, and multiplexers for selected columns of memory cells according to an embodiment of a memory array of the present invention. 
       FIGS. 4A–4C  illustrate write operations in TDP and SDP modes in a memory block of the present invention. 
       FIGS. 5A–5C  illustrate read operations in TDP and SDP modes in a memory block of the present invention. 
       FIG. 6  illustrates the signals that control the multiplexers and the precharge circuitry in a memory array, according to an embodiment of the present invention. 
       FIG. 7  is a simplified block diagram of a programmable logic device that can be used with the techniques of the present invention. 
       FIG. 8  is a block diagram of an electronic system that can implement embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  illustrates an example of a typical static random access memory (SRAM) cell. The SRAM cell includes cross coupled inverters  10  and  11  and pass transistors  12 – 15 . Inverters  10  and  11  store a bit of digital data. Pass transistors  12 – 15  control access to inverters  10 – 11  from word lines for ports A and B (WLA and WLB) and from the differential bitlines for ports A and B (DLA, DLB, NDLA and NDLB). 
     FIG. 2  illustrates a dual port memory block according to a first embodiment of the present invention. The dual port memory block includes an input/output data path  101  that receives input and output data. The example shown in  FIG. 2  includes 36 data input lines and 36 data output lines. The dual port memory block also includes a column decoder  102  for port A, a column decoder  103  for port B, a width decoder  104 , a block  105  of sense amplifiers, a block  106  of write drivers, multiplexers  107 , an array  108  of memory cells, a row decoder  110  for port B, and a row decoder  111  for port A. 
   The memory cells can be SRAM cells as shown in  FIG. 1  or EEPROMs, FLASH, or other suitable types of memory cells. Sense amplifier block  105  includes Port A sense amplifiers and Port B sense amplifiers. Write driver block  106  includes Port A write drivers and Port B write drivers. 
   In the example shown in  FIG. 2 , block  105  has 36 sense amplifiers that are fed to 36 columns of RAM array  108  through multiplexers  107 . The memory block includes 18 sense amplifiers associated with Port A, and 18 sense amplifiers that are associated with Port B. 
   Port A sense amplifiers can read data from Port A bitlines of two adjacent columns of memory during TDP mode operation. Port A sense amplifiers can also read data from Port B bitlines of the first column during SDP mode operation. Port B sense amplifiers can read data from Port B bitlines of two adjacent columns during TDP Mode operation. Port B sense amplifiers can also read data from Port B bit lines of the second column during SDP mode operation. 
   Block  106  has 36 write drivers that feed into 36 columns of the memory array. 18 write drivers are associated with Port A, and 18 write drivers are associated with Port B. Memory blocks of the present invention have N columns of memory cells, N sense amplifiers, and N write drivers. Although 36 sense amplifiers, 36 write drivers, and 36 columns of memory cells are shown in the example of  FIG. 2 , it should be understood that any number N of write drivers, sense amplifiers, and columns of memory cells can be used with the present invention. 
   Port A write drivers can write data to Port A bitlines of two adjacent columns during TDP mode. Port A write drivers can also write data to Port A bitlines of the first column during SDP mode. Port B write drivers can write data to Port B bitlines of two adjacent columns during TDP mode. Port B write drivers can also write data to Port A bitlines of the second column during SDP mode operation. 
   Multiplexers  107  connect write drivers  106  and sense amplifiers  105  to the correct RAM array column and input/output port. The memory array  108  is arranged as M rows×36 columns. 
   In the embodiment of  FIG. 2 , there are only 18 columns of write drivers and 18 columns of sense amplifiers for each port. The total number of write drivers is 36, and the total number of sense amplifiers is 36. Prior art dual port memories had 72 write drivers and 72 sense amplifiers for a memory array of the same size. In a typical prior art design, a write driver and sense amplifier of a particular column can only access the bitline of their own column and port (e.g. Column  0  Port A write driver and sense amplifier can only access column  0  Port A bitline). 
   In contrast, each write driver and sense amplifier in  FIG. 2  can access the same port of the adjacent column or the other port of the same column depending on the operation mode configured. This is implemented by adding multiplexers in block  107  between the write drivers  106  and the memory array  108 . The multiplexers add extra area to the design, but the additional area is small compared to the area saved by reducing the number of write drivers and sense amplifiers in blocks  105 – 106 . Moreover, the extra multiplexers in block  107  are shared by both write drivers and sense amplifiers to access to the memory array. 
   Each column of write drivers and sense amplifiers is shared by two columns of memory cells. In the embodiment of  FIG. 2 , the columns of memory cells are organized in an alternating order  0 ,  18 ,  1 ,  19 ,  2 ,  20  . . .  16 ,  34 ,  17 ,  35  so that each write bitline driver/sense amplifier column can access the respective least significant bit (LSB) and most significant bit (MSB) more easily. 
   During TDP mode operation, each write driver or sense amplifier can access two memory columns from its own port. The multiplexers in block  107  serve as a second stage column decoder to write or read the data for each port. The MSB bit of the column address of each port generates a control signal that determines which column will be accessed during the read write operation. During SDP, both Port A and Port B write drivers and sense amplifiers are used at the same time to access the whole 36-bit data from the memory array. The details of the data path and the control mechanism of the read and write process are explained below with respect to  FIG. 3 . 
     FIG. 3  illustrates write drivers such as drivers  203 – 204  that are used to write data bits into the memory cells, and sense amplifiers such as amplifiers  201 – 202  that amplify the output signals of the memory cells. The memory blocks of  FIGS. 2 and 3  have 36 sense amplifiers and 36 write drivers that are connected to 36 columns of memory cells through multiplexer block  107 . 
   Block  107  includes tristate drivers coupled to Port A and Port B bitlines for each column of memory cells. For example, tristate drivers  210 – 212  are coupled to bitlines DLA 0  and DLB 0 , and tristate drivers  221 – 223  are coupled to bitlines DLA 18  and DLB 18 . 
   The tristate drivers are controlled by the column address signals. When the column address signals select memory cell columns  0 – 17 , tristate driver  210  couples Port A write driver  203  to bitline DLA 0 , and tristate driver  212  couples Port B write driver  204  to bitline DLB 0 . When the column address signals select memory cell columns  18 – 35 , tristate driver  221  couples Port A write driver  203  to bitline DLA 18 , and tristate driver  223  couples Port B write driver  204  to bitline DLB 18 . 
   Further details of true dual port (TDP) mode and simple dual port (SDP) mode are now discussed with respect to  FIGS. 4A–4C  and  5 A– 5 C.  FIGS. 4A and 4B  illustrate write operations in TDP mode for 2 of the columns of memory cells  401 – 402 . During TDP mode, each Port A write driver has access to two columns of Port A bitlines, and each Port B write driver has access to two columns of Port B bitlines. 
   As shown by the bolded lines in  FIG. 4A , tristate driver  210  couples Port A write driver  203  to bitline DLA 0  in response to a selected Port A column address. Tristate driver  212  couples Port B write driver  204  to bitline DLB 0  in response a selected Port B column address. Bitlines DLA 0  and DLB 0  are both coupled to memory cell column  401 . Therefore, write drivers  203  and  204  are able to write data to column  401  in TDP mode. 
   As shown by the bolded lines in  FIG. 4B , tristate driver  221  couples Port A write driver  203  to bitline DLA 18  in response to a selected Port A column address. Tristate driver  223  couples Port B write driver  204  to bitline DLB 18  in response to a selected Port B column address. Bitlines DLA 18  and DLB 18  are both coupled to memory cell column  402 . Thus, write drivers  203 – 204  are able to write data to column  402  in TDP mode. 18-bit data from Port A and 18-bit data from Port B can be written to the memory array at any time during TDP Mode. 
   During SDP operation, Port A write bitline drivers access 18-bit LSB data and Port B write bitline drivers access 18-bit MSB data at the same time. Port B inputs DINB[ 17 : 0 ] are used for data input bits DIN[ 35 : 18 ], and Port A inputs DINA[ 17 : 0 ] are used for data input bits DIN[ 17 : 0 ] during SDP mode. The write operation only goes through Port A bitlines. The Port A drivers are used to write the first half (LSB) of the memory array, and the Port B write bitline drivers are used to write to the second half (MSB) of the memory array. 36-bit data can be written during the SDP operation. 
     FIG. 4C  illustrates write operations in SDP mode for memory cells columns  401 – 402 . Tristate driver  210  couples Port A write driver  203  to bitline DLA 0  in response to a selected Port A column address. Tristate driver  222  couples Port B write driver  204  to bitline DLA 18  in response to a selected Port B column address. The bolded lines in  FIG. 4C  illustrate these connections. Thus, write drivers  203 – 204  are able to write data to columns  401 – 402 , respectively, in SDP mode. 
     FIGS. 5A and 5B  illustrate read operations in TDP mode for memory cells columns  401 – 402 . During TDP mode, each Port A sense amplifier has access to two columns of Port A bitlines, and each Port B sense amplifier has access to two columns of Port B bitlines. 
   During TDP mode, each Port A sense amplifier can access one of the two Port A bitlines, and each Port B sense amplifier can access one of the two Port B bitlines depending on the Port A and Port B column address. When the column address signals select memory cell columns  0 – 17 , Port A sense amplifier  201  reads out data from bitline DLA 0  through tristate driver  210 , and Port B sense amplifier  202  can read out data from bitline DLB 0  through tristate driver  212  as shown by the bolded lines in  FIG. 5A . 
   When the column address signals select memory cell columns  18 – 35 , Port A sense amplifier  201  reads out data from bitline DLA 18  through tristate driver  221 , and Port B sense amplifier  202  reads out data from bitline DLB 18  through tristate driver  223  as shown by the bolded lines in  FIG. 5B . 18-bit data from Port A and 18-bit data from Port B can be read from the memory array at any time during TDP Mode. 
     FIG. 5C  illustrates read operations in SDP mode for memory cell columns  401 – 402 . During SDP operation, Port A sense amplifiers read the 18-bit LSB data, and Port B sense amplifiers read the 18-bit MSB data. Sense amplifier outputs DOUTB[ 17 : 0 ] serve as data output bits DOUT[ 35 : 18 ], and sense amplifier outputs DOUTA[ 17 : 0 ] serve as data output bits DOUT[ 17 : 0 ] during SDP mode. For example, Port A sense amplifier  201  reads data from bitline DLB 0  through tristate driver  211 , and Port B sense amplifier  202  reads data from bitline DLB 18  through tristate driver  223  as shown by the bolded lines in  FIG. 5C . 
   The read operation during SDP mode only goes through Port B bitlines. Port A sense amplifiers are used to read the first half (LSB) of the memory array through Port B bitlines, and Port B sense amplifiers are used to read from the second half (MSB) of the memory array through Port B bitlines. 36-bit data can be read at any time during the SDP operation. 
   The control signals that control the multiplexers during write and read operation are now discussed.  FIG. 6  shows the signals that control the multiplexers for memory cell columns  0  and  18 . The multiplexer control signals for columns  0  and  18  include signals R 36  and a_col 0 , a_col 1 , W 36 , b_col 0 , and b_col 1 . The multiplexers for the other columns of memory cells have corresponding control signals. Signals R 36  and W 36  are set to ‘1’ only when the memory is configured as a 36-bit width memory in SDP mode. Otherwise, signals R 36  and W 36  are both set to ‘0’. 
   The precharge signals a_prechg and b_prechg are generated by the read/write control logic (not shown). Precharge signals a_prechg and b_prechg are only set to ‘1’ during pre-charge operation for each port. When a_prechg signal is ‘1’ and both a_col 0  and a_col 1  signals are set to ‘1’, the Port A pre-charge transistor  301  can pre-charge both DLA 0  and DLA 18 . When b_prechg signal is ‘1’, both b_col 0  and b_col 1  are set to ‘1’, so that the Port B pre-charge transistor  302  can pre-charge both DLB 0  and DLB 18 . This pre-charge scheme is used for both TDP and SDP operation. One pre-charge circuit is always used to pre-charge two columns of bitlines of its own port. 
   Except during the pre-charge operation, each write bitline driver and each sense amplifier selectively access only one bitline. When W 36  is set to ‘0’ for TDP mode, the a_col 0  signal and the a_col 1  signal depend on the MSB bit of the Port A column address acol[MSB]. If acol[MSB] is ‘0’, the a_col 0  signal is set to ‘1’, and the a_col 1  signal is set to ‘0’ so that the Port A write driver or sense amplifier can access bitline DLA 0  through tristate driver  210 . If acol[MSB] is ‘1’, the a_col 0  signal is set to ‘0’, and the a_col 1  signal is set to ‘1’ so that the Port A write driver or sense amplifier can access DLA 18  through tristate driver  221 . 
   The same concept applies to the Port B operation. When R 36  is set to ‘0’ for TDP mode, the b_col 0  and b_col 1  signals depend on the MSB bit of the Port B column address bcol[MSB]. If bcol[MSB] is ‘0’, the b_col 0  signal is set to ‘1’, and the b_col 1  signal is set to ‘0’ so that the Port B write driver or sense amplifier can access bitline DLB 0  through tristate driver  212 . If bcol[MSB] is ‘1’, the b_col 0  signal is set to ‘0’, and the b_col 1  signal is set to ‘1’ so that the Port B write driver or sense amplifier can access DLB 18  through tristate driver  223 . 
   If the W 36  and R 36  signals are both set to ‘1’ for SDP mode, the a_col[ 1 : 0 ] and b_col[ 1 : 0 ] signals do not depend on the column address. The a_col 0  signal is set to ‘1’ so that the Port A write driver  203  can access bitline DLA 0  through tristate driver  210 . When signal a_col 0  is set to ‘0’ and W 36  is ‘1’, Port B write driver  204  has access to bitline DLA 18  through tristate driver  222 . 
   When signal b_col 0  is set to ‘0’ to and R 36  set to ‘1’, Port A sense amplifier  201  has access to bitline DLB 0  through tristate driver  211 . When signal b_col 1  is set to ‘1’, Port B sense amplifier  202  as access to bitline DLB 18  through tristate driver  223 . Pass gates  303 – 304  are added to solve contention in the data path during SDP operation. Table 1 below is a truth table that generates the multiplexer control signals a_col 0 , a_col 1 , b_col 0 , and b_col 1 . 
   
     
       
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
           
           
             
               a_prechg 
               W36 
               acol[MSB] 
               a_col0 
               a_col1 
             
             
                 
             
             
               1 
               X 
               X 
               1 
               1 
             
             
               0 
               0 
               0 
               1 
               0 
             
             
               0 
               0 
               1 
               0 
               1 
             
             
               0 
               1 
               X 
               1 
               0 
             
             
                 
             
             
               b_prechg 
               R36 
               bcol(MSB) 
               b_col0 
               b_col1 
             
             
                 
             
             
               1 
               X 
               X 
               1 
               1 
             
             
               0 
               0 
               0 
               1 
               0 
             
             
               0 
               0 
               1 
               0 
               1 
             
             
               0 
               1 
               X 
               0 
               1 
             
             
                 
             
           
        
       
     
   
   A configurable memory of the present invention is designed to support various operating modes such as TDP and SDP modes and the maximum data width allowed by the input and output resources. The techniques of the present invention require half the write drivers and sense amplifiers required by many prior art dual port memory blocks. Saving half of the write drivers and sense amplifiers results in a significant area savings, because the write drivers and sense amplifiers are usually made to have a large area for higher performance. 
   The present invention also requires half of the column decoder and width decoder circuitry, because the number of write and read logic columns is reduced by half, saving some additional area. A configurable 4K-bit memory design using the techniques of the present invention can achieve up to 10% area saving compared to prior art designs. A memory of the present invention can also save standby power, because the number of write drivers and sense amplifiers is reduced by half. 
     FIG. 7  is a simplified partial block diagram of an example of a PLD  700 . PLD  700  is an example of a programmable logic integrated circuit in which a memory block of the present invention can be placed. It should also be understood that the present invention can be implemented in numerous types of integrated circuits other than programmable logic integrated circuits such as field programmable gate arrays (FPGAs) and programmable logic arrays. PLD  700  includes a two-dimensional array of programmable logic array blocks (or LABs)  702  that are interconnected by a network of column and row interconnects of varying length and speed. LABs  702  include multiple (e.g., 10) logic elements (or LEs). 
   An LE is a programmable logic block that provides for efficient implementation of user defined logic functions. PLD  700  has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration. 
   PLD  700  also includes a distributed memory structure including RAM blocks of varying sizes provided throughout the array. The RAM blocks include, for example, 512 bit blocks  704 , 4K blocks  706  and a block  708  that provides 512K bits of RAM. These memory blocks can also include shift registers and FIFO buffers. 
   PLD  700  further includes digital signal processing (DSP) blocks  710  that can implement, for example, multipliers with add or subtract features. I/O elements (IOEs)  712  located, in this example, around the periphery of the device support numerous single-ended and differential I/O standards. It is to be understood that PLD  700  is described herein for illustrative purposes only and that the present invention can be evaluate many different types of PLDs, FPGAs, and the like. 
   While PLDs of the type shown in  FIG. 7  provide many of the resources required to implement system level solutions, the present invention can also benefit systems wherein a PLD is one of several components.  FIG. 8  shows a block diagram of an exemplary digital system  800 , for which the present invention can be implemented. System  800  can be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems can be designed for a wide variety of applications such as telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, Internet communications and networking, and others. Further, system  800  can be provided on a single board, on multiple boards, or within multiple enclosures. 
   System  800  includes a processing unit  802 , a memory unit  804  and an I/O unit  806  interconnected together by one or more buses. According to this exemplary embodiment, a programmable logic device (PLD)  808  is embedded in processing unit  802 . PLD  808  can serve many different purposes within the system in  FIG. 8 . PLD  808  can, for example, be a logical building block of processing unit  802 , supporting its internal and external operations. PLD  808  is programmed to implement the logical functions necessary to carry on its particular role in system operation. PLD  808  can be specially coupled to memory  804  through connection  810  and to I/O unit  806  through connection  812 . 
   Processing unit  802  can direct data to an appropriate system component for processing or storage, execute a program stored in memory  804  or receive and transmit data via I/O unit  806 , or other similar function. Processing unit  802  can be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, programmable logic device programmed for use as a controller, network controller, and the like. Furthermore, in many embodiments, there is often no need for a CPU. 
   For example, instead of a CPU, one or more PLDs  808  can control the logical operations of the system. In an embodiment, PLD  808  acts as a reconfigurable processor, which can be reprogrammed as needed to handle a particular computing task. Alternately, programmable logic device  808  can itself include an embedded microprocessor. Memory unit  804  can be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, PC Card flash disk memory, tape, or any other storage means, or any combination of these storage means. 
   While the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes, and substitutions are intended in the present invention. In some instances, features of the invention can be employed without a corresponding use of other features, without departing from the scope of the invention as set forth. Therefore, many modifications may be made to adapt a particular configuration or method disclosed, without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments and equivalents falling within the scope of the claims.