Abstract:
An electronic apparatus having a multiplicity of operably connected semiconductor integrated circuits (ICs) arranged on a substrate and operable at different operating voltages. The interface voltages between two ICs is set to the lowest operating voltage of the ICs. Each IC other than those operating at the lowest operating voltage has an input circuit for converting the lowest operating voltage of an input signal to its operating voltage and an output circuit for converting the voltage of its output signal to the lowest operating voltage.

Description:
FIELD OF THE INVENTION 
     The invention relates to an electronic apparatus incorporating a multiplicity of semiconductor integrated circuits (ICs) arranged on an substrate which operate at different operating voltages and a semiconductor IC for use in such electronic apparatus. 
     BACKGROUND OF THE INVENTION 
     Recent advance in semiconductor technology has enabled fabrication of large scale integrated (LSI) semiconductor circuits. The maximum allowable level of the operating voltage for such LSI is limited more than ever to a lower operating voltage, for example from conventional 5 Volts to 3 Volts or to an even lower voltage of 2 Volts. Besides, a multiplicity of LSIs used in an electronic apparatus often have different operating voltages. In order to allow transmission of signals between two LSIs running at two different operating voltages, an interface is required to adjust or absorb the difference in the operating voltages. 
     Conventionally, adjustment of the voltages is done by converting the lower operating voltage of one LSI to a higher voltage to match with the operating voltage of other conventional (mostly well established) LSI. 
     Consequently, for an electronic apparatus having a multiplicity of LSIs which are operated at different operating voltages, it is a common practice to raise the lower voltage (2 Volts for example) of the interface section of the LSIs to the higher operating voltage of the other LSI by making oxide layers of the gates thicker or making the channels longer, or by utilizing dedicated special transistors. 
     However, these resolutions inhibit high-degree integration of low voltage LSIs, sacrificing the merit of up-to-date large scale integration technology, and resulting in not only increase of chip areas but also additional complexity to the manufacturing processes, and hence increases production cost of the electronic apparatus. 
     SUMMARY OF THE INVENTION 
     In accordance with one aspect of the invention, there is provided an electronic apparatus incorporating a multiplicity of operably connected semiconductor integrated circuits (ICs) arranged on a substrate which operate at different operating voltages, wherein all the interface voltages between operably connected ICs are set to the lowest operating voltage. 
     Each of the ICs other than those operating at the lowest operating voltage is provided with: 
     an input circuit for converting the lowest operating voltage of a signal input thereto from another IC to its own operating voltage; and 
     an output circuit for converting the voltage of the signal to be output therefrom to the lowest operating voltage. 
     In accordance with another aspect of the invention, there is provided an electronic apparatus incorporating a multiplicity of operably connected semiconductor integrated circuits (ICs) arranged on a substrate which operate at different operating voltages, wherein 
     the interface voltage between any two operably connected ICs operating at two operating voltages is the lower operating voltage of the two. 
     Each of the ICs other than those operating at the lower operating voltage is provided with: 
     an input circuit for converting a lower operating voltage of a signal input thereto from another IC to its own operating voltage; and 
     an output circuit for converting the voltage of the signal to be output therefrom to a required lower operating voltage. 
     In this arrangement, although the electronic apparatus incorporates a multiplicity of LSIs that operate at different operating voltages, the most highly integrated IC having the lowest operating voltage can be interfaced with its own operating voltage, so that the electronic apparatus can enjoy the merit of the large scale integration. 
     It is noted that those LSIs not operating at the lowest operating voltage can be interfaced with other LSIs at a lower voltage than their own operating voltages using input/output circuits. 
     Since the interfacing is done at a low voltage, energy loss due to electromagnetic interference (EMI) for example can be reduced accordingly. 
     If all the interface voltages for the operably connected LSIs are set to the lowest operating voltage of the LSIs, then all the LSIs can be interfaced through the their input and output circuits connected at the same lowest voltage, thereby simplifying the design of the input/output circuits. 
     When the interface voltage for any two operably connected LSIs operating at two different operating voltages is set to the lower one of the two, the LSI having a lower operating voltage needs no input circuit or output circuit, thereby advantageously reducing the number of input/output circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a first embodiment of an electronic apparatus incorporating a multiplicity of LSIs according to the invention. 
     FIG. 2 is a schematic diagram of a second embodiment of an electronic apparatus incorporating a multiplicity of LSIs according to the invention. 
     FIG. 3 is a circuit diagram of an I/O circuit of an output circuit. 
     FIG. 4 is a circuit diagram of an I/O circuit of an input circuit. 
     FIG. 5 shows an exemplary interface voltage supply means. 
     FIG. 6 shows an LSI having an I/O register and an example of operational modes stored in the I/O register. 
     FIG. 7 shows an example of an internal voltage generator of an LSI. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     What follows is a description of preferred embodiments of an electronic apparatus incorporating a multiplicity of LSIs and LSIs for use in such electronic apparatus in accordance with the invention, as shown in the accompanying drawings. 
     Referring to FIG. 1, there is shown a first embodiment of an electronic apparatus incorporating a multiplicity of LSIs, illustrating the concept of the invention. 
     In FIG. 1, the electronic apparatus is shown to have four LSIs, indicated as LSI 1 , LSI 2 , LSI 3 , and LSI 4 , respectively, mounted on a substrate  10 . These LSIs operate at respective operating voltages V 1 , V 1 , V 2 , and V 3 . In the example shown herein, V 1  is 5 Volts; V 2  is 3 Volts; and V 3  is 2 Volts. However, the operating voltages of the LSIs are not limited in number to three, nor to the three voltages. Also, the number of the LSIs mounted on the substrate  10  is arbitrary. The number of the LSIs that operates at the same operating voltage is also arbitrary. 
     The substrate  10  is provided with power lines Lv 1  (for 5 Volts), Lv 2  (for 3 Volts), and Lv 3  (for 2 Volts) for supplying each of the LSI on the substrate with the operating voltages V 1 , V 2 , and V 3 , respectively. Each of the LSIs, LSI 1 -LSI 4 , are coupled to the power lines to obtain power for its own operation and power for performing required interface with other LSIs. 
     In the example shown in FIG. 1, the interface voltage between any two LSIs on the substrate  10  is commonly set to the lowest operating voltage V 3  (2 Volts). 
     Consequently, except for the LS 14  that operates at the lowest operating voltage V 3  (2 Volts), each of the LSIs requires an output circuit for converting its own operating voltage, V 1  (5 Volts) or V 2  (3 Volts), of the output signal to the lowest operating voltage V 3 , and an input circuit for converting the lowest voltage V 1  of the input signal to their own operating voltage. These input/output circuits are provided in the respective input/output (I/O) interface circuits of each LSI. 
     Thus, advantageously the interface voltage for the most highly integrated LSI, LSI 4 , are set to the operating voltage of its own, so that the merit of large scale integration can be fully effected for the electronic apparatus. 
     It would be appreciated that, since all the interface voltages are set to the lowest voltage V 3 , radiative energy loss e.g. EMI can be reduced. Also, since all the input and output circuits of the LSI except for the one having the lowest operating voltage operate at the lowest operating voltage, design of the input and the output circuits is simple. Further, since the interface voltage is lower than the operating voltage of the LSI, the input and the output circuits may be easily provided in the LSI. 
     FIG. 2 is a schematic diagram of a second embodiment of an electronic apparatus incorporating a multiplicity of LSIs according to the invention. 
     As in the first embodiment, the second embodiment is shown to have four LSIs LSI 1 -LSI 4  mounted on a substrate  20  that operate at respective operating voltages V 1 , V 1 , V 2 , and V 3  as shown in FIG.  2 . In the example shown herein, V 1  is 5 Volts; V 2  is 3 Volts; and V 3  is 2 Volts. However, the operating voltages of the LSIs are not limited in number to three, nor limited to these voltages. They can be all different. Also, the number of the LSIs mounted on the substrate  20  is arbitrary. The substrate  20  is provided with power lines Lv 1  (for 5 Volts), Lv 2  (for 3 Volts), and Lv 3  (for 2 Volts) for supplying each of the LSI on the substrate with the operating voltages V 1 , V 2 , and V 3 , respectively. Each of the LSIs, LSI 1 -LSI 4 , are coupled to these power lines to obtain power for its own operation and for performing interface with other LSIs. 
     In the example shown in FIG. 2, the interface voltage between any two LSIs operating at two different voltages is set to the lower operating voltage of the two. Thus, the interface voltage for the LSI 1  and LSI 2  is taken as V 1 , which is the lower operating voltages of the two LSIs. Similarly, the interface voltage for the LSI 1  and LSI 3  is V 2 , and the interface voltage for the LSI 1  and LSI 4  is V 3 , as well as the interface voltage for the LSI 3  and LSI 4 . 
     Hence, except for the LSI 4  that operates at the lowest operating voltage V 3  (2 Volts), the rest of the LSIs must have an input circuit to convert the interface voltage V 2  (3 Volts) or V 3  (2 Volts) to their (higher) operating voltages when the LSI receives an input signal from another LSI operating at a lower voltage, and/or an output circuit to convert the voltage of the signal they output to a lower interface voltage V 2  or V 3  when the LSI outputs the signal to another LSI operating at a lower operating voltage. These input/output circuits are provided in the respective I/O interface circuits of the respective LSIs. 
     Since the interface voltages between arbitrary two LSIs are set to the operating voltages of the two LSIs in the manner as described, the most highly integrated LSI, LSI 4 , can be interfaced with its own operating voltage V 3  (2 Volts). Therefore, the merit of large scale integration can be fully effected in the electronic apparatus. 
     The fact that the interface voltage for the two LSIs is set to the lower one of the their operating voltages implies that the LSI having the lower operating voltage does not require an input/output circuit, thereby having less number of input and output circuits, as compared with the first embodiment. 
     Further, in the example shown herein, the interface voltage between a pair of two LSIs (other than the LSI 4 ) operating at two different voltages is V 2  or V 3 , which is lower than their operating voltages V 1  or V 2 , respectively. 
     It would be understood that the electronic apparatus as shown in FIGS. 1 and 2 and an external electronic apparatus can be the interfaced by the lowest operating voltage V 3  (2 Volts). It is also possible to use individual operating voltages V 1 -V 3  in interfacing each of LSIs with an external LSI. 
     As an example, FIGS. 3 and 4 illustrate an output circuit and an input circuit, respectively, formed in the I/O circuit of the LSI of FIGS. 1 and 2 other than those that runs at the lowest operating voltage V 1 . Although MOSFETs are used in the example shown in FIGS. 3 and 4, other types of switching elements such as bipolar transistors may be used equally well. 
     In the output circuit  30  shown in FIG. 3, transistors Q 31 -Q 37  are MOSFETs. Of these, the transistors Q 31 , Q 33 , and Q 35  each marked with a circle are P-channel MOSFETs. The rest are N-channel MOSFETs. The transistors Q 31  and Q 32  forming an inverter circuit is supplied with the operating voltage V 1 . An interface voltage supply circuit  31  is connected with a cross-linked circuit forming by transistors Q 33 -Q 37 , so that one of the three interface voltages V 1 -V 3  is selectively supplied. Incidentally, in cases where the interface voltage of any LSI is the lowest operating voltage V 3  (2 Volts), as in the first embodiment, the interface voltage supply circuit  31  outputs the lowest voltage V 3 . 
     The cross-linked circuit includes series transistors Q 33  and Q 34 , which is connected in parallel with another set of series transistors Q 35  and Q 36 , with the gate of the transistor Q 33  connected to the node of the series transistors Q 35  and Q 36 , and the gate of the transistor Q 35  connected to the node of the series transistors Q 33  and Q 34 . When the gates of the transistors Q 34  and Q 36  are supplied with an inverted signal and a non-inverted signal, respectively, the output signal is provided at the node of the series transistors Q 33  and Q 34 . An auxiliary transistor Q 37  is provided to accelerate the operating speed of the cross-linked circuit. The transistor Q 37  is optional. 
     Suppose now that the output circuit  30  is provided with a high (H) level signal (referred to as signal H) of voltage V 1  or a low (L) level signal (referred to as signal L) of voltage Vss (0 Volt) from an internal circuit. When signal H is supplied to input end of the output circuit  30 , the transistor Q 31  is turned OFF, and the transistor Q 32  is turned ON, so that the transistor Q 34  is turned OFF, while the transistor Q 36  is turned ON. As a result, the cross-linked transistors Q 33  and Q 35  are turned ON and OFF, respectively. Thus, with the transistor Q 33  turned ON and the transistor Q 34  turned OFF, the voltage selected by the interface voltage supply circuit  31  from the operating voltages V 1 -V 3  is supplied to the output node, so that the signal H having the selected operating voltage is output from the terminal OUT to other LSIs as the interface voltage therefor. 
     On the other hand, when signal L is supplied to the input end of the circuit  30 , the transistor Q 31  is turned ON, the transistor Q 32  is turned OFF, so that the operating voltage V 1  is supplied to the gate of the transistor Q 34 , turning ON the transistor Q 34  and turning OFF the transistor Q 36 . As a result, the transistor Q 33  is turned OFF, while the transistor Q 35  is turned ON. Thus, with the transistor Q  33  turned OFF and the transistor Q 34  turned ON, the signal L having the low level voltage Vss is output from the output terminal OUT to other LSIs, instead the voltage selected by the interface voltage supply circuit  31 . 
     In the input circuit  40  shown in FIG. 4, transistors Q 41 -Q 47  are MOSFETs. Of these, the transistors Q 41 , Q 43 , and Q 45  each marked with a circle are P-channel MOSFETs. The rest are N-channel MOSFETs. The interface voltage supply circuit  41  is coupled with the gates of the transistors Q 41  and Q 42  forming an inverter circuit. One of the operating voltages V 1 -V 3  specified by the signal externally input thereto is selectively output by the interface voltage supply circuit  41 . 
     Incidentally, it is possible to have the interface voltage supply circuit  41  to provide only the lowest operating voltage V 3  by feeding the lowest voltage V 3  to the gates of the inverter transistors Q 41  and Q 42 . 
     The cross-linked circuit formed of the transistors Q 43 -Q 47  is supplied with the operating voltage V 1  of the associated transistor, which is LSI 1  in this example. The structure of the cross-linked circuit is identical to that of the output circuit shown in FIG.  3 . 
     The input circuit  40  receives signal H or signal L from another LSI. The level of the input signal is the same as the lowest interface voltage V 3  in the first embodiment, and is the same as one of the three voltages V 1 -V 3  in the second embodiment depending on the LSI issuing that input signal. 
     In any event, given signal H, the transistor Q 41  is turned OFF and the transistor Q 42  is turned ON, so that the transistor Q 44  is turned OFF and the Q 46  is turned ON. The cross-linked transistors Q 43  and Q 45  are turned ON and OFF, respectively. Thus, with the transistor Q 43  turned ON and the transistor Q 44  turned OFF, signal H is given the operating voltages V 1  as it is fed to the internal circuit of the LSI 1 . 
     On the other hand, when signal L is supplied to the input circuit  40 , the transistor Q 41  is turned ON and the transistor Q 42  is turned OFF, so that the operating voltage set by the interface voltage supply circuit  41  (V 3 ; V 1 -V 3 ) is supplied to the gate of the transistor Q 44 , turning ON the transistor Q 44  and turning OFF the transistor Q 46 . As a result, the cross-linked transistors Q 43  and Q 45  are turned OFF and ON, respectively. Thus, with the transistor Q 43  turned OFF and the transistor Q 44  turned ON, the signal L having the low voltage Vss is supplied to the internal circuit. 
     In this way, the invention provides the input circuit as shown in FIG.  3  and the output circuit as shown in FIG. 4 to every LSI (LSI 1 -LSI 3 ) except for the LSI 4  having the lowest operating voltage V 3 . Thus, all the LSIs (other than LSI 4 ) are interfaced by a lower voltage (V 2  or V 3 ) than their operating voltages (V 1  or V 2 ), so that provision of such input circuit and/or output circuit in the LSIs is relatively easy. 
     If the interface voltage between two LSIs were established at a higher operating voltage, as is the case with conventional LSIs, at least the transistors Q 33 -Q 37  (FIG. 3) of the output circuit of an LSI (e.g. LSI operating at V 3  (2 Volts)) for example should be resistible against a high voltage, and at least the transistors Q 41 , Q 42 , and Q 46  (FIG. 4) of the input circuit of an LSI (e.g. LSI operating at V 3  (2 Volts) ) should be resistible against a high voltage, which requires changes in manufacturing process to form thicker or larger oxide layers of the gates of these transistors, thereby adding extra complexity and cost. 
     FIG. 5 illustrates an interface voltage supply circuit shown in FIGS. 3 and 4. FIG. 6 shows how operational modes are set for the interface voltage supply circuit of FIG.  5 . 
     As an example, take the LSI 1  operating at V 1 . The interface voltage supply circuit  31  of FIG. 5 is designed for the LSI 1  such that the interface voltage supply circuit  31  selects and outputs one of three operating voltages V 1 , V 2 , and V 3 . Thus, the interface voltage supply circuit  31  is provided with transistor switches Sv 1 - 1 -Sv 3 - 2  for selecting and outputting the three operating voltages V 1 -V 3  at the output ends OUT 1 , OUT 2 , and OUT 3 , respectively. Although an exemplary switching elements for output circuit is shown in FIG. 5, it would be apparent that the same switching elements may be used in the input circuit as needed. 
     FIG. 6 illustrates how switching modes of the interface voltage supply circuit  31  is established for LSI 1 . 
     The LSI 1  is provided with three power supply terminals for receiving three operating voltages V 1 , V 2 , and V 3  connected with the respective power supply lines Lv 1  (for 5 Volts), Lv 2  (for 3 Volts), and Lv 3  (for 2 Volts). The LSI 1  is also provided with an I/O resistor REG in the I/O circuit, together with a select pin SEL and a select clock pin CLK therefor for connection with an external device. 
     Switching modes in the form of serial data each associated with corresponding one of the output voltages are entered in the I/O register REG from the select pin SEL in synchronism with the clock entered at the clock pin CLK. In this way, the switching modes are stored in the I/O register REG for all the outputs (n outputs say) of the LSI. The switching modes may be assigned to a set of different binary data such as {0, 0}, {0, 1} and {1, 0} associated with the respective operating voltages V 1 , V 2 , and V 3 , as shown in FIG.  6 B. The operating voltages can be selected and output to the corresponding output ends OUT 1 , OUT 2 , and OUT 3  by actuating the respective switches Sv 1 - 1 -Sv 3 - 2  of FIG. 5, in accordance with the binary data retrieved from the register REG. 
     Thus, by registering a serial data representing the switching modes in the I/O register REG, an arbitrary number of modes may be stored in the I/O register without adding pins for selecting the modes. If a need arises to change the number of the operating voltages, it can be done easily by externally rewriting the data stored in the I/O register REG. 
     If it is preferred not to add any pin for setting the switching modes, the I/O register REG of FIG. 6 may be replaced by a storage device such as a ROM or RAM to store the switching modes. 
     Desired switching modes can be imprinted in the substrate using appropriate aluminum masks and contact masks during the manufacturing processes for the LSIs. 
     FIG. 7 shows a circuit for establishing operating voltages (referred to as operating voltage generator) which can be used in place of the interface voltage supply circuit shown in FIG. 5, especially when all the power supply lines are not entirely available to a given LSI 1 . 
     The operating voltage generator comprises resistors R 1 , R 2 , and R 3  connected in series between the v 1  line and the Vss line, as shown in FIG.  7 . Operating voltages V 2  (3 Volts) and V 3  (2 Volts) may be obtained from the nodes of the resisters R 1  and R 2  via a voltage follower circuit OP 1  and from the nodes of the resisters R 2  and R 3  via a voltage follower circuit OP 2 , respectively. 
     With this operating voltage generator, any operating voltage, V 2 , V 3 , besides its own operating voltage V 1 , may be internally generated, so that no extra pin is needed to externally obtain necessary operating voltages.