Abstract:
The present invention is directed to system(s), method(s), and apparatus for accurate fast forward rate when performing trick play with variable distance between frames. In one embodiment, there is presented a circuit for providing a fast forward video sequence. The circuit comprises a system time clock for providing a time reference, said time reference incremented at a predetermined fast forward rate; a comparator for comparing the time reference with timing information associated with a picture; and a controller for determining whether to display the picture based at least in part on the comparison between the timing information and the time reference.

Description:
RELATED APPLICATIONS 
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     FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
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     MICROFICHE/COPYRIGHT REFERENCE 
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     BACKGROUND OF THE INVENTION 
     Video decoders often cannot decode all of the pictures in a compressed stream quickly enough to perform fast forward. Parsing the stream to extract the I frames and feeding only the I frames to the decoder and repeating display of the I frame a specific number of times relies on the assumption that the frequency of I frames is constant. 
     Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments presented in the remainder of the present application with references to the drawings. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is directed to system(s), method(s), and apparatus for accurate fast forward rate when performing trick play with variable distance between frames as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
     These and other features and advantages of the present invention may be appreciated from a review of the following detailed description of the present invention, along with the accompanying figures in which like reference numerals refer to like parts throughout. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is a block diagram of an exemplary circuit in accordance with an embodiment of the present invention; 
         FIG. 2  is a block diagram of an exemplary circuit in accordance with another embodiment of the present invention; 
         FIG. 3  is a flow diagram describing the operation of an MPEG decoder in accordance with an embodiment of the invention; and 
         FIG. 4  is a block diagram of another exemplary circuit in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to  FIG. 1 , there is illustrated a block diagram of an exemplary circuit for providing a fast forward video sequence. The circuit  100  receives video data. The video data comprises a series of pictures  105   0  . . .  105   n . The pictures  105   0  . . .  105   n  can be compressed or not compressed. The pictures  105   0  . . .  105   n  are each associated with timing information T 0  . . . T n  that indicates the time for the display of the associated picture. When the pictures  105  are displayed at their particular time indicated in the timing information T, motion picture is simulated. 
     The circuit  100  comprises a system time clock STC, a comparator  110 , and a controller  115 . The system time clock  105  provides a local time reference. The comparator  110  compares the time reference provided by the system time clock  105  with the timing information T associated with pictures  105 . Based on the comparisons between the time reference and the timing information, the controller  115  can determine the particular picture  105  to display. 
     The circuit  100  can provide a fast forward video sequence by incrementing the system time clock  105  by a fast forward factor. For example, where the system time clock  105  increments based on clock cycles, the system time clock  105  can increment by the product of the increment step and the fast forward factor. For example, to fast forward at a rate of 10×, the system time clock  105  can increment at 10 times the increment step. 
     Certain embodiments of the present invention can be used alongside a variety of different video compression standards. For example, in an exemplary case, the present invention can be used with video data that is compressed in accordance with one of the video compression standards promulgated by the Motion Picture Experts Group (MPEG). 
     Referring now to  FIG. 2 , there is illustrated a block diagram of an embodiment of the present invention in the context of video data that is compressed in accordance with a standard promulgated by the MPEG. While the embodiment is shown in the context of an MPEG standard, it should be noted that the present invention is not limited and can be used with video data that is compressed in accordance with other standards or uncompressed. 
     The circuit  200  receives pictures I 0 , B 1 , B 2 , B 3 , P 4 , B 5 , B 6 , B 7 , P 8 , . . . . The subscript indicates the order that the picture is presented for display. MPEG standards provide for the prediction of pictures from other pictures. MPEG standards provide for what are known as I pictures, P pictures, and B pictures. 
     I pictures (or Intra-pictures) are pictures that are not data dependent on other pictures. P pictures are pictures that are predicted from one other picture, wherein the other picture is displayed prior to the P picture (or Prediction Pictures). B pictures (or Bi-directional pictures) are pictures that are predicted from two other pictures, one that is presented for display prior to the B picture and the other that is presented for display after the B picture. 
     The arrows indicate the data dependencies of the pictures. For example, picture P 4  is predicted from I 0 . Pictures B 1  B 2  and B 3  are predicted from I 0  and P 4 . It is noted that pictures B 1  B 2  and B 3  are presented for display prior to picture P 4 . However, because pictures B 1  B 2  and B 3  are data dependent on picture P 4 , picture P 4  is decoded and decompressed prior to pictures B 1  B 2  and B 3 . 
     Since pictures can be decoded and displayed at different times, a Decode Time Stamp (DTS) indicates the time when an associated video picture is to be decoded, while a Presentation Time Stamp indicates the time when an associated video picture is to be presented for display. Times indicated by PTS and DTS are evaluated with respect to the current System Time Clock value—locked to Program Clock Reference (PCR). 
     The pictures I 0 , B 1 , B 2 , B 3 , P 4 , B 5 , B 6 , B 7 , P 8 , . . . are received by circuit  200  in decode order, e.g., I 0 , P 4 , B 1 , B 2 , B 3 , P 8 , B 5 , B 6 , B 7 , . . . . The foregoing forms what is known as a video sequence  205 . The video sequence is packetized forming what is known as a packetized elementary stream  210 . The packetized elementary stream  210  includes headers  210   h . The packetized elementary stream  210  is carried in transport packets  215  forming a transport stream TS. Presentation Time Stamps (PTS) and Decode Time Stamps (DTS) are carried in headers of the packetized elementary stream  210   h.    
     The circuit  200  includes a transport processor  220 , a video decoder  225 , display engine  230 , frame buffers  235 , controller  240 , a system time clock STC, comparator  245 . The transport processor  220  receives and parses the transport stream TS. 
     The comparator  245  compares the DTS and PTS of the pictures to the system time clock STC. Based on the comparison, the controller  240  determines the appropriate picture to decode by the video decoder  225 . When the video decoder  225  decodes the picture, the decoded pictures is written to the frame buffers  235 . The frame buffers  235  store the decoded picture in the time between decoding and presentation, as well as for reference by the video decoder  225  when decoding other pictures that are dependent thereon. The controller  240  also determines the appropriate picture to display by the display engine  230 . The display engine  230  outputs the pictures for display. 
     Although the controller  240 , the video decoder  225 , and display engine  230  are shown separate, it is noted that any combination of the controller  240 , video decoder  225 , and display engine  230  can be integrated. It is also noted that part of the controller  240  can be integrated with the video decoder  225  and/or part of the controller  240  can be integrated with the display engine  230 . 
     The circuit  200  also provides fast-forward video output. During a fast-forward operation, the controller  240  causes the system time clock STC to increment at the product of the fast forward speed and the incrementation step. For example, for a 10× fast-forward operation, during each display period, the STC can be increased at a rate of 10 times the display period. As a result, the controller  240  causes the display engine  230  to output fast-forward video. In the foregoing manner, the fast-forward operation can be effectuated with accurate fast-forward resolution, especially over a large number of frames. 
     To avoid decoding the pictures at the fast-forwarded rate, in certain embodiments of the present invention, the controller  240  checks the pictures for pictures that are data independent of other pictures, such as I-pictures, and does not decode or present pictures that are data dependent, irrespective of the time stamps. When the PTS associated with the I-pictures are compared to the system time clock STC, the controller  240  can select the I-picture with the presentation time stamp that is nearest to the STC for display. Alternatively, the controller  240  can select the next picture that exceeds the STC for display. In the foregoing manner, the fast-forward operation can be effectuated with accurate fast-forward resolution, especially over a large number of frames. 
     Referring now to  FIG. 3 , there is illustrated a flow diagram describing a method for fast-forwarding a video sequence. At  305 , the controller  240  sets the system time clock STC to increment at a predetermined fast forward rate. At  310 , the controller  240  extracts the PES header associated with a picture. The controller  240  makes a determination at  315 , whether the picture is an intracoded picture. If the picture is not an intracoded picture, the controller  240  discards the picture at  320 , selects the next picture at  325  and returns to  315 . 
     If the picture is an intracoded picture, at  325 , the controller  240  extracts the presentation time stamp associated with the picture. At  330 , the comparator compares the presentation time stamp to the system time clock to determine if the presentation time stamp exceeds the system time clock. If at  330 , the presentation time stamp does not exceed the system time clock, the controller  340  discards the picture at  320 , selects the next picture at  325  and returns to  315 . 
     If at  330 , the presentation time stamp exceeds the system time clock, the controller  240  signals (at  335 ) the decoder  225  to decode the picture and the display engine  230  to output the decoded picture. The controller  240  then waits until the beginning of the next display period at  340 . At the beginning of the next display period, the controller  240  returns to  325 . 
     Referring now to  FIG. 4 , there is illustrated a block diagram of an exemplary circuit in accordance with an embodiment of the present invention. The circuit  400  comprises a processor  405  and a memory  410  connected to the processor  405 . 
     In certain embodiments of the present invention, the memory  410  can store a plurality of instructions for instructions effectuating, for example, the flow chart described in  FIG. 3 . 
     In certain embodiments, the processor  405  and memory  410  can be integrated onto a single integrated circuit. The memory  410  can comprise ROM, wherein the instructions are burned into the ROM as firmware. 
     In other embodiments, the processor  405  and the memory  410  can be board level components. The memory  410  can comprise, for example, a hard disc. The memory  410  can also comprises RAM. The hard disc can store the instructions. When the processor  405  executes the instructions, the RAM can store the instructions. In other embodiments, the memory  410  can be removable from the processor  405  and can include, for example, a floppy disc, or an optical disk. 
     While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.