Abstract:
A DLL system includes a phase detector coupled to an input signal for generating a first phase error signal according to the input signal and a clock signal; an up-down counter coupled to the phase detector for generating a counting signal according to the first phase error signal; a sigma-delta modulator (SDM) coupled to the up-down counter for generating a second phase error signal according to the counting signal; an adder coupled to the SDM and the phase detector for summing the first phase error signal and the second phase error signal to generate a sum signal; a clock generator for generating a plurality of candidate clock signals according to a reference clock; and a multiplexer coupled to the clock generator and the phase detector for selecting one of the candidate clock signals to be the clock signal inputted into the phase detector according to the sum signal.

Description:
BACKGROUND 
   The invention relates to a delay-locked loop (DLL), and more particularly, to a second order DLL utilized for clock and data recovery. 
   When recovering data transmitted via an input data signal, a phase locking circuit is required to track the input data signal. If the input data signal is under a fixed clock with only minor frequency variation caused by noise, either a phase-locked loop (PLL) or a delay-locked loop (DLL) can be utilized as the above-mentioned phase locking circuit since both the PLL and the DLL are capable of tracking such a phase variation of the input data signal. On the other hand, if the input data signal is a spread-spectrum signal, such as a Serial ATA (SATA) signal, a PLL is utilized since a conventional DLL is unable to track a spread-spectrum signal. 
   However, a PLL suffers from several shortcomings despite its ability to track a variety of signals. Firstly, a PLL occupies a large chip area in an integrated circuit (IC), resulting in a high cost compared to a DLL. Secondly, a PLL includes a voltage controlled oscillator (VCO) for generating a clock signal locked to an input signal of the PLL. The VCO inherently accumulates jitters, causing the noise immunity of the PLL to be poorer than that of a DLL. 
   SUMMARY 
   It is therefore one of the objectives of the claimed invention to provide a second order delay-locked loop (DLL) circuit having the ability to track a spread-spectrum signal, to solve the above-mentioned problem. 
   The claimed invention provides a high-order DLL system. The DLL system comprises a phase detector coupled to an input signal for generating a first phase error signal according to the input signal and a clock signal; an up-down counter coupled to the phase detector for generating a counting signal according to the first phase error signal; a sigma-delta modulator (SDM) coupled to the up-down counter for generating a second phase error signal according to the counting signal; an adder coupled to the SDM and the phase detector for summing the first phase error signal and the second phase error signal to generate a sum signal; a clock generator for generating a plurality of candidate clock signals according to a reference clock; and a multiplexer coupled to the clock generator and the phase detector for selecting one of the candidate clock signals to be the clock signal inputted into the phase detector according to the sum signal. 
   The claimed invention further provides a method for generating a clock signal to track an input signal. The method includes generating a first phase error signal according to the input signal and the clock signal; counting up or down according to the first phase error signal to generate a counting signal; generating a second phase error signal by performing a sigma-delta modulation on the counting signal; summing the first phase error signal and the second phase error signal to generate a sum signal; generating a plurality of candidate clock signals according to a reference clock; and selecting one of the candidate clock signals to be the clock signal locked to the input signal according to the sum signal. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a second order delay-locked loop circuit according to an embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   The present invention is related to a DLL system, which refers to a reference clock CLK ref  to track an input signal S i . The reference clock is of frequency f 1 . The input signal S i , might be a target clock signal or a data signal of frequency f 2 . The target clock frequency f 2  might be more than or less than the reference clock frequency f 1 , and the phase of the reference clock might lead or lag the target clock. In order to track the input signal S i  with the reference clock CLK ref , the present invention uses a delay-locked loop (DLL) technique implemented as two correcting paths. The two correcting paths compensate variations between the reference clock and target clock, the variations including frequency variation and phase variation. The reference clock is corrected by the two correcting paths to recover a clock that has substantially the same frequency and phase with the target clock. Then the recovered clock is applied to track the input signal S i . 
   Please refer to  FIG. 1 .  FIG. 1  is a block diagram illustrating a second order delay-locked loop (DLL) system  200  according to an embodiment of the present invention. As shown in  FIG. 1 , the second order DLL system  200  contains a phase detector (PD)  210 , a low pass filter that is implemented by an accumulator  220  in this embodiment, a sigma-delta modulator (SDM)  230 , an clock index generator  240 , a multi-phase clock generator  260 , a cycle slip detector  270 , and an attenuator  280 . The PD  210  detects a phase difference between an input signal S i  and a recovered clock CLK and generates a phase error signal S e . The phase error signal S e  represents the direction and amount of the phase difference between the input signal S i  and the recovered clock CLK, the direction of the phase difference is either phase leading or phase lagging. The path from the phase error signal S e , which is then accumulated by the accumulator  220  and further integrated and quantized by the SDM  230  to be a frequency correcting signal S c1 , forms the frequency correcting path. The path from the phase error signal S e , which is then attenuated by the attenuator  290  to be a phase correcting signal S c2 , forms a phase correcting path. The frequency correcting signal S c1  and the phase correcting signal S c2  are further fed into a clock index generator  240  for correcting the clock index to control the phase shift of the recovered clock CLK. 
   The multi-phase clock generator  260  is used to generate K candidate clocks CLK 1 ˜CLK K  providing to the multiplexer  250  with referred to a reference clock CLK ref . The candidate clocks CLK 1 ˜CLK K  are delayed versions of the reference clock CLK ref  and therefore, each has identical frequency but different phases with the reference clock and with each other candidate clock. 
   The clock index generator  240  generates a clock index and corrects the clock index according to the frequency correcting signal S c1  and the phase correcting signal S c2 . Once the sum of the two correcting signals S c1  and S c2  is Δi, the clock index will be corrected from i to i+Δi accordingly. 
   According to the clock index, the multiplexer  250  selects one of the K candidate clocks CLK 1 ˜CLK K  to be as the recovered clock CLK, the selection is determined by the clock index. When the clock index is of value i, the i th  of the K candidate clocks CLK i  is selected as the recovered clock CLK. Once the clock index from i changed to i′, the multiplexer  250  accordingly changes the clock selection from CLK i  to CLK i′ , the selection change causes a phase shift of the recovered clock. The number of K determines the resolution of the phase shift. If the clock period of the reference clock is T, with K equals to 32, in one embodiment of the present invention, the 32 delayed candidate clocks are designed to be with evenly spaced phase difference within one clock period. That is, every step of selection change corresponds to T/32 phase shift. The clock index changing from i to i+1 causes T/32 phase delaying, and clock index change from i to i−1 causes T/32 phase advancing. 
   The delayed range among the K candidate clocks CLK 1 ˜CLK K , from the least delayed candidate clock to the most delayed candidate clock at least covers one cycle period of the reference clock CLK ref . A cycle slip detector  270  is provided to discover the cycle slip between the reference clock CLK ref  and the recovered clock CLK. Once the cycle slip is detected, the cycle slip detector  270  informs the clock index generator  240  to remove the cycle slip. 
   In this embodiment, the accumulator  220  is an 8-bit counter capable of counting up or counting down. The output of the accumulator  220  is either positive or negative, with a dynamic range from −127 to +127, to accumulate the phase error signal S e  to be as an accumulated factor S a . 
   The SDM  230  further integrates and quantizes the accumulated factor S a . The S a  is first fed into a subtractor  232 , in which being subtracted by a quantized signal S q  and becomes a difference signal S a′ . The difference signal S a′  is further integrated by an integrator  234  to be an integrated signal S t . A quantizer  236  quantizes the integrated signal S t  to be as the quantized signal S q  according to three quantization levels, −128, 0 and 128. The quantized signal S q  is then fed back to the subtractor  232 . A mapping unit  238  maps the three levels −128, 0, 128 quantized signal S q  into three controlling levels of values −1, 0, 1, respectively. The SDM  230  in the present embodiment is a first order SDM. However, the clock recovery system  200  is not limited to utilizing the first order SDM. For example, the second order SDM or higher-order SDM could also be used in this clock/data recovery system. 
   The phase difference between two signals could be expressed as a function of time t, as phase diff =f v t+p v . The zero order term p v , which is substantially time-invariant, represents the phase difference caused by the phase variation between two signals. The first order term f v t, which is substantially linear time-varying, represents the phase difference caused by the frequency variation f v  between two signals. In order to track the input signal referred to the reference clock, the present invention extracts and compensates the two variations between input signal and reference clock. The extraction and compensation is implemented as two correcting paths corresponding to two correcting signals. 
   The attenuator  280  inserted in the phase correcting path, attenuates the phase gain along the phase correcting path. The phase gain is defined as the ratio between the corrected phase shift and the detected phase difference, wherein the corrected phase shift is the phase shift of the recovered clock CLK in response to the updating of the clock index based on the phase correcting signal S c2  and the detected phase difference is the phase difference between the input signal S i  and the recovered clock CLK being detected by the phase detector  210 . For example, the detected phase difference between the input signal and the recovered clock difference is T/8, and the corrected phase shift of the recovered clock is T/32, the corresponding phase gain is ¼. A less than 1 phase gain makes the phase shift of the recovered clock not so sensitively react as the detected phase difference. Thus the instantaneous phase jitter or phase noise will be filtered out or attenuated and will not be directly reflected on the recovered clock, the stability of the recovered clock is therefore improved. 
   In the frequency correcting path of the present embodiment, the detection of phase difference will be accumulated in the accumulator  220  as an accumulated factor S a , which acts as a frequency controlling factor. The frequency controlling factor controls the direction and amount of the phase correcting to compensate the frequency variation between the reference clock CLK ref  and the target clock. Direction of the phase correcting is either phase delaying or phase advancing. If the target clock frequency is larger than the reference clock frequency, the frequency controlling factor is negative. This negative frequency controlling factor integrated and quantized by the SDM  230  produces one time negative S c1  within few recovered clock cycles, the negative S c1  results in phase advancing of the recovered clock CLK. The regularly happened phase advancing causes the recovered clock frequency more than the reference clock frequency. If the target clock frequency is less than the reference clock frequency, the frequency controlling factor is positive. This positive frequency controlling factor integrated and quantized by the SDM  230  produces one time positive S c1  within few recovered clock cycles, the positive S c1  results in phase delaying of the recovered clock CLK. The regularly happened phase delaying causes the recovered clock frequency less than the reference clock frequency. If the target clock frequency still less than the recovered clock frequency, the phase detector detects the phase leading of the recovered clock than the input signal to increase the frequency controlling factor. The increased frequency controlling factor produces more times positive S c1  within the same few recovered clock cycles which makes more frequently phase delaying. Then the recovered clock frequency will become further less. For example, if the accumulated factor S a  is 32, every four reference clock cycles the accumulated factor S a  is integrated to be 128, which produces the frequency correcting signal S c1  as 1 to cause one phase delaying. If the reference clock period is T, with the phase shifting step of T/32, the time period for every 4 recovered clock cycles is 4T+T/32, the recovered clock frequency is corrected as slightly less than the reference clock frequency. 
   The present embodiment uses the DLL technique to implement the clock recovery system. This makes the clock recovery system tracking the frequency variation and phase variation between the reference clock and the target clock in all digital way, whereas the DLL technique saves the large area caused by the PLL technique. Also the same one candidate clocks generator could be shared by several input signals tracking. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.