Abstract:
Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register.

Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates generally to refreshing peripheral parameters. 
       BACKGROUND 
       [0002]    Microcontrollers can be configured to communicate with a variety of peripherals using a direct memory access (DMA) system. In many real-time applications, a set of peripheral registers are refreshed with new parameters. The refresh can be done by software and a central processing unit (CPU), but the latency introduced by an interrupt execution may be significant in real-time applications. Additionally, power consumption can increase if the parameters are updated often. 
       SUMMARY 
       [0003]    Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register. Other implementations are directed to systems, methods, circuits and non-transitory, computer-readable mediums. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a block diagram of an example microcontroller system including peripheral sequencing using DMA. 
           [0005]      FIG. 2  is a block diagram illustrating peripheral sequencing using DMA. 
           [0006]      FIG. 3A-3C  illustrates registers used in peripheral sequencing using DMA. 
           [0007]      FIG. 4  includes event diagrams illustrating peripheral sequencing using DMA. 
           [0008]      FIG. 5  is a flow diagram of an example process of peripheral sequencing using DMA. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]      FIG. 1  is a block diagram of an example microcontroller system  100  including peripheral sequencing using DMA. In some implementations, microcontroller system  100  can include CPU  102 , controller  104 , peripheral bus bridge  106 , memory controller  108 , display controller  110  and several example peripheral devices  112 ,  114 ,  116 . In practice, system  100  can include more or fewer components or subsystems than is shown in  FIG. 1 . 
         [0010]    Controller  104  can be, for example, a system DMA controller or peripheral DMA controller (PDC). A system DMA controller transfers data between memories and peripherals with minimal CPU intervention. While the CPU spends time in low-power sleep modes or performs other tasks, the DMA controller offloads the CPU by taking care of data copying from one area to another. A complete DMA read and write operation between memories and/or peripherals is called a DMA transaction. A transaction is performed in data blocks and the size of the transaction (number of bytes to transfer) is selectable from software and controlled by the block size and repeat counter settings. 
         [0011]    A PDC transfers data between on-chip serial peripherals and on and/or off-chip memories. Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller system performance. To launch a transfer, the peripheral triggers its associated PDC channels by using handshake signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself. 
         [0012]    Peripheral bridge  106  can be, for example, an advanced microcontroller bus architecture (AMBA) peripheral bus (APB) bridge that bridges an advanced high performance bus/AMBA Advanced eXtensible Interface (AHB/AXI) matrix  118  with an APB Matrix  120 . Memory controller  108  can be, for example, a double data rate (DDR) memory controller used to drive DDR memory (e.g., SDRAM), where data is transferred on both rising and falling edges of the system&#39;s memory clock. Display controller  110  can be, for example a liquid crystal display (LCD) controller for running a segment of an LCD display. 
         [0013]    The example peripherals include an event system  112 , an analog to digital converter (ADC)  114 , and a timer/counter (T/C) module  116 . The event system  112  can be a module that routes events reported from modules within the system to appropriate destinations. For example, the T/C module  116  can generate an event  124  and send the event to the event system  112 , which can in turn send the event  126  to the ADC  114 . This is useful, e.g., to cause the ADC to sample a voltage periodically. 
         [0014]    One or more of the peripherals can include a DMA sequencer to initiate a DMA sequence trigger. In some implementations, peripherals  112 ,  114 ,  116  each have a physically separate communication link  122   a - 122   c  (each physically separate and independent of the system bus channels) to controller  104  that allows each of peripherals  112 ,  114 ,  116  to communicate directly with controller  104 . 
         [0015]      FIG. 2  is a block diagram illustrating peripheral sequencing using DMA. In some implementations, DMA system  200  includes a DMA controller  202  and at least one peripheral  204 . DMA system  200  can include a number of channels, each having individual settings to transfer data to/from memory to peripheral  204 . A data transfer can start when DMA controller  202  receives a trigger from the peripheral or from a CPU. Some examples of peripherals include but are not limited to: a timer/counter (T/C) module, analog-to-digital-converter (ADC) and digital-to-analog converter (DAC). When the trigger is received, a data transfer or multiple data transfers (e.g., a burst transfer) are completed before DMA controller  202  can accept a new trigger. In general, a trigger is received by DMA controller  202  when a peripheral “cycle” is completed and the peripheral registers can be safely refreshed. For example, a trigger can be generated by an ADC or DAC when a data conversion result is available in the peripheral. When an ADC trigger is received a user may want to change the ADC input selection. If the input selection is changed, some other parameters may be refreshed as well (e.g., offset, gain correction) to ensure the final result is accurate. A trigger can also be generated by a T/C module when a compare operation between a counter value and a programmable register results in a match. When the trigger is generated, the user may want to change the timer period and compare register settings. 
         [0016]    In DMA system  200 , when trigger  214  is received, DMA controller  202  transfers data between system memory (not shown) and peripheral  204 . There are two issues with this data transfer. First, the trigger is cleared only if DMA controller  202  reads or writes to a specific peripheral address. For example, in the case of an ADC, the trigger is cleared only if a RESULT register storing the conversion result is read. Second, in any DMA system, the address (source or destination) is incremented with the same increment value (+1, +2, +4, etc.). This requires a specific peripheral address mapping register definition, which may not fit specific applications. 
         [0017]    Referring to  FIGS. 2 and 3 , in some implementations peripheral  204  includes three registers  206 ,  208 ,  210  for peripheral sequencing using DMA. Registers  206 ,  208 ,  210  interoperate to provide a “round robin” demultiplexer for data on data bus  216 . Control register  206  (DMACTRL) is initialized with control data (e.g., programmed by the CPU) before a DMA sequence starts to select which peripheral registers  212   a - 212   n  are to be refreshed during the DMA sequence. In some implementations, after initialization control register  206  stores control data (e.g., a set of bits) which identify which peripheral registers will be updated. As shown in  FIGS. 3A and 3B , there are 8 peripheral registers (labeled as Registers A-H). In this example, the physical memory addresses for the 8 registers start at 0x00 and end at 0x08. 
         [0018]    In this example, the trigger is generated when an ADC conversion has completed and the three peripheral registers to be refreshed are Registers A, D and E, as indicated by shading in  FIG. 3A . The parameters to be refreshed in these registers are as follows: Register A=input, Register B=offset correction and Register E=gain correction. Thus, the peripheral memory address pointer is incremented by 3 (from Register A to Register D) and by 2 (from Register D to Register E). A conventional DMA system cannot efficiently refresh the ADC configuration data because the memory addresses are not contiguous and the memory address (source or destination) are incremented with the same value (+1, +2, +4). 
         [0019]    To access registers A, D and E in a DMA sequence, the value 0x19 (8′b00011001) is written to control register  206 , where each bit position corresponds to peripheral register, as shown in  FIG. 3B . In this example, the bit positions  1 ,  4 ,  5  in control register  206  (counting from LSB to MSB), corresponding to Registers A, D, E, each contain a 1 value and the other bit positions each contain a 0 value. For high flexibility, control register  206  can include all peripheral registers in a system (e.g., a microcontroller system). 
         [0020]    Status register  208  (DMASTAT) is updated when the CPU writes to control register  206  and when data register  210  access is completed. When all status bits in status register  208  are cleared (0 value), the DMA sequence is completed and the bit values in control register  206  are loaded into status register  208  to start the next DMA sequence. In some implementations, status register  208  stores the same number of bits as stored in control register  206 . 
         [0021]    Data register  210  (DMADATA) stores data to be transferred between memory and the peripheral register to be updated. When DMA controller  202  writes or reads data register  210 , status register  208  is updated. For example, the least significant bit (LSB) in status register  208  with a 1 value is cleared, as described in more detail in reference to  FIG. 4 . 
         [0022]      FIG. 4  includes event diagrams illustrating peripheral sequencing using DMA. A first event diagram  402  illustrates the writing of control register  206 , a second event diagram  404  illustrates bit clearing in status register  208 , a third event diagram  406  illustrates DMA triggers, a fourth event diagram  408  illustrates indirect access of physical memory and diagram  410  illustrates the physical address of the peripheral registers A-H. 
         [0023]    As shown in  FIG. 4 , when the CPU writes control data to control register  206 , status register  208  is automatically updated with the control data and the DMA sequence starts. While at least a bit is one in status register  208 , a trigger is generated (e.g., by the peripheral). When the trigger is detected, DMA controller  202  will access (read/write) data register  210 . Peripheral  204  detects this access to data register  210  and redirects the access to a physical memory address corresponding to the peripheral register. In some implementations, to detect an access to data register  210 , peripheral  204  detects the first LSB set to 1 in status register  208 . In other implementations, peripheral  204  detects the first MSB set to 1 in status register  208 . When the access of data register  210  for a peripheral register is completed, the corresponding LSB (or MSB) for that peripheral register in status register  208  is cleared (reset to 0) and the DMA sequence restarts. When status register  208  has only one bit set to 1, it means that the current access is the last access in the DMA sequence. After the last access is completed, status register  208  is re-initialized with the value in control register  206 . 
         [0024]      FIG. 5  is a flow diagram of an example process  500  of peripheral sequencing using DMA. Process  500  can be implemented in hardware or software, or a combination of hardware and software. In some implementations, process  500  can be implemented in a DMA system of a microcontroller system. 
         [0025]    In some implementations, process  500  can begin by initializing a control register ( 502 ) with control data indicating which peripheral register(s) are to be refreshed during the DMA sequence and initializing a status register ( 504 ). For example, the control data can include a set of bits, where each bit position corresponds to peripheral register. Bit positions that contain a 1 value are to be updated during the current DMA sequence and bit positions that contain a 0 value are not to be updated during the current DMA sequence. The control data can also be used to initialize the status register. In some implementations, the status register can have the same number of bits as the control register. In some implementations, a single register can be divided into two portions, where a first portion stores control bits and a second portion stores status bits. In some implementations, a bit value of 0 can indicate which peripheral registers are to be updated and bit value of 1 indicates which peripherals are not to be updated. 
         [0026]    Process  500  can continue by, for each peripheral register to be refreshed, accessing (read/write) a data register ( 506 ). The peripheral detects the access of the data register and redirects the access to a corresponding physical memory address of the peripheral register using a memory map. Process  500  then updates the peripheral register ( 508 ). 
         [0027]    Process  500  can continue by updating the status register ( 510 ) by clearing the status bit corresponding to the peripheral register that was refreshed. 
         [0028]    Process  500  can continue by determining if the last bit in the status register has been cleared ( 512 ). If the last bit, process  500  returns to step ( 504 ) to initialize the status register again and start a new DMA sequence. In some implementations, when status register  208  has only one bit set to 1 the current access is the last access in the current DMA sequence. A request for a new refresh sequence is generated and the status register is again initialized to start a new DMA sequence to update or refresh peripheral registers. 
         [0029]    In some examples, a new DMA sequence is started automatically when a previous sequence is completed, e.g., as described above. In some other examples, the new sequence can be started based on receipt of an event, e.g., from the event system  112  of  FIG. 1 . The source of the event can be a counter overflow, e.g., a real time counter (RTC) event such as a time kick or the like. 
         [0030]    While this document contains many specific implementation details, these should not be construed as limitations on the scope what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can, in some cases, be excised from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination.