Abstract:
The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a driver circuit, a method of controlling a driver circuit, and a connector using a driver circuit. 
       BACKGROUND OF THE INVENTION 
       [0002]    Driver circuits are used in many different applications to transmit a digital signal from a source device to a destination device. They operate by switching a supply current or voltage to control the level and polarity of the transmitted signal. 
         [0003]      FIG. 1  illustrates switching of a driver circuit by plotting signal level against time. The signal level denotes the signal passed by a transistor which has been turned on at time T o . It will readily be appreciated that the precise values of the high and low signal levels will vary depending on the operating voltage/current of the circuit. 
         [0004]    The bold line illustrates a circuit with a symmetric switch-on time and switch-off time. The dotted lines illustrate schematically variations in the switch-on and switch-off times. A rise time Tr is defined as the time taken from 20% of the maximum signal value to 80% of the maximum signal value. Similarly, a fall time Tf is defined as the time taken to drop from 80% of the high signal value to 20% of the high signal value. These times are illustrated in  FIG. 1  for the fastest rise time and slowest fall time. 
         [0005]    Fast rise and fall times are generally advantageous in a circuit, particularly in the context of digital connectors, such as LVDS (low voltage differential signal) Transmission cables can be subject to a so-called Eye Pattern Test to analyze the quality of a digital signal transmitted by the connector. The eye test is carried out using a tool which provides a sampled version of the signals&#39; oscilloscope display as a mechanism for judging the signals&#39; behavior. An “eye” is defined in the centre of a screen displaying the sampled signal, the eye representing how much space separates ones and zeros in the digital signal to ensure that they do not cross. The more space around the “eye” the better the signal quality. The “eye” is sometimes referred to as a mask or mask region, and for some tests it can take a hexagonal or approximately hexagonal shape. This is referred to herein as a hexagonal eye mask test. Other, similar tests can operate using different shaped “eyes”, for example, a diamond shape. However, the hexagonal eye mask test is considered to be the more demanding. 
         [0006]    Generally, the faster the switch time, the higher the quality of the signal and the better the separation between ones and zeros or bit levels in a multi level transmission (MLT) environment. 
         [0007]    As the quality of the signal degrades, the sample digital wave present on the display starts to extend into the “eye” which is indicative of a low quality and a high probability that ones and zeros will become confused in the destination device. 
         [0008]    However, fast switching of transistors through a load generates electromagnetic interference (EMI) which takes the form of radiating high frequency signal components. The faster the rise and fall times, the greater the EMI. 
         [0009]    Therefore, it would useful to provide a circuit with a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. 
         [0010]    There have been previous attempts. One attempt is RC slew rate control.  FIG. 2  illustrates a switch circuit comprising upper switches  2   a,    4   a  and lower switches  2   b,    4   b.  Numeral  6  denotes a resistive load at a destination device (receiver side) coupled between terminals Y and YZ. Each switch path is associated with a capacitor  8  for slowing down the switch transition in conjunction with the resistor  6 , according to an RC delay factor. 
         [0011]    The switch circuit shown in  FIG. 2  operates as a current mode transmitter to drive differential inputs across the load illustrated in the form of resistor  6 . Input signals GP, GN are applied to control switches  2   a  and  2   b.    2   a  is a switch of a first polarity, for example, implemented with a P-channel CMOS transistor and  2   b  is a switch of a second polarity, for example, implemented as an N-channel CMOS transistor. The complement signals of GP, GN, are applied to switches  4   a  and  4   b,  which are similarly switches of a first and second polarity respectively. 
         [0012]    When the input signal GP is negative or logic 0, switch  2   a  is caused to close and switch  4   a  is open. Its complement signal GN causes switch  2   b  to close. This creates a current path through  2   a,  load  6  and switch  2   b  through which current supplied by a current source  10  can flow. In this way, a differential voltage indicative of the polarity of GP is developed across the load  6 . When the polarity of the input signal GP changes, switch  2   a  opens and switch  4   a  closes. The input signal GNB causes switch  4   b  to close while GN opens switch  2   b.  Thus, a current path is supplied for current from the current source  10  through switch  4   a,  load  6  and switch  4   b,  reversing the polarity of the differential voltage. Terminals Y, YZ are coupled to transmitter wires in a cable or the like for transmitting the current to develop a differential voltage at a destination device. 
         [0013]      FIG. 2A  shows the effect of differing values for RC, where C is the capacitance of capacitor  8  and the effect of those differing values on the signal characteristics in the “eye” test. 
         [0014]    One difficulty with this attempt is that as the value of the capacitor increases to slow down the switch transition times and therefore reduce EMI, so the quality of the digital signal subject to the eye test decreases. Thus there is a limit to the effectiveness that can be obtained using this technique. Moreover, relatively large capacitors are required, and it is difficult to control the characteristics of the circuit across PVT (process, voltage, temperature), because of these capacitors. Where EMI levels remain too high, spread spectrum clocking has been used to reduce their effect on circuitry in the source device/connector. 
         [0015]    Another attempt to reduce EMI is described in U.S. Pat. No. 5,917,340 which describes a Twisted Pair current driver implemented in CMOS. The driver circuit is divided into four differential drivers labeled S 1  . . . S 4  in  FIG. 3 . Each differential driver has a current source which is a fraction of the total current required to be driven. In U.S. Pat. No. 5,917,340, these current values are all equal, at ¼. Each differential driver takes a pair of differential inputs P 0 , N 0 ; P 1 , N 1 ; P 2 , N 2  and P 4 , N 4  respectively. The drivers are coupled in parallel across the twisted pair outputs TP+, TP−. The connections between the drivers are not shown in  FIG. 3  for the sake of clarity, but it will be appreciated that the TP+ outputs are coupled together, and TP− outputs are coupled together. 
         [0016]    The inputs P 1 , P 2  . . . P 4  are all derived from a single positive input P 0 , while the inputs N 1 , N 2  . . . N 4  are all derived from a negative input N 0 . P 0  and N 0  are differential inputs, such that when the input P 0  is positive, the input N 0  is negative and vice versa. The positive inputs P 1 , P 2  . . . P 4  are derived from the input PO by respective delay elements  12 , each of which delays activation of the respective driver by an amount td. Similarly, for the negative inputs N 1  . . . N 4 . 
         [0017]    This provides a smoothing or “staircase” effect for switching the switches on and off, which is illustrated in  FIG. 4 . Figure shows the progressive turning on of the switches responsive to the individual inputs P 0 , P 1  . . . P 4  and N 0 , N 1  . . . N 4  respectively. The delay td is shown operating between each successive activation. At each successive activation, the level of current driven onto the outputs TP+. TP− increases as shown in the lower graph of  FIG. 4  which shows the output current I out  of the twisted pair outputs TP+, TP−. 
         [0018]    The limitations of this approach include the consumption of a large area and the requirement for PVT compensated delay elements for finer steps. Further area is wasted for routing of the PVT compensated delay elements. 
       SUMMARY OF INVENTION 
       [0019]    According to one aspect of the present invention, there is provided a driver circuit comprising: first and second output terminals for connection across a load; a pair of first switches of a first polarity, the first switches coupled in parallel between a first current node and respective ones of the first and second output terminals, the first current node enabling a current of a first value to flow between the first current node and the first or second output terminal; a plurality of pairs of second switches of a second polarity, each pair coupled in parallel between a respective second current node and the first and second output terminals to enable a current portion to flow between the second current node and the first or second output terminal, the current portions summing to the first value; and timing circuitry arranged to apply a first input signal to one of the pair of first switches and a first inverse input signal to the other switch of the first pair, said first input and inverse input signals remaining applied while successive second input signals are applied to the one of each of the pairs of second switches whereby the current enabled to flow through a load successively changes to develop a staggered voltage across the load. 
         [0020]    Another aspect of the invention provides a connector for coupling a source device to a destination device, the destination device having a load, the connector comprising a driver circuit having: first and second terminals for connection across the load; a pair of first switches of a first polarity, the first switches coupled in parallel between a first current node and respective ones of the first and second terminals; the first current node enabling a current of a first value to flow through the load; a plurality of pairs of second switches of a second polarity, each pair coupled in parallel between a respective second current node and the first and second terminals to enable a current portion to flow through the load, the current portions of the second current nodes summing to the first value; timing circuitry arranged to apply a first input signal to one of the pair of first switches and a first inverse input signal to the other switch of the first pair, said first input and inverse input signals remaining applied while successive second input signals are applied to the one of each of the pairs of second switches whereby the current enabled to flow through a load successively changes to develop a staggered voltage across the load; and input terminals for receiving said first and second input signals for connection to the timing circuitry. 
         [0021]    Another aspect of the invention provides a method of controlling switching in a driver circuit, the driver circuit comprising: a pair of first switches of a first polarity, the first switches coupled in parallel between a first current node and respective first and second terminals; a plurality of pairs of second switches of a second polarity, each pair coupled in parallel between a respective second current node and the first and second terminals, the method comprising: applying an input signal to one of the pair of first switches, whereby said one of the pair of first switches is closed; supplying an inverse input signal to the other switch of the first pair, to open said other switch; and while said input signal and inverse input signal are applied, successively applying second input signals to one of each of the pair of second switches whereby each of said one of the pair of second switches is closed in succession to provide a current path for a current of a first value enabled by the first current node and successive current portions enabled by the second current nodes to flow, such that the current flowing through a load coupled across the first and second terminals successively changes to develop a staggered voltage across the load. 
         [0022]    The driver circuit/connector can be implemented in a number of different contexts. It can be used in cameras, particularly according to the compact camera port  2  (CCP 2 ) Standard, with twisted pair cables using low voltage differential signal (LVDS) technology, in a MIPI (Mobile Industry Processor Interface), with universal serial buses (USB&#39;s) and in standard I/Os. 
         [0023]    For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made by way of example, to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIG. 1  is a timing diagram illustrating switch rise and fall times in a driver circuit; 
           [0025]      FIG. 2  is a circuit diagram of an H-bridge current mode transmitter with RC slew delay; 
           [0026]      FIG. 3  is a schematic diagram of a prior art twisted pair current driver; 
           [0027]      FIG. 4  is a timing diagram for the circuit of  FIG. 3 ; 
           [0028]      FIG. 5  is a schematic block diagram of a driver circuit in accordance with one embodiment of the invention; 
           [0029]      FIG. 6  is a timing diagram for the driver circuit of  FIG. 5 ; 
           [0030]      FIG. 7  is a graph depicting signal values against time; and 
           [0031]      FIG. 8A to 8C  are Fourier transforms. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0032]      FIG. 5  illustrates an embodiment of the present invention. An H-bridge current mode transmitter is implemented by splitting the upper or lower half of a switch circuit to stagger the output drivers. The transmitter is for driving digital signals (ones and zeros) along a transmitter line, such as a cable, to a receiver. 
         [0033]      FIG. 5  is somewhat schematic and for reasons of clarity does not show all of the connections in the circuit. The “upper half” of the circuit comprises a current source  14  providing a current of value I. It has two switches M 1 , M 2  of a first polarity coupled in parallel between the connect source and respective first and second output terminals Y, YZ. A resistive load R  12  is illustrated to represent the load at the receiver. The switches in the upper half can be implemented, for example, as PMOS transistors. The resistive load  12  is coupled between outputs at the end of transmission lines coupled to terminals Y and YZ. The upper PMOS switches are controlled by pseudo-differential signals. They are referred to herein as “pseudo-differential” because input signals P 0 , P 0 B are applied without regards to a staggered timing, while the signal which represents their inverse, N 0 , N 0 B are staggered signals as will be described in more detail in the following. The input signals P 0 , N 0  are received at input terminals  22 ,  24  of the driver circuit. The inverse signals P 0 B, N 0 B are derived from P 0 , N 0  respectively by inversion. 
         [0034]    The lower part of the circuit comprises a plurality of switch pairs coupled in parallel across outputs terminals Y, YZ. The switch pairs are denoted M 3 , M 4 ; M 5 , M 6 ; M 7 , M 8 ; M 9 , M 10 , and can be implemented for example as NMOS transistors. There are K such switch pairs. Each switch pair is associated with a current drain having a current value which represents a portion of the current I. For the switch pair M 3 , M 4 , the current portion is labeled I−K δ n . For the switch pair M 5 , M 6 , the current portion is labeled δ 1 . For the current pair M 7 , M 8 , the current portion is labeled δ 2  and for the current pair M 9 , M 10 , the current portion is labeled δ n . These current portions can be of equal magnitude or of differing magnitudes, the only requirement being that they add up to the value of the current I supplied by current source  14 . In the described embodiment, I−Kδ n  is larger than the other current portions as described later. 
         [0035]    The lower switch circuits are controlled by staggered timing signals N 0 , N 1 , N 2  . . . NK; N 0 B, N 1 B, N 2 B . . . NKB. Each signal N 1  . . . NK is derived from the input signal N 0  after a predetermined delay td provided by respective delay elements  22 . Each signal N 1 B . . . NKB is derived from the inverse input signal N 0 B after a predetermined delay td provided respective delay elements  20 . 
         [0036]    Operation of the circuit will now be described with reference to  FIG. 6 .  FIG. 6  is a timing diagram showing progressive turn-on and off of the switches of the staggered driver circuit. The top line shows the signal P 0  applied at time zero and the signal N 0  applied at time zero. The following description applies to the example where the upper transistors are PMOS, and the lower transistors are NMOS. It will be appreciated that the logic and polarity can easily be reversed, wherein a logic 1 for PMOS switches would be logic 0 for NMOS switches. To start with when P 0 =1 and N 0 , N 1 , . . . NK=0 then switches M 2 , M 3 ,M 5 ,M 7 ,M 9  are ON. Current I from top flows from M 2  and I−Kδn flows into M 3 . Current δ 1  flows from M 5 , δ 2  from M 7  and δn from M 9 . The total current I goes onto ground. When P 0  switches to 0 and N 0  switches to 1 then M 1  and M 4  are turned ON, and M 2 ,M 3  are turned OFF, however M 5 ,M 7  and M 9  are still on and conduct their respective currents of δ 1 , δ 2 , δn. So M 1  conducts current I but only I−Kδn flows through M 4  and remaining current flows through M 5 ,M 7  and M 9 . The voltage at Y rises to R*(I−Kδn) only as Kδn current is flowing in opposite direction. After delay td M 5  turns OFF and M 6  turns ON and thus potential at Y rises by R*(δ 1 ). Note that M 7  and M 9  are still ON and drain the remaining current. After delay  2   td  M 7  turns OFF and M 8  turns ON and thus potential at Y rises by another R*(δ 2 ). This operation continues until after Ktd potential RI is attained at Y. 
         [0037]    A differential voltage Vdiff thus develops across the outputs Y and YZ.  FIG. 6  shows the first component of the rise to a value V 0  over time Ts. This is a relatively fast switch on time up to V 0 . This initial “boost” can be designed to avoid encroachment in the “eye” area of a hexagonal/diamond eye test. The value V 0  is equal to R×(I−K δ n ). After delay td, N 1  is applied turning M 6  ON and M 5  off, as described above. After delay  2   d,  N 2  is applied and so on up to Ktd, when NK is applied. In the embodiment of  FIG. 5 , the values of the current drains vary between the switch circuits, as can be seen from the difference between the subsequent voltage levels at each subsequent delay time. In the particular embodiment illustrated, δ 1 =δ 2 , δ 2 =2 δ 3 , δ 3 =δ 4 , but it will be appreciated that any values are possible depending on the desired turn on characteristic. In particular it is preferred in some circumstances to have equal steps. As an alternative to having current drains of differing sizes, the value of the current drawn can be determined by sizing the transistors. 
         [0038]    A similar effect occurs when the driver circuit receives the trailing edge of the input signal (P 0  falling to zero), with the current decreasing in a staggered way as NK, then N 2 , then N 1  successively change polarity to successively discharge via the drain transistors. 
         [0039]    In  FIG. 5 , it is the lower part of the circuit which is shown divided into a plurality of switch circuits. It will readily be appreciated that the invention could be operated by having a single lower switch circuit pair and a current drain of value I, and split upper switch pairs associated with differing current source values. 
         [0040]    As mentioned, the switches in the upper half can be PMOS transistor with the lower halves being NMOS transistors, or vice-versa. Other alternatives are possible, for example, upper and lower transistors can both be NMOS type, or PMOS type. The switches can be implemented with transmission gates, BJT&#39;s or any suitable switches. 
         [0041]    The invention has the advantage that delay elements are only required for one half of the circuit, either the PMOS or the NMOS switches. So the number of delay elements is reduced. As delay elements generally have to be PVT compensated, the compensation itself requiring a lot of area, this is a significant reduction in the area required for the circuit on-chip. 
         [0042]    While the examples illustrated show the same delay for each delay element, different delays may be provided. 
         [0043]    Additional advantages of the invention will now be discussed with reference to  FIGS. 7 and 8 . Consider the prior art circuit of  FIG. 3  and consider a modification where each of the switches S 1  to S 4  is an H-bridge switch with upper and lower switch pairs of the type illustrated in  FIG. 2 . It would in principle be possible to use the staggering arrangement of  FIG. 3  with such switches, where the top and bottom halves are staggered in a synchronized manner. In attempting to implement a full staggering, synchronization difficulties arise which have the effect of causing ripples in the signal developed across the load. This is shown in Graph (i) of  FIG. 7 , where ripples labeled  30  can clearly be seen on the fall and rise edges. Furthermore, the shape of the waveform is not desirable and would not perform well on the eye test because of inadequate separation between ones and zeros. With a “half staggered” arrangement, an initial boost ensures that the differential signal crosses the zero level line to clear the hexagon eye, but there are also ripples  32  on the waveform, which is shown in Graph (ii) in  FIG. 7 , arising from synchronization difficulties. 
         [0044]    Graph (iii) illustrates a signal produced by a driver circuit according to an embodiment of the invention, with relatively smooth rise and fall times and good separation of ones and zeros. As shown in  FIG. 7 , Graph (iii), and as already described with reference to  FIG. 6 , the value of the current in the portion of the first circuit can be set at a sufficiently high value that the first part of the rise time is relatively fast. The expectation would be that this would generate unwanted EMI components as compared with, for example, the slower rise times of a full staggered arrangement as shown in Graph (i). 
         [0045]    However, analysis of the frequency transform shows that this is not the case. The frequency transform of  FIG. 8A  corresponds to the proposal of the present invention. The frequency transform of  FIG. 8B  is a fully staggered arrangement, and the frequency transform of  FIG. 8C  is a half staggered arrangement. There is not a significant difference between the frequency responses. Therefore, the conclusion can be reached that the proposal according to the present invention can provide embodiments with a frequency response comparable to other arrangements, but with a much improved switch time and signal quality. Furthermore, this can be achieved with lesser circuitry and without the difficulty of synchronizing control signals. 
         [0046]    In particular, no synchronization is needed to keep the common mode constant, because the on and off timing of the upper and lower switches does not need to be matched. Therefore, it is significantly easier to design and more reliable in operation. 
         [0047]    The circuit has the additional advantage that it is suitable for a Hexagon Eye Mask test. 
         [0048]    The circuit can be used in a variety of different scenarios where a low EMI current mode transmitter is required. This includes CCP2, LVDS, MIPI, USB and standard inputs and outputs. 
         [0049]    Although the present invention has been described in connection with a preferred embodiment and modifications thereto, those of ordinary skill in the art will understand that many other modifications can be made to the present invention within the scope of the claims that follow. Accordingly, it is not intended that the scope of the invention in any way be limited by the above description, but instead be determined entirely only by reference to the claims that follow.