Abstract:
A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.

Description:
RELATED APPLICATIONS 
   This application is a continuation application of U.S. patent application Ser. No. 10/366,292, entitled “PULSED WRITE TECHNIQUES FOR MAGNETO-RESISTIVE MEMORIES,” filed on Feb. 13, 2003, now U.S. Pat. No. 6,724,654 issued on Apr. 20, 2004, which is a continuation application of U.S. patent application Ser. No. 10/174,215, filed on Jun. 17, 2002, now U.S. Patent No. 6,532,168 issued on Mar. 11, 2003 which was a divisional of U.S. patent application Ser. No. 09/638,637, filed on Aug. 14, 2000, now U.S. Pat. No. 6,493,259 issued on Dec. 10, 2002, the entireties of which are hereby incorporated by reference herein. 
   This application is also related to U.S. Pat. No. 6,538,918 issued on Mar. 25, 2003; to U.S. Pat. No. 6,269,027 issued Jul. 31, 2001; to U.S. Pat. No. 6,175,525 issued Jan. 16, 2001; and to U.S. Pat. No. 6,147,922 issued Nov. 14, 2000; the entireties of which are hereby incorporated by reference herein. 

   BACKGROUND OF THE INVENTION 
   The present invention relates to ferromagnetic thin film memories and, more particularly, to ferromagnetic thin film memories in which states of the memory cells based on magnetization direction are determined through magnetoresistive properties of the thin film sensed by an electronic circuit. 
   Digital memories of various kinds are used extensively in computers and computer system components, in digital processing systems, and the like. Such memories can be formed, to considerable advantage, based on the storage of digital bits as alternative states of magnetization in magnetic materials in each memory cell, typically thin film materials. These films may be ferromagnetic thin films having information stored therein through the direction of the magnetization occurring in that film, with this information being obtained through either inductive sensing to determine the magnetization state, or by magnetoresistive sensing of such states. Such ferromagnetic thin film memories may be conveniently provided on the surface of a monolithic integrated circuit to provide easy electrical interconnection between the memory cells and the memory operating circuitry. 
   Ferromagnetic thin film memory cells can be made very small and packed very closely together to achieve a significant density of stored digital bits, properties which permit them to be provided on the surface of a monolithic integrated circuit as indicated above. One construction, as an example, is shown in  FIG. 1 , where a bit structure  10  for a memory cell that is presented is formed over a semiconductor material body  12 , as used in a monolithic integrated circuit, and directly on an insulating layer  13 , itself supported on a major surface of body  12  in the integrated circuit. Only a small portion of the integrated circuit is shown, and then only a small portion of the semiconductor body is shown in that integrated circuit portion. 
   These bit structures in an assemblage in a memory are usually provided in a series string of such bit structures often called sense lines. There are typically a plurality of such sense lines in a memory. In order to make interconnections between members of such sense lines, or between the sense lines and the external circuitry in the integrated circuit for operating the memory, terminal regions or junctures  14  are typically provided at each end of the bit structure for interconnection purposes. These interconnections might be formed of copper alloyed in aluminum. 
   The remainder of the bit structure disposed on the exposed major surface of insulating layer  13  includes a lower ferromagnetic thin film  15  and an upper ferromagnetic thin film  16 . Ferromagnetic thin film layers  15  and  16  typically exhibit uniaxial anisotropy, magnetoresistance, little magnetostriction, and are of an alloy composition typically comprising nickel, cobalt and iron. The magnetic device structure can be a spin valve that includes a pinned reference layer  15  spaced apart from a “free layer” that stores the digital information. The lower ferromagnetic thin film  15  is typically, but not always, thicker than the upper ferromagnetic thin film  16 . Alternatively, a pseudo-spin-valve structure can be used where the lower ferromagnetic thin film  15  is often called the hard layer, and the upper ferromagnetic thin film  16  is often called the soft layer. 
   Between ferromagnetic thin film layers  15  and  16  is typically a further thin layer  17  which usually would not exhibit ferromagnetism but may be either an electrical conductor or an electrical insulator. Layer  17  must, however, in this construction, minimize the exchange interaction between layers  15  and  16  so that the magnetization vectors of each layer are decoupled. A typical choice for layer  17  would be copper. An insulating layer  18  covers bit structure  10  although only a part of it is shown in FIG.  1 . 
   Finally, a word line  19  is shown in  FIG. 1  disposed on the major surface of insulating layer  18 . Word line  19  typically includes an aluminum layer alloyed with copper on a titanium-tungsten base layer. A protective and insulating layer over the entire structure of  FIG. 1  is often used in practice, but is not shown here. 
   Bit structure  10  can be operated in a longitudinal mode having its easy axis extend between internal interconnections  14  perpendicular to the direction of word line  19 . Information kept as a digital bit having one of two alternative logic values in bit structure  10  is stored therein in layer  15  by having the magnetization vector point in one direction or the other, generally along the easy axis of magnetization. If the direction of magnetization is caused to rotate from such a direction by external magnetic fields, the electrical resistance of layers  15  and  16  changes with this magnetization direction rotation because of the magnetoresistive properties of such layers. For the kinds of materials typically used in layers  15  and  16 , the maximum change in resistance is on the order of a few percent of the minimum resistance value. 
   Sense current refers to the current flow through bit structure  10  from one terminal  14  to the other terminal  14  thereof, and word current refers to current flowing in word line  19  adjacent to, and transverse to the orientation of, bit structure  10 . Bit structure  10  can be placed in one of the two possible magnetization states of layer  15  (pinned layer) through the selective application of sense and word currents i.e., information can be “written” in bit structure  10 . A bit structure  10  of a typical configuration can be placed in a “0” magnetization state by the application of a sense current of typically 1.0 mA , and coincidentally with the provision of a word current in one direction from 20 mA to 40 mA. The opposite magnetization state representing a “1” logic value can be provided through providing the same sense current and a word current of the same magnitude in the opposite direction. Such states typically occur fairly quickly after the proper current levels are reached, such state changes typically occurring in less than about 5 ns. 
   Determining which magnetization state is stored in bit structure  10  i.e., reading the information stored in bit structure  10 , is typically done by providing externally caused magnetic fields in that bit structure, through providing, for example, wordline currents and sometimes coincident sense line currents. These currents rotate the magnetization of the upper ferromagnetic thin film  16  (free layer) of the bit structure  10 , but preferably not the lower ferromagnetic thin film  15  (pinned layer). As indicated above, this causes a change in the electrical resistance encountered between terminal regions  14  in bit structure  10  for different magnetization directions in the structure, including changing from one easy axis direction magnetization state to the opposite direction state. As a result, there is detectable differences in the voltage developed across magnetic bit structure  10  by the sense current flowing therethrough, depending on the relative magnetization direction of the pinned and free layers of bit structure  10 . 
   As the size of the bit structure  10  decreases, the magnetic field required to rotate the upper ferromagnetic thin film  16  and the lower ferromagnetic thin film  15  also tend to increase. Accordingly, the magnitude of the word line currents and sense lines currents increase. Depending on the technology used, this may cause the electro-migration limits of the metal interconnect layers to be exceeded. To help compensate for this, a digital line is sometimes provided over the bit structure  10  parallel with the sense line. The digital line provides an additional metal layer for carrying the required current, and provides additional lateral torque at the bit structure  10 . 
   A limitation of many prior art magneto-resistive memories is that both sense lines and word lines are separately provided. Each of the sense lines and word lines typically requires a separate and often relatively large driver, which can result in significant peripheral overhead. This peripheral overhead often decreases the overall density of the memory and increases the overall power, both of which are undesirable. 
   SUMMARY OF THE INVENTION 
   The present invention overcomes many of the disadvantages of the prior art by providing a magneto-resistive memory that has a shared word line and sense line. By providing a shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents may be reduced. This may reduce the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory. 
   In accordance with one illustrative embodiment of the present invention, a word line is provided adjacent a magneto-resistive bit. Rather than providing a separate sense line that interconnects the bit ends of the magneto-resistive bit to adjacent bits, one end of the magneto-resistive bit is connected to the word line and the other end is connected to a predetermined voltage such as ground through a switch or the like. The switch, which is preferably a transistor, selectively provides a path for a sense current to flow from the word line, through at least part of the magneto-resistive bit, and to the predetermined voltage. Accordingly, the word line may deliver both the word line current and the sense line current for the magneto-resistive bit. As such, no separate sense line current driver is required. Instead, a relatively small buffer or the like may be used to activate the switch, which then draws the sense line current from the word line. 
   Preferably, the magneto-resistive bit is elongated and has a length and a width. The magnetization vector of the pinned layer of the magneto-resistive bit preferably remains in a predetermined direction. Thus, the magneto-resistive bit may be written to a desired magneto-resistive state by changing the magnetization vector of only the free layer. The word line carries a word line current that produces a word line magnetic field component along the length of the elongated magneto-resistive bit. The word line magnetic field component provides the longitudinal force for switching the magnetization vector of the free layer of the magneto-resistive bit. The sense current, which passes through at least part of the magneto-resistive bit, preferably produces a sense magnetic field component that extends along the width of the elongated magneto-resistive bit. The sense magnetic field component provides the lateral torque sometimes necessary to initiate the rotation of the magnetization vector of the free layer of the magneto-resistive bit. A digital line may also be provided adjacent the magneto-resistive bit to provide additional lateral torque, if desired. 
   During a write operation, a word line current is provided to the word line, and the switch is activated. The switch draws a write sense current from the word line and through the magneto-resistive bit. The magnetic fields produced by the word line current and the write sense current are preferably sufficient to write the free layer of the magneto-resistive bit to the desired magneto-resistive state. 
   During a read operation, a word line current is not provided. Instead, a read circuit provides a path for a read sense current to flow to the word line. The switch is again activated, which draws the read sense current through the magneto-resistive bit. The read circuit senses the resistive state of the magneto-resistive bit by sensing the magnitude of the read sense current or by sensing the voltage drop across the magneto-resistive bit. 
   During a write operation, it is desirable to limit the magnitude of the write sense current so that the magnetic bit is not damaged by the current. During a read operation, it is desirable to reduce the resistance that is in series with the magneto-resistive bit to maximize the sensitivity to the resistance change of the GMR bits. Accordingly, it is contemplated that the switch may have at least two resistive modes including an intermediate resistive mode and a lower resistive mode. The intermediate resistance mode may provide a limiting resistance in series with the magneto-resistive bit to limit the amount of write sense current that is drawn from the word line during a write operation. The lower resistance mode may be used to reduce the resistance that is in series with the magneto-resistive bit during a read operation to maximize the sensitivity of the read operation. 
   When the switch includes a transistor, the intermediate resistive mode may be provided by operating the transistor in the saturation region, where the current flowing through the transistor is controlled by the voltage on the gate of the transistor. By providing an appropriate voltage to the gate of the transistor, the desired write sense current can be provided. The lower resistance mode may be provided by operating the transistor in the linear region, with the transistor fully turned on. 
   It is contemplated that the switch may also have a higher resistive mode for substantially preventing the write sense current and the read sense current from flowing from the word line. This higher resistance mode may allow the magneto-resistive bit to be deselected, which may be particularly important when multiple magneto-resistive bits are controlled by the same word line. 
   To provide a differential magneto-resistive output signal, it is contemplated that a magneto-resistive storage element may be provided that includes two magneto-resistive bits. In this illustrative embodiment, the word line may extend adjacent the first and second magneto-resistive bits. The word line may be connected to the first end of the first magneto-resistive bit and the first end of the second magneto-resistive bit. The word line preferably extends adjacent the first magneto-resistive bit in a first direction and adjacent the second magneto-resistive bit in a second opposite direction. This may provide a word line magnetic field component that extends toward one end of the first magneto-resistive bit and toward the other end of the second magneto-resistive bit. Since the magnetization vector of the pinned layer of the first and second magneto-resistive bits preferably are in the same direction, this configuration causes the first and second magneto-resistive bits to be written into opposite magneto-resistive states. 
   As above, a switch is preferably coupled to the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit. The switch selectively provides a path for a write sense current and a read sense current to flow from the word line, through at least part of the first and second magneto-resistive bits, and to a predetermined voltage such as ground. The switch preferably has at least two resistive states including an intermediate resistive state and a lower resistive state. 
   During a write operation, a word line current is provided to the word line. The word line current provides a write magnetic field component toward one end of the first magneto-resistive bit and toward the other end of the second magneto-resistive bit. When the switch is activated, the write sense current is drawn from the word line current and through the first and second magneto-resistive bits. This causes the first magneto-resistive bit to be written to a first resistive state and the second magneto-resistive bit to a second opposite resistive state. 
   During a read operation, the word line is preferably divided into a first word line and a second word line, with the first word line extending adjacent the first magneto-resistive bit and the second word line extending adjacent the second magneto-resistive bit. This may be accomplished by providing a word line switch between the first word line and the second word line. The word line switch may be activated to connect the first word line and the second word line during a write operation, and may be deactivated to effectively disconnect the first word line from the second word line during a read operation. 
   It is recognized that in some embodiments, a word line switch may not be needed. For example, the first word line and the second word line may always be separated, even during a write operation. In this embodiment, the word line current does not traverse from the first word line to the second word line. Instead, a first word line current may be provided to the first word line, and a second word line current may be provided to the second word line. The polarity of the first and second word line currents may then be adjusted so that the first magneto-resistive bit and the second magneto-resistive bit are written into opposite resistive states. 
   A read circuit is preferably coupled to the first word line and the second word line. The read circuit provides a path for a first read sense current to the first word line and a second read sense current to the second word line. The first read sense current and the second read sense current are preferably substantially identical. The switch or switches in the magneto-resistive element are activated to draw the first read sense current through the first magneto-resistive bit and the second read sense current through the second magneto-resistive bit. The read circuit senses the resistive state of the magneto-resistive bits by sensing the difference between the first read sense current and the second read sense current, or the differential voltage at the first ends of the first and second magneto-resistive bits. 
   It is contemplated that the read circuit may include a latch circuit similar to that shown in co-pending U.S. patent application Ser. No. 09/059,871, filed Apr. 14, 1998, and entitled “NON-VOLATILE STORAGE LATCH”, U.S. patent application Ser. No. 09/396,189, filed Sep. 14, 1999 and entitled “NON-VOLATILE STORAGE LATCH”, and U.S. patent application Ser. No. 09/429,664, filed Oct. 28, 1999 and entitled “NON-VOLATILE STORAGE LATCH”, all of which are incorporated herein by reference. More specifically, the read circuit may include a latch circuit that includes a first inverter and a second inverter coupled together in a cross-coupled configuration. The latch circuit preferably also includes a load transistor coupled between the input terminals of the first and second inverters. The load transistor is used to load the state on the negative supply terminals of the first and second inverters into the latch circuit. 
   In accordance with this embodiment of the present invention, the first word line may be coupled to the negative supply terminal of the first inverter, and the second word line may be coupled to the negative supply terminal of the second inverter. The first end of the first magneto-resistive bit is preferably coupled to the negative supply terminal of the first inverter via the first word line, and the first end of the second magneto-resistive bit is preferably coupled to the negative supply terminal of the second inverter via the second word line. During a read operation, the second ends of the first and second magneto-resistive bits are preferably coupled to ground via a switch or the like, as described above. 
   In this configuration, when the load transistor of the read circuit is activated, identical sense line currents are provided to the first word line and the second word line via the negative supply terminals of the first and second inverters. With the switch enabled, the first and second read sense line currents pass through the first and second magneto-resistive bits, respectively. Since the first and second magneto-resistive bits are in opposite resistive states, the voltage at the negative supply terminals of the latch circuit is not equal. Thus, when the load transistor is deactivated, the latch circuit assumes the state that corresponds to the voltage differential between the negative supply terminals of the first and second inverters. This state corresponds to the resistive state of the magneto-resistive bits. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects of the present invention and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof and wherein: 
       FIG. 1  is a partial cut-away perspective view of a prior art magneto-resistive memory; 
       FIG. 2  is a graph showing illustrative minor loops of a magneto-resistive bit as a function of the write sense current; 
       FIG. 3  is a schematic diagram showing an illustrative magneto-resistive memory having a shared word line and sense line; 
       FIG. 4  is a schematic diagram showing a preferred magneto-resistive memory having shared word lines and sense lines; 
       FIG. 5  is a timing diagram showing illustrative write and read operations of the magneto-resistive memory of  FIG. 4 ; 
       FIG. 6  is a partial cross-sectional side view of an illustrative magneto-resistive memory element in accordance with the present invention; and 
       FIG. 7  is a partial cross-sectional side view of yet another illustrative magneto-resistive memory element in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2  is a graph showing a number of illustrative minor loops of a GMR magneto-resistive bit as a function of write sense current. The x-axis of the graph illustrates the applied easy axis magnetic field, which in the example shown, corresponds to the word line magnetic field component that extends along the length of the magneto-resistive bit. The y-axis of the graph illustrates the corresponding resistance of the magneto-resistive bit assuming the magnetic field vector  39  of the pinned layer of the magneto-resistive bit remains pointing to the left, as shown. 
   At point A, the magnetization vector  38   a  of the free layer and the magnetization vector  39  of the pinned layer point to the left, which in the example shown, corresponds to a negative word line magnetic field. During a write operation, the word line magnetic field is first reduced to zero, which corresponds to point B. During this transition, the magneto-resistive state of the magneto-resistive bit does not change. The word line magnetic field is then increased in a positive direction to point C. As the word line magnetic field increases beyond point C, the magnetization vector of the free layer switches state, resulting in a higher bit resistance as indicated at point D. In this state, the magnetization vector  38   b  of the pinned layer points to the right. 
   To return the magneto-resistive bit to its original state, the word line magnetic field is again reduced to zero, which corresponds to point E, and is then increased in a negative direction to point F. As the word line magnetic field increases beyond point F, the magnetization vector of the free layer again switches state, resulting in a lower bit resistance as indicated at point A. In this state, the magnetization vector  38   a  of the free layer points to the left, as shown. 
   An increase in the magnitude of the sense line magnetic field can often reduce the word line magnetic field that is required to switch the state of the free layer of the magneto-resistive bit. Minor loop  40 , which corresponds to the smallest sense line magnetic field present, requires the highest word line magnetic field to switch the state of the free layer. Minor loops  42 ,  44  and  46 , which have increasingly larger sense line magnetic fields, require increasingly smaller word line magnetic fields to switch the state of the free layer. This phenomenon can often be used to provide selectivity to a memory, and no digital line may be required. 
   To further illustrate the selectivity that can often be provided by the sense line current, a specific word line magnetic field (and thus a specific word line current) is shown at  50 . Those magneto-resistive bits that have an insufficient sense line magnetic field, such as those corresponding to minor loops  40  and  42 , will not be written. However, those magneto-resistive bits that have a sense line magnetic field that is greater than a threshold level, such as those corresponding to minor loops  44  and  46 , will be written. Accordingly, it is contemplated that the present invention may provide the desired selectivity using only a sense line, and may not require a digital line. However, it is contemplated that a digital line may be provided, if desired. 
     FIG. 3  is a schematic diagram showing an illustrative magneto-resistive memory having a shared word line and sense line. The illustrative magneto-resistive memory is generally shown at  60  and includes a word line  62 , a magneto-resistive bit  64 , a switch  66  and a read block  68 . 
   The word line  62  is provided adjacent the magneto-resistive bit  64  to provide a word line magnetic field at the magneto-resistive bit. Preferably, the word line  62  extends over or under the magneto-resistive bit, as further shown in  FIGS. 6-8  below. One end  70  of the magneto-resistive bit  64  is preferably connected to the word line  62 , and the other end  72  is preferably connected to a predetermined voltage  74  such as ground through switch  66 . The switch  66 , which is preferably a transistor, selectively provides a path for a sense current to flow from the word line  62 , through at least part of the magneto-resistive bit  64 , and to the predetermined voltage  74 . Accordingly, the word line  62  may deliver both the word line current and the sense line current for the magneto-resistive bit  64 . As such, no separate sense line current driver may be required. Instead, a relatively small buffer or the like may be used to control the switch  66  via the switch control terminal  76 . 
   Preferably, the magneto-resistive bit  64  is elongated and has a length and a width. The word line  62  carries a word line current that produces a word line magnetic field component along the length of the elongated magneto-resistive bit  64 . The word line magnetic field component provides the longitudinal force for switching the magnetization vector of the free layer of the magneto-resistive bit  64 . The sense current, which passes through at least part of the magneto-resistive bit  64 , preferably produces a sense magnetic field component that extends along the width of the elongated magneto-resistive bit  64 . The sense magnetic field component provides the lateral torque sometimes necessary to initiate the rotation of the magnetization vector of the free layer of the magneto-resistive bit  64 . A digital line (not shown) may also be provided adjacent the magneto-resistive bit  64  to provide additional lateral torque, if desired. 
   During a write operation, a word line current is provided to the word line  64  via word current terminal  80 . The switch  66  is then activated via the switch control terminal  76 , which draws a write sense current from the word line  62  and through the magneto-resistive bit  64 . The magnetic fields produced by the word line current and the write sense current write the free layer of the magneto-resistive bit  64  to the desired magneto-resistive state. The read block  68  is preferably disabled to prevent any read sense currents from being provided to the word line  64 . 
   During a read operation, the word line current is preferably not provided. Instead, the read block  68  provides a path for a read sense current to flow to the word line  62 . The switch  66  is then activated, which draws a read sense current through the magneto-resistive bit  64 . The read block  68  senses the resistive state of the magneto-resistive bit  64  by sensing the magnitude of the read sense current or by sensing the voltage drop across the magneto-resistive bit  64 . 
   During a write operation, it is desirable to limit the magnitude of the write sense current so that sufficient word line current remains to effectively write the free layer of the magneto-resistive bit  64 . In contrast, and during a read operation, it is desirable to reduce the resistance that is in series with the magneto-resistive bit  64  to maximize the sensitivity of the read operation. Accordingly, it is contemplated that the switch  66  may have at least two resistive modes including an intermediate resistive mode and a lower resistive mode. The intermediate resistance mode may provide a limiting resistance in series with the magneto-resistive bit  64  to limit the amount of write sense current that is drawn from the word line  62  during a write operation. The lower resistance mode may be used to reduce the resistance that is in series with the magneto-resistive bit  64  during a read operation to maximize the sensitivity of the read operation. 
   When switch  66  includes a transistor as shown, the intermediate resistive mode may be provided by operating the transistor in the saturation region, where the current flowing through the transistor is controlled by the voltage on the gate of the transistor (e.g., at the switch control terminal  76 ). By providing an appropriate voltage to the gate of the transistor, the desired write sense current can be provided. The lower resistance mode may be provided by operating the transistor in the linear region, with the transistor fully turned on. 
   It is contemplated that the switch  66  may further have a higher resistive mode for substantially preventing the write sense current and the read sense current from flowing from the word line  62 . This higher resistance mode may allow the magneto-resistive bit  64  to be deselected, which may be particularly important when other magneto-resistive bits (see  FIG. 4 ) are controlled by the same word line  62 . 
     FIG. 4  is a schematic diagram showing a preferred magneto-resistive memory having shared word lines and sense lines. The magneto-resistive memory is generally shown at  100 , and includes a number of magneto-resistive memory elements  102   a-f , a number of read circuits  104   a  and  104   b , a number of word lines  106   a-d , a number of word line switches  108   a  and  108   b  and a controller  110 . 
   The memory architecture includes a number of columns and a number of rows. Each of the columns correspond to one of the read circuits  104   a  and  104   b . During a write operation, a desired column can be selected by providing a word line current to the word lines that correspond to the desired column of magneto-resistive bits. For example, to select the column that includes read circuit  104   a , a word line current may be provided to word lines  106   a  and  106   b  via write current- 1  terminals  114 . Likewise, to select the column that includes read circuit  104   b , a word line current may be provided to word lines  106   c  and  106   d  via write current-N terminals  116 . 
   During a read operation, the desired column can be selected by asserting the load terminal of the corresponding read circuit. For example, to select the column that includes read circuit  104   a , the load- 1  terminal  120  of read circuit  104   a  may be asserted. Likewise, to select the column that includes read circuit  104   b , the load-N terminal  122  of read circuit  104   b  may be asserted. An advantage of this embodiment is that a differential magneto-resistive output signal is provided to the read circuits  104   a  and  104   b , thereby potentially increasing the signal-to-noise ratio of the memory. 
   Each of the magneto-resistive storage elements  102   a-f  preferably include two magneto-resistive bits. The magnetization vector of the pinned layer of each of the magneto-resistive bits preferably remains in a common direction, such as pointing to the left. For clarity, the operation of magneto-resistive storage element  102   a  is described in detail. The remaining magneto-resistive storage elements  102   b-f  operate in a similar manner. 
   Magneto-resistive storage element  102   a  includes magneto-resistive bits  112   a  and  112   b . Word line  106   a  extends adjacent the first magneto-resistive bit  112   a , and word line  106   b  extends adjacent magneto-resistive bit  112   b . Word line  106   a  is connected to the first end  124  of the first magneto-resistive bit  112   a , and word line  106   b  is connected to the first end  126  of the second magneto-resistive bit  112   b . Word lines  106   a  and  106   b  can be selectively connected via word line switch  108   a  during a write operation so that the word line current travels past the first magneto-resistive bit  112   a  in a first direction (e.g., downward), and past the second magneto-resistive bit  112   b  in a second opposite direction (e.g., upward). If word lines  106   a  and  106   b  are positioned above the first and second magneto-resistive bits  112   a  and  112   b , respectively, the word line current produces a word line magnetic field component that extends to the right in the first magneto-resistive bit  112   a  and to the left in the second magneto-resistive bit  112   b . Since the pinned layer of the first and second magneto-resistive bits  112   a  and  112   b  both preferably point in a common direction such as to the left, the first and second magneto-resistive bits  112   a  and  112   b  may be written into opposite magneto-resistive states. 
   Preferably, a switch is coupled to the second end  130  of the first magneto-resistive bit  112   a  and the second end  132  of the second magneto-resistive bit  112   b . In the embodiment shown, the switch includes two identical transistors, each having a gate coupled to a select line, such as select- 1  line  130 . The switch may selectively provide a path for a write sense current and a read sense current to flow from the word lines  106   a  and  106   b , through at least part of the first and second magneto-resistive bits  112   a  and  112   b , and to a predetermined voltage such as ground. The switch preferably has at least two resistive states including an intermediate resistive state and a lower resistive state. 
   During a write operation, a word line current is provided, for example, down word line  106   a , through write switch  108   a , and up word line  106   b . As indicated above, such a word line current produces a write magnetic field component that points to the right in the first magneto-resistive bit  112   a  and to the left in the second magneto-resistive bit  112   b . When the switch is activated, a write sense current is drawn from the word line current and through the first and second magneto-resistive bits  112   a  and  112   b . This causes the first magneto-resistive bit  112   a  to be written to a first resistive state and the second magneto-resistive bit  112   b  to a second opposite resistive state. Preferably, the read circuit  104   a  is disabled to prevent any read sense currents from being provided to word line  64 . 
   During a read operation, the word line is preferably divided into a first word line  106   a  and a second word line  106   b , with the first word line  106   a  extending adjacent the first magneto-resistive bit  112   a  and the second word line  106   b  extending adjacent the second magneto-resistive bit  112   b . This is preferably accomplished by providing a word line switch  108   a  between the first word line  106   a  and the second word line  106   b . The word line switch  106   a  may be activated to connect the first word line  106   a  and the second word line  106   b  during a write operation, and may be deactivated to effectively disconnect the first word line  106   a  from the second word line  106   b  during a read operation. 
   The read circuit  104   a  is preferably coupled to the first word line  106   a  and the second word line  106   b . The read circuit  104   a  provides a path for a first read sense current to the first word line  106   a  and a second read sense current to the second word line  106   b . The switch or switches in the magneto-resistive element are then activated to draw the first read sense current through the first magneto-resistive bit  112   a  and the second read sense current through the second magneto-resistive bit  112   b . The read circuit  104   a  may sense the resistive state of the magneto-resistive bits  112   a  and  112   b  by sensing the difference between the first read sense current and the second read sense current. Alternatively, the read circuit  104   a  may sense the resistive state of the magneto-resistive bits  112   a  and  112   b  by sensing the differential voltage between the first ends  124  and  126  of the first and second magneto-resistive bits  112   a  and  112   b , respectively. 
   It is contemplated that the read circuit  104   a  may include a latch circuit similar to that shown in co-pending U.S. patent application Ser. No. 09/059,871, filed Apr. 14, 1998, and entitled “NON-VOLATILE STORAGE LATCH”, U.S. patent application Ser. No. 09/396,189, filed Sep. 14, 1999, and entitled “NON-VOLATILE STORAGE LATCH”, and U.S. patent application Ser. No. 09,429,664, filed Oct. 28, 1999 and entitled “NON-VOLATILE STORAGE LATCH”, all of which are incorporated herein by reference. More specifically, the read circuit  104   a  may include a latch circuit that includes a first inverter  140  and a second inverter  142  coupled together in a cross-coupled configuration. The latch circuit preferably also includes a load transistor  144  coupled between the input terminals of the first and second inverters. The load transistor  144  is used to load the state that corresponds to the voltage difference on the negative supply terminals  146  and  148  of the first and second inverters  140  and  142 , respectively, into the latch circuit. 
   The first word line  106   a  is coupled to the negative supply terminal  146  of the first inverter  140 , and the second word line  106   b  is coupled to the negative supply terminal  148  of the second inverter  142 . The first end  124  of the first magneto-resistive bit  112   a  is preferably coupled to the negative supply terminal  146  of the first inverter  140  via the first word line  106   a , and the first end  126  of the second magneto-resistive bit  112   b  is preferably coupled to the negative supply terminal  148  of the second inverter  142  via the second word line  106   b . During a read operation, the second ends  124  and  126  of the first and second magneto-resistive bits  112   a  and  112   b , respectively, are coupled to ground via the switch or the like, as described above. 
   In this configuration, when the load transistor  144  of the read circuit  104   a  is activated, identical sense line currents are provided to the first word line  106   a  and the second word line  106   b  via the negative supply terminals  146  and  148  of the first and second inverters  140  and  142 . With the switch in the magneto-resistive element  102   a  enabled via select- 1  terminal  130 , the first and second sense line currents pass through the first and second magneto-resistive bits  112   a  and  112   b , respectively. Since the first and second magneto-resistive bits  112   a  and  112   b  are in opposite resistive states, the voltages at the negative supply terminals  146  and  148  of the latch circuit are not equal. Thus, when the load transistor  144  is deactivated, the latch circuit will assume the state that corresponds to the voltage differential between the negative supply terminals  146  and  148  of the first and second inverters  140  and  142 . This state corresponds to the resistive state of the magneto-resistive bits  112   a  and  112   b.    
   A controller  110  is preferably provided for controlling the various terminals including the write current- 1  terminals  114 , the select terminals such as select- 1  terminal  130 , the write- 1  terminal, the load- 1  terminal  120 , the write current-N terminals  116 , the write-N terminal, the load-N terminal  122 , etc. 
     FIG. 5  is a timing diagram showing illustrative write and read operations of the magneto-resistive memory of FIG.  4 . The timing diagram is divided into six regions including regions  180 ,  182 ,  184 ,  186 ,  188  and  190 . Region  180  shows a write operation that writes a “1” to magneto-resistive memory element  102   a . The illustrative write operation begins with all control terminals deselected. These control terminals include write current- 1  terminals  114 , write current-N terminals  116 , write- 1  terminal  200 , write-N terminal  202 , select- 1  terminal  130 , select- 2  terminal  204 , select-N terminal  208 , load- 1  terminal  120 , and load-N terminal  122 . 
   The write current- 1  terminals  114  are asserted to provide a positive write current  110  pulse  210  to word lines  106   a  and  106   b . The write- 1  terminal  200  is also asserted as shown at  212 , which closes the word line switch  108   a  and connects word lines  106   a  and  106   b  as shown. The word line current provided to write current- 1  terminals  114  thus passes down word line  106   a , through word line switch  108   a , and up word line  106   b . To select magneto-resistive memory element  102   a , the select- 1  terminal  130  is asserted as shown at  214 . This turns on the switch transistors in magneto-resistive memory element  102   a , which draw a sense current from word lines  106   a  and  106   b  and through magneto-resistive bits  112   a  and  112   b . Preferably, the select- 1  terminal  130  is only asserted to a level that allows the switch transistors in the magneto-resistive memory element  102   a  to operate in the saturation region to limit the magnitude of the sense currents provided. As described above, the combination of the word line currents and the sense line currents causes the magneto-resistive bits  112   a  and  112   b  to be written into opposite magneto-resistive states, and in the illustrative embodiment, into a state that corresponds to a logic “1”. To complete the illustrative write operation, the write current- 1  terminals  114 , write- 1  terminal  200  and the select- 1  terminal  130  are deselected. 
   Region  182  shows a write operation that writes a “0” to magneto-resistive memory element  102   b . For this write operation, the write current- 1  terminals  114  are again asserted, but now provide a negative write current pulse  216  to word lines  106   a  and  106   b . The write- 1  terminal  200  is also asserted as shown at  218 , which closes the word line switch  108   a  and connects word lines  106   a  and  106   b  as shown. The word line current provided to write current- 1  terminals  114  thus passes down word line  106   b , through word line switch  108   a , and up word line  106   a . To select magneto-resistive memory element  102   b , the select- 2  terminal  204  is asserted as shown at  220 . This turns on the switch transistors in magneto-resistive memory element  102   b , which draws a sense current from word lines  106   a  and  106   b  and through the corresponding magneto-resistive bits. Preferably, the select- 2  terminal  204  is only asserted to a level that allows the switch transistors in the magneto-resistive memory element  102   b  to operate in the saturation region to limit the magnitude of the sense currents provided. As described above, the combination of the word line currents and the sense line currents causes the magneto-resistive bits to be written into opposite magneto-resistive states, and in the illustrative embodiment, into a state that corresponds to a logic “0”. To complete the illustrative write operation, the write current- 1  terminals  114 , write- 1  terminal  200  and the select- 2  terminal  204  are deselected. 
   Region  184  shows a write operation that writes a “1” to magneto-resistive memory element  102   d . For this write operation, the write current-N terminals  116  are asserted to provide a positive write current pulse  222  to word lines  106   c  and  106   d . The write-N terminal  202  is also asserted as shown at  224 , which closes the word line switch  108   b  and connects word lines  106   c  and  106   d  as shown. The word line current provided to write current-N terminals  116  thus passes down word line  106   c , through word line switch  108   b , and up word line  106   d . To select magneto-resistive memory element  102   d , the select- 1  terminal  130  is asserted as shown at  226 . This turns on the switch transistors in magneto-resistive memory element  102   d , which draw a sense current from word lines  106   c  and  106   d  and through the corresponding magneto-resistive bits. Preferably, the select- 1  terminal  130  is only asserted to a level that allows the switch transistors in the magneto-resistive memory element  102   d  to operate in the saturation region to limit the magnitude of the sense currents provided. As described above, the combination of the word line currents and the sense line currents causes the magneto-resistive bits to be written into opposite magneto-resistive states, and in the illustrative embodiment, into a state that corresponds to a logic “1”. To complete the illustrative write operation, the write current-N terminals  116 , write-N terminal  202  and the select- 1  terminal  130  are deselected. 
   Region  186  shows a write operation that writes a “0” to magneto-resistive memory element  102   e . For this write operation, the write current-N terminals  116  are again asserted, but now provide a negative write current pulse  228  to word lines  106   c  and  106   d . The write-N terminal  202  is also asserted as shown at  230 , which closes the word line switch  108   b  and connects word lines  106   c  and  106   d  as shown. The word line current provided to write current-N terminals  116  thus passes down word line  106   d , through word line switch  108   b , and up word line  106   c . To select magneto-resistive memory element  102   e , the select- 2  terminal  204  is asserted as shown at  232 . This turns on the switch transistors in magneto-resistive memory element  102   e , which draws a sense current from word lines  106   c  and  106   d  and through the corresponding magneto-resistive bits. Preferably, the select- 2  terminal  204  is only asserted to a level that allows the switch transistors in the magneto-resistive memory element  102   e  to operate in the saturation region to limit the magnitude of the sense currents provided. As described above, the combination of the word line currents and the sense line currents causes the magneto-resistive bits to be written into opposite magneto-resistive states, and in the illustrative embodiment, into a state that corresponds to a logic “0”. To complete the illustrative write operation, the write current-N terminals  116 , write-N terminal  202  and the select- 2  terminal  204  are deselected. 
   Region  188  shows a read operation for reading magneto-resistive memory element  102   a . During the illustrative read operation, the load- 1  terminal  120  is activated as shown at  234 . Activating the load- 1  terminal  120  causes the load transistor  144  to connect the inputs of the first inverter  140  and the second inverter  142 . Because the first inverter  140  and second inverter  142  are in a cross-coupled configuration, this causes the first inverter  140  and second inverter  142  to go into an intermediate state, and in particular, into a state where both the n-channel and p-channel transistors are at least partially on. Because both the n-channel and p-channel transistors are at least partially on, a sense line current path is provided to each of the first and second word lines  106   a  and  106   b . The resistance of each sense line current path is preferably substantially identical so that the sense line current provided to the first word line  106   a  and the sense line current provided to the second word line  106   b  are substantially identical. The write- 1  terminal  200  remains off, thereby effectively disconnecting word line  106   a  from word line  106   b.    
   To select magneto-resistive memory element  102   a , the select- 1  terminal  130  is activated as shown at  236 . This turns on the switch transistors in magneto-resistive memory element  102   a , which draws the read sense currents from word lines  106   a  and  106   b  through magneto-resistive bits  112   a  and  112   b , respectively. To reduce the resistance that is in series with the magneto-resistive bits  112   a  and  112   b , the select- 1  terminal  130  is preferably activated at a level that allows the switch transistors in the magneto-resistive memory element  102   a  to operate in the linear region, and preferably fully turned on. This may help increase the sensitivity of the read operation by minimizing the resistance of the switch transistors. 
   Because the magneto-resistive bits  112   a  and  112   b  are in opposite resistive states, the sense line currents that pass through the first and second magneto-resistive bits produce different voltages at the first and second word lines  106   a  and  106   b . This voltage differential is provided to the negative supply terminals  146  and  148  of the first and second inverters  140  and  142  via word lines  106   a  and  106   b , respectively. Thereafter, the load- 1  terminal  120  is released. Releasing the load- 1  terminal  120  causes the cross-coupled inverter pair  140  and  142  to assume the data state that corresponds to the voltage differential that is present at the negative supply terminals  146  and  148 . This state is stored by the cross-coupled inverter pair and provided to the out 1 - 1  terminal  206  as shown at  238 . 
   Finally, region  190  shows a read operation that reads magneto-resistive memory element  102   b . During this illustrative read operation, the load- 1  terminal  120  is again activated as shown at  240 . Activating the load- 1  terminal  120  causes the load transistor  144  to connect the inputs of the first inverter  140  and the second inverter  142 . Because the first inverter  140  and second inverter  142  are in a cross-coupled configuration, this causes the first inverter  140  and second inverter  142  to go into an intermediate state, and in particular, into a state where both the n-channel and p-channel transistors are at least partially on. Because both the n-channel and p-channel transistors are at least partially on, a sense line current path is provided to each of the first and second word lines  106   a  and  106   b . The resistance of each sense line current path is preferably substantially identical so that the sense line current provided to the first word line  106   a  and the sense line current provided to the second word line  106   b  are substantially identical. The write- 1  terminal  200  remains off, thereby effectively disconnecting word line  106   a  from word line  106   b.    
   To select magneto-resistive memory element  102   b , the select- 2  terminal  204  is activated as shown at  242 . This turns on the switch transistors in magneto-resistive memory element  102   b , which draws the read sense currents from word lines  106   a  and  106   b  through the corresponding magneto-resistive bits. To reduce the resistance that is in series with the magneto-resistive bits, the select- 2  terminal  204  is preferably activated at a level that allows the switch transistors in the magneto-resistive memory element  102   b  to operate in the linear region, and preferably fully turned on. This may help increase the sensitivity of the read operation by minimizing the resistance of the switch transistors. 
   Because the magneto-resistive bits are in opposite resistive states, the sense line currents that pass through the first and second magneto-resistive bits produce different voltages at the first and second word lines  106   a  and  106   b . This voltage differential is provided to the negative supply terminals  146  and  148  of the first and second inverters  140  and  142  via word lines  106   a  and  106   b , respectively. Thereafter, the load- 1  terminal  120  is released. Releasing the load- 1  terminal  120  causes the cross-coupled inverter pair  140  and  142  to assume the data state that corresponds to the voltage differential that is present at the negative supply terminals  146  and  148 . This state is stored by the cross-coupled inverter pair and provided to the out 1 - 1  terminal  206  as shown at  244 . 
     FIG. 6  is a partial cross-sectional side view of the magneto-resistive memory element  102   f  of  FIG. 4  taken along line  6 —- 6 . The magneto-resistive memory element is generally shown at  120   f , and includes a magneto-resistive bit  260 , a magneto-resistive bit  262  and switch block  268 . 
   The switch block  268  preferably includes a first transistor  270  and a second transistor  272 . The first and second transistors  270  and  272  are preferably fabricated into the under-layers of an integrated circuit, and adjacent the location of corresponding magneto-resistive bits  260  and  262 . The gates of the first transistor  270  and a second transistor  272  are preferably coupled to a buffer or the like (not shown), which is also fabricated into the under-layers of the integrated circuit. The gates of the first and second transistors  270  and  272  are preferably coupled to the buffer via a metal interconnect line, a poly-silicon line, or a combination thereof. 
   A first insulating layer is then preferably provided over the first and second transistors  270  and  272 . A metal layer may then be provided over the first insulating layer and selectively etched to form word lines  106   c  and  106   d . A second insulating layer may then be provided over word lines  106   c  and  106   d . Via holes may then be cut through the second insulating layer down to the-word lines  106   c  and  106   d.    
   The top surface of the second insulting layer is preferably planarized using a Chemical-Mechanical-Polishing (CMP) step. Once planarized, magneto-resistive bits  260  and  262  are provided. Magneto-resistive bits  260  and  262  preferably have a lower ferromagnetic thin film, an upper ferromagnetic thin film, and a thin non-ferromagnetic layer therebetween. One purpose of the thin non-ferromagnetic layer is to de-couple the magnetization vectors of the lower and upper ferromagnetic layers. The thin non-ferromagnetic layer may be, for example, copper. The upper and lower ferromagnetic thin film layers preferably exhibit uni-axial anisotropy, magneto-resistance, little magneto-striction, and are of an alloy composition that includes nickel, cobalt and iron. The magnetic device structure can be a spin valve that includes a pinned reference layer spaced apart from a free layer that stores the digital information. The lower ferromagnetic thin film is typically, but not always, thicker than the upper ferromagnetic thin film. Alternatively, a pseudo-spin valve structure can be used, where the lower ferromagnetic thin film is often called the hard layer, and the upper ferromagnetic thin film is often called the soft layer. For the memory shown in  FIG. 4 , the magnetization vector of the pinned layer preferably remains pointing in a single direction such as to the left during both read and write operations. 
   Once formed, the magneto-resistive bits  260  and  262  are preferably covered with a third insulating layer. The third insulating layer may be selectively removed to expose the bit ends of magneto-resistive bits  260  and  262 . Yet another metal layer may then be used to connect one end of magneto-resistive bits  260  and  262  to the word lines  106   c  and  106   d , respectively, preferably using one or more of the previously formed via holes, such as via hole or contact structure  266 . The same metal layer may also be used to connect the other ends of magneto-resistive bits  260  and  262  to the drain terminals of transistors  270  and  272 , respectively. 
   As can readily be seen, a word line is provided adjacent each of the magneto-resistive bits  260  and  262 . One end of each of the magneto-resistive bits  260  and  262  is connected to the corresponding word line  106   c  and  106   d , and the other end is connected to a predetermined voltage such as ground through switch block  268 . The switch block  268  selectively provides a path for a sense current to flow from the word lines  106   c  and  106   d  through magneto-resistive bits  260  and  262  and to ground. Accordingly, word line  106   c  delivers the word line current and the sense line current for magneto-resistive bit  260 , and the word line  106   d  delivers the word line current and the sense line current for magneto-resistive bit  262 . 
     FIG. 7  is a partial cross-sectional side view of yet another illustrative magneto-resistive memory element in accordance with the present invention. This illustrative embodiment is similar to that shown and described above with respect to FIG.  6 . However, the word lines  106   c  and  106   d  are positioned above the magneto-resistive bits  260  and  262 , rather than below. 
   Having thus described the preferred embodiments of the present invention, those of skill in the art will readily appreciate that the teachings found herein may be applied to yet other embodiments within the scope of the claims hereto attached.