Abstract:
The present invention discloses an adaptive voltage position DC-DC regulator and the method thereof, the regulator comprising a main circuit and a control circuit which includes a sensing unit, a feedback unit, a comparing unit, a PWM generator and a driver. The regulator realizes the adaptive voltage position control with simple internal circuit and fewer pins.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
       [0001]    This application claims priority to and the benefit under 35 U.S.C. §119 of the filing date of Chinese Application Serial No. 200810046122.9, filed on Sep. 23, 2008, which is incorporated herein by reference in its entirety. 
       TECHNICAL FIELD 
       [0002]    The present invention relates to DC-DC regulators, and more particularly, the present invention relates to adaptive voltage position DC-DC regulators. 
       BACKGROUND 
       [0003]    Recently, adaptive voltage position (AVP) control has been widely used in DC-DC regulators. The basic principle of such AVP control is referred to  FIG. 1 , wherein the y-axis represents the output voltage V O , while the x-axis represents the output current I O . The mathematic relation of the output voltage V O  and the output current I O  is: 
         [0000]        V   O   =V   SET   −R*I   O    (1) 
         [0000]    wherein the coefficient R represents the variation slope. Both V SET  and R are constants. 
         [0004]    According to equation (1), the output voltage V O  decreases when load current is increased rapidly (such as from light load condition to heavy load condition, i.e. the output current IO is increased). As can be seen from  FIG. 2 , the output voltage V O  is decreased to V MAX  from V MIN . When load current is decreased rapidly (such as from heavy load condition to light load condition, i.e., the output current I O  is decreased), the output voltage V O  is increased to V MIN  from V MAX . The variation range of the output voltage is (VMAX−VMIN), wherein VMAX and VMIN are respectively the output voltage V O &#39;s allowed positive and negative fluctuating values. However, as shown in the middle graph of  FIG. 2 , to those circuits without AVP control, the output voltage V O  is firstly decreased to VMIN, and then back to V immediately when load current is increased rapidly at time t 1 . Similarly, V O  is increased to VMAX, and then back to V immediately when load current is decreased rapidly at time t 2 . Thus the variation range of the output voltage of these circuits is 0.5*(VMAX−VMIN). However, the variation range of the output voltage of circuits with AVP control is twice than that without AVP control as shown in the bottom graph of  FIG. 2 . Furthermore, when load current is increased, the output voltage of circuits with AVP control is decreased accordingly, which reduces power loss. 
         [0005]    Prior art adaptive voltage position control is shown in  FIG. 3 . As shown in  FIG. 3 , a circuit  50  includes a conventional buck circuit as its main circuit which comprises a switch S 1 , a switch S 2 , an inductor L, a capacitor C 0 , and a load RL. Circuit  50  further includes a control circuit which comprises a current sensing resistor RS which is coupled between the inductor L and the capacitor C 0 , feedback resistors R 1  and R 2  which are coupled to the load RL in parallel, a comparator U 0 , an operational transconductance amplifier (OTA) U 1 , a current source A, a PWM generator and a driver. The OTA U 1  has its two input terminals receive the drop voltage of the current sensing resistor RS, and converts the voltage into corresponding current ISENSE which is sent to the first input terminal of the PWM generator. 
         [0006]    Feedback resistors R 1  and R 2  constitute a voltage divider, which feeds back the output voltage to the inverting input terminal of the comparator U 0  via the resistor R 3 . The comparator U 0  receives a reference VREF at its non-inverting input terminal. Current (I=K*ISENSE) provided by the current source US is sent to the inverting input terminal of the comparator U 0  and one terminal of the resistor R 3 , wherein K is a constant coefficient, while ISENSE is the output current of the OTA U 1 . The output terminal of the comparator U 0  is coupled to one terminal of a compensation net Zf—the other terminal of the compensation net Zf is grounded. The output terminal of the comparator U 0  is also coupled to the second input terminal of the PWM generator. The PWM generator has its third input terminal receive a CLK signal, while its output terminal is coupled to the input terminal of the driver. The two output terminals of the PWM generator are coupled to the gates of the switches S 1  and S 2 , respectively. 
         [0007]    The operation of the main circuit of circuit  50  is as the operation of the conventional buck circuit, which is not illustrated herein for brevity. The operation of the control circuit of circuit  50  is illustrated as follows. 
         [0008]    Since the comparator U 0  exhibits a high impedance, the current provided by the current source US flows to the resistor R 3 . According to the “virtual short” characteristic of the comparator U 0 , the voltage at its non-inverting input terminal is equal to that at its inverting input terminal, namely, 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       O 
                     
                     * 
                     
                       R 
                       2 
                     
                   
                   
                     
                       R 
                       1 
                     
                     + 
                     
                       R 
                       2 
                     
                   
                 
                 + 
                 
                   I 
                   * 
                   
                     R 
                     3 
                   
                 
               
               = 
               
                 V 
                 REF 
               
             
             , 
             
               
 
             
              
             thus 
             , 
             
               
 
             
              
             
               
                 
                   
                     
                       V 
                       O 
                     
                     = 
                       
                      
                     
                       
                         
                           ( 
                           
                             
                               R 
                               1 
                             
                             + 
                             
                               R 
                               2 
                             
                           
                           ) 
                         
                         * 
                         
                           ( 
                           
                             
                               V 
                               REF 
                             
                             - 
                             
                               I 
                               * 
                               
                                 R 
                                 3 
                               
                             
                           
                           ) 
                         
                       
                       
                         R 
                         2 
                       
                     
                   
                 
               
               
                 
                   
                     = 
                       
                      
                     
                       
                         
                           
                             V 
                             REF 
                           
                           * 
                           
                             ( 
                             
                               
                                 R 
                                 1 
                               
                               + 
                               
                                 R 
                                 2 
                               
                             
                             ) 
                           
                         
                         
                           R 
                           2 
                         
                       
                       - 
                       
                         
                           
                             
                               R 
                               3 
                             
                             * 
                             
                               ( 
                               
                                 
                                   R 
                                   1 
                                 
                                 + 
                                 
                                   R 
                                   2 
                                 
                               
                               ) 
                             
                           
                           
                             R 
                             2 
                           
                         
                         * 
                         I 
                       
                     
                   
                 
               
             
           
         
       
     
         [0000]    wherein I=K*ISENSE. As a result, 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           V 
                           O 
                         
                         = 
                           
                          
                         
                           
                             
                               
                                 V 
                                 REF 
                               
                               * 
                               
                                 ( 
                                 
                                   
                                     R 
                                     1 
                                   
                                   + 
                                   
                                     R 
                                     2 
                                   
                                 
                                 ) 
                               
                             
                             
                               R 
                               2 
                             
                           
                           - 
                           
                             
                               
                                 
                                   R 
                                   3 
                                 
                                 * 
                                 
                                   ( 
                                   
                                     
                                       R 
                                       1 
                                     
                                     + 
                                     
                                       R 
                                       2 
                                     
                                   
                                   ) 
                                 
                               
                               
                                 R 
                                 2 
                               
                             
                             * 
                             I 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             
                               
                                 V 
                                 REF 
                               
                               * 
                               
                                 ( 
                                 
                                   
                                     R 
                                     1 
                                   
                                   + 
                                   
                                     R 
                                     2 
                                   
                                 
                                 ) 
                               
                             
                             
                               R 
                               2 
                             
                           
                           - 
                           
                             
                               
                                 
                                   R 
                                   3 
                                 
                                 * 
                                 
                                   ( 
                                   
                                     
                                       R 
                                       1 
                                     
                                     + 
                                     
                                       R 
                                       2 
                                     
                                   
                                   ) 
                                 
                               
                               
                                 R 
                                 2 
                               
                             
                             * 
                             K 
                             * 
                             
                               I 
                               SENCE 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0009]    Since ISENSE is determined by the output current IO, equation (2) behaves as the same function of the output voltage VO and the output current IO as equation (1). 
         [0010]    Therefore prior art circuit  50  realizes the AVP control. That is, when the load current of circuit  50  is increased rapidly from light load condition to heavy load condition, the drop voltage of the current sensing resistor RS is increased, which causes the output current ISENSE of the OTA U 1  to be increased. Thus the output current I of the current source US is increased, which causes the output voltage of circuit  50  to be deceased according to equation (2). On the contrary, when the load current of circuit  50  is decreased rapidly from heavy load condition to light load condition, the drop voltage of the current sensing resistor RS is decreased, which causes the output current ISENSE of the OTA U 1  to be decreased. Thus the output current I of the current source US is decreased, which causes the output voltage of circuit  50  to be increased according to equation (2). Therefore, circuit  50  realizes the advantages of the AVP control such as a wide variation range of the output voltage and low power loss. 
         [0011]    However, prior art circuit  50  receives the output current which is fed back by the current sensing resistor RS through the OTA U 1 , which requires two additional pins. In addition, the current sensing resistor RS consumes power, which decreases the efficiency. Furthermore, circuit  50  needs a current source US reflecting the output current, which causes the internal circuit complicated. 
         [0012]    As a result, there is a need to provide a regulator which realizes the AVP control with simple internal circuit and fewer pins. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
           [0014]      FIG. 1  illustrates the basic principle of AVP control in a mathematic relation. 
           [0015]      FIG. 2  illustrates the output voltage comparison of circuits with and without AVP control. 
           [0016]      FIG. 3  is a schematic diagram of a prior art circuit with AVP control. 
           [0017]      FIG. 4  is a schematic diagram of a circuit with AVP control in accordance with an embodiment of the present invention. 
           [0018]      FIG. 5  is a schematic diagram of a circuit with AVP control in accordance with another embodiment of the present invention. 
           [0019]      FIG. 6  is a schematic diagram of a circuit with AVP control in accordance with yet another embodiment of the present invention. 
           [0020]      FIG. 7  is a schematic diagram of a circuit with AVP control in accordance with yet another embodiment of the present invention. 
           [0021]      FIG. 8  is a schematic diagram of a circuit with AVP control in accordance with yet another embodiment of the present invention. 
           [0022]      FIG. 9  is a schematic diagram of a circuit with AVP control in accordance with an embodiment of the present invention. 
           [0023]      FIG. 10  is a schematic diagram of a circuit with AVP control in accordance with yet another embodiment of the present invention. 
           [0024]      FIG. 11  is a schematic diagram of a circuit with AVP control in accordance with yet another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. 
         [0026]    Now referring to  FIG. 4 , a schematic diagram of circuit  100  with AVP control in accordance with an embodiment of the present invention is illustrated. It is the first embodiment of the present invention. Like elements in  FIG. 4  that are similar to prior art circuit  50  as shown in  FIG. 3  have the same reference numbers and titles. As shown in  FIG. 4 , circuit  100  includes a conventional buck circuit as its main circuit which comprises two switches S 1  and S 2 , an inductor L, a capacitor C 0 , and a load RL connected as shown. Circuit  100  also includes a resistor DCR which is the DC resistor of the inductor L, electrically coupled between the inductor L and the output capacitor CO. Circuit  100  further includes a control circuit which comprises a sensing unit, a feedback unit, a comparing unit, a PWM generator and a driver. In one embodiment, the sensing unit comprises a resistor RS and a capacitor CS coupled in series between the common coupled terminal of the switch S 1 , the switch S 2  and the inductor L and the common coupled terminal of the inductor L&#39;s DC resistor DCR, the output capacitor CO and the load RL. The sensing unit senses the output current of the regulator and converts it into a corresponding voltage, which is provided to the feedback unit. 
         [0027]    In one embodiment, the feedback unit is a divider comprised of a first resistor R 1  and a second resistor R 2 , which are coupled in series between the sensing unit and ground as shown. In one embodiment, the comparing unit includes a comparator U 0  and a compensation net Zf—wherein the compensation net Zf is coupled between the output terminal of the comparator U 0  and ground for compensation. The comparator U 0  receives a feedback signal from the feedback unit at its inverting input terminal and a reference VREF at its non-inverting input terminal. The output of the comparator U 0  is a comparison signal which is provided to the PWM generator. The PWM generator also receive a CLK signal (the clock signal generator is not shown) at another input terminal. If current control mode is adopted, the PWM generator will further receive a current sense signal of the switch S 1  or the inductor current which is represented as IHS in dotted lines. The output of the PWM generator is a PWM signal which is provided to the driver. In one embodiment, the driver receives the PWM signal and provides two driving signals to the control terminals of the switch S 1  and the switch S 2 , so as to control the ON and OFF status of these two switches. The PWM generator and the driver may be any conventional circuit designed for that purpose. 
         [0028]    The main circuit of circuit  100  adopts the conventional buck circuit, its operation is well known and will not be illustrated herein for brevity. The following text will illustrate how to realize AVP control by circuit  100 . 
         [0029]    According to the “virtual short” characteristic of the comparator U 0 , the voltage at its non-inverting input terminal is equal to that at its inverting input terminal, whose value is: 
         [0000]    
       
         
           
             
               
                 
                   ( 
                   
                     
                       V 
                       O 
                     
                     + 
                     
                       V 
                       CS 
                     
                   
                   ) 
                 
                 * 
                 
                   R 
                   2 
                 
               
               
                 
                   R 
                   1 
                 
                 + 
                 
                   R 
                   2 
                 
               
             
             , 
           
         
       
     
         [0000]    wherein VO is the output voltage of circuit  100 , VCS is the drop voltage across the capacitor CS. 
         [0000]    
       
         
           
             
               
                 
                   Thus 
                    
                   
                     
 
                   
                    
                   
                     
                       
                         
                           
                             ( 
                             
                               
                                 V 
                                 O 
                               
                               + 
                               
                                 V 
                                 CS 
                               
                             
                             ) 
                           
                           * 
                           
                             R 
                             2 
                           
                         
                         
                           
                             R 
                             1 
                           
                           + 
                           
                             R 
                             2 
                           
                         
                       
                       = 
                       
                         V 
                         REF 
                       
                     
                     , 
                     
                       
 
                     
                      
                     
                       
                         
                           = 
                         
                          
                         
                           &gt; 
                         
                          
                         
                             
                         
                          
                         
                           V 
                           O 
                         
                       
                       = 
                       
                         
                           
                             
                               ( 
                               
                                 
                                   R 
                                   1 
                                 
                                 + 
                                 
                                   R 
                                   2 
                                 
                               
                               ) 
                             
                             
                               R 
                               2 
                             
                           
                           * 
                           
                             V 
                             REF 
                           
                         
                         - 
                         
                           V 
                           CS 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The voltage drop across the resistor R S  added with the voltage drop across the capacitor C S  is equal to the voltage drop across the inductor L and its DC resistor DCR. Computed in the S domain, the voltage drop across the capacitor C S  is: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     CS 
                   
                   = 
                   
                     
                       
                         1 
                         
                           S 
                           * 
                           
                             C 
                             S 
                           
                         
                       
                       
                         
                           1 
                           
                             S 
                             * 
                             
                               C 
                               S 
                             
                           
                         
                         + 
                         
                           R 
                           S 
                         
                       
                     
                     * 
                     
                       ( 
                       
                         SL 
                         + 
                         DCR 
                       
                       ) 
                     
                     * 
                     
                       I 
                       L 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    wherein I L  is the inductor current. Thus 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     CS 
                   
                   = 
                   
                     
                       
                         
                           
                             S 
                             * 
                             L 
                           
                           DCR 
                         
                         + 
                         1 
                       
                       
                         
                           S 
                           * 
                           
                             C 
                             S 
                           
                           * 
                           
                             R 
                             S 
                           
                         
                         + 
                         1 
                       
                     
                     * 
                     DCR 
                     * 
                     
                       I 
                       L 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    If the resistance of the resistor R S  and the capacitance of the capacitor C S  satisfy the mathematic relation: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       C 
                       S 
                     
                     * 
                     
                       R 
                       S 
                     
                   
                   = 
                   
                     L 
                     DCR 
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Then equation (5) becomes: 
         [0000]        V   CS   =DCR*I   L    (7) 
         [0030]    Combining equation (7) with equation (3), we get: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     O 
                   
                   = 
                   
                     
                       
                         
                           
                             ( 
                             
                               
                                 R 
                                 1 
                               
                               + 
                               
                                 R 
                                 2 
                               
                             
                             ) 
                           
                           
                             R 
                             2 
                           
                         
                         * 
                         
                           V 
                           REF 
                         
                       
                       - 
                       
                         V 
                         CS 
                       
                     
                     = 
                     
                       
                         
                           
                             ( 
                             
                               
                                 R 
                                 1 
                               
                               + 
                               
                                 R 
                                 2 
                               
                             
                             ) 
                           
                           
                             R 
                             2 
                           
                         
                         * 
                         
                           V 
                           REF 
                         
                       
                       - 
                       
                         DCR 
                         * 
                         
                           I 
                           L 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0031]    Since the inductor current I L  is determined by the output current I O , when the resistances of the resistors R 1 , R 2 , DCR, and the voltage level of reference V REF  are set, equation (8) is equivalent, with respect to the output voltage V O  and the output current I O , to equation (1). 
         [0032]    Furthermore, regulation method used in conventional DC-DC converters is adopted by the control circuit of circuit  100  through controlling the ON and OFF status of the switch S 1  and the switch S 2  via the PWM generator and the driver. Thus, control to the whole circuit  100  is realized. 
         [0033]    Referring to  FIG. 5 , a schematic diagram of circuit  200  with AVP control in accordance with another embodiment of the present invention is illustrated. It is the second embodiment of the present invention. In contrast to circuit  100  shown in  FIG. 4 , there is a resistor R X  coupled in series with the inductor L and its DC resistor DCR, and in parallel with the resistor R S  and the capacitor C S  in circuit  200 . That is, in one embodiment, the sensing unit comprises two resistors R S , R X  and one capacitor C S . The resistor R X  is added in case the resistance of the inductor&#39;s DC resistor DCR may be too small. 
         [0034]    Referring to  FIG. 6 , a schematic diagram of circuit  200  with AVP control in accordance with yet another embodiment of the present invention is illustrated. It is the third embodiment of the present invention. In contrast to circuit  100  shown in  FIG. 4 , there is a resistor R S2  coupled in parallel with the capacitor C S  in circuit  300 . That is, in one embodiment, the sensing unit comprises two resistors R S , R S2  and one capacitor C S . The resistor R S2  is first coupled in parallel with the capacitor C S , and then they are coupled in series with the resistor R S . The resistor R S2  is used when the resistance of the inductor&#39;s DC resistor DCR may be too large. 
         [0035]    Referring to  FIG. 7 , a schematic diagram of circuit  400  with AVP control in accordance with yet another embodiment of the present invention is illustrated. It is the fourth embodiment of the present invention. In contrast to circuit  100  shown in  FIG. 4 , a resistor R S  coupled in series with the inductor L replaces the series connected resistor R S  and capacitor C S . The inductor&#39;s DC resistor DCR is neglected. That is, in one embodiment, the sensing unit comprises one resistor R S  which is coupled to the inductor L in series. 
         [0036]    According to the “virtual short” characteristic of the comparator U O , the voltage of the comparator U O  at its non-inverting input terminal is equal to that at its inverting input terminal. That is: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         ( 
                         
                           
                             V 
                             O 
                           
                           + 
                           
                             
                               R 
                               S 
                             
                             * 
                             
                               I 
                               L 
                             
                           
                         
                         ) 
                       
                       * 
                       
                         R 
                         1 
                       
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         R 
                         2 
                       
                     
                   
                   = 
                   
                     V 
                     REF 
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       = 
                     
                      
                     
                       &gt; 
                     
                      
                     
                         
                     
                      
                     
                       V 
                       O 
                     
                   
                   = 
                   
                     
                       
                         
                           ( 
                           
                             
                               R 
                               1 
                             
                             + 
                             
                               R 
                               2 
                             
                           
                           ) 
                         
                         
                           R 
                           1 
                         
                       
                       * 
                       
                         V 
                         REF 
                       
                     
                     - 
                     
                       
                         
                           R 
                           S 
                         
                         
                           R 
                           1 
                         
                       
                       * 
                       
                         I 
                         L 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0037]    Since the inductor current I L  is determined by the output current I O , when the resistances of the resistors R 1 , R 2 , and the voltage level of reference V REF  are set, equation (10) behaves the same function of the output voltage V O  and the output current I O  as equation (1). 
         [0038]    Furthermore, regulation method used in conventional DC-DC converters is adopted by the control circuit of circuit  400  through controlling the ON and OFF status of the switch S 1  and the switch S 2  via the PWM generator and the driver. Thus the control to the whole circuit  400  is realized. 
         [0039]    Referring to  FIG. 8 , a schematic diagram of circuit  500  with AVP control in accordance with yet another embodiment of the present invention is illustrated. It is the fifth embodiment of the present invention. In contrast to circuit  100  shown in  FIG. 4 , the input terminal of circuit  500  is coupled to the main circuit (the buck circuit) via an isolated circuit  10  with a transformer T. When the signal comes out from the isolated circuit  10 , the operation principle of the subsequent part of circuit  500  is same to that of circuit  100 , which will not be illustrated herein. Furthermore, the topology of the isolated circuit  10  can be half-bridge, full-bridge or forward, etc. The operation principle of the isolated circuit  10  is well known and will not be illustrated hereinafter. 
         [0040]    Referring to  FIG. 9 , a schematic diagram of circuit  600  with AVP control in accordance with yet another embodiment of the present invention is illustrated. It is the sixth embodiment of the present invention. In contrast to circuit  200  shown in  FIG. 5 , the input terminal of circuit  600  is coupled to the main circuit (the buck circuit) via a isolated circuit  20  with a transformer T. When the signal comes out from the isolated circuit  20 , the operation principle of the subsequent part of circuit  600  is same to that of circuit  200 , which will not be illustrated hereinafter. Furthermore, the topology of the isolated circuit  20  can be half-bridge, full-bridge or forward, etc. The operation principle of the isolated circuit  20  is well known and will not be illustrated hereinafter. 
         [0041]    Referring to  FIG. 10 , a schematic diagram of circuit  700  with AVP control in accordance with yet another embodiment of the present invention is illustrated. It is the seventh embodiment of the present invention. In contrast to circuit  300  shown in  FIG. 6 , the input terminal of circuit  700  is coupled to the main circuit (the buck circuit) via a isolated circuit  30  with a transformer T. When the signal comes out from the isolated circuit  30 , the operation principle of the subsequent part of circuit  700  is same to that of circuit  300 , which will not be illustrated hereinafter. Furthermore, the topology of the isolated circuit  30  can be half-bridge, full-bridge or forward, etc. The operation principle of the isolated circuit  30  is well known and will not be illustrated hereinafter. 
         [0042]    Referring to  FIG. 11 , a schematic diagram of circuit  800  with AVP control in accordance with yet another embodiment of the present invention is illustrated. It is the fifth embodiment of the present invention. In contrast to circuit  400  shown in  FIG. 7 , the input terminal of circuit  800  is coupled to the main circuit (the buck circuit) via a isolated circuit  40  with a transformer T. When the signal comes out from the isolated circuit  40 , the operation principle of the subsequent part of circuit  800  is same to that of circuit  400 , which will not be illustrated hereinafter. Furthermore, the topology of the isolated circuit  40  can be half-bridge, full-bridge or forward, etc. The operation principle of the isolated circuit  40  is well known and will not be illustrated hereinafter. 
         [0043]    The present invention further provides an adaptive voltage position control method for the DC-DC regulator that includes a main circuit and a control circuit which includes a sensing unit, a feedback unit, a comparing unit, a PWM generator part and a driver. The method comprises: sensing the output current of the main circuit; converting the sensed current into a corresponding voltage signal; feeding back the voltage signal to get a feedback signal; comparing the feedback signal with a pre-determined value to get a comparison signal; sending the comparison signal to a PWM generator to get a PWM signal; sending the PWM signal to a driver to get a driving signal; and sending the driving signal to the main circuit. In one embodiment, the pre-determined signal is a reference V REF . 
         [0044]    As described above, circuit  100 , circuit  200 , circuit  300 , circuit  400 , circuit  500 , circuit  600 , circuit  700 , and circuit  800  provided in the present invention realize the adaptive voltage position control. That is, when the load current is increased rapidly from light load condition to heavy load condition, the inductor current is increased accordingly. However, the reference V REF  keeps constant, thus the output voltage V O  is deceased according to equation (3) and/or equation (10). In contrast, when the load current is decreased rapidly from heavy load condition to light load condition, the inductor current is decreased accordingly. However, the reference V REF  keeps constant, thus the output voltage V O  is increased according to equation (3) and/or equation (10). Therefore, circuit  100 , circuit  200 , circuit  300 , circuit  400 , circuit  500 , circuit  600 , circuit  700 , and circuit  800  realize the advantages of the AVP control such as a wide variation range of the output voltage and low loss. In addition, compared to prior art circuit  50 , the circuits provided in the present invention do not need the two external pins and other external components such as the current source U S  used in circuit  50 , which makes the internal circuit simpler. 
         [0045]    While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.