Abstract:
A multipath RAKE receiver, for combining various significant component signals of a multipath fading signal and correcting the frequency error and the phase error associated with each significant component signal, consists of a multipath splitter, a plurality of delay devices, a plurality of complex multipliers, a plurality of path strength estimators, a plurality of error signal generators, a plurality of complex scaling signal updating devices, an adder, a decision circuit, and a controller. First, the controller extracts information about each significant component signal and generates initial complex scaling signals and other control and timing signals. Under the control of the controller, each delay device delays a corresponding significant component signal for a different amount of time so that all the delayed significant component signals can be aligned up. Multiplying one of the delayed significant signals by a corresponding complex scaling signal from one of the complex scaling signal updating devices, each complex multiplier puts a proper weight on a corresponding component signal and corrects both frequency error and phase error associated with this component signal. By adding the signals from all the complex multipliers together, the adder generates a summation signal. With the summation signal, the decision circuit makes a decision on the transmitted symbol. Comparing the signal from the decision circuit with a corresponding significant component signal, each error signal generator produces an error signal for the component signal. By monitoring a corresponding significant component signal, a path strength estimator generates a corresponding path strength signal. Finally, receiving all the error signals and all the path strength signals, the complex scaling signal updating devices generate updated complex scaling signals.

Description:
FEDERALLY SPONSORED RESEARCH  
         [0001]    Not Applicable  
         SEQUENCE LISTING OR PROGRAM  
         [0002]    Not Applicable  
         FIELD OF THE INVENTION  
         [0003]    The invention is generally related to a multipath receiver of a burst communication system with high symbol rate. More particularly the invention is related to combining weight adjustment device and phase adjustment device together and applying weight scaling, frequency correction, and phase correction at one complex multiplication.  
         BACKGROUND OF THE INVENTION  
         [0004]    In a wireless communication system, especially in a mobile communication system, fading occurs from times to times. Buildings, mountains, and foliage on the transmission path between a transmitter and a receiver can cause reflection, diffraction, and scattering on a propagating electromagnetic wave. The electromagnetic waves reflected from various large objects, travel along different paths of varying lengths. If there is an obstacle with sharp irregularities on the transmission path, the secondary waves resulting from the obstructing surface are present around the obstacle. Also if there are small objects, rough surfaces, and other irregularities on the transmission path, scattered waves are created. All these waves will interact with each other and result in multipath fading.  
           [0005]    A multipath signal combiner is one of the methods to deal with the multipath-fading problem. For each path of a multipath-fading signal, there is a corresponding component signal. A multipath signal combiner in a receiver is to combine all the significant component signals according to their corresponding signal strengths. On average, a multipath signal combiner can provide a signal more stable and stronger than each individual component signal and therefore improves the system performance.  
           [0006]    A demodulator of a coherent receiver has to remove both frequency error and phase error to recover data. Ordinarily, there are a frequency corrector and a phase rotator. The frequency corrector is for removing the frequency error so that the frequency error remaining after correction does not exceed a few percent of the symbol rate. The phase rotator is for getting rid of the residual frequency error and the phase error.  
           [0007]    Nowadays one of the most common burst communication systems is packet-switched communication system. As a burst communication system, a packet-switched communication system places unusual demand on a carrier recover circuit especially when the transmitted data rate is substantially high. The data received at a receiver could from a transmitter for a short length of time and then from another different transmitter for another short length of time. The different bursts of data come from different transmitters and have no phase coherence from one burst to the next in most situations. In order to achieve good efficiency, only a very small portion of each burst can be devoted to carrier recovery in a packet-switched communication system. Usually, this very small portion is located at the beginning of each burst. The symbols in the very small portion are called preamble symbols.  
           [0008]    When symbol rate is so high that the combination of Doppler frequency spread and frequency offset is no more than a few percent of a symbol rate, it is possible to use only a phase rotator to correct both the frequency error and phase error.  
           [0009]    [0009]FIG. 1 is the essential portion of a baseband multipath RAKE receiver with the capability of frequency correction and phase correction. Suppose that there are at most K significant multipath components. Multipath splitter  105  splits the received complex signal R in  into K complex component signals. Each of the delay devices  110   1  to  110   K  delays one of the K complex component signals for a different amount of time. Each of the multipliers  115   1  to  115   K  scales the output complex signal from one of the delay devices  110   1  to  110   K  by a corresponding weight from controller  130  respectively. Each of the phase rotator devices  120   1  to  120   K  rotates the output complex signal from one of the multipliers  115   1  to  115   K  by a corresponding phase from the controller  130  respectively. Adder  125  adds the output signals from the phase rotator devices  120   1  to  120   K  together to generate a summation signal. Decision circuit  130  makes decision on the transmitted symbol from the summation signal. Controller  135  collects information from various devices and generates necessary control and timing signals for relevant devices such as the delay devices  110   1  to  110   K , the multipliers  115   1  to  115   K  and the phase rotator devices  120   1  to  120   K .  
           [0010]    [0010]FIG. 2 shows the structure of a conventional phase rotator. The desired phase adjustment θ is fed to ROM (read only memory) device  205  to obtain corresponding signals sin(θ) and cos(θ). The complex input signal of the phase rotator consists of a real signal I in  and an imaginary signal Q in . Multiplier  210   1  multiplies the real signal I in  by cos(θ) to obtain the first product and multiplier  210   2  multiplies the real signal I in  by sin(θ) to obtain the second product. Multiplier  210   3  multiplies the imaginary signal Q in  by cos(θ) to obtain the third product and multiplier  210   4  multiplies the imaginary signal Q in  by sin(θ) to obtain the fourth product. Adder  215   1  subtracts the fourth product from the first product to obtain a signal I out  and adder  215   2  adds the second product to the third product to obtain a signal Q out . The output signal of the phase rotator is a complex signal (I out , Q out ).  
           [0011]    Mathematically, one can obtain  
             I   out   +jQ   out =( I   in   +jQ   in )· e   lθ =( I   in ·cos(θ)− Q   in ·sin(θ))+ j ( I   in ·sin(θ)+ Q   in ·cos(θ))  (1)  
           [0012]    Since sine and cosine functions are nonlinear functions and difficult to calculate them with enough precision on real time, usually they are pre-calculated and stored in ROM as shown in FIG. 2 and therefore a lot of hardware will be consumed.  
           [0013]    Therefore, it would be desirable to eliminate the evaluation of the nonlinear function sin(θ) and cos(θ) in a phase rotator.  
         OBJECTIVES OF THE INVENTION  
         [0014]    The primary objective of the invention is to eliminate the calculation of sine and cosine functions in a conventional phase rotator device.  
           [0015]    Another objective of the invention is to combine weight adjustment device and phase adjustment device together.  
           [0016]    Another objective of the invention is to apply weight scaling, frequency correction, and phase correction at one complex multiplication. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    The accompanying drawings, which are incorporated in and constitute a part of the specification, describe the preferred embodiment of the present invention, and together with the description, serve to explain the principle of the invention. In the figures, like reference numerals refer to the same or similar elements.  
         [0018]    [0018]FIG. 1 illustrates a conventional implementation of a multipath RAKE receiver with conventional phase rotators.  
         [0019]    [0019]FIG. 2 illustrates one of the conventional phase rotators in FIG. 1.  
         [0020]    [0020]FIG. 3 illustrates the preferred embodiment of a multipath Rake receiver of the invention with combining a weight updating device and a phase updating device as a complex scaling signal updating device.  
         [0021]    [0021]FIG. 4 illustrates a complex scaling signal updating device to update the magnitude and the phase of a complex scaling signal.  
         [0022]    [0022]FIG. 5 illustrates an implementation of the phase adjustment device in FIG. 4.  
         [0023]    [0023]FIG. 6 illustrates an implementation of the magnitude adjustment device in FIG. 4.  
         [0024]    [0024]FIG. 7 illustrates another implementation of the phase adjustment device in FIG. 4.  
         [0025]    [0025]FIG. 8 illustrates another implementation of the magnitude adjustment device in FIG. 4. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]    Detailed description of the preferred embodiment is provided herein. The embodiment illustrates a multipath RAKE receiver with phase rotators to serve both frequency error correction and phase error correction by way of examples, not by way of limitations. It is to be understood that it could be easy for those skilled in the art to modify the embodiment in many different ways without departing from the spirit and scope of the invention. Therefore, specific details disclosed are not to be interpreted as limitations, but rather as bases for the claims and as representative bases for teaching one to employ the present invention in virtually any appropriately detailed system, structure or manner.  
         [0027]    [0027]FIG. 3 shows structure of a multipath Rake receiver with combining a weight updating device and a phase updating device as a complex scaling signal updating device.  
         [0028]    Again we assume there are at most K significant paths and therefore there are at most K significant component signals.  
         [0029]    The received complex signal R in  is fed to signal register  305 , which consists of a plurality of signal shift registers with the first signal shift register coupled to the received complex signal R in  and each of the rest signal shift registers cascaded to its previous signal shift register. There is a tapped output signal from each signal shift register. The received signal R in  and all these tapped output signals are sent to matched-filter  310 .  
         [0030]    The matched filter  310  is to find the correlation between a segment of the received complex signal represented by the tapped output signals of the signal register  305  and a segment of reference signal. Coupled to the output of the matched filter  310 , controller  315  extracts the information about each significant path of a multipath fading signal from preamble symbols associated with each burst. The information could include the position, magnitude, and phase about each significant path. Generally speaking, the controller  315  collects necessary information from relevant devices and generates control and timing signals for pertinent devices.  
         [0031]    For simplicity, we further assume that all preamble symbols have a zero reference phase. The average real magnitude and imaginary magnitude for significant path k over preamble period are A Ik  and A Qk  respectively. The conjugate signal of the complex signal (A Ik  A Qk ) is (A Ik , −A Qk ), which is the initial complex scaling signal (W Ik (θ), W Qk (θ) for path k. Each of the K complex signals (A I1 , −A Q1 ), . . . , (A IK , −A QK ) is sent to one of the complex scaling signal updating devices  320   1  to  320   K  respectively.  
         [0032]    The received complex signal R in  is also sent to a multipath splitter  325  to obtain K significant component signals. Each of delay devices  330   1  to  330   K  delays one of the K significant component signals by a different amount of time. The controller  315  controls the amount of delay possessed by a delay device based on the position of a corresponding significant component signal.  
         [0033]    Complex multiplier  335   k  multiplies the output signal from the delay device  330   k  by a corresponding complex scaling signal (W Ik (n), W Qk (n)), where k=1, . . . , K and n=0, 1, 2, . . . .  
         [0034]    Adder  340  adds the K output signals from each of the K complex multipliers  335   1  to  335   K  together and decision device  345  makes a decision on the transmitted symbols from the output signal of the adder  340 . Suppose there are M possible different transmitted symbols and the decision for the current symbol is (I m , Q m ), where m takes integer value from 1 to M . . . .  
         [0035]    Error signal generators  350   1  to  350   K  receive signals from the decision circuit  345  and the complex multipliers  335   1  to  335   K  to find error signal E k , k=1, . . . , K. Each error signal E k  is a signal reflecting the phase error between the estimated transmitted signal determined by the decision device  345  and the estimated transmitted signal determined by the significant component signal k alone. Let&#39;s denote the estimated transmitted signal determined by the significant component signal k alone by (R Ik , R Qk ). One can define an error signal as  
           E   k =( I   m   +jQ   m )·( R   Ik   +j   R   Qk )* =( I   m   ·R   Ik   +Q   m   ·R   Qk )+ j ( Q   m   ·R   Ik   −I   m   ·R   Qk ) ≡E   Ik   +jE   Qk   ≡|E   k   |·e   jφ   (2)  
         [0036]    When the phase error |φ|&lt;&lt;90°, E Qk ≈0, E Ik &gt;0 and |E k |≈E Ik .  
         [0037]    Each of path strength estimators  355   1  to  355   K  receives the output signal from one of the K delay devices  330   1  to  330   K  for estimating the signal strength of a different significant path. The signal strength of a signal could be anything which can be used to measure the relatively strength of a signal, such as the power of the signal, the magnitude of the signal, or the energy of the signal in one symbol period. The signal strength of path k is represented by P k .  
         [0038]    Complex scaling signal updating devices  320   k  receives the signals from the error signal generator  350   k  and path strength estimator  355   k  to obtain a updated complex scaling signal (W Ik (n), W Qk (n)), where k=1, . . . , K and n=1, 2, 3, . . . .  
         [0039]    [0039]FIG. 4 shows a complex scaling signal updating device.  
         [0040]    The initial complex scaling signal for significant path k is denoted by (W Ik (0), W Qk (0)).  
         [0041]    The controller  315  generates initial loading signal to make multiplexer  405   1  pass A Ik  and generates updating signal to save A Ik  into register  410   1 . Also the initial loading signal makes multiplexer  405   2  pass −A Qk  and the updating signal saves −A Qk  into register  410   2 . That is, (W Ik (0), W Qk (0))=(A Ik , −A Qk ).  
         [0042]    Phase adjusting device  415  receives the error signal E k  from the error signal generator k to update the phase of the complex scaling signal (W Ik (n), W Qk (n)). The output signal of the phase adjusting device  415  is denoted by (W′ Ik (n), W′ Qk (n)).  
         [0043]    Scaling strength estimator  420  is to estimate the signal strength denoted by Wk of the complex signal (W′ Ik (n), W′ Qk (n)). Magnitude adjustment device  425  receives signals from the phase adjustment device  415  and the scaling strength estimator  420  to adjust the magnitude of (W′ Ik (n), W′ Qk (n)) to produce (W″ Ik (n), W″ Qk (n)). When the updating signal is active, the real part and imaginary part of (W″ Ik (n), W″ Qk (n)) will be loaded into the register  410   1  to  410   2  through the multiplexers  405   1  and  405   2  respectively. The updated outputs of the register  410   1  to  410   2  constitute an updated complex scaling signal denoted by (W Ik (n+1), W Qk (n+1)).  
         [0044]    [0044]FIG. 5 shows the first implementation of the phase adjustment device  415  in FIG. 4. The error signal E k  from a corresponding error signal generator  350   k  is split into real signal E Ik  and imaginary signal E Qk . Comparison circuit  505  tests if the imaginary signal E Qk  is larger than 0. If yes, the comparison circuit  505  generates a binary 1 otherwise generates a binary 0.  
         [0045]    Multiplexer  510  has two constant input signals, one is sin(α) and another is −sin(α), where α is a small positive number sin(α)&lt;&lt;1. With the control signal from the comparison circuit  505 , the multiplexer  510  selects sin(α) if E Qk &gt;0 and selects −sin(α) otherwise.  
         [0046]    The output signal of the multiplexer  510  is denoted by sin(Δθ) with Δθ=α or −α. Coupled to the output of the multiplexer  510 , multiplier  515 , multiplies sin(Δθ) by W Ik (n) from the register  410   1  to obtain the first product and multiplier  515   2  multiplies sin(Δθ) by W Qk (n) from the register  4102  to obtain the second product. Adder  5202  adds the first product to W Qk (n) to generate signal W′ Qk (n) and adder  520   1  subtracts the second product from W Ik (n) to generate signal W′ Ik (n). Mathematically,  
           W′   Ik ( n )+ j·W′   Qk ( n )=( W   Ik ( n )− W   Qk ( n )sin(Δθ))+ j ·( W   Qk ( n )+ W   Ik ( n)sin(Δθ))   (3)  
         [0047]    [0047]FIG. 6 shows the first implementation of the magnitude adjustment device in FIG. 4.  
         [0048]    Comparison circuit  605  receives the path strength P k  from the path strength estimator  355   k  and scaling strength signal W k  from scaling strength estimator  420  to generate a control signal L with two binary digits. L=00 when P k &gt;W k +h1, L=01 when W k +h1&gt;=P k &gt;=W k −h2, and L=10 when P k &lt;W k −h2. Where h1 and h2 are predefined positive numbers.  
         [0049]    With the control signal L from the comparison circuit  605 , multiplexer  610  selects one factor δ from a factor vector {overscore (δ)}. Multiplier  615   1  multiplies δ by W′ Ik (n) to obtain W″ Ik (n) and Multiplier  615   2  multiplies δ by W″ Qk (n) to obtain W′ Qk (n).  
         [0050]    Mathematically,  
           W″   Ik ( n )+ j·W″   Qk ( n )= W′   Ik ( n )·δ+ j·W′   Qk ( n )·δ  (4)  
         [0051]    With the phase adjustment device in FIG. 5 and the magnitude adjustment device in FIG. 6, the updated complex scaling signal (W Ik (n+1), W Qk (n+1)) can be expressed as:  
           W   Ik ( n+ 1)+ j·W   Qk (n+1)=( W   Ik ( n )− W   Qk ( n )−sin(Δθ))·δ+ j ·( W   Qk ( n )+ W   Ik ( n )·sin(Δθ))·δ  (5)  
         [0052]    In order to cover larger distance or have better performance, it is a common practice to increase the energy of a symbol by repeating the symbol several times to generate a large symbol. The phase error accumulated in several symbol periods or a large symbol period could be substantial. For simplicity, either a symbol period or a large symbol period is called a symbol period. In order to correct the phase error, it may be necessary to adjust the phase of a complex scaling signal several times during a large symbol period. The complex scaling signal updating device as shown in FIG. 4 with the implementation of phase adjustment device shown in FIG. 5 and the implementation shown in FIG. 6 can run one time or several times during every symbol period. To be able to adjust several times during one symbol period, the controller  315  has to make control signals such as updating signal active for a corresponding number of times during each symbol period and also to replace E Qk  by E′ Qk . Here E′ Qk  is equal to E Qk  for the first adjustment and E′ Qk =E′ Qk −E Ik ·sin(Δθ) for each of the rest adjustment during one symbol period.  
         [0053]    Another way to adjust a complex scaling signal several times is shown in FIG. 7 and FIG. 8. One can first adjust the phase of a complex scaling signal several times and then adjust the magnitude of the complex scaling signal several times.  
         [0054]    [0054]FIG. 7 shows the second implementation of the phase adjustment device in FIG. 4. It has the capability to adjust the phase of a complex scaling signal several times during a symbol period while without over adjusting.  
         [0055]    The error signal E k  from the error signal generator  350   k  is split into real signal E Ik  and imaginary signal E Qk . Multiplexer  705  receives the imaginary signal E Qk  of E k  and the signal from register  720 . There is a selecting signal C 1  from the controller  315 . When C 1 =0, the multiplexer  705  lets the imaginary signal E Qk  pass. When C 1 ≠0, the multiplexer  705  lets the signal from the register  720  pass. The output signal of the multiplexer  705  controls the selecting logic device  725  to select one number from the vector {overscore (sin(Δθ))} for best compensating phase error, where {overscore (Δθ)} is a set of numbers, which could be (α, −α), (α, 0, −α) with α being a small positive number.  
         [0056]    After the each phase adjustment, the error signal should be reduced to  
         ( E′   Ik   +j·E′Qk )· e    −j·Δθ =( E′   Ik ·cos(Δθ)+ E′   Qk ·sin(Δθ))+ j ·( E′   Qk ·cos(Δθ)− E′   Ik ·sin(Δθ))≈ E′   Ik   +j ·( E′   Qk   −E′   Ik ·sin(Δθ))  (6)  
         [0057]    Where E′ Ik =E Ik  and E′ Qk =E Qk  for the very first phase adjustment during each symbol period.  
         [0058]    Multiplier  710  multiplies E Ik  by sin(Δθ) to generate a product. Adder  715  subtracts the product from the output signal of the multiplexer  705 . Register  720  saves the subtraction and feeds the subtraction back to the multiplexer  705  as one of its input signals.  
         [0059]    The selecting signal C 1  from the controller  315  makes the multiplexer  730   1  to pass W Ik (n) for the very first time and to pass the signal from the register  745   1  for each of the rest times during each symbol period. Similarly, the selecting signal C 1  from the controller  315  makes multiplexer  7302  to pass W Qk (n) for the very first time and to pass the signal from the register  7452  for each of the rest times during each symbol period.  
         [0060]    Coupled to the output of the selecting device  725 , the multipliers  7351  and  7352  multiply sin(Δθ) by the output signal of the multiplexer  730   1  and the output signal of multiplexer  7302  respectively. Adder  740 , subtracts the output signal of multiplier  7352  from the output signal of multiplexer  730   1  to generate signal W′ Ik (n). Adder  7402  adds the output signal of multiplier  735   1  to the output signal of multiplexer  7302  to generate signal W′ Qk (n).  
         [0061]    A slight modification can be made to make sure no over adjustment. The dot line  750  shows that the selecting device  725  also receives the real signal E Ik  of an error signal E k . Also assume sin(α1) is the smallest positive element among all the elements of vector {overscore (sin(Δθ))} and sin(α2) is the largest negative element among all the elements of vector {overscore (sin(Δθ))}.  
         [0062]    No further phase updating should be allowed or the output of selecting device  725  should be set to 0, when E Ik sin(α1)&gt;2E′ Qk  and E′ Qk &gt;0, or E Ik sin(α2)&lt;2E′ Qk  and E′ Qk   &lt;0. Where E′   Qk  is the output of the multiplexer  705 .  
         [0063]    [0063]FIG. 8 shows the second implementation of the magnitude adjustment device in FIG. 4.  
         [0064]    Multiplexer  805  receives the scaling strength signal W k  from the scaling strength estimator  420  and signal from register  820 . There is a selecting signal C 2  from the controller  315 . When C 2 =0, the multiplexer  805  lets the scaling strength signal W k  from the scaling strength estimator  420  to pass. When C 2 ≠0, the multiplexer  805  lets the signal from the register  820  pass.  
         [0065]    The selecting device  810  receives the output signal of the multiplexer  801   5  and the path strength P k  from the path strength estimator  355   k  to choose one factor δ from a predefined factor vector {overscore (δ)}. Basically, when the scaling strength signal W k  is smaller than the path signal strength P k , the scaling strength signal W k  should be increased. One way to do is to select a factor larger than 1 to multiply the complex signal (W′ Ik (n), W′ Qk (n)). When scaling strength signal W k  is larger than the path strength P k , the scaling strength signal W k  should be reduced. One way to do is to select a factor smaller than 1 to multiply the complex signal (W′ Ik (n), W′ Qk (n)). When the scaling strength signal W k  is almost equal to the path strength signal P k , the scaling strength signal W k  should not be changed, or a factor 1 will be used to multiply the complex signal (W′ Ik (n), W′ Qk (n)).  
         [0066]    Multiplexer  825   1  receives signals from the phase adjustment device  415  and register  835   1 . During each symbol period, the selecting signal C 2  from the controller  315  makes multiplexer  825   1  pass W′ Ik (n) for the very first time and pass the signal from the register  835   1  for rest times. Similarly, multiplexer  825   2  receives signals from the phase adjustment device  415  and register  835   2 . During each symbol period, the selecting signal C 2  from the controller  315  makes multiplexer  825   2  pass W′ Qk (n) for the very first time and pass the signal from the register  835   2  for rest times. Multipliers  830   1  and  830   2  multiply the output signal δ of the selecting device  810  by the output signals from the multiplexer  825   1  and the multiplexer  825   2  to obtain signals W″ Ik (n) and W″ Qk (n) respectively.  
         [0067]    With the initial loading signal disabled and the updating signal enabled, the signals W″ Ik (n) and W″ Qk (n) pass the multiplexers  405   1  and  405   2  respectively and are loaded in the registers  410   1  and  410   2  respectively. The updated signals from the registers  410   1  and  4102  constitute the updated complex scaling signal (W Ik (n+1), W Ik (n+1)).