Abstract:
A control apparatus and a control method for a power factor correction power converter are provided. The control apparatus is configured to reduce the variation rate of a reference signal with a rising portion and a falling portion. When the primary winding almost completely releases the stored energy, and the falling portion of the reference signal reaches a determined condition, the control apparatus turns on a switch for increasing the stored energy of the primary winding.

Description:
This application claims priority to Taiwan Patent Application No. 097131900 filed on Aug. 21, 2008, the disclosures of which are incorporated herein by reference. 
     CROSS-REFERENCES TO RELATED APPLICATIONS 
     Not applicable. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention provides an alternative current (AC) to direct current (DC) converter structure, and more particularly, provides an AC to DC converter structure with a power factor correction (PFC) capability. 
     2. Descriptions of the Related Art 
     In most AC to DC converters, the whole circuit should exhibit a pure resistive nature to an AC input voltage. For this reason, a variety of active PFC structures have been developed which, in response to an AC input voltage, may generate a corresponding AC input current. 
     In the design of PFC, it is essential to generate a sinusoidal current with very low total harmonic distortion (THD). Both the THD and the power factor reflect the operational performances of a PFC circuit. The power factor has a maximum value of 1, and generally in practice, a THD value is acceptable as long as it is less than 15%. 
       FIG. 1  shows a PFC circuit  20  with a boost-type converter topology disclosed in U.S. Pat. No. re40016. PFC circuit  20  receives an input voltage V IN , which may be a rectified AC voltage. Resistors  38  and  40  form a voltage divider configured to provide a feedback signal V INV  to a terminal INV of an integrated circuit (IC) 32 by detecting a DC output voltage V O  of a load capacitor  76 . Capacitor  42  acts as a low-pass filter for filtering out high-frequency components of the feedback signal V INV , generating a comparison signal V CMP  to a terminal CMP of IC  32 . Secondary winding  39  corresponding to booster inductor  34  detects the zero-crossing of the current flowing through booster inductor  34 , which is accomplished via a zero current detection (ZCD) terminal of IC  32 . 
     In PFC circuits, the conventional ICs are configured to internally generate a sawtooth signal for comparison against the comparison signal V CMP  at the CMP end to modulate the on-time of the switch. The basic idea is that when the DC output voltage V O  is at a high level, the on-time of switch  36  shall be shortened to reduce the energy transferred to the output capacitor. The level of the comparison signal V CMP  decreases as the output voltage V O  increases. When the switch is turned on, the sawtooth signal V saw  begins to rise. Once the rising sawtooth signal V saw  reaching to or higher than the voltage level of the comparison signal V CMP , the switch is turned off and, accordingly, the sawtooth signal Vsaw suddenly decreases to and then remains at a minimum level without falling portion. The re-opening of the switch is triggered by purely detecting the occurrence of zero-crossing of the current flowing through the booster inductor, and the rising portion of the sawtooth signal Vsaw begins at the same time. In few successive periods of the AC input voltage V IN , the comparison signal V CMP  may be considered a constant value, so the on-time of the switch also remains roughly at a constant value. 
     In U.S. Pat. No. re40016, the on-time of switch  36 , rather than determined solely by the comparison signal V CMP , may be extended slightly to mitigate cross-over distortion as the off-time decreases “Cross-over distortion” means the THD contributed when the level of the input voltage V IN  approaches the minimum point because of the insufficient voltage across booster inductor  34  to provide power. The mitigation of the cross-over distortion will lead to a decrease in the THD. 
     However, even if the on-time is extended slightly as the off-time decreases, the off-time may still be over short, causing unnecessary high-frequency switching loss. Besides, the variation of the on-time along with the variation of the off-time may cause an increase in the THD contrary to expectation. 
     SUMMARY OF THE INVENTION 
     The primary objective of the present invention is to provide a control apparatus applied in a power-factor-correction (PFC) power converter. The converter comprises a primary winding, an auxiliary winding and a power switch. The primary winding is coupled to receive an input voltage and controlled by the power switch to increase or release the stored energy. The control apparatus comprises a reference signal generator, a detection circuit, and a driving circuit. The reference signal generator for generating a reference signal having a rising and falling portion. The slew rate of the reference signal is adjustable. The detection circuit for determining whether the input voltage approaches a zero voltage, and detecting whether the stored energy of the primary winding is almost completely released. The driving circuit for turning on the power switch to increase the stored energy of the primary winding when the stored energy of the primary winding is almost completely released and the falling portion of the reference signal reaches a predetermined condition. When the input voltage approaches the zero voltage, the slew rate of the reference signal is reduced. 
     Another objective of the present invention is to provide a control method applied in a power-factor-correction (PFC) power converter. The converter comprises a primary winding, an auxiliary winding and a power switch. The primary winding is coupled to receive an input voltage and is controlled by the power switch to increase or release the stored energy. The method comprises the following steps: generating a reference signal with a rising and falling portion; detecting whether the input voltage approaches the zero voltage; reducing the slew rate of the reference signal when the input voltage approaches the zero voltage; detecting the stored energy of the primary winding; detecting the falling portion of the reference signal; and turning on the power switch to increase the stored energy of the primary winding when the stored energy of the primary winding is almost completely released and the falling portion of the reference signal reaches a predetermined condition. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a PFC circuit of the prior art disclosed in U.S. Pat. No. re40016; 
         FIG. 2  is a schematic view of an AC to DC converter according to an embodiment of this invention; 
         FIG. 3  is a schematic view illustrating connections between the internal portions of the circuitry of an IC shown in  FIG. 2  and some peripheral devices; 
         FIG. 4  is a schematic view illustrating voltage signals at some nodes in  FIGS. 2 and 3 ; 
         FIG. 5  is a schematic view illustrating connections between the internal portions of the circuitry of an IC shown in  FIG. 2  and some peripheral devices; 
         FIG. 6  is a schematic view illustrating voltage signals at some nodes in  FIGS. 2 and 5 ; 
         FIGS. 7   a  and  7   b  are schematic views illustrating two embodiments of the reference signal generator shown in  FIG. 5  respectively; and 
         FIGS. 8   a  and  8   b  are schematic views illustrating signal variations under two different load conditions. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following description, this invention will be explained with reference to embodiments thereof. However, these embodiments are not intended to limit this invention to any specific environment, applications or particular implementations described in these embodiments. Therefore, the description of these embodiments is only for purposes of illustration rather than to limit this invention. It should be appreciated that in the following embodiments and the attached drawings, elements not related directly to this invention are omitted from depiction. To facilitate the understanding of the technical concepts of this invention, identical or similar elements or those with similar functions are labeled with the same reference numerals in the description. However, it should be emphasized that elements bearing the same labels in different embodiments may be implemented as different elements. 
     As shown in  FIG. 2 , an AC to DC converter  50  according to an embodiment of this invention is depicted therein. A rectifier  54  is configured to rectify an AC voltage to generate an input voltage V IN . Booster inductor  34 , switch  36 , capacitors  42 ,  76 , and  35 , resistors  38  and  40 , and diode  78  all have similar operating principles or play similar roles to those of  FIG. 1 , and are well-known to those skilled in the art; hence, connections and functions thereof will not be further described herein for simplicity. 
       FIG. 2  differs from  FIG. 1  primarily in the connection between IC  52  and auxiliary winding  39  as well as the internal operations or structures of IC  52 . Auxiliary winding  39  is connected to a voltage divider formed by resistors  412  and  413 . A voltage dividing point of the voltage divider may be connected to a terminal ZCD of IC  52  directly or through an optional resistor  416 . According to such a circuit connection, terminal ZCD of IC  52  may serve as a multi-function pin, which not only detects the zero-crossing of booster inductor  34  current, but also detects whether the input voltage V IN  approaches its minimum value. For example, through terminal ZCD and auxiliary winding  39 , IC  52  may detect whether the stored energy in booster inductor  34  is almost completely released to generate zero-crossing of the inductor current when switch  36  is turned off. Similarly, through terminal ZCD and auxiliary winding  39 , IC  52  may detect a value of the voltage V IN  when switch  36  is turned on to determine whether the input voltage V IN  approaches a zero voltage and take corresponding measures. 
       FIG. 3  is a schematic view illustrating the connections between the internal portions of circuitry within IC  52  shown in  FIG. 2  and some peripheral devices. Within IC  52  are provided a driving circuit  57 , a detection circuit  55  and a regulation circuit  53 . 
     Driving circuit  57  is configured to turn on or off switch  36  through a terminal Gate or a terminal Out of the IC  52  to increase or release the stored energy in the booster inductor  34  (i.e., a primary winding). 
     When switch  36  is turned off, a comparator  450  in detection circuit  55  detects the voltage at node ZCD to determine whether the stored energy in booster inductor  34  is almost completely released. In detail, when switch  36  is turned off, and the current in booster inductor  34  is approaching to zero, the voltage across auxiliary winding  39  will experience a sudden drop, resulting in a sudden drop in the voltage at node ZCD through voltage signal generation circuit  51 . In this way, it is possible for comparator  450  to determine whether the stored energy in booster inductor  34  is almost completely released by detecting such a voltage drop. 
     When switch  36  is turned on, comparator  417  and the subsequent circuits in detection circuit  55  determine whether the input voltage V IN  approaches a zero voltage. When switch  36  is turned on, the voltage across booster inductor  34  is substantially equal to the value of the input voltage V IN . The voltage across auxiliary winding  39  is in direct proportion to the voltage across booster inductor  34  by a factor of the turn ratio. The voltage at the node ZCD is also approximately proportional to the voltage across auxiliary winding  39 . Therefore, when switch  36  is turned on, the voltage at node ZCD could be adapted to represent the value of the input voltage V IN , so comparator  417  can determine whether the input voltage V IN  approaches the zero voltage by detecting the voltage at node ZCD. Moreover, when switch  36  is turned on, regulation circuit  53  can simultaneously turn on switch  415  to shift or regulate the voltage value at node ZCD by means of a current source  414  to make the voltage at the node ZCD easier for detection. This will be described in detail hereinafter. 
       FIG. 4  illustrates voltage signals at some nodes in  FIGS. 2 and 3 . From top to bottom, the curves in this figure represent voltage signals at nodes V IN , Gate, ZCD 1 , ZCDDTO and ZCDDT respectively. It can be seen from this figure that the voltage signal V IN  decreases gradually to a minimum value and then rises again. The voltage signal V GATE  at node Gate has a roughly constant on-time and a variable off-time that increases or decreases synchronously with the voltage signal V IN . When the voltage signal V GATE  is at a low level, i.e., the switch  36  is turned off, voltages V ZCD1  and V ZCD  at nodes ZCD 1  and ZCD respectively can be given by the following equation (1): 
     
       
         
           
             
               
                 
                   
                     V 
                     ZCD 
                   
                   = 
                   
                     
                       V 
                       
                         ZCD 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     = 
                     
                       
                         
                           
                             R 
                             413 
                           
                           
                             
                               R 
                               413 
                             
                             + 
                             
                               R 
                               412 
                             
                           
                         
                         · 
                         
                           V 
                           39 
                         
                       
                       = 
                       
                         
                           
                             R 
                             413 
                           
                           
                             
                               R 
                               413 
                             
                             + 
                             
                               R 
                               412 
                             
                           
                         
                         · 
                         
                           ( 
                           
                             
                               N 
                               39 
                             
                             
                               N 
                               34 
                             
                           
                           ) 
                         
                         · 
                         
                           ( 
                           
                             
                               V 
                               IN 
                             
                             - 
                             
                               V 
                               O 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     where R x  represents a resistance value of the resistor x, V 39  represents a voltage across auxiliary winding  39 , and N 39  and N 34  represent the turning numbers of auxiliary winding  39  and booster inductor  34  respectively. 
     When the voltage V GATE  is at a high level, i.e., switch  36  is turned on, the voltage V ZCD  at node ZCD and the voltage V ZCD1  at node ZCD 1  can be given by the following equations (2) and (3) respectively: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           V 
                           ZCD 
                         
                         = 
                           
                         ⁢ 
                         
                           
                             
                               
                                 R 
                                 413 
                               
                               
                                 
                                   R 
                                   413 
                                 
                                 + 
                                 
                                   R 
                                   412 
                                 
                               
                             
                             · 
                             
                               V 
                               39 
                             
                           
                           + 
                           
                             
                               ( 
                               
                                 
                                   
                                     
                                       R 
                                       413 
                                     
                                     · 
                                     
                                       R 
                                       412 
                                     
                                   
                                   
                                     
                                       R 
                                       413 
                                     
                                     + 
                                     
                                       R 
                                       412 
                                     
                                   
                                 
                                 + 
                                 
                                   R 
                                   416 
                                 
                               
                               ) 
                             
                             · 
                             
                               I 
                               414 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             
                               
                                 R 
                                 413 
                               
                               
                                 
                                   R 
                                   413 
                                 
                                 + 
                                 
                                   R 
                                   412 
                                 
                               
                             
                             · 
                             
                               ( 
                               
                                 
                                   - 
                                   
                                     
                                       N 
                                       39 
                                     
                                     
                                       N 
                                       34 
                                     
                                   
                                 
                                 · 
                                 
                                   V 
                                   IN 
                                 
                               
                               ) 
                             
                           
                           + 
                           
                             
                               ( 
                               
                                 
                                   
                                     
                                       R 
                                       413 
                                     
                                     · 
                                     
                                       R 
                                       412 
                                     
                                   
                                   
                                     
                                       R 
                                       413 
                                     
                                     + 
                                     
                                       R 
                                       412 
                                     
                                   
                                 
                                 + 
                                 
                                   R 
                                   416 
                                 
                               
                               ) 
                             
                             · 
                             
                               I 
                               414 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     
                       ZCD 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   = 
                   
                     
                       
                         
                           R 
                           413 
                         
                         
                           
                             R 
                             413 
                           
                           + 
                           
                             R 
                             412 
                           
                         
                       
                       · 
                       
                         ( 
                         
                           
                             
                               N 
                               39 
                             
                             
                               N 
                               34 
                             
                           
                           · 
                           
                             V 
                             IN 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         ( 
                         
                           
                             
                               R 
                               413 
                             
                             · 
                             
                               R 
                               412 
                             
                           
                           
                             
                               R 
                               413 
                             
                             + 
                             
                               R 
                               412 
                             
                           
                         
                         ) 
                       
                       · 
                       
                         I 
                         414 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     where I 414  represents a current value of the current source  414 . 
     Accordingly, the voltage signals V ZCD  and V ZCD1  in  FIG. 4  are plotted based on the above equations (2) and (3). The bottom dashed line in the curve of the voltage signal V ZCD  represents the corresponding voltage signal V ZCD1  at the same time points. It can be seen that when switch  36  is turned on, the voltage signal V ZCD  at node ZCD is higher than the voltage signal V ZCD1  at node ZCD 1  because of presence of the resistor  416 . In other words, in case the voltage signal V ZCD1  at node ZCD 1  is not high enough for comparator  417  to determine whether the input voltage V IN  approaches a zero voltage, resistor  416  may be provided to generate a voltage signal V ZCD  of a higher level at node ZCD. 
     When switch  36  is turned off, once the voltage signal V ZCD  falls below a reference voltage value V ref2 , comparator  450  determines that the stored energy in booster inductor  34  has almost completely been released. Subsequently, through node ZCO, comparator  450  enables driving circuit  57  to turn on switch  36 . 
     When switch  36  is turned on and the voltage signal V ZCD  at node ZCD higher than the reference voltage V ref1 , comparator  417  determines that the input voltage V IN  has approached the zero voltage.  FIG. 4  shows a voltage signal V ZCDDTO  at the node ZCDDTO, a high level of which represents that the input voltage V IN  has fallen below a certain level, i.e., has approached the zero voltage. Circuit  421  in  FIG. 3  maintains the high level portion of the voltage signal V ZCDDTO  for one switching period to remove the low level portions between the two high level portions of the voltage signal V ZCDDTO , thus generating a voltage signal V ZCDDT  with a single pulse at node ZCDDT. 
     Hence, according to the embodiment shown in  FIG. 3 , the pulse in the voltage signal V ZCDDT  can function as a signal for indicating a zero voltage crossing zone to direct other circuits of IC  52  to take necessary actions. For instance, once IC  52  determines that the zero voltage crossing zone has been reached, it will extend the on-time of switch  36  slightly. 
       FIG. 5  is a schematic view illustrating the connections between portions of the internal circuitry within IC  52  shown in  FIG. 2  and some peripheral devices. Disposed within IC  52  are driving circuit  57 , detection circuit  55 , and reference signal generator  64 .  FIG. 6  illustrates voltage signals at some nodes shown in  FIGS. 2 and 3 . From top to bottom, the curves in  FIG. 6  represent V IN , the voltage signal V ZCDCT  at node ZCDDT, a current signal I 34  through booster inductor  34 , and the voltage signals V CMP , V RAMP  and V Gate  at nodes CMP, RAMP and Gate. 
     In reference to  FIGS. 5 and 6 , detection circuit  55  in  FIG. 7  is coupled to terminal ZCD of IC  52 . Detection circuit  55  is configured to determine whether the input voltage V IN  approaches the zero value and to detect whether the stored energy in booster inductor  34  almost completely releases. As the input voltage V IN  falls and raises, detection circuit  55  correspondingly outputs a pulse from the terminal ZCDDT to indicate the zero voltage crossing zone of the input voltage V IN , as shown in  FIG. 6 . On the other hand, detection circuit  55  also outputs a voltage signal at the terminal ZCO to notice driving circuit  57  that the current through the booster inductor  34  is approaching to zero, i.e. the energy stored in booster inductor  34  is almost released. 
     The reference signal generator  64  in  FIG. 7  is coupled to terminals ZCDDT and GATE. Through terminal RAMP, reference signal generator  64  outputs a reference signal V RAMP  with a rising portion and a falling portion, as shown in  FIG. 6 . 
     As shown in  FIG. 6 , when V GATE  (the voltage signal at node Gate) is at a high level, switch  36  is turned on to increase the stored energy in booster inductor  34 , and the current I 34  increases linearly with time accordingly. Meanwhile, the reference signal V RAMP  is pulled up, resulting in the rising portion. Once the rising portion of the reference signal V RAMP  reaches or goes higher than the voltage level of the comparison signal V CMP , V GATE  transitions to a low level to turn off switch  36 , and accordingly, the current I 34  begins to decrease linearly with the time. Meanwhile, the reference signal V RAMP  begins to decrease gradually, thus resulting in the falling portion. As shown by the 1 st  and 2 nd  switching periods in  FIG. 6 , when the stored energy in booster inductor  34  almost completely releases, i.e., when the current I 34  approaches the zero value, V GATE  transitions from the low level to the high level to begin the next switching period. 
     The slew rate of V RAMP  can be varied, particularly, for instant, depending on whether the input voltage V IN  falls within the zero voltage crossing zone. In  FIG. 6 , when the input voltage V IN  fall within the zero voltage crossing zone, both the rising rate of the rising portion and the falling rate of the falling portion of V RAMP  decline. In the embodiment of  FIG. 6 , the 3 rd , 4 th  and 5 th  switching periods are all overlapped with the pulse outputted at terminal ZCDDT, in which all the rising rate and the falling rate of V RAMP  become lower (slower) than those in the 1 st  and 2 nd  switching periods not overlapped with the pulse. In other embodiments, it is possible that only the rising rate of the rising portion or the falling rate of the falling portion of V RAMP  declines in the zero voltage crossing zone. The decline of the rising rate of the rising portion means that the on-time is extended in the zero voltage crossing zone, which results in a decreased cross-over distortion and decreased THD. Unlike the case of the 1 st  and 2 nd  switching periods, in the 3 rd , 4 th  and 5 th  switching periods, V GATE  will not transition immediately from the low level to the high level when the current I 34  approaching zero, but waits until the falling portion of the reference signal V RAMP  falls to the lowest point. In other words, in the embodiment shown in  FIG. 6 , one of the conditions for V GATE  transiting from the low level to the high level is that the stored energy in the booster inductor  34  almost completely releases and the falling portion of the reference signal V RAMP  reaches the lowest point. This also means that extending the off-time may result in the decrease of the switching frequency and consequent decrease of unnecessary switching loss. 
       FIG. 7   a  depicts an embodiment of reference signal generator  64  shown in  FIG. 7 . When the voltage signal at node ZCDDT is at the low level (i.e., currently outside the zero voltage crossing zone), capacitor  719  is charged by current sources  711  and  713  together or discharged by current sources  712  and  714  together. On the other hand, when the voltage signal at node ZCDDT is at the high level (i.e., currently in the zero voltage crossing zone), capacitor  719  is charged by current source  711  alone or discharged by current source  712  alone. Considering the current source(s) for charging the capacitor as a charging current source(s), the current value of the charging current source(s) will decrease in the zero voltage crossing zone. Likewise, the current value of the discharging current source(s) will also decrease in the zero voltage crossing zone. Hence, when the voltage enters from outside into the zero voltage crossing zone, the slew rate of the reference signal V RAMP  will decrease. 
       FIG. 7   b  depicts another embodiment of the reference signal generator  64  shown in  FIG. 7 . When the voltage signal at the node ZCDDT is at the low level, capacitor  735  is charged by current source  731  or discharged by current source  732 . On the other hand, when the voltage signal at the node ZCDDT is at the high level, both capacitor  735  and  736  are charged together by current source  731  or discharged together by current source  732 . Therefore, the capacitance values of the charged or discharged capacitors decrease when the voltage enters the zero voltage cross zone. Similarly, it can be inferred that the slew rate of the reference signal V RAMP  will decrease when the voltage enters from outside into the zero voltage crossing zone. 
     The embodiment of this invention can generate an adaptive minimum off-time (T OFF-MIN ) that varies with the load.  FIGS. 8   a  and  8   b  illustrate signal variations under two different load conditions. As known from the background of this invention, the on-time (T ON , T ON ) of the switch in  FIGS. 8   a  and  8   b  is extended as V CMP  rises or as the output voltage V O  decreases. Accordingly, an extended on-time provides more energy to be transmitted to the load to increase the output voltage V O . As described in the embodiment of this invention, one of the conditions for V GATE  transiting from the low level to the high level is that the stored energy of the booster inductor  34  almost completely releases and the falling portion of the reference signal V RAMP  reaches the lowest point. In other words, the time taken for the falling portion of the reference signal V RAMP  to reach the lowest point is just the time at least in which the switch  36  shall be maintained in an off state, which is defined as the minimum off-time (T OFF-MIN , T OFF-MIN ′). As shown in  FIGS. 8   a  and  8   b , the time spent in the whole falling portion of the reference signal V RAMP  will be extended as V CMP  increases; i.e., the minimum off-time T OFF-MIN  varies adaptively with the load. 
     The above disclosure is related to the detailed technical contents and inventive features thereof. People skilled in this field may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the following claims as appended.