Abstract:
A Sigma-Delta modulator with a shared operational amplifier (op-amp) includes an integrated circuit, having two integrators sharing the op-amp, capable of integrating two input signals of the two integrators; a plurality of quantizers, coupled to the integrating circuit, for comparing outputting signals of the integrators with a predetermined signal and then generating digital outputting signals; a plurality of DACs, respectively coupled to the quantizers, for converting the digital outputting signals to analog feedback signals to the integrators; and a clock generator, for providing clock signals to the integrating circuit and the quantizers. Accordingly, layout area and power consumption of the modulator are reduced due to the shared op-amp.

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This patent application claims the benefit of U.S. provisional patent application No. 61/242,349 filed on Sep. 14, 2009, the entirety of which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to a Sigma-Delta (Σ-Δ) modulator and an associated method, and more particularly, to a multi-path Σ-Δ modulator with a shared operational amplifier (op-amp) and an associated method. 
       BACKGROUND OF THE INVENTION 
       [0003]    As science and technology develop day by day, more and more common functions (e.g., audio processing, video processing, USB/DDR processing, and power management) are integrated on one chip, referred to as a system-on-chip, i.e., an SOC. A Σ-Δ modulator widely applied to audio analog-to-digital (DA) converting and radio frequency (RF) receiving fields may also be integrated with the SOC system. 
         [0004]    The Σ-Δ modulator for converting an analog signal into a digital signal via over-sampling comprises an integrator, a quantizer, and a digital-to-analog converter (DAC).  FIG. 1  shows a schematic diagram of a conventional single-path one-stage Σ-Δ modulator. An adder subtracts a feedback signal Vfb outputted by a DAC  300  from an input signal Vin to obtain a signal represented by (a 1 *Vin−b 1 *Vfb), where a 1  and b 1  are gain factors. The obtained signal is received and integrated by an integrator  100  to obtain an integrated signal that is transmitted to a quantizer  200 . The quantizer  200  quantizes the integrated signal to obtain a digital signal Yout, which is converted by the DAC  300  into an analog signal that is then fed to the adder. 
         [0005]      FIG. 2  shows a schematic circuit diagram of a single-path one-stage Σ-Δ modulator in the prior art. On top of the quantizer  200  and the DAC  300 , the one-stage Σ-Δ modulator further comprises an op-amp  500 , a sampling component Cs, an integrating component CI, and switches S 1  to S 4 . Supposing that the op-amp  500  is in an ideal operating state, and the switches S 1  to S 4  are respectively controlled by two non-overlapped clocks P 1  and P 2 . During a first period of a clock cycle, the clock signal P 1  is at a high level, and the clock signal P 2  is at a low level. At this point, the switches S 1  and S 3  are closed, and the switches S 2  and S 4  are open. During a second period of the clock cycle, the clock signal P 1  is at a low level, and the clock signal P 2  is at a high level. At this point, the switches S 1  and S 3  are open, and the switches S 2  and S 4  are closed. Detailed descriptions are given with reference to  FIG. 3  and  FIG. 4 . Referring to  FIG. 3 , during the first period of the clock cycle, the sampling component Cs samples the input signal Vin via the switches S 1  and S 3 , such that a voltage between two ends of the sampling component Cs is Vi[n-1]. At this point, the op-amp  500  is inactive, and a voltage at an output end of the op-amp  500  is maintained as Vo[n-1]. Referring to  FIG. 4 , during the second period of the clock cycle, a sampling component Cs, the op-amp  500  and the integrating component CI are coupled in sequence. Being affected by a feedback effect of the op-amp  500 , charges of the sampling component Cs charged during the first period of the clock cycle are shifted to the integrating component CI, and a voltage at an output end of the op-amp  500  is calculated as: 
         [0000]    
       
         
           
             
               
                 Vo 
                  
                 
                   [ 
                   n 
                   ] 
                 
               
               = 
               
                 
                   Vo 
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                     ] 
                   
                 
                 + 
                 
                   
                     Ccs 
                     Cci 
                   
                    
                   
                     Vi 
                      
                     
                       [ 
                       
                         n 
                         - 
                         1 
                       
                       ] 
                     
                   
                 
               
             
             , 
           
         
       
     
         [0000]    where Ccs is a capacitance value of the component Cs, and Cci is a capacitance value of the component CI. In addition, a Z-transform of the foregoing equation is: 
         [0000]    
       
         
           
             
               Vo 
                
               
                 ( 
                 z 
                 ) 
               
             
             = 
             
               
                 Ccs 
                 Cci 
               
               * 
               
                 
                   
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                     1 
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         [0000]    Accordingly, the circuit structure in  FIG. 2  can realize a principle illustrated in  FIG. 1 . 
         [0006]    The Σ-Δ modulator is widely applied as a contribution of having a simple structure and a high conversion accuracy, and various types of multi-stage modulators are accordingly developed.  FIG. 5  and  FIG. 6  show schematic diagrams of a conventional single-path two-stage Σ-Δ modulator. The single-path two-stage Σ-Δ modulator comprises a first-stage integrating circuit and a second-stage integrating circuit, and an operating principle of the single-path two-stage Σ-Δ modulator is similar to that of the single-path one-stage Σ-Δ modulator in  FIG. 2  and shall not be described for brevity. Compared to other components, op-amps  502  and  504  as main components of the integrating circuit consume most resources of area and power consumption of an overall system. Through a current technique, a size of the second stage op-amp  504  (even op-amps after the second stage op-amp) is manufactured to be much smaller than that of the first stage op-amp  502 , so as to effectively reduce area and power consumption of the overall system. However, the single-path two stage Σ-Δ modulator still has numerous disadvantages. For example, the first stage op-amp of an one-stage or multi-stage modulator is disadvantaged by having large area, high power consumption, and high cost; op-amps are operated only during a half of the clock cycle, and are left idle during another half of the clock cycle to cause a waste of resources. 
         [0007]    In order to solve the foregoing problem that the op-amps are left idle, a technique of a two-stage integrating circuit sharing an op-amp is provided.  FIG. 7  shows a single-path two-stage Σ-Δ modulator sharing an op-amp in the prior art. The single-path two-stage Σ-Δ modulator comprises an integrator  102 , an integrator  104 , and an op-amp  506  shared by the integrators  102  and  104 . During a first period of a clock cycle, the op-amp  506  is connected to the integrator  102  to serve as a first-stage integrating circuit. During a second period of the clock cycle, the op-amp  506  is connected to the integrator  104  to serve as a second-stage integrating circuit. Operation details of the op-amp  506  connected to the integrator  102  or the integrator  104  are similar to those of the op-amp  500  of the single-path one-stage Σ-Δ modulator in  FIG. 2 , and shall not be described for brevity. The approach of sharing one op-amp by two stages of integrating circuits is capable of reducing the number of the op-amps as well as reducing area and power consumption of the overall system to some extent; nevertheless, a problem of crosstalk is incurred meanwhile. 
         [0008]      FIG. 8  shows a schematic diagram of a two-stage integrating circuit with the shared op-amp  506 , in which crosstalk is incurred. Under ideal circumstances, a gain of an op-amp under an ideal operating conditions approaches infinity, such that a voltage at a negative input end of the ideal op-amp equals a voltage at a positive input end. However, in practical applications, the gain and a bandwidth of the op-amp  506  are limited. During a first period of a clock cycle, when the op-amp  506  is connected to the integrating circuit CI, the first-stage integrating circuit performs integration, and at this point a residual voltage Vr is left at the negative input end of the op-amp  506 , such that a parasitic capacitor Cr at the negative input end of the op-amp  506  is stored with an amount of residual charge Qr represented by Qr=Cr×Vr. Therefore, during a second period of the clock cycle, the residual charge Qr enters a second-stage integrating circuit to incur crosstalk, and thus a transfer function of the Σ-Δ modulator is changed to cause performance deterioration due to the noises. 
         [0009]    In addition, in a two-stage integrating circuit that does not adopt the shared op-amp technique, since a size of an op-amp of a second-stage integrating circuit is already much smaller than that of an op-amp of a first-stage integrating circuit, the reduced amount of chip area is not obvious when the op-amp of the first-stage integrating circuit is shared by the second-stage integrating circuit. Accordingly, current various multi-paths multi-stage Σ-Δ modulators does not implement the op-amp sharing technique. 
         [0010]    In conclusion, there is a need for a solution applying the op-amp sharing technique to a multi-path multi-stage Σ-Δ modulator to yield better overall performance. 
       SUMMARY OF THE INVENTION 
       [0011]    An object of the present invention is to provide a multi-path Σ-Δ modulator with a shared op-amp and an associated auxiliary method. 
         [0012]    Another object of the present invention is to provide a multi-path Σ-Δ modulator with a shared op-amp and an associated auxiliary method, so as to reduce area and power consumption of an SOC system. 
         [0013]    Yet another object of the present invention is to provide a multi-path Σ-Δ modulator with a shared op-amp and an associated auxiliary method, so as to reduce crosstalk caused by the shared op-amp. 
         [0014]    According to an embodiment of the present invention, a multi-path Σ-Δ modulator comprises a first integrator, a second integrator, a shared op-amp, two quantizers, two DACs, and a clock signal generator. The first integrator is coupled to a first path input end, and the second integrator is coupled to a second path input end. The shared op-amp is alternately coupled to the first and second integrators to generate an integrated signal. The quantizers, respectively coupled to the first and second integrators, compare the integrated signal with a predetermined signal to output a digital signal. The DACs, respectively coupled between output ends of the quantizers and the first and second integrators, convert the digital signal outputted by the quantizers into an analog that is fed to either the first integrator or the second integrator. The clock signal generator, coupled to the first integrator, the second integrator and the quantizers, provides clock signals for controlling the first integrator, the second integrator and the quantizers. 
         [0015]    According to another embodiment of the present invention, a multi-path Σ-Δ modulator comprises a first integrator, a second integrator, a first shared op-amp, a third integrator, a fourth integrator, a second shared op-amp, two quantizers, two DACs, and a clock signal generator. The first integrator is coupled to a first path input end, and the second integrator is coupled to a second path input end. The first op-amp is alternately coupled to first and second integrators to generate a first integrated signal. The third integrator is coupled to the first path input end and the first shared op-amp, and the fourth integrator is coupled to the second path input end and the first shared op-amp. The second shared op-amp is alternately coupled to the third integrator and the fourth integrator to generate a second integrated signal according to the first integrated signal. The quantizers, respectively coupled to the third integrator and the fourth integrator, compare the second integrated signal with a predetermined signal to output a digital signal. The DACs, respectively coupled between output ends of the two quantizers and the first integrator, the second integrator, the third integrator and the fourth integrator, convert the digital signal outputted by the quantizers to an analog signal that is fed to either the first integrator and the third integrator or the second integrator and the fourth integrator. The clock generator, coupled to the first integrator, the second integrator, the third integrator, the fourth integrator and the quantizers, provides clock signals for the first integrator, the second integrator, the third integrator, the fourth integrator and the quantizers. 
         [0016]    According to an embodiment of the present invention, a multi-path Σ-Δ modulating method for a multi-path Σ-Δ modulator with a shared op-amp is provided. The multi-path Σ-Δ modulator is inputted with two signals comprising a first input signal and a second input signal, and correspondingly outputs a first output signal and a second output signal. The auxiliary method comprises sampling the first input signal during a second period of a clock cycle to obtain a first sampled signal, and integrating the first sampled signal and a feedback signal of the first output signal during a first period of the clock cycle to obtain a first integrated signal; and sampling the second input signal during a first period of a clock cycle to obtain a second sampled signal, and integrating the second sampled signal and a feedback signal of the second output signal during a second period of the clock cycle to obtain a second integrated signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The following description and figures are disclosed to gain a better understanding of the advantages of the present invention. 
           [0018]      FIG. 1  is a schematic diagram of a single-path one-stage Σ-Δ modulator in the prior art. 
           [0019]      FIG. 2  to  FIG. 4  are circuit diagrams of a conventional single-path one-stage Σ-Δ modulator. 
           [0020]      FIG. 5  and  FIG. 6  are respectively schematic diagrams of a conventional single-path two-stage Σ-Δ modulator in the prior art. 
           [0021]      FIG. 7  is a circuit diagram of a conventional single-path two-stage Σ-Δ modulator with a shared op-amp. 
           [0022]      FIG. 8  is a schematic diagram of a two-stage integrating circuit with a shared op-amp in which crosstalk is incurred. 
           [0023]      FIG. 9  is a circuit diagram of a two-path one-stage Σ-Δ modulator in accordance with a first embodiment of the present invention. 
           [0024]      FIG. 10  is a schematic diagram of a shared op-amp in which crosstalk exists in accordance with the second embodiment of the present invention. 
           [0025]      FIG. 11  is a schematic diagram of a T-type switch. 
           [0026]      FIG. 12  is a principle of a two-path two-stage Σ-Δ modulator in accordance with a first embodiment of the present invention. 
           [0027]      FIG. 13  to  FIG. 15  are circuit diagrams of the two-path two-stage Σ-Δ modulator in accordance with the first embodiment of the present invention. 
           [0028]      FIG. 16  is a schematic diagram of a two-path N-stage Σ-Δ modulator in accordance with a third embodiment of the present invention. 
           [0029]      FIG. 17  is a schematic diagram of a three-path two-stage Σ-Δ modulator in accordance with a fourth embodiment of the present invention. 
           [0030]      FIG. 18  is a timing diagram of integrators of a first-stage integrating circuit in the fourth embodiment and a timing diagram of integrators of a second-stage integrating circuit in the fourth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0031]    Details of a multi-path Σ-Δ modulator with a shared op-amp and an associated auxiliary method are given in accordance with following embodiments of the invention. 
         [0032]      FIG. 9  shows a circuit diagram of a two-path one-stage Σ-Δ modulator in accordance with a first embodiment of the present invention. The two-path one-stage Σ-Δ modulator comprises two path input ends for respectively providing input signals Vin_L and Vin_R, an op-amp  508 , two first-stage integrators (represented by a first integrator and a second integrator in the following description) sharing the op-amp  508 , and two DACs  306  and  308  respectively corresponding to the two integrators. The first integrator that receives the input signal Vin_L comprises a sampling capacitor Cs 1 _L, an integrating capacitor CI 1 _L, and switches S 11 _L, S 12 _L, S 13 _L, S 14 _L, S 31  and S 32 . The switches are respectively controlled by four clock signals P 1 , P 2 , P 1 D and P 2 D generated by a clock signal generator  600  (shown in  FIG. 9 ). In this embodiment, the four clock signals P 1 , P 2 , P 1 D and P 2 D are respectively two groups of non-overlapped clock signals; preferably, the clock signal P 1 D has a delay compared to the clock signal P 1 , and the clock signal P 2 D has a delay compared with the clock signal P 2 . Waveforms of the four clock signals are shown in  FIG. 9 . When the clock signals P 1  and P 1 D are at a high level, the input signal Vin_L flows into the sampling capacitor Cs 1 _L; and when the clock signals P 2  and P 2 D are at a high level, the sampling capacitor Cs 1 _L is coupled to the negative input end of the op-amp  508 , the integrating capacitor CI 1 _L is coupled to a negative input end and an output end of the op-amp  508 . The switch S 31  coupled between the negative input end of the op-amp  508  and the integrating capacitor CI 1 _L is controlled by the clock signal P 2 . The switch S 32  coupled between the integrating capacitor CI 1 _L and the output end of the op-amp  508  is controlled by the clock signal P 2 D. The switch S 11 _L for controlling whether to forward the input signal Vin_L into the sampling capacitor Cs 1 _L is controlled by the clock signal P 1 D. The switch S 12 _L having one end coupled between the switch S 11 _L and the sampling capacitor Cs 1 _L and one end coupled to ground is controlled by the clock signal P 2 D. The switch S 13 _L having one end coupled between the sampling capacitor Cs 1 _L and the switch S 14 _L and one end coupled to ground is controlled by the clock signal P 1 . The switch S 14 _L coupled between the sampling capacitor Cs 1 _L and a negative input end of the op-amp  508  is controlled by the clock signal P 2 . 
         [0033]    The second integrator that receives the input signal Vin_R comprises a sampling capacitor Cs 1 _R, an integrating capacitor CI 1 _R and switches S 11 _R, S 12 _R, S 13 _R, S 14 _R, S 33  and S 34 . The switches are controlled by the four clock signals generated by the clock signal generator  600 . When the clock signal P 2  and the clock signal P 2 D are at a high level, the input signal Vin_R flows into the sampling capacitor Cs 1 _R; when the clock signal P 1  and P 1 D are at a high level, the sampling capacitor Cs 1 _R is coupled to the negative input end of the op-amp  508 , and the integrating capacitor CI 1 _R is coupled to the negative input end and the output end of the op-amp  508 . The switch S 33  coupled between the negative input end of the op-amp  508  and the integrating capacitor CI 1 _R is controlled by the clock signal P 1 . The switch S 34  coupled between the integrating capacitor CI 1 _R and the output end of the op-amp  508  is controlled by the clock signal P 1 D. The switch S 11 _R for controlling whether to forward the input signal Vin_R into the sampling capacitor Cs 1 _R is controlled by the clock signal P 2 D. The switch S 12 _R having one end coupled between the switch S 11 _R and the sampling capacitor Cs 1 _R and one end coupled to ground is controlled by the clock signal P 1 D. The switch S 13 _R having one end coupled between the sampling capacitor Cs 1 _R and the switch S 14 _R and one end coupled to ground is controlled by the clock signal P 2 . The switch S 14 _R coupled between the sampling capacitor Cs 1 _R and the negative input end of the op-amp  508  is controlled by the clock signal P 1 . 
         [0034]    A principle of the two-path one-stage Σ-Δ modulator in the first embodiment is described below. 
         [0035]    During a first period of a clock cycle, the clock signals P 1  and P 1 D are at a high level, the clock signals P 2  and P 2 D are at a low level, the switches S 13 _L, S 14 _R, S 33 , S 11 _L, S 12 _R, S 34  and S 51  are closed, and the switches S 14 _L, S 13 _R, S 31 , S 12 _L, S 11 _R S 32  and S 52  are open. For the first integrator, the input signal Vin_L flows into the sampling capacitor Cs 1 _L via the switches S 11 _L and S 13 _L, i.e., the sampling capacitor Cs 1 _L samples the input signal Vin_L, and a voltage between two ends of the integrating capacitor CI 1 _L stays unchanged. For the second integrator, since the sampling capacitor Cs 1 _R is charged during a previous period of the clock cycle, under the influence of the op-amp  508 , charge stored in the sampling capacitor Cs 1 _R and charge of a feedback signal outputted by the DAC  308  are shifted to the integrating capacitor CI 1 _R via the switches S 12 _R, S 14 _R, S 33  and S 34 . After the shifting is stabilized, an output signal of the op-amp  508  is denoted as Vo_R. 
         [0036]    During a second period of the clock cycle, the clock signals P 1  and P 1 D are at a low level, the clock signals P 2  and P 2 D are at a high level, switches S 13 _L, S 14 _R, S 33 , S 11 _L, S 12 _R, S 34  and S 51  are open, and switches S 14 _L, S 13 _R, S 31 , S 12 _L, S 11 _R, S 32  and S 52  are closed. For the first integrator, since the sampling capacitor is charged during the first period of the clock cycle, under the influence of the op-amp  508 , charge stored in the sampling capacitor Cs 1 _L and charge of a feedback signal outputted by the DAC  306  are shifted to the integrating capacitor CI 1 _L via the switches S 12 _L, S 14 _L, S 31  and S 32 . After the shifting is stabilized, an output signal Vo of the op-amp  508  is denoted as Vo_L. For the second integrator, the input signal Vin_R flows into the sampling capacitor Cs 1 _R via the switches S 11 _R and S 13 _R, i.e., the sampling capacitor Cs 1 _R samples the input signal Vin_R, and a voltage between two ends of the integrating capacitor CI 1 _R stays unchanged. 
         [0037]    Referring to  FIG. 9 , two quantizers  202  and  204 , respectively coupled to the integrators via switches S 51  and S 52 , compares the output signal Vo_L or Vo_R of the op-amp  508  with a predetermined signal to output a digital signal Yout_L or Yout_R. The DAC  306  receives and converts the digital signal Yout_L into an analog signal that is fed to the first integrator, and the DAC  308  receives and converts the digital signal Your_R into an analog signal that is fed to the second integrator. Structures of the quantizers  202  and  204  and DACs  306  and  308  are readily apparent to a person having ordinary skills in the art, and shall not be described for brevity. 
         [0038]    As observed for the foregoing description, the output signal of the two-path one-stage Σ-Δ modulator is Yout_R during the first period of the clock cycle, and the output signal of the two-path one-stage Σ-Δ modulator is Yout_L during the second period of the clock cycle. In this embodiment, the op-amp  508  alternately operates for the two integrators during one complete clock cycle, and thus utilization efficiency of the op-amp  508  is effectively increased. 
         [0039]    However, crosstalk may be incurred from sharing an op-amp by two independent integrators.  FIG. 10  shows a schematic diagram of the shared op-amp  508  incurring crosstalk in accordance with the first embodiment of the present invention. Under ideal circumstances, since a gain of the op-amp  508  in ideal operating conditions approximate infinity, a voltage at the negative input end of the op-amp equals a voltage at the positive input end of the op-amp  508 . However, in practical applications, the gain and bandwidth of the op-amp  508  are limited. Therefore, during the first period of the clock cycle, when the op-amp  508  is connected to the integrating capacitor CI 1 _R, the second integrator performs integration. At this point, a residual voltage Vr′ is left at the negative input end of the op-amp  508  (shown in  FIG. 10 ), such that a parasitic capacitor Cr′ at the negative input end of the op-amp  508  is stored with an amount of residual charge Qr′ represented by Qr′=Cr′×Vr′. Therefore, during the second period of the clock cycle, the residual charge Qr enters the first integrator to generate crosstalk. Meanwhile, there are other imperfect factors in the circuits, e.g., charge injection of opening the switches S 32  and S 34  that may also incur crosstalk. In order to solve the problem of incurring crosstalk due to the shared op-amp, various solutions are provided below. 
         [0040]    In a first solution, delayed clocks are implemented to operate the switches, i.e., to close or open the switches. Since charge may be injected at the instant that the switches are opened, during the first period of the clock cycle, when a connection between the second integrator and the op-amp  508  is open, charge is injected into the parasitic capacitor Cr′ at the negative input end of the op-amp  508 . Accordingly, during the second period of the clock cycle, the injected charge flows into the first integrator to incur crosstalk. In order to solve the problem, delayed clocks are implemented. That is, referring to  FIG. 10 , the switch S 31  is coupled between the negative input end of the op-amp  508  and the integrating capacitor CI 1 _L, the switch S 32  is coupled between the integrating capacitor CI 1 _L and the output end of the op-amp  508 , the switches S 31  and S 32  are simultaneously closed, but the switch S 31  is opened before the switch S 32  is opened. Since the charge injection through the switch S 31  is constant and the charge injection through the switch S 32  is signal correlated, when the switch S 31  is opened before the switch S 32  is, the signal correlated charge through the switch S 32  is not induced to the parasitic capacitor Cr′, such that the crosstalk brought by the switches is also reduced. Likewise, the switch S 33  is coupled between the negative input end of the op-amp  508  and the integrating capacitor CI 1 _R, the switch S 34  is coupled between the integrating capacitor CI 1 _R and the output end of the op-amp  508 , the switch S 33  and the switch S 34  are simultaneously closed, but the switch S 33  is opened before the switch S 34  is opened. Generally, the delay time is determined according to actual situations, and in this embodiment, the delay time is 100 ps. It is to be noted that, the two groups of delayed clocks are optional factors of the Σ-Δ modulator, i.e., only the two non-overlapped clock signals P 1  and P 2  may also be used for controlling the switches. 
         [0041]    In a second solution, T-type switches are adopted.  FIG. 11  shows a schematic diagram of a T-type switch. When the switches S 31  and S 33  in  FIG. 10  are T-type switches in  FIG. 11 , the switch S 31  or the switch S 33  has an end A and an end B respectively coupled to the negative input end of the op-amp  508  and the integrating capacitor CI 1 _L or the integrating capacitor CI 1 _R, a third end coupled to ground (i.e., a voltage level at the third end equals that at the positive input end of the op-amp  508 ), and a fourth end coupled to the clock generator  600  (i.e., the switch S 31  or the switch S 33  is controlled by the clock signals). Accordingly, the switches S 31  and S 33  are coupled to ground when being opened, and thus the integrating capacitors CI 1 _L and CI 1 _R become better isolated from the op-amp  508  to reduce crosstalk. Likewise, when the switches S 32  and S 34  are T-type switches, the crosstalk between integrators are reduced even more effectively. 
         [0042]    In a third solution, a gain and a bandwidth of the shared op-amp are appropriately increased. While a voltage difference between the negative input end and the positive input end of the op-amp  508  becomes smaller as the gain of the bandwidth of the shared op-amp approximate infinity as in the ideal operating conditions, the residual charge stored in the parasitic capacitor Cr′ (as shown in  FIG. 10 ) also becomes less, which means that crosstalk caused by the residual charge is significantly reduced. 
         [0043]    Each of the foregoing solutions for eliminating crosstalk may be separately used or be combined with one another. For example, the solutions of using T-type switches and increasing the gain and bandwidth of the op-amp may be simultaneously applied. 
         [0044]    In addition, the sharing technique of an op-amp according to the present invention is not only applied to the two-path one-stage Σ-Δ modulator, but also applied to multi-path two-stage Σ-Δ modulators. 
         [0045]      FIG. 12  shows a schematic diagram of a two-path two-stage Σ-Δ modulator in accordance with a second embodiment of the present invention. The two-path two-stage Σ-Δ modulator comprises a first-stage integrating circuit, a second-stage integrating circuit connected to the first-stage integrating circuit, two quantizers  202  and  204  respectively coupled to the second-stage integrating circuit, two DACs  306  and  308  respectively coupled to the two quantizers  202  and  204 , and a clock signal generator (not shown). The first-stage integrating circuit comprises two integrators  106  and  110 , and two adders (i.e., a first adder and a second adder) respectively coupled to the integrators  106  and  110 . The integrators  106  and  110  share an op-amp  508 . It is to be noted that, since the two quantizers  202  and  204 , two DACs  306  and  308 , and the op-amp  508  in this embodiment are respectively of the same functions as those in the first embodiment, they&#39;re designated by same numbers for illustration purposes. The second-stage integrating circuit comprises two integrators  108  and  112 , and two adders (i.e., a third adder and a fourth adder) respectively coupled to the integrators  108  and  112 . The integrators  108  and  112  share an op-amp  510 . The integrator  108  is coupled to the integrator  106  via the third adder, and the integrator  112  is coupled to the integrator  110  via the fourth adder. In  FIG. 12 , a 1 , a 2 , b 1  and b 2  are gain factors, and are indicated for illustration purposes. The principle of the two-path two-stage Σ-Δ modulator is described below. The first adder subtracts two products of respectively multiplying an input signal Vin_L and a feedback signal Vfb_L outputted by the DVC  306  by the gain factors a 1  and b 1  to obtain an output signal (i.e., a 1 *Vin_L−b 1 *Vfb_L)) of the first adder. The integrator  106  receives and integrates the output signal of the first adder to obtain an integrated signal Vo 1 _L that is transmitted to the third adder. The third adder subtracts two products of respectively multiplying the input signal Vin_L and the feedback signal Vfb_L outputted by the DAC  306  by the gain factors a 2  and b 2  to obtain a result, and adds the result to the integrated signal Vo 1 _L to obtain an output signal (i.e., Vo 1 _L+a 2 *Vin_L−b 2 *Vfb_L) of the third adder. The integrator  108  receives and integrates the output signal of the third adder to obtain an integrated signal Vo 2 _L that is transmitted to the quantizer  202 . The quantizer  202  compares the integrated signal Vo 2 _L with a predetermined signal to output a digital signal Yout. The DAC  306  receives and converts the digital signal Yout outputted by the quantizer  202  into an analog signal (i.e., the feedback signal) Vfb_L that is then fed to the first-stage integrating circuit and the second-stage integrating circuit. For an input signal Vin_R, the second adder subtracts two products of respectively multiplying the input signal Vin_R and a feedback signal Vfb_R outputted by the DAC  308  by the gain factors a 1  and b 1  to obtain an output signal (i.e., a 1 *Vin_R−b 1 *Vfb_R) of the second adder. The integrator  112  receives and integrates the output signal of the second adder to obtain an integrated signal Vo 1 _R that is transmitted to the fourth adder. The fourth adder subtracts two products of multiplying the input signal Vin_R and the feedback signal outputted by the DAC  308  by the gain factors a 2  and b 2  to obtain a result, and adds the result to the integrated signal Vo 1 _R so as to obtain an output signal (i.e., Vo_R+a 2 *Vin_R−b 2 *Vfb_R) of the fourth adder. The integrator  112  receives and integrates the output signal of the fourth adder into an integrated signal Vo 2 _R that is transmitted to the quantizer  204 . The quantizer  204  compares the integrated signal Vo 2 _R with a predetermined signal to output a digital signal Yout. The DAC  308  receives and converts the digital signal Yout outputted by the quantizer  204  into an analog signal (i.e., the feedback signal) Vfb_R that is then fed to the first-stage integrating circuit and the second-stage integrating circuit. 
         [0046]      FIG. 13  shows a circuit diagram of the two-path two-stage Σ-Δ modulator in accordance with the second embodiment of the present invention. The first-stage integrating circuit comprises two path input ends for respectively providing two input signals Vin_L and Vin_R, the op-amp  508 , two first-stage integrators (i.e., a first integrator and a second integrator in the following description) sharing the op-amp  508 , and DACs  310  and  312  respectively corresponding to the first integrator and the second integrator. The first integrator that receives the input signal Vin_L comprises a sampling capacitor Cs 1 _L, an integrating capacitor CI 1 _L, and switches S 11 _L, S 12 _L, S 13 _L, S 14 _L, S 31  and S 32 . The foregoing switches are controlled by four clock signals P 1 , P 2 , P 1 D and P 2 D generated by a clock signal generator  600  as shown in  FIG. 13 . In this embodiment, the four clock signals P 1 , P 2 , P 1 D and P 2 D are non-overlapped clock signals. Preferably, the delayed clock signals P 1 D/P 2 D are similar but with a slight delay compared with the clock signals P 1 /P 2 . Waveforms of the four clock signals are shown in  FIG. 13 . When the clock signals P 1  and P 1 D are at a high level, the input signal Vin_L flows into the sampling capacitor Cs 1 _L. When the clock signals P 2  and P 2 D are at a high level, the sampling capacitor Cs 1 _L is coupled to a negative input end, and the sampling capacitor CI 1 _l is coupled to the negative input end and an output end of the op-amp  508 . The switch S 31  coupled between the negative input end of the op-amp  508  and the integrating capacitor CI 1 _L is controlled by the clock signal P 2 . The switch S 32  coupled between the integrating capacitor CI 1 _L and the output end of the op-amp  508  is controlled by the clock signal P 2 D. The switch S 11 _L for controlling whether to forward the input signal Vin_L into the sampling capacitor Cs 1 _L is controlled by the clock signal P 1 D. The switch S 12 _L having one end coupled between the switch S 11 _L and the sampling capacitor Cs 1 _L and one end coupled to ground is controlled by the clock signal P 2 D. The switch S 13 _L having one end coupled between the sampling capacitor Cs 1 _L and the switch S 14 _L and one end coupled to ground is controlled by the clock signal P 1 . The switch S 14 _L coupled between the sampling capacitor Cs 1 _L and the negative input end of the op-amp  508  is controlled by the clock signal P 2 . The second integrator of the first-stage integrating circuit that receives the input signal Vin_R comprises a sampling capacitor Cs 1 _R, an integrating capacitor CI 1 _R, and switches S 11 _R, S 12 _R, S 13 _R, S 14 _R, S 33  and S 34 . The switches are respectively controlled by the four clock signals generated by the clock signal generator  600 . When the clock signals P 2  and P 2 D at a high level, the input signal Vin_R flows into the sampling capacitor Cs 1 _R; when the clock signals P 1  and P 1 D are at a high level, the sampling capacitor Cs 1 _R is coupled to the negative input end of the op-amp  508 , and the integrating capacitor CI 1 _R is coupled to the negative input end and the output end of the op-amp  508 . The switch S 33  coupled between the negative input end of the op-amp  508  and the integrating capacitor CI 1 _R is controlled by the clock signal P 1 . The switch S 34  coupled between the integrating capacitor CI 1 _R and the output end of the op-amp  508  is controlled by the clock signal P 1 D. The S 11 _R for controlling whether to forward the input signal Vin_R into the sampling capacitor Cs 1 _R is controlled by the clock signal P 2 D. The switch S 12 _R having one end coupled between the switch S 11 _R and the sampling capacitor Cs 1 _R and one end connected to ground is controlled by the clock signal P 1 D. The switch S 13 _R having one end coupled between the sampling capacitor Cs 1 _R and the switch S 14 _R and one end connected to ground is controlled by the clock signal P 2 . The switch S 14 _R coupled between the sampling capacitor Cs 1 _R and the negative input end of the op-amp  508  is controlled by the clock signal P 1 . 
         [0047]    The second-stage integrating circuit comprises two path input ends for respectively providing two input signals Vin_L and Vin_R, an op-amp  510 , two second-stage integrators (i.e., a third integrator and a fourth integrator in the following description) sharing the op-amp  510 , and DACs  314  and  316  respectively corresponding to the third integrator and the fourth integrator. The third integrator receives the input signal Vin_L and is coupled to the output end of the op-amp  508 . The third integrator comprises a sampling capacitor Cs 2 _L, an integrating capacitor CI 2 _L, a sampling capacitor Ca 2 _L, and switches S 21 _L, S 22 _L, S 23 _L, S 24 _L, S 25 _L, S 26 _L, S 41  and S 42 . The foregoing switches are respectively controlled by the four clock signals generated by the clock signal generator  600 . When the clock signals P 2  and P 2 D are at a high level, the output signal Vo 1  outputted by the op-amp  508  flows into the sampling capacitor Cs 2 _L, and the input signal Vin_L flows into the sampling capacitor Ca 2 _L. When clock signals P 1  and P 1 D are at a high level, the sampling capacitors Cs 2 _L and Ca 2 _L are coupled to a negative input end of the op-amp  510 , and the integrating capacitor CI 2 _L is coupled to the negative input end and an output end of the op-amp  510 . The switch S 41  coupled between the negative input end of the op-amp  510  and the integrating capacitor CI 2 _L is controlled by the clock signal P 1 . The switch S 42  coupled between the integrating capacitor CI 2 _L and the output end of the op-amp  510  is controlled by the clock signal P 1 D. The switch S 21 _L for controlling whether to forward the output signal Vo 1  outputted by the op-amp  508  into the sampling capacitor Cs 2 _L is controlled by the clock signal P 2 D. The switch S 22 _L having one end coupled between the switch S 21 _L and the capacitor Cs 2 _L and one end coupled to ground is controlled by the clock signal P 1 D. The switch S 23 _L having one end coupled between the capacitor Cs 2 _L and the switch S 24 _L and one end coupled to ground is controlled by the clock signal P 2 . The switch S 24 _L coupled between the sampling capacitor Cs 2 _L and the negative input end of the op-amp  510  is controlled by the clock signal P 1 . The switch S 25 _L for controlling whether to forward the input signal Vin_L into the sampling capacitor Ca 2 _L is controlled by the clock signal P 2 D. The switch S 26 _L having one end coupled between the switch S 25 _L and the sampling capacitor Ca 2 _L and one end coupled to ground is controlled by the clock signal P 1 D. The fourth integrator that receives the input signal Vin_R comprises a sampling capacitor Cs 2 _R, an integrating capacitor CI 2 _R, a sampling capacitor Ca 2 _R, switches S 21 _R, S 22 _R, S 23 _R, S 24 _R, S 25 _R, S 26 _R, S 43 , and S 44 . The switches are also controlled by the four clock signals generated by clock signal generator  600 . When the clock signal P 1  and P 1 D are at a high level, the output signal Vo 1  of the op-amp  508  flows into the sampling capacitor Cs 2 _R, and the input signal Vin_R flows into the sampling capacitor Ca 2 _R. When the clock signals P 2  and P 2 D are at a high level, the sampling capacitors Cs 1 _R and Ca 2 _R are coupled to the negative input end of the op-amp  510 , and the integrating capacitor CI 2 _R is coupled to the negative input end and the output end of the op-amp  510 . The switch S 43  coupled between the negative input end of the op-amp  510  and the integrating capacitor CI 2 _R is controlled by the clock signal P 2 . The switch S 44  coupled between the integrating capacitor CI 2 _R and the output end of the op-amp  510  is controlled by the clock signal P 2 D. The switch S 21 _R controlling whether to forward the output signal Vo 1  of the op-amp  508  into the sampling capacitor Cs 2 _R is controlled by the clock signal P 1 D. The switch S 22 _R having one end coupled between the switch S 21 _R and the sampling capacitor Cs 2 _R and one end coupled to ground is controlled by the clock signal P 2 D. The switch S 23 _R having one end coupled between the capacitor Cs 2 _R and the switch S 24 _R and one end coupled to ground is controlled by the clock signal P 1 . The switch S 24 _R coupled between the sampling capacitor Cs 2 _R and the negative input end of the op-amp  510  is controlled by the clock signal P 2 . The switch S 25 _R for controlling whether to forward the input signal Vin_R to the sampling capacitor Ca 2 _R is controlled by the clock signal P 1 D. The switch S 26 _R having one end coupled between the switch S 25 _R and the sampling capacitor Ca 2 _R and one end coupled to ground is controlled by the clock signal P 2 D. 
         [0048]    The two-path two-stage Σ-Δ modulator in  FIG. 13  further comprises two quantizers  202  and  204  respectively connected to the second-stage integrating circuit via switches S 51  and S 52 . The quantizers  202  and  204  compare an output signal Vo 2  outputted by the op-amp  510  of the second-stage integrating circuit with a predetermined signal to output a digital signal Yout_L or Yout_R. The DACs  310  and  314  respectively receive and convert the digital signal Yout_L into an analog signal that is fed to the first integrator and the third integrator. The DACs  312  and  316  respectively receive and convert the digital signal Yout_R into an analog signal that is fed to the second integrator and the fourth integrator. Structures of the quantizers  202  and  204  and the DACs  310 ,  312 ,  314  and  316  are readily apparent to a person having ordinary skills in the art, and shall not be described for brevity. 
         [0049]    Referring to  FIG. 13 , the clock signals P 1  and P 2 , and the clock signals P 1 D and P 2 D are two groups of non-overlapped clock signals. In this embodiment, the clock signal P 1 D is delayed by 100 ps compared with the clock signal P 1 , and the clock signal P 2 D is delayed by 100 ps compared with the clock signal P 2 . The structure of the control signal generator  600  is readily apparent to a person having ordinary skills in the art, and shall not be described for brevity. 
         [0050]    The principle of the two-path two-stage Σ-Δ modulator is described below. 
         [0051]      FIG. 14  shows a circuit diagram of the two-path two-stage Σ-Δ modulator in  FIG. 13  during a first period of a clock cycle in accordance with the second embodiment of the present invention. During the first period of the clock cycle, the clock signals P 1  and P 1 D are at a high level, the clock signals P 2  and P 2 D are at a low level, the switches S 13 _L, S 14 _R, S 33 , S 24 _L, S 23 _R, S 41 , S 11 _L, S 12 _R, S 34 , S 22 _L, S 26 _L, S 21 _R, S 25 _R, S 42  and S 51  are closed, and the switches S 14 _L, S 13 _R, S 31 , S 23 _L, S 24 _R, S 43 , S 12 _L, S 11 _R, S 32 , S 21 _L, S 25 _L, S 26 _R, S 22 _R, S 44  and S 52  are open. Relative positions of the foregoing switches and components are identical to those in  FIG. 10 , and shall not be described for brevity. For the first integrator, the input signal Vin_L flows into the sampling capacitor Cs 1 _L via the switch S 11 _L and the switch S 13 _L, i.e., the sampling capacitor Cs 1 _L samples the input signal Vin_L. For the second integrator, since the sampling capacitor Cs 1 _R is charged during a previous period of the clock cycle, under the influence of the op-amp  508 , charge stored in the sampling capacitor Cs 1 _R and charge of a feedback signal outputted by the DAC  312  are shifted to the integrating capacitor CI 1 _R via the switches S 12 _R, S 14 _R, S 33  and S 34 . After the shifting is stabilized, an output signal Vo 1  of the op-amp  508  is denoted as Vo 1 _R. For the third integrator, since the sampling capacitor Ca 2 _L and the sampling capacitor Cs 2 _L are charged during the previous period of the clock cycle, under the influence of the op-amp  510 , charge stored in the sampling capacitor Ca 2 _L and the sampling capacitor Cs 2 _L and charge of a feedback signal outputted by the DAC  314  are shifted to the integrating capacitor CI 2 _L via the switches S 26 _L, S 22 _L, S 24 _L, S 41  and S 42 . After the shifting is stabilized, an output signal Vo 2  of the op-amp  510  is denoted as Vo 2 _L. For the fourth integrator, the output signal Vo 1 _R of the op-amp  508  flows into the sampling capacitor Cs 2 _R via the switches S 21 _R and S 23 _R, i.e., the sampling capacitor Cs 2 _R samples the output signal Vo 1 _R of the op-amp  508 . At this point, the input signal Vin_R flows into the sampling capacitor Ca 2 _R via the switches S 25 _R and S 23 _R, i.e., the sampling capacitor Ca 2 _R samples the input signal Vin_R. Since the switch S 51  is closed, the output signal Vo 2 _L of the op-amp  510  is quantized by the quantizer  202  to generate an output signal Yout_L, which is first converted by the DACs  310  and  314  and is then respectively fed to the first integrator and the third integrator. 
         [0052]      FIG. 15  shows circuits of the two-path two-stage Σ-Δ modulator in  FIG. 13  during a second period of the clock cycle in accordance with the second embodiment of the present invention. During the second period of the clock cycle, the clock signals P 1  and P 1 D are at a low level, P 2  and P 2 D are at a high level, the switches S 13 _L, S 14 _R, S 33 , S 24 _L, S 23 _R, S 41 , S 11 _L, S 12 _R, S 34 , S 22 _L, S 26 _L, S 21 _R, S 25 _R, S 42 , and S 51  are open, and the switches S 14 _L, S 13 _R, S 31 , S 23 _L, S 24 _R, S 43 , S 12 _L, S 11 _R, S 32 , S 21 _L, S 25 _L, S 26 _R, S 22 _R, S 44  and S 52  are closed. For the first integrator, since the sampling capacitor Cs 1 _L is charged during the first period of the clock period, under the influence of the op-amp  508 , charge stored in the sampling capacitor Cs 1 _L and charge of a feedback signal outputted by the DAC  310  are shifted to the integrating capacitor CI 1 _L via the switches S 12 _L, S 14 _L, S 31  and S 32 . After the shifting is stabilized, an output signal Vo 1  of the op-amp  508  is denoted as Vo 1 _L. For the second integrator, the input signal Vin_R flows into the sampling capacitor Cs 1 _R via the switches S 11 _R and S 13 _R, i.e., the sampling capacitor Cs 1 _R samples the input signal Vin_R. For the third integrator, the output signal Vo 1 _L of the op-amp  508  flows into the sampling capacitor Cs 2 _L via the switches S 21 _L and S 23 _L, i.e., the sampling capacitor Cs 2 _L samples the output signal Vo 1 _L of the op-amp  508 . At this point, the input signal Vin_L flows into the sampling capacitor Ca 2 _L via the switches S 25 _L and S 23 _L, i.e., the sampling capacitor Ca 2 _L samples the input signal Vin_L. For the fourth integrator, since the sampling capacitors Ca 2 _R and Cs 2 _R are charged during the first period of the clock cycle, under the influence of the op-amp  510 , charge of the sampling capacitors Ca 2 _R and Cs 2 _R and charge of a feedback signal outputted by the DACs are shifted to the integrating capacitor CI 2 _R via the switches S 26 _R, S 22 _R, S 24 _R, S 43  and S 44 , and an output signal of the op-amp  510  is denoted as Vo 2 _R. Since the switch S 52  is closed, the output signal Vo 2 _R of the op-amp  510  is quantized by the quantizer  204  to generate an output signal Yout_R, which is first converted by the DACs  312  and  316  and is then respectively fed to the second integrator and the fourth integrator. 
         [0053]    As mentioned above, according to the two-path two-stage Σ-Δ modulator provided by the present invention, only one integrator of each stage integrating circuit performs integration at a time, and meanwhile another integrator of the stage integrating circuit performs sampling. 
         [0054]    Crosstalk may also be incurred from sharing an op-amp by two independent integrators. Since a gain of an op-amp in ideal operating conditions approximate infinity, a voltage at a negative input end of the op-amp equals a voltage at a positive input end of the op-amp. However, in practical applications, the gain and bandwidth of the op-amp  508  are limited. Therefore, in  FIG. 14 , during the first period of the clock cycle, when the op-amp  508  is connected to the integrating capacitor CI 1 _R, the second integrator of the first-stage integrating circuit performs integration. At this point, a residual voltage Vr′ is left at the negative input end of the op-amp  508 , such that a parasitic capacitor Cr′ at the negative input end of the op-amp  508  is stored with an amount of residual charge Qr′ represented by Qr′=Cr′×Vr′. Therefore, during the second period of the clock cycle, the residual charge Qr enters the first integrator and the second-stage integrating circuit to generate crosstalk. Meanwhile, there are other imperfect factors in the circuits, e.g., charge injection of opening the switches S 32  and S 34  that may also incur crosstalk. It is to be noted that, the crosstalk incurred in the first stage of integrators needs to be attended to most. The reason is that the Σ-Δ modulator has a noise shaping function, and influences on the Σ-Δ modulator caused by the crosstalk incurred at back-end stages are significantly reduced. 
         [0055]    In this embodiment, the foregoing three solutions (i.e., implementing delayed clocks to operate the switches, adopting T-type switches, and appropriately increasing a gain and a bandwidth of the shared op-amp described in the first embodiment) may also adopted to solve the problem of incurring crosstalk due to the shared op-amp. Other than the foregoing three solutions, a gain factor a 2  is brought. Influences of a feed-forward gain factor a 2  are brought into each of the integrators of the second-stage integrating circuit. The feed-forward gain factor a 2  of the third integrator is realized by the sampling capacitor Ca 2 _L and the integrating capacitor CI 2 _L, and the feed-forward gain factor a 2  of the fourth integrator is realized by the sampling capacitor Ca 2 _R and the integrating capacitor CI 2 _R. By properly adjusting the feed-forward gain factors a 2  of the second-stage integrating circuit, signal components of the output signal of the first-stage integrating circuit are restrained. When the output signal of the first-stage integrating circuit comprises highly-attenuated signal components, crosstalk between integrators of the first-stage integrating circuit only brings shaped quantized noises and significantly-reduced signal components. 
         [0056]    Each of the foregoing solutions for eliminating crosstalk may be separately used or be combined with one another. For example, the solutions of adding the feed-forward gain factor a 2  and increasing the gain and bandwidth of the op-amp may be simultaneously applied. 
         [0057]      FIG. 16  shows a schematic diagram of a two-path N-stage Σ-Δ modulator in accordance with a third embodiment of the present invention. N is a positive integer larger than or equal to 1. In a first-stage integrating circuit, an integrator  106  and an integrator  110  sharing an op-amp  508  simultaneously process two input signals Vin_L and Vin_R inputted from two path input ends. In an N-th integrating circuit, an integrator  108  and an integrator  112  sharing an op-amp  510  simultaneously process the two input signals Vin_L and Vin_R, an output signal of a previous-stage integrating circuit, and received feedback signals. Since the principle of two-path N-stage Σ-Δ modulator in this embodiment is similar to that of the second embodiment and may be inferred from the first embodiment, it shall not be described for brevity. 
         [0058]      FIG. 17  shows a schematic diagram of a three-path two-stage Σ-Δ modulator in accordance with a fourth embodiment of the present invention. In a first-stage integrating circuit, integrators  106 ,  110  and  114  sharing an op-amp  508  simultaneously process input signals Vin_ 1 , Vin_ 2  and Vin_ 3  from three path input ends. In a second-stage integrating circuit, integrators  108 ,  112 ,  116  sharing an op-amp  510  simultaneously process the input signals Vin_ 1 , Vin_ 2  and Vin_ 3 , output signals Vo 1 _ 1 , Vo 2 _ 2  and Vo 1 _ 3  of the integrators  106 ,  110 ,  114 . 
         [0059]      FIG. 18  shows a timing diagram of each of integrators of a first-stage integrating circuit in the fourth embodiment and a timing diagram of each of integrators of a second-stage integrating circuit in the fourth embodiment of the present invention. The principle of the embodiment is given with reference to  FIG. 18 . 
         [0060]    During a first period of a clock cycle Ts, in the first-stage integrating circuit, the integrator  106  integrates the input signal Vin_ 1 , and the integrators  110  and  114  respectively sample the input signals Vin_ 2  and Vin_ 3 . At this point, in the second-stage integrating circuit, the integrator  116  performs integration, the integrator  108  samples the input signal Vin_ 1  and the output signal Vo 1 _ 1  of the integrator  106 , and the integrator  112  is idle, i.e., the integrator  112  performs neither sampling nor integrating. During a second period of the clock cycle, in the first-stage integrating circuit, the integrator  110  integrates the input signal Vin_ 2 , and the integrators  106  and  114  respectively sample the input signals Vin_ 1  and Vin_ 3 . At this point, in the second-stage integrating circuit, the integrator  108  performs integration, the integrator  112  samples the input signal Vin_ 2  and the outputs signal Vo 1 _ 2  outputted by the integrator  110 , and the integrator  116  is idle, i.e., the integrator  116  performs neither sampling nor integrating. During a third stage of the clock cycle, in the first-stage integrating circuit, the integrator  114  integrates the input signal Vin_ 3 , the integrators  106  and  110  samples the input signals Vin_ 1  and Vin_ 2 . At this point, in the second-stage integrating circuit, the integrator  112  performs integration, the integrator  116  samples the input signal Vin_ 3  and the output signal Vo 1 _ 3  outputted by the integrator  114 , and the integrator  108  idle, i.e., the integrator  108  performs neither sampling nor integrating. 
         [0061]    According to an embodiment of the present invention, an auxiliary method for a multi-path Σ-Δ modulator applied to a multi-path Σ-Δ modulator is provided. The multi-path Σ-Δ modulator comprises one shared op-amp, is inputted with one first input signal and one second input signal, and outputs one first output signal and one second output signal. 
         [0062]    The auxiliary method comprises sampling the first input signal during a second period of a clock cycle to obtain a first sampled signal, and integrating the first sampled signal and a feedback of the first output signal during a first period of the clock cycle to obtain a first integrated signal; and sampling the second input signal during a first period of the clock cycle to obtain a second sampled signal, and integrating the second sampled signal and a feedback of the second input signal to obtain a second integrated signal; wherein, the feedback signal of the first output signal is obtained by quantizing and digital-to-analog converting the first integrated signal, and the feedback signal of the second output signal is obtained by quantizing and digital-to-analog converting the second integrated signal. 
         [0063]    Preferably, in the auxiliary method of a multi-path Σ-Δ modulator, the multi-path Σ-Δ modulator may correspondingly output a third output signal and a fourth output signal, and the auxiliary method further comprises: respectively sampling the first input signal and the first integrated signal during the first period of the clock cycle to obtain a third sampled signal and a fourth sampled signal, and integrating the third sampled signal, the fourth sampled signal and a feedback signal of the third output signal during a next period of the clock cycle to obtain a third integrated signal; and respectively sampling the second input signal and the second integrated signal during the second period of the clock cycle to obtain a fifth sampled signal and a sixth sampled signal, and integrating the fifth sampled signal, the six sampled signal and a feedback signal of the fourth output signal during a next period of the clock cycle to obtain a fourth integrated signal; wherein, the feedback signal of the third output signal is generated by quantizing and digital-to-analog converting the third integrated signal, and the feedback signal of the fourth output signal is generated by quantizing and digital-to-analog converting the fourth integrated signal. 
         [0064]    The foregoing clock cycle is determined by two non-overlapped clock signals generated by a clock signal generator, the two non-overlapped clock signals comprises delayed clock signals and original clock signals, and the shared op-amp has a high gain and a wider bandwidth compared to an op-amp of a multi-path Σ-Δ modulator that does not implement the op-amp sharing technique. 
         [0065]    Likewise, in order to solve the problem of crosstalk caused by sharing the op-amp, when the multi-path Σ-Δ modulator according to the present invention comprises two stages or more than two stages of integrating circuits, feed-forward gain factors may be provided to integrating circuits subsequent to the second-stage integrating circuit. Further, T-type switches may also be applied to the multi-path Σ-Δ modulator according to the present invention so as to reduce charge injected at the instant that switches are opened. 
         [0066]    In conclusion, according to a multi-path Σ-Δ modulator with a shared op-amp and an associated auxiliary method, an area of an SOC system is effectively reduced by sharing the op-amp, thus reducing production cost. Moreover, approaches of providing feed-forward gain factor a 2 , delay clock signals, T-type switches and increasing a gain and a bandwidth of the op-amp can be applied to effectively reduce crosstalk caused by sharing the op-amp. 
         [0067]    While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not to be limited to the above embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.