Abstract:
A miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from a process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

Description:
BACKGROUND OF THE PRESENT INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to surface-mount device (SMD) diode packages, and more particularly to a miniaturized SMD diode package having a circuit board used instead of a conventional lead frame, and a process for producing the same. 
         [0003]    2. Description of Related Art 
         [0004]    In a given process for making IC or semiconductor packages (or called IC devices), lead frames are conventionally used to hold IC or semiconductor dies (or called IC chips) and further make an electrical connection with the IC chips before performing package of epoxy resin and formed as IC devices. 
         [0005]    The lead frame after packaged acts as an inner electrode for the IC devices and further has pins (or contacting points) exposed outside to be worked as outer electrodes for the same IC devices. Therefore, IC device can be connected to a printed circuit board (PCB) via outer electrodes formed from so-called lead frame and to transmit workable functions from IC chips to the PCB, and vice versa. 
         [0006]    Accordingly, a lead frame is an essential element for packaging IC chips. Depending on IC chips possessing what function, usage, shape and/or size, various different lead frames are designed for use in packaging those IC chips. 
         [0007]    To take a miniaturized SMD diode package as an example, since a miniaturized diode package has a package size like chip scale, it is hardly to allow miniaturized diode chips are accurately and precisely installed on so-called lead frame. The inevitable problem is that a miniaturized diode package leads to have distortion and even failure if inaccurately packaged with lead frames for diode chips. 
         [0008]    Therefore, the conventional packaging method that uses lead frames acted as inner electrodes and also as outer electrodes for diode chips do not suitably apply for use in producing the miniaturized SMD diode package. 
       SUMMARY OF THE INVENTION 
       [0009]    In view of this, for improving the existing packaging process for miniaturized SMD diode packages, the present invention discloses a process for producing miniaturized SMD diode packages involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding. 
         [0010]    The beneficial advantages brought from the disclosed process for producing miniaturized SMD diode packages include:
   1. to simplify producing process and reduce manufacturing cost;   2. to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of the conventionally used lead frame;   3. to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect; and   4. to produce increasingly miniaturized SMD electronic devices more suitable.   
 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a schematic drawing showing a SMD diode chip package of the present invention. 
           [0016]      FIG. 2  is a schematic drawing showing another embodiment of an array-type SMD diode chip package of the present invention. 
           [0017]      FIG. 3  depicts the SMD diode chip package of  FIG. 1  or  FIG. 2  in the course of packaging process using a circuit board instead of the conventionally used lead frame to make electrical connections with one or more diodes chips. 
           [0018]      FIG. 4  is a flowchart for producing a first or second embodiment of SMD diode chip package of the present invention. 
           [0019]      FIG. 5  is an illustrating drawing to show how to produce a first embodiment of SMD diode chip package of the present invention. 
           [0020]      FIG. 6  is an illustrating drawing to show how to produce a second embodiment of SMD diode chip package of the present invention. 
           [0021]      FIG. 7  is a flowchart for producing a third or fourth embodiment of SMD diode chip package of the present invention. 
           [0022]      FIG. 8  is an illustrating drawing to show how to produce a third embodiment of SMD diode chip package of the present invention. 
           [0023]      FIG. 9  is an illustrating drawing to show how to produce a fourth embodiment of SMD diode chip package of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    Referred to  FIGS. 1 and 3 , a SMD diode chip package  10  of the present invention is herein defined as a diode package miniaturized in whole package size like chip scale and having two ends formed with outer electrodes  80   a ,  80   b  respectively. 
         [0025]    The SMD diode chip package  10  is packaged with a single diode chip  30  and has three basic features including: using a circuit board instead of the conventionally used lead frame, containing no outer pins extended from the so-called lead frame, and possessing excellent diode characteristics. 
         [0026]    The SMD diode chip package  10  of the present invention contains four embodiments described as follows. 
         [0027]    Referred to  FIGS. 1 ,  3  and  5 , formed as a first embodiment of the present invention, a diode package  10   a  is composed of a diode chip  30   a , a bottom circuit board  50 , two circuit electrodes  56   a ,  56   b , an encapsulation  75  and two outer electrodes  80   a ,  80   b.    
         [0028]    The diode chip  30   a  for having function of electrical connection has its bottom surface provided with two lower electrodes  31  acting as a positive electrode and a negative electrode, respectively. 
         [0029]    The circuit electrodes  56   a ,  56   b  are separately deposited on the bottom circuit board  50 , and each corresponds to and electrically connects to the corresponding lower electrode  31  of the diode chip  30   a , respectively. 
         [0030]    The encapsulation  75  is attached to the bottom circuit board  50  and integrated with the bottom circuit board  50  as an integrated structure, so that the diode chip  30   a  and the circuit electrodes  56   a ,  56   b  are contained therein, and the circuit electrodes  56   a ,  56   b  each have one end extended to and exposed at one end of the encapsulation  75 . 
         [0031]    The outer electrodes  80   a ,  80   b  each cover one end of the integrated structure formed by the encapsulation  75  and the bottom circuit board  50 , and each are electrically connected to the corresponding circuit electrode  56   a ,  56   b , respectively. 
         [0032]    Referred to  FIG. 6 , formed as a second embodiment of the present invention, a diode package  10   b  comprises all basic structures presented on the aforesaid diode package  10   a , and further has an upper cover  53  that is attached to a top surface of the encapsulation  75  and forms an integrated structure together with the encapsulation  75  and the bottom circuit board  50 . 
         [0033]    Accordingly, the outer electrodes  80   a ,  80   b  each cover one end of the integrated structure formed by the upper cover  53 , the encapsulation  75  and the bottom circuit board  50 , and each are electrically connected to the corresponding circuit electrode  56   a ,  56   b , respectively. 
         [0034]    Referred to  FIGS. 1 ,  3  and  8 , formed as a third embodiment of the present invention, a diode package  10   c  is composed of a diode chip  30   b  having three electrodes, a bottom circuit board  50 , two circuit electrodes  56   a ,  56   b , a top circuit board  60 , an upper circuit electrode  66   a , an encapsulation  75  and two outer electrodes  80   a ,  80   b.    
         [0035]    The diode chip  30   b  for increasing current capacity has its bottom surface provided with two lower electrodes  31  acting as a positive electrode and a negative electrode respectively, and has its top surface provided with a higher electrode  32  acting as a positive electrode or a negative electrode. 
         [0036]    The circuit electrodes  56   a ,  56   b  are separately deposited on the bottom circuit board  50 , and each corresponds to and electrically connects to the corresponding lower electrode  31  of the diode chip  30   b , respectively. 
         [0037]    The upper circuit electrode  66   a  is deposited on the top circuit board  60 , and corresponds to and electrically connects to the higher electrode  32  of the diode chip  30   b.    
         [0038]    The encapsulation  75  is attached between the bottom circuit board  50  and the top circuit board  60  as well as integrated with them as an integrated structure, so that the diode chip  30   b , the circuit electrodes  56   a ,  56   b  and the upper circuit electrode  66   a  are all contained therein, and the circuit electrodes  56   a ,  56   b  and the upper circuit electrode  66   a  each have one end extended to and exposed at one end of the encapsulation  75 . 
         [0039]    The outer electrodes  80   a ,  80   b  each cover one end of the integrated structure formed by the bottom circuit board  50 , the encapsulation  75  and the top circuit board  60 , and each are electrically connected to the corresponding circuit electrode  56   a ,  56   b  and one of them is further electrically connected to the upper circuit electrode  66   a , respectively. 
         [0040]    Referred to  FIGS. 1 ,  3  and  9 , formed as a fourth embodiment of the present invention, a diode package  10   d  is composed of a diode chip  30   c  having four electrodes, a bottom circuit board  50 , two circuit electrodes  56   a ,  56   b , a top circuit board  60 , two upper circuit electrodes  66   a ,  66   b , an encapsulation  75  and two outer electrodes  80   a ,  80   b.    
         [0041]    The diode chip  30   c  for increasing current capacity has its bottom surface provided with two lower electrodes  31  acting as a positive electrode and a negative electrode, and has its top surface provided with two higher electrode  32  acting as a positive electrode and a negative electrode, respectively. 
         [0042]    The circuit electrodes  56   a ,  56   b  are separately deposited on the bottom circuit board  50 , and each corresponds to as well as electrically connects to the corresponding lower electrode  31  of the diode chip  30   c , respectively. 
         [0043]    The upper circuit electrodes  66   a ,  66   b  are separately deposited on the top circuit board  60 , and each corresponds to as well as electrically connects to the corresponding higher electrode  32  of the diode chip  30   c , respectively. 
         [0044]    Accordingly, the outer electrodes  80   a ,  80   b  each cover one end of the integrated structure formed by the bottom circuit board  50 , the encapsulation  75  and the top circuit board  60 , and each are electrically connected to the corresponding circuit electrode  56   a ,  56   b  as well as the corresponding upper circuit electrode  66   a ,  66   b , respectively. 
         [0045]    Referred to  FIG. 2 , another alternative embodiment of the present invention is to disclose an array-type SMD diode chip package  20  (also abbreviated as diode array package  20 ) is formed from being packaged with two or more diode chips  30   a ,  30   b  or  30   c  that are separated and arranged into an array. The diode array package  20  has such an infrastructure like the aforesaid SMD diode chip package  10  has disclosed, which basic structure at least comprises a bottom circuit board  50 , an encapsulation  75  to encase two or more diode chips  30   a ,  30   b  or  30   c , and two or more pairs of outer electrodes  80   a ,  80   b  electrically connected to the corresponding diode chip  30   a ,  30   b  or  30   c , respectively. 
         [0046]    For example, a first diode array package  20  has one encapsulation  75  to encase two identical diode chips  30   a  each having two lower electrodes  31 ; the bottom circuit board  50  has deposited two pairs of circuit electrodes  56   a  and  56   b , and each pair corresponds to as well as electrically connects to the corresponding lower electrode  31  of each corresponding diode chip  30   a , respectively; and each pair of outer electrodes  80   a  and  80   b  corresponds to each corresponding diode chip  30   a  and is separately arranged on two opposite ends of the encapsulation  75  as well as electrically connects to each corresponding pair of circuit electrodes  56   a  and  56   b , respectively. 
         [0047]    Similarly, a second diode array package  20  has one encapsulation  75  to encase two identical diode chips each one is chosen from the diode chip  30   b  having three electrodes (or the diode chips  30   c  having four electrodes). The diode array package  20  further have a top circuit board  60  deposited with an upper circuit electrode  66   a  (or a pair of upper circuit electrodes  66   a  and  66   b ), and said upper circuit electrode  66   a  (or said pair of upper circuit electrodes  66   a  and  66   b ) corresponds to as well as electrically connects to the corresponding higher electrode  32  of each corresponding diode chip  30   b  (or  30   c ), respectively. And, each pair of outer electrodes  80   a  and  80   b  corresponds to each corresponding diode chip  30   b  (or  30   c ) and is separately arranged on two opposite ends of the encapsulation  75  as well as electrically connects to each corresponding pair of circuit electrodes  56   a  and  56   b , and said corresponding upper circuit electrode  66   a  (or said pair of upper circuit electrodes  66   a  and  66   b ), respectively. 
         [0048]    Referred to  FIGS. 1 ,  2  and  3 , a process for producing a miniaturized SMD diode chip package  10  or diode array package  20  of the present invention has the following specific features so different from the existing packaging process for making SMD diode packages:
   1. In the course of packaging process, a bottom circuit board  50  is used instead of the conventionally used lead frame for packaging;   2. Referred to  FIG. 3 , the bottom circuit board  50  has deposited with plural thin-film or thick-film circuits  55  that are separated and arranged into an array (hereinafter referred to as arrayed film circuits  55 ); and two arrayed film circuits  55  which are located at positions separated from and adjacent to each other on the bottom circuit board  50  is hereinafter referred to as two spaced and arrayed film circuits  56 ;   3. Process of paste dispensing is performed using CCD image registration on two ends of each arrayed film circuit  55  of the bottom circuit board  50 , so that lead-free conductive pastes  40  are accurately printed and dispensed to predetermined locations thereof; and   4. Process of chip bonding is performed using CCD image registration, so that as shown in  FIG. 3  a miniaturized diode chip  30  can have its own positive and negative electrodes already formed on its bottom surface accurately aligned with one corresponding end of two spaced and arrayed film circuits  56  of the bottom circuit board  50  respectively. More particularly, through the lead-free conductive paste  40  coated at the corresponding positions, the positive and negative electrodes of diode chip  30  due to making electrical connection with two spaced and arrayed film circuits  56  are without a risk of short circuit.   
 
         [0053]    Referred to  FIG. 4  and  FIG. 5 , the process for producing a miniaturized SMD diode package  10   a  of the first embodiment of the present invention comprises steps of:
   A 1 . prefabricating a diode chip  30   a  having a bottom surface provided with two lower electrodes  31  acting as a positive electrode and a negative electrode;   A 2 . prefabricating a bottom circuit board  50  having arrayed film circuits  55 ;   A 3 . performing paste dispensing via CCD image registration to print or dispense lead-free conductive paste  40  onto two ends of each arrayed film circuits  55  of the bottom circuit board  50 ;   A 4 . as shown in  FIG. 3 , taking every two opposite corresponding ends of two spaced and arrayed film circuits  56  of the bottom circuit board  50  as predefined connecting terminals, and performing chip bonding via CCD image registration to allow the two lower electrodes  31  of the diode chip  30   a  are securely and electrically connected to the predefined connecting terminals of the bottom circuit board  50  through the lead-free conductive paste  40 ;   A 5 . performing packaging an insulating package  70  to encase every diode chip  30   a  and every arrayed film circuit  55 , which is performed through using an insulating material packaged on the bottom circuit board  50  after chip bonding;   A 6 . defining cutting lines  73  across every arrayed film circuit  55  of the bottom circuit board  50  via CCD image registration, and making semi-finished diode packages  15   a  obtained from cutting the insulating package  70  and the bottom circuit board  50  along the cutting lines  73  to allow every arrayed film circuit  55  deposited on the bottom circuit board  50  is cut into two separate circuit electrodes, i.e., the semi-finished diode packages  15   a  is composed of the diode chip  30   a , the bottom circuit board  50 , two circuit electrodes  56   a ,  56   b  formed from cutting of the arrayed film circuit  55  and an encapsulation  75  formed from cutting of the insulating package  70 ;   A 7 . performing a coating, silver-dipping or film-making process to form outer electrodes  80   a ,  80   b  on two ends of the semi-finished diode packages  15   a , and making the outer electrodes  80   a ,  80   b  electrically connected to the corresponding circuit electrodes  56   a ,  56   b  to obtain the diode package  10   a  of the first embodiment.   
 
         [0061]    Referred to  FIG. 4  and  FIG. 6 , the process for producing a miniaturized SMD diode package  10   b  of the second embodiment of the present invention comprises steps of:
   B 1 . Same as Step A 1 ;   B 2 . Same as Step A 2 ;   B 3 . Same as Step A 3 ;   B 4 . Same as Step A 4 ;   B 5 . Same as Step A 5 ;   B 6 . coating an adhesive layer  45  on a cured surface of the insulating package  70  and covering an upper cover  53  thereon;   B 7 . Similar to Step A 6  to obtain a semi-finished diode packages  15   b  composed of the diode chip  30   a , the bottom circuit board  50 , two circuit electrodes  56   a ,  56   b  formed from cutting of the arrayed film circuit  55 , an encapsulation  75  formed from cutting of the insulating package  70  and an upper cover  53 ;   B 8 . Similar to Step A 7  to make outer electrodes  80   a ,  80   b  on two ends of semi-finished diode packages  15   b  and obtain the diode package  10   b  of the second embodiment.   
 
         [0070]    Referred to from  FIG. 7  to  FIG. 9 , the process for producing a miniaturized SMD diode package  10   c  (or  10   d ) of the third (or the fourth) embodiment of the present invention comprises steps of:
   C 1 . prefabricating a diode chip  30   b  (or  30   c ) having a bottom surface provided with two lower electrodes  31  and having a top surface provided with a higher electrode  32  (or two higher electrodes  32 );   C 2 . prefabricating a bottom circuit board  50  having arrayed film circuits  55  deposited thereon and a top circuit board  60  having arrayed film circuits  65  deposited thereon;   C 3 . performing paste dispensing via CCD image registration to print or dispense lead-free conductive paste  40  onto two ends of each arrayed film circuits  55  of the bottom circuit board  50 ;   C 4 . performing chip bonding via CCD image registration to allow the two lower electrodes  31  of the diode chip  30   b  (or  30   c ) are securely and electrically connected to predefined connecting terminals of the bottom circuit board  50  through the lead-free conductive paste  40  of Step C 3 ;   C 5 . performing paste dispensing via CCD image registration to print or dispense lead-free conductive paste  40  onto every higher electrode  32  of the diode chip  30   b  (or  30   c );   C 6 . performing covering with top circuit board  60  via CCD image registration to allow predefined connecting terminals of the top circuit board  60  accurately connected to the higher electrodes  32  of the diode chip  30   b  (or  30   c ) through the lead-free conductive paste  40  of Step C 5 ;   C 7 . performing packaging an insulating package  70  to encase every diode chip  30   b  (or  30   c ) and every arrayed film circuit  55  and  65 , which is performed through using an insulating material packaged on the space between the bottom circuit board  50  and the top circuit board  60  after chip bonding;   C 8 . defining cutting lines  73  across every arrayed film circuit  55  of the bottom circuit board  50  via CCD image registration, and making semi-finished diode packages  15   c  (or  15   d ) obtained from cutting the top circuit board  60 , the insulating package  70  and the bottom circuit board  50  along the cutting lines  73 ;   C 9 . performing a coating, silver-dipping or film-making process to form outer electrodes  80   a ,  80   b  on two ends of the semi-finished diode packages  15   c  (or  15   d ), and making the outer electrodes  80   a ,  80   b  electrically connected to the corresponding circuit electrodes  56   a ,  56   b  and  66   a  (or  56   a ,  56   b ,  66   a  and  66   b ) to obtain the diode package  10   c  (or  10   d ) of the third (or fourth) embodiment of the present invention.   
 
         [0080]    The diode chip  30  for use in making the SMD diode chip package  10  or the diode array package  20  of the present invention is preferably chosen from a transient voltage suppression diode (TVS diode), a Schottky diode, a switch diode, a Zener diode or a rectifier diode, but not limited. 
         [0081]    Accordingly, the SMD diode chip package  10  or the diode array package  20  of the present invention is preferably a TVS diode package, a Schottky diode package, a switch diode package, a Zener diode package or a rectifier diode package, but not limited. 
         [0082]    As shown in  FIG. 3 , the arrayed film circuit  55  (or  65 ) of the bottom circuit board  50  (or the top circuit board  60 ) is acted as inner electrodes for use in in making the SMD diode chip package  10  or the diode array package  20  of the present invention. 
         [0083]    The insulating package  70  or the encapsulation  75  for use in making the SMD diode chip package  10  or the diode array package  20  of the present invention is formed from a ceramic material or a plastic material, preferably formed from an epoxy resin. 
         [0084]    The bottom circuit board  50  or the top circuit board  60  for use in making the SMD diode chip package  10  or the diode array package  20  of the present invention is formed from a ceramic plate, a plastic plate, a composite sheet or a heat-dissipated plate, wherein the ceramic plate is chosen from an alumina plate or an aluminum nitride plate; the plastic plate is chosen from PE plate, PP plate, PC plate or polyamide plate; and the composite sheet is formed from carbon fiber plate or glass fiber plate. 
         [0085]    The outer electrodes  80   a ,  80   b  for use in making the SMD diode chip package  10  or the diode array package  20  of the present invention are formed from one or more lead-free conductive metals or its alloys selected from the group consisting of silver (Ag), tin (Sn), copper (Cu), gold (Au), nickel (Ni), palladium (Pd) and platinum (Pt), but not limited. 
         [0086]    The lead-free conductive paste  40  for use in making the SMD diode chip package  10  or the diode array package  20  of the present invention contains one or more lead-free conductive metals selected from the group consisting of silver (Ag), tin (Sn), copper (Cu), gold (Au), nickel (Ni), palladium (Pd) and platinum (Pt), but not limited. 
         [0087]    Due to using a circuit board instead of the conventionally used lead frame, the process for producing a miniaturized SMD diode package of the present invention helps to improve setting accuracy during packaging miniaturized diode chips, and more suitably uses for producing a diode chip package  10  shown in  FIG. 1  that has a length (L) of 0.4-1.0 mm, a width (W) of 0.2-0.5 mm and a thickness (T) of 0.2-0.5 mm, preferably producing those diode chip packages  10  with specific specification listed in Table 1. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 SMD diode chip 
                 Number 
                   
                   
                 Thick- 
               
               
                 package 
                 of Outer 
                 Length 
                 Width 
                 ness 
               
               
                 (sizes code) 
                 Electrodes 
                 (L) 
                 (W) 
                 (T) 
               
               
                   
               
             
             
               
                 Chip Scale 
                 2 
                 0.4 ± 0.1 mm 
                 0.2 ± 0.1 mm 
                 Max 
               
               
                 (01005) 
                   
                   
                   
                 0.2 mm 
               
               
                 Chip Scale 
                 2 
                 0.6 ± 0.1 mm 
                 0.3 ± 0.1 mm 
                 Max 
               
               
                 (0201) 
                   
                   
                   
                 0.3 mm 
               
               
                 Chip Scale 
                 2 
                 1.0 ± 0.1 mm 
                 0.5 ± 0.1 mm 
                 Max 
               
               
                 (0402) 
                   
                   
                   
                 0.5 mm 
               
               
                   
               
             
          
         
       
     
         [0088]    The disclosed manufacturing method is also suitable for the diode array package  20  shown in  FIG. 2  that has a length (L) of 1.0-2.4 mm a width (W) of 0.5-1.0 mm and a thickness (T) of 0.4-0.8 mm. Preferably, it is used to make the diode array package  20  with the specification listed in Table 2. 
         [0089]    The process for producing a miniaturized SMD diode package of the present invention also suitably uses for producing a diode array package  20  shown in  FIG. 2  that has a length (L) of 1.0-2.4 mm a width (W) of 0.5-1.0 mm and a thickness (T) of 0.4-0.8 mm, preferably producing those diode chip packages  10  with specific specification listed in Table 2. 
         [0000]    
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 SMD diode chip 
                 Number 
                   
                   
                 Thick- 
               
               
                 package 
                 of Outer 
                 Length 
                 Width 
                 ness 
               
               
                 (sizes code) 
                 Electrodes 
                 (L) 
                 (W) 
                 (T) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Array-type Chip 
                 ≦4 
                 1.0 ± 0.1 mm 
                 0.5 ± 0.1 mm 
                 Max 
               
               
                 Scale (0204) 
                   
                   
                   
                 0.4 mm 
               
               
                 Array-type Chip 
                 ≦6 
                 1.6 ± 0.1 mm 
                 0.8 ± 0.1 mm 
                 Max 
               
               
                 Scale (0306) 
                   
                   
                   
                 0.7 mm 
               
               
                 Array-type Chip 
                 ≦6 
                 1.3 ± 0.1 mm 
                 1.0 ± 0.1 mm 
                 Max 
               
               
                 Scale (0405) 
                   
                   
                   
                 0.8 mm 
               
               
                 Array-type Chip 
                 ≦8 
                 2.0 ± 0.2 mm 
                 1.3 ± 0.2 mm 
                 Max 
               
               
                 Scale (0508) 
                   
                   
                   
                 0.8 mm 
               
               
                 Array-type Chip 
                 ≦10 
                 2.4 ± 0.2 mm 
                 1.0 ± 0.2 mm 
                 Max 
               
               
                 Scale (0410) 
                   
                   
                   
                 0.8 mm 
               
               
                   
               
             
          
         
       
     
         [0090]    Moreover, the process for producing a miniaturized SMD diode package of the present invention due to no use of lead-containing tin paste conforms to requirements for environmental protection.