Abstract:
A power-on reset circuit input stage includes a current source charging a capacitor from a first power supply voltage to produce a reset signal, and a current shutoff means for shutting off the current source when the reset signal reaches a desired threshold voltage (i.e., when the capacitor is charged up). Beneficially, the current shutoff means comprises a transistor connected between the current source and a second power supply voltage. Advantageously, the transistor is controlled by a feedback voltage that may be the output signal, or a voltage derived from the output signal by a capacitive divider, for example.

Description:
TECHNICAL FIELD 
     This invention pertains to the field of digital circuits, and more particularly, to a power-on reset circuit for a digital circuit, and a semiconductor device including the same. 
     BACKGROUND AND SUMMARY 
     When a power supply voltage is turned on, to be supplied to a digital circuit (such as a memory circuit), there is a period of time necessary for the power supply voltage to ramp-up to its final (steady-state) value and stabilize. If the power supply voltage is applied to the digital circuit during this ramp-up period, then an unpredictable and undesired operation of the digital circuit may occur, including possible latch-up problems, etc. Such problems may not recover once the power supply voltage reaches its final value and stabilizes. 
     Accordingly, it is common to provide a power-on reset circuit for a digital circuit to provide a reset signal to the digital circuit to reset the digital circuit to a known state once the power supply voltage reaches a desired threshold voltage level. Such a power-on reset circuit typically includes a delay circuit connected to the power supply voltage to provide a delayed reset signal that will only reach a reset threshold voltage level to reset the digital circuit(s) after the power supply voltage reaches a desired power supply voltage threshold level. 
     FIG. 1 illustrates the input stage  100  of a conventional power-on reset circuit. The input stage  100  includes first and second PMOS transistors  110  and  120 , resistor  130 , and capacitor  140 . The power supply voltage is indicated as V SS  and the output signal is indicated as V OUT . The input stage  100  is followed by a second stage, typically a Schmidt trigger, to provide a power-on reset signal to the remaining digital circuits as will be described in more detail below. 
     The input stage  100  can be modeled as a current source connected in series with the capacitor  140 . The current source is established by the current mirror relationship of first and second PMOS transistors  110  and  120 . The output signal V OUT  is a ramp signal whose slope is determined by the current of the current source and the capacitance of the capacitor  140 . The V OUT  ramp signal is provided to a second stage, typically a Schmidt trigger, having a threshold to convert the V OUT  ramp signal into a V RESET  pulse signal having a sharp transition edge. 
     Because of the current mirror, a power-on reset circuit having the input stage  100  can produce a reset signal V RESET  with a much higher delay for the same values of resistor  130  and capacitor  140  compared to a power-on reset circuit whose input stage is a simple RC delay circuit. For example, if the current mirror scales down the current through the capacitor  140  by a factor of ten ( 10 ), then the resulting delay will be scaled up by about the same factor of  10  compared to an RC delay circuit having the same size capacitor. This can be especially beneficial when the power-on reset circuit having the input stage  100  is incorporated into a digital integrated circuit (IC) device where space considerations are very important. 
     Unfortunately, there are problems with the conventional power-on reset circuit having the input stage  100 . For example, once the power-on reset circuit has performed its principle function (providing a delayed reset signal upon power-up), there remains a DC static current through the circuit by means of the current through the current mirror transistor  110  and the resistor  130 . As a result, the power-on reset circuit will needlessly consume and waste power even in its “standby” mode of operation. 
     One solution to the above-mentioned problem has been disclosed in U.S. Pat. No. 6,052,006. However, the disclosed solution requires more than five additional transistors to stop the current flow through the power-on reset circuit once the circuit has performed its principle function. 
     Accordingly, it would be desirable to provide an improved power-on reset circuit, and in particular, a power-on reset circuit having an improved input stage. It would also be desirable to provide a power-on reset circuit that consumes very little, if any, power in a standby mode. It would be further desirable to provide a power-on reset circuit that eliminates static DC current flow through the circuit during a standby mode. It would be still further desirable to provide a power-on reset circuit that includes a less complicated means of eliminating static DC current flow through the circuit during a standby mode. The present invention is directed to addressing one or more of the preceding concerns. 
     In one aspect of the invention, a power-on reset circuit comprises a current mirror connected to a first power supply voltage, a capacitor receiving current from the current mirror, and current shutoff means connected between the current mirror and a second power supply voltage, the current shutoff means being adapted to shut off the current received by the first capacitor when a voltage across the capacitor reaches a threshold voltage level. 
     In another aspect of the invention, a semiconductor device includes a digital circuit having a reset input and power-on reset circuit providing a reset signal to the reset input, the power-on reset circuit comprising a current mirror connected to a first power supply voltage, a first capacitor receiving current from the current mirror, and current shutoff means connected between the current mirror and a second power supply voltage, the current shutoff means being adapted to shut off the current received by the first capacitor when a voltage across the capacitor reaches a threshold voltage level. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows an input stage of a conventional power-on reset circuit. 
     FIG. 2 shows a first embodiment of an input stage of a power-on reset circuit according to one or more aspects of the invention. 
     FIG. 3 shows the circuit of FIG. 2 connected to an input of a second stage of the power-on reset circuit. 
     FIG. 4 shows a second embodiment of an input stage of a power-on reset circuit according to one or more aspects of the invention. 
     FIG. 5 shows a third embodiment of an input stage of a power-on reset circuit according to one or more aspects of the invention. 
     FIG. 6 shows a fourth embodiment of an input stage of a power-on reset circuit according to one or more aspects of the invention. 
     FIG. 7 shows a fifth embodiment of an input stage of a power-on reset circuit according to one or more aspects of the invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 shows a first embodiment of an input stage  200  of a power-on reset circuit according to one or more aspects of the invention. The power-on reset circuit input stage  200  includes: a current mirror comprising first and second PMOS transistors  210  and  220 , resistor  230 , capacitor  240 , and current shutoff means comprising a third PMOS transistor  250 . The power supply voltage is indicated as V SS  and the output signal is indicated as V OUT . Although the exemplary power-on reset circuit input stage  200  is shown being connected between the power supply voltage V SS  and a ground voltage, more generally the power-on reset circuit input stage  200  could be thought off as being connected between first and second power supply voltages or terminals. The input stage  200  of the power-on reset circuit is followed by a second stage, typically a Schmidt trigger, to provide a power-on reset signal to the remaining digital circuits as will be described in more detail below. 
     Beneficially, the power-on reset circuit input stage  200  is included in a semiconductor device having a digital integrated circuit, such as a memory device. 
     An explanation of the operation of a power-on reset circuit including the first embodiment input stage  200  will now be provided. A current source comprising the current mirror and the resistor  230  supplies current to charge a voltage across the capacitor  240 , which voltage is the output voltage V OUT  supplied by the power-on reset circuit input stage  200 . When the output voltage charges up to a threshold voltage level, the current shutoff means comprising the third PMOS transistor  250  is activated to thereby shut off the current source supplying current to the capacitor  240 , as the power-on reset circuit enters the standby mode. 
     More specifically, the power-on reset circuit input stage  200  receives the power supply voltage V SS  from the power supply, and provides a ramp output signal V OUT  to a second stage of the power-on reset circuit. Upon Power-up, the power supply voltage V SS  begins to ramp up to its final value (e.g., 3 volts); At this point, the transistor  220  starts to turn on, thereby turning on the transistor  210  and the transistor  250 . Current flows through the series path comprising transistors  210  and  250  and resistor  230 . Through the current mirror a reduced current also flows through the series combination of the transistor  220  and capacitor  240 , charging the voltage on the capacitor  240 , which is V OUT . The voltage V OUT  is provided to the second stage, typically a Schmidt trigger, having a threshold to convert the V OUT  ramp signal into a V RESET  pulse, signal having a sharp transition edge. 
     As the voltage V OUT  charges up (ramps up), feedback begins to turn off the transistor  250 . When the capacitor  240  is almost completely charged to its final value, the current source goes into sub-threshold conduction. When the capacitor  240  is completely charged, the transistor  250  blocks the DC current path through the transistor  210  and resistor  230 . Also beneficially, the transistor  250  drains some of the current through the transistor  220  at start-up, increasing the threshold of the power supply voltage level at which the capacitor  240  starts to charge. This provides for either a longer delay, or the ability to use a slightly smaller capacitor  240  (less area). 
     FIG. 3 shows the input stage  200  of a power-on reset circuit connected to an input of a second stage  300 , such as a Schmidt trigger circuit, for converting the ramp-like VOUT signal to a pulse-like reset signal for resetting digital circuits. The input of the second stage  300  includes a PMOS transistor  310  connected in series with an NMOS transistor  320 . In this case, it can be seen that the voltage across the capacitor  240 , V OUT , does not completely charge up to the supply voltage V SS . As a result of this, a voltage drop occurs across the gate and source of the PMOS transistor  310  of the digital circuit  300 , causing a current to flow through the PMOS transistor  310  while the power-on reset circuit is in the standby mode. 
     Accordingly, to address this drawback, a second embodiment power-on reset circuit input stage  400  shown in FIG. 4 includes a series combination of two capacitors  442  and  444 . The feedback voltage to the current shutoff means comprising the third PMOS transistor  450 , V FDBK , is based on the voltage charged onto capacitor  442 , while the output voltage V OUT  is based on the voltage across the series combination of capacitors  442  and  444 . Advantageously, in the power-on reset circuit  400 , the output voltage V OUT  gets almost completely charged before the feedback voltage V FDBK  turns off the current source. This ensures that the PMOS transistor  310 , for example, of a second stage of the power-on reset circuit is not left conducting when the power-on reset circuit is in the standby mode. 
     In the power-on reset circuit input stage  400 , the two capacitors  442  and  444  are connected in series so as to reduce the total capacitance into which the current through transistor  420  charges. In order to achieve the same power-on reset delay as for the power-on reset circuit including the input stage  200 , each of the capacitors  442  and  444  will need to be larger than the capacitor  240  of power-on reset circuit input stage  200 . Disadvantageously, these larger capacitors occupy a greater area in an integrated circuit, requiring a greater area for the power-on reset circuit input stage  400  compared with the power-on reset circuit input stage  200  to achieve the same power-on reset delay. 
     Accordingly, to address this drawback, a third embodiment power-on reset circuit input stage  500  shown in FIG. 5 includes a series combination of two capacitors  543  and  545  together in parallel with the capacitor  540 . In similarity to FIG. 4, the feedback voltage to the current shutoff means comprising the third PMOS transistor  550 , V FDBK , is based on the voltage charged onto capacitor  543 , while the output voltage V OUT  is provided by the voltage across the series combination of capacitors  543  and  545 . Advantageously, in the power-on reset circuit input stage  500 , the output voltage V OUT  gets almost completely charged before the feedback voltage V FDBK  turns off the current source. This ensures that the PMOS transistor  310 , for example, of a second stage of the power-on reset circuit is not left conducting when the power-on reset circuit is in the standby mode. Also advantageously, the capacitors  543  and  545  can be very small compared with the capacitor  540 , leaving the delay and the total area required for the power-on reset circuit largely unaffected. 
     Alternatively, in a fourth embodiment power-on reset circuit input stage  600  shown in FIG. 6, instead of the capacitor  545 , an NMOS transistor  660  is used to provide the feedback voltage V FDBK  to the current shutoff means comprising the third PMOS transistor  650 . As in the second and third embodiments, in the fourth embodiment power-on reset circuit input stage  600 , the output voltage V OUT  gets almost completely charged before the feedback voltage V FDBK  turns off the current source. Also, since the capacitor  670  can be very small, the overall area of the circuit is almost unaffected. 
     FIG. 7 shows a fifth embodiment power-on reset circuit input stage  700 . The fifth embodiment power-on reset circuit input stage  700  is similar to the fourth embodiment power-on reset circuit input stage  600 , except the NMOS transistor  660  is replaced by a diode-connected fourth PMOS transistor  780 , taking its charge from the capacitor  740  instead of the first power supply. This eliminates the effect of any differences between the threshold voltages of the NMOS and PMOS transistors in FIG. 6, and effectively adds the capacitance of the smaller capacitor  770  to that of the larger capacitor  740 , allowing the size of capacitor  740  to be correspondingly reduced, or increasing the delay of the power-on reset circuit  700 . 
     While preferred embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention. Such variations would become clear to one of ordinary skill in the art after inspection of the specification, drawings and claims herein. The invention therefore is not to be restricted except within the spirit and scope of the appended claims.