Abstract:
A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to a process-insensitive delay line used to accommodate inherent differences in devices due to fabrication inconsistencies. 
       BACKGROUND OF THE INVENTION 
       [0002]    Delay lines are typically incorporated into electronic devices to accommodate inherent differences in electronic components due to fabrication imperfections. A conventional delay line typically utilizes the input to output delay of one or more invertors arranged in series to accommodate the inherent differences of electronic components. The number and type of invertors used is determined by the required delay time. However, the overall delay time resulting from the one or more serial invertors is subject to process and/or environmental variations such as process corners (i.e., process variations arising during fabrication), changes in temperature during operation and power supply fluctuations. When variations in the process and environmental factors are aggregated together, the resulting delay time may vary from the expected delay time by as much as fifty percent. Faced with such inconsistencies, circuit and device designers are forced to over-design their circuits or devices, with respect to the original specifications, to accommodate the resulting overall delays experienced. 
         [0003]    For example, in a high-speed pipe line analog-to-digital converter (ADC) with a clock frequency of 25 Megahertz (MHz), the duration of a clock pulse is 20 nanoseconds (nS). Of this 20 nS, 4 nS is typically allocated to the non-overlapping time of the non-overlapping clock (thereby allowing time for the comparator to settle), 2 nS is typically allocated to a slew-rate limiting period of the operational amplifier (opamp) settling time, 1 nS is typically allocated to the bottom-plate sampling edge, leaving only 12 nS for a bandwidth limiting period of the opamp settling time. If a conventional delay line is used to control the 4 nS non-overlapping time of the non-overlapping clock, the actual delay time can vary between approximately 2.5 nS to 6 nS. In this case the designer would be forced to over design the comparator to ensure that the comparator is capable of settling within 2.5 nS in the worst case, and would have to over design the opamp to ensure that the opamp can settle within 10 nS (rather than the 12 nS) in light of the uncertainty of the non-overlapping time. 
         [0004]    As a second example,  FIG. 1  depicts a pixel-array readout scheme  100  that is well understood by one of ordinary skill in the art. For example, and without limitation, the pixel-array readout scheme of  FIG. 1  includes one hundred columns  105 . The pixel array is read out row-by-row. Each time a row is read, the voltage values from the pixel array are stored in capacitors  110  located in sampling columns. In order to read the voltage values stored in the sampling columns, the sampling columns (cs) are connected to the readout circuitry column by column through column select switches  115 . The column select switches  115  are controlled by the column address. The charges stored in the capacitors  110  are then “crow-bared” out to the readout circuitry through crow-bar (cb) switches  120 . 
         [0005]      FIG. 2  illustrates a desired timing relationship between the sampling columns (cs) and the crow-bar (cb) switches. The time t 1  is typically used to reset the first stage of the readout circuitry. The time t 2  is reserves as a time margin to ensure the current crow-bar is completed prior to any column address change. Typically, cs 1 -cs 100  and cb 1 -cb 100  are derived from a column address and a crow-bar clock. In this case, the falling edge of cb is typically, for example, several nanoseconds ahead of the falling edge of cs. The falling edge of cs is controlled by a delay line in a clock generation block. In light of power supply voltage variations, process variations and environmental temperature variations, a design margin must be include to ensure cb falls before the column address changes. However, including this design margin reduces the available time for t 1  resulting in a reduced reset time for the first stage of the readout circuitry. This reduced reset time may manifest itself in column-wise fixed pattern noise. 
         [0006]    A need exists to reduce or eliminate uncertainties in delay times caused by process and environmental variations. A further need exists to accurately predict the resulting delay times for circuits or devices added to overcome inherent differences due to device fabrication. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  depicts a pixel-array readout scheme; 
           [0008]      FIG. 2  illustrates a timing relationship between the sampling columns and the crow-bar switches of  FIG. 1 , 
           [0009]      FIG. 3  depicts a block diagram of a desired embodiment of a process-insensitive delay line.; 
           [0010]      FIG. 4  depicts an exemplary design of the phase detector  110  of  FIG. 3 ; 
           [0011]      FIG. 5  depicts an exemplary design of the voltage-controlled delay-unit  130  of  FIG. 3 , and 
           [0012]      FIG. 6  illustrates an application of the controllable delay line in the clock generation block of an imager. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]    In a desired embodiment, a process-insensitive delay line is continuously adjustable and is used to reduce or eliminate delay time uncertainties due to process and/or environmental variations. In the desired embodiment, the delay time of the process-insensitive delay line is controlled by the ratio of a charging current (I charge ) and a control current (I control ). The charging current and the control current typically come from a digitally controlled current source (IDAC), in which the control current is adjustable by a multi-bit digital code. For example, and without limitations, the process-insensitive delay line may be used in a CMOS imager to improve performance with a sample and hold circuit having a continuously-adjustable accurate crow-bar delay control to reduce column-wise fixed noise pattern (FPN), and to improve a continuously-adjustable accurate non-overlapping time control for an analog to dicitral converter (ADC). 
         [0014]      FIG. 3  depicts a block diagram of a desired embodiment of a process-insensitive delay line  300 . Process-insensitive delay line  300  includes an input signal terminal  305 , a phase detector  310 , a charge current (I charge ) source  315 , a control current source (I control )  320 , a voltage-control node (V control )  325 , a voltage-controlled delay-unit  330 , a two position switch  340 , a capacitor  345 , and an output terminal  335 . The output from output terminal  335  of the voltage-controlled delay-unit  330  is a delayed version of the signal received at the input terminal  305 . The delay time resulting from  FIG. 3  is controlled by the voltage level at voltage-control node  325 . As the voltage level at voltage-control node  325  increases, the resulting delay time decreases. 
         [0015]    The phase detector  310  compares the phase difference between the input signal IN and the output signal OUT and produces a pulse (K) that corresponds to the time difference of the rising edges of the input IN and output OUT signals. The pulse produced by phase detector  310  is used to configure the two position switch  340  such that the charge current source  315  is connected to the voltage-control node  325 . When no delay is required, phase detector  310  does not pulse the two position switch  340  and the charge current source  315  is not connected to the voltage-control node  325 . However, during a desired delay period of the output of the process-insensitive delay line  300 , phase detector  310  pulses two position switch  340  such that charge current source  315  is connected to voltage-control node  325 . In this configuration, charge current source  315  attempts to increase the charge on voltage-control node  325 . Simultaneously, control current source  320  extracts charges from voltage-control node  325  during the entire clock cycle. At equilibrium, there is no net charge being received by voltage-control node  325  and there is no net charge being dissipated from voltage-control node  325 . At equilibrium the following equation is satisfied: I charge *t delay =I control  *t clk  where I charge  is the charge added during 1 clock period from charge current source  315 , I control  is the charge dissipated during one clock period, t delay  is the delay time and t clk  is the clock time in nanoseconds (clock pulse). Rearranging the equation results in: t delay =(I control /I charge )*t clk , while the absolute values of both I charge  and I control  are affected by process and/or environmental variations, since both I charge  and I control  come from the same IDAC, the ratio of I control /I charge  remains unaffected by process and/or environmental variations. Based on the design of the IDAC, the ratio I control /I charge  is controlled by a multi-bit digital code. 
         [0016]    For example, and without limitation, in one of the possible IDAC designs, the charging current source  315  is designed to be 16 microamps (μA), while the control current source  320  is adjustable through a 6-bit digital code between 0 μA and 16 μA linearly. For example, if a digital code of 000100 (binary) is selected, then the control current source  320  is 1.016 μA. Assuming a clock frequency of 25 MHz, the corresponding delay time is expected to be: 
         [0000]        t   delay =( I   control   /I   charge )* t   clk    
         [0000]        t   delay =1.016  μA/ 16  μA* 40 nS 
         [0000]        t   delay =0.0635*40 nS=2.54 nS 
         [0017]    When process and/or environmental variations occur, the absolute values of both I control  and I charge  change, but the ratio of the two currents is only determined by the multi-bit digital code and remains at 0.0635, which ensures the delay time is still 2.54 nS. Similarly, a digital code of 001000 would result in a t delay  of 5.08 nS and a digital code of 010000 would result in a t delay  of 10.16 nS. 
         [0018]    In a desired embodiment, voltage-controlled delay unit  330  has two inputs, one of which is connected to the voltage-control node  325  and the second of which is connected to receive the input signal IN. When a delay is required, the input connected to the voltage-control node  325  is determined by the net effect of integration of the charge current source  315  and the control current source  320  on the capacitor  345 . 
         [0019]      FIG. 4  depicts one exemplary phase detector which may be used as phase detector  310  of  FIG. 3 . The illustrated embodiment of the phased detector  310  of  FIG. 4  includes two input terminals  405  and  415 , an inverter  410 , a NAND gate  420  and an output terminal  425 . The phased detector  310  compares the phase difference between the input (received at terminal  415 ) and the output signal (received at terminal  405 ), and outputs a pulse, at output terminal  425 , that corresponds to the time difference of the rising edges of the received input and output signals. 
         [0020]      FIG. 5  depicts one exemplary voltage-controlled delay-unit which may be used as delay-unit  330  of  FIG. 3 . In the illustrated embodiment, the voltage-controlled delay-unit  330  includes two input terminals  505  and  510 , a node  515 , three transistors  520 ,  525  and  530 , an inverter  540  and an output terminal  545 . The voltage-controlled delay unit  330  receives V control  at terminal  505 , input at terminal  510  and produces an output signal at terminal  545 . 
         [0021]    The process-insensitive delay line  300  may be utilized within many applications such as in a CMOS imager as described above and in other applications such as DRAM applications, and may also be characterized as an analog delay lock loop, or a charge pump. 
         [0022]      FIG. 6  illustrates the use of the controllable delay line  610  in the clock generation block  615  of an imager  620 . As illustrated, when the controllable delay line  610  is used in the generation block  615  the imager  620  can better tolerate power supply voltage variations, process variations, and environmental temperature variations. As described, the falling edge of the crow-bar can be more accurately controlled, allowing more time to reset the first stage of the readout circuitry to potentially improve the performance of the readout circuitry.