Abstract:
Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photoresist layer as a mask, c) sequentially depositing a gate oxide layer and a gate polysilicon layer on an entire surface of the silicon substrate and defining the gate using the photoresist layer, d) etching the resulting silicon substrate using the photoresist layer as a mask to form the gate and forming an N −  ion region by means of ion implantation, and e) depositing and etching back an oxide layer to form a sidewall oxide layer and forming an N +  ion region by means of ion implantation. Consequently, the gate is made by etching the silicon substrate. Thus, a length of the gate is reduced, so that it is possible not only to make a cell area smaller but also to prevent a short-channel effect.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is a divisional of U.S. patent application Ser. No. 10/977,036, filed on Oct. 28, 2004, now pending, which claims priority from Korean Patent Application No. 2003-83785, filed on Nov. 24, 2003, the disclosures of which are incorporated herein by reference in their entirety. 

   BACKGROUND 
   1. Technical Field 
   The present invention relates to semiconductor devices and to a method of manufacturing the same, and more particularly, to transistors and to a method of manufacturing the same. 
   2. Discussion of the Related Art 
   MOS field effect transistors (hereinafter, referred to as MOS transistors) are widely used in semiconductor devices. High speed devices such as static random access memories and dynamic random access memories (DRAM) generally include MOS transistors. In order to improve the speed of such devices, it is desirable to increase the drive current passing through the channel of the MOS transistors in the devices. 
   The amount of drive current that can pass through the channel of a MOS transistor is proportional to the channel width and inversely proportional to the channel length. In general, when the size of the cells in a semiconductor memory is reduced, the size of the MOS transistor inside the cell is reduced. When the size of the transistor is reduced, the channel length of the MOS transistor is also reduced. This reduction can help improve the drive current. However, a reduction of the channel length can also have negative effects such as a hot carrier effect. In order to avoid such negative effects, it is desirable to improve the drive current capability of MOS transistors by an increase in the channel width. 
     FIG. 1  is a sectional view illustrating a conventional MOS transistor taken along the direction of channel width.  FIG. 1  shows a typical MOS transistor having a flat-shaped active region  100 . If the channel width W is extended with a flat-shape, the drive current of the MOS transistor can be improved. However, the amount of space used by the MOS transistor is increased. Such an increase is not helpful with respect to the high-integration of the semiconductor device. It is noted that the reference numeral “ 102 ,” refers to the gate electrode of the device. 
   A MOS transistor having a trench in an active region, and a method of fabricating the same are disclosed in US Patent Publication No. 2003-0085434. According to the US Patent Publication No. 2003-0085434, an isolation layer defining an active region is disposed inside a semiconductor substrate. The active region has at least one trench displaced across a gate electrode. Such a MOS transistor has an effective channel width that extends as long as the length of both sidewalls of the trench. However, when manufacturing a MOS transistor by the method disclosed in the US Patent Publication No. 2003-0085434, an additional photolithography process is necessary to form the trench. Thus, the processes become more complicated. Further, limitations in pattern resolution of the photolithography process makes it more difficult to achieve high integration. 
   SUMMARY OF THE INVENTION 
   One object of the present invention is to provide a transistor having a high effective channel width in order to improve the operation speed of a transistor. 
   Another object of the present invention is to provide a method of manufacturing a transistor, which is simplified and which does not require an additional photolithography process, thus, reducing production costs. 
   The present invention provides a transistor having an active region with mesa structure. The transistor includes an isolation layer disposed on a semiconductor substrate to define an active region. A pair of source/drain regions are disposed in the active region. The source/drain regions are spaced apart from each other, and a channel region is interposed between the source/drain regions. The active region has a mesa disposed across the channel region, which extends to the source/drain regions. A gate electrode is disposed to cross over the active region along the direction which is across the mesa. Thus, the transistor has a high effective channel width. 
   The present invention also provides a method of fabricating a transistor such as that described as above. The method includes forming an isolation trench defining an active region in a semiconductor substrate. An isolation hard mask pattern remains on the active region. The isolation hard mask pattern is isotropically etched to expose a boundary portion of the active region. This forms a mesa hard mask pattern on a central portion of the active region, and concurrently forms an extended opening defined by the mesa hard mask pattern. A buried insulating layer is formed to fill the isolation trench and the extended opening. Then, by removing the buried insulating layer of the extended opening, the boundary portion of the active region is exposed. Concurrently, a buried insulating layer pattern inside the isolation trench is formed. The exposed boundary portion of the active region is anisotropically etched using the buried insulating layer pattern and the mesa hard mask pattern as etch masks. This forms a mesa in the active region. The mesa hard mask pattern and the upper portion of the buried insulating layer pattern are removed. A gate electrode is formed to cross over the active region along the direction across the mesa. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which: 
       FIG. 1  is a sectional view illustrating a conventional MOS transistor taken along a direction of channel width; 
       FIG. 2  is a top plan view of a MOS transistor according to one embodiment of the present invention; 
       FIG. 3  is a sectional view illustrating the MOS transistor according to one embodiment of the present invention taken along the line I-I′ of  FIG. 2 ; and 
       FIGS. 4 to 11  are sectional views illustrating a method of fabricating the MOS transistor according to one embodiment of the present invention taken along the line I-I′ of  FIG. 2 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification. 
     FIG. 2  is a top plan view of a MOS transistor according to one embodiment of the present invention, and  FIG. 3  is a sectional view taken along line I-I′ of  FIG. 2 . 
   Referring to  FIGS. 2 and 3 , an isolation layer  512   c  is disposed in a semiconductor substrate  500 . The isolation layer  512   c  may be, for example, a HDP oxide layer. An active region  504  is defined by the isolation layer  512   c . Further, sequentially from the surface of the semiconductor substrate  500 , a sidewall oxide layer  514  and a liner insulating layer  516  may be interposed between the semiconductor substrate  500  and the isolation layer  512   c . The sidewall oxide layer  514  may be a thermal oxide layer. The liner insulating layer  516  may be a silicon nitride layer. A pair of source/drain regions  504   b  may be disposed in the active region  504 , with spaced apart from each other. Further, a channel region  504   a  is disposed between a pair of the source/drain regions  504   b . A mesa  518  is disposed across the channel region  504   a  with straight extended to the source/drain regions  504   b . As such, the channel region  504   a  has a protrusion structure, which includes a top surface of the mesa  518 , sidewalls b 1 , b 2  of the mesa  518 , and surfaces c 1 , c 2  of the active region on both sides of the mesa  518 . A gate electrode  522  is disposed to cross over the channel region  504   a  along the direction across the mesa  518 . The gate electrode  522  may be formed of polysilicon. A gate insulating layer  520  is interposed at least between the semiconductor substrate of the active region  504  and the gate electrode  522 . The gate insulating layer  520  may be a thermal oxide layer. 
   As described above, in one exemplary embodiment of the present invention, the channel region  504   a  of the MOS transistor may include a mesa  518 , which is disposed along the direction across the gate electrode  522 . As a result, the MOS transistor of the present invention may have an effective channel width corresponding to a width of the top surface a of the mesa  518 , a height of the sidewalls b 1 , b 2  of the mesa  518 , and a width of the surfaces c 1 , c 2  of active region on both side of the mesa  518 . That is, the MOS transistor of the present invention has an effective channel width that includes height of the sidewalls b 1 , b 2  of the mesa  518 . This is in comparison to a conventional MOS transistor that has a flat active region. 
     FIGS. 4 to 11  are sectional views illustrating a method of fabricating the MOS transistor according to one embodiment of the present invention.  FIGS. 4 to 11  are taken along the line I-I′ of  FIG. 2 . 
   Referring to  FIGS. 2 and 4 , a hard mask layer is formed on the whole surface of a semiconductor substrate  500 . Preferably, before the hard mask layer is formed, a pad oxide layer may be formed on the whole surface of the semiconductor substrate  500 . The hard mask layer may be a silicon nitride layer. The pad oxide layer may be a thermal oxide layer. Then, a photoresist pattern  502  is formed on the hard mask layer with openings at predetermined positions in the hard mask layer. The hard mask layer is anisotropically etched using the photoresist pattern  502  as an etch mask, and the semiconductor substrate  500  is anisotropically etched, so as to form an isolation trench  506  defining an active region  504  in the semiconductor substrate  500 . An isolation hard mask pattern  508  is formed and non-etched. It remains on the active region  504 . The isolation trench  506  preferably has a depth of at least 4000 Å. 
   Referring to  FIGS. 2 and 5 , the photoresist pattern  502  is removed. Then, an isotropic etch is performed on the isolation hard mask pattern  508  remaining on the active region  504 . The isotropic etch may be a wet etch using, for example, phosphoric acid as an etching solution. The isotropic etch is performed until the isolation hard mask pattern  508  is reduced in size to have an appropriate width. As a result, the isolation hard mask pattern  508  on the boundary region of the active region  504  (hereinafter, referred to as boundary portion P) is removed, so as to expose a boundary portion P. Further, there a mesa hard mask pattern  508 ′ is formed and it remains on the central portion of the active region  504  defined by the exposed boundary portion P. The mesa hard mask pattern  508 ′ is the pattern to which the isolation hard mask pattern  508  is reduced by the isotropic etch. Further, over the isolation trench  506 , an extended opening  510  is defined by the mesa hard mask pattern  508 .′ 
   Referring to  FIGS. 2 and 6 , an insulating layer  512  is formed to fill the isolation trench  506  and the extended opening  510  on the whole surface of the semiconductor substrate that has the mesa hard mask pattern  510 . The insulating layer  512  may be formed of a HDP oxide layer. Preferably, before the insulating layer  512  is formed, a sidewall oxide layer  514  and a liner insulating layer  516  may be formed conformally and sequentially at least on the inner surface of the isolation trench  506  and on the boundary portion P. The sidewall oxide layer  514  is formed to cure any etch damage on the semiconductor substrate  500  due to high energy of ions during etching of the isolation trench  506 . The sidewall oxide layer  514  may be a thermal oxide layer. The liner insulating layer  516  is formed to prevent further oxidization of the semiconductor substrate  500  around the isolation trench  506  by a following thermal process. The liner insulating layer  516  may be a silicon nitride layer. 
   Referring to  FIGS. 2 and 7 , the insulating layer  512  is planarized to expose the mesa hard mask pattern  508 ′ or the liner insulating layer  514  on the mesa hard mask pattern  508 .′ As a result, there is a buried insulating layer  512   a  filling the isolation trench  506  and the extended opening  510 . The planarization of the insulating layer  512  can be performed by using CMP process. 
   Referring to  FIGS. 2 and 8 , the buried insulating layer  512   a  of the extended opening  510  is removed to expose the boundary portion P. At the same time, a buried insulating layer pattern  512   b  is formed on the inside the isolation trench  506 . The buried insulating layer  512   a  inside the extended opening  510  can be removed through a selective wet etch using an etching solution having a high selectivity with respect to the silicon oxide layer. As described above, if the sidewall oxide layer  514  and the liner insulating layer  516  are formed on the boundary portion P, after the buried insulating layer  512   a  on the extended opening  510  is removed, additional wet etch is performed to sequentially remove the sidewall oxide layer  514  and the liner insulating layer  516  in the boundary portion P. Further, the liner insulating layer  516  on the mesa hard mask pattern  508 ′ can be also removed. 
   Referring to  FIGS. 2 and 9 , after exposing the boundary portion P, by using the mesa hard mask pattern  508 ′ and the buried insulating layer pattern  512   b  as etch masks, the boundary portion P is isotropically etched and made recessed. As a result, mesa  518  is formed in the active region  504 . During the process, an upper side of the buried insulating layer pattern  512   b  can be partially recessed. Further, as described above, in the case where the sidewall oxide layer  514  and the liner insulating layer  516  are formed, upper portions of the sidewall oxide layer  514  and the liner insulating layer  516  may be exposed over the surface of the semiconductor substrate in the recessed boundary portion P. 
   Referring to  FIGS. 2 and 10 , after the mesa  518  is formed, the mesa hard mask pattern  508 ′ is removed. Further, the buried insulating layer pattern  512   b  is recessed to form an isolation layer  512   c  on the inside of the isolation trench  506 . In this embodiment of the present invention the mesa hard mask pattern  508 ′ may be a silicon nitride layer, and the buried insulating layer pattern  512   a  may be a silicon oxide layer by HDP. Thus, the removal of the mesa hard mask pattern  508 ′ and the recess of the upper portion of the buried insulating layer pattern  512   b  can be performed by wet etch using separate etching solutions. 
   However, by using an etching solution having an appropriate selectivity with respect to the silicon nitride layer and the silicon oxide layer, the removal of the mesa hard mask pattern  508 ′ and the recess of the buried insulating layer pattern  512   b  can be performed at the same time. 
   Further, in the case where the sidewall oxide layer  514  and the liner insulating layer  516  are formed, the upper portions of the sidewall oxide layer  514  and the liner insulating layer  516 , which are exposed over the surface of the semiconductor substrate in the recessed boundary portion P, are also etched during the process. Further, the buried insulating layer pattern  512   b  is preferably recessed to an extent that a tilt ion implantation process is possible on the sidewall of the mesa  518  during a following impurity ion implantation process used to control the threshold voltage. 
   Referring to  FIGS. 2 and 11 , after the mesa hard mask pattern  508 ′ is removed, and an isolation layer  512   c  is formed inside the isolation trench  506 , an impurity ion implantation process for controlling a threshold voltage is performed in a normal manner. Then, a gate insulating layer  520  is formed on the active region  504 . The gate insulating layer  520  may be a thermal oxide layer. A conformal conductive layer is formed on the whole surface of the semiconductor substrate  500  having the gate insulating layer  520 . The conductive layer may be a polysilicon layer. Then, by patterning the conductive layer, a gate electrode  522  is formed across the active region  504 . The gate electrode  522  is formed to cross over the active region  504  along the direction across the mesa  518 . As a result, the MOS transistor has a channel width corresponding to a width of the top surface of the mesa  518 , a height of the sidewalls of the mesa  518 , and a width of the surfaces of the active region on both side of the mesa. 
   Then, impurity ions are implanted into the semiconductor substrate by using the gate  25  electrode  522  as an ion implantation mask, so as to form source/drain regions  504   b  inside the active region adjacent to both sides of the gate electrode  522 . Further, a channel region  504   a  is defined. The channel region  504   a  is interposed between the source/drain regions  504   b  and overlapping the gate electrode  522 . 
   Therefore, in accordance with the present invention, a channel width is increased by the mesa disposed in the active region of the transistor. As a result, there can be an increase in the drive current passing the channel of the transistor, and also, the operation speed of the transistor is increased. Further, this can be done without any additional photolithography process. The production cost is reduced, and the resulting transistor effectively has an extended channel width produced by a simple processes. 
   While the invention has been shown and described with respect to preferred embodiments thereof, it should be understood that various other changes in form and detail may be made without departing from the spirit and scope of the invention. The scope of the invention is defined and limited only by the appended claims.