Abstract:
A circuit and method for providing a fast transitioning output buffer that may be configured to operate using either a 3 volt or 5 volt supply voltage. The pullup behaves similarly to a MOS diode, but the circuit lowers the gate voltage on a pullup while the output is being pulled up. The circuit does not affect the final pullup voltage. As a result, a single PMOS device may be used as a pullup device that does not generally require an increased size to support a high operating voltage.

Description:
This is a continuation of U.S. Ser. No. 08/939,196, filed Sep. 29, 1997, now U.S. Pat. No. 6,066,963, issued May 23, 2000 and Ser. No. 09/451,958, filed Nov. 30, 1999, now U.S. Pat. No. 6,246,263, issued Jun. 12, 2001. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to output drivers generally and, more particularly, to an output driver using MOS technology that is configured to operate using either a 3 volt or 5 volt supply voltage. 
     BACKGROUND OF THE INVENTION 
     For integrated circuits operating at a relatively high supply voltage (e.g., a TTL voltage such as 5 volts), it is advantageous to have an NMOS output pullup driver. The NMOS output driver reduces system power by not pulling the output all the way up to the supply voltage. Integrated circuits operating with a relatively low supply voltage (e.g., 3 volts) typically use CMOS voltage levels and are therefore generally required to pull their outputs up to voltages near the supply. This is usually accomplished using a PMOS pullup transistor. 
     It is desirable to have a single part that can be programmed using fuses, or some other type of step late in the fabrication process, to configure the part to operate using either 5 volt or 3 volt supply voltages. One implementation may be realized by providing two independent pullup sections. The first pullup would be an NMOS pullup while the second pullup would be a PMOS pullup. The late configuration would configure the appropriate pullup for the desired voltage operation. However, this would require the output section to generally duplicate the pullups which would result in a larger chip. 
     Implementing a single pullup device for use with both 3 volt and 5 volt input supply voltages may reduce the overall die size. One alternative to such an implementation would be using an NMOS pullup with a boot strapped gate. Another implementation may be a PMOS pullup with an additional circuit to turn off the PMOS pullup after the output has been pulled up to the desired voltage. One way of implementing the PMOS pullup approach is to connect the pullup as a diode for 5V operation. However, the size of the PMOS pullup is generally (and usually undesirably) determined by the larger 5 volt part rater than the smaller 3 volt part. 
     SUMMARY OF THE INVENTION 
     The present invention concerns a circuit and method for providing a fast transitioning output buffer configured for low voltage operation (e.g., a 3 volt supply voltage) with the same output devices as for a high voltage operation (e.g., a 5 volt supply voltage). In one embodiment, the circuit lowers the gate voltage on a P-channel pullup while the output is being pulled up. In another embodiment, the circuit raises the gate voltage on an N-channel pulldown as the output is pulled down. As a result, MOS devices configured for low voltage operation (e.g., 3 volt) may be used as pullup and pulldown devices in a relatively high operating voltage environment (e.g., 5 volts) in the absence of devices configured to operate at the high voltage (e.g., having an increased size relative to a device configured for 3 volt operation). 
     The objects, features and advantages of the present invention include providing a 5V output driver that uses the same PMOS pullup and NMOS pulldown as a 3V output driver, does not require a larger PMOS device to support the 5 volt operation, provides a fast output transition and has a reduced final pullup voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a circuit diagram of a preferred embodiment of the present invention; 
     FIG. 2 is a timing diagram of the various nodes of the circuit of FIG. 1; 
     FIG. 3 is a circuit diagram of an alternate embodiment of the present invention; and 
     FIG. 4 is a circuit diagram of another alternate embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a diagram of a circuit  10  for providing an output driver using a PMOS technology pullup driver transistor that operates using a 5 volt supply voltage is shown in accordance with a preferred embodiment of the present invention. Another example of an output driver that operates using either a 3 volt or 5 volt supply voltage may be found in U.S. application Ser. No. 08/635,022, filed on Apr. 14, 1996, which is hereby incorporated by reference in its entirety. The circuit  10  generally comprises a transistor Q 1 , a transistor Q 2 , a transistor Q 3 , a transistor Q 4 , a transistor Q 5 , a transistor Q 6 , a transistor Q 7 , an inverter I 1  and an inverter I 2 . The circuit  10  generally has a pullup input PU, a pulldown input PD and an output OUT. The inverter I 2 , the transistor Q 2  and the transistor Q 3  generally form an enable/disable section (or circuit)  12 . The transistor Q 4 , the transistor Q 5 , the transistor Q 6  and the inverter I 1  generally form an output transition time-decreasing section (or circuit)  14 . A disable circuit comprising the transistor Q 3  may be configured in parallel with the output transition time-decreasing circuit  14 . 
     The pullup input PU may be presented to a gate of the transistor Q 3 , a gate of the transistor Q 5  and to the inverter,I 2 . The source of the transistors Q 1  and Q 3  are generally connected to an input supply voltage (not shown). The drain of the transistor Q 3  may be connected to the gate of the transistor Q 1 , the source of the transistor Q 2  and the drain of the transistor Q 4 . The drain of the transistor Q 3  is shown generally as a node N 1 . The output of the inverter I 2  may be presented to the gate of the transistor Q 2  and is shown generally as a node N 2 . The sources and drains of each of the transistors may be referred to generally as terminals. The inverter I 2  may be implemented directly after the pullup input PU (e.g., outside the disable circuit  12 ), if a complementary pullup input (e.g., PUB) is used. 
     The drain of the transistors Q 1  and Q 2  are generally coupled together with the source of the transistor Q 5  and the drain of the transistor Q 7  to create the output OUT. A source of the transistor Q 6  is also coupled to the input supply voltage. A gate of the transistor Q 6  is generally coupled to ground. The supply voltage and ground may be referred to generally as power busses. The drain of the transistor Q 6  as well as the source of the transistor Q 5  are shown generally as a node N 4  that may be presented to the inverter I 1 . The output of the inverter I 1  is generally shown as a node N 3  that may be presented to the gate of the transistor Q 4 . The source of the transistor Q 4  is generally coupled to ground. The pulldown input PD is generally coupled to the gate of the transistor Q 7  while the source of the transistor Q 7  is generally coupled to ground. The transistor Q 1  is shown generally as a PMOS type device while the transistor Q 4  is shown generally as a NMOS type device. PMOS devices and NMOS devices may be considered to be complementary type devices. 
     The operation of the circuit  10  can be described generally as either pulling the output OUT to a high state, pulling the output OUT to a low state, or not pulling the output OUT to either state (i.e., a three-state or high impedance state) in response to the pullup input PU and the pulldown input PD. When the output OUT is pulled to a high state, the transistor Q 1  is generally configured as a diode having a gate and drain shorted by the transistor Q 2 . When the output OUT is pulled low by the transistor Q 7 , the transistor Q 1  is generally held in an off state by the transistor Q 3 . When the output OUT is pulled high, the transistors Q 4 , Q 5 , Q 6  and the inverter I 1  generally speed up the pullup transition by decreasing the voltage present at the gate of the transistor Q 1 . 
     When the output OUT is to be pulled from low to high, the pullup input PU is generally taken high, which turns off the transistor Q 3 , turns on the transistor Q 2  and turns on the transistor Q 5 . When the transistor Q 2  is on, the node N 1  is generally pulled down to a voltage equal to the ground voltage plus a P-channel threshold. The transistor Q 5  generally pulls the node N 4  down to a voltage below the threshold voltage of the inverter I 1 . The transistor Q 6  is generally configured as a weak device which allows the transistor Q 5  to pull the node N 4  below the threshold of the inverter I 1 . Next, the node N 3  rises which generally turns “on” the transistor Q 4  which generally pulls the node N 1  down to the ground voltage. This generally causes the transistor Q 2  to turn off and remain off until the output OUT has risen to a voltage equal to the ground voltage plus a P-channel threshold. As the output OUT is pulled above the P-channel threshold, the transistor Q 2  starts to turn on which increases the voltage on the node N 1 . 
     The ratio of the drive strengths of the transistors Q 2  and Q 4  may be adjusted to insure that the increase in the voltage at the node N 1  is a slight voltage increase. As the output OUT is pulled up, the transistor Q 5  starts to turn off. The ratio of the drive strengths of the transistors Q 5  and Q 6  as well as the threshold voltage of the inverter I 1  create a threshold voltage. Once the threshold voltage is reached, the voltage at the node N 3  will begin to fall, which generally turns off the transistor Q 4 . The voltage at the node N 1  rises up to the voltage at the output OUT. As a result, the transistor Q 1  is configured as a diode and the output OUT will be pulled up to a voltage equal to the input supply voltage minus a P-channel threshold. 
     Referring to FIG. 2, a timing diagram of the node N 1 , the node N 3  and the output OUT is shown. The voltages are shown as generally ranging between a zero voltage level and a supply voltage VCC. The node N 1  initially starts at a voltage near the supply voltage VCC. At a time T 1 , the node N 3  begins to rise. At a time T 2  the node N 3  reaches a maximum voltage that is generally slightly less than the supply voltage VCC. After the time T 2 , the node N 3  begins to fall until it reaches a zero voltage at the time T 4 . At or near the time T 1 , the output OUT begins to gradually rise. At the time T 3 , the node N 1  begins to gradually rise. 
     The transistor Q 4  generally pulls the gate of the transistor Q 1  down during the initial states of pullup of the output OUT. This gives the transistor Q 1  a sufficient drive for a 5 volt operation without the requirement of increasing the size of the transistor Q 1  beyond what may be required for a 3 volt operation. The transistors Q 5  and Q 6 , and the inverters I 1  and I 2 , generally control the gate of the transistor Q 4 . The transistor Q 4  is generally only on during the beginning of the pullup (i.e., up to time T 4 ). Once the output OUT has risen sufficiently, the transistor Q 4  is generally turned off and allows the transistor Q 1  to act as a diode. The transistor Q 4  is generally not left on after the time T 4  to avoid overshoot on the output OUT. Conversely, if the transistor Q 4  turns off too soon, then the drive generally required for a 5 volt operation will not be present. 
     At the start of a pullup transition, the signal PU is taken high, the transistor Q 3  turns off and the transistor Q 5  turns on. The output of inverter I 2  falls, which turns on the transistor Q 2  and generally pulls the node N 1  down to the output OUT. If there is a very large load at the output OUT, the node N 1  will get pulled down to a P-channel threshold above ground which generally provides a slight pullup on the output OUT by transistor Q 1 . As the output OUT rises, the node N 1  will rise until the output rises to the supply voltage minus the P-channel threshold when the transistor Q 1  generally starts turning off. The transistor Q 1  starts turning off as the node N 1  approaches VCC. 
     As the pullup input PU rises, the transistor Q 5  generally turns on. This generally pulls the node N 4  down. The weak load on the node N 4  from the transistor Q 6  will generally start delivering load current into the output OUT. The current from the node N 4  is generally small compared with the main load current, but is generally transitioning in the correct direction for proper operation of the circuit  10 . The current from the node N 4  is generally pulling the output OUT up. After the transistor Q 5  has turned on, the node N 4  will generally start to fall. Once it reaches the threshold of the inverter I 1  the node N 3  will generally rise and it will generally turn on the transistor Q 4 . Generally, the transistors Q 4  and Q 2  turn on at about the same time. The transistor Q 4  is generally a small device. The output OUT initially responds to the transistor Q 2  pulling node N 1  down. A capacitance on the node N 1  is generally realized due to the gate capacitance of the transistor Q 1 . The transistor Q 2  generally pulls the node N 1  down until the transistor Q 2  starts turning off because as the node N 1  approaches a P-channel threshold above ground (e.g., a P-channel threshold voltage), but the transistor Q 4  continues to pull the node N 1  low. If the output capacitance is large, then transistor Q 4  will generally pull the node N 1  all the way to ground, insuring maximum drive from the transistor Q 1 . 
     The transistor Q 2  is generally larger than the transistor Q 4 . In one embodiment, the transistor Q 2  is generally about  5  times as large as the transistor Q 4 . As the output rises, the transistor Q 2  turns on more. Once the output has risen to the extent that the transistor Q 4  is off, the transistor Q 1  generally functions as a diode. When the transistor Q 4  is off, it generally does not influence the output OUT. Generally, the transistor Q 4  is a speed up device while the output OUT is low. 
     A bleed device may be implemented on the node N 1  to help pull the node N 1  up to VCC. The bleed device may help eliminate noise on the node N 1  that may cause OUT to be pulled up by the transistor Q 1 . However, the circuit  10  may operate adequately without such a bleed device. 
     Referring to FIG. 3, a circuit  10 ′ is shown in accordance with an alternate embodiment of the present invention. The transistors Q 1 , Q 2 , Q 3  and Q 6  are implemented as PMOS transistors while the transistors Q 4 , Q 5  and Q 7  are implemented as NMOS transistors. The transistor Q 6  is generally configured as a leaker (or load) device, which precharges the node N 4  to a voltage that deactivates the transistor Q 4  when the transistor Q 5  is inactive (i.e., not conducting). A conventional resistive device may replace the transistor Q 6 . Preferably, the resistivity of transistor Q 6  is selected such that the charge on the node N 4  is substantially discharged through the transistor Q 5  in response to an active pullup control signal PUB. The alternative circuit  10 ′ provides a similar operation as the circuit  10  shown in FIG.  1 . Furthermore, one may independently select active low or active high pullup input signals for the enabling circuit  30  and the output transition time-decreasing circuit  40 , then match the polarity of the circuit to the active logic level of the input control signal. 
     Referring to FIG. 4, a circuit  10 ″ is shown in accordance with a preferred embodiment of the present invention. The transistors Q 2 ′, Q 3 ′, Q 4 ′, Q 5 ′, Q 6 ′ and Q 7 ′ are shown coupled to the pulldown transistor Q 7 . As a result, a complementary operation to the circuit  10  and the circuit  10 ′ is generally implemented. The transistors Q 4 ′, Q 5 ′ and Q 7 ′ are shown implemented as PMOS devices, while the transistors Q 1 ′, Q 2 ′, Q 3 ′ and Q 6 ′ are shown implemented as NMOS devices. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.