Abstract:
A system for testing circuit boards comprising a probe network having a plurality of probes wherein each probe is adapted for contacting an end of a corresponding circuit board network and wherein each probe and network define a node having an address. The system further comprises a control device that includes a node address generator and a timing circuit having an output for outputting a pulse to the node having the address generated by the node address generator and for coupling the remaining nodes to electrical ground. The system further comprises a comparator for comparing the pulse outputted by the timing circuit to predetermined data.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to detecting defects in circuit boards or integrated circuit chip carriers. 
     2. Problem to be Solved 
     Circuit boards and integrated circuit (IC) chip carriers, such as single chip module (SCM), multi-chip module (MCM) and hybrid chip carriers are typically used for mounting and interconnecting electronic components in most electronic equipment. Such circuit boards or IC chip carriers usually include metal interconnections, voltage planes, a ground plane and dielectric materials such as ceramic, glass ceramic, silicon-oxide, polymer and/or epoxy glass. The circuit boards also include a plurality of interconnection networks (&#34;nets&#34;). Each net may be distributed either across a single layer or across multiple layers within the circuit board. 
     As packaging density in such boards continues to increase, the metal interconnections which comprise each interconnection network are decreasing in size and are being spaced closer together. Such continual miniaturization of the metal interconnections within the circuit boards or chip carriers results in an increase in the probability of a variety of defects. For example, the points of a conductor network that should be connected together may have one (or more) discontinuities in the conductor path(s). This results in an &#34;open circuit&#34; condition having substantially infinite resistance between certain sections of the network. A further defect occurs when two independent conductor networks or conductor areas that are supposed to have no electrical connection and therefore substantially infinite internet resistance, in fact display an unacceptable, low value of internet resistance. This is commonly referred to as a &#34;short circuit&#34;. In addition, a conductive pathway may be defective because it displays one or more sections having resistances which exceed an acceptable level. This defect is referred to as a &#34;resistive fault&#34;. In a properly manufactured high-density passive board, the resistance between terminals of a common conductor network is normally in the range of from a few milliohms to many ohms. This resistance is dependent on the length and cross-section of the conductors. Furthermore, the resistance between independent networks should approach infinity. This resistance typically exceeds 100 megohms. 
     A necessary step in the manufacture of high-density substrates, chip carriers, and passive boards is to test the proper continuity and isolation of all nets before any electronic components are mounted. Continuity testing measures relatively low resistance within particular networks. Open circuits and resistive faults are thus typical defects which are found in continuity testing. Isolation testing measures the expected high resistance levels that should exist between conductors. Short circuits are typical defects which are found when conducting isolation testing. 
     A common continuity and isolation test method uses cluster probes which match and contact test pads on the substrate surface. By controlling the switching matrix, resistance from a network under test to all other networks in the substrate can be measured. This is a relatively fast testing method, however, it lacks flexibility. Substrates with different designs usually require different cluster probes or &#34;bed-of-nail&#34; fixtures. In addition, complexity and long lead-time to produce custom cluster probes make this technique costly especially for early manufacturing where product design may not be finalized. 
     Another isolation test is the so called point-to-point or single probe testing wherein two moving probes are used on an X-Y positioning mechanism. This flexible probing method can perform individual tests between all possible pairs of nets. In this method, testing of passive substrates is accomplished by using moving probes in a series of two-point resistance measurements. In this manner, the continuity of individual nets may be verified. This method allows a series of one-point measurements to be made to determine the capacitance of a network relative to a reference plane or indicate short-circuits between nets through excessive internet capacitance. While this approach has great flexibility, it suffers from several severe practical difficulties which limit its effectiveness and speed. These include a need for switching between resistance and capacitive test modes, lengthy cycle times, difficulty of detecting a low-capacitance net shorted to a high-capacitance net when testing the high capacitance net, and an inability to distinguish between a high-resistance short to a net and a leakage path directly to ground. Furthermore, this method relies on simple scalar matching of capacitance values during the defect isolation process. In this manner, the continuity of nets which display excessive capacitance is checked against a potentially long list of other nets showing similar capacitance. 
     Bearing in mind the problems and deficiencies of conventional processes and systems for testing circuit boards, it is an object of the present invention to provide a new and improved system for testing the integrity of circuit boards. 
     It is another object of the present invention to provide a new and improved system for identifying defects in circuit boards that requires relatively fewer components than conventional testing systems. 
     It is a further object of the present invention to provide a new and improved system for testing the integrity of interconnection networks on circuit boards or unpopulated chip carriers in relatively less time than conventional testing systems. 
     Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification. 
     SUMMARY OF THE INVENTION 
     The above and other objects, which will be apparent to those skilled in the art, will be achieved in the present invention which is directed to, in a first aspect, a system for testing circuit boards, comprising: 
     a probe network having a plurality of probes, each probe adapted for contacting an end of a corresponding circuit board network, each probe and network defining a node having an address; and 
     a control device including, 
     a node address generator, 
     a timing circuit having an output for outputting a pulse to the node having the address generated by the node address generator and coupling the remaining nodes to electrical ground; and 
     a comparator for comparing the pulse to predetermined data. 
     In a related aspect, the present invention is directed to a system for testing circuit boards, comprising: 
     a probe network having a plurality of probes, each probe adapted for contacting an end of a corresponding circuit board network, each probe and network defining a node having an address; and 
     a control device including, 
     a node address generator, 
     a plurality of timing circuits, each timing circuit corresponding to one of the nodes, each timing circuit having an enable signal input and an output coupled to a corresponding one of the nodes, each timing circuit outputting a pulse upon receipt of the enable signal and coupling the corresponding nodes to ground potential when no enable signal is received; 
     a plurality of address decoders, each decoder corresponding to one of the timing circuits and having an input for receiving the node addresses generated by the node address generator, each decoder having a predetermined address stored therein that is the same as the node address of the node to which the output of the corresponding timing circuit is coupled, each decoder outputting an enable signal when the decoder receives a node address from the node address generator that is the same as the predetermined address; 
     a comparator for comparing the pulse to predetermined data; and 
     a data storage device for storing the predetermined data. 
     In a further aspect, the present invention is directed to a system for testing circuit boards, comprising: 
     a probe network having a plurality of probes, each probe adapted for contacting an end of a corresponding circuit board network, each probe and network defining a node having an address; and 
     a control device including, 
     a node address generator, 
     a plurality of timing circuits, each timing circuit corresponding to one of the nodes, each timing circuit having an enable signal input and an output coupled to a corresponding one of the nodes, each timing circuit outputting a pulse upon receipt of the enable signal and coupling the corresponding node to ground potential when no enable signal is received; 
     a plurality of address decoders, each decoder corresponding to one of the timing circuits and having an input for receiving the node addresses generated by the node address generator, each decoder having a predetermined address stored therein that is the same as the node address of the node to which the output of the corresponding timing circuit is coupled, each decoder outputting an enable signal when the decoder receives a node address from the node address generator that is the same as the predetermined address; 
     a plurality of resistors, each resistor being coupled between a power source and the output of a corresponding timing circuit, the pulse width of the pulse outputted by each timing circuit being determined by the product of the resistance of the corresponding resistor and a capacitance of the network forming the node that is coupled to the output of the corresponding timing circuit; 
     a data storage device for storing predetermined pulse data; and 
     a comparator for comparing the pulse to the predetermined pulse data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the invention are believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. the invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a perspective view of an unpopulated high-density circuit board. 
     FIG. 2 is a block diagram of the testing system of the present invention. 
     FIG. 3 is a schematic diagram of the system of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In describing the preferred embodiment of the present invention, reference will be made herein to FIGS. 1-3 of the drawings in which like numerals refer to like features of the invention. 
     FIG. 1 shows an exemplary board used for electronic component packaging. Circuit board 4 is a multi-layer circuit board that is unpopulated, i.e. electrical components have not yet been placed on the board. Circuit board 4 comprises power plane 6, ground plane 8 and interconnection networks (&#34;nets&#34;) NET1 and NET2. Each net may be distributed either across a single layer or across multiple layers within the circuit board. Although FIG. 1 shows only two (2) nets, it is to be understood that circuit board 4 has many nets and that the simplicity of circuit board 4, as shown in FIG. 1, facilitates description of the system of the present invention. 
     FIG. 2 shows a block diagram of testing system 10 of the present invention. System 10 comprises computer or microprocessor 12, circuit 14, probe network 16 and circuit board 4 that is to be tested. Probe network 16 is a cluster-type probe network comprising a plurality of individual probes P 1  -P N  wherein each individual probe corresponds to a net of circuit board 4. For example, if circuit board 4 has N nets, then probe network 16 has N probes. Probe P N  contacts the Nth net of circuit board 4. Thus, all nets are contacted simultaneously by probes P 1  -P N . Circuit 14 outputs test signals S 1  -S N  which are inputted into probe network 16. Each test signal S 1  -S N  corresponds to an individual probe P 1  -P N , respectively. Circuit 14 receives data from computer 12 over data bus 18 which identifies the particular net of board 4 that is to be tested. Circuit 14 outputs data to bus 20 which pertains to the test signals S 1  -S N . The data on bus 20 is inputted into computer 12. Computer 12 compares the data received from circuit 14 with stored reference data. This comparison function determines whether a circuit board is defective. A monitor (not shown) may be used with computer 12 to allow the user to quickly ascertain whether a circuit board is defective. System 10 will now be discussed in detail. 
     Referring to FIG. 3, circuit 14 comprises address decoders 22a-n, timer circuits 24a-n, logic AND gates 26a-n, resistors 28a-n and counter circuit 30. Computer 12 outputs data to circuit 14 via data bus 18. Data bus 18 comprises gating signal 18a, address data 18b, counter-enable signal 18c and system clock 18d. Gating signal 18a and address data 18b are inputted into every address decoder 22a-n. Enable signal 18c and system clock signal 18d are inputted into counter 30. Probe network 16 defines a plurality of nodes designated by Nodes 1-N. Each node corresponds to a particular probe of probe network 16. For example, Node 1 corresponds to probe P 1 , Node 2 corresponds to probe P 2  and Node N corresponds to probe P N . 
     In the ensuing discussion, particular signals are referred to as having logic &#34;1&#34; or logic &#34;0&#34; levels. Although, certain functions of system 10 are implemented when a particular signal has a stated logic level, it is to be understood that simple modifications may be made so the functions of system 10 can be implemented when the particular signals have logic levels that are opposite to the stated logic levels. 
     Referring to FIG. 3, each node has a corresponding node address that is decoded by a corresponding address decoder. For example, the address for Node 1 is decoded by address decoder 22a. Similarly, the address for Node N is decoded by address decoder 22n. Each address decoder 22a-n simultaneously receives gating signal 18a and address data 18b from computer 12. Each address decoder 22a-n contains a pre-programmed node address and compares the incoming address data 18b to this preprogrammed node address. If address data 18b matches the preprogrammed node address and gating signal 18a has a logic &#34;1&#34; level, each address decoder 22a-n outputs a logic &#34;1&#34; trigger signal 32a-n, respectively. If address data 18b does not match the preprogrammed node address, each address decoder 22a-n outputs a logic &#34;0&#34; gating signal. In a preferred embodiment, computer 12 is programmed with software that generates node addresses sequentially. Thus, only one address decoder 22a-n at a time outputs a logic &#34;1 &#34; trigger signal 32a-n. Each of the remaining decoders outputs a trigger signal having a logic level that disables the corresponding timer circuit. When a timer circuit is disabled, the node corresponding to that timer circuit is coupled through the timer circuit to electrical ground. 
     Each timer circuit 24a-n has a trigger input 34a-n, discharge terminal 36a-n, external capacitor terminal 38a-n and output 40a-n, respectively. In a preferred embodiment, each timer-circuit is a CMOS type timer. Each discharge terminal and external capacitor terminal are coupled to a corresponding node. For example, discharge terminal 36a and external capacitor terminal 38a are coupled to Node 1. Each resistor 28a-n is coupled between the supply voltage V CC  and a node. In a preferred embodiment, V CC  is about 15 volts d.c. and each resistor has a resistance between about 100 KΩ and 2MΩ ohms. The actual resistance of each resistor 28a-n depends on the size of the circuit board being tested and the number of nodes and probes utilized in system 10. Each resistor 28a-n is coupled to NET1-N, respectively, through probes P 1-N , respectively. The capacitance of each net C NET1-N  and resistors 28a-n, respectively, form a plurality of R/C (resistor/capacitor) timing circuits. Since each discharge terminal 36a-n and external capacitor terminal 38a-n of each timer 24a-n, respectively is coupled to a Node 1-N, respectively, each R/C timing circuit becomes the R/C timing circuit for a corresponding timer circuit 24a. When each trigger input 34a-n of timer circuits 24a-n, respectively, receives a trigger signal 32a-n, respectively, a pulse 27 is outputted at output terminals 40a-n, respectively. 
     The presence and duration of the pulse outputted at output terminals 40a-n of each timer circuit 24a-n, respectively, depends upon the R/C time constant of each R/C timing circuit. Specifically, the pulse width of each pulse outputted at outputs 40a-n is proportional to the net capacitance C NET1-N , respectively. The pulses outputted at output terminals 40a-n are inputted into AND gates 26a-n, respectively. Trigger signals 32a-n are also inputted into AND gates 26a-n, respectively. Thus, when trigger signals 32a-n have a logic &#34;1&#34; level, the pulses outputted at terminals 40a-n, are gated into input 31 of counter circuit 30. The function of counter 30 will be discussed in detail below. 
     As stated above, the width of each pulse outputted at output terminals 40a-n of timers 24a-n is proportional to the capacitance of each net, i.e. C NET1-N , respectively. Thus, the pulse width of each pulse outputted at the timer circuit output terminals 40a-n determines whether the net under test has an open circuit or a short circuit. Counter 30 digitizes the incoming pulse into an m-bit word. The m-bit word is transferred to computer 12 via data bus 20 when counter 30 is enabled by computer 12 via counter-enable signal 18c. Computer 12 compares the digitized pulse width to predetermined data stored therein. The predetermined data may consists of engineered data, e.g. pulse width data based on circuit board design characteristics or data based on tests performed on circuit boards having no defects. System 10 can also generate the predetermined data by a &#34;self learn&#34; process on a &#34;golden part&#34;, i.e. a circuit board or card having known defects or no defects. Predetermined tolerances may be incorporated into the predetermined data stored in computer 12. Table I below illustrates the characteristics of the width of the pulse outputted from the timer circuits and the corresponding circuit board condition. 
     
                       TABLE I______________________________________Pulse Width         Circuit Board Condition______________________________________1.  Reference Value ± Tolerance                   Good Network                   (Single end contacted)2.  Pulse Appears When No                   Open Node In A Multi-    Pulse Should Be Present                   Point Contacted Net3.  No Pulse Appears When A                   Short/Leakage To A    Pulse Should Be Present                   Contacted Net4.  Pulse Width &gt; Reference Value                   Short To A Non Contacted                   &#34;to&#34; Net5.  Pulse Width &lt; Reference Value                   Open In A Single Node                   Contacted Net6.  Pulse Width &lt; Open Probe Value                   Probe Wire Discontinuity______________________________________ 
    
     Theory of Operation 
     The first step in testing the integrity of a circuit board is to attach probe network 16 to the circuit board such that one probe contacts one end of a net. The appropriate software program is then chosen for testing the circuit board. Preferably, the program allows the user to input data in order to tailor the integrity test to specific requirements. For purposes of this discussion, it is assumed that a software program is chosen that implements a normal integrity test, i.e. every net of the circuit board is tested. Preferably, the software program also contains the information in Table I shown above. Next, the electronic circuit supply voltages are then activated. The user then initiates the test via a key board or other control that is connected to computer 12. The software program generates sequentially the addresses of Nodes 1-N and outputs the addresses over address bus 18b. Each decoder 22a has a corresponding node address stored therein. When an address on data bus 18b matches the address stored in a particular decoder, that decoder outputs a trigger signal (trigger signals 32a-n in FIG. 3) that is inputted into the trigger input (trigger inputs 34a-n in FIG. 3) of the corresponding timer circuit. The remaining decoders do not output a trigger signal thereby disabling the remaining timer circuits. All unaddressed nodes are coupled to electrical ground to form a reference plane for the tested net. The trigger signal outputted from the decoder is also inputted into the AND gate (AND gates 26a-n in FIG. 3). Each timer circuit 24a-n, upon receiving a trigger signal from a corresponding decoder, outputs a pulse (output terminals 40a-n) that is inputted into the corresponding AND gate along with the trigger signal. Thus, the output pulse of the timer circuit is gated into counter circuit 30. Counter circuit 30 measures the pulse width and digitizes the pulse width into an m-bit word. The m-bit is then transferred to computer 12 via data bus 20. Computer 12 compares the digitized pulse width to the stored reference data of Table I. 
     Thus, system 10 of the present invention provides significant advantages over the conventional test systems discussed above. Specifically, system 10 utilizes fewer probes than the conventional cluster probe or &#34;bed of nails&#34; system since system 10 requires that only one end of the net under test be contacted by a probe. Furthermore, the probe network 16 does not have to be reconfigured to test circuit boards of varying designs. It is apparent that system 10 costs significantly less to fabricate and maintain. System 10 also offers significant advantages over the conventional serial probe test system discussed above. The test speed of the conventional serial probe test system is severally limited due to the mechanical movements of the test probe. Typically, the test speed of the conventional serial probe test system is about 100 tests/minute. On the other hand, system 10 of the present invention implements tests at electronic speeds of about 50 μs/test. 
     System 10 of the present invention provides leakage detection capability that is significantly improved over conventional test systems, especially the conventional &#34;capacitance only&#34; testing. System 10 also provides a resistive continuity test if all net points are contacted. The typical accuracy of the timer circuits 24a-n, about ±2%, is adequate for implementing non-parametric &#34;go/no-go&#34; shorts and continuity tests. The low component count required by system 10, as compared to conventional test matrices, allows the front end circuits to be mounted in close proximity to the test probe. This reduces the interface problems of physically small test probes with large test matrices. 
     While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention. 
     Thus, having described the invention, what is claimed is: