Abstract:
A semiconductor device includes a plurality of logic cells formed on a semiconductor substrate, wherein each of the plurality of logic cells has a circuit for a function block of a logic circuit; and a wiring layer which connects the plurality of logic cells to form the logic circuit function blocks and thereby the logic circuit. The wiring layer includes a power supply wiring line pattern formed in a region corresponding to each of the plurality of logic cells; a ground wiring line pattern formed in the region; and a plurality of terminal patterns formed in the region. Each of the plurality of terminal patterns is connected with the circuit of the logic cell, and the plurality of terminal patterns are arranged adjacent to at least one of the power supply wiring line pattern and the ground wiring line pattern.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor device and a manufacturing method for the same. 
   2. Description of the Related Art 
   Conventionally, a logic cell array is known. In the logic cell array, a plurality of cells are arranged in an array in a lower layer, and a wiring layer is formed on the lower layer to connect the plurality of cells and thereby to form a logic circuit. Thus, a semiconductor device can be manufactured to have a desired function. In one of such logic cell arrays, logic cells having functional blocks such as a multiplexer, a flip-flop, and an inverter are arranged. 
   For example, in Japanese Laid Open Patent application (JP-P2001-523048A corresponding to WO99/25023) is disclosed ASIC wiring architecture, in which various IC devices are mutually connected to form a customized circuit.  FIG. 1  is a logic notation showing a circuit of a logic cell disclosed in that conventional example. The logic cell is composed of a 4-input and 1-output multiplexer. The multiplexer has four data input terminals D 0 , D 1 , D 2  and D 3 , two selection terminals S 0  and S 1  and one output terminal P. 
     FIG. 2  shows the arrangement of each terminal of the logic cell. Each of the terminals D 0 , D 1 , D 2 , D 3 , S 0 , S 1  and P is composed of a pair of terminals (vias), between which a power supply wiring line pattern VDD and a ground wiring line pattern GND are put. Each pair of terminals is provided in parallel to the power supply wiring line pattern VDD and the ground wiring line pattern GND, and the terminals of each pair have the same potential. 
   In the above-described conventional logic cell, some of the input terminals D 0 , D 1 , D 2 , D 3 , S 1  and S 2  are connected with the power supply wiring line pattern VDD or the ground wiring line pattern GND in order to realize a desired logical function. For this reason, the two terminals with the same potential are provided on either side of the power supply wiring line pattern VDD and the ground wiring line pattern GND, as described above. Two horizontal tracks are occupied irrespective of the use/non-use of the terminals in the logic cell. 
   Also, the logic cell has only the terminals necessary to realize a multiplexer function. Therefore, the logic circuit to be realized using the multiplexer is limited. 
   Moreover, the positions for the terminals to be arranged are not especially considered. For this reason, it is required to provide a bypass wiring line pattern except for a case to apply the same potential to the adjacent input terminals. Therefore, the wiring line pattern to form the logic cell for a desired logical function becomes complicated. As a result, the wiring line area between the logic cells is restricted and causes the deterioration of the electric characteristic and the workability of wiring line through the bypassing of the wiring line. 
   SUMMARY OF THE INVENTION 
   Therefore, an object of the present invention is to provide a semiconductor device in which wiring workability and electric characteristic of a semiconductor chip can be improved, and a manufacturing method for the same. 
   In an aspect of the present invention, a semiconductor device includes a plurality of logic cells formed on a semiconductor substrate, wherein each of the plurality of logic cells has a circuit for a function block of a logic circuit; and a wiring layer which connects the plurality of logic cells to form the logic circuit function blocks and thereby the logic circuit. The wiring layer includes a power supply wiring line pattern formed in a region corresponding to each of the plurality of logic cells; a ground wiring line pattern formed in the region; and a plurality of terminal patterns formed in the region. Each of the plurality of terminal patterns is connected with the circuit of the logic cell, and the plurality of terminal patterns are arranged adjacent to at least one of the power supply wiring line pattern and the ground wiring line pattern. 
   Here, the plurality of terminal patterns may include signal input terminal patterns, one or more of which are selectively opened depending on the logic circuit function block to be formed. The wiring layer further may include a pattern connecting each of remaining ones of the signal input terminal patterns to one of the power supply wiring line pattern, the ground wiring line pattern and another of the remaining signal input terminal patterns, depending on the logic circuit function block to be formed. 
   Also, ones of the plurality of terminal patterns to be connected each other depending on the logic circuit function block to be formed may be arranged adjacent to each other. 
   Also, ones of the plurality of terminal patterns to be connected with the power supply wiring line pattern depending on the logic circuit function block to be formed may be arranged adjacent to the power supply wiring line pattern. 
   Also, ones of the plurality of terminals to be connected with the ground wiring line pattern depending on the logic circuit function block to be formed may be arranged adjacent to the ground wiring line pattern. 
   Also, the logic cell may have a multi-purpose circuit as the circuit. In this case, the multi-purpose circuit may include first to third inverters and first and second transfer gates. In the first inverter, an input is connected with a first terminal pattern of the plurality of terminal patterns, and an output is connected with a second terminal pattern of the plurality of terminal patterns. In the second inverter, an input is connected with a third terminal pattern of the plurality of terminal patterns and an output is connected with a fourth terminal pattern of the plurality of terminal patterns. In the third inverter, an input is connected with a fifth terminal pattern of the plurality of terminal patterns. In the first transfer gate, an input is connected with the output of the first inverter, a first control terminal is connected with the input of the third inverter and a second control terminal is connected to an output of the third inverter. In the second transfer gate, an input is connected with the output of the second inverter, a first control terminal is connected with the output of the third inverter and a second control terminal is connected to the input of the third inverter. An output of the first transfer gate and an output of the second transfer gate are connected to a sixth terminal pattern of the plurality of terminal patterns. 
   In this case, the power supply wiring line pattern may include a first power supply wiring line pattern and a second power supply wiring line pattern. The first terminal and the fourth terminal may be arranged between the first power supply wiring line pattern and the ground wiring line pattern, the second terminal and the third terminal may be arranged between the ground wiring line pattern and the second power supply wiring line pattern, and the fifth terminal and the sixth terminal may be arranged between the second power supply wiring line pattern and an edge portion of the region. 
   In this case, a NAND circuit may be formed in which the first terminal pattern is connected with the ground wiring line pattern, and the second terminal pattern and the fourth terminal pattern have no connection such that the third terminal pattern and the fifth terminal pattern are set as inputs and the sixth terminal pattern is set as an output. 
   Also, a NOR circuit may be formed in which the third terminal pattern is connected with the second power supply wiring line pattern, and the second terminal pattern and the fourth terminal pattern have no connection such that the first terminal pattern and the fifth terminal pattern are set as inputs and the sixth terminal pattern is set as an output. 
   Also, an EXOR circuit may be formed in which the first terminal pattern is connected with the fourth terminal pattern, and the second terminal pattern has no connection such that the third terminal pattern and the fifth terminal pattern are set as inputs and the sixth terminal is set as an output. 
   Also, an EXNOR circuit may be formed in which the second terminal pattern is connected with the third terminal pattern, and the fourth terminal pattern has no connection such that the first terminal pattern and the fifth terminal pattern are set as inputs and the sixth terminal pattern is set as an output. 
   In another aspect of the present invention, a method of manufacturing a semiconductor device may be achieved by forming MOS transistors for each of cells on a semiconductor substrate; by forming a lower wiring line layer to produce a multi-purpose circuit for the cell by connecting the MOS transistors by the lower wiring line layer; and by forming an upper wiring line layer to produce a logic circuit for the cells by connecting the multi-purpose circuits by the upper wiring line layer. 
   Here, the step of forming an upper wiring line layer may be achieved by forming a power supply wiring line pattern in a region of the cell; by forming a ground wiring line pattern in the region; and by forming a plurality of terminal patterns formed in the region. Each of the plurality of terminal patterns is connected with the multi-purpose circuit of the cell, and the plurality of terminal patterns are arranged adjacent to at least one of the power supply wiring line pattern and the ground wiring line pattern. 
   Also, the plurality of terminal patterns may include signal input terminal patterns, one or more of which are selectively opened depending on the logic circuit to be formed. In this case, the step of forming an upper wiring line layer may include: forming a pattern connecting each of remaining ones of the signal input terminal patterns to one of the power supply wiring line pattern, the ground wiring line pattern and another of the remaining signal input terminal patterns, depending on the logic circuit function block to be formed. 
   Also, the step of forming an upper wiring line layer may include: arranging adjacent to each other, ones of the plurality of terminal patterns to be connected each other depending on the logic circuit to be formed. 
   Also, the step of forming an upper wiring line layer may include: arranging adjacent to the power supply wiring line pattern, ones of the plurality of terminal patterns to be connected with the power supply wiring line pattern depending on the logic circuit to be formed. 
   Also, the step of forming an upper wiring line layer may include: arranging adjacent to the ground wiring line pattern, ones of the plurality of terminals to be connected with the ground wiring line pattern depending on the logic circuit function block to be formed. 
   Also, the multi-purpose circuit may include: Also, the logic cell may have a multi-purpose circuit as the circuit. In this case, the multi-purpose circuit may include first to third inverters and first and second transfer gates. In the first inverter, an input is connected with a first terminal pattern of the plurality of terminal patterns, and an output is connected with a second terminal pattern of the plurality of terminal patterns. In the second inverter, an input is connected with a third terminal pattern of the plurality of terminal patterns and an output is connected with a fourth terminal pattern of the plurality of terminal patterns. In the third inverter, an input is connected with a fifth terminal pattern of the plurality of terminal patterns. In the first transfer gate, an input is connected with the output of the first inverter, a first control terminal is connected with the input of the third inverter and a second control terminal is connected to an output of the third inverter. In the second transfer gate, an input is connected with the output of the second inverter, a first control terminal is connected with the output of the third inverter and a second control terminal is connected to the input of the third inverter. An output of the first transfer gate and an output of the second transfer gate are connected to a sixth terminal pattern of the plurality of terminal patterns. 
   Also, the step of forming an upper wiring line layer may be achieved by forming a first power supply wiring line pattern and a second power supply wiring line pattern as the power supply wiring line pattern, by arranging the first terminal and the fourth terminal between the first power supply wiring line pattern and the ground wiring line pattern, by arranging the second terminal and the third terminal between the ground wiring line pattern and the second power supply wiring line pattern, and by arranging the fifth terminal and the sixth terminal between the second power supply wiring line pattern and an edge portion of the region. 
   In this case, the step of forming an upper wiring line layer may be achieved by forming a NAND circuit in which the first terminal pattern is connected with the ground wiring line pattern, and the second terminal pattern and the fourth terminal pattern have no connection such that the third terminal pattern and the fifth terminal pattern are set as inputs and the sixth terminal pattern is set as an output. 
   Also, the step of forming an upper wiring line layer may be achieved by forming a NOR circuit in which the third terminal pattern is connected with the second power supply wiring line pattern, and the second terminal pattern and the fourth terminal pattern have no connection such that the first terminal pattern and the fifth terminal pattern are set as inputs and the sixth terminal pattern is set as an output. 
   Also, the step of forming an upper wiring line layer may be achieved by forming an EXOR circuit in which the first terminal pattern is connected with the fourth terminal pattern, and the second terminal pattern has no connection such that the third terminal pattern and the fifth terminal pattern are set as inputs and the sixth terminal is set as an output. 
   Also, the step of forming an upper wiring line layer may be achieved by forming an EXNOR circuit in which the second terminal pattern is connected with the third terminal pattern, and the fourth terminal pattern has no connection such that the first terminal pattern and the fifth terminal pattern are set as inputs and the sixth terminal pattern is set as an output. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram showing a logic symbol of a conventional logic cell; 
       FIG. 2  is a diagram showing an arrangement of a power supply wiring line pattern, a ground wiring line pattern and terminals in the conventional logic cell; 
       FIG. 3  is a diagram showing an arrangement example of a power supply wiring line pattern and a ground wiring line pattern and terminals in a logic cell used in a semiconductor device according to an embodiment of the present invention; 
       FIG. 4  is a circuit diagram showing the structure of a logic cell used in the semiconductor device according to the embodiment of the present invention; 
       FIG. 5A  is a diagram showing a NAND circuit, and  FIG. 5B  is a diagram showing a pattern of the logic cell of the NAND circuit in the semiconductor device according to the embodiment of the present invention; 
       FIG. 6A  is a diagram showing a NOR circuit, and  FIG. 6B  is a diagram showing a pattern of the logic cell of the NOR circuit in the semiconductor device according to the embodiment of the present invention; 
       FIG. 7A  is a diagram showing an EXOR circuit, and  FIG. 7B  is a diagram showing a pattern of the logic cell of the EXOR circuit in the semiconductor device according to the embodiment of the present invention; and 
       FIG. 8A  is a diagram showing an EXNOR circuit, and  FIG. 8B  is a diagram showing a pattern of the logic cell of the EXNOR circuit in the semiconductor device according to the embodiment of the present invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Hereinafter, a semiconductor device of the present invention will be described in detail with reference to the attached drawing. 
   In a semiconductor device with a logic circuits designed by a user, a logic cell array is formed on a semiconductor substrate. The logic cell array is composed of basic circuits called logic cells arranged in an array, and each logic cell is composed of MOS transistors. The logic cell is formed by electrically connecting the MOS transistors by a lower wiring line layer of three layers, for example. The logic circuit designed by the user is realized by forming an upper or customized wiring line layer on the lower wiring line layer to electrically connect the logic cells. The upper wiring line layer is composed of two layers, for example. Thus, a semiconductor device with the logic circuit designed by the user is manufactured. 
     FIG. 4  is a circuit diagram showing the circuit structure of a logic cell according to an embodiment of the present invention. The logic cell has an inverted output type 2-input multiplexer  1  as a multi-purpose circuit, which is provided with inverters at the first stage, and with transfer gates at the second stage. The logic cell is composed of six terminals such as a first terminal T 1 , a second terminal T 2 , a third terminal T 3 , a fourth terminal T 4 , a fifth terminal T 5  and a sixth terminal T 6 , and five logic elements such as a first inverter  10 , a second inverter  11 , a third inverter  12 , a first transfer gate  20  and a second transfer gate  21 . 
   Each of the first to third inverters  10  to  12  has the well-known structure in which an N channel MOS transistor and a P channel MOS transistor are connected between the power supply line and the ground in serial. Each of the first to third inverters  10  to  12  inverts an input signal and outputs the inversion result. Each of the first to third inverters  10  to  12  is formed from MOS transistors with a small size to decrease an input capacity. 
   Also, each of the first and second transfer gates  20  and  21  has a structure in which an N channel MOS transistor and a P channel MOS transistor are connected in parallel, i.e., a structure in which the drains are connected and the sources are connected. Each of the first and second transfer gates  20  and  21  passes a signal supplied to an input terminal or prevents the passage of the signal in accordance with signals supplied to the gate of the N channel MOS transistor and the gate of the P channel MOS transistor. In the following description, the gate of the P channel MOS transistor is called a first control input terminal and the gate of the N channel MOS transistor is called a second control input terminal. 
   The first terminal T 1  is connected with the input terminal of the first inverter  10 . The output terminal of the first inverter  10  is connected with the input terminal of the first transfer gate  20  and the second terminal T 2 . The second terminal T 2  is referred to as a middle terminal. The middle terminal can be appropriately used when a function block of the logic circuit is formed using the logic cell. Kinds of the logical circuit function blocks which can be realized using the logic cells can be increased by providing the middle terminal. For example, an EXOR circuit to be described later with reference to  FIGS. 7A and 7B  can be simply formed. 
   The third terminal T 3  is connected with the input terminal of the second inverter  11 . The output terminal of the second inverter  11  is connected with the input terminal of the second transfer gate  21  and the fourth terminal T 4 . The fourth terminal T 4  is referred to as a middle terminal like the above second terminal T 2 . The middle terminal can be appropriately used when a logic device is formed using the logic cells. Kinds of the logical function blocks which can be realized using the logic cells can be increased by providing the middle terminal. For example, the EXNOR circuit to be described later with reference to  FIGS. 8A and 8B  can be simply formed. 
   The fifth terminal T 5  is connected with the input terminal of the third inverter  12 , the first control input terminal of the first transfer gate  20 , and the second control input terminal of the second transfer gate  21 . The output terminal of the third inverter  12  is connected with the second control input terminal of the first transfer gate  20  and the first control input terminal of the second transfer gate  21 . 
   The output terminal of the first transfer gate  20  and the output terminal of the second transfer gate  21  are connected with the sixth terminal T 6 . 
   Next, the operation of the logic cell with the structure described above will be described. The logic cell functions as a multiplexer basically. That is, when the signal of the low (L) level is supplied to the fifth terminal T 5 , the P channel MOS transistor and the N channel MOS transistor in the first transfer gate  20  are both turned on. Also, the P channel MOS transistor and the N channel MOS transistor in the second transfer gate  21  are both turned off. As a result, the signal supplied to the first terminal T 1  is inverted by the first inverter  10  and is outputted from the sixth terminal T 6  through the first transfer gate  20 . On the other hand, when the signal of the high (H) level is supplied to the fifth terminal T 5 , the P channel MOS transistor and the N channel MOS transistor in the first transfer gate  20  are both turned off. Also, the P channel MOS transistor and the N channel MOS transistor in the second transfer gate  21  are both turned on. As a result, the signal supplied to the third terminal T 3  is inverted by the second inverter  11  and is outputted from the sixth terminal T 6  through the second transfer gate  21 . 
   In above operation, either of the signal supplied to the first terminal T 1  and the signal supplied to the third terminal T 3  is inverted in accordance with the level of the signal supplied to the fifth terminal T 5  and is outputted from the sixth terminal T 6 . Thus, the function of the inversion output-type multiplexer is realized. 
   As above described, the connection between the terminal T 1  to T 6 , the first to third inverters  10  to  12 , and the first and second transfer gates  20  and  21  in the logic cell is carried out in the logic cell by the lower wiring line layer. In this case, patterns of the terminal T 1  to T 6 , a power supply wiring line pattern and a ground wiring line pattern are formed in the upper wiring line layer or the customized wiring line layer which is formed on the lower wiring line layer. In the upper wiring line layer, the wiring connection between the patterns of the terminals, the power supply wiring line pattern and the ground wiring line pattern is carried out in order to realize the logical function of the logic cell and the logic circuit designed by the user. 
   Next, when the wiring connection of the above-described logic cell is carried out in the upper wiring line layer, an arrangement example of the terminals, the ground wiring line pattern and the power supply wiring line pattern, which are formed in the logic cell will be described with reference to FIG.  3 . 
   In an area of one logic cell, a first power supply wiring line pattern VDD 1 , a ground wiring line pattern GND and a second power supply wiring line pattern VDD 2  are formed in this order like lands to have predetermined widths and lengths as accommodated in the area, as shown in FIG.  3 . The first power supply wiring line pattern VDD 1 , the ground wiring line pattern GND and the second the power supply wiring line pattern VDD 2  are provided in parallel to each other to have a same interval. It should be noted that the first power supply wiring line pattern VDD 1  and the second the power supply wiring line pattern VDD 2  are different in the arranged physical position and the same potential is given to them. 
   Also, the first terminal T 1  and the fourth terminal T 4  are provided between the first power supply wiring line pattern VDD 1  and the ground wiring line pattern GND. Also, the second terminal T 2  and the third terminal T 3  are provided between the ground wiring line pattern GND and the second the power supply wiring line pattern VDD 2 . Moreover, the fifth terminal T 5  and the sixth terminal T 6  are provided on the side opposite to the second terminal T 2  and third terminal T 3  with respect to the second power supply wiring line pattern VDD 2 . 
   Each of the first terminal T 1  to the fourth terminal T 4  has a possibility that the terminal is connected with the power supply or the ground. It should be noted that the fifth terminal T 5  is a terminal to which a signal is given from outside, and is generally not connected with the power supply or the ground. Also, the sixth terminal T 6  is an output terminal and is never connected with the power supply or the ground. Therefore, the fifth terminals T 5  and the sixth terminal T 6  are provided in an edge of the area of the logic cell, i.e., between the second power supply wiring line pattern VDD 2  and an end portion of the logic cell. 
   Next, an example when a logic circuit functional block is formed by using the logic cell having the above structure will be described. 
     FIGS. 5A and 5B  show an example when a NAND circuit is formed using the logic cell shown in FIG.  4 .  FIG. 3A  shows a logic symbol of the NAND circuit, and  FIG. 3B  shows a wiring line pattern when the NAND circuit is formed. The NAND circuit is formed by connecting the first terminal T 1  of the logic cell with the ground wiring line pattern GND (logic “0”) and by opening the second terminal T 2  and the fourth terminal T 4 . By the wiring line, the  2 -input NAND circuit is realized in which the third terminal T 3  (A) and the fifth terminal T 5  are used as input terminals and the sixth terminal T 6  is used as an output terminal (O). As shown in  FIG. 5B , the NAND circuit can be formed by connecting the first terminal T 1  with the adjacent ground wiring line pattern GND in a straight line. Therefore, the wiring line pattern is short. According to the NAND circuit formed in this way, a semiconductor device can be obtained to have excellent wiring workability and good electric characteristic in a semiconductor chip. 
     FIGS. 6A and 6B  show an example when a NOR circuit is formed using the logic cell shown in FIG.  4 .  FIG. 4A  shows a logic symbol of the NOR circuit, and  FIG. 4B  shows a wiring line pattern when the NOR circuit is formed. The NOR circuit is formed by connecting the third terminal T 3  of the logic cell with the second power supply wiring line pattern VDD 2  (logic “1”) and by opening the second terminal T 2  and the fourth terminal T 4 . By the wiring line, the 2-input NOR circuit can be realized to have the first terminal T 1  (A) and the fifth terminal T 5  (B) as input terminals and have the sixth terminal T 6  as an output terminal (O). As shown in  FIG. 6B , the NOR circuit can be formed by connecting the third terminal T 3  with the adjacent second power supply wiring line pattern VDD 2  in a straight line. Therefore, the wiring line pattern is short. According to the NOR circuit formed in the way, the semiconductor chip has excellent in the wiring workability and the good electric characteristic. 
     FIGS. 7A and 7B  show an example when an EXOR circuit is formed using the logic cell shown in FIG.  4 .  FIG. 7A  shows a logic symbol of the EXOR circuit and  FIG. 7B  shows a wiring line pattern when the EXOR circuit is formed. The EXOR circuit is formed by connecting the first terminal T 1  and the fourth terminal T 4  in the logic cell and by opening the second terminal T 2 . By the wiring line, the 2-input EXOR circuit is realized to have the third terminal T 3  (A) and the fifth terminal T 5  (B) as input terminals and the sixth terminal T 6  as an output terminal (O). As shown in  FIG. 7B , the EXOR circuit can be formed by connecting only the first terminal T 1  with the adjacent fourth terminal T 4  in a straight line. Therefore, the wiring line pattern is short. According to the EXOR circuit formed in the way, the semiconductor chip is excellent in the wiring workability and the good electric characteristic. 
     FIGS. 8A and 8B  show an example when an EXNOR circuit is formed using the logic cell shown in FIG.  4 .  FIG. 8A  shows a logic symbol of the EXNOR circuit and  FIG. 8B  shows a wiring line pattern when the EXNOR circuit is formed. The EXNOR circuit is formed by connecting the second terminal T 2  and the third terminal T 3  in the logic cell and by opening the fourth terminal T 4 . By the wiring line, the 2-input EXNOR circuit is realized to have the first terminal T 1  (A) and the fifth terminal T 5  (B) as input terminals and the sixth terminal T 6  as an output terminal (O). As shown in  FIG. 8B , the EXNOR circuit can be formed by connecting only the second terminal T 2  with the adjacent third terminal T 3  in a straight line. Therefore, the wiring line pattern is short. According with the EXNOR circuit formed in the way, the semiconductor chip is excellent in the wiring workability and the good electric characteristic. 
   The examples described above are a part of the logic circuit function blocks which can be realized using the logic cell with the structure of the multiplexer shown in  FIGS. 3 and 4 . In addition to the above, a latch and a flip-flop can be formed using a plurality of logic cells. Such examples are described in Japanese Patent Application No. 2000-319269 corresponding to U.S. application Ser. No. 09/978,721 and its divisional application, whose application number is not yet designated. The disclosure thereof is incorporated herein by reference. 
   As described above, the first terminal T 1  and the fourth terminal T 4  of the logic cell which have a possibility that they are connected with the power supply or the ground are provides between the first power supply wiring line pattern VDD 1  and the ground wiring line pattern GND. Also, the second terminal T 2  and the third terminal T 3  are provided between the ground wiring line pattern GND and the second power supply wiring line pattern VDD 2 . Therefore, a logic circuit function block can be realized using the logic cell with the structure of the multiplexer by connecting each terminal with the power supply wiring line pattern or the ground wiring line pattern which is adjacent to the terminal in a straight wiring line pattern, or by connecting the adjacent terminals in a straight wiring line pattern. In other words, it is unnecessary to provide a bypassed wiring line pattern. Therefore, the wiring line pattern can be made short. As a result, the wiring workability at the formation of a wiring line pattern can be improved, and it is possible to decrease parasitic capacity due to the wiring line, resulting in the improved electric characteristic. 
   Also, the logic cell with the structure of the multiplexer is used as the logic cell. Also, the middle terminals drawn out from the internal element, i.e., the second terminal T 2  and the fourth terminal T 4  are provided. Therefore, the kinds of the logic circuit function blocks which can be realized based on the logic cell can be increased and the application range spreads. 
   As described above in detail, according to the present invention, a semiconductor device can be provided in which the wiring workability is improved and the electric characteristic can be improved and a manufacturing method for the same.