Abstract:
A current reference generator including a current network, a bias network, and a loop amplifier. The current network includes first and second transistors of a first conductivity type and third, fourth and fifth transistors of a second conductivity type. The first, third and fifth transistors are series-coupled between voltage supply lines forming a first current path, and the second and fourth transistors are series-coupled between the supply lines forming a second current path. The control terminals of the first and second transistors are coupled together and the control terminals of the third and fourth transistors are coupled together. The bias network biases the fifth transistor. The loop amplifier is coupled to the current network and is operative to maintain constant current level through the first and second current paths independent of voltage variations of the supply lines and at very low supply voltage.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates in general to current reference generators in CMOS technology, and particularly to CMOS current reference generators that are capable of operating with very low supply voltage. 
       BACKGROUND OF THE INVENTION 
       [0002]    A current reference generator is a useful component for providing a known current level within an electronic circuit. Classic current reference generators were typically implemented using bipolar transistors and resistors and the like. Many modern electronic devices, however, are implemented using complementary metal-oxide semiconductor (CMOS) technology for reduced size and power consumption. CMOS technology, for example, is particularly advantageous for smaller and/or lower power electronic devices including those which are powered by a battery. Although bipolar devices may be integrated along with CMOS devices on a common chip (e.g., BiCMOS or BiMOS), it is preferred to implement as many devices components as possible using the same process because it is generally easier, less expensive, and more efficient. Resistors can also be problematic since they generally consume a significant amount of space, and precision resistors are relatively difficult to fabricate. 
         [0003]    U.S. Pat. No. 5,949,278, entitled “Reference Current Generator In CMOS Technology,” invented by Henri Oguey taught an implementation of a CMOS current reference generator without the use of bipolar devices or resistors. The CMOS current reference generator described in this patent exhibited insensitivity to temperature and process variations. The primary configuration described therein, however, also exhibited an undesirable degree of dependence upon the supply voltage. An additional configuration was described which added a cascode stage to reduce the dependence upon supply voltage variations. The added series-coupled cascode stage, however, increased the minimum supply voltage level sufficient to properly operate the current generator. In particular, the added cascode stage raised the minimum supply voltage to about twice the threshold voltage (V T ) of the individual MOS transistors, or to about 2V T . Although MOS devices do not completely shut down when their gate-to-source voltage (V GS ) is below V T  for sub-threshold operation, the current becomes very low during sub-threshold operation so that V T  is a practical limitation for reliable operation. The V T  of most readily available technologies is above 0.7 Volts (V), so that the current generator described by the Oguey patent implemented using these technologies required a supply voltage of well over 1V (e.g., 1.4-1.8V). Certain newer technologies have reduced V T  of the devices to about 0.4V. Nonetheless, the requirement that the current generator operate with a supply voltage of about 2V T  prevents the full benefits of the lower voltage technologies. 
         [0004]    The higher voltage level is not advantageous for certain applications, such as battery-operated devices with limited supply voltage range. It is desired to provide a current reference generator that is independent of supply voltage and which successfully operates using a supply voltage of at the threshold voltage V T  of the applicable technology. 
       BRIEF SUMMARY OF INVENTION 
       [0005]    A current reference generator including a current network, a bias network, and a loop amplifier. The current network includes first second and transistors of a first conductivity type and third, fourth and fifth transistors of a second conductivity type. The first and second transistors each have a first current terminal coupled to a first supply line and a control terminal coupled to a first node. The first transistor has a second current terminal coupled to a second node and the second transistor has a second current terminal coupled to a third node. The third transistor has a first current terminal coupled to the second node, a control terminal coupled to a fourth node, and a second current terminal coupled to a fifth node. The fourth transistor has a first current terminal coupled to the third node, a control terminal coupled to the fourth node, and a second current terminal coupled to a second supply line. The fifth transistor has a first current terminal coupled to the fifth node, a second current terminal coupled to the second supply line, and has a control terminal. The bias network is coupled to at least one of the supply lines and has a control output coupled to the control terminal of the fifth transistor. The loop amplifier is coupled to the current network and is operative to maintain relatively constant current level through the current terminals of the fifth transistor. 
         [0006]    In a first configuration, the third transistor is diode-coupled in which the second and fourth nodes are coupled together, and the loop amplifier has an input coupled to the third node and an output driving the first node. In a more specific first configuration, the loop amplifier is implemented using a sixth transistor of the first conductivity type and a seventh transistor of the second conductivity type. The sixth transistor has a first current terminal coupled to the first supply line and is diode-coupled having a second current terminal and a control terminal coupled together at the first node. The seventh transistor in this configuration has a first current terminal coupled to the first node, a second current terminal coupled to the second supply line, and a control terminal coupled to the third node. A capacitor may be provided and coupled between the control terminal of the seventh transistor and the second supply line. 
         [0007]    In a second configuration, the second transistor is diode-coupled in which the first and third nodes are coupled together, and the loop amplifier has an input coupled to the second node and an output driving the fourth node. In a more specific second configuration, the loop amplifier is implemented using a sixth transistor of the first conductivity type and a seventh transistor of the second conductivity type. The sixth transistor has a first current terminal coupled to the first supply line, a control terminal coupled to the second node, and a second current terminal coupled to the fourth node. The seventh transistor in this configuration is diode-coupled having a first current terminal and a control terminal coupled together at the fourth node, and has a second current terminal coupled to the second supply line. A capacitor may be provided and coupled between the control terminal of the sixth transistor and the second supply line. 
         [0008]    In any of these configurations, a startup network may be provided to initiate desired current flow through the current branches of the current network. Also, one or more reference or output devices may be provided to tap a reference current for use. Dual configurations are also contemplated by swapping polarities of the supply lines and the transistor types. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where: 
           [0010]      FIG. 1  is a schematic diagram of a current reference generator implemented according to one embodiment coupled to a startup network; 
           [0011]      FIG. 2  is a schematic diagram of another current reference generator implemented according to another embodiment similar to the current reference generator of  FIG. 1 ; 
           [0012]      FIG. 3  is a schematic diagram of another current reference generator implemented according to another embodiment which is similar to the current reference generator of  FIG. 1  including complementary devices implementing the loop amplifier; 
           [0013]      FIG. 4  is a schematic diagram of another current reference generator implemented according to another embodiment which is similar to the current reference generator of  FIG. 2  including complementary devices implementing the loop amplifier; 
           [0014]      FIG. 5  is a schematic diagram of another current reference generator implemented according to another embodiment in a dual configuration of the current reference generator of  FIG. 3 ; and 
           [0015]      FIG. 6  is a schematic diagram of another current reference generator implemented according to another embodiment in a dual configuration of the current reference generator of  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. 
         [0017]      FIG. 1  is a schematic diagram of a current reference generator  101  implemented according to one embodiment coupled to a startup network  103 . The current reference generators described herein are implemented using transistors of complementary conductivity types, such as P-type or P-channel metal-oxide semiconductor (MOS) transistors (or PMOS transistors) and N-type or N-channel MOS transistors (or NMOS transistors). The current reference generators described herein may be implemented using CMOS technology in which the transistors are coupled to supply voltage lines shown as VDD and VSS, in which VSS provides a reference voltage level (e.g., ground) and VDD develops a difference voltage level relative to VSS to establish proper circuit operation. Although VDD and VSS are usually configured to provide a relatively stable voltage difference, variations may occur. The current reference generators described herein establish at least one reference current that remains relatively constant in spite of variations of VDD and/or VSS (or, generally, variations of the voltage difference between VDD and VSS). Also, the current reference generators described herein maintain a valid reference current for a very low voltage difference between VDD and VSS, such as a supply voltage at about the threshold voltage (V T ) of the MOS transistors of the applicable MOS technology. 
         [0018]    The current reference generator  101  includes PMOS transistors MP 1 , MP 2  and MP 3 , NMOS transistors MN 1 , MN 2 , MN 3  and MN 4 , an operational amplifier (op-amp)  106  and a voltage source  105 . MP 1 , MP 2  and MP 3  each have a source coupled to VDD and a gate coupled to a node  107 , which is further coupled to the output of the op-amp  106 . Thus, the gates of MP 1 -MP 3  are driven by the output of the op-amp  106  at node  107 . MP 1  has its drain coupled to the drain of MN 1  at a node  102 , MP 2  has its drain coupled to the drain of MN 2  at a node  104 , and MP 3  has its drain coupled to the drain of MN 3  at a node  108 . The sources of MN 2 , MN 3  and MN 4  are each coupled to VSS. MN 4  has its drain coupled to the source of MN 1  at a node  111 . The gates of MN 1  and MN 2  are coupled together at a node  109 , and MN 1  is diode-coupled so that its drain is also coupled to its gate at node  109  (so that nodes  102  and  109  are coupled together). The gates of MN 3  and MN 4  are coupled together at node  108  and MN 3  is diode-coupled having its drain coupled to its gate. The voltage source  105  develops a voltage VDN, and has a negative terminal coupled to VSS and a positive terminal coupled to a non-inverting (+) input of the op-amp  106 . The inverting (−) input of op-amp  106  is coupled to the drains of MP 2  and MN 2 . 
         [0019]    The op-amp  106  and the voltage source  105  are coupled and configured to operate as a loop amplifier  110  as further described herein. The series-coupled drain-source configuration of the transistors MP 1 , MN 1  and MN 4  forms a first current path having a current I 1 . The series-coupled drain-source configuration of the transistors MP 2  and MN 2  forms a second current path having a current I 2 . The series-coupled drain-source configuration of the transistors MP 3  and MN 3  forms a third current path having a current I 3 . 
         [0020]    The startup network  103  includes NMOS transistors SN 1  and SN 2  and a capacitor C. SN 1  and SN 2  have their sources coupled to VSS. The drain of SN 2  is coupled to the gate of SN 1  and to one end of the capacitor C. The other end of C is coupled to VDD. The drain of SN 1  is coupled to node  107 . The gate of SN 2  is coupled to node  109 . Operation of the startup network  103  is further described below. 
         [0021]    In operation of the current reference generator  101 , the loop amplifier  110  drives the gates of MP 1  and MP 2  at node  107  forcing their drain currents I 1  and I 2  to be defined by the ratio of the sizes of MP 1  and MP 2 . In one embodiment, MP 1  and MP 2  are matched transistors having approximately the same size so that the currents I 1  and I 2  are approximately the same. Also, MN 1  may be sized larger than MN 2  so that the gate-to-source voltage V GS  of MN 2  is larger than the V GS  of MN 1 . The voltage difference between the V GS  of MN 1  and MN 2  develops as the drain-source voltage of MN 4 , which is the voltage at node  111  relative to VSS. In one embodiment, MP 3  is sized about the same as MP 1  and MP 2  so that the current I 3  is effectively a mirror image current of the currents I 1  and I 2  (e.g., I 1 =I 2 =I 3 ). MP 3  and the diode-coupled MN 3  collectively form a bias network to establish a gate voltage for MN 4 . MN 3  and MN 4  are also coupled in a current mirror configuration to equalize I 1  and I 3 . The level of the currents I 1  and I 2  (and I 3 ) is determined by the size of MN 4  and the ratio of sizes of MN 1  and MN 2 . 
         [0022]    In one embodiment, the voltage VDN of the voltage source  105  is chosen to be about the same as the voltage of node  109  relative to VSS. Although the non-inverting input of the op-amp  106  may be coupled directly to node  109 , an independent voltage source is also contemplated. In one embodiment, a separate transistor configuration (not shown) is coupled to develop the appropriate voltage level. In another embodiment, the expected voltage of  109  is configured or otherwise known and the voltage source  105  independently develops the expected voltage level. The op-amp  106  may be independently configured on the same integrated circuit (IC) chip and configured with suitable parameters and characteristics. Alternatively, the op-amp  106  is implemented using complementary devices as further described below. The virtual ground input of the op-amp  106  drives the drains of MP 2  and MN 2  to about the same voltage of VDN. The drain-source voltages of the pair of transistors MN 1  and MN 2  are about the same regardless of variations of VDD and/or VSS, and the drain-source voltages of the pair of transistors MP 1  and MP 2  are also about the same regardless of variations of VDD and/or VSS. Thus, the currents I 1  and I 2  are not dependent upon the supply voltage between VDD and VSS. Furthermore, the current reference generator  101  exhibits insensitivity to temperature and process variations. 
         [0023]    In summary for the current reference generator  101 , the current level of I 1 -I 3  is essentially determined by the relative sizes of MN 1 , MN 2  and MN 4  (assuming MP 1 -MP 3  are configured to be approximately the same size). MN 3  may be configured to be smaller than up to about the same size as MN 4 . The loop amplifier  110  operates to drive the gates of MP 1 -MP 3  to equalize the currents I 1 -I 3 . Because of the operation of the loop amplifier  110 , the current level of each of the currents I 1 -I 3  remains substantially independent of the voltage difference between VDD and VSS down to a very low voltage level, such as about the threshold voltage V T  of the MOS transistors. 
         [0024]    At least one significant benefit of the current reference generator  101  is that the currents I 1 -I 3  remain relatively constant and are relatively independent of the supply voltages VDD and VSS. Thus, changes of VDD and/or VSS does not appreciably affect the level of current I 1 -I 3  through the current branches, resulting in a very reliable and stable current reference. In prior art or conventional configurations using current mirrors or the like, the branch currents exhibited dependency on the supply voltage which required relatively stable supply voltages. 
         [0025]    Another significant advantage of the current reference generator  101  is that the voltage difference between VDD and VSS may be very low without affecting current reference operation. In prior art or conventional configurations using current mirrors or the like, the dependency upon the supply voltage may be reduced by adding a cascode stage or the like between the transistor pairs MP 1 /MP 2  and MN 1 /MN 2 . Although the cascode stage reduced dependence upon supply voltage, it increased the minimum voltage level needed between VDD and VSS to ensure proper operation (e.g., to ensure that the transistors operated in the appropriate operating modes for reference current operation). In typical conventional configurations using the added cascode stage, the minimum voltage difference between VDD and VSS for proper operation was about twice the threshold voltage V T  of the MOS devices. The minimum voltage difference between VDD and VSS for the current reference generator  101  is about V T , or even just below V T  for sub-threshold operation, which is particularly advantageous for battery-operated electronic devices. Further, although the voltage difference between VDD and VSS may be at very low levels, it may also be increased to higher voltage levels without changing the current levels of I 1 -I 3 . The maximum voltage difference depends upon the breakdown voltages of the CMOS devices (PMOS and NMOS devices). Also, the current reference generator  101  exhibits insensitivity to temperature and process variations. 
         [0026]    The startup network  103  is provided to ensure proper initial startup operation of the current reference generator  101 . Upon startup, the capacitor C is initially discharged pulling the gate of SN 1  high thus initially turning SN 1  on. While turned on, SN 1  pulls current through the PMOS transistors MP 1 -MP 3  which causes current flow of I 1 -I 3  through the respective current branches. A corresponding voltage develops on the gate of SN 2  at node  109 , which turns SN 2  on to charge the capacitor C, which eventually charges to a sufficient level to turn off SN 1 . SN 2  does not draw appreciable current so that the current reference generator  101  operates in accordance with normal operation after SN 1  is turned off. The specific startup network  103  shown illustrates only one of many different methods to achieve start up operation. 
         [0027]      FIG. 2  is a schematic diagram of another current reference generator  201  implemented according to another embodiment similar to the current reference generator  201 . The startup network  103  is not shown in  FIG. 2  but may be included and coupled to the current reference generator  201  in substantially the same manner. The current reference generator  201  is substantially similar to the current reference generator  101  in which similar components and devices assume identical reference numbers. The transistors MP 1 -MP 3  and MN 1 -MN 4  are configured in substantially the same manner and also coupled in substantially the same manner (via nodes  102 ,  104 ,  107 ,  108 ,  109 ,  111 ), except that MN 1  is not diode-coupled and MP 1  is diode-coupled. Thus, the gate of MN 1  is not coupled to its own drain and the gate of MP 2  is coupled to its own drain. The gates of MP 1  and MP 2  are coupled together in similar manner at node  107 , which is further coupled to the drain of MP 2  at node  104  (so that nodes  104  and  107  are coupled together). Nodes  102  and  109  are not coupled together. The voltage source  105  is replaced by a voltage source  205  developing a voltage VDP. The op-amp  103  is included, except that its inverting (−) input is coupled to the drains of MN 1  and MP 1 , its non-inverting (+) input is coupled to the negative terminal of the voltage source  205 , and its output is coupled to node  209 . The positive terminal of the voltage source  205  is coupled to VDD. The op-amp  103  and the voltage source  205  are coupled to operate as a loop amplifier  210  in analogous manner as the loop amplifier  110 . 
         [0028]    In operation of the current reference generator  201 , the loop amplifier  210  drives the gates of MN 1  and MN 2  at node  209  forcing their drain currents I 1  and I 2  to be approximately equal. In one embodiment, the voltage VDP is chosen to be about the same voltage level as the voltage of node  107  relative to VDD. The voltage source  205  may be implemented in a similar manner as described above for the voltage source  105 . The virtual ground input of the op-amp  106  drives the drains of MP 1  and MN 1  to about the same voltage of VDP. Again, the drain-source voltages of the pair of transistors MN 1  and MN 2  are about the same regardless of variations of VDD and/or VSS, and the drain-source voltages of the pair of transistors MP 1  and MP 2  are also about the same regardless of variations of VDD and/or VSS. Thus, the currents I 1  and I 2  are substantially independent upon the supply voltage between VDD and VSS. Also, the current reference generator  201  exhibits insensitivity to temperature and process variations 
         [0029]    In summary for the current reference generator  201 , the current level of I 1 -I 3  is essentially determined by the relative sizes of MN 1 , MN 2  and MN 4  (assuming MP 1 -MP 3  are configured to be approximately the same size). MN 3  may be configured to be smaller than up to about the same size as MN 4 . The loop amplifier  210  operates to drive the gates of MN 1  and MN 2  to equalize the currents I 1 -I 3 . Substantially the same benefits of the current reference generator  101  are achieved by the current reference generator  201 . The currents I 1 -I 3  are relatively constant and independent of the supply voltages VDD and VSS, so that changes of VDD and/or VSS does not appreciably affect the level of current through the current branches, resulting in a very reliable and stable current reference. The voltage difference between VDD and VSS may be very low, such as about the threshold voltage V T  as previously described, which again is particularly advantageous for battery-operated electronic devices. Also, the voltage difference between VDD and VSS may be significantly higher without changing the current levels of I 1 -I 3 . 
         [0030]      FIG. 3  is a schematic diagram of another current reference generator  301  implemented according to another embodiment. The startup network  103  is not shown but may be included and coupled to the current reference generator  301  in substantially the same manner as previously described. The current reference generator  301  is substantially similar to the current reference generator  101  in which similar components and devices assume identical reference numbers. The transistors MP 1 -MP 3  and MN 1 -MN 4  are configured in substantially the same manner and also coupled in substantially the same manner in which MN 1  is diode-coupled at node  109  and MP 2  is not diode-coupled. The loop amplifier  110  is replaced by a loop amplifier  310 , which includes PMOS transistor MP 4 , NMOS transistor MN 5 , and capacitor C 1 . MP 4  is diode-coupled having its gate and drain coupled together at node  107  and its source coupled to VDD. MN 5  has its source coupled to VSS, its drain coupled to the drain of MP 4 , and its gate coupled to the common drains of MP 2  and MN 2 . The capacitor C 1  is coupled between the gate of MN 5  and VSS. In this case, MN 5  is an amplifying element, and MP 4  is a load of the loop amplifier  310 . C 1  is provided to stabilize the loop if the loop is not already stable. In some configurations, if the loop is stable without C 1 , then C 1  is not needed. Also, alternative methods may be used to stabilize the loop rather than the capacitor C 1 . 
         [0031]    In operation of the current reference generator  301 , the gate of MN 5  effectively functions as the input of the loop amplifier  310  at node  104 , and the gate of MP 4  operates as its output at node  107 . In one embodiment, MP 4  is configured in substantially the same manner as MP 1  and MP 2 , such as being another matched PMOS transistor. Also, MN 5  is configured in substantially the same manner as MN 2 , such as having the same or similar size. During operation, the gate voltage of MN 5  at node  104  is about the same as the voltage of the gates and drains of MN 1  and MN 2  (nodes  102  and  109 ), so that MN 5  is biased on thus drawing another current I 4  through both MP 4  and MN 5 . Since MP 4  is diode-coupled in a current mirror configuration, the current I 4  flowing through a current branch created by the series drains-sources of MP 4  and MN 5  is related to the currents I 1  and I 2 . If MP 4  is about the same size and MP 1  and MP 2 , then I 4  is also about the same current level as I 1  and I 2 . 
         [0032]    If the gate voltage of MN 5  attempts to increase, it increases the V GS  of MN 5  turning it on more thus attempting to increase I 4 . An increase of I 4  tends to turn MP 4  on more, thus decreasing its gate voltage and the gate voltages of MP 1  and MP 2  at node  107 . A decrease of the voltage of node  107  tends to turn MP 1  and MP 2  more on resulting in a corresponding increase of I 1  and I 2 , which tends to turn MN 2  on more. If MN 2  turns on more, it pulls the gate voltage of MN 5  lower to counteract any tendency of increasing the gate voltage of MN 5 . In this manner, the loop amplifier  310  has negative feedback to drive the gates of MP 1  and MP 2  to keep I 1  and I 2  relatively constant. 
         [0033]    The loop gain of the loop amplifier  310  has positive and negative counterparts. The negative loop gain G( 310 ) NEG  can be expressed according to the following equation (1): 
         [0000]        G (310) NEG   =−A (− GM   MP1 )( −K )( R   0 )=− A ( GM   MP1 )( K )( R   O )   (1)
 
         [0000]    where A is the gain of the amplifier, GM MP1  is the transconductance gain of MP 1 , K is a mirror factor of the current mirror components MN 1  and MN 2 , and R O  is an impedance on the drains of MN 2  and MP 2 . The positive loop gain G( 310 ) POS  has a similar form and may be expressed according to the following equation (2): 
         [0000]        G (310) POS   =−A (− GM   MP2 )( R   O )= A ( GM   MP2 )( R   O )   (2)
 
         [0000]    in which GM MP2  is the transconductance gain of MP 2 . If MP 1  and P 2  are chosen to have about the same size and configuration, then GM MP1 ≈GM MP2  (in which “≈” means approximately equal or equivalent), so that the difference between the positive and negative loop gains is the mirror factor K of MN 1  and MN 2 . Because of the presence of MN 4 , the mirror factor K is greater than 1 (K&gt;1), so that the negative gain is greater than the positive gain (G( 310 ) NEG &gt;G( 310 ) POS ) such that the negative gain dominates the loop to ensure proper function. 
         [0034]    The current reference generator  301  is shown including additional reference transistors for tapping and providing one or more reference currents. A first reference transistor, PMOS transistor MP 5 , has its source coupled to VDD, its gate coupled to node  107  and its drain providing a reference current I 5 . MP 5  may be sized to scale the current of I 5 , such as to be approximately equal to I 1  and I 2 . A second reference transistor, NMOS transistor MN 6 , has its gate coupled to node  104 , its source coupled to VSS and its drain providing a reference current I 6 . MN 6  may be sized to scale the current of I 6 , such as to be approximately equal to I 1  and I 2 . A third reference transistor, NMOS transistor MN 7  has its gate coupled to node  108 , its source coupled to VSS and its drain providing a reference current I 7 . MN 7  may be sized to scale the current of I 7 , such as to be approximately equal to I 1  and I 2 . 
         [0035]    The current reference generator  301  operates in substantially the same manner as the current reference generator  101  and exhibits substantially the same advantages. The loop amplifier  310  operates to drive the gates of MP 1 -MP 3  to equalize the currents I 1 -I 3 . Because of the operation of the loop amplifier  310 , the current level of each of the currents I 1 -I 3  remains substantially independent of the voltage difference between VDD and VSS down to a very low voltage level, such as about V T . Also, the current reference generator  301  exhibits insensitivity to temperature and process variations. 
         [0036]      FIG. 4  is a schematic diagram of another current reference generator  401  implemented according to another embodiment. The startup network  103  is not shown but may be included and coupled to the current reference generator  401  in substantially the same manner as previously described. The current reference generator  401  is substantially similar to the current reference generator  201  in which similar components and devices assume identical reference numbers. The transistors MP 1 -MP 3  and MN 1 -MN 4  are configured and coupled in substantially the same manner and also coupled in substantially the same manner in which MP 2  is diode-coupled at node  107  and MN 1  is not diode-coupled. The loop amplifier  210  is replaced by a loop amplifier  410 , which includes PMOS transistor MP 4 , NMOS transistor MN 5 , and capacitor C 1 . In this case, MN 5  is diode-coupled having its gate and drain coupled together at node  109  and its source coupled to VSS. MP 4  has its source coupled to VDD, its drain coupled to the drain of MN 5 , and its gate coupled to the drains of MP 1  and MN 1  at node  102 . The capacitor C 1  is coupled between the gate of MP 4  and VSS. In this case, MP 4  is an amplifying element, MN 5  is a load of the loop amplifier  410 , and C 1  is provided to stabilize the loop. 
         [0037]    In operation of the current reference generator  401 , the gate of MP 4  effectively functions as the input of the loop amplifier  410  at node  102 , and the gate of MN 5  operates as its output at node  109 . In one embodiment, MP 4  is configured in substantially the same manner as MP 1  and MP 2 , such as being another matched PMOS transistor. Also, MN 5  is configured in substantially the same manner as MN 2 , such as having the same or similar size. During operation, the gate voltage of MP 4  is about the same as the gates and drains of MP 1  and MP 2  (nodes  104  and  107 ), so that MP 4  is biased on thus drawing current I 4  through both MP 4  and MP 5 . MN 5  is diode-coupled in a current mirror configuration so that I 4  is about the same current level as I 1  and I 2 . If the gate voltage of MP 4  attempts to increase, it decreases the V GS  of MP 4  attempting to decrease I 4 . A decrease of I 4  tends to decrease the V GS  of MN 2 , so that the current I 2  through MN 2  also tends to decrease. This, in turn, tends to decrease the current I 1  through MN 1 , which tends to decrease the gate voltage of MP 4 , thereby closing the loop and counteracting the increase of the gate voltage of MP 4 . In this manner, the loop amplifier  410  has negative feedback to drive the gates of MN 1  and MN 2  to keep I 1  and I 2  relatively constant. 
         [0038]    The loop gain of the loop amplifier  410  also has positive and negative counterparts. The negative loop gain G( 410 ) NEG  can be expressed according to the following equation (3): 
         [0000]        G (410) NEG   =−A ( GM   MN2 )( R   O )   (3)
 
         [0000]    where again A is the gain of the amplifier, GM MN2  is the transconductance gain of MN 2 , and R O  is an impedance on the drains of MN 1  and MP 1 . The positive loop gain G( 410 ) POS  has a similar form and may be expressed according to the following equation (4): 
         [0000]        G (410) POS   =−A (− GM   MN1 )( R   O )= A ( GM   MN1 )( R   O )   (4)
 
         [0000]    in which GM MN1  is the transconductance gain of MN 1 . MN 1  and MN 2  are chosen so that MN 1  is larger than MN 2 . The presence of MN 4  coupled to the source of MN 1  lowers the transconductance of MN 1 , so that the effective transconductance gain GM MN2  of MN 2  is greater than the transconductance gain GM MN1  of MN 1 . Thus, the negative gain is greater than the positive gain (G( 410 ) NEG &gt;G( 410 ) POS ) so that the negative gain dominates the loop to ensure proper function. 
         [0039]    The current reference generator  401  is shown including additional reference transistors MP 5 , MN 6  and MN 7  for tapping one or more reference currents I 5 , I 6  and I 7 , respectively, in a similar manner as previously described for the current reference generator  301 . The respective sizes of the reference transistors are chosen to scale the reference currents as desired, where the reference currents I 5 -I 7  are each related to the currents I 1  and I 2  as previously described. 
         [0040]    The current reference generator  401  operates in substantially the same manner as the current reference generator  201  and exhibits substantially the same advantages. The loop amplifier  410  operates to drive the gates of MN 1  and MN 2  to equalize the currents I 1 -I 3 . Because of the operation of the loop amplifier  410 , the current level of each of the currents I 1 -I 3  remains substantially independent of the voltage difference between VDD and VSS down to a very low voltage level, such as about V T . Also, the current reference generator  401  exhibits insensitivity to temperature and process variations. 
         [0041]      FIG. 5  is a schematic diagram of another current reference generator  501  implemented according to another embodiment. The current reference generator  501  is a dual configuration of the current reference generator  301  in which VSS and VDD are swapped (i.e., VSS→VDD, VDD→VSS), each NMOS transistor is replaced by a corresponding PMOS transistor with the same index number (MN 1 →MP 1 , MN 2 →MP 2 , etc.), each PMOS transistor is replaced by a corresponding NMOS transistor with the same index number (MP 1 →MN 1 , MP 2 →MN 2 , etc.), and the schematic diagram is vertically flipped so that VDD is above and VSS is below. The loop amplifier  310  is replaced by a loop amplifier  510  including loop transistors MP 5  (MN 5 →MP 5 ) and MN 4  (MP 4 →MN 4 ) and capacitor C 1 . C 1  is coupled between the gate of MP 5  and VDD (rather than VSS, since VSS→VDD). Additional reference current transistors MN 5  and MP 6  are provided for providing reference currents I 5  and I 6 , respectively. Operation is analogous to that of the current reference generator  301 , in which the currents I 1 -I 4  are substantially equal and constant. The benefits and advantages are substantially the same, in which the difference between VDD and VSS may be very low (about V T ) and the reference currents I 1  and I 2  are relatively independent of changes of VDD and VSS. Also, the current reference generator  501  exhibits insensitivity to temperature and process variations. 
         [0042]      FIG. 6  is a schematic diagram of another current reference generator  601  implemented according to another embodiment. The current reference generator  601  is a dual configuration of the current reference generator  401  in which VSS and VDD are swapped (i.e., VSS→VDD, VDD→VSS), each NMOS transistor is replaced by a corresponding PMOS transistor with the same index number (MN 1 →MP 1 , MN 2 →MP 2 , etc.), each PMOS transistor is replaced by a corresponding NMOS transistor with the same index number (MP 1 →MN 1 , MP 2 →MN 2 , etc.), and the schematic diagram is vertically flipped so that VDD is above and VSS is below. The loop amplifier  410  is replaced by a loop amplifier  610  including loop transistors MP 5  (MN 5 →MP 5 ) and MN 4  (MP 4 →MN 4 ) and capacitor C 1 . C 1  is coupled between the gate of MN 4  and VDD (rather than VSS, since VSS→VDD). Additional reference current transistors MN 5  and MP 6  are provided for providing reference currents I 5  and I 6 , respectively. Operation is analogous to that of the current reference generator  401 , in which the currents I 1 -I 4  are substantially equal and constant. The benefits are substantially the same, in which the difference between VDD and VSS may be very low down to about V T ) and the reference currents I 1  and I 2  are relatively independent of changes of VDD and VSS. Also, the current reference generator  501  exhibits insensitivity to temperature and process variations. 
         [0043]    While various embodiments of the present invention have been described herein, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant arts that various changes in form and detail can be made therein without departing from the scope of the invention. Finally, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims.