Abstract:
In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Description:
BACKGROUND 
   1. Technical Field 
   Embodiments of the invention relate generally to interrupts for processors. 
   2. Background Art 
   An Advanced Programmable Interrupt Controller (APIC) is a programmable interrupt controller (PIC) that receives interrupt requests and provides interrupt outputs according to programmable procedures or priorities. Local APICs are used in processors (such as microprocessors). I/O APICs are used in chipset devices (such as an input/output (I/O) controller hub (ICH)) and peripheral devices. Examples of peripheral devices include device coupled to the ICH that are compatible with one of the Peripheral Component Interconnect (PCI) standards or one of the PCI Express (PCIe) standards such as the PCI Express® Base Specification Revision 2.0, Dec. 20, 2006, provided by the PCI-SIG®. An xAPIC is an extended APIC, which is similar to early APICs but with some additional features and in the xAPIC architecture, local and I/O APICs communicate through a system bus rather than through an APIC bus. A further Extended xAPIC includes additional extensions and features. 
   Processor packages may include more than one core, each of which may include more than one processor. Physical mode interrupts are interrupts for which an interrupting device designates a processor by a physical identification number or is broadcast to all processors. Logical mode interrupts are interrupts for which an interrupting device designates a processor or processors by a logical identification numbers or numbers. APIC interrupt deliveries include directed interrupts (single processor target), multi-cast (multiple processor target) and broadcast (all processors). In a lowest priority interrupt, a procedure is used to select a processor that is in the lowest processor priority to respond to the interrupt. Lowest priority may be decided in the chipset—often in an ad hoc fashion or with stale data of processor priority. Because the priority information is often not reliable, some chipsets merely select a particular processor (such as through a round robin technique) and provide the interrupt to that processor in a broadcast manner in which the other processors also receive the interrupts but do not respond to them. 
   The logical mode provides significantly greater flexibility in directed interrupts and is the mode used by Microsoft Windows &amp; some Linux shrink-wrap operating systems. The logical mode of the xAPIC architecture provides an operating system software with flexibility in initializing the logical APIC identification number (ID), which is the unique identifier for each processor in the system. (The processors also have physical APIC IDs.) Other processors as well as devices or IOxAPICs use this ID to send interrupts to this processor. Given the flexibility in initialization of the logical xAPIC ID, there is no relationship between the actual physical topology of the platform and how the IDs are assigned. Although operating system initialization allows operating systems greater flexibility in grouping processors, at a platform level this complicates the routing of directed logical mode interrupts. Routing of logical mode interrupts is done through broadcasting the interrupts and having the local processor logic accept the interrupt if it matches its local APIC ID. 
   Having each processor check for every interrupt leads to both performance and power inefficiencies. For example, under a broadcast approach, each processor checks to see if the interrupt is directed to the processor although the processor is in a low power state. Since interrupts occur fairly often, it makes it difficult for a processor to stay in a deep low power state. Further, performance is reduced because there is traffic on interconnects in sending interrupts to packages for which the interrupt is not directed. Under one approach, an operating system has attempted to have a logical cluster of processors be for processors in the same package by assigning logical IDs in the order the processors are started. This approach provides only a partial solution if relied upon and broadcasting is still used. Accordingly, there remains a need for creating logical APICs that can be routed to processors in an efficient manner. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The inventions will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the inventions which, however, should not be taken to limit the inventions to the specific embodiments described, but are for explanation and understanding only. 
       FIG. 1  is a block diagram representation of a system including multi-core processor packages, an input/output hub, and a device according to some embodiments of the inventions. 
       FIG. 2  is a block diagram representation of a system including multi-core processor packages, an input/output hub, and a device according to some embodiments of the inventions. 
       FIG. 3  is a block diagram representation of sockets on a circuit board for use in some embodiments of the inventions. 
       FIG. 4  is a block diagram representation of a physical APIC ID register for use in some embodiments of the inventions. 
       FIG. 5  is a block diagram representation of a logical APIC ID register for use in some embodiments of the inventions. 
       FIG. 6  is a block diagram representation of logical APIC ID creation logic. 
       FIG. 7  illustrates generation of a logical APIC ID from a physical APIC ID for use in some embodiments of the inventions. 
       FIG. 8  illustrates physical and logical APIC IDs for a two socket system with four cores per package and two logical processors per core according to some embodiments of the inventions. 
       FIG. 9  is a block diagram representation of an APIC redirection table with multiple entries for use in some embodiments of the inventions. 
       FIG. 10  is a block diagram representation of an APIC redirection table entry for use in some embodiments of the inventions. 
   

   DETAILED DESCRIPTION 
   In some embodiments, a system creates logical APIC IDs for each processor from the processor physical IDs. The logical APIC IDs include a processor cluster ID and a processor number within the cluster (intra-cluster ID). The logical APIC IDs are created such that all processors within a cluster are contained in the same processor package. This helps reduce traffic on interconnects because interrupts can be directed to only one processor package, rather than be broadcast to all processor packages. Further, this reduces power consumption because processors in other processor packages (or in some cases other clusters within the same processor package) do not receive the interrupts and, therefore, do not have to determine whether the interrupt is directed to them. In some cases, this prevents processors from having to come out of a sleep state. 
   In some embodiments, a logical destination identification number can include processors that are available to respond to an interrupt. Processor selection logic selects one of the available processors to receive the interrupt. 
   In the following discussion, physical APIC IDs are examples of physical processor identification numbers and logical APIC IDs are examples of logical processor identification numbers. Logical APIC ID creation logic is an example of logical identification number creation logic. 
   1. System Overview 
     FIG. 1  illustrates a system that may be used in some embodiments of the inventions, but other embodiments may include systems that include different details. Referring to  FIG. 1 , a system includes multiple processor packages including at least a processor package  0  and a processor package  1  coupled to an input/output hub (IOH)  12 . IOH  12  includes a IOH I/O APIC  14 , redirection logic  18 , and processor selection logic  20 . A PCIe device  26  including a PCIe I/O APIC  28  is coupled to IOH  12  through interrupt interface circuitry  30 . Devices  36  (such as a keyboard and a mouse) provide interrupts through IOH I/O APIC  14 . IOH I/O APIC  14 , I/O PCIe APIC  28 , and local APICs  72 - 1  . . .  72 - 4  and  78 - 1  . . .  78 - 4  may be various types of APICs such as xAPICs or extended xAPICs. Alternatively, interrupt controllers other than APICs may be used. 
   Package  0  includes cores  0  and  1  and additional circuitry referred to herein as uncore  42 . Core  0  includes processors  70 - 1  and  70 - 2 , which include local APICs  72 - 1  and  72 - 2 , respectively, and core  1  includes processors  70 - 3  and  70 - 4 , which include local APICs  72 - 3  and  72 - 4 , respectively. Package  1  includes cores  2  and  3  and additional circuitry referred to as uncore  52 . Core  1  includes processors  76 - 1  and  76 - 2 , which include local APICs  78 - 1  and  78 - 2 , respectively, and core  3  includes processors  76 - 3  and  76 - 4 , which include local APICs  78 - 3  and  78 - 4 , respectively. Packages  0  and  1  will include various components not specifically illustrated. Memory  64  (such as main memory DRAM) is coupled to uncore  42 , and memory  66  is coupled to uncore  52 . Memory  60  (including a hard drive that holds an operating system (OS)) is coupled to IOH  12 . There may be intermediate components between memory  60  and IOH  12 . BIOS memory  62  is coupled to IOH  12 . 
   Processors  70 - 1 ,  70 - 2 ,  70 - 3 , and  70 - 4  have physical APIC IDs P 0 , P 1 , P 2 , and P 3 , respectively. Processors  70 - 1 ,  70 - 2 ,  70 - 3 , and  70 - 4  have physical APIC IDs P 0 , P 1 , P 2 , and P 3 , respectively. The logical APIC ID creation logic (in  FIG. 6 ) provides logical APIC IDs L 0 , L 1 , L 2 , and L 3  and L 16 , L 17 , L 18 , and L 19  based on the physical IDs P 0 , P 1 , P 2 , and P 3  and P 16 , P 17 , P 18 , and P 19 , respectively. (Of course, P 0  . . . P 4  and P 16  . . . P 19  and L 0  . . . L 3  and L 16  . . . L 19  represent ID bits and not the letter “P” or “L” and a number.) In some embodiments, packages  0  and  1  include more than two cores (see, for example,  FIG. 8 ) and a core may include more than two processors. In the illustrated embodiment, there is a gap in physical IDs between P 3  and P 16  and in corresponding logical IDs between L 3  and L 16 . A reason for this is that in these embodiments, a cluster includes IDs for sixteen processors, whether or not there are sixteen actual processors. A processor package may include one chip (die) or more than one chip. A processor package may include zero, one or more than one memory chips. 
   Redirection logic  18  receives a value (for example, a 16-bit value) from device  26  and provides an interrupt to package  0  or package  1 . The decision of which processor to use to respond to an interrupt can be made in various places. For example, depending on the embodiment, the decision may be made in processor selection logic  20  in IOH  12 , and/or in a processor selection sub-logic in an uncore (such as processor selection sub-logic  46  in uncore  42  or processor selection sub-logic  56  in an uncore  52 ). A filter  48  in sub-logic  48  and a filter  58  in sub-logic  56  may be used to filter out from consideration processors based on, for example, power states (c-states) and/or processor priority. A similar filter may be used in processor selection logic  20 . In some embodiments, there is not a processor selection logic  20 , but merely processor selection sub-logic. 
     FIG. 2  is similar to  FIG. 1  and illustrates an IOH  112  with a IOH APIC  114 , redirection logic  118 , processor selection logic  120 , and interrupt interface circuitry  130  that may be similar to or identical to IOH APIC  14 , redirection logic  18 , processor selection logic  20 , and interrupt interface circuitry  30  in  FIG. 1 .  FIG. 2  also illustrates a processor package  0  including cluster of processors  0  and clusters of processors  1 , a processor package  1  including cluster of processors  2  and clusters of processors  3 , processor package N- 1  including cluster of processors  2  (N- 1 ) and clusters of processors  2  (N- 1 )+1. Processor packages  0 ,  1 , . . . N- 1  are coupled to IOH  112  through interconnects  142 - 0 ,  142 - 1  . . .  142 -N- 1 . In some embodiments, there are separate interconnects to separate processors and in other embodiments there one set of interconnects is used for each processor package or one set of interrupts for each cluster. The cluster ID of an interrupt indicates which of the clusters is to receive the interrupt. 
   For example, assume that the cluster ID is 0000000000000010b (where b indicates binary). That would indicate cluster  2  is to receive the interrupt. This involves less power and involves less traffic on the interconnects as compared to an approach in which the interrupt is broadcast to all processors. The interrupt is not sent on interconnects  142 - 0  and  142 -N- 1  so there is less traffic on these interconnects which helps with bandwidth and reducing power. Also, processors in clusters  0 ,  1 ,  3 ,  2 (N- 1 ), and  2 (N- 1 )+1 do not have to check whether the interrupt is directed to them, which reduces power (particularly where a processor must come out of a deep low power state to determine whether the interrupt is directed to it). There may also be less cache line traffic between processors in different clusters because of locality. Other embodiments may include even more clusters of processors in processor packages. Other components (such as uncores if included) are not shown in  FIG. 2 . There may be additional components such as bridges between the IOH and processor packages. Further, there may be more than one IOH in a system. 
     FIG. 3  illustrates a circuit board  190  (such as a printed circuit board) includes sockets including a socket  0  to receive a processor package  0 , socket N- 1  to receive a processor package N- 1 , and socket  194  to receive an IOH chip. In some implementations, circuit board  190  includes additional sockets for processor packages and for various other chips, but in other implementations, circuit board  190  includes only two sockets. As used herein, the term “socket” covers various techniques for coupling a chip or chips to a circuit board. 
   2. APIC ID Initialization 
   In some embodiments, the physical APIC IDs are statically initialized/latched by hardware and/or micro-code in, for example, coming out of reset and persists until the next power cycle.  FIG. 4  illustrates a register  110  to hold a 32-bit physical APIC ID that in some embodiments is included in a corresponding local APIC. 
   The logical APIC ID which is used in logical mode is partitioned into two fields—a 16-bit wide cluster ID and a 16-bit wide logical ID within the cluster of processors. The sixteen most significant bits of the logical ID contain the address or identification number of the destination cluster, while the lower sixteen bits identify an individual local APIC unit within the cluster. The logical ID portion may be a bit-mask with 1 bit per processor in the cluster—for example, bit  0  would be set for processor  0  in a processor cluster, bit  1  for processor  1  in the processor cluster, etc.  FIG. 5  illustrates a register  112  to hold a 32-bit logical APIC ID, with bits  16  to  31  hold a cluster ID and bits  0  to  15  holding an intra-cluster logical ID. As a practical matter, many systems will have a small number of processor clusters such that, for example, only one or two bits needed to identify the cluster ID. In different embodiments, the remaining bits may be treated differently. For example, some of the bits are ignored in some systems and used in other systems. 
   Through the initialization algorithm there may be an established, persistent relationship between the logical APIC ID and the physical APIC ID based on platform topology. This provides the routing fabric with knowledge of the specific processor packages (sockets) to route interrupts to as opposed to doing a broadcast. 
   In the case in which a processor cluster may hold a limit of sixteen processors, if there are more than sixteen processors in a processor package, then there will be multiple clusters per package. If there are fewer than sixteen processors in a cluster, then a padding of APIC IDs may be used. 
   Logical APIC ID creation logic  216  creates logical APIC IDs from physical APIC IDs. The logical APIC ID creation logic  216  may be implemented in hardware, software, or microcode or a combination of them. The hardware may be in the uncore or local APIC or elsewhere. In some embodiments, the logical APIC ID is derived such that the lower 4-bits of the physical APIC ID are “decoded” (i.e. 1&lt;&lt;Physical APIC ID[3:0]) to provide a 16-bit logical ID within the cluster. The remaining 16-bits of the physical APIC ID then form the cluster ID portion of the logical xAPIC ID. The logical xAPIC ID is thus derived from the local xAPIC ID using the following formula:
 
Logical APIC ID=[(Physical APIC ID[19:4]&lt;&lt;16)∥(1&lt;&lt;Physical APIC ID[3:0])]
 
In the formula, the symbol ∥ means “OR” but could be replaced with addition and the same result would be achieved.
 
   This formula can be re-stated in a similar way as follows:
 
Logical ID=(1&lt;&lt;Local xAPIC ID[3:0]) //Intra-cluster Logical ID
 
∥(Local xAPIC ID[19:4]&lt;&lt;16) //Cluster ID
 
     FIG. 7  illustrates at example of the process of deriving logical APICs converting a physical APIC ID in register  210  to a logical APIC ID in register  212 . Bits  20 - 31  may be ignored or used for various purposes. 
     FIG. 8  shows an example of obtaining the logical APIC ID through the physical APIC ID in processor packages  0  and  1  each including four cores with two processor each. Since there are fewer than sixteen processors per package, there is only one cluster per package. Referring to package  0 , the physical APIC ID for processor P 0  is shown as 0 0000 b. The “b” is for binary. The first 0 is from a cluster ID and indicates the cluster is the one in package  0 . To save space in the figure, other bits from the cluster ID are not illustrated in  FIG. 8 . The four underlined 0&#39;s are in the intra-cluster ID and indicate that the physical APIC ID is 0 (without listing all the zeros). Following the procedure discussed above, the logical APIC ID is created by starting with a “1” in the least significant bit (LSB) in an intra-cluster logical ID otherwise containing zeros and then shifting the “1” by an amount found in the first four bits of the physical ID. Since, the first four bits of the physical ID of processor P 0  is 0000, the “1” is not shifted, and therefore the logical ID is 0001h (where “h” refers to hexadecimal). Hexadecimal is used to allow large numbers to be illustrated in  FIG. 8 . The cluster ID (0) remains the same as in bits  4 - 19  of the physical ID. In the case of processor P 1 , the four LSBs of the physical ID are 0001, so the “1” is shift by one bit such that the cluster ID is 0 for cluster  0  and the logical ID is 0002h which is caused by a 1 being shifted by one bit For example, in the case of processor P 5 , the “1” is shifted to the left by 5 bits which is 32 in decimal or 20 in hex. The same follows for the package  1  except that the cluster ID is 1 in both the physical and logical APIC IDs. 
   The initialization can happen at multiple points in time, for example, depending on the ease of implementation. Examples of when the initialization can occur including while coming out of reset when the physical APIC ID is initialized or at the time with the operating system first reads the logical APIC ID. The above algorithm with the padding of APIC IDs if needed may ensure that each APIC cluster is confined to a single processor package. 
   3. Processor Selection Logic and Redirection 
   Processor selection logic selects a processor to receive an interrupt from among available choices. Having a local APIC receive an interrupt is an example of a processor receiving the interrupt. In the prior art, processors have been chosen for interrupts through a lowest priority scheme. However, as is explained below, factors other than or in addition to the processor priority can be considered in deciding which processor is to receive the interrupt. 
   The operating system can select a cluster and at least one processor within cluster as being available for the interrupt. This information may be included directly or indirectly in the interrupt provided by a device such as device  26  in  FIG. 1 . For example, in a direct implementation, the interrupt may include a 16-bit field, one for each processor in the cluster in a bit mapped fashion (although there may be fewer than 16 processors in which case some bits might not be used). A processor that is available as a “1” in a position associated with that processor, such the position used in providing logical APIC IDs from physical APIC IDs in the formula discussed above and in  FIG. 8 . This can be called the logical destination ID. As an example, a logical destination ID bit mask could be 00101101, which indicates processors P 0 , P 2 , P 3 , and P 5  are available for an interrupt. This assumes there are eight processors in a cluster, so the eight left most bits are not shown. Of course, the role of “0 and “1” could be reversed so a 0 represents a available processor and a 1 represents a processor that is not available. The processor selection logic discussed above can select which of the available processors is to receive the interrupt. Note that while typically only one processor receives an interrupt, in some cases an interrupt may be directed to more than one processor. 
   As an alternative, the interrupt from device  36  may include an index (such as a 16-bit index), which provides an index into a redirection table, that may be included redirection logic  19  of  FIG. 1 . Referring to  FIG. 9 , a redirection table  230  includes, for example, 64-bit entries for different index values. Entry  234  is an example.  FIG. 10  shows details of example entry  234  according to some embodiments, but in other embodiments it may be different. Referring to  FIG. 10 , bits  48 - 63  indicate a cluster ID, which in the example of  FIG. 10  indicates that a cluster  2  is to receive the interrupt. See example in connection with  FIG. 2 . Still referring to  FIG. 10 , the logical destination ID lists available processors for the processor selection logic (or sub-logic) to consider. The destination ID bit mask 011b indicates processors P 0  and P 1  are available and the other processors are not. Only three of the sixteen bits are shown in  FIG. 10  for convenience of illustration. As another example, the destination bit mask could be 00101101b which indicates processors P 0 , P 2 , P 3 , and P 5  are available and processors P 1 , P 4 , P 6  and P 7  are not. There are not processors P 8 -P 15  in this example. It could be that only one processor is available. Bits  0  to  31  can give various type of routing information such as whether direct interrupts are involved. “Lowest priority” is shown in  FIG. 10  but as mentioned other factors such as power states can be considered, so that strictly speaking it might not be considered a lowest priority selection. 
   There are several possible implementations that may be used for routing the interrupt within the cluster based on knowledge of the processor power states and priorities. One possible implementation in the “uncore” would use the processor power states knowledge and priorities to provide interrupt routing to enables both power aware interrupt routing that takes performance implications into account. The uncore will have knowledge of the C-state (power saving state) of the processor—these are referred to, for example, as C 0 , C 1 , C 2 , . . . C 6 —where C 0  is the state where the processor (or core) is running code and C 1 , . . . C 6  are idle states where the processor is halted: C 1  is the lowest power saving state and C 6  is the higher power saving state. Also the latency (and micro-architectural side effects) to get into C 1  may be the lowest while those are highest for C 6 . To provide the highest value from the deeper C-states (such as C 6 ), it may be desirable to allow for processors that have entered a C 6  state to stay resident in that state for the longest possible interval. In this possible implementation, the uncore would identify the target by (1) identifying the processors(s) in the lowest numbered C-state and (2) finding the processor with the lowest priority among these processors as the target for the interrupt. There are several ways in which these approaches may be implemented. An implementation can retain a bitmap of the processors in a package in various C-states, AND these against the incoming target bit map and pick the highest or lowest APIC ID in that bitmap as the target. Other implementation details may be used. 
   ADDITIONAL INFORMATION AND EMBODIMENTS 
   The “logic” referred to herein can be implemented in circuits, software, microcode, or a combination of them. 
   An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. 
   When it is said the element “A” is coupled to element “B,” element A may be directly coupled to element B or be indirectly coupled through, for example, element C. 
   When the specification or claims state that a component, feature, structure, process, or characteristic A “causes” a component, feature, structure, process, or characteristic B, it means that “A” is at least a partial cause of “B” but that there may also be at least one other component, feature, structure, process, or characteristic that assists in causing “B.” Likewise, that A is responsive to B, does not mean it is not also responsive to C. 
   If the specification states a component, feature, structure, process, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, process, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. 
   The inventions are not restricted to the particular details described herein. Indeed, many other variations of the foregoing description and drawings may be made within the scope of the present inventions. Accordingly, it is the following claims including any amendments thereto that define the scope of the inventions.