Abstract:
In accordance with an embodiment, a modulator includes a comparator and ramp generating circuitry. A first comparison signal is generated in response to comparing a first input signal with a compensation signal. A second comparison signal is generated in response to comparing a second input signal with the compensation signal. A first latch signal is generated in response to the first comparison signal and a second latch signal is generated in response to the second comparison signal.

Description:
BACKGROUND 
       [0001]    The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductor devices and structure. 
         [0002]    Numerous techniques have been used to control switching power supplies. One of the most common is known as pulse-width modulation (PWM) in which the switching frequency is held constant while the duty cycle is modulated to control the output. Another common technique is known as pulse frequency modulation (PFM) in which the switch on-time or off-time is held constant, and the frequency is modulated to control the output. In another technique known as hysteretic control (or ripple regulation) frequency and duty cycle are varied to keep the output ripple constant. 
         [0003]    Accordingly, it would be advantageous to have a method and circuit suitable for use in controlling switching power supplies. It would be of further advantage for the method and structure to be cost efficient to implement. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which: 
           [0005]      FIG. 1  is a circuit schematic of a converter that includes a ramp pulse modulation stage in accordance with an embodiment of the present invention; 
           [0006]      FIG. 2  is circuit schematic of a ramp pulse modulation stage in accordance with an embodiment of the present invention; 
           [0007]      FIG. 3  is a timing diagram of circuit parameters of the ramp pulse modulation stage of  FIG. 2  in accordance with an embodiment of the present invention; 
           [0008]      FIG. 4  is circuit schematic of a ramp pulse modulation stage in accordance with an embodiment of the present invention; 
           [0009]      FIG. 5  is a timing diagram of circuit parameters of the ramp pulse modulation stage of  FIG. 4  in accordance with an embodiment of the present invention; 
           [0010]      FIG. 6  is a timing diagram of circuit parameters of the ramp pulse modulation stage of  FIG. 2  in accordance with an embodiment of the present invention; 
           [0011]      FIG. 7  is a timing diagram of circuit parameters of the ramp pulse modulation stage of  FIG. 4  in accordance with an embodiment of the present invention; 
           [0012]      FIG. 8  is a circuit schematic of a converter that includes a constant-on-time modulation stage in accordance with an embodiment of the present invention; 
           [0013]      FIG. 9  is circuit schematic of a constant-on-time modulation stage in accordance with an embodiment of the present invention; 
           [0014]      FIG. 10  is a timing diagram of circuit parameters of the constant-on-time modulation stage of  FIG. 9  in accordance with an embodiment of the present invention; 
           [0015]      FIG. 11  is circuit schematic of a constant-on-time modulation stage in accordance with an embodiment of the present invention; 
           [0016]      FIG. 12  is a timing diagram of circuit parameters of the constant-on-time modulation stage of  FIG. 11  in accordance with an embodiment of the present invention; 
           [0017]      FIG. 13  is a timing diagram of circuit parameters of the constant-on-time modulation stage of  FIG. 9  in accordance with an embodiment of the present invention; and 
           [0018]      FIG. 14  is a timing diagram of circuit parameters of the constant-on-time modulation stage of  FIG. 11  in accordance with an embodiment of the present invention. 
       
    
    
       [0019]    For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. The use of the word approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described. 
         [0020]    It should be noted that a logic zero voltage level (V L ) is also referred to as a logic low voltage and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family. For example, in a Complementary Metal Oxide Semiconductor (CMOS) logic family a logic zero voltage may be thirty percent of the power supply voltage level. In a five volt Transistor-Transistor Logic (TTL) system a logic low voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts. A logic one voltage level (V H ) is also referred to as a logic high voltage level and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts. 
       DETAILED DESCRIPTION 
       [0021]      FIG. 1  is a circuit schematic of a voltage regulator  10  in accordance with an embodiment of the present invention. Voltage regulator  10  includes a drive circuit  12  configured to drive switching devices  14  and  16  in response to a Ramp Pulse Modulation (RPM) signal from a ramp pulse modulator  18 . Drive circuit  12  may be referred to as a gate drive circuit and ramp pulse modulator  18  may be referred to as an RPM stage. Ramp pulse modulator  18  is configured to operate in response to a compensation signal (V COMP ). Switching devices  14  and  16  may be power field effect transistors, such as, for example, power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), where each switching device has a control electrode and a pair of current carrying electrodes. As discussed above, the control electrodes may be gate terminals and the current carrying electrodes may be drain and source terminals. It should be noted that  FIG. 1  illustrates body diodes  24  and  26  of switching devices  14  and  16 , respectively, and that the source terminals of switching devices  14  and  16  are connected to their body regions. The drain terminal of switching device  14  is coupled for receiving an input signal (V IN ) and the source terminal of switching device  14  is commonly connected to the drain terminal of switching device  16  and to a terminal of an inductor  22 . The source terminal of switching device  16  is coupled for receiving a source of operating potential such as, for example, V SS . Potential V SS  may be, for example, a ground potential. The other terminal of inductor  22  is commonly connected to an input terminal of a summer  21 , an input terminal of a current sense circuit  26 , a terminal of an output capacitor  28 , and a terminal of a load  30  to form an output terminal or node  32  at which an output voltage V OUT  appears. Summer  21  has an input terminal connected to an output terminal of current sense circuit  26 . The output terminal of summer  21  is connected to an input terminal of a compensation circuit  20 . Compensation circuit  20  has another input terminal, which is coupled for receiving, for example, a voltage identification digital (VID) control signal, and an output terminal connected to an input terminal  18 A of ramp pulse modulator  18 . By way of example, compensation circuit  20  is a comparator. In addition to input terminal  18 A, ramp pulse modulator  18  has at least input terminals  18 B,  18 C,  18 D,  18 E, and  18 F and an output terminal  18 G, which output terminal is connected to an input terminal of drive circuit  12 . Output terminals  12 A and  12 B of gate drive circuit  12  are connected to the gate terminals of switching devices  14  and  16 , respectively. 
         [0022]    In operation and in response to an input voltage V IN  at the drain terminal of switching device  14  and drive signals V ARA  and V ERB  at the gate terminals of switching transistors  14  and  16 , a switching voltage V SWN  appears at node  25  and a current I L  flows through inductor  22 . Inductor current I L  flows through load  30  and generates an output voltage V OUT  at output node  32 . Inductor current I L  is sensed by current sense circuit  26  to generate a current sense signal V cs . Current sense signal V cs  and output signal V OUT  are summed or added together by summer  21  to generate a summed signal V SUM , which is transmitted to the inverting input terminal of compensation circuit  20 . In response to summed signal V SUM  and control signal VID, compensation circuit  20  generates a compensation signal V COMP , which serves as an input signal for ramp pulse modulator  18 . Ramp pulse modulator  18  generates a pulse signal DUTY_ 10  at output terminal  18 G that causes drive circuit  12  to generate drive signals V DRA  and V DRB . The operation of ramp pulse modulator  18  will be explained in more detail below with reference to  FIG. 2 . 
         [0023]      FIG. 2  is a circuit schematic of ramp pulse modulation circuit  18  in accordance with an embodiment of the present invention. Ramp pulse modulation circuit  18  comprises comparators  50  and  52  each having a noninverting input terminal, an inverting input terminal, and an output terminal. The inverting input terminal of comparator  50  and the noninverting input terminal of comparator  52  are connected together and coupled for receiving compensation signal V COMP  at terminal  18 A of ramp pulse modulator  18 . Comparator  50  has an output terminal  54  connected to the reset input terminal (R) of a latch  60  and comparator  52  has an output terminal  56  connected to the set input terminal (S) of latch  60 . The signals that appear at comparator output terminals  54  and  56  are referred to as comparison signals. Latch  60  has an output terminal  62  that serves as output terminal  18 G (shown in  FIG. 1 ) and an output terminal  64  that is connected to a control electrode of a transistor  66 . Output terminal  18 G is connected to the input terminal of drive circuit  12  (shown in  FIG. 1 ). 
         [0024]    In addition to a control electrode, transistor  66  has current carrying electrodes such as, for example drain and source electrodes or terminals. By way of example, the source terminal is commonly connected to a terminal of a capacitor  68  and to a terminal of a current source  70  to form an input terminal such as, for example, input terminal  18 D of ramp pulse modulator  18 . The commonly connected source terminal and terminals of capacitor  68  and current source  70  are coupled for receiving a potential V B  from voltage source  72 . The drain terminal is commonly connected to the other terminals of capacitor  68  and current source  70  and to the noninverting input terminal of comparator  50  and may serve as terminal  18 C shown in  FIG. 1 . Current source  70  is coupled between terminals  18 D and  18 C and sources a current signal I B . Transistor  66 , capacitor  68 , and current source  70  may be referred to as a ramp generation circuit  71 . 
         [0025]    Ramp pulse modulator  18  further includes a transistor  106  having a control electrode and current carrying electrodes. Output terminal  62  (and therefore terminal  18 G) is connected to the control electrode of transistor  106 . The source terminal of transistor  106  is commonly connected to a terminal of capacitor  108  and to the inverting input terminal of comparator  52  to form a node that can serve as input terminal  18 E. A ramp pulse modulation signal V RPM1  appears at the inverting input terminal of comparator  52 . The drain terminal of transistor  106  is connected to the other terminal of capacitor  108  to form a node that may serve as input terminal  18 F. A current source  110  is connected between input terminals  18 E and  18 F and a voltage source  112  is connected to input terminal  18 F. Transistor  106 , capacitor  108 , and current source  110  may be referred to as a ramp generation circuit  113 . Voltage source  112  provides a voltage V T  and current source  110  sources a current I T . A diode  116  has a cathode connected to input terminal  18 E and an anode that serves as input terminal  18 B. 
         [0026]    A voltage source  114  is coupled to input terminal  18 B, voltage source  72  is connected to input terminal  18 D, and a voltage source  112  is connected to input terminal  18 F. 
         [0027]    Output terminal  18 G is connected to the input terminal of drive circuit  12  (shown in  FIG. 1 ). 
         [0028]    In operation, input signals V COMP , D TH , V B , and V T  are coupled to input terminals  18 A,  18 B,  18 D, and  18 F, respectively, of ramp pulse modulator  18  (shown in  FIGS. 1 and 2 ). Current source  70  is connected between input terminals  18 D and  18 C (shown in  FIGS. 1 and 2 ) and in response to the input signal at the control electrode of transistor  66  the current flowing through current source  70  generates an input signal V RPM  at the noninverting input terminal of comparator  50 , i.e., input terminal  18 C.  FIG. 3  is a timing diagram  115  showing signals V COMP , V B , D TH , V RPM , V RPM1 , V T , and pulse signal DUTY_ 10 . Referring now to  FIGS. 2 and 3 , before time t 0 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at the Q output, of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus the voltage at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is discharged to make the voltage at terminal  18 C substantially equal to that at terminal  18 D. Because voltage V RPM  is less than voltage V COMP  before time t 0 , comparator  50  generates a logic low voltage at output terminal  54 . 
         [0029]    As the time approaches time t 0  from a time before time t 0 , voltage V RPM1  approaches voltage D TH . 
         [0030]    In response to voltage V COMP  increasing and crossing through voltage level V RPM1  at time t 0 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal (S) of latch  60 . In response to the logic high voltage at the set input terminal of latch  60 , the signal at Q output terminal  62 , i.e., output terminal  18 G, transitions to a logic high voltage level. It should be noted that Q output terminal  62  of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at the Q output terminal serves as a pulse signal (DUTY_ 10 ) that is transmitted to the input terminal of drive circuit  12 . 
         [0031]    The logic high voltage at output terminal  62  turns on transistor  106 , which sets voltage V RPM1  at input node  18 E to a voltage substantially equal to voltage V T . In addition, latch  60  generates a logic low voltage at output terminal  64  which turns off transistor  66 . Current source  70  generates a current I B  which charges capacitor  68  such that the voltage at input terminal  18 D, i.e., at the noninverting input terminal of comparator  50 , increases at a rate of approximately I B /C 68  volts per second, where I B  is the current sourced by current source  70  and C 68  is the capacitance value of capacitor  68 . Thus, the voltage V RPM  at the noninverting input terminal of comparator  50  is a ramp signal having a slope of approximately I B /C 68 . 
         [0032]    At time t 1 , voltage V COMP  crosses through the voltage level of voltage V RPM  and after time t 1  becomes less than voltage V RPM . In response to voltage V COMP  becoming less than voltage V RPM  and the logic high voltage level at the reset input terminal (R) of latch  60 , a logic low voltage level appears at output terminal  62 , which turns off transistor  106 . Current source  110  sources a current I T  which charges capacitor  108  such that the voltage at input terminal  18 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 108  volts per second, where current I T  is the current sourced by current source  110  and C 108  is the capacitance value of capacitor  108 . Thus, the voltage V RPM1  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 0  to approximately time t 1  and is a ramp signal from approximately time t 1  to approximately time t 2  having a negative slope of approximately I T /C 108 . It should be noted that pulse signal DUTY_ 10  appearing at output terminal  62  transitions to a logic low voltage level at time t 1  and that the duration of pulse signal DUTY_ 10  being at a logic high voltage and the duration of the constant voltage portion of voltage V RPM1  are substantially equal. It should be further noted that the period of pulse signal DUTY_ 10  is substantially equal to the period of voltage signal V RPM1 , i.e., the sum of the time at which signal V RPM1  is at a substantially constant voltage level and the time that signal V RPM1  is a ramp. The duration of the constant voltage portion of signal V RPM1  is substantially equal to the duration at which pulse signal DUTY_ 10  is at a logic high voltage level and the duration of the ramp portion of voltage signal V RPM1  is substantially equal to the duration at which pulse signal DUTY_ 10  at a logic low voltage level. 
         [0033]    Between times t 1  and t 2 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at the Q output, of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus voltage V RPM  at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is discharged to a make the voltage at input terminal  18 C substantially equal to that at input terminal  18 A. Because voltage V RPM  is less than voltage V COMP  between times t 1  and t 2 , comparator  50  generates a logic low voltage at output terminal  54 . 
         [0034]    In response to voltage V COMP  increasing and becoming greater than voltage V RPM1  at time t 2 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60  and causes the signal at the Q output terminal to transition to a logic high voltage level. As noted above, the Q output terminal of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at the Q output terminal serves as pulse signal DUTY_ 10  that is transmitted to the input terminal of drive circuit  12 . 
         [0035]    The logic high voltage at output terminal  62  turns on transistor  106 , which sets voltage V RPM1  at input terminal  18 E to a voltage substantially equal to voltage V T . In addition, the logic high voltage at output terminal  62  causes latch  60  to generate a logic low voltage at output terminal  64  which turns off transistor  66 . Current source  70  sources a current I B  which charges capacitor  68  such that the voltage at input terminal  18 C, i.e., at the noninverting input terminal of comparator  50 , increases at a rate of approximately I B /C 68  volts per second, where I B  is the current sourced by current source  70  and C 68  is the capacitance value of capacitor  68 . Thus, beginning at about time t 2  the voltage V RPM  at the noninverting input terminal of comparator  50  is a ramp signal having a slope of approximately I B /C 68 . 
         [0036]    At time t 3 , voltage V COMP  becomes less than voltage V RPM . In response to voltage V COMP  becoming less than voltage V RPM  and the logic high voltage level at the reset input of latch  60 , a logic low voltage level appears at output terminal  62 , which turns off transistor  106 . Current source  110  generates a current I T  which charges capacitor  108  such that voltage V RPM1  at input terminal  18 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 108  volts per second. Thus, voltage V RPM1  at the inverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 2  to approximately time t 3  and is a ramp signal from approximately time t 3  to approximately time t 4  having a negative slope of I T /C 108 . It should be noted that pulse signal DUTY_ 10  appearing at output terminal  62  transitions to a logic low voltage level at time t 3  and that the duration of pulse signal DUTY_ 10  being at a logic high voltage and the duration of the constant voltage portion of voltage V RPM1  are substantially equal. It should be further noted that the period of pulse signal DUTY_ 10  is substantially equal to the sum of the time that pulse signal DUTY_ 10  is at a logic high voltage level and the time that pulse signal DUTY_ 10  is at a logic low voltage level. Thus, the period of pulse signal DUTY_ 10  is substantially equal to the period of voltage signal V RPM1 , i.e., the sum of the time at which signal V RPM1  is at a substantially constant voltage level and the time that signal V RPM1  is a ramp. The duration of the constant voltage portion of signal V RPM1  is substantially equal to the duration at which pulse signal DUTY_ 10  is at a logic high voltage level and the duration of the ramp portion of voltage signal V RPM1  is substantially equal to the duration at which pulse signal DUTY_ 10  at a logic low voltage level. 
         [0037]    Between times t 3  and t 4 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at the Q output, of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus voltage V RPM  at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is discharged to a make voltage V RPM  at input terminal  18 C substantially equal to that at input terminal  18 A. Because voltage V RPM  is less than voltage V COMP  between times t 3  and t 4 , comparator  50  generates a logic low voltage at output terminal  54 . In response to voltage V COMP  increasing and becoming greater than voltage level V RPM1  at time t 4 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60  and causes the signal at Q output terminal  62  to transition to a logic high voltage level. As noted above, Q output terminal  62  of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at the Q output terminal  62  serves as pulse signal DUTY_ 10  that is transmitted to the input terminal of drive circuit  12 . 
         [0038]    Ramp pulse modulator  18  generates a pulse signal DUTY_ 10  that is at a logic high voltage for a time that is coincident with the ramp portion of voltage V RPM  and is at a logic low voltage for a time that is coincident with the ramp portion of voltage V RPM1 . For example, pulse signal DUTY_ 10  transitions from a logic low voltage to a logic high voltage in response to voltage signal V RPM  beginning to rise from voltage level V B  and pulse signal DUTY_ 10  transitions from the logic high voltage to the logic low voltage in response to voltage signal V RPM1  beginning to decrease from voltage level V T . Thus, the frequency of pulse signal DUTY_ 10  varies in accordance with the ramp portions of voltage signals V RPM  and V RPM1 . 
         [0039]      FIG. 4  is a circuit schematic of ramp pulse modulation circuit  150  in accordance with an embodiment of the present invention. It should be noted that the input/output configuration of ramp pulse modulation circuit  150  may be the same as that of ramp pulse modulation circuit  18 . Thus, ramp pulse modulation circuit  18  can be replaced by ramp pulse modulation circuit  150 . It should be further noted that the operation of voltage regulator  10  described with reference to  FIGS. 1 and 2  may also apply to embodiments in which ramp pulse modulation circuit  150  replaces ramp pulse modulation circuit  18 . Ramp pulse modulation circuit  150  comprises comparators  50  and  52 , latch  60 , transistors  66  and  106 , capacitors  68  and  108 , diode  116 , input terminals  18 A,  18 B,  18 C,  18 D,  18 E, and  18 F, and output terminal  18 G as described with reference to  FIG. 2 . In addition, ramp pulse modulation circuit  150  includes a one shot  152  connected between output terminal  62  and the gate of transistor  106 . 
         [0040]    A voltage source  114  is coupled to input terminal  18 B, voltage source  72  is connected to input terminal  18 D, and a voltage source  112  is connected to input terminal  18 F. 
         [0041]    Output terminal  18 G is connected to the input terminal of drive circuit  12  (shown in  FIG. 1 ). 
         [0042]    In operation, input signals V COMP , D TH , V B , and V T  are coupled to input terminals  18 A,  18 B,  18 D, and  18 F, respectively, of ramp pulse modulator  150  (shown in  FIGS. 1 and 4 ). Current source  70  is connected between input terminals  18 D and  18 C (shown in  FIG. 4 ) and in response to the input signal at the control electrode of transistor  66  the current flowing through current source  70  generates an input signal V RPM  at the noninverting input terminal of comparator  50 , i.e., input terminal  18 C.  FIG. 5  is a timing diagram  155  showing signals V COMP , V B , D TH , V RPM , V RPM1 , V T , and pulse signal DUTY_ 150 . Referring now to  FIGS. 4 and 5 , before time t 0 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at the Q output, of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus the voltage at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is discharged to make voltage V RPM  at terminal  18 C substantially equal to that at terminal  18 D. Because voltage V RPM  is less than voltage V COMP  before time t 0 , comparator  50  generates a logic low voltage at output terminal  54 . 
         [0043]    Before time t 0 , voltage V RPM1  approaches voltage D TH . 
         [0044]    In response to voltage V COMP  increasing and crossing through the signal level of signal V RPM1  at time t 0 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60 . In response to the logic high voltage at the set input terminal of latch  60 , the signal at Q output terminal  62 , i.e., output terminal  18 G transitions to a logic high voltage level. It should be noted that Q output terminal  62  of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at the Q output terminal serves as a pulse signal (DUTY_ 150 ) that is transmitted to the input terminal of drive circuit  12 . 
         [0045]    The logic high voltage level at output terminal  62  appears at the input terminal of one shot  152  and triggers one shot  152 . Thus, a logic high voltage appears at the control electrode of transistor  106 , turning on transistor  106 , which sets voltage V RPM1  at input node  18 E to a voltage substantially equal to voltage V T . In addition, latch  60  generates a logic low voltage at output terminal  64  which turns off transistor  66 . Current source  70  generates a current I B  which charges capacitor  68  such that the voltage at input terminal  18 D, i.e., at the noninverting input terminal of comparator  50 , increases at a rate of approximately I B /C 68  volts per second. Thus, the voltage V RPM  at the noninverting input terminal of comparator  50  is a ramp signal having a slope of approximately I B /C 68 . 
         [0046]    One shot  152  creates at logic high voltage at the control electrode of transistor  106  for a fixed period of time. This fixed time period ends at time t 1 . Thus, at time t 1  one shot  152  reverts to its stable state which turns off transistor  106 . Current source  110  sources a current I T  which charges capacitor  108  such that the voltage at input terminal  18 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 108  volts per second. Thus, the voltage V RPM  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 0  to approximately time t 1  and is a ramp signal from approximately time t 1  to approximately time t 3  and has a negative slope of I T /C 108 . The period of pulse signal DUTY_ 150  is substantially equal to the sum of the time that pulse signal DUTY_ 150  is at a logic high voltage level and the time that pulse signal DUTY_ 150  is at a logic low voltage level. The period of pulse signal DUTY_ 150  is substantially equal to the period of voltage signal V RPM1 , i.e., the sum of the time at which signal V RPM1  is at a substantially constant voltage level and the time that signal V RPM1  is a ramp signal. 
         [0047]    At time t 2 , compensation signal V COMP  becomes substantially equal to voltage V RPM , which causes comparator  50  to generate a logic high voltage at output  54 . In response to the logic high voltage appearing at output  54 , a logic high voltage appears at output  64  of latch  60  and a logic low voltage appears at output  62  of latch  60 . Accordingly, pulse signal DUTY_ 150  transitions to a logic low voltage level. 
         [0048]    Between times t 2  and t 3 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at the Q output, of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus voltage V RPM  at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is discharged to a make voltage V RPM  at input terminal  18 C substantially equal to that at input terminal  18 A. Because voltage V RPM  is less than voltage V COMP  between times t 2  and t 3 , comparator  50  generates a logic low voltage at output terminal  54 . 
         [0049]    In response to voltage V COMP  increasing and becoming greater than voltage V RPM1  at time t 3 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60  and causes the signal at the Q output terminal to transition to a logic high voltage level. As noted above, the Q output terminal of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at the Q output terminal serves as pulse signal DUTY_ 150  that is transmitted to the input terminal of drive circuit  12 . 
         [0050]    The logic high voltage level at output terminal  62  appears at the input terminal of one shot  152  and triggers one shot  152 . Thus, a logic high voltage appears at the control electrode of transistor  106 , turning on transistor  106 , which sets voltage V RPM1  at input node  18 E to a voltage substantially equal to voltage V T . In addition, latch  60  generates a logic low voltage at output terminal  64  which turns off transistor  66 . Current source  70  generates a current I B  which charges capacitor  68  such that voltage V RPM  at input terminal  18 C, i.e., at the noninverting input terminal of comparator  50 , increases at a rate of approximately I B /C 68  volts per second. Thus, voltage V RPM  at the noninverting input terminal of comparator  50  is a ramp signal having a slope of approximately I B /C 68 . 
         [0051]    One shot  152  creates at logic high voltage at the control electrode of transistor  106  for a fixed period of time. This fixed time period ends at time t 4 . Thus, at time t 4  one shot  152  reverts to its stable state which turns off transistor  106 . Current source  110  sources a current I T  which charges capacitor  108  such that voltage V RPM1  at input terminal  18 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 108  volts per second. Thus, the voltage V RPM1  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 3  to approximately time t 4  and is a ramp signal from approximately time t 4  to approximately time t 6  having a slope of I T /C 108 . The period of pulse signal DUTY_ 150  is substantially equal to the sum of the time that pulse signal DUTY_ 150  is at a logic high voltage level and the time that pulse signal DUTY_ 150  is at a logic low voltage level. The period of pulse signal DUTY_ 150  is substantially equal to the period of voltage signal V RPM1 , i.e., the sum of the time at which signal V RPM1  is at a substantially constant voltage level and the time that signal V RPM1  is a ramp signal. 
         [0052]    At time t 5 , compensation signal V COMP  becomes substantially equal to voltage V RPM , which causes comparator  50  to generate a logic high voltage at output  54 . In response to the logic high voltage appearing at output  54 , a logic high voltage appears at output  64  of latch  60  and a logic low voltage appears at output  62  of latch  60 . Accordingly, pulse signal DUTY_ 150  transitions to a logic low voltage level. 
         [0053]    Between times t 5  and t 6 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at the Q output, of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus the voltage at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is discharged to make voltage V RPM  at input terminal  18 C substantially equal to that at input terminal  18 A. Because voltage V RPM  is less than voltage V COMP  between times t 5  and t 6 , comparator  50  generates a logic low voltage at output terminal  54 . 
         [0054]    In response to voltage V COMP  increasing and becoming greater than voltage V RPM1  at time t 6 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60  and causes the signal at the Q output terminal to transition to a logic high voltage level. 
         [0055]      FIG. 6  is a timing diagram  120  of pulse ramp modulator  18  operating in Discontinuous Conduction Mode (DCM) mode. In operation, input signals V COMP , D TH , V B , V RPM , V RPM1 , and V T  appear at input terminals  18 A,  18 B,  18 D,  18 C,  18 E, and  18 F, respectively, of pulse ramp modulator  18  (shown in  FIGS. 1 and 2 ). Current source  70  is connected between input terminals  18 D and  18 C (shown in  FIGS. 1 and 2 ). In response to the input signal at the control electrode of transistor  66  the current flowing through current source  70  sources a current I B  and in response to current I B  signal V RPM  appears at the noninverting input terminal of comparator  50 , i.e., input terminal  18 C. Current source  110  is connected between input terminals  18 E and  18 F and in response to the input signal at the control electrode of transistor  106  current source  110  sources a current I T  which is used to generate a voltage signal V RPM1  at the inverting input terminal of comparator  52 , i.e., input terminal  18 E.  FIG. 6  is a timing diagram showing signals V COMP , V B , D TH , V RPM , V RPM1 , V T , and pulse signal DUTY_ 10 . Referring now to  FIGS. 1 and 2 , before time t 0 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output terminal, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at the Q output terminal, of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus voltage V RPM  at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is charged to a voltage substantially equal to voltage V B . Because voltage V RPM  is less than voltage V COMP  before time t 0 , comparator  50  generates a logic low voltage at output terminal  64 . As the time approaches time t 0  from a time before time t 0 , voltage V RPM1  is clamped at voltage level D TH . 
         [0056]    In response to voltage V COMP  increasing and crossing through voltage level D TH  at time t 0 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60  and causes the signal at Q output terminal  62 , i.e., output terminal  18 G, to transition to a logic high voltage level. It should be noted that Q output terminal  62  of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at Q output terminal  62  serves as a pulse signal DUTY_ 10  that is transmitted to the input terminal of drive circuit  12 . 
         [0057]    The logic high voltage at output terminal  62  turns on transistor  106 , which sets voltage V RPM1  at input terminal  18 E to a voltage substantially equal to voltage V T . In addition, latch  60  generates a logic low voltage at output terminal  64  which turns off transistor  66 . Current source  70  sources a current I B  which charges capacitor  68  such that voltage V RPM  at input terminal  18 C, i.e., at the noninverting input terminal of comparator  50 , increases at a rate of approximately I B /C 68  volts per second. Thus, voltage V RPM  at the noninverting input terminal of comparator  50  is a ramp signal having a slope of approximately I B /C 68 . 
         [0058]    At time t 1 , voltage V COMP  crosses through the voltage level of voltage V RPM  and after time t 1  becomes less than voltage V RPM . In response to voltage V COMP  becoming less than voltage V RPM  and the logic low voltage level at the set input terminal of latch  60 , a logic low voltage level appears at output terminal  62 , which turns off transistor  106 . Current source  110  sources a current I T  which charges capacitor  108  such that voltage V RPM1  at input terminal  18 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 108  volts per second. Thus, voltage V RPM1  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 0  to approximately time t 1 , a ramp signal from approximately time t 1  to approximately time t 2  having a negative slope of I T /C 108 , and a substantially constant voltage signal from approximately time t 2  to approximately time t 3 . Pulse signal DUTY_ 10  appearing at output terminal  62  transitions to a logic low voltage level at time t 1 . The duration of pulse signal DUTY_ 10  being at a logic high voltage is substantially equal to the duration of the ramp portion of voltage V RPM . The duration of pulse signal DUTY_ 10  being at a logic low voltage is substantially equal to the sum of the time for the ramp portion of voltage V RPM1  and the time at which voltage V RPM1  is at voltage level D TH . 
         [0059]    Between times t 1  and t 2 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output terminal, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at Q output terminal  62 , of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus voltage V RPM  at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is charged to a voltage substantially equal to voltage V B . Because voltage V RPM  is less than voltage D TH  between times t 1  and t 2 , comparator  50  generates a logic low voltage at output terminal  54 . In response to voltage V COMP  increasing and crossing through voltage level D TH  at time t 3 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60 . In response to the logic high voltage at the set input terminal of latch  60 , the signal at Q output terminal  62  transitions to a logic high voltage level. Accordingly, pulse signal DUTY_ 10  transitions to a logic high voltage level. As noted above, Q output terminal  62  of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at Q output terminal  62  serves as a pulse signal DUTY_ 10  that is transmitted to the input terminal of drive circuit  12 . 
         [0060]    In response to voltage V RPM1  decreasing and becoming less to voltage D TH  at time t 2 , diode  116  turns on, which clamps voltage V RPM1  at a voltage substantially equal to voltage D TH . It should be noted that voltage V RPM1  is clamped at a voltage level substantially equal to voltage D TH  less the voltage across diode  116 . 
         [0061]    From about time t 2  to about time t 3 , current source  110  sources a current I T  which discharges capacitor  108 . At about time t 3 , the voltage at the inverting input of comparator  52  becomes less that the voltage at its noninverting input, which causes comparator  52  to generate a logic high voltage at output  56 . In response to the logic high voltage, latch  60  generates a logic high voltage at output  62 , which turns on transistor  106  and causes voltage V RPM1  to transistor to voltage level V T . In addition, latch  60  generates a logic low voltage at output  64  which turns off transistor  66 . In response to transistor  66  being off, current source  70  sources a current I B  which charges capacitor  68  such that voltage V RPM  at input terminal  18 C, i.e., at the noninverting input terminal of comparator  50 , increases at a rate of approximately I B /C 68  volts per second. Thus, voltage V RPM  at the noninverting input terminal of comparator  50  is a ramp signal having a slope of approximately I B /C 68 . 
         [0062]      FIG. 7  is a timing diagram  130  of pulse ramp modulator  102  operating in Discontinuous Conduction Mode (DCM) mode. In operation, input signals V COMP , D TH , V B , V RPM , and V RPM1 , V T  appear at input terminals  18 A,  18 B,  18 D,  18 C,  18 E, and  18 F, respectively, of pulse ramp modulator  18  (shown in  FIGS. 1 and 2 ). Current source  70  is connected between input terminals  18 D and  18 C. In response to the input signal at the control electrode of transistor  66  the current flowing through current source  70  sources a current I B  and in response to current I B  signal V RPM  appears at the noninverting input terminal of comparator  50 , i.e., input terminal  18 C. Current source  110  is connected between input terminals  18 E and  18 F and in response to the input signal at the control electrode of transistor  106  current source  110  sources a current I T  which is used to generate a voltage signal V RPM1  at the inverting input terminal of comparator  52 , i.e., input terminal  18 E.  FIG. 7  is a timing diagram showing signals V COMP , V B , D TH , V RPM , V RPM1 , V T , and pulse signal DUTY_ 150 . Before time t 0 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output terminal, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at the Q output terminal, of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus voltage V RPM  at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is charged to a voltage substantially equal to voltage V B . Because voltage V B  is less than voltage V COMP  before time t 0 , comparator  50  generates a logic low voltage at output terminal  64 . As the time approaches time t 0  from a time before time t 0 , voltage V RPM1  is clamped at voltage level D TH . 
         [0063]    In response to voltage V COMP  increasing and crossing through voltage level D TH  at time t 0 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60 . In response to the logic high voltage at the set input terminal of latch  60 , the signal at Q output terminal  62 , i.e., output terminal  18 G, transitions to a logic high voltage level. It should be noted that Q output terminal  62  of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at Q output terminal  62  serves as a pulse signal DUTY_ 150  that is transmitted to the input terminal of drive circuit  12 . 
         [0064]    The logic high voltage at output terminal  62  triggers one shot  152 , which turns on transistor  106  for a predefined period, setting voltage V RPM1  at input terminal  18 E to a voltage substantially equal to voltage V T . It should be noted that timing diagram  130  is drawn under the assumption that the duration of one shot  152  is very short compared to the time between times t 0  and t 3 . Thus, signal V RPM1  shown in  FIG. 7  appears to decrease beginning at time t 0 . This assumption was not made with reference to  FIG. 5 . In addition, the logic high voltage at output terminal  62  causes latch  60  to generate a logic low voltage at output terminal  64  which turns off transistor  66 . Current source  70  sources a current I B  which charges capacitor  68  such that voltage V RPM  at input terminal  18 C, i.e., at the noninverting input terminal of comparator  50 , increases at a rate of approximately I B /C 68  volts per second. Thus, voltage V RPM  at the noninverting input terminal of comparator  50  is a ramp signal having a slope of I B /C 68 . 
         [0065]    At time t 1 , voltage V COMP  crosses through the voltage level of voltage V RPM  and after time t 1  becomes less than voltage V RPM . In response to voltage V COMP  becoming less than voltage V RPM , and the logic low voltage level at the set input terminal of latch  60 , a logic low voltage level appears at output terminal  62 , which turns off transistor  106 . Current source  110  sources a current I T  which charges capacitor  108  such that voltage V RPM1  at input terminal  18 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 108  volts per second. Thus, voltage V RPM1  at the noninverting input terminal of comparator  52  is a ramp signal from approximately time t 0  to approximately time t 2  having a negative slope of approximately I T /C 108  and a substantially constant voltage signal from approximately time t 2  to approximately time t 3 . Pulse signal DUTY_ 150  appearing at output terminal  62  transitions to a logic low voltage level at time t 1 . The duration of pulse signal DUTY_ 150  being at a logic high voltage is substantially equal to the duration of the ramp portion of voltage V RPM . The duration of pulse signal DUTY_ 150  being at a logic low voltage is substantially equal to the sum of the time for the ramp portion of voltage V RPM1  and the time at which voltage V RPM1  is at voltage level D TH . 
         [0066]    Between times t 0  and t 2 , a logic high voltage level appears at output terminal  64 , i.e., at the Qbar output terminal, of latch  60  and a logic low voltage level appears at output terminal  62 , i.e., at Q output terminal  62 , of latch  60 . The logic high voltage level at output terminal  64  appears at the gate terminal of transistor  66  and turns it on. Thus voltage V RPM  at input terminal  18 C, i.e., the noninverting input terminal of comparator  50 , is substantially equal to voltage V B  and capacitor  68  is charged to a voltage substantially equal to voltage V B . Because voltage V RPM  is less than voltage V COMP  between times t 1  and t 2 , comparator  50  generates a logic low voltage at output terminal  54 . In response to voltage V COMP  increasing and crossing through voltage level D TH  at time t 3 , comparator  52  generates a logic high voltage at its output, which signal is transferred via output terminal  56  to the set input terminal of latch  60 . In response to the logic high voltage at the set input terminal of latch  60 , the signal at Q output terminal  62  transitions to a logic high voltage level. As noted above, Q output terminal  62  of latch  60  serves as output terminal  18 G of ramp pulse modulator  18  and the signal at Q output terminal  62  serves as a pulse signal DUTY_ 150  that is transmitted to the input terminal of drive circuit  12 . 
         [0067]    In response to voltage V RPM1  decreasing and becoming less to voltage D TH  at time t 2 , diode  116  turns on, which clamps voltage V RPM1  at a voltage substantially equal to voltage D TH . It should be noted that voltage V RPM1  is clamped at a voltage level substantially equal to voltage D TH  less the voltage across diode  116 . 
         [0068]    From about time t 2  to about time t 3 , current source  110  sources a current I T  which discharges capacitor  108 . At about time t 3 , the voltage at the inverting input of comparator  52  becomes less that the voltage at its noninverting input, which causes comparator  52  to generate a logic high voltage at output  56 . In response to the logic high voltage, latch  60  generates a logic high voltage at output  62 , which turns on transistor  106  and causes voltage V RPM1  to transistor to voltage level V T . In addition, latch  60  generates a logic low voltage at output  64  which turns off transistor  66 . In response to transistor  66  being off, current source  70  sources a current I B  which charges capacitor  68  such that voltage V RPM  at input terminal  18 C, i.e., at the noninverting input terminal of comparator  50 , increases at a rate of approximately I B /C 68  volts per second. Thus, voltage V RPM  at the noninverting input terminal of comparator  50  is a ramp signal having a slope of approximately I B /C 68 . 
         [0069]    In response to voltage V COMP  becoming substantially equal to signal V RPM  at time t 1  in timing diagrams  115  ( FIG. 3 ),  120  ( FIG. 6 ),  130  ( FIG. 7 ) and at time t 2  in timing diagram  155  ( FIG. 5 ), signal V RPM  resets to its minimum. In response to voltage V COMP  becoming substantially equal to signal V RPM1 , signal V RPM  increases and signal V RPM1  sets to its maximum value. This inhibits signal V COMP  from re-triggering the turn on signal and thereby inhibiting the generation of a double pulse. 
         [0070]      FIG. 8  is a circuit schematic of a voltage regulator  200  in accordance with an embodiment of the present invention. Like voltage regulator  10 , voltage regulator  200  includes a drive circuit  12 , switching devices  14  and  16 , compensation circuit  20 , inductor  22 , summer  21 , current sense circuit  26 , load capacitor  28 , and load  30 . Voltage regulator  200  includes a constant-on-time (COT) modulator  202  instead of a pulse ramp modulator as shown in  FIG. 1 . Constant-on-time modulator  202  has input terminals  202 A,  202 B,  202 C,  202 D, and  202 E, and an output terminal  202 F. Similar to ramp pulse modulator  18  shown in  FIG. 1 , constant-on-time modulator  202  is configured to operate in response to a compensation signal and to generate a pulse signal DUTY_ 200 . Thus, the configuration of voltage regulator  200  is similar to that of voltage regulator  10 . 
         [0071]      FIG. 9  is a circuit schematic of constant-on-time modulator  202  in accordance with an embodiment of the present invention. Constant-on-time modulator  202  comprises a comparator  52  which has a noninverting input terminal, an inverting input terminal, and an output terminal  56 . The inverting input terminal of comparator  52  is coupled for receiving a constant-on-time modulation signal V COT1  and the noninverting input terminal is coupled for receiving compensation signal V COMP . The noninverting input terminal of comparator  52  serves as an input terminal  202 A. Output terminal  56  is connected to the set input terminal of latch  60 . The Q output terminal  62  of latch  60  is connected to the reset input terminal of latch  60  through a constant-on-time feedback network  204 . Constant-on-time feedback network  204  has an input terminal  206  and an output terminal  208 , where input terminal  206  is connected to output terminal  62  of latch  60 . Output terminal  208  is connected to the reset input terminal of latch  60  wherein the connection forms input terminal  202 C. By way of example, constant-on-time feedback network  204  may be comprised of a one shot coupled to a timer, wherein input terminal  206  serves as the input terminal of the one shot and output terminal  208  serves as the output terminal of the timer. 
         [0072]    In addition, Q output terminal  62  of latch  60  is connected to a transistor  256 , which has a control electrode and a pair of current carrying electrodes. By way of example the control electrode is a gate electrode or gate terminal and the current carrying electrodes include a source electrode or terminal and a drain electrode or terminal. The source terminal of transistor  256  is commonly connected to a terminal of capacitor  258  and to the inverting input terminal of comparator  52  to form a node that can serve as input terminal  202 E. A constant-on-time modulation signal V COT1  appears at the inverting input terminal of comparator  52 . The drain terminal of transistor  256  is connected to the other terminal of capacitor  258  to form a node that may serve as input terminal  202 D. A current source  206  is connected between input terminals  202 E and  202 D and a voltage source  112  is connected to input terminal  202 D. Transistor  256 , capacitor  258 , and current source  260  may be referred to as a ramp generation circuit  261 . A diode  262  has a cathode connected to input terminal  202 E and an anode that serves as input terminal  202 B. A voltage source  114  is coupled to input terminal  202 B. Voltage source  112  provides a voltage V T  and voltage source  114  provides a voltage D TH . 
         [0073]    Output terminal  62  of latch  60 , input terminal  206  of constant-on-time feedback network  204 , and the gate electrode of transistor  256  form output terminal  202 F, which is connected to the input terminal of drive circuit  12  (shown in  FIG. 8 ). 
         [0074]    In operation, input signal V COMP  is coupled to input terminal  202 A and voltage V COT1  is formed at terminal  202 E of constant-on-time modulator  202  (shown in  FIGS. 8 and 9 ).  FIG. 10  is a timing diagram  212  showing signals V COMP , D TH , impulse signal COT CLK  that appears at input terminal  202 C, signal V COT1  that appears at input terminal  202 E, and pulse signal DUTY_ 200  that appears at output terminal  202 F. Referring now to  FIGS. 9 and 10 , before time t 0  voltage V COMP  is less than voltage V COT1 , voltage V COT1  approaches voltage level D TH , and the voltage at output  62  is at a logic low voltage level. Thus, transistor  256  is off. In response to compensation signal V COMP  being substantially equal to voltage D TH  at time t 0 , comparator  52  generates a logic high voltage at output  56 , which is latched by latch  60  to output  62 . Thus, pulse signal DUTY_ 200  transitions to a logic high voltage level. The logic high voltage at output  62  appears at the gate electrode of transistor  256  and turns it on, which causes voltage V COT1  to transition to voltage level V T . 
         [0075]    At about time t 1 , the logic high voltage at output  62  triggers the one shot of constant-on-time modulator  204 , which generates an impulse signal COT CLK . In response to impulse signal COT CLK  at input  202 C, latch  60  generates logic low output signal at output  62 . The logic low output voltage at output  62  turns off transistor  256 . Current source  260  sources a current I T  which charges capacitor  258  such that voltage V COT1  at input terminal  202 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 258  volts per second. Thus, voltage V COT1  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 0  to approximately time t 1  and a ramp signal from approximately time t 1  to approximately time t 2  having a negative slope of I T /C 258 , where I T  is the current sourced by current source  260  and C 258  is the capacitance value of capacitor  258 . Pulse signal DUTY_ 200  appearing at output terminal  62  transitions to a logic low voltage level at time t 1 . The duration of pulse signal DUTY_ 200  being at a logic high voltage is substantially equal to the duration of the constant voltage portion of voltage V COT1 . The duration of pulse signal DUTY_ 200  being at a logic low voltage is substantially equal to the ramp portion of voltage V COT1 . 
         [0076]    It should be noted that timing diagram  212  is drawn under the assumption that the duration of the one shot is very short compared to the time between times t 0  and t 2 . Thus, signal V COT1  shown in  FIG. 10  appears to decrease beginning at time t 1 . 
         [0077]    At time t 2  and in response to compensation signal V COMP  being substantially equal to voltage D TH , comparator  52  generates a logic high voltage at output  56 , which is latched by latch  60  to output  62 . Thus, pulse signal DUTY_ 200  transitions to a logic high voltage level. The logic high voltage at output  62  appears at the gate electrode of transistor  256  and turns it on, which causes voltage V COT1  to transition to voltage level V T . 
         [0078]    At about time t 3 , the logic high voltage at output  62  triggers the one shot of constant-on-time modulator  204 , which generates an impulse signal COT CLK . In response to impulse signal COT CLK  at input  202 C, latch  60  generates logic low output signal at output  62 . The logic low output voltage at output  62  turns off transistor  256 . Current source  260  sources a current I T  which charges capacitor  258  such that voltage V COT1  at input terminal  202 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 258  volts per second. Thus, voltage V COT1  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 2  to approximately time t 3  and a ramp signal from approximately time t 3  to approximately time t 4  having a negative slope of I T /C 258 . Pulse signal DUTY_ 200  appearing at output terminal  62  transitions to a logic low voltage level at time t 3 . The duration of pulse signal DUTY_ 200  being at a logic high voltage is substantially equal to the duration of the constant voltage portion of voltage V COT1 . The duration of pulse signal DUTY_ 200  being at a logic low voltage is substantially equal to the ramp portion of voltage V COT1 . 
         [0079]    At time t 4  and in response to compensation signal V COMP  being substantially equal to voltage D TH , comparator  52  generates a logic high voltage at output  56 , which is latched by latch  60  to output  62 . Thus, pulse signal DUTY_ 200  transitions to a logic high voltage level. The logic high voltage at output  62  appears at the gate electrode of transistor  256  and turns it on, which causes voltage V COT1  to transition to voltage level V T . 
         [0080]      FIG. 11  is a circuit schematic of constant-on-time modulator  300  in accordance with an embodiment of the present invention. It should be noted that the input/output configuration of constant-on-time modulator  300  may be the same as that of constant-on-time modulator  202 . Thus, constant-on-time modulator  202  can be replaced by constant-on-time modulator  300 . It should be further noted that the operation of voltage regulator  200  described with reference to  FIG. 8  may also apply to embodiments in which constant-on-time modulator  300  replaces constant-on-time modulator  202 . Constant-on-time modulator  300  comprises comparator  52 , latch  60 , constant-on-time regulator  204 , transistor  256 , capacitor  258 , and diode  262  as described with reference to  FIG. 9 . In addition, constant-on-time modulator  300  includes a one shot  302  connected between output terminal  62  and the gate of transistor  256 . 
         [0081]    A voltage source  112  is connected to input terminal  202 D, a voltage source  114  is connected to input terminal  202 B, and a current source  260  is connected between input terminals  202 E and  202 D. 
         [0082]    Output terminal  202 F is connected to the input terminal of drive circuit  12  (shown in  FIG. 4 ). 
         [0083]    In operation, input signal V COMP  is coupled to input terminal  202 A and voltage V COT2  is formed at terminal  202 E of constant-on-time modulator  202  (shown in  FIGS. 8 and 11 ).  FIG. 12  is a timing diagram  300  showing signals V COMP , D TH , impulse signal COT CLK  that appears at input terminal  202 C, ramp signal V COT2  that appears at input terminal  202 E, and pulse signal DUTY_ 300  that appears at output terminal  202 F. Referring now to  FIGS. 11 and 12 , before time t 0  voltage V COMP  is less than voltage V COT2 , voltage V COT2  approaches voltage level D TH , and the voltage at output  62  is at a logic low voltage level. Thus, transistor  256  is off. In response to compensation signal V COMP  Wow being substantially equal to voltage D TH  at time t 0 , comparator  52  generates a logic high voltage at output  56 , which is latched by latch  60  to output  62 . Thus, pulse signal DUTY_ 300  transitions to a logic high voltage level. 
         [0084]    The logic high voltage level at output terminal  62  appears at the input terminal of one shot  302  and triggers one shot  302 . Thus, a logic high voltage appears at the control electrode of transistor  256 , turning on transistor  256 , which sets voltage V COT2  at input node  202 E to a voltage substantially equal to voltage V T . 
         [0085]    One shot  302  creates at logic high voltage at the control electrode of transistor  106  for a fixed period of time. This fixed time period ends at time t 1 . Thus, at time t 1  one shot  302  reverts to its stable state which turns off transistor  106 . Current source  260  sources a current I T  which charges capacitor  258  such that the voltage at input terminal  202 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 258  volts per second. Thus, the voltage V COT1  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 0  to approximately time t 1  and is a ramp signal from approximately time t 1  to approximately time t 3  and has a negative slope of I T /C 108 . 
         [0086]    At about time t 2 , the logic high voltage at output  62  triggers the one shot of constant-on-time modulator  204 , which generates an impulse signal COT CLK . In response to impulse signal COT CLK  at input  202 C, latch  60  generates logic low output signal at output  62 . Thus, pulse signal DUTY_ 300  transitions to a logic low voltage level at time t 2 . Voltage V COT2  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 0  to approximately time t 1  and a ramp signal from approximately time t 1  to approximately time t 3  having a negative slope of I T /C 258 . 
         [0087]    In response to compensation signal V COMP  being substantially equal to voltage D TH  at time t 3 , comparator  52  generates a logic high voltage at output  56 , which is latched by latch  60  to output  62 . Thus, pulse signal DUTY_ 300  transitions to a logic high voltage level. 
         [0088]    The logic high voltage level at output terminal  62  appears at the input terminal of one shot  302  and triggers one shot  302 . Thus, a logic high voltage appears at the control electrode of transistor  256 , turning on transistor  256 , which sets voltage V COT2  at input node  202 E to a voltage substantially equal to voltage V T . 
         [0089]    One shot  302  creates at logic high voltage at the control electrode of transistor  106  for a fixed period of time. This fixed time period ends at time t 4 . Thus, at time t 4  one shot  302  reverts to its stable state which turns off transistor  106 . Current source  260  sources a current I T  which charges capacitor  258  such that the voltage at input terminal  202 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 258  volts per second. Thus, the voltage V COT2  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 3  to approximately time t 4  and is a ramp signal from approximately time t 1  to approximately time t 4  and has a negative slope of I T /C 108 . 
         [0090]    At about time t 5 , the logic high voltage at output  62  triggers the one shot of constant-on-time modulator  204 , which generates an impulse signal COT CLK . In response to impulse signal COT CLK  at input  202 C, latch  60  generates a logic low output signal at output  62 . Thus, pulse signal DUTY_ 300  transitions to a logic low voltage level at time t 5 . Voltage V COT2  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 3  to approximately time t 4  and a ramp signal from approximately time t 4  to approximately time t 6  having a negative slope of I T /C 258 . 
         [0091]    In response to compensation signal V COMP  being substantially equal to voltage D TH  at time t 6 , comparator  52  generates a logic high voltage at output  56 , which is latched by latch  60  to output  62 . Thus, pulse signal DUTY_ 300  transitions to a logic high voltage level. 
         [0092]    The logic high voltage level at output terminal  62  appears at the input terminal of one shot  302  and triggers one shot  302 . Thus, a logic high voltage appears at the control electrode of transistor  256 , turning on transistor  256 , which sets voltage V COT2  at input node  202 E to a voltage substantially equal to voltage V T . 
         [0093]    One shot  302  creates at logic high voltage at the control electrode of transistor  106  for a fixed period of time. This fixed time period ends at time t 7 . Thus, at time t 7  one shot  302  reverts to its stable state which turns off transistor  106 . Current source  260  sources a current I T  which charges capacitor  258  such that the voltage at input terminal  202 E, i.e., at the inverting input terminal of comparator  52 , decreases at a rate of approximately I T /C 258  volts per second. Thus, the voltage V COT2  at the noninverting input terminal of comparator  52  is a substantially constant voltage from approximately time t 6  to approximately time t 7  and is a ramp signal beginning at approximately time t 7 . 
         [0094]      FIG. 13  is a timing diagram  350  of pulse ramp modulator  202  operating in Discontinuous Conduction Mode (DCM). The operation is similar to that described for constant-on-time modulator  202  with reference to  FIGS. 9 and 10 , except that at time t 2  in timing diagram  350  diode  262  turns on and clamps signal V COT2  at voltage level D TH . In response to signal V COT2  becoming less than voltage D TH . It should be appreciated that signal V COT2  may be clamped at a voltage substantially equal to a diode voltage drop less than voltage D TH . Similar to the operation shown in timing diagram  212  of  FIG. 10 , in response to compensation signal V COMP  being substantially equal to voltage D TH  at time t 2 , comparator  52  generates a logic high voltage at output  56 , which is latched by latch  60  to output  62 . Thus, pulse signal DUTY_ 200  transitions to a logic high voltage level. The logic high voltage at output  62  appears at the gate electrode of transistor  256  and turns it on, which causes voltage V COT1  to transition to voltage level V T . 
         [0095]      FIG. 14  is a timing diagram  400  of pulse ramp modulator  300  operating in Discontinuous Conduction Mode (DCM). The operation is similar to that described for pulse ramp modulator  300  with reference to  FIGS. 11 and 12 , except that in response to pulse signal DUTY_ 300  transitioning to a logic high state, signal V COT2  transitions to voltage level V T  and begins to decrease at a rate of I T /C 258  volts per second. It should be noted that timing diagram  400  is drawn under the assumption that the duration of one shot  302  is very short compared to the time between times t 0  and t 3 . Thus, signal V COT2  shown in  FIG. 14  appears to decrease beginning at time t 0 . 
         [0096]    By now it should be appreciated that a switching power supply controller and a method for controlling the switching power supply have been provided. An advantage of embodiments in accordance with the present invention is that they mitigate stability issues that arise from signal delays and phase lag within the switching power supplies. In addition, they mitigate the effects of sub-harmonic oscillations within the system. Another advantage is the power switching supplies can operate at a lower switching frequency under light load conditions. 
         [0097]    Although specific embodiments have been disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is intended that the invention encompass all such modifications and variations as fall within the scope of the appended claims.