Abstract:
In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A ploysilicon layer is formed over the silicon germanium layer and is polished. The ploysilicon layer over the first work function metal layer is thicker than the ploysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the ploysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

Description:
BACKGROUND 
       [0001]    The etching rate of conductive material (e.g., polysilicon) over different p-diffusion and n-diffusion work metals is inherently different. When forming gate stacks this different etching rate results in over etching and exposure of the underlying metal for certain gate stacks and gate stacks that are notched and have flared profile. As semiconductor devices continue to be scaled to smaller dimensions even small amounts of notched or flared gate profiles will significantly hinder device performance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0002]    The features and advantages of the various embodiments will become apparent from the following detailed description in which: 
           [0003]      FIG. 1  illustrates an example substrate having N and P transistor regions formed therein, according to one embodiment; 
           [0004]      FIG. 2  illustrates the example substrate after a first gate stack layer is formed on the gate conducting layers, according to one embodiment; 
           [0005]      FIG. 3  illustrates the example substrate after a second gate stack layer is formed on the first gate stack layer and is polished, according to one embodiment; 
           [0006]      FIG. 4  illustrates the example substrate after a hard mask is formed and patterned over the diffusion fins, according to one embodiment; 
           [0007]      FIG. 5  illustrates the example substrate after the gate stack layers are etched to create gate stacks, according to one embodiment; 
           [0008]      FIG. 6  illustrates a cross sectional view of the gate stacks of  FIG. 5 , according to one embodiment. 
           [0009]      FIG. 7  illustrates the example substrate after a hard mask gate electrode pattern is formed and patterned that extends over the n-type metal gate layer and the p-type metal gate layer, according to one embodiment; 
           [0010]      FIG. 8  illustrates the example substrate after the gate stack layers are etched to create a gate electrode, according to one embodiment; 
           [0011]      FIG. 9  illustrates a cross sectional view of the gate electrode of  FIG. 8 , according to one embodiment; 
           [0012]      FIG. 10  illustrates cross sectional views of the substrate from varying distances away from the n-type fin, according to one embodiment; and 
           [0013]      FIG. 11  illustrates cross sectional views of the substrate from varying distances away from the p-type fin, according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    In order to reduce or eliminate the effect of differential etch rates on formation of gate stacks, gate stacks may be formed from more than one material where the thicknesses of the materials are selected to account for the different etch rates. Materials having superior and desirable etch qualities may be used for one of the layers to provide more vertically aligned gate profiles. 
         [0015]      FIG. 1  illustrates an example substrate having N and P transistor regions formed therein. The substrate (e.g., silicon) includes fins  100 ,  110  formed therein separated by an electrically insulating layer  120  (e.g., oxide) to provide shallow trench isolation (STI). The fin  100  may be an n-diffusion fin and the fin  110  may be a p-diffusion fin. A dielectric layer (e.g., oxide, nitride, high dielectric constant (K) material)  130  is formed on the substrate (fins  100 ,  110  and insulating layer  120 ). A conductive gate layer (e.g., metal) is created on the dielectric layer  130 . The metal gate layer may include an n-type metal gate layer  140  over the n-diffusion fin  100  and p-type metal gate layer  145  over the over the p-diffusion fin  110 . The n-type metal gate layer  140  and the p-type metal gate layer  145  may have different thicknesses (e.g., p-type metal gate layer  145  thicker). The metal gate layers  140 ,  145  may be formed of different materials or one layer (e.g., p-type metal gate layer  145 ) may include an additional layer (e.g., material) on top of an initial layer. The diffusion fins  100 ,  110  and the various layers  120 ,  130 ,  140 ,  145  may be formed through any number of known processes. 
         [0016]      FIG. 2  illustrates the example substrate after a first gate stack layer (e.g., Si—Ge)  150  is formed on the metal gate layers  140 ,  145 . The first gate stack layer  150  may be formed through any number of known processes. 
         [0017]      FIG. 3  illustrates the example substrate after a second gate stack layer (e.g., polysilicon)  160  is formed on the first gate stack layer  150  and is polished. The second gate stack layer  160  may be formed having a substantial thickness to ensure that after polishing the top surface is flat (planarized). After polishing the thickness of the second gate stack layer  160  is different over the metal gate layers  140 ,  145  (e.g., thicker over the n-type metal gate layer  140 ). The second gate stack layer  160  may be formed and polished through any number of known processes. 
         [0018]    The thicknesses of the first gate stack layer  150  is selected to account for the different etch rates of the first gate stack layer  150  over the n-type metal gate layer  140  (n-diffusion fin  100 ) and the p-type metal gate layer  145  (p-diffusion fin  110 ), the difference in the thickness of the metal gate layers  140 ,  145  which impacts the difference in the thickness of the second gate stack layer  160  over the n-type metal gate layer  140  and the p-type metal gate layer  145 , and the etch rate of the second gate stack layer  160 . The thickness of the second gate stack layer  160  is selected based on the thickness of the first gate stack layer  150  and the desired thickness of the gate stacks. 
         [0019]    The difference in thickness of the metal gate layers  140 ,  145  and the thickness of the first gate stack layer  150  can be selected to dictate the relative exposure of the metal gate layers  140 ,  145 . The etching of the gate stack layers  150 ,  160  and exposure of the metal gate layers  140 ,  145  should ideally complete at the same (or substantially the same) time so over etching of a metal gate layer (e.g., n-type metal gate layer  140 ) and exposure of the insulating layer  130  doesn&#39;t occur. 
         [0020]      FIG. 4  illustrates the example substrate after a hard mask n-type gate pattern  170  and a hard mask p-type gate pattern  175  is formed and patterned over the diffusion fins  100 ,  110  respectively. The hard mask gate patterns  170 ,  175  may be patterned through any number of known processes. For example, a resist layer may be patterned (e.g., lithography) over a hard mask layer and the hard mask layer may be etched using the resist pattern and then the resist layer may be removed. 
         [0021]      FIG. 5  illustrates the example substrate after the gate stack layers  150 ,  160  are etched to create an n-type gate stack  200  over the n-type metal gate layer  140  and a p-type gate stack  210  over the p-type metal gate layer  145 . The overall height that the gate stacks  200 ,  210  protrude from the substrate is the same (or substantially the same) while the thicknesses of the gate stacks is different (e.g., gate stack  200  is thicker). The first gate stack layer  150  has the same (or substantially the same) thickness in the two gate stacks  200 ,  210  while the second gate stack layer  160  has a different thickness in the two gate stacks  200 ,  210 . The gate stack layers  150 ,  160  may be etched through any number of known processes. 
         [0022]    As the thicknesses of the second gate stack layer  160  are different over the different metal gate layers  140 ,  145  and the etch rates are the same (or substantially the same), the etching of a first portion (e.g., over the P-type metal layer  145 ) of the second gate stack layer  160  will complete prior to a second portion (e.g., over the n-type metal layer  140 ) the etching of the first gate stack layer  150  will begin earlier for the first portion. As the etch rates for the first gate stack layer  150  are different but the thicknesses are the same (or substantially the same), the etching of a first portion (over the n-type metal layer  140 ) of the first gate stack layer  160  will take less time than the etching of a second portion (e.g., over the P-type metal layer  145 ). 
         [0023]    The overall etching of the gate stacks  200 ,  210  based on the thicknesses of the gate stack layers  150 ,  160  and the etching rates of the first gate stack layer  150  should complete at the same (or substantially the same) time so that the metal gate layers  140 ,  145  are exposed at relatively the same time. The etch completion/metal gate layer  140 ,  145  exposure at the same time ensures that the metal gate layers  140 ,  145  are not over etched and the dielectric layer  130  is not exposed. Utilizing SiGe as the first gate layer  150  reduces charge induced notching and improves charge conductivity (relative to poly silicon) due to the inherent properties of the SiGe. 
         [0024]      FIG. 6  illustrates a cross-sectional view through each of the gate stacks  200 ,  210 . The n-type gate stack  200  includes the n-type fin  100 , the n-type metal layer  140 , the first gate stack layer  150  and the second gate stack layer  160 . The p-type gate stack  210  includes the n-type fin  110 , the p-type metal layer  145 , the first gate stack layer  150  and the second gate stack layer  160 . The p-type metal layer  145  is thicker than the n-type metal layer  140 , the first gate stack layer  150  is the same thickness on each stack  200 ,  210  but has a relative height (height from top of substrate) that is higher for the p-type gate stack  210 , the second gate stack layer  160  is thicker for the n-type gate stack  200 , and the overall relative height of the gate stacks  200 ,  210  is the same. 
         [0025]      FIGS. 5 and 6  illustrated gate electrodes  200 ,  210  being formed over each of the fins  100 ,  110  respectively. It is possible that a gate electrode will be formed that extends over more then one fin to create a device utilizing more than one transistor (e.g., SRAM cell). 
         [0026]      FIG. 7  illustrates the example substrate after a hard mask gate electrode pattern  180  is formed and patterned that extends over the diffusion fins  100 ,  110 . The hard mask gate electrode pattern  180  may be patterned through any number of known processes. 
         [0027]      FIG. 8  illustrates the example substrate after the gate stack layers  150 ,  160  are etched to create a gate electrode  220  that extends over the n-type metal gate layer  140  and the p-type metal gate layer  145 . 
         [0028]      FIG. 9  illustrates a cross sectional view of the gate electrode  220 . The cross sectional view more easily illustrates the relative heights and thicknesses of the various layers. The cross sectional view also includes marks indicating cross sectional views of the substrate that will be illustrated in  FIGS. 10 and 11 . 
         [0029]      FIG. 10  illustrates two cross sectional views of the substrate from varying distances away from the fin  100 . View A-A illustrates how the first gate layer (e.g., SiGe)  150  will extend above the fin  100 . The use of SiGe provides better etching properties at the corners of the fin  100  to reduce notching and provide a vertical (or substantially vertical) gate stack at this critical point. View B-B illustrates how the first gate layer  150  is below the level of the fin as you proceed away from the fin  100 . 
         [0030]      FIG. 11  illustrates two cross sectional views of the substrate from varying distances away from the fin  110 . 
         [0031]    While the embodiments described above focused on formation of dual layer gate stacks for non-planar transistors, it is not limited thereto. Rather, the dual layer gate stack could be utilized for planar transistors as well. Furthermore, the embodiments were described with respect to gate stacks having two layers but are not limited thereto. Rather, more than two layers can be used. 
         [0032]    Moreover, the embodiments were described with respect to the gate stack having the same thickness first gate stack layer over the n and p type metal gate layers and different thickness second layers over the n and p type metal gate layers, but are not limited thereto. Rather, the first gate stack layer could be polished so the thickness is different over the n and p type metal gate layers with the overall thickness of the first gate stack layer determined based on the difference in the thickness of the metal gate stack layers and the difference in the etch rates of the first gate stack layer over the n and p type metal gate layers. The second gate stack layer could then be the same thickness over the n and p type metal gate layers with the thickness based on overall desired gate stack thickness. 
         [0033]    If the etch rate delta of the first gate stack layer over the n and p type metal gate layers is not linear, then tuning the thickness alone may be insufficient to obtain a desired gate height and the addition of second gate stack layer may be imperative. Due to certain integration requirements the total stack height plays a very critical role in fabrication process, especially when the device pitch size (measure of spacing between adjacent structures) becomes smaller. 
         [0034]    Although the disclosure has been illustrated by reference to specific embodiments, it will be apparent that the disclosure is not limited thereto as various changes and modifications may be made thereto without departing from the scope. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described therein is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment. 
         [0035]    The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.