Abstract:
A SEPIC converter with over-voltage protection includes a high-side inductor that connects a node V w  to a node V x . The node V x  is connected, in turn to ground by a power MOSFET. The node V x  is also connected to a node V y  by a first capacitor. The node V y  is connected to ground by a low-side inductor. A rectifier diode further connects the node V y  and a node V out  and an output capacitor is connected between the node V out  and ground. A PWM control circuit is connected to drive the power MOSFET. An over-voltage protection MOSFET connects an input supply to the PWM control circuit and the node V w . A comparator monitors the voltage of the input supply. If that voltage exceeds a predetermined value V ref  the comparator output causes the over-voltage protection MOSFET to disconnect the node V w  and the PWM control circuit from the input supply.

Description:
BACKGROUND OF THE INVENTION 
     Most DC to DC switching voltage regulators such as the Buck converter and boost converter are capable of only regulating a voltage above or below a given input but not capable of both step up and step down regulation. A SEPIC (single ended primary inductor converter) is a DC-DC converter which allows the output voltage to be greater than, less than, or equal to the input voltage. The output voltage of the SEPIC is controlled by the duty cycle of the control transistor. The largest advantage of a SEPIC over the buck-boost converter is a non-inverted output (positive voltage). SEPICs are useful in applications where the battery voltage can be above and below the regulator output voltage. For example, a single Lithium ion battery typically has an output voltage ranging from 4.2 Volts to 3 Volts. If the accompanying device requires 3.3 Volts, then the SEPIC would be effective since the battery voltage can be both above and below the regulator output voltage. Other advantages of SEPICs are input/output isolation and true shutdown mode: when the switch is turned off output drops to 0 V. 
     As shown in  FIG. 1  a prior art SEPIC converter  1  comprises a PWM control circuit  2 , N-channel power MOSFET  3  with intrinsic drain-to-source diode  4 , high-side inductor  5 , capacitor  6 , low-side inductor  7 , rectifier diode  8  and output capacitor  9  powering load  10 . Operation comprises repeatedly magnetizing inductor  5  whenever MOSFET  3  is in its ON and conducting state and transferring energy to output capacitor  9  and load  10  in alternating phases. 
     During operation, the node voltage Vx peaks at a voltage (V IN +V OUT ). The BV DSS  breakdown of MOSFET  3  and diode  4  must exceed this peak voltage with some reserve. 
     The converter as shown cannot survive an over-voltage condition because no means exists to stop the switching operation of MOSFET  3 . Instead of limiting the maximum input voltage, converter  1  continues to operate at any input voltage until the drain voltage on MOSFET  3  exceeds safe limits and damages the device. In addition to this inability to survive high input voltages, PWM controller  2  contains low-voltage control circuitry which cannot operate when powered directly from a high voltage input. 
     The circuit as shown also suffers from the lack of a true load disconnect. Current sensing is also problematic since there is no convenient means to detect the input current in inductor  5 . 
     What is needed is a SEPIC converter offering high-voltage operation up to some safe level below the rating of the power MOSFET, a means to inhibit switching operation under excessive input voltage conditions, the ability to disconnect the load from the input, and a means to detect the input current either to implement current mode control, to prevent over-current conditions, or ideally both. 
     SUMMARY OF THE INVENTION 
     The present invention provides a family of SEPIC converters that overcome the disadvantages of the prior art. A basic building block of this family is the generic SEPIC converter shown in  FIG. 1 . This converter includes a high-side inductor that connects a node V w  to a node V x . The node V x  is connected, in turn to ground by a power MOSFET. The node V x  is also connected to a node V y  by a first capacitor. The node V y  is connected to ground by a low-side inductor. A rectifier diode further connects the node V y  and a node V out  and an output capacitor is connected between the node V out  and ground. 
     A PWM control circuit is connected to drive the power MOSFET. The PWM control circuit turns the power MOSFET ON an OFF in a repeating pulse-width-modulation pattern. The duty cycle of the power MOSFET is varied in proportion to the voltage at the node V out  to maintain the output of the SEPIC converter within regulation. Whenever the power MOSFET is ON, current from the input supply magnetizes the high-side inductor. When the power MOSFET subsequently turns OFF, the energy stored in the magnetic field of the inductor is transferred to the output capacitor. A load connected over the output capacitor is powered in this fashion. 
     To this basic SEFIC topology just described, a first embodiment of the present invention adds circuitry for over-voltage protection. Specifically, this embodiment uses over-voltage protection MOSFET to connect the input supply to the PWM control circuit and the node V w . The over-voltage protection MOSFET is driven by the output of a comparator. The comparator is connected to monitor the difference between a predetermined reference voltage V ref  and the voltage of the input supply. If the voltage of the input supply exceeds the predetermined value V ref  the comparator output causes the over-voltage protection MOSFET to disconnect the node V w  and the PWM control circuit from the input supply. In this way, a SEPIC converter is provided that can survive input voltages that would otherwise damage the power MOSFET or PWM control circuit. 
     A second embodiment of the present invention provides a high-voltage SEPIC converter. For this embodiment (once again, based on the topology described above) a linear regulator (typically, an LDO) is used to supply current from the input supply to the PWM control circuit. In this way, the voltage applied to the PWM control circuit never exceeds the regulated output of the linear regulator and the SEPIC converter can survive input voltages that would otherwise damage the PWM control circuit. 
     A third embodiment of the present invention provides a high-voltage SEPIC with over-voltage protection. This embodiment includes all of the elements of the high-voltage SEPIC just described. To add over-voltage protection, an AND gate is added to drive the power MOSFET. The inputs to the AND gate are the output of the PWM control circuit and the output of a comparator. The comparator is connected to monitor the difference between a predetermined reference voltage V ref  and the voltage of the input supply. If the voltage of the input supply exceeds the predetermined value V ref  the comparator output causes the AND gate to disable the output of the PWM control circuit. In turn, this causes the power MOSFET to turn OFF. 
     By shutting down the power MOSFET under over-voltage conditions, the SEPIC converter ensures that the drain of the power MOSFET never exceeds the voltage of the input supply. In this way, the power MOSFET is protected in over-voltage conditions. At the same time, the PWM circuit is protected by the LDO as described for the previous embodiment. 
     A fourth embodiment of the present invention provides a high-voltage SEPIC with over-voltage protection and load disconnect. This embodiment includes all of the elements of the high-voltage SEPIC with over-voltage protection just described. To add load disconnect, current sensing and load disconnect circuitry is added to monitor the current flowing from the input supply to the high-side inductor. The current sensing and load disconnect circuitry includes a P-channel MOSFET connected between the input supply and the high-side inductor. During normal operation, this P-channel device is biased to allow current to pass to the high-side inductor. 
     The current through the P-channel MOSFET is monitored using a current mirroring technique. This produces an over-current signal that is connected as an input to the AND gate (in this implementation the AND gate has three inputs). If current flowing through the P-channel MOSFET exceeds a predetermined value, the over-current signal causes the AND gate to disable the output of the PWM control circuit. In turn, this causes the power MOSFET to turn OFF and protects the SEPIC converter from over-current damage. The use of a P-channel MOSFET to monitor the current to the high-side inductor also means that, by biasing that MOSFET to be OFF, the SEPIC converter may be disconnected from the input supply. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic of a conventional SEPIC converter (Prior Art). 
         FIG. 2  is a schematic of a SEPIC converter with series over-voltage protection as provided by an embodiment of the present invention. 
         FIG. 3  is a schematic of a high voltage SEPIC without over-voltage protection as provided by an embodiment of the present invention. 
         FIG. 4  is a schematic of a high voltage SEPIC with over-voltage protection as provided by an embodiment of the present invention. 
         FIG. 5  is a schematic of a high voltage SEPIC with over-voltage protection, current sensing, over-current protection and true load disconnect as provided by an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Over-Voltage-Protected SEPIC 
     One means to extend the voltage range of the SEPIC converter is to utilize an over-voltage protection, i.e. OVP, circuit that disconnects the converter from the input in the event the input voltage exceeds a pre-specified value. In converter  20  of  FIG. 2 , SEPIC converter  21  is protected by P-channel MOSFET  31  controller by comparator  33  which compares the input voltage V IN  to a reference voltage V ref . Reference voltage  34  may be implemented using a bandgap reference, Zener diode, a series of forward biased diodes or any other well known voltage reference technique, or a scaled multiple of said voltage. P-channel MOSFET  31  includes reverse-biased intrinsic P-N diode  32  with its anode tied to V IN  and its cathode connected to the input to converter  21 . 
     SEPIC converter  21  comprises a PWM control circuit  22 , N-channel power MOSFET  23  with intrinsic drain-to-source diode  24 , high-side inductor  25 , capacitor  26 , low-side inductor  27 , rectifier diode  28  and output capacitor  29  powering load  30 . Operation comprises repeatedly magnetizing inductor  25  whenever MOSFET  23  is in its ON and conducting state and transferring energy to output capacitor  29  and load  30  in alternating phases. 
     Whenever V IN  is below V ref  the gate of P-channel  31  is pulled down by comparator  33  and P-channel  31  is turned on. The maximum gate to source voltage V GSP  cannot exceed the maximum gate rating of the P-channel  31 , i.e. V GSP &lt;|V IN −V GP |. Accordingly, the V cc  input of SEPIC converter  21  is connected to V IN  and the converter is operating. Whenever V IN  is above V ref  an over-voltage condition has occurred and the input V cc  of SEPIC converter  21  is disconnected from V IN  and allowed to float or alternatively is grounded. The V ref  voltage determines the maximum value of V cc  powering SEPIC converter  21  and PWM controller  22 . PWM controller must therefore utilize devices capable of operating at the maximum allowed V cc  voltage, i.e. V ref . During operation, the node voltage V x  peaks at a voltage (V IN +V OUT )&lt;(V ref +V OUT ). The BV DSS  breakdown of MOSFET  23  and diode  24  must exceed this peak voltage with some guardband. 
     As such OVP protection MOSFET  31  protects SEPIC converter  21  but must be rated for the maximum V IN  input voltage. The devices used in PWM control circuit  22  must support the same voltage rating. An even higher voltage is imposed on node V x  and across diode  24  of N-channel MOSFET  23 . Implementation  20  therefore requires two high voltage MOSFETs, N-channel  23  and P-channel  31  with respective on-resistances R DSN  and R DSP , to implement an over-voltage protected SEPIC converter. The current capability of the converter is adversely affected by the higher on-resistance of such high voltage devices, i.e. R total =(R DSP +R DSN ). While the approach of circuit  20  may be used for any input voltage, practically these considerations limit the input voltage to the 12V to 18V range, especially in implementing PWM controller  22 . 
     Another benefit of OVP protected SEPIC converter  20  is its ability to implement the load-disconnect function, simply by turning OFF P-channel MOSFET  31  by biasing its gate to its source potential, i.e. where V GP =V IN . 
     High-Voltage SEPIC 
     Another method to extend the voltage range of the SEPIC converter is to utilize a high voltage low-drop-out linear regulator, or LDO, to protect the control circuitry from high voltages up to a pre-specified value. In SEPIC converter  50  of  FIG. 3  linear regulator  60  limits the maximum voltage imposed on PWM controller  51  to some predefined maximum voltage V cc , typically 3V or 5V, so that the devices utilized within PWM circuit  51  may comprise only low-voltage devices. 
     SEPIC converter  50  includes a PWM control circuit  51 , N-channel power MOSFET  52  with intrinsic drain-to-source diode  53 , high-side inductor  54 , capacitor  55 , low-side inductor  56 , rectifier diode  57  and output capacitor  58  powering load  59 . Operation comprises repeatedly magnetizing inductor  54  whenever MOSFET  52  is in its ON and conducting state and transferring energy to output capacitor  58  and load  59  in alternating phases. 
     As illustrated linear regulator  60  is preferably a low-drop-out type, e.g. with a series voltage drop under 200 mV, to extend the operating voltage range of converter  50  to lower input voltage V IN . The design of low drop-out linear regulators is well known to one skilled in the art of power electronics. Input and output capacitors  61  and  62  acts as filter capacitors and prevent LDO  60  from oscillating. The benefit of the smaller sized devices is the silicon die area may be reduced compared to the area occupied by high voltage PWM circuit  22  of aforementioned SEPIC converter circuit  20 . 
     While LDO  60  protects PWM controller  51  from high input voltages it does not limit the voltage on the remainder of the converter circuit or on MOSFET  52 . Lacking any over-voltage protection circuitry and series disconnect switch, the N-channel MOSFET  52  and diode  53  must be rated to operate up to the maximum input voltage with adequate guard-banding to avoid accidental or momentary avalanche breakdown. During operation the peak V x  voltage is typically (V IN +V OUT ). 
     Since only one high voltage MOSFET is present in converter  50 , the current capability of the converter is improved in comparison to converter  20 , where the total MOSFET resistance is only that of MOSFET  52 , i.e. where R total =(R DSN ). Without over-voltage protection however, the breakdown voltage of MOSFET  52  must be higher than (V IN +V OUT ). In this approach, the breakdown voltage guard-band of MOSFET  52  increases with increasing input voltage. While the approach of circuit  50  may be used for any input voltage, practically these considerations preferably limit the input voltage to the 18V to 30V range, beyond which the need for excessive voltage guard-banding makes MOSFET  52  unnecessarily large to compensate for its higher resistance. 
     Without OVP protection, one disadvantage of high-voltage SEPIC converter  50  is its inability to offer the load-disconnect function. As a result the circuit provides no means to disconnect load  59  from V IN . 
     High-Voltage SEPIC with Over-Voltage Protection 
     An improved SEPIC converter combines the over-voltage protection features of converter  20  with the high voltage capability of converter  50 . The resulting OVP protected high-voltage SEPIC converter is illustrated in circuit  69  of  FIG. 4 . As such, an over-voltage protection circuit  83  in conjunction with a high voltage MOSFET  72  protects the power circuitry while a linear regulator protects the PWM control circuit  70  from high voltages. Unlike in converter  20 , OVP protection is achieved without inserting a second high voltage device in the high current path, but instead is achieved by changing the control of the high-voltage rated low-side N-channel MOSFET  70 . 
     Specifically, linear regulator  80  limits the maximum voltage imposed on PWM controller  70  to some predefined maximum voltage V cc , typically 3V or 5V, so that the devices utilized within PWM circuit  70  may comprise only low-voltage devices. Linear regulator  80  is preferably a low-drop-out type, e.g. with a series voltage drop under 200 mV, to extend the operating voltage range of converter  69  to lower input voltages V IN . The design of low drop-out linear regulators is well known to one skilled in the art of power electronics. Input and output capacitors  81  and  82  acts as filter capacitors and prevent LDO  80  from oscillating. The benefit of the smaller sized devices is the silicon die area may be reduced compared to the area occupied by high voltage PWM circuit  22  of aforementioned SEPIC converter circuit  20 . 
     For over-voltage protection SEPIC converter  69  achieves OVP capability by shutting OFF high-voltage MOSFET  72  whenever an over-voltage condition is detected. The maximum operating voltage of high voltage N-channel MOSFET  72  is set by OVP reference voltage  84 . Comparing the input voltage V IN  to the reference voltage V ref , at the point of over-voltage shutdown when V IN &gt;V ref , comparator  83  inhibits PWM control of MOSFET  72  with logic AND gate  71 . In such an event PWM controller  70  no longer determines the turn ON and OFF of MOSFET  71 . The maximum V x  voltage at this moment is (V ref +V OUT ) plus some guard banding. Above this voltage, converter  69  no longer functions and the maximum voltage imposed on the drain of OFF state MOSFET  72  is simply V IN . 
     So in improved SEPIC converter  69 , the voltage capability of MOSFET  72  and diode  75  needed for operation is used to achieve the OVP function without adding extra series resistance to the high-current power path. Comparator  83  is used to monitor the input voltage V IN  and compare it to an over-voltage reference set to a voltage V ref . Reference voltage  84  may be implemented using a bandgap reference, Zener diode, a series of forward biased diodes or any other well known voltage reference technique, or a scaled multiple of said voltage. 
     The remaining elements of SEPIC converter  69  comprises a PWM control circuit  70 , N-channel power MOSFET  72  with intrinsic drain-to-source diode  73 , high-side inductor  74 , capacitor  75 , low-side inductor  76 , rectifier diode  77  and output capacitor  78  powering load  79 . Normal operation comprises repeatedly magnetizing inductor  74  whenever MOSFET  72  is in its ON and conducting state and transferring energy to output capacitor  78  and load  79  in alternating phases. 
     Since only one high voltage MOSFET is present in converter  69 , the current capability of the converter is improved in comparison to converter  20 , where the total MOSFET resistance is only that of MOSFET  72 , i.e. where R total =(R DSN ). With over-voltage protection, the breakdown voltage of MOSFET  72  must be only slightly higher than (V ref +V OUT ) offering the need for less voltage guard banding and on-resistance penalty. Therefore, the approach of circuit  69  may be used for any input voltage with minimal impact on conversion efficiency. 
     Like converter  50 , without a series P-channel MOSFET, OVP protected high-voltage SEPIC converter  69  is unable to offer the load-disconnect function. As a result the circuit provides no means to disconnect load  79  from V IN . 
     High-Voltage SEPIC with Over-Voltage Protection and Load Disconnect 
     As another embodiment of this invention, improved SEPIC converter  80  combines the over-voltage protection features and load disconnect capability of converter  20  with the high voltage capability of converter  50 . The resulting OVP protected high-voltage SEPIC converter is illustrated in circuit  90  of  FIG. 5  including current sensing and load disconnect circuitry  106 . 
     As such, an over-voltage protection comparator  104  in conjunction with a high voltage MOSFET  93  protects the power circuitry while a linear regulator  102  protects the PWM control circuit  91  from high voltages. Similar to converter  69  and unlike in converter  20 , OVP protection is achieved without inserting a second high voltage device in the high current path, but instead is achieved by changing the control of the high-voltage rated low-side N-channel MOSFET  93 . 
     To avoid the need for substantial high voltage circuitry, linear regulator  102  limits the maximum voltage imposed on PWM controller  91  to some predefined maximum voltage V cc , typically 3V or 5V, so that the devices utilized within PWM circuit  91  may comprise only low-voltage devices. Linear regulator  80  is preferably a low-drop-out type, e.g. with a series voltage drop under 200 mV, to extend the operating voltage range of converter  90  to lower input voltages V IN . The design of low drop-out linear regulators is well known to one skilled in the art of power electronics. Input and output capacitors  101  and  103  acts as filter capacitors and prevent LDO  102  from oscillating. The benefit of the smaller sized devices is the silicon die area may be reduced compared to the area occupied by high voltage PWM circuit  22  of aforementioned SEPIC converter circuit  20 . 
     For over-voltage protection SEPIC converter  90  achieves OVP capability by shutting OFF high-voltage MOSFET  93  whenever an over-voltage condition is detected. The maximum operating voltage of high voltage N-channel MOSFET  93  is set by OVP reference voltage  105 . Comparing the input voltage V IN  to the reference voltage V ref , at the point of over-voltage shutdown when V IN &gt;V ref , comparator  104  inhibits PWM control of MOSFET  93  with triple-input logic AND gate  92 . In such an event PWM controller  91  no longer determines the turn ON and OFF of MOSFET  93 . The maximum V x  voltage at this moment is (V ref +V OUT ) plus some guard banding. Above this voltage, converter  90  no longer functions and the maximum voltage imposed on the drain of OFF state MOSFET  93  is simply V IN . 
     In improved SEPIC converter  90  the voltage capability of MOSFET  93  and diode  94  needed for operation is used to achieve the OVP function without adding extra series resistance to the high-current power path. Comparator  104  is used to monitor the input voltage V IN  and compare it to an over-voltage reference set to a voltage V ref . Reference voltage  105  may be implemented using a bandgap reference, Zener diode, a series of forward biased diodes or any other well known voltage reference technique, or a scaled multiple of said voltage. 
     Current sensing is achieved in improved SEPIC converter  90  using current sensing and load disconnect circuitry  106 , utilizing a low-loss current sensing technique described in a pending U.S. patent application entitled “Cascode Current Sensor for Discrete Power Semiconductor Devices” by R. K. Williams. That disclosure is incorporated in this document by reference. Rather than using a resistor as a current sense element, low-voltage low-resistance P-channel MOSFET  107  with intrinsic reverse biased P-N diode  108  is inserted in the path of the input current flowing in inductor  95 . Under normal operation the gate voltage V GP  of P-channel  107  is pulled down by gate buffer  109  to fully enhance the MOSFET into a low-resistance state with a resistance R DSP  for a given area substantially lower than that of high-voltage P-channel  31  described previously in  FIG. 20 . 
     The maximum gate to source voltage V GSP  of P-channel  108  in its ON condition cannot exceed the maximum gate rating of the P-channel  107 , i.e. V GSP &lt;|V IN −V GP | as determined by the output of gate buffer  109 . When MOSFET  107  is ON and conducting, amplifier or comparator  110  is used to determine the input current flowing into inductor  95 . By using a mirror technique the current in MOSFET  107  can be accurately determined. 
     During normal operation, the gate buffer  109  biases MOSFET  107  into a low-resistance conducting state. Amplifier or comparator  110  accurately detects the current flowing in conducting MOSFET  107  and outputs a signal. If this signal is analog, representing a measurement of inductor  95  current, the information may be used to implement current mode control of PWM block  91 . 
     In another implementation shown in  FIG. 5 , comparator  110  has a digital output representing over-current protecting shutdown or OCS, and used as one input to triple NAND gate  110 . Only when converter  90  has an input voltage V IN  below a specified preset level and the measured current in MOSFET  107  does not cause comparator  110  to flip states as an over-current condition, then the output of PWM controller  91  controls the turning ON and OFF of N-channel MOSFET  93 . Accordingly, the V w  input of SEPIC converter  90  is connected to V IN  and the converter is operating. 
     The remaining elements of SEPIC converter  90  comprises a PWM control circuit  91 , N-channel power MOSFET  93  with intrinsic drain-to-source diode  94 , high-side inductor  95 , capacitor  96 , low-side inductor  97 , rectifier diode  98  and output capacitor  99  powering load  100 . Normal operation comprises repeatedly magnetizing inductor  95  whenever MOSFET  93  is in its ON and conducting state and transferring energy to output capacitor  99  and load  100  in alternating phases. 
     Since only one high voltage MOSFET  93  plus one low-voltage MOSFET  107  is present in converter  90 , the current capability of the converter is improved in comparison to converter  20 , where the total MOSFET resistance is that of high-voltage MOSFET  93  plus the resistance of low-voltage MOSFET  107 , i.e. where R total =(R DSP +R DSN ). With over-voltage protection, the breakdown voltage of MOSFET  93  must be only slightly higher than (V ref +V OUT ) offering the need for less voltage guard banding and on-resistance penalty. Therefore, the approach of circuit  90  may be used for any input voltage with minimal impact on conversion efficiency. 
     By including series low voltage P-channel MOSFET  107 , the disclosed OVP protected high-voltage SEPIC converter  90  is able to offer the load-disconnect function whereby the circuit provides a means to disconnect load  100  from V IN . Load disconnect is controlled by P-type current sense PCS signal, the input to gate buffer  109 .