Abstract:
A high speed write driver for an inductive head of a magnetic storage medium is provided which contains a mechanism to reduce the inductive head current overshoot and therefore reduce jitter and, thus, increase the write cycle frequency. An input voltage control stage controls a voltage applied to the inductive head from the voltage source. A current supply to supplies current to the inductive head element, and a damping circuit in communication with the inductive head element. An overshoot suppressor circuit is provided such that the input voltage control tage is responsive to the overshoot suppressor circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to write drivers for an inductive head in a magnetic data storage system, and particularly to write drivers designed to operate at high rates of data transfer. 
     2. Description of Related Art 
     Conventional storage systems include an inductive head that uses an inductive element to write information on a recording surface of a magnetic media, such as a magnetic disk. The inductive element usually is an inductive coil that writes information by creating a changing magnetic field. A write driver circuit is connected to the inductive at first and second head nodes. During writing operations, the write driver circuit forces a relatively large write current through the inductive coil to create a magnetic field that polarizes adjacent bit positions on a recording surface. Digital information is stored by reversing the polarization of selected bit positions which is done by reversing the direction of the current flow in the inductive head. 
     The rate at which information can be stored on a recording surface through the inductive head is directly proportional to the rate at which the direction of current can be reversed in the inductive coil. The rise/fall time of the inductive coil is determined by: 
      di/dt= V/L   
     where di/dt is the rate of change of the write current, V is the available voltage across the inductive coil and L is the head inductance. Therefore the rise time is inversely proportional to the available voltage across the inductive coil. 
     There is, however, a fundamental limit as to how fast current can change in an inductive head due to its capacitance, parasitic capacitance and write driver capacitance. The combination of inductance and capacitance produces ringing which in conventional high speed write drivers can be controlled by means of a damping resistor coupled across the inductive head. Another limitation on performance of high speed drivers is the current overshoot which occurs in the inductive head element after the current reaches its threshold. The overshoot can cause significant data dependent jitter. 
     Four U.S. patents are known to deal with magnetic media high speed current drivers. 
     U.S. Pat. No. 5,386,328 (Chiou, et al.) describes a current mirror based write driver to operate inductive heads for magnetic recording. The write driver has a head voltage that swings between the upper and lower supply rails and thus may be used with CMOS circuits or differential ECL circuits. The 3.3V write driver maintains the same performance characteristics as magnetic recording devices that are powered at supply voltage levels of 5V and 12V. 
     U.S. Pat. No. 5,822,141 (Chung, et al.) discloses a high speed FET write driver for an inductive head. The FET write driver provides high rate of data transfer to a magnetic storage medium by effectively using the voltage swing provided by the supply voltage. During operation, the low voltage drops across the FET switches allow for a substantial portion of the supply voltage to be available across the inductive head. The circuit is inherently stable and avoids ringing and overshoot which results in improved timing and maintains signal integrity. This patent does not provide a means for controlling current overshoot resulting from the fast rise time of the inductive head write current. 
     U.S. Pat. No. 5,612,828 (Brannon, et al.) teaches a write driver circuit for driving a magnetic head in an information storage system. The write driver circuit is connected to first and second voltage supply terminals and includes first and second data input terminals for receiving data input signals. The write driver circuit is formed of an H-switch to switch current flow through the magnetic head. A pair of anti-saturation circuits is connected to the H-switch to bias the pull-up transistors of the H-switch 
     U.S. Pat. No. 5,869,988 (Jusuf, et al.) discloses a high-speed write driver for inductive heads of a magnetic storage medium. The write driver induces a faster write current reversal in an inductive head element by using two significant improvements that operate during the current switch cycle. One is a current boost mechanism to generate a faster rise time when the current switches direction through the inductive head element and the other is a mechanism to reduce the damping resistor effect during the current reversal time. 
     SUMMARY OF THE INVENTION 
     The present invention describes a high speed write driver for an inductive head of a magnetic storage medium which contains a mechanism to reduce the inductive head current overshoot and therefore reduce jitter and, thus, increase the write cycle frequency. The write driver is comprised of a pair of switches, S 1  and S 2  coupled to a pair of current sources, I 1  and I 2 . Current source I 1  is controlled by first control signal CKNL and current source I 2  is controlled by second control signal CKNR which is complementary to CKNL. The first switch S 1  is coupled to the first current source I 1 , and is controlled by first switch control signal CKPL, and the second switch S 2  is coupled to the second current source I 2  and is controlled by second switch control signal CKPR. In one embodiment, a current booster is coupled to each current source to boost the write current and increase the write current rate of change during current switch transitions; a programmable damping resistor Rd is incorporated in order to momentarily increase Rd and, thus, increase write current and write current rate of change during current switch transitions; switches S 1  and S 2  which are controlled, respectively, by CKPL and CKPR to maximize rail to rail voltage swing and to suppress current overshoot in the inductive head element by momentarily forcing the voltage across the inductive head element to zero when the threshold current is reached. Other embodiments incorporating the current overshoot suppression with and without the current booster and with or without the programmable resistor are possible. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a high speed write driver constructed in accordance with the principles of this invention. 
     FIG. 2 illustrates a timing diagram for the high speed write driver of FIG.  1 . 
     FIG. 3 illustrates an alternative and the preferred embodiment of a high speed write driver shown in FIG.  1 . 
     FIG. 4 illustrates a timing diagram for the high speed write driver of FIG.  3 . 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT 
     FIG. 1 illustrates a high speed write driver  100  described in accordance with the principles of this invention. Write driver  100  induces a faster write current switch across an inductive head element  152  of a magnetic storage device comprising an input voltage control stage. The input voltage control stage comprises a pair of switches, including a first switch (S 1 )  112  and a second switch (S 2 )  114 , comprising PMOS transistors PDL and PDR respectively, coupled to a pair of current sources comprising, a first current source circuit (I 1 )  116  that includes a first NMOS transistor (NDL)  120  coupled to a second NMOS transistor (NCSL)  124  which is coupled to a current bias source (CBI)  160  and a second current source circuit (I 2 )  118  comprising a third NMOS transistor (NDR)  122  coupled to a fourth NMOS transistor (NCSR)  126  which is also coupled to the current bias source (CBI)  160 . The pair of switches further comprises switch S 1   112  coupled between a voltage source (Vdd)  138  and the first node (A)  140  of damping resistor (PD)  110 . Node A  140  is also coupled to current source I 1   116 . A first current switch control signal (CLK)  162  is coupled to control transistor NDL  120  of current source I 1   116  and to switch S 1   112  to generate a rail to rail voltage swing at node A  140  of damping resistor PD  110 . Switch S 2   114  is coupled between the voltage source Vdd  138  and to second node (B)  142  of damping resistor PD  110 . Node B  142  of damping resistor PD  110  also being coupled to current source (I 2 )  118 . A second current switch control signal (/CLK)  164 , signal /CLK  164  being a complimentary signal of CLK  162 , is coupled to control transistor NDR  122  of current source I 2   118  and to switch S 2   114  to also produce a rail to rail voltage swing at node B  142  of damping resistor PD  110 . During a clock transition, such as when CLK  162  transitions from LOW to HIGH, current source I 1   116  switches ON to allow current flow IL  146 , while switch S 1   112  correspondingly switches OFF to de-couple from voltage source Vdd  138 . Concurrently, switch S 2   114  switches ON when /CLK signal  164  transitions HIGH to LOW, thereby pulling node B  142  quickly to voltage Vdd value, while current source I 2   118  shuts OFF, blocking current flow IR  148 . Consequently, IW  144  quickly switches the direction of its flow, such as to flow from node B to node A rather than from node A to node B, thus corresponding to a fast write current change. 
     Current sources  116  and  118  constitute a current supply. A capacitance (Ctot)  125  is shown to represent the parasitic capacitance of inductive head element (L)  152 , its parasitic capacitance, and the capacitance of the write driver. Write driver  100  further comprises a pair of additional current boosters including a first current booster transistor (NBL)  102  coupled to current source I 1   116  and a second current booster transistor (NBR)  104  coupled to current source I 2   118 . As illustrated in the timing diagram of FIG. 2, current booster NBL  102  is controlled by first booster control signal (VbI)  106  that is triggered by a rising edge of CLK signal so that current IbI from booster circuit NBL is added to current source I 1   116  current to increase current IL  146  during CLK transition from LOW to HIGH. Since current IW  144  is proportional to IL  146  during CLK transition from LOW to HIGH, the increased current of IL  146  from current booster NBL  102  produces a faster rise time of write current Iw  144 . Similarly, current booster NBR  104  is controlled by a second booster control signal (Vbr)  108  that is triggered by the rising edge of /CLK signal so that current from booster circuit NBR is added to current from current source I 2   118  to increase current (IR)  148  during /CLK transition from LOW to HIGH. The write driver  100  further comprises a programmable active damping resistor PD  110 . The programmable resistor PD  110  is controlled by a timing signal RDMP  111  which is coupled to be triggered by a falling edge of both, CLK  162  and /CLK  164 . Timing signal RDMP  111  controls the value of PD  110  such as to switch between a desired low resistance value Rd and a high value when PD  110  is OFF. As illustrated in FIG. 2 at the beginning of a write operation, i.e. when CLK  162  transitions from LOW to HIGH, damping resistor PD  110  is HIGH for a short time period t 1 , essentially removing PD  110  from the circuit and, thereby speeding up the fall time of write current IL  146  to generate a faster write operation. Similarly, when /CLK  164  transitions from LOW to HIGH, damping resistor PD  110  is OFF for a short time period t 1 , thereby speeding up the rise time of current Iw  144 . Thus, the improvement to the rise and fall times of the driver due to the programmable resistor PD  110  is accomplished without need to increase driver power consumption. 
     The write driver further comprises a pair of switching transistors (POSL)  130  and (POSR)  132  which provide a mechanism for current overshoot suppression. Transistor POSL is of the same type as switch S 1  transistor PDL and is coupled in parallel with transistor PDL, i.e. it is identically coupled between Vdd  138  and node A  140  of the damping resistor PD  110 . The control signal (COSL)  134  of transistor POSL  130  is triggered by the falling edge of booster control signal VbI  106  to turn transistor POSL  130  ON for a short period t 2 , thereby forcing the voltage across the inductive head element L  152  to zero, transistor PDR  114  of switch S 2  also being ON during this time. Similarly, transistor POSR is of the same type as transistor PDR  114  of switch S 2  and is coupled in parallel with transistor PDR  114 . The control signal (COSR)  136  of transistor POSR  132  is triggered by the falling edge of booster control signal Vbr  108  to turn transistor POSR  132  ON for the short period t 2  to force the voltage across the inductor L  152  to zero. During the boost periods the inductor current reaches the threshold value and the action of POSL and POSR, by forcing the voltage across the inductor to zero, reduces the rate of change of current in the inductor L  152  to zero, stabilizing the inductor current and significantly suppressing current overshoot without compromising the rise and fall times. FIG. 2 which illustrates the timing diagram for the write driver  100  depicts the idealized control timing for overshoot suppressor transistors POSL and POSR. 
     FIG. 3 illustrates an alternative embodiment of a high speed write driver described in accordance to the principles of this invention. Write driver  200  operates essentially as described for write driver  100  of FIG.  1 . However, in this embodiment the function of overshoot suppressing transistors POSL and POSR has been incorporated respectively, into switch S 1  transistor (PDL)  212  and into switch S 2  transistor (PDR)  214 . The control signals of transistors PDL  212  and PDR  214  have been appropriately modified to implement the new combined function. Thus, the PDL  212  control signal (CKPL)  234  in FIG. 3 becomes the logical superposition of control signal CLK  164  and control signal COSL  134  of FIG.  1 . The resulting timing diagram is shown in FIG.  4 . Similarly, the PDR  214  control signal (CKPR)  236  in FIG. 3 becomes the logical superposition of control signal /CLK  164  and control signal COSR  136  of FIG.  1 . The resulting timing diagram is also shown in FIG.  4 . The control signal CLK  162  of FIG.1 is de-coupled from switch S 1  transistor PDL 112  and becomes the control signal (CKNL)  262  which is coupled only to current source I 1   216  transistor NDL  220 . Similarly, the control signal /CLK  164  of FIG.1 is de-coupled from switch S 2  transistor PDR  114  and becomes the control signal (CKNR)  264  which is coupled only to current source I 2   218  transistor NDR  222 . The high speed driver  200  depicted in FIG. 3 compared to the write driver  100  of FIG. 1 has a reduced footprint, lower capacitance and lower power consumption and, therefore, is the preferred implementation. 
     While the write driver implementation depicted in FIG.  1  and FIG. 3 has the pair of switches comprised of PMOS transistors and the pair of current sources comprised of NMOS transistors, an implementation which embodies the principles of this invention and is comprised of NMOS transistors for the pair of switches and PMOS transistors for the pair of current sources is not precluded. In such an implementation, the positive supply voltage Vdd would be reversed and a negative supply voltage would be provided. 
     While the write amplifiers depicted in FIG.  1  and in FIG. 3 are illustrated in CMOS technology, the concepts described in accordance to the principles of this invention are applicable to other types of process technology, such as MOS or Bipolar. 
     The advantages of the present invention are: 
     Rise and fall time of write current is reduced. 
     Write current overshoot is reduced. 
     Driver write frequency is increased with minimum jitter. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.