Abstract:
A system and method are directed to measuring incoming transition widths by counting asynchronous clock pulses, deriving a reference shortest validated width, and using the shortest validated width for comparison in discriminating further incoming pulse widths.

Description:
REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority from U.S. Provisional Patent Application Ser. No. 60/492,708, filed Aug. 5, 2003, the entire content of which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates generally to asynchronous serial data modulation and demodulation and, in particular, apparatus and methods for discriminating transition width across a broad frequency range without use of a synchronous clock.  
       BACKGROUND OF THE INVENTION  
       [0003]     Many asynchronous serial data modulation schemes are reliant upon pulse width (RZ—return to zero) or state width (NRZ—no return to zero) modulation. The most common modulation schemes rely upon discrimination between two or more pulse or state widths related by a specified multiplicative factor ‘n’. In order to demodulate such data streams, it has been common practice to extract a clock signal from the data stream with a period equal to, or an integer fraction of, the shortest transition width. For robust demodulation, this extracted clock signal must be phase locked to the data stream, which usually indicates the use of a phase-locked loop (PLL) design. Not only do PLLs bring complexity and additional cost to demodulator designs, they almost always employ fixed-frequency filters, and their performance is inversely proportional to bandwidth. This precludes their use in frequency-agile designs. There exists a need of a simple demodulation method for asynchronous serial data which facilitates wide frequency ranges.  
       SUMMARY OF THE INVENTION  
       [0004]     The present invention resides in the method of measuring incoming transition widths by counting asynchronous clock pulses, deriving a reference based upon a shortest validated width, and using the shortest validated width for comparison in discriminating further incoming pulse widths. 
     
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0005]      FIG. 1  shows a block diagram of a binary preferred embodiment of the present invention demodulating a NRZ data stream. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0006]     Referring now to  FIG. 1 , transition detector  102  is driven by incoming asynchronous serial data stream  101 , and outputs a narrow pulse  115  at each transition. UP counter  104  is clocked by asynchronous clock  103 , presumably of a period one half or less that of the minimum incoming transition width  101  expected. At each transition of incoming data stream  101 , pulse  115  simultaneously latches the current value of the UP counter  104  in latch  105 , and resets it in preparation for measuring the next pulse width. The output of latch  105  resultantly is a measure in asynchronous clock  103  pulses of the last incoming transition width, or period, shown as transition width signal  115 .  
         [0007]     Transition width signal  115  is applied to comparator  111  for comparison with a calculated reference  117 , described below, to yield an output  119  which indicates the relative width of the last transition width. Transition width  115  is also applied to comparator  112  for comparison with another calculated reference  118 , also described below, to yield an output  120  which indicates that the last transition width was of sufficient length to be valid.  
         [0008]     The output  119  of comparator drives a switch  107  which supplies either the incoming transition width  116 , when a long incoming transition width is not indicated by comparator  111 ; or the incoming transition width  116  divided by n (supplied by divider  106 ) when a long incoming transition width is indicated by comparator  111 , to averaging filter  108 .  
         [0009]     The foregoing scheme ensures that short transition widths are directly input to filter  108 , and long transition widths are divided by n before input to filter  108 . Filter  108  is updated by AND gate  113 , from the simultaneous condition of detected transition pulse  115  and validated transition width  120 . Filter  108  resultantly outputs the average short transition width  114 .  
         [0010]     Average short transition width  114  is divided by two by divider  110  and supplied as reference input to comparator  112 , which resultantly indicates that the incoming transition width  116  is above one-half the average short transition width  114 . Comparator  112  thus provides protection against glitches on incoming serial data stream  101 .  
         [0011]     Average short transition width signal  114  is multiplied by ((n+1)/2) by multiplier  109 , and supplied as reference input to comparator  111 , which resultantly indicates that the incoming transition width  116  is above one-half the difference between the average short transition width  114  and the average short transition width  114  times n. Comparator  111  thus provides short or long transition width indication  119 , which is strobed as demodulated data by the output of AND gate  113 , which indicates a transition ( 115 ) with a validated minimum width ( 120 ).  
         [0012]     A circuit incorporating the present invention robustly discriminates transition width across a broad frequency range, without use of a synchronous clock. Implementations employing differing physical width indications, and/or number of states are anticipated.