Abstract:
A semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode structure and a side wall structure. The gate insulating layer is formed on the semiconductor substrate. The gate electrode structure is formed on the gate insulating layer, and includes a lower gate electrode layer and a cap gate layer. The side wall structure includes a nitride side wall spacer, and an oxide layer formed between the semiconductor substrate and the nitride side wall spacer and between the lower gate electrode layer and the nitride side wall spacer. A thickness of the oxide layer is greater than a thickness of the gate insulating layer, so as to prevent diffusion of nitrogen from the nitride side wall spacer to the semiconductor substrate. A height of the gate electrode structure is substantially equal to a height of the side wall structure after completion of the semiconductor device.

Description:
This is a divisional application of application Ser. No. 10/762,361, filed Jan. 23, 2004, now U.S. Pat. No. 6,953,732, which is a divisional application of application Ser. No. 10/320,660, filed Dec. 17, 2002, now U.S. Pat. No. 6,700,167, which is a divisional application of application Ser. No. 10/320,543, filed Dec. 17, 2002, now U.S. Pat. No. 6,677,651, which is a divisional application of Ser. No. 09/759,639 filed Jan. 16, 2001, now U.S. Pat. No. 6,528,854, which are hereby incorporated by reference in their entirety for all purposes. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a semiconductor device and to a method for manufacturing the same. In particular, the present invention relates to a MOSFET which has side wall structure and to a method for manufacturing the same. 
     This is a divisional application Ser. No. 10/762,361, filed Jan. 23, 2004, now U.S. Pat. No. 6,953,732, which is a divisional application of application Ser. No. 10/320,660, filed Dec. 17, 2002, now U.S. Pat. No. 6,700,167, which is a divisional application of Ser. No. 09/759,639 filed Jan. 16, 2001, now U.S. Pat. No. 6,528,854, which are hereby incorporated by reference in their entirety for all purposes. 
     2. Description of the Related Art 
     A Self-Aligned Contact (SAC) method is an important technique used in fabricating semiconductor devices. This technology is described in the article entitled “A Process Technology for 1 Giga-Bit DRAM” IEDM Tech. Dig., pp907-910, 1995. 
     SiN is generally used as sidewalls of a gate electrode in the SAC process. This is because the etching rate of SiN is different from that of silicon-oxide, and therefore SiN sidewalls are used as a stopper in etching on an intermediate oxide layer. 
       FIG. 23  is a schematic diagram of a MOSFET 800 manufactured using an SAC process. 
     A gate oxide layer  824  having a constant thickness is formed on a silicon substrate  802 . A gate electrode  816  is formed on the gate oxide layer  824 . A SiN cap layer  820  is formed on the gate electrode  816 . SiN sidewalls  822 , which cover the side surfaces of the gate electrode  816 , are formed on the gate oxide layer  824 . 
     A heat treatment is generally performed in manufacturing of the MOSFET 800 after the formation of sidewalls. In case of SiN sidewalls, hydrogen and nitrogen may be diffused into the silicon substrate  802  through the gate oxide layer  824  during the heat treatment. Therefore, MOSFETs which have SiN sidewalls are less reliable due to resultant hot-carrier degradation than MOSFETs which have sidewalls of silicon oxide. These problems are pointed out and discussed in the article entitled “Enhancement of Hot-Carrier Induced Degradation under Low Gate Voltage Stress due to Hydrogen for NMOSFETs with SiN films” S. Tokitoh et al. IRPS, pp307-311, 1997 and “Hot-carrier Degradation Mechanism and Promising Device Design of nMOSFETs with Niteride Sidewall Spacer” Y. Yamasugi et al. IRPS, pp 184-188, 1998. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a reliable semiconductor device, and to provide a method for manufacturing the same. 
     According to an aspect of the present invention, a semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode structure and a side wall structure. The gate insulating layer is formed on the semiconductor substrate. The gate electrode structure is formed on the gate insulating layer. The gate electrode structure includes a lower gate electrode layer and a cap gate layer. The side wall structure includes a nitride side wall spacer, and an oxide layer formed between the semiconductor substrate and the nitride side wall spacer and between the lower gate electrode layer and the nitride side wall spacer. The oxide layer is formed using at least one of chemical vapor deposition and thermal annealing. A thickness of the oxide layer between the semiconductor substrate and the nitride side wall spacer is greater than a thickness of the gate insulating layer, so as to prevent diffusion of nitrogen from the nitride side wall spacer to the semiconductor substrate. A height of the gate electrode structure is substantially equal to a height of the side wall structure after completion of the semiconductor device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter that is regarded as the invention, the invention, along with the objects, features, and advantages thereof, will be better understood from the following description taken in conjunction with the attached drawings, in which: 
         FIG. 1  is a cross sectional view showing a semiconductor device according to a first preferred embodiment. 
         FIG. 2  is a flow chart of a method for manufacturing the semiconductor device of first embodiment. 
         FIG. 3  is a cross sectional view showing the method for manufacturing the semiconductor device of the first embodiment. 
         FIG. 4  is a cross sectional view showing a semiconductor device according to a second preferred embodiment. 
         FIG. 5  is a flow chart of a method for manufacturing the semiconductor device of the second embodiment. 
         FIG. 6  is a cross sectional view showing the method for manufacturing the semiconductor device of the second embodiment. 
         FIG. 7  is a cross sectional view showing a semiconductor device according to a third preferred embodiment. 
         FIG. 8  is a flow chart of a method for manufacturing the semiconductor device of the third embodiment. 
         FIG. 9  is a cross sectional view showing the method for manufacturing the semiconductor device of the third embodiment. 
         FIG. 10  is a cross sectional view showing a semiconductor device according to a fourth preferred embodiment. 
         FIG. 11  is a flow chart of a method for manufacturing the semiconductor device of the fourth embodiment. 
         FIG. 12  is a cross sectional view showing the method for manufacturing the semiconductor device of the fourth embodiment. 
         FIG. 13  is a cross sectional view showing a semiconductor device according to a fifth preferred embodiment. 
         FIG. 14  is a flow chart of a method for manufacturing the semiconductor device of the fifth embodiment. 
         FIG. 15  is a cross sectional view showing the method for manufacturing the semiconductor device of the fifth embodiment. 
         FIG. 16  is a cross sectional view showing a semiconductor device according to a sixth preferred embodiment. 
         FIG. 17  is a flow chart of a method for manufacturing the semiconductor device of the sixth embodiment. 
         FIG. 18  is a cross sectional view showing the method for manufacturing the semiconductor device of the sixth embodiment. 
         FIG. 19  is a cross sectional view showing a semiconductor device according to a seventh preferred embodiment. 
         FIG. 20  is a flow chart of a method for manufacturing the semiconductor device of the seventh embodiment. 
         FIG. 21  is a cross sectional view showing the method for manufacturing the semiconductor device of the seventh embodiment. 
         FIG. 22  shows the impurity concentration of the LDD regions of the seventh embodiment 
         FIG. 23  shows a schematic diagram of the MOSFET 800 manufactured by using a Self Aligned Contact process. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 1  is a cross sectional view showing a semiconductor device according to a first preferred embodiment of this invention. 
     The semiconductor device  100  of this embodiment has a silicon substrate  102 , an intermediate insulating layer  104 , and a MOSFET  110 . The MOSFET  110  is formed on the silicon substrate  102 . The intermediate insulating layer  104  is formed on the silicon substrate  102  and MOSFET  110 . The intermediate insulating layer  104  is made of silicon oxide. 
     MOSFET  110  has a source region  112 , a drain region  114 , a gate electrode  116 , and a channel region  118 . The MOSFET  110  of this embodiment has a LDD structure as shown by  112   a ,  114   a . The source region  112 , the drain region  114  and the channel region  118  are formed in the semiconductor substrate  102 . The gate electrode  116  is formed over the semiconductor substrate  102 . The channel region  118  is formed between the source region  112  and the drain region  114 , and under the gate electrode  116 . For example, the N channel MOSFET ( 110 ) includes a P type substrate ( 102 ) into which two heavily doped N regions ( 112 , 114 ) and two lightly doped regions ( 112   a , 114   a ) have been diffused. 
     MOSFET  110  has a cap layer  120  and sidewall structure  122 . The cap layer  120  is formed on the gate electrode  116 . Sidewall structure  122  are formed over the silicon substrate  102 . The sidewalls  122  cover both sides of the gate electrode  116 . A material which is different from the intermediate insulating layer  104  is used as the cap layer  120  and sidewalls  122 . The cap layer  120  and sidewalls  122  are made of SiN in this embodiment. 
     The MOSFET  110  has a gate oxide layer  124  and diffusion deterrent layers  126 . The gate oxide layer  124  and a diffusion deterrent layer  126  are formed on the surface of the silicon substrate  102 . The gate oxide layer  124  is formed under the gate electrode  116 . The diffusion deterrent layers  126  are formed under the sidewalls  122 . These diffusion deterrent layers  126  prevent hydrogen and nitrogen in the sidewalls  122  from diffusing into the silicon substrate  102 . The gate oxide layer  124  has a thickness of about 10 nm (100 Å). The diffusion deterrent layers  126  are preferably twice the thickness against of the gate oxide layer  124 . The gate oxide layer  124  and the diffusion deterrent layers  126  are made of silicon oxide. Since the thicknesses of the diffusion deterrent layers  126  are greater than the gate oxide layer  124 , hydrogen and nitrogen in the sidewalls do not diffuse into the silicon substrate  102 . 
     The semiconductor device also has first contact holes  106   a , first interconnections  108   a , a second contact hole  106   b , and a second interconnection  108   b.    
     The first contact holes  106   a  are formed using a SAC process. SiN sidewalls  122  are used as a stopper in etching on the intermediate oxide layer  104 . The first interconnections  108   a  are respectively connected to the drain region  114  and the source region  112 . The second interconnection  108   b  is connected to the gate electrode  116 . 
     For example, in a semiconductor memory-cell, the source region  112  is connected to a bit line, and the drain region  114  is connected to a storage capacitor, through first interconnections  108   a . The gate electrode  116  is connected to a word line through the second interconnection  108   b.    
     The MOSFET  110  of this embodiment has a silicon oxide layer  126  under the sidewalls, and this silicon oxide layer  126  is thicker than the silicon oxide layer  124  under the gate electrode  116 . The silicon oxide layer  126  has a thickness to prevent the diffusion of hydrogen and nitrogen. Therefore, the silicon oxide layer  126  works as diffusion deterrent layer. The thickness of the diffusion deterrent layer  126  depends on the width of sidewalls  122 . There is an effect if the thickness of the silicon oxide layer  126  is 50% greater than the thickness of the silicon oxide layer  124 . However, it is desirable that the diffusion deterrent layer  126  be at least twice the thickness of the gate oxide layer  124 . 
       FIG. 2  is a flow chart of a method for manufacturing the semiconductor device of this embodiment, and  FIG. 3  is a cross sectional view showing the method for manufacturing the same. The method for manufacturing the semiconductor device of this embodiment is described below. 
     The gate oxide layer  124  is formed on the surface of the semiconductor substrate  102  using a thermal oxidation. (Step  21 ) This gate oxide layer  124  has a thickness of about 10 nm. 
     The gate electrode material  116  and the cap layer material  120  are formed on the gate oxide layer  124  as seen in  FIG. 3(   a ). A lithography method and an anisotropic etching technique, such as a RIE method, are employed to etch the gate electrode material  116  and the cap layer material  120 . The gate electrode  116  and the cap layer are formed as seen in  FIG. 3(   b ). (Step  22 ) 
     Ion implantation for forming the LDD region  112   a  and  114   a  is performed by using the cap layer  120  as the mask. This implantation makes lightly doped regions  112   a  and  114   a . (Step  23 ) 
     A silicon oxide layer  126  is formed on the gate oxide layer  124  using CVD. As the gate electrode  116  and the cap layer  120  are used as a mask, this silicon oxide layer  126  is deposited on the gate oxide layer  124  other than the portion under the gate electrode  116  (as shown in  FIG. 3(   c )). Therefore, a thickness of the gate oxide layer other than the portion under the gate electrode layer is increased. This silicon oxide layer  126  works as the diffusion deterrent layer  126 . (Step  24 ) The oxide layer  126  is deposited at about 10 nm on the gate oxide layer beside the gate electrode  126 , therefore the diffusion deterrent layer  126  has a thickness of about 20 nm. 
     An SiN sidewall layer, having a thickness of from 100 nm to 200 nm, is formed over the semiconductor substrate using LP-CVD. An anisotropic etching technique, such as a RIE method, is employed to etch the SiN sidewall layer, so that SiN sidewalls are formed. (Step  25 ) 
     An ion implantation for forming the source region  112  and the drain region  114  is performed by using the cap layer  120  and sidewalls  122  as a mask. An annealing is performed after the ion implantation. This annealing diffuses implanted ions and forms the source region  112  and the drain region  114  as shown in  FIG. 3(   d ). (Step  26 ) 
     The intermediate insulating layer  104  is formed over the semiconductor substrate  102 . (Step  27 ) The intermediate insulating layer  104  is made of a material which is different from the material of the cap layer  120  and the side walls  122 . The intermediate insulating layer  104  is made of silicon oxide in this embodiment. 
     The first contact holes  106   a  are formed using a SAC process. (Step  28 ) The intermediate insulating layer  104  is etched using an etchant which has a smaller etching rate for SiN than for silicon-oxide. SiN sidewalls are used as a stopper. The intermediate layer  104  and the silicon oxide  126  over the source region and drain region are etched in this step. 
     The interconnections  108   a  are formed in the contact holes  106   a . The second contact hole and the second interconnection are formed after the first interconnections are formed. 
     In this embodiment, the diffusion deterrent layers  126  prevent hydrogen and nitrogen in the sidewalls from diffusing into the silicon substrate  102  during annealing. Therefore, interface traps, which are related to hot carrier, are reduced near the surface of the semiconductor substrate, this improving the reliability of the MOSFET  110 . 
     The diffusion deterrent layer  126  is formed using CVD in this embodiment. Therefore, the thickness of the diffusion deterrent layer  126  is controlled precisely, and characteristics of the MOSFET are easily controlled. 
       FIG. 4  is a cross sectional view showing a semiconductor device according to a second preferred embodiment of this invention. 
     The semiconductor device  200  has a MOSFET  210 . The MOSFET  210  has a gate electrode  216 . The gate electrode  216  of this embodiment has oxide wall layers  216   a  on its side surfaces. 
     The MOSFET  210  has a diffusion deterrent layer  226  on the surface of the silicon substrate  202 . The other parts of the semiconductor device of this embodiment are the same as those in the first embodiment. 
       FIG. 5  is a flow chart of a method for manufacturing the semiconductor device of this embodiment, and  FIG. 6  is a cross sectional view showing the method for manufacturing the same. The method for manufacturing the semiconductor device of this embodiment is described below. 
     The gate oxide layer  224  is formed on the surface of the semiconductor substrate  202  using thermal oxidation. This gate oxide layer  224  has a thickness of about 10 nm. (Step  51 ) 
     The gate electrode material  216  and the cap layer material  220  are formed on the gate oxide layer  224 . A lithography method and an anisotropic etching technique, such as a RIE method, are employed to etch the gate electrode material  216  and the cap layer material  220 . The gate electrode  216  and the cap layer are formed as seen in  FIG. 6(   a ). (Step  52 ) 
     Ion implantation for forming the LDD region  212   a  and  214   a  is performed by using the cap layer  220  as the mask. This implantation makes lightly doped regions  212   a  and  214   a . (Step  53 ) 
     A silicon oxide layer  226  is formed on the gate oxide layer  224  using a thermal oxidation. The thermal oxidation of this embodiment is performed at a temperature of 850° C. and in an oxygen atmosphere. This thermal oxidation thickens the gate oxide layer other than at the portion thereof under the gate electrode  216 . Oxide wall layers  216   a  of the gate electrode  216  are also formed in this thermal oxidation as seen in  FIG. 6(   b ). This silicon oxide layer  226  works as the diffusion deterrent layer  226 . The oxide layer  226  has a thickness of about 20 nm. (Step  54 ) 
     A SiN sidewall layer, having a thickness from 100 nm to 200 nm, is formed on the semiconductor substrate using LP-CVD. An anisotropic etching technique, such as a RIE method, is employed to etch the SiN sidewall layer, so that SiN sidewalls  222  are formed as seen in  FIG. 6(   c ). (Step  55 ) Subsequent steps are the same as those in the first embodiment. (Steps  56 - 58 ) 
     In this embodiment, the diffusion deterrent layer  226  prevent hydrogen and nitrogen in the sidewalls from diffusing into the silicon substrate  202  during annealing. Therefore, interface traps, which are related to hot carrier, are reduced near the surface of the semiconductor substrate, and the reliability of the MOSFET is improved. 
     The diffusion deterrent layer  226  is formed using thermal oxidation in this embodiment. A thin oxide layer between the sidewalls and the cap layer as shown in the first embodiment is not formed. Therefore, the alignment in the SAC process becomes more flexible. 
       FIG. 7  is a cross sectional view showing a semiconductor device according to a third preferred embodiment of this invention. 
     The semiconductor device  300  has a structure which is similar to that of the second embodiment. In third embodiment, the silicon oxide layer covering the side surfaces of the gate electrode is not formed. 
       FIG. 8  is a flow chart of a method for manufacturing the semiconductor device of this embodiment, and  FIG. 9  is a cross sectional view showing the method for manufacturing the same. The method for manufacturing the semiconductor device of this embodiment is described below. 
     The gate oxide layer  324  is formed on the surface of the semiconductor substrate  302  using a thermal oxidation. This gate oxide layer  324  has a thickness of about 10 nm. (Step  81 ) 
     The gate electrode material  316  and the cap layer material  320  are formed on the gate oxide layer  324 . A lithography method and an anisotropic etching technique, such as a RIE method, are employed to etch the gate electrode material  316  and the cap layer material  320 . The gate electrode  316  and the cap layer are formed as seen in  FIG. 9(   a ). (Step  82 ) 
     Ion implantation for forming the LDD regions  312   a  and  314   a  is performed using the cap layer  320  as a mask. This implantation makes lightly doped regions  312   a  and  314   a . (Step  83 ) 
     A SiN sidewall layer, having a thickness from 100 nm to 200 nm, is formed on the semiconductor substrate using LP-CVD. An anisotropic etching technique, such as a RIE method, is employed to etch the SiN sidewall layer, so that SiN sidewalls  322  are formed as seen in  FIG. 9(   b ). (Step  84 ) 
     A silicon oxide layer  326  is formed on the gate oxide layer  324  using a thermal oxidation as seen in  FIG. 9(   c ). The thermal oxidation of this embodiment is performed at a temperature of 850° C. and in an oxygen atmosphere. Thickening begins from the edge portion  322   a  under the side walls, and it expand into the portion near the gate electrode  326 . The time of this oxidation is controlled to expand the thickness of the gate oxide layer other than at the portion lying under the gate electrode  316 . This silicon oxide layer  326  works as the diffusion deterrent layer  326 . The oxide layer  326  has a thickness of about 20 nm. (Step  85 ) Subsequent steps are the same as those in the second embodiment. (Step  86 - 88 ) 
     In this embodiment, the diffusion deterrent layer  326  prevents hydrogen and nitrogen in the sidewalls from diffusing into the silicon substrate  102  during annealing. Therefore, interface traps, which are related to hot carrier, are reduced near the surface of the semiconductor substrate, and the reliability of the MOSFET is improved. 
     The thermal oxidation is performed after the formation of sidewalls in this invention. This thermal oxidation reduces hydrogen in the oxide layer  324  under the sidewalls. Also an oxide layer on the side surface of the gate electrode is not formed in this embodiment. Therefore, a variation of the gate electrode resistance is prevented. 
       FIG. 10  is a cross sectional view showing a semiconductor device according to a fourth preferred embodiment of this invention. 
     The semiconductor device  400  has the same structure as the third embodiment. 
       FIG. 11  is a flow chart of the method for manufacturing a semiconductor device of this embodiment, and  FIG. 12  is a cross sectional view showing the method for manufacturing the same. The method for manufacturing the semiconductor device of this embodiment is described below. 
     The gate oxide layer  424  is formed on the surface of the semiconductor substrate  402  by using thermal oxidation. This gate oxide layer  424  has a thickness of about 10 nm. (Step S 111 ) 
     The gate electrode material  416  and the cap layer material  420  are formed on the gate oxide layer  424 . A lithography method and an anisotropic etching technique, such as a RIE method, are employed to etch the gate electrode material  416  and the cap layer material  420 . The gate electrode  416  and the cap layer are thereby formed. (Step S 112 ) 
     Ion implantation for forming the LDD region  412   a  and  414   a  is performed by using the cap layer  420  as the mask. This implantation makes lightly doped regions  412   a  and  414   a . (Step S 113 ) 
     A SiN sidewall layer, having a thickness from 100 nm to 200 nm, is formed on the semiconductor substrate using LP-CVD. An anisotropic etching technique, such as a RIE method, is employed to etch the SiN sidewall layer so that SiN sidewalls  422  are formed. (Step S 114 ) 
     Ion implantation for forming the source region  412  and drain region  414  is performed using the cap layer  420  and sidewalls  422  as a mask. An annealing is performed after the ion implantation. This annealing diffuses implanted ion and forms source region  412  and drain region  414 . ( FIG. 12(   a ), Step S 115 ) 
     The intermediate insulating layer  404  is formed on the semiconductor substrate  402 . The intermediate insulating layer  404  is made of BPSG in this embodiment. ( FIG. 12(   b ), Step S 116 ) 
     A silicon oxide layer  426  is formed on the gate oxide layer  424  using thermal oxidation. The thermal oxidation of this embodiment is performed at a temperature of over 850° C. and in an oxygen atmosphere. Thickening begins from the edge portion  422   a  of the side walls, and expands into the portion near the gate electrode  416 . The time of this oxidation is controlled to expand the thickness of the gate oxide layer other than at the portion lying under the gate electrode  416 . This silicon oxide layer  426  works as the diffusion deterrent layer. The oxide layer  426  has a thickness of about 20 nm. Subsequent steps are the same as those in the third embodiment. ( FIG. 12(   c ), Step S 118 ) 
     In this embodiment, the thermal oxidation is performed after the formation of the sidewalls and source/drain regions. Hydrogen and nitrogen in the sidewalls are diffused into the surface of silicon substrate during annealing. However, the thermal oxidation oxidizes the surface of silicon substrate. Therefore, interface traps, which are related to hot carrier, are reduced, and reliability is improved. An oxide layer on the side surface of the gate electrode is not formed in this embodiment. Therefore, the variation in resistance of the gate electrode is prevented. 
     The surface of the intermediate insulating layer  404  is flattened during thermal oxidation because the intermediate insulating layer is made of BPSG. Therefore, manufacturing is simplified in this embodiment. 
       FIG. 13  is a schematic diagram of this embodiment. As shown in  FIG. 13 , the semiconductor device of this embodiment has a structure which is similar to that of the prior art. In this embodiment, however, the method for manufacturing the semiconductor device is different from the prior art. 
       FIG. 14  is a flow chart of the method for manufacturing the semiconductor device of this embodiment, and  FIG. 15  is a cross sectional view showing the method for manufacturing the same. The method for manufacturing the semiconductor device of this invention is described below. 
     The gate oxide layer  524  is formed on the surface of the semiconductor substrate  502  by using thermal oxidation. This gate oxide layer  524  has a thickness of about 10 nm. (Step S 141 ) 
     The gate electrode material  516  and the cap layer material  520  are formed on the gate oxide layer  524 . A lithography method and an anisotropic etching technique, such as a RIE method, are employed to etch the gate electrode material  516  and the cap layer material  520 . The gate electrode  516  and the cap layer are thereby formed as seen in  FIG. 15(   a ). (Step S 142 ) 
     Ion implantation for forming the LDD region  512   a  and  514   a  is performed using the cap layer  520  as a mask. This implantation makes lightly doped regions  512   a  and  514   a . (Step S 143 ) 
     A SiN sidewall layer, having a thickness from 100 nm to 200 nm, is formed on the semiconductor substrate using LP-CVD. The formation of the SiN sidewall layer is performed at a temperature of over 850° C. In experiments, the inventors have shown that high temperature formation of the SiN sidewall reduces the hydrogen that diffuses into the semiconductor substrate. An anisotropic etching technique, such as a RIE method, is employed to etch the SiN sidewall layer, so that SiN sidewalls  522  are formed. ( FIG. 15(   b ), Step S 144 ) 
     Ion implantation for forming the source region  512  and drain region  514  is performed using the cap layer  520  and sidewalls  522  as a mask. An annealing is performed after the ion implantation. This annealing diffuses implanted ions and forms source region  512  and drain region  514 . ( FIG. 15(   c ), Step S 145 ) 
     The intermediate insulating layer  504  is formed on the semiconductor substrate  502 . The intermediate insulating layer  504  is made of a material which is different from the material of the cap layer  520  and the side walls  522 . The intermediate insulating layer  104  is made of silicon oxide in this embodiment. (Step S 146 ) 
     The first contact holes  506   a  are formed using a SAC process. The intermediate insulating layer  504  is etched using an etchant which has a smaller etching rate for SiN than for silicon-oxide. Therefore, the SiN sidewalls are used as a stopper. The intermediate layer  504  and the silicon oxide  524  over the source region and drain region are etched in this step. (Step S 147 ) Subsequent steps are the same as those of other embodiments. 
     In this embodiment, high temperature formation of SiN sidewalls reduces the hydrogen and nitrogen that diffuses into the silicon substrate  502 . For example, amount of hydrogen which diffuses into the semiconductor substrate when the sidewalls are made at 850° C. is about one-third of that made at 780° C. 
     Therefore, interface traps, which are related to hot carrier, are reduced near the surface of the semiconductor substrate, and the reliability of the MOSFET is improved. 
       FIG. 16  is a schematic diagram of this embodiment. As shown in  FIG. 16 , The SiN sidewalls of this embodiment have two layers. 
       FIG. 17  is a flow chart of a method for manufacturing the semiconductor device of this embodiment, and  FIG. 18  is a cross sectional view showing the method for manufacturing the same. The method for manufacturing the semiconductor device of this embodiment is described below. 
     The gate oxide layer  624  is formed on the surface of the semiconductor substrate  602  by using thermal oxidation. This gate oxide layer  624  has a thickness of about 10 nm. (Step S 171 ) 
     The gate electrode material  616  and the cap layer material  620  are formed on the gate oxide layer  624 . A lithography method and an anisotropic etching technique, such as a RIE method, are employed to etch the gate electrode material  616  and the cap layer material  620 . The gate electrode  616  and the cap layer are thereby formed. (Step S 172 ) 
     Ion implantation for forming the LDD region  612   a  and  614   a  is performed by using the cap layer  620  as the mask. This implantation makes lightly doped regions  612   a  and  614   a . (Step S 173 ) 
     A first SiN sidewall layer  622   a , having a thickness from 20 nm to 40 nm, is formed on the semiconductor substrate using LP-CVD. The formation of the first SiN sidewall layer is performed at a temperature exceeding 850° C. as shown in  FIG. 18(   a ). (Step S 174 ) The high temperature formation of the SiN sidewall reduces the hydrogen that diffuses into the semiconductor substrate. Then, a second SiN sidewall layer  622   b , having a thickness from 80 nm to 160 nm, is formed on the first sidewall layer using LP-CVD. ( FIG. 18(   b ) The formation of the second SiN sidewall is performed at a temperature of about 780° C. An anisotropic etching technique, such as a RIE method, is employed to etch first and second SiN sidewall layers, so that SiN sidewalls  622  are formed as shown in  FIG. 18(   c ). (Step S 175 ) 
     Ion implantation for forming the source region  612  and drain region  614  is performed by using the cap layer  620  and sidewalls  622  as a mask. An annealing is performed after the ion implantation. This annealing diffuses implanted ions and forms source region  612  and drain region  614 . (Step S 176 ) 
     The intermediate insulating layer  604  is formed over the semiconductor substrate  602 . The intermediate insulating layer  604  is made of a material which is different from the material of the cap layer  620  and the side walls  622 . The intermediate insulating layer  604  is made of silicon oxide in this embodiment. (Step S 177 ) 
     The first contact holes  606   a  are formed using a SAC process. The intermediate insulating layer  604  is etched using an etchant which has a smaller etching rate for SiN than for silicon-oxide. Therefore, the SiN sidewalls are used as a stopper. The intermediate layer  604  and the silicon oxide  624  over the source region and drain region are etched in this step. Subsequent steps are the same as those of the other embodiments. (Step S 178 ) 
     In this embodiment, high temperature formation of the first SiN sidewalls reduces the hydrogen and nitrogen that diffuses into the silicon substrate  602  and the first SiN layers, which are formed at high temperature, prevent hydrogen and nitrogen in the second sidewalls from diffusing into the silicon substrate  102 . Therefore, interface traps, which are related to hot carrier, are reduced near the surface of the semiconductor substrate, and the reliability of the MOSFET is improved. 
       FIG. 19  is a schematic diagram of this embodiment. As shown in  FIG. 19 , The impurity concentration of the LDD of this embodiment regions is different from that of the prior art. The LDD portion  712   a  of this embodiment has a shallow portion  712   a   1  near the surface of the semiconductor substrate, and the deep portion  712   a   2  formed under the shallow portion  712   a   1 . The LDD portion  714   a  of this embodiment has a shallow portion  714   a   1  near the surface of the semiconductor substrate, and the deep portion  714   a   2  formed under the shallow portion  714   a   1 . 
       FIG. 22  shows the impurity concentration of the LDD regions of this embodiment. In  FIG. 22 , the dotted line shows an impurity concentration of the prior art. As shown in  FIG. 22 , the peak of the impurity concentration of this embodiment is deeper than that of the prior art. This peak is made in the deep portion  712   a   2  and  714   a   2 . The depth of these deep portions are about 0.1 μm from the surface of the silicon substrate. 
     The hot carrier generation region is deeper than that of the prior art, because the peak of the impurity concentration is formed in a deeper portion of the substrate. 
       FIG. 20  is a flow chart of the method for manufacturing the semiconductor device of this embodiment, and  FIG. 21  is a cross sectional view showing the method for manufacturing the same. The method for manufacturing the semiconductor device of this invention is described below. 
     The gate oxide layer  724  is formed on the surface of the semiconductor substrate  702  by using thermal oxidation. This gate oxide layer  724  has a thickness of about 10 nm. (Step S 201 ) 
     The gate electrode material  716  and the cap layer material  720  are formed on the gate oxide layer  724 . A lithography method and an anisotropic etching technique, such as a RIE method, are employed to etch the gate electrode material  716  and the cap layer material  720 . The gate electrode  716  and the cap layer are thereby formed. (Step S 202 ) 
     A first ion implantation for forming the shallow portion  712   a   1  and  714   a   1  of LDD regions is performed using the cap layer  720  as a mask. This implantation is performed at an acceleration voltage of 20 keV. ( FIG. 21(   a ), Step S 203 ) 
     Then, a second ion implantation for forming the deep portion  712   a   2  and  714   a   2  of LDD regions is performed using the cap layer  720  as a mask. This implantation is performed at an acceleration voltage of 70 keV. (Step S 204 ) 
     A SiN sidewall layer, having a thickness of from 100 nm to 200 nm, is formed on the semiconductor substrate using LP-CVD. 
     An anisotropic etching technique, such as a RIE method, is employed to etch the SiN sidewall layer, so that SiN sidewalls  722  are formed. (Step S 205 ) 
     Ion implantation for forming the source region  712  and drain region  714  is performed by using the cap layer  720  and sidewalls  722  as a mask. An annealing is performed after the ion implantation. This annealing diffuses implanted ions and forms source region  712  and drain region  714 . (Step S 206 ) 
     The intermediate insulating layer  704  is formed on semiconductor substrate  702 . The intermediate insulating layer  704  is made of a material which is different from the material of the cap layer  720  and the side walls  722 . The intermediate insulating layer  704  is made of silicon oxide in this embodiment. (Step S 207 ) 
     The first contact holes  706   a  are formed using a SAC process. The intermediate insulating layer  704  is etched using an etchant which has smaller etching rate for SiN than than for silicon-oxide. Therefore, the SiN sidewalls are used as a stopper. The intermediate layer  704  and the silicon oxide  724  located over the source region and drain region are etched in this step. Subsequent steps are the same as those of other embodiments. 
     The hot carrier region is made deeper in this embodiment. Therefore, the trapping of hot carriers near the surface of the semiconductor substrate is decreased, and the reliability of the MOSFET is improved.