Abstract:
Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is related to the following U.S. Patent Applications, which are hereby incorporated by reference herein in its entirety: 
         [0002]    IBM Docket No. ROC920070125US1, filed herewith titled “Controlling Impedance and Thickness Variations for Multilayer Electronic Structures”. 
         [0003]    IBM Docket No. ROC920080067US1, filed herewith titled “Controlling Impedance and Thickness Variations for Multilayer Electronic Structures”. 
     
    
     BACKGROUND 
       [0004]      FIGS. 1A-1C  illustrate the current state of the art in developing at least one type of multilayer electronic structure. A core comprises at least one layer of copper a layer of bonding film (e.g., FR4, etc.), and a second layer of copper. Selected locations of the second layer of copper are removed (e.g., etched), leaving intact copper signal traces that provide for the internal circuitry of the electronic structure. Bonding film is laminated between a first core and a second core to provide a multilayer electronic structure. When signal trace density changes (i.e., in a first location on the core there are numerous signal traces, and in a second location there are very few, if any, signal traces,) the distance from the signal traces to a reference ground layer varies across the PCB. This variation of distance results in variations in mechanical thickness, impedance, and electrical performance of the multilayer electronic structure. 
         [0005]    For example see  FIG. 1A .  FIG. 1A  depicts a prior art multilayer electronic structure having a single isolated signal trace. For instance if the signal trace is 4 mils wide, 0.7 mils thick, and the bonding film is 4 mils thick, after lamination the distance from the top of the signal trace to the adjacent reference ground layer approaches 3.3 mils. 
         [0006]    Alternatively see  FIG. 1B .  FIG. 1B  depicts a prior art multilayer electronic structure having a signal trace nestled between two wide traces (e.g., power signal trace, ground signal trace, etc.). For instance if the signal trace is 4 mils wide, 0.7 mils thick, and the bonding film is 4 mils thick, after lamination the distance from the top of the signal trace to the adjacent reference ground layer approaches 4.0 mils. 
         [0007]    Alternatively see  FIG. 1C .  FIG. 1C  depicts a prior art multilayer electronic structure having a single trace nestled between two other signal traces. For instance if each signal trace is 4 mils wide, 0.7 mils thick, and the bonding film is 4 mils thick, after lamination the distance from the top of the signal traces to the adjacent reference ground layer approaches 3.65 mils. 
         [0008]    In the examples depicted in  FIGS. 1A ,  1 B, and  1 C, the distance from the top of the signal traces to the adjacent reference ground layer by itself leads to impedance differences of 48-51-53 Ohms respectively. 
         [0009]    In the current state of the art, impedance and mechanical (i.e., thickness) tolerance requirements are tight and may in fact become tighter. Currently impedance tolerances of ±10% are typical (e.g., 50 Ohms±5 Ohms). In the future, impedance tolerances of ±7.5% or 5.0% may become more common. In the examples depicted in  FIGS. 1A ,  1 B, and  1 C, 50% of the ±10.0% tolerance is taken up by the effect of the distance variations from the top of the signal trace to the adjacent reference ground layer. 
       SUMMARY 
       [0010]    The present invention generally relates to multilayer electronic structures (i.e., electronic structure (PCB), microstrip, coplanar PCB, stripline, etc., or any such equivalent multilayer structures.) and method(s) relating to the multilayer electronic structures. 
         [0011]    Herein multilayer electronic structures may be referred to generally as electronic structures. In other words, the terms multilayer electronic structure, electronic structure, PCB, microstrip, etc. may be used interchangeably. 
         [0012]    Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. 
         [0013]    In an embodiment of the present invention characteristic impedance variations due to non uniformity in both signal density and dielectric bonding film thickness are improved. In other words, the cross section thickness across the entire electronic multilayer structure is more uniform. 
         [0014]    In another embodiment a method of multilayer electronic structure manufacture comprises: removing material of a dielectric layer, and laminating the dielectric layer to a core, wherein the material of the dielectric layer is removed in locations such that when the dielectric layer is laminated to the core the locations having material removed correspond to the locations upon the core having signal traces. In other words the dielectric layer is removed only in locations that mirror signal trace locations. In another embodiment the amount of dielectric material removed is proportional to the density of signal traces upon the core. In another embodiment the volume of removed dielectric material is approximately equal to the volume of the signal traces. 
         [0015]    In another embodiment the method of multilayer electronic structure manufacture further comprises determining an optimum impedance, and adjusting the amount of dielectric material to be removed based on the optimum impedance. In another embodiment the method of multilayer electronic structure manufacture further comprises determining an optimum via size or via density, and adjusting the amount of dielectric material to be removed based on the optimum via size or via density. 
         [0016]    In another embodiment a multilayer electronic structure comprises a dielectric layer comprising at least a displaced section of the dielectric layer having had material removed and a original section of the dielectric layer not having had material removed, and; a core layer comprising at least one signal trace thereupon; wherein when the dielectric is positioned versus the core layer the displaced section corresponds to a location of the core having at least one signal trace thereupon. 
         [0017]    In another embodiment the removed location corresponds to the location of the at least one signal trace after the dielectric layer is laminated to the core layer. In another embodiment the amount of dielectric material removed is proportional to the volume of the at least one signal trace. In another embodiment the amount of dielectric material removed is approximately equal to the volume of the at least one signal trace. 
         [0018]    In another embodiment a method of multilayer electronic manufacture comprises characterizing bonding film and laminating the characterized bonding film to a core layer. In another embodiment characterizing bonding film comprises selectively removing material of the bonding film resulting in at least a displaced section of the bonding film having had material removed, and a original section of the bonding film not having had material removed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. 
           [0020]    It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
           [0021]      FIG. 1A  depicts a prior art multilayer electronic structure section having a single isolated signal trace. 
           [0022]      FIG. 1B  depicts a prior art multilayer electronic structure section having a signal trace nestled between two wide signal traces. 
           [0023]      FIG. 1C  depicts a prior art multilayer electronic structure section having a single trace nestled between two other signal traces. 
           [0024]      FIG. 2A  depicts an exploded view of the components of a multilayer electronic structure, utilizing characterized boding film, according to an embodiment of the present invention. 
           [0025]      FIG. 2B  depicts the multilayer electronic structure of  FIG. 2A , after lamination, according to an embodiment of the present invention. 
           [0026]      FIG. 2C  depicts an isometric exploded view of a particular multilayer electronic structure utilizing characterized bonding film, according to an embodiment of the present invention. 
           [0027]      FIG. 2D  depicts an isometric view of an alternative example of the displaced section and original section of characterized bonding film. 
           [0028]      FIG. 3A  depicts an exploded view of the components of a multilayer electronic structure, utilizing characterized boding film, according to an embodiment of the present invention. 
           [0029]      FIG. 3B  depicts the multilayer electronic structure of  FIG. 3A  according to an embodiment of the present invention. 
           [0030]      FIG. 4  depicts a process of generating equalization data used to equalize thickness and/or impedance tolerances in multilayer electronic structures, according to an embodiment of the present invention. 
           [0031]      FIG. 5A  depicts a top view of a section of a multilayer electronic structure having a signal trace thereupon wherein cells are utilized to determine the signal trace density. 
           [0032]      FIG. 5B  depicts a side view a section of a multilayer electronic structure having three signal traces thereupon wherein cells are utilized to determine thickness and/or impedance. 
           [0033]      FIG. 6  depicts a process of generating equalization data utilizing the signal trace density of particular layers of multilayer electronic structure, according to an embodiment of the present invention. 
           [0034]      FIG. 7  depicts a process of generating equalization data utilizing the thickness/impedance of a particular layer(s) of a multilayer electronic structure, according to an embodiment of the present invention. 
           [0035]      FIG. 8  depicts a method of multilayer electronic structure manufacture according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0036]    Referring to the drawings, wherein like numbers denote like parts throughout the several views, please refer to  FIG. 2A .  FIG. 2A  depicts an exploded multilayer electronic structure, according to an embodiment of the present invention. The exploded multilayer electronic structure comprises a first layer (e.g., core  20 , etc.), a second layer (e.g., copper ground  15 , etc.), and characterized bonding film  22  utilized to bond the first and second layers together. For example, characterized bonding film may bond two different core  20  layers together, or may bond a single core  20  layer with a copper ground  15  layer. Other layer types may be bonded together without deviation from the scope of the present invention. The copper ground  15  layer may itself be a layer, or may be the bottom of a second core  20 . 
         [0037]    Core  20  comprises a copper ground  14  (may be used as a reference ground layer), a layer of bonding film  24  (e.g., FR4, etc.), and a second layer of copper. Selected locations of the second layer of copper are removed (e.g., etched), leaving intact copper signal traces that provide for the internal circuitry of the electronic structure. In the embodiment shown by  FIG. 2A , the second layer of copper is etched leaving a signal trace  18  nestled between two wide signal traces  16 . 
         [0038]    Characterized bonding film  22  comprises a sheet of bonding film  21  with displaced sections  23 . Displaced sections  23  may be removed by various removal techniques or apparatus (drilling, etching, scraping, chemically, mechanically, laser, etc) without deviating from the scope of the present invention. The geometry of displaced sections  23  depend on the removal technique or apparatus utilized to remove the bonding film sections. The amount and location of the removal of sections  23  depend on the density and location of the various signal traces (i.e., signal trace  18 ,  16 , etc.). The more signal traces upon core  20 , the more displaced sections  23 . In certain embodiments the volume of displaced sections  23  is approximately equal to the volume of removed copper (the remaining copper being the various signal traces). In yet other embodiments the displaced sections  23  are located such that when the characterized bonding film is bonded to core  20 , the displaced sections  23  correspond the locations of the various signal traces (signal traces  16  and  18 , etc). In certain embodiments, bonding film  21  and bonding film  24  are the same type of material; however the materials need not be similar. 
         [0039]      FIG. 2B  depicts the multilayer electronic structure of  FIG. 2A  after lamination, according to an embodiment of the present invention. By utilizing characterized bonding film  22 , the effect of the distance variations from the top of signal trace  18  to the adjacent reference ground layer (i.e., copper ground  15 ) is greatly reduced, if not eliminated. Please refer back to  FIG. 1B , wherein a similar core configuration resulted in a distance (the distance from the top of the signal trace to the adjacent reference ground layer) of 4.0 mils as compared to a distance of 3.3 mils when utilizing the characterized bonding film  22 . 
         [0040]    By utilizing characterized bonding film  22 , a designer may calculate a desired distance between the top of a signal trace to the adjacent reference ground layer or a desired impedance. Via size and signal trace density may be determined in order to provide the desired distance and/or impedance. The designer would then adjust the amount and location of displaced sections  23  accordingly, to achieve the desired distance/impedance. 
         [0041]    In certain other embodiments the designer may also characterize the bonding film by removing a uniform thickness (or other geometry) from the bonding film in addition to or in lieu of the displaced sections  23  as described above. 
         [0042]    Please refer to  FIG. 2C .  FIG. 2C  depicts an exploded multilayer electronic structure, according to an embodiment of the present invention. Upon core  20 , there comprises a high density signal trace area  27  at least having more signal traces as compared to other locations upon core  20 . Similarly, characterized bonding film  22  comprises a characterized area  26  at least having an increased number of displaced sections  23  as compared to other locations of bonding film  22 . Characterized area  26  is arranged on characterized bonding film  22  such that when laminated to core  20 , the characterized area  26  corresponds to high density signal trace area  27 . In other words characterized bonding film  22  is configured such that there are more displaced sections  23  in higher dense signal trace areas. 
         [0043]      FIG. 2D  depicts an alternative embodiment of characterized bonding film, having an alternative displaced section geometry, in accordance with the present invention.  FIG. 2D  shows characterized bonding film  22  having displaced sections  32  being rectangular; however in other embodiments displaced sections  32  are other geometries. Displaced sections  32  may be removed by various removal techniques or apparatus (drilling, etching, scraping, chemically, mechanically, laser, etc) without deviating from the scope of the present invention. The geometry of displaced sections  32  depend on the removal technique or apparatus utilized to remove bonding film mater. 
         [0044]      FIG. 3A  depicts an exploded multilayer electronic structure, according to an embodiment of the present invention. The exploded multilayer electronic structure comprises a first layer (e.g., core  20 , etc.), a second layer (e.g., copper ground  15 , etc.), and characterized bonding film  22  utilized to bond the first and second layers together. For example, characterized bonding film may bond two different core  20  layers together, or may bond a single core  20  layer with a copper ground  15  layer. Other layer types may be bonded together without deviation from the scope of the present invention. The copper ground  15  layer may itself be a layer, or may be the bottom of a second core  20 . 
         [0045]    Core  20  comprises a copper ground  14  (may be used as a reference ground layer), a layer of bonding film  24  (e.g., FR4, etc.), and a second layer of copper. Selected locations of the second layer of copper are removed (e.g., etched), leaving intact copper signal traces that provide for the internal circuitry of the electronic structure. In the embodiment shown by  FIG. 3A , the second layer of copper is etched leaving signal traces  18 . 
         [0046]      FIG. 3B  depicts the multilayer electronic structure of  FIG. 3A  after lamination, according to an embodiment of the present invention. By utilizing characterized bonding film, the effect of the distance variations from the top of signal trace  18  to the adjacent reference ground layer (i.e., copper ground  15 ) is greatly reduced, if not eliminated. Please refer back to  FIG. 1C , wherein a similar core configuration resulted in a distance (the distance from the top of the signal trace to the adjacent reference ground layer) of 3.65 mils as compared to a distance of 3.3 mils when utilizing the characterized bonding film  22 . 
         [0047]    By utilizing characterized bonding film  22  a constant distance from the top of the signal trace to the adjacent reference ground layer occurs in multiple signal trace configurations. This constant distance reduces the impedance tolerance across the multilayer circuit board. 
         [0048]    Please refer to  FIG. 4 .  FIG. 4  depicts a process  60  of generating equalization data utilized to equalize thickness and/or impedance variations across a multilayer electronic structure, according to an embodiment of the present invention. Process  60  begins at block  61 . In order to determine the geometrical and/or manufacturing properties (quantity, location, etc.) of characterized bonding film  22 , equalization data is created. Equalization data is utilized to equalize thickness and/or impedance variations across a multilayer electronic structure. Equalization data represents the data associated with characterized bonding film  22  (i.e., the locations of displaced sections  23 , etc.). An equalization data matrix is the equalization data of at least two locations of the multilayer electronic structure. In an alternative embodiment, the equalization data matrix is the equalization data of the entire multilayer electronic structure. Creating equalization data may be dependent on determining the signal trace density of a particular area (block  64 ) of the circuit card. In other embodiments, discussed infra, equalization data may be dependent on determining circuit board layer(s) thickness/impedance (block  64 ). The particular location of the electronic structure considered is referred to as a cell. The cell may be a two dimensional area or a three dimensional volume. The area/volume of the cell is adjustable, however the smaller the area/volume of a cell, better equalization data may be created. When a generation of cells (block  62 ) in/from/to the computer aided design (CAD) data of the multilayer electronic structure occurs, equalization data may be created for each cell. When there is more than one cell, the equalization data matrix is created (block  66 ). Once generated, the equalization data, or equalization data matrix, may be transferred (block  68 ), for example to a card manufacturer. Process  60  ends at block  69 . 
         [0049]    Please refer to  FIG. 5A  and  FIG. 6  concurrently.  FIG. 5A  depicts a top view of a multilayer electronic structure layer having a signal trace thereupon and also comprising a baseline cell  150 , and cells  151 - 153 .  FIG. 6  depicts another process  70  of determining the signal trace density of each cell and the generating equalization data, according to an embodiment of the present invention. Process  70  starts at block  72 . Upon generating of cells in/from/to the CAD data (block  62  shown in  FIG. 4 ), a baseline cell  150  is identified (block  74 ). The baseline cell  150  has a corresponding baseline signal trace density (for instance the percentage of the cell filled by the signal traces). In a particular embodiment, shown in  FIG. 5A , the baseline cell  150  is a cell having no signal trace(s) within. In another embodiment, the baseline cell is completely filled by a signal trace. In other embodiments the baseline cell may have any percentage of the cell encapsulating a signal trace, however it is preferable that the baseline entirely encapsulates a signal trace, or does not encapsulate any signal trace. The base line cell  150  (and/or baseline cell signal trace density) is compared to another cell (and/or another cell signal trace density) (block  76 ). If the resultant of the comparison indicates that there is more/less signal trace(s) in the another cell, equalization data is generated for the another cell (block  82 ). Take for example, FIG.  5 A. The baseline cell  150  encapsulates no signal trace(s), cell  153  also encapsulates no signal trace(s), cell  152  is 50% filled by a signal trace and 50% not filled by a signal trace, and finally cell  151  entirely encapsulates a signal trace(s). A preset maximum comparison signal trace density value (block  78 ) is set, for example at 0.10, meaning that equalization data is generated for the another cell if the another cell has a signal trace density of greater than 10% of the baseline cell. The maximum preset comparison signal trace density value may be adjustable by a user. Cell  152  (50% filled, 50% not filled) has a signal trace density of 0.5 because it is half filled by a signal trace. Cell  153  has a signal trace density of 0.0 because it does not encapsulate a signal trace. Cell  151  has a signal trace density of 1.0 because it does entirely encapsulate a signal trace. Because 1.0 and 0.5, respectively exceeds the maximum comparison signal trace density value of 0.1, equalization data is generated for cell  152  and  151  (block  82 ). If however the actual signal trace density value does not exceed the preset maximum signal trace density value of 0.1, such as cell  153 &#39;s value of 0.0, equalization data is not generated for cell  153  (block  80 ). In another embodiment equalization data is generated for cell  153  indicating that no characterization shall occur in the location of the characterized bonding film in the corresponding location. Process  70  ends at block  84 . 
         [0050]    In a particular embodiment equalization data is generated for use relating to characterized bonding film  22  utilizing the cell structure exemplified in  FIG. 5A . In this particular embodiment the equalization data indicates the locations and quantity of material to be removed from bonding film  21 . Please continue the example from above (i.e., baseline cell  150  encapsulates no signal trace(s), cell  153  also encapsulates no signal trace(s), cell  152  is 50% filled by a signal trace and 50% not filled by a signal trace, and finally cell  152  entirely encapsulates a signal trace(s)). Signal trace properties are determined or are known (i.e., height and width, etc.). The area of each cell is known or is determined. Each cell is analyzed whereby it is determined that 50% of the cell  152  is filled by a signal trace(s). Assume each cell&#39;s area is 0.5 mil square, and the thickness of the signal trace  18  is 1.4 mils. Therefore, 0.25 mil square of cell  152  is filled by the signal trace  18 , (50% of the cell area). Thus, 0.25 mil square×the signal trace  18  height (1.4 mils)=0.35 cubic mils. This volume therefore is the approximate volume that needs to be removed from bonding film  21  in the particular location that corresponds with cell  152 . Again the location corresponds if after lamination the particular location of the electronic structure layer (where the particular cell was located) is laminated with the bonding film that has the particular displaced section. Any such volume approximately being 0.35 cubic mils may be removed from the bonding film in the corresponding location (i.e., the geometry of the displaced section may be any such geometry without departing from the scope of the present invention). 
         [0051]    Please refer to  FIG. 5B  and  FIG. 7  concurrently.  FIG. 5B  depicts a side view of a multilayer electronic structure core  20  having signal traces thereupon, further depicting baseline cell  160 , and cells  161 - 163 .  FIG. 7  depicts yet another alternative process of determining the signal trace impedance/width of each cell and generating equalization data, according to an embodiment of the present invention. Process  90  starts at block  92 . Upon generating cells in/from/to the CAD data (block  62 , shown in  FIG. 4 ), a baseline cell  160  is identified (block  94 ). The cells (baseline and others), as contemplated in utilizing process  90 , may be three dimensional volumes. The baseline cell  160  encapsulates a section of the at least one CAD circuit card layer. Therefore the baseline cell  160  has a particular first dimension, second dimension, and a third dimension that corresponds to the thickness of the at least one CAD circuit card layer. In a particular embodiment, the baseline cell is a cell encapsulating a section of core  20  and no signal trace(s) (not shown). In another embodiment the base line cell  160  encapsulates a section of core  20  and a signal trace (as shown in  FIG. 5B ). It may be preferred to create the baseline cell  160  such that the cell has the largest volume possible without empty space above and below the particular circuit board layer(s). In another embodiment the other cell (i.e., cells  161 - 163 ) volume equals the volume of baseline cell  160 . In other embodiments the volumes of the other cells do not equal the volume of the baseline cell. Further, the volume of cell  161  for instance, may not equal the volume of cell  162 . For example because there is empty space in cell  161 , cell  161  may be shortened such that the height would be similar to the height of the copper ground  14  and bonding film  24  stack. In another embodiment in an instance where there is empty space in a cell (i.e., cell  161  and  162 ) the height of those cells are shortened by a distance similar to the distance of the signal trace  18  height. 
         [0052]    Baseline cell  160  has a baseline thickness/impedance. The baseline cell  160  thickness/impedance is compared to another cell&#39;s (cell  161 - 163 ) thickness/impedance (block  96 ). If the resultant of the comparison indicates that the delta exceeds a maximum signal trace comparison value (block  98 ), equalization data is generated for the another cell (block  102 ). In a new example, the baseline cell  160  encapsulates the at least one layer of a electronic structure (e.g., copper ground  14  and bonding film  24 ) and at least part of a signal trace  18 . In the present embodiment, as shown in  FIG. 5B , the dimension of cells  161 - 163  are set similarly to the dimensions of the baseline cell  160 , however as indicated above the volumes of each cell need not be similar. Cell  163  similarly encapsulates the at least one layer of a electronic structure and at least part of a signal trace  18 . Cell  162  encapsulates the at least one layer of an electronic structure and at least part of a signal trace  18 , but also encapsulates empty space (i.e., space without a section of signal trace  18 ). Cell  161  encapsulates the at least one layer of a electronic structure and does not encapsulate at least part of a signal trace  18  (i.e., cell  161  has more empty space than  162 ). Thus cells  161 - 163  demonstrate the transition from a location of a electronic structure layer going from at least one layer without a signal trace there upon (cell  161 ), to a location where part of the cell encapsulates a signal trace and part of the cell does not (cell  162 ), to a location of a layer with a signal trace there upon (cell  163 ). 
         [0053]    A preset maximum comparison impedance/thickness value (block  98 ) is generated, meaning that equalization data is generated (block  102 ) for the another cell if the another cell has thickness/impedance greater than the baseline cell. The maximum preset comparison value may be adjustable. If however the actual impedance/thickness value does not exceed the preset maximum comparison value, equalization data is not generated for the another cell (block  100 ). Process  90  ends at block  104 . 
         [0054]    In a particular embodiment equalization data is generated for use relating to characterized bonding film  22 , utilizing the cell structure exemplified in  FIG. 5B . In this particular embodiment the equalization data indicates the locations and quantity of material to be removed from bonding film  21  (thereby creating characterized bonding film). Please consider the example depicted in  FIG. 5B . Cells may be generated in multiple configurations, two such configurations are depicted in  FIG. 5B . Cells  161 - 163  depict cells of similar geometries, and cells  164 - 166  depict cells of varying geometries. The volume of each cell is known or is determined. Equalization data is created for each cell. 
         [0055]    For example cell  164  is compared with cell  166 . The volume differential of cell  166  and  164  would represent the equalization data for cell  166 . The impedance/height of the cells may also be translated into a volume. This volume differential would be the volume of material that is to be removed from characterized bonding film  22  in the location that corresponds to cell  166 . 
         [0056]      FIG. 8  depicts a method of multilayer electronic structure manufacture according to an embodiment of the present invention. Method  110  begins at block  112  and may be practiced, for example, by a card manufacturer. The equalization data matrix is read (block  114 ) to determine the particular areas to be removed from a sheet of bonding film, thus creating characterized bonding film  22 . The particular areas of the bonding film that will correspond to high signal trace density after lamination are removed (block  116 ) thereby creating characterized bonding film  22 . The characterized bonding film  22  is then laminated (block  118 ) to the core such that the characterized area  26  corresponds to the high density signal trace area  27 . Method  110  ends at block  120 . 
         [0057]    The accompanying figures and this description depicted and described embodiments of the present invention, and features and components thereof. Those skilled in the art will appreciate that any particular program nomenclature used in this description was merely for convenience, and thus the invention should not be limited to use solely in any specific application identified and/or implied by such nomenclature.