Abstract:
In at least one embodiment, a TFT includes: a first capacitor formed of a first capacitor electrode connected to a source electrode and a second capacitor electrode; a second capacitor formed of a third capacitor electrode and a fourth capacitor electrode; a first lead-out line; a second lead-out line connected to a gate electrode; a third lead-out line; a fourth lead-out line; a first interconnection; and a second interconnection. This realizes a TFT which can be easily saved from being a defective product even if leakage occurs in a capacitor connected to a TFT body section.

Description:
TECHNICAL FIELD 
     The present invention relates to a TFT including a capacitor that is added between a gate and a source. 
     BACKGROUND ART 
     In recent years, monolithic integration of a gate driver has been developed for the purpose of cost reduction. In the monolithic integration, the gate driver is formed from amorphous silicon on a liquid crystal panel. The term “monolithic gate driver” is also associated with the terms such as “gate driver-free”, “built-in gate driver in panel”, and “gate in panel”. For example, Patent Literature 1 discloses shift registers of monolithic gate drivers. 
       FIG. 11  shows circuit configuration of each shift register stage disclosed in Patent Literature 1. 
     The following describes essential structure and operations of this circuit.  FIG. 11  shows the structure of an n-th stage of shift register stages cascaded with each other. To an input terminal  12 , a gate output from a preceding stage is supplied. This supply causes an output transistor  16  to be turned ON through a drain of a transistor  18 . A bootstrap capacitor  30  is connected between a gate and a source of the output transistor  16 . When a clock signal C 1  in High level is supplied to the output transistor  16  from its drain side during ON-state of the output transistor  16 , a gate potential of the output transistor  16  sharply increases to a level greater than power source voltage due to capacitive coupling between the gate and source of the output transistor  16  through the bootstrap capacitor  30 . This substantially decreases a resistance between the source and drain of the output transistor  16 . Then, the clock signal C 1  in High level is outputted to a gate bus line  118 , and this gate output is supplied to an input of a subsequent stage. 
       FIG. 12  shows a plan view of elements used when such a bootstrap capacitor is built into a display panel. 
     A bootstrap capacitor  101   b  shown in  FIG. 12 , as part of a TFT  101 , is connected to a TFT body section  101   a . In a case where a display panel is made from amorphous silicon or the like material with lower mobility, it is a widespread practice that the TFTs monolithically built into the display panel are patterned to have a much larger channel width than standard for decrease in resistance between a source and drain of the TFT body section  101   a . Therefore, the TFT body section  101   a  shown in  FIG. 11  secures a large channel width, with such an arrangement that comb-shaped source electrode  102  and drain electrode  103  are arranged to be mutually opposed in such a manner that the source electrode  102  and the drain electrode  103  are engaged with each other. Under a region of the engagement between the source electrode  102  and the drain electrode  103 , a gate electrode  104  is provided. The bootstrap capacitor  101   b  is formed such that a first capacitor electrode  102   a  led out from the source electrode  102  of the TFT body section  101   a  and a second capacitor electrode  104   a  led out from the gate electrode  104  of the TFT body section  101   a  are arranged to be stacked and mutually opposed across a gate dielectric layer therebetween. 
     In addition, the first capacitor electrode  102   a  is connected to an output OUT of a shift register stage, and the output OUT is connected to a gate bus line GL via a contact hole  105 . 
       FIG. 13  shows a cross-sectional view taken along the line X-X′ in  FIG. 12 . 
     As shown in the cross-sectional view of  FIG. 13 , the arrangement in  FIG. 13  is such that: a gate metal GM, a gate dielectric layer  106 , an i layer  107  formed from Si, an n+ layer  108  formed from Si, a source metal SM, and a passivation layer  109  are stacked on a glass substrate  100  in this order. The gate electrode  104 , the second capacitor electrode  104   a , and the gate bus line GL are all formed from the gate metal GM that has been formed in a concurrent manufacturing process. The source electrode  102 , the drain electrode  103 , and the first capacitor electrode  102   a  are all formed from the source metal SM that has been formed in the concurrent manufacturing process. The i layer  107  is a layer that serves as a channel forming region in the TFT body section  101   a . The n+ layer  108  is provided as a source/drain contact layer between the i layer  107  and the source electrode  102  and between the i layer  107  and the drain electrode  103 . 
     The above-described transistor including the bootstrap capacitor is also disclosed in Patent Literature 2, etc. 
     CITATION LIST 
     Patent Literature 1 
     Japanese Patent No. 3863215 (Registration Date: Oct. 6, 2006) 
     Patent Literature 2 
     Japanese Patent Application Publication, Tokukaihei, No. 8-87897 A (Publication Date: Apr. 2, 1996) 
     SUMMARY OF INVENTION 
     The conventional TFT provided with a bootstrap capacitor requires being large in size so that the TFT body section secures a large channel width, as described previously. Therefore, it is inevitable that manufacturing of TFTs with low yield seriously decreases a proportion of non-defective panels obtained. However, with increase of a load connected to an output of a TFT including the bootstrap capacitor, a capacitance value required for the bootstrap capacitor to obtain a satisfactory bootstrap effect increases. Accordingly, the bootstrap capacitor occupies a large area on a panel. A magnitude of such a capacitance value depends on circuit configuration and specification of a display panel. However, the capacitance value is equal to or greater than 3 pF for a 7-inch panel, for example. A greater screen size further increases the capacitance value. Therefore, the bootstrap capacitor  101   b  shown in  FIG. 12  is extremely large in size. As an example is given a 7-inch WVGA display device with a monolithically fabricated gate driver which device performs gate scanning for three color lines of RGB under the condition where a capacitance value of the bootstrap capacitor  101   b  is 3 pF. Assume that a dot pitch in the gate scanning direction is 63 μm in an arrangement where the gate driver is disposed in one of two regions adjoining a display region, and a gate dielectric layer (SiNx) has a relative permittivity of 6.9 and has a layer thickness of 4100 Å. In this case, the bootstrap capacitor  101   b  is such that a side H along the gate scanning direction is 50 μm, and the other side W is 400 μm. 
     Such a large area occupied by the bootstrap capacitor results in a higher probability of the occurrence of leakage between two opposed electrodes of the bootstrap capacitor. If the bootstrap capacitor has leakage in at least one spot, the entire TFT fails to operate normally. This decreases manufacturing yield of TFTs and, in turn, seriously decreases manufacturing yield of display panels. 
     Thus, the conventional TFT provided with a bootstrap capacitor has the problem that it is liable to have lower manufacturing yield due to the occurrence of leakage in the bootstrap capacitor. 
     The present invention has been attained in view of the above program caused by the conventional arrangement, and an object thereof is to realize: a TFT which can be easily saved from being a defective product even if leakage occurs in the capacitor connected to the TFT body section; a shift register; a scan signal line driving circuit; a display device, all of which include the TFT; and a TFT trimming method. 
     In order to solve the above problem, a TFT of the present invention is a TFT comprising: a first capacitor formed so as to have a region where a first capacitor electrode connected to a source electrode and a second capacitor electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween; a second capacitor formed so as to have a region where a third capacitor electrode and a fourth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween; a first lead-out line led out from the first capacitor electrode in a planar direction; a second lead-out line led out from a gate electrode in a planar direction; a third lead-out line out from the third capacitor electrode in a planar direction; a fourth lead-out line led out from the fourth capacitor electrode in a planar direction; a first interconnection intersecting the second lead-out line and the fourth lead-out line when viewed in the thickness direction; and a second interconnection intersecting the first lead-out line and the third lead-out line when viewed in the thickness direction, the second capacitor electrode and the gate electrode being connected to each other via the second lead-out line, the third capacitor electrode and the source electrode not being connected to each other, the fourth capacitor electrode and the gate electrode not being connected to each other. 
     As a method for trimming the above TFT is given a method comprising: causing separation between the second capacitor electrode and the gate electrode by fusing the second lead-out line, causing the first lead-out line and the third lead-out line to be connected to the second interconnection by welding; and causing the second lead-out line and the fourth lead-out line to be connected to the first interconnection by welding. 
     According to the above invention, the first capacitor is connected to the TFT body section so as to electrically function. In the event of occurrence of leakage in the first capacitor, the second capacitor electrode is separated from the second lead-out line by laser-fusing or the like method, so that the second capacitor electrode and the gate electrode are separated from each other. Then, connections of the second lead-out line and the fourth lead-out line to the first interconnection by laser-welding or the like method and connections of the first lead-out line and the third lead-out line to the second interconnection by laser-welding or the like method enable the second capacitor to be connected to the TFT body section so that the second capacitor electrically functions. 
     Thus, the occurrence of leakage in the first capacitor of the TFT does not mean a failure of the entire TFT. Such a TFT is serviceable with the second capacitor used as an alternative capacitor. 
     As described above, the present invention produces the effect of realizing a TFT which can be easily saved from being a defective product even if leakage occurs in the capacitor connected to the TFT body section. 
     In order to solve the above problem, a TFT of the present invention is a TFT comprising: a first capacitor formed so that a first capacitor electrode connected to a source electrode and a second capacitor electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween; a second capacitor formed so that a third capacitor electrode and a fourth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween; a first lead-out line led out from the first capacitor electrode in a planar direction; a second lead-out line led out from a gate electrode in a planar direction; a third lead-out line led out from the third capacitor electrode in a planar direction; a fourth lead-out line led out from the fourth capacitor electrode in a planar direction; a first interconnection intersecting the second lead-out line and the fourth lead-out line when viewed in the thickness direction; and a second interconnection intersecting the first lead-out line and the third lead-out line when viewed in the thickness direction, the second capacitor electrode and the gate electrode not being connected to each other, the first lead-out line and the third lead-out line being connected to the second interconnection, whereby the third capacitor electrode and the source electrode are connected to each other, the second lead-out line and the fourth lead-out line being connected to the first interconnection, whereby the fourth capacitor electrode and the gate electrode are connected to each other. 
     According to the above invention, connection relationship is determined such that the second capacitor, which is selected from the first and second capacitors, is connected to the TFT body section so that the second capacitor functions electrically. 
     Thus, the occurrence of leakage in the first capacitor of the TFT does not mean a failure of the entire TFT. Such a TFT is serviceable with the second capacitor used as an alternative capacitor. 
     As described above, the present invention produces the effect of realizing a TFT which can be easily saved from being a defective product even if leakage occurs in the capacitor connected to the TFT body section. 
     In order to solve the above problem, a TFT of the present invention is such that the first capacitor electrode, the third capacitor electrode, the first lead-out line, the third lead-out line, and the first interconnection are formed from source metal, and the second capacitor electrode, the fourth capacitor electrode, the second lead-out line, the fourth lead-out line, and the second interconnection are formed from gate metal. 
     The above invention produces the effect of enabling easy formation of the first and second capacitors with use of a metallic material that is an original material for a TFT. 
     In order to solve the above problem, a TFT of the present invention is such that each of the first dielectric layer and the second dielectric layer is a gate dielectric layer. 
     The above invention produces the effect of enabling easy formation of the first and second capacitors with use of an insulating material that is an original material for a TFT. 
     In order to solve the above problem, a TFT of the present invention is a TFT comprising: a lead-out line connected to a source electrode; and a capacitor formed so as to have a region where a plurality of first capacitor electrodes and a second capacitor electrode connected to a gate electrode are arranged to be stacked in a thickness direction and mutually opposed across a dielectric layer therebetween, the plurality of first capacitor electrodes being led out from the lead-out line so as to be branched off from the lead-out line in a planar direction. 
     Further, as a method for trimming the above TFT is given a method of causing disconnection of at least one of the first capacitor electrodes from the lead-out line by fusing. 
     According to the above invention, capacitances provided between the first capacitor electrodes and the second capacitor electrode (hereinafter referred to as partial capacitance) are connected in parallel to each other. These capacitances constitute the total capacitance (hereinafter referred to as total capacitance). If these partial capacitances are sufficiently small as compared with the total capacitance, separation of a small number of the first capacitor electrodes with the leakage from the lead-out line by laser-fusing or the like method causes negligible difference in total capacitance between before and after separation of the first capacitor electrodes. 
     Thus, the occurrence of leakage in the capacitor of the TFT does not mean a failure of the entire TFT. Such a TFT is serviceable by repair to the capacitor. 
     As described above, the present invention produces the effect of realizing a TFT which can be easily saved from being a defective product even if leakage occurs in the capacitor connected to the TFT body section. 
     In order to solve the above problem, a TFT of the present invention is such that each of the first capacitor electrodes has: a pairing portion forming an opposing pair with the second electrode which is in the region of the capacitor; and a non-pairing portion with the second electrode such that the non-pairing portion extends from the lead-out line and leads to the pairing portion. 
     The above invention produces the effect of enabling easy separation of the first capacitor electrode with leakage by laser-fusing or the like method in the non-pairing portion. 
     In order to solve the above problem, a TFT of the present invention is such that a cutout is provided in the first capacitor electrode at a boundary between the non-pairing portion and the pairing portion and/or provided in the lead-out line at a place where the first capacitor electrode is branched off from the lead-out line. 
     The above invention produces the effect of enabling the use of the cutout as a marking for separation in separating the first capacitor electrode with leakage by laser-fusing or the like method in the non-pairing portion. 
     In order to solve the above problem, a TFT of the present invention is such that the first capacitor electrodes and the lead-out line are formed from source metal, and the second capacitor electrode is formed from gate metal. 
     The above invention produces the effect of enabling easy formation of the first and second capacitors with use of a metallic material that is an original material for a TFT. 
     In order to solve the above problem, a TFT of the present invention is such that the dielectric layer is a gate dielectric layer. 
     The above invention produces the effect of enabling easy formation of the first and second capacitors with use of an insulating material that is an original material for a TFT. 
     In order to solve the above problem, a TFT of the present invention is a TFT comprising: a first capacitor formed: so as to have a region where a first capacitor electrode connected to a source electrode and a second capacitor electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween; and so as to have a region where the first capacitor electrode and a third capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween with a coupling between the first capacitor electrode and the third capacitor electrode and a coupling between the first capacitor electrode and the second capacitor electrode formed over mutually opposite faces of the first capacitor electrode; a second capacitor formed: so as to have a region where a fourth capacitor electrode and a fifth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a third dielectric layer therebetween; and so as to have a region where the fourth capacitor electrode and a sixth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a fourth dielectric layer therebetween with a coupling between the fourth capacitor electrode and the sixth capacitor electrode and a coupling between the fourth capacitor electrode and the fifth capacitor electrode formed over mutually opposite faces of the fourth capacitor electrode; a first lead-out line led out from the first capacitor electrode in a planar direction; a second lead-out line led out from the second capacitor electrode in a planar direction; a gate lead-out line led out from a gate electrode in a planar direction; a third lead-out line led out from the third capacitor electrode in a planar direction; a fourth lead-out line led out from the fourth capacitor electrode in a planar direction; a fifth lead-out line led out from the fifth capacitor electrode in a planar direction; a first interconnection intersecting the gate lead-out line and the fifth lead-out line when viewed in the thickness direction; and a second interconnection intersecting the first lead-out line and the fourth lead-out line when viewed in the thickness direction, the third capacitor electrode and the gate electrode being connected to each other via the third lead-out line, the sixth capacitor electrode being connected to the fifth lead-out line, the second capacitor electrode and the gate electrode being connected to each other via the second lead-out line, the gate lead-out line and the fifth lead-out line not being connected to the first interconnection, the first lead-out line and the fourth lead-out line not being connected to the second interconnection. 
     Further, as a method for trimming the above TFT is given a method comprising: causing separation between the third capacitor electrode and the gate electrode by fusing the third lead-out line; causing the sixth capacitor electrode to be connected to the fifth lead-out line by welding; causing separation between the second capacitor electrode and the gate electrode by fusing the second lead-out line; causing the gate lead-out line and the fifth lead-out line to be connected to the first interconnection by welding; and causing the first lead-out line and the fourth lead-out line to be connected to the second interconnection by welding. 
     According to the above invention, the first capacitor is connected to the TFT body section so as to electrically function. In the event of occurrence of leakage in the first capacitor, the second capacitor electrode is separated from the gate electrode by subjecting the second lead-out line to laser-fusing or the like method, the third capacitor electrode is separated from the gate electrode by subjecting the third lead-out line to laser-fusing or the like method. Then, connections of the gate lead-out line and the fifth lead-out line to the first interconnection by laser-welding or the like method and connections of the first lead-out line and the fourth lead-out line to the second interconnection by laser-welding or the like method enable the second capacitor to be connected to the TFT body section so that the second capacitor electrically functions. 
     Thus, the occurrence of leakage in the first capacitor of the TFT does not mean a failure of the entire. TFT. Such a TFT is serviceable with the second capacitor used as an alternative capacitor. 
     As described above, the present invention produces the effect of realizing a TFT which can be easily saved from being a defective product even if leakage occurs in the capacitor connected to the TFT body section. 
     In order to solve the above problem, a TFT of the present invention is a TFT comprising: a first capacitor formed: so as to have a region where a first capacitor electrode connected to a source electrode and a second capacitor electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween; and so as to have a region where the first capacitor electrode and a third capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween with a coupling between the first capacitor electrode and the third capacitor electrode and a coupling between the first capacitor electrode and the second capacitor electrode formed over mutually opposite faces of the first capacitor electrode; a second capacitor formed: so as to have a region where a fourth capacitor electrode and a fifth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a third dielectric layer therebetween; and so as to have a region where the fourth capacitor electrode and a sixth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a fourth dielectric layer therebetween with a coupling between the fourth capacitor electrode and the sixth capacitor electrode and a coupling between the fourth capacitor electrode and the fifth capacitor electrode formed over mutually opposite faces of the fourth capacitor electrode; a first lead-out line led out from the first capacitor electrode in a planar direction; a second lead-out line led out from the second capacitor electrode in a planar direction; a gate lead-out line led out from a gate electrode in a planar direction; a third lead-out line led out from the third capacitor electrode in a planar direction; a fourth lead-out line led out from the fourth capacitor electrode in a planar direction; a fifth lead-out line led out from the fifth capacitor electrode in a planar direction; a first interconnection intersecting the gate lead-out line and the fifth lead-out line when viewed in the thickness direction; and a second interconnection intersecting the first lead-out line and the fourth lead-out line when viewed in the thickness direction, the third capacitor electrode and the gate electrode not being connected to each other, the sixth capacitor electrode being connected to the fifth lead-out line, the second capacitor electrode and the gate electrode not being connected to each other, the gate lead-out line and the fifth lead-out line being connected to the first interconnection, whereby the fifth capacitor electrode and the sixth electrode are connected to the gate electrode, the first lead-out line and the fourth lead-out line being connected to the second interconnection, whereby the fourth capacitor electrode and the source electrode are connected to each other. 
     According to the above invention, connection relationship is determined such that the second capacitor, which is selected from the first and second capacitors, is connected to the TFT body section so that the second capacitor functions electrically. 
     Thus, the occurrence of leakage in the first capacitor of the TFT does not mean a failure of the entire TFT. Such a TFT is serviceable with the second capacitor used as an alternative capacitor. 
     As described above, the present invention produces the effect of realizing a TFT which can be easily saved from being a defective product even if leakage occurs in the capacitor connected to the TFT body section. 
     In order to solve the above problem, a TFT of the present invention is such that the first capacitor electrode, the fourth capacitor electrode, the first lead-out line, the fourth lead-out line, and the first interconnection are formed from source metal, the second capacitor electrode, the fifth capacitor electrode, the second lead-out line, the fifth lead-out line, the gate lead-out line, and the second interconnection are formed from gate metal, and the third capacitor electrode, the sixth capacitor electrode, and the third lead-out line are formed from transparent electrodes. 
     The above invention produces the effect of enabling easy formation of the first and second capacitors with use of a metallic material that is an original material for a TFT. 
     In order to solve the above problem, a TFT of the present invention is such that each of the first dielectric layer and the third dielectric layer is a gate dielectric layer, and each of the second dielectric layer and the fourth dielectric layer is a passivation layer. 
     The above invention produces the effect of enabling easy formation of the first and second capacitors with use of an insulating material that is an original material for a TFT. 
     In order to solve the above problem, a TFT of the present invention is a TFT comprising: a lead-out line connected to a source electrode; and a capacitor formed: so as to have a region where a plurality of first capacitor electrodes and a second capacitor electrode connected to a gate electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween, the plurality of first capacitor electrodes being led out from the lead-out line so as to be branched off from the lead-out line in a planar direction; and so as to have a region where the first capacitor electrodes and a third capacitor electrode connected to the gate electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween with a coupling between the first capacitor electrodes and the third capacitor electrode and a coupling between the first capacitor electrodes and the second capacitor electrode formed over mutually opposite faces of the first capacitor electrode. 
     Further, as a method for trimming the above TFT is given a method of causing disconnection of at least one of the first capacitor electrodes from the lead-out line by fusing. 
     According to the above invention, capacitances provided between the first capacitor electrodes and the second capacitor electrode (hereinafter referred to as first partial capacitance) are connected in parallel to each other, and capacitances provided between the first capacitor electrodes and the third capacitor electrode (hereinafter referred to as second partial capacitance) are connected in parallel to each other. These capacitances constitute the total capacitance (hereinafter referred to as total capacitance). If a sum of the first and second partial capacitances is sufficiently small as compared with the total capacitance, separation of a small number of the first capacitor electrodes with the leakage from the lead-out line by laser-fusing or the like method causes negligible difference in total capacitance between before and after separation of the first capacitor electrodes. 
     Thus, the occurrence of leakage in the capacitor of the TFT does not mean a failure of the entire TFT. Such a TFT is serviceable by repair to the capacitor. 
     As described above, the present invention produces the effect of realizing a TFT which can be easily saved from being a defective product even if leakage occurs in the capacitor connected to the TFT body section. 
     In order to solve the above problem, a TFT of the present invention is such that each of the first capacitor electrodes has: a pairing portion forming an opposing pair with either of the second and third capacitor electrodes closer to the lead-out line which electrodes are in the region of the capacitor; and a non-pairing portion with the second and third electrodes such that the non-pairing portion extends from the lead-out line and leads to the pairing portion. 
     The above invention produces the effect of enabling easy separation of the first capacitor electrode with leakage by laser-fusing or the like method in the non-pairing portion. 
     In order to solve the above problem, a TFT of the present invention is such that a cutout is provided in the first capacitor electrode at a boundary between the non-pairing portion and the pairing portion and/or provided in the lead-out line at a place where the first capacitor electrode is branched off from the lead-out line. 
     The above invention produces the effect of enabling the use of the cutout as a marking for separation in separating the first capacitor electrode with leakage by laser-fusing or the like method in the non-pairing portion. 
     In order to solve the above problem, a TFT of the present invention is such that the first capacitor electrode and the lead-out line are formed from source metal, the second capacitor electrode is formed from gate metal, and the third capacitor electrode is formed from a transparent electrode. 
     The above invention produces the effect of enabling easy formation of the first and second capacitors with use of a metallic material that is an original material for a TFT. 
     In order to solve the above problem, a TFT of the present invention is such that the first dielectric layer is a gate dielectric layer, and the second dielectric layer is a passivation layer. 
     The above invention produces the effect of enabling easy formation of the first and second capacitors with use of an insulating material that is an original material for a TFT. 
     In order to solve the above problem, a TFT of the present invention is such that the TFT is manufactured with use of amorphous silicon. 
     The above invention produces the effect of preventing manufacturing yield of the entire TFT from seriously decreasing by improving the manufacturing yield of the capacitor of a TFT manufactured from amorphous silicon, because the TFT using amorphous silicon generally has a large channel width and is more likely to have lower manufacturing yield. 
     In order to solve the above problem, a TFT of the present invention is such that the TFT is manufactured with use of microcrystalline silicon. 
     A TFT using microcrystal silicon has higher mobility than an amorphous silicon TFT. As such, the above invention produces the effect of making the transistor size small in comparison with the amorphous silicon TFT. Moreover, using microcrystal silicon in a TFT realizes a small-footprint TFT, which is advantageous for a slim picture frame. It is also possible to curb variations in threshold voltage caused by application of DC biases. 
     In order to solve the above problem, a shift register of the present invention includes a plurality of stages composed of transistors, wherein at least one of the transistors is the above TFT. 
     The above invention produces the effect of enabling manufacturing of a shift register with high yield. 
     In order to solve the above problem, a scan signal line driving circuit of the present invention includes the above shift register, wherein the shift register is used to generate a scan signal for a display device. 
     The above invention produces the effect of enabling manufacturing of a scan signal line driving circuit with high yield. 
     In order to solve the above problem, a scan signal line driving circuit of the present invention is such that the TFT is an output transistor that outputs the scan signal. 
     The above invention produces the effect of enabling manufacturing of a TFT for which high driving ability is required with high yield, by using the TFT as an output transistor that outputs a scan signal. 
     In order to solve the above problem, a display device of the present invention comprises the above scan signal line driving circuit. 
     The above invention produces the effect of enabling manufacturing of a display device with high yield. 
     In order to solve the above problem, a display device of the present invention is such that the scan signal line driving circuit is formed on a display panel so as to be monolithically integrated with a display region. 
     The above invention produces the effect that it can make up for the disadvantages that the display device requires a large capacitance and that the TFT cannot help but having a large channel width. Consequently, it is possible to manufacture, with high yield, a display device in which the scan signal line driving circuit is formed on the display panel so as to be monolithically integrated with the display region. 
     In order to solve the above problem, a display device of the present invention comprises a display panel in which the above TFT is formed. 
     The above invention produces the effect of realizing a display device which can be easily saved from being a defective product even if leakage occurs in the capacitor connected to the TFT body section. 
     Additional objects, features, and strengths of the present invention will be made clear by the description below. Further, the advantages of the present invention will be evident from the following explanation in reference to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a plan view showing an embodiment of the present invention and showing the structure of a TFT according to a first example. 
         FIG. 2  is a cross-sectional view taken along the line A-A′ in  FIG. 1 . 
         FIG. 3  is a plan view showing an embodiment of the present invention and showing the structure of a TFT according to a second example. 
         FIG. 4  is a plan view showing an embodiment of the present invention and showing the structure of a TFT according to a third example. 
         FIG. 5  shows cross-sectional views of the TFT shown in  FIG. 4 , wherein (a) is a cross-sectional view taken along the line B-B′, and (b) is a cross-sectional view taken along the line C-C′. 
         FIG. 6  is a plan view showing an embodiment of the present invention and showing the structure of a TFT according to a fourth example. 
         FIG. 7  is a block diagram showing an embodiment of the present invention and showing the structure of a display device. 
         FIG. 8  is a circuit block diagram showing the structure of a shift register included in the display device shown in  FIG. 7 . 
         FIG. 9  is an explanatory view of a shift register stage included in the shift register shown in  FIG. 8 , wherein (a) is a circuit diagram showing the structure of the shift register stage, and (b) is a timing chart showing operations of the circuit shown in (a). 
         FIG. 10  is a timing chart showing operations of the shift register shown in  FIG. 8 . 
         FIG. 11  is a circuit diagram showing the conventional art and showing the structure of a shift register stage. 
         FIG. 12  is a plan view showing the conventional art and showing the structure of a TFT. 
         FIG. 13  is a cross-sectional view taken along the line X-X′ in  FIG. 12 . 
     
    
    
     REFERENCE SIGNS LIST 
     
         
           1  Liquid crystal display device (display device) 
           61 ,  71 ,  81 , and  91  TFTs 
           61   b  Capacitor (first capacitor) 
           61   c  Capacitor (second capacitor) 
           62  Source electrode 
           64  Gate electrode 
           62   a  First capacitor electrode 
           64   a  Second capacitor electrode 
           62   b  Third capacitor electrode 
           64   b  Fourth capacitor electrode 
           62   i  Lead-out line (first lead-out line) 
           64   h  Lead-out line (second lead-out line) 
           62   j  Lead-out line (third lead-out line) 
           64   i  Lead-out line (fourth lead-out line) 
           66  Gate dielectric layer (first dielectric layer, second dielectric layer, and dielectric layer) 
           71   a  Capacitor 
           72   h  Lead-out line 
           72   a  First capacitor electrode 
           74   a  Second capacitor electrode 
           73 ,  74 , and  75  Cutouts 
           81   b  Capacitor (first capacitor) 
           81   c  Capacitor (second capacitor) 
           82  Source electrode 
           84  Gate electrode 
           82   a  First capacitor electrode 
           84   a  Second capacitor electrode 
           80   a  Third capacitor electrode 
           82   b  Fourth capacitor electrode 
           84   b  Fifth capacitor electrode 
           80   b  Sixth capacitor electrode 
           82   i  Lead-out line (first lead-out line) 
           84   h  Lead-out line (second lead-out line) 
           80   c  Lead-out line (third lead-out line) 
           84   d  Lead-out line (gate lead-out line) 
           82   j  Lead-out line (fourth lead-out line) 
           84   e  Lead-out line (fifth lead-out line) 
           86  Gate dielectric layer (first dielectric layer, third dielectric layer) 
           89  Passivation layer (second dielectric layer, fourth dielectric layer) 
           91   a  Capacitor 
           92   h  Lead-out line 
           92   a  First capacitor electrode 
           94   a  Second capacitor electrode 
           90   a  Third capacitor electrode 
           93 ,  94 ,  95  Cutouts 
         Tr 4  Transistor (TFT) 
         CAP Capacitor (first capacitor and second capacitor) 
       
    
     DESCRIPTION OF EMBODIMENTS 
     The following will describe one embodiment of the present invention with reference to  FIGS. 1 through 10 . 
       FIG. 7  shows the configuration of a liquid crystal display device  1  that is a display device according to the present embodiment. 
     The liquid crystal display device  1  includes a display panel  2 , a flexible printed circuit board  3 , and a control board  4 . 
     The display panel  2  is an active matrix display panel arranged such that, using amorphous silicon, polycrystalline silicon, CG silicon, microcrystalline silicon, or the like silicon, a display region  2   a , a plurality of gate bus lines GL, a plurality of source bus lines SL, and gate drivers  5   a  and  5   b  are built onto a glass substrate. The display region  2   a  is a region where a plurality of pixels PIX are arranged in a matrix manner. Each of the pixels PIX includes a TFT  21  that is a selection element of the pixel PIX, a liquid crystal capacitor CL, and an auxiliary capacitor Cs. A gate of the TFT  21  is connected to the gate bus line GL, and a source of the TFT  21  is connected to the source bus line SL. The liquid crystal capacitor CL and auxiliary capacitor Cs are connected to a drain of the TFT  21 . 
     The plurality of gate bus lines GL are gate bus lines GL 1 , GL 2 , GL 3 , . . . and GLn. Among these, the gate bus lines GL in a first group consisting of the alternate gate bus lines GL 1 , GL 3 , GL 5 , . . . are connected to respective outputs of the gate driver  5   a , and the gate bus lines GL in a second group consisting of the other alternate gate bus lines GL 2 , GL 4 , GL 6 , . . . are connected to respective outputs of the gate driver  5   b . The plurality of source bus lines SL are source bus lines SL 1 , SL 2 , SL 3 , . . . SLm, which are connected to respective outputs of a source driver  6  that will be described later. Although not shown, an auxiliary capacitor line is formed to apply an auxiliary capacitor voltage to each of the auxiliary capacitors Cs of the pixels PIX. 
     The gate driver  5   a  is provided in one of two regions adjoining the display region  2   a  of the display panel  2  in a direction in which the gate bus lines GL extend, and sequentially supplies a gate pulse to each of the gate bus lines GL 1 , GL 3 , GL 5 , . . . of the first group. The gate driver  5   b  is provided in the other region adjoining the display region  2   a  of the display panel  2 , and sequentially supplies a gate pulse to each of the gate bus lines GL 2 , GL 4 , GL 6 , . . . of the second group. These gate drivers  5   a  and  5   b  are built into the display panel  2  so as to be monolithically integrated with the display region  2   a . Examples of the gate drivers  5   a  and  5   b  can include all gate drivers referred to with the terms such as “monolithic gate driver”, “gate driver-free”, “built-in gate driver in panel”, and “gate in panel”. 
     The flexible printed circuit board  3  includes the source driver  6 . The source driver  6  supplies a data signal to each of the source bus lines SL. The control board  4  is connected to the flexible printed circuit board  3  and supplies necessary signals and power to the gate drivers  5   a  and  5   b  and the source driver  6 . The signals and power to be supplied to the gate drivers  5   a  and  5   b  from the control board  4  pass through the flexible printed circuit board  3  and are then supplied to the gate driver  15  on the display panel  2 . 
       FIG. 8  shows the configurations of the respective gate drivers  5   a  and  5   b.    
     The gate driver  5   a  includes a first shift register  51   a  having a plurality of cascaded shift register stages SR (SR 1 , SR 3 , SR 5 , . . . ) therein. Each of the shift register stages SR includes a set input terminal Qn−1, an output terminal GOUT, a reset input terminal Qn+1, clock input terminals CKA and CKB, and a Low power source input terminal VSS. From the control board  4  are supplied a clock signal CK 1 , a clock signal CK 2 , a gate start pulse GSP 1 , and Low power source VSS (For convenience of explanation, the same reference sign as that for the Low power source input terminal VSS is used). The Low power source VSS may be at negative potential, at ground potential, or at positive potential. However, the Low power source VSS is herein assumed at negative potential to ensure OFF state of the TFTs. 
     In the first shift register  51   a , an output from the output terminal GOUT of a j-numbered (j=1, 2, 3, . . . , i=1, 3, 5, . . . , j=(i+1)/2) shift register stage SRi is a gate output Gi to be outputted to an i-th gate bus line GLi. 
     To the set input terminal Qn−1 of a first shift register stage SR 1  that lies at one of opposite ends in the scanning direction, the gate start pulse GSP 1  is supplied. To the respective set input terminals Qn−1 of the j-numbered second and succeeding shift register stages SRi, gate outputs Gi−2 of preceding shift register stages SRi−2 are supplied. Further, to the respective reset input terminals Qn+1 thereof, gate outputs Gi+2 of subsequent shift register stages SRi+2 are supplied. 
     In the alternate j-numbered shift register stages SR that start from the first shift register stage SR 1 , the clock signal CK 1  is supplied to the clock input terminals CKA, and the clock signal CK 2  is supplied to the clock input terminals CKB. In the alternate j-numbered shift register stages SR that start from the second shift register stage SR 3 , the clock signal CK 2  is supplied to the clock input terminals CKA, and the clock signal CK 1  is supplied to the clock input terminals CKB. In this manner, the first and second stages are aligned alternately in the first shift register  51   a.    
     The clock signals CK 1  and CK 2  have waveforms as shown in (b) of  FIG. 9  (see CKA and CKB for CK 1  and CK 2 , respectively). The clock signals CK 1  and CK 2  are arranged so that their clock pulses do not overlap each other. In addition, timings for the clock signals CK 1  and CK 2  are such that the clock pulse of the clock signal CK 1  appears after a one clock pulse delay subsequent to the clock pulse of the clock signal CK 2 , and the clock pulse of the clock signal CK 2  appears after a one clock pulse delay subsequent to the clock pulse of the clock signal CK 1 . 
     The gate driver  5   b  includes a second shift register  51   b  having a plurality of cascaded shift register stages SR (SR 2 , SR 4 , SR 6 , . . . ) therein. Each of the shift register stages SR includes a set input terminal Qn−1, an output terminal GOUT, a reset input terminal Qn+1, clock input terminals CKA and CKB, and a Low power source input terminal VSS. From the control board  4  are supplied a clock signal CK 3 , a clock signal CK 4 , a gate start pulse GSP 2 , and the Low power source VSS. 
     In the second shift register  51   b , an output from the output terminal GOUT of a k-numbered (k=1, 2, 3, . . . , i=2, 4, 6, . . . , k=i/2) shift register stage SRi is a gate output Gi to be outputted to an i-th gate bus line GLi. 
     To the set input terminal Qn−1 of a first shift register stage SR 2  that lies at one of opposite ends in the scanning direction, the gate start pulse GSP 2  is supplied. To the respective set input terminals Qn−1 of the k-numbered second and succeeding shift register stages SRi, gate outputs Gi−2 of preceding shift register stages SRi−2 are supplied. Further, to the respective reset input terminals Qn+1 thereof, gate outputs Gi+2 of subsequent shift register stages SRi+2 are supplied. 
     In the alternate k-numbered shift register stages SR that start from the first shift register stage SR 2 , the clock signal CK 3  is supplied to the clock input terminals CKA, and the clock signal CK 4  is supplied to the clock input terminals CKB. In the alternate k-numbered shift register stages SR that start from the second shift register stage SR 4 , the clock signal CK 4  is supplied to the clock input terminals CKA, and the clock signal CK 3  is supplied to the clock input terminals CKB. In this manner, the third and fourth stages are aligned alternately in the second shift register  51   b.    
     The clock signals CK 3  and CK 4  have waveforms as shown in (b) of  FIG. 9  (see CKA and CKB for CK 3  and CK 4 , respectively). The clock signals CK 3  and CK 4  are arranged so that their clock pulses do not overlap each other. In addition, timings for the clock signals CK 3  and CK 4  are such that the clock pulse of the clock signal CK 3  appears after a one clock pulse delay subsequent to the clock pulse of the clock signal CK 4 , and the clock pulse of the clock signal CK 4  appears after a one clock pulse delay subsequent to the clock pulse of the clock signal CK 3 . 
     Further, as shown in  FIG. 10 , the clock signals CK 1 , CK 2 , CK 3 , and CK 4  are out of sync with each other. Timings for the clock signals CK 1 , CK 2 , CK 3 , and CK 4  are such that the clock pulse of the clock signal CK 1  appears subsequently to the clock pulse of the clock signal CK 4 , the clock pulse of the clock signal CK 3  appears subsequently to the clock pulse of the clock signal CK 1 , the clock pulse of the clock signal CK 2  appears subsequently to the clock pulse of the clock signal CK 3 , and the clock pulse of the clock signal CK 4  appears subsequently to the clock pulse of the clock signal CK 2 . 
     As shown in  FIG. 10 , the gate start pulses GSP 1  and GSP 2  are pulses such that the gate start pulse GSP 1  precedes the gate start pulse GSP 2  and the gate start pulses GSP 1  and GSP 2  are adjacent to each other. The pulse of the gate start pulse GSP 1  is in synchronism with the clock pulse of the clock signal CK 2 , and the pulse of the gate start pulse GSP 2  is in synchronism with the clock pulse of the clock signal CK 4 . 
     Next, the following will describe the configuration of the shift register stage SRi of the shift registers  51   a  and  51   b  with reference to (a) of  FIG. 9 . 
     The shift register stage SRi includes transistors Tr 1 , Tr 2 , Tr 3 , and Tr 4 . Particularly, the transistor Tr 4  includes a capacitor CAP that is a bootstrap capacitor. These transistors are all n-channel type TFTs. 
     As to the transistor Tr 1 , a gate and a drain are connected to a set input terminal Qn−1, and a source is connected to a gate of the transistor Tr 4 . As to the transistor Tr 4 , a drain is connected to a clock input terminal CKA, and a source is connected to an output terminal GOUT. That is, the transistor Tr 4  serves as a transfer gate to perform passage and interruption of a clock signal to be supplied to the clock input terminal CKA. The capacitor CAP is provided between the gate and the source of the transistor Tr 4 . A node that is set to the same potential as the gate of the transistor Tr 4  is referred to as a netA. 
     As to the transistor Tr 2 , a gate is connected to the clock input terminal CKB, a drain is connected to the output terminal GOUT, and a source is connected to the Low power source input terminal VSS. As to the transistor Tr 3 , a gate is connected to the reset input terminal Qn+1, a drain is connected to the node netA, and a source is connected to the Low power source input terminal VSS. 
     Next, with reference to (b) of  FIG. 9 , the following will describe the operations of the shift register stage SRi configured as shown in (a) of  FIG. 9 . 
     When a shift pulse is supplied to the set input terminal Qn−1, the transistor Tr 1  is turned ON, which charges the capacitor CAP. For the shift register stages SR 1  and SR 2 , the shift pulse corresponds to the gate start pulses GSP 1  and GSP 2 , respectively. For the other shift register stages SRi, the shift pulse corresponds to gate outputs Gj−1 and Gk−1 from preceding shift register stages. Charging of the capacitor CAP increases a potential of the node netA and causes the transistor Tr 4  to be turned ON. This causes the clock signal supplied through the clock input terminal CKA to appear in the source of the transistor Tr 4 . At the instant when the subsequent clock pulse is supplied to the clock input terminal CKA, the potential of the node netA rapidly increases due to the bootstrap effect of the capacitor CAP, and the incoming clock pulse is transferred to the output terminal GOUT of the shift register stage SRi and outputted from the output terminal GOUT as a gate pulse. 
     When the supply of the gate pulse to the set input terminal Qn−1 is completed, the transistor Tr 4  is turned OFF. Then, in order to release charge retention caused by floating of the node netA and the output terminal GOUT of the shift register stage SRi, the transistor Tr 3  is turned ON by a reset pulse supplied to the reset input terminal Qn+1. This causes the node netA and the output terminal GOUT to be set to a potential of the Low power source VSS. 
     Thereafter, until the shift pulse is supplied to the set input terminal Qn−1 again, the transistor Tr 2  is periodically turned ON by the clock pulse supplied to the clock input terminal CKB. This refreshes the node netA and the output terminal GOUT of the shift register stage SRi with Low power source potential, i.e. sinks the gate bus line GLi voltage down. 
     In this manner, the gate pulses are sequentially outputted to the gate bus lines G 1 , G 2 , G 3 , and the like as shown in  FIG. 10 . 
     Next, the structures of elements applied to the transistor Tr 4  in (a) of  FIG. 9  will be described with Examples. 
     Example 1 
     The following will describe a TFT of the present example with reference to  FIGS. 1 and 2 . 
       FIG. 1  shows a plan view of the structure of a TFT  61  applicable to the transistor Tr 4  and provided on the display panel  2 , according to the present example. 
     The TFT  61  includes a TFT body section  61   a , capacitors  61   b  and  61   c , and interconnections  62   c  and  64   c . Each of the capacitors  61   b  and  61   c  is a capacitor capable of serving as a bootstrap capacitor and applicable to the capacitor CAP. 
     The TFT body section  61   a  has a comb-shaped source electrode  62  and a comb-shaped drain electrode  63  disposed above a gate electrode  64  in a thickness direction and opposed to each other in a panel plane in such a manner that the source electrode  62  and drain electrode  63  are engaged with each other, which secures a large channel width. However, this is merely one arrangement example. The source electrode  62 , the drain electrode  63 , and the gate electrode  64  may be disposed at any positions with any shapes. 
     The capacitor (first capacitor)  61   b  is formed so as to have a region where a first capacitor electrode  62   a  and a second capacitor electrode  64   a  are arranged to be stacked in the thickness direction and mutually opposed across a gate dielectric layer (first dielectric layer, see  FIG. 2 )  66  therebetween. The first capacitor electrode  62   a  is formed so as to be led out from the source electrode  62  of the TFT body section  61   a  through a lead-out line  62   h  in a planar direction. The second capacitor electrode  64   a  is formed so as to be led out from the gate electrode  64  of the TFT body section  61   a  through a lead-out line (second lead-out line)  64   h  in a planar direction. 
     The first capacitor electrode  62   a  is connected to an output OUT of the shift register stage SR via a lead-out line (first lead-out line)  62   i  in a planar direction. The output OUT is connected via a contact hole  65  to the gate bus line GL which lies at a lower position in the thickness direction. 
     The capacitor (second capacitor)  61   c  is disposed adjacent to the capacitor  61   b  and formed so as to have a region where a third capacitor electrode  62   b  and a fourth capacitor electrode  64   b  are arranged to be stacked in the thickness direction and mutually opposed across a gate dielectric layer (second dielectric layer)  66  therebetween. The first dielectric layer and the second dielectric layer may be dielectric layers different from each other. In this case, the capacitors  61   b  and  61   c  are designed so as to have the same value of capacitance. From the third capacitor electrode  62   b , a lead-out line (third lead-out line)  62   j  is led out in a planar direction. From the fourth capacitor electrode  64   b , a lead-out line (fourth lead-out line)  64   i  is led out in a planar direction. 
     The interconnection (first interconnection)  62   c  is provided so as to intersect both of the lead-out lines  64   h  and  64   i  at upper positions in the thickness direction. The interconnection (second interconnection)  64   c  is provided so as to intersect both of the lead-out lines  62   i  and  62   j  at lower positions in the thickness direction. 
       FIG. 2  shows a cross-sectional view taken along the line A-A′ in  FIG. 1 . 
     As shown in the cross-sectional view in  FIG. 2 , the arrangement in  FIG. 1  is such that: a gate metal GM, the gate dielectric layer  66 , an i layer  67  formed from Si, an n+ layer  68  formed from Si, a source metal SM, and a passivation layer  69  are stacked on a glass substrate  60  in this order. The gate electrode  64 , the second capacitor electrode  64   a , the lead-out line  64   h , the interconnection  64   c , and the gate bus line GL are all formed from the gate metal GM that has been formed in a concurrent manufacturing process. For example, the gate metal GM can be used in a single layer of Ta (or TaN), Ti (or TiN), Al (or an alloy whose major component is Al), Mo (or MoN), or Cr or used in a stack with any combinations of these metals. The source electrode  62 , the drain electrode  63 , the first capacitor electrode  62   a , the lead-out line  62   i , and the interconnection  62   c  are all formed from the source metal SM that has been formed in the concurrent manufacturing process. The source metal SM can be formed from the same material(s) as the material(s) for the gate metal GM. For example, the source metal SM can be used in a single layer of Ta (or TaN), Ti (or TiN), Al (or an alloy whose major component is Al), Mo (or MoN), or Cr or used in a stack with any combinations of these metals. The i layer  67  is a layer that serves as a channel forming region in the TFT body section  61   a . The n+ layer  68  is provided as a source/drain contact layer between the i layer  67  and the source electrode  62  and between the i layer  67  and the drain electrode  63 . 
     Besides, in  FIG. 1 , the fourth capacitor electrode  64   b  and the lead-out line  64   i  are formed from the gate metal GM, and the third capacitor electrode  62   b  and the lead-out line  62   j  are formed from the source metal SM. 
     As the gate dielectric layer  66 , for example, SiN, SiO 2 , or the like material can be used. As the passivation layer  69 , for example, SiN, SiO 2 , an organic resin film, or the like material can be used. 
     As to the TFT  61  arranged as above, during the manufacture of the TFT  61 , the capacitor  61   b  is electrically connected to the TFT body section  61   a  through the lead-out lines  62   h  and  64   h , while the capacitor  61   c  is not electrically connected to the TFT body section  61   a  since the third capacitor electrode  62   b  and the fourth capacitor electrode  64   b  are not connected to the source electrode  62  and the gate electrode  64 , respectively. If it is found out by an inspection conducted after manufacturing that leakage has occurred due to a leakage defect L 1  between the first capacitor electrode  62   a  and the second capacitor electrode  64   a  or the like defect, no voltage is applied across the capacitor  61   b  through both of the lead-out lines  62   h  and  64   h , and the capacitor  61   c  is made electrically connected to the TFT body section  61   a  through the lead-out line  62   j  and the interconnection  64   c  and through the lead-out line  64   i  and the interconnection  62   c . The inspection may be an electrical inspection or a visual inspection. 
     Specifically, the interconnection  62   c  and the lead-out lines  64   h  and  64   i  are made connected to each other at intersection points P 1  and P 2  by laser welding, so that the fourth capacitor electrode  64   b  is connected to the gate electrode  64 , and the interconnection  64   c  and the lead-out lines  62   i  and  62   j  are made connected to each other at intersection points P 3  and P 4  by laser welding so that the third capacitor electrode  62   b  is connected to the source electrode  62 . Further, the lead-out line  64   h  is subjected to laser fusing at a point Q 1  between the second capacitor electrode  64   a  and the intersection point P 1 , so that the second capacitor electrode  64   a  is separated from the lead-out line  64   h . As such, the second capacitor electrode  64   a  is separated from the gate electrode  64 . 
     Thus, the occurrence of leakage in the capacitor  61   b  does not mean a failure of the entire TFT  61 . Such a TFT  61  is serviceable with the capacitor  61   c  used as an alternative bootstrap capacitor. 
     Note that the alternative capacitor like the capacitor  61   c  is not limited to one alternative capacitor. Alternatively, a plurality of alternative capacitors may be provided. In this case, one available alternative capacitor can be selected from among them for use at the occurrence of leakage. 
     Example 2 
     A TFT of the present example will be described with reference to  FIG. 3 . Unless otherwise noted, members given the same reference numerals as those shown in  FIGS. 1 and 2  have the same functions as the members in  FIGS. 1 and 2 . 
       FIG. 3  shows a plan view of the structure of a TFT  71  applicable to the transistor Tr 4  and provided on the display panel  2 , according to the present example. 
     The TFT  71  includes a TFT body section  61   a , a capacitor  71   a , and interconnections  72   h  and  74   h . The capacitor  71   a  is a capacitor capable of serving as a bootstrap capacitor and applicable to the capacitor CAP. 
     The capacitor  71   a  is formed so as to have a region where a plurality of first capacitor electrodes  72   a  and a second capacitor electrode  74   a  are arranged to be stacked in the thickness direction and mutually opposed across a gate dielectric layer  66  therebetween. The plurality of first capacitor electrodes  72   a  are formed so as to be led out from the lead-out line  72   h , which is led out from the source electrode  62  of the TFT body section  61   a , and to be branched off in a comb-like manner in a planar direction. The second capacitor electrode  74   a  is formed so as to be led out from the gate electrode  64  of the TFT body section  61   a  through the interconnection  74   h.    
     The lead-out line  72   h  is connected to an output OUT of the shift register stage SR, and the output OUT is connected via a contact hole  65  to the gate bus line GL which lies at a lower position in the thickness direction. 
     The plurality of first capacitor electrode  72   a  and the lead-out line  72   h  are formed from source metal SM, and the second capacitor electrode  74   a  and the lead-out line  74   h  are formed from gate metal GM. 
     As to the TFT  71  arranged as above, if it is found out by an inspection conducted after manufacturing that leakage has occurred in the capacitor  71   a  due to a leakage defect L 2  caused between at least one of the first capacitor electrodes  72   a  and the second capacitor electrode  74   a  or for other reasons, the first capacitor electrode  72   a  having the leakage. defect L 2  is electrically separated from the lead-out line  72   h . Specifically, the lead-out line  72   h  is provided at a distance from a region above the second capacitor electrode  74   a  in the thickness direction. The first capacitor electrode  72   a  having the leakage defect L 2  is laser-fused at a point Q 2 . The point Q 2  lies on the first capacitor electrode  72   a  of interest in the range extending from the lead-out line  72   h  to the region above the second capacitor electrode  74   a  in the thickness direction. In this manner, the first capacitor electrode  72   a  having the leakage defect L 2  is separated from the lead-out line  72   h . The inspection may be an electrical inspection or a visual inspection. If it is difficult to localize the leakage defect  72   h  in any of the first capacitor electrodes  72   a  by the electrical inspection, the visual inspection is useful. 
     In the first capacitor electrode  72   a , a cutout  73  may be provided in the first capacitor electrode  72   a  at an overlap boarder where the first capacitor electrode  72   a  extending from the lead-out line  72   h  side overlaps with the second capacitor electrode  74   a . Additionally, cutouts  74  and  75  may be provided in a branch point of the lead-out line  72   h  from which point the first capacitor electrode  72   a  is branched off, at two spots adjoining the first capacitor electrode  72   a . This makes it easy to determine a spot that can be laser-fused, by following the cutouts  73 ,  74 , and  75  as markings. Note that the cutout  73  may be provided in plurality at the same first capacitor electrode  72   a , and the cutouts  74  and  75  may be provided in the first capacitor electrode  72   a.    
     Capacitances provided between the first capacitor electrodes  72   a  and the second capacitor electrode  74   a  (hereinafter referred to as partial capacitances) are connected in parallel to each other. These capacitances constitute the total capacitance of the capacity  71   a  in its entirety (hereinafter referred to as total capacitance). If these partial capacitances are sufficiently small as compared with the total capacitance, separation of a small number of the first capacitor electrodes  72   a  with the leakage defect L 2  from the lead-out line  72   h  causes negligible difference in total capacitance between before and after separation of the first capacitor electrodes  72   a.    
     Thus, the occurrence of leakage in the TFT  71  does not mean a failure of the entire TFT  71 . Such a TFT  71  is serviceable by repair to the capacitor  71   a.    
     Example 3 
     The following will describe a TFT of the present example with reference to  FIGS. 4 and 5 . 
       FIG. 4  shows a plan view of the structure of a TFT  81  applicable to the transistor Tr 4  and provided on the display panel  2 , according to the present example. 
     The TFT  81  includes a TFT body section  81   a , capacitors  81   b  and  81   c , and interconnections  82   c  and  84   c . Each of the capacitors  81   b  and  81   c  is a capacitor capable of serving as a bootstrap capacitor and applicable to the capacitor CAP. 
     The TFT body section  81   a  has a comb-shaped source electrode  82  and a comb-shaped drain electrode  83  disposed above a gate electrode  84  in a thickness direction, and opposed to each other in a panel plane in such a manner that the source electrode  82  and drain electrode  83  are engaged with each other, which secures a large channel width. However, this is merely one arrangement example. The source electrode  82 , the drain electrode  83 , and the gate electrode  84  may be disposed at any positions with any shapes. 
     The capacitor  81   b  is formed so as to have a region where a first capacitor electrode  82   a  and a second capacitor electrode  84   a  are arranged to be stacked in the thickness direction and mutually opposed across a gate dielectric layer (first dielectric layer, see  FIG. 5 )  86  therebetween. The capacitor  81   b  is also formed so as to have a region where the first capacitor electrode  82   a  and a third capacitor electrode  80   a  are arranged to be stacked in the thickness direction and mutually opposed across a passivation layer (second dielectric layer, see  FIG. 5 )  89  therebetween, with a coupling between the first capacitor electrode  82   a  and the third capacitor electrode  80   a  and a coupling between the first capacitor electrode  82   a  and the second capacitor electrode  84   a  formed over mutually opposite faces of the first capacitor electrode  82   a . The first capacitor electrode  82   a  is formed so as to be led out from the source electrode  82  of the TFT body section  81   a  through a lead-out line  82   h  in a planar direction. The second capacitor electrode  84   a  is formed so as to be led out from the gate electrode  84  of the TFT body section  81   a  through a lead-out line (second lead-out line)  84   h  in a planar direction. The third capacitor electrode  80   a  is formed from a transparent electrode (see  FIG. 5 ) TM. From the third capacitor electrode  80   a , a lead-out line (third lead-out line)  80   c  is led out, and the lead-out line  80   c  is connected via a contact hole  85   a  to a lead-out line  84   d  that has been led out from the gate electrode  84  in a planar direction. 
     The first capacitor electrode  82   a  is connected to an output OUT of the shift register stage SR via a lead-out line (first lead-out line)  82   i  in a planar direction. The output OUT is connected via a contact hole  85   c  to the gate bus line GL which lies at a lower position in the thickness direction. 
     The capacitor  81   c  is disposed adjacent to the capacitor  81   b  and formed so as to have a region where a fourth capacitor electrode  82   b  and a fifth capacitor electrode  84   b  are arranged to be stacked in the thickness direction and mutually opposed across a gate dielectric layer (third dielectric layer)  86  therebetween. The capacitor  81   c  is also formed so as to have a region where the fourth capacitor electrode  82   b  and a sixth capacitor electrode  80   b  are arranged to be stacked in the thickness direction and mutually opposed across a passivation layer (fourth dielectric layer)  89  therebetween, with a coupling between the fourth capacitor electrode  82   b  and the sixth capacitor electrode  80   b  and a coupling between the fourth capacitor electrode  82   b  and the fifth capacitor electrode  84   b  formed over mutually opposite faces of the fourth capacitor electrode. The first dielectric layer and the third dielectric layer may be dielectric layers different from each other. Also, the second dielectric layer and the fourth dielectric layer may be dielectric layers different from each other. The sixth capacitor electrode  80   b  is formed from a transparent electrode (see  FIG. 5 ) TM. From the sixth capacitor electrode  80   b , a lead-out line  80   d  is led out in a planar direction. The lead-out line  80   d  is connected via a contact hole  85   b  to a lead-out line (fifth lead-out line)  84   e , which is led out from the fifth capacitor electrode  84   b  in a planar direction. Further, from the fourth capacitor electrode  82   b , a lead-out line (fourth lead-out line)  82   j  is led out in a planar direction. 
     In this case, the capacitors  81   b  and  81   c  are designed so as to have the same value of capacitance. 
     The interconnection (first interconnection)  82   c  is provided so as to intersect both of the lead-out lines  84   d  and  84   e  at upper positions in the thickness direction. The interconnection (second interconnection)  84   c  is provided so as to intersect both of the lead-out lines  82   i  and  82   j  at lower positions in the thickness direction. 
     (a) of  FIG. 5  shows a cross-sectional view taken along the line B-B′ in  FIG. 4 , and (b) of  FIG. 5  shows a cross-sectional view taken along the line C-C′ in  FIG. 4 . 
     As shown in the cross-sectional views in  FIG. 5 , the arrangement in  FIG. 4  is such that: a gate metal GM, the gate dielectric layer  86 , an i layer  87  formed from Si, an n+ layer  88  formed from Si, a source metal SM, a passivation layer  89 , and a transparent electrode TM are stacked on a glass substrate  60  in this order. The gate electrode  84 , the second capacitor electrode  84   a , the lead-out line  84   d , the interconnection  84   c , and the gate bus line GL are all formed from the gate metal GM that has been formed in a concurrent manufacturing process. For example, the gate metal GM can be used in a single layer of Ta (or TaN), Ti (or TiN), Al (or an alloy whose major component is Al), Mo (or MoN), or Cr or used in a stack with any combinations of these metals. The source electrode  82 , the drain electrode  83 , the first capacitor electrode  82   a , the lead-out line  82   i , and the interconnection  82   c  are all formed from the source metal SM that has been formed in the concurrent manufacturing process. The source metal SM can be formed from the same materials) as the material(s) for the gate metal GM. For example, the source metal SM can be used in a single layer of Ta (or TaN), Ti (or TiN), Al (or an alloy whose major component is Al), Mo (or MoN), or Cr or used in a stack with any combinations of these metals. Further, both of the third capacitor electrode  80   a  and the sixth capacitor electrode  80   b  are formed from the transparent electrode TM that has been formed at a time with the transparent electrode TM for pixel electrode in the manufacturing process. As the transparent electrode TM, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or the like can be used. 
     As the gate dielectric layer  86 , for example, SiN or SiO 2 , or the like can be used. As the passivation layer  89 , for example, SiN, SiO 2 , an organic resin film, or the like material can be used. 
     The i layer  87  is a layer that serves as a channel forming region in the TFT body section  81   a . The n+ layer  88  is provided as a source/drain contact layer between the i layer  87  and the source electrode  82  and between the i layer  87  and the drain electrode  83 . 
     Besides, in  FIG. 4 , the fifth capacitor electrode  84   b  and the lead-out line  84   e  are formed from the gate metal GM, and the fourth capacitor electrode  82   b  and the lead-out lines  82   h  and  82   j  are formed from the source metal SM. 
     As to the TFT  81  arranged as above, during the manufacture of the TFT  81 , the capacitor  81   b  is electrically connected to the TFT body section  81   a  through the lead-out lines  82   h ,  84   h , and  80   c , while the capacitor  81   c  is not electrically connected to the TFT body section  81   a  since the fourth capacitor electrode  82   b  and the fifth capacitor electrode  84   b  are not connected to the source electrode  82  and the gate electrode  84 , respectively. If it is found out by an inspection conducted after manufacturing that leakage has occurred due to a leakage defect L 1  between the first capacitor electrode  82   a  and the third capacitor electrode  80   a , no voltage is applied to the capacitor  81   b  through both of the lead-out lines  82   h  and  84   h  and both of the lead-out lines  82   h  and  80   c , and the capacitor  81   c  is made electrically connected to the TFT body section  81   a  through the lead-out line  82   j  and the interconnections  84   c  and  82   c . The inspection may be an electrical inspection or a visual inspection. 
     Specifically, the interconnection  82   c  and the lead-out lines  84   d  and  84   e  are made connected to each other at intersection points P 5  and P 6  by laser welding, so that the fifth capacitor electrode  84   b  and the sixth capacitor electrode  80   b  are connected to the gate electrode  84 , and the interconnection  84   c  and the lead-out lines  82   i  and  82   j  are made connected to each other at intersection points P 7  and P 8  by laser welding, so that the fourth capacitor electrode  82   b  is connected to the source electrode  82 . Further, the lead-out line  84   h  is subjected to laser fusing at a midpoint Q 3   x , and the lead-out line  80   c  is subjected to laser fusing at a midpoint Q 3   y , so that the second capacitor electrode  84   a  and the third capacitor electrode  80   a  are separated from the gate electrode  84 . 
     Thus, the occurrence of leakage in the capacitor  81   b  of the TFT  81  does not mean a failure of the entire TFT  81 . Such a TFT  81  is serviceable with the capacitor  81   c  used as an alternative bootstrap capacitor. 
     Further, the capacitor  81   b  is arranged such that capacitance formed between the first capacitor electrode  82   a  and the second capacitor electrode  84   a  are connected in parallel to capacitance formed between the first capacitor electrode  82   a  and the third capacitor electrode  80   a . Still further, the capacitor  81   c  is arranged such that capacitance formed between the fourth capacitor electrode  82   b  and the fifth capacitor electrode  84   b  are connected in parallel to capacitance formed between the fourth capacitor electrode  82   b  and the sixth capacitor electrode  80   b . Therefore, under the conditions where the gate dielectric layer  86  is equal in thickness to the passivation layer  89 , a footprint of each of the capacitors  81   b  and  81   c  on the panel, which area is determined by H×W in  FIG. 12   c , can be reduced to about one half, as compared with the conventional arrangement without parallel connection. Further, under the conditions where a layer thickness of the passivation layer  89  is one half of that of the gate dielectric layer  86 , a footprint of each of the capacitors  81   b  and  81   c  can be reduced to about one third, as compared to the conventional arrangement without parallel connection. Consequently, the alternative capacitor can be formed to address the occurrence of leakage, without increase of a footprint of the entire capacitor element occupied on the panel. 
     Note that the alternative capacitor like the capacitor  81   c  is not limited to one alternative capacitor. Alternatively, a plurality of alternative capacitors may be provided. In this case, one available alternative capacitor can be selected from among them for use at the occurrence of leakage. 
     Example 4 
     A TFT of the present example will be described with reference to  FIG. 6 . Unless otherwise noted, members given the same reference numerals as those shown in  FIGS. 4 and 5  have the same functions as the members in  FIGS. 4 and 5 . 
       FIG. 6  shows a plan view of the structure of a TFT  91  applicable to the transistor Tr 4  and provided on the display panel  2 , according to the present example. 
     The TFT  91  includes a TFT body section  81   a , a capacitor  91   a , and interconnections  92   h  and  94   h . The capacitor  91   a  is a capacitor capable of serving as a bootstrap capacitor and applicable to the capacitor CAP. 
     The capacitor  91   b  is formed so as to have a region where a plurality of first capacitor electrodes  92   a  and a second capacitor electrode  94   a  are arranged to be stacked in a thickness direction and mutually opposed across a gate dielectric layer (first dielectric layer)  86  therebetween. The capacitor  91   b  is also formed so as to have a region where the plurality of first capacitor electrodes  92   a  and a third capacitor electrode  90   a  are arranged to be stacked in a thickness direction and mutually opposed across a passivation layer (second dielectric layer)  89  therebetween, with a coupling between the first capacitor electrode  92   a  and the third capacitor electrode  90   a  and a coupling between the first capacitor electrode  92   a  and the second capacitor electrode  94   a  formed over mutually opposite faces of the first capacitor electrode. The plurality of first capacitor electrodes  92   a  are formed so as to be led out from the lead-out line  92   h , which is led out from the source electrode  82  of the TFT body section  81   a , and to be branched off in a comb-like manner in a planar direction. The second capacitor electrode  94   a  is formed so as to be led out from the gate electrode  84  of the TFT body section  81   a  through a lead-out line  94   h  in a planar direction. From the third capacitor electrode  90   a , a lead-out line  90   c  is led out, and the lead-out line  90   c  is connected via a contact hole  95   b  to a lead-out line  84   d.    
     The lead-out line  92   h  is connected to an output OUT of the shift register stage SR, and the output OUT is connected via a contact hole  85   c  to the gate bus line GL which lies at a lower position in the thickness direction. 
     The plurality of first capacitor electrode  92   a  and the lead-out line  92   h  are formed from source metal SM, and the second capacitor electrode  94   a  and the lead-out line  94   h  are formed from gate metal GM. The third capacitor electrode  90   a  is formed from a transparent electrode TM. 
     As to the TFT  91  arranged as above, if it is found out by an inspection conducted after manufacturing that leakage has occurred in the capacitor  91   a  due to a leakage defect L 4  caused between at least one of the first capacitor electrodes  92   a  and the second capacitor electrode  94   a  or between at least one of the first capacitor electrodes  92   a  and the third capacitor electrode  90   a , or for other reasons, the first capacitor electrode  92   a  having the leakage defect L 4  is electrically separated from the lead-out line  92   h . Specifically, the lead-out line  92   h  is provided at a distance from a region above the second capacitor electrode  94   a  in the thickness direction and from a region below the third capacitor electrode  90   a  in the thickness direction. The first capacitor electrode  92   a  having the leakage defect L 4  is laser-fused at a point Q 4 . The point Q 4  lies on the first capacitor electrode  92   a  of interest in the range extending from the lead-out line  92   h  to either region closer to the lead-out line  92   h  of (i) the region above the second capacitor electrode  94   a  in the thickness direction and (ii) the region below the third capacitor electrode  90   a  in the thickness direction. In this manner, the first capacitor electrode  92   a  having the leakage defect L 4  is separated from the lead-out line  92   h . The inspection may be an electrical inspection or a visual inspection. If it is difficult to localize the leakage defect  92   h  in any of the first capacitor electrodes  92   a  by the electrical inspection, the visual inspection is useful. 
     In the first capacitor electrode  92   a , a cutout  93  may be provided in the first capacitor electrode  92   a  at an overlap boarder where the first capacitor electrode  92   a  extending from the lead-out line  92   h  side overlaps with either of the second capacitor electrode  94   a  and the third capacitor electrode  90   a  closer to the lead-out line  92   h . Additionally, cutouts  94  and  95  may be provided in a branch point of the lead-out line  72   h  from which point the first capacitor electrode  92   a  is branched off, at two spots adjoining the first capacitor electrode  92   a . This makes it easy to determine a place that can be laser-fused, by following the cutouts  93 ,  94 , and  95  as markings. Note that the cutout  93  may be provided in plurality at the same first capacitor electrode  92   a , and the cutouts  94  and  95  may be provided in the first capacitor electrode  92   a.    
     Capacitances provided between the first capacitor electrodes  92   a  and the second capacitor electrode  94   a  (hereinafter referred to as first partial capacitances) are connected in parallel to each other. In addition, capacitances provided between the first capacitor electrodes  92   a  and the third capacitor electrode  90   a  (hereinafter referred to as second partial capacitances) are connected in parallel to each other. These capacitances constitute the total capacitance of the capacity  91   a  in its entirety (hereinafter referred to as total capacitance). If a sum of the first and second partial capacitances is sufficiently small as compared with the total capacitance, separation of a small number of the first capacitor electrodes  92   a  with the leakage defect L 4  from the lead-out line  92   h  causes negligible difference in total capacitance between before and after separation of the first capacitor electrodes  92   a.    
     Thus, the occurrence of leakage in the capacitor  91   a  of the TFT  91  does not mean a failure of the entire TFT  91 . Such a TFT  91  is serviceable by repair to the capacitor  91   a.    
     Further, the capacitor  91   b  is arranged such that capacitances formed between the first capacitor electrodes  92   a  and the second capacitor electrode  94   a  are connected in parallel to capacitances formed between the first capacitor electrodes  92   a  and the third capacitor electrode  80   a . Therefore, a total area of the plurality of comb-shaped first capacitor electrodes  92   a  can be made smaller than electrode areas of a bootstrap capacitor in the form of a single normal parallel plate capacitor, without increase of a footprint of the entire capacitor element occupied on the panel. 
     All of the examples have been described above. In Examples 1 and 2, the source metal SM is located at an upper position than the gate metal GM when viewed in the thickness direction. However, this is not the only possibility. Alternatively, the source metal SM may be located at a lower position than the gate metal GM when viewed in the thickness direction. Further, in Examples 3 and 4, the locations of the gate metal GM and the transparent electrode TM may be reversed as long as the source metal SM is provided between the gate metal GM and the transparent electrode TM. 
     Further, gate drivers can be provided so as to adjoin to opposite sides of the display region  2   a  or to adjoin to one of the opposite sides of the display region  2   a . Thus, the gate driver(s) may be positioned at a desired place(s). 
     Still further, the TFT may be used at any spot in a display device, or may be used at a place other than the display device. 
     Yet further, the present invention can be applied to any other display devices such as an electroluminescent display device, without limitation to a liquid crystal display device. 
     The present invention is not limited to the aforementioned embodiments and is susceptible of various changes within the scope of the accompanying claims. Also, an embodiment obtained by suitable combinations of technical means disclosed in the different embodiments are also included within the technical scope of the present invention. 
     INDUSTRIAL APPLICABILITY 
     The present invention can be suitably used for a display device including a TFT.