Abstract:
Disclosed are various embodiments for a power stage that can drive various types of loads. The power stage includes a first capacitor and a second capacitor that are coupled to the load. The power stage also includes switches that are operable in a first power stage state and a second power stage state. When the switches are in the first power stage state, the first capacitor discharges to the load, and the second capacitor charges. When the switches are in the second power stage state, the second capacitor discharges to the load, and the first capacitor charges.

Description:
CROSS-REFERENCE TO RELATED CASES 
       [0001]    This application claims priority to co-pending U.S. Provisional Patent Application 61/665,733, titled “Three Level LED Drivers, and Methods of Use Thereof,” and filed on Jun. 28, 2012, which is incorporated by reference herein in its entirety. 
     
    
     BACKGROUND 
       [0002]    DC-DC power supply systems may be used to efficiently power modern electronic devices and circuits. For example, light emitting diode (LED) circuits may employ an LED driver to illuminate one or more LEDs. To control the illumination, the LED driver may attempt to regulate output currents and output voltages such that they are at relatively constant levels. While early generation of LED drivers employed open loop driver designs, there may be considerable variations in the forward diode voltage of the LEDs due to process variations, operating temperatures, device ageing, the usage time of the LEDs, the wavelength of the light emitted by the LEDs, and/or other factors. Thus, closed loop drivers can be used to achieve uniform brightness and high efficiency. 
         [0003]    Various LED drivers may employ buck, boost, or floating buck power stage topologies. Because some lighting systems may include a large number of LEDs connected in series, the output voltage for a power stage can be several tens of volts. Thus, switches in the power stage can be subjected to considerable voltage stress. As a result, the reliability of the power stage may be impacted. 
         [0004]    Furthermore, various LED applications, such as backlights for display devices, may employ multiple “strings” of LEDs. Such systems may use multiple LED drivers. However, the use of multiple LED drivers may result in high costs and/or the use of bulky components, and the efficiency may be relatively poor. Additionally, complex control circuitry may be used to ensure that a relatively constant current is delivered by each power stage for each respective LED string. 
         [0005]    In some power stage designs of LED drivers, low-voltage integrated circuit (IC) technologies cannot be used because of the corresponding dielectric breakdown, junction breakdown, hot carriers, and/or other parameters. Instead, high-voltage transistors comprising thick gate oxides and drain extensions may be used. However, high-voltage transistors may result in higher costs as compared to low-voltage transistors. 
         [0006]    Various power stage designs may use multiple switches that are connected in series in order to distribute the voltage stress that a single switch would otherwise experience. However, having multiple switches perform the function of a single switch may increase the cost and/or silicon real estate requirements for an LED driver. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0008]      FIG. 1  is drawing of an example of a power stage. 
           [0009]      FIGS. 2A-2D  are drawings showing an example of the operation of the power stage of  FIG. 1 . 
           [0010]      FIG. 3  is a timing diagram showing an example of signals associated with the power stage of  FIG. 1 . 
           [0011]      FIG. 4  is a drawing of another example of a power stage, which is capable of delivering multiple supply voltages. 
           [0012]      FIG. 5  is a timing diagram showing an example of signals associated with the power stage of  FIG. 4 . 
           [0013]      FIG. 6  is a drawing of another example of a power stage capable of delivering bipolar voltages. 
           [0014]      FIG. 7  is a flowchart illustrating an example of functionality implemented by the power stage of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    The present disclosure is directed towards three-level power stages that can provide output voltages and/or currents to one or more loads. With reference to  FIG. 1  shown is an example of a power stage  100 . In particular, the power stage  100  shown in  FIG. 1  is coupled to a voltage source  103 , a controller  106 , and a load  109 . 
         [0016]    The power stage  100  is configured to provide an output voltage V out  for the load  109 . As such, the power stage  100  may be regarded as being a direct current (DC)-to-DC converter, an LED driver, or any other type of circuitry that provides an output voltage V out . Such a DC-DC converter in various embodiments may employ a three-level buck, a boost, a floating-buck, or any other type of suitable power stage architecture. The power stage  100  may be considered a three-level power stage, because various components of the power stage  100  may be subjected to three voltage levels at various times during operation. 
         [0017]    In various embodiments, the power stage  100  comprises an inductor  113 , a first switch  116 , a second switch  119 , a third switch  123 , a fourth switch  126 , a first capacitor  133 , a second capacitor  136 , and/or other components. The inductor  113  is a component that is configured to be energized and de-energized by suitably controlling the voltage across its terminals. In the embodiment shown in  FIG. 1 , the positive terminal of the inductor  113  is coupled to the positive terminal of the voltage source  103 . The negative terminal of the inductor  113  is coupled to the first switch  116  and the third switch  123  as shown. 
         [0018]    The first switch  116 , the second switch  119 , the third switch  123 , and the fourth switch  126  are components that are configured to operate in respective on states and off states. When the first switch  116 , for example, is in the off state, electrical currents are restricted from flowing through the first switch  116 . Alternatively, configuring the first switch  116  to be in the on state facilities electrical currents flowing through the first switch  116 . Thus, the first switch  116 , the second switch  119 , the third switch  123 , and the fourth switch  126  can each selectively restrict and facilitate current flow. As such, in various embodiments, each of the first switch  116 , the second switch  119 , the third switch  123 , and/or the fourth switch  126  may comprise a transistor, a relay, or any other suitable type of switching element. Such a transistor may be embodied in the form of a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), or any other type of available transistor. 
         [0019]    As shown in  FIG. 1 , a first terminal of the first switch  116  is coupled to the negative terminal of the inductor  113  and to a first terminal of the third switch  123 . A second terminal of the first switch  116  is coupled to a first terminal of the second switch  119  and to a first terminal (e.g., the bottom plate in  FIG. 1 ) of the first capacitor  133  and to a first terminal (e.g., the top plate) of the second capacitor  136  as shown. A first terminal of the second switch  119  is coupled to the second terminal of the first switch  116  and to the first terminal (e.g., the bottom plate) of the first capacitor  133  and the first terminal (e.g., the top plate) of the second capacitor  136  as shown. A second terminal of the second switch  119  is coupled to the negative terminal of the voltage source  103  and a first terminal of the fourth switch  126  as shown. 
         [0020]    A first terminal of the third switch  123  is coupled to the negative terminal of the inductor  113  and to the first terminal of the first switch  116 . A second terminal of the third switch  123  is coupled to a second terminal (e.g., the top plate in  FIG. 1 ) of the first capacitor  133  as shown. The first terminal of the fourth switch  126  is coupled to the output terminal of the second switch  119  and to the negative terminal of the voltage source  103 . The second terminal of the fourth switch  126  is coupled to the ground node and to a second terminal (e.g., the bottom plate) of the second capacitor  136 . 
         [0021]    The first capacitor  133  and the second capacitor  136  are each configured to charge and discharge, as may be appreciated. The second terminal of the first capacitor  133  is coupled to the second terminal of the third switch  123  and to the load  109  as shown. The first terminal of the first capacitor  133  is coupled to the first terminal of the second capacitor  136 , to the second terminal of the first switch  116  and to the first terminal of the second switch  119  as shown. 
         [0022]    The power stage  100  operates in various states to appropriately energize or de-energize the inductor  113 , which will be discussed in more detail later. Additionally, in various states, the first capacitor  133  and/or the second capacitor  136  may be charged or discharged. To configure the power stage  100  in a particular state, the first switch  116 , the second switch  119 , the third switch  123 , and/or the fourth switch  126  can be configured to be in appropriate on states or off states, as will be described in more detail later. 
         [0023]    The voltage source  103  is configured to provide an input voltage V in  to the power stage  100 . To this end, the voltage source  103  may comprise, for example, a battery or any other suitable type of voltage supply. 
         [0024]    The load  109  comprises one or more components that are powered through the output voltage V out  from the power stage  100 . In the embodiment shown in  FIG. 1 , the load  109  comprises one or more LEDs  139  and a resistor  143 . Thus, the power stage  100  in the embodiment shown in  FIG. 1  can be regarded as being an LED driver. In alternative embodiments, the load  109  can comprise a digital pulse generator (e.g., for an ultrasound medical imaging system) or any other type of component that is configured to receive power from the power stage  100 . 
         [0025]    A sense voltage V sns  is also associated with the load  109 . For example, the level of the sense voltage V sns  may correspond to the level of the output voltage V out , the average load current, and/or any other signal of interest. Thus, as will be discussed in more detail later, the sense voltage V sns  can be used as an indicator in order to adjust the load current or the output voltage V out  to a desired value. 
         [0026]    The controller  106  is configured to control various aspects of the operation of the power stage  100 . For example, the controller  106  may cause the first switch  116 , the second switch  119 , the third switch  123 , and/or the fourth switch  126  to be in various on states or off states. To this end, the controller  106  outputs one or more control signals, such as the first control signal S 1 , the second control signal S 2 , the third control signal S 3 , and the fourth control signal S 4  that control the first switch  116 , the second switch  119 , the third switch  123 , and/or the fourth switch  126 , respectively, to be in their desired states. For instance, for embodiments in which the first switch  116  is a n-channel MOSFET, the controller  106  can assert a high voltage control signal or a low voltage control signal, as applicable, to cause the first switch  116  to be in the on state or the off state. 
         [0027]    The controller  106  in the embodiment of  FIG. 1  also receives the sense voltage V sns  and a reference voltage V ref . The controller  106  may respond to a comparison between the level of the sense voltage V sns  and the reference voltage V ref  and adjust one or more control signals to thereby adjust the output voltage V out  and/or the load current. For example, the controller  106  may increase or decrease one or more duty cycles for the power stage  100  in order to increase or decrease the level of the output voltage V out . In this regard, the controller  106  may adjust the amount of time that one or more of the switches is in the open state or the closed state to thereby adjust the resulting output voltage V out  and/or load current. Furthermore, the controller  106  can adjust the amount of time that the power stage  100  is in one or more of the various states to thereby adjust the resulting output voltage V out . It is understood that any other suitable type of controller  106  can be used to control the power stage  100  in alternative embodiments. 
         [0028]    With reference to  FIGS. 2A-2D , a description of an example of the operation of the power stage  100  is provided.  FIGS. 2A-2D  are drawings depicting a progression of the power stage  100  in various states. In  FIGS. 2A-2D ,  106  ( FIG. 1 ) is not shown for the purposes of clarity. 
         [0029]    Beginning with  FIG. 2A , shown is the power stage  100  in a particular state. In this state, the first switch  116  is in the on state, the second switch  119  is in the on state, the third switch  123  is in the off state, and the fourth switch  126  is in the off state. Because these switches  116 - 126  are in these respective states, a positive voltage V in  across the terminals of the inductor  113  results in a current I L  that flows from the voltage source  103 , through the inductor  113 , through the first switch  116 , through the second switch  119 , and to the voltage source  103 . As a result of the current I L  flowing through the inductor  113 , the inductor  113  becomes energized. 
         [0030]    Additionally, the first capacitor  133  and/or the second capacitor  136  may have been previously charged. As such, when the power stage  100  is in the state shown in  FIG. 2A , the first capacitor  133  and/or the second capacitor  136  may discharge to the load  109  and thereby provide the output voltage V out . Thus, when the power stage  100  is in the state shown in  FIG. 2A , the inductor  113  energizes, and the first capacitor  133  and/or the second capacitor  136  may discharge to the load  109 . 
         [0031]    With reference to  FIG. 2B , shown is the power stage  100  in another state. The controller  106  ( FIG. 1 ) may configure the power stage  100  to be in this state subsequent to the power stage  100  being in the previous state shown in  FIG. 2A . 
         [0032]    In the state shown in  FIG. 2B , the first switch  116  is in the on state, the second switch  119  is in the off state, the third switch  123  is in the off state, and the fourth switch  126  is in the on state. Because these switches  116 - 126  are in these respective states, a current I L  flows from the voltage source  103 , through the inductor  113 , through the first switch  116 , through the second capacitor  136 , through the fourth switch  126 , and to the voltage source  103 . As a result, the inductor  113  de-energizes, and the energy from the inductor  113  charges the second capacitor  136 . Additionally, when the power stage  100  is in the state shown in  FIG. 2B , the first capacitor  133  may discharge to the load  109  and thereby provide the output voltage V out . Thus, when the power stage  100  is in the state shown in  FIG. 2B , the inductor  113  de-energizes, the second capacitor  136  charges, and the first capacitor  133  may discharge to the load  109 . 
         [0033]    With reference to  FIG. 2C , shown is the power stage  100  in another state. The controller  106  ( FIG. 1 ) may configure the power stage  100  to be in this state subsequent to the power stage  100  being in the previous state shown in  FIG. 2B . 
         [0034]    In the state shown in  FIG. 2C , the first switch  116  is in the on state, the second switch  119  is in the on state, the third switch  123  is in the off state, and the fourth switch  126  is in the off state. Because these switches  116 - 126  are in these respective states, a current I L  flows from the voltage source  103 , through the inductor  113 , through the first switch  116 , through the second switch  119 , and to the voltage source  103 . As a result of the current I L  flowing through the inductor  113 , the inductor  113  becomes energized. 
         [0035]    Additionally, the first capacitor  133  and/or the second capacitor  136  may have been previously charged. As such, when the power stage  100  is in the state shown in  FIG. 2C , the first capacitor  133  and/or the second capacitor  136  may discharge to the load  109  and thereby provide the output voltage V out . Thus, when the power stage  100  is in the state shown in  FIG. 2C , the inductor  113  energizes, and the first capacitor  133  and/or the second capacitor  136  may discharge to the load  109 . 
         [0036]    With reference to  FIG. 2D , shown is the power stage  100  in another state. The controller  106  ( FIG. 1 ) may configure the power stage  100  to be in this state subsequent to the power stage  100  being in the previous state shown in  FIG. 2C . 
         [0037]    In the state shown in  FIG. 2D , the first switch  116  is in the off state, the second switch  119  is in the on state, the third switch  123  is in the on state, and the fourth switch  126  is in the off state. Because these switches  116 - 126  are in these respective states, a current I L  flows from the voltage source  103 , through the inductor  113 , through the third switch  123 , through the first capacitor  133 , through the second switch  119 , and to the voltage source  103 . As such, the inductor  113  de-energizes to charge the first capacitor  133 . Additionally, when the power stage  100  is in the state shown in  FIG. 2D , the second capacitor  136  may discharge to the load  109  and thereby provide the output voltage V out . Thus, when the power stage  100  is in the state shown in  FIG. 2D , the inductor  113  de-energizes, the first capacitor  133  charges, and the second capacitor  136  may discharge to the load  109 . The controller  106  may then configure the power stage  100  to be in the state that is shown in  FIG. 2A , and the process described above with respect to  FIGS. 2A-2D  may be repeated. 
         [0038]    It may be appreciated that in all of the states of the power stage  100  shown in  FIGS. 2A-2D , the greatest voltage level across the first switch  116 , the second switch  119 , the third switch  123 , and the fourth switch  126  is half of the level of the output voltage V out . As such, various power stages  100  in accordance with the present disclosure may employ relatively low-voltage transistor technologies. For example, low-voltage transistors can be used for the first switch  116 , the second switch  119 , the third switch  123 , and/or the fourth switch  126 . As a result, the power stage  100  may occupy a relatively small area, with lower cost, improved circuit reliability, and potentially other benefits being achieved. 
         [0039]    With reference to  FIG. 3 , shown is a timing diagram depicting an example of the functionality associated with the power stage  100  ( FIG. 1 ). In particular, the timing diagram of  FIG. 3  shows the levels of the current I L , the output voltage V out  for the load  109  ( FIG. 1 ), the first control signal S 1  that controls the first switch  116  (FIG.  1 ), the second control signal S 2  that controls the second switch  119  ( FIG. 1 ), the third control signal S 3  that controls the third switch  123  ( FIG. 1 ), and the fourth control signal S 4  that controls the fourth switch  126  ( FIG. 1 ). In the embodiment shown in  FIG. 3 , high levels for the first control signal S 1 , the second control signal S 2 , the third control signal S 3 , and the fourth control signal S 4  cause the respective switches to be in the on states. Additionally, low levels for the first control signal S 1 , the second control signal S 2 , the third control signal S 3 , and the fourth control signal S 4  cause the respective switches to be in the off states. However, it is understood that in alternative embodiments, alternative signal levels may cause the respective switches to be in the off states or the on states. 
         [0040]    Beginning at time t 1 , the power stage  100  is in the state that was previously discussed with reference to  FIG. 2A . As shown in  FIG. 3 , the current I L  increases as time progresses due to the positive voltage of V in  across the terminals of the inductor  113 . Additionally, the output voltage V out  is at a relatively constant level. The first control signal S 1  and the second control signal S 2  are high, causing the first switch  116  and the second switch  119  to be in on states. The third control signal S 3  and the fourth control signal S 4  are low, causing the third switch  123  and the fourth switch  126  to be in off states. 
         [0041]    At time t 2 , the power stage  100  transitions to the state that was previously discussed with respect to  FIG. 2B . As shown, the current I L  decreases as time progresses due to a negative voltage V in −V out /2 being across the terminal of the inductor  113 . Additionally, the output voltage V out  is at a relatively constant level. The first control signal S 1  and the fourth control signal S 4  are high, causing the first switch  116  and the fourth switch  126  to be in on states. The second control signal S 2  and the third control signal S 3  are low, causing the second switch  119  and the third switch  123  to be in off states. 
         [0042]    At time t 3 , the power stage  100  transitions to the state that was previously discussed with respect to  FIG. 2C . As shown, the current I L  increases as time progresses, and the output voltage V out  is at a relatively constant level. The first control signal S 1  and the second control signal S 2  are high, causing the first switch  116  and the second switch  119  to be in on states. The third control signal S 3  and the fourth control signal S 4  are low, causing the third switch  123  and the fourth switch  126  to be in off states. 
         [0043]    At time t 4 , the power stage  100  transitions to the state discussed above with respect to  FIG. 2D . As shown, the current I L  decreases as time progresses, and the output voltage V out  is at a relatively constant level. The second control signal S 2  and the third control signal S 3  are high, causing the second switch  119  and the third switch  123  to be in on states. The first control signal S 1  and the fourth control signal S 4  are low, causing the first switch  116  and the fourth switch  126  to be in off states. 
         [0044]    With reference to  FIG. 4 , shown is a second example of a power stage  100 , referred to herein as the power stage  400 . In particular, the power stage  400  is shown coupled to the voltage source  103 , the controller  106 , and multiple loads  109 , referred to herein as the loads  109   1 - 109   n . 
         [0045]    The power stage  400  is similar to the embodiment of the power stage  100  that is shown in  FIG. 1 . For example, the power stage  400  comprises the inductor  113 , the first switch  116 , the second switch  119 , and the fourth switch  126 . However, an instance of the first capacitor  133 , referred to herein as the first capacitors  133   1 - 133   n , and an instance of the second capacitor  136 , referred to herein as the second capacitors  136   1 - 136   n  are associated with each of the loads  109   1 - 109   n . The first capacitors  133   1 - 133   n  and/or the second capacitors  136   1 - 146   n  charge and discharge in order to provide the corresponding output voltages V out , referred to herein as the output voltages V out1 -V outn , to the corresponding loads  109   1 - 109   n . 
         [0046]    Each of the loads  109   1 - 109   n  is associated with a corresponding sense voltage V sns , referred to herein as the sense voltages V sns1 -V snsn . The levels of the sense voltages V sns1 -S snsn  correspond to the respective output voltages V out1 -V outn , their corresponding loading currents, and/or any other signal of interest. Thus, the sense voltages V sns1 -V snsn  are provided to the controller  106  to facilitate adjusting the various output voltages V out1 -V outn  to desired levels. 
         [0047]    Respective instances of the third switch  123 , referred to herein as the third switches  123   1 - 123   n , are associated with the loads  109   1 - 109   n . For example, the third switch  123   n  corresponds to the load  109   n . First terminals of the third switches  123   1 - 123   n  are coupled to the inductor  113  as shown. Additionally, second terminals of the third switches  123   1 - 123   n  are coupled to the respective first capacitors  133   1 - 133   n  and the corresponding loads  109   1 - 109   n . The third switches  123   1 - 123   n , in conjunction with the fifth switches  403   1 - 403   n , determine which first capacitors  133   1 - 133   n  are to be charged. For instance, the third switch  123   1  determines whether the first capacitor  133   1  is to be charged, and the third switch  123   2  determines whether the first capacitor  133   2  is to be charged. 
         [0048]    Additionally, fifth switches  403   1 - 403   n  are associated with the respective loads  109   1 - 109   n . In this regard, the fifth switch  403   1  corresponds to the load  109   1 , the fifth switch  403   2  corresponds to the load  109   2 , and the fifth switch  403   n  corresponds to the load  109   n . First terminals of the fifth switches  403   1 - 403   n  are coupled to the first switch  116  and to the second switch  119  as shown. Additionally, respective second terminals of the fifth switches  403   1 - 403   n  are coupled to the respective first capacitors  133   1 - 133   n  and the respective second capacitors  136   1 - 136   n  as shown. 
         [0049]    The fifth switches  403   1 - 403   n  are configured to operate in respective on states and off states. For example, when the fifth switch  403   n  operates in the off state, electric currents are restricted from flowing through the fifth switch  403   n . Alternatively, configuring the fifth switch  403   n  to be in the on state facilitates the flow of electrical currents through the fifth switch  403   n . In conjunction with the fourth switch  126 , the fifth switches  403   1 - 403   n  determine which first capacitors  133   1 - 133   n  and second capacitors  136   1 - 136   n  are to be charged. For instance, along with the fourth switch  126 , the fifth switch  403   1  determines whether the first capacitor  133   1  and the second capacitor  136   1  are to be charged, and the fifth switch  403   2  along with the fourth switch  126  determines whether the first capacitor  133   1  and the second capacitor  136   2  are to be charged, and so on. 
         [0050]    The controller  106  in the embodiment shown in  FIG. 4  is similar to the controller  106  discussed with respect to the  FIG. 1 . In the embodiment shown in  FIG. 4 , the controller  106  receives the sense voltages V sns1 -V snsn  as inputs. The controller  106  may also receive reference voltages V ref1 -V refn . The respective reference voltages V ref1 -V refn  may, for example, be compared to the sense voltages V sns1 -V snsn  in order to adjust the output voltages V out1 -V outn  and/or the load currents. 
         [0051]    The controller  106  also outputs the first control signal S 1 , the second control signal S 2 , and the fourth control signal S 4 . Additionally, the controller  106  outputs multiple instances of the third control signal S 3 , referred to herein as the third control signals S 31 -S 3n , and multiple instances of a fifth control signal S 51 -S 5n . The third control signals S 31 -S 3n  control respective ones of the third switches  123   1 - 123   n , and the fifth control signals S 5   1 -S 5   n  control respective ones of the fifth switches  403   1 - 403   n . For example, the third control signal S 3n  determines whether the third switch  123   n  is in its on state or off state, and the fifth control signal S 5n  determines whether the fifth switch  403   n  is in its on state or off state. 
         [0052]    With reference to  FIG. 5 , shown is a timing diagram depicting an example of portions of functionality associated with the power stage  400  ( FIG. 4 ). In, particular, the timing diagram of  FIG. 5  shows the levels of the current I L  that flows through the inductor  113  ( FIG. 4 ), the output voltage V out1  for the load  109   1  ( FIG. 4 ), the output voltage V out2  for the load  109   2  ( FIG. 4 ), the first control signal S 1  that controls the first switch  116  ( FIG. 4 ), the second control signal S 2  that controls the second switch  119  ( FIG. 4 ), the third control signal S 31  that controls the third switch  123   1  ( FIG. 4 ), the third control signal S 32  that controls the third switch  123   2  ( FIG. 4 ), the fourth control signal S 4  that controls the fourth switch  126  ( FIG. 4 ), the fifth control signal S 51  that controls the fifth switch  403   1  ( FIG. 4 ), and the fifth control signal S 52  that controls the fifth control switch  403   2  ( FIG. 4 ). In the embodiment shown in  FIG. 5 , high levels for the first control signal S 1 , the second control signal S 2 , the third control signal S 31  the third control signal S 32 , the fourth control signal S 4 , the fifth control signal S 51 , and the fifth control signal S 52  cause the respective switches to be in the on states. Additionally, low levels for the first control signal S 1 , the second control signal S 2 , the third control signal S 31  the third control signal S 32 , the fourth control signal S 4 , the fifth control signal S 51 , and the fifth control signal S 52  cause the respective switches to be in the off states. However, it is understood that in alternative embodiments, alternative signal levels may cause the respective switches to be in the off states or the on states. 
         [0053]    Beginning at time t 1 , the power stage  400  is in a state in which the inductor  113  energizes. The current I L  increases as time progresses, and the output voltage V out1  and the output voltage V out2  are at relatively constant levels. The first control signal S 1 , the second control signal S 2 , and the fifth control signal S 51  are high, causing the first switch  116 , the second switch  119 , and the fifth switch  403   1  to be in on states. The third control signal S 31 , the third control signal S 32 , the fourth control signal S 4 , and the fifth control signal S 52  are low, causing the third switch  123   1 , the third switch  123   2 , the fourth switch  126 , and the fifth switch  403   2  to be in off states. 
         [0054]    At time t 2 , the power stage  400  transitions to a state in which the inductor  113  de-energizes and the second capacitor  136   1  charges. As shown, the current I L  decreases as time progresses, and the output voltage V out1  and output voltage V out2  are at relatively constant levels. The first control signal S 1 , the fourth control signal S 4 , and the fifth control signal S 51  are high, causing the first switch  116 , the fourth switch  126 , and the fifth switch  403   1  to be in on states. The second control signal S 2 , the third control signal S 31 , the third control signal S 32 , and the fifth control signal S 52  are low, causing the second switch  119 , the third switch  123   1 , the third switch  123   2 , and the fifth switch  403   2  to be in off states. 
         [0055]    At time t 3 , the power stage  400  transitions to a state in which the inductor  113  energizes. As shown, the current I L  increases as time progresses, and the output voltage V out1  and the output voltage V out2  are at relatively constant levels. The first control signal S 1 , the second control signal S 2 , and the fifth control signal S 51  are high, causing the first switch  116 , the second switch  119 , the fifth switch  403   1  to be in on states. The third control signal S 31 , the third control signal S 32 , the fourth control signal S 4 , and the fifth control signal S 52  are low, causing the third switch  123   1 , the third switch  123   2 , the fourth switch  126 , and the fifth switch  403   2  to be in off states. 
         [0056]    At time t 4 , the power stage  400  transitions to a state in which the inductor  113  de-energizes and the first capacitor  133   1  charges. As shown, the current I L  decreases as time progresses, and the output voltage V out1  and the output voltage V out2  are at relatively constant levels. The second control signal S 2 , the third control signal S 31 , and the fifth control signal S 51  are high, causing the second switch  119 , the third switch  123   1 , and the fifth switch  403   1  to be in on states. The first control signal S 1 , the third control signal S 32 , the fourth control signal S 4 , and the fifth control signal S 52  are low, causing the first switch  116 , the third switch  123   2 , the fourth switch  126 , and the fifth switch  403   2  to be in off states. 
         [0057]    At time t 5 , the power stage  400  transitions to a state in which the inductor  113  energizes. The current I L  increases as time progresses, and the output voltage V out1  and the output voltage V out2  are at relatively constant levels. The first control signal S 1 , the second control signal S 2 , and the fifth control signal S 52  are high, causing the first switch  116 , the second switch  119 , and the fifth switch  403   2  to be in on states. The third control signal S 31 , the third control signal S 32 , the fourth control signal S 4 , and the fifth control signal S 51  are low, causing the third switch  123   1 , the third switch  123   2 , the fourth switch  126 , and the fifth switch  403   1  to be in off states. 
         [0058]    At time t 6 , the power stage  400  transitions to a state in which the inductor  113  de-energizes and the second capacitor  136   2  charges. As shown, the current I L  decreases as time progresses, and the output voltage V out1  and output voltage V out2  are at relatively constant levels. The first control signal S 1 , the fourth control signal S 4 , and the fifth control signal S 52  are high, causing the first switch  116 , the fourth switch  126 , and the fifth switch  403   2  to be in on states. The second control signal S 2 , the third control signal S 31 , the third control signal S 32 , and the fifth control signal S 51  are low, causing the second switch  119 , the third switch  123   1 , the third switch  123   2 , and the fifth switch  403   1  to be in off states. 
         [0059]    At time t 7 , the power stage  400  transitions to a state in which the inductor  113  energizes. As shown, the current I L  increases as time progresses, and the output voltage V out1  and the output voltage V out2  are at relatively constant levels. The first control signal S 1 , the second control signal S 2 , and the fifth control signal S 52  are high, causing the first switch  116 , the second switch  119 , and the fifth switch  403   2  to be in on states. The third control signal S 31 , the third control signal S 32 , the fourth control signal S 4 , and the fifth control signal S 51  are low, causing the third switch  123   1 , the third switch  123   2 , the fourth switch  126 , and the fifth switch  403   2  to be in off states. 
         [0060]    At time t 8 , the power stage  400  transitions to a state in which the inductor  113  de-energizes and the first capacitor  133   2  charges. As shown, the current I L  decreases as time progresses, and the output voltage V out1  and the output voltage V out2  are at relatively constant levels. The second control signal S 2 , the third control signal S 32 , and the fifth control signal S 52  are high, causing the second switch  119 , the third switch  123   2 , and the fifth switch  403   2  to be in on states. The first control signal S 1 , the third control signal S 31 , the fourth control signal S 4 , and the fifth control signal S 51  are low, causing the first switch  116 , the third switch  123   1 , the fourth switch  126 , and the fifth switch  403   1  to be in off states. 
         [0061]    With reference to  FIG. 6 , shown is a third example of a three-level power stage  100  ( FIG. 1 ), referred to herein as the power stage  600 . In particular, the power stage  600  is shown coupled to the voltage source  103 , the controller  106 , and the load  109 . 
         [0062]    The power stage  600  is similar to the power stage  100  shown in  FIG. 1 . However, the power stage  600  shown in  FIG. 6  is a bipolar-output power stage. In this regard, the power stage  600  is configured to output a positive output voltage V outP  and a negative output voltage V outN . To this end, the first capacitor  133  and the second capacitor  136  are coupled to ground as shown. Thus, the power stage  600  can provide the positive output voltage V outP  and the negative output voltage V outN  and regulate the outputs by controlling the first switch  116 , the second switch  119 , the third switch  123 , and/or the fourth switch  126  in a manner as previously described. 
         [0063]    The controller  106  in the embodiment shown in  FIG. 6  receives at least one reference voltage V ref , the positive output voltage V outp , and the negative output voltage V outn . The controller  106  may compare the positive output voltage V outp  and/or the negative output voltage V outn  to the voltage V ref  in order to generate the control signals S 1 -S 4  to thereby adjust the positive output voltage V outp , the negative output voltage V outn , and/or the load current. 
         [0064]    With reference to  FIG. 7 , shown is a flowchart illustrating an example of functionality implemented by the power stage  100  and/or the controller. It is understood that the flowchart of  FIG. 7  provides merely an example of the many different types of functionality that may be implemented by power stage  100  and/or the controller  106  as described herein. 
         [0065]    At number  703 , the inductor  113  ( FIG. 1 ) is energized. To this end, the first switch  116  and the second switch  119  may be configured to be in on states, and the third switch  123  and the fourth switch  126  may be configured to be in off states. Simultaneously, the first capacitor  133  ( FIG. 1 ) and/or the second capacitor  136  ( FIG. 1 ) may discharge to provide the output voltage V out . 
         [0066]    As shown at number  706 , the second capacitor  136  is then charged by de-energizing the inductor  113 . Charging the second capacitor  136  by de-energizing the inductor  113  may be accomplished, for example, by configuring the first switch  116  and the fourth switch  126  to be in on states, with the second switch  119  and the third switch  123  in off states. Simultaneously, the first capacitor  133  may discharge to provide the output voltage V out . 
         [0067]    As indicated at number  709 , the inductor  113  is then energized. To this end, the first switch  116  and the second switch  119  may be configured to be in on states, and the third switch  123  and the fourth switch  126  may be configured to be in off states. Simultaneously, the first capacitor  133  and/or the second capacitor  136  may discharge to provide the output voltage V out . 
         [0068]    The first capacitor  133  is then charged by de-energizing the inductor  113 , as shown at number  713 . To charge the first capacitor  133  by de-energizing the inductor  113 , the second switch  119  and the third switch  123  can be configured to be in on states, and the first switch  116  and the fourth switch  126  can be configured to be in off states. Simultaneously, the second capacitor  136  may discharge to provide the output voltage V out . 
         [0069]    Next, as shown at number  716 , the controller  106  obtains the sense voltage V sns . As previously discussed, the level of the sense voltage V sns  may correspond to the level of the output voltage V out  or the load current. Thus, as indicated at number  719 , the controller  106  adjusts one or more duty cycles in order to adjust the level of the output voltage V out . The process described above may be repeated, for example, as long as the power stage  100  and the controller  106  are powered. Thereafter, the process ends. 
         [0070]    Although the flowchart of  FIG. 7  shows a specific order of execution, it is understood that the order of execution may differ from that which is depicted. For example, the order of execution of two or more numbers may be scrambled relative to the order shown. Also, two or more numbers shown in succession may be executed concurrently or with partial concurrence. Further, in some embodiments, one or more of the numbers shown may be skipped or omitted. In addition, any number of elements might be added to the logical flow described herein, for purposes of enhanced utility, accounting, performance measurement, or providing troubleshooting aids, etc. It is understood that all such variations are within the scope of the present disclosure. 
         [0071]    The components described herein may be implemented by circuitry. In this regard, such circuitry may be arranged to perform the various functionality described above by generating and/or responding to electrical or other types of signals. The circuitry may be general purpose hardware or hardware that is dedicated to performing particular functions. The circuitry may include, but is not limited to, discrete components, integrated circuits, or any combination of discrete components and integrated circuits. Such integrated circuits may include, but are not limited to, one or more microprocessors, system-on-chips, application specific integrated circuits, digital signal processors, microcomputers, central processing units, programmable logic devices, state machines, other types of devices, and/or any combination thereof. As used herein, the circuitry may also include interconnects, such as lines, wires, traces, metallization layers, or any other element through which components may be coupled. Additionally, the circuitry may be configured to execute software to implement the functionality described herein. 
         [0072]    It is emphasized that the above-described embodiments of the present disclosure are merely examples of implementations to set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.