Abstract:
A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a divisional of U.S. application Ser. No. 12/777,881, filed on May 11, 2010 the disclosure of which are incorporated herein by reference in their entirety. 
     
    
     FEDERAL RESEARCH STATEMENT 
       [0002]    This invention was made with Government support under Government Contract FA8650-08-C-7806, awarded by the Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention. 
     
    
     FIELD 
       [0003]    This disclosure relates generally to the field of tunnel field effect transistors. 
       DESCRIPTION OF RELATED ART 
       [0004]    Tunnel field effect transistors (TFETs) may be used as a replacement for or complement to metal-oxide-semiconductor FETs (MOSFETs). A TFET may comprise a nanowire channel, which may provide good electrostatic control of the channel due to gate-all-around (GAA) geometry. However, relatively high fields at the drain end of a nanowire channel TFET may lead to parasitic ambipolar behavior that increases the TFET off current, resulting in a relatively inefficient device. 
       SUMMARY 
       [0005]    In one aspect, a tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region. 
         [0006]    Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0007]    Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
           [0008]      FIG. 1  illustrates an embodiment of a method of forming a TFET with a nanowire source. 
           [0009]      FIG. 2  illustrates an embodiment of a silicon-on-insulator (SOI) wafer. 
           [0010]      FIG. 3  illustrates an embodiment of the SOI wafer of  FIG. 2  after formation of a nanowire. 
           [0011]      FIG. 4  illustrates an embodiment of the structure of  FIG. 3  after formation of a gate. 
           [0012]      FIG. 5  illustrates an embodiment of the structure of  FIG. 4  after formation of a spacer. 
           [0013]      FIG. 6  illustrates an embodiment of the structure of  FIG. 5  after formation of the drain region. 
           [0014]      FIG. 7  illustrates an embodiment of a TFET with a nanowire source. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Embodiments of systems and methods for a TFET with a nanowire source are provided, with exemplary embodiments being discussed below in detail. The TFET source injection point may be located in a GAA nanowire, and the drain may be located in a planar single-gated region. This configuration suppresses ambipolar behavior in the TFET, thereby reducing the TFET off current. 
         [0016]      FIG. 1  illustrates an embodiment of a method of forming a TFET with a nanowire source.  FIG. 1  is discussed with reference to  FIGS. 2-7 . In block  101 , a SOI wafer  200  as shown in  FIG. 2  is used to form a structure  300  comprising a silicon nanowire  302  as shown in  FIG. 3 . SOI wafer  200  comprises silicon substrate  201  under buried oxide (BOX)  202  under silicon layer  203 . To form nanowire  302 , the locations of nanowire  302  and silicon pads  301 A-B are lithographically defined and etched in silicon layer  203 . After nanowire  302  and silicon pads  301 A-B are etched, a portion of BOX  202  is removed to form recess  303  under nanowire  302  and silicon pads  301 A-B. Recess  303  may be formed using a hydrofluoric (HF) acid dip in some embodiments. Nanowire  302  is located between silicon pads  301 A-B, may have a length between about 50 nanometers (nm) and about 200 nm in some embodiments, and may have a diameter between about 3 nm and about 50 nm in some embodiments. 
         [0017]    In block  102 , a gate comprising dielectric layer  401  and gate polysilicon  402  is formed around nanowire  302  and in recess  303 , as shown in  FIG. 4 . The gate has a GAA configuration. Dielectric layer  401  completely surrounds nanowire  302 . Dielectric layer  401  may comprise thermally grown oxide or a high-k material in some embodiments. The gate may optionally comprise a metal layer (not shown) located between dielectric layer  401  and gate polysilicon  402 . A hardmask layer  403 , which may comprise silicon nitride, is then formed over the gate polysilicon  402 . 
         [0018]    In block  103 , a spacer  501  is formed adjacent to the gate comprising dielectric layer  401  and gate polysilicon  402 , as shown in  FIG. 5 . Spacer  501  may comprise a nitride in some embodiments. 
         [0019]    In block  104 , a drain region  601  is formed in silicon pad  301 B by implantation of dopants, as shown in  FIG. 6 . Drain region  601  may be implanted with n-type dopants including but not limited to arsenic (As) or phosphorous (P). Implantation of drain region  601  may be followed by an anneal in some embodiments. Drain region  601  is located in a planar single-gated region 
         [0020]    In block  105 , silicon pad  301 A and a portion of nanowire  302  are implanted with dopants to form nanowire source  701  as shown in  FIG. 7 . Nanowire source  701  may be implanted with p-type dopants including but not limited to boron (B) or boron diflouride (BF 2 ). Implantation of nanowire source  701  is followed by an anneal. The resulting device comprises a TFET  700  with a nanowire source  701 . A portion of nanowire source  701  comprises a GAA configuration (i.e., a portion of nanowire source  701  is located inside the gate of TFET  700 ). The undoped portion of nanowire  302  comprises the channel of TFET  700 ; the channel also comprises a GAA configuration. TFET  700  may exhibit good electrostatic control of the nanowire channel  302  while having reduced ambipolar behavior due to the GAA portion of nanowire source  701 . In some embodiments, hardmask layer  403  may be removed after formation of nanowire source  701 , and a top portion of gate polysilicon  402  may be silicided to form a gate contact (not shown). 
         [0021]    The technical effects and benefits of exemplary embodiments include formation of a TFET with reduced off current. 
         [0022]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0023]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.