Abstract:
Active areas of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines on two sides and by conductors separated from the semiconductor substrate by electrically insulating layers on two other sides. The conductors are electrically biased during operation of the DRAM to cause portions of the semiconductor substrate therebelow to increase in majority carrier concentration and thus to inhibit inversion thereof. Each buried bit line is formed in a trench in the semiconductor substrate. Each trench houses a separate bit line and is lined with an electrical insulator and has a conductor in a bottom portion thereof.

Description:
FIELD OF THE INVENTION 
   The invention relates, generally, to semiconductor devices, and more particularly, to structures which define active areas of semiconductor substrates (bodies), particularly those useful for memory cells of dynamic random accesss memories (DRAMS) 
   BACKGROUND OF THE INVENTION 
   DRAMS and SRAMS are used extensively in computer memories. Each DRAM cell is composed of a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), and a capacitor. Static random access memories (SRAMS) are based on a larger cell comprised of several transistors and capacitors. 
   Circuit designers focus on methods of device layouts which can increase device density and circuit speed. As techniques and tools are developed to handle larger wafers for improved yield, several design strategies have emerged. 
   One of these strategies disclosed in prior art is that memory cells can be achieved with high integration by forming word lines that lie between the source and drain regions and capacitors which use one of the source and drain regions as a storage node electrode. Also, the bit lines are buried in the semiconductor substrate and are electrically connected to the source or drain regions. However, the active area containing the MOSFET arrays is defined by a combination of the isolation regions and buried bit lines troughs. Overlay errors between the isolation mask and the buried bit lines mask result in a variation in the width of the buried bit lines conductors which increases the likelihood that bit lines opens will occur. A more serious result is that the alignment tolerances between these mask levels create a leakage path between two adjacent capacitor contact diffusions. Yet another concern associated with this design is that overlay errors between a buried bit line and isolation masks results in a variation in the dimensions of the active areas containing the transistors. This variation in active area leads to variation in electrical characteristics and reduced process yield. These defects in the cell design can render it inoperable. 
   A second strategy disclosed in prior art relies on a layout in which bit lines are not recessed beneath the upper surface of the silicon. This forces a pattern of conductive segments which must be wired with separate word lines conductors. Therefore, word lines and bit lines compete for the same space which results in a loss of surface area and a decrease in the packing density. 
   To write in and to read out information stored as bits in individual cells it is necessary to form orthogonal arrays of word lines and bit lines. Word lines and bit lines are connected to the gate and drain, respectively, of the transistor of each memory cell. One popular type of capacitor used in DRAMS is the “stacked capacitor” which is fabricated over a top surface of a semiconductor substrate. The source of the transistor of each memory cell is connected to a capacitor storage node of a stacked capacitor. The output terminals, the drains and sources, of an n-channel field effect transistor reverse function as current flow through the transistor reverses. For example, during a write of a logical “1” into a memory cell having an n-channel transistor and a stored logical “0”, the output terminal of the transistor coupled to the bit line is the drain and the output terminal coupled to the capacitor is the source. During a read operation, with a “1” stored in the memory cell, the output terminal of the transistor coupled to the capacitor is the drain and the other output terminal coupled to the bit line is the source. 
   Stacked capacitors are popular because the capacitance can be increased as the overlapping area of the capacitor plates is increased., and the process complexity associated with deep trench processing is avoided. 
   Previous problems have been encountered when a via is used to make contact to a stacked capacitor. As a result of etching the via, the design line width of the bit lines can be effected. With design ground rules of &lt;0.25 um today and moving toward 0.10 um in the not too distant future, any process step which effects the line width will raise serious questions of device reliability and manufacturability. 
   Another problem occurs when processing sequences in the formation of the transistors lead to the need for a deep contact hole. This leads to an increase in the distance from the bit lines to the surface of the semiconductor body which can result in poor filing of a contact hole. Poor contact hole filing can cause reliability problems as result of and lead to contact failures. 
   It is desirable to reduce many of these problems and provide an efficient structure which defines active areas of a semiconductor substrate in which circuits and/or memory cells can be formed. 
   SUMMARY OF THE INVENTION 
   Viewed from a first aspect, the present invention is directed to apparatus comprising a semiconductor body having a top surface, a plurality of separated trenches, and a plurality of second conductors. The plurality of separated trenches extend from the top surface into the semiconductor body. Each of the trenches is lined with an insulating material and filled with a first conductor which is electrically isolated from the semiconductor body by the insulating material. The plurality of second conductors is separated from the top surface by an electrically insulating layer. The plurality of second conductors intersect the plurality of trenches with the intersection of the trenches and the second conductors defining areas of the semiconductor body in which devices can be formed. Each of the first conductors has a sufficient length so as to facilitate connections to at least two active areas. 
   Viewed from a second aspect, the present invention is directed to an integrated circuit formed in and/or a silicon body having a top surface. The integrated circuit comprises a plurality of parallel trenches and a plurality of second conductors. The plurality of parallel trenches extends from the top surface into the silicon body. Each of the trenches is lined with an insulating material and filled with a first conductor which is electrically isolated from the semiconductor body by the insulating material. The plurality of second conductors are separated from the top surface by an electrically insulating layer. The plurality of second conductors intersect the plurality of trenches with the intersection of said trenches and said conductors defining areas of the semiconductor body in which devices can be formed. Each of the first conductors has a sufficient length so as to facilitate connections to at least two active areas. 
   Viewed from a third aspect, the present invention is directed to a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns with each column being coupled to a bit line. The DRAM comprises a silicon body having a major surface, a plurality of separated trenches, and a plurality of separated second conductors which are separated from the top surface by an electrically insulating layer. The plurality of separated trenches extends from the major surface into the silicon body. Each of the trenches is lined with an insulating material and filled with a first conductor which is electrically isolated from the semiconductor body by the insulating material. The plurality of second conductors intersects the trenches with the intersection of the trenches and the second conductors defining a plurality of active areas of the semiconductor body in which memory cells can be formed. The active areas are adjacent each other and separated by the two of the trenches and by two of the second conductors. Each of the first conductors is of a sufficient length so as to facilitate an electrical connection to each of the active areas which contains memory cells of a given column of memory cells. 
   The invention will be better understood from the following more detailed description taken in conjunction with the accompanying drawings and claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1 ,  2 , and  3  show a schematic partially stripped away simplified top view (FIG.  1 ), a first cross-sectional view ( FIG. 2 ) taken through a dashed line  2 — 2  of  FIG. 1 , and a second cross-sectional view ( FIG. 3 ) taken through a dashed line  3 — 3  of  FIG. 1 , of a semiconductor structure in accordance with the present invention. 
     The drawings are not necessarily to scale. 
   

   DETAILED DESCRIPTION 
   Referring now to  FIGS. 1 ,  2 , and  3 , there are shown a schematic partially stripped away simplified top view (FIG.  1 ), a first cross-sectional view ( FIG. 2 ) taken through a dashed line  2 — 2  of  FIG. 1 , and a second cross-sectional view ( FIG. 3 ) taken through a dashed line  3 — 3  of  FIG. 1 , of a semiconductor structure  10  in accordance with the present invention. Semiconductor structure (apparatus, integrated circuit)  10  comprises a semiconductor body (substrate)  12  having a top surface  11  in which are formed a plurality of trenches  14  and a plurality of conductors  20  which crossover trenches  14  but which are electrically isolated therefrom by a dielectric layer  22  which is typically silicon dioxide. Each of trenches  14  is lined with an insulating layer  16  and is partly filled with a conductor  18 A. The trenches  14  and the conductors  20  cross each other to define a plurality of “active areas” in which electrical devices can be formed such as memory cells of a DRAM. A DRAM typically has a plurality of memory cells arranged in rows and columns with a bit line coupled to each column of memory cells and a word line coupled to each row of memory cells. Each of these active areas has a width of “X” and a length of “Y”. A variety of different types of semiconductor devices and/or circuits can be fabricated in each active area with different devices and/or circuits formed in various active areas. 
   The trenches  14  can be askew but separated from each other and the conductors  20  can also be askew and separated from each other. The active areas formed can be parallelograms, rectangular, square, trapezoidal, or comprise four sides. 
   Within one of the active areas there is shown within a first dashed line rectangle  24 A a first memory cell comprising a field effect transistor and a capacitor (both shown in electrical schematic form) and within a second dashed line rectangle  24 B is shown an essentially identical second memory cell which also comprises a field effect transistor and a capacitor. Drain regions of both transistors are shown coupled to a common node  23  with the source region of each transistor coupled to a terminal of the capacitor associated with that transistor. In an illustrative embodiment a single drain region  23 A (shown in  FIG. 3 ) is shared by both transistors. With the devices in an active area forming two memory cells, the common drains  23 , which are typically combined in a common drain region  23 A shown in  FIG. 3 , are coupled to conductor  18 a which serves as a bit line  1  (BL 1 ). For simplicity the drain region  23 A is shown next to an insulating layer  16  of a trench  14  which contains a conductor  18 A. Typically it would be located between the two memory cells occupying an active area. Three bit lines (BL 1 , BL 2 , and BL 3 ) of a plurality of bit lines are shown in  FIGS. 1 and 3 . The gates of the transistors are each coupled to a separate word line with word line WL 1  shown coupled to the gate of a transistors shown in dashed line rectangle  24 A and the gate of the transistor shown in dashed line rectangle  24 B coupled to a word line WL 2 . Each of the gates is typically a conductor separated from surface  11  by a gate dielectric layer (not shown). The gates associated with a given word line, which is a conductor that is typically doped polysilicon or a metal, are connected to that word line. 
     FIG. 3  shows that a portion of an opening above conductor  18 A is filled with an insulating layer  28 A and the remaining portion is filled with a conductor  32  which extends above the top surface  11  and thereacross to contact a common drain region  23 A (shown only in  FIG. 3 ) of the two transistors (shown schematically in FIG.  1 ). 
     FIG. 2  shows that each of the conductors  20  is separated from the surface  11  by and insulating layer  22 . Below each of the insulating layers  22  is shown a separate portion  12 A (within a dashed line rectangle) of substrate  12 . With an appropriate voltage applied to conductors  20 , the conductivity (majority carrier concentration) of the portions  12 A of substrate  12  is increased above that of the remainder of substrate  12 . This makes it more difficult to invert the conductivity of portions  12 A when transistors within an active area are biased on by inverting (changing from one conductivity type to the other, e.g., changing from p-type to n-type) a surface portion of substrate  12  to create a channel region of the same conductivity type between a drain and a source region of the same conductivity type. This type of electrical isolation is sometimes denoted as field plate isolation and the combination of conductors  20  and dielectric layers  22  may be denoted as field plates. 
   In an illustrative embodiment structure  10  is used as dynamic random access memory (DRAM) with each active area having formed therein a pair of memory cells (shown within separate dashed line rectangles  24 A and  24 B with the trenches  14  being parallel to each other and the conductors  20  being parallel to each other and orthogonal to the trenches  14 . 
   Various modifications are possible within the spirit and scope of the invention. For example, the opening in insulating layer  28  which is occupied by conductor  32  can be the full width of conductor  18 a or can be through a central portion of insulating layer  28  which could extend over the entire width of conductor  18 A. Further, a variety of electrical semiconductor compatible insulators other than those specifically denoted can be substituted for those denoted. Still further, the active areas can house a variety of circuity other than memory cells and the buried conductors  18 A can serve as power supply lines or interconnections between circuitry of different active areas. Still further, the buried conductors  18 A need not be connected to portions of each of the active areas. Furthermore, the conductors  18 A can be discontinuous so long as each length of conductor  18 A is at least long enough to interconnect circuitry in two active areas. Still further, the plurality of conductors separated from the top surface of the semicondcutor body by an electrically insulating layer can be formed at the same time as word lines, which have essentially the same configuration, and may be denoted as “dummy word lines”. Furthermore, a defined active area can contain just one memory cell or more than two memory cells.