Abstract:
An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.

Description:
This application is a divisional application claiming priority to Ser. No. 11/924,662, filed Oct. 26, 2007, now U.S. Pat. No. 7,935,408, issued May 3, 2011. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a substrate anchor structure and associated method for forming a substrate anchor structure. 
     BACKGROUND OF THE INVENTION 
     Connections between structures typically do not comprise any additional means of support and are therefore typically unreliable and subject to failure. Accordingly, there exists a need in the art to overcome at least one of the deficiencies and limitations described herein above. 
     SUMMARY OF THE INVENTION 
     The present invention provides an electrical structure comprising: 
     a first substrate; 
     a first dielectric layer formed over a top surface of said first substrate, wherein said first dielectric layer comprises a first opening extending from a top surface through a bottom surface of said first dielectric layer; 
     a first solder structure formed within said first opening and over a portion of said top surface of said first dielectric layer, wherein said first solder structure comprises a solder material, wherein said first solder structure is not electrically connected to said first substrate; 
     an underfill layer comprising a silica-epoxy composite adhesive material, wherein said underfill layer is formed over said top surface of said first dielectric layer and over said first solder structure; and 
     a second substrate formed over and in contact with said underfill layer, wherein said second substrate is not in contact with said first solder structure. 
     The present invention provides a method for forming an electrical structure comprising: 
     providing a first substrate and a second substrate; 
     forming a electrically conductive pad formed within said first substrate, wherein said electrically conductive pad comprises a metallic pad; 
     forming a passivation layer over and in direct mechanical contact with a top surface of said first substrate, wherein said passivation layer comprises a first independent layer formed over and in contact with said first substrate and said electrically conductive pad, a second independent layer formed over and in contact with said first independent layer, and a third independent layer formed over and in contact with said second independent layer; 
     forming a first dielectric layer over and in direct mechanical contact with a top surface of said passivation layer, wherein said first dielectric layer in combination with said passivation layer comprises a first opening extending from a top surface through a bottom surface of said first dielectric layer and completely through said first independent layer, said second independent layer, and said third independent layer of said passivation layer, and wherein said first dielectric layer in combination with said passivation layer comprises a second opening comprising a first portion extending from said top surface through said bottom surface of said first dielectric layer and a second portion extending completely through said first independent layer, said second independent layer, and said third independent layer of said passivation layer and over said electrically conductive pad; 
     forming a first metallic pad comprising a first section formed over said passivation layer and a second section formed within said second portion of said second opening and in direct mechanical contact with said electrically conductive pad; 
     forming a barrier layer comprising a first barrier layer formed over and in contact with said first metallic pad and a second barrier layer formed over and in contact with said first barrier layer; 
     forming a first solder interconnect formed over and in contact with said second barrier layer; 
     forming an underfill layer comprising a silica-epoxy composite adhesive material, wherein said underfill layer comprises a first underfill portion formed over said top surface of said first dielectric layer and a second underfill portion formed within an entire portion of said first opening, wherein a first portion of said dielectric layer is formed between said second underfill portion and said barrier layer, wherein said first portion of said dielectric layer is in direct mechanical contact with a bottom surface of said first barrier layer, a first surface of said electrically conductive pad, and a second surface of said electrically conductive pad, wherein said first surface of said electrically conductive pad is perpendicular to said second surface of said of said electrically conductive pad, wherein said second underfill portion is in direct mechanical contact with said first portion of said dielectric layer, a second portion of said dielectric layer, said first independent layer, said second independent layer, said third independent layer, and said first substrate, and wherein said first underfill portion is in direct mechanical contact with said first barrier layer, said second barrier layer, and said first solder interconnect; and a second substrate formed over and in contact with said underfill layer. 
     The present invention provides a method for forming an electrical structure comprising: 
     providing a first substrate and a second substrate; 
     forming a first dielectric layer over a top surface of said first substrate; 
     forming a first opening extending from a top surface through a bottom surface of said first dielectric layer; 
     forming a first solder structure within said first opening and over a portion of said top surface of said first dielectric layer, wherein said first solder structure comprises a solder material wherein said first solder structure is not electrically connected to said first substrate; 
     forming an underfill layer over said top surface of said first dielectric layer and over said first solder structure, wherein said underfill layer comprises a silica-epoxy composite adhesive material; and 
     placing said second substrate over and in contact with said underfill layer, wherein said second substrate is not in contact with said first solder structure. 
     The present invention advantageously provides a simple structure and associated method for proving additional means of support for connections between structures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a cross sectional view of an electrical structure, in accordance with embodiments of the present invention. 
         FIG. 2  depicts a first alternative to  FIG. 1 , in accordance with embodiments of the present invention. 
         FIG. 3  depicts a first alternative to  FIG. 2 , in accordance with embodiments of the present invention. 
         FIG. 4  illustrates a second alternative to  FIG. 1 , in accordance with embodiments of the present invention. 
         FIG. 5  illustrates a first alternative to  FIG. 4 , in accordance with embodiments of the present invention. 
         FIG. 6  illustrates a first alternative to  FIG. 5 , in accordance with embodiments of the present invention. 
         FIGS. 7A-7D  illustrate a process for generating the electrical structures of  FIGS. 1-3 , in accordance with embodiments of the present invention. 
         FIGS. 8A-8C  illustrate a process for generating the electrical structures of  FIGS. 4-6 , in accordance with embodiments of the present invention. 
         FIG. 9  illustrates a top view of the electrical structures of  FIGS. 1-6 , in accordance with embodiments of the present invention. 
         FIG. 10  illustrates an alternative top view of the electrical structures of  FIGS. 1-6 , in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  illustrates a cross sectional view of an electrical structure  2   a , in accordance with embodiments of the present invention. Electrical structure  2   a  comprises a substrate  1 , a substrate  4 , an electrical interconnection structure  19 , a dielectric layer  11 , layer and an underfill encapsulant layer  17 . Substrate  1  comprises an electrically conductive pad  12  and an optional hard passivation layer  6 . Passivation layer  6  comprises a plurality of optional layers  6   a  . . .  6   c . Layers  6   a  and  6   c  comprise silicon nitride. Layer  6   b  comprises silicon dioxide. Electrically conductive pad  12  may be connected to wires or electrical components within substrate  1 . Electrically conductive pad  12  may comprise any type of metallic material including, inter alia, copper. Substrate  4  comprises an electrically conductive pad  10 . Electrically conductive pad  12  may be connected to wires or electrical components within substrate  4 . Substrate  1  may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc. Substrate  4  may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc. Electrically conductive pad  10  may comprise any type of metallic material including, inter alia, copper, a chromium/copper combination, etc. Electrical interconnection structure  19  comprises a metallic pad  14 , an optional barrier layer metallurgy (BLM)  20 , and a solder structure  18 . Electrical interconnection structure  19  electrically and mechanically connects electrically conductive pad  10  to electrically conductive pad  12  thereby connecting substrate  4  to substrate  1 . Metallic pad  14  electrically and mechanically connects electrically conductive pad  12  to BLM  20 . BLM  20  electrically and mechanically connects metallic pad  14  to solder structure  18 . Solder structure  18  electrically and mechanically connects BLM  20  to electrically conductive pad  10 . Solder structure  18  may be a C4 solder ball. Solder structure  18  comprises solder. Solder is defined herein as a metal alloy comprising a low melting point (i.e., about 100 degrees Celsius to about 340 degrees Celsius) that is used to join metallic surfaces together without melting the metallic surfaces. Solder structure  18  may comprise any solder material suitable for flip chip interconnections including, inter alia, an alloy of tin such as SnCu, SnAgCu, SnPb, etc. BLM  20  may comprise, inter alia, a layer of chromium/copper  20   a  and a layer of titanium  20   b . Metallic pad  14  may comprise, inter alia, aluminum. Dielectric layer  11  may comprise, inter alia, a polyimide layer. Underfill encapsulant layer  17  surrounds solder structure  18  and is in contact with substrate  4 . Underfill encapsulant layer  17  may comprise a material such as, inter alia, a highly filled silica-epoxy composite adhesive, a lightly filled silica-epoxy composite adhesive, etc. Underfill encapsulant layer  17  may comprise a coefficient of thermal expansion selected from a range of about 5-40 ppm/C. Underfill encapsulant layer  17  may additionally comprise a filler material dispersed throughout. Underfill encapsulant layer  17 . Underfill encapsulant layer  17  comprises an anchor portion  17   a . Anchor portion  17   a  is formed within an opening (see opening  21   b  in  FIG. 7A ) in dielectric layer  11  and optionally within passivation layer  6 . The opening may comprise a single via (e.g., a through hole via) as illustrated by vias  17   x  in  FIG. 9  or a trench as illustrated by trench  17   y  or  17   z  in  FIG. 10 . Underfill encapsulant layer  17  and anchor portion  17   a  (i.e., in combination) are used to provide support for reducing stresses on solder structure  18 . Stresses on solder structure  18  may be caused by thermal cycling of electrical structure  2   a.    
       FIG. 2  depicts a first alternative to  FIG. 1  illustrating a cross-sectional view of an electrical structure  2   b , in accordance with embodiments of the present invention. In contrast with electrical structure  2   a  of  FIG. 1 , electrical structure  2   b  of  FIG. 2  comprises an extra portion  17   b  of anchor portion  17   a . Extra portion  17   b  is formed within an opening in substrate  1 . The opening may comprise a single via or a trench. Underfill encapsulant layer  17 , anchor portion  17   a , and extra portion  17   b  (i.e., in combination) are used to provide extra support for reducing stresses on solder structure  18 . 
       FIG. 3  depicts a first alternative to  FIG. 2  illustrating a cross-sectional view of an electrical structure  2   c , in accordance with embodiments of the present invention. In contrast with electrical structure  2   b  of  FIG. 2 , electrical structure  2   c  of  FIG. 3  comprises lateral portion  17   c  attached to extra portion  17   b . Lateral portion  17   c  extends laterally from extra portion  17   b  in directions D 1  and D 2  such that lateral portion  17   c  is formed below a top surface  1   a  of substrate  1 . Note that lateral portion  17   c  may extend in any direction below top surface  1   a  of substrate  1 . Underfill encapsulant layer  17 , anchor portion  17   a , extra portion  17   b , and lateral portion  17   c  (i.e., in combination) are used to provide extra support for reducing stresses on solder structure  18 . 
       FIG. 4  illustrates a cross sectional view of an electrical structure  2   d , in accordance with embodiments of the present invention. Electrical structure  2   d  comprises a substrate  1 , a substrate  4 , an electrical interconnection structure  19 , a dielectric layer  11 , a solder anchor structure  28 , and an underfill encapsulant layer  17 . Substrate  1  comprises an electrically conductive pad  12  and an optional hard passivation layer  6 . Passivation layer  6  comprises a plurality of optional layers  6   a  . . .  6   c . Layers  6   a  and  6   c  comprise silicon nitride. Layer  6   b  comprises silicon dioxide. Electrically conductive pad  12  may be connected to wires or electrical components within substrate  1 . Electrically conductive pad  12  may comprise any type of metallic material including, inter alia, copper. Substrate  4  comprises an electrically conductive pad  10 . Electrically conductive pad  12  may be connected to wires or electrical components within substrate  4 . Substrate  1  may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc. Substrate  4  may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc. Electrically conductive pad  10  may comprise any type of metallic material including, inter alia, copper, a chromium/copper combination, etc. Electrical interconnection structure  19  comprises a metallic pad  14 , an optional barrier layer metallurgy (BLM)  20 , and a solder structure  18 . Electrical interconnection structure  19  electrically and mechanically connects electrically conductive pad  10  to electrically conductive pad  12  thereby connecting substrate  4  to substrate  1 . Metallic pad  14  electrically and mechanically connects electrically conductive pad  12  to BLM  20 . BLM  20  electrically and mechanically connects metallic pad  14  to solder structure  18 . Solder structure  18  electrically and mechanically connects BLM  20  to electrically conductive pad  10 . Solder structure  18  may be a C4 solder ball. Solder structure  18  comprises solder. Solder is defined herein as a metal alloy comprising a low melting point (i.e., about 100 degrees Celsius to about 340 degrees Celsius) that is used to join metallic surfaces together without melting the metallic surfaces. Solder structure  18  may comprise any solder material suitable for flip chip interconnections including, inter alia, an alloy of tin such as SnCu, SnAgCu, SnPb, etc. BLM  20  may comprise, inter alia, a layer of chromium/copper  20   a  and a layer of titanium  20   b . Metallic pad  14  may comprise, inter alia, aluminum. Dielectric layer  11  may comprise, inter alia, a polyimide layer. Underfill encapsulant layer  17  surrounds solder structure  18  and solder anchor structure  28  and is in contact with substrate  4 . Underfill encapsulant layer  17  may comprise, inter alia, a highly filled silica-epoxy composite adhesive, a lightly filled silica-epoxy composite adhesive, etc. Underfill encapsulant layer  17  may comprise a coefficient of thermal expansion selected from a range of about 5-40 ppm/C. Underfill encapsulant layer  17  may additionally comprise a filler material dispersed throughout. Underfill encapsulant layer  17 . Solder anchor structure  28  is formed within an opening (see opening  21   b  in  FIG. 7A ) in dielectric layer  11  and optionally within passivation layer  6 . The opening may comprise a single via (e.g., a through hole via) as illustrated by vias  17   x  in  FIG. 9  or a trench as illustrated by trench  17   y  or  17   z  in  FIG. 10 . BLM  20  may optionally be located between solder anchor structure  28  and the opening. Solder anchor structure  28  is not in contact with substrate  4  (i.e., as illustrated in  FIG. 4 ). Alternatively, solder anchor structure  28  may be in contact with substrate  4  (i.e., not shown). Solder anchor structure  28  is not in electrical contact with any electrical components (e.g., transistors resistors, capacitors, wires, etc) in substrate  4  or substrate  1 . Solder anchor structure  28  may comprise any solder material including, inter alia, an alloy of tin such as SnCu, SnAgCu, SnPb, etc. Underfill encapsulant layer  17  and solder anchor structure  28  (i.e., in combination) are used to provide support for reducing stresses on solder structure  18 . Stresses on solder structure  18  may be caused by thermal cycling of electrical structure  2   a.    
       FIG. 5  depicts a first alternative to  FIG. 4  illustrating a cross-sectional view of an electrical structure  2   e , in accordance with embodiments of the present invention. In contrast with electrical structure  2   d  of  FIG. 4 , electrical structure  2   e  of  FIG. 5  comprises an extra portion  28   a  of solder anchor structure  28 . Extra portion  28   a  is formed within an opening in substrate  1 . The opening may comprise a single via or a trench. Underfill encapsulant layer  17 , solder anchor structure  28 , and extra portion  28   a  (i.e., in combination) are used to provide extra support for reducing stresses on solder structure  18 . 
       FIG. 6  depicts a first alternative to  FIG. 5  illustrating a cross-sectional view of an electrical structure  2   f , in accordance with embodiments of the present invention. In contrast with electrical structure  2   e  of  FIG. 5 , electrical structure  2   f  of  FIG. 6  comprises lateral portion  28   b  attached to extra portion  28   a . Lateral portion  28   b  extends laterally from extra portion  28   a  in directions D 1  and D 2  such that lateral portion  28   b  is formed below a top surface  1   a  of substrate  1 . Note that lateral portion  28   b  may extend in any direction below top surface  1   a  of substrate  1 . Underfill encapsulant layer  17 , solder anchor structure  28 , and extra portion  28   a  and lateral portion  28   b  (i.e., in combination) are used to provide extra support for reducing stresses on solder structure  18 . 
       FIGS. 7A-7D  illustrate a process for generating electrical structures  2   a - 2   c  of  FIGS. 1-3 , in accordance with embodiments of the present invention. 
       FIG. 7A  illustrates a cross sectional view of a formation of openings  21   a  and  21   b , in accordance with embodiments of the present invention. Metallic pad  14  is formed by metal deposition, lithography, and a resistive ion etch (RIE) process. Dielectric layer  11  may be formed by a spin-on baking process. Openings  21   a  and  21   b  may be formed by an exposing, developing, and curing process. An RIE process may be used to etch through passivation layer  6 . 
       FIG. 7B  illustrates a cross sectional view of a formation of solder structure  18   a , in accordance with embodiments of the present invention. BLM  20  may be formed by using a sputter deposition process. BLM  20  may comprise a thickness of about 0.5 um. Resist layer  30  is applied and on opening in resist layer  30  is formed for solder structure  18   a . Solder structure  18   a  is formed by an electroplating process. 
       FIG. 7C  illustrates a cross sectional view of the structure illustrated in  FIG. 7B  after resist layer  30  has been stripped away and opening  21   b  has been formed, in accordance with embodiments of the present invention. 
       FIG. 7D  illustrates a cross sectional view of the structure illustrated in  FIG. 7C  after solder structure  18  has been formed by reflowing solder structure  18   a , in accordance with embodiments of the present invention. In order to generate structures  2   a - 2   c  of  FIGS. 1-3  from the structure illustrated in  FIG. 7D : 
     1. Substrate  4  is connected to solder structure  18 . 
     2. Underfill encapsulant layer  17  is dispensed. 
       FIGS. 8A-8C  illustrate a process for generating electrical structures  2   d - 2   f  of  FIGS. 4-6 , in accordance with embodiments of the present invention. 
       FIG. 8A  illustrates a cross sectional view of a formation of openings  21   a  and  21   b , in accordance with embodiments of the present invention. Metallic pad  14  is formed by metal deposition, lithography, and a resistive ion etch (RIE) process. Dielectric layer  11  may be formed by a spin-on baking process. Openings  21   a  and  21   b  may be formed by an exposing, developing, and curing process. An RIE process may be used to etch through passivation layer  6 . 
       FIG. 8B  illustrates a cross sectional view of a formation of solder structure  18   a  and solder structure  28   c , in accordance with embodiments of the present invention. BLM  20  may be formed by using a sputter deposition process. BLM  20  may comprise a thickness of about 0.5 um. Resist layer  30  is applied and on opening in resist layer  30  is formed for solder structure  18   a  and solder structure  28   a . Solder structure  18   a  and solder structure  28   c  is formed by an electroplating process. 
       FIG. 8C  illustrates a cross sectional view of the structure illustrated in  FIG. 8B  after solder structure  18  has been formed by reflowing solder structure  18   a  and solder structure  28  has been formed by reflowing solder structure  28   c , in accordance with embodiments of the present invention. In order to generate structures  2   d - 2   f  of  FIGS. 4-6  from the structure illustrated in  FIG. 8B : 
     1. Substrate  4  is connected to solder structure  18 . 
     2. Underfill encapsulant layer  17  is dispensed. 
       FIG. 9  illustrates a top view of electrical structures  2   a - 2   f  of  FIGS. 1-6 , in accordance with embodiments of the present invention. Structures  17   x  illustrate either anchor portion  17   a  of underfill encapsulant layer  17  or extra portion  28   a  of solder anchor structure  28 . Structures  17   x  are formed within vias. 
       FIG. 10  illustrates an alternative top view of electrical structures  2   a - 2   f  of  FIGS. 1-6 , in accordance with embodiments of the present invention. Structures  17   y  illustrate either anchor portion  17   a  of underfill encapsulant layer  17  or extra portion  28   a  of solder anchor structure  28 . Structures  17   y  are formed within trenches. 
     While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.