Abstract:
A capacitive sensor includes a switching capacitor circuit, a comparator, and a charge dissipation circuit. The switching capacitor circuit reciprocally couples a sensing capacitor in series with a modulation capacitor during a first switching phase and discharges the sensing capacitor during a second switching phase. The comparator is coupled to compare a voltage potential on the modulation capacitor to a reference and to generate a modulation signal in response. The charge dissipation circuit is coupled to the modulation capacitor to selectively discharge the modulation capacitor in response to the modulation signal.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 60/947,865, filed on Jul. 3, 2007, the contents of which are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to electronic circuits, and in particular but not exclusively, relates to capacitance sensing circuits. 
     BACKGROUND INFORMATION 
     Capacitance sensors are used to implement a variety of useful functions including touch sensors (e.g., touch pad, touch dial, touch wheel, etc.), determining the presence of an object, accelerometers, and other functions. In general, capacitive sensors are intended to replace mechanical buttons, knobs, and other similar mechanical user interface controls. A capacitive sensor permits eliminating complicated mechanical switches and buttons, providing reliable operation under harsh conditions. Capacitive sensors are widely used in the modern consumer applications, providing new user interface options in the exiting products (cell phones, digital music players, personal digital assistances, etc.). 
     One class of capacitive sensor uses a charge transfer technique. Referring to  FIG. 1 , the charge transfer technique charges a sensing capacitor Cx in one phase (switch SW 1  closed, switch SW 2  open) and discharges the sensing capacitor Cx into a summing capacitor Csum in a second phase (SW 1  open, SW 2  closed). Switches SW 1  and SW 2  are operated in a non-overlapping manner repeating the transfer of charge from Cx to Csum. 
     Capacitance sensor  100  is operated to measure the capacitance of Cx in the following manner. In an initial stage, Csum is reset by discharging Csum by temporarily closing switch SW 3 . Then, switches SW 1  and SW 2  commence operating in the two non-overlapping phases that charge Cx and transfer the charge from Cx into Csum. The voltage potential on Csum rises with each charge transfer phase, as illustrated in  FIG. 1B . The voltage on Csum can by calculated according to equation 1. 
                     V     C   ⁢           ⁢   sum       =       V   dd     ⁡     (     1   -     ⅇ       -   N     ⁢       C   ⁢           ⁢   x       C   ⁢           ⁢   sum             )               (     Equation   ⁢           ⁢   1     )               
where V Csum  represents the voltage on Csum, N represents the cycle count, Cx and Csum represent capacitance values, and Vdd represents a power supply voltage. Accordingly, the capacitance of Cx can be determined by measuring the number of cycles (or time) required to raise Csum to a predetermined voltage potential.
 
     The charge transfer method is advantageous due to its relative low sensitivity to RF fields and RF noise. This relative noise immunity stems from the fact that the sensing capacitor Cx is typically charged by a low-impedance source and the charge is transferred to a low-impedance accumulator (i.e., the summing capacitor Csum). However, conventional capacitance sensors have the disadvantage that that voltage on the summing capacitor Csum rises versus time/cycles in an exponential manner (see  FIG. 1B  and Equation 1). The exponential relationship between the accumulated voltage potential on Csum and the charge transfer time/cycles requires some linearization if the capacitance of Cx is calculated as a function of the voltage potential on Csum after a predetermined time or number of cycles. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
         FIG. 1A  is a circuit diagram illustrating a conventional capacitance sensor circuit. 
         FIG. 1B  is a graph illustrating the exponential relationship between voltage on a summing capacitor and charge transfer cycles. 
         FIG. 2  is circuit diagram of a capacitive sensor with a sigma-delta modulator, in accordance with an embodiment of the invention. 
         FIG. 3  is a diagram illustrating operation of a capacitive field sensor, in accordance with an embodiment of the invention. 
         FIG. 4A  is a timing diagram illustrating non-overlapping clock signals, in accordance with an embodiment of the invention. 
         FIG. 4B  includes two phase diagrams illustrating operation of a switching capacitor circuit, in accordance with an embodiment of the invention. 
         FIG. 5  is a flow chart illustrating operation of a capacitive sensor with a sigma-delta modulator, in accordance with an embodiment of the invention. 
         FIG. 6  is circuit diagram of a capacitive sensor with a sigma-delta modulator, in accordance with an embodiment of the invention. 
         FIG. 7  is a circuit diagram illustrating pin-out connections for implementing a single field sensor interface, in accordance with an embodiment of the invention. 
         FIG. 8  is a circuit diagram illustrating pin-out connections for implementing a multi-field sensor interface time sharing a single sigma-delta modulator, in accordance with an embodiment of the invention. 
         FIG. 9  is a functional block diagram illustrating a demonstrative processing system for implementing a capacitive sense user interface, in accordance with an embodiment of the invention. 
         FIGS. 10A-C  are circuit diagrams illustrating alternative dissipation circuit implementations within a sigma-delta modulator, in accordance with embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of an apparatus and method for a capacitive sensor with a sigma-delta modulator are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. 
     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. 
       FIG. 2  is a circuit diagram illustrating a capacitive sensor  200 , in accordance with an embodiment of the invention. Capacitive sensor  200  is capable of converting the measurement of the capacitance of sensing capacitor (Cx) into the measurement of the duty cycle of a feedback pulse signal (FB_SIG). Furthermore, the relationship between the duty cycle of FB_SIG and the capacitance of Cx is substantially linear. Capacitive sensor  200  may also be regarded as a switching capacitor current to duty cycle converter. 
     The illustrated embodiment of capacitance sensor  200  includes a switching capacitor circuit  205 , sigma-delta modulator  210 , a measurement circuit  215 , logic  217 , and a control circuit  220 . The illustrated embodiment of switching capacitor circuit  205  includes sensing capacitor (Cx), switches SW 1 , SW 2 , and SW 3 , a diode D 1 , and a modulation capacitor (Cmod). The illustrated embodiment of sigma-delta modulator  210  includes a comparator (CMP)  225 , a latch  230 , a clock source  235 , a discharge resistor (Rd), and a discharge switch SW 4 . Collectively, the discharge resistor Rd and discharge switch SW 4  may be referred to as a charge dissipation circuit  227 . While component values of switching capacitor circuit  205  and sigma-delta modulator  210  may vary based on the particular application, in general, the capacitance of Cmod will be substantially larger than the capacitance of Cx. Since Cmod acts to accumulate charge transferred from Cx over multiple cycles, it is often referred to as a summing capacitor or an integrating capacitor. In one embodiment, comparator  225  is an analog voltage comparator. 
       FIG. 3  is a diagram illustrating operation of a capacitive field sensor  300 , in accordance with an embodiment of the invention. Capacitive field sensor  300  may be used to implement a user interface of an electronic device. Capacitive field sensor  300  is one possible physical implementation of sense capacitor Cx. The illustrated embodiment of capacitive field sensor  300  is made of two interlocking combs  305  and  310  on a printed circuit board (PCB) substrate. Each comb has a capacitance represented as C A  while the finger has a variable capacitance represented as C F . The sense capacitance Cx represents the capacitance divider circuit  315  formed when the finger is brought into proximity with capacitive field sensor  300 . 
     During a finger touch event, part of the electric field is shunted to ground. From a simplified equivalent schematic point of view, this can be illustrated as adding the finger capacitance C F , forming the capacitive voltage divider circuit  315 . The finger capacitance changes the transmission coefficient of capacitance divider circuit  315 . It is this overall change in capacitance that is sensed by capacitive sensor  200  and converted into a measurement of the duty cycle of a signal FB_SIG output from latch  230  and measured by measurement circuit  215 . In one embodiment, logic  217  includes hardware and/or software logic for deciding when a significant change in the duty cycle of FB_SIG should be recognized as a valid finger interaction with capacitive field sensor  300 . 
       FIGS. 4A and 4B  illustrate the two non-overlapping phase operation of switching capacitor circuit  205 , in accordance with an embodiment of the invention. In one embodiment, during operation of capacitive sensor  200 , two configuration phases of switching capacitor circuit  205  are cycled through to perform capacitive sensing. The two phases include: a series charging phase (control signal Phi 1  asserted) and a discharge phase (control signal Phi 2  asserted). 
     In one embodiment, control signals Phi 1  and Phi 2  (see  FIG. 2 ) are generated by control circuit  220  based on a single clock signal CLK. As illustrated in  FIG. 4A , Phi 1  and Phi 2  are generated as non-overlapping pulse signals sufficiently spaced to prevent cross conduction or latch up between SW 1 , SW 2 , and SW 3 . As illustrated in  FIG. 4B , during the series charging phase (Phi 1 =‘1’; Phi 2 =‘0’), Phi 1  close circuits SW 1  and open circuits SW 2  and SW 3 . This configuration couples sensing capacitor Cx in series with modulation capacitor Cmod. A charging current Icharge flows from the power source Vdd to ground through Cx, D 1 , and Cmod causing Cx and Cmod to charge. During the charging phase, diode D 1  conducts Icharge in a forward biased operating regime. 
     During the discharging phase (Phi 2 =‘1’; Phi 1 =‘0’), Phi 1  open circuits SW 1  and close circuits SW 2  and SW 3 . This configuration disconnects the power source Vdd, while coupling both terminals of sensing capacitor Cx to ground to discharge the sensing capacitor. This configuration also reverse biases diode D 1 , which prevents Cmod from discharging. Accordingly, the voltage Umod at node N 1  is held during the discharging phase. When a finger is moved in proximity to field sensor  300 , the variable capacitance of Cx is increased causing less charge to be passed to Cmod during each series charging phase. The greater charge captured by Cx during the charging phase is discharged to ground during the discharge phase. Therefore, the larger Cx, the greater the number of switching cycles of SW 1 , SW 2 , and SW 3  to charge Cmod to a given voltage. 
     During operation, the charge on Cmod accumulates via the technique described above until the voltage Umod at node N 1  reaches Vref. At this point, the output MOD_SIG from CMP  225  toggles, which is latched and fed back to control switch SW 4  as feedback signal FB_SIG. FB_SIG causes switch SW 4  to close circuit. Discharge circuit  227  discharges Cmod through Rd until Umod drops below Vref, causing MOD_SIG to toggle once again. Latch  230  introduces a small delay into the feedback path prior to open circuiting SW 4 . This latch delay is controlled by clock source  235 . Once SW 4  is open circuited, the switching of SW 1 , SW 2 , and SW 3  recharges Cmod once again. The voltage Umod continuously dithers back and forth about Vref generating a square wave at the output latch  230 . This square wave is analyzed by measurement circuit  215  to determine the duty cycle or percentage of time FB_SIG is high versus low. This percentage averaged over time is representative of the capacitance or capacitance change of sensing capacitor Cx. 
       FIGS. 10A-C  are circuit diagrams illustrating alternative implementations of charge dissipation circuit  227  within a sigma-delta modulator, in accordance with embodiments of the invention.  FIG. 10A  illustrates a sigma-delta modulator  211  having a charge dissipation circuit  228 , which replaces SW 4  and discharge resistor Rd of charge dissipation circuit  227  with a current source I D  controlled by feedback pulse signal FB_SIG. When FB_SIG is a logic HIGH, the current source sinks a current I D  from modulation capacitor Cmod to ground. When FB_SIG is logic LOW, the current source is disabled. 
       FIG. 10B  illustrates a sigma-delta modulator  212  having a charge dissipation circuit  229  including a switching capacitor resistor circuit with a gated clock source. When FB_SIG is logic HIGH, the clock signal CLK is applied to the switches SW 5  and SW 6  with non-overlapping pulses (e.g., such as clock signals Phi 1  and Phi 2  generated by control circuit  220 ), causing a discharging current to flow to ground from modulation capacitor Cmod. At a logic LOW value for FB_SIG, the clock signal CLK is gated and switching capacitor circuit including Ccomp does not sink current from modulator capacitor Cmod. 
       FIG. 10C  illustrates a sigma-delta modulator  213  having a charge dissipation circuit  231  where the non-overlapping clock phases Phi 1  and Phi 2  are applied constantly to switches SW 5  and SW 6 , but SW 5  and SW 6  are selectively connected in series between Umod and either Vref or ground by the multiplexor MUX, depending on the value of the feedback pulse signal FB_SIG. The principle of operation of charge dissipation circuit  231  is similar to charge dissipation circuit  229  in that SW 5 , SW 6 , and Ccomp operate as a switching capacitor resistor circuit. 
       FIG. 5  is a flow chart illustrating operation of a capacitive sensor  200  in further detail, in accordance with an embodiment of the invention. The order in which some or all of the process blocks appear in process  500  should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated, or even in parallel. 
     In a process block  505 , capacitance sensor  200  is powered on and the output of CMP  210  (MOD_SIG) is initially low, assuming Cmod is initially discharged and the voltage Umod is less than Vref. In this state, MOD_SIG is logic “LOW”. On the next rising clock edge output from clock source  235 , latch  230  latches the value of MOD_SIG to its output. This output is fed back to the control terminal of switch SW 4  as feedback signal FB_SIG. A logic LOW open circuits SW 4  decoupling node N 1  from ground (process block  510 ) and permitting Cmod to accumulate charge. 
     With power provided to switching capacitor circuit  205 , switches SW 1 , SW 2 , and SW 3  commence operation (process block  515 ). Switches SW 1 , SW 2 , and SW 3  switch under control of a control signals Phi 1  and Phi 2  generated by control circuit  220 , as discussed above. As switching capacitor circuit  205  begins charging Cmod, the voltage potential Umod at node N 1  begins to rise gradually. Cmod continues to accumulate charge until Umod reaches Vref, as determined by CMP  225  (decision block  520 ). When Umod reaches or passes Vref, CMP  225  toggles its output (MOD_SIG) to a logic “HIGH” (process block  525 ). 
     In a process block  530 , latch  230  latches the value of MOD_SIG to its output as FB_SIG. Latching is synchronized to a clock signal output by clock source  235 . FB_SIG is fed back to discharge switch SW 4 . The toggled value is a logic HIGH, which close circuits discharging switch SW 4  and commences discharge of Cmod through Rd (process block  535 ). Cmod is discharged until Umod drops back below Vref, as determined by CMP  225  (decision block  540 ), at which point CMP  225  toggles MOD_SIG (process block  545 ). Discharge switch SW 4  is once again open circuited after MOD_SIG is latched and process  500  repeats from process block  510 . 
     After an initial transitory startup phase, capacitance sensor  200  enters its steady state phase where the voltage potential Umod on Cmod oscillates or dithers about Vref. This oscillation about Vref creates the modulation signal MOD_SIG upon which the feedback pulse signal FB_SIG is based. Once operating in the steady state phase, the duty cycle of the FB_SIG is directly proportional to the capacitance or capacitance change of Cx. 
     Accordingly, in a process block  550 , the duty cycle of FB_SIG is measured by measurement circuit  215 . In one embodiment, measurement circuit  215  may include a clock gated by FB_SIG and a counter to count a number of clock cycles occurring while FB_SIG is HIGH for a given period of time. Furthermore, there can be other methods to extract the multi-bit digital values from the bit stream data output by the sigma-delta modulator, such as various types of the digital filters or otherwise. Finally, in a process block  555 , the measured duty cycle is used to determine the capacitance Cx or capacitance change ΔCx of the sensing capacitor. Logic  217  may use this digital code to determine whether a user finger has interacted with a capacitive field sensor within a user interface. In one embodiment, measurement circuit  215  may output a digital code indicative of the capacitance or capacitance change of Cx. In one embodiment, capacitive sensor  200  operates as a Cmod charge current (i.e., Icharge in  FIG. 4B ) to digital code converter. Of course, the charge current of Cmod is related to the variable capacitance of the field sensor Cx. 
       FIG. 6  is a circuit diagram of a capacitive sensor  600  including a sigma-delta modulator, in accordance with an embodiment of the invention. Capacitive sensor  600  is an alternative embodiment to capacitive sensor  200 , but operates using the same principles. The illustrated embodiment of capacitive sensor  600  includes a switching capacitor circuit  605 , a sigma-delta modulator  210 , measurement circuit  215 , and a clock source  620 . The illustrated embodiment of switching capacitor circuit  605  includes sensing capacitor Cx, a filter resistor Rfilt, diode D 1 , modulation capacitor Cmod, a discharge switch SW 5 , and an inverter INV 1 . In one embodiment, clock source  620  is a pseudo-random signal (PRS) generator for generating a pseudo-random pulse signal. Other signal generators maybe used, such as a pulse width modulator; however, a PRS generator provides greater electromagnetic noise immunity. Additionally, other frequency spreading techniques can also be used to implement clock source  620 , such as frequency sweeping, frequency hopping, changing frequency in the pseudo random order, etc. 
     Sigma-delta modulator  210  and measurement circuit  215  operate as discussed above in connection with capacitive sensor  200 . Similarly, switching capacitor circuit  605  operates to sequentially charge Cmod, just as switching capacitor circuit  205 , with a slight variation on its specific implementation. When clock source  620  outputs a logic HIGH, diode D 1  is forward biased and switch SW 5  is open circuited. The open circuited SW 5  connects Cmod in series with Cx and clock source  620 . The forward biased D 1  permits a charging current to flow through sensing capacitor Cx and filter resistor Rfilt into modulation capacitor Cmod. While clock source  620  is logic HIGH, switching capacitor circuit  605  is in the “charging phase.” 
     When clock source  620  transitions to a logic LOW, switch SW 5  is closed circuited. The closed circuited SW 5  connects node N 2  to ground. This couples sensing capacitor Cx to ground through Rfilt and reverse biases diode D 1 . With Cx coupled to ground it discharges, while the reversed biased diode D 1  prevents discharge from modulation capacitor Cmod and Cmod retains its voltage Umod. While clock source  620  is logic LOW, switching capacitor circuit  605  is in the “discharge phase.” 
     During the discharge phase, filter resistor Rfilt and switch SW 5  coupled to ground creates a high frequency cutoff low pass filter (LPF). This LPF increases noise immunity to high frequencies. The LPF prevents high amplitude, ultra high frequency noise from erroneously flipping the bias state of diode D 1  and causing false triggering. 
       FIG. 7  is a circuit diagram illustrating pin-out connections for implementing a single field sensor interface  700  within an integrated circuit, in accordance with an embodiment of the invention. Integrated circuit (“IC”)  705  includes sigma-delta modulator  210 , clock source  620 , inverter INV 1 , and switch SW 5  integrated on a single die. The following components including: sensing capacitor Cx, filter resistor Rfilt, discharge resistor Rd, modulation capacitor Cmod, and diode D 1  are externally coupled to IC  705 . In one embodiment, inverter INV 1  may be implemented in software or firmware using a look up table (“LUT”). 
       FIG. 8  is a circuit diagram illustrating pin-out connections for implementing a multi field sensor interface  800  within an integrated circuit, in accordance with an embodiment of the invention. IC  805  couples multiple field sensors Cx 1  and Cx 2  to a single general purpose input/output (“GPIO”) pin  810 . Field sensors Cx 1  and Cx 2  time share a single GPIO  810 , clock source  620 , and sigma-delta modulator  210 . However, each externally coupled sensor includes its own externally coupled filter resistor (e.g., Rfilt 1 , Rfilt 2 ) and its own internal switch SW 5  (e.g., SW 5 A, SW 5 B). Each field sensor Cx 1  or Cx 2  is scanned one at a time via appropriate switching of the select switches SEL 1  and SEL 2 . Select switches SEL 1  and SEL 2  either activate the control terminals of switches SW 5 A and SW 5 B thereby grounding the corresponding field sensors Cx 1  or Cx 2 , or connect the control terminal to the output of inverter INV 1 . Although  FIG. 8  illustrates just two field sensors Cx 1  and Cx 2 , it should be appreciated that a large number of field sensors can thus timeshare GPIO pin  810 . 
       FIG. 9  is a functional block diagram illustrating a demonstrative system  1100  for implementing a capacitive sense user interface, in accordance with an embodiment of the invention. The illustrated embodiment of system  1100  includes a processing device  1110 , a capacitive sense pad  1120 , a capacitive sense linear slider  1130 , a capacitive sense radial slider  1140 , a host processor  1150 , an embedded controller  1160 , and non-capacitance sensor elements  1170 . Processing device  1110  may include analog and/or digital general purpose input/output (“GPIO”) ports  1107 . GPIO ports  1107  may be programmable. GPIO ports  1107  may be coupled to a Programmable Interconnect and Logic (“PIL”), which acts as an interconnect between GPIO ports  1107  and a digital block array of processing device  1110  (not illustrated). The digital block array may be configured to implement a variety of digital logic circuits (e.g., DAC, digital filters, digital control systems, etc.) using, in one embodiment, configurable user modules (“UMs”). The digital block array may be coupled to a system bus. Processing device  1110  may also include memory, such as random access memory (RAM)  1105  and program flash  1104 . RAM  1105  may be static RAM (“SRAM”), and program flash  1104  may be a non-volatile storage, which may be used to store firmware. Processing device  1110  may also include a memory controller unit (“MCU”)  1103  coupled to memory and the processing core  1102 . 
     Processing device  1110  may also include an analog block array (not illustrated). The analog block array is also coupled to the system bus. The analog block array also may be configured to implement a variety of analog circuits (e.g., ADC, analog filters, etc.) using, in one embodiment, configurable UMs. The analog block array may also be coupled to the GPIO  1107 . 
     As illustrated, capacitance sensor  1101 , which includes an implementation of capacitance sensor  200 ,  600 ,  700 , or  800  may be integrated into processing device  1110 . Capacitance sensor  1101  may include analog I/O for coupling to an external component, such as capacitive sense pad  1120 , capacitive sense linear slider  1130 , capacitive sense radial slider  1140 , and/or other capacitive sense devices. Capacitive sense pad  1120 , capacitive sense linear slider  1130 , and/or capacitive sense radial slider  1140  may each include one or more sensing capacitors Cx to implement the individual capacitive sense buttons therein. 
     Processing device  1110  may include internal oscillator/clocks  1106  and communication block  1108 . The oscillator/clocks block  1106  provides clock signals to one or more of the components of processing device  1110 . Communication block  1108  may be used to communicate with an external component, such as a host processor  1150 , via host interface (I/F) line  1151 . Alternatively, processing device  1110  may also be coupled to embedded controller  1160  to communicate with the external components, such as host  1150 . Interfacing to the host  1150  can be through various methods. In one exemplary embodiment, interfacing with the host  1150  may be done using a standard PS/2 interface to connect to embedded controller  1160 , which in turn sends data to the host  1150  via low pin count (LPC) interface. In some instances, it may be beneficial for processing device  1110  to do both touch-sensor pad and keyboard control operations, thereby freeing up the embedded controller  1160  for other housekeeping functions. In another exemplary embodiment, interfacing may be done using a universal serial bus (USB) interface directly coupled to host  1150  via host interface line  1151 . Alternatively, processing device  1110  may communicate to external components, such as host  1150  using industry standard interfaces, such as USB, PS/2, inter-integrated circuit (I2C) bus, or system packet interfaces (SPI). Host  1150  and/or embedded controller  1160  may be coupled to processing device  1110  with a ribbon or flex cable from an assembly, which houses the sensing device and processing device. 
     In one embodiment, processing device  1110  is configured to communicate with embedded controller  1160  or host  1150  to send and/or receive data. The data may be a command or alternatively a signal. In an exemplary embodiment, system  1100  may operate in both standard-mouse compatible and enhanced modes. The standard-mouse compatible mode utilizes the HID class drivers already built into the Operating System (OS) software of host  1150 . These drivers enable processing device  1110  and sensing device to operate as a standard cursor control user interface device, such as a two-button PS/2 mouse. The enhanced mode may enable additional features such as scrolling (reporting absolute position) or disabling the sensing device, such as when a mouse is plugged into the notebook. Alternatively, processing device  1110  may be configured to communicate with embedded controller  1160  or host  1150 , using non-OS drivers, such as dedicated touch-sensor pad drivers, or other drivers known by those of ordinary skill in the art. 
     Processing device  1110  may reside on a common carrier substrate such as, for example, an integrated circuit (IC) die substrate, a multi-chip module substrate, or the like. Alternatively, the components of processing device  1110  may be one or more separate integrated circuits and/or discrete components. In one exemplary embodiment, processing device  1110  may be a Programmable System on a Chip (PSoC™) processing device, manufactured by Cypress Semiconductor Corporation, San Jose, Calif. Alternatively, processing device  1110  may be one or more other processing devices known by those of ordinary skill in the art, such as a microprocessor or central processing unit, a controller, special-purpose processor, digital signal processor (“DSP”), an application specific integrated circuit (“ASIC”), a field programmable gate array (“FPGA”), or the like. In an alternative embodiment, for example, processing device  1110  may be a network processor having multiple processors including a core unit and multiple microengines. Additionally, processing device  1110  may include any combination of general-purpose processing device(s) and special-purpose processing device(s). 
     Capacitance sensor  1101  may be integrated into the IC of processing device  1110 , or alternatively, in a separate IC. Descriptions of capacitance sensor  1101  may be generated and compiled for incorporation into other integrated circuits. For example, behavioral level code describing capacitance sensor  1101 , or portions thereof, may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a machine-accessible medium (e.g., CD-ROM, hard disk, floppy disk, etc.). Furthermore, the behavioral level code can be compiled into register transfer level (“RTL”) code, a netlist, or even a circuit layout and stored to a machine-accessible medium. The behavioral level code, the RTL code, the netlist, and the circuit layout all represent various levels of abstraction to describe capacitance sensor  1101 . 
     In one embodiment, electronic system  1100  may be used in a notebook computer. Alternatively, system  1100  may be used in other applications, such as a mobile handset, a personal data assistant (PDA), a keyboard, a television, a remote control, a monitor, a handheld multi-media device, a handheld video player, a handheld gaming device, or a control panel. 
     The processes explained above are described in terms of computer software and hardware. The techniques described may constitute machine-executable instructions embodied within a machine (e.g., computer) readable medium, that when executed by a machine will cause the machine to perform the operations described. Additionally, the processes may be embodied within hardware, such as an application specific integrated circuit (“ASIC”) or the like. 
     A machine-accessible medium includes any mechanism that provides (e.g., stores) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine-accessible medium includes recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). 
     The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
     These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.