Abstract:
A current source circuit for providing a stable current into a filter element of a phase-lock-loop circuit of a clock generator. The current source circuit comprises a first resistor coupled to a voltage supply. The emitter of a first transistor is coupled to the first resistor; the base is coupled to a bias voltage, and the collector is coupled to a capacitor. The capacitor forms part of the filter of the phase-lock-loop circuit. Current flows from the voltage supply through the first resistor and first transistor into the capacitor. A second transistor has a collector coupled to the capacitor; a base; and an emitter coupled to ground via a second resistor. The second transistor and resistor causes a fixed amount of current to be sinked from the capacitor. Leakage current flowing out of the capacitor due to the inherent Rcb impedance associated with the second transistor is directed to a path provided by a third transistor. The third transistor has an emitter coupled to the base of the second transistor and a collector coupled to the emitter of the first transistor. The third transistor directs the Rcb leakage current inherent to the second transistor back into the capacitor. Thereby, the Rcb leakage current flowing out from the capacitor is canceled by the current flowing back into the capacitor via the third and first transistors. This produces a more stable current, and hence, more stable voltage being maintained by the capacitor. A more stable voltage means that the capacitor can be made smaller. In turn, this enables the phase-lock-loop to be fabricated on-chip with the rest of the clock generator, thereby minimizing its susceptibility to external noise and interferences. Furthermore, a more stable voltage across the filter element of the phase-lock-loop reduces unwanted jitter in the clock signal.

Description:
This Application is a Continuation-in-Part of Ser. No. 09/183,452, filed Oct. 30, 1998, now U.S. Pat. No. 6,188,268 and a Continuation-in-Part of Ser. No. 09/183,198 filed on Oct. 30, 1998 and a Continuation-in-Part of Ser. No. 09/183,321 filed on Oct. 30, 1998. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a circuit for minimizing the current leakage associated with a phase-lock-loop filter necessary for high speed clock generators used in advanced digital systems. More particularly, the present invention provides a novel circuit for reducing the effect associated with the Rcb leakage path inherent in the low side current source transistor of the PLL filter. 
     BACKGROUND OF THE INVENTION 
     High speed digital systems, such as engineering workstations and personal computers, require clock sources to provide a timing reference. It is imperative that these timing references be highly accurate and stable. Otherwise, the performance of the digital systems relying on these clock sources would be impaired. One method for achieving a clean, fast, and accurate clock source is to use a crystal oscillator coupled with a phase-lock-loop (PLL) circuit to regulate its frequency. In this type of arrangement, the goal then is to design the PLL such that it exhibits low jitter and high bandwidth in order to generate an optimal clock signal. 
     The PLL circuitry in the clock generator typically contains a voltage controlled oscillator (VCO) that receives a voltage level maintained by filter components. Normally, charging currents and voltage controlled oscillator gains are so high that externally situated filter components are required to external, e.g., “off-chip,” filter components (e.g., capacitors, etc.) increase the overall cost of the digital system in part by making manufacturing more complex, and also increase the physical size of the digital system. Furthermore, off-chip filter components also decrease system reliability by increasing the phase jitter by allowing external noise to be injected into the clock circuit through the PLL filter. Clock jitter is reduced if external elements of the PLL loop filter can be eliminated. To integrate filter components “on-chip,” it is necessary to use smaller sized filter components. However, this leads to tighter filter leakage requirements because smaller sized capacitors are more sensitive to changes in current when compared to larger sized capacitors. 
     It is desired to reduce the effects of leakage current within a PLL circuit because, as discussed above, on-chip filter components are very sensitive to small leakage currents. PLL filters are normally driven by current source circuits and require outputs having a very high impedance. A problem exists in eliminating off-chip filters and placing them on-chip. Namely, reducing the size of the filters (thereby allowing them to be placed on-chip) unfortunately makes these components more sensitive to leakage current which impedes the ideal operation of certain PLL circuits. As a result, it is desired to use buffer circuits that have reduced leakage current to drive differential filters for higher PLL accuracy. At the same time, this circuitry needs to operate from increasingly lower power supply voltages, e.g., to accommodate hand-held and other portable battery operated applications. integrated on the same chip, which reduces cost and minimizes its susceptibility to external noise and other interferences, while also minimizing the effects of current leakage, thereby reducing clock jitter and maintaining tight PLL bandwidth requirements. 
     SUMMARY OF THE INVENTION 
     The present invention pertains to a highly stable current source circuit. Basically, the present invention provides a mechanism whereby the leakage current inherent to a transistor used in the current source is first detected and then an equal but opposite amount of current is fed back in order to effectively cancel out the leakage current. The net effect is as if there were no leakage current at all, thereby providing a highly stable current source. This current source circuit is ideal for providing a stable current into a filter element of a phase-lock-loop circuit of a clock generator. For example, a more stable current provided into the capacitor of the phase-lock-loop will ultimately result in reducing unwanted clock jitter. Furthermore, a more stable current means that the capacitor can be made smaller because its voltage can be maintained at a constant level. In turn, this enables the phase-lock-loop to be fabricated on-chip with the rest of the clock generator, thereby minimizing its susceptibility to external noise and interferences. 
     In the currently preferred embodiment of the present invention, the current source circuit comprises a resistor coupled to ground. The emitter of a transistor is coupled to the resistor; the base is coupled to a bias voltage; and the collector is coupled to a capacitor which is part of the filter elements of the phase-lock-loop. Current is sinked from the capacitor through the resistor and transistor to ground. Leakage current flowing out of the capacitor due to the inherent Rcb impedance associated with the transistor is directed to a path provided by a second transistor. The second transistor has an emitter coupled to the base of the first transistor and a collector coupled to the capacitor. The second transistor is biased such that the Rcb leakage current inherent to the first transistor is directed back into the capacitor. The Rcb leakage current flowing out from the capacitor through the first transistor is canceled by the current flowing back into the capacitor via the second transistor, thereby providing a highly stable current source. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention: 
     FIG. 1 is a logical block diagram of a clock generator circuit  100  upon which the present invention can be practiced. 
     FIG. 2 illustrates in more detail a clock generation circuit as one example in which the current source circuit of the present invention can operate. 
     FIG. 3 illustrates a circuit design according to the present invention that can be used to implement high side current sources. 
     FIG. 4 illustrates the circuitry of one embodiment of a differential side of the clock generation circuit. 
     FIG. 5 illustrates an exemplary circuit for generating the Vbias voltage for biasing transistors used in the high side current source. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following detailed description of the present invention, a novel circuit for Rcb cancellation in high-side, low power supply current sources, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention. 
     FIG. 1 is a logical block diagram of a clock generator circuit  100  upon which the present invention can be practiced. Clock generator circuit  100  includes a crystal oscillator  101  that generates an input frequency (fin) at  102 . The fn signal is input to a phase lock loop circuit  103 . PLL circuit  103  is comprised of voltage regulator  104 , phase frequency detector (PFD)  105 , filter  106 , voltage controlled oscillator (VCO)  107 , and divider  108 . The PFD  105  is coupled to receive frequency  102  and is coupled to a divider circuit  108  which receives an external divider control signal  109 . The PFD  105  is also coupled to a filter circuit  106  which, in turn, is coupled to VCO  107 . A feedback loop from the output of VCO  107  to the divider circuit  108  back to the PFD  105  is established to control the output frequency (fo)  110 . The filter  106  and the VCO circuit  107  are coupled to receive power from a regulator  104  which is coupled to a power supply. The output of the VCO circuit  107  generates the output clock frequency (fo) at  110 . 
     FIG. 2 illustrates in more detail a clock generation circuit  100  as one example in which the current source circuit of the present invention can operate. The high-side current source design of the present invention can operate in conjunction with a variety of different circuit systems where Rcb cancellation is required, (e.g., a high impedance load in an operational amplifier). Therefore, it is appreciated that the clock generation circuit  100  is only one example of such a circuit system. 
     Specifically, clock generation circuit  100  of FIG. 2 contains a phase lock loop circuit having a differential circuit configuration. Circuit  100  is implemented “on chip,” that is, a single integrated circuit chip is used to realize circuit  100 . The high side of a power supply voltage is coupled to regulator  104 . Although the high side voltage can be of a wide range of voltages, in one embodiment the high side voltage is approximately within the range of 2.7 to 3.3 volts. The regulator  104  is coupled via line  201  to two ends of a differential circuit configuration having differential side  202  and differential side  203 . Each differential side include a current source circuit (e.g.,  204 ) and a current sink circuit (e.g.,  205 ). Voltage supply line  201  is coupled to resistors  206  and  207 . Resistor  206  is coupled to the other components of current source  204  of the present invention. Current source  208 , also of the design of the present invention includes resistor  207 . As described in more detail below, current source  204  contains a feedback loop  209  and an operational amplifier circuit  210  which receives a direct current (DC) bias voltage at its (−) input  211  and a feedback loop  209  at its (+) input. A charge pump injects current over line  212 . 
     Current sink circuits  205  and  213  are described in co-pending U.S. patent application Ser. No. 09/183,452, concurrently filed herewith, entitled “Low Side Current Sink Circuit Having Improved Output Impedance to Reduce Effects of Leakage Current,” by Nayebi et al., now U.S. Pat. No. 6,188,268, and assigned to the assignee of the present invention. 
     The current sources  204  and  208  are used, in one embodiment, in combination with current sink circuits  205  and  213 , to maintain current through filter elements  215  and  215 . Charge pumps  216  and  217  inject additional current to thereby establish a differential voltage across the filter elements  214  and  215 . 
     Filter components  214  and  215  are integrated circuit capacitors and as such they are integrated within the IC chip of circuit  100 . The differential voltage is used as an input to a voltage controlled oscillator circuit of the phase lock loop circuit within clock generation circuit  100 . It is desired to provide a stable voltage at the input of the voltage controlled oscillator circuit in order to reduce clock jitter within clock generation circuit  100 . One way that the voltage can change across the filter elements  214  and  215  is as a result of current fluctuations in the current injected from current sources  204  and  208 . 
     Specifically, current flowing across the filter elements  214  and  215  charges them, thereby changing their differential voltage. In circuit  100 , the filter elements, e.g., capacitors  214  and  215 , are designed to be small internal “on-chip” devices (having correspondingly small capacitance values). As a result, the voltage level across these small filter elements  214  and  215  is very sensitive to small changes in the injected currents at nodes  216  and  217 . The changing differential voltage across filter elements  214  and  215  causes time jitter in circuit  100  because it causes changes in the input voltage of the voltage controlled oscillator. 
     Buffer circuits  218  and  219  sample the voltage over the filter elements. Buffer circuits contain a high input impedance buffer circuit as described in patent application Ser. No. 09/183,198, concurrently filed herewith, entitled “High Input Impedance Buffer Circuit,” by Nayebi et al., and assigned to the assignee of the present invention. 
     Therefore, in accordance with the design of the present invention, the current supplied from current sources  204  and  208  is very stable once it is set to a desired level and held there over time. In accordance with the present invention, by reducing leakage current, the filter elements  214  and  215  maintain a stable differential voltage level. In operation, the current supplied from current sources  204  and  208  is adjusted to set a particular operational frequency of clock generation circuit  100  and then held over a hold period. Hold periods are situated in between phase lock loop correction pulses. The present invention advantageously offsets the effects of leakage current as one way to stabilize the current supplied from current sources  204  and  208  during the hold periods. The effects of leakage current are reduced, in accordance with the present invention, by establishing a current path through which the Rcb leakage current is routed back to nodes  216  and  217 . By establishing a separate current path for the Rcb leakage current, this leakage current is effectively fed back into the filter component  214 , thereby providing a stable input voltage to the voltage controlled oscillator of the phase lock loop circuit and reducing jitter in the output clock signal of circuit  100 . 
     FIG. 3 illustrates a circuit design  300  according to the present invention that can be used to implement the high side current sources  204  and  208  of FIG.  2 . It should be noted that a bipolar process is used in the currently preferred embodiment of the present invention. One end of a resistor  301  is coupled to a supply voltage, Vcc. The other end of resistor  301  is coupled to the emitter of a PNP transistor  302 . The collector of PNP transistor is coupled to a capacitor  214 . Capacitor  214  is part of the filter component of the PLL as described above. The base of PNP transistor  302  is coupled to a bias voltage. Hence, a fixed current, I 1 , is caused to flow through resistor  301 . The current, I 1 , is equal to (Vcc- Vbias- Vbe) divided by the resistivity of resistor  301 . Thereby, transistor  302  conducts the I 1  current through to node  308 . This part of the circuit comprises the high side current source, I 1  to flow into capacitor  214 . The low side current source for sinking current from capacitor  214  is comprised of NPN transistor  305  and resistor  306 . One end of resistor  306  is coupled to ground. The other end of resistor  306  is coupled to the emitter of NPN transistor  305 . The collector of transistor  305  is coupled to capacitor  214 . Thereby, a sink current,  12 , flowing from capacitor  214  is produced. In effect, the I 1  current is flowing into node  308  from the high side current source while the  12  current from the low side current source is caused to flow out from node  308 . Thus, there is a current of I 1 -I 2  flowing through to capacitor  214 , which is part of the filter components of the PLL as described above. Capacitor  214  is fabricated on the same chip as the rest of the circuit shown in FIGS. 2 and 3. Consequently, capacitor  214  is relatively small in order to conserve silicon area on the chip. In the currently preferred embodiment, capacitor  214  is on the order of 100 picofarads. Resistors  301  and  306  are 30 KΩ. 
     Ideally, transistor  302  would have an infinite impedance looking from its collector to base. However, in practice, all transistors have a finite Rcb impedance, anywhere from approximately 500 kΩ to 2 MΩ. As such, there will be some amount of leakage current (IL) flowing from node  308  through Rcb  303 . Note that Rcb  303  is not a separate resistor; it represents the impedance inherent between the collector-base of transistor  305 . As discussed above, this leakage current can cause the voltage across capacitor  214  to fluctuate, which leads to unwanted jitter. The present invention does not stop or reduce this leakage current, IL, from flowing through Rcb  303 . Instead, the present invention routes IL such that it essentially cancels itself out. This is accomplished by adding NPN transistor  304 . The emitter of NPN transistor  304  is coupled to the base of NPN transistor  305 . The collector of NPN transistor  304  is coupled to the emitter of transistor  302 . The base of transistor  304  is coupled to the output of an operational-amplifier (op-amp)  307 . Op-amp  307  has two inputs. A bias voltage is provided to the positive input of op-amp  307 ; the negative input to op-amp  307  is coupled to the emitter of transistor  305 . In operation, the base of transistor  304  is biased by op-amp  307  such that it is conducting. It conducts the leakage current IL flowing from Rcb  303  back through transistor  302  to node  308 , thereby effectively canceling itself out. In other words, the present invention compensates by detecting how much current is leaking and then injecting the equal but opposite amount of current back so that the net effect is as if there were no leakage. Applying Kirchoff&#39;s current law (the algebraic sum of all currents entering a node must equal the algebraic sum of all the currents leaving a node) to node  308 , one can determine that there is a current I 1  flowing from the high side current source and entering node  308 ; a current IL flowing from transistor  304  and entering node  308 ; a current I 2  flowing from transistor  305  of the low side current source and leaving node  308 ; and a current IL flowing through Rcb  303  and leaving node  308 . Therefore, adding all these currents entering and leaving node  308  yields the fact that there must be I 1 -I 2  current flowing out of node  308  and into capacitor  214 . Note that the leakage current IL flowing out of node  308  due to Rcb of transistor  302  is effectively canceled out by approximately the same amount of IL current being fed back into node  308  via transistor  304 . As such, the present invention is ideally suited for canceling out Rcb (e.g., it could be used as a high impedance load in an op-amp, or it could be used to provide accurate current sources in a digital-to-analog converter). 
     FIG. 4 illustrates the circuitry  400  of one embodiment of a differential side of the clock generation circuit. The circuitry  400  includes a particular embodiment of current source circuit  300  in accordance with the present invention and also includes a current sink. It should be noted that the current source and sink circuitry for either differential side are the same. Specifically, the emitter degeneration resistor, RE,  301  is coupled to Vcc  405 . Resistor  301  is coupled to the emitter of transistor  302 . The positive (+) input of the operational amplifier circuit (shown as  307  of FIG. 3) is represented by line  445  which is coupled to the base of transistor  409 . The negative (−) input of operational amplifier circuit  307  is represented by the base of transistor  405  which is coupled to the emitter of transistor  302  in a feedback loop. The output of operational amplifier  307  is taken at the emitter of transistor  304  which is coupled to the base of transistor  302 . 
     The collector of transistor  302  is coupled to output node  460  which is coupled to transistor  305 . Transistor  305  is coupled to line  445  and also coupled to transistor  304  and to transistor  461 . The emitter of transistor  302  is coupled to transistor  427  which is coupled to the base of transistor  331  which is also coupled to transistor  429 . Transistor  429  is coupled to resistor  435  which is coupled to line  443 . The supply voltage  405  is also coupled to transistor  405  which is coupled to the base of transistor  407  and also coupled to transistor  423 . Transistor  423  is coupled to resistor  425  which is coupled to line  441 . The supply voltage  405  is coupled to resistor  411  which is coupled to both transistors  409  and  407 . Transistor  407  is coupled to the base of transistor  304  and also coupled to transistor  470  which is coupled to resistor  433  which is coupled to line  439 . 
     The base of transistor  470  is coupled to line  485  which is also coupled to the base of transistor  429 . Transistor  409  is coupled to line  437 . The base of transistor  461  is coupled to the emitter of transistor  461  and also coupled to the base of transistor  463  and also coupled to transistor  473 . Line  487  is coupled to transistor  463 . Transistor  463  is coupled to the base of transistor  427  and also coupled to transistor  475 . Line  483  is coupled to the base of transistor  423 . Line  447  is coupled to transistor  421 . In addition to the base of transistor  409 , line  245  is coupled to the bases of transistors  473 ,  475 ,  477  and  479 . 
     The supply voltage  405  is also coupled to transistor  413 . The collector of transistor  413  is coupled to the base of collector  413  and also to the collector of transistor  415  and to the base of transistor  415  and to transistor  479 . Transistor  415  is coupled to the collector and base of transistor  417 . Transistor  417  is coupled to resistor  419  which is coupled to transistor  421 . The supply voltage  205  is also coupled to resistors  471 ,  469 ,  467  and  465 . Resistor  471  is coupled to transistor  473 . Resistor  469  is coupled to transistor  475 . Resistor  467  is coupled to transistor  477 . Resistor  465  is coupled to transistor  479 . 
     It is appreciated that resistor  411  of FIG. 4 is used between the supply voltage  405  and the emitters of transistors  407  and  409  in lieu of a transistor in an effort to increase the operational (e.g., DC) voltage at the emitters of PNP transistors  409  and  407 . In low voltage applications (e.g., where the supply voltage  405  is between 2.0 and 3.3 volts), this arrangement acts to increase the dynamic range of the current source in accordance with the present invention so that the current source can more effectively operate within low voltage environments. The voltage at the emitters of transistor  407  and  409  is a function of the tail current and the bias current. 
     In addition to the resistor  411 , the operational amplifier circuit  220  of the present invention also contains a level shifting circuit to increase the operational voltage at the emitter of transistor  430  to help increase the dynamic range of current source in low voltage environments. The level shifting circuitry includes PNP transistor  407  and NPN transistor  405 . There is a {fraction (7/10)} volt drop from the voltage supply  405  to the base of transistor  407 . From the base of transistor  407  there is a {fraction (7/10)} volt increase to the base of transistor  405  which is also the emitter of transistor  430 . This circuit configuration creates a DC level shift to increase the DC voltage at the emitter of transistor  430 . This effectively increases the dynamic linear range of operation for the current source in cases when a low voltage power supply is used. It is desired to have the output of the current source swing as large as possible to achieve a low VCO gain for the VCO of FIG.  1 . 
     FIG. 5 illustrates an exemplary circuit for generating the Vbias voltage over line  545 . Using a resistor divider technique, Vcc  505  is coupled to resistor  542  which is coupled in series to resistor  544  which is coupled to ground. The node between resistors  542  and  544  is coupled in parallel to the bases of NPN transistors of a buffer circuit  536 . The NPN transistors of buffer circuit  436  are also coupled to Vcc  505  and also to line  545 . Line  245  is coupled to the base of transistor  514 . Buffer circuit  536  makes the Vbias voltage on line  545  less dependent on loading. 
     Line  545  is also coupled to transistor  524  which is coupled to resistor  528  which is coupled to ground. Vcc  505  is coupled to resistor  540  which is coupled to transistor  520  which is coupled to transistor  522  which is coupled to resistor  526  which is coupled to ground. The node between transistors  522  and  520  is coupled to the base of transistor  522  and  524  and supplied as line  583 . The node between resistor  540  and transistor  520  is coupled to the base of transistor  520 . Node  510  is coupled to resistor  530  and supplied as line  587 . 
     Vcc  505  of FIG. 5 is coupled to resistor  512  which is coupled to transistor  514  which is coupled to transistor  516  which is coupled to resistor  518  which is coupled to ground. The node between transistor  514  and  516  is coupled to the base of transistor  516  and supplied as line  585 . 
     Although a number of different resistor configurations can be used in accordance with the present invention, Table I below illustrates one exemplary resister assignment. 
     
       
         
               
               
               
             
           
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                 Resistor 
                 Approximate Resistor Valve (ohms) 
               
               
                   
                   
               
             
             
               
                   
                 471 
                 75k 
               
               
                   
                 469 
                 60k 
               
               
                   
                 467 
                 75k 
               
               
                   
                 465 
                 60k 
               
               
                   
                 419 
                 30k 
               
               
                   
                 411 
                 30k 
               
               
                   
                 433 
                 45k 
               
               
                   
                 425 
                 30k 
               
               
                   
                 435 
                 65k 
               
               
                   
                 301 
                 30k 
               
               
                   
                 542 
                  3k 
               
               
                   
                 544 
                 24k 
               
               
                   
                 540 
                 25k 
               
               
                   
                 512 
                 60k 
               
               
                   
                 518 
                 45k 
               
               
                   
                 526 
                  7k 
               
               
                   
                 528 
                 27k 
               
               
                   
                 530 
                  3k 
               
               
                   
                   
               
             
          
         
       
     
     The operation of the circuit implementation is described as follows. The emitter degeneration resistor is resistor  301  as shown in FIG.  3 . The inverting side of the operational amplifier  307  is formed by transistors  405  and transistor  407 . Tail current is provided by resistor  411 . A current sink which is half the tail current is provided by transistor  470 . The output of the operational amplifier  307  is at the emitter of transistor  304 . The non-inverting side of the operational amplifier  307  consists of transistor  405 . 
     With respect to FIG. 5, the Vbias voltage input is formed by the divider consisting of resistors  542  and  544 . Resistor  512 , transistor  514 , transistor  516  and resistor  518  of FIG. 5 provide the bias line  585  for the current source transistor  570 . The operational amplifier topology of the present invention is designed to operate within low power supply environments where the power supply voltage, Vcc  205 , is low (e.g., 2.0 to 3.3 volts). In one embodiment, the power supply voltage Vcc  205  is 2.7 volts. Low power supply voltage restricts the size of the voltage that can be impressed across resistor  310 . This requires that an NPN input stage (transistor  405 ) be used in the operational amplifier circuit  307 . This NPN transistor  405  also provides level shifting so that a PNP input operational amplifier can be used to simplify the resulting circuit. This NPN transistor  405  is therefore followed by a PNP transistor  407 . In one embodiment, a resistor  411  is used to supply tail current in lieu of a transistor due to constraints. This current is constant. 
     The preferred embodiments of the present invention, a novel circuit for Rcb cancellation in a high side, low power supply current source, are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.