Abstract:
A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2002-12640, filed Jan. 22, 2002, and No. 2002-183983, filed Jun. 25, 2002, the entire contents of both of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same and, more particularly, to a semiconductor integrated circuit device having a memory cell including a magnetoresistive element and a method of manufacturing the same. 
     2. Description of the Related Art 
       FIG. 73  is a sectional view showing a typical magnetic random access memory. 
     As shown in  FIG. 73 , a memory cell of a magnetic random access memory has a cell transistor and an MTJ (Magnetic Tunnel Junction) element  118  connected between a bit line  113 - 1  and one of source and drain regions  105  of the cell transistor. The other of the source and drain regions  105  of the cell transistor is connected to a source line  109 - 1  through a contact  107 . A gate electrode  104  functions as a read word line. 
     The MTJ element  118  is connected to one of the source and drain regions  105  through an intracell local interconnection  121 - 1 , contact  120 , intracell via  113 - 2 , contact  111 , intracell via  109 - 2 , and contact  107 . 
     Conventionally, the MTJ element  118  is formed on the intracell local interconnection  121 - 1 . A write word line  124 - 1  is formed under the intracell local interconnection  121 - 1 . The bit line  113 - 1  is formed on the MTJ element  118 . 
     However, the typical magnetic random access memory has some problems to be described below. 
       FIG. 74  is a sectional view for explaining the first problem of the typical magnetic random access memory. 
     As shown in  FIG. 74 , the write word line  124 - 1  is formed under the intracell local interconnection  121 - 1 . For this reason, a thickness t 1  of the intracell local interconnection  121 - 1  and a thickness t 2  of a dielectric interlayer that insulates the intracell local interconnection  121 - 1  and write word line  124 - 1  from each other are present between the MTJ element  118  and the write word line  124 - 1 . Hence, a distance D between the MTJ element  118  and the write word line  124 - 1  is large. When the distance D is large, it is difficult to efficiently apply the magnetic field from the write word line  124 - 1  to the MTJ element  118 . This makes it hard to, e.g., write data. 
     To reduce the distance D, for example, the intracell local interconnection  121 - 1  is thinned. However, it is difficult to thin the intracell local interconnection  121 - 1  due to the following reason. 
       FIGS. 75A ,  75 B, and  75 C are sectional views for explaining the second problem of the typical magnetic random access memory. 
     As shown in  FIG. 75A , to form an MTJ element, a magnetic tunnel junction is formed from a ferromagnetic layer  114 , insulating layer  115 , and ferromagnetic layer  116 . Then, a mask layer  117  corresponding to the formation pattern of the MTJ element is formed. 
     Next, as shown in  FIG. 75B , the magnetic tunnel junction is etched using the mask layer  117  as a mask. At this time, a metal layer  121  that forms an intracell local interconnection functions as, e.g., an etching stopper. In this etching, if the metal layer  121  is thin, it may vanish, as shown in FIG.  75 C. When the metal layer  121  vanishes, the intracell local interconnection cannot be formed. 
     Due to, e.g., the above reason, the intracell local interconnection  121 - 1  is hard to thin. 
     Even if the metal layer  121  does not vanish, it is etched, as shown in FIG.  75 B. For this reason, the thickness of the metal layer  121  varies. The etching amount of the metal layer  121  is not always uniform in, e.g., the chip or wafer. Hence, the thickness of the metal layer  121  varies in a wide range. The wide-ranging variation in thickness of the metal layer  121  causes, e.g., a variation in resistance value of the intracell local interconnection  121 - 1 . 
     If the resistance value of the intracell local interconnection  121 - 1  varies, the resistance value of a resistor  200  between the bit line  113 - 1  and the cell transistor also varies, as shown in the equivalent circuit diagram shown in FIG.  76 . Such a variation in resistance value may influence, e.g., the reliability related to a data read. 
     BRIEF SUMMARY OF THE INVENTION 
     A semiconductor integrated circuit device according to an aspect of the present invention comprises: a cell transistor; a bit line provided above the cell transistor a magnetoresistive element provided above the bit line, an under end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a top end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, the write word line applying a magnetic field to the magnetoresistive element under the intracell local connection. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         FIG. 1  is a plan view showing the planar pattern of a magnetic random access memory according to a first embodiment of the present invention; 
         FIG. 2A  is a sectional view taken along a line A—A in  FIG. 1 ; 
         FIG. 2B  is a sectional view taken along a line B—B in  FIG. 1 ; 
         FIG. 2C  is a sectional view taken along a line C—C in  FIG. 1 ; 
         FIG. 2D  is a sectional view of the substrate contact portion of a peripheral circuit; 
         FIGS. 3A ,  3 B,  3 C, and  3 D are sectional views showing a method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 4A ,  4 B,  4 C, and  4 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 5A ,  5 B,  5 C, and  5 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 6A ,  6 B,  6 C, and  6 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 7A ,  7 B,  7 C, and  7 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 8A ,  8 B,  8 C, and  8 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 9A ,  9 B,  9 C, and  9 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 10A ,  10 B,  10 C, and  10 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 11A ,  11 B,  11 C, and  11 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 12A ,  12 B,  12 C, and  12 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 13A ,  13 B,  13 C, and  13 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 14A ,  14 B,  14 C, and  14 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIGS. 15A ,  15 B,  15 C, and  15 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention; 
         FIG. 16  is a plan view showing the planar pattern of a magnetic random access memory according to a second embodiment of the present invention; 
         FIG. 17A  is a sectional view taken along a line A—A in  FIG. 16 ; 
         FIG. 17B  is a sectional view taken along a line B—B in  FIG. 16 ; 
         FIG. 17C  is a sectional view taken along a line C—C in  FIG. 16 ; 
         FIG. 17D  is a sectional view of the substrate contact portion of a peripheral circuit; 
         FIGS. 18A ,  18 B,  18 C, and  18 D are sectional views showing a first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 19A ,  19 B,  19 C, and  19 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 20A ,  20 B,  20 C, and  20 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 21A ,  21 B,  21 C, and  21 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 22A ,  22 B,  22 C, and  22 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 23A ,  23 B,  23 C, and  23 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 24A ,  24 B,  24 C, and  24 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 25A ,  25 B,  25 C, and  25 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 26A ,  26 B,  26 C, and  26 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 27A ,  27 B,  27 C, and  27 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 28A ,  28 B,  28 C, and  28 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 29A ,  29 B,  29 C, and  29 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 30A ,  30 B,  30 C, and  30 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 31A ,  31 B,  31 C, and  31 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 32A ,  32 B,  32 C, and  32 D are sectional views showing a second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 33A ,  33 B,  33 C, and  33 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 34A ,  34 B,  34 C, and  34 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 35A ,  35 B,  35 C, and  35 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 36A ,  36 B,  36 C, and  36 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 37A ,  37 B,  37 C, and  37 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 38A ,  38 B,  38 C, and  38 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 39A ,  39 B,  39 C, and  39 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 40A ,  40 B,  40 C, and  40 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 41A ,  41 B,  41 C, and  41 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 42A ,  42 B,  42 C, and  42 D are sectional views showing the third method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 43A ,  43 B,  43 C, and  43 D are sectional views showing the third method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 44A ,  44 B,  44 C, and  44 D are sectional views showing the third method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 45A ,  45 B,  45 C, and  45 D are sectional views showing the third method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 46A ,  46 B,  46 C, and  46 D are sectional views showing the third method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 47A ,  47 B,  47 C, and  47 D are sectional views showing the third method of manufacturing the magnetic random access memory according to the second embodiment of the present invention; 
         FIGS. 48A ,  48 B,  48 C, and  48 D are sectional views showing a modification to the magnetic random access memory according to the second embodiment of the present invention; 
         FIG. 49  is a plan view showing the planar pattern of a magnetic random access memory according to the third embodiment of the present invention; 
         FIG. 50A  is a sectional view taken along a line A—A in  FIG. 49 ; 
         FIG. 50B  is a sectional view taken along a line B—B in  FIG. 49 ; 
         FIG. 50C  is a sectional view taken along a line C—C in  FIG. 49 ; 
         FIG. 50D  is a sectional view of the substrate contact portion of a peripheral circuit; 
         FIGS. 51A ,  51 B,  51 C, and  51 D are sectional views showing a method of manufacturing the magnetic random access memory according to the third embodiment of the present invention; 
         FIGS. 52A ,  52 B,  52 C, and  52 D are sectional views showing the method of manufacturing the magnetic random access memory according to the third embodiment of the present invention; 
         FIGS. 53A ,  53 B,  53 C, and  53 D are sectional views showing the method of manufacturing the magnetic random access memory according to the third embodiment of the present invention; 
         FIGS. 54A ,  54 B,  54 C, and  54 D are sectional views showing the method of manufacturing the magnetic random access memory according to the third embodiment of the present invention; 
         FIGS. 55A ,  55 B,  55 C, and  55 D are sectional views showing the method of manufacturing the magnetic random access memory according to the third embodiment of the present invention; 
         FIGS. 56A ,  56 B,  56 C, and  56 D are sectional views showing the method of manufacturing the magnetic random access memory according to the third embodiment of the present invention; 
         FIGS. 57A ,  57 B,  57 C, and  57 D are sectional views showing the first modification to the magnetic random access memory according to the third embodiment of the present invention; 
         FIGS. 58A ,  58 B,  58 C, and  58 D are sectional views showing the second modification to the magnetic random access memory according to the third embodiment of the present invention; 
         FIGS. 59A ,  59 B,  59 C, and  59 D are sectional views showing a method of manufacturing a magnetic random access memory according to a fourth embodiment of the present invention; 
         FIGS. 60A ,  60 B,  60 C, and  60 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fourth embodiment of the present invention; 
         FIGS. 61A ,  61 B,  61 C, and  61 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fourth embodiment of the present invention; 
         FIGS. 62A ,  62 B,  62 C, and  62 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fourth embodiment of the present invention; 
         FIGS. 63A ,  63 B,  63 C, and  63 D are sectional views showing a method of manufacturing the magnetic random access memory according to a fifth embodiment of the present invention; 
         FIGS. 64A ,  64 B,  64 C, and  64 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fifth embodiment of the present invention; 
         FIGS. 65A ,  65 B,  65 C, and  65 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fifth embodiment of the present invention; 
         FIGS. 66A ,  66 B,  66 C, and  66 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fifth embodiment of the present invention; 
         FIGS. 67A ,  67 B,  67 C, and  67 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fifth embodiment of the present invention; 
         FIGS. 68A ,  68 B,  68 C, and  68 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fifth embodiment of the present invention; 
         FIGS. 69A ,  69 B,  69 C, and  69 D are sectional views showing the method of manufacturing the magnetic random access memory according to the fifth embodiment of the present invention; 
         FIG. 70A  is a sectional view showing a MTJ element according to a first example; 
         FIG. 70B  is a sectional view showing a MTJ element according to a second example; 
         FIG. 70C  is a sectional view showing a MTJ element according to a third example; 
         FIG. 70D  is a sectional view showing a MTJ element according to a fourth example; 
         FIGS. 71A and 71B  are side views showing a magnetic random access memory according to a reference embodiment of the present invention; 
         FIGS. 72A and 72B  are side views showing a magnetic random access memory according to the second to fifth embodiment of the present invention; 
         FIG. 73  is a sectional view showing a typical magnetic random access memory; 
         FIG. 74  is a sectional view for explaining the first problem of the typical magnetic random access memory; 
         FIGS. 75A ,  75 B, and  75 C are sectional views for explaining the second problem of the typical magnetic random access memory; and 
         FIG. 76  is an equivalent circuit diagram for explaining the third problem of the typical magnetic random access memory. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The embodiments of the present invention will be described below with reference to the accompanying drawing. In this description, the same reference numerals denote the same parts throughout the drawing. 
     (First Embodiment) 
       FIG. 1  is a plan view showing the planar pattern of a magnetic random access memory according to a first embodiment of the present invention.  FIG. 2A  is a sectional view taken along a line A—A in FIG.  1 .  FIG. 2B  is a sectional view taken along a line B—B in FIG.  1 .  FIG. 2C  is a sectional view taken along a line C—C in FIG.  1 .  FIG. 2D  is a sectional view of the substrate contact portion of a peripheral circuit. 
     As shown in  FIGS. 1 and 2A  to  2 D, the magnetic random access memory according to the first embodiment has a memory cell including a magnetoresistive element. In this embodiment, as a memory cell including a magnetoresistive element, a 1-magnetoresistive-element—1-transistor memory cell including one magnetoresistive element and one cell transistor will be exemplified. The cell transistor is formed in the element region of, e.g., a p-type silicon substrate  1 . The element region is defined by an element isolation region  2  formed on the substrate  1 . The cell transistor has a gate electrode  4  and n-type source and drain regions  5 . The gate electrode  4  functions as a read word line and extends in the first direction. A source line  9 - 1  and intracell via  9 - 2  are formed above the cell transistor. These elements are formed from, e.g., a first metal layer. The source line  9 - 1  extends in the first direction, like the read word line, and is connected to one of the source and drain regions  5 , e.g., the source region of the cell transistor through a first metal layer—substrate contact  7 . The intracell via  9 - 2  is connected to the other of the source and drain regions  5 , e.g., the drain region of the cell transistor through the first metal layer—substrate contact  7 . A bit line  13 - 1  and intracell via  13 - 2  are formed above the source line  9 - 1  and the intracell via  9 - 2 . These elements are formed from, e.g., a second metal layer. The intracell via  13 - 2  is connected to the intracell via  9 - 2  through a second metal layer—first metal layer contact  11 . The bit line  13 - 1  extends in the second direction that crosses, e.g., is perpendicular to the read word line. A magnetoresistive element, e.g., an Magnetic Tunnel Junction (MTJ) element  18  is formed on the bit line  13 - 1 . The MTJ element  18  is a Tunneling Magneto Resistive (TMR) element. The MTJ element  18  includes a fixed-layer and memory-layer, which are formed from magnetic layers, e.g., ferromagnetic layers, and a tunnel barrier layer formed from an insulating nonmagnetic layer formed between the fixed-layer and the memory-layer. In the fixed-layer, the direction of spin is fixed. In the memory-layer, the direction of spin changes in accordance with the write magnetic field. One end of the MTJ element  18 , e.g., the memory-layer is connected to the bit line  13 - 1 . An intracell local interconnection  21 - 1  is formed on the MTJ element  18 . The intracell local interconnection  21 - 1  is connected to the other end of the MTJ element  18 , e.g., the fixed-layer and also connected to the intracell via  13 - 2  through an extra metal—second metal layer contact  20  (in the present invention, a conductive layer that forms the intracell local interconnection  21 - 1  is called an extra metal layer for the descriptive convenience). With this structure, the MTJ element  18  is connected between the bit line  13 - 1  and the other of the source and drain regions  5 , e.g., the drain region of the cell transistor. A write word line  24 - 1  is formed above the intracell local interconnection  21 - 1 . The write word line  24 - 1  extends in the first direction, like, e.g., the read word line, to cross the bit line  13 - 1  on the upper side of the MTJ element  18 . In writing data in the MTJ element  18 , the write word line applies a magnetic field to the MTJ element  18 . The easy axis of magnetization of the MTJ element  18  is set in the first direction in which the write word line  24 - 1  extends. 
     In the magnetic random access memory according to the first embodiment, the MTJ element  18  is formed under the intracell local interconnection  21 - 1 . Hence, the intracell local interconnection  21 - 1  is not influenced when patterning the MTJ element  18 . For this reason, the intracell local interconnection  21 - 1  can be made thin, and the distance between the write word line  24 - 1  and the MTJ element  18  can be reduced. 
     The MTJ element  18  can easily receive the magnetic field for the write word line  24 - 1  as compared to a typical magnetic random access memory having an MTJ element on an intracell local interconnection. Hence, data can easily be written in the MTJ element  18 . 
     In addition, since the intracell local interconnection  21 - 1  is not influenced when patterning the MTJ element  18 , any variation in thickness of the intracell local interconnection  21 - 1  can be suppressed. This also makes it possible to suppress a variation in resistance value between the bit line and the cell transistor. Hence, the reliability related to a data read can be improved. 
     A method of manufacturing the magnetic random access memory according to the first embodiment of the present invention will be described next. 
       FIGS. 3A  to  15 D are sectional views showing the method of manufacturing the magnetic random access memory according to the first embodiment of the present invention.  FIGS. 3A ,  4 A,  5 A,  6 A,  7 A,  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A, and  15 A correspond to the section shown in FIG.  2 A.  FIGS. 3B ,  4 B,  5 B,  6 B,  7 B,  8 B,  9 B,  10 B,  11 B,  12 B,  13 B,  14 B, and  15 B correspond to the section shown in FIG.  2 B.  FIGS. 3C ,  4 C,  5 C,  6 C,  7 C,  8 C,  9 C,  10 C,  11 C,  12 C,  13 C,  14 C, and  15 C correspond to the section shown in FIG.  2 C.  FIGS. 3D ,  4 D,  5 D,  6 D,  7 D,  8 D,  9 D,  10 D,  11 D,  12 D,  13 D,  14 D, and  15 D correspond to the section shown in FIG.  2 D. 
     First, as shown in  FIGS. 3A  to  3 D, a shallow trench corresponding to an element isolation region is formed in the p-type silicon substrate  1 . The shallow trench is filled with an insulating material, e.g., SiO 2  to form an element isolation region (shallow trench isolation: STI). 
     Next, as shown in  FIGS. 4A  to  4 D, the substrate  1  corresponding to the element region defined by the element isolation region is thermally oxidized to form a gate insulating film (SiO 2 )  3 . Conductive polysilicon is deposited on the substrate  1  and on the element isolation region  2  to form a conductive polysilicon film. The conductive polysilicon film is patterned to form the gate electrode  4 . An n-type impurity such as arsenic or phosphorus is ion-implanted into the substrate  1  using the gate electrode  4  and element isolation region  2  as a mask and diffused to form n-type source and drain regions  5 . 
     As shown in  FIGS. 5A  to  5 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 4A  to  4 D to form a first dielectric interlayer  6 . Next, openings that reach the n-type source and drain regions  5  are formed in the first dielectric interlayer  6 . The openings are filled with a conductive material, e.g., a metal such as tungsten to form the first metal layer—substrate contacts  7 . 
     As shown in  FIGS. 6A  to  6 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 5A  to  5 D to form a second dielectric interlayer  8 . First metal layer interconnection trenches that reach the contacts  7  are formed in the second dielectric interlayer  8 . The interconnection trenches are filled with a conductive material, e.g., a metal such as tungsten to form interconnection patterns of a first metal layer  9 . In this embodiment, of the interconnection patterns, the source line  9 - 1 , intracell via  9 - 2 , and intra-peripheral-circuit via  9 - 3  are formed. 
     As shown in  FIGS. 7A  to  7 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 6A  to  6 D to form a third dielectric interlayer  10 . Next, openings that reach the intracell via  9 - 2  and intra-peripheral-circuit via  9 - 3  are formed in the third dielectric interlayer  10 . The openings are filled with a conductive material, e.g., a metal such as tungsten to form second metal layer—first metal layer contacts  11 . 
     As shown in  FIGS. 8A  to  8 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 7A  to  7 D to form a fourth dielectric interlayer  12 . Next, second layer metal interconnection trenches that reach the contacts  11  are formed in the fourth dielectric interlayer  12 . The interconnection trenches are filled with a conductive material, e.g., a metal such as tungsten to form interconnection patterns of a second metal layer  13 . In this embodiment, of the interconnection patterns, the bit line  13 - 1 , the intracell via  13 - 2 , and an intra-peripheral-circuit via  13 - 3  are formed. 
     As shown in  FIGS. 9A  to  9 D, a ferromagnetic material, e.g., CoFe or NiFe is sputtered on the structure shown in  FIGS. 8A  to  8 D to form a ferromagnetic layer  14 . Next, an insulating material, e.g., Alumina is deposited on the ferromagnetic layer  14  to form an insulating layer  15 . Subsequently, a ferromagnetic material e.g., CoFe or NiFe is sputtered on the insulating layer  15  to form a ferromagnetic layer  16 . Then, a mask material is deposited on the ferromagnetic layer  16  to form a mask layer  17 . The mask layer  17  is patterned into a shape corresponding to the layout pattern of the MTJ element. 
     As shown in  FIGS. 10A  to  10 D, the ferromagnetic layer  16 , insulating layer  15 , and ferromagnetic layer  14  are sequentially etched using the mask layer  17  as a mask. With this process, the MTJ element  18  having, e.g., a three-layered structure including the ferromagnetic layer  14 , insulating layer  15 , and ferromagnetic layer  16  is formed. In this embodiment, for example, the ferromagnetic layer  14  functions as a memory-layer in which the direction of spin changes in accordance with the write magnetic field. The insulating layer  15  functions as a tunnel barrier. The ferromagnetic layer  16  functions as a fixed-layer in which the direction of spin is fixed. Note that the MTJ element  18  is not limited to the above three-layered structure. 
     As shown in  FIGS. 11A  to  11 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 10A  to  10 D to form a fifth dielectric interlayer  19 . The fifth dielectric interlayer  19  is subjected to, e.g., chemical mechanical polishing (CMP) to expose the MTJ element  18 . Next, an opening that reaches the intracell via  13 - 2  is formed in the fifth dielectric interlayer  19 . The opening is filled with a conductive material, e.g., a metal such as tungsten to form an extra metal—second metal layer contact  20 . 
     As shown in  FIGS. 12A  to  12 D, a conductive material, e.g., a metal such as tungsten is deposited on the structure shown in  FIGS. 11A  to  11 D to form an extra metal layer  21 . In this embodiment, for example, the thickness of the extra metal layer  21 , i.e., the thickness of the extra metal layer in the typical magnetic random access memory can be made small. 
     As shown in  FIGS. 13A  to  13 D, the extra metal layer  21  is patterned to form the intracell local interconnection  21 - 1 . 
     As shown in  FIGS. 14A  to  14 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 13A  to  13 D to form a sixth dielectric interlayer  22 . An opening that reaches the intra-peripheral-circuit via  13 - 3  is formed in the sixth dielectric interlayer  22  and fifth dielectric interlayer  19 . The opening is filled with a conductive material, e.g., a metal such as tungsten to form a third metal layer—second metal layer contact  23 . 
     Next, as shown in  FIGS. 15A  to  15 D, a conductive material such as AlCu or Cu is deposited on the structure shown in  FIGS. 14A  to  14 D to form a third metal layer  24 . For example, when AlCu or Cu is used for the third metal layer  24 , it is generally sandwiched between barrier metal layers. To do this, barrier metal layers may be formed under and on the third metal layer  24 . This also applies to other embodiments to be described below. Examples of the material of the barrier metal layer are Ti, TiN, Ta, TaN, and W. The third metal layer  24  is patterned to form the write word line  24 - 1  and an intra-peripheral-circuit interconnection  24 - 2 . 
     In this way, the magnetic random access memory according to the first embodiment can be formed. 
     (Second Embodiment) 
       FIG. 16  is a plan view showing the planar pattern of a magnetic random access memory according to a second embodiment of the present invention.  FIG. 17A  is a sectional view taken along a line A—A in FIG.  16 .  FIG. 17B  is a sectional view taken along a line B—B in FIG.  16 .  FIG. 17C  is a sectional view taken along a line C—C in FIG.  16 .  FIG. 17D  is a sectional view of the substrate contact portion of a peripheral circuit. 
     As shown in  FIGS. 16 and 17A  to  17 D, the magnetic random access memory of the second embodiment is different from the first embodiment in that a yoke layer  28  that covers the upper and side surfaces of a write word line  24 - 1  and the side surface of an MTJ element  18  to confine the magnetic field from the write word line  24 - 1  is formed. The yoke layer  28  of this embodiment is made of, e.g., a conductive magnetic material. Since the yoke layer  28  of this embodiment is formed from a conductive magnetic material, it is separated for each write word line  24 - 1 . Additionally, in this embodiment, a yoke layer  26  that covers the bottom and side surfaces of a bit line  13 - 1  is formed. 
     The magnetic random access memory according to the second embodiment has the yoke layer  28  that covers the upper and side surfaces of the write word line  24 - 1  and the side surface of the MTJ element  18 . For this reason, as compared to a structure without the yoke layer  28 , the magnetic field from the write word line  24 - 1  can be efficiently applied to the MTJ element  18 . 
     In addition, an adjacent unselected MTJ element  18  is hard to be influenced by the magnetic field from the selected write word line  24 - 1 . For this reason, the reliability related to, e.g., a data read can be improved. 
     Furthermore, since the yoke layer  26  that covers the bottom and side surfaces of the bit line  13 - 1  is formed, the magnetic field from the bit line  13 - 1  can be efficiently applied to the MTJ element in a data write mode. 
     The yoke layer  26  is not in contact with the yoke layer  28 . Since the yoke layer  26  is not in contact with the yoke layer  28 , for example, any interference between the magnetic field from the yoke layer  26  and that from the yoke layer  28  can advantageously be suppressed. 
     [First Manufacturing Method] 
     A first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention will be described next. 
       FIGS. 18A  to  31 D are sectional views showing the first method of manufacturing the magnetic random access memory according to the second embodiment of the present invention.  FIGS. 18A ,  19 A,  20 A,  21 A,  22 A,  23 A,  24 A,  25 A,  26 A,  27 A,  28 A,  29 A,  30 A, and  31 A correspond to the section shown in FIG.  17 A.  FIGS. 18B ,  19 B,  20 B,  21 B,  22 B,  23 B,  24 B,  25 B,  26 B,  27 B,  28 B,  29 B,  30 B, and  31 B correspond to the section shown in FIG.  17 B.  FIGS. 18C ,  19 C,  20 C,  21 C,  22 C,  23 C,  24 C,  25 C,  26 C,  27 C,  28 C,  29 C,  30 C, and  31 C correspond to the section shown in FIG.  17 C.  FIGS. 18D ,  19 D,  20 D,  21 D,  22 D,  23 D,  24 D,  25 D,  26 D,  27 D,  28 D,  29 D,  30 D, and  31 D correspond to the section shown in FIG.  17 D. 
     First, the structure shown in  FIGS. 18A  to  18 D is obtained by the manufacturing method described with reference to  FIGS. 3A  to  7 D. 
     Next, as shown in  FIGS. 19A  to  19 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 18A  to  18 D to form a fourth dielectric interlayer  12 . Second metal layer interconnection trenches  25  that reach contacts  11  are formed in the fourth dielectric interlayer  12 . In this embodiment, a bit line trench  25 - 1 , intracell via trench  25 - 2 , and intra-peripheral-circuit via trench  25 - 3  are formed. 
     As shown in  FIGS. 20A  to  20 D, a conductive or insulating yoke material is deposited on the structure shown in  FIGS. 19A  to  19 D to form the yoke layer  26 . In this embodiment, the conductive yoke layer  26  is exemplified. As a conductive yoke material, for example, an Ni—Fe alloy, Co—Fe—Ni alloy, Co—(Zr, Hf, Nb, Ta, Ti) film, or (Co, Fe, Ni)—(Si, B)—(P, Al, Me, Nb, Mn)-based amorphous material can be used. As an insulating yoke material, for example, insulating ferrite, (Fe, Co)—(B, Si, Hf, Zr, Sm, Ta, Al)—(F, O, N)-based metal-nonmetal nanogranular film can be used. Next, a conductive material, e.g., a metal such as tungsten is deposited on the conductive yoke layer  26  to form a second metal layer  13 . 
     As shown in  FIGS. 21A  to  21 D, the second metal layer  13  and conductive yoke layer  26  are subjected to, e.g., chemical mechanical polishing (CMP) to fill the bit line trench  25 - 1 , intracell via trench  25 - 2 , and intra-peripheral-circuit via trench  25 - 3  with the second metal layer and conductive yoke material. With this process, a bit line  13 - 1 , intracell via  13 - 2 , and intra-peripheral-circuit via  13 - 3  are formed. 
     As shown in  FIGS. 22A  to  22 D, a ferromagnetic material is sputtered on the structure shown in  FIGS. 21A  to  21 D to form a ferromagnetic layer  14 . Next, an insulating material is deposited on the ferromagnetic layer  14  to form an insulating layer  15 . Subsequently, a ferromagnetic material is sputtered on the insulating layer  15  to form a ferromagnetic layer  16 . Then, a mask material is deposited on the ferromagnetic layer  16  to form a mask layer  17 . The mask layer  17  is patterned into a shape corresponding to the layout pattern of the MTJ element. 
     As shown in  FIGS. 23A  to  23 D, the ferromagnetic layer  16 , insulating layer  15 , and ferromagnetic layer  14  are sequentially etched using the mask layer  17  as a mask. With this process, the MTJ element  18  having, e.g., a three-layered structure including the ferromagnetic layer  14 , insulating layer  15 , and ferromagnetic layer  16  is formed. In this embodiment, for example, the ferromagnetic layer  14  functions as a memory-layer in which the direction of spin changes in accordance with the write magnetic field. The insulating layer  15  functions as a tunnel barrier. The ferromagnetic layer  16  functions as a fixed-layer in which the direction of spin is fixed. 
     As shown in  FIGS. 24A  to  24 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 23A  to  23 D to form a fifth dielectric interlayer  19 . The fifth dielectric interlayer  19  is subjected to, e.g., chemical mechanical polishing (CMP) to expose the MTJ element  18 . Next, an opening that reaches the intracell via  13 - 2  is formed in the fifth dielectric interlayer  19 . The opening is filled with a conductive material, e.g., a metal such as tungsten to form an extra metal—second metal layer contact  20 . 
     As shown in  FIGS. 25A  to  25 D, a conductive material, e.g., a metal such as tungsten is deposited on the structure shown in  FIGS. 24A  to  24 D to form an extra metal layer  21 . 
     As shown in  FIGS. 26A  to  26 D, the extra metal layer  21  is patterned to form an intracell local interconnection  21 - 1 . 
     As shown in  FIGS. 27A  to  27 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 26A  to  26 D to form a sixth dielectric interlayer  22 . An opening that reaches the intra-peripheral-circuit via  13 - 3  is formed in the sixth dielectric interlayer  22  and fifth dielectric interlayer  19 . The opening is filled with a conductive material, e.g., a metal such as tungsten to form a third metal layer—second metal layer contact  23 . 
     As shown in  FIGS. 28A  to  28 D, a conductive material, e.g., AlCu or Cu is deposited on the structure shown in  FIGS. 27A  to  27 D to form a third metal layer  24 . Next, a conductive yoke material is deposited on the third metal layer  24  to form a conductive yoke layer  27 . As a material of the conductive yoke layer  27 , for example, an Ni—Fe alloy, Co—Fe—Ni alloy, Co—(Zr, Hf, Nb, Ta, Ti) film, or (Co, Fe, Ni)—(Si, B)—(P, Al, Mo, Nb, Mn)-based amorphous material can be used. 
     As shown in  FIGS. 29A  to  29 D, the conductive yoke layer  27 , third metal layer  24 , and sixth dielectric interlayer  22  are etched using a mask material (not shown) corresponding to the write word line pattern and intra-peripheral-circuit interconnection pattern as a mask. In addition, the fifth dielectric interlayer  19  is etched halfway. With this process, a write word line  24 - 1  and intra-peripheral-circuit interconnection  24 - 2  are formed. The reason why the fifth dielectric interlayer  19  is etched halfway is that the yoke layer  28  to be formed later need be brought close to, e.g., the bit line  13 - 1  as much as possible. The reason why the fifth dielectric interlayer is not etched until the bit line  13 - 1  is exposed is that the yoke layer  26  need be prevented from coming into contact with the yoke layer  28  to be formed later. 
     Next, as shown in  FIGS. 30A  to  30 D, a conductive yoke material is deposited on the structure shown in  FIGS. 29A  to  29 D to form the conductive yoke layer  28 . As a material of the conductive yoke layer  28 , for example, an Ni—Fe alloy, Co—Fe—Ni alloy, Co—(Zr, Hf, Nb, Ta, Ti) film, or (Co, Fe, Ni)—(Si, B)—(P, Al, Mo, Nb, Mn)-based amorphous material can be used, like the conductive yoke layer  27 . 
     As shown in  FIGS. 31A  to  31 D, the conductive yoke layer  28  is anisotropically etched using anisotropic etching, e.g., reactive ion etching (RIE) to leave the conductive yoke layer  28  on the side surfaces of the conductive yoke layer  27 , write word line  24 - 1  or intra-peripheral-circuit interconnection  24 - 2 , sixth dielectric interlayer  22 , and fifth dielectric interlayer  19 . 
     In this way, the magnetic random access memory according to the second embodiment can be formed. 
     [Second Manufacturing Method] 
     A second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention will be described next. 
       FIGS. 32A  to  41 D are sectional views showing the second method of manufacturing the magnetic random access memory according to the second embodiment of the present invention.  FIGS. 32A ,  33 A,  34 A,  35 A,  36 A,  37 A,  38 A,  39 A,  40 A, and  41 A correspond to the section shown in FIG.  17 A.  FIGS. 32B ,  33 B,  34 B,  35 B,  36 B,  37 B,  38 B,  39 B,  40 B, and  41 B correspond to the section shown in FIG.  17 B.  FIGS. 32C ,  33 C,  34 C,  35 C,  36 C,  37 C,  38 C,  39 C,  40 C, and  41 C correspond to the section shown in FIG.  17 C.  FIGS. 32D ,  33 D,  34 D,  35 D,  36 D,  37 D,  38 D,  39 D,  40 D, and  41 D correspond to the section shown in FIG.  17 D. 
     First, the structure shown in  FIGS. 32A  to  32 D is obtained by the manufacturing method described with reference to  FIGS. 3A  to  7 D and  FIGS. 19A  to  23 D. 
     Next, as shown in  FIGS. 33A  to  33 D, an insulating material, e.g., SiN is deposited on the structure shown in  FIGS. 32A  to  32 D to form a stopper layer  29 . Next, an insulating material, e.g., SiO 2  is deposited on the stopper layer  29  to form the fifth dielectric interlayer  19 . An example of the material of the stopper layer  29  is SiN. However, any other material that can ensure an etching selectivity ratio with respect to the fifth dielectric interlayer  19  can be used. 
     As shown in  FIGS. 34A  to  34 D, the fifth dielectric interlayer  19  and stopper layer  29  are subjected to, e.g., chemical mechanical polishing (CMP) to expose the MTJ element  18 . Next, an opening that reaches the intracell via  13 - 2  is formed in the fifth dielectric interlayer  19  and stopper layer  29 . The opening is filled with a conductive material, e.g., a metal such as tungsten to form the extra metal—second metal layer contact  20 . 
     As shown in  FIGS. 35A  to  35 D, a conductive material, e.g., a metal such as tungsten is deposited on the structure shown in  FIGS. 34A  to  34 D to form the extra metal layer  21 . As shown in  FIGS. 36A  to  36 D, the extra metal layer  21  is patterned to form the intracell local interconnection  21 - 1 . 
     As shown in  FIGS. 37A  to  37 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 36A  to  36 D to form a sixth dielectric interlayer  22 . An opening that reaches the intra-peripheral-circuit via  13 - 3  is formed in the sixth dielectric interlayer  22  and fifth dielectric interlayer  19 . The opening is filled with a conductive material, e.g., a metal such as tungsten to form the third metal layer—second metal layer contact  23 . 
     As shown in  FIGS. 38A  to  38 D, a conductive material, e.g., AlCu or Cu is deposited on the structure shown in  FIGS. 37A  to  37 D to form the third metal layer  24 . Next, a conductive yoke material is deposited on the third metal layer  24  to form the conductive yoke layer  27 . 
     As shown in  FIGS. 39A  to  39 D, the conductive yoke layer  27 , third metal layer  24 , sixth dielectric interlayer  22 , and fifth dielectric interlayer  19  are etched using a mask material (not shown) corresponding to the write word line pattern and intra-peripheral-circuit interconnection pattern as a mask, e.g., until the stopper layer  29  is exposed. With this process, the write word line  24 - 1  and intra-peripheral-circuit interconnection  24 - 2  are formed. 
     Next, as shown in  FIGS. 40A  to  40 D, a conductive yoke material is deposited on the structure shown in  FIGS. 39A  to  39 D to form the conductive yoke layer  28 . 
     As shown in  FIGS. 41A  to  41 D, the conductive yoke layer  28  is anisotropically etched using anisotropic etching, e.g., reactive ion etching (RIE) to leave the conductive yoke layer  28  on the side surfaces of the conductive yoke layer  27 , write word line  24 - 1  or intra-peripheral-circuit interconnection  24 - 2 , sixth dielectric interlayer  22 , and fifth dielectric interlayer  19 . 
     In this way, the magnetic random access memory according to the second embodiment can be formed. 
     [Third Manufacturing Method] 
     A third method of manufacturing the magnetic random access memory according to the second embodiment of the present invention will be described next. 
       FIGS. 42A  to  47 D are sectional views showing the third method of manufacturing the magnetic random access memory according to the second embodiment of the present invention.  FIGS. 42A ,  43 A,  44 A,  45 A,  46 A, and  47 A correspond to the section shown in FIG.  17 A.  FIGS. 42B ,  43 B,  44 B,  45 B,  46 B, and  47 B correspond to the section shown in FIG.  17 B.  FIGS. 42C ,  43 C,  44 C,  45 C,  46 C, and  47 C correspond to the section shown in FIG.  17 C.  FIGS. 42D ,  43 D,  44 D,  45 D,  46 D, and  47 D correspond to the section shown in FIG.  17 D. 
     First, the structure shown in  FIGS. 42A  to  42 D is obtained by the manufacturing method described with reference to  FIGS. 3A  to  7 D and  FIGS. 19A  to  27 D. 
     Next, as shown in  FIGS. 43A  to  43 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 42A  to  42 D to form a seventh dielectric interlayer  30 . Third layer metal interconnection trenches  31  are formed in the seventh dielectric interlayer  30 . With this process, a write word line trench  31 - 1  and intra-peripheral-circuit interconnection trench  31 - 2  are formed. 
     As shown in  FIGS. 44A  to  44 D, a conductive material, e.g., AlCu or Cu is deposited on the structure shown in  FIGS. 42A  to  42 D to form the third metal layer  24 . The third metal layer  24  is, e.g., etched back to bury the third metal layer  24  halfway in the write word line trench  31 - 1  and intra-peripheral-circuit interconnection trench  31 - 2 . A conductive yoke material is deposited on the third metal layer  24  and seventh dielectric interlayer  30  to form the conductive yoke layer  27 . The conductive yoke layer  27  is subjected to, e.g., chemical mechanical polishing (CMP) to bury it in the write word line trench  31 - 1  and intra-peripheral-circuit interconnection trench  31 - 2 . 
     As shown in  FIGS. 45A  to  45 D, the conductive yoke layer  27 , third metal layer  24 , seventh dielectric interlayer  30 , and sixth dielectric interlayer  22  are etched using a mask material (not shown) corresponding to the write word line pattern and intra-peripheral-circuit interconnection pattern as a mask. In addition, the fifth dielectric interlayer  19  is etched halfway. With this process, the write word line  24 - 1  and intra-peripheral-circuit interconnection  24 - 2  are formed. 
     As shown in  FIGS. 46A  to  46 D, the seventh dielectric interlayer  30  is, e.g., wet-etched to remove the seventh dielectric interlayer  30  that is present on the side surface of the conductive yoke layer  27 . With this process, a portion  32  where the side surface of the conductive yoke layer  27  is exposed is obtained. This process is executed as needed. 
     As shown in  FIGS. 47A  to  47 D, a conductive yoke material is deposited on the structure shown in  FIGS. 46A  to  46 D to form the conductive yoke layer  28 . The conductive yoke layer  28  is anisotropically etched using anisotropic etching, e.g., reactive ion etching (RIE) to leave the conductive yoke layer  28  on the side surfaces of the conductive yoke layer  27 , write word line  24 - 1  or intra-peripheral-circuit interconnection  24 - 2 , seventh dielectric interlayer  30 , sixth dielectric interlayer  22 , and fifth dielectric interlayer  19 . 
     In this way, the magnetic random access memory according to the second embodiment can be formed. 
     [Modification] 
     A modification to the magnetic random access memory according to the second embodiment of the present invention will be described next. 
       FIGS. 48A ,  48 B,  48 C, and  48 D are sectional views showing the modification to the magnetic random access memory according to the second embodiment of the present invention.  FIG. 48A  corresponds to the section shown in FIG.  17 A.  FIG. 48B  corresponds to the section shown in FIG.  17 B.  FIG. 48C  corresponds to the section shown in FIG.  17 C.  FIG. 48D  corresponds to the section shown in FIG.  17 D. 
     As shown in  FIGS. 48A  to  48 D, the conductive yoke layer  28  may be formed to cover the side surfaces of the write word line  24 - 1  and MTJ element  18 . 
     (Third Embodiment) 
       FIG. 49  is a plan view showing the planar pattern of a magnetic random access memory according to the third embodiment of the present invention.  FIG. 50A  is a sectional view taken along a line A—A in FIG.  49 .  FIG. 50B  is a sectional view taken along a line B—B in FIG.  49 .  FIG. 50C  is a sectional view taken along a line C—C in FIG.  49 .  FIG. 50D  is a sectional view of the substrate contact portion of a peripheral circuit. 
     As shown in  FIGS. 49 and 50A  to  50 D, the magnetic random access memory of the third embodiment is different from the second embodiment in that a yoke layer  34  is made of an insulating material. 
     When the yoke layer  34  is formed from an insulating material, an intracell local interconnection  21 - 1  may be in contact with the yoke layer  34 . This is advantageous in micropatterning a memory cell as compared to a memory having a conductive yoke layer. This is because, for example, in forming a write word line  24 - 1 , no mask alignment margin for, e.g., the intracell local interconnection  21 - 1  need be taken into consideration. 
     Additionally, since the intracell local interconnection  21 - 1  can be in contact with the yoke layer  34 , the intracell local interconnection  21 - 1  can be widened. For example, as in this embodiment, the width of the intracell local interconnection  21 - 1  can be equalized with that of the write word line  24 - 1 . When the width of the intracell local interconnection  21 - 1  can be increased, the resistance value of the intracell local interconnection  21 - 1  can be made small. 
     [Manufacturing Method] 
     A method of manufacturing the magnetic random access memory according to the third embodiment of the present invention will be described next. 
       FIGS. 51A  to  56 D are sectional views showing the method of manufacturing the magnetic random access memory according to the third embodiment of the present invention.  FIGS. 51A ,  52 A,  53 A,  54 A,  55 A, and  56 A correspond to the section shown in FIG.  50 A.  FIGS. 51B ,  52 B,  53 B,  54 B,  55 B, and  56 B correspond to the section shown in FIG.  50 B.  FIGS. 51C ,  52 C,  53 C,  54 C,  55 C, and  56 C correspond to the section shown in FIG.  50 C.  FIGS. 51D ,  52 D,  53 D,  54 D,  55 D, and  56 D correspond to the section shown in FIG.  50 D. 
     First, the structure shown in  FIGS. 51A  to  51 D is obtained by the manufacturing method described with reference to  FIGS. 3A  to  7 D and  FIGS. 19A  to  25 D. 
     Next, as shown in  FIGS. 52A  to  52 D, an extra metal layer  21  is etched to form a slit  33  in the extra metal layer  21 . The slit  33  extends in the same direction as that of, e.g., a bit line  13 - 1  and serves as an isolation region for sequentially isolating the intracell local interconnection  21 - 1  to be formed later along the direction in which, e.g., a read word line  4  extends. 
     As shown in  FIGS. 53A  to  53 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 52A  to  52 D to form a sixth dielectric interlayer  22 . An opening that reaches an intra-peripheral-circuit via  13 - 3  is formed in the sixth dielectric interlayer  22  and fifth dielectric interlayer  19 . The opening is filled with a conductive material, e.g., a metal such as tungsten to form a third metal layer—second metal layer contact  23 . 
     As shown in  FIGS. 54A  to  54 D, a conductive material, e.g., AlCu or Cu is deposited on the structure shown in  FIGS. 53A  to  53 D to form a third metal layer  24 . 
     As shown in  FIGS. 55A  to  55 D, the third metal layer  24 , sixth dielectric interlayer  22 , and extra metal layer  21  are etched using a mask material (not shown) corresponding to the write word line pattern and intra-peripheral-circuit interconnection pattern as a mask. In addition, the fifth dielectric interlayer  19  is etched halfway. With this process, the write word line  24 - 1 , the intra-peripheral-circuit interconnection  24 - 2 , and the intracell local interconnection  21 - 1  are formed. 
     Next, as shown in  FIGS. 56A  to  56 D, an insulating yoke material is deposited on the structure shown in  FIGS. 55A  to  55 D to form the insulating yoke layer  34 . As a material of the insulating yoke layer  34 , for example, an insulating ferrite, (Fe, Co)—(B, Si, Hf, Zr, Sm, Ta, Al)—(F, O, N)-based metal-nonmetal nanogranular film can be used. 
     In this way, the magnetic random access memory according to the third embodiment can be formed. 
     [First Modification] 
     A first modification to the magnetic random access memory according to the third embodiment of the present invention will be described next. 
       FIGS. 57A ,  57 B,  57 C, and  57 D are sectional views showing the first modification to the magnetic random access memory according to the third embodiment of the present invention.  FIG. 57A  corresponds to the section shown in FIG.  50 A.  FIG. 57B  corresponds to the section shown in FIG.  50 B.  FIG. 57C  corresponds to the section shown in FIG.  50 C.  FIG. 57D  corresponds to the section shown in FIG.  50 D. 
     As shown in  FIGS. 57A  to  57 D, the insulating yoke layer  34  may be formed to cover the side surfaces of the write word line  24 - 1  and MTJ element  18 . 
     [Second Modification] 
     A second modification to the magnetic random access memory according to the third embodiment of the present invention will be described next. 
       FIGS. 58A ,  58 B,  58 C, and  58 D are sectional views showing the second modification to the magnetic random access memory according to the third embodiment of the present invention.  FIG. 58A  corresponds to the section shown in FIG.  50 A.  FIG. 58B  corresponds to the section shown in FIG.  50 B.  FIG. 58C  corresponds to the section shown in FIG.  50 C.  FIG. 58D  corresponds to the section shown in FIG.  50 D. 
     As shown in  FIGS. 58A  to  58 D, the side surfaces of the write word line  24 - 1  and MTJ element  18  may be covered with the insulating yoke layer  34 , and the upper surface of the write word line  24 - 1  may be covered with a conductive yoke layer  27 . 
     (Fourth Embodiment) 
       FIGS. 59A  to  62 D are sectional views showing a method of manufacturing a magnetic random access memory according to a fourth embodiment of the present invention.  FIGS. 59A ,  60 A,  61 A, and  62 A correspond to the section shown in FIG.  17 A.  FIGS. 59B ,  60 B,  61 B, and  62 B correspond to the section shown in FIG.  17 B.  FIGS. 59C ,  60 C,  61 C, and  62 C correspond to the section shown in FIG.  17 C.  FIGS. 59D ,  60 D,  61 D, and  62 D correspond to the section shown in FIG.  17 D. 
     First, the structure shown in  FIGS. 59A  to  59 D is obtained by the manufacturing method described with reference to  FIGS. 3A  to  7 D and  FIGS. 19A  to  28 D. 
     As shown in  FIGS. 60A  to  60 D, a conductive yoke layer  27  and third metal layer  24  are etched using a mask material (not shown) corresponding to the write word line pattern and intra-peripheral-circuit interconnection pattern as a mask. With this process, a write word line  24 - 1  and intra-peripheral-circuit interconnection  24 - 2  are formed. 
     As shown in  FIGS. 61A  to  61 D, a mask layer  35  of, e.g., a photoresist is formed to cover the peripheral circuit portion. A sixth dielectric interlayer  22  and fifth dielectric interlayer  19  are etched halfway using the mask layer  35  and write word line  24 - 1 , and particularly, the yoke layer  27  in this embodiment as a mask. With this process, a recess used to form the yoke layer is formed only, e.g., at the memory cell portion where memory cells are integrated. After that, the mask layer  35  is removed in this embodiment. 
     As shown in  FIGS. 62A  to  62 D, a conductive yoke material is deposited on the exposed surface of the fifth dielectric interlayer  19 , on the exposed surface of the write word line  24 - 1 , on the exposed surface of the yoke layer  27 , and on the sixth dielectric interlayer  22  to form a conductive yoke layer  28 . Then, the conductive yoke layer  28  is left on the side surfaces of the conductive yoke layer  27 , write word line  24 - 1  or intra-peripheral-circuit interconnection  24 - 2 , sixth dielectric interlayer  22 , and fifth dielectric interlayer  19 . 
     In the magnetic random access memory formed in the above way, the recess used to form the yoke layer  28  can be formed only, e.g., at the memory cell array portion so that, e.g., the peripheral circuit portion can have satisfactory planarity. 
     If the peripheral circuit portion has satisfactory planarity, the interconnection process using the fourth metal layer, fifth metal layer, . . . above the third metal layer can easily be executed in, e.g., the peripheral circuit portion. 
     (Fifth Embodiment) 
       FIGS. 63A  to  69 D are sectional views showing a method of manufacturing a magnetic random access memory according to a fifth embodiment of the present invention.  FIGS. 63A ,  64 A,  65 A,  66 A,  67 A,  68 A, and  69 A correspond to the section shown in FIG.  17 A.  FIGS. 63B ,  64 B,  65 B,  66 B,  67 B,  68 B, and  69 B correspond to the section shown in FIG.  17 B.  FIGS. 63C ,  64 C,  65 C,  66 C,  67 C,  68 C, and  69 C correspond to the section shown in FIG.  17 C.  FIGS. 63D ,  64 D,  65 D,  66 D,  67 D,  68 D, and  69 D correspond to the section shown in FIG.  17 D. 
     First, the structure shown in  FIGS. 63A  to  63 D is obtained by the manufacturing method described with reference to  FIGS. 3A  to  7 D and  FIGS. 19A  to  25 D. 
     Next, as shown in  FIGS. 64A  to  64 D, an extra metal layer  21  is etched to form a slit  33  in the extra metal layer  21 . The slit  33  is similar to the slit  33  shown in  FIGS. 52A  to  52 D. The slit  33  extends in the same direction as that of, e.g., a bit line  13 - 1  and serves as an isolation region for sequentially isolating the intracell local interconnection  21 - 1  to be formed later along the direction in which, e.g., a read word line  4  extends. 
     As shown in  FIGS. 65A  to  65 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 64A  to  64 D to form a sixth dielectric interlayer  22 . An opening that reaches an intra-peripheral-circuit via  13 - 3  is formed in the sixth dielectric interlayer  22  and fifth dielectric interlayer  19 . The opening is filled with a conductive material, e.g., a metal such as tungsten to form a third metal layer—second metal layer contact  23 . 
     As shown in  FIGS. 66A  to  66 D, a conductive material, e.g., AlCu or Cu is deposited on the structure shown in  FIGS. 65A  to  65 D to form a third metal layer  24 . Next, a conductive yoke material is deposited on the third metal layer  24  to form a conductive yoke layer  27 . As a material of the conductive yoke layer  27 , for example, an Ni—Fe alloy, Co—Fe—Ni alloy, Co—(Zr, Hf, Nb, Ta, Ti) film, or (Co, Fe, Ni)—(Si, B)—(P, Al, Mo, Nb, Mn)-based amorphous material can be used. 
     As shown in  FIGS. 67A  to  67 D, the conductive yoke layer  27 , third metal layer  24 , sixth dielectric interlayer  22 , and extra metal layer  21  are etched using a mask material (not shown) corresponding to the write word line pattern and intra-peripheral-circuit interconnection pattern as a mask. In addition, the fifth dielectric interlayer  19  is etched halfway. With this process, the write word line  24 - 1 , the intra-peripheral-circuit interconnection  24 - 2 , and the intracell local interconnection  21 - 1  are formed. 
     As shown in  FIGS. 68A  to  68 D, an insulating material, e.g., SiO 2  is deposited on the structure shown in  FIGS. 67A  to  67 D to form an insulation layer  36 . The insulation layer  36  is anisotropically etched using anisotropic etching, e.g., reactive ion etching (RIE) to leave the insulation layer  36  on the side surfaces of the write word line  24 - 1 , intra-peripheral-circuit interconnection  24 - 2 , sixth dielectric interlayer  22 , intracell local interconnection  21 - 1 , and fifth dielectric interlayer  19 . A portion of the side surface of the conductive yoke layer  27  is exposed. 
     Next, as shown in  FIGS. 69A  to  69 D, a conductive yoke material is deposited on the structure shown in  FIGS. 68A  to  68 D to form the conductive yoke layer  28 . As a material of the conductive yoke layer  28 , for example, an Ni—Fe alloy, Co—Fe—Ni alloy, Co—(Zr, Hf, Nb, Ta, Ti) film, or (Co, Fe, Ni)—(Si, B)—(P, Al, Mo, Nb, Mn)-based amorphous material can be used, like the conductive yoke layer  27 . The conductive yoke layer  28  is anisotropically etched using anisotropic etching, e.g., reactive ion etching (RIE) to leave the conductive yoke layer  28  on the side surfaces of the conductive yoke layer  27  and the insulation layer  36 . 
     In the magnetic random access memory thus formed, even when the yoke layer formed on the side wall of the write word line  24 - 1  is formed using a conductive yoke material, the intracell local interconnection  21 - 1  can be patterned and formed simultaneously with the write word line  24 - 1 . For this reason, the intracell local interconnection  21 - 1  can have the same width as that of the write word line  24 - 1 , and the resistance value of the intracell local interconnection  21 - 1  can advantageously be decreased. 
     EXAMPLE OF MAGNETORESISTIVE ELEMENT 
     First Example 
     As described in the first to fifth embodiments, an MTJ element can be used as a magnetoresistive element. Several examples of an MTJ element will be described below. 
       FIG. 70A  is a sectional view showing the first example of an MTJ element. 
     As shown in  FIG. 70A , an antiferromagnetic layer  51 , ferromagnetic layer  52 , tunnel barrier layer  53 , ferromagnetic layer  54 , and protective layer  55  are sequentially formed on an underlying layer  50 . 
     In this example, the ferromagnetic layer  52  functions as a fixed-layer in which the direction of spin is fixed. The ferromagnetic layer  54  functions as a memory-layer in which the direction of spin can be changed. The antiferromagnetic layer  51  fixes the direction of spin in the ferromagnetic layer  52 . The direction of spin in the ferromagnetic layer  52  which functions as a fixed-layer, as in this example, may be fixed using, e.g., the antiferromagnetic layer  51 . 
     The underlying layer  50  makes it possible to easily form, e.g., the ferromagnetic layer or antiferromagnetic layer or protect the layer and is formed as needed. The protective layer  55  protects, e.g., the ferromagnetic layer or antiferromagnetic layer. The protective layer  55  is also formed, as needed, like the underlying layer  50 . Matters about the underlying layer  50  and protective layer  55  also apply to the second to fourth examples to be described below. 
     Examples of the material of the ferromagnetic layer  52  or  54  are as follows. 
     Fe, Co, Ni, or an alloy thereof 
     Magnetite with high spin polarization ratio 
     An oxide such as CrO 2  or RXMnO 3 -y (R: rare earth. X: Ca, Ba, Sr)
         Heusler alloy such as NiMnSb or PtMnSb       

     The ferromagnetic material  52  or  54  may contain a nonmagnetic element within a range in which the ferromagnetism is not lost. 
     Examples of a nonmagnetic element are as follows. 
     Ag, Cu, Au, Al, Mg, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Ir, W, Mo, and Nb 
     The ferromagnetic layer  52  or  54  has such a thickness that the ferromagnetic layer  52  or  54  does not become super-paramagnetic. More specifically, the ferromagnetic layer  52  or  54  is formed to a thickness of 0.4 nm or more. The thickness of the ferromagnetic layer  52  or  54  has no particular upper limit. However, the thickness of the ferromagnetic layer  52  or  54  is preferably, e.g., 100 nm or less from the viewpoint of formation of the MTJ element. 
     Examples of the material of the antiferromagnetic layer  51  are as follows. 
     Fe—Mn, Pt—Mn, Pt—Cr—Mn, Ni—Mn, Ir—Mn, NiO, and Fe 2 O 3    
     Examples of the material of the tunnel barrier layer  53  are as follows. 
     Al 2 O 3 , SiO 2 , MgO, AlN, Bi 2 O 3 , MgF 2 , CaF 2 , SrTiO 2 , and AlLaO 3    
     The material of the tunnel barrier layer  53  may contain at least one of oxygen, nitrogen, and fluorine within a range in which the tunnel barrier layer  53  does not lose, e.g., the insulting properties. Alternatively, at least one of oxygen, nitrogen, and fluorine may be omitted within a range in which the tunnel barrier layer  53  does not lose, e.g., the insulting properties. 
     The thickness of the tunnel barrier layer  53  is preferably as much as small but is not particularly limited. For example, the thickness of the tunnel barrier layer  53  is set to 10 nm or less from the viewpoint of formation of the MTJ element. 
     Second Example 
       FIG. 70B  is a sectional view showing the second example of an MTJ element. 
     The MTJ element of the second example is an MTJ element called a double-junction type. 
     As shown in  FIG. 70B , an antiferromagnetic layer  51 - 1 , ferromagnetic layer  52 - 1 , tunnel barrier layer  53 - 1 , ferromagnetic layer  54 , tunnel barrier layer  53 - 2 , ferromagnetic layer  52 - 2 , antiferromagnetic layer  51 - 2 , and protective layer  55  are sequentially formed on an underlying layer  50 . 
     In this example, the ferromagnetic layers  52 - 1  and  52 - 2  function as fixed-layers. The ferromagnetic layer  54  functions as a memory-layer. The antiferromagnetic layer  51 - 1  fixes the direction of spin in the ferromagnetic layer  52 - 1 . The antiferromagnetic layer  51 - 2  fixes the direction of spin in the ferromagnetic layer  52 - 2 . 
     The double-junction-type MTJ element as in this example can increase the ratio of a resistance value in a low resistance mode to that in a high resistance mode, i.e., so-called MR ratio (Magneto-Resistance ratio) as compared to, e.g., the MTJ element (single-junction-type) shown in FIG.  70 A. 
     Examples of the materials of the antiferromagnetic layers  51 - 1  and  51 - 2 , ferromagnetic layers  52 - 1 ,  52 - 2 , and  54 , and tunnel barrier layers  53 - 1  and  53 - 2  are the same as described in the first example. 
     Examples of the thicknesses of the ferromagnetic layers  52 - 1 ,  52 - 2 , and  54  are the same as described in the first example. 
     Examples of the materials and thicknesses of the tunnel barrier layers  53 - 1  and  53 - 2  are the same as described in the first example. 
     Third Example 
       FIG. 70C  is a sectional view showing the third example of an MTJ element. 
     As shown in  FIG. 70C , in the MTJ element of the third example, each of ferromagnetic layers  52  and  54  in the MTJ element of the first example has a stack structure of a ferromagnetic layer and nonmagnetic layer. An example of the stack structure is a three-layered structure of ferromagnetic layer/nonmagnetic layer/ferromagnetic layer. In this example, the ferromagnetic layer  52  has a three-layered structure of ferromagnetic layer  61 /nonmagnetic layer  62 /ferromagnetic layer  63 . The ferromagnetic layer  54  has a three-layered structure of ferromagnetic layer  64 /nonmagnetic layer  65 /ferromagnetic layer  66 . 
     Examples of the material of the ferromagnetic layers  61 ,  63 ,  64 , and  66  are the same as described in the first example. 
     Examples of the material of the nonmagnetic layers  62  and  65  are as follows. 
     Ru, Ir 
     Detailed examples of the three-layered structure of ferromagnetic layer/nonmagnetic layer/ferromagnetic layer are as follows. 
     Co/Ru/Co, Co/Ir/Co 
     Co—Fe/Ru/Co—Fe, Co—Fe/Ir/Co—Fe 
     When the ferromagnetic layer  52  that functions as a fixed-layer has a stack structure, e.g., a three-layered structure of ferromagnetic layer  61 /nonmagnetic layer  62 /ferromagnetic layer  63 , antiferromagnetic bond is preferably generated between the ferromagnetic layer  61  and the ferromagnetic layer  63  through the nonmagnetic layer  62 . In addition, an antiferromagnetic layer  51  is formed in contact with the three-layered structure. With this structure, the direction of spin in the ferromagnetic layer  52  and, more particularly, the ferromagnetic layer  63  functioning as a fixed-layer can be more firmly fixed. With this advantage, the ferromagnetic layer  52  and, more particularly, the ferromagnetic layer  63  is hardly affected by the current field. Hence, any unexpected reversal of the direction of spin in the ferromagnetic layer  52  that function as a fixed-layer can be suppressed. 
     Even when the ferromagnetic layer  54  that functions as a memory-layer has a stack structure, e.g., a three-layered structure of ferromagnetic layer  64 /nonmagnetic layer  65 /ferromagnetic layer  66 , antiferromagnetic bond is preferably generated between the ferromagnetic layer  64  and the ferromagnetic layer  66  through the nonmagnetic layer  65 . In this case, since the magnetic flux closes in the three-layered structure, any increase in switching field due to, e.g., the magnetic pole can be suppressed. As a result, even when the size of a memory cell or the size of an MTJ element is less than the submicron order, any increase in power consumption due to a current field by a diamagnetic field can advantageously be suppressed. 
     The ferromagnetic layer  54  that functions as a memory-layer may have a stack structure of a soft ferromagnetic layer and a ferromagnetic layer. A soft ferromagnetic layer means a layer whose direction of spin is more readily reversed as compared to, e.g., a ferromagnetic layer. 
     When the ferromagnetic layer  54  has a stack structure of a soft ferromagnetic layer and a ferromagnetic layer, the soft ferromagnetic layer is arranged on a side close to a current field line, e.g., a bit line. 
     This stack structure may also include a nonmagnetic layer. For example, as in this example, when a three-layered structure of ferromagnetic layer  64 /nonmagnetic layer  65 /ferromagnetic layer  66  is formed, e.g., the ferromagnetic layer  66  may be formed as a soft ferromagnetic layer. 
     In this example, the ferromagnetic layers  52  and  54  have stack structures, respectively. However, only the ferromagnetic layer  52  or ferromagnetic layer  54  may have a stack structure. 
     Fourth Example 
       FIG. 70D  is a sectional view showing the fourth example of an MTJ element. 
     As shown in  FIG. 70D , in the MTJ element of the fourth example, each of ferromagnetic layers  52 - 1 ,  54 , and  52 - 2  of the MTJ element of the second example has a stack structure described in the third example. 
     In this example, the ferromagnetic layer  52 - 1  has a three-layered structure of ferromagnetic layer  61 - 1 /nonmagnetic layer  62 - 1 /ferromagnetic layer  63 - 1 . The ferromagnetic layer  54  has a three-layered structure of ferromagnetic layer  64 /nonmagnetic layer  65 /ferromagnetic layer  66 . The ferromagnetic layer  52 - 2  has a three-layered structure of ferromagnetic layer  61 - 2 /nonmagnetic layer  62 - 2 /ferromagnetic layer  63 - 2 . 
     Examples of the material of the ferromagnetic layers  61 - 1 ,  61 - 2 ,  63 - 1 ,  63 - 2 ,  64 , and  66  are the same as described in the first example. 
     Examples of the material of the nonmagnetic layers  62 - 1 ,  62 - 2 , and  65  are the same as described in the third example. 
     In this example, all the ferromagnetic layers  52 - 1 ,  54 , and  52 - 2  have stack structures, respectively. However, only one of them may have a stack structure. 
     [Effects Obtained from Second to Fifth Embodiments] 
     In the second to fifth embodiments, a yoke layer that covers, e.g., at least the side surface of the write word line  24 - 1  and the side surface of the MTJ element  18  is arranged. Hence, as compared to a case wherein no yoke layer is formed, the magnetic field from the write word line  24 - 1  can be efficiently applied to the MTJ element  18 . 
     In addition, an adjacent unselected MTJ element  18  is hard to be influenced by the magnetic field from the selected write word line  24 - 1 . For this reason, the reliability related to, e.g., a data write can be improved. 
     Furthermore, according to the second to fifth embodiments, the following effects can be obtained as compared to a reference example. 
       FIGS. 71A and 71B  are side views of a magnetic random access memory of the reference example. 
     In this reference example, yoke layers are formed in, e.g., the magnetic random access memory shown in  FIG. 73 , as shown in  FIGS. 71A and 71B . In this reference example, the yoke layers include a conductive yoke layer  126  that covers the lower and side surfaces of a write word line  124 - 1  and a conductive yoke layer  128  that covers the upper and side surfaces of a bit line  113 - 1  and the side surface of an MTJ element  118 . 
     In the magnetic random access memory shown in  FIG. 73 , an intracell local interconnection  121 - 1  is formed above the write word line  124 - 1 . For this reason, a thickness t 1  of the intracell local interconnection  121 - 1  and a thickness t 2  of a dielectric interlayer which insulates the intracell local interconnection  121 - 1  from the write word line  124 - 1  are added between the MTJ element  118  and the write word line  124 - 1 . 
     When the yoke layer  128  is formed for such a magnetic random access memory, the distance from the memory-layer of the MTJ element  118  to the yoke layer  128  decreases. However, a distance D WWL-M  from the memory-layer of the MTJ element  118  to the yoke layer  126  increases. 
       FIGS. 72A and 72B  are side views of a magnetic random access memory according to the second to fifth embodiments. 
     As shown in  FIGS. 72A and 72B , in the magnetic random access memory according to the second to fifth embodiments, an intracell local interconnection  21 - 1  is formed below a write word line  24 - 1 . An MTJ element  18  is formed on a bit line  13 - 1 . More specifically, the bit line  13 - 1  is arranged under the MTJ element  18 . In addition, an upper surface Stop of the bit line  13 - 1  is flush with a lower surface Sbtm of the MTJ element  18 . For this reason, it is only necessary to set an insulating distance Diso between a yoke layer  28  which covers the upper and side surfaces of the write word line  24 - 1  and the side surface of the MTJ element  18  and a conductive yoke layer  26  which covers the bottom and side surfaces of the bit line  13 - 1 . 
     Hence, in the magnetic random access memory according to the second to fifth embodiments, the memory-layer of the MTJ element  18  can be made closer to the yoke layer  26 , as compared to the reference example. 
     In addition, in the magnetic random access memory according to the second to fifth embodiments, the distance D BL-M  from the memory-layer of the MTJ element  18  to the yoke layer  26  and the distance D WWL-M  from the memory-layer of the MTJ element  18  to the yoke layer  28  can substantially equal. When the distances D BL-M  and D WWL-M  can substantially equal, the magnetic field generated from the yoke layer  26  and that generated from the yoke layer  28  can be uniformly applied to the memory-layer. For this reason, for example, the magnetic field from the write word line  24 - 1  and the magnetic field from the bit line  13 - 1  can be more efficiently applied to the MTJ element  18 , as compared to the reference example. 
     In addition, as compared to the reference example, an adjacent unselected MTJ element  18  is hard to be influenced by the magnetic field from the selected write word line  24 - 1 . For this reason, the reliability related to, e.g., a data write can be further improved. 
     The first to fifth embodiments of the present invention have been described above. However, the present invention is not limited to these embodiments, and various changes and modifications can be made without departing from the sprit and scope of the present invention. 
     The embodiments can be independently practiced but they may be appropriately combined. 
     The embodiments incorporate inventions of various phases, and the inventions of various phases can be extracted by appropriately combining a plurality of components disclosed in the embodiments. 
     In the above embodiments, the description has been done on the basis of examples in which present invention is applied to a magnetic random access memory. However, the present invention also incorporates a semiconductor integrated circuit device incorporating the above-described magnetic random access memory, e.g., a processor or system LSI. 
     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.