Abstract:
A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit  200  including multiple integrated circuits  202 - 205  each having internal power supplies is contained in an enclosure  201 . Integrated circuits  202 - 205  are described showing how to make external connection to internal power supplies. Connections  208 - 212  are provided to the internal power supplies of each of devices  202 - 205 . Another embodiment  500  of the system provides for disablement of regulators in multiple integrated circuits  502, 503 , and  504  by another integrated circuit  501  for power consumption reduction. The method FIG.  6  includes providing devices and connecting the internal power supplies together. An integrated circuit  501  with a power supply  400  adapted to the system and method with additional circuitry  308, 404  and  402  for disabling a regulator  306  is described.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to integrated circuit devices and in particular to integrated circuit devices having internal power supplies. 
     BACKGROUND OF THE INVENTION 
     Integrated Circuit devices such as DRAM (Dynamic Random Access Memory) and Flash (electrically erasable/programmable non-volatile memory) typically require for operation a number of voltages for separate operations including storing, reading, and erasing data. These voltages are internally generated by using an externally supplied voltage source often referred to as V dd . 
     A conventional DRAM device may have a V pp  supply for providing a high voltage for driving a wordline above the V dd  level stored in a memory cell, a V dd /2 supply for driving the cell plate to a mid-rail potential, and a V bb  supply for providing a negative back bias potential to the memory cell substrate. 
     A conventional NAND Flash device may have pump circuits for generating V pass  for application to unselected wordlines in a selected block during page read operations, V pgm  for applying to selected wordlines in page program operations, and V ers  for applying to wordlines in a selected block during block erase operations. 
     These internal voltage supply circuits occupy significant chip area and increase the die size and cost, this is particularly the case if capacitive pump circuits are used which require large pump and reservoir capacitors. The voltage supply circuits may also limit performance. For example, in a NAND Flash device the V pgm  voltage must be pulsed and applied repeatedly to a wordline in alternation with verify read operations. The time that it takes to charge the wordline adds overhead to each program/verify read cycle and can extend the program time parameter t PROG  which is a critical factor in NAND Flash performance. 
     In some integrated circuit devices, for example LPDDR2 (Low-Power Double Data Rate 2) DRAM as described in JEDEC (Joint Electron Device Engineering Council) specification JESD209-2B, the number of banks that can be activated within a given time window depends of t FAW  (Four bank Activate Window) which is specified as 50 ns for the higher speed grades. Although commands to activate all 8 banks could be issued to the device within this period of time, the t FAW  restriction limits the current drive requirements on the internal V pp  generator, and perhaps other internal voltage generators as well, by forcing the user to activate a maximum of four banks in the rolling t FAW  window. This restriction allows a size of the V pp  generator to be reduced from that required for unrestricted bank activation, thereby saving die area and cost. 
     When a number of memory devices are combined to provide a larger memory subsystem, they are often connected to a common shared bus. In this case there may not be sufficient command bandwidth to exercise all devices to their maximum capabilities. For example, in the case of eight LPDDR2 DRAM devices connected to a shared command bus operating at 400 MHz, it is impossible to issue four bank activate commands to each device within a 50 ns t FAW  window. One command requires two edges of the clock or 2.5 ns. Therefore at least some of the devices will not be fully utilizing the capabilities of their internal V pp  generators. It is not practical for DRAM manufacturers to offer different variants of memory products with a range of internal voltage generator drive capabilities and optimized die size. Memory product manufacturers rely on high volume of standardized product to drive costs down. 
     SUMMARY OF THE INVENTION 
     The invention provides a method and apparatus for connecting the internal voltages of multiple integrated circuits together. This allows shared use of otherwise idle resources resulting in greater capacity and reduced size. The invention is adaptable to single or multiple voltage sharing. The apparatus includes an integrated circuit with a connection to the internal power supply from the external environment. Additional embodiments provide access to several internal supplies. The method includes the process of making access available and connecting multiple integrated circuits internal voltages and control. 
     An additional embodiment allows one integrated circuit to control the internal power supply of another similar integrated circuit. This is illustrated by the ability to disable the regulator in the power supply of the controlled integrated circuit resulting in reduced power consumption and more efficient allocation of resources. 
     The system includes multiple integrated circuits connected together sharing power supplies. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       Further features and advantages of the present invention will become apparent from the following detailed description, taken in combination with the appended drawings, in which: 
         FIG. 1  is a block diagram of a conventional MCP (Multi-Chip Package) enclosure; 
         FIG. 2  is a block diagram of an MCP enclosure containing embodiments of the invention; 
         FIG. 3  is a block diagram of a conventional power supply; 
         FIG. 4  is a block diagram of a switchable power supply suitable for a third embodiment of the invention; and 
         FIG. 5  is another block diagram of an MCP enclosure incorporating a third embodiment of the invention; and 
         FIG. 6  is a flowchart of the method of the invention. 
     
    
    
     It will be noted that throughout the appended drawings, like features are identified by like reference numerals. 
     DESCRIPTION OF EMBODIMENTS 
     Memory die may be stacked and packaged together on a single substrate to achieve higher volumetric efficiency. Interconnection between memory devices in the package and terminals on the package may be accomplished with wire bonds or TSVs (Through Silicon Via). U.S. patent application Ser. No. 12/757,540, filed Apr. 9, 2010, describes chip selection and bus configurations for stacked memory devices. As with discrete packaged memory devices, multiple die within a MCP (Multi-Chip Package) enclosure are often connected to the same bus. 
     Referring to  FIG. 1 , in a conventional configuration, assume that 4 LPDDR DRAM die having the t FAW  specification described hereinabove are packaged together in a single MCP  100 . 
     Address and command inputs on all four die are wired together and connected to MCP address/command terminals. Likewise, bidirectional databus terminals (DQ) are connected in common to each die. Separate chip enable pins (CE 1  . . . CE 4 ) allow commands to be directed towards individual LPDDR2 die within the MCP. Clocks are not specifically shown but are included as part of the address/command and data busses. Power supplies (V dd , V ss , V ddq , and V ssq ) are also provided in common to all four die. This configuration shares the same drawbacks as a board level memory subsystem comprising discrete individually packaged memory devices. Bank activation in each die is limited by the t FAW  specification and beyond a certain number of die there is insufficient command bandwidth to exercise each die to the t FAW  limit. 
     Referring to  FIG. 2 , in an embodiment of the invention  200  assume that 4 die having LPDDR2 functionality  202 ,  203 ,  204  and  205  all having the same t FAW  specification as the conventional MCP  100  are packaged together in a single MCP  201 . These die have been modified by the addition of a wire bond pad or TSV bump connection  212 ,  213 ,  214  and  215  respectively to the internal V pp  voltage supply via a common bus  207 . A second embodiment provides connections to other internal voltage supplies such as V bb  or V dd /2 in a similar manner. The result can be a reduction in the size of circuit components when all of die  202 ,  203 ,  204  and  205  power supplies are in parallel. 
     Within the MCP enclosure or encapsulation the internal V pp  supply nodes  212 ,  213 ,  214  and  215  for each of the die  202 ,  203 ,  204  and  205  are wired together to bus  207 . Assuming each of die  202 ,  203 ,  204  and  205  is capable of providing sufficient V pp  current to activate 4 banks within a 50 ns t FAW  window, the four die stack  200  can support 16 bank activations within the t FAW  window, regardless of the distribution of the 16 banks among the four die. This can result in significant increases in performance without any additional die area penalty for larger internal supplies. 
       FIG. 3  is a block diagram of a conventional V pp  pump circuit  300 . A capacitive pump circuit draws current from the V dd  supply and boosts the level to a potential higher than V dd . A simple form of the circuit can achieve a V pp  level close to double that of V dd . More complex circuits are known in the art for achieving voltage levels higher than 2×V dd . A V bb  pump (not shown) has a similar structure. 
     An oscillator generates  302  a clock signal to control the capacitive pump  304 . On each clock cycle, a quantity of charge is delivered to the output to increase the V pp  level. Often, a reservoir capacitor is connected to the output for holding the charge and attenuating a voltage step caused by dumping charge on each clock cycle such capacitors can become quite large and occupy substantial space on the integrated circuit chip. A regulator  306  senses the level of V pp  to determine when V pp  has reached the desired level. When this occurs the regulator  306  output goes low to disable the oscillator  302  and pump  304 . The V pp  supply can be enabled or disabled with the EN input signal. In a deep power down mode when data in the memory does not have to be maintained the EN input signal can be brought low to disable the regulator  306  directly and turn off the oscillator  302  and pump  304  with an AND gate  308 . In operation when the V pp  level is below the desired level all three blocks  302 ,  304  and  306  consume power. When V pp  reached the desired level only the regulator  306  consumes power. In the deep power down mode the regulator  306  is completely turned off by the EN input signal to save power. 
     In a third embodiment, a regulator in only one of the die is enabled while the remaining regulators are disabled. This can significantly reduce the power in self-refresh data retention mode which is particularly important in handheld portable devices such as cell phones. 
       FIG. 4  is a block diagram of a switchable power supply  400  suitable for the third embodiment of the invention. V pp  supply  400  has an additional input EN R    407  to enable regulator  306 . If EN R    407  is at a high level (1) the circuit functions identically to the  FIG. 3  V pp  supply. In this embodiment regulator  306  may be disabled by a low level signal (0) on EN R  input  407 . Input EN R    407  is connected to one input on AND gate  402  the result is disabling regulator  306  when the signal (0) is on EN R . Additionally, externally provided regulator input R IN    406  is connected through a multiplexor  404  to control oscillator  302  and pump  304 . V pp  supply  400  also provides the local regulator output on the R OUT  terminal  408 . 
     Referring to  FIG. 5  a third embodiment of the invention incorporating the power supply of  FIG. 4 . As in  FIG. 1  the internal V pp  supply nodes  212 ,  213 ,  214  and  215  for each of the die  501 ,  502 ,  503  and  504  are wired together to bus  207  in a MCP  500 . In this embodiment however, LPDDR2 die # 1   501  has an enabled regulator so as a result of a logic high (1)  511  or V dd  level applied to the EN R  input  512 , while LPDDR2 die # 2   502 , # 3   503 , and # 4   504  have disabled regulators as a result of a logic low (0) on lines  521 ,  531  and  541  respectively or V ss  level applied to the corresponding EN R  inputs  522 ,  532  and  542 . The regulator output R OUT    513  on die # 1  is connected to the regulator inputs  523 ,  533  and  543  R IN  on die # 2   502 , # 3   503 , and # 4   504  respectively. As a result only one regulator (the one on LPDDR2 die # 1   501 ) within MCP  500  is enabled and power consumption is reduced. As before, all V pp  pumps on dies  501 ,  502 ,  503  and  504  can be activated when necessary to meet the current drive requirements on V pp  as when multiple banks are activated within a short period of time. This technique can also be applied to other supplies in MCP DRAM such as the V bb  substrate bias supply. It can also be applied to internal supplies on NAND Flash devices in MCP configurations such as V prog  or V ers  charge pumps. 
     Pumped supplies such as V pp  can be ganged together without problem. In the case where each device has its own regulator enabled, due to variations from device to device each regulator may disable the pump at a slightly different voltage. Essentially the regulator with the highest threshold will determine the overall V pp  of the combined system. Since the regulator in a V pp  supply typically does not drain off excess charge to establish a voltage at exactly the threshold point, no power is wasted by having some variation in regulator threshold levels. 
       FIG. 6  is a flowchart of the method of the invention. As described above the first step is providing terminals on the individual memory devices connected to the internal power supply. In prior art devices these connections are inaccessible to other components. As described this method will work with such diverse devices as DRAM, flash memory including NAND flash, NOR flash, PCRAM (Phase Change Random Access Memory) and any memory element which includes an internal power supply. 
     The next step is connecting the terminals of the devices together allowing the devices to share power supplies. In the simplest embodiment as shown in  FIG. 1  ends. The same process can be continued to connect other voltages internal to the memory devices such supplies in MCP DRAM such as the V bb  substrate bias supply. It can also be applied to internal supplies on NAND Flash devices in MCP configurations such as V prog  or V ers  charge pumps. 
     The process continues in devices having internal regulators in their internal power supply. In such cases the devise can be provided with a regulator input and/or a regulator output connection. The regulator output connection of the first device is connected to the regulator input of at least one and frequently several devises. As described above this allow the first device to switch off and on the regulators of the other devices to save power and reduce heat buildup. 
     Although the figures show only sharing of V pp  supply, any combination of internal supplies or all of the internal supplies can be shared within an MCP enclosure to improve performance, reduce power consumption, and optimize the die area within each individual die. These techniques can be applied to DRAM, flash memory including NAND flash and NOR flash, as well as other forms of memory such as PCRAM (Phase Change Random Access Memory) and other emerging memory technologies.