Abstract:
A metal frame is provided with plural terminals that are respectively connected to a tuner, a video intermediate frequency circuit part, and a stereo demodulator. The frame is preferably divided bilaterally into two regions, with the tuner in a first region and the video intermediate frequency circuit part and the stereo demodulator in a second region. The various components are preferably connected in series, with a U-shaped geometrical layout on the metal frame.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a television tuner unit having: a tuner for frequency-converting a received television signal into an intermediate frequency signal; a video intermediate frequency circuit part for detecting the intermediate frequency signal and outputting a video signal and a sound signal; and a stereo demodulator for demodulating a composite signal outputted from the video intermediate frequency circuit part and outputting a stereo sound signal. 
   2. Description of the Prior Art 
     FIG. 2  is a plan view showing a circuit layout of a conventional television tuner unit (hereinafter simply referred to as a tuner unit). A rectangular metal frame  11  has opposite long sides, a first side  11   a  and a second side  11   b , and opposite short sides, a third side  11   c  and a fourth side  11   d . A connector  12  through which television signals are inputted is attached to the third side  11   c . The metal frame  11  is partitioned to first to third regions  11   e ,  11   f , and  11   g  in this order from the third side  11   c  toward the fourth side  11   d . In the regions  11   e ,  11   f , and  11   g , wiring boards (not shown) for forming circuits are respectively mounted. 
   In the first region  11   e , a tuner  13  is formed which frequency-converts a received television signal into an intermediate frequency signal. The tuner  13  has an antenna tuning circuit  13   a , a high-frequency amplifier circuit  13   b , an interstage tuning circuit  13   c , a composite IC (integrated circuit)  13   d , a resonance circuit  13   e , and an intermediate frequency tuning circuit  13   f , and the like. The high-frequency amplifier circuit  13   b  is configured with a variable gain amplifier, and the composite IC  13   d  is configured with a mixer transistor, an oscillator transistor, a PLL circuit for selecting channels, and the like (not shown). The resonance circuit  13   e  is coupled to the oscillator transistor within the composite IC  13   d  to make up an oscillator. 
   In the second region  11   f , a video intermediate frequency circuit part  14  is formed which detects an intermediate frequency signal and outputs a composite signal of a video signal, a sound signal, and stereo, and generates an AGC voltage. The video intermediate frequency circuit part  14  has a SAW filter  14   a , a video intermediate frequency IC  14   b  including a video detector and an intermediate frequency amplifier (not shown), a voltage controlled oscillator  14   c , a trap circuit  14   d , and the like. The voltage controlled oscillator  14   c  is used to detect video. 
   In the third region  11   g , a stereo demodulator  15  is formed which outputs a stereo sound signal from a composite signal outputted from the video intermediate frequency circuit part  14 . A major portion of the stereo demodulator  15  is configured with integrated circuits. 
   The first side  11   a  is provided with plural terminals  16  that are respectively connected to the tuner  13 , the video intermediate frequency circuit part  14 , and the stereo demodulator  15 . When the tuner unit is mounted on a mother board (not shown) on which television set main circuits are formed, the terminals  16  are inserted in the mother board and connected to the circuits. 
   The first side  11   a  corresponding to the first region  11   e  is provided with terminals related to the operation of the tuner  13  such as an AGC voltage input terminal (AGC)  16   a , a PLL circuit address terminal (AS)  16   b , a clock terminal (CL)  16   c , a data terminal (D)  16   d , a power terminal (B)  16   e , a tuning voltage source terminal (TU)  16   f , and the like. 
   The AGC terminal  16   a  is connected to the high-frequency amplifier circuit  13   b ; the address terminal  16   b , clock terminal  16   c , and data terminal  16   d  are connected to the composite IC  13   d ; the power terminal  16   e  is connected to the high-frequency amplifier circuit  13   b  and the composite IC  13   d ; and the tuning voltage source terminal  16   f  is connected to the composite IC  13   d.    
   The first side  11   a  corresponding to the second region  11   f  is provided with terminals related to the operation of the video intermediate frequency circuit part  14  such as a power terminal (B)  16   g , an AGC voltage output terminal (AGC)  16   h , a video signal terminal (V)  16   i , a sound signal terminal (A)  16   j , and the like. The power terminal  16   g  and the AGC voltage output terminal  16   h  are connected to the video intermediate frequency IC  14   b , and the video signal terminal  16   i  and the sound signal terminal  16   j  are connected to the trap circuit  14   d.    
   The first side  11   a  corresponding to the third, region  11   g  is provided with a power terminal (B)  16   k , a right sound signal terminal (R)  16   l , and a left sound signal terminal (L)  16   m  that are connected to the stereo demodulator  15 . 
   From a power supply part of the television set body, a power supply voltage is applied to the three power terminals  16   e ,  16   g , and  16   k  through which it is supplied to corresponding circuits. This prevents a power supply line within the tuner unit from becoming long. Also to the tuning voltage source terminal  16   f , a voltage (30 V) is supplied from the power supply part of the television set body. This voltage serves as a voltage source for generating a tuning voltage for selecting a channel, and the tuning voltage is set based on a signal related to channel selection, inputted to the address terminal  16   b , clock terminal  16   c , and data terminal  16   d . The set tuning voltage is supplied to the antenna tuning circuit  13   a  and the interstage tuning circuit  13   c.    
   A video signal and a sound signal of a selected channel are outputted to the video signal terminal  16   i  and the sound signal terminal  16   j , respectively. For stereo broadcasting, a stereo sound signal is outputted to the right sound signal terminal (R)  16   l  and the left sound signal terminal (L)  16   m . An AGC voltage outputted to the AGC voltage output terminal  16   h  is inputted to the AGC voltage input terminal  16   a  again via the mother board and supplied to the high-frequency amplifier circuit  13   b.    
   With the structure of conventional tuner units, circuits (tuner, video intermediate frequency circuit part, and stereo demodulator) are disposed in the horizontally extending region, the first region to third region, increasing a mounting area on a mother board of the television set body. Also, the three power terminals are provided because of the long disposition of the circuits, increasing the number of terminals. Moreover, the two AGC terminals are provided to supply an AGC voltage generated in the video intermediate frequency circuit part to the high-frequency amplifier, increasing the number of terminals. 
   SUMMARY OF THE INVENTION 
   This disclosure teaches the construction of a television tuner unit that requires reduced mounting area on a mother board of a television set body and fewer terminals for connecting with the mother board. 
   In one embodiment, the television tuner unit includes: a tuner for frequency-converting a received television signal into an intermediate frequency signal; a video intermediate frequency circuit part for detecting the intermediate frequency signal and outputting a video signal and a sound signal; a stereo demodulator for demodulating a composite signal outputted from the video intermediate frequency circuit part and outputting a stereo sound signal; and a metal frame having four sides and storing the tuner, the video intermediate frequency circuit part, and the stereo demodulator therein. The components of the television tuner unit are preferably arranged in a geometric layout that that allows sequential processing elements on the metal frame to form a U-shaped signal path. 
   In a preferred embodiment of the television tuner unit, a first side of the metal frame is provided with plural terminals that are respectively connected to the tuner, the video intermediate frequency circuit part, and the stereo demodulator. The tuner is disposed in a first of two partitioned regions of the metal frame; a connector for inputting the television signal is attached to the first partitioned region. The stereo demodulator and the video intermediate frequency circuit part are disposed in the second partitioned region. The stereo demodulator is disposed in a first region of the second partitioned region, and the video intermediate frequency circuit part is disposed in a second region of the second partitioned region. 
   One of the plural-terminals is a power terminal through which a power supply voltage is supplied from the outside, and the power supply voltage is supplied from the power terminal to the tuner, the video intermediate frequency circuit part, and the stereo demodulator. 
   The video intermediate frequency circuit part outputs an AGC voltage, the tuner is provided with a variable gain amplifier, and the AGC voltage is inputted to the variable gain amplifier within the metal frame. 
   Of the plural terminals, a stereo sound terminal for outputting the stereo sound signal is provided in the first region, and a video terminal for outputting the video signal and a sound terminal for outputting the sound signal are provided in the second region. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Preferred embodiments of the present invention will be described in detail based on the followings, wherein: 
       FIG. 1  is a plan view showing a circuit layout of the television tuner unit of the present invention; and 
       FIG. 2  is a plan view showing a circuit layout of a conventional television tuner unit. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  is a plan view showing a circuit layout of one version of a television tuner unit, hereinafter simply referred to as a tuner unit. A rectangular metal frame  1  has one pair of opposite sides, a first side  1   a  and a second side  1   b , and another pair of opposite sides, a third side  1   c  and a fourth side  1   d . A connector  2  through which television signals are inputted is attached at the third side  1   c . A wiring board (not shown) for forming circuits is stored within the metal frame  1 . The inside of the metal frame  1  is halved to a first partitioned region  1   e  at the second side  1   b  and a second partitioned region if at the first side  1   a  opposite to the second side  1   b , and the second partitioned region  1   f  is halved to a first region  1   g  at the third side  1   c  and a second region  1   h  at the fourth side  1   d.    
   A tuner  3  for frequency-converting a received television signal into an intermediate signal is formed on a wiring board in the first partitioned region  1   e . The tuner  3  has an antenna tuning circuit  3   a , a high-frequency amplifier circuit  3   b , an interstage tuning circuit  3   c , a composite IC (integrated circuit)  3   d , a resonance circuit  3   e , and an intermediate frequency tuning circuit  3   f , and the like. The high-frequency amplifier circuit  3   b  is configured with a variable gain amplifier, and the composite IC  3   d  is configured with a mixer transistor, an oscillator transistor, a PLL circuit for selecting channels, and the like. The resonance circuit  3   e  is coupled to the oscillator transistor within the composite IC  3   d  to make up an oscillator. 
   In the second region  1   h  in the second partitioned region  1   f , a video intermediate frequency circuit part  4  is formed which detects an intermediate frequency signal and outputs a composite signal of a video signal, a sound signal, and stereo, and generates an AGC voltage. The video intermediate frequency circuit part  4  has a SAW filter  4   a , a video intermediate frequency IC  4   b  including a video detector and an intermediate frequency amplifier (not shown), a voltage controlled oscillator  4   c , a trap circuit  4   d , and the like. The voltage controlled oscillator  4   c  is coupled to a video detector within the video intermediate frequency circuit part  4 . 
   In the first region  1   g  in the second partitioned region  1   f , a stereo demodulator  5  is formed which outputs a stereo sound signal from a composite signal outputted from the video intermediate frequency circuit part  4 . The major portion of the stereo demodulator  5  is configured with integrated circuits. 
   The first side  1   a  is provided with plural terminals  6  that are respectively connected to the tuner  3 , the video intermediate frequency circuit part  4 , and the stereo demodulator  5 . When the tuner unit is mounted on. a mother board (not shown) on which television set main circuits are formed, the terminals  6  are inserted in the mother board and connected to the circuits on the mother board. 
   The first side  1   a  corresponding to the first region  1   g  is provided with a right sound signal terminal (R)  6   a  and a left sound signal terminal (L)  6   b  that are connected to the stereo demodulator  5 , and an address terminal (AS)  6   c  for PLL circuits related to the operation of the tuner, a clock terminal (CL)  6   d , a data terminal (D)  6   e , and the like. 
   The first side  1   a  corresponding to the second area  1   h  is provided with a power terminal (B)  6   f , a tuning voltage source terminal (TU)  6   g  related to the operation of the tuner  3 , a video signal terminal (V)  6   h  related to the operation of the video intermediate frequency circuit part  4 , a sound signal terminal (A)  6   i , and the like. Of the above terminals, the power terminal  6   f  and the tuning voltage source terminal  6   g  may be provided at the first side  1   a  corresponding to the first region  1   g.    
   The address terminal  6   c , the clock terminal  6   d , and the data terminal  6   e  are connected to the composite IC  3   d , and the power terminal  6   f  is connected to the high-frequency amplifier circuit  3   b , the composite IC  3   d , the video intermediate frequency IC  4   b , and the stereo demodulator  5 . The tuning voltage source terminal  6   g  is connected to the composite IC  3   d . The video signal terminal  6   h  and the sound signal terminal  6   i  are connected to the trap circuit  4   d.    
   A cover (not shown) covering the partitioned regions  1   e  and  1   f  of the metal frame  1  is installed in the metal frame  1  and electromagnetically shielded. 
   From a power supply part of the television set body, a power supply voltage (5 V) is applied to the power terminal  6   f  through which it is supplied to the high-frequency amplifier circuit  3   b , the composite IC  3   d , the video intermediate frequency IC  4   b , and the stereo demodulator  5 . Also to the tuning voltage source terminal  6   g , a voltage (30 V) is supplied from the power supply part of the television set body. This voltage serves as a voltage source for generating a tuning voltage for selecting a channel, and the tuning voltage is set based on a signal related to channel selection, inputted to the address terminal  6   c , clock terminal  6   d , and data terminal  6   e . The set tuning voltage is supplied to the antenna tuning circuit  3   a , the interstage tuning circuit  3   c , the resonance circuit  3   e , and the like. 
   In the above configuration, a television signal inputted from the connector  2  is frequency-converted into an intermediate signal by the tuner  3  disposed in the first partitioned region  1   e , and the intermediate signal is processed by the video intermediate frequency circuit part  4  disposed in the second region  1   h  to output a video signal, a sound signal, a composite signal and an AGC voltage. The video signal and the sound signal are outputted to the video signal terminal  6   h  and the sound signal terminal  6   i , respectively. The outputted AGC voltage is supplied to the high-frequency amplifier circuit  3   b  through a wiring board. For stereo broadcasting, the composite signal is demodulated by the stereo demodulator  5  disposed in the first region to output a stereo sound signal to the right sound signal terminal (R)  6   a  and the left sound signal terminal (L)  6   b.    
   Since the first partitioned region  1   e  in which the tuner  3  is disposed faces the second partitioned region  1   f —including the second region  1   h  in which the video intermediate frequency circuit part  4  is disposed, and the first region  1   g  in which the stereo demodulator  5  is disposed—signals processed in the circuit parts flow within the metal frame in the shape of the letter U as shown by the arrows in the drawing. In one implementation of the tuner unit, the circuit connections are designed to exploit this geometry so that little or no interference occurs among the circuit parts. Since the first side  1   a  at which the terminals  6  are provided is shortened for the reason described above, a mounting area on the mother board is reduced. Also, since the shortened first side  1   a  reduces distances between the circuit parts, one power terminal preferably suffices for the supply of a power supply voltage, and the AGC terminals can be omitted to reduce the number of terminals. 
   As has been described above, according to the present invention, the first side of the metal frame is provided with the plural terminals that are connected to the tuner, the video intermediate frequency circuit part, and the stereo demodulator. The tuner is disposed in the first partitioned region adjacent to the second side of the metal frame. The connector for inputting the television signal is attached to the first partitioned region on the third side of the metal frame. The stereo demodulator and the video intermediate frequency circuit part are disposed in the second partitioned region, near the first side of the metal frame. With this construction, the first side at which the terminals are provided is shortened, so that a mounting area on the mother board of the television set body is reduced. 
   The stereo demodulator is disposed in the first region adjacent to the third side in the second partitioned region and the video intermediate frequency circuit part is disposed in the second region adjacent to the fourth side in the second partitioned region. With this construction, signals processed in the circuit parts flow within the metal frame in the shape of the letter U. 
   One of the terminals is a power terminal to which a power supply voltage is supplied from the outside. From the power terminal, the power supply voltage is supplied to the-video intermediate frequency circuit part and the stereo demodulator. With this construction, only one power terminal is preferably required, thereby reducing the total number of terminals. 
   The video intermediate frequency circuit part preferably outputs an AGC voltage, the tuner includes a variable gain amplifier, and the AGC voltage is inputted to the variable gain amplifier. With this construction, an AGC voltage terminal is not required, contributing to reduction in the number of terminals. 
   Of the plural terminals, a stereo sound terminal for outputting the stereo sound signal is provided at the first side of the metal frame in the first region, and a video terminal for outputting the video signal and a sound terminal for outputting the sound signal are provided at the first side of the metal frame in the second region. With this construction, the stereo sound signal, video signal, and sound signal can be outputted with a minimum distance between their output terminals.