Abstract:
A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.

Description:
BACKGROUND 
       [0001]    The subject matter of this disclosure relates generally to electronic gate drive circuits and more particularly to a system and method for providing a high speed, low loss gate drive circuit for semiconductor switches such as, without limitation, metal oxide semiconductor field effect transistor (MOSFET) switches, insulated gate bipolar transistor (IGBT) switches, and thyristor switches. 
         [0002]    Turn-on and turn-off speeds of some types of semiconductor switches such as MOSFET switches and IGBT switches are disadvantageously limited by R-C circuit elements when employed in conventional voltage source gate drive circuits. Such voltage source gate drive circuits further suffer from lost gate charge. 
         [0003]    As shown in  FIG. 1 , a conventional gate driver circuit  10  is typically implemented in an IC that consists of a pair of N and P-channel low voltage MOSFETs. When the control signal Vsig turns on the upper P-channel MOSFET, a charging current goes from Vc through a gate resistor Rg, internal gate mesh resistance Rg_i, to charge up the gate input capacitance, C ISS (=C gs +C gd ), of the power switch, SW, causing it turn on. When the control signal Vsig turns off the P-channel switch and turns on the lower N-channel switch, a discharging current discharges the input capacitance thereof and the SW is turned off. 
         [0004]    Although the conventional gate driver ICs are easy to use, they usually suffer from two major issues. One issue is related to the gate driver power losses and the other is related to the operation modes of the power switch they drive. Since the resistance is in the charging and discharging path the gate driver loses approximately twice the energy stored in the power switch&#39;s input capacitance each time the switch goes through an on and off cycle. Therefore the gate driver power loss is simply proportional to the operation frequency. Nevertheless high frequency operation provides fast transient response, small component size and superior power density. 
         [0005]    There is a steady trend to increase converters&#39; switching frequency continuously over the past decades. The gate driver loss becomes a limiting factor when the operation frequency enters MHz region. Thanks to the great demand on the computer and telecommunication power converters, significant efforts have been made to find innovative ways to reduce the gate driver losses. A fair amount of reference papers and patents can be found in literature, such as Steigerwald, Robert L. (Burnt Hills, N.Y.) U.S. Pat. No. 5,010,261 , “Lossless gate driver circuit for a high frequency converter,” Maksimovic, D.; “ A MOS gate drive with resonant transitions,” IEEE PESC &#39;91 Record., Page(s): 527-532, Yuhui Chen; etc. “A resonant MOSFET gate driver with efficient energy recovery,” IEEE Transactions on Power Electronics, Volume: 19 , Issue: 2, 2004 , Page(s): 470-477, de Vries, I. D.; “A resonant power MOSFET/IGBT gate driver,” IEEE APEC 2002. Page(s): 179-185 vol. 1, Faye, Li, U.S. Pat. No. 6,650,169, “Gate driver apparatus having an energy recovering circuit,” Inoshita, Ryousuke (Nishikamo-gun, JP), U.S. Pat. No. 7,091,753 ,“Gate driving circuit,” Omura, Ichiro (Yokohama, JP), U.S. Pat. No. 7,459,945, “Gate driving circuit and gate driving method of power MOSFET,” Yang, Zhihua (Kingston, Calif.), Liu, Yan-fei (Kingston, Calif.), U.S. Pat. No. 7,612,602, “Resonant gate drive circuits,” etc., to name a few. 
         [0006]    The above mentioned references mostly achieve the goal of lowering gate driver losses. They, however, lack a systematic approach to deal with the issues associated with the power switch operation modes where the effects of parasitic components as well as transient and extreme operating conditions are important. 
         [0007]      FIG. 2  shows a half-bridge model  20  with important parasitic components included. The half-bridge configuration is widely used in applications such as high power hard or soft switching, high frequency low voltage synchronous rectifier power supplies, and soft switching resonant converters. It also represents a so-called clamped inductive switching model where most MOSFET transistors and high speed drive circuit work in that operating mode. 
         [0008]    The turn-off procedure of the power switches can be roughly categorized into four time intervals: 1) turn-off delay interval where C ISS  is discharged from its initial value to the Miller plateau level; 2) Miller plateau interval where the drain-to-source voltage rises from I D R DS(on)  to the final V DS(off)  level clamped by the body diode of the complementary switch and the gate current is strictly discharging C gd ; 3) linear interval where the gate voltage resumes falling from V GS,Miller  to V th  and the drain current of the power switch decreases following the declining of gate-to-source voltage; 4) fully off interval where the C ISS  is fully discharged. 
         [0009]    The turn-on procedure is back tracking the turn-off steps. It is intuitively obvious that switching losses exist due to high current and high voltage being present in the power device simultaneously for a short period corresponding to the Miller plateau interval when the drain voltage goes through its switching transient and linear interval when the drain current changes responding to the change in the gate voltage. It becomes essential to shorten these two intervals to reduce the switching losses of the power switch. 
         [0010]    In practical applications, the effects of parasitic components and dv/dt limits have to be taken into account since the shapes of the current and voltage, as well as the switching times during the switching procedure are altered significantly when the parasitic inductive components come into play. The dv/dt limit of the power switch sets the up speed limit of the switching transient time. The dv/dt limit describes an unintentional turn-on phenomenon caused by the current flowing through the gate-drain capacitor and generating a positive gate-to-source voltage when the drain-to-source voltage rises rapidly. Since the turn-on threshold voltage V th  changes with an approximately −7 mV/° C. temperature coefficient, MOSFET transistors are more susceptible to dv/dt when operating at elevated temperature. Therefore the effect of high junction temperature must be taken into account. 
         [0011]    As discussed herein, the parasitic inductive components alter the current and voltage waveforms that exhibit a profound effect on switching performance. The most important parasitic inductive components are the source inductance L S  and drain inductance L D  as shown in  FIG. 2 . The source inductance L S  not only causes the oscillatory spikes observed in most gate drive circuit, it also shows a negative feedback effect whenever the drain current of the device is changing rapidly. This feedback mechanism establishes a delicate balance of gate current and drain di/dt. The drain inductance L D  on the other hand acts as a beneficial turn-on snubber but produces an overshoot in the drain-to-source and an increase in turn-off switching losses. 
         [0012]    To further improve gate driver performance, it is important to recognize that gate driver turn-off capability has more profound impact on the power device switching losses, dv/dt limit and di/dt EMI performance than the turn-on characteristic does, especially in the typical application shown in  FIG. 2 . In the hard switching case the turn-on speed is usually limited by the turn-off, or reverse recovery speed of the diode, not by the strength of the gate drive circuit. Therefore, it is beneficial to match the diode switching characteristics. 
         [0013]    In a zero-voltage-switching case, the Miller effect is not present since the drain-to-source voltage is practically zero when the gate is turned-on, or the turn-on of power switch starts with the turn-off of the other complementary power switch. The turn-off speed of the power MOSFET on the other side depends almost solely on the gate drive circuit. The gate driver circuit, however, is required to handle the maximum dv/dt that can occur under worst case conditions; for example, most resonant and soft switching converters can force a dv/dt across the power switch right after its turn-off instance due to the power stage resonant components. 
         [0014]    It would be both advantageous and beneficial to provide a high speed, low loss gate drive circuit that overcomes the foregoing disadvantages generally associated with conventional voltage source gate drive circuits. 
       SUMMARY 
       [0015]    The embodiments of the present invention described herein provide a systematic approach for driving a power semiconductor switching device of a high frequency converter in a new and improved high speed low loss gate driver circuit. The new gate driver circuit comprises a full bridge configuration with an inductor connected between the mid points of the bridge. Two capacitors, Cpos and Cneg, connected in series, are coupled into the DC link of the bridge with a gate DC power supply Vc as an input. The low voltage switches are controlled in way that the gate driver circuit provides a programmable magnitude of the discharge current to turn the power switch device off fast enough to reduce turn-off switching loss and keep voltage overshoot in a safe limit A negative voltage bias is applied to the gate to maximize the dv/dt immunity for the power MOSFET when it is in an off state. The gate driver circuit provides a tunable turn-on current to match switching characteristics of other power devices used in a practical application. Furthermore, the gate driver circuit recovers turn-on/off gate energies stored in the input capacitance of the power switch to ensure a high frequency operation. 
     
    
     
       BRIEF DESCRIPTION 
         [0016]    The above and further features and advantages of the present invention will become apparent when reading the detailed description of the preferred embodiments with the accompanying drawings in which: 
           [0017]      FIG. 1  is a conventional gate driver schematic diagram 
           [0018]      FIG. 2  is a schematic diagram of a half-bridge model with parasitic components; 
           [0019]      FIG. 3  is a circuit diagram of a gate driver circuit according to a preferred first embodiment of the present invention; 
           [0020]      FIG. 4  is a topological stages showing a preferred operation of the preferred first embodiment of the present invention; 
           [0021]      FIG. 5  is a timing diagram according to one embodiment of the present invention; 
           [0022]      FIG. 6  is an exemplary scheme of duty ratio control according to one embodiment of the present invention; 
           [0023]      FIG. 7  is a circuit diagram showing the gate driver circuits used in a half-bridge configuration; 
           [0024]      FIG. 8  is a circuit diagram according to a second embodiment of the invention; 
           [0025]      FIG. 9  is a circuit diagram according to a third embodiment of the invention; and 
           [0026]      FIG. 10  is a circuit diagram according to a fourth embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    The embodiments of the present invention described herein are directed to a new gate driver scheme that controls power semiconductor switches with high performance. More specifically, an embodied gate driver circuit provides a fast turn-off transient with reduced power switching losses and a controllable overshoot. The turn-on procedure matches switching characteristics of other power component in the power stage and maximizes dv/dt immunity with a negative voltage clamped to the gate when it is in an off state. Meanwhile, the gate driver losses are kept low to ensure a higher switching frequency operation. 
         [0028]      FIG. 3  is a circuit diagram of a gate driver circuit  30  according to a preferred first embodiment of the present invention. As shown in  FIG. 3 , two capacitors  21 ,  22  are connected in series forming a voltage divider. The voltage divider ratio could be simply determined by a high resistive resistor divider connected in parallel with the capacitor pair. These two capacitors  21 ,  22  preferably have a low ESR (equivalent series resistance) and a low ESL (equivalent series inductance) with a compact size, such as SM (surface mount) ceramic capacitors. The SM capacitor Cneg  22  and the low voltage MOSFET S 3  are arranged closely both physically and electrically so that a very small loop area possible is formed with the gate input capacitance of the power switch to maximize the dv/dt immunity. The loop area formed by MOSFET S 4 , Lg, gate input capacitance and Cneg is less important in the electromagnetic susceptibility point of view, but it is favorable to make it small so that the high turn-off current transients are localized to reduce EMI noise generation. The loop formed by MOSFET S 2 , Lg, gate input capacitance and Cpos is mainly for the turn-on transient and it is also favorable to have a small area to confine EMI noise generation. Unlike a conventional gate driver circuit, the loop area formed by the MOSFET S 1 , Cpos and the gate input capacitance is not necessary very tight since the main function of this part of the circuit is to fully enhance the conducting channel of the power switch by applying a higher gate drive voltage. 
         [0029]    Referring to the topological stages and timing diagram shown in  FIG. 4  and  FIG. 5  respectively, the turn-off procedure begins with the turn-on of S 4 . With the turn-on of S 4 , a current is established through Lg that increases linearly with time until the magnitude reaches a preset value such that S 1  is turned-off at time t 1  [stage t 0 -t 1 ]. With the turn-off of S 1 , the energy stored in Lg together with the voltage on Cneg  22  discharges the gate capacitor Cm rapidly so that the power switch transverses a turn-on delay, wherein a Miller plateau period and linear interval speedily precede the fully turn-off stage [stage t 1 -t 2 ]. The high discharging current helps alleviate the di/dt induced voltage overshoot by deviating Id through C GD . The body diode of MOSFET S 3  is forced on when the gate voltage reaches the voltage on Cneg  22 , ensuring that the current i Lg  is freewheeling in the loop formed by S 4  and S 3  [stage t 2 -t 3 ]. S 3  is turned-on any time during this stage. This stage ends with the turn-off of S 4  causing inductor energy recovery back to the power supply [stage t 3 -t 4 ]. The inductor current reduces linearly until it reaches zero at time t 4 . Since S 3  has turned-on previously, the gate input is firmly clamped by Cneg  22 , and a positive gate-to-source voltage cannot be established even under severe dv/dt conditions [stage t 4 -t 5 ]. The gate driver circuit  30  remains in this stage until a control signal instructs the turn-on procedure at t 5 . At time t 5 , MOSFET S 2  is turned on establishing a current through Lg [stage t 5 -t 6 ]. With the turn-off of S 3 , the energy stored in Lg together with Cpos  21  operate to charge the gate input Cm so that the power switch is turned on [stage t 6 -t 7 ]. Under a hard switched clamped inductive power converter application, an optimum design solution would match the diode switching characteristic without over speeding the turn-on procedure; under most resonant and soft witching applications, the turn-on speed would be less of a concern as long as it turns on the power switch in time since the drain-to-source voltage is practically zero, making the Miller effect disappear. The body diode of S 1  is turned on when the gate voltage reaches Vcpos, freewheeling the inductor current [stage t 7 -t 8 ]. This stage ends when S 2  is turned off, recycling inductor energy back to the gate power supply [stage t 8 -t 9 ]. When the inductor current drops to zero, the body diode of S 4  is turned off and completes a switching cycle [stage t 9 -t 0 ]. 
         [0030]    It becomes clear that the timing for the MOSFETs S 1  to S 4  is essential for a proper operation. It is important not to alter a normal PWM control or other control method used with a conventional gate driver circuit.  FIG. 6  illustrates an exemplary scheme of duty ratio control according to one embodiment of the present invention. The exemplary scheme depicts generation of the control timing from a typical PWM controller. Vd is a control voltage output for comparing a rising ramp saw-tooth PWM carrier that determines the duty ratio D. Voltages Vt 1  and Vt 2  generate two control signals Sa and Sb, respectively. Accordingly, the time duration of t 1  and t 2  is proportional to the voltage magnitude of Vt 1  and Vt 2 , where Vt 1  is the voltage difference from the carrier magnitude and Vt 1  is the voltage difference from the Vd. Therefore, the falling edge of Sa and Sb defines the PWM duty ratio, and now it is very easy to generate S 1  to S 4  from Sab (a combination of Sa and Sb) with a simple logic circuit. As already described herein, the duration of Sb determines the turn-off discharging current magnitude while the duration of Sa determines the turn-on charging current magnitude. A feedback mechanism may be introduced to dynamically control the turn-off/-on procedure of the gate drive circuit  30  by changing the magnitude of Vt 1  and/or Vt 2 . Now the gate drive circuit  30  becomes a closed loop with a power stage that achieves superior performance beyond that achievable by a more conventional gate driver circuit. It should be noted, the embodied scheme is easily adapted for use with a falling ramp saw-tooth PWM, a symmetrical PWM and a digital PWM as well. 
         [0031]      FIG. 7  illustrates an exemplary gate driver circuit topology when the embodied gate driver is used in a half-bridge configuration  70 . These two gate drive circuits  72 ,  74  operate in harmony using the principles described herein to ensure a best match for respective speed and dv/dt immunity under all operating condition with lowest switching losses possible. 
         [0032]      FIG. 8  and  FIG. 9  illustrate gate driver circuit embodiments  80  and  90  respectively. Gate driver circuits  80 ,  90  use asymmetrical discharging/charging inductance  82 ,  84  and  92 ,  94  respectively to again provide fast turn-off speed and turn-on with an added flexibility. 
         [0033]      FIG. 10  illustrates another gate drive circuit embodiment  100 , where a negative voltage is generated with Cneg  102  and a zener+diode branch  104 . 
         [0034]    While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.