Abstract:
A common-mode feedback circuit which calculates the common-mode signal at each stage of a pipeline ADC, rather than calculating it globally and distributing it. The local calculation thus provides a local interpolation between the positive and negative voltage reference, and also provides a mechanism for storing the interpolated charge for application to the common-mode feedback input of the amplifier.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a circuit which causes a differential op-amp common-mode output level to track a DACs common-mode level, and in particular to such circuits for use in a pipeline analog-to-digital converter (ADC). 
     In fully differential circuits, it is desirable to avoid variations in the common-mode component of differential signals. This is especially true in high resolution ADCs. A 1.5b/stage pipeline ADC, typically uses a switched digital-to-analog converter (DAC) in each stage to supply the required reference voltages that are used in the algorithm for the given stage. This switched DAC reference voltage is applied to the input of an op-amp. The op-amp is biased to accept a common-mode input at the same level as the common-mode output level of the previous stage. In addition, the op-amp typically has a limited common-mode rejection ratio (CMRR), and common-mode input range (CMIR). To minimize the variation in the common-mode component of these two inputs, it would be helpful to have the common-mode output level of the previous stage track the common-mode level of the DAC. Further, it would be helpful if this tracking function could be done without requiring any additional external decoupling capacitors. (Two decoupling capacitors are usually required for a positive DAC reference voltage (Vdacp) and a negative DAC reference voltage (Vdacn)). Also, it is helpful for this circuit to be insensitive to wire resistance, and for this circuit to track any high frequency variations in the common-mode DAC voltage. 
     SUMMARY OF THE INVENTION 
     The present invention provides a common-mode feedback circuit which capacitively interpolates the common-mode DAC signal at each stage of the pipeline, rather than resistively calculating it globally and distributing it, and sets the op-amp output equal to this interpolated voltage. 
     In the preferred embodiment, two capacitors are coupled in series with their common node connected to the CMFB input, and their other nodes connected to the positive and negative outputs of the amplifier. A first phase clock and switching circuit selectively couples the capacitors to the positive and negative outputs. A second switching circuit, and a second phase clock selectively couples the capacitors to the global positive and negative DAC voltage supplies. The common node of the capacitors is selectively connected by the second phase clock to the 0 input reference level of the common-mode op-amp. Thus, the two capacitors locally interpolate between the positive and negative voltages to generate the desired common-mode output level for the op-amp. 
     For a further understanding of the nature and advantages of the invention, reference should be made to,-the following description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an illustrative prior art ADC. 
     FIG. 2 is a diagram of a prior art DAC and amplifier in one stage of an ADC such as that in FIG. 1. 
     FIG. 3 is a circuit diagram of a typical prior art CMFB circuit. 
     FIG. 4 is a diagram of a typical prior art circuit for generating a global common-mode voltage. 
     FIG. 5 is a diagram of a common-mode feedback circuit according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 illustrates a typical prior art multi-stage pipeline ADC. A differential input is provided through an input buffer 12. The differential lines from the buffer are applied to a 1.5-bit flash circuit 14 for determining 1.5 bits of the eventual digital result. The extra 1/2 bit is used for digital error correction by circuit 16 after passing through a digital delay 18. Accordingly, the ADC is commonly referred to as a 1.5 bit/stage converter. A 1.5-bit digital-to-analog converter 20 is also provided in each stage to generate a required reference voltage. Essentially, this can be thought of as converting the digital estimate back into analog form to subtract it from the original signal in a summing circuit 22. The output of the summing circuit is then supplied to a multiplying amplifier 24 which amplifies the signal by a factor of 2 so that the residue can be presented in the same voltage range as an original signal to the next stage. 
     FIG. 2 illustrates the circuitry for a typical DAC 20, summer 22, and amplifier 24 of FIG. 1. 
     FIG. 2 is a circuit diagram of DAC 20 and amplifier 24, and summer 22. In operation, during a first phase, the phase 1 clock φ 1  is applied. The phase 1 clock connects the input voltage positive and negative signals (Vip, Vin) on lines 26 and 28 to capacitors 30, 34, and 32, 36, respectively. The other side of the capacitors are connected to reference voltage Vb4. Vb4 is the optimum common-mode Input level for the op-amp. 
     During a second phase of the clock, the φ 2  clock signal closes the switches shown, with the φ 1  switches being opened. Thus, the voltages on the capacitors 34 and 36 are connected to the outputs on lines 38 and 40, outp and outn. During this second phase, the 1.5-bit analog-to-digital conversion is produced by a circuit such as flash circuit 14 of FIG. 1. The flash circuit includes two comparators and logic which generate the 1.5-bit=3 value clock signals C10, C00, C01. These clock signals are applied to the switches as shown in FIG. 2, which compose the local DAC. Three DAC outputs are possible +Vdac, 0, and -Vdac. Vdacp is the positive voltage reference for the entire ADC. Vdacn is the global negative reference. 
     In the following descriptions, we use the following definitions: ##EQU1## where the following reference numbers are used in the figures: Vip=26 
     Vin=28 
     Vdacp=120 
     Vdacn=121 
     The control clocks select either Vdacd+Vdacc, 0+Vic, or-Vdacd+Vdacc to be applied, respectively. Vic is the common-mode input from the previous stage. Vdacd is the global differential dac voltage, and Vdacc is the global common-mode DAC voltage. 
     It can be seen that if C01 or C10 is selected, a common-mode voltage of Vic-Vdacc is applied at the op-amp input. If Vic is not equal to Vdacc, then there is a residual common-mode voltage that is applied to the op-amp input. If this residual voltage is large, and the common-mode input range of the op-amp is small, then the accuracy of the stage may be affected. The result of this residual voltage may exceed the common-mode input range of the op-amp causing the op-amp open loop gain to drop or it may cause the CMRR of the op-amp to drop. Finally, if the op-amp does not have good CMRR then the DAC 0 voltage point may not be properly interpolated. 
     FIG. 3 is circuit diagram of a typical prior art CMFB circuit. The outputs 38 and 40 of amplifier 24 are shown, along with the common-mode feedback input (V CMFB ) on line 42. These connect across two capacitors 44 and 46. Three switches 48, 50, and 52 connect these signals during phase 2 across capacitors 54 and 56. During phase 1, three switches 58, 60, and 62 connect capacitors 54 and 56 to the common-mode voltage (V CM ) and an intermediate reference voltage Vb5 which is equal to the zero level of the common-mode op-amp input 103. 
     In a typical prior art circuit, the common-mode voltage (V CM ) is generated globally by a circuit shown in FIG. 4. An external capacitor 64 connects via a chip pad 66 to a node 68 which is coupled between the positive ADC reference voltage Vdacp and the negative ADC reference voltage Vdacn by resistors 70 and 72, respectively. These resistors perform an interpolation function, and generate the common-mode voltage, V CM . This signal line is then routed to each of the stages to provide the respective V CM  signals such as shown on line 58 in FIG. 3. This voltage Vcm is used with switched capacitor common-mode feedback (SC CMFB) to set Vic to be equal to Vdacc. There are several drawbacks to this approach. The first disadvantage is that the buffer that generates Vdac voltages must be able to drive a resistive load. This takes additional dc drive current, and can be more difficult to construct. Also, since a large, high-speed switched capacitive load is applied to this node voltage, typically an external decoupling capacitor is required. Finally, since the time constant of this node does not track the time constant of the Vdacp and Vdacn nodes, it is possible that in a transient sense Vdacc and Vic do not track. 
     The present invention shows a CMFB circuit for each stage as set forth in FIG. 5. Here, capacitive interpolation is used to directly force Vic to be equal to Vdacc. This is done with a modification to the switched-capacitor common-mode feedback circuit of FIG. 3. The circuit is configured to act as a sample-and-hold circuit and interpolator, causing Vic to track Vdacc very closely at all frequencies. This circuit also overcomes the disadvantages of the resistive generation of Vic globally. 
     In particular, FIG. 5 shows outputs 38 and 40 connected directly to capacitors 80 and 82 through phase 2 switches 84 and 86, respectively. The CMFB op-amp input is directly connected to a common node 88 of the two capacitors. The other nodes 90 and 92 are connected to the outputs during phase 2, but are connected directly to the global positive reference voltage (Vdacp) and the negative voltage reference (Vdacn) of FIG. 4 and phase 1 switches 98 and 100. Common node 88 is connected to an intermediate voltage reference Vb5 through another phase 1 switch 102. The present invention thus locally, in each stage, interpolates between Vdacp and Vdacn, rather than doing it globally as in FIG. 4 to produce a V cM  signal. This overcomes a number of disadvantages of the resistive generation shown in FIG. 4. 
     There is only a capacitive load on the buffer that drives the Vdacp and Vdacn nodes, simplifying buffer design. A decoupling capacitor for Vcm of FIG. 4 is not required, thus saving an additional external decoupling capacitor and pad. The time constant of Vdacc precisely tracks that of Vic, forcing them to match under transient conditions. Parasitic matched resistance between global Vdacp and switch 98, and global Vdacn and switch 100 does not cause an error in the generated Vic voltage. 
     As will be understood by those of skill in the art, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the foregoing description is intended to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.