Abstract:
Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Patent Applications Nos. 60/920,908, filed Mar. 30, 2007, and 60/957,066, filed Aug. 21, 2007, each of which is hereby incorporated by reference herein in its entirety. 
    
    
     TECHNICAL FIELD 
     The disclosed subject matter relates to circuits for forming the inputs of a latch. 
     BACKGROUND 
     Continuing decreases in the sizes and power requirements for electronic devices has resulted in a requirement for ever decreasing supply voltages for digital and analog circuits. For example, as more and more circuits are designed for implementation in scaled nanometer CMOS technologies, the supply voltages will continue to decrease from 1.2 V to 0.5 V. These decreasing supply voltages often have the added benefit of prolonging battery life in portable devices. 
     In order to address the decreasing supply voltages, it is desirable to provide circuit designs that operate on lower supply voltages. 
     SUMMARY 
     Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal. 
     In some embodiments, circuits for forming inputs of an AND gate and a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a first input to the AND gate; a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a second input to the AND gate and the second drain terminal is coupled to the first source terminal; and a third transistor having a third gate terminal, a third drain terminal, a third source terminal, a third gate length, and a third common mode level at the third gate terminal, wherein the third gate terminal provides a clock input to the latch, the third drain terminal is coupled to the second source terminal, and the first gate length, the second gate length, and the third gate length are sized so that the first common model level, the second common mode level, and the third common mode level are substantially equal. 
     In some embodiments, methods for calibrating a tuning gain of a second port in a frequency synthesizer having a first port and the second port are provided, the methods comprising: setting the second port to a first input level; locking a loop in the frequency synthesizer to a known frequency; setting a reference level to a measured level at the first port; changing the second port to a second input level; changing the frequency of the frequency synthesizer; comparing a measured level at the first port to the reference level; and computing the tuning gain of the second port based on the change to the second port and the change to the frequency of the frequency synthesizer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a low-voltage, fractional-N frequency synthesizer in accordance with some embodiments. 
         FIG. 2  is a diagram of a voltage controlled oscillator in accordance with some embodiments. 
         FIG. 3  is a diagram showing relationships between oscillation frequency and tuning voltage in a voltage controlled oscillator in accordance with some embodiments. 
         FIG. 4  is a diagram of a programmable divider in accordance with some embodiments. 
         FIG. 5  is a diagram of a latch in accordance with some embodiments. 
         FIGS. 6(   a ),  6 ( b ), and  6 ( c ) are diagrams showing threshold voltage (V T ) values, gate lengths, and forward body biases of latch transistors in accordance with some embodiments. 
         FIGS. 7(   a ) and  7 ( b ) are diagrams of an AND gate integrated with a latch in NMOS and PMOS technologies accordance with some embodiments. 
         FIG. 8  is a diagram of a delta sigma modulator in accordance with some embodiments. 
         FIG. 9  is a diagram of a phase frequency detector and a charge-pump in accordance with some embodiments. 
         FIG. 10  is a diagram of a calibration procedure in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     In accordance with various embodiments, circuits for forming the inputs of a latch are provided. In some embodiments, low-voltage, fractional-N frequency synthesizers, such as a synthesizer  100  illustrated in  FIG. 1 , are provided. In some embodiments, a low-voltage, fractional-N frequency synthesizer can be used as a Frequency Shift Keying (FSK) modulator by modulating the data through the frequency control word according to a modulation data input  101 . In some embodiments, a low-voltage, fractional-N frequency synthesizer can be used as a local oscillator. In some embodiments, the circuit can be implemented in a standard 90 nm CMOS process with one polysilicon and nine metal layers, and with only regular V T  devices. 
     As can be seen from  FIG. 1 , synthesizer  100  can include a voltage controlled oscillator with programmable varactor bank  102 , a programmable divider  104 , a delta-sigma modulator  106 , an interface/memory module  107  (which can be used to store configuration settings for use by the synthesizer), a phase/frequency detector  108 , a charge-pump  110 , buffers  111  and  112 , a loop filter  114  (to filter the feedback signal to VCO  102 ; which filter can be external (as shown) or internal), and a load driver  116 . Within these components, a control loop is formed for locking the synthesizer at a specified frequency. 
     As can also be seen from  FIG. 1 , one portion  154  of the synthesizer can operate using an analog power supply and another portion  156  can operate using a digital power supply. 
     To operate synthesizer  100  of  FIG. 1 , a reference frequency can be provided at point  150 , clock, serial data, latch enable, and reset signals can be provided at the interface/memory  107 , modulation data can be provided at input  101 , and a differential load provided at output  152 . Any suitable reference frequency source can be used, such as a crystal oscillator, in some embodiments. 
     One embodiment of a voltage controlled oscillator  200  that can be used in some embodiments as VCO  102  of  FIG. 1  is illustrated in  FIG. 2 . As shown, VCO  200  includes a biasing scheme based on a top-biased topology  202  in which the common-mode of a cross-coupled pair  204  is designed to be about half of its supply voltage by sizing NMOS switching transistors  208  and  210  and a PMOS current mirror  206  so that all of the internal nodes are kept in between the power supply voltage and ground which can improves long-term circuit reliability. In some embodiments, this VCO can be implemented with only regular V T  devices. For example, when the VCO operates from a 0.5 V power supply, there can be at least 250 mV available across PMOS current source  244 , which can cause transistor  244  to operate in the saturation region. 
     A hybrid tuning scheme that can be used in VCO  200  can include discrete and continuous parts in some embodiments. The switched varactors in regions  236  and  238  (e.g., varactors  216 ,  218 ,  220 ,  224 ,  226 ,  228 ,  230 , and  232 ) can be used as capacitances for discrete frequency tuning. Although only four varactors are illustrated in each of regions  236  and  238 , each of these regions can have any suitable number of varactors. For example, each region can contain 16 varactors in some embodiments. 
     The tuning nodes of the varactors in regions  236  and  238  can be driven by logic signals from thermometer encoder  234 . The size of thermometer encoder  234  can be modified to correspond to the number of varactors in regions  236  and  238 . These logic signals can switch the varactors between two discrete states—high capacitance and low capacitance. The varactors can be implemented with inversion mode PMOS transistors whose gate nodes are connected to the LC tank while source and drain nodes are shorted and connected to the outputs of thermometer encoder  234 . 
     Varactors  212  and  214  can be used to form variable capacitances for the continuous part of the hybrid tuning scheme. The varactors can be implemented with inversion mode PMOS transistors whose gate nodes are connected to the inductors and the cross-coupled transistors, while source and drain nodes are shorted and connected to the feedback tuning voltage  240  from the loop filter (see  FIG. 1 ). In some embodiments, while the tuning voltage increases from 200 mV to 500 mV, the source-gate voltage across varactors  212  and  214  can change from 50 mV to 250 mV, and thus the PMOS varactors can be biased from the depletion region (low capacitance) toward the inversion region (high capacitance). 
     The varactors in regions  236  and  238  can be laid-out using unit cells, which can have a width of 20 um, a length of 0.4 um, and a threshold voltage of 150 mV. Varactors  212  and  214  can be laid out using unit cells which have a width of 80 um, a length of 0.4 um, and a threshold voltage of 150 mV. Transistors  208  and  210  can be laid out using unit cells which have a width of 50 um and a length of 0.25 um. Transistor  244  can be laid out using unit cells which have a width of 1500 um and a length of 0.5 um. 
     The use of switched varactors as described above can lead to a compact layout and a better matching between the discrete and continuous tuning parts. 
     As shown in  FIG. 2 , VCO  200  can also include a 4.5 nH, six-turn, center-tapped symmetric inductor  242  that is constructed using metal-9 and metal-8 in parallel. The inductor can be designed to have an even number of turns to minimize the effect of parasitic looping formed by the power rails outside the LC tank. Inductor  242  along with varactors  212  and  214 , varactors  216 ,  218 ,  220 ,  224 ,  226 ,  228 ,  230 , and  232 , and the parasitic capacitance of the negative resistance formed by transistors  208  and  210  can be used to form the LC tank. 
     In some embodiments, the VCO can nominally drain a bias current of 4 mA from a 0.5 V supply and can be tuned from 2.4 GHz to 2.6 GHz with 16 discrete settings of the varactors in regions  236  and  238  as shown in  FIG. 3 . 
     In some embodiments, the tuning range of the continuous part, which can be composed of eight unit varactor cells, can vary from 25 MHz to 60 MHz with different settings, and the tune voltage while in lock can vary from 320 mV to 480 mV. 
     Turning to  FIG. 4 , a programmable divider  400  that can be used in some embodiments as programmable divider  104  of  FIG. 1  is illustrated. Programmable divider  400  can be implemented using a high frequency front-end section and a low frequency back-end section, which can be implemented using current-mode logic (CML) and standard CMOS logic, respectively. Programmable divider  400  adopts a modular architecture using a cascade of divide-by-⅔ stages  402 ,  404 ,  406 ,  408 ,  410 ,  412 ,  414 ,  416 ,  418 ,  420 , and  422 , which can each be constructed logically as illustrated by diagram  434 . Although eleven total stages are illustrated, any suitable number of stages can be used in some embodiments. Because the clock in each stage is halved compared to its preceding stage, each stage can also be scaled and optimized for lower power consumption in some embodiments. As shown, the front-end section includes cascaded current-mode logic divide-by-⅔ divider cells  402 ,  404 ,  406 , and  408 , and can receive a feedback signal from a VCO at input  401  (e.g., as illustrated in  FIG. 1 ) and divide it down. For example, the front end can receive a 2.5 GHz feedback signal and divide it down to about 150 MHz. The back-end section includes seven cascaded CMOS divide-by-⅔ divider cells  410 ,  412 ,  414 ,  416 ,  418 ,  420 , and  422 , modulus extension logic  424 , and modulus decoder  426 , and can further divide the feedback signal down (e.g., to about 16 MHz). The dividers can be connected to a digital V DD  of 0.65V. 
     To bridge the common mode logic (CML) to CMOS logic of the front end and back end, respectively, a CML to CMOS logic converter  430  can be provided between the front end and the back end. Converter  430  can be constructed as illustrated in diagram  432  of  FIG. 4 . 
     In some embodiments, a latch (such as latch  435 ) in the current-mode logic of  FIG. 4  can be implemented as illustrated in  FIG. 5 . In some embodiments, the components shown in  FIG. 5  can be operated in moderate to strong inversion in order to obtain sufficient f T  for high-speed operation. For example, with a supply of 0.65 V, the output DC level at Q and Qb can be chosen to be 0.5 V to provide a swing of 150 mV single-ended. Since the clock (CK and CKb) and data (D and Db) inputs can be connected to the outputs from other cells with 0.5 V output DC level, the DC common mode level at all inputs can also be 0.5 V. 
     Examples of node bias voltage levels of the current-mode latch of  FIG. 5  that can be used in some embodiments are illustrated in  FIGS. 6(   a ),  6 ( b ), and  6 ( c ). As shown in  FIG. 6(   a ), the current source transistor M 3  can be designed to have a V DS  of 200 mV to operate in the saturation region. The transistor M 1  can be designed to have an overdrive of 75 mV, while the clock transistor M 2  can be designed to have an overdrive of 100 mV for a higher speed requirement. In order to meet these designed overdrive voltages, the V T  of M 1  can be 125 mV, while the V T  of M 2  can be 200 mV. In some embodiments, when the biasing constraints are satisfied, the latch can operate from a supply voltage as low as 0.5 V with the required swing and with a current source at its tail. 
     A technique that can be used to adjust the threshold voltage (V T ) of NMOS devices is to make use of the reverse short channel effect. For instance, in a 90 nm CMOS technology, by increasing the length of the NMOS transistor from 90 nm to 350 nm, the nominal threshold voltage can be reduced from 300 mV to about 140 mV as illustrated in  FIG. 6(   b ). Transistor M 1  can be sized to have a length of 240 nm, while transistor M 2  can be sized to have a length of 120 nm with slightly higher V T . To further adjust the V T  of the devices, forward body bias can be applied to all the NMOS transistors in the current-mode logic gates and deep N-well isolation can be used to isolate different P-bodies biased by different voltages. In  FIG. 6(   c ), the nominal V T  of NMOS transistors with the length of 120 nm and 240 nm is plotted versus body-source voltage, V BS . To have an additional 50 mV of V T  reduction, a 450 mV forward body bias can be applied to the transistors in the current-mode logic gates. Thus, the fully differential latch can be sized to have transistor M 1  be 240 nm long with 125 mV V T  and transistor M 2  be 120 nm long with 200 mV V T . 
     In addition to the latches illustrated in  FIGS. 5 and 6 , each divide-by-⅔ cell illustrated in diagram  434  of  FIG. 4  also requires AND gates, such as AND gate  437 . If an AND gate is implemented as a separate gate, doing so can introduce extra delay which degrades the maximum speed of the divider. Thus, in accordance with some embodiments, an AND gate  700  can be combined with the latch circuitry illustrated above and constructed as shown in  FIG. 7(   a ). 
     In some embodiments, in the first divide-by-⅔ stage, the cross-coupled latch transistor pairs  702  and  704  are sized smaller than the logic transistors  706  and  708  and its clock port  710  is DC biased to set its self-oscillation frequency between 2 and 3 GHz, which can maximize the divider sensitivity over the VCO operation range. In some embodiments, the power scaling factor along the cascade of stages is 0.7 rather than 0.5 in order to leave enough margin for parasitics which cannot be scaled. 
     In some embodiments, the transistors in  FIG. 7(   a ) can be sized so that transistors  712  and  714  have lengths of 120 nm and transistors  706 ,  708 ,  716 ,  718 , and  720  have lengths of 240 nm. As described in connection with  FIG. 6(   b ), such lengths can cause the threshold voltages of these transistors to permit operation off a low supply voltage, such as 0.65 V. 
     A PMOS version of the circuit of  FIG. 7(   a ) can be implemented as illustrated in  FIG. 7(   b ) in accordance with some embodiments. 
     As mentioned above, the back-end divider section is also based on the cascade of divide-by-⅔ cells. Since the division ratio of a cascaded truly modular divider can be formulated as N=2M+K, K=0 to 2M−1, where M is the number of cascaded stages, making the number of cascades reconfigurable can extend the available modulus range. In some embodiments, modulus extension logic  424  and modulus decoder  426  can be used to reconfigure the number of cascades by providing a programmable interconnecting mechanism for the CTRLO and CTRLI terminals of stages  414 ,  416 ,  418 ,  420 , and  422 . 
     Due to the cascade nature of the divider architecture, delay uncertainty can introduce extra jitter that is accumulated along the chain of divider cells. Accordingly, in some embodiments, a re-timing circuit formed by  436 ,  438 , and  440  as shown in  FIG. 4  can be used to retime the divider output signal to the VCO output signal and eliminate this divider jitter. The divided signal (output of  436 ) (which can have a standard CMOS logic level) can then be converted back to a differential signal by buffer  438  and fed into a current-mode latch  440  which is triggered by the original VCO signal. 
     In order to synthesize frequencies with steps finer than the reference clock in low-voltage, fractional-N frequency synthesizers, a digital delta-sigma modulator can be used to modulate the modulus control word and generate a sequence of over-sampled words to control the integer programmable divider. Through changing the instantaneous integer division ratio controlled by the modulated words, the equivalent ratio can be made fractional and the phase spectrum of the divided signal can be properly shaped to have a high-pass characteristic. In some embodiments, a MASH-1-1-1 architecture can be used for the delta-sigma modulator. This architecture can include a cascade of first order delta-sigma modulators, which can be equivalent to digital accumulators with fixed length, and, therefore, can be scalable for different orders. 
     Turning to  FIG. 8 , a delta-sigma modulator  800  that is based on a MASH-1-1-1 architecture and that can be used in some embodiments as delta-sigma modulator  106  of  FIG. 1  is illustrated. 
     During operation of modulator  800 , a 16-bit long data path  802  is summed to a 24-bit fractional part  804  of a modulus control word by a pipelined adder  806 . The modulator then modulates the 24-bit fractional sum at points  810 ,  812 , and  814  into an over-sampled 4-bit (in 2s complement format) word sequence at point  808 , and then this sequence is summed with an 11-bit integer number  816 . The resulting 11-bit modulated modulus control word  818  can then be applied to the current-mode logic (CML) and the CMOS logic divider stages (shown in  FIG. 4 ). 
     To reduce the hardware in the modulator to save power and reduce switching noise coupled to the substrate, the content stored in registers  822 ,  824 ,  826 ,  828 ,  830 ,  832 ,  834 ,  836 ,  838 ,  840 ,  842 ,  844 ,  846 , and  848 , which is the residual quantization error in each section, can be truncated to lower resolution in some embodiments. This truncation can provide a result that is similar to adding extra quantization error to the input of truncated sections, and can introduce a mismatch when quantization error cancellation is performed. 
     In some embodiments, the divider modulus  818  is modulated over a range from N+4 to N−3 in a noise shaped fashion and results in a non-integer division ratio between N+1 and N. With 24-bit fractional resolution, the frequency synthesis can give a step size below 4 Hz with a reference frequency of 16 MHz. However, this arrangement can lead to a significant increase in phase noise on the synthesizer output spectrum at higher offset frequencies. This is because switching by the noise-shaped bit stream on the modulus of the divide-by-⅔ cells can cause a switching current noise coupling through the substrate with higher sensitivity due to the forward body bias. As a result, the VCO can be contaminated by switching interference, especially from the divider cells with larger bias currents. 
     To address this problem, in some embodiments, the dithering bits of the digital modulator can be shifted to later bits by shifter  820  (as controlled by shift control  822 ), resulting in a multiplication of the modulated word stream by powers of two. Given that the first two stages  402  and  404  of the programmable divider (as shown in  FIG. 4 ) can consume higher power for high-speed operation, the dithering can be shifted to start from the third stage  406  ( FIG. 4 ) to prevent it from switching the high power stages, and the modulus control word can then be changed over a range from N+16 to N−12 by the modulator. However, this shifting can result in a higher level of phase noise due to the larger quantization noise. This additional noise can be outside of the bandwidth of loop filter  114  ( FIG. 1 ) and can be properly rejected with an appropriate loop filter design with higher attenuation. For applications requiring medium phase noise performance, such as a BLUETOOTH transceiver, the increase in quantization noise may not cause significant degradation of phase noise, but this dithering re-arrangement can effectively avoid the substrate noise injection into the forward-biased body. 
     An asynchronous tri-state phase and frequency detector (PFD)  902  that can be used in some embodiments as phase/frequency detector  108  of  FIG. 1  is shown in  FIG. 9 . As illustrated in  FIG. 9 , one or more delay cells  903  which can correspond to about a 1 ns delay time can be inserted in the feedback of the PFD in order to increase the on-state pulse width to prevent a dead-zone problem due to the finite turn-on time of the charge-pump current. As also illustrated in  FIG. 9 , the output of the PFD can be multiplexed by devices  904  and  906  to provide dual polarity for flexibility of loop filters. 
     A charge-pump circuit  908  that can be used in some embodiments as charge-pump  110  of  FIG. 1  is also shown in  FIG. 9 . As illustrated, charge-pump circuit  908  can use a source switch topology, in which multiple stages  910  and  912  of the charge pump can be provided. Although only two stages  910  and  912  are shown in  FIG. 9  for simplicity, any suitable number of stages (e.g., such as four) can be provided. The switching of the stages can be implemented progressively so that, initially, only the first stage is engaged, then the first and second stages are engaged, then the first, second, and third stages are engaged, and then the first, second, third, and fourth stages are engaged. This switching can be controlled by interface/memory module  107  via control lines  158 . 
     In accordance with some embodiments, a technique for wideband data transmission that can be used with low-voltage, fractional-N frequency synthesizers can be referred as two-point modulation. In two-point modulation, modulation data applied to the divider control word sees a low-pass characteristic while data applied at the VCO tune node sees a high-pass characteristic. The low-pass and high-pass paths can be combined to reconstruct an all-pass channel for data transmission. This architecture is suitable for integration since the low-pass data path can be built into the divider modulus control, and an additional DAC can be implemented to convert the digitally modulated data to an analog voltage signal to modulate the VCO tune node for the high-pass modulation path. 
     More specifically, in some embodiments, modulation port  101  of  FIG. 1  can receive digital modulation data and see a low-pass characteristic while the VCO has a secondary tuning port  118  that can receive analog modulation data from a DAC and see a high-pass characteristic. If the data is fed to both ports at the same time, the modulation data will see an all-pass transfer function. In an FSK system, the frequency deviation is usually given implicitly with the modulation index or β. If the bandwidth of the modulation data is smaller than the bandwidth of the loop formed by the synthesizer (which means it can be applied to the digital data port only), the frequency deviation can be well controlled through the division modulus since the reference frequency is a known parameter. In the case of two-point modulation, however, the transfer function of the high-pass modulation path will be related with the combination of DAC and VCO tuning gain, which can be difficult to control. Therefore, the modulation can be affected by the resulting gain mismatch between the two paths. 
     In some embodiments, the gain mismatch can be calibrated through a procedure  1000  illustrated in  FIG. 10 . First, the synthesizer can be powered-up at  1002 . Next, at  1004 , a voltage increase amount to be supplied to the secondary modulation port ( 118  of  FIG. 1 ) can be initialized. At  1006 , the secondary modulation port can be set to V REF2  (which can be any suitable value), the loop can be locked to a known frequency, and a value V REF1  can be set to the voltage measured on the primary tuning port. Then, at  1008 , the secondary tuning port modulation value can be increased by a known increment. At  1010 , the frequency control word of the synthesizer can be increased. Then, at  1012 , the voltage at the primary port can be measured and compared to V REF1 . If the voltage is less than V REF1 , procedure  1000  can loop back to  1010  and the frequency control word can be increased again. If the voltage is more than V REF1 , procedure  1000  can check at  1014  whether any other secondary port values are to be checked. If so, then the secondary port increment can be increased at  1016  and procedure  1000  will loop back to  10008 . If not, then the tuning gain of the secondary port can be computed, and the modulation gain in the code domain adjusted, at  1018 . 
     The procedure illustrate in  FIG. 10  can be implemented in some embodiments using on-chip components, such as suitable logic and an analog to digital converter for measuring voltages ports  118  and  120  of  FIG. 1 . 
     Apart from the gain mismatch, there can also be path delay mismatch which can come from latency from the DAC and the pipeline. To address this, additional registers can be inserted in some embodiments after a Gaussian filter used to drive the synthesizer to add a delay, and/or the data used to drive the two inputs can be phased to compensate for delay. 
     Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is only limited by the claims which follow. Features of the disclosed embodiments can be combined and rearranged in various ways.