Abstract:
The object of the invention is to provide a semiconductor device realizing high-speed operation of surrounding gate transistors (SGTs), which are three-dimensional semiconductors, by increasing the ON current of the SGTs. This object is achieved by a semiconductor element being provided in which a source, a drain and a gate are positioned in layers on a substrate, the semiconductor element being provided with: a silicon column; an insulating body surrounding the side surface of the silicon column; a gate surrounding the insulating body; a source region positioned above or below the silicon column; and a drain region positioned below or above the silicon column; wherein the contact surface of the silicon column with the source region is smaller than the contact surface of the silicon column with the drain region.

Description:
RELATED APPLICATIONS 
       [0001]    Pursuant to 35 U.S.C. §119(e), this application claims the benefit of the filing date of Provisional U.S. Patent Application Ser. No. 61/281,437 filed on Nov. 16, 2009. This application also claims priority under 35 U.S.C. §119(a) to JP2009-259491 filed on Nov. 13, 2009. The entire contents of these applications are hereby incorporated by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to a semiconductor element and to a semiconductor device which uses the semiconductor element, and specifically relates to a semiconductor device which uses a surrounding gate transistor (SGT) comprising a three-dimensional semiconductor and the semiconductor device by which it is used. 
       BACKGROUND OF THE INVENTION 
       [0003]    A miniaturized planar transistor is used in the broad sector of computers, communication equipment, instruments, automatic control devices, and machinery and tools used in daily life, as microprocessors, ASIC and microcomputers which have low power consumption, are low in cost and which have high information processing ability; and as low-cost high-capacity memory. With a planar type transistor, a source, gate, and drain are horizontally arranged relative to a silicon substrate surface. On the other hand, with an SGT, the source, gate and drain are arranged vertically relative to the silicon substrate. The gate incorporates a convex semiconductor layer arranged on a silicon substrate (for example, reference is made to non-patent literature 1, and to  FIG. 94  of the specification of the present application). Furthermore, in comparison to a planar type transistor, the area possessed by the SGT is small relative to the substrate (for example, reference is made to non-patent literature 2). 
         [0004]    For an SGT as well, as with the planar transistor, the realization of high-speed operation and low power consumption is sought. The SGT structure is greatly influenced by the creation process. With a typical SGT production method, an SGT silicon column is formed by etching the silicon layer by means of the dry etching method. The cross-sectional shape of an SGT silicon column thus formed by the characteristics and dry etching generally becomes a trapezoid (for example, reference is made to patent literature 1, and to  FIG. 94  of the specification of the present application). Furthermore, with an SGT in which the cross-section of a silicon column is a trapezoid, the realization of high-speed operation and low power consumption is sought.
   [Patent Literature 1] Unexamined Japanese Patent Application KOKAI Publication No. 2007-123415   [Non-Patent Literature 1] H. Takato. Et. al, IEEE Transactions on electron devices vol. 38, No. 3, March 1991, pp. 573-578   [Non-Patent Literature 2] S. Watanabe, IEEE Transactions on electron devices, vol. 50, October 2003, pp. 2073-2080   
 
       SUMMARY OF THE INVENTION 
       [0008]    The present invention, in considering the problem, has the objective of providing a semiconductor element and semiconductor device which operates at high speed. 
         [0009]    The semiconductor element relating to the first aspect of the present invention is wherein it is provided with: 
         [0010]    a silicon column, and an insulating body arranged on the silicon column so as to encompass the side surface of the silicon column, and 
         [0011]    a gate arranged on the insulating body so is to encompass the insulating body, and 
         [0012]    a source region arranged on the upper part or the lower part of the silicon column, and 
         [0013]    a drain region arranged on the lower part or the upper part of the silicon column, 
         [0014]    wherein the contact surface between the silicon column and the source region is smaller than the contact surface between the silicon column and the drain region. 
         [0015]    At this time, a semiconductor element is composed to be capable of being arranged on the substrate, and on the substrate are arranged one or more semiconductor elements having the same structure as a semiconductor element which is different from that of the referenced semiconductor element, and it would be desirable for the gate of the semiconductor element to be connected to the gate of a separate semiconductor element, and for the drain region of the semiconductor element to be connected to the drain region of a separate semiconductor, and for the source region of the semiconductor element to be connected to the source region of a separate semiconductor element. 
         [0016]    The semiconductor device relating to a second aspect of the present invention is wherein it is a semiconductor device that operates as a NAND circuit composed of four semiconductor elements arranged on a substrate in an array of 2 rows and 2 columns, and 
         [0017]    the drain regions of the semiconductor element arranged in a 1st row 1st column, 2nd row 1st column, and 2nd row 2nd column are respectively arranged toward the substrate side from the silicon column; and 
         [0018]    the source region of the semiconductor elements arranged in the 1st row 
         [0019]    2nd column is arranged toward the substrate side from the silicon column; and 
         [0020]    the gates of the semiconductor elements arranged in a 1st row 1st column and 1st row 2nd column are mutually connected; and 
         [0021]    the gates of the semiconductor elements arranged in a 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0022]    the drain regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0023]    the source region of the semiconductor element arranged in a 2nd row 2nd column is connected to the drain region of the semiconductor element arranged in the 1st row 2nd column. 
         [0024]    The semiconductor device relating to a third aspect of the present invention is wherein it is a semiconductor device that operates as a NAND circuit composed of four semiconductor elements arranged on a substrate in an array of 2 rows and 2 columns, 
         [0025]    the drain regions of the semiconductor elements are respectively arranged toward the substrate side from the silicon column; and 
         [0026]    the gates of the semiconductor elements arranged in a 1st row 1st column and 1st row 2nd column are mutually connected; and 
         [0027]    the gates of the semiconductor elements arranged in a 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0028]    the drain regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0029]    the source region of the semiconductor element arranged in a 2nd row 2nd column is connected to the drain region of the semiconductor element arranged in the 1st row 2nd column. 
         [0030]    The semiconductor device relating to a fourth aspect of the present invention is wherein it is a semiconductor device that operates as a NAND circuit composed of four semiconductor elements arranged on a substrate in an array of 2 rows and 2 columns, and 
         [0031]    the drain region of the semiconductor element arranged in a 1st row 2nd column is arranged toward the substrate side from the silicon column; and 
         [0032]    the source regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are arranged toward the substrate side from the silicon column; and 
         [0033]    the gates of the semiconductor elements arranged in a 1st row 1st column and 1st row 2nd column are mutually connected; and 
         [0034]    the gates of the semiconductor elements arranged in a 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0035]    the drain regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0036]    the source region of the semiconductor element arranged in a 2nd row 2nd column, is connected to the drain region of the semiconductor element arranged in the 1st row 2nd column. 
         [0037]    The semiconductor device relating to a fifth aspect of the present invention is wherein it is a semiconductor device that operates as a NAND circuit composed of four semiconductor elements arranged on a substrate in an array of 2 rows and 2 columns, and 
         [0038]    the source regions of the semiconductor elements arranged in a 1st row 1st column, 1st row 2nd column, 2nd row 1st column and 2nd row 2nd column are respectively arranged toward the substrate side from the silicon column; and 
         [0039]    the gates of the semiconductor elements arranged in a 1st row 1st column and 1st row 2nd column are mutually connected; and 
         [0040]    the gates of the semiconductor elements arranged in a 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0041]    the drain regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0042]    the source regions of the semiconductor elements arranged in a 2nd row 2nd column, are connected to the drain region of the semiconductor element arranged in the 1st row 2nd column. 
         [0043]    A semiconductor element relating to the sixth aspect of the present invention is wherein it is provided with: 
         [0044]    a first silicon column which has a first contact surface and a second contact surface, and 
         [0045]    an insulating body arranged on the first silicon column so as to encompass the side surface of the first silicon column, and a gate arranged on the insulating body so as to encompass the insulating body, and 
         [0046]    a second silicon column connected to the first silicon column within the side of the first contact surface, wherein it is a second silicon column arranged on the upper part or the lower part of the first silicon column, and 
         [0047]    a third silicon column connected to the first silicon column within the side of the second contact surface, wherein it is a third silicon column arranged on the lower part or the upper part of the first silicon column, and 
         [0048]    a source region which covers the second silicon column in accompaniment with covering the part which does not contact the second silicon column within the first contact surface, and 
         [0049]    a drain region which covers the third silicon column in accompaniment with covering the part which does not contact the third silicon column within the second contact surface, wherein the first contact surface is smaller than the second contact surface. 
         [0050]    At this time, a semiconductor element is composed so as to be capable of being arranged on a substrate, and on the substrate are arranged one or more separate semiconductor elements of the same structure as semiconductor elements which are different from the above semiconductor element, wherein it is desirable that: 
         [0051]    the gate of the semiconductor element is connected to the gate of the separate semiconductor element, and 
         [0052]    that the drain region of the semiconductor element is connected to the drain region of the separate semiconductor element, and 
         [0053]    that the source region of the semiconductor element is connected to the source region of the separate semiconductor element. 
         [0054]    The semiconductor device relating to a seventh aspect of the present invention is wherein it is a semiconductor device that operates as a NAND circuit composed of four semiconductor elements arranged on a substrate in an array of 2 rows and 2 columns, and that: 
         [0055]    the drain regions of the semiconductor element arranged in a 1st row 1st column, 2nd row 1st column, and 2nd row 2nd column are respectively arranged toward the substrate side from the first silicon column; and 
         [0056]    the source region of the semiconductor element arranged in a 1st row 2nd column is arranged on the substrate side from the first silicon column; and 
         [0057]    the gates of the semiconductor elements arranged in a 1st row 1st column and 1st row 2nd column are mutually connected; and 
         [0058]    the gates of the semiconductor elements arranged in a 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0059]    the drain regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0060]    the source region of the semiconductor element arranged in a 2nd row 2nd column is connected to the drain region of the semiconductor element arranged in the 1st row 2nd column. 
         [0061]    The semiconductor device relating to a eighth aspect of the present invention is wherein it is a semiconductor device that operates as a NAND circuit composed of four semiconductor elements arranged on a substrate in an array of 2 rows and 2 columns, and 
         [0062]    the drain regions of all of the semiconductor elements are respectively arranged toward the substrate side from the first silicon column; and 
         [0063]    the gates of the semiconductor elements arranged in a 1st row 1st column and 1st row 2nd column are mutually connected; and 
         [0064]    the gates of the semiconductor elements arranged in a 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0065]    the drain regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0066]    the source region of the semiconductor element arranged in a 2nd row 2nd column is connected to the drain region of the semiconductor element arranged in a 1st row 2nd column. 
         [0067]    The semiconductor device relating to a ninth aspect of the present invention is wherein it is a semiconductor device that operates as a NAND circuit composed of four semiconductor elements arranged on a substrate in an array of 2 rows and 2 columns, and 
         [0068]    the drain region of the semiconductor element arranged in a 1st row 2nd column is arranged toward the substrate side from the first silicon column, and 
         [0069]    the source regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are respectively arranged toward the substrate side from the first silicon column, and 
         [0070]    the gates of the semiconductor elements arranged in a 1st row 1st column and 1st row 2nd column are mutually connected; and 
         [0071]    the gates of the semiconductor elements arranged in a 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0072]    the drain regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0073]    the source region of the semiconductor element arranged in a 2nd row 2nd column is connected to the drain region of the semiconductor element arranged in a 1st row 2nd column. 
         [0074]    The semiconductor device relating to a tenth aspect of the present invention is wherein it is a semiconductor device that operates as a NAND circuit composed of four semiconductor elements arranged on a substrate in an array of 2 rows and 2 columns, and 
         [0075]    the source regions of all of the semiconductor elements are respectively arranged towards the substrate side from the first silicon column, and 
         [0076]    the gates of the semiconductor elements arranged in a 1st row 1st column and 1st row 2nd column are mutually connected; and 
         [0077]    the gates of the semiconductor elements arranged in a 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0078]    the drain regions of the semiconductor elements arranged in a 1st row 1st column, 2nd row 1st column and 2nd row 2nd column are mutually connected; and 
         [0079]    the source region of the semiconductor element arranged in a 2nd row 2nd column is connected to the drain region of the semiconductor element arranged in a 1st row 2nd column. 
         [0080]    According to the semiconductor element having the above structure, since the ON current through which the SGT flows is large in comparison with a conventional SGT, high speed processing of the semiconductor device is made possible using this semiconductor element. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0081]    A more complete understanding of this application can be obtained when the following detailed description is considered in conjunction with the following drawings, in which: 
           [0082]      FIG. 1  is a planar drawing which shows the transistor relating to the first embodiment of the present invention; 
           [0083]      FIG. 2  is a cross-sectional view along line a-a′ of the transistor in  FIG. 1 ; 
           [0084]      FIG. 3  is a cross-sectional view along line b-b′ of the transistor in  FIG. 2 ; 
           [0085]      FIG. 4  is a cross-sectional view along line c-c′ of the transistor in  FIG. 2 ; 
           [0086]      FIG. 5  is a cross-sectional view a long line d-d′ of the transistor in  FIG. 2 ; 
           [0087]      FIG. 6  is an electric current-voltage drawing of the transistor relating to the first embodiment of the present invention accomplished by model simulation analysis; 
           [0088]      FIG. 7  is an electric current-voltage drawing in which the electric current in  FIG. 6  is logarithmically plotted; 
           [0089]      FIG. 8  is a drawing of a NAND circuit; 
           [0090]      FIG. 9  is a summary top view of the semiconductor device relating to the second embodiment of the present invention which functions as a NAND circuit; 
           [0091]      FIG. 10  is a cross-sectional view along the line a-a′ of the semiconductor device in  FIG. 9 ; 
           [0092]      FIG. 11  is a cross-sectional view along the line b-b′ of the semiconductor device in  FIG. 9 ; 
           [0093]      FIG. 12  is a cross-sectional view along line c-c′ of the semiconductor device in  FIG. 9 ; 
           [0094]      FIG. 13  is a cross-sectional view along line d-d′ of the semiconductor device in  FIG. 9 ; 
           [0095]      FIG. 14A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0096]      FIG. 14B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 14A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0097]      FIG. 14C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 14A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0098]      FIG. 15A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0099]      FIG. 15B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 15A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0100]      FIG. 15C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 15A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0101]      FIG. 16A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0102]      FIG. 16B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 16A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0103]      FIG. 16C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 16A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0104]      FIG. 17A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0105]      FIG. 17B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 17A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0106]      FIG. 17C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 17A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0107]      FIG. 18A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0108]      FIG. 18B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 18A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0109]      FIG. 18C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 18A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0110]      FIG. 19A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0111]      FIG. 19B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 19A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0112]      FIG. 19C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 19A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0113]      FIG. 20A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0114]      FIG. 20B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 20A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0115]      FIG. 20C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 20A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0116]      FIG. 21A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0117]      FIG. 21B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 21A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0118]      FIG. 21C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 21A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0119]      FIG. 22A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0120]      FIG. 22B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 22A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0121]      FIG. 22C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 22A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0122]      FIG. 23A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0123]      FIG. 23B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 23A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0124]      FIG. 23C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 23A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0125]      FIG. 24A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0126]      FIG. 24B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 24A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0127]      FIG. 24C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 24A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0128]      FIG. 25A  is a top view showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0129]      FIG. 25B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 25A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0130]      FIG. 25C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 25A  showing an example of producing a semiconductor device according to a second embodiment of the present invention; 
           [0131]      FIG. 26  is a summary top view of a semiconductor device relating to a third embodiment of the present invention functioning as a NAND circuit; 
           [0132]      FIG. 27  is the line a-a′ of the semiconductor device in  FIG. 26 ; 
           [0133]      FIG. 28  is the line b-b′ of the semiconductor device in  FIG. 26 ; 
           [0134]      FIG. 29  is the line c-c′ of the semiconductor device in  FIG. 26 ; 
           [0135]      FIG. 30  is the line d-d′ of the semiconductor device in  FIG. 26 ; 
           [0136]      FIG. 31A  is a top view showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0137]      FIG. 31B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 31A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0138]      FIG. 31C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 31A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0139]      FIG. 32A  is a top view showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0140]      FIG. 32B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 32A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0141]      FIG. 32C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 32A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0142]      FIG. 33A  is a top view showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0143]      FIG. 33B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 33A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0144]      FIG. 33C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 33A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0145]      FIG. 34A  is a top view showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0146]      FIG. 34B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 34A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0147]      FIG. 34C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 34A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0148]      FIG. 35A  is a top view showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0149]      FIG. 35B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 35A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0150]      FIG. 35C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 35A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0151]      FIG. 36A  is a top view showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0152]      FIG. 36B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 36A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0153]      FIG. 36C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 36A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0154]      FIG. 37A  is a top view showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0155]      FIG. 37B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 37A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0156]      FIG. 37C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 37A  showing an example of producing a semiconductor device according to a third embodiment of the present invention; 
           [0157]      FIG. 38  is a summary top view of the semiconductor device relating to a fourth embodiment of the present invention functioning as a NAND circuit; 
           [0158]      FIG. 39  is the line a-a′ of the semiconductor device in  FIG. 38 ; 
           [0159]      FIG. 40  is the line b-b′ on a semi-conductor device in  FIG. 38 ; 
           [0160]      FIG. 41  is the line c-c′ of the semiconductor device in  FIG. 38 ; 
           [0161]      FIG. 42  is the line d-d′ of the semiconductor device in  FIG. 38 ; 
           [0162]      FIG. 43A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0163]      FIG. 43B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 43A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0164]      FIG. 43C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 43A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0165]      FIG. 44A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0166]      FIG. 44B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 44A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0167]      FIG. 44C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 44A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0168]      FIG. 45A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0169]      FIG. 45B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 45A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0170]      FIG. 45C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 45A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0171]      FIG. 46A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0172]      FIG. 46B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 46A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0173]      FIG. 46C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 46A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0174]      FIG. 47A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0175]      FIG. 47B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 47A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0176]      FIG. 47C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 47A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0177]      FIG. 48A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0178]      FIG. 48B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 48A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0179]      FIG. 48C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 48A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0180]      FIG. 49A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0181]      FIG. 49B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 49A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0182]      FIG. 49C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 49A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0183]      FIG. 50A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0184]      FIG. 50B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 50A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0185]      FIG. 50C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 50A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0186]      FIG. 51A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0187]      FIG. 51B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 51A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0188]      FIG. 51C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 51A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0189]      FIG. 52A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0190]      FIG. 52B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 52A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0191]      FIG. 52C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 52A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0192]      FIG. 53A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0193]      FIG. 53B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 53A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0194]      FIG. 53C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 53A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0195]      FIG. 54A  is a top view showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0196]      FIG. 54B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 54A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0197]      FIG. 54C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 54A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0198]      FIG. 55  is a summary top view of a semiconductor device relating to a fifth embodiment of the present invention which functions as a NAND circuit; 
           [0199]      FIG. 56  is the line a-a′ of the semiconductor device in  FIG. 55 ; 
           [0200]      FIG. 57  is the line b-b′ of the semiconductor device in  FIG. 55 ; 
           [0201]      FIG. 58  is the line c-c′ of the semiconductor device in  FIG. 55 ; 
           [0202]      FIG. 59  is the line d-d′ of the semi conductor device in  FIG. 55 ; 
           [0203]      FIG. 60A  is a top view showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0204]      FIG. 60B  is a cross-sectional view along the line a-a′ of the semiconductor device in  FIG. 60A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0205]      FIG. 60C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 60A  showing an example of producing a semiconductor device according to a fourth embodiment of the present invention; 
           [0206]      FIG. 61A  is a top view showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0207]      FIG. 61B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 61A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0208]      FIG. 61C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 61A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0209]      FIG. 62A  is a top view showing an example of producing a semiconductor device according to a fifth embodiment of the present invention. 
           [0210]      FIG. 62B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 62A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0211]      FIG. 62C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 62A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0212]      FIG. 63A  is a top view showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0213]      FIG. 63B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 63A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0214]      FIG. 63C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 63A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0215]      FIG. 64A  is a top view showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0216]      FIG. 64B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 64A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0217]      FIG. 64C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 64A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0218]      FIG. 65A  is a top view showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0219]      FIG. 65B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 65A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0220]      FIG. 65C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 65A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0221]      FIG. 66A  is a top view showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0222]      FIG. 66B  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 66A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0223]      FIG. 66C  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 66A  showing an example of producing a semiconductor device according to a fifth embodiment of the present invention; 
           [0224]      FIG. 67  is a planar drawing showing a transistor according to a sixth embodiment of the present invention; 
           [0225]      FIG. 68  is a cross-sectional view along line a-a′ of the semiconductor device in  FIG. 67 ; 
           [0226]      FIG. 69  is a cross-sectional view along line b-b′ of the semiconductor device in  FIG. 67 ; 
           [0227]      FIG. 70  is a cross-sectional view along line c-c′ of the semiconductor device in  FIG. 67 ; 
           [0228]      FIG. 71  is a cross-sectional view along line d-d′ of the semiconductor device in  FIG. 67 ; 
           [0229]      FIG. 72  is an electric current-voltage drawing of a transistor concerning a first and sixth embodiment accomplished by means of model simulation analysis with the gate electric current (Id) plotted logarithmically; 
           [0230]      FIG. 73  is an electric current-voltage drawing in which the electric current in  FIG. 72  is plotted linearly; 
           [0231]      FIG. 74  is a summary top view of a semiconductor device concerning a seventh embodiment of the present invention functioning as a NAND circuit; 
           [0232]      FIG. 75  is the line a-a′ of the semiconductor device in  FIG. 74 ; 
           [0233]      FIG. 76  is the line b-b′ of the semiconductor device in  FIG. 74 ; 
           [0234]      FIG. 77  is the line c-c′ of the semiconductor device in  FIG. 74 ; 
           [0235]      FIG. 78  is the line d-d′ of the semiconductor device in  FIG. 74 ; 
           [0236]      FIG. 79  is a summary top view of a semiconductor device concerning an eighth embodiment of the present invention functioning as a NAND circuit; 
           [0237]      FIG. 80  is the line a-a′ of the semiconductor device in  FIG. 79 ; 
           [0238]      FIG. 81  is the line b-b′ of the semiconductor device in  FIG. 79 ; 
           [0239]      FIG. 82  is the line c-c′ of the semiconductor device in  FIG. 79 ; 
           [0240]      FIG. 83  is the line d-d′ of the semiconductor device in  FIG. 79 ; 
           [0241]      FIG. 84  is a summary top view of a ninth embodiment of the present invention functioning as a NAND circuit; 
           [0242]      FIG. 85  is the line a-a′ of the semiconductor device in  FIG. 84 ; 
           [0243]      FIG. 86  is the line b-b′ of the semiconductor device in  FIG. 84 ; 
           [0244]      FIG. 87  is the line c-c′ of the semiconductor device in  FIG. 84 ; 
           [0245]      FIG. 88  is the line d-d′ of the semiconductor device in  FIG. 84 ; 
           [0246]      FIG. 89  is a summary top view of a semiconductor device concerning a seventh embodiment functioning as a NAND circuit; 
           [0247]      FIG. 90  is the line a-a′ of the semiconductor device in  FIG. 89 ; 
           [0248]      FIG. 91  is the line b-b′ of the semiconductor device in  FIG. 89 ; 
           [0249]      FIG. 92  is the line c-c′ of the semiconductor device in  FIG. 89 ; 
           [0250]      FIG. 93  is the line d-d′ of the semiconductor device in  FIG. 89 ; 
           [0251]      FIG. 94  is a bird&#39;s-eye view showing one example of a conventional SGT, and a cross-section along line A-A′ therein; 
           [0252]      FIG. 95  is a cross-sectional view showing one example of a conventional SGT; 
           [0253]      FIG. 96  is a cross-sectional view showing one example of a conventional SGT; and 
           [0254]      FIG. 97  is a cross-sectional view showing one example of a conventional SGT. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0255]    A detailed explanation of the semiconductor element and semiconductor device relating to the present invention is provided hereafter, with reference to the drawings. 
       First Embodiment 
     Semiconductor Element 
       [0256]    An explanation will be provided first concerning the transistor relating to the first embodiment of the present invention. The transistor relating to the embodiment is an SGT of the pMOS type or the nMOS type. 
         [0257]      FIG. 1  is a summary bird&#39;s eye view of the transistor relating to the first embodiment of the present invention.  FIG. 2  is a simplified cross-sectional view along the vertical cut line a-a′.  FIG. 3  is a simplified cross-sectional view along the horizontal cut line b-b′ in the upper part of  FIG. 2 .  FIG. 4  is a simplified cross-sectional view along the horizontal cut line c-c′ in the center part of  FIG. 2 .  FIG. 5  is a simplified cross-sectional view along the horizontal cut line d-d′ in the lower part of  FIG. 2 . 
         [0258]    The transistor relating to the first embodiment is provided with a silicon column  1010  comprising the high resistance region. Above the silicon column  1010  is arranged a silicon column  131 ; and below the silicon column  1010  is arranged silicon column  1410 . The silicon column  1010 , silicon column  1310  and silicon column  1410  are arranged as a complete circular truncated cone. In the embodiment, the silicon column  1310  functions as a source diffusion layer, and the silicon column  1410  functions as a drain diffusion layer respectively. 
         [0259]    The silicon column  1310  and the silicon column  1410  are of the p type and n type, into which the impurities of arsenic and boron are introduced. The silicon column  1010  between the silicon column  1310  and a silicon column  1410  functions as a channel region. A first gate insulating film  310  is arranged so as to encompass the silicon column  1010 . The first gate insulating film  310  is a high-k film, composed for example, of a silicon oxynitride film, a silicon nitride film, hafnium oxide, hafnium oxynitride, and lanthanum oxide, and the like. The gate electrode  210  is arranged so as to encompass the first gate insulating film  310 . Gate electrode  210  is composed for example from titanium, titanium nitride, tantalum, tantalum nitride and tungsten, and the like. 
         [0260]    In the present embodiment, during operation, a channel is formed in the silicon column  1010  by impressing voltage on the gate electrode  210 . 
         [0261]    The SGT relating to the present embodiment is an overall circular truncated cone. Owing to this, as shown in  FIG. 2 , its vertical cross-section is shaped like a trapezoid, and as shown in  FIGS. 3-5  the horizontal cross-section is a circular shape. In the embodiment, the diameter Td of the contact surface between the silicon column  1010  and the silicon column  1410  comprising the drain diffusion layer is larger than the diameter Ts of the contact surface between the silicon column  1010  and the silicon column  1310  comprising the source of diffusion layer. By this means, as explained hereafter, the transistor ON/OFF current ratio relating to the present embodiment is relatively large. 
         [0262]    Regarding a transistor composed where Ts&lt;Td, the fact that the ON/OFF current ratio is greater than that of a transistor composed where Td&lt;Ts is explained based on the analytical results of model simulation. In order to examine the ON/OFF current ratio of a trapezoid cross-section transistor flow, two types of transistor models were designed and simulation testing performed. Each of the two types of transistors used in the tests had, in common, a metal gate in which, the gate length (L) is 100 nm, the work function is 4.3 eV, the film thickness of the gate insulating film is 2 nm, the height of the silicon column which functions as a channel region is 100 nm and the impurity concentration of its P type impurity region is 10 15  (/cm 3 ) (for a summary form reference is made to  FIG. 1 ). 
         [0263]    In the transistor composed where Ts&lt;Td, Td is 100 nm and Ts is 80 nm. In the transistor composed where Td&lt;Ts, Td is 80 nm and Ts is 100 nm. The silicon column functioning as a source region with the height of 100 nm and the silicon column functioning as a drain region with the height of 100 nm are truncated cone-shaped as the silicon column functioning as the channel region (for a summary form reference is made to  FIG. 1 ). In addition, the impurity concentration of the N-type impurity region of these columns is 10 20  (/cm 3 ). 
         [0264]    Using the above structure, the drain flow voltage dependency was calculated by solving the Poisson equation and the drift diffusion transport equation. In addition, consideration was also given to the Boltzmann carrier statistical model, the Shockley lead whole recombination model and the Darwish CVT mobility model. 
         [0265]      FIG. 6  is a block diagram of the drain current (Id) of the simulation results using these transistor models and the gate voltage (Vg). In addition,  FIG. 7  is a drawing which plot the simulation results of  FIG. 6  and the drain current (Id) using logarithms, and shows a magnification of the drain current (Id). With this experiment, the ON current is equal to the drain current (Id) when the drain voltage (Vd) and the gate voltage (Vg) is 1.2 V, and the OFF leakage current is equal to the drain current (Id) when the gate voltage (Vg) is OV. As shown in  FIG. 6 , the ON current of a transistor composed where Td&lt;Ts is greater than the ON current composed where Ts&lt;Td. In addition, as shown in  FIG. 6  and  FIG. 7 , the OFF leakage current of the transistor composed where Td&lt;Ts is substantially the same as the OFF leakage current of a transistor composed where Ts&lt;Td. From these results, for a transistor composed where Ts&lt;Td, in comparison with a transistor composed where Td&lt;Ts, it is understood that the ON current is great where the OFF leakage current does not change. 
         [0266]    As indicated above, the transistor relating to the present embodiment shows a relatively large ON current with the above structure in which Ts&lt;Td. Owing to this, the transistor is capable of high speed operation. 
       Second Embodiment 
     Semiconductor Device 
       [0267]    The first embodiment explained only a single semiconductor element. However, with the second embodiment, an explanation is provided of the example of a semiconductor device composed of multiple units of the semiconductor elements relating to the first embodiment. The semiconductor device relating to the second embodiment functions as a NAND circuit. An electronic circuit diagram of a NAND circuit is shown in  FIG. 8 . Moreover, the NAND circuit shows nothing more than an example of an electronic circuit. Other circuits are also capable of creating high-speed operation through the use of the transistor relating to the first embodiment. 
         [0268]      FIG. 9  is a summary top view of a semiconductor device relating to the second embodiment of the present invention.  FIG. 10  is a simplified cross-sectional view along the cut line a-a′ in  FIG. 9 .  FIG. 11  is a simplified cross-sectional view along the cut line b-b′ in  FIG. 9 .  FIG. 12  is a simplified cross-sectional view along the cut line c-c′ in  FIG. 9 .  FIG. 13  is a simplified cross-sectional view along the cut line d-d′ in  FIG. 9 . 
         [0269]    As shown in  FIG. 9 , the semiconductor device relating to the present embodiment is composed from an SGT relating to four first embodiments arranged in two rows and two columns. The width of each SGT channel is equal to the perimeter length of the silicon column. With the present embodiment, since the size of each SGT silicon column is equal, the width of each SGT channel is also equal. 
         [0270]    In order to accomplish circuit optimization, in the case of increasing the SGT channel width by increasing the diameter of the silicon column, since there will also be an accompanying current leakage, which leads to concern of an increase in the amount of power consumed by the circuit, or to the operational deficiency of the circuit. Therefore, in the present embodiment, in the case of increasing some SGT channel width, it would be desirable to connect in parallel multiple SGT units having the same diameter silicon column as the SGT silicon column, mutually to the gates, drain region and source region. By this means, the channel width can be increased and the circuit optimized without increasing the amount of current leakage. This method for obtaining increased channel width by connecting the SGT in parallel is not limited to NAND circuits, but may be applied to all other circuits as well. 
         [0271]    The first SGT arranged in a 1st row 1st column is provided with a silicon column  1010  comprising the high resistance region. The silicon column  1010  forms the ordered taper of a circular truncated cone. The first insulating body  310  is arranged on an upper side surface of the silicon column  1010  so as to encompass the silicon column  1010 . A gate electrode  210  is arranged on a side surface of the first insulating body  310  so as to encompass the first insulating body  310 . On the lower part of the silicon column  1010  is arranged a p+ high-density impurity region  410  (drain region), and on the upper part, is arranged a p+ high density impurity region  510 , respectively. The p+ high-density impurity region  410  (drain region) is arranged on an oxide film  120  formed above a semiconductor substrate  100 . On the upper part of the p+ high-density impurity region  410 , is formed a silicide region  610 , and on the upper part of the p+ high-density impurity region  510  is formed a silicide region  710 , respectively. On the silicide region  710  is arranged a contact  1280 . 
         [0272]    With the first SGT, the diameter Ts 1  of the contact cross-sectional surface between the silicon column  1010  and the p+ high-density impurity region  510  is smaller than the diameter Td 1  of the contact cross-sectional surface between the silicon column  1010  and the p+ high-density impurity region  410 . 
         [0273]    The second SGT arranged in the 2nd row 1st column is provided with a silicon column  1020  comprising a high resistance region. Overall, the silicon column  1020  has an ordered tapered circular truncated cone. In order to encompass the silicon column  1020 , a first insulating body  320  is arranged on a side surface of the silicon column  1020 . In order to encompass the first insulating body  320 , a gate electrode  220  is arranged on the side surface of the first insulating body  320 . On the lower part of the silicon column  1020  is arranged a p+ high-density impurity region  410  (drain region), and on the upper part is arranged a p+ high-density impurity region  520  (source region), respectively. The p+ high-density impurity region  410  (drain region) is arranged on the oxide film  120  formed on the semiconductor substrate  100 . On the upper part of the p+ high-density impurity region  420  is formed a silicide region  610 , and on the upper part of the p+ high-density impurity region  520 , a silicide region  720 , respectively. 
         [0274]    On the silicide region  720  is arranged a contact  1230 . On the contact  1230  is arranged metal wiring  1130 . The metal wiring  1130  is connected to a first SGT contact and an electric source potential Vcc. 
         [0275]    With the second SGT, the diameter Ts 2  of the contact cross-sectional surface between the silicon column  1020  and the p+ high-density impurity region  520  is smaller than the diameter Td 2  of the contact cross-sectional surface between the silicon column  1020  and the p+ high-density impurity region  410 . 
         [0276]    The third SGT arranged in the 2nd row 2nd column is provided with a silicon column  1030  comprising a high resistance region. The silicon column  1030  forms an overall ordered tapered circular truncated cone. In order to encompass the silicon column  1030 , a first insulating body  330  is arranged on the side surface of the silicon column  1030 . In order to compass the first insulating body  330 , a gate electrode  220  is arranged on the side surface of the first insulating body  330 . On the lower part of the silicon column  1030  is arranged an n+ high-density impurity region  420  (drain region), and on the upper part is arranged an n+ high-density impurity region  530  (source region), respectively. The n+ high density impurity region  420  (drain region) is arranged on the oxide film  120  formed on the semiconductor substrate  100 . On the upper part of the n+ high-density impurity region  420  is formed a silicide region  610 , and on the upper part of the n+ high-density impurity region  530  is formed a silicide region  730 , respectively. On the silicide region  730 , is arranged a contact  1240 . 
         [0277]    With the third SGT, the diameter Ts 3  of the contact cross-sectional surface of the silicon column  1030  and the n+ high density impurity region  530  is smaller than the diameter Td 3  of the contact surface between the silicon column  1030  and the n+ high density impurity region  410 . 
         [0278]    The fourth SGT arranged in the 1st row 2nd column is provided with a silicon column  1040  comprising a high resistance region. The silicon column  1040  forms an overall reverse taper circular truncated cone. In order to encompass the silicon column  1040  the first insulating body  340  is arranged on the side surface of the silicon column  1040 . In order to encompass the first insulating body  340 , a gate electrode  210  is arranged on the side surface of the first insulating body  340 . On the lower part of the silicon column  1040  is arranged an n+ high-density impurity region  420  (source region), and on the upper part is arranged an n+ high-density impurity region  540  (drain region), respectively. The n+ high-density impurity region  420  is arranged on the oxide film  120  formed on the semiconductor substrate  100 . On the upper part of the n+ high-density impurity region  420  is formed a silicide region  620 , and on the upper part of the n+ high-density impurity region  540  is formed a silicide region  740 , respectively. On the silicide region  740  is arranged a contact  1270 . On the contact  1270  is arranged metal wiring  1140 . The metal wiring  1140  is connected to the third SGT contact  1240 . 
         [0279]    With the fourth SGT, the diameter Ts 4  of the contact cross-sectional surface of the silicon column  1040  and the n+ high density impurity region  420  is smaller than the diameter Td 4  of the contact surface between the silicon column  1040  and the n+ high density impurity region  540 . 
         [0280]    In addition, on the first SGT gate  210  is arranged a contact  1210 . On the contact  1210 , is arranged metal wiring  1110 . Metal wiring  1110  is connected to input electric potential Vinb. On the gate  220  of the second SGT is arranged a contact  1220 . On the contact  1220  is arranged metal wiring  1120 . Metal wiring  1120  is connected to input electric potential Vina. On the third SGT n+ high-density impurity region  420  is arranged a contact  1250 . On the contact  1250  is arranged metal wiring  1150 . The metal wiring  1150  is connected to output electric potential Vout. On the fourth SGT n+ high-density impurity region  420  is arranged a contact  1260 . On the contact  1260  is arranged metal wiring  1160 . Metal wiring  1160  is connected to ground potential Vss. The silicide region  610  formed on the first SGT p+ high-density impurity region  410  is connected to the second SGT p+ high-density impurity region  410  and the third SGT n+ high-density impurity region  420 . In addition, on the side surface of the p+ high-density region  410  and the n+ high-density impurity region  420  is formed an element isolation insulating film  910 . 
         [0281]    With the present embodiment, all of the transistors composing the electronic circuit have the same structure as the transistors relating to the first embodiment, and since it is high-speed operation capable, the semiconductor device relating to the present embodiment is also capable of high-speed operation. 
         [0282]    Next, an explanation is provided of an example of a production method of the semiconductor device relating to the second embodiment of the present invention, with reference to  FIG. 14  A- FIG. 25C . Moreover, in these drawings, the same labels are applied relative to the same structural elements. In  FIG. 14A-FIG .  25 C, A is a planar drawing, B is a cross-sectional view along the line a-a′, and C is a cross-sectional view along the line b-b′. 
         [0283]    As shown in  FIG. 14A-FIG .  14 C, on the Si substrate  100  is chronologically formed a BOX layer  120 , an SOI layer  110 , pad oxide film  121  and nitride film  130 . 
         [0284]    The resist pattern numbers  141 ,  142 ,  143  and  144  of the cylindrical shape are formed on the scheduled location for forming column silicon. Continuing, by means of dry etching, formation is accomplished of nitride films  131 ,  132 ,  133  and  134  and oxide films  121 ,  122 ,  123 , and  124  in respective cylindrical shapes. The semiconductor device involving these steps is shown in  FIG. 15A-FIG .  15 C. Continuing, resist patterns  141 ,  142 ,  143  and  144  are removed. 
         [0285]    By means of etching, silicon columns  111 ,  112 ,  113 , and  114  are respectively formed below nitride films  131 ,  132 ,  133  and  134 . These steps are shown in  FIG. 16A-FIG .  16 C. 
         [0286]    Nitride film  135  is formed on the results and substance of the process. Continuing, resist pattern number  145  is formed on the nitride film  135 . The semiconductor device involved in the steps is shown in  FIG. 17A-FIG .  17 C. Moreover, since nitride films  131 ,  132 ,  133  and  134  are pressed into the nitride film  135 , the nitride film number  135  is viewed as a unit. 
         [0287]    Using the resist pattern  145 , nitride film  139  is formed by etching. At this time, the nitride film  139  is formed by means of a side well of the nitride film  135  formed from nitride film  134  and etching. Continuing, the resist pattern  145  is removed. The semiconductor device involved in these steps is shown in  FIG. 18-FIG .  18 C. 
         [0288]    Using nitride films  135  and  139 , as shown in  FIG. 19A-19C , a reverse taper silicon column  118  is formed by means of dry etching. 
         [0289]    As shown in  FIG. 20A-FIG .  20 C, an oxide film is formed on the resultant substance, and a flattened oxide film  125  is formed using CMP (Chemical Mechanical Polishing). 
         [0290]    As shown in  FIG. 21A-FIG .  21 C, a resist pattern  146  is formed on the resultant substance. 
         [0291]    Using a resist pattern number  146 , nitride films  136 ,  137  and  138  are formed by etching of the oxide film  125  and the nitride film  135 . At this time, the nitride film  136  is formed by the side well of the nitride film  135  formed by nitride film  131  and etching. The nitride film  137  is formed by the side well of the nitride film  135  formed by nitride film  132  and etching. Nitride film number  138  is formed by the side well out nitride film  135  formed by the nitride film  133  and etching. Continuing, the transistor pattern  146  is removed. The semiconductor device involved in the steps is shown in  FIG. 22A-FIG .  22 C. 
         [0292]    As shown in  FIG. 23A-FIG .  23 C, using nitride films  136 ,  137  and  138 , ordered taper silicon columns  115 ,  116  and  117  are respectively formed by dry etching. 
         [0293]    As shown in  FIG. 24A-FIG .  24 C, nitride films  136 ,  137 ,  138  and  139  and oxide films  121 ,  122 ,  123  and  124  are removed. 
         [0294]    As shown in  FIG. 25A-FIG .  25 C, element separating insulation film  910 , gate electrodes  210  and  220 , contacts  1210 ,  1220 ,  1230 ,  1240 ,  1250 ,  1260 ,  1270  and  1280 , and metal wiring  1110 ,  1120 ,  1130 ,  1140 ,  1150  and  1160  are formed. 
       Third Embodiment 
     Semiconductor Device 
       [0295]    The semiconductor device relating to the second embodiment is composed of an SCT which has an ordered taper silicon column and an SGT which has a reverse taper silicon column. Owing to this, at the time of producing a semiconductor device, there was a need for formation to be separately accomplished by an SGT which had an ordered taper silicon column and an SGT which has a reverse taper silicon column. Therefore, a semiconductor device is shown in which all of the SGT silicon columns all have an ordered taper. 
         [0296]      FIG. 26  is a summary top view of the semiconductor device relating to a third embodiment of the present invention.  FIG. 27  is a simplified cross-sectional view along the cut line a-a′ of  FIG. 26 .  FIG. 28  is a simplified cross-sectional view along the cut line b-b′ of  FIG. 26 .  FIG. 29  is a simplified cross-sectional view along the cut line c-c′ of  FIG. 26 .  FIG. 30  is a simplified cross-sectional view along the cut line d-d′ of  FIG. 26 . 
         [0297]    The semiconductor device relating to the present embodiment is composed from an SGT relating to 4 first embodiments arrange in a 2nd row 2nd column. The channel width of each SGT is equal to the peripheral length of the silicon column. With the present embodiment, since the size of the silicon column of each SGT is equal, the channel width of each SGT is also equal. 
         [0298]    The first SGT arranged in the 1st row 1st column is provided with a silicon column  1010  comprising a high resistance region. The silicon column  1010  has an ordered tapered circular truncated cone. In order to encompass the silicon column  1010 , a first insulating body  310  is arranged on a side surface of the silicon column  1010 . In order to encompass the first insulating body  310 , a gate electrode  210  is arranged on the side surface of the first insulating body  310 . On the lower part of the silicon column  1010  is arranged a p+ high-density impurity region  410  (drain region), and on the upper part is arranged a p+ high-density impurity region  510  (source region), respectively. The p+ high-density impurity region  410  (drain region) is arranged on the oxide film  120  formed on the semiconductor substrate  100 . On the upper part of the p+ high-density impurity region  410  is formed a silicide region  610 , and on the upper part of the p+ high-density impurity region  510 , is formed a silicide region  710 , respectively. On the silicide region  710  is arranged a contact  1280 . 
         [0299]    With the first SGT, the diameter Ts 1  of the contact cross-sectional surface between the silicon column  1010  and the p+ high-density impurity region  510  is smaller than the diameter Td 1  of the contact cross-sectional surface between the silicon column  1010  and the p+ high-density impurity region  410 . 
         [0300]    The second SGT arranged in the 2nd row 1st column is provided with a silicon column  1020  comprising a high resistance region. The silicon column  1020  has an ordered tapered circular truncated cone. In order to encompass the silicon column  1020 , a first insulating body  320  is arranged on a side surface of the silicon column  1020 . In order to encompass the first insulating body  320 , a gate electrode  220  is arranged on the side surface of the first insulating body  330 . On the lower part of the silicon column  1020  is arranged a p+ high-density impurity region  410  (drain region), and on the upper part is arranged a p+ high-density impurity region  520  (source region), respectively. 
         [0301]    The p+ high-density impurity region  410  (drain region) is arranged on the oxide film  120  formed on the semiconductor substrate  100 . On the upper part of the p+ high-density impurity region  410  is formed a silicide region  610 , and on the upper part of the p+ high-density impurity region  520 , is formed a silicide region  720 , respectively. On the silicide region  720  is arranged a contact  1230 . On the contact  1230  is arranged metal wiring  1130 . The metal wiring  1130  is connected to the contact  1280  of the first SGT and the electricity source and electric potential Vcc. 
         [0302]    With the second SGT, the diameter Ts 2  of the contact cross-sectional surface between the silicon column  1020  and the p+ high-density impurity region  520  is smaller than the diameter Td 2  of the contact cross-sectional surface between the silicon column  1020  and the p+ high-density impurity region  410 . 
         [0303]    The third SGT arranged in the 2nd row 2nd column is provided with a silicon column  1030  comprising a high resistance region. The silicon column  1030  has an overall ordered tapered circular truncated cone. In order to encompass the silicon column  1030 , a first insulating body  330  is arranged on a side surface of the silicon column  1030 . In order to encompass the first insulating body  330 , a gate electrode  220  is arranged on the side surface of the first insulating body  330 . 
         [0304]    On the lower part of the silicon column  1030  is arranged an n+ high-density impurity region  430  (drain region), and on the upper part is arranged an n+ high-density impurity region  530  (source region), respectively. The n+ high-density impurity region  430  (drain region) is arranged on the oxide film  120  formed on the semiconductor substrate  100 . On the upper part of the n+ high-density impurity region  430  is formed a silicide region  610 , and on the upper part of the n+ high-density impurity region  530 , is formed a silicide region  730 , respectively. On the silicide region  730  is arranged a contact  1240 . 
         [0305]    With the third SGT, the diameter Ts 3  of the contact cross-sectional surface between the silicon column  1030  and the n+ high-density impurity region  530  is smaller than the diameter Td 3  of the contact cross-sectional surface between the silicon column  1030  and the n+ high-density impurity region  430 . 
         [0306]    The fourth SGT arranged in the 1st row 2nd column is provided with a silicon column  1040  comprising a high resistance region. The silicon column  1040  has an overall reverse taper circular truncated cone. In order to encompass the silicon column  1040 , a first insulating body  340  is arranged on a side surface of the silicon column  1040 . In order to encompass the first insulating body  340 , a gate electrode  210  is arranged on the side surface of the first insulating body  340 . On the lower part of the silicon column  1040  is arranged an n+ high-density impurity region  420  (drain region), and on the upper part is arranged an n+ high-density impurity region  540  (source region), respectively. 
         [0307]    The n+ high-density impurity region  420  (drain region) is arranged on the oxide film  120  formed on the semiconductor substrate  100 . On the upper part of the n+ high-density impurity region  420  is formed a silicide region  620 , and on the upper part of the n+ high-density impurity region  540 , is formed a silicide region  740 , respectively. On the silicide region  740  is arranged a contact  1270 . 
         [0308]    With the fourth SGT, the diameter Ts 4  of the contact cross-sectional surface between the silicon column  1040  and the n+ high-density impurity region  540  is smaller than the diameter Td 4  of the contact cross-sectional surface between the silicon column  1040  and the n+ high-density impurity region  420 . 
         [0309]    In addition, on the gate electrode  210  of the first SGT is arranged a contact  1210 . On contact  1210  is arranged metal wiring  1110 . Metal wiring  1110  is connected to a second input electric potential Vinb. On the gate electrode  220  of the second SGT is arranged the contact  1220 . On the contact  1220 , is arranged metal wiring  1120 . Metal wiring  1120  is connected to the first input electric potential Vina. The silicide region  610  formed on the third SGT n+ high-density impurity region  430  is connected to the contact  1250 . On the contact  1250  is arranged metal wiring  1140 . Metal wiring  1140  is connected to the output potential Vout. The silicide region  624  formed on the upper part of the fourth SGT n+ high-density impurity region  420  is connected to contact  1260 . On contact  1260  is arranged wiring  1150 . Metal wiring  1150  is connected to the third SGT contact  1240 . Silicide  610  connected to the first SGT p+ high-density impurity region is connected to the second SGT p+ high-density impurity region and to the third SGT n+ high-density impurity region. In addition, an element separating insulating film  910  is formed on the side surface of the p+ high-density impurity region  410  and on the n+ high-density impurity region  420 . 
         [0310]    With the present embodiment, all of the transistors compose electronic circuits, but are the same structure as the transistors of the first embodiment. Since it is capable of high speed operation, the semiconductor device relating to the present embodiment is also capable of high-speed operation. In addition, since the silicon columns are all ordered circular truncated cones, the production of the silicon columns can be accomplished in a single step. Therefore, the production of the semiconductor device relating to the present invention is simplified. 
         [0311]    Next, an example of a production method of the semiconductor device relating to the second embodiment of the present invention is explained with reference to  FIG. 31A-FIG .  37 C. Moreover, these drawings have the same labels applied relative to the same structural elements. In  FIG. 31A-FIG .  37 C, A is a planar view, B is a cross-sectional view along the line a-a′, and C is a cross-sectional view along the line b-b′. 
         [0312]    As shown in  FIG. 31A-FIG .  31 C, on a Si substrate  100 , a BOX layer  120 , an SOI layer  110 , a pad oxide film  121 , and a nitride film  130  are chronologically formed. 
         [0313]    In the scheduled location on which is formed a silicon column, are formed cylindrical resist patterns  141 ,  142 ,  143 , and  144 . Continuing, by means of dry etching, nitride films  131 ,  132 ,  133  and  134 , and oxide films  121 ,  122 ,  123 , and  124  are respectively formed into cylindrical shapes. The semiconductor devices involved in these steps are shown in  FIGS. 32A-32C . Continuing, the resists omit patterns  141 ,  142 ,  143  and  144 . 
         [0314]    By means of etching, silicon columns  111 ,  112 ,  113  and  114  are respectively formed below nitride films  131 ,  132 ,  133  and  134 . The semiconductor device involved in these steps is shown in  FIG. 33A-FIG .  33 C. 
         [0315]    Nitride film  135  is formed in the process results, and etching is performed. As a result, as shown in  FIGS. 34A-34C , formation is accomplished of nitride film  136  in which the sidewall of the nitride film  135  is formed on the side surface of the nitride film  131 , and nitride film  137  in which the nitride film  135  sidewall is formed on the side surface of nitride film  132 , and nitride film  138  in which the nitride film  135  sidewall is formed on the side surface of the nitride film  133  and nitride film  139  in which the nitride film  135  side wall is formed on the side surface of the nitride film  134 . 
         [0316]    Using nitride films  136 ,  137 ,  138  and  139 , as shown in  FIGS. 35A-35C , ordered tapered type silicon columns  115 ,  116 ,  117  and  118  are respectively formed by dry etching. 
         [0317]    As shown in  FIG. 36A-FIG .  36 C, nitride films  136 ,  137 ,  138  and  139 , and oxide films  121 ,  122 ,  123  and  124  are removed. 
         [0318]    As shown in  FIG. 37A-FIG .  37 C element separation insulating film  910 , gate electrodes  210  and  220 , contacts  1210 ,  1220 ,  1230 ,  1240 ,  1250 ,  1260 ,  1270  and  1280 , and wiring  1110 ,  1120 ,  1130 ,  1140 ,  1150  and  1160  are formed. 
       Fourth Embodiment 
     Semiconductor Device 
       [0319]    With the semiconductor device relating to the second embodiment, an SOI substrate is used as the substrate. The fourth embodiment shows a semiconductor device in which use is made of a bulk substrate as the substrate. 
         [0320]      FIG. 38  is a summary top view of a semiconductor device relating to the fourth embodiment of the present invention.  FIG. 39  is a simplified cross-sectional view along the cut line a-a′ of  FIG. 38 .  FIG. 40  is a simplified cross-sectional view along the cut line b-b′ of  FIG. 38 .  FIG. 41  is a simplified cross-sectional view along the cut line c-c′ of  FIG. 38 .  FIG. 42  is a simplified cross-sectional view on the cut line d-d′ of  FIG. 38 . 
         [0321]    The semiconductor device relating to the present embodiment is composed from an SGT relating to 4 of the first embodiments arranged in the 2nd row 2nd column. Each SGT channel width is equal in terms of the length of the peripheral length of the silicon column. In the present embodiment, since the size of each SGT silicon column is equal, the width of each SGT channel is also equal. 
         [0322]    The first SGT arranged in the 1st row 1st column is provided with a silicon column comprising a high resistance region. The silicon column  1010  forms a reverse taper circular truncated cone. In order to encompass the silicon column  1010 , the first insulating body  310  is arranged on the side surface of the silicon column  1010 . In order to encompass the first insulating body  310 , gate electrode  210  is arranged on the side surface the first insulating body  310 . On the lower part of the silicon column  1010  is arranged a p+ high-density impurity region  410  (source region), and on the upper part is arranged a p+ high-density impurity region  510  (drain region), respectively. The p+ high-density impurity region  410  is arranged on the N well  810 . On the upper part of the p+ high-density impurity region  410  is arranged a silicide region  610 , and on the upper part of the p+ high-density impurity region  510  is arranged a silicide region  710 . On the silicide region  710  is arranged a contact  1270 . 
         [0323]    The diameter Ts 1  of the contact cross-sectional surface between the silicon column  1010  and the p+ high-density impurity region  410  is smaller than the diameter Td 1  of the contact cross-sectional surface between the silicon column  1010  and the p+ high-density impurity region  510 . 
         [0324]    The second SGT arranged in the 2nd row 1st column is provided with a silicon column comprising a high resistance region. The silicon column  1020  forms a reverse taper circular truncated cone. In order to encompass the silicon column  1020 , the first insulating body  320  is arranged on the side surface of the silicon column  1020 . In order to encompass the first insulating body  320 , gate electrode  220  is arranged on the side surface the first insulating body  320 . On the lower part of the silicon column  1020  is arranged a p+ high-density impurity region  410  (source region), and on the upper part is arranged a p+ high-density impurity region  520  (drain region), respectively. 
         [0325]    The p+ high-density impurity region  410  is arranged on the N well  810 . On the upper part of the p+ high-density impurity region  410  is formed a silicide region  610 , and on the upper part of the p+ high-density impurity region  520  is formed a silicide region  720 , respectively. On the silicide region  720  is arranged a contact  1230 . 
         [0326]    The diameter Ts 2  of the contact cross-sectional surface between the silicon column  1020  and the p+ high-density impurity region  410  is smaller than the diameter Td 2  of the contact cross-sectional surface between the silicon column  1020  and the p+ high-density impurity region  520 . 
         [0327]    The third SGT arranged in the 2nd row 2nd column is provided with a silicon column  1030  comprising a high resistance region. The silicon column  1030  forms an overall reverse taper circular truncated cone. In order to encompass the silicon column  1030 , the first insulating body  330  is arranged on the side surface of the silicon column  1030 . In order to encompass the first insulating body  330 , gate electrode  220  is arranged on the side surface the first insulating body  330 . On the lower part of the silicon column  1030  is arranged an n+ high-density impurity region  420  (source region), and on the upper part is arranged an n+ high-density impurity region  530  (drain region), respectively. 
         [0328]    The n+ high-density impurity region  420  is arranged on the N well  810 . On the upper part of the n+ high-density impurity region  420  is formed a silicide region  620 , and on the upper part of the n+ high-density impurity region  530  is formed a silicide region  730 , respectively. 
         [0329]    On the silicide region  730  is arranged a contact  1250 . On the contact  1250  is arranged metal wiring  1130 . The metal wiring  1130  is connected to the first SGT contact  1270  and to the second SGT contact  1230  and to the Output Electric Potential Vout. With the third SGT, the diameter Ts 3  of the contact cross-sectional surface between the silicon column  1030  and the n+ high density impurity region  410  is smaller than the diameter Td 3  of the contact cross-sectional surface between the silicon column  1030  and the n+ high density impurity region  530 . 
         [0330]    The fourth SGT arranged in the 1st row 2nd column is provided with a silicon column  1040  comprising a high resistance region. The silicon column  1040 , as an entirety, forms an ordered tapered circular truncated cone. In order to encompass the silicon column  1040 , the first insulating body  340  is arranged on the side surface of the silicon column  1040 . In order to encompass the first insulating body  340 , gate electrode  210  is arranged on the side surface the first insulating body  340 . On the lower part of the silicon column  1040  is arranged an n+ high-density impurity region  420  (drain region), and on the upper part is arranged an n+ high-density impurity region  540  (source region), respectively. The n+ high-density impurity region  420  is arranged on the P well  820 . On the upper part of the n+ high-density impurity region  420  is formed a silicide region  620 , and on the upper part of the n+ high-density impurity region  540  is formed a silicide region  740 , respectively. On the silicide region  740  is arranged a contact  1260 . On the contact  1260  is arranged metal wiring  1150 . The metal wiring  1150  is connected to the Electric Ground Potential Vss. 
         [0331]    With the fourth SGT, the diameter Ts 4  of the contact cross-sectional surface between the silicon column  1040  and the n+ high density impurity region  540  is smaller than the diameter Td 4  of the contact cross-sectional surface between the silicon column  1040  and the n+ high density impurity region  420 . 
         [0332]    In addition, on the first SGT gate electrode  210  is arranged a contact  1210 . On contact  1210  is arranged metal wiring  1110 . Metal wiring  1110  is connected to the second output electric potential Vinb. On the second SGT gate electrode  220  is arranged a contact  1220 . On the contact  1220  is arranged metal wiring  1120 . 
         [0333]    Metal wiring  1120  is connected to the first output electric potential Vina. A silicide region  610  formed on the upper part of the second SGT n+ high-density impurity region  410  is connected to the electricity source potential Vcc through contact  1240  and metal wiring  1140 . The silicide region  610  connected to the first SGT p+ high-density impurity region  410  is also connected to the second SGT p+ high-density impurity region. 
         [0334]    The silicide region  620  connected to the third SGT n+ high-density impurity region  420  is also connected to the fourth SGT n+ high-density impurity region. In addition, an element separation insulating film  910  is formed on the side surface of the p+ high-density impurity region  410  and the n+ high-density impurity region  420 . 
         [0335]    With the present embodiment, all of the transistors composing the electronic circuits have the same structure as transistors relating to the first embodiment. Since it is capable of high speed operation, the semiconductor device relating to the present embodiment also is capable of high speed operation. In addition, since utilization is made of a bulk substrate as the substrate, in comparison with the use of an SOI substrate, the production costs can be maintained at low cost. 
         [0336]    Next, an example of a production method of the semiconductor device related to the fourth embodiment of the present invention is explained, with reference to  FIG. 43A-FIG .  54 C. Moreover, with these drawings, the same labels are applied to the same structural elements. In  FIG. 43A-FIG .  54 , A is a planar view, B is a cross-sectional view along the line a-a′, and C is a cross-sectional view along the line b-b′. 
         [0337]    As shown in  FIG. 43A-FIG .  43 C, a pad oxide file  121  and nitride film  130  are chronologically formed on the Si substrate  100 . 
         [0338]    Resist patterns  141 ,  142 ,  143  and  144  are formed in a scheduled location which forms the silicon column. Continuing, by means of dry etching, using the resists patterns  141 ,  142 ,  143  and  144 , nitride films  131 ,  132 ,  133  and  134 , and oxide films  121 ,  122 ,  123  and  124  are respectively formed in a cylindrical shape. The semiconductor device involved in these steps is shown in  FIG. 44A-FIG .  44 C. Continuing, resist patterns  141 ,  142 ,  143  and  144  are removed. 
         [0339]    By means of etching, silicon columns  111 ,  112 ,  113  and  114  are respectively formed below the cylindrical nitride films  131 ,  132 ,  133  and  134 . The semiconductor device involved in these steps in explained in  FIG. 45A-FIG .  45 C. 
         [0340]    A nitride film  135  is formed on the process results substance. Continuing, a resist pattern  145  is formed on the nitride film  135 . The semiconductor device involved in these steps is shown in  FIG. 46A-FIG .  46 C. Moreover, nitride films  131 ,  132 ,  133  and  134  are embedded in the nitride film  135 , and shown in the drawings as the unitized nitride film  135 . 
         [0341]    Using resist pattern  145 , nitride film  139  is formed by means of etching Continuing, the resist  145  is removed. The transistors involved in these steps are shown in  FIGS. 47A-47C . 
         [0342]    Using nitride films  135  and  139 , as shown in  FIGS. 48A-48C , formation is accomplished of an ordered taper type silicon column  118 , by means of dry etching. 
         [0343]    As shown in  FIGS. 49A-49C , an oxide film is formed on the results substance forming oxide film  125 , which is flattened by using a CMP. 
         [0344]    As shown in  FIG. 50A-FIG .  50 C, on the above results substance is formed a resist pattern  146 . 
         [0345]    Using the resist pattern  146 , nitride films  136 ,  137  and  138  are formed by etching the oxide film  125  and the nitride film  135 . Continuing, the resist pattern  146  is removed. The semiconductor transistor involved in this step is shown in  FIG. 51A-FIG .  51 C. 
         [0346]    As shown in  FIGS. 52A-52C , using nitride films  136 ,  137  and  138 , reversed taper silicon columns  115 , 116  and  117  are respectively formed by dry etching. 
         [0347]    As shown in  FIG. 53A-FIG .  53 C, the nitride films  136 ,  137 ,  138  and  139  and oxide films  121 ,  122 ,  123  and  124  are removed. 
         [0348]    As shown in  FIG. 54A-FIG .  54 C, element separation insulating film  910 , gate electrodes  210 ,  220 , contacts  1210 ,  1220 ,  1230 ,  1240 ,  1250 ,  1260  and  1270 , and wiring  1110 ,  1120 ,  1130 ,  1140  and  1150  are formed. 
       Fifth Embodiment 
     Semiconductor Device 
       [0349]    With the semiconductor device relating to the third embodiment, use is made of an SOI substrate as the substrate. With the fifth embodiment, a semiconductor device is explained which uses a bulk substrate as the substrate. 
         [0350]      FIG. 55  is a summary top view of the semiconductor device relating to the fifth embodiment of the present invention.  FIG. 56  is a simplified cross-sectional view along the cut line a-a′ of  FIG. 55 , and  FIG. 57  is a simplified cross-sectional view along the cut line b-b′ of  FIG. 55 .  FIG. 58  is a simplified cross-sectional view along the cut line c-c′ of  FIG. 55 .  FIG. 59  is a simplified cross-sectional view along the cut line d-d′ of  FIG. 55 . 
         [0351]    The first SGT arranged in a 1st row 1st column is provided with a silicon column  1010  comprising a high resistance region. The silicon column  1010  forms a reverse taper circular truncated cone. The first insulating body  310  is arranged on an upper side surface of the silicon column  1010  so as to encompass the silicon column  1010 . 
         [0352]    A gate electrode  210  is arranged on a side surface of the first insulating body  310  so as to encompass the first insulating body  310 . On the lower part of the silicon column  1010  is arranged a p+ high-density impurity region  410  (source region), and on the upper part, is arranged a p+ high density impurity region  510  (drain region), respectively. 
         [0353]    The p+ high-density impurity region  410  is arranged on an N well  810 . On the upper part of the p+ high-density impurity region  410 , is formed a silicide region  610 , and on the upper part of the p+ high-density impurity region  510  is formed a silicide region  710 , respectively. On the silicide region  710  is arranged a contact  1290 . On the contact  1290  is arranged metal wiring  1130 . 
         [0354]    With the first SGT, the diameter Ts 1  of the contact cross-sectional surface between the silicon column  1010  and the p+ high-density impurity region  410  is smaller than the diameter Td 1  of the contact cross-sectional surface between the silicon column  1010  and the p+ high-density impurity region  510 . 
         [0355]    The second SGT arranged in a 2nd row 1st column is provided with a silicon column  1020  comprising a high resistance region. The silicon column  1020  forms a reverse taper circular truncated cone. The first insulating body  320  is arranged on an upper side surface of the silicon column  1020  so as to encompass the silicon column  1020 . A gate electrode  220  is arranged on the upper side surface of the first insulating body  320  so as to encompass the first insulating body  320 . On the lower part of the silicon column  1020  is arranged a p+ high-density impurity region  410  (source region), and on the upper part, is arranged a p+ high density impurity region  520  (drain region), respectively. The p+ high-density impurity region  410  is arranged on an N well  810 . On the upper part of the p+ high-density impurity region  410 , is formed a silicide region  610 , and on the upper part of the p+ high-density impurity region  520  is formed a silicide region  720 , respectively. On the silicide region  710  is arranged a contact  1230 . On the contact  1290  is arranged metal wiring  1130 . 
         [0356]    With the second SGT, the diameter Ts 2  of the contact cross-sectional surface between the silicon column  1020  and the p+ high-density impurity region  410  is smaller than the diameter Td 2  of the contact cross-sectional surface between the silicon column  1020  and the p+ high-density impurity region  520 . 
         [0357]    The third SGT arranged in a 2nd row 2nd column is provided with a silicon column  1030  comprising a high resistance region. The silicon column  1030  forms an overall reverse taper circular truncated cone. The first insulating body  330  is arranged on an upper side surface of the silicon column  1030  so as to encompass the silicon column  1030 . 
         [0358]    A gate electrode  220  is arranged on an upper side surface of the first insulating body  330  so as to encompass the first insulating body  330 . On the lower part of the silicon column  1030  is arranged an n+ high-density impurity region  420  (source region), and on the upper part, is arranged an n+ high density impurity region  530  (drain region), respectively. 
         [0359]    The n+ high-density impurity region  420  is arranged on an N well  810 . On the upper part of the n+ high-density impurity region  420 , is formed a silicide region  620 , and on the upper part of the n+ high-density impurity region  530  is formed a silicide region  730 , respectively. On the silicide region  730  is arranged a contact  1250 . On the contact  1250  is arranged metal wiring  1130 . 
         [0360]    With the third SGT, the diameter Ts 3  of the contact cross-sectional surface between the silicon column  1030  and the n+ high-density impurity region  420  is smaller than the diameter Td 3  of the contact cross-sectional surface between the silicon column  1030  and the n+ high-density impurity region  530 . 
         [0361]    The fourth SGT arranged in the 1st row 2nd column is provided with a silicon column  1040  comprising a high resistance region. The silicon column  1040  forms a reverse taper circular truncated cone. The first insulating body  340  is arranged on an upper side surface of the silicon column  1040  so as to encompass the silicon column  1040 . 
         [0362]    A gate electrode  210  is arranged on an upper side surface of the first insulating body  340  so as to encompass the first insulating body  340 . On the lower part of the silicon column  1040  is arranged an n+ high-density impurity region  420  (drain region), and on the upper part, is arranged an n+ high density impurity region  540  (source region), respectively. 
         [0363]    The n+ high-density impurity region  420  is arranged on a P well  820 . On the upper part of the n+ high-density impurity region  420 , is formed a silicide region  620 , and on the upper part of the n+ high-density impurity region  540  is formed a silicide region  740 , respectively. On the silicide region  740  is arranged a contact  1270 . On the contact  1270  is arranged metal wiring  1150 . 
         [0364]    With the fourth SGT, the diameter Ts 4  of the contact cross-sectional surface between the silicon column  1040  and the n+ high-density impurity region  540  is smaller than the diameter Td 4  of the contact cross-sectional surface between the silicon column  1040  and the n+ high-density impurity region  420 . 
         [0365]    In addition, on the first SGT gate electrode  210  is arranged a contact  1210 . On contact  1210  is arranged metal wiring  1110 . On the second SGT gate electrode  220  is arranged a contact  1220 . On the contact  1220  is arranged metal wiring  1120 . On the p+ high-density impurity region  410  is arranged a contact  1240 . On the contact  1240  is arranged metal wiring  1140 . On the fourth SGT n+ high-density impurity region  420  is arranged a contact  1270 . On the contact  1270 , is arranged metal wiring  1150 . On the fourth SGT n+ high-density impurity region  420  is arranged a contact  1280 . On the contact  1280  is arranged metal wiring  1150 . In addition, an element separation insulating film  910  is formed on the side surface between the p+ high-density impurity region  410  and the n+ high-density impurity region  420 . 
         [0366]    With the present embodiment, all of the transistors composing the electronic circuits have the same structure as transistors relating to the first embodiment. Since it is capable of high speed operation, the semiconductor device relating to the present embodiment is also capable of high speed operation. In addition, since all of the silicon columns have a reverse taper circular truncated cone, the production of the silicon columns can be accomplished in a single step. Owing to this, the production of the semiconductor device relating to the present embodiment is simplified. In addition, since utilization is made of a bulk substrate as the substrate, in comparison with the use of an SOI substrate, the production costs can be maintained at low cost. 
         [0367]    Next, an example of the production method of the semiconductor device relating to the fifth embodiment of the present invention is explained with reference to  FIG. 60A-FIG .  66 C. Moreover, with these drawings, the same labels are applied relative to the same structural elements. In  FIG. 60A-FIG .  66 C, A is a planar view, B is a cross-sectional view along the line a-a′, and C is a cross-sectional view along the line b-b′. 
         [0368]    As shown in  FIG. 60A-FIG .  60 C a pad oxide film  121  and nitride film  130  are chronologically formed on Si substrate  100 . 
         [0369]    Resist patterns  141 ,  142 ,  143  and  144  are formed in a scheduled location which forms the silicon column. Continuing, by means of dry etching, using the resists patterns  141 ,  142 ,  143  and  144 , nitride films  131 ,  132 ,  133  and  134 , and oxide films  121 ,  122 ,  123  and  124  are respectively formed in a cylindrical shape. The semiconductor device involved in these steps is shown in  FIG. 61A-FIG .  61 C. Continuing, resist patterns  141 ,  142 ,  143  and  144  are removed. 
         [0370]    By dry etching, silicon columns  111 ,  112 ,  113  and  114  are respectively formed below the cylindrical nitride films  131 ,  132 ,  133  and  134 . The semiconductor devices involved in these steps are shown in  FIG. 62A-FIG .  62 C. 
         [0371]    Etching is accomplished in forming a nitride film  135  on the process results substance. As a result, as shown in  FIG. 63A-FIG .  63 C, formation is accomplished of a nitride film  136  in which the nitride film  135  sidewall is formed on the side surface of the nitride film  131 , and a nitride film  137  in which the nitride film  135  sidewall is formed on the side surface of nitride film  132 , and nitride film  138  in which the nitride film  135  sidewall is formed on the side surface of the nitride film  133 , and a nitride film  139  in which the nitride film  135  sidewall is formed on the side surface of the nitride film  134 . 
         [0372]    As shown in  FIGS. 64A-64C , using nitride films  136 ,  137 ,  138  and  139 , reverse taper type silicon columns  115 ,  116 ,  117  and  118  are formed by dry etching. 
         [0373]    As shown in  FIGS. 65A-65C , nitride films  136 ,  137 ,  138  and  139 , and oxide films  121 ,  122 ,  123  and  124  have been removed. 
         [0374]    As shown in  FIGS. 66A-66C , formation is accomplished of element separating insulation film  910 , gate electrodes  210 ,  220 , contacts  1210 ,  1220 ,  1230 ,  1240 ,  1250 ,  1260 ,  1270 ,  1290 , and wiring  1110 ,  1120 ,  1130 ,  1140 ,  1150  and  1160 . 
       Sixth Embodiment 
     Semiconductor Device 
       [0375]    In the above embodiment, the source region and the drain region are all p type or n type silicon columns. However, by attaching a high resistance region to the inside of the silicon column, a reduction of the transistor OFF leakage electric current can be accomplished. 
         [0376]    Therefore, an explanation is provided of the embodiments to which high resistance regions are attached within the silicon columns  1310  and  1410 .  FIG. 67  is a summary birds-eye view of the transistors relating to the sixth embodiment of the present invention.  FIG. 68  is a simplified cross-sectional view along the cut line a-a′ of  FIG. 67 , and  FIG. 69  is a simplified cross-sectional view along the cut line b-b′ of  FIG. 67 .  FIG. 70  is a simplified cross-sectional view along the cut line c-c′ of  FIG. 67 , and  FIG. 71  is a simplified cross-sectional view along the cut line d-d′ of  FIG. 67 . 
         [0377]    The transistors relating to the sixth embodiment are provided with a silicon column  1010  comprising a high resistance region. On the silicon column  1010  is arranged a silicon column  1510 , and below the silicon column  1010  is arranged a silicon column  1710 . In addition, a silicon column  1310  is arranged above silicon column  1010  so as to cover the silicon column  1510 , and the silicon column  1410  is arranged below silicon column  1410  so as to cover silicon column  1710 , respectively. The silicon column  1010 , silicon column  1310 , and silicon column  1410 , as an entirety, are circular truncated cones. 
         [0378]    The silicon layer  1310  and silicon layer  1410  are p type or n type, which introduce arsenic or boron impurities. With the present embodiment, the silicon column  1310  functions as a source diffusion layer, and the silicon column  1410  functions as a drain diffusion layer, respectively. The silicon layer  1010  between the silicon layer  1310  and the silicon layer  1410  functions as a channel region. The silicon column  1510  and the silicon column  1710  respectively function as high resistance regions within the silicon column  1310  and the silicon column  1410 . 
         [0379]    The first gate insulating film  310  is arranged so as to encompass the silicon column  1010 . The first gate insulating film  310  is composed from high-k film, for example oxy-nitride film, silicon nitride film, hafnium oxide, hafnium oxy-nitride, and titanium oxide and the like. A gate electrode  210  is provided so as to encompass the first gate insulating film  310 . The gate electrode  210  is composed, for example, from titanium, titanium nitride, tantalum, tantalum nitride, and tungsten, and the like. 
         [0380]    In the present embodiment, at the time of operation, through the impression of the gate electrode  210 , a channel is formed in the silicon column  1010 . 
         [0381]    With the present embodiment, the Ts comprising the contact surface between the silicon column  1010  and the silicon column  1310  is smaller than the Td comprising the diameter between the silicon column  1010  and the silicon column  1410 . Owing to this, as with the first embodiment, the transistor ON-current relating to the present embodiment is relatively large. In addition, the diameter Td′ of the contact surface between the silicon column  1010  and the silicon column  1710  is greater than the diameter Ts′ of the contact surface between the silicon column  1010  and the silicon column  1510 . Moreover, at this time, Td′ and Ts′ are greater than 0. By such a structure, as explained hereafter, the Off-leakage electric current of the transistor relating to the present embodiment is relatively small. 
         [0382]    The fact that the OFF-leakage current of the transistors relating to the sixth embodiment is smaller than the OFF-leakage current of transistors relating to the first embodiment is based on the analytical results accomplished through model simulation. 
         [0383]    The transistor models relating to the first and sixth embodiments are respectively formed. Both models are joint in that the silicon gate work constant is 4.3 eV and the silicon column  1010  P type impurity concentration is 10 15  (/cm 3 ), formed from a silicon column  1010  where the height is 100 nm, the gate electrode  210  height (L) is 100 nm, the film thickness of the gate insulating film is 2 nm, and the height of the silicon column  1410  and the silicon column  1310  is 100 nm, and from silicon column  1010 . 
         [0384]    With the transistor model relating to the first embodiment, the Td comprising the diameter of the contact surface between the silicon column  1010  and the silicon column  1410  (drain region) is 100 nm, and the Ts comprising the diameter between the contact surface of the silicon column  1010  and the silicon column  1310  (source region) is 80 nm. On the other hand, with the transistor model relating to the sixth embodiment, the Td comprising the diameter between the contact surface of the silicon column  1010  and the silicon column  1410  is 100 nm, and the diameter Td′ between the contact surface of the silicon column  1010  and the silicon column  1710  is 80 nm, and the Ts comprising the diameter between the contact surface of the silicon column  1010  and the silicon column  1310  is 80 nm, and the diameter Ts′ of the contact surface between the silicon column  1010  and the silicon column  1510  is 60 nm. 
         [0385]    In addition, the impurity and concentration of the N-type impurity region of the silicon column  1410  and the silicon column  1310  is 10 20  (/cm 3 ). Using the above structure, with the production method of the first embodiment, simulation was performed.  FIG. 72  is a plotted view of the drain current (Id, log indication) and the gate voltage (Vg). 
         [0386]    What this experiment, the OFF-leakage current is equal to the drain current (Id) when the gate voltage (Vg) is OV. From  FIG. 72  it is understood that the OFF-leakage current of the transistor relating to the sixth embodiment is smaller than the OFF-leakage current of the transistor model relating to the first embodiment. In addition,  FIG. 73  is a plotted diagram of the drain current (Id) and the gate voltage (Vg). With this experiment, the ON current is equal to the drain voltage (Vd) when the drain voltage (Vd) in the gate voltage (Vg) is 1.2V. from  FIG. 73 , and is understood that the ON current of the transistor models relating to the first and sixth embodiments are substantially the same. Hence, according to  FIG. 72  and  FIG. 73 , the transistors relating to the sixth embodiment, in comparison with the transistors relating to the first embodiment is greater than the ON-current when the ON-current does not change. 
         [0387]    As indicated above, the transistors relating to the present embodiment by means of the above structure where Ts&lt;Td and Ts′&lt;Td′, while supporting a relatively great ON current, shows a relatively small OFF leakage current. Owing to this, through the use of the present transistors, semiconductor device high-speed operation and energy power conservation is possible. 
         [0388]    In the second to fifth embodiments are shown the semiconductor devices composed from transistors relating to the first embodiment. In the seventh to tenth embodiments, examples are shown of semiconductor devices composed from transistors relating to the sixth embodiment. The semiconductor devices relating to these embodiments function as NAND circuits. Moreover, NAND circuits do nothing more than show examples of electronic circuits, and other electronic circuits are also capable of high speed operation when using the transistors relating to the seventh to tenth embodiments. 
       Seventh Embodiment 
     Semiconductor Device 
       [0389]      FIG. 74  is a summary top view of the semiconductor device relating to the seventh embodiment of the present invention.  FIG. 75  is a simplified cross-sectional view along the cut line a-a′ of  FIG. 74 , and  FIG. 76  is a simplified cross-sectional view along the cut line b-b′ of  FIG. 74 .  FIG. 77  is a simplified cross-sectional view along the cut line c-c′ of  FIG. 74 , and  FIG. 78  is a simplified cross-sectional view along the cut line d-d′ of  FIG. 74 . 
         [0390]    The semiconductor device relating to the seventh embodiment, within the source region and the drain region, with the exception of the point of the formation of the respective high resistance regions, is the same as the semiconductor device relating to the second embodiment. 
         [0391]    With the present embodiment, all of the transistors composing the electronic circuits have the same structure as transistors relating to the sixth embodiment. By this means, the semiconductor device of the present embodiment is capable of high speed operation, and by this means the semiconductor device relating to the present embodiment conserves electric power. 
         [0392]    In addition, the method of producing the trapezoidal column is the same as for the semiconductor device relating to the second embodiment. 
       Eighth Embodiment 
     Semiconductor Device 
       [0393]      FIG. 79  is a summary top view of the semiconductor device relating to the eighth embodiment of the present invention.  FIG. 80  is a simplified cross-sectional view along the cut line a-a′ of  FIG. 80 , and  FIG. 81  is a simplified cross-sectional view along the cut line b-b′ of  FIG. 79 .  FIG. 82  is a simplified cross-sectional view along the cut line c-c′ of  FIG. 79 , and  FIG. 83  is a simplified cross-sectional view along the cut line d-d′ of  FIG. 79 . 
         [0394]    The semiconductor device relating to the eighth embodiment, within the source region and the drain region, with the exception of the point of the formation of the respective high resistance regions, is the same as the semiconductor device relating to the third embodiment. 
         [0395]    With this embodiment, all of the transistors composing the electronic circuits have the same structure as the transistors relating to the sixth embodiment. By this means, a semiconductor device relating to the present embodiment is capable of high-speed performance. In addition, by this means, for example, a semiconductor device relating to the present embodiment conserves electric power. In addition, since all of the devices have a circular truncated cone having an ordered tapered shape, the production of the silicon columns can be accomplished in a single step. Therefore, production of the semiconductor device relating to the present embodiment becomes simplified. 
         [0396]    In addition, the production method for producing a trapezoidal silicon column is the same as the semiconductor device relating to the third embodiment. 
       Ninth Embodiment 
     Semiconductor Device 
       [0397]      FIG. 84  is a summary top view of the semiconductor device relating to the ninth embodiment of the present invention.  FIG. 85  is a simplified cross-sectional view along the cut line a-a′ of  FIG. 84 , and  FIG. 86  is a simplified cross-sectional view along the cut line b-b′ of  FIG. 84 .  FIG. 87  is a simplified cross-sectional view along the cut line c-c′ of  FIG. 84 , and  FIG. 88  is a simplified cross-sectional view along the cut line d-d′ of  FIG. 84 . 
         [0398]    The semiconductor device relating to the ninth embodiment, within the source region and the drain region, with the exception of the point that respective high resistance regions are formed, is the same as the semiconductor device relating to the fourth embodiment. 
         [0399]    With this embodiment, all of the transistors composing electronic circuits have the same structure as the transistors relating to the sixth embodiment. By this means, the semiconductor relating to the present embodiment is capable of high speed operation. In addition, by this means, the semiconductor device relating to the present embodiment conserves electric power. In addition, since as the substrate, use is made of a bulk substrate, in comparison with the case of using an SOI substrate as the substrate, the production costs can be maintained at low cost. 
         [0400]    In addition, the production method of producing a trapezoidal silicon column is the same as the semiconductor device relating to the fourth embodiment. 
       Tenth Embodiment 
     Semiconductor Device 
       [0401]      FIG. 89  is a summary top view of the semiconductor device relating to the tenth embodiment.  FIG. 90  is a simplified cross-sectional view along the cut line a-a′ of  FIG. 89 .  FIG. 91  is a simplified cross-sectional view along the cut line b-b′ of  FIG. 89 .  FIG. 92  is a summary top view along the cut line c-c′ of  FIG. 89 , and  FIG. 93  is a summary top view along the cut line d-d′ of  FIG. 89 . 
         [0402]    The semiconductor device relating to the ninth embodiment, within the source region and the drain region, with the exception of the point that respective high resistance regions are formed, is the same as the semiconductor device relating to the fifth embodiment. 
         [0403]    With this embodiment, all of the transistors composing the electronic circuit have the same structure as the transistors relating to the sixth embodiment. By this means, a semiconductor device relating to the present embodiment is capable of high speed operation. In addition, by this means, the semiconductor device relating to the present embodiment conserves electric power. In addition, as the substrate, since utilization is made of a bulk substrate, in comparison with the case of using an SOI substrate as the substrate, production costs can be maintained at low cost. 
         [0404]    In addition, the production method for producing a trapezoidal silicon column is the same as for the semiconductor device relating to the fifth embodiment. 
         [0405]    Having described and illustrated the principles of this application by reference to one or more preferred embodiments, it should be apparent that the preferred embodiments may be modified in arrangement and detail without departing from the principles disclosed herein and that it is intended that the application be construed as including all such modifications and variations insofar as they come within the spirit and scope of the subject matter disclosed herein.