Abstract:
A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a Continuation of U.S. application Ser. No. 12/330,270, filed Dec. 8, 2008 which claims the benefit of U.S. Provisional Application No. 61/005,772, filed on Dec. 7, 2007. The entire teachings of the above applications are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by ‘clock’ voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability. 
         [0003]    In certain charge-domain signal-processing circuits, the charge packets are stored on capacitors. Most charge-domain operations can be described by the well known expression, Q=CV, where Q represents the size of the charge packet, in Coulombs, C represents the capacitance on which the charge packet is stored, in Farads, and V represents the voltage of the node on which the charge packet is stored, in Volts. The process of charge transfer and storage in a charge-domain signal-processing circuit is explained with the aid of  FIGS. 1 and 2 . These figures omit some of the details needed to implement a complete charge domain signal processing circuit, but they suffice to permit the description below of the essential features of charge storage and transfer in charge-domain circuits (such details are described in other published patent applications by Anthony, M., such as U.S. Patent Publication No. 2007/0279507 entitled “Boosted Charge Transfer Circuit” and U.S. Patent Publication 2008/0205581 entitled “Common-mode Charge Control in a Pipelined Charge-domain Signal-Processing Circuit” hereby incorporated by reference). Charge, as represented by electrons, flows in the opposite direction from conventional current. Note that all descriptions below assume electrons as the signal-charge carriers. The corresponding quantities of charge (Q) in the equations have negative values. The identical description can be applied equally well using holes as charge carriers with reversed voltage polarities. 
         [0004]      FIG. 1  depicts a simple charge transfer and storage circuit and  FIG. 2  shows the potential charge-storage of node A shown in  FIG. 1 . Assume Node A has been given an initial voltage of V Aic  (such as may be imposed by closing a precharge switch PRE at some time prior to time t 0 ). Its potential (voltage) is then allowed to float (such as by then opening switch PRE at time t 0 ). One terminal of capacitor C A , which provides a charge-storage function, is connected to node A; the other terminal of capacitor C A  is connected to a static voltage V 1 . When a quantity of charge (Q) is transferred onto node A at time t 1 , (such as by closing switch SW 1 ) the voltage at Node A falls to voltage V A1 . Please note that switches SW 1  and SW 2  are meant to illustrate charge transfer functions at a conceptual level. Practical charge transfer circuits are typically more complex or different, and the exact design of SW 1  and SW 2  are not pertinent to the present invention. Equation 1 relates the transferred charge, Q i , to the node voltage at A, V A1 , given the capacitance of node A, C A , and its initial potential, V Aic . 
         [0000]        V   A1   =V   Aic   −Q   i   /C   A   Equation 1
 
         [0005]    In charge storage devices, the allowable voltage at Node A is constrained by various factors relating to the specific circuit implementation. In circuits using electrons as the charge carrier, the initial voltage, V Aic , is usually set to the most positive voltage available V A1  is limited by the minimum Voltage (V Amin ) at which electrons can be attracted from the transferring source and stored. This constraint sets the maximum allowable charge that can be transferred onto node A. Equation 2 relates the charge capacity of Node A, Q imax1 , to the minimum voltage allowed at Node A, V Amin , given the capacitance of node A, C A , and its initial potential V A . 
         [0000]        Q   imax1 =( V   Aic   −V   Amin ) C   A   Equation 2
 
         [0006]    Charge transfer off of storage node A begins at time t 2 . At time t 2 , a switch SW 2  is closed which connects node A to a voltage source SV delivering a voltage V o . The quantity of charge transferred through the voltage source SV is described by Equation 3 which relates the charge transferred through the voltage source, Q o1 , to the initial charge transferred to node A, Q i , given the capacitance of node A, C A , its initial potential V Aic , and the potential, V o  of the voltage source SV. 
         [0000]        Q   o1   =Q   i −( V   Aic   −V   o ) C   A   Equation 3
 
         [0007]    As stated above, in charge-domain signal-processing circuits, the signal is represented by a charge packet. In this case, the charge Q 1  transferred onto node A represents the signal, thus the maximum signal value allowed is Q imax1 . In all analog circuits, one figure of merit is the signal-to-noise ratio (SNR). Equation 4 describes this quantity. 
         [0000]      SNR=Signal/Noise= Q   imax1   /Q   noise   Equation 4
 
         [0008]    Equation 2 describes the quantity Qimax 1 . In the simplified circuit of  FIG. 1 , the quantity Qnoise is often referred to as kTC noise and is proportional to the square root of capacitance, C A . Equation 5 describes this relationship. 
         [0000]        Q noise=√( kTC   A )  Equation 5
 
         [0009]    Substituting Equations 5 and 2 into Equation 4 gives Equation 6. 
         [0000]      SNR=( V   Aic   V   Amin )]√( C   A )√( kT )  Equation 6
 
         [0010]    From Equation 6, it is clear that SNR is proportional to the square root of C A  and the voltage difference (V Aic −V Amin ). Since a change in either of these quantities will result in a change in Q o1 , as expressed in Equation 3, it is not possible to increase SNR without altering the charge transfer characteristics of this simplified circuit. (Similar limitations apply to more complex circuits.) Moreover, the conventional approach of increasing C A  to improve SNR can be shown to increase the area occupied by the circuit and also the power consumed. It would therefore be beneficial to improve SNR in some manner that does not create these disadvantages while also not altering the circuit&#39;s charge transfer characteristics. 
       SUMMARY OF THE INVENTION 
       [0011]    In the prior art, increasing SNR has been achieved by increasing the capacitance of the charge storage nodes of the system. This method is disadvantageous for several reasons. First, the charge transfer characteristics are altered, necessitating circuit and system changes. Second, due to the square-law relation between SNR and capacitance, it takes a quadratic change in C A  to produce a linear change in SNR. Finally, increasing capacitance C A  results in a physically larger implementation that consumes more power. 
         [0012]    It would be advantageous to allow the charge capacity of a node to be increased, thereby increasing its signal-to-noise ratio, and without changing its inherent charge transfer function or incurring the usual penalties associated with increasing C A . 
         [0013]    In a preferred embodiment, this is accomplished by connecting a clock signal to a charge storage device such as a capacitor. The clock signal adjusts a voltage difference across the capacitor while charge is being transferred, but then returns the voltage difference to an initial condition thereafter. The result is to increase the charge capacity without changing the amount of charge transferred. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention. 
           [0015]      FIG. 1  is a simplified diagram of a known charge storage circuit. 
           [0016]      FIG. 2  is a timing diagram for the circuit of  FIG. 1 . 
           [0017]      FIG. 3  is a simplified diagram of a charge storage circuit that implements the present invention. 
           [0018]      FIGS. 4A and 4B  are timing diagrams for the circuit of  FIG. 3 . 
           [0019]      FIG. 5  is a high level diagram of a charge pipeline Analog to Digital Converter (ADC) that uses the circuit of  FIG. 3 . 
           [0020]      FIG. 6  is a high level diagram of a digital radio receiver that uses the ADC of  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    A description of example embodiments of the invention follows. 
         [0022]      FIGS. 3 ,  4 A and  4 B illustrate a simplified charge storage and transfer circuit similar to that of  FIG. 1 . In  FIG. 3  the second terminal of capacitor C A  is connected to a clocked node Kminv rather than to a fixed voltage as in  FIG. 1 . Assume floating Node A is set to the same initial condition, V Aic  at time t 0  as for the circuit of  FIG. 1  to such as by operating precharge switch PRE. However, in the circuit of  FIG. 3 , at time t 1 , the voltage of node Kminv is now clocked from voltage V 1  to voltage V 2  while charge Q i  is injected onto Node A (e.g., by operating switch SW 1 ). Equation 7 relates the transferred charge, Q i , to the node voltage at A, V A2 , given the capacitance of node A, C A , its initial potential V Aic , and the voltage transition of Kminv. 
         [0000]        V   A2   =V   Aic   Q   i   /C   A ( V   2   −V   1 )= V   A1 +( V   2   −V   1 )  Equation 7
 
         [0000]    where V A1  is given Equation 1. 
         [0023]    The voltage V A2  will always be more positive than V A1  as long as the relationship V 2 &gt;V 1  is maintained. Equation 8 describes the charge capacity of this device. 
         [0000]        Q   Amax2 =( V   Aic   −V   Amin +( V   2   −V   1 )) C   A   =Q   Amax1 +( V   2   −V   1 ) C   A   Equation 8
 
         [0000]    This the use of a switched voltage on the second terminal of the capacitor CA increases the charge capacity of the circuit by the quantity (V 2 −V 1 )C A ). 
         [0024]    At time t 2 , while the switch SW 2  is closed connecting to Node A to voltage V O  and initiating charge transfer off of node A, node Kminv is also returned from V 2  to V 1 . Since node Kminv is returned to its initial condition, V 1 , at time t 2 , it has no net effect on the quantity of charge transferred into the Voltage source. The charge transferred through the voltage source VS is described by Equation 9. 
         [0000]        Q   o2   =Q   i −( V   Aic   −V   o ) C   A   =Q   ol   Equation 9
 
         [0025]    Since Q o2 =Q o1 , the charge transfer function of this device is identical to that of the device described in  FIGS. 1 and 2 , however its charge capacity has been increased. In practice, V 2  can be set to the maximum voltage available, while V i  can be set to the minimum available. Note that the scale of  FIGS. 4A and 4B  are not the same; in most cases, the difference (V 2 −V 1 ) will be greater than (V Aic −V Amin ). Thus the charge capacity of the transfer and storage node can be more than doubled without incurring the penalties described earlier. 
         [0026]      FIG. 5  illustrates a charge domain pipeline stage that may use the principles of  FIG. 3 . The circuit contains two charge pipelines. The upper pipeline contains a charge transfer circuit  1 A, storage node  2 A, charge transfer circuit  3 A, and capacitor  5 A. In operation of the upper pipeline, charge is stored on the combination of capacitor  5 A, which is connected between storage node  2 A and clock voltage V C1 , and capacitor C A  which is connected between storage node  2 A and clock voltage K minVA . Charge enters the stage via charge-transfer circuit  1 A, and later exits the stage via charge-transfer circuit  3 A. Voltage V ci  is a digital clock signal which controls the timing of charge processing in the stage. Note the use of capacitor C A  and corresponding signal KminvA to provide increased charge storage capability. The lower pipeline contains elements  1 B . . .  5 B and C B  as well as signal K minVB  that are equivalent to elements  1 A,  2 A,  3 A,  4 A,  5 A and C A  of the upper pipeline. 
         [0027]    Multiple circuits as shown in  FIG. 5 , with certain added elements can be arranged in a pipeline to provide the operations needed to carry out charge-domain Analog to Digital conversion: namely charge storage and transfer, charge comparison, and conditional and constant charge addition. These operations can be combined in various ways to carry out a variety of ADC algorithms, which may for example, carry out 1-bit, 1½ bit, 2 bits per stage or in other configurations as described in a co-pending U.S. Patent Publication No. 2008/0246646 entitled “Charge Domain Pipeline Analog to Digital Converter”, U.S. Patent Publication filed Jan. 18, 2008, which is incorporated by reference herein. 
         [0028]    One particular use of the ADC of  FIG. 5  is to implement a digital radio receiver as generally shown in  FIG. 6 . A Radio Frequency (RF) signal is received at a radio frequency RF amplifier  504 . The RF signal may have originated from an antenna  502 , such as in a wireless end application, or may have been provided via a wire or optic fiber, such as may be in a cable modem or other wired communication signal interface. The amplified RF signal is then fed to an RF translator  506  to down-convert the amplified RF signal to an intermediate frequency (IF). After the RF translator  506  (which may be optional) the ADC  510  is then used to digitize the RF input into digital samples for subsequent processing. A digital local oscillator  511  may operate digital mixers  512 - i  and  512 - q  to provide in-phase and quadrature samples thereof. A digital low pass filter  520  limits the frequency content of resulting signal to the desired bandwidth. A demodulator  530  then recovers the original modulated signal. One or more of the operations of the digital local oscillator  511 , mixers  512 , low pass filter  520  and/or demodulator  530  may be implemented in a digital signal processor  550 . The recovered signal may then be further processed, e.g., converted back to an analog baseband signal or the like, depending on the specific end application of the digital receiver. 
         [0029]    While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.