Abstract:
An integrated circuit (IC) includes an internal clock generator apparatus that provides various modes of operation of the integrated circuit. The internal clock generator apparatus includes a clock generator portion that is operable to provide a clock signal for various circuitry/logic of the integrated circuit and a control portion that is operable to receive a control signal to cause the integrated circuit to operate in one of several modes. In particular, the clock generator apparatus is responsive to the control signal, preferably from an external source, to bypass the clock signal, introduce a test clock signal for digital testing, and isolate and/or measure a delay through the clock generator portion of the clock generator apparatus.

Description:
[0001]    This application claims the benefit of U.S. provisional patent application serial No. 60/191,798 filed on Mar. 24, 2000 entitled “Controllable and Testable Ring Oscillator Apparatus”. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates to integrated circuits and, more particularly, to an internal clock generating apparatus in an integrated circuit.  
         BACKGROUND OF THE INVENTION  
         [0003]    Integrated circuits (ICs) are extensively, if not exclusively, used in most electronic devices of today. Such ICs may be digital, analog, or a combination of digital/analog technology. In all types of ICs, it is necessary to provide on-chip clock circuitry to generate and/or provide an on-chip clock.  
           [0004]    Ring oscillators are commonly used to generate on-chip clocks in digital ICs. Ring oscillators are particularly attractive for such usage because they are fully self-contained in the IC and do not require the use of any Input/Output (I/O) pins of the IC. It is beneficial for various reasons to limit the number of I/O pins on an IC.  
           [0005]    It is critical to perform production testing of the various functions and/or characteristics of an IC including a ring oscillator. However, in order to perform production testing of an IC that contains a ring oscillator, it is desirable to provide a means of bypassing the ring oscillator and introducing a test clock in its place. For example, a test procedure for testing digital ICs usually includes timing tests, such as tests to determine setup and hold time data. These tests typically require control of the test clock and thus cannot simply use the free-running ring oscillator.  
           [0006]    In addition, since a ring oscillator is basically an analog circuit, it is desirable to provide a means to test the ring oscillator via I/O pins of the IC. In particular, the delay through the ring oscillator determines its frequency, and thus it is desirable to characterize this delay over process, temperature, and voltage.  
           [0007]    Thus, it is desirable to provide an IC with a ring oscillator that can be bypassed.  
           [0008]    It is also desirable to provide an IC with a ring oscillator that will allow the introduction of a test clock for digital testing.  
           [0009]    It is further desirable to provide an IC with a ring oscillator in which the delay through the ring oscillator may be isolated and/or measured.  
         SUMMARY OF THE INVENTION  
         [0010]    The present invention is a clock generator apparatus for an integrated circuit that is functional in various modes of operation. Such modes of operation include generating a clock signal for clocking internal circuitry/logic of the integrated circuit, bypassing the clock generator and/or only a portion of the clock generator, introducing a test clock for digital testing, and/or isolating and measuring a delay time through the clock generator.  
           [0011]    In a general form, the clock generator apparatus includes an oscillator and associated control circuitry/logic. The oscillator and associated control circuitry/logic are in communication with and utilize only existing input/output pins of the integrated circuit. The control circuitry/logic is operable to receive control signals via the input/output pins to provide the various modes of operation via the input/output pins.  
           [0012]    The existing input/output pins are pins that are normally functional pins of the integrated circuit. The present invention utilizes these pins to enable the various test modes. The multiplexing of the selective input/output pins allows the integrated circuit to operate in a normal mode, but enables test modes when it is desired to test the integrated circuit. Sharing the function of these pins eliminates the need for adding test pins on the integrated circuit.  
           [0013]    In a particular form, the clock generator apparatus is a ring oscillator and the control circuitry/logic includes multiplexers operable to receive the control signals from the input/output pins. The ring oscillator is formed by a delay line having a net inversion around a feedback loop to provide any frequency of clock signal. The delay line may be formed by a plurality of digital buffers. In order to provide net inversion, the ring oscillator is formed by either an odd number of inverters, or an even number of non-inverting buffers and an inverter. The frequency of the clock signal from the plurality of digital buffers may be reduced by appropriate divider circuitry/logic. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    Reference to the following description of the present invention should be taken in conjunction with the accompanying drawings, wherein:  
         [0015]    [0015]FIG. 1 is a representation of an integrated circuit in which the present invention may be utilized;  
         [0016]    [0016]FIG. 2 is a schematic diagram of an exemplary embodiment of a ring oscillator and accompanying IC circuitry/logic in accordance with the principles of the present invention;  
         [0017]    [0017]FIG. 3 is a Table showing the various functionality of the exemplary embodiment of the ring oscillator and accompanying IC circuitry/logic of FIG. 2 under the control conditions also presented in the Table; and  
         [0018]    [0018]FIG. 4 is a timing diagram for the exemplary embodiment of the ring oscillator and accompanying IC circuitry/logic of FIG. 2. 
     
    
       [0019]    Corresponding reference characters indicate corresponding parts throughout the several views.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0020]    With reference to FIG. 1, there is depicted an integrated circuit (IC) generally designated  10  in which the present invention may be used. The IC  10  includes a case  12  that may contain analog, digital, and/or analog/digital logic/circuitry. The IC  10  includes a plurality of Input/Output (I/O) pins each one of which is generally designated  14 . The number of I/O pins  14  will vary per the type and/or function of the IC. However, in accordance with an aspect of the present invention, the number of I/O pins  14  of the IC  10  does not change with the addition of the present invention.  
         [0021]    Each one of the I/O pins  14  has a specific purpose/function dictated by the particular type and/or design of the IC. It should be appreciated that the particular type of IC is not material to the application and/or implementation of the principles of the present invention. Given this premise, however, several of the I/O pins  14  will be arbitrarily designated to comport with at least FIG. 2 and the discussion relating thereto. Therefore, it should be additionally appreciated that the below designation of specific I/O pins of the general I/O pins  14  are completely arbitrary. As well, the name of each designated I/O pin is arbitrary.  
         [0022]    I/O pin  15  of the general I/O pins  14  is thus arbitrarily designated a DATA_OUT I/O pin. I/O pin  16  of the general I/O pins  14  is thus arbitrarily designated a SCAN_MODE I/O pin. I/O pin  17  of the general I/O pins  14  is thus arbitrarily designated a RESETN I/O pin. I/O pin  18  of the general I/O pins  14  is thus arbitrarily designated a SCAN_ENABLE I/O pin. I/O pin  19  of the general I/O pins  14  is thus arbitrarily designated a Port_A 5  I/O pin.  
         [0023]    Referring now to FIG. 2, there is shown a schematic or circuit/logic diagram/layout of a portion of circuitry/logic, generally designated  20 , within the IC  10 . In accordance with an aspect of the present invention, there is provided an oscillator or oscillator circuitry/logic, generally designated  30 , within or as part of the portion of circuitry/logic  20 . In a preferred form the oscillator  30  comprises a ring oscillator and hereinafter, will be referred to as a ring oscillator. It should be appreciated, however, that the oscillator  30  may constitute another type of oscillator that functions/performs in the manner set forth herein. In addition, there is provided control circuitry/logic, generally designated  31 , that may or may not form a part of the ring oscillator  30  proper, that is responsive to control signals to provide various modes of operation thereof as described herein either in conjunction with or not in conjunction with other circuitry/logic of the circuitry/logic  20  as herein described. Hereinafter, the term ring oscillator  30  will be assumed to include the control circuitry/logic  31  therein unless specifically indicated otherwise.  
         [0024]    The ring oscillator  30  is coupled to or in communication with several I/O pins  14 . In particular, the ring oscillator  30  is coupled to the DATA_OUT I/O pin  15 , the SCAN_MODE I/O pin  16 , the RESETN I/O pin  17 , the SCAN_ENABLE I/O pin  18 , and the Port_A 5  I/O pin  19 . The line labeled Port_A 5 _Intemal is the Port_A 5  of the integrated circuit  10  without the addition of the present invention. Thus, when the multiplexer  44  receives a logic “0” or low, the Port_A 5 _Internal signal is provided to the Port_A 5  I/O pin  19  as it would without the addition of the present invention. When the multiplexer  44  receives a logic “1” or high, the output signal from the multiplexer  40  is provided as the signal to the Port_A 5  I/O pin  19 .  
         [0025]    The output of the ring oscillator  30  is a clock signal which, in response to a control signal or control signals, may be provided to the IC_CLK output  48 , may be bypassed completely, and/or may be provided as an output of the IC  10  on Port_A 5  I/O pin  19 . For example, I/O pins provided for implementing a test mode function of the IC  10  (such as “SCAN_ENABLE” and “SCAN_MODE” I/O pins  18  and  16  respectively used to perform a digital scan test) may be used to provide control signals to control a series of multiplexers (MUXs) as explained further below. The IC_CLK output  48  is an output of the oscillator arrangement shown in FIG. 2 that produces a signal that is coupled to circuitry internal to IC  10 . That is, IC_CLK output  48  is an output that is in communication with further IC circuitry/logic (not shown) to provide the clock signal generated by the ring oscillator  30  to the further IC circuitry/logic internal to the IC  10 . Thus, the IC_CLK signal is used to clock digital logic/circuitry (not shown) internal to the IC  10 .  
         [0026]    The ring oscillator  30  includes delay logic  34  that preferably comprises a plurality of digital buffers or inverters (hereinafter, inclusively “digital buffers”). In FIG. 2, the delay logic  34  includes an even number of digital buffers to provide a net inversion. The output of the delay logic  34  is provided as one input (here arbitrarily the “0” input) of a multiplexer  32  that has an inverted output (hence the “dot” or “circle” designation at its output). Alternatively, the delay logic  34  may be provided with an odd number of inverters in which case the output of the multiplexer  32  would not be inverted. In either case, when a control signal from the SCAN_MODE I/O pin  16  provides a logic “0” or low to the multiplexer  32 , a closed loop is formed. The resulting circuit will oscillate at a frequency of approximately ½*td, where td is the total delay time around the closed loop. In an exemplary embodiment described herein, td equals n times the typical propagation delay of one of the digital buffers or inverters where n is the number of digital buffers or inverters in the loop (200 digital buffers or inverters in the exemplary embodiment). When the multiplexer  32  receives a control signal from the SCAN_MODE I/O pin that provides a logic “1” or high, the multiplexer  32  provides the signal that is on the DATA_OUT I/O pin  15  to the delay logic  34  such that an open loop is formed. When an open loop is formed, there is no oscillator functionality. Various modes are achieved when the multiplexer  32  receives a logic “1” from the SCAN_MODE I/O pin  16 , some of which are provided in the Table  50  of FIG. 3.  
         [0027]    The output signal from the delay logic  34  is also provided to an input of divider circuitry/logic  36 . The divider  36  is operable during receipt of a logic “1” or high signal from the RESETN I/O pin  17 , while a logic “0” or low signal from the RESETN I/O pin  17  resets the divider  36 . Continued receipt of a logic “0” or low signal from the RESETN I/O pin  17  disables the divider  36  until a logic “1” or high signal is received. The divider  36  divides down or lowers the frequency of the ring oscillator (F ring ) by a value determined by the circuitry/logic of the divider  36 . By providing a divider  36 , the silicon area of the integrated circuit occupied by the digital buffers of the delay logic  34  is minimized or reduced, because a higher frequency reduces the number of digital buffers needed to implement the delay circuitry/logic  34 ). Thus, the ring oscillator  30  operates at a higher frequency than a desired frequency for the operation of the internal circuitry/logic of the integrated circuit that is then divided down by the divider  36  to produce a clock signal at a system clock rate (desired frequency of operation of the integrated circuit).  
         [0028]    In the exemplary embodiment, the number of buffers included in the ring oscillator  30  is chosen to achieve a nominal frequency of 40 MHz (F ring ). The output of the ring oscillator  30  is provided to the divider  36  that divides the F ring  by four (4) resulting in a 10 MHz output signal (F ring /4) that is provided to the multiplexer  38  at one input (the “0” input) thereof.  
         [0029]    Another input (the “1” input) of the multiplexer  38  receives the undivided signal (F ring ) from the delay logic  34 . Selection of the output of the multiplexer  38  is under control of the signal from the SCAN_MODE I/O pin  16 . A logic “1” or high signal on or from the SCAN_MODE I/O pin  17  selects the “1” input of the multiplexer  38  or the undivided signal (F ring ) from the delay logic  34 . A logic “0” or low signal on or from the SCAN_MODE I/O pin  17  selects the “0” input of the multiplexer  38  or the divided signal (F ring /4) from the delay logic  34 .  
         [0030]    The output of the multiplexer  38  as selected by the SCAN_MODE signal is provided to one input (the “1” input) of a multiplexer  40 . Another input (the “0” input) of the multiplexer  40  receives the undivided signal (F ring ) from the delay logic  34 . Selection of the output of the multiplexer  40  is under control of the signal from the RESETN I/O pin  17 . A logic “1” or high signal on or from the RESETN I/O pin  17  provides the output signal from the multiplexer  38  as the output signal of the multiplexer  40 , while a logic “0” or low signal on or from the RESETN I/O pin  17  provides the output signal from the delay logic  34  (i.e. the undivided frequency signal F ring ) as the output signal of the multiplexer  40 .  
         [0031]    The output of the multiplexer  40  as selected by the RESETN signal is provided to one input (the “0” input) of a multiplexer  42  and to the “1” input of the multiplexer  44  as indicated above. Another input (the “0” input) of the multiplexer  42  receives the signal on or from the DATA_OUT I/O pin  15 . Selection of the output of the multiplexer  42  is under control of the signal from the SCAN_MODE I/O pin  16 . A logic “1” or high signal on or from the SCAN_MODE I/O pin  16  provides the DATA_OUT signal as the output of the multiplexer  42 , while a logic “0” or low signal on or from the SCAN_MODE I/O pin  16  provides the output of the multiplexer  40  as the output of the multiplexer  42 . The output of the multiplexer  40  is provided to the IC_CLK line  48  as an internal signal. The internal signal on the IC_CLK line  48  is provided to the various internal circuitry/logic of the IC  10 . Depending on the internal signal, various modes of operation may be maintained. These various modes of operation may be in conjunction with signals on, from, and/or to the various inputs and/or outputs of the integrated circuit  10  as herein described.  
         [0032]    It should be recognized that the inputs (“1” and “0”) to the various multiplexers may be reversed in which case the various input signals as indicated in the truth table portion of the Table  50  of FIG. 3 would be modified accordingly to provide the function and/or signals to the Outputs as indicated.  
         [0033]    Referring to FIG. 3, there is shown a Table, generally designated  50 , for the various multiplexers shown in FIG. 2 to implement the functions described herein and in the Table  50  under the control conditions defined by the truth table included therein and, in particular for the Inputs SCAN_ENABLE, SCAN_MODE, and RESETN. The Table  50  also shows the Outputs IC_CLK and PORT_A 5 , and the Function(Mode)/Comments.  
         [0034]    In FIG. 2 and the Table  50  of FIG. 3, SCAN_ENABLE, SCAN_MODE, RESETN, and DATA_OUT are signals associated with input and/or output (I/O) pins of the IC  10 . These signals are logically combined by the operation of the various multiplexers shown in FIG. 2 to generate the various mode functions listed in the Table  50 . IC_CLK is a clock signal generated by the arrangement shown in FIG. 2 that is used to clock digital logic internal to the IC  10 . Port_A 5  is an output signal from the IC  10  that is generated by the multiplexer  44  to provide, as shown in the Table  50 , either observation of the ring oscillator operation during a test mode of operation of the IC  10 , or a normal output of the IC  10  during a normal mode of operation of the IC  10 .  
         [0035]    Referring to FIG. 4, there is shown an exemplary timing chart, generally designated  80 , illustrating the operation of the various features/functions shown in FIG. 2, listed in the Table  50  of FIG. 3, and described herein in conjunction therewith. It also represents a simulation display of the various test modes described in the Table  50 .  
         [0036]    While this invention has been described as having a preferred design and/or configuration, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the invention using its general principles. Further, this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.