Abstract:
A semiconductor capable of reducing skew between plural-bit output data by using a plurality of data output drivers and a method thereof. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state in response to signals received from other data output drivers.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to Korean Patent Application No. 2001-14112, filed on Mar. 19, 2001, which is commonly owned and incorporated by reference herein. 
     BACKGROUND 
     1. Technical Field 
     The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of minimizing skew between plural-bit output data and a method thereof. 
     2. Description of Related Art 
     Semiconductor devices that output data comprising a large number of bits typically output the data bits simultaneously (i.e., in parallel). When the logic levels of the plural-bit output data simultaneously transition, a large amount of electrical current is applied to a power line, which causes a transition noise due to parasitic components of the power line. As a result, output data can be delayed and distorted. 
     Further, if a portion of the output data transits in one direction to a logic state (e.g., from a logic “high” to a logic “low” level), and another portion of the output data transits in the opposite direction (e.g., from a logic “low” to a logic “high” level), a delay time difference occurs between the output data because of the difference of the transition directions. As a result, skew occurs between the output data. The skew will increase as the number of bits comprising the output data increases, the parasitic components increase, and as the operation speed increases. 
     FIG. 1 is a circuit diagram illustrating a conventional data output circuit. The data output circuit comprises a plurality of data output drivers  10 - 1  to  10 - n,  parasitic components  12  and  14 , and a capacitor C 3 . The data output drivers  10 - 1  to  10 - n  drive input data bits D 1  to D n  to generate output data bits DQ 1  to DQn, respectively. Each of the data output drivers  10 - 1  to  10 - n  comprises an inverter comprising a PMOS transistor P 1  and an NMOS transistor N 1 . The parasitic component  12  is represented by a resistor R 1 , an inductor L 1 , and a capacitor C 1 , connected between an external power voltage VDDQ and each power voltage terminal of the data output drivers  10 - 1  to  10 - n.  The parasitic component  14  is represented by a resistor R 2 , an inductor L 2  and a capacitor C 2 , connected between an external ground voltage VSSQ and each ground voltage terminal of the data output drivers  10 - 1  to  10 - n.    
     The data output drivers  10 - 1  to  10 - n  drive the input data bits D 1  to Dn to generate the output data bits DQ 1  to DQn, respectively. When the output data bits DQ 1  to DQn change their logic levels (e.g., from a high level to a low level or vice versa), a large amount of current is drawn through power lines for receiving the external power voltage VDDQ and for receiving the external ground voltage VSSQ. Consequently, a transition noise occurs due to the parasitic components  12  and  14 . The capacitor C 3  is connected between the parasitic components  12  and  14  for interactively changing the external power voltage VDDQ and the external ground voltage. 
     FIGS. 2A to  2 C are graphs illustrating a relationship between the external power voltage VDDQ the external ground voltage VSSQ, and the output data bits DQ 1  to DQn of FIG. 1, during logic level transitions of output data bits DQ 1  to DQn. 
     As illustrated in FIG. 2A, when input data bits D 1  to D((n+2) transition from a logic “low” level to a logic “high” level and input data bits D((n+1)/2) to Dn transition from a logic “high” level to a logic “low” level, output data bits DQ 1  to DQ(n/2) transition from a logic “high” level to a logic “low” level and output data bits DQ((n+1)/2) to DQn transition from a logic “low” level to a logic “high” level. Because of the transition of each of the n/2 bits, the level of the external power voltage VDDQ falls and a level of the external ground voltage VSSQ rises. 
     As further illustrated in FIG. 2B, when input data bits D 1  to D(n−1) transition from a logic “low” level to a logic “high” level and input data bit Dn transitions from a logic “high” level to a logic “low” level, output data bits DQ 1  to DQ(n−1) transition from a logic “high” level to a logic “low” level and output data bit DQn transitions from a logic “low” level to a logic “high” level. 
     At this moment, because the input data bits D 1  to D(n−1) transition from a logic “low” level to a logic “high” level, the voltage levels of the external ground voltage VSSQ and the external power voltage VDDQ rise significantly due to the capacitor C 3 . Consequently, a threshold voltage of each NMOS transistor N 1  of the data output drivers  10 - 1  to  10 - n  rises, causing the transition time from a logic “high” to a logic “low” level of the output data bits DQ 1  to DQ(n−1) to become slower as shown in FIG.  2 B. Further, a threshold voltage of each PMOS transistor P 1  of the data output drivers  10 - 1  to  10 - n  also rises, so that the transition time from a logic “low” to a logic “high” level of the output data bit DQn becomes faster. That is, skew occurs between output data bits DQ 1  to DQ(n−1) and the output data bit DQn, as illustrated in FIG.  2 B. 
     Further, as shown in FIG. 2C, when the transition time from a logic “low” to a logic “high” level of the output data bits DQ 1  to DQ(n−1) becomes slower, and the transition time from a logic “high” to a logic “low” level of the output data bit DQn becomes faster, skew occurs between the output data bits DQ 1  to DQ(n−1) and the output data bit DQn. 
     As described above, in conventional semiconductor devices, as the number of output bits increases, skew occurs between output data that transitions from a logic “high” level to a logic “low” level and other output data that transitions from a logic “low” level to a logic “high” level. 
     SUMMARY OF THE INVENTION 
     To overcome the above problems, it is an object of the present invention to provide a semiconductor device and output method thereof for minimizing skew between plural-bit output data. 
     According to one aspect of the present invention, a data output circuit of a semiconductor device comprises a plurality of data output drivers for generating plural-bit output data. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state, in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state, in response to signals received from other data output drivers. 
     Preferably, the first delay circuit comprises a plurality of first switching devices, which are activated in response to the first state of the input data, for transitioning a level of the input data from the first state to the second state; and a plurality of first capacitors for delaying the transition delay time of the input data having the first state. Each of first capacitors are connected to a corresponding one of the first switching devices and an internal ground voltage. The second delay circuit preferably comprises a plurality of second switching devices, which are activated in response to the second state of the input data, for transitioning a level of the input data from the second state to the first state; and a plurality of second capacitors, connected between the plurality of the second switching devices and an internal ground voltage, for varying the transition delay time of the input data having the second state. 
     According to another aspect of the present invention, a semiconductor device comprises a controller for receiving plural-bit input data and a plurality of data output drivers. The plural-bit input data comprise a first group of bits that transition from a first state to a second state and a second group of bits that transition from the second state to the first state. The controller compares the number of bits in the first group and the number of bits in the second group to generate a falling transition delay time control signal and a rising transition delay time control signal. The plurality of data output drivers generate plural-bit output data in response to the plural-bit input data and the falling and rising transition delay time control signals. 
     According to another aspect of the present invention, a semiconductor device comprises a controller for receiving plural-bit input data, wherein the plural-bit input data comprises a first group of bits that transition from a first state to a second state and a second group of bits that transition from the second state to the first state, and wherein the controller compares the number of bits in the first group and the number of bits in the second group to generate a falling transition delay time control signal and a rising transition delay time control signal; a plurality of clock signal generators for receiving a clock signal and generating a delayed clock signal with respect to each of the plural-bit input data in response to the rising transition delay time control signal and the falling transition delay time control signal, respectively; a plurality of registers for receiving the plural-bit input data in response to the corresponding delayed clock signal, respectively; and a plurality of data output drivers for generating plural-bit output data in response to the output from the plurality of the registers, respectively. 
     According to further aspect of the present invention, a method is provided for outputting plural-bit output data in a semiconductor device comprising a plurality of data output drivers, in which the plurality of data output drivers are connected between an external power voltage and an external ground voltage, pull up the plural-bit output data is in response to plural-bit input data of a first state, and pull down the plural-bit output data in response to the plural-bit input data of a second state. The method comprises the steps of: receiving a first group of the plural-bit input data that transition from the second state to the first state and a second group of the plural-bit input data that transition from the first state to the second state; comparing the number of bits in the first group with the number of bits in the second group to generate a rising transition delay time control signal and a falling transition delay time control signal; controlling transition delay time of the first group and the second group in response to the rising transition delay time control signal and the falling transition delay time control signal, respectively; and generating the plural-bit output data in response to the plural-bit input data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which: 
     FIG. 1 is a circuit diagram illustrating a conventional data output circuit of a semiconductor device; 
     FIGS. 2A to  2 C are graphs illustrating a relationship between an external power voltage, an external ground voltage and the output data of FIG. 1; 
     FIG. 3 is a circuit diagram illustrating a data output circuit according to one embodiment of the present invention; 
     FIG. 4 is a block diagram illustrating a data output circuit according to another embodiment of the present invention; 
     FIG. 5 is a block diagram illustrating a data output driver according to an embodiment of the present invention; and 
     FIG. 6 is a block diagram illustrating a data output circuit according to another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 3 is a circuit diagram illustrating a data output circuit according to one embodiment of the present invention. Referring to FIG. 3, a data output circuit comprises a plurality of data output drivers  20 - 1  to  20 - n . Each of the data output drivers  20 - 1  to  20 - n  comprises buffers I 1  and I 2 , delay circuits DY 1  and DY 2 , a PMOS transistor P 1 , and an NMOS transistor N 1 . 
     The delay circuit DY 1  comprises a plurality of NMOS transistors MN 1 ( 1 ) to MN 1 (n−1) serial-connected to each other and connected an output terminal of the buffer I 1 , and a plurality of PMOS capacitors MPC( 1 ) to MPC(n−1) connected between respective NMOS transistors MN 1 ( 1 ) to MN 1 (n−1) and an internal power voltage VDD. The delay circuit DY 2  comprises a plurality of NMOS transistors MN 2 ( 1 ) to MN 2 (n−1) serial-connected to each other and connected an output terminal of the buffer  12 , and a plurality of NMOS capacitors MNC( 1 ) to MNC(n−1) connected between respective NMOS transistors MN 2 ( 1 ) to MN 2 (n−1) and an internal ground voltage VSS. 
     The NMOS transistors MN 1 ( 1 ) to MN 1 (n−1) and the NMOS transistors MN 2 ( 1 ) to MN 2 (n−1) of each data output driver receive signals at their gate terminals from the output of buffers I 1  and I 2  from other drivers. For example, the NMOS transistors MN 1 ( 1 ) to MN 1 (n−1) and MN 2 ( 1 ) to MN 2 (n−1) of the delay circuits DY 1  and DY 2  of the data output driver  20 - 1  receive gate signals p 2  to pn and n 2  to nn from the output of buffers I 1  and I 2  of the data output drivers  20 - 2  to  20 - n.    
     For each output driver  20 - 1  to  20 - n , an external power voltage VDDQ is applied to the source of the PMOS transistor P 1 , and an external ground voltage VSSQ is applied to the source of the NMOS transistor N 1 . The PMOS transistor P 1  and the NMOS transistor N 1  are connected at their drains. 
     In output driver  20 - 1 , for example, the buffer I 1  buffers data D 1  to generate a signal p 1 , and the buffer I 2  buffers data bit D 1  to generate signal n 1 . Each of the NMOS transistors MN 1 ( 1 ) to MN 1 (n−1) of the delay circuit DY 1  turns on in response to corresponding gate signals p 2  to pn having logic “low” levels. When the signal p 1  having a logic “low” level is applied to the delay circuit DY 1 , the PMOS capacitors MPC( 1 ) to MPC(n−1) turn on to delay the signal p 1 . Each of the NMOS transistors MN 2 ( 1 ) to MN 2 (n−1) of the delay circuit DY 2  turns on in response to the signals n 2  to nn having logic “high” levels. When the signal n 1  having a logic “high” level is applied to the delay circuit DY 2 , the NMOS capacitors MNC( 1 ) to MNC(n−1) turn on to delay the signal n 1 . The NMOS transistor MN 1 ( 1 ) makes output data bit DQ 1  to change from a logic “low” level to a logic “high” level in response to the signal p 1  having a logic “low” level, and the NMOS transistor MN 21  makes the output data bit DQ 1  to change from a logic “high” level to a logic “low” level in response to the signal n 1  having a logic “high” level. 
     The other data output drivers  20 - 2  to  20 - n  operate similarly to the data output driver  20 - 1  and, thus detailed explanation of their operation is omitted to avoid redundancy. 
     By way of example, assume that “n” is 4 (i.e., output data comprises output data bits DQ 1  to DQ 4 . Assume further that output data bits DQ 1  to DQ 3  transition from a logic “high” level to a logic “low” level, and output data bit DQ 4  transitions from a logic “low” level to a logic “high” level. When the output data bits D 1  to D 3  transition from a logic “low” level to a logic “high” level and output data bit D 4  transitions from a logic “high” level to a logic “low” level, the buffers I 1  and I 2  of each data output driver (e.g.,  20 - 1  to  20 - 4 ) generate the buffered signals p 1  to p 3  and n 1  to n 3  having a logic “high” level and the buffered signals p 4  and n 4  having a logic “low” level. 
     At this time, in each delay circuit DY 2  of three data output drivers (e.g.,  20 - 1  to  20 - 3 ), the NMOS capacitors MNC( 1 ) and MNC( 2 ) turn on in response to the buffered signals n 2  and n 3 , n 1  and n 3 , and n 1  and n 2  to delay the signals n 1  to n 3 . And then, each NMOS transistor N 1  of the data output drivers  20 - 1  to  20 - 3  makes the output data bits DQ 1  and DQ 3  to change to a logic “low” level, in response to the signals n 1  to n 3 , respectively. Meanwhile, in the delay circuit DY 1  of the last data output driver (e.g.,  204 ), the NMOS transistors MN 1 ( 1 ) to MN 1 ( 3 ) turn on in response to the buffered signals p 1  to p 3  having a logic “high” level, and the PMOS capacitors MPC( 1 ) to MPC( 3 ) turn on in response to the signal p 1  having a logic “low” level to delay the signal p 1 . The PMOS transistor P 1  of the data output driver  20 - 4  makes the output data bit DQ 4  transition to a logic “high” level in response to the signal p 1 . 
     As described above, a transition of output data bit DQ 4  from a logic “low” level to a logic “high” level is slower than the transitions of output data bits DQ 1  to DQ 3  from a logic “high” level to a logic “low” level, that is, the delay time of the output data bit DQ 4  is longer than that of the output data bits DQ 1  to DQ 3 . In contrast to the conventional data output circuit in which three-bit output data DQ 1  to DQ 3  are more delayed than the one-bit output data DQ 4  as shown in FIG. 2B, in a data output circuit according to the embodiment as shown in FIG. 3, output data bit DQ 4  is more delayed than output data bits DQ 1  to DQ 3  and thus, skew between four-bit output data DQ 1  to DQ 4  is reduced. 
     FIG. 4 is a block diagram illustrating a data output circuit according to another embodiment of the present invention. The data output circuit of FIG. 4 comprises registers  30 - 1  to  30 - n , data output drivers  32 - 1  to  32 - n  and a control circuit  34 . 
     The registers  30 - 1  to  30 - n  receive respective input data bits D 1  to Dn and output respective data bits D 01  to D 0   n  to the data output drivers  32 - 1  to  32 - n , in response to a clock signal CLK. 
     The control circuit  34  receives the input data bits D 1  to Dn and compares the number of data bits that transitioned to a logic “high” level with the number of data bits that transitioned to a logic “low” level, to thereby generate a falling transition delay time control signal C 1  and a rising transition delay time control signal C 2 . When the number of data bits that transitioned to a logic “high” level is greater than the number of data bits that transitioned to a logic “low” level, the control circuit  34  makes the delay time of the bits that transitioned to a logic “low” level (i.e., the falling transition delay time) longer than the delay time of the data bits that transitioned to a logic “high” level (i.e., the rising transition delay time), thereby decreasing skew between the output data bits DQ 1  to DQn. On the other hand, when the number of data bits that transitioned to a logic “low” level is greater than the number of data bits that transitioned to a logic “high” level, the control circuit  34  makes the rising transition delay time longer than the falling transition delay time, thereby decreasing skew between the output data bits DQ 1  to DQn. 
     The data output drivers  32 - 1  to  32 - n  receive a corresponding one of the data bits D 01  to D 0   n , and each driver  32 - 1  to  32 - n  receives the falling transition delay time control signal C 1  and the rising transition delay time control signal C 2  from the control circuit to generate output data bits DQ 1  to DQn. In response to a rising transition delay time control signal C 2  and the data bits D 01  to D 0 n having a logic “low” level, the data output drivers  32 - 1  to  32 - n  generate output data bits DQ 1  to DQn having a logic “high” level. And, in response to the falling transition delay time control signal C 1  and the data bits D 01  to D 0   n  having a logic “high” level, the data output drivers  32 - 1  to  32 - n  generate the output data bits DQ 1  to DQn having a logic “low” level. 
     In a data output circuit having an embodiment shown in FIG. 3, as the number of the output data bits DQ 1  to DQn increases, the number of transistors of each delay circuit of the data output drivers increases, whereas in a data output circuit having an embodiment as shown in FIG. 4, the number of the transistors of each delay circuit of the data output drivers decreases. In particular, the data output circuit of FIG. 3 uses all the data bits as a control signal for controlling delay time, but the data output circuit of FIG. 4 divides the data bits into several data (having different bit number to use the divided bit data as a control signal. For example, 16-bit data is divided into two 8-bit data or four 4-bit data. Therefore, the number of the transistors of the delay circuits of each of the data output drivers could be decreased using the embodiment of FIG.  4 . 
     FIG. 5 is a block diagram illustrating an embodiment of a data output driver of FIG. 4 according to the present invention. Each of the data output drivers  32 - 1  to  32 - n  comprises delay circuits DY 1  and DY 2 , a PMOS transistor P 1  and an NMOS transistor N 1 . 
     The delay circuits of FIGS. 3 and 5 have similar configurations except that the delay circuits DY 1  of FIG. 5 receive the falling transition delay time control signal C 1 , and the delay circuits DY 2  of FIG. 5 receive the rising transition delay time control signal C 2 . Operation of the data output drivers of FIG. 5 can be understood with reference to FIG.  3  and thus their description is omitted to avoid redundancy. 
     FIG. 6 is a block diagram illustrating a data output circuit according to another embodiment of the present invention. The data output circuit of FIG. 6 comprises buffers  40 - 1  to  40 - n,  clock signal delay circuits  42 - 1  to  42 - n,  registers  44 - 1  to  44 - n,  data output drivers  46 - 1  to  46 - n,  and a control circuit  48 . 
     The buffers  40 - 1  to  40 - n  buffer input data bits D 1  to Dn and output data bits DA 1  to Dan. The clock signal delay circuits  42 - 1  to  42 - n  delay a falling transition of a clock signal CLK in response to a falling transition delay time control signal C 1  output from the control circuit  48  and delay a rising transition of the clock signal CLK in response to a rising transition delay time control signal C 2  to generate clock signals CLK1 to CLKn. The registers  44 - 1  to  44 - n  generate data bits DB 1  to DBn having a logic “low” level in response to a rising transition of the clock signals CLK1 to CLKn and generate data bits DB 1  to DBn having a logic “high” level in response to a falling transition of the clock signals CLK 1  to CLKn. Accordingly, the delay time of data that is output from the registers  44 - 1  to  44 - n  in response to the clock signals CLK1 to CLKn is controlled. The data output drivers  46 - 1  to  46 - n  drive the data bits DB 1  to DBn to generate output data bits DQ 1  to DQn. The control circuit  48  receives the data bits D 1  to Dn and compares the number of data bits that transitioned to a logic “low” level with the number of data bits that transitioned to a logic “high” level, to thereby generate the falling transition delay time control signal C 1  or the rising transition delay time control signal C 2 . 
     In the data output circuit of FIG. 6, the falling transition and the rising transition of the clock signals CLK1 to CLKn are controlled by the control signals C 1  and C 2  to thereby decrease the skew between the output data bits DQ 1  to DQn. The clock signal delay circuits  42 - 1  to  42 - n  of FIG. 6 comprise the same configuration as the data output drivers  32 - 1  to  32 - n  of FIG. 5 except that the clock signal CLK is applied thereto instead of the data bits D 1  to Dn. 
     As described herein before, the semiconductor device compares the number of data bits that transitioned to a logic “high” level with the number of data bits that transitioned to a logic “low” level, to control a delay time of the plural-bit output data, thereby decreasing skew between the plural-bit output data. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.