Abstract:
A noise elimination circuit which can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level comprises: a ring oscillator unit for receiving first and second signals and generating a pulse signal according to the first signal, and stopping generation of the pulse signal when the first and the second signals have a first potential level; and a frequency division unit for receiving an output signal of the ring oscillator unit and then, N times frequency-dividing to generate the signal to the second signal, and being reset by the first signal.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates generally to a noise elimination circuit, and in particular, to an improved noise elimination circuit which can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level.  
           [0003]    2. Description of the Background Art  
           [0004]    [0004]FIG. 1 is a circuit diagram illustrating a conventional noise elimination circuit.  
           [0005]    Referring to FIG. 1, the conventional noise elimination circuit includes: an inverter INV 1  receiving a reset bar signal /RESET, and outputting an inverted signal to a node Nd 1 ; a noise elimination unit  10  receiving the signal transmitted to the node Nd 1 , for eliminating noise of the signal, and outputting the resultant signal to a node Nd 2 ; a NOR gate NOR 1  NORing the signals of the nodes Nd 1 , Nd 2 ; an AND gate AND 1  ANDing the signals of the nodes Nd 1 , Nd 2 ; and an RS latch circuit unit  12  receiving the output signal from the NOR gate NOR 1  as a set signal and the output signal from the AND gate AND 1  as a reset signal, and generating a chip reset signal to an output terminal Q.  
           [0006]    In the conventional noise elimination circuit, when the reset bar signal /RESET is enabled in a low level, the signal of the node Nd 1  is transited to a high level by the inverter INV 1 . The signal of the node Nd 1  (high) outputs a high level signal to the node Nd 2  through the noise elimination unit  10  after a delay time tl. Accordingly, the reset input of the RS latch circuit unit  12  is enabled in a high level, thus clearing the RS latch circuit unit  12 .  
           [0007]    Here, the noise elimination unit  10  eliminates noise of the reset bar signal /RESET, so that an unwanted chip reset signal cannot be generated due to noise in the signal.  
           [0008]    [0008]FIG. 2A is a circuit diagram illustrating a noise elimination unit using the R-C delay shown in FIG. 1, and FIG. 2B is a circuit diagram illustrating a noise elimination unit using an inverter and capacitor delay shown in FIG. 1.  
           [0009]    As illustrated in FIG. 2A, the conventional noise elimination unit  10  includes: an inverter INV 2  and a resistor R 1  connected in series between the nodes Nd 1 , Nd 3 ; a capacitor C 1  connected between the node Nd 3  and the ground voltage Vss; a resistor R 2  connected between the nodes Nd 3 , Nd 4 ; a capacitor C 2  connected between the node Nd 4  and the ground voltage Vss; a resistor R 3  connected between the nodes Nd 4 , Nd 5 ; a capacitor C 3  connected between the node Nd 5  and the ground voltage Vss; and an inverter INV 3  connected between the nodes Nd 5 , Nd 2 .  
           [0010]    As depicted in FIG. 2B, the conventional noise elimination unit  10  using the inverter and capacitor delay includes: an inverter INV 4  connected between the nodes Nd 1 , Nd 6 ; a capacitor C 4  connected between the node Nd 6  and the ground voltage Vss; an inverter INV 5  connected between the nodes Nd 6 , Nd 7 ; a capacitor C 5  connected between the node Nd 7  and the ground voltage Vss; an inverter INV 6  connected between the nodes Nd 7 , Nd 8 ; a capacitor C 6  connected between the node Nd 8  and the ground voltage Vss; and an inverter INV 7  connected between the nodes Nd 8 , Nd 2 .  
           [0011]    The operation of the conventional noise elimination unit  10  will now be explained.  
           [0012]    When the signal of the node Nd 1  is inputted to the noise elimination unit  10 , the signal is outputted to the node Nd 2  without noise after a predetermined delay time t 1  in the noise elimination unit  10 . That is, when the signal of the node Nd 1  has a smaller noise period than the delay time t 1 , the noise elimination unit  10  filters the signal to prevent influence of the noise on the signal of the node Nd 2 .  
           [0013]    Accordingly, the reset input signal of the RS latch circuit unit  12  (FIG. 1) has a low level, and thus the output signal Q is maintained as it is.  
           [0014]    However, the conventional noise elimination circuit has a disadvantage in that when noise is consecutively generated before the delay time, the noise elimination unit does not successfully eliminate noise.  
           [0015]    The problem of the conventional noise elimination circuit will now be explained with reference to FIGS. 3A and 3B.  
           [0016]    Referring to FIG. 3A, when noise t 2 -t 4  is consecutively inputted to the reset bar signal /RESET after the delay time t 1 , the signals of the nodes Nd 3 , Nd 4 , Nd 5  of the noise elimination unit  10  gradually reduce the corresponding potential levels. As shown in FIG. 3A(f), the signal outputted to the node Nd 2  through the inverter INV 3  has an undesirable high level, as shown by the spike.  
           [0017]    The high level signal of the node Nd 2  converts the reset input signal of the RS latch circuit unit  12  into a high level signal, and thus converts the output signal Q into a high level signal. That is, the chip reset signal is generated due to unwanted noise, which causes a misoperation of the circuit.  
           [0018]    As illustrated in FIG. 3B, when noise t 5 -t 6  is consecutively inputted to the reset bar signal /RESET after the delay time t 1 , the signals of the nodes Nd 6 , Nd 7 , Nd 8  of the noise elimination unit  10  gradually reduce the corresponding potential levels. As shown in FIG. 3B(f), the signal outputted to the node Nd 2  through the inverter INV 7  has an undesirable high level.  
           [0019]    The high level signal of the node Nd 2  converts the reset input signal of the RS latch circuit unit  12  into a high level signal. Therefore, the chip reset signal is generated due to unwanted noise, thereby causing a misoperation of the circuit.  
         SUMMARY OF THE INVENTION  
         [0020]    Accordingly, it is an object of the present invention to provide a noise elimination circuit that can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level, by varying a filtering time through a ring oscillator and a frequency division circuit.  
           [0021]    In order to achieve the above-described object of the present invention, there is provided a noise elimination circuit including: a ring oscillator unit for receiving first and second signals and generating a pulse signal according to the first signal, and stopping generation of the pulse signal when the first and the second signals have a first potential level; and a frequency division unit for receiving an output signal of the ring oscillator unit and then, N times frequency-dividing to generate the signal to the second signal, and being reset by the first signal. When the first potential is at a logic high level, and the second potential is at a logic low level. Conversely, when the first potential is at a logic low level, and the second potential is at a logic high level.  
           [0022]    Preferably, the ring oscillator unit includes: a third inverter for inverting a signal of the first node, and outputting the inverted signal to a third node; an OR gate for ORing the signals of the third node and the second node, and outputting the resultant signal to a fourth node; a fourth inverter for inverting a signal of a fifth node according to the signal of the fourth node; a resistor connected between the output terminal of the fourth inverter and a sixth node; fifth and sixth inverters connected in series between the sixth node and the fifth node; a capacitor connected between the fifth node and the sixth node; an NMOS transistor for discharging a signal of the sixth node into the ground voltage according to the signal of the fourth node; and seventh and eight inverters connected in series between the fifth node and the seventh node.  
           [0023]    In addition, the frequency division of the frequency division circuit unit is dependent upon the structure and design of the ring oscillator unit.  
           [0024]    According to another aspect of the present invention, a noise elimination circuit includes: a first inverter receiving a reset bar signal, and outputting an inverted signal to a first node; a noise elimination unit receiving the signal of the first node, eliminating all noise of the signal, and outputting the resultant signal to a second node; a second inverter inverting the signal of the first node; an AND gate ANDing the signal of the first node and the signal of the second node; and an RS latch circuit unit receiving the output signal from the second inverter as a set signal and the output signal from the AND gate as a reset signal, and generating a chip reset signal to an output terminal.  
           [0025]    Preferably, the noise elimination unit includes: a ring oscillator unit generating a pulse signal having a predetermined period when the signal of the first node is at a first potential, stopping the operation and clearing an output signal thereof, when the signal of the second node is at the first potential; and a frequency division circuit unit frequency-dividing the output signal from the ring oscillator unit, outputting the frequency-divided signal to the second node, and being reset when the signal of the first node is at the second potential. When the first potential is at a logic high level, and the second potential is at a logic low level. Conversely, when the first potential is at a logic low level, and the second potential is at a logic high level.  
           [0026]    Preferably, the ring oscillator unit includes: a third inverter for inverting a signal of the first node, and outputting the inverted signal to a third node; an OR gate for ORing the signals of the third node and the second node, and outputting the resultant signal to a fourth node; a fourth inverter for inverting a signal of a fifth node according to the signal of the fourth node; a resistor connected between the output terminal of the fourth inverter and a sixth node; fifth and sixth inverters connected in series between the sixth node and the fifth node; a capacitor connected between the fifth node and the sixth node; an NMOS transistor for discharging a signal of the sixth node into the ground voltage according to the signal of the fourth node; and seventh and eight inverters connected in series between the fifth node and the seventh node.  
           [0027]    The frequency division of the frequency division circuit unit is dependent upon the design of the ring oscillator unit.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein:  
         [0029]    [0029]FIG. 1 is a circuit diagram illustrating a conventional noise elimination circuit;  
         [0030]    [0030]FIG. 2A is a circuit diagram illustrating the conventional noise elimination unit using an R-C delay of FIG. 1;  
         [0031]    [0031]FIG. 2B is a circuit diagram illustrating the conventional noise elimination unit using an inverter and capacitor delay of FIG. 1;  
         [0032]    [0032]FIG. 3A is an operation timing diagram of the conventional noise elimination circuit using the R-C delay of FIG. 1;  
         [0033]    [0033]FIG. 3B is an operation timing diagram of the conventional noise elimination circuit using the inverter and capacitor delay of FIG. 1;  
         [0034]    [0034]FIG. 4 is a circuit diagram illustrating a noise elimination circuit in accordance with a preferred embodiment of the present invention;  
         [0035]    [0035]FIG. 5 is a detailed circuit diagram illustrating the noise elimination unit shown in FIG. 4; and  
         [0036]    [0036]FIG. 6 is an operation timing diagram of the noise elimination circuit by nodes in accordance with the preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0037]    A noise elimination circuit in accordance with a preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawing FIGS.  4 - 6 .  
         [0038]    [0038]FIG. 4 is a circuit diagram illustrating the noise elimination circuit in accordance with the preferred embodiment of the present invention, and FIG. 5 is a detailed circuit diagram illustrating the noise elimination unit shown in FIG. 4.  
         [0039]    Referring to FIG. 4, the noise elimination circuit includes: an inverter INVll receiving a reset bar signal /RESET, and outputting an inverted signal to a node Nd 11 ; a noise elimination unit  100  receiving the signal transmitted to the node Nd 11 , eliminating the noise of the signal, and outputting the resultant signal to a node Nd 12 ; an inverter INV 12  inverting the signal of the node Nd 11 ; an AND gate AND 11  ANDing the signals of the nodes Nd 11 , Nd 12 ; and an RS latch circuit unit  120  receiving the output signal from the inverter INV 12  as a set signal and the output signal from the AND gate AND 11  as a reset signal, and generating a chip reset signal to an output terminal Q.  
         [0040]    Here, the noise elimination unit  100  eliminates noise of the reset bar signal /RESET.  
         [0041]    As illustrated in FIG. 5, the noise elimination unit  100  includes: a ring oscillator unit  102  for generating a pulse signal having a predetermined period when the signal of the node Nd 11 , which is an input signal, has a high level, stopping the operation when the signal of the node Nd 12 , which is an output signal, is enabled at a high level, and clearing a signal at its output terminal Nd 17 ; and a frequency division circuit unit  104  frequency-dividing the output signal from the ring oscillator unit  102 , outputting the frequency-divided signal to the node Nd 12 , and being reset when the signal of the node Nd 11  has a low level. Here, the frequency division of the frequency division circuit unit  104  is dependent upon the design of the ring oscillator unit  102 .  
         [0042]    The ring oscillator unit  102  includes: an inverter INV 13  for inverting a signal of the node Nd 11 , and outputting the inverted signal to a node Nd 13 ; an OR gate OR 11  for ORing the signals of the nodes Nd 13 , Nd 12 , and outputting the resultant signal to a node Nd 14 ; an inverter INV 16  for inverting a signal of a node Nd 16  according to the signal of the node Nd 14 ; a resistor R 11  connected between the output terminal of the inverter INV 16  and a node Nd 15 ; inverters INV 14 , INV 15  connected in series between the nodes Nd 15 , Nd 16 ; a capacitor C 11  connected between the nodes Nd 16 , Nd 15 ; an NMOS transistor N 11  for discharging a signal of the node Nd 15  into the ground voltage Vss according to the signal of the node Nd 14 ; and inverters INV 17 , INV 18  connected in series between the nodes Nd 16 , Nd 17 .  
         [0043]    The operation of the noise elimination circuit in accordance with the present invention will now be explained.  
         [0044]    [0044]FIG. 6 is an operation timing diagram of the noise elimination circuit shown in FIG. 5 in accordance with the preferred embodiment of the present invention.  
         [0045]    As shown in FIG. 6, when the reset bar signal /RESET is enabled at a low level and then disabled at a high level, the signal of the node Nd 11 , which is an input signal of the noise elimination unit  100 , has an opposite signal to the input signal by the inverter INV 11 . That is, when the reset bar signal /RESET is disabled at a high level and noise t 2 -t 4  is consecutively applied, the signal of the node Nd 11  is also influenced.  
         [0046]    When the signal of the node Nd 11  has a high level, the ring oscillator unit  102  of the noise elimination unit  100  is operated to generate to the node Nd 17  a pulse signal (FIG. 6( c )) having a predetermined period. Thereafter, the signal of the node Nd 17  is frequency-divided through the frequency division circuit unit  104 , thus outputting the frequency-divided pulse signal to the node Nd 12 . Here, the frequency-divided signal outputted to the node Nd 12  is a signal enabled at a high level after a frequency division time t 1  of the frequency division circuit unit  104 . In addition, the high level signal of the node Nd 12  and the high level signal of the node Nd 11  reset the RS latch circuit unit  120  by the AND gate AND 11 , thereby generating the chip reset signal to the output terminal Q.  
         [0047]    When the signal of the node Nd 12  is enabled at a high level, the inverter INV 16  of the ring oscillator unit  102  is turned off, and the NMOS transistor N 11  is turned on, thus discharging the potential. Accordingly, the ring oscillator unit  102  is disabled.  
         [0048]    Therefore, the output signal of the ring oscillator unit  102  is cleared. Here, the frequency division circuit unit  104  is not operated according to the signal of the node Nd 13  (high), which is an inverted signal of the node Nd 11 , and maintains a current output state value. In order to reoperate the frequency division circuit unit  104 , the signal of the node Nd 12  must be cleared at a low level. In addition, the externally-inputted reset bar signal /RESET must be disabled at a high level. That is, the signal of the node Nd 11  must be transited to a low level.  
         [0049]    Here, the previous-operation value does not influence the current operation, by resetting the noise elimination unit  100  according to the reset bar signal /RESET.  
         [0050]    The noise elimination circuit of the present invention clears the output signal of the ring oscillator unit  102  during a period where the reset bar signal /RESET has a high level (namely, the node Nd 11  has a low level), and operates the ring oscillator unit  102  in a period where the reset bar signal /RESET has a low level (namely, the node Nd 11  has a high level), thereby generating to the node Nd 17  a pulse signal of a predetermined period. The frequency division circuit unit  104  receives the signal of the node Nd 17 , and outputs a signal enabled at a high level to the node Nd 12  after the frequency division time t 1 .  
         [0051]    Referring to FIG. 6, the input period of the noise t 2 -t 4  applied to the reset bar signal /RESET is smaller than the frequency division time t 1  of the frequency division circuit unit  104 . As a result, the noise elimination circuit of the present invention includes the ring oscillator unit  102  for generating the pulse signal having a predetermined period in a low period of the reset bar signal /RESET, and frequency-divides the pulse signal from the ring oscillator unit  102  through the frequency division circuit unit  104 , to eliminate the noise of the input signal.  
         [0052]    In the noise elimination circuit shown in FIGS. 4 and 5, the ring oscillator unit  102  and the frequency division circuit unit  104  are designed to be reset at a high level period of the node Nd 11  for applications to the low active signal.  
         [0053]    In another embodiment of the present invention, the ring oscillator unit  102  and the frequency division circuit unit  104  may be reset at a low level period of the node Nd 11  in order to be operated at a high active period of the input signal.  
         [0054]    As discussed earlier, the noise elimination circuit in accordance with the present invention can adjust the period of the noise applied to the input signal smaller than the filtering time, by using the ring oscillator unit and the frequency division circuit unit, which prevents a misoperation of the circuit due to noise.  
         [0055]    As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description which are illustrative only, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes, alterations and modifications that fall within the meets and bounds of the claims, or equivalences thereof are intended to be embraced by the appended claims.