Abstract:
A DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor is desposed in a substrate; a gate is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and an upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. The DRAM cell can be applied to an open bitline DRAM, a folder bitline DRAM, and a foler bitline DRAM with bordless bitline contact window.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a dynamic random access memory (DRAM). In particular, the present invention relates to a DRAM with vertical transistors and deep trench capacitors.  
           [0003]    2. Description of the Related Art  
           [0004]    With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are produced based on different objectives. DRAM is such an important semiconductor device in the information and electronics industry.  
           [0005]    Most of the DRAMs nowadays have one transistor and one capacitor in one DRAM cell. The memory capacity of the DRAM has reached 64 megabits, and can even reach 256 megabits. Therefore, under the increasing of the integration it is needed to shrink the size of the memory cell and the transistor so as to manufacture the DRAM with higher memory capacity and higher processing speed. A 3-D capacitor structure itself can reduce its occupation area in the semiconductor substrate, so the 3-D capacitor, such as a deep trench capacitor, is applied to the fabrication of the DRAM of 64 megabits and above. Referring to a traditional plane transistor, it covers quite a few areas of the semiconductor substrate and cannot satisfy the request of high integration. Therefore, a vertical transistor which can save space is a trend of fabrication of a memory unit.  
           [0006]    One of the most used DRAM cell array is an open bitline structure, in which each memory cell is arrayed with a matrix.  
           [0007]    Another frequently used DRAM cell array is a folded bitline structure, as shown in FIG. 9. Each memory cell, using label  10  as an example, comprises a transistor  12 , a storage capacitor  14 , a bitline  22 , a wordline  18  and a passing wordline  20 . When an approproate voltage is applied to the bitline  22  and the wordline  18 , data can be written into or read from the capacitor  14 . When an output volage is applied to the memory cell  10  covering the connecting wordline  18  and the passing wordline  20 , bitlines  22  and  24  are switched to differential sense amplifier.  
           [0008]    [0008]FIG. 10 is a cross-sectional view of the memory cell  10  in FIG. 9. The wordline  18  is also used as a gate of the transistor  12 . The passing wordline  20  is located over the thick oxide layer  36 , and works no function for operation of the memory cell  10 . The bitline  22  is connected to a source  40  of the transistor  12  through a contact window  38 . A drain  42  of the transistor  12  is connected to the deep trench capacitor  44  through a buried strap  41 .  
           [0009]    However, such structure of the memory cell  10  has some challenges as described below. The outdiffusion of the dopants contained in the buried strap  41  may induce the short channel effect. Therefore, it is impossible to decrease the distance between the wordline  18  and deep trench capacitor  44  to increase the integration of the DRAM.  
           [0010]    With the enhancement of the memory capacity, a DRAM with more compact transistors and deep trench capacitors is needed to satisfy the requirements of memory capacity.  
         SUMMARY OF THE INVENTION  
         [0011]    An object of the present invention is to provide a DRAM cell array with a vertical transistor and a deep trench capacitor, so as to release the limitation from the wordline to deep trench to increase the integration of the DRAM.  
           [0012]    Another object of the present invention is to provide an open bitline DRAM with a vertical transistor and a deep trench capacitor, so as to increase the integration of the DRAM.  
           [0013]    Another object of the present invention is to provide a folder bitline DRAM with avertical transistor and a deep trench capacitor, so as to increase the integration of the DRAM.  
           [0014]    Another object of the present invention is to provide a folder bitline DRAM with a vertical transistor, a deep trench capacitor and a borderless bitline contact window, so as to increase the integration of the DRAM.  
           [0015]    The present invention provides a DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor comprising an upper electrode, an insulating film and a storage electrode is desposed in a substrate; a gate of the vertical transistor is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and the upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer of the vertical transistor is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. Moreover, a shallow trench isolation is disposed on another sidewall of the ion doped layer.  
           [0016]    The present invention provides an open bitline DRAM with straight wordlines, wherein each DRAM cell is as mentioned above, the deep trench capacitors are arranged in a matrix in the substrate.  
           [0017]    The present invention provides an open bitline DRAM with zigzag wordlines, wherein each DRAM cell is as mentioned above. The deep trench capacitors belonging to different rows are arranged with a shift.  
           [0018]    The present invention provides a folder bitline DRAM, wherein each DRAM cell is as mentioned above.  
           [0019]    The present invention provides a folder bitline DRAM with borderless bitline contact window, wherein each DRAM cell is as mentioned above. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:  
         [0021]    [0021]FIG. 1 is a cross-sectional diagram of a DRAM with a vertical transistor and a deep trench capacitor in accordance with first and second embodiments of the present invention;  
         [0022]    [0022]FIG. 2 is a layout diagram of an open bitline DRAM in accordance with the first embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1;  
         [0023]    [0023]FIG. 3 is a layout diagram of another open bitline DRAM in accordance with the second embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1;  
         [0024]    [0024]FIGS. 4 and 5 are cross-sectional diagrams of a DRAM with a vertical transistor and a deep trench capacitor in accordance with a third embodiment of the present invention;  
         [0025]    [0025]FIG. 6 is a layout diagram of a folder bitline DRAM in accordance with the third embodiment of the present invention, wherein the cross-sectional view of the cutting line IV-IV is showed in FIG. 4, and the cross-sectional view of the cutting line V-V is showed in FIG. 5;  
         [0026]    [0026]FIG. 7 is a cross-sectional diagram of a DRAM with a vertical transistor, a deep trench capacitor and a borderless bitline contact window in accordance with a fourth embodiment of the present invention;  
         [0027]    [0027]FIG. 8 is a layout diagram of a folder bitline DRAM with a borderless bitline contact window in accordance with the fourth embodiment of the present invention, wherein the cross-sectional view of the cutting line VII-VII is showed in FIG. 7;  
         [0028]    [0028]FIG. 9 is a layout diagram of a conventional and most used folder bitline DRAM; and  
         [0029]    [0029]FIG. 10 is a cross-sectional view of the memory cell in FIG. 9. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0030]    Detailed descriptions of DRAMs with vertical transistors and deep trench capacitors are given hereafter, by the accompanying four embodiments. The four embodiments include DRAM cell arrays with an open bitline and a folded bitline, a folder bitline DRAM cell array, and a folder bitline DRAM cell array with borderless bitline contact window.  
         [0031]    First Embodiment: a DRAM Cell Array with an Open Bitline  
         [0032]    [0032]FIG. 1 is a cross-sectional diagram of a DRAM with a vertical transistor and a deep trench capacitor of the present invention. FIG. 2 is a layout diagram of an open bitline DRAM in accordance with the first embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1.  
         [0033]    The deep trench capacitors  102  arranged in a matrix are formed in the substrate  100 . Each of the deep trench capacitors  102  comprises an upper electrode  102   a , an insulating film  102   b  and a storage electrode  102   c . A vertical transistor  104  comprising a gate  104   a , a gate insulating layer  104   b , a source  104   c  and a common drain  104   d  is disposed over each deep trench capacitor  102 . The gate  104   a  comprises an upper portion, which is not embedded in the substrate  100 , and a lower portion, which is embedded in the substrate  100 . The gate-insulating layer  104   b  is disposed on the sidewall of the lower portion of the gate  104   a . A vertical region between the source  104   c  and the common drain  104   d  is a channel region  109 .  
         [0034]    An insulating layer  108  and an ion-doped layer  106  are disposed between the gate  104   a  and the upper electrode  102   a  of the capacitor  102 . The source  104   c  is disposed on the sidewall of the ion-doped layer  106 . A shallow trench isolation  110  is disposed at least on another sidewall of the ion doped layer  106 . The insulating layer  108  is disposed between the gate  104   a  and the ion doped layer  106 , so as to isolate the gate  104   a  and the ion doped layer  106  with each other.  
         [0035]    Wordlines  118   a ,  118   b ,  118   c  and  118   d  are also functioned as gates  104   a  of the transistors  104 . Moreover, two adjacent wordlines  118   a  and  118   b , or  118   c  and  118   d  share a common drain  104   d  in an active region  112 . The region outside the active region  112  is the shallow trench isolation  110 . The bitlines  6   116   a  and  116   b  perpendicular to the wordline  118   a ,  118   b ,  118   c  and  118   d  are connected with the common drains  104   d  through contact windows  114  in different rows respectively.  
         [0036]    Second Embodiment: a DRAM Cell Array with a Folded Bitline  
         [0037]    [0037]FIG. 3 is a layout diagram of an open bitline DRAM in accordance with the second embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is as showed in FIG. 1.  
         [0038]    The deep trench capacitors  102  substantially corresponding to the adjacent bitlines  116   a  and  116   b  are arranged with a shift. That is, the deep trench capacitor  102  corresponding to the bitline  116   b  is opposite to the common drain  104   d  corresponding to the bitline  116   a . Under the above-mentioned layout, the isolation between the deep trench capacitor  102  corresponding to the bitline  116   a  and the deep trench capacitor  102  corresponding to the bitline  116   b  are enhanced. Moreover, the wordlines  118   a ,  118   b ,  118   c  and  118   d  run zigzag and are parallel with each other.  
         [0039]    Third Embodiment: a Folder Bitline DRAM Cell Array  
         [0040]    [0040]FIGS. 4 and 5 are cross-sectional diagrams of a DRAM with a vertical transistor and a deep trench capacitor. FIG. 6 is a layout diagram of a folder bitline DRAM in accordance with the third embodiment of the present invention, wherein the cross-sectional view of the cutting line IV-IV is shown in FIG. 4, and the cross-sectional view of the cutting line V-V is shown in FIG. 5.  
         [0041]    The structures of a deep trench capacitor  402  and a vertical transistor  404  are the same as the first and second embodiments substantially. The deep trench capacitor  402  comprises an upper electrode  402   a , an insulating film  402   b , and a storage electrode  402   c . A vertical transistor  404  comprising a gate  404   a , a gate insulating layer  404   b , a source  404   c  and a common drain  404   d  is disposed over each deep trench capacitor  402 . The gate-insulating layer  404   b  is disposed on a sidewall of the lower portion of the gate  404   a . A vertical region between the source  404   c  and the common drain  404   d  is a channel region  409 .  
         [0042]    An insulating layer  408  and an ion-doped layer  406  are disposed between the gate  404   a  and the upper electrode  402   a  of the capacitor  402 . The source  404   c  is disposed on the sidewall of the ion-doped layer  406 . A shallow trench isolation  410  is disposed at least on another sidewall of the ion doped layer  406 . The insulating layer  408  is disposed between the gate  404   a  and the ion doped layer  406  so as to isolate the gate  404   a  and the ion doped layer  406  with each other.  
         [0043]    In this embodiment, each active region  412 , such as corresponding to the bitline  416   a , comprises two deep trench capacitors  402 , two wordlines  418   a  and  418   d  corresponding to the two deep trench capacitors  402 , and two passing wordlines  418   b  and  418   c  disposed between the two wordlines  418   a  and  418   d . The wordlines  418   a  and  418   d  corresponding to the active region  412  below the bitline  416   a  are functioned as gates  404   a  of the transistors  404 . The deep trench capacitors  402  are under the gates  404   a . The region outside the active region  412  is the shallow trench isolation  410 .  
         [0044]    Furthermore, contact windows  414  are disposed between the gates  404   a  and the passing wordlines  418   b  and  418   c  and connected with the bitline  416 . The bitline  416  is substantially parallel with the active region  412  and perpendicular with the wordlines  418   a  and  418   d  and the passing wordlines  418   b  and  418   c.    
         [0045]    Fourth Embodiment: a Folder Bitline DRAM Cell Array with Borderless Bitline Contact Window  
         [0046]    [0046]FIG. 8 is a layout diagram of a folder bitline DRAM with a borderless bitline contact window in accordance with the fourth embodiment of the present invention, and the cross-sectional view of the cutting line VII-VII is shown in FIG. 7.  
         [0047]    The deep trench capacitors  702  arranged in rows and columns are formed in the substrate  700 . The deep trench capacitors  702  belonging to different rows are arranged with a shift. Each of the deep trench capacitors  702  comprises an upper electrode  702   a , an insulating film  702   b  and a storage electrode  702   c . A vertical transistor  704  comprising a gate  704   a , a gate insulating layer  704   b , a source  704   c  and a common drain  704   d  is disposed over each deep trench capacitor  702 . The gate-insulating layer  704   b  is disposed on a sidewall of the lower portion of the gate  704   a . A vertical region between the source  704   c  and the common drain  704   d  is a channel region  709 .  
         [0048]    An insulating layer  708  and an ion-doped layer  706  are disposed between the gate  704   a  and the upper electrode  702   a  of the capacitor  702 . The source  704   c  is disposed on the sidewall of the ion-doped layer  706 . A shallow trench isolation  710  is disposed on at least one other sidewall of the ion doped layer  706 . The insulating layer  708  is disposed between the gate  704   a  and the ion doped layer  706 , so as to isolate the gate  704   a  and the ion doped layer  706  with each other.  
         [0049]    The gate  704   a  and the passing wordline are disposed over each deep trench capacitor  702 . A part of the shallow trench isolation  710  is expanded to cover a part of the deep trench capacitor  702 , and the passing wordline is disposed on the part of the shallow trench isolation  710 .  
         [0050]    In this embodiment, each active region  712 , such as corresponding to the bitline  716   b  and the wordlines  718   a ″ and  718   b ′, comprises two deep trench capacitor  702 , two wordlines  718   a ″ and  718   b ′ corresponding to the two deep trench capacitors  702 , and a common drain  704   d  between the wordlines  718   a ″ and  718   b ′. Two passing wordlines  718   a ′ and  718   b ″ are disposed outside the two wordlines  718   a ″ and  718   b ′. The wordlines  718   a ″ and  718   b ′ corresponding to the active region  712  below the bitline  716   b  are functioned as gates  704   a  of the transistors  704 . The region outside the active region  712  is a shallow trench isolation  710 .  
         [0051]    Furthermore, the bitlines  716   a ,  716   b ,  716   c  and  716   d  are connected with the common drain  704   d  through contact windows  714 . The bitlines  716  are perpendicular to the wordlines (or passing wordlines)  718   a ′,  718   a ″,  718   b ′,  718   b ″,  718   c ′,  718   c ″,  718   d ′ and  718   d ″. Because the surface of the wordlines (or passing wordlines)  718   a ′,  718   a ″,  718   b ′,  718   b ″,  718   c ′,  718   c ′,  718   d ′ and  718   d ″ are covered by the insulating layer  720 , the contact window  714  cannot meet with the common drain  704   d , even if misalignment happens in the photolithography process. Therefore, no short circuit happens.  
         [0052]    Finally, while the invention has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.