Abstract:
MB810 encoder and/or decoder, dual mode encoder and/or decoder, and a method for generating MB810 codes are provided. The method for generating MB810 codes comprises: forming 12 state points in the form of a 4×3 matrix on a state transition map formed with binary unit digital sum variation &amp; alternate sum variation (BUDA) to generate a 10-bit code from 8-bit data; outputting a 10-bit code from a predetermined state point forming the matrix; selecting codes forming a complementary pair from a set of codes capable of arriving at state points forming the matrix; selecting codes forming the 12 state points by supplementing state points lacked in the codes forming a complementary pair; selecting control codes including IDLE code from the codes forming the 12 state points; and removing codes generating the IDLE code by a bit string between neighboring codes among the codes forming the 12 state points.

Description:
[0001]     This application claims priority from Korean Patent Application No.2003-48426, filed on Jul. 15, 2003, the contents of which are incorporated herein by reference in their entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an MB810 encoder and/or decoder, a dual mode encoder and/or decoder, and an MB810 code generation method, and more particularly, to an MB810 encoder and/or decoder, a dual mode encoder and/or decoder, and an MB810 code generation method using control codes satisfying conditions of a DC-free code and spectrum 0 at Nyquist frequency.  
         [0004]     2. Description of the Related Art  
         [0005]     When data is to be encoded into codes and transmitted, it should be first guaranteed due to the characteristic of transmission lines that the condition of a DC-free code is satisfied. A lot of research projects have been focused on generation methods of this DC-free code. Also, it has been known that in order to transmit data at a high speed, a smaller transmission bandwidth that is required to encoded codes is more advantageous than a larger bandwidth and theoretically the minimum bandwidth desired to be transmitted should have spectral null at the Nyquist frequency.  
         [0006]     In an article, “A condition for stable minimum-bandwidth line codes”, published in IEEE Trans. on Comm., Vol. COM-33, No. 2, pp152-157, February 1985, the rationale of the condition that in addition to the DC-free condition, the spectrum should also be 0 at the Nyquist frequency is theoretically analyzed. Also, in an article, “DC-free and Nyquist-free error correcting convolutional codes”, published in Electronics Letters, Vol. 32, No. 24, pp 2196-2198, November, 1996, a (4, 3) code satisfying the conditions described above is suggested.  
         [0007]     Meanwhile, U.S. Pat. No. 4,486,739 discloses a method in which a 5B/6B coder and a 3B/4B coder are combined to generate an 8B/10B coder to limit a run length, and based on 8-bit data, 10-bit code and control codes (align, skip, comma, etc.) required for transmission of the generated code are generated. However, though the codes generated by this method are DC-free codes, those are not minimum bandwidth codes.  
         [0008]     U.S. Pat. No. 5,663,724 discloses a method in which by a 16B/20B encoder implemented by placing two 8B/10B encoders in parallel in order to apply the method of U.S. Pat. No. 4,486,739 to fiber channels, an upper 3B/4B encoder controls the disparity of a lower 5B/6B encoder and a lower 3B/4B encoder controls the disparity of an upper 5B/6B encoder of the next word. However, since the encoder suggested in the U.S. Pat. No. 5,663,724 is also an 8B/10B encoder in essence, the codes generated by the encoder are DC-free codes but not minimum bandwidth codes.  
         [0009]     Also, U.S. Pat. No. 6,501,396 discloses a method in which in order to solve the shortcoming of the U.S. Pat. No. 5,663,724 that the number of encoders connected in parallel is limited to 2, a block to control disparity is separately implemented to control disparity in each channel. Though this method solves the problem of the limited number of channels capable of transmitting data in parallel, the codes generated by the encoder are also DC-free codes but not minimum bandwidth codes.  
         [0010]     U.S. Pat. No. 6,425,107 discloses a method in which in order to more simply implement an encoder in encoding 8 bits into 10 bits, all possible balanced (equal number of logic 0 and logic 1 bits) 10-bit codes are selected to obtain 256 entries, and if there are less than 256 entries, imbalanced 10-bit codes which are imbalanced by 2 bits or less are used. However, the codes generated by this method are also DC-free but not minimum bandwidth codes.  
         [0011]     Also, U.S. Pat. No. 6,441,756 discloses an 8B/14B code formed with a control code group separate from a data conversion code group in order to increase the probability of DC suppression. However, the codes suggested here are also DC-free codes but not minimum bandwidth codes.  
         [0012]     Meanwhile, U.S. Pat. No. 6,362,757 discloses MB810 line code generation method and structure. The method disclosed by the U.S. Pat. No. 6,362,757 can generate minimum bandwidth codes capable of generating spectral null even at the Nyquist frequency, as well as DC-free codes, but has some problems when practically applied. First, there is a code whose run length (that is, the number of contiguous 0&#39;s or 1&#39;s) is 7 in the code itself. Also, there is a danger that run length exceeds 7 due to neighboring codes when 10-bit codes are transmitted. At this time, the worst case that the run length is 9 may occur. Accordingly, in the MB810 line code generation method and structure disclosed in the U.S. Pat. No. 6,362,757, it is difficult to utilize the clock extraction circuit used in the conventional 8B/10B codes. Also, since a code (comma code) for distinguishing frames used in the conventional 8B/10B encoder is included in a data code and there is no specific mention on the code (comma code) for distinguishing frames, it is difficult to use this method in a dual mode operation in which an 8B/10B encoder and an MB810 encoder are embedded and a user selects one encoder.  
         [0013]     Also, Korean Patent Laying-Open No. 2003-0020519 discloses a method to enable dual mode use of the conventional 8B/10B coder and MB810 coder in order to complement the method of U.S. Pat. No. 6,362,757. This method uses codes /A/, /K/, /R/, as IDLE code group, in order to determine whether a received code is an 8B/10B code or an MB810 code. However, in order to use this method, the structures of 8B/10B encoders and decoders widely used at present should be changed.  
       SUMMARY OF THE INVENTION  
       [0014]     The present invention provides an MB810 encoder and/or decoder capable of utilizing a clock extraction circuit used in the prior art 8B/10B code method by reducing a run length to 6 or less, a dual mode encoder and/or decoder capable of selectively using MB810 encoder and/or decoder without changing the structure of the prior art 8B/10B encoder and/or decoder, and an MB810 code generation method having a reduced transmission bandwidth compared to the prior art 8B/10B codes.  
         [0015]     According to an aspect of the present invention, there is provided an MB810 code generation method comprising: forming 12 state points in the form of a 4×3 matrix on a state transition map formed with binary unit digital sum variation &amp; alternate sum variation (BUDA) to generate a 10-bit code from 8-bit data; outputting a 10-bit code from a predetermined state point forming the matrix; selecting codes forming a complementary pair from a set of codes capable of arriving at state points forming the matrix; selecting codes forming the 12 state points by supplementing state points lacked in the codes forming a complementary pair; selecting control codes including IDLE code from the codes forming the 12 state points; and removing codes generating the IDLE code by a bit string between neighboring codes among the codes forming the 12 state points.  
         [0016]     According to another aspect of the present invention, there is provided an MB810 encoder comprising: a table storage unit which stores code tables having data codes written therein, the data codes generated by forming 12 state points in the form of a 4×3 matrix on a state transition map formed with binary unit digital sum variation &amp; alternate sum variation (BUDA) to generate a 10-bit code from 8-bit data, and outputting a 10-bit code from a predetermined state point forming the matrix, and then, supplementing second codes having state points lacked in first codes forming complementary pairs selected from a set of 10-bit codes capable of arriving at state points forming the matrix, and then, selecting control codes including IDLE code among the first and second codes, and removing codes generating the IDLE code by a bit string between neighboring codes among the second codes, and codes that are selected as the control codes; a first buffer unit which stores an 8-bit control code input from the outside; a second buffer unit which stores an 8-bit control code input from the outside; and a state transition unit which, based on a current state and the contents of the 8-bit data code input from the first buffer unit, reads out a 10-bit data code from a code table stored in the table storage unit and outputs the code, and, based on a current state and the contents of the 8-bit control code input from the second buffer unit, reads out a 10-bit control code from a code table stored in the table storage unit, and based on predetermined state transition information, is transited to one of 12 state points on the state transition map.  
         [0017]     According to still another aspect of the present invention, there is provided an MB810 decoder comprising: a table storage unit which stores code tables having data codes written therein, the data codes generated by forming 12 state points in the form of a 4×3 matrix on a state transition map formed with binary unit digital sum variation &amp; alternate sum variation (BUDA) to generate a 10-bit code from 8-bit data, and outputting a 10-bit code from a predetermined state point forming the matrix, and then, supplementing second codes having state points lacked in first codes forming complementary pairs selected from a set of 10-bit codes capable of arriving at state points forming the matrix, and then, selecting control codes including IDLE code among the first and second codes, and removing codes generating the IDLE code by a bit string between neighboring codes among the second codes, and codes that are selected as the control codes; a decoding unit which based on the contents of a 10-bit code input from the outside, reads out an 8-bit data code or an 8-bit control code from a code table stored in the table storage unit; a first buffer unit which stores the 8-bit data code input from the decoding unit and then outputs the code to the outside; and a second buffer unit which stores the 8-bit control code input from the decoding unit and then outputs the code to the outside.  
         [0018]     According to yet still another aspect of the present invention, there is provided a dual mode encoder comprising: an MB810 encoder; an 8B/10B encoder; a determination unit which determines an encoder to be used as an operation encoder between the MB810 encoder and the 8B/10B encoder; a first selection unit which provides an 8-bit code input from the outside to the encoder determined as the operation encoder; a second selection unit which receives a 10-bit code corresponding to the 8-bit code from the encoder determined as the operation encoder, and outputs the code; a serial conversion unit which converts the 10-bit code input from the second selection unit into a 10-bit serial code; a code clock generation unit which receives a data clock from the outside, generates a code clock, and provides the clock signal to the serial conversion unit; a first low pass filter which when the MB810 encoder is determined as the operation encoder, removes a predetermined frequency bandwidth from a 10-bit serial code input from the serial conversion unit; a first amplifier which amplifies a 10-bit serial code input from the first low pass filter and outputs the code; a second low pass filter which when the 8B/10B encoder is determined as the operation encoder, removes a predetermined frequency bandwidth from a 10-bit serial code input from the serial conversion unit; a second amplifier which amplifies a 10-bit serial code input from the second low pass filter and outputs the code; and a switch unit which according to the encoder determined as the operation encoder, provides a 10-bit serial code output from the serial conversion unit selectively to the first and second low pass filters, and selectively outputs a 10-bit serial code output from the first and second amplifiers to the outside.  
         [0019]     According to a further aspect of the present invention, there is provided a dual mode decoder comprising: an MB810 decoder; an 8B/10B decoder; a mode detection unit which detects a decoder to be used as an operation decoder between the MB810 decoder and the 8B/10B decoder; a first low pass filter which when the MB810 decoder is determined as the operation decoder, removes a predetermined frequency bandwidth from a 10-bit code input from the outside; a second low pass filter which when the 8B/10B decoder is determined as the operation decoder, removes a predetermined frequency bandwidth from a 10-bit code input from the outside; an IDLE code detection unit which detects IDLE code from the 10-bit code and transfers to the mode detection unit; a first switch unit which according to the decoder determined as the operation decoder, selectively outputs the 10-bit code input from the first low pass filter and the second low pass filter; a parallel conversion unit which converts the 10-bit code input from the first switch into a parallel code and outputs a 10-bit parallel code; a first selection unit which provides the 10-bit parallel code to the decoder determined as the operation decoder between the MB810 decoder and the 8B/10B decoder; and a second selection unit which selectively outputs an 8-bit code corresponding to the 10-bit parallel code input from the decoder determined as the operation decoder.  
         [0020]     According to the apparatuses and method, the transmission bandwidth is reduced compared to the prior art 8B/10B codes such that long distance transmission is enabled, and without changing the prior art 8B/10B coding method, the codes are applied together with MB810 codes such that the dual mode operation can be performed in which a user can select a desired line code. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]     The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:  
         [0022]      FIG. 1  is a state transition map showing a binary unit digital sum variation &amp; alternate sum variation (BUDA) stack for generating MB810 codes according to the present invention and 12 state points;  
         [0023]      FIGS. 2   a  through  2   f  are diagrams of code tables in which codes used in an MB810 encoder according to the present invention are recorded;  
         [0024]      FIG. 3  is a diagram of a code table in which codes that can be internally used in the MB810 according to the present invention are recorded;  
         [0025]      FIGS. 4   a  through  4   e  are diagrams of code tables in which codes used in an MB810 decoder according to the present invention are recorded;  
         [0026]      FIGS. 5 through 7  are diagrams of tables in which state transition information related to operations of MB810 encoder when encoding 8-bit data information according to the present invention is recorded;  
         [0027]      FIGS. 8 through 10  are diagrams of tables in which state transition information related to operations of the MB810 encoder when encoding 8-bit control information according to the present invention is recorded;  
         [0028]      FIG. 11  is a diagram showing the power spectrum of an 8B/10B line code;  
         [0029]      FIG. 12  is a block diagram of the structure of an MB810 encoder according to the present invention constructed by using codes generated by an MB810 code generation method according to the present invention;  
         [0030]      FIG. 13  is a block diagram of the structure of an MB810 decoder according to the present invention constructed by using codes generated by an MB810 code generation method according to the present invention;  
         [0031]      FIG. 14  is a block diagram showing the structure of a dual mode encoder according to the present invention;  
         [0032]      FIG. 15  is a block diagram showing the structure of a dual mode decoder according to the present invention; and  
         [0033]      FIGS. 16   a  and  16   b  are flowcharts of the steps performed by a dual mode processing method according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0034]     Hereinafter, the present invention will be described in detail by explaining preferred embodiments of an improved MB810 line code apparatus including control codes and an MB810 code generation method according to the present invention with reference to the attached drawings.  
         [0035]     Referring to  FIG. 1 , s 0 , . . . , s 11  denote respective state points of an MB810 encoder and a group of state points are set in the form of a 4×3 matrix. Arrows shown in  FIG. 1  indicate paths through which an MB810 encoder can change according to the output of a 10-bit code converted corresponding to data input to the encoder when the MB810 encoder is in each state point. If the sign of output bits is 0, the state moves to the left by one arrow, and if the sign of output bits is 1, the state moves to the right by one arrow. Since the number of output bits is 10, the state moves along 10 arrows according to the sign of the code. A method for selecting a code on this state transition map will now be explained.  
         [0036]     First, after a 10-bit code is output from an arbitrary state point among s 0 , . . . , s 11 , only those codes that can reach any one state point of s 0 , . . . , s 11  are useful codes having minimum bandwidths and therefore those codes can be set as valid codes. The number of valid codes among 1024 codes is 890.  
         [0037]     Next, in selecting IDLE code, in order to easily distinguish from 8B/10B codes when the encoder operates in dual mode, IEEE 802.3 standard K28.7 (0011111000 and 1100000111) which embeds a comma among those codes that are not used by 8B/10B codes is selected, and removed from candidate lists for data codes and control codes.  
         [0038]     Then, codes whose run length exceeds 6 (for example, in the case of 1011011110, the run length is 4) are removed among the output codes. In case when the run length exceeds 6 by a neighboring code, the code having a longer run length is removed. That is, if the preceding code is 1011001111 and the succeeding code is 1110010111, 1011001111 is removed from the candidate list.  
         [0039]     After combining all the remaining codes into complementary pairs, code combinations according to state transitions of these pairs are generated continuously three times. Then, among the generated code combinations, those code combinations that cause −K28.7 to occur immediately after +K28.7 or +K28.7 to occur immediately after −K28.7 are collected and code pairs providing such code combinations are removed from the candidate list.  
         [0040]     Next, by using the characteristic that an encoder necessarily returns to a starting state point according to state transitions, complementary code pairs that make the highest number of complementary code pairs as possible are selected when these code pairs are selected.  
         [0041]     Next, codes that can travel all state points only with one complementary code pair (that is, only with two codes) among the selected complementary code pairs are selected. All 161 pairs are selected as these codes.  
         [0042]     Next, among the selected complementary code pairs, K28.0, K28.3, K28.4, K27.7 and K20.7 codes that are 8B/10B control codes defined in IEEE 802.3ae are selected as MB810 control codes with the same function as the control function of 8B/10B codes. Among the existing 8B/10B control codes, only with one code pair, K29.7 code is short of the number of states such that it is difficult to make a code combination having a minimum bandwidth when K29.7 code is used as a control code having the same function even in the MB810 code. Accordingly, another code pair capable of traveling lacked state points should be added or the code should be replaced by a code capable of traveling all state points only with one code pair. For simplification of control function operation, one code pair, 1100111000 and 001100011, is used as K29.7 of MB810 code.  
         [0043]     Next, code combinations that can travel all state points with two pairs (that is, four codes) are selected. The number of combinations in which thus selected two pairs are assigned to data is 73 (that is, 73×4=292 codes).  
         [0044]     Next, by combining 24 codes having only state points of s 0 , s 1  and s 2  with 24 codes having state points of s 3 , s 4 , s 5 , s 6 , s 7 , s 8 , s 9 , s 10 , and s 11  (that is, 9 state transition points) among the 161 pairs having state transitions selected above, 24 code pairs are selected.  
         [0045]     Also, by combining 24 codes having only state points of s 9 , s 10  and s 11  with 24 codes having state points of s 0 , s 1 , s 2 , s 3 , s 4 , s 5 , s 6 , s 7 , and s 8  (that is, 9 state transition points) among the 161 pairs having state transitions selected above, 24 code pairs are selected.  
         [0046]     Finally, among codes having 9 state points and not included in the 161 pairs selected above, complementary pairs whose run length is 4 and whose bit shapes are 1111XXXXXX and 0000XXXXXX (X is 0 or 1) are combined into two pairs each. That is, it is made to be possible to output a different code according to the shape of final bits of a code output immediately before. Thus selected two code pairs are two kinds and include 1111001000, 0000110111, 000011101 and 1111000100, and 1111000010, 000011111101, 0000111110, and 1111000001.  
         [0047]     Since thus the number of selected code pairs is 260, 256 pairs are assigned to data and the remaining four pairs can be used for special purposes internally in the MB810 coder, such as state synchronization of physical coding sublayer (PCS: physical coding lower layer defined in IEEE 802.3 standard), transmission of state information from an encoder to a decoder during IDLE cycle, and transmission of state information from an encoder to a decoder before data frame start.  
         [0048]     MB810 codes generated by the above method are shown in  FIGS. 2   a  through  3   e.  Codes shown in  FIGS. 2   a  through  2   f  are those codes that are used by an MB810 encoder and forming 7 groups. Codes shown in  FIG. 3  are those codes that can be internally used in an MB810 encoder and state information that can be output for each data item is shown together. Codes shown in  FIGS. 4   a  through  4   e  are those codes that are used by an MB810 decoder. Since the decoder does not need state information when decoding data, state information is not written in  FIGS. 4   a  through  4   e.    
         [0049]     Meanwhile,  FIGS. 5 through 10  are tables in which codes and/or state information related to encoding operations of an MB810 encoder are written.  
         [0050]     First, IDLE codes (that is, +K28.7/−K28.7) shown in  FIG. 8  are those code that are always transmitted when data is not transmitted. In  FIG. 8 , s 0 , s 1 , . . . , s 11  indicate states of an MB810 encoder, and in spaces below s 0 , s 1 , . . . , s 11  columns, state information to which the encoder is transited after a corresponding code is transmitted is written. In case where state information is not written, a corresponding code is not transmitted and the code in the row of the space where state information is located is output. Accordingly, if the state when IDLE code is desired to be transmitted is s 0 , the MB810 encoder outputs 1100000111 (that is, +K28.7) and is transited to s 3  state. Also, if IDLE code is continuously transmitted, 0011111000 (that is, −K28.7) is output and the encoder is transited to s 0  state.  
         [0051]     If the state when IDLE code is desired to be transmitted is s 7 , the MB810 encoder outputs 1100000111 (that is, +K28.7) and is transited to s 10  state. Also, if IDLE code is continuously transmitted, 0011111000 (that is, −K28.7) is output and the encoder is transited to s 7  state. The codes in the second table of  FIG. 8  are those codes that are used when skip control information code is transmitted. The operation of the MB810 encoder is the same as when IDLE code is output. The codes in the third table of  FIG. 8  are those codes that are used when align control information code is output. When the state of the MB810 encoder is s 3 , 1100001011 (that is, +K28.3) as shown in  FIG. 8  is output and the encoder is transited to s 4  state. Also, when align control information code is continuously transmitted, 1100001011 (that is, +K28.3) is transmitted and the encoder is transited to s 5  state. When align control information code is continuously transmitted further, 0011110100 (that is, −K28.3) is output and the encoder is transited to s 4  state.  
         [0052]     Codes written in the first table of  FIG. 9  are fault control information codes, codes written in the second table are frame start information codes, codes written in the third table are frame end information codes, and codes written in the fourth table are error control information codes. When the codes shown in  FIG. 9  are output, the MB810 encoder operates in the same manner as when IDLE code is output.  
         [0053]     Next, state transition information related to operations of the MB810 encoder when encoding 8-bit data information is written in tables shown in  FIGS. 5 through 7 .  
         [0054]     In the first table shown in  FIG. 5 , a method used to encode data items of data group  0 ˜ 57  shown in  FIGS. 2   a  and  2   b  is shown. For example, when the MB810 encoder is in s 4  state, a code in group A_L row in the first table shown in  FIG. 5  is output and the encoder is transited to s 1  state. If a data item of data group  0 ˜ 57  is continuously encoded, a code in group A_R row in the first table shown in  FIG. 5  is output and the encoder is transited to s 4  state.  
         [0055]     In the second table shown in  FIG. 5 , a method used to encode data items of data group  58 ˜ 136  shown in  FIGS. 2   b  and  2   c  is shown. For example, when the MB810 encoder is in s 3  state, a code in group A_L row of the second table shown in  FIG. 5  is output and the encoder is transited to s 4  state. If a data item of data group  58 ˜ 136  is continuously encoded, a code in group A_L row of the second table of  FIG. 5  is output and the encoder is transited to s 5  state. If a data item of data group  58 ˜ 136  is continuously encoded further, a code in group A_R row of the second table of  FIG. 5  is output and the encoder is transited to s 4  state.  
         [0056]     In the third table shown in  FIG. 5 , a method used to encode data items of data group  137 ˜ 160  shown in  FIGS. 2   c  and  2   d  is shown. For example, when the MB810 encoder is in s 3  state, a code in group A_L row of the third table shown in  FIG. 5  is output and the encoder is transited to s 0  state. If a data item of data group  137 ˜ 160  is continuously encoded, a code in group A_R row of the third table shown in  FIG. 5  is output and the encoder is transited to s 9  state. If a data item of data group  137 ˜ 160  is continuously encoded further, a code in group A_L row of the third table shown in  FIG. 5  is output and the encoder is transited to s 6  state. If a data item of data group  137 ˜ 160  is continuously encoded still further, a code in group A_L row of the third table shown in  FIG. 5  is output and the encoder is transited to s 3  state.  
         [0057]     In the first table shown in  FIG. 6 , a method used to encode data items of data group  161 ˜ 185  shown in  FIG. 2   d  is shown. For example, when the MB810 encoder is in s 10  state, a code in group A_L row of the first table shown in  FIG. 6  is output and the encoder is transited to s 1  state. If a data item of data group  161 ˜ 185  is continuously encoded, a code in group A_R row of the first table shown in  FIG. 6  is output and the encoder is transited to s 4  state. If a data item of data group  161 ˜ 185  is continuously encoded further, a code in group A_R row of the first table of  FIG. 6  is output and the encoder is transited to s 7  state. If a data item of data group  161 ˜ 185  is continuously encoded still further, a code in group A_R row of the first table shown in  FIG. 6  is output and the encoder is transited to s 10  state.  
         [0058]     In the second and third tables shown in  FIG. 6 , a method used to encode data items of data group  186 ˜ 215  shown in  FIGS. 2   d  and  2   e  is shown. For example, when the MB810 encoder is in s 10  state, a code in group A_L row in the second table shown in  FIG. 6  is output and the encoder is transited to s 5  state. If a data item of data group  186 ˜ 216  is continuously encoded, a code in group B_R row of the third table shown in  FIG. 6  is output and the encoder is transited to s 0  state. If a data item of data group  186 ˜ 216  is continuously encoded further, a code in group B_L row of the third table shown in  FIG. 6  is output and the encoder is transited to s 5  state. If a data item of data group  186 ˜ 216  is continuously encoded still further, a code in group B_R row of the third table shown in  FIG. 6  is output and the encoder is transited to s 0  state.  
         [0059]     In the first and second tables shown in  FIG. 7 , a method used to encode data items of data group  216 ˜ 244  shown in  FIG. 2   e  is shown. For example, when the MB810 encoder is in s 1  state, a code in group A_L row in the first table shown in  FIG. 7  is output and the encoder is transited to s 8  state. If a data items of data group  216 ˜ 244  is continuously encoded, a code in group B_R row of the second table shown in  FIG. 7  is output and the encoder is transited to s 9  state. If a data items of data group  216 ˜ 244  is continuously encoded further, a code in group B_L row of the first table shown in  FIG. 7  is output and the encoder is transited to s 8  state.  
         [0060]     In the first and second tables shown in  FIG. 7 , a method used to encode data items of data group  216 ˜ 244  shown in  FIG. 2   e  is shown. For example, when the MB810 encoder is in s 1  state, a code in group A_L row in the first table shown in  FIG. 7  is output and the encoder is transited to s 8  state. If a data item of data group  216 ˜ 244  is continuously encoded, a code in group B_R row of the second table shown in  FIG. 7  is output and the encoder is transited to s 9  state. If a data item of data group  216 ˜ 244  is continuously encoded further, a code in group B_L row of the first table shown in  FIG. 7  is output and the encoder is transited to s 8  state.  
         [0061]     In the third and fourth tables shown in  FIG. 7 , a method used to encode data items of data group  245 ˜ 255  of the data group shown in  FIGS. 2   e  and  2   f  is shown. For example, when the MB810 encoder is in s 0  state, a code in group B_L row in the fourth table shown in  FIG. 7  is output and the encoder is transited to s 7  state. If a data item of data group  245 ˜ 255  is continuously encoded, a code in group A_L row of the third table shown in  FIG. 7  is output and the encoder is transited to s 2  state. If a data item of data group  245 ˜ 255  is continuously encoded further, a code in group A_R row of the third table shown in  FIG. 7  is output and the encoder is transited to s 7  state.  
         [0062]      FIG. 10  shows a state transition method for surplus codes that can be used internally for special purposes such as transition state information transmission, PCS synchronization or error indication. The operation method of codes belonging to the first and second tables shown in  FIG. 10  is the same as the operation method to encode data items of data group  245 ˜ 255  explained above referring to  FIG. 7 .  
         [0063]     Meanwhile, the operation method of codes belonging to the third and fourth tables shown in  FIG. 10  is basically the same as the operation method of the codes belonging to the first table shown in  FIG. 5 , but in selecting a code, a code beginning with a sign opposite that of the last bit of a code output immediately before is selected. For example, if the last bit output immediately before is 1 and the current state after finishing transmission of a corresponding code is s 3 , a code in group B_L row in the fourth table shown in  FIG. 10  is output and the encoder is transited to s 0  state. If the last bit output immediately before is 0 and the current state after finishing transmission of a corresponding code is s 3 , a code in group A_L row in the fourth table shown in  FIG. 10  is output and the encoder is transited to s 0  state.  
         [0064]     By using the characteristics of the codes selected as described above, a code error can be easily detected similarly to the 8B/10B code. That is, all control codes except IDLE code and align control code (that is, K28.3) have five 1&#39;s among 10 bits, and disparity (the degree that the number of 1&#39;s is not the same as the number of 0&#39;s in a code) is 0, and if identical codes are continuously transmitted, codes are always output in an alternate method (that is, outputting a complementary code). In addition, though disparity of K28.3 is 2, if identical codes are continuously transmitted, codes are always output in an alternate method in all the remaining state except s 0 , s 3 , s 8 , and s 11  states. Also, when codes of an identical group are continuously transmitted, data group  0 ˜ 57  operate the same as IDLE code and disparity is 0. Data group  59 ˜ 136  operate in the same manner as K28.3 and disparity is the same as that of K28.3. Data group  137 ˜ 184  do not operate in an alternate method but disparity is 0. Data group  185 ˜ 255  are combinations of codes whose disparities are 2 and 4, but when codes of an identical group (data group  185 ˜ 255  and the first and second code groups shown in  FIG. 10  are regarded as identical groups) are continuously output, states are transited always in the direction that disparity is reduced. Finally, though disparity of data group  245 ˜ 255  and the first and second code groups shown in  FIG. 10  is 2, when identical codes are continuously transmitted, codes are always output in an alternate method in all the remaining states except s 0 , s 3 , s 8 , and s 11  states. That is, except codes whose disparity is 0, those codes that continuously cause identical disparities are not transmitted twice or more. Accordingly, by using these characteristic, if an increasing or decreasing direction of disparity occurs twice or more, it is possible to determine an error.  
         [0065]     When the power spectra of MB810 line code generated by the method described above and the power spectra of the prior art 8B/10B line code are calculated according to a method disclosed in an article “Spectra of Block Coded Digital Signals” (IEEE Trans. on Comm., Vol., COM-22, No. 10, pp1555-1564, October, 1974), the power spectra of 8B/10B line code are DC-free, while the power spectra of MB810 line code are not only DC-free but also spectral null in the Nyquist frequency (that is, a normalized frequency=0.5) as shown in  FIG. 11 .  
         [0066]      FIG. 12  is a block diagram of the structure of an MB810 encoder according to the present invention constructed by using codes selected by the method described above.  
         [0067]     Referring to  FIG. 12 , the MB810 encoder according to the present invention comprises a control data buffer  310 , an 8-bit data buffer  320 , a state transition unit  330 , and a code table storage unit  340 . The code table storage unit  340  comprises table A_L block  341 , table A_R block  342 , table B_L block  343 , table B_R block  344 , a comma code block  345 , and a control code block  346  and these blocks can be combined and implemented as one block. Table A_L block  341 , table A_R block  342 , table B_L block  343 , table B_R block  344  are for data codes and the comma code block  345  and control code block  346  are for control codes. A selection signal is a signal provided from the outside and indicates whether or not the MB810 encoder  300  is used.  
         [0068]     Even though the internal state of the state transition unit  330  is an arbitrary state in an initial state of the MB810 encoder, it does not affect the operation of the MB810 encoder. However, for convenience, the internal state of the state transition unit  330  may be set to 0 when the encoder is initialized.  
         [0069]     Input data is 8-bit data and is input from the outside in parallel. Control data is an 8-bit signal for controlling the operational state of the MB810 encoder and is input from the outside in parallel. Examples of control data are shown in  FIG. 3  and  FIGS. 8 through 10  and control data includes IDLE signal, align control information, and so on.  
         [0070]     Control data input from the outside is stored in the control data buffer  310  and the control data buffer  310  outputs the stored control data to the state transition unit  330 . Meanwhile, the input data input from the outside is stored in the 8-bit data buffer  320  and the 8-bit data buffer  320  outputs the stored input data to the state transition unit  330 .  
         [0071]     At this time, a case where the input data and control data are input at the same does not take place. That is, when the input data is input, the control data is not input, and when the control data is input, the input data is not input.  
         [0072]     Accordingly, if the input data is input from the 8-bit data buffer  320 , the state transition unit  330  reads out a code recorded in table A_L block  341 , table A_R block  342 , table B_L block  343 , and table B_R block  344  according to the its own state information and the content of the input data, and outputs a 10-bit parallel code as an output code. Then, the state is transited as described above referring to  FIGS. 5 through 7 .  
         [0073]     Also, if the control data is input from the control data buffer  310 , the state transition unit  330  reads out a code recorded in the comma code block  345  and control code block  346  as shown in  FIGS. 8 through 10  according to its own state information and the content of the control data, and outputs a 10-bit parallel code as an output code. Then, the state is transited as described above referring to  FIGS. 8 through 10 .  
         [0074]      FIG. 13  is a block diagram of the structure of MB810 decoder according to the present invention.  
         [0075]     Referring to  FIG. 13 , the MB810 decoder  400  according to the present invention comprises a control data buffer  410 , an 8-bit data buffer  420 , a state processing unit  430 , a code table storage unit  440 , and a code decoding unit  450 . The code table storage unit  440  comprises table A_L block  441 , table A_R block  442 , table B_L block  443 , table B_R block  444 , a comma code block  445 , and a control code block  446 , and these blocks may be combined and implemented as one block. Table A_L block  441 , table A_R block  442 , table B_L block  443 , table B_R block  444  are for data codes and the comma code block  445  and control code block  446  are for control codes. A selection signal is a signal provided from the outside and indicates whether or not the MB810 decoder  400  is used. Data clock is a clock signal provided from the outside to operate the MB810 decoder  400 .  
         [0076]     If a 10-bit input code input from the outside in parallel is a data code, the code decoding unit  450  converts the input data code into 8-bit data information, referring to code tables stored in table A_L block  441 , table A_R block  442 , table B_L block  443 , table B_R block  444 , and transfers the converted 8-bit data to the 8-bit data buffer  420 .  FIGS. 3   a  through  3   e  show code tables stored in table A_L block  441 , table A_R block  442 , table B_L block  443 , table B_R block  444 . The 8-bit data buffer  420  outputs in parallel the 8-bit data input from the code decoding unit  450 .  
         [0077]     Also, if the 10-bit input code input in parallel from the outside is a control code, the code decoding unit  450  converts the input control code into an 8-bit control code, referring to code tables stored in the comma code block  445  and control code block  446 , and transfers the converted 8-bit control code to the control data buffer  410 . Code tables stored in the comma code block  445  and control code block  446  are shown in  FIGS. 8 through 10 . The control data buffer  410  outputs in parallel the 8-bit control code input from the code decoding unit  450 .  
         [0078]     Meanwhile, the code decoding unit  450  transfers two types of information to the state processing unit  430 . First, error determination information by the error detection unit  451  placed inside the code decoding unit  450  is transferred to the state processing unit  430 . Also, when a 10-bit code is input in parallel from the outside, if the input code is a code internally defined in the MB810 encoder/decoder, the code decoding unit  450  converts the input 10-bit code into 8-bit data information, referring to the ode table recorded in the control code block  446 , and transfers the converted 8-bit data information to the state processing unit  430 . The code table stored in the control code block  446  is shown in  FIG. 3 .  
         [0079]     The error detection unit  451  is an element placed inside the code decoding unit  450  checks whether or not the input 10-bit code is a code existing in the code table storage unit  440 , checks disparity of the input 10-bit code according to the method described above, counts the frequency of the increasing or decreasing directions of disparity, and if the increases or decreases are twice or more, determines that an error occurred in the input 10-bit code. That is, a code whose disparity is 0 does not cause a change to the previous disparity state, but if the previous disparity state is +1 (that is, a code in which the number of 1&#39;s is less than the number of 0&#39;s is once received) and the disparity of the currently input code is also +, the internal counter of the error detection unit  451  becomes +2. Meanwhile, if the previous disparity state is +1 and the disparity of the currently input code is −, the internal counter of the error detection unit  451  becomes 0. When the internal counter of the error detection unit  451  is +2, if the disparity of the currently input code is also +, the internal counter of the error detection unit becomes +3 such that the error detection unit  451  determines that an error occurred in the received code.  
         [0080]     Based on the error determination result input from the code decoding unit  450 , the state processing unit  430  outputs 8-bit diagnosis data in parallel. In addition, based on the 8-bit data code input from the code decoding unit  450 , the state processing unit  430  outputs 8-bit diagnosis data in parallel. Since the codes internally defined by this MB810 encoder/decoder are not essential in the operation of the MB810 encoder/decoder, those codes can be used selectively.  
         [0081]      FIG. 14  is a block diagram showing the structure of a dual mode encoder according to the present invention.  
         [0082]     Referring to  FIG. 14 , the dual mode encoder according to the present invention comprises a determination unit  510 , a first selection unit  520 , a clock generation unit  530 , an MB810 encoder  540 , an 8B/10B encoder  550 , a second selection unit  560 , a serial conversion unit  570 , a switch unit  575 , a first low pass filter  580 , a first amplifier  585 , a second low pass filter  590 , and a second amplifier  595 . The clock generation unit  530 , the 8B/10B encoder  540 , the serial conversion unit  570 , the first low pass filter  580 , and the first amplifier  585  are elements forming the prior art 8B/10B encoder.  
         [0083]     The determination unit  510  determines whether the dual mode encoder according to the present invention is to be used in MB810 encoder mode or 8B/10B encoder mode. The determination unit provides mode selection information to the first selection unit  520 , the MB810 encoder  540 , the 8B/10B encoder  550 , the second selection unit  560 , and the switch unit  575 . By input a mode selection command, a user can control the determination content of the determination unit  510 .  
         [0084]     If a data clock is provided, the clock generation unit  510  generates a code clock for a 10-bit code, and provides to the serial conversion unit  570 .  
         [0085]     Based on mode selection information provided by the determination unit  520 , the first selection unit  520  transfers 8-bit input data and control data input in parallel from the outside, to one of the MB810 encoder  540  and the 8B/10B encoder  550 .  
         [0086]     The MB810 encoder  540  has the same structure as that of the MB810 encoder  300  explained referring to  FIG. 12 . If mode selection information indicating that the MB810 encoder is determined as the operating encoder is input from the determination unit  510 , the MB810 encoder  540  performs encoding based on the encoding method of the MB810 encoder  300  explained referring to  FIG. 12 , and provides the generated 10-bit code to the second selection unit  560 .  
         [0087]     If mode selection information indicating that the 8B/10B encoder is determined as the operating encoder is input from the determination unit  510 , the 8B/10B encoder  550  performs encoding based on the 8B/10B encoding method, and provides the generated 10-bit code to the second selection unit  560 .  
         [0088]     The second selection unit  560  provides the 10-bit parallel code provided by the encoder determined as the operating encoder by the determination unit  510  (that is, any one of the MB810 encoder  540  and the 8B/10B encoder  550 ), to the serial conversion unit  570 . The serial conversion unit  570  converts the input 10-bit parallel code into a 10-bit serial code and provides to the switch unit  575 .  
         [0089]     The switch unit  575  drives switch A so that the output signal of the serial conversion unit  570  is transferred to a low pass filter  580  or  590  corresponding to the encoder selected as the operating encoder by the determination unit  510  and drives switch B so as to selectively output the output signal of an amplifier  585  or  595 .  
         [0090]     The first low pass filter  580  and the first amplifier  585  are elements corresponding to the MB810 encoder  540  and the second low pass filter  590  and the second amplifier  595  are elements corresponding to the 8B/10B encoder  550 .  
         [0091]     The first low pass filter  580  in combination with a first low pass filter  605  shown in  FIG. 15  has a cut-off frequency which becomes an optimum filter, and the roll off characteristic at the cut-off frequency is the same as that of the second low pass filter  590 . At this time, the roll off characteristic at the cut-off frequency means the attenuation amount for each frequency level compared to a reference frequency and group delay distortion.  
         [0092]     The cut-off frequency that becomes an optimum filter by combination of the first low pass filter  580  and the first low pass filter  605  shown in  FIG. 15  is half the cut-off frequency by combination of the second low pass filter  590  and a second low pass filter  610  corresponding to the 8B/10B decoder  660  shown in  FIG. 15 .  
         [0093]     The fist low pass filter  580  cuts off the high frequency band of the 10-bit serial code input through switch A of the switch unit  575  according to a designed cut-off frequency and roll off characteristic, and transfers the code to the first amplifier  585 . The first amplifier  585  amplifies the signal input from the first low pass filter  580  to suit an output power level determined by IEEE 802.3 standard specifications, and outputs the signal as a 10-bit output code through switch B of the switch unit  575 .  
         [0094]     The second low pass filter  590  cuts off the high frequency band of the 10-bit serial code input through switch A of the switch unit  575  according to a cut-off frequency designed complying with IEEE 802.3 standard specifications and roll off characteristic, and transfers the code to the second amplifier  595 . The second amplifier  595  amplifies the signal input from the second low pass filter  590  to suit an output power level determined by IEEE 802.3 standard specifications, and outputs the signal as a 10-bit output code through switch B of the switch unit  575 .  
         [0095]      FIG. 15  is a block diagram showing the structure of a dual mode decoder according to the present invention.  
         [0096]     Referring to  FIG. 15 , the dual mode decoder comprises a first low pass filter  605 , a second low pass filter  610 , a first switch unit  615 , a second switch unit  620 , a frequency multiplying unit  625 , a clock reproduction unit  630 , an IDLE code detection unit  635 , a mode detection unit  640 , a parallel conversion unit  645 , a first selection unit  650 , an MB810 decoder  655 , an 8B/10B decoder  660 , a data clock generation unit  665 , and a second selection unit  670 . Among these elements, the second switch unit  620  and the frequency multiplying unit  625  are selected employed, and when there is a user request, mode selection information detected in the mode detection unit  640  is transferred to the second switch unit  620 .  
         [0097]     The first low pass filter  605  is a filter corresponding to the MB810 decoder  655 . The first low pass filter  605  cuts off the high frequency band of an input 10-bit serial code according to a designed cut-off frequency and roll off characteristic, and transfers the code to the first switch unit  615 . The second low pass filter  610  is a filter corresponding to the 8B/10B decoder  660 . The second low pass filter  610  cuts off the high frequency band of the input 10-bit serial code according to a designed cut-off frequency and roll off characteristic, and transfers the code to the first switch unit  615 . The first low pass filter  605  has a cut-off frequency which becomes an optimum filter by combination with the first low pass filter  580  shown in  FIG. 14 , and the roll off characteristic at the cut-off frequency is the same as that of the second low pass filter  610 . The cut-off frequency which becomes an optimum filter by combination of the first low pass filter  605  and the first low pass filter  580  shown in  FIG. 14  is half the cut-off frequency by combination of the second low pass filter  610  and the second low pass filter  590  corresponding to the 8B/10B encoder  550  shown in  FIG. 14 .  
         [0098]     In its initial state, the first switch unit  615  selects the output of the second low pass filter  610 , and when there is a request of the mode detection unit  640 , selects the first low pass filter  605 . The first switch unit  615  transfers the output of the selected low pass filter  605  or  610 , to the second switch unit  620 , the frequency multiplying unit  625 , the IDLE code detection unit  635 , and the parallel conversion unit  645 .  
         [0099]     The frequency multiplying unit  625  multiplies the frequency of the 10-bit serial code provided through the first switch unit  615  by 2, and outputs the result to the second switch unit  620 . When there is no request from the mode detection unit  640 , the second switch unit  620  selects the output of the first switch unit  615 , and when there is a request from the mode detection unit  640 , selects the output of the frequency multiplying unit  625 . The second switch unit  620  transfers the selected output to the clock reproduction unit  630 .  
         [0100]     The clock reproduction unit  630  extracts a 10-bit clock signal from the 10-bit serial code input through the second switch unit  620 , and provides the signal to the IDLE code detection unit  635 , the parallel conversion unit  645 , and the data clock generation unit  665 . The data clock generation unit  665  converts the 10-bit code clock input from the clock reproduction unit  630 , into an 8-bit data clock and provides the clock signal to the MB810 decoder  655  and the 8B/10B decoder  660 .  
         [0101]     The IDLE  635  detects +K28.5/−K28.5 and +K28.7/−K28.7 codes that are IDLE codes to recognize as the boundary of a 10-bit code, and transfers input codes in units of 10-bit codes, to the mode detection unit  640 . At this time, if K28.7 code is detected contiguously twice or more, the IDLE code detection unit  635  recognizes the corresponding code as IDLE code.  
         [0102]     The mode detection unit  640  analyzes the contents of IDLE code input from the IDLE code detection unit  635  and determines whether the dual mode decoder according to the present invention is to be used as the MB810 decoder  655  or the 8B/10B decoder  660 . The mode detection unit  640  transfers mode determination information to the first switch unit  650 , the second selection unit  670 , the MB810 decoder  655 , and the 8B/10B decoder  660 . Also, when there is a user request, the mode detection unit  640  operates the second switch unit  620  so that the output of the frequency multiplying unit  625  is transferred to the clock reproduction unit  630 .  
         [0103]     The parallel conversion unit  645  converts the 10-bit serial code input from the first switch unit  615  into a 10-bit parallel code and transfers the parallel code to the first selection unit  650 . The first selection unit  650  transfers the 10-bit parallel code input from the parallel conversion unit  645  to one of the MB810 decoder  655  and the 8B/10B decoder  660  according to the mode determination information input from the mode detection unit  640 .  
         [0104]     The MB810 decoder  655  converts the 10-bit code information input from the first selection unit  650  into 8-bit data information according to the MB810 decoding method explained referring to  FIG. 13 . The 8-bit data information output from the MB810 decoder  655  is output as 8-bit parallel data, clock information and control code, through the second selection unit  670 .  
         [0105]     The 8B/10B decoder  660  converts the 10-bit code information into 8-bit data information according to the 8B/10B decoding method. The 8-bit data information output from the 8B/10B decoder  660  is output as 8-bit parallel data, clock information and control code, through the second selection unit  670 .  
         [0106]      FIGS. 16   a  and  16   b  are flowcharts of the steps performed by a dual mode processing method according to the present invention. The flowcharts of  FIGS. 16   a  and  16   b  are showing a process for the mode detection unit  640  determining a mode of the decoder when the dual mode decoder shown in  FIG. 15  is initialized.  
         [0107]     Referring to  FIGS. 16   a  and  16   b,  if the dual mode decoder is initialized in step S 700 , the mode detection unit  640  sets count value N of the counter arranged inside the mode detection unit  640 , to 0 in step S 705 . The initialization operation of the dual mode decoder may be set so that the initialization operation is performed when an enough IDLE time continues according to the set state. The counter is an element counting the number of IDLE codes in order to determine the operation mode of the dual mode decoder. After the initialization is performed, the mode detection unit  640  receives a code from the IDLE code detection unit  635  in step S 710 . Then, the mode detection unit  640  checks whether or not the received code is +K28.7 that is the IDLE code of the MB810 decoder in step  715 . If the input code is +K28.7, the mode detection unit  640  increases count value N of the counter by 1 and again receives a next code from the IDLE code detection unit  635  in step S 720 .  
         [0108]     Next, the mode detection unit  640  checks whether or not the code input in the step S 720  is −K28.7 in step S 725 . If the code input in the step S 720  is −K28.7, the mode detection unit  640  compares the number of K28.7 codes input till that time, with a set reference value M 1  in step S 730 . Reference value M 1  is a value preset by the user and a value defined in IEEE 802.3 specifications may be set as reference value M 1 . If it is determined that the number of K28.7 codes input till that time is equal to or greater than reference value M 1 , the mode detection unit  640  outputs mode determination information indicating that the dual mode decoder according to the present invention operates as the MB810 decoder in step S 735 . Unlike this, if it is determined that the number of K28.7 codes input till that time is less than reference value M 1 , the step S 710  is performed. If it is determined that the code input in the step S 720  is not −K28.7, the mode detection unit  640  performs step S 755 .  
         [0109]     Meanwhile, if it is determined that the code input in the step S 710  is not +K28.7, the mode detection unit  640  checks whether or not the code input in the step S 710  is −K28.7 in step S 740 . If the code input in the step S 710  is −K28.7, the mode detection unit  640  increases count value N of the counter by 1, and again receives a next code from the IDLE code detection unit  635  in step S 745 . Then, the mode detection unit  640  checks whether or not the code input in the step S 745  is +K28.7 in step S 750 . If the code input in the step S 745  is +K28.7, the mode detection unit  640  performs the step S 730 . Unlike this, if the code input in the step S 745  is not +K28.7, the mode detection unit  640  checks whether or not the code input in the step S 745  is +K28.5 that is the IDLE code of the 8B/10B decoder in the step S 755 . If the code input in the step S 710  is not −K28.7, the mode detection unit  640  performs the step S 755 . The step S 755  is performed when the code received by the mode detection unit in the step S 710  is neither +K28.7 nor −K28.7, when the code input in the step S 720  is not −K28.7, and when the code input in the step S 745  is not +K28.7.  
         [0110]     If the result of performing the step S 755  indicates that the input code is +K28.5, the mode detection unit  640  again receives a next code from the IDLE code detection unit  635  in step S 760 . Then, the mode detection unit  640  checks whether or not the code input in the step S 760  is D5.6 code of 8B/10B (that is, 1010010110) in step S 765 . If the code input in the step S 760  is D5.6 code, the mode detection unit  640  increases count value N of the counter by 1 in step S 770 . After increasing count value N of the counter by 1, the mode detection unit  640  checks whether or not the number of K28.5 codes received till that time is equal to or greater than reference number M 2  in step S 775 . Reference number M 2  is a value preset by the user and a value defined in IEEE 802.3 specifications may be set as reference number M 2 . If the number of K28.5 codes continuously received till that time is equal to or greater than reference number M 2 , the mode detection unit  640  outputs mode determination information indicating that the dual mode decoder according to the present invention operates as the 8B/10B decoder in step S 780 . Unlike this, if the number of K28.7 codes input till that time is less than set reference number M 2 , the mode detection unit  640  performs the step S 710 .  
         [0111]     Meanwhile, if the code input in the step S 760  is not D5.6 code, the mode detection unit checks whether the code input in the step S 760  is a control code in step S 800 . If the code input in the step S 760  is a control code, the mode detection unit  640  performs the step S 710 . Unlike this, if the code input in the step S 760  is not a control code, the mode detection unit  640  determines that an error such as a transmission line error has occurred, and performs the step S 700  or performs a diagnostic operation such as transmission of a test code in step S 805 .  
         [0112]     Meanwhile, if the result of performing the step S 755  indicates that the codes input in the steps S 710 , S 720 , and S 745  are not +K28.5, the mode detection unit  640  checks whether or not the codes input in the steps S 710 , S 720 , and S 745  are −K28.5 in step are −K28.5 in step S 785 . If the codes input in the steps S 710 , S 720 , and S 745  are −K28.5, the mode detection unit again receives a next code from the IDLE code detection unit  635  in step S 790 . Then, the mode detection unit  640  checks whether or not the code input in the step S 790  is D16.2 in step S 795 . If the code input in the step S 790  is D16.2, the mode detection unit  640  performs the step S 770 . Unlike this, if the code input in the step S 790  is not D16.2, the mode detection unit  640  performs the step S 800 .  
         [0113]     According to the MB810 line code apparatus and MB810 code generation method using the control codes according to the present invention, the transmission bandwidth becomes half that of the prior art including the 8B/10B codes such that when an identical transmission medium is used, relatively long-distance transmission is enabled. In addition, the present invention can be applied with the MB810 codes without changing the prior art 8B/10B code method such that the dual mode operation allowing the user to select a desired line code can be performed. Furthermore, the serial conversion apparatus, the parallel conversion apparatus, the clock reproducing unit and data clock generation unit of the decoder, and code clock generation unit of the encoder in the prior art 8B/10B code apparatus can be utilized without change.  
         [0114]     Meanwhile, according to the present invention, the low pass filter used in the MB810 encoder and the low pass filter used in the MB810 decoder have characteristics identical to the roll off characteristics of the low pass filters of the 8B/10B encoder and decoder. In addition, the cut-off frequency by combination of the low pass filter of the MB810 encoder and the low pass filter used in the MB810 decoder is half the cut-off frequency by combination of the low pass filter of the 8B/10B encoder and the low pass filter of the 8B/10B decoder and is much easier to be implemented by an identical technology. In particular, the bandwidth required by the amplifier of the MB810 encoder is half the bandwidth required by the amplifier of the 8B/10B encoder and can be implemented easily by an identical technology.  
         [0115]     Furthermore, when a code is set, a complementary code is always used such that the operation of the decoder is simplified. Also, transition from all states is available and K28.7 that has a single pair and is a reserved code in the 8B/10B code system is set as IDLE code. By doing so, when the apparatus operates in dual mode, the 8B/10B codes and MB810 codes can be easily distinguished and the structure in the physical layer is simplified.  
         [0116]     The invention can also be embodied as computer readable codes on a computer readable recording medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, optical data storage devices, and carrier waves (such as data transmission through the Internet). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.  
         [0117]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. Such variations and modifications are within the scope of the present invention defined in the appended claims.