Abstract:
Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2 n  steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2 m  steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     The application is a divisional application of U.S. patent application Ser. No. 10/858,240, filed on Jun. 1, 2004 which claims priority to Korean Patent Application No. 2003-34225, filed on May 29, 2003. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field  
         [0003]     The present invention relates to a circuit for compensating for the declination of balanced impedance elements and a frequency mixer, and more particularly to a circuit for reducing secondary-order inter modulation -distortion (IMD2) in a direct conversion receiver (DCR).  
         [0004]     2. Discussion of the Related Art  
         [0005]     Recently, various communication circuits have been integrated into a single semiconductor chip using a system-on-a-chip (SOC) design. For example, a typical radio frequency (RF) transmitter and receiver circuit used by a mobile communications device has been integrated into a single integrated circuit (IC) using a SOC design.  
         [0006]     Balanced impedance elements are commonly used in SOC designs. Each of the impedance values of the balanced impedance elements may typically deviate from the designed (or desired) impedance values and have a variation (or declination) from one another due to certain technical limits resulting from the manufacture of the semiconductor device. Such technical limits or constraints that occur during manufacturing are, for example, mismatch of the area of the impedance elements and mismatch of the concentration of impurities. In a typical RF receiver circuit, the impedance variation of the balanced impedance elements may distort signals and deteriorate communication qualities.  
         [0007]      FIG. 1  is a block diagram showing a conventional DCR. Referring to  FIG. 1 , the DCR converts an input RF signal into a baseband signal having an in-phase (I) component and a quadrature (Q) component instead of an intermediate frequency (IF) signal. An RF signal received from an antenna  10  is input to a low noise amplifier (LNA)  12  and is applied to mixers  14  and  16 .  
         [0008]     The mixer  14  mixes the RF signal output from the LNA  12  with a first local oscillating signal, such as cos(ωt). The local oscillating signal is generated from a local oscillator (LO)  20  and has the same frequency as a carrier frequency (fc) of the RF signal. The mixer  16  mixes the RF signal output from the LNA  12  with a second local oscillating signal, for example sin(ωt), having a phase difference of more than π/2 with respect to the first oscillating signal.  
         [0009]     The mixers  14  and  16  generate a baseband signal that has a carrier frequency of 2*fc and an I component and Q component. Subsequently, some of the harmonics in the baseband signal are removed by low pass filters  22  and  24 , and the baseband signal is then amplified by amplifiers  26  and  28 .  
         [0010]     The DCR of  FIG. 1  has a basic circuit structure that occupies a small surface area on an IC and thus may easily be integrated into a SOC design. Because the DCR occupies such a small area, it may be manufactured at a low price. However, the DCR has certain disadvantages. For example, the mixers  14  and  16  generate a IMD2 because the mixers  14  and  16  are non-linear devices. Thus, the mixers  14  and  16  cause a direct current (DC) offset and generate not only a desired frequency signal but also a second order harmonic signal.  
         [0011]     In particular, when signals having two frequencies f 1  and f 2  are input to a general non-linear circuit, signals having 2*f 1 , 2*f 2 , f 1 +f 2 , 3f 1 , 3f 2 , 2*f 1 -f 2 , 2f 2 -f 1 , 2f 1 +f 2  or 2f 2 +f 1 , . . . frequencies are generated from, for example, the mixers  14  and  16  due to the non-linear properties of the mixers  14  and  16 .  
         [0012]     Normally, the undesired frequencies resulting from the non-linear properties of the mixers  14  and  16  are removed by means of, for example, the low pass filters  22  and  24 . However, when the input frequencies f 1  and f 2  are almost equal and the desired frequency signal is the baseband signal, the frequencies of f 1  and f 2  may be in the range of the baseband frequencies and may not be removed by the filters  22  and  24 . These unfiltered signals may then cause interferences between channels having small frequency differences from adjacent channels and signal distortions due to the interferences between the unfiltered signals themselves.  
         [0013]     The f 1  and f 2  frequency signal is referred to as the IMD2. The degree of the linearity of a circuit is represented by the relationship between the ratio of the IMD2 and the amplification of the signal input to the circuit. The degree of the linearity is referred to as 2 nd  order intercept point (IP2). In addition, since the DCR shifts the desired signal to the baseband frequencies, the IMD2 generated from the mixers  14  and  16  may greatly deteriorate the performance of the DCR. Accordingly, the mixers  14  and  16  or a frequency mixer should have a high IP2 to reduce the ratio of the IMD2.  
         [0014]      FIG. 2  is a circuit diagram showing a conventional Gilbert cell mixer. Referring to  FIG. 2 , the Gilbert cell mixer includes an emitter coupled pair of transistors Q 1  and Q 2  to which RF signals (RF + , RF − ) are input, regeneration resistors RE 1  and RE 2 , Gilbert cell core transistors Q 3 , Q 4 , Q 5  and Q 6 , pull-up resistors R 1  and R 2 , and differential output nodes NO 1  and NO 2 .  
         [0015]     In the Gilbert cell mixer, when second order harmonic signals (each of which is the same) are generated at each of the differential output nodes NO 1  and NO 2 , the second order harmonic signals may be cancelled by each other and rejected by a common mode rejection property. However, when the second order harmonic signals have a phase and amplitude different from each other, the second order harmonic signals may not be cancelled due to a mismatch in their phases and amplitudes.  
         [0016]     The mismatch may occur at the transistors Q 1  and Q 2 , the resistors RE 1  and RE 2  and result from the duty ratio of the local oscillating signals and the RF signal. The mismatch at certain elements (resistors, transistors, etc.), is caused by the size difference between the elements and a difference in the concentration of impurities.  
         [0017]     A feedback circuit for compensating for the non-linearity of the Gilbert cell mixer is disclosed in U.S. Patent Application Publication No. 2002-193089A1, and a system for reducing intermodulation distortion in a DCR is disclosed in PCT Laid Open Patent Publication No. WO 02/80384 A1. According to the disclosure in the U.S. Patent Application Publication No. 2002-193089A1, a bias voltage of the transistor in the Gilbert cell core is regulated in response to the voltage difference between the differential output nodes, so that the mismatch of the area of the transistor is compensated. In the PCT Laid Open Patent Publication No. WO 02/80384 A1, a frequency mixer detects an intermodulation signal included in an RF signal input to the frequency mixer, and applies a compensation signal to an output signal of the frequency mixer, so that intermodulation distortion in the output signal may be reduced.  
         [0018]     Thus, there is a need for a circuit that reduces IMD2 and DC offset in DCRs.  
       SUMMARY OF THE INVENTION  
       [0019]     In one embodiment of the present invention, a compensation circuit for compensating for a difference between impedance measured from first and second impedance elements comprises a first impedance circuit and a second impedance circuit. The first impedance circuit transforms a first impedance value into a fine impedance value having 2 n  steps in response to n lower bits of a control signal having k bits. The first impedance value is measured at the first impedance element, and k is equal to m plus n. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2 m  steps in response to m upper bits of the control signal. The second impedance value is measured at the second impedance element.  
         [0020]     The first and second impedance elements may be a pair of balanced impedance elements wherein each of which provides two nodes of the circuit that has a symmetric structure with the same impedance in a balanced condition. For example, the first and second impedance elements comprise resistive elements or capacitive elements. When the first and second impedance elements are resistive elements, the first and second impedance circuits respectively may be coupled in parallel to one of the first and second resistive elements.  
         [0021]     In accordance with an embodiment of the present invention where the first and second impedance elements are resistive elements, the first resistor comprises n resistors and n first switching elements. The n resistors may be coupled with one another in parallel, the n resistors have a 2 (k−p) (n−m≦p≦n) different resistance, and p is a positive integer. The n first switching elements may be respectively serially coupled with one of the n resistors, and each of said n first switching elements is switched in response to a corresponding bit of said n lower bits of the control signal.  
         [0022]     The second resistor comprises m resistors, m second switching elements and a dummy resistor. The m resistors may be coupled with one another in parallel, the m resistors have a 2 (k−q) (n+ 1≦q≦m+n) different resistance, and q is zero or the positive integer. The m second switching elements may be respectively serially coupled with one of the m resistors, and each of said m second switching elements is switched in response to a corresponding bit of said m upper bits of the control signal. The dummy resistor may be coupled with said m resistors in parallel, and the dummy resistor has a resistance substantially the same as an equivalent resistance of said n resistors coupled in parallel with one another.  
         [0023]     The first and second resistors further comprise a third switching element switched in response to the sign bit so that the first resistor is coupled in parallel with the second resistive element and the second resistor is coupled in parallel with the first resistive element.  
         [0024]     The difference detection section comprises first and second measuring sections, a difference obtaining section and a look-up table. The first and second measuring sections measure the resistance of the first and second resistive elements, respectively, and the difference obtaining section obtains a difference value between the measured resistance of the first and second resistive elements. The look-up table outputs the control signal in response to the difference value.  
         [0025]     When the first and second impedance elements are capacitive elements, the first and second impedance circuits respectively may be coupled in parallel to one of the first and second capacitive elements.  
         [0026]     In accordance with an embodiment of the present invention where the first and second impedance elements are capacitive elements, the first capacitor comprises n capacitors and n first switching elements. The n capacitors may be coupled with one another in series, the n capacitors have a 2 (k−p)  (n−m≦p≦n) different capacitance, and p is the positive integer. The n first switching elements may be respectively in parallel coupled with one of the n capacitors, and each of said n first switching elements is switched in response to a corresponding bit of said n lower bits of the control signal.  
         [0027]     The second capacitor comprises m capacitors, m second switching elements and a dummy capacitor. The m capacitors may be coupled with one another in series, the m capacitors have a 2 (k−q)  (n+1≦q≦m+n) different capacitance, and q is zero or the positive integer. The m second switching elements may be respectively in serial coupled with one of the m capacitors, and each of said m second switching elements are switched in response to a corresponding bit of said m upper bits of the control signal. The dummy capacitor may be coupled with said m capacitors in parallel, and the dummy capacitor has a capacitance substantially the same as an equivalent capacitance of said n capacitors coupled in parallel with one another. Each of the first and second capacitors further comprise a third switching element being switched in response to the sign bit so that the first capacitor is coupled in serial with the second capacitive element and the second capacitor is coupled in serial with the first capacitive element.  
         [0028]     According to the compensation circuit of the present invention, the impedance difference between the impedance elements vary substantially linearly based on a control code of the control signal. In a coarse compensation operation, the impedance difference varies according to 2 m  steps in response to the control code. In a fine compensation operation, the impedance difference varies according to 2 n  steps (m&lt;n) in response to the control code. Therefore, the difference of the impedance measured at the first and second impedance elements varies linearly according to the control code.  
         [0029]     In accordance with yet another embodiment of the present invention, a circuit for mixing frequencies comprises a mixer, first and second pull-up resistors and a difference compensation circuit. The mixer receives a first input signal having a first frequency and a second input signal having the first frequency, and the first input s signal has an inverted phase with respect to the second input signal. The mixer mixes a local oscillating signal having a second frequency with the first and second input signals to output first and second output signals to first and second output terminals, respectively. The first output signal has a third frequency corresponding to a first difference between the second and first frequency, and the second output signal has the third frequency. The first pull-up resistor pulls up the first output terminal, and the second pull-up resistor pulls up the second output terminal. The difference compensation circuit is coupled with the first and second pull-up resistors, and compensates for a second difference between the resistance measured from the first and second pull-up resistors in response to a control signal having (k+1) bits.  
         [0030]     The difference compensation circuit comprises first and second resistors. The first resistor may be coupled in parallel to the first pull-up resistor, and transforms a first compound resistance value into a fine resistance value having 2 n  steps in response to n lower bits of the k bits of the control signal. The first resistance value is measured at the first pull-up resistor, and k is equal to m plus n, wherein m and n are positive integers. The second resistor may be coupled in parallel to the second pull-up resistor, and transforms a second resistance value into a coarse resistance value having 2 m  steps in response to m upper bits of k bits of the control signal. The second compound resistance value is measured at the second pull-up resistor.  
         [0031]     The difference compensation circuit further comprises a difference detection section, and the difference detection section comprises a detection section, an analog-to-digital converter and a look-up table. The detection section detects a voltage difference between the first and second output terminals. The analog-to-digital converter generates a digital voltage difference corresponding to the detected voltage difference, and the look-up table outputs the control signal in response to the digital voltage difference.  
         [0032]     In accordance with yet another embodiment of the present invention, a compensation circuit for compensating for a difference between impedance measured from first and second impedance elements, comprises: a first impedance circuit, coupled to a first impedance element, for transforming a first impedance  10  value of the first impedance element into a fine impedance value in response to a control signal; a second impedance circuit, coupled to a second impedance element, for transforming a second impedance value of the second impedance element into a coarse impedance value in response to the control signal; and a difference detection circuit, coupled to the first and second impedance circuits, for measuring the impedance of the first and second impedance elements and for generating the control signal to compensate for a difference between the measured impedance. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0033]     The aspects of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:  
         [0034]      FIG. 1  is a block diagram showing a conventional direct conversion receiver (DCR);  
         [0035]      FIG. 2  is a circuit diagram showing a conventional Gilbert cell mixer;  
         [0036]      FIG. 3  is a block diagram showing a difference compensation circuit according to an exemplary embodiment of the present invention;  
         [0037]      FIG. 4  is a circuit diagram showing digital variable impedance elements of  FIG. 3 ;  
         [0038]      FIG. 5  is a graph showing a resistance variation according to a variation of a digital value of a control signal generated from the difference compensation circuit of  FIG. 3 ;  
         [0039]      FIG. 6  is a block diagram showing a difference compensation circuit according to another exemplary embodiment of the present invention;  
         [0040]      FIG. 7  is a circuit diagram showing digital variable impedance elements of  FIG. 6 ;  
         [0041]      FIG. 8  is a block diagram showing a frequency mixer according to yet another exemplary embodiment of the present invention;  
         [0042]      FIG. 9  is a block diagram showing a variant of a difference compensation circuit of  FIG. 8 ; and  
         [0043]      FIG. 10  is a block diagram showing another variant of the difference compensation circuit of  FIG. 8 . 
     
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0044]      FIG. 3  is a block diagram showing a difference compensation circuit  100  for compensating for the difference between impedance measured from balanced impedance elements according to an exemplary embodiment of the present invention.  FIG. 4  is a circuit diagram showing digital variable impedance elements of  FIG. 3 . For exemplary purposes, the impedance measured from the balanced impedance elements of  FIG. 3  and the digital variable impedance elements of  FIG. 4 , are hereinafter referred to and depicted as a resistance measured from balanced resistive elements and digital variable resistors, respectively. It is to be understood that the term “impedance” as used herein is known to a person of ordinary skill in the art to mean, a measure of the total opposition to current flow in an electric circuit, which is determined by a particular combination of resistance (measured across a resistor), capacitive reactance (measured across a capacitor) or inductive reactance (measured across an inductor) in a given circuit. Referring to  FIGS. 3 and 4 , the difference compensation circuit  100  includes a first digital variable resistor  110 , a second digital variable resistor  120  and a difference detection section  130 .  
         [0045]     The first digital variable resistor  110  is connected in parallel to a resistor R 1 , the second digital variable resistor  120  is connected in parallel to a resistor R 2 . The difference detection section  130  is connected to the resistors R 1  and R 2 , calculates the resistance difference between the resistors R 1  and R 2 , and provides the first and second digital variable resistors  110  and  120  with an 8 bit control signal (D 7 , D 6 , . . . , D 0 ) or (DO, D 1 , . . . , D 7 ) for compensating for the calculated resistance difference. The uppermost bit D 7  of the 8 bit control signal is a sign bit. The sign bit is positive or negative according to the bit value ‘1’ or ‘0’: The upper 3 bits (D 6 , D 5 , D 4 ) are provided to the first digital variable resistor  110 , and the lower 4 bits (D 3 , D 2 , D 1 , D 0 ) are provided to the second digital variable resistor  120 . The upper 4 bits (D 7 , D 6 , D 5 , D 4 ) are inverted by inverters INV 1 , INV 2 , INV 3  and INV 4  before the upper 4 bits (D 7 , D 6 , D 5 , D 4 ) are output from the difference detection section  130 .  
         [0046]     The first digital variable resistor  110  includes four resistors R,  2 R,  4 R and Rd each of which is coupled in parallel to nodes NA 1  and NA 2 . The resistor R has a unit resistance R, the resistance of the resistor  2 R is two times as large as the unit resistance R, and the resistance of the resistor  4 R is four times as large as the unit resistance R. The resistor Rd is a dummy resistor, and the resistance of the dummy resistor Rd is the same as an equivalent resistance of resistors  8 R,  16 R,  32 R and  64 R, which are coupled in parallel with one another in the second digital variable resistor  120 .  
         [0047]     A switching element ST 1  is serially connected to the resistor R, a switching element ST 2  is serially connected to the resistor  2 R, a switching element ST 3  is serially connected to the resistor  4 R, and a switching element ST 4  is serially connected to the resistor Rd. The switching element ST 4  is maintained in a turn-on state. The switching elements ST 1 , ST 2  and ST 3  are turned on in response to inverted upper 3 bits {overscore (D 6 )}, {overscore (D 5 )} and {overscore (D 4 )}, respectively. As shown in  FIG. 4 , when a positive-channel metal oxide semiconductor (PMOS) transistor is used as the switching elements (e.g., ST 1 -ST 4 ), a control electrode of the switching element ST 4  is connected to a low power source (VSS), for example, an earth potential.  
         [0048]     The second digital variable resistor  120  includes the four resistors  8 R,  16 R,  32 R and  64 R each of which is coupled in parallel to nodes NA 4  and NA 5 . The resistance of the resistor  8 R is eight times as large as the unit resistance R, the resistance of the resistor  16 R is sixteen times as large as the unit resistance R, and the resistance of the resistor  64 R is sixty four times as large as the unit resistance R.  
         [0049]     A switching element ST 5  is serially connected to the resistor  8 R, a switching element ST 6  is serially connected to the resistor  16 R, a switching element ST 7  is serially connected to the resistor  32 R, and a switching element ST 8  is serially connected to the resistor  64 R. The switching elements ST 5 , ST 6 , ST 7  and ST 8  are turned on in response to the lower 4 bits D 3 , D 2 , D 1  and D 0 , respectively.  
         [0050]     The output resistance of the first digital variable resistor  110  has 8 coarse levels ( 0 ,  1 , . . . ,  7 ) according to the value of the  3  inverted bits {overscore (D 6 )}, {overscore (D 5 )} and {overscore (D 4 )}. The dummy resistor Rd determines a difference between each of the coarse 8 levels. The output resistance of the second digital variable resistor  120  has 16 fine levels ( 0 ,  1 , . . . ,  15 ) determined by the value of  4  the bits D 3 , D 2 , D 1  and D 0 . The resistor  64 R determines the difference between each of the fine 16 levels.  
         [0051]     Therefore, a total equivalent resistance Rx (or Rt 1  of  FIG. 5 ) between the node NA 1  and a node NA 3  varies according to the coarse  8  levels. In the coarse 8 levels, the dummy resistor Rd is a unit resistance. A total equivalent resistance Ry (or Rt 2  of  FIG. 5 ) between the node NA 4  and a node NA 6  varies according to the fine 16 levels. In the fine 16 levels, the resistor  64 R is a unit resistance.  
         [0052]     For example, when the resistors R 1  and R 2  are respectively 1□, and the resistor R is 22.5□, the difference resistance in the coarse 8 levels varies by about 11□, and the difference resistance in the fine 16 levels varies by about 0.7□. Therefore, the total difference resistance ΔR varies linearly according to 127 levels. The total difference resistance ΔR is shown in expression 1. 
 
 ΔR=Rx (or  Rt 1)− Ry (or  Rt 2)   (1) 
 
         [0053]     The first digital variable resistor  110  also includes a first switching circuit  112 , and the second digital variable resistor  120  includes a second switching circuit  122 . In the first switching circuit  112 , a switching element ST 9  is connected between the nodes NA 2  and NA 3 , and a switching element ST 10  is connected between the nodes NA 2  and NA 6 . The switching element ST 9  is switched by the upper most bit D 7 , and the switching element ST 10  is switched by the inverted upper most bit {overscore (D 7 )}. In the second switching circuit  122 , a switching element ST 11  is connected between the nodes NA 5  and NA 3 , and a switching element ST 12  is connected between the nodes NA 5  and NA 6 . The switching element ST 11  is switched by the inverted upper most bit {overscore (D 7 )}, and the switching element ST 12  is switched by the upper most bit D 7 .  
         [0054]     When the switching elements ST 9 , ST 10 , ST 11  and ST 12  are PMOS transistors and D 7  has a logic value of ‘0’, the switching elements ST 9  and ST 12  are turned on and the switching elements ST 10  and ST 11  are turned off. Accordingly, the first digital variable resistor  110  is connected to the node NA 3  via the switching element ST 9 , and the second digital variable resistor  120  is connected to the node NA 6  via the switching element ST 12 . When D 7  has logic value of ‘1’, the switching elements ST 9  and ST 12  are turned off and the switching elements ST 10  and ST 11  are turned on. Accordingly, the first digital variable resistor  110  is connected to the node NA 6  via the switching element ST 10 , and the second digital variable resistor  120  is connected to the node NA 3  via the switching element ST 11 .  
         [0055]     According to the first and second switching circuits  112  and  122 , the first digital variable resistor  110  is electrically connected in parallel to not only the resistor R 1  but also the resistor R 2 , and the second digital variable resistor  122  is electrically connected in parallel to not only the resistor R 2  but also the resistor R 1 .  
         [0056]     As shown in  FIG. 5 , the total difference resistance AR is regulated to vary from a −127 level to +127 level according to the 8 bit control signal (D 0 , D 1 , . . . , D 7 ). According to the first and second switching circuits  112  and  122 , an 8 bit control signal instead of a 16 bit control signal is input to the first and second digital variable resistors  110  and  120 . Therefore, a number of external terminals (in, for example, the difference compensation circuit  100 ) is reduced by ½. When the 16 bit control signal is input to each of the first and second digital variable resistors  110  and  120 , the number of external terminals may increase by two.  
         [0057]     As shown in  FIG. 3 , the difference detection section  130  includes first and second resistance measuring sections  132  and  134 , a difference obtaining section  136  and a look-up table  138 . The first resistance measuring section  132  measures the resistance of the resistor R 1 , and the second resistance measuring section  134  measures the resistance of the resistor R 2 . The first and second resistance measuring sections  132  and  134  are not electrically connected to the resistors R 1  and R 2  in a normal operation mode, but are electrically connected to the resistors R 1  and R 2  in a compensation operation mode. In addition, the first and second resistance measuring sections  132  and  134  have high input impedance to enable precise measurements of the resistance of the resistors R 1  and R 2 .  
         [0058]     The measured resistance is provided to the difference obtaining section  136 . The difference obtaining section  136  obtains a difference value (e.g., a declination or variation) between the measured resistance of the resistor R 1  and the measured resistance of the resistor R 2 , and generates digital data corresponding to the difference value. The digital data is represented in an address of the look-up table  138 , and the 8 bit control signal corresponding to the address designated by the digital data is provided to the first and second digital variable resistors  110  and  120 .  
         [0059]      FIG. 6  is a block diagram showing a difference compensation circuit  200  for compensating for the difference between impedance measured from balanced impedance elements according to another exemplary embodiment of the present invention.  FIG. 7  is a circuit diagram showing digital variable impedance elements of  FIG. 6 . For exemplary purposes, the impedance measured from the balanced impedance elements of  FIG. 6  and the digital variable impedance elements of  FIG. 7 , are hereinafter referred to and depicted as capacitance measured from balanced capacitive elements and digital variable capacitors, respectively. Referring to  FIGS. 6 and 7 , the difference compensation circuit  200  includes a first digital variable capacitor  210 , a second digital variable capacitor  220  and a difference detection section  230 .  
         [0060]     The first digital variable capacitor  210  is connected in series to a capacitor C 1 , and the second digital variable capacitor  220  is connected in series to a capacitor C 2 . The difference detection section  230  is connected to the capacitors C 1  and C 2 , calculates the capacitance difference between the capacitors C 1  and C 2 , and provides the first and second digital variable capacitors  210  and  220  with an 8 bit control signal (D 7 , D 6 , . . . , D 0 ) for compensating for the capacitance difference. The uppermost bit D 7  of the 8 bit control signal is a sign bit. The sign bit is positive or negative according to the bit value ‘1’ or ‘0’. The upper 3 bits (D 6 , D 5 , D 4 ) are provided to the first digital variable capacitor  210 , and the lower 4 bits (D 3 , D 2 , D 1 , D 0 ) are provided to the second digital variable capacitor  220 . The upper 4 bits (D 7 , D 6 , D 5 , D 4 ) are inverted by inverters INV 5 , INV 6 , INV 7  and INV 8  before the upper 4 bits (D 7 , D 6 , D 5 , D 4 ) are output from the difference detection section  230 .  
         [0061]     The first digital variable capacitor  210  includes four capacitors C,  2 C,  4 C and Cd each of which is connected in series to nodes NB 3  and NB 4 . The capacitor C has a unit capacitance C, the capacitance of the capacitor  2 C is two times as large  10  as the unit capacitance C, and the capacitance of the capacitor  4 C is four times as large as the unit capacitance C. The capacitor Cd is a dummy capacitor, and the capacitance of the dummy capacitor Cd is the same as an equivalent capacitance of capacitors  8 C,  16 C,  32 C and  64 C, which are coupled in series to one another in the second variable capacitor  220 . A switching element ST 21  is connected in parallel to the capacitor C, a switching element ST 22  is connected in parallel to the capacitor  2 C, a switching element ST 23  is connected in parallel to the capacitor  4 C, and a switching element ST 24  is connected in parallel to the capacitor Cd. The switching element ST 24  is maintained in a turn-on state. The switching elements ST 21 , ST 22  and ST 23  are turned on in response to the inverted 3 bits {overscore (D 6 )}, {overscore (D 5 )} and {overscore (D 4 )}, respectively. As shown in  FIG. 7 , when a PMOS transistor is used as the switching elements (e.g., ST 21 -ST 24 ), a control electrode of the switching element ST 24  is connected to a low power source (VSS), for example, an earth potential.  
         [0062]     The second digital variable capacitor  220  includes the four capacitors  8 C,  16 C,  32 C and  64 C each of which is coupled in series to nodes NB 8  and NB 9 . The capacitance of the capacitor  8 C is eight times as large as the unit capacitance C, the capacitance of the capacitor  16 C is sixteen times as large as the unit capacitance C, and the capacitance of the capacitor  64 C is sixty four times as large as the unit capacitance C.  
         [0063]     A switching element ST 25  is connected in parallel to the capacitor  8 C, a switching element ST 26  is connected in parallel to the capacitor  16 C, a switching element ST 27  is connected in parallel to the capacitor  32 C, and a switching element ST 28  is connected in parallel to the capacitor  64 C. The switching elements ST 25 , ST 26 , ST 27  and ST 28  are turned on in response to the lower 4 bits D 3 , D 2 , D 1  and D 0 , respectively.  
         [0064]     In particular, the output capacitance of the first digital variable capacitor  210  has 8 coarse levels ( 0 ,  1 , . . . ,  7 ) according to the value of the  3  inverted bits {overscore (D 6 )}, {overscore (D 5 )} and {overscore (D 4 )}. The dummy capacitor Cd determines a difference between each of the coarse 8 levels. The output capacitance of the second digital variable capacitor  220  has 16 fine levels ( 0 ,  1 , . . . ,  15 ) according to the value of the 4 bits D 3 , D 2 , D 1  and D 0 . The capacitor  64 C determines the difference between each of the fine 16 levels.  
         [0065]     Therefore, a total equivalent capacitance Cx between nodes NB 1  and NB 5  varies according to the coarse 8 levels. In the coarse 8 levels, the dummy capacitor Cd is a unit capacitance. A total equivalent capacitance Cy between a node NB 6  and the node NB 1  varies according to the fine 16 levels. In the fine 16 levels, the capacitor  64 C is a unit capacitance.  
         [0066]     For example, when the capacitors C 1  and C 2  are respectively 1 μF, and the capacitor C is 22.5 μF, the difference capacitance in the coarse 8 levels varies by about 11 μF, and the difference capacitance in the fine 16 levels varies by about 0.7 μF. Therefore, the total difference capacitance Lc varies linearly according to 127 levels.  
         [0067]     As shown in  FIGS. 6 and 7 , the first digital variable capacitor  210  includes switching circuits  212  and  214 , and the second digital variable capacitor  220  includes switching circuits  222  and  224 .  
         [0068]     In the switching circuit  212 , a switching element ST 29  is connected between a node NB 2  and the node NB 3 , and a switching element ST 30  is connected between a node NB 7  and the node NB 8 . The switching element ST 29  is switched by the upper most bit D 7 , and the switching element ST 30  is switched by the inverted upper most bit {overscore (D 7 )}. In the switching circuit  214 , a switching element ST 31  is connected between nodes NB 4  and NB 5 , and a switching element ST 32  is connected between the node NB 4  and a node NB 10 . The switching element ST 31  is switched by the upper most bit D 7 , and the switching element ST 32  is switched by the inverted upper most bit {overscore (D 7 )}.  
         [0069]     In the switching circuit  222 , a switching element ST 33  is connected between a node NB 2  and the node NB 8 , and a switching element ST 34  is connected between a is node NB 7  and the node NB 8 . The switching element ST 33  is switched by the inverted upper most bit {overscore (D 7 )}, and the switching element ST 34  is switched by the upper most bit D 7 . In the switching circuit  224 , a switching element ST 35  is connected between the nodes NB 9  and NB 5 , and a switching element ST 36  is connected between the node NB 9  and a node NB 10 . The switching element ST 35  is switched by the inverted upper most bit {overscore (D 7 )}, and the switching element ST 36  is switched by the upper most bit D 7 .  
         [0070]     When the switching elements ST 29 , ST 30 , . . . , ST 36  are PMOS transistors and D 7  has a logic value of ‘0’, the switching elements ST 29 , ST 31 , ST 34  and ST 36  are turned on and the switching elements ST 30 , ST 32 , ST 33  and ST 35  are turned off. Accordingly, the first digital variable capacitor  210  is connected to the nodes NB 2  and NB 5  via the switching elements ST 29  and ST 31 , and the second digital variable capacitor  220  is connected to the nodes NB 7  and NB 10  via the switching elements ST 34  and ST 36 .  
         [0071]     When D 7  has logic value of ‘1’, the switching elements ST 29 , ST 31 , ST 34  and ST 36  are turned off and the switching elements ST 30 , ST 32 , ST 33  and ST 35  are turned on. Accordingly, the first digital variable capacitor  210  is connected to the nodes NB 7  and NB 10  via the switching elements ST 30  and ST 32 , and the second digital variable capacitor  220  is connected to the nodes NB 2  and NB 5  via the switching elements ST 33  and ST 35 .  
         [0072]     According to the switching circuits  212 ,  214 ,  222  and  224 , the first digital variable capacitor  210  is electrically connected in series to not only the capacitor C 1  but also the capacitor C 2 , and the second digital variable capacitor  220  is electrically connected in series to not only the capacitor C 2  but also the capacitor C 1 .  
         [0073]     The total difference resistance Ac is regulated to vary from a −127 level to +127 level according to the 8 bit control signal (D 0 , D 1 , . . . , D 7 ).  
         [0074]     The difference detection section  230  includes first and second capacitance measuring sections  232  and  234 , a difference obtaining section  236  and a look-up table  238 . The first capacitance measuring section  232  measures the capacitance of the capacitor C 1 , and the second capacitance measuring section  234  measures the capacitance of the capacitor C 2 .  
         [0075]     The measured capacitance is provided to the difference obtaining section  236 . The difference obtaining section  236  obtains a difference value (or declination or variation) between the measured capacitance of the capacitor C 1  and the measured capacitance of the capacitor C 2 , and generates digital data corresponding to the difference value. The digital data is represented in an address of the look-up table  238 , and the 8 bit control signal corresponding to the address designated by the digital data is provided to the first and second digital variable capacitors  210  and  220 .  
         [0076]      FIG. 8  is a block diagram showing a frequency mixer  300  (or a circuit for mixing frequencies) according to yet another exemplary embodiment of the present invention.  FIG. 9  is a block diagram showing a variant of a difference compensation circuit  320  of  FIG. 8 . Referring to  FIGS. 8 and 9 , the frequency mixer  300  includes a mixer circuit  310  and the difference compensation circuit  320 . The mixer circuit  310  includes a differential input circuit  312  and a driving circuit  314 .  
         [0077]     The differential input circuit  312  receives two RF signals (RF + , RF − ) through differential input terminals, respectively, and amplifies the two RF signals (RF + , RF − ). The driving circuit  314  mixes the amplified RF signals with local oscillating signals (LO + , LO − ) and outputs intermediate frequency (IF) signals (IF + , IF − ) to output nodes NO 1  and NO 2 . For example, the mixer circuit  310  includes an active balanced mixer such as a Gilbert mixer, folded cascade mixer, harmonic mixer and double balanced harmonic mixer, etc.  
         [0078]     As shown in  FIG. 8 , a pull-up resistor R 1  is connected between the output is node NO 1  and a high power source VCC, and a pull-up resistor R 2  is connected between the output node NO 2  and the high power source VCC. The difference compensation circuit  320  is connected between the pull-up resistors R 1  and R 2  and, compensates for a declination of balanced resistive elements (e.g., the pull-up resistors R 1  and R 2 ). In other words, the difference compensation circuit  320  compensates for the difference between the resistance measured at the pull-up resistors R 1  and R 2 , so that a direct current (DC) offset between the output nodes NO 1  and NO 2  is removed or reduced significantly.  
         [0079]     Referring to  FIG. 9 , the difference compensation circuit  320  includes a comparator  321 , an analog-to-digital converter (ADC)  322 , a-look-up table (LUT)  323 , a first digital variable resistor  324  and a second digital variable resistor  325 . First and second switching elements SW 1  and SW 2  are connected to a non-inverting terminal (+) and an inverting terminal (−) of the comparator  321 , respectively. The first and second switching elements SW 1  and SW 2  are switched in response to an enable signal (EN).  
         [0080]     The comparator  321  detects a voltage difference between the output nodes NO 1  and NO 2  when the switching elements SW 1  and SW 2  are turned on. The ADC  322  converts the voltage difference into digital data. The digital data is represented in addresses of the look-up table  323 . The look-up table  323  generates a control signal for compensating for the declination of balanced resistive elements (e.g., the pull-up resistors R 1  and R 2 ) in response to the digital data. The most significant bit (MSB) or sign bit, and 3 upper bits of the 8 bit control signal are provided to the first digital variable resistor  324 , and the MSB and 4 lower bits of the 8 bit control signal are provided to the second digital variable resistor  325 .  
         [0081]     Therefore, the digital variable resistors  324  and  325  compensate for the declination of balanced resistive elements in response to the 8 bit control signal, so that the voltage difference between the output nodes NO 1  and NO 2  is maintained at zero when in a balanced condition of the mixer circuit  310 .  
         [0082]     When the compensation operation is completed, the switching elements SW 1  and SW 2  are turned off, and the resistance compensated by the digital variable resistors  324  and  325  are maintained. It is to be understood that the difference compensation circuit  320  compensates for not only the resistance difference between the pull-up resistors R 1  and R 2  but also for the DC offset of the mixer circuit  310 .  
         [0083]      FIG. 10  is a block diagram showing another variant of the difference compensation circuit  320  of  FIG. 8 . Referring to  FIG. 10 , a user, such as a system designer or hardware developer, measures the DC offset of the mixer circuit  310 , and sets a control code value based on the measured result to compensate for the impedance difference. The difference compensation circuit  320  includes the first digital variable resistor  324 , the second digital variable resistor  325  and a user interface  326 , the analog-to-digital converter (ADC)  322  and the look-up table  323 .  
         [0084]     In an alternative variant of the present invention, a frequency mixer may be formed on a semiconductor substrate such as a silicon (Si) substrate, silicon-germanium (Si—Ge) substrate, gallium-arsenide (GaAs) substrate or an indium-phosphorous substrate using a bipolar junction transistor (BJT), metallic oxide semiconductor (MOS), complementary metallic oxide semiconductor (CMOS), a bipolar-CMOS (Bi—CMOS), heterojunction bipolar transistor (HBT), metal  10  semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) design technologies.  
         [0085]     In yet another alternative variant of the present invention, the difference compensation circuit and frequency mixer may be incorporated into a portable communications device such as an RF transmitter-receiver of a mobile phone, a personal communications service (PCS) phone, a wireless local area network (LAN) transmitter-receiver, etc. Particularly, the difference compensation circuit and the frequency mixer may be incorporated in a DCR of a 900 Mhz mobile phone using a global system for mobile communication (GSM) technology and 1,800 Mhz or 1900 Mhz PCS phones.  
         [0086]     In another alternative variant of the present invention, the difference compensation circuit may be incorporated in the active balanced mixer of the DCR. Therefore, IMD2 distortion due to the non-linear properties of the devices in the difference compensation circuit such as a mixer may be removed, the linearity of the circuit may be enhanced, and the receiver may effectively receive input signals.  
         [0087]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it should be understood by those of ordinary skill in the art that various changes, substitutions and alterations can be made herein without departing from the scope of the invention as defined by appended claims and their equivalents.