Abstract:
A processing system capable of downloading and executing firmware at the same time, and from multiple storages, is disclosed. The processing system includes a first storage unit for storing firmware; a second storage unit for storing frequently accessed firmware, the second storage unit having a higher operating speed than the first storage unit; a download unit for downloading firmware from the first storage unit to the second storage unit; an execution unit for executing firmware from the first storage unit or the second storage unit; and a processor for controlling the download unit and execution unit to operate concurrently.

Description:
BACKGROUND  
       [0001]     As computer technology develops, the speed of processors also increases. Many modern processors utilize a parallel FLASH memory, which has a relatively high operating speed but requires many pins for the necessary connections, thereby increasing the cost of the processing unit design. Serial FLASH needs very few pins to transmit the data in some kind of serial form, but with a lower bandwidth compared to that of a parallel FLASH. Conventional processors download the whole firmware from the serial flash to a DRAM before the system starts up. However, large firmware will require a large DRAM space. Lowering the cost and complexity of the processing unit while maintaining a fast operational speed therefore becomes an important issue for the manufacturers.  
       SUMMARY  
       [0002]     It is therefore one of the objectives of the present invention to provide a processing system that utilizes a serial FLASH memory, while maintaining a high operational speed.  
         [0003]     To achieve this aim, the processing system includes a download unit and an execution unit that can be operated by a processor concurrently.  
         [0004]     Briefly described, the processing system comprises: a first storage unit for storing firmware; a second storage unit for storing frequently accessed firmware; a download unit for downloading firmware from the first storage unit to the second storage unit; an execution unit for executing firmware from the first storage unit or the second storage unit; and a processor for controlling the download unit and execution unit to operate concurrently.  
         [0005]     A method is also disclosed for downloading and executing firmware, the method comprising: storing firmware in a first storage unit; downloading firmware from the first storage unit to a second storage unit; selectively executing firmware from the second storage unit or executing firmware from the first storage unit; and controlling the download process and the execution process to operate concurrently.  
         [0006]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0007]      FIG. 1  is a diagram of a processing system according to a first embodiment of the present invention.  
         [0008]      FIG. 2  is a diagram of a processing system according to a second embodiment of the present invention.  
         [0009]      FIG. 3  is a first diagram of look-up tables utilized for assigning memory space to downloaded firmware.  
         [0010]      FIG. 4  is a second diagram of look-up tables utilized for assigning memory space to downloaded firmware. 
     
    
     DETAILED DESCRIPTION  
       [0011]     Please refer to  FIG. 1 .  FIG. 1  is a diagram of a processing system  10  according to a first embodiment of the present invention. The processing system  10  comprises a processor  12 ; an execution unit  14 , further comprising a cache  15 ; a download unit  16 ; a first storage unit  18 ; and a second storage unit  19  having a faster access speed than the first storage unit  18 . In this embodiment the first storage unit  18  is implemented by a serial FLASH memory, and the second storage unit  19  is implemented by a DRAM. Please note this is merely an embodiment of the present invention, and other kinds of memories can be utilized. For example, in other embodiments, the second storage unit  19  is implemented by an SRAM instead of a DRAM. The serial FLASH memory  18  contains all of the firmware required by the processor  12 , whereas firmware frequently executed by the processor  12  will be downloaded to the faster DRAM  19 . The download process will be described herein, with reference to the path numerals detailed in  FIG. 1 . Initially the processor  12  sends a download request, containing an address of required firmware, to the download unit  16  (path a 1 ). The download unit  16  reads the requested firmware from the serial FLASH  18  (path a 2 ) and writes it to the DRAM  19  (path a 3 ), then sends a notification signal to the processor  12  once the download process is complete (path a 4 ).  
         [0012]     The execution process will now be detailed. The processor  12  sends an address of required firmware to the execution unit  14  (path b 1 ), which then searches the download unit  16  to determine if the requested firmware is located in the FLASH  18  or the DRAM  19  (path b 2 ). Once the location is determined, the execution unit  14  sets an instruction path to the storage unit containing the requested firmware, fetches the desired firmware and writes it to the cache  15  (paths b 3 /b 4 ). The processor  12  then fetches the instructions buffered in the cache  15  of the execution unit  14  (path b 5 ).  
         [0013]     The utilization of a separate execution unit  14  and download unit  16  allows the processor  12  to control these units to operate concurrently. The separation of the download unit  16  and execution unit  14  means separate, independent download and execution paths exist in the processing system  10 . As the units can work at the same time, firmware can be downloaded from the first storage unit  18  to the second storage unit  19  by the download unit  16  at the same time as other firmware is executed by the execution unit  14 . The execution unit  14  can access either storage unit by switching an instruction path to the storage units, according to information supplied by the download unit  16 , and the download process can be carried out at the same time.  
         [0014]     In an event where the execution unit  14  and the download unit  16  wish to access the same storage unit simultaneously, the present invention discloses using arbitration units, connected to each storage unit, for buffering read and write requests. Please refer to  FIG. 2 .  FIG. 2  is a diagram of a processing system  20  according to a second embodiment of the present invention. The configuration of the processing system  20  shown in  FIG. 2  is similar to that of the processing system  10  shown in  FIG. 1 . The key difference is that the second embodiment contains two arbitration units  23 ,  27  connected between the second storage unit (i.e. the DRAM)  29  and the execution unit  24 , and the first storage unit (i.e. the FLASH memory)  28  and the download unit  26  respectively. In this embodiment the arbitration units  23 ,  27  are implemented by buffers. It should be noted that the components of the same name have the same functionality and operation, and further description is therefore omitted for brevity. The processor  22  may send many download and execution commands at the same time. The arbitration units  23 ,  27  can prioritize the commands by buffering all commands and sending them to the DRAM  29  and FLASH  28  respectively, according to a queue dictated by the processor  22 . Please note that although buffers are utilized as the arbitration units in this embodiment, any storage units that fulfill the function of organizing read and write requests into a priority queue can be utilized. That is, other circuits could be utilized to achieve the same objective of arbitrating access of a target storage unit.  
         [0015]     To further increase the capacity of the above processing systems  10 ,  20 , discontinuous firmware, i.e. randomly stored firmware, downloaded from the serial FLASH memory  18 ,  28  to the DRAM  28 ,  29  will be stored in the DRAM  28 ,  29  in continuous space. Please refer to  FIG. 3 .  FIG. 3  is a diagram of look-up tables utilized for assigning memory space to downloaded firmware. The processing system  10 ,  20  maintains three look-up tables (LUTs) in the download unit  16 ,  26 ; an access map  31 , a download map  32 , and an address index table  33 . The access map  31  indicates which banks in the serial FLASH memory  18 ,  28  have been downloaded to the DRAM  19 ,  29 . Please note that a boot code is commonly stored in the beginning of the FLASH memory  18 ,  28 . In this embodiment, occupied banks are assigned a ‘1’ and unoccupied banks are assigned a ‘0’. The download map  32  indicates which banks in the FLASH memory  18 ,  28  are waiting to be downloaded to the DRAM  19 ,  29 , by assigning said banks a ‘1’. In  FIG. 3 , it can be seen that bank  3  and bank  6  of the FLASH memory  18 ,  28  will be downloaded. As these banks are discontinuous they would conventionally be stored in discontinuous addresses. The present invention utilizes the address index table  33  to assign them to continuous DRAM space. The download unit  16 ,  26  compares the address index table  33  with the access map  31 . As can be seen from  FIG. 3 , firmware from the serial FLASH memory  18 ,  28  has already been downloaded to banks  0 ,  1  and  2  in the DRAM  19 ,  29 , so the two units to be downloaded are assigned to bank addresses  3  and  4  respectively. After the firmware has been downloaded to the DRAM  19 ,  29 , the access map  31  will be updated by assigning the downloaded banks in the FLASH memory  18 ,  28  with a ‘1’. As shown in  FIG. 4 , the access map  31  and the download map  32  have been updated accordingly.  
         [0016]     Please note that the utilization of two storage units is simply an embodiment of the present invention and should not be taken as a limitation. More than one execution unit and download unit respectively can be utilized in the claimed processing system, and more than two storage units may also be utilized. These changes still obey the spirit of the present invention.  
         [0017]     Please note that the above description utilizes a serial FLASH and a DRAM to illustrate the working of the claimed processing system. These storage units, however, are merely illustrations of the claimed invention and should not be taken as limitations. Any combination of storages may be utilized; these changes also obey the spirit of the present invention.  
         [0018]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.