Abstract:
High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on” resistance of the device.

Description:
RELATED APPLICATION  
       [0001]     This Application claims priority to U.S. Provisional Application Ser. No. 60/753,550, Attorney Docket VISH-8756.PRO, entitled “High Mobility P-Channel Trench Power Metal-Oxide Semiconductor Field Effect Transistors,” filed Dec. 22, 2005, to Pattanayak et al., which is hereby incorporated by reference herein in its entirety. 
     
    
     FIELD OF INVENTION  
       [0002]     Embodiments of the present invention relate to the design and fabrication of semiconductors. More specifically, embodiments of the present invention relate to systems and methods for high mobility power metal-oxide semiconductor field effect transistors.  
       BACKGROUND  
       [0003]     The on-state (or “on”) resistance of a MOSFET (metal-oxide semiconductor field-effect transistor) device is an important figure of merit, especially for power devices. For example, when such a device is on, or conducting, a portion of the system power is lost due to resistance heating in the device. This leads to deleteriously decreased efficiency. Such resistance heating may also lead to heat dissipation problems, which in turn may lead to system overheating and/or decreased reliability. Consequently, devices with low on resistances are much desired.  
         [0004]     The on resistance of a MOSFET (metal-oxide semiconductor field-effect transistor) device comprises mostly resistance of the channel, the drift layer and the substrate components. For low voltage MOSFETs, the channel resistance component provides a dominant contribution. The channel resistance is inversely proportional to the mobility of the carriers in the channel. In Silicon, the mobility of the carriers in the channel depends upon the crystal plane and the direction of current flow and this dependence is different for different types of carriers, e.g., electrons versus holes.  
         [0005]     MOSFETs may be fabricated in crystalline Silicon. Geometry related to a crystal lattice is generally described in terms of the Miller index, which references the crystallographic axes of a crystal, e.g., a, b and c. As a crystal is periodic, there exist families of equivalent directions and planes. Herein, a plane, e.g., a surface of a wafer sliced from a crystal ingot, is described enclosed within parenthesis, e.g., (abc). This notation describes the (abc) plane and equivalent planes. Directions relative to the crystal lattice are described enclosed within brackets, e.g., [abc]. This notation describes the [abc] direction and equivalent directions.  
         [0006]     The mobility of electrons in Silicon is known to be the maximum in the (100) crystalline plane and is weakly dependent on the direction of the current flow. In contrast, the mobility of holes is a strong function of both the orientation of the crystalline plane and the direction of the current flow. The mobility of the holes is maximum in the (110) crystalline plane and in the [110] direction.  
         [0007]     It has been known for quite some time that the mobility of holes in the (110) crystalline plane depends on the direction of current flow being maximum in the [110] direction (D. Colman et al., Journal of Applied Physics, pp. 1923-1931, 1968). Their experimental results are shown in the graph of  FIG. 1  (conventional art). From the graph of  FIG. 1 , it is evident that compared to the conventional (100) orientation, the hole mobilities in the (110) crystalline plane are increased by more than a factor of two, depending upon the gate bias.  
         [0008]     Plummer et al. have also reported (1980 IEDM, pp. 104-106) that a trench power MOSFET fabricated on (100) wafers with trench side walls parallel to the (110) crystalline planes do exhibit higher hole mobility at higher gate voltages than corresponding trench MOSFETs with trench walls parallel to the (110) plane but with the direction of current flow being also in the [100] direction.  
         [0009]     More recently, various authors have reiterated that the hole mobility is highest in the (110) plane and in the [110] direction (H. Irie et al., IEDM, pp. 225-228, 2004 and references therein). A patent for a trench lateral device has also been granted to Wendell P. Noble et al. (U.S. Pat. No. 6,580,154, issued Jun. 17, 2003).  
         [0010]     However, conventional P-channel trench MOSFET devices are fabricated such that the holes flow in an inversion channel which is along the (100) crystalline plane and the direction of the current flow is in the [100] direction.  
       SUMMARY OF THE INVENTION  
       [0011]     Therefore there exists a need for a power MOSFET device with reduced on resistance. What is additionally needed is a system and method for a P-Channel Trench Power MOSFET in which the holes are confined to the (110) plane and flow in the [110] direction. A further need exists for systems and methods for power MOSFETs that are compatible and complementary with existing systems and methods of semiconductor design and manufacturing. Embodiments of the present invention provide these advantages.  
         [0012]     High mobility P-channel power metal oxide semiconductor field effect transistors are disclosed. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, and the current flow is in the [110] direction when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on” resistance of the device.  
         [0013]     In accordance with still another embodiment of the present invention, a power MOSFET structure includes a gate and a source. The power MOSFET further includes an inversion/accumulation channel, wherein holes flow in said inversion/accumulation channel. The channel is aligned along a (110) crystalline plane and the current flow is in a [110] direction when a negative potential is applied to said gate with respect to said source.  
         [0014]     Alternative embodiments are directed to a vertical trench MOSFET wherein hole current is restricted to flow in a (110) plane and in a direction selected from the group comprising [110], [111], [112], [001] and their equivalents. The vertical trench MOSFET may be fabricated in a (110) wafer. The vertical trench MOSFET may operate wherein said hole current is responsive to applying a negative voltage potential to a gate of said MOSFET device with respect to a source of said MOSFET.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Unless otherwise noted, the drawings are not drawn to scale.  
         [0016]      FIG. 1  illustrates experimental measurements of hole mobility based on crystalline plane orientation.  
         [0017]      FIG. 2  illustrates a conventional wafer that is used to fabricate conventional P channel trench Power MOSFETs.  
         [0018]      FIGS. 3, 4 ,  5 ,  6  and  7  illustrate formation of trenches in a variety of different trench rotations.  
         [0019]      FIGS. 8A, 8B ,  8 C and  8 D illustrate (110) wafers with a variety of flats, in accordance with embodiments of the present invention.  
         [0020]      FIG. 9  illustrates etched trenches perpendicular to the flat of wafer, in accordance with embodiments of the present invention.  
         [0021]      FIG. 10  illustrates etched trenches that are both parallel and perpendicular to the flat of wafer, in accordance with embodiments of the present invention.  
         [0022]      FIG. 11  illustrates a schematic diagram of a trench MOSFET structure, in accordance with embodiments of the present invention.  
         [0023]      FIG. 12  illustrates a schematic diagram of a vertical double diffused planar gate p channel MOSFET structure (DMOSFET), in accordance with embodiments of the present invention.  
         [0024]      FIG. 13  illustrates a schematic drawing of a high mobility P channel trench MOSFET device, in accordance with embodiments of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0025]     Reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it is understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be recognized by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention.  
       High Mobility P-Channel Trench Power Metal-Oxide Semiconductor Field-Effect Transistors  
       [0026]      FIG. 2  illustrates a conventional wafer  200  that may be used to fabricate conventional P channel trench Power MOSFETs. Wafer  200  is described as a (001) wafer with a (001) flat. Wafer  200  may also be described as having a flat in the &lt;010&gt; direction. The top surface of wafer  200  is a (100) plane. It is to be appreciated that the current flow direction in trench MOSFETs, where the current flow is from the top surface to the bottom surface of a wafer, e.g., wafer  200 , will always be in the [100] direction, e.g., into the plane of the drawing, as illustrated in  FIG. 2 .  
         [0027]      FIGS. 3, 4 ,  5 ,  6  and  7  illustrate formation of trenches in a variety of different trench rotations.  FIG. 3  illustrates a closed cell trench structure  300 . The vertical  310  and horizontal  320  trenches are bounded by equivalent (100) planes.  
         [0028]      FIG. 4  illustrates a closed cell trench structure  400  formed with a 45 degree rotation. The rotated trenches  410  and  420  are bounded by equivalent (110) planes.  
         [0029]      FIG. 5  illustrates a stripe cell trench structure  500 . The vertical trenches  510  are bounded by equivalent (100) planes.  
         [0030]      FIG. 6  illustrates a stripe cell trench structure  600  formed with a 45 degree rotation. The rotated trenches  610  are bounded by equivalent (110) planes.  
         [0031]      FIG. 7  illustrates a stripe cell trench structure  700  formed with a −45 degree rotation. The rotated trenches  710  are bounded by equivalent (110) planes.  
         [0032]     Experimental examples of die comprising stripe cell trench structure  500  of  FIG. 5  and die comprising trench structure  600  formed with a 45 degree rotation of  FIG. 5  have been fabricated. Preliminary analysis shows that the overall resistance of the rotated trench structure  600  formed with a 45 degree rotation, e.g., when the current flow is in the (110) plane, is lower than the conventional art devices with trenches in the (100) planes.  
         [0033]     However, it is to be appreciated that, although current flow may be aligned with a (110) plane of wafer  200 , trench current flow is in the [100] direction, as described previously.  
         [0034]      FIGS. 8A, 8B ,  8 C and  8 D illustrate (110) wafers with a variety of flats, in accordance with embodiments of the present invention. It is to be appreciated that other flats are well suited to embodiments in accordance with the present invention. Wafer  800  of  FIG. 8A  is described as a (110) wafer with a (110) flat. A variety of crystalline orientations are illustrated, including [001], [111], and [110] to enable etching trenches with planes parallel to (001), (111) and (110) Equivalent Surfaces of the Silicon crystal respectively.  
         [0035]     Wafer  810  of  FIG. 8B  is described as a (110) wafer with a [111] directed flat to enable etching trenches perpendicular to the flat so that the trench will have its surfaces bounded by {111} equivalent planes. The [111] crystalline direction is illustrated. Wafer  820  of  FIG. 8C  is described as a (110) wafer with a [001] directed flat.  
         [0036]     Wafer  830  of  FIG. 8D  is described as a (110) wafer with a [112] directed flat.  
         [0037]     In accordance with embodiments of the present invention, a trench MOSFET formed in wafer  800  ( FIG. 8A ) will have hole current flow in the (110) plane and in the [110] direction. For example, the current flow from the top surface to the bottom surface will be in the [110] direction, e.g., into the plane of the drawing, as illustrated in  FIG. 8A .  
         [0038]     In accordance with other embodiments of the present invention, a trench MOSFET formed in wafer  810  ( FIG. 8B ) will have hole current flow in the (110) plane and in the [111] direction.  
         [0039]     In accordance with alternative embodiments of the present invention, a trench MOSFET formed in wafer  820  ( FIG. 8C ) will have hole current flow in the (110) plane and in the [001] direction.  
         [0040]     In accordance with still other embodiments of the present invention, a trench MOSFET formed in wafer  830  ( FIG. 8D ) will have hole current flow in the (110) plane and in the [112] direction.  
         [0041]      FIG. 9  illustrates etched trenches  900  perpendicular to the flat of wafer  800  ( FIG. 8A ), in accordance with embodiments of the present invention. It is appreciated that trenches  900  are in (110) or equivalent planes. As the wafer surface is (110) plane, the direction of hole current flow is thus also in the [110] direction. It is appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in  FIGS. 8B, 8C  and/or  8 D.  
         [0042]      FIG. 10  illustrates etched trenches  1000  that are both parallel and perpendicular to the flat of wafer  800  ( FIG. 8A ), in accordance with embodiments of the present invention. It is appreciated that trenches  1000  are in (110) or equivalent planes. As the wafer surface is (110) plane, the direction of hole current flow is thus also in the [110] direction. It is appreciated that embodiments of the present invention are well suited to trenches formed relative to other flat orientations, e.g., as illustrated in  FIGS. 8B, 8C  and/or  8 D.  
         [0043]      FIG. 11  illustrates a schematic diagram of a trench MOSFET structure  1100 , in accordance with embodiments of the present invention. Trench MOSFET structure  1100  comprises a P+ source  1110 , an N body  1130  and a P+ drain  1120 . Trench MOSFET structure  1100  may be formed in and on wafer  800  ( FIG. 8A ), to provide a desirable orientation for hole current flow. The crystalline plane directions of trench MOSFET structure  1100  are illustrated in  FIG. 11 . It is to be appreciated that current flow between the source  1110  and drain  1120  of trench MOSFET structure  1100  is in the [110] (or equivalent) direction. It is to be appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in  FIGS. 8B, 8C  and/or  8 D.  
         [0044]      FIG. 12  illustrates a schematic diagram of vertical double diffused MOSFET with a planar gate (DMOSFET) P channel structure  1200 , in accordance with embodiments of the present invention. DMOSFET P channel structure  1200  comprises a P+ source  1210 , an N body  1230  and a P+ drain  1220 . DMOSFET P channel structure  1200  may be formed in and on wafer  800  ( FIG. 8A ), to provide a desirable orientation for hole current flow. The crystalline plane directions of DMOSFET P channel structure  1200  are illustrated in  FIG. 12 . It is to be appreciated that current flow between the source  1210  and drain  1220  of DMOSFET P channel structure  1200  is in the [110] direction. It is appreciated that embodiments of the present invention are well suited to channel alignment perpendicular to other flat orientations, e.g., as illustrated in  FIGS. 8B, 8C  and/or  8 D.  
         [0045]     It is appreciated that oxide growth rates are different in different crystalline planes. For example, oxide generally grows faster in the [110] direction compared to in the [100] direction. The surface charge in the (110) plane is about twice that in the ( 100 ) plane. It is desirable to take these characteristics into account while designing for required threshold voltage of the high mobility MOSFETs.  
         [0046]      FIG. 13  illustrates a schematic drawing of a high mobility P channel accumulation trench MOSFET  1300 , in accordance with embodiments of the present invention. Trench MOSFET  1300  comprises source metal  1310 , an insulator  1320 , P+ source regions  1330  and an N body  1340 . Trench MOSFET  1300  also comprises a polysilicon gate  1350 , gate oxide  1390  and a P− drift region  1360 . Trench MOSFET  1300  further comprises a substrate  1370  and drain metallization  1380 .  
         [0047]     It is to be appreciated that trench MOSFET  1300  is fabricated in a [110] direction, as indicated in  FIG. 13 . In accordance with embodiments of the present invention, trench MOSFET  1300  may be formed perpendicular to a (110) flat. It is appreciated that embodiments of the present invention are well suited to trenches formed perpendicular to other flat orientations, e.g., as illustrated in  FIGS. 8B, 8C  and/or  8 D.  
         [0048]     During current conduction, trench MOSFET  1300  inverts the channel (N body  1340 ) and accumulates charge in the lightly doped accumulation region (P− drift region  1360 ) forming a P+ accumulation layer near gate  1350 . Hence, current flows in an inversion layer within N body  1340  as well as within the accumulation layer formed next to gate  1350 .  
         [0049]     The breakdown voltage is supported at the P N junction extending into the drift region. However, unlike the conventional trench MOSFET, the drift resistance consists of two parallel components: one is the accumulation region resistance and the other is the resistance of the drift region. The accumulation resistance component is less than that of the drift region resistance. In accordance with embodiments of the present invention, the overall resistance of the drift region will be substantially reduced from the corresponding values for conventional accumulation power MOSFET devices due to the current flow being in a (110) plane and a [110] direction.  
         [0050]     In this novel MOSFET design, by fabricating a MOSFET with the plane of the accumulation layer as (110), and direction of accumulation layer as [110], the accumulation layer resistance will be greatly reduced, e.g., by a factor of about two.  
         [0051]     Embodiments in accordance with the present invention provide a system and method for a power MOSFET device with reduced on resistance. Embodiments in accordance with the present invention also provide for systems and methods for a P-Channel Trench Power MOSFET in which the holes are confined to the (110) plane and flow in the [110] direction. Further, embodiments in accordance with the present invention provide for systems and methods for power MOSFETs that are compatible and complementary with existing systems and methods of semiconductor design and manufacturing.  
         [0052]     Various embodiments of the invention, high mobility P-channel power metal oxide semiconductor field effect transistors, are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the invention should not be construed as limited by such embodiments, but rather construed according to the below claims.