Abstract:
A frequency synthesizer includes a phase locked loop (PLL) for generating a desired frequency. The PLL includes two loop filters. A characterization circuit is included, which is configured to receive a digital word for characterizing the PLL and provide a pre-charge value for pre-charging one of the loop filters to generate the desired frequency. A successive approximation analog to digital (A/D) converter is coupled between the loop filters and the characterization circuit, for providing both (a) the digital word to the characterization circuit, and (b) the pre-charge value to the selected loop filter. The digital word includes n-bits ranging in values from a most significant bit (MSB) to a least significant bit (LSB), and the pre-charge value is formed by the n-bits. The successive approximation A/D converter includes a successive approximation register (SAR) for forming the digital word, and a digital to analog (D/A) converter for forming the pre-charge value. The successive approximation A/D converter includes a comparator for comparing (a) a value corresponding to a loop filter voltage with (b) an analog value formed by a bit of the digital word.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates, generally, to frequency synthesizers. More particularly, the present invention relates to systems and methods for characterizing a synthesizer in real-time and pre-positioning the synthesizer to a new frequency to reduce settling time. 
       BACKGROUND OF THE INVENTION 
       [0002]    The use of fast hopping frequency synthesizers is well known in the art for applications such as frequency hopping spread spectrum (FHSS) transmitters and receivers. In most transceivers, the synthesized frequency source (i.e. the local oscillator (LO)) is used to create the carrier signal in the transmitter and to down convert the signal in the receiver. 
         [0003]    Local oscillator signals are normally generated using a phase locked loop (PLL) coupled to a crystal oscillator that provides the frequency reference. The loop bandwidth of the PLL determines its settling rate, as well as some of the phase noise properties of the generated local oscillator signal. The underlying trade off is that lower loop bandwidths may provide lower phase noise by better rejecting the high frequency phase noise of the PLL oscillator, but at a cost of longer settling times. 
         [0004]    Some frequency synthesizers rely on a programmable PLL to control a voltage controlled oscillator (VCO) that produces desired output frequencies. A conventional, non-prepositioned PLL-type frequency synthesizer includes a phase comparator, a loop filter, a VCO, and a frequency divider all arranged in a loop, and a reference frequency source. Such an arrangement is shown in  FIG. 1 , which is also disclosed in U.S. Pat. No. 4,511,858, issued to Charavit et al. on Apr. 16, 1985. 
         [0005]    As disclosed therein, frequency synthesizer  7  includes voltage-controlled oscillator (VCO)  1  for delivering an output frequency f N  which is dependent on the control voltage V N  applied thereto. The output of VCO  1  is connected to a frequency-divider circuit  2  which delivers an output signal at the frequency f N /N applied to phase comparator  3  to which is also applied a reference frequency free Phase comparator  3  delivers a signal whose average component is proportional to the phase difference existing between the two input signals applied to phase comparator  3 . A low-pass filter  4  is connected to the output of comparator  3  for removing high frequency components of the spectrum of the output signal of the phase comparator. Finally, optional amplifier  5  is placed between filter  4  and VCO  1  in order to provide the loop gain and buffering of the phase control loop of synthesizer  7 . 
         [0006]    Since the switching time of synthesizer  7  is inversely proportional to the bandwidth of the loop, the switching time is preferably reduced by increasing the bandwidth. 
         [0007]    A method for increasing the bandwidth may be provided by use of frequency pre-positioning, an example of which is shown by frequency synthesizer  12  in  FIG. 2  (also disclosed by Charavit et al.). Frequency synthesizer  12  includes VCO  1 , divider circuit  2  for dividing the output frequency f N  which is controlled by control device  11 , phase comparator  3  and frequency discriminator  6 . 
         [0008]    The frequency discriminator delivers a voltage proportional to the difference in frequencies applied as inputs to frequency discriminator  6 . When the compared frequencies are identical, the discriminator does not deliver a control voltage. Rather, the control voltage is delivered by phase comparator  3 . A summing amplifier  7  receives the signals from comparator  3  and discriminator  6  and delivers a signal which is filtered by low-pass filter  8 . 
         [0009]    In order to minimize the frequency deviation to be compensated by the control loop after a frequency switchover, pre-positioning voltage generator  9  is added to the loop in such a manner, as to position the VCO  1  as close as possible to the frequency to be delivered at the time of the frequency switchover. The frequency-switching control device  11  produces action both on divider circuit  2  and on voltage generator  9 . Voltage generator  9  delivers a voltage V NP  which, combined by summing circuit  10  with the voltage V NE  delivered by filter  8 , constitutes the control voltage V N  of VCO  1 . 
         [0010]    Disadvantages of frequency synthesizer  12  are that it does not provide a high accuracy of positioning the output frequency of the synthesizer and does not provide a high rate of stabilizing (settling) the output frequency. 
         [0011]    Referring next to  FIG. 3 , there is shown pre-positioned frequency synthesizer  80  disclosed in U.S. Pat. No. 6,714,085, issued on Mar. 30, 2004 to Bruce Alan Fette. Synthesizer  80  includes a reference frequency signal source  12  from which a reference signal  14  oscillating at a reference frequency is supplied. Reference frequency signal source  12  couples to a reference frequency divider  16 . Frequency divider  16  is configured to produce a divided reference signal  18  oscillating at the reference frequency divided by M. Divided reference signal  18  couples to a first input of phase comparator  20 . An output of phase comparator  20  provides a phase-error signal  22  and couples to an input of loop filter  24 , which is configured to influence the bandwidth of phase-locked loop (PLL)  26 . 
         [0012]    As shown, the loop filter includes resistor  28  and capacitor  30  coupled to ground reference  34 . A control signal  32  drives an input of variable frequency oscillator  36 , whose output provides synthesizer-output signal  38 . 
         [0013]    Synthesizer-output signal  38  drives frequency divider  40 , which is configured to divide the frequency of synthesizer-output signal  38  by N, producing a divided synthesizer-output signal  42 . Divided synthesizer-output signal  42  is provided to phase comparator  20 . 
         [0014]    Control signal  32  also drives pre-positioning circuit  44 . Pre-positioning circuit  44  causes synthesizer  80  to hop to new frequencies and to settle at these new frequencies. 
         [0015]    Specifically, control signal  32  is routed to an input of filter-state-recording circuit  46 . Filter-state-recording circuit  46  measures and records the various states exhibited by loop filter  24  as synthesizer  80  hops from frequency to frequency. 
         [0016]    Filter-state-recording circuit  46  includes an analog-to-digital (A/D) conversion circuit  48  and read/write memory  50 . The output of A/D conversion circuit  48  also couples to an input of controller  52 , and an output of controller  52  couples to an address input of memory  50 . A data output of memory  50  serves as the output for filter-state-recording circuit  46  and couples to an input of compensation circuit  54 . 
         [0017]    Compensation circuit  54  has an output coupled to an input of filter-state-assigning circuit  56 , and filter-state-assigning circuit  56  has an output that drives control signal  32  from time to time. During these driving times, filter-state-assigning circuit  56  assigns states to loop filter  24 , which causes loop-filter capacitor  30  to charge or discharge to desired voltage levels. 
         [0018]    Filter-state-assigning circuit  56  includes multiplexer (MUX)  58 . The compensation circuit output couples to an input of multiplexer  58 . Outputs from controller  52  also couple to multiplexer  58 . An output of multiplexer  58  couples to an input of a digital-to-analog (D/A) conversion circuit  60 , and an output of D/A conversion circuit  60  couples to switching device  62 . Switching device  62  also couples to loop filter  24 , variable frequency oscillator  36 , and filter-state-recording circuit  46 . A selection input of switching device  62  couples to an output from controller  52 . 
         [0019]    The A/D conversion circuit  48  and D/A conversion circuit  60  have the same resolution, typically in the range of 8-16 bits. Compensation circuit  54  compensates for response differences between filter-state-recording circuit  46  and filter-state-assigning circuit  56 . The response differences are due to offset differences and linearity differences between A/D conversion circuit  48  and D/A conversion circuit  60 . 
         [0020]    Pre-positioning circuit  44  seeks to record a given state of loop filter  24  during an earlier hop period in which a given synthesizer-output frequency is generated. Then, during a later hop period occurring the next time that same synthesizer-output frequency is to be generated, pre-positioning circuit  44  seeks to assign that same state to loop filter  24 . But due, at least in part, to the response differences between filter-state-recording circuit  46  and filter-state-assigning circuit  56  error is inevitably introduced while recording the state during the earlier hop period, and additional error is introduced in reproducing the recorded state for assignment to loop filter  24  during the later hop period. Thus, compensation circuit  54  is provided to compensate for these errors. 
         [0021]    In addition, compensation circuit  54  adapts to the individual characteristics of filter-state-recording circuit  46  and filter-state-assigning circuit  56 . The adaptation is accomplished through a training process, whereby controller  52  trains compensation circuit  54  when synthesizer  80  is initially energized and on additional occasions while synthesizer  80  remains energized. 
         [0022]    As will be explained, the present invention provides improvements over the frequency synthesizers shown in  FIGS. 2 and 3 . 
       SUMMARY OF THE INVENTION 
       [0023]    To meet this and other needs, and in view of its purposes, the present invention provides a frequency synthesizer including at least one phase locked loop (PLL) for generating a desired frequency. The one PLL includes a loop filter. Also included is a characterization circuit configured to receive a digital word for characterizing the one PLL and provide a pre-charge value for pre-charging the loop filter to generate the desired frequency. A successive approximation analog to digital (A/D) converter is coupled between the loop filter and the characterization circuit, for providing both (a) the digital word to the characterization circuit, and (b) the pre-charge value to the loop filter. The digital word includes n-bits ranging in values from a most significant bit (MSB) to a least significant bit (LSB), and the pre-charge value is formed by the n-bits. The characterization circuit includes a memory portion for providing a look-up table (LUT), and the pre-charge value is stored in the LUT. 
         [0024]    The successive approximation A/D converter includes a successive approximation register (SAR) for forming the digital word, and a digital to analog (D/A) converter for forming the pre-charge value. The successive approximation A/D converter also includes a comparator for comparing (a) a value corresponding to the loop filter voltage in the PLL with (b) an analog value formed by a bit of the digital word. The loop filter voltage in the PLL is provided from a phase comparator disposed in the PLL, and the analog value is provided from the D/A converter. 
         [0025]    The frequency synthesizer includes one PLL for generating first and second desired frequencies. The PLL includes first and second loop filters, and a set of switches for sequentially selecting the first and second loop filters for generating, respectively, the first desired frequency and the second desired frequency. During a first period, the characterization circuit is configured to pre-charge the first loop filter to a first pre-charge value, and during a second period, the characterization circuit is configured to pre-charge the second loop filter to a second pre-charge value. 
         [0026]    The frequency synthesizer includes, during the first period, a successive approximation A/D converter is configured to provide a first digital word to characterize the second loop filter, and during the second period, the successive approximation A/D converter is configured to provide a second digital word to characterize the first loop filter. 
         [0027]    Another embodiment of the invention is a frequency synthesizer having a phase locked loop (PLL) with first and second loop filters. Each loop filter is selectively coupled between a phase comparator and a voltage controlled oscillator (VCO). A characterization circuit is selectively coupled to the first or second loop filter, and configured to determine a loop filter voltage and provide a pre-charge value to pre-charge the first or second loop filter to a desired frequency. The first loop filter is coupled to the characterization circuit during a period of pre-charge of the second loop filter, and the second loop filter is coupled to the characterization circuit during another period of pre-charge of the first loop filter. 
         [0028]    The frequency synthesizer includes a controller for selectively coupling the first or second loop filter between the phase comparator and the VCO, and selectively coupling the pre-charge value to the first loop filter or the second loop filter. 
         [0029]    The first loop filter is predetermined to operate at a first frequency, the characterization circuit is configured to determine the loop filter voltage of the first frequency, and the pre-charge value is configured to pre-charge the first loop filter to the first frequency. The second loop filter is predetermined to operate at a second frequency, the characterization circuit is configured to determine the loop filter voltage of the second frequency, and the pre-charge value is configured to pre-charge the second loop filter to the second frequency. 
         [0030]    The frequency synthesizer includes an analog to digital (A/D) converter, coupled to the characterization circuit, for providing a digital representation of a first or a second loop filter voltage in the PLL. A processor determines a pre-charge value corresponding to a desired frequency based on the first or the second loop filter voltage, and the processor stores the pre-charge value in a look-up table (LUT). 
         [0031]    A comparator is included for comparing (a) an analog value corresponding to the loop filter voltage in the first loop filter or the second loop filter with (b) an analog value of a portion of a word formed by the D/A converter during a process of forming an entire word representing the loop filter voltage. 
         [0032]    During a first period, the first loop filter is pre-charged by a pre-charge value for providing a first operational frequency. During a second period, the second loop filter is pre-charged by another pre-charge value for providing a second operational frequency. The first and second periods are sequential time periods. 
         [0033]    It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0034]    The invention is best understood from the following detailed description when read in connection with the accompanying figures: 
           [0035]      FIG. 1  is a conventional frequency synthesizer. 
           [0036]      FIG. 2  is a conventional pre-positioned frequency synthesizer. 
           [0037]      FIG. 3  is another conventional pre-positioned frequency synthesizer. 
           [0038]      FIG. 4  is a pre-positioned frequency synthesizer, in accordance with an embodiment of the present invention. 
           [0039]      FIG. 5  is a method for pre-positioning the frequency synthesizer shown in  FIG. 4 , in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0040]      FIG. 4  depicts a block diagram of a pre-positioned frequency synthesizer, generally designated as  100 , in accordance with an embodiment of the present invention. Synthesizer  100  includes a set of switches  102 ,  106 ,  110 ,  116 ,  122  and  124 . Switch  102  is coupled at the input side to a phase comparator, which may be similar to phase comparator  20  shown in  FIG. 3 . The output side of switch  106  is coupled to a composite voltage controlled oscillator (VCO) for producing the desired output frequencies. Sandwiched between switches  102  and  106  are loop filter A and loop filter B, respectively designated as  104  and  108 . 
         [0041]    Loop filter A is active, when the arms of switches  102  and  106  are each set to position A. Loop filter B is active, on the other hand, when the arms of switches  102  and  106  are each set to position B. As an example, when loop filter A is active the output of the composite VCO produces a frequency of f A . When loop filter B is active, the composite VCO produces a frequency of f B . 
         [0042]    It will be appreciated that loop filter A and loop filter B are configured to influence the bandwidth of frequency synthesizer  100 . The loop filters may be any one of a variety of loop filter topologies known in the phase-locked loop (PLL) arts. For example, the loop filters may include loop filter resistor  28  coupled in series with loop filter capacitor  30 , as shown in  FIG. 3 . In addition, the VCO may be similar to variable frequency oscillator  36 , as shown in  FIG. 3 , or may be a composite VCO operating in tandem. 
         [0043]    Furthermore, although not shown, loop filter A and loop filter B are each part of a PLL that includes a feedback loop from the output of the composite VCO to an input of the phase comparator, usually through a frequency divider. In other words, the PLL may be similar to PLL  26  shown in  FIG. 3 . As shown, the output from variable frequency oscillator  36  loops back into one input of phase comparator  20  through divider  40 . The other input of phase comparator  20  is provided from a reference oscillator, which provides reference frequency  12  on input line  14 . The output of the phase comparator provides an error signal. As such, a phase error signal on line  140 , shown in  FIG. 4 , drives either loop filter A or loop filter B. The resulting signal from loop filter A or loop filter B is output on line  142  and provided to the composite VCO to produce the desired frequency output. 
         [0044]    Also shown in  FIG. 4  are ON/OFF switches  110  and  124 . Furthermore, switches  116  and  122  are similar to switches  102  and  106 , each providing a selectable connection to either position A or position B. Each of the switches are controlled by a controller/processor, which may include an integrated memory or a separate memory, the controller/processor/memory being designated as  114 . As will be explained, controller/processor/memory  114  includes a successive approximation register (SAR)  120 , which converts an analog input signal into a digital output signal when utilized in conjunction with comparator  118  and either digital-to-analog (D/A) converter  112  or D/A converter  126  and provides the digital output signal onto bus  130 , by way of latch  128 . 
         [0045]    It will be understood that comparator  118 , D/A converter  112 , D/A converter  126 , SAR  120  and latch  128 , together, form a successive approximation A/D converter. A digital bit (1 level, or 0 level) is provided to SAR  120  by way of output line  144  from comparator  118 . Comparator  118  receives, at its first input port, a voltage from the input side of loop filter A or loop filter B (shown connected to loop filter A). At its second input port, comparator  118  receives, by way of switch  122 , an analog signal from D/A converter  112 . When switch  122  is connected to position B, however, comparator  118  receives, by way of switch  122 , an analog signal from D/A converter  126 . 
         [0046]    Although D/A converters  112  and  126  are shown as two circuits that are separate from controller/processor/memory  114 , it will be appreciated that all these circuits may be disposed in one integral circuit, such as controller/processor/memory  114 . Furthermore, the two D/A converters  112  and  126  may be replaced by a single D/A converter having a multiplexed output, which is first connected to port A of switch  122  and, next, connected to port B of switch  122 . 
         [0047]    As shown, controller/processor/memory  114  may be implemented using any microprocessor, microcontroller, memory, timer, and like circuit managed by one or more computer programs to carryout various controlling processes. controller/processor/memory  114  may also include other latching and counting circuits, configured so that multiple events may be setup in advance, under control of a computer program, then clocked or synchronized to occur substantially simultaneously, or at a specified instance of time. 
         [0048]    As known in the art, a successive approximation A/D converter approximates an analog signal to form an n-bit digital code (or word) in n-clock cycles. The successive approximation A/D converter compares, by way of comparator  118 , an analog input voltage at a midpoint of one of n-ranges to determine the value of a single bit. Accordingly, comparator  118  compares the analog input voltage from the input side of loop filter A, or loop filter B to a voltage from D/A converter  112 , or D/A converter  126 , respectively, and provides a 1-bit value. This comparison process is repeated for a total of n-clock cycles, using n-ranges to determine the n-bits in the digital code (word). 
         [0049]    The comparison process is accomplished as follows: comparator  118  determines if the analog input voltage is above or below the value output from D/A converter  112  and then sets the output of the comparator, on line  144 , accordingly. The SAR  120  assigns the bits beginning with the most significant bit (MSB). The bit is set to a one, if the analog input voltage is greater than the D/A MSB voltage, as determined by comparator  118 . On the other hand, the bit is set to a zero, if the analog input voltage is less than the D/A MSB voltage, as determined by comparator  118 . The D/A bit is kept as a one, if the comparison is true (analog input is greater than D/A voltage); otherwise, it is set to zero. The SAR  120  then moves to the next bit and sets the bit to a 1 level or a 0 level, based on the results of the comparison by comparator  118 . Because SAR  120  performs one approximation for each bit of the digital code, an n-bit code (or word) requires n-approximations. After completing the n-approximations, latch  128  produces the digital output code on line  130 . 
         [0050]    Still referring to  FIG. 4 , the output voltage of D/A converter  126  is provided as an input voltage to loop filter B, by way of switch  124 , which is in the ON position. Similarly, the output voltage from D/A converter  112  is provided to the input side of loop filter A, when switch  110  is in the closed position (shown in the OFF position). 
         [0051]    Although the output voltage from D/A converter  112  and the output voltage from D/A converter  126  are shown provided as voltages to the input sides of loop filter A and loop filter B, they may also be provided at the output sides of loop filter A and loop filter B. Similarly, the voltage provided into the input side of comparator  118  is shown arriving from the input side of loop filter A or loop filter B. It will be appreciated, however, that the voltage provided into the input side of comparator  118  may arrive from the output side of loop filter A or loop filter B. 
         [0052]    Using the A/B digital output code (word), controller/processor/memory  114  characterizes the phase lock loop (PLL) including loop filter A and the PLL including loop filter B. In operation, frequency synthesizer  100  is shown with switches selecting the A state, where loop filter A controls the composite VCO to produce an output frequency of f A . Accordingly, switches  102  and  106  are both in position A. There is no analog voltage provided from D/A converter  112 , because switch  110  is in the OFF position. On the other hand, an analog voltage is provided from D/A converter  126 , because switch  124  is in the ON position. The analog voltage from D/A converter  126  modifies the characteristics of loop filter B. In this manner, loop filter B is pre-charged and is readied for controlling the composite VCO to provide the desired output frequency of f B . 
         [0053]    During the A state, as shown, the voltage at the input side of loop filter A is provided to the first input side of comparator  118  by way of switch  116 . The analog voltage from D/A converter  112  is provided to the second input side of comparator  118  by way of switch  122 . If the voltage from loop filter A is greater than a voltage provided by D/A converter  112 , then comparator  118  outputs a 1 level to SAR  120 , as previously described. This is repeated for a number n of clock cycles, the number n depending on the resolution of SAR  120 . After n-approximations, latch  128  provides a digital output word on line  130 , corresponding to the voltage on line  140  from the phase comparator. The digital output word on line  130  is used to characterize loop filter A. 
         [0054]    The characterization of the PLL may change over time, due to temperature changes and component aging changes. The new characterization of the PLL, including loop filter A, which is necessary to provide the desired frequency of f A , may be stored in a look-up table (LUT) in the memory portion of controller/processor/memory  114 . 
         [0055]    After providing the output frequency f A , controller/processor/memory  114  modifies the positions of all the switches to place synthesizer  100  in the B state. The modification is configured by switches  102 ,  106 ,  116  and  122  set to position B, and switch  110  set to the ON position and switch  124  set to the OFF position. In this manner, loop filter B, which was pre-charged during the A state, is ready to control the composite VCO, by way of line  142 , to provide the desired output frequency of f B . The analog voltage from D/A converter  112  is provided to pre-charge loop filter A to achieve the desired output frequency of f B . 
         [0056]    While loop filter A is pre-charging to provide the desired output frequency, comparator  118  receives the analog voltage from the input side of loop filter B and compares that voltage to an analog voltage from D/A converter  126 . After n-clock cycles, SAR  120 , by way of latch  128 , produces a digital word corresponding to the analog voltage at the input side of loop filter B. This word is then used to characterize loop filter B. Once characterized, the desired voltage needed to precharge loop filter B may be stored in the look-up table (LUT). 
         [0057]    This process is repeated by cycling sequentially between the A state (loop filter A of the PLL) and the B state (loop filter B of the PLL). While loop filter A and the VCO are being characterized and the synthesizer is operating at frequency f A , loop filter B is being pre-charged and readied for the upcoming VCO frequency f B . 
         [0058]    Referring now to  FIG. 5 , there is shown a method for real-time synthesizer characterization of a frequency synthesizer, the method designated by  500 . Beginning at step  501 , all the switches are set to the A state. The A state includes switches  102 ,  106 ,  116  and  122  set to position A; switch  110  set to the OFF position; and switch  124  set to the ON position. 
         [0059]    At step  502 , controller/processor/memory  114  reads the voltage or signal at the input side of loop filter A. At step  503 , the controller/processor/memory characterizes the PLL, which includes loop filter A and the VCO. At step  504 , the characterization value of loop filter A and the VCO are stored in a look-up table in the controller/processor/memory  114 . 
         [0060]    In step  505 , while the VCO is still operating to provide frequency output f A , loop filter B is pre-charged and readied for the upcoming VCO output frequency f B . After the pre-charging of loop filter B, step  506  sets the switches to the B state. The B state is configured by switches  102 ,  106 ,  116 , and  122  set to position B; switch  110  set to the ON position; and switch  124  set to the OFF position. The composite VCO is now ready to provide the desired output frequency of f B . 
         [0061]    During operation of the synthesizer using loop filter B to provide output frequency f B , loop filter B is also being characterized in a manner similar to steps  502  through  506 . This is summarized by step  507 . Method  500  loops back to the beginning of step  501  and the process repeats by switching to the A state and then switching to the B state, and so on. 
         [0062]    It will now be appreciated that frequency synthesizer  100  is an improvement over frequency synthesizer  80  shown in  FIG. 3 . Because frequency synthesizer  100  uses (1) a successive approximation A/D converter to provide a digital word and (2) the D/A converter(s), which is part of the successive approximation A/D converter, to provide the analog voltage for pre-charging the loop filters, the circuitry of synthesizer  100  is less complicated then the circuitry of synthesizer  80 . 
         [0063]    The synthesizer  80  requires both an A/D converter ( 48  in  FIG. 3 ) and a D/A converter ( 60  in  FIG. 3 ). As a result, synthesizer  80  requires matching components during fabrication between A/D converter  48  and D/A converter  60 . Furthermore, due to mismatches still existing between the two converters, synthesizer  80  requires compensation circuit  54  for compensating any mismatches between A/D converter  48  and D/A converter  60 . 
         [0064]    Synthesizer  100  of the present invention, however, does not have such complications. Furthermore, synthesizer  100  is effective in providing more hopping frequencies during a fixed period, than conventional synthesizers are capable of providing during the same fixed period. This is due to frequency synthesizer  100  providing an output frequency by way of one loop filter, while the other loop filter is being pre-charged to the next desired frequency. 
         [0065]    Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.