Abstract:
A circuit and method are described which suppresses reset noise in active pixel sensor arrays. A circuit having a number of N −  wells formed in a P −  silicon epitaxial layer or a number of P −  wells formed in an N −  silicon epitaxial layer is provided. A pixel is formed in each of the wells so that each of the wells is surrounded by silicon of the opposite polarity and an array of pixels is formed. Means are provided for selectively combining or binning adjacent N −  or P −  wells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated. The reset is accomplished using a PMOS transistor formed in each N −  well or an NMOS transistor formed in each P −  well. The selective binning is accomplished using NMOS or PMOS transistors formed in the region between adjacent wells. Conductive traces between adjacent wells can also be used to accomplish the selective binning.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    (1) Field of the Invention  
           [0002]    This invention relates to a circuit and method for suppressing noise during pixel reset and more specifically to using programmable binning to selectively bin adjacent pixels during reset.  
           [0003]    (2) Description of the Related Art  
           [0004]    In optical imagers noise resulting form switching between pixels is a very important consideration. Control of this noise is a very important consideration in these optical imagers.  
           [0005]    U.S. Pat. No. 6,452,153 B1 to Lauxterman et al. describes an optoelectronic sensor having at least two sensors and binning between sensors.  
           [0006]    U.S. Pat. No. 6,424,750 B1 to Colbeth et al. describes an X-Ray imaging system. In one aspect of the invention pixel binning is used to combine pixel information collected by the detector array.  
           [0007]    U.S. Pat. No. 5,970,115 to Colbeth et al. describes radiation imaging systems, in particular X-Ray radiation systems, capable of operating in multiple detection and display modes.  
           [0008]    U.S. Pat. No. 5,848,123 to Strommer describes methods and apparatus for imaging an object by detecting radiation reflected from and/or transmitted through the object using an imaging sensor system. The sensor system is configured by means of a control scheme based on combining or binning the imaging elements.  
           [0009]    U.S. Pat. No. 5,134,488 and U.S. Pat. No. 5,134,489 to Sauer describe an X-Y addressable solid state imager.  
         SUMMARY OF THE INVENTION  
         [0010]    Electrical noise is a fundamental limitation in any electronic circuit, and control of noise is especially important in optical imaging system. Switching noise generated by reading out an array of pixels causes undesirable noise in the image and represents a fundamental limitation of the sensitivity of the optical system.  
           [0011]    It is a principle objective of this invention to provide an imaging circuit having pixels and reset noise suppression.  
           [0012]    It is another principle objective of this invention to provide a method of suppressing reset noise in an imaging circuit.  
           [0013]    These objectives are achieved by providing a circuit having a number of N −  wells formed in a P −  silicon epitaxial layer. A pixel is formed in each of the N −  wells so that each of the N −  wells is surrounded by P −  type silicon and an array of pixels is formed. Means are provided for selectively combining or binning adjacent N −  wells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated.  
           [0014]    One means for binning the pixels is to connect selected N −  wells with selected adjacent N −  wells using traces of conductive material formed over the P −  regions between the selected N −  wells. This electrically connects or bins the selected adjacent N −  wells. Another method of binning pixels is to form N +  channel regions between the selected adjacent N −  wells followed by forming a gate dielectric and gate electrode over the N +  channel regions. This forms an N channel metal oxide semiconductor, NMOS, transistor which can be used to connect or disconnect the selected adjacent N −  wells as desired by turning the NMOS transistors on or off.  
           [0015]    These objectives can also be achieved by providing a circuit having a number of P −  wells formed in an N −  silicon epitaxial layer. A pixel is formed in each of the P −  wells so that each of the P −  wells is surrounded by N −  type silicon and an array of pixels is formed. Means are provided for selectively combining or binning adjacent P −  wells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated.  
           [0016]    One means for binning the pixels is to connect selected P −  wells with selected adjacent P −  wells using traces of conductive material formed over the N −  regions between the selected P −  wells. This electrically connects or bins the selected adjacent P −  wells. Another method of binning pixels is to form P +  channel regions between the selected adjacent P −  wells followed by forming a gate dielectric and gate electrode over the P +  channel regions. This forms a P channel metal oxide semiconductor, PMOS, transistor which can be used to connect or disconnect the selected adjacent P −  wells as desired by turning the PMOS transistors on or off. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 shows a top view of an array of pixels formed in N −  or P −  wells showing a reset transistor in each N −  or P −  well and binning connections between adjacent N −  or P −  wells.  
         [0018]    [0018]FIG. 2 shows a top view of one of the pixels of FIG. I showing the reset transistor in greater detail.  
         [0019]    [0019]FIG. 3 shows a cross section view of the pixel of FIG. 2 taken along line  3 - 3 ′ of FIG. 2.  
         [0020]    [0020]FIG. 4 shows a top view of two adjacent pixels formed in N −  or P −  wells having an NMOS or a PMOS transistor for binning connection and an electrical conductor used to turn the transistor on or off.  
         [0021]    [0021]FIG. 5 shows a cross section view of the pixels of FIG. 4 taken along line  5 - 5 ′ of FIG. 4.  
         [0022]    [0022]FIG. 6 shows a cross section view, taken along line  6 - 6 ′ of FIG. 1, of two adjacent pixels formed in N −  or P −  wells having conductive traces for binning connections.  
         [0023]    [0023]FIG. 7 shows a top view of an array of pixels formed in N −  or P −  wells with binning connections between selected adjacent N −  or P −  wells.  
         [0024]    [0024]FIG. 8A shows a schematic view of four of the pixels of FIG. 6 wherein the binning connections are NMOS transistors.  
         [0025]    [0025]FIG. 8B shows a schematic view of four of the pixels of FIG. 6 wherein the binning connections are PMOS transistors.  
         [0026]    [0026]FIG. 9 shows a block diagram for the method of this invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0027]    Refer now to FIGS.  1 - 7  and  8 A for a detailed description of a preferred embodiment of the circuit and method of this invention. FIG. 1 shows part of an active pixel sensor, APS, array with four pixels  12  shown in FIG. 1. Each of the pixels  10  comprise an N −  well  12  formed in a layer of P −  epitaxial silicon  16 . The junction between these N −  wells and the P −  substrate forms a number of photodiodes. A reset transistor  14  is formed in each of the N −  wells  12  and is used to reset the pixel after the charge integration period has been completed and the charge accumulated by the pixel has been read. As an example the reset transistor  14  is a P channel metal oxide semiconductor, PMOS, transistor formed in each of the N −  wells. The N −  well is reverse biased relative to the P −  epitaxial silicon layer. During the first part of the cycle a signal incident on the pixel causes the charge stored at this reverse biased PN junction to decay. This signal is usually optical radiation, however other signals may be used to cause this charge decay. After the charge on the pixel has been read the PMOS transistor can be turned on to inject negative charge into the N −  well and restore the pixel charge to its initial value.  
         [0028]    [0028]FIGS. 2 and 3 show a more detailed view of the reset transistor. FIG. 2 shows a top view and FIG. 3 a cross section view taken along line  3 - 3 ′ of FIG. 2. Two P regions  18  are formed in the N −  well to form source and drain regions. A gate oxide  22  is formed over the part of the N −  well between the two P regions  18 , see FIG. 2. An electrical contact  21  is formed to the gate electrode  20  and an electrical contact  19  is formed to one of the P regions  18  to form a source connection. The other P region  18  forms the drain and is in contact with the N −  well forming the connection to the photodiode formed by the N −  well and the P −  substrate.  
         [0029]    [0029]FIG. 1 shows a number of interconnections  22  between selected adjacent pixels. These interconnections can be conductive traces which form a hard connection between selected N −  wells  12  or can be switches which can be programmed to select different combinations of N −  wells  12  at different times. FIGS. 4 and 5 show the case where the interconnections are switches formed by N channel metal oxide semiconductor, NMOS, transistors. FIG. 4 shows a top view and FIG. 5 a cross section view, taken along line  5 - 5 ′ of FIG. 4, of two adjacent N −  wells  12  connected by an NMOS binning transistor. The N −  wells  12  each have a PMOS reset transistor  14  formed therein. The NMOS binning transistor is formed by forming an N +  channel region  23  between two adjacent N −  wells  12 , see FIG. 5. A gate electrode  28  is formed over the N +  channel region  23  with a layer of gate dielectric  22  formed between the gate electrode  28  and the N +  channel region  23 , see FIG. 5. A layer of second dielectric  26  is formed over the gate electrode  28  and the layer of gate dielectric  22  so that a conducting electrode  24  can be routed across the pixel array to contact the gate electrodes.  
         [0030]    Returning to FIG. 1 the interconnections between selected N −  wells  12  can be conductive traces which form permanent binning connections. FIG. 6 is a cross section view of two adjacent N −  wells of FIG. 1 taken along line  6 - 6 ′ of FIG. 1 showing permanent binning connections. As shown in FIG. 6 a layer of dielectric  52  is formed over the N −  wells  12  and the intervening P −  epitaxial silicon  16 . A conducting electrode  50  is formed on the layer of dielectric  52 . Electrical contacts  54  are then formed through the dielectric  52  between each end of the conducting electrode  50  and the two N −  wells  12 .  
         [0031]    [0031]FIG. 7 shows a top view of a part of an array of or N −  wells  12 , or pixels, arranged in rows and columns with a PMOS reset transistor  14  in each of the N −  wells. FIG. 7 shows four rows;  100 ,  101 ,  102 , and  103 ; of N −  wells  12  and four columns;  200 ,  201 ,  202 ,  203 ; of N −  wells  12 . While the part of the array shown in FIG. 7 shows four rows and four columns of pixels there could be more or fewer than four rows of N −  wells  12  and more or fewer than four columns of N −  wells  12 . In the array shown in FIG. 7 the binning connections are NMOS transistors as previously described. Vertical electrodes  32  between selected columns of N −  wells  12 , between columns  200  and  201  and between columns  202  and  203 , form electrical connection to the gate electrodes  22  of the NMOS binning transistors connecting the N −  wells  12  in one of the selected columns to the adjacent N −  wells  12  in the adjacent selected column. In this example the connections are between each of the N −  wells  12  in column  200  and the adjacent N −  wells  12  in column  201  and between each of the N −  wells  12  in column  202  and the adjacent N −  wells  12  in column  203 .  
         [0032]    In like manner, horizontal electrodes  32  between selected rows of N −  wells  12  form electrical connection to the gate electrodes  22  of the NMOS binning transistors connecting the N −  wells  12  in one of the selected rows to the adjacent N −  wells  12  in the adjacent selected row. In this example the connections are between each of the N −  wells  12  in row  100  and the adjacent N −  wells  12  in row  101  and between each of the N −  wells  12  in row  102  and the adjacent N −  wells  12  in row  103 . The connections shown in this example result in sub-arrays of four N −  wells which can be binned in groups of two or four depending on which NMOS binning transistors are turned on and isolated from one another when the NMOS transistors are turned off. Different arrays and different electrical connections can aggregate different sub arrays when the binning transistors are turned on. An entire array of N −  wells could be binned if that were desired.  
         [0033]    [0033]FIG. 8A shows a schematic diagram of an array of four photodiodes  38 A arranged in two rows and two columns. The photodiodes  38 A correspond to the PN junction between the N −  and the P −  epitaxial layer forming the pixel. The reset PMOS transistors  14 A are shown connected to each photodiode  38 A. The NMOS binning transistors  34 A between adjacent photodiodes  38 A in adjacent columns and the binning NMOS transistors  36 A between adjacent photodiodes  38 A in adjacent rows are shown in FIG. 8A. An output amplifier  40 A for each photodiode  38 A is shown in FIG. 8A. In the operation of the imager the incident signal caused charge to accumulate in the pixel during an integration period when charge is stored by the photodiode  38 A. Following the readout cycle the reset transistors  14 A are turned on to reset the photodiodes  38 A. The binning transistors,  34 A and  36 A, are turned on and remain turned on while the reset transistors  14 A are turned of. Since the binning transistors are turned on the charge injected when the reset transistors  14 A are turned off is averaged among the binned photodiodes which minimizes pixel-to-pixel noise caused by reset. In the conventional active pixel sensor array the reset transistor resets each photodiode individually, since binning is not used, resulting in greater pixel-to-pixel noise caused by reset.  
         [0034]    Refer now to FIGS.  1 - 7  and  8 B for a detailed description of another preferred embodiment of the circuit and method of this invention. FIG. 1 shows part of an active pixel sensor, APS, array with four pixels  12  shown in FIG. 1. Each of the pixels  10  comprise a P −  well  12  formed in a layer of N −  epitaxial silicon  16 . The junction between these P −  wells and the N −  substrate forms a number of photodiodes. A reset transistor  14  is formed in each of the P −  wells  12  and is used to reset the pixel after the charge integration period has been completed and the charge accumulated by the pixel has been read. As an example the reset transistor  14  is an N channel metal oxide semiconductor, NMOS, transistor formed in each of the P −  wells. The P −  well is reverse biased relative to the N −  epitaxial silicon layer. During the first part of the cycle a signal incident on the pixel causes the charge stored at this reverse biased PN junction to decay. This signal is usually optical radiation but other signals may cause this charge decay as well. After the charge on the pixel has been read the NMOS transistor can be turned on to inject positive charge into the P −  well and restore the pixel charge to its initial value.  
         [0035]    [0035]FIGS. 2 and 3 show a more detailed view of the reset transistor. FIG. 2 shows a top view and FIG. 3 a cross section view taken along line  3 - 3 ′ of FIG. 2. Two N regions  18  are formed in the P −  well to form source and drain regions. A gate oxide  22  is formed over the part of the P −  well between the two N regions  18 , see FIG. 2. An electrical contact  21  is formed to the gate electrode  20  and an electrical contact  19  is formed to one of the N regions  18  to form a source connection. The other N region  18  forms the drain and is in contact with the P −  well forming the connection to the photodiode formed by the P −  well and the N −  substrate.  
         [0036]    [0036]FIG. 1 shows a number of interconnections  22  between selected adjacent pixels. These interconnections can be conductive traces which form a hard connection between selected P −  wells  12  or can be switches which can be programmed to select different combinations of P −  wells  12  at different times. FIGS. 4 and 5 show the case where the interconnections are switches formed by P channel metal oxide semiconductor, PMOS, transistors. FIG. 4 shows a top view and FIG. 5 a cross section view, taken along line  5 - 5 ′ of FIG. 4, of two adjacent P −  wells  12  connected by a PMOS binning transistor. The P −  wells  12  each have an NMOS reset transistor  14  formed therein. The PMOS binning transistor is formed by forming an P +  channel region  23  between two adjacent P −  wells  12 , see FIG. 5. A gate electrode  28  is formed over the P +  channel region  23  with a layer of gate dielectric  22  formed between the gate electrode  28  and the P +  channel region  23 , see FIG. 5. A layer of second dielectric  26  is formed over the gate electrode  28  and the layer of gate dielectric  22  so that a conducting electrode  24  can be routed across the pixel array to contact the gate electrodes.  
         [0037]    Returning to FIG. 1 the interconnections between selected P −  wells  12  can be conductive traces which form permanent binning connections. FIG. 6 is a cross section view of two adjacent P −  wells of FIG. 1 taken along line  6 - 6 ′ of FIG. 1 showing permanent binning connections. As shown in FIG. 6 a layer of dielectric  52  is formed over the P −  wells  12  and the intervening N −  epitaxial silicon  16 . A conducting electrode  50  is formed on the layer of dielectric  52 . Electrical contacts  54  are then formed through the dielectric  52  between each end of the conducting electrode  50  and the two P −  wells  12 .  
         [0038]    [0038]FIG. 7 shows a top view of a part of an array of or P −  wells  12 , or pixels, arranged in rows and columns with an NMOS reset transistor  14  in each of the P −  wells. FIG. 7 shows four rows;  100 ,  101 ,  102 , and  103 ; of P −  wells  12  and four columns;  200 ,  201 ,  202 ,  203 ; of P −  wells  12 . While the part of the array shown in FIG. 7 shows four rows and four columns of pixels there could be more or fewer than four rows of P −  wells  12  and more or fewer than four columns of P −  wells  12 . In the array shown in FIG. 7 the binning connections are PMOS transistors as previously described. Vertical electrodes  32  between selected columns of P −  wells  12 , between columns  200  and  201  and between columns  202  and  203 , form electrical connection to the gate electrodes  22  of the PMOS binning transistors connecting the P −  wells  12  in one of the selected columns to the adjacent P −  wells  12  in the adjacent selected column. In this example the connections are between each of the P −  wells  12  in column  200  and the adjacent P −  wells  12  in column  201  and between each of the P −  wells  12  in column  202  and the adjacent P −  wells  12  in column  203 .  
         [0039]    In like manner, horizontal electrodes  32  between selected rows of P −  wells  12  form electrical connection to the gate electrodes  22  of the PMOS binning transistors connecting the P −  wells  12  in one of the selected rows to the adjacent P −  wells  12  in the adjacent selected row. In this example the connections are between each of the P −  wells  12  in row  100  and the adjacent P −  wells  12  in row  101  and between each of the P −  wells  12  in row  102  and the adjacent P −  wells  12  in row  103 . The connections shown in this example result in sub-arrays of four P −  wells which can be binned in groups of two or four depending on which PMOS binning transistors are turned on and isolated from one another when the PMOS transistors are turned off. Different arrays and different electrical connections can aggregate different sub arrays when the binning transistors are turned on. An entire array of P −  wells could be binned if that were desired.  
         [0040]    [0040]FIG. 8B shows a schematic diagram of an array of four photodiodes  38 B arranged in two rows and two columns. The photodiodes  38 B correspond to the PN junction between the P −  well and the N −  epitaxial layer forming the pixel. The reset NMOS transistors  14 B are shown connected to each photodiode  38 B. The PMOS binning transistors  34 B between adjacent photodiodes  38 B in adjacent columns and the binning PMOS transistors  36 B between adjacent photodiodes  38 B in adjacent rows are shown in FIG. 8B. An output amplifier  40 B for each photodiode  38 B is shown in FIG. 8B. In the operation of the imager the incident signal, such as optical, radiation caused charge to accumulate in the pixel during an integration period when charge is stored by the photodiode  38 B. Following the readout cycle the reset transistors  14 B are turned on to reset the photodiodes  38 B. The binning transistors,  34 B and  36 B, are turned on and remain turned on while the reset transistors  14 B are turned of. Since the binning transistors are turned on the charge injected when the reset transistors  14 B are turned off is averaged among the binned photodiodes which minimizes pixel-to-pixel noise caused by reset. In the conventional active pixel sensor array the reset transistor resets each photodiode individually, since binning is not used, resulting in greater pixel-to-pixel noise caused by reset.  
         [0041]    [0041]FIG. 9 shows a block diagram showing the method of this invention. As shown in the first block  90  the imager accumulates charge in the pixels during an integration period when charge is stored by the photodiodes. Next, during the readout period, as shown by the second block  91 , the charge on the pixels is read out to a suitable location such as a register. As shown in the third and fourth blocks,  92  and  93 , after the readout period has been completed the reset transistors are turned on and a reset period occurs when the initial charge on the photodiodes is restored. As shown in the next three blocks;  94 ,  95 , and  96 ; after the reset period has been completed the binning transistors are turned on while the reset transistors are still on. The reset transistors are then turned off while the binning transistors are on. Having the binning transistors on when the reset transistors are turned off is key to the noise suppression of this method. Next, after the reset transistors have been turned off the binning transistors are turned off and the cycle can begin again with the next integration period.  
         [0042]    Although the binning gates have been shown in the context of a sensor array in which the photosensitive elements are formed from N −  wells in a P −  type substrate or P −  type wells in an N −  type substrate the binning gates could be implemented in arrays having conventional CMOS pixel structures.  
         [0043]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.