Abstract:
A method for reading from a cell of a network of photosensitive cells arranged in rows and in columns, each cell being adapted to providing an image voltage or a reference voltage, including charging, simultaneously for all the cells in the row of the cell, at least one capacitor with a resulting charge which is a function of the difference between a reference current and an image current respectively corresponding to the conversion, by an amplifying factor greater than one, of the reference voltage and of the image voltage, and measuring for the cell column the capacitor charge.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a photosensitive cell reading method and device. 
     2. Discussion of the Related Art 
       FIG. 1  shows an example of a conventional device for reading a photosensitive cell  10  belonging to an array of cells arranged in rows and columns. 
     Cell  10  is formed of a photosensitive diode  12  having its anode connected to ground GND, and having its cathode connected to the source of a MOS-type N-channel transfer transistor  14 . The drain of transistor  14  is connected to the source of a MOS-type N-channel reset transistor  16  having its drain connected to a source of a supply voltage V RT . 
     The gate of transfer transistor  14  is controlled by a voltage V TG . The gate of reset transistor  16  is controlled by a voltage V R . The drain of transistor  14  and the source of transistor  16  are connected to the cathode of a transfer diode  18  and to the gate of a transistor  20 . Call V S  the voltage at the gate of transistor  20 , which is equal to the voltage across diode  18 . The anode of diode  18  is connected to ground GND. The drain of transistor  20  is connected to the source of reference voltage V RT . The source of transistor  20  is connected to the drain of a read transistor  22 . The source of read transistor  22  forms the output of cell  10 . The gate of read transistor  22  is controlled by a voltage V READ . 
     The source of transistor  22  is connected to a conductive column track  24 . To each column of the array of photosensitive cells is associated a column conductive track which is connected to all cells  10  in the column. 
     To each column track is associated a read device  30 . Read device  30  includes a first capacitor  32  having a terminal connected to ground GND and its other terminal connected to a track of column  24 , via a first switch  33 , and to the input of a first unity-gain impedance corrector  34 . The output of first impedance corrector  34  provides a voltage V 35  on a first output terminal  35  of device  30 . 
     Device  30  includes a second capacitor  36  having a terminal connected to ground GND and its other terminal connected to column track  24 , via a second switch  37 , and to the input of a second unity-gain impedance corrector  38 . The output of second impedance corrector  38  provides a voltage V 39  on a second output terminal  39  of device  30 . 
     Switches  33 ,  37  may be formed of MOS-type transistors operating as switches and having their gates respectively controlled by voltages V 11  and V 12 . Impedance correctors  34 ,  38  may be formed of follower-assembled transistors. 
     A current source  40  is present on column track  24 . 
       FIG. 2  shows a timing diagram of voltages at specific points of  FIG. 1 , illustrating a conventional method of reading of cell  10  by read device  30 . Each step of the process is in fact simultaneously carried out for all the cells  10  in a same row. The read method will be described hereafter for a single cell  10 . 
     On the abscissa axis are shown successive times t 1  to t 8 . On the ordinate axis are shown different variation curves  50  to  56  of voltages at specific points of cell  10  and of read device  30  of  FIG. 1 . 
     Curve  50  shows voltage V S  on the gate of transistor  20  and across diode  18 . Curve  51  shows voltage V R  applied to the gate of transistor  16 . Curve  52  shows control voltage V 11  of switch  33 . Curve  53  shows voltage V TG  applied to the gate of transistor  14 . Curve  54  shows control voltage V 12  of switch  37 . Curve  55  shows voltage V 35  on output terminal  35 , and curve  56  shows voltage V 39  on output terminal  39 . 
     Diode  12  is a reverse-biased photosensitive diode. It behaves as a capacitor charged under an initial voltage, which discharges when exposed to a light source, the charge lost by diode  12  being a function of the received light intensity. 
     All along the read phase, voltage V READ  on the gate of transistor  22  is such that transistor  22  behaves as an on switch. 
     At time t 1 , voltage V R  switches from a zero value to a positive value. Transistor  16  turns on. Voltage V RT  is then applied across diode  18  which, as it is reverse biased, behaves as a capacitor. Voltage V S  on the gate of transistor  20  is then equal to voltage V RT . 
     At time t 2 , voltage V R  becomes zero again. Transistor  16  is then off. Voltage V S  slightly drops due to a coupling between diode  18  and transistor  16 . 
     At time t 3 , voltage V 11  switches from a zero value to a positive value. Switch  33 , which used to be off, turns on. Voltage V 35 , corresponding to the voltage across capacitor  32 , is then equal to a constant value V REF  which is a function of voltage V S . 
     At time t 4 , voltage V 11  switches back to zero and switch  33  turns off. Capacitor  32  keeps between its terminals voltage V REF . 
     At time t 5 , voltage V TG  switches from a zero value to a positive value. Transistor  14  turns on. Diode  18  then discharges into diode  12 , which translates as a decrease in voltage V S . This decrease is representative of the amount of light received by diode  12 . 
     At time t 6 , voltage V TG  switches back to zero, and transistor  14  turns off. Voltage V S  at the gate of transistor  20  remains steady. 
     At time t 7 , voltage V 12  switches from a zero value to a positive value. Switch  37 , which used to be off, turns on. Voltage V 39 , corresponding to the voltage across capacitor  36 , is then equal to a constant voltage V PIX  which is a function of voltage V S . 
     At time t 8 , voltage V 12  switches back to zero and switch  37  turns off. Capacitor  36  keeps between its terminals voltage V PIX . 
     Difference V U  between voltages V REF  and V PIX  is representative of the light intensity received by cell  10 . Output terminals  35 ,  39  are connected to amplifiers or converters (not shown) enabling performing different processings on voltage V U . 
     The fact of considering voltage V u  to be useful enables suppressing the noise sampled on diode  18  upon disconnection from voltage V RT  by transistor  16 . Indeed, this noise reappears identically on both transistors V REF  and V PIX , and is thus suppressed when the difference between these two voltages is calculated to obtain useful voltage V U . 
     Voltage V U  however includes noise which originates from the read chain including transistors  20 ,  22 , and current source  40 . This noise is not suppressed or decreased by the previously-described read process. 
     Read device  30  is generally directly integrated at the level of the column having a width on the order of some ten micrometers. For want of room, it is not possible to directly include amplifiers in device  30 . Said amplifiers must be placed downstream of read circuit  30  and thus amplify all the noises added downstream of read device  30 . The presence of amplifiers is all the more necessary as the cell  10  of the type shown in  FIG. 1  exhibits a reduced dynamic range since voltage V PIX  can only vary between a voltage which depends on the maximum number of charges stored in diode  12  (which is variable according to the manufacturing process of diode  12  ) and a voltage V REF  smaller than V RT . Typically, the difference between V REF  and V PIX  does not exceed 1 volt. 
     Further, the dissymmetry of impedance correctors  34 ,  38 , results in an offset voltage which can be different for the correctors of the different columns Accordingly, voltages V U , obtained from cells belonging to two different columns having received the same light intensity, may be different. This may translate as the occurrence of vertical bars on an image calculated based on signals V U . 
     SUMMARY OF THE INVENTION 
     The present invention aims at providing a method and a device for reading from a cell which does not exhibit the above-mentioned disadvantages. 
     To achieve this and other objects, the present invention provides a method for reading from a cell of an array of photosensitive cells arranged in rows and columns, each cell being adapted to providing an image voltage or a reference voltage, comprising the steps of: 
     a) charging, simultaneously for all the cells in the row of said cell, at least one capacitor with a resulting charge which is a function of the difference between a reference current and an image current respectively corresponding to the conversion of the reference voltage and of the image voltage; and 
     b) measuring for the cell column the capacitor charge. 
     According to another feature of the present invention, step a) comprises the steps, simultaneously carried out for all the cells in the row, of converting the reference voltage into a reference current; charging a capacitor under the reference current for a first determined duration; converting the image voltage into an image current; discharging the capacitor under the image current for a second determined duration. 
     According to another feature of the present invention, step a) comprises the steps, simultaneously carried out for all the cells in the row, of converting the reference voltage into a reference current; charging a first capacitor under the reference current for a first determined duration; converting the image voltage into an image current; charging a second capacitor under the reference current for a second determined duration; and connecting the first and second capacitors in series. 
     According to another feature of the present invention, the amplification factor varies according to a setting voltage. 
     The present invention also provides a device for reading from cells of an array of photosensitive cells arranged in lines and columns, each cell being adapted to providing an image voltage or a reference voltage, comprising for each column a voltage-to-current converter having an input terminal connected to all the column cells and receiving the voltages provided by one of the column cells; and at least one capacitor charged under the current provided by the converter. 
     According to another feature of the present invention, the device comprises a single capacitor charged or discharged under the current provided by the converter and switching means for connecting a first terminal of the capacitor to an output terminal of the converter and a second terminal of the capacitor to a first voltage, or the first terminal of the capacitor to the first voltage and the second terminal of the capacitor to the output terminal of the converter, according to the voltages received by the converter. 
     According to another feature of the present invention, the device comprises first and second capacitors and switching means for alternately connecting the first capacitor or the second capacitor to an output terminal of the converter. 
     According to another feature of the present invention, the voltage-to-current converter comprises a first MOS-type transistor having its drain connected to the input terminal of the converter; second and third MOS-type transistors having their gates connected together to the input terminal, and having their sources connected to a second voltage, the second transistor having its drain connected to the source of the first transistor; a fourth MOS-type transistor having its gate connected, with the gate of the first transistor, to a source of a control voltage, and having its source connected to the drain of the third control transistor; and a current mirror having its input connected to the drain of the fourth transistor and having its output connected to the output terminal of the converter. 
     According to another feature of the present invention, the second and third transistors operate in a mode in which, for each transistor, for a determined voltage between the gate and the source, the drain current is proportional to the voltage between the drain and the source. 
     The foregoing object, features, and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1 , previously described, shows a conventional photosensitive cell read device; 
         FIG. 2 , previously described, shows a timing diagram of different voltages illustrating a conventional method for reading from the cell with the device of  FIG. 1 ; 
         FIG. 3  shows a first embodiment of a cell read device according to the present invention; 
         FIG. 4  shows a timing diagram of different voltages illustrating a read method according to the present invention with the device of  FIG. 3 ; 
         FIG. 5  shows a second embodiment of a cell read device according to the present invention; 
         FIG. 6  shows a timing diagram of different voltages illustrating a read method according to the present invention with the device of  FIG. 5 ; 
         FIG. 7  shows the detail of an element of the devices of  FIGS. 3 and 5 ; and 
         FIG. 8  shows the frequency response of the device of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  shows a first embodiment of a device  60  according to the present invention for reading from a cell  10 , identical to that of  FIG. 1 . A read device  60  according to the present invention is associated with each column of the photosensitive cell array. 
     Read device  60  comprises a voltage-to-current converter  61  of gain G having its input connected to column track  24 . The output of converter  61  is connected to a first terminal  62  of a capacitor  63 , of capacitance C, via a first switch  64 , and to second terminal  65  of capacitor  63  via a second switch  66 . First terminal  62  of capacitor  63  is connected to a variable voltage source V D  via a third switch  67 . Second terminal  65  of capacitor  63  is connected to voltage source V D  via a fourth switch  68 . Call V C  the voltage between the first  62  and second  65  terminals of capacitor  63 . A current source  69  is placed between the input of converter  61  and ground GND. 
     Switches  64 ,  68  are controlled by a voltage V 1 . They are on when voltage V 1  is equal to a determined positive value and off when voltage V 1  is zero. Switches  66 ,  67  are controlled by a voltage V 2 . They are on when voltage V 2  is equal to a determined positive value and off when voltage V 2  is zero. Switches  64 ,  66 ,  67 ,  68  each comprise, for example, two complementary MOS-type transistors. 
     A charge measurement means (not shown) is connected between terminals  62 ,  65  of capacitor  63  to measure the capacitor charge for a subsequent processing. 
       FIG. 4  shows a timing diagram of voltages at specific points of  FIG. 3  illustrating the read method according to the first embodiment of the present invention. Each step of the method is in fact performed simultaneously for all cells  10  in a same row. The read method will be described hereafter for a single cell  10 . 
     Successive times t′ 1  to t′ 8  are shown on the abscissa axis. On the ordinate axis, curves  50 ,  51 ,  53  are identical to those of  FIG. 2 . Curve  70  shows the variation of control voltage V 1  of switches  64  and  68 . Curve  71  shows the variation of control voltage V 2  of switches  66 ,  67 . Curve  72  shows the variation of voltage V D . Curve  73  shows the variation of voltage V C  across capacitor  63 . 
     The variations of voltages V S  and V R  at times t′ 1  and t′ 2  are identical to those at times t 1  and t 2  of  FIG. 2 . 
     At time t′ 3 , voltage V 1  switches from a zero value to a positive value turning on switches  64  and  68 . Voltage V 2  remains zero so that switches  66  and  67  remain off. Reference voltage V REF , which is a function of the value of voltage V S  at time t′ 3 , is applied to the input of converter  61  and is converted into a current which flows through capacitor  63  of first terminal  62  towards second terminal  65 . The current being constant, voltage V C  across capacitor  63  linearly increases, which is shown by section  74  of curve  73 . 
     At time t′ 4 , voltage V 1  switches back to zero. Switches  64  and  68  are thus off. Voltage V C  across capacitor  63  remains constant, which is shown by section  75  of curve  73 . 
     At times t′ 5  and t′ 6 , as previously described, part of the charge of diode  18  is transferred to diode  12 , which decreases voltage V S . Between times t′ 4  and t′ 7 , voltage V D  switches from a zero value to a value V DD , to avoid the presence of a negative voltage at the output of converter  61  at time t′ 7 . 
     At time t′ 7 , voltage V 2  switches from a zero value to a positive value, turning-on switches  66 ,  67 . Voltage V 1  remains zero so that switches  64  and  68  remain off. Voltage V PIX , which is a function of the value of voltage V S  at time t′ 7 , is applied to the input of converter  61  and is converted into a current which flows through capacitor  63  from second terminal  65  to first terminal  62 . Since the current is constant, voltage V C  across capacitor  63  linearly decreases, which is shown by section  76  of curve  73 . 
     At time t′ 8 , voltage V 2  switches back to zero. Switches  66 ,  67  are thus off. Voltage V C  across capacitor  63  remains constant, which is shown by section  77  of curve  73 . 
     On section  74 , the charge acquired by capacitor  63  is given by the following formula:
 
 Q   1   =V   REF   *G*T   1  
 
where  T   1   =t′   4   −t′   3 .
 
     On section  76 , the charge lost by capacitor  63  is given by the following formula:
 
 Q   2   =V   PIX   *G*T   2  
 
where  T   2   =t′   8   −t′   7 .
 
     After time t′8, the resulting charge of capacitor  63  is equal to:
 
 Q   R   =V   REF   *G*T   1   −V   PIX   *G*T   2  
 
     In the case where T 1 =T 2 =T one can write:
 
 Q   R   =G*T* ( V   REF   −V   PIX )
 
     The voltage across capacitor V C  can thus be written as:
 
 V   C =( G*T/C )*( V   REF   −V   PIX )=( G*T/C )* V   U  
 
     In the case where term G*T/C is greater than 1, an amplification of voltage V U  by read device  60  is obtained. 
     To avoid the dependence of V C  with respect to capacitance C of capacitor  63 , which may slightly vary from one column to another, it is preferable to measure the resulting charge Q R  stored in capacitor  63  rather than directly measuring V C . Indeed, resulting charge Q R  is independent from capacitance C. For this purpose, a conventional charge storage measurement means which carries out the transfer of the charge stored in capacitor  63  onto one or several read capacitors is used. The voltage across the read capacitor(s), which will be a function of charge Q C  and of the capacitances of the read capacitors, is finally read. The same read capacitor(s) being used for all columns, the voltage finally read is independent from the non-uniformity of capacitances C of capacitors  63  of each column. 
       FIG. 5  shows a second embodiment of a device  60  according to the present invention for reading from a cell  10 . 
     According to this second mode, the output of voltage-to-current converter  61  is connected to a first terminal of a first capacitor  80 , of capacitance C 1 , via a first switch  82  controlled by a voltage V 82 , and to a first terminal of a second capacitor  84  via a second switch  86  controlled by a voltage V 86 . The second terminals of the first  80  and second  84  capacitors are connected to ground GND via a third switch  88 . 
       FIG. 6  shows a timing diagram of voltages at specific points of  FIG. 5  illustrating the read method according to the second embodiment of the present invention. Each step of the method is in fact carried out simultaneously for all cells  10  in a same row. The read method will be described hereafter for a single cell  10 . 
     Successive times t″ 1  to t″ 8  are shown on the abscissa axis. On the ordinate axis, curves  50 ,  51 ,  53  are identical to those of  FIG. 2 . Curve  90  shows the variation of voltage V 82 . Curve  91  shows the variation of voltage V 86 . Curve  92  shows the variation of the voltage across capacitor  80 . Curve  93  shows the variation of the voltage across capacitor  84 . 
     From time t″ 1  to time t″ 8 , switch  88  remains on. 
     The variations of voltages V S  and V R  at times t″ 1  and t″ 2  are identical to those at times t 1  and t 2  of  FIG. 2 . 
     At time t″ 3 , voltage V 82  switches from a zero value to a positive value turning on switch  82 . Voltage V 86  remains zero so that switch  86  remains off. Reference voltage V REF , which is a function of the value of voltage V S  at time t″ 3 , is applied to the input of converter  61  and is converted into a current which flows through capacitor  80 . Since the current is constant, the voltage across capacitor  80  increases linearly, which is shown by section  94  of curve  92 . 
     At time t″ 4 , voltage V 82  switches back to zero. Switch  82  is thus off. The voltage across capacitor  80  remains constant. 
     At times t″ 5  and t″ 6 , as previously described, part of the charge of diode  18  is transferred to diode  12 , which decreases voltage V S . 
     At time t″ 7 , voltage V 86  switches from a zero value to a positive value, turning on switch  86 . Voltage V 82  remains zero, so that switch  82  remains off. Voltage V PIX , which is a function of the value of voltage V S  at time t″ 7 , is applied to the input of converter  61  and is converted into a current which flows through capacitor  84 . Since the current is constant, the voltage across capacitor  84  increases linearly, which is shown by section  95  of curve  93 . 
     At time t″ 8 , voltage V 86  switches back to zero. Switch  86  is thus off. The voltage across capacitor  84  remains constant. 
     The reading is performed by turning off both switches  82 ,  86  and by turning off switch  88 . Capacitors  80 ,  84  are then arranged in series. The charges balance between capacitors  80 ,  84 , so that the resulting charge on each of the capacitors is linked to the difference between voltages V REF  and V PIX . The resulting charge can then be read on one of capacitors  80 ,  84 , or on both capacitors, as explained previously. 
     The device according to the present invention has many advantages. 
     First, the device according to the present invention enables reducing the noise coming from transistors  20 ,  22  and from current source  40 . Indeed, voltage V C  across capacitor  63  in the first embodiment and across capacitors  80 ,  84  in the second embodiment corresponds to the integration of a current originating from converter  61 . The noise present on voltages V REF  and V PIX  at the input of converter  61  is thus averaged. 
     Second, the first embodiment of the device according to the present invention enables reducing the “fixed column noise” originating from the dissymmetry of impedance correctors  34 ,  38 . Indeed, in the present invention, the offset originating from voltage-to-current converter  61  is suppressed or eliminated by the “charge subtraction” operation performed at the level of capacitor  63 . 
     Third, the present invention enables performing an amplification of useful voltage V U  directly at the level of the read device. As an example, for a duration T on the order of 1 μs, a capacitance C of 500*10 −15  F, and a gain G of 10 −6  A/V, an amplification of useful voltage V U  on the order of two is obtained. 
     Fourth, the present invention enables setting the amplification factor of the read device by modifying gain G of voltage-to-current converter  61 , or by modifying durations T 1  and T 2 . Accordingly, the present invention enables, for example, varying the amplification factor according to the cell which is read by the read device. It can thus be envisaged to vary the amplification factor according to the color to be used in the image calculated from useful signal V U . 
     Fifth, in the first embodiment, one capacitor has been eliminated in device  60  according to the present invention with respect to device  30  of  FIG. 1 . By forming voltage-to-current converter  61  and current source  69  with a limited number of MOS-type transistors, space gains from 20% to 25% can be obtained. 
       FIG. 7  shows an example of embodiment of voltage-to-current converter  61  and of current source  69  of  FIG. 3 . Terminal  100  represents the input of converter  61  where a voltage V IN  is applied and terminal  101  represents the output of converter  61  which provides a current I O . 
     Converter  61  comprises two N-channel MOS transistors  102 ,  103  having their gates controlled by a setting voltage V G . Terminal  100  is connected to the drain of transistors  102 . The source of transistor  102  is connected to the drain of an N-channel MOS transistor  104 . The source of transistor  103  is connected to the drain of an N-channel MOS transistor  105 . The sources of transistors  104 ,  105  are connected to ground GND. The gates of transistors  104 ,  105  are connected together to terminal  100 . 
     The drain of transistor  103  is connected to a current mirror which is formed of two P-channel MOS transistors  106 ,  107 . The drain of transistor  106  is connected to the drain of transistor  103 . The drain of transistor  107  is connected to output terminal  101 . The gates of transistors  106 ,  107  are connected together to the drain of transistor  106 . The sources of transistors  106 ,  107  are connected to a source of a voltage V A , which may be equal to voltage V RT . 
     The operating principle of converter  61  is the following: 
     transistors  104 ,  105  operate linearly, that is, for a given voltage between the gate and the source, the drain current is substantially proportional to the voltage between the drain and the source. The drain current I D104  of transistor  104  is given by the following expression:
 
 I   D104   =K* ( V   GS104   −V   TH )* V   DS104  
 
where V GS104  is the voltage between the gate and the source of transistor  104  and V DS104  is the voltage between the drain and the source of transistor  104 , K is a constant, and V TH  a threshold voltage specific to transistor  104 . Voltage V GS104  is equal to input voltage V IN . Voltage V DS104  is provided by:
 
 V   DS104   =V   G   −V   GS102  
 
     where V GS102  is the voltage between the gate and the source of transistor  102 . Transistors  102  and  103  operate in saturated mode and V GS102  is set by the value of drain current I D102  of transistor  102 , equal to I D104 . The value of V GS102  varies little, so that V DS104  varies little. 
     Given the circuit symmetry, the drain current of transistor  103  is equal to I D104 . Transistors  106 ,  107  forming a current mirror, one obtains: 
     
       
         
           
             
               
                 
                   
                     I 
                     O 
                   
                   = 
                     
                   ⁢ 
                   
                     
                       I 
                       D103 
                     
                     = 
                     
                       
                         K 
                         * 
                         
                           ( 
                           
                             
                               V 
                               GS104 
                             
                             - 
                             
                               V 
                               TH 
                             
                           
                           ) 
                         
                         * 
                         
                           V 
                           DS104 
                         
                       
                       = 
                       
                         K 
                         * 
                         
                           ( 
                           
                             
                               V 
                               GS104 
                             
                             - 
                             
                               V 
                               TH 
                             
                           
                           ) 
                         
                         * 
                         
                           ( 
                           
                             
                               V 
                               G 
                             
                             - 
                             
                               V 
                               GS102 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
             
             
               
                 
                   
                     ≈ 
                       
                     ⁢ 
                     
                       G 
                       * 
                       
                         V 
                         GS104 
                       
                     
                   
                   = 
                   
                     G 
                     * 
                     
                       V 
                       IN 
                     
                   
                 
               
             
           
         
       
     
     Gain G of converter  61  substantially only depends on setting voltage V G . 
     Previously-described converter  61  has a particularly simple design and requires a reduced number of MOS-type transistors only. It also enables changing gain G in a simple way by means of setting voltage V G . 
       FIG. 8  shows the frequency response of the device according to the present invention. Curve  100  shows the standardized output voltage V U  of read device  30  of  FIG. 1 . Curve  111  shows standardized output voltage V C  of read device  60  according to the present invention. 
     As appears from  FIG. 6 , for both curves  110 ,  111 , the output signal is not attenuated at frequencies close to 100 kHz, which may correspond to the usual operating frequencies of read device  30 . For curve  110 , the signal is not attenuated either at certain frequencies greater than one megahertz, in particular at frequencies of several tens of megahertz which correspond to operating frequencies of the system clock. Conversely, read device  60  according to the present invention also attenuates signals beyond one megahertz. 
     Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, in the foregoing description, it is possible to arrange the transistors differently to optimize the linearity of the response of converter  61  and/or to minimize the effects of the dispersion of the characteristic of the MOS transistors to avoid fixed noise. 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.