Abstract:
An improved digital-to-analog converter comprises a reference node, switches providing an input digital signal, and an output stage including at least one resistive element. A resistance ladder, coupled to the switches, includes branches corresponding respectively to bit positions, in which selective operation of the switches in response to the input digital signal produces a corresponding analog output signal from the output stage. The ladder includes a first trim structure coupled to the most significant bit position (MSB) and a second trim structure in the output stage resistive element or elements. The first trim structure is configured to adjust the gain of the converter without affecting the relative bit weights of the bit positions, and wherein the resistances of the first and second trim structures are substantially of a prescribed ratio prior to any trimming.

Description:
TECHNICAL FIELD 
   This disclosure relates generally to digital-to-analog converters, and more particularly to improvements in trimming circuitry and methodology that may be implemented therein 
   BACKGROUND 
   A digital-to-analog converter (DAC) converts a digital input word to an analog output signal. DACs typically operate in either a unipolar or bipolar mode. The generic equation for determining the output V OUT  in unipolar and bipolar DACs is shown in Equation 1: 
   
     
       
         
           
             
               
                 
                   V 
                   OUT 
                 
                 = 
                 
                   G 
                   * 
                   
                     V 
                     REF 
                   
                   * 
                   
                     ( 
                     
                       
                         K1 
                         * 
                         
                           
                             INPUT 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             CODE 
                           
                           
                             2 
                             n 
                           
                         
                       
                       - 
                       K2 
                     
                     ) 
                   
                 
               
             
             
               
                 ( 
                 1 
                 ) 
               
             
           
         
       
     
   
   where INPUT CODE is an n-bit digital word, G is the gain of the DAC and K1 and K2 are constants that determine the configuration mode. In unipolar mode configuration (e.g., when the output varies from 0 volts to V REF ), K1=1 and K2=0 so that V OUT  varies between 0 and G*V REF . In bipolar mode configuration (e.g., output varies from −V REF  to V REF ), K1=2 and K2=1 so that V OUT  varies between −G*V REF  and G*V REF . For the inverting unipolar configuration K1=−1 and K2=0 so that V OUT  varies between 0 and −G*V REF . 
     FIG. 1  shows the example of a well known architecture of an inverting unipolar 3-bit DAC  10 , which receives input V REF , control signal UPDATE and digital input INPUT CODE, and generates analog output V OUT . The DAC of  FIG. 1  has 3-bit resolution (i.e. n=3) for illustration only and can easily be modified to any practical resolution desired. The digital input INPUT CODE is a 3-bit digital word used by DAC  10  to convert input V REF  into analog output V OUT . UPDATE is a binary control signal which determines when the digital word INPUT CODE can be used to convert V REF  to produce a new V OUT . When UPDATE is LOW, V OUT  remains substantially constant. When UPDATE changes from LOW to HIGH, DAC  10  converts V REF  to analog output V OUT  based on the digital input INPUT CODE. 
   DAC  10  comprises resistor ladder  12 , switches  16   1 ,  16   2  and  16   3 , switch compensation element  17   4 , switch control block  18 , op-amp  22  and feedback element  20 . Resistor ladder  12  is of a type commonly called an R-2R ladder, and includes substantially identical fixed resistors  23   11  to  23   42  and substantially identical trim structures  30   11  to  30   42 . The input V REF  is applied to input node  1  of DAC  10  while the output V OUT  is produced at output node  3 . An additional DAC node referred henceforth as GROUND is used as reference potential for both input V REF  and output V OUT . 
   Resistor ladder  12  receives the input V REF  on node  1 , is connected to switches  16   1 ,  16   2  and  16   3  through nodes  15   1 , 15   2  and  15   3 , respectively, and to switch compensation element  17   4  through node  15   4 . It comprises a number of switched and series branches. The first switched connected in series, and is coupled between input node  1  and node  15   1 . It functions as the most significant bit (MSB) of the ladder. The first series branch comprises fixed resistor  23   13  and trim structure  30   13 , connected in series, and is coupled between input node  1  and network and two trim structures  30   21  and  30   22 , all connected in series, and is coupled between internal node  4  and node  15   2 . It functions as the second bit of the ladder. The second series branch comprises fixed resistor  23   23  and trim structure  30   23 , connected in series, and is coupled between internal node  4  and internal node  5 . The third switched branch comprises two fixed resistors,  23   31 , and  23   32 , and two trim structures  30   31  and  30   32 , all connected in series, and is coupled between internal node  5  and node  15   3 . It functions as the least significant bit (LSB) structures  30   41  and  30   42 , all connected in series, and is coupled between internal node  5  and node  15   4 . It functions as the ladder termination and is connected to GROUND through the switch resistance compensation element  17   4 . 
   In describing an R-2R ladder, the series branches are conventionally called the R-branches, and the switched branches and the termination branch are called the 2R-branches. 
   Switch control block  18  receives control input UPDATE and digital input INPUT CODE. When UPDATE changes state from LOW to HIGH, switch control block  18  adjusts the states of switch control nodes  28   1  through  28   3 , according the present value of INPUT CODE. In this example of a 3-bit DAC, INPUT CODE will be a 3-bit binary signal. When the most significant bit (MSB) of INPUT CODE is HIGH, the switch control  18  will set node  28   1  directing switch  16   1  to couple node  15   1  to node  2 . When the most significant bit (MSB) of INPUT CODE is LOW, switch control  18  will set node  28   1  directing switch  16   1  to couple node  15   1  to GROUND. Similarly, a HIGH or LOW state in the second bit of INPUT CODE will result in switch control  18  setting node  28   2  directing switch  16   2  to couple node  15   2  to node  2  or GROUND respectively. A HIGH or LOW state in the third, least significant bit (LSB), of INPUT CODE will result in switch control  18  setting node  28   3  directing switch  16   3  to couple node  15   3  to node  2  or GROUND respectively. In the manner described, the digital input INPUT CODE in combination with input V REF  causes an intermediate current, I DAC  to flow into node  2  from the switch elements  16   1  to  16   3  according to Equation 2, where R DAC  is the input impedance of the R-2R ladder: 
                         I   DAC     =       (       V   REF       R   DAC       )     *     (       INPUT   ⁢           ⁢   CODE       2   n       )                   =       (       V   REF       R   DAC       )     *     (       INPUT   ⁢           ⁢   CODE     8     )                     (   2   )               
Feedback element  20  and op-amp  22  form a current-to-voltage converter. The op-amp  22  has an inverting input terminal (−) coupled to node  2 , a non-inverting input terminal (+) coupled to GROUND, and an output terminal coupled to node  3 . Feedback element  20 , coupled between node  2  and node  3 , creates a feedback loop around the op-amp  22 .
 
   Feedback element  20  comprise fixed resistor  24 , trim structure  31 , and switch resistance compensation element  17   5 , all connected in series. The total resistance of feedback element  20  is commonly referred to as R FB . 
   The current to voltage converter operates to convert intermediate current I DAC  into output voltage V OUT . The resulting V OUT  is described by Equation 3: 
   
     
       
         
           
             
               
                 
                   
                     
                       
                         V 
                         OUT 
                       
                       = 
                         
                       ⁢ 
                       
                         
                           - 
                           
                             I 
                             DAC 
                           
                         
                         * 
                         
                           R 
                           FB 
                         
                       
                     
                   
                 
                 
                   
                     
                       = 
                         
                       ⁢ 
                       
                         
                           - 
                           
                             V 
                             REF 
                           
                         
                         * 
                         
                           ( 
                           
                             
                               R 
                               FB 
                             
                             
                               R 
                               DAC 
                             
                           
                           ) 
                         
                         * 
                         
                           ( 
                           
                             
                               INPUT 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               CODE 
                             
                             
                               2 
                               n 
                             
                           
                           ) 
                         
                       
                     
                   
                 
                 
                   
                     
                       = 
                         
                       ⁢ 
                       
                         
                           - 
                           
                             V 
                             REF 
                           
                         
                         * 
                         
                           ( 
                           
                             
                               R 
                               FB 
                             
                             
                               R 
                               DAC 
                             
                           
                           ) 
                         
                         * 
                         
                           ( 
                           
                             
                               INPUT 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               CODE 
                             
                             8 
                           
                           ) 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 3 
                 ) 
               
             
           
         
       
     
   
   For the 3-bit DAC example, MAX INPUT CODE=2 3 −=7. 
   When DIGITAL INPUT=0: 
   
       
       
         
           V OUT =0V, corresponding to ZERO SCALE
 
and when DIGITAL INPUT=7:
 
         
       
     
  
               V   OUT     =       -     V   REF       *     (       R   FB       R   DAC       )     *     (     7   8     )         ,         
corresponding to FULL SCALE
 
   From equation (3), the value of V OUT  is scaled by the ratio R FB /R DAC . Comparing equations (3) and (1) it is immediate that G=(R FB /R DAC ). A common choice for a unipolar DAC is G=1 requiring R FB =R DAC . It is highly desirable for ratio G to be accurate, stable with respect to external factors like temperature, time, etc. and have minimal pre-trim errors. Thus it is common practice to maintain, with a high degree of accuracy, the same ratio G between constituent structures of the same type contained in feedback element  20  and ladder  12 . Toward this goal corresponding feedback element and ladder components of same type (i.e. fixed resistors, trim structures and switches) are implemented using mutually identical unit components with good matching properties. 
     FIG. 2  shows a known bipolar DAC  110  comprising current converter  40 , reference inverting circuit  114 , offset resistive element  125 , op-amp  22  and feedback element  120 . DAC  110  receives input V REF , control signal UPDATE and digital input INPUT CODE and generates analog output V OUT . The input V REF  is applied to input node  8  of DAC  110  while the output V OUT  is produced at output node  3 . 
   The reference inverting circuit  114 , comprising op-amp  140  and gain resistors  142  and  144  is configured as a standard inverting buffer amplifier. It has an input terminal coupled to input node  8  and an output terminal connected to internal node  1 . Input gain resistor  142  is connected between node  8  and the inverting input of op-amp  140  while feedback gain resistor  144  is connected between output and inverting input of op-amp  140 . The non-inverting input of op-amp  140  is connected to GROUND. The output of op-amp  140  is connected to internal node  1 . The reference inverting circuit  114  serves to produce an inverted V REF  (i.e., −V REF ) signal at node  1 . The Current Converter  40 , coupled between internal nodes  1  and  2  is described in detail in  FIG. 1 . 
   Alternatively, amplifier  140  and resistors  142  and  144  could be external to signal processor  110  in the signal path. 
   The offset resistive element  125 , coupled between input node  8  and internal node  2 , has an internal structure similar to feedback element  20  comprising a fixed resistor structure, a trim structure, and a switch resistance compensation element, all connected in series. The total resistance of offset resistive element  125  is referred to as R OFFSET . 
   Feedback element  120  and op-amp  22  form a current-to-voltage converter. The op-amp  22  has an inverting input terminal (−) coupled to node  2 , a non-inverting input terminal (+) coupled to GROUND, and an output terminal coupled to node  3 . Feedback element  120 , coupled between node  2  and node  3 , creates a feedback loop around the op-amp  22 . Feedback element  120  has similar internal structure as previously described feedback element  20 , and comprises a fixed resistor structure, a trim structure, and a switch resistance compensation element, all connected in series. The total resistance of feedback resistor element  120  is referred to as R FB . 
   In the same manner described above for DAC  10  of  FIG. 1 , the digital input INPUT CODE in combination with the input signal present at node  1  causes an intermediate current, I DAC  to flow into node  2  from the converter  40  according to Equation 4, where R DAC  is the input impedance of the R-2R ladder and the signal on node  1  is −V REF :
 
 I   DAC =(− V   REF   /R   DAC )·(INPUT CODE/2 n )  (4)
 
   A second signal path from input node  8  through offset resistive element  125  to node  2  causes a second intermediate current, I OFFSET  to flow into node  2  according to Equation 5:
 
 I   OFFSET =( V   REF   /R   OFFSET )  (5)
 
   The current to voltage converter operates to convert the sum of the intermediate currents I DAC  and I OFFSET  to the output V OUT . The resulting V OUT  is described by Equation 6:
 
V OUT =−(I DAC +I OFFSET )·R FB  
 
= V   REF [( R   FB   /R   DAC )*(INPUT CODE/2 n )−( R   FB   /R   OFFSET )]  (6)
 
   For a 3-bit DAC example, 2 n =8 and MAX INPUT CODE=2 3 −1=7. 
   Thus for DIGITAL INPUT=0:
 
 V   OUT   =−V   REF ·( R   FB   /R   OFFSET )
 
And for DIGITAL INPUT=7:
 
 V   OUT   =V   REF *[( R   FB   /R   DAC )*(⅞)−( R   FB   /R   OFFSET )]
 
   From equation (6), the value of V OUT  is scaled by the ratio R FB /R DAC  and is offset by the ratio R FB /R DAC . By comparison to equation (1), as K2=1 for a bipolar DAC, it results:
 
( R   FB   /R   OFFSET )=1
 
Therefore
 
R FB =R OFFSET  
 
   By further comparison to equation (1) it results:
 
 G=(   R   FB   /R   DAC )/K1
 
A common choice for a bipolar DAC is G=1, resulting in
 
 R   FB =2 *R   DAC  
 
   To maintain an accurate transfer function for DAC  110  as given by equation 6, it is therefore highly desirable for ratios R FB /R DAC , and R FB /R OFFSET  to be accurate, stable with respect to external factors like temperature, time, etc. and have minimal pre-trim errors. Thus it is common practice to maintain, with a high degree of accuracy, the same ratio between constituent structures of the same type contained in feedback element  120  and current converter  40 . Toward this goal, corresponding feedback element and current converter components of same type (i.e. fixed resistors, trim structures and switches) are implemented using mutually identical unit components with good matching properties. Furthermore it is common practice to maintain, with a high degree of accuracy, the same ratio between constituent structures of the same type contained in feedback element  120  and offset resistive element  125 . Toward this goal, corresponding feedback element and offset resistive element components of same type (i.e. fixed resistors, trim structures and switch resistance compensation structures) are implemented using mutually identical unit components with good matching properties. 
   DAC  110  shows one technique for applying opposite polarity to the current converter and to the level shift structure, a condition which is required for this type of bipolar DAC. However, other suitable techniques for establishing this condition are well-known in the art. 
   The prior art includes various configurations of DAC  10  and DAC  110  in monolithic or discrete form. The configurations are typically chosen to be unipolar, bipolar or a combination thereof, such as a software programmable signal processor of a type described in U.S. Pat. No. 6,310,567, incorporated herein by reference. 
   A person skilled in the art will be familiar with resistor ladder  12  and other versions of R-2R ladder networks, and will be aware that R-2R ladders are classic and widely employed examples of networks whose transfer functions depend primarily on the ratio matching of identical unit elements of the constituent structures. 
   Errors in resistor ladder  12 , current converter  40 , feedback elements  20  and  120  and offset resistive element  125  are caused by the resistances and switches in each of the branches not matching or ratioing exactly. It is common practice to use mutually identical unit resistors like fixed resistors  23   11  through  23   42  of resistor ladder  12  when implementing such networks in order to minimize matching errors. Nevertheless, matching errors between identical fixed elements are inherent in any practical implementation and result in transfer function linearity errors. The problem is usually alleviated by connecting adjustable structures like trim structures  30   11  through  30   42  in series with fixed resistors. Such trim structures can be adjusted in calibration processes such as to correct residual mismatch of the fixed elements. In order to further reduce mismatch errors it is common practice to use trim structures which are mutually identical prior to any trimming and to associate a trim structure to every fixed element in the network. In this manner every constituent structure of the network has the same ratio between the value and number of fixed elements to trim structures 
   Mismatch between different branches of resistor ladder  12  produce Linearity Errors in the DAC transfer function and are adjusted using the built-in trim structures  30   11  through  30   42 . Errors in R FB /R DAC  ratio introduce a gain error in transfer functions of both unipolar DAC  10  and bipolar DAC  110  commonly called Gain Error. Errors in R FB /R OFFSET  ratio introduce an undesired offset in transfer function of bipolar DAC  110  commonly called Bipolar Offset Error. Gain Errors and Bipolar Offset Errors must be corrected in a calibration process in the same manner as Linearity Errors. 
   For unipolar DAC  10  the Gain Error is commonly adjusted using the trim structure contained by feedback element  20 . For bipolar DAC  110  the Gain Error is commonly adjusted using the trim structure contained by feedback element  120 . Similarly the Bipolar Offset Error of DAC  110  is adjusted using the trim structure contained by the offset resistive element  125 . 
   When trim structures are adjusted by laser trimming of fuse links or other common techniques their value typically can only be increased. Thus, when Linearity Errors are reduced using the trim structures  30   11  through  30   42 , the ladder equivalent impedance R DAC  is increased thus changing the ratio R FB /R DAC  and producing a Gain Error. Due to this undesired interaction the Gain Error adjustment must be performed after the Linearity Error adjustment. 
   For the bipolar DAC  110 , a change in value of R FB  during Gain Error adjustment modifies the ratio R FB /R OFFSET  and thus produces a Bipolar Offset Error. Therefore for a bipolar DAC a Linearity Error adjustment must be followed by a Gain Error adjustment and subsequently by a Bipolar Offset Error adjustment. 
   A problem will occur in implementing this adjustment sequence if, following a Linearity Error correction, the ratio R FB /R DAC  is higher than desired. Because the value R FB  can only be increased through the adjustment process it is not possible to directly lower the ratio R FB /R DAC . This suggests the option of increasing the value of R DAC . However, with resistor networks commonly used in implementing DACs, a change in R DAC  will directly result in Linearity Errors. In addition many practical adjustment means, including laser trim, can be used one time only on any given trim structure. Therefore, once linearity trimming is completed it is generally not possible to make any further adjustments to the trim structures  30   11  through  30   42 . Thus the Gain Error adjustment is, for all practical purposes, a “unidirectional trim” able to correct only a negative Gain Error and must be performed after Linearity Error adjustments. 
   A common solution for this problem is to introduce a systematic negative pre-trim Gain Error so large that it will remain negative following the worst case Linearity Error adjustment. This strategy has significant undesirable consequences. It requires a substantial increase in the trim range resulting in substantially larger trim structures. Due to the “worst case” design target most DACs will need to by adjusted by large amounts resulting in excessively long trim time and increased likelihood of post-trim drift. 
   Another common solution is to add a “look-ahead” calculation and additional skew trim within the linearity trim procedure such as to insure that the Gain Error will remain slightly negative following Linearity Error adjustment. According to this strategy attempts are made to predict the resulting Gain Error at intermediary steps in the Linearity Error adjustment and corrective skew trims are applied. While preferable to the previous solution, this approach has its own undesirable consequences. The prediction process requires complex measurements and calculations which together with the additional skew trim operations substantially increase the overall adjustment time. Moreover additional trim range is still necessary forcing an increase in size for certain trim structures. An increase in size for some trim structures results in a size increase for all trim structures because, in order to reduce pre-trim matching errors, the use of mutually identical structures is highly desirable. Furthermore the prediction algorithm is complex and imperfect thus not always effective. 
   SUMMARY 
   Accordingly, one aspect of this disclosure is in providing methods and apparatus for making bi-directional trim adjustments to certain parameters, including Gain Error and Bipolar Offset Error, to digital-to-analog converters (DACs) without disturbing the DAC linearity, without introducing significant additional pre-trim systematic or random errors, and without requiring ‘look ahead’, or pre-compensation in the linearity trim procedure. 
   In accord with one implementation of the disclosure, a digital-to-analog converter comprises a reference node, switches providing an input digital signal and an output stage including at least one resistive element. A resistance ladder coupled to the switches includes branches corresponding respectively to bit positions, in which selective operation of the switches in response to the input digital signal produces a corresponding analog output signal from the output stage. A first trim structure is coupled to the most significant bit position (MSB) of the resistance ladder, and a second trim structure is provided in the at least one output stage resistive element. The first trim structure is configured to adjust the gain of the digital-to-analog converter without affecting the relative bit weights of the bit positions. The resistances of the first and second trim structures, respectively, are substantially of a prescribed ratio. 
   Additional advantages of the teachings herein will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which: 
       FIG. 1  is a circuit diagram showing a conventional unipolar DAC having trim structures. 
       FIG. 2  is a circuit diagram showing a conventional bipolar DAC having trim structures. 
       FIG. 3  is a circuit diagram showing a unipolar DAC having trim structures similar to that in  FIG. 1 , improved in accord with the principles taught herein. 
       FIG. 4  is a circuit diagram of another improved embodiment corresponding to  FIG. 2 . 
       FIG. 5  is a circuit diagram showing a Softspan™ type DAC improved in accord with the principles taught herein. 
   

   DETAILED DESCRIPTION 
     FIG. 3  shows a unipolar DAC  210  similar to DAC  10  improved according to the principles taught by the present invention. DAC  210  comprises current converter  40 , output stage  70  and first trim structure  250   1 . The input V REF  is applied to input node  9  while the output V OUT  is produced at output node  3 . An additional DAC node referred henceforth as GROUND is used as a reference potential for both input V REF  and output V OUT . 
   Current converter  40 , described in  FIG. 1  receives control input UPDATE and digital input INPUT CODE and is coupled between nodes  1 ,  2  and GROUND of DAC  210 . The output node  2  of current converter  40  is connected to input terminal of output stage  70 . The output terminal of output stage  70  is connected to output node  3  of DAC  210 . The output stage  70  comprises op-amp  22  and resistive element  60 . Resistive element  60 , comprising series combination of feedback element  20  and second trim structure  2502 , is coupled between nodes  2  and  3  implementing a feedback path around op-amp  22 . The pre-trim resistance of second trim structure  250   2  is referred to as RT 2 . DAC  210  further comprises first trim structure  250   1  coupled between input node  9  and current converter  40  input node  1 . Thus first trim structure  250   1  is coupled to the most significant bit (MSB) position of the resistance ladder  12  comprised within current converter  40 . The pre-trim resistance of first trim structure  250   1  is referred to as RT 1 . For illustrative purposes, second trim structure  250   2  is shown in  FIG. 3  coupled between feedback element  20  and output node  3 . However, it will be obvious to those skilled in the art that the relative positions of the trim structure  250   2  and the series connected components of feedback element  20  (i.e. fixed resistor  24 , trim structure  31 , and switch resistance compensation element  175 ) can be changed if desired without affecting circuit behavior. 
   DAC  210  ladder pre-trim equivalent input resistance RT DAC  is the series combination of current converter  40  equivalent input resistor R DAC  and first trim structure  250   1  pre-trim resistance RT 1  thus:
 
 RT   DAC   =R   DAC   +RT   1 .
 
The resistive element  60  pre-trim equivalent resistance RT FB  is the series combination of feedback element  20  equivalent resistance R FB  and second trim structure  250   2  pre-trim resistance RT 2  thus:
 
 RT   FB   =R   FB   +RT   2 .
 
It is apparent to persons skilled in the art that DAC  210  transfer function is described by the same equation (3) as previously derived DAC  10  transfer function in which R DAC  is replaced by RT DAC  and R FB  is replaced by RT FB . Consequently the gain G of the unipolar DAC  210  is:
 
 G=RT   FB   /RT   DAC =( R   FB   +RT   2 )/( R   DAC   +RT   1 )
 
   As aforesaid it is highly desirable for ratio G to be accurate, stable with respect to external factors like temperature, time, etc. and suffer minimal pre-trim errors. Toward this goal, first trim structure  250   1  and second trim structure  250   2  are preferably constructed of mutually identical unit components configured to make pre-trim ratio RT 2 /RT 1  equal R FB /R DAC  ratio. Thus the nominal gain ratio G of DAC  210  is substantially identical with gain ratio G of DAC  10 .
 
 RT   FB   /RT   DAC =( R   FB   +RT   2 )/( R   DAC   +RT   1 )= R   FB   /R   DAC  
 
   It should be noted that no restrictions have been introduced with respect to ratios of any one value RT 1 , RT 2  and any one value R DAC , R FB . Therefore mutually identical unit components used to construct first trim structure  250   1  and second trim structure  250   2  may differ from mutually identical unit components used to construct feedback element  20  and resistor ladder  12 . Trim structures  250   1  and  250   2  may be purposefully sized for trim range and resolution as required by Gain Error adjustment without compromising optimal sizing of feedback element  20  and resistor ladder  12  constituent trim structures. 
   Persons skilled in the art will recognized from gain ratio G expression derived above that properly sized trim structures  250   1  and  250   2  enable Gain Error adjustment for any practical ratio R FB /R DAC  that may exist following Linearity Error adjustment. 
   In a preferred method, Gain Error adjustment is performed in two steps, following Linearity Error adjustment. Current converter  40  equivalent input resistor changes from pre-trim nominal value R DAC  to post-trim value RPT DAC  following Linearity Error adjustment. In first step of Gain Error adjustment trim structures  250   1  and  250   2  are adjusted from nominal pre-trim values RT 1  and RT 2  to equal or greater post-trim values RTPT 1  and RTPT 2  respectively. In second step of Gain Error adjustment the equivalent value of feedback element  20  is adjusted from pre-trim nominal value R FB  to an equal or greater post-trim value RPT FB . 
   The gain ratio G following Linearity Error adjustment
 
 G =( R   FB   +RT   2 )/( RPT   DAC   +RT   1 )
 
may be less or greater than a final target value. The first step of Gain Error adjustment shall insure that ratio G is less than the target value and close enough to said target value for the residual gain error to fall within the trim range of feedback element  20 . Thus, if ratio G is greater than target value, trim structure  250   1  should be adjusted increasing RT 1  accordingly. If ratio G is less than target value, trim structure  250   2  should be adjusted increasing RT 2  accordingly. It is commonly known that under certain conditions multiple sequential iterative adjustments of both trim structures  250   1  and  250   2  may be desirable in order to reduce trim resolution requirement. Trim structures  250   1  and  250   2  should be sized recognizing that the trim range available must be large enough to account for worst case changes in R DAC  following Linearity Error adjustment and for worst case pre-trim errors in R FB  value. The trim resolution built in at least one of trim structures  250   1  and  250   2  must be fine enough to lower the residual gain error of ratio G with respect to target within the trim range available in feedback element  20 .
 
   Gain ratio G, following first step of Gain Error adjustment is:
 
 G =( R   FB   +RTPT   2 )/( RPT   DAC   +RTPT   1 )
 
The second step of Gain Error adjustment should make ratio G substantially equal to target value using the trim element contained within feedback element  20 .
 
An additional benefit of the present invention and preferred method is reduced trim resolution for trim structures  250   1  and  250   2 . As aforementioned, in the desire to reduce pre-trim matching errors, mutually identical unit components are commonly used in implementing constituent trim elements for feedback element  20  and resistor ladder  12 . Thus the trim resolution available within feedback element  20  is very fine as it must match the trim resolution required by Linearity Error adjustment. Using this inherent fine resolution in second step of Gain Error adjustment substantially reduces the trim resolution required from trim structures  250   1  and  2502 .
 
     FIG. 4  shows a bipolar DAC  410  similar to DAC  110  improved according to the present invention. DAC  410  comprises current converter  40 , output stage  170 , reference inverting circuit  114 , offset resistive element  125 , first trim structure  350   1  and third trim structure  350   3 . The input V REF  is applied to input node  8  while the output V OUT  is produced at output node  3 . An additional DAC node referred henceforth as GROUND is used as a reference potential for both input V REF  and output V OUT . 
   Current converter  40 , described in  FIG. 1  receives control input UPDATE and digital input INPUT CODE and is coupled between nodes  1 ,  2  and GROUND of DAC  310 . The output node  2  of current converter  40  is connected to input terminal of output stage  170 . The output terminal of output stage  170  is connected to output node  3  of DAC  310 . 
   The output stage  170  comprises op-amp  22  and resistive element  160 . Resistive element  160 , comprising series combination of feedback element  120  and second trim structure  350   2 , is coupled between nodes  2  and  3  implementing a feedback path around op-amp  22 . The pre-trim resistance of second trim structure  350   2  is referred to as RT 2 . For illustrative purposes, second trim structure  350   2  is shown in  FIG. 4  coupled between feedback element  120  and output node  3 . However, it will be apparent to those skilled in the art that the relative positions of trim structure  350   2  and the series connected components of feedback element  120  (i.e. fixed resistor, trim structure, and switch resistance compensation element) can be changed if desired without affecting circuit behavior. 
   The reference inverting circuit  114  described in  FIG. 2  receives input signal V REF  through an input terminal connected to input node  8  and has an output terminal connected at internal node  61  to the first trim structure  350   1 . First trim structure  350   1  is coupled between reference inverting circuit output node  61  and current converter  40  input node  1 . Thus first trim structure  350   1  is coupled to the most significant bit (MSB) position of the resistance ladder  12  comprised within current converter  40 . The pre-trim resistance of first trim structure  350   1  is referred to as RT 1 . 
   DAC  310  further comprises the series connection of third trim structure  350   3  and offset resistive element  125  coupled between input node  8  and output stage  170  input node  2 . The pre-trim resistance of third trim structure  350   3  is referred to as RT 3 . For illustrative purposes, trim structure  350   3  is shown in  FIG. 4  coupled between offset resistive element  125  and input node  8 . However, it will be apparent to those skilled in the art that the relative positions of trim structure  350   3  and the series connected components of offset resistive element  125  (i.e. fixed resistor, trim structure, and switch resistance compensation element) can be changed if desired without affecting circuit behavior. 
   DAC  310  ladder pre-trim equivalent input resistance RT DAC  is the series combination of current converter  40  equivalent input resistor R DAC  and first trim structure  350   1  pre-trim resistance RT 1  thus:
 
 RT   DAC   =R   DAC   +RT   1 .
 
The output stage resistive element  160  pre-trim equivalent resistance RT FB  is the series combination of feedback element  20  equivalent resistance R FB  and second trim structure  3502  pre-trim resistance RT 2  thus:
 
 RT   FB   =R   FB   +RT   2 .
 
The pre-trim total equivalent offset resistance RT OFFSET  of DAC  310  is the series combination of offset resistive element  125  equivalent resistance R OFFSET  and third trim structure  350   3  pre-trim resistance RT 3  thus:
 
RT OFFSET   =R   OFFSET   +RT   3 .
 
It is apparent to persons skilled in the art that DAC  310  transfer function is described by the same equation (6) as previously derived DAC  110  transfer function in which R DAC  is replaced by RT DAC , R FB  is replaced by RT FB , and R OFFSET  is replaced by RT OFFSET . Consequently the gain G and coefficient K2 of the bipolar DAC  310  are:
 
 G=RT   FB   /RT   DAC =( R   FB   +RT   2 )/( R   DAC   +RT   1 )
 
 K 2= RT   FB   /RT   OFFSET =( R   FB   +RT   2 )/( R   OFFSET   +RT   3 )
 
   As aforesaid it is highly desirable for ratio G to be accurate, stable with respect to external factors like temperature, time, etc. and suffer minimal pre-trim errors. It is similarly highly desirable for offset ratio K2 to equal 1 as to minimize DAC offset errors. Toward this goal, first trim structure  350   1 , second trim structure  350   2  and third trim structure  350   3  are preferably constructed of mutually identical unit components configured to make pre-trim ratio RT 2 /RT 1  equal R FB /R DAC  ratio and pre-trim ratio RT 2 /RT 3  equal R FB /R OFFSET  ratio. Thus the nominal gain ratio G of DAC  310  is substantially identical with gain ratio G of DAC  110 .
 
 RT   FB   /RT   DAC =( R   FB   +RT   2 )/( R   DAC   +RT   1 )= R   FB   /R   DAC  
 
   Similarly the nominal offset ratio K2 of DAC  310  is substantially identical with offset ratio K2 of DAC  110 .
 
 RT   FB   /RT   OFFSET =(R FB +RT 2 )/(R OFFSET +RT 3 )=R FB /R OFFSET  
 
   It should be noted that no restrictions have been introduced with respect to ratios of any one value RT 1 , RT 2 , RT 3  and any one value R DAC , R FB , R OFFSET . Therefore mutually identical unit components used to construct first trim structure  350   1 ; second trim structure  350   2  and third trim structure  350   3  may differ from mutually identical unit components used to construct feedback element  20  and resistor ladder  12 . Trim structures  350   1 ,  350   2  and  350   3  may be purposefully sized for trim range and resolution as required by Gain Error adjustment and Bipolar Offset Error adjustment without compromising optimal sizing of feedback element  20  and resistor ladder  12  constituent trim structures. 
   Persons skilled in the art will recognized from gain ratio G and offset ratio K2 expressions derived above that properly sized trim structures  350   1 ,  350   2  and  350   3  enable Gain Error and Bipolar Offset Error adjustment for any practical ratio R FB /R DAC  that may exist following Linearity Error adjustment and any practical pre-trim error in ratio R FB /R OFFSET . 
   In a preferred method, Gain Error and Bipolar Offset Error adjustment is performed in four steps, following Linearity Error adjustment. Current converter  40  equivalent input resistor changes from pre-trim nominal value R DAC  to post-trim value RPT DAC  following Linearity Error adjustment. In first step of Gain Error and Bipolar Error adjustment trim structures  350   1  and  350   2  are adjusted from nominal pre-trim values RT 1  and RT 2  to equal or greater post-trim values RTPT 1  and RTPT 2  respectively. In second step the equivalent value of feedback element  20  is adjusted from pre-trim nominal value R FB  to an equal or greater post-trim value RPT FB . In third step the trim structure  350   3  is adjusted from nominal pre-trim value RT 3  to an equal or greater post-trim value RTPT 3 . In the forth step the equivalent value of offset resistive element  125  is adjusted from pre-trim nominal value R OFFSET  to an equal or greater post-trim value RPT OFFSET . 
   Gain ratio G and offset ratio K2 following Linearity Error adjustment are:
 
 G =( R   FB   +RT   2 )/( RPT   DAC   +RT   1 )
 
K2=( R   FB   +RT   2 )/( R   OFFSET   +RT   3 )
 
The Linearity Error adjustment may produce a gain ratio G less or greater than a final gain target value and does not modify offset ratio K2. The first step shall insure that ratio G is less than the gain target value and close enough to said target value for the residual gain error to fall within the trim range of feedback element  20 . Furthermore, for a bipolar DAC, the first step must insure that, following second step of this method, offset ratio K2 will be greater than the offset target value (commonly unity) and close enough to said target value for the residual offset error to fall within the trim range of trim structure  350   3  and offset resistive element  125 . A predictive algorithm is still required at the beginning of the first step but the use of purposely sized trim structures  350   1 ,  350   2  and  350   3  substantially reduces its complexity. The estimation is performed using commonly known algorithms and is based upon the evaluation of gain ratio G and offset ratio K2 following Linearity Error adjustment. The first step adjusts trim structure  350   1  and/or trim structure  350   2  increasing RT1 and/or RT2 accordingly. Trim structures  350   1  and  350   2  should be sized recognizing that the trim range available must be large enough to account for worst case changes in R DAC  following Linearity Error adjustment and for worst case pre-trim errors in R FB  and R OFFSET  values. The trim resolution of trim structures  350   1  and  350   2  must be fine enough to lower the residual gain error of ratio G with respect to target within the trim range available in feedback element  20 .
 
   Gain ratio G and offset ratio K2 following first step of Gain Error and Bipolar Offset Error adjustment are:
 
 G =( R   FB   +RTPT   2 )/( RPT   DAC   +RTPT   1 )
 
 K 2=( R   FB   +RTPT   2 )/( R   OFFSET   +RT   3 )
 
The second step should make gain ratio G substantially equal to gain target value using the trim element contained within feedback element  20 . Consequently the nominal value R FB  is changed into RPT FB .
 
   Offset ratio K2 following second step of Gain Error and Bipolar Offset Error adjustment is:
 
K2=(RPT FB +RTPT 2 )/(R OFFSET +RT 3 )
 
The predictive calculations of the first step insure that the offset ratio K2 is greater than the offset target. The third step should bring offset ratio K2 close enough to said target value for the residual offset error to fall within the trim range of offset resistive element  125 . Consequently the nominal value RT 3  is changed into RPT 3 .
 
   Offset ratio K2 following third step of Gain Error and Bipolar Offset Error adjustment is:
 
 K 2=( RPT   FB   +RTPT   2 )/( R   OFFSET   +RTPT   3 )
 
The fourth and final step should make offset ratio K2 substantially equal to offset target value using the trim element contained within offset resistive element  125 . Consequently the nominal value R OFFSET  is changed into RPT OFFSET .
 
An additional benefit of the present invention and preferred method is reduced trim resolution for trim structures  350   1 ,  350   2  and  350   3 . As aforementioned, in the desire to reduce pre-trim matching errors, mutually identical unit components are commonly used in implementing constituent trim elements for feedback element  20 , resistor ladder  12  and offset resistive element  125 . Thus the trim resolution available within feedback element  20  and offset resistive element  125  is very fine as it must match the trim resolution required by Linearity Error adjustment. Using this inherent fine resolution in second and fourth steps of Gain Error adjustment substantially reduces the trim resolution required from trim structures  350   1 ,  350   2  and  350   3 .
 
     FIG. 5  shows Softspan™ unipolar DAC  410  of a type described in U.S. Pat. No. 6,310,567, incorporated herein by reference, and improved according to the principles taught by the present invention. DAC  410  comprises current converter  40 , output stage  470  and first trim structure  450   1 . The input V REF  is applied to input node  9  while the output V OUT  is produced at output node  3 . An additional DAC node referred henceforth as GROUND is used as a reference potential for both input V REF  and output V OUT . DAC  410  receives control signal UPDATE and digital input INPUT CODE coupled to current converter  40  and control signal SPAN coupled to output stage  470 . 
   Current converter  40 , described in  FIG. 1  receives control input UPDATE and digital input INPUT CODE and is coupled between nodes  1 ,  2  and GROUND of DAC  410 . The output node  2  of current converter  40  is connected to input terminal of output stage  470 . 
   The output terminal of output stage  470  is connected to output node  3  of DAC  410 . The output stage  470  comprises op-amp  22 , resistive elements  461  and  462  and span control block  418 . Resistive elements  461  and  462  are coupled in a parallel combination between nodes  2  and  3  implementing a double feedback path around op-amp  22 . 
   Resistive element  461  comprises series combination of feedback element  20  and second trim structure  450   2 . The pre-trim resistance of second trim structure  450   2  is referred to as RT 2 . The feedback element  20  comprises the series combination of fixed resistor  24 , trim structure  31  and switch resistance compensation element  175 . The equivalent resistance of feedback element  20  is referred to as R FB . The resistive element  461  pre-trim equivalent resistance RT FB  is the series equivalent of feedback element  20  equivalent resistance R FB  and second trim structure  450   2  pre-trim resistance RT 2  thus:
 
 RT   FB   =R   FB   +RT   2 .
 
   Resistive element  462  comprises series combination of feedback element  420  and third trim structure  450   3  and functions as programmable feedback element for op-amp  22 . The pre-trim resistance of third trim structure  450   3  is referred to as RT 3 . The feedback element  420  comprises series combination of fixed resistor  424  and trim structure  431  coupled to switch  416  through node  415 . Switch  416  couples node  415  to node  2  or GROUND as directed by state of node  428  thus changing the feedback network of op-amp  22 . Switch  416  is coupled through node  428  to span control block  418 . The equivalent resistance of feedback element  420  is referred to as RS FB . The resistive element  462  pre-trim equivalent resistance RST FB  is the series equivalent of feedback element  420  equivalent resistance RS FB  and third trim structure  450   3  pre-trim resistance RT 3  thus:
 
 RST   FB   =RS   FB   +RT   3 .
 
   Span control block  418  receives control signal SPAN and accordingly sets node  428  directing switch  416  position thus modifying the overall gain of DAC  410 . In a first state, when switch  416  couples between node  415  and GROUND, op-amp  22  feedback path includes only resistive element  461  and has equivalent pre-trim resistance value RT FB . In a second state, when switch  416  couples between nodes  415  and  2 , op-amp  22  feedback path includes the parallel combination of resistive elements  461  and  462  and has equivalent pre-trim resistance value RT2 FB =RT FB ∥RST FB . 
   DAC  410  further comprises first trim structure  450   1  coupled between input node  9  and current converter  40  input node  1 . Thus first trim structure  450   1  is coupled to the most significant bit (MSB) position of the resistance ladder  12  comprised within current converter  40 . The pre-trim resistance of first trim structure  450   1  is referred to as RT 1 . For illustrative purposes, second trim structure  450   2  is shown in  FIG. 5  coupled between feedback element  20  and output node  3 . However, it will be apparent to those skilled in the art that the relative positions of the trim structure  450   2  and the series connected components of feedback element  20  (i.e. fixed resistor  24 , trim structure  31 , and switch resistance compensation element  17   5 ) can be changed if desired without affecting circuit behavior. It should be similarly recognized that the relative positions of trim structure  450   3  and the series connected components of feedback element  420  (i.e. fixed resistor  424 , trim structure  431 , and switch  416 ) can be changed if desired without affecting circuit behavior. 
   DAC  410  ladder pre-trim equivalent input resistance RT DAC  is the series combination of current converter  40  equivalent input resistor R DAC  and first trim structure  450   1  pre-trim resistance RT 1  thus:
 
 RT   DAC   =R   DAC   +RT   1 .
 
It is apparent to persons skilled in the art that DAC  410  transfer function is described by the same equation (3) as previously derived DAC  10  transfer function in which R DAC  is replaced by RT DAC  and R FB  is replaced by RT FB  in first state of control signal SPAN and by RT2 FB  in second state of control signal SPAN. If DAC  410  overall gain is referred to as G1 in first state of control signal SPAN and as G2 in second state of control signal SPAN than:
 
 G 1 =RT   FB   /RT   DAC =( R   FB   +RT   2 )/( R   DAC   +RT   1 )
 
 G 2= RT 2 FB   /RT   DAC =[( R   FB   +RT   2 )|( RS   FB   +RT   3 )]/( R   DAC   +RT   1 )
 
   As aforesaid it is highly desirable for ratios G1 and G2 to be accurate, stable with respect to external factors like temperature, time, etc. and suffer minimal pre-trim errors. Toward this goal, first trim structure  450   1 , second trim structure  450   2  and third trim structure  450   3  are preferably constructed of mutually identical unit components configured to make pre-trim ratio RT 2 /RT 1  equal ratio R FB /R DAC  and ratio RT 3 /RT 2  equal ratio RS FB /R FB . Thus the nominal gain ratios G1 and G2 of DAC  410  are substantially independent of pre-trim absolute value of trim structures  450   1 ,  450   2  and  450   3 :
 
 G 1 =RT   FB   /RT   DAC   =R   FB   /R   DAC  
 
 G 2= RT 2 FB   /RT   DAC =( R   FB   ∥RS   FB )/ R   DAC  
 
   It should be noted that no restrictions have been introduced with respect to ratios of any one value RT 1 , RT 2  RT 3  and any one value R DAC , R FB , RS FB . Therefore mutually identical unit components used to construct first trim structure  450   1 , second trim structure  450   2  and third trim structure  450   3  may differ from mutually identical unit components used to construct feedback element  20 , feedback element  420  and resistor ladder  12 . Trim structures  450   1 ,  450   2  and  450   3  may be purposefully sized for trim range and resolution as required by Gain Error adjustment without compromising optimal sizing of feedback element  20 , feedback element  420  and resistor ladder  12  constituent trim structures. 
   Persons skilled in the art will recognized from gain ratios G1 and G2 expression derived above that properly sized trim structures  450   1 ,  450   2  and  450   3  enable Gain Error adjustment for any practical ratios R FB /R DAC  and RS FB /R DAC  that may exist following Linearity Error adjustment. 
   In a preferred method, Gain Error adjustment is performed in four steps, following Linearity Error adjustment. Current converter  40  equivalent input resistor changes from pre-trim nominal value R DAC  to post-trim value RPT DAC  following Linearity Error adjustment. In first step of Gain Error adjustment trim structures  450   1  and  450   2  are adjusted from nominal pre-trim values RT 1  and RT 2  to equal or greater post-trim values RTPT 1  and RTPT 2  respectively. In second step the equivalent value of feedback element  20  is adjusted from pre-trim nominal value R FB  to an equal or greater post-trim value RPT FB . In third step the trim structure  350   3  is adjusted from nominal pre-trim value RT 3  to an equal or greater post-trim value RTPT 3 . In the forth step the equivalent value of feedback element  420  is adjusted from pre-trim nominal value RS FB  to an equal or greater post-trim value RSPT FB . 
   Gain ratios G1 and G2 following Linearity Error adjustment are:
 
 G 1=( R   FB   +RT   2 )/( RPT   DAC   +RT   1 )
 
 G 2=[( R   FB   +RT   2 )∥( RS   FB   +RT   3 )]/( RPT   DAC   +RT   1 )
 
The Linearity Error adjustment may produce gain ratio G1 less or greater than a final first gain target value and gain ratio G2 less or greater than a final second gain target value. The first step shall insure that ratio G1 is less than the first gain target value and close enough to said target value for the residual gain error to fall within the trim range of feedback element  20 . Furthermore, the first step must insure that, following second step of this method, gain ratio G2 will be less than the second gain target value and close enough to said target value for the residual gain error to fall within the trim range of trim structure  450   3  and feedback element  420 . A predictive algorithm is still required at the beginning of the first step but the use of purposely sized trim structures  450   1 ,  450   2  and  450   3  substantially reduces its complexity. The estimation is performed using commonly known algorithms and is based upon the evaluation of gain ratios G1 and G2 following Linearity Error adjustment. The first step adjusts trim structure  450   1  and/or trim structure  450   2  increasing RT1 and/or RT2 accordingly. Trim structures  450   1  and  450   2  should be sized recognizing that the trim range available must be large enough to account for worst case changes in R DAC  following Linearity Error adjustment and for worst case pre-trim errors in R FB  and RS FB  values. The trim resolution of trim structures  450   1  and  450   2  must be fine enough to lower the residual gain error of ratio G1 with respect to first gain target within the trim range available in feedback element  20 .
 
   Gain ratios G1 and G2 following first step of Gain Error adjustment are:
 
 G 1=( R   FB   +RTPT   2 )/( RPT   DAC   +RTPT   1 )
 
 G 2=[( R   FB   +RTPT   2 )∥( RS   FB   +RT   3 )]/( RPT   DAC   +RTPT   1 )
 
The second step should make gain ratio G1 substantially equal to first gain target value using the trim element contained within feedback element  20 . Consequently the nominal value R FB  is changed into RPT FB .
 
   Gain ratio G2 following second step of Gain Error adjustment is:
 
 G 2=[( RPT   FB   +RTPT   2 )∥( RS   FB   +RT   3 )]/( RPT   DAC   +RTPT   1 )
 
The predictive calculations of the first step insure that the gain ratio G2 is less than the second gain target. The third step should bring gain ratio G2 close enough to said target value for the residual gain error to fall within the trim range of feedback element  420 . Consequently the nominal value RT 3  is changed into RPT 3 .
 
   Gain ratio G2 following third step of Gain Error adjustment is:
 
 G 2=[( RPT   FB   +RTPT   2 )∥( RS   FB   +RTPT   3 )]/( RPT   DAC   +RTPT   1 )
 
The fourth and final step should make gain ratio G2 substantially equal to second gain target value using the trim element contained within feedback element  420 . Consequently the nominal value RS FB  is changed into RSPT FB .
 
   An additional benefit of the present invention and preferred method is reduced trim resolution for trim structures  450   1 ,  450   2  and  450   3 . As aforementioned, in the desire to reduce pre-trim matching errors, mutually identical unit components are commonly used in implementing constituent trim elements for feedback element  20 , feedback element  420  and resistor ladder  12 . Thus the trim resolution available within feedback element  20  and feedback element  420  is very fine as it must match the trim resolution required by Linearity Error adjustment. Using this inherent fine resolution in second and fourth steps of Gain Error adjustment substantially reduces the trim resolution required from trim structures  450   1 ,  450   2  and  450   3 . 
   In the example described above, of the principles of the invention are presented within the context of a Softspan™ unipolar DAC. However, persons skilled in this art will readily appreciate that the principles are equally applicable to a Softspan™ bipolar DAC. This can easily be accomplished for example by replacing the feedback resistive element of  FIG. 4  with one or more parallel structures that are substantially equal to the switched feedback leg presented in  FIG. 5 . The bipolar configuration may, for example, comprise four or more trim structures, wherein one or more trim structures is coupled to an offset resistive element and two or more trim structures coupled to respective output stage resistive elements. Further details are not presented, for brevity, as such would be apparent. 
   For illustrative purposes, this invention has been described for embodiments containing resistor ladder DACs of the R-2R ladder type. A person skilled in the art will see that the invention also applies directly to other known types of DAC resistor networks, including, but not limited to “segmented” and “partially segmented” resistor ladders. For brevity, embodiments of segmented and partially segmented resistor ladders are not described herein, as such are well known to persons skilled in this art. Examples of a segmented resistor ladder architecture may be found in the LTC 1599 DAC and other LTC 159x products. A description of the LTC 1599 DAC, for example, may be found in Linear Technology Databook for LTC 1599, 16-Bit Wide, Low Glitch Muliplying DACs with 4-Quadrant Resistors, incorporated herein by reference. 
   The problem to be solved and invention are shown herein using examples of trim structures which can be adjusted only by increasing their equivalent value. To a person skilled in the art, it will be obvious that the invention applies equally to alternative embodiments where the trim structure can only be adjusted by decreasing their equivalent value. Furthermore the invention applies equally to alternative embodiments using any trim structures, said embodiments experiencing interaction between successive error adjustments. 
   In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.