Abstract:
An apparatus comprising a native device coupled to an input of an amplifier. The native device is configured to provide a high voltage protection in response to an enable signal.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method and/or architecture for implementing differential amplifiers generally and, more particularly, to a method and/or architecture for implementing a low voltage differential amplifier with high voltage protection. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits (ICs) can be required to operate with secondary devices that can have a variety of supply voltages. If the IC is implemented using low voltage, thin oxide devices, but needs to operate with devices that use higher voltages, some sort of protection needs to be provided for the low voltage devices. FIG. 1 illustrates a conventional circuit  10  that uses thick oxide devices for high voltage protection. Such conventional approaches use high voltage devices HV 1 , HV 2 , HV 3  and HV 4  to implement an input differential amplifier. 
     Such an approach has the disadvantage of a reduced input common mode range due to a high threshold voltage Vt of the thick oxide devices HV 1 , HV 2 , HV 3  and HV 4 . Also, such an approach requires a larger silicon area to implement and has slower performance. The high voltage devices HV 1 , HV 2 , HV 3  and HV 4  are larger, which impacts the size and the parasitic capacitance of the circuit  10 . 
     FIG. 2 illustrates a conventional circuit  30  implementing high voltage complementary switches HV 1  and HV 2  (each comprising a p-channel and an n-channel device) to protect the input devices LV 1  and LV 2  of the low voltage input differential amplifier  32 . The circuit  30  has the disadvantage of implementing a combination of high voltage thresholds and a low voltage gate bias, which causes an input voltage region in which signals can not be passed to the low voltage amplifier  32 . This region is referred to as the dead zone, as shown in FIG. 3, where Vin is an input voltage. For example, if the n-channel device threshold voltage Vtn is 1.0V, the p-channel device threshold voltage Vtp is −1.0V, and the control voltages LV 13  COMP 13  EN and LV 13  COMP 13  ENb are 1.8V and 0.0V respectively, neither device of the complementary switches HV 1  and HV 2  will be turned on when the input level is between 0.8V and 1V. The dead zone region will be exaggerated as the control voltage LV 13  COMP 13  EN is reduced. 
     Both the circuit  10  and the circuit  30  do not meet the speed objective for the input paths of modern integrated circuits. Also, the circuit  30  fails to pass (or propagate) input levels residing within the dead zone, which is undesirable. 
     It would be desirable to implement a low voltage differential amplifier with high voltage protection that does not have a dead zone and does not sacrifice other performance specifications, such as speed, die size, input common mode range, etc. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a native device coupled to an input of an amplifier. The native device is configured to provide high voltage protection in response to an enable signal. 
     The objects, features and advantages of the present invention include implementing a low voltage differential amplifier that may (i) implement fast signal propagation through the differential amplifier; (ii) implement a simple high voltage protection scheme without requiring a voltage pump or voltage reference circuit; (iii) avoid input level dead zone regions that may be associated with conventional approaches; and/or (iv) allow the differential amplifier to be implemented with low voltage devices, which may yield a wide input common mode range and lower parasitic capacitance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a diagram of a conventional differential amplifier using thick oxide devices; 
     FIG. 2 is a diagram of a conventional differential amplifier using thin oxide devices with high voltage complementary switches connected to the amplifier inputs; 
     FIG. 3 is a diagram illustrating a dead zone created by the circuit of FIG. 2; 
     FIG. 4 is a block diagram of a preferred embodiment of the present invention; and 
     FIG. 5 is a diagram illustrating a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 4, a block diagram of a circuit  50  is shown illustrating a context of a preferred embodiment of the present invention. The circuit  50  generally comprises an I/O pad  52 , a voltage reference (VREF) pad  54  and an amplifier  56 . A positive input of the amplifier  56  may receive a signal from the I/O pad  52 . A negative input of the amplifier  56  may receive a signal from the VREF pad  54 . 
     Referring to FIG. 5, a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  may be similar to the amplifier  56 . The circuit  100  generally comprises an amplifier block (or circuit)  102 , a protection device M 3  and a clamp block (or circuit)  104 . The clamp section  104  and the protection device M 3  may be implemented between an input signal (e.g., VIN+) and an input (e.g., V+) of the amplifier circuit  102 . The amplifier circuit  102  is shown implemented as a differential amplifier. However, the amplifier circuit  102  may be implemented as a single ended amplifier (not shown). A single ended amplifier would only have one input. If the amplifier circuit  102  is implemented as a differential amplifier, a clamp block (or circuit)  104 ′ and a protection device M 3 ′ may be implemented between an input signal (e.g., VIN−) and an input (e.g., V−) of the amplifier circuit  102 . 
     The circuit  100  uses, in one example, a high voltage n-channel native device (e.g., the protection device M 3 ) with a gate connected to a signal LV 13  COMP 13  EN, whose high level is the internal regulator supply level. The low voltage devices within the differential amplifier  102  are protected since the native device M 3  does not allow voltage levels higher than the regulated supply (VCC), which is a low voltage supply, to pass to the input of the differential amplifier  102 . The circuit  100  may reliably pass all specified input levels required for low voltage input standards. 
     The clamp circuit  104  generally comprises a transistor M 1  and a transistor M 2 . The amplifier section  102  generally comprises a number of devices LV 1 , LV 2 , LV 3  and LV 4 . The devices LV 1 , LV 2 , LV 3  and LV 4  may be implemented as low voltage devices having a thin oxide. In general, the lower the operating voltage of a device, the thinner the oxide. If the differential input signals VIN+ and VIN+ are high voltage signals, they must be reduced in voltage before being presented to the amplifier circuit  102 . 
     The circuit  100  provides protection to the low voltage differential inputs V+ and V− of the amplifier circuit  102 . Such protection allows the amplifier circuit  102  to be implemented using thin oxide devices. The circuit  100  may allow input voltages VIN+ and VIN− that satisfy low voltage differential input standards (e.g., the low voltage input standards HSTL, GLT+, etc.) while protecting the low voltage differential amplifier  102  when the inputs VIN+ and VIN− are driven to higher voltages for high voltage standards. 
     The device M 3  may be implemented as an n-channel native device. A native device may be a device where the threshold voltage (e.g., Vt) may be zero, or near zero. While such native devices may be difficult to control (e.g., turn off) in certain applications, native devices can be used in the context of the present invention to provide voltage protection. By implementing the native device M 3 , the dead zone region of FIG. 3 is eliminated. However, high voltage protection is still provided since the gate of the native device M 3  is controlled by a signal (e.g., LV_COMP_EN) whose high level does not exceed the internal regulated supply. In one example, the signal LV 13  COMP 13  EN may be implemented as an enable signal. A digital complement (e.g., LV 13  COMP 13  ENb) of the signal LV 13  COMP 13  EN may control the clamp  104 . 
     The n-channel native device M 3  may be implemented with a device threshold near (e.g., +/−200 mV) 0V to protect the input circuitry in the differential amplifier  102 . The gate of the native device M 3  is held low when the input is configured for high voltage operation (in which case a different input circuit is used to support a high voltage input standard). The gate of the device M 3  is pulled high (e.g., to 1.8V for a 1.8V supply, 2.5V for a 2.5V supply, ect.) when the input is configured for the differential amplifier  102  is to be used for a low voltage input standard. 
     The transistor diode M 1  of the clamp circuit  104  may be an optional device that may prevent current flow when the gate of the native device M 3  is grounded. Without the transistor diode M 1 , a current path may exist when the threshold of the native device M 3  is negative, since grounding the gate would not turn off the native device M 3 . In certain design applications, such an effect may be minimal and the transistor diode M 1  may be eliminated. The transistor diode M 1  may also prevent the gate of the differential amplifier  102  from either floating or coupling high enough to cause damage to the thin oxide devices LV 3  and LV 4 . Again, in certain design applications, such an effect may be minimal and the transistor diode M 1  may be eliminated. The circuit  100  generally provides high voltage protection, passes a wide range of input levels, and has speed and common mode range benefits from the low voltage differential amplifier  102 . 
     The circuit  100  implements high voltage protection without using a voltage pump or similar voltage reference circuit and uses relatively little silicon area. The low voltage devices M 1  and M 2  are included to prevent a DC current path when the gate of the native device M 3  is forced to ground and the native threshold is negative. The devices M 1  and M 2  may also protect the gate oxide of the low voltage devices LV 3  and LV 4  when the differential amplifier  102  is in a disabled state and the node voltage V+ attempts to float too high. 
     The circuit  100  may provide faster signal propagation through the differential amplifier  102  than the circuits discussed in the background section. In one example, the circuit  100  may implement a simple three device high voltage protection scheme (e.g., the devices M 1 , M 2  and M 3 ) without requiring a voltage pump or voltage reference circuit. The circuit  100  may be implemented without a dead zone region, therefore accommodating a wide range of input levels. The circuit  100  may allow the differential amplifier  102  to be implemented with low voltage devices LV 1 , LV 2 , LV 3  and LV 4 , which may yield a wide input common mode range and lower parasitics. 
     The circuit  100  may protect thin oxide devices from damage when input signals are driven to high voltage levels. The circuit  100  may protect thin oxide devices from damage without distorting the input signal to the differential amplifier  102 . The circuit  100  may protect thin oxide devices from damage without DC shifting the input signals to the differential amplifier  102 . The circuit  100  may protect thin gate oxide devices from damage while not (significantly) slowing down the input to the amplifier  102 . 
     Alternatively, the circuit  100  may be used with any input buffer design that requires high voltage protection (e.g., single ended or differential amplifiers). The invention provides a simple, non-analog method for protecting low voltage input circuits. The implementation of the native device M 3  may provide a signal with low distortion. The diode connected low voltage device M 1  may eliminate the DC current path that is normally a major concern when designing with device thresholds that can be either positive or negative. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.