Abstract:
An electronic balance having a strain gauge transducer. The analog output signal of the transducer is processed digitally so that the displayed weight is based on several successive digitized analog signal samples. Various operating parameters (e.g., conversion factors for several different units of weight) are stored in a non-volatile memory so that the scale can perform various weighing functions. The scale has a parts counter mode of operation requiring re-taring of the parts container whenever the scale is recalibrated for a different individual part weight.

Description:
BACKGROUND OF THE INVENTION 
     The present application pertains generally to the field of precision balances, and more particularly pertains to the field of electronic balances. 
     A precise, and yet relatively inexpensive, balance capable of providing a weight accurate, e.g., to one part per thousand, in a reasonably short time would be highly desirable. 
     SUMMARY OF THE INVENTION 
     The principal object of the present invention is to provide an electronic balance of relatively low cost and high precision. 
     Another object of the invention is to provide such a balance comprising a strain gauge transducer. 
     Another object of the invention is to provide such a balance capable of expressing a measured weight in any of several units, and capable of stabilizing the output with a precision that varies as a function of the units selected. 
     The present invention, in one aspect, is an electronic balance comprising a transducer, preferably a strain gauge, to generate an analog electrical signal representative of the weight being measured, an analog-to-digital converter to generate a series of digital signals representative of the information conveyed by the analog signal, and a filter capable of filtering a portion of the series of digital signals at once. This permits one portion of the data obtained during the measurement of a weight to be processed digitally while a later-obtained portion of the data is being converted from analog to digital form. The analog to digital conversion can be carried out with resolution less that what would be necessary to obtain the desired precision if the final output of the balance were derived from a single portion of the data only. 
     In another aspect, the present invention is an electronic balance having a non-volatile memory in which are stored conversion factors for converting processed data into weights expressed in any of several conventional units (grams, ounces, carats, etc.). The units in which a particular balance can express weights are selected permanently in the factory from among those for which conversion factors are stored in the memory, e.g., by means of a logic mask. Alternatively, the memory may store general sets of constants necessary for analyzing the data, the sets corresponding respectively to different full-scale ranges (e.g., 300 grams versus 3,000 grams), the set appropriate for the particular balance being selected in the factory. 
     In yet another aspect, the present invention is an electronic balance operable in a parts counter mode, in which the balance is tared while a container that is to be used to contain the sample is on the balance pan, an initial sample consisting of a specified number of uniform pieces is weighed in the container to determine unit weight, and a sample consisting of an unknown number of such pieces is weighed in the container, the balance then displaying the number of pieces in the sample. According to this aspect of the invention, the balance is disabled from making any measurements while in the parts counter mode until after taring to compensate for the container weight. If the balance is then recalibrated with another sample consisting of a different specified number of pieces from the sample previously used, the balance must again be tared to compensate for the weight of the container before any additional measurements can be made to prevent zero-drift errors. 
     Many other objects and features of the present invention will become clear upon consideration of the following description of one preferred embodiment, taken in conjunction with the accompanying figures, in which like reference characters refer to like elements throughout. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     FIG. 1 is a schematic block diagram of the balance of the invention. 
     FIG. 2 is a schematic diagram of the analog-to-digital conversion circuitry indicated in FIG. 1. 
     FIG. 3 is a schematic diagram of the processing and display circuitry indicated in FIG. 1. 
     FIG. 4 is a schematic diagram of the power supply circuitry indicated in FIG. 1. 
     FIGS. 5-17 are flow charts illustrating the software used in conjunction with the circuitry of FIGS. 1-4. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The general arrangement of the balance of the invention is indicated schematically in FIG. 1. The balance includes a strain gauge 10 of a known type, which produces an electrical signal representative of the stress on the strain gauge, which in turn is representative of the weight load on the strain gauge. The strain gauge output signal varies approximately linearly with the weight load on the strain gauge, which is the sum of the weight of the balance pan (not shown), the weight of the sample on the pan and the weight of the container, if any, holding the sample. The strain gauge output signal is herein assumed to vary exactly linearly with the weight, although some means for compensating for the actual slight non-linearity of this relation could be used, if desired, to improve the precision of the balance still further. 
     The signal output by the strain gauge is converted to a digital signal by means of analog-to-digital conversion (hereinafter &#34;ADC&#34;) circuitry 12. The resulting digital signal is processed by processing circuitry 14 to produce electrical signals (indicated collectively by arrow 16) that drive a display unit 18 to display the weight of an object on the balance pan. The processing circuitry 14 includes a microprocessor, although it is to be understood that the invention could be practiced using hardware instead of the software disclosed herein. The balance also includes power supply circuitry 20 to provide the DC voltages required by circuits 12, 14 and 18. 
     The strain gauge 10 is a conventional device comprising a four-arm resistive bridge 22 (see FIG. 2) mounted on a frame that has the form of a parallelogram disposed in a vertical plane and including upper and lower parallel beams that are horizontal when the balance is in its equilibrium position. Two of the four resistors of the bridge 22 are mounted on each of the beams in such a manner that the four resistors 24, 26, 28, 30 define a rectangle when the strain gauge is unstressed. One end of the strain gauge is mounted securely to the frame of the balance. The pan of the scale is arranged so that the weight of the sample tends to shear the strain gauge downward about the connection of the strain gauge to the balance frame. This deflection creates strains in the four resistors 24, 26, 28, 30, but the resistors, because of their different locations, are not equally stressed. The changes in the resistance of the resistors 24, 26, 28, 30 resulting from the stress are therefore unequal. If the bridge 22 is so balanced electrically as to produce an output signal nearly equal to zero (i.e., no substantial difference in voltage between junctions 36 and 38) when the pan is empty, placement of a weight on the pan will cause the bridge 22 to generate a detectable output signal. The use of a strain gauge frame having the shape of a parallelogram tends to make the exact placement of a weight on the pan less important to the accuracy of the weight measurement, as is well known. 
     The four resistors 24, 26, 28, 30 are connected in the form of a parallelogram, with a constant 5-volt potential applied across two opposite vertices 32, 34 of the square. In the unloaded condition, the voltage at the third vertex 36 is adjusted to a voltage of value V1 by means of a resistive voltage divider comprising potentiometer R1 and fixed resistors R2, R6 and R7, and connected between the 5-volt analog source and analog ground. The voltage at the connection between resistors R6 and R7 is applied to the non-inverting input of an operational amplifier &#34;OP AMP&#34; hereinafter) U1. The voltage V2 at the fourth vertex 38 of the bridge 22 is applied via resistor R3 to the inverting input of OP AMP U1. The OP AMP U1 has a feedback network consisting of capacitor C1 and a resistor R4 connected in parallel with each other. The feedback network is connected between the inverting input and the output terminal 40 of OP AMP U1. The leads to both inputs of the OP AMP U1, the wire 42 connecting the non-inverting input lead and R7, and the conductors 44-48 connecting the inverting input to capacitor C1 and resistor R4 are guarded against leakage by being enclosed in respective conductive tracks 50, 52 on the printed circuit board bearing these leaks. The traces 50, 52, are connected to be at the voltage V2 of junction 38. 
     It will be clear to those skilled in the art that when a weight is placed on the pan, the deflection of the strain gauge causes V1 and V2 to shift in opposite directions from their equilibrium value, causing OP AMP U1 to output a signal proportional to the weight on the pan. The OP AMP U1, together with its feedback network and input resistors R3, R6 and R7, acts as a differential amplifier with negative gain, and acts also as an active low-pass filter (due to the presence of capacitor C1). The potentiometer R1 is permanently adjusted in the factory so that when no weight is on the pan, the output voltage of OP AMP U1 is near but not equal to zero. 
     The output terminal 40 of OP AMP U1 is connected across a resistor R5 to the inverting input of a second OP AMP U2. The inverting input of OP AMP U2 is also connected to analog ground across a capacitor C14. The non-inverting input of OP AMP U2 is grounded. OP AMP U2 has a feedback network consisting of capacitor C3, connected between the output terminal 54 and the inverting input of the OP AMP U2. The negative power supply terminal 56 of OP AMP U2, in addition to being connected to the negative voltage supply line, is also connected across capacitor C4 to analog ground. This circuit acts as an integrator, as described below. 
     A field effect transistor (&#34;FET&#34;) Q2 is provided, having its source connected to the inverting input of OP AMP U2, its gate connected to three data bus terminals DB2-4 of the microprocessor U4 (see FIG. 3), and its drain connected across resistors R11 and R10 to the 5-volt analog supply. Transistor Q2 acts as a feedback switch for the integrator, as described below. A thermistor RT1 is connected in parallel with resistor R10 to provide temperature compensation. 
     The output of OP AMP U2 is applied across resistor R8 to the base of a bipolar junction transitor Q1, whose emitter is grounded and whose collector is connected via resistor R9 to the 5-volt DC source. The collector of transistor Q1 is also connected to the interrupt terminal INT of the microprocessor U4. Transistor Q1 serves as a comparator, outputting a signal only when the voltage at its base falls below a certain value. 
     The lead 57 connecting resistor R5 to the inverting input of OP AMP U2 is guarded against leakage as is the wire 58 connecting lead 57 and capacitor C3. A short length of the wire 62, which connects lead 57 to the source of transistor Q2, is also guarded. The guards comprise conductive traces on the printed circuit board carrying the ADC circuitry. 
     When the output of OP AMP U1 departs substantially from zero responsive to a weight on the pan, the output voltage of OP AMP U2 ramps up at a constant rate as charge is drawn from capacitor C3, producing a triangular wave as output. When the output voltage of OP AMP U2 rises above a certain value, transistor Q1 is turned on, lowering the voltage of the INT terminal of the microprocessor U4 from the high to the low state. At regular intervals (in the illustrated embodiment, approximately one millisecond), a timer, which in the embodiment shown is part of the microprocessor U4, turns FET Q2 on. This causes the 5-volt supply to recharge the integrator capacitor C3, in the process causing the integrator output voltage to ramp back down. When the output voltage of OP AMP U2 has ramped back down to a certain level, transistor Q1 turns off again, returning the signal of the INT terminal to the high state. The microprocessor then turns FET Q2 off. The length of time FET Q2 is on is directly proportional to the magnitude of the output signal of OP AMP U1, and therefore to the weight of the pan. A pulse-length counter in the microprocessor U4 measures the length of time FET Q2 is on. This information is used by the microprocessor U4 in a manner described below to determine the weight. 
     A small error is introduced, because the timer is operated by a clock and is therefore able to examine the signal being received from transistor Q1 only at discrete intervals. It will be apparent, however, that if one pulse ramps down too far (i.e., below the prescribed level), the ramp-up portion of the following pulse will not reach as high a level as would otherwise be the case, and the next pulse, to recharge the integrator to the prescribed level, will therefore be shorter. Errors of this kind are therefore non-cumulative, and by adding a large number of pulses together the total accuracy is actually improved. 
     FIG. 3 shows the arrangement of the logic and display circuits 14, 18 of the balance of the invention. This circuitry includes the microprocessor U4, which is preferably available from National Semiconductor 8049 LN-11 chip. A non-volatile memory, preferably an electrically alterable read only memory (&#34;EAROM&#34;) U3, is also provided to store certain information while the balance is turned off. The EAROM U3 is preferably a XD 2210 chip, available from Xicor, and has four input-output data lines I/O1-4 connected to four respective port terminals P20-23 of the microprocessor U4. Port terminals P16 and P17 of the microprocessor U4 are connected, respectively, to an ARRAY RECALL input and a STORE input of the EAROM U3. P17 is also connected via capacitor C6 to the 5-volt DC supply. Two data bus terminals DB5 and DB7 of the microprocessor U4 are connected respectively to terminals WE and CS of the EAROM U3. Additional port terminals P10-P14 of the microprocessor U4 are connected to address inputs A0-A4, respectively, of EAROM U3. Data bus DB6 is connected via resistor R12 to the base of a transistor Q3, whose collector is connected to terminal 8 of EAROM U3 and whose emitter is grounded. Port terminal P15 of microprocessor U4 is unconnected. The 5-volt supply is connected to address terminal A5 and terminals 5, 26 and 40 of EAROM U3; terminals 5, 26 and 40 are also connected to ground across capacitor C5. 
     The clock for the microprocessor U4 is provided by an oscillator circuit comprising a crystal Y1 of frequency 6 mHz and capacitor C7 and C8 which are connected between ground and the respective two sides of the crystal Y1. The crystal terminals are also connected respectively to terminals 2 and 3 of microprocessor U4. 
     Port terminal P25 of microprocessor U4 is connected to one side of a momentary switch S1 whose other side is grounded. S1 serves as an OFF switch for the balance and is used with the ON/TARE switch S2 (see FIG. 4) in a manner described below to select the units in which a measured weight is to be displayed by the balance. In addition, terminals 7 and 20 are grounded and terminal 4 is connected to ground via capacitor C9. 
     A two-pole switch S3, one side of which is grounded and the other side of which is connected to port terminals P27 and P24 (one switch pole being connected to each terminal), serves to disable the automatic shut-off feature of the balance. According to this feature, the miroprocessor U4 turns the balance off automatically if the ON/TARE switch S2, after being depressed, is not depressed again within a set time (e.g., 30 seconds), or if switch S2 is not depressed within a set time (e.g., 45 seconds) after the balance is turned on. By actuating switch S3, however, the user disables the automatic shut-off. S3 also enables/disables the calibration routine to prevent tampering. 
     Terminal T1 of the microprocessor U4 is connected to the ON/TARE switch S2 (shown in FIG. 4) through diode D2 (connection (a)). In addition, terminal T0 is connected to a circuit (shown in FIG. 4) that serves to indicate when the battery is low. 
     Data bus terminals DB0, DB1 of the microprocessor U4 are respectively connected to the DATA IN  and CLOCK IN  terminals of the LCD driver circuit U5, which is a conventional circuit MM5453, available from National Semiconductor Company, used to control the liquid crystal display (&#34;LCD&#34;) U6 of the balance. The wire 64 connecting DB1 to the CLOCK IN  terminal is also connected to ground via a capacitor C11. 
     The 5-volt DC supply is also connected directly to terminal V DD , via resistor R13 to terminal OSC IN  and via grounded capacitor C10 to terminal GND (the ground terminal) of driver circuit U5. 
     The LCD U6 is designed to provide a display of the weight measured by the scale, in seven-segment digits, and to show the unit of measurment. In addition, as explained below, the microprocessor disables the display of the unit symbol until the weight measurement becomes stable enough to be considered reliable. Also, the LCD displays all segments when the balance is first turned on, and displays various prompting characters during the calibration procedure and during operation in the parts counter mode, as described below. These displays are controlled entirely by the microprocessor U4, the LCD U6 including only the liquid crystal array itself. The design of the LCD U6 is accordingly believed to be well within the skill of one of ordinary skill in the art, and therefore will not be further described herein. 
     FIG. 4 shows the power supply and associated circuitry. Power is derived from a battery B1, which is preferably either an 8.4-volt nickel-cadmium battery or a 12-volt alkaline battery. The battery terminals are connected as indicated in FIG. 4 to a jack (&#34;AISI&#34;), which is used to plug in an external power supply to recharge the battery, if a nickel-cadmium batter is used. The jack is connected to the remainder of the power supply circuitry via terminals E1, E2 and E3. A line 66 connected to terminal E3 is also connected to the COM terminal of a voltage regulator VR1 and serves as the 5-volt supply line. VR1 is preferably a standard LM320LZ -5.0 volt voltage regulator. The OUT terminal of VR1 serves as the ground for the balance circuitry, and is connected across capacitor C2 to line 66. The IN terminal of VR1 is connected to line 68, which serves as the negative voltage supply line. In the preferred embodiment, using an alkaline battery, line 68 supplies a voltage of -7 volts DC. Lines 66 and 68 are connected via capacitor C12. 
     Line 68 is connected to the collector of a transistor Q6, whose emitter is connected across a diode D4 to terminal E1. The ON/TARE switch S2 is connected between line 66 and diode D3, which is connected across resistor R21 to the base of transistor Q6 and is oriented to allow current to flow into the base of Q6. A resistor R20 and a diode D1 are used as a charging circuit for a nickel-cadmium battery, and are connected to a jumper terminal J2-2. A second jumper terminal J2-1 is connected to terminal E2, and, when a nickel-cadmium battery is used, is connected by a jumper indicated in phantom at 70 to jumper terminal J2-2 to permit battery recharging. In addition, line 66 is connected to the emitter of a PNP transistor Q7, whose collector is connected to the junction between diode D3 and resistor R21. Line 66 is connected to the base of transistor Q7 via resistor R22 and capacitor C13, connected in parallel. The base of Q7 is also connected by a resistor R23 to port terminal P26 of the microprocessor U4. The junction between diode D3 and switch S2 is connected across diode D2 to terminal T1, which is also connected to ground across resistor R19. When switch S2 is depressed to turn the balance on, Q6 is turned on. The microprocessor U4 latches on transistor Q7, which serves as a latch to hold Q6 on after S2 is released. 
     To indicate when the battery is low, transistors Q4 and Q5 are provided. The collector of Q4 is connected to terminal To of the microprocessor U4 and, across resistor R14, to the 5-volt DC supply. The base of Q4 is connected to the collector of Q5 and, across a resistor R15, to the 5-volt supply. The base of Q5 is connected to the positive and negative voltage supply lines across resistors R16 and R18, respectively, and across resistor R17 to the collector of Q4. The emitters of both Q4 and Q5 are grounded. 
     As the battery B1 weakens, the voltage on the negative supply line gradually rises, raising the base voltage of Q5 and eventually turning Q5 on. This essentially grounds the base of Q4, turning Q4 off and raising the voltage of terminal To from its normal low state to the high state. When this occurs, the microprocessor U4 causes the LCD U5 to display a &#34;battery low&#34; symbol. 
     MODE OF OPERATION OF THE BALANCE 
     When the power is turned on by means of the ON/TARE switch S2, the LCD U5 initially verifies that all liquid crystal segments of the LCD are operating correctly by displaying all segments briefly. 
     The balance is capable of displaying weights in several units. Typically, the user will have a choice of grams, ounces and penny weights (or some other custom unit ordered by the customer in place of penny weights, e.g., carats, taels, etc.). In addition, the user can choose to operate the scale in a parts counter mode, described below. (It is particularly contemplated that a given balance will offer the user either a choice among several units, or a choice between weight measurement with the result expressed in, e.g., grams and operation in the parts counter mode, but not both; however, it is believed that from the present disclosure, one of ordinary skill in the art could design and produce a balance having both arrangements, and such a balance is considered to be within the scope of the invention.) After the segment verification display disappears, a symbol for one of the possible units will appear (e.g., &#34;g&#34; for grams). If the user wants a different unit, he simultaneously depresses switches S1 and S2 and then releases them. This causes the balance to display another of the units with which it has been provided. This procedure is repeated until the symbol of the unit the user desires is displayed. When the balance is then used for weighing, the result will be expressed in whatever unit is displayed as a result of the unit-shifting procedure just described. 
     In a balance having the parts counter mode, simultaneous actuation of both switches S1 and S2 activates the parts counter mode. In the illustrated embodiment, once this mode has been selected, it is impossible to return to the ordinary weighing mode except by turning the balance off and then on again. 
     For weighing, when the units have been selected, an empty container is placed on the pan, and the ON/TARE switch S2 is depressed to tare the balance. The sample is then placed in the container and the weight of the sample is displayed by the LCD. 
     To enter the parts counter mode, the user depresses the switches S1 and S2 together and releases them, and the balance displays the prompting characters &#34;CON&#34;. The empty container is then placed on the pan, and the balance is tared. The balance then displays &#34;5&#34;. By pressing S1 and S2 simultaneously, the user causes the balance to display &#34;10&#34;. This can be repeated to shift to &#34;20&#34;. (If the process is again repeated, the tare prompt characters &#34;CON&#34; will again be displayed, and the balance must be tared again before anything further can be done, except by turning off and reactivating the balance.) A number of pieces equal to the display number is placed in the container and the ON/TARE switch S2 is depressed again. This enables the balance to determine the unit weight of the parts. The user then places the sample to be counted in the container and again depresses the ON/TARE switch S2, and the number of parts in the sample is displayed on the LCD. 
     In the weighing mode, to indicate when a reliable reading has been obtained, the balance does not display a unit symbol at the end of the read-out until flutter of the weight measurement falls below a predetermined level, indicating that stability has been achieved. In the weighing mode, the unit symbol then appears in order to indicate stability. 
     In the parts counting mode, the user is required to retare the balance with the empty container each time a new initial sample (i.e., the parts counter calibration sample of 5, 10 or 20 pieces) is used, to protect against drift. To ensure that the user does not omit this step, each time the initial sample is changed, the balance displays a tare prompt display on the LCD and will not make a measurement until the ON/TARE switch S2 has been depressed again to retare the balance. 
     Calibration of the balance is begun in the factory by adjustment of potentiometer R1, to balance the bridge 22 as indicated above. R1 is then sealed to prevent readjustment of it. Final calibration can be done at the factory or by the user. To calibrate the balance, the ON/TARE switch S2 is depressed and held down for a minimum predetermined period of time, preferably five seconds. When the five second period is up, the LCD displays &#34;-C-&#34; for a short time, and then, after the switch S2 is released, &#34;CAL&#34;. Switch S2 is then depressed to tare the balance. When this has been done, a standard weight equal to the full scale capacity of the balance (in the preferred embodiment, either 300 grams or 3000 grams) is put on the pan, and switch S2 is again depressed. This completes calibration. The calibration routine can be disabled by a switch (S3) provided for that purpose, to prevent tampering. When the balance is turned off, whether manually or by the automatic shut-off feature described above, the non-volatile memory U3 automatically stores a record of the units selected by the user. When the balance is reactivated, this unit is the first one offered to the user, so that the user need not cycle through all the possible units again. 
     The Software 
     In the preferred embodiment, the balance is controlled by the microprocessor U4, using software described herein. The best mode now contemplated by practicing the invention is to use the program identified as Appendix I to this specification, which Appendix is a part of this disclosure. Details beyond those given below are to be found in Appendix I. The source listing reproduced in Appendix I is in assembler&#39;s language for an 8049 microprocessor. In FIGS. 5-17, the hexadecimal numbers beside some boxes of the flow charts indicate program step locations in the program memory. The appended program listing is to be taken as controlling and as the authoritative, enabling disclosure of the software of the invention, in preference to the following description and flowcharts. 
     The microprocessor U4 runs in a closed loop, which is interrupted once every 1 ms. by a timer, when the microprocessor U4 generates a feedback pulse as described above. After the generation of each feedback pulse, the microprocessor resumes executing the main loop. A digital filter algorithm in the timer interrupt routine processes the data pulses in batches, and the results of this processing are accumulated until a certain number of pulses have been processed. The accumulated processed data batch is then averaged by the main program loop with earlier data, until the weighing of the sample has been completed. 
     When the scale is turned on, the data memory (a portion of the RAM of microprocessor U4) is cleared, and all program flags are given their proper initial values. The timer to control automatic balance shut-off is also activated, and the timer interrupt is enabled. 
     The microprocessor then reads the EAROM U3, using a routine described below in connection with FIGS. 14a and 14b, to retrieve the calibration constants, the ADC data indicating zero tare, the average constant (i.e., the number of readings to be averaged before displaying a result), and the conversion constants needed to translate the ADC data into the various possible units. The liquid crystal segments are then displayed on the LCD for the verification test. The routine passes until this test is complete. 
     The routine then continues from point &#34;A&#34; in FIG. 7, first determining whether the ON/TARE switch S2 is depressed. If not, the routine proceeds to point &#34;B&#34; in FIG. 7, and determines whether the &#34;OFF&#34; switch S1 is depressed. If so, the routine proceeds to point &#34;E&#34; in FIG. 8, loads into the EAROM U3 data indicating the balance status (i.e., the units last selected by the user) and turns off the balance. 
     If the OFF switch S1 is not asserted when checked after point &#34;B&#34;, the routine checks to see whether a new datum flag is asserted (i.e., whether a new data pulse is ready for averaging); if not, the routine returns to point &#34;A&#34;, while if a new pulse is ready, the routine proceeds to point &#34;F&#34; and proceeds as described below. 
     If after point &#34;A&#34;, the ON/TARE switch S2 is asserted when checked, the routine sets a tare flag which indicates this fact, and resets the automatic shut-off timer. If the calibration routine has not been disabled, the routine proceeds to point &#34;Y&#34;; otherwise, switch S2 is again checked. If switch S2 is not being asserted, the routine again proceeds to point &#34;B&#34;. If switch S2 is depressed, however, the routine checks whether S1 is also depressed. If both are being asserted simultaneously, the routine proceeds to point &#34;X&#34; to perform unit selection (referred to in the Figures as &#34;range&#34; selection). If switch S1 is not asserted, however, the routine determines whether the ON/TARE switch S2 has been depressed for the full five seconds needed to access the calibration process; if not, it returns to point &#34;K&#34; of the routine, while otherwise, the tare flag is cleared, the span calibration flag is set and the calibration prompt &#34;-C-&#34; is displayed on the LCD. The routine then proceeds to point &#34;Y&#34;. (This is the beginning of calibration, but the actual calibration process is performed subsequently to point &#34;F&#34;, as described below.) 
     At point &#34;Y&#34;, switches S1 and S2 are checked to determine whether both are asserted simultaneously to select the display units or, if the balance has the parts counter mode, to chose between the parts counter mode and the weighing mode. (Balances of both types have identically programmed microprocessors, the balance type being determined by information stored in the EAROM U3 and retrieved from there by the microprocessor U4 when the balance is turned on. In this manner, all balances according to the invention can be manufactured the same way, differing only in that different EAROM&#39;s are included.) If not, it is determined whether switch S2 has been released; if switch S2 has not been released, the routine returns to point &#34;Y&#34;. If S2 has been released and the parts counter mode has not been selected, the routine proceeds to point &#34;B&#34;. If switch S2 has been released, and if the parts counter mode has been selected by the user, the routine sets up the average counters and the average sum register to operate in this mode. The routine then proceeds to point &#34;B&#34;. 
     For unit or mode selection, the routine proceeds from point &#34;X&#34; to clear the tare and span calibration flags. In the parts counter mode, the appropriate flags are set, and the LCD initially displays &#34;CON&#34;. On subsequent passes through the routine from point &#34;X&#34;, if the container has been tared, the switches S1 and S2 are depressed and released one or more times (once per pass) to enter the number of pieces to be included in the initial sample. The display driver U5 is then cleared, and the decimal point and unit symbol are displayed. The routine then waits for release of switches S1 and S2, and looks for a new data flag. If the flag is asserted, the routine continues from point &#34;F&#34;, and otherwise, the routine returns to point &#34;A&#34;. 
     If the parts counter mode is not available in the balance in question, then from point &#34;X&#34; the routine displays the possible units in sequence, changing to the next unit each time switches S1 and S2 are simultaneously depressed and then released (one unit change per pass). After clearing the driver U5 and displaying the decimal point and unit, the program then waits for switch release, looks for a new data flag, and proceeds to point &#34;F&#34; or point &#34;A&#34; as described in the preceding paragraph. 
     As stated above, the processing of data by the main program loop begins at point &#34;F&#34;. From point &#34;F&#34;, the microprocessor U4 de-asserts the new-data flag that sent the routine to Point &#34;F&#34; (This is necessary to retian the full desired number of significant digits.) It is then determined whether the shifted data falls within the range of the balance. If not, an overrange-error or underrange-error signal (&#34;EEE&#34; and &#34; - - - &#34;, respectively) is displayed, and the routine returns to point &#34;A&#34;. If no such error is present, the new data is averaged with previously received and processed data. If the calibration routine has ben accessed by the user, calibration is now effected by means of the calibration routine (described below), after which the main routine returns to point &#34;A&#34;. If no calibration flag is asserted, another check is made for overrange error after determining the error limits proper to the selected mode (weighing or parts counter), a suitable error message is displayed if necessary, and the routine returns to point &#34;A&#34;. If no error is present, the routine proceeds to point &#34;C&#34;. 
     As shown in FIG. 9, proceeding from point &#34;C&#34;, the routine determines whether a sample is already set (This is done whether the balance is in, or has, the parts-counting mode, because the following steps are performed in any event.) If so, it then checks whether the balance has been tared, and checks that the measurement is sufficiently stable to be reliable (the stability-determination routine is described below). If both of these conditions are satisfied, the tare flag is cleared, and the contents of the tare register are subtracted from the new data. If either of these two conditions is not satisfied, or if the parts counter flag has been asserted, then the tare flag is left as is, and the minus sign in the average register is cleared. The contents of average register are then added to the tare register. If the result of this operation is negative, the minus sign is set again, and the 2&#39;s complement of the weight-after-tare (&#34;W.A.T.&#34;) register is taken to obtain a positive value. After this, or if no negative result is obtained, the routine proceeds to point &#34;P&#34; of the program. 
     As shown in FIG. 10, from point &#34;P&#34;, the routine first checks to determine whether the parts counter flag is asserted. If the parts counter mode has not been selected, then the averaged data in the average counter is divided by the total range of the balance and the result is converted to an indication of the weight of the sample expressed the units chosen by the user. If the data is sufficiently stable to be reliable, the appropriate flags are asserted, and if the data is non-zero, the routine proceeds to point &#34;D&#34; to display the data. If the data is equal to zero, the minus sign is cleared before proceeding to point &#34;D&#34;. 
     From point &#34;P&#34;, if the parts counter mode has been asserted, the microprocessor determines the stability of the data according to a different standard, which detects fluctuations of approximately 20 milligrams (compared to approximately 100 milligrams for the normal mode of operation). If the parts constant has not already been set, then the program proceeds to point &#34;L&#34;. If the parts constant (i.e., the number of units in the initial sample used to determine unit weight) has already been selected by the user, the routine multiplies the data by 10 and then divides by the parts constant. The resulting data is then processed as in the normal mode. 
     As indicated in FIG. 11, from point &#34;L&#34;, the routine first determines whether the container has been tared. If not, it checks to see whether a container tare has been requested, and if so, the stability of the measurement is checked. If the stability is insufficient, the routine returns to point &#34;B&#34;; otherwise, the tare flag is cleared, and the 2&#39;s complement of the tare register contents is taken. The routine then proceeds to point &#34;M&#34;. 
     If the container has not been tared and a tare has not now been requested by the user, then the tare container prompt &#34;CON&#34; is displayed on the LCD U6, after which the routine turns to point &#34;A&#34;. 
     Proceeding from point &#34;M&#34;, if the user has not already set the initial sample size, the LCD unit U6 displays a prompt to load the sample, after which the routine returns to point &#34;A&#34;. If the number of units in the initial sample has been entered, the routine proceeds to point &#34;H&#34; to clear the display if the measurement is insufficiently stable, but otherwise subtracts the tare value from the average value obtained from the measurement. If this operation produces a zero or negative weight, the signal for underrange error is displayed and the routine returns to point &#34;A&#34;; otherwise, the weight of the initial sample is divided by the number of units therein to obtain the unit weight. The routine then returns to point &#34;G&#34;. 
     In any mode, once the final measurement has been made and determined to be sufficiently stable, the routine proceeds from point &#34;D&#34; as shown in FIG. 8, converting the binary data to binary coded digital (&#34;BCD&#34;) data, which is saved in BCD registers in the microprocessor U4. Unless the automatic shut-off timer has timed out, the data in the BCD registers is displayed on the LCD U5, and the routine returns to point &#34;A&#34;. If the timer has timed out, switch S3-1 (the automatic shut-off override switch) is checked; if it is on, the routine proceeds to point &#34;E&#34; and turns off the balance as described above, while otherwise the data in the BCD registers is displayed and the routine returns to point &#34;A&#34;. 
     FIG. 12 illustrates the timer interrupt routine which is initiated by the timer approximately ever millisecond, when the timer generates a feedbac pulse and measures how long the feedback pulse must be to return the integration to the desired level. When this occurs, the main routine, described above in connection with FIGS. 5-11, is halted wherever it is, the necessary information in the registers, accumulator and time counter being preserved while the timer interrupt routine is run. The timer interrupt counter is then reset, and a pulse-length counter counts up a number of counts proportional to the length of the pulse output to the gate of transistor Q2. When the ADC output pulse has terminated and FET Q2 has been turned off, the count in the pulse-length counter is summed up in a register as a new input X(I), and the pulse length counter is cleared. The old accumulator and register values are restored to resume running the main routine. If a multiple of twenty-five such input sums have been received, the sums are filtered by means of a digital filtering subroutine described below, after which the old accumulator and register values are restored. After each sixteen sets of twenty-five sums, the new-data flag is asserted, and, after the filtering, the summed ADC output (i.e., the four hundred input sums) is stored in the process registers, after which the sum register is cleared. After filtering and restoration of the pre-interrupt register values, the microprocessor U4 returns to the main routine. 
     FIG. 13 shows the filter subroutine. As can be seen, the sum R(I-1) of all previously filtered inputs is first added to the sum register. (This sum register is cleared after each sixteen sums.) If this results in an overflow of the sum register, the register is set to the maximum permissible value. Thereafter, or if there is no overflow, R(I-1) (stored in a separate sum register) is divided by means of being rotated one bit to the right three times in succession. The result is then subtracted from the preceding value R(I-1) to produce the value S(I). A new value R(I) is calculated according to the equation R(I)=X(I)+S(I)=X(I)+7R(I-1)/8, where X(I) is the most recently added sum from the pulse-length counter. The X(I) input holding register is then cleared, and the filtering subroutine is complete. This subroutine ensures that minor flutters in the signal received from the strain gauge do not produce a corresponding flutter in the weight displayed by the balance. This feature permits the balance to be used for such purposes as weighing animals. 
     FIGS. 14a and 14b show the procedure for reading data from the EAROM. To begin with, the EAROM is powered up by the microprocessor U4 by means of the transistor Q3. After a pause for settling time, the array recall line is toggled low. The subroutine ROMRD (described below) is then called and used to retrieve the bytes containing status information and then is used again to retrieve the X data byte, various conversion factors (which are sequentially looked up from tables in the EAROM U3), the values of the various flags, the averaging constant and the custom multiplier (i.e., the multiplier used to convert data to any custom units the user may have ordered). These data, as they are extracted from the EAROM, are stored in suitable registers in the microprocessor U4. After this has been done, the power to the EAROM U3 is turned off by means of transistor Q3, ending the routine. 
     The subroutine ROMRD begins by settling the address of the data location to be read from the EAROM, and four bits of data are input to the accumulator of microprocessor U4. The lower four bits in the accumulator are stored elsewhere for later use. The EAROM address is then incremented, and an additional four bits are transferred to the accumulator. The lower four bits of the new datum are again separated and are transferred to the four high bits of the accumulator. The previously obtained low four bits recovered from the EAROM are then returned to the low four bits of the accumulator. The resulting eight bit byte is stored in the appropriate register in the microprocessor U4. The EAROM address on the microprocessor terminals P10 through P14 is then incremented, and the process is repeated for each additional eight-bit byte to be read from the EAROM. The microprocessor then returns to the &#34;READ EAROM&#34; routine. 
     FIGS. 15a and 15b show the routine for writing information into the EAROM, which is done preparatory to the balance being turned off to save the balance status, and which is also done to store calibration data. The EAROM is powered up by the microprocessor U4 by means of the transistor Q3. The subroutine ROMRD is used to read in a byte from the EAROM. If the write enable flag is set, the data byte to be written into the EAROM is summoned from the register where it is stored in the microprocessor. The subroutine ROMWRT (described below) is then called and used to write the byte into the EAROM. The STORE line of the EAROM is then toggled low, and the EAROM is turned off. Power to the EAROM is then turned off by transistor Q3, ending the routine. If the balance status is the same as when the balance was turned on, or if the balance is in the parts counter mode, no attempt is made to store information in the EAROM when the balance is being turned off. The write routine is terminated immediately after turning off power to the EAROM. 
     The subroutine ROMWRT begins with the microprocessor setting the address of the data location to which data is to be written. The lower four bits of the data are called from the microprocessor register where they are stored and are placed on the four input/output lines of the EAROM (I/O1-4). A low input is then applied to the WE terminal of the EAROM, and the input to the CS line is toggled, entering the four bits in the EAROM. The input to the WE line is then toggled high, and after the EAROM address is incremented, the upper four bits of the byte to be stored are entered in the same manner. When this has been done, the subroutine is repeated for each eight-bit byte that is to be stored. When all such bytes have been sotred, the microprocessor returns to the WRITE EAROM routine. 
     FIG. 16 shows the calibration routine. This routine is begun by transferring the ADC output data to the weight-after-tare register (because the stability routine operates on the contents of this register, as described below. The stability of the data is then determined. If the X data has not yet been loaded, then the calibration prompt &#34;CAL&#34; is displayed. If the switch S2 is off or if the stability is found to be insufficient, the program returns to point &#34;A&#34; of the main routine. Otherwise, it proceeds to clear the parts sample flag (because calibration in the parts counter mode would invalidate subsequent parts counter mode results) and the tare flag, and sets the X data loaded flag. The X data is then loaded into the X data register from the average register. A calibration weight prompt is then displayed, with the grams symbol &#34;g&#34;. If the resulting measurement is sufficiently stable and if the tare switch S2 is depressed, the routine proceeds to clear the span calibration, tare and X data loaded flags; otherwise, the routine returns to point &#34;A&#34; of the main program. After clearance of the flags, data is loaded from the average register to the Y data register, and the contents of the X data register are subtracted from the Y data register. The result is multiplied by 10,000  (to retain the desired number of significant digits in the ensuing division) and is then divided by the full range of the balance (300 or 3000 grams). The result is saved and is thereafter used as the full range calibration datum &#34;KSPAN&#34;. The EAROM U3 is then powered up, and after a pause for settling time, the KSPAN data is stored in the EAROM using the ROMWRT sub-routine. The routine then returns to point &#34;A&#34;. 
     FIG. 17 shows the routine for determining stability. This routine first subtracts the current data whose stability is in question from the stability holding register. If the absolute value of the difference exceeds a certain value, the routine goes to point &#34;K&#34;, clears the flags indicating an acceptable or nearly acceptable degree of stability, transfers the WAT register data to the stability holding register, and returns to the main routine. Otherwise, the routine sets a counter to 2 (16 for the calibration routine, because stability is checked or uncalibrated data during that routine, and 3 in the parts counter mode). The stability register contents are repeatedly decremented along with the counter until one or the other is zero. If the counter reaches zero first the routine goes to point &#34;K&#34;; otherwise the near-stable flag is set, or if that flag was already set, the stable flag is set, indicating acceptable stability. The WAT register data is moved to the stability holding register, and the routine returns. In effect, if two consecutive pairs of data differ by sufficiently small amounts, stability is considered to have been attained. 
     Although it is preferred to use software to practice the invention, hardware implementations are also within the scope of the invention. Also, the disclosed ADC circuitry could be replaced by other circuitry that would generate width-modulated pulses to represent weight, and the digital filter disclosed could be replaced with another digital filter algorithm (or, if desired for any reason, with an analog filter located between the difference amplifier and the integrator circuit), without departing from the scope of the invention. 
     Although the present invention has been described with particular reference to one preferred embodiment thereof by way of illustration only, many modifications and variations thereof will now be apparent to those skilled in the art. Accordingly, the scope of the present invention is to be limited not by the illustrative details described herein, but only by the terms of the appended claims. ##SPC1## ##SPC2## ##SPC3## ##SPC4##