Abstract:
A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Technical Field 
         [0002]    The present invention relates to a semiconductor device comprising a symmetric capacitor structure. 
         [0003]    2. Related Art 
         [0004]    A device within an electrical structure typically does not comprise terminals extending from the device that comprise equivalent electrical properties. Terminals that do not comprise equivalent electrical properties may cause other devices within the electrical structure to operate inefficiently. Thus, there is a need for a structure and associated method for forming an electrical structure with terminals comprising equivalent electrical properties. 
       SUMMARY OF THE INVENTION 
       [0005]    The present invention provides a structure, comprising: 
         [0006]    a first doped region formed within a substrate, wherein said first doped region comprises a first dopant having a first polarity; 
         [0007]    a second doped region formed within said substrate and over said first doped region, wherein said second doped region forms a first electrode of a symmetric capacitor; 
         [0008]    a third doped region formed within said substrate and over first doped region, wherein said third doped region forms a second electrode of said symmetric capacitor, wherein each of said second doped region and said third doped region comprises a same second dopant having a second polarity, wherein each of said second doped region and said third doped region is formed simultaneously, and wherein said first doped region, said second doped region, and said third doped region in combination form a PN junction; and 
         [0009]    a first shallow trench isolation structure formed between said second doped region and said third doped region, wherein said first shallow trench isolation structure electrically isolates said second doped region from said third doped region, wherein said symmetric capacitor comprises a main capacitance, wherein said structure comprises a first parasitic capacitance and a second parasitic capacitance, wherein said main capacitance comprises a capacitance between said second doped region and said third doped region, wherein said first parasitic capacitance represents a parasitic connection between said second doped region and said first doped region, wherein said second parasitic capacitance represents a parasitic connection between said third doped region and said first doped region, wherein a first distance between said second doped region and said first doped region is about equal to a second distance between said third doped region and said first doped region, and wherein said first parasitic capacitance is about equal to said second parasitic capacitance. 
         [0010]    The present invention provides a method for forming a structure, comprising: 
         [0011]    providing, a substrate; 
         [0012]    forming, a first doped region within said silicon substrate, wherein said first doped region comprises a first dopant having a first polarity; 
         [0013]    forming, a second doped region within said substrate and over first doped region, wherein said second doped region forms a first electrode of a capacitor; 
         [0014]    forming, a third doped region within said substrate and over first doped region, wherein said third doped region forms a second electrode of said capacitor, wherein each of said second doped region and said third doped region comprises a same second dopant having a second polarity, wherein said forming said second doped region and said forming said third doped region is performed simultaneously, and wherein said first doped region, said second doped region, and said third doped region in combination form a PN junction; and 
         [0015]    forming, a first shallow trench isolation structure between said second doped region and said third doped region, wherein said first shallow trench isolation structure isolates said second doped region from said third doped region, wherein said capacitor comprises a main capacitance, wherein said structure comprises a first parasitic capacitance and a second parasitic capacitance, wherein said main capacitance comprises a capacitance between said second doped region and said third doped region, wherein said first parasitic capacitance represents a parasitic connection between said second doped region and said first doped region, wherein said second parasitic capacitance represents a parasitic connection between said third doped region and said first doped region, wherein a first distance between said second doped region and said first doped region is about equal to a second distance between said third doped region and said first doped region, and wherein said first parasitic capacitance is about equal to said second parasitic capacitance. 
         [0016]    The present invention advantageously provides a structure and associated method for forming a symmetric capacitor with terminals comprising equivalent electrical properties. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  illustrates a schematic diagram of an equivalent circuit for a capacitor formed within a semiconductor device, in accordance with embodiments of the present invention. 
           [0018]      FIGS. 2A-2G  illustrates stages in a fabrication process of the capacitor of  FIG. 1 , in accordance with embodiments of the present invention. 
           [0019]      FIG. 2H  illustrates a top view of the substrate structure in the semiconductor device of  FIG. 2F , in accordance with embodiments of the present invention. 
           [0020]      FIG. 2I  illustrates a top view of the substrate structure in the semiconductor device of  FIG. 2G , in accordance with embodiments of the present invention. 
           [0021]      FIG. 3A  illustrates an alternative semiconductor device to the semiconductor device of  FIG. 2F , in accordance with embodiments of the present invention. 
           [0022]      FIG. 3B  illustrates an alternative semiconductor device to the semiconductor device of  FIG. 3A , in accordance with embodiments of the present invention. 
           [0023]      FIG. 4A  illustrates an alternative semiconductor device to the semiconductor device of  FIG. 3A , in accordance with embodiments of the present invention. 
           [0024]      FIG. 4B  illustrates an alternative semiconductor device to the semiconductor device of  FIG. 4A , in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0025]      FIG. 1  illustrates a schematic diagram of an equivalent circuit for a capacitor  9  formed within a semiconductor device  2 , in accordance with embodiments of the present invention. The capacitor  9  comprises a main capacitor (Cm), a first parasitic capacitor (Cp 1 ) and a second parasitic capacitor (Cp 2 ). The first parasitic capacitor Cp 1  represents a parasitic connection from a first electrode  8  of the main capacitor Cm to a semiconductor (e.g., silicon) substrate  15  within the semiconductor device  2 . The second parasitic capacitor Cp 2  represents a parasitic connection from a second electrode  10  of the main capacitor Cm to the substrate  15 . The main capacitor Cm is a high density capacitor comprising a density of about 0.15 fF/um 2  to about 5.0 fF/um 2 . A distance from the first electrode  8  of the main capacitor Cm to the semiconductor (e.g., silicon) substrate  15  is about equal to a distance from the second electrode  10  of the main capacitor Cm to the semiconductor (e.g., silicon) substrate  15  and therefore the first parasitic capacitor Cp 1  comprises a capacitance that is about equal to the second parasitic capacitor Cp 2 . The about equal capacitance values of the first parasitic capacitor Cp 1  and the second parasitic capacitor Cp 2  cause the capacitor  9  to be a symmetric capacitor. Additionally, the capacitor  9  comprises a high (e.g., 50 to 1) ratio of main capacitance (i.e., capacitance of main capacitor Cm) to parasitic capacitance (capacitance values of the first parasitic capacitor Cp 1  and the second parasitic capacitor Cp 2 ). 
         [0026]      FIGS. 2A-2G  illustrates and details stages in a fabrication process of the capacitor  9  of  FIG. 1 , in accordance with embodiments of the present invention.  FIGS. 2A-2G  represents a cross sectional view. The fabrication process described with respect to  FIGS. 2A-2G  illustrates the formation of the capacitor  9  within a semiconductor device  2 . The semiconductor device  2  may be, inter alia, a semiconductor chip. 
         [0027]    In  FIG. 2A , a substrate  15  within a semiconductor device  2  is provided for the fabrication process, in accordance with embodiments of the present invention. The substrate  15  may include, inter alia, a silicon substrate, a SOI substrate, a GaAs substrate, an InP substrate, etc. 
         [0028]      FIG. 2B  illustrates substrate  15  of  FIG. 2A  after a resist layer  17  has been deposited (and patterned) over portions of the substrate  15 , in accordance with embodiments of the present invention. The resist layer  17  may be patterned using, inter alia, a lithography process, a lithography process with a dry etch or wet etch, etc. Ion implant  19  is directed at a portion  23  of the substrate  15  in order to form a first doped region  21   a  in the substrate  15 . Ion implant  19  may comprise, inter alia, a deep ion implementation, a shallow ion implementation, etc. The first doped region  21   a  may comprise an N+ dopant (e.g., phosphorus, arsenic, antimony, etc) or a P+ type (e.g., boron, aluminum, gallium, indium, etc). 
         [0029]      FIG. 2C  illustrates the substrate  15  of  FIG. 2B  after resist layer  17  has been removed and a resist layer  25  has been deposited (and patterned) over portions of the substrate  15 , in accordance with embodiments of the present invention. In order to form the shallow trench isolation structures  28 , exposed portions of the substrate  15  (i.e., portions that are not protected by the resist layer  25 ) have been removed (e.g., using an etching process) so that the shallow trench isolation structures  28  may be formed within trenches formed by removing the exposed portions of the resist layer  25 . The resist layer  25  may be patterned using, inter alia, a lithography process, a lithography process with a dry etch or wet etch, etc. The resist layer  25  is removed prior to the filling of shallow trench with a dielectric material. The shallow trench isolation structures  28  may comprise an oxide or high-K dielectric material. A high-K dielectric material is defined herein as a dielectric material comprising a dielectric constant that is greater than or equal to about 20. 
         [0030]      FIG. 2D  illustrates the substrate  15  of  FIG. 2C  after resist layer  25  has been removed and a resist layer  31  has been deposited (and patterned) over the shallow trench isolation structures  28 , in accordance with embodiments of the present invention. Ion implant  34  is directed at the exposed portions of the substrate  15  in order to simultaneously form doped regions  35  in the substrate  15 . Ion implant  34  may comprise, inter alia, a deep ion implementation, a shallow ion implementation, etc. The doped regions  35  have an opposite polarity to a polarity of the doped region  21   a.  The doped regions  35  may comprise a P+ type dopant (e.g., boron, aluminum, gallium, indium, etc) or a N+ dopant (e.g., phosphorus, arsenic, antimony, etc). The doped regions  35  form electrodes  8  and  10  of capacitor  9  of  FIG. 1 . 
         [0031]      FIG. 2E  illustrates the substrate  15  of  FIG. 2D  after resist layer  31  has been removed and a resist layer  58  has been deposited (and patterned) over the shallow trench isolation structures  28  and the doped regions  35 , in accordance with embodiments of the present invention. Ion implant  40  is directed at the exposed portions of the substrate  15  in order to form doped regions  42  in the substrate  15 . Ion implant  40  may comprise, inter alia, a deep ion implementation, a shallow ion implementation, etc. The doped regions  42  have a same type of dopant as the first doped region  21   a.  The doped regions  42  may comprise an N+ dopant (e.g., phosphorus, arsenic, antimony, etc) or a P+ dopant (e.g., boron, aluminum, gallium, indium, etc). The doped regions  42  are electrically shorted to the first doped region  21   a.  The doped regions  35  in combination with the doped region  21   a  form a PN junction. The doped regions are biased electrically such that the PN junction is reverse biased. 
         [0032]      FIG. 2F  illustrates a substrate structure  15   a  formed from the substrate  15  of  FIG. 2E  comprising the capacitor  9  from  FIG. 1 , in accordance with embodiments of the present invention. The substrate structure  15   a  comprises all of the structures formed in the substrate  15  during the process illustrated in  FIGS. 2A-2E . The substrate  15  comprises a P-type substrate. The first doped region  21  a comprises an N+ doped region. The doped regions  42   a  and  42   b  comprise N+ doped regions. The first doped region  21   a  is electrically connected to the doped regions  42   a  and  42   b.  The capacitor Cm is formed by P+ doped regions  35   a,    35   b,    35   c,    35   d,  and the shallow trench isolation structures  28   a  . . .  28   e.  The capacitor Cm utilizes the P+ doped regions  35   a,    35   b,    35   c,  and  35   d  as electrodes or plates for the capacitor Cm (i.e.,  35   a  and  35   c  form a first electrode and  35   b  and  35   d  form a second electrode). The P+ doped region  35   a  is isolated from the P+ doped region  35   b  by the shallow trench isolation structure  28   b.  The P+ doped region  35   b  is isolated from the P+ doped region  35   c  by the shallow trench isolation structure  28   c.  The P+ doped region  35   c  is isolated from the P+ doped region  35   d  by the shallow trench isolation structure  28   d.  A capacitance comprised by the capacitor Cm is controlled by a distance D 1  between the P+ doped region  35   a  and the P+ doped region  35   b  (i.e., a width of the shallow trench isolation structure  28   b ), a distance D 2  between the P+ doped region  35   b  and the P+ doped region  35   c  (i.e., a width of the shallow trench isolation structure  28   c ), a distance D 3  between the P+ doped region  35   c  and the P+ doped region  35   d  (i.e., a width of the shallow trench isolation structure  28   d ) and an area (i.e., a plate area) of the P+ doped region  35   a  . . .  35   d.  A first parasitic capacitor (e.g., see Cp 1  in  FIG. 1 ) represents a parasitic connection between the P+ doped region  35   a  and  35   c  (i.e., a first electrode of the capacitor Cm) and the first doped region  21   a.  A second parasitic capacitor (e.g., see Cp 2  in  FIG. 1 ) represents a parasitic connection between the P+ doped region  35   b  and  35   d  (i.e., a second electrode of the capacitor Cm) and the first doped region  21   a.  A distance (e.g., about 1500 angstroms to 5000 angstroms) from the P+ doped region  35   a  and  35   c  (i.e., a first electrode of the capacitor Cm) to the first doped region  21   a  is about equal to a distance(e.g., about 1500 angstroms to 5000 angstroms) from the P+ doped region  35   b  and  35   d  (i.e., a second electrode of the capacitor Cm) to the first doped region  21   a  and therefore the first parasitic capacitor Cp 1  comprises a capacitance that is about equal to the second parasitic capacitor Cp 2 . The about equal capacitance values of the first parasitic capacitor Cp 1  and the second parasitic capacitor Cp 2  cause the capacitor Cm to be a symmetric capacitor. Additionally, the capacitor Cm comprises a high (e.g., 50 to 1) ratio of main capacitance (i.e., capacitance of capacitor Cm) to parasitic capacitance (capacitance values of the first parasitic capacitor Cp 1  and the second parasitic capacitor Cp 2 ). The capacitor Cm in  FIG. 2F  is high density capacitor comprising a density of about 0.15 fF/um 2 . A voltage may be applied to the first doped region  21   a  (i.e., an N+ region) through the doped regions  42   a  and  42   b.  The capacitors Cm is isolated from the substrate  15 . 
         [0033]      FIG. 2G  illustrates an alternative substrate structure  15   b  to the substrate structure  15   a  of  FIG. 2F , in accordance with embodiments of the present invention. In contrast with  FIG. 2F , a doped region  21   b  comprises a P+ doped region. The doped regions  42   c  and  42   d  comprise P+ doped regions. The first doped region  21   b  is electrically connected to the doped regions  42   c  and  42   d.  The capacitor Cm is formed by N+ doped regions  35   e  . . .  35   h  and the shallow trench isolation structures  28   b,    28   c,  and  28   d.  The capacitor Cm utilizes the N+ doped regions  35   e,    35   f,    35   g,  and  35   h  as electrodes or plates for the capacitor Cm. The N+ doped region  35   e  is isolated from the N+ doped region  35   f  by the shallow trench isolation structure  28   b.  The N+ doped region  35   f  is isolated from the N+ doped region  35   g  by the shallow trench isolation structure  28   c.  The N+ doped region  35   g  is isolated from the N+ doped region  35   h  by the shallow trench isolation structure  28   c.  A capacitance comprised by the capacitor Cm is controlled by a distance D 1  between the P+ doped region  35   e  and the P+ doped region  35   f  (i.e., a width of the shallow trench isolation structure  28   b ), a distance D 2  between the P+ doped region  35   f  and the P+ doped region  35   g  (i.e., a width of the shallow trench isolation structure  28   c ), a distance D 3  between the P+ doped region  35   g  and the P+ doped region  35   h  (i.e., a width of the shallow trench isolation structure  28   d ) and an area (i.e., a plate area) of the P+ doped region  35   e  . . .  35   h.  A voltage may be applied to the first doped region  21   b  (i.e., a P+ region) through the P+ doped regions  42   c  and  42   d.  The capacitor Cm is isolated from the substrate  15 . 
         [0034]      FIG. 2H  illustrates a top view of the substrate structure  15   a  in the semiconductor device  2  of  FIG. 2F , in accordance with embodiments of the present invention. In addition to the substrate structure  15   a  of  FIG. 2F , the substrate structure  15   a  in  FIG. 2H  illustrates a terminal  47   a  electrically connected to P+ doped regions  35   a  and  35   c  and a terminal  47   b  electrically connected to P+ doped regions  35   b  and  35   d.  The terminals  47   a  and  47   b  are for connecting the capacitor Cm to another circuit. 
         [0035]      FIG. 21  illustrates a top view of the substrate structure  15   b  in the semiconductor device  2  of  FIG. 2G , in accordance with embodiments of the present invention. In addition to the substrate structure  15   b  of  FIG. 2G , the substrate structure  15   a  in  FIG. 21  illustrates a terminal  47   a  electrically connected to N+ doped regions  35   e  and  35   g  and a terminal  47   b  electrically connected to N+ doped regions  35   f  and  35   h.  The terminals  47   a  and  47   b  are for connecting the capacitor Cm to another circuit. 
         [0036]      FIG. 3A  illustrates an alternative semiconductor device  2   a  to the semiconductor device  2  of  FIG. 2F , in accordance with embodiments of the present invention. In contrast with the semiconductor device  2  of  FIG. 2F , the semiconductor device  2   a  of  FIG. 3A  comprises vertical parallel plate (VPP) structures  72   a  . . .  72   d.  The VPP structures  72   a  . . .  72   d  increase an area for the electrodes or plates  35   a  . . .  35   d  and therefore allows the capacitor Cm in  FIG. 3A  to achieve a higher capacitance value than the capacitor Cm in  FIG. 2F  while maintaining a low parasitic capacitance (i.e., capacitance for Cp 1  and Cp 2  in  FIG. 1 ) thereby maintaining a high (e.g., 50 to 1) ratio of main capacitance (i.e., capacitance of capacitor Cm) to parasitic capacitance (capacitance values of the first parasitic capacitor Cp 1  and the second parasitic capacitor Cp 2 ). The VPP structure  72   a  is electrically connected to the doped region  35   a,  the VPP structure  72   b  electrically connected to the doped region  35   b,  the VPP structure  72   c  is electrically connected to the doped region  35   c,  and the VPP structure  72   d  is electrically connected to the doped region  35   d.  The VPP structure  72   a  comprises a wire structure  62   a,  a wire structure  53   a,  a contact via  59   a,  and a contact  50   a.  The contact via  59   a  electrically connects the wire structure  62   a  to the wire structure  53   a.  The contact  50   a  electrically connects the doped region  35   a  to the wire structure  53   a.  The VPP structure  72   b  comprises a wire structure  62   b,  a wire structure  53   b,  a contact via  59   b,  and a contact  50   b.  The contact via  59   b  electrically connects the wire structure  62   b  to the wire structure  53   b.  The contact  50   b  electrically connects the doped region  35   b  to the wire structure  53   b.  The VPP structure  72   c  electrically connected to the doped region  35   c  and the VPP structure  72   d  is electrically connected to the doped region  35   d.  The VPP structure  72   c  comprises a wire structure  62   c,  a wire structure  53   c,  a contact via  59   c,  and a contact  50   c.  The contact via  59   c  electrically connects the wire structure  62   c  to the wire structure  53   c.  The contact  50   c  electrically connects the doped region  35   c  to the wire structure  53   c.  The VPP structure  72   d  comprises a wire structure  62   d,  a wire structure  53   d,  a contact via  59   d,  and a contact  50   d.  The contact via  59   d  electrically connects the wire structure  62   d  to the wire structure  53   d.  The contact  50   d  electrically connects the doped region  35   d  to the wire structure  53   d.  The capacitor Cm in  FIG. 3A  is a high density capacitor comprising a density of about 0.65 fF/um 2 . A dielectric layer(s)  90  may be formed over the substrate structure  15   a  and surrounding the VPP structures  72   a  . . .  72   d.  The dielectric layer(s)  90  may comprise, inter alia, a standard BEOL dielectric film(s) such as undoped silicate glass, fluorinated silicate glass, a low k dielectric layer(s), etc. A low k dielectric is defined herein as a dielectric material comprising a dielectric constant that is less than or equal to about 3. 
         [0037]      FIG. 3B  illustrates an alternative semiconductor device  2   b  to the semiconductor device  2   a  of  FIG. 3A , in accordance with embodiments of the present invention. In contrast with the semiconductor device  2   a  of  FIG. 3A , the semiconductor device  2   b  comprises the substrate structure  15   b  of  FIG. 2G . 
         [0038]      FIG. 4A  illustrates an alternative semiconductor device  2   c  to the semiconductor device  2   a  of  FIG. 3A , in accordance with embodiments of the present invention. In contrast with the semiconductor device  2   a  of  FIG. 3A , the semiconductor device  2   c  of  FIG. 4A  comprises gate layers G 1  . . . G 4  and gate oxide layers  75   a  . . .  75   d  formed between the contacts  50   a  . . .  50   d  and doped regions  35   a  . . .  35   d.  The aforementioned configuration in  FIG. 4A  allows the capacitor Cm in  FIG. 4A  to achieve significantly higher capacitance values than the capacitor Cm in  FIG. 3A  because the gate layers G 1  . . . G 4  and gate oxide layers  75   a  . . .  75   d  formed between the contacts  50   a  . . .  50   d  and doped regions  35   a  . . .  35   d  form higher capacitance values. The gate layers G 1  . . . G 4  may comprise any material including, inter alia, polysilicon. The gate oxide layers  75   a  . . .  75   d  may comprise any dielectric material including inter alia, silicon dioxide, etc. The gate oxide layers  75   a  . . .  75   d  may comprise a high-K dielectric material. The gate oxide layer  75   a  is formed over the doped region  35   a  and the gate layer G 1  is formed over the gate oxide layer  75   a.  The gate oxide layer  75   b  is formed over the doped region  35   b  and the gate layer G 2  is formed over the gate oxide layer  75   b.  The gate oxide layer  75   c  is formed over the doped region  35   c  and the gate layer G 3  is formed over the gate oxide layer  75   c.  The gate oxide layer  75   d  is formed over the doped region  35   d  and the gate layer G 4  is formed over the gate oxide layer  75   d.  The capacitor Cm in  FIG. 4A  is high density capacitors each comprising a density of about 5.0 fF/um 2 . 
         [0039]      FIG. 4B  illustrates an alternative semiconductor device  2   d  to the semiconductor device  2   c  of  FIG. 4A , in accordance with embodiments of the present invention. In contrast with the semiconductor device  2   c  of  FIG. 4A , the semiconductor device  2   d  of  FIG. 4A  comprises the substrate structure  15   b  of  FIG. 2G . 
         [0040]    While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.