Abstract:
An internal voltage generator for a semiconductor memory device is provided. The internal voltage generator includes a first reference voltage generator for generating a first reference voltage, a second reference voltage generator for generating a second reference voltage, a core voltage generator for raising a core voltage based on the first reference voltage, and a core voltage discharger for discharging the core voltage depending on the second reference voltage.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to semiconductor design technologies, and more particularly, to an internal voltage generator for a semiconductor memory device for stably generating a core voltage applied to its internal circuits.  
       BACKGROUND  
       [0002]     As well-known in the art, cell size within a semiconductor memory chip has become smaller as the chip is more highly integrated. Also, the operating voltage decreases due to meet requirements of the smaller-sized cell. Most semiconductor memory chips employ an operating voltage derived from an external power supply voltage VDD, but such a power supply voltage may introduce noise or change in its level. Therefore, an internal voltage generator has been provided within a chip to generate a stable internal voltage, in which a stable operation is always performed even in change of the external power supply voltage.  
         [0003]      FIG. 1  is a block diagram of a conventional internal voltage generator.  
         [0004]     Referring to  FIG. 1 , the internal voltage generator  20  for applying a core voltage VCORE to an internal circuit  10  includes a sense amplifier over driving portion  21 , a core voltage supplier  22 , a core voltage discharger  23  and a reference voltage generator  24 .  
         [0005]     Prior to describing the operation, various signals used therein are first defined as follows. An external voltage VR, which is a high voltage that may vary with a process, is divided to provide several reference voltages. A division control signal TRIM refers to a control signal to generate a constant supply reference voltage VREF based on the external voltage VR. The supply reference voltage VREF generally has ½ voltage level of required target value of the core voltage VCORE.  
         [0006]     The circuit configurations of the sense amplifier over driving portion  21 , the core voltage supplier  22  and the core voltage discharger  23  are already well-known in the art, and thus, details thereof will be omitted. The circuit configuration of the reference voltage generator  24  that is related to the present invention, however, will be illustrated below.  
         [0007]     The following is a brief operation description of the sense amplifier over driving portion  21 , the core voltage supplier  22  and the core voltage discharger  23 .  
         [0008]     The sense amplifier over driving portion  21  serves to apply a short circuit connection between an external power supply voltage VDD and the core voltage end VCORE and then apply the external power supply voltage VDD directly to the core voltage end VCORE so that sufficient core voltage VCORE is supplied to the internal circuit  10  when an activation signal Act (not shown) for activating the operation of Dynamic Random Access Memory (DRAM) is applied thereto.  
         [0009]     The core voltage supplier  22  compares the supply reference voltage VREF with ½ voltage level of the core voltage VCORE (hereinafter, “half core voltage”) and charges the core voltage VCORE when the half core voltage is lower than the supply reference voltage VREF.  
         [0010]     The core voltage discharger  23  compares the supply reference voltage VREF with the half core voltage and discharges the core voltage VCORE when the half core voltage is higher than the supply reference voltage VREF.  
         [0011]     The reference voltage generator  24  divides the external voltage VR and provides a required voltage level among the divided external voltages as the supply reference voltage VREF in response to the division control signal TRIM.  
         [0012]      FIG. 2  is a detailed circuit diagram of the reference voltage generator  24  shown in  FIG. 1 .  
         [0013]     With reference to  FIG. 2 , the reference voltage generator  24  is provided with a voltage divider  27  for receiving and dividing an external voltage VR, and a reference voltage output portion  28  for providing one of voltage levels at nodes N 1  to N 3  of the voltage divider  27  as the supply reference voltage VREF depending on first to third division control signals TRIM 1  to TRIM 3 .  
         [0014]     To be more specific, the voltage divider  27  is composed of a plurality of resistors R 1  to R 4  connected in series between the external voltage end VR and a ground voltage end VSSA, and provides divided voltages into which the external voltage VR is divided at each of the nodes N 1  to N 3 .  
         [0015]     The reference voltage output portion  28  is composed of inverters INV 1  to INV 3  that receive the first to third division control signal TRIM 1  to TRIM 3 , and first to third transfer gates G 1  to G 3  for outputting any one of the voltage levels at the first to third nodes N 1  to N 3  as the discharge reference voltage VREF in response to the first to third division control signal TRIM 1  to TRIM 3  and respective corresponding output signals of the inverters N 1  to N 3 .  
         [0016]     For example, if the voltage level at the second node N 2  has the supply reference voltage VREF as required, the second division control signal TRIM 2  becomes logic high and the first and third division control signals TRIM 1  and TRIM 3  become logic low. Thus, only the second transfer gate G 2  is enabled and the divided external voltage level at the second node N 2  is output as the supply reference voltage VREF.  
         [0017]     Similarly, the voltage levels at the first node N 1  and the third node N 3  may be provided as the supply reference voltage VREF as required in response to the first to third division control signals TRIM 1  to TRIM 3 .  
         [0018]      FIG. 3  shows a simulation result for the input/output signals of the reference voltage generator  24  shown in  FIG. 1 . Here, the supply reference voltage VREF is one of the voltages into which the external voltage VR is divided and has a voltage level lower than that of the external voltage VR  
         [0019]      FIG. 4  is a waveform for describing a change in voltage level of the core voltage VCORE created according to the prior art.  
         [0020]     Referring to  FIGS. 1 and 4 , when an activation signal Act to activate the operation of DRAM is input, the core voltage VCORE is decreased by operation of the internal circuit  10  and the sense amplifier over driving portion  21  and the core voltage supplier  22  charges the decreased core voltage VCORE. In the meantime, the core voltage discharger  23  compares the supply reference voltage VREF with the half core voltage and discharges the core voltage VCORE if the half core voltage is higher than the supply reference voltage.  
         [0021]     In other words, it can be seen that the internal voltage generator  20  according to the prior art provides the single supply reference voltage VREF generated by the reference voltage generator  24  to the core voltage supplier  22  and the core voltage discharger  23  as the reference voltage.  
         [0022]     Accordingly, when the core voltage VCORE is discharged by the core voltage discharger  23 , it is discharged beyond the target value of the core voltage VCORE due to a response speed delay of the core voltage discharger  23 . The discharged core voltage VCORE is again charged by the core voltage supplier  22 . For the above reason, the core voltage VCORE assumes an unstable, saw tooth like, waveform while repeating the charge and discharge operations.  
         [0023]     The external voltage VR that may vary with a process is divided at each of the nodes N 1  to N 3  of the voltage divider  27  shown in  FIG. 2  and a desired voltage level among the divided voltages can be provided as the supply reference voltage VREF as required according to the first to third division control signals TRIM 1  to TRIM 3 .  
         [0024]     However, since the core voltage supplier  22  and the core voltage discharger  23  receive the single constant supply reference VREF generated by the reference voltage generator  24 , the core voltage VCORE has an unstable voltage level while repeating the charge and discharge operations owing to the response speed delay of the core voltage discharger  23 .  
       SUMMARY OF THE INVENTION  
       [0025]     It is, therefore, an object of the present invention to provide an internal voltage generator for a semiconductor memory device which generates a discharge reference voltage in consideration of a response speed delay of a core voltage discharger and applies it thereto to thereby prevent unnecessary charge/discharge operations.  
         [0026]     In accordance with one aspect of the present invention, there is provided an internal voltage generator for a semiconductor memory device, including: a reference voltage generator for generating a first reference voltage and a second reference voltage with a voltage level higher than that of the first reference voltage; a core voltage supplier for raising a core voltage based on the first reference voltage; and a core voltage discharger for discharging the core voltage based on the second reference voltage.  
         [0027]     In accordance with another aspect of the present invention, there is provided an internal voltage generator for a semiconductor memory device, including: a first reference voltage generator for generating a first reference voltage; a second reference voltage generator for generating a second reference voltage; a core voltage generator for raising a core voltage based on the first reference voltage; and a core voltage discharger for discharging the core voltage depending on the second reference voltage.  
         [0028]     The conventional internal voltage generator applies a single reference voltage to a core voltage supplier and a core voltage discharger, which makes a core voltage created by the reference voltage unstable. On the contrary, the internal voltage generator of the present invention provides a supply reference voltage to a core voltage supplier and also a discharge reference voltage higher than the supply reference voltage to a core voltage discharger, thereby generating a more stable core voltage than the prior art generator.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0030]      FIG. 1  is a block diagram of a conventional internal voltage generator;  
         [0031]      FIG. 2  is a detailed circuit diagram of the reference voltage generator shown in  FIG. 1 ;  
         [0032]      FIG. 3  is a diagram of voltage levels for input/output signals of the reference voltage generator shown in  FIG. 1 ;  
         [0033]      FIG. 4  is a waveform diagram for describing a change in voltage level of the core voltage created according to the prior art;  
         [0034]      FIG. 5  is a block diagram of an internal voltage generator in accordance with a preferred embodiment of the present invention;  
         [0035]      FIG. 6  is a detailed circuit diagram of the reference voltage generator shown in  FIG. 5 ;  
         [0036]      FIG. 7  is a diagram of voltage levels for input/output signals of the reference voltage generator shown in  FIG. 6 ; and  
         [0037]      FIG. 8  is a waveform diagram for describing a change in voltage level in accordance with the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0038]      FIG. 5  is a block diagram of an internal voltage generator in accordance with a preferred embodiment of the present invention.  
         [0039]     Referring to  FIG. 5 , the internal voltage generator  200  for applying a core voltage VCORE to an internal circuit  100  includes a sense amplifier over driving portion  210 , a core voltage supplier  220 , a core voltage discharger  230  and a reference voltage generator  240 .  
         [0040]     Prior to describing the operation, various signals used therein are first defined as follows. An external voltage VR, which is a high voltage that may vary with a process, is divided to provide several reference voltages. A division control signal TRIM refers to a control signal to generate a constant supply reference voltage VREF and a discharge reference voltage VREFdischarge based on the external voltage VR. The supply reference voltage VREF has ½ voltage level of a required target value of the core voltage VCORE and the discharge reference voltage VREFdischarge has a voltage level higher than the supply reference voltage by a level that takes into account the response speed delay of the core voltage discharger  230 .  
         [0041]     In operation, the sense amplifier over driving portion  210  serves to apply a short circuit connection between an external power supply voltage VDD and the core voltage end VCORE and then apply it directly to the core voltage end so that the sufficient core voltage VCORE is supplied to the internal circuit  10  when an activation signal Act (not shown) for activating the operation of DRAM is applied thereto.  
         [0042]     The core voltage supplier  220  compares the supply reference voltage VREF with ½ voltage level of the core voltage VCORE (hereinafter, “half core voltage”) and charges the core voltage VCORE when the half core voltage is lower than the supply reference voltage VREF.  
         [0043]     The core voltage discharger  230  compares the discharge reference voltage VREFdischarge with the half core voltage and discharges the core voltage VCORE when the half core voltage is higher than the discharge reference voltage VREFdischarge.  
         [0044]     The reference voltage generator  240  is composed of first and second reference voltage generators  241  and  242 , and divides the input external voltage VR to provide a required voltage level among the divided external voltages as the supply reference voltage VREF and the discharge reference voltage VREFdischarge in response to the division control signal TRIM.  
         [0045]      FIG. 6  is a detailed circuit diagram of the reference voltage generator  240  shown in  FIG. 5 .  
         [0046]     With reference to  FIG. 6 , the reference voltage generator  240  is provided with a voltage divider  270  for receiving and dividing an external voltage VR, a reference voltage output portion  280  for providing one of voltage levels at second and fourth nodes N 5  to N 7  of the voltage divider  270  as the supply reference voltage VREF in response to first to third division control signals TRIM 1  to TRIM 3 , and a discharge reference voltage output portion  290  for providing one of voltage levels at first to third nodes N 4  to N 6  of the voltage divider  270  as the discharge reference voltage VREFdischarge in response to the first to third division control signals TRIM 1  to TRIM 3 .  
         [0047]     More specifically, the voltage divider  270  is composed of a plurality of resistors R 5  to R 9  connected in series between the external voltage end VR and a ground voltage end VSSA, and provides different divided voltages into which the external voltage VR is divided at each of the nodes N 4  to N 7 .  
         [0048]     The supply reference voltage output portion  280  is provided with inverters INV 4  to INV 6  for receiving the first to third division control signals TRIM 1  to TRIM 3 , and first to third transfer gates G 4  to G 6  for outputting one of the divided voltages at the second to fourth nodes N 5  to N 7  as the supply reference voltage VREF in response to the first to third division control signal TRIM 1  to TRIM 3  and respective corresponding output signals of the inverters INV 4  to INV 6 .  
         [0049]     The discharge reference voltage output portion  290  is provided with inverters INV 7  to INV 9  for receiving the first to third division control signals TRIM 1  to TRIM 3 , and fourth to sixth transfer gates G 7  to G 9  for outputting one of the divided voltages at the first to third nodes N 4  to N 6  as the discharge reference voltage VREFdischarge in response to the first to third division control signal TRIM 1  to TRIM 3  and respective corresponding output signals of the inverters INV 7  to INV 9 .  
         [0050]     Although the present invention has been described with respect to the preferred embodiment, it should be noted that the embodiment is for illustration but not for limitation. Further, it will be apparent to those skilled in the art that various changes or modifications may be made within the technical aspect of the present invention.  
         [0051]     In operation, the voltage divider  270  accepts the external voltage VR and provides the divided different voltages at each of the nodes N 4  to N 7  via the resistors R 5  to R 9  connected in series. The supply reference voltage output portion  280  outputs one of the voltage levels at the second to fourth nodes N 5  to N 7  as the supply reference voltage VREF in response to the first to third division control signal TRIM 1  to TRIM 3 . The discharge reference voltage output portion  290  provides one of the voltage levels at the nodes N 4  to N 6  as the discharge reference voltage VREFdischarge in response to the first to third division control signal TRIM 1  to TRIM 3 .  
         [0052]     For instance, if the voltage level at the third node N 6  has the supply reference voltage VREF as required, the second division control signal TRIM 2  becomes logic high and the first and third division control signals TRIM 1  and TRIM 3  become logic low. Thus, only the second and fifth transfer gate G 5  and G 8  are enabled and the remaining transfer gates G 4 , G 6 , G 7  and G 9  are disabled, so that the divided voltage level at the third node N 6  is output as the supply reference voltage VREF and the voltage level at the second node N 5  as the discharge reference voltage VREFdischarge.  
         [0053]     It is possible that the external voltage VR rises during the process. In this case, the third division control signal TRIM 3  becomes logic high and the first and second division control signals TRIM 1  and TRIM 2  become logic low. Accordingly, the voltage level at the fourth node N 7  is given as the supply reference voltage VREF and the voltage level at the third node N 6  as the discharge reference voltage VREFdischarge.  
         [0054]     On the contrary, in case where the external voltage VR falls, the first division control signal TRIM 1  becomes logic high and the second and third division control signals TRIM 2  and TRIM 3  become logic low, and thus, the voltage level at the second node N 5  is provided as the supply reference voltage VREF and the voltage level at the first node N 4  as the discharge reference voltage VREFdischarge.  
         [0055]      FIG. 7  shows voltage of the reference voltage generator  240  shown in  FIG. 6 .  
         [0056]     In  FIG. 7 , there are shown the external voltage VR, the discharge reference voltage VREFdischarge into which the external voltage VR is divided, the supply reference voltage VREF. It can be seen that the discharge reference voltage VREFdischarge has a voltage level higher than that of the supply reference voltage VREF.  
         [0057]     Referring back to  FIG. 6 , the discharge reference voltage VREFdischarge that is issued by the control of the first to third division control signal TRIM 1  to TRIM 3  always has a voltage level higher than that of the supply reference voltage VREF. For instance, let&#39;s assume that when the external voltage VR is “1.4 V,” the voltage into which the external voltage VR is divided at the first node N 4  is “1.2 V,” the voltage at the second node N 5  is “1.0 V,” the voltage at the third node N 6  is “0.8 V,” the voltage at the fourth node N 7  is “0.6 V.” Then, when the supply reference voltage VREF has the voltage level of “0.6 V” at the fourth node N 7 , the discharge reference voltage VREFdischarge has the voltage level of “0.8 V” at the third node N 6  higher than that of the supply reference voltage VREF. Further, when the supply reference voltage VREF has the voltage level of “1.0 V” at the second node N 5 , the discharge reference voltage VREFdischarge has the voltage level of “1.2 V” at the first node N 4  higher than that of the supply reference voltage VREF.  
         [0058]      FIG. 8  is a waveform for describing a change in voltage level at the core voltage end VCORE created in accordance with the present invention.  
         [0059]     With reference to  FIGS. 5 and 8 , when an activation signal Act to active the operation of DRAM is input, the core voltage VCORE is decreased by operation of the internal circuit  100  and the sense amplifier over driving portion  210  and the core voltage supplier  220  charge the decreased core voltage VCORE.  
         [0060]     In the meantime, the core voltage discharger  230  compares the discharge reference voltage VREFdischarge with the half core voltage and discharges the core voltage VCORE if the half core voltage is higher than the discharge reference voltage VREFdischarge.  
         [0061]     At this time, the core voltage discharger  230  receives the discharge reference voltage VREFdischarge higher than the supply reference voltage VREF, which takes into account the response speed delay of the core voltage discharger  230 . Accordingly, the core voltage VCORE is discharged by just its target value, thereby keeping the target value and thus a stable state.  
         [0062]     As described above, the present invention provides a core voltage discharger with a discharge reference voltage higher than a supply reference voltage, thereby generating a core voltage to be input to an internal circuit more rapidly and stably and also preventing unnecessary charge/discharge operations.  
         [0063]     The present application contains subject matter related to Korean patent application Nos. 2005-91565 and 2006-38700, filed with the Korean Intellectual Property Office on Sep. 29, 2005 and Apr. 28, 2006, the entire contents of which are incorporated herein by reference.  
         [0064]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.