Abstract:
A system and method are disclosed for controlling a regulator circuit that outputs a plurality of radio frequency power amplifier bias voltages. A feedback loop is connected to the regulator circuit from the plurality of bias voltages that are output from the regulator circuit. The feedback loop comprises a demultiplexer circuit and a multiplexer circuit that are connected to the regulator circuit. The demultiplexer circuit and the multiplexer circuit each receive an enable signal and provide a feedback signal to the regulator circuit from the bias voltage that is associated with the received enable signal. The invention allows the regulator circuit to be configured as needed to provide different values of radio frequency power amplifier bias voltages.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The system and method of the present invention is generally directed to the manufacture of integrated circuits and, in particular, to a system and method for controlling a regulator circuit for multi-band radio frequency power amplifier biases. 
     BACKGROUND OF THE INVENTION 
     Portable communication devices such as cellular phones typically have a number of radio frequency (RF) power amplifiers (PAs) in order to be able to handle transmissions on a number of different communication standards (e.g., Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM/EDGE)) and on different communication bands (e.g., low band (800 MHz to 900 MHz), high band (1.8 GHz to 1.9 GHz). Each power ampflifier (PA) may have its own individual value of bias voltage. 
     In prior art radio frequency (RF) power management circuits, each individual value of bias voltage may be provided by an individual regulator (e.g., low drop out (LDO) regulator) in order to meet specified load requirements. For communication systems that have many different power amplifiers (PAs), this approach will require many different regulators in order to provide the required bias voltages for the power amplifier (PA) biases. 
     For example, in the Direct Current (DC) to Direct Current (DC) Converter LM3280 manufactured by National Semiconductor Corporation there are three low dropout (LDO) regulators that provide three bias voltages intended for three Wideband Code Division Multiple Access (WCDMA) power amplifiers. This type of architecture is illustrated in  FIG. 1 . 
     As shown in  FIG. 1 , prior art circuit  100  employs three regulators ( 110 ,  120 ,  130 ). First regulator  110  receives an enable signal EN 1  and a reference voltage signal V REF  and outputs an output voltage V BIAS1 . Second regulator  120  receives an enable signal EN 2  and a reference voltage signal V REF  and outputs an output voltage V BIAS2 . Third regulator  130  receives an enable signal EN 3  and a reference voltage signal V REF  and outputs an output voltage V BIAS3 . The three regulators ( 110 ,  120 ,  130 ) operate in parallel. Each regulator may comprise a low dropout (LDO) regulator circuit, a charge pump regulator circuit (also known as a switching capacitor regulator circuit), or any similar type of regulator circuit. 
     In other types of prior art circuits there are two regulators for the low band power amplifiers (PAs) and two regulators for the high band power amplifiers (PAs). There will be a need for an increased number of regulators as cellular phone technology continues to develop. There will be a need to be able to handle more standards and more frequency bands. For example, there are presently ten (10) frequency bands in Wideband Code Division Multiple Access (WCDMA) technology. 
     One prior art approach to reducing the number of regulators for the power amplifier (PA) bias voltages is to switch the output of a regulator to one specific bias voltage output port and disable the other bias voltage output ports. This approach is illustrated in the circuit  200  shown in  FIG. 2 . As shown in  FIG. 2 , one regulator  210  is employed. Regulator  210  separately receives three enable signals (EN 1  and EN 2  and EN 3 ) on a first input. Regulator  210  receives a reference voltage signal V REF  on a second input. Regulator  210  also receives a feedback signal (FB) on a third input. 
     In response to receiving one of the enable signals (e.g., EN 1 ), regulator  210  outputs to a demultiplexer circuit  220  a regulator voltage V REG  that is associated with the received enable signal. The feedback signal (FB) that is provided to the third input of regulator  210  is from a common internal node (V REG ) taken at the output of the regulator  210 . 
     Demultiplexer circuit  220  also separately receives the three enable signals (EN 1  and EN 2  and EN 3 ) on a selector input. When the demultiplexer circuit  220  receives the first enable signal EN 1 , the demultiplexer circuit  220  outputs the regulator voltage signal V REG  that is associated with the first enable signal EN 1  on the first bias voltage output port as V BIAS1 . The other two bias voltage output ports (V BIAS2  and V BIAS3 ) are disabled. 
     When the demultiplexer circuit  220  receives the second enable signal EN 2 , the demultiplexer circuit  220  outputs the regulator voltage signal V REG  that is associated with the second enable signal EN 2  on the second bias voltage output port as V BIAS2 . The other two bias voltage output ports (V BIAS1  and V BIAS3 ) are disabled. Similarly, when the demultiplexer circuit  220  receives the third enable signal EN 3 , the demultiplexer circuit  220  outputs the regulator voltage signal V REG  that is associated with the third enable signal EN 3  on the bias voltage output port as V BIAS3 . The other two bias voltage output ports (V BIAS1  and V BIAS2 ) are disabled. 
     This prior art approach has several problems. First, all of the power amplifiers (PAs) have to have similar steady state levels. Second, there will be differences at the bias voltage outputs due to loading differences. Third, each bias voltage output will have process, temperature and supply variations due to switch resistance variations. 
     Therefore, there is a need in the art for a system and method that is capable of solving the problems that occur in the prior art. In particular, there is a need in the art for a system and method for efficiently controlling a regulator circuit for multi-band radio frequency (RF) power amplifier (PA) biases. 
     The system and method of the present invention solve the problems that are associated with the prior art by controlling the regulator circuit with a feedback loop that is connected to the plurality of the bias voltages that are output from the regulator circuit. The feedback loop comprises a demultiplexer circuit and a multiplexer circuit that each receive an enable signal and provide a feedback signal to the regulator circuit from the bias voltage that is associated with the received enable signal. The system and method of the invention allow the regulator circuit to be configured as needed to provide different values of radio frequency power amplifier bias voltages. 
     Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. 
     Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
         FIG. 1  illustrates a schematic diagram of three prior art regulator circuits that each provide a separate bias voltage intended for a power amplifier circuit; 
         FIG. 2  illustrates a schematic diagram of a prior art regulator circuit that provides a regulator voltage to a demultiplexer circuit that transmits the regulator voltage to a selected one of three bias voltage output ports; 
         FIG. 3  illustrates a schematic diagram of a regulator circuit constructed in accordance with the principles of the present invention; 
         FIG. 4  illustrates a schematic diagram showing a first advantageous embodiment of the present invention for two voltage bias outputs; 
         FIG. 5  illustrates a schematic diagram showing a second advantageous embodiment of the present invention for two voltage bias outputs; and 
         FIG. 6  illustrates a flow chart showing the steps of an advantageous embodiment of a method of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIGS. 3 through 6 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented with any type of suitably arranged integrated circuit device. 
     The system and method of the present invention provides a feedback loop that provides a feedback signal to the regulator directly from the bias voltage outputs.  FIG. 3  illustrates a schematic diagram of an advantageous embodiment  300  of the present invention showing a regulator circuit  310  that separately receives three enable signals (EN 1  and EN 2  and EN 3 ) on a first input. Regulator  310  receives a reference voltage signal V REF  on a second input. Regulator  310  receives a feedback signal (FB) on a third input. The origin of the feedback signal (FB) will be discussed more fully below. In response to receiving one of the enable signals (e.g., EN 1 ), regulator  310  outputs to a demultiplexer circuit  320  a regulator voltage V REG  that is associated with the received enable signal. 
     The three enable signals (EN 1  and EN 2  and EN 3 ) on the first input of regulator  310  may be decoded from a serial interface (e.g., a two-wire Inter-Integrated Circuit (I2C) bus interface or a three-wire Serial Peripheral Interface (SPI) bus interface). A serial interface may also be used to generate individual V REF  signals. 
     In one advantageous embodiment of the invention regulator circuit  310  comprises a low dropout (LDO) regulator circuit. It is understood that the invention is not limited to a regulator circuit  310  that comprises a low dropout (LDO) regulator circuit. Regulator circuit  310  may comprise any suitable type of regulator circuit including, without limitation, a charge pump regulator circuit (also known as a switching capacitor regulator circuit). 
     Demultiplexer circuit  320  also separately receives the three enable signals (EN 1  and EN 2  and EN 3 ) on a selector input. When the demultiplexer circuit  320  receives the first enable signal EN 1 , the demultiplexer circuit  320  outputs the regulator voltage signal V REG  that is associated with the first enable signal EN 1  on the first bias voltage output port as V BIAS1 . The other two bias voltage output ports (V BIAS2  and V BIAS3 ) are disabled. 
     When the demultiplexer circuit  320  receives the second enable signal EN 2 , the demultiplexer circuit  320  outputs the regulator voltage signal V REG  that is associated with the second enable signal EN 1  on the second bias voltage output port as V BIAS2 . The other two bias voltage output ports (V BIAS1  and V BIAS3 ) are disabled. Similarly, when the demultiplexer circuit  320  receives the third enable signal EN 3 , the demultiplexer circuit  320  outputs the regulator voltage signal V REG  that is associated with the third enable signal EN 3  on the third bias voltage output port as V BIAS3 . The other two bias voltage output ports (V BIAS1  and V BIAS2 ) are disabled. 
     The prior art regulator  210  receives a feedback signal (FB) from the common internal node V REG  that is located between the regulator  210  and the demultiplexer  220 . In contrast, the regulator circuit  310  of the present invention receives a feedback signal (FB) directly from the bias voltages that are output from demultiplexer  320 . 
     As shown in  FIG. 3 , the bias voltage signals on the output ports (V BIAS1  and V BIAS2  and V BIAS3 ) are provided to three separate inputs of multiplexer  330 . Multiplexer circuit  330  separately receives the three enable signals (EN 1  and EN 2  and EN 3 ) on a selector input. When the multiplexer circuit  330  receives the first enable signal EN 1 , the multiplexer circuit  330  outputs the first bias voltage signal V BIAS1  as a feedback signal (FB) on feedback line  340  to regulator circuit  310 . The other two bias voltages (V BIAS2  and V BIAS3 ) that are input to multiplexer  330  are disabled. 
     When the multiplexer circuit  330  receives the second enable signal EN 2 , the multiplexer circuit  330  outputs the second bias voltage signal V BIAS2  as a feedback signal (FB) on feedback line  340  to regulator circuit  310 . The other two bias voltages (V BIAS1  and V BIAS3 ) that are input to multiplexer  330  are disabled. Similarly, when the multiplexer circuit  330  receives the third enable signal EN 3 , the multiplexer circuit  330  outputs the third bias voltage signal V BIAS3  as a feedback signal (FB) on feedback line  340  to regulator circuit  310 . The other two bias voltages (V BIAS1  and V BIAS2 ) that are input to multiplexer  330  are disabled. 
     The circuitry  300  of the present invention solves the problems associated with the prior art regulator  210  and prior art demultiplexer  220  shown in  FIG. 2 . The feedback loop of the regulator circuit  310  of the present invention is formed directly from the bias output voltages (V BIAS1  and V BIAS2  and V BIAS3 ) instead of from a common internal node (such as V REG  in  FIG. 2 ). 
     In an alternate advantageous embodiment of the invention, the regulator  310  may be enabled by a separate signal (not shown) before the arrival of an enable signal (e.g., EN 1 ) for one of the desired values of bias voltage (e.g., V BIAS1 ). The purpose of enabling the regulator  310  in advance is so that the value of V REG  will be already stabilized before selecting it for a particular output port. For example, this means that the bias voltage V BIAS1  will be available right away when the enable signal EN 1  is activated. Otherwise, the bias voltage V BIAS1  will be available only after the regulator  310  settles. 
       FIG. 4  illustrates a schematic diagram showing a first advantageous embodiment  400  of the present invention for two voltage bias outputs (V BIAS1  and V BIAS2 ). The regulator circuit  410  may comprise a low dropout (LDO) regulator  410  or a charge pump regulator  410  (or other similar type of regulator). As shown in  FIG. 4 , the regulator circuit  410  receives as inputs (1) a first enable signal EN 1 , (2) a second enable signal EN 2 , (3) a reference voltage signal V REF , and (4) a feedback signal (FE). The regulator circuit  410  outputs regulator voltage V REG  to a demultiplexer circuit that comprises four transistors (M 1 , M 2 , M 3 , M 4 ) that are connected together as shown in  FIG. 4 . 
     The first branch of the demultiplexer comprises P-type metal oxide semiconductor (PMOS) transistor M 1  and N-type metal oxide semiconductor (NMOS) transistor M 2 . A first end of PMOS transistor M 1  is connected to the output of the regulator circuit  410  and a second end of PMOS transistor M 1  is connected to the first bias voltage output port V BIAS1 . NMOS transistor M 2  has one end connected to a node located between PMOS transistor M 1  and the first bias voltage output port V BIAS1 . NMOS transistor M 2  has a second end connected to ground. The gate of the PMOS transistor M 1  and the gate of the NMOS transistor M 2  are connected to an inverted version  EN 1    of the first enable signal EN 1 . When the first enable signal EN 1  is active, the PMOS transistor M 1  provides the regulator voltage V REG  to the V BIAS1  output port. 
     The second branch of the demultiplexer comprises P-type metal oxide semiconductor (PMOS) transistor M 3  and N-type metal oxide semiconductor (NMOS) transistor M 4 . A first end of the PMOS transistor M 3  is connected to the output of the regulator circuit  410  and a second end of the PMOS transistor M 3  is connected to the second bias voltage output port V BIAS2 . NMOS transistor M 4  has one end connected to a node located between PMOS transistor M 3  and the second bias voltage output port V BIAS2 . NMOS transistor M 4  has a second end connected to ground. The gate of the PMOS transistor M 3  and the gate of the NMOS transistor M 4  are connected to an inverted version EN 2  of the second enable signal EN 2 . When the second enable signal EN 2  is active, the PMOS transistor M 3  provides the regulator voltage V REG  to the V BIAS2  output port. 
     The first bias voltage V BIAS1  and the second bias voltage V BIAS2  are also connected to a multiplexer circuit that comprises four transistors (M 5 , M 6 , M 7 , M 8 ) that are connected together as shown in  FIG. 4 . The first branch of the multiplexer circuit comprises the two transistors M 5  and M 6  and the second branch of the multiplexer circuit comprises the two transistors M 7  and M 8 . 
     In the first branch of the multiplexer circuit, P-type metal oxide semiconductor (PMOS) transistor M 5  is coupled in parallel with N-type metal oxide semiconductor (NMOS) transistor M 6  at input node  420  and at output node  430 . The first bias voltage V BIAS1  is provided to input node  420  through a first resistor divider that comprises resistors R 1  and R 2 . The gate of the NMOS transistor M 6  is connected to the first enable signal EN 1  and the gate of the PMOS transistor M 5  is connected to an inverted version EN 1  of the first enable signal EN 1 . The output node  430  is connected to the regulator circuit  410  through feedback line  440 . When the first enable signal EN 1  is active, the output node  430  of the first branch of the multiplexer circuit provides a feedback signal to the regulator circuit  410  on feedback line  440  based on the first bias voltage V BIAS1 . 
     In the second branch of the multiplexer circuit, P-type metal oxide semiconductor (PMOS) transistor M 7  is coupled in parallel with N-type metal oxide semiconductor (NMOS) transistor M 8  at input node  450  and at output node  460 . The second bias voltage V BIAS2  is provided to input node  450  through a second resistor divider that comprises resistors R 3  and R 4 . The gate of the NMOS transistor M 8  is connected to the second enable signal EN 2  and the gate of the PMOS transistor M 7  is connected to an inverted version  EN 2    of the second enable signal EN 2 . The output node  460  is connected to the regulator circuit  410  through feedback line  440 . When the second enable signal EN 2  is active, the output node  460  of the second branch of the multiplexer circuit provides a feedback signal to the regulator circuit  410  on feedback line  440  based on the second bias voltage V BIAS2 . 
     The first advantageous embodiment  400  of the present invention described above utilized a first resistor divider that comprises resistors R 1  and R 2  and a second resistor divider that comprises resistors R 3  and R 4 . It is understood that it is also possible to use a direct feedback signal without the use of resistor divider circuits. 
       FIG. 5  illustrates a schematic diagram showing a second advantageous embodiment  500  of the present invention for two voltage bias outputs (V BIAS1  and V BIAS2 ). The regulator circuit  510  may comprise a low dropout (LDO) regulator  510  or a charge pump regulator  510  (or other similar type of regulator). As shown in  FIG. 5 , the regulator circuit  510  receives as inputs (1) a first enable signal EN 1 , (2) a second enable signal EN 2 , (3) a reference voltage signal V REF , and (4) a feedback signal (FB). The regulator circuit  510  outputs regulator voltage V REG  to a demultiplexer circuit that comprises four transistors (M 9 , M 10 , M 11 , M 12 ) that are connected together as shown in  FIG. 5 . 
     The first branch of the demultiplexer comprises P-type metal oxide semiconductor (PMOS) transistor M 9  and N-type metal oxide semiconductor (NMOS) transistor M 10 . A first end of PMOS transistor M 9  is connected to the output of the regulator circuit  510  and a second end of PMOS transistor M 9  is connected to the first bias voltage output port V BIAS1 . NMOS transistor M 10  has one end connected to a node located between PMOS transistor M 9  and the first bias voltage output port V BIAS1 . NMOS transistor M 10  has a second end connected to ground. The gate of the PMOS transistor M 9  and the gate of the NMOS transistor M 10  are connected to an inverted version  EN 1    of the first enable signal EN 1 . When the first enable signal EN 1  is active, the PMOS transistor M 9  provides the regulator voltage V REG  to the V BIAS1  output port. 
     The second branch of the demultiplexer comprises P-type metal oxide semiconductor (PMOS) transistor M 11  and N-type metal oxide semiconductor (NMOS) transistor M 12 . A first end of the PMOS transistor M 11  is connected to the output of the regulator circuit  510  and a second end of the PMOS transistor M 11  is connected to the second bias voltage output port V BIAS2 . NMOS transistor M 12  has one end connected to a node located between PMOS transistor M 11  and the second bias voltage output port V BIAS2 . NMOS transistor M 12  has a second end connected to ground. The gate of the PMOS transistor M 11  and the gate of the NMOS transistor M 12  are connected to an inverted version  EN 2    of the second enable signal EN 2 . When the second enable signal EN 2  is active, the PMOS transistor M 11  provides the regulator voltage V REG  to the V BIAS2  output port. 
     The first bias voltage V BIAS1  and the second bias voltage V BIAS2  are also connected to a multiplexer circuit that comprises four transistors (M 13 , M 14 , M 15 , M 16 ) that are connected together as shown in  FIG. 5 . The first branch of the multiplexer circuit comprises the two transistors M 13  and M 14  and the second branch of the multiplexer circuit comprises the two transistors M 15  and M 16 . 
     In the first branch of the multiplexer circuit, P-type metal oxide semiconductor (PMOS) transistor M 13  has a first end that is connected to first bias voltage V BIAS1  and a second end that is connected to resistor R 5  of a first resistor divider circuit that comprises resistor R 5  and resistor R 6 . As shown in  FIG. 5 , an output node  520  is located between resistor R 5  and resistor R 6 . Output node  520  is connected to regulator circuit  510  through feedback line  530 . 
     N-type metal oxide semiconductor (NMOS) transistor M 14  has a first end that is connected to resistor R 6  of the first resistor divider circuit. NMOS transistor M 14  has a second end that is connected to ground. The gate of NMOS transistor M 14  is connected to the first enable signal EN 1 . The gate of PMOS transistor M 13  is connected to an inverted version EN 1  of the first enable signal EN 1 . When the first enable signal EN 1  is active, the output node  520  of the first branch of the multiplexer circuit provides a feedback signal to the regulator circuit  510  on feedback line  530  based on the first bias voltage V BIAS1 . 
     In the second branch of the multiplexer circuit, P-type metal oxide semiconductor (PMOS) transistor M 15  has a first end that is connected to second bias voltage V BIAS2  and a second end that is connected to resistor R 7  of a second resistor divider circuit that comprises resistor R 7  and resistor R 8 . As shown in  FIG. 5 , an output node  540  is located between resistor R 7  and resistor R 8 . Output node  540  is connected to regulator circuit  510  through feedback line  530 . 
     N-type metal oxide semiconductor (NMOS) transistor M 16  has a first end that is connected to resistor R 8  of the second resistor divider circuit. NMOS transistor M 16  has a second end that is connected to ground. The gate of NMOS transistor M 16  is connected to the second enable signal EN 2 . The gate of PMOS transistor M 15  is connected to an inverted version EN 2  of the second enable signal EN 2 . When the second enable signal  EN 2    is active, the output node  540  of the second branch of the multiplexer circuit provides a feedback signal to the regulator circuit  510  on feedback line  530  based on the second bias voltage V BIAS2 . 
     The second advantageous embodiment  500  of the present invention described above utilized a first resistor divider that comprises resistors R 5  and R 6  and a second resistor divider that comprises resistors R 7  and R 8 . It is understood that it is also possible to use a direct feedback signal without the use of resistor divider circuits. It is understood that it is also possible to have a resistor and its respective series switch (e.g., resistor R 5  and series switch M 13 ) in a different order. 
     The first advantageous embodiment  400  and the second advantageous embodiment  500  of the present invention has been described for the case in which there are two voltage bias outputs (V BIAS1  and V BIAS2 ). It is understood that the principles of the present invention can be extended to cases in which there are more than two bias voltages. In addition, it is also understood that there are also many other ways to implement a feedback multiplexer circuit depending upon the feedback potential. 
     In the advantageous embodiments of the present invention that have been described a fixed reference voltage V REF  is shown (presumably an internally generated reference voltage). It is understood that it is also possible that the reference voltage V REF  could also be scaled to different values for different values of bias voltage V BIAS . 
       FIG. 6  illustrates a flow chart  600  showing the steps of an advantageous embodiment of a method of the present invention. In the first step of the method a regulator circuit  310  is provided that separately receives a plurality of enable signals and receives a voltage reference signal V REF  and receives a feedback signal FB and outputs a voltage regulation signal V REG  (step  610 ). Then the output of the regulator circuit  310  is connected to the input of a demultiplexer circuit  320  that has a plurality of bias voltage output ports where each of the plurality of bias voltage output ports is associated with one of the plurality of enable signals (step  620 ). 
     Then a multiplexer circuit  330  is provided that separately receives the plurality of enable signals (step  630 ). Then each of the plurality of bias voltage output ports of the demultiplexer circuit  320  is connected to an input of multiplexer circuit  330  that is associated with a respective enable signal (step  640 ). Then the output of the multiplexer circuit  330  is connected to a feedback signal line  340  and the feedback signal line  340  is connected to a feedback input port of the regulator circuit  310  (step  650 ). 
     In response to receiving one of the plurality of enable signals in the demultiplexer circuit  320  and in the multiplexer circuit  330 , the multiplexer circuit  330  provides a feedback signal to the regulator circuit  310  that is related to the bias voltage output that is associated with the received enable signal (step  660 ). 
     The foregoing description has outlined in detail the features and technical advantages of the present invention so that persons who are skilled in the art may understand the advantages of the invention. Persons who are skilled in the art should appreciate that they may readily use the conception and the specific embodiment of the invention that is disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Persons who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 
     For example, it is possible to connect to the regulator circuit  310  a plurality of separate feedback lines (not shown) to form a separate feedback loop from each of the plurality of bias output voltage ports. This embodiment would not need the multiplexer  330 . This approach, however, would not be efficient for large numbers of bias output voltage ports. 
     Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.