Abstract:
An embodiment of the present invention provides a configuration of a cross-coupled common-source differential amplifier stage which enables performing a gain step down (attenuation) while maintaining good step flatness over a large relative bandwidth.

Description:
BACKGROUND 
       [0001]    The present invention relates generally to amplifier circuits, and more specifically to amplifier circuits for high frequency operation having a wide input range. 
         [0002]    Low noise amplifier (LNA) that use differential amplifiers are often used in high performance analog and mixed-signal integrated circuits, as part of a buffer or gain block. An output of a differential amplifier is a measure of the difference between a pair of input signals, so that if the differential amplifier is made of matched transistor devices (e.g., ones that are structural replicates of each other and, accordingly, exhibit very similar DC and AC electrical characteristics), then common mode noise occurring at the inputs of the amplifier or the power supply is significantly reduced at its output. The difficulty in designing a multi-band LNA circuit comes from the fact that it has to provide different functions at different operating frequencies. Therefore, to design a multi-band amplifier, it must satisfy different operating bandwidths at different standards. In order to meet the trends of increasingly standards, the operation bandwidths and gain flatness performance of the multi-band LNA must be improved. The amplifier must be able to provide input matching, wide-band interference rejection and maximum gain flatness performance. However, conventional LNAs can not meet the required of multi-standard function or wide-band solution. 
         [0003]    Thus, a critical need is prevalent for apparatus, systems and methods that enable differential amplifiers, especially when used in LNAs, to overcome at least the gain flatness limitations that limit the suitability to wideband applications. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which: 
           [0005]      FIG. 1  is a block diagram of a cross-coupled common-source differential amplifier with current canceling in accordance to an embodiment; 
           [0006]      FIG. 2  is a schematic diagram of the low noise amplifier (LNA) with a cross-coupled common-source differential amplifier in accordance to an embodiment; and 
           [0007]      FIG. 3  is a graph of gain step flatness, wherein the X-axis corresponds to frequency and the Y-axis is the gain of the LNA circuit of  FIG. 2 . 
       
    
    
       [0008]    It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. 
       DETAILED DESCRIPTION 
       [0009]    In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the preset invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. 
         [0010]    Although embodiments of the invention are not limited in this regard, discussions utilizing terms such as, for example, “processing,” “computing,” “calculating,” “determining,” “establishing”, “analyzing”, “checking”, or the like, may refer to operation(s) and/or process(es) of a computer, a computing platform, a computing system, or other electronic computing device, that manipulate and/or transform data represented as physical (e.g., electronic) quantities within the computer&#39;s registers and/or memories into other data similarly represented as physical quantities within the computer&#39;s registers and/or memories or other information storage medium that may store instructions to perform operations and/or processes. 
         [0011]    Although embodiments of the invention are not limited in this regard, the terms “plurality” and “a plurality” as used herein may include, for example, “multiple” or “two or more”. The terms “plurality” or “a plurality” may be used throughout the specification to describe two or more components, devices, elements, units, parameters, or the like. For example, “a plurality of stations” may include two or more stations. The terms “first,” “second,” and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. 
         [0012]    Referring to  FIG. 1  which illustrates a current canceling amplifier applicable to any type of device technologies, such as high frequency transceivers, wideband transceivers, low noise amplifiers (LNAs), variable gain amplifiers (VGAs), active antennas, phased arrays, phase shifters, and the like. 
         [0013]      FIG. 1  is a block diagram of a cross-coupled (CC) common-source (CS) differential amplifier  100  with current canceling in accordance to an embodiment. The illustrated CCCS differential amplifier  100  comprise a first amplifying stage  110 , a second amplifying stage  120 , coupling transformer  125  at the output port, controller such as multiplexer  107 , and input port  103 . 
         [0014]    In order to get gain attenuation, the stage is split into two sub-stages  110  and  120  that are shorted at input and output. Each stage (illustrated as stage  110  and stage  120 ) includes a common-source (CS) differential stage (M 2 ,M 3 , M 6 , M 7 ) with cross-couple (CC) transistors (M 1 ,M 4 ,M 5 , M 8 ) and DC block capacitors (C 1 , C 4 , C 5 , C 8 , C 2 , C 4 , C 6 , C 7 ), along with big resistors for biasing (R 1 , R 4 , R 5 , R 8 , R 2 , R 3 , R 6 , R 7 ). At each sub-stage such as stage  110  all four (4) transistors (M 1 , M 2 , M 3 , M 4 ) are the same size, although two are common source (CS) and the other two act as their cross-couple (CC) capacitors. As illustrated, CC transistors (M 1 , M 4 , M 5 , and M 8 ) are MOScaps and all DC block capacitors (C 1 , C 4 , C 5 , C 8 , C 2 , C 4 , C 6 , C 7 ) are MOMcaps. The importance of all transistors to be same and all MOMcaps to be same (i.e., matched and symmetrical) is for having exact same path of the RF signal when operating in full gain or attenuated gain (when the current canceling is occurring). The DC block capacitors are connected between the gate of the transistors and an input terminal which is connected to a signal source such as an active antenna, and a bias resistor (R 2 , R 3 , R 6 , R 7 ) to supply bias voltage to the gate transistor is connected as gating voltage (Vbias and Vb). Since the input impedance of the differential amplifier circuit depends on the bias resistor (R 2 , R 3 , R 6 , R 7 ), the resistance value of this bias resistor cannot be reduced below a certain value. Thus one function of the cross-coupling capacitor is to prevent supply back to the signal source a DC potential established at the gate of the transistor, which DC potential is determined by the resistance value of the bias resistor. 
         [0015]    In operation, stage  110  is always “ON” (Vbias=‘1’) while stage  120  has two (2) working modes as selected by a control device such as multiplexer  107 . The first mode is a gain attenuation mode and the second mode is a full gain mode which is normal operation at full gain. In the second mode the common source (CS) differential pair transistors (M 6  and M 7 ) are “ON” (Vb=‘1’) and the cross-coupled (CC) transistors (M 5  and M 8 ) are “OFF” (Vb_b=‘0’). Full gain is achieved because the current at the coupling transformer, output terminal  125 , are in phase causing an accumulation of the output from stage  110  and stage  120 . 
         [0016]    In the gain attenuation mode, first mode, the CS transistors (M 6  and M 7 ) are “OFF” (Vb=‘0’) and the CC transistors (M 5  and M 8 ) “ON” (Vb_b=‘1’) to cause a current canceling/reduction at output terminal  125 . The gain attenuation is caused by the fact that in this mode the CC transistors (M 5  and M 8 ), which are connected with a cross compared to stage  110 , now carry the opposite phase current that resist the main current (i.e., output of stage  110  which is always “ON”), therefore creating “current canceling” that is translated to gain attenuation. Note that the CS transistors (M 6  and M 7 ) that are now in “OFF” mode act as the CC capacitors (MOScaps), that is, the CS transistors (M 6  and M 7 ) and CC transistors(M 5  and M 8 ) of stage  120  actually switched their role in this operating mode. 
         [0017]    The gain attenuation value is determined by the ratio between the stage  110  transistors (M 1 , M 2 , M 3 , and M 4 ) width to the stage  120  transistors (M 5 , M 6 , M 7 , and M 8 ) width. In order to change the attenuation value, one must “transfer” width from left side (stage  110 ) to the right side (stage  120 ) but keep same total width (to keep total gain unchanged). As bigger stage  120  transistor width, the current canceling will be stronger, i.e. bigger attenuation. 
         [0018]    Selectively controlling stage  120  we can see that at all time, there is same size of transistors at “ON” and at “OFF” modes. This fact is important, because it creates constant input impedance towards the former amplifier stage, enabling constant impedance matching and therefore the power gain curve will have same behavior over frequency at different gain modes, i.e., good gain step flatness. This flatness is evident from the graph at  FIG. 3 . The Vb signal is therefore Vbias or Vss, being controlled by a one (1) bit control signal, using a simple MUX cell such as multiplexer  107 , digital-to-analog converter, or duty cycle logic circuit. In order to create Vb_b=NOT (Vb) there is a need for an inverter cell such as inverter  109 . 
         [0019]      FIG. 2  is a schematic diagram showing the inputs and outputs of a differential LNA. The LNA of  FIG. 2  is an integrated differential low noise amplifier and as such has two inputs  201  primarily RF_in_P and RF_in_N. For most differential signals, a signal p applied to RF_in_P will be 180 degrees out of phase with (i.e. of opposite phase to) a signal n applied to RF_in_N. The LNA of  FIG. 2  has two outputs  250 , one for positive components of the differential signal and one for negative components of the differential signal: RF_out_N and RF_out_P. In some implementations the two outputs may be connected to provide a single output. The LNA of  FIG. 2  is powered by a voltage supply VDD and is connected to ground. The voltage supply supplies a DC voltage. A differential amplifier typically has two parts, one for a first differential signal component, e.g. p, and one for a second differential signal component, e.g. n. These parts will be referred to herein as the positive or “plus” side of the differential amplifier and the negative or “minus” side of the differential amplifier. Each side of the differential amplifier will have a corresponding input and output, e.g. for a signal p, the p side will have input RF_in_P and output RF_out_P, likewise for a signal n the n side will have input RF_in_N and output RF_out_P. In some embodiments the p and n sides of the differential amplifier are coupled at the outputs, for example via a coupling transformer. 
         [0020]    LNA circuit  200  employs the concepts enumerated with reference to the cross-coupled (CC) common-source (CS) differential amplifier  100 . The LNA design includes four (4) amplifying stages (DA1, DA2, DA3, and DA4) with transformers (e.g., coupling transformer  207  and input coupling transformer  203 ) between them for impedance matching. Stages 1 and 3 (DA1 and DA3) are regular CS with CC stages like stage  110 , while stages 2 and 4 are automatic gain control (AGC) stages like stage  120  connected to stage  110  as in  FIG. 1  using the idea as explained above. It should be noted that a programmable stage like stage  120  could be used for all the amplifying stages and their functionality could be selected on the fly by a combination of control device such as multiplexer  212  inverter  190 , and data line to carry the control code.  FIG. 3  is a graph showing the gain and AGC results comparing measured ( 320 ,  330 , and  340 ) and simulation  310  values. 
         [0021]    While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents may occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.