Abstract:
A pulse width modulator based on a pair of rotary traveling wave oscillators. The first oscillator operates freely or as part of a phase-locked loop. The second oscillator operates at the same frequency as the first oscillator, but with a controllable phase offset from the first oscillator. The phase offset is set by an input voltage. A block takes the outputs of the first and second oscillators and combines them so that the output is a pulse whose width is the overlap of the oscillation signals from the first and second oscillators. The output pulse width is thus a function of the input voltage. When the pulse width modulator receives the input voltage from the output of a switching power supply, it can use the modulated pulse width to control the switching transistor of the power supply to maintain the output at a regulated voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     1. Field of the Invention 
     The present invention relates generally to pulse width modulators and more specifically to pulse width modulators employing at least one rotary traveling wave oscillator. 
     2. Description of the Related Art 
     DC to DC converters commonly include a switching transistor connected to a filter circuit and a control circuit.  FIG. 1A  shows a simple converter configuration  100 . The converter includes a switching transistor  102 , a diode  104 , an inductor  106 , and a capacitor  108 . The switching transistor  102  is connected between the primary energy source  110 , such as a battery, and a low pass filter circuit  112 , which is formed by the inductor  106  and capacitor  108 , as shown. In this type of converter, the inductor  106  also functions as an energy storage element. The capacitor  108  is connected across the load  112  and is used to filter out voltage variations (ripple) at the load  112  that would otherwise occur. Typically, a diode  104  is connected across the filter circuit  113  and the control circuit  114  is connected to the output and to the switching transistor  102 . 
     Such a converter operates with at least two phases, defined by the state of the switching transistor  102 . During a first phase when the switching transistor  102  is on, energy is transferred from a primary energy source  110 , such as a battery, to a storage element  106 , and in this particular case to the capacitor  108  and the load  112 . During a second phase when the switch is off, energy is transferred from the storage element  106  to the capacitor  108  and the load  112  and the diode  104  operates to maintain continuity of current. 
     The control circuit  114  of the converter  100  has two important tasks. It must monitor the voltage vl  118  at the load  112  and it must compare the monitored voltage to a reference voltage. The output of such a comparison is a control voltage vc. Based on the comparison signal vc internal to the control circuit, the control circuit must create a switch control signal d  116  that sets the on and off times during a switching cycle of the switching transistor  102  to compensate for changes in the primary energy source  110  or the load  112 . Controlling the on and off times of the switching transistor  102  is called duty cycle control, when the cycle frequency is fixed. A signal derived from the duty cycle control signal d  116  then drives the switching transistor  102 . Thus, the control circuit  114  must convert the comparison signal vc to a duty cycle control signal d  116 . 
     A common circuit that performs the conversion from the comparison signal to the duty cycle control signal (vc→d) is a pulse width modulator (PWM). The modulator receives the comparison signal and alters the duty cycle control signal usually in a linear fashion, between a minimum and a maximum duty cycle. For example, if the comparison signal vc ranges from 1.0 to 4.0 volts, the duty cycle control signal d ranges from 10% to 95%. A pulse width modulator operates at some preset switching frequency so that the duty cycle fixes the maximum on and off times of the switching transistor. 
     Switching frequencies from 100 to 200 KHz are common. Switching frequencies determine the size of the energy storage inductor  106  and filter capacitor  108  shown in  FIG. 1A . At 200 KHz, an inductor may have a value of 5 μH and a capacitor a value of 2000 μF. At higher switching frequencies, the values and thus sizes of these components can become much smaller. 
     However, high switching frequencies affect the power lost in driving the switching transistor. Common types of transistors used for the switching transistor include the MOSFET, the IGBT, and the BJT. When the transistor is a MOSFET, these power losses arise from the input capacitance of the MOSFET. During turn on and turn off, the input capacitance of a MOSFET is a combination of a gate-to-source capacitance Cgs and a gate-to-drain capacitance Cgd, both of which vary with the voltage across them because their capacitance derives in part from the depletion layers in the transistor. The greatest variation in capacitance comes from Cgd, which can vary by a factor of 10 to 100 as a function of the drain-to-gate voltage, V DG  (≈V DS ). Charging and discharging these capacitances causes a power loss in the converter according to the relation CV 2 f, where V is the voltage output of the driver and f is the switching frequency, and C is the combination of the Cgs and Cgd capacitances at the voltages across them. Values for Cgs might be about 1000 pF and for Cgd about 150 pF to 1500 pF. If the switching frequency is about 200 KHz, then the power lost in charging and discharging the capacitance of a single switching transistor is about 6 to 12 milliwatts (assuming a 5 Volt swing). The losses due to switching rise linearly with the frequency of operation and affect the efficiency of the converter at low load currents. 
     As mentioned above, a diode is used in combination with the switching transistor to maintain current continuity in the converter. However, diodes also contribute to power losses, thus lowering the efficiency of the converter. For example, if the voltage drop across a diode is about 1 volt with 5 A of current flowing through it, the loss is 5 Watts. This is a serious problem at low loads because the power loss in the diode can be a large fraction of the power delivered to the load, causing low efficiency. Therefore, it is common to replace the diode with a synchronous rectifier. This is shown in  FIG. 1B , where a transistor  152  replaces the diode  104  in  FIG. 1A  and connects via d 2   156  to the control circuit  154 . When the switching transistor  102  is off, the control circuit  154  turns on the synchronous rectifier  152  to maintain continuity of current in the circuit. The synchronous rectifier arrangement substantially lowers the power that would have been dissipated in the diode, because the on-resistance of the transistor  152  can be very small. The on-resistance r DS(on)  of the transistor  152  ranges from 0.01 to 0.1 ohms. However, the additional transistor  152  also causes a frequency-dependent power loss because the control circuit  154  must charge and discharge the input capacitance of the transistor  152 . 
     Also as mentioned above, many converters operate with two phases. Additional phases can improve the converter in at least three ways. First, the additional phases can lower the time to bring the load back into regulation after a significant change in the load occurs. Instead of waiting for multiple switching cycles to occur, the converter need only wait for the additional phases to occur. Second, additional phases can permit the combining of multiple converters so that output currents higher than those obtainable from a single converter are possible. Third, output ripple tends to be smaller in a multiphase converter, making such a converter suitable for a wider variety of applications. However, each additional phase requires at least one additional switch, again increasing CV 2  f dissipation. 
     Given the above considerations, it would be desirable to have a very high frequency power converter, synchronously switched and operating with multiple phases. 
     BRIEF SUMMARY OF THE INVENTION 
     In one embodiment, the present invention is a pulse-width modulator (PWM) formed from a pair of RTWOs. The RTWOs drive the switches of a power converter. 
     One advantage of the present invention are that CV 2 f losses are eliminated. Instead, a small RTWO power overhead is incurred, as the capacitances of the switches become part of the capacitance of the RTWO. 
     Another advantage is that the RTWOs can operate at very high frequencies, permitting components to become physically much smaller. 
     Yet another advantage is that synchronous rectifiers are easily driven from the same RTWOs as the switches. 
     Yet another advantage is that phase shifts that optimally time the synchronous rectifiers are achieved with RTWO phasing and there is no additional CV 2 f penalty when driven with RTWOs. 
     Yet another advantage is that poly phase power supplies simply tap uniform phases on the RTWO, with no significant increase in CV 2 f loss. 
     Yet another advantage is that devices will operate in series. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
         FIG. 1A  shows a conventional step down converter; 
         FIG. 1B  shows a conventional step down converter with a synchronous rectifier; 
         FIG. 2A  shows one embodiment of the present invention; 
         FIG. 2B  shows another embodiment of the present invention; 
         FIG. 2C  shows yet another embodiment of the present invention; 
         FIG. 2D  shows an implementation of the PW block; 
         FIG. 2E  shows an implementation of the PD 2 , T-V, EA, LPF 2 , and CTL blocks; 
         FIG. 3  a conceptual version of the embodiment of  FIG. 2C ; 
         FIG. 4A  shows a power converter using an embodiment of PWM of the present invention; 
         FIG. 4B  shows a power converter using an embodiment of the PWM of the present invention; 
         FIG. 4C  shows a power converter using yet another embodiment of the PWM of the present invention; 
         FIG. 4D  shows a power converter using yet another embodiment of the PWM of the present invention; 
         FIG. 4E  shows a power converter using yet another embodiment of the PWM of the present invention; and 
         FIG. 5  shows a multiphase converter. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     One embodiment  200  of the present invention is a pulse-width modulator.  FIG. 2A  shows the arrangement of blocks for achieving this function. The arrangement includes a first RTWO 1   202  and a second RTWO 2   204 . The RTWO 1   202  may run freely or optionally be phase-locked to a reference such as a crystal oscillator  212 . When RTWO 1   202  operates in a phase-locked loop, blocks PD 1   206 , LPF 1   208  and CTL 1   210  are included. Block PD 1   206  is a phase detector which determines the difference in phase between crystal oscillator output and the RTWO 1  output. Block LPF 1   208  is a low pass filter which averages out the output of the PD block. Block CTL 1   210  is a control block that adjusts the RTWO 1   202  so that its frequency and phase matches that of the crystal oscillator  212 . The first RTWO  202  sets the operating frequency of the PWM. 
     The RTWO 2   204  operates to generate a phase that is offset by a controlled amount from the phase of RTWO 1   202 . The phase offset is controlled by the PD 2   214 , T-V  216 , EA  218 , LPF 2   220 , and CTL 2   222  blocks and Vin  224 . The PD 2  block  214  detects the phase difference between the RTWO 1   202  and RTWO 2   204  outputs. The T-V block  216  converts the output of the PD 2  block  214  into a voltage. The EA block  218  amplifies (a) the difference (Verror=Vref−Vin) between a reference voltage Vref  226  and the input voltage Vin  224 , properly scaled, to create an error voltage Verror, and the (b) difference between the T-V block  216  output and Verror  228 . The LPF 2  block  220  filters the output of the EA block  218 . The CTL 2  block  222  alters the phase and/or frequency of the RTWO 2   204  to have an offset that is, in effect, set by the Verror signal. 
       FIG. 2E  shows one embodiment  250  of the PD 2   214 , T-V  216 , EA  218 , LPF 2   220 , and CTL blocks  222 . The PD 2  block  214  includes the exclusive-OR gate (XOR)  252 , whose function in the circuit is described in more detail below. The T-V block  216  includes an RC filter  254 . The EA block  218  includes a first error amplifier  256  for boosting the difference (Verror) between a scaled Vout and Vref, and a second error amplifier  258  for boosting the difference between the first error amplifier  256  output (Verror) and the filtered output via  254  of the exclusive-OR gate  252 . LPF 2  block  220  is a conventional low pass filter. In this embodiment, the CTL block  222  is a varactor  260  whose capacitance alters the frequency and phase of the RTWO 2   204  in  FIG. 2A . 
     The exclusive-OR gate  252  operates to determine the phase difference between the two RTWOs  202 ,  204 . If the RTWOs  202 ,  204  are in phase alignment (zero phase difference), then the output of the XOR gate  252  is close to zero volts, which is designed to correspond to a no-load condition. If the RTWOs  202 ,  204  are 90 degrees out of phase, then the output of the XOR gate  252  is approximately VOH/2, which is designed to correspond to a maximum load condition. As described above, the output of the XOR gate  252  is filtered and applied to a first input of the second error amplifier  258 , which compares the first input to the second input, received from the first error amplifier  256 . Thus, a voltage error (Verror)  262  between the reference  264  and the scaled output  266  creates a finite-size output pulse from the XOR gate  252 , which attempts to remove the voltage error  264 , via negative feedback. 
     Block PW  228  in  FIGS. 2A and 2B  combines selected output taps of RTWO 1   202  and RTWO 2   204 . The output  229  of the PW block  228  is thus a pulse whose width is modulated by the input Vin  224 .  FIG. 2D  shows an embodiment  270  of the PW block. Instead of using a single switching transistor, two transistors  272 ,  274  are used in series. The top transistor in the series receives the output of RTWO 1   202 . The bottom transistor receives the output of RTWO 2   204 . The pair of transistors  276  has an on time that is the overlap of the two RTWO outputs, as shown. An alternative to two transistors is a single transistor with dual gates (MOSFET) or bases (BJT), although such transistors are less common. 
       FIG. 2B  shows an alternative design  240  in which the phase offset is digitally controlled. In this embodiment, the operation of RTWO 1   202  is the same as in the embodiment of  FIG. 2A . The blocks for controlling the phase offset derived from RTWO 2  are different. These blocks include a PD 2  block  242 , an LPF 2  block  246 , a CTL 2  block  248 , an A/D block  243 , and a PS (Phase Selector) block  247 . The PD 2  block  242  determines the phase difference between RTWO 1   202  and RTWO 2   204 . The LPF 2  block  246  receives the output of the PD 2  block  242  and filters it. The CTL 2  block  248  adjusts the frequency and/or phase of RTWO 2   204 . The A/D block converts  243  the input voltage to a digital value  245 . The PS block  247  selects one of the phases of RTWO 2   204  according to the digital value  245  from the A/D block  243 . Therefore, the Verror signal controls the phase offset from RTWO 2   204  by selecting it in a phase selector  247 . The PW block then combines the output of RTWO 1  and RTWO 2  to create the desired pulse. 
       FIG. 2C  shows a more simple embodiment  300  for digitally controlling the pulse width, which is illustrated conceptually in  FIG. 3 . This embodiment includes an A/D block  302 , a PS block  304  and a PW block  306 , along with a single RTWO  308 . The A/D block  302  receives the voltage Verror  310  to generate a digital version [d 1 , d 2 , . . . , dn]  312  of the control voltage. The digital version of the control voltage [d 1 , d 2 , . . . , dn]  312  operates to select one of N phases tapped directly from the RTWO  308  via the PS block  304 . The PW block  306  receives the selected phase  316  from the RTWO  308  along with a phase from a fixed tap  314  of the RTWO and operates to combine the phases to create the desired pulse width. 
     Power Converter Design 
       FIG. 4A  shows the pulse width modulator used in a power converter  400 . The input voltage Vin  402  connects to the output voltage  404  of the converter via a scaler block  406 , which may increase or decrease the load voltage  404 , and the output of the PW block  408  connects to the duty cycle input d  410  of the converter, as shown. 
       FIG. 4B  shows the pulse width modulator used in a power converter with a synchronous rectifier  104 . In  FIG. 4B , a second PW block  452  is added to form the duty cycle signal  454  for operating the synchronous transistor  104 . 
       FIG. 4C  shows a pulse width modulator used in a power converter  480  with a synchronous rectifier. In  FIG. 4C , the output of each RTWO  202 ,  204  operates the switching transistor  102  and synchronous rectifier  104  directly, eliminating the need for the PW blocks. 
       FIG. 4D  shows a pulse width modulator used in a power converter  500  with a synchronous rectifier  104 . The pulse width modulator uses a digital selection  312  for the phase based on the error voltage  310  from the error amplifier  502 , in accordance with the design in  FIG. 2C . Error amplifier receives input from Vref  504  and the scaler  406  to create the Verror signal  310 . 
       FIG. 4E  shows a pulse width modulator used in a power converter  520  with a synchronous rectifier  104 . The pulse width modulator uses a digital selection  312  for the phase based on the error voltage  310 , in accordance with the design in  FIG. 3 . In  FIG. 4E , it should be noted that not only can the main switching transistor  102  be controlled by the digital phase selector, the synchronous rectifier transistor  104  could also be controlled in the same manner, i.e., by adding a separate phase selector PS circuit  522  that receives the output of the A/D converter  312  and N taps  524  from the RTWO  314 . 
     Multiphase Power Converter 
     Yet another embodiment  550  of the present invention is a multiphase power converter. A portion of such a converter is shown in  FIG. 5 . Each of the switches  552   a,b    554   a,b    556   a,b  charges and discharges inductors  560 ,  562 ,  564  via voltage and current source  564  shown and can be controlled by a PW block derived from pulse width modulator of the present invention or directly from an RTWO, in accordance with  FIG. 4A ,  4 B,  4 C,  4 D, or  4 E. The design  580  in  FIG. 3  can also be used as a PWM for a multiphase converter, by using taps  582   a - n  from the RTWO  584  that are spaced 360/N degrees apart for an N phase converter. 
     Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.