Abstract:
A constant current circuit includes a first FET providing an input reference current flow, a second FET providing an output current flow and a non-linear impedance element connected between the drain and the gate of the first FET. By setting a parameter of the non-linear impedance element and a parameter of the first FET to have a specific relationship with each other, the output current can be maintained at a substantially definite value irrespective of relatively large variations of the input reference current.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a constant current circuit formed to include field effect transistors in a compound semiconductor integrated circuit. 
     In order to realize constant current sources, a current mirror circuits have typically been utilized in the past. For instance, an example thereof wherein Si bipolar elements are used is shown at page 234 of &#34;Analysis and Design of Analog Integrated Circuits,&#34; by Gray Meyer, Second Edition, John Wiley &amp; Sons Inc., 1984, and an example thereof wherein Si MOS field effect transistors are used is shown at page 710 of the same literature. 
     FIG. 2 shows the case where the current mirror circuit is constructed of field effect transistors (hereinafter abbreviated as FETs). In FIG. 2, F21 and F22 denote FETs, R21 a linear resistance element as a load, and V 1  a power source. I ref  denotes a reference current flowing through R21 and F21, and the circuit is so constructed that an output constant current I flows through F22 with said reference current used as an input current. 
     This constant current circuit of FIG. 2 has a defect in that the gate-source voltage V gs  of two FETs F21 and F22 increases and also the output current I increases when the input reference current I ref  increases beyond a prescribed value owing to the voltage fluctuation of the power source V 1 , the nonuniformity in the resistance R 21  and the distribution of the threshold voltage of FET F21. 
     FIG. 3 shows a constant current circuit which was disclosed by Japanese Patent Publication No. 16463/1971. In this circuit, a linear resistance R 51  set as in the following is connected between the collector and the base of a bipolar transistor Q l  on the input side: 
     
         (qR.sub. 51/kT)=1 
    
     where q indicates an amount of charge of electrons, k is a Boltzmann&#39;s constant, and T - absolute temperature. 
     Accordingly, an increase in the base-emitter voltage V BE  of the transistor Q l  caused by an increase in the input reference current I ref  is canceled by an increase in a voltage drop R 51  I ref  of the linear resistance R 51 , and consequently an output current I flowing through the collector of a bipolar transistor Q 2  on the output side remains at a substantially fixed value. 
     SUMMARY OF THE INVENTION 
     However, the studies of the inventors of the present application revealed that the known constant current circuit of FIG. 3 known publicly had the following problems. 
     (1) The cancellation by the linear resistance R 51  is deficient when the input reference current I ref  is small, while it becomes over-cancellation when I ref  is large, and thus the range of the input reference current wherein the output current I is fixed substantially is narrow. 
     (2) Considerations are given only to the setting of the resistance value of the linear resistance R 51  in the case when bipolar transistors are used as the basic elements for constructing the constant current circuit, and no consideration is given to the setting of the resistance value of the resistance R 51  in the case when field effect transistors are used as said basic elements. 
     An object of the present invention is, therefore, to furnish a constant current circuit, the basic elements of which consist of field effect transistors, and which enables the maintenance of an output current at a prescribed definite value even when an input reference current varies over a wide range. 
     Other objects and novel characteristics of the present invention will be apparent from the following description of embodiments. 
     The aforesaid object is attained by connecting an impedance element having non-linear characteristics between the gate and the drain of FET, wherein the input reference current I ref  flows through a drain-source current channel. According to this non-linear characteristics, a voltage drop of αI ref   n  +β (where n≠1) occurs between both ends of said, impedance element. If the mutual conductance of the FET through the input reference current I ref  flows is denoted by k, parameters α, I ref , n and k satisfy the following equation substantially. ##EQU1## 
     The aforesaid impedance element carrying the non-linear characteristics operates to reduce the sensitivity to the fluctuation of an output current I flowing through the current supply source in relation to the non-uniformity in the input reference current I ref  caused by the fluctuation of a source voltage or the like, In other words, it controls a gate voltage of the FET which makes the output current I flow so that the value of I decreases (increases) when the value of I ref  increases (decreases). This operation enables providing a very stable constant current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a constant current circuit according to one embodiment of the present invention; 
     FIGS. 2 and 3 are circuit diagrams of constant current circuits known publicly heretofore; 
     FIG. 4 is a circuit diagram of a constant current circuit according to a concrete embodiment of the present invention; 
     FIG. 5 (a) to (g) show other concrete means to realize a non-linear impedance element of FIG. 1; and 
     FIGS. 6 and 7 show constant current circuits according to improved embodiments. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     One embodiment of the present invention will be described hereunder according to FIG. 1. In FIG. 1, Z1 denotes an impedance element carrying non-linear characteristics, and F11, F12, F13 and F14 denote field effect transistors. 
     F11 is FET which provides an input reference current I ref  flow, while F12 to F14 are FETs which provide output currents I 2  to I 4  flow respectively. One end of Z1 is connected to the gate of F11, and the other end of Z1 to the drain of F11 and the gates of F12 to F14, while the source of F11 and F12 to F14 are connected to ground potential points. The respective sources of F11 and F12 to F14 can also be connected to the ground potential points through the intermediary of linear resistances. 
     Now, it is assumed that Z1 is a non-linear element and that a potential difference arising between both ends of Z1 is expressed by αI ref   n+  β. If an effect of drain conductance is ignored, on the occasion, I ref  can be expressed by 
     
         I.sub.ref =K.sub.l (V.sub.gsl -V.sub.th1).sup.2            (1). 
    
     In this equation, K 1  denotes mutual conductance of F11, and V th1  denotes a threshold voltage of F11. From the equation (1) ##EQU2## If a current flowing through F12 is denoted by I 2 , on the other hand, the following equation is established in the same way. ##EQU3## Herein K 2  denotes the mutual conductance of F12, and V th2  a threshold voltage of F12. Furthermore, the relationship 
     
         V.sub.gs1 =V.sub.gs2 +(αI.sub.ref.sup.n +β)     (4) 
    
     is established, and therefore, if V th1  =V th2 , ##EQU4## Thus, the following equation is obtained. ##EQU5## If a value of I ref  whereat (dI 2  /dI ref )= 0 is calculated from the equation (6), ##EQU6## 
     In the case when FETs F11 and F12 to F14 of FIG. 1 are Schottky barrier type field effect transistors formed on a GaAs substrate, a gate current comes to flow from gate electrodes into source electrodes or drain electrodes when a gate voltage exceeds 0.6 V. When it is 0.6 V or below, however, the input impedance of the gate electrodes is very large, and then the construction of FIG. 1 can be realized. Although the gate voltage, i.e. V gs2  of F12 to F14 needs to be 0.6 V or below in this case, the necessity is met constantly by setting the gate voltage V gs1  of F11 at 0.6 V or below. 
     FIG. 4 is a circuit diagram of a constant current circuit according to a concrete embodiment of the present invention, and an impedance element Z1 carrying non-linear characteristics consists of a field effect transistor F3 the drain and the gate of which are connected together by short-circuiting. 
     If the mutual conductances of FETs F11, F12 and F3 are denoted by K l , K 2  and K 3 , the gate-source voltages thereof by V gs1 , V gs2  and V gs3 , and the threshold voltages thereof by V th1 , V th2  V th3 , ##EQU7## 
     From the above equations (8), (9) and (10), the following equation is obtained. ##EQU8## The condition of (dI 2  /dI ref )=0 is K 1  =K 3 . This condition can be realized easily by forming FETs F11 and F3 at the same time and under the same manufacturing conditions in the same integrated circuit chip. 
     Besides, it can be seen that the aforesaid condition of K 1  =K 3  corresponds to the case of n=1/2 and α=1√/k 3  in the above equation (7). 
     Moreover, it is necessary to set the relationship of V th1  -V th2  -V th3  ≠0 for realizing I 2  ≠0 under the condition of K 1  =K 3 . For this purpose, it is preferable to set any two of V th1 , V th2  and V th3  (e.g. V th2  and V th3 ) to be equal to each other and to set the remaining one (e.g. V th1 ) at a value not being zero. It is effective, for this purpose, to form FETs F11 and F3 at the same time and under the same manufacturing conditions. High-precision control of the threshold voltage V th2  by ion implanation of impurities into a channel region of FET F2 is effective to this end. 
     FIG. 5 (a) to (g) show other concrete means to realize the non-linear impedance element of FIG. 1. F01 to F06 denote field effect transistors, D, G and S the respective drains, gates and sources thereof, R03 to R05 linear resistances, and D01 a diode. 
     F01 in FIG. 5 (a) is FET an of a normally-ON type (depletion mode). In FIG. 5 (f) and (g), a fixed bias voltage is impressed on the gates G of F05 and F06. 
     The FET described above may be an FET other than of a Schottky junction type, for example namely, an HEMT element or MOS-type FET. Besides, a constant current constituent element may be constructed on other than the GaAs substrate, on an Si substrate, for instance. 
     FIG. 6 shows a circuit wherein the sources of FETs F20 to F40 are connected to the drains of FETs F12 to F14 of FIG. 1 respectively and a fixed bias V 3  is impressed on the gates of FETs F20 to F40. Consequently, the drain voltage of FETs F12 to F14 is stabilized, and thereby output currents I 2  to I 4   are stabilized. 
     FIG. 7 is an illustration of one embodiment concerned with a case wherein V3 in FIG. 6 is generated by a power source V1, and shows a method wherein the potential of V1 is divided by impedance elements Z3 and Z4 and supplied. Z3 and Z4 can be constructed of resistance elements or the like. 
     According to the present invention, as described above, an output current can be maintained at a prescribed value irrespective of wide-range variation of an input reference current, in a constant current circuit using FET as a basic element.