Abstract:
A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates generally to the fabrication of semiconductor integrated circuit devices, and more specifically to a technique for fabricating contacts with zero offset.  
           [0003]    2. Description of the Prior Art  
           [0004]    Formation of field effect transistors in integrated circuits often includes the formation of lightly doped drain (LDD) regions adjacent the channel. This minimizes hot-electron effects, and improves operation of the transistor. In order to form these LDD regions using a self-aligned process, a sidewall oxide (SiO 2 ) spacer is formed along side the transistor gate.  
           [0005]    When forming the oxide sidewall spacers, it is necessary to over etch the oxide layer from which they are formed in order to insure that all contact areas are completely clear. This over etching also damages field oxide regions, and significant over etch of the field oxide regions can allow implanted dopants to penetrate through the field oxide during later source/drain formation.  
           [0006]    Also, it is necessary to insure that substrate contacts are not misaligned so as to extend over the gate electrodes. When this type of misalignment happens, etching required to clear the contact of interlevel oxide can damage the oxide cap and sidewall spacers on the gate. Significant damage of the oxide sidewall spacer can cause a short between the sidewall and gate.  
           [0007]    A number of processing approaches have been used to address these and other problems. One approach is to deposit a thick oxide on top of the gate prior to the gate definition etch. This provides some margin, but does not solve the problem of the required enclosure near gate electrodes.  
           [0008]    Other approaches use additional poly layers as “landing pads” for contacts in the matrix of DRAM and SRAM devices.  
           [0009]    As described in parent application Ser. No. 639,316, which has been incorporated herein to by reference, spacers formed of silicon nitride may be used for LDD definition. These spacers protect the gate from later over etching during contact formation, because silicon nitride and oxide can be highly selectively etched over each other.  
           [0010]    As device geometries continue to shrink, contacts are formed which have a very high aspect ratio. This is particularly true between adjacent gate electrodes in a device having regular structure, such as a memory matrix. It is difficult to provide sufficient barrier metal at the bottom of these high aspect ratio openings to provide proper protection for the underlying substrate.  
           [0011]    It would therefore be desirable to provide an improved technique for fabricating contacts and semiconductor integrated circuits which addresses and solves the problems described above.  
         SUMMARY OF THE INVENTION  
         [0012]    Therefore, in accordance with the present invention, a technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0014]    [0014]FIGS. 1 through 6 illustrate a preferred method for fabricating semiconductor integrated circuit contacts in accordance with the present invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0015]    The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figure representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.  
         [0016]    Referring to FIG. 1, a contact is to be formed to a selected portion of integrated circuit substrate  10 . On an upper surface of the substrate is formed a gate oxide layer  12 , which may be a thermal oxide or ONO layer as known in the art. Polycrystalline silicon layer  14  is deposited over the gate oxide layer  12 , and doped to improve conductivity as known in the art. Preferably, a refractory metal silicide layer  16  can be formed over the polycrystalline silicon layer  14  to improve conductivity of the poly layer. Finally, a layer of silicon nitride  18  is deposited over the refractory metal silicide layer  16 .  
         [0017]    Using photoresist (not shown) as known in the art, the device is patterned and etched to form an opening  20  through layers  12 ,  14 ,  16 ,  18 , and expose a portion of substrate  10 . A reoxidation step is performed as known in the art to form a thermal oxide layer  22  on the exposed substrate surface. Oxide layer  22  also forms along side sidewalls of the gate electrodes  24  which were defined by the previous etch step. A dopant implant step is performed to create LDD region  26  between the gate electrodes  24 .  
         [0018]    Referring to FIG. 3, nitride sidewall spacers  28 ,  30  are formed alongside the gate electrodes  24  as known in the art. These spacers are formed by a blanket conformal deposition of silicon nitride, followed by anisotropic etch back to leave sidewall spacers  28 ,  30 . A heavy dopant implant is used to form source/drain region  32 , with the sidewall spacers  28 ,  30  defining LDD regions  26  for the two transistors.  
         [0019]    Referring to FIG. 4, the interlevel oxide layer is then formed over the device. In a preferred embodiment, a layer  34  of undoped oxide is conformally deposited over the device, followed by a layer of BPSG, or similar oxide such as SOG. Deposition of SOG, or reflow of a BPSG layer, provides a relatively planar upper surface for layer  36 .  
         [0020]    Referring to FIG. 5, an opening  38  is etched through the interlevel oxide to expose portions of the substrate  10 . This etch will remove portions of layers  36 ,  34 , and  22 . An etch is used which is selective for oxide over nitride, so that the sidewall spacers  28 ,  30 , and the nitride cap layer  18 , protects the gate  24  during this step.  
         [0021]    In FIG. 5, the opening  38  is misaligned with respect to the contact region with the substrate  10 . Ideally, opening  38  would be properly aligned. However, in actual processing it is common for openings to be somewhat misaligned as shown. Because nitride layer  18  and spacers  28 ,  30  protect the gates  24  during the opening etch step, alignment is not critical during this self-aligned process.  
         [0022]    Once opening  38  has been formed, a layer of doped amorphous or polycrystalline silicon  40  is formed over the device. This layer should be formed to a depth sufficient to completely fill all openings such as opening  38 , which will typically leave fairly thick portions of layer  40  over regions outside the opening  38 .  
         [0023]    Referring to FIG. 6, polycrystalline silicon layer  40  is etched back, using chemical and mechanical polishing, or other etchback techniques, to form an amorphous or polycrystalline silicon reach-up plug  42 . As shown in FIG. 6, plug  42  has an upper surface approximately coplanar with the upper surface of oxide layer  36 . In actual practice, plug  42  will usually be etched a little below the surface of oxide layer  36  to ensure that all amorphous or polycrystalline silicon is removed from the surface of layer  36 .  
         [0024]    A barrier metal layer  44  is formed over the device, followed by aluminum (typically aluminum alloy with small amounts of copper and silicon) layer  46 . The barrier layer is typically formed from materials such as titanium and titanium nitride. The metal layer  44  may also be formed from tungsten or another suitable material. Because the upper surface of plug  42  is approximately co-planar with the upper surface of oxide layer  36 , the barrier metal layer  44  is formed with 100% coverage. In other words, because the barrier metal layer  44  does not reach down into a relatively deep opening having a high aspect ratio, a good, reliable barrier layer is formed. This remains true even if the layer  40  is overetched somewhat; the upper surface of the plug  42  is close enough to the surface of oxide layer  36  that the problems caused by PVD of a metal into a deep opening do not occur. The high quality of barrier layer  44  on the plug  42  prevents the formation of junction spikes (if the interconnect material is aluminum) or volcanos (if the interconnect material is tungsten).  
         [0025]    Although FIG. 6 shows the use of a metal layer over the poly plug  42 , this technique can be used with multiple levels of poly/silicide contacts as well.  
         [0026]    In a typical embodiment, the following ranges of layer thicknesses and sizes may be used. As will be appreciated by those skilled in the art, these numbers may be modified to suit various processing requirements.  
         [0027]    Typically, polycrystalline silicon layer  14  has a thickness of between 1500 and 2000 angstroms, as does silicide layer  16 . Typically, the poly layer is a little thicker than silicide layer  16 . Silicon nitride layer  18  preferably has a thickness of approximately 1000 angstroms. Layers  16  and  18  are preferably deposited using CVD processing.  
         [0028]    The silicon nitride layer which is deposited to form spacers  28 ,  30  is typically deposited to a thickness of 2000 to 4000 angstroms. Thickness of this layer is determined by the necessary spacer width of the resulting sidewalls. Polycrystalline silicon layer  40  is preferably deposited using a technique such as LPCVD, which generally results in amorphous rather than polycrystalline silicon. Preferably, layer  40  is doped in situ but doping could be done afterward using techniques known in the art.  
         [0029]    It will be appreciated by those skilled in the art that materials other than those specified may be used for the sidewall and top cap layers. The sidewalls should have the property that they can be selectively etched over the material used for the interlevel dielectric, and vice versa. Also, depending on the application, materials other than amorphous or polycrystalline silicon could be used to form the reach-up plug in the opening.  
         [0030]    When a contact is formed using the technique described above, a superior contact is formed while completely protecting the gate electrodes from damage due to contact opening misalignment. Because the gate is so well protected, zero enclosure designs are possible. Because the material in plug  42  is very highly doped, typically approximately 10 20  atoms/cm 3 , contact resistance remains low even in cases of fairly significant misalignment.  
         [0031]    Although the invention has been described with reference to a specific embodiment, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments that fall within the true scope of the invention.