Abstract:
There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. An occupation ratio of the semiconductor element in the semiconductor device is enhanced, the semiconductor device can be miniaturized, and a mounting density onto a circuit board can be enhanced. By forming outer electrodes on the outer terminals, multiple pins can further be provided, which is difficult with a small-sized semiconductor device such as conventional TSOP and the like.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    (i) Field of the Invention  
           [0002]    The present invention relates to a resin-sealed semiconductor device with a semiconductor element mounted thereon, a circuit member for use therein and a method of manufacturing a circuit member.  
           [0003]    (ii) Description of the Related Art  
           [0004]    Recently, there has been a tendency (trend) toward the progress of technique for high integration and miniaturization and toward the sophistication and lightening/shortening of electrical equipment. Therefore, semiconductor devices represented by ASIC of LSI have increasingly advanced in high integration and high function.  
           [0005]    To accompany the advancement, also in a sealed-type semiconductor device using a lead frame, the trend of its development has progressed via surface mounting type packages such as SOJ (Small Outline J-Bend Package) and QFP (Quad Flat Package) to the miniaturization of a package mainly by thinning the package like TSOP (Thin Small Outline Package) and further to a structure of LOC (Lead On Chip) which aims at improvement of a chip containing efficiency by three-dimensionally constructing the inside of a package.  
           [0006]    However, the resin-sealed semiconductor device is requested not only to be highly integrated and sophisticated but also to be provided with multiple pins and have a thinned and miniaturized structure. Even in the conventional package described above, since leads are drawn around in an outer peripheral portion of a semiconductor element, the miniaturization of the package is limited.  
           [0007]    Furthermore, in the small package such as TSOP and the like, the provision of multiple pins is also limited in respect of the drawing-around of leads and the pin pitch.  
         SUMMARY OF THE INVENTION  
         [0008]    Wherefore, an object of the invention is to realize a resin-sealed semiconductor device which has a high occupation ratio of a semiconductor element and can be miniaturized, enhance a mounting density onto a circuit board and further provide multiple pins and to provide a circuit member for use in the semiconductor device and a method of manufacturing the circuit member.  
           [0009]    To attain this and other objects, the invention provides a resin-sealed semiconductor device in which plural circuit portions integrally having inner terminals and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, the inner terminals of the circuit portions are electrically connected to terminals of a semiconductor element with wires and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. In the device, the circuit portions have leads for integrally interconnecting the inner terminals and the outer terminals, surfaces of the circuit portions are semiconductor element mounted faces on which the inner terminals, the leads and the outer terminals form one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner terminals and terminal faces of the outer terminals, the semiconductor element is mounted in such a manner that a terminal mounted face of the semiconductor element is mounted via an insulating layer on the semiconductor element mounted faces of the circuit portions, and the terminals of the semiconductor element are electrically connected with wires to the terminal faces of the inner terminals.  
           [0010]    The invention also provides a resin-sealed semiconductor device in which plural circuit portions integrally having inner terminals and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, the inner terminals of the circuit portions are electrically connected to terminals of a semiconductor element with wires and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. In the device, the circuit portions have leads for integrally interconnecting the inner terminals and the outer terminals, surfaces of the circuit portions are semiconductor element mounted faces on which the inner terminals, the leads and the outer terminals form one plane, the inner terminals and the leads are thinner than the outer terminals, the surfaces of the circuit portions are provided with terminal faces of the inner terminals, back surfaces of the circuit portions are provided with terminal faces of the outer terminals, the semiconductor element is mounted in such a manner that a face opposite to a terminal mounted face of the semiconductor element is mounted via an insulating layer on the semiconductor element mounted faces of the circuit portions, and the terminals of the semiconductor element are electrically connected with wires to the terminal faces of the inner terminals.  
           [0011]    The invention provides a circuit member for use in manufacture of a resin-sealed semiconductor device in which plural circuit portions integrally having inner terminals and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, the inner terminals of the circuit portions are electrically connected to terminals of a semiconductor element with wires and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. The circuit member comprises an outer frame member and plural circuit portions extended from the outer frame member via connection leads independent of one another. The circuit portions are arranged two-dimensionally substantially in a plane. Each circuit portion is constituted by integrally interconnecting the outer terminal, a lead and the inner terminal in this sequence to a tip end of each connection lead. Surfaces of the circuit portions are semiconductor element mounted faces on which the inner terminals, the leads and the outer terminals form one plane, and the inner terminals and the leads are thinner than the outer terminals.  
           [0012]    The invention also provides a circuit member for use in manufacture of a resin-sealed semiconductor device in which plural circuit portions integrally having inner terminals and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, the inner terminals of the circuit portions are electrically connected to terminals of a semiconductor element with wires and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. The circuit member comprises an outer frame member and plural circuit portions extended from the outer frame member via connection leads independent of one another. The circuit portions are arranged two-dimensionally substantially in a plane. Each circuit portion is constituted by integrally interconnecting the inner terminal, a lead and the outer terminal in this sequence to a tip end of each connection lead. Surfaces of the circuit portions are semiconductor element mounted faces on which the inner terminals, the leads and the outer terminals form one plane, and the inner terminals and the leads are thinner than the outer terminals.  
           [0013]    The invention provides a method of manufacturing a circuit member for a resin-sealed semiconductor device in which plural circuit portions integrally having inner terminals and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, the inner terminals of the circuit portions are electrically connected to terminals of a semiconductor element with wires and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. The method has an outer configuration processing process of half-etching a conductive board with one face of the conductive board being left as a surface to form the circuit member provided with an outer frame member and plural circuit portions extended from the outer frame member via connection leads independent of one another. In the outer configuration processing process, plural circuit portions are arranged two-dimensionally substantially in a plane, and each circuit portion is constituted by integrally interconnecting the outer terminal, a lead and the inner terminal in this sequence to a tip end of each connection lead. Surfaces of the circuit portions are made as semiconductor element mounted faces on which the inner terminals, the leads and the outer terminals form one plane, the inner terminals and the leads are made thinner than the conductive board, and the outer terminals are made as thick as the conductive board.  
           [0014]    The invention further provides a method of manufacturing a circuit member for a resin-sealed semiconductor device in which plural circuit portions integrally having inner terminals and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, the inner terminals of the circuit portions are electrically connected to terminals of a semiconductor element with wires and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. The method has an outer configuration processing process of half-etching a conductive board with one face of the conductive board being left as a surface to form the circuit member provided with an outer frame member and plural circuit portions extended from the outer frame member via connection leads independent of one another. In the outer configuration processing process, plural circuit portions are arranged two-dimensionally substantially in a plane, and each circuit portion is constituted by integrally interconnecting the inner terminal, a lead and the outer terminal in this sequence to a tip end of each connection lead. Surfaces of the circuit portions are made as semiconductor element mounted faces on which the inner terminals, the leads and the outer terminals form one plane, the inner terminals and the leads are made thinner than the conductive board, and the outer terminals are made as thick as the conductive board.  
           [0015]    In the aforementioned invention, the occupation ratio of the semiconductor element in the resin-sealed semiconductor device is raised, the semiconductor device can be miniaturized, and a mounting density onto a circuit board can be enhanced. Furthermore, by forming outer electrodes on the outer terminals, multiple pins can be easily mounted, which is difficult in the conventional TSOP or another small-sized semiconductor device. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 is a diagrammatic view showing a structure of an embodiment of a resin-sealed semiconductor device according to the invention.  
         [0017]    [0017]FIG. 2 is a plan view of the resin-sealed semiconductor device of FIG. 1 seen from an outer-electrode side.  
         [0018]    [0018]FIG. 3 is a perspective view of the outer-electrode side of the resin-sealed semiconductor device shown in FIG. 1.  
         [0019]    [0019]FIG. 4 is an enlarged perspective view showing one circuit portion of the resin-sealed semiconductor device shown in FIG. 1.  
         [0020]    [0020]FIG. 5 is a diagrammatic view showing a constitution of another embodiment of the resin-sealed semiconductor device according to the invention.  
         [0021]    [0021]FIG. 6 is a diagrammatic view showing a constitution of another embodiment of the resin-sealed semiconductor device according to the invention.  
         [0022]    [0022]FIG. 7 is a diagrammatic view showing a constitution of another embodiment of the resin-sealed semiconductor device according to the invention.  
         [0023]    [0023]FIG. 8 is a plan view of the resin-sealed semiconductor device of FIG. 7 seen from an outer-electrode side.  
         [0024]    [0024]FIG. 9 is a perspective view of the outer-electrode side of the resin-sealed semiconductor device shown in FIG. 7.  
         [0025]    [0025]FIG. 10 is an enlarged perspective view showing one circuit portion of the resin-sealed semiconductor device shown in FIG. 7.  
         [0026]    [0026]FIG. 11 is a diagrammatic view showing a constitution of another embodiment of the resin-sealed semiconductor device according to the invention.  
         [0027]    [0027]FIG. 12 is a diagrammatic view showing a constitution of another embodiment of the resin-sealed semiconductor device according to the invention.  
         [0028]    [0028]FIG. 13 is a plan view showing an embodiment of a circuit member according to the invention.  
         [0029]    [0029]FIG. 14 is an enlarged perspective view of a section of the circuit member surrounded with a chain line III shown in FIG. 13 as seen from a back-surface side.  
         [0030]    [0030]FIG. 15 is a plan view showing another embodiment of the circuit member according to the invention.  
         [0031]    [0031]FIG. 16 is an enlarged perspective view of a section of the circuit member surrounded with a chain line V shown in FIG. 15 as seen from a back-surface side.  
         [0032]    [0032]FIG. 17 is a process diagram showing an embodiment of a method of manufacturing the circuit member according to the invention.  
         [0033]    [0033]FIG. 18 is a process diagram showing a method of manufacturing the resin-sealed semiconductor device shown in FIGS.  1  to  4  by using the circuit member according to the invention.  
         [0034]    [0034]FIG. 19 is a process diagram showing anther embodiment of the method of manufacturing the circuit member according to the invention.  
         [0035]    [0035]FIG. 20 is a process diagram showing a method of manufacturing the resin-sealed semiconductor device shown in FIGS.  7  to  10  by using the circuit member according to the invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0036]    Preferred embodiments of the invention will be described with reference to the accompanying drawings.  
         [0037]    Resin-sealed Semiconductor Device  
         [0038]    First, a resin-sealed semiconductor device of the invention will be described.  
         [0039]    [0039]FIG. 1 is a diagrammatic view showing a resin-sealed semiconductor device according to an embodiment of the invention, and FIG. 2 is a view of the resin-sealed semiconductor device shown in FIG. 1 as seen from an outerterminal side. FIG. 3 is a perspective view clearly showing the outer-terminal side and side faces of the resin-sealed semiconductor device shown in FIG. 1. Furthermore, FIG. 4 is an enlarged perspective view showing one circuit portion of the resin-sealed semiconductor device shown in FIG. 1. Additionally, FIG. 1 is a vertical sectional view taken along a one-dot chain line I-I of FIG. 2. Moreover, to facilitate the understanding of a positional relationship of the circuit portion and a semiconductor element in FIG. 2, the circuit portion is shown by a two-dot chain line while the semiconductor element is shown by a chain line.  
         [0040]    In a resin-sealed semiconductor device  1  shown in FIGS.  1  to  4 , plural circuit portions  30 A are arranged two-dimensionally substantially in a plane and electrically independent of one another. The circuit portion  30 A has a lead  33  for integrally interconnecting an inner terminal  31  and an outer terminal  32 . Furthermore, since the resin-sealed semiconductor device  1  is manufactured by using a circuit member described later, a connection lead  34  remains extending from the outer terminal  32  toward the side face of the resin-sealed semiconductor device  1 . A surface  30 S of the circuit portion  30 A is a semiconductor element mounted face on which the inner terminal  31 , the lead  33  and the outer terminal  32  form one plane. Additionally, the inner terminal  31  and the lead  33  are thinner than the outer terminal  32 , and a back surface  30 B of the circuit portion  30 A is provided with a terminal face  31 S of the inner terminal  31  and a terminal face  32 S of the outer terminal  32 . Therefore, on the back surface  30 B of the circuit portion  30 A, the terminal face  32 S of the outer terminal  32  is protruded in a convex configuration from the back surface. Additionally, a silver plating layer  60  is formed on the terminal face  31 S of the inner terminal  31 .  
         [0041]    For a semiconductor element  10 , a face of the semiconductor element  10  on the side of terminals  11  is mounted via insulating layers  20  on the semiconductor element mounted faces  30 S of the circuit portions  30 A. The terminals  11  of the semiconductor element  10  are electrically connected with wires  40  to the terminal faces  31 S (the silver plating layers  60 ) of the inner terminals  31 .  
         [0042]    The semiconductor element  10 , the circuit portions  30 A and the wires  40  are sealed with a sealing member  50  in such a manner that the outer terminals  32  are partially exposed to the outside. For the sealing member  50 , a known sealing resin material for use in the resin-sealed semiconductor device can be used. In the embodiment shown in FIG. 1, only the terminal faces  32 S of the outer terminals  32  are exposed to the outside, and outer electrodes  70  consisting of solders are formed on the exposed faces. Thereby, a BGA (Ball Grid Array) type semiconductor device is formed. When the resin-sealed semiconductor device  1  is mounted on the circuit board, the outer terminals  32  can be electrically connected to an outside circuit by melting and solidifying the outer electrodes  70 .  
         [0043]    In the resin-sealed semiconductor device  1 , at least the terminal faces  31 S of the inner terminals  31  are made flat through coining, and the silver plating layers  60  are formed on the terminal faces  31 S.  
         [0044]    Furthermore, in the resin-sealed semiconductor device  1 , the terminals  11  of the semiconductor element  10  are arranged along a center line  10   c  between a pair of sides  10   a  of the terminal mounted face of the semiconductor element  10  (refer to FIGS. 1 and 2). On the other hand, the inner terminals  31  of the circuit portions  30 A are arranged along the center line  10   c  to sandwich the center line  10   c  from opposite sides. As aforementioned, the terminal mounted face of the semiconductor element  10  is laid via the insulating layers  20  on the surfaces (semiconductor element mounted faces)  30 S of the circuit portions  30 A, and this structure is called LOC (Lead On Chip). Moreover, in the resin-sealed semiconductor device  1 , a resin sealed region is substantially adapted to a size of the semiconductor element  10 , and the structure is called CSP (Chip Size Package) in which the outer configuration dimension of the semiconductor device is substantially the same as that of the semiconductor element.  
         [0045]    In the embodiment shown in FIG. 1, the insulating layer  20  is provided with adhesive layers  25  on opposite faces of an electrically insulating base film  23 , or a marketed dia-touch agent can be used. For example, an adhesive double coated tape like UX1W (manufactured by Kabushiki Kaisha Tomoegawa Seishisho) with RXF layers (adhesives manufactured by Kabushiki Kaisha Tomoegawa Seishisho) formed on opposite faces of UPLEX (electrically insulating base film manufactured by Ube Kosan Kabushiki Kaisha) can be used. Additionally, a 42 alloy (Fe alloy containing 41% of Ni), a copper alloy or the like is used as a material of the circuit portion  30 A.  
         [0046]    [0046]FIG. 5 is a diagrammatic view showing a constitution of another embodiment of the resin-sealed semiconductor device according to the invention. As shown in FIG. 5, in a resin-sealed semiconductor device  2  of the invention, different from the aforementioned resin-sealed semiconductor device  1 , the outer electrodes  70  are not formed on the exposed faces (terminal faces  32 S) of the outer terminals  32 .  
         [0047]    [0047]FIG. 6 is a diagrammatic view showing a constitution of another embodiment of the resin-sealed semiconductor device according to the invention. In FIG. 6, a resin-sealed semiconductor device  3  of the invention is an LOC (Lead On Chip) type semiconductor device which is different from the aforementioned resin-sealed semiconductor device  1  in that the semiconductor element  10  is mounted on the inner terminals  31  subjected to upsetting. By applying the upsetting to the inner terminals  31 , a distance between the terminal faces  31 S of the inner terminals  31  and an outer-terminal mounted face  50 S of the sealing member  50  is increased. Therefore, a sufficient distance “D” can be obtained between the wires  40  connecting the terminals  11  of the semiconductor element  10  to the terminal faces  31 S of the inner terminals  31  and the outer-electrode mounted face  50 S of the sealing member  50 , the wires  40  can be sealed more firmly. In the resin-sealed semiconductor device  3 , the exposed faces (terminal faces  32 S) of the outer terminals  32  are not provided with the outer electrodes  70  in the same manner as the resin-sealed semiconductor device  2 .  
         [0048]    Additionally, the number of terminals, the arrangement of the terminals and the like in the resin-sealed semiconductor device  1 ,  2  or  3  are shown by way of illustration, and it is natural that the invention is not restricted to the embodiments. For example, by two-dimensionally arranging the terminals  11  along four sides of the semiconductor element  10  and by arranging the circuit portions  30 A along a periphery of the semiconductor element  10 , more pins can further be mounted on the resin-sealed semiconductor device  1 ,  2  or  3 .  
         [0049]    [0049]FIG. 7 is a diagrammatic view showing another embodiment of the resin-sealed semiconductor device according to the invention, and FIG. 8 is a view of the resin-sealed semiconductor device shown in FIG. 7 as seen from an outer-terminal side. FIG. 9 is a perspective view clearly showing the outer-terminal side and side faces of the resin-sealed semiconductor device shown in FIG. 7. Furthermore, FIG. 10 is an enlarged perspective view of one circuit portion of the resin-sealed semiconductor device shown in FIG. 7. Additionally, FIG. 7 is a vertical sectional view taken along a one-dot chain line II-II of FIG. 8. Moreover, to facilitate the understanding of a positional relationship of the circuit portion and a semiconductor element in FIG. 8, the circuit portion is shown by a two-dot chain line while a semiconductor element region is shown by a chain line.  
         [0050]    In a resin-sealed semiconductor device  101  shown in FIGS.  7  to  10 , plural circuit portions  130 A are arranged two-dimensionally substantially in a plane and electrically independent of one another. The circuit portion  130 A has a lead  133  for integrally interconnecting an inner terminal  131  and an outer terminal  132 . Furthermore, since the resin-sealed semiconductor device  101  is manufactured by using a circuit member described later, a connection lead  134  remains extending from the outer terminal  132  toward the side face of the resin-sealed semiconductor device  101 . A surface  130 S of the circuit portion  130 A is a semiconductor element mounted face on which the inner terminal  131 , the lead  133  and the outer terminal  132  form one plane. Additionally, the inner terminal  131  and the lead  133  are thinner than the outer terminal  132 , a surface  130 S of the circuit portion  130 A is provided with a terminal face  131 S of the inner terminal  131 , and a back surface  130 B of the circuit portion  130 A is provided with a terminal face  132 S of the outer terminal  132 . Therefore, on the back surface  130 B of the circuit portion  130 A, the terminal face  132 S of the outer terminal  132  is protruded in a convex configuration from the back surface. Additionally, a silver plating layer  160  is formed on the terminal face  131 S of the inner terminal  131 .  
         [0051]    For a semiconductor element  110 , a face of the semiconductor element  110  opposite to the side of terminals  111  is mounted via an insulating layer  120  on the semiconductor element mounted faces  130 S of the circuit portions  130 A. The terminals  111  of the semiconductor element  110  are electrically connected with wires  140  to the terminal faces  131 S (the silver plating layers  160 ) of the inner terminals  131 .  
         [0052]    The semiconductor element  110 , the circuit portions  130 A and the wires  140  are sealed with a sealing member  150  in such a manner that the outer terminals  132  are partially exposed to the outside. For the sealing member  150 , a known sealing resin material for use in the resin-sealed semiconductor device can be used. In the embodiment shown in FIG. 7, only the terminal faces  132 S of the outer terminals  132  are exposed to the outside, and outer electrodes  170  consisting of solders are formed on the exposed faces. Thereby, a BGA (Ball Grid Array) type semiconductor device is formed. When the resin-sealed semiconductor device  101  is mounted on the circuit board, the outer terminals  132  can be electrically connected to an outside circuit by melting and solidifying the outer electrodes  170 .  
         [0053]    Moreover, in the resin-sealed semiconductor device  101 , the inner terminals  131  are arranged along each side (four sides) of the semiconductor element  110  and outside a semiconductor element region (region surrounded with a chain line in FIG. 8). As aforementioned, the face of the semiconductor element  110  opposite to the terminal mounted face is laid via the insulating layer  120  on the surfaces (semiconductor element mounted faces)  130 S of the circuit portions  130 A, and this structure is called COL (Chip On Lead). Moreover, in the resin-sealed semiconductor device  101 , a resin sealed region is substantially adapted to a size of the semiconductor element  110 , and the structure is called CSP (Chip Size Package) in which the outer configuration dimension of the semiconductor device is substantially the same as that of the semiconductor element.  
         [0054]    In the embodiment shown in FIG. 7, the insulating layer  120  is provided with adhesive layers  125  on opposite faces of an electrically insulating base film  123 , or a marketed dia-touch agent can be used. For example, an adhesive double coated tape like UX1W (manufactured by Kabushiki Kaisha Tomoegawa Seishisho) with RXF layers (adhesives manufactured by Kabushiki Kaisha Tomoegawa Seishisho) formed on opposite faces of UPLEX (electrically insulating base film manufactured by Ube Kosan Kabushiki Kaisha) can be used. Additionally, a 42 alloy (Fe alloy containing 41% of Ni), a copper alloy or the like is used as a material of the circuit portion  130 A.  
         [0055]    [0055]FIG. 11 is a diagrammatic view showing another embodiment of the resin-sealed semiconductor device according to the invention. In FIG. 11, a resin-sealed semiconductor device  102  of the invention is constituted by providing the circuit portions  130 A of the aforementioned resin-sealed semiconductor device  101  with semiconductor mounting leads  135 . Specifically, the semiconductor mounting leads  135  are integrally extended from the outer terminals  132  of the circuit portions  130 A toward the inside of the resin-sealed semiconductor device  102 . The semiconductor mounting lead  135  is thinner than the outer terminal  132 , and its surface  135 S forms the same plane as the surface (semiconductor element mounted face)  130 S of the circuit portion  130 A. By provision of the semiconductor mounting leads  135 , the semiconductor element  110  can be fixed and mounted onto the circuit portions  130 A more firmly.  
         [0056]    [0056]FIG. 12 is a diagrammatic view showing a constitution of another embodiment of the resin-sealed semiconductor device according to the invention. As shown in FIG. 12, in a resin-sealed semiconductor device  103  of the invention, different from the aforementioned resin-sealed semiconductor device  101 , the outer electrodes  170  are not formed on the exposed faces (terminal faces  132 S) of the outer terminals  132 , and portions to be connected to a printed board are formed of solder paste or the like.  
         [0057]    Additionally, the number of terminals, the arrangement of the terminals and the like in the resin-sealed semiconductor device  101 ,  102  or  103  are shown by way of illustration, and it is natural that the invention is not restricted to the embodiments.  
         [0058]    Circuit Member  
         [0059]    A circuit member of the invention will be described.  
         [0060]    [0060]FIG. 13 is a plan view showing an embodiment of a circuit member of the invention, and FIG. 14 is an enlarged perspective view of a section surrounded with a chain line III of the circuit member shown in FIG. 13.  
         [0061]    In FIGS. 13 and 14, a circuit member  30  of the invention is a circuit member which can be used in manufacture of the resin-sealed semiconductor device  1 ,  2  or  3  of the invention, and is provided with an outer frame member  36  and plural circuit portions  30 A mutually independently extended from the outer frame member  36  via connection leads  34 . A region surrounded with a one-dot chain line IV of FIG. 13 is a region used with a resin sealed therein when the resin-sealed semiconductor device of the invention is manufactured, and a region outside the one-dot chain line IV is finally separated and removed.  
         [0062]    An outer configuration and an inner opening configuration of the outer frame member  36  are rectangular. The connection leads  34  are extended from a pair of opposite sides defining an inner opening of the outer frame member  36  into the same plane. The outer frame member  36  usually has the same thickness as the conductive board which is a material of the circuit member  30 . Furthermore, as aforementioned, since the region outside the one-dot chain line IV of FIG. 13 is finally separated and removed after resin sealing, as shown in FIG. 1, the connection leads  34  partially remain inside the resin-sealed semiconductor device  1 .  
         [0063]    The circuit portion  30 A is formed by integrally interconnecting the outer terminal  32 , the lead  33  and the inner terminal  31  in this sequence on a tip end of the connection lead  34 . The inner terminal  31  and the lead  33  are thinner than the outer terminal  32 . The thickness of the outer terminal  32  is set to the same thickness as that of the conductive board being the material of the circuit member  30 . Additionally, the back surface  30 B of the circuit portion  30 A is provided with the terminal face  31 S of the inner terminal  31  and the terminal face  32 S of the outer terminal  32 . Moreover, the surface  30 S of the circuit portion  30 A is a semiconductor element mounted face on which the inner terminal  31 , the lead  33  and the outer terminal  32  form one plane. The semiconductor element mounted face is usually constituted by using a surface of the conductive board or material of the circuit member  30  as it is. Therefore, on the back surface  30 B of the circuit portion  30 A, the terminal face  32 S of the outer terminal  32  is protruded in a convex configuration from the back surface. In the embodiment shown in FIG. 14, the terminal face  31 S of the inner terminal  31  is made flat through coining.  
         [0064]    A 42 alloy (Fe alloy containing 41% of Ni), a copper, a copper alloy or the like is used as a material of the circuit member  30 .  
         [0065]    Additionally, in a case of a circuit member for use in the resin-sealed semiconductor device  3  of the invention, the inner terminals  31  are subjected to upsetting.  
         [0066]    Furthermore, the number of terminals, the arrangement of the terminals and the like in the aforementioned circuit member are shown by way of illustration, and it is natural that the invention is not restricted to the embodiment.  
         [0067]    [0067]FIG. 15 is a plan view showing another embodiment of the circuit member of the invention, and FIG. 16 is an enlarged perspective view of a section surrounded with a chain line V of the circuit member shown in FIG. 15.  
         [0068]    In FIGS. 15 and 16, a circuit member  130  of the invention is a circuit member which can be used in manufacture of the resin-sealed semiconductor device  101 ,  102  or  103  of the invention, and is provided with an outer frame member  136  and plural circuit portions  130 A mutually independently extended from the outer frame member  136  via connection leads  134 . A region surrounded with a one-dot chain line VI of FIG. 15 is a region used with a resin sealed therein when the resin-sealed semiconductor device of the invention is manufactured, and a region outside the one-dot chain line VI is finally separated and removed.  
         [0069]    An outer configuration and an inner opening configuration of the outer frame member  136  are rectangular. The connection leads  134  are extended from a pair of opposite sides defining an inner opening of the outer frame member  136  into the same plane. The outer frame member  136  usually has the same thickness as the conductive board being a material of the circuit member  130 . Furthermore, as aforementioned, since the region outside the one-dot chain line VI of FIG. 15 is finally separated and removed after resin sealing, as shown in FIG. 7, the connection leads  134  partially remain inside the resin-sealed semiconductor device  101 .  
         [0070]    The circuit portion  130 A is formed by integrally interconnecting the inner terminal  131 , the lead  133  and the outer terminal  132  in this sequence on a tip end of the connection lead  134 . The inner terminal  131  and the lead  133  are thinner than the outer terminal  132 . The thickness of the outer terminal  132  is set to the same thickness as that of the conductive board being the material of the circuit member  130 . Additionally, the surface  130 S of the circuit portion  130 A is provided with the terminal face  131 S of the inner terminal  131  while the back surface  130 B is provided with the terminal face  132 S of the outer terminal  132 . Moreover, the surface  130 S of the circuit portion  130 A is a semiconductor element mounted face on which the inner terminal  131 , the lead  133  and the outer terminal  132  form one plane. The semiconductor element mounted face is usually constituted by using a surface of the conductive board or material of the circuit member  130  as it is. Therefore, on the back surface  130 B of the circuit portion  130 A, the terminal face  132 S-of the outer terminal  132  is protruded in a convex configuration from the back surface.  
         [0071]    A 42 alloy (Fe alloy containing 41% of Ni), a copper, a copper alloy or the like is used as a material of the circuit member  130 .  
         [0072]    Furthermore, the number of terminals, the arrangement of the terminals and the like in the aforementioned circuit member are shown by way of illustration, and it is natural that the invention is not restricted to the embodiment.  
         [0073]    Method of Manufacturing Circuit Member  
         [0074]    A method of manufacturing the circuit member of the invention will be described.  
         [0075]    The method of manufacturing the circuit member of the invention is described by using a case where the circuit member  30  shown in FIGS. 13 and 14 is manufactured.  
         [0076]    [0076]FIG. 17 is a process diagram showing an embodiment of the method of manufacturing the circuit member according to the invention. Each process is shown in a cross section taken along a one-dot chain line VII-VII shown in FIG. 13.  
         [0077]    First, a conductive board  80  with a thickness of about 100 to 250 μm formed of a 42 alloy (Fe alloy containing 41% of Ni) or the like is prepared as a material of the circuit member. After well cleaning the conductive board  80  by degreasing opposite faces  80 S or otherwise (FIG. 17A), a photosensitive resist is applied to the opposite faces  80 S and dried to form resist layers  82  (FIG. 17B). As the photosensitive resist, a known conventional resist can be used and, for example, a casein resist using a photosensitive material of potassium bichromate, a negative liquefied resist (PMER resist) manufactured by Tokyo Ouka Kogyo Kabushiki Kaisha or the like can be used.  
         [0078]    Subsequently, after only predetermined sections of the resist layers  82  are exposed to light via predetermined pattern masks, developing is performed to form resist patterns  82 A on one face of the conductive board  80  and resist patterns  82 B on the other face (FIG. 17C). In a region on which the inner terminals, the leads and the connection leads are to be formed, one face of the conductive board  80  is not covered with the resist patterns  82 A.  
         [0079]    Subsequently, by using the resist patterns  82 A and  82 B as films resistant to etching agents, the conductive board  80  is etched with an etching liquid. The etching proceeds as shown in FIG. 17D, and is completed as shown in FIG. 17E. Since in the region with the inner terminals, the leads and the connection leads to be formed thereon one face of the conductive board  80  is not covered with the resist patterns  82 A, the etching proceeds only from one side. This is called a half etching in the invention. Through the half etching, thin-gage portions  83  are formed, and sections in which no resist pattern  82 A or  82 B is present are melted and removed.  
         [0080]    For the etching liquid, an aqueous solution of ferric chloride is usually used to spray and etch the opposite faces of the conductive board  80 . By adjusting an etching quantity in the half etching process, a thickness of each thin-gage portion  83  can be regulated.  
         [0081]    Subsequently, by peeling and removing the resist patterns  82 A and  82 B, the inner terminals  31 , the leads  33  and the connection leads  34  are formed thinner than the material of the conductive board  80 , and the outer terminals  32  and the outer frame member  36  are formed as thick as the material of the conductive board  80  (FIG. 17F). A portion between adjoining inner terminals  31  is separated because the etching proceeds from the opposite faces. The material face  80 S of the conductive board  80  is left as one face (surface) of the inner terminal  31 , the lead  33  or the connection lead  34 . Opposite faces of the outer terminal  32  or the outer frame member  36  are formed by the material faces  80 S of the conductive board  80 .  
         [0082]    Subsequently, by coining a terminal-face forming side  31 A of the inner terminal  31 , the flat terminal face  31 S is formed to obtain the circuit member  30  of the invention (FIG. 17G).  
         [0083]    Additionally, for reasons of productivity, when etching is performed, plural faces are processed as aforementioned.  
         [0084]    Moreover, for the circuit member to be used in the resin-sealed semiconductor device  3  of the invention, the inner terminal  31  is subjected to upsetting by using a predetermined metal mold. The upsetting may be performed after formation of the silver plating layer  60  described later.  
         [0085]    A method of manufacturing the resin-sealed semiconductor device  1  shown in FIGS.  1  to  4  by using the circuit member  30  manufactured as aforementioned will be described with reference to FIG. 18.  
         [0086]    First, by performing the processes shown in FIG. 17, the circuit member  30  is prepared (FIG. 18A). Subsequently, after cleaning the circuit member  30 , the silver plating layers  60  are formed on the terminal faces  31 S of the inner terminals  31  (FIG. 18B). Additionally, instead of the silver plating layers  60 , gold plating layers, palladium plating layers or the like may be formed.  
         [0087]    Subsequently, the face on the side of the terminals  11  of the semiconductor element  10  is fixed via the insulating layers  20  onto the material face (semiconductor element mounted face) of the circuit member  30 , and the semiconductor element  10  is mounted thereon. Subsequently, the terminals  11  of the mounted semiconductor element  10  and the silver plating layers  60  of the inner terminals  31  of the circuit member  30  are electrically connected with the wires  40  (FIG. 18C).  
         [0088]    Subsequently, the circuit portions  30 A, the semiconductor element  10  and the wires  40  are sealed with the sealing member  50  in such a manner that portions (terminal faces  32 S) of the outer terminals  32  are exposed to the outside (FIG. 18D).  
         [0089]    After sealing with the sealing member  50 , a solder plating or another surface treatment agent is applied to the terminal faces  32 S exposed to the outside of the outer terminals, then the outer electrodes  70  consisting of solder balls are formed (FIG. 18E).  
         [0090]    Subsequently, the connection leads  34  of the circuit member  30  are cut to remove the outer frame member  36 , thereby obtaining the resin-sealed semiconductor device  1  of the invention (FIG. 18F).  
         [0091]    Additionally, the outer electrode of solder can be formed by applying a solder paste through screen printing, reflowing or the like, and it is sufficient only to obtain a necessary amount of solder for connecting the circuit board and the resin-sealed semiconductor device.  
         [0092]    The method of manufacturing the circuit member of the invention will be described by using a case where the circuit member  130  shown in FIGS. 15 and 16 is manufactured.  
         [0093]    [0093]FIG. 19 is a process diagram showing another embodiment of the method of manufacturing the circuit member according to the invention. Each process is shown in a cross section taken along a one-dot chain line VIII-VIII shown in FIG. 15.  
         [0094]    First, a conductive board  180  with a thickness of about 100 to 250 μm formed of a 42 alloy (Fe alloy containing 41% of Ni) or the like is prepared as a material of the circuit member. After well cleaning the conductive board  180  by degreasing opposite faces  180 S or otherwise (FIG. 19A), a photosensitive resist is applied to the opposite faces  180 S and dried to form resist layers  182  (FIG. 19B). As the photosensitive resist, a known conventional resist can be used and, for example, a casein resist using a photosensitive material of potassium bichromate, a negative liquefied resist (PMER resist) manufactured by Tokyo Ouka Kogyo Kabushiki Kaisha or the like can be used.  
         [0095]    Subsequently, after only predetermined sections of the resist layers  182  are exposed to light via predetermined pattern masks, developing is performed to form resist patterns  182 A on one face of the conductive board  180  and resist patterns  182 B on the other face (FIG. 19C). In a region on which the inner terminals, the leads and the connection leads are to be formed, one face of the conductive board  180  is not covered with the resist patterns  182 A.  
         [0096]    Subsequently, by using the resist patterns  182 A and  182 B as films resistant to etching agents, the conductive board  180  is etched with an etching liquid. The etching proceeds as shown in FIG. 19D, and is completed as shown in FIG. 19E. Since in the region with the inner terminals, the leads and the connection leads to be formed thereon one face of the conductive board  180  is not covered with the resist patterns  182 A, the etching proceeds only from one side to perform a half etching. Through the half etching, thin-gage portions  183  are formed, and sections in which no resist pattern  182 A or  182 B is present are melted and removed.  
         [0097]    For the etching liquid, an aqueous solution of ferric chloride is usually used to spray and etch the opposite faces of the conductive board  180 . By adjusting an etching quantity in the half etching process, a thickness of each thin-gage portion  183  can be regulated.  
         [0098]    Subsequently, by peeling and removing the resist patterns  182 A and  182 B, the inner terminals  131 , the leads  133  and the connection leads  134  are formed thinner than the material of the conductive board  180 , and the outer terminals  132  and the outer frame members  136  are formed as thick as the material of the conductive board  180 , thereby obtaining the circuit member  130  (FIG. 19F). A portion between adjoining outer terminals  132  is separated because the etching proceeds from the opposite faces. The material face  180 S of the conductive board  180  is left as one face (surface) of the inner terminal  131 , the lead  133  or the connection lead  134 . Opposite faces of the outer terminal  132  or the outer frame member  136  are formed by the material faces  180 S of the conductive board  180 .  
         [0099]    Additionally, for reasons of productivity, when etching is performed, plural faces are processed as aforementioned.  
         [0100]    A method of manufacturing the resin-sealed semiconductor device  101  shown in FIGS.  7  to  10  by using the circuit member  130  manufactured as aforementioned will be described with reference to FIG. 20.  
         [0101]    First, by performing the processes shown in FIG. 19, the circuit member  130  is prepared (FIG. 20A). Subsequently, after cleaning the circuit member  130 , the silver plating layers  160  are formed on the terminal faces  131 S of the inner terminals  131  (FIG. 20B). Additionally, instead of the silver plating layers  160 , gold plating layers, palladium plating layers or the like may be formed.  
         [0102]    Subsequently, the face opposite to the side of the terminals  111  of the semiconductor element  110  is fixed via the insulating layer  120  onto the material face (semiconductor element mounted face) or the terminal faces  131 S of the inner terminals  131  inside a region where the inner terminals  131  of the circuit member  130  are formed, and the semiconductor element  110  is mounted thereon. Subsequently, the terminals  111  of the mounted semiconductor element  110  and the silver plating layers  160  of the inner terminals  131  of the circuit member  130  are electrically connected with the wires  140  (FIG. 20C).  
         [0103]    Subsequently, the circuit portions  130 A, the semiconductor element  110  and the wires  140  are sealed with the sealing member  150  in such a manner that portions (terminal faces  132 S) of the outer terminals  132  are exposed to the outside (FIG. 20D).  
         [0104]    After sealing with the sealing member  150 , a solder plating or another surface treatment agent is applied to the terminal faces  132 S exposed to the outside of the outer terminals, then the outer electrodes  170  consisting of solder balls are formed (FIG. 20E).  
         [0105]    Subsequently, the connection leads  134  of the circuit member  130  are cut to remove the outer frame member  136 , thereby obtaining the resin-sealed semiconductor device  101  of the invention (FIG. 20F).  
         [0106]    Additionally, the outer electrode of solder can be formed by applying a solder paste through screen printing, reflowing or the like, and it is sufficient only to obtain a necessary amount of solder for connecting the circuit board and the resin-sealed semiconductor device.