Abstract:
A method of making tungsten plug of integrated circuit is disclosed. The present invention is structured to deposit W metal by CVD onto the wafer which has Ti/TiN sputtered on as its top layer by employing quartz clamp rings of different sizes in two CVD chambers. The method can eliminate the Volcano phenomena in Ti, TiN or W metals and prevent peeling.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates to a method of making tungsten plugs in integrated circuit devices by a chemical vapor deposition process, and more particularly, to an improvement in the method which eliminates the volcano phenomena. The method of the present invention dramatically increases the efficiency of the method by producing fewer defective devices exhibiting the undesirable volcano phenomena.  
           [0003]    2. Description of the Prior Art  
           [0004]    It is widely known that Ti, W, TiN or Al alloys are used for metal interconnection in USLI technology. For example, the double level metal interconnection process used commercially today employs a Ti/TIN/W tri-layer structure to form the first level metal interconnection, in which the Ti is the bottom layer that makes electrical contact with the source and drain electrodes of the Field Effect Transistor devices.  
           [0005]    Conventional methods of making the first level metal interconnection in the double level metal interconnection process include the following steps:  
           [0006]    (1) Depositing a SiO 2  insulation layer on top of the contact hole and devices by chemical vapor deposition (CVD), then depositing a layer of BPSG (Boronphospliosilicate Glass) onto the SiO2 layer for surface planarization by employing CVD again;  
           [0007]    (2) Forming contact holes as shown in FIGS. 1 and 2;  
           [0008]    (3) Making ion implantation through the contact holes and forming the devices;  
           [0009]    (4) Sputter depositing a barrier metal layer made up of Ti and TiN, in which the Ti metal is underneath the TiN; the barrier layer crosses the contact holes mentioned above;  
           [0010]    (5) Depositing W metal to form the W-plug in the contact hole by plasma anisotropic etchback technique.  
           [0011]    Using these methods, the Ti layer is about 300 angstroms thick and the TiN is about 1500 angstroms thick. The following reactions occur to form W metal by CVD: 
           WF 6 ( g )+SiH4( g )→W( s )+SiF 4 ( g )+H 2 ( g ) 
           WF 6 ( g )+H 2 ( g )→W( s )+HF( g ) 
           [0012]    WF 6  is reacted with SiH4 in the first step of the process. Thereafter hydrogen gas (H 2 (g)) is reacted with WF 6  which produces tungsten (W).  
           [0013]    However, the Ti/TiN layer made in step (4) has a very poor step coverage capability. Therefore the Ti/TiN layer can be very thin near the top and bottom of the sidewalls of the contact holes, as shown in FIG. 3. As a consequence of this phenomenon, the WF 6  gas used for W metal deposition will penetrate the TiN layer and react with the Ti metal underneath to produce the evaporative TiF 4 , which will result in an explosive phenomena near the contact hole. This is called the volcano phenomena. The reaction of Ti with WF 6  is as follows: 
           Ti( s )+WF 6 ( g )→W( s )+TiF 4 ( g ) 
           [0014]    This volcano phenomena can easily cause peeling of the Ti, TiN or W layers which makes the devices defective and thereby reduces the yield of acceptable devices produced by the process.  
           [0015]    In addition, the deposited tungsten layer will not adhere to the surface of SiO 2  or BPSG. The TiN layer is deposited before the tungsten layer is formed as a barrier layer to avoid peeling. Since the TiN layer is deposited by sputtering, the volcano phenomenon is even more likely to happen near the edge of the silicon wafer. Because the wafer was held down by a quartz clamp ring inside the reaction chamber, some BPSG will be left near the edge of the wafer. This makes the tungsten nucleation layer insufficient near the edge and thus reduces the reaction speed for the WF 6  gas to produce the tungsten (W) metal. The overabundant WF 6  gas facilitates peeling of the tungsten (W) layer resulting in the production of defective devices which reduces the overall yield of acceptable devices manufactured by the process.  
           [0016]    U.S. Pat. No. 5,489,552 the entire disclosure of which is herein incorporated by reference, relates to a multiple layer tungsten deposition process and discusses the volcano phoneme. U.S. Pat. No. 5,436,200, the entire disclosure of which is herein incorporated by reference, describes a blanket tungsten deposition process utilizing a ceramic ring.  
         SUMMARY OF THE INVENTION  
         [0017]    In view of the foregoing, the primary object of the present invention is to provide a high yield, low cost and highly efficient manufacturing process for making IC metal interconnections and avoiding the volcano phenomena.  
           [0018]    This invention uses two CVD (chemical vapor deposition) chambers with clamp rings of different sizes to control the deposition area and thickness. This approach ensures that the bulk deposition of tungsten (W) is on the nucleation layer. Thus, the penetrating of excessive WF 6  gas into TiN barrier layer is avoided. This prevents the volcano phenomena from happening.  
           [0019]    The process of the present invention comprises the following steps:  
           [0020]    (1) Depositing a SiO 2  insulation layer ( 25 ) on top of a substrate ( 20 ) by CVD; and then depositing a layer of BPSG ( 30 ) onto the SiO 2  layer ( 20 ) for surface planarization by again employing CVD;  
           [0021]    (2) Partially etching the SiO 2  insulation layer ( 25 ) and the BPSG layer ( 30 ) to form contact holes on the substrate ( 20 );  
           [0022]    (3) Making ion implantation through the contact hole and forming the devices;  
           [0023]    (4) Sputter depositing a barrier metal layer made up of Ti followed by rapid thermal nitridation to form a TiN layer in which the Ti metal is underneath the TiN layer which is bilayer ( 40 );  
           [0024]    (5) Depositing tungsten (W) metal in two CVD chambers with different quartz clamp rings to control the area and thickness of the tungsten nucleation layer ( 50 ) and bulk deposition area of the tungsten (W) layer ( 60 ) in order to ensure the bulk deposition is onto the nucleation layer;  
           [0025]    (6) Forming the tungsten-plug in the contact hole by plasma anisotropic etch back technique;  
           [0026]    (7) Sputtering on a Al/Si/Cu layer and pattern metal lines by conventional technology.  
           [0027]    The rapid thermal nitridation of step (4) may take place at, for example, 760° C. for 30 seconds. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    The accompanying drawings further describe the prior art and the invention.  
         [0029]    [0029]FIG. 1-3 show the cross-sectional representation of the conventional process for making the first level metal interconnection.  
         [0030]    [0030]FIG. 1 shows the cross-sectional representation of the silicon wafer after SiO 2  deposition. The SiO 2  is used as an insulation layer.  
         [0031]    [0031]FIG. 2 shows the cross-sectional representation after etching unwanted SiO 2  layer to make contact holes. The metal layer will form electrical contact to the devices.  
         [0032]    [0032]FIG. 3 shows the cross-sectional representation of Ti and TiN deposition by sputtering. These metal layers contact the devices on the silicon wafer through the contact holes in the SiO 2  layer.  
         [0033]    [0033]FIG. 4 shows the cross-sectional representation of the process of the invention for making the first level metal interconnection.  
         [0034]    [0034]FIGS. 5A, 5B, and  5 C show the top view and cross-sectional view of the three quartz ( 1 ,  2 ,  3 ) clamp rings of different size used in the CVD process in this invention.  
         [0035]    [0035]FIG. 6 shows the system of operation procedure with the CVD chamber A and chamber B used in this invention for the deposition of tungsten (W) metal. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0036]    In the conventional method for making IC, a field contact hole is formed to insulate the active area from the silicon substrate, then the FET is made which contains the gate dielectric, the gate electrode, spacer and source/drain region. Thereafter the metal interconnection process is widely used today and has been described in the field of this invention mentioned above.  
         [0037]    This invention improves the process for making the first level metallization in the double level metal interconnection process, to prevent the volcano phenomena and peeling of the metal layer. FIG. 4, depicts the cross-sectional view of the device made by the process of the present invention. The process comprises the following steps:  
         [0038]    (1) Depositing a SiO 2  insulation layer ( 25 ) on top of a substrate ( 20 ) by CVD; and then depositing a layer of BPSG ( 30 ) onto the SiO 2  layer ( 20 ) for surface planarization by again employing CVD;  
         [0039]    (2) Partially etching the SiO 2  insulation layer ( 25 ) and the BPSG layer ( 30 ) to form contact holes on the substrate ( 20 );  
         [0040]    (3) Making ion implantation through the contact hole and forming the devices;  
         [0041]    (4) Sputter depositing a barrier metal layer made up of Ti followed by rapid thermal nitridation to form a TiN layer in which the Ti metal is underneath the TiN layer which is bilayer ( 40 );  
         [0042]    (5) Depositing tungsten (W) metal in two CVD chambers with different quartz clamp rings to control the area and thickness of the tungsten nucleation layer ( 50 ) and bulk deposition area of the tungsten (W) layer ( 60 ) in order to ensure the bulk deposition is onto the nucleation layer;  
         [0043]    (6) Forming the tungsten-plug in the contact hole by plasma anisotropic etch back technique;  
         [0044]    (7) Sputtering on a Al/Si/Cu layer and pattern metal lines by conventional technology.  
         [0045]    The rapid thermal nitridation of step (4) may take place at, for example, 760° C. for 30 seconds.  
         [0046]    Referring now more particularly to FIG. 5A for further explaining the critical step (5) in this process. There is shown a wafer  10  in step (4) and it is held down by a quartz clamp ring  1  of 2 mm width. This wafer now has BPSG  30  as its top layer. A Ti/TiN bilayer  40  is then sputtered onto the wafer  10 , with the result that near the edge of the wafer  10  is a 2 mm wide band of the BPSG layer not covered with Ti/TiN  40 , but only the BPSG  30  film from the previous step. Thereafter referring now to FIG. 5B, tungsten metal is deposited by the following two steps: First, a tungsten nucleation layer  50  is formed on the wafer  10  using CVD in chamber A  90  (referring FIG. 6) by reducing the WF 6  by SiH 4 : 
         WF 6 ( g )+SiH 4 ( g )→4W( s )+SiF4( g )+H 2 ( g ). 
         [0047]    The reaction pressure is about between 4.5 to 30 torr and reaction temperature is between 445 to 475° C. by Ar with 1000 to 3000 Sccm, N 2  with 300 to 500 Sccm, H 2  with 1000 to 1500 Sccm, SiH 4  with 5 to 10 Sccm and WF 6  with 10 to 20 Sccm.  
         [0048]    This nucleation layer  50  is about between 500 to 800 angstroms thick. In this process, the silicon wafer  10  is held down by a quartz clamp ring  2  of 3 mm width, thus the ring  2  covers the 2 mm wide BPSG  30  layer and an additional 1 mm band of the Ti/TiN bilayer  40 . No tungsten metal is deposited onto the BPSG  30  surface and no peeling will occur. Moreover, separating the formation of the nucleation layer  50  and the bulk deposition of tungsten into two CVD chambers enables better control of the nucleation layer thickness, and thus better protection for the Ti/TiN structure underneath.  
         [0049]    After this step, referring now to FIG. 5C, the wafer  10  is transferred into CVD chamber B  95  (referring FIG. 6) from chamber A  90  (referring to FIG. 6) and held by a quartz clamp ring  3  which is about 5 mm wide, then tungsten metal  60  is bulk deposited onto the tungsten nucleation layer  50  on the wafer  10  with between 7500 to 8000° by reducing WF 6  with H 2  employing CVD and the following reaction: 
         WF 6 ( g )+H 2 ( g )→W( s )+HF( g ) 
         [0050]    The reaction pressure is about between 70 to 90 torr and reaction temperature is between 445 to 475° C. by Ar with 2000 to 4000 Sccm, N 2  with 300 to 500 Sccm, H 2  with 500 to 1500 Sccm and WF 6  with 10 to 20 Sccm.  
         [0051]    The tungsten-plug in the contact hole is formed by plasma anisotropic etchback technique.  
         [0052]    This is followed by sputtering an Ai/Si/Cu layer and pattern metal lines by etching out unwanted Ti, TiN and Al/Si/Cu employing conventional etching and lithography technology.  
         [0053]    The tungsten nucleation layer  50  made in chamber A  90  (referring FIG. 6) can be used as a passivation layer to prevent the WF 6  penetrating the TiN layer and reacting with Ti to form TiF 4  during the bulk deposition of tungsten in chamber B  95  (referring to FIG. 6). By depositing tungsten using two different quartz claim rings and two chambers facilitates the elimination of the volcano phenomena as mentioned above. Therefore, the overall yield of the process is increased by producing fewer devices with defects and the particle contamination of wafer will be avoided also.  
         [0054]    [0054]FIG. 6 shows the system for the performing the process of the invention. First, the operator loads cassettes filled with wafers into the cassette indexer  75  which has two stages. Then the robot  85 , located inside the loadlock chamber  88 , moves the wafers one at a time from the cassette to slots in the storage elevator  80 , which is also located inside the loadlock chamber  88 . After the loadlock chamber  88  is pumped down to a low pressure, the robot  85  moves a wafer into chamber a  90  for depositing the nucleation layer, and then robot  85  transfers the nucleated wafer to chamber B 95  for bulk deposition. When processing of the wafer is completed, the wafer transfer sequence is reversed and the wafer is moved out of the chamber B  95  to the cassette by through the storage elevator  80 . Finish the operator can remove the cassette with wafers from the system.