Abstract:
A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    This invention relates in general to valves and to semiconductor electromechanical devices, and in particular, to micromachined components formed from wafers of a semiconductor material, such as silicon, bonded together. 
         [0002]    MEMS (micro electro mechanical systems) are a class of systems that are physically small, having features or clearances with sizes in the micrometer range or smaller (i.e., smaller than about 10 microns; as is well known, “micron” is another term for micrometer, a unit of length equal to 0.001 millimeter). These systems have both electrical and mechanical components. The term “micro machining” is commonly understood to mean the production of three-dimensional structures and moving parts of MEMS devices. MEMS originally used modified integrated circuit (e.g., computer chip) fabrication techniques (such as chemical etching) and materials (such as silicon semiconductor material) to micro machine these very small mechanical devices. Today there are many more micro machining techniques and materials available. The term “MEMS device” as may be used in this application means a device that includes a micro machined component having features or clearances with sizes in the micrometer range, or smaller (i.e., smaller than about 10 microns). It should be noted that if components other than the micro machined component are included in the MEMS device, these other components may be micro machined components or standard sized (i.e., larger) components. Similarly, the term “microvalve” as may be used in this application means a valve having features or clearances with sizes in the micrometer range, or smaller (i.e., smaller than about 10 microns) and thus by definition is at least partially formed by micro machining. The term “microvalve device” as may be used in this application means a device that includes a microvalve, and that may include other components. It should be noted that if components other than a microvalve are included in the microvalve device, these other components may be micro machined components or standard sized (i.e., larger) components. 
         [0003]    Many MEMS devices may be made of multiple wafers (or plates) of material, which may be micromachined to form components of the MEMS device prior to assembly of the multiple wafers into a completed MEMS device. For example, such a MEMS device may be manufactured using suitable MEMS fabrication techniques, such as the fabrication techniques disclosed in U.S. Pat. No. 6,761,420, the disclosures of which are incorporated herein by reference; U.S. Pat. No. 7,367,359, the disclosures of which are incorporated herein by reference; Klassen, E. H. et al. (1995), “Silicon Fusion Bonding and Deep Reactive Ion Etching: A New Technology for Miscrostructures,” Proc. Transducers 95 Stockholm Sweden pp. 556-559, the disclosures of which are incorporated herein by reference; and Petersen, K. E. et al. (June 1991), “Surface Micromachined Structures Fabricated with Silicon Fusion Bonding,” Proc. Transducers 91 pp. 397-399, the disclosures of which are incorporated herein by reference. 
       SUMMARY OF THE INVENTION 
       [0004]    The invention relates to a method to prevent movable structures within a MEMS device from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon to aid in preventing movable structures from bonding to adjacent surfaces during bonding of other surfaces, including during high force, high temperature fusion bonding. 
         [0005]    Various aspects of this invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiment, when read in light of the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is a non-scale cross-sectional view of a MEMS device. 
           [0007]      FIG. 2  is a flow chart illustrating a method for preparing a surface for selective fusion bonding. 
           [0008]      FIG. 3  is a flow chart providing detail of a step of the method of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0009]    Preliminarily, it should be noted that certain terms used herein, such as “upper”, “lower”, “middle”, “upward”, “downward”, “top”, “bottom”, “front”, “back”, and “side”, are used to facilitate the description of the preferred embodiment of the invention. Unless otherwise specified or made apparent by the context of the discussion, such terms should be interpreted with reference to the figure under discussion. Such terms are not intended as a limitation on the orientation in which the components of the invention may be used. 
         [0010]    Referring now to the drawings, there is illustrated in  FIG. 1  a portion of a first component, indicated generally at  10 . The component  10  is a MEMS device with a portion that moves (actuates) relative to other, fixed portions, such as may be found in a microvalve, a micromachined sensor, or a micromachined optical switch. In the illustrated embodiment, the component  10  is formed from three wafers of single crystal silicon, including (as viewed with reference to  FIG. 1 ) an upper wafer  12 , a middle wafer  14 , and a lower wafer  16 . 
         [0011]    The upper wafer  12  has a recess  12   a  formed in a lower surface  12   b  thereof. A thermal silicon dioxide layer  18  is fixed to the lower surface  12   b,  including the upper surface of the recess  12   a.  As will be explained further below, a silicon nitride layer  20  is deposited on the thermal silicon dioxide layer  18  in the recess  12   a ; preferably the silicon nitride layer  20  is a Plasma-Enhanced Chemical Vapor Deposition (PECVD). The PECVD silicon nitride layer  20  has non-uniform distribution within the recess  12   a,  as will be further explained below, and is preferably provided with relatively high surface roughness (sufficiently rough to prevent fusion bonding with a silicon component in contact with the rough surface—in a preferred embodiment, the surface roughness of the silicon nitride layer  20  within the recess  12   a  may be greater than about 3 Angstroms RMS, for reasons which will also be explained below. Non-recessed portions of the lower surface  12   b  are bonded via the silicon dioxide layer  18  to portions of an upper surface  14   a  of the middle wafer  14 , with the recess  12   a  disposed adjacent to the middle wafer  14 . 
         [0012]    Similarly, the lower wafer  16  has a recess  16   a  formed in an upper surface  16   b  thereof. A second thermal silicon dioxide layer  22  is fixed to the upper surface  16   b,  including the lower surface of the recess  16   a.  As will be explained further below, a second PECVD silicon nitride layer  24  is deposited on the thermal silicon dioxide layer  18  in the recess  16   a.  The PECVD silicon nitride layer  24  has non-uniform distribution within the recess  16   a,  as will be further explained below, and is preferably formed with relatively high surface roughness (a surface with “relatively high surface roughness” as used in this disclosure is defined as a surface that is sufficiently rough to substantially prevent fusion bonding between the surface and a silicon component in contact with the rough surface), for reasons which will also be explained below. In a preferred embodiment, the surface roughness of the silicon nitride layer  24  within the recess  16   a  may be greater than 3 Angstroms RMS. Non-recessed portions of the upper surface  16   b  are bonded via the second silicon dioxide layer  22  to portions of a lower surface  14   b  of the middle wafer  14 , with the recess  16   a  disposed adjacent to the middle wafer  14 . 
         [0013]    The middle wafer  14  has fixed portions  14   c  and  14   d  that do not move relative to the upper wafer  12  or the lower wafer  16 . The middle wafer  14  also has one or more cuts  14   e  micromachined through the middle wafer  14  so as to define a movable portion  14   f  of the middle wafer  14 , in the region between the recess  12   a  and the recess  16   a.  When the movable portion  14   f  is spaced apart from the material above and below the movable portion  14   f  (i.e., the thermal dioxide layer  18  and the PECVD silicon nitride layer  20  fixed to the upper wafer  12 , and the thermal dioxide layer  22  and the PECVD silicon nitride layer  24  fixed to the lower wafer  16 ) then the movable portion  14   f  is able to move relative to the fixed portions  14   c  and  14   d  of the middle wafer  14 , as well as the upper wafer  12  and the lower wafer  16 . Respective conformal thin silicon dioxide layers  15   
         [0014]    During the process of fusion bonding of the upper wafer  12 , the middle wafer  14 , and the bottom wafer  16 , pressure and heat may be applied to the wafers to facilitate the formation of a high bond strength bond, a process that may induce stresses in the wafers. The stresses that may be set up can cause the movable portion  14   f  to move out of the plane of the middle wafer  14 , and contact either the silicon nitride layer  18  in the bottom of recess  12   a  or the silicon nitride layer  24  in the bottom of the recess  16   a.  If the silicon nitride layer  18 ,  24  in bottom of the recess  12   a,    16   a  and the moveable portion  14   f  were sufficiently smooth, the part of the movable portion  14   f  contacting the bottom of the recess  12   a,    16   a  might form a bond at the point of contact with the bottom of the recess  12   a,    16   a  while heated during the bonding process. However, as indicated above, the PECVD silicon nitride layers  18 ,  24  are deposited such that the surfaces of the PECVD silicon nitride layers  18 ,  24  have relatively high surface roughness, i.e., sufficiently rough that fusion bonding (which generally requires very smooth, flat surfaces in intimate contact with each other to create a bond) will not occur between the movable portion  14   f  and any point of contact of the movable portion  14   f  with the PECVD silicon nitride layers  18 ,  24 . 
         [0015]    Furthermore, there may be residual stresses existing after the bonding process that may cause the movable portion  14   f  to be urged out of the plane of the middle wafer  14  following a post-bonding high temperature annealing step, for example. Post-bonding high temperature annealing may desirably improve the bond strength between wafers, thus enabling fluidic MEMS devices, for example, to withstand increased internal pressures. The recesses  12   a  and  16   a  may permit some out of plane movement of the movable portion  14   f,  but it may not be desirable to leave a large clearance between the movable portion  14   f  and the components immediately above and below the movable portion  14   f.  An example of this is a fluidic MEMS device such as a microvalve, where excessive clearance between the movable portion  14  and the non-moving components immediately above and below may result in excessive leakage past a closed valve. 
         [0016]    To prevent excessive clearances, during construction of the component  10 , one preferred method of construction is to deeply etch the recess  12   a  in the upper wafer  12  and the recess  16   a  in the lower wafer  16 , then fill the recesses  12   a  and  16   a  with, first, their respective silicon dioxide layers  18 ,  22 , and then build up the PECVD silicon nitride layers  20 ,  24  to create the desired clearance from the movable portion  14   f.    
         [0017]    However, with relatively small clearances, residual stress in the component  10  may leave the movable portion  14   f  in contact with the PECVD silicon nitride layers  20 ,  24  after the component  10  is cooled following bonding and annealing. However, in a preferred embodiment the upper and lower surfaces of the movable portion  14   f  are smooth, and the rough PECVD silicon nitride layers  20 ,  24  are relatively hard and wear resistant, so that the movable portion  14   f  will normally ride smoothly on the highpoints of the rough PECVD silicon nitride layer  20  or  24  with which the movable portion  14   f  is in contact, with little sliding resistance. 
         [0018]    General steps of preparing the surfaces of the wafers  12 ,  14 , and  16  forming the component  10  in accordance with a preferred method for selective fusion bonding are described below with respect to  FIGS. 2 and 3 . Various temperatures, time durations, etc., are given in the following description; these should be considered starting point values. As one of ordinary skill in the art will recognize, adjustments to the starting point values of temperature and time duration indicated below may be required based on experience in a particular fabrication line to account for various environmental factors, feedstock qualities, etc. 
         [0019]    In a first step  101 , the surfaces are cleaned of organics. The first step  101  includes a first sub-step of clean the surfaces using a first cleaning solution of 1:4:20 NH 4 OH:H2O2:H2O (1 part Ammonium hydroxide, 4 parts Hydrogen Peroxide, and 20 parts Water), at about 70 ° C., for about 10 minutes to facilitate removal of organics. It is contemplated that alternate solutions with other ratios of constituent chemicals, and indeed different chemicals, may be utilized to facilitate removal of organics, as different organic materials may respond differently to such alternate solutions. 
         [0020]    The first step  101  also includes a second sub-step, rinse the surface using DI water (Deionized water), preferably in a dump rinse, for about 10 minutes. 
         [0021]    In a second step  102 , the native oxide is removed from the surfaces of the component  10 . In a first sub-step of step  102 , clean the surfaces using a second cleaning solution of 1:100 HF:H2P (1 part Hydrogen fluoride and 100 parts Water) at about 25° C., for about 5 minutes to facilitate removal of native oxide. It is contemplated that alternate solutions with other ratios of constituent chemicals, and indeed different chemicals, may be utilized to facilitate removal native oxide. 
         [0022]    In a second sub-step of the step  102 , rinse the surfaces using DI water (Deionized water), preferably in a dump rinse, for about 10 minutes. 
         [0023]    In a third sub-step of the step  102 , soak the surfaces in fresh IPA (isopropyl alcohol) about for 5 minutes. 
         [0024]    In a fourth sub-step of the step  102 , dry the surfaces at room temperature for about 15 minutes or furnace dry the component  10  at about 56° C. for about 6 minutes. 
         [0025]    In a third step  103 , an oxide layer  15 ,  18 ,  24  is formed on the surface of the wafer, to promote bonding during a later fusion bonding process. The type of oxide layer to be formed depends on the type of wafer on which the oxide layer is being formed. For the cover wafers (the upper wafer  12  and the lower wafer  16 ), a thermal silicon dioxide layer  18 ,  24  of perhaps 2000 to 3000 Angstroms in thickness is grown utilizing an oxidation furnace (not shown). For the middle wafer  14 , which is a bare silicon wafer, a conformal thin silicon dioxide layer  15  is grown utilizing nitric acid (HNO3) to promote formation of an oxide-monolayer. The conformal thin silicon dioxide layer  15  may be generally considered an oxide monolayer. 
         [0026]    Initially the third step  103  will be described with respect to processing of the middle wafer  14 : In a first sub-step of the third step  103 , apply HNO3 at about 70° C. to about 110° C., for about 15 minutes for promotion of a hydrous chemical oxide, the conformal thin silicon dioxide layer  15 . 
         [0027]    In a second sub-step of the step  103 , rinse the surfaces using DI water (Deionized water), preferably in a dump rinse, for about 10 minutes. 
         [0028]    In a third sub-step of the step  103 , soak the surfaces in fresh IPA (isopropyl alcohol) about for 5 minutes. 
         [0029]    In a fourth sub-step of the step  103 , dry the surfaces of the wafer  14  at room temperature for about 15 minutes or furnace dry the component  10  at about 56° C. for about 6 minutes. 
         [0030]    Next with respect to processing of the cover layers  12 ,  16 , the third step  103  simply consists of the third step  103  may be growing a thermal silicon dioxide layer  18 ,  24  (of perhaps 2000 to 3000 Angstroms thickness) in an oxidation furnace. The thermal silicon dioxide layers  18  and  24  are grown on, respectively, the lower surface  12   b  of the upper wafer  12  and the upper surface  16   b  of the lower wafer  16 . 
         [0031]    Note: Not all steps are required for all parts of the component  10 . The middle wafer  14  (known as a mechanical wafer, since moveable portions  14   f  are formed in the middle wafer  14 ) is formed of a bare silicon wafer (there are no oxide layers on the surfaces thereof before fusion bonding occurs. For bare silicon wafers (such as the middle wafer  14 ), perform the first step  101 , the second step  102 , and the third step  103  to prepare the bonding interface surfaces of the wafer for fusion bonding. 
         [0032]    However, only the first step  101  and the third step  103  need be run to prepare the oxidized silicon wafer surfaces for fusion bonding (such as are found on the bonding interface surfaces of the upper wafer  12  and lower wafer  16 —more specifically, the lower surface  12   b  of the upper wafer  12  and the upper surface  16   b  of the lower wafer  16 ). 
         [0033]    Oxygen plasma can also be used to promote hydrophilicity of wafer surfaces. However, the tool chamber in which oxygen plasma is utilized should be completely free of contamination. 
         [0034]    In a fourth step  104 , the upper wafer  12  and the lower wafer  16  are treated to create selective bonding regions. 
         [0035]      FIG. 3  is a more detailed look at the fourth step shown in  FIG. 2 . The creation of a reusable shadow mask, in a sub-step  104 A, will normally be preliminary to the actual process, since the shadow mask utilized may have been previously used in the manufacture of other components  10 . Assuming that suitable shadow masks had been previously created, then the first sub-step  104 B of the step  104  may include aligning the upper wafer  12  and a respective first shadow mask, and securing them in this aligned condition, and may further include aligning the lower wafer  16  and a respective second shadow mask, and securing them in this aligned condition. A preferred method is to use a fixture to align the shadow mask and the wafer  12 ,  16 , and clamps to secure the shadow mask to the silicon wafer  12 ,  16 . The silicon wafer  12 ,  16 , of course, may have been previously micromachined to form features, such as the recesses  12   a,    16   a.  Alternative shadow mask attachment methods may include the use of mechanical fixtures or clamps, utilizing photoresist as a glue layer, utilizing thermally retardant tapes, etc. 
         [0036]    Note, in a preferred embodiment, each shadow mask is made from an 8 inch silicon wafer, which is preferably the same size as the upper wafer  12  and the lower wafer  16  for ease of alignment; however, the sizes of the shadow mask, upper wafer  12 , and lower wafer  16  may be made otherwise—indeed, as fab technology advances, preferences are expected to change. Furthermore, while this disclosure discusses only one component  10 , it will be realized that preferably components for multiple components  10  will be fabricated from each wafer  12 ,  14 , and  16 . Preferably, the shadow mask is made out of silicon or metal with laser or chemically etched opening(s) therethrough. 
         [0037]    Preferably, the shadow mask wafer is pre-coated with PECVD silicon nitride to avoid bonding between the cover wafer and the shadow mask wafer during alignment. The PECVD silicon nitride coat thickness on the shadow masks are preferably in the range of 500 Angstroms (50 nanometers) to 1000 Angstroms (100 nanometers). Shadow masks can also be created, for example, from LPCVD (Low Pressure Chemical Vapor Deposition) nitride wafers that have gone through an HMDS (Hexamethyldisilazane) oven process. 
         [0038]    In  FIG. 2 , the second sub-step of the step  104  is to treat the unmasked areas of the surface of the cover wafer  12 ,  16  to prevent fusion bonding to the treated surface. Any suitable treatment may be utilized. For example, silicon nitride is a more difficult surface for a silicon member (for example the movable portion  14   f  of the middle wafer  14 ) to fusion bond to than a silicon dioxide surface, for example, and so, compared to the silicon dioxide surface, the silicon nitride surface may be considered to be bonding resistant. Thus, the application of silicon nitride to the unmasked area may be considered a treatment of the unmasked area to prevent bonding. Another treatment, described in more detail below, may be roughening the unmasked areas sufficiently to prevent fusion bonding. 
         [0039]    In a third sub-step  104 C of the third step  103 , after a silicon dioxide layer  18  or  24  is built up, and the shadow mask fixed in position relative to the cover wafers  12 ,  14 , the portion of the silicon dioxide layer  18  or  24  within the recesses  12   a  or  16   a  of the cover wafer  12  or  14  may be deliberately roughened as a treatment to decrease the possibility of fusion bonding inside the recesses  18  or  24 , respectively. The silicon dioxide layer  18  or  24  is preferably roughened by etching, such as by RF (radiofrequency) based dry etching methods or reactive ion etching. 
         [0040]    A sub-step  104 D shown in  FIG. 3  is a deposition sub-step, and includes inserting a cover wafer (the upper wafer  12  or the bottom wafer  16 ) and the associated aligned and secured shadow mask into a PECVD nitride tool (process temperature approximately 300° C.-350° C.) and deposit PECVD silicon nitride on the surfaces which are not masked off (i.e., in the recess  12   a,    16   a ). A typical nitride target thickness is 2000 Angstroms-3000 Angstroms. Preferably, the rate of deposition of PECVD silicon nitride to form the silicon nitride layers  20 ,  24  changes: Initially, in the sub-step  104 D, the rate of deposition should be relatively slow rate of deposition (less than about 25 Angstroms per minute, and preferably less than 20 Angstroms per minute) to achieve a thin, but substantially complete coating of the unmasked area. In a second deposition step, the sub-step  104 E, the deposition of the PECVD silicon nitride layer  20 ,  24  into the recess  12   a,    16   a  is preferably finished utilizing a relatively fast rate of deposition (greater than or equal to about 25 Angstroms per minute, and preferably about 50 Angstroms per minute). This relatively fast rate of deposition is used to achieve a relatively rough surface on the resultant nitride layer  20 ,  24  in the unmasked area. The varying deposition rates of the silicon nitride layer  20 ,  24  will give good coverage and varying surface roughness on the silicon nitride layer  20 ,  24 . The thickness of the silicon nitride layer  20 ,  24  is determined by the final desired cavity clearance required between the sandwich structures (i.e., between the surface of the silicon nitride layer  20 ,  24  and the adjacent movable component  14   f  of the middle wafer  14 . As indicated above, the amount of roughness is that sufficient to prevent fusion bonding with a silicon component (such as a movable portion  14   f  of the middle wafer  14 ) if such component comes in contact with the rough surface while the wafers  12 ,  14 ,  16  are heated to fusion bond the wafers together—in a preferred embodiment, the surface roughness of the silicon nitride layer  20 ,  24  within the respective recess  12   a,    16   a  may be greater than 3 Angstroms RMS. The silicon nitride layer  20 ,  24  is also preferably deposited with a non-uniform distribution pattern. This pattern should achieve the desired cavity clearance at the thickest part of the silicon nitride layer  20 ,  24 . However, the non-uniform distribution pattern should result in the silicon nitride layer  20 ,  24  being thinner away from the thickest part of the silicon nitride layer  20 ,  24  so as to minimize friction between a movable portion  14   f  of the middle wafer  14  and the silicon nitride layer  20 ,  24 . As seen in  FIG. 1 , in one embodiment the silicon nitride layer  20 ,  24  is generally thicker in a central portion of the recess  12   a,    16   a,  and thinner elsewhere. 
         [0041]    The deposition of PECVD silicon nitride is terminated when the depth of the recess  12   a,    16   a  less (minus) the combined thickness of the silicon nitride layer  20 ,  24  and the oxide layer (silicon dioxide layer  18 ,  22 ) provides a desired cavity clearance. The cavity clearance is the clearance from the silicon nitride layer  20 ,  24  to an adjacent component (such as the middle wafer  14 , particularly, the movable portion  14   f ) when the adjacent component is disposed over the recess  12   a,    16   a  and supported by the non-recessed portions of the silicon surface ( 12   b,    16   b ) of the wafer  12 ,  16  in which the recess  12   a,    16   a  is formed. 
         [0042]    In a final sub-step  104 F of the step  104 , remove shadow masks from the cover wafer (wafers  12 ,  16 ) after the deposition steps (the sub-steps  104 D and  104 E of the step  104 ). Preferably, prior to bonding, the wafers  12 ,  14 ,  16  should be cleaned, such as with DI water in a spin rinse dryer, or any other suitable method. 
         [0043]    After completing of the step  104 , the wafers  12 ,  14 ,  16  are arranged in proper order and orientation, heated, and subjected to pressure to cause fusion bonding of the wafers together, with bonding occurring where the silicon dioxide layer  18 ,  22  built up in the third step  103  are in contact with the middle wafer, and no bonding occurring where the respective silicon nitride layer  20 ,  24  is interposed between the silicon dioxide layers  18 ,  22  and the middle wafer  14 , especially when the silicon nitride layer  20 ,  24  has a relatively high surface roughness. 
         [0044]    In summary,  FIG. 1  shows the overall surface composition of a MEMS device composed of wafers configured for selective fusion bonding during manufacture of the MEMS device. The MEMS device includes a first generally planar silicon wafer having a silicon dioxide layer formed thereon, a portion of the silicon dioxide layer having a silicon nitride layer deposited thereon. The MEMS device further includes a second generally planar silicon wafer micromachined to form a movable portion and a fixed portion, the fixed portion being bonded to the silicon dioxide layer of the first silicon wafer, the movable portion being movable relative to the fixed portion and disposed adjacent the silicon nitride layer, such that a line perpendicular to the first and second wafers passing through the movable portion would also pass through the silicon nitride layer.  FIGS. 2 and 3  illustrate processes for achieving the structure shown in  FIG. 1 . First the adjacent surfaces of the wafers  12 ,  14 , and  16  are cleaned, especially to remove organics. Then the native oxides are removed from the adjacent surfaces of the wafers  12 ,  14 , and  16 . Next an oxide layer (preferably a thermal silicon dioxide layer  18 ,  22 ) is formed on the surface of the wafer  12 ,  16  that faces the middle wafer  14 , including within the recess  12   a,    16   a.  Next, the silicon dioxide layer within the recess  12   a,    16   a  may be roughened utilizing an etching process such as reactive ion etching or radiofrequency based dry etching methods. Next, the PECVD silicon nitride layer  20 ,  24  is deposited onto the silicon cover wafer recess  12   a,    16   a  utilizing a re-usable shadow wafer to mask off areas which are not to be coated in rough silicon nitride, so that the masked-off areas remain amenable to fusion bonding. 
         [0045]    Preferably the deposition of the PECVD silicon nitride layer  20 ,  24  into the recess  12   a,    16   a  is initially made at a low deposition rate. In the sub-step  104 D, the deposition of the PECVD silicon nitride layer  20 ,  24  into the recess  12   a,    16   a  is preferably finished utilizing a final high deposition rate. The varying deposition rates of the silicon nitride layer  20 ,  24  will give good coverage and varying surface roughness on the silicon nitride layer  20 ,  24 . 
         [0046]    The thickness of the silicon nitride layer  20 ,  24  is determined by the final desired cavity clearance required between the sandwich structures (i.e., between the surface of the silicon nitride layer  20 ,  24  and the adjacent movable component  14   f  of the middle wafer  14 . When the treatment of the unmasked areas is completed, a final sub-step  104 E includes removing the shadow mask from the wafer surface. Preferably, prior to bonding, the wafers  12 ,  14 ,  16  should be cleaned, such as with DI water in a spin rinse dryer, or any other suitable method. 
         [0047]    Once the wafers  12 ,  14 ,  16  are brought together for fusion bonding, the chemical properties of the silicon nitride layer  20 ,  24 , and the surface roughness of the silicon nitride layer  20 ,  24  will inhibit the bonding of the middle wafers  14  to the cover wafers (upper wafer  12 , lower wafer  16 ). The silicon nitride layers  20 ,  24  are also preferably deposited with a non-uniform distribution pattern, such that the general thickness (i.e., ignoring variations caused by surface roughness) of the silicon nitride layer  20 ,  24  varies from location to location, as seen in  FIG. 1 . This pattern should achieve the desired cavity clearance at the thickest part of the silicon nitride layer  20 ,  24 . However, the distribution pattern should result in the silicon nitride layer  20 ,  24  being thinner away from the thickest part of the silicon nitride layer  20 ,  24  so as to minimize friction between a movable portion  14   f  of the middle wafer  14  and the silicon nitride layer  20 ,  24 . The wafer can then be safely annealed after fusion bonding, for example at temperatures up to 1000 C for high bond strength, without degradation of the engineered surfaces that can facilitate the bonding of the middle wafer  14 . In testing, this process has been successfully implemented to achieve cavity clearances from 2000 Angstroms (200 nanometers) to 2 microns. 
         [0048]    The innovative combinations of processes described above will permit the practitioner to achieve selective fusion bonding of not only relatively smooth wafers, but also to achieve selective fusion bonding of wafers with features having relatively high and even non-uniform aspect ratios. For example, the processes taught above are believed to permit bonding surfaces of wafers forming parts of MEMS devices, in which recesses have been etched of varying relatively deep (greater than 2 microns) depth; these processes have been used to fusion bond wafers assembled into MEMS devices, the wafers having etched into them a variety of cavity depths, including, for example recesses with depths on the order of 2 microns to recesses on the order of 150 microns. In a typical wet chemical etch process, one has to spin coat a protective layer of photoresist across the surface of a wafer, expose it to light to pattern the photoresist, develop the photoresist to remove photoresist in unprotected areas, etch the unprotected areas, and then remove the remaining photoresist. It is extremely difficult to spin coat photoresist uniformly across a wafer that has many etched structures with varying aspect ratios. Even if this could be accomplished, which is doubtful, many steps have to be implemented to etch each wafer. In contrast, the innovative processes described herein use a hard mask (shadow mask) to protect areas which are not to be roughened by etching. Formation of the mask on a separate smooth surface, and mechanically aligning it with the wafer to be etched is a relatively straightforward process, much easier than spreading photoresist across a wafer that has multiple etched structures with varying aspect ratios. Additionally, the shadow mask can be reused with multiple wafers without requiring the difficult application of a sacrificial photoresist protective layer to direct the etching of each wafer to be etched. 
         [0049]    The principles and modes of operation of this invention have been explained and illustrated in its preferred embodiments. However, it must be understood that this invention may be practiced otherwise than as specifically explained and illustrated without departing from its spirit or scope.