Abstract:
Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of co-pending U.S. patent application Ser. No. 13/433,061, filed on Mar. 28, 2012, which claims priority to Taiwan Patent Application Serial No. 100123897, filed on Jul. 6, 2011. The priority applications are incorporated herein by reference in their entireties. 
     
    
     BACKGROUND 
       [0002]    The present embodiments relate to semiconductor device packages, and more particularly to semiconductor device packages having a lead frame and related manufacturing methods. 
       DESCRIPTION OF RELATED ART 
       [0003]    A quad-flat no-leads (QFN) package is a type of semiconductor device package having short signal traces and, thus, fast signal transmission speed. Therefore, QFN packages are well suited to chip packages with high frequency transmission (e.g. high frequency transmission through the RF bandwidth), and have become common for package applications in the wireless field, for example. 
         [0004]    In one method of making a conventional QFN package, a lead frame having die pads and leads is provided. Chips, or dies, are configured on the die pads and electrically connected to the leads via bonding wires. The leads, the bonding wires, and the chips are encapsulated and protected by a molding compound, or encapsulant, and the bottom surfaces of the leads are exposed from the encapsulant for electrical connection to an external device, such as a printed circuit board (PCB). A singulation process is then performed to divide the structure into individual QFN packages. 
         [0005]    After PCB surface mount, a drop test may be performed to evaluate solder joint reliability between the QFN package and the PCB. During the drop test, the solder joint is usually broken at the corners of the QFN package. Therefore, there is a need to improve the solder joint strength at the corners. 
       SUMMARY 
       [0006]    One of the present embodiments comprises an electronic device. The electronic device comprises a semiconductor device package. The semiconductor device package includes a die pad, a plurality of leads disposed about the die pad, and a plurality of enhancement elements disposed about the die pad. Each of the enhancement elements has a substantially triangular outer surface and three side surfaces. The semiconductor device package further includes a chip disposed on the die pad and electrically connected to the leads, and a package body encapsulating the chip, at least portions of the leads and at least portions of the enhancement elements, but leaving exposed at least two of the side surfaces of each enhancement element. The exposed side surfaces of the enhancement elements are coplanar with side surfaces of the package body. The electronic device further comprises a substrate including a plurality of first pads corresponding to the leads and a plurality of second pads corresponding to the enhancement elements. The electronic device further comprises a plurality of first solder joints disposed between the first pads and the leads. The electronic device further comprises a plurality of second solder joints disposed between the second pads and the enhancement elements. A surface area of each of the second pads is larger than a surface area of a corresponding one of the enhancement elements. The second solder joints contact the side surfaces of the enhancement elements. 
         [0007]    Another of the present embodiments comprises an electronic device. The electronic device comprises a semiconductor device package. The semiconductor device package includes a die pad and a plurality of leads disposed about the die pad. The semiconductor device package further includes a plurality of enhancement elements disposed symmetrically about the die pad. Each enhancement element including substantially rectangular inner and outer surfaces. The semiconductor device package further includes a chip disposed on the die pad and electrically connected to the leads, and a package body encapsulating the chip, at least portions of the leads and at least portions of the enhancement elements, but leaving exposed at least one side surface of each enhancement element. The exposed side surfaces of the enhancement elements are coplanar with side surfaces of the package body. The electronic device further comprises a substrate including a plurality of first pads corresponding to the leads and a plurality of second pads corresponding to the enhancement elements. The electronic device further comprises a plurality of first solder joints disposed between the first pads and the leads. The electronic device further comprises a plurality of second solder joints disposed between the second pads and the enhancement elements. The enhancement elements include first enhancement elements disposed at corners of the package body and second enhancement elements disposed at a center of each edge of the package body. The second solder joints contact the side surfaces of the enhancement elements. 
         [0008]    Another of the present embodiments comprises a method of manufacturing an electronic device. The method comprises providing a semiconductor device package. The semiconductor device package comprises a die pad, a plurality of leads surrounding the die pad, and a plurality of enhancement elements surrounding the die pad. The semiconductor device package further comprises a chip disposed on the die pad and electrically connected to the leads, and a package body encapsulating the chip, portions of the leads and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. The side surface of each enhancement element is coplanar to the side surface of the package body. The method further comprises providing a substrate. The substrate comprises a plurality of first pads corresponding to the leads and second pads corresponding to the enhancement elements. The method further comprises mounting the semiconductor device package to the substrate by first and second solder joints. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The area of each of the second pads is greater than the area of each of the corresponding enhancement elements. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1A  is a bottom plan view illustrating one embodiment of the present semiconductor device packages; 
           [0010]      FIG. 1B  is a cross-sectional side view of the semiconductor device package of  FIG. 1A , taken through the line  1 B- 1 B in  FIG. 1A ; 
           [0011]      FIG. 1C  is a cross-sectional side view of the semiconductor device package of  FIG. 1A , taken through the  1 C- 1 C in  FIG. 1A ; 
           [0012]      FIG. 1D  is a cross-sectional side view the semiconductor device package of  FIG. 1A  after PCB surface mount; 
           [0013]      FIG. 2  is a bottom plan view illustrating another embodiment of the present semiconductor device packages; 
           [0014]      FIG. 3  is a bottom plan view illustrating another embodiment of the present semiconductor device packages; 
           [0015]      FIG. 4  is a bottom plan view illustrating another embodiment of the present semiconductor device packages; 
           [0016]      FIG. 5  is a bottom plan view illustrating another embodiment of the present semiconductor device packages; 
           [0017]      FIG. 6  is a bottom plan view illustrating another embodiment of the present semiconductor device packages; 
           [0018]      FIG. 7A  is a bottom plan view illustrating one embodiment of the present electronic devices; 
           [0019]      FIG. 7B  is a partial cross-sectional side view of the electronic device of  FIG. 7A , taken through the line  7 B- 7 B in  FIG. 7A ; and 
           [0020]      FIG. 8  is a bottom plan view illustrating another embodiment of the present electronic devices. 
       
    
    
       [0021]    Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements. The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. 
       DETAILED DESCRIPTION 
       [0022]    Referring to  FIGS. 1A-1C , a bottom plan view and two cross-sectional side views of a QFN semiconductor device package  100   a  according to one of the present embodiments is illustrated. The cross-section of the semiconductor device package  100   a  shown in  FIG. 1B  is taken along the line  1 B- 1 B in  FIG. 1A . The cross-section of the semiconductor device package  100   a  shown in  FIG. 1C  is taken along the line  1 C- 1 C in  FIG. 1A . 
         [0023]    With reference to  FIG. 1A , the semiconductor device package  100   a  includes a carrier  200   a,  a chip  300 , and a molding compound  500 . The carrier  200   a  includes a die pad  210 , a plurality of leads  220  and an enhancement element  230   a.  The die pad  210  has a cavity  210   a  for disposing the chip  300 . The leads  220  are disposed around the die pad  210 , in which each lead  220  has a first inner surface  222  (shown in  FIG. 1B ) and a first outer surface  224  opposite to each other. The enhancement element  230   a  is disposed around the die pad  210  and continuously circumscribes the outer perimeter of the package  100   a,  in which the enhancement element  230   a  has a second inner surface  232   a  and a second outer surface  234   a  opposite to each other. A surface area of the second outer surface  234   a  of the enhancement element  230   a  is larger than a surface area of the first outer surface  224  of each of the leads  220 . Further, a surface area of the second inner surface  232   a  is smaller than a surface area of the second outer surface  234   a.  The shapes of the second inner surface  232   a  and the second outer surface  234   a  of the enhancement element  230   a  may both be, for example, annular when viewed in upper or lower plan view. 
         [0024]    With reference to  FIG. 1B , metal plating layers  223 ,  225  may be provided on the first inner surface  222  and the first outer surface  224 . The metal layers  223 ,  225  may be formed from titanium/copper (Ti/Cu), nickel/gold (Ni/Au), or other suitable metals, alloys, or sequences of metals and/or alloys, such as, but not limited to Cr/Cr—Cu/Cu, Ti/Ni—V, Ti/Ni—V/Cu, Ti/W, or Ti/W/Au. 
         [0025]    With continued reference to  FIG. 1B , the chip  300  is disposed on the die pad  210  of the carrier  200   a.  The semiconductor device package  100   a  further includes a plurality of bonding wires  400  that electrically connect the chip  300  to the first inner surfaces  222  of the leads  220 . The bonding wires  400  may also electrically connect the chip  300  to the die pad  210 . The molding compound  500  encapsulates the chip  300 , the bonding wires  400 , and the first inner surfaces  222  of the leads  220 , but leaves exposed the first outer surfaces  224  of the leads  222  and the lower surface of the die pad  210 . 
         [0026]    With reference to  FIG. 1C , as discussed above, the enhancement element  230   a  has the second inner surface  232   a  and the second outer surface  234   a  opposite to each other. The bonding wires  400  may electrically connect the chip  300  to the second inner surface  232   a  of the enhancement element  230   a.  The molding compound  500  further encapsulates the second inner surface  232   a  of the enhancement element  230   a,  but leaves exposed the second outer surface  234   a  of the enhancement element  230   a.    
         [0027]    Referring to  FIG. 1D , a cross-sectional side view of the semiconductor device package  100   a  after PCB surface mount is illustrated. The first outer surfaces  224  of the leads  220  and the second outer surface  234   a  of the enhancement element  230   a  are mounted to a PCB  10  by solder  600 . Advantageously, since the enhancement element  230   a  increases the solder contact area and solder capacity so as to enhance the connection strength, it can improve the solder joint reliability between the semiconductor device package  100   a  and the PCB  10 . The solder  600  can be formed on the semiconductor device package  100   a  by a dip soldering process, a solder printing process, or an electroless plating process, for example, or any other process for PCB surface mount. Alternatively, the solder  600  can be formed on the PCB  10  by a dispensing process, a screen printing process or a stencil printing process, for example, or any other process for PCB surface mount. 
         [0028]    Referring to  FIG. 2 , a bottom plan view of a semiconductor device package  100   b  according to another of the present embodiments is illustrated. The package  100   b  is similar to the semiconductor device package  100   a  of  FIG. 1A , except that an enhancement element  230   b  of the package  100   b  includes a plurality of enhancement element portions  236   b . The enhancement element portions  236   b  are located at the corners C of the carrier  200   b,  and symmetrically disposed about the die pad  210  as a center. Each enhancement element portion  236   b  has an outer surface  237   b  and an inner surface  237   b ′ opposite to each other. The shape of each surface  237   b,    237   b ′ is substantially triangular, and edges of the outer surfaces  237   b  are substantially aligned with lateral edges of the molding compound  500 . However, a surface area of each outer surface  237   b  is larger than a surface area of its corresponding inner surface  237   b ′, so that edges of the inner surfaces  237   b ′ are recessed from, or not substantially aligned with, lateral edges of the molding compound  500 . Further, the surface area of each outer surface  237   b  of each enhancement element portion  236   b  is larger than a surface area of the first outer surface  224  of each lead  220 . 
         [0029]    Referring to  FIG. 3 , a bottom plan view of a semiconductor device package  100   c  according to another of the present embodiments is illustrated. The semiconductor device package  100   c  is similar to the semiconductor device package  100   b  of  FIG. 1B , except that an outer surface  237   c  and an inner surface  237   c ′ of each enhancement element portion  236   c  is substantially circular. A surface area of each outer surface  237   c  is larger than a surface area of each inner surface  237   c ′. The surface area of the outer surface  237   c  of each enhancement element portion  236   c  is larger than the surface area of the first outer surface  224  of each lead  220 . 
         [0030]    Referring to  FIG. 4 , a bottom plan view of a semiconductor device package  100   d  according to another of the present embodiments is illustrated. The semiconductor device package  100   d  is similar to the semiconductor device package  100   c  of  FIG. 3 , except that an enhancement element  230   d  of the semiconductor device package  100   d  includes a plurality of first enhancement element portions  236   d  and a plurality of second enhancement element portions  238   d.  The first enhancement element portions  236   d  are similar to the first enhancement element portions  236   c  of  FIG. 3 . The second enhancement element portions  238   d  are connected to a periphery of the die pad  210  at a center of each edge thereof, symmetrically disposed, and extend to the edges of the carrier  200   d.  Each second enhancement element portion  238   d  has a second outer surface  239   d  and a second inner surface  239   d ′ opposite to each other. The shapes of the second outer surfaces  239   d  and the shapes of the second inner surfaces  239   d ′ are substantially rectangular, and the surface area of the second outer surface  239   d  of each second enhancement element portion  238   d  is larger than the surface area of the first outer surface  224  of each lead  220 . 
         [0031]    Referring to  FIG. 5 , a bottom plan view of a semiconductor device package  100   e  according to another of the present embodiments is illustrated. The semiconductor device package  100   e  is similar to the semiconductor device package  100   d  of  FIG. 4 , except that the first enhancement element portions  236   d  are omitted. 
         [0032]    Referring to  FIG. 6 , a bottom plan view of a semiconductor device package  100   f  according to another of the present embodiments is illustrated. The semiconductor device package  100   f  is similar to the semiconductor device package  100   a  of  FIG. 1A , except that an enhancement element  230   f  of the semiconductor device package  100   f  includes a plurality of first enhancement element portions  236   f  and a plurality of second enhancement element portions  238   f . The first enhancement element portions  236   f  are located at the corners C of the carrier  200   f,  and symmetrically disposed about the die pad  210  as a center. The second enhancement element portions  238   f  are symmetrically disposed at a center of each edge of the carrier  200   f  with the die pad  210  as a center. Each first enhancement element portion  236   f  has a first outer surface  237   f  and a first inner surface  237   f  opposite to each other. The shapes of the first outer surfaces  237   f  and the first inner surfaces  237   f  are substantially rectangular, and edges of the first outer surfaces  237   f  are substantially aligned with lateral edges of a molding compound  500 . However, a surface area of each first outer surface  237   f  is larger than a surface area of its corresponding first inner surface  237   f ′, so that edges of the first inner surfaces  237   f  are recessed from, or not substantially aligned with, lateral edges of the molding compound  500 . Each second enhancement element portion  238   f  has a second outer surface  239   f  and a second inner surface  239   f ′ opposite to each other. The shapes of the second outer surfaces  239   f  and the second inner surfaces  239   f ′ are substantially rectangular. Edges of the second outer surfaces  239   f  of the second enhancement element portions  238   f  are substantially aligned with lateral edges of the molding compound  500 . However, a surface area of each second outer surface  239   f  is larger than a surface area of its corresponding second inner surface  239   f′,  so that edges of the second inner surfaces  239   f′  are recessed from, or not substantially aligned with, lateral edges of the molding compound  500 . A surface area of each outer surface  238   f,    239   f  of each enhancement element portion  238   f,    239   f  is larger than a surface area of each first outer surface  224  of each lead  220 . 
         [0033]    In alternative embodiments, the enhancement elements  230   a,    230   b,    236   c,    236   d ,  236   e,    236   f  may be changed to other forms and/or shapes. However, it is preferred that the surface areas of the second outer surfaces  234   a,    237   b,    237   c,    237   d,    237   e,    237   f,    239   d,    239   f  of the enhancement elements  230   a,    230   b,    236   c,    236   d,    236   e,    236   f  are larger than the surface areas of the first outer surface  224  of each lead  220 . The ratio of the surface area of each the outer surfaces of the enhancement elements to the surface area of the outer surface of each the lead is larger than or equal to 4. This configuration can enhance the connection strength and improve the solder joint reliability between the semiconductor device package and the PCB. 
         [0034]    Referring to  FIG. 7A , a bottom plan view of an electronic device  700   a  according to another of the present embodiments is illustrated. The electronic device  700   a  includes the semiconductor device package  100   b  of  FIG. 2  and a PCB  20   a.  However, in alternative embodiments, the semiconductor device package  100   b  may be replaced with any other semiconductor device package, such as those  100   a,    100   d,    100   e,    100   f,    100   g  described above. 
         [0035]    The PCB  20   a  includes a plurality of enhancement pads  40   a,  which are located at the corners C of the carrier  200   b,  and are symmetrically disposed about the die pad  210  as a center. Positions of the enhancement pads  40   a  of the PCB  20   a  correspond to positions of the enhancement element portions  236   b  of the semiconductor device package  100   b.  The surface area of each enhancement pad  40   a  is larger than the surface area of the outer surface  237   b  of each first enhancement element portion  236   b.    
         [0036]    Referring to  FIG. 7B , a partial cross-sectional side view of the electronic device  700   a  of  FIG. 7A  is illustrated. The PCB  20   a  includes a plurality of bonding pads  30   a,  the enhancement pads  40   a  and a solder mask layer  50 . The solder mask layer  50  covers the upper surface of the PCB  20   a  and exposes portions  32   a,    42   a  of the bonding pads  30   a  and the enhancement pads  40   a,  respectively. The semiconductor device package  100   b  is mounted to the PCB  20   a  by the solder  600 . 
         [0037]    The surface area of the exposed surface  42   a  of the enhancement pad  40   a  is larger than the surface area of the exposed surface  32   a  of the bonding pad  30   a.  Positions of the bonding pads  30   a  correspond to positions of the leads  220 . Positions of the enhancement pads  40   a  correspond to positions of the enhancement elements  230   b.  The enhancement pads  40   a  extend outside the carrier  200   b  of the semiconductor device package  100   b  in the direction away from the chip  300 . The exposed surface  42   a  of each enhancement pad  40   a  has a width Wd in the direction away from the chip  300 . The outer surface  237   b  of the enhancement element portion  236   b  of the semiconductor device package  100   b  has a width Wb in the same direction, and the ratio (Wd/Wb) is preferably greater than or equal to 1.3. 
         [0038]    The solder  600  is disposed between the leads  220  of the semiconductor device package  100   b  and the bonding pads  30   a  of the PCB  20   a.  Although not shown in  FIG. 7B , the solder  600  may cover the entire surface of each lead  220  that is exposed from the molding compound  500 . The solder  600  is also disposed between the enhancement element portions  236   b  and the enhancement pad portions  44   a.  Since the enhancement pad  40   a  extends outside the enhancement element portions  236   b,  when the ratio (Wd/Wb) is greater than or equal to 1.3, the solder  600  can overflow to contact side surfaces  237   b ″ of the enhancement element portions  236   b.  The overflowed solder  600  can provide additional joint strength and improve the solder joint reliability between the semiconductor device package  100   b  and the PCB  20   a  due to the increased contact area between the solder  600  and the package  100 . 
         [0039]    Referring to  FIG. 8 , a bottom plan view of an electronic device  700   b  according to another of the present embodiments is illustrated. The electronic device  700   b  is similar to the electronic device  700   a  of  FIG. 7A , except that an enhancement pad  40   b  of a PCB  20   b  includes a plurality of first and second enhancement pad portions  45   a,    46   b.  An enhancement element  230   h  of a carrier  200   h  of a semiconductor device package  100   h  includes a plurality of first and second enhancement element portions  236   h,    238   h.    
         [0040]    The first enhancement element portions  236   h  are located at the corners C of the carrier  200   h  and symmetrically disposed about the die pad  210  as a center. The second enhancement element portions  238   h  are symmetrically disposed at centers of the edges of the carrier  200   h  with the die pad  210  as a center. The shapes of the outer surfaces  237   h  and the inner surfaces  237   h ′ of the first enhancement element portions  236   h  are substantially triangular. The shapes of the outer surfaces  239   h  and the inner surfaces  239   h ′ of the second enhancement element portions  238   h  are substantially semicircular. 
         [0041]    Positions of the second enhancement pad portions  46   b  correspond to positions of the second enhancement element portions  238   h.  A surface area of the exposed surface of the second enhancement pad portion  46   b  is larger than a surface area of the outer surface  239   h  of the second enhancement element portion  238   h.  In addition, the edges of the outer surfaces  239   h  of the second enhancement element portions  238   h  are substantially aligned with the lateral edges of the molding compound  500 . Positions of the first and second enhancement pad portions  45   a ,  46   b  correspond to positions of the first and second enhancement element portions  236   h,    238   h . The first and second enhancement pad portions  45   a,    46   b  extend outside the carrier  200   h  of the semiconductor device package  100   h  in the direction away from the chip  300 . The surface area of the exposed surfaces of first and second enhancement pad portions  45   a,    46   b  are larger than the surface area of the outer surfaces the first and second enhancement element portions  236   h,    238   h  respectively. This configuration allows the solder  600  to overflow to the side surfaces of the first and second enhancement element portions  236   h,    238   h.  The overflowed solder  600  can provide additional joint strength and improve the solder joint reliability between the semiconductor device package  100   h  and the PCB  20   b  due to the increased contact area between the solder  600  and the package  100   h.    
         [0042]    While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present invention which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.