Abstract:
A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. The asymmetric stressor enables low leakage current for the body region during charge storage while the drain voltage is low, and enables a body potential coupled to the drain region and a lower threshold voltage for the access transistor during read and write operations.

Description:
BACKGROUND 
       [0001]    The present disclosure relates to a dynamic random access memory (DRAM) structure, and particularly to a DRAM structure including an asymmetric stressor and a method of manufacturing the same. 
         [0002]    Generally, low leakage current is desirable in a DRAM cell in order to provide long retention time for the electrical charge stored in a capacitor. However, in the case of a DRAM cell formed on a semiconductor-on-insulator (SOI) substrate, excessively low leakage current can induce a floating body potential problem in which the voltage of the body of an access transistor is not predictable, and thus, the threshold voltage of the access transistor becomes unstable. 
       SUMMARY 
       [0003]    A stressor structure is formed within a contact region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a deep trench (DT) capacitor region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction (on the contact side) than at the body-source junction (on DT side). The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. The asymmetric stress enables low leakage current for the body region during charge storage while the drain voltage is low, and enables a body potential coupled to the drain region and a lower threshold voltage for the access transistor during read and write operations. 
         [0004]    According to an aspect of the present disclosure, a semiconductor structure includes a trench capacitor embedded within a semiconductor substrate, and an access field effect transistor including a source region and a drain region. The source region is electrically shorted to an inner electrode of the trench capacitor. The semiconductor structure further includes a stressor structure embedded within the drain region, the stressor structure generating asymmetric stress across a body region of the access field effect transistor. 
         [0005]    According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. A capacitor is formed in a semiconductor substrate. An access transistor is formed on the semiconductor substrate. A source region of the access transistor is electrically shorted to an inner electrode of the capacitor. A stressor structure is formed within a drain region of the access transistor. The stressor structure generates asymmetric stress across a body region of the access field effect transistor. 
     
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         [0006]      FIG. 1  is a vertical cross-sectional view of an exemplary semiconductor structure after formation of deep trenches according to an embodiment of the present disclosure. 
           [0007]      FIG. 2  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a node dielectric and an inner electrode in each deep trench according to an embodiment of the present disclosure. 
           [0008]      FIG. 3  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a conductive strap structure according to an embodiment of the present disclosure. 
           [0009]      FIG. 4  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of shallow trench isolation structures according to an embodiment of the present disclosure. 
           [0010]      FIG. 5  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of gate structures and source and drain regions according to an embodiment of the present disclosure. 
           [0011]      FIG. 6  is a vertical cross-sectional view of the exemplary semiconductor structure after deposition and patterning of a dielectric liner according to an embodiment of the present disclosure. 
           [0012]      FIG. 7  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a cavity within a drain of access field effect transistors according to an embodiment of the present disclosure. 
           [0013]      FIG. 8  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a stressor structure according to an embodiment of the present disclosure. 
           [0014]      FIG. 9  is a vertical cross-sectional view of the exemplary semiconductor structure after additional patterning of the dielectric liner according to an embodiment of the present disclosure. 
           [0015]      FIG. 10  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of metal semiconductor alloy regions according to an embodiment of the present disclosure. 
           [0016]      FIG. 11  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a contact level dielectric layer and contact via structures according to an embodiment of the present disclosure. 
           [0017]      FIG. 12  is a vertical cross-sectional view of a first variation of the exemplary semiconductor structure according to an embodiment of the present disclosure. 
           [0018]      FIG. 13  is a vertical cross-sectional view of a second variation of the exemplary semiconductor structure according to an embodiment of the present disclosure. 
           [0019]      FIG. 14  is a vertical cross-sectional view of a third variation of the exemplary semiconductor structure according to an embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    As stated above, the present disclosure relates to a dynamic random access memory (DRAM) structure, and particularly to a DRAM structure including an asymmetric stressor and a method of manufacturing the same. These aspects of the present disclosure are now described in detail with accompanying figures. It is noted that like reference numerals refer to like elements across different embodiments. The drawings are not necessarily drawn to scale. As used herein, ordinals such as “first” and “second” are employed merely to distinguish similar elements, and different ordinals may be employed to designate a same element in the specification and/or claims. 
         [0021]    Referring to  FIG. 1 , an exemplary semiconductor structure according to an embodiment of the present disclosure includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate as provided includes a stack, from bottom to top, of a bottom semiconductor layer  10 , a buried insulator layer  20 , and a top semiconductor layer  30 L. Each of the bottom semiconductor layer  10 , the buried insulator layer  20 , and the top semiconductor layer  30 L can be provided as an unpatterned layer, i.e., a blanket layer having the same thickness throughout. 
         [0022]    The bottom semiconductor layer  10  includes a semiconductor material. The buried insulator layer  20  includes a dielectric material such as silicon oxide, silicon nitride, a dielectric metal oxide, or a combination thereof. The top semiconductor layer  30 L includes a semiconductor material, which can be the same as, or different from, the semiconductor material of the bottom semiconductor layer  10 . The semiconductor material of the top semiconductor layer  30 L is herein referred to as a first semiconductor material. 
         [0023]    Each of the bottom semiconductor layer  10  and the top semiconductor layer  30 L includes a semiconductor material independently selected from elemental semiconductor materials (e.g., silicon, germanium, carbon, or alloys thereof), III-V semiconductor materials, or II-VI semiconductor materials. Each semiconductor material for the bottom semiconductor layer  10  and the top semiconductor layer  30 L can be independently single crystalline, polycrystalline, or amorphous. In one embodiment, the bottom semiconductor layer  10  and the top semiconductor layer  30 L are single crystalline. In one embodiment, the bottom semiconductor layer  10  and the top semiconductor layer  30 L include single crystalline silicon. 
         [0024]    In one embodiment, the bottom semiconductor layer  10  can be doped with dopants of a first conductivity type. The first conductivity type can be p-type or n-type. 
         [0025]    In one embodiment, the thickness of the top semiconductor layer  30 L can be from 5 nm to 300 nm, the thickness of the buried insulator layer  20  can be from 20 nm to 1,000 nm, and the thickness of the bottom semiconductor layer  10  can be from 50 microns to 2 mm, although lesser and greater thicknesses can also be employed for each of these layers ( 10 ,  20 ,  30 L). 
         [0026]    At least one dielectric pad layer  62 L and a trench etch mask layer  64 L can be deposited on the SOI substrate ( 10 ,  20 ,  30 L), for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The at least one dielectric pad layer  62 L includes at least one dielectric layer that can be employed as a stopping layer for planarization purposes. The trench etch mask layer  64 L can include one or more layers that can be employed as an etch mask for forming deep trenches  45  in the SOI substrate ( 10 ,  20 ,  30 L). As used herein, a “deep trench” refers to a trench that extends from a topmost surface of a semiconductor-on-insulator (SOI) substrate through a top semiconductor layer and a buried insulator layer and partly into an underlying semiconductor layer. 
         [0027]    In one embodiment the at least one dielectric pad layer  62 L can include a dielectric material such as silicon nitride, a dielectric metal nitride, a doped silicon undoped silicon oxide, a dielectric metal oxide, or a stack thereof. In one embodiment, the thickness of the at least one dielectric pad layer  62 L can be from 40 nm to 200 nm, although lesser and greater thicknesses can also be employed. The trench etch mask layer  64 L can include, for example, borosilicate glass. The thickness of the trench etch mask layer  64 L can be from 400 nm to 2,000 nm, although lesser and greater thicknesses can also be employed. 
         [0028]    A photoresist layer (not shown) can be applied over the at least one dielectric pad layer  62 L, and can be lithographically patterned to form openings having areas of deep trenches  45  to be subsequently formed. As used herein, a deep trench  45  refers to a trench that extends below the bottom surface of a buried insulator layer. The pattern in the photoresist layer can be transferred into the at least one dielectric pad layer  62 L. Subsequently, the pattern in the at least one dielectric pad layer  62 L can be transferred through the top semiconductor layer  30 L, the buried insulator layer  20 , and an upper portion of the bottom semiconductor layer  10  by an anisotropic etch that employs the at least one dielectric pad layer  62 L as an etch mask. Deep trenches  45  can be formed for each opening in the at least one dielectric pad layer  62 L. The photoresist can be removed by ashing, or can be consumed during the etch process that forms the deep trenches  45 . Any remaining portion of the trench etch mask layer  64  can be subsequently removed selective to the at least one dielectric pad layer  62 L. 
         [0029]    The sidewalls of the deep trenches  45  can be substantially vertically coincident among the various layers ( 62 L,  30 L,  20 ,  10 ) through which the deep trenches  45  extend. As used herein, sidewalls of multiple elements are “vertically coincident” if the sidewalls of the multiple elements overlap in a top-down view. As used herein, sidewalls of multiple elements are “substantially vertically coincident” if the lateral offset of the sidewalls of the multiple elements from a perfectly vertical surface is within 5 nm. The depth of the deep trenches  45 , as measured from the plane of the topmost surface of the SOI substrate ( 10 ,  20 ,  30 L) to the bottom surface of the deep trenches  45 , can be from 500 nm to 10 microns, although lesser and greater depths can also be employed. The lateral dimensions of each deep trench  45  can be limited by the lithographic capabilities, i.e., the ability of a lithographic tool to print the image of an opening on the photoresist layer. In one embodiment, the “width,” i.e., a sidewall to sidewall distance, of each deep trench  45  can be from 30 nm to 150 nm, although lesser dimensions can be employed with availability of lithographic tools capable of printing smaller dimensions in the future. 
         [0030]    Referring to  FIG. 2 , a buried plate  12  can be formed by doping a portion of the bottom semiconductor layer  12  in proximity to sidewalls of the bottom semiconductor layer  10  within each deep trench  45 . Dopants can be introduced, for example, by outdiffusion from a dopant-including disposable material (such as a doped silicate glass) or by ion implantation as known in the art. Further, any other method of forming a buried plate  12  in the bottom semiconductor layer  10  of an SOI substrate ( 10 ,  20 ,  30 L) can be employed in lieu of outdiffusion from a dopant-including disposable material or ion implantation. Alternately, the buried plate  12  can be provided as a contiguous layer constituting a top portion of the bottom semiconductor layer  10  within the SOI substrate ( 10 ,  20 ,  30 L) as provided prior to the processing steps of  FIG. 1 . In one embodiment, the thickness of the buried plate  12  (i.e., the vertical distance between the top surface of the buried plate  12  and the bottom surface of the buried plate  12 ) can be in a range from 2 microns to 10 microns, although lesser and greater thicknesses can also be employed. In an illustrative example, the buried plate  12  can be composed of heavily doped single crystalline silicon or a heavily doped polycrystalline silicon-containing material. 
         [0031]    In one embodiment, the buried plate  12  can be doped with dopants of a second conductivity type which is the opposite of the first conductivity type. For example, the first conductivity type can be p-type and the second conductivity type can be n-type, or vice versa. A p-n junction is formed between the remaining portion of the bottom semiconductor layer  10  and the buried plate  12 . The dopant concentration in the buried plate  12  can be, for example, from 1.0×10 18 /cm 3  to 2.0×10 21 /cm 3 , and typically from 5.0×10 18 /cm 3  to 5.0×10 19 /cm 3 , although lesser and greater dopant concentrations can also be employed. 
         [0032]    A node dielectric layer can be deposited conformally on all physically exposed sidewalls in the deep trenches and on the top surface of the at least one dielectric pad layer  62 L. The node dielectric layer can include any dielectric material that can be employed as a node dielectric material in a capacitor known in the art. For example, the node dielectric layer can include at least one of silicon nitride and a dielectric metal oxide material such as high dielectric constant (high-k) gate dielectric material as known in the art. 
         [0033]    An inner electrode layer can be deposited to completely fill the deep trenches  45 . The inner electrode layer includes a conductive material, which can be a metallic material or a doped semiconductor material. The metallic material can be an elemental metal such as W, Ti, Ta, Cu, or Al, or an ally of at least two elemental metals, or a conductive metallic nitride of at least one metal, or a conductive metallic oxide of at least one metal. The doped semiconductor material can be a doped elemental semiconductor material, a doped compound semiconductor material, or an alloy thereof. The inner electrode layer can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or a combination thereof. The inner electrode layer is deposited to a thickness that is sufficient to completely fill the deep trenches  45 . 
         [0034]    The inner electrode layer can be vertically recessed to a level between the top surface of the buried insulator layer  20  and the bottom surface of the buried insulator layer  20  by a recess etch. The recess etch of the conductive material layer can employ an anisotropic etch such as a reactive ion etch, an isotropic etch such as a wet etch, or a combination thereof. The recess etch can be selective to the material of the node dielectric layer. 
         [0035]    Each remaining portion of the inner electrode layer constitutes an inner electrode  44 . Each inner electrode  44  includes the conductive material of the inner electrode layer, and is formed in a deep trench  45 . The topmost surface of each inner electrode  44  can be substantially planar, and can be located between the level of the top surface of the buried insulator layer  20  and the level of the bottom surface of the buried insulator layer  20 . As used herein, a surface is “substantially planar” if the planarity of the surface is limited by microscopic variations in surface height that accompanies semiconductor processing steps known in the art. A cavity  47  is formed above each inner electrode  44 . 
         [0036]    The physically exposed portions of the node dielectric layer can be patterned by an etch, which can be a wet etch. For example, if the node dielectric layer includes silicon nitride, the physically exposed portions of the node dielectric layer can be removed by a wet etch employing hot phosphoric acid. The remaining portion of the node dielectric layer within each deep trench  45  constitutes a node dielectric  42 . Each set of a portion of the buried plate  12  laterally surrounding a deep trench, a node dielectric  42  on the sidewalls of the deep trench, and the inner electrode  44  therein constitute a trench capacitor ( 12 ,  42 ,  44 ). The buried plate  12 , which can be a single contiguous structure, is an outer node of the trench capacitors, each node dielectric  42  is a dielectric separating an outer electrode from an inner electrode, and each inner electrode  44  is the inner electrode of a trench capacitor. Each trench capacitor is embedded within the SOI substrate ( 10 ,  12 ,  20 ,  30 L). The buried insulator layer  20  overlies the buried plate  12  (i.e., the outer electrode). 
         [0037]    Referring to  FIG. 3 , a conductive strap structure  46  can be formed directly on a top surface of each inner electrode  46 , for example, by depositing a conductive material within the cavity  47  and above the at least one dielectric pad layer  62 L, and subsequently recessing the conductive material. Specifically, the conductive material can be a metallic material or a doped semiconductor material. The metallic material can be an elemental metal such as W, Ti, Ta, Cu, or Al, or an alloy of at least two elemental metals, or a conductive metallic nitride of at least one metal, or a conductive metallic oxide of at least one metal. The doped semiconductor material can be a doped elemental semiconductor material, a doped compound semiconductor material, or an alloy thereof. The conductive material can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or a combination thereof. The conductive material can be deposited to a thickness that is sufficient to completely fill each cavity  47  immediately after deposition. 
         [0038]    The conductive material can be planarized, for example, by chemical mechanical planarization (CMP) employing the at least one dielectric pad layer  62 L as a stopping layer. Subsequently, the conductive material is recessed to a depth between the top surface of the at least one dielectric pad layer  62 L and the bottom surface of the top semiconductor layer  30 L to form the conductive strap structures  46 . In one embodiment, the top surface of each conductive strap structure  46  can be located at, or above, the top surface of the top semiconductor layer  30 L. The conductive strap structure  46  can include the same material as, or a material different from, the inner electrode  44 . A cavity  47  is formed above each conductive strap structure  46 . Each conductive strap structure  46  is in contact with, and overlies, an inner electrode  44 . 
         [0039]    Referring to  FIG. 4 , a shallow trench isolation structure  22  can be formed by forming a contiguous shallow trench and filling the contiguous shallow trench with a dielectric material. The contiguous shallow trench can be formed, for example, by applying a photoresist layer (not shown) over the at least one dielectric pad layer  62 L, by lithographically patterning the photoresist layer to cover the active regions of the top semiconductor layer  30 L and adjacent portions of the conductive strap structures  46 , and by anisotropically recessing physically exposed portions of the top semiconductor layer  30 L and the conductive strap structures  46 . The photoresist layer can be removed, for example, by ashing. 
         [0040]    The contiguous shallow trench can be filled with a dielectric material such as silicon oxide and/or silicon nitride, for example, by chemical vapor deposition (CVD) or spin-coating. Excess portions of the deposited dielectric material is removed, for example, by chemical mechanical planarization (CMP) employing the at least one dielectric pad layer  62 L as a stopping layer. The dielectric material filling the contiguous shallow trench can be recessed, for example, by a recess etch to a height that can be substantially coplanar with, raised above, or recessed below, the top surface of semiconductor material portions  30 , which are remaining portions of the top semiconductor layer  30 L. The remaining dielectric material in the contiguous shallow trench constitutes the shallow trench isolation structure  22 . The at least one dielectric pad layer  62 L can be removed, for example, by a wet etch process that is selective to the materials of the semiconductor material portions  30  and the conductive strap structures  46 . In one embodiment, the wet etch can be selective to the dielectric material of the shallow trench isolation structure  22 . In one embodiment, the initial recess depth for the dielectric material of the shallow trench isolation structure  22  during the recess etch can be controlled such that the top surface of the shallow trench isolation structure  22  after any collateral etching during the removal of the at least one dielectric pad layer  62 L can be at a target height, which can be substantially coplanar with, raised above, or recessed below, the top surfaces of the semiconductor material portions  30 . 
         [0041]    Each semiconductor material portion  30  is a contiguous remaining portion of the top semiconductor layer  30 L, and include a regions for forming at least one field effect transistor. In one embodiment, each semiconductor material portion  30  can include a region for forming a pair of access field effect transistors for accessing the inner electrodes  44  of a pair of trench capacitors ( 12 ,  42 ,  44 ). 
         [0042]    Referring to  FIG. 5 , a pair of field effect transistors can be formed on each semiconductor material portion  30 . Specifically, two gate stack structures ( 50 ,  52 ) are formed over, and across, each semiconductor material portion  30 . Each gate electrode  50  can include gate dielectric materials known in the art. Each gate electrode  52  can include a doped semiconductor material such as doped polysilicon or a doped silicon-containing semiconductor alloy material. 
         [0043]    In an array environment, each gate stack structure ( 50   52 ) can be formed as a line structure that overlies a plurality of semiconductor material portions  30  and a plurality of deep trench capacitors ( 12 ,  42 ,  44 ). A gate spacer  56  can be formed around each gate stack structure ( 50 ,  52 ). A pair of source regions  3 S and a drain region  3 D can be formed by doping portions of each semiconductor material portion  30  employing the gate stack structures ( 50 ,  52 ) as an implantation mask. A remaining portion of each semiconductor material portion  30  underlying the gate stack structure ( 50 ,  52 ) constitutes a body region  3 B. Thus, each semiconductor material portion ( 3 S,  3 D,  3 B) can include a pair of source regions  3 S, a drain region  3 D, and a pair of body regions  3 B. 
         [0044]    Each field effect transistor can be an access transistor for a trench capacitor ( 12 ,  42 ,  44 ). As used herein, an “access transistor” refers to a transistor that controls the flow of electrical charges into a capacitor. The source region  3 S of each access transistor contacts a conductive strap structure  46 , and is electrically shorted to an inner electrode  44  of a trench capacitor ( 12 ,  42 ,  44 ). The gate electrode  52  of an access transistor can have a first width w 1  between a pair of vertical parallel sidewalls that straddle a semiconductor material portion ( 3 S,  3 B,  3 D). 
         [0045]    Referring to  FIG. 6 , a dielectric liner  60  can be deposited on the physically exposed surfaces of the gate electrodes  52 , the gate spacers  56 , the shallow trench isolation structure  22 , the source regions  3 S, and the drain regions  3 D. The dielectric liner  60  includes a dielectric material such as silicon nitride, silicon oxide, a dielectric metal oxide, or a combination thereof. In one embodiment, the dielectric liner  60  can include silicon nitride. The dielectric liner  60  can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or can be deposited by a non-conformal deposition method such as plasma enhanced chemical vapor deposition (PECVD). The thickness of horizontal portions of the dielectric liner  60  can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. At the time of deposition, the dielectric liner  60  is formed as a single contiguous structure that contacts all physically exposed top surfaces and sidewall surface of the exemplary semiconductor structure. 
         [0046]    A photoresist layer  67  is applied over the dielectric liner  60 , and is lithographically patterned to form an opening over each drain region  3 D. The edges of the patterned photoresist layer  67  around each opening can be located between a first vertical plane VP 1  including a sidewall of a neighboring gate electrode  52  and a second vertical plane VP 2  including an outer sidewall of the dielectric liner  60  in proximity to the opening. In one embodiment, the edges of the patterned photoresist layer  67  around each opening can be located between another vertical plane including an inner sidewall of the dielectric liner  60  in proximity to the opening and the second vertical plane VP 2 . Horizontal portions of the dielectric liner  60  that are not masked by the photoresist layer  67  can be removed by an etch, which can be an anisotropic etch. A portion of the top surface of each drain region  3 D can be physically exposed after the anisotropic etch. The lateral extent of the physically exposed portion of the drain region can extend between a pair of vertical sidewalls of the dielectric liner  60  along one direction, and by sidewalls of the shallow trench isolation structure  22  along another direction. The photoresist layer  67  may, or may not, be removed after the anisotropic etch. The removal of the photoresist layer  67  can be performed, for example, by ashing. 
         [0047]    Referring to  FIG. 7 , each physically exposed portion of drain regions  3 D is vertically recessed employing an anisotropic etch. The dielectric liner  60  alone, or the combination of the dielectric liner  60  and the photoresist layer  67  (if the photoresist layer  67  is still present) can be employed as an etch mask for the anisotropic etch that recesses the physically exposed portions of the drain regions  3 D. A cavity  3 C is formed within each drain region  3 D. All surfaces of each cavity  3 C are surfaces of the drain region  3 D that embeds the cavity  3 C. Because the dielectric liner  60  is employed as the etch mask during the anisotropic etch that forms the cavities  3 C, sidewalls of each cavity  3 C can be vertically coincident with sidewalls of the dielectric liner  60  during, and after, formation of the cavities  3 C. In one embodiment, the dielectric liner  60  can cover the entirety of the top surface of each source region  3 C while the cavities  3 C are formed within the drain regions  3 D. Any remaining portion of the photoresist layer  67  can be removed, for example, by ashing. 
         [0048]    Referring to  FIG. 8 , a stressor structure  3 E is formed within each cavity  3 C by deposition of a second semiconductor material that is different from the first semiconductor material, i.e., the semiconductor material of the semiconductor material portions ( 3 S,  3 D,  3 B). The second semiconductor material can be deposited by selective epitaxy, in which the second semiconductor material is deposited on semiconductor surfaces, and is not deposited on dielectric surfaces such as the surfaces of the dielectric liner  60 . During the selective epitaxy process, one or more reactant gases including at least one precursor for the second semiconductor material and an etchant gas are simultaneously or alternately flowed into a process chamber including the exemplary semiconductor structure. The deposition rate of the second semiconductor material on the surfaces of the cavities  3 C is greater than the etch rate of the second semiconductor material provided by the etchant gas, while the deposition rate of the second semiconductor material on the surfaces of the dielectric liner  60  is less than the etch rate of the second semiconductor material provided by the etchant gas. 
         [0049]    In an illustrative example, the first semiconductor material can be silicon, the source regions  3 S and the drain regions  3 E can include n-doped silicon, the body regions  3 B can include p-doped silicon, and the stressor structure  3 E can include a silicon-carbon alloy. In this case, the at least one precursor for the silicon-carbon alloy can include a precursor for silicon and a precursor for carbon. The precursor for silicon can be selected from, for example, SiH 4 , Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , and other precursor gases for silicon. The precursor for carbon can be selected from, for example, CH 4 , C 2 H 2 , C 2 H 4 , C 2 H 6 , and C 3 H 8 , and other known precursor gases for carbon. The etchant gas can be, for example, HCl. A carrier gas such as hydrogen gas can be employed during the epitaxy process. The temperature and the pressure for the selective epitaxy process can be selected from ranges known in the art. 
         [0050]    Each stressor structure  3 E is formed as a single crystalline semiconductor material region having a lattice constant different from the lattice constant of the drain regions  3 D. Because the stressor structures  3 E are formed within the drain regions  3 D and not in the source regions  3 S, the stressor structures  3 E generate an asymmetric stress across each combination of a drain region  3 D, a body region  3 B, and a source region  3 S of an access transistor. Specifically, the stress generated by the stressor structure  3 E has the greatest magnitude within the drain regions  3 D, has a lesser magnitude within the body regions  3 B, and has the least magnitude within the source region  3 S. Correspondingly, within each access transistor, the magnitude of the asymmetric stress is greater at a first interface between the drain region  3 D and the body region  3 B than at a second interface between the source region  3 S and the body region  3 B. 
         [0051]    In the case of stressor structures  3 E including a silicon-carbon alloy and semiconductor material portions ( 3 S,  3 B,  3 D) that include single crystalline silicon material, the stressor structures  3 E can apply a tensile stress on the source regions  3 S, the body regions  3 B, and the drain regions  3 D of the access transistors such that the magnitude of the tensile stress decreases as the location of measurement of the stress moves away from the stressor structure  3 E in each access transistor. 
         [0052]    The stressor structures  3 E can have the same type of doping as the drain regions  3 D. For example, if the drain regions  3 D have n-type doping, the stressor structures  3 E can have n-type doping. If the drain regions  3 D have p-type doping, the stressor structures  3 E can have p-type doping. The stressor structure  3 E can be doped with electrical dopants, which can be p-type dopants or n-type dopants, by in-situ doping during the selective epitaxy process by flowing a dopant gas concurrently with the one or more reactant gases, and/or can be formed by ex-situ doping by implanting electrical dopants into the stressor structure  3 E, for example, by ion implantation. 
         [0053]    Referring to  FIG. 9 , a photoresist layer  77  can be applied over the dielectric liner  60 , and can be lithographically patterned to form openings therein. Each opening in the photoresist layer  77  can extend along the lengthwise direction of the gate electrodes  52 . The photoresist layer  77  is patterned such that the sidewalls of the photoresist layer are located between the pairs of sidewalls that define the widths of the gate electrodes  52 . The patterned photoresist layer  77  covers all areas of the source regions  3 S, adjoining portions of the gate spacers  56 , and adjoining portions of the gate electrodes  52 . All areas of the stressor structures  3 E and neighboring top surfaces of the drain regions  3 D become physically exposed between various portions of the patterned photoresist layer  77 . An etch is performed to remove physically exposed portions of the dielectric liner  60 . The etch can be an anisotropic etch or an isotropic etch. The etch can be selective to the semiconductor materials of the drain regions  3 D and the stressor structures  3 E. The duration of the etch can be selected such that collateral etching of the gate spacers  56  can be minimized. The photoresist layer  77  can be subsequently removed, for example, by ashing. 
         [0054]    Portions of the top surfaces of the gate electrodes  52  are physically exposed after the etch. A bottom edge of a sidewall of a dielectric liner  60  can run parallel to the sidewalls of an underlying gate electrode  52 , and can be laterally spaced from each of the top edges of the sidewalls of the underlying gate electrode  52 . The percentage of the physically exposed portions of the top surface of each gate electrode  52  with respect to the total area of the top surface of the same gate electrode  52  can be in a range from 20% to 80%, although lesser and greater percentages can also be employed. 
         [0055]    Referring to  FIG. 10 , a metal semiconductor alloy region ( 62 ,  64 ) can be formed on each physically exposed semiconductor surface of the exemplary semiconductor structure. The metal semiconductor alloy regions ( 62 ,  64 ) include drain metal semiconductor alloy regions  62  and gate metal semiconductor alloy regions  64 . The metal semiconductor alloy regions ( 62 ,  64 ) can be formed by inducing a reaction of a metal with physically exposed portions of the semiconductor materials of the exemplary semiconductor structure. For example, a metal layer (not shown) can be deposited on the physically exposed surfaces of the stressor structures  3 E, drain regions  3 D, the gate electrodes  52 , the dielectric liner  60 , and the gate spacers  56 . The metal layer includes an elemental metal or an alloy of elemental metals. For example, the metal layer can include Ni, Pt, Co, W, Ti, or a combination thereof. An anneal is performed at a temperature that induces formation of metal semiconductor alloy materials by reaction of the deposited metal and physically exposed portions of the semiconductor materials. Unreacted portions of the deposited metal, which are present on surfaces of the dielectric liner  60  and the gate spacers  56 , are removed, for example, by a wet etch that removes unreacted metal selective to the metal semiconductor alloy materials. 
         [0056]    A center portion of each drain metal semiconductor alloy region  62  includes a metal semiconductor alloy of the second semiconductor material of the stressor structure  3 E and the metal provided through the metal layer. Further, peripheral portions of each drain metal semiconductor alloy region  62  include another metal semiconductor alloy of the first semiconductor material of the drain region  3 D and the metal provided through the metal layer. Each drain metal semiconductor alloy region  62  can contact an underlying stressor structure  3 E, an underlying drain region  3 D, and sidewalls of two gate spacers  56 . Each gate metal semiconductor alloy region  64  formed on a gate electrode  52  includes an alloy of the semiconductor material of the gate electrodes  52  and the metal from the metal layer. 
         [0057]    A gate electrode  52  straddling a semiconductor material region ( 3 S,  3 B,  3 D) can have a first width w 1  between a pair of sidewalls of the gate electrode  52 . A gate metal semiconductor alloy region  64  on the gate electrode  52  can contact a sidewall of a dielectric liner  64  and an inner sidewall of a gate spacer  56 . The distance of between the vertical surface of the gate metal semiconductor alloy region  64  in contact with the sidewall of the dielectric liner  64  and the vertical surface of the gate metal semiconductor alloy region  64  in contact with the sidewall of the gate spacer  56  is herein referred to as a second width w 2 , which is less than the first width w 1 . The second width w 2  is defined between a pair of vertical sidewalls of the gate metal semiconductor alloy region  64 . In one embodiment, the maximum lateral dimension of the gate metal semiconductor alloy region  64  along the direction perpendicular to the lengthwise direction of the gate electrode  52  can be less than the first width w 1 , which is the width of the gate electrode  52 . The direction of the stress applied to the underlying body region  3 B is along the direction perpendicular to the lengthwise direction of the gate electrode  52 . 
         [0058]    Referring to  FIG. 11 , a contact level dielectric layer  70  can be formed over the gate electrodes  52  and the various metal semiconductor alloy regions ( 62 ,  64 ), and can be planarized. The contact level dielectric layer  70  includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, porous or non-porous organosilicate glass (OSG), or a combination thereof. Drain contact via structures  72  can be formed through the contact level dielectric layer  70  by forming via cavities overlying the stressor structures  3 E, and by filling the via cavities with a conductive material. Gate contact via structures (not shown) can be formed through the contact level dielectric layer to provide electrical contact the gate electrodes  52 . 
         [0059]    The exemplary semiconductor structure includes at least a trench capacitor ( 12 ,  42 ,  44 ) embedded within a semiconductor substrate, which can be an SOI substrate ( 10 ,  20 ,  3 S,  3 B,  3 D,  22 ). The exemplary semiconductor structure further includes an access field effect transistor including a source region  3 S and a drain region  3 D. The source region  3 S is electrically shorted to an inner electrode  44  of the trench capacitor ( 12 ,  42 ,  44 ). The exemplary semiconductor structure further includes a stressor structure  3 E embedded within the drain region  3 D. The stressor structure  3 E generates asymmetric stress across a body region  3 B of the access field effect transistor. The stressor structure  3 E can generate a uniaxial stress along a direction of current flow within the body region  3 B, which is the direction perpendicular to the lengthwise direction of the gate electrode  52 . As used herein, a “lengthwise direction” refers to a direction along which a element extends the farthest. The magnitude of the asymmetric stress can be greater at a first interface between the drain region  3 D and the body region  3 B than at a second interface between the source region  3 S and the body region  3 B. 
         [0060]    The source region  3 S and the drain region  3 D can include a first semiconductor material, and the stressor structure  3 E can include a second semiconductor material having a different lattice constant than the first semiconductor material. The exemplary semiconductor structure can include a drain metal semiconductor alloy region  3 D including a metal semiconductor alloy of a metal and a semiconductor material of the stressor structure  3 E, which is the second semiconductor structure. The drain metal semiconductor alloy region  3 D can further include another metal semiconductor alloy of the metal and another semiconductor material of the drain region, i.e., the first semiconductor material that is different from the second semiconductor material of the stressor structure  3 E. 
         [0061]    In one embodiment, the exemplary semiconductor structure can further include a gate spacer  56  laterally surrounding a gate electrode  52  of the access field effect transistor. A sidewall of the stressor structure  3 E can be laterally offset from a sidewall of the gate spacer  56 . The offset distance can be the same as the lateral thickness of a dielectric liner  60 , which is not present over the drain region  3 D, but is present over the source region  3 S. The dielectric liner  60  can contact an entire top surface of the source region  3 S. The dielectric liner  60  does not have any surface that contacts the top surface of the drain metal semiconductor alloy regions  62  or the gate metal semiconductor alloy regions  64 . 
         [0062]    In one embodiment, a gate spacer  56  laterally surrounds a gate electrode  52  of the access field effect transistor. The dielectric liner  60  contacts a portion of the gate spacer  56  located on a source side, and does not contact a portion of the gate spacer  56  located on a drain side. The dielectric liner  60  does not contact the drain metal semiconductor alloy regions  62 . The access field effect transistor includes a gate structure containing a gate electrode  52  having a first width w 1  (See  FIG. 10 ) between a pair of vertical parallel sidewalls, and a gate metal semiconductor alloy region  64  having a second width w 2  (See  FIG. 10 ) that is lesser than the first width w 1 . 
         [0063]    Referring to  FIG. 12 , a first variation of the exemplary semiconductor structure according to an embodiment of the present disclosure can be derived from the exemplary semiconductor structure of  FIG. 8  by omitting the processing steps of  FIG. 9 , and by performing the processing steps of  FIGS. 10 and 11 . In this case, the dielectric liner  60  contacts sidewalls of the drain metal semiconductor alloy regions  62 . The sidewalls of each stressor structure  3 E can be vertically coincident with sidewalls of the overlying drain metal semiconductor alloy region  62 . 
         [0064]    Referring to  FIG. 13 , a second variation of the exemplary semiconductor structure according to an embodiment of the present disclosure can be derived from the exemplary semiconductor structure of  FIG. 8  by performing the processing steps of  FIG. 9  with the modification that the sidewalls of the patterned photoresist layer  77  are formed between a vertical plane W 1  including a sidewall of a gate electrode  52  that is proximal to a source region  3 S and another vertical plane W 2  including an outer sidewall of the dielectric liner  60  that overlies the source region  3 S. Subsequently, the processing steps of  FIGS. 10 and 11  are performed. In this case, each gate metal semiconductor alloy portion  64  can laterally extend from one sidewall of the gate electrode  52  to another sidewall of the gate electrode  52 , and thus, can have the first width w 1 . (See  FIG. 10 .) The entire top surface of each gate electrode  52  can be in contact with a bottom surface of a gate metal semiconductor alloy region  64 . 
         [0065]    Referring to  FIG. 14 , a third variation of the exemplary semiconductor structure according to an embodiment of the present disclosure can be derived from the exemplary semiconductor structure or any previous variations therefrom by performing an additional etch process after the processing steps of  FIG. 7  and before the processing steps of  FIG. 8  to alter the shape of the cavities  3 C. For example, a crystallographic etch process or an isotropic etch process can be employed to widen, deepen, and/or shape the cavities  3 C. Subsequently, the processing steps of  FIGS. 8 ,  9 ,  10 , and  11  can be performed. In this case, the stressor structures  3 E can be formed in a shape that can optimize the unilateral stress applied to the body regions  3 B of the access transistors. 
         [0066]    The asymmetric stress applied to the body region  3 B of each access transistor has the benefit of providing an increased leakage current only between the body region  3 B and the drain region  3 D, while not increasing leakage current between the body region  3 B and the source region  3 S. Thus, the source leakage current can remain at an insignificant level, while the increased drain leakage current rapidly increases the voltage of the body region  3 B toward the voltage of the drain region  3 D immediately prior to turning on the gate electrode  52  of the access transistor. The effect of changing the voltage of the body region  3 B toward the voltage at the drain region  3 D (which is a “high” voltage that can cause an on-current to flow as soon as the gate electrode  52  is turned on) has the effect of lowering the threshold voltage of the access transistor, and speeding up the turn-on operation of the access transistor and increasing the on-current of the access transistor once the access transistor is turned on. 
         [0067]    While the disclosure has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Each of the embodiments described herein can be implemented individually or in combination with any other embodiment unless expressly stated otherwise or clearly incompatible. Accordingly, the disclosure is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the disclosure and the following claims.