Abstract:
A highly accurate system to measure the value of a capacitor using proportionality against a time base reference. The capacitor under test is linearly sequentially charged in three discrete steps yielding integrated net neutral charge as well as a delay for discharging dielectric absorption during each measurement cycle.

Description:
FIELD OF THE INVENTION 
     This invention relates to capacitance measuring devices, generally, and in particular to devices for measuring the capacitance in a material-sensing probe. 
     BACKGROUND OF THE INVENTION 
     There are a variety of uses of capacitance measuring devices. One use in particular relates to detection of material levels (such as, for example, fluid in a tank). In these applications, a capacitance measuring probe is disposed in a material-containing vessel. The vessel and the probe are at different potentials so as to form a capacitor therebetween. The air and material contained in the vessel act as dielectrics. As the material level changes, so does the capacitance between the probe and the vessel. 
     Capacitance is normally measured using one of the following parameters: (a) differential impedance or admittance; (b) phase difference; or (c) frequency (or time), based on capacitive reactance. 
     The differential impedance technique is based on the generalized impedance formula: ##EQU1## To use this technique, two parallel systems are established, each having identical drive frequency, drive amplitude, resistance and inductance. One system includes a reference capacitor of known value. The other system contains the capacitor which is to be measured. Thus, the only difference between the systems is capacitance. The output of the system with the known reference capacitor is compared to the output of the system with the unknown capacitance to determine a voltage or current differential. In accordance with Ohm&#39;s Law (v=iZ), the voltage (or current) differential is proportional to the values of capacitance. 
     One drawback to this system is that exact control and matching of inductances is difficult. Therefore, systems based on this principle, while very rugged, tend to have moderate overall accuracies (i.e., an error of approximately between one and three percent). 
     The phase difference technique is based on the capacitive reactance formula: ##EQU2## To use this technique, two parallel systems are established, each with identical drive frequency and drive phase. One system includes a reference capacitor of known value. The other system contains the capacitor which is to be measured. Thus, the only difference between the systems is capacitance. The different capacitance causes the system&#39;s outputs to have different phase angles. The difference of phase angles is theoretically proportional to the values of capacitance. Unfortunately, a phase system with a linear relationship between capacitance and phase angle can be realized only with difficulty, and overall accuracy tends to be poor. 
     The frequency and time-based techniques are based on the generalized extension of Maxwell&#39;s electromagnetic theory: 
     
         v=λf 
    
     Under this equation, frequency of repetitive waveforms is the inverse of wavelength (because velocity remains constant for a given set of propagation conditions). For a given time constant, 
     
         τ=RC, 
    
     the voltage Vc across a capacitor that is subjected to a charging voltage V is: ##EQU3## and the voltage across a discharging capacitor that is initially at voltage V is: ##EQU4## Reversing the charge and discharge equations allows substitution of current for voltage. The curves generated by the above equations are of exponential form and extend to asymptotes, never fully converging. 
     By establishing an electronic oscillator or multivibrator which uses capacitive reactance as the variable frequency-determining element, a proportionality is established between the value of the capacitor and the resultant frequency or wavelength. Integrated circuit astable and monostable circuits (such as the 555 timer) often use this principle, and have been used to measure capacitance. 
     Typical gating for these forms of measurement is some form of comparator. Since waveforms are either exponential or transcendental (i.e., constantly varying slope), fixed comparator propagation delays contribute to errors. Frequency based systems also suffer from nonsynchronous gating, resulting in a±1 count errorband. 
     For use in (industrial) metrology systems, the symmetrical bipolar waveforms of sinusoidal oscillators are preferable. Typical pulse mode and astable type systems generate asymmetrically polarized waveforms which cause plating with certain chemical (i.e., ionic) dielectrics. Systems which A.C. couple (via a very large capacitor) to the sensed dielectric are also common. These charges are never totally in balance, resulting in plating. 
     Since frequency is directly proportional to capacitive reactance and inversely proportional to capacitance, a direct reading instrument based on frequency tends to be complex (usually requiring digital division). Time based systems are relatively simple due to direct scaling proportionality. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide a highly accurate time-based system to measure the value of a capacitor. In accordance with the invention, the capacitor under test is subjected to a measurement cycle, the period of which defines a predetermined base reference time. During each measurement cycle, the capacitor is subjected to a charge-discharge-charge cycle yielding integrated net neutral charge. The duration of the charge-discharge-charge cycle is compared to the reference time to determine capacitance. At the conclusion of the charge-discharge-charge cycle, the capacitor is shunted or &#34;clamped&#34; to a reference ground for the remaining duration of the measurement cycle. This shunt or &#34;dwell&#34; time provides a delay for discharging dielectric absorption during each measurement cycle. 
     The charging of the capacitor is linear with respect to time. To create a linear charging (discharging) slope with a capacitor ##EQU5## is used by maintaining ΔQ/Δt=k (k depends on range of capacitance to be measured) for any state of capacitor charge. Constant charge accumulation yields constant capacitor voltage amplitude change, therefore a linear slope. Practical realization is a positive and a negative constant current source that can be switched to the capacitor at appropriate charge level intervals. To minimize dielectric absorption effects a shunt is applied to the capacitor as a portion of each measurement cycle. 
     In one embodiment, a capacitance measuring device generates an output signal having a time duration that is a linear function of the capacitance being measured. The device includes two constant current sources of opposite polarity. The current sources provide linear charging of the capacitor at identical rates. The capacitor being measured has one electrode coupled to a reference ground, and the other coupled to a sensing lead. A plurality of comparators (or other suitable voltage sensors) are coupled to the sensing lead and a resistor network to detect the voltage level across the tested capacitor. 
     A control subsystem is responsive to the voltage sensors. The control subsystem initially couples the sensing lead to the first current source to charge the capacitor to a first predetermined voltage. When the capacitor has reached the first predetermined voltage, the control subsystem couples the sensing lead to the second current source to charge the capacitor to a second predetermined voltage. The second predetermined voltage is opposite in polarity to the first predetermined voltage, but is preferably equal in magnitude. Thus, the ground reference voltage is intermediate the first and second predetermined voltages. 
     When the capacitor attains the second predetermined voltage, the control subsystem couples the sensing lead back to the first current source to charge the capacitor to the ground reference voltage. When the capacitor reaches the ground reference voltage, the charge-discharge-charge cycle is complete. The control subsystem couples the sensing line to the reference ground to clamp the capacitor to ground for the remaining duration of the measurement cycle (i.e., dwell time). The time to complete the charge-discharge-charge cycle as a percentage of the reference time is proportional to the capacitance. 
     The control subsystem can be constructed in a variety of ways. The preferred technique is based on a counter. Other control techniques can be used. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a capacitance measuring device in accordance with the invention; 
     FIG. 2 is a timing diagram illustrating the operation of the device shown in FIG. 1; and 
     FIG. 3 is a fluid measuring system which employs the capacitance measuring device shown in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 illustrates a device 10 for measuring the capacitance of a capacitor C x  having plates 12 and 14. Capacitance measuring device 10 includes a sensor line 16 which is coupled to probe plate 12 of measured capacitor C x , a positive current source 18, a negative current source 20, and a reference ground 22. Current sources 18 and 20 are mirror sources of opposite polarity and equal amperage. Sensor line 16 is selectively coupled to ground 22, current source 18, and current source 20 by switches S0, S1 and S2, respectively. As explained below, switches S0-S2 are actuated via control lines A 0  -A 2  respectively by a control subsystem 24. Each switch S0-S2 remains open until its respective control line is asserted. Plate 14 of capacitor C x  is connected to a ground 27, which is at the same potential as reference ground 22. 
     Measuring device 10 calculates the capacitance of capacitor C x  during a reference time (or &#34;measurement cycle&#34;) that is determined by the period of an external master clock signal SYSCLK, discussed below. During the measurement cycle, device 10 subjects the measured capacitor to a linear charge-discharge-charge cycle which includes three discrete stages, discussed below in greater detail. The time to complete the charge-discharge-charge cycle is compared to the reference time to determine the capacitance of capacitor C x . The process is repeated for continuous monitoring of capacitance. 
     In charging measured capacitance C x , one complete linear triangle wave is used. The desired characteristics of the waveform are described using the general slope equation y=mx+b. Offset [b] must be equal to 0 (i.e. reference ground 22) to ensure symmetrical polarities yielding net integration of zero charge to prevent polarization and potential plating. The slope [m] must be linear at all points to negate the variability of propagation delays. Its absolute abscissa referenced value in all quadrants must be inversely proportional to the measured capacitor (directly propotional to capacitive reactance). During the detection cycle, the capacitor C x  is initially discharged by closing switch S0 to couple sensor line 16 to reference ground 22. Then, capacitor C x  is charged to a predetermined capacitor C x  reaches this positive voltage, capacitor C x  is positive voltage level (such as +5 V) by closing switch S1 to couple sensor line 16 to positive current source 18. When discharged to a predetermined negative voltage (such as -5 V) by closing switch S2 to couple sensor line 16 to negative current source 20. When capacitor C x  reaches this negative voltage, capacitor C x  is charged to the reference ground 22 by closing switch S1 to couple sensor line 16 to positive current source 18. When capacitor C x  reaches the reference ground, it is clamped to ground by closing switch S0. Capacitor C x  remains clamped to ground until the beginning of the next measured cycle (i.e., the next pulse of master clock signal SYSCLK). 
     The desired opening and closing of switches S0-S2 is achieved by means of control subsystem 24. Control subsystem 24 features a system counter 26 and three voltage sensing comparators 28, 30 and 32. System counter 26 has five outputs Q 0  through Q 4 , along with RESET and CLOCK inputs. System counter 26 operates like a ring counter in that only one output may be high at any given time. When the RESET input goes high, system counter 26 sets output Q 0  to high, and outputs Q 1  -Q 4  to low. System counter 26 then sequentially sets one (and only one) of the outputs Q 1  through Q 4  high each time the CLOCK input is strobed. 
     Output Q 0  is coupled to an external signal OUTPUT and switch control line A 0 . The OUTPUT signal is discussed below in connection with the dynamic operation of device 10. Switch control line A 0  closes switch S 0  during the time the clock output Q 0  is asserted. Clock output Q 1  is coupled via an OR gate 34 to line A 1  so that switch S1 is closed when output Q 1  is asserted. Output Q 2  is coupled to line A 2  so that switch S2 is closed when output Q 2  is asserted. Output Q 3  is coupled to OR gate 34. As explained above in connection with output Q 1 , the output of OR gate 34 is coupled to line A 1  to close switch S1 when either output Q 3  or Q 1  is high. Output Q 4  is coupled via an OR gate 36 to the RESET input. Thus, when output Q 4  is high, system counter 26 is reset. 
     An externally generated master reset signal INIT is connected to the RESET input of counter 26 through OR gate 36. OR gate 36 allows both master reset signal INIT and output Q 4  of system counter 26 to control the return to the initial state. Master reset signal INIT is generated when the system is being prepared for operation, such as, for example, at initial power up. Otherwise, the process automatically resets at the conclusion of each charge-discharge-charge cycle when output Q 4  is asserted as explained above. 
     The period of the external master clock signal SYSCLK defines the time reference. Master clock signal SYSCLK is gated through an OR gate 38 to the CLOCK input of system counter 26, so that each pulse of master clock SYSCLK increments system counter 26. 
     A resistive divider network composed of R1, R2, R3 and R4 establishes a positive reference voltage 40, a ground reference 42, and a negative reference voltage 44, as illustrated in FIG. 1. (Ground references 22, 27 and 42 are isopotential). Reference voltages 40 and 44 should be equal in magnitude (5 V) and opposite in polarity. 
     The output of first comparator 28 is high when sensor line 16 is more positive than positive reference voltage 40. The output of third comparator 32 is high when sensor line 16 is more negative than the negative reference voltage 44. The output of second comparator 30 is high when sensor line 16 crosses ground reference 42. The output of second comparator 30 is enabled or disabled by output Q 3  of the system counter 26 through an AND gate 46. 
     All three comparators 28, 30 and 32 are connected without any hysteresis feedback for optimizing switching points and times. This is possible since at first switching the effectiveness of each is negated as charging direction is changed at that point in time. For propagation delay equalization, two buffers 48 are added to the outputs of comparators 28 and 32, respectively, effectively equalizing the delay through AND gate 46. 
     Suitable components for constructing the foregoing device 10 are set forth below. The preferred current sources 18 and 20 are disclosed in U.S. patent application Ser. No. 08/122,212 entitled &#34;Bipolar Tracking Current Source/Sink With Ground Clamp&#34; and filed concurrently herewith (the disclosure of which is hereby incorporated by reference in its entirety). 
     
         ______________________________________Supply voltages         ±7 VdcSystem counter (26)     CD4017BC2 input OR gate (34)    CD4071BC2 input AND gate (46)   CD4081BC4 input OR gate (38)    CD4072BCAnalog switches (S0-S2) CD4066BCOperational amplifier (28, 30, 32)                   LM308Base reference time     1 mSMaster clock signal     CD528BCResistors R1, R4        2KΩResistors R2, R3        5KΩ______________________________________ 
    
     The dynamic operation of capacitance measuring device 10 is illustrated n the timing diagram of FIG. 2. For clarity, lines (a) through (i) of FIG. 2 illustrate the following signals: 
     (a) Master clock 50 
     (b) Voltage waveform of capacitor C x   
     (c) Q 0  of system counter 26 
     (d) Q 1  of system counter 26 
     (e) Q 2  of system counter 26 
     (f) Q 3  of system counter 26 
     (g) Q 4  of system counter 26 
     (h) A 1  switch control line 
     (i) Charging current waveform of sensor line 16 
     The outputs of comparators 28, 30, 32 are connected via OR gate 38 to the CLOCK input of system counter 26. As explained above, counter 26 increments each time the CLOCK input is strobed. Thus, system counter 26 increments whenever an output from one of the three level sensing comparators 28, 30 and 32 goes high. As explained above, master clock signal SYSCLK is also gated through the OR gate 38 to the CLOCK input of system counter 26. Master clock signal SYSCLK establishes the base reference time for the entire measuring cycle, and provides an initial clock pulse to start the operation. 
     As best seen in lines (a) and (b) of FIG. 2, the entire charge-discharge-charge cycle occurs during the measuring cycle (i.e., during interval between pulses of master clock signal SYSCLK). This interval is set to 1 mS (for example) to ensure that it is longer than the expected duration of the charge-discharge-charge cycle. This provides a dwell line during each measurement cycle where the sensor line 16 is shunted (or &#34;clamped&#34;) to reference ground 22. 
     The temporal duration of the charge-discharge-charge cycle is determined with reference to output Q 0  of the system counter (available externally as the OUTPUT signal). Output Q 0  is illustrated in line (c) of FIG. 2. The duration of the charge-discharge-charge cycle is compared to the time reference (i.e., the period between clock pulses from the master clock signal SYSCLK) to establish the proportionality for determining the value of the measured capacitor C.sub. x. For example, if the base reference time of  1  mS corresponds to a capacitance value of 100 pF, then a charge-discharge-charge cycle that lasts is 0.75 mS indicates a capacitance value of 75 pF. 
     Referring to FIG. 2, at time T 0  (before a measurement cycle begins) sensor line 16 is clamped to the reference ground 22 to minimize the dielectric absorption error and standardize the starting condition. Since sensor line 16 is clamped to reference ground 22, the outputs of comparators 28 and 32 are low. The zero crossing detector comparator 30 is also low because its output is disabled by AND gate 46 (Q 4  of system counter 26 is low). Clamping is achieved by closing analog switch SO by output Q 0  of system counter 26. System counter 26 can have one, and only one, output high at any point in time. Therefore, current sources 18 and 20 are not connected to the sense line 16 by the analog switches S1 and S2 at time T 0 . 
     At time T 1 , counter 26 receives a pulse from master clock signal SYSCLK. System counter output Q 0  goes low, opening switch S0. Simultaneously, output Q 1  goes high and (via OR gate 34) causes switch S1 to close. Lines (c) and (d) of FIG. 2 illustrate the outputs Q 0  and Q 1  of the system counter 26. The closing of switch S1 connects positive current source 18 with measured capacitor C x  (via sensor line 16), allowing the positive current source 18 to charge the measured capacitor C x  towards predetermined positive reference voltage 40 (established by resistors R 1  and R 2  as illustrated in line (b) of FIG. 2. At time T 2  (shown in FIG. 2), measured capacitor C x  (and sensor line 16) is charged to positive reference voltage 40. The output of first comparator 28 goes high, pulsing the CLOCK input of system counter 26 (via 0R gate 38). As explained above, this causes counter 26 to increment. 
     When system counter 26 increments at time T 2 , outputs Q 1  and Q 2  simultaneously reverse states, opening switch S1 and closing switch S2. (Line (e) of FIG. 2 displays output Q 2  of system counter 26.) When switch S2 is closed, negative current source 20 provides charging current to measured capacitor C x  and the sense line 16. Measured capacitor C x  begins to discharge toward negative reference voltage 44 established by resistive divider network R3 and R4. The (dis)charging continues in a linear fashion until measured capacitor C x  reaches negative reference voltage 44 at time T 3  (shown in FIG. 2). The output of third comparator 32 goes high, pulsing the clock input of system counter 26 through OR gate 38. As explained above, this causes counter 26 to increment. 
     When system counter 26 increments at time T 3 , outputs Q 2  and Q 3  reverse states. Output Q 2  goes low, opening switch S2, thereby disabling negative current source 20. Simultaneously, output Q 3  goes high, closing switch S1 (via OR gate 34), and enabling second comparator 30 (via AND gate 46). The closing of switch S1 enables positive current source 18. The polarity reverses and the measured capacitor C x  begins to (dis)charge towards ground reference 22. As illustrated at line (b) of FIG. 2, at time T 4 , the voltage of sensor line 16 crosses the ground reference level 42. The output of second comparator 30 goes high, pulsing the CLOCK input to increment and system counter 26. 
     When system counter 26 increments at time T 4 , output Q 3  goes low and output Q 4  goes high. Output Q 4  resets the system counter 26 (via OR gate 36 and the RESET input). Output Q 0  returns to high (as seen in line (c) of FIG. 2), thereby closing switch SO to clamp measured capacitor C x  to reference ground 22. This completes one bipolar charge-discharge-charge cycle of the measured capacitor C x , and maintains the isopotential clamp. 
     Another charging sequence will begin at time T 5 , when the next master clock pulse SYSCLK is received by the system counter 26. The duration of the charge-discharge-charge cycle is represented by the period between times T 1  and T 4 , during which output Q 0  is low (as shown in line (c) of FIG. 2). This period is the sum of the durations of three discrete charge events that occur during the charge-discharge-charge cycle, illustrated respectively as reference numerals 50, 52 and 54 in FIG. 2. The entire charge-discharge-charge cycle must occur between two sequential clock pulses of master clock signal SYSCLK, which defines the base time reference (i.e., between times T 1  and T 5  of FIG. 2). As part of the design, current amplitude supplied by the current sources 18 and 20 (as well as the frequency master clock signal SYSCLK) must be balanced against the expected range of capacitance values to be measured so that the charge-discharge-charge cycle is completed within the base time reference. 
     The charge-discharge-charge cycle should complete early enough to provide a dwell time wherein the measured capacitor C x  remains charged to reference ground 22 until the next pulse of master clock signal SYSCLK. Dwell time (as illustrated in FIG. 2) occurs between times T 4  and T 5 . Dwell time should be at least approximately nine percent by the base reference time. An adequate dwell time allows device 10 to measure a range of capacitances. The range can be adjusted by changing the rate of the constant current sources 18 and 20. 
     It is important that the integrated net charge imposed on the measured capacitor be neutral. Accordingly, the current sources should be of equal current amplitude. Also, the positive and negative voltage references should be of equal magnitude (albeit opposite polarity). Finally, the charging of the capacitor must be linear with respect to time. Linear charging allows the positive and negative portions of the capacitor&#39;s voltage waveform to sum to a net neutral charge. 
     The ratio of the duration of output Q 0  (available externally as the OUTPUT signal) to the base reference time is proportional to the measured capacitance. Thus, if the base reference time is preserved, the OUTPUT signal is capable of being interfaced to analog circuitry, time base referencing, digital computational or other final readout circuitry. 
     There are a variety of uses of capacitance device 10. One particularly useful application relates to detection of material levels (such as, for example, fluid in a tank). Referring to FIG. 3, a capacitance measuring probe 56 is disposed in a vessel 58 containing a material 60. The vessel and the probe are at different potentials so as to create a capacitance therebetween. This capacitance is represented by the capacitor symbol 62 of FIG. 3. The air and materials contained in the vessel act as dielectrics. As the material level changes, so does the capacitance between the probe and the vessel. In accordance with the invention, probe 56 is coupled to sensor line 16, and the vessel to reference ground 27. The capacitance between probe 56 and vessel 58 is then measured as explained above to determine the level of material in the vessel. A suitable probe is disclosed in U.S. patent application Ser. No. 08/122,849 entitled &#34;High Pressure, Leak Resistant, Explosionproof Capacitance Probe&#34;  filed concurrently herewith (the disclosure of which is hereby incorporated by reference in its entirety).