Abstract:
A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention generally relates to computer architecture.  
           [0003]    2. Description of Related Art  
           [0004]    Conventional computer architecture typically includes a single bus that couples a microprocessor with memory and Input/Output (I/O) devices. The bus carries a number of electrical signals between the various components of the system. The speed of the signals is somewhat dictated by the length of the bus. High speed signals are difficult to send over long distances, because of the cross inductance between bus lines. Generally speaking, higher frequencies require shorter bus lines.  
           [0005]    I/O ports are typically located on a separate card, whereby the signals must travel through connectors and various printed circuit boards to communicate with of the processor. This limits the speed of the bus and degrades the performance of the processor. The bus speed also controls the rate of data transfer between the processor and memory devices. It is generally desirable to have high data rates between the processor and memory. Usually an increase in data rate requires a larger number of pins on the chip. Adding pins enlarges the size of the chip, increasing the cost and complexity of the same. It would therefore be desirable to have a high speed memory bus that would provide a high data rate with a minimal amount of pins. It would also be desirable to have an architecture that would allow such a high speed bus to operate independently of the I/O devices of the system.  
           [0006]    Microprocessors are constantly being redesigned to run at faster clock rates. Usually the development of faster CPU devices require the addition of hardware and/or software, so that the existing system can interface with the new processor. This is particularly true for the interface between the processor and the bus, which contains existing I/O devices that run at the slower data rate. Recent systems have incorporated various levels of cache memory to compensate for the slow data rate between the processor and main memory. Additionally, cache requires additional components, thereby increasing the cost and complexity of the system. It would therefore be desirable to have an architecture that would allow faster processors to be installed into existing systems, without having to drastically change the existing hardware and software of the system.  
         SUMMARY OF THE INVENTION  
         [0007]    The present invention is a computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of high speed dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus greatly increases the performance between the processor and memory devices. High speed processors can be substituted or added to the system, without drastically modifying the existing memory and bus. High speed I/O devices such as graphic controllers can also be added to the bus to improve the performance of the controller.  
           [0008]    The high speed bus may be used with a conventional bus, so that conventional devices (e.g. I/O devices, system ROMs, etc.) can communication with the processor using existing bus protocols. The dual bus arrangement allows high speed data rates between the processor and memory to occur, while slower devices communicate with the processor on the conventional bus. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows data to be transferred between the busses. For example, if the conventional bus is connected to I/O devices, I/O data can be diverted directly to the high speed bus and memory. Conversely if the high speed bus contains an I/O device, the device can communicate with the conventional bus.  
           [0009]    The present invention includes means to incorporate cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both the conventional bus and the separate high speed bus.  
           [0010]    Therefore it is an object of this invention to provide a high speed low pin bus between a processor and system memory.  
           [0011]    It is also an object of this invention to provide a high speed memory bus that allows faster processors to be substituted or added, without changing the bus or memory structure.  
           [0012]    It is also an object of this invention to provide a high speed memory bus that can operate with a conventional bus.  
           [0013]    It is also an object of this invention to provide a method for allowing I/O devices to be placed on both a high speed bus and a conventional bus.  
           [0014]    It is also an object of this invention to provide a cache on a high speed memory bus.  
           [0015]    It is also an object of this invention to provide a multiple bus architecture that allows devices on one bus to communicate with devices on the other bus.  
           [0016]    It is also an object of this invention to provide a computer architecture that decouples the performance of the CPU to memory path from the CPU to I/O path.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    The objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, wherein:  
         [0018]    [0018]FIG. 1 is a schematic of a system of the present invention, showing two busses connected to a microprocessor;  
         [0019]    [0019]FIG. 2 is a schematic of a high speed bus line of the present invention;  
         [0020]    [0020]FIG. 3 is a schematic of a high speed DRAM with an internal cache;  
         [0021]    [0021]FIG. 4 is a schematic showing a number of DRAM&#39;s on a high speed bus;  
         [0022]    [0022]FIG. 5 is a schematic showing a processor interface connected to a pair of busses;  
         [0023]    [0023]FIG. 6 is a schematic showing a dual bus architecture with an I/O device on a high speed bus;  
         [0024]    [0024]FIG. 7 is a schematic showing a single high speed bus with both I/O and memory devices;  
         [0025]    [0025]FIG. 8 is a schematic showing a high speed bus connected to a conventional bus by a bridge;  
         [0026]    [0026]FIG. 9 is a schematic showing I/O devices on each bus of a dual bus architecture;  
         [0027]    [0027]FIG. 9 a  is a schematic of the CPU interface;  
         [0028]    [0028]FIG. 10 is a schematic showing a cache located on a high speed memory bus;  
         [0029]    [0029]FIG. 11 is a schematic showing an alternate embodiment of a cache on a high speed memory bus;  
         [0030]    [0030]FIG. 12 is a schematic showing two CPU&#39;s connected to a bus that contains a DRAM with an internal cache.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0031]    Referring to the drawings more particularly by reference numbers, FIG. 1 shows a schematic of a computer system  10  of the present invention. The system  10  includes a central processing unit (CPU)  12  that is coupled to an I/O device(s)  14  by a first bus  16 . The I/O device(s)  14  may include a printer, keyboard, screen or other conventional computer components that are connected to a microprocessor  12 . The first bus  16  is a conventional system bus that may contain 16, 32 or 64 data lines (2, 4 or 8 byte data transfer), along with other additional address, control and power lines, as is known in the art. The first bus  16  typically transfers information at a first predetermined clock rate.  
         [0032]    The processor  12  is coupled to a memory device(s)  18  by a second bus  20 . The memory device  18  typically contains system memory for the computer  10 . FIG. 2 shows a preferred embodiment of the second bus  20 . The bus  20  has 9 data lines, which allows a byte of data plus a horizontal parity bit to be transferred during each clock cycle. Addresses and data are transferred in serial byte form. Unless otherwise distinguished, data will include both instruction and data. The bus  20  also has an ACK/NACK line to allow the memory device to transmit an ACK or NACK signal, along clock, power and ground lines. In the preferred embodiment, data is transferred on the second bus 500 Mbytes/sec (2 nanosecond clock).  
         [0033]    The memory device  18  is preferably a dynamic random access memory (DRAM) chip. A DRAM is preferred because of the large memory content characteristics of the device. The memory device  18  is preferably placed in close physical proximity to the processor. By placing the memory and processor close together, a reliable very high speed bus can be established, which is not susceptible to errors due to line noise, etc. The second bus  20  provides a direct line between the processor  12  and memory  18 . In this manner, the processor  12  to memory  18  protocol can be constructed independently from the rest of the computer. The second bus  20  allows a high speed processor  12  to be coupled to a high speed memory device  18  without being impeded by the speed of the I/O devices  14  or first bus  16 .  
         [0034]    As shown in FIG. 3, the DRAM may have two main blocks of memory  22   a  and  22   b,  each containing a 36×256×256 array of memory cells. Each block has a cache  24   a  and  24   b,  that stores a row of data from the main memory block. The DRAM has a control circuit  26  to provide memory logic and a buffer  28  that provides an interface with the second bus  20 . Such a memory device has been developed by Rambus, Inc.  
         [0035]    The protocol of the second bus  20  and memory device  18  includes a request packet. The request packet includes the addresses that are being accessed within the memory device. The request packet also contains a start bit to indicate the start of the request packet and coded signals that indicate whether the transaction is a memory read or a memory write, and how many bytes of data are requested. The DRAM constantly monitors the second bus  20  for a request packet. If the addresses are in the cache of a DRAM, the DRAM provides an ACK signal on the ACK/NACK line and then either reads or writes the data. If the DRAM has the addresses but the addresses are not within cache, the DRAM will provide a NACK signal and perform an internal cache fetch of the requested address from main memory.  
         [0036]    As shown in FIG. 4, the system memory  18  may have a number of DRAMs all connected parallel to the second bus  20 . Because each memory device contains a large cache line of available data, the probability of a single DRAM cache line containing a requested address is quite high. This allows the DRAMs to operate independently of each other. Thus when an address request misses (not in cache) and the DRAM cache internally fetches the data for the new request, the data in the other DRAM caches are left undisturbed. The result is a large number of cache lines waiting to be accessed, greatly improving the probability of an address request being in one of the DRAMs caches.  
         [0037]    As shown in FIG. 5, the processor  12  can be provided with a bus interface  30  that allows the processor  12  to communicate with the busses  16  and  20 . The bus interface  30  contains a first unit  32 , a second unit  34  and a third unit  36 . The first unit  32  is connected to the first bus  16  and provides a conventional interface between the processor  12  and the I/O devices  14 . The first unit  32  may contain a buffer to store data and means to allow the processor  12  to communicate with the protocol of the first bus  16 .  
         [0038]    The third unit  36  primarily serves the same function for the second bus  20 . The third unit  36  has logic circuitry (not shown) which modifies the request from the CPU to conform to the protocol of the second bus  20 . The third unit  36  generates a request packet that is sent to memory. The request packet includes the addresses requested, device id, and coded signals described above.  
         [0039]    In operation, the CPU generates a request for memory. The third unit  36  generates a request packet which is sent to memory  18  on the second bus  20 . If the transaction is a memory write, the third unit  36  will also send the data to be written. The DRAMs decode the device id. If the id matches, the DRAM will further decode the addresses requested. If the requested addresses are within cache, the DRAM will send an ACK signal to the third unit  36 . If the transaction is a read, the DRAM will send the requested data onto the second bus  20 .  
         [0040]    If the address are within the DRAM but not within the DRAM&#39;s cache, the DRAM sends a NACK signal to the third unit  36  and then transfers the requested data from main memory into cache. The third unit  36  then resubmits the same request packet to memory. The cache now has the data which is sent to the third unit  36 . The memory device  18  will typically transmit data at a higher rate than the rate at which the processor  12  reads the data. The third unit  36  will therefore have a buffer which stores the data as it is received from memory. With a byte wide second bus  20 , the third unit  36  will store each byte of data as it is received from memory. The processor  12  can then retrieve the data at its leisure. Likewise, when the processor writes to memory, the data can be stored within the buffer, while the third unit  36  sends the data onto the second bus  20 , byte by byte.  
         [0041]    One of the functions of the second unit  34  is to direct address request from the CPU  12  to the appropriate bus. When the processor  12  writes data, the second unit  34  looks at the addresses being written and directs the data to the appropriate bus. For example, the computer can be mapped so that memory is given certain designated addresses (0-79K) and I/O is given another range of addresses (80K-119K). If the processor  12  sends out a packet to write addresses  64 - 128 , the second unit  34  will store and compare the first and last addresses in the address packet. The addresses are compared to a stored value that represents the line between memory and I/O. If the stored value is 80K, then all addresses less than the stored value are directed to the second bus  20 . Addresses equal to or greater than the stored value are directed to the first bus  16 . In the example above, because the addresses  64  and  128  are less than 80K, the address write packet is sent to memory on the second bus  20 . When the processor  12  sends out a read request, the second unit  34  again maps the request to the appropriate bus. The second unit  34  may also allow both busses to transfer data at the same time. For instance, while the processor  12  is writing data to I/O  14 , the memory device  18  can be writing data to the third unit  36  which stores the data until retrieved by the processor  12 .  
         [0042]    The second unit  34  can also direct request between the busses  16  and  20 . For example, submasters  38  and  40  may be connected to the first  16  and second  20  busses respectively. Submaster  38  may be a math coprocessor and submaster  40  may be a graphic controller. The coprocessor  38  may generate a read request which is provided onto the first bus  16 . The first unit  32  provides the request to the second unit  34 , which determines whether the requested addresses are located on the second bus  20 . If the requested addresses are on a device on the second bus  20 , the second unit  34  sends the request to the third unit  36 . The third unit  36  generates a read request packet that is sent onto the second bus  20 . If the addresses are within a DRAM, the cache ACK/NACK cycle is performed and the data is sent to the third unit  36  which transfers the data to the coprocessor  38  via the first unit  32 . Similarly when the controller  40  generates a request, the second unit  34  determines if the requested addresses are located on the first bus  16  and directs the request accordingly.  
         [0043]    Either the coprocessor  38  or controller  40  may have dedicated internal caches. When one of the submasters generates a write into the cache of the DRAM, the second unit  34  will invalidate the caches of the CPU and other submaster that also contains the write address. For example, if the graphic controller generates a DRAM cache write of addresses  0 - 15 , the addresses are also sent to the second unit  34  which initiates a cache invalidation cycle on the first bus  16 . Thus if the CPU cache or coprocessor cache contains the addresses  0 - 15 , those lines in the caches are invalidated. This prevents the other (sub)masters from processing invalid data from their internal cache.  
         [0044]    The second unit  34  is also capable of “rolling up” address request from the CPU  12 . A conventional CPU may establish a predetermined memory map that is incompatible with a dual bus system. For example, the conventional CPU may map the first 640K of memory to the DRAM&#39;s and the next block of addresses (640K-767K) to an I/O device. As shown in FIG. 6, the computer may have a dual bus architecture with the I/O device (640K-767K) placed on the second bus  20 . The system may also have memory on the second bus with 4.0 Mbytes of memory. It is not possible to leave a gap in the address range that the memory will respond to (0 to 4.0 Mbyte is this example), so the I/O device on the second bus  20  cannot be allocated the block of addresses 640-767K it would normally respond to on the second bus  20 . Instead the I/O device  60  it is allocated a new and otherwise unused block of addresses, typically above the memory on the second bus  20 . When the CPU generates a read request for addresses within the 640K-767K block, the second unit  12  of the present invention remaps the addresses for the I/O device to address locations above the memory of the DRAM. Using the above example, the second unit  12  may change the addresses associated with space 640K-767K to addresses associated with space 4.0-4.12 Mbytes. This remapping of addresses allows I/O devices to be located on the second bus in a manner which allows them to co-exist with any amount of memory devices without requiring any software changes. The “roll up” feature allows I/O devices to be added to a memory bus without changing the CPU mapping scheme.  
         [0045]    [0045]FIG. 7 shows a system where memory and I/O devices are both connected to the high speed second bus  20 , which may or may not coexist with the first bus  16 . The I/O device  14  is constructed to meet the protocol of the second bus  20 . In the alternative, the I/O device  14  may have an interface  38  that allows the device  14  to meet the protocol of the second bus  20 . The interface  38  being constructed to function in the same manner as the third unit  36 .  
         [0046]    The addition of an I/O device  14  on the high speed bus creates a means for providing high data rates between the device  14  and memory  18 . Such an arrangement is particularly useful when the I/O device is a graphics control card, wherein large bandwidths of data can be transferred between the devices  14  and  18 . The memory devices are preferably the cache DRAM&#39;s described above. The high probability of “hits” in the DRAM&#39;s cache, greatly increases the speed and performance of the graphic controller  14 .  
         [0047]    [0047]FIG. 8 shows another embodiment of the system, wherein the second bus  20  is coupled to the first bus  16  by a bridge  40 . System memory or a high speed I/O device (graphic controller) may be connected to the second bus. The bridge  40  functions in a similar manner to the third unit  36  in FIG. 5, serving to convert the data from the second bus  20  to meet the protocol of the first bus  14  and vice versa. Such an arrangement allows high speed memory or I/O devices to be added to existing computer systems through the second bus  20 , without drastically changing the microprocessor  12 .  
         [0048]    [0048]FIG. 9 shows another embodiment of the present invention, with I/O devices  50  and  60  on the first bus  16  and the second bus  20 , respectively. I/O device  60  may have an interface to match the protocol of the second bus  20 . When the processor  12  sends out a write packet, it sends the data onto both busses  16  and  20 . The I/O devices with the corresponding write addresses will then write the data from the bus. When the processor sends out a read request, the request is again sent out onto both busses. If I/O device  60  on the second bus  20  has the addressed data, the device  60  will send an ACK signal to the interface  30 . The interface contains a timer circuit that is coupled to a bus multiplexer. When the processor generates a request, the timer is activated and the bus multiplexer is set to receive data only from the second bus. The interface  30  then reads the data on the second bus  20  and ignores any data on the first bus  16 . If the device  60  on the second bus  20  does not have the addressed data, no acknowledge is sent before the timer expires. Upon expiration of the timer, the bus multiplexer switches to the first bus so that the interface  30  reads the data on the first bus  16 .  
         [0049]    The processor may send out a read request such that part of the request is located in I/O device  60  and the remainder of the request in device  50 . The CPU request is converted to a request packet as described above when sent to the second I/O device  60 . The request packet typically requests multiple bytes of data. Therefore the second I/O device will always send multiple bytes of data. Not all of the data bytes sent to the CPU  12  by the second I/O device  60  may be valid. The I/O device  60  on the second bus  20  then sends an enable code (typically a byte wide) which indicates to the processor  12  which bytes of the data package on the second bus  20  are valid. Each bit in the enable byte may correlate to each data byte. For example, if the data block is 8 bytes long, then each bit ( 0 - 7 ) of the enable byte may correspond to a corresponding byte ( 0 - 7 ) of data. The least significant bit within the enable byte may correlate to the first data byte, the most significant bit may correlate to the last data byte and so forth and so on. If the enable bit is a binary 0, then the corresponding byte may have valid data, a binary 1 may indicate invalid data. The processor  12  may then replaces all of the invalid bytes from the second bus  20  with the valid bytes from the first bus  16 .  
         [0050]    [0050]FIG. 9 a  shows a schematic for the interface  30  which allows invalid data on the second bus  20  to be replaced with valid data on the first bus  16 . The interface has a plurality of first buffers  62  that store the data from the first bus  16 . Each buffer  62  may store a byte of data. The interface  30  may also have a plurality of second buffers  64  that each store a byte of data from the second bus  20 . The output of each buffer is connected to a tri-state buffer  66 . The enable pin of the tri-state buffer  66  is connected to the output of an exclusive OR (XOR) gate  68 . The XOR gates  68  of the first bus  16  have an input connected to a stored binary 0. The XOR gates  68  of the second bus  20  have an input connected to a stored binary 1. The other inputs of the XOR gates are connected to a byte enable buffer  69  which stores the enable byte on the second bus  20 .  
         [0051]    In operation, the buffers  62  and  64  store all of the data from both the first bus  16  and second  20  bus, respectively. The CPU  12  is then provided with the correct data in accordance with the data bit string in the enable byte provided by the I/O device  60  on the second bus  20 .  
         [0052]    For example, the I/O device  60  may send 8 bytes of data, the first 4 bytes being valid, the subsequent 4 bytes being invalid. The I/O device  60  may then send an enable byte 00001111. The first 4 bits of the enable byte may correspond to the first 4 bytes of data. The 0&#39;s are provided to the XOR gates  68 , which enable the corresponding tri-state buffers to send the data stored in the second buffers  64  ( 0 - 3 ) to the CPU  12 . The 1&#39;s of the enable byte are XORed with the XOR gates  68 , so that the tri-state buffers  66  of the second buffers  64  are disabled and the tri-state buffers  66  of the first buffers  62  are enabled. The data from the first buffers  62  ( 4 - 7 ) is then provided to the CPU  12 .  
         [0053]    The byte enable format could be used with the ACK signal described above, wherein the processor will ignore the first bus if the I/O device  60  sends an ACK signal. If the ACK signal is not incorporated, the processor always reads both busses. If all of the bytes from the second bus are valid, then the processor does not replace any of the second bus data with the first bus data. The first bus is essentially ignored the same as if an ACK was given to the processor.  
         [0054]    [0054]FIGS. 10 and 11 show the incorporation of a cache  70  on a second bus  20  with high speed system memory devices. This embodiment may be incorporated with the dual bus architectures described above. The cache  70  typically includes high speed static RAMs that contain tags and data for a number of cache lines. The physical memory of the processor preferably contains the high speed DRAMs described above. In the first embodiment shown in FIG. 10, the CPU has two bus interfaces  72  and  74 . The first interface  72  is connected to cache  74 . The second interface is connected to the DRAM&#39;s  18 . Both interfaces preferably meet the high speed bus protocol described above. The cache  70  may also have an interface that meets the requirements of the bus protocol. The cache interface will therefore be capable of reading a request packet from the CPU interface and generating an ACK or NACK signal in response. The CPU  12  typically generates all initial requests through interface  72 .  
         [0055]    When the processor  12  generates a read request, the cache  70  decodes the addresses to determine if it contains the requested data. If the address is within cache  70 , the cache  70  sends an ACK signal to the processor  12  and the processor  12  reads the data. If the cache  70  does not have the data, the cache  70  will send a NACK signal to the processor  12 . The processor  12  will then resubmit the read request packet through the second interface  74 . The DRAM&#39;s  18  will then write the data to the processor  12 . The requested data may also be written into cache  70  through the first interface  72 . When the processor  12  issues a write, the data can be written to either the cache  70  alone, or to the cache  70  and system memory  18 . If the CPU  12  generates a write request and the cache  70  contains the address, but with different data (“a dirty cache miss”), the cache  70  will generate a busy ACK signal and send the modified data to the CPU  12 , which retransmits the same to the DRAM  18 . The CPU  12  then resubmits the write request, wherein the data is stored in cache  70 .  
         [0056]    [0056]FIG. 11 is another embodiment showing the DRAM&#39;s  18  and cache  70  both coupled to a single CPU interface  30 . The DRAM  18  is coupled to the interface  30  by a transceiver  78 . When the processor  12  sends out a read request, the cache  70  decodes the addresses to determine if it will respond. If the cache  70  has the requested data, it will send an ACK signal to the processor  12 . The ACK signal is also received by the transceiver  78  which prevents the DRAM from sending the data to the processor. If the cache  70  sends a NACK signal, the transceiver allows the DRAM to send the data to the processor  12 . The processor  12  will also write the data from the DRAM back into cache  70 . When the processor  12  sends a write package and the cache  70  sends an ACK signal to both the processor and the DRAM, the DRAM can either read the data with the cache, or the ACK signal can disable the DRAM so that it does not read the data.  
         [0057]    [0057]FIG. 12 shows another embodiment of the present invention, wherein there are two masters  80  and  82  connected to the high speed bus  20  and DRAM&#39;s  18  with cache, described above. The masters are typically CPU&#39;s that can each access the DRAM&#39;s  18  on the bus  20 . Each CPU has a bus interface  30  that generates a read request packet that is interpreted by the memory devices. The request packet may contain a lock bit which is either set (1) or not set (0). The masters constantly monitor the bus  20  to insure that another master has not sent a request packet with the lock bit set. Once a master sends a request with a set lock bit, the other master is prevented from making a request until the requesting matter submits a subsequent request with the lock bit not set. The lock bit allows a master to go through entire memory read and write cycles without corruption of the DRAM by another master.  
         [0058]    Although a dual bus architecture is shown and described, it is to be understood that the present invention may incorporate more than two busses or processors.  
         [0059]    While certain exemplary embodiments have been described in detail and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the present invention and that the invention not be limited to the specific arrangements and constructions shown and described, since various other modifications may occur to those ordinarily skilled in the art.