Abstract:
A signal regeneration circuit using first and second phase-locked loop (PLL) circuits each having a phase comparator, a loop filter and a voltage controlled oscillator (VCO) in which the phase of an input signal is shifted by a desired amount. The first PLL operates as an input signal frequency averaging means, and the second PLL operates to satisfy the final performance as a signal regenerative circuit based on the output of the VCO in the first PLL, thereby producing as a regenerative signal the output of the VCO in the second PLL. Thus, this signal regeneration circuit can regenerate a clear signal having no noise from an unclear input signal deeply immersed in noise.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a signal regeneration circuit which is used to regenerate an extremely weak original signal deeply immersed in noise. 
     2. Description of the Prior Art 
     A typical conventional signal regeneration circuit of this type has employed a phase-locked loop (referred to as a PLL). This PLL has necessitated the following two requirements, since the PLL should consider for the case that an original signal to be regenerated is likely to be modulated by noise and has more than two types of frequencies so that the original signal is included as a whole wide frequency band. 
     Firstly, since noise is superposed on the original signal and the original signal including a number of jitters should be processed, the loop band-width of the loop filter should be narrowed to be able to reduce the influence of the noise. Secondly, the pull-in range of the PLL should be sufficiently wide so as to be able to pull in the frequency even if the original signal is transferred from one frequency to other frequencies. 
     Concerning the first requirement, the reduction in the loop band-width can be solved by increasing the time constant of the loop filter of the PLL. Further, the increase in the pull-in range of the PLL of the second requirement is ordinarily solved by employing an edge trigger type phase frequency comparator (referred to as a PFC) for the phase comparator. Since this PFC can increase the pull-in range up to the lock-in range, the entire PLL can attain sufficiently wide pull-in range even if the loop band-width of the PLL is set to narrow width. 
     The PFC serves, as shown in (a) to (c) of FIG. 1, to detect the phase difference between two input signals R and S and to produce as an output signal Q having logic level &#34;HIGH&#34; and &#34;LOW&#34; pulses whose width is proportional to the phase difference, and operates to set the output signal Q to &#34;HIGH IMPEDANCE&#34; (the state that is neither logic level &#34;HIGH&#34; nor logic level &#34;LOW&#34;) during a period of time in which these two inputs R and S are in phase. For example, when the phase of the input signal R leads, the output signal Q becomes &#34;LOW&#34; at the rise of the input signal R, and the output signal Q becomes &#34;HIGH IMPEDANCE&#34; at the rise of the input signal S. When the phase of the input signal R, on the other hand, lags, the output Q becomes &#34;HIGH&#34; at the rise of the input signal S, and the output signal Q becomes &#34;HIGH IMPEDANCE&#34; at the rise of the input signal R. 
     Accordingly, if the input signal to the PFC lacks one or more pulses or includes excessive pulse or pulses, the PFC might invert the output signal Q immediately after the pulse irregularity of the input signal. In other words, if the input signal R lacks, as shown in (a) of FIG. 2, a pulse P 1 , the PFC operates in the same manner as the phase of the input signal R lags with respect to the phase of the input signal S (refer to (b) of FIG. 2), and as a result the output signal Q unfavorably becomes &#34;HIGH&#34; instead of becoming &#34;LOW&#34; (refer to (c) of FIG. 2). The output signal Q thus varied is applied to a voltage controlled oscillator (referred to as a VCO) through a loop filter. Since the VCO judges such an abrupt change in the output signal Q as a rapid change in the control voltage, the VCO regards the entire loop of the PLL as in a lock-out state, and operates to correct to hold in range. 
     If the input signal R includes an excessive pulse P 2  as shown in (a) of FIG. 3, the PFC operates in the same manner as the phase of the input signal R leads with respect to the phase of the input signal S (refer to (b) of FIG. 3), and as a result the output signal Q unfavorably becomes &#34;LOW&#34; instead of becoming &#34;HIGH&#34; (refer to (c) of FIG. 3). In this case, the VCO judges such an output signal Q thus varied abruptly as a rapid change in the control voltage, and accordingly regards the entire loop of the PLL as in a lock-out state, and operates to correct to hold in range. 
     The signal which lacks one or more pulses or includes an excessive pulse or pulses due to a chattering, etc. as described above can be frequently observed in a signal deeply immersed in an ordinary noise. However, if such a signal is inputted to a PLL, the PLL should frequently correct to hold in range as described above. As a result, the PLL cannot maintain the lock-in range in operation. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of this invention is to provide a signal regeneration circuit which can eliminate the aforementioned drawbacks and disadvantages of the conventional signal regeneration circuit and which is capable of regenerating a clear signal having no noise from an unclear input signal deeply immersed in a noise and thus unknown in any state. 
     A signal regeneration circuit according to this invention is constructed to comprise a first PLL which operates as an input signal frequency averaging means, and a second PLL which operates to satisfy the requirements as a signal regenerative circuit based on the output of a VCO in the first PLL, thereby producing the output of the VCO in the second PLL as a regenerative signal. Therefore, the first PLL employs as its phase comparator an exclusive OR circuit type or a flip-flop circuit type which serves to detect the phase difference between the input signal and the output of the VCO in the first PLL and to produce a pulse of one polarity corresponding to the phase difference, and attains a sufficient pull-in range to set a wide loop band-width capable of avoiding the influence of the temporary phase error between the input signal and the output of the VCO in the first PLL. Further, the second PLL is arranged to have narrow loop band-width so as to attenuate a noise superposed on the input signal and the PFC capable of providing the PLL with sufficiently wide pull-in range when the narrow loop band-width in comparison with that of the first PLL is set in the second PLL is employed as a phase comparator which receives the output of the VCO of the first PLL and the output of the VCO of the second PLL as comparison signals. 
     In this manner, the first PLL can produce a signal which becomes a pulse train that is corrected from the signal which lacks a pulse or includes an excessive pulse even if the signal includes a noise or a jitter (i.e., the frequency is averaged), and the second PLL which again pulls in the signal thus corrected as this pulse train, can produce a clear pulse signal which is stabilized in frequency and is excluded from the noise and the jitter. 
     Further, since the first PLL is set to a wide loop band-width which can attain sufficient pull-in range, the PLL can pull in the input signal over a wide frequency range and can stably lock in range. Further, since the second PLL is constructed to pull in the pulse train stabilized by the first PLL, the PLL can stably maintain the lock-in range. In other words, according to the signal regeneration circuit of the present invention, a clear pulse signal can be regenerated stably over a wide frequency range. 
     An embodiment of the invention will now be described in detail with reference to the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings: 
     FIGS. 1, 2, and 3 are timing diagram showing the input versus output signal characteristics of the PFC; 
     FIG. 4 is a block diagram showing an embodiment of a signal regeneration circuit according to the present invention; 
     FIGS. 5 and 6 are timecharts showing the input versus output signal characteristics of a phase comparator using an exclusive OR circuit; 
     FIGS. 7 and 8 are timecharts illustrating examples of the operation of the signal regeneration circuit according to the present invention; 
     FIGS. 9 and 10 are circuit diagrams of a lag-lead filter used in the signal regeneration circuit; and 
     FIGS. 11 and 12 are timecharts showing the operating characteristics of the lag-lead filter shown in FIGS. 9 and 10. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 shows one preferred embodiment of a signal regeneration circuit according to the present invention. 
     In FIG. 4, reference numeral 1 designates an input terminal, to which a signal deeply immersed in a noise is inputted. The signal inputted from the input terminal 1 is in turn inputted to a band pass filter (referred to as a BPF) 2, and is arranged to be a signal having only frequency components which are near to those of an original signal by means of the BPF. The output signal from the BPF is further inputted to a waveform shaping circuit 3, and is waveform-shaped to be a logic level signal of a first PLL 4. 
     This signal is then inputted to the first PLL 4. The output signal of the first PLL 4 becomes an input signal of a second PLL 5. The output signal of the second PLL 5 is outputted from an output terminal 6. 
     The first PLL 4 has a phase comparator 41, a loop filter 42 and a VCO 43. The signal outputted from the waveform shaping circuit 3 is applied to an input R1 of the phase comparator 41, is further applied through the loop filter 42 and the VCO 43, and is sequentially outputted to the second PLL 5. The output signal of the VCO 43 is fed back to the other input S1 of the phase comparator 41. The phase comparator 41 employs the type for outputting a pulse of one polarity corresponding to the phase difference between the two input signals R1 and S1. The phase comparator of this type includes various outputs such as a so-called &#34;sawtooth wave characteristic&#34; and a &#34;triangular wave characteristic&#34;, etc. As an example, the input versus output characteristics of a phase comparator for producing a &#34;triangular wave characteristic&#34; employing an exclusive OR circuit are shown in FIGS. 5 and 6. 
     Referring to (a) to (c) of FIG. 5 and (a) to (c) of FIG. 6, the output signals Q1 of the phase comparator vary is shown in the drawings as depending upon the phase differences between the input signals R1 and S1 applied to the phase comparator 41. More particularly, when both the input signals R1 and S1 are logic level &#34;HIGH&#34; or &#34;LOW&#34;, the output signal Q1 becomes logic level &#34;LOW&#34;, and only when the input signals R1 and S1 become different logic levels, the output signal Q1 becomes logic level &#34;HIGH&#34;. Accordingly, even if the input signal R1 lacks a pulse P 1  as shown in (a) of FIG. 5, or even if the input signal R1 includes an excessive pulse P 2  as shown in (a) of FIG. 6, the output signal Q1 is temporarily affected thereby, but does not produce a large variation in the output level as shown in the case of the PFC in FIGS. 2 and 3. 
     On the other hand, the loop filter 42 is assumed to have a time constant which can attain the sufficient pull-in range by increasing the loop band-width of the PLL 4. 
     The second PLL 5 has a phase comparator 51, a loop filter 52 and a VCO 53. The output signal of the first PLL 4 (i.e., the output signal of the VCO 4) is inputted as an input signal R2 to the phase comparator 51, is fed through the phase comparator 51 to the loop filter 52, and is further outputted from the VCO 53. The output signal from the VCO 53 is fed back to the other input S2 of the phase comparator 51. 
     The loop filter 52 is constructed to have a time constant which narrows the loop band-width of the PLL 5, and the phase comparator 51 is constructed to have a PFC having the input versus output characteristics shown in FIG. 1 so as to attain the wide pull-in range even if the loop band-width is narrowed in this manner. 
     The operation of the embodiment of the signal regeneration circuit thus constructed will now be described. 
     Assume that an input signal which has a number of jitters and lacks one or more pulses is inputted to the input terminal 1, the signal is so arranged through the BPF 2 so that its frequency components are similar to the original signal, is then waveform-shaped through the waveform shaping circuit 3, and is, for example, inputted to the first PLL 4 in the form of the waveform shown in (a) of FIG. 7. 
     As described above, since a phase comparator of exclusive OR type which operates, for example, as shown in FIGS. 5 and 6, is used as the phase comparator 41 of the first PLL 4 and the loop band-width of the first PLL 4 is selected widely, the output signal of the first PLL and hence the output of the VCO 43 has a number of jitters, but is locked to the input R1 (more accurately, to the average frequency of the input signal R1) of the phase comparator 41, and thus becomes a signal which lacks no pulse as shown in (b) of FIG. 7. This output becomes an input R2 of the phase comparator 51 of the second PLL 5 (refer to (a) of FIG. 8). 
     Since the loop band-width of the second PLL 5 is selected of sufficiently narrow width and the phase comparator 51 employs a PFC, the output of the PLL 5 and hence the output of the VCO 53 (also becoming the other input S2 of the phase comparator 51) is effectively locked to the average frequency (i.e., the frequency of the original signal) of the input R2 of the phase comparator 51, and becomes a signal which has almost no jitter, and is outputted from the output terminal 6. 
     The above mentioned operation of the embodiment of the signal regeneration circuit thus constructed is fundamentally similar to that when an input signal having an excessive pulse is applied to the input terminal 1, and a clear signal which is corrected from the excessive pulse can be outputted from the output terminal 6. 
     In the embodiment described above, if the frequency of the input signal falls within the predetermined frequency band width capable of being pulled in the first PLL 4, the similar effect to the above PLL can be obtained even if the BPF 2 is omitted. If the input signal level is a predetermined level corresponding to the logic level of the phase comparator 41, the similar effect to the above PLL can be obtained even if the waveform shaping circuit 3 is omitted. If the frequency of the input signal falls further within the predetermined frequency band width capable of being pulled in by the first PLL 4 and the level is a predetermined level corresponding to the logic level of the phase comparator 41, the similar effect to the PLL can also be obtained even if the PBF 2 and the waveform shaping circuit 3 are omitted. 
     Examples of designing the above-described circuit will be shown so as to prove the effect with numeral values. In this case, the assumption will be placed as in the following fundamental items: 
     (1) The first PLL 4 receives an input signal through the BPF 2, and the band width of the BPF 2 is represented by Bi. 
     (2) The phase comparator 41 employs an exclusive OR circuit type, and the input/output waveforms are approximated to a sinusoidal waveform. 
     (3) The loop filters 42 and 52 are lag-lead type filters as shown in FIG. 9. 
     The fundamental equations for designing the PLL are initially given. However, the constants of the lag-lead filter shown in FIG. 9 are defined as follows: 
     
         τ.sub.1 =R.sub.1 ·C 
    
     
         τ.sub.2 =R.sub.2 ·C 
    
     The transfer function H(s) of the PLL is ##EQU1## where K d  represents the sensitivity of the phase comparator, and the K 0  represents the sensitivity of the VCO. This equation will be rewritten by preparing coefficients so that the denominator becomes (s 2  +2ξ·ω n  s+ω n   2 ) as follows: ##EQU2## ω n  and ξ are respectively called a natural angular frequency and a damping factor. 
     Then, equations for obtaining a loop noise band width and a phase jitter component will be given. 
     The loop noise band width B L  is defined by the following equation: ##EQU3## where the relationship of (ω n  /K 0  ·K d )&lt;&lt;2ξ should exist. 
     The signal-to-noise ratio S/N of the input signal through the BPF 2 of the band width Bi can be obtained by the following equation: ##EQU4## where the noise electric power per 1 Hz of frequency is represented by N o  and the signal electric power is represented by A. Further, the variance ρ.sub.φ of the phase jitter component through the PLL can be represented by the following equation: 
     
         ρ.sub.φ =N.sub.o ·B.sub.L /A              (5) 
    
     Therefore, the effective value φ of the phase jitter becomes the following equation: ##EQU5## It is understood from the equation (6) that, the smaller the loop noise band width B L  of the PLL is, the lower the phase jitter component becomes. The equation (6) can be reformed as follows: 
     
         B.sub.L =(φ.sup.2 ·A)N.sub.o                  (7) 
    
     Then, an equation for obtaining the pull-in range of the PLL will be given. 
     The pull-in range ω P  of the PLL of the case that the sinusoidal waveform phase comparator is used for the phase comparator and that the lag-lead filter is used for the loop filter as assumed previously can be represented by the following equation: ##EQU6## where the constant m is defined as follows: 
     
         m=τ.sub.2 /(τ.sub.1 +τ.sub.2) 
    
     The circuit exemplified in FIG. 4 will be designed based on the above respective equations. As one example, the designing conditions are determined as follows: 
     (1) The frequency of the input signal is 6,000 Hz. 
     (2) The band width Bi of the BPF 2 is 1,200 Hz. 
     (3) The pull-in range ω P  (which is determined by the first PLL in this embodiment) is ±500 Hz. 
     (4) The maximum value of the phase jitter in the final output (i.e., the output of the second PLL) is ±20° under the condition that the signal-to-noise ratio S/N of the input signal is S/N=10 dB. 
     (Design of First PLL 4) 
     Initially, the constants τ 1 , τ 2 , the natural angular frequency ω n  and the loop noise band width B L  of the loop filter will be obtained from the pull-in range ω P . 
     Firstly, the pull-in range ω P  =2π×500(rad), the sensitivity K 0  =2π×500 of the VCO 43, and the sensitivity K d  =1 of the phase comparator 41 are substituted in the above equation (8), and the value of the m will be obtained as follows: ##EQU7## 
     Secondly, assuming that the damping factor ξ=0.7, and the filter constants (τ 1  +τ 2 ) of the loop filter 42 will be obtained as follows: That is, the τ 2  in the above equation (2) is substituted for the following: ##EQU8## A variable x is here defined as x=√τ 1  +τ 2 , then, ##EQU9## substituted in the above equation to obtain the value of x as follows: ##EQU10## 
     Since there is a relationship of τ 1  +τ 2  =x 2 , ##EQU11## Since the filter constant τ 2  is τ 2  =m(τ 1  +τ 2 ), the τ 2  becomes as follows: ##EQU12## 
     Then, the natural angular frequency ω n  will be obtained using the above equation (1). That is, K 0  ·K d  =2π×250, and τ 1  +τ 6  =3.98×10 -3  are substituted in the above equation (1), and the natural angular frequency can be obtained as follows: ##EQU13## 
     Therefore, the loop noise band width B L  can be obtained as follows by substituting ξ=0.7, and ω n  =628 in the above equation (3): ##EQU14## The above results thus obtained can be summarized as follows: 
     Natural angular frequency: ω n  =628 
     Damping factor: ξ=0.7 ##EQU15## 
     Loop noise band width: B L  =332 (Hz) 
     Then, the maximum value (4φ) of the phase jitter in the first PLL 4 will be obtained from the value of the loop noise band width B L  obtained as above. That is, the signal-to-noise ratio S/N of the input signal, S/N=10 (dB) and the band width Bi of the BPG 2, Bi=1,200 (Hz) are first substituted in the equation (4) as follows: ##EQU16## Then, ##EQU17## and B L  =332 (Hz) are substituted are substituted in the equation (6) as follows: ##EQU18## 
     In this manner, the maximum value of the phase jitter in the first PLL 4 is ±38.1°. 
     (Design of Second PLL 5) 
     In this design, the maximum value of the phase jitter will be suppressed within ±20° as described above. 
     It is assumed that the maximum value of the phase jitter is afforded to be 18° as follows: 
     
         4φ=18°=0.314 (rad) 
    
     Therefore, ##EQU19## This value is substituted in the equation (7), and the loop noise band width B L  of the second PLL 5 will be obtained as follows: In this case, A/N 0  =12000 is given as previously obtained. ##EQU20## Then, the value of the damping factor ξ is suitably selected, and the natural angular frequency ω n  in the second PLL 5 will be obtained as follows: Since the phase response error against the variation in the phase step becomes smaller value in a short time when the damping factor ξ is set to larger value, the damping factor ξ is selected to ξ=1.4. First, the equation (3) is modified as follows: ##EQU21## The B L  =73.9 (Hz), and ξ=1.4 are substituted in the above equation as follows: ##EQU22## 
     Then, with the sensitivity K 0  =2π×250 of the VCO 53 and the sensitivity K d  =0.25 of the phase comparator 51 (PFC), the filter constant (τ 1  +τ 2 ) of the loop filter 52 will be obtained as follows: First, the equation (1) is modified as follows: ##EQU23## The ω n  =93.6, K 0  =2π×250, and K d  =0.25 are substituted in the above equation as follows: ##EQU24## Further, the filter constant τ 2  can be modified from the equation (2) as follows: ##EQU25## Similarly, the  n  =93.6, K 0  =2 250, and K d  =0.25 as well as ξ=1.4 are substituted in the above equation as follows: ##EQU26## The above results thus obtained can be summarized as follows: Natural angular frequency: ω n  =93.6 
     Damping factor: ξ=1.4 ##EQU27## 
     Loop noise band width: B L  =73.9 (Hz) 
     The final phase jitter characteristics of the signal generation circuit is determined by the respective constants of the second PLL 5. 
     In order to prove the advantages and the effects of the circuit thus exemplified in the above design, the responsiveness of the first and the second PLLs 4 and 5 will be described in the case that the input signal lacks a pulse. 
     Initially, the input signal to the VCO 43 of the first PLL 4 in the case that a rectangular signal which lacks no pulse is inputted will be obtained as an ordinary operation. 
     When the voltages of the respective sections in the lag-lead filter shown in FIG. 9 are first determined as shown in FIG. 9, the filter current i becomes as follows: ##EQU28## and the filter current i can be expressed as follows: ##EQU29## Further, the output voltage v out  of the filter can be expressed as follows: ##EQU30## Then, the voltage v C  across the capacitor can be obtained as follows from the equations (9) and (10): ##EQU31## When this differential equation is solved, v C  becomes as follows: ##EQU32## 
     Therefore, when the input signal v in  to the above filter is a rectangular wave as shown in (a) of FIG. 11, the stationary value of the voltage v C  becomes as shown in (b) of FIG. 11. Then, the initial values of the duration I in (b) of FIG. 11 are substituted into equation (12) to obtain the coefficient C 1  as follows: That is, since t=t 2n , v C  =v CL  and v in  =h (refer to (a) of FIG. 11), v CL  becomes as follows: ##EQU33## Therefore, C 1  becomes as follows: ##EQU34## When this equation (13) is substituted in the above equation (12) and is arranged, this equation becomes as follows, (where α=1/(C·R 1  +C·R 2 ): 
     
         v.sub.C =v.sub.CL ·e.sup.-α(t-t.sbsp.2n.sup.) +h(1-e.sup.-α(t-t.sbsp.2n.sup.))                    (14) 
    
     Since v C  =v CH  can be obtained in case of t=t 2n+1  in (b) of FIG. 11, the following equation can be obtained: 
     
         v.sub.CH =v.sub.CL ·e.sup.-α(t.sbsp.2n+1.sup.-t.sbsp.2n.sup.) +h(1-e.sup.-α(t.sbsp.2n+1.sup.-t.sbsp.2n.sup.)) 
    
     When (t 2t+1  -t 2n )=a is defined, 
     
         v.sub.CH =v.sub.CL ·e.sup.-αa +h(1-e.sup.-αa) (15) 
    
     Further, v in  =0 (refer to FIG. 11A) can be obtained in case of t=t 2n  +1 in the duration II in (b) of FIG. 11, and accordingly the following equation can be obtained: 
     
         v.sub.CH =C.sub.1 ·e.sup.-α·t.sbsp.2n+1 
    
     Accordingly, the coefficient C 1  becomes as follows: ##EQU35## When this equation (16) is substituted in the above equation (12) and is arranged, the following equation can be obtained: 
     
         V.sub.C =v.sub.CH ·e.sup.-α(t-t.sbsp.2n.sup.) (17) 
    
     Since v C  =v CL  can be obtained in case of t=t 2n  +2  in (b) of FIG. 11, the following equation can be obtained: 
     
         v.sub.CL =v.sub.CH ·e.sup.-αa               (18) 
    
     When the v CH  is eliminated from the equations (18) and (15), the following equation can be obtained: ##EQU36## Further, from the relationship of the equation (18), the v CH  becomes as follows: ##EQU37## 
     Then, the output voltage of the filter can be obtained from the equations (11), (19) and (20) thus attained as follows: 
     Since v in  =0 and v C  =v CL  can be obtained in case of t=t 2n  -0 (immediately before t=t 2n ) in (a) and (b) of FIG. 11, when they are substituted in the equation (11), the output voltage v out  of the filter can be obtained as follows: ##EQU38## 
     Since the following relationship can be however defined, this is represented by m (refer to the above equation (8)). ##EQU39## 
     This v out  corresponds to the v L1  in FIG. 11C. Similarly, since v in  =h and v C  =v CL  can be attained in case of t=t 2n+0  (immediately after t=t 2n ) in (a) and (b) of FIG. 11, when they are similarly substituted in the equation (11), the following equation can be obtained: ##EQU40## This v out  corresponds to the v H1  in (c) of FIG. 11. Further, since v in  =h and v C  =v CH  can be attained in case of t=t 2n+1-0  (immediately before t=t 2n+1 ) in (a) and (b) of FIG. 11, when they are substituted in the equation (11), the following equation can be obtained: ##EQU41## The v out  corresponds to the v CH  in (c) of FIG. 11. Since v in  =0 and v C  =v CH  can be obtained in case of t=t 2n+1+1  (immediately after t=t 2n+1 ), when they are substituted in the equation (11), the following equation can be obtained: 
     
         v.sub.out =(1-m)v.sub.CH                                   (24) 
    
     This v out  corresponds to the v L2  in (c) of FIG. 11. 
     Since the output voltage v out  of the filter is filtered before being inputted to the VCO 43 and the phase comparison frequency components are removed from the output voltage v out , the waveform of the signal actually applied to the VCO 43 becomes a waveform as shown in (d) of FIG. 11. However, in (d) of FIG. 11, the lower voltage v VL  becomes an averaged value of the v out  indicated by the equation (21) and the v out  indicated by the equation (22), and the higher voltage v VH  becomes an averaged value of the v out  (V H2 ) indicated by the equation (23) and the v out  (V L2 ) indicated by the equation (24). Accordingly, they can be represented as follows: ##EQU42## Then, when the equations (21) and (22) are substituted in the equation (25), and the equations (23) and (24) are substituted in the equation (26), the following equations can be obtained: ##EQU43## 
     Then, the constants of the first PLL 4 obtained previously are substituted in the above equations (19),(20), and (27), (28), and actual values will be obtained as follows: 
     The values of a and α in the equations (19) and (20) can be calculated as follows: ##EQU44## When the value of the h is 7 (V), the v CL  can be obtained from the equation (19) as follows: ##EQU45## Then, the v CH  can be obtained from the equation (20) as follows: ##EQU46## 
     Further, since the value of the m in the equations (27) and (28) can be obtained as follows, ##EQU47## the input voltages v VL  and v VH  of the VCO 43 can be respectively obtained as follows from the equations (27) and (28): ##EQU48## It is thus understood that the input voltages v VL  and v VH  of the VCO 43 are varied within ±0.02 (V) 
     Since the modulation sensitivity of the VCO 43 is 500 (Hz/V), the variations in the oscillation frequency of the first PLL 4 with respect to the variations in the input voltages v VL  and v VH  can be obtained as follows: 
     
         500×(±0.02)=±10 (Hz) 
    
     Further, the lock-in range Δω of the first PLL 4 can be defined as follows: 
     
         Δω=2ξ·ω.sub.n 
    
     When ξ=0.7 and ω n  =628 previously obtained are substituted in the above equation, the following value can be obtained: ##EQU49## It can be understood from this that the first PLL can operated without causing out of the lock-in range. 
     Then, the variation in the oscillation frequency of the first PLL 4 will be obtained in the case that the input voltage to the phase comparator 41 lacks a pulse as shown in (a) FIG. 12. 
     Initially, the voltage v C  across the capacitor in the lag-head filter shown in FIG. 10 will be obtained. However, in this case, the change of the voltage v C  with passage of time when the input voltage lacks a pulse becomes the state shown in (d) of FIG. 12, the coefficient C 1  of the differential equation (12) will be obtained, where the voltage v C  at the time t b2  in FIG. 12 is represented by v CLL  and the voltage v C  at the time t C  in FIG. 12 is represented by v CHL  as follows: 
     In this case, in (d) of FIG. 12, since v in  =0 in case of t=t a  to t b  (refer to FIG. 12C) and v C  =v CH  in case of t-t a , the following equation can be obtained: ##EQU50## Therefore, the coefficient C 1  can be obtained as follows: ##EQU51## When this equation is substituted in the equation (12) and is arranged, 
     
         v.sub.C =v.sub.CH ·e.sup.-(t-t.sbsp.a.sup.)/(τ.sbsp.1.sup.+τ.sbsp.2.sup.) 
    
     Since the v C  is v CLL  in case of t=t b  as described above in this case, this is substituted in the above equation, and following equation can be obtained: ##EQU52## 
     In (d) of FIG. 12, since v in  =h in case of t=t b  -t c  (refer to (c) of FIG. 12) and v C  =v CLL  in case of t=t b , the v CLL  can be obtained as follows: ##EQU53## 
     Therefore, the coefficient C 1  can be obtained as follows: ##EQU54## When this equation is substituted in the equation (12) and is arranged, following equation can be obtained: ##EQU55## Since the v C  is v CHL  in case of t=t c  as described above in this case, this is substituted in the above equation, and the following equation can be obtained: ##EQU56## 
     From this onward, the equation of the relationship obtained previously in the stationary pulse state can be employed. Accordingly, when the v CL  and the v CH  are respectively substituted by the v CLL  and the v CHL  in the above equations (27) and (28), the input voltages v VLL  and v VHL  to the VCO 43 of this case can be obtained as follows: ##EQU57## 
     Then, actual values will be obtained by substituting the constants of the first PLL 4 in the equations (29), (30) and (31), (32) in the same manner as above. In this case, the constants used in the equations (29) to (32) are as follows: 
     
         v.sub.CH =3.54 (V) 
    
     
         a=8.33×10.sup.-5 
    
     
         τ.sub.1 +τ.sub.2 =3.98×10.sup.-3 
    
     
         m=0.4 
    
     
         h=7 (V) 
    
     From the equation (29), the v CLL  can be obtained as follows: ##EQU58## Further, from the equation (30), the v CHL  can be obtained as follows: ##EQU59## Therefore, the input voltages v VLL  and v VHL  to the VCO 43 of this case can be obtained from the equations (31) and (32) as follows: ##EQU60## Thus, it is understood that the input voltages v VLL  and v VHL  of the VCO 43 are varied with +0.03 (V) and -0.06 (V). 
     The oscillation frequency of the first PLL 4 of this case is as follows: ##EQU61## 
     This case can sufficiently fall within the range of the lock-in range Δω=140 (Hz) previously obtained, and the PLL can continue the normal operation without causing out of lock-in range. Accordingly, the output waveform which lacks no pulse as shown in (c) of FIG. 12 can be always obtained from the first PLL 4. Therefore, a stable operation can also be secured even in the second PLL 5 which receives the output of the first PLL 4. The output of the signal regeneration circuit becomes a clear waveform having less jitter with the loop constants of the second PLL 5 as described above.