Abstract:
A method of forming a trench capacitor and memory cells using the trench capacitor. The method includes: forming an opening in a masking layer; and forming a trench in the substrate through the opening, the trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into the substrate, the upper region of the trench adjacent to the top surface of the substrate having a vertical sidewall profile and a first width in the horizontal direction, the middle region of the trench having a tapered sidewall profile, a width in a horizontal direction of the middle region at a juncture of the upper region and the middle region being the first width and being greater than a second width in the horizontal direction of the middle region at a juncture of the middle region and the lower region.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of semiconductor devices; more specifically, it relates to semiconductor trench capacitors and memory cells using the trench capacitors and method of fabricating the semiconductor trench capacitors and memory cells using the trench capacitors. 
     BACKGROUND OF THE INVENTION 
     A predominate use of trench capacitors is as the storage nodes of dynamic random access memory (DRAM) cells, though there are many other uses. As the density of DRAM increases and the photolithographic groundrules and resultant physical dimensions of the trench capacitors decrease, it has become increasingly difficult to fabricate the resultant narrow trenches. Additionally, narrow trenches have lower capacitance and higher resistance than wide trenches leading to lower reliability. Therefore, there is a need for trench capacitor structures and a method of fabricating trench capacitors that is scalable to ever decreasing trench widths and that overcomes fabrication limits and capacitance and resistance problems of current trench capacitor designs. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention is a structure, comprising: a substrate having a top surface defining a horizontal direction; a trench having contiguous upper, middle and lower regions, the middle region between the upper and lower regions, the trench extending from the top surface of the substrate into the substrate along an axis perpendicular to the top surface of the substrate, the axis defining a vertical direction; the upper region of the trench adjacent to the top surface of the substrate having a vertical sidewall profile and a first width in the horizontal direction; and the middle region of the trench having a tapered sidewall profile, a width in the horizontal direction of the middle region at a juncture of the upper region and the middle region being the first width and being greater than a second width in the horizontal direction of the middle region at a juncture of the middle region and the lower region. 
     A second aspect of the present invention is a method forming a trench in a substrate having a top surface defining a horizontal direction, comprising: forming a masking layer on the top surface of the substrate; forming an opening in the masking layer to define a perimeter of a trench; and forming the trench in the substrate through the opening, the trench having contiguous upper, middle and lower regions, the middle region between the upper and lower regions, the trench extending from the top surface of the substrate into the substrate along an axis perpendicular to the top surface of the substrate, the axis defining a vertical direction, the upper region of the trench adjacent to the top surface of the substrate having a vertical sidewall profile and a first width in the horizontal direction, the middle region of the trench having a tapered sidewall profile, a width in the horizontal direction of the middle region at a juncture of the upper region and the middle region being the first width and being greater than a second width in the horizontal direction of the middle region at a juncture of the middle region and the lower region. 
     A third aspect of the present invention is a memory cell, comprising: a trench capacitor in a substrate, the trench capacitor having contiguous upper, middle and lower regions, the middle region between the upper and lower regions, the trench extending from a top surface of the substrate into the substrate along an axis perpendicular to the top surface of the substrate, the axis defining a vertical direction; the upper region of the trench adjacent to the top surface of the substrate having a vertical sidewall profile; the middle region of the trench having a tapered sidewall profile, a width in the horizontal direction of the middle region at a juncture of the upper region and the middle region being greater than a width in the horizontal direction of the middle region at a juncture of the middle region and the lower region; and a field effect transistor comprising a gate electrode separated from a channel region in the substrate by a gate dielectric layer on the top surface of the substrate and first and second source/drains formed in the substrate on opposite side of the channel region, the second source/drain electrically connected to an electrode formed in the trench. 
     A fourth aspect of the present invention is a method of fabricating a memory cell, comprising: forming a trench capacitor in a substrate, the trench capacitor having contiguous upper, middle and lower regions, the middle region between the upper and lower regions, the trench extending from a top surface of the substrate into the substrate along an axis perpendicular to the top surface of the substrate, the axis defining a vertical direction; the upper region of the trench adjacent to the top surface of the substrate having a vertical sidewall profile; the middle region of the trench having a tapered sidewall profile, a width in the horizontal direction of the middle region at a juncture of the upper region and the middle region being greater than a width in the horizontal direction of the middle region at a juncture of the middle region and the lower region; and forming a field effect transistor comprising a gate electrode separated from a channel region in the substrate by a gate dielectric layer on the top surface of the substrate and first and second source/drains formed in the substrate on opposite side of the channel region, the second source/drain electrically connected to an electrode formed in the trench. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
         FIGS. 1A through 1H  are cross-sectional drawings illustrating fabrication of trench capacitors according to the embodiments of the present invention; 
         FIG. 2  is a cross-sectional view of a memory cell using trench capacitors according to the embodiments of the present invention; and 
         FIGS. 3A ,  3 B and  3 C are cross-sectional views illustrating alternative lower region trench geometries of trench capacitors according to the embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIGS. 1A through 1H  are cross-sectional drawings illustrating fabrication of trench capacitors according to the embodiments of the present invention. In  FIG. 1A , on a top surface  100  of a silicon substrate  105  a pad layer  115  is formed and a trench  120  is etched in the substrate through an opening formed in the pad layer. Pad layer  115 , serves, among other uses, as a hardmask layer. Trench  120  has three distinct regions, an upper region  125  adjacent to top surface  100  of substrate  105 , a middle region  130  and a lower region  135 . In one example, pad layer  115  comprises a layer of silicon dioxide between about 2 nm and about 10 nm in thickness in contact with top surface  100  and a silicon nitride layer between about 100 nm and 2000 nm on the silicon dioxide layer. Additional one or more hardmask layers (not shown) can be formed on the pad layer  115  before the deep trench is etched. For example, a layer (not shown) comprising borosilicate glass (BSG) can be deposited on the pad layer  115  by chemical vapor deposition (CVD) and patterned along with the underlying pad layer  115 . The additional hardmask layers facilitate the deep trench formation and can be removed after the deep trench  120  is etched. 
     Upper region  125  of trench  120  has a substantially uniform width W 1  along an axis  136  perpendicular to top surface  100 . Upper region  125  of trench  120  extends a distance D 1  into substrate  105 . Sidewall region  137  of upper region  125  of trench  120  is at an angle a 1  relative to top surface  100  of substrate  105 . Sidewall region  137  of upper region  125  of trench  120  is substantially perpendicular to top surface  100  of substrate  105 . In one example, angle a 1  is about 90°. In one example, angle a 1  is between about 89.5° and about 90.5°. Sidewall region  137  is essentially a trench region having a vertical sidewall (relative to top surface  100 ). 
     Middle region  130  of trench  120  has width W 1  where the middle region adjoins upper region  125  and a width W 2  where it adjoins lower region  135 . Middle region  130  extends a distance D 2  into substrate  100  below upper region  125 . W 1  is greater than W 2 . Sidewall region  138  of middle region  135  is at an angle a 2  relative to top surface  100  of substrate  105 . Sidewall region  138  of middle region  130  of trench  120  tapers inward toward axis  122 . In one example, angle a 2  is about 1.0°. In one example, angle a 2  is between about 3.0° and about 0.5°. In one example, the ratio (W 1 −W 2 )/W 1  is less than about 0.2. In one example, W 1 −W 2  is less than or equal to about 10 nm. In one example, W 1  is equal to less than about 90 nm and W 2  is equal to or less than about 80 nm. In one example, W 1  is equal to less than about 65 nm and W 2  is equal to or less than 55 nm. Sidewall region  138  is essentially a trench region having a tapered sidewall (relative to top surface  100 ). In one example D 1  is between about four times and about five times D 2 . 
     Lower region  135  of trench  120  has width W 2  where the lower region adjoins middle region  130  and a width W 2  where it adjoins lower region  135 . Lower region  135  of trench  120  has a substantially uniform width W 2  along axis  136  and extends a distance D 3  into substrate  105  below middle region  130 . Sidewall region  139  of lower region  135  of trench  120  is essentially perpendicular to top surface  100  of substrate  100  in  FIG. 1A . Sidewall region  139  is essentially a sidewall region having a vertical sidewall (relative to top surface  100 ). However, other geometries of lower region  135  are possible and are illustrated in  FIGS. 3A ,  3 B and  3 C and described infra. 
     Trench  120  may be formed by a reactive ion etch (RIE) process using a multiple step RIE process. Upper region  125  of trench  120  may be formed by a first RIE process step, middle region  130  of the trench may be formed by a second RIE process step different from the first RIE step process and lower region  135  of the trench may be formed by one or more additional RIE process steps. Table I illustrates exemplary first and second RIE process steps. 
     
       
         
               
             
               
               
               
               
               
             
           
               
                 TABLE I 
               
               
                   
               
               
                 Exemplary RIE Process Steps for a Trench with W1 less than or 
               
               
                 equal to 90 nm (300 mm Wafer, about 20% Trench Area) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Trench Region 
                 Upper 
                 Middle 
                 Lower 
               
               
                   
                 RIE 
                 Step 1 
                 Step 2 
                 Step 3 
               
               
                   
                 Bias power (W) 
                 1300 
                 1500 
                 1800 
               
               
                   
                 Pressure (mT) 
                 150 
                 150 
                 200 
               
               
                   
                 O 2  (sccm) 
                 28 
                 23 
                 16 
               
               
                   
                 NF 3  (sccm) 
                 36 
                 36 
                 32 
               
               
                   
                 HBr (sccm) 
                 300 
                 300 
                 300 
               
               
                   
                 Profile of Region 
                 Vertical 
                 Tapered 
                 Vertical 
               
               
                   
                 Depth of Region (um) 
                 1.2 (D1) 
                 0.3 (D2) 
                 6.0 (D3) 
               
               
                   
                   
               
             
          
         
       
     
     A person of ordinary skill in the art, will be able to modify the conditions given in Table I to fit other trench profiles and geometries without undue experimentation. 
     In  FIG. 1B , a node dielectric layer  140  is formed on a sidewall  145  (includes sidewall regions  137 ,  138  and  139  illustrated in  FIG. 1A  and described supra) of trench  120 , on a bottom  150  of the trench and on a top surface  155  of pad layer  115 . In one example node dielectric is formed by low pressure chemical vapor deposition (LPCVD) of silicon nitride between about 2.5 nm and about 6.0 nm thick followed by an optional thermal oxidation. In one example, node dielectric comprises a high-k (dielectric constant) material between about 0.5 nm and about 6.0 nm thick formed by atomic layer deposition (ALD) or metalorganic chemical vapor deposition (MOCVD), examples of which include but are not limited metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. A high-k dielectric material has a relative permittivity above about 10. 
     In  FIG. 1C , trench  120  is filled with a first electrically conductive fill material  160 . In one example, the first fill material  160  preferably comprises N-type doped polysilicon. Alternatively, first fill material  160  may comprise electrically conductive materials, including but not limited to, doped silicon germanium, , tungsten, titanium, cobalt, copper, aluminum, other metals, tungsten silicide, titanium nitride, polysilicon and combinations thereof. In some cases, when first fill material  160  is polysilicon, a void  165  may form in the polysilicon in upper region  125  of trench  120 . 
     Because the upper part of the trench is vertical for a significant distance before is tapers down, filling of the trench with polysilicon is more easily accomplished and any voids formed do not extend far enough into the tapered portion of the trench and can be removed or their disruption of fill interfaces drastically reduced during subsequent processing steps. 
     In  FIG. 1D , a portion of first polysilicon  160  is removed from trench  120  so that a top surface  167  of first polysilicon  160  is within middle region  130  of trench  167 . Top surface  167  is a distance D 4  from the top of middle region  130 . Node dielectric layer  140  is also removed from all surfaces (particularly sidewall  145  of trench  120 ) no longer protected by first polysilicon  160 . In one example, first polysilicon  160  is removed by a recess RIE process. In one example, a chemical-mechanical-polish (CMP) is performed to coplanarize a top surface of first polysilicon  160  in trench  120  with atop surface  155  of pad layer  115  prior to a recess RIE process. In one example, node dielectric  140  (if not removed during the recess RIE) is removed by wet etching with an etchant of hydrofluoric acid mixed with ethylene glycol. 
     In  FIG. 1E , a dielectric collar  170  is formed on sidewall  145  where sidewall  145  is not covered by node dielectric  140  and first polysilicon  160 . In one example, collar  170  is formed by CVD deposition of a tetraethoxysilane (TEOS) oxide followed by an RIE process and is between about 15 nm and about 50 nm thick. In one example, a thermal oxidation process is performed to form a silicon dioxide (not shown) on the exposed sidewall  145  and on the top surface of the polysilicon  160  prior to the TEOS deposition. In one example, an annealing process at a temperature between 800° C. to 1200° C. is performed prior to the RIE process. In one example, collar  170  comprises a low-k (dielectric constant) material, examples of which include but are not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), SiLK™ (polyphenylene oligomer) manufactured by Dow Chemical, Midland, Tex., Black Diamond™ (methyl doped silica or SiO x (CH 3 ) y  or SiC x O y H y  or SiOCH) manufactured by Applied Materials, Santa Clara, Calif., organosilicate glass (SiCOH), and porous SiCOH between about 15 nm and about 40 nm thick. A low-k dielectric material has a relative permittivity of about 3.1 or less. 
     Because the upper part of the trench is vertical for a significant distance before is tapers down, formation of collars is easily accomplished and the collars may be kept relatively thick with no fear of reducing the cross-sectional area of the polysilicon fill which would increase the resistance of the capacitor. 
     In  FIG. 1F , trench  120  is filled with a second electrically conductive fill material  175  and then second fill material is recessed back so a top surface  177  of second fill material  175  is within upper region  125  of trench  120  in a manner similar to that described supra for recessing first fill material  160 . In one example, second fill material  175  preferably comprises N-type doped polysilicon. Alternatively, second fill material  175  may comprise electrically conductive materials, including but not limited to, doped silicon germanium, tungsten, titanium, cobalt, copper, aluminum, other metals, tungsten silicide, titanium nitride, polysilicon and combinations thereof. 
     In  FIG. 1G , collar  170  is removed from sidewall  145  where the collar is not protected by second polysilicon  175 . Dry etch processing (such as plasma etching) or wet etch processing (such as etching in hydrofluoric acid containing etchants) may be used depending on the composition of collar  170 . 
     In  FIG. 1H , trench  120  is filled with a third electrically conductive fill material  180  and then the third fill material recessed back so a top surface  182  of the second fill material is within upper region  125  of trench  120  but below top surface  100  of substrate  105  in a manner similar to that described supra for recessing first fill material  160 . In one example, third fill material  180  preferably comprises N-type doped polysilicon. Alternatively, third fill material  180  may comprise electrically conductive materials, including but not limited to, doped silicon germanium, tungsten, titanium, cobalt, copper, aluminum, other metals, tungsten silicide, titanium nitride, polysilicon and combinations thereof. 
     Fabrication of a trench capacitor  185  according to the embodiments of the present invention is essentially complete. Additional steps, described infra, may be performed to fabricate a dynamic access memory (DRAM) cell. 
       FIG. 2  a cross-sectional view of a memory cell using trench capacitors according to the embodiments of the present invention. In  FIG. 2 , a trench isolation  190  is formed in substrate  105  and partially into trench capacitor  185 . In one example, trench isolation  190  may be formed by (1) etching trenches into substrate  105  and into a portion of trench capacitor  185 , using pad layer  115  (see  FIG. 1H ) as a hardmask, (2) over-filling the trench with a dielectric material, such as TEOS oxide and (3) performing a CMP down to the pad layer. 
     Next, pad layer  115  (see  FIG. 1H ) is removed and a field effect transistor (FET)  200  is formed adjacent to and physically and electrically connected to trench capacitor  185 . Formation of FETs is well known in the art. FET  200  includes a gate electrode  205  and dielectric spacers  210  formed over a gate dielectric  215  formed over a channel region  220  separating a first source/drain  225  from a second source/drain  230 . A buried strap  235  (formed by out-diffusion of dopants from third polysilicon  180  provides an electrical connection between second source/drain  230  and third polysilicon  180 . In one example. FET  200  is an n-channel FET (NFET). 
       FIGS. 3A ,  3 B and  3 C are cross-sectional views illustrating alternative lower region trench geometries of trench capacitors according to the embodiments of the present invention. Any of the trenches  120 A,  120 B or  120 C of respective  FIGS. 3A ,  3 B and  3 C may replace trench  120  of  FIG. 1A  as the starting trench for the fabrication of a trench capacitor according to the embodiments of the present invention. 
     In  FIG. 3A , upper and middle regions  125  and  130  of trench  120 A are the same as upper and middle regions  125  and  130  of trench  120  of  FIG. 1A . A lower region  135 A of trench  120 A has an inward tapering sidewall region  139 A so a width W 3  at the bottom of the lower region is less than the width W 2  at the top of the lower region. 
     In  FIG. 3B , upper and middle regions  125  and  130  of trench  120 B are the same as upper and middle regions  125  and  130  of trench  120  of  FIG. 1A . A lower region  135 B of trench  120 B has an outward tapering sidewall region  139 B so a width W 4  at the bottom of the lower region is greater than the width W 2  at the top of the lower region. 
     In  FIG. 3C , upper and middle regions  125  and  130  of trench  120 C are the same as upper and middle regions  125  and  130  of trench  120  of  FIG. 1A . A lower region  135 C of trench  120 C includes a vertical region  240  and a bulbous region  245  (the vertical region is between middle region  130  and bulbous region  245 ). Vertical region  240  has a width W 2  and bulbous region  245  has a maximum width W 5 , where W 5  is greater than W 2 . Trenches  120 B and  120 C are known as a “bottle” trenches and when used for a trench capacitor results in a “bottle trench capacitor.” 
     Thus the present invention provides trench capacitor structures and a method of fabricating trench capacitors that is scalable to ever decreasing trench widths and that overcomes fabrication limits and capacitance and resistance problems of current trench capacitor designs. 
     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.