Abstract:
In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention is generally related to digital computer systems. 
       BACKGROUND OF THE INVENTION 
       [0002]    One of the important features of integrated circuits deigned for portable applications is their ability to efficiently utilize the limited capacity of the battery power source. Typical applications include cellular telephones and personal digital assistants (PDAs), which might have a Lithium ion battery or two AAA alkaline batteries as the power source. Users have come to expect as much as three to four weeks of standby operation using these devices. Standby operation refers to the situation where the cellular phone, handheld device, etc. is powered on but not being actively used (e.g., actively involved in a call). Generally, is estimated that that the integrated circuits providing the functionality of the device is only performing useful work approximately 2% of the time while the device is in standby mode. 
         [0003]    Removing the power supply from selected circuits of a device during standby is a technique employed by designers for battery powered applications. The technique is generally applied only to circuit blocks outside of the central processing unit (CPU). A primary reason for not applying this technique to CPUs, has been the difficulty in being able to retain the current processor state information necessary to continue execution after coming out of the standby mode. One solution for this limitation involves saving the current processor state information to external storage mechanisms (e.g., such as flash memory, a hard disk drive, etc.). In such a case there is the overhead required in transferring the state to and from the external storage mechanism. Even if the battery powered device had a hard disk drive, and many don&#39;t, the time consuming state transfer would not meet the real time response requirements of the application when the device needs to wake up to respond to a new event. 
         [0004]    Other issues are presented when the functionality of a device is implemented by a system-on-a-chip (SOC) integrated circuit. For example, when the core of a system-on-a-chip CPU is temporarily powered down (e.g., deep sleep mode), some of the outputs that connect to assorted peripherals (e.g. LCD display, SPI interface, SDIO, Hard-disk, etc.) should be held in an idle state to avoid having to reprogram the peripheral or lose existing context in the peripheral. This causes a problem since some peripherals need particular values to be set at their inputs (which are connected to the outputs of the SOC) to hold a safely inactive state. For example, if a device is connected to a SOC that is clocked on the falling edge of a clock signal, and the SOC is powered down with that signal as a logic 1, but the power down state is a logic 0 (e.g., ground), it will cause a spurious clock on that signal. 
         [0005]    This problem is further exacerbated by the heavy use of pin-muxing or sharing, in which a single pin can have multiple functions in different designs by different customers. In one design a pin may be set to act as part of an SPI interface that wants to be held low when in sleep mode, while the same pin in another design, perhaps by a different customer may be used as a UART pin which would need to be held high when the CPU is put to deep sleep mode. While pin-muxing provides a way to put more features in each chip and allows the chip to be more suitable for a wide range of designs, it precludes knowing exactly at IC design time what each pin will be used for. A more flexible method of configuring the power down states is needed. 
         [0006]    One solution to this problem would be to have a software defined register for each pin that drives the pin to any one of the allowed number of states, such as: Input, output 0, output 1, output Hi-Z, open drain, etc. This is a workable solution, but has a problem that since normally the signals that control these functions come from the core of the CPU, they will not be present when the core is powered down in deep sleep mode. To overcome this, a second set of registers on the SOC will have to be in the special power domain. 
         [0007]    The special power domain is configured to always have power on (AO), even in the deep sleep mode. The special power domain allows the state information of these IO pads to be preserved. However the big problem is that it requires multiple signals from the portion of the chip that is in the special power domain to each pad, this can cause traces to be required. For example, with 300 signal pads and 3 wires per pad, as many as 900 traces have to be routed on the integrated circuit die, which is a large number at the top level of an integrated circuit die layout. These pad control signals must also be powered by the AO rail, which complicates the distribution of this AO rail or the routing of these pad control signals. Standard interrupt mechanism from the peripheral should result in an answer from the processor whatever is it&#39;s current state (e.g., active or standby). The benefits of a low power strategy cannot be fully realized if this mechanism is not transparent to the external environment. 
         [0008]    Thus, what is needed is a solution for powering down a CPU for reduced standby power consumption while retaining the integrity of the operating state. What is further needed is a solution for powering down the CPU without imposing burdensome trace routing requirements on the integrated circuit die layout. 
       SUMMARY OF THE INVENTION 
       [0009]    Embodiments of the present invention provides a method and system for powering down an integrated circuit device for reduced standby power consumption while retaining the integrity of the operating state. Embodiments of the present invention further provide a solution for powering down the integrated circuit device without imposing burdensome trace watering requirements on the integrated circuit die layout. 
         [0010]    In one embodiment, the present invention is implemented as a circuit for maintaining asserted values on an input output pin (e.g., pad, etc.) of an integrated circuit device when one or more functional blocks of the device are placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value (e.g., logical one, logical zero, etc.) of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin. The current value (e.g., as generated by the functional block) is stored prior to the functional block entering a sleep mode. The output storage element causes the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also configured to deactivate the storage element when the sleep mode is exited, thereby allowing the input output pin to resume being driven by the awakened functional block. In one embodiment, the deactivation is performed independently among the different functional blocks. The integrated circuit device can be a CPU (central processor unit), a system-on-a-chip, and embedded computer system, or the like. The input output pin can be coupled to a peripheral device (e.g., display screen, USB interface, etc.) for providing functionality to a user. 
         [0011]    In this manner, the signal state of the input output pins can be maintained as one or more functional blocks of the integrated circuit device are powered down. Upon exit from sleep mode (e.g., wake up), the input output pins can resume being driven by the one or more functional blocks. Additionally, this capability is provided without requiring the routing of multiple signals from a special power domain to the input output pin, which greatly reduces signal trace routing requirements. For example, embodiments of the present invention enabled a wake-up when one of a designated set of inputs transitions state. This allows the integrated circuit device to use the same pins that are used to recognize events during normal operation as wake pins to transition the device out of deep sleep. 
         [0012]    In one embodiment, different voltage rails are provided to accommodate the different peripheral voltages. For example, a camera can work at one voltage while a WiFi chipset within the camera is working at another voltage. Waking-up from the standard signal of a peripheral (e.g., such as an interrupt) avoids creating additional pads just for this function, which would require a specific voltage choice and voltage translators on the board. So some few selected pads are used as a generic input in the processor active mode but as a wake-up in the processor standby mode, thus at the correct voltage. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements. 
           [0014]      FIG. 1  shows a computer system in accordance with one embodiment of the present invention. 
           [0015]      FIG. 2  shows an overview diagram of a flexible pin configuration system in accordance with one embodiment of the present invention. 
           [0016]      FIG. 3  shows a circuit diagram of a flexible pin configuration component in accordance with one embodiment of the present invention. 
           [0017]      FIG. 4  shows a circuit diagram showing an input output capture component  400  in accordance with one embodiment of the present invention. 
           [0018]      FIG. 5  shows a circuit diagram showing an implementation where multiple capture components are utilized to capture a variety of different input output signals for an integrated circuit device in accordance with one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of embodiments of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the embodiments of the present invention. 
       Notation and Nomenclature: 
       [0020]    Some portions of the detailed descriptions, which follow, are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. 
         [0021]    It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “processing” or “accessing” or “executing” or “storing” or “rendering” or the like, refer to the action and processes of a computer system (e.g., computer system  100  of  FIG. 1 ), or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system&#39;s registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices. 
       Computer System Platform: 
       [0022]      FIG. 1  shows a computer system  100  in accordance with one embodiment of the present invention. Computer system  100  depicts the components of a basic computer system in accordance with embodiments of the present invention providing the execution platform for certain hardware-based and software-based functionality. In general, computer system  100  comprises at least one CPU  101 , a system memory  115 . A graphics processor unit (GPU)  110  can optionally be included, or any number of special function units. As shown in  FIG. 1 , the CPU  101  includes a special “always on” power domain  120  for managing the entry and exit of the computer system  100  into and out of a sleep mode. Similarly, the GPU  110  can also include an always on power domain  121 . The CPU  101  can be coupled to the system memory  115  via a bridge component/memory controller (not shown) or can be directly coupled to the system memory  115  via a memory controller (not shown) internal to the CPU  101 . The GPU  110  is coupled to a display  112 . 
         [0023]    System  100  can be implemented as a programmable system-on-a-chip integrated circuit device, where for example, the CPU  101 , memory  115 , and GPU  110  are fabricated as a single integrated circuit die, with the display  112  being coupled as a peripheral device. Similarly, the system  100  can be implemented as an embedded computer system within, for example, a handheld device (e.g., PDA, cell phone, etc.). Alternatively, system  100  can be implemented as, for example, a desktop computer system or server computer system, having a powerful general-purpose CPU  101  coupled to a dedicated graphics rendering GPU  110 . In such an embodiment, components can be included that add peripheral buses, specialized graphics memory, IO devices, and the like. Similarly, system  100  can be implemented a set-top video game console device such as, for example, the Xbox®, available from Microsoft Corporation of Redmond, Wash., or the PlayStation3®, available from Sony Computer Entertainment Corporation of Tokyo, Japan. 
       EMBODIMENTS OF THE INVENTION 
       [0024]    Embodiments of the present invention implement a method and system for powering down an integrated circuit device for reduced standby power consumption while retaining the integrity of the operating state. Embodiments of the present invention enable the reliable powering down and waking up of the integrated circuit device without imposing burdensome trace routing requirements on the integrated circuit die layout. 
         [0025]      FIG. 2  shows an overview diagram of a flexible pin configuration system  200  in accordance with one embodiment of the present invention. As depicted in  FIG. 2 , system  200  includes a processor  210  including a plurality of functional blocks  211 - 214 . These functional blocks are each communicatively coupled to an always on power domain  230 . System  200  also includes a flexible pin configuration component  240  that is configured to dynamically manage the connectivity of one or more input output pins to communicatively connect the functional blocks  211 - 214  to the multiple peripheral devices  250 . 
         [0026]    In the  FIG. 2  embodiment, the flexible pin configuration component  240  is the interface that enables the multiple functions provided and implemented by the multiple functional blocks  211 - 214  to share a limited number of input output pins. For example, in one embodiment, via the interface provided by the flexible pin configuration component  240 , the multiple functional blocks  211 - 214  can share a single input output pin to deliver their functionality to the peripheral devices  250 , which may themselves also be sharing the single input output pin. 
         [0027]    It should be noted that processor  210  can be used to implement a central processor unit, such as, for example, CPU  101  of  FIG. 1 , or a GPU such as the GPU  110  of  FIG. 1 . The processor  210  can also be part of a programmable system-on-a-chip device. Similarly, the processor  210  can be used to implement an integrated circuit device where the functions of a CPU and the functions of a GPU are combined. 
         [0028]    The power domain  230  provides a mechanism for waking up the processor  210  from a sleep mode. For example, in one embodiment, the power domain  230  is configured to consistently have power applied to its constituent circuits. For example, the constituent circuits of the power domain  230  can be configured to receive a clock signal in an uninterrupted manner so that it can execute sequential state machine logic, instructions, etc. while the rest of the processor  210  is powered down. This can allow, for example, an internal state machine within the power domain  230  to detect wake event signals, the signals indicating a wake up from the sleep mode. For example, in one embodiment, the wake event signals are detected by the AO block (e.g., AO functional block  230 ). This block is on the AO rail. The one or more of the functional blocks  211 - 214  that normally process the events are powered down. Once power is returned, the functional blocks  211 - 214  can process the event, and resume normal operation. 
         [0029]    In accordance with embodiments of the present invention, the one or more input output pins between the flexible pin configuration component  240  and the peripheral devices  250  will have their state reliably maintained even though the functional blocks of the processor  210  are powered down. The state will be maintained such that the entry and exit from sleep mode will be completely transparent to the peripheral devices  250 . 
         [0030]    In one embodiment, different voltage rails are provided to accommodate the different peripheral voltages. For example, a camera can work at one voltage while a WiFi chipset within the camera is working at another voltage. Waking-up from the standard signal of a peripheral (e.g., such as an interrupt) avoids creating additional pads just for this function, which would require a specific voltage choice and voltage translators on the board. So some few selected pads are used as a generic input in the processor active mode but as a wake-up in the processor standby mode, thus at the correct voltage. While some parts of the processor are powered off in standby, the system should be able to power them up again automatically after detecting a wake-up event. In one embodiment, this is done by a hardware control circuit on the AO voltage rail (e.g., AO functional block  230 ). 
         [0031]      FIG. 3  shows a circuit diagram  300  of a flexible pin configuration component in accordance with one embodiment of the present invention. As depicted in the diagram  300  embodiment, the pin configuration component includes an output multiplexer for pin sharing  301 , an output enable multiplexer  311 , an input enable multiplexer  312 , and an input signal line for pin sharing  302 . The multiplexer  301  is coupled a common input output pin (e.g., pad  330 ) via an output buffer  321 . The input buffer  322  drives the input  302  for pin sharing (e.g., shared by multiple functional blocks). The multiplexers  301 ,  311 , and  312  allow multiple functional blocks of a processor (e.g., functional blocks  211 - 214  of  FIG. 2 ) to selectively control the input output pin  330 . For example, the multiplexers  301 ,  311 , and  312  can allow the flexible pin configuration component to dynamically change control of the input output pin  330  between any of a number of different multiple functional blocks. In one embodiment, the selective allocation of the input output pin  330  can be placed under software control, for example as in a case where a control utility or the like executes on the processor to allocate control of the input output pin  330 . The control allocation can be implemented on an as needed basis depending upon whatever function the device might be performing. 
         [0032]      FIG. 4  shows a circuit diagram showing an input output capture component  400  in accordance with one embodiment of the present invention. The capture component  400  includes a flexible pin configuration component operating in conjunction with an output storage element and an input enable storage element in accordance with one embodiment of the present invention. 
         [0033]    In normal operation, the selected function drives the output via the output multiplexer  301  as described above. The output of the multiplexer  301  is coupled to the input output pin  330  via a multiplexer  411  and the buffer  321  as shown. Similarly, in normal operation, the output enable  311  turns on the buffer  321  via the multiplexer  412  as shown. During sleep mode, a sleep mode enable  430  in conjunction with a capture signal  420  causes the storage element  401  and the storage element  402  to store the current value (e.g., logical one, logical zero, etc.) of the output multiplexer  301  and the current value of the output enable signal (e.g., the output enable multiplexer  311  as described above). This causes the input output pin  330  to be driven by the output of the storage element  401 , which would be the previously stored current value from the multiplexer  301 . Thus, after sleep mode entry, the functional blocks driving the inputs of the multiplexer  301  can be inactive. Additionally, in the  FIG. 4  embodiment, the output enable signal itself can be inactive, since its value is stored within the storage element  402 . Upon exit from sleep mode, the sleep mode enable  430  causes the input output pin  330  to resume being driven by the multiplexer  301 , thereby deactivating the storage element  401  and  402 . 
         [0034]    With respect to the input enable  312 , the input enable  312  has its current value saved by the storage element  403  in accordance with the capture signal  420  and the sleep mode enable  430 . Thus, the input enable  312  can control the input buffer  322  even though the functional block that generates the input enable signal  312  is in sleep mode. The input  302  routes signals from the input output pin  330  to be shared by the appropriate functional blocks. 
         [0035]    Thus, embodiments of the present invention limit the use of a central register to store state data for the input output pins of the device. Embodiment of the present invention utilize storage element as described above to enable each pad or input output pin to recall it&#39;s last state. For example, when the software executing on the chip wishes to put the chip in deep sleep mode, it simply cleanly tells each interface (e.g. UART, SPI, HDD, USB etc.) to enter it&#39;s inactive state (if it is not already there) and then asserts a HW signal (e.g., sleep mode enable) to each of the pads to capture their current value (e.g., input, output 0, output 1, hi-Z, open drain, etc.) and hold that value without the core of the chip being awake. Once this is done, the core can safely be powered down into a deep sleep mode. It should be noted that the constituent logic for performing the state retention function is comparatively small, and is located near each signal input output pin. Thus, very few top level signals are required to clock these storage elements, as these signals can be shared for all affected input-output pins, and don&#39;t need to be point to point routed from the always on the core (e.g., core  230  of  FIG. 2 ), thereby minimizing trace routing requirements. The entry and exit for sleep mode is transparent to the peripheral devices. From an external devices&#39; point of view, nothing has happened. The external devices&#39; do not know the CPU has gone to deep sleep, as their inputs are not affected at all. 
         [0036]    It should be noted that in one embodiment, the system  400  is configured such that the output enable  311  is not used to exit the sleep mode. In such a configuration, a separate control register can be utilized to disable the sleep mode on an interface by interface basis. The use of separate control registers to disable the sleep mode provides an advantage in that there can be less impact on signal timing. 
         [0037]      FIG. 5  shows a circuit diagram  500  showing an implementation where multiple capture components  501 - 505  are utilized to capture a variety of different input output signals for an integrated circuit device in accordance with one embodiment of the present invention. 
         [0038]    The  FIG. 5  embodiment shows a case where multiple capture components  501 - 505  are used to capture signals around the integrated circuit device for different selected interfaces. This enables an application where the integrated circuit device can “unlock” just a single selected interface, or group of interfaces. be useful in applications such as where only the LCD needs to wake up to update the time on the display without needing to wake up all other interfaces. This aspect is illustrated in  FIG. 3  where the capture components  501 - 503  are part of a first interface, Capture_A, and the Components  504 - 505  are part of a second interface, Capture_B.  FIG. 5  also shows how to connect multiple pads with this feature to avoid routing a large number of signals around the integrated circuit die, with the input/output and I/O enable signals  520  for each to component  501 - 505  being as illustrated in  FIG. 4 . 
         [0039]    In one embodiment, the de-assertion to re-assertion of the output enable signal for each capture component would switch each output from driving the latched idle state to the value driven from the core once software had reinitialized the peripheral controller to match the idle state. This is necessary for interfaces where the reset state of the controller may not match the idle sate. 
         [0040]    The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.