Abstract:
Methods and apparatus for temperature compensation for hard disk drive writer overshoot current are disclosed. A disclosed system comprises creating a first delay based on the temperature of the hard disk drive, creating a second delay based on the temperature of the hard disk drive, and creating a pulse based on the first and second delay.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure pertains to hard disk drives and, more particularly, to methods and apparatus for temperature compensation for hard disk drive writer overshoot current. 
       BACKGROUND 
       [0002]    A hard drive is a non-volatile storage device that stores digitally encoded data on rotating platters with an associated magnetic surface. As shown in  FIG. 1 , a hard drive  100  includes a spindle  101  that holds at least one platter  102  having a magnetic surface  104 , which spins at a constant speed (e.g., 10,000 revolutions per minute (rpm), 7,200 rpm, or 5,400 rpm). To write data onto a rotating platter, a portion of the magnetic surface  104  is magnetized via a magnetic write head  106 . The write head  106  is coupled with an actuator arm  108  that moves radially across the spinning platters  102 . To create a current pulse to control the write operation, a differential hard drive write system  110  including a hard drive controller  112  is coupled to the write head  106 . The hard drive controller  112  is configured to control the read and/or write operations via a hard drive write system  110 . 
         [0003]    To increase hard drive write speed and capacity, the hard drive write system  110  generates narrow current pulses via a differential control pulse to write information to the magnetic surface  104 . However, as the duration of the current pulse decreases to accommodate increased hard drive speed and storage capacity, the current pulse becomes distorted during transmission to the write head  106 . To correct the distorted edge of the current pulse, the hard drive write system  110  produces current pulses with an overshoot portion to prevent distortion to the leading edge of the current pulse. The overshoot portion is followed by a sustain portion to write information to the platter for the full duration of the write operation. 
         [0004]    As appreciated by a person with ordinary skill in art, the hard drive operation results in a significant amount of heat. Generally, hard drives may achieve temperatures of up to 130° C. The increased temperature of the hard drive affects performance of the devices in the write driver system  110 . Temperature in the hard drive  100  affects performance of devices and causes the parasitics and parameters of the devices to vary either in a linear or non-linear fashion. For example, resistors and stray, parasitic resistances vary over temperature. 
         [0005]    Another example of how device performance varies is an NPN transistor, which experiences reduced switching speed due to increased temperature. In other words, as temperature increases, switching time between transistors increases and results in slower transmission of the overshoot current pulse between devices. As illustrated in  FIG. 1B , the overshoot current pulse  120  has a sharp leading edge  122  and delayed switching time between transistors results the loss and degradation of the leading edge  122 . The solid line illustrated in  FIG. 1B  shows the ideal current pulse, but the dashed line shows how the current pulse degrades with temperature. Consequently, the amplitude and the duration of the overshoot current pulse is reduced in the write drive system. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1A  is an illustration of a known hard drive system. 
           [0007]      FIG. 1B  is an illustration of the degradation of the current pulse due to temperature. 
           [0008]      FIG. 2  is block diagram of an example hard drive write system of  FIG. 1 . 
           [0009]      FIG. 3  is block diagram showing additional detail of the pulse former of  FIG. 2 . 
           [0010]      FIGS. 4A-C  are diagrams illustrating the timing delays of  FIG. 3 . 
           [0011]      FIG. 5  is a diagram showing the example pulses formed by the pulse former of  FIG. 3 . 
           [0012]      FIG. 6  is a schematic diagram showing additional detail of an example implementation of one of the delays of  FIG. 3 . 
           [0013]      FIG. 7  is a block diagram of an implementation of the example pulse generator of  FIG. 2 . 
           [0014]      FIG. 8  is a schematic diagram showing additional detail of an example implementation of the signal generator of  FIG. 7 . 
           [0015]      FIG. 9  is a diagram illustrating the pulses formed by the pulse generator of  FIGS. 7 and 8 . 
           [0016]      FIG. 10  is a schematic diagram showing additional detail of a second example implementation of the pulse generator of  FIG. 7 . 
           [0017]      FIG. 11  is a diagram illustrating example pulses formed by the example pulse generator of  FIG. 10 . 
           [0018]      FIG. 12  is a schematic diagram showing additional detail of the switching device of  FIG. 7  in combination with a pulse generator. 
           [0019]      FIG. 13  is a diagram illustrating example pulses formed by the switching device of  FIG. 12  in combination with a pulse generator. 
       
    
    
     DETAILED DESCRIPTION 
     I. System Overview 
       [0020]      FIG. 2  illustrates an example architecture of a hard drive write system  200 , which may be used to implement an improved version of the hard drive write system  110  of  FIG. 1A . Generally, the hard drive write system  200  includes a pulse former  202 , a signal generator  204 , and a driver  206 . The driver  206  is coupled to one or more of the write heads  208  via a transmission line  210 . The hard drive write system  200  is a differential system that receives a differential write data (W DATA     —     X  and W DATA     —     Y ), which represents the data to be stored on the disk. A person having ordinary skill in the art will readily appreciate that the write data (W DATA     —     X  and W DATA     —     Y ) is complementary such that W DATA     —     Y  is 180 degrees out of phase with W DATA     —     X . Accordingly, a person having ordinary skill in the art will understand that for each complementary pair, there is a complementary circuit that operates identically but with a different input, a different output, and additionally, 180 degrees out of phase. 
         [0021]    In the example hard drive write system  200 , the pulse former  202  receives differential write data (W DATA     —     X  and W DATA     —     Y ) in order to generate pulses to control the signal generator  204 . In one particular example, the pulse former  202  forms three pairs of differential signals: a write control signal (W CONTROL     —     X  and W CONTROL     —     Y ), a write sustain control signal (W SUSTAIN     —     X  and W SUSTAIN     —     Y ), and a write duration control signal (W DURATION X  and W DURATION Y ). The signal generator  204  receives the three pairs of differential control signals generated by the pulse former device  202  and, as explained below, using the three control signals, generates a consolidated current pulse with an overshoot portion and sustain portion. The overshoot portion has a current amplitude substantially equal to a predetermined overshoot value and the sustain portion has a current amplitude that is a portion of the overshoot. 
         [0022]    The signal generator  204  conveys the consolidated current pulse to the driver  206 . A person having ordinary skill in the art will appreciate that the driver  206  conditions the current pulse to be conveyed to the write head  208 . The driver  206  then transmits the current pulse to the write head  208  via the transmission line  210  for the purpose of writing the write data (W DATA     —     X  and W DATA     —     Y ) to the magnetic surface  104  of the platter  102 . 
       II. Example Pulse Former Device 
       [0023]      FIG. 3  illustrates an example pulse former device  202  that generates the differential control signals used by the signal generator  204  in order to generate the consolidated current pulse. For the purpose of forming two control signals, the example pulse former  202  includes delays  302  and  304 . A third delay  306  is further included to generate a third control signal that will be described in detail below. Delays  302  and  304  both receive differential write data (W DATA     —     X  and W DATA     —     Y ). However, delay  302  forms a write sustain signal (W SUSTAIN     —     X  and W SUSTAIN     —     Y ) and delay  304  forms a write control signal (W CONTROL     —     X  and W CONTROL     —     Y ), both of which are described in detail below in conjunction with the signal generator  204 . The delay  306  receives the write control signal (W CONTROL     —     X  and W CONTROL     —     Y ) and forms a write duration control signal (W DURATION     —     X  and W DURATION     —     Y ). 
         [0024]    In the example of  FIG. 3 , the current applied to delays  302 ,  304 , and  306  modifies the time delay between receiving an input and forming a signal. That is, because the current sources  310  and  312  alter the current based on temperature, the delays alter the time delay based on temperature. A person having ordinary skill in the art will readily appreciate that the delays are inversely proportional to the current (i.e., as current increases, the time delay decreases or switching speed increases). 
         [0025]    As previously noted, increased temperature causes signals to propagate slower in the hard drive write system  200 , which causes the current pulse to become distorted before the current pulse is used to write data to the hard disk via the write head  208 . For the purpose of making a linear delay between 0° C. and 130° C. as a function of temperature, the delays  302 ,  304  are powered by a power supply  308  via current sources  310  and  312 , respectively. To selectively alter the current in response to temperature changes and thereby affect delays, the current sources  310  and  312  each have a base current that is modified by an associated temperature coefficient. In the example of  FIG. 3 , current source  310  has a negative temperature coefficient (NTC) and current source  312  has a positive temperature coefficient (PTC). The temperature coefficients of the two current sources are inversely related (e.g., the temperature coefficients are −k 1  and +k 2 ). In other words, the negative temperature coefficient of current source  310  decreases the current provided to the delay  302  as temperature of the hard drive write system  200  increases. Conversely, the positive temperature coefficient of current source  312  increases the current provided to the delay  304  as temperature of the hard drive write system  200  increases. These current changes affect the switching speeds of the delays  302  and  304 . The current sources  310 ,  312  alter the current in a linear fashion over broad temperature ranges. 
         [0026]      FIGS. 4A and 4B  illustrate the time delays associated with delays  302  and  304  as the hard drive write system  200  varies between temperatures of 0° C. and 130° C. In  FIG. 4A , as temperature increases, the current source  310  decreases the current provided to delay  302 . As described above, decreased current causes the delay  302  to increase the time delay of the associated output (W SUSTAIN     —     X  and W SUSTAIN     —     Y ). Conversely, in  FIG. 4B , as temperature increases, the current source  312  increases the current provided to delay  304 . As described above, increased current causes delay  304  to decrease the time delay of the associated output (W CONTROL     —     X  and W CONTROL     —     Y ).  FIG. 4C  illustrates the difference between delay  302  and delay  304 , which is substantially linear between 0° C. and 130° C. The signal generator  204 , using the control signals (e.g., W CONTROL     —     X  and W SUSTAIN     —     X ) provided via delays  302  and  304 , creates a current pulse with an overshoot portion in which the duration of the overshoot portion of the pulse is a linear function of temperature before the pulse is conveyed to the write head  208  (i.e., the overshoot duration is equal to a baseline duration that increases linearly with respect to temperature). However, because loss in the hard drive increases as a function of temperature, the duration of the overshoot portion may be constant or substantially constant when the pulse is received by the write head  208 . 
         [0027]    Delay  306  operates in substantially the same manner as delay  302  and  304 . However, delay  302  receives the output of delay  304  as input for the purpose of providing a third timing control, which is described in detail below. The differential output of delay  306  is accordingly is a write duration control signal (W DURATION     —     X  and W DURATION     —     Y ). 
         [0028]    A. Operation of Example Pulse Former Device 
         [0029]    As shown in the example of  FIG. 5 , when an input signal (e.g., W DATA     —     X ) is received by delay  302 , delay  302  forms a delayed write sustain signal on the output (e.g., W SUSTAIN     —     X ). A person having ordinary skill in the art will readily appreciate that  FIG. 5  depicts only one half of the differential system and that the other half would be identical, albeit 180 degrees out of phase. As illustrated in  FIG. 5 , the time difference between receiving the input signal and forming the output control signal is ΔT 1 . As described above, the time delay of ΔT 1  is inversely related to the current provided to delay  302  (i.e., as current decreases, the time delay increases). Because the current source  310  is associated with a negative temperature coefficient, current provided to delay  302  decreases as temperature increases. Thus, as illustrated in  FIG. 4A , ΔT 1  increases as temperature increases. 
         [0030]    When input data is received by the delay  304 , delay  304  creates a delayed write control signal on the output (e.g., W CONTROL     —     X ). As illustrated in  FIG. 5 , the time difference between receiving the input signal and forming the output control signal is ΔT 2 . Because the current source  312  is associated with a positive temperature coefficient, current provided to delay  304  increases as temperature increases. As described above, the time delay of ΔT 2  is inversely related to the current provided to delay  304  (i.e., as temperature increases, the time delay decreases). Thus, as illustrated in  FIG. 4B , ΔT 2  decreases as temperature increases. 
         [0031]    At an initial temperature, the time delays ΔT 1  and ΔT 2  are set to a baseline delay (e.g., I 1 =n 1 , I 2 =n 2 ) with a baseline time delay. However, as temperature increases, ΔT 1  increases and ΔT 2  decreases, thus the difference between ΔT 1  and ΔT 2  (ΔT DURATION ) increases based on temperature of the hard drive write system  200 . As readily appreciated those having ordinary skill in the art, the delays  302 ,  304 , and  306  vary non-linearly as a function of current. As illustrated in  FIGS. 4A and 4B , because the current sources  310  and  312  vary linearly with respect to temperature, the time delays associated with delays  302  and  304  are non-linear as a function of temperature. However, in one example, the respective amounts of which ΔT 1  and ΔT 2  change are inversely proportional to each other. Consequently, the time difference between ΔT 1  and ΔT 2 , which is illustrated in  FIG. 4C , is substantially linear as a function of temperature. 
         [0032]    At an initial temperature, the time delay between the write control signal and the sustain control signal (ΔT DURATION ) is a predetermined delay. As temperature increases, the delay window changes in two directions by decreasing the delay of the write control signal and increasing the delay of the write sustain signal. If the time delay was altered in one direction by adjusting, the resulting time delay would be non-linear because the delays are non-linear as a function of current. However, due to the time duration being altered in two directions, the non-linear portions of the time delays are substantially cancelled out, resulting in a time delay that is substantially linear as a function of temperature. As will be described below, the control signals cause the signal generator  204  to create the current pulse with an overshoot portion with a duration of ΔT DURATION . Thus, to prevent amplitude loss of the overshoot portion of the current pulse as a result of slower response time in the hard drive write system  200 , the duration of the overshoot portion of the current pulse varies as a function temperature of the hard drive write system  200 . 
         [0033]    B. Description of Example Delay 
         [0034]    More detail of an example delay (e.g., one of the delays  302 ,  304 , or  306 ) is illustrated in  FIG. 6 . However, a person having ordinary skill in the art will recognize the example of  FIG. 6  is also representative of delays  304  and  306 , except for the aspects noted. The delay  302  includes a differential pair of transistors,  602  and  604 . The base of transistor  602  is coupled the input W INPUT     —     X  and the base of transistor  604  is coupled with the input W INPUT     —     Y . The inputs may be write data (e.g., W DATA     —     X ) or control signals (e.g. W CONTROL     —     X ) as illustrated in  FIG. 3 . The emitters of transistors  602  and  604  are coupled with a current sink  606 , which is further coupled to a low output signal, such as a ground. The current sink  606  shunts an amount of current, I DELAY , to the low output signal. I DELAY  is equal to a baseline current adjusted via temperature coefficients, which may be positive or negative depending on the desired delay response to temperature. Thus, I DELAY  may be equal to the following equations: 
         [0000]        I   DELAY   =I   1 −( k   1   ×t ) 
         [0000]        I   DELAY   =I   2 +( k   2   ×t ) 
         [0000]    where I 1  and I 2  are baseline currents, k 1  and k 2  are temperature coefficients, and t is temperature in Celsius. 
         [0035]    The collector of transistor  602  is coupled to a voltage source  608  via a current source  610 . The collector of transistor  604  is coupled to a voltage source  608  via a current source  612 . The current sources  610  and  612  source currents substantially equal to half of the current sink  606 , I DELAY . The output W OUTPUT     —     X  is coupled to the collector of transistor  602  and the output W OUTPUT     —     Y  is coupled to the collector of transistor  604 . Thus, the differential output of the delay  302  is coupled to the respective collectors of the differential pair formed by transistors  602  and  604 , The outputs may be a write control signal, a write duration control signal, or a write sustain signal, depending on the delay and input signal. 
         [0036]    In addition, the example delay illustrated in  FIG. 6  includes four additional devices for the purpose of clamping the output voltage of the delay  302  to a predetermined voltage range. In one example, the voltage clamping prevents saturation of the transistors  602  and  604  by clamping their respective collectors to the predetermined voltage range. In the configuration described below, the transistors  614 ,  616 ,  618  and  620  clamp the output of the delay device to a voltage range based on the first and second voltage threshold. The output of the delay, W OUTPUT     —     X  and W OUTPUT     —     Y , is generated at the collector of transistor  602 ,  604 . In the example of  FIG. 6 , the transistors  614 - 620  are illustrated either as NPN or PNP transistors, but a person having ordinary skill in the art will readily appreciate that any active device known in the art, such as a P-channel metal oxide semiconductor field effect transistor (“mosfet”), a N-channel mosfet, or a digital logic device may be used in the example pulse generator  704 . 
         [0037]    In the configuration illustrated in  FIG. 6 , transistors  614  and  618  are NPN transistors and transistors  616  and  620  are PNP transistors. The collectors of transistor  614  are  618  are coupled with the voltage source  608 . Additionally, the bases of transistors  614  and  616  are both coupled with a first voltage threshold (V T1 ). However, the emitter of transistor  614  is coupled with the collector of transistor  602  and the emitter of transistor  618  is coupled with the collector of transistor  604 . The emitters of transistor  616  and  620  are both coupled with a low output signal such as a ground. The bases of transistor  616  and  618  are coupled to a second voltage threshold (V T2 ). The collector of transistor  616  is coupled to the collector of transistor  602  and the collector of transistor  620  is coupled to the collector of transistor  604 . 
         [0038]    The operation of the example of  FIG. 6  is best described in conjunction with the timing diagram illustrated in  FIG. 5 . As previously described, the input data into the hard drive write system  200  is differential and is therefore complementary (e.g., one input will be a positive voltage and the other input will be a negative voltage). Thus, due to the complementary nature of the differential input into the transistors  602 ,  604 , one of the transistors  602 ,  604  may be biased to couple the respective collector and emitter of the transistor. For example, when W INPUT     —     X  applies a positive voltage of at least a predetermined threshold to the base of transistor  602 , transistor  602  opens a channel for conduction between the base, collector and emitter such that the current will flow through the emitter of transistor  602 . 
         [0039]    In this configuration, the current from current source  610  is shunted via the current sink  606  which causes the output, W OUTPUT     —     Y , to have a low output signal. At the same time, W INPUT     —     X  will apply a bias to transistor  604  such that the respective collector and emitter of transistor  604  are uncoupled. Consequently, the current from the current source  612  flows to the output, W OUTPUT     —     X . The voltage of the output (W OUTPUT     —     X ) will be based on the first and second voltage thresholds (V T1  and V T2 ). With regards to the reverse operation (e.g., W INPUT     —     X  has a positive voltage and W INPUT     —     Y  has a negative voltage), W OUTPUT     —     X  has a low output signal and W OUTPUT     —     Y  has an output based on the current source  610  and the first and second voltage thresholds (V T1  and V T2 ). 
         [0040]    As appreciated by person of ordinary skill in the art, the transistors  602 ,  604  do not immediately couple their respective collector, base and emitter when a signal is applied to the base of the transistor that causes the transistor to be biased. Rather, there is a brief time delay that is inversely proportional to the current provided to the collector. A person with skill in the art will readily appreciate that the time delay may be described by the following equation: 
         [0000]    
       
         
           
             
               T 
               DELAY 
             
             = 
             
               
                 
                   ( 
                   
                     
                       V 
                       
                         T 
                          
                         
                             
                         
                          
                         1 
                       
                     
                     - 
                     
                       V 
                       
                         T 
                          
                         
                             
                         
                          
                         2 
                       
                     
                   
                   ) 
                 
                 × 
                 
                   C 
                   P 
                 
               
               
                 
                   A 
                   * 
                   
                     I 
                     DELAY 
                   
                 
                 + 
                 
                   
                     B 
                     2 
                   
                   * 
                   
                     I 
                     DELAY 
                   
                 
               
             
           
         
       
     
         [0000]    where V T1  and V T2  are the first and second clamp voltages, C P  is the parasitic capacitance of the devices coupled to the collector of transistors  602 ,  604 , I DELAY  is the current of the current sink  606 , and both A and B are coefficients. That is, as current decreases, the time to couple the collector and emitter of the transistor  602  and  604  increases non-linearly. Thus, by varying current to the transistors  602 ,  604 , the example delay device may delay the output of the delay devices  302 . As described above, the description is above is exemplary for the delay device  302 . However,  FIG. 6  is also representative of delay devices  304  and  306  which function the same way, albeit different currents (i.e., delays  302  and  306  use different currents in order to have different time delays). 
       III. Example Signal Generator 
       [0041]      FIG. 7  illustrates an example signal generator  204 , which may include a pulse generator  702  coupled with a switching device  704 . The pulse generator  702  receives a differential control input (W CONTROL     —     X  and W CONTROL     —     Y ) and a differential sustain input (W SUSTAIN     —     X  and W SUSTAIN     —     Y ). As previously described, each differential pair is complementary and 180 degrees out of phase. In response to these inputs, the pulse generator  702  produces a differential current pulse (I PULSE     —     X  and I PULSE     —     Y ) with two current amplitudes (i.e., the overshoot portion and the sustain portion). The switching device  704  receives the current pulse generated by the pulse generator  704 . As will be described in detail below, the switching device  704 , using a differential biasing input (W DURATION     —     X  and W DURATION     —     Y ), truncates the output current pulse by shunting the input of the switching device with a low output signal such as a ground. 
         [0042]    A. Example Pulse Generator and Switching Device 
         [0043]      FIG. 8  illustrates a schematic diagram of an example pulse generator  702  that also implements the switching device  704  of  FIG. 7 . The example pulse generator  704  receives two pairs of differential control signals generated by the pulse former  202  to generate a current pulse on the output (I OUT     —     X  and I OUT     —     Y ). For the purpose of generating a current pulse, the example pulse generator  702  receives a write control signal (W CONTROL     —     X  and W CONTROL     —     Y ). In order to stop generating the pulse, a write sustain signal is provided (W SUSTAIN X  and W SUSTAIN Y ). In the example of  FIG. 8 , the example pulse generator  704  does not receive a third differential input (W DURATION     —     X  and W DURATION     —     Y ) as illustrated in  FIG. 2 . As will be described below in the example  FIG. 8 , the write control input (W CONTROL     —     X  and W CONTROL     —     Y ) is received by a differential transistor pair for the purpose of selectively coupling a current source to an output of the pulse generator  704 , thus generating a current pulse. Another differential transistor pair receives the write sustain signal (W SUSTAIN     —     X  and W SUSTAIN     —     Y ) for the purpose of selectively removing the current from the output, thus ending the generation of the current pulse on the output. 
         [0044]    1. Description of the Example Pulse Generator 
         [0045]    As shown in  FIG. 8 , the write control signal (W CONTROL     —     X  and W CONTROL     —     Y ) is received by a buffer  814  and the write sustain signal (W SUSTAIN     —     X  and W SUSTAIN     —     Y ) is received by a buffer  816 . A person having ordinary skill in the art will recognize the buffers  814 ,  816  condition the input signals in order to properly drive the devices of the pulse generator  704 . Additionally, the pulse generator  704  includes transistors  820 ,  822 ,  826 ,  828 ,  832 , and  834 . In the example of  FIG. 8 , the transistors  820 - 834  are illustrated either as NPN or PNP transistors, but a person having ordinary skill in the art will readily appreciate that any active device known in the art, such as a P-channel mosfet, a N-channel mosfet, or a digital logic device may be used in the example pulse generator  704 . Additionally, the transistors  820 - 834  may have the same rise time (i.e., the time associated between coupling and uncoupling the collector and emitter of the transistor). 
         [0046]    Transistors  820  and  824  serve as a differential pair having their respective emitters coupled to a current source  804 . Transistors  826  and  828  serve as a differential pair having their respective emitters coupled to a current source  806 . The base of transistor  820  and the base of transistor  828  are coupled to W CONTROL     —     X  via buffer  816 . The base of transistor  822  and the base of transistor  826  are coupled to W CONTROL     —     Y  via buffer  816 . The collector of transistor  820  is coupled with the output of signal generator  704  (I OUT     —     X ) and the collector of transistor  822  is coupled with a low output signal such as a ground. The collector of transistor  826  is coupled with the output of signal generator  704  (I OUT Y ) and the collector of transistor  828  is coupled with a low output signal such as a ground. 
         [0047]    In the example of  FIG. 8 , the emitter of transistor  832  and the emitter of transistor  836  are coupled to a current source  802 , which sinks a current of I OS . Additionally, the base of transistor  832  is coupled to W SUSTAIN     —     Y  via buffer  814  and the base of transistor  836  is coupled to W SUSTAIN     —     X  via buffer  814 . The collector of transistor  832  is coupled to the emitters of transistors  820  and  822 . Furthermore, a current source  804  is coupled to the emitters of transistor  820 , the emitter of transistor  822 , and the collector of transistor  832 . The current source  804  provides a current of I OS     —     X , which is substantially equal to I OS . The collector of transistor  836  is coupled to the emitters of transistors  826  and  828 . Furthermore, a current source  806  is coupled to the emitter of transistor  826 , the emitter of transistor  828 , and the collector of transistor  836 . The current source  806  provides a current of I OS     —     Y , which is substantially equal to I OS . 
         [0048]    The operation of the example pulse generator  704  is best described in conjunction with  FIG. 9 , which illustrates the input and output of the pulse generator  704 . Initially, at time T 0 , the voltage received by the base of transistor  822  is greater than the voltage received by the base of transistor  820 , thus the current source  804  (I OS     —     X ) is shunted to the low output signal via transistor  822 . In other words, there is no current output of the pulse generator  704  via I OUT     —     X  at time T 0 . At the same time, the voltage received by the base of transistor  836  is less than the voltage received by the base of transistor  832 , thus, due to the PNP configuration of  FIG. 8 , the current source  802  (I OS ) is not coupled to the collector of emitter of transistor  820  and the emitter of transistor  822 . Rather, the current source  802  sinks the current from current source  806  via transistor  836 . In other words, the current source  806  is not coupled with the emitter of transistor  826 . Accordingly, at time T 0 , the signal generator does not generates a current pulse via the output, I OUT     —     X . 
         [0049]    In the example of  FIG. 9 , at time T 2 , the voltage received by the base of transistor  822  (W CONTROL     —     Y ) is reduced and less than voltage received by the base of transistor  820  (W CONTROL     —     X ). As a result, transistor  820  couples the output (I OUT     —     X ) with the current source  804  at time T 2 , thus generating a current pulse substantially equal to I OS  via the output, I OUT     —     X . Additionally, the voltage received by the base of transistor  832  is greater than the base voltage of transistor  834 , thus transistor  832  does not couple its respective collector and emitter. In other words, the current source  802  is not coupled with the emitter of transistor  820 . Accordingly, at time T 2 , the pulse generator  704  generates a current pulse via the output, I OUT     —     X . 
         [0050]    At time T 3 , the transistors  822  and  820  have not changed since time T 1  and the output (I OUT     —     X ) remains coupled with the current source  804 . However, the voltage received by the base of transistor  832  is reduced to less than the voltage received by the base of transistor  834 , which thus removes the coupling between current source  806  and current source  802  and instead couples current source  804  with current source  802 . In other words, the current source  802  steals the current from current source  804  and transistor  820  and causes the pulse generator  704  to stop generating a current output via I OUT     —     X . Thus, at time T 3 , the signal generator stops generating a current pulse via I OUT     —     X  when W SUSTAIN     —     X  causes the current source  802  to steal the current. 
         [0051]    The operation of the example pulse generator  704  thus operates by selectively coupling the current sources  804  with the output of the signal generator (I OUT     —     X ) when the control signal (W CONTROL     —     X ) rises. However, when the sustain signal (W SUSTAIN     —     X ) rises, the current provided by current source  804  is stolen by the current source  802 , thus ending the current generated on the output (I OUT     —     X ). That is, a current is generated on the output of the pulse generator  704  when W CONTROL     —     X  rises and stops generating the current when W SUSTAIN     —     X  rises. With respect to the output I OUT     —     Y , as previously discussed, the control inputs and sustain inputs are differential and 180 degrees out of phase, thus the same operation would occur with respect to the second output, I OUT     —     Y . 
         [0052]    B. Second Example Pulse Generator 
         [0053]    Referring back to  FIG. 7 , a second example pulse generator  704  will be described. In the second example, the pulse generator  702  produces a consolidated pulse with two current amplitudes (the overshoot portion and the sustain portion). The write control signals (W CONTROL     —     X  and W CONTROL     —     Y ) cause the pulse generator  702  to produce a current pulse on the outputs (I PULSE     —     X  and I PULSE     —     Y ) with a first pulse amplitude substantially equal to a current overshoot. The write sustain signals (W SUSTAIN     —     X  and W SUSTAIN     —     Y ) are precisely timed to lag the write control signals (W CONTROL     —     X  and W CONTROL     —     Y ) in order to produce the sustain portion of the consolidated current pulse. In other words, the write sustain signals cause the pulse generator  702  to reduce the current of the current pulse for the duration of the control inputs (W CONTROL     —     X  and W CONTROL     —     Y ). 
         [0054]    The pulse generator  702  thus generates current pulses that are conveyed to the switching device  704  via I PULSE     —     X  and I PULSE     —     Y . The switching device  704  also receives the write duration signals (W DURATION,     —     X  and W DURATION,     —     Y ) as biasing inputs in order to selectively couple the pulse generator  702  to the outputs of the switching device  704  (I OUT     —     X  and I OUT     —     Y ). Alternatively, the biasing inputs may also selectively couple the pulse generator  702  with a low output signal such as a ground. In one example, the biasing inputs (W DURATION     —     X  and W DURATION     —     Y ) may bias the switching device  704  to convey a portion of the consolidated current pulse to the driver device  206  and a portion of the consolidated current pulse to the low output signal, thereby truncating the duration of the consolidated current pulse generated by the pulse generator  702 . 
         [0055]    1. Example Pulse Generator 
         [0056]    A second example pulse generator  702  is shown in  FIG. 10 . The example of  FIG. 10  is a pulse generator  704  similar to the first example of  FIG. 8 . However, a current sink  1002  is provided to shunt a portion of the current provided by current sources  804  and  806  (i.e., current sink  1002  sinks a percentage of I OS ). In other words, the example of  FIG. 10  functions as described in conjunction with the first example of  FIG. 8 . However, because the example of  FIG. 10  does not shunt the entire current from current sources  804  and  806  via the current sink  1002 , the pulse generator  702  does not end the generation of the pulse. Instead, the pulse generator  702  steals a portion of the current, thus reducing the current of the pulse rather than ending generation of the current pulse. In other words, the second example pulse generator  702  produces a consolidated pulse having a first overshoot current and a second sustain current. 
         [0057]    i. Operation of the Signal Generator 
         [0058]    The current pulse generated by the example pulse generator  702  of  FIG. 10  is best described in reference to the timing diagram exhibited in  FIG. 11 .  FIG. 11  illustrates the timing diagram of the pulse generator  702  with the output of the pulse generator  702  illustrated as I PULSE . A person having ordinary skill in the art will readily appreciate that the pulse generator  704  is a differential system and that  FIG. 11  does not illustrate the complementary inputs and outputs of the differential pulse generator  704 . 
         [0059]    As described above, on the rising edge of the write control signal (W CONTROL     —     X  or W CONTROL     —     Y ) at time T 1 , the pulse generator  702  generates a current via the associated output (I PULSE     —     X  or I PULSE     —     Y ). The current of the pulse is substantially equal to an overshoot value, I OS . On the rising edge of the sustain input (W SUSTAIN     —     X  or W SUSTAIN     —     Y ) at time T 2 , as described above, the pulse generator  702  reduces the output current (I PULSE     —     X  or I PULSE     —     Y ) to a portion of I OS . In the example of  FIG. 11 , when the control input (W CONTROL     —     X  or W CONTROL     —     Y ) falls at time T 3 , the pulse generator  702  stops generating current on the output (I PULSE     —     X  or I PULSE     —     Y ). In other words, a current pulse with an overshoot current amplitude is generated on the output (I PULSE     —     X  or I PULSE     —     Y ) which has substantially the same pulse duration of the control input (W CONTROL     —     X  or W CONTROL     —     Y ), but the amplitude is reduced when the sustain input (W SUSTAIN     —     X  or W SUSTAIN     —     Y ) removes a portion of the current. Thus, the pulse created by the pulse generator  702  is a consolidated overshoot and sustain pulse. 
         [0060]    2. Example Switching Device 
         [0061]    Referring back to  FIG. 7 , a switching device  704  is coupled with the pulse generator  704 . The switching device  704  receives a current pulse via a differential input (I PULSE     —     X  or I PULSE     —     Y ). Using a biasing input, the switching device selectively couples the input with either the driver  206  (i.e., I OUT     —     X  and I OUT     —     Y ) or a low input signal such as a ground. As illustrated in example of  FIG. 7 , the biasing input (W DURATION     —     X  or W DURATION     —     Y ) controls the duration of the current pulse conveyed to the driver  206 .  FIG. 12  illustrates a schematic for an example switching device  704 . A person having ordinary skill in the art will readily appreciate that the switching device  704  is a differential system, and accordingly only one of the differential operation will be described because the second differential operation is identical to the first, albeit 180 degrees out of phase. 
         [0062]    The example pulse generator in  FIG. 12  depicts a first pulse generator, such as a pulse generator illustrated in  FIG. 10 . The pulse generator is coupled with the switching device  704 . The switching device  704  consists of four switching devices: NPN bipolar transistors  1202 ,  1204 ,  1206  and  1208 . However, the switching devices may be of any type of device known in the art that can be configured to control the switching device  704  via biasing inputs. For example, the switching devices may be PNP or NPN bipolar transistors, heterojunction bipolar transistors, P-channel or N-channel field effect transistors, or digital logic gates. 
         [0063]    As shown in the example of  FIG. 12 , the emitter of both transistors  1202  and transistor  1204  are coupled to the differential input of the switching device, I PULSE     —     X  and I PULSE     —     X , respectively. The base of transistor  1202  is coupled to W DURATION     —     Y  and the base of transistor  1204  is coupled to the biasing input, W DURATION     —     X . The collector of transistor  1202  is coupled to I OUT     —     X  and the collector of transistor  1204  is coupled to a low output signal (e.g., a ground, a system ground, etc). Additionally, the emitter of transistor  1206  and the emitter of transistor  1208  are coupled to I PULSE     —     Y . The base of transistor  1206  is coupled to W DURATION     —     X  and the base of transistor  1208  is coupled to W DURATION     —     Y . The collector of transistor  1206  is coupled to I OUT     —     Y  and the collector of transistor  1208  is coupled to a low output signal (e.g., a ground, a system ground, etc). 
         [0064]    As previously described, the biasing inputs of switching device  704  (W DURATION     —     X  and W DURATION     —     Y ) is the differential write duration control signal generated by pulse former device  202 . Thus, W DURATION     —     X  and W DURATION     —     Y  are complementary and 180 degrees out of phase. The biasing inputs applied to the bases of the transistors  1202 ,  1204 ,  1206 , and  1208  via W DURATION     —     X  and W DURATION     —     Y  may bias the transistors such that the transistors  1202 - 1208  couple their respective collector and emitter, thus conducting signals between their respective collector and emitter. A person having ordinary skill in the art will appreciate that the illustrative example is just one of many configurations that can achieve the result described herein. 
         [0065]    Turning now the operation of transistor  1202  and  1204 , the emitters of both transistors are both coupled to I PULSE     —     X  and are best explained in operation together in reference to  FIG. 13 . Presuming that W DURATION  shown in  FIG. 13  is representative of W DURATION     —     X , and then at time T 0 , W DURATION     —     Y  has a positive voltage because it is inversely related to W DURATION     —     X . W DURATION     —     Y  thus applies a voltage to the base of transistor  1202  to bias the transistor  1202 . As a result of the biasing applied to transistor  1202 , a channel for conduction between the collector and emitter of transistor  1202  is opened and thus couples I PULSE     —     X  with I OUT     —     X . Thus, as illustrated in  FIG. 13 , signals may be may be conveyed to I OUT     —     X  via I PULSE     —     X . Now turning to transistor  1204 , the voltage applied to base of transistor  1204  via W DURATION     —     X  does not bias the transistor, and thus the transistor  1204  prevents conduction between the emitter and collector. 
         [0066]    Now turning to time T 3 , due to the complementary nature of the differential biasing inputs, W DURATION     —     Y  falls and W DURATION     —     X  rises. That is, W DURATION     —     X  applies a biasing voltage to transistor  1204  to couple the emitter and collector of transistor  1204 . At the same time, W DURATION     —     Y  applies a voltage to the transistor  1202  that does not bias the transistor  1202 . In other words, the transistor  1204  couples I PULSE     —     X  with a low output signal such as a ground, which shunts any current to the low output signal after time T 3 . As illustrated in  FIG. 13 , the current pulse associated with I OUT     —     X  is truncated based on the write duration control signal. The operation of transistors  1202  and  1204  can be summarized by the following: when W DURATION     —     Y  biases transistor  1202 , I OUT     —     X  is coupled to I PULSE     —     X , and thus the signal generator  204  is coupled with the driver  206 . Likewise, when W DURATION X  is not biased, the I PULSE     —     X  output of the signal generator  204  is coupled to a low output signal. 
         [0067]    As previously described, the switch accepts differential control signals that are 180 degrees out of phase. A person having ordinary skill in the art will readily appreciate that the operation of the transistor  1206  and  1208  pair works identical to the transistor  1202  and  1204  pair except the output of the pair is either I OUT     —     Y  or a low output signal such as a ground. Additionally, the I PULSE     —     Y  may be coupled I OUT Y  such that the differential output of switching device  804  (I OUT X  and I OUT     —     Y ) are 180 degrees out of phase with each other. 
         [0068]    In addition, although certain methods, apparatus, and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all apparatuses, methods and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.