Abstract:
A temperature-compensated output buffer is disclosed that incorporates a temperature-compensating network into a GaAs output buffer that has been interfaced to Silicon-based circuitry to regulate the output voltage of the buffer under changing temperature conditions. The temperature-compensating network includes a differential amplifier whose output varies with temperature due to a network of series-connected Schottky diodes. The output of the differential amplifier controls a bleeder MESFET that controls the output voltage of the buffer so that temperature variations do not adversely affect the buffer output.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to circuits that electrically compensate for temperature changes, and, more specifically, to circuits that compensate for signal errors induced by temperature changes when a circuit including GaAs elements is interfaced with a circuit containing Silicon-based elements. 
     2. Description of the Related Art 
     The majority of electronic systems in production and use today are made using Silicon technology. A systems designer who wants to produce the fastest circuit possible using Silicon-based components would likely use emitter-coupled logic circuitry (ECL), which also provides the advantage of low power consumption. 
     Faster technologies exist, however, including the popular III-V technology using the likes of Gallium Arsenide (GaAs). GaAs circuits and components, however, suffer from fragility during manufacture, and, thus, are relatively expensive Until GaAs chips are available at lower cost, they will be short in both supply and variety. A designer, therefore, must integrate GaAs technology into ECL circuitry to achieve the highest-speed circuits until GaAs chips are more plentiful. 
     A problem exists, however, when interfacing the two technologies. Silicon chips behave differently than do GaAs chips when both are operated in the same temperature-varying environment. Since electronic circuits inherently produce heat, the difference in electrical behavior between Silicon chips and GaAs chips in the same circuit due to temperature effects must be compensated. The present invention is designed to obviate the problem. 
     SUMMARY OF THE INVENTION 
     The present invention incorporates a temperature-compensating network into a GaAs output buffer interfaced to Silicon-based circuitry to regulate the output voltage and current of the buffer under changing temperature conditions. The buffer includes a differential amplifier stage, an output stage, and the temperature-compensating network that responds with temperature to vary the current and voltage on the output of the differential amplifier stage so that the differing temperature characteristics of GaAs with respect to silicon is properly compensated. 
     The entire buffer, including the differential amplifier stage, the output stage, and the temperature-compensating network, is designed using metal-semiconductor field-effect transistors (MESFETs) as the control and switching elements. The temperature-compensating network includes a differential amplifier and two voltage dividers whose node voltages vary differently with temperature. The output of the temperature-compensating network differential amplifier controls the gate of a &#34;bleeder&#34; MESFET, which channel is connected to the line connecting the buffer differential amplifier to the output stage. As temperature rises, the bleeder FET shunts less current away from the buffer differential amplifier output line so that a higher output buffer voltage results, in accordance with interface requirements of Silicon ECL technology. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 shows an electrical circuit designed in accordance with the teachings of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows in detail a preferred embodiment of the present temperature-compensated GaAs output buffer. Output buffer 4 includes differential amplifier stage 6 and output stage 8, the transistors of which are all preferably GaAs MESFETs. The high speed of GaAs components makes them desirable for use in a variety of systems. GaAs circuits, however, respond to variations in temperature differently than do circuits fabricated using Silicon technology. Since GaAs is very expensive at present, and very fragile during chip or wafer manufacture, circuits using GaAs chips are used sparingly. Where used, they must be interfaced with surrounding circuitry so that the effects of temperature variations are reflected uniformly throughout the circuit. 
     For this reason, the present invention includes temperature-compensating network 10, which operates in conjunction with MESFET T 6  to regulate the voltage appearing on buffer differential amplifier output line 14 in response to variations in temperature. 
     In preferred form, output buffer 4 interfaces with a following Silicon-based circuit stage 2. Differential amplifier 6 comprises MESFETs T 1  and T 2 , whose drains are connected to power supply V H  via resistors R 1  and R 2 , respectively. The sources of T 1  and T 2  are connected in common to power supply V L  via MESFET T 3 , which has its gate tied to its source in a known constant-current configuration. The output of stage 2 controls the gate of T 1 , while the gate of T 2  is tied to a reference voltage on the order of -2.6 V. 
     The output of differential amplifier 6 appears at node 14, and is a function of the difference in gate voltages between T 1  and T 2 . Node 14 controls the gate of MESFET T 4 , of output stage 8. The drain of T 4  is connected to V H  MESFET T 5  has its gate tied to its source between the source of T 4  and V L . 
     Temperature-compensating network 10 comprises differential amplifier 16, voltage dividers 18 and 20, and &#34;bleeder&#34; MESFET T 6  . Differential amplifier 16 includes MESFETs T 7  and T 8 , whose drains are tied to V H  via resistors R 3  and R 4 . The sources of T 7  and T 8  are tied in common to V L  via MESFET T 9 , which has a constant-current configuration similar to T 3 . 
     Voltage divider 18 comprises resistor R 5  in series with three series Schottky diodes D 1 , D 2  and D 3 . Three diodes are preferable by design, although the circuit will operate substantially as designed using fewer or more diodes. Moreover, diodes other than Schottky diodes may perform similarly, but Schottky diodes are preferred for their speed and for their simplicity of manufacture. Node 22 controls the gate of T 7 . Similarly, reference voltage divider network 20 comprises resistors R 6  and R 7 , with node 24 tied to the gate of T 8 . The terminals of resistors R 5  and R 6  that do not comprise nodes 22 and 24, respectively, are tied to V H . 
     The output of network 10 is taken from node 26, and controls the gate of bleeder FET T 6  . As temperature increases, the voltages at nodes 22 and 24 differ due to the differing temperature coefficients of the diode network and the resistors. Increased temperature causes decreased voltage at node 22 with respect to node 24, since the series resistance of diodes D 1 , D 2  and D 3  decreases with increasing temperature. The ratio of resistances R 5  /R D , where R D  is the series resistance of the Schottky diodes, increases in comparison to the ratio R 6  /R 7 . Consequently, the voltage differential between the gates of T 7  and T 8  changes in favor of T 8 , resulting in a decrease in voltage at node 26 (more negative). 
     The decreasing voltage on node 26 increases the resistivity in the channel of bleeder FET T 6 , which results in decreased conductivity of the channel. As the channel conductivity decreases, the portion of the current drawn from line 14 also decreases. The current drawn through R 2  likewise decreases, resulting in a smaller voltage drop across R 2 , and thus a higher voltage on line 14. Network 10 thus operates to vary the voltage and current on line 14 to make the GaAs buffer compatible with the ECL Silicon circuit. 
     In the circuit just described, V H  and V L  are set at levels consistent with conventional ECL technology. For example, V H  may be set to OV, and V L  to -5.2V. Resistors may comprise resistive regions in the monolithic circuit or may be constructed using FETS having gates tied to sources. The various MESFET pairs are preferably matched for balanced differential pair operation. 
     The output swings for V OH  and V OL  vary with temperature, of course, and for ECL 10,000 family, V OH  preferably ranges from -930 mv to -1080 mV at -55.C ° C.; from -810 m V to -960 mV at 25° C.; and from -660 mV to -810 mV at 125° C. V OL  preferably ranges from -1770 mV to -1970 mV at -55° C.; from -1650 mV to -1850 mV at 25° C.; and from -1575 mV to -1775 mV at 125° C. The temperature coefficient of V OH  is thus about 1.5 mV/° C.; for V OL  is about 0.75 mV/° C. 
     The use of MESFETs instead of conventional JFETs, depletion-mode MOSFETs or other suitable devices is a design choice made in light of the speed advantages achieved by MESFETs. The higher carrier mobilities and carrier saturation velocities of III-V semiconductors such as GaAs or InP in MESFETs give these advantages, making MESFETs especially useful in high-speed digital or microwave applications. Furthermore, GaAs chips can be operated at higher temperatures, and thus higher power levels, than can Silicon chips, and, since no diffusions are necessary (although possible) in MESFETs, close geometrical tolerances may be achieved and the MESFETs made very small. This is especially important at high frequencies, where drift time and stray capacitances must be kept to a minimum. 
     Various modifications to the invention described above will become apparent to those skilled in the art. All such modifications that basically rely on the teachings through which the invention has advanced the art are properly considered within the spirit and scope of the invention.