Abstract:
A high frequency semiconductor module, includes: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2002-240529 filed on Aug. 21, 2002; the entire contents of which are incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor module, a semiconductor device, and a manufacturing method of a semiconductor module. In particular, it relates to a manufacturing method that reduces the ground inductance of a high frequency circuit. 
     2. Description of the Related Art 
     Compound semiconductors such as a gallium arsenide (GaAs) and the like have superior characteristics including a favorable high-speed operation capability and a favorable power conversion efficiency as compared to silicon (Si). Development and implementation is progressing regarding a monolithic microwave integrated circuit (MMIC), an integrated high frequency circuit that utilizes such characteristics of compound semiconductors. A power amplifier module is a kind of MMIC that uses, for example, gallium arsenic hetero-junction bipolar transistors (HBT), and is widely used in equipment such as mobile phones. As the size of such equipment is reduced, demand has emerged for reducing the size of built in semiconductor devices therein. MMICs that meet these demands are being fabricated. However, the problem of parasitic impedance in ground wiring and the like may occur in reducing the size of semiconductor devices. In high frequency circuits, the parasitic impedance of wiring connecting the semiconductor device, and in particular ground wiring, affects the high frequency characteristic. For example, as shown in FIG. 1, the connection between a signal pad  112  and a ground pad  111  formed on a semiconductor device, and a signal line  107  and a ground  105 , respectively, on a mounting substrate  103  is implemented by bonding wires  118   a  and  118   b . Since the ground connection between the semiconductor device on a semiconductor chip  121  and the mounting substrate  103  is made by the bonding wire  118   b , ground inductance increases and the power gain of the power amplifier module deteriorates. In order to solve such problems regarding ground inductance, through-holes formed in the semiconductor substrate are used for the connection between the ground pad formed on a top surface of the semiconductor chip and the ground of the mounting substrate. With this method, after thinning semiconductor substrate, the through-holes are formed so as to pass through the semiconductor substrate from a bottom surface to the top surface, and a gold plating is formed on the entire area of the bottom surface of the semiconductor chip. It is thereby possible to make a ground connection without using wires, and ground inductance is drastically reduced. Nevertheless, this leads to a significant drop in yield since complicated processes are needed on a very thin semiconductor substrate, including a photolithography process on the bottom surface, an etching process to form the through-holes, and a plating process for the bottom surface. To avoid an etching process in forming the through-holes in a semiconductor substrate that already has been thinned, a proposed method includes, first forming through-holes in the top surface of the semiconductor substrate, forming a gold plated layer within each through-hole, polishing the bottom surface of the semiconductor substrate to expose the gold plated layer, and then forming a metal layer on the whole area of the bottom surface. However, with this method as well, the etching process to form the through-holes in the semiconductor substrate is necessary. Also, since process controlling in forming a cross-section of the through-holes appropriate for metallic filling is further required, complexity is not eliminated. Moreover, since individual chips are separated following formation of the metallic layer on the bottom surface of the thin semiconductor substrate, such a method causes yield to drop. 
     Thus the ground inductance may increase caused by the bonding wire with the earlier mounting configuration of high frequency semiconductor devices such as MMIC. In order to reduce the ground inductance, methods have been proposed to form the through-holes in a thin semiconductor substrate. However, a complicated process forming the through-holes or the like are required, in addition to regular fabrication processes for the semiconductor device. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention inheres in a semiconductor module including: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal. 
     A second aspect of the present invention inheres in a semiconductor device including: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element arranged on the top surface; and a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip. 
     A third aspect of the present invention inheres in a manufacturing method for a semiconductor module including: fabricating semiconductor elements and ground pads of the semiconductor elements, on a top surface of a semiconductor substrate; physically forming isolation trenches in isolation regions configured to divide the semiconductor substrate into a plurality of semiconductor chips; depositing a metal layer configured to connect to the ground pad and extend to the isolation trenches; separating the semiconductor substrate into the semiconductor chips at the isolation trenches by polishing a bottom surface of the semiconductor substrate across bottoms of the isolation trenches; disposing a conductive material to a ground metal arranged on a mounting substrate; and mounting one of the semiconductor chips on the conductive material configured to connect the metal layer with the ground metal with the conductive material. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional mounting configuration of a semiconductor chip; 
     FIG. 2 is a schematic diagram showing the mounting configuration of a semiconductor chip on a semiconductor module according to an embodiment of the present invention; 
     FIGS. 3A through 3F are cross-sectional diagrams describing the manufacturing process of a semiconductor chip according to an embodiment of the present invention; 
     FIG. 4 is a top view of a block diagram of a semiconductor chip according to an embodiment of the present invention; 
     FIG. 5 is a schematic diagram showing the mounting configuration of a semiconductor chip on a semiconductor module according to an embodiment of the present invention; 
     FIG. 6 is a schematic diagram showing the mounting configuration of a semiconductor chip on a semiconductor module according to an embodiment of the present invention; and 
     FIG. 7 is a top view of a block diagram of a semiconductor chip according to a modified example of the present invention. 
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. 
     A semiconductor device scheduled to be assembled in a semiconductor module according to an embodiment of the present invention includes, shown in FIG. 2 corresponding to a cross sectional view at IV—IV line in FIG. 4, a semiconductor chip  21   a  having top and bottom surfaces, a semiconductor element merged in the semiconductor chip  21   a , signal line pads  12   a  and  12   b  and ground pads  11   a  and  11   b  of the semiconductor element arranged on the top surface, and a ground metal layer  26  connected to the ground pads  11   a  and  11   b  and arranged so as to cover sidewalls of the semiconductor chip  21   a.    
     The semiconductor element (omitted from the drawing) is merged in the semiconductor chip  21   a  so as to form an MMIC. The ground pads  11   a  and  11   b  and signal line pads  12   a  and  12   b  are fabricated from a metal film such as gold (Au) or aluminum (Al). The electrical connections of the ground pads  11   a  and  11   b  and the signal line pads  12   a  and  12   b  are respectively made through openings provided on an insulating film  13   a , such as a silicon oxide (SiO 2 ) film or a silicon nitride (Si 3 N 4 ) film. A ground foundation layer  25   a  such as a gold/titanium (Au/Ti) film is deposited on the ground pads  11   a  and  11   b  so as to cover the sidewalls of the semiconductor chip  21   a  via the insulating film  13   a , and a ground metal layer  26   a  made of a gold plated layer, is further deposited upon the ground foundation layer  25   a . The semiconductor chip  21   a  is placed onto a ground metal  5  made from a metal film such as a gold, on the mounting substrate  3  made of an insulator substrate such as an alumina substrate, and the ground pads  11   a  and  11   b  of the semiconductor chip  21   a  and the ground metal  5  of the mounting substrate  3  are connected using a conductive material  17  such as a silver (Ag) paste in contact with the ground metal layer  26   a  on the sidewalls of the semiconductor chips. In addition, the signal line pads  12   a  and  12   b  of the semiconductor chip  21   a  are connected to the signal lines  7   a  and  7   b  with a metal film such as gold, on the mounting substrate  3 , through bonding wires  18   a  and  18   b  made of gold wires and the like. With the mounting substrate  3  according to the embodiment of the present invention, since the ground pads  11   a  and  11   b  of the semiconductor chip  21   a  are connected to the ground metal  5  of the mounting substrate  3  by the conductive material  17  in contact with the ground metal layer  26   a , there is no longer any need for bonding wires to make the ground connection between the semiconductor chip  21   a  and the mounting substrate  3 , and accordingly, ground inductance may be reduced. Moreover, as bonding pads for the ground wiring are no longer necessary, dimensions of the semiconductor chip  21   a  and the mounting substrate  3  may be reduced. 
     A manufacturing process for the semiconductor chips  21   a ,  21   b ,  21   c , . . . according to the embodiment of the present invention is now described using cross-sectional views, shown in FIGS. 3A-3F. 
     (a) As shown in FIG. 3A, the MMIC (omitted from the drawing) including the HBT, and the ground pads  11   a ,  11   b ,  11   e , and  11   f  and the signal line pads  12   a ,  12   b ,  12   e , and  12   f  are fabricated on the top surface of the semiconductor substrate  1 . To the ground pads  11   a ,  11   b ,  11   e , and  11   f  and the signal line pads  12   a ,  12   b ,  12   e , and  12   f , gold metal films are applied. Thereafter, insulating films  13   a  through  13   c  having openings, are formed upon the top surface of the semiconductor substrate  1  in dicing lane (isolation region)  31   a  and  31   b  and a portion of the surface of the ground pads  11   a ,  11   b ,  11   e , and  11   f  and signal line pads  12   a ,  12   b ,  12   e , and  12   f . The dicing lane  31   a  and  31   b  may separate the semiconductor elements with respect to each semiconductor chip. 
     (b) Thereafter, as shown in FIG. 3B, isolation trenches  32   a  and  32   b  having a depth of, for example, 100 μm are formed in the dicing lanes  31   a  and  31   b  from the top surface of the semiconductor substrate  1  using a blade  100  of a dicing apparatus. Using a blade  100  with a V-shaped edge, a normal mesa shape is formed, on a cross-section view, so as to provide tapered sidewalls of the isolation trenches  32   a  and  32   b.    
     (c) As shown in FIG. 3C, a feed metal layer  14  is formed by depositing a gold/titanium film onto the top surface of the semiconductor substrate  1  to a thickness of approximately 100 nm. Since the sidewalls of the isolation trenches  32   a  and  32   b  are tapered, the feed metal layer  14  may be formed to sufficient thickness on the tapered sidewalls of the isolation trenches  32   a  and  32   b . A titanium layer is inserted to improve adhesion strength between the gold metal layer and the insulating films  13   a  through  13   c  or the semiconductor substrate  1 , and has a thickness ranging from several nanometers to several dozen nanometers. 
     (d) Next, as shown in FIG. 3D, a photoresist film  15  is formed, which has openings exposing the region including the ground pads  11   a  and  11   b  and isolation trenches  32   a  and  32   b  arranged on the top surface of the semiconductor substrate  1 . Thereafter, while in the electrolytic plating fluid, electric current is supplied through the feed metal layer  14  to perform selective electrolytic gold plating and form a plated layer  16  with a thickness of 2 μm. However, care should be taken so that the gold plating does not completely fill in the isolation trenches  32   a  and  32   b.    
     (e) After removing the photoresist film  15 , the gold/titanium film of the exposed feed metal layer  14  is removed through a process such as ion milling, and as shown in FIG. 3E, a ground foundation layer  24  is formed under the plated layer  16 . 
     (f) Thereafter, a polishing process for a bottom surface of the semiconductor substrate  1  is performed. As the semiconductor substrate  1  is made thin through the polishing process, at a thickness of approximately 100 μm, the ground foundation layer  24  and the plated layer  16  in bottoms of the isolation trenches  32   a  and  32   b  become exposed. By continuing the polishing process to make the thickness of the semiconductor substrate  1  between 50 and 80 μm, as shown in FIG. 3F, semiconductor chips  21   a  through  21   c  are separated into individual pieces. Sidewalls of the semiconductor chips  21   a  through  21   c  are covered with ground foundation layers  25   a  through  25   c  and ground metal layers  26   a  through  26   c.    
     By performing the bottom surface polishing after filling the inside of the isolation trenches  32   a  and  32   b  with a substance capable to remove in a post process such as a resist or a wax, the ground foundation layer films  25   a  through  25   c  and the ground metal layers  26   a  through  26   c  may be cleanly fabricated. “Cleanly fabricated” means that polishing is performed in a manner such that neither the ground foundation layer films  25   a  through  25   c  nor the ground metal layers  26   a  through  26   c  are peeled away from the semiconductor chips  21   a  through  21   c , and neither the ground foundation layer films  25   a  through  25   c  nor the ground metal layers  26   a  through  26   c  remain on bottom surface portions of the semiconductor chips  21   a  through  21   c.    
     As shown in FIG. 4, the ground metal layer  26   a  connected to the ground pads  11   a  through  11   d  of the fabricated semiconductor chip  21   a  covers the sidewalls of the semiconductor chip  21   a , extending from the periphery of a semiconductor element region  40  having the signal line pads  12   a  through  12   d  in the insulating film  13   a . In addition, the semiconductor chip  21   a  is assembled in the semiconductor module, as shown in FIG. 2, by being mounted onto the ground metal  5  arranged on the mounting substrate  3  using the conductive material  17  such as the silver paste. The conductive material  17  is formed so as to connect the ground metal layer  26   a  of the semiconductor chip  21   a  with the ground metal  5  of the mounting substrate  3 . 
     With the method of manufacturing the semiconductor chip  21   a  according to the embodiment of the present invention, the isolation trenches  32   a  and  32   b  are physically formed in the dicing lanes  31   a  and  31   b  provided between the semiconductor element regions  40  using the blade  100 . Accordingly, the process of forming the isolation trenches  32   a  and  32   b  is simplified. It should be noted that using the blade  100  with the V-shaped edge provides the taper of the normal mesa shapes to the sidewalls of the isolation trenches  32   a  and  32   b . An angle of the V-shaped edge of the blade  100  may be as sharp as is possible. In cases where the V-shaped edge of the blade  100  is blunter, the amount of chip area that is lost increases because the dicing lane width is widened. 
     In addition, as shown in FIG. 5, a glass coat  4  having a projecting shape may be arranged upon the mounting substrate  3   a  so as to enclose the region where the semiconductor chip  21   a  is to be mounted. The semiconductor chip  21   a  may be then placed in a hollow space of the glass coat  4 . The signal line pads  12   a  through  12   d  of the semiconductor chip  21   a  are connected to the signal lines  7   a  through  7   d  upon the mounting substrate  3   a  through bonding wires  18   a  through  18   b . The glass coat  4  makes it possible to keep the conductive material  17  from spreading into the surrounding areas when mounting the semiconductor chip  21   a  onto the mounting substrate  3   a . The glass coat  4  may be formed, for instance, by processing the mounting substrate  3   a , or alternatively may be formed by attaching an insulating material such as silica glass to the mounting substrate  3   a . The conductive material  17  may be filled in the gap between the semiconductor chip  21   a  and the glass coat  4 . The conductive material  17  is filled so as to reach at least the level of the height of projection of the glass coat  4  at the sidewalls of the semiconductor chip  21   a . Accordingly, the glass coat  4  allows a secure contact with the conductive material  17  between the ground metal  5  and the ground metal layer  26   a  fabricated from the gold plated layer on the sidewall of the semiconductor chip  21   a.    
     Alternatively, as shown in FIG. 6, it is possible to keep the conductive material  17  from spreading into the surrounding areas by forming the ground metal  5   a  of the mounting substrate  3   b  on a bottom of a shallow recess, and then mounting the semiconductor chip  21   a . The conductive material  17  may be filled in the gap between the semiconductor chip  21   a  and the sidewalls and the bottom of the recessed. The conductive material  17  is filled so as to reach at least the level of the height of the sidewalls of the recess at the sidewalls of the semiconductor chip  21   a . Accordingly, arranging the ground metal  5   a  on the bottom of the recess in this manner allows a secure contact with the conductive material  17  between the ground metal  5   a  and the ground metal layer  26   a  fabricated with a gold plated layer on the sidewalls of the semiconductor chip  21   a.    
     With the method of manufacturing the semiconductor module according to the embodiment of the present invention, ground inductance may be easily reduced, and it becomes possible to reduce the dimensions of the semiconductor chip  21   a  and make the mounting substrate smaller. 
     The ground metal layer  26   a  may also be formed using a method other than electrolytic plating. For instance, a method may be used where a gold/titanium film having a thickness of 2 μm is formed on the surface of the semiconductor substrate using a vacuum deposition, sputtering, or the like. A resist mask is then formed, and unnecessary portions of the gold/titanium film are removed with etching. With the electrolytic plating method, it is necessary to expose the resist film with light inside the isolation trenches  32   a  and  32   b  having a depth of 100 μm and then to remove the resist film through a developing step. However, with the method of removing the gold/titanium film using etching, there is no need to remove the resist film from inside the deep isolation trenches  32   a  and  32   b , and accordingly, the process is simplified. 
     (Modified Example) 
     The method of manufacturing a semiconductor module according to a modified example of the embodiment of the present invention has a feature where the semiconductor chip  21   a  has sidewalls prescribed as being parallel to the [001] and [010] directions. As the remainder is similar to the embodiment of the present invention, repetitive descriptions are omitted. 
     With a semiconductor chip  21   a  of the semiconductor module according to the modified example of the embodiment of the present invention, in a semiconductor element including an HBT fabricated on a semiconductor substrate  1  with a plane direction ( 100 ) given as a top surface as shown in FIG.  7 , the semiconductor chip  21   a  is defined by sidewalls  51   a  through  51   d  that are parallel to the [001] and [010] directions, and emitter regions  41  of the HBT are defined as rectangular shapes that are parallel to the [011] and [01{overscore (1)}] directions. In a typical semiconductor element manufacturing process for a compound semiconductor such as GaAs, the direction of dicing lane is prescribed as being so that the sidewalls  51   a  through  51   d  of the semiconductor chip  21   a  lie parallel to the [011] and [01{overscore (1)}] directions. In the GaAs or similar compound semiconductors, the [011] and [01{overscore (1)}] directions are the directions of cleavage. Accordingly, dicing is made easier because the dicing lane is substantially lined up with the direction of cleavage. Nevertheless, with the method of manufacturing a semiconductor device according to the embodiment of the present invention, isolation trenches are formed with a blade  100  along the direction of the dicing lane. If the dicing lane is aligned along the [011] and [01{overscore (1)}] directions of the cleavage, it is highly possible that cleavage may occur along the isolation trenches during formation of the isolation trenches. Therefore, as with the modified example of the embodiment of the present invention, cleavage during formation of the isolation trenches may be prevented by aligning the dicing lane along the [001] and [010] directions that are shifted 45° from the directions of cleavage. Physical and chemical characteristics of a compound semiconductor vary with the plane direction. For instance, with chemical etching that uses an HBT emitter fabrication process, an etching rate shows an anisotropic performance, and the width of side etching differs between orthogonal edges of a rectangular etching mask. Accordingly, when the etching is performed so as to leave the emitter regions  41  remaining, the photomask for the emitter fabrication process is designed in consideration of the anisotropy of the side etching in order to prevent variation in the dimensions of the emitters from designed values. In the modified example of the embodiment of the present invention, since the HBT emitter is prescribed as being a rectangular shape parallel to the typical [011] and [01{overscore (1)}] directions, the typical process conditions for fabricating the emitters may be applied without modification. In addition, cleavage may also be prevented, if the dicing lane are shifted approximately 10° from the cleavage directions. Accordingly, the same effects preventing cleavage, may be obtained if the isolation trenches are fabricated so that the sidewalls  51   a  through  51   d  of the semiconductor chip  21   a  are shifted more than 10° from the [011] and [01{overscore (1)}] directions of the cleavage. 
     With the method of manufacturing the semiconductor module according to the modified example of the embodiment of the present invention, the cleavage of the semiconductor substrate during isolation trench fabrication process may be prevented, ground inductance may be easily reduced, and it becomes possible to reduce the dimensions of the semiconductor chip and make the mounting substrate smaller. 
     (Other Embodiments) 
     Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof. 
     In the embodiment of the present invention, an MMIC using an HBT as the semiconductor element was illustrated. However, the same results may naturally also be obtained with an MMIC that uses, for example, a metal-semiconductor field-effect transistor (MESFET) or a high electron mobility transistor (HEMT) or the like. Furthermore, while the blade  100  was described as the blade of the dicing apparatus, a blade of, for example, a semiconductor wafer scriber may naturally also be used.