Abstract:
Disclosed are a metal interconnection of a semiconductor device and a method for manufacturing the same, capable of improving the reliability of the semiconductor device. The metal interconnection of the semiconductor device includes a first metal interconnection formed on a semiconductor substrate; an interlayer dielectric layer formed on the semiconductor substrate including the first metal interconnection, the interlayer dielectric layer being selectively removed to form a via hole and a trench on the via hole; a metal diffusion blocking layer formed in the via hole and the trench formed on the via hole; a second metal interconnection buried in the via hole and the trench below a top portion of the metal diffusion blocking layer; and a protection layer covering the interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.

Description:
RELATED APPLICATION(S) 
       [0001]    This application claims priority under 35 U.S.C. §119(e) of Korean Patent Application No. 10-2005-0134403 filed Dec. 29, 2005, which is incorporated herein by reference in its entirety. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to a metal interconnection of a semiconductor device. 
       BACKGROUND OF THE INVENTION 
       [0003]    Generally, when manufacturing a semiconductor, the most used metal materials are aluminum and aluminum alloys. This is because aluminum and aluminum alloys have superior conductivity and a superior adhesive force with an oxide layer, and they can be easily molded. 
         [0004]    However, aluminum and aluminum alloys have problems such as electric material migration, hillocks, and spikes. 
         [0005]    In detail, if a current is applied to aluminum for a metal interconnection, the diffusion of aluminum atoms may occur in a high-current density area such as an area in contact with silicon or a step area. The diffusion causes a metal line of aluminum existing in the high-current density area to narrow such that a short occurs, which is called “an electric material migration”. Such an electric material migration occurs after a long elapse of time of operation because the aluminum atoms diffuse slowly. 
         [0006]    In order to solve such problems, aluminum-copper alloys made by adding a small amount of copper (Cu) to aluminum (Al) must be employed, a step coverage must be improved, or a wide contact area must be designed. 
         [0007]    Another problem occurs during an alloying process. In other words, when a heat treatment process is performed, silicon migrates to an aluminum thin film, and an excessive reaction occurs in a predetermined local area, causing a device to be destructed, which is called “a spike phenomenon”. 
         [0008]    The spike problem may be solved by employing aluminum-silicon alloys, in which silicon is added by more than a predetermined solubility or by inserting a metal thin film such as TiW or PtSi between aluminum and silicon so as to form a diffusion barrier. 
         [0009]    Accordingly, the development of alternative materials for the metal interconnection has been required. Copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr), and nickel (Ni) having superior conductivity exists as the alternative materials. Copper and copper alloys, which have low resistivity, superior reliability for electro migration (EM) and stress migration (SM), and economical manufacturing costs, have been widely used. 
         [0010]    Accordingly, copper is deposited in a via hole (or a contact hole) and a trench having a single damascene structure or a dual damascene structure so that a plug and a metal interconnection are simultaneously formed, and then undesirable copper remaining on the surface of a wafer is removed through a chemical mechanical polishing (CMP) process. 
         [0011]    Hereinafter, a method for forming a conventional metal interconnection of a semiconductor device will be described with reference to accompanying drawings. 
         [0012]      FIGS. 1A to 1E  are sectional views showing the method for forming the conventional metal interconnection of the semiconductor device. 
         [0013]    Referring to  FIG. 1A , a first copper thin film is formed on the semiconductor substrate  11  and is selectively removed through a photolithography process, thereby forming a first copper interconnection  12 . 
         [0014]    Thereafter, a nitride layer  13  is formed on the entire surface of the semiconductor substrate  11  including the first copper connection  12 , and an interlayer dielectric layer  14  is formed on the nitride layer  13 . 
         [0015]    The nitride layer  13  is used as an etching stop layer, and the interlayer dielectric layer  14  includes a low K material. 
         [0016]    Then, after coating a first photoresist  15  on the interlayer dielectric layer  14 , the first photoresist  15  is patterned through an exposure and development process, thereby defining a contact area. 
         [0017]    Then, the interlayer dielectric layer  14  is selectively removed by using the first photoresist  15  as a mask and the nitride layer  13  as an etching end point, thereby forming a via hole  16 . 
         [0018]    Referring to  FIG. 1B , the first photoresist  15  is removed, a second photoresist  17  is coated on the entire surface of the semiconductor substrate  11  including the via hole  16 , and the second photoresist  17  is patterned through an exposure and development process. 
         [0019]    Subsequently, the interlayer dielectric layer  14  is selectively removed from the surface of the resultant structure by a predetermined thickness using the second photoresist  17  as a mask, thereby forming a trench  18 . 
         [0020]    Referring to  FIG. 1C , the second photoresist  17  is removed, and the nitride layer  13  remaining at the lower part of the via hole  16  is etched off. 
         [0021]    Thereafter, a metal diffusion blocking layer  19  is formed on the entire surface of the semiconductor substrate  11  including the trench  18  and the via hole  16  by using conductive materials such as titanium (Ti) or titanium nitride (TiN). 
         [0022]    Thereafter, a copper (Cu) seed layer is formed on the metal diffusion blocking layer  19 , and then a second copper thin film  20   a  is formed through an electroplating scheme. 
         [0023]    Referring to  FIG. 1D , a CMP process is performed with respect to the entire surface of the second copper thin film  20   a  by employing the upper surface of the interlayer dielectric layer  14  as a polishing stop layer, so that the second copper thin film  20   a  and the metal diffusion blocking layer  19  are selectively polished. Accordingly, a second copper interconnection  20  is formed in the trench  18  and the vial hole  16 . 
         [0024]    Referring to  FIG. 1E , after performing the CMP process, a silicon nitride (SiN) capping layer and a dielectric material are deposited on the interlayer dielectric layer  14 , thereby forming a protection layer  22 . 
         [0025]    However, the method for the conventional metal interconnection of a semiconductor device has the following problems. 
         [0026]    In detail, if the silicon nitride (SiN) capping layer and the dielectric material are deposited right after the CMP process so as to form the protection layer  22 , CMP residues are created between the copper interconnection  20  and the protection layer  22  adjacent to the copper interconnection  20 . Therefore, a micro-bridge may be formed in the reliability test of the semiconductor device. Accordingly, semiconductor defects may be caused. 
         [0027]    In addition, the second copper interconnection diffuses toward the dielectric material due to a problem related to a bonding force of the nitride silicon capping layer, so characteristics such as electro migration (EM) and stress migration (SM) may be degraded. 
       BRIEF SUMMARY 
       [0028]    Accordingly, it is an object of embodiments of the present invention to provide a metal interconnection of a semiconductor device and a method for forming the same, capable of improving the reliability of the semiconductor device by completely removing residues between metal interconnections. 
         [0029]    In order to accomplish the object of the present invention, there is provided a metal interconnection of a semiconductor device including a first metal interconnection formed on a semiconductor substrate, an interlayer dielectric layer formed on the semiconductor substrate including the first metal interconnection, a metal diffusion blocking layer formed in a via hole and a trench formed on to the via hole by selectively removing the interlayer dielectric layer, a second metal interconnection buried in the via hole and the trench lower than a top portion of the metal diffusion blocking layer, and a protection layer covering the interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection. 
         [0030]    In addition, according to another embodiment of the present invention, there is provided a method for forming a metal interconnection of a semiconductor device, including the steps of: forming a first metal interconnection on a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate including the first metal interconnection, forming a via hole and a trench on the via hole by selectively removing the interlayer dielectric layer, forming a metal diffusion blocking layer on the interlayer dielectric layer formed with the trench and the via hole, forming a second metal film on the metal diffusion blocking layer, forming a second metal interconnection lower than the interlayer dielectric layer in the trench and the via hole by selectively etching the second metal film and the metal diffusion blocking layer through a chemical mechanical polishing (CMP) process, etching the interlayer dielectric layer through an etching process corresponding to a height of the second metal interconnection, and forming a protection layer covering the etched interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIGS. 1A to 1E  are sectional views showing a method for forming a conventional metal interconnection of a semiconductor device. 
           [0032]      FIG. 2  is a sectional view showing a metal interconnection of a semiconductor device according to an embodiment of the present invention. 
           [0033]      FIGS. 3A to 3G  are sectional views showing a method for forming a metal interconnection of a semiconductor device according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0034]    Hereinafter, a metal interconnection of a semiconductor device and a method for forming the same according to a preferred embodiment of the present invention will be described in detail with reference to accompanying drawings. 
         [0035]      FIG. 2  is a sectional view showing a metal interconnection of a semiconductor device according to an embodiment of the present invention. 
         [0036]    As shown in  FIG. 2 , a first copper interconnection  32  is formed on a semiconductor substrate  31 ; a nitride layer  33  is formed on the entire surface of the semiconductor substrate  31  including the first copper interconnection  32 ; an interlayer dielectric layer  34  is formed on the nitride layer  33 ; a metal diffusion blocking layer  39  is formed in a via hole and a trench formed on the via hole, which are formed by selectively removing the interlayer dielectric layer  34 , a second copper interconnection  40  is buried in the via hole and the trench through a chemical mechanical polishing (CMP) process to be lower than the metal diffusion blocking layer  39  by a height of about 30 nm to about 50 nm; and a protection layer is formed on the interlayer dielectric layer  34  etched through an etching process by a depth of about 30 nm to about 50 nm, the metal diffusion blocking layer  39 , and the second copper interconnection  40 . 
         [0037]    The second copper interconnection  40  can be formed through an electroplating scheme after forming a copper (Cu) seed layer on the metal diffusion blocking layer  39 . 
         [0038]    In addition, the second copper interconnection  40  and the metal diffusion blocking layer  39  can be selectively polished through a CMP process, thereby forming the second copper interconnection  40  lower than the metal diffusion blocking layer  39  by a height of about 30 nm to about 50 nm. 
         [0039]    When the CMP process is performed, a removal rate for copper can be made relatively higher as compared with a removal rate for the interlayer dielectric layer  34  or the metal diffusion blocking layer  39 , so that the second copper interconnection  40  formed in the via hole and the trench can be lower than the metal diffusion blocking layer  39  by, for example, a height of about 30 nm to about 50 nm. 
         [0040]    The protection layer  42  can be formed on the interlayer dielectric layer  34  etched through an etching process by a depth of about 30 nm to about 50 nm, the metal diffusion blocking layer  39 , and the second copper interconnection  40 , after performing the CMP process. 
         [0041]    In addition, the protection layer  42  can be formed by depositing a silicon nitride (SiN) capping layer and a dielectric material on the interlayer dielectric layer  34 , which is etched through an etching process, the metal diffusion blocking layer  39 , and the second copper interconnection  40 . 
         [0042]      FIGS. 3A to 3G  are sectional views showing a method for forming a metal interconnection of a semiconductor device according to an embodiment of the present inventions. 
         [0043]    Referring to  FIG. 3A , a first copper thin film can be formed on a semiconductor substrate  31  (or dielectric layer), and can be selectively removed through a photolithography and etching process, thereby forming a first copper interconnection  32 . 
         [0044]    Thereafter, a nitride layer  33  can be formed on the entire surface of the semiconductor substrate  31  including the first copper connection  32 , and an interlayer dielectric layer  34  can be formed on the nitride layer  33 . 
         [0045]    The nitride layer  33  can be used as an etching stop layer, and the interlayer dielectric layer  34  can include a low K material or an ultra low k material (k&lt;2.5). 
         [0046]    Then, after coating a first photoresist  35  on the interlayer dielectric layer  34 , the first photoresist  35  can be patterned by an exposure and development process, thereby defining a contact area. 
         [0047]    Then, the interlayer dielectric layer  34  can be selectively removed using the first photoresist  35  as a mask and the nitride layer  33  as an etching end point, thereby forming a via hole  36 . 
         [0048]    Referring to  FIG. 3B , the first photoresist  35  can be removed, a second photoresist  37  can be coated on the entire surface of the semiconductor substrate  31  including the via hole  36 , and the second photoresist  37  can be patterned by an exposure and development process. 
         [0049]    Subsequently, the interlayer dielectric layer  14  can be selectively removed from the surface of the resultant structure by a predetermined thickness using the second photoresist  37  as a mask, thereby forming a trench  38 . 
         [0050]    Thereafter, the second photoresist  37  can be removed, and the nitride layer  33  remaining at the lower part of the via hole  36  can be etched off. 
         [0051]    In an embodiment, the nitride layer  33  can be etched off using the second photoresist  37  as a mask, or by using the interlayer dielectric layer  34  as a mask. 
         [0052]    Referring to  FIG. 3C , a metal diffusion blocking layer  39  can be formed on the entire surface of the semiconductor substrate  31  including the trench  38  and the via hole  36 . The metal diffusion blocking layer  39  can be formed of conductive materials such as titanium (Ti) or titanium nitride (TiN). 
         [0053]    Referring to  FIG. 3D , a copper (Cu) seed layer can be formed on the metal diffusion blocking layer  39 , and then a second copper thin film  40   a  can be formed through an electroplating scheme. 
         [0054]    Referring to  FIG. 3E , a CMP process is performed with respect to the entire surface of the second copper thin film  40   a  while employing the upper surface of the interlayer dielectric layer  34  as a polishing stop layer. The second copper thin film  40   a  and the metal diffusion blocking layer  39  can be polished/etched selectively by the CMP process, thereby forming a second copper interconnection  40  in the trench  38  and the via hole  36 , which is lower than the metal diffusion blocking layer  38  by a height of, for example, about 30 nm to about 50 nm. 
         [0055]    When the CMP process is performed, the removal rate for copper can be made relatively higher as compared with the removal rate for the interlayer dielectric layer  34  or the metal diffusion blocking layer  39 , so that the second copper interconnection  40  formed in the via hole and the trench can be lower than the metal diffusion blocking layer  39 . 
         [0056]    As shown in  FIG. 3F , after performing the CMP process, an etching process can be performed to etch the interlayer dielectric layer  34 . The interlayer dielectric layer  34  can be etched to a depth of about 30 nm to about 50 nm. 
         [0057]    In one embodiment, the interlayer dielectric layer  34  can be etched by the etching process after the CMP process such that the height of the interlayer dielectric layer  34  corresponds to the height of the copper interconnection  40 . In a specific embodiment, both the interlayer dielectric layer  34  and the copper interconnection  40  can be about 30 nm to about 50 nm from a top portion of the metal diffusion blocking layer  39 . 
         [0058]    Referring to  FIG. 3G , a silicon nitride (SiN) capping layer and a dielectric material can be deposited on the interlayer dielectric layer  34 , which is etched through an etching process, the metal diffusion blocking layer  39 , and the second copper interconnection  40 , thereby forming a protection layer  42 . 
         [0059]    The protection layer  42  can be formed by depositing the silicon nitride (SiN) capping layer and the dielectric material on the interlayer dielectric layer  34 , which is etched through the etching process, the metal diffusion blocking layer  39 , and the second copper interconnection  40   
         [0060]    As described above, the metal interconnection of the semiconductor device and the method for forming the same according to embodiments of the present invention have the following advantages. 
         [0061]    The second copper interconnection, which is formed in the via hole and the trench, can be formed lower than the metal diffusion blocking layer by a height of about 30 nm to about 50 nm through the CMP process, and the interlayer dielectric layer can be etched corresponding to the height of the second copper interconnection. Then, the silicon nitride (SiN) capping layer and the dielectric material can be deposited on the interlayer dielectric layer so as to form the protection layer, such that CMP residues between the second copper interconnections can be completely removed. Accordingly, it is possible to prevent a micro-bridge phenomenon in the reliability test of the semiconductor device. 
         [0062]    In addition, since the metal diffusion blocking layer extends into the protection layer including silicon nitride (SiN), a capping function for the diffusion of copper can be enhanced, so that it is possible to improve the characteristics of the semiconductor device such as electro migration (EM) and stress migration (SM). 
         [0063]    While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.