Abstract:
A structure and methods of making the structure. The structure includes: first and a second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; a first gate electrode extending over the first semiconductor region and the region of the trench isolation; a second gate electrode extending over the second silicon region and the region of the trench isolation; a trench in the trench isolation; and a strap in the trench connecting the first and second gate electrodes.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of semiconductor devices; more specifically, it relates to MOSFET gate-to-gate interconnections and methods of fabricating MOSFET gate-to-gate interconnections. 
       BACKGROUND 
       [0002]    As the dimensions of integrated circuits decrease, lithographic constraints are tending toward the gates of field effect transistors (FETs) to be orientated in a single direction on a fixed pitch. This adds to an increase in the density of the wiring at the next level used to interconnect gates of two or more FETs which are also constrained by lithography. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove. 
       SUMMARY 
       [0003]    A first aspect of the present invention is a structure, comprising: first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; a first gate electrode extending over the first semiconductor region and the region of the trench isolation; a second gate electrode extending over the second silicon region and the region of the trench isolation; a trench in the trench isolation; and a strap in the trench connecting the first and second gate electrodes. 
         [0004]    A second aspect of the present invention is a method, comprising: forming first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; forming a trench in the trench isolation; and forming a first gate electrode extending over the first semiconductor region and the region of the trench isolation, an integral second gate electrode extending over the second silicon region and the region of the trench isolation, and an integral strap in the trench, the strap connecting the first and second gate electrodes. 
         [0005]    A third aspect of the present invention is a method comprising: forming first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; forming a first trench in the trench isolation; forming a dummy structure comprising a first dummy gate electrode extending over the first semiconductor region and the region of the trench isolation, an integral second dummy gate electrode extending over the second silicon region and the region of the trench isolation, and an integral dummy strap in the first trench, the dummy strap connecting the first and second dummy gate electrodes; and removing the dummy structure and replacing the dummy structure with a first gate electrode, an integral second gate electrode and an integral dummy strap. 
         [0006]    These and other aspects of the invention are described below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0008]      FIGS. 1 through 8  illustrate a first method of fabricating a gate-to-gate strap according to an embodiment of the present invention; 
           [0009]      FIG. 9  illustrates an alternative processing sequence for the first method; 
           [0010]      FIGS. 10 through 13  illustrate a second method of fabricating a gate-to-gate strap according to an embodiment of the present invention; and 
           [0011]      FIG. 14  illustrates an alternative processing sequence for the second method. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]      FIGS. 1 through 8  illustrate a first method of fabricating a gate-to-gate strap according to an embodiment of the present invention.  FIG. 1  is a plan view and  FIGS. 1A and 1B  are cross-sectional views through lines  1 A- 1 A and  1 B- 1 B respectively of  FIG. 1 . A cross-section through line  1 C- 1 C would be similar to  FIG. 1B . Formed in a semiconductor substrate  100  (or a semiconductor layer of semiconductor-on-insulator (SOI) substrate) is trench isolation  105  surrounding the perimeters of substrate regions  110 A and  110 B. In one example, semiconductor substrate is a single-crystal silicon substrate (or semiconductor layer is a single-crystal silicon layer of an SOI substrate). Trench isolation may be formed by etching a trench into the substrate, depositing a dielectric material (e.g., silicon dioxide (SiO 2 )) to overfill the trench and cover the surface of substrate, followed by a chemical-mechanical-polish (CMP) to coplanarize the top surfaces of the substrate and the dielectric material in the trench. 
         [0013]      FIG. 2  is a plan view and  FIGS. 2A and 2B  are cross-sectional views through lines  2 A- 2 A and  2 B- 2 B respectively of  FIG. 2 . A cross-section through line  2 C- 2 C would be similar to  FIG. 2B . In  FIGS. 2 ,  2 A and  2 B a gate dielectric layer has been formed on trench isolation  115  and substrate regions  110 A and  110 B. In one example, gate dielectric layer  115  comprises SiO 2 , silicon nitride (Si 3 N 4 ) or combinations of layers thereof. In one example gate dielectric layer  105  is a high-K (dielectric constant) material, examples of which include but are not limited to metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. A high-K dielectric material has a relative permittivity above about 10. In one example, gate dielectric layer  115  is about 0.5 nm to about 20 nm thick. 
         [0014]      FIG. 3  is a plan view and  FIGS. 3A and 3B  are cross-sectional views through lines  3 A- 3 A and  3 B- 3 B respectively of  FIG. 3 . A cross-section through line  3 C- 3 C would be similar to  FIG. 3B . In  FIGS. 3 and 3A , a trench  120  has been etched in trench isolation  105  through gate dielectric layer  115 . Trench  120  is formed by a photolithographic process that forms a patterned photoresist layer on gate dielectric layer  115 , followed by a reactive ion etch (RIE), followed by removal of the patterned photoresist layer. Trench  120  is contained within trench isolation  105  and does not extend through the trench isolation to contact underlying substrate  100 . 
         [0015]      FIG. 4  is a plan view and  FIGS. 4A and 4B  are cross-sectional views through lines  4 A- 4 A and  4 B- 4 B respectively of  FIG. 4 . A cross-section through line  4 C- 4 C would be similar to  FIG. 4B . In  FIGS. 4 ,  4 A and  4 B a polysilicon layer  125  has been deposited on substrate  100  and in trench  120 . In a preferred embodiment, a top surface  127  of polysilicon layer  125  in trench  120  is recessed below a top surface of  128  of trench isolation  105 . Alternatively, top surfaces  127  and  128  may be coplanar or top surface  127  may extend above top surface  128 . In one example, polysilicon layer  125  is formed by chemical vapor deposition (CVD). 
         [0016]      FIG. 5  is a plan view and  FIGS. 5A and 5B  are cross-sectional views through lines  5 A- 5 A and  5 B- 5 B respectively of  FIG. 5 . A cross-section through line  5 C- 5 C would be similar to  FIG. 5B . In  FIGS. 5 ,  5 A and  5 B, gate electrodes  130 A and  130 B connected by a strap  130 C have been formed. Gate electrodes  130 A and  130 B and strap  130 C are integrally formed by a photolithographic process that forms a patterned photoresist layer on polysilicon layer  125  (see  FIGS. 4 ,  4 A and  4 B), followed by a reactive ion etch (RIE), followed by removal of the patterned photoresist layer. Strap  130 C is recessed into trench  120 . 
         [0017]    In  FIG. 5 , first major axes A 1  of gate electrode  130 A and A 2  of second gate electrode  130 B are parallel. Second major axes A 3  of first semiconductor region  110 A and A 4  of second semiconductor region  110 B and A 5  of strap  130 C are parallel. Major axes A 1  and A 2  are perpendicular to major axes A 3 , A 4  and A 5 . 
         [0018]      FIG. 6  is a plan view and  FIGS. 6A and 6B  are cross-sectional views through lines  6 A- 6 A and  6 B- 6 B respectively of  FIG. 6 . A cross-section through line  6 C- 61 C would be similar to  FIG. 6B . In  FIGS. 6 and 6B  source/drain extensions  135  have been formed in substrate regions  110 A and  110 B. Source/drain extensions may be formed by an angled (at an acute angle relative to the top surface of substrate  100 ) ion implantation while substrate  100  is rotating about an axis perpendicular to the top surface of the substrate. 
         [0019]      FIG. 7  is a plan view and  FIGS. 7A and 7B  are cross-sectional views through lines  7 A- 7 A and  7 B- 7 B respectively of  FIG. 7 . A cross-section through line  7 C- 7 C would be similar to  FIG. 7B . In  FIGS. 7 ,  7 A and  7 B dielectric sidewall spacers  140  have been formed on the sidewalls of gate electrodes  130 A and  130 B. In one example sidewall spacers comprise Si 3 N 4 . Sidewall spacers  140  may be formed by a blanket deposition of a conformal dielectric layer followed by an RIE to remove the dielectric material from horizontal surfaces (surfaces parallel to the top surface of substrate  100 ). After sidewall spacer formation, source/drains  145  are formed in substrate regions  110 A and  110 B, for example, by ion implantation where substrate regions  110 A and  110 B are not protected by gate electrodes  130 A,  130 B or sidewall spacers  140 . Source/drains  145  include integral source/drain extensions  135 . Channel regions  150  of substrate region  110 A (and  110 B) are defined between source/drain extensions  135  under gate electrodes  130 A and  130 B. In one example, gate dielectric layer  115  is also removed by the spacer RIE process where the gate dielectric layer is not protected by gate electrodes  130 A and  130 B or sidewall spacers  140  (as they are formed). 
         [0020]    Although, both first and second gate electrodes  130 A and  130 B are illustrated as extending over both first and second semiconductor regions  110 A and  110 B and trench isolation, alternatively, first gate electrode  130 A may extend only over first semiconductor region  110 A and trench isolation  105  and first gate electrode  130 A may extend only over first semiconductor region  110 A and trench isolation  105  as long as the first and second gate electrodes are joined by strap  130 C in trench  120 . 
         [0021]      FIG. 8  is a plan view and  FIGS. 8A and 8B  are cross-sectional views through lines  8 A- 8 A and  8 B- 8 B respectively of  FIG. 8 . A cross-section through line  8 C- 8 C would be similar to  FIG. 8B . In  FIGS. 8A and 8B  metal silicide layers  155  (when semiconductor regions  110 A and  110 B include or are silicon) are formed on exposed surfaces of source/drains  145  and gate electrodes  130 A and  130 B. Metal silicide layers  155  may be formed by depositing a thin metal layer, followed by high temperature heating in an inert or reducing atmosphere at a temperature that will cause the metal to react with silicon followed by an etch to remove un-reacted metal. 
         [0022]      FIG. 9  illustrates two alternative processing sequences for the first method.  FIG. 9  is a plan view and  FIGS. 9A and 9B  are cross-sectional views through lines  9 A- 9 A and  9 B- 9 B respectively of  FIG. 9 . A cross-section through line  9 C- 9 C would be similar to  FIG. 9B . In the first alternative dielectric layer  115  has been formed after forming trench  120  so the bottom and sidewalls of trench  120  are lined with gate dielectric layer  115 . In the second alternative, the spacers  140  over strap  130 C were removed prior to metal silicide formation resulting in a metal silicide strap  155 A connecting gate electrodes  130 A and  130 B in the vicinity of strap  130 C providing enhanced electrical conduction. Either the first alternative may be used alone, the second alternative used alone, both the first and second alternatives used together, or neither the first and second alternatives used. 
         [0023]      FIGS. 10 through 13  illustrate a second method of fabricating a gate-to-gate strap according to an embodiment of the present invention.  FIG. 10  is a plan view and  FIGS. 10A and 10B  are cross-sectional views through lines  10 A- 10 A and  10 B- 10 B respectively of  FIG. 10 . A cross-section through line  10 C- 10 C would be similar to  FIG. 10B .  FIGS. 10 ,  10 A and  10 B are performed after the steps illustrated in  FIGS. 1 through 7  have been performed. In  FIGS. 10 ,  10 A and  10 B an interlevel dielectric layer (ILD)  160  has been deposited over substrate  100 . 
         [0024]      FIG. 11  is a plan view and  FIGS. 11A and 11B  are cross-sectional views through lines  11 A- 11 A and  11 B- 11 B respectively of  FIG. 11 . A cross-section through line  11 C- 11 C would be similar to  FIG. 11B . In  FIGS. 11 ,  11 A and  11 B, a CMP has been performed to expose the top surfaces of gate electrodes  130 A and  130 B (see  FIGS. 10A and 10B ). Next gate electrodes  130 A and  130 C and gate dielectric layer  115  (see  FIGS. 10A and 10B ) are removed and a replacement gate dielectric layer  165  has been formed in place of gate dielectric layer  115  where the gate dielectric layer  115  was not protected by sidewall spacers  140 . When a gate electrode (i.e.,  130 A or  130 B) is used in this manner, it often called a dummy gate electrode. When a gate dielectric layer (i.e.,  115 ) is used in this manner, it is often called a dummy gate dielectric layer. When the dummy gates are polysilicon, they may be removed by using wet or dry etching processes, for instance, a wet etch process using tetramethyl ammonium hydroxide (TMAH) or ammonium hydroxide (NH 4 OH), or a fluorine based RIE process. In the example that dummy gate dielectric is SiO 2 , the dummy gate electrode may be removed by a fluorine based RIE or a dilute HF etch. In one example, gate dielectric layer  165  comprises SiO 2 , silicon nitride (Si 3 N 4 ) or combinations of layers thereof. In one example gate dielectric layer  165  is a high-K (dielectric constant) material, examples of which include but are not limited to metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. In one example, gate dielectric layer  165  is about 0.5 nm to about 20 nm thick. 
         [0025]      FIG. 12  is a plan view and  FIGS. 12A and 12B  are cross-sectional views through lines  12 A- 12 A and  12 B- 12 B respectively of  FIG. 12 . A cross-section through line  12 C- 12 C would be similar to  FIG. 12B . In  FIGS. 12 and 12A  ILD  160 , sidewall spacers  140  over gate strap  130 C and gate strap  130 C (see  FIG. 11A ) are removed by, for example, combinations of wet and RIE etches. In this example, strap  130 C (see  FIG. 11A ) may be considered a dummy strap. 
         [0026]      FIG. 13  is a plan view and  FIGS. 13A and 13B  are cross-sectional views through lines  13 A- 13 A and  13 B- 13 B respectively of  FIG. 13 . A cross-section through line  13 C- 13 C would be similar to  FIG. 13B . In  FIGS. 13 and 13A  first and second replacement gates  170 A and  170 B and replacement strap  170 C are formed. Replacement gates  170 A and  170 B and replacement strap  170 C are integrally formed. In one example, replacement gates  170 A and  170 B and replacement strap  170 C comprise aluminum. Replacement gates  170 A and  170 B and replacement strap  170 C may be formed, for example, by atomic layer deposition (ALD), CVD, plasma vapor deposition (PVD), electroplating (EP), and electroless plating (EL). A thin aluminum seed layer may be first formed by evaporative deposition prior to ALD, CVD, PVD, EP and EL. In a preferred embodiment, a top surface  172  of strap  170 C in trench  120  is recessed below a top surface of  128  of trench isolation  105 . Alternatively, top surfaces  172  and  128  may be coplanar or top surface  172  may extend above top surface  128 . 
         [0027]    Although, both first and second gate electrodes  170 A and  170 B are illustrated as extending over both first and second semiconductor regions  110 A and  110 B and trench isolation, alternatively, first gate electrode  170 A may extend only over first semiconductor region  110 A and trench isolation  105  and first gate electrode  170 A may extend only over first semiconductor region  110 A and trench isolation  105  as long as the first and second gate electrodes are joined by strap  170 C in trench  120 . 
         [0028]      FIG. 14  illustrates an alternative processing sequence for the second method.  FIG. 14  is a plan view and  FIGS. 14A and 14B  are cross-sectional views through lines  14 A- 14 A and  14 B- 14 B respectively of  FIG. 14 . A cross-section through line  14 C- 14 C would be similar to  FIG. 14B . In the alternative processing sequence, dielectric layer  165  has been formed after removing ILD  160  and sidewall spacers  140  over gate strap  130 C (see  FIG. 11A ) and forming replacement gate electrodes  170 A and  170 B and strap  170 C. 
         [0029]    Thus the embodiments of the present invention provide a recessed strap for interconnecting two or more gates of adjacent MOSFETs, reducing the need for interconnecting the gates at a higher interconnect level. 
         [0030]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.