Abstract:
The present invention discloses a 1-bit cell circuit used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to pipelined ADCs, and more particularly to a  1 -bit cell circuit used in pipelined ADCs. 
         [0003]    2. Description of the Related Art 
         [0004]    In mixed modes circuits, ADC (Analog-Digital-Converter) is an inevitable part. Recently, pipelined ADC is widely adopted due to its concise structure and superior performance. Please refer to  FIG. 1 , which shows the typical architecture of a prior art 1-bit cell of a pipelined ADC. The 1-bit cell has a sampling phase and a charge transfer phase during a clock cycle. As shown in  FIG. 1 , the 1-bit cell includes an OTA (Operational Transconductance Amplifier)  101 , four matched capacitors  102 ˜ 105 , a first set of switches  106 ˜ 113 , a second set of switches  114 ˜ 121 , two multiplexers  122  and  123 , and two latched comparators  124  and  125 . 
         [0005]    The OTA  101  is used to generate a residue output Vout according to an input signal Vin, wherein the residue output Vout is composed of a positive output Voutp and a negative output Voutn, and the input signal Vin is composed of a positive input signal Vinp and a negative input signal Vinn. The matched capacitors  102 ˜ 105  are used to hold a sampled voltage of the input signal Vin. The first set of switches  106 ˜ 113  are closed for sampling the input signal Vin during the sampling phase. The second of switches  114 ˜ 121  are closed during the charge transfer phase to make the matched capacitors  102 ˜ 105  and the OTA  101  form a negative feedback circuit to generate the residue output Vout. The two multiplexers  122  and  123  are used to respectively provide a first multiplexer output voltage and a second multiplexer output voltage which are selected from a group consisting of a negative reference voltage Vrefn, a positive reference voltage Vrefp and a ground voltage according to two select signals bp and bn, wherein bp is a positive bit signal and bn is a negative bit signal. When bp=0 and bn=0, the first multiplexer output voltage and the second multiplexer output voltage are both connected to the ground voltage; when bp=0 and bn=1, the first multiplexer output voltage is connected to the negative reference voltage Vrefn and the second multiplexer output voltage is connected to the positive reference voltage Vrefp; and when bp=1 and bn=0, the first multiplexer output voltage is connected to the positive reference voltage Vrefp and the second multiplexer output voltage is connected to the negative reference voltage Vrefn. The comparator  124  is used to generate the positive bit signal bp according to voltage comparison of the input signal Vin and a first reference voltage Vref/ 4 , and the comparator  125  is used to generate the negative bit signal bn according to voltage comparison of the input signal Vin and a second reference voltage −Vref/4, wherein the Vref is equal to the voltage difference between the Vrefp and the Vrefn. When Vin is between −Vref/4 and Vref/4, (bp, bn) is (0,0); when Vin is smaller than −Vref/4, (bp, bn) is (0,1); and when Vin is greater than Vref/4, (bp, bn) is (1,0). 
         [0006]    During the sampling phase, the input signal Vin is sampled and hold, and the positive bit signal bp and the negative bit signal bn are generated. Please refer to  FIG. 2   a , which shows an illustrating diagram of the sampling phase of the prior art 1-bit cell. As shown in  FIG. 2   a , the top plates of the capacitor  102  and the capacitor  103  are connected to the positive terminal of the Vin, and the top plates of the capacitor  104  and the capacitor  105  are connected to the negative terminal of the Vin, and all the bottom plates of the capacitors  102 ,  103 ,  104  and  105  are connected to the ground. The comparator  124  and  125  respectively generates the positive bit signal bp and the negative bit signal bn for the charge transfer phase. 
         [0007]    During the charge transfer phase, the residue output is generated. Please refer to  FIG. 2   b , which shows an illustrating diagram of the charge transfer phase of the prior art 1-bit cell. As shown in  FIG. 2   b , due to the virtual ground of the OTA  101  in negative feedback, there will be charge drawn from the Vref, flowing through the capacitors  102 ˜ 105  to generate the residue output Vout=2×Vin−(bp−bn)×Vref. 
         [0008]    However, as the Vin is a varying signal, the charge delivered by the Vref will be different. That is, the loading of the Vref will be varying and dependent on the input signal Vin. The total amount of charge Q taken from the Vref by each 1-bit cell can be easily computed as being the capacitance of the capacitor  102 , the capacitor  104  times the voltage difference between the final voltage appearing on the capacitor  102 , the capacitor  104  at the end of the charge transfer phase, and the voltage appearing on the capacitor  102 , the capacitor  104  at the beginning of the charge transfer phase. For a first order analysis, assuming complete settling at each clock phase, and neglecting any mismatch between the positive and negative channels of the differential architecture, e.g. consider the capacitance of the capacitor  102 =Csp, the capacitance of the capacitor  104 =Csn, and Csp=Csn=Cs. The total amount of charge Q is derived according to bit decision as follows: 
         [0000]      for  b=+ 1( bp= 1&amp; bn= 0),  Q=Csp *( V ref p−V in p )=− Csn *( V ref n−V in n )= Cs* ( V ref− V in)/2;
 
         [0000]      for  b=− 1( bp= 0&amp; bn= 1),  Q=Csn *( V ref p−V in n )= Csp ( V ref n−V in p )= Cs* ( V ref+ V in)/2; and 
         [0000]      for  b= 0( bp= 0&amp; bn+ 0),  Q= 0. 
         [0009]    The minimal input voltage Vin yielding a positive bit decision (b=+1) is Vref/4, and the maximal amount of charge thereof arises to: Q,max=Cs*(Vref−Vref/4)/2=3*Cs*Vref/8=0.375*Vref. The negative (b=−1) bit decision yields the same maximal value for Q (the input signal Vin gets the opposite value, and the connection of the capacitor  102 , the capacitor  104  to the reference voltage Vref are cross-swapped). Since there is no load at all applied on the reference voltage Vref for a null bit decision (b=0), the total variation (with the input signal Vin) of the charge taken from the reference voltage Vref is thus: Q,var=Q,MAX−0=0.375*Cs*Vref. 
         [0010]    Since the loading of the reference voltage Vref depends on the input signal Vin, complete settling of voltage on the sampling capacitor is then needed to prevent sampling noise. However, this implies a longer sampling time. If high speed is required, then more power has to be burned on the reference voltage buffer to shorten the settling time. 
         [0011]    Therefore, there is a need to provide a solution capable of reducing the power consumption and eliminating the need of full settling of the voltage on the sampling capacitor charged by a voltage reference. 
         [0012]    To overcome the drawback, the present invention proposes a novel topology of signal independent voltage reference loading for the pipelined ADC. 
       SUMMARY OF THE INVENTION 
       [0013]    One objective of the present invention is to provide a signal independent voltage reference loading circuit to construct a concise and power saving pipelined ADC. 
         [0014]    Another objective of the present invention is to provide a signal independent voltage reference loading circuit to release the speed requirement of the voltage reference buffer. 
         [0015]    Still another objective of the present invention is to provide a signal independent voltage reference loading circuit to construct a  4 x interleaved pipelined ADC. 
         [0016]    To achieve the foregoing objectives, the present invention provides a 1-bit cell circuit used in a pipelined analog to digital converter, having a sampling phase including a first half period and a second half period and a charge transfer phase in a cycle. The 1-bit cell circuit comprises a differential amplifier, having a positive input end, a negative input end, a positive output end and a negative output end, for outputting a residue output signal; a first capacitor, having a first plate and a second plate, and a second capacitor, having a third plate and a fourth plate, wherein said first plate is connected to a positive input signal, said third plate is connected to a negative input signal, and said second plate and said fourth plate are both connected to an input common mode reference ground during said sampling phase, and said first plate is connected to said third plate, said second plate is connected to said negative input end of said differential amplifier, and said fourth plate is connected to said positive input end of said differential amplifier during said charge transfer phase; and a third capacitor, having a fifth plate and a sixth plate, and a fourth capacitor, having a seventh plate and an eighth plate, wherein said fifth plate and said seventh plate are connected to an output common mode reference ground, and said sixth plate and said eighth plate are both connected to said input common mode reference ground during said first half period of said sampling phase; said fifth plate is connected to a first reference contact, said seventh plate is connected to a second reference contact, and said sixth plate and said eighth plate are both connected to said input common mode reference ground during said second half period of said sampling phase; and said fifth plate is connected to said positive output end of said differential amplifier, said sixth plate is connected to said negative input end of said differential amplifier, said seventh plate is connected to said negative output end of said differential amplifier and said eighth plate is connected to said positive input end of said differential amplifier during said charge transfer phase; wherein voltages of said first reference contact and said second reference contact are determined according to an input voltage and a reference voltage, and said input voltage is a voltage difference between said positive input signal and said negative input signal. 
         [0017]    In addition, according to another embodiment of the present invention, a 1-bit cell circuit is used in a pipelined analog to digital converter, having a sampling phase including a first half period and a second half period and a charge transfer phase in a cycle. The 1-bit cell circuit comprises a differential amplifier, having a pair of differential input ends and a pair of differential output ends, for outputting a differential residue output signal; a first pair of capacitors, having a pair of first top plates and a pair of first bottom plates, wherein said pair of first top plates are connected to a differential input signal, and said first bottom plates are connected to an input common mode reference ground during said sampling phase, and said first top plates are connected to each other and said first bottom plates are connected to said differential input ends of said differential amplifier during said charge transfer phase; and a second pair of capacitors, having a pair of second top plates and a pair of second bottom plates, wherein said second top plates are connected to an output common mode reference ground and said second bottom plates are connected to an input common mode reference ground during said first half period of said sampling phase; said second top plates are connected to a pair of reference contacts and said second bottom plates are connected to said input common mode reference ground during said second half period of said sampling phase; and said second top plates are connected to said differential output ends of said differential amplifier and said second bottom plates are connected to said differential input ends of said differential amplifier during said charge transfer phase; wherein voltages of said reference contacts are determined according to an input voltage of said differential input signals and a reference voltage. 
         [0018]    In addition, according to another embodiment of the present invention, a 1-bit cell circuit is used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal. 
         [0019]    To make it easier for our examiner to understand the objective of the invention, its structure, innovative features, and performance, we use a preferred embodiment together with the accompanying drawings for the detailed description of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIG. 1  is the typical architecture of a prior art 1-bit cell of a pipelined ADC. 
           [0021]      FIG. 2   a  is an illustrating diagram of sampling phase of the prior art 1-bit cell. 
           [0022]      FIG. 2   b  is an illustrating diagram of charge transfer phase of the prior art 1-bit cell. 
           [0023]      FIG. 3  is the circuit diagram of a 1-bit cell using a signal independent voltage reference loading circuit according to a preferred embodiment of the present invention. 
           [0024]      FIG. 4   a  is an illustrating diagram of a first half period of sampling phase of the 1-bit cell in  FIG. 3 . 
           [0025]      FIG. 4   b  is an illustrating diagram of a second half period of sampling phase of the 1-bit cell in  FIG. 3 . 
           [0026]      FIG. 4   c  is an illustrating diagram of a charge transfer phase of the 1-bit cell in  FIG. 3 . 
           [0027]      FIG. 5  is a circuit diagram of a cascade of two 1-bit cells according to a preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0028]    The present invention will be described in more detail hereinafter with reference to the accompanying drawings that show the preferred embodiment of the invention. 
         [0029]    Please refer to  FIG. 3   a˜b , which shows the circuit diagram of a 1-bit cell using a signal independent voltage reference loading circuit according to a preferred embodiment of the present invention. The 1-bit cell ADC procedure includes a first half period of sampling phase, a second half period of sampling phase and a charge transfer phase during a converting period. As shown in  FIG. 3   a , the 1-bit cell ADC serve as a sample and charge transfer circuit comprises an OTA (Operational Transconductance Amplifier )  301 , six matched capacitors  302 ˜ 307 , eight sampling phase switches  308 ˜ 315 , seven charge transfer phase switches  316 ˜ 322 , two multiplexers  323  and  324 , two comparators  337  and  338  and a voltage reference buffer  339 . As shown in  FIG. 3   b , a dump circuit comprises two multiplexers  330  and  336 , two matched capacitors  325  and  331 , four sampling phase switches  326 ˜ 327  and  332 ˜ 333 , and four charge transfer phase switches  328 ˜ 329  and  334 ˜ 335 . 
         [0030]    In the 1-bit cell circuit, the OTA  301 , having a positive input end, a negative input end, a positive output end and a negative output end, is used to generate a residue output V out  according to an input signal V in , wherein the residue output V out  is composed of a positive output V outp  and a negative output V outn , and the input signal V in  is composed of a positive input signal V inp  and a negative input signal V inn . The eight matched capacitors  302 ˜ 307 ,  325  and  331  are implemented to function as follows. In the circuit, the capacitors  302 ,  303  can be viewed as a first capacitor and the capacitors  305 ,  306  can be viewed as a second capacitor. The first capacitor and the second capacitor can be viewed as a first pair of capacitors; the capacitors  304 ,  307  can be viewed as a second pair of capacitors; and the capacitors  325 ,  331  can be viewed as a third pair of capacitors, wherein the first pair of capacitors are used to hold the sampled voltage of the input signal, and the second pair of capacitors are used to hold the sampled voltage of a differential voltage, which is selected from one of a reference voltage and an output common mode reference ground, and the third pair of capacitors are used to serve as a dump circuit for the reference voltage when the reference voltage is not selected to charge the second pair of capacitors. The first capacitor, composed of capacitors  302  and  303 , both implemented according to a predetermined capacitance, is used to hold a sampled voltage of the positive input signal V inp . The capacitor  304 , implemented according to the predetermined capacitance, is used to hold one voltage selected from a group consisting of a positive reference voltage V refp , a negative reference voltage V refn  and the output common mode reference ground. The second capacitor, composed of capacitors  305  and  306 , both implemented according to the predetermined capacitance, is used to hold a sampled voltage of the negative input signal V inn . The capacitor  307 , implemented according to the predetermined capacitance, is used to hold one voltage selected from a group consisting of the positive reference voltage V refp , the negative reference voltage V refn  and the output common mode reference ground. The capacitor  325 , implemented according to the predetermined capacitance, is used to provide a dump load for the positive reference voltage V refp  when the output voltage of the multiplexer  323  and the output voltage of the multiplexer  324  both connect to the output common mode reference ground. The capacitor  331 , implemented according to the predetermined capacitance, is used to provide a dump load for the negative reference voltage V refn  when the output voltage of the multiplexer  323  and the output voltage of the multiplexer  324  both connect to the output common mode reference ground. 
         [0031]    The twelve sampling phase switches  308 ˜ 315 ,  326 ˜ 327  and  332 ˜ 333  are implemented to function during the sampling phase as follows. The switches  308  and  309  are used to sample the positive input signal V inp  into the capacitors  302  and  303 . The switch  310  is used to connect the bottom plate of the capacitor  304  to an input common mode reference ground and the switch  311  is used to connect the top plate of the capacitor  304  to the output of the multiplexer  323 . The switches  312  and  313  are used to sample the negative input signal V inn  into the capacitors  305  and  306 . The switch  314  is used to connect the bottom plate of the capacitor  307  to the input common mode reference ground and the switch  315  is used to connect the top plate of the capacitor  307  to the output of the multiplexer  324 . The switch  326  is used to connect the bottom plate of the capacitor  325  to the input common mode reference ground and the switch  327  is used to connect the top plate of the capacitor  325  to the output of the multiplexer  330 . The switch  332  is used to connect the bottom plate of the capacitor  331  to the input common mode reference ground and the switch  333  is used to connect the top plate of the capacitor  331  to the output of the multiplexer  336 . 
         [0032]    The eleven charge transfer phase switches  316 ˜ 322 ,  328 ˜ 329  and  334 ˜ 335  are implemented to function during the charge transfer phase as follows. The switch  316  is used to interconnect the top plates of the capacitors  302 ,  303 ,  305  and  306 . The switch  317  is used to connect the bottom plates of the capacitors  302 ,  303  to the negative input end of the OTA  301 . The switch  318  is used to connect the bottom plate of the capacitor  304  to the negative input end of the OTA  301 . The switch  319  is used to connect the bottom plate of the capacitors  304  to the positive output end of the OTA  301 . The switch  320  is used to connect the bottom plates of the capacitors  305  and  306  to the positive input end of the OTA  301 . The switch  321  is used to connect the bottom plate of the capacitor  307  to the positive input end of the OTA  301 . The switch  322  is used to connect the top plate of the capacitor  307  to the negative output end of the OTA  301 . As a result, the capacitors  302 ˜ 307  and the OTA  301  together form a negative feedback circuit to generate the residue output V out  during the charge transfer phase. Besides, the switch  328  is used to connect the bottom plate of the capacitor  325  to the input common mode reference ground and the switch  329  is used to connect the top plate of the capacitor  325  to the output common mode reference ground. The switch  334  is used to connect the bottom plate of the capacitor  331  to the input common mode reference ground and the switch  335  is used to connect the top plate of the capacitor  331  to the output common mode reference ground. The multiplexer  323  is used to provide a first multiplexer output voltage selected from a group consisting of the negative reference voltage V refn , the positive reference voltage V refp  and the output common mode reference ground according to two select signals bp&amp;e and bn&amp;e, wherein bp&amp;e is logic-AND of a positive bit signal bp and a clock signal e, and bn&amp;e is logic-AND of a negative bit signal bn and the clock signal e, and the rising edge of the clock e is the breaking point of the first half period and the second half period of sampling phase. When bp&amp;e=0 and bn&amp;e=0, the first multiplexer output voltage is connected to the output common mode reference ground; when bp&amp;e=0 and bn&amp;e=1, the first multiplexer output voltage is connected to the positive reference voltage V refp ; and when bp&amp;e=1 and bn&amp;e=0, the first multiplexer output voltage is connected to the negative reference voltage V refn . Therefore, the first multiplexer output voltage is connected to the output common mode reference ground during the first half period of sampling phase, and connected to one of the negative reference voltage V refn , the positive reference voltage V refp  and the output common mode reference ground according to the bp&amp;e and bn&amp;e during the second half period of sampling phase. 
         [0033]    The multiplexer  324  is used to provide a second multiplexer output voltage selected from a group consisting of the negative reference voltage V refn , the positive reference voltage V refp  and the output common mode reference ground according to bp&amp;e and bn&amp;e. When bp&amp;e=0 and bn&amp;e=0, the second multiplexer output voltage is connected to the output common mode reference ground; when bp&amp;e=0 and bn&amp;e=1, the second multiplexer output voltage is connected to the negative reference voltage V refn ; and when bp&amp;e=1 and bn&amp;e=0, the second multiplexer output voltage is connected to the positive reference voltage V refp . Therefore, the second multiplexer output voltage is connected to the output common mode reference ground during the first half period of sampling phase, and connected to one of the negative reference voltage V refn , the positive reference voltage V refp  and the output common mode reference ground according to the bp&amp;e and bn&amp;e during the second half period of sampling phase. 
         [0034]    The multiplexer  330  is used to provide a third multiplexer output voltage selected from a group consisting of the positive reference voltage V refp  and the output common mode reference ground according to a select signal e&amp;˜(bp+bn). When e&amp;˜(bp+bn)=0, the third multiplexer output voltage is connected to the output common mode reference ground; when e&amp;˜(bp+bn)=1, the third multiplexer output voltage is connected to the positive reference voltage V refp . Therefore, the third multiplexer output voltage is connected to the output common mode reference ground during the first half period of sampling phase, and connected to one of the positive reference voltage V refp  and the output common mode reference ground according to the e&amp;˜(bp+bn) during the second half period of sampling phase. 
         [0035]    The multiplexer  336  is used to provide a fourth multiplexer output voltage selected from a group consisting of the negative reference voltage V refn  and the output common mode reference ground according to a select signal e&amp;˜(bp+bn). When e&amp;˜(bp+bn)=0, the fourth multiplexer output voltage is connected to the output common mode reference ground; when e&amp;˜(bp+bn)=1, the fourth multiplexer output voltage is connected to the negative reference voltage V refn . Therefore, the fourth multiplexer output voltage is connected to the output common mode reference ground during the first half period of sampling phase, and connected to one of the negative reference voltage V refp  and the output common mode reference ground according to the e&amp;˜(bp+bn) during the second half period of sampling phase. 
         [0036]    The comparator  337 , having a first positive comparing input end, a first negative comparing input end and a first comparing output end, is used to generate the positive bit signal bp according to voltage comparison of the input signal V in  and a first reference voltage V ref /4 at the rising edge of the clock e, wherein the V ref  is equal to the voltage difference between the V refp  and the V refn . The comparator  338 , having a second positive comparing input end, a second negative comparing input end and a second comparing output end, is used to generate the negative bit signal bn according to voltage comparison of the input signal V in  and a second reference voltage −V ref /4 at the rising edge of the clock e, wherein (bp, bn) is (0,0) when V in  is between −V ref /4 and V ref /4; (bp, bn) is (0,1) when V in  is smaller than −V ref /4; and (bp, bn) is (1,0) when V in  is greater than V ref /4. 
         [0037]    The voltage reference buffer  339  is used to provide the V refp  and the V refn , and the voltage reference buffer  339  can be an OTA or a low output impedance amplifier. 
         [0038]    The configurations of the first half period of sampling phase, the second half period of sampling phase and the charge transfer phase of the 1-bit cell circuit according to a preferred embodiment of the present invention is shown in  FIG. 4   a˜c.  Please refer to  FIG. 4   a , which shows an illustrating diagram of the first half period of sampling phase of the 1-bit cell in  FIG. 3 . As shown in  FIG. 4   a , the top plates of the capacitors  302  and  303  are connected to the positive terminal of the V in , and the top plates of the capacitors  305  and  306  are connected to the negative terminal of the V in , and all the bottom plates of the capacitors  302 ,  303 ,  305  and  306  are connected to the input common mode reference ground. The bottom plates of the capacitors  304 ,  307  are connected to the input common mode reference ground, and the top plate of the capacitor  304  is connected to a first reference contact, which is the output of the multiplexer  323 , being connecting to the output common mode reference ground according to the bp&amp;e and bn&amp;e during the first half period of sampling phase, and the top plate of the capacitor  307  is connected to a second reference contact, which is the output of the multiplexer  324 , being connecting to the output common mode reference ground according to the bp&amp;e and bn&amp;e during the first half period of sampling phase. The bottom plates of the capacitor  325 ,  331  are connected to the input common mode reference ground, and the top plates of the capacitors  325 ,  331  are respectively connected to the output ends of the multiplexer  330 ,  336 , being both connecting to the output common mode reference ground according to the e&amp;˜(bp+bn). The comparator  337  generates the positive bit signal bp and the comparator  338  generates the negative bit signal bn at the end of the first half period of sampling phase. 
         [0039]      FIG. 4   b  shows an illustrating diagram of the second half period of sampling phase of the 1-bit cell in  FIG. 3 . As shown in  FIG. 4   b , the top plates of the capacitors  302  and  303  are connected to the positive terminal of the V in , and the top plates of the capacitors  305  and  306  are connected to the negative terminal of the V in , and all the bottom plates of the capacitors  302 ,  303 ,  305  and  306  are connected to the input common mode reference ground. The top plate of the capacitor  304  is connected to the first reference contact, which is the output of the multiplexer  323 , being connecting to one of the negative reference voltage V refn , the positive reference voltage V refp  and the output common mode reference ground according to the bp&amp;e and bn&amp;e. The top plate of the capacitor  307  is connected to the second reference contact, which is the output of the multiplexer  324 , being connecting to one of the negative reference voltage V refn , the positive reference voltage V refp  and the output common mode reference ground according to the bp&amp;e and bn&amp;e. The voltage difference between the top plates of the capacitor  304  and  307  is therefore equal to a first differential voltage (bn-bp)*V ref . The bottom plate of the capacitor  325  is connected to the input common mode reference ground and the top plate of the capacitors  325  is connected to the output of the multiplexer  330 , which is connected to one of the positive reference voltage V refp  and the output common mode reference ground according to the e&amp;˜(bp+bn). The bottom plate of the capacitor  331  is connected to the input common mode reference ground and the top plate of the capacitors  331  is connected to the output of the multiplexer  336 , which is connected to one of the negative reference voltage V refn  and the output common mode reference ground according to the e&amp;˜(bp+bn). The voltage difference between the top plates of the capacitor  325  and  331  is therefore equal to a second differential voltage (1-bn-bp)*V ref . It can be proven that the sum of the absolute value of the first differential voltage (bn-bp)*V ref  and the absolute value of the second differential voltage (1-bn-bp)*V ref  is equal to V ref  no matter what the (bp,bn) may be. 
         [0040]      FIG. 4   c  shows an illustrating diagram of the charge transfer phase of the 1-bit cell in  FIG. 3 . During the charge transfer phase, the top plates of the capacitors  302 ˜ 303 ,  305 ˜ 306  are connected together, and the bottom plates of the capacitors  302 ˜ 303  are connected to the negative input end of the OTA  301 , and the bottom plates of the capacitors  305 ˜ 306  are connected to the positive input end of the OTA  301 ; the bottom plate of the capacitor  304  is connected to the negative input end of the OTA  301 , and the top plate of the capacitor  304  is connected to the positive output end of the OTA  301 , and the bottom plate of the capacitor  307  is connected to the positive input end of the OTA  301 , and the top plate of the capacitor  307  is connected to the negative output end of the OTA  301 ; and the bottom plates of the capacitor  325 ,  331  are connected to the input common mode reference ground and the top plates of the capacitor  325 ,  331  are connected to the output common mode reference ground. In this phase, the V ref  is not used, and due to the virtual ground of the OTA  301  in negative feedback, the charge in the capacitors  302 ˜ 307  will be redistributed to generate the residue output V out =2×V in −(bp−bn)×V ref . 
         [0041]    Please refer to  FIG. 5 , which shows a circuit diagram of a cascade of two 1-bit cells in a pipelined ADC according to a preferred embodiment of the present invention. As shown in  FIG. 5 , the residue output of a 1-bit cell  510  is connected to the input of a 1-bit cell  520 , and the 1-bit cell  510  generates a positive bit signal bp 1  and a negative bit signal bn 1 , and the 1-bit cell  520  generates a positive bit signal bp 2  and a negative bit signal bn 2 . In an n-bit pipelined converter with resolution n&gt;2, there will be at each clock phase more than one cell using the reference voltage (if n is even, there will be always n/2 cells using the reference voltage; if n is odd, there will be alternately (n+1)/2 and (n−1)/2 cells using the reference voltage). In the second half period of all clock phases, V ref  is not used at all, i.e., not used by the cell  510  (and all other odd cells not depicted), nor by the cell  520  (and all other even cells not depicted). This allows the reference voltage to be shared with another set of cells operated with half a clock phase delay, to build a 4× time-interleaved ADC. This feature cannot be achieved in the prior art implementation, not really because the reference voltage is used for the complete duration of each clock period, but rather because of the cascade settling of the reference buffer and OTA in each 1-bit cell. For example, if, at the half instance of a clock phase, a new extra load is suddenly connected to the reference buffer, a resulted glitch will propagate to all the 1-bit cells currently in settling, that will significantly delay their final settling. As a matter of fact, the novel implementation of the present invention uses the reference voltage only for half the duration of each clock phase, while the maximal current (or load) sunk from the reference voltage is staying the same. This fact, together with the relaxed requirement on the reference settling, makes the 4× time-interleaved ADC possible. 
         [0042]    In summary, according to the present invention, the positive reference voltage V refp  has a load capacitor with constant initial charge no matter what bp and bn may be during the second half period of sampling phase, and the load capacitor can be the capacitor  304  when bp&amp;e=0 and bn&amp;e=1, or be the capacitor  307  when bp&amp;e=1 and bn&amp;e=0, or be the capacitor  325  when bp&amp;e=0 and bn&amp;e=0 (i.e., e&amp;˜(bp+bn)=1); and the negative reference voltage V refn  has a load capacitor with constant initial charge no matter what bp and bn may be during the second half period of sampling phase, and the  32  1, gload capacitor can be the capacitor  307  when bp&amp;e=0 and bn&amp;e=1, or be the capacitor  304  when bp&amp;e=1 and bn&amp;e=0, or be the capacitor  331  when bp&amp;e=0 and bn&amp;e=0 (i.e., e&amp;˜(bp+bn)=1). 
         [0043]    As a result, the sum of the absolute value of a first differential voltage, which is the voltage difference between the first multiplexer output voltage and the second multiplexer output voltage, and the absolute value of a second differential voltage, which is the voltage difference between the third multiplexer output voltage and the fourth multiplexer output voltage, is equal to a settling voltage of the reference voltage V ref  at the end of the second half period of sampling phase, wherein the reference voltage V ref  is the voltage difference between the positive reference voltage V refp  and the negative reference voltage V refn . The capacitors  325  and  331  therefore serve as a dump circuit for the positive reference voltage V refp  and the negative reference voltage V refn  respectively when the capacitors  304  and  307  are isolated from the positive reference voltage V refp  and the negative reference voltage V refn  by the multiplexers  323  and  324  in the case of (bp, bn)=(0,0). 
         [0044]    Therefore, a novel 1-bit cell according to the present invention is proposed. The novel 1-bit cell ensures that the amount of charges provided by the reference buffer in each clock period is not dependent on the signal currently converted. Besides, assuming that the clock has achieved the minimal jitter required for aperture noise concerns on high frequency input signal, the novel 1-bit cell ensures both a constant load and a constant settling time for the reference buffer to have a constant settling, even if incomplete, whereas, with a load depending on input signal, full settling is the only way to guaranty a constant final value. Furthermore, it is known that the group delay of a 1-bit cell is critical for the data rate of a pipelined converter in that a shorter group delay will result in a higher data rate, and also critical for the total conversion delay, the time elapsed between signal sampling and full n-bit code delivery, which is of extreme importance in some application like AGC (Automatic Gain Control) or other closed loop systems. The 1-bit cell of the present invention preserves the fundamental 1-clock phase group delay, i.e., a new residue output is delivered to the next cell exactly one clock phase after an old residue was sampled from the previous cell, so it can offer a smallest group delay, a smallest total conversion delay and therefore a high data rate. The present invention thus possesses the following advantages. First, the settling voltage of the second pair of capacitors needs not equal to the reference voltage V ref , so the speed requirement on the reference buffer can be relaxed, and the power needed by the reference buffer is thereby reduced. Second, since during the second half period of sampling phase the voltage reference V ref  always has a pair of capacitors implemented according to a predetermined capacitance, and the pair of capacitors being with constant initial charge, the total charge supplied by the voltage reference V ref  is therefore constant, i.e. independent of the input signal. Even though there exists mismatch between the capacitors, for example, ˜0.1%, the variation of the charge taken from the voltage reference V ref  will be ˜0.1%×the predetermined capacitance×V ref /2, much smaller than the 0.75×Cs×V ref /2 of the prior art. This ensures a constant value to the final output voltage of the reference buffer, and thus avoids any samples interference of the input signal and greatly improves the linearity of the ADC operation. Third, compared to the prior art 1-bit cell circuit, the settling of the reference buffer is not interfering with the setting of the OTA&#39;s (no cascade setting), and thereby avoids any slow down of each cell settling. Fourth, since the reference buffer is only used half the time, it can, within same power, be shared by one more ADC time-shifted by half a clock cycle to build a 4× interleaved ADC even if scaling down design is progressively applied from 1 st  (MSB) to last (LSB) cells for optimal power and area concerns. Finally, the novel design of the 1-bit cell of the present invention offers the signal independent loading of the reference voltage with only 1-clock phase group delay. 
         [0045]    Through the implementation of the 1-bit cell circuit used in pipelined ADCs according to a preferred embodiment of the present invention, a novel pipelined ADC is presented. The topology of the present invention saves much more power than prior art circuits and can be utilized to build a 4× interleaved ADC, so the contribution of the present invention is indeed worthy of the grant of a patent. 
         [0046]    While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. 
         [0047]    In summation of the above description, the present invention herein enhances the performance than the conventional structure and further complies with the patent application requirements and is submitted to the Patent and Trademark Office for review and granting of the commensurate patent rights.