Abstract:
Timing-signal delay equipment which provides an adjustable delay time, equal to a multiple of a predetermined time unit, to an input signal pulse is used as a timing source required in a circuit tester of LSIs (semiconductor large-scale integrated circuits). The timing-signal delay equipment has a plurality of delay elements (D ij  &#39;s) with weighted delay times arranged in a matrix form; a selector (S) coupled with the matrix for selecting one of the delay elements for each column of the matrix, wherein the selected delay elements are connected in series; and an arithmetic control circuit (M) that controls the selectors based on a set-up value of delay time and an error in delay time of each delay equipment. In order to provide a delay time which is equal to a multiple of a predetermined time unit in spite of an error in delay time of each delay element, either a correction matrix is connected in series to the matrix or the weight of each delay element is modified.

Description:
FIELD OF THE INVENTION 
     The Invention relates to timing-signal delay equipment that gives a predetermined set-up value of delay time to a timing signal. 
     BACKGROUND OF THE INVENTION 
     FIG. 7 shows one of the conventional timing-signal delay equipment where an input timing signal Q1 is supplied to a logic gate 1 whose output is connected to a cascade circuit G composed of n delay elements D 1  -D n  connected serially, each of which is of the same structure comprising a resistor R and a variable capacitor C as shown. The binary coded error information E, which is defined to represent the difference between a predetermined set-up value of delay time and the delay time of an output timing signal Q2 actually obtained at the cascade circuit G to its input timing signal Q1, makes a D/A converter B generate an analog control signal that controls the capacitance of each variable capacitor in delay elements D 1  -D n  so that the delay time of output timing signal Q2 to its input timing signal Q1 becomes almost equal to said set-up value. 
     FIG. 8 shows another conventional timing-signal delay equipment which has a cascade circuit G composed of a waveform converter 11 which converts an input timing signal Q1 to a triangular waveform, whose output is connected to a threshold gate circuit 12. A D/A converter B with error information E of the same definition as before at its input, provides an analog control signal that controls the threshold level of the threshold gate circuit 12 so that the delay time of an output timing signal Q2 obtained at the cascade circuit G to its input timing signal Q1 becomes almost equal to said set-up value. 
     DISADVANTAGES TO BE SOLVED BY THE INVENTION 
     The type of timing-signal delay equipment shown in FIG. 7, however, has the following drawback. As the degree of precision in the delay time given by the equipment a timing signal depends on the fineness in structure of the D/A converter B, which makes it difficult to integrate the whole circuitry into a small size and with high density with IC technology. 
     The same is true for the type of timing-signal delay equipment shown in FIG. 8, where the waveform converter 11, threshold gate circuit 12, and the D/A converter B should be of finely controlled structure in order to generate an output timing signal with a precisely specified delay time. 
     SUMMARY OF THE INVENTION 
     The object of the invention, accordingly, is to provide new types of timing-signal delay equipment without above drawback. 
     A type of timing-signal delay equipment noted in the first invention of this specification has a cascade circuit composed of a plural number (=n) of delay circuits U 1  -U n  connected serially, each of which has a plural number (=m) of delay elements D 1  -D m  that give mutually different m values of delay time to a timing signal, and has a selection circuit connected to its input side or output side for selecting one of said m delay elements D 1  -D m  on receiving control information, and said timing-signal delay equipment has also an arithmetic control circuit which receives both set-up information representing a predetermined set-up value of delay time that an output timing signal should have to its input timing signal and error information representing the difference between the delay time of an output timing signal obtained at the cascade circuit to its input timing signal and said set-up value and performs necessary calculations with them to generate said control information to each selection circuit of said delay circuits U 1  -U n  so that said output timing signal obtained at said cascade circuit has a delay time to said input timing signal whose value is an optimum approximation to said set-up value. 
     A type of timing-signal delay equipment noted in the second invention has a cascade circuit that comprises two circuit units connected serially. The first circuit unit is composed of a plural number (=n) of main delay circuits U 1  -U n  connected serially, each of which has a plural number (=m) of delay elements D 1  -D m  that give mutually different m values of delay time to a timing signal, and has a selection circuit connected to its input side or output side for selecting one of said m delay elements D 1  -D m  on receiving control information. The second circuit unit is composed of an integer (=l) number of correction delay circuits U 1  &#39;-U l  &#39; connected serially where l is greater than or equal to 1, each of which has a plural number (=k) of correction delay elements D 1  &#39;-D k  &#39; that give mutually different k values of delay time to a timing signal, and has a correction selection circuit for selecting one of said k correction delay elements D 1  &#39;-D k  &#39; on receiving correction control information. The timing-signal delay equipment has also an arithmetic control circuit which receives both set-up information representing a predetermined set-up value of delay time that an output timing signal should have to its input timing signal, and error information representing the difference between the value of delay time that an output timing signal obtained at said cascade actually has to its input timing signal and said set-up value, performs necessary calculations with them to generate said control information to each of the selection circuits in said delay circuits U 1  -U n  and said correction control information to each of the selection circuits in correction delay circuits U 1  &#39;-U l  &#39; so that said output timing signal obtained at said cascade circuit has a desired delay time to said input timing signal whose value is an optimum approximation to said set-up value. 
     According to a type of timing-signal delay equipment noted in the first invention of this specification, one of delay elements D 1  -D m  in each of delay circuits U 1  -U n  is selected by its selection circuit, and output timing signal obtained at the cascade circuit has a delay time to its input timing signal that is the sum of n delay times, each of which is the delay time of one of the selected delay elements. Thus the function of timing-signal delay equipment is obtained. 
     Moreover, when the value of delay time of each of delay elements D 1  -D m  in each of delay circuits U 1  -U n  is designed properly, then even if said delay time is not realized so precisely in the circuitry or each of the delay elements D 1  -D m  in each of the delay circuits U 1  -U n  is not in high precision, the timing-signal delay equipment can provide an output timing signal with a delay time of a precise value. 
     As delay elements D 1  -D m  in each of delay circuits U 1  -U n  are not necessarily of highly precise structure, and selection circuits associated with delay circuits U 1  -U n  and the arithmetic control circuit are easily integrated with IC technology, said type of timing-signal delay equipment can be integrated into a small size and with high density with ease. 
     In addition, in a type of timing-signal delay equipment noted in the first invention of this specification, suppose that T d  stands for an expected set-up temporal resolution, T ij  stands for the delay time of i&#39;th delay element D i  (i=1,2, - - - ,m) of j&#39;th delay circuit U j  (j=1,2, - - - ,n). 
     When the delay time T ij  satisfies the relation below, 
     
         T.sub.ij =T.sub.d.(i-1).m.sup.j-1                          ( 1) 
    
     then if the delay time by each delay element which gives a timing signal, has no relative error but some absolute error, then, this type of timing-signal delay equipment can provide an output timing signal whose delay time to its input timing signal is given by one of a plural number of values starting with a value equal to the sum of the values of said set-up temporal resolution and said absolute error, its double, its triple, and so on leaping one after another with an equal distance being equal to the first value. 
     Also, in a type of timing-signal delay equipment noted in the first invention of this specification, suppose that T d  stands for an expected set-up temporal resolution, T ij  stands for the delay time of i&#39;th delay element D i  (i=1,2, - - - ,m) of j&#39;th delay circuit U j  (j=1,2, - - - ,n) and e stands for the absolute value of said T ij  &#39;s relative error rate. 
     When the delay time T ij  satisfies the relation below, ##EQU1## then if the delay time of each delay element which gives a timing signal has a relative error, this type of timing-signal delay equipment can provide an output timing signal whose delay time to its input timing signal is given by one of a plural number of values starting with a value equal to the sum of the value of said set-up temporal resolution and the absolute value of said relative error, its double, its triple, and so on leaping one after another with an equal distance being equal to the first value. 
     According to the type of timing-signal delay equipment noted in the second invention of this specification, one of delay elements D 1  -D m  in each of main delay circuits U 1  -U n  is selected by its selection circuit and one of correction delay elements D 1  &#39;-D k  &#39; in each of correction delay circuits U 1  &#39;-U l  &#39; is selected by its selection circuits, an output timing signal obtained at the cascade circuit has a delay time to its input timing signal which is equal to the total sum of the sum of n delay times, each of which is the delay time of one of the selected main delay elements, and the sum of l delay times, each of which is the delay time of one of the selected correction delay elements gives a timing signal. Thus the function of timing-signal delay equipment is obtained as the case of the type of timing-signal delay equipment noted in the first invention. 
     Like the type of timing-signal delay equipment noted in the first invention, in this case when the delay time of each of delay elements D 1  -D m  in each of main delay circuits U 1  -U n  and the delay time of each of correction delay elements D 1  &#39;-D k  &#39; in each of correction delay circuits U 1  &#39;-U l  &#39; are designed properly, then even if said delay times are not realized so precisely in circuitry or each of delay elements D 1  -D m  in each of delay circuits U 1  -U n  and each of correction delay elements D 1  &#39;-D k  &#39; in each of correction delay circuits U 1  &#39;-U l  &#39; are not manufactured with high precision, the timing-signal delay equipment can provide an output timing signal with a delay time of a precise step value. 
     As the type of timing-signal delay equipment noted in the second invention has not only delay circuits U 1  -D m  but also correction delay circuits U 1  &#39;-U l  &#39; it can provide an output timing signal with a more precise value of delay time as compared with one obtained at the type of timing-signal delay equipment noted in the first invention. 
     In this case, like the type of timing-signal delay equipment noted in the first invention of this specification, delay elements D 1  -D m  in each of main delay circuits U 1  -U n  and correction delay elements D 1  &#39;-D k  &#39; in each of correction delay circuits U 1  &#39;-U l  &#39; are not necessarily manufactured with high precision, together with the selection circuits connected with main delay circuits U 1  -U n  and correction delay circuits U 1  &#39;-U l  &#39; and the arithmetic control circuit are easily integrated with IC technology, the type of timing-signal delay equipment noted in the second invention of this specification can be integrated into a small size and with high density with ease. 
     In addition, in the type of timing-signal delay equipment noted in the second invention, suppose that T d  stands for an expected set-up temporal resolution, T ij  stands for the delay time of i&#39;th delay element D i  (i=1,2, - - - ,m) of j&#39;th delay circuit U j  (j=1,2, - - - ,n). And also, T.sub.αβ  stands for the delay time of α-th correction delay element D.sub.α &#39; (α=1,2, - - - ,k) of β-th correction delay circuit U.sub.β &#39; (β=1,2, - - - ,l). When the delay time T ij  satisfies the relation of the equation (1) described earlier, and the delay time T.sub.αβ satisfies the relation below, 
     
         T.sub.αβ =T.sub.d.(α-1).k.sup.β-1    ( 3) 
    
     then, if the delay time of each delay element and the delay time of each correction delay element have some relative error, like the case of the type of timing-signal delay equipment noted in the first invention where the relation of the equation (2) described earlier is satisfied, this type of timing-signal delay equipment can provide an output timing signal whose delay time to its input timing signal is given by a desired value chosen from a plural number of values starting with a value equal to the sum of the values of said set-up temporal resolution and said relative error, its double, its triple, and so on, leaping one after another with an equal distance being equal to the first value. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is the systematic block diagram of an embodiment of timing-signal delay equipment noted in the first invention of this specification. 
     FIG. 2 is the block diagram of a delay element structure for each of delay elements D 1  -D 4  in each of delay circuits U 1  -U 3  of FIG. 1. 
     FIG. 3 and FIG. 4 are a matrix representation of delay time, where the delay time of i&#39;th delay element D i  (i=1, - - - , 4) of j&#39;th delay circuit U j  (j=1, - - - , 3) in the timing-signal delay equipment noted in this invention shown in FIG. 1 gives a timing signal as indicated. 
     FIG. 5 is the systematic block diagram of an embodiment of timing-signal delay equipment noted in the second invention of this specification. 
     FIG. 6 is a matrix representation of delay time, where the delay time of i&#39;th delay element D i  (i=1, - - - , 4) of j&#39;th delay circuit U j  (j=1, - - - , 3) gives a timing signal, and the delay time of i&#39;th correction delay element D i  (i=1, - - - , 4) of correction delay circuit U 1  &#39; gives a timing signal as indicated. 
     FIG. 7 and FIG. 8 are the systematic block diagram of the conventional timing-signal delay equipment. 
     FIG. 9 is the functional block diagram of an embodiment of the arithmetic control circuit noted in this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiment 1 
     An embodiment of timing-signal delay equipment noted in the first invention of this specification is described in accordance with FIG. 1. 
     The embodiment of timing-signal delay equipment shown in FIG. 1 has a cascade circuit G that is composed of a plural number n (e.g., n=3), of delay circuits U 1  -U n (=3) connected serially. 
     Each delay circuit U j  (j=1,2, - - - , n(=3)) has a plural number m (e.g., m=4), of delay elements D 1  -D m (=4) that give mutually different delay times to a timing signal, and a selection circuit S connected to, e.g., the output side of delay elements D 1  -D m (=4) that selects one of the m (in this case, m=4) delay elements according to a control signal sent from an arithmetic control circuit M described later. 
     An example of delay element D i  (i=1,2, - - - , m(=4)) of delay circuit U j  (j=1,2, - - - , n(=3)) is shown in FIG. 2 where a transmission system with a NAND gate 21 is used. This transmission system has its line capacitance 22, a capacitor element 23 utilizing the base-collector capacitance of a bipolar transistor, a capacitor element 24 utilizing the base-emitter capacitance of a bipolar transistor and the like connected along the line. 
     Moreover, the timing-signal delay equipment shown in FIG. 1 has an arithmetic control circuit M for each selection circuit S in delay circuit U 1  -U 3 . 
     Set-up information (which is denoted by P) is defined to represent the value of a predetermined set-up delay time (which is denoted by T P ) of an output timing signal Q2 obtained at the cascade circuit G to its input timing signal Q1, and error information (which is denoted by E) is defined to represent the difference between an actual delay time (which is denoted by T R ) of said output timing signal Q2 to said input timing signal Q1 and said set-up value T P , whose definition is the same as those in the cases of FIG. 7 and FIG. 8. 
     On receiving set-up information P and error information E, the arithmetic control circuit M performs necessary calculations with them to produce control information W 1  -W 3  for each selection circuit S of delay circuits U 1  -U 3  so that T R , actually obtained delay time, becomes an optimum approximation to T P , said set-up value. 
     What is described above is a brief explanation of the embodiment of timing-signal delay equipment noted in the first invention of this specification. 
     According to this structure of timing-signal delay equipment noted in the first invention of this specification, one of delay elements D 1  -D 4  in each of delay circuits U 1  -U 3  is selected by its selection circuit S, an output timing signal that has a delay time to its input timing signal, whose value is nearly equal to said set-up value T p  and is the sum of the three delay times, each of which is the delay time of one of the selected delay elements can be obtained at the cascade circuit G. 
     That is, when the delay time that delay element D i  (i=1,2, - - - , m(=4)) of delay circuit U j  (j=1,2, - - - , n(=3)) gives a timing signal is denoted by T ij , and in delay circuit U 1 , for example, delay element D 2  is selected by its selection circuit S based on the contents of control information W 1 , in delay circuit U 2 , for example, delay element D 1  is selected by its selection circuit S based on the contents of control information W 2 , and in delay circuit U 3 , for example, delay element D 3  is selected by its selection circuit S based on the contents of control information W 3 . 
     Then, an output timing signal with a delay time T R  to its input timing signal, is obtained at the cascade circuit where T R  is expressed as follows. 
     
         T.sub.R =T.sub.21 +T.sub.12 +T.sub.33 
    
     And T R  is nearly equal to said set-up value T P   
     This shows that the structure of timing-signal delay equipment in FIG. 1 has the function of timing-signal delay equipment. 
     And, as an output timing signal Q2 with said delay time can be obtained at the cascade circuit G, if T 11  -T 41 , T 12  -T 42 , T 13  -T 43 , the delay times which delay elements D 1  -D 4  in delay circuit U 1 , delay elements D 1  -D 4  in delay circuit U 2 , and delay elements D 1  -D 4  in delay circuit U 3  &#39; give a timing signal, respectively, are chosen in an appropriate way in advance, then even if their values are (T 11  -T 41 , T 12  -T 42 , T 13  -T 43 ) not so accurately realized in circuitry, or in other words, delay elements D 1  -D 4  in each of delay circuits U 1  -U 3  are not manufactured with high precision, an output timing signal Q 2  with a delay time of high precision can be obtained at the cascade circuit G. 
     As delay elements D 1  -D 4  in each of delay circuits U 1  -U 3  are not necessarily manufactured with high precision, and the selection circuit S in each of delay circuits U 1  -U 3  and the arithmetic control circuit M are easily integrated with IC technology, this type of timing-signal delay equipment can be integrated into a small size and with high density with ease. 
     Moreover, in the structure of timing-signal delay equipment shown in FIG. 1, suppose that T d  stands for an expected set-up temporal resolution of said set-up value, T ij  stands for the delay time of the delay element D i , and delay element D i  of delay circuit U j  is so designed that its delay time T ij  satisfies the relation below which is the same as the equation (1) described earlier. 
     
         T.sub.ij =T.sub.d . (i-1) m.sup.j-1                        (4) 
    
     As an example, said set-up temporal resolution T d  is supposed to be equal to 10 ps. (pico second), and the values of T ij  &#39;s are, according to the equation (4), given in pico second in FIG. 3. 
     Suppose that an output timing signal Q2 with the maximum delay time T max  to its input timing signal Q1 is obtained at the cascade circuit G. It is obvious that T max  is given by the following equation. 
     
         T.sub.max =T.sub.d.(m.sup.n -1)                            (5) 
    
     If each of the delay times that delay elements D 1  -D 4  in delay circuits U 1  -U 3  give a timing signal, has an absolute error (which is denoted by T e ) but has no relative error (which is denoted by T c ), an output timing signal obtained at the cascade circuit G is with a delay time to its input timing signal whose value is a desired one chosen from a set of values starting with (T d  +T e ), the sum of the values of said set-up temporal resolution and said absolute error, (for simplicity this is denoted by T.sub. q), its double (2T q ), its triple (3T q ), and so on, leaping one after another with an equal distance of T q , until reaching (T d  +T e ) (m n  -1) that is obtained by replacing T d  in the right-hand side term of the equation (5) with (T d  +T e ). 
     For example, suppose that said set-up temporal resolution T d  is 10 ps., and T ij , the delay time that the delay element D i  of delay circuit U j  gives a timing signal, is given by FIG. 3, and said absolute error T e  is 10%, an output timing signal Q2 obtained at the cascade circuit G is with a delay time to its input timing signal Q1 whose value is a desired one chosen from the sequence of values below. 
     T q  (=10±1), 2T q  (=2(10±1)), 3T q  (=3(10±1)), - - - 
     When T ij , the delay time associated with delay element D i  of delay circuit U j  is designed to satisfy said relation of the equation (4) but has some relative error T c , the delay time of an output timing signal is not given by one chosen from a plural number of values that are arranged with an equal distance of T q , i.e., T q , 2T q , 3T q , - - - . Instead, it is given by one chosen from a plural number of values that are found between (T d  +T c ), sum of the values of said set-up temporal resolution T d  and said relative error T c , and (T d  +T c )(m n  -1), that is obtained by replacing T d  in the right-hand side term of the equation (5) with (T d  +T c ), with unequal distances that are greater than said distance or leap time T q  (step size of delay time). In this case, the maximum leap time (which is denoted by T m ) is given by the following equation. 
     
         T.sub.m =e.T.sub.d (2m.sup.n -2m.sup.n-1 -1)               (6) 
    
     where e is the absolute value of the relative error rate of delay time T ij . 
     In the structure of timing-signal delay equipment shown in FIG. 1, delay element D i  of delay circuit U j  is designed so that said delay time T ij  satisfies the relation below which is the same as the equation (2) described earlier. ##EQU2## 
     For example, support m=4, and let&#39;s determine T 21 . As (1-e)T 11  =0, the first term on the right-hand side of the equation (7), so 
     (1+e)T 21  ≈T d  and T 21  is determined as 
     T 21  ≈T d  /(1+e). 
     In the same way, from (1+e)T 31  ≈(1-e)T 21  +T d , the T 31  is determined as T 31  ≈2/(1+e) T 21 . 
     And from (1+e)T 41  ≈(1-e)T 31  +T d , the T 41  is determined as T 41  ≈(1-e)/(1+e) T 31  +T 21 , from (1+e)T 22  ≈(1-e)(T 41  +T 12 )+T d , the T 22  is determined as, T 22  ≈(1-e)/(1+e) (T 41  +0)+T 21 , and so on. 
     The value of T ij  &#39;s are, in this way, determined one after another from the smallest toward larger in an ascending order. For example, suppose delay element D i  of delay circuit U j  is designed so that the delay time T ij  that said delay element gives a timing signal can satisfy said equation (7). With the value of said set-up temporal resolution T d  being equal to 10 ps., the values of T ij  &#39;s are given in pico second in FIG. 4. 
     Then, the maximum delay time T max  of an output timing signal Q2 obtained at the cascade circuit G to its input timing signal Q1 is, considering said relative error rate ±e, given by the relation below. 
     
         [{(1-E).sup.m /(1-E)}.sup.n -1]. T.sub.d≦T.sub.max≦(1/E)[{(1-E).sup.m /(1-E)}.sup.n -1] . T.sub.d              (8) 
    
     where E=(1-e)/(1+e). 
     Even if the delay time that each of delay elements D 1  -D 4  in delay circuits U 1  -U 3  gives a timing signal, has a relative error, the cascade circuit G can provide an output timing signal Q2 whose delay time to its input timing signal Q1 whose value is a desired one chosen from a plural number of values that are found between (1+e)T d  and [{(1-E) m  /(1-E)} n  -1].T d , the minimum value of the maximum delay time T max  of the equation (8), with a leap time of (1+e)T d  (which is denoted by T q  &#39;), i.e., T q  &#39;, 2T q  &#39;, 3T q  &#39;, - - - . 
     The arithmetic control circuit M, as shown in FIG. 9, has a group of registers 1, an adder 2, a subtractor 3, and a comparator 4, and those are basic facilities of the one-chip microprocessor. 
     A combination of delay elements to be selected that gives an optimum approximation to a given set-up value T P  is determined in the procedures as follows. In FIG. 9, P stands for set-up information, E stands for error information, W stands for control information, and W&#39; stands for correction control information. 
     That is, 
     (1) The measured delay time value of each delay element is stored in the group of registers 1 in advance. 
     (2) For each delay circuit, comparison is made between a given set-up delay time T P  and one of the measured delay time values, one after another, in a descending order of their values. 
     (3) When a compared one is found to be smaller than T P , its delay element is selected, and the difference between said set-up value T P  and the measured delay time value, which is denoted by T P  &#39;, is used as an updated set-up value for next delay circuit. 
     (4) Steps (2) and (3) are carried out one delay circuit after another, from the delay circuit with the largest delay time downward, and when said set-up value reaches smaller than the set-up temporal resolution T d , the process is stopped. 
     (5) If some delay circuits remain uncompared when the process is stopped, their delay elements with zero delay time are selected. 
     As an example, suppose that said set-up temporal resolution T d  is 9 ps. and delay element D i  of delay circuit U j  is so designed that the delay time T ij  that it gives a timing signal is given by FIG. 4. If said relative error T c  is ±10% of the delay time that each delay element gives a timing signal, the cascade circuit G can provide an output timing signal Q2 whose delay time to its input timing signal Q1 is a desired one chosen from the following sequence of values. 
     T q  &#39;(=9±0.9), 2T q  &#39;(=2(9±0.9)), 3T q  &#39;(=3(9±0.9)), - - - . 
     Embodiment 2 
     Then, let&#39;s explain an embodiment of timing-signal delay equipment noted in the second invention of this specification with FIG. 5. 
     In FIG. 5, functional parts corresponding to those shown in FIG. 1 are referred by the same symbols, and detailed explanation about them is omitted for simplicity. 
     The structure of timing-signal delay equipment shown in FIG. 5 is the same as the structure of timing-signal delay equipment shown in FIG. 1 except the points to described below. 
     That is, in FIG. 5, the cascade circuit G, composed of a plural number (=n) of delay circuits U 1  -U n  connected in series, shown in FIG. 1 is connected with a cascade circuit G&#39; that is composed of l (which is an integer greater than or equal to (1) correction delay circuits U 1  &#39;-U l  &#39; connected in series. In FIG. 5, the case where l=&#39;1&#39; is shown for simplicity. 
     Each correction delay circuit U.sub.β &#39; (β=1,2, - - - , l) has, like delay circuit U j  shown in FIG. 1, a plural number k (e.g., k=4) of correction delay elements D 1  &#39;-D&#39; k (=4) that give mutually different delay times to a timing signal, and a selection circuit S&#39; connected to e.g., the output side of correction delay elements D 1  &#39;-D&#39; k (=4) that selects one of correction delay elements D 1  &#39;-D&#39; k (=4) based on correction control information W.sub.β(=1) &#39; sent from an arithmetic control circuit M. 
     Said system shown in FIG. 2 that can be used as delay element D i  of delay circuit U j  can be used as correction delay element D.sub.α &#39;(α=1,2, - - - , k) of correction delay circuit U.sub.β &#39;. 
     The arithmetic control circuit M functions in a similar manner to that shown in FIG. 1. The arithmetic control circuit M receives both set-up information P defined to represent a set-up delay time T P  that an output timing signal Q2 obtained at the cascade circuit composed of the cascade circuit G and the cascade circuit G&#39; connected in series should have to its input timing signal Q1, and error information E defined to represent the difference between said set-up value T P  and the delay time T R  that an output timing signal Q2 obtained at the cascade circuit composed of the cascade circuit G and the cascade circuit G&#39; connected in series really has to its input timing signal Q1. 
     It performs necessary calculations with said set-up information and said error information to generate control information W 1  -W n  for each selection circuit S in delay circuits U 1  -U n , and correction control information W 1  --W l  &#39; for each selection circuit S&#39; in correction delay circuits U 1  &#39;-U l  &#39; in such a way that the delay time T R  of an output timing signal Q2 obtained at said cascade circuit to its input timing signal Q1 is an optimum approximation to said set-up value T P . 
     What is explained above is the structure of the embodiment of timing-signal delay equipment noted in the second invention of this specification. 
     As the structure of timing-signal delay equipment noted in the second invention of this specification is like that of timing-signal delay equipment noted in the first invention of this specification except for said cascade circuit G&#39; added, it is not necessary to explain it in detail. 
     In the structure of timing-signal delay equipment noted in the second invention of this specification, an output timing signal Q2 is obtained at the cascade circuit composed of the cascade circuit G and the cascade circuit G&#39; connected in series. The total delay time to its input timing signal Q1 is given by the total sum of the sum of n delay times that one of delay elements D 1  -D m  in each of main delay circuits U 1  -U n  selected by its selection circuit S and sum of l, delay times that one of correction delay elements D 1  &#39;-D k  &#39; in each of correction delay circuits U 1  &#39;-U l  &#39; selected by its selection circuit S&#39;. Said total delay time is an optimum approximation to said set-up value T P . 
     Accordingly, it has the function of timing-signal delay equipment just like the structure of timing-signal delay equipment noted in the first invention of this specification shown in FIG. 1. 
     The structure of timing-signal delay equipment shown in FIG. 5, like the case shown in FIG. 1, can provide an output timing signal Q2 at the cascade circuit composed of the cascade circuit G and the cascade circuit G&#39; connected in series with a precise delay time to its input timing signal Q1, even though delay elements D 1  -D m  in delay circuits U 1  -U n  and correction delay elements D 1  &#39;-D k  &#39; in correction delay circuits U 1  &#39;-U l  &#39; are not made with high precision. Therefore, like the case of timing-signal delay equipment shown in FIG. 1, this type of timing-signal delay equipment can be integrated into a small size and with high density with ease. 
     Moreover, in the structure of timing-signal delay equipment shown in FIG. 5, suppose that delay element D i  of delay circuit U j  is so designed that the delay time T ij  that delay element D i  of delay circuit U j  gives a timing signal satisfies said relation of the equation (4), and correction delay element D.sub.α &#39; in correction delay circuit U.sub.β &#39; is so designed that the delay time T.sub.αβ that correction delay element D.sub.α &#39; of correction delay circuit U.sub.β &#39; gives a timing signal satisfies the relation to follow that is similar to said equation (4). 
     
         T.sub.αβ =T.sub.d . (α-1)m.sup.-1         (9) 
    
     And, the number of correction delay elements D 1  &#39;-D k  &#39; and l, the number of correction delay circuits U 1  &#39;-U l  &#39; are chosen in advance in such a way that an output timing signal obtained at the cascade circuit G&#39; is with a delay time that can be one of values that increase one after another with a leap time of the temporal resolution T d  until the maximum leap time T m  of the equation (6) obtained in the case of the cascade circuit G. 
     Then, in an output timing signal Q2 obtained at the cascade circuit composed of the cascade circuit G and the cascade circuit G&#39; connected in series with the maximum delay time to its input timing signal Q1, the maximum delay time T max  is, as there is said relative error rate ±e, given as follows. 
     
         (1-e)(m.sup.n -1)T.sub.d ≦T.sub.max                 (10) 
    
     T max  ≦(1+e)(m n  -1)T d   
     Even though the delay times that delay elements D 1  -D m  in delay circuits U 1  -U n  and correction delay elements D 1  &#39;-D k  &#39; in correction delay circuits U 1  &#39;-U l  &#39; give a timing signal, have a relative error, an output timing signal Q2 obtained at the cascade circuit composed of the cascade circuit G and the cascade circuit G&#39; connected in series can have a delay time to its input timing signal Q1 whose value is a desired one chosen from a plural number of values increasing one after another with a leap time being equal to (1+e)T d  that are found in an interval between (1+e)T d  and at least {(1-e)(m n  -1)T d  }, the minimum value of the maximum delay time T max  shown in the equation (10). That is, if (1+e)T d , said leap time, is denoted by T q  &#39; these values are given as follows. 
     
         T.sub.q &#39;, 2T.sub.q &#39;, 3T.sub.q, - - - 
    
     Arithmetic control circuit M can be made as shown in FIG. 9, with a group of registers, an adder, a substractor and a comparator which are basic facilities of the one-chip microprocessor for ordinary use. The combination of delay elements that provides an optimum approximation to a given set-up value T P  is determined in the following procedures. That is, 
     (1) The value of T m  /2, where T m  is the maximum leap time given by the equation (6), and the measured delay time values of delay elements in all the delay circuits including correction delay circuits, are stored in said group of registers in advance. 
     (2) Adding said T m  /2 to a given set-up delay time T P  and the sum, denoted by T&#39;, is stored in the group of registers as the delay time to be generated. 
     (3) The measured delay time values of delay elements to be selected in delay circuits, determined by the value of said set-up delay time T P , are read out of the group of registers and added up together. The sum, denoted by T 1 , is stored in the group of registers. T 1  is the delay time actually generated by the delay circuits. 
     (4) Substracting said T 1  from the delay time to be generated T&#39; and the difference obtained is denoted by T 2 . T 2  is the delay time to be generated by the correction delay circuits. 
     (5) The measured delay time values of correction delay elements are read out of the group of registers and compared with said T 2  to be generated, and the correction delay element whose measured delay time gives the nearest to the value of T 2 , is selected. 
     While the invention has been particularly shown and described, in reference to preferred embodiments thereof, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the invention. 
     APPLICATION TO INDUSTRY 
     As explained above, according to the invention, a delay time being equal to a multiple of a predetermined unit can be provided even though the delay elements for it have an error in their delay time values. 
     The invention is utilized for generating timing signals for use in testing IC&#39;s.