Abstract:
A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory transients (&#34;ringing&#34;), along with its associated voltage spikes at the associated output transistor source, can be avoided. Such transients and their associated voltages are avoided by clamping the gate-source voltage on the circuit&#39;s output NMOS transistor over the entire positive operation voltage range.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The invention relates generally to electronic circuitry, and more particularly to circuitry for clamping gate to source of MOS transistors. 
     BACKGROUND OF THE INVENTION 
     For many applications, it is desirable, when converting a voltage from one level to another, to do so in a manner that is substantially power lossless. One popular way to accomplish this objective is to utilize a switch mode regulator circuit as an interface between a voltage supply and device to be driven, such as a motor. Switch mode regulators can be used, for example, in personal computer power supplies, where an AC voltage is stepped down from line voltage to computer operating voltage, typically on the order of about 5 volts or less, depending upon the type of computer. Other uses for switch mode regulators relate to the control of motors such as computer printer motors that are provided in printers such as ink jet printers. In such instances, the printer motors, such as paper transport and carriage or ink jet transport motors, need to be controlled and coordinated in a precise manner to ensure optimal printer performance and coordination of the respective printing and paper transport functions. 
     Switch mode power supplies can operate in a discontinuous or continuous mode. In instances where the power supply never operates in a discontinuous mode, clamping the gate and source of the output transistor to ground is acceptable. However, if the power supply can operate in a discontinuous mode, voltage can occur on the source pin as a result of inductor-capacitor oscillatory transients, known also as &#34;ringing&#34;. This &#34;ringing&#34; can cause tens of volts to appear on the output transistor source. As power discrete MOSFETs typically run only about 20V gate-source voltages, loads in excess of 20V can damage the gate of the MOSFET output driver. 
     While use of the ground clamped gate option of a gate-source voltage clamp can be used to limit the gate-source voltage on the output NMOS, this can pull the current to ground through the clamp, which can be undesirable. In the case of printer and computer system operation, such current draws are clearly undesirable. Accordingly, it would be desirable to provide a circuit which clamps the output transistor gate to the source, over an entire positive voltage range, without pulling a DC current, and while also maintaining all gate-source voltages within their specified voltage range limits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the invention have been chosen for purposes of illustration and description, and are shown with reference to the accompanying drawings, wherein: 
     FIG. 1 is a schematic diagram of a conventional switch mode regulator output circuit; 
     FIG. 2 is a block diagram of a wide range gate-source clamp in accordance with the present invention; 
     FIG. 3 is a schematic diagram of a switch mode regulator circuit in accordance with the present invention; 
     FIG. 4 is block diagram of an alternative wide range gate-source clamp in accordance wits the present invention; and 
     FIG. 5 is a schematic diagram of the circuit illustrated in FIG. 4. 
    
    
     SUMMARY OF THE INVENTION 
     A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory transients (&#34;ringing&#34;), along with its associated voltage spikes at the associated output transistor source, can be avoided. Such transients and their associated voltages are avoided by clamping the gate-source voltage on the circuit&#39;s output NMOS transistor over the entire positive operation voltage range. 
     In the circuit of the present invention a logic level input is converted by an associated pre-drive circuit to drive &#34;high&#34; and &#34;low&#34; voltage off-drive circuitry and on-drive circuitry to the output switch serving as a switching transistor for the switch mode power supply. The &#34;high&#34; and &#34;low&#34; voltage off-drive circuits are operable to force the output switch into an &#34;off&#34; state to render wide-range gate-source clamping of the output transistor. 
     Two voltage clamps are provided in the circuit and are operable to control the gate-source of the output transistor in accordance with the voltage level of a logic input signal to the circuit. One clamp is located within the low voltage &#34;off&#34; drive whereas the other clamp is located within the high voltage &#34;off&#34; drive. Threshold voltages can be selected for each of the voltage clamps to modify performance characteristics of the switch mode regulator. In a preferred aspect of the invention, an input voltage in excess of about 19V activates the high voltage &#34;off&#34; drive clamp, clamping the gate to source of the output transistor to render an &#34;off&#34; state. A voltage input between about 15V-19V activates both clamps. When the input is switched to a logic level low, both clamps are deactivated, thereby allowing for the output transistor to be turned &#34;on&#34;. 
     Two alternative circuit embodiments are provided. One embodiment (FIG. 3) optimizes control of &#34;off&#34; state current flow, at the nominal expense of die area. The other embodiment (FIG. 5) optimizes die area, but exhibits a small off-state current flow, which is usually insignificant in comparison to the inductor current flow of external circuitry with which the switch mode regulator is associated. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to the drawings, wherein like reference characters represent corresponding parts throughout the various views, and with particular reference to FIG. 1, there is illustrated the output stage of a conventional switch mode regulator circuit. The output stage includes a pre-drive or level shift 20 that is comprised of an inverter 22 and a parallel array of transistors 24, 26, 28, 30, 32 and 34. Transistors 24 and 26 are NMOS transistors, whereas transistors 28, 30, 32 and 34 are PMOS transistors. The gates of PMOS transistors 28 and 34 are shorted to a reference voltage, as shown in the drawing. 
     The pre-drive or level shift 20 is provided to switch the output transistor 40 between &#34;on&#34; and &#34;off&#34; conditions. Switching is accomplished through the operation of an &#34;on&#34; drive transistor 44 and an &#34;off&#34; drive transistor 48. An inductor-capacitor circuit 54, such as a Buck regulator 54, is connected between the output transistor 40 and the output node 56 and is operable to regulate current flow between the transistor 40 and the output node 56. The output transistor 40 is typically configured as an external FET, as it consumes considerable power. The drive transistors 44 &amp; 48 are operable in conjunction with the level shift 20 to maintain the output transistor 40 in its linear region. 
     FIG. 2 is a block diagram of a wide range gate-source clamp 60 in accordance with the present invention. The logic level input 62 is converted by a pre-drive circuit 20 to drive on-drive circuitry 44, high voltage off-drive circuitry 66 &amp; low voltage 68 off-drive circuitry (collectively represented by block 48), to an output switching transistor 40 for the switch-mode power supply output circuit. Output from the high and low voltage drives 66 &amp; 68, respectively, is directed to the source of the output transistor 40 through an inductor-capacitor bandpass filter in the form of a Buck regulator, indicated generally at 54, as discussed previously. The bandpass filter includes a diode 70 that is coupled to a capacitor 72. Output from the capacitor 72 is directed through an inductor coil 74 prior to the delivery to the output switch 40 to regulate voltage supplied to the output switches within prescribed levels typically zero to 40 V. The foregoing circuit is operable to actively clamp across the entire positive range of gate-source operation so as not to exceed a gate-source voltage maximum and not pull current from the inductor-capacitor circuit 54. 
     Further aspects of the gate-source clamp 60 illustrated in FIG. 2 are depicted in FIG. 3. The circuit pre-drive 20 comprises inverter 22 and a parallel array of transistors 24, 26, 28, 30, 32 and 34. Transistors 28-34 are PMOS transistors that are arranged in a parallel configuration such that the gates of transistors 28 and 34 are coupled to one another and shorted to a reference voltage, which is typically about 14-20V less than the typical V shift  value of about 34-35V. Transistors 24 and 26 are NMOS transistors. When transistor 26 is turned &#34;on&#34;, it pulls the gate of transistor 28 low. However, the voltage pull on the gate is restricted to the value of V ref , since as V source  approaches V gate , transistor 28 shuts &#34;off&#34;. As a result, the full gate voltage swing that would otherwise be available on transistor 28 is not experienced, thereby preventing gate-source damage. 
     The &#34;on&#34; drive 44 is comprised of PMOS transistor 80 and resistor 82. The transistor 80 is connected to the pre-drive 20 through PMOS transistors 28, 30, 32 and 34. As has been noted previously, the &#34;off&#34; drive 48 is comprised of high voltage 66 and low voltage 68 components. The high voltage component 66 is comprised of voltage source 84, NMOS transistors 86, 88 and 90 that are serially connected to the voltage source 84, and to the PMOS transistors 92 and 94. Resistors 96 and 98 are respectively coupled to transistors 86 and 88. Transistor 100 is connected to PMOS transistor 94. The &#34;off&#34; drive low voltage component 68 is comprised of NMOS transistors 110, 111 &amp; 114, and PMOS transistors 116 and 118. Resistors 120, 122 &amp; 124 are respectively associated with transistors 112, 114 &amp; 118. A reference supply voltage 128 powers the low voltage component 68. In a preferred aspect of the invention, the low voltage component 128 is a 19 volt reference, whereas high voltage reference 84 is a 15 volt reference. Input 130 serves as a logic level switch input that determines whether output switching transistor 132 is &#34;on&#34; or &#34;off&#34;. In instances where the logic level input 130 is high, low voltage transistor 110 is &#34;on&#34;, and high voltage transistors 86 and 88 are &#34;off&#34; which, in turn, turns &#34;on&#34; high voltage transistors 90 &amp; 92 and low voltage transistors 114 &amp; 116. High voltage transistor 94 and &#34;on&#34; drive transistor 80 are in an &#34;off&#34; state. Operation of the transistors in the foregoing manner serves to clamp the output switch transistor 132 gate to source and defines the transistor &#34;off&#34; state. 
     In instances where the voltage at node 136 is less than 15 volts, the gate-source clamp that is &#34;active&#34; is the &#34;off&#34; drive low voltage transistor 114. When the voltage exceeds 19 volts, the &#34;off&#34; drive high voltage transistor 92 serves as the &#34;active&#34; transistor, with a transition between 15 and 19 volts being where both gate-source clamps provided by the foregoing transistors 92 and 114 are &#34;active.&#34; The transistors 92 &amp; 114 are sized so that either transistor 92 or transistor 114 is individually capable of maintaining effective clamping. During clamping, virtually no DC current flows from node 136 to either V dd  supply or ground. In instances where input 130 is switched to a logic level &#34;low&#34;, transistors 92 &amp; 114 are turned &#34;off&#34;, and &#34;on&#34; drive transistor 80 is turned &#34;on&#34;, thereby turning &#34;on&#34; output switching transistor 132. 
     With reference to FIG. 4, there is depicted a block diagram for an alternative circuit embodiment of the present invention. As with the foregoing embodiment, a logic input 62 is converted by a pre-drive unit 20 to drive &#34;high&#34; and &#34;low&#34; voltage (not shown) &#34;off&#34; -drive circuitry 48 and &#34;on&#34; -drive circuitry 44 to the output switch 132 used as a switching transistor for the switch-mode power output circuit. A diode array 140 is interposed between the &#34;off&#34; -drive 48 &amp; &#34;on&#34; -drive 44 and the gate of the output transistor 132. As will be described below, the diode assembly serves as a gate-source clamp for the output switch 132. 
     With concurrent reference to FIGS. 4 and 5, the circuit pre-drive 20 is comprised of the same transistor and diode array as that described previously with respect to the embodiment depicted in FIG. 3. The circuit &#34;on&#34; -drive 44 is comprised of PMOS transistor 80 and resistor 82, as described previously. 
     The principal differences between the embodiments depicted in FIGS. 3 and 5 relate to the structure of the &#34;off&#34; drive 48. The &#34;off&#34; -drive 48 is comprised of NMOS transistor 150, back-gate connected PMOS transistor pair 154 &amp; 158, PMOS transistor 160, back-gate connected NMOS transistor pair 162 &amp; 166, and NMOS transistor 168. The drains of transistors 160 and 168 are connected to capacitor 170 and inverter 174. Output from the inverter 174 is directed to NAND gate 176, the output of which, in turn, is directed to NMOS transistor 180 through inverter 182. The drain of NMOS transistor 180 is connected to the drain of on-drive transistor 80 through resistor 82. As was mentioned previously, a gate-source clamp in the form of a diode array 140 is provided between the gate 186 and source 188 of the output switching transistor (not shown) and is comprised of a serial array of diodes 190, 192, 194 &amp; 196. 
     With further reference to FIGS. 4 and 5, input at node 200 serves as the logic level switch input which defines whether the output switching transistor 132 is in an &#34;on&#34; or &#34;off&#34; state. In instances where the input at node 200 is &#34;high&#34; NAND gate 176 is enabled, and NMOS transistor 26 is &#34;on&#34;, output from the on-drive transistor 80 is turned &#34;off&#34;. When transistor 168 is turned &#34;off&#34;, its drain voltage gradually rises due to charging of capacitor 170, during which time NMOS transistor 180 is temporarily turned &#34;on&#34;. Activation of transistor 180 turns &#34;off&#34; the output transistor gate 186, pulling the gate &#34;low&#34; at a fast rate. Once this initial transient has been completed, a controlled and small current of approximately 200μ amps is pulled from the gate 186 to the ground. In instances where the input at node 200 is switched to logic level &#34;low,&#34; the on-drive transistor 80 is turned &#34;on&#34; while the &#34;off&#34; -drive transistor is 180 is turn off. 
     The foregoing embodiments each have unique advantages. For example, the embodiment depicted in FIG. 3 is advantageous in instances where die area is not a critical design constraint, as this embodiment features a virtually non-existent &#34;off&#34; state current flow through the output transistor 132. In contrast, the embodiment depicted in FIG. 5 exhibits an appreciably reduced die footprint, but allows for a modest &#34;off&#34; state current through the output transistor. This &#34;off&#34; state current is typically insignificant in comparison to the inductor current of associated external circuitry. As such, the circuit design of FIG. 5 is believed to be suitable for the majority of commercial implementations. 
     Those skilled in the art to which the invention relates will appreciate that other substitutions and modifications can be made to the described embodiment, without departing from the spirit and scope of the invention as defined by the claims below.