Abstract:
A SEPIC converter having synchronous rectification, accommodating changes in the converter duty cycle, and the ringing conditions when the converter changes operation from a continuous mode to a discontinuous mode, and back. Conductive losses are significantly reduced.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention is generally related to power converters, and more particularly to SEPIC converters.  
       BACKGROUND OF THE INVENTION  
       [0002]     Technical issues in applying synchronous rectification to a SEPIC converter include accommodating a changing duty cycle and the ringing conditions when the converter changes operation from continuous mode to discontinuous mode and back. In particular, the frequency of the ring decreases as the load decreases, and there is a decrease in the duty cycle that affects the synchronous rectification.  
       SUMMARY OF THE INVENTION  
       [0003]     The present invention achieves technical advantages as a SEPIC converter having synchronous rectification. The converter accommodates changes in the converter duty cycle, and the ringing conditions when the converter changes operation from a continuous mode to a discontinuous mode, and back. Conductive losses are significantly reduced.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]      FIG. 1  is an electrical schematic of one embodiment of the invention;  
         [0005]      FIG. 2  is a waveform diagram showing voltages at various nodes of the schematic of  FIG. 1  with a light load; and  
         [0006]      FIG. 3  is a waveform diagram showing voltages at various nodes of the schematic of  FIG. 1  with a heavy load.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0007]     Referring to  FIG. 1 , there is shown a SEPIC converter  10  according to one embodiment of the invention. Inductor L 1 , indicator L 2 , capacitor C 1 , transistor Q 1 , transistor Q 3  and associated body diode, and capacitor C 5  form a classic SEPIC converter shown at  12 . As the load on the converter  10  decreases, the voltage at the junction J 1  of capacitor C 1 , inductor L 1  and the drain of transistor Q 3  tend to ring, as shown in the waveform diagram at  20  in  FIG. 2  for a light load. Under a light load condition at output V out , the first positive going pulse contains almost all of the transferable energy. The remaining pulses are low energy ringing.  
         [0008]     According to this embodiment of the present invention, amplifier U 1 , diode D 1 , resistor R 1 , diode D 2 , resistor R 2 , resistor R 6 , resistor R 10 , resistor R 11 , capacitor C 4  and transistor Q 4  form a dual slope integrator shown at  14 . The integrator  14  captures the gate on-time at control line  16 , and then uses this gate on-time to capture the energy in the inductance of inductor L 1 . If transistor Q 3  is turned on when the voltage at its drain is less than the voltage at its source, capacitor C 5  discharges through inductor L 1 . When the gate drive to transistors Q 1  transitions high, the output voltage at pin  1  of amplifier U 1  moves in a positive direction. The gate drive voltage for transistor Q 1  is also applied to the inverting input, pin  6 , of amplifier U 2 . This gate drive voltage is always higher than the output of amplifier U 1  due to the bias network formed by resistors R 7 , R 8 , R 9  and diode D 3 , which forces the output of amplifier U 2  to remain low while the non-inverting input to amplifier U 2  is going in a positive direction, thus, insuring the transistor Q 2  does not force transistor Q 3  into an on condition.  
         [0009]     The rising slope constant of integrator  14  is the product of capacitor C 4 , resistor R 2  and diode D 2 . When the gate drive voltage at control line  16  transitions low, the descending slope constant at the amplifier U 1  output is the product of capacitor C 4 , resistor R 1  and diode D 1 . It is at this time that the voltage at the non-inverting input to amplifier U 2 , pin  7 , is higher than the voltage at the inverting input, pin  6 , of amplifier U 2 . This causes the output of amplifier U 2 , at pin  1 , to move to a positive level that consequently causes transistor Q 2  to conduct, thereby causing transistor Q 3  to conduct, thereby transferring the energy at inductor L 1  to the output capacitor C 5 . When the integrator  14  output, the output of amplifier U 1 , descends below the voltage level at the inverting input of amplifier U 2  the output of amplifier U 2  returns to a low level, thereby causing transistor Q 2 , and subsequently transistor Q 3 , to stop conducting.  
         [0010]     Resistors R 6 , R 10  and R 11  form a voltage divider such that integration of integrator  14  follows the gate drive voltage at  16 . The alternate paths for integrating “up” verses integrating “down” allow different timing for each direction of the integrator  14  to accommodate duty cycle, or timing, differences.  
         [0011]     Capacitor C 6  and resistor R 14  form a differentiation circuit, where the positive pulse created when the gate transitions high briefly turns on transistor Q 4  to eliminate integration wind up. Diode D 5  clips the negative going portion of the differentiated pulse.  
         [0012]     When circuit  10  operates at high load conditions, where the duty cycle at gate drive  16  is such that capacitor C 4  would never completely discharge and, as such, would eventually reach positive saturation keeping transistors Q 2  and Q 3  in a state of constant conduction, the non-inverting input to amplifiers U 2  is biased by transistor Q 4  to keep the output of circuit  10  low when the gate drive voltage is high. The non-inverting input to amplifier U 2  is also biased when the output of the integrator  14  has descended below the voltage level at the non-inverting input of amplifier U 2  when the gate drive voltage is low.  
         [0013]     In this manner, transistor Q 3  is advantageously controlled to conduct for a period equal to, or slightly less than, the “on” period required to transfer the output energy stored in inductor L 1  and eliminate reverse conduction through transistor Q 3  when the voltage at the junction of inductor L 1 , capacitor C 1 , and transistor Q 3 &#39;s drain is less then the voltage across capacitor C 5 . The arrangement of the forward biased body diode of transistor Q 3  provides a means of charging capacitor C 5  before the voltage across capacitor C 5  is sufficient to support the drive circuitry for transistors Q 2  and Q 3 , and advantageously avoids contending with the ripple voltage at the source of transistor Q 3 . Advantageously, in this manner, good Vgs across transistor Q 3  is maintained. In addition, any small amount of energy remaining in inductor L 1  during the ringing is captured.  
       EXAMPLE  
       [0014]     When using the circuit  10  in a typical application, such as a 100 Watt inverter, the output current, at an output voltage equal to 15 volts, is about 6.66 amps. Using 1.0 volt as a typical forward drop for power diodes, the losses are:  
         [0015]     6.66 (amps)*1.0(volt)*0.65 (Duty Cycle)=4.33 watts.  
         [0016]     Using a 75.0 volt Vdss, 0.0063Ω Rdson MOSFET transistor, the power losses are:  
         [0017]     (6.66) 2  amps*0.011Ω (Rdson hot)*0.65 (Duty cycle)=0.317 watts.  
         [0018]     Use of the circuit  10  realizes a 21 times reduction in conductive losses. In addition, switching losses are minimized with the body diode oriented in the direction shown. The maximum voltage across the body diode is 1.0 volts so the transistor Q 3  switches when the Vds is at a minimum.  
         [0019]     6.66 (amps)*1.0 (volt)*25 nsec*50,000 Hz*2=0.02 watts.  
         [0020]     Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.