Abstract:
Conventional C2 coding and interleaving for multi-track data tape in LTO-¾ do not support recording data onto a number of concurrent tracks which is not a power of two. Higher-rate longer C2 codes, which do not degrade error rate performance, are provided. An adjustable format and interleaving scheme accommodates future tape drives in which the number of concurrent tracks is not necessarily a power of two. A data set is segmented into a plurality of unencoded subdata sets and parity bytes are generated for each row and column. The parameters of the C2 code include N 2  as the least common multiple of the number of possible tracks to which codeword objects are to be written. COs are formed from N 2  C1 codewords, mapped onto a logical data track according to information within headers of the CO and modulation encoded into synchronized COs which are written to the tape.

Description:
RELATED APPLICATION DATA 
       [0001]    The present application is related to commonly-assigned and co-pending U.S. application Ser. No. ______ [IBM Docket TUC920070253US1], entitled REWRITE-EFFICIENT ECC/INTERLEAVING FOR MULTI-TRACK RECORDING ON MAGNETIC TAPE, and ______ [IBM Docket TUC920070254US1], entitled REWRITING CODEWORD OBJECTS TO MAGNETIC DATA TAPE UPON DETECTION OF AN ERROR, both filed on the same date as the present application, which related applications are hereby incorporated herein by reference in their entireties. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates generally to formatting data to be recorded onto magnetic tape and, in particular, to an adjustable ECC format and interleaving process to accommodate tape drives having a multiple of eight transducers/sensors per head to read and write from/to a multiple of eight number of tracks simultaneously. 
       BACKGROUND ART 
       [0003]    The Linear Tape Open (LTO) formats Generations 3 and 4 use error-correcting codes (ECC), which are based on a 2-dimensional product code. The C1-code is arranged along the rows of the 2-dimensional array. It is an even/odd interleaved Reed-Solomon (RS) code of length  240  giving rise to a row of length  480 . The C2-code is arranged along the columns of the array. It is a RS-code of length  64  and dimension  54 . The codewords are 2-dimensional arrays of size 64×480 and they are called subdata sets in the LTO standard. It is anticipated that future generation of drives will write on more than 16 tracks simultaneously. However, all current generations of LTO formats (Gen-1 to Gen-4) are based on the above C2 coding scheme which, together with its associated interleaving, cannot accommodate future tape-drive systems that will support heads with 16, 24, 32 or 48 (or other multiple of eight) transducers/sensors per head to read/write 16, 24, 32 or 48 (or other multiple of eight) concurrent tracks, respectively. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention provides higher-rate and longer C2 codes, which do not degrade error rate performance. The code rate associated with these C2 codes is greater than the LTO-¾ C2 code rate  54 / 64  and the codeword length is greater than the LTO-¾ C2 codeword length  64 . In particular, the present invention provides a C2 code with rate K 2 /N 2 =84/96 and codeword length N 2 =96 and a corresponding encoder. 
         [0005]    More specifically, the present invention provides methods, apparatus and computer program product for writing data to multi-track tape. In one embodiment, a method comprises receiving a stream of user data symbols, the stream comprising a data set and segmenting the data set into a plurality S of unencoded subdata sets, each subdata set comprising an array having K2 rows and K1 columns. For each unencoded subdata set, N1−K1 C1-parity bytes are generated for each row of a subdata set which are appended to the end of the row to form an encoded C1 codeword having a length N1. Similarly, for each unencoded subdata set, N2−K2 C2-parity bytes are generated for each column of the subdata set which are appended to the end of the column to form an encoded C2 codeword having a length N2, whereby an encoded subdata set is generated having N2 C1 codewords. From the S encoded data subsets, a plurality (S×N2)/2 codeword objects (COs) are formed, each comprising a first header, a first C1 codeword, a second header and a second C1 codeword. Each CO is mapped onto a logical data track according to information within the headers of the CO and modulation encoded into synchronized COs that contain various sync patterns in addition to modulation encoded COs. T synchronized COs are then written simultaneously to the tape, where T equals the number of concurrent active tracks on the tape. 
         [0006]    In another embodiment, a data storage tape device comprises a host interface through which a stream of user data symbols comprising a data set is received and a segmenting module operable to segment the data set into a plurality S of unencoded subdata sets, each subdata set comprising an array having K2 rows and K1 columns. A C1 encoder is operable to generate N1−K1 C1 parity bytes for each row of a subdata set and append the C1 parity bytes to the end of the row to form an encoded C1 codeword having a length N1 and a C2 encoder is operable to generate N2−K2 C2 parity bytes for each column of the subdata set and append the C2 parity bytes to the end of the column to form an encoded C2 codeword having a length N2, whereby an encoded subdata set is generated having N2 C1 codewords. A codeword object formatter is operable to form a plurality (S×N2)/2 codeword objects (COs) from the S encoded data subsets, each CO comprising a first header, a first C1 codeword, a second header and a second C1 codeword. A codeword object interleaver is operable to map each CO onto a logical data track according to information within the headers of the CO. A modulation encoder is operable to encode the COs into synchronized COs that contain various sync patterns in addition to modulation encoded COs. A write channel, including a write head, is operable to write T synchronized COs simultaneously to the tape, where T equals the number of concurrent active tracks on the tape. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a block diagram of a magnetic tape drive with which the present invention may be implemented; 
           [0008]      FIG. 2  is a schematic representation of an encoded data set, including interleaved C1 and C2 ECC; 
           [0009]      FIG. 3  is a block diagram of components of the present invention used to form data sets from a stream of user data symbols; 
           [0010]      FIGS. 4A and 4B  are schematic representations of unencoded and encoded subdata sets, respectively; 
           [0011]      FIG. 5  illustrates a codeword object (CO) of the present invention; 
           [0012]      FIG. 6  is a logic diagram of a C2-encoder of the present invention for a [96, 84, 13]-RS code; 
           [0013]      FIG. 7  illustrates an alternative CO of the present invention; 
           [0014]      FIG. 8  illustrates an example of a distribution of subdata sets along 24 tracks of recording media in accordance with the present invention; 
           [0015]      FIG. 9  illustrates a synchronized CO of the present invention; and 
           [0016]      FIG. 10  illustrates an alternative synchronized CO of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0017]    Some of the functional units described in this specification have been labeled as modules in order to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like. Modules may also be implemented in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. A module of executable code could be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs and across several memory devices. 
         [0018]    Furthermore, the described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of programming, software modules, hardware modules, hardware circuits, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. 
         [0019]      FIG. 1  is a high level block diagram of a data tape drive  100  in which the present invention may be incorporated. Data to be recorded is transmitted from a host (not shown) to the drive  100  through a host interface  102 . The data undergoes a first encoding in a C1 encoder  104  and passed to a DRAM buffer controller  106 . The C1-encoded data undergoes a second encoding in a C2 encoder  108  and is stored in a DRAM buffer  110 . The data is subsequently stored in an SRAM buffer  112  and formatted in a formatter  114 . Formatted data is sent to a write channel and then to a write head  118  which records the data onto the tape  120 . 
         [0020]    When the data is read back from the tape  120 , a read head  122  detects the data and passes it to a read channel. The data is then processed in a de-formatter  126  and COs are verified in a verifier  128 . The data is then decoded and, ultimately, sent to the requesting host. 
         [0021]    The Linear Tape Open (LTO) format is based on the concept of data sets (the smallest unit written to tape) and subdata sets. A data set contains two types of data: user data and administrative information about the data set, the latter being in a Data Set Information Table (DSIT). All data is protected by an error correction code (ECC) to minimize data loss due to errors or defects. A data set comprises a number of subdata sets, each containing data arranged in rows. A subdata set row may contain user data or contain the DSIT. As illustrated in  FIG. 2 , each row consists of two interleaved byte sequences. A first level ECC (C1 ECC) is computed separately for the even bytes and for the odd bytes for each row. The resulting C1 ECC even and odd parity bytes are appended to the corresponding row, also in an interleaved fashion. The ECC protected row is the Codeword Pair (CWP). The even bytes form the even C1 Codeword while the odd bytes form the odd C1 Codeword. A second level ECC (C2 ECC) is computed for each column and the resulting C2 ECC parity bytes are appended to the corresponding columns. The ECC protected column is a C2 Codeword. 
         [0022]    The subdata set, when so protected by C1 and C2 ECC, is the smallest ECC-protected unit written to tape. Each subdata set is independent with respect to ECC; that is, errors in a subdata set affect only that subdata set. The power of any ECC algorithm depends upon the number of parity bytes and is stated in terms of its correction capability. For a given number of N1−K1 C1-parity bytes computed for a C1 codeword, up to floor((N1−K1)/4) errors may be corrected in each of the two interleaves of that codeword, where floor(x) denotes the integer part of the real number x. And, for a given number of N2−K2 C2-parity bytes computed for a C2 codeword, up to floor((N2−K2)/2) errors or N2−K2 erasures may be corrected in that C2 Codeword. 
         [0023]    It will be appreciated that multiple errors in the same subdata set can overwhelm the ability of the C1 or the C2 correction power to the extent that an error occurs when the data is read. Errors may be caused by very small events such as small particles or small media defects. Errors may also be caused by larger events such as scratches, tracking errors or mechanical causes. 
         [0024]    To mitigate the possibility that a single large error will affect multiple Codewords in a single subdata set, some methods of writing place Codewords from each subdata set as far apart as possible along and across the tape surface. A single error would therefore have to affect multiple Codewords from the same subdata set before the ECC correction capability is overwhelmed. Spatial separation of Codewords from the same subdata set reduces the risk and is accomplished in the following manner for a multi-track recording format. For each track of a set of tracks being recorded simultaneously, a Codeword Quad (CQ) is formed by combining a Codeword Pair from one subdata set with a Codeword Pair from a different subdata set. The resulting CQ is written on one of the multiple recorded tracks. In like manner, CQs are formed for all remaining tracks by combining Codeword Pairs, all Codeword Pairs being from differing subdata sets. The group of CQs written simultaneously is called a CQ Set. 
         [0025]    As illustrated in the block diagram of  FIG. 3 , data sets of a specified fixed size are formed by segmentation of a stream of user data symbols in a data set segmentation module  302 . The data set is further partitioned into S unencoded subdata sets. The subdata set structure is matched to an ECC module  304 , which is based on a C1/C2 product code. The unencoded subdata sets comprise 2-dimensional arrays of bytes of size K 2 ×K 1 , where K 1  and K 2  are the dimensions of the C1 and C2 code, respectively ( FIG. 4A ). A C1-encoder  306  operates on rows and adds parity bytes in each row. A C2-encoder  308  operates on the C1-encoded columns and appends parity in each column. The resulting C1/C2-encoded subdata set is an N 2 ×N 1  array of bytes, where N 1  and N 2  are the lengths of the C1 and C2 code, respectively ( FIG. 4B ). It will be appreciated that, although in  FIG. 3  and in  FIG. 4  the C1 encoding is shown as being performed first followed by the C2 encoding, the resulting encoded subdata sets are the same regardless of whether C1 encoding is performed first followed by C2 encoding or whether C2 encoding is performed first followed by C1 encoding. 
         [0026]    In LTO-¾, S=64 subdata sets (or codewords) form a data set (DS), the C1 code has length N 1 =480 and the C2 code has length N 2 =64. The C1-codewords within a DS are fully determined by the subdata set (SDS) number (in the range from 0 to S- 1 ) and by the row number within the subdata set (codeword array). In LTO-¾, this assignment is called codeword pair designation. It is determined by the following expression: 
         [0000]        C 1-codeword_number=SDS_number+64×row_number, 
         [0000]    where SDS_number=0, 1, 2, . . . , S- 1  and row_number=0, 1, . . . , 63. For LTO-¾, the C1-codeword_number index takes values from 0 to 4095. 
         [0027]    A structure  500  as shown in  FIG. 5  is a Codeword Object (CO) structure and reflects the organization of the basic unit that includes C1-codewords and associated headers. 
         [0028]    From the ECC module  304 , a CO formatter  310  forms COs consisting of two 10-byte headers  502 ,  504  and of two C1-codewords  506 ,  508  out of the S×N 2 =4096 C1-codewords per DS. Thus, there are S×N 2 /2=2048 COs, which are numbered from 0 to 2047. The CO structure  500  with index CO_number contains the two C1-codewords with indices C1-codeword_number that are related as follows. The indices C1-codeword_number_ 0  and C1-codeword_number_ 1  of the first and second C1-codewords, respectively, are given by 
         [0000]        C 1-codeword_number — 0=2×CO_number 
         [0000]        C 1-codeword_number — 1=2×CO_number+1. 
         [0029]    According to a first embodiment of the present invention, the C2-code generated by the C2 encoder  308  is a Reed-Solomon (RS) code of length N 2 =96 over the Galois field GF(256). The Galois field GF(2 8 ) is defined by the primitive polynomial P(z)=z 8 +z 4 +z 3 +z 2 +1 and the primitive element in GF(2 8 )=GF(2)[z]/(z 8 +z 4 +z 3 +z 2 +1) is: 
         [0000]      α=(0 0 0 0 0 0 1 0)= z (modulo  z   8   +z   4   +z   3   +z   2 +1). 
         [0000]    Note that α 255 =1. The generator polynomials for the C2-codes are chosen to have as few different coefficients as possible, which helps reduce the complexity of encoders and decoders. In particular, the generator polynomial for the [N 2 =96, K 2 =84, d min =13] RS-code is given by: 
         [0000]    
       
         
           
             
               
                 
                   
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                         11 
                       
                     
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                         209 
                       
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                         α 
                         80 
                       
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                         32 
                       
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                         5 
                       
                     
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                         99 
                       
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                         4 
                       
                     
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                         209 
                       
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                         3 
                       
                     
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                         32 
                       
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                         x 
                         2 
                       
                     
                     + 
                     
                       
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                         224 
                       
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                       x 
                     
                     + 
                     1. 
                   
                 
               
             
           
         
       
     
         [0030]    The encoding by the C2 encoder  308  is performed by a linear feedback shift register (LFSR)  600  as shown in  FIG. 6 . In the example illustrated, the LFSR  600  includes 12 registers R 0  to R 11  ( 602 A- 602 L) and 11 multipliers  604 A- 604 K whose feedback coefficients α c  are given by the generator polynomial of the [96,84,13]-RS code. The initial state of the LFSR  600  is the all-zero state. The N 2 −K 2 =12 parity bytes of an RS codeword are obtained by clocking all the systematic K 2 =84 data bytes through the LFSR, multiplying them in the respective multipliers  604 A- 604 L, adding  606 A- 606 K the results to the respective register outputs and reading out registers R 0  to R 11  ( 602 A- 602 L). In an actual implementation, the number of multipliers may be reduced by “reusing” multipliers whose coefficients are duplicated. For example, although illustrated as separate multipliers, multipliers  604 A and  604 K, having the common coefficient α 224 , may be implemented as a single multiplier, multipliers  604 B,  604 E,  604 G and  604 J, having the common coefficient α 32 , may be implemented as a single multiplier, etc. Thus, the LFSR  600  may be more efficiently implemented with five multipliers instead of 11. Moreover, the number n of registers, the number n of adders and the number n−1 of multipliers may be greater than or less than the numbers illustrated in  FIG. 6  to accommodate different codes. 
         [0031]    Additional generator polynomials may also be defined. A generator polynomial for a [128,112,17] code is given by: 
         [0000]    
       
         
           
             
               
                 
                   
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                         240 
                       
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                         15 
                       
                     
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                         14 
                       
                     
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                         13 
                       
                     
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                         12 
                       
                     
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                         192 
                       
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                         116 
                       
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                         9 
                       
                     
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                         198 
                       
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                         8 
                       
                     
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                         192 
                       
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                         5 
                       
                     
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                         79 
                       
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                         212 
                       
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                         89 
                       
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                         240 
                       
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                     + 
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         [0032]    And, a generator polynomial for a [192,168,25] RS code is given by: 
         [0000]    
       
         
           
             
               
                 
                   
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                         14 
                       
                     
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                         12 
                       
                     
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                         x 
                         11 
                       
                     
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                         65 
                       
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                         x 
                         10 
                       
                     
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                         183 
                       
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                         9 
                       
                     
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                         34 
                       
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                         8 
                       
                     
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                         43 
                       
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                         7 
                       
                     
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                         48 
                       
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                         6 
                       
                     
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                         26 
                       
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                         ++ 
                       
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                         65 
                       
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                         x 
                         10 
                       
                     
                     + 
                     
                       
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                         2 
                       
                        
                       
                         x 
                         4 
                       
                     
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                         228 
                       
                        
                       
                         x 
                         3 
                       
                     
                     + 
                     
                       
                         α 
                         98 
                       
                        
                       
                         x 
                         2 
                       
                     
                     + 
                   
                 
               
             
             
               
                 
                     
                    
                   
                     
                       
                         α 
                         90 
                       
                        
                       x 
                     
                     + 
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         [0033]    It is assumed that the C1-codewords are pre-defined and, thus, their length N 1  is given. That is, the C1-code may be a 2-way interleaved RS-code of length  480  as in LTO-4, as illustrated in  FIG. 5 , or may be a 4-way interleaved RS-code of length  960 , as illustrated in  FIG. 7 . The format of the present invention includes subdata sets, which are arrays of dimension N 2 ×N 1 , where N 2 =96, and a predetermined number S of subdata sets forms a data set. The codeword number is determined by the expression: 
         [0000]        C 1-codeword_number=SDS_number+S×row_number, 
         [0000]      where SDS_number=0, 1, 2 , . . . , S -1 and row_number=0, 1 , . . . , N   2 −1. 
         [0034]    The CO structures are mapped onto the logical tracks (16 for LTO-¾) according to the information in the header, viz., C1-codeword_number index. This mapping will be referred to as CO-interleaving and is performed in a CO interleaver  312  ( FIG. 3 ). In LTO-4, the CO structures is referred to as a codeword quad because it consists of four RS codewords. In this case, there are S=64 subdata sets per DS. 
         [0035]    An alternative CO structure is shown in  FIG. 7 , where one C1-codeword consists of a 4-way interleaved RS-code. This CO structure is referred to as a codeword octet. In this case, the DS is partitioned into S=32 subdata sets. 
         [0036]    Again, each CO consists of two 10-byte headers and two C1-codewords out of the S×N 2  C1-codewords per DS and, thus, there are S×N 2 /2 COs, which are numbered in consecutive order starting from 0. The CO structure with index CO_number contains the two C1-codewords with indices C1-codeword_number that are related as follows. The indices C1-codeword_number_ 0  and C1-codeword_number_ 1  of the first and second C1-codewords, respectively, are given by: 
         [0000]        C 1-codeword_number — 0=2×CO_number 
         [0000]        C 1-codeword_number — 1=2×CO_number+1. 
         [0000]    Therefore, two C1-codewords in an CO are taken from two SDSs with consecutive SDS_number indices. 
         [0037]    The COs are written simultaneously onto the tape in batches of T COs, where T is the number of concurrent active tracks. The CO-interleaver  312  assigns a logical track number t in the range 0, 1, . . . , T- 1  to each CO of the DS. Thus, the S×N 2 /2 COs of a DS are grouped into batches of T COs based on their consecutive CO_number indices and then these batches are written onto the T active tracks. Thereby, one CO of each batch is written onto one of the T tracks in a one-to-one fashion, which is determined by the CO-interleaver  312 . More specifically, the CO-interleaver  312  maps a CO structure with index n=CO_number to logical track number t based on the formula: 
         [0000]      t≡5 floor(2n/S)+n (mod T)   [Expression 1] 
         [0000]    where floor(x) denotes the integer part of the real number x and (mod T) denotes the modulo operation with modulus T in which the remainder is in the range 0, 1, . . . , T- 1 . For N 2 =96, one can accommodate T=16, 24, 32, 48 or 96 parallel tracks. In  FIG. 8 , the result of the CO-interleaving is illustrated for a DS with S=96 SDSs by showing the data set layout of two pairs of SDSs along T=24 tracks. The 96 dots correspond to the 96 COs of the SDSs with SDS_number  0  and  1 ; the 96 crosses correspond to the 96 COs of the SDSs with SDS_number  2  and  3 . It can be seen that the 96 C1-codewords within a SDS are uniformly distributed along and across the T=24 tracks. 
         [0038]    The approach described in the embodiment described above is general and may be applied also to C2-codes of length N 2 =128 and N 2 =192. In both cases, the CO-interleaving Expression 1 is valid. For N 2 =128, one can accommodate T=16, 32, 64 or 128 parallel tracks and, for N 2 =192, there can be T=16, 24, 32, 48, 64, 96, or 192 tracks. When designing a C2-code of the present invention, a determination would first be made of the number of possible parallel tracks T 1 , T 2 , . . . , T m  to which COs are to be written. N 2  may then be calculated as the least common multiple of numbers T 1 , T 2 , . . . , T m . For example, if it is desired to accommodate T=16, 24, 32, 48 or 96 parallel tracks, the least common multiplier is N 2 =96. Similarly, if it is desired to accommodate T=16, 32, 64 or 128 parallel tracks, the least common multiplier is N 2 =128. And, if it is desired to accommodate T=T=16, 24, 32, 48, 64, 96, or 192 parallel tracks, the least common multiplier is N 2 =192. It will be appreciated that the foregoing are provided as examples and that the present invention is not limited to any particular value of N 2  or to any particular number T of parallel tracks to which the COs are to be written. 
         [0039]    After CO-interleaving and before writing them onto tape, the COs are modulation encoded and transformed into synchronized codeword object (SCO) structures by inserting VFO, forward, resync and reverse sync fields.  FIGS. 9 and 10  illustrate alternative COs. In LTO-4, the headers and codeword pairs are passed through a rate-16/17 RLL encoder resulting in RLL-encoded bit-sequences of length  85  and  4080 , respectively. More generally, the CO structures can be modulation encoded using an RLL-encoder of rate R H  for the header portion and an RLL-encoder of rate R for the C1-codewords ( FIG. 9 ). For the alternative CO structure of  FIG. 7 , the resulting SCO-structure is illustrated in  FIG. 10 , where the VFO, forward sync, re-sync and reverse sync fields have some suitable lengths L VFO , L FS , L RS , and L FS , respectively. 
         [0040]    The proposed interleaving scheme is designed to provide robustness against dead tracks and have an increased robustness against stripe errors (that is, errors across all tracks). The robustness of an ECC/CO-interleaving scheme against stripe errors depends on three factors: (i) the parameters [N 2 , K 2 , d min ] of the C2-code, (ii) the interleaving depth given by the number S of subdata sets (SDS) within each Data Set (DS), and (iii) the number T of parallel channels (tracks). In case of a stripe error, the decoder operates as follows. The C1-decoder detects that certain rows in a number of subdata sets are uncorrectable and provides erasure-flags of these rows to the C2-decoder. The C2-decoder performs erasure-decoding and can correct up to N 2 −K 2 −M erasures per subdata set while keeping a margin of M bytes to avoid miscorrections. If a stripe error along tape extends over no more than (S/2)×(N 2 −K 2 −M)/T SCOs, then there are no more than (S/2)×(N 2 −K 2 −M) COs which are affected by errors and these erroneous COs are evenly distributed by the inverse CO-interleaving map over the S/2 pairs of subdata sets of an affected DS. Thus, each subdata set will contain at most N 2 −K 2 −M erased rows, which can be corrected and, therefore, the maximum stripe error length (MSEL) in terms of SCO units is given by: 
         [0000]      MSEL= S ×( N   2   −K   2   −M )/(2 T ). 
         [0000]    The absolute length of the MSEL along the tape in [mm] depends on the length of the SCO in [mm]. 
         [0041]    The maximum number of dead tracks (MNDT) that can be tolerated in the absence of channel errors can be derived in a similar manner. Specifically, the formula: 
         [0000]      MNDT=floor(( N   2   −K   2 )/( N   2   /T )) 
         [0000]    may be used to compute the maximum number of dead tracks. 
         [0042]    Based on the synchronized codeword quad (SCQ), which is the SCO structure of LTO-4, TABLE 1 shows specific configurations of C2-code designs and properties with regard to maximum stripe error length and dead track support. In TABLE 1, an erasure-correction margin of M=2 was assumed. It should be emphasized that the CO-interleaving Expression 1 applies in all these cases. All C2-codes with N 2 &gt;64 have 3.7% improved format efficiency (FE) when compared to the C2-code in LTO-4 (see first row in TABLE 1). All of these long C2-codes have improved error rate performance that translates into a gain in linear density. The linear density gains in TABLE 1 were obtained from measurements in the lab using a semi-analytic approach. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Specific C2-Code Configurations for Codeword Quad-Based SCO-Structures 
               
             
          
           
               
                   
                   
                   
                   
                 Relative 
                 FE 
                 Lin. density 
                 MSEL 
                   
               
               
                 N 2   
                 K 2   
                 Tracks T 
                 S 
                 DS size 
                 in % 
                 gain in % 
                 in SCQs 
                 Dead tracks 
               
               
                   
               
             
          
           
               
                 64 
                 54 
                 16 
                 64 
                 1X 
                 0 
                 0 
                 16 
                 2 
               
               
                 128 
                 112 
                 16 
                 32 
                 1X 
                 3.7 
                 6.5 
                 14 
                 2 
               
               
                 128 
                 112 
                 16 
                 64 
                 2X 
                 3.7 
                 6.5 
                 28 
                 2 
               
               
                 128 
                 112 
                 32 
                 64 
                 2X 
                 3.7 
                 6.5 
                 14 
                 4 
               
               
                 128 
                 112 
                 32 
                 128 
                 4X 
                 3.7 
                 6.5 
                 28 
                 4 
               
               
                 96 
                 84 
                 16 
                 64 
                   1.5X 
                 3.7 
                 4.0 
                 20 
                 2 
               
               
                 96 
                 84 
                 24 
                 96 
                   2.25X 
                 3.7 
                 4.0 
                 20 
                 3 
               
               
                 96 
                 84 
                 32 
                 128 
                 3X 
                 3.7 
                 4.0 
                 20 
                 4 
               
               
                 192 
                 168 
                 16 
                 32 
                   1.5X 
                 3.7 
                 8.5 
                 22 
                 2 
               
               
                 192 
                 168 
                 24 
                 48 
                   2.25X 
                 3.7 
                 8.5 
                 22 
                 3 
               
               
                 192 
                 168 
                 32 
                 64 
                 3X 
                 3.7 
                 8.5 
                 22 
                 4 
               
               
                   
               
             
          
         
       
     
         [0043]    In TABLES 2 and 3, the results are summarized for the two described embodiments for T=16 parallel tracks and SCO-structures, which are based on codeword quads and octets, respectively. The length of a codeword octet in [mm] is roughly twice as long as that of a codeword quad. Thus, for the ECC-1 scheme, the maximum stripe error length of 20 SCQs is comparable to 10 SCOs in TABLES 2 and 3, respectively. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Proposed C2-Code Configurations for Codeword Quad-Based 
               
               
                 SCO-Structures and T = 16 Tracks 
               
             
          
           
               
                   
                   
                   
                   
                   
                   
                 Lin. 
                   
                   
               
               
                   
                   
                   
                   
                 Relative 
                 FE 
                 density 
                 MSEL 
                 Dead 
               
               
                 Code 
                 N 2   
                 K 2   
                 S 
                 DS size 
                 in % 
                 gain in % 
                 in SCQs 
                 tracks 
               
               
                   
               
             
          
           
               
                 LTO-4 
                 64 
                 54 
                 64 
                 1X   
                 0 
                 0 
                 16 
                 2 
               
               
                 ECC-1 
                 96 
                 84 
                 64 
                 1.5X 
                 3.7 
                 4.0 
                 20 
                 2 
               
               
                 ECC-2 
                 192 
                 168 
                 32 
                 1.5X 
                 3.7 
                 8.5 
                 22 
                 2 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
             
             
               
                   
               
               
                 Proposed C2-Code Configurations for Codeword Octet-Based 
               
               
                 SCO-Structures and T = 16 Tracks. 
               
             
          
           
               
                   
                   
                   
                   
                   
                   
                 Lin. 
                   
                   
               
               
                   
                   
                   
                   
                 Relative 
                 FE 
                 density 
                 MSEL 
                 Dead 
               
               
                 Code 
                 N 2   
                 K 2   
                 S 
                 DS size 
                 in % 
                 gain in % 
                 in SCOs 
                 tracks 
               
               
                   
               
             
          
           
               
                 ECC-1 
                 96 
                 84 
                 32 
                 1.5X 
                 3.7 
                 4.0 
                 10 
                 2 
               
               
                 ECC-2 
                 192 
                 168 
                 32 
                 3X   
                 3.7 
                 8.5 
                 22 
                 2 
               
               
                   
               
             
          
         
       
     
         [0044]    It is important to note that while the present invention has been described in the context of a fully functioning data processing system, those of ordinary skill in the art will appreciate that the processes of the present invention are capable of being distributed in the form of a computer readable medium of instructions and a variety of forms and that the present invention applies regardless of the particular type of signal bearing media actually used to carry out the distribution. Examples of computer readable storage media include recordable-type media such as a floppy disk, a hard disk drive, a RAM, and CD-ROMs. 
         [0045]    The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Moreover, although described above with respect to methods and systems, the need in the art may also be met with a computer program product containing instructions for writing data to a multi-track data tape medium or a method for deploying computing infrastructure comprising integrating computer readable code into a computing system for writing data to a multi-track data tape medium.