Abstract:
A shift register, a driving circuit and a display device using the same are disclosed. The shift register includes a 1 st  and a 2 nd  rectifying elements and 1 st ˜4 th  transistors. 1 st  source/drains of the 1 st ˜3 rd  transistors receive a common voltage respectively. The gates of the 1 st  and 3 rd  transistors and a 2 nd  source/drain of the 2 nd  transistor are coupled to a 2 nd  terminal of the 2 nd  rectifying element. The gates of the 2 nd  and 4 th  transistors and a 2 nd  source/drain of the 1 st  transistor are coupled to a 2 nd  terminal of the 1 st  rectifying element. A 1 st  source/drain of the 4 th  transistor is coupled to a 2 nd  source/drain of the 3 rd  transistor. The 1 st  terminals of the 1 st  and 2 nd  rectifying elements respectively receive input signals and a 1 st  clock signal. A 2 nd  source/drain of the 4 th  transistor receives a 2 nd  clock signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims the priority benefit of Taiwan application serial no. 95145120, filed on Dec. 5, 2006. All disclosure of the Taiwan application is incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a shift register; in particular, to a shift register for reducing the number of clock control signals thereof, and a driving circuit and a display device using the same. 
   2. Description of Related Art 
   Nowadays the thin-film transistor (TFT) made from amorphous silicon (a-Si:H) is used in most liquid crystal displays (LCD). In the design of the large LCD panel, a driving integrated circuit is designed to surround the LCD panel. The gate voltage of the TFT is used for controlling the TFT to be on or off, wherein the corresponding pixel is driven by the source of a driving signal at proper timing through the on/off state of the TFT. As a result, each of the display pixels can function independently without being influenced by other display pixels. 
   The driving circuits in an LCD, like a scan driving circuit and a data driving circuit, are mainly coordinated with a clock control signal to output in order the scan driving signal and the data driving signal to the next stage shift register within a fixed duty cycle so as to drive each of the scan lines and the data lines in the LCD panel. 
     FIG. 1A  is a circuit diagram of a shift register employed by a conventional N-type metal-oxide-semiconductor field-effect transistor (MOSFET).  FIG. 1B  is a timing diagram of the circuit operation of  FIG. 1A . Referring to  FIGS. 1A and 1B , within the period of T 1 , when an input signal G n−1  is a logic-high voltage, transistors N 1  and N 7 -N 8  are turned on such that the voltage of a node “P 2 ” is pulled down to a logic-low voltage, that is, transistors N 5 -N 6  and N 10  are turned off. Meanwhile, a clock signal CLK 1  inputs a logic-high voltage from a node “c 1 ” such that a transistor N 2  is turned on and the voltage of a node “P 1 ” is pulled up to conduct a transistor N 9 . Next, within the period of T 2 , a clock signal CLK 2  inputs a logic-high voltage from a node “c 2 ” to change an output signal G n  into a logic-high voltage and transmit the logic-high voltage to the next stage device. 
   Within the period of T 3 , the input signal G n−1  is a logic-low voltage and the transistors N 1  and N 7 -N 8  are turned off. Meanwhile, the clock signal CLK 1  inputs a logic-low voltage from the node “c 1 ” so that the transistor N 2  is turned off. The voltage of the node “P 1 ” is sufficient to turn on the transistor N 9 . The output signal G n  changes into a logic-low voltage because of the logic-low voltage inputted from the node “c 2 ” by the clock signal CLK 2  and is transmitted to the next stage device. Within the period of T 4 , a clock signal CLK 3  inputs a logic-high voltage from a node “c 3 ” to turn on transistors N 3 -N 4 . The voltage of the node “P 2 ” is pulled up to turn on the transistors N 5 -N 6  and N 10 , and the voltages of the node “P 1 ” and the output signal G n  are pulled down to logic-low voltages such that the resetting operation of the shift register is completed. 
   The foregoing single shift register requires 3 sets of clock signals CLK 1 -CLK 3  to complete operation within the periods of T 1 -T 4 . The circuit consisted of a plurality of shift registers requires at least 4 sets of clock signals CLK 1 -CLK 4  for controlling.  FIG. 2A  is a circuit block diagram of a conventional scan driving circuit consisted of a plurality of shift registers of different stages.  FIG. 2B  is a timing diagram of the circuit operation of  FIG. 2A . Referring to  FIGS. 2A and 2B , a first stage shift register  201  receives a scan driving signal SP. The first shift register  201  utilizes clock signals CLK 1 , CLK 2  and CLK 3  to output a signal G 1  during the period of T 2  through the input nodes “c 1 ”, “c 2 ” and “c 3 ” (the same as the circuit operation of a single shift register  100  of  FIG. 1A ). 
   A second stage shift register  202  receives the output signal G 1  from the last stage shift register  201  and utilizes clock signals CLK 2 , CLK 4  and CLK 1  to output a signal G 2  within the period of T 3  through the clock input nodes “c 1 ”, “c 2 ” and “c 3 ”. A third stage shift register  203  receives the output signal G 2  from the last stage shift register  202  and utilizes clock signals CLK 4 , CLK 3  and CLK 2  to output a signal G 3  within the period of T 4  through the clock input nodes “c 1 ”, “c 2 ” and “c 3 ”. A fourth stage shift register  204  receives the output signal G 3  from the last stage shift register  203  and utilizes clock signals CLK 3 , CLK 1  and CLK 4  to output a signal G 4  within the period of T 5  through the clock input nodes “c 1 ”, “c 2 ” and “c 3 ”. 
   In the prior art, a multiple-stage shift register requires 4 sets of clock control signals to output one type of signal and cannot generate other complementary output signals to drive other pixel circuits. For instance, the driving circuit of an LCD with an organic light emitting diode (OLED) has to be supplied with additional control signals in order to complete the operation of driving the OLED. Moreover, since a shift register operates by transmitting the output signal from the last stage shift register as its own input signal to the next stage shift register, if an output impedance of the shift register is too large, a mistake in the level of the output signal from the last stage shift register would occur because of the loading effect of the next stage shift register, and cause the circuit operation to function abnormally. Besides, the said situation also creates overlapping of the output signals from shift registers of different stages. If such shift registers that may cause output signal overlapping are used in the scan driving circuit, two scan lines may be opened during the same time period, and the frame display is therefore rendered abnormal. 
   Furthermore, for LCD panels of medium and small sizes, for instance, the display panels of the cellular phone and the personal digital assistant (PDA), the driving circuit is designed to be disposed on the glass substrate of the LCD panel. Hence, a thin-film transistor (TFT) made from low temperature polycrystalline silicon (LTPS) is required. However, the driving circuit disposed on the glass substrate of the LCD panel is probably to be limited by unsatisfactory characteristics of the transistor element, such as low mobility, shifting threshold voltage and large leakage current. Therefore, during designing the driving circuit on the LCD panel, the above problems have to be especially taken into consideration so as to select appropriate elements. Generally speaking, during the process of manufacturing low temperature polycrystalline silicon, the P-type metal-oxide-semiconductor field effect transistor (MOSFET) is one of the elements whose characteristics possess better reliability. 
   SUMMARY OF THE INVENTION 
   A shift register is provided by the present invention. Only two sets of clock signals are required to control the output signals of the shift register. The number of the clock signals is thus reduced so as to further reduce the complexity and the area of the wiring in the hardware. 
   A driving circuit including a plurality of shift registers is further provided by the present invention. Only three sets of clock signals are required to control the operation of the driving circuit. The number of the clock signals is thus reduced so as to further reduce the complexity and the area of the wiring in the hardware. 
   The present invention is also directed to provide a display device including at least one scan driving circuit and a data driving circuit. The driving circuits are consisted of a plurality of shift registers operating with driving signals and three sets of clock signals to control each of the scan lines and data lines in the display device to achieve the purpose of displaying. 
   A shift register is provided by the present invention, and which includes a first to a second rectifying elements and a first to a fourth transistors. A first terminal of the first rectifying element is coupled to a first input node. A first terminal of the second rectifying element is coupled to a second input node. A first source/drain of the first transistor is coupled to a common voltage, wherein a gate of the first transistor is coupled to a second terminal of the second rectifying element, and a second source/drain of the first transistor is coupled to a second terminal of the first rectifying element. A first source/drain of the second transistor is coupled to the common voltage, wherein a gate of the second transistor is coupled to the second terminal of the first rectifying element, and a second source/drain of the second transistor is coupled to the second terminal of the second rectifying element. A first source/drain of the third transistor is coupled to the common voltage, wherein a gate of the third transistor is coupled to the second terminal of the second rectifying element, and a second source/drain is coupled to a first output node. A first source/drain of the fourth transistor is coupled to the first output node, wherein a gate of the fourth transistor is coupled to the second terminal of the first rectifying element, and a second source/drain of the fourth transistor is coupled to a third input node. 
   A driving circuit is provided by the present invention, and which includes a plurality of shift registers. Each of the shift registers includes a first to a second rectifying elements and a first to a fourth transistors, wherein all of the elements within the each shift register are coupled in the same way as described in the aforementioned shift register. A first input node of an (i+1) th  shift register is coupled to a first output node of an i th  shift register, and the (i+1) th  shift register utilizes a first to a third clock signals to control the output of the driving circuit, where i is a non-zero natural number. 
   A display device is provided by the present invention, and which at least includes a scan driving circuit and a data driving circuit. Those driving circuits include a plurality of shift registers, wherein each of the shift registers includes a first to a second rectifying elements and a first to a fourth transistors, wherein all of the elements within the each shift register are coupled in the same way as described in the aforementioned shift register. A first input node of an (i+1) th  shift register is coupled to a first output node of an i th  shift register, and the (i+1) th  shift register utilizes a first to a third clock signals to control the output of the driving circuit, where i is a non-zero natural number. 
   In one embodiment of the present invention, in the said driving circuit or display device, when i=3k+1, a second input node of the i th  shift register receives the first clock signal, and a third input node of the i th  shift register receives the second clock signal. When i=3k+2, the second input node of the i th  shift register receives the second clock signal, and the third input node of the i th  shift register receives the third clock signal. When i=3k, the second input node receives the third clock signal, and the third input node receives the first clock signal; where k is a natural number. 
   The said shift register, driving circuit or display device further includes a fifth to a sixth transistors in one embodiment of the invention. A first source/drain of the fifth transistor is coupled to a common voltage, wherein a gate of the fifth transistor is coupled to the second terminal of the second rectifying element, and a second source/drain of the fifth transistor is coupled to a second output node. A first source/drain of the sixth transistor is coupled to the second output node, wherein a gate of the sixth transistor is coupled to the second terminal of the first rectifying element, and a second source/drain of the sixth transistor is coupled to a third input node. 
   The said shift register, driving circuit and display device further includes an inverter in one embodiment of the invention. An input terminal of the inverter is coupled to the second output node, and an output terminal of the inverter is coupled to a third output node. 
   The inverter includes a seventh transistor and a third rectifying element in one embodiment of the invention. A first source/drain of the seventh transistor is coupled to a common voltage, wherein a gate of the seventh transistor is coupled to the second output node, and a second source/drain of the seventh transistor is coupled to the third output node. A first terminal of the third rectifying element is coupled to the second input node, and a second terminal of the third rectifying element is coupled to the third output node. 
   The said shift register, driving circuit and display device further includes an inverter in one embodiment of the invention. The input terminal of the inverter is coupled to the first output node, and the output terminal of the inverter is coupled to the third output node. 
   The inverter includes the seventh transistor and the third rectifying element in one embodiment of the invention. A first source/drain of the seventh transistor is coupled to a common voltage, wherein a gate of the seventh transistor is coupled to the first output node, and a second source/drain of the seventh transistor is coupled to the third output node. A first terminal of the third rectifying element is coupled to the second input node, and a second terminal of the third rectifying element is coupled to the third output node. 
   The said shift register, driving circuit and display device further includes an eighth transistor and a fourth rectifying element in one embodiment of the invention. A first source/drain of the eighth transistor is coupled to a common voltage, wherein a gate of the eighth transistor is coupled to the first input node, and a second source/drain of the eighth transistor is coupled to a fourth output node. A first terminal of the fourth rectifying element is coupled to the second input node, and a second terminal of the fourth rectifying element is coupled to the fourth output node. 
   The circuit design of the shift register in the present invention reduces the number of the clock control signals and further reduces the complexity and the area of the layout. The shift register can be further applied in general driving circuits to drive devices of different stages or in the scan driving circuit and the data driving circuit of the display device. Furthermore, the shift register provides appropriate output signals according to different designs of the driving pixel circuit in a display device. As regards the manufacturing techniques, the elements in the shift register of the invention may be selected according to the designer&#39;s needs or the characteristics of the elements. 
   In order to make the aforementioned and other objects, features and advantages of the present invention with more comprehensible, preferred embodiments accompanied with figures are described in detail below. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1A  is a circuit diagram of a shift register employed by a conventional N-type metal-oxide-semiconductor (MOS). 
       FIG. 1B  is a timing diagram of the circuit operation of  FIG. 1A . 
       FIG. 2A  is a circuit block diagram showing the connection of a conventional multi-staged shift register. 
       FIG. 2B  is a timing diagram of the circuit operation of  FIG. 2A . 
       FIG. 3  is a circuit block diagram of a display device according to one embodiment of the invention. 
       FIG. 4  is a circuit block diagram of the scan driving circuit according to the embodiment of  FIG. 3 . 
       FIG. 5A  is a circuit diagram of the shift register according to the embodiment of  FIG. 4 . 
       FIG. 5B  is a timing diagram of the circuit operation of  FIG. 5A . 
       FIG. 6A  is a circuit implementation diagram of shift registers  401 - 403  according to one embodiment of  FIG. 4 . 
       FIG. 6B  is a timing diagram of the circuit operation of  FIG. 6A . 
       FIG. 7  is a circuit block diagram of a conventional OLED pixel unit. 
       FIG. 8A  is another circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . 
       FIG. 8B  is a timing diagram of the circuit operation of  FIG. 8A . 
       FIG. 9A  is another circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . 
       FIG. 9B  is a timing diagram of the circuit operation of  FIG. 9A . 
       FIG. 10A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . 
       FIG. 10B  is a timing diagram of the circuit operation of  FIG. 1A . 
       FIG. 11A  is another circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . 
       FIG. 11B  is a timing diagram of the circuit operation of  FIG. 11A . 
       FIG. 12A  is another circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . 
       FIG. 12B  is a timing diagram of the circuit operation of  FIG. 12A . 
       FIG. 13A  is another circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . 
       FIG. 13B  is a timing diagram of the circuit operation of  FIG. 13A . 
       FIG. 14A  is another circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . 
       FIG. 14B  is a timing diagram of the circuit operation of  FIG. 14A . 
       FIG. 15A  is another circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . 
       FIG. 15B  is a timing diagram of the circuit operation of  FIG. 15A . 
       FIG. 16  is a timing diagram of the circuit operation of  FIG. 4 . 
   

   DESCRIPTION OF EMBODIMENTS 
     FIG. 3  is a circuit block diagram of a display device according to one embodiment of the invention. Referring to  FIG. 3 , the display device includes a display panel  301 , a timing controller  302 , a scan driving circuit  303  and a data driving circuit  304 . To facilitate explanation, it is assumed that the display device of the present embodiment is an LCD device, and the scan driving circuit  303  is utilized for describing the characteristic of the invention. 
     FIG. 4  is a circuit block diagram of the scan driving circuit  303  according to the embodiment of  FIG. 3 . Referring to  FIG. 4 , the scan driving circuit  303  includes a plurality of shift registers  401 - 403  (only three shift registers of different stages are shown herein as the example). A first stage shift register  401  receives a scan driving signal SP and is controlled by clock signals CLK 1 -CLK 3  to output the scan driving signal SP in order within a fixed duty cycle to different stage shift registers  402 ,  403  and so forth, so that each of the scan lines is opened in order. More details on the circuit and the circuit operation are to be followed hereunder. 
     FIG. 5A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIG. 5A , a shift register  500  is implemented by a P-type metal-oxide-semiconductor field effect transistor (MOSFET), wherein the shift register  500  includes transistors MP 1 -MP 4  and transistors DP 1 -DP 2 . For the convenience of explanation, in this circuit diagram, a common voltage VDD and a plurality of nodes are marked out. They are “I 1 ”, “a”, “b”, “O 1 ”, “Q” and “QB”. The common voltage VDD in the present embodiment may be a power source voltage. 
     FIG. 5B  is a timing diagram of the circuit operation of  FIG. 5A . Referring to  FIGS. 5A and 5B , within the period of T 1 , when a signal NEXT i−1  is a logic-low voltage, since the transistor DP 1  is diode-connected, the node “I 1 ” thereof where NEXT i−1  is received is equivalent to the cathode of the diode. As a result, the voltage of the node “Q” is pulled down to a logic-low voltage through the transistor DP 1  so as to turn on the transistors MP 2  and MP 4 . Since the transistor MP 2  is turned on, the voltage of the node “QB” is pulled up to a logic-high voltage such that the transistors MP 1  and MP 3  are turned off. Afterwards within the period of T 2 , the clock signal CLK 1  inputs a logic-low voltage from the node “b”. Since the transistor MP 4  is turned on, an output signal NEXT i  is changed into a logic-low voltage, and the output signal NEXT i  is outputted through the node “O 1 ” to the next stage shift register and the display panel to drive the scan lines. 
   Within the period of T 3 , the clock signal CLK 2  inputs a logic-low voltage from the node “a”. Since the transistor DP 2  is diode-connected, the node “a” thereof where the clock signal CLK 2  is received is equivalent to the cathode of the diode, and the voltage of the node “QB” is pulled down to a logic-low voltage through the transistor DP 2  so as to turn on the transistors MP 1  and MP 3 . Since the transistor MP 1  is turned on, the voltage of the node “Q” is pulled up to a logic-high voltage such that the transistors MP 2  and MP 4  are turned off. As the transistor MP 3  is turned on, the output signal NEXT i  is changed into a logic-high voltage. Within the period of T 4 , the clock signals CLK 1  and CLK 2  input logic-high voltages respectively through the nodes “b” and “a” so as to turn off the transistors MP 4  and DP 2 . Since the voltages of the nodes “Q” and “QB” maintain as the state of T 3 , the output signal NEXT i  still remains as a logic-high voltage. 
     FIG. 6A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 5A and 6A , the difference between  FIGS. 6A and 5A  is that the circuit of  FIG. 6A  further includes transistors MP 5 -MP 6 .  FIG. 6B  is a timing diagram of the circuit operation of  FIG. 6A . Referring to  FIGS. 6A and 6B , the circuit operation of the transistor MP 5  is the same as that of the transistor MP 3 , and the circuit operation of the transistor MP 6  is the same as that of the transistor MP 4 ; hence, an output signal SCAN i  is of the same phase as the output signal NEXT i . If the output signal NEXT i  of the shift register is simultaneously outputted to the next stage shift register and the display panel to drive the scan lines, it may result in that the signal outputted to the next stage shift register influenced by the loading effect such that the operation of the scan driving circuit is rendered abnormal. Therefore, in the present embodiment, the output signal follows two paths. One path is outputting the output signal SCAN i  to the display panel to drive the scan lines, and the other path is outputting the output signal NEXT i  to the next stage shift register. 
   The foregoing embodiment illustrates a scan driving circuit that can be applied in the LCD. However, the present invention is not limited to the LCD. One embodiment is described in the following to illustrate how the spirit of the present invention may be applied in devices such as an organic light emitting diode (hereinafter referred to as OLED) display device. In order that people skilled in the art may implement the embodiment, the way the pixel units operate in the OLED is explained first before the embodiment is further described. 
     FIG. 7  is a circuit block diagram of a conventional OLED pixel unit. Referring to  FIG. 7 , a pixel unit  710  includes a data exchange module  701 , a driving circuit  702 , a display exchange module  703  and an OLED  704 . Signal DATA is the data provided by the data driving circuit of the OLED display device. The data are in the voltage form. The data exchange module  701  stores the signal DATA during a period and then the driving circuit  702  converts the data into a current flow and outputs a signal to the display exchange module  703 . As the data exchange module  701  requires a period to store the voltage, the OLED  704  does not need to be driven during this period. The pixel unit  701  utilizes a control signal SX to control whether the display exchange module  703  is turned on so as to determine whether the output signal of the driving circuit  702  drives the OLED  704 . Besides, when a frame is updated, the pixel unit  710  utilizes a control signal DIS with a larger duty cycle to control the resetting of the voltage stored in the data exchange module  701 . 
   Since the pixel unit  710  of the OLED requires a control signal to control whether the display exchange module  703  is turned on and another control signal to reset the stored voltage in the data exchange module  701 . Hence, the organic light emitting diode (OLED) display panel is taken as the display panel  301  in the embodiment of  FIG. 3  in the following embodiment, and likewise the scan driving circuit  303  is taken as the example for the following embodiment. The structure of the scan driving circuit  303  is the same as that shown in the embodiment of  FIG. 4 . 
     FIG. 8A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 5A and 8A , the difference between  FIGS. 8A and 5A  is that the circuit of  FIG. 8A  further includes transistors MP 7  and DP 3 .  FIG. 8B  is a timing diagram of the circuit operation of  FIG. 8A . Referring to  FIGS. 8A and 8B , within the period of T 2 , the output signal NEXT i  is a logic-low voltage, and the transistor MP 7  is turned on. As a result, an output signal NEXTX i  is pulled up to a logic-high voltage. Within the period of T 3 , the output signal NEXT i  is a logic-high voltage, the transistor MP 7  is turned off, and the transistor DP 3  is turned on because the clock signal CLK 2  inputs a logic-low voltage. As a result, the output signal NEXTX i  is pulled down to a logic-low voltage. Within the period of T 4 , the output signal NEXT i  is a logic-high voltage, the transistor MP 7  is turned off, and the transistor DP 3  is turned off because the clock signal CLK 2  inputs a logic-high voltage. As a result, the output signal NEXTX i  maintains at a logic-low voltage. As shown in  FIG. 8B , the output signal NEXTX i  is a complementary signal corresponding to the output signal NEXT i . The output signals NEXTX i  and NEXT i  are out of phase. The purpose of the present embodiment is outputting the output signal NEXT i  to the next stage shift register and the display panel to drive the pixel unit  710 , and also utilizing the output signal NEXTX i  to control whether the display exchange module  703  is turned on. 
     FIG. 9A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 5A and 9A , the difference between  FIGS. 9A and 5A  is that the circuit of  FIG. 9A  further includes transistors MP 5 -MP 7  and DP 3 .  FIG. 9B  is a timing diagram of the circuit operation of  FIG. 9A . Referring to  FIGS. 9A and 9B , the circuit operation of the transistor MP 5  is the same as that of the transistor MP 3 , and the circuit operation of the transistor MP 6  is the same as that of the transistor MP 4 ; hence, the output signal SCAN i  and NEXT i  are in phase. The circuit operations of the transistors MP 7  and DP 3  are the same as the descriptions for  FIGS. 8A and 8B . The difference is that the outputted SCANX i  and SCAN i  are out of phase. The purpose of the present embodiment is outputting the output signal SCAN i  to the display panel to drive the pixel unit  710  with consideration of the influence of the loading effect, outputting the output signal NEXT i  to the next stage shift register, and utilizing the output signal SCANX i  to control whether the display exchange module  703  is turned on. 
   People who are ordinarily skilled in the art should know the function of the transistors MP 7  and DP 3  in the embodiments of  FIGS. 8A and 9A  is in fact equivalent to that of an inverter. Therefore, those ordinarily skilled in the art can replace the transistors MP 7  and DP 3  with an inverter through the teachings of the embodiment. The invention is thus not limited to the embodiment. 
     FIG. 10A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 5A and 10A , the difference between  FIGS. 10A and 5A  is that the circuit of  FIG. 10A  further includes transistors MP 8  and DP 4 .  FIG. 10B  is a timing diagram of the circuit operation of  FIG. 10A . Referring to  FIGS. 10A and 10B , within the period of T 1 , the input signal NEXT i−1  is a logic-low voltage, the transistor MP 8  is turned on, and an output signal VA i  is pulled up to a logic-high voltage. Until within the period of T 3 , the clock signal CLK 2  is inputted as a logic-low voltage to make the transistor DP 4  turned on, thus the output signal VA i  is pulled down to a logic-low voltage. As shown in  FIG. 10B , the output signal VA i  is a signal with a double duty cycle than the input signal NEXT i−1 . The purpose of the present embodiment is providing the control signal VA i  with the double duty cycle to reset the stored voltage in the data exchange module  701 . 
   In the foregoing description of the embodiment, the transistors DP 1 -DP 4  utilize the gate/drain of the P-type MOSFET for coupling; they are rectifying elements using a diode connection method. Hence, people ordinarily skilled in the art can use a diode, an diode-connected N-type MOSFET or a common PN junction diode to substitute for the transistors DP 1 -DP 4  through the teachings of the embodiments of the invention. The details are not to be reiterated herein. 
   It is noted that the shift register of the foregoing embodiment is employed by a P-type MOSFET. Nevertheless, other elements may be selected depending on the user&#39;s needs and the characteristics of an element, such as an N-type MOSFET. Another embodiment is described in the following so that people ordinarily skilled in the art can easily implement the present invention. 
     FIG. 11A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 5A and 11A , the difference between  FIGS. 11A and 5A  is that a shift register  1100  of  FIG. 11A  is employed by an N-type MOSFET, and it includes transistors MN 1 -MN 4  and DN 1 -DN 2 .  FIG. 11B  is a timing diagram of the circuit operation of  FIG. 11A . Referring to  FIGS. 11A ,  11 B,  5 A and  5 B, those ordinarily skilled in the art can know that since the transistors constituting the circuit of  FIG. 11A  are exemplified as the N-type transistors of  FIG. 5A , the voltage levels of the input signals, the clock signals and the output signals in  FIG. 11B  are opposite to the voltage levels of those corresponding signals in  FIG. 5B  respectively. Additionally, as the circuit of  FIG. 11A  utilizes N-type transistors, a ground voltage is used for a common voltage VSS in the embodiment of  FIG. 11A . 
     FIG. 12A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 11A and 12A , the difference between the circuit of  FIG. 12A  and the circuit of  FIG. 11A  is that the circuit of  FIG. 12A  further includes transistors MN 5 -MN 6 .  FIG. 12B  is a timing diagram of the circuit operation of  FIG. 12A . Referring to  FIGS. 12A ,  12 B,  6 A and  6 B, those ordinarily skilled in the art can know that since the transistors constituting the circuit of  FIG. 12A  are exemplified as the N-type transistors of  FIG. 6A , the voltage levels of the input signals, the clock signals and the output signals in  FIG. 12B  are opposite to the voltage levels of those corresponding signals in  FIG. 6B  respectively. The purpose of the present embodiment is outputting the output signal SCAN i  to the display panel to drive the scan lines and outputting the output signal NEXT i  to the next stage shift register with consideration of the influence of the loading effect. 
     FIG. 13A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 11A and 13A , the difference between the circuit of  FIG. 13A  and the circuit of  FIG. 11A  is that the shift register  1100  of  FIG. 13A  further includes transistors MN 7  and DN 3 .  FIG. 13B  is a timing diagram of the circuit operation of  FIG. 13A . Referring to  FIGS. 13A ,  13 B,  8 A and  8 B, those ordinarily skilled in the art can know that since the transistors constituting the circuit of  FIG. 13A  are exemplified as the N-type transistors of  FIG. 8A , the voltage levels of the input signals, the clock signals and the output signals in  FIG. 13B  are opposite to the voltage levels of those corresponding signals in  FIG. 8B  respectively. The present embodiment aims at outputting from different designs of the driving circuit of the display device, such as the scan driving circuit of the OLED, the output signal NEXT i  to the OLED display panel to drive the pixel unit thereof and to the next stage shift register, and providing alternatively a complementary output signal NEXTX i  wherein the output signal NEXTX i  and NEXT i  are out of phase. 
     FIG. 14A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 11A and 14A , the difference between the circuit of  FIG. 14A  and the circuit of  FIG. 11A  is that the shift register  1100  of  FIG. 14A  further includes transistors MN 5 -MN 7  and DN 3 .  FIG. 14B  is a timing diagram of the circuit operation of  FIG. 14A . Referring to  FIGS. 14A ,  14 B,  9 A and  9 B, those ordinarily skilled in the art can know that since the transistors constituting the circuit of  FIG. 14A  are exemplified as the N-type transistors of  FIG. 9A , the voltage levels of the input signals, the clock signals and the output signals in  FIG. 14B  are opposite to the voltage levels of those corresponding signals in  FIG. 9B  respectively. The present embodiment aims at outputting from different designs of the driving circuit of the display device, such as the scan driving circuit of the OLED, the output signal SCAN i  to the OLED display panel to drive the pixel unit thereof, outputting the output signal NEXT i  to the next stage shift register, and providing alternatively a complementary output signal SCANX i  with consideration of the influence of the loading effect, wherein the output signal SCANX i  and SCAN i  are out of phase. 
   Those ordinarily skilled in the art should know that the function of the transistors MN 7  and DN 3  of the embodiments of  FIGS. 13A and 14A  is in fact equivalent to that of an inverter. Therefore, those ordinarily skilled in the art can replace the transistors MN 7  and DN 3  with an inverter through the teachings of the embodiment. The invention is not limited to the embodiment. 
     FIG. 15A  is a circuit implementation diagram of the shift registers  401 - 403  according to the embodiment of  FIG. 4 . Referring to  FIGS. 11A and 15A , the difference between the circuit of  FIG. 15A  and the circuit of  FIG. 11A  is that the shift register  1100  of  FIG. 15A  further includes transistors MN 8  and DN 4 .  FIG. 15B  is a timing diagram of the circuit operation of  FIG. 15A . Referring to  FIGS. 15A ,  15 B,  10 A and  10 B, those ordinarily skilled in the art can know that since the transistors constituting the circuit of  FIG. 15A  are exemplified as the N-type transistors of  FIG. 10A , the voltage levels of the input signals, the clock signals and the output signals in  FIG. 15B  are opposite to the voltage levels of those corresponding signals in  FIG. 10B  respectively. The present embodiment aims at outputting from different designs of the driving circuit of the display device, such as the scan driving circuit of the OLED display device, the output signal NEXT i  to the OLED display panel to drive the pixel unit thereof and to the next stage shift register, and providing alternatively a complementary output signal VA i  with a double duty cycle than the input signal NEXT i−1 . 
   In the foregoing descriptions of the embodiments, the transistors DN 1 -DN 4  utilize the diode-connected N-type MOSFET; they are rectifying elements using a diode connection method. Hence, people ordinarily skilled in the art can replace the transistors DN 1 -DN 4  with a diode or a diode-connected P-type MOSFET. 
     FIG. 16  is a timing diagram of the circuit operation of  FIG. 4 . Referring to  FIGS. 4 and 16 , the shift registers  401 - 403  respectively utilize the circuit of  FIG. 6A  as an example to describe the spirit of the invention. The first stage shift register  401  receives the scan driving signal SP, utilizes the clock signals CLK 1  and CLK 2  to output a signal NEXT 1  through the input nodes “a” and “b” within the period of T 2  to the shift register  402 , and outputs a signal SCAN 1  to the display panel to drive the scan lines. The second stage shift register  402  receives the output signal NEXT 1  outputted from the last stage shift register  401 , utilizes the clock signals CLK 2  and CLK 3  to output an output signal NEXT 2  through the input nodes “a” and “b” of the shift register  402  within the period of T 3 , and outputs a signal SCAN 2  to the display panel to drive the scan lines. The third stage shift register  403  receives the output signal NEXT 2  outputted from the last stage shift register  402 , utilizes the clock signals CLK 3  and CLK 1  to output a signal NEXT 3  through the input nodes “a” and “b” of the shift register  403  within the period of T 4 , and outputs a signal SCAN 3  to the display panel to drive the scan lines. 
   Although only the circuit of  FIG. 6A  is taken as an example, the invention is not limited to the example. Any person ordinarily skilled in the art should know from the teachings of the foregoing embodiment that according to different occasions of application, the shift registers of  FIG. 4  may utilize the circuits of  FIGS. 5A ,  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A and  15 A to implementation. 
   Moreover, the data driving circuit  304  of the embodiment in  FIG. 3  may be implemented by the shift registers of  FIGS. 5A ,  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A and  15 A. The only difference is in the different occasions of application. In the data driving circuit  304 , the function of the shift registers is transmitting pixel data to the next stage shift register through controlling the clock signals. The present invention is not limited to application in the scan driving circuit. 
   In summary, the advantages of the present invention at least include the following: 
   1. A single shift register utilizes 2 sets of clock signals to control the output of the output signals and reduces the number of clock control signals and the complexity and the area of the wiring in the hardware. 
   2. A driving circuit constituted by a plurality of shift registers and the display device using the driving circuit utilizes 3 sets of clock signals to control the output of the output signals so as to reduce the number of the clock control signals and the complexity and the area of the wiring in the hardware. 
   The embodiments of the invention further include the following advantages: 
   1. With consideration of the loading effect of resistance-capacitance, a shift register, a driving circuit constituted by a plurality of shift registers and a display device using the driving circuit have two paths to output signals. One is outputting the signals to drive the scan lines of the display panel (or other devices), and the other is transmitting the signals to the next stage shift register. 
   2. A shift register, a driving circuit constituted by a plurality of shift registers and a display device utilizing the driving circuit provide a complementary signal or a signal with a double duty cycle. 
   3. Appropriate elements are selected considering the needs of the user and the characteristics of the elements. For example, a shift register employed by the whole P-type MOSFET may be applied in a driving circuit which is designed to be disposed on the glass substrate of a display panel. 
   It will be apparent to those skilled in the art that various modifications, and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.