Abstract:
The cascaded multilevel inverter is considered to be a promising topology alternative for low-cost and high-efficiency photovoltaic (PV) systems. However, the leakage current issue, resulting from the stray capacitances between the PV panels and the earth, remains a challenge in the photovoltaic cascaded multilevel inverter application. The present invention presents leakage current suppression solutions for the PV cascaded multilevel inverter by introducing properly arranged and designed passive filters. The embodiments of the invention do not include an active semiconductor device, and as such, the leakage current suppression techniques of the present invention retain the simple structure of the cascaded inverter and do not complicate the associated control system.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to currently pending U.S. Provisional Patent Application No., 61/780,119, filed on Mar. 13, 2013 and entitled, “Leakage Current Suppression Solutions for Photovoltaic Cascaded Multilevel Inverter”. 
    
    
     FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     This invention was made with Government support under Grant No. ECCS -1125658 awarded by National Science Foundation. The government has certain rights in the invention. 
    
    
     BACKGROUND OF THE INVENTION 
     To maximize the energy harvested from solar panels, cascaded multilevel inverter topology has been considered in photovoltaic (PV) applications for decades. The cascaded multilevel inverter topology features separate DC (direct current) inputs, making possible the string, or even panel level, maximum power point tracking. The energy harvested from the solar panels can be maximized in case of mismatch in the PV panels due to panel aging, shading effect or accumulation of dust in the panel surface. The cascaded structure can also generate high-quality output waveforms with each semiconductor of the cascaded inverter switching at lower frequency. Moreover, the number of cascaded modules can be extended to allow a transformerless connection to the grid. Consequently, the cascaded multilevel inverter topology can achieve greater DC/AC conversion efficiency. Additionally, compared with conventional central/string inverters, less expensive power semiconductors, having a lower voltage rating, can be utilized. 
     However, the transformerless structure of the cascaded inverters results in undesirable galvanic connections between the grid and the PV panels interfaced with separate cascaded inverters. Due to the parasitic capacitance between the PV panels and earth ground, circulating leakage current can flow through the panels and grid ground, leading to an undesirable increase of the output harmonic content, higher losses, safety concerns and electromagnetic interference problems. 
     In a PV cascaded multilevel inverter topology, two types of leakage current loops may exist. With reference to  FIG. 1 , in a PV cascaded multiple inverter  100 , a first leakage current loop  105  is formed by the parasitic capacitance  110   a,    110   b,    110   c,  inverter-bridge  115   a,    115   b,    115   c  and grid ground  120 . The second leakage current loop  125  is formed between the individual inverter bridges  115   a,    115   b,    115   c  of the cascaded multilevel inverter. The second leakage current loop  125  between the inverter bridges  115   a,    115   b,    115   c  is a capacitive coupling path exhibiting negligible inductance. The high-frequency pulse-width modulation (PWM) voltage of the cascaded inverter results in pulsewise leakage current in the second leakage current loop. In comparison to single transformerless inverters, the second leakage current loop is a unique leakage current loop in the cascaded multiple inverter topology. In addition, the second leakage current loop is present regardless of whether or not there is a transformer at the cascaded inverter output. 
     Leakage current suppression techniques for conventional single transformerless inverters have been well reported. However, there has been limited research regarding the leakage current issues in PV cascaded multilevel inverters. The leakage current issue present a challenge for the design of a reliable PV system based on a cascaded multilevel inverter. There exists a need in the art for a system and method that can produce a reliable PV system based on a cascaded multilevel inverter. 
     However, in view of the art considered as a whole at the time the present invention was made, it was not obvious to those of ordinary skill in the field of this invention how the shortcomings of the prior art could be overcome. 
     BRIEF SUMMARY OF THE INVENTION 
     This present invention relates to suppression techniques for a photovoltaic system based upon a multilevel cascaded inverter. More specifically, it relates to various embodiments for suppressing leakage current in a photovoltaic cascaded multilevel inverter. 
     A system for leakage current suppression in a photovoltaic cascaded multilevel inverter is provided. In one embodiment, the system includes a photovoltaic cascaded inverter, the photovoltaic cascaded inverter comprising one or more inverter modules and each of the one or more inverter modules comprising a DC-side and an AC-side. The system further includes a common mode DC-side choke coupled to the DC-side of each of the one or more inverter modules and a common mode AC-side choke coupled to the AC -side of each of the one or more inverter modules. The system further includes one or more common mode capacitors coupled to the DC-side of the one or more inverter modules and the parameters of the DC-side choke, AC-side choke and common mode capacitors are designed to suppress the leakage current of the photovoltaic cascaded multilevel inverter. In a particular embodiment, the DC-side choke, the AC-side choke and the common mode capacitors are designed to have a resonant frequency that is substantially lower than a switching frequency of the photovoltaic cascaded inverter. 
     In another embodiment, a system for leakage current suppression in a photovoltaic cascaded multilevel inverter includes a photovoltaic cascaded inverter, a common mode DC-side choke coupled to the DC-side of each of the one or more inverter modules, a common mode AC-side choke coupled to the AC-side of each of the one or more inverter modules, one or more DC-side circulating path capacitors coupled to the DC-side of the one or more inverter modules and one or more AC-side circulating path capacitors coupled to the AC-side of the one or more inverter modules. In this embodiment, the DC-side circulating path capacitors and the AC-side circulating path capacitors are connected at a common node and the DC-side choke, the AC-side choke, the DC-side circulating capacitors and the AC-side circulating capacitors are designed to have a resonant frequency that is substantially lower than a switching frequency of the photovoltaic cascaded inverter. 
     A method for suppressing leakage current in a photovoltaic cascaded multilevel inverter is provided wherein the leakage current is suppressed using a DC-side choke, an AC-side choke and a common mode capacitor coupled to the inverter modules of the photovoltaic cascaded multilevel inverter. In this method, the DC-side choke, the AC-side choke and the one or more common mode capacitors are designed to have a resonant frequency that is substantially lower than a switching frequency of the photovoltaic cascaded inverter. 
     In an additional embodiment, a method for suppressing leakage current in a photovoltaic cascaded multilevel inverter is provided wherein the leakage current is suppressed using a DC-side choke, an AC-side choke, one or more DC-side circulating path capacitors coupled to the DC-side of the one or more inverter modules and one or more AC-side circulating path capacitors coupled to the AC-side of the one or more inverter modules. In this method, the DC-side choke, the AC-side choke, the DC-side circulating capacitors and the AC-side circulating capacitors are designed to have a resonant frequency that is substantially lower than a switching frequency of the photovoltaic cascaded inverter. 
     Leakage current suppression technique for photovoltaic cascaded multilevel inverters is provided. The leakage current suppression system and method in accordance with the present invention provide a reliable PV system based upon a cascaded multilevel inverter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a fuller understanding of the invention, reference should be made to the following detailed description, taken in connection with the accompanying drawings, in which: 
         FIG. 1  is a circuit diagram illustrating the exemplary leakage current loops in a photovoltaic cascaded multilevel inverter. 
         FIG. 2  is a circuit diagram of a PV cascaded multilevel inverter using a method of leakage current suppression in accordance with a first embodiment of the present invention. 
         FIG. 3  is a circuit diagram illustrating an equivalent circuit of the PV cascaded inverter employing the first embodiment for leakage current suppression in accordance with the present invention. 
         FIG. 4  is a circuit diagram illustrating a simplified leakage current analytical model in accordance with the first embodiment of the present invention. 
         FIG. 5  is a circuit diagram of a PV cascaded multilevel inverter using a method of leakage current suppression in accordance with a second embodiment of the present invention. 
         FIG. 6  is a circuit diagram illustrating an equivalent circuit of the PV cascaded inverter employing the second embodiment for leakage current suppression in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings, which form a part hereof, and within which are shown by way of illustration specific embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. 
     With reference to  FIG. 2 , a first embodiment of the present invention is illustrated wherein AC (alternating current) side and DC (direct current) side common-mode (CM) filters C cm , L cm   _   dc , and L cm   _   ac  are added to the multilevel cascaded inverter circuitry. As shown with reference to  FIG. 2 , a system for leakage current suppression in a photovoltaic cascaded multilevel inverter  200  includes, a photovoltaic cascaded inverter comprising one or more inverter modules  215   a,    215   b,    215   c.  Each of the inverter modules  215   a,    215   b,    215   c  has a DC-side and an AC-side. In this exemplary embodiment, the DC-side of the each of the inverter modules  215   a,    215   b,    215   c  is coupled to an element of photovoltaic array  220   a,    220   b,    220   c  and receives the DC source from the photovoltaic array. The photovoltaic cascaded inverter transforms the DC power source from the photovoltaic array to a source of AC power  230  on the AC-side of each of the inverter modules  215   a,    215   b,    215   c.  Each of the inverter modules  215   a,    215   b,    215   c  comprises a plurality of inverter circuits. In one embodiment, the plurality of inverter circuits of the inverter modules  215   a,    215   b,    215   c  may be configured as H-bridge inverter modules. In this embodiment, a common mode DC-side choke (inductor)  235   a,    235   b,    235   c  is coupled to the DC-side of each of the inverter modules  215   a,    215   b,    215   c  and a common mode AC-side choke  240   a,    240   b,    240   c  is coupled to the AC-side of each of the inverter modules  215   a,    215   b,    215   c.  Additionally, two common mode capacitors  245   a,    245   b,    245   c  are coupled to the DC-side of each of the inverter modules  215   a,    215   b,    215   c.  A DC-link capacitor  250   a,    250   b,    250   c  is coupled between the DC-side choke  235   a,    235   b,    235   c  and the DC-side of each of the one or more inverter modules  215   a,    215   b,    215   c  and two same split inductor  255   a,    255   b  are coupled between the common mode AC-side choke  240   a,    240   b,    240   c  and a ground node  260 , at the output of the photovoltaic cascaded inverter. A parasitic capacitor of the PV array for each cascaded module is designated as C pvi , i=1,2, . . . , n,  265   a,    265   b,    265   c.  The current through the parasitic capacitor to be suppressed is designated as i leak   _   Hi , i=1,2, . . . , n.  270   a,    270   b,    270   c  and the leakage current flowing through the grid side to be suppressed is denoted as i leak   _   g    275 . 
     In operation of this embodiment, the leakage current of the PV multilevel cascaded inverter is limited by the low-pass LC filters formed by the PV array parasitic common mode capacitors  245   a,    245   b,    245   c  and the added CM filters formed by the DC-side chokes  235   a,    235   b,    235   c  and the AC-side choke  240   a,    240   b,    240   c.  The resonant frequencies of the LC filters are designed to be much lower than the inverter switching frequency. Therefore, the carrier harmonics across the parasitic capacitors  265   a,    265   b,    265   c  can be attenuated. However, the capacitance of the CM capacitors C cm    245   a,    245   b,    245   c  is usually limited by safety requirements, so the resonant frequency of the formed LC filter cannot be designed very low. Otherwise, large CM inductors are needed. Therefore, this embodiment is more suitable for the cascaded multilevel inverter operated at high switching frequency. 
     In the transformerless PV cascaded multilevel inverter with leakage current suppression  200  illustrated in  FIG. 2 , each cascaded inverter module is composed of a PV array  220   a,    220   b,    220   c,  DC-side CM choke L cm   _   dc    235   a,    235   b,    235   c,  CM capacitors C cm    245   a,    245   b,    245   c,  DC-link capacitor C in    250   a,    250   b,    250   c,  H-bridge inverter  215   a,    215   b,    215   c  and AC-side CM choke L cm   _   ac    240   a,    240   b,    240   c.  Additionally, there are two same split inductors L  255   a,    255   b  at the total output of the inverter. A parasitic capacitor of the PV array for each cascaded module is designated as C pvi , i=1,2, . . . n,  265   a,    265   b,    265   c.  The current through the parasitic capacitor to be suppressed is designated as i leak   _   Hi , i=1,2, . . . n.  270   a,    270   b,    270   c  and the leakage current flowing through the grid side to be suppressed is denoted as i leak   _   g    275 . The leakage current is suppressed by properly designing the parameters of L cm   _   ac , L cm   _   dc  and C cm . 
     The equivalent circuit  300  of the PV cascaded inverter using leakage suppression system  200  of  FIG. 2  is illustrated with reference to  FIG. 3 . The equivalent circuit  300  includes the two commond mode capacitors  245   a,    245   b,    245   c,    245   d  and the parasitic capacitors  265   a,    265   b,    265   c,    265   d  associated with each level of the inverter circuit. The equivalent circuit  300  further includes an inductance L cm   _   dc +L cm   _   ac    380   a,    380   b,    380   c,    380   d  which is a combination of the DC-side inductance and the AC-side inductance and the output inductors  255   a,    255   b.  The voltage sources v ia    305   a,    305   b,    305   c,    305   d  and v ib (i=1,2, . . . ,n)  310   a,    310   b,    310   c,    310   d  represent the two phase leg voltages of the ith cascaded module referring to the negative terminal of its DC bus. v ia    305   a,    305   b,    305   c,    305   d  and v ib    310   a,    310   b,    310   c,    310   d  mainly contain the DC component, fundamental frequency component and baseband harmonics, carrier harmonics and the related sideband harmonics. The carrier harmonics and the related sideband harmonics are the main contributors to the leakage current i leak   _   Hi , i=1,2, . . . ,n.  270   a,    270   b,    270   c  of the photovoltaic cascaded multilevel interver. The magnitude of these harmonics is dependent upon the PV string/panel output voltage and inverter modulation strategy. To better understand the suppression principle and introduce the filter design criteria, the analytical expression for the leakage current is derived based on the equivalent model. The xth inverter module is selected arbitrarily for the calculation. 
     According to the superposition theory, the branch current i zx    385  through the inductance L cm   _   dc +L cm   _   ac    380   a,    380   b,    380   c,    380   d  of the xth inverter module can be first calculated as in (1). 
                     i   Zx     =             v     1   ⁢           ⁢   a       +     v   nb             Z   L     +     (         Z   1     //   …     //     Z   n       )       //     Z   L         ·         (               Z   1     //   …     //     Z     x   -   1         //     Z     x   +   1         //   …     //     Z   n       )     //     Z   L             Z   x     +     (               Z   1     //   …     //     Z     x   -   1         //     Z     x   +   1         //   …     //     Z   n       )       //     Z   L           +       ∑     i   =   2     x     ⁢           v   ia     -     v       (     i   -   1     )     ⁢   b               (         Z   1     //   …     //     Z     i   -   1         )     //       Z   L     +     (         Z   i     //   …     //     Z   n       )         //     Z   L         ·         (               Z   i     //   …     //     Z     x   -   1         //     Z     x   +   1         //   …     //     Z   n       )     //     Z   L             Z   x     +     (               Z   i     //   …     //     Z     x   -   1         //     Z     x   +   1         //   …     //     Z   n       )       //     Z   L             +       ∑     i   =   x       n   -   1       ⁢           v   ib     -     v       (     i   +   1     )     ⁢   a               (         Z     i   +   1       //   …     //     Z   n       )     //       Z   L     +     (         Z   1     //   …     //     Z   i       )         //     Z   L         ·         (               Z   1     //   …     //     Z     x   -   1         //     Z     x   +   1         //   …     //     Z   i       )     //     Z   L             Z   x     +     (               Z   1     //   …     //     Z     x   -   1         //     Z     x   +   1         //   …     //     Z   i       )       //     Z   L                       (   1   )               
where
 
                 Z   i     =       jω   ⁡     (       L   cm_dc     +     L   cm_ac       )       +     1     jω   ⁡     (       C   pvi     +     2   ⁢     C   cm         )             ,     i   =   1     ,   2   ,   …   ⁢           ,       n   ⁢           ⁢   and   ⁢           ⁢     Z   L       =     jω   ⁢           ⁢     L   .               
The contribution of the grid voltage to the ground leakage current  275  is relatively small, so it is ignored in the calculation.
 
     Because Z L  is usually much smaller than the impedance of L cm   _   dc +L cm   _   ac    380   a,    380   b,    380   c,    380   d  at the inverter switching frequency and above frequencies, the values of the terms containing Z L  in (1) should have the same order of magnitude. Also the value of (Z i // . . . //Z x−1 //Z x+1 //Z n )//Z L  and (Z 1 // . . . //Z x−1 //Z x+1 //Z i )//Z L  should be close to the value of Z L . As a result, eq. (1) can be simplified as in (2). 
     
       
         
           
             
               
                 
                   
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     The simplified model implies an equivalent circuit  400  as shown with reference to  FIG. 4 , which is composed of a voltage source  405  connected with an LC circuit in series  410 . The voltage source  405  is related to the phase leg voltages of all cascaded inverter modules. The LC circuit is formed by L cm   _   dc +L cm   _   ac +L and C pvi +2C cm· i leak   _   Hx  can be calculated by (3). 
     
       
         
           
             
               
                 
                   
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     According to the simplified model, the impedance of Z x +Z L  should be designed large enough at the switching frequency to suppress the leakage current. The resonant frequency of Z x +Z L  needs to be much lower than the inverter switching frequency to fulfill that requirement. The final parameters of the filters can be designed using (2), providing that v ia  and v ib  (i=1,2, . . . ,n) are known. Because the capacitance of the CM capacitors C cm  is usually limited by safety requirements, the resonant frequency of the formed LC filter cannot be designed very low, otherwise, large CM inductors are necessary. Therefore, this embodiment is more suitable for the cascaded multilevel inverter which is operating at a high switching frequency. The applicability of this embodiment, at a pre-selected switching frequency, depends upon the constraint of the filter size and cost. 
     In an additional embodiment, as illustrated with reference to  FIG. 5 , a current leakage suppression system  500  is realized by adding AC-side common mode chokes  240   a,    240   b,    240   c  and DC-side common mode chokes  235   a,    235   b,    235   c  as in the first embodiment, and capacitors C cir   _   dc    505   a,    505   b,    505   c  and C cir   _   ac    510 . An extra current circulating path is formed among the common mode chokes  240   a,    240   b,    240   c,    235   a,    235   b,    235   c,  bridges of the inverter modules  215   a,    215   b,    215   c,  and capacitors C cir   _   dc    505   a,    505   b,    505   c  and C cir   _   ac    510 . The circulating path contains LC circuits whose resonant frequencies are designed to be lower than the inverter switching frequency. The carrier harmonics across the parasitic capacitors  265   a,    265   b,    265   c  can be attenuated by the formed LC circuits. The advantage of this solution is that the capacitance of C cir   _   dc    505   a,    505   b,    505   c  and C cir   _   ac    510  can be relatively large, so this embodiment can be applied for the inverter which is operating at a much lower switching frequency without using very large common mode chokes. 
     The leakage current suppression system  500  is realized by adding commond mode chokes L cm   _   dc    235   a,    235   b,    235   c  and L cm   _   ac    240   a,    240   b,    240   c,  DC-side circulating capacitors C cir   _   dc    505   a,    505   b,    505   c  and AC-side circulating capacitor C cir   _   ac    510 . In this embodiment, there is a common connection point among the capacitors C cir   _   dc    505   a,    505   b,    505   c  of each cascaded module and the AC-side capacitor C cir   _   ac    510 . An additional current circulating path is formed by the common mode chokes, bridges, and circulating capacitors C cir   _   dc  and C cir   _   ac . To better understand the suppression principle and introduce the filter design criteria, the analytical expression for the leakage current is derived. 
     As illustrated with reference to  FIG. 6 , in a system equivalent circuit  600  of  FIG. 5 , the current through the xth parasitic capacitor i leak   _   Hx    605   a,    605   b,    605   c,    605   d  is equal to 
                     i   leak_Hx     =         i   cir_dcx     ⁢       C   pvx       2   ⁢           ⁢     C   cir_dc           +       i   cir_ac     ⁢       C   pvx       2   ⁢           ⁢     C   cir_ac                     (   4   )               
where i cir   _   dcx    615   a,    615   b,    615   c,    615   d  is the sum current through the two C cir   _   dc  capacitors  505   a,    505   b,    505   c,    505   d  of the xth inverter module; i cir   _   ac    610  is the total current through the two C cir   _   ac  capacitors  510 . Usually C cir   _   ac    510  and C cir   _   dc    505   a,    505   b,    505   c,    505   d  are designed to be much larger than the parasitic capacitance  265   a,    265   b,    265   c,    265   d,  so we can get that
 
                 c   pvx       2   ⁢           ⁢     C   cir_dc         ⪡   1         
and
 
                 c   pvx       2   ⁢           ⁢     C   cir_ac         ⪡   1.         
Therefore, according to (4), i leak   _   Hx    605   a,    605   b,    605   c,    605   d  can be limited when the value of i cir   _   ac    615   a,    615   b,    615   c,    615   d  and i cir   _   ac    610  are attenuated.
 
     Based on the equivalent model, i cir   _   dcx    615   a,    615   b,    615   c,    615   d  and i cir   _   ac    610  can be calculated as in (5) and (6) respectively. 
     
       
         
           
             
               
                 
                   
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                                     + 
                                     1 
                                   
                                   ) 
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     i 
                                     - 
                                     1 
                                   
                                   ) 
                                 
                               
                               i 
                             
                           
                           
                             Z 
                             ⁡ 
                             
                               ( 
                               
                                 
                                   2 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   Z 
                                 
                                 + 
                                 
                                   2 
                                   ⁢ 
                                   
                                     nZ 
                                     cir_ac 
                                   
                                 
                                 + 
                                 
                                   nZ 
                                   L 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
                     i   cir_ac     =       ∑     i   =   1     n     ⁢     i   cir_dci               (   6   )               
where Z cir   _   ac =1/j2ωC cir   _   ac , Z=jω(L cm   _   dc +L cm   _   ac )+1/j2ωC cir   _   dc  and Z L =jωL. Because the parasitic capacitance  265   a,    265   b,    265   c,    265   d  is usually much smaller than C cir   _   ac    505   a,    505   b,    505   c,    505   d  and C cir   _   dc    510 , they are ignored in the calculation of i cir   _   dcx    615   a,    615   b,    615   c,    615   d  and i cir   _   ac    610 .
 
     The expression i cir   _   dcx  in (5) is composed of three terms. In order to attenuate i cir   _   dcx  and i cir   _   ac , the denominators of the three terms should be designed large enough at the inverter switching frequency and at frequencies above the inverter switching frequency. The attenuation can be realized by designing the resonant frequencies of both impedance Z and (2Z +2nZ cir   _   ac +nZ L ) lower than the inverter switching frequency. The final parameters of the filters  620   a,    620   b,    620   c,    620   d  can be designed by using (4)-(6). 
     The present invention provides various embodiments for leakage current suppression for photovoltaic cascaded multilevel inverters. The leakage current suppression systems and methods in accordance with the present invention provide a reliable PV system based upon a cascaded multilevel inverter. 
     The advantages set forth above, and those made apparent from the foregoing description, are efficiently attained. Since certain changes may be made in the above construction without departing from the scope of the invention, it is intended that all matters contained in the foregoing description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.