Abstract:
A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layerand a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

Description:
BACKGROUND OF INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a wafer production method used in an etching process of a substrate, and more particularly, to a high density wafer production method for controlling a thickness of the wafer.  
           [0003]    2. Description of the Prior Art  
           [0004]    Silicon substrates are presently widely used in integrated circuits, optical electronics, microelectronics and microelectromechanical systems (MEMS). However, silicon substrates have shortcomings in many applications. For example, silicon substrates are crystal materials with crystal directions. Anisotropic etching processes are performed on silicon substratesby usinga potassium hydroxide (KOH) solution.The etching speed of silicon in the direction &lt;100&gt; and &lt;110&gt; is far faster than that in the direction of &lt;111 &gt; for forming an inclined plan with 54.74 °, creating a large waste of space. The waste of space becomes more serious with an increasing thickness of the silicon substrate.  
           [0005]    Please refer to FIG. 1 through FIG. 3, which are diagrams of print head structures of the prior art. FIG. 1 is disclosed in U.S. Pat. No. 6,019,907 “Forming refill for monolithic inkjet printhead”. As shown in FIG. 1, the prior art inkjet printhead is formed on a silicon substrate  10  comprising two slots  11 , 12  for passing ink, two nozzle chambers  14 , 15  located on the surface of slots  11 , 12  for jetting the ink, and two resistors  16 , 17 . The resistor  16  is located between the nozzle chamber  14  and the slot  11 , and the resistor  17  is located between the nozzle chamber  15  and the slot  12  for heating the ink. The slots  11 , 12  form a refilling chamber  13  for decreasing the turbulent effect.  
           [0006]    [0006]FIG. 2 is disclosed in U.S. Pat. No. 5,658,471 “Fabrication of thermal ink-jet feed slots in a silicon substrate.” As shown in FIG. 2, the prior art inkjet printhead is formed on a silicon substrate  20  comprising slot  21  formed in the center of the substrate  20  for passing the ink, a dielectric layer  22  formed on the surface of the substrate  20 , and two heaters  23 , 24  formed on the surface of the dielectric layer  22  for heating the ink. The dielectric layer  22  isolates the substrate  22  from the heaters  23 , 24 . The structures shown in FIG. 1 and FIG. 2 are different, but they are manufactured by similar processes, and both waste space.  
           [0007]    Please refer to FIG. 3, which shows a prior art inkjet printhead formed on a silicon substrate. As shown in FIG. 3, a standard cleaning process is performed on a silicon substrate with a width W 1  and a thickness T 1 .A passivation layer  31  and a patterned passivation layer  32 P are formed on a top surface and a bottom surface of a silicon substrate  30  for forming the surface patterns of slots  33 , 34 . A distance between the slot  33  and the slot  34  is L 1  and a distance between slots  33 , 34  and the wafer edge is L 0 . An etching process is performed on the silicon substrate by using potassium hydroxide (KOH) solution to form the structure of the slots  33 , 34 , as shown in FIG. 3.  
           [0008]    The passivation layers  31 , 32 P are composed of silicon oxide or silicon nitride.  
           [0009]    The process of FIG. 3 applied in FIG. 1 and FIG. 2 for producing the inkjet printhead forms an inclined plane at 54.74°, creating a large waste of space. Additionally, the substrateneedssufficient space in L 0  and L 1  (as shown in FIG. 3) to glue an ink box (not shown). An inclined plane formed at 54.74°, and the space required for gluing the box lead to the creation of a large waste of space.  
         SUMMARY OF INVENTION  
         [0010]    It is therefore a primary objective of the present invention to provide a method of high density wafer production that saves space.  
           [0011]    Briefly, the claimed invention provides an etching method for highdensity wafer production used when etching a substrate for controlling a thickness of the wafer. The etching method forms a first patternedpassivation layerand a second passivation layer on a top surface and a bottom surface, followed by performing a first etching process for simultaneously etching the substrate and the first passivation layer. After the first passivation layer is removed, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.  
           [0012]    It is an advantage of the present invention that the etching method controls the thickness of the wafer and the size of slots for inkjet printhead and MicroElectroMechanical Systems applications.  
           [0013]    These and other objectives and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0014]    [0014]FIG. 1 to FIG. 2 are views of an ejecting apparatus according to the prior art.  
         [0015]    [0015]FIG. 3 is a view of a process according to the prior art.  
         [0016]    [0016]FIG. 4 is a view of a process according to the present invention high density wafer production method.  
         [0017]    [0017]FIG. 5 is a view of a second preferred embodiment of the high density wafer production method.  
         [0018]    [0018]FIG. 6 is a third preferred embodiment of the high density wafer production method.  
         [0019]    [0019]FIG. 7 is a fourth preferred embodiment of the high density wafer production method. 
     
    
       [0020]    Table 1 shows a structure size of two slots.  
         [0021]    Table 2 shows a structure size of three slots.  
         [0022]    Table 3 shows a structure size of six slots.  
       DETAILED DESCRIPTION  
       [0023]    [0023]FIG. 4 to FIG. 7 are views of a gradational etching method according to the present invention. Please refer to FIG. 4A. The present invention provides a silicon substrate  40  having the same width W 1  and thickness T 1  as the silicon substrate  30  in FIG. 3 has. A standard cleaning process is performed on the silicon substrate  40 . Please refer to FIG. 4B. A passivation layer  41  and a patterned passivation layer  42 P are formed on a top surface and a bottom surface of the silicon substrate  40  for forming the surface pattern of slots  43 , 44 , which are of the same size as slots  33 , 34  in FIG. 3. The etching speeds of passivation layer  41  and the passivation layer  42 P are different for the same etching solution. The silicon substrate in the present invention is used in an inkjet printhead, so that the slots  43 , 44  are used for passing ink in the inkjet printhead.  
         [0024]    Also, the silicon substrate in the present invention can be substituted by glass, ceramics, metal, or semiconductor crystal.  
         [0025]    Please refer to FIG. 4C. An etching process is performed on the silicon substrate  40  using potassium hydroxide (KOH) for etching the silicon substrate  40  and the passivation layer  42 P simultaneously. The etching speed of the silicon substrate  40  is faster than the etching speed of the passivation layer  42 P. When the silicon substrate  40  is etched to the thickness T 2  (as shown in FIG. 4), the passivation layer  42 P is removed and the passivation layer  41  is reserved. Please refer to FIG. 4D. An etching process is performed subsequently on the silicon substrate  40  and through the silicon substrate  40  from back to front, so as to get a structure with substrate thickness T 3  (T 3 &lt;T 1 ) and two slots  43 , 44 . The distance between the slot  43  and the slot  44  is L 2  and the distance between the slots  43 , 44  and the wafer edge is L 3 . The passivation layers  41  , 42 P are made of metal, ceramics or large molecular compounds. If the passivation layer  41  and the passivation layer  42 P are composed of the same material, the passivation layer  41  is thicker than the passivation layer  42 P. If the passivation layer  41  and the passivation layer  42 P are composed of different materials, the etching speed of  42 P is faster than the etching speed of the passivation layer  41 . Additionally, the etching process described before can be substituted with a wet etching process, a dry etching process, or a mechanical process. The etching processes in FIG. 4C and FIG. 4D can alternatively be an isotropic etching process.  
         [0026]    In contrast to the prior art, the method of the present invention increases the distance L 2  between  43 , 44  (L 2 &gt;L 1 ) and the distance L 3  between the slots  43 , 44  and the edge of silicon substrate  40 . However, the area of the silicon substrate  40  in the present invention is the same with that of the silicon substrate  30  of the prior art.  
         [0027]    Please refer to FIG. 5, which is a view of the second preferred embodiment of the present invention. A silicon substrate  50  having the same width W 1  and thickness T 1  as that shown in FIG. 1 and FIG. 4 has a passivation layer  51  and a patterned passivation layer  52 P on a top surface and a bottom surface of the silicon substrate  50 . Two slots  53 , 54  are formed on the patterned passivation layer  52 P subsequently, and the distance between the slot  53  and the slot  54  is decreased to L 4 , while retaining the same width of slots  53 , 54 . The distance between the slots  53 , 54  and the silicon substrate  50  edge is L 5 . The structure is shown in FIG. 5B. The patterned passivation layer  52 P is formed by a photo-etching process. Other steps are similar with the process shown in FIG. 4. The structure is shown in FIG. 5D after performing an etching process.  
         [0028]    In contrast to the first preferred embodiment in FIG. 4, the second preferred embodiment of the present invention largely decreases the distance L 6  between the slot  53  and the slot  54  (L 6 &lt;L 2 ). If the distance L 6  is the same as the distance L 1 , the length L 7  is used for gluing to the ink box. The second preferred embodiment of the present invention decreases the width of the substrate  50  (W 2 &lt;W 1 ).  
         [0029]    Table 1 shows the results of the mask design pattern size L 4 , L 5  and the silicon substrate size W 2  after performing an etching process to the silicon substrate in the present invention and the prior art.  
         [0030]    Please refer to FIG. 6, which is a view of athird preferred embodiment ofthe present invention. A silicon substrate  60  having the same width W 1  and thickness T 1  as that of FIG. 1 to FIG. 5 is shown in FIG. 6A. A passivation layer  61  and a patterned passivation layer  62 P are formed on a top surface and a bottom surface of the silicon substrate  60 , as shown in FIG. 6B. Three slots  63 , 64 , 65  are formed on the passivation layer  62 P for shortening the distances L 1  to L 4 , while retaining the same width of the slots  63 , 64 , 65 . The distance between slots  63 , 65  and the edge of the silicon wafer  60  is L 5 . Other steps are similar to steps of the process shown in FIG. 4. The structure is shown in FIG. 6C after performing an etching process on the silicon substrate  60 .  
         [0031]    Table 2 shows results of the mask design pattern size L 4 ,L 5  and the silicon substrate size W 3  after performing an etching process to the silicon substrate in the present invention and the prior art.  
         [0032]    Please refer to FIG. 7, which is a view of thefourth preferred embodiment of the present invention. A silicon substrate  70  having the same width W 1  and thickness T 1  as that of FIG. 1 to FIG. 6 is shown in FIG. 7A. A passivation layer  71  and a patterned passivation layer  72 P are formed on a top surface and a bottom surface of the silicon substrate  70 , as shown in FIG. 7B. Six slots  73 , 74 , 75 , 76 , 77 , 78  are formed on the passivation layer  72 P for shortening the distance L 1  to L 4 , while retaining the same width of the slots  73 , 74 , 75 , 76 , 77 , 78 . The distance between slots  73 , 78  and the edge of the silicon wafer  70  is L 5 . Other steps are similar with the steps shown in FIG. 4.  
         [0033]    The structure is shown in FIG. 7C after performing an etching process to the silicon substrate  60 .  
         [0034]    Table 3 shows the results of the mask design pattern size L 4 ,L 5  and the silicon substrate size W 4  after performing an etching process to the silicon substrate in the present invention and the prior art.  
         [0035]    According to a fifth embodiment of the present invention, a first etching process is performed on the silicon substrate of any one preferred embodiment described before. A second etching process is performed on the unpatterned passivation layer for removing the unpatterned passivation layer. A third etching process is performed on the silicon substrate to a designed thickness. Other steps are similar with the preferred embodiment described before.  
         [0036]    The feature of the present invention is to use two passivation layers having different etching speeds of an etching solution for fabricating a device, which reduces wafer size. When two passivation layers have the same etching speed and solution, a passivation layer is removed first for arriving at the same goal of reducing the device wafer size. The size of the wafer in the present invention changes with the thickness of the wafer. The reduction rating of the wafer increases with the slots of the pattern increasing. The present invention discloses a gradational etching process for the advantage of increasing the production yield and reducing the production cost in large wafer size and high density structure processes.  
         [0037]    In comparison to the prior art, the method of the present invention reduces the size of a print head wafer and increases the number of slots, thereby increasing the production yield. In addition, the present invention also applies to different devices such as filtering systems, inkjet print head systems, micro channel systems and sensor systems. The gradational etching process disclosed in the present invention decreases the inclined plane effect by using an isotropic etching process. The process of the present invention is similar with the prior art, without adding complex steps for producing a similar structure and appearance to that of the designed pattern.  
         [0038]    Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.