Abstract:
There is provided a semiconductor device that operates at an internal clock based on a system clock and inputs/outputs data in synchronization with the internal clock. The semiconductor device includes a phase locked loop generating the internal clock and a switching element switching delay paths to be inserted into a feedback loop to the phase locked loop in accordance with data input/output in the semiconductor device.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device and a data input/output system using the semiconductor device and, particularly, to a system for inputting and outputting data based on a system clock. 
         [0003]    2. Description of Related Art 
         [0004]    In a system where a plurality of semiconductor devices are mounted, a signal for synchronizing the entire system, which is called a system clock, is distributed to each semiconductor device. Each semiconductor device operates in synchronization with the system clock, so that the system as a whole operates at the same timing. When transferring data between the semiconductor devices within the system, clock skew between a semiconductor device at the transmitting end and a semiconductor device at the receiving end or a transmission time to transfer data from an output buffer of the semiconductor device at the transmitting end through a line on a printed circuit system board to an input buffer of the semiconductor device at the receiving end vary by external factors such as power supply voltage and temperature. Therefore, it is necessary for the semiconductor device at the receiving end to retain a wide set up margin and hold margin, which hampers the high-speed system clock operation. 
         [0005]      FIG. 5  shows the configuration of such a system.  FIG. 5  illustrates a system which synchronizes semiconductor devices using a phase locked loop, which is abbreviated to PLL. In  FIG. 5 , a system clock is supplied to a transmitting-end semiconductor device  1  through an input terminal  132 . The system clock is input to a reference input point b 1  of a PLL  141  through an input buffer  102 . The clock output from the PLL  141  is then supplied to a clock distribution tree  171 . The clock distribution tree  171  is composed of a plurality of CTS buffers  172  and clock distribution lines. Through the clock distribution tree  171 , the clock with minimal skew is supplied to flip-flops  151  and  152 . 
         [0006]    The output b 2  of the clock distribution tree  171  is supplied as a feedback clock to the feedback input of the PLL  141  through an input buffer  103 . The input buffer  103  is inserted in order to add to the feedback path the same delay time as that of the input buffer  102  at the reference input side of the PLL  141 . Thus, it may be simply a delay circuit as long as it has the same delay characteristics as the input buffer  102 . 
         [0007]    A system clock is supplied also to a receiving-end semiconductor device  2  through an input terminal  232 . The system clock is supplied to flip-flops  251  and  252  or the like through an input buffer  202 , a PLL  241 , and a clock distribution tree  271 . The configuration of the receiving-end semiconductor device  2  is basically the same as that of the transmitting-end semiconductor device  1  and it is thus not described in detail herein. 
         [0008]    The data transfer between the semiconductor devices in such a system is described hereinbelow. In the transmitting-end semiconductor device  1 , external data is input through a data input terminal  131  and supplied to the flip-flop  151  through the input buffer  101 . The flip-flop  151  latches the data based on the clock at the point b 2 . The input data is processed in a logic circuit  161  and the processing result is stored in the flip-flop  152 . The processing result data is output from the flip-flop  152  through an output buffer  111 . The output data is latched into the flip-flop  251  of the receiving-end semiconductor device  2  through an output terminal  133  of the semiconductor device  1 , a line between the semiconductor devices (e.g. a line of the printed circuit board)  300 , an input terminal  231  and an input buffer  201  of the semiconductor device  2 . 
         [0009]    In the receiving-end semiconductor device  2 , the flip-flop  251  latches the data based on the clock at the output point c 2  of the clock distribution tree  271  in the same manner as in the transmitting-end semiconductor device  1 . The data is thereby transferred from the semiconductor device  1  to the semiconductor device  2 . 
         [0010]      FIG. 6  shows a timing chart based on the above-described operation. In the transmitting-end semiconductor device  1 , the phase of the reference CLK input b 1  of the PLL  141  delays to the phase of the system clock a by the delay of tpd 1 I through the input buffer  102 . On the other hand, the phase of the output b 2  of the clock distribution tree  171  advances to the phase of b 1  by the delay through the input buffer  103 . The phase at the data output terminal point b 3  further delays to the phase of b 2  by the delay of tpd 1 O through the output buffer  111  as shown in  FIG. 6 . 
         [0011]    In the receiving-end semiconductor device  2 , if the delay through the line  300  is tpd 3 O and the delay through the input buffer  201  is tpd 2 I, the phase of the data input c 3  to the flip-flop  251  delays to the phase of b 3  by the delay of tpd 3 O+tpd 2 I. On the other hand, the phase of the PLL reference CLK input c 1  delays to the system clock a by the delay of tpd 2 I through the input buffer  202 . 
         [0012]    In the system with such a configuration, if the setup margin and the hold margin of the flip-flop  251  are referred respectively as tSetup (a time from a change of the input data to the flip-flop to a clock edge) and tHold (a time to retain the state value of input data from a clock edge of clock input to the flip-flop), the system clock cycle T is represented as Expression 2 below. Upon consideration of the delay tpd 1 O through the transmitting-end output buffer  111 , the delay tpd 3 O through the line  300 , the delay tpd 2 I through the receiving-end input buffer  201 , and the setup margin tSetup, the system clock cycle T is represented as Expression 1 below. For simplification, the present description defines the setup margin tSetup and the hold margin tHold assuming that the setup time and hold time of the flip-flop are both 0. In these conditions, the following expressions are given: 
         [0000]        T=tpd 1 O+tpd 3 O+tpd 2 I+tSetup   Expression 1: 
         [0000]        T=tSetup+tHold.   Expression 2: 
         [0000]    Expression 1 can be rewritten as: 
         [0000]        tSetup=T −( tpd 2 I+tpd 1 O+tpd 3 O ).  Expression 3: 
         [0000]    From Expressions 2 and 3, the following expression is given: 
         [0000]        tHold=tpd 2 I+tpd 1 O+tpd 3 O.   Expression 4: 
         [0013]    The delay of the output buffer, the delay of the input buffer or the like varies by external factors such as power supply voltage and temperature. Thus, the setup margin tSetup and the hold margin tHold should be wide enough to absorb the variation. It is therefore difficult to shorten the cycle T. 
         [0014]    The technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-347764 (Nomura et al.) addresses this drawback.  FIG. 7  shows the system taught by Nomura et al. In  FIG. 7 , the same elements as in  FIG. 5  are denoted by the same reference symbols and redundant description is omitted. In the semiconductor devices  1  and  2  shown in  FIG. 7 , the outputs b 2  and c 2  of the clock distribution trees  171  and  271  are supplied as feedback clocks to the feedback inputs of the PLLs  141  and  241  through the input buffers  103 ,  203  and the output buffers  113 ,  213 , respectively. The semiconductor devices of  FIG. 7  are different from the semiconductor devices of  FIG. 5  in that the output buffers  113  and  213  are added to the clock feedback paths to the PLLs  141  and  241 . 
         [0015]    According to the technique taught by Nomura et al., such a configuration is not affected by the delay through the output buffer  111  of the transmitting-end semiconductor device  1 .  FIG. 8  shows the timing chart of the device described in Nomura et al. In consideration of the delay tpd 2 O through the output buffer  213  which is inserted to the feedback path at the receiving end, the setup margin and the hold margin in the system according to Nomura et al. are expressed as follows: 
         [0000]        tSetup=T −( tpd 2 O+tpd 2 I+tpd 3 O )  Expression 5: 
         [0000]        tHold=tpd 2 O+tpd 2 I+tpd 3 O.   Expression 6: 
         [0016]    In the technique disclosed in Nomura et al., however, the setup margin tSetup and the hold margin tHold vary by the external factor of the output buffer delay at the receiving end as is obvious from the fact that Expressions 5 and 6 contain the delay tpd 2 O through the output buffer of the receiving-end semiconductor device  2 . Accordingly, even with the configuration as taught by Nomura et al., it is still difficult to shorten the system clock cycle T to achieve high-speed operation due to the effects of external factors. 
       SUMMARY OF THE INVENTION 
       [0017]    According to one aspect of the present invention, there is provided a semiconductor device that operates at an internal clock based on a system clock and inputs/outputs data in synchronization with the internal clock, including a phase locked loop generating the internal clock, and a switching element switching delay paths to be inserted into a feedback loop to the phase locked loop in accordance with data input/output in the semiconductor device. 
         [0018]    According to another aspect of the present invention, there is provided a data input/output system including a first semiconductor device outputting data in synchronization with a first internal clock based on a system clock, and a second semiconductor device inputting data in synchronization with a second internal clock based on a system clock, wherein the first internal clock advances to the second internal clock by a phase corresponding to an output buffer delay in the first semiconductor device. 
         [0019]    This configuration prevents a setup margin and hold margin from being affected by output buffer delay in the semiconductor device. Furthermore, the configuration allows the reduction of a setup margin to thereby enable the system to operate at a higher speed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
           [0021]      FIG. 1  is a view showing the configuration according to a first embodiment of the present invention; 
           [0022]      FIG. 2  is a timing chart showing the operation according to the first embodiment; 
           [0023]      FIG. 3  is a view showing the configuration according to a second embodiment of the present invention; 
           [0024]      FIG. 4  is a view showing the configuration according to a third embodiment of the present invention; 
           [0025]      FIG. 5  is a view showing the configuration according to a related art; 
           [0026]      FIG. 6  is a timing chart to describe the operation according to a related art; 
           [0027]      FIG. 7  is a view showing the configuration according to a related art; and 
           [0028]      FIG. 8  is a timing chart to describe the operation according to a related art. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0029]    The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed. 
       First Embodiment 
       [0030]      FIG. 1  is a block diagram showing the system according to a first embodiment of the present invention. A first embodiment is described with reference to a system which includes a plurality of semiconductor devices that are mounted on a mother board or the like and operate in synchronization with the system clock of the mother board. The system of this embodiment includes a transmitting-end semiconductor device  10  and a receiving-end semiconductor device  20 . The transmitting-end semiconductor device  10  and the receiving-end semiconductor device  20  are connected through a line  300  on a printed circuit board, for example. The transmitting-end semiconductor device  10  and the receiving-end semiconductor device  20  include PLL  141  and  241 , clock distribution trees  171  and  271 , flip-flops  151 ,  152  and  251 ,  252 , logic circuits  161  and  261 , input buffers  101  to  103  and  201  to  203 , output buffers  111 ,  113  and  211 ,  213 , and switches SW 1  and SW 2 , respectively. 
         [0031]    The semiconductor device which is mounted on the system according to this embodiment is described hereinafter with reference to the transmitting-end semiconductor device  10  as an example. In this embodiment, the system clock which is input through the point a shown in  FIG. 1  is input as a reference clock to the PLL  141  through the input terminal  132  and the input buffer  102 . The PLL  141  outputs an internal clock based on the reference clock to the clock distribution tree  171 . The clock distribution tree  171  distributes the clock to the flip-flops  151  and  152  or the like in the semiconductor device  10  through the CTS buffers  172  and the clock distribution lines. The output b 2  of the clock distribution tree  171  is input as a feedback clock to the PLL  141  through the switch SW 1 , the output buffer  113  and the input buffer  103 . 
         [0032]    The output buffer  113  and the input buffer  103  which are inserted to the feedback path may be simply configured as delay circuits as long as they have the same delay characteristics as the output buffer  111  which outputs data and the input buffers  101  and  102  which receive system clocks in the semiconductor device  10 . 
         [0033]    The switch SW 1  includes selectors  181  and  182  to select whether to supply the output of the clock distribution tree  171  to the input buffer  103  either directly or through the output buffer  113  according to a feedback path switching signal S 1 , which is described later. Specifically, the switch SW 1  outputs the output b 2  of the clock distribution tree  171  either through the point d or through the point f depending on the feedback path switching signal. When supplying the output b 2  of the clock distribution tree  171  directly to the point d, the selector  182  selects the ground voltage to thereby stop the operation of the output buffer  113 . 
         [0034]    Data to be processed in the semiconductor device  10  is latched into the flip-flop  151  through the data input terminal  131  and the input buffer  101 . After being processed in the logic circuit  161 , the data is latched into the flip-flop  152 . The latched data is then output through the output buffer  111  and the output terminal  133 . In accordance with its operation, the logic circuit  161  outputs the feedback path switching signal S 1  described above. In this embodiment, during the transmitting operation (output), the output b 2  of the clock distribution tree  171  is input to the input buffer  103  through the output buffer  113  by connecting the point b 2  to the point f. During the receiving operation (input), the output of the clock distribution tree  171  is input to the input buffer  103  directly by connecting the point b 2  to the point d. 
         [0035]    The receiving-end semiconductor device  20  has basically the same configuration as the transmitting-end semiconductor device  10  and it is thus not described in detail herein. 
         [0036]    In the data transfer from the transmitting-end semiconductor device  10  to the receiving-end semiconductor device  20 , data is latched into the flip-flop  151  in synchronization with the clock at the output b 2  of the clock distribution tree  171 . The latched data is processed in the logic circuit  161  and then latched into the flip-flop  152  in synchronization with the clock at b 2 . After that, the data is output through the output buffer  111  and the output terminal  133 . The data output from the semiconductor device  10  is then latched into the flip-flop  251  of the semiconductor device  20  through the line  300  between the semiconductor devices and the input terminal  232  and the input buffer  201  of the semiconductor device  20 . 
         [0037]      FIG. 2  is a timing chart showing the timing of the series of operations described above. The above-described operations are described hereinafter in detail with reference to  FIGS. 1 and 2 . 
         [0038]    When a system clock as shown at the top of  FIG. 2  is supplied to the point a in  FIG. 1 , the phase of the reference clock which is input to the PLL  141  at the point b 1  in the semiconductor device  10  delays by the delay of tpd 1 I due to the input buffer  102 . The phase of the feedback input b 4  to the PLL  141  is aligned with the phase of the input b 1  by the PLL  141  and therefore it is the same as the phase of the input b 1 . 
         [0039]    Because the semiconductor device  10  is at the transmitting end, the switch SW 1  selects the path to feedback through the output buffer  113  and the input buffer  103 . Thus, the phase of b 2  advances to the phase of b 4  by the delay of tpd 1 O through the output buffer  113  and the delay of tpd 1 I through the input buffer  103 . On the other hand, the phase of data at b 3  which is output from the semiconductor device  10  delays to the clock at b 2  by the delay of tpd 1 O through the output buffer  111 . Accordingly, the data with the phase aligned with the phase of the system clock (a) is output at b 3  from the semiconductor device  10  as shown in  FIG. 2 . 
         [0040]    On the other hand, the data at c 3  which is input to the flip-flop  251  of the semiconductor device  20  changes from the data change at b 3  by the delay tpd 3 O through the line  300  and the delay through the input buffer  201  as illustrated in the sixth waveform in  FIG. 2 . Because the semiconductor device  20  is supplied with the same system clock as that for the semiconductor device  10 , the reference clock input c 1  to the PLL  241  has the phase difference corresponding to the delay tpd 2 I of the input buffer  202  with respect to the point a. The phase of the feedback input c 4  to the PLL  241  is aligned with the phase of the input c 1  by the PLL  241  and therefore the inputs c 1  and c 4  have the same phase. 
         [0041]    Because the semiconductor device  20  is at the receiving end, the switch SW 2  selects the path to feedback without through the output buffer  213 . The output c 2  of the clock distribution line is thus supplied directly to the input buffer  203  by connecting the point c 2  to the point i. 
         [0042]    Accordingly, the phase at the point c 2  advances to the phase at the point c 4  by the delay of tpd 2 I due to the input buffer  203 . The cycle T of the system clock is determined by the following expressions in consideration of the delay tpd 3 O through the line and the delay through the input buffer  201 : 
         [0000]        T=tpd 3 O+tpd 2 I+tSetup   Expression 7: 
         [0000]        T=tSetup+tHold   Expression 8: 
         [0000]    From Expressions 7 and 8, the setup margin tSetup and the hold margin tHold can be calculated as follows: 
         [0000]        tSetup=T −( tpd 3 O+tpd 2 I )  Expression 11: 
         [0000]        tHold=tpd 3 O+tpd 2 I   Expression 12: 
         [0043]    As obvious from the above expressions, neither of the expressions representing the setup margin and the hold margin includes the term indicating the delay through the output buffer of the semiconductor  10  or  20  according to this embodiment. 
         [0044]    In the related art, if the delay tpd 1 O and tpd 2 O are 3 ns (typ), they vary in the range from 1.5 ns to 4.5 ns under the conditions of a power supply voltage of +/−10% and a temperature of −40° C. to 125=C. The timing margins of tSetup and tHold decrease by the variation range of 3 ns, and it is thus difficult to shorten the cycle T. 
         [0045]    Because the term indicating the output buffer is not included in any expressions according to this embodiment, the cycle T can be set shorter by the variation range of 3 ns. It is thereby possible to set the system clock to a higher frequency to thereby achieve higher-speed operation. 
         [0046]    Furthermore, according to this embodiment, the clock edge of the clock which is output from the clock distribution tree  171  in the transmitting-end semiconductor device  10  is set earlier than the clock edge of the clock which is output from the clock distribution tree  271  in the receiving-end semiconductor device  20 , thereby increasing the timing margin. 
       Second Embodiment 
       [0047]      FIG. 3  is a view showing the configuration according to a second embodiment of the present invention. In  FIG. 3 , the same elements as in  FIG. 1  are denoted by the same reference symbols and not described in detail herein. The second embodiment is different from the first embodiment in that the semiconductor device  10  and the semiconductor device  20  transfer data with each other. In this system, the output buffer  111  of the semiconductor device  10  is replaced by a bidirectional buffer  121 , and the input buffer  201  of the semiconductor device  20  is replaced by a bidirectional buffer  221 . The bidirectional buffer  121  is composed of the output buffer  111  and an input buffer  104 , and the bidirectional buffer  221  is composed of the output buffer  212  and an input buffer  201 . The output buffer  111  incurs the delay of tpd 1 O, the input buffer  104  incurs tpd 1 I, the output buffer  212  incurs tpd 2 O, and the input buffer  201  incurs tpd 2 I. 
         [0048]    In such a configuration, the semiconductor devices  10  and  20  select the feedback path through the output buffer  113  and  213 , respectively, when transmitting data and select the feedback path not through the output buffer  113  or  213  when receiving data as described earlier. 
         [0049]    Further, based on the feedback path switching signals S 1  and S 2  for selecting the feedback path, the output buffer of the bidirectional buffer is set to ENABLE or DISABLE state. The system is in output mode when the output buffer of the bidirectional buffer is ENABLE state; the system is in input mode when the output buffer is DISABLE state. 
         [0050]    For example, in the semiconductor device  10 , the output buffer  111  is ENABLE state (and the output buffer  212  of the bidirectional buffer  221  is DISABLE state) when the bidirectional buffer  121  transmits data to the semiconductor device  20 . On the other hand, the output buffer  111  is DISABLE state (and the output buffer  212  of the bidirectional buffer  221  is ENABLE state) when the bidirectional buffer  121  receives data from the semiconductor device  20 . The states (ENABLE/DISABLE) of the bidirectional buffers  121  and  221  are set opposite to each other in this manner. 
         [0051]    Such a configuration achieves the high-speed operation of the system as in the first embodiment and further enables the intercommunication between the semiconductor devices. Although  FIG. 3  illustrates the case where only the output buffer  111  of the semiconductor device  10  and the input buffer  201  of the semiconductor device  20  are configured as bidirectional buffers, the input buffer  101  of the semiconductor device  10  and the output buffer  211  of the semiconductor device  20  may also be configured as bidirectional buffers. 
       Third Embodiment 
       [0052]      FIG. 4  is a circuit diagram showing the configuration according to a third embodiment of the present invention. As described in the second embodiment, if data input and output are performed using bidirectional buffers, each bidirectional buffer includes an input buffer and an output buffer. Thus, it is possible to replace the output buffers  113  ( 213 ) and  103  ( 203 ) which are included in the feedback path in the second embodiment by bidirectional buffers that are identical to those used for data input and output. The use of the identical bidirectional buffers allows the delay characteristics in the feedback path to be substantially the same as the delay characteristics in the data input/output, which enables the reduction of timing mismatch with a simple configuration. In such a case, an input buffer  107  which incurs the delay time corresponding to that of the input buffer  103  (i.e. tpd 1 I) in  FIG. 3 , and an input buffer  207  which incurs the delay time corresponding to that of the input buffer  203  (i.e. tpd 2 I) in  FIG. 3  are inserted between the selector  181  and the point b 2  and between the selector  281  and the point c 2 , respectively. The input buffer  107  and the input buffer  207  may be simply a buffer or a delay circuit as long as the delay time is a desired value as described above. 
         [0053]    As described above, the present invention prevents the setup margin and the hold margin from being affected by the delay through the output buffer in the semiconductor device. This allows the reduction of a setup margin to thereby enable the system to operate at a higher speed. 
         [0054]    It is apparent that the present invention is not limited to the above embodiment and it may be modified and changed without departing from the scope and spirit of the invention.