Abstract:
A method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g 1  and a gate g 2  in a netlist; mapping source gates of g 1  with any permutation of source gates of g 2  by using calls to an isomorphism detection algorithm; determining whether a permutation exists of pairings between the gates sourcing g 1  and g 2 ; resetting pairing of gates if the permutation exists; and eliminating pairwise-identical source gates of g 1  and g 2.

Description:
TRADEMARKS  
       [0001]     IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to enhanced structural redundancy detection, and particularly to sequential redundancy identification algorithms for identifying gates within a sequential netlist.  
         [0004]     2. Description of Background  
         [0005]     Sequential redundancy identification algorithms have widespread applications, such as being the core techniques for sequential equivalence checking, and being critical to sequential design optimization techniques (for synthesis purposes).  
         [0006]     A variety of techniques have been proposed for sequential redundancy identification. For example, one approach consists of first assuming all gates to be sequentially redundant, then performing an inductive fixed-point computation of iteratively forming smaller “buckets” of suspected-redundant pairs based upon failed equivalence-checking proofs. As another example, structural isomorphism approaches may be employed to attempt to identify gates, which must be sequentially redundant because of the structure of their cones of influence.  
         [0007]     For instance, if gates g 1  . . . gn in the logic cones upon which gates h 1  and h 2  are constructed may be correlated 1:1 such that only gates of identical function are mapped to each other; gates gi and gj are correlated only if all of their inputs are correlated; and inputs in the cone of h 1  and h 2  can only be reflexively mapped, then it is assured that h 1  and h 2  are sequentially redundant. Isomorphism-based redundancy detection is lossy, in that two gates, which behave redundantly, may not have isomorphic cones. Nonetheless, isomorphism-based redundancy detection may be much faster than traditional semantic-analysis approaches.  
         [0008]     A variety of techniques have been proposed for sequential redundancy identification. However, existing sequential redundancy identification techniques are slow and not scalable. It is desired to provide sequential identification techniques to advance the speed and scalability of sequential redundancy identification.  
       SUMMARY OF THE INVENTION  
       [0009]     The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g 1  and a gate g 2  in a netlist; mapping source gates of g 1  with any permutation of source gates of g 2  by using calls to an isomorphism detection algorithm; determining whether a permutation exists of pairings between the gates sourcing g 1  and g 2 ; resetting pairing of gates if no permutation of source gates g 1  and g 2  exists; and eliminating pairwise-identical source gates of g 1  and g 2 .  
         [0010]     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.  
       TECHNICAL EFFECTS  
       [0011]     As a result of the summarized invention, technically we have achieved a solution which identifies isomorphic cones with sub-linear resources by exploiting reflexivities. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:  
         [0013]      FIG. 1  illustrates one example of a traditional algorithm for redundancy identification through isomorphism detection;  
         [0014]      FIG. 2  illustrates one example of isomorphism detection that requires a 1:1 mapping;  
         [0015]      FIG. 3  illustrates one example of isomorphism detection for redundant gate identification that allows n:1 mapping between redundant gates;  
         [0016]      FIG. 4  illustrates one example of a super-linear redundancy identification algorithm;  
         [0017]      FIG. 5  illustrates one example of an improved super-linear redundancy identification algorithm; and  
         [0018]      FIG. 6  illustrates one example of a hybrid algorithm for redundancy detection using structural and semantic analysis.  
     
    
       [0019]     The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0020]     One aspect of the exemplary embodiments is a mechanism to identify isomorphic cones with sub-linear resources by exploiting reflexivities during the mapping process. Another aspect of the exemplary embodiments is a mechanism to speed up isomorphism detection by exploiting on the fly merging during the analysis. Another aspect of the exemplary embodiments is a mechanism to improve the performance and completeness of redundancy identification by intertwining semantic and structural approaches in an efficient resource-bounded manner.  
         [0021]     Turning now to the drawings in greater detail,  FIG. 1  illustrates a traditional algorithm for redundancy identification through isomorphism detection.  
         [0022]     A netlist contains a directed graph with vertices representing gates, and edges representing interconnections between those gates. The gates have associated functions, such as constants, primary inputs, combinational logic such as AND gates, and sequential elements (e.g., registers). Registers have two associated components: their next-state functions, and their initial-value functions. Both are represented as other gates in the graph. Semantically, for a given register, the value appearing at its initial-value gate at time “0” (“initialization” or “reset” time) is applied as the value of the register itself; the value appearing at its next-state function gate at time “i” is applied to the register itself at time “I+1.” Two gates h 1  and h 2  are said to be sequentially redundant if for every trace, comprising valuations to h 1  and h 2  over time which are consistent with the netlist semantics, h 1  and h 2  evaluate the same sequence of values.  
         [0023]     Note that isomorphism detection algorithms are required to traverse the entire cone driving g 1  and g 2  before they are allowed to return a TRUE answer. This is generally required to ensure that there is a 1:1 mapping between the gates in the cone of g 1  and g 2 , without which isomorphism is difficult. Second, due to the need to attempt all permutations of pairings between the gates sourcing g 1  and g 2 , note that isomorphism detection generally requires exponential resources. Lastly step  3  of the algorithm of  FIG. 1  is necessary only for algorithms which use isomorphism detection for redundancy identification, which is needed to ensure that not only are g 1  and g 2  implementing identical functions due to their isomorphic structures, but over an identical set of inputs.  
         [0024]     Referring to  FIG. 2 , a mechanism to identify isomorphic cones with sub-linear resources by exploiting reflexivities during the mapping process is illustrated. This mechanism relies upon the observation that for redundancy-identification geared isomorphism checking, mapping gate g 1  to g 2  does not preclude mapping another gate g 3  to g 2 . In traditional isomorphism-detection algorithms this would be disallowed. For example, consider the netlist of  FIG. 2 . Assume that identification of whether gates g 5  and g 6  are isomorphic. During this process, gates g 4 , the “top” source gate of both g 5  and g 6 , is paired with itself; and gates g 1  and g 2 , the source gates of g 4 , with themselves. However, in attempting to pair gate g 3 , the “bottom” source gate of g 6 , with g 2 , the “bottom” source gate of g 5 , this pairing attempt fails since g 2  is already paired with itself. Gates g 5  and g 6  are not truly isomorphic, nor are they redundant, since g 6  is a gate, which cannot evaluate to 1 (since it is an AND expression over both g 2  and NOT (g 2 )). In contrast, gate g 5  may evaluate to both 0 and 1 since it does not have such an expression.  
         [0025]     Referring to  FIG. 3 , there are certain conditions in which mappings may safely be n:1 while preserving isomorphism. Consider the netlist of  FIG. 3 . Assume that it is desired to check the isomorphism of gates g 5  and g 6 . During this process, gate g 3 , the “top” source gate of both g 5  and g 6 , is paired with itself. However, when attempting to pair the “bottom” source gates of g 5  and g 6 , a conflict arises and g 3  cannot be paired with g 4  because g 3  is already paired with itself. Nonetheless, if this pairing were allowed, it would succeed in allowing isomorphism detection to detect that g 5  and g 6  are truly redundant; both implement function (g 1  AND g 2 ).  
         [0026]     Referring to  FIG. 4 , the reasons why in some cases a 1:1 gate mapping is not necessary for the use of isomorphism for redundancy detection, is due to the fact that it is safe to enable n:1 mappings among redundant gates. For example, it is safe to map g 3  to both g 3  and g 4  in  FIG. 3 . This observation allows the modification of the algorithm of  FIG. 1  to effectively neglect recording reflexive mappings, which enables n:1 mappings in cases to identify redundancy, as in the example of  FIG. 3 . This also enables the algorithm to run in super-linear time in cases, i.e., it need not even touch every gate in the cone of g 1  and g 2  once, if g 1 ==g 2 .  
         [0027]     Furthermore, with regards to  FIG. 4 a  mechanism to achieve further speedups through on the fly merging is illustrated. The modified redundancy identification algorithm of  FIG. 4  has two distinct benefits. First, it enables substantial performance benefits by avoiding the traversal of “reflexive” cones where g 1 ==g 2 , and further exploits this performance boost by reordering permutations of possible recursive calls to prune identical source gates. Second, it enables the algorithm to identify certain redundant gates which require n:1 mappings vs. flagging those as irredundant as would be the case with traditional algorithms, as per  FIG. 1 . An additional extension to the algorithm of  FIG. 4 , which further exploits these benefits, is described in  FIG. 5 .  
         [0028]     Referring to  FIG. 5 , in identifying redundant gates, it is safe to map any redundant gates to each other, whereas the extension of  FIG. 1  only allows at most a 2:1 mapping: the reflexive mapping, and one other arbitrary redundant mapping. A mechanism that enables true n:1 mapping is described in  FIG. 5 .  
         [0029]     The algorithm of  FIG. 5  offers several improvements over that of  FIG. 4 . First, it “remembers” gates that were previously demonstrated to be redundant through the “mapping” field. In particular, if it is demonstrated that g 1  and g 2  are redundant, this is recorded in step  13  of the algorithm. Later, while attempting to assess redundancy of gates which may have g 1  and g 2  in their fan-in, this recording is exploited in steps  1  and  2  of the algorithm to basically treat all gates that have been demonstrated to be redundant with g 1  as if they were g 1 , enabling a true n:1 redundant gate identification paradigm.  
         [0030]     Second, this recording enables further speedups to the process due to step  3 , which precludes traversing reflexive cones. Whereas in the algorithm of  FIG. 4 , the cone of g 1  is not traversed only when attempting to pair g 1  with g 3 , provided that g 1  and g 3  were previously identified as being redundant. This enables iterative and incremental speedups to the redundancy identification process as more and more gates in the cones of the top-level gate pair under analysis are determined to be redundant.  
         [0031]     Referring to  FIG. 6 , an efficient mechanism to improve the performance and completeness of redundancy detection via a resource-constrained iteration between semantic and structural analysis is illustrated. This aspect leverages the observation raised in  FIG. 2 , that gages identified as redundant during earlier phases of analysis can be used to simplify later analysis. It further improves upon the solution of  FIG. 2  by leveraging the use of semantic algorithms to identify redundant gates, which may not be identifiable as such via structural analysis.  
         [0032]     Semantic analysis is often more expensive than structural isomorphism analysis. For instance, the approach of  FIG. 1  requires refinement iterations based upon failed proof attempts. In other words, each proof attempt may require exponential resources, and there may be a linear number of proof attempts (one per gate in the cone of g 1  and g 2 ).  
         [0033]     Also, the identification of redundant gates simplifies the structural analysis of subsequent gates in terms of run-time improvements (since reflexive traversals are neglected), and in enabling the identification of gates which are redundant but not in a readily-identifiable structural way (due to necessary n:1 pairings to enable structural redundancy identification).  
         [0034]     Algorithm is_equivalent(g 1 ,g 2 ,mapping) uses any semantic approach for attempting to prove the equivalence gates g 1  and g 2 . Passing “mapping” into this algorithm only serves to simplify the analysis therein, by flagging the gates within the cones of g 1  and g 2  which were previously identified as redundant by either the structural analysis (e.g., from a prior call to is_isomorphic) or semantic analysis (e.g., from a prior call to is_equivalent). This algorithm iterates between the semantic and structural algorithms in an increasing-resource fashion, ultimately yielding a conclusive result with minimal resources. This is because for many problems, structural analysis is faster than semantic; though in others, we have the opposite solution. So leveraging both algorithms together renders an optimal solution with minimal resources.  
         [0035]     Furthermore, for some gates in the sub-cones of g 1  and g 2 , one approach may outperform the other and for other gates in the same sub-cones, the other may hold true. Therefore, the hybrid approach may yield exponentially faster results than either standalone approach, as would be the limits with traditional approaches.  
         [0036]     The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.  
         [0037]     As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.  
         [0038]     Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.  
         [0039]     The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.  
         [0040]     While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.