Abstract:
A method and apparatus that utilizes soft outputs from a paging device demodulator to perform frame synchronization is provided. The soft outputs are summed after being correlated to a first pattern associated with a paging protocol. The summation is then compared to a frame synchronization threshold. Frame synchronization occurs when the summation reaches the threshold. Using soft outputs, and a summation of the outputs based on a correlation with the first pattern, the method and apparatus require less processing, are more efficient and are more reliable than conventional synchronization schemes.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of paging devices and, more particularly to a reliable and fast frame synchronization scheme for FLEX protocol paging devices. 
     2. Description of the Related Art 
     The use of paging devices has increased dramatically over the years. Paging allows a person to contact a user of a paging device even in situations where the user is not in close proximity of a telephone. Paging devices allow the calling party to leave a telephone number where the party can be reached and/or a textual message such as “CALL TOM” so that the purpose of the “page” is apparent to the user. 
     Due to recent developments, paging is being performed at higher speeds and with increased data capacity. The developments are attributable to the FLEX paging protocol that has quickly become the industry standard. In addition, newly developed power management techniques designed for use with the FLEX protocol have increased the battery power-savings capability of the paging devices. 
     The power-savings result from the fact that a pager designed to operate with the FLEX protocol will remain in a dormant low-power “standby” mode for almost the entire time that the paging device is powered-on. Once every four minutes, the paging device “wakes up” from the dormant standby mode and determines if there are any incoming messages destined for that paging device. Any incoming messages are processed and the paging device resumes the standby mode. Older protocols required the paging device to continuously check for incoming messages which quickly reduced the life of the pager&#39;s batteries. Battery savings is a major concern in the paging industry and the FLEX protocol increases the battery savings of paging devices. 
     Referring to FIGS. 1 and 2, the paging device can remain dormant for long periods of time because the FLEX protocol uses a synchronous time-slotted frame format having a data-frame cycle  10  lasting four minutes. Each cycle  10  contains one hundred and twenty-eight data packets or frames  20  that are transmitted once during each cycle  10 . Each frame  20  lasts approximately 1.875 seconds and has a preferred base data rate of 6400 bits per second. The FLEX protocol also supports data rates of 1600 and 3200 bit per second. 
     Each frame  20  contains a first bit synchronization portion  22  (hereinafter referred to as “bit sync #1”), first rate information portion  24  (hereinafter referred to as “rate info #1”), second bit synchronization portion  26  (hereinafter referred to as “bit sync #2”), second rate information portion  28  (hereinafter referred to as “rate info #2”) and eleven message block portions  30 . 
     As shown in FIG. 2, bit sync # 1  is a 32-bit pattern comprising alternating 1&#39;s and 0&#39;s. Bit sync # 2  is a 16-bit pattern comprising alternating 0&#39;s and 1&#39;s. Rate info # 1  is a 32-bit pattern containing the data rate of the frame while rate info # 2  is a 32-bit pattern containing the complement of rate info # 1 . As is known in the art, the message blocks  30  contain the address of the pager that will receive the message and message information. 
     In general, each paging device is assigned a frame  20  within a cycle  10 . To determine if the paging device has an incoming message, the paging device must wake up and synchronize itself to its assigned frame  20 . Once synchronized, the paging device checks the remainder of the frame to determine if there is an incoming message destined for the address of the paging device. If there is no incoming message, the paging device resumes its standby mode. If there is an incoming message, the paging device processes the message and then resumes its standby mode. The process is repeated once every four minutes, i.e., once every cycle. 
     FIG. 3 illustrates the synchronization process  60  currently performed by conventional paging devices. The process  60  begins by reading a bit input from the assigned frame (step  62 ) and updating the last thirty-two input bits with the new input bit (step  64 ). A bit-by-bit comparison is made between the last thirty-two input bits and the bit sync # 1  pattern (step  66 ) to determine a number of matches between the two. Once the number of matches between the last thirty-two input bits and the bit sync # 1  pattern is obtained, it is determined if the number of matches is greater than or equal to a predetermined threshold T (step  68 ). Since the input bits may be corrupted by noise or other adverse conditions, a threshold T less than thirty-two is typically used. If the number of matches is greater than or equal to the threshold T, the frame is in sync (step  70 ) and the process  60  is complete. Upon completion of the process  60 , further message processing is performed by the paging device. If the number of matches is not greater than or equal to the threshold T, the process continues at step  62  where the next input bit is read and the process  60  continues until there is a frame synchronization (at step  70 ). 
     The synchronization process  60  is not without its shortcomings. For example, the bit-by-bit comparisons used to determine whether there is a match between the input bits and the bit sync # 1  pattern are made using “hard-decision” bits (that is, the decision is based on 1&#39;s and 0&#39;s). The bit-by-bit comparison resulting in the number of matches between the bit sync # 1  pattern and the input data is performed using the hard-decision numbers means that any incorrect hard-decisions values will corrupt the number of matches. Thus, the process  60  is not too reliable. Accordingly, there is a desire and need for a reliable frame synchronization scheme for a paging device utilizing the FLEX paging protocol. 
     In addition, the process  60  is currently implemented in the software controlling the paging device. The hard-decisions and the bit-by-bit comparisons used to determine the number of matches between the input bits and the bit sync # 1  pattern require numerous programming operations. The numerous programming operations slow down the processing required to perform the frame synchronization. 
     The reliability of the conventional frame synchronization process  60  can be improved by further considering bit-by-bit comparisons and the number of matches between the input data and the bit sync # 2  or frame info patterns. These additional matches, however, add additional programming operations and processing time to the frame synchronization and would be inefficient. An inefficient and slow frame synchronization scheme is undesirable. Accordingly, there is a desire and need for a reliable frame synchronization scheme for a paging device utilizing the FLEX paging protocol that can be performed quickly and efficiently. 
     SUMMARY OF THE INVENTION 
     The present invention provides a reliable frame synchronization scheme for a paging device utilizing the FLEX paging protocol. 
     The present invention also provides a reliable frame synchronization scheme for a paging device utilizing the FLEX paging protocol that can be performed quickly and efficiently. 
     The above and other features and advantages of the invention are achieved by providing a method and apparatus that utilizes soft outputs from a paging device demodulator to perform frame synchronization. The soft outputs are summed after being correlated to a first pattern associated with a paging protocol. The summation is then compared to a frame synchronization threshold. Frame synchronization occurs when the summation reaches the threshold. Using soft outputs, and a summation of the outputs based on a correlation with the first pattern, the method and apparatus require less processing, are more efficient and are more reliable than conventional synchronization schemes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other advantages and features of the invention will become more apparent from the detailed description of the preferred embodiments of the invention given below with reference to the accompanying drawings in which: 
     FIGS. 1 and 2 illustrate a data cycle of the FLEX paging protocol; 
     FIG. 3 illustrates the synchronization process performed by conventional paging devices; 
     FIG. 4 illustrates in block diagram form an exemplary paging device constructed in accordance with the present invention; 
     FIG. 5 is a flow chart illustrating a first embodiment of a frame synchronization process performed by the present invention; and 
     FIG. 6 is a flow chart illustrating a second embodiment of a frame synchronization process performed by the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The invention is implemented on a conventional paging device by the provision of some additional programming of the paging device processor to enable the device to carry out the operations described herein. The invention may be implemented in any conventional paging device which includes a processor to control the complex functions of the device. Thus, the invention is not restricted to any particular paging device circuit architecture. 
     FIG. 4 illustrates a high-level block diagram of a representative paging device  100  for performing the frame synchronization method of the present invention. The device  100  includes an antenna  102 , receiving circuit  104 , demodulator  106 , memory circuit  108 , controller  110 , alerting circuitry  112  and a display  114 . 
     The antenna  102  is coupled to the receiving circuit  104 . The receiving circuit  104  is also coupled to a demodulator  106 . The demodulator is also coupled to a controller  110 . The controller  110  may be a digital signal processor, microcomputer or other processor capable of being programmed to perform the functions of a paging device. The controller  110  is also coupled to the memory circuit  108 , display  114  and the alerting circuitry  112 . The components are all conventional and cooperate together to perform the functions of a conventional paging device  100 . Examples of paging devices and their operation can be found in U.S. Pat. No. 5,649,315 (Eaton) and U.S. Pat. No. 5,646,589 (Murray et al) which are hereby incorporated by reference in their entirety. 
     As is known in the art, the receiving circuit  104  receives radio frequency (RF) page signals from the antenna  102 , processes the RF signals and passes the processed signals to the demodulator  106 . Typical processing performed by the receiving circuit  104  includes amplification, modulation and filtering of the received RF signals. The demodulator  106  receives the signals from the receiving circuit  104 , demodulates the signal and delivers the demodulated signal to the controller  110 . The controller  110  attempts to synchronize to the demodulated signal. Synchronization according to the present invention will be described below in detail with reference to FIGS. 5 and 6. Once the controller  110  is synchronized to the input signal, the signal is inspected to see if there is a message for this paging device  100 . If there is a message for the paging device  100 , the controller  110  processes it, displays it on the display  114  and/or sends a signal to the alerting circuitry  112  which alerts the user of the device  100  that an incoming page has been received. 
     Program instructions, as well as data required by the controller  110 , are stored in the memory circuit  108 . The programming instructions stored in the memory  108  will include instructions required by the controller  110  to perform the conventional functions of a paging device  100  (as disclosed in the &#39;315 and &#39;589 patents) as well as instructions to carry out the frame synchronization method of the present invention. In addition, outputs from the demodulator  106  are used as inputs by the controller  110  as is described below with reference to FIGS. 5 and 6. 
     FIG. 5 is a flow chart illustrating a first embodiment of a frame synchronization process  200  performed by the present invention. The process  200  begins by reading an input value received from the demodulator (i.e., an output from the demodulator) from the frame assigned to the paging device (step  202 ). Unlike the conventional frame synchronization process  60  (illustrated in FIG.  3 ), the process  200  of the present invention reads in the soft outputs from the demodulator, not a hard-decision output created from the soft output. As is known in the art, the demodulator of a paging device outputs “soft” or multi-bit outputs corresponding to a real number (e.g., 0.8). In the conventional paging devices, once the soft output is received by the paging device&#39;s controller, a decision is made as to whether this multi-bit real number represents a −1 or a +1 (known in the art as a hard-decision). Therefore, in the conventional frame synchronization process  60  (illustrated in FIG.  3 ), the multi-bit demodulator outputs are being converted to a 1-bit value corresponding to either a −1 (represented by a logic 0) or +1 (represented by a logic 1). The process  200  of the present invention inputs the actual real number value that is output by the demodulator. Therefore, there is no need to perform the hard-decision on the demodulator output to create input bits representing either a −1 or a +1 as required by the conventional process  60  (FIG.  3 ). This saves processing time since the hard decision is not being performed. The reliability of the frame synchronization process  200  is also greatly improved since no conversions or hard-decisions are being performed and thus, no information concerning the value of the demodulator outputs is being lost. 
     As will become apparent, the process  200  is designed to operate on thirty-two values input from the demodulator. As in the process  60  (FIG.  3 ), the step of inputting the first thirty-one input values is not shown in FIG.  5 . Once at least thirty-two input values are read in, the last thirty-two input values are correlated c 1 (n) to the bit sync # 1  pattern (step  204 ). A threshold T 1 (n) for the correlation c 1 (n) is also calculated at step  204 . 
     The correlation c 1 (n) and the threshold T 1 (n) are computed as follows. In the following equations, x(n) is the current input value received from the demodulator, n is an index associated with the current input value and the last thirty-two input values are represented as x(n−31), x(n−30), . . . x(n−1), x(n). The correlation c 1 (n) and the threshold T 1 (n) are calculated as follows:              c   1          (   n   )       =       ∑     k   =   0     31                       x        (     n   -   k     )            b        (   k   )             ,     
              T   1          (   n   )       =       ∑     k   =   0     31                          x        (     n   -   k     )                ,                          
     where k is a bit position, b(k) is the bit sync # 1  pattern at position k, b(k)=1 if the corresponding bit in the bit sync # 1  pattern is a 1 and b(k)=−1 if the corresponding bit in the bit sync # 1  pattern is 0. It must be noted that the input values x(n), etc. are being correlated to the bit sync # 1  pattern and are then added to form a summed correlation c 1 (n), and are not being not matched bit-by-bit as performed in the conventional process  60  (FIG.  3 ). Using the above equations, it is apparent that there will be a large value for the correlation c 1 (n) when there is a frame synchronization and a low value when there is no frame synchronization. 
     Referring again to FIG. 5, at step  206 , the correlation c 1 (n) is compared to the threshold T 1 (n) to determine if a frame synchronization has occurred. To account for some noise that may corrupt the input values, the threshold T 1 (n) is multiplied by a constant α, where 0&lt;α&lt;1, to form a modified threshold αT 1 (n). Preferably, the constant α=0.83. If the correlation c 1 (n) is greater than the modified threshold αT 1 (n), then a frame synchronization has occurred (step  208 ) and the process  200  is complete. If the correlation c 1 (n) is not greater than the modified threshold αT 1 (n), then a frame synchronization has not occurred and the process  200  continues at step  202  where the next input value is read in. The process  200  continues until there is a frame synchronization (i.e., c 1 (n)&gt;αT 1 (n)). 
     It should be appreciated that the process  200  does not perform a bit-by-bit comparison between the input values received from the demodulator and the bit sync # 1  pattern. The input values are summed after being correlated to the bit sync # 1  pattern. Using the above equations and using input values corresponding to the soft outputs from the demodulator, the process  200  is faster, more reliable and thus, more efficient than the convention frame synchronization process  60  (FIG.  3 ). 
     It has been determined that the above correlation c 1 (n) and threshold T 1 (n) computations can be greatly reduced by taking advantage of the knowledge of the bit synchronization patterns within the FLEX protocol data frame (see FIGS.  1  and  2 ). The above correlation c 1 (n) and threshold T 1 (n) computations can be reduced to: 
     
       
           c   1 ( n )= x ( n )− x ( n− 32)− c   1 ( n− 1) 
       
     
     and 
       T   1 ( n )=| x ( n )|−| x ( n− 32)|+ T   1 ( n− 1), 
     where c 1 (n−1) is the previous correlation and T 1 (n−1) is the previous threshold. 
     It should be appreciated that the correlation c 1 (n) computation has been reduced to merely two subtractions and the threshold T 1 (n) computation has been reduced to a subtraction and one addition. Thus, the processing time of these computations has been reduced even more. These new equations for the correlation c 1 (n) and threshold T 1 (n) could be used in the process  200 . However, since potential errors may occur if the incoming signal is slightly misaligned, any declared frame synchronization (i.e., where c 1 (n)&gt;αT 1 (n)) should be confirmed by an additional comparison of the input values to another portion of the data frame. 
     Accordingly, FIG. 6 is a flow chart illustrating a second embodiment of a frame synchronization process  300  performed by the present invention. The process  300  begins by reading an input value received from the demodulator (i.e., an output from the demodulator) from the frame assigned to the paging device (step  302 ). Similar to the process  200  (FIG. 5) and unlike the conventional frame synchronization process  60  (illustrated in FIG.  3 ), the process  300  reads in the soft outputs from the demodulator, not a hard-decision output created from the soft output. Once at least thirty-two input values are read in, the last thirty-two input values are correlated to the bit sync # 1  pattern to form a first correlation c 1 (n) (step  304 ). A first threshold T 1 (n) for the first correlation c 1 (n) is also calculated at step  304 . As stated above, the first correlation c 1 (n) and the first threshold T 1 (n) are computed as follows: 
     
       
           c   1 ( n )= x ( n )− x ( n− 32)− c   1 ( n− 1) 
       
     
     and 
     
       
           T   1 ( n )=| x ( n )|−| x ( n− 32)|+ T   1 ( n− 1), 
       
     
     where c 1 (n−1) is the previous correlation and T 1 (n−1) is the previous threshold, x(n) is the current input value, n is an index associated with the current input value and the last thirty-two input values are represented as x(n−31), x(n−30), . . . x(n−1), x(n). Using the above equations, it is apparent that there will be a large value for the first correlation c 1 (n) when there is a frame synchronization and a low value when there is no frame synchronization. 
     Referring again to FIG. 6, at step  306 , the first correlation c 1 (n) is compared to the first threshold T 1 (n) to determine if a frame synchronization has occurred. To account for some noise that may corrupt the input values, the first threshold T 1 (n) is multiplied by a constant α, where 0&lt;α&lt;1, to form a modified first threshold αT 1 (n). Preferably, the constant α=0.83. If the first correlation c 1 (n) is greater than the modified first threshold αT 1 (n), then a frame synchronization is declared (step  308 ). As stated above, the declared frame synchronization will be confirmed at step  310 . 
     At step  310  the declared frame synchronization is confirmed by a second correlation c 2 (n) that correlates the input values to the rate info # 1  and rate info # 2  patterns (FIGS.  1  and  2 ). This second correlation c 2 (n) will be compared to a second threshold T 2 (n). The second correlation c 2 (n) and second threshold T 2 (n) are computed as follows:          -       c   2          (   n   )         =       ∑     k   =   0     31                       -     x        (     n   +   32   -   k     )              x        (     n   +   80   -   k     )                     and                   β                     T   2          (   n   )         =       ∑     k   =   0     31                            x        (     n   +   32   -   k     )            x        (     n   +   80   -   k     )                  ,                          
     where 0&lt;β&lt;1. Preferably, β is 0.83. Continuing at step  310 , the second correlation c 2 (n) is then compared to the second threshold T 2 (n) as follows: 
     
       
           −c   2 ( n )&gt;β T   2 ( n ). 
       
     
     If the second correlation c 2 (n) exceeds the threshold, then the declared frame synchronization has been confirmed and the frame is in sync (step  312 ). If the second correlation c 2 (n) does not exceed the second threshold βT 2 (n), then the frame synchronization has not been confirmed and the process  300  continues at step  302  where the next input value is read in. The process  300  continues until there is a declared frame synchronization (i.e., c 1 (n)&gt;αT 1 (n)) and that declared frame synchronization is confirmed (i.e., −c 2 (n)&gt;βT 2 (n)). 
     If at step  306 , the first correlation c 1 (n) is not greater than the first modified threshold αT 1 (n), then a frame synchronization has not occurred and the process  300  continues at step  302  where the next input value is read in. The process  300  continues until there is a declared frame synchronization (i.e., c 1 (n)&gt;αT 1 (n)) and that declared frame synchronization is confirmed (i.e., −c 2 (n)&gt;βT 2 (n)). 
     It has been determined that the above second correlation c 2 (n) and second threshold T 2 (n) computations can be greatly reduced by taking advantage of the knowledge of the bit synchronization patterns within the FLEX protocol data frame (see FIGS.  1  and  2 ). The above second correlation c 2 (n) and second threshold T 2 (n) computations can be reduced to: 
     
       
           c   2 ( n )= c   2 ( n− 1)+ x ( n ) x ( n+ 48)− x ( n+ 32) x ( n+ 80) 
       
     
     and 
     
       
           T   2 ( n )= T   2 ( n− 1)+| x ( n ) x ( n+ 48)− x ( n+ 32) x ( n+ 80)|, 
       
     
     where c 2 (n−1) is the previous computed second correlation and T 2 (n−1) is the previous computed second threshold. 
     The present invention is implemented in software and the software instructions and data can be stored in PROM, EEPROM or other non-volatile memory of the paging device. The program embodying the present invention can be stored on a hard drive, floppy disc, CD-ROM or other permanent or semi-permanent storage medium and subsequently transferred to the memory of the paging device. The program embodying the present invention can also be divided into program code segments, downloaded, for example, from a server computer or transmitted as a data signal embodied in a carrier wave to the paging device as is known in the art. In addition, the present invention can be implemented in hardware or a combination of hardware and software. In particular, the controller of the present invention can be implemented in an application specific integrated circuit (ASIC), a digital signal processor, microcomputer or other processor capable of being programmed to perform the functions of the paging device and the present invention. 
     While the invention has been described in detail in connection with the preferred embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.