Abstract:
A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point.

Description:
FIELD OF DISCLOSURE 
       [0001]    Various embodiments described herein relate to the design of integrated circuits, and more particularly, to the design of three-dimensional integrated circuits. 
       BACKGROUND 
       [0002]    System-on-a-chip (SoC) integrated circuits which include digital, analog, power management or radio frequency (RF) circuit elements have been popular for mobile devices and other electronic devices that have stringent form factor requirements. More recently, three-dimensional integrated circuits (3D ICs) with multiple tiers of dies for placement of circuit elements are being designed for SoC implementations with further reduced chip footprints to allow mobile and other electronic devices to achieve even smaller form factors. In mobile applications and various other applications, it is also often desirable to operate such 3D IC chips with low power consumption which may be achievable by low-power circuit design. In theory, low-power design may be realized by lowering the dynamic power, that is, C·V 2 ·f, where C is the capacitance, V is the voltage, and f is the frequency, as well as the static leakage power, that is, I leak ·V dd , where I leak  is the leakage current and V dd  is the power supply voltage. The dynamic power and the static leakage power may be reduced by reducing the power supply voltage V dd . However, reducing the power supply voltage V dd  results in reduced clock speed and degraded performance. 
         [0003]    Various IC design techniques have been devised in attempts to improve the performance of low-power integrated circuits. Such design techniques include, for example, voltage boosting, deep pipeline, multiple threshold voltages (multi-Vt), and hardware parallelism. However, these design techniques often trade performance with other important metrics such as power and area footprint. For example, raising the power supply voltage V dd  results in an increase in dynamic and leakage power but would contradict the principle of low-power circuit design. Moreover, in advanced technology nodes such as 22 nm or 14 nm nodes, for example, a high power supply voltage V dd  is generally not available. Furthermore, many modern integrated circuits typically have large resistance-capacitance (RC) loads and generally do not respond well to voltage increases. 
         [0004]    Deep pipelining by reducing the logic depth of the pipeline stage is often costly. Performance of circuits designed by using the deep pipelining technique may be hampered by sensitivity to clock skew at high frequencies and insertion delay at critical paths, in addition to power and area penalties due to the insertion of extra flops. Although the multi-Vt technique may alleviate some critical path issues, it may, however, result in increased technological complexity and fabrication cost. Hardware parallelism, on the other hand, may present considerable challenges in instruction coding due to the limit of Amdahl&#39;s Law and may incur area penalties. 
       SUMMARY 
       [0005]    Exemplary embodiments of the disclosure are directed to apparatus and method for dual power swing pipeline design in three-dimensional integrated circuits with separation of combinational and sequential logics. 
         [0006]    In an embodiment, a circuit is provided, the circuit comprising: a first sequential logic element having a logic input, a first power supply input operable to receive a first power supply voltage, and a logic output; a combinational logic element having a logic input coupled to the logic output of the first sequential logic element, a second power supply input operable to receive a second power supply voltage that is lower than the first power supply voltage, and a logic output; and a second sequential logic element having a logic input coupled to the logic output of the combinational logic element, a third power supply input operable to receive the first power supply voltage, and a logic output. 
         [0007]    In another embodiment, a three-dimensional integrated circuit is provided, the three-dimensional integrated circuit comprising: a first tier of circuit elements, comprising: a first sequential logic element having a logic input, a first power supply input operable to receive a first power supply voltage, and a logic output; a second sequential logic element having a logic input, a second power supply input operable to receive the first power supply voltage, and a logic output; and a second tier of circuit elements, comprising: a combinational logic element having a logic input coupled to the logic output of the first sequential logic element, a third power supply input operable to receive a second power supply voltage that is lower than the first power supply voltage, and a logic output coupled to the logic input of the second sequential logic element. 
         [0008]    In another embodiment, a method of operating a three-dimensional integrated circuit having a plurality of tiers is provided, the method comprising: supplying power at a first voltage to a first one of the tiers; supplying power at a second voltage to a second one of the tiers, wherein the second voltage is lower than the first voltage; shifting up a logic level from the second voltage to the first voltage for sequential logic elements in the first tier; and shifting down the logic level from the first voltage to the second voltage for combinational logic elements in the second tier. 
         [0009]    In yet another embodiment, a three-dimensional integrated circuit having a plurality of tiers is provided, the three-dimensional integrated circuit comprising: means for supplying power at a first voltage to a first one of the tiers; means for supplying power at a second voltage to a second one of the tiers, wherein the second voltage is lower than the first voltage; means for shifting up a logic level from the second voltage to the first voltage for sequential logic elements in the first tier; and means for shifting down the logic level from the first voltage to the second voltage for combinational logic elements in the second tier. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The accompanying drawings are presented to aid in the description of embodiments and are provided solely for illustration of the embodiments and not limitations thereof. 
           [0011]      FIG. 1  is a simplified diagram showing an embodiment of a three-dimensional integrated circuit with two tiers. 
           [0012]      FIG. 2  is a simplified diagram showing an embodiment of a three-dimensional integrated circuit having a first tier which includes sequential circuits and a clock network supplied with a relatively high power supply voltage and a second tier which includes combinational circuits supplied with a relatively low power supply voltage. 
           [0013]      FIG. 3A  is a circuit diagram illustrating an embodiment of a logic pipeline in a three-dimensional integrated circuit operating at a relatively low clock rate. 
           [0014]      FIG. 3B  is a circuit diagram illustrating an embodiment of a logic pipeline operating at a relatively high clock rate. 
           [0015]      FIG. 4  is a flowchart illustrating an embodiment of a method of operating a three-dimensional integrated circuit having a plurality of tiers. 
           [0016]      FIG. 5  is a diagram illustrating an example of upshifting and downshifting of the logic voltage level between a relatively low voltage level V dd   _   Low  and a relatively high voltage level V dd  in response to the SET input of a D flip-flop. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Aspects of the disclosure are described in the following description and related drawings directed to specific embodiments. Alternate embodiments may be devised without departing from the scope of the disclosure. Additionally, well-known elements will not be described in detail or will be omitted so as not to obscure the relevant details of the disclosure. 
         [0018]    The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments” does not require that all embodiments include the discussed feature, advantage or mode of operation. 
         [0019]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Moreover, it is understood that the word “or” has the same meaning as the Boolean operator “OR,” that is, it encompasses the possibilities of “either” and “both” and is not limited to “exclusive or” (“XOR”), unless expressly stated otherwise. It is also understood that the symbol “/” between two adjacent words has the same meaning as “or” unless expressly stated otherwise. Moreover, phrases such as “connected to,” “coupled to” or “in communication with” are not limited to direct connections unless expressly stated otherwise. 
         [0020]    In an embodiment, a three-dimensional integrated circuit is provided by using a dual or multiple power supply domain design in combination with deep pipeline for enhanced power-performance-area (PPA) envelope. In an embodiment, a logic pipeline design is provided that includes two separate power domains for sequential and combinational logic functions. In an embodiment, sequential logic is used to control system clock and throughput, whereas combinational logic is used to control overall system power, including dynamic and static power. In an embodiment, three-dimensional partitioning of tiers in a three-dimensional integrated circuit allows for efficient separation of power domains for sequential logic and for combinational logic. In a further embodiment, the tier on which the sequential logic is implemented is supplied with a relatively high power supply voltage (V dd ), whereas the tier on which the combinational logic is implemented is supplied with a relatively low power supply voltage (V dd   _   Low ). 
         [0021]      FIG. 1  is a simplified diagram showing an embodiment of a three-dimensional integrated circuit with two tiers, including a lower tier  102  (Tier  0 ) and an upper tier  104  (Tier  1 ). In an embodiment, the lower tier  102  is supplied with a power supply voltage V dd  whereas the upper tier  104  is supplied with another power supply voltage V dd   _   Low . In an embodiment, the power supply voltage V dd   _   Low  for the upper tier  104  is lower than the power supply voltage V dd  for the lower tier  102 . Although the three-dimensional integrated circuit in the example shown in  FIG. 1  comprises two tiers, namely, Tier  0  and Tier  1 , the principles of the disclosure may also be applicable to other three-dimensional integrated circuits with more than two tiers. For example, in a four-tier three-dimensional integrated circuit, a relatively high power supply voltage V dd  may be applied to Tier  0 , whereas a relatively low power supply voltage V dd   _   Low  may be applied to Tier  1 . 
         [0022]    Although in practical applications, it may be desirable to have a relatively high voltage V dd  supplied to the bottom tier, or Tier  0 , which is the tier of integrated circuits on the bottom die or substrate, it is not mandatory that the relatively high power supply voltage V dd  be supplied to the bottom tier in all embodiments. Furthermore, while it may also be desirable in practical applications to have sequential logic supplied with a relatively high V dd  in one tier and to have combinational logic supplied with a relatively low power supply voltage V dd   _   Low  in an adjacent tier, for example, a tier immediately above the bottom tier which implements the sequential logic, the tiers need not be adjacent to each other if the logic pipelines between the sequential logic and the combinational logic pass through one or more intermediate tiers in the physical design of the three-dimensional integrated circuit. Moreover, inter-tier connections between sequential logic having a relatively high power supply voltage V dd  in one tier and combinational logic having a relatively low power supply voltage V dd   _   Low  in another tier along the logic pipeline may be realized by metal interconnects, pad contacts, inter-tier vias, or various other types of connections, for example. 
         [0023]      FIG. 2  is a simplified diagram showing that Tier  0 , which is supplied with a relatively high power supply voltage V dd , includes sequential circuits  212  and a clock network  214 , whereas Tier  1 , which is supplied with a relatively low power supply voltage V dd   _   Low , includes combinational circuits  216 . In an embodiment, the sequential circuits  212  in Tier  0  include sequential logic elements whereas the combinational circuits  216  in Tier  1  include combinational logic elements. In an embodiment, the clock network  214  and the sequential circuits  212  in Tier  0  control system clock and throughput whereas the combinational circuits  216  in Tier  1  control overall system power including dynamic and static power. In an embodiment, Tier  0  and Tier  1  may also include various types of additional circuit elements other than circuit elements for the sequential circuits  212 , circuit elements for the clock network  214 , and circuit elements for the combinational circuits  216  as illustrated in  FIG. 2 . 
         [0024]      FIG. 3A  is a circuit diagram illustrating an embodiment of a logic pipeline in a three-dimensional integrated circuit operating at a relatively low clock rate, for example, a clock rate of 700 MHz. In  FIG. 3A , the logic pipeline includes a first sequential logic element  302  on Tier  0 , a combinational logic element  304  on Tier  1 , and a second sequential logic element on Tier  0 . As described above, the first and second sequential logic elements  302  and  306  on Tier  0  are supplied with a first power supply voltage V dd , whereas the combinational logic element  304  on Tier  1  is supplied with a second power supply voltage V dd   _   Low , which is lower than the first power supply voltage V dd  for Tier  0 . In an embodiment, the first sequential logic element  302  comprises a flip-flop, whereas the second sequential logic element  306  also comprises a flip-flop. In a further embodiment, the first sequential logic element  302  comprises a first D flip-flop  308 , whereas the second sequential logic element  306  comprises a second D flip-flop  310 , as shown in  FIG. 3A . 
         [0025]    In the embodiment shown in  FIG. 3A , the first D flip-flop  308  has a D input  312  which is coupled to receive a logic input having an input logic voltage level, a SET pin  313 , a CLR pin  315 , and a Q output  316  for outputting a logic output in response to the input logic voltage level received at the D input  312  and the inputs at the SET and CLR pins. In the embodiment shown in  FIG. 3A , the SET pin  313  of the first D flip-flop  308  is applied the voltage V dd  to set the output Q value to logic 1, whereas the CLR pin  315  is used to clear or reset the output Q value to logic 0. The combinational logic element  304  on Tier  1  has a logic input coupled to the Q output  316  of the first D flip-flop  308  on Tier  0 , and also a power supply input  318  coupled to receive the second power supply voltage V dd   _   Low , which is lower than the first power supply voltage V dd . 
         [0026]    In an embodiment, the second D flip-flop  310  on Tier  0  has a D input  320  coupled to the logic output of the combinational logic element  304  on Tier  1 , a SET pin  321 , a CLR pin  323 , and a Q output  324  for outputting a logic output in response to the logic voltage level received from the combinational logic element  304  at the D input  320  and the inputs at the SET and CLR pins  321  and  323 , respectively. In the embodiment shown in  FIG. 3A , the SET pin  321  of the second D flip-flop  310  is applied the voltage V dd  to set the output Q value to logic 1, whereas the CLR pin  323  is used to clear or reset the output Q value to logic 0. The logic operations of the first and second D flip-flops  308  and  310  will be described in further detail below with respect to  FIGS. 4 and 5 . 
         [0027]      FIG. 3B  is a circuit diagram illustrating an embodiment of the logic pipeline operating at a relatively high clock rate, for example, a clock rate of 1 GHz. In  FIG. 3B , the first and second D flip-flops  308  and  310  operate in the same manner as the first and second D flip-flops  308  and  310  in  FIG. 3A , respectively, except that the clock network  214  in Tier  0  (shown in  FIG. 2 ) operates at a higher clock frequency. Referring to  FIG. 3B , the first D flip-flop  308  has a D input  312  coupled to receive an input logic voltage level, a SET pin  313  coupled to receive the first power supply voltage V dd , and a Q output  316  for outputting a logic output to the combinational logic element  326  on Tier  1 . In the embodiment shown in  FIG. 3B , the combinational logic element  326 , which operates at a relatively low power supply voltage V dd   _   Low  but at a relatively high clock rate on Tier  1 , has a reorganized pipeline compared to the combinational logic element  304  operating at a relatively low clock rate on Tier  1  as shown in  FIG. 3A . 
         [0028]    In the embodiment shown in  FIG. 3B , the combinational logic element  326  with reorganized pipeline on Tier  1  has a logic input coupled to the Q output  316  of the first D flip-flop  308  on Tier  0 , and also a power supply input  318  coupled to receive the second power supply voltage V dd   _   Low . In an embodiment, the second D flip-flop  310  on Tier  0  has a D input  320  coupled to the logic output of the combinational logic element  326  with reorganized pipeline on Tier  1 , a SET input  322  which is coupled to receive the first power supply voltage V dd , and a Q output  324  for outputting a logic output in response to the logic voltage level received from the combinational logic element  326  with reorganized pipeline at the D input  320  and the first power supply voltage V dd  received at the SET input  322 . 
         [0029]      FIG. 4  is a flowchart illustrating an embodiment of a method of operating a three-dimensional integrated circuit having a plurality of tiers. A first power supply voltage is supplied to a first tier of the three-dimensional integrated circuit in step  402 . In an embodiment, the first tier is the bottom tier or Tier  0  in a multi-tier three-dimensional integrated circuit, although the first tier may be any one of the tiers in alternate embodiments. Referring to  FIG. 4 , a second power supply voltage is supplied to a second tier of the three-dimensional integrated circuit in step  404 . In an embodiment, the second power supply voltage supplied to the second tier in step  404  is a voltage lower than the first power supply voltage supplied to the first tier in step  402 . In an embodiment, the second tier is the tier positioned immediately above the first tier in a multi-tier three-dimensional integrated circuit, although the second tier may be any one of the tiers other than the first tier in alternate embodiments. 
         [0030]    Referring to  FIG. 4 , the logic voltage level for sequential logic elements in the first tier of the three-dimensional integrated circuit is shifted up in step  406 . In step  408 , the logic voltage level for combinational logic elements in the second tier of the three-dimensional integrated circuit is shifted down. In an embodiment, the logic voltage level for the sequential logic elements in the first tier is shifted up by using at least one flip-flop, such as a D flip-flop  308  or  310  in the first tier  102  (Tier  0 ), as shown in  FIGS. 3A and 3B . 
         [0031]    In an embodiment in which shifting up of the logic voltage level is performed by the first D flip-flop  308 , for example, the power supply voltage V dd  supplied to the SET input  314  of the first D flip-flop shifts up a relatively low input logic voltage level, for example, V dd   _   Low  at the D input  312 , to a relatively high output logic voltage level, for example, V dd , at the Q output  316 . Even if the input logic voltage at the D input  312  is already at a relatively high voltage level, for example, V dd , the voltage V dd  applied to the SET pin  313  ensures that the output logic voltage level at the Q output  316  of the first D flip-flop remains at V dd . If, on the other hand, the relatively high power supply voltage V dd  is no longer supplied to the SET pin  313  of the first D flip-flop  308 , the output logic voltage level at the Q output  316  of the first D flip-flop is shifted down to the relatively low power supply voltage level V dd   _   Low . 
         [0032]    In an embodiment, the second D flip-flop  310  has its D input  320  coupled to the combinational logic elements  304  in relatively low clock rate operations as shown in  FIG. 3A  or the combinational logic elements  326  with reorganized pipeline in relatively high clock rate operations as shown in  FIG. 3B . In an embodiment, the second D flip-flop  310  operates in the same manner as the first D flip-flop  308  described above. The upshifting and downshifting of the logic voltage level between the relatively low voltage level V dd   _   Low  and the relatively high voltage level V dd  in response to the SET input of each D flip-flop is illustrated in  FIG. 5 . 
         [0033]    While the foregoing disclosure shows illustrative embodiments, it should be noted that various changes and modifications could be made herein without departing from the scope of the appended claims. The functions, steps or actions of the method claims in accordance with embodiments described herein need not be performed in any particular order unless expressly stated otherwise. Furthermore, although elements may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.