Abstract:
Disclosed is a method of fabricating a lateral semiconductor device, comprising:  
     providing a substrate, having at least an upper silicon portion forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to the field of semiconductor devices; more specifically, it relates to lateral diodes and lateral bipolar transistors and the method of fabricating said diodes and transistors.  
         BACKGROUND OF THE INVENTION  
         [0002]    In both silicon-on-insulator (SOI), bipolar/complementary metal-oxide-silicon (BICMOS) and SiGe BICMOS technologies there is a need for diodes and non-SiGe bipolar transistors.  
           [0003]    One type of diode available to SOI/CMOS technology is a gated diode. Gated diodes use a dummy gate over the PN junction. The dielectric spacers formed on the sidewalls of the dummy gate prevent the silicide contact process from shorting out the junction. However, gated diodes, especially as the gate oxide becomes thin, can suffer from the problem of the leakage current through the dummy gate being greater than the leakage current through the diode, resulting in excessive power consumption.  
           [0004]    In BICMOS technology there is a need for transistors capable of running at voltages higher than the gate dielectric breakdown voltages of the CMOS transistors. One such need is found in pre-amplifier circuits. One type of bipolar transistor available for BICMOS and SiGe BICMOS technology is a lateral bipolar transistor wherein the base width of the transistor is defined by the CMOS gate process, which also prevents the silicide contact process from shorting out the emitter, base and collector. The emitter and collector are defined by the CMOS source/drain (S/D) dopant processes. However, the resultant bipolar transistor exhibits both FET and bipolar characteristics and is difficult to model.  
           [0005]    A diode and lateral bipolar transistor, fabricated without the use of CMOS gate technology to prevent the junctions of the diode and the emitter, base and collector of the transistor from shorting would result in devices with lower leakages and purer diode and bipolar transistor characteristics and allow voltages to be applied to the diode and lateral bipolar transistor greater than the CMOS device gate dielectric breakdown voltage.  
         SUMMARY OF THE INVENTION  
         [0006]    A first aspect of the present invention is a method of fabricating a lateral semiconductor device, comprising: providing a substrate, having at least an upper silicon portion, forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region  
           [0007]    A second aspect of the present invention is a method of fabricating a lateral diode, comprising: providing a silicon substrate; forming an N-region and a P-region in the substrate, the P-region abutting the N-region and thereby forming a PN junction; and forming a protective island on a top surface of the substrate, the protective island extending the length of the PN junction and overlapping a portion of the N-region and a portion of the P-region.  
           [0008]    A third aspect of the present invention is a method of fabricating a lateral bipolar transistor, comprising: providing a silicon substrate; forming an emitter region, a base region and a collector region in the silicon substrate, the emitter region abutting the base region and thereby forming a first PN junction and the collector region abutting the base region and thereby forming a second PN junction; forming a protective island on the top surface of the silicon substrate, the protective island extending the length of the first PN junction and overlapping a portion of the emitter region and a portion of the base region; and the protective island extending the length of the second PN junction and overlapping a portion of the collector region and a portion of the base region.  
           [0009]    A fourth aspect of the present invention is a method of fabricating a lateral diode, comprising: providing a silicon on insulator substrate comprising a silicon layer over an insulator; forming an N-region and a P-region in the silicon layer, the P-region abutting the N-region and thereby forming a PN junction; and forming a protective island on a top surface of the silicon layer of the substrate, the protective island extending the length of the PN junction and overlapping a portion of the N-region and a portion of the P-region.  
           [0010]    A fifth aspect of the present invention is a method of fabricating a lateral bipolar transistor, comprising: providing a silicon on insulator substrate comprising a silicon layer over an insulator; forming an emitter region, a base region and a collector region in the silicon layer, the emitter region abutting the base region and thereby forming a first PN junction and the collector region abutting the base region and thereby forming a second PN junction; forming a protective island on the top surface of the silicon layer of the substrate, the protective island extending the length of the second PN junction and overlapping a portion of the emitter region and a portion of the base region; and the protective island extending the length of the third PN junction and overlapping a portion of the collector region and a portion of the base region.  
           [0011]    A sixth aspect of the present invention is a lateral semiconductor device, comprising: a substrate, having at least an upper silicon portion; at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.  
           [0012]    A seventh aspect of the present invention is a lateral diode, comprising: a silicon substrate; an N-region and a P-region in the substrate, the P-region abutting the N-region and thereby forming a PN junction; and a protective island on a top surface of the silicon substrate, the protective island extending the length of the PN junction and overlapping a portion of the N-region and a portion of the P-region.  
           [0013]    An eighth aspect of the present invention is a lateral bipolar transistor, comprising: a silicon substrate; an emitter region, a base region and a collector region in the silicon substrate, the emitter region abutting the base region and thereby forming a first PN junction and the collector region abutting the base region and thereby forming a second PN junction; a protective island on the top surface of the silicon substrate, the protective island extending the length of the first PN junction and overlapping a portion of the emitter region and a portion of the base region; and the protective island extending the length of the second PN junction and overlapping a portion of the collector region and a portion of the base region.  
           [0014]    A ninth aspect of the present invention is a lateral diode, comprising: a silicon on insulator substrate comprising a silicon layer over an insulator; an N-region and a P-region in the silicon layer, the P-region abutting the N-region and thereby forming a PN junction; and a protective island on a top surface of the silicon layer of the substrate, the protective island extending the length of the PN junction and overlapping a portion of the N-region and a portion of the P-region.  
           [0015]    A tenth aspect of the present invention is a lateral bipolar transistor, comprising: a silicon on insulator substrate comprising a silicon layer over an insulator; an emitter region, a base region and a collector region in the silicon layer, the emitter region abutting the base region and thereby forming a first PN junction and the collector region abutting the base region and thereby forming a second PN junction; a protective island on the top surface of the silicon layer of the substrate, the protective island extending the length of the second PN junction and overlapping a portion of the emitter region and a portion of the base region; and the protective island extending the length of the third PN junction and overlapping a portion of the collector region and a portion of the base region. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0016]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:  
         [0017]    [0017]FIGS. 1 through 10 are cross-sectional side views illustrating fabrication of a lateral diode and a lateral bipolar transistor according to a first embodiment of the present invention;  
         [0018]    [0018]FIG. 11 is a cross-sectional side view illustrating the lateral diode according to a second embodiment of the present invention;  
         [0019]    [0019]FIG. 12 is a cross-sectional side view illustrating the lateral bipolar transistor according to a second embodiment of the present invention; and  
         [0020]    [0020]FIG. 13 is a top view illustrating the lateral diode and lateral bipolar transistor according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]    The first embodiment of the invention will be described and illustrated showing a lateral diode, a lateral bipolar PNP transistor and a SiGe bipolar transistor fabricated together. It should be understood, however, that the lateral diode, the lateral bipolar PNP transistor and the SiGe bipolar transistor may be fabricated separately or in any combination.  
         [0022]    [0022]FIGS. 1 through 10 are cross-sectional side views illustrating fabrication of a lateral diode and a lateral bipolar transistor according to a first embodiment of the present invention. In FIG. 1, a P-type bulk silicon substrate  100  is provided. Formed on a top surface  105  of silicon substrate  100  is a protective layer  110 . Formed on a top surface  115  of protective layer  110  is a patterned ion implantation (I/I) mask  120 . In one example, protective layer is thermal or chemical vapor deposition (CVD) silicon oxide and is about 50 to 250 Å thick and patterned I/I mask  120  is photoresist.  
         [0023]    In FIG. 2, an N-type I/I is performed. I/I implant mask  120  and protective layer  110  are removed. Top surface  105  of silicon substrate  100  is cleaned. An epitaxial layer  125  grown to form buried N+ regions  130 . A protective lower layer  140  is formed on a top surface  135  of epitaxial layer  125  and an protective upper layer  145  is formed on top of the lower protective layer. In one example, the N-type I/I is about 1E 15  to 2E 16  atm/cm 2  of arsenic implanted at about 20 to 500 Kev, lower layer  140  is silicon oxide about 60 to 80 Å thick and upper layer  145  is silicon nitride about 1000 to 1700 Å thick. Epitaxial layer  125  is about 0.60 to 2.0 microns thick. Epitaxial layer  125  is grown intrinsic but is doped N type by auto-doping and out diffusion from buried N+ regions  130 . In one example, the cleaning of top surface  105  of silicon substrate  100  comprises acid and basic cleans followed by a dry/wet/dry oxidation followed by removal of the oxide layer formed prior to epitaxial growth.  
         [0024]    In FIG. 3, trench isolation  150  is formed in epitaxial layer  125 , the trench isolation recessed and upper layer  145  removed leaving islands of lower layer  140 . Trench isolation  150  is formed by etching a pattern in upper and lower layers  140  and  145 , etching a trench in epitaxial layer  125 , depositing an insulator (e.g. silicon oxide) to fill the trench and then performing a chemical-mechanical-polish (CMP) to remove excess insulator from on top of upper layer  145  and planarize the resulting surface. Trench isolation  150  defines a lateral diode region  155 , a lateral bipolar transistor region  160  and a SiGe bipolar transistor region  165 . In lateral bipolar transistor region  160 , buried N+ region  130  becomes buried isolation  130 A and in SiGe bipolar transistor region  165 , buried N+ region  130  becomes subcollector  130 B.  
         [0025]    In FIG. 4, a reach through I/I is performed to form diffused isolation/base contacts  170 A to intrinsic base  125 A and buried isolation  130 A in lateral bipolar transistor region  160  and to form a diffused collector contact  170 B to buried subcollector  130 B in SiGe bipolar transistor region  165 . In one example, reach through I/I is about 2E 15  to 4E 15  atm/cm 2  of phosphorus implanted at about 70 to 150 Kev.  
         [0026]    In FIG. 5, a P-type isolation I/I is performed to create isolation regions  175  in epitaxial layer  125 , the isolation regions extending into silicon substrate  100 , and a P-region  180  in lateral diode region  155 , near top surface  135  of epitaxial layer  125 . Formation of isolation regions  175  also defines an intrinsic base region  125 A in lateral bipolar transistor region  160  and a collector region  125 B in SiGe bipolar transistor region  165 . In one example, the isolation implant is a three step I/I. The first I/I is about 1E 12  to 1E 14  atm/cm 2  of boron implanted at about 25 to 75 Kev. The second I/I is about 1E 12  to 1E 14  atm/cm 2  of boron implanted at about 100 to 300 Kev. The third I/I is about 1E 12  to 1E 14  atm/cm 2  of boron implanted at about 200 to 600 Kev. The first I/I implant controls the diode characteristics of the diode that will be formed in lateral diode region  155 . Then, an N-type I/I implant is performed to form an N+−region  185  in lateral diode region  155 . In a first example, the N-type I/I is about 1.5E 15  to 4E 5  atm/cm 2  of phosphorus implanted at about 5 to 25 Kev. In a second example, the N-type I/I is about 1E 14  to 1E 16  atm/cm 2  of arsenic implanted at about 0.5 to 50 Kev.  
         [0027]    In FIG. 6, an emitter and base for an NPN SiGe bipolar transistor is formed in SiGe bipolar transistor region  165  by processes known to one skilled in the art. Briefly those processes include: forming an opening in lower layer  140 , forming an intrinsic SiGe layer over the opening in lower layer  140 , performing a P-type I/I to define an extrinsic base region  195 , an intrinsic base region  200 , forming a patterned dielectric layer  205  over the intrinsic base region, and depositing polysilicon silicon followed by an N-type ion implant to form a poly-crystalline emitter  210  and an emitter contact  215 . The N-type polysilicon auto-dopes emitter  210  N-type.  
         [0028]    In FIG. 7, a P-type I/I is performed to form a P+ contact region  220  to P-region  180  in lateral diode region  155  and an emitter  225  and a collector  230  in lateral bipolar transistor region  160 . In one example, the P-type I/I is about 11E 14  to 4E 15  atm/cm 2  of boron implanted at about 7 to 15 Kev.  
         [0029]    In FIG. 8, lower layer  140  is removed. A rapid thermal anneal (RTA) is performed under 6% O 2  in N 2  to grow about 10 to 20 Å of thin oxide on exposed silicon surfaces. In one example, about 150 to 500 Å of silicon nitride is deposited by CVD and patterned to form protective islands  235 . Protective islands  235  may also be formed from silicon nitride or silicon nitride over silicon oxide, silicon carbide or any insulator capable of withstanding 700° C. Protective islands  235  extend the entire length of the P-region  180 /N+−region  185  PN junction and partially overlap the P-region and the N+−region. Protective islands  235  extend the entire length of the emitter  225 /intrinsic base  125 A PN junction and partially overlap the emitter and the base. Protective islands  235  extend the entire length of the collector  230 /intrinsic base  125 A PN junction and partially overlap the collector and the base. Spacers  240 , in SiGe bipolar transistor region  165  may be formed at the same time protective islands  235  are formed or may be formed in a separate process step.  
         [0030]    In FIG. 9, the thin oxide layer formed by RTA described above is removed and silicide contacts  245  are formed. Silicide contacts  245  are formed in N+−region  185  P+ and P+ contact region  220  in lateral diode region  155 . Silicide contacts  245  are formed in emitter  225 , collector  230  and diffused isolation/base contacts  170 A in lateral bipolar transistor region  160 . Silicide contacts  245  are formed in diffused collector contact  170 B, extrinsic base region  195  and emitter contact  215  in SiGe bipolar transistor region  165 . Silicide contacts  245  may be formed by depositing about 400 to 500 Å of titanium or cobalt and annealing at 700° C. under N 2  to form titanium silicide or cobalt silicide respectively. Unreacted titanium or cobalt is removed by wet etching.  
         [0031]    In FIG. 10, an interlevel dielectric layer  250  has been formed on substrate  100  and vias  255  formed in the interlevel dielectric layer contacting silicide contacts  245 . Vias  255  may be formed by etching holes in interlevel dielectric layer  250  down to silicide contacts  240 , depositing a conductor material to fill the hole and performing a CMP process to remove excess conductive material from the surface of the interlevel dielectric layer. In one example, vias  255  comprise tungsten.  
         [0032]    [0032]FIG. 11 is a cross-sectional side view illustrating the lateral diode according to a second embodiment of the present invention. In FIG. 11, the lateral diode of the present invention is fabricated in a silicon-on-insulator (SOI) substrate  260 . SOI substrate comprises a silicon substrate  265  and a buried oxide layer (BOX)  270  formed between the silicon substrate and an upper, thin silicon layer  275 . Formed in thin silicon layer  275  is trench isolation  150  reaching down to BOX layer  270 . Formed between trench isolation  150  in thin silicon layer is a lateral diode comprising: P-region  180  and N+−region  185 . P+ contact region  220  is formed in P region  180 . Protective islands  235  are formed between and partially overlapping the P-region  180 /N+−region  185 . Silicide contacts  245  are formed in N+−region  185  P+ and P+ contact region  220 . Vias  255  formed in interlevel dielectric layer  250  contact silicide contacts  245 .  
         [0033]    [0033]FIG. 11 illustrates a fully depleted diode, in that P-region  180 ,and N+−region  185  and P+ contact region  220  reach down to BOX  270 . In the fully depleted case, thin silicon layer  275  would be less than 0.15 microns thick. In a partially depleted diode N+−region  185  and P+ contact region  220  would not reach down to BOX  270 . In the partially depleted case, thin silicon layer  275  would be greater than 0.15 microns thick.  
         [0034]    Fabrication of the lateral diode illustrated in FIG. 11 is similar to the process illustrated in FIGS. 1 through 10 and described above with the exceptions that no epitaxial layer is required and what was the isolation I/I is modified to a one-step tailoring implant if performed at all. The tailor I/I is about 1E 12  to 1E 14  atm/cm 2  of boron implanted at about 25 to 75 Kev.  
         [0035]    [0035]FIG. 12 is a cross-sectional side view illustrating the lateral bipolar transistor according to a second embodiment of the present invention. In FIG. 13, the lateral bipolar transistor of the present invention is fabricated in SOI substrate  260 . SOI substrate comprises silicon substrate  265  and BOX layer  270  formed between the silicon substrate and upper, thin silicon layer  275 . Formed in thin silicon layer  275  is trench isolation  150  reaching down to BOX layer  270 . Formed between trench isolation  150  in thin silicon layer is a lateral bipolar transistor comprising: emitter  225 , intrinsic base  125 A, collector  230  and base contacts  170 A. Diffused base contact  170 A are formed between trench isolation  150  and collector  230 . Protective islands  235  are formed between and partially overlap emitter  225  and collector  230 . Protective islands  235  are formed between and partially overlap collector  230  and diffused base contact  170 A. Silicide contacts  245  are formed in emitter  225 , collector  230  and diffused isolation/base contacts  170 A. Vias  255  formed in interlevel dielectric layer  250  contact silicide contacts  245 .  
         [0036]    [0036]FIG. 12 illustrates a partially depleted bipolar transistor, in that emitter  225 , collector  230  and diffused base contacts  170 A do not reach down to BOX  270 . In the partially depleted case, thin silicon layer  275  is greater than 0.15 microns thick.  
         [0037]    Fabrication of lateral bipolar transistor illustrated in FIG. 12 is similar to the process illustrated in FIGS. 1 through 10 and described above with the exceptions that no epitaxial layer is required and the isolation I/I is not needed and thus not performed.  
         [0038]    [0038]FIG. 13 is a top view illustrating the lateral diode and lateral bipolar transistor according to the present invention. In FIG. 13, a lateral diode  295  is surrounded by trench isolation  150 . Within trench isolation  150  is P-region  180  and N+−region  185 . P+ contact region  220  is within P-region  180 . Protective island  235  (cross-hatched) extends the length of the P-region  180  and N+−region  185  PN junction and partially overlaps the P-region and the N+−region. Silicide contacts  245  in N+−region  185  P+ and P+ contact region  220  are contacted by vias  255 .  
         [0039]    Also, in FIG. 13, a lateral bipolar transistor  300  according to the first embodiment is surrounded by trench isolation  150 . Within trench isolation  150  is a shallow trench isolation ring  150 A. Within ring  150 A is emitter  225 , intrinsic base  125 A and collector  230 . Protective island  235  (cross-hatched) extends the entire length of the emitter  225 /intrinsic base  125 A PN junction and partially overlaps the emitter and the base. Protective island  235  also extends the entire length of the collector  230 /intrinsic base  125 A boundary and partially overlaps the collector and the base. Silicide contacts  245  in emitter  225 , collector  230  and diffused base contacts  170 A are contacted by vias  255 .  
         [0040]    In the second embodiment, ring  150 A is not present and a second protective island in the form of a ring is formed between collector  230  and diffused base contacts  170 A.  
         [0041]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. For example, fabrication of the lateral bipolar transistor has been illustrated and described using a PNP bipolar transistor. A NPN bipolar transistor may be similarly fabricated. Additionally, the lateral diode and lateral bipolar transistor may be fabricated in combination with complementary metal-oxide-silicon (CMOS) transistors. Further, while a ring type diode and a ring type bipolar transistor have been illustrated in FIG. 13 and described above, linear diodes and linear lateral bipolar transistors may be fabricated as well.  
         [0042]    It is also apparent that process steps may be consolidated. For example, protective layer  110  may also be used to formed sidewall spacers on CMOS transistors. Additionally, the protective islands may be used to form other types of devices, such as resistors, by not forming P+ contact region  220  and adjusting the doping level of P-region  180 . Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.