Abstract:
Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

Description:
BACKGROUND 
       [0001]    The invention relates generally to semiconductor device fabrication and, in particular, to methods for fabricating a metal-insulator-metal (MIM) capacitor and structures for a MIM capacitor. 
         [0002]    On-chip passive elements, such as MIM capacitors, are deployed in many types of integrated circuits, such as radiofrequency integrated circuits (RFICs), and may be integrated into one or more of the metallization levels of the BEOL interconnect structure using the BEOL metallurgy. The BEOL interconnect structure is routinely fabricated by damascene processes. For example, in a dual damascene process, vias and trenches are etched in one or more dielectric layers using reactive ion etching (RIE) and are simultaneously filled with a plugs and wiring using a single blanket deposition of a conductor and planarization. The process of dielectric deposition, via and trench etch, conductor deposition, and planarization is replicated to generate stacked metallization levels of the BEOL interconnect structure. 
         [0003]    A MIM capacitor is a stacked structure formed in the BEOL interconnect structure. A two-electrode MIM capacitor includes planar top and bottom conductive plates, which operate as electrodes, and an interplate dielectric layer disposed between the top and bottom conductive plates as an electrical insulator. The capacitance, or amount of charge held by the MIM capacitor per applied voltage, depends upon the area of the top and bottom conductive plates, their separation, and the dielectric constant of the material constituting the interplate dielectric layer. 
         [0004]    Improved methods are needed for fabricating MIM capacitors, as well as improved structures for MIM capacitors. 
       BRIEF SUMMARY 
       [0005]    In an embodiment of the invention, a method is provided for fabricating a metal-insulator-metal (MIM) capacitor. The method includes depositing an interlayer dielectric (ILD) layer having a top surface and forming a plurality of apertures each bounded by a plurality of sidewalls extending from the top surface of the ILD layer into the ILD layer. A layer stack, which includes a bottom electrode layer and a capacitor dielectric layer, is deposited on the top surface of the ILD layer and the sidewalls bounding each of the apertures. The method further includes forming a block mask that covers a first surface area of ILD layer including the apertures and that exposes a second surface area of the ILD layer surrounding the first surface area. The layer stack is removed from the second surface area to define a perimeter of the layer stack. 
         [0006]    In an embodiment of the invention, a metal-insulator-metal (MIM) capacitor includes an interlayer dielectric (ILD) layer having a top surface and a plurality of apertures each bounded by a plurality of sidewalls extending from the top surface of the ILD layer into the ILD layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0007]    The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. 
           [0008]      FIG. 1A  is a top view of a portion of a substrate at an initial fabrication stage of a processing method for fabricating a device structure in accordance with an embodiment of the invention. 
           [0009]      FIG. 1B  is a cross-sectional view taken generally along line  1 B- 1 B of  FIG. 1A . 
           [0010]      FIG. 2A  is a top view of the substrate portion of  FIG. 1A  at a subsequent fabrication stage of the processing method. 
           [0011]      FIG. 2B  is a cross-sectional view taken generally along line  2 B- 2 B of  FIG. 2A . 
           [0012]      FIG. 3A  is a top view of the substrate portion of  FIG. 2A  at a subsequent fabrication stage of the processing method. 
           [0013]      FIG. 3B  is a cross-sectional view taken generally along line  3 B- 3 B of  FIG. 3A . 
           [0014]      FIG. 4A  is a top view of the substrate portion of  FIG. 3A  at a subsequent fabrication stage of the processing method. 
           [0015]      FIG. 4B  is a cross-sectional view taken generally along line  4 B- 4 B of  FIG. 4A . 
           [0016]      FIG. 5A  is a top view of the substrate portion of  FIG. 4A  at a subsequent fabrication stage of the processing method. 
           [0017]      FIG. 5B  is a cross-sectional view taken generally along line  5 B- 5 B of  FIG. 5A . 
           [0018]      FIG. 6  is a cross-sectional view similar to  FIG. 1B  at an initial fabrication stage of a MIM capacitor constructed in accordance with an alternative embodiment of the invention. 
           [0019]      FIG. 7  is a cross-sectional view similar to  FIG. 5B  of a MIM capacitor in accordance with an alternative embodiment of the invention. 
           [0020]      FIG. 8  is a cross-sectional view similar to  FIG. 5B  of a MIM capacitor in accordance with an alternative embodiment of the invention. 
           [0021]      FIG. 9  is a cross-sectional view similar to  FIG. 5B  of a MIM capacitor in accordance with an alternative embodiment of the invention. 
           [0022]      FIG. 9A  is a cross-sectional view similar to  FIG. 9  taken in a slotted opening between adjacent via bars. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    With reference to  FIGS. 1A ,  1 B and in accordance with an embodiment of the invention, a back-end-of-line (BEOL) interconnect structure, generally indicated by reference numeral  10 , includes a dielectric layer  12  constituting an interlayer dielectric (ILD) of a metallization level (M x ), conductive wiring features  16 ,  18  embedded in the dielectric layer  12  of metallization level (M x ), and a dielectric layer  14  constituting an interlayer dielectric (ILD) of a metallization level (M x+1 ). Additional metallization levels (not shown) may exist below the metallization level (M x ). Typical constructions for the BEOL interconnect structure  10  may consist of about two (2) to about eight (8) metallization levels. The metallization levels of the BEOL interconnect structure  10  are formed by known techniques characteristic of damascene processes conventionally associated with BEOL processing. The dielectric layers  12 ,  14  provide physical and electrical separation between different metallization levels. 
         [0024]    The dielectric layers  12 ,  14  of the BEOL interconnect structure  10  may be comprised of any suitable organic or inorganic electrical insulator or dielectric material recognized by a person having ordinary skill in the art. Candidate inorganic dielectric materials may include, but are not limited to, silicon dioxide (SiO 2 ), fluorine-doped silicon glass (FSG), and combinations of these dielectric materials. Alternatively, the dielectric material of dielectric layers  12 ,  14  may be characterized by a relative permittivity or dielectric constant smaller than the dielectric constant of silicon dioxide, which is about 3.9. Candidate low-k dielectric materials include, but are not limited to, porous and nonporous spun-on organic low-k dielectrics, such as spin-on aromatic thermoset polymer resins like polyarylenes, porous and nonporous inorganic low-k dielectrics like organosilicate glasses, hydrogen-enriched silicon oxycarbide (SiCOH), and carbon-doped oxides, and combinations of these and other organic and inorganic dielectrics. The dielectric layers  12 ,  14  may be deposited by any number of well known conventional techniques such as sputtering, spin-on application, chemical vapor deposition (CVD) process or a plasma-enhanced CVD (PECVD) process. 
         [0025]    An etch stop layer  20  is optionally disposed between the dielectric layers  12 ,  14 . The etch stop layer  20  may be comprised of any organic or inorganic dielectric material that is an electrical insulator and that etches selectively to the dielectric material forming the dielectric layer  12 . For example, the etch stop layer  20  may be a thin film comprised of porous or non-porous hydrogen-enriched silicon oxycarbide (SiCOH), also known as organosilicate glass (OSG) or carbon doped oxide (CDO), and having a dielectric constant of about 3.0 or less. The composition and properties of such inorganic low-k dielectric materials may vary contingent upon the selection of deposition conditions and source gases. The etch stop layer  20  may be comprised of other low-k dielectric materials, such as or methyl silsesquioxane polymer (MSQ), or from materials like silicon oxycarbonitride (SiOCN), silicon nitride (Si 3 N 4 ), silicon carbonitride (SiCN), or silicon carbide (SiC). The etch stop layer may be deposited on the top surface  13  of dielectric layer  12  by, for example, CVD or PECVD. 
         [0026]    The conductive wiring features  16 ,  18  of the BEOL interconnect structure  10  may be comprised of a metal such as copper, aluminum, or an alloy of these metals. In the representative construction, the conductive wiring feature  16  is not solid metal, but is instead cheesed with metal portions removed and replaced by dielectric material from dielectric layer  12 . 
         [0027]    The BEOL interconnect structure  10  is carried on a die or chip (not shown) that has been processed by front-end-of-line (FEOL) processes, such as a complementary metal-oxide-semiconductor (CMOS) process, to fabricate one or more integrated circuits that contain device structures. Conductive features in the different metallization levels interconnect devices of the integrated circuit and may provide circuit-to-circuit connections, or may establish contacts with input and output terminals. The chip may be formed from any suitable wafer of semiconductor material that a person having ordinary skill in the art would recognize as suitable for integrated circuit fabrication. 
         [0028]    Multiple openings or apertures  22  are formed in a region, generally indicated with reference numeral  23 , of the dielectric layer  14  that will be used to form the MIM capacitor. The apertures  22  in the MIM capacitor region  23  may be formed by patterning the constituent dielectric material using conventional lithography and etch operations characteristic of a damascene process. To that end, a resist layer (not shown) is applied to a top surface  21  of dielectric layer  14 , exposed to radiation to impart a latent image of a hole pattern, and developed to transform the latent image into a final image pattern with laterally dispersed surface areas of dielectric layer  14  unmasked at the intended sites of apertures  22 . Unmasked regions of dielectric layer  14  at these intended sites are removed with an etching process, such as reactive ion etching (RIE), capable of producing substantially vertical sidewalls  25  bounding apertures  22 . The RIE process stops on etch stop layer  20  and, then, the chemistry of the RIE process is modified to extend the apertures  22  through the etch stop layer  20  to a top surface  13  of dielectric layer  12 . The apertures  22  may have an array arrangement, as depicted in the representative embodiment. The apertures  22  may be square, rectangular, or any other geometrical shape as comprehended by a person having ordinary skill in the art, and may have a cross-sectional area measured in a direction normal to the top surface  13 . 
         [0029]    The apertures  22  penetrate into the dielectric layer  14  and etch stop layer  20  in the MIM capacitor region  23 . At least one of the apertures  22  lands either partially or totally on the conductive wiring feature  16  and, preferably, all of the apertures  22  land either partially or totally on the conductive wiring feature  16 . The apertures  22  parse the dielectric material in the MIM capacitor region  23  into parallel lines  24  of the dielectric material of dielectric layer  14  that are aligned orthogonal to other parallel lines  26  of dielectric layer  14 . The parallel lines  24 ,  26  have a grid-like arrangement because the apertures  22  in the representative embodiment are arranged in rows and columns of an array. The thickness of the residual lines  24 ,  26  may be equal to the physical layer thickness of the dielectric layer  14 . The sidewalls  25  of dielectric material of the residual lines  24 ,  26 , which peripherally bound the apertures  22 , may extend from the top surface  21  of dielectric layer  14  to the top surface  13  of dielectric layer  12  such that the apertures  22  perforate the dielectric layer  14 . 
         [0030]    Vias  28  of metallization level (M x ) may be formed in the dielectric layer  14  and etch stop layer  20  outside of the area in which the apertures  22  are formed. Each of the vias  28  may land on one of the conductive wiring features  18 . In one embodiment, the patterned resist layer used to form the apertures  22  may be a via mask that further includes windows used to form the vias  28 . Hence, the same via mask and the same lithography and etch operations may be used to form the vias  28  of metallization level (M x ) and the apertures  22 . In the representative embodiment, the dimension and pitch of the vias  28  is identical to the dimension and pitch of the apertures  22 . However, the dimensions and pitch of the vias  28  may be selected independently of the dimensions and pitch of the apertures  22  so that the dimensions and pitch are not identical. 
         [0031]    With reference to  FIGS. 2A ,  2 B in which like reference numerals refer to like features in  FIGS. 1A ,  1 B and at a subsequent fabrication stage, layers  30 ,  32  are serially formed to define a layer stack. Layer  30  is initially deposited and is preferably conformally deposited with a physical layer thickness that remains approximately constant independent of the geometry of underlying features. Layer  30  coats the top surface  21  of the dielectric layer  14 , the sidewalls  25  bounding the apertures  22 , and the areas of the top surface  13  of dielectric layer  12  and conductive wiring feature  16  exposed at the base of each aperture  22 . Layer  30  directly contacts the conductive wiring feature  16  at the base of each aperture  22  to establish a physical and electrical connection between layer  30  and the conductive wiring feature  16 . 
         [0032]    After layer  30  is formed, layer  32  is deposited and is preferably conformally deposited with a physical layer thickness that remains approximately constant independent of the geometry of underlying features. Layer  32  coats a top surface  34  of the layer  30 , which is disposed between layer  32  and the dielectric material of dielectric layers  12 ,  14  and conductive wiring feature  16 . Layer  32  indirectly coats the top surface  21  of dielectric layer  14 , the sidewalls  25  bounding the apertures  22 , and the areas of the top surface  13  of dielectric layer  12  and conductive wiring feature  16  exposed at the base of each aperture  22 . 
         [0033]    Layer  30  is comprised of one or more conductive materials, such as titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), tungsten (W), tungsten nitride (WN), ternary refractory metals like titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or tungsten silicon nitride (WSiN). Each conductive material of layer  30  may be deposited by, for example, direct current (DC) sputtering or radio frequency (RF) sputtering. Alternatively, layer  30  may contain multi-layered combinations of these materials, such as either Ti clad with TiN or Ta clad with TaN. 
         [0034]    Layer  32  may be comprised of one or more dielectric materials deposited by atomic layer deposition (ALD), CVD, or another conventional deposition technique. The capacitance of a MIM capacitor generally scales with the dielectric constant of the dielectric material of layer  32 . The dielectric material comprising layer  32  may be SiO 2  or Si 3 N 4 . Alternatively, the dielectric material selected for layer  32  may be a high-k dielectric having a dielectric constant (e.g., permittivity) higher than the dielectric constant of SiO 2 . In particular, candidate high-k dielectrics for layer  32  may have a dielectric constant greater than 10 and, preferably, a dielectric constant in a range of 10 to 100. Air, which is an accepted reference point for values of dielectric constant, has a dielectric constant of approximately unity. Suitable high-k dielectrics for layer  32  include, but are not limited to, aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), tantalum pentoxide (Ta 2 O 5 ), lanthanum oxide (La 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO), yttrium oxide (Y 2 O 3 ), strontium oxide (SrO), or strontium titanium oxide (SrTiO), a hafnium-based dielectric material like hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), or nitrided hafnium silicate (HfSiON), layered stacks of these materials and other dielectric materials, mixtures of these materials, and other like materials. 
         [0035]    With reference to  FIGS. 3A ,  3 B in which like reference numerals refer to like features in  FIGS. 2A ,  2 B and at a subsequent fabrication stage, a block mask  36  is applied in the MIM capacitor region  23  that contains the apertures  22  and residual lines  24 ,  26  of dielectric layer  14 . In areas outside of the MIM capacitor region  23 , a RIE process is used to subtractively etch the layers  30 ,  32  from exposed portions of the top surface  21  of the dielectric layer  14 . The etch chemistry may be adjusted during the RIE process to selectively remove each of the layers  30 ,  32 . 
         [0036]    The block mask  36  preserves the integrity of the layers  30 ,  32  in the MIM capacitor region  23  during the RIE process and defines an outer perimeter  35  for the preserved portions of layers  30 ,  32 . Although the process forming the MIM capacitor requires an additional block mask  36 , the block mask  36  is not needed at a critical mask level where the feature sizes and spaces are designed to the minimum capability of the available lithographic resolution and overlay abilities (tools and processes). Instead, the block mask  36  is a non-critical mask where feature sizes and spaces are larger than the minimum lithographic capability. As a result, extensive measurement and control over the block mask  36  is not required because the processes involved in the subtractive removal of the layers  30 ,  32  outside of the masked MIM capacitor region  23  do not have to be controlled tightly. 
         [0037]    With reference to  FIGS. 4A ,  4 B in which like reference numerals refer to like features in  FIGS. 3A ,  3 B and at a subsequent fabrication stage, the block mask  36  ( FIGS. 3A ,  3 B) is removed by, for example, chemical stripping or a plasma ashing process. A dielectric layer  38  is deposited on the top surface  13  of dielectric layer  14 . The dielectric layer  38  may be formed of the same or different dielectric materials as dielectric layers  12 ,  14 . 
         [0038]    A conventional lithography and etch operation is used to form trenches  40 ,  42 ,  44  in the dielectric material of the dielectric layer  38 . Trenches  40 ,  42  may be aligned with the vias  28 . Trench  44  may be aligned with the MIM capacitor region  23  over which the apertures  22  and the residual lines  24 ,  26  of dielectric layer  14  are coated by layers  30 ,  32 . In the lithography operation, a resist layer (not shown) is applied to cover a top surface  37  of the dielectric layer  38 , exposed to impart a latent image pattern, and developed to transform the latent image pattern into a final image pattern having unmasked areas at the intended locations for the trenches  40 ,  42 ,  44 . The dielectric layer  38  is etched with an etching process, such as RIE, using the patterned resist as an etch mask to localize the trenches  40 ,  42 ,  44 . After the etching process concludes, residual resist is stripped by, for example, oxygen plasma ashing or chemical stripping. 
         [0039]    A liner layer  46  is applied that conformally coats the apertures  22 , vias  28 , and trenches  40 ,  42 ,  44 , as well as coats the top surface  37  of dielectric layer  38 . The liner layer  46  may be comprised of any conductive material or multilayer combination of conductive materials recognized by a person having ordinary skill in the art. Liner layer  46  may comprise a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), ruthenium (Ru), a tantalum-ruthenium alloy (TaRu), tungsten (W), tungsten nitride (WN), chromium (Cr), niobium (Nb), or another suitable conductive material or layered combination of conductive materials. The properties of the conductive material are suitable to operate as a diffusion barrier and an adhesion promoter for a subsequent metal plating operation used to fill the apertures  22 , vias  28 , and trenches  40 ,  42 ,  44 . The liner layer  46  may be deposited, for example, by conventional deposition processes well known to those skilled in the art, including but not limited to physical vapor deposition (PVD), ionized-PVD (iPVD), ALD, plasma-assisted ALD, CVD, or PECVD. 
         [0040]    With reference to  FIGS. 5A ,  5 B in which like reference numerals refer to like features in  FIGS. 4A ,  4 B and at a subsequent fabrication stage, conductive lines  48 ,  50 ,  52  are formed as wiring features in the open volumes inside the trenches  40 ,  42 ,  44 , respectively, and conductive plugs  51  are formed in the open volumes inside the vias  28 . Conductive lines  48 ,  50 ,  52  and conductive plugs  51  are comprised of a conductor such as copper (Cu), aluminum (Al), binary alloys such as AlCu, and other similar metals. The conductor may be deposited as a blanket layer by a conventional deposition process, such as an electrochemical process like electroplating or electroless plating. Before the performance of an electrochemical process, a thin seed layer (not shown) may be deposited on the trenches  40 ,  42 ,  44  and vias  28  by CVD or PVD to facilitate the electrochemical formation of the conductive lines  48 ,  50 ,  52 . 
         [0041]    A chemical-mechanical polishing (CMP) process is used to remove excess liner material and conductor from the top surface  37  of dielectric layer  38  and to planarized the conductive lines  48 ,  50 ,  52  flush with the top surface  37  of dielectric layer  38 . Conductive lines  48 ,  50  are electrically and physically connected by the conductive plugs  51  with the conductive wiring features  18  in dielectric layer  12 . 
         [0042]    Additional metallization levels and via levels (not shown) may be stacked above the M x+1  level and may be fabricated by deposition, lithography, and etching operations similar to those described above for forming the M x+1  level. 
         [0043]    Layer  30  in the MIM capacitor region  23  functionally defines a bottom plate or electrode  56  of a MIM capacitor  54 . Liner layer  46  in the MIM capacitor region  23  functionally defines a top plate or electrode  58  of the MIM capacitor  54 . The conductive line  52  is electrically and physically connected with the top electrode  58 . The layer  32  of dielectric material interposed between liner layer  46  and layer  30  forms an insulative capacitor dielectric  57 , which functions to electrically insulate the top electrode  58  from the bottom electrode  56 . The MIM capacitor region  23  and the conductive wiring feature  16  may be positioned relative to each other such that one or more peripheral edges  31  of the conductive wiring feature  16  are disposed inside the lateral boundary of the bottom electrode  56  at the level of the top surface  13  of dielectric layer  12  and/or such that one or more peripheral edges  33  are disposed outside of the lateral boundary of the bottom electrode  56  at the level of the top surface  13  of dielectric layer  12 . 
         [0044]    The superjacent layers  30 ,  32 ,  46  provide a layer stack that coats the top surface  21  of the dielectric layer  14  in the MIM capacitor region  23 , as well as the sidewalls  25  bounding the apertures  22  and the areas of the top surface  13  of dielectric layer  12  and conductive wiring feature  16  exposed at the base of each aperture  22 . The bottom and top electrodes  56 ,  58  and the capacitor dielectric  57  have a three-dimensional, non-planar topology that increases the effective plate area of the MIM capacitor  54  and, therefore, increases the capacitance of the MIM capacitor  54  while presenting a compact footprint within the MIM capacitor region  23 . The layers  30 ,  32 ,  46  conform to the topology of the underlying patterned dielectric layer  14 . 
         [0045]    The capacitance of the MIM capacitor  54  is proportional to the overlapping surface area of the bottom and top electrodes  56 ,  58 . The topology provided by the apertures  22  in the MIM capacitor region  23  of the dielectric layer  14  increases the capacitance density in the MIM capacitor  54 , which reduces the surface area required to achieve a needed capacitance value in comparison with conventional MIM capacitor structures. In one embodiment, the areal reduction for an equivalent capacitance value may be as large as 50%. The construction of the MIM capacitor  54  may overcome difficulties between electrode and plate integration, may reduce defect density by reducing difficulties experience with electrode and plate integration, may improve capacitor reliability, and may reduce cost by replacing one or more critical masks with a non-critical mask, namely block mask  36 . 
         [0046]    In use, either the top electrode  58  or the bottom electrode  56  may be electrically connected to power and the other of the top electrode  58  or the bottom electrode  56  may be electrically connected to ground. For example, the top electrode  58  may be electrically connected to V DD  and the bottom electrode  56  may be electrically connected to V SS . 
         [0047]    With reference to  FIG. 6  in which like reference numerals refer to like features in  FIG. 1B  and in accordance with an alternative embodiment, the shape of the residual lines  24 ,  26  in the MIM capacitor region  23  may be modified before the layers  30 ,  32  are deposited. The shape modification may operate to reduce any potential issues with the corners of the residual lines  24 ,  26 . 
         [0048]    In one embodiment, spacers  60  are formed on the residual lines  24 ,  26  of the dielectric layer  14  as a shaper modifier before the layers  30 ,  32  are deposited. The spacers  60  may be formed on the sidewalls  25  of residual lines  24 ,  26  by a conventional spacer formation process. For example, the spacers  60  may be formed by depositing a conformal layer of an electrically insulating material, such as a thickness of Si 3 N 4  deposited by CVD, and anisotropic etching the conformal layer to preferentially remove the electrically insulating material from horizontal surfaces. In an alternative embodiment, the spacers  60  may be formed directly using a PECVD process. The spacers  60  round the corners of the sidewalls  25  associated with the residual lines  24 ,  26 . 
         [0049]    In one embodiment, a conformal insulating layer  62  comprised of a dielectric material may be deposited across the residual lines  24 ,  26 . The conformal insulating layer  62  is added as a shaper modifier before the layers  30 ,  32  are deposited and, in the representative embodiment, after the spacers  60  are formed. The conformal insulating layer  62  may be comprised of SiO 2  deposited by CVD using tetraethylorthosilicate (TEOS)/ozone, Al 2 O 3  deposited by ALD, SiO 2  or Si 3 N 4  deposited with LPCVD, etc. The conformal insulating layer  62  further rounds the corners of sidewalls  25  associated with the residual lines  24 ,  26 . 
         [0050]    In an alternative embodiment, the spacers  60  may be omitted and only the conformal insulating layer  62  may be applied on the residual lines  24 ,  26  in the MIM capacitor region  23  as a shaper modifier. In another alternative embodiment, the conformal insulating layer  62  may be omitted and only the spacers  60  may be applied on the residual lines  24 ,  26  in the MIM capacitor region  23  as a shaper modifier. 
         [0051]    With reference to  FIG. 7  in which like reference numerals refer to like features in  FIG. 5B  and in accordance with an alternative embodiment, the top electrode of the MIM capacitor  54  may be formed by depositing a layer  66  on layer  32  before the block mask  36  is formed. Layer  66  may be comprised of the same conductive materials and formed by the same deposition techniques as layer  30 . Processing continues by removing regions of layers  30 ,  32 ,  66  that are not protected by the block mask  36  ( FIGS. 2A ,  2 B), and then with the process flow described above ( FIGS. 3A ,  3 B- 5 A,  5 B) resulting in the final structure shown in  FIG. 5B . 
         [0052]    With reference to  FIG. 8  in which like reference numerals refer to like features in  FIG. 5B  and in accordance with an alternative embodiment, the bottom and top electrodes  56 ,  58  of the MIM capacitor  54  may be contacted from above with conductive features in metallization level (M x+1 ). As a consequence, the conductive wiring feature  16  may be omitted from a location in dielectric layer  12  beneath the MIM capacitor region  23 . 
         [0053]    A peripheral strip  63  of layer  30  is exposed by trimming layer  32  and layer  66  is trimmed to provide a lateral spacing of layer  66  from the peripheral strip  63  of layer  30 . The layer trimming requires two critical masks and conventional lithography and etching processes to produce the tiered side edges that promote the establishment of electrical contact with the peripheral strip  63  of layer  30 . Specifically, an initial patterned resist layer (not shown) is formed on layer  66  and a RIE process is used to trim the edge of layer  66 . After the initial resist layer is removed, another patterned resist layer (not shown) is formed on layers  32 ,  66  and a RIE process is used to trim the edge of layer  32  and expose the peripheral strip  63  of layer  30 . 
         [0054]    Processing continues by applying block mask  36  and removing regions of layers  30 ,  32 ,  66  that are not protected by the block mask  36  ( FIGS. 3A ,  3 B), and continues with the process flow described above ( FIGS. 4A ,  4 B- 5 A,  5 B) to result in the final structure shown in  FIG. 8 . When the trench  44  is formed, another trench  70  is provided that is aligned with the peripheral strip of layer  30 . The trench  70  is filled by a conductive wiring feature  72  that contacts the peripheral strip  63  of layer  30 . In a representative embodiment, the perimeter  53  of the conductive line  52  may be recessed relative to the end of layer  66 . Alternatively, the perimeter  53  of the conductive line  52  may be flush with the end of layer  66 . 
         [0055]    With reference to  FIGS. 9 ,  9 A in which like reference numerals refer to like features in  FIG. 5B  and in accordance with an alternative embodiment, the apertures  22  may be elongated to define slotted openings that perforate the dielectric layer  14  and etch stop layer  20  in the MIM capacitor region  23 . Residual parallel via bars  80  of the dielectric material from dielectric layer  14  are defined by the etching process as lines between adjacent pairs of the elongated apertures  22 . Processing continues by depositing layers  30 ,  32  ( FIGS. 2A ,  2 B), and following the process flow described above ( FIGS. 1A ,  1 B- 5 A,  5 B) resulting in the final structure shown in  FIGS. 9 ,  9 A. In the elongated slots between adjacent pairs of via bars  80 , layer  30  directly contacts the conductive wiring feature  16  as apparent in  FIG. 9A . This provides electrical contact from underneath the MIM capacitor  54  between the bottom electrode  56  and the conductive wiring feature  16 . 
         [0056]    The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
         [0057]    It will be understood that when an element is described as being “connected” or “coupled” to or with another element, it can be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. In contrast, when an element is described as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. When an element is described as being “indirectly connected” or “indirectly coupled” to another element, there is at least one intervening element present. 
         [0058]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”,  an    and  th e  are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0059]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.