Abstract:
A semiconductor substrate is coated with an insulating film followed by a layer of polysilicon. The polysilicon layer is coated with a non-oxidizable mask, such as silicon nitride, and then oxidized to convert the exposed regions to silicon oxide and add further thickness to the converted oxide regions. When the mask is removed, the thicker silicon oxide regions serve as an in situ mask for selectively implanting impurity ions through the thinner polysilicon regions and into the semiconductor substrate. When the silicon oxide regions are etched away, the remaining polysilicon regions serve as an ion implantation mask for permitting selective ion implantation through the voids left by etching the silicon oxide regions.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a method of fabricating microelectronic circuit elements and particularly to a method of forming electrically isolated regions of polycrystalline silicon on an insulating substrate. 
     Polycrystalline silicon, more commonly referred to as polysilicon, is used extensively in silicon integrated circuit technology as a first layer of isolated conductive elements, particularly in structures where a second conductive layer is to be formed. It is also advantageously used as a conductor in MOS structures and techniques known as &#34;silicon gate.&#34; 
     In the usual processing of the foregoing structures, the polysilicon is deposited over the entire surface of a wafer and then it is selectively etched through a mask. The mask is usually a material such as silicon nitride or alumina which itself is formed by photolithographic masking and etching techniques into a pattern which is duplicated by the polysilicon. The etching step that forms the polysilicon pattern is referred to as silicon etch and employs an etchant that removes the polysilicon from the unwanted regions without attacking the silicon nitride or alumina, and thereby leaves polysilicon directly beneath the silicon nitride or alumina. Finally, the silicon nitride or alumina is removed by etching. 
     The foregoing silicon etch process has several disadvantages. One drawback is that the polysilicon is undesirably undercut beneath the silicon nitride or alumina. When a layer of material suffers undercutting, it is difficult to deposit and pattern thereover subsequent layers which do not have discontinuities at the undercut boundaries. Another drawback is that the polysilicon structure that remains after the silicon nitride or alumina is removed is higher or thicker than the etched region surrounding it. Such a structure does not readily faciliate the formation of selective ion implants beneath the polysilicon. 
     SUMMARY OF THE INVENTION 
     The fabrication process according to the invention comprises forming the silicon nitride or alumina pattern over the polysilicon layer in the conventional manner. However, instead of etching the polysilicon layer, the structure is subjected to an oxidation treatment whereby the exposed regions of the polysilicon layer are not only converted to silicon oxide throughout their entire depth but also the silicon oxide is built up to a greater thickness than the unexposed polysilicon. Consequently, when the silicon nitride or alumina layer is removed, the remaining polysilicon layer is surrounded by or embedded in a silicon oxide layer that is higher or thicker than the polysilicon. 
     The thicker silicon oxide layer may be advantageously used as a self-aligned mask for ion implantation in the regions beneath the polysilicon pattern. Subsequent removal of the silicon oxide leaves the polysilicon layer thicker thann its surrounding regions, which is the condition that prevails after conventional silicon etch. 
     The oxidation process accordingly provides an additional self aligned thick oxide pattern which may serve as a mask for ion implantation processing. The oxidation process also yields a tapered polysilicon structure rather than an undercut structure. These features may be advantageously employed in the silicon gate technology when multilayer continuous pattern structures are required and self aligned doping is often advantageous. As an example of the use of these features, a charge coupled device may be constructed which incorporates multilayer elements and self-aligned ion implanted regions to form the charge transfer and storage regions. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIGS. 1 through 7 are sectional views showing various stages of constructing a charge coupled device according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A charge coupled device (CCD) may be advantageously fabricated according to the method of the invention. As shown by way of example in FIG. 1, a wafer 10, which may be of p type silicon, is first provided with a silicon oxide coating 12 and then with a layer 14 of polysilicon. The silicon oxide coating 12 may be thermally grown on the wafer 10 by conventional means to a desired thickness which is a fucntion of the temperature and time of exposure to an oxidizing atmsophere. The polysilicon layer 14 is formed by the pyrolysis of ammonia and silane or silicon tetrachloride in a nitrogen carrier gas at a temperature of about 800° C., as is well known. 
     Referring now to FIG. 2, the next step comprises forming a layer 16 of silicon nitride or alumina on the polysilicon layer 14. The nature of the layer 16 is such that it will not readily oxidize, and also that it can be etched by an etchant that does not attack either the polysilicon layer 14 or the silicon oxide layer 12. Furthermore, the layer 16 must not interact with the other materials of the structure at temperatures in the neighborhood of 1000° C. Silicon nitride or alumina satisfy all the above requirements, although silicon nitride is preferred because of its better etchability. 
     The next step in the processing is shown in FIG. 3 and comprises forming the silicon nitride layer 16 into a pattern of separate strip-like elements. The patterning may be done most conveniently be well known photolithographic techniques. The patterned layer 16 serves as a mask for the selective oxidation of the polysilicon layer 14 which is next performed by simply heating the fabricated structure in air at a temperature of about 1000° C. Such heat treatment is carried out until the exposed regions of the polysilicon layer 14 are converted to silicon oxide through the entire depth of the layer 14. During this same heat treatment the silicon oxide will grow in thickness in the exposed regions to a height exceeding that of the silicon nitride layer 16, as shown in FIG. 4. In this figure, the oxide elements formed by converting the exposed regions of the polysilicon layer 14 and by further thermal growth are shown as the thick strip elements 18. 
     Those portions of the polysilicon layer 14 that are converted to oxide and now constitute the lower portions of the thick oxide elements 18 are tapered in width towards the bottom. Conversely, the isolated regions of the polysilicon layer 14 adjacent the thick oxide elements 18 are tapered in width towards the top. As pointed out above, a tapered configuration for the polysilicon elements is a more desirable one than the undercut geometry that results from conventional selective acid etching thereof. 
     The silicon nitride mask or patterned layer 16 is removed by chemical etching, such as with hot phosphoric acid at about 180° C. The structure now remaining consists of isolated elements 14a of polysilicon layer 14 separated by insulation elements 18 of silicon oxide, as shown in FIG. 5. The polysilicon strip elements 14a will serve ultimately as a first group of electrodes in the finished structure. The oxide elements 18 are substantially thicker than the polysilicon elements 14a. This difference in thickness may be advantageously utilized to the end of having the oxide elements 18 serve as a self-aligned mask for selective ion implantation of a first dopant species into the silicon wafer 10. 
     Ions may be implanted selectively in the regions of the silicon wafer 10 underlying the polysilicon elements 14a by exposing the wafer to a beam of ions of appropriate impurity concentration and of sufficient energy to penetrate the polysilicon elements 14a and silicon oxide layer 12 without penetrating the thick silicon oxide elements 18. For a polysilicon layer of 5000 A thickness, boron may be used with an ion beam energy of 200 keV so as to produce p implanted regions 20 having a moderate concentration of 6 × 10 11  ions/cm 2  to produce a moderately doped p region in a lightly doped p- background. This beam will not penetrate the adjacent approximately 10,000 A layer of SiO 2  elements 18, bearing in mind the 200 keV boron ion would penetrate approximately 6500 A of Si or SiO 2 . 
     After the ion implanted regions 20 are produced, the silicon oxide elements 18 are removed by etching with buffered hydrofluoric acid. Oxide is removed right down to the surface of the silicon wafer 10, as shown in FIG. 6. Now the polysilicon elements 14a may serve as a self aligned mask for ion implantation of a second dopant species in the surface regions of the wafer 10 between the first implanted regions 20. 
     For the second dopant species a less energetic beam of boron ions is used that will not penetrate the polysilicon elements 14a and the underlying silicon oxide layer 12. In the example given above, a beam energy of less than 100 keV of boron would not penetrate the 5000 A polysilicon elements 14a and the silicon oxide layer 12 while allowing the regions 22 to be doped with a heavy concentration of 2 × 10 12  ions/cm 2 . It will be seen at this stage that the alternate moderatly doped p regions 20 and heavily doped p+ regions 22 are self aligned with the polysilicon pattern of elements 14a lying above. 
     In the next stage of the processing shown in FIG. 7, a thermal oxide coating 24 is grown to cover the entire structure. Finally, a layer of metal, such as aluminum is deposited over the oxide coating 24 and patterned to form a second group of strip electrodes 26 interleaved with and preferably overlapping the first group of electrodes constituted by the polysilicon strip elements 14a. 
     It will be seen that the more lightly doped p regions 20 are registered with the lower gate electrodes or polysilicon elements 14a, and the more heavily doped p+ regions 22 are registered with the upper gate electrodes 26. A two phase charged coupled device is produced when alternate pairs of gate electrodes 14a and 26 are connected together to a common first voltage phase φ 1  and the intermediate adjacent pairs of gate electrodes are coupled together to a common second voltage phae φ 2 . 
     Voltage levels of the two phases φ 1  and φ 2  may be adjusted to produce appropriate transfer-storage regions beneath the electrodes 14a and 26. With a p type wafer 10, the voltages are positive to produce an inversion in the semiconductor surface from the majority carriers or holes, to minority carriers, or electrons. Since the lower gate electrodes 14a are closer to the substrate surface than the upper gate electrodes 26, a lower positive threshold voltage is required to produce the necessary inversion, and for the same positive voltage above threshold, a deeper potential well exists under each lower gate electrode 14a than under each upper electrode 26. Moreover, this difference in threshold voltage and potential wells is further enhanced by the difference in the doping of the two implanted regions 20 and 22, with the more heavily doped regions 22 requiring a still higher threshold voltage than the more lightly doped regions 20 and also producing still shallower potential wells under the upper gate electrodes 26 than under the lower gate electrodes 14a. 
     It will of course be understood by those skilled in the art that instead of the p type CCD structure described above by way of illustration, an n type CCD structure may be fabricated according to the teachings of the invention by starting with a wafer of n type silicon and thereafter selectively implanting n type impurity ions therein, such as phosphorus, in a manner similar to that described above.