Abstract:
In one embodiment, a method for forming a semiconductor device, comprises forming a first aperture and a second aperture in a first surface of the substrate, the first and second apertures being coaxial; forming, in the first aperture, a first conductive path between the first surface of the substrate and a second surface of the substrate; and forming, in the second aperture, a second conductive path between the first surface of the substrate and a second surface of the substrate.

Description:
BACKGROUND  
       [0001]     Through silicon via structures provide an electrical connection between a conductor on a first layer of a semiconductor device and a conductor on a second layer of a semiconductor device. The first and second layers of the semiconductor device may be separated by a dielectric, and/or by a substrate material. Semiconductor devices that incorporate via structures may be used in a variety of applications, including radio frequency (RF) applications.  
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0002]     The detailed description is described with reference to the accompanying figures.  
         [0003]      FIG. 1  is a flowchart illustrating operations in a method for fabricating a semiconductor device including low inductance via structures in accordance with an embodiment.  
         [0004]      FIGS. 2A-2G  are cross-sectional views illustrating a method for fabricating a semiconductor device including low inductance via structures in accordance with an embodiment.  
         [0005]      FIG. 3A  is a schematic plan view of a semiconductor device including a low inductance via structure in accordance with an embodiment.  
         [0006]      FIG. 3B  is a schematic cross-sectional view of the semiconductor device of  FIG. 3A .  
         [0007]      FIG. 4A  is a schematic plan view of a semiconductor device including a low inductance via structure in accordance with an embodiment.  
         [0008]      FIG. 4B  is a schematic cross-sectional view of the semiconductor device of  FIG. 4A .  
         [0009]      FIG. 5  is a schematic illustration of a wireless telephone in accordance with one embodiment.  
     
    
     DETAILED DESCRIPTION  
       [0010]     Described herein are examples of low inductance via structures that may be incorporate into, e.g., in a semiconductor device, and techniques to make via structures. In the following description, numerous specific details are set forth to provide a thorough understanding of various embodiments. However, it will be understood by those skilled in the art that the various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments.  
         [0011]     In the following description, the term “semiconductor device” is used to identify discrete layers of material that form active semiconductor elements. A device, individually and in combination, can form many configurations, such as, but not limited to, a diode, a transistor, and a field effect transistor (FET), including devices found in electronic and optoelectronic devices. A device may also refer to one or more passive circuit elements, such as inductors, capacitors, or resistors, or a microelectromechanical system (MEMS) device, such as a cantilever switch.  
         [0012]     Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.  
         [0013]     One embodiment of a technique to form low inductance via structures is illustrated with reference to  FIG. 1  and  FIGS. 2A-2G .  FIG. 1  is a flowchart illustrating operations in a method for fabricating a semiconductor device including low inductance via structures in accordance with an embodiment.  FIGS. 2A-2G  are cross-sectional views illustrating various stages of a method for fabricating a semiconductor device including low inductance via structures in accordance with an embodiment.  
         [0014]      FIG. 2A  is a side-view of a semiconductor substrate  240 . At operation  110  a pair of adjacent trenches  242   a,    242   b  ( FIG. 2B ) are formed in a first surface of semiconductor substrate  240 . A variety of processes may be used to form trenches  240   a,    242   b.  In one embodiment trenches  242   a,    242   b  are formed using an etching process such as, e.g., a mechanical etching process, a chemical etching process, a plasma etching process, a photo-chemical etching process, or the like.  
         [0015]     The dimensions of trenches  242   a,    242   b  are not important. In one embodiment trenches  242   a,    242   b  measure approximately between 200 microns and 500 microns in depth, and may have a similar measurement in width.  
         [0016]     At operation  115  an insulator is deposited on the surface of the substrate  240  in which the trenches  242   a,    242   b  were formed. Referring to  FIG. 2C , the layer of insulating material  230  is deposited to coat the surface of substrate  240 , including the surfaces of trenches  242   a,    242   b.  A variety of processes may be used to deposit the layer of insulating material  230 . In one embodiment the layer of insulating material  230  may be deposited using a deposition process such as, e.g., chemical vapor deposition (CVD), electrodeposition, epitaxy, thermal oxidation, physical vapor deposition (PVD) casting, evaporation, sputter-coating, or the like.  
         [0017]     The dimensions of insulating layer  230  are not important. In one embodiment insulating layer measures approximately between 5 microns and 100 microns in depth.  
         [0018]     At operation  120  a layer of conducting material is deposited on the layer of insulating material  230  and is patterned to form a first conductor  220   a  and a second conductor  220   b.  Referring to  FIG. 2D , the first conductor  220   a  covers portions of the insulating layer  230  and fills at least a portion of trench  242   a.  Similarly, second conductor  220   b  covers portions of the insulating layer  230  and fills at least a portion of trench  242   b.  The thickness of the layer of conductive material is not important. In one embodiment the layer of conductive material measures approximately between 5 microns and 100 microns in thickness. The portion of conductive layer that fills the trenches  242   a,    242   b  is, of course, much thicker than the rest.  
         [0019]     A variety of processes may be used to deposit the layer of conducting material. The layer of conductive material may be deposited using any of the aforementioned deposition techniques. Similarly, a variety of processes may be used to form conductors  220   a,    220   b  is not critical. In one embodiment the layer of conductive material may be formed using any of the aforementioned selective etching techniques.  
         [0020]     At operation  125  material is removed from the back surface of the substrate  240 . As used herein, the term “back” refers to the surface of the substrate opposite the surface in which trenches  242   a,    242   b  were formed. This nomenclature is arbitrary. In one embodiment a sufficient quantity of material is removed from the back surface of the substrate  240  to expose the conductors  220   a,    220   b  that were filled in trenches  242   a,    242   b,  respectively. Referring to  FIG. 2D , in one embodiment an amount corresponding to the material within dashed box  244  may be removed. In the embodiment depicted in  FIG. 2E  portions of the layer of insulating material  230  are removed, resulting in three electrically isolated layers of insulating material labeled  230   a,    230   b,  and  230   c.    
         [0021]     A variety of processes may be used to remove material from the back surface of the substrate  240  is not critical. In one embodiment material is removed using a suitable grinding process. Alternately, one or more of the aforementioned etching processes may be used to remove material from the back surface of substrate  240 .  
         [0022]     At operation  130  a layer of insulating material is deposited onto the back surface and patterned to expose the conductors  220   a,    220   b  that were filled in trenches  242   a,    242   b,  respectively. Referring to  FIG. 2F , the deposition and etching operations form three electrically isolated insulators, identified by  230   a,    230   b,  and  230   c.  Any of the aforementioned deposition and patterning techniques may be used in operation  130 .  
         [0023]     At operation  135  a layer of conductive material is deposited onto the insulators  230   a,    230   b,    230   c  ( FIG. 2F ) on the back surface of substrate  240  and the exposed surfaces of conductors  220   a,    220   b  that were filled in trenches  242   a,    242   b,  respectively. Referring to  FIG. 20 , the layer of conductive material is patterned to maintain the separation between the conductors  220   a  and  220   b.  In the embodiment depicted in  FIG. 2G  the conductive layer is patterned to expose the insulator  230   c.  In an alternate embodiment, portions of insulator  230   c  may remain covered by the layer of conductive material. Any of the aforementioned deposition and patterning techniques may be used in operation  135 .  
         [0024]     Operations  110 - 135  permit the fabrication of conductive pathways that traverse the front surface of substrate  240 , traverse a cross-section of substrate  240 , and traverse the back surface of substrate  240 . The portion of the conductive pathway that traverses the cross-section of substrate  240  is referred to as a via. Hence, operations  110 - 135  permit the construction of multi-layered semiconductor devices coupled by vias.  
         [0025]     Operations  110 - 135  illustrate the construction of vias between front surface of substrate  240  and the back surface of substrate  240 . The techniques of operations  110 - 135  may be used to construct any number of vias between the front surface of substrate  240  and the back surface of substrate  240 . Further, the techniques illustrated in operation  110 - 135  may be extended to construct multi-layered semiconductor devices.  
         [0026]     A variety of materials may be used to fabricate the semiconductor device. Semiconductor substrates may comprise silicon, silicon-germanium, germanium, glass, and the like. Insulating materials may comprise various oxides, nitrides, polymers, or the like. Conductors may comprise copper, gold, aluminum, various alloys thereof, and the like.  
         [0027]     The techniques illustrated in  FIGS. 1 and 2 A- 2 G may be used to construct low inductance via structures.  FIG. 3A  is a schematic plan view of a semiconductor device  300  including a low inductance via structure in accordance with an embodiment. In one embodiment the semiconductor device depicted in  FIG. 3A  may include a coplanar waveguide.  FIG. 3B  is a schematic partial, cross-sectional sectional view of the semiconductor device  300  depicted in  FIG. 3A . In one embodiment the semiconductor device  300  may include a coplanar waveguide. In another embodiment the semiconductor device  300  may include planar signal and ground lines coupled through via structures.  
         [0028]     Referring to  FIGS. 3A and 3B , semiconductor device  300  may include a signal conductor  320   a  that traverses a portion of the front of substrate  340  and a portion of the back of substrate  340 . Signal conductor  320   a  traverses the cross-section of substrate  340  through via  350 . Similarly, semiconductor device  300  includes a ground conductor  320   b  that traverses a portion of the front of substrate  340  and a portion of the back of substrate  340 . Ground conductor  320   b  traverses the cross-section of substrate  340  through via  352 . Insulator  330   c  in  FIG. 3B  corresponds to the portion of insulating layer  330  visible in  FIG. 3A   
         [0029]     In the embodiment depicted in  FIGS. 3A-3B , via  350  and via  352  are substantially coaxial along an axis extending perpendicularly through substrate  340 . As used herein, the term coaxial should not be construed in a strict geometric sense to require perfect alignment of the longitudinal axes of via  350  and via  352 . Rather, the term coaxial should be construed to permit deviations between the longitudinal axes of via  350  and via  352 , as may result from design constraints and/or manufacturing imperfections. Because signal conductor  320   a  and ground conductor  320   b  are substantially co-planar, via  352  cannot completely encircle via  350 . Nevertheless, the coaxial via structure defined by via  350  and via  352  may provide a low inductance path between the front of substrate  340  and the back of substrate  340 .  
         [0030]      FIG. 4A  is a schematic plan view of a semiconductor device  400  including a low inductance via structure in accordance with an embodiment. In one embodiment the semiconductor device depicted in  FIG. 3A  may include a coplanar waveguide.  FIG. 4B  is a schematic partial, cross-sectional view of the semiconductor device  400  depicted in  FIG. 4A . In one embodiment the semiconductor device  400  may include a coplanar waveguide. In another embodiment the semiconductor device  400  may include planar signal and ground lines coupled through via structures.  
         [0031]     Referring to  FIGS. 4A and 4B , semiconductor device  400  includes a signal conductor  420   a  that traverses a portion of the front of substrate  440  and a portion of the back of substrate  440 . Signal conductor  420   a  traverses the cross-section of substrate  440  through via  450 . Similarly, semiconductor device  400  includes a ground conductor  420   b  that traverses a portion of the front of substrate  440  and a portion of the back of substrate  440 . Ground conductor  420   b  traverses the cross-section of substrate  440  through via  452 . Insulator  430   c  in  FIG. 4B  corresponds to the portion of insulating layer  430  visible in  FIG. 4A   
         [0032]     In the embodiment depicted in  FIGS. 4A-4B , via  450  and via  452  are substantially coaxial along an axis extending perpendicularly through substrate  440 . As used herein, the term coaxial should not be construed in a strict geometric sense to require perfect alignment of the longitudinal axes of via  450  and via  452 . Rather, the term coaxial may be construed to permit deviations between the longitudinal axes of via  450  and via  452 , e.g., as may result from design constraints and/or manufacturing imperfections. Referring to  FIG. 4B , because signal conductor  420   a  resides in a plane that is above the plane in which ground conductor  420   b  resides, via  452  can completely encircle via  450 . The coaxial via structure defined by via  450  and via  452  may provide a low inductance path between the front of substrate  440  and the back of substrate  440 .  
         [0033]     Semiconductor devices comprising low inductance vias as described herein may be used as circuit components in radio frequency (RF) transceiver applications such as, e.g., wireless telephones, and wireless networking adapters for computing devices.  FIG. 5  is a schematic illustration of a wireless telephone  500  in accordance with one embodiment. Referring to  FIG. 5 , wireless telephone  500  includes a display  510 , keypad  515 , wireless circuitry  520 , audio circuitry  525 , and processor  530 . The processor  530  is coupled to a memory module  535 . Wireless circuitry  520  is coupled to an antenna  555  by a suitable connection  560 .  
         [0034]     Wireless signals received by antenna  555  are processed by wireless circuitry  520 , which may operate as an RF transceiver. Wireless circuitry  520  may include a receiver filter, a downconverter circuit, baseband filters, analog-to-digital-converters (ADCs), local oscillator circuits, and the like. Wireless circuitry  520  may further include a transmitter that comprises a power amplifier (PA) circuit, which is used to amplify a transmit signal to a level appropriate for transmission from antenna  555 . Wireless circuitry  520  may support one or more frequency ranges. For example, unlicensed wireless signals may be sent at 900 MHz or in the frequency range between 2.4 GHz and 5 GHz.  
         [0035]     Processing circuit  530  may include a baseband processor, which may comprise one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other digital logic devices, and one or more supporting circuits, such as clocking/timing control circuits, input/output (I/O) interface circuits, and one or more memory devices, such as electrically erasable programmable read only memory (EEPROM) or FLASH memory, to store instructions and calibration data, etc., as needed or desired.  
         [0036]     Processed wireless signals are converted to an audio signal by audio circuitry  525 . Audio signals may be presented to a user by an audio interface  532  that includes a speaker, microphone, and/or other device. Audio signals received in audio interface  532  may be processed by the processor  530 , audio circuitry  525 , and wireless circuitry  520 . Wireless signals are then sent to the antenna  555 , where they are broadcast as RF signals.  
         [0037]     The memory module  535  may include logic instructions for implementing various features or functions. For example, memory module  535  may include a handover module  540  to manage handoffs between base stations in a cellular network. Memory module  535  may also include a location tracking module  545  that determines the current location of the wireless telephone  500 . In addition, memory module  535  may include authentication module  550  to coordinate an authentication procedure for authenticating that the wireless telephone  500  is licensed for use within a network.  
         [0038]     Thus, although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.