Abstract:
A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of prior U.S. application Ser. No. 12/113,510, filed May 1, 2008, now U.S. Pat. No. 8,232,604. The entire disclosure of U.S. application Ser. No. 12/113,510 is herein incorporated by reference. 
     Additionally, this application is related to application “Metal High Dielectric Constant Transistor with Reverse-T Gate,” Ser. No. 12/113,527, now U.S. Pat. No. 7,736,981, and application “Method for Fabricating a Metal High Dielectric Constant Transistor with Reverse-T Gate,” Ser. No. 12/113,557, now abandoned. These related applications are incorporated herein by reference in their entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention generally relates to the field of semiconductors, and more particularly relates to metal high dielectric constant transistors. 
     BACKGROUND OF THE INVENTION 
     Metal high dielectric constant (high-k) transistors, or “MHK transistors”, are experiencing extremely active development in the industry. One observed problem with such transistors relates to the presence of an elevated outer fringe capacitance C of, on the order of 40-80 aF/μm. This elevated capacitance C of occurs because the gate sidewall of an MHK transistor no longer depletes as in a transistor with a conventional polysilicon gate. The elevated value of outer fringe capacitance C of is of concern because it at least impairs high frequency operation of the MHK transistor. The elevated value of this capacitance C of has a performance impact of approximately 1.25% per 10 aF, resulting in a 5%-10% decrease in performance. 
     Also, with the lack of gate length scaling in recent technologies, alternatives to improve short channel effects so that the gate length may be reduced become critical to reduce the overall device dimensions enough to permit scaling. However, current technologies do not provide a reduction in the parasitic Miller capacitance when metal-like materials (such as TiN) are used. 
     SUMMARY OF THE INVENTION 
     One embodiment of the present invention provides a transistor that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. 
     Another embodiment of the present invention provides a method for fabricating a transistor. According to the method, a silicon layer is provided, and a first layer is formed on the silicon layer. A second layer is formed on the first layer, and a third layer is formed on the second layer. At least the second and third layers are etched so as to form at least second and third layers of a gate stack. A sidewall spacer layer is deposited and etched so as to form a sidewall spacer on sidewalls of the gate stack. The sidewall spacer covers the sidewalls of at least the second and third layers of the gate stack. The first layer comprises a high dielectric constant material, the second layer comprises a metal or metal alloy, the third layer comprises silicon or polysilicon, and the sidewall spacer layer comprises a high dielectric constant material. 
     Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1 to 8  are cross-sectional views of a process for fabricating a transistor with a high-k dielectric sidewall spacer according to one embodiment of the present invention; 
         FIG. 9  is a cross-sectional view of a conventional MHK transistor; and 
         FIGS. 10 to 13  are cross-sectional views of a process for fabricating a transistor with a high-k dielectric sidewall spacer according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1 to 8  illustrate a process for fabricating a transistor with a high-k dielectric sidewall spacer according to an embodiment of the present invention. In these figures an NFET transistor and a PFET transistor are shown arranged in a side-by-side manner for convenience of description. However, this is not meant to limit the present invention. Embodiments of the present invention can be directed to one or more NFET transistors, one or more PFET transistors, or a combination of these two types of transistors. 
     The process begins with a silicon-on-insulator (SOI) wafer that has a silicon substrate  102 , an overlying oxide layer (“BOX”)  104  (e.g., of 3 μm), and an overlying silicon layer  106 . One or more STI regions  110  are formed in the silicon layer  106 . Conventional hafnium dioxide (HfO 2 ) and titanium nitride (TiN) depositions are used to form a high-k dielectric layer  112  and a metal layer  114  for the gate stack, as shown in  FIG. 1 . The hafnium dioxide layer  112  has a k value in the range of about 20-25 (as compared to 3.9 for SiO 2 ) and has an exemplary thickness in the range of about 1-3 nm. The titanium nitride layer  114  has an exemplary thickness of about 10 nm. These layers  112  and  114  together form the (as yet unpatterned) MHK gate stack. This initial structure represents a conventional  501  CMOS with a MHK gate stack. 
       FIG. 2  shows the structure after the deposition of an amorphous silicon (or polysilicon) layer  216  having an exemplary thickness in the range of about 30-100 nm, and the subsequent deposition and patterning of a photoresist layer  220 . The photoresist  220  is left where a device gate is desired to be formed.  FIG. 3 , which is a partial view that does not include the silicon substrate  102  and oxide layer  104  for simplicity, shows the result after a gate stack etch and subsequent removal of the photoresist  220 . In this embodiment, the gate stack etch stops at the high-k material (hafnium dioxide layer  112 ). 
       FIG. 4  shows the structure after deposition, for example a blanket deposition by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), of a high-k spacer material layer  218 . As opposed to an amorphous silicon or polycrystalline silicon material, the high-k spacer material is a material with a dielectric constant greater than about 10. The high-k layer  218  of this embodiment illustratively has a thickness in the range of about 10-20 nm. As shown in  FIG. 4 , the high-k spacer layer  218  covers the high-k layer  112  and the exposed surfaces of the metal layer  114  and the silicon layer  216  of the gate stack. The high-k spacer layer  218  and the high-k layer  112  can comprise the same or different high-k materials. 
     A process such as reactive ion etching (RIE) is used to selectively etch the high-k spacer layer  218  so that it remains only on the sidewalls of the gate stack, as shown in  FIG. 5 . Therefore, a high-k sidewall spacer is created on the sides of each of the gates, extending down to the high-k layer  112 . The high-k sidewall spacer of this embodiment has an exemplary thickness of about 6-15 nm. Further, this etching is continued through the high-k hafnium dioxide layer  112 , so that only the portions of the high-k layer  112  located below the gate stacks  114  and  216  and the sidewall spacers  218  remain, as shown in  FIG. 6 . Thus, the gate stack is formed by the high-k layer  112 , the metal layer  114 , and the silicon layer  216 . In this gate stack, a lateral extent (width) of the high-k layer  112  is greater than a lateral extent (width) of the metal and silicon layers  114  and  216 . In this embodiment, a wet etch using a dilute hydrofluoric acid (DHF) solution is used to remove portions of the high-k hafnium dioxide layer  112 . Such a process is described in the article “Etching of zirconium oxide, hafnium oxide, and hafnium silicates in dilute hydrofluoric acid solutions” (V. Lowalekar et al., Materials Research Society, Vol. 19, No. 4, pp. 1149-1156), which is hereby incorporated by reference. In further embodiments, other processes are used to etch the high-k layer. 
     As shown in  FIG. 7 , extension implants  720  are then alternately performed on the NFET and PFET transistors. In particular, photolithography is used to selectively define the areas for the source/drain extension implants for the NFET and PFET, and ions are implanted. The extension implant is performed using an n-type species for the NFET, and using a p-type species for the PFET. Because of the presence of the high-k sidewall spacers, these implantations can be performed at a much lower dose than with a conventional structure having a conventional sidewall spacer, such as at an at least a 50% lower dose). For example, in preferred embodiments the implantation is performed at a dose of less than about 1.5 e 15 /cm 3 , and in this exemplary embodiment is performed at a dose of 0.5 to 0.8 e 15 /cm 3  (compared to a typical dose of 2.0 to 3.0 e 15 /cm 3  in a conventional fabrication processes). 
     The remainder of the fabrication process is the same as the conventional CMOS fabrication process. As shown in  FIG. 8 , oxide and/or nitride diffusion spacers  824  are formed (for example, by PECVD). The diffusion spacers  824  of this embodiment have an exemplary thickness of about 2-10 nm. Source and drain regions are then implanted. The source/drain implant is performed using a p-type species for the NFET (for example, As or P), and using an n-type species for the PFET (for example, B or BF 2 ). A subsequent rapid thermal anneal (RTA) is performed (e.g., millisecond laser anneal or flash anneal) to provide relatively deep diffusions for the source and drain regions. Subsequent conventional processing is used to silicide the gates, sources, and drains (typically with Ni or Co) to complete the NFET and PFET transistors. 
     As shown in  FIG. 8 , extensions  721  and halos  722  are formed in the silicon layer  106  by the extension implants and annealing. The extension implant dose and subsequent anneal operate to drive each extension implant (i.e., extension region  721 ) under part but not all of the high-k sidewall spacer  218 , and not under any of the gate stack. That is, each high-k sidewall spacer  218  is only partially underlapped by an extension junction. This results in the effective device length Leff being greater than the physical device length Lgate. In contrast, in the conventional MHK transistor with conventional oxide and/or nitride sidewall spacers as shown in  FIG. 9 , the extension implant dose and anneal drive operate to drive each extension implant  920  (i.e., extension region) completely under the sidewall spacers  924  and partially under the gate stack, which causes the effective device length Leff to be less than the physical device length Lgate. 
     Because the present invention provides an effective device length Leff that is greater than the physical device length Lgate, the gating action of the fringing fields from the gate is enhanced, so as to invert the extension regions in proximity to the gate. The gate electrode gates both the normal inversion layer under the gate as well as regions to the left and right of the gate. 
     Although the overlap capacitance component from the outer fringe increases, the capacitance component from gate to extension region drops, as the direct overlap capacitance component is eliminated. The extension region can also be implanted right before the spacer deposition to reduce the effect in the region. 
       FIGS. 10-13  illustrate a process for fabricating a transistor with a high-k dielectric sidewall spacer according to an embodiment of the present invention. In this embodiment, the gate stack etch stops on the silicon layer  106 , as shown in  FIG. 10 . Thus, the gate stack is formed by the high-k layer  112 , the metal layer  114 , and the silicon layer  216 . In this gate stack, a lateral extent (width) of the high-k layer  112  is the same as a lateral extent (width) of the metal and silicon layers  114  and  216 . 
     After the gate stack etch, a high-k spacer material layer  218  is deposited, for example with a thickness in the range of about 10-20 nm. As shown in  FIG. 11 , the high-k spacer layer  218  covers the exposed surfaces of the high-k layer  112 , the metal layer  114 , and the silicon layer  216  of the gate stack. The high-k spacer layer  218  and the high-k layer  112  can comprise the same or different high-k materials. 
     A process such as reactive ion etching (RIE) is used to selectively etch the high-k spacer layer  218  so that it remains only on the sidewalls of the gate stack, as shown in  FIG. 12 . Therefore, a high-k sidewall spacer is created on the sides of each of the gates, extending down to the silicon layer  106 . The high-k sidewall spacer of this embodiment has an exemplary thickness of about 6-15 nm. Extension implants are then performed. Because of the presence of the high-k sidewall spacers, this implant can be performed at a much lower dose than with a conventional structure having a conventional sidewall spacer (for example, a 50% lower dose). 
     The remainder of the fabrication process is the same as in the embodiment described above. As shown in  FIG. 13 , oxide and/or nitride diffusion spacers  824  are formed (for example, by PECVD) with an exemplary thickness of about 2-10 nm. Source and drain region are then implanted, and a subsequent rapid thermal anneal (RTA) is performed (e.g., millisecond laser anneal or flash anneal) to provide relatively deep diffusions for the source and drain regions. Subsequent conventional processing is used to silicide the gates, sources, and drains (typically with Ni or Co) to complete the NFET and PFET transistors. 
     As shown in  FIG. 13 , in this embodiment also the extension implant dose and subsequent anneal operate to drive each extension implant (i.e., extension region  721 ) under part but not all of the high-k sidewall spacer  218 , and not under any of the gate stack. That is, each high-k sidewall spacer  218  is only partially underlapped by an extension junction. This results in the effective device length Leff being greater than the physical device length Lgate. 
     The embodiments of the present invention described above are meant to be illustrative of the principles of the present invention. These MHK device fabrication processes are compatible with CMOS semiconductor fabrication methodology, and thus various modifications and adaptations can be made by one of ordinary skill in the art. All such modifications still fall within the scope of the present invention. 
     For example, while the exemplary embodiments of the present invention described above relate to gate structures that use hafnium dioxide for the high-k layer and titanium nitride for the metal layer, further embodiments can use other compatible materials, such as ZrO 2  or HfSi x O y , which both exhibit the high dielectric constant (e.g., k of approximately 20-25) needed to provide a larger equivalent oxide thickness. Similarly, other metal oxide-based materials may be used, such as a uniform or a composite layer comprised of one or more of Ta 2 O 5 , TiO 2 , Al 2 O 3 , Y 2 O 3  and La 2 O 5 . The metal-containing layer  114  could also be formed of another material, such as one or more of Ta, TaN, TaCN, TaSiN, TaSi, AlN, W and Mo. Additionally, in further embodiments the silicon layer  216  described above can be comprised of another material that is able to be etched, remain conductive, and withstand high temperatures. Similarly, while the embodiments described above relate to a transistor on an SOI wafer, the transistors and fabrication methods of the present invention are also applicable to bulk technologies. Likewise, the various layer thicknesses, material types, deposition techniques, and the like discussed above are not meant to be limiting. 
     Furthermore, some of the features of the examples of the present invention may be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples and exemplary embodiments of the present invention, and not in limitation thereof. 
     It should be understood that these embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in the plural and vice versa with no loss of generality. 
     The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed. 
     The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard, or other input device, and a central processor.