Abstract:
A controlling method of a voltage regulator is provided. The voltage regulator at least includes a differential circuit and a pump high-voltage circuit which has a bias path, an output transistor and an output terminal. The controlling method includes steps of: providing at least a pre-charge path to the pump high-voltage circuit, closing the bias path and charging the output terminal with the pre-charge path when the output terminal is transient, detecting an output level of the output terminal, and closing the pre-charge path and open the bias path to bias the output transistor when the output level reaches a predetermined value.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a voltage regulator and controlling method thereof, and more particularly to a high speed and low power voltage regulator for memory. 
       BACKGROUND OF THE INVENTION 
       [0002]    Please refer to  FIG. 1 , which is a circuit diagram showing a conventional voltage regulator according to the prior art. In  FIG. 1 , the voltage regulator includes a differential circuit  11  and a pump high-voltage circuit  12 . The differential circuit  11  includes a first stage circuit and a second stage circuit. The pump high-voltage circuit  12  includes a third stage circuit and a fourth stage circuit. The pump high-voltage circuit  12  is further electrically connected to an output stage circuit. 
         [0003]    In the first stage circuit, the respective sources of the PMOS transistors P 1  and P 2  are electrically connected to a high voltage source Vdd. The respective gates of the PMOS transistors P 1  and P 2  are electrically connected to each other. The gate of the PMOS transistor P 2  is electrically connected to the drain thereof. The drain of the NMOS transistor N 1  is electrically connected to the drain of the PMOS transistor P 1 . The gate of the NMOS transistor N 1  is to receive a voltage reference signal V_Reference. The drain of the NMOS transistor N 2  is electrically connected to the drain of the PMOS transistor P 2 . The gate of the NMOS transistor N 2  is to receive a feedback signal fb. The respective sources of the NMOS transistors N 1  and N 2  are electrically connected to the drain of the NMOS transistor N 3 . The gate of the NMOS transistor N 3  is to receive a voltage bias signal V_bias. The source of the NMOS transistor N 3  is electrically connected to a low voltage source Vss. 
         [0004]    In the second stage circuit, the source of the PMOS transistor P 3  is electrically connected to the high voltage source Vdd. The gate of the PMOS transistor P 3  is electrically connected to the drain of the NMOS transistor N 1 . The drain of the PMOS transistor P 3  is electrically connected to the drain of the NMOS transistor N 4 . The gate of the NMOS transistor N 4  is electrically connected to the drain thereof. The source of the NMOS transistor N 4  is electrically connected to the low voltage source Vss. 
         [0005]    In the third stage circuit, the respective sources of the PMOS transistors P 4  and P 5  are electrically connected to a pump voltage source Pump HV. The respective gates of the PMOS transistors P 4  and P 5  are electrically connected to each other. The gate of the PMOS transistor P 4  is electrically connected to the drain thereof. The drain of the NMOS transistor N 5  is electrically connected to the drain of the PMOS transistor P 4 . The gate of the NMOS transistor N 5  is electrically connected to the gate of the NMOS transistor N 4 . The source of the NMOS transistor N 5  is electrically connected to the low voltage source Vss. 
         [0006]    In the fourth stage circuit, the drain of the PMOS transistor P 5  is electrically connected to electrically series-connected resistors R 1  and R 2 . Another end of the resistor R 2  is electrically connected to the low voltage source Vss. 
         [0007]    The output stage circuit includes a capacitance load Cload. One end of the capacitance load Cload is electrically connected to a node between the drain of the PMOS transistor P 5  and the resistor R 1  to be the output terminal output, and another end of the capacitance load Cload is electrically connected to the low voltage source Vss. 
         [0008]    Please refer to  FIG. 2 , which is a graph showing the output terminal voltage of the voltage regulator and the currents of the PMOS transistors P 4  and P 5  according to  FIG. 1 . When the capacitance load Cload is charged, the voltage level of the output terminal output is still low. The feedback signal fb is then raised to be close to the voltage reference signal V_Reference. The voltage of the node A is low, and the voltage of the node B rises from a low point. The voltage of the node B being at the high point will cause the voltage pbias of the node C to go low, and the current I 2  of the PMOS transistor P 5  is thus increased. 
         [0009]    Besides, the current I 1  of the PMOS transistor P 4  is increased since the voltage pbias of the node C is low. The currents I 1  and I 2  are both provided by the pump voltage source Pump HV. For the increase of the currents I 1  and I 2  leads to the complex design and the poor current efficiency of the pump voltage source. 
       SUMMARY OF THE INVENTION 
       [0010]    It is therefore an object of the present invention to provide a controlling method of a voltage regulator is provided. The voltage regulator at least includes a differential circuit and a pump high-voltage circuit which has a bias path, an output transistor and an output terminal. The controlling method includes steps of: providing at least a pre-charge path to the pump high-voltage circuit, closing the bias path and charging the output terminal with the pre-charge path when the output terminal is transient, detecting an output level of the output terminal, and closing the pre-charge path and open the bias path to bias the output transistor when the output level reaches a predetermined value. 
         [0011]    According to the foregoing object of the present invention, a voltage regulator is provided. The voltage regulator includes:
       a differential circuit; and   a pump high-voltage circuit for pumping an output of the differential circuit, comprising:
           an output terminal having an output level;   an output transistor with one end electrically connected to the output terminal;   a bias path closed when the output terminal is transient;   a pre-charge path for charging the output terminal when the output terminal is transient;   a discharge path for discharging the output terminal when the output terminal is transient; and   an output level detector for detecting the output level, closing the pre-charge path or the discharge path and opening the bias path to bias the output transistor when the output level reaches a predetermined level.   
               
 
         [0020]    According to the foregoing object of the present invention, a voltage regulator is provided. The voltage regulator includes:
       a differential circuit; and   a pump high-voltage circuit for pumping an output of the differential circuit, comprising:
           an output terminal having an output level;   an output transistor with one end electrically connected to the output terminal;   a bias path closed when the output terminal is transient;   a pre-charge path for charging the output terminal when the output terminal is transient;   a discharge path for discharging the output terminal when the output terminal is transient; and   an controller for closing the pre-charge path or the discharge path and opening the bias path to bias the output transistor according to the output level.   
               
 
         [0029]    The foregoing and other features and advantages of the present invention will be more clearly understood through the following descriptions with reference to the drawings, wherein: 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]      FIG. 1  is a circuit diagram showing a conventional voltage regulator according to the prior art; 
           [0031]      FIG. 2  is a graph showing the output terminal voltage of the voltage regulator and the currents of the PMOS transistors P 4  and P 5  according to  FIG. 1 ; 
           [0032]      FIG. 3  is a circuit diagram showing a voltage regulator according to the first embodiment of the present invention; 
           [0033]      FIG. 4  is a circuit diagram showing a voltage regulator according to the second embodiment of the present invention; and 
           [0034]      FIG. 5  is a graph showing the output voltage of the output terminal, the voltage of the bias path, the output voltage of the output level detector, the currents of the PMOS transistors P 4 ˜P 6 , and the charging/discharging voltage of the capacitance load Cload according to  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0035]    The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for the purposes of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed. 
         [0036]    Please refer to  FIG. 3 , which is a circuit diagram showing a voltage regulator according to the first embodiment of the present invention. In  FIG. 3 , the voltage regulator includes a differential circuit  31  and a pump high-voltage circuit  32 . The differential circuit  31  includes a first stage circuit and a second stage circuit. The pump high-voltage circuit  32  includes a third stage circuit and a fourth stage circuit. The pump high-voltage circuit  32  is further electrically connected to an output stage circuit. 
         [0037]    In the first stage circuit, the respective sources of the PMOS transistors P 1  and P 2  are electrically connected to a high voltage source Vdd. The respective gates of the PMOS transistors P 1  and P 2  are electrically connected to each other. The gate of the PMOS transistor P 2  is electrically connected to the drain thereof. The drain of the NMOS transistor N 1  is electrically connected to the drain of the PMOS transistor P 1 . The gate of the NMOS transistor N 1  is to receive a voltage reference signal V_Reference. The drain of the NMOS transistor N 2  is electrically connected to the drain of the PMOS transistor P 2 . The gate of the NMOS transistor N 2  is to receive a feedback signal fb. The respective sources of the NMOS transistors N 1  and N 2  are electrically connected to the drain of the NMOS transistor N 3 . The gate of the NMOS transistor N 3  is to receive a voltage bias signal V_bias. The source of the NMOS transistor N 3  is electrically connected to a low voltage source Vss. 
         [0038]    In the second stage circuit, the source of the PMOS transistor P 3  is electrically connected to the high voltage source Vdd. The gate of the PMOS transistor P 3  is electrically connected to the drain of the NMOS transistor N 1 . The drain of the PMOS transistor P 3  is electrically connected to the drain of the NMOS transistor N 4 . The gate of the NMOS transistor N 4  is electrically connected to the drain thereof. The source of the NMOS transistor N 4  is electrically connected to the low voltage source Vss. 
         [0039]    In the third stage circuit, the respective sources of the PMOS transistors P 4  and P 5  are electrically connected to a pump voltage source Pump HV. The respective gates of the PMOS transistors P 4  and P 5  are electrically connected to each other. The gate of the PMOS transistor P 4  is electrically connected to the drain thereof to form a bias path  34 . The drain of the NMOS transistor N 6  is electrically connected to the drain of the PMOS transistor P 4 . The drain of the NMOS transistor N 5  is electrically connected to the source of the NMOS transistor N 6 , the gate of the NMOS transistor N 5  is electrically connected to the gate of the NMOS transistor N 4 , and the source of the NMOS transistor N 5  is electrically connected to the low voltage source Vss. 
         [0040]    In the fourth stage circuit, the drain of the PMOS transistor P 5  is electrically connected to electrically series-connected resistors R 1  and R 2 . Another end of the resistor R 2  is electrically connected to the low voltage source Vss. 
         [0041]    The output stage circuit includes a capacitance load Cload. One end of the capacitance load Cload is electrically connected to a node between the drain of the PMOS transistor P 5  and the resistor R 1  to be the output terminal output, and another end of the capacitance load Cload is electrically connected to the low voltage source Vss. 
         [0042]    Besides, the output stage circuit is further electrically connected to a pre-charge path  33 . In this embodiment, the pre-charge path  33  includes a PMOS transistor P 6  which has a source electrically connected to the pump voltage source Pump HV and a drain electrically connected to the output terminal output. 
         [0043]    The output stage circuit is further electrically connected to a discharge path. The output terminal output is electrically connected to the drain of the NMOS transistor N 7 . The gate of the NMOS transistor N 7  is electrically connected to a signal discharge and the source of the NMOS transistor N 7  is electrically connected to the low voltage source Vss. 
         [0044]    Moreover, the pump high-voltage circuit  32  is further electrically connected to an output level detector  30  which has an input electrically connected to the output terminal output and an output electrically connected to the control terminal of the pre-charge path  33  and the control terminal of the NMOS transistor N 6 . 
         [0045]    In order to overcome the drawback of the prior art where the currents I 1  and I 2  increases owing to the decreased voltage pbias, in this embodiment, the output level detector  30  is used to detect the output current level of the output terminal output. When the output level detector  30  detects the output level of the output terminal being increased to a predetermined value for the capacitance load Cload is charged, the output level detector  30  closes the bias path  34  (NMOS transistor N 6 ) with the signal transientb and opens the pre-charge path  33  (PMOS transistor P 6 ) with the signal chargeb. Therefore, the PMOS transistors P 4  and P 5  are nearly turned off. The current through the pump voltage source Pump HV constitutes the current I 3  through the PMOS transistor P 6 . 
         [0046]    Besides, when the output level detector  30  detects the output level of the output terminal being decreased to a predetermined value for the capacitance load Cload is discharged, the output level detector  30  closes the bias path  34  (NMOS transistor N 6 ) with the signal transientb, opens the discharge path with the signal discharge, and closes the pre-charge path  33  (PMOS transistor P 6 ) with the signal chargeb. The process afterward is the same with the prior art. 
         [0047]    Please refer to  FIG. 4 , which is a circuit diagram showing a voltage regulator according to the second embodiment of the present invention. The difference between  FIGS. 3 and 4  is the input of the output level detector  40  is changed to be electrically connected to the node between the series-connected resistors R 1  and R 2 , so as to detect the output voltage level of the output terminal output. The rest of the implementation is the same with the prior embodiment. 
         [0048]    Except for the above two embodiments, a controller (now shown in the Figs,) can also be used to replace the output level detector. A predetermined program is integrated in the controller to automatically open the bias path and close the pre-charge path if necessary. Being not as smart as the above two embodiment, the controller is still easily achieved by one skilled in the art. 
         [0049]    Please refer to  FIG. 5 , which is a graph showing the output voltage of the output terminal, the voltage of the bias path, the output voltage of the output level detector, the currents of the PMOS transistors P 4 ˜P 6 , and the charging/discharging voltage of the capacitance load Cload according to  FIG. 3 . 
         [0050]    When the capacitance load Cload is about to be charged at time t 1 , the charging voltage charge is low and the level of the output terminal output is also about to be raised to a high level. The output level detector closes the bias path and opens the pre-charge path, so that the levels of the currents I 1  and I 2  are low and the level of the current I 3  is high. At this time, the voltage pbias of the node C is high, and the output levels transient and chargeb of the output level detector are both low. 
         [0051]    When the capacitance load Cload is about to be discharged at time t 2 , the charging voltage charge is high and the level of the output terminal output is also about to be decreased to a low level. The output level detector closes the bias path and opens the discharge path, so that the levels of the currents I 1  and I 2  are low. At this time, the voltage pbias of the node C is high, the output levels discharge and chargeb of the output level detector are both high, and the signal transient is low. 
         [0052]    In conclusion, with the voltage regulator and controlling method provided in the invention, the power of the voltage regulator can be decreased, the output current of the pump high-voltage circuit can be reduced, and the layout size of the pump high-voltage circuit can be minimized. 
         [0053]    While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.