Abstract:
A low cost digital conference trunk system of the simple construction with a smaller volume, which uses a single memory both as a memory for holding input highway data and a memory for holding output highway data by address operation and timing control.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital conference trunk system and particularly to a digital conference trunk system which employs a memory used both for input and output. 
     2. Description of the Related Art 
     FIG. 1 is a block diagram illustrating the basic constitution of a digital exchange. In an ordinary speech between a telephone 101 and a telephone 108, for example, data sent from the telephone 101 passes through a line circuit LC1 and a highway HW and is inputted to a network NW. After the highway HW being connected to the destination telephone circuit by the switching operation of the network NW, the data from the telephone 101 passes the highway HW again and a line circuit LC2, and is received by the telephone 105. 
     The digital exchange is of time-division switching type, where time-division multiplexed serial data of a plurality of circuits is carried in the highway HW, with a time slot allocated to each telephone circuit. The serial data is input ted to the line circuits LC1 or LC2, or to a conference trunk equipment TRK. 
     In an add-on with the conference trunk equipment TRK among telephones 101, 102 and 105 For example, data sent from each telephone circuit passes through the highway HW to be inputted to the network NW and, after the highway HW is connected to the destination telephone circuit by the switching operation of the network NW, the data from each telephone circuit is inputted to the conference trunk equipment TRK to be mixed. After being mixed, the data is sent via the network NW and the line circuits LC1 and LC2 again, and data from the telephones 102 and 105 is received by the telephone 101, data from the telephones 101 and 105 is received by the telephone 102, and data from the telephones 101 and 102 is received by the telephone 105. 
     In addition to the use in such a conference as described above, the conference trunk equipment may be used in an attendant transfer by an operator in a hotel or the like, where among an outside line, the operator and a telephone in a guest room temporarily form an add-on condition when the operator transfers data received from the outside line to the guest room. 
     FIG. 2 is a block diagram illustrating an outline of a conventional digital conference system. FIG. 3 through FIG. 7 are timing charts thereof. 
     Input highway data dn (n: 0, 1, . . . , 15) is serially transmitted by a time slot TSn (8 bits per 1 time slot) with a band width of a quarter of a specified frequency N (if N=1MHz, for example, N/4=256KHz) and is serially stored in shift registers 90n. Because eight bits are transmitted by one time slot, data is shifted in a direction from 90 15  to 90 14  to 90 13 , and so on bit by bit by the main clock having a frequency 2N (if N=1MHz, for example, 2N=2MHz). 
     When all pieces of data of 16 time slots TS0 through TS15 are stored in the respective shift registers 90 0 , 90 1 , . . . , 90 15  (FIG.3(b), FIG.4(b)), a data selector 80 reads data of P time slots (P is the number of circuits which can attend a conference supported by a conference system), that is the data d 0 , d 1 , d 2 , d 3  of the time slots TS0, TS1, TS2, TS3 from the respective shift registers 90 0  through 90 3  in the example, in a period of two time slots ( FIG. 5 (a)), to input the read data to an addition/subtraction circuit 70 via a P/L conversion means 30a, which converts data from PCM to linear (FIG. 5(c)). The addition/subtraction circuit 70 adds up the input highway data dn successively to obtain the sum da=d 0  +d 1  +d 3  +d 3  in the time snot TS17. 
     In the following two time slots (TS18, TS19), the sum da and the data d 0 , d 1 , d 2 , d 3  of each slot are used to calculate the output highway data D 0  =d 1  +d 2  +d 3 , D 0  =d 1  +d 2  +d 3 , D 2  =d 0  +d 1  +d 3 , D 3  =d 0  +d 1  +d 2 , which are to be outputted in the respective time slots (TS0 through TS3). 
     The output highway data Dn thus calculated is temporarily stored in output shift registers 60n via an L/P conversion means 30b, which converts data from linear to PCM. At this time, upon receipt of a signal from a decoder 40, the shift registers 60n are opened in the order from 60 0  to 60 1  to 60 2  and so on, to store the specified output highway data Dn in the specified registers 60 n . 
     Then the input highway data d 4  through d 7  of the subsequent four slots (TS4, TS5, TS6, TS7) are processed to obtain output data D 4  =d 5  +d 6  +d 7 , D 5  =d 4  +d 6  +d 7 , D 6  =d 4  +d 5  +d 7 , and D 7  =d 4  +d 5  +d 6  which is to be outputted to the corresponding register 60n (time slots TS20 through TS23). Remaining two sets of highway data (d 8  through d 11 ) and (d 12  through d 15 ) are also processed successively in the time slots (TS24 through TS27) and (TS28 through TS31). 
     When all shift registers 60 0  through 60 15  receive the output highway data Dn, the data is sequentially outputted by shifting the shift registers 60n, and the next input highway data dn is inputted at the same time. 
     Usually, two sets of the unit described above are installed, with one shift register 60 processing the highway data of the time slots 0 through 15 and another unit processing the highway data of the time slots 16 through 31. 
     In FIG. 2, various timing signals are generated in a clock generator 50. 
     In the above case, a conference trunk is a four circuits set. When a conference trunk is formed of an eight circuits set, input highway data dn of eight time slots is read at a time and is subjected to addition/subtraction operations, instead of data dn of four time slots. 
     The principle of switching the trunk equipment of the four circuits set to the trunk equipment of the eight circuits set, is to change the timing signal which controls the selector 80. 
     According to the conventional system provided with shift registers 90n, 60n (buffer memories) provided on the input and output sides as above, the input side shift register 90n converts the input highway data dn to parallel data by sequentially shifting the data which is inputted as serial data, while the output side shift register 60n outputs the output highway data Dn as serial data by shifting the data which is inputted as parallel data. Therefore, because the shift registers 90n and 60n have different functions, both the registers cannot be replaced with a single memory. 
     As a result, the system has such a defect as to require buffer memories on the input side and the output side, respectively, which results in greater size and higher costs. 
     Also switching the trunk equipment for four circuits to that for eight circuits requires to change the timing signals outputted from the timing circuit 50. However, such switching construction with the conventional circuit requires too many parts to be mounted on a package. So that, two packages for the four circuits and eight circuits are separately prepared which are selected by a switch. This results in the system of further larger size and with larger number of parts, thereby to raise manufacturing cost. 
     SUMMARY OF THE INVENTION 
     The present invention has been made to solve such problems as described above, and has for its object to provide a conference trunk system which uses a single memory both as a memory for temporarily storing data which is inputted From a plurality of circuits via a highway and as a memory for temporarily storing data which is to be outputted to the respective circuits after addition and subtraction, by means of address operation, thereby to simplify the constitution with a less volume of a low price. 
     The above and further objects and features of the invention will more fully be apparent from the following detailed description with accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating the basic constitution of a digital exchange; 
     FIG. 2 is a block diagram of a conventional digital conference trunk system; 
     FIG. 3(a) is a timing chart of the conventional conference trunk system: 
     FIG. 3(b) is a timing chart of the conventional conference trunk system; 
     FIG. 3 (c) is a timing chart of the conventional conference trunk system; 
     FIG. 3(d) is a timing chart of the conventional conference trunk system; 
     FIG. 3(e) is a timing chart of the conventional conference trunk system; 
     FIG. 4(a) is a timing chart of the conventional conference trunk system; 
     FIG. 4(b) is a timing chart of the conventional conference trunk system; 
     FIG. 4 (c) is a timing chart of the conventional conference trunk system; 
     FIG. 4 (d) is a timing chart of the conventional conference trunk system; 
     FIG. 4 (e) is a timing chart of the conventional conference trunk system; 
     FIG. 5 (a) is a timing chart of the conventional conference trunk system; 
     FIG. 5 (b) is a timing chart of the conventional conference trunk system; 
     FIG. 5(c) is a timing chart of the conventional conference trunk system; 
     FIG. 5(d) is a timing chart of the conventional conference trunk system; 
     FIG. 5(e) is a timing chart of the conventional conference trunk system; 
     FIG. 6(a) is a timing chart of the conventional conference trunk system; 
     FIG. 6(b) is a timing chart of the conventional conference trunk system; 
     FIG. 6(c) is a timing chart of the conventional conference trunk system; 
     FIG. 6(d) is a timing chart of the conventional conference trunk system; 
     FIG. 6(e) is a timing chart of the conventional conference trunk system; 
     FIG. 7(a) is a timing chart of the conventional conference trunk system; 
     FIG. 7(b) is a timing chart of the conventional conference trunk system; 
     FIG. 7(c) is a timing chart of the conventional conference trunk system; 
     FIG. 7(d) is a timing chart of the conventional conference trunk system; 
     FIG. 7(e) is a timing chart of the conventional conference trunk system; 
     FIG. 8 is a block diagram explanatory of the principle of a digital conference trunk system of the invention; 
     FIG. 9 is a block diagram illustrating an embodiment of a digital conference trunk system of the invention; 
     FIG. 10 is a block diagram of a timing signal generation means of FIGS. 8 and 9; 
     FIG. 11 is a block diagram of an address generation means of FIGS. 8 and 9; 
     FIG. 12 is a block diagram including an area around a selector of FIGS. 8 and 9; 
     FIG. 13(a) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 13(b) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 13(c) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 13(d) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 13(e) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 13(f) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 14(a) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 14(b) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 14(c) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 14(d) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 14(e) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 14(f) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 15(a) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 15(b) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 15(c) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 15(d) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 15(e) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 15(f) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 16(a) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 16(b) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 16(c) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 16(d) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 16(e) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 16(f) is a timing chart of the digital conference trunk system of the invention; 
     FIG. 17(a) is a timing chart of one time slot; 
     FIG. 17(b) is a timing chart of one time slot; 
     FIG. 17(c) is a timing chart of processing each division time of one time slot; 
     FIG. 18(a) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(b) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(c) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(d) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(e) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(f) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(g) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(h) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(i) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(j) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(k) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(l) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(m) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(n) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(o) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(p) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(q) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 18(r) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(a) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(b) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(c) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(d) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(e) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(f) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(g) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(h) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(i) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(j) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(k) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(l) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(m) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(n) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(o) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(p) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(q) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 19(r) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(a) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(b) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(c) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(d) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(e) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(f) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(g) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(h) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(i) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(j) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(k) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(l) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(m) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(n) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(o) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(p) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention; 
     FIG. 20(q) is a timing chart of a timing signal general on means of the digital conference trunk system of the invention; and 
     FIG. 20(r) is a timing chart of a timing signal generation means of the digital conference trunk system of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention will now be described below with reference to the drawings illustrative of preferred embodiments. 
     FIG.8 is a block diagram of a digital conference trunk system illustrative of the principle of the invention. The digital conference trunk system of the invention comprises a memory means 200 for temporarily storing the input highway data dn and the output highway data Dn used both as a memory for input and output, an address generation means 300 which generates write and read addresses A 0 , A 1 , A 6 , A 7  of the memory means 200, an addition/subtraction means 400 which generates the output highway data Dn to be outputted in the time slot TSn by addition and subtraction of the highway data dn which is read From the memory means 200, and a timing signal generation means 100 which controls the operation timing of the memory means 200 and of the addition/subtraction means 400. 
     FIG.9 is a block diagram illustrative of an embodiment of the invention. FIG. 13 through FIG. 16 are timing charts indicating an outline of the operation of the invention. FIG. 17 is an enlarged timing chart of one time slot. 
     The one time slot shown in FIG. 17 (a) has 8 times the period of the main clock signal CLK9 of frequency 2N (2MHz, for example) shown in FIG. 17 (b), with the first 1/8 division time being denoted as the 0th division time t 0 , the second 1/8 division time being denoted as the 1st division time t 1 , and the eighth 1/8 division time being denoted as the 7th division time t 7 . 
     The input highway data dn (n is a suffix indicating the time slot number and is an integer from 0 to 15) is inputted to an S/P converter 11 in the order of the time slot numbers, to be converted from serial to parallel and tentatively latched in a latch circuit 12. 
     Then the data is stored at corresponding addresses a 0  through a 15  of the memory means 200 to the respective time slots TS n  according to a write address A 0  to be described below, which is given by the address generation means 300 (the 0th division time t 0  in FIG. 13 through FIG. 17). 
     The input highway data dn which is written in the memory means 200 as described above is read by specified pieces P (where P is the number of circuits capable of simultaneously speaking in the digital conference system and P is four or eight in this embodiment) according to a read address A 1  given by the address generation means 300, sent via the selector 21 to the PCM/linear data conversion means (referred to as a data conversion means hereinafter) 22 where the input highway data is converted from PCM to linear, and is inputted to the addition/subtraction means 400. 
     The addition/subtraction means 400 first calculates da which is the sum of the specified pieces P of the input highway data dn (for example, da=d 0  +d 1  +d 2  +d 3 ), and temporarily stores the sum in the register 41. Subsequently, the output highway data Dn which corresponds to the time slot TSn (for example, D 0  =d 1  +d 2  +d 3 , . . . , D 3  =d 0  +d 1  +d 2 ) is obtained. The output highway data Dn thus obtained is sent via the selector 21 to the data conversion means 22 to convert the output highway data Dn from linear to PCM (processed in the 1st division time t 1  through 5th division time t 5 ). 
     Then the data is stored in the memory means 200 in a write address A 6  which is given by the address generation means 300 (in the  6  th division time t 6 ). 
     Finally, the data is read from the memory means 200 from a read address A 7  which is given by the address generation means 300, to be outputted after being converted to serial data by the P/S conversion means 15, 
     FIG. 10 shows the detailed construction of the timing signal generation means 100 of the invention. FIG. 18 through FIG. 20 are detailed timing charts of the timing signal generation means 100. 
     As shown in FIG. 10, the timing signal generation means 100 generates; a gate signal Y 0  which supplies the write address A 0  to the memory means 200 in the 0th division time t 0  which is the first 1/8 division time of one time slot for the purpose of writing the input highway data dn to the memory means 200; a gate signal Y 06  which gives the read address A 1  to the memory means 200 for reading the input highway data dn from the memory means 200 for the purpose of adding/subtracting the input highway data dn in the 1st time slot t 1  through the 5th time slot t 5  to specify the time of addition/subtraction; a gate signal Y 6  which supplies the write address A 6  to the memory means 200 for writing the output highway data Dn which has been obtained as the result of the above addition/subtraction in the 6th division time t 6  of one time slot; and gate signal Y 7  which gives the read address A 7  to the memory means 200 for reading the output highway data Dn which has been written in the memory means 200 and sending out the output highway data Dn in the  7  th division time t 7  of one time slot. 
     The timing signal generation means 100 is provided with a counter 110 which counts the main clock signal CLK9 having frequency 2N (for example, 2MHz: FIG. 18(a), FIG. 19(a), FIG. 20(a)) with eight times the period of one time slot (FIG. 18(c), FIG. 19(c), FIG. 20(c)), so that the clock signals CLK1 through CLK8 having the frequencies to be described below are obtained (FIGS. 18(d) through (k), FIGS. 19(d) through (k), FIGS. 20 (d) through (k)). 
     
         ______________________________________   BIT      FREQUENCY   CLK No.______________________________________FIG. 13(d)     bit 0      N           CLK1FIG. 13(e)     bit 1      1/2 × N                            CLK2FIG. 13(f)     bit 2      1/4 × N                            CLK3FIG. 13(g)     bit 3      1/8 × N                            CLK4FIG. 13(h)     bit 4      1/16 × N                            CLK5FIG. 13(i)     bit 5      1/32 × N                            CLK6FIG. 13(j)     bit 6      1/64 × N                            CLK7FIG. 13(k)     bit 7      1/128 × N                            CLK8______________________________________ 
    
     The following output signals are obtained from the outputs of the counter 110 as shown in FIG. 10 and TABLE 1. The gate signal Y 0  which supplies the write address a 0  to the memory means 200 is obtained in the 0th division time t 0  from the inverted signals of the clock signals CLK1, CLK2, CLK3 which are ANDed by an AND gate G 1 . (FIG. 18(l), FIG. 19(1), FIG. 20( l ). 
     Similarly to he above, the gate signal Y 6  which gives the write address A 6  to the memory means 200 is obtained in the 6th division time t 6  after the addition/subtraction by inputting the clock signals CLK2, CLK3 and the inverted signal of the clock signal CLK 1 to an AND gate G 2 , and further by inverting the output from the AND gate G 2  (FIG. 18(m), FIG. 19(m), FIG. 20(m)). 
     The gate signal Y 7  which supplies the read address A 7  to the memory means 200 is obtained in the 7th division time from inverting the ANDed clock signals CLK1, CLK2, CLK3 by an AND gate G 3  (FIG. 18(n), FIG. 19(n), FIG. 20(n)). 
     Further, the gate signal Y 06  which specifies the time of addition/subtraction (the 1st division time t 1  through the 5th division time t 5 ) is obtained from the ANDed gate signals Y 0  and Y 6  by an AND gate G 4  (FIG. 18(o), FIG. 19(o), FIG. 20(o)). 
     The gate signal Y45 which specifies the time of processing after addition/subtraction, that is, the time of latching the added/subtracted value to the register 41, and converting the output highway data to PCM (the 4th and 5th division times) is obtained by AND operation of an AND gate G 5  between the inverted signal of the clock signal CLK2 and the clock signal CLK3 (FIG. 18(p), FIG. 19(p), FIG. 20(p)). 
     The addition/subtraction processing time comprises a period of addition T O  in the first P time slots and a period of subtraction T 1  in the next P time slots. The write address A 6  is sufficient to be given in the period of the subtraction period T 1  after the subtraction. 
     The timing signal generation means 100 further generates a write signal We which consists of a 1st write signal We 1  for enabling the memory means 200 to be written in the 0th division time t 0  of every time slot, and a 2nd writing signal We 2  For enabling the memory means 200 to be written in the 6th division time t 6  of every time slot within the subtraction period T 1 . The timing signal generation means 100 also generates a read signal Re for enabling the memory means 200 to be read by supplying the read addresses A 1 , A 7  to the memory means 200 in a 1/8 division time of every time slot at least other than the 1/8 division time where the write signal We is being outputted. 
     More specifically, the 1st write signal We 1  is obtained from AND operation between the inverted gate signal Y 0  and the main clock signal CLK9 by a gate G 6  (FIG. 18(q), FIG. 19(q), FIG. 20(q)). The 2nd write signal We 2  is obtained from AND operation between the inverted gate signal Y 6  and the clock signal CLK6 by gate G 7 . The write signal We is obtained from OR operation between the 1st and the 2nd write signals by a gate G 8 . The 1st write signal We 1  is used for writing the input highway data dn to the memory means 200, and the 2nd write signal We 2  is for writing the output highway data Dn obtained by the addition/subtraction to the memory means 200. 
     The 1st read signal Re 1  is obtained from OR operation between the inverted gate signal Y 0  and the gate signal Y 6  by a gate G 9 . The 2nd read signal Re 2  is obtained from AND operation between the inverted gate signal Y 6  and the clock signal CLK6 by a gate G 10 . The read signal Re is obtained by OR operation between the 1st and 2nd read signals by a gate G 11  (FIG. 18(r), FIG. 19(r), FIG. 20(r)). The 1st read signal Re 1  enables the memory means 200 to be accessed during a time in the subtraction period T 1  other than the time of latching the sum da to the register 41 and converting the output highway data Dn. The 2nd read signal Re 2  inhibits the memory means 200 to be read while the 2nd write signal We 2  being generated. 
     The counter 110 is reset by a frame clock FC (FIG. 18(b), FIG. 19(b), FIG. 20(b)) which is outputted in every 32 time slots. 
     FIG. 11 is a detailed diagram of the address generation means 300. As shown in FIG. 11, the address generation means 300 outputs the write address A 0  to write the input highway data dn to the memory means 200, the read address A 1  to read the input highway data dn from the memory means 200 for addition/subtraction, the write address A 6  to write the output highway data Dn which is obtained as a result of the addition/subtraction to the memory means 200, and the read address A 7  to read the written output highway data Dn from the memory means 200 to output the same. The address generation means 300 generates addresses by outputs from a counter 310 which receives the main clock signal CLK9 and is reset by the frame clock FC. Because the counter 310, upon shifting the outputs twice, becomes identical with the counter 110 of the timing signal generation means 100, it is a matter of course that these counters can be used in common. 
     Similarly to the above, tile counter 310 outputs clock signals CLK1 through CLK8, among which clock signals CLK1 through CLK5 are directly used as the address A 7  for reading the output highway data Dn, while the value lagged by two counts behind the read address A 7  (delayed by a shift register 20) is used as the write address A 0  for writing the input highway data dn to the memory means 200 (refer to TABLE 2, `ordinary mode`). 
     On the other hand, the address A 1  (A 6 ) which uses the clock signals CLK1, CLK2, CLK4, CLK5 among the clock signals CLK1 through CLK5 which constitute the address A 0 , counts the same value twice every four times as shown in the case of `4-subscriber mode` in TABLE 2 (for example, counts 0 through 3 for the address A 1 , again counts 0 through 3 for the address A 6 , counts 4 through 7 for the address A 1 , again counts 4 through 7 for the address A 6 ). Similarly, the address A 1  (A 6 ) which uses the clock signals CLK1, CLK2, CLK3, CLK5 among the clock signals CLK1 through CLK5 which constitute the address A 0 , counts the same value twice every eight times shown in the case of `8-subscriber mode` in TABLE 2. 
     The addresses A 0 , A 1 , A 6 , A 7  are inputted to the memory means 200 as will be described below by giving various gate signals to the selector 500 shown in FIG. 12. 
     That is, the write address A 0  is sent to the memory means 200 via an AND gate G 21  which is controlled by the inverted gate signal Y 0  as shown in FIG. 12 (the 0th division time t 0 ). Since the write signal We is also inputted to the memory means 200 at this time, the input highway data dn (d 0 , d 1 , . . . , d 15 ) which is latched by the latch means 12 as described above is written in the memory means 200 at the specified addresses (a 0  through a 15 ) which correspond to the respective time slots (FIG. 13(a), 14(a), FIG. 15(a), FIG. 16(a)). 
     Then, the address A 1  is supplied to the memory means 200 via an AND gate G 23  which is controlled by the inverted gate signal Y 06  during tile period from the 1st division time t 1  to the 5th division time t 5  of the time slots TS0 through TS3. Because the read signal Re is active during tile period from the 1st division time t 1  to the 3rd division time t 3 , the input highway data d 0 , d 1 , d 2 , d 3  stored in the memory means 200 at the respective addresses is read sequentially. 
     The input highway data dr, which is read as described above is inputted to the data conversion means 22 via the selector 21 where the input highway data is converted to linear data and is inputted to the addition/subtraction means 400 (FIG. 13(b), FIG. 14(b), FIG. 15(b), FIG. 16(b)). P pieces of data (where P is the number of the circuits capable of simultaneously speaking in a conference system) are added/subtracted in the addition/subtraction means 400. Addition/subtraction processing is achieved in the addition period T O  and in the subtraction period T 1 . During the addition period T 0 , P pieces of the input highway data read from the memory means 200 by supplying the address A 1  in the first P time slots, and during the subtraction period T 1 , the output highway data Dn is obtained by subtracting each piece of the input highway data corresponding to each time slot from the added result in the next P time slots. In this embodiment, the sum da=d 0  +d 1  +d 2  +d 3  is obtained by sequentially adding the read out data d O , d 1 , d 2 , d 3 . 
     The sum da obtained as described above is temporarily stored in the register 41 provided in the addition/subtraction means 400 in the 4th division time t 4  and the 5th division time t 5  specified by the gate signal Y 45  (time slot TS3 in FIG. 13(c), FIG. 14(c), FIG. 15(c), FIG. 16(c)). The 1st division time t 1  through the 5th division time t 5  of the time slots TS 0  through TS 3  constitute the addition period T 0 . 
     In the 1st division time t 1  to the 3rd division time t 3  of the next four time slots TS4 through TS7, the address A 1  is also supplied to the memory means 200 to read the input highway data d 0 , d 1 , d 2 , d 3  therefrom and each piece of the input highway data is complemented when being inputted to the addition/subtraction means 400. Then, the sum da=d 0  +d 1  +d 2  +d 3  obtained as described above and each complement -d 0 , -d 1 , -d 2 , -d 3  are added to obtain the output highway data D O  (d 1  +d 2  +d 3 ), D 1  (d 0  +d 2  +d 3 ), D 2  (d 0  +d 1  +d 3 ), D 3  (d 0  +d 1  +d 3 ) which correspond to the time slots TS0, TS1, TS2, TS3 (FIG. 13(d), FIG. 14(d), FIG. 15(d), FIG. 16(d)). 
     The output highway data Dn obtained as described above is inputted to the data conversion means 22 where it is converted to PCM data via the selector 21 (the 4th and the 5th time slots t 4 , t 5 ). The 1st division time t 1  through the 5th division time t 5  of the time slots TS4 through TS7 constitute the subtraction period T 1 . 
     Then, the address A 6  is supplied to the memory means 200 via the AND gate G 22  which is controlled by the inverted gate signal Y 6  memory means 200 during the 6th division time t 6 , and the second write signal We 2  is also supplied to the memory means 200 in the 6th division time of the subtraction period T 1 . Consequently, the output highway data D O  through D 3  is written to the memory means 200 at the specified addresses (FIG. 13(e), FIG. 14(e), FIG. 15(e), FIG. 16(e)). 
     The output highway data D 0 , D 1 , D 2 , D 3  is read by the read address A 7  which is supplied to the memory means 200 in the 7th division time via the gate G 24  which is controlled by the inverted gate signal V 7 , and is outputted in the respective slots TS0, TS1, TS2, TS3 (FIG. 13(f), FIG. 14(f), FIG. 15(f), FIG. 16(f)). However, the output highway data D 0 , D 1 , . . . obtained in the slots TS4, TS5, . . . is read in the slots after TS30. 
     When the data of the four time slots is processed, the data of eight slots is stored in the memory means 200. Thus the read address A1 is supplied to the memory means 200 in the 1st and 2nd division, time of each time slot, and four pieces of the input data d 4 , d 5 , d 6 , d 7  of the subsequent four time slots TS4, TS5, TS6, TS7 are added and subtracted as above to obtain the outpost highway data D 4 , D 5 , D 6 , D 7 . 
     The output highway data D 4  through D 7  is then written in the memory means 200 at the write address A 6 , and is later read from the memory means 200 at the read address A 7 . 
     The above processes are repeated on the input highway data d O  through d 15  of the time slots TS0 through TS15, and processing of the entire input highway data d O  through d 15  requires a time length of 32 time slots. 
     The timing signal generation means 100 also generates control signals of the selector 21. That is, the selector 21 selects the memory means 200 by the read signal Re when the input highway data dn is inputted to the data conversion means 22 from the memory means, and selects the data conversion means 22 by the ANDed gate signal Y 45  and clock signal CLK6 when the output highway data Dn is input Led to the data conversion means 22 from the addition/subtraction means 400. The data conversion means 22 is controlled by the clock signal CLK6 to switch the addition period T O  and the subtraction period T 1 . 
     As a practical matter, two of such units as described above are provided, so that the highway data of the time slots 0 through 15 is processed in one unit while the highway data of the time slots 16 through 31 is processed in the other unit. 
     Although the above description is for the 4-subscriber mode, operation in the 8-subscriber mode proceeds similarly. In the 8-subscriber mode, the clock signals CLK1, CLK2, CLK3, CLK5 from the write address A 0  are used during addition and subtraction, and the address A 1  (A 6 ) based on double counting every eight Limes as shown in `8-subscriber mode` of TABLE 2. This provides a trunk circuit which is capable of processing the input and output highway data in the unit of 8 pieces. 
     The 4-subscriber mode and the 8-subscriber mode can be easily switched by changing the address A 1  (A 6 ) generation mode to the 4-scriber mode or to the 8-scriber mode in TABLE 2 by subscriber&#39;s number changing means 600 shown in FIG. 9. However, when operating in the 8-subscriber mode, the clock signal CLK7 is used instead of the clock signal CLK6 for switching in FIG. 9, FIG. 10. 
     To construct a conference trunk of the 4-circuit mode, a set of four of the address A 1  and a set of four of the address A 6 , for the addition and subtraction are generated twice, respectively (the first four are the read address A 1 , the second four are the write address A 6 ) while the main write addresses A 0  is generated eight times. To constitute a conference trunk of the 8-circuit mode, on the other hand, a set of eight of the address A 1  a set of eight of the address A 6 , For the addition and subtraction are generated twice, respectively, While the main write address A 0  is generated sixteen times. 
     The address generation modes can be easily changed by selecting the output bits of the address counter 310 as shown in FIG. 11 and TABLE 1. 
     As for the methods of converting PCM data to linear data, there are the μ-Law and the a-Law. The apparatus can be applied to either method by storing two types of data in the data conversion means 22. 
     As this invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, the present embodiment is therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalence of such metes and bounds thereof are therefore intended to be embraced by the claims. 
     
                       TABLE 1______________________________________OUTPUT SIGNAL        INPUT SIGNAL       GATE______________________________________ ##STR1##         ##STR2##           G.sub.1 ##STR3##         ##STR4##           G.sub.2 ##STR5##     CLK1 × CLK2 × CLK3                            G.sub.3Y.sub.06     Y.sub.0 × Y.sub.6                           G.sub.4 Y.sub.45         ##STR6##           G.sub.5 We.sub.1         ##STR7##           G.sub.6 We.sub.2         ##STR8##           G.sub.7We           We.sub.1 + We.sub.2                           G.sub.8 Re.sub.1         ##STR9##           G.sub.9 Re.sub.2         ##STR10##          .sub. G.sub.10Re           Re.sub.1 + Re.sub.2                           .sub. G.sub.11______________________________________ 
    
     
                                           TABLE 2__________________________________________________________________________ORDINARY MODE              4-SUBSCRIBER MODE  bit                        bit  5   4   3   2   1            5   4   2   1DECIMAL  4   3   2   1   0   DECIMAL                             4 3   2   1   0__________________________________________________________________________ 0     0   0   0   0   0   0      0 0   0   0   0 1     0   0   0   0   1   1      0 0   0   0   1 2     0   0   0   1   0   2      0 0   0   1   0     A.sub.1 3     0   0   0   1   1   3      0 0   0   1   1 4     0   0   1   0   0   0      0 0   0   0   0 5     0   0   1   0   1   1      0 0   0   0   1 6     0   0   1   1   0   2      0 0   0   1   0     A.sub.6 7     0   0   1   1   1   3      0 0   0   1   1 8     0   1   0   0   0   4      0 0   1   0   0 9     0   1   0   0   1   5      0 0   1   0   110     0   1   0   1   0   6      0 0   1   1   0     A.sub.111     0   1   0   1   1   7      0 0   1   1   112     0   1   1   0   0   4      0 0   1   0   013     0   1   1   0   1   5      0 0   1   0   114     0   1   1   1   0   6      0 0   1   1   0     A.sub.615     0   1   1   1   1   7      0 0   1   1   116     1   0   0   0   0   8      0 1   0   0   017     1   0   0   0   1   9      0 1   0   0   118     1   0   0   1   0   10     0 1   0   1   0     A.sub.119     1   0   0   1   1   11     0 1   0   1   120     1   0   1   0   0   8      0 1   0   0   021     1   0   1   0   1   9      0 1   0   0   122     1   0   1   1   0   10     0 1   0   1   0     A.sub.623     1   0   1   1   1   11     0 1   0   1   124     1   1   0   0   0   12     0 1   1   0   025     1   1   0   0   1   13     0 1   1   0   126     1   1   0   1   0   14     0 1   1   1   0     A.sub.127     1   1   0   1   1   15     0 1   1   1   128     1   1   1   0   0   12     0 1   1   0   029     1   1   1   0   1   13     0 1   1   0   130     1   1   1   1   0   14     0 1   1   1   0     A.sub.631     1   1   1   1   1   15     0 1   1   1   1__________________________________________________________________________                      8-SUBSCRIBER MODE                           bit                             5    3   2   1                    DECIMAL                           4 3    2   1   0__________________________________________________________________________                    0      0 0    0   0   0                    1      0 0    0   0   1                    2      0 0    0   1   0                    3      0 0    0   1   1                    4      0 0    1   0   0      A.sub.1                    5      0 0    1   0   1                    6      0 0    1   1   0                    7      0 0    1   1   1                    0      0 0    0   0   0                    1      0 0    0   0   1                    2      0 0    0   1   0                    3      0 0    0   1   1                    4      0 0    1   0   0      A.sub.6                    5      0 0    1   0   1                    6      0 0    1   1   0                    7      0 0    1   1   1                    8      0 1    0   0   0                    9      0 1    0   0   1                    10     0 1    0   1   0                    11     0 1    0   1   1                    12     0 1    1   0   0      A.sub.1                    13     0 1    1   0   1                    14     0 1    1   1   0                    15     0 1    1   1   1                    8      0 1    0   0   0                    9      0 1    0   0   1                    10     0 1    0   1   0                    11     0 1    0   1   1                    12     0 1    1   0   0      A.sub.6                    13     0 1    1   0   1                    14     0 1    1   1   0                    15     0 1    1   1   1__________________________________________________________________________