Abstract:
A method of operating a PSRAM includes selecting a bit on a word line of the PSRAM, keeping the word line on for a first predetermined duration after selecting the bit, writing a data into the bit in response to a write command, and keeping the word line on for a second predetermined duration after the write command ends.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention is related to a method of operating a PSRAM and related device, and more particularly, to a method of providing write recovery in a PSRAM and related device. 
         [0003]    2. Description of the Prior Art 
         [0004]    Random access memory (RAM) is a form of computer data storage. There are two main types of RAM: static RAM (SRAM) and dynamic RAM (DRAM). In DRAM, memory cells are essentially made up of a transistor and capacitor pair. The capacitor holds a high or low charge, and the transistor acts as a switch to allow the control circuitry on the chip to access or change the capacitor&#39;s state. Data are stored in the DRAM memory cells in the form of electric charges which need to be periodically refreshed. In SRAM, memory cells store data using flip-flops which do not need to be refreshed, thereby providing faster access time. However, an SRAM device generally is larger in size and consumes more power than a DRAM device. 
         [0005]    A pseudo-static RAM (PSRAM) internally uses a cell structure of DRAM and is externally similar to SRAM, thereby combining the higher density of DRAM with the simpler control of SRAM. Refresh operation is also needed to prevent loss of data stored in memory cells . Awaiting period is required for writing a last bit of data into a PSRAM before issuing a precharge command and after a write cycle. Such waiting period is known as the write recovery time. 
         [0006]    In the prior art PSRAM, a protection scheme is provided after a bit of a word line is selected for a write command. If the PSRAM is performing a dummy read before receiving the write command, the word line remains on for improving performance. However, the prior art protection scheme may fail to provide a sufficient write recovery time under such circumstance. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention provides a method of providing write recovery protection in a PSRAM. The method includes selecting a bit on a word line of the PSRAM; keeping the word line on for a first predetermined duration after selecting the bit; writing a data into the bit in response to a write command; and keeping the word line on for a second predetermined duration after the write command ends. 
         [0008]    The present invention also provides a PSRAM memory device with write recovery protection. The PSRAM memory device includes a PSRAM; a memory control circuit configured to generate a chip enable signal, a write enable signal, and a bit select signal for operating the PSRAM; a write recovery protection circuit configured to generate a protection signal which includes information of a first protection scheme associated with the bit select signal and a second protection scheme associated with the write enable signal; and a word line control circuit configured to turn on or turn off a word line according to the protection signal. 
         [0009]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a function diagram illustrating a PSRAM memory device according to the present invention. 
           [0011]      FIG. 2  is a signal diagram illustrating the operation of the PSRAM memory device according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]      FIG. 1  is a function diagram illustrating a PSRAM memory device  100  according to the present invention. The PSRAM memory device  100  includes a memory control circuit  10 , a write recovery protection circuit  20 , a word line control circuit  30 , and a PSRAM  40 . The memory control circuit  10  is configured to generate control signals for operating the PSRAM  40  according to an external command S EXT . The control signals may includes a chip enable signal  CE , a write enable signal  WE , and a bit select signal BS. As well known to those skilled in the art, the chip enable signal  CE  is used to block or allow input signals to the PSRAM memory device  100 , the write enable signal  WE  is used to choose between a read and a write operation, and the bit select signal BS is used to select a bit of the PSRAM  40 . 
         [0013]    The write recovery protection circuit  20  is configured to provide a protection signal S p  according to the chip enable signal  CE , the write enable signal  WE , and the bit select signal BS. The protection signal S p  includes information of two protection schemes. The first protection scheme is associated with the start of a bit selecting operation, such as when the bit select signal BS goes high. The second protection scheme is associated with the end of a write operation, such as when the chip enable signal  CE  or the write enable signal  WE  goes low. 
         [0014]    The word line control circuit  30  is configured to turn on or off a specific word line of the PSRAM  40  according to the protection signal S p . 
         [0015]      FIG. 2  is a signal diagram illustrating the operation of the PSRAM memory device  100  according to the present invention. In  FIG. 2 , WL represents the level of a specific word line, and BL/  BL  represent the level of a specific bit line pair. When the chip enable signal  CE  is high, input signals applied to the PSRAM memory device  100  are ignored; when the chip enable signal  CE  is low, input signals may be applied to the PSRAM memory device  100 . When the write enable signal  WE  is high, the PSRAM  40  is configured to perform a read operation; when the write enable signal  WE  is low, the PSRAM  40  is configured to perform a write operation. T WHP  is the high pulse width of the write enable signal  WE  after the chip enable signal  CE  goes low. T ARD  is the period when the PSRAM  40  operates in asynchronous read mode. T AWT  is the period when the PSRAM  40  operates in asynchronous write mode. T WR1  represents the duration of the first protection scheme. T WR2  represents the duration of the second protection scheme. 
         [0016]    After the specific word line is turned on, the PSRAM  40  enters asynchronous read mode before the write enable signal  WE  goes low. Bit selection starts after the bit select signal BS goes high, which is the start of the first protection scheme T WR1 . For exiting asynchronous write mode, the write enable signal  WE  goes high, which is the start of the second protection scheme T WR2 . In other words, the present invention keeps the specific word line on for a predetermined duration so as to guarantee a sufficient write recovery time. 
         [0017]    In the embodiment illustrated in  FIG. 2 , the PSRAM  40  switches to asynchronous write mode before completing a dummy read operation in asynchronous read mode. Under such circumstance, both the first protection scheme T WR1  and the second protection scheme T WR2  are activated. 
         [0018]    In another embodiment when T WHP  is very short, the PSRAM  40  may enter asynchronous write mode without entering asynchronous read mode. Under such circumstance, only the first protection scheme T WR1  is activated. 
         [0019]    In yet another embodiment when T WHP  is very long, the PSRAM  40  may complete a dummy read operation in asynchronous read mode before entering asynchronous write mode. Under such circumstance, only the first protection scheme T WR1  is activated. 
         [0020]    The present invention provides a PSRAM device with an improved write recovery protection. The two protection schemes may guarantee a sufficient write recovery time when switching between read/write operations. 
         [0021]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.