Abstract:
A problem arises with related art liquid crystal displays in that the amount of power consumed will not be reduced any further, as a voltage generator circuit to supply power is kept activated. An exemplary method for driving a display uses a first plurality of operational amplifiers to generate a first plurality of voltages of different levels associated with a first plurality of grayscale levels displayable in the display so as to provide the display with a second plurality of grayscale levels out of the first plurality of grayscale levels. The method includes activating a second plurality of operational amplifiers corresponding to the second plurality of grayscale levels out of the first plurality of operational amplifiers, and deactivating remaining operational amplifiers other than the second plurality of operational amplifiers.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of Invention 
   The present invention relates to a display driving method and a driver to drive a display, such as a liquid crystal display (LCD) panel. More particularly, the invention relates to a display driving method and a driver to apply multiple voltages associated with multiple grayscale levels specified by a plurality of image data to a plurality of source lines (data lines) of a number of thin film transistors (TFTs) provided in such an LCD panel. 
   2. Description of Related Art 
   To generate multiple potentials, for example, 64 potentials associated with 64 grayscale levels, related art display drivers require 64 operational amplifiers. Assuming that each of the 64 operational amplifiers consumes a current of 100 μA, all of the 64 operational amplifiers consume 6.4 mA (100 μA×64) in total. When using a power voltage of 5 V, for example, this results in a large amount of power consumed, which reaches 32 mW (6.4 mA×5 V). 
   The LCD disclosed in Japanese Unexamined Patent Publication No. 2003-140618 (p. 1,  FIG. 1 ), which is an example of such a display, is capable of reducing the total amount of power consumed for the LCD by switching the supply of operational power to a voltage generator circuit, corresponding to the operational amplifiers, between multi-grayscale display and dual-grayscale display. 
   SUMMARY OF THE INVENTION 
   The related art LCD, however, does not switch the supply of power when providing only the multi-grayscale display. Since the voltage generator circuit is kept activated in this state of things, a problem arises in that the amount of power consumed will not be reduced any further. 
   In order to address the above and/or other problems, a first exemplary method to drive a display according the present invention uses a first plurality of operational amplifiers to generate a first plurality of voltages of different levels associated with a first plurality of grayscale levels displayable in the display so as to provide the display with a second plurality of grayscale levels out of the first plurality of grayscale levels. The method includes activating a second plurality of operational amplifiers corresponding to the second plurality of grayscale levels out of the first plurality of operational amplifiers and deactivating remaining operational amplifiers other than the second plurality of operational amplifiers. 
   With the first exemplary method to drive a display according to the present invention, which activates the second plurality of operational amplifiers out of the first plurality of operational amplifiers and deactivates the remaining operational amplifiers, it is possible to reduce power consumed compared to related art display drivers that always activate the first plurality of operational amplifiers. 
   A second exemplary method to drive a display according to the present invention uses a first plurality of operational amplifiers to generate a first plurality of voltages of different levels associated with a first plurality of grayscale levels displayable in the display so as to perform displaying of the display. The method includes, prior to a horizontal synchronization period, identifying a second plurality of operational amplifiers corresponding to a second plurality of grayscale levels to be displayed on the display during the horizontal synchronization period out of the first plurality of operational amplifiers; and activating the second plurality of operational amplifiers and deactivating remaining operational amplifiers other than the second plurality of operational amplifiers. 
   With the second exemplary method to drive a display according to the present invention, which identifies the second plurality of operational amplifiers out of the first plurality of operational amplifiers prior to the horizontal synchronization period, and activates the second plurality of operational amplifiers and deactivates the remaining operational amplifiers, it is possible to make the remaining operational amplifiers remain deactivated during the horizontal synchronization period and thus reduce power consumed compared to related art display drivers that always activate the first plurality of operational amplifiers, that is, both the second plurality of operational amplifiers and the remaining operational amplifiers, during the horizontal synchronization period. 
   In the second exemplary method to drive a display according to the present invention, it is preferable that the display includes a plurality of source lines; each of the second plurality of grayscale levels being specified by one of a plurality of image data corresponding to the plurality of source lines, each of the plurality of image data specifying one of the first plurality of grayscale levels; the identifying including referring to all of the plurality of image data at once so as to identify the second plurality of operational amplifiers corresponding to the second plurality of grayscale levels specified by the plurality of image data out of the first plurality of operational amplifiers. 
   In the second exemplary method to drive a display according to the present invention, it is preferable that the display includes a plurality of source lines; each of the second plurality of grayscale levels being specified by one of a plurality of image data corresponding to the plurality of source lines, each of the plurality of image data specifying one of the first plurality of grayscale levels; the identifying including referring the plurality of image data sequentially so as to identify the second plurality of operational amplifiers corresponding to the second plurality of grayscale levels specified by the plurality of image data out of the first plurality of operational amplifiers. 
   In the second exemplary method to drive a display according to the present invention, it is preferable that the display includes a plurality of source lines; each of the second plurality of grayscale levels being specified by one of a plurality of image data corresponding to the plurality of source lines, each of the plurality of image data specifying one of the first plurality of grayscale levels; the identifying including examining a plurality of blocks, block by block, each of the plurality of blocks including two or more image data divided from the plurality of image data, so as to identify the second plurality of grayscale levels out of the first plurality of grayscale levels, and a degree of activating the second plurality of operational amplifiers is calculated based on a number of the two or more image data; the activation and deactivation including activating the second plurality of operational amplifiers according to the degree of activation calculated in the identification step. 
   Driver 
   A first exemplary driver to drive a display according to the present invention includes a plurality of vertical lines connectable to the display that is driven by using a first plurality of voltages of different levels associated with a first plurality of grayscale levels displayable in the display, a first plurality of horizontal lines connectable to the plurality of vertical lines, a plurality of switches to establish and terminate a connection between the plurality of vertical lines and the first plurality of horizontal lines, a first plurality of operational amplifiers including an output terminal coupled to one of the first plurality of horizontal lines to generate the first plurality of voltages, a control circuit for making the plurality of switches establish and terminate a connection between the plurality of vertical lines and the first plurality of horizontal lines according to a second plurality of grayscale levels to be displayed on the display out of the plurality of grayscale levels, a charging circuit to charge a second plurality of horizontal lines coupled to at least one of the plurality of vertical lines out of the first plurality of horizontal lines with the plurality of switches by charging the plurality of vertical lines, a detection circuit to detect the second plurality of horizontal lines that are charged, and an activation circuit to activate a second plurality of operational amplifiers coupled to the second plurality of horizontal lines detected by the detection circuit. 
   In the first exemplary driver to drive a display according to the present invention, the control circuit makes the plurality of switches establish and terminate a connection between the plurality of vertical lines and the first plurality of horizontal lines based on the second plurality of grayscale levels, the detection circuit detects the second plurality of horizontal lines that are coupled to the plurality of vertical lines by turning on and shutting off of the plurality of switches and charged by the charging circuit out of the first plurality of horizontal lines, and the activation circuit activates only the second plurality of operational amplifiers that are coupled to the second plurality of horizontal lines that are charged out of the first plurality of operational amplifiers. Therefore, it is possible to reduce power consumed compared to related art display drivers that always activate the first plurality of operational amplifiers. 
   The first exemplary driver to drive a display according to the present invention preferably includes a discharging circuit to discharge the plurality of vertical lines and the first plurality of horizontal lines, prior to the charging of the plurality of vertical lines by the charging circuit. 
   Decoder circuit 
   A second exemplary driver to drive a display according to the present invention includes a first plurality of operational amplifiers to generate a first plurality of voltages of different levels associated with a first plurality of grayscale levels displayable in the display, and a decoder circuit for, by referring to a conversion table specifying correspondence between two or more grayscale levels out of the first plurality of grayscale levels and a plurality of representative grayscale levels that represent the two or more grayscale levels, the plurality of representative grayscale levels being fewer than the first plurality of grayscale levels, converting each of a second plurality of grayscale levels to be displayed on the display out of the first plurality of grayscale levels into one of the plurality of representative grayscale levels and activating an operational amplifier corresponding to the one of the plurality of representative grayscale levels out of the first plurality of operational amplifiers. 
   In the second exemplary driver to drive a display according to the present invention, by referring to the conversion table, the decoder circuit converts each of the second plurality of grayscale levels into the one representative grayscale level and activates an operational amplifier corresponding to the representative grayscale level out of the first plurality of operational amplifiers. Here, the power consumed by an operational amplifier is the total of stationary power that is fixedly consumed irrespective of the size of the load or grayscale level of the operational amplifier (the number of grayscale levels assigned to the operational amplifier to generate a voltage) and load power that is consumed depending on the size of the load of the operational amplifier as widely known. For example, if eight grayscale levels to be displayed on the display are represented by two representative grayscale levels and two operational amplifiers corresponding to the two representative grayscale levels are activated, the total power consumed (a total of two stationary powers and eight load powers) is less than the amount of power consumed by eight operational amplifiers generating eight voltage levels for the eight grayscale levels (resulting in a total of eight stationary powers and eight load powers) by six stationary powers. Therefore, with the second exemplary driver to drive a display according to the present invention, it is possible to reduce the power consumed compared to related art drivers that activate a plurality of operational amplifiers (eight in the above example) corresponding to the second plurality of grayscale levels that are more than the operational amplifiers (two in the above example) corresponding to the representative grayscale levels. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic that shows a display driver according to one exemplary embodiment of the present invention; 
       FIG. 2  is a schematic that shows a logic circuit of the exemplary embodiment; 
       FIG. 3  is a schematic that shows a memory circuit and decoders of the exemplary embodiment; 
       FIG. 4  is a schematic that shows a conversion table of the exemplary embodiment; 
       FIG. 5  is a schematic that shows the operation of the driver of the exemplary embodiment; 
       FIG. 6  is a schematic that shows the operation of a first exemplary modification; and 
       FIG. 7  is a schematic that shows the operation of a second exemplary modification. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   An exemplary embodiment of a display driver of the present invention is described below with reference to the accompanying drawings. 
     FIG. 1  shows a display driver according to one exemplary embodiment of the invention. A driver  1  of the present exemplary embodiment provides a display with four grayscale levels according to line-by-line sequential drives. In order to address or achieve this, the driver  1  has a function of applying voltages associated with grayscale levels specified by image data to contact points PA, PB, PC (the three shown by way of example, and not as a limitation) by horizontal lines M 1 , M 2 , M 3 , M 4  and vertical lines LA, LB, LC. Each of the contact points is coupled to a source line of a plurality of TFTs included in a display, such as an LCD panel. 
   To perform this function, the driver  1  includes operational amplifiers  11 ,  12 ,  13 ,  14 ; logic circuits  21 ,  22 ,  23 ,  24 ; switches  41 ,  42 ,  43 ,  44 ; switches  51 A,  52 A,  53 A,  54 A,  51 B,  52 B,  53 B,  54 B,  51 C,  52 C,  53 C,  54 C; a memory circuit  60 ; decoders  70 A,  70 B,  70 C; switches  80 A,  80 B,  80 C; a control circuit  90 ; resistors R 1 , R 2 , R 3 , R 4 , R 5 ; switches SWA, SWB, SWC; and switches swa, swb, sbc as shown in  FIG. 1 . 
   The operational amplifiers  11  to  14  output four voltages Vp, Vq, Vr, Vs to the horizontal lines M 1  to M 4 . The four voltages are associated with the four grayscale levels specified by divided voltages using the resistors R 1  to R 5  based on a power potential VDD (3 V or 5V, for example) and a ground potential VSS. The voltages Vp, Vq, Vr, Vs output by the operational amplifiers  11 ,  12 ,  13 ,  14 , respectively, satisfy the inequality Vp&gt;Vq&gt;Vr&gt;Vs. Here, the operational amplifier is referred to as general amplifiers including related art operational amplifiers. 
   Provided in between the horizontal lines M 1  to M 4  and the operational amplifiers  11  to  14 , the logic circuits  21  to  24  activate or deactivate the operational amplifiers  11  to  14  under the control of the control circuit  90 . 
   The switches  41  to  44  are provided in between the horizontal lines M 1  to M 4  and the ground potential VSS. For example, the switch  41  is provided in between the horizontal line M 1  and the ground potential VSS. 
   The switches  51 A to  54 A,  51 B to  54 B,  51 C to  54 C are provided in matrix form in between the vertical lines LA, LB, LC and the horizontal lines M 1 , M 2 , M 3 , M 4 . For example, the switch  51 A is provided in between the vertical line LA and the horizontal line M 1 . 
   The memory circuit  60  stores a plurality of image data DATAA, DATAB, DATAC that specify an image to be displayed on the display. 
   The decoders  70 A,  70 B,  70 C output switching control signals SW_CNTA, SW_CNTB, SW_CNTC associated with the plurality of image data DATAA, DATAB, DATAC stored in the memory circuit  60  to the switches  51 A to  54 C under the control of the control circuit  90 . 
   According to the present exemplary embodiment, the decoders  70 A,  70 B,  70 C and the control circuit  90  cooperate to output (1) activation control signals AP, LP, SE to control activation and deactivation by the logic circuits  21  to  24  to the logic circuits  21  to  24 ; (2) an open/close control signal BP to control the open/close of the switches  41  to  44  to the switches  41  to  44 ; (3) an open/close control signal UP to control the open/close of the switches SWA, SWB, SWC to the switches SWA, SWB, SWC; (4) an open/close control signal DP to control the open/close of the switches swa, swb, swc to the switches swa, swb, swc; and (5) an open/close control signal CP to control the open/close of the switches  51 A to  54 A,  51 B to  54 B,  51 C to  54 C to the switches  51 A to  54 A,  51 B to  54 B,  51 C to  54 C. 
   The switches  80 A,  80 B,  80 C are provided in between the contact points PA, PB, PC, which are included in the display, and the vertical lines LA, LB, LC. For example, the switch  80 A is provided in between the contact point PA and the vertical line LA. 
   The control circuit  90  outputs the above-mentioned control signals AP, LP, SE, BP, CP, UP, DP, so as to control the whole operation of the driver  1 . 
   The switches SWA, SWB, SWC are provided in between the vertical lines LA, LB, LC and the power potential VDD. For example, the switch SWA is provided in between the vertical line LA and the power potential VDD. 
   The switches swa, swb, swc are provided in between the vertical lines LA, LB, LC and the ground potential VSS. For example, the switch swa is provided in between the vertical line LA and the ground potential VSS. 
     FIG. 2  shows the configuration of the logic circuit according to the present exemplary embodiment of the invention. The logic circuit  21  operates at both the power voltage VDD and an operational voltage Vdd (1.5 V, for example) that is lower than the operational voltage VDD of the logic circuit  21 , i.e. the power voltage VDD. The logic circuit  21  detects the power voltage VDD applied to the horizontal line M 1  from the power potential VDD via the switch SWA, at least one of the vertical lines LA, LB, LC, and at least one of the switches  51 A,  51 B,  51 C. To perform this, the logic circuit  21  includes a level shifter  211 , a flip-flop  212 , an AND circuit  213 , a level shifter  214 , and a switch  215  as shown in  FIG. 2 . The level shifter  211 , the flip-flop  212 , and the AND circuit  213  operate at the voltage Vdd, while the level shifter  214  operates at the voltage VDD. 
   The switch  215  establishes or terminates a connection between the horizontal line M 1  and the level shifter  211  according to the activation control signal SE from the control circuit  90 . 
   The level shifter  211  lowers the voltage level of the power voltage VDD applied to the horizontal line M 1 . The flip-flop  212  latches a signal L 1  from the level shifter  211  in sync with the activation control signal LP from the control circuit  90 . The AND circuit  213  performs the logical AND operation between a signal L 2  from the flip-flop  212  and the activation control signal AP from the control circuit  90  to output a signal L 3 . This means that the AND circuit  213  outputs the signal L 3  at a timing specified by the activation control signal AP. The level shifter  214  raises the voltage level of the signal L 3 . Thus the logic circuit  21  outputs a power control signal PS 1  to activate or deactivate the operational amplifier  11 . The other logic circuits  22  to  24  also have the same configuration and operate in the same manner as the logic circuit  21 , outputting power control signals PS 2  to PS 4  to the operational amplifiers  12  to  14 , respectively. 
   Instead of the above-mentioned configuration of the logic circuits  21  to  24 , the logic circuits  21  to  24  are also capable of outputting the control signals PS 1  to PS 4  with the configuration composed of the switch  215 , the flip-flop  212 , and the AND circuit  213  when the power voltage VDD and the operational voltage VDD of the logic circuits  21  to  24  are exactly or nearly the same (for example, both of the voltages VDD and Vdd are around 5 V). 
     FIG. 3  shows the configuration of the memory circuit and the decoders according to the present exemplary embodiment of the invention. To facilitate the description referring to  FIG. 3  and understanding of the memory circuit and the decoders according to the present exemplary embodiment, here the four grayscale levels are replaced by 64 grayscale levels (six bits), the four operational amplifiers  11  to  14  by 64 operational amplifiers OP 0  to OP 63 , and the four switches  51 A to  54 A by 64 switches SWA 0  to SWA 63 . 
   As shown in  FIG. 3 , the memory circuit  60  stores the image data DATAA, DATAB, DATAC. For example, the image data DATAA are composed of image data D 5  to D 0  (six bits) to specify a grayscale level out of the 64 levels and grayscale data GS selected from 2, 4, 8, 16, 32, or 64. Both the image data D 5  to D 0  and the grayscale data GS are given an address. For example, the image data D 5  to D 0  of 000110 and the grayscale data GS of 2 are stored in an address A 0  included in the image data DATAA. The other image data DATAB, DATAC also have the same configuration as the image data DATAA. 
   As shown in  FIG. 3 , the decoder  70 A outputs switching control signals SCA 0  to SCA 63  to control turning on and shutting off of the switches SWA 0  to SWA 63  to the switches SWA 0  to SWA 63  based on the image data D 5  to D 0  and the grayscale data GS included in the image data DATAA stored in the memory circuit  60 . To achieve this, the decoder  70 A includes a converter  71 A to convert the image data D 5  to D 0  and the grayscale data GS into the switching control signals SCA 0  to SCA 63 , and an address counter  72 A to count the number of addresses included in the image data DATAA, as shown in  FIG. 3 . The converter  71 A further includes a conversion table  73 A defining the correspondence among the image data D 5  to D 0 , the grayscale data GS, and the operational amplifiers OP 0  to OP 63 . 
     FIG. 4  shows the configuration of the conversion table according to the present exemplary embodiment of the invention. The conversion table  73 A includes the numbers of the operational amplifiers OP, the values of the image data D 5  to D 0 , and the values of the grayscale data GS as shown in  FIG. 4 . The conversion table  73 A shows that, for example, the image data D 5  to D 0  ranging from 000100 to 000111 with the grayscale data GS of 16 are represented by the marked image data of 000100 corresponding to the operational amplifier OP 4 . In other words, the four grayscale levels ranging from 000100 to 000111 are represented by one marked representative grayscale level 000100 corresponding to the operational amplifier OP 4 . 
   Referring back to  FIG. 3 , the address counter  72 A specifies the address A 0  in the image data DATAA stored in the memory circuit  60 , making the converter  71 A read out the image data D 5  to D 0  and the grayscale data GS corresponding to the address A 0  (the image data D 5  to D 0  and the grayscale data GS corresponding to the address A 0  in the image data DATAA are hereinafter referred to as image data D 5  to D 0  (A_A 0 ) and grayscale data GS (A_A 0 ), and the same goes for the other image data DATAB, DATAC.). With the image data D 5  to D 0  (A_A 0 ) of 000110 and the grayscale data GS (A_A 0 ) of 2, the converter  71 A refers to the column GS=2 of the conversion table  73 A, and specifies the operational amplifier OP 0  that corresponds to the marked representative grayscale level 000000. The converter  71 A outputs the switching control signals SCA 0  to SCA 63  (corresponding to SW_CNTA in  FIG. 1 ) for making the switch SWA 0  for the operational amplifier OP 0  turn on and the other switches SWA 1  to SWA 63  shut off to the switches SWA 0  to SWA 63 , and thereby connecting the vertical line LA (corresponding to the vertical line LA in  FIG. 1 ) and a horizontal line HL 0  (corresponding to any of the horizontal lines M 1  to M 4  in  FIG. 1 ), that is, making a connection between the vertical line LA and the operational amplifier OP 0 . 
   In sync with the output of the switching control signals SCA 0  to SCA 63  based on the image data D 5  to D 0  (A_A 0 ) and the grayscale data GS (A_A 0 ) from the decoder  70 A, the other decoders  70 B,  70 C also output switching control signals SCB 0  to SCB 63 , SCC 0  to SCC 63  based on image data D 5  to D 0  (B_A 0 ), (C_A 0 ) and grayscale data GS (B_A 0 ), (C_A 0 ) to switches SWBO to SWB 63 , SWCO to SWC 63  (the switches not shown, corresponding to the switches  51 B to  54 B,  51 C to  54 C in  FIG. 1 ), respectively, provided in between the horizontal lines HL 0  to HL 63  and the vertical lines LB, LC in the same manner. 
   For example, the switch SWB 0  is made turn on by the switching control signals SCB 0  to SCB 63  based on the image data D 5  to D 0  (B_A 0 ) of 001100 and the grayscale data GS (B_A 0 ) of 2, while the switch SWC 0  is made turn on by the switching control signals SCC 0  to SCC 63  based on the image data D 5  to D 0  (C_A 0 ) of 011011 and the grayscale data GS (C_A 0 ) of 2. Also, since the grayscale data GS (A_A 0 ), (B_A 0 ), (C_A 0 ) are all 2, the operational amplifiers OP 1  to OP 62  other than the operational amplifiers OP 0  and OP 63  remain deactivated. At the same time, only the operational amplifier OP 0  is activated according to the image data D 5  to D 0  (A_A 0 ), (B_A 0 ), (C_A 0 ), while the operational amplifier OP 63  remains deactivated. 
   The address counter  72 A specifies an address A 1  in the image data DATAA stored in the memory circuit  60  following the address A 0 , making the converter  71 A read out image data D 5  to D 0  (A_A 1 ) and grayscale data GS (A_A 1 ) corresponding to the address A 1  from the memory circuit  60 . With the image data D 5  to D 0  (A_A 1 ) of 100001 and the grayscale data GS (A_A 1 ) of 8, the converter  71 A refers to the conversion table  73 A and specifies the operational amplifier OP 36  that corresponds to the marked representative grayscale level 100100. The converter  71 A outputs the switching signals SCA 0  to SCA 63  to make the switch SWA 36  turn on and the other switches SWA 0  to SWA 35  and SWA 37  to SWA 63  shut off to the switches SWA 0  to SWA 63 , and thereby connecting the vertical line LA and the horizontal line HL 36 , that is, making a connection between the vertical line LA and the operational amplifier OP 36 . 
   In the same manner as mentioned above, in sync with the output of the switching control signals SCA 0  to SCA 63  based on the image data D 5  to D 0  (A_A 1 ) and the grayscale data GS (A_A 1 ) from the decoder  70 A, the other decoders  70 B,  70 C also output the switching control signals SCB 0  to SCB 63 , SCC 0  to SCC 63  based on image data D 5  to D 0  (B_A 1 ), (C_A 1 ) and grayscale data GS (B_A 1 ), (C_A 1 ) to the switches SWB 0  to SWB 63 , SWC 0  to SWC 63 , respectively. 
   According to the present exemplary embodiment, for example, when the grayscale data GS (A_A 0 ), GS (B_A 0 ), and GS (C_A 0 ) are all 4, the image data D 5  to D 0  (A_A 0 ) is 000000, D 5  to D 0  (B_A 0 ) is 000001, and D 5  to D 0  (C_A 0 ) is 000010, the decoders  70 A,  70 B,  70 C do not activate all the three operational amplifiers OP 0 , OP 1 , OP 2  corresponding to the grayscale levels of 000000, 000001, 000010, respectively, but activate only the operational amplifier OP 0  corresponding to the grayscale level of 000000 that represents the three grayscale levels. Here, the power consumed by an operational amplifier is the total of stationary power (power consumed irrespective of the size of the load or grayscale level of the operational amplifier) and load power (power consumed depending on the size of the load of the operational amplifier) as widely known. If one operational amplifier takes three grayscale levels, the amount of power it consumes (a total of one stationary power and three load powers) is less than the amount of power consumed by three operational amplifiers each taking a grayscale level (resulting in a total of three stationary powers and three load powers) as with the case of related art methods. Therefore, making the decoders  70 A,  70 B,  70 C activate one operational amplifier OP 0  can reduce the power consumed compared to the related art methods in which the three operational amplifiers OP 0 , OP 1 , OP 2  are all activated. 
     FIG. 5  shows the operation of the driver according to the present exemplary embodiment of the invention. The driver  1  drives a plurality of gate lines (not shown in the drawing) of a display line by line as shown in  FIG. 5 . In other words, a gate line is driven during a horizontal synchronization period (1H) in which a voltage based on a grayscale level specified by the image data D 5  to D 0  (A_A 0 ), (B_A 0 ), (C_A 0 ) etc. via the vertical lines LA, LB, LC corresponding to a plurality of source lines is applied to the plurality of source lines. Since the driving is performed line by line, the decoders  70 A,  70 B,  70 C operate simultaneously, or more specifically, synchronously as described above. For example, the switching control signals SW_CNTA, SW_CNTB, SW_CNTC specified by the image data D 5  to D 0  (A_A 0 ), (B_A 0 ), (C_A 0 ), respectively, are simultaneously output to the switches  51 A to  54 A,  51 B to  54 B,  51 C to  54 C, respectively. Now the operation of the decoder  70 A will be described in greater detail for the better understanding. 
   During a first horizontal synchronization period HSP 1 , the decoder  70 A activates the operational amplifier  11  corresponding to a grayscale level specified by the image data D 5  to D 0  (A_A 0 ), for example, the grayscale level of 4 using the power control signal PS 1  (at high level) in an ON period ONT 1 , while deactivates the other operational amplifiers  12 ,  13 ,  14  using the power control signals PS 2 , PS 3 , PS 4  (all at low level). The decoder  70 A thus provides the grayscale level of 4 on a display. 
   Following the display, at a beginning timing t 1  of an OFF period OFT 1 , the control circuit  90  makes the switches  80 A,  80 B,  80 C shut off using the open/close control signal CP (at low level) to control the open/close of the switches  80 A,  80 B,  80 C, while the logic circuits  21  to  24  deactivate the operational amplifiers  11  to  14  using the power control signals PS 1  to PS 4  (all at low level). Consequently, during the OFF period OFT 1  the vertical lines LA, LB, LC and the contact points PA, PB, PC are close, while the operational amplifiers  11  to  14  remain deactivated. 
   Following the timing t 1 , at a timing t 2  the control circuit  90  makes the switches  41  to  44  turn on using the open/close control signal BP (at high level), that is, making a connection between the horizontal lines M 1 , M 2 , M 3 , M 4  and the ground potential VSS. The control circuit  90  also makes the switches swa, swb, swc turn on using the open/close control signal DP (at high level), that is, making a connection between the vertical lines LA, LB, LC and the ground potential VSS. The former connection allows the discharge of any charge possibly remaining on the horizontal lines M 1 , M 2 , M 3 , M 4 , while the latter connection allows the discharge of any charge possibly remaining on the vertical lines LA, LB, LC. Since only the operational amplifier  11  is activated in the ON period ONT 1  as described above, the charge remains only on the horizontal line M 1  that is coupled to the operational amplifier  11 . The above-mentioned connections discharge the horizontal line M 1  and any of the vertical lines LA, LB, LC coupled to the horizontal line M 1 . 
   After the discharge begins, at a timing t 3  the control circuit  90  outputs the open/close control signal BP (at low level), and thereby making the switches  41  to  44  and the switches swa, swb, swc shut off. 
   At a timing t 4 , the decoder  70 A reads out the image data D 5  to D 0  (A_A 1 ) following the image data D 5  to D 0  (A_A 0 ) from the memory circuit  60 , that is, the image data D 5  to D 0  (A_A 1 ) to specify a grayscale level to be displayed in the next horizontal synchronization period or a second horizontal synchronization period HSP 2 . Then the decoder  70 A outputs the switching control signal SW_CNTA corresponding to the image data D 5  to D 0  (A_A 1 ) to the switches  51 A to  54 A, and thereby connecting the vertical line LA and one operational amplifier that is selected from the operational amplifiers  11  to  14  and corresponds to the grayscale level to be achieved based on the image data D 5  to D 0  (A_A 1 ). The following description assumes that a connection between the vertical line LA and the operational amplifier  12  is made by turning on and shutting off of the switches  51 A to  54 A according to the switching control signal SW_CNTA based on the grayscale level of 3 specified by the image data D 5  to D 0  (A_A 1 ). 
   At a timing t 5 , the control circuit  90  turns on the switches SWA, SWB, SWC using the open/close control signal UP (at high level), that is, making a connection between the vertical lines LA, LB, LC and the power potential VDD, and thereby setting the vertical lines LA, LB, LC to have the power potential VDD. Since the operational amplifier  12  has a connection to the vertical line LA as mentioned above, the output terminal of the operational amplifier  12 , i.e. the horizontal line M 2  is set to have the power potential VDD, which means to be charged, via the vertical line LA and the switch  52 A. 
   At this timing t 5 , the control circuit  90  couples the horizontal lines M 1  to M 4  to the logic circuits  21  to  24 , respectively, all at once using the switching control signal SE (at high level). For example, the control circuit  90  couples the horizontal line M 1  to the logic circuit  21  as shown in  FIG. 2 . 
   At a timing t 6 , the control circuit  90  outputs the activation control signals LP, AP to the logic circuits  11  to  14 . With the rising edge of the activation control signals LP, AP, the logic circuits  21  to  24  identify whether the power potential VDD is on the horizontal lines M 1  to M 4 , in other words, which of the horizontal lines M 1  to M 4  is charged. 
   As mentioned above, only the horizontal line M 2  among the horizontal lines M 1  to M 4  is charged to have the power potential VDD. Therefore, only the logic circuit  22  detects the power potential VDD on the horizontal line M 2 , and as a result it applies the power control signal PS 2  (at high level) to the operational amplifier  12  and recognizes that the operational amplifier  12  is to be activated. Detecting no power potential VDD on the horizontal lines M 1 , M 3 , M 4 , the other logic circuits  21 ,  23 ,  24  apply the power control signals PS 1 , PS 3 , PS 4  (at low level) to the operational amplifiers  11 ,  13 ,  14  and recognize that the operational amplifiers  11 ,  13 ,  14  are to be deactivated. 
   At a beginning timing t 7  of an ON period ONT 2  of the second horizontal synchronization period HSP 2  following the first horizontal synchronization period HSP 1 , the logic circuit  22  activates the operational amplifier  12  using the power control signal PS 2  (at high level), while the logic circuits  21 ,  23 ,  24  deactivate the operational amplifiers  11 ,  13 ,  14  using the power control signals PS 1 , PS 3 , PS 4  (at low level). Also at this timing t 7 , the control circuit  90  turns on the switches SWA, SWB, SWC using the open/close control signal CP (at high level), that is, making a connection between the vertical lines LA, LB, LC and the output terminals PA, PB, PC. As a result, the voltage Vq from the operational amplifier  12  is output by the output terminal PA via the horizontal line M 2 , the switch  52 A, and the vertical line LA. 
   As mentioned above, the driver  1  of the present exemplary embodiment includes the control circuit  90 , the decoder  70 A, and the logic circuits  21  to  24  cooperating to recognize that, during the OFF period OFT 1  of the first horizontal synchronization period HSP 1  based on the image data D 5  to D 0  (A_A 1 ) to be displayed during the second horizontal synchronization period HSP 2 , only the operational amplifier  12  is to be activated and the other operational amplifiers  11 ,  13 ,  14  are to be deactivated during the ON period ONT 2  of the second horizontal synchronization period HSP 2 . Thus, the operational amplifier  12  is activated, while the other operational amplifiers  11 ,  13 ,  14  are deactivated at the beginning timing t 7  of the ON period ONT 2 . This makes it possible to reduce the amount of power consumed compared to related art drivers that always activate all the operational amplifiers  11  to  14 . 
   In addition to the above-mentioned activation of the operational amplifier  12  by the decoder  70 A during the OFF period OFT 1  of the first horizontal synchronization period HSP 1 , the decoder  70 B, which synchronizes with the decoder  70 A, and the logic circuits  21  to  24  cooperate to recognize that, during the OFF period OFT 1  of the first horizontal synchronization period HSP 1  based on the image data D 5  to D 0  (B_A 1 ) to be displayed during the second horizontal synchronization period HSP 2 , only the operational amplifier  11 , for example, is to be activated during the ON period ONT 2  of the second horizontal synchronization period HSP 2 . Furthermore, the decoder  70 C, which synchronizes with the decoders  70 A,  70 B, and the logic circuits  21  to  24  cooperate to recognize that, during the OFF period OFT 1  of the first horizontal synchronization period HSP 1  based on the image data D 5  to D 0  (C_A 1 ) to be displayed during the second horizontal synchronization period HSP 2 , only the operational amplifier  12 , for example, is to be activated during the ON period ONT 2  of the second horizontal synchronization period HSP 2 . In this case, the logic circuits  21  to  24  activate only the operational amplifiers  11 ,  12  at the beginning timing t 7  of the ON period ONT 2  of the second horizontal synchronization period HSP 2 . To put it another way, during the OFF period OFT 1  of the first horizontal synchronization period HSP 1 , the driver  1  identifies which of the operational amplifiers  11  to  14  is to be required during the ON period ONT 2  of the second horizontal synchronization period HSP 2  based on the plurality of image data D 5  to D 0  (A_A 1 ), (B_A 1 ), (C_A 1 ) to be displayed during the second horizontal synchronization period HSP 2 , and activates only the required one at the timing t 7 . This makes it possible to reduce the amount of power consumed compared to related art drivers that always activate all the operational amplifiers  11  to  14   
   First Exemplary Modification 
   Instead of the above-mentioned operational structure, in which in sync with the timing the decoder  70 A outputs the switching control signal SW_CNTA corresponding to the image data D 5  to D 0  (A_A 1 ) to the switches  51 A to  54 A, the other decoders  70 B,  70 C output the switching control signals SW_CNTB, SW_CNTC corresponding to the image data D 5  to D 0  (B_A 1 ), (C_A 1 ) to the switches  51 B to  54 B,  51 C to  54 C, respectively, the following operational structure is also conceivable. During the OFF period OFT 1  of the first horizontal synchronization period HSP 1  as shown in  FIG. 6 , the decoders  70 A,  70 B,  70 C may sequentially output the switching control signals SW_CNTA, SW_CNTB, SW_CNTC to the switches  51 A to  54 A,  51 B to  54 B,  51 C to  54 C, respectively. More specifically, during the OFF period OFT 1 , a cycle of operations from the timing t 1  to the timing t 7  shown in  FIG. 5  is executed sequentially for the vertical lines LA, LB, LC in this order. Like the above-mentioned exemplary embodiment, this makes it possible to identify which of the operational amplifiers  11  to  14  is required to be activated, and moreover, to what degree each required operational amplifier is to be activated. 
   For example, the decoder  70 A outputs the switching control signal SW_CNTA corresponding to the image data D 5  to D 0  (A_A 1 ), making the logic circuit  21  recognize that the operational amplifier  11  is to be activated for one vertical line. Then the decoder  70 B outputs the switching control signal SW_CNTB corresponding to the image data D 5  to D 0  (B_A 1 ), making the logic circuit  22  recognize that the operational amplifier  12  is to be activated for one vertical line. Subsequently, the decoder  70 C outputs the switching control signal SW_CNTC corresponding to the image data D 5  to D 0  (C_A 1 ), making the logic circuit  22  recognize that the operational amplifier  12  is to be activated for another vertical line, which means that the operational amplifier  12  is to be activated for two vertical lines in total. Therefore, the logic circuits  21  to  24  recognize that for how many vertical lines each required operational amplifier is to be activated. This makes it possible to control the degree of activation using the power control signals PS 1  to PS 4 , and thereby increasing accuracy in the activation and decreasing the amount of power consumed compared to the above-mentioned exemplary embodiment. 
   Second Exemplary Modification 
   Instead of the operational structure of the first exemplary modification, another operational structure is also conceivable in which the decoders  70 A,  70 B,  70 C, i.e. the switching control signals SW_CNTA, SW_CNTB, SW_CNTC, are divided into a plurality of blocks BL 1 , BL 2 , BL 3  (not limited to the three) as shown in  FIG. 7 . For example, the block BL 1  is composed of the decoders  70 A,  70 B,  70 C,  70 D. 
   In addition, during the OFF period OFT 1 , a cycle of operations from the timing t 1  to the timing t 7  shown in  FIG. 5  is executed sequentially for the blocks BL 1 , BL 2 , BL 3  in this order. Moreover, the switching control signal SW_CNT from the decoder  70 , more specifically, the switching control signals SW_CNTA, SW_CNTB, SW_CNTC, SW_CNTD from the decoder  70 A are output all at once. These allow a reduction in power consumed compared to the above-mentioned exemplary embodiment. 
   For example, during the OFF period OFT 1  of the first horizontal synchronization period HSP 1 , the decoders  70 A to  70 D output the switching control signals SW_CNTA to SW_CNTD all at once, making the logic circuits  21  to  24  recognize that the operational amplifiers  11 ,  12  are to be activated. Then, decoders  70 E to  70 H output switching control signals SW_CNTE to SW_CNTH all at once, making the logic circuits  21  to  24  recognize that the operational amplifiers  11 ,  13  are to be activated. Subsequently, decoders  70 I to  70 L output switching control signals SW_CNTI to SW_CNTL, making the logic circuits  21  to  24  recognize that the operational amplifiers  11 ,  12  are to be activated. In this case, the operational amplifier  11  needs to take the three blocks BL 1 , BL 2 , BL 3 , and is required to be activated for 12 vertical lines at most (four lines×three blocks); the operational amplifier  12  needs to take the two blocks BL 1 , BL 3 , and is required to be activated for eight vertical lines at most (four lines×two blocks); the operational amplifier  13  needs to take the one block BL 2 , and is required to be activated for four vertical lines at most (four lines×one block); and the operational amplifier  14  is not required to be activated at all. 
   Therefore, the logic circuit  21  activates the operational amplifier  11  for  12  vertical lines using the power control signal PS 1 , the logic circuit  22  activates the operational amplifier  12  for eight vertical lines using the power control signal PS 2 , the logic circuit  23  activates the operational amplifier  13  for four vertical lines using the power control signals PS 3 , and the logic circuit  24  deactivates the operational amplifier  14  using the power control signal PS 4 . The total amount of power consumed in the second modification is for 24 vertical lines (12+8+4+0), which is less than that of related art drivers that always activate the operational amplifiers  11  to  14  each for 12 vertical lines, that is, consuming power for 48 vertical lines (12 lines×four operational amplifiers).