Abstract:
A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to phase-change memory devices and methods for writing phase-change memory cells. More particularly, the present invention relates to phase-change memory devices and methods of writing phase-change memory devices in which write current pulse characteristics are varied according to a load of a phase-change cell to be written.  
         [0003]     2. Description of the Related Art  
         [0004]     Phase change memory cell devices rely on phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The differing resistance values exhibited by the two phases are used to distinguish logic values of the memory cells. That is, an amorphous state exhibits a relatively high resistance, and a crystalline state exhibits a relatively low resistance.  
         [0005]      FIG. 1  illustrates a phase-change memory cell in an amorphous state  52 - 1  and in a crystalline state  52 - 2 . The phase-change memory cell may be part of a Phase-change Random Access Memory (PRAM). The phase-change memory cell  52  includes a phase-change layer  55  between a bottom electrode (BE)  54  and an upper electrode (UE)  56 . The phase-change layer  55  is formed of a phase-change material, such as a chalcogenide alloy (GST). A bit line (BL) is coupled to the upper electrode  56 . The bottom electrode  54  is coupled to ground through transistor NT. A word line (WL) is coupled to the gate of transistor NT.  
         [0006]     When phase-change memory cell  52  is in an amorphous state  52 - 1 , a portion of the phase-change layer  55  is amorphous. Likewise, when phase-change memory cell  52  is in a crystalline state  52 - 2 , the portion of the phase-change layer  55  is crystalline. As shown by the equivalent circuit diagram in  FIG. 1 , the phase-change material layer  55  is SET (ST 1 ) to the crystalline state or RESET (ST 2 ) to the amorphous state depending on an electrical current applied via the bit line BL.  
         [0007]     As would be appreciated by one skilled in the art, the terms “amorphous state” and “crystalline state” are not absolute characterizations of the phase-change material. Rather, when a portion of the phase-change material is said to be in an amorphous state (i.e. a RESET state), this means that the material is sufficiently amorphous to take on a resistive value R 1  which may be readily distinguished from a resistive value R 2  of the material in the crystalline state (SET state). Conversely, when a portion of the phase-change material is said to be in a crystalline state (SET state), this means that the material is sufficiently crystalline to take on a resistive value which may be readily distinguished from the resistive value of the material in the amorphous state (RESET state).  
         [0008]      FIG. 2  illustrates the temperature characteristics of a phase-change memory cell in a set programming operation and a reset programming operation. A set programming operation causes a phase-change material layer of a phase-change memory cell to crystallize, thus decreasing the resistivity of the phase-change material layer. Likewise, a reset programming operation causes a phase-change material layer of a phase-change memory cell to become amorphous, thus increasing the resistivity of the phase-change material layer.  
         [0009]     As illustrated in  FIG. 2 , the programming of a phase-change memory cell is dependent on the temperature of the phase-change memory cell. An amorphizing (RESET) temperature pulse includes a rising portion  12 , a peak portion  10 , and a declining portion  14 . In order to reset a phase-change memory cell, using an amorphizing (RESET) pulse, the phase change material layer is heated above its melting point (Tm) by a resistive heater for a relatively short period of time. Between time T 0  and time T 1 , the temperature of the phase-change material layer is rapidly increased to a temperature above the melting point (Tm) of the phase-change material layer. During the declining portion  14 , the phase-change material layer is rapidly cooled, thus causing the phase-change material layer to become relatively amorphous. In other words, raising the temperature of the phase-change material layer above its melting point (Tm) causes crystal structures in the phase-change material to be broken apart. Because the phase-change material layer is cooled rapidly, there is little opportunity for crystals to form in the phase-change material layer before the phase-change material layer becomes solid in a relatively amorphous state.  
         [0010]     Likewise, a crystallizing (SET) temperature pulse includes a rising portion  22 , a peak portion  20 , and a declining portion  24 . In order to set a phase-change memory cell, using a crystallizing (SET) pulse, the phase change material layer is heated above its crystallization point (Tx) by a resistive heater for a relatively short period of time (e.g. 50 ns), which is longer than the period of time that the temperature is raised during a amorphizing (RESET) temperature pulse. Between time T 0  and time T 2 , the temperature of the phase-change material layer is rapidly increased to above the crystallization point (Tx) of the phase-change material layer and crystallization occurs. During the declining portion  24 , the phase-change material layer is rapidly cooled, thus causing the phase-change material layer to set in a relatively crystalline state.  
         [0011]      FIG. 3  comparatively illustrates the RESET current pulse G 1  and the SET current pulse G 2 . The RESET current pulse G 1 , which is a relatively short pulse of magnitude I-RESET, causes the temperature of the phase-change material to RESET the material into an amorphous state as shown above in  FIG. 2 . The SET current pulse G 2 , which is a relatively long pulse of magnitude I-SET (where I-SET is less than I-RESET), causes the temperature of the phase-change material to SET the material into crystalline state as shown above in  FIG. 2 .  
         [0012]      FIG. 4  illustrates a memory  100  having a phase-change memory cell array  160 . As shown, the cell array  160  includes a plurality of memory blocks, namely, Block(A 00 )  160   a,  Block(A 01 )  160   b,  Block(A 10 )  160   c,  and Block (A 11 )  160   d.  Each memory block includes a plurality phase-change memory cells commonly connected to a word lines WLi, WLj, WLk, and WLl respectively contained in the memory blocks.  
         [0013]     Buffers  110 _ 1  and  110 _ 2  receive addressing signals A 0  and A 1 . The address signals A 0  and A 1  are decoded by a pre-decoder  120  to generate decoded signals A 00 _DEC, A 01 _DEC, A 10 _DEC, and A 11 _DEC, which in turn are decoded by a main decoder  140  to output block selection signals A 00 , A 01 , A 10  and A 11 . The block selection signals A 00 , A 01 , A 10  and A 11  drive word lines WLi, WLj, WLk, and WLl of memory blocks  160   a,    160   b,    160   c,  and  160   d,  respectively.  
         [0014]     A write driver  130  outputs a SET or RESET write current pulse SDL according to a programming signal SET(RESET)_CON_PULSE and a data signal DIN from buffer  111 . A column decoder  150  then supplies the write current pulse SDL to the memory blocks  160   a,    160   b,    160   c,  and  160   d.    
         [0015]     As illustrated in example  FIG. 4 , memory block  160   d  is closer to decoder  150  than memory cell block  160   a.  Accordingly, different loads are present from decoder  150  to the memory blocks  160   a,    160   b,    160   c,  and  160   d.  These loads are represented in the figure by resistive elements R 1 , R 2 , R 3  and R 4 .  
         [0016]     The differing loads of the memory blocks  160   a,    160   b,    160   c,  and  160   d,  result in different write conditions of the phase change memory cells of the memory blocks. This is explained with reference to  FIGS. 5 through 7 .  
         [0017]      FIG. 5  is a simplified diagram illustrating the different set programming pulses (e.g. SET_CON_PULSE) applied to the phase-change memory cell blocks  160   a,    160   b,    160   c,  and  160   d  of the memory array  160 . As can be seen from  FIG. 5 , the set programming pulses all have the same pulse width.  
         [0018]      FIG. 6  illustrates the RESET resistance distribution regions of the phase-change memory cells in blocks  160   a,    160   b,    160   c,  and  160   d.  As the load of the memory blocks is increased, the resistance distribution region is decreased. In order to avoid write errors, the RESET write current pulse must be capable of writing the highest-load memory block  160   a  such that the lowest resistance distribution region (Region (A 00 )) is fully in a RESET region. Since the memory block  160   d  has the lowest load, a relatively strong RESET write current pulse is applied to memory cells of the memory block  160   d.  As such, a relatively high crystalline state is achieved which results in a relatively high resistance distribution region (Region (A 11 )). Conversely, the memory block  160   a  with the greatest load will exhibit a relatively low resistance distribution region (Region (A 00 ).  
         [0019]      FIG. 7  illustrates the SET resistance distribution regions of the phase-change memory cells in blocks  160   a,    160   b,    160   c,  and  160   d.  Again, as the load of the memory blocks is increased, the resistance distribution region is decreased. In order to avoid write errors, the SET write current pulse must be capable of writing the lowest-load memory block  160   d  such that the highest resistance distribution region (Region (A 11 )) is fully in a SET region. Otherwise, SET failures will occur in the portion WIN of the distribution region of the nearest block (Region (A 11 ). Thus, in order to bring the Region (A 11 ) fully into the SET region, the phase-change memory cells of the Region (A 00 ) become “over-programmed”. That is, power is unnecessarily expended with regards to the SET programming of the phase-change memory cells associated with Region (A 00 ). Further, additional power is needed to bring the same memory cells back into the RESET region during RESET programming.  
       SUMMARY OF THE INVENTION  
       [0020]     According to an aspect of the present invention, a phase-change cell memory device is provided which includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.  
         [0021]     According to another aspect of the present invention, a phase-change cell memory device is provided which includes a plurality of memory cell blocks, an address circuit, a write driver, and a write driver control circuit. The memory cell blocks each include a plurality of phase-change memory cells, and each of the phase-change memory cells includes a volume of material that is programmable between amorphous and crystalline states. The address circuit selects each of the memory cell blocks, and the write driver selectively generates a reset pulse current to program memory cells of a memory cell block selected by the address circuit into the amorphous set state, and a set pulse current to program memory cells of the memory cell block selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least of the set and reset pulse currents according to the memory cell block selected by the address circuit.  
         [0022]     According to still another aspect of the present invention, a phase-change cell memory device is provided which includes a phase-change memory cell array, an address decoder, a bit line selection circuit, a write driver, and a write driver control circuit. The phase-change memory cell array includes a plurality of word lines, a plurality of bit lines, and a plurality of phase-change cells at respective intersection regions of the word lines and bit lines, where the memory cell array is defined by a plurality of memory blocks each including at least one word line, and where each of the phase-change memory cells includes a volume of material that is programmable between amorphous and crystalline states. The address decoder decodes an input row address to select a word line of each memory block, and to select one of the memory blocks. The bit line selection circuit selects at least one bit line according to an input column address. The write driver selectively generates a reset pulse current to program a memory cell at the intersection of the selected bit line and the selected word line within the selected memory block into the amorphous set state, and a set pulse current to program a memory cell at the intersection of the selected bit line and the selected word line within the selected memory block into the crystalline state. The write driver control circuit varies at least one a pulse width and a pulse count of at least one of the set and reset pulse currents according to the memory cell block selected by the address decoder.  
         [0023]     According to yet another aspect of the present invention, a method is provided of programming a phase-change memory device having a plurality of phase-change memory cells each including a volume of material that is programmable between amorphous and crystalline states. The method includes using a write driver to selectively generate a reset pulse current to program the memory cells selected by an address circuit into the amorphous state, and a set pulse current to program the memory cells selected by the address circuit into the crystalline state, and varying at least one of a pulse width and a pulse count of the reset and set pulse currents according to a load between the write driver and the memory cells being programmed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]     The above and other aspects and features of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which:  
         [0025]      FIG. 1  is an illustration of a phase-change memory cell in an amorphous state and a crystalline state;  
         [0026]      FIG. 2  is a graph illustrating the temperature characteristics of a phase-change memory cell in response to a reset programming signal and a set programming signal;  
         [0027]      FIG. 3  is a graph illustrating the write current pulses of a reset programming signal and a set programming signal;  
         [0028]      FIG. 4  is a circuit diagram of a phase-change memory cell device;  
         [0029]      FIG. 5  illustrates set programming pulses applied to the phase-change memory cell blocks;  
         [0030]      FIG. 6  illustrates RESET resistance distribution regions of phase-change memory cells in different memory blocks;  
         [0031]      FIG. 7  illustrates SET resistance distribution regions of phase-change memory cells in different memory blocks;  
         [0032]      FIG. 8  is a circuit diagram of a phase-change memory cell device according to an embodiment of the present invention;  
         [0033]      FIG. 9  illustrates set programming pulses applied to the phase-change memory cell blocks according to an embodiment of the present invention;  
         [0034]      FIG. 10  illustrates RESET resistance distribution regions of phase-change memory cells in different memory blocks according to an embodiment of the present invention;  
         [0035]      FIG. 11  illustrates SET resistance distribution regions of phase-change memory cells in different memory blocks according to an embodiment of the present invention;  
         [0036]      FIG. 12  is a circuit diagram of a pre-decoder according to an embodiment of the present invention;  
         [0037]      FIG. 13  is a circuit diagram of a set control pulse generator according to an embodiment of the present invention;  
         [0038]      FIG. 14  is a circuit diagram of a multiplexer according to an embodiment of the present invention;  
         [0039]      FIG. 15  is a circuit diagram of a write driver according to an embodiment of the present invention, where the write driver is in a RESET operation;  
         [0040]      FIG. 16  is a circuit diagram of a write driver according to an embodiment of the present invention, where the write driver is in a SET operation;  
         [0041]      FIG. 17  is a timing diagram for describing the generation of set programming pulses according to an embodiment of the present invention;  
         [0042]      FIG. 18  is a circuit diagram of a main decoder, column decoder, and memory array according to an embodiment of the present invention;  
         [0043]      FIG. 19  illustrates set programming pulses applied to the phase-change memory cell blocks according to another embodiment of the present invention;  
         [0044]      FIGS. 20 and 21  are circuit diagrams of a pre-decoder according to another embodiment of the present invention;  
         [0045]      FIG. 22  is a timing diagram for describing the generation of set programming pulses according to another embodiment of the present invention;  
         [0046]      FIG. 23  is a circuit diagram of a set control pulse generator according to another embodiment of the present invention;  
         [0047]      FIG. 24  illustrates reset programming pulses applied to the phase-change memory cell blocks according to yet another embodiment of the present invention;  
         [0048]      FIG. 25  illustrates reset programming pulses applied to the phase-change memory cell blocks according to yet another embodiment of the present invention; and  
         [0049]      FIGS. 27 and 28  are timing diagrams for describing the generation of reset programming pulses according to other embodiments of the present invention; 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0050]     The present invention is generally characterized by controlling a write driver of a phase-change memory device such that at least one of a pulse width and a pulse count of at least one of RESET and SET pulse currents are varied according to a load between the write driver and an addressed memory cell. In this manner, over-programming of memory cells can be avoided, thus reducing the power consumption needed to reliably write the cells into the SET and/or RESET states.  
         [0051]     The present invention will now be described in detail by way of several preferred but non-limiting embodiments.  
         [0052]      FIG. 8  is a circuit diagram of a phase-change memory cell device  200  according to an exemplary embodiment of the present invention. As shown, the phase-change memory cell device  200  includes address buffers  210 _ 1  and  210 _ 2 , a input data buffer (DIN BUF)  211 , a write enable buffer  212 , a pre-decoder  220 , a write driver  230 , a main decoder  240 , a memory array  260 , a SET control pulse generator  270 , a multiplexer (MUX)  280 .  
         [0053]     The input buffer  210 _ 1  receives an input address signal XA 0  and outputs buffered address signals A 0 P and A 0 PB to the pre-decoder  220 . Likewise, the input buffer  210 _ 2  receives an input address signal XA 1  and outputs buffered address signals A 1 P and A 1 PB to the pre-decoder  220 . Further, the write enable signal buffer  212  receives write enable signal XWE and outputs buffered write enable signal WEb to the pre-decoder  220  and the multiplexer  280 .  
         [0054]     The pre-decoder  220  receives the buffered address signals A 0 P, A 0 PB, A 1 P and ALPB, and the buffered write enable signal WEb, and outputs decoded address signals A 00 _DEC, A 01 _DEC, A 10 _DEC, and A 11 _DEC to the main decoder  240 , and further outputs decoded write control signals WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC to the multiplexer  280 . In this exemplary embodiment, the decoded write control signals WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC indicate which one of the blocks  260   a,    260   b,    260   c,  and  260   d  of the memory array  260  is being written.  
         [0055]     The main decoder  240  receives the decoded signals A 00 _DEC, A 01 _DEC, A 10 _DEC, and A 11 _DEC, and outputs block selection signals A 00 , A 01 , A 10  and A 11 . The block selection signals A 00 , A 01 , A 10  and A 11  drive word lines WLi, WLj, WLk, and WLl of the blocks  260   a,    260   b,    260   c,  and  260   d,  respectively, of the memory array  260 .  
         [0056]     The SET control pulse generator  270  is responsive to an address transition detection (ADT) signal to generate a plurality of SET_PULSEs having different pulse widths, namely, SET_PULSE (A 00 ), SET_PULSE (A 01 ), SET_PULSE (A 10 ), and SET_PULSE (A 11 ). As will be explained later in more detail, these different SET_PULSEs are selectively used to set the pulse width of a write SET current pulse applied to the memory array  260 .  
         [0057]     The multiplexer  280  selects and outputs (as SET_CON_PULSE) one of the SET_PULSE (A 00 ), SET_PULSE (A 01 ), SET_PULSE (A 10 ), and SET_PULSE (A 11 ), according to the buffered write enable signal WEb and the decoded write control signals WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC. More specifically, when enabled by the buffered write enable signal WEb, the multiplexer  280  outputs the SET_PULSE (A 00 ) when WE_A 00 _DEC is active; the multiplexer outputs the SET_PULSE (A 01 ) when WE_A 01 _DEC is active; the multiplexer outputs the SET_PULSE (A 10 ) when WE_A 10 _DEC is active; and the multiplexer outputs the SET_PULSE (A 11 ) when WE_A 11 _DEC is active. Note that only one of WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC is active at any given time.  
         [0058]     Depending on the input data signal (DIN) from the input buffer  211 , the write driver  230  outputs a write current pulse (SDL) according to either the SET current control pulse SET_CON_PULSE (from the multiplexer  280 ) or a RESET current control pulse RESET_CON_PULSE. For example, if the data to be written is LOW, the write driver outputs a SET programming write current pulse having a pulse width defined by SET_CON_PULSE. On the other hand, if the data to be written is HIGH, the write driver outputs a RESET programming write current pulse having a pulse width defined by RESET_CON_PULSE. Also, as will be explained later, the write driver  230  outputs a higher current for the RESET programming than for the SET programming (i.e., Ireset&gt;Iset).  
         [0059]     Column decoder  250  supplies the write current pulse SDL from the write driver  230  to selected columns of the memory blocks  160   a,    160   b,    160   c,  and  160   d.    
         [0060]      FIG. 9  illustrates the different pulse widths of SET current control signals (SET_CON_PULSE) which define the pulse widths of the SET write current pulses applied to respective blocks  260   a,    260   b,    260   c,  and  260   d,  of the phase-change memory cell array  260 . As illustrated in  FIG. 9 , the pulse width of a SET current signal input into a far block ( 260   a ) is shorter than the pulse width of a SET current signal input into a near block ( 260   d ).  
         [0061]     By applying a shorter pulse current width to the far block  260   a,  over-programming of the memory cells of that block during the SET write operation is avoided. This is graphically illustrated in  FIGS. 10 and 11 . Assume that the resistance distribution regions during the RESET state are as shown in  FIG. 10 . Assume next that the SET write operation is carried out using the set current pulses shown in  FIG. 9 . The resultant resistance distribution regions in the SET state are shown in  FIG. 11 . When compared to previously discussed  FIG. 7 , the resistance distribution regions are more compacted, and accordingly, less power is needed to bring the far block  260   a  back to the RESET region.  
         [0062]      FIG. 12  is a circuit diagram of a pre-decoder  220  according to an embodiment of the present invention. In this specific example, the pre-decoder  220  includes NAND gates ND 1 , ND 2 , ND 3 , and ND 4 ; NOR gates NOR 1 , NOR 2 , NOR 3 , and NOR 4 ; and inverters IN 1 , IN 2 , IN 3 , IN 4 , IN 5 , IN 6 , IN 7 , IN 8 , IN 9 , IN 10 , IN 11 , and IN 12 . As shown, the pre-decoder  220  receives the buffered address signals A 0 P, A 0 PB, A 1 P and A 1 PB, and the buffered write enable signal WEb, and outputs-decoded address signals A 00 _DEC, A 01 _DEC, A 10 _DEC, and A 11 _DEC, and decoded write control signals WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC. In this example, only one of the decoded write control signals WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC is HIGH when the buffered write enable signal WEb is LOW.  
         [0063]      FIG. 13  is a circuit diagram of the SET control pulse generator  270  according to an embodiment of the present invention. In this specific example, SET control pulse generator includes NAND gates ND 1 , ND 2 , ND 3 , and ND 4 ; NOR gate NOR 1 ; delay circuits D 1 , D 2 , D 3 , and D 4 ; and inverters IN 1 , IN 2 , IN 3 , IN 4 , and IN 5 . As should be apparent, the circuit of  FIG. 13  is configured to output SET_PULSE_SIGNALs of different pulse widths as illustrated in  FIG. 9 .  
         [0064]      FIG. 14  is a circuit diagram of the multiplexer  280  according to an embodiment of the present invention. The multiplexer  280  of this specific example includes transmission gates PG 1 , PG 2 , PG 3 , and PG 4 ; inverters IN 1 , IN 2 , IN 3 , IN 4 , IN 5 , and IN 6 ; and transistor NM 1 . When the buffered write enable signal WEb is LOW, one of the SET_PULSES (A 00 ), (A 01 ), (A 10 ), or (A 11 ) is output as the SET_CON_PULSE when a respective one of the decoded write control signals WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC is HIGH.  
         [0065]      FIG. 15  is a circuit diagram of a write driver  230  according to an embodiment of the present invention. The “H”, “L”, “OFF” and “ON” designations in the figure denote a RESET programming operation where the input data is HIGH.  FIG. 16  is the same as  FIG. 15 , expect that “H”, “L”, “OFF” and “ON” designations in the figure denote a SET programming operation where the input data is LOW.  
         [0066]     In the specific example of  FIGS. 15 and 16 , the write driver circuit  230  includes a logic circuit  231 , a current mirror  233 , and an output circuit  235 . The logic circuit  231  includes transmission gates PG 1  and PG 2  and inverters IN 1 , IN 2 , IN 3 , and IN 4 . The current mirror  233  includes transistors NM 1 , NM 2 , NM 3 , NM 4 , NM 5 , PM 1 , and PM 2 . The output circuit  235  includes transistors PM 3  and NM 6 , and inverter IN 5 .  
         [0067]     Referring to  FIG. 15 , in the RESET programming operation, the input data (DATA) is HIGH, which turns off the transmission gate PG 1 . In the case where the RESET_CON_PULSE is LOW, the output of inverter IN 4  of the logic circuit  231  is LOW. As such, transistor NM 6  is ON, and transistor NM 5  is OFF, and the node ND 2  becomes LOW (ground). As a result, the output current SDL becomes Ireset=0 as shown. On the other hand, when the RESET_CON_PULSE is HIGH, the output of inverter IN 4  of the logic circuit  231  is HIGH, and the transistor NM 6  is turned OFF. Further, since DATA is HIGH, the output of inverter IN 2  of the logic circuit  231  is HIGH, and the transistors NM 3  and NM 4  of the current mirror  233  are turned ON. As a result, the output current SDL becomes Ireset=i 1 +i 2  as shown.  
         [0068]     Referring to  FIG. 16 , in the SET programming operation, the input data (DATA) is LOW, which turns off the transmission gate PG 2 . In the case where the SET_CON_PULSE is LOW, the output of inverter IN 4  of the logic circuit  231  is LOW. As such, transistor NM 6  is ON, and transistor NM 5  is OFF, and the node ND 2  becomes LOW (ground). As a result, the output current SDL becomes Iset=0 as shown. On the other hand, when the SET_CON_PULSE is HIGH, the output of inverter IN 4  of the logic circuit  231  is HIGH, and the transistor NM 6  is turned OFF. Further, since DATA is LOW, the output of inverter IN 2  of the logic circuit  231  is LOW, and the transistors NM 3  and NM 4  of the current mirror  233  are turned OFF. As a result, the output current SDL becomes Iset=i 1  as shown.  
         [0069]      FIG. 17  illustrates a timing diagram for explaining the generation of the SET programming pulse SET_CON_PULSE. As shown in this figure, the buffer write enable signal WEb is HIGH when the write enable signal XWE is HIGH. Further, responsive to the falling edge of the address transition detection (ATD) signal, the SET_CON_PULSE signal is generated. The SET_CON_PULSE signal corresponds to SET_PULSE (A 00 ) when WEb is LOW and WE_A 00 _DEC is HIGH; the SET_CON_PULSE signal corresponds to SET_PULSE (A 01 ) when WEb is LOW and WE_A 01 _DEC is HIGH; the SET_CON_PULSE signal corresponds to SET_PULSE (A 10 ) when WEb is LOW and WE_A 10 _DEC is HIGH; and the SET_CON_PULSE signal corresponds to SET_PULSE (A 11 ) when WEb is LOW and WE_A 11 _DEC is HIGH.  
         [0070]     For completeness of the explanation,  FIG. 18  shows a detailed circuit diagram of phase-change random access memory (PRAM), including pre-decoders  220 - 1 ,  220 - 2 ,  220 - 3  and  220 - 4 , a main decoder  240 , column decoder  250 , and a memory array according to an embodiment of the present invention. In this example, each block (BLK) of the memory array is comprised of 256 word lines (WL), with each word line WL coupled to a plurality of phase-change memory cells.  
         [0071]     Outputs from the pre-decoders  220 - 1 ,  220 - 2 ,  220 - 3  through  220 -n are applied to NOR elements of the main decoder  240 , together with inverted decoded address signals from inverters I 1  . . . In. The outputs of the NOR elements drive respective word lines WL. The column decoder  250  includes a plurality of select transistors T 1  through Tn coupled between a corresponding write driver  230 - 1  . . .  230 -n and bit lines BL 0  . . . BLn.  
         [0072]     The above-described first embodiment is generally characterized by controlling a write driver of a phase-change memory device such that the pulse width the SET pulse currents is varied according to a load between the write driver and an addressed memory cell. In this manner, over-programming of memory cells can be avoided, thus reducing the power consumption needed to reliably write the cells into the SET and RESET states.  
         [0073]      FIG. 19  illustrates an alternative to the first embodiment. That is, according to the second embodiment of  FIG. 19 , the write driver of the phase-change memory device is controlled such that the pulse count of the SET pulse currents is varied according to the load between the write driver and an addressed memory cell. As shown, different pulse counts of SET current control signals (SET_CON_PULSE) define pulse counts of the SET write current pulses applied to respective blocks  260   a,    260   b,    260   c,  and  260   d,  of the phase-change memory cell array  260 . As illustrated in  FIG. 19 , the pulse count of a SET current signal input into a far block ( 260   a ) is less than the pulse count of a SET current signal input into a near block ( 260   d ).  
         [0074]      FIG. 20  and  21  illustrate the pre-decoder  220  of  FIG. 8  in the case of the second embodiment of the present invention. In this specific example, the pre-decoder  220  includes NAND gates ND 1  . . . ND 14 ; NOR gates NOR 1  . . . ND 4 ; and inverters IN 1  . . . IN 9 . As shown, the pre-decoder  220  receives the buffered address signals A 0 P, A 0 PB, A 1 P and A 1 PB, and the buffered write enable signal WEb, and outputs decoded address signals A 00 _DEC, A 01 _DEC, A 10 _DEC, and A 11 _DEC, and decoded write control signals WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC. In this example, one or more of the decoded write control signals WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC is HIGH when the buffered write enable signal WEb is LOW.  
         [0075]      FIG. 22  illustrates a timing diagram for explaining the generation of the SET programming pulse SET_CON_PULSE according to the second embodiment of the present invention. As shown in this figure, the buffer write enable signal WEb is HIGH when the write enable signal XWE is HIGH. Further, responsive to the falling edge of the address transition detection (ATD) signal, the SET_CON_PULSE signal is generated.  
         [0076]     As shown in  FIG. 22 , the SET_CON_PULSE signal corresponds to SET_PULSE (A 00 ) when WEb is LOW and only WE_A 00 _DEC is HIGH; the SET_CON_PULSE signal corresponds to the combination of SET_PULSE (A 00 ) and SET_PULSE (A 01 ) when WEb is LOW and only WE_A 00 _DEC and WE_A 01 _DEC are HIGH; the SET_CON_PULSE signal corresponds to the combination of SET_PULSE (A 00 ), SET_PULSE (A 01 ) and SET_PULSE (A 10 ) when WEb is LOW and only WE_A 00 _DEC, WE_A 01 _DEC and WE A 10 _DEC are HIGH; the SET_CON_PULSE signal corresponds to combination of SET_PULSE (A 00 ), SET_PULSE (A 01 ), SET_PULSE (A 0 ) and SET_PULSE (A 11 ) when WEb is LOW and WE_A 00 _DEC, WE_A 01 _DEC, WE A 10 _DEC and WE_A 11 _DEC are all HIGH.  
         [0077]      FIG. 23  is a circuit diagram of the SET control pulse generator  270  of  FIG. 8  according to the second embodiment of the present invention. In this specific example, SET control pulse generator includes NOR gate NOR 1 ; NAND gate ND 1 ; and delay circuits D 1 , D 2 , D 3 , and D 4 . As should be apparent, the circuit of  FIG. 23  is configured to output SET_PULSE signals (A 01 ), (A 01 ), (A 10 ) and (A 11 ) as illustrated in  FIG. 22 .  
         [0078]     The above-described second embodiment is generally characterized by controlling a write driver of a phase-change memory device such that the pulse count of the SET pulse current is varied according to a load between the write driver and an addressed memory cell. In this manner, over-programming of memory cells can be avoided, thus reducing the power consumption needed to reliably write the cells into the SET and RESET states.  
         [0079]      FIG. 24  illustrates an alternative to the first and second embodiments. That is, according to the third embodiment of  FIG. 24 , the write driver of the phase-change memory device is controlled such that the pulse width of the RESET pulse currents is varied according to the load between the write driver and an addressed memory cell. As shown, different pulse widths of the RESET current control signals applied to respective blocks  260   a,    260   b,    260   c,  and  260   d  are defined by pulse widths of the RESET pulses A_RESET_PULSE, B_RESET_PULSE, C_RESET_PULSE, and D_RESET_PULSE. As illustrated in  FIG. 24 , the pulse width of a RESET current signal input into a far block Region (A 00 ) is greater than the pulse width of a RESET current signal input into a near block Region (A 11 ).  
         [0080]      FIG. 25  illustrates yet another alternative to the first through third embodiments. That is, according to the fourth embodiment of  FIG. 25 , the write driver of the phase-change memory device is controlled such that the pulse count of the RESET pulse currents is varied according to the load between the write driver and an addressed memory cell. As shown, different pulse counts of the RESET current control signals applied to respective blocks  260   a,    260   b,    260   c,  and  260   d  are defined by pulse counts of the RESET pulses A_RESET_PULSE, B_RESET_PULSE, C_RESET_PULSE, and D_RESET_PULSE. As illustrated in  FIG. 25 , the pulse count of a RESET current signal input into a far block Region (A 00 ) is greater than the pulse count of a RESET current signal input into a near block Region (A 11 ).  
         [0081]      FIG. 26  illustrates a timing diagram for explaining the generation of the RESET programming pulse RESET_CON_PULSE according to the third embodiment of the present invention. As shown in this figure, the buffer write enable signal WEb is HIGH when the write enable signal XWE is HIGH. Further, responsive to the falling edge of the address transition detection (ATD) signal, the RESET_CON_PULSE signal is generated.  
         [0082]     As shown in  FIG. 26 , the RESET_CON_PULSE signal corresponds to A_RESET_PULSE when WEb is LOW and WE_A 00 _DEC is HIGH; the RESET_CON_PULSE signal corresponds to B_RESET_PULSE when WEb is LOW and WE_A 01 _DEC is HIGH; the RESET_CON_PULSE signal corresponds to C_RESET_PULSE when WEb is LOW and WE_A 10 _DEC is HIGH; and the RESET_CON_PULSE signal corresponds to D_SET_PULSE when WEb is LOW and WE_A 11 _DEC is all HIGH. In this case, A_RESET_PULSE, B_RESET_PULSE, C_RESET_PULSE, and D_SET_PULSE are as shown in  FIG. 24 .  
         [0083]      FIG. 27  illustrates a timing diagram for explaining the generation of the RESET programming pulse RESET_CON_PULSE according to the fourth embodiment of the present invention. As shown in this figure, the buffer write enable signal WEb is HIGH when the write enable signal XWE is HIGH. Further, responsive to the falling edge of the address transition detection (ATD) signal, the RESET_CON_PULSE signal is generated.  
         [0084]     As shown in  FIG. 27 , the RESET_CON_PULSE signal corresponds to the combination of A_RESET_PULSE, B_RESET_PULSE, C_RESET_PULSE, and D_RESET_PULSE when WEb is LOW and WE_A 00 _DEC, WE_A 01 _DEC, WE_A 10 _DEC and WE_A 11 _DEC are all HIGH; the RESET_CON_PULSE signal corresponds to the combination of A_RESET_PULSE, B_RESET_PULSE, and C_RESET_PULSE when WEb is LOW and only WE_A 01 _DEC, WE_A 10 _DEC, and WE_A 11 _DEC are HIGH; the RESET_CON_PULSE signal corresponds to the combination of A_RESET_PULSE and B_RESET_PULSE when WEb is LOW and only WE_A 10 _DEC and WE_A 11 _DEC are HIGH; and the RESET_CON_PULSE signal corresponds to A_RESET_PULSE when WEb is LOW and only WE_A 11 _DEC is HIGH.  
         [0085]     The above-described third and fourth embodiments are generally characterized by controlling a write driver of a phase-change memory device such that the pulse width or pulse count of the RESET pulse current is varied according to a load between the write driver and an addressed memory cell. In this manner, over-programming of memory cells can be avoided, thus reducing the power consumption needed to reliably write the cells into the RESET state.  
         [0086]     It is noted that combinations of the above-described embodiments may also be implemented. For example, the pulse width and/or pulse count of both the RESET and SET write current pulses may be varied according to the load of the phase-change memory cell being written.  
         [0087]     In the drawings and specification there have been disclosed embodiments of the present invention, including specific examples. This discussion is used in a generic and descriptive sense only and not purpose of limitation. It should be therefore understood that this invention is to be construed by the appended claims and not by the exemplary embodiments. Further, one of ordinary skill in the art would deviate from this disclosure without departing from the spirit and scope of the embodiments of the present invention.