Abstract:
A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

Description:
RELATED APPLICATION 
     This application is a continuation-in-part of U.S. patent application Ser. No. 09/083,205 filed May 21, 1998, entitled Programmable Logic Device, of same assignee. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to integrated circuits, and in particular, to a programmable integrated circuit device with slew control and skew control. 
     BACKGROUND OF THE INVENTION 
     Many integrated circuit (IC) devices can be programmed. Examples of such programmable IC devices include some volatile and non-volatile memory devices, field programmable gate arrays (“FPGAs”), programmable logic devices (“PLDs”), and complex programmable logic devices (“CPLDs”). 
     A programmable IC device typically includes a plurality of input/output (I/O) cells which are coupled to respective I/O pins for the receipt of input signals and the transmission of output signals. In operation, various output signals may be provided at the same or different times to several respective I/O cells. Numerous problems, however, are associated with such provision of output signals at the I/O cells. 
     For example, under certain circumstances, when several output signals are simultaneously provided to several respective I/O cells, there can be a degradation in the quality of these signals. Specifically, output bus lines external to a programmable logic device may be connected to the I/O cells. These output bus lines may be powered by a single power supply with a limited peak current capacity. As such, the simultaneous fast switching of several output signals may exceed the peak current capacity of the power supply, thus resulting in slow switching on all bus lines. Furthermore, the simultaneous switching of several output signals may create noise and interference in the output signals due to ground bounce and other phenomena. 
     Under other circumstances, it is desirable to have several output signals appear simultaneously at respective I/O cells. For example, a plurality of output signals may each convey one bit of the same multi-bit address, and thus, ideally, should be presented at the same time on respective I/O pins. In actual operation, however, such output signals are provided at different times due to internal delays within the programmable IC device. 
     A complex programmable IC device can be connected together with other devices on a printed circuit board. An inherent characteristic of circuit connects on such a board is that the amount of noise introduced into a signal is directly proportional to the length of a connection. Thus, longer connections can produce a degradation of quality in the transmission of signal transitions when slew rates are too fast. Accordingly, a reduction in slew rate would improve transition over long distances. 
     Another inherent characteristic of printed circuit board interconnects is that transmission delay of a signal is directly proportional to the trace length of a connection over which the signal travels. The trace lengths of various connections within the same bus can be different. Thus, even though the transition of signals conveyed over the same bus ideally should be concurrent, this is often not the case in actual application. Accordingly, delaying the output sources of various signals on a bus could result in a lessskewed transition of the signals at the respective destinations. 
     SUMMARY OF THE INVENTION 
     Thus, a need has arisen for a programmable IC device that addresses the disadvantages and deficiencies of the prior art. In particular, the need has arisen for a programmable IC with the capability to control the timing of output signals at respective I/O cells. 
     In accordance with one embodiment of the present invention, a programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal transition on each output terminal and is further operable to control an output signal transition slew rate on each output terminal. The timing control circuitry may comprise one or more programmable delay elements and one or more programmable drivers. Each programmable delay element can delay an output signal transition on a respective output terminal. Each programmable driver can control the slew rate of an output signal transition on a respective output terminal. 
     In accordance with another embodiment of the present invention, a method for controlling the timing of output signals in a programmable integrated circuit device includes the following steps: generating a plurality of output signals for transmission at a plurality of respective output terminals; controlling the skew of at least a first portion of the output signals en route to the respective output terminals; and controlling the slew rate of at least a second portion of the output signals at the respective output terminals. 
     In accordance with yet another embodiment of the present invention, a programmable logic device includes a plurality of input/output (I/O) cells. A number of logic circuits are each operable to generate a separate output signal on a respective output line, each output line being coupled to at least one of the I/O cells. Timing control circuitry, coupled to the output line of at least one of the logic circuits, can programmably delay the output signal of such logic circuit. The timing control circuitry can also programmably control the slew rate of the same output signal. 
     A technical advantage of the present invention includes providing a separate programmable delay element for at least a portion of the output terminals of a programmable IC device. Each programmable delay element can delay an output signal on the respective output terminal, thereby providing skew control of the output signal. Another technical advantage includes providing a separate programmable driver for at least the same, or a separate, portion of the output terminals. Each programmable driver can be used to speed up or slow down the transition from HIGH to LOW (or vice versa) of an output signal on the respective output terminal, thereby providing slew control of that output signal. With the combined skew control and slew control, the timing of output signals at respective output terminals in the programmable logic device can be controlled as desired. For example, one or more output signals can be delayed, or their transition time increased or decreased, so that there is no simultaneous fast switching of a large number of output signals. Accordingly, noise and interference is reduced within the programmable IC device. 
     Furthermore, multiple output signals can be controlled to appear simultaneously at the output terminals, thereby providing synchronization of the signals when appropriate. In addition, for a printed circuit interconnect bus, it is possible to selectively skew signals at their respective output sources to reduce the skew between signals at their respective destinations. 
     Other aspects and advantages of the present invention will become apparent from the following descriptions and accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and for further features and advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a programmable logic device constructed in accordance with the present invention; 
     FIG. 2 is a schematic diagram in partial block form of an exemplary generic logic block in the programmable logic device; 
     FIG. 3 is a schematic diagram in partial block form of an exemplary macrocell in the programmable logic device; 
     FIG. 4 is a more detailed schematic diagram of a register for use in the exemplary macrocell; 
     FIG. 5A is a schematic diagram of one exemplary embodiment for a programmable delay element for use in the programmable logic device; 
     FIG. 5B is a schematic diagram of another exemplary embodiment for a programmable delay element for use in the programmable logic device; 
     FIG. 6 is a schematic diagram of the exemplary macrocell with signal paths highlighted; 
     FIG. 7A is a schematic diagram in partial block of one exemplary embodiment for a programmable driver for use in the programmable logic device; 
     FIG. 7B is a schematic diagram of another exemplary embodiment for a programmable driver for use in the programmable logic device; and 
     FIG. 8 is a schematic diagram of an exemplary embodiment for a programmable slew rate control block for use in the programmable driver. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The preferred embodiments of the present invention and their advantages are best understood by referring to FIGS. 1 through 8 of the drawings. Like numerals are used for like and corresponding parts of the various drawings. 
     Referring to FIG. 1, a programmable logic device  10  constructed in accordance with the present invention is shown. The present invention is described below primarily in the context of a programmable logic device, but it should be understood that the invention is not so limited. Rather the present invention is applicable for any programmable IC device, including, but not limited to, field programmable gate arrays and various forms of volatile and non-volatile memory. With reference to FIG. 1, programmable logic device  10  includes twelve generic logic blocks  12 . Each generic logic block  12  includes a set of logic gates which may be programmed to perform logic functions on input signals. Generic logic blocks  12  will be described more fully below. 
     Generic logic blocks  12  receive input signals and transmit output signals via I/O cells  14 . I/O cells  14  are coupled to I/O pins (not shown) on programmable logic device  10 . The type of I/O pins used for programmable logic device  10  depends on the type of packaging used for programmable logic device  10 . For example, in a surface mount package, the I/O pins may be leads extending from a lead frame, while in a ball grid array package, the pins would be solder connections on the bottom surface of the package. In this example, a ball grid array package is used to achieve the desired I/O pin density. Other standard packaging and pinout techniques may also be used. 
     A global routing pool  16  provides programmable communication lines for communication among generic logic blocks  12  and I/O cells  14 . Global routing pool  16  includes  576  bus lines  18 , each of which carries either a signal conducted from an I/O cell  14  by a line  22  or a signal conducted from a generic logic block  12  by a line  23 . Some bus lines  18  may be programmably connected to input lines  20  of generic logic blocks  12 . 
     An EEPROM cell array (not shown) is used to provide programmable interconnections and signal routing in global routing pool  16 . The EEPROM cell array also provides various other programmable interconnections throughout programmable logic device  10 , as will be described more fully below. 
     In this example, global routing pool  16  is not fully populated. Thus, not every bus line  18  has a programmable interconnection to every input line  20  of every generic logic block  12 . This reduces the number of EEPROM cells required for global routing pool  16 , and also increases the switching speed of bus lines  18  in global routing pool  16 . 
     Programmable logic device  10  may be used to perform logic operations on binary logic input signals to produce output signals. For example, programmable logic device  10  may be programmed to solve the following simple equation: 
     
       
         X=A{circle around (x)}B{circle around (x)}C⊕A{circle around (x)}B{circle around (x)}D⊕D{circle around (x)}E  (1) 
       
     
     In equation (1), A, B, C, D and E are input signals received by programmable logic device  10  and X is an output signal produced by programmable logic device  10 . The symbol ⊕ denotes an OR operation and {circle around (x)} denotes an AND operation. Thus, “A{circle around (x)}B{circle around (x)}C” is a combination of the A, B and C input signals in an AND operation. This type of AND grouping will be referred to herein as a product term. 
     Generic Logic Block Overview 
     Referring to FIG. 2, a block diagram of an exemplary generic logic block  12  is shown. Generic logic block  12  is, as the name implies, representative of all generic logic blocks  12  in programmable logic device  10 . 
     Generic logic block  12  has an AND array  24  with  165  AND gates  28 . AND array  24  receives inputs  26  from an AND array input fuse pattern. The input fuse pattern establishes programmable interconnections between AND array input lines  26  and bus lines  18  in global routing pool  16 . The bus lines  18  in global routing pool  16  may be output lines from I/O cells  14  or from other generic logic blocks  12 , as previously discussed. 
     Within AND array  24 , the signal on each input line  26  is provided in both inverted and noninverted forms on bus lines  27 . Each AND gate  28  has a set of input lines  30  providing input to the AND gate  28 . Each input line  30  has a programmable interconnection to each bus line  27  in AND array  24 . Thus, AND array  24  is said to be fully populated. 
     The programmable interconnections in AND array  24 , and throughout programmable logic device  10 , may be provided by any known programmable interconnect cell. For example, a “Non-Volatile Erasable and Programmable Interconnect Cell” is disclosed in U.S. Pat. No. 5,251,169, issued to Gregg Josephson on May 6, 1991, which is incorporated herein by reference. Such interconnect cells may be part of the previously discussed EEPROM cell array in programmable logic device  10 . Alternatively, the programmable interconnections in programmable logic device  10 , also known as “fuses,” may be SRAM cells, metal fuses, or other known types of programmable interconnections. 
     AND array  24  produces  165  AND gate outputs, also known as product term outputs  32 . AND gates  28  are generally grouped into sets of five AND gates each. Each set of AND gates  28  is assigned to a corresponding macrocell  34 . Generic logic block  12  includes  32  macrocells  34 . The product term outputs  32  may be shared by macrocells  34  by means of product term sharing array (PTSA)  36 , as will be described more fully below. AND array  24  also produces five shared product term outputs  38 , which will be described in more detail below. 
     Macrocell Overview 
     Referring to FIG. 3, an exemplary macrocell  34  from generic logic block  12  is shown in greater detail. Macrocell  34  receives product term outputs  32   a  through  32   e  from the five AND gates  28  assigned to macrocell  34 . Each product term output is routed by a demultiplexer  40   a  through  40   e  according to a select signal received from one or more EEPROM cells (not shown) . One of the outputs from each demultiplexer  40   a  through  40   e  is connected, via a multiplexer  42 , to the input of a first product term summing OR gate  44 . Similarly, a second output from each demultiplexer  40   a  through  40   e  is connected, via a multiplexer  46 , to the input of a second product term summing OR gate  48 . Other alternative outputs from demultiplexers  40   a  through  40   e  will be described below. 
     Thus, any one or more of the product term outputs  32   a  through  32   e  may be routed to product term summing OR gate  44  by demultiplexers  40   a  through  40   e . Likewise, any one or more of the product term outputs  32   a  through  32   e  may be routed to product term summing OR gate  48  by demultiplexers  40   a  through  40   e.    
     Demultiplexers  40   a  through  40   e  are non-exclusive demultiplexers, meaning that any product term output  32   a  through  32   e  may be routed to product term summing OR gate  44 , to product term summing OR gate  48 , to a multiplexer  41 , or to any combination of these destinations. This allows each product term output  32   a  through  32   e  to be used for two or more independent functions within macrocell  34 , as will be described more fully below. 
     This non-exclusive routing feature requires a number of EEPROM cells to provide the select signal for each demultiplexer  40   a  through  40   e . The number of EEPROM cells required for each demultiplexer  40   a  through  40   e  is equal to the number of outputs of the respective demultiplexer. This is a greater number of EEPROM cells than would be required for an exclusive demultiplexer (e.g. one EEPROM cell for two exclusive demultiplexer outputs). However, as will be described more fully below, the increased flexibility and functionality provided by macrocell  34  may reduce the number of macrocells required to perform a given function, thereby providing an overall reduction in cost to the user of programmable logic device  10 . 
     The product term outputs routed to product term summing OR gate  48  are summed and the output is routed to product term sharing array  36 , where adjacent macrocells may use the output signal, as will be described more fully below. The output of product term summing OR gate  44  is routed on a product term sharing array bypass line  50  to a register data multiplexer  52  and two macrocell output multiplexers  54  and  56 . 
     Macrocell Register 
     A register  58  receives a data input signal (D) from register data multiplexer  52 . Register  58  may be, for example, a rising-edge-triggered D flip-flop or a toggle flip-flop, as will be described more fully below. Register data multiplexer  52  selects the source of the data input signal (D) for register  58  according to a select signal received from one or more EEPROM cells (not shown). 
     The data input signal (D) may come from product term summing OR gate  44  via PTSA bypass line  50 , as previously discussed. Alternatively, the data input signal may come from an XOR gate  51 , the function of which will be described below, or from an I/O cell  14 . When an I/O cell  14  is selected as the data input signal source, register  58  may be used as an input register for the I/O cell  14 . In this mode, macrocell  34  can still produce a logic output signal in addition to the register output signal, as will be described more fully below. 
     Because any macrocell register  58  in programmable logic device  10  may be used as an input register, the need for additional, dedicated input registers in programmable logic device  10  is reduced or eliminated altogether, thereby reducing the cost of programmable logic device  10 . Moreover, the input signal is received at the data input of register  58  directly from I/O cell  14 , without using any of the product term inputs or outputs from AND array  24 . 
     Register  58  receives a clock enable signal (Clk En) from a clock enable multiplexer  60 . Clock enable multiplexer  60  selects the source of the clock enable signal according to a select signal received from one or more EEPROM cells (not shown). Clock enable multiplexer  60  may select one of two global clock signals (CLK0 and CLK1) as the clock enable signal for register  58 . Alternatively, clock enable multiplexer  60  may select a constant HIGH signal (V cc ) as the clock enable signal for register  58 . Other alternatives for the clock enable signal will be described more fully below. 
     Register  58  receives a clock signal (Clk) from a clock signal multiplexer  64 . Clock signal multiplexer  64  selects the source of the clock signal according to a select signal received from one or more EEPROM cells (not shown). Clock signal multiplexer  64  may select one of several global clock signals (CLK0, CLK1, CLK2, and CLK3) as the clock signal for register  58 . Alternatively, clock signal multiplexer  64  may select a constant HIGH signal (V cc ). Other alternatives for the clock signal will be described more fully below. 
     Register  58  receives a reset signal (R) and a preset signal (P) which may be used to clear the register. A global set/reset signal is selectively routed to either a reset multiplexer  66  or a preset multiplexer  67  by an exclusive demultiplexer  68 . Demultiplexer  68  selects the destination of the global set/reset signal according to a select signal received from a single EEPROM cell (not shown). Reset multiplexer  66  may select either the reset output of demultiplexer  68  or a LOW signal (ground) for routing to the reset input of register  58 , according to a select signal received from one or more EEPROM cells (not shown). Likewise, preset multiplexer  66  may select either the preset output of demultiplexer  68  or a LOW signal (ground) for routing to the preset input of register  58 , according to a select signal received from one or more EEPROM cells (not shown). 
     By routing the global set/reset signal to either the reset input or the preset input of register  58 , demultiplexer  68  and multiplexers  66  and  67  allow register  58  to “reset” to a programmable value when a global set/reset signal is received, such as when programmable logic device  10  is initially powered up. Thus, a user may program an initial state for all registers  58  in programmable logic device  10 , or for some subset of the registers, using three EEPROM cells per register. This is an advantage over previous programmable logic devices, in which a global reset signal would typically reset (zero) all registers in the device. 
     Referring to FIG. 4, a more detailed schematic diagram of one embodiment of register  58  is shown. Register  58  includes a D flip-flop  58   d , which receives a data input (D′) and a clock input (Clk) and generates an output (Q′). A data multiplexer  58   c  selects the source of the data input to flip-flop  58   d  according to a select signal (D/T). The select signal (D/T) determines whether register  58  will operate as a D flip-flop or a toggle flip-flop. 
     Thus, if the D/T signal is LOW, then the output of a multiplexer  58   a  is selected as the data input of flip-flop  58   d . Multiplexer  58   a  selects either the register data input (D) or the flip-flop output signal (Q′) as an output, according to the register clock enable signal from clock enable multiplexer  60 . Thus, if the clock enable signal is HIGH, the register data input (D) is selected as the data input (D′) for flip-flop  58   d , enabling flip-flop  58 d to act as a D flip-flop. If the clock enable signal is LOW, the flip-flop output signal (Q′) is selected as the data input (D′) for flip-flop  58   d , causing flip-flop  58   d  to hold its present output. 
     If the D/T signal is HIGH, then the output of a programmable inverter  58   b  is selected as the data input (D′) of flip-flop  58   d . Programmable inverter  58   b  selects either the uninverted flip-flop output signal (Q′) or the inverted flip-flop output signal (Q′-bar) as an output, according to the register clock enable signal from clock enable multiplexer  60 . Thus, if the clock enable signal is LOW, the uninverted flip-flop output signal (Q′) is selected as the data input (D′) for flip-flop  58   d , while if the clock enable signal is HIGH, the inverted flip-flop output signal (Q′-bar) is selected. As a result, register  58  acts as a toggle flip-flop, with output (Q) changing state every time the clock enable signal from clock enable multiplexer  60  changes state. The register data input signal (D) has no effect on the operation of register  58  in this mode. 
     Either one of the foregoing modes may be selected according to the particular functions to be performed by macrocell  34 . Alternatively, other configurations of register  58  may be selected for particular applications, and will be understood to be within the scope of the present invention. 
     Macrocell Input and Register Control 
     Referring again to FIG. 3, demultiplexers  40   a  through  40   e , together with multiplexers  42  and  46 , allow each product term output  32   a  through  32   d  from AND array  24  to be used within macrocell  34  as a product term input to product term summing OR gate  44 , as a product term input to product term summing OR gate  48 , or as a control signal for macrocell  34 , or any combination of the above. 
     Thus, for example, product term outputs  32   d  and  32   e  may be used as reset and preset inputs, respectively, for register  58 . If demultiplexer  40   d  and multiplexer  41   d  are programmed to use product term output  32   d  as a reset signal, then product term output  32   d  is routed to a reset multiplexer  70 . Reset multiplexer  70  selects either the output from multiplexer  41   d  or one of two shared product term outputs as a reset input for register  58 , according to a select signal received from one or more EEPROM cells (not shown). The output of reset multiplexer  70  is selectively inverted by programmable inverter  72  according to a signal received from one or more EEPROM cells (not shown). 
     The output of programmable inverter  72  is received at an input of a reset OR gate  74 . Reset OR gate  74  ORs the selected reset signal with the reset output from global set/reset demultiplexer  68 . The output from reset OR gate  74  is provided to the reset input (R) of register  58 . Thus, either product term output  32   d  or the global set/reset signal will be used to reset register  58 . 
     Likewise, if demultiplexer  40   e  is programmed to use product term output  32   e  as a preset signal, then product term output  32   e  is routed to a preset multiplexer  76 . Preset multiplexer  76  selects either the output from multiplexer  41   e  or one of two shared product term outputs as a preset input for register  58 , according to a select signal received from one or more EEPROM cells (not shown). The output of preset multiplexer  37  is selectively inverted by programmable inverter  78  according to a signal received from one or more EEPROM cells (not shown). 
     The output of programmable inverter  78  is received at an input of a preset OR gate  80 . Preset OR gate  80  ORs the selected preset signal with the preset output from global set/reset demultiplexer  68 . The output from preset OR gate  80  is provided to the preset input (P) of register  58 . Thus, either product term output  32   e  or the global set/reset signal may be used to reset register  58 . 
     Demultiplexer  40   c  may be programmed to use product term output  32   c  from AND array  24  as a clock signal or clock enable signal for register  58 . This is useful when a clock signal or clock enable signal resulting from a logic operation, rather than a standard clock signal or clock enable signal, is required. Thus, demultiplexer  40   c  and multiplexer  41   c  may be programmed to route product term output  32   c  to a multiplexer  82 . Multiplexer  82  selects the output of multiplexer  41   c  or one of two shared product term outputs as an output signal according to a select signal received from one or more EEPROM cells (not shown). The output of multiplexer  82  is selectively inverted by a programmable inverter  84  according to a select signal received from one or more EEPROM cells (not shown). The output of programmable inverter  84  is provided to clock enable multiplexer  60  and clock signal multiplexer  64 . Thus, using multiplexers  60  and  64 , product term output  32   c  can be programmed to be either the clock enable signal or the clock signal for register  58 . 
     Demultiplexer  40   a  may be programmed to use product term output  32   a  from AND array  24  as an output enable signal for macrocell  34 . Thus, demultiplexer  40   a  and multiplexer  41   a  may be programmed to route product term output  32   a  to an output enable multiplexer  86 . Output enable multiplexer  86  selects the output of multiplexer  41   a  or one of six global output enable signals as an output signal according to a select signal received from one or more EEPROM cells (not shown). The output of multiplexer  88  is selectively inverted by a programmable inverter  88  according to a select signal received from one or more EEPROM cells (not shown). The output of programmable inverter  88  is provided to an input of an AND gate  90 . AND gate  90  also receives a global test output enable (TOE) signal as an input. During normal operation, the TOE signal is always HIGH, allowing the output enable signal selected by multiplexer  86  to act as an output enable signal. However, programmable logic device  10  may be tested by making the TOE signal LOW, thereby “tristating” (floating) all output signals from macrocells  34 . 
     Product term output  32   b , unlike the other product term outputs, may not be used as a control signal for register  58 . Thus, product term output  32   b  may only be routed to product term summing OR gates  44  and  48 . 
     Macrocell Output and Timing Control The output (Q) of register  58  is routed to macrocell output multiplexers  54  and  56 . Macrocell output multiplexer  56  provides an output signal to global routing pool  16 , where the signal may be programmably routed to another generic logic block  12  in programmable logic device  10 . The output signal from macrocell output multiplexer  56  may be selected from the register output (Q), PTSA bypass line  50 , XOR gate  51  or ground. Macrocell output multiplexer  56  selects the output signal according to a select signal received from one or more EEPROM cells (not shown). 
     Likewise, the output signal from macrocell output multiplexer  54  may be selected from the register output (Q), PTSA bypass line  50 , XOR gate  51  or ground. Macrocell output multiplexer  54  selects the output signal according to a select signal received from one or more EEPROM cells (not shown). Macrocell output multiplexer  54  provides an output signal to a programmable inverter  92 , which selectively inverts the signal according to a select signal received from one or more EEPROM cells (not shown). The output of programmable inverter  92  is provided to a programmable delay element  94 , which selectively delays the signal according to a signal received from one or more EEPROM cells (not shown). 
     Programmable delay element  94  provides a programmable delay for output signals en route to I/O cells  14 . As such, programmable delay element  94  essentially functions to provide skew control for the output signals. In one embodiment, programmable delay element  94  preferably delays the output signal of programmable inverter  92  by approximately 0.5 nanoseconds when programmed to do so. 
     Referring to FIG. 5A, a schematic diagram of one exemplary embodiment for a programmable delay element  94  is shown. A delay control signal is received at the gate of an n-channel field effect transistor (FET)  94   a , which is connected at its source to a capacitor  94   b . The delay control signal may come from, for example, an EEPROM cell (not shown). 
     If the delay control signal is LOW, FET  94   a  will not conduct from drain to source, leaving the conduction line from programmable inverter  92  to programmable driver  96  essentially unaffected by programmable delay element  94 . If the delay control signal is HIGH, FET  94   a  will conduct from drain to source, allowing the output signal to pass through FET  94   a  to capacitor  94   b . FET  94   a  has a gate-channel capacitance that introduces a delay in the output signal from programmable inverter  92  as it passes through programmable delay element  94 . Capacitor  94   b  also introduces delay in the output signal as it charges. Thus, the capacitances of FET  94   a  and capacitor  94   b  causes a delay in the transition of the output signal from LOW to HIGH or vice versa. 
     Because the gate-channel capacitance varies with gate-source voltage, particularly near the threshold voltage of FET  94   a , the delay introduced by FET  94   a  into the output signal transition will be different for HIGH-to-LOW transitions than for LOW-to-HIGH transitions. To compensate for this asymmetry, capacitor  94   b  is connected to the source of FET  94   a . Thus, when the delay control signal is HIGH, both FET  94   a  and capacitor  94   b  add a capacitive load to the signal conduction path. Programmable delay element  94  therefore introduces a symmetrical delay of approximately 0.5 nanoseconds into the output signal from programmable inverter  92 . 
     Referring to FIG. 5B, a schematic diagram of another exemplary embodiment for a programmable delay element  94  is shown. A delay block  104  receives the output signal from programmable inverter  92 . Delay block  104  generally functions to introduce delay in the output signal. This delay can be in the transition of the output signal from LOW to HIGH, or vice versa. Various implementations for delay block  104  are wellknown and understood by those in the art. For example, as shown, delay block  104  can be implemented using an even number of series-connected inverters. 
     An n-channel FET  106  is coupled between the output node of delay block  104  and the input node of programmable driver  96 . FET  106  receives a control (CONTROL) signal at its gate. Another n-channel FET  108  is coupled between the output node of programmable inverter  92  and the input node of programmable driver  96 . FET  108  receives the complementary signal ({overscore (CONTROL)}) to the control signal at its gate. Each of FETs  106  and  108  functions as a passgate. In particular, if the control signal is HIGH, FET  106  will conduct from drain to source, thus allowing the output signal, delayed by delay block  104 , to pass. If the complementary control signal is HIGH, FET  108  will conduct from drain to source. This allows the output signal to pass from programmable inverter  92  to programmable driver  96 , and avoids any delay which would otherwise be introduced by delay block  104 . 
     Besides the implementations shown in FIGS. 5A and 5B, other configurations for programmable delay element  94  may be implemented which produce similar delay characteristics without departing from the spirit and scope of the invention. 
     Returning to FIG. 3, the output of programmable delay element  94  is provided to a programmable driver  96 . Programmable driver  96  receives the output enable signal from AND gate  90 . If the output of AND gate  90  is HIGH, programmable driver  96  drives the output signal from programmable delay element  94  to an I/O cell  14 . If the output of AND gate  90  is LOW, programmable driver  96  leaves I/O cell  14  tristated, or floating. This latter state is useful when an input signal is to be received from I/O cell  14 . The input signal is unaffected by programmable driver  96 , and is received by an input multiplexer  98  for routing to global routing pool  16 . Programmable driver  96  may also include a slew rate control and a passive pull-up option to increase the suitability of programmable logic device  10  to a variety of output needs. 
     Referring to FIG. 7A, a schematic diagram in partial block of one exemplary embodiment for programmable driver  96  is shown. With this depicted implementation, programmable driver  96  provides slew control for the output signal appearing at a respective I/O pad. In particular, programmable driver  96  controls the rate at which the output signal transitions from LOW to HIGH, and vice versa. 
     Programmable driver  96  includes a rising edge slew control circuit  110  and a falling edge slew control circuit  112 . Rising edge slew control circuit  110  controls the rate of transition from LOW to HIGH for an output signal. Falling edge slew control circuit  112  controls the rate of transition from HIGH to LOW for an output signal. Rising edge slew control circuit  110  is coupled to the gate of an n-channel FET  132 , and falling edge slew control circuit  112  is coupled to the gate of an n-channel FET  134 . 
     Rising edge slew control circuit  110  includes an inverter  120  which inverts the output signal from programmable delay element  94 . A programmable slew rate control block  114  receives the output signal from inverter  120  and also a slew rate signal. Programmable slew rate control block  114  generates two output signals: a fast slew output signal and a slow slew output signal. A first p-channel FET  116  and a second p-channel FET  118  are coupled in parallel between a voltage supply (which can be an alternate supply voltage to V cc ) and an output node A for rising edge slew control circuit  110 . FET  116  receives the slow slew output signal at its gate, and FET  118  receives the fast slew output signal at its gate. FET  118  is preferably a stronger (e.g., larger width and/or shorter length) device than FET  116 , and hence, has a greater drive value than FET  116 . An n-channel FET  122  is connected at its gate to the output node of inverter  120 . The drain of FET  122  is coupled to output node A and its source is coupled to ground. In general, the fast and slow slew output signals (output by programmable slew rate control block  114 ) dictate the rate at which the output signal rises from LOW to HIGH. Specifically, one predetermined set of values for the fast slew output signal and the slow slew output signal causes the output to rise at a slower rate, whereas another predetermined set of values for the fast and the slow slew output signals causes the output to rise at a faster rate. 
     Falling edge slew control circuit  112  includes a programmable slew rate control block  124  which receives the output signal from programmable delay element  94  and also the slew rate signal. Programmable slew rate control block  124  generates a fast slew output signal and a slow slew output signal. A first p-channel FET  126  and a second p-channel FET  128  are coupled in parallel between the alternate supply voltage and an output node B for falling edge slew control circuit  112 . FET  128  is preferably a stronger (e.g., larger width and/or shorter length) device than FET  126 , and hence, has a greater drive value than FET  126 . FETs  126  and  128  receive the slow slew output signal and the fast slew output signal, respectively, at their gates. An n-channel FET  130  receives the output signal from programmable delay element  94  at its gate. The drain of FET  130  is coupled to output node B and its source is coupled to ground. In general, the fast and slow slew output signals (output by programmable slew rate control block  124 ) dictate the rate at which the output signal falls from HIGH to LOW. Specifically, one predetermined set of values for the fast slew output signal and the slow slew output signal causes the output to fall at a slower rate, whereas another predetermined set of values for the fast and the slow slew output signals causes the output to fall at a faster rate. 
     FET  132  is connected to the alternate voltage supply at its drain and the output node A of rising edge slew control circuit  110  at its the gate. The source of FET  132  is connected to the drain of FET  134 . The gate of FET  134  is connected to the output node B of falling edge slew control circuit  112  and the source of FET  134  is connected to ground. FETs  132  and  134  drive the output node. These FETs operate in different modes. Specifically, FET  132  operates as a source follower while FET  134  operates as an inverting amplifier in the saturation mode. Thus, slew control circuits  110  and  112  may be formed with different characteristics (e.g., edge rates) in order to produce similar slew rate characteristics on the output node. Therefore, although slew control circuits  110  and  112  can be similar, they may be optimized and sized differently. 
     FIG. 8 is a schematic diagram of an exemplary embodiment for a programmable slew rate control block  114  (or  124 ) for use in programmable driver  96 . As depicted, programmable slew rate control block  114  (or  124 ) includes an inverter  136  which receives an input signal. For programmable slew rate control block  124 , this input signal is the output signal from delay element  94 . For programmable slew rate control block  114 , this input signal is the inverted output signal from delay element  94 . The output signal of inverter  136  constitutes the slow slew output signal for programmable slew rate control block  114  (or  124 ). A NAND gate  138  receives the input signal at one input and the slew rate signal at another input. The output signal NAND gate  138  constitutes the fast slew output signal for programmable slew rate control block  114  (or  124 ). 
     Referring again to FIG. 7A, in operation for this exemplary embodiment for programmable driver  96 , if the output signal of programmable delay element  94  is low, falling edge slew control circuit  112  turns on FET  134 , thus pulling the voltage at the output node of programmable driver  96  to ground. Accordingly, the output signal falls. The slew rate signal input into programmable slew rate control block  124  of falling edge slew control circuit  112  causes control block  124  to output one of two predetermined sets of values for the fast slew output signal and the slow slew output signal. One predetermined set of values causes the output signal of programmable driver  96  to fall at a slower rate; the other predetermined set of values causes the output signal to fall at a faster rate. 
     On the other hand, if the output signal of programmable delay element  94  is high, rising edge slew control circuit  110  turns on FET  132 , thus pulling the voltage at the output node of programmable driver  96  to the voltage level of the alternate voltage supply. Accordingly, the output signal rises. The slew rate signal input into programmable slew rate control block  114  of rising edge slew control circuit  110  causes control block  114  to output one of two predetermined sets of values for the fast slew output signal and the slow slew output signal. One predetermined set of values causes the output signal of programmable driver  96  to rise at a slower rate; the other predetermined set of values causes the output signal to rise at a faster rate. 
     FIG. 7B is a schematic diagram of another exemplary embodiment for a programmable driver  96 . As with the embodiment shown and described with reference to FIG. 7A, the embodiment depicted in FIG. 7B provides slew control for the output signal appearing at a respective I/O pad. That is, programmable driver  96  controls the rate at which the output signal transitions from LOW to HIGH, and vice versa. 
     A separate programmable delay element  94  and programmable driver  96  are provided for various I/O pads of programmable logic device  10 . Each programmable delay element  94  can delay the time at which an output signal appearing at the respective I/O pad transitions from HIGH to LOW or vice versa. Each programmable driver  96  controls the rate at which such transitions occur for the respective output signal. As such, the skew control provided by programmable delay elements  94  and the slew control provided by programmable drivers  96  can be used to control the timing of output signals appearing at the I/O pins of programmable logic device  10 . Thus, programmable delay elements  94  and programmable drivers  96  constitute timing control circuitry. 
     This timing control circuitry can be useful when several output signals are being provided simultaneously to several respective I/O cells  14 . Output bus lines external to programmable logic device  10  may be connected to the respective I/O cells. These output bus lines may be powered by a single power supply with a limited peak current capacity. Thus, the simultaneous fast switching of several output signals may exceed the peak current capacity of the power supply, resulting in slow switching on all bus lines. In addition, simultaneous switching of several output signals may create noise in the output signals due to ground bounce and other phenomena in the power supply. 
     Some of the output signals may be more time-critical than other output signals. In other words, fast and timely signal transitions are more important for some output signals than for others. Thus, some or all macrocells  34  are provided with a programmable delay element  94 . The programmable delay elements  94  selectively delay those macrocell output signals which are not time-critical, allowing fast switching of the limited number of time-critical macrocell output signals. 
     In addition, when desirable, programmable delay elements  94  can be used to selectively delay one or more output signals en route to respective I/O cells  14  so that a group of related output signals appear simultaneously at the respective I/O cells. This may be the case, for example, when a group of output signals conveys a multi-bit address, each output signal associated with one bit of the address. 
     Referring again to FIG. 3, macrocell output multiplexers  54  and  56  receive select signals from two separate sets of EEPROM cells. Thus, macrocell output multiplexers  54  and  56  may independently select the sources of their respective output signals. This is an improvement over previous programmable logic devices, in which only a single macrocell output signal was typically available. 
     It should be noted that the number of macrocells  34  may exceed the number of I/O cells  14 , in which case not every macrocell  34  will provide an output signal to an I/O cell. Thus, with reference to FIG. 3, the output of programmable driver  96  may not be connected to an I/O cell  14 . Indeed, output multiplexer  54 , programmable inverter  92 , programmable delay element  94  and programmable driver  96  are superfluous components that need not be included in any macrocell  34  that will not provide an output signal to an I/O cell  14 . 
     Product Term Sharing Array 
     As previously described, each macrocell  34  has five dedicated product term outputs  32   a  through  32   e  from AND array  24 . These dedicated product term outputs are available to the macrocell  34  by means of product term sharing array bypass line  50  regardless of the state of product term sharing array  36 . However, to enhance the capability and flexibility of programmable logic device  10 , product terms may be shared among macrocells by means of product term sharing array  36 . 
     Referring to FIG. 2, product term sharing array  36  includes a set of bus lines  37 . The number of bus lines  37  is equal to the number of macrocells  34 , for reasons which will become apparent. Thus, in this example, product term sharing array  36  includes  32  bus lines. 
     In each macrocell  34 , a set of five product term outputs  32   a  through  32   e  is coupled to a product term summing OR gate  48  as previously described. Each product term summing OR gate  48  has an output connected to a respective one of the bus lines  37 . Thus, each bus line  37  in product term sharing array  36  carries an output signal from a respective one of the product term summing OR gates  48 . 
     Product term sharing array  36  also includes  32  output OR gates  35 . Each output OR gate  35  produces an output signal on an output line  35   a , which is connected to an input of XOR gate  51 , as shown in FIG.  3 . 
     Each output OR gate  35  receives input signals from selected bus lines  37 . A set of programmable interconnections  37   a  determines which bus lines  37  provide input to each output OR gate  35 . Programmable interconnections  37   a  may be any known type of programmable interconnect cell. Programmable interconnections  37   a  are available to connect each output OR gate  35  to the product term summing OR gate  48  dedicated to that macrocell  34 , as well as product term summing OR gates from adjacent macrocells. 
     In this example, each output OR gate  35  may be connected to as many as six product term summing OR gates  48  in addition to its own dedicated product term summing OR gate  48 . The available product term summing OR gates  48  include the three product term summing OR gates  48  immediately “above” the macrocell and the three product term summing OR gates  48  immediately “below” the macrocell. Thus, each output OR gate  35  may be connected to its own dedicated product term summing OR gate  48  and six adjacent product term summing OR gates. 
     For the output OR gate  35  located at the top of product term sharing array  36 , it will be apparent that there are no product term summing OR gates  48  located “above” the output OR gate  35 . Thus, in an asymmetrical product term sharing arrangement, the output OR gate  35  located at the top of product term sharing array  36  would have only four product term summing OR gate  48  outputs available to it: the product term summing OR gate  48  dedicated to that macrocell and the three product term summing OR gates  48  immediately “below” the macrocell. This is in contrast to the output OR gates  35  located near the center of product term sharing array  36 , which would each have seven product term summing OR gate  48  outputs available to it. 
     Likewise, the output OR gate  35  located at the bottom of product term sharing array  36  would have only four product term summing OR gate  48  outputs available to it in an asymmetrical arrangement. This difference in the number of available paths to each output OR gate  35  would create restrictions in the routing of product terms through product term sharing array  36 , making programmable logic device  10  less flexible and more cumbersome to program. 
     However, as illustrated by programmable interconnections  37   a  in FIG. 2, the output OR gate  35  located at the top of product term sharing array  36  may be connected to the three bottom-most product term summing OR gates  48  as well as the three product term summing OR gates  48  immediately “below” the output OR gate  35 . Likewise, the bottom-most output OR gate  35  in product term sharing array  36  may be connected to the three top-most product term summing OR gates  48  as well as the three product term summing OR gates  48  located immediately “above” the output OR gate  35 . As is shown in FIG. 2, similar arrangements are made for the other output OR gates  35  near the top and bottom of product term sharing array  36 . 
     Thus, product term sharing array  36  is said to have “wraparound” or circular symmetry. Each output OR gate  35  has programmable interconnections to seven bus lines  37 , and each product term summing OR gate  48  output is made available to seven output OR gates  35 , regardless of location within product term sharing array  36 . 
     This is an improvement over previous programmable logic devices, in which product term sharing became asymmetric near the ends of the product term sharing array, thereby placing limitations on routing within the programmable logic device and creating an uneven distribution of product term sharing. Moreover, the symmetrical product term sharing of the present invention is accomplished with only one additional OR gate (output OR gate  35 ) per output line from product term sharing array  36 . Thus, product term sharing array  36  may be expanded in size without significantly increasing the signal delays created by product term sharing array  36 . 
     It should be noted that the number of available connections for each output OR gate  35  could be any number from two to the total number of product term summing OR gates  48 , which in this example is  32 . In the case of  32  available connections for each output OR gate  35 , the output of every product term summing OR gate  48  is made available to each output OR gate  35 . This arrangement, referred to as “fully populated,” may be feasible for smaller generic logic blocks with fewer product term inputs and fewer product term sharing array outputs. However, with  32  product term sharing array outputs, such an arrangement would be prohibitively large and slow. Thus, a more limited, but still symmetrical, arrangement is preferred in this example. 
     In accordance with the foregoing, each output OR gate  35  receives output signals from up to seven product term summing OR gates  48 . These signals are ORed together at output OR gate  35 . Referring to FIG. 3, the output of output OR gate  35  is received by XOR gate  51 . If XOR multiplexer  53  is programmed to select ground as its output, then the output from output OR gate  35  is passed through XOR gate  51  to register data multiplexer  52 , where the signal may be selected as the data input signal (D) for register  58 . Alternatively, if XOR multiplexer  53  is programmed to select a HIGH signal as its output, then the output from output OR gate  35  is inverted by XOR gate  51  and passed to register data multiplexer  52 . If XOR multiplexer  53  is programmed to select PTSA bypass line  50  as its output, then the signal on PTSA bypass line  50  is combined in an exclusive OR operation with the output signal from output OR gate  35  in product term sharing array  36 . The resulting output signal is provided to register data multiplexer  52 , where the signal may be selected as the data input signal (D) for register  58 , and is also provided to macrocell output multiplexers  54  and  56  as previously described. The output signal from XOR gate  51  is also provided to clock enable multiplexer  60 , where the signal may be selected as the clock enable signal for register  58 . 
     While product term sharing array  36  has been described herein as receiving product term outputs from AND array  24 , product term sharing array  36  may be used to share output values derived from any kind of logic array. Thus, the phrase “product term,” as used herein, may be any type of logic output signal. 
     Furthermore, while product term sharing array  36  is described as allowing product term sharing primarily among adjacent macrocells, product term sharing array  36  may be configured to allow product term sharing according to any desired pattern. For example, product term sharing array  36  could be configured to allow each output OR gate  35  to receive signals from every third or fourth product term summing OR gate  48 . The selected product term sharing pattern may or may not involve an even distribution of shared product terms throughout product term sharing array  36 , as described above. 
     Shared Product Terms 
     In a generic logic block  12  of programmable logic device  10 , it may be desirable for some or all of the macrocells  34  within the generic logic block to use clock, clock enable, set/reset or output enable signals that result from a logic operation. Furthermore, it may be desirable for some or all of the macrocells  34  to use common or shared signals that result from a logic operation. This could be accomplished by means of the previously described control methods using the product term outputs dedicated to each macrocell, and by duplicating within AND array  24  the logic operation that produces the desired control signal. However, this method would result in unnecessary waste of product terms and other resources in the respective macrocells. This method may also result in significant signal skew between the control signals for the respective macrocells, which would be unacceptable, for example, for a common clock signal. 
     To solve this problem, shared product term outputs  38  from AND array  24  are provided to each macrocell  34 , as shown in FIG.  2 . Shared product term outputs  38  are independent of the other product term outputs provided to macrocells  34 . In this example, shared product terms outputs  38  include two shared product term clock lines  38   a  and  38   b , two shared product term set/reset lines  38   c  and  38   d , and one shared product term output enable line  38   e.    
     Referring to FIG. 3, shared product term clock lines  38   a  and  38   b  are provided to multiplexer  82  of each macrocell  34 , where they may be routed to clock enable multiplexer  60  and clock signal multiplexer  64 . If one of these multiplexers is programmed to select shared product term output  38   a  or  38   b , then shared product term output  38   a  or  38   b  may be used as either the clock enable signal or the clock signal for register  58  in the macrocell  34 . 
     Alternatively, clock enable multiplexer  60  or clock signal multiplexer  64  for any given macrocell  34  may be programmed to utilize product term output  32   c  as a product term clock signal or clock enable signal for that macrocell. Thus, each macrocell  34  may utilize either an individualized product term clock signal (product term output  32   c ) or a shared product term clock signal (shared product term output  38   a  or  38   b ). This is an improvement over previous programmable logic devices, in which the choice between a shared product term clock signal and an individualized product term clock signal was not available. 
     Similarly, shared product term set/reset lines  38   c  and  38   d  are provided to reset multiplexer  70  and preset multiplexer  76  of each macrocell  34 , where they may be routed to the reset and preset inputs, respectively, of register  58 . Shared product term output enable line  38   e  is provided (with some redundancy) to output enable multiplexer  86 , where it may be routed as an output enable signal to programmable driver  96 . 
     Macrocell Flexibility 
     As described above, each macrocell  34  has two independent product term summing OR gates  44  and  48 , as well as two independent output multiplexers  54  and  56 . Each product term summing OR gate  44  or  48  may use any one or more of the five product term outputs  32   a  through  32   e  dedicated to that macrocell. Furthermore, each product term summing OR gate  44  or  48  may have its signal routed to either output multiplexer  54  or  56 . Thus, each macrocell  34  is capable of simultaneous performing two discrete functions. 
     This property is illustrated in FIG. 6, in which a macrocell  34  is shown with two independent signal paths  101  and  102  highlighted. On path  101 , product term outputs  32   a  and  32   b  are routed to product term summing OR gate  44 . The output of product term summing OR gate  44  is routed on product term sharing array bypass line  50 , through output multiplexer  54 , through programmable inverter  92 , and through programmable driver  96  to I/O cell  14 . 
     On path  102 , product term outputs  32   b ,  32   c ,  32   d  and  32   e  are routed to product term summing OR gate  48 . The output of product term summing OR gate  48  passes through product term sharing array  36 , where it may be summed with product terms from other macrocells as previously described. The output of product term sharing array  36  is routed through XOR gate  51  and register data multiplexer  52  to be stored by register  58 . The output (Q) of register  58  is routed through output multiplexer  56  to global routing pool  16 . 
     Thus, macrocell  34  simultaneously performs the following operations: 
     
       
         Output 1=PT(A)⊕PT(B)  (2) 
       
     
     
       
         Output 2=PT(B)⊕PT(C)⊕PT(D)⊕PT(E)  (3) 
       
     
     This increased macrocell functionality requires additional EEPROM cells to control demultiplexers  40   a  through  40   e  as previously described, as well as an additional product term summing OR gate for each macrocell, than would be required for a single-function macrocell. However, this increased component cost of each macrocell may be justified by doubling the functionality of even a few macrocells  34 . 
     The increased functionality of macrocells  34  also makes the programming of programmable logic device  10  easier. In assigning functions to various macrocells  34  in programmable logic device  10 , one consideration is the limited number of communication paths provided among macrocells  34  by global routing pool  16 . As previously discussed, creating a fully populated global routing pool would make global routing pool  16  prohibitively expensive and slow. Thus, not all macrocell outputs have available routing to all macrocell inputs. Likewise, communication paths do not exist between all I/O cells  14  and all macrocells  12 . 
     Accordingly, in programmable logic device  10  and other programmable logic devices, some macrocell function assignment plans which would otherwise be feasible for the programmable logic device are infeasible due to the lack of available routing among macrocells and I/O cells to accomplish the desired functions. This situation can resolved by “swapping,” in which function assignments for two selected macrocells are exchanged in an attempt to find a feasible function assignment plan that has the necessary routing available. 
     In a programmable logic device with single-function macrocells, if all or nearly all macrocells are assigned a function, swapping is an inefficient way to locate a feasible function assignment plan, since each swap may create a new routing problem. Indeed, if the programmable logic device is at or near capacity, there may be no feasible function assignment plan. Thus, a macrocell “vacancy” rate of up to 20% or more may be preferred in order to generate a feasible function assignment plan for programming the device. 
     In programmable logic device  10 , if each macrocell  34  is assigned a single function, macrocell “vacancies” may still exist, since each macrocell  34  may perform two discrete functions. In particular, a function may be swapped into a macrocell without swapping out the existing macrocell function if (a) the two functions together use a total of five or fewer product terms, or (b) the two functions have one or more product terms in common, so that the number of unique product terms required to perform the two functions is less than or equal to five. 
     Of course, there are some limitations on the combining of functions within a macrocell  34 . For example, if two functions each require the use of a register  58  to store the output signal, then the two functions may not be performed in a single macrocell  34 . Likewise, if two functions each require the introduction of product terms from adjacent macrocells via product term sharing array  36 , the two functions may not be performed in a single macrocell  34 . 
     However, many times it is possible to combine two functions in a single macrocell  34 . This is particularly true when the mean number of product terms required for each function in programmable logic device  10  is LOW. For example, if a set of functions is to be performed by programmable logic device  10  in which the average number of product terms required per function is 2.5 or less, then the number of functions which may be performed by programmable logic device  10  may be close to two times the number of macrocells  34  in programmable logic device  10 . 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.