Abstract:
Methods and apparatuses are disclosed for retrieving data stored in a magnetic integrated memory. In one embodiment, the method comprises: a) applying a perturbing hard-axis magnetic field to a magnetic element in a magnetic integrated memory; and b) detecting a change in an electrical parameter caused by said perturbing hard-axis magnetic field.

Description:
BACKGROUND  
         [0001]    Information is extremely valuable for modern development and progress, especially in the development of new technology. However, many ways of storing and preserving information do not allow easy access to it. For example, information may be stored in library books, but identifying and obtaining the correct book often requires significant effort. Costs associated with accessing stored information may reduce the effective value of the information.  
           [0002]    Many developing technologies have been embraced because they increase accessibility to information. Microfilm, magnetic tapes, magnetic disk media, optical disk media, and non-volatile integrated memories are examples of technologies that have increased accessibility to information stored on them. Non-volatile integrated memories are of particular interest here.  
           [0003]    Integrated memories are electrical circuits that are configured to store information in digital form. This digital information, or “data,” is readily accessible to a digital device appropriately coupled to the integrated memory. Depending on the particular technology employed, data can be accessed at truly astonishing rates.  
           [0004]    Not all integrated memories are non-volatile. Volatile integrated memories suffer loss of stored data in the absence of electrical power. In the past, this shortcoming has been offset by the high rate of access to the data.  
           [0005]    Magnetic integrated memories, as that term is used herein, are integrated memories that use magnetization states to store data. Magnetic materials can be given magnetization states (e.g., magnetic orientations) that do not rely on the continued presence of electrical power to preserve the magnetization state. A variety of sensing techniques may be employed to detect magnetization states in these memories and to determine the data these states represent.  
           [0006]    One issue with the current technology for these memories is non-uniformity. A given portion of a magnetic integrated memory may have characteristics that vary from another portion of the memory. These characteristics may relate to the strength of the stored magnetization and to the sensitivity of sensing configurations. Accordingly, a sense signal that indicates stored magnetization characteristics is expected to exhibit position-dependent variation.  
           [0007]    One proposed method for dealing with the position-dependent variation makes use of the reproducibility of the variation. The proposed method involves multiple measurements: a measurement of the original sense signal associated with a storage location; and a measurement of the original sense signal after known data value is placed in the storage location. This second measurement is repeated for each possible data value. The known data value having a sense signal “closest” to the original sense signal is identified as the stored data value.  
           [0008]    Because this method involves replacing the originally stored data with known data, it is often called a “destructive read.” Destructive read methods require numerous operations on the storage location. A read method that accommodates position-dependent variation while requiring fewer operations may offer higher access rates.  
         BRIEF SUMMARY  
         [0009]    Accordingly, methods and apparatuses are disclosed for retrieving data stored in a magnetic integrated memory. In one embodiment, the method comprises: a) applying a perturbing hard-axis magnetic field to a magnetic element in a magnetic integrated memory; and b) detecting a change in an electrical parameter caused by said perturbing hard-axis magnetic field. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    For a detailed description of exemplary embodiments, reference will now be made to the accompanying drawings in which:  
         [0011]    [0011]FIG. 1 shows a computer system in which certain embodiments may be employed;  
         [0012]    [0012]FIGS. 2 a - 2   c  show examples of magnetic integrated memory architectures in accordance with certain embodiments;  
         [0013]    [0013]FIGS. 3 a - 3   b  show examples of magnetic tunneling junction (MTJ) memory elements in accordance with certain embodiments;  
         [0014]    [0014]FIGS. 4 a - 4   b  show examples of giant magneto-resistive (GMR) memory elements in accordance with certain embodiments;  
         [0015]    [0015]FIGS. 5 a - 5   c  show examples of electrical models of certain memory cell array embodiments;  
         [0016]    [0016]FIGS. 6 a - 6   c  show examples of electrical models of certain alternative memory cell array embodiments;  
         [0017]    [0017]FIGS. 7 a - 7   c  show examples of certain sense circuit embodiments; and  
         [0018]    [0018]FIG. 8 shows a flow diagram for an example of certain method embodiments. 
     
    
     NOTATION AND NOMENCLATURE  
       [0019]    Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, computer companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.  
       DETAILED DESCRIPTION  
       [0020]    The drawings and following discussion are directed to various embodiments. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.  
         [0021]    [0021]FIG. 1 shows a computer system, an example of where a magnetic memory may be employed. The computer system of FIG. 1 includes a central processing unit (CPU)  10  coupled by a bridge  12  to a system memory  14  and a display  16 . CPU  10  is further coupled by bridge  12  to an expansion bus  18 . Also coupled to the expansion bus  18  are a storage device  20  and an input/output interface  22 . A keyboard  24  may be coupled to the computer via input/output interface  22 .  
         [0022]    CPU  10  may operate in accordance with software stored in memory  14  and/or storage device  20 . Under the direction of the software, the CPU  10  may accept commands from an operator via keyboard  24  or some alternative input device, and may display desired information to the operator via display  16  or some alternative output device. CPU  10  may control the operations of other system components to retrieve, transfer, and store data.  
         [0023]    Bridge  12  coordinates the flow of data between components. Bridge  12  may provide dedicated, high-bandwidth, point-to-point buses for CPU  10 , memory  14 , and display  16 .  
         [0024]    Memory  14  may store software and data for rapid access. Memory  14  may be magnetic integrated memory. Alternatively, memory  14  may be volatile integrated memory.  
         [0025]    Display  16  may provide data for use by an operator. Display  16  may further provide graphics and may include advanced graphics processing capabilities.  
         [0026]    Expansion bus  18  may support communications between bridge  12  and multiple other computer components. Bus  18  may couple to removable modular components and/or components integrated onto a circuit board with bridge  12  (e.g., audio cards, network interfaces, data acquisition modules, or modems).  
         [0027]    Storage device  20  may store software and data for long-term preservation. Storage device  20  may be portable, or may accept removable media, or may be an installed component, or may be a integrated component on the circuit board. Storage device  20  may be magnetic integrated memory. Alternatively, storage device  20  may be a nonvolatile integrated memory, a magnetic media storage device, an optical media storage device, or some other form of long-term information storage.  
         [0028]    Input/output interface  22  may support communications with legacy components and devices not requiring a high-bandwidth connection. Input/output interface  22  may further include a real-time clock and may support communications with scan chains for low-level testing of the system.  
         [0029]    Keyboard  24  may provide data in response to operator actuation. Other input devices (e.g., pointing devices, buttons, or sensors) may also be coupled to input/output interface  22  to provide data in response to operator actuation. Output devices (e.g., parallel ports, serial ports, printers, speakers, or lights) may also be coupled to input/output interface  22  to communicate information to the operator.  
         [0030]    In addition to the above-described system, many other general purpose and customized digital devices and systems may beneficially employ magnetic integrated memories.  
         [0031]    [0031]FIG. 2 a  shows a first architecture for a magnetic integrated memory  100 . Memory  100  includes a memory cell array  102  and support circuitry  104 . Memory cell array  102 , as the name suggests, is an array of cells (see, e.g., FIG. 5 a ). Each cell can store a data value (e.g., a bit), and may be identified by its position (e.g., by row and column coordinate).  
         [0032]    Support circuitry  104  may receive an address signal, a read/write signal, and a data signal. The address signal may represent an address value as a binary number. Each address value may be associated with one or more cells in the memory array. For example, each cell may be associated with a unique address value. As an alternative example, each address value may be associated with a corresponding ordered set of 64 cells.  
         [0033]    The read/write signal may be a signal with at least two values, one value being the “asserted” state, and the other value being the “de-asserted” state. In the asserted state, the read/write signal may cause a read operation to occur, in which data is retrieved from the memory cell array  102 . In the de-asserted state, the read/write signal may cause a write operation to occur, in which data is stored in the memory cell array.  
         [0034]    The data signal may represent a data value as a binary number. The data signal may be bi-directional so that it may be received by the support circuitry  104  during a read operation, and may be provided by the support circuitry  104  during a write operation. Although the address, read/write, and data signals are shown separately, they may be multiplexed with each other and/or multiplexed with other signals.  
         [0035]    Support circuitry  104  may be coupled to memory cell array  102  by row lines  106  and column lines  108 . Depending on the memory cell architecture, data may be retrieved from memory cell(s) associated with an address by asserting a row line associated with the address and de-asserting all the other row lines. The data may be available as a voltage or current signal on the column line(s) associated with the address value. Alternatively, data may be sequentially retrieved from the memory cell(s) associated with an address by selectively passing individual currents through the cell(s). These methods will be described in greater detail when FIG. 5 a  is discussed below.  
         [0036]    Support circuitry  104  may store data in memory cell(s) associated with an address by simultaneously passing currents through associated row and column lines. When multiple cells are associated with an address value, the data storage in the cells may be performed sequentially or in parallel, depending on the cell architecture.  
         [0037]    [0037]FIG. 2 b  shows a second architecture for magnetic integrated memory  100 . This embodiment has a “three conductor” architecture in which the support circuitry  104  is coupled to memory cell array  102  by pairs of row lines  110  and single column lines  108 . One of the row lines in each pair (the “row sense” line) may be used for establishing direct electrical contact with storage element(s) in associated memory cell(s). The other row line in each pair (the “row affect” line) may be used for establishing magnetic coupling with the storage element(s) in associated memory cell(s). During read operations, both row lines may be used simultaneously to achieve a non-destructive read operation that is insensitive to memory cell variations.  
         [0038]    [0038]FIG. 2 c  shows a third architecture for magnetic integrated memory  100 . This embodiment has a “four conductor” architecture in which the support circuitry  104  is coupled to memory cell array  102  by column line pairs  112  as well as by row line pairs  110 . As with the row line pairs, the column line pairs may include a line for direct electrical contact (the “column sense” line) and a line for magnetic coupling (the “column affect” line).  
         [0039]    Many types of memory cells may be suitable for use in memory cell array  102 . FIG. 3 a  shows one example in idealized form: a magnetic tunnel junction (MTJ). The MTJ may be formed by placing a thin nonconductive layer  202  between a conductive hard magnetic layer  204  and a conductive soft magnetic layer  206 . When a voltage is established between the magnetic layers  204  and  206 , current carriers “tunnel” through the nonconductive layer  202 . Accordingly, the MTJ structure electrically resembles a resistor.  
         [0040]    Importantly, the MTJ resistance may be adjusted. When the orientations of the magnetic layers  204  and  206  are aligned (parallel) as shown by arrows  208  and  210 , the resistance is lower than when the orientations are opposed (anti-parallel) as shown by arrows  208  and  212  (FIG. 3 b ).  
         [0041]    With respect to magnetic materials, the terms “hard” and “soft” connote relatively high and low magnetic coercivities, respectively. A soft magnetic material can be oriented by a weaker magnetic field than can a hard magnetic material. Thus, soft magnetic layer  206  can be re-oriented without altering the orientation of hard magnetic layer  204 , simply by not allowing the magnetic field to exceed the critical level required for re-orienting the hard magnetic layer.  
         [0042]    Another factor that determines the orientation of the magnetic layers is the “easy axis.” Each of the layers may have an axis of preferential orientation along which less of a magnetic field is required to orient the layer, and along which the persistent magnetization of the layer will point (e.g., arrows  208 ,  210 ,  212 ). Such an axis may be established by the geometry of the layer and/or by a crystalline orientation of the layer and/or by providing an anti-ferromagnetic layer for exchange biasing. Axes perpendicular to the easy axis are “hard” axes, and may require much higher fields to establish a persistent orientation. In some cases, magnetization along these axes may not be stable.  
         [0043]    Arrow  214  shows a field along a hard axis of the soft magnetic layer  206 . Such a field may be established by passing a current along conductor  216  as shown by arrows  218 . Current flowing in conductor  216  creates a circular magnetic field around the conductor in accordance with the “right hand rule.” A current flowing in conductor  216  may make soft magnetic layer  206  more susceptible to re-orientation by a magnetic field along its easy axis. Such a field may be provided by a current flowing through conductor  220  as shown by arrows  222 . Current flowing in the direction shown may orient the soft magnetic layer  206  as shown by arrow  210 . A current flowing in the opposite direction through conductor  220  while current flows in conductor  216  may orient the soft magnetic layer as shown by arrow  212  (FIG. 3 b ). Thus currents flowing through a row line  106  and column line  108  (FIG. 2 a ) may store information by appropriately orienting a magnetic layer at the intersection of the row and column lines.  
         [0044]    Conductors  216  and  220  may be in electrical contact through the MTJ. A parallel orientation of layers in the MTJ (arrows  208  and  210  in FIG. 3 a ) may be detected as a (relatively) low resistance between conductors  216  and  220 , while an anti-parallel orientation (arrows  208  and  212  in FIG. 3 b ) may be detected as a (relatively) high resistance between these conductors.  
         [0045]    However, position-dependent variation of memory cell characteristics may make it difficult to determine when a measured resistance value is high or low without using destructive read techniques. As an alternative, the resistance state of the memory cell may be detected by measuring a change in resistance caused by placing a perturbing hard axis field across the MTJ, e.g., in the direction shown by arrow  214 .  
         [0046]    A transient hard-axis field may temporarily alter the effective orientation of the magnetic layers  204  and  206 , partially and temporarily “rotating” their orientations in the direction of the transient field. (The rotations for the different layers may be unequal.) For MTJs in the anti-parallel orientation state, this rotation may decrease the resistance value since the layer orientations are “less” anti-parallel. For MTJs in the parallel orientation state, this rotation may increase the resistance value since the layer orientations are “less” parallel. Accordingly, the parallel and anti-parallel states may be distinguished by the sign of the resistance change caused by a perturbing hard axis field. The perturbing field may be imposed by an element external to the memory cell.  
         [0047]    [0047]FIG. 3 b  shows an alternative example of a memory cell. The memory cell of FIG. 3 b  includes the structural elements of the two-conductor MTJ memory cell of FIG. 3 a , and may further include an affect conductor  224  that runs parallel to conductor  216 . The affect conductor  224  may be separated from conductor  216  by an insulating layer  226 . In addition, a second affect conductor  228  may be included and may run parallel to conductor  220 . Affect conductor  228  may be separated from conductor  220  by an insulating layer  230 . As shown, the memory cell of FIG. 3 b  is a four-conductor configuration. A three conductor configuration may be obtained by omitting affect conductor  228 .  
         [0048]    Affect conductors  224  and  228  may be used to establish the orientation of soft magnetic layer  206 . Conductors  216  and  220  may be used as sense conductors for determining the resistance of the MTJ. During a sense operation, a transient current may be passed through conductor  224  to create a perturbing hard-axis field as indicated by arrow  214 . The sign of the resulting change in resistance may be used to determine the state of the MTJ.  
         [0049]    [0049]FIG. 4 a  shows another example of a memory cell. Unlike an MTJ, the present example includes a conductive layer  302  sandwiched between a hard magnetic layer  304  and a soft magnetic layer  306 . Current flowing through conductor  308  (and consequently though layer  302 ) experiences a resistance that depends on the relative magnetic orientations of layers  304  and  306 . The resistance of the magnetic memory cell comprising layers  304 ,  302  and  306  may be low when the orientations of layers  304  and  306  are aligned (as shown by arrows  310  and  312 ). Conversely, when the orientations the layers are opposed, the resistance of the magnetic memory cell may be high.  
         [0050]    The easy axes of the layers may be transverse to the axis of conductors  308  and  314 . The orientation of soft layer  306  may be set in the direction shown by arrow  312  by passing currents through conductors  308  and  314  in the directions shown by arrows  316  and  318 , respectively. (Conductor  314  may be electrically isolated from the memory cell.) The magnetic fields around conductors  308  and  314  may combine to provide a magnetic field strength sufficient to re-orient soft layer  306 , where the fields individually would be insufficient to do so. The orientation of layer  306  may be set in a direction opposite arrow  312  by reversing the currents in both conductors.  
         [0051]    Arrow  320  shows a field along a hard axis of soft magnetic layer  306 . As before, a transient hard-axis field may temporarily “rotate” the orientations of layers  304  and  306 . The rotations for the hard and soft layer may be unequal. In a preferred embodiment, the rotation of the hard layer is small compared to the rotation of the soft layer). When the layers are in an anti-parallel state, the rotation may decrease the resistance since the orientations are “less” opposed. Conversely, when the layers are in a parallel state, the rotation may increase the resistance since the orientations are “less” aligned. The perturbing field may be imposed by an element external to the memory cell.  
         [0052]    [0052]FIG. 4 b  shows yet another alternative example of a memory cell. It may include the structural elements of the memory cell in FIG. 4 a , and may further include an affect conductor  322 . Affect conductor  322  may be electrically isolated from the other components of the memory cell. A transient current passing through affect conductor  322  as shown by arrows  324  may temporarily impose a perturbing hard axis field in the direction of arrow  320 . The resulting change in resistance to current flowing through conductor  308  may be used to determine the state of the memory cell.  
         [0053]    [0053]FIG. 5 a  shows an electrical model for a memory cell array  102  having MTJs as memory cells. At each intersection between a row line and a column line there is a corresponding memory cell, e.g., memory cell  402  corresponds to the intersection between row line n- 1  and column line k- 1 . Each memory cell may store data in the form of a magnetization state, and the magnetization state may be detectable as a resistance change during a read operation.  
         [0054]    To read the contents of a memory cell, say memory cell  402 , the corresponding row line may be asserted (driven to a predetermined potential) while all the other row lines are de-asserted (driven to a complementary potential). Concurrently, the corresponding column line may be de-asserted while all the other column lines are asserted. The current flowing from the corresponding row line to the corresponding column line may then be measured and monitored for changes caused by perturbations of a hard-axis field. An increase in current (which may indicate a decrease in resistance) may represent one binary value, while a decrease in current (which may indicate an increase in resistance) may represent another binary value. Other suitable sensing methods are described in U.S. Pat. Nos. 6,259,644 and 6,424,565, which are hereby incorporated by reference.  
         [0055]    [0055]FIG. 5 b  shows an electrical model for an alternative memory cell  402  having an MTJ in series with a diode. The diode may be inherent in the MTJ structure or the diode may be created through extra processing steps. To read the contents of memory cell  402 , the corresponding row line is asserted, and the corresponding column line is de-asserted. The current flowing to the column line may then be measured and monitored for changes caused by perturbations of a hard-axis field. An increase in current may be indicative of one binary value, while a decrease in current may be indicative of the complementary value.  
         [0056]    [0056]FIG. 5 c  shows an electrical model for an alternative memory cell  402  having the structure of FIG. 4 a . To read the contents of memory cell  402 , a current may be passed through the corresponding column line. The voltage drop across the column of cells may be measured and monitored for changes caused by a hard axis field perturbation to memory cell  402 .  
         [0057]    [0057]FIGS. 5 a - 5   c  show electrical models applicable to two-conductor memory cells. FIGS. 6 a - 6   c  show corresponding models for three-conductor memory cells. In FIG. 6 a , three sets of lines are shown: row lines, column lines, and perturbation lines. The perturbation lines may be affect lines (previously described) paired with the row lines. The read operations described above with respect to FIGS. 5 a - 5   c  may be applied to the corresponding model in FIGS. 6 a - 6   c . The hard-axis field perturbations described in each of the read operations may be produced by passing a transient current through the perturbation line that is paired with the corresponding row line.  
         [0058]    [0058]FIG. 7 a  shows one example of a sense circuit which may be included in support circuitry  104  to detect resistance changes caused by a hard-axis field perturbation. The sense input may be configured to receive a voltage indicative of current flowing in a column line (e.g., via a current mirror of a virtual ground). Alternatively, the sense input may be coupled to a column line to detect a voltage drop on the column line. A buffer  502  may amplify the sense signal and may provide the sense signal to a differentiator  504 .  
         [0059]    Differentiator  504  may comprise a series capacitor  508  and one or more bias resistors  510 . Differentiator  504  may take a derivative of the sense signal and may provide the derivative to a comparator  506 . Comparator  506  may compare the derivative to a threshold voltage (e.g., ground) and may determine if the derivative is above the threshold (positive) or is below the threshold (negative).  
         [0060]    The output of the comparator on a clock edge may be indicative of a data value. For example, if a positive change in current or voltage is indicative of a binary “1,” a positive derivative may cause comparator  506  to assert the data line as an active-high signal. Conversely, if a negative change in current or voltage is indicative of a binary “1,” a negative derivative may cause comparator  506  to assert the data line as an active-low signal.  
         [0061]    [0061]FIG. 7 b  shows another example of a sense circuit which may be included in support circuitry  104  to detect resistance changes caused by a hard-axis field perturbation. The differentiator is replaced with a sample-and-hold circuit and bypass. The sample and hold circuit comprises a switch  512  and a capacitor  514 . During a first portion of the read operation, switch  512  is closed and capacitor  514  follows the sense signal from amplifier  502 . During a second portion of the read operation, switch  512  is opened, and capacitor  514  holds a “before” sample of the sense signal, i.e., the sense signal value at the time the switch  512  is opened. Comparator  506  compares the before sample with the sense signal received via the bypass line. If the sense signal is rising, comparator  506  detects a positive difference, whereas if the sense signal is falling, comparator  506  detects a negative difference. Signal changes caused by hard-axis field perturbations can thus be detected and converted to indications of stored digital data.  
         [0062]    [0062]FIG. 7 c  shows yet another example of a sense circuit which may be included in support circuitry  104  to detect resistance changes caused by a hard axis field perturbation. The sense circuit includes two copies of the sense circuit of FIG. 7 a . One copy receives the sense input, while the other copy receives the perturbation signal (e.g., a voltage indicative of a current flowing in an affect conductor). The outputs of each sense circuit may be “high” when the signal derivative is positive, and may be “low” when the signal derivative is negative.  
         [0063]    If an increase in the hard-axis perturbation (caused by an increase in the perturbation signal) leads to an increase in current, the two derivatives may be in phase with each other. Conversely, if the increase in hard-axis perturbation leads to a decrease in current, the two derivatives may be 180 degrees out-of-phase with each other. A phase detector  520  may be used to determine the phase relationship between the sense signal and the perturbation signal.  
         [0064]    A significant increase in signal-to-noise ratio (SNR) may be achieved by making the perturbation signal an alternating signal that cycles multiple times during a read operation. Accordingly, the phase detector may include an exclusive-or (XOR) gate  522  and a counter  524 . An out-of-phase relationship may be indicated by an asserted output from XOR gate  522 , and an in-phase relationship may be indicated by a de-asserted output from XOR gate  522 . Counter  524  may combine multiple values from gate  522  to reduce any probability of error. If the counter exceeds a predetermined threshold, an out-of-phase relationship may be determined, and the data line may be asserted accordingly. Counter  524  may be reset after each read operation.  
         [0065]    [0065]FIG. 8 shows a flow diagram of a read method for magnetic integrated memories. In block  602 , data may be stored in a magnetic memory cell. The storing operation may involve suitably orienting an easy-axis magnetization of a magnetic layer parallel or anti-parallel to the persistent magnetization of a second magnetic layer. At some subsequent time, the data may be read from the magnetic memory cell as indicated by block  604 . In block  604 , a measurement may be performed to detect a resistance change caused by perturbing a hard-axis field of one or both of the magnetic layers. The sign of the resistance change may be indicative of the stored data.  
         [0066]    The above-described hard-axis perturbation technique may be applied to a host of magnetic integrated memory technologies including ferromagnetic memory (FRAM), spin-dependent tunneling (SDT) memory, pseudo-spin valve resistance (PSV) memory, crosstie memory (CRAM), memories employing anisotropic magneto-resistance (AMR) materials, giant-magneto-resistance (GMR) sensors, induction sensors, hall-effect sensors, and more.  
         [0067]    The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. The terms row and column may be exchanged throughout the discussion above. Though two, three, and four conductor architectures have been described, the principles described herein may be readily applied to architectures having architectures with different numbers and arrangements of conductors. It is intended that the following claims be interpreted to embrace all such variations and modifications.