Abstract:
The invention concerns a method for maintaining an optimal operating point of an LDMOS device ( 32 ) stable, said LDMOS device ( 32 ) producing an output signal including an error signal component (err). The method comprises separating said error signal component (err) from the output signal of said LDMOS device ( 32 ) and using said error signal component (err) for controlling the gate-to-source bias voltage, or Vgs, of said LDMOS device ( 32 ) to maintain the optimal operating point of said LDMOS device ( 32 ) stable.

Description:
FIELD OF THE INVENTION  
         [0001]    The invention relates to a method and an arrangement for maintaining an optimal operating point of LDMOS semiconductor devices stable. The invention is especially useful in a feedforward amplifier arrangement.  
         BACKGROUND OF THE INVENTION  
         [0002]    Particularly in broadband amplifiers and in power amplifiers, amplifier non-linearities cause distortion to an output signal. FIG. 1 illustrates the formation of intermodulation products (IM-products) causing distortion to an output signal. An undistorted input signal  12  consisting of two frequency components ω 1  and ω 2  is fed into an amplifier  14 . At the output of the amplifier  14  appears a distorted signal  16 , which includes desired signal components at frequencies ω 1  and ω 2  and also two strong undesired signal components close to the desired signal components at the frequencies 2*ω 1 -ω 2  and 2*ω-ω 1 . These undesired signals may appear in the desired signal band, and thereby corrupt the output signal.  
           [0003]    LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices are relatively new semiconductor devices, which have improved characteristics compared to conventional semiconductor devices. For example, they have improved IM performance, i.e. they produce less IM-products at the same input power than the conventional semiconductor devices. Typical input power/IM-products curves of a conventional semiconductor device and of an LDMOS device are illustrated in FIG. 2 by a dashed line and a solid line, respectively. In a conventional semiconductor device, the amount of IM-products increases as the input power increases. The advantage of an LDMOS device is that it has an optimal operating point called “sweet point” producing an optimal input power/IM-products ratio.  
           [0004]    The characteristics of LDMOS devices make them especially well suited for power amplification. However, they are not widely used at the moment. A reason for this is a considerable drift in gate-source bias voltage, or Vgs. The Vgs is a DC voltage which is used to provide a certain drain-source quiescent current, or ldq. The location of the “sweet point” on the input power axis in FIG. 2 is dependent on this quiescent current. Therefore, the Vgs can be used to set the “sweet point”, i.e. optimal operating point, to the preferred input power level. However, if the Vgs is kept constant, the ldq decreases in the course of time because of aging of the LDMOS transistors. In other words, the Vgs corresponding to a certain ldq changes in the course of time. This kind of drift in bias voltage due to transistor aging also appears in “normal” semi-conductor devices, but it is a considerable problem with LDMOS transistors, in particular. Therefore, a method of keeping the ldq constant is needed for LDMOS devices in order to maintain their “sweet point” at the desired signal level. This object can be achieved by reducing the Vgs drift or by adjusting the Vgs for keeping the ldq constant.  
           [0005]    One possible method of reducing the Vgs drift is to “burn in” LDMOS devices before they are used, because the drift phenomenon is most considerable at the beginning of the use of an LDMOS device. The disadvantage of this procedure is that it reduces the lifetime of the device. Additionally, “burn in” is difficult and expensive to implement.  
           [0006]    Since the Vgs drift has been reduced from more than 25% to 5% for 900 MHz parts and to 12-15% for 2 GHz parts by device manufacturers, the problem of the drift has diminished. However, the problem has not disappeared, because a 10% drift may produce 5-10 dB IM-products, which is still relatively much in a linear amplifier.  
           [0007]    One proposed method of adjusting the Vgs to keep the ldq constant is to measure the ldq and make Vgs adjustments on the basis of the measured ldq. The problem in this kind of an arrangement is that the amplifier has to be shut down during the measurement. Additionally, the transistor characteristics that vary from one transistor to another have an effect on the measurement results.  
         DISCLOSURE OF THE INVENTION  
         [0008]    An object of the present invention is to overcome or alleviate the above described problems by providing a method and an arrangement for keeping the ldq constant in an LDMOS device.  
           [0009]    The object is achieved by a method and an arrangement which are characterized by what is disclosed in the attached independent claims. Preferred embodiments of the invention are disclosed in the attached dependent claims. ln the present invention the bias voltage Vgs of an LDMOS device is adjusted to keep the ldq of the device constant and consequently to maintain an optimal operating point, i.e. the “sweet point”, of the device stable. The invention employs a method known from a feedforward amplifier arrangement. A feedforward amplifier arrangement is one possible solution to achieve high power amplification, high efficiency and low distortion. In a feedforward amplifier arrangement, distortion in the output signal of the arrangement is reduced by separating an error signal component from the output signal of the amplifier and then subtracting this error signal component from the output signal of the amplifier containing the error signal component. Thus, the error signal components cancel each other out and the resulting output signal contains considerably less distortion than the original output signal of the amplifier.  
           [0010]    According to the invention, this kind of separate error signal component is used for controlling the Vgs of an LDMOS device to maintain the optimal operating point of the LDMOS device stable. The absolute value of the error signal component at the output of the LDMOS device is defined and the Vgs is adjusted in response to this error signal component so that the error signal component at the output of the LDMOS device reaches its minimum.  
           [0011]    This invention provides a simple way to control the operating point of LDMOS devices. The invention suits especially well for a feedforward amplifier arrangement, since it employs an error signal that is already generated in a feedforward arrangement and therefore, only few extra components are needed. An advantage of a preferred embodiment of the invention is also that the amplifier does not need to be completely shut down during the Vgs adjustment. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    In the following, the invention will be described in greater detail by means of preferred embodiments with reference to the accompanying drawings, in which  
         [0013]    [0013]FIG. 1 illustrates formation of IM-products,  
         [0014]    [0014]FIG. 2 illustrates typical input power/IM-products curves of a conventional semiconductor device and of an LDMOS device,  
         [0015]    [0015]FIG. 3A is a block diagram illustrating an arrangement according to the invention,  
         [0016]    [0016]FIG. 3B is a block diagram illustrating an embodiment according to the invention,  
         [0017]    [0017]FIG. 4 is a block diagram illustrating another embodiment according to the invention,  
         [0018]    FIG. 5  is a flow chart illustrating the operation of the Vgs control block according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    The present invention can be applied to bias voltage control of an LDMOS device. In the following, the preferred embodiments of the invention will be described by means of a feedforward arrangement, but the invention is not limited to a feedforward arrangement. The same reference numerals are used for equivalent components in the figures.  
         [0020]    [0020]FIG. 3A illustrates a block diagram of an arrangement according to the invention including an LDMOS device  32 , error signal separating means  30  and Vgs control means  39 . The LDMOS device  32  receives an input signal In and produces, on the basis of this input signal In, an output signal including distortion. This output signal of the LDMOS device is connected to the error signal separating means  30  together with the input signal In. The error signal separating means  30  produce an error signal component err which is connected to the Vgs control means  39 . On the basis of the error signal component err, the Vgs control means adjust the Vgs of the LDMOS device  32  to keep the operating point of the LDMOS device  32  stable.  
         [0021]    [0021]FIG. 3B illustrates an embodiment of the invention including a basic feedforward arrangement  31  and Vgs control means  39 . The feedforward arrangement includes an LDMOS amplifier  32 , attenuation means  35 , time (delay) adjusting means  33  and  36 , adders  34  and  37  and an error signal amplifier  38 . An input signal In is connected to an input of the LDMOS amplifier  32 . For obtaining an error signal component err, the input signal is adjusted in time (delayed) with time adjusting means  36  for producing signal A and the output signal of the LDMOS amplifier  32  is attenuated with attenuation means  35  for obtaining signal B. In this way, signals A and B, which are fed into the adder  37 , have equal amplitudes and a 180° phase difference relative to each other, and the error signal component err is obtained as an output of the adder  37 . For obtaining an output signal Out, in which the error signal component is canceled, the error signal component err is amplified by the error signal amplifier  38  for obtaining signal C and the output signal of the LDMOS amplifier  32  is adjusted in time (delayed) with time adjusting means  33  for obtaining signal D. In this way, signals C and D, which are fed into the adder  34 , have equal amplitudes and a 180° phase difference relative to each other, and the output signal Out, in which the error signal component is canceled, is obtained as an output of the adder  34 .  
         [0022]    According to the embodiment shown in FIG. 3, the error signal component err is also connected to the Vgs control means  39 . The Vgs control means produce the Vgs for the LDMOS amplifier  32  on the basis of the error signal component err, as will be described later in connection with FIG. 5.  
         [0023]    [0023]FIG. 4 illustrates another embodiment of the invention including a feedforward arrangement  40  and Vgs control means  39 . The feedforward arrangement  40  includes an LDMOS amplifier  32 , adders  34  and  37 , time (delay) adjusting means  33  and  36  and an error signal amplifier  38 , all of which operate essentially in the same way as in the arrangement of FIG. 3B. Gain/phase adjustment means  41  are added for adjusting the phase φ and gain A of the input signal In before amplification. Additionally, the arrangement  40  includes down converter means  44  for converting the error signal and the input signal to a lower frequency, and A/D converters  45  and  46  for converting respective downconverted signals to a digital form for digital signal processing. In response to the output signals of the A/D converters  45  and  46 , signal processing means  47  produce a control signal which is connected to adjustment means  41  via sample &amp; hold means  48  and a D/A converter  49 .  
         [0024]    The error signal component err obtained as an output of the A/D converter  45  is also connected to the Vgs control means  39 . The Vgs control means produce the Vgs for the LDMOS amplifier  32  on the basis of the error signal component err. The error signal component err is handled in digital domain by the Vgs control means, and the Vgs is produced in a digital form and then converted to an analog form by the Vgs control means.  
         [0025]    The operation of the adjustment means in FIGS. 3B and 4 must not be changed during the Vgs adjustment, but otherwise the LDMOS amplifier  32  can be operated normally. In other words, the LDMOS amplifier does not have to be completely shut down during the Vgs adjustment.  
         [0026]    [0026]FIG. 5 is a flow chart illustrating the operation of a possible implementation of the Vgs control means  39  in FIGS. 3 and 4. This implementation tries several Vgs values, each attempt having an attempt number N. In step  51 , the power level of the Nth error signal err(N) is measured. Then Vgs is increased in step  52  and the power level of the (N+1)th error signal err(N+1) is measured in step  53 . In step  54 , the power levels of Nth and (N+1)th error signal are compared and, if err(N)&gt;err(N+1), N is incremented in step  55  and steps  52  to  54  are repeated. Otherwise, the Vgs is first decreased to the value corresponding the Nth error signal in step  56  and then decreased again in step  57 . Next, the power level of the (N+1)th error signal err(N+1) is measured in step  58 , and the power levels of Nth and (N+1)th error signal are compared in step  59 . If err(N)&gt;err(N+1), N is incremented in step  60 , and steps  57  to  59  are repeated. Otherwise, the Vgs is increased to the value corresponding the Nth error signal in step  61 , and the operation is terminated in step  62 .  
         [0027]    The description only illustrates preferred embodiments of the invention. The invention is not, however, limited to these examples, but it may vary within the scope of the appended claims.