Abstract:
An image pickup apparatus has a solid-state image pickup device which outputs a charge signal according to a timing signal, a sampling unit which samples the charge signal in response to the timing signal, an A/D converting unit which converts a sample signal to a digital signal in response to the timing signal, and a timing unit which, in response to the number of first clocks in a horizontal period of the timing signal when a picture signal is outputted at a first frame rate (60 fps), generates a timing signal having the number of clocks in the horizontal period higher than the number of the first clocks, and supplies a timing signal based on the generated timing signal, the sampling unit, and the A/D converting unit in case of a second frame rate (50 fps) lower than first frame rate.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-303256, filed Oct. 18, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an image pickup apparatus which uses a solid-state image pickup device such as a charge coupled device (CCD), and more particularly, to an image pickup apparatus and an image pickup method for converting a frame rate.  
         [0004]     2. Description of the Related Art  
         [0005]     Conventionally, an image pickup apparatus for receiving picture light and outputting a frame rate in response to the receipt of the light has been well known as that which uses a solid-state image pickup device such as, for example, a CCD. In such an image pickup apparatus, it becomes possible to output a picture signal at plural types of resolutions.  
         [0006]     Patent document 1 (Jpn. Pat. Appln. KOKAI Publication No. 2000-23007) discloses a CCD image pickup apparatus for switching a picture signal in accordance with a plurality of resolutions, wherein a user can select a picture signal according to an arbitrary resolution as required.  
         [0007]     However, in the prior art of Patent document 1, it is impossible to known what to do when an attempt is made to change a frame rate of the image pickup apparatus. That is, in general, in the CCD image pickup apparatus, a frame rate of 50 fps or a frame rate of 60 fps is known. However, there is a problem that an image pickup apparatus designed for use in the frame rate of 60 fps cannot be easily changed so as to obtain a picture output at the frame rate of 50 fps.  
       BRIEF SUMMARY OF THE INVENTION  
       [0008]     An embodiment of the present invention is an image pickup apparatus comprising: a solid-state image pickup device which receives a picture light and outputs a charge signal according to the receipt of the light in response to a given timing signal; a sampling unit which samples the charge signal from the solid-state image pickup device in response to the given timing signal and outputs a sample signal according to a result of the sampling; an A/D converting unit which converts the sample signal from the sampling unit to a digital signal in response to the given timing signal; a digital processing unit which applies predetermined processing for the digital signal and outputs the processed signal; a D/A converting unit which outputs a picture signal obtained by converting to an analog signal the digital signal to which the predetermined processing has been applied; and a timing unit which, in response to the number of first clocks in a horizontal period of the timing signal supplied in the case where a picture signal of a first frame rate (60 fps) is obtained from the D/A converting unit, generates a timing signal having the number of clocks in the horizontal period than the number of the first clocks, and supplies a timing signal based on the generated timing signal to at least one of the solid-state image pickup device, the sampling unit, and the A/D converting unit in the case where a picture signal of a second frame rate (50 fps) which is lower than the first frame rate. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0009]      FIG. 1  is a block diagram depicting an example of a configuration of an image pickup apparatus according to one embodiment of the present invention;  
         [0010]      FIG. 2  is a plan view showing an example of a configuration of a CCD element in the image pickup apparatus according to the embodiment of the invention;  
         [0011]      FIG. 3  is an illustrative view for explaining a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing a CCD drive frequency in the image pickup apparatus according to the embodiment of the invention;  
         [0012]      FIG. 4  is a timing chart showing a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing a CCD drive frequency in the image pickup apparatus according to the embodiment of the invention;  
         [0013]      FIG. 5  is a timing chart showing a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing a CCD drive frequency in the image pickup apparatus according to the embodiment of the invention;  
         [0014]      FIG. 6  is an illustrative view for explaining a case in which conversion from a frame rate of 60 fps to 50 fps has been made by increasing the number of horizontal period clocks in the image pickup apparatus according to the embodiment of the invention;  
         [0015]      FIG. 7  is a timing chart showing a case in which conversion from a frame rate of 60 fps to 50 fps has been made by increasing the number of horizontal period clocks in the image pickup apparatus according to the embodiment of the invention;  
         [0016]      FIG. 8  is an illustrative view for explaining a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing the number of horizontal period clocks in the image pickup apparatus according to the embodiment of the invention; and  
         [0017]      FIG. 9  is a timing chart showing a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing the number of horizontal period clocks in the image pickup apparatus according to the embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.  
         [0019]     An image pickup apparatus according to the invention is an image pickup apparatus using a solid state image pickup device such as a CCD.  FIG. 1  is a block diagram depicting an example of a configuration of an image pickup apparatus according to one embodiment of the invention;  FIG. 2  is a plan view showing an example of a configuration of a CCD element in the image pickup apparatus;  FIG. 3  is an illustrative view for explaining a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing a CCD drive frequency in the image pickup apparatus;.  FIG. 4  is a timing chart showing a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing a CCD drive frequency in the image pickup apparatus;  FIG. 5  is a timing chart showing a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing a CCD drive frequency in the image pickup apparatus;  FIG. 6  is an illustrative view for explaining a case in which conversion from a frame rate of 60 fps to 50 fps has been made by increasing the number of horizontal period clocks in the image pickup apparatus;  FIG. 7  is a timing chart showing a case in which conversion from a frame rate of 60 fps to 50 fps has been made by increasing the number of horizontal period clocks in the image pickup apparatus;  FIG. 8  is an illustrative view for explaining a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing the number of horizontal period clocks in the image pickup apparatus; and  FIG. 9  is a timing chart showing a case in which conversion from a frame rate of 60 fps to 50 fps has been made by decreasing the number of horizontal period clocks in the image pickup apparatus.  
         [0000]     &lt;Configuration of Image Pickup Apparatus According to the Present Invention&gt; 
         [0020]     An image pickup apparatus M according to the invention, as shown in  FIG. 1 , has a CCD  11  which is a solid-state image pickup device; a correlate double sample (CDS) circuit  12  which is an analog circuit for receiving a charge signal being an output from the CCD; a filter  13  for filtering the output at a high frequency; a signal processing unit  14  for carrying out color correction and gamma correction in response to the filter output; an A/D converter  15  for A/D converting the output; a digital signal processing unit  16  for carrying out, for example, G-channel pixel correction processing, scaling processing, IP conversion and the like with respect to the converted digital signal; and a D/A converter  17  for D/A converting the output.  
         [0021]     Here, the CCD  11 , the CDS circuit  12 , the filter  13 , the signal processing unit  14 , the A/D converter  15 , the digital signal processing unit  16 , the D/A converter  17  and the like, of the image pickup apparatus M are configured so that three sequences are in parallel to each other for each of an R channel, a G channel, and a B channel, if the image pickup apparatus M outputs an image signal of each of the RGB.  
         [0022]     On the other hand, the image pickup apparatus M, unlike these constituent elements, has: an oscillator  20  using crystal oscillation or the like; a timing generator for receiving an oscillating clock from the oscillator and supplying a desired timing signal to the CCD  11 , the CDS  12 , the A/D converter  15  and the like; a ROM  21  for supplying a program and a set value to the timing generator  18 ; and a V driver  19  for receiving a desired timing signal from the timing generator  18  and supplying a vertical drive pulse to the CCD  11 .  
         [0023]     In addition, in the CCD element  11  which is a solid-state image pickup device, as shown in  FIG. 2  as one example, elements in vertical 768 lines and horizontal 1024 columns are provided to be arranged on a substrate of about 1 cm 2  in square. Three CCD elements  11  are provided if the RGB signal specification is followed.  
         [0024]     In the above-described configuration, the image pickup apparatus M according to the invention outputs a picture signal as follows. That is, from the CCD element  11  configured for each of the R channel, G channel, and B channel, as an example, a charge signal of about 500 mV is outputted to the CDS circuit  12  as an example.  
         [0025]     At this time, on the basis of a value assigned from the ROM  21  or the like under a clock from the crystal signal generator  20  as an operating timing, a timing signal serving as a CCD drive pulse (vertical drive pulse) is supplied from the timing generator  18  to the CCD element  11 , providing an output timing of each pixel on the CCD element  11 . At the same time, a timing signal is supplied from the timing generator  18  to the V driver  19 . From the V driver  19 , the CD drive pulse of 1024 elements for one line is supplied to the CCD element  11 , followed by a vertical drive pulse which is a timing of moving to a next line. In accordance with these two timing signals, a detecting signal for each frame is supplied to the CDS circuit  12 .  
         [0026]     Here, as an example, in the case of the image pickup apparatus M having a frame rate of 60 fps, a CCD drive frequency of the CCD drive pulse is 33.53639 MHz, the number of horizontal period clocks is 1411 ck, and the number of vertical period lines is 396 lines.  
         [0027]     Next, the CDS circuit  12  samples a charge signal assigned from the CCD element  11  in response to a sampling hold pulse which is a timing signal from the timing generator  18 . The sampled charge signal is supplied to the signal processing unit  14  after a high frequency noise has been eliminated by the filter  13 . In the signal processing unit  14 , for example, color correction processing and gamma correction processing are applied for an image signal whose high frequency noise has been eliminated.  
         [0028]     Further, an output from the signal processing unit  14  is A/D converted in response to an A/D clock signal which is a timing signal from the timing generator  18 , and a digital signal is supplied to the digital signal processing unit  16 . In the digital signal processing unit  16 , scaling processing, IP conversion and the like are carried out with respect to the digital signal.  
         [0029]     The scaling processing used here denotes that the G channel is set to be shifted by a half pixel with respect to the R channel and B channel in the previously described CCD element  11  in order to a nominal resolution, and then, processing is carried out in order to recover the shifting in the digital signal processing unit  16  or the like, thereby obtaining a signal for 2048 pixels. The IP conversion used here denotes processing for changing an interlace image signal to a progressive image signal in order.  
         [0030]     Thereafter, this digital image signal is D/A converted in the D/A converter  17 , and the converted signal is outputted as an analog color image signal such as a composite video output signal.  
         [0000]     &lt;Changing Frame Rate&gt; 
         [0000]     (Frame Rate Change by Changing CCD Drive Frequency)  
         [0031]     In general, in an image pickup apparatus utilizing a CCD element or the like, a frame rate of 60 fps (frame per second) or 50 fps is often taken. Here, for example, in the image pickup apparatus M of case A as shown in  FIG. 3 , the CCD drive frequency is set to 33.53639 MHz, the number of horizontal period clocks is set to 1411 ck, and the number of vertical period lines is set to 396 lines in the case of the frame rate of 60, whereby the timing generator  18  is set and the circuit constants of the CDS circuit  12 , the A/D converter  15  and the like are determined.  
         [0032]     When an attempt is made to use this frame rate of 60 fps by converting it to 50 fps, in general, there can be proposed a method for replacing the oscillator  20  with the replacement oscillator, changing a CCD drive frequency is changed to 27.9378 MHz, and changing a circuit constant of a peripheral circuit in response to the change, as shown in case B of  FIGS. 3 and 4 .  
         [0033]     However, if this method is used, it becomes necessary to change parts of the oscillator  20 , the filter  13  and the like. Further, as indicated by the arrow in case B in  FIG. 5 , a rise timing of an A/D clock and a timing of a CCD output do not coincide with each other at an optimal value (phase shifting). That is, the rise timing of the A/D clock is required to coincide with each center of the CCD output as in the case A, in order to detect a stable signal. However, in case B, the rise timing of the A/D clock is obtained as a timing deviating from each center of the CCD output. Thus, there is an inconvenience that the value of the CCD output is not precisely conveyed to the rear stage.  
         [0000]     (Frame Rate Change by Changing the Number of Horizontal Period Clocks: 60 to 50)  
         [0034]     Now, description will be given for a method for changing a frame rate by changing the number of horizontal period clocks, as shown in  FIG. 6 , in the timing generator  18 . That is, when the frame rate of case C is 50 fps with respect to the frame rate of 60 fps in case A, the CCD drive frequency is maintained to be 33.53639 MHz without changing it, and the number of horizontal period clocks is changed to 1694 ck, thereby achieving frame rate change.  
         [0035]     This is clear from formula 1 shown in  FIG. 6 . That is, the frame rate is a value defined by: (Frame rate)=1/((CCD drive frequency)×(number of horizontal period clocks)×(number of vertical period lines)).  
         [0036]     Here, the timing generator  18  is composed of PLD, and the contents of the ROM  21  of the PLD is rewritten, thereby making it possible to change a horizontal drive stop period. Thus, there is no need for a circuit change.  
         [0037]     By using such a method, it becomes possible to convert a frame rate without changing a signal processing circuit such as an oscillator, an electric filter, and a high speed pulse (S/H pulse or A/D clock for CDS) phase.  
         [0000]     (Frame Rate Change by Changing the Number of Horizontal Period Clocks: 50 to 60)  
         [0038]     Further, it becomes possible to increase a frame rate by changing the number of horizontal period clocks. That is, as shown in the illustrative view of  FIG. 8 , it is possible to change a frame rate of 50 fps in case D to a frame rate of 60 fps in case E. In this case, it becomes possible to change the number of horizontal period clocks from 1411 ck to 1178 ck on the basis of formula 1 without changing the CCD drive frequency from 27.9378 MHz. At this time, as shown in  FIG. 9 , a horizontal drive stop period is changed from “305” to “70”, and the changed period meets formula 1.  
         [0039]     In this manner, in the image pickup apparatus M, it becomes possible to increase the frame rate of 50 to the frame rate of 60 merely by changing a constant or the like of the ROM  21  or the like, and there is no need for a work such as a change of the oscillator  20  or a change of the filter  13 .  
         [0040]     In addition, while the present embodiment has described a typical example of changing the frame rate 50 fps to 60 fps and vice versa, it is also possible to easily change a frame rate of one value to that of another value in a similar manner.  
         [0041]     As has been described above in detail, in the above-described image pickup apparatus, a frame rate is changed by increasing the number of horizontal period clocks without changing the CCD drive frequency.  
         [0042]     Consequently, for example, as compared with a case of changing the CCD drive frequency in order to change a frame rate, there is no need for a risk such as an oscillator frequency change or electric filter characteristic change and a phase change of a high speed pulse (S/H pulse or A/D clock for use in CDS) relevant to a total amount of circuit delay. Therefore, according to the present invention, there can be provided an image pickup apparatus using a solid-state image pickup device or the like capable of changing a frame rate by using a simplified method.  
         [0043]     According to a variety of embodiments described above, although one skilled in the art can achieve the present invention, it is obvious for one skilled in the art to conceive a variety of modified examples of these embodiments. In addition, even if one skilled in the art does not have any inventive ability, it is possible to apply the present invention to a variety of embodiments. Therefore, the invention covers a broad scope without departing from the disclosed principle and novel features, and is not limited to the above-described embodiments.