Abstract:
Reverse bias leakage testing may be used to determine the health of a vertical cavity surface emitting laser (VCSEL). When VCSELs are integrated on a die with other electronic devices such testing may damage the other electronic devices or be prohibited by circuits on the die designed to protect the electronics from being reverse biased. Accordingly, reverse bias testing may be facilitated by providing a second ground pad, separate from the die ground pad, specific to the VCSEL.

Description:
FIELD OF THE INVENTION  
       [0001]     Embodiments of the present invention relate to optics and, more particularly, to reverse bias testing of lasers.  
       BACKGROUND INFORMATION  
       [0002]     Lasers are used in a wide variety of applications. In particular, lasers are integral components in optical communication systems where a beam modulated with vast amounts of information may be communicated great distances at the speed of light over optical fibers. More recently, lasers have been investigated for communicating information short distances, such as chip-to-chip in computing environments.  
         [0003]     Of particular interest is the so-called vertical cavity surface emitting laser (VCSEL). As the name implies, this type of laser is a semiconductor micro-laser diode that emits light in a coherent beam orthogonal to the surface of a fabricated wafer. VCSELs are compact, relatively inexpensive to fabricate in mass quantities, and may offer advantages over more traditional edge emitting lasers. Edge emitting laser diodes emit coherent light parallel to the semiconductor junction layer. In contrast, VCSELs emit a coherent beam perpendicular to the boundaries between the semiconductor junction layers. Among other advantages, this may make it easier to couple the light beam to an optical fiber and may be more efficient.  
         [0004]      FIG. 1  shows a cross-sectional view of a basic VCSEL  100  along with its symbolic representation  100 ′. The VCSEL  100  may include an inactive layer  101 . Also shown is an active layer  102  comprising for example InGaAs, and optical confinement layers  104  comprising for example AlGaAs. These layers  102  and  104  may be sandwiched between a p-side semiconductor multi-layer reflector  106  (or p-side Distributed Bragg Reflector (DBR)), and an n-side semiconductor multi-layer reflector  108  (or n-side DBR). A resonator cavity is formed in the space between the p-DBR  106  and the n-DBR  108 . A current flowing between an anode  110  and a cathode  112  excites laser oscillation such that generated laser light  114  may be emitted through a plane of the substrate  116 . Of course other VCSEL configurations are possible.  
         [0005]     As similarly discussed in, for example Reedy et al., U.S. Pat. No. 6,583,445, VCSELs may be efficiently fabricated on wafers using standard microelectronic fabrication processes and, as a result, may be integrated on-board with other components to combine both the silicon electronic and the optoelectronic devices in a single unit or integrated circuit (IC). However, since high-density CMOS electronic circuits are typically made in silicon and high performance optoelectronic devices such as VCSELs are typically made with various other optically active materials (e.g. III-V materials), such as GaAs and ZnSe, combining the two may not be entirely straight forward.  
         [0006]     Attempts to integrate Si and III-V materials have been proposed. Heteroepitaxial growth for example involves the crystalline growth of one material on a dissimilar crystal substrate such as the heteroepitaxial growth of GaAs on silicon, and silicon on GaAs and has been done with some limited success.  
         [0007]     More practical approaches may involve fabricating the CMOS electronic chips and optoelectronic chips separately and then later combining the two such as by epoxy casting to form what are referred to as multi-chip modules, or MCMs. Flip-chip bonding may be another approach where a chip is flipped over and attached to a substrate or other chip by a solder joint to join two dissimilar chips into intimate electrical and mechanical contact with each other to form a single module. However, when joined testing of the laser may be difficult.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  is cutaway view of a vertical cavity surface emitting laser (VCSEL) diode and its symbolic representation;  
         [0009]      FIG. 2  is an integrated circuit (IC) module including a separate VCSEL ground for reverse bias testing according to one embodiment;  
         [0010]      FIG. 3  is a plan view of a parallel optics module according to one embodiment of the invention;  
         [0011]      FIG. 4  is a parallel optics module according to one embodiment of the invention; and  
         [0012]      FIG. 5  is a router including an optics module according to one embodiment of the invention.  
     
    
     DETAILED DESCRIPTION  
       [0013]     Like many electronic and optoelectronic components, VCSELs are inherently prone to damage from electrostatic discharge (ESD). An ESD level of just 200 Volts can destroy a VCSEL. The device may not fail immediately, but after some time. This time could be a year or more depending on the operating conditions. Unfortunately, after an optoelectronic device has been integrated on-board with other silicon electronic devices, it may be difficult to test the VCSEL for damage such as that caused by an ESD event.  
         [0014]     One test to determine if ESD damage has occurred is by doing a measure of the reverse bias leakage current of the VCSEL. If the leakage current is too high, this may signify that the p-n junction in the VCSEL has sustained some damage. Integrated designs where the VCSEL anode  110  and cathode  112  have been connected to an IC have not been able to measure this leakage current. A reason for this is that ESD diodes designed into the IC prevent reverse biasing of the IC. Therefore the VCSEL, now part of the IC, also cannot be reverse biased.  
         [0015]     Referring now to  FIG. 2 , there is shown a block diagram of a VCSEL  200  integrated with an IC module  202  according to an embodiment of the invention. Other components  204  which may include MOS, CMOS or bi-polar devices may be integral to the IC module  202 . In one embodiment, one of these other components may include a VCSEL driver  206  comprising the circuitry for operating the VCSEL  200 . The VSCEL  200  may be integrally formed with the IC module  202 , such as by heteroepitaxial growth, or may comprise a separate die that is epoxy bonded, flip-chip bonded, wire bonded or otherwise mechanically and electrically attached to the IC module  202 .  
         [0016]     The IC module  202  comprises an input voltage source (Vcc)  208  as well as an IC ground  210 . As may be typical, during normal operation of the IC  202 , Vcc  208  supplies the voltage to operate the various components including, in this example, the VCSEL  200 , the VCSEL driver  206 , as well as any other components  204  that may be present. Similarly, the IC ground  210  provides electrical grounding for the VSCEL driver and any other components  204 .  
         [0017]     According to one embodiment of the invention, the VCSEL  200  may have its anode  212  share Vcc  208  with the IC  202 , however, the VCSEL cathode  214  may include its own ground  216 , separate from the IC ground  210 . Thus, the VCSEL cathode  214  may be electrically separated from the rest of the module package  202 . This VCSEL ground  216  may comprises a pad or lead which may be accessible from outside the IC module  202  to be used for reverse bias testing of the VSCEL  200 , such as to detect ESD damage. As shown, a conductive element such as, for example, a diode  226 , or alternatively a resistor  228  may be provided to provide a conduction path between the anode  212  of the VCSEL  200  and the Vcc pad  208 .  
         [0018]     A reverse bias test may be performed using a test voltage source  218 . During such a test, the VCSEL ground  216  may be supplied with a voltage, for example 5-10 Volts, and the Vcc pad  208  may be grounded  220 . Of course the pad for Vcc  208  is disconnected from any voltage source during this test. Leakage current through the VCSEL  200  may be detected by a current meter  222  in the test path  224 . For a typical VCSEL  200 , a leakage current as small as a nano-amp may signify VCSEL  200  damage.  
         [0019]      FIG. 2  shows a single VCSEL  200  integrated with the IC module  202 . However, in one embodiment of the invention, the IC module  202  may comprise a plurality of VCSELs, such as a single die comprising an array of VCSELs or an array of individual VCSEL dies.  
         [0020]      FIG. 3  is illustrative of a parallel optics module  400 , such as that disclosed in co-pending application Ser. No 10/______ (attorney docket P20233). Referring to  FIG. 3 , an embodiment of a parallel optics module  400  is shown. The parallel optics module  400  may include singulated VCSEL dies  402  arranged in a two-dimensional array. The singulated VCSEL dies  402  are coupled to a substrate  410  which may contain other components such as VCSEL drivers  403  and transmitter circuitry  401 . It will be understood the two-dimensional die  402  array is not limited to the arrangement shown in  FIG. 3 . In one embodiment, each of the singulated VCSEL dies  402  may share Vcc  409  with the IC, but each may have its own accessible ground  405  separate from the IC ground  407  to enable reverse bias testing.  
         [0021]     Referring to  FIG. 4 , an embodiment of a parallel optics module  500  coupled to a printed circuit board (PCB)  512  is shown. Parallel optics module  500  includes VCSEL dies with separate grounds as previously described. Parallel optics module  500  may include an optical transmitter, an optical receiver, or an optical transceiver.  
         [0022]     Parallel optics module  500  includes an electrical connector  504  to couple module  500  to PCB  512 . Electrical connector  504  may include a ball grid array (BGA), a pluggable pin array, a surface mount connector, or the like.  
         [0023]     Parallel optics module  500  may include an optical port  506 . In one embodiment, optical port  506  may include an optical port to receive a Multi-Fiber Push On (MPO) connector  508 . MPO connector  508  may be coupled to an optical fiber ribbon  510 . In one embodiment, the optical fiber ribbon  510  includes two or more plastic optical fibers.  
         [0024]     In one embodiment, the singulated dies of parallel optics module  500  may emit light at different wavelengths for use in Wavelength Division Multiplexing (WDM). In one embodiment, parallel optics module  500  may transmit and/or receive optical signals at approximately 850 nanometers (nm). In another embodiment, parallel optics module  500  may operate with optical signals having a transmission data rate of approximately 3-4 Gigabits per second (Gb/s) per channel. In yet another embodiment, optical signals transmitted and received by parallel optics module  500  may travel up to a few hundred meters. It will be understood that embodiments of the invention are not limited to the optical signal characteristics described herein.  
         [0025]      FIG. 5  illustrates an embodiment of a router  600 . Router  600  includes a parallel optics module  606  included singulated dies as described herein. In another embodiment, router  600  may be a switch, or other similar network element. In an alternative embodiment, parallel optics module  606  may be used in a computer system, such as a server.  
         [0026]     Parallel optics module  606  may be coupled to a processor  608  and storage  610  via a bus  612 . In one embodiment, storage  610  has stored instructions executable by processor  608  to operate router  600 .  
         [0027]     Router  600  includes input ports  602  and output ports  604 . In one embodiment, router  600  receives optical signals at input ports  602 . The optical signals are converted to electrical signals by parallel optics module  606 . Parallel optics module  606  may also convert electrical signals to optical signals and then the optical signals are sent from router  600  via output ports  604 .  
         [0028]     The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible, as those skilled in the relevant art will recognize. These modifications can be made to embodiments of the invention in light of the above detailed description.  
         [0029]     The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the following claims are to be construed in accordance with established doctrines of claim interpretation.