Abstract:
Contact openings are formed in a dielectric layer overlying conductive paths where the openings and the paths have essentially the same dimension or width, thus allowing for minimized area contacts. Process buffering regions are formed adjacent the conductive paths to provide additional landing area for the contact openings without exposing the sidewall of the conductive path. In some embodiments the contact openings and methods for forming thereof provide electrical coupling between metal layers of a multilevel metal structure or for electrically coupling polysilicon layers and metal layers. In some embodiments the contact opening and methods for forming thereof provide for direct contact to a gate electrode.

Description:
BACKGROUND  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to semiconductor integrated circuits (ICs) and methods of fabrication thereof, and more specifically to a semiconductor IC with minimized dimensions for contact openings and methods for the fabrication of thereof.  
           [0003]    2. Related Art  
           [0004]    The ability to scale the size of semiconductor device geometries downward is key to meeting the demands for integrated circuits having increased functionality and performance while maintaining low fabrication costs. The industry&#39;s ability to meet this demand to date has very much been due to improvements in the optical resolution of photolithography equipment and associated processes. However, the full impact of these improvements is often not realized, as process buffering regions are needed to account for registration and other process tolerances. This is particularly true for contact openings.  
           [0005]    For example, in the manner of the prior art, FIG. 1A depicts a plan view of a first contact opening  40  formed overlying a first conductive trace  30 . Typically, both first trace  30  and first contact  40  are formed having a minimum design dimension. Thus, first trace  30  has a width  50  and first contact  40  a width  52  that are essentially equal. However, to ensure that first contact  40  overlies only first trace  30 , contact  40  is positioned within a contact region  34 , an expanded region of trace  30 , that has a dimension  54 , larger than widths  50  and  52 . The size difference between width  54  and width  50  is the amount of process buffering required to form first contact  40  entirely overlying conductive trace  30 . Therefore despite less than perfect alignment of first opening  40  to first trace  30 , as depicted, contact opening  40  is fully within contact region  34 . Where a second conductive trace  32  does not provide any process buffering region, that is no region analogous to expanded region  34 , the less than perfect alignment of a second contact  42  to second trace  32  results in second contact  42  being positioned having a portion of second contact  42  off second trace  34 , as depicted. As known, such mis-positioning can result in both yield and reliability problems. Thus to avoid these problems, prior art processing provides process buffering regions.  
           [0006]    Expanded process buffering regions, such as contact region  34 , are not the only forms of process buffering regions employed in the prior art. Turning now to FIG. 1B, a plan view of a metal on silicon (MOS) transistor  90  is shown. An active area  80  has source and drain (S/D) regions  62  formed therein. A gate electrode  70  is disposed adjacent to and between S/D regions  62  and overlying a channel region (not shown) in active area  80  bordered by S/D regions  62 . Electrical contact to gate electrode  70  is made within a process buffering region  74  extending outward from area  80 , as depicted. As known, an extended process buffering region, such as region  74 , is often employed in prior art MOS transistors for providing electrical contact to gate electrode  70 . Use of an expanded buffering region, such as region  34  of FIG. 1A, is problematic as such an expanded region increases gate length. As known, an increased gate length will result in a change in the electrical characteristics of transistor  90  from that of a transistor having the nominal gate length. On the other hand, failure to use any process buffering region, as shown for second contact  42  in FIG. 1A, can result in lowered yield and reliability due to electrical shorting of gate  70  to S/D regions  60 . Therefore the-prior art process and MOS transistors formed thereby, require that an extension of gate  70  be employed to form process buffering region  74  and that gate contact  72  is disposed within extended region  74 . Hence it can be seen that contacts formed in the manner of the prior art require either expanded process buffering regions or extended process buffering regions. And that these buffering regions require substrate surface area in excess of that required by the functional structures themselves, for example trace  32  and contact  42  of FIG. 1A. Thus, processing in the manner of the prior art does not allow for the full realization of the benefits that downward scaling of device structures can provide.  
           [0007]    Thus it would be advantageous to have IC structures and devices that realize the full benefit of scaling the size of such structures and devices downward, and the methods of manufacture thereof. It would also be advantageous to have methods for forming such fully realized size scaled devices and structures that do not require additional photomasking processes. In addition it would be advantageous for such methods of manufacture to be broadly applicable, thus providing for the manufacture of both MOS and Bipolar devices as well as any combination of such devices thereof that fully realize such size scaling. Finally, it would be advantageous to manufacture such fully realized size scaled devices in a cost effective manner and where devices so manufactured have yield and reliability at least equal to that of the prior art.  
         SUMMARY  
         [0008]    In accordance with the present invention, methods for forming minimized area contact structures, and the structures and IC&#39;s formed thereby, are provided. In some embodiments of the present invention, MOS integrated circuits and circuit elements are formed. In some embodiments of the present invention, bipolar integrated circuits and circuit elements are formed and in some embodiments, both MOS and bipolar circuit elements and circuit elements are formed.  
           [0009]    In accordance with the present invention some embodiments employ a non-conductive material to form process buffering regions adjacent conductive traces. In some embodiments the non-conductive material employed is a dielectric material such as silicon oxide, silicon nitride or a combination of silicon oxide and silicon nitride. In some embodiments both silicon oxide and silicon nitride materials are employed. In some embodiments of the present invention the dielectric material is formed as a layer overlying a semiconductor substrate and selectively etched to form process buffering regions or process buffering spacers adjacent sidewalls of the conductive traces formed on the substrate. In some embodiments process buffering spacers are formed using more than one layer of dielectric material.  
           [0010]    Embodiments in accordance with the present invention typically employ a dielectric layer disposed over the process buffering regions. In some embodiments, the material of the process buffering regions is selectively etchable with respect to the dielectric layer. In some embodiments the dielectric layer is formed of more than one layer of dielectric material, each layer being selectively etchable with respect to an underlying layer. In some embodiments of the present invention contact holes or vias are formed by etching portions of the dielectric layer left exposed after deposition and patterning of a photomasking layer to define such portions. In embodiments where a conductive trace is a gate electrode, process buffering regions formed in accordance with the present invention allow direct contact to be made to the gate electrode, if desired. Finally, in some embodiments, the process buffering regions formed, prevent exposure of sidewalls of the conductive traces. In this manner, embodiments in accordance with the present invention avoid the need for formation of either expanded or extended process buffering regions, thus enabling minimized area contacts. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. For ease of understanding and simplicity, where elements are common between illustrations, common numbering of those elements is employed between illustrations.  
         [0012]    [0012]FIGS. 1A and 1B are plan views of conductive traces and contact regions formed in the manner of the prior art;  
         [0013]    FIGS.  2 A- 2 E are cross-sectional representations of stages in the formation of contact regions on conductive traces in accordance with an embodiment of the present invention; and  
         [0014]    FIGS.  3 A- 3 B are a plan and cross-sectional representation, respectively, of contact regions on a gate electrode in accordance with another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0015]    As embodiments of the present invention are described with reference to the drawings, various modifications or adaptations of the specific methods and or structures may become apparent to those skilled in the art. All such modifications, adaptations or variations that rely upon the teachings of the present invention, and through which these teachings have advanced the art, are considered to be within the spirit and scope of the present invention. For example, in some embodiments of the present invention, process buffering spacers are formed after removal of sidewall spacers used for, among other things, formation of silicide regions.  
         [0016]    FIGS.  2 A- 2 E depict a series of stages in the fabrication of an embodiment in accordance with the present invention. As shown, in each of FIGS. 2D and 2E, a first portion and a second portion of the embodiment are depicted. The first portion, on the left, illustrates an embodiment of the invention having a slight mis-alignment, as was seen with respect to the prior art conductive trace  30  and contact  40  in FIG. 1A. The second portion, on the right, illustrates an embodiment of the invention having less than perfect alignment as was seen with respect to the prior art conductive trace  32  and contact  42 , also in FIG. 1A.  
         [0017]    Turning to FIG. 2A, a semiconductor substrate or wafer  100  is shown having a conductive layer  200  disposed thereon. While wafer  100  is depicted as having a minimum of complexity, other types of substrates or wafers may be advantageously employed. For example, substrate  100  can be an N-type or P-type substrate, or can be an N-type or P-type substrate encompassing N and/or P-type well regions (not shown) and/or an epitaxial layer (not shown). Alternatively, wafer  100  can encompass a silicon on insulator (SOI) structure, or any other appropriate semiconductor substrate material or structure. In addition, in some embodiments in accordance with the present invention, substrate  100  encompasses a dielectric layer (not shown) formed on an upper surface and disposed underlying layer  200 . Two masking portions  300  and  320  are depicted overlying predetermined portions of conductive layer  200 . Typically, masking portions  300  and  320  are a photoresist material formed by well known photolithographic processes, although other appropriate materials can be employed in addition to or in place of photoresist.  
         [0018]    Conductive layer  200  is any of the commonly employed conductive materials or combination of such materials used to form conductive paths or traces for IC&#39;s. For example, in some embodiments layer  200  can encompass aluminum, copper or an alloy of aluminum and/or copper. Layer  200  can also encompass more than one layer of conductive material, for example, a conductive barrier layer such as tungsten or a tungsten alloy overlaid with an aluminum layer. In some embodiments layer  200  can also encompass a polysilicon material, an amorphous silicon material or any combination of amorphous and polysilicon doped with an N or P-type dopant. In some embodiments of the present invention, where layer  200  is a polysilicon layer formed adjacent substrate  100 , layer  200  is a first conductive layer of an IC having multiple conductive layers. In some embodiments, where layer  200  is an aluminum alloy layer, layer  200  is one conductive metal layer of an IC having a multilayer metal structure. In some embodiments, layer  200  is employed to form a silicon or metal gate electrode (not shown). Therefore it will be understood that the representation of layer  200  in FIG. 2B and the structures of FIGS.  2 A- 2 E are all depicted in their simplest form for illustrative purposes only, and that embodiments of the present invention have a wide range of specific application.  
         [0019]    Referring to FIG. 2B, conductive layer  200  (FIG. 2A) is etched to form conductive paths or traces  210  and  220 , and masking portions  300  and  320  (FIG. 2A) is subsequently removed. After removal of portions  300  and  320 , an essentially conformal layer  400  of a dielectric material is formed overlying substrate  100  and conductive traces  210  and  220 . In some embodiments of the present invention, layer  400  encompasses silicon oxide, silicon nitride or any combination of silicon oxide and silicon nitride, although other appropriate materials can be employed.  
         [0020]    Turning now to FIG. 2C, the structure of FIG. 2B is shown subsequent to forming process buffering areas or spacers  410 . As depicted, process buffering spacers  410  are formed adjacent sidewalls of conductive traces  210  and  220 , and have a predetermined width  415 . It will be understood that width  415  defines the amount of process buffering that an embodiment in accordance with the present invention provides. Thus, with knowledge of the process capabilities of the various processes for which such process buffering is needed, width  415  is determined to be the sum of the buffering required for each of the various processes. For example, where a photolithography process requires 0.1 micron (μm) of buffering and is followed by an etch process also requiring 0.1 μm of process buffering, width  415  is the sum of these two processes, 0.2 μm. It will be understood that while the magnitude of width  415  needed by a specific application is determined by the amount of process buffering required, width  415  is set by the thickness of layer  400  (FIG. 2B) as formed. Thus, for a 0.2 μm width  415 , layer  400  is formed having a thickness of at least 0.2 μm. Where more or less process buffering is required, layer  400  is formed with a greater or lesser thickness, respectively. Thus the thickness of layer  400 , as deposited, will vary in accordance with the nature of the specific application for which an embodiment of the present invention is employed.  
         [0021]    Typically, process buffering areas  410  are formed using an anisotropic etch process appropriate for the material from which layer  400  (FIG. 2B) is formed. As one having ordinary skill in the art will know, the specific etch process selected will be selective to the material employed for conductive traces  210  and  220  as well as any underlying dielectric layer (not shown). In this manner, spacers  410  are formed adjacent sidewalls of each trace  210  and  220  while an upper surface  215  and  225  of each trace, respectively, is exposed. For example, where conductive traces  210  and  220  are doped polysilicon traces overlying a substrate  100  having an upper surface formed of a silicon oxide dielectric layer (not shown) and layer  400  (FIG. 2B) is selected to be a silicon nitride material, process buffering spacers  410  are formed employing an etch process that preferentially etches silicon nitride. For example, a reactive ion etch (RIE) process employing a mixture of CHF 3 /O 2  and C 2 HF 5  at an appropriate power and pressure has been found to be effective, although other etch process can also be employed. It will be understood that the etch process of this embodiment of the present invention is only provided for illustrative purposes and other etch processes can be employed where appropriate.  
         [0022]    Turning now to FIG. 2D, as previously mentioned, a first and second portion of the embodiment of FIG. 2C, in accordance with the present invention, is shown. In each portion, a dielectric layer  500  is formed overlying each conductive trace  210  and  220 , respectively, and underlying substrate  100 . In some embodiments, one of the commonly known planarization processes is employed to planarize layer  500 , as is depicted. For example, in some embodiments layer  500  is planarized using a chemical mechanical planarization (CMP) process, while in some embodiments a sacrificial layer/etch-back process is employed.  
         [0023]    A masking layer  600  is disposed on layer  500  and a first contact area  610  is formed in layer  600  to expose a portion of layer  500  overlying a portion of conductive trace  210  and a portion of one process buffering area  410 . Thus contact area  610  is shown aligned to trace  210  in a manner analogous to the alignment of contact  40  to trace  30  depicted in FIG. 1A. In the second portion of the embodiment of FIG. 2D, a second contact area  620  is formed in layer  600  to expose another portion of layer  500  overlying a portion of conductive trace  220 , a portion of one process buffering area  410  and extending to expose some of layer  500  beyond that process buffering area  410 . The alignment of contact area  620  is in a manner analogous to the alignment of contact  42  to trace  32  depicted in FIG. 1B. It will be understood that the alignment of areas  610  and  620  are shown in the manner of the alignment of contact  40  and  42  for illustrative purposes only. Thus these depictions of FIG. 2D serve to highlight, as will be discussed, the advantages of embodiments of the present invention as compared to the previously illustrated prior art structures.  
         [0024]    [0024]FIG. 2E is a cross-sectional view of the embodiments of FIG. 2D subsequent to etching layer  500  to form a first contact  510 , a second contact  520  and removal of masking layer  600 . As depicted, first contact  510  exposes surface  215  of conductive trace  210 . In addition, a portion of process buffering area  410  adjacent trace  210  is exposed. Thus the slight mis-alignment of contact area  610  (FIG. 2D) is accommodated by process buffering spacer  410  and no expanded contact region as seen in FIG. 1A is required. Second contact  520  exposes surface  225  of conductive trace  220 , a portion of buffering spacer  410  and an edge  430  of buffering spacer  410 . Thus, it will be understood that process buffering spacer  410  advantageously protects edge  230  of conductive trace  220  from being exposed, despite the misalignment of contact  520 .  
         [0025]    As known for the prior art structure of FIG. 1B, where contact  42  is formed over an aluminum (Al) trace  32 , any exposed edge of Al trace  32  can lead to the formation aluminum fluoride (AlF 3 ) and/or “volcano” defects where a tungsten (W) plug (not shown) is formed to subsequently fill contact  42 . For embodiments of the present invention, edge  230  is not exposed, but rather protected by buffering spacer  410 . Thus embodiments in accordance with the present invention advantageously provide protection against such yield and reliability as AlF 3  and “volcano” defects.  
         [0026]    In addition, where trace  220  is a polysilicon material, often a metal silicide is formed at surface  225  to enhance electrical coupling by lowering the resistance of the surface. As known, where edge  230  is exposed during a silicide process, metal silicide (not shown) can undesirably form at edge  230  providing for unplanned and therefore undesirable electrical coupling to other closely spaced conductive regions (not shown). Therefore, embodiments in accordance with the present invention advantageously provide protection against such undesirable couplings.  
         [0027]    It will also be understood, that the advantages of embodiments of the present invention, as described herein, are provided without use of expanded contact areas or extended contact areas as described with regard to the prior art (See FIGS. 1A and 1B). Therefore, embodiments in accordance with the present invention do not require the additional area required by these prior art contact areas, and minimized contact areas are provided.  
         [0028]    Turning now to FIG. 3A, a plan view of an MOS transistor  900  formed in accordance with an embodiment of the present invention is depicted. An active area  800  is defined by an isolation region  700  and has S/D regions  820  formed therein. The nature of embodiments of the present invention make them applicable to any type of MOS transistor  900 . Thus the benefits and advantages of the present invention are equally applicable to an NPN or a PNP transistor  900 . In addition, the benefits and advantages of the present invention are equally applicable to MOS transistors formed having silicon gates or metal gates. In addition, as the characteristics of S/D regions  820 , isolation region  700  and other transistor structures depicted in FIGS. 3A and 3B are well known and additionally encompass well known and commonly practiced methods, for simplicity and ease of understanding, descriptions of these characteristics and methods will be omitted. A gate electrode  840  is disposed adjacent to and between S/D regions  820  and overlying a channel region (not shown) defined by S/D regions  820  in active area  800 . While gate electrode  840  is typically formed from a polysilicon material, other appropriate materials can be used. For example, gate electrode  840  can be formed using amorphous silicon which is converted in-situ to polysilicon in a manner known to one of ordinary skill in the art. In addition, in some embodiments in accordance with the present invention, gate electrode  840  is a metal such as tungsten (W), molybdenum (Mo) or tantalum (Ta). For example, in some embodiments a W gate electrode  840  is advantageously used. Alternatively, in some embodiments it is advantageous to employ a Mo or Ta gate electrode  840 . Gate process buffering areas  810  are depicted adjacent edges of gate electrode  840 . Buffering areas  810  are formed of any of the materials, and in the manner described with respect to FIGS. 2B and 2C. S/D contacts  920  are formed overlying and within S/D regions  820 . As known, gate contact  940  and S/D contacts  920  are formed in a dielectric layer not visible in a plan view. It will be understood, that as transistor  900  is formed in accordance with embodiments of the present invention, no extended contact area as seen in FIG. 1B is needed.  
         [0029]    [0029]FIG. 3B is a cross-sectional view of transistor  900  of FIG. 3A taken through section line BB. Thus active area  800  is shown defined by isolation region  700 . Gate electrode  840  with adjacent gate buffering areas  810  is shown overlying a gate dielectric  730  and channel region  830  which in turn is seen to be adjacent S/D regions  820 . In embodiments of the present invention employing a silicon gate electrode  840 , gate dielectric  730  is typically formed of a silicon oxide material, although other appropriate materials can be used. In embodiments where gate electrode  840  is a metal material, for example tungsten (W), a Ta 2 O 5  gate dielectric layer  730  can be advantageously used. In some embodiments employing a Mo or Ta gate electrode  840  a silicon oxide gate dielectric layer  730  having an intervening barrier layer such as titanium/titanium nitride (not shown) is employed. The cross-sectional view of FIG. 3A illustrates the formation of gate contact  940  and S/D contacts  920  in dielectric layer  720  as previously mentioned. It will be understood that the In addition, process buffering areas  810  are formed of materials and by the methods previously described for embodiments of buffering areas  410  with regard to FIGS. 2B and 2C. Therefore, these materials and methods are understood to be applicable to the formation of gate process buffering areas or spacers  810  as well.  
         [0030]    In a manner analogous to the first portion of FIG. 2E, it is seen that gate contact  940  is formed exposing surface  845  of gate electrode  840 . In embodiments of the present invention where gate electrode  840  encompasses a silicon material, it is advantageous to form a metal silicide contact region (not shown) at surface  845 . As known, such metal silicide regions serve to lower the contact resistance to gate electrode  840 . While in accordance with the present invention, any of the well known processes for forming such metal silicide regions can be employed, it is a particular benefit of the present invention that process buffering regions  810  limit any metal silicide formation to surface  845 . Thus gate electrode edge  842  is free of such metal silicide formation. In embodiments of the present invention where gate electrode  840  encompasses a metal material, no metal silicide region is formed at surface  845 .  
         [0031]    It will also be understood, that the advantages of embodiments of the present invention previously described with respect to FIG. 2E are also provided by the embodiment of FIGS. 3A and 3B. Thus it will be realized that embodiments of the present invention have been described that provide for semiconductor integrated circuits, and methods thereof, that employ minimized area contacts. In addition, it will be realized that embodiments in accordance with the present invention do not require the additional area required by these prior art expanded or extended contact areas. Additionally, it will realized that the embodiments of the present invention described herein do not require any photolithographic processing for their benefits to be realized. It will also be realized that embodiments of the present invention are broadly applicable to a wide range of semiconductor structures and devices. And that while only an MOS transistor has been specifically described, that the process buffering provided by these embodiments is applicable to MOS ICs as well as bipolar ICs and ICs that combine MOS and bipolar device structures. For example, process buffering areas analogous to those previously described herein can be utilized to form minimized area contacts to bipolar base, collector or emitter regions. Thus, the method of formation and structure of process buffering areas for the polysilicon emitter region of a bipolar transistor are readily determined from the descriptions herein. It will also be realized that embodiments of the present invention provide protection to sidewalls of conductive traces, for example gate electrodes. Thus where metal silicide regions are formed, this protection serves to prevent formation of metal silicide on such sidewalls. Finally, it will be realized that embodiments of the present invention are cost effect structures that offer yield and reliability enhancement.