Abstract:
An address control apparatus for a semiconductor memory device using a bank address, and more particularly an address control apparatus for a semiconductor memory device using a bank address being concurrently used as a row address in accordance with an architectural bank in realizing various dynamic random access memory (DRAM) macro sets more than 2M˜64M, utilizing a memory compiler in embedded-DRAM, resulting in reduced design time for the macro sets with a minimum of circuit elements.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention generally relates to an address control apparatus for a semiconductor memory device using a bank address, and more specifically to an address control apparatus which can be applied to various DRAM macro sets more than 2M˜64M, as well as reducing the time required for designing the macro sets.  
         BACKGROUND OF THE INVENTION  
         [0002]    In general, address buffers in a DRAM device perform to receive address signals. Each address signal(e.g., A 0  through An) is independently assigned to one address buffer and one address bus line. And, each address signal provided through each address buffer is stored in an address register in synchronization with an internal clock.  
           [0003]    Meanwhile, it is generally known in the address buffers that the address signals are inputted thereto synchronously with row active, read, or write commands. In cases where the address signals are performing a multiplexing operation, the address signals may be used for a row address or a column address in accordance with the kinds of commands. In cases without the multiplex procedure, i.e., de-multiplexing, the address signals are classified into row and column address signals at the time they are incoming, and then provided to the address buffers in response to activation of row and column signals. At this time, the row and column address signals are converted into pre-decoded signals by row and column pre-decoders, respectively.  
           [0004]    [0004]FIG. 1 is a block diagram of the conventional demultiplexing address control apparatus for receiving the row and column address signals which are separately input thereto.  
           [0005]    Referring to FIG. 1, the conventional address control unit includes a row address buffer  10 , a column address buffer  30 , and a bank address buffer  50 , theses three buffers being associated with their own signal input paths.  
           [0006]    First, the row address buffer  10  receives and buffers external row address signals RAN&lt;0:10&gt;, and then generates internal row address signals RA&lt;0:10&gt; and /RA&lt;0:10&gt;. The internal row address signals RA&lt;0:10&gt; and /RA&lt;0:10&gt; are applied to a row pre-decoder  20  and converted into pre-decoded row address signals. At that time, first refresh control unit  15  applies control signals RCNT&lt;0:10&gt; and /RCNT&lt;0:10&gt; to the row pre-decoder  20  in response to clock signal CLK in order to control a refresh operation.  
           [0007]    The column address buffer  30  receives and buffers external column address signals CAN&lt;0:4&gt;, and then generates internal column address signals CA&lt;0:4&gt; and /CA&lt;0:4&gt;. The internal column address signals CA&lt;0:4&gt; and /CA&lt;0:4&gt; are applied to a column decoder  40  and converted into decoded column address signals.  
           [0008]    The bank address buffer  50  receives and buffers external bank address signals BAN&lt;0:1&gt;, and then generates internal bank address signals BA&lt;0:1&gt; and /BA&lt;0:1&gt;. The internal bank address signals BA&lt;0:1&gt; and /BA&lt;0:1&gt; are applied to a bank control unit  60 . Here, the bank address signals serve to activate a selected bank in multi-bank DRAM.  
           [0009]    However, according to the conventional address control apparatus, since the row address buffer  10 , the column address buffer  30 , and the bank address buffer  50  respectively should have their own signal input paths to buffer the address signals, a time required for designing a DRAM macro set inevitably increases. Such a long time for design makes it difficult to completely fabricate the DRAM macro set in a given turn-around-time (TAT).  
           [0010]    As a result, it would be difficult to design DRAM macro sets having various memory densities of 2M through 64M because of the numerous signal paths for the buffers.  
         SUMMARY OF THE INVENTION  
         [0011]    It is, therefore, an object of the present invention to utilize a bank address as a row address in accordance with a bank architecture.  
           [0012]    In order to attain the above object, according to an aspect of the present invention, it is an object of the present invention to provide an address control apparatus for a semiconductor memory device using a bank address, the address control unit including a row address buffer for buffering and generating a row address signal, a bank address buffer for buffering and generating a bank address signal, a bank control unit for activating a bank selected in response to the buffered bank address signal provided from the bank address buffer, an address control unit for converting the buffered bank address signal provided from the bank address buffer into an additional row address signal, and then generating, and a row pre-decoder for pre-decoding the buffered row address signal provided from the row address buffer and the additional row address signal converted in the address control unit, and then generating a composite address signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:  
         [0014]    [0014]FIG. 1 is a block diagram of an address control apparatus of a semiconductor memory device according to the conventional art;  
         [0015]    [0015]FIG. 2 is a block diagram of an address control apparatus of a semiconductor memory device using a bank address according to a preferred embodiment of the present invention;  
         [0016]    [0016]FIG. 3 is a circuit diagram of a bank address latch according to the preferred embodiment of the present invention; and  
         [0017]    [0017]FIG. 4 is a circuit diagram of a row pre-decoder according to the preferred embodiment of the present invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0018]    [0018]FIG. 2 depicts an address control apparatus for a semiconductor memory device according to a preferred embodiment of the present invention.  
         [0019]    The address control apparatus according to the present invention includes a bank address latch  510 , and a second refresh control unit  520 , which are not found in the conventional address control apparatus. Also, contrary to the conventional one, the inventive address control apparatus has a row pre-decoder  300  which receives the band address as well as the row address.  
         [0020]    As shown in FIG. 2, a row address buffer  100  receives and buffers external row address signals RAN&lt;0:10&gt;, and then generates internal row address signals RA&lt;0:10&gt; and /RA&lt;0:10&gt; to the row pre-decoder  300 . A first refresh control unit  250  applies control signals RCNT&lt;0:10&gt; and /RCNT&lt;0:10&gt; for controlling refresh to the row pre-decoder  300  in synchronization with clock signals CLK and /CLK. A bank address buffer  200  receives and buffers external bank address signals BAN&lt;0:1&gt;, and then generates internal bank address signals BA&lt;0:1&gt; and /BA&lt;0:1&gt; to a bank control unit  400 . Here, the bank address signals (e.g., BA 0 ˜BA 1 ) are address signals to determine which bank is set to be activated in multi-bank DRAM. The bank control unit  400  receives the bank address signals BA&lt;0:1&gt; and /BA&lt;0:1&gt; provided from the bank address buffer  200 , and generates a signal for activating a selected bank, and a precharge signal.  
         [0021]    In the present invention, the bank address is used in parallel with the row address in accordance with the bank architecture, considering the layout and construction. Thus, in order to utilize the bank address signal in parallel with additional row address signals (e.g., RAN&lt;11:12&gt;), the bank address latch  510  which latches the bank address signal provided from the bank address buffer  200  is employed.  
         [0022]    For instance, in the case where row address signals A 0 ˜A 12  are provided and the bank address signal is used in parallel with the row address signal, the address signals A 0 ˜A 10  are used for the row address signals, and the additional row address signals of A 11  and A 12  are used for the bank address signals.  
         [0023]    In other words, the external row address signals RAN&lt;0:10&gt; are applied through the row address buffer  100  to the row pre-decoder  300 , and the additional row address signals are applied through the bank address buffer  200  to the row pre-decoder  300 .  
         [0024]    For the purpose of utilizing the external bank address signals BAN&lt;0:1&gt; as the additional row address signal, the internal bank address signals BA&lt;0:1&gt; and /BA&lt;0:1&gt; provided from the bank address buffer  200  are applied to the bank address latch  510  of an address control unit  500 .  
         [0025]    The bank address latch  510  latches the internal bank address signals BA&lt;0:1&gt; and /BA&lt;0:1&gt;, and generates the additional row address signals RA&lt;11:12&gt; and /RA&lt;11:12&gt;. The additional row address signals RA&lt;11:12&gt; and /RA&lt;11:12&gt; are applied to the row pre-decoder  300  and converted into decoded row address signals.  
         [0026]    Further, the second refresh control unit  520  of the address control unit  500  applies control signals RCNT&lt;11:12&gt; and /RCNT&lt;11:12&gt; to the row pre-decoder  300  in response to the clock signals CLK and /CLK in order to refresh the row address signals RA&lt;11:12&gt; and /RA&lt;11:12&gt; provided in the row pre-decoder  300  through the bank address latch  510 . The row address signals RA&lt;0:12&gt; and /RA&lt;0:12&gt; provided in the row pre-decoder  300  are converted to pre-decoded row address signals AXBC&lt;0:3&gt;.  
         [0027]    The bank address buffer  200  serves to select a building block below a unit of basic memory block for tiling a memory compiler. Thus, the external row address signals RAN&lt;0:1&gt;, RAN&lt;9:10&gt; being used for selecting word line driving signals, and a memory core cell block are utilized for bank address latch control signals and fast control signals.  
         [0028]    The embodiment of the invention is a case of tiling the building block of a memory compiler 4M core cell, and the building block is selected by allowing the bank address buffer  200  to generate the row address signal.  
         [0029]    In the case of tiling a building block of 2M core cell, the bank address latch  510  is added to each of three address buffers of the bank address signals BAN&lt;0:2&gt;.  
         [0030]    [0030]FIG. 3 is a circuit diagram of the bank address latch  510  using the bank address.  
         [0031]    Referring to FIG. 3, the bank address signals BA&lt;0:1&gt; and /BA&lt;0:1&gt; applied from the bank address buffer  200  shown in FIG. 2 are applied to a flip-flop unit  513 , and respectively become input signals for a first OR gate  511  and a second OR gate  512 .  
         [0032]    Here, an output signal of the first OR gate  511  is applied to an input of the second OR gate  512 , and an output signal of the second OR gate  512  is applied to an input of the first OR gate  511 . The output signals being logically operated in the flip-flop unit  513  are respectively applied to non-inverted inverters IV 1  and IV 2 , and IV 3  and IV 4  in a delay unit  514 , delayed, and converted into the additional row address signals RA&lt;11:12&gt; and /RA&lt;11:12&gt;.  
         [0033]    In the case of designing a two-bank device, the external bank address signal BAN&lt;0&gt; is used for the bank address signal, and the external bank address signal BAN&lt;1&gt; is used for the additional row address signal. Meanwhile, in the case of a single bank device, all the external bank address signals BAN&lt;0:1&gt; are used for the additional row address signals, for example, RA&lt;11:12&gt; and /RA&lt;11:12&gt; in selecting the building block of the 4M core cell.  
         [0034]    [0034]FIG. 4 is a circuit diagram of the row pre-decoder  300  for selecting (2M/4M) memory compiler tiling unit building block.  
         [0035]    Referring to FIG. 4, in a decode unit  301  of the row pre-decoder  300 , NMOS transistors N 1 , N 2 , and N 3  are serially connected, and respectively coupled to a row active command signal ROWATV, the row address signals RA&lt;0:12&gt; and /RA&lt;0:12&gt; provided from the row address buffer  100  and the bank address buffer  200  shown in FIG. 2 through gates.  
         [0036]    A NMOS transistor N 4  is connected between the NMOS transistors N 2  and N 3 , and has a gate to which a wafer burn-in signal WBI is applied. A NMOS transistor N 5  in a refresh unit  302  is connected to the NMOS transistor N 1  in parallel, and has a gate to which a refresh command signal INT_XAT is applied. Further, NMOS transistors N 6  and N 7 , serially connected between the NMOS transistor N 5  and ground voltage, have gates each of which receives the refresh control signals RCNT&lt;0:12&gt; and /RCNT&lt;0:12&gt; applied from the first and second refresh control units  250  and  520  shown in FIG. 2.  
         [0037]    In a control unit  303 , PMOS transistors P 1  and P 2  are serially connected between the power supply voltage and a common drain terminal to which the NMOS transistors N 1  and N 5  are connected, and have gates to which the refresh command signal INT_XAT and the row active command signal ROWATV are respectively applied. In a drive unit  304 , an inverter IV 5  is connected to a common drain terminal of the NMOS transistors N 1  and N 5 , and generates a pre-decoding signal AXM&lt;0:12&gt; of the row pre-decoder  300  through an output terminal thereof. Here, both ends of the inverter IV 5  are respectively coupled to drain and gate terminals of a PMOS transistor P 3 . The pre-decoding signal AXM&lt;0:12&gt; provided from the drive unit  304  is converted into the composite row address signals AXBC&lt;0:3&gt; through a logic operation unit  305 .  
         [0038]    Here, in the case of selecting a block in a normal operation, the NMOS transistors N 1 , N 2 , and N 3 , serially connected in the decode unit  301 , input the row address signals RA&lt;0:12&gt;, /RA&lt;0:12&gt;, and the row active command signal ROWATV in order to minimize the effect of a charge share in operation.  
         [0039]    Further, for the purpose of activating all the blocks in a wafer burn-in mode, the NMOS transistor N 4  is connected in parallel.  
         [0040]    In accordance with the foregoing description, the address control apparatus of the semiconductor memory device using the bank address can flexibly realize the density of row/high (2M˜64M) embedded-DRAM as well as reducing design time in employing the memory compiler.  
         [0041]    In other words, the design time can be remarkably reduced by utilizing the bank address in parallel with the row address in accordance with the bank architecture, considering the optimum layout and the minimum modification of the circuit appropriate for the DRAM compiler.  
         [0042]    Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as described in the accompanying claims.