Abstract:
The present invention relates to an arithmetic decoding system and apparatus based on the adaptive content. The system includes a control unit, a decoding unit and an interface unit. The control unit fills the code stream data into the decoding unit and configures and controls the decoding unit through the interface unit. The decoding unit performs a decoding for all the syntax elements from the code stream data in the macro block, assembles the syntax elements and transmits them to the control unit. The interface unit transfers the interaction information between the decoding unit and the control unit. The present invention obtains syntax elements by the CABAC decoding through hardware so that the decoding efficiency is highly improved and the requirements for the video processing speed and the data processing capacity of the real-time and high definition applications are satisfied.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to video communication fields, and more particularly to an arithmetic decoding system and apparatus based on an adaptive content.  
       BACKGROUND OF THE INVENTION  
       [0002]     The CABAC (Context-based Adaptive Binary Arithmetic Coding) is one of the two entropy-coding schemes adopted in the international video coding standard H. 264. Compared with the other entropy-coding scheme CAVLC (Context-based Adaptive Variable Length Coding), the CABAC has a higher compressing efficiency but is also more complicated in implementation.  
         [0003]     The function of the entropy-coder is to code the values of all the syntax elements in each macro-block (MB) into the code stream successively according to the MB scan order. MB is a basic unit block in the video image coding and each image is divided into MBs and then coded.  
         [0004]     The CABAC arithmetic decoding is based on the principle of space recursion partition. When decoding the current bin, the probability of the current bin being 0 or 1 is required to know, which is represented by p and is decided by the content probability model corresponding to the current bin. The more probable symbol (MPS) and the less probable symbol (LPS) should be firstly differentiated and they correspond to 0 or 1 respectively. The value of LPS (valLPS) and the value of MPS (valMPS) are represented by 0 and 1 and applied in the content probability model corresponding to the decoding of the current bin. If the value of MPS corresponding to the current bin is represented by p(0), the value of LPS is represented by p(1)=1−p(0).  
         [0005]     The space range of the dualized probability is (0, 1) and the whole space is determined by the value of codIRange. The range of the subinterval is calculated by the probability value p corresponding to the decoding of the current bin such that the range of the MPS space corresponds to p(0)*codIRange and the range of the LPS space corresponds to codIRange−p(0)*codIRange. After the probability space is determined, within which subinterval the probability value corresponding to the decoding of the current bin is can be determined according to the value of codIOffset. If the probability is within the LPS space, the value corresponding to the decoding of the current bin corresponds to the valLPS; and if the probability is within the MPS space, the value corresponding to the decoding of the current bin corresponds to the valMPS. If the probability is within the MPS space, the value of the MPS space p(0)*codIRange is considered as the whole probability space codIRange when decoding the next bin so as to continually partition the space and perform decoding. The above is only a brief illustration of the CABAC decoding, and as to the detailed illustration of the CABAC decoding, please refer to H. 264 protocol, which is cited here for reference and will not be illustrated in detail.  
         [0006]     For example, in the maintenance of the content probability model, the probability evaluation is accomplished through a group of Finite State Machines, which are based on a probability state table covering 64 different probability events. The probability state table is represented by {pLPS(pStateIdx)|0&lt;=pStateIdx&lt;64}.  
         [0007]     Each value in the table corresponds to a LPS value pLPS. The table is organized according to the principle that with the increase of the pStateIdx value, the LPS value decreases and when pStateIdx=0, the corresponding LPS value is 0.5.  
         [0008]     The CABAC algorithm was instituted and proposed on the JVT (the joint group of MPEG of ITU-T international video organization ISO) conference in 2003. Since the CABAC algorithm has developed a comparatively short period of time, proposed structures for realizing an integrated decoding are quite few, especially the high speed and high throughput real-time decoding processor.  
         [0009]     The known CABAC hardware-decoding units mainly have the architecture of software decoding and the combination of the software decoding and the hardware decoding.  
         [0010]     The CABAC software/hardware-decoding units can refer to the jm95 software provided by JVT. The software decoding performs the decoding procedure on the PC according to the algorithm flow and the software is responsible for all the CABAC decoding tasks. However, the decoding speed is slow and the need of real-time applications cannot be satisfied.  
         [0011]     “Arithmetic coding architecture for H.264/AVC CABAC compression system”, Digital System Design, 2004. DSD 2004. Euromicro Symposium on, 31 Aug.-3 Sep., 2004 Page 62-69 by Osorio, R. R.; Bruguera, J. D. provides a hardware-decoding unit architecture with the combination of the software and the hardware, which adopts the hardware speedup mode. The decoding for the coefficient syntax element, which occupies the most workload is realized by the hardware speedup architecture, and the decoding for other syntax elements such as the mb_type, sub_mb_type, CBP (Coded Block Patterns), dquant, brightness predicting mode, chroma predicting mode, MVD (Motion Vector Data) and reference frame index etc., are all realized by the software. Such kind of decoding architecture has a higher efficiency than the software-hardware combined decoding unit. However in the decoding architecture, the hardware only performs the decoding for one kind of syntax element in the macro block, i.e. the decoding for the coefficient, while the software performs the decoding for other syntax elements; and the interaction between the hardware and the software not only relates to the border macro block information but also relates to the continuous interaction in the software and hardware decoding procedure for the Range and Offset variables generated during the CABAC decoding process, which may lead to the unclear function designation of the software and the hardware, to the complex interaction procedure and to the low efficiency.  
         [0012]     Moreover, in the decoding architecture, the software is responsible for the decoding for all the syntax elements except the coefficient and the hardware is only responsible for the decoding for the coefficient, which may result in the resource waste to some extent.  
         [0013]     In brief, in the prior art, the software performs the decoding for all or the majority of syntax elements in the macro block, which may lead to the low efficiency of CABAC decoding and complex realization and cannot satisfy the requirements for the video processing speed and the data processing capacity of the real-time and high definition applications.  
         [0014]     In brief, in the prior art, the software performs the decoding for all or the majority of syntax elements in the macro block, which may lead to the low efficiency of CABAC decoding and complex realization and cannot satisfy the requirements for the video processing speed and the data processing capacity of the real-time and high definition applications.  
       SUMMARY OF THE INVENTION  
       [0015]     The present invention provides an arithmetic decoding system based on the adaptive content. The system includes a control unit, a decoding unit and an interface unit, in which the control unit fills the code stream data into the decoding unit and configures and controls the decoding unit through the interface unit; the decoding unit performs a decoding for all the syntax elements from the code stream data in the macro block, assembles the syntax elements and transmits them to the control unit; and the interface unit transfers the interaction information between the decoding unit and the control unit.  
         [0016]     Preferably, the decoding unit includes a decoding control unit, a decoding management unit and a decoding information management unit, in which the decoding control unit connects the decoding management unit and the decoding information management unit, receives the decoding control signal from the control unit and outputs the control signal of all the syntax elements in the code stream data to the decoding management unit and the decoding information management unit; the decoding management unit receives the decoding control signal from the decoding unit and in the macro block performs the decoding for all the syntax elements from the code stream data filled in the decoding unit; and the decoding information management unit stores the content probability models, selects a content probability model required by decoding each bin for the current syntax element according to the border block and macro block information and outputs the selected model to the decoding management unit for decoding.  
         [0017]     Preferably, the decoding management unit includes a code stream management module, a single bin decoding unit and a regrouping bin module, in which the code stream management stream receives the code stream data and inputs the code stream data to the single bin decoding module; the single bin decoding module decodes the code stream data inputted by the code stream management module and outputs the decoding result to the regrouping bin module; and the regrouping bin module assembles the single bin decoding result outputted from the single bin decoding module into syntax elements, inputs the syntax elements through the interface unit to the control unit and considers the syntax elements of the border block information needed in the subsequent decoding as the reference information when performing the decoding for the later syntax elements.  
         [0018]     Preferably, the decoding information management unit includes a content probability model selecting module, a content probability model memory and a border block information maintaining module, in which the content probability model memory stores the content probability models needed when performing the decoding for the syntax elements; the border block information maintaining module maintains the border macro block information needed when decoding the current macro block; and the content probability model selecting module selects the content probability model needed when decoding each bin for the current syntax element according to the border macro block and the macro block information provided by the border block information maintaining module and outputs an indication signal of the content probability model to the content probability model memory.  
         [0019]     Preferably, the decoding information management unit further includes a content probability model buffer, which is used to buffer the content probability model needed when performing the decoding for the syntax elements, to transmit the corresponding content probability model to the single bin decoding module according to the indication signal of the content probability model outputted from the content probability model selecting module, and to receive the content probability model updated by the single bin decoding module and write the updated content probability model to the content probability model memory.  
         [0020]     Preferably, the code stream management module further includes a code stream memory, which is used to store the code stream data and to provide the code stream data to the single bin decoding module.  
         [0021]     Preferably, the border block information maintaining module further includes a first group of registers for storing the information of the left neighboring macro block and a second group of registers for storing the information of the upper neighboring macro block.  
         [0022]     Preferably, the content probability model buffer further includes a register group and the register group comprises a plurality of registers for buffering the content probability model needed by the single bin decoding module.  
         [0023]     Preferably, the interface unit further includes a decoding circuit for decoding the address of the read-write data from the control unit to the interface unit, a configuration register group for storing the decoding configuration information written by the control unit through the decoding circuit and an output result register and an output result register group for storing the decoding results inputted by the single bin decoding module.  
         [0024]     Preferably, the interaction information includes the code stream data, the border macro block information and the decoding control signal, and the decoding control signal comprises the start signal of the skip decoding, the start signal of the field decoding and the start signal of the mb_layer decoding.  
         [0025]     In order to better realize the object of the present invention, the present invention further provides an arithmetic decoding apparatus based on the adaptive content. The decoding apparatus is realized by hardware, which is used to obtain all the syntax elements by decoding the code stream data needed to be decoded in the macro block and to assemble the syntax elements and then transmit them.  
         [0026]     Preferably, the decoding apparatus includes a decoding control unit, a decoding management unit and a decoding information management unit, in which the decoding control unit connects the decoding management unit and the decoding information management unit, receives the decoding control signal and outputs the control signal of all the syntax elements in the code stream data to the decoding management unit and the decoding information management unit; the decoding management unit receives the decoding control signal from the decoding unit and in the macro block performs the decoding for all the syntax elements from the code stream data filled in the decoding unit; and the decoding information management unit stores the content probability models, selects a content probability model required by decoding each bin for the current syntax element according to the border block and macro block information and outputs the selected model to the decoding management unit for decoding.  
         [0027]     Preferably, the decoding management unit includes a code stream management module, a single bin decoding unit and a regrouping bin module, in which the code stream management stream receives the code stream data and inputs the code stream data to the single bin decoding module; the single bin decoding module decodes the code stream data inputted by the code stream management module and outputs the decoding result to the regrouping bin module; and the regrouping bin module assembles the single bin decoding result outputted from the single bin decoding module into syntax elements, outputs the syntax elements and considers the syntax elements of the border block information needed in the subsequent decoding as the reference information when performing the decoding for the later syntax elements.  
         [0028]     Preferably, the decoding information management unit includes a content probability model selecting module, a content probability model memory and a border block information maintaining module, in which the content probability model memory stores the content probability models needed when performing the decoding for the syntax elements; the border block information maintaining module maintains the border macro block information needed when decoding the current macro block; and the content probability model selecting module selects the content probability model needed when decoding each bin for the current syntax element according to the border macro block and the macro block information provided by the border block information maintaining module and outputs an indication signal of the content probability model to the content probability model memory.  
         [0029]     Preferably, the decoding apparatus further includes a content probability model buffer, which is used to buffer the content probability model needed when performing the decoding for the syntax elements, to transmit the corresponding content probability model to the single bin decoding module according to the indication signal of the content probability model outputted from the content probability model selecting module, and to receive the content probability model updated by the single bin decoding module and write the updated content probability model to the content probability model memory.  
         [0030]     Preferably, the code stream management module further includes a code stream memory, which is used to store the code stream data and to provide the code stream data to the single bin decoding module.  
         [0031]     Preferably, the border block information maintaining module further includes a first group of registers for storing the information of the left neighboring macro block and a second group of registers for storing the information of the upper neighboring macro block.  
         [0032]     Preferably, the content probability model buffer further includes a register group and the register group comprises a plurality of registers for buffering the content probability model needed by the single bin decoding module.  
         [0033]     The present invention uses the hardware to obtain all the syntax elements by the CABAC decoding so that the software and the hardware have clear function designations, the interface is clear, the decoding process is easy to be controlled and realized, the decoding efficiency is highly improved and the requirements for the video processing speed and the data processing capacity of the real-time and high definition applications are satisfied. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0034]      FIG. 1  is a diagram showing the configuration architecture of the decoding system according to an embodiment of the present invention;  
         [0035]      FIG. 2  is a diagram showing the architecture of the decoding unit in the decoding system according to an embodiment of the present invention;  
         [0036]      FIG. 3  is a diagram showing the composition of the syntax element obtained from the decoding unit according to an embodiment of the present invention;  
         [0037]      FIG. 4  is a status schematic diagram showing the decoding for the mb_layer syntax elements by the decoding unit according to an embodiment of the present invention;  
         [0038]      FIG. 5  is a diagram showing the architecture of the decoding unit according to an embodiment of the present invention;  
         [0039]      FIG. 6  is a flow chart showing the decoding of the macro blocks of frames P and B according to an embodiment of the present invention;  
         [0040]      FIG. 7  is a flow chart showing the decoding of the macro blocks of frame I according to an embodiment of the present invention;  
         [0041]      FIG. 8  is an architecture diagram of the interface unit in the decoding system according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0042]     The present invention will be illustrated in detail with reference to the drawings and embodiments in order to make the solution and advantages of the present invention more apparent. It should be noted that the embodiments here are only for the purpose of illustration and are not intended to limit the scope of the present invention.  
         [0043]     In the present invention, the values or the bin values of the neighboring macro blocks are used to calculate the value of the content probability model for decoding the current bin. According to a certain calculating rules, the value of the corresponding content probability model is selected from the RAM (Random Access Memory), which stores the content probability models. The value corresponding to the decoding of the current bin is obtained according to the above calculating rules and the probability of the current bin being 0 or 1 is updated, i.e. the value of the content probability model corresponding to the decoding of the current bin is updated and written to the corresponding RAM space. The above procedure shows that the CABAC decoding is a content based arithmetic decoding. The essence of “content based” is to determine the probable value of the next syntax element according to the value of the former syntax elements obtained from decoding. If the determination is right, the current syntax element can be obtained with little or no consumption of bits so that the aim of improving the code stream compression ratio is achieved.  
         [0044]     According to the above solution, the present invention provides a CABAC decoding apparatus in hardware which is used for the decoding for all the syntax elements of CABAC. The parameters of Range and Offset of the CABAC correlative decoding characteristics required in the decoding process and the variables such as the content probability model required to be updated and maintained in the decoding process can be totally maintained by the decoding apparatus itself.  
         [0045]     In the CABAC decoding system of the present invention, the decoding process of the decoding apparatus is controlled by the corresponding software, however, the software needn&#39;t participate any data maintenance and decoding process of the CABAC decoding itself, but only provides the border macro block information, the code stream data and the control signal. The interaction between the hardware and the software includes the interaction of code stream data, the interaction of the configuration information and the obtainment of the result data after the decoding based on the macro block.  
         [0046]      FIG. 1  is an architecture diagram of the decoding system according to an embodiment of the present invention. The system is composed of three parts, a decoding unit  100  for the CABAC decoding, a control unit  200  for the configuration and control of the decoding unit  100 , and an interface unit  300 . The control unit  200  exchanges data with the interface unit  300  through the access bus and controls the decoding unit  100  to perform decoding. The decoding unit  100  is the main part of the CABAC decoding system and implements the decoding for all the syntax elements in the macro block. The control unit  200  transmits the decoding control signal and the code stream data required for decoding to the decoding unit  100  through the interface unit  300 , and the decoding unit  100  transmits the decoded data to the control unit  200  through the interface unit  300 .  
         [0047]      FIG. 2  is an architecture diagram of the decoding unit in the decoding system according to an embodiment of the present invention.  
         [0048]     The decoding unit  100  may include a decoding control unit  101 , a decoding management unit and a decoding information management unit.  
         [0049]     The decoding control unit  101 , which is connected to the decoding management unit and the decoding information management unit, receives the decoding control signal from the control unit  200  and outputs the control signal of all the syntax elements decoded from the code stream data to the decoding management unit and the decoding information management unit.  
         [0050]     The decoding management unit receives the decoding control signal from the decoding control unit and in the macro block performs decoding to obtain all the syntax elements from the code stream data in the decoding unit.  
         [0051]     The decoding information management unit stores the content probability models, selects the content probability model required by each bin in the decoding for the current syntax element according to the border block and macro block information, and then outputs the selected content probability model to the decoding management unit for decoding.  
         [0052]     The decoding management unit includes a code stream management module  102 , a single bin decoding module  106  and a regrouping bin module  107 .  
         [0053]     The decoding information management unit includes a content probability model selecting module  105 , a content probability model memory  104  and a border block information maintaining module  103 .  
         [0054]     In practice, the single bin decoding unit  106  and the content probability model selecting module  105  are realized by the combinational circuit, the other module units are realized by the sequential circuit and the whole decoding unit  100  is realized by the digital circuit, which is integrated on an integrated circuit chip.  
         [0055]     The decoding control unit  101  is responsible for controlling the decoding processes of other modules in the decoding unit  100  and transmits the decoding control signal to each module to coordinate the operation of each module. The decoding control unit  101  includes a control state machine internally, and realizes the object to perform the decoding for all the syntax elements in the whole macro block through controlling each decoding state.  
         [0056]      FIG. 3  shows the three decoding control processes of the control state machine in the decoding control unit  101 , which are the decoding control process of skip state, the decoding control process of field state and the decoding control process of mb_layer state respectively.  FIG. 3  contains all the syntax elements of the CABAC coding and decoding adopted in the H.264 protocol (main profile) as follows:  
         [0057]     (1) Skip represents the decoding signal showing whether the macro blocks in the frame P are skipped.  
         [0058]     (2) End_slice represents the identification signal showing whether the current macro block is the last macro block in the slice layer.  
         [0059]     (3) mb_type represents the type signal of the current macro block and sub_mb_type represents the type signal of four  8 * 8  blocks included in the macro blocks.  
         [0060]     (4) Intra_pre_mode represents the brightness prediction mode signal and the chroma prediction mode signal showing the decoding of the 4*4 type when the current macro block is an intra block.  
         [0061]     (5) Cbp represents the indication signal showing the coefficient of the current macro block exists.  
         [0062]     (6) Dquant represents the quant stagger signal of the current macro block.  
         [0063]     (7) Mvd represents the stagger signal showing the motion vector of the current macro block.  
         [0064]     (8) Refframe represents the reference frame signal of the current macro block.  
         [0065]     (9) Coeff represents the coefficient signal of the current macro block.  
         [0066]     (10) Field represents the field identification signal of the current macro block.  
         [0067]     An embodiment of the present invention separates the skip decoding and field decoding from the mb_layer decoding, which helps to improve the decoding efficiency and to reduce the cost of the interaction between the software and the hardware to the maximum extent. The skip decoding, field decoding and mb_layer decoding can be respectively controlled by the control unit  200  so as to accomplish the decoding for the corresponding syntax element.  
         [0068]     The mb_layer decoding includes the decoding for 9 kinds syntax elements and is the main part of the CABAC decoding. In the mb_layer, the 9 syntax elements are obtained through a certain decoding order and the order is associated with the H.264 protocol. Please refer to the JVT-G050, “Draft ITU-T Recommendation H.264 and Draft ISO/IEC 14496-10 AVC” in JVT of ISO/IEC doc, T. Wig, Ed., Pattaya, Thailand, March 2003, which is incorporated for reference in the present invention and will not be illustration in detail. If the value of the skip is 1 during the skip decoding, the decoding is performed for the end_slice syntax element and the process is ended, and if the value of the skip is 0, the process is ended immediately and the decoding unit  100  performs the next decoding operation.  
         [0069]     In the present embodiment, the reason why the skip decoding process is an individual process and is not integrated in the mb_layer decoding is that the configuration information for the skip decoding process is comparatively less while the mb_layer decoding requires much configuration information, and when the macro block is the skip mb, the mb_layer decoding process need not be started. Therefore, the decoding of the whole macro blocks can be accomplished with little configuration information, which is very cost effective.  
         [0070]     The field decoding is optional. The reason why this decoding process for the syntax element field is an individual process is that the selecting mode of neighboring macro blocks of this syntax element is different from those of the mb skip decoding and mb_layer decoding in some cases. Therefore, it is necessary to be operated individually by the independent mode of the software-hardware interaction.  
         [0071]     According to another embodiment of the present invention, the skip decoding and the field decoding can be combined into the mb_layer decoding, and also, the decoding for certain syntax elements in the mb_layer can be separated from the mb_layer decoding and independently controlled by the control unit  200 .  
         [0072]      FIG. 4  shows the detailed state control procedure when the decoding control unit controls the decoding unit  100  to perform the decoding for the syntax elements in the mb_layer (macro block). During the decoding for the syntax elements in the mb_layer, the initial state of the decoding unit  100  is idle. When receiving the effective mb_layer decoding start signal (C 1 ), the decoding unit  100  performs the mb_type decoding.  
         [0073]     After the decoding unit  100  finishes the mb_type decoding, if it is the macro block P or macro block B decoding and the macro block partition is not in the form of four 8*8 blocks (C 2 ), the refframe decoding, the mvd decoding, the cbp and dqp decoding and the coeff decoding are performed successively; if it is the macro block I decoding and not the I_PCM mode decoding (C 3 ), the cbp and dqp decoding and the coeff decoding are performed successively; if it is the macro block I decoding and also the I_PCM mode decoding (C 4 ), the flow returns to the idle state; and if it is the macro block P or macro block B decoding and the macro block is in the form of four 8*8 blocks, the sub_mb_type decoding (C 7 ), the refframe decoding, the mvd decoding, the cbp and dqp decoding and the coeff decoding are performed successively.  
         [0074]     After the coeff decoding, if it is now in the mbaff decoding mode and the serial number of the current macro block is even (C 5 ), the flow returns to the idle state; and if it is in the non-mbaff decoding mode or in the mbaff decoding mode but the serial number of the current macro block is odd, the send_slice decoding will be performed and then the flow returns to the idle state.  
         [0075]     The code stream management module  102  receives the code stream data and transmits the code stream data to the single bin decoding module  106 . The code stream management module  102  includes a code stream memory  1021 , which is used to provide the code stream data to the single bin decoding module  106 . When the code streams in the code stream memory  1021  are going to be consumed, the code stream management module  102  sends a request for the code stream uploading to the control unit  200 .  
         [0076]     In the macro block decoding process, if the code streams in the code stream memory  1021  are consumed, the code stream management module  102  sends a request for the code stream uploading to the control unit  200 . And at this time, the code stream management module  102  interrupts the decoding until the control unit  200  fills the needed code streams.  
         [0077]     The border block information maintaining module  103  maintains the border macro block information, and the border macro block information includes the information of the upper neighboring and left neighboring macro blocks. The border block information maintaining module  103  includes two groups of registers  1031  and  1032 , which respectively store the information of the left neighboring macro block and that of the upper neighboring macro block. The border macro block information includes whether the neighboring macro block is effective, whether the neighboring macro block is the skip, the frame field mode of the neighboring macro block and the decoded syntax elements in the neighboring macro blocks. When performing the decoding for the syntax element in the current macro block, the already decoded syntax elements in the neighboring macro block are required for the first bin of the syntax element to determine how to choose the probability model. And at this time, the border block information maintaining module  103  is required to provide the border macro block information needed when choosing the probability model to the content probability model selecting module  105 .  
         [0078]     According to an embodiment of the present invention, the control unit  200  maintains all the border macro block information of the current macro block, and the control unit  200  transfers the border macro block information to the border block information maintaining module  103  through the interface unit  300  when decoding the current macro block. However, the interaction between the software and hardware decoding in such solution is comparatively complex.  
         [0079]     In another embodiment of the present invention, the information of the syntax element in the border macro block may be absolutely maintained by the border block information maintaining module  103  in the decoding unit  100  and thus the interaction between the software and the hardware is simple, but the border block information maintaining module  103  needs to maintain the information of the left neighboring macro block and the upper row of the macro blocks, which costs a lot of resources.  
         [0080]     According to the preferred embodiment of the present invention, the control unit  200  maintains the information of the syntax element in the upper neighboring macro block and the border block information maintaining module  103  maintains the information of the syntax element in the left neighboring macro block. Therefore, the interaction between the software and the hardware is simple and the resource consumed by the hardware is only the information for maintaining the syntax element in the left neighboring one or two (in mbaff mode) macro blocks.  
         [0081]     The content probability model memory  104  is an RAM for storing the probability models needed by all the syntax elements. The total number of the stored probability models in the content probability model memory  104  is  399  and this is all the probability model information needed to decode the whole macro block for all the syntax elements.  
         [0082]     The content probability model selecting module  105  includes the probability model selecting strategies of all the bins for all the syntax elements and determines the probability model needed when decoding each bin for the current syntax element. The output of the content probability model selecting module  105  is similar to a pointer indicating which probability model should be selected from those provided by the content probability model memory  104  when the single bin decoding unit  106  decodes each bin for the current syntax element. The principles to determine the probability model are as follows: 1) for which syntax element the decoding is performed now; 2) which bin is decoded to obtain the current syntax element; and 3) the value of the syntax element corresponding to the border macro block. The rules of determining the probability model are described in the H.248 protocol and refer to JVT-G050, “Draft ITU-T Recommendation H.264 and Draft ISO/IEC 14496-10 AVC” in JVT of ISO/IEC doc, T. Wig, Ed., Pattaya, Thailand, March 2003, which will not be illustrated in detail here.  
         [0083]     The single bin decoding unit  106  decodes the bin for each syntax element and the decoding mode adopts the CABAC arithmetic decoding method specified by H.264 protocol. Please refer to JVT-G050, “Draft ITU-T Recommendation H.264 and Draft ISO/IEC 14496-10 AVC” in JVT of ISO/IEC doc, T.Wig,Ed.,Pattaya, Thailand, March 2003, which will not be illustrated in detail here. The code streams needed in the decoding process are obtained from the code stream management module  102  and the probability models needed in the decoding process are obtained from the content probability model buffer  108 . The decoding result of the single bin decoding unit  106  is transmitted to the regrouping bin module  107  and is used to reconstruct the syntax element.  
         [0084]     Since the single bin decoding unit  106  decodes only one bin for a syntax element, if the final syntax element is to be recovered from the decoding result of the bins, a regrouping bin process is needed. The regrouping bin module  107  is used to accomplish the assembling of the current syntax element. The assembling manner of each syntax element is different, the assembling is according to the type of the current syntax element, and the assembling principle is according to the H.264 protocol. After the assembling of the syntax elements, the regrouping bin module  107  sends the decoded syntax element to the control unit  200  and sends the syntax elements of the border macro block information needed in the subsequent decoding to the border block information maintaining module  103 , which are regarded as the reference information for the decoding for the later syntax element.  
         [0085]     In the above embodiment, the single bin decoding unit  106  directly selects the needed probability model from the content probability model memory  104 . Due to the limit of reading the RAM, the selecting and updating of the probability model will greatly influence the decoding efficiency. According to a preferred embodiment of the present invention, the probability model needed in the decoding for a certain type of syntax elements is read into the content probability model buffer  108  as shown in  FIG. 5 . The content probability model buffer  108  is a cache and provides the high speed buffer for the invoking of the content probability model by the single bin decoding unit  106  so as to improve the efficiency in selecting and updating the content probability model. When receiving the indication signal from the content probability model selecting module  105 , the content probability model buffer  108  sends the corresponding probability model to the single bin decoding unit  106 .  
         [0086]     The corresponding content probability model needs to be updated when decoding each bin. 44 7-bit registers are set in the content probability model buffer  108  in order to avoid loading models from the content probability model memory  104  and writing back the updated content probability model repeatedly. All the content probability models are grouped according to their possible invoking order. During the process of decoding a macro block, each group of the content probability models are loaded into the register group once and are written back after being used and updated and the number of the content probability models in one group is less than or equal to 44.  
         [0087]     According to an embodiment of the present invention, all the content probability models are divided into the following 18 groups according to the invoking order of the syntax elements:  
         [0088]     the 1 st  group: mb_skip_flag;  
         [0089]     the 2 nd  group: mb_field_decoding flag;  
         [0090]     the 3 rd  group: mb_type for SI slice;  
         [0091]     the 4 th  group: mb_type for I slice;  
         [0092]     the 5 th  group: mb_type for P slice;  
         [0093]     the 6 th  group: mb_type for B slice;  
         [0094]     the 7 th  group: sub_mb_type for P slice;  
         [0095]     the 8 th  group: sub_mb_type for B slice;  
         [0096]     the 9 th  group: syntax elements for intra prediction mode, including prev_inrta4×4_pred_mode_flag,rem_intra4×4_pred_mode, intra_chroma_pred_mode;  
         [0097]     the 10 th  group: ref_idx;  
         [0098]     the 11 th  group: abs_mvd;  
         [0099]     the 12 th  group: coded_block_pattern;  
         [0100]     the 13 th  group: mb_dq_delta;  
         [0101]     the 14th group: and the decoding of DC coefficient in intra16*16 luminance mode for the coded_block_flag, significant_coeff_flag, last_significant_coeff_flag, coeff_abs_level_minus1;  
         [0102]     the 15th group: the decoding of AC coefficient in intra16*16 luminance mode for the coded_block_flag, significant_coeff_flag, last_significant_coeff_flag, coeff_abs_level_minus1;  
         [0103]     the 16th group: the decoding of coefficient not in the intra16*16 luminance mode for the coded_block_flag, significant_coeff_flag, last_significant_coeff_flag, coeff_abs_level_minus1;  
         [0104]     the 17th group: and the decoding of DC coefficient in the chroma mode for the coded_block_flag, significant_coeff_flag, last_significant_coeff_flag, coeff_abs_level_minus1;  
         [0105]     the 18th group: and the decoding of AC coefficient in the chroma mode for the coded_block_flag, significant_coeff_flag, last_significant_coeff_flag, coeff_abs_level_minus1.  
         [0106]     It should be noted that the grouping manner of the above content probability models is flexible if it can guarantee that the content probability models needed in the decoding for a certain type of syntax elements can be accessed through the content probability model buffer  108 .  
         [0107]     The control unit  200  is the computer program for the configuration and control of the CABAC decoding process of the decoding unit  100 . The control unit  200  is loaded and operated in the CPU (Central Processing Unit) or DSP (Digital Signal Processor) and realizes the decoding configuration and control of the decoding unit  100  through the interface unit  300 , which specifically includes as follows:  
         [0108]     (1) Initializing the decoding unit  100 ;  
         [0109]     (2) Configuring the border macro information and the code stream data needed in the CABAC decoding process;  
         [0110]     (3) Reading the decoding result data from the decoding unit  100 ;  
         [0111]     (4) Sending a control signal to control the decoding unit  100  to perform the CABAC decoding process.  
         [0112]     According to an embodiment of the present invention, before decoding the macro block, the control unit  200  checks if the decoding unit needs to be filled with code streams, if yes, it fills the needed code streams and then starts the decoding flow of the macro block.  
         [0113]      FIG. 6  and  FIG. 7  respectively show the flows of decoding the frames P, B and I by the decoding unit  100  under the control of the control unit  200 .  
         [0114]     The whole flow can be divided into two parts: one is the control unit  200  configures the decoding unit  100 , i.e. the control unit writes the configuration data, code streams and control data in the decoding unit  100 , the other is the control unit  200  reads the data from the decoding unit  100  and the read data indicate the corresponding syntax elements obtained by the decoding unit  100  through the configuration and decoding control of the control unit  200 .  
         [0115]     The configuration process of the decoding unit  100  by the control unit  200  includes configuring the skip decoding information, field decoding information, mb_layer decoding information and code streams. The reading data process from the decoding unit  100  by the control unit  200  includes reading the skip information, field information, decoding information of the mb_layer and end_slice information.  
         [0116]      FIG. 6  and  FIG. 7  show the difference between the decoding of the frames P or B and that of the frame I decoding is that the control unit  200  adds a skip decoding control process to the configuration of the decoding unit  100 . If the value of the decoded skip is 1, the decoding of the whole macro block is finished, otherwise, the decoding of the macro block for the syntax elements is performed continuously and this process is the same with the control process of the frame I decoding.  
         [0117]     The following is the description of the decoding process of the frame P and the frame B:  
         [0118]     In Step S 602 , the control unit  200  configures the border macro block information needed when performing the decoding for the syntax element of skip for the decoding unit  100 , and then sends the start signal of the skip decoding.  
         [0119]     In Step S 602 , after receiving the start signal, the decoding unit  100  begins to perform the decoding for the syntax element of skip.  
         [0120]     In Step S 603 , the control unit  200  reads the value of the decoded skip from the decoding unit  100 .  
         [0121]     In Step S 604 , the control unit  200  determines whether the value of skip is 1, if yes, the decoding of the whole macro block is finished, otherwise, the procedure proceeds to the step S 605 .  
         [0122]     In Step S 605 , the control unit  200  determines whether the decoding should be performed for the syntax element of field, i.e. whether the dec_field_flag is 1, if yes, the procedure proceeds to the step S 606 , otherwise, the procedure proceeds to the step S 609 .  
         [0123]     In Step S 606 , the control unit  200  configures the needed border macro block information for the decoding unit  100  and sends the start signal of the field decoding. The prerequisites for the field decoding are that it&#39;s in the mbaff mode and the macro block under decoding is the upper one of a macro block pair, or the macro block under decoding is the lower one of the macro block pair and the upper macro block is a skip macro block.  
         [0124]     In Step S 607 , after receiving the start signal, the decoding unit  100  performs the decoding for the syntax element of field.  
         [0125]     In Step S 608 , after the decoding unit  100  finishes the field decoding, the control unit  200  reads the result data of the field decoding.  
         [0126]     In Step S 609 , the control unit  200  configures the border macro block information needed in the mb_layer decoding for the decoding unit  100 , and then sends the start signal of the mb_layer decoding.  
         [0127]     In Step S 610 , after receiving the start signal, the decoding unit  100  performs the decoding for the syntax elements in the mb_layer.  
         [0128]     In Step S 611 , after the decoding unit  100  finishes the decoding, the control unit  200  reads the result data of the mb_layer decoding.  
         [0129]     In Step S 612 , the decoding unit  100  determines whether the load_bits_flag is 1, i.e. whether the code streams should be filled into the decoding unit  100 , if yes, the procedure proceeds to the step S 613 , otherwise the flow is ended.  
         [0130]     In Step S 613 , the decoding unit interrupts internally and requests the control unit  200  to fill code streams into the decoding unit  100 . After the fill of the code streams, the decoding unit  100  cancels the internal interrupting automatically and resumes the decoding. It should be noted that after the mb_layer decoding, the control unit  200  checks if the code stream memory  1021  in the decoding unit  100  is empty, if yes, the control unit  200  fills the code streams into the decoding unit  100  so as to make the code stream memory  1021  in the decoding unit  100  full and to reduce the interrupting times due to the exhaust of code streams during the mb_layer decoding since too many interrupting times can reduce the decoding efficiency of the decoding unit  100 .  
         [0131]     In Step S 614 , if the control unit  200  determines that in the mb_layer decoding the current macro block is an I_PCM type, the control unit  200  acquires the information indicating the code streams are exhausted from the decoding unit  100 , recovers those which are corresponding to the I_PCM among the code streams outside the decoding unit  100  to the image of the macro block, and refills the remaining code streams into the decoding unit  100 . The code stream memory  1021  in the decoding unit  100  is defaulted to be null in this code stream filling process.  
         [0132]     In Step S 615 , the decoding unit  100  performs the decoding for the syntax elements in the mb_layer of the code streams refilled by the control unit  200 .  
         [0133]     In Step S 616 , the decoding unit  100  performs the decoding for the end_slice syntax elements. End_slice syntax elements are usually obtained in the mb_layer decoding and are read by the control unit  200 . But when the macro block is of I_PCM type, the control unit  200  has to recover the macro block to the I_PCM data and to refill the code streams into the decoding unit  100  and then the decoding unit  100  performs the decoding for the end_slice. After the decoding of the decoding unit  100 , the control unit  200  reads the end_slice syntax elements.  
         [0134]      FIG. 7  shows the decoding process of the frame I, and the steps S 701 ˜ 712  are the same with the above steps S 605 ˜ 616 , which will not be illustrated in detail here.  
         [0135]     The interface unit  300  is responsible for the transmission of the interaction information between the decoding unit  100  and the control unit  200 . The interface unit  300  transmits the code streams, border macro block information and control signal to be configured in the decoding process to the decoding unit  100  and the border macro block information includes following signal and information:  
         [0136]     (1) the avaible_flag signal showing whether the neighboring blocks exist;  
         [0137]     (2) the skip_flag signal showing whether the neighboring macro block is a skip block;  
         [0138]     (3) the field_flag signal showing the neighboring macro block frame field mode;  
         [0139]     (4) the neighboring macro block type signal and sub_mb_type signal;  
         [0140]     (5) the neighboring macro block CBP signal and CBF signal;  
         [0141]     (6) the signal showing whether the neighboring block is an inside-frame macro block or between-frames macro block;  
         [0142]     (7) the neighboring macro block chroma prediction mode signal;  
         [0143]     (8) the neighboring macro block dquant signal;  
         [0144]     (9) the information of the reference frame, and the mvd of the neighboring macro blocks;  
         [0145]     (10) the signal showing whether the current slice is in the mbaff mode;  
         [0146]     (11) the current slice type signal, i.e. determining whether the current frame is frame I, frame P or frame B;  
         [0147]     (12) the information of num_refidx0_minus1, num_refidx1_minus1, slice_data_partition and constrained_intra_predflag obtained in decoding the current slice header.  
         [0148]     The interface unit  300  includes a series of registers and a group of RAMs. The interface unit  300  sets an address for each register and for each data segment in the RAM respectively. The control unit  200  interacts with the interface unit  300  through accessing these addresses and writing and reading the data corresponding to these address segments.  
         [0149]      FIG. 8  shows the interface unit  300  includes a decoding circuit  301 , a configuration register group  302 , an output result register group  303  and an output result memory  304 .  
         [0150]     The decoding circuit  301  implements the address decoding from the control unit  200  to the interface unit  300  so that the control unit  200  can write data into and read data from the interface unit  300 .  
         [0151]     The configuration register group  302  stores the configuration information for controlling the decoding of the decoding unit  100 , and the configuration information is written by the control unit  200  through the decoding circuit  301 .  
         [0152]     The decoding unit  100  writes the decoding result directly into the interface unit  300 , in which the MVD data and coeff data are written into the output result memory  304  and the other syntax elements are directly written into the output result register group  303 . The control unit  200  can read the result data obtained by the decoding unit  100  by reading the data in the corresponding addresses.  
         [0153]     It should be noted that in the present invention, the interface unit  300  has a plurality of methods in configuring the neighboring macro block. It can configure the complete information of the upper neighboring macro block and the left neighboring macro block, can only configure the information of the upper neighboring macro block but not the information of the left neighboring macro block while the information of the left neighboring macro block is maintained by the decoding unit  100  itself, and can only configure the control signal and the information of all the other reference syntax elements is maintained by the decoding unit  100 .  
         [0154]     Though illustration and description of the present invention have been given with reference to preferred embodiments thereof, it should be appreciated by ordinary personnel skilled in the art that various changes in forms and details can be made without deviation from the spirit and scope of this invention as defined by the appended claims.