Abstract:
A method is provided for manufacturing a LED package base including providing a metal core substrate having a top surface and a bottom surface and forming two first trenches in the metal core substrate. The first trenches extend from the top surface to the bottom surface. The method further includes at least partially filling in the first trenches with first dielectric material to form dielectric isolations. The dielectric isolations divide the metal core substrate into three metal core portions. Two of the metal core portions may be configured to serve as LED package electrodes. The method also includes applying a second dielectric material to cover at least a portion of the first dielectric material, and forming a conductive layer over the second dielectric material to form circuit contacts. The conductive layer includes a first conductive material.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 14/073,643, titled “LED Package and Method of Manufacturing The Same,” filed Nov. 6, 2013, which is incorporated by reference herein in its entirety. 
    
    
     TECHNICAL FIELD 
     The example embodiments of the present invention generally relate to light emitting diode (LED) packages, and more particularly to designs and fabrication processes of light emitting diode package bases. 
     BACKGROUND 
     A LED package typically includes a LED chip bonded on a package base with an optical-based lens system covering the LED chip. The LED package is typically mounted on a printed circuit board (PCB) which provides electrical current to the LED chip. The LED package illuminates when electrical current flows through the LED package. 
     Conventional LED packages may face challenges in many aspects, such as light distribution of the LED and thermal management. Light distribution is the basis of the LED when LEDs are applied to the light sources in any kind of light application. Insufficient thermal dissipation may result in overheating, which may cause severe performance degradation or permanent damage to the PCB. To improve thermal dissipation, a substrate may be used, which may increase the cost of the LED package. It is desired to improve light distribution and thermal dissipation of a LED package. 
     BRIEF SUMMARY 
     According to one exemplary embodiment of the present invention, a method of manufacturing a light emitting diode (LED) package base comprises providing a metal core substrate having a top surface and a bottom surface and forming two first trenches in the metal core substrate. The first trenches extend from the top surface to the bottom surface. The method further comprises filling in the first trenches with first dielectric material to form dielectric isolations. The dielectric isolations divide the metal core substrate into three metal core portions. Two of the metal core portions serve as light emitting diode package electrodes. The method also comprises applying a second dielectric material to cover at least a portion of the first dielectric material and forming a conductive layer over the second dielectric material to form circuit contacts. The conductive layer includes a first conductive material. 
     According to one exemplary embodiment of the present invention, a light emitting diode (LED) package base comprises a metal core substrate having top surface and bottom surface and two dielectric isolations. The dielectric isolations are formed from the top surface to the bottom surface of the metal core substrate to divide the metal core substrate into three metal core portions. Two of the three metal core portions serve as light emitting diode package electrodes. The dielectric isolations comprise a first dielectric material. The light emitting diode package base comprises a dielectric layer covering at least a portion of the first dielectric material. The dielectric layer includes a second dielectric material. The light emitting diode package base also comprises a conductive layer formed on the dielectric layer. The conductive layer serves as circuit contacts. The conductive layer comprises a first conductive material. The light emitting diode package base further comprises at least two conductive vias formed through the conductive layer and the dielectric layer. The conductive vias comprises a second conductive material. Each conductive via connects a circuit contact to a metal core portion. 
     According to one exemplary embodiment of the present invention, a light emitting diode (LED) package comprises a light emitting diode (LED) package base and a light emitting diode (LED) chip. Contact pads of the light emitting diode chip are electrically coupled to an associated light emitting diode package electrode through circuit contacts and conductive vias. A thermal pad of the light emitting diode chip is thermally coupled to a thermal projection via bonding material. The circuit contacts may comprise different conductive material than that of the conductive vias. 
     These characteristics as well as additional features, functions, and details of various embodiments are described below. Similarly, corresponding and additional embodiments are also described below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING(S) 
       Having thus described the example embodiments of the present invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein: 
         FIG. 1  illustrates a cross-sectional view of a metal core substrate according to some example embodiments of the present invention; 
         FIG. 2  illustrates a cross-sectional view of forming first trenches in the metal core substrate according to some example embodiments of the present invention; 
         FIGS. 3A and 3B  illustrate cross-sectional views of dielectric isolations according to some example embodiments of the present invention; 
         FIGS. 4A and 4B  illustrate cross-sectional views of forming a dielectric layer and a conductive layer according to some example embodiments of the present invention; 
         FIGS. 5A and 5B  illustrate cross-sectional views of forming second trenches according to some example embodiments of the present invention; 
         FIGS. 6A and 6B  illustrate cross-sectional views of conductive vias according to some example embodiments of the present invention; 
         FIGS. 7A and 7B  illustrate cross-sectional views of forming circuit contacts according to some example embodiments of the present invention; 
         FIG. 8A  illustrates a cross-sectional view of a metal core substrate according to some example embodiments of the present invention; 
         FIG. 8B  illustrates a cross-sectional view of forming a first trenches in the metal core substrate according to some example embodiments of the present invention; 
         FIGS. 9A and 9B  illustrate cross-sectional views of dielectric isolations according to some example embodiments of the present invention; 
         FIGS. 10A and 10B  illustrate cross-sectional views of forming a second dielectric layer and a conductive layer according to some example embodiments of the present invention; 
         FIGS. 11A and 11B  illustrate cross-sectional views of forming second trenches according to some example embodiments of the present invention; 
         FIGS. 12A and 12B  illustrate cross-sectional views of forming conductive vias according to some example embodiments of the present invention; 
         FIGS. 13A and 13B  illustrate cross-sectional views of forming circuit contacts according to some example embodiments of the present invention; and 
         FIG. 14  illustrates a cross-sectional view of a light emitting diode package base assembled with a light emitting diode chip structure according to some example embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure now will be described more fully with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. This disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout. “Example,” “exemplary” and like terms as used herein refer to “serving as an example, instance or illustration.” 
       FIG. 1  illustrates a cross-sectional view of a metal core substrate  100  according to some example embodiments of the present invention. The metal core substrate  100  may comprise a top surface  104  and a bottom surface  106 . A thermal projection  102  may be formed on top surface  104  of the metal core substrate  100 , such as by one of mechanical carving, mechanical punch, chemical etching and laser carving. The metal core substrate  100  may comprise thermal conductive material, such as Cu, Al, Au, Ni, metal alloy, graphite, or other thermal conductive material. The thermal projection  102  may comprise thermal conductive material, such as Ag, Cu, Au, Sn, Ni, and Al. The thermal projection  102  may comprise the same material as that of the metal core substrate  100 . 
     At least two first trenches, such as  108 A and  108 B, may be formed in the metal core substrate  100  according to some example embodiments of the present invention, as illustrated in  FIG. 2 . The first trenches  108 A and  108 B may be formed, for example, by mechanical carving, mechanical punch, chemical etching, or laser carving. The first trenches  108 A and  108 B may extend from the top surface  104  to the bottom surface  106  and divide the metal core substrate  100  into three metal core portions, such as  100 A,  100 B, and  100 C. Two of the metal core portions, such as the metal core portions  100 A and  100 B, may serve as light emitting diode package electrodes. The thermal projection  102  may be on top of the center metal core portion  100 C. 
     The first trenches  108 A and  108 B may be at least partially or completely filled with a first dielectric material to form dielectric isolations, such as dielectric isolations  110 A and  110 B, such as by physical vapor deposition, chemical vapor deposition, material molding or injection. Each of the dielectric isolations may electrically isolate two adjacent metal core portions. For example, as shown in  FIGS. 3A and 3B , the dielectric isolation  110 A may electrically isolate the metal core portion  100 A and  100 C. The dielectric isolation  110 B may electrically isolate the metal core portion  100 B and  100 C. The first dielectric material may comprise, for example, at least one of epoxy, polymer resin, a pre-preg composite, Al 2 O 3 , AlN, and SiO 2 . In one embodiment, the first dielectric material may be removed from the top surface  104  to make surface of the dielectric isolations, such as dielectric isolation surface  112 , planar to the top surface  104  as shown in  FIG. 3A . In another embodiment, the first dielectric material may also be applied to the top surface  104  to form a first dielectric layer  114 , as shown in  FIG. 3B . 
     A layer comprising a second dielectric material may be applied to cover at least a portion of the first dielectric material. For example, referring to  FIG. 4A , layer  116  comprising a second dielectric material may be formed on the top surface of the metal core substrate  100  and cover surfaces of the dielectric isolations  110 A and  110 B. In another embodiment, layer  116  comprising a second dielectric material may be formed on the first dielectric layer  114 , as shown in  FIG. 4B . The second dielectric material may comprise, for example, at least one of epoxy, polymer resin, a pre-preg composite, Al 2 O 3 , AlN, plastic, and SiO 2 . The second dielectric material may be the same as the first dielectric material, or different than the first dielectric material. The layer  116  may be formed, for example, using physical vapor deposition, such as sputtering and thermal evaporation, or chemical vapor deposition, such as reaction mechanism, or lamination, such as directly pressing the pre-formed dielectric layer over the substrate. 
     Still referring to  FIGS. 4A and 4B , a conductive layer  118  may be formed on the dielectric layer  116 , such as using physical vapor deposition, chemical vapor deposition, electrical plating or conductive foil lamination. The conductive layer  118  may comprise a first conductive material, such as one or more of Cu, Al, Au, Ni, Ti, Ag, Sn, and metal alloy. An etching process may be subsequently applied to remove the first conductive material from surface of the thermal projection  102  resulting in a planar top surface of the conductive laser  118  and the thermal projection  102 . 
     As shown in  FIGS. 5A and 5B , at least two second trenches, such as  120 A and  120 B, may be formed. The second trenches  120 A and  120 B may extend from top surface of the conductive layer  118  to the top surface of the metal core substrate  100 . The second trenches may be formed, for example, by one of mechanical carving, mechanical punch, chemical etching and laser carving. 
     Referring to  FIGS. 6A and 6B , the second trenches  120 A and  120 B (shown in  FIGS. 5A and 5B ) may be at least partially or completely filled with a second conductive material to form conductive vias, such as  122 A and  122 B, such as by one of metal plating, metal sputtering deposition, and metal liquid deposition. Filing the second trenches may be followed by a polishing process, such as a chemical mechanical polishing process, resulting in a planar surface. The second conductive material may comprise at least one of Cu, Al, Au, Ni, Ti, Ag, Sn, and metal alloy. The second conductive material may be the same as the first conductive material, or different than the first conductive material. 
     To form circuit contacts, a process, such as mechanical carving, mechanical punch, chemical etching, or laser carving, may be applied to remove undesired material from the conductive layer  118 . For example, as shown in  FIGS. 7A and 7B , undesired material may be removed to form two spaces  124 A and  124 B. One space, for example, the space  124 A, may be formed on one side of the thermal projection  102 . The other space  124 B may be formed on the other side of the thermal projection  102 . As a result, circuit contacts, such as  126 A and  126 B are formed. Each circuit contact may be separated from the thermal projection  102  by a space such as circuit contact  126 A separated by space  124 A from thermal projection  102 . A light emitting diode package base  700 A and a light emitting diode package base  700 B may be achieved and are respectively illustrated in  FIGS. 7A and 7B . 
     In another embodiment, as illustrated in  FIG. 8A , a metal core substrate  200  is provided. The metal core substrate  200  may comprise a planar top surface  204  and a bottom surface  206 . As shown in  FIG. 8B , at least two first trenches, such as  208 A and  208 B, may be formed in metal are substrate  200  extending from the top surface  204  to the bottom surface  206 . The first trenches  208 A and  208 B may be formed, for example, by mechanical carving, mechanical punch, chemical etching, or laser carving. The metal core substrate  200  may be divided into three metal core portions, such as metal core portions  200 A,  200 B, and  200 C, by the first trenches  208 A and  208 B. As described above, two of the metal core portions, such as  200 A and  200 B, may serve as light emitting diode package electrodes. The metal core substrate  200  may comprise at least one of one of Cu, Al, Au, Ni, metal alloy, and graphite. 
     The first trenches  208 A and  208 B may be at least partially or completely filled with a first dielectric material to form dielectric isolations, such as  210 A and  210 B as shown in  FIGS. 9A and 9B . The first dielectric material may comprise, for example, at least one of epoxy, polymer resin, a pre-preg composite, Al 2 O 3 , AlN, and SiO 2 . In one embodiment, each of the dielectric isolations may have a surface planar to the top surface  204  of the metal core substrate  200 . For example, the dielectric isolation  210 A may have a surface  212 A planar to the top surface  204 , and the dielectric isolation  210 B may have a surface  212 B planar to the top surface  204 , as shown in  FIG. 9A . In another embodiment, the first dielectric material may be filled in the first trenches to form dielectric isolations  210 A and  210 B, and also applied to the top surface  204  of the metal core substrate  200  to form a first dielectric layer  214 , as shown in  FIG. 9B . The first dielectric layer  214  may comprise the same dielectric material as that of the dielectric isolations  210 A and  210 B. 
     A second dielectric layer may be applied to cover at least a portion of the dielectric isolations. For example, referring to  FIG. 10A , a second dielectric layer  216  may be applied to cover surfaces of the dielectric isolations  210 A and  210 B, and top surface  204  (shown in  FIG. 9A ) of the metal core substrate  200 . In another embodiment as shown in  FIG. 10B , the second dielectric layer  216  may be applied and formed on the first dielectric layer  214 . The second dielectric layer  216  may comprise a second dielectric material. The second dielectric material may be the same as the first dielectric material, or different than the first dielectric material. A conductive layer  218  is then formed on the second dielectric layer  216 , as shown in  FIGS. 10A and 10B . The conductive layer  218  may comprise a first conductive material, such as at least one of Cu, Al, Au, Ni, Ti, Ag, Sn, and metal alloy. 
     A plurality of second trenches, such as  220 A,  220 B, and  220 C, are then formed to extend from top surface of the conductive layer  218  to the top surface of the metal core substrate  200 . The second trenches  220 A,  220 B, and  220 C may be formed, for example, by one of mechanical carving, mechanical punch, chemical etching, and laser carving. In one embodiment illustrated by  FIG. 11A , the second trenches  220 A,  220 B, and  220 C may extend through the conductive layer  218  and the dielectric layer  216  to the top surface of the metal core substrate  200 . In another embodiment illustrated by  FIG. 11B , the second trenches  220 A,  220 B, and  220 C may extend through the conductive layer  218 , the second dielectric layer  216 , and the first dielectric layer  214  to the top surface of the metal core substrate  200 . 
     Some of the second trenches, such as the second trenches  220 A and  220 B may then be at least partially or completely filled with a second conductive material to form conductive vias  222 A and  222 B, shown in  FIGS. 12A and 12B . At least one of the second trenches, such as the second trench  220 C (shown in  FIGS. 11A and 11B ) may be filled with a thermal conductive material to form a thermal projection  202 . The second conductive material may comprise, for example, at least one of Cu, Al, Au, Ni, Ti, Ag, Sn, and metal alloy. The thermal conductive material may comprise, for example, at least one of Ag, Cu, Au, Sn, Ni, and Al. The second trenches, such as  220 A,  220 B, and  220 C, may be filled, for example, by applying one of metal plating, metal sputtering deposition, and metal liquid deposition processes. 
     Similar to the above description of  FIGS. 7A and 7B , a process, such as mechanical carving, mechanical punch, chemical etching, or laser carving, may be applied to remove undesired material from the conductive layer  218  to form circuit contacts. For example, as shown in  FIGS. 13A and 13B , undesired material may be removed form two spaces  224 A and  224 B. One space, for example the space  224 A, may be formed on one side of the thermal projection  202 . The other space  224 B may be formed on the other side of the thermal projection  202 . As a result, circuit contacts, such as  226 A and  226 B, are formed. Each circuit contact may be separated from the thermal projection  202  by a space, such as spaces  224 A and  224 B. A light emitting diode package base  1300 A and a light emitting diode package base  1300 B may be obtained and are respectively illustrated in  FIGS. 13A and 13B . 
       FIG. 14  illustrates a cross-sectional view of light emitting diode package base  700 A assembled with a light emitting diode chip structure  1400  according to some example embodiments of the present invention. The light emitting diode chip  1400  may also be assembled with one of the light emitting diode package bases  700 B,  1300 A, and/or  1300 B described above. The light emitting diode chip structure  1400  may comprise a light emitting diode chip substrate  1402 , a thermal pad  1404  on a passivation layer  1406  and contact pads  1408 A,  1408 B. When assembled, contact pads  1408 A and  1408 B of the light emitting diode chip structure  1400  may be electrically coupled to circuit contacts, such as  126 A and  126 B respectively (where  126   a  and  126   b  are portions of the conductive layer  118 ), through bonding material  1502 A and  1502 B. The thermal pad  1404  may be thermally coupled to the thermal projection  102  through bonding material  1502 C. 
     In operation, the contact pad  1406 A may electrically couple to the metal core portion  100 A through circuit contact  126 A and conductive via  122 A. Similarly, the contact pad  1406 B may electrically couple to the metal core portion  100 B through circuit contact  126 B and conductive via  122 B. 
     Many modifications and other example embodiments set forth herein will come to mind to one skilled in the art to which these example embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the embodiments are not to be limited to the specific ones disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing descriptions and the associated drawings describe example embodiments in the context of certain example combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and/or functions other than those explicitly described above are also contemplated as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.