Abstract:
A shift register and a shift register unit for diminishing clock coupling effect are introduced herein. Each stage shift register unit includes at least one pull-up driving module, a pull-up module, at least one pull-down module and a pull-down driving module. Before a waveform of either a first clock signal or a second clock signal employed by the pull-up module transits into a rising edge, the pull-down driving module employs a first periodic signal to turn on the pull-down module in advance for a specific period, and/or before the waveform of the first or second clock signal employed by the pull-up module transits into a falling edge, the pull-down driving module employs a second periodic signal to turn off the pull-down module in advance for a specific period. Accordingly, the pull-down module can gain a sufficient capability against the clock coupling effect so as to optimize the waveform outputted from the shift register unit.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a shift register and a shift register unit, and more particularly to a shift register and a shift register unit used for diminishing clock coupling effect. 
         [0003]    2. Description of the Prior Art 
         [0004]    Conventional liquid crystal display (LCD) utilizes a set of driving circuits for controlling gray signal outputs of a plurality of pixel units located in a LCD panel. The driving circuits further include a gate driver electrically connected with transverse scan lines (or gate lines) in turn each for outputting a gate pulse signal to each corresponding pixel unit, and a source driver electrically connected with longitudinal data lines (or source lines) each for transmitting a data signal to each corresponding pixel unit  20  separately. Each of the intersections between the transverse scan lines and longitudinal data lines is electrically connected with two terminals of an active component (such as a transistor having a gate and a source) corresponding to the pixel unit. At the same time when the gate driver outputs gate pulse signals in turn via the scan lines to turn on the transistor of each pixel unit, the source driver outputs corresponding data signals via the data lines to charge a capacitor of each pixel unit to reach a required voltage level so as to display various gray levels. 
         [0005]    To lower chip expense of the gate driver, the conventional Thin-Film Transistor LCD (TFT-LCD) panel based on such as a Low Temperature Poly-Silicon (LTPS) process technique adopts an integrated gate driver module design, by way of relocating a shift register from the existing gate driver chip to the glass substrate, to constitute cascaded multi-stage shift register modules as implementing “Gate on Array (GOA)”. This functions as same as the shift register did in the original gate driver. Because the LTPS-based panel mostly adopts Poly-Silicon transistors, the Poly-Silicon transistors have a mobility of over two-hundred multiple than that of amorphous-Si transistors. However, for the same reason as reducing the panel cost, the a-Si process with a very low mobility also realize such a circuit design on its glass substrate, gradually. 
         [0006]    Presently, a shift register design adopted by the most conventional integrated gate driver modules is disposed with a pull-down module or the likes to prevent the gate pulse signal output of the shift register from distortions invoked by pull up of other signals. Such a pull-down module is mostly driven by a clock signal (CK) or an inverted clock signal (XCK). Please refer to  FIG. 1A , which is illustrated with a schematic circuitry diagram of the Nth stage shift register  210  as disclosed in U.S. Pat. No. 7,310,402 B2. In the Nth stage shift register  210 , all of a pull-up transistor Q 2  and two pull-down modules  1  and  2  employ a first clock signal (CK 1 ). Although a prefect waveform of an ideal first clock signal (CK 1 -ideal) is introduced in  FIG. 1B , the first clock signal (CK 1 ) is inevitably involved with a coupling effect of a capacitor inhering between both of the drain and gate of the pull-up transistor Q 2  under an actual operation and therefore transforms into a waveform of a real first clock signal (CK 1 -real), as depicted in FIG.  1 C., with a curved edge “E 1 ” representing a slower rising velocity. This would cause periodic occurrences of a plurality of upward spikes “B 1 ” on waveform output (Out) of the gate pulse signal as depicted in  FIG. 1D . Simultaneously, with involvement of driving the pull-down modules  1  and  2  in delays by the first clock signal (CK 1 ), a signal level of either an output node (P 8 ) or an input node (P 2 ) of a pull-up module containing the pull-up transistor of Q 2  also would not be timely pulled down and therefore provides a poor pull-down performance. Besides, an ideal second clock signal (CK 2 -ideal) as depicted in  FIG. 1E  employed by the pull down module  2  also is transformed into a real second clock signal (CK 2 -real) as depicted in  FIG. 1F , based on the same coupling effect as occurring in the first clock signal (CK 1 ), with the curved edge “E 1 ” representing a slower rising velocity. This causes periodic occurrences of a plurality of downward spikes “B 2 ” on the waveform output (Out) of the gate pulse signal as depicted in  FIG. 1D . 
         [0007]    Hence, it is a significant topic of how to deal with such a problem. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    To resolve the abovementioned drawbacks, a primary object of the present invention is to provide a shift register and a shift register unit used for diminishing clock coupling effect, which employ other periodic signals for driving a pull-down module and thereby provide the pull-down module with a capability of sufficiently resisting the clock coupling effect occurring in clock signal, so as to optimize waveform output of the shift register. 
         [0009]    To accomplish the above invention object, a shift register according to the present invention comprises a plurality of odd-stage shift register units and a plurality of even-stage shift register units. Each of the shift register units has at least one pull-up driving module, a pull-up module, at least one pull-down module and a pull-down driving module. 
         [0010]    The pull-up driving module provides a driving signal according to a pulse signal. The pull-up module outputs an output signal according to one of a first signal and a second signal as long as triggered by the driving signal to be electrically conductive. The pull-down module provides the pull-up module with a first source voltage. The pull-down driving module is based on a third signal to turn on the pull-down module in advance for a specific period before a waveform of either the first signal or the second signal transits into a rising edge, and/or the pull-down driving module is based on a fourth signal to turn off the pull-down module in advance for a specific period before the waveform of either the first signal or second signal transits into a falling edge. 
         [0011]    In an embodiment according to the present invention, for the odd-stage shift register units the first signal is designated into a first clock signal, the second signal is designated into a second clock signal which is inverted with relative to the first clock signal, the third signal is designated into a first periodic signal and the fourth signal is designated into a second periodic signal which is inverted with relative to the first periodic signal. The odd-stage shift register units, at least one of which utilizes the pull-up driving module to turn on the pull-up module based on a setting signal generated from the previous odd-stage shift register unit or an initial setting signal so that the turned-on pull-up module of the odd-stage shift register unit generates a pulse signal for the pull-up driving module of the next odd-stage shift register unit. Furthermore, the pull-up driving module of the odd-stage shift register unit connects the first source voltage to turn off the pull-up module of the odd-stage shift register unit, based on a setting signal generated from the next odd-stage shift register unit. 
         [0012]    For the even-stage shift register units, the first signal is designated into the first periodic signal, the second signal is designated into the second periodic signal, the third signal is designated into the first clock signal and the fourth signal is designated into the second clock signal. At least one of the even-stage shift register units utilizes the pull-up driving module to provide the driving signal to turn on the pull-up module based on a setting signal generated from the previous even-stage shift register unit or an initial setting signal so that the turned-on pull-up module of the even-stage shift register unit generates a pulse signal for the pull-up driving module of the next even-stage shift register unit, and utilizes the pull-up driving module of the even-stage shift register unit to connect the first source voltage to turn off the pull-up module of the even-stage shift register unit, based on a setting signal generated from the next even-stage shift register unit. 
         [0013]    In the embodiment, a waveform of the first periodic signal is maintained ahead of a waveform of the first clock signal in a phase shift less than 180 degree, and a waveform of the second periodic signal is maintained to lag behind a waveform of the first clock signal in a phase shift less than 180 degree. In another embodiment, a crest width of the waveform of the first periodic signal is smaller than a trough width of the waveform of the second periodic signal, and a crest width of the waveform of the first clock signal is smaller than a trough width of the waveform of the second clock signal, or each of the waveforms of the first periodic signal, second periodic signal, the first clock signal and the second clock signal has a trough width and a crest width smaller than the trough width. 
         [0014]    In another embodiment, each of the pull-down driving modules of the shift register unit can be changed to connect with a second source voltage having a level lower than that of the first source voltage, and thereby timely turn off the corresponding pull-down modules. 
         [0015]    In another embodiment, before the first clock signal transits from a low level to a high level, a capacitor is used to pre-maintain the second periodic signal at the high level which can turn on the pull-down module, and thereby can resist the coupling effect. 
         [0016]    The advantages and novel features of the invention will become more apparent from the following detailed description of a preferred embodiment when taken in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The present invention may best be understood through the following description with reference to the accompanying drawings, in which: 
           [0018]      FIG. 1A  illustrates a schematic circuitry diagram of a conventional shift register; 
           [0019]      FIG. 1B  to  FIG. 1F  illustrate various signal waveforms of the conventional shift register as shown in  FIG. 1A , which respectively depict an ideal first clock signal, a real first clock signal, a output signal, an ideal second clock signal and an real second clock signal; 
           [0020]      FIG. 2  illustrates an architecture diagram of a shift register according to a first preferred embodiment of the present invention; 
           [0021]      FIG. 3A  illustrates a schematic circuitry diagram of each of shift register units in the shift register of the according to the first preferred embodiment of the present invention; 
           [0022]      FIG. 3B  illustrates a schematic circuitry diagram of each of shift register units in the shift register according to a second preferred embodiment of the present invention; 
           [0023]      FIG. 3C  illustrates a schematic circuitry diagram of each of shift register units in the shift register according to a third preferred embodiment of the present invention; 
           [0024]      FIG. 4A  to  FIG. 4E  illustrate various signal waveforms of the shift register unit according to the first preferred embodiment of the present invention, which respectively depict a first periodic signal, a second periodic signal, a first clock signal, a second clock signal and a setting signal generated from the previous stage shift register unit; 
           [0025]      FIG. 5  illustrates a signal-simulated coordinate diagram of the third shift register unit according to the first preferred embodiment of the present invention, which respectively depict waveforms of a second periodic signal, a first clock signal, an output signal and an input signal; 
           [0026]      FIG. 6A  to  FIG. 6H  illustrate various signal waveforms of the shift register unit according to the second preferred embodiment of the present invention, which respectively depict a first periodic signal, a second periodic signal, a first clock signal, a second clock signal, a setting signal generated from the previous stage shift register unit, an input signal and several signals of various nodes; 
           [0027]      FIG. 7A  to  FIG. 7H  illustrate various signal waveforms of the shift register unit according to the third preferred embodiment of the present invention, which respectively depict a first periodic signal, a second periodic signal, a first clock signal, a second clock signal, a setting signal generated from the previous stage shift register unit, several signals of various nodes and an input signal generated from the previous stage shift register unit; and 
           [0028]      FIG. 8  illustrates a signal-simulated coordinate diagram of the third shift register unit according to the third preferred embodiment of the present invention, which respectively depict waveforms of a second periodic signal, a first clock signal, an output signal and an input signal. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0029]    Firstly referring to illustration of  FIG. 2 , a shift register  200  according to a first prefer embodiment of the present invention is introduced herein, which includes a plurality of odd-stage cascaded shift register units  203   a  (e.g. GOA 1 , GOA 3 , GOA 5 . GOA N ) and a plurality of even-stage cascaded shift register units  203   a  (e.g. GOA 2 , GOA 4 , GOA 6  . . . GOA N+1 ). Those even-stage and odd-even shift register units  203   a  are used to output their gate pulse signals (OUT 1 , OUT 2 , . . . OUT N+1 ) in turns via a plurality of corresponding gate lines or scan lines to trigger gates of thin film transistors (TFTs) intersected between the gate lines and data lines disposed on matrix pixels  220  of a liquid crystal display (LCD) panel and thereby store several gray data transmitted from the data lines of the LCD panel. 
         [0030]    In the odd-stage cascaded shift register units  203   a  (e.g. GOA 1 , GOA 3 , GOA 5  . . . GOA N ), except that the first stage shift register unit  203   a  (e.g. GOA 1 ) generates its first gate pulse signal (OUT 1 ) based on an initial setting signal (STO), each of the other odd-stage shift register units  203   a  (e.g. GOA 3 , GOA 5  . . . GOA N ) generates the gate pulse signal based on a setting signal generated from a previous odd-stage shift register unit. For example, as shown in  FIG. 2 , the third shift register unit  203   a  (e.g. GOA 3 ) is based on a first setting signal (ST 1 ) generated from the first shift register unit  203   a  (e.g. GOA 1 ) to output its third gate pulse signal (OUT 3 ). Likewise, in the even-stage cascaded shift register units  203   a  (e.g. GOA 2 , GOA 4 , GOA 6  . . . GOA N+1 ), except that the second stage shift register unit  203   a  (e.g. GOA 2 ) generates its second gate pulse signal (OUT 2 ) based on another initial setting signal (STE), each of the other even-stage shift register units  203   a  (e.g. GOA 4 , GOA 6  . . . GOA N+1 ) generates the gate pulse signal based on a setting signal generated from a previous even-stage shift register unit. For example, as shown in  FIG. 2 , the fourth shift register unit  203   a  (e.g. GOA 4 ) is based on a second setting signal (ST 2 ) generated from the second shift register unit  203   a  (e.g. GOA 2 ) to output its fourth gate pulse signal (OUT 4 ). 
         [0031]    Each of the shift register units  203   a  (e.g. GOA 1 , GOA 2 , GOA 3  . . . GOA N+1 ) is electrically connected with all of a first clock signal (CKO), a second clock signal (XCKO), a first periodic signal (CKE) and a second periodic signal (XCKE) but different connecting locations thereamong in compliance with difference between the odd and even stages (detailed later), wherein the first clock signal (CKO) reveals an inverted phase relative to the second clock signal (XCKO), and the first periodic signal (CKE) reveals an inverted phase relative to the second periodic signal (XCKE). 
         [0032]    Please further refer to  FIGS. 2 and 3A  which illustrates a schematic circuitry diagram of each of the shift register units  203   a  of the shift register  200 . Each of the shift register units  203   a  primarily comprises a first pull-up driving module  300   a , a second pull-up driving module  300   b , a pull-up module  310 , a first pull-down module  320   a , a second pull-down module  320   b , a first pull-down driving module  330   a  and a second pull-down driving module  330   b . In the stage shift register unit  203   a , the first pull-up driving module  300   a  comprises a first transistor (T 1 ) having a drain and a gate both jointed to a pulse signal, such as a setting signal (STN−1) generated from the previous stage shift register unit  203   a  or an initial setting signal (i.e. STO or STE). In an exemplar of odd stage, the first pull-up driving module  300   a  of the third stage shift register unit  203   a  is based on a setting signal (ST 1 ) generated from the first stage shift register unit  203   a  or an initial setting signal (STO) to provide a driving signal to turn on the pull-up module  310  of the third stage shift register unit  203   a . Then the turned-on pull-up module  310  of the third stage shift register unit  203   a  generates a setting signal STN (e.g. ST 3 ) via an output point to the first pull-up driving module  300   a  of the fifth stage shift register unit  203   a  next to the third stage shift register unit  203   a . The second pull-up driving module  300   b  of the third stage shift register unit  203   a  connects a first source voltage (VSS 1 ) to turn off the pull-up module  310  of the third stage shift register unit, based on a setting signal (i.e. ST 5 ) generated from the fifth stage shift register unit  203   a . In an exemplar of even stage, the first pull-up driving module  300   a  of the fourth stage shift register unit  203   a  is based on a setting signal (ST 2 ) generated from the second stage shift register unit  203   a  or an initial setting signal (STE) to provide a driving signal to turn on the pull-up module  310  of the fourth stage shift register unit  203   a . Then the turned-on pull-up module  310  of the fourth stage shift register unit  203   a  generates a setting signal STN (e.g. ST 4 ) via an output point to the first pull-up driving module  300   a  of the sixth stage shift register unit  203   a  next to the fourth stage shift register unit  203   a . The second pull-up driving module  300   b  of the fourth stage shift register unit connects the first source voltage (VSS 1 ) to turn off the pull-up module  310  of the fourth stage shift register unit, based on a setting signal (i.e. ST 6 ) generated from the sixth stage shift register unit  203   a.    
         [0033]    In each of the shift register units  203   a  as shown in  FIG. 3A , the pull-up module  310  has a second transistor (T 2 ), a third transistor (T 3 ), an input node (Q) and an output node (OUT). The second transistor (T 2 ) has a drain connected with one of a first signal (CK) and a second signal (XCK) (but only connected with the first signal (CK) in this embodiment), a gate connected with the input node (Q) of the pull-up module  310  for connecting to the driving signal, and a source connected with the output node (OUT) for generating an output signal as gate pulse signal (OUT 1 ˜OUT N+1 ). The third transistor (T 3 ) has a drain connected with one of the first and second signals (CK and XCK), a gate connected with the input node (Q) of the pull-up module  310  for further connecting to the driving signal, and a source connected with the output point for generating the setting signal (STN) to the next stage shift register unit  203   a . The input node (Q) is connected with a source of the first transistor (T 1 ) of the first pull-up driving module  300   a  for further connecting the driving signal to the gates of both of the second and third transistors (T 2  and T 3 ). The output node (OUT) is used for outputting said gate pulse signal (OUT 1 ˜OUT N+1 ). 
         [0034]    In operation, when the first transistor (T 1 ) of the first pull-up driving module  300   a  is turned on via the drain and gate thereof by a specific level of the setting signal (i.e. STN−1), the source of the first transistor (T 1 ) generates the driving signal via the input node (Q) to trigger the gates of both of the second and third transistors (T 2  and T 3 ) of the pull-up module  310  so that the second transistor (T 2 ) is turned on and based on a specific level of the first signal (CK) to output its gate pulse signal (OUT 1 ˜OUT N+1 ), and the third transistor (T 3 ) is turned on and generates the output signal serving as the setting signal (STN) via the output point to the next stage shift register unit  203   a.    
         [0035]    In each of the shift register units  203   a  as shown in  FIG. 3A , the first pull-down driving module  330   a  further comprises a fourth transistor (T 4 ) and a fifth transistor (T 5 ). The fourth transistor (T 4 ) has a drain and a gate both jointed to a third signal (P_CK). The fifth transistor (T 5 ) has a drain connected with a source of the fourth transistor (T 4 ), a gate connected with a fourth signal (P_-XCK), and a source connected with the first source voltage (VSS 1 ). 
         [0036]    In each of the shift register units  203   a  as shown in  FIG. 3A , the first pull-down module  320   a  has a first input node (K), a sixth transistor (T 6 ), a seventh transistor (T 7 ) and an eighth transistor (T 8 ). The first input node (K) is connected with both the source of the fourth transistor (T 4 ) and the drain of the fifth transistor (T 5 ). The sixth transistor (T 6 ) has a drain connected with the input node (Q) of the pull-up module  310 , a gate connected with the first input node (K), and a source connected with the first source voltage (VSS 1 ). The seventh transistor (T 7 ) has a drain connected with the setting signal (STN) via the output point to the next stage shift register unit  203   a , a gate connected with the first input node (K) of the first pull-down module  320   a , and a source connected with the first source voltage (VSS 1 ). The eighth transistor (T 8 ) has a drain connected with the output node (OUT) of the pull-up module  310 , a gate connected with the first input node (K), and a source connected with the first source voltage (VSS 1 ). 
         [0037]    In operation, after the fourth transistor (T 4 ) of the first pull-down driving module  330   a  is turned on by a specific high level (i.e. Vh) of the third signal (P_CK), all of the sixth transistor (T 6 ), the seventh transistor (T 7 ) and the eighth transistor (T 8 ) of the first pull-down module  320   a  are therefore triggered via the first input node (K) to provide the first source voltage (VSS 1 ) respectively for the output node (OUT), the input node (Q) and the output point of setting signal (STN) of the pull-up module  310 . Due to a low level of the first source voltage (VSS 1 ), the signal levels of the output node (OUT), the input node (Q) and the output point of the pull-up module  310  are pulled down. On the opposite, the fourth transistor (T 4 ) can not be turned on by the third signal (P_CK) having an inverted phase relative to the fourth signal (P_XCK) after the fifth transistor (T 5 ) of the first pull-down driving module  330   a  is turned on by a specific high level of the fourth signal (P_XCK). The turned-on fifth transistor (T 5 ) provides the first source voltage (VSS 1 ) via the first input node (K) to the gates of all of the sixth transistor (T 6 ), the seventh transistor (T 7 ) and the eighth transistor (T 8 ) of the first pull-down module  320   a  so that the sixth transistor (T 6 ), the seventh transistor (T 7 ) and the eighth transistor (T 8 ) all can not be turned on. 
         [0038]    In each of the shift register units  203   a  as shown in  FIG. 3A , the second pull-down driving module  330   b  further comprises a ninth transistor (T 9 ), a tenth transistor (T 10 ), an eleventh transistor (T 11 ) and a twelveth transistor (T 12 ). The ninth transistor (T 9 ) has a drain connected with the first input node (K) of the first pull-down module  320   a , a gate connected with the output node (Q) of the pull-up module  310 , and a source connected with the first source voltage (VSS 1 ). The tenth transistor (T 10 ) has a gate connected with the input node (Q) of the pull-up module  310  and a source connected with the first source voltage (VSS 1 ). The eleventh transistor (T 11 ) has a drain and a gate both jointed to the fourth signal (P_XCK). The twelveth transistor (T 12 ) has a drain connected with both of a source of the eleventh transistor (T 11 ) and a drain of the tenth transistor (T 10 ), a gate connected with the third signal (P_CK), and a source connected with the first source voltage (VSS 1 ). 
         [0039]    In each of the shift register units  203   a  as shown in  FIG. 3A , the second pull-down module  320   b  further comprises a second input node (P), a thirteenth transistor (T 13 ), a fourteenth transistor (T 14 ) and a fifteenth transistor (T 15 ). The second input node (P) is electrically connected with the drain of the tenth transistor (T 10 ), the source of the eleventh transistor (T 11 ) and the drain of the twelveth transistor (T 12 ), respectively. The thirteenth transistor (T 13 ) has a drain connected with the input node (Q) of the pull-up module  310 , a gate connected with the second input node (P), the source of the eleventh transistor (T 11 ) and the drain of the twelveth transistor (T 12 ) of the second pull-down driving module  330   b , and a source connected with the first source voltage (VSS 1 ). The fourteenth transistor (T 14 ) has a drain connected with the setting signal (STN) via the output point of the pull-up module  310  to the next stage shift register unit, a gate connected with the second input node (P), and a source connected with the first source voltage (VSS 1 ). The fifteenth transistor (T 15 ) has a drain connected with the output node (OUT) of the pull-up module  310 , a gate connected with the second input node (P), and a source connected with the first source voltage (VSS 1 ). 
         [0040]    In operation, after the eleventh transistor (T 11 ) of the second pull-down driving module  330   b  is turned on by a specific high level (i.e. Vh) of the fourth signal (P_XCK), all of the thirteenth transistor (T 13 ), the fourteenth transistor (T 14 ) and the fifteenth transistor (T 15 ) of the second pull-down module  320   b  are therefore triggered via the second input node (P) to provide the first source voltage (VSS 1 ) respectively for the output node (OUT), the input node (Q) and the output point of setting signal (STN) of the pull-up module  310 . Due to the low level of the first source voltage (VSS 1 ), the signal levels of the output node (OUT), the input node (Q) and the output point of the pull-up module  310  are pulled down. On the opposite, the eleventh transistor (T 11 ) of the second pull-down driving module  330   b  can not be turned on by the fourth signal (P_XCK) having an inverted phase relative to the third signal (P_CK) after the twelveth transistor (T 12 ) of the second pull-down driving module  330   b  is turned on by a specific high level of the third signal (P_CK). The turned-on twelveth transistor (T 12 ) provides the first source voltage (VSS 1 ) via the second input node (P) to the gates of all of the thirteenth transistor (T 13 ), the fourteenth transistor (T 14 ) and the fifteenth transistor (T 15 ) of the second pull-down module  320   b  so that the thirteenth transistor (T 13 ), the fourteenth transistor (T 14 ) and the fifteenth transistor (T 15 ) all can not be turned on. When the signal of the input node (Q) of the pull-up module  310  reaches a high level to trigger the gates of the ninth transistor (T 9 ) of the second pull-down driving module  330   b , the first source voltage (VSS 1 ) is connected to the gates of several transistors disposed in both of the first and second pull-down module  320   a ,  320   b  as so to turn off the first and second pull-down module  320   a ,  320   b  and avoid pulling down the signal levels of the output node (OUT), the input node (Q) and the output point of the pull-up module  310 . 
         [0041]    In each of the shift register units  203   a  as shown in  FIG. 3A , the second pull-up driving module  300   b  comprises a sixteenth transistor (T 16 ) and a seventeenth transistor (T 17 ). The sixteenth transistor (T 16 ) has a drain connected with the input node (Q) of the pull-up module  310  and the gates of both of the second and third transistors (T 2 ), (T 3 ), a gate connected with the setting signal (STN+1) generated from the next stage shift register unit  203   a  via an input point, and a source connected with the first source voltage (VSS 1 ). The seventeenth transistor (T 17 ) has a drain connected with the output node (OUT) of the pull-up module  310 , a gate connected with the setting signal (STN+1) generated from the next stage shift register unit  203   a  via the input point, and a source connected with the first source voltage (VSS 1 ). 
         [0042]    To sufficiently resist clock coupling effect, it has to be ensured that the signal level output from the pull-up module  310  is timely pulled down to acquire an optimal waveform output of the gate pulse signal. Differently from the prior art whose two clock signals (e.g. CK and XCK) use respective 50% of each duty cycle to drive its pull-down driving circuit, the third signal (P_CK) and the fourth signal (P_XCK) of the present invention respectively use different percentages of each duty cycle to drive the first and second pull-down driving modules  330   a ,  330   b , wherein a waveform of the third signal (P_CK) is maintained ahead of a waveform of the first signal (CK) or the second signal (XCK) in a phase shift less than 180 degree, and a waveform of the fourth signal (P_XCK) is maintained to lag behind the waveform of the first signal (CK) or the second signal (XCK) in a phase shift less than 180 degree, or the waveform of the fourth signal (P_XCK) is maintained ahead of the waveform of the first signal (CK) or the second signal (XCK) in a phase shift less than 180 degree, and the waveform the third signal (P_CK) of is maintained to lag behind the waveform of the first signal (CK) or the second signal (XCK) in a phase shift less than 180 degree. 
         [0043]    With utilization of the waveform of the third signal (P_CK) or the fourth signal (P_XCK) maintaining ahead of or lagging behind the waveform of the first signal (CK) or the second signal (XCK) in a phase shift less than 180 degree, the drawback of the prior art that a signal intensity of driving the pull-down driving circuit is insufficient can be overcome. For example, the fourth transistor (T 4 ) of the first pull-down driving module  330   a  is based on a specific high level (i.e. Vh) of the third signal (P_CK) to trigger the gates of the sixth, seventh and eighth transistors (T 6 ), (T 7 ), (T 8 ) of the first pull-down module  320   a  as turning on the first pull-down module  320   a  in advance for a specific period before the waveform of the first signal (CK) (or the second signal (XCK)) employed by the pull-up module  310  transits into a rising edge from a low level to a high level. This can ensure that the signal waveforms of the output node (OUT), the input node (Q) and the output point of setting signal (STN) of the pull-up module  310  all reach a pulled-down level for the specific period. For the same period, the twelveth transistor (T 12 ) of the second pull-down driving module  330   b  is also based on the specific high level (i.e. Vh) of the third signal (P_CK) to connect the first source voltage (VSS 1 ) to the gates of the thirteenth, fourteenth and fifteenth transistors (T 13 ), (T 14 ), (T 15 ) of the second pull-down module  320   b  as turning off the second pull-down module  320   b . Oppositely, the fifth transistor (T 5 ) of the first pull-down driving module  330   a  is based on a specific high level (i.e. Vh) of the fourth signal (P_XCK) to connect the first source voltage (VSS 1 ) to the gates of the sixth, seventh and eighth transistors (T 6 ), (T 7 ), (T 8 ) of the first pull-down module  320   a  as turning off the first pull-down module  320   a  in advance for a specific period before the waveform of the first signal (CK) (or the second signal (XCK)) employed by the pull-up module  310  transits into a falling edge from a high level to a low level. For the same period, the eleventh transistor (T 11 ) of the second pull-down driving module  330   b  is also based on the specific high level (i.e. Vh) of the fourth signal (P_XCK) to trigger the gates of the thirteenth, fourteenth and fifteenth transistors (T 13 ), (T 14 ), (T 15 ) of the second pull-down module  320   b  as turning on the second pull-down module  320   b . This can ensure that the signal waveforms of the output node (OUT), the input node (Q) and the output point of setting signal (STN) of the pull-up module  310  all reach a pulled-down level for the specific period. 
         [0044]    Turning to  FIG. 2 , the plurality of odd-sage shift register units (e.g. GOA 1 , GOA 3 , GOA 5  . . . GOA N ) and the plurality of even-sage shift register units (e.g. GOA 2 , GOA 4 , GOA 6  . . . GOA N+1 ) of the shift register  200  according to the present invention are respectively connected with a first clock signal (CKO), a second clock signal (XCKO) inverted relative to the first clock signal (CKO), a first periodic signal (CKE) and a second periodic signal (XCKE) inverted relative to the first periodic signal (CKE) for driving. As shown in  FIG. 3A , in each of the odd-stage shift register units of this embodiment, the first signal (CK) is designated into the first clock signal (CKO), the second signal (XCK) is designated into the second clock signal (XCKO), the third signal (P_CK) is designated into the first periodic signal (CKE) and the fourth signal (P_XCK) is designated into the second periodic signal (XCKE); oppositely, in each of the even-stage shift register units of this embodiment, the first signal (CK) is designated into the first periodic signal (CKE), the second signal (XCK) is designated into the second periodic signal (XCKE), the third signal (P_CK) is designated into the first clock signal (CKO) and the fourth signal (P_XCK) is designated into the second clock signal (XCKO), wherein there are fixed phase shifts predetermined among the first periodic signal (CKE), the second periodic signal (XCKE), the first clock signal (CKO) and the second clock signal (XCKO). For example, as shown in  FIG. 4A  to  FIG. 4E , waveforms of various signals employed by the shift register unit  203   a  according to the first preferred embodiment of the present invention are respectively depicted, which includes the first periodic signal (CKE), the second periodic signal (XCKE), the first clock signal (CKO), the second clock signal (XCKO) and a setting signal (STN−1) generated from the previous stage shift register unit  203   a . Under presetting, the waveform of the second periodic signal (XCKE) is always maintained ahead of a rising edge (E 1 ) of the waveform of the first clock signal (CKO) in a phase shift (P 1 ) less than 180 degree, and the waveform of the first periodic signal (CKE) is always maintained to lag behind a falling edge (E 2 ) of the waveform of the first clock signal (CKO) in a phase shift (P 2 ) less than 180 degree. To acquire an optimal pulled-down waveform of the gate pulse signal outputted from the output node (OUT), a crest width of the waveform of the first periodic signal (CKE) can be preset smaller than a trough width of the waveform of the second periodic signal (XCKE), and a crest width of the waveform of the first clock signal (CKO) can be preset smaller than a trough width of the waveform of the second clock signal (XCKO), or each of the waveforms of the first periodic signal (CKE), the second periodic signal (XCKE), the first clock signal (CKO) and the second clock signal (XCKO) has a crest width (W 1 ) and a trough width (W 2 ) wherein the crest width (W 1 ) can be preset smaller than the trough width (W 2 ). In another exemplar, the crest and trough (or High/Low) of the waveform of each of the first periodic signal (CKE), the second periodic signal (XCKE), the first clock signal (CKO) and the second clock signal (XCKO) can be preset to respectively use 45% and 55% of each duty cycle. By the crest and trough of the signal waveform using 45% and 55% of each duty cycle,  FIG. 5  illustrates a signal-simulated coordinate diagram with a horizontal axis representative of time (S) and a vertical axis representative of voltage (V), which respectively simulates waveforms of the second periodic signal (XCKE), the first clock signal (CKO), the output signal of the output node (OUT 3 ) and the input signal of the input node (Q 3 ) of the pull-up module  310  in the third stage shift register unit  203   a  according to the first preferred embodiment of the present invention. As shown in  FIG. 5 , when the second periodic signal (XCKE) is maintained ahead of the first clock signal (CKO) in a phase shift less than 180 degree, it is acquired that the third stage shift register unit  203   a  can generate an optimal output signal waveform of the output node (OUT 3 ) and an optimal rising and falling edges of the input signal waveform of the input node (Q 3 ) and therefore its clock coupling effect can be completely diminished. 
         [0045]    It notes that the first and second periodic signals (CKE), (XCKE) do not need to be limited in a clock type but can be implemented with any signal source which can be controlled to have a specific phase shift relative to the first and second clock signals (CKO), (XCKO). 
         [0046]    Further referring to illustration of  FIG. 3B , a shift register unit  203   b  according to a second prefer embodiment of the present invention is introduced herein. The shift register unit  203   b  can be one of the odd-stage cascaded shift register unit (e.g. GOA 1 , GOA 3 , GOA 5  . . . GOA N ) and the even-stage cascaded shift register units (e.g. GOA 2 , GOA 4 , GOA 6  . . . GOA N+1 ), as the same as shown in  FIG. 2 . Differences from the shift register unit  203   a  of the first embodiment is that in the shift register unit  203   b  of the second prefer embodiment, the source of the fifth transistor (T 5 ) of the first pull-down driving module  330   a  is connected to a second source voltage (VSS 2 ), and the sources of all the ninth transistor (T 9 ), the tenth transistor (T 10 ) and the twelveth transistor (T 12 ) of the second pull-down driving module  330   b  are also connected to the second source voltage (VSS 2 ). By the level of the second source voltage (VSS 2 ) (i.e. −10V to −15V) lower than that of the first source voltage (VSS 1 ) (i.e. −6V to 0V), the various transistors (T 6 ), (T 7 ), (T 8 ) of the first pull-down module  330   a  and various transistors (T 13 ), (T 14 ), (T 15 ) of the second pull-down module  330   b  can be turned off, timely. Hereinafter does not repeat where the rest of the shift register unit  203   b  of the second prefer embodiment is the same as the shift register unit  203   a  of the first embodiment. 
         [0047]    Further referring to  FIG. 6A  to  FIG. 6H , which illustrate various signal waveforms of the shift register unit  203   b  according to the second embodiment of the present invention, which depict the lowest level of each of the first clock signal (CKO), the second clock signal (XCKO) and a setting signal (STN−1) generated from the previous stage shift register unit  203   b  and an input signal of the input node (Q) of the shift register unit  203   b  is the same as the level of the first source voltage (VSS 1 ), but the lowest level of each of the first periodic signal (CKE), the second periodic signal (XCKE), the signal of the first input node (K) of the first pull-down module  320   a  and the signal of the second input node (P) of the second pull-down module  320   b  is the same as the level of the second source voltage (VSS 2 ). 
         [0048]    Further referring to illustration of  FIG. 3C , a shift register unit  203   c  according to a third prefer embodiment of the present invention is introduced herein. As the same as shown in  FIG. 2 , the shift register unit  203   c  can be one of the odd-stage cascaded shift register unit (e.g. GOA 1 , GOA 3 , GOA 5  . . . GOA N ) and the even-stage cascaded shift register units (e.g. GOA 2 , GOA 4 , GOA 6  . . . GOA N+1 ). The shift register unit  203   c  of the third embodiment is designed only for connecting the first signal (CK), the second signal (XCK) and the fourth signal (P_XCK), and primarily comprises a first pull-up driving module  300   a , a second pull-up driving module  300   b , a pull-up module  310 , a pull-down module  320 , and a pull-down driving module  330 . 
         [0049]    The first pull-up driving module  300   a  of the shift register unit  203   c  comprises a first transistor (T 1 ) having a drain and a gate both jointed to a pulse signal, such as a setting signal (STN−1) generated from the previous stage shift register unit  203   c  or an initial setting signal (i.e. STO or STE), and a source for generating a driving signal in response to trigger of the pulse signal on the first transistor (T 1 ). 
         [0050]    The pull-up module  310  of the shift register unit  203   c  has an input node (Q), a second transistor (T 2 ), a first capacitor (C 1 ), a second capacitor (C 2 ), a third transistor (T 3 ) and an output node (OUT). The second transistor (T 2 ) has a drain connected with one of a first signal (CK) and a second signal (XCK) (but only connected with the first signal (CK) in this third embodiment), a gate connected with the input node (Q) for connecting to the driving signal of the first pull-up driving module  300   a , and a source connected with the output node (OUT) for generating an output signal as gate pulse signal (e.g. OUT 1 ·OUT N+1 ). The first capacitor (C 1 ) has a polar terminal connected with the first signal (CK) (or the second signal (XCK)) and another polar terminal connected with both of the input node (Q) and the driving signal. The second capacitor (C 2 ) has a polar terminal connected with the first signal (CK) (or the second signal (XCK)) and another polar terminal connected with the source of the second transistor (T 2 ). The third transistor (T 3 ) has a drain connected with the first signal (CK) (or the second signal (XCK)), a gate connected with the input node (Q) for further connecting to the driving signal, and a source connected with the output point for generating the setting signal (STN) to the next stage shift register unit  203   c.    
         [0051]    The pull-down driving module  330  of the shift register unit  203   c  comprises a third capacitor (C 3 ) and a fourth transistor (T 4 ), wherein the third capacitor (C 3 ) has a polar terminal connected with the fourth signal (P_XCK) and another polar terminal connected with a first input node (K) of the pull-down module  320 , and the fourth transistor (T 4 ) has a drain connected with the first input node (K), a gate connected with an input signal on an input node (Q—1) of the previous stage shift register unit  203   c , and a source connected with the first source voltage (VSS 1 ). Accordingly, the whole system reliability can be raised by the pull-down driving module  330  which is constituted with connections of the third capacitor (C 3 ) to the fourth signal (P_XCK) and the fourth transistor (T 4 ). 
         [0052]    The pull-down module  320  of the shift register unit  203   c  comprises a fifth transistor (T 5 ), a sixth transistor (T 6 ), a seventh transistor (T 7 ), an eighth transistor (T 8 ) and a ninth transistor (T 9 ). The fifth transistor (T 5 ) has a drain connected with the input node (Q) of the pull-up module  310 , a gate connected with the first input node (K) of the pull-down module  330 , and a source connected with the first source voltage (VSS 1 ). The sixth transistor (T 6 ) has a drain connected with the setting signal (STN) to the next stage shift register unit  203   c  via an output point of the pull-up module  310 , a gate connected with the first input node (K), and a source connected with the first source voltage (VSS 1 ). The seventh transistor (T 7 ) has a drain connected with the output node (OUT) of the pull-up module  310 , a gate connected with the first input node (K), and a source connected with the first source voltage (VSS 1 ). The eighth transistor (T 8 ) has a drain connected with the output node (OUT) of the pull-up module  310 , a gate connected with the second signal (XCK), and a source connected with the first source voltage (VSS 1 ). The ninth transistor (T 9 ) has a drain connected with the setting signal (STN) to the next stage shift register unit  203   c  via the output point of the pull-up module  310 , a gate connected with the second signal (XCK), and a source connected with the first source voltage (VSS 1 ). 
         [0053]    The pull-up driving module  300   b  of the shift register unit  203   c  comprises a tenth transistor (T 10 ), an eleventh transistor (T 11 ) and a twelveth transistor (T 12 ). The tenth transistor (T 10 ) has a drain connected with the source of the first transistor (T 1 ) of the first pull-up driving module  300   a , a gate connected with a setting signal (STN+1) generated from the next stage shift register unit  203   c , and a source connected with the first source voltage (VSS 1 ). The eleventh transistor (T 11 ) has a drain connected with the output node (OUT) of the pull-up module  310 , and a gate connected with the setting signal (STN+1) generated from the next stage shift register unit  203   c , and a source connected with the first source voltage (VSS 1 ). The twelveth transistor (T 12 ) has a drain connected with the setting signal (STN) to the next stage shift register unit  203   c  via the output point of the pull-up module  310 , a gate connected with the setting signal (STN+1) generated from the next stage shift register unit  203   c , and a source connected with the first source voltage (VSS 1 ). As the same as the shift register units  203   a  disposed in the first embodiment, in each of the odd-stage shift register units  203   c  of the third embodiment, the first signal (CK) is designated into the first clock signal (CKO), the second signal (XCK) is designated into the second clock signal (XCKO), the third signal (P_CK) is designated into the first periodic signal (CKE) and the fourth signal (P_XCK) is designated into the second periodic signal (XCKE); oppositely, in each of the even-stage shift register units of this embodiment, the first signal (CK) is designated into the first periodic signal (CKE), the second signal (XCK) is designated into the second periodic signal (XCKE), the third signal (P_CK) is designated into the first clock signal (CKO) and the fourth signal (P_XCK) is designated into the second clock signal (XCKO). 
         [0054]    Further referring to  FIG. 7A  to  FIG. 7H , which illustrate various signal waveforms of the shift register unit  203   c  according to the third preferred embodiment of the present invention, which depict the first periodic signal (CKE), the second periodic signal (XCKE), the first clock signal (CKO), the second clock signal (XCKO), a setting signal (STN−1) generated from the previous stage shift register unit  203   c , an input signal of the input node (Q) of the shift register unit  203   c , an input signal inputted from an input node (Q−1) of the previous stage shift register unit  203   c  and a signal inputted from the first input node (K) of the pull-down module  320 . In operation, after the fourth transistor (T 4 ) of the pull-down driving module  330  is triggered to be electrically conductive by a specific high signal level (i.e. Vh) of the input node (Q−1) of the previous stage shift register unit  203   c  as shown in  FIG. 7G , the first source voltage (VSS 1 ) is connected to the first input node (K) of the pull-down module  320  and thereby pulls down the signal level of the first input node (K) to reach a voltage level ‘VSS 1 ’ as shown in  FIG. 7H  so that the pull-down module  320  is not turned on to facilitate rise of signal waveform of the input node (Q) of the shift register unit  203   c  to reach a level ‘Vh’ as shown in  FIG. 7F . Oppositely, for a specific time period before the first clock signal (CKO) in  FIG. 7C  transits from a low level ‘VSS 1 ’ to a high level ‘Vh’, the second periodic signal (XCKE) in  FIG. 7B  is pre-maintained in a high level ‘Vh’ by the third capacitor (C 3 ) to turn on the pull-down module  320  for pulling down the signal level of the input node (Q) to reach a level ‘VSS 1 ’ as shown in  FIG. 7F . For the same specific time period, the first and second capacitors (C 1 ), (C 2 ) and coupling effect invoked from the first clock signal (CKO) are also able to pull down the signal level of the input node (Q) to reach the level ‘VSS 1 ’ in  FIG. 7F  and further prevent the signal level of the input node (Q) from being pulled up. Thus, this can ensure stability of the output waveform of the output node (OUT) of the pull-up module  310 . 
         [0055]      FIG. 8  illustrates a signal-simulated coordinate diagram with a horizontal axis representative of time (S) and a vertical axis representative of voltage (V), which respectively simulates waveforms of the second periodic signal (XCKE), the first clock signal (CKO), the output signal of the output node (OUT 3 ) and the input signal of the input node (Q 3 ) of the pull-up module  310  in the third stage shift register unit  203   c  according to the third embodiment of the present invention. As shown in  FIG. 8 , when the second periodic signal (XCKE) is maintained ahead of the first clock signal (CKO) in a phase shift less than 180 degree, it is acquired that the third stage shift register unit  203   c  can generate an optimal output signal waveform of the output node (OUT 3 ) and an optimal rising and falling edges of the input signal waveform of the input node (Q 3 ) and therefore its clock coupling effect can be completely diminished. 
         [0056]    It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set fourth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.