Abstract:
Multi-function chipset and related design/manufacturing method for realizing different kinds of chipsets respectively supporting accelerated graphic port (AGP) bus and peripheral component interconnect extended (PCI-X) bus. The integrated circuit of the chipset includes both the AGP and PCI-X bus controllers, which share a common I/O pad configuration, and the chipset is selected to be an AGP-supported chipset or a PCI-X supported chipset by pin strapping. Also, the chipset can be packaged with different wire bonding configurations to alternatively realize chipsets supporting AGP bus or PCI-X bus.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to a multi-function chip set and related design/manufacturing method, and more particularly, to a chip set and related design/manufacturing method capable of utilizing a single IC to implement chipsets with different functions.  
         [0003]     2. Description of the Prior Art  
         [0004]     Computer systems are the most important hardware foundation in today&#39;s modern information society. As the need for computer systems increases, demands of different users of the computer systems have become more apparent. In order to meet these demands, the information service provider discloses different related components of computer systems. As known by those skilled in the art, the computer system utilizes chipsets to manage/control data exchanges among the CPU, system memory, graphic acceleration cards, other cards/circuits, and peripheral devices. For example, the chip set is electrically connected to the graphic acceleration card through a bus of a specific standard in order to manage and control the data exchange between the graphic card and the CPU. In today&#39;s computer system, the graphic acceleration card of an AGP (accelerated graphic port) is often utilized. Therefore, in this type of computer system, a chipset that can support an AGP bus is utilized. On the other hand, for a network server computer system having a greater data flow and requiring a higher efficiency, the PCI-X bus is often utilized to connect the graphic card or other cards (such as a high-speed network card). Therefore, in a network server computer system, a chipset that can support a PCI-X bus has to be utilized.  
         [0005]     In the prior art, the chipset for supporting the AGP bus and the chipset for supporting the PCI-X bus are separately designed and produced. In other words, the above-mentioned chipsets are designed through different ICs instead of the same circuit layout. Furthermore, time and cost involved in the semiconductor procedure of the two chipsets can not be reduced because different ICs need different masks, procedures, and packaging settings.  
       SUMMARY OF INVENTION  
       [0006]     The invention provides a technique of utilizing the same IC to respectively support chipsets with different functions so that the same IC can be utilized to support the chipset of both the AGP bus and the PCI-X bus, to solve the above-mentioned problem.  
         [0007]     In the present invention, a chipset supporting two bus techniques is disclosed. The chip set comprises: a first bus controller for managing signal exchanging of a first bus technique; a second bus controller for managing signal exchanging of a second bus technique; and a multiplexer module comprising a plurality of multiplexers, wherein each input and output end of the first bus controller and the second bus controller is respectively connected to a corresponding input end of the corresponding multiplexer, and the multiplexer module manages the chip set to receive or transfer a signal of the first bus technique or the second bus technique according to a setting signal.  
         [0008]     In the present invention, an AGP bus controller and a PCI-X bus controller are installed in the same IC. Furthermore, one of the two bus controllers can be enabled, and the other bus controller can be disabled. Therefore, the same IC can be utilized to selectively support the AGP bus or the PCI-X bus. Although the AGP bus and the PCI-X bus utilize different protocols and data structures, the standards/protocols of the two buses also have things in common. For example, the clock frequency of the data transmission of the two buses is the same (533 MHz). This represents that the two bus controllers can share some layout designs in the same IC (for example, the I/O pad layout).  
         [0009]     As known by those skilled in the art, the clock frequency of each input/output signal of the input/output pad is one of the most important design considerations. Designers have to think about the clock frequency of the input/output signals, and then the designers can determine the spacing between two input/output pads, wire and layout configuration according to the above-mentioned clock frequency in order to prevent noises between input/output pads (for example, cross-talk or clock skew and jitter). In the present invention, the similar clock frequencies of the AGP and PCI-X buses are well utilized so that the two bus controllers can be integrated in the same IC and share the same layout of input/output pads. In a preferred embodiment of the present invention, a multiplexer module having at least one multiplexer is utilized to control electrical connections between the two bus controllers and the input/output pads. The multiplexer module can utilize the pin strapping technique to selectively connect one of the two bus controllers to the input/output pads so that the selected bus controller can work. At the same time, the unselected bus controller is disabled. Therefore, the same IC can achieve two chipsets supporting two different buses.  
         [0010]     Because different chipsets can share the same IC design, production procedures, and packaging procedures, the present invention can reduce the time and cost of producing the chipset. Furthermore, because the layout area of input/output pad configuration of today&#39;s chipset is bigger than the layout area of the logic circuits of the IC, the layout area of input/output pads dominates the whole occupied layout area. Therefore, in the present invention, although two bus controllers are integrated in the same IC, the entire occupied area is not increased.  
         [0011]     In another embodiment of the present invention, two bus controllers in the same IC can respectively utilize different input/output pads. In addition, when the IC is packaged, a different wire producing (wiring) procedure is utilized to electrically connect different bus controllers to the balls(or pins) on the substrate. Therefore, the same IC can be utilized to achieve chipsets supporting different buses.  
         [0012]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0013]      FIG. 1  is a diagram of a chipset of an embodiment according to the present invention.  
         [0014]      FIG. 2  and  FIG. 3  are diagrams illustrating the chip set shown in  FIG. 1  utilized in different computer systems.  
         [0015]      FIG. 4  is a diagram of another embodiment of utilizing a single IC to implement two chip sets having different functions. 
     
    
     DETAILED DESCRIPTION  
       [0016]     Please refer to  FIG. 1 , which is a diagram of a chipset  10  of an embodiment according to the present invention. The chipset  10  has an IC  12 A with a packaging substrate  12 B. The IC  12 A comprises a peripheral component interconnect (PCI) controller for managing PCI buses, a storage interface controller  14 C for controlling storage devices (for example, the hard disk or optical disk), a memory controller  14 D for accessing memory, and an interface circuit  14 A for managing the chipset  10  and the data exchange between the chipset  10  and the CPU. In addition, the IC  12 A can selectively comprise an audio circuit for managing audio outputs, a display processing circuit for managing graphic signals, or a network controller. The above-mentioned circuits can receive/transfer signals or biases through the input/output pads  22  of the IC  12 A. When the IC  12 A is packaged on the packaging substrate  12 B, the input/output pads  22  can be electrically connected to each corresponding ball (pin)  28  on the packaging substrate  12 B through the wires between the IC  12 A and packaging substrate  12 B and the wire layout inside the packaging substrate  12 B.  
         [0017]     In addition to the above-mentioned circuit arrangement, in order to achieve the technique of the present invention, the present invention IC  12 A further comprises an AGP bus controller  16 A, a PCI-X bus controller  16 B, and a multiplexer module  20 . The AGP bus controller  16 A (which can be regarded as a first bus controller) can manage signal exchange and data exchange among the devices connected to the AGP bus. Similarly, the PCI-X bus controller  16 B (which can be regarded as a second bus controller) can manage signal exchange and data exchange among the devices connected to the PCI-X bus. The multiplexer module  20  can comprise a plurality of multiplexers  18 . Each output end and input end of the two bus controllers  16 A and  16 B is electrically connected to a corresponding input/output pad  24  through a corresponding multiplexer  18 . Furthermore, each input/output pad  24  is electrically connected to each corresponding ball  30  through the wire between the IC and the packaging substrate and the wire layout inside the packaging substrate. Under the above-mentioned arrangement, each multiplexer  18  can control the electrical connection between the input/output end of two bus controllers and corresponding input/output pad  24  (ball  30 ) according to a setting signal S.  
         [0018]     For example, as shown in  FIG. 1 , the AGP bus controller  16 A and PCI-X  16 B bus controller both comprise an input/output end a 1 , p 1 , respectively, which are electrically connected to a corresponding multiplexer  18 . When the multiplexer  18  receives a setting signal S having a specific content (for example, a high-level DC signal), the multiplexer  18  establishes the electrical connection between the input/output end al of the AGP bus controller  16 A and corresponding input/output pad  24  (and ball  30 ), and the multiplexer  18  breaks the connection between the input/output end p 1  of the PCI-X bus controller  16 B and corresponding input/output pad  24  (and ball  30 ). In the other situation, when the multiplexer  18  receives a setting signal S having another specific content (for example, a low-level DC signal), the multiplexer  18  establishes the electrical connection between the input/output end p 1  of the PCI-X bus controller  16 B and corresponding input/output pad  24  (and ball  30 ), and the multiplexer  18  breaks the connection between the input/output end al of the AGP bus controller  16 A and corresponding input/output pad  24  (and ball  30 ). Therefore, because of the operations of the multiplexers  18  of the multiplexer module  20 , the AGP bus controller  16 A and the PCI-X bus controller  16 B can be selectively utilized to receive/transfer signals through each input/output pad  24  and ball  30 . These balls can be regarded as the bus balls of the AGP bus or the PCI-X bus.  
         [0019]     In other words, if the present invention needs the chipset  10  to achieve the chipset supporting AGP bus, the present invention can utilize the multiplexer module  20  to make the AGP bus controller  16 A transfer/receive signals through the input/output pads  24  and balls  30 . Therefore, the AGP bus controller  16 A is able to work but the PCI-X bus controller  16 B is unable to work, because the connection between the PCI-X bus controller  16 B, the input/output pads  28  and balls  30  is broken by the multiplexer module  20 . Oppositely, if the same chipset  10  has to be utilized to achieve a chipset of PCI-X bus, the multiplexer module  20  can be utilized to make the PCI-X bus controller  16 B receive/transfer signals from the input/output pads  24  and balls  30 . Therefore, in this situation, the PCI-X bus controller  16 B is able to work. The AGP bus controller  16 A, however, is unable to work because the connection between the AGP bus controller  16 A, the input/output pads  28  and balls  30  is broken by the multiplexer module  20 . In the practical implementation, the present invention can utilize the operation of the multiplexer module  20  to disable the bus controller, which is not connected to the input/output pads  28  and balls  30 . For example, the multiplexer module  20  can make the bus controller, which is not connected to the input/output pads  28  and balls  30 , be unable to get power. This is achieved by the multiplexer module  20  breaking the electrical connection between the above-mentioned bus controller and the power wire (such as power plane) of the IC. Oppositely, another bus controller, which is electrically connected to the input/output pads  28  and balls  30 , is able to work because the power is supplied and it can receive/transfer signals through connected input/output pads  28  and balls  30 .  
         [0020]     Furthermore, the setting signal S can be received by the input/output pads  26  and the corresponding ball  32  (as shown in  FIG. 1 ) from external circuits outside the chipset  10 . In other words, the ball  32  can be utilized as a multiple setting ball so that the user can utilize a pin strapping method to select whether the chipset  10  supports the AGP standard or PCI-X standard. For example, when the user connects the multiple setting ball  32  of the chipset  10  to a high-level DC voltage, this represents that the multiplexer module  20  receives a high-level setting signal. Therefore, the multiplexer module  20  can enable one of the AGP and PCI-X bus controllers and allow the enabled bus controller to transfer/receive signals through corresponding input/output pad  24  and corresponding ball  30 . The enabled bus controller is now able to work. Furthermore, in some pin strapping methods, a chip can utilize a specific pin to receive the setting signal only when the chip is in a specific mode (for example, an initial set-up or boot mode). When the chip is in a normal operation mode, the specific pin is utilized as a normal input/output pin instead of a strapping pin. In the present invention, this pin-strapping setting technique can be utilized to control the function of the multiplexer module  20 . For example, the multiplexer module  20  can comprise a setting signal register. The setting signal register can be electrically connected to the multiple setting ball  32  when the chipset  10  is operated in the initial set-up mode (for example, the computer system is booting) for receiving the setting signal from external circuits (such as a motherboard) through the ball  32  to determine whether the chipset  10  supports the AGP or PCI-X bus. Until the chipset  10  is in the normal operation mode (for example, the computer system is already booted), each multiplexer  18  of the multiplexer module  20  can determine which bus controller is enabled and connected to each ball according to the setting signal stored in the setting signal register. Furthermore, the ball  32  can be separated outside the register and switched to connect to other controllers of the chipset  10  so that the ball  32  becomes a normal signal input/output ball. In other words, in a normal operation mode, the multiplexer module  20  does not change the electrical connection of the bus controller according to the signal of the ball  32  anymore.  
         [0021]     As mentioned above, in the embodiment shown in  FIG. 1 , the AGP bus controller and PCI-X bus controller can share the same input/output pads configuration through the arrangement of the multiplexer module  20 . Because the AGP and PCI-X buses are both based on the PCI bus, the standards of the AGP and PCI-X buses have many similar signals. For example, IRDY, TRDY, Frame, and other signals are all defined in the standards of both the AGP and PCI-X buses. The present invention utilizes the above-mentioned characteristic to make the two bus controllers share the same input/output pads configuration. Furthermore, the clock frequencies of signal transmission in the AGP and PCI-X bus standards are very close (in fact, the clock frequency is 533 MHz, but a small acceptable inaccuracy may occur). As known by those skilled in the art, the clock frequency of the signal transmission is one of the most important design configurations. The clock frequency influences the wire, spacing, or other settings. Therefore, different input/output pads configurations are used in order to transfer signals with different clock frequency. However, because the clock frequencies in the AGP and PCI-X bus standards are close, the AGP and PCI-X bus controllers can easily share most of the input/output pads configurations. The present invention utilizes the above-mentioned characteristic to integrate the two bus controllers in the same IC.  
         [0022]     In addition, in today&#39;s IC design for the chipsets, the layout area is dominated by the input/output pads configuration. That is, the occupied area of all controllers is smaller than the total area of the IC. It implies that, since the input/output pads configuration dominates total area of an IC, no matter how small the area of the controller is, the total area of the IC can not be reduced. Considering the present invention, because the AGP and PCI-X bus controllers can share the same input/output pads configurations, the two bus controllers can be integrated in the same IC without increasing the occupied area. In other words, even in the present invention chipset comprising AGP and PCI-X bus controllers, the occupied area of the two bus controllers is still smaller than the occupied area of the input/output pads configuration. Therefore, as long as the occupied area of the input/output pads configuration is not increased, the whole area of the IC is not increased.  
         [0023]     In the AGP and PCI-X bus standards, the number of needed signals may be different. For example, because the PCI-X bus utilizes a 64-bit signal transmission, the bus controller may need more input/output pads and balls to transfer/receive more signals/data. As shown in  FIG. 1 , the additional input/output pads and balls can be achieved by the input/output pads  24 B and balls  30 B. Therefore, if the chipset  10  is utilized as a PCI-X bus controller chipset, the PCI-X bus controller  16 B of the chipset  10  can utilize the balls  30  and  30 B to transfer/receive signals. Oppositely, if the chipset  10  is utilized as an AGP bus controller chipset, the balls  30 B can be unused balls.  
         [0024]     Please refer to  FIG. 2  and  FIG. 3  in conjunction with  FIG. 1 .  FIG. 2  and  FIG. 3  are diagrams illustrating the chipset  10  shown in  FIG. 1  utilized in different computer systems. In order to illustrate this more clearly, some circuits of the chipset  10  are omitted in  FIG. 2  and  FIG. 3 . As shown in  FIG. 2 , the computer system  40 A can be a personal computer. Through an appropriate pin strapping setting of the multiplexer module  20 , the multiplexer module  20  can disable the PCI-X bus controller  16 B and enable the AGP bus controller  16 A of the chipset  10 . Therefore, the AGP bus controller  16 A can be electrically connected to an AGP slot  42 A through each ball  30 . Through the AGP slot  42 A, the chipset  10  can achieve the control function of the AGP bus controller to become a chipset supporting the AGP bus. This means the chipset  10  can manage the device on the AGP bus (for example, the AGP graphic acceleration card  46 A). Furthermore, other balls  28  of the chipset  10  can be respectively connected (for example, the balls can be electrically connected through the wire layout of the motherboard) to a CPU  36 A, a system memory  38 A (such as DRAM), one or more storage devices (such as hard disks)  50 A, and one or more slots  48 A (such as the PCI bus slot) to manage signal exchanges among the CPU  36 A, the system memory  38 A, the AGP device, the PCI device (for example, network card, sound card), and other storage devices.  
         [0025]     As shown in  FIG. 3 , the computer system  40 B can be a high-speed network server. Therefore, the computer system  40 B needs a chipset supporting a high-speed PCI-X bus. Through an appropriate pin strapping setting of the multiplexer module  20 , the multiplexer module  20  can enable the PCI-X bus controller  16 B and disable the AGP bus controller  16 A. Furthermore, the PCI-X bus controller  16  can be electrically connected to one or more PCI-X slots through the balls  30  (and  30 B) to achieve a chipset supporting the PCI-X bus. So the chipset  10  can manage the device on the PCI-X slot. For example, the device can be a PCI-X add-in card  46 B (such as a PCI-X graphic acceleration card or a high-speed network card). Other balls  28  of the chipset  10  can be respectively connected to a CPU  36 B, a system memory  38 B, one or more storage devices  50 B, and slots  48 B (such as PCI slots) in order to manage signal exchanges among the CPU  36 A, the system memory  38 A, the PCI-X device, the PCI device, and other storage devices (such as hard disks).  
         [0026]     From the above-mentioned discussion, the present invention can utilize the same chipset to achieve two chipsets, which respectively support AGP and PCI-X buses. In other words, the present invention only has to design, produce, and develop a single chipset. The chipset can be utilized as a multi-function chipset to achieve different functions. Therefore, the cost and time involved in production/development of the chipset can be reduced.  
         [0027]     Please refer to  FIG. 4 , which is a diagram of another embodiment utilizing a single IC  52  to implement two chipsets having different functions. The IC  52  can comprise a processing circuit  54 , an AGP bus controller  56 A, and a PCI-X bus controller  56 B. The processing circuit  54  not only comprises many types of interface circuits and controllers, such as the circuits  14 A to  14 D shown in  FIG. 1 , but also comprises audio circuits, display processing circuits, and network controlling circuits. In addition, the processing circuit  54  can transfer/receive signals through each input/output pad  58 C of the IC  52 . The AGP bus controller  56 A can transfer/receive signals to manage and control the devices on the AGP bus through each input/output pad  58 A. The PCI-X bus controller  56 B can transfer/receive signals through each input/output pad  58 B to control and manage the devices on the PCI-X bus. In other words, in the IC  52 , the AGP bus controller and the PCI-X bus controller respectively have their own input/output pads  58 A and  58 B.  
         [0028]     In this embodiment, if the IC  52  has to be utilized as a chipset  60 A supporting the AGP bus controller  60 A, each input/output pad  58 A of the AGP bus controller  56 A has to be electrically connected to each ball  64  (the bus ball) of the substrate  66 A when the IC  52  is being packaged. Therefore, the AGP bus controller  56 A can transfer/receive signals through the input/output ports  58 A and balls  64  to achieve the control function of the AGP bus. Oppositely, each input/output pad of the PCI-X controller  56 B is not electrically connected to each ball at this time. In other words, the PCI-X controller  56 B does not work. Furthermore, the input/output pads  58 C of the processing circuit  54  are electrically connected to the corresponding balls  62  when the IC is being packaged.  
         [0029]     On the other hand, if the IC  52  has to be utilized as a chipset  60 B supporting the PCI-X bus controller  60 B, each input/output pad  58 B of the PCI-X bus controller  56 B has to be electrically connected to each ball  64  (the bus ball) of the substrate  66 B when the IC  52  is being packaged. Therefore, the PCI-X bus controller  56 B can transfer/receive signals through the input/output ports  58 B and balls  64  to achieve the control function of the PCI-X bus. Oppositely, each input/output pad of the AGP controller  56 A is not electrically connected to each ball at this time. In other words, the AGP controller  56 A does not work. Furthermore, the input/output pads  58 C of the processing circuit  54  are electrically connected to the corresponding balls  62  when the IC is being packaged. Please note that the substrate  66 A can be the same as the substrate  66 B.  
         [0030]     As mentioned above, in the embodiment shown in  FIG. 4 , the same IC (even the IC utilizing the same substrate) is utilized to achieve two functions (AGP bus controller and PCI-X bus controller) through different packaging methods. In other words, the IC can support both the AGP and PCI-X buses.  
         [0031]     In contrast to the prior art, the present invention can utilize the same IC (and also the same substrate and the same packaging procedure such as in the embodiment shown in  FIG. 1 ) to support AGP and PCI-X buses. Therefore, the present invention can reduce the cost and time involved in production of the chipset and can be utilized in different computer systems.  
         [0032]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.