Abstract:
This disclosure concerns a semiconductor memory device including a ferroelectric capacitor; a cell transistor having a source connected to a first electrode of the ferroelectric capacitor; bit lines; word lines; n plate lines corresponding to n column blocks and connected to a second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-249768, filed on Sep. 14, 2006, the entire contents of which are incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor memory device such as a semiconductor memory device using a ferroelectric capacitor for memory cells. 
   2. Related Art 
   A ladder ferroelectric RAM (Random Access Memory) includes plate lines corresponding to bit lines provided in respective memory cell columns. Furthermore, such a ferroelectric RAM includes at least one reset line for resetting all memory cells in a cell array. Accordingly, if the number of bit lines is k in a certain cell array, k plate lines and at least one reset line are necessary. Namely, to drive a cell array including memory cells in k columns, the sum of the number of plate lines and that of reset lines is equal to or greater than (k+1). 
   If the numbers of plate lines and reset lines are large, an area of wirings for these lines is disadvantageously made large. Further, if the numbers of plate lines and reset lines are large, circuits for driving these lines are disadvantageously made large in scale. 
   SUMMARY OF THE INVENTION 
   A semiconductor memory device according to an embodiment of the present invention comprises a ferroelectric capacitor including a ferroelectric between a first electrode and a second electrode; a cell transistor having a source connected to the first electrode; a cell array in which a plurality of memory cells including the ferroelectric capacitors and the cell transistors are arranged in a matrix on a semiconductor substrate; a plurality of bit lines provided to correspond to columns of the memory cells and connected to a drain of the cell transistor; a plurality of word lines provided to correspond to rows of the memory cells and connected to a gate of the cell transistor; n plate lines corresponding to n column blocks and connected to the second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks. 
   A semiconductor memory device according to an embodiment of the present invention comprises a ferroelectric capacitor including a ferroelectric between a first electrode and a second electrode; a cell transistor having a source connected to the first electrode; a cell array in which a plurality of memory cells including the ferroelectric capacitors and the cell transistors are arranged in a matrix on a semiconductor substrate; a plurality of bit lines provided to correspond to columns of the memory cells and connected to a drain of the cell transistor; a plurality of word lines provided to correspond to rows of the memory cells and connected to a gate of the cell transistor; a plurality of reset transistors connected between the bit lines and the plate lines; n reset lines corresponding to n column blocks, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2, the n reset lines being connected to gates of m reset transistors provided for one of the n column blocks; and m plate lines provided for the n columns respectively included in the n different column blocks and connected to the second electrodes provided in the n columns. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram showing an internal configuration of a ferroelectric memory device according to a first embodiment of the present invention; 
       FIG. 2  is a timing chart showing a data read operation performed by the ferroelectric memory device according to the first embodiment; 
       FIG. 3  is a timing chart showing a data read operation performed by the ferroelectric memory device according to a modification of first embodiment; 
       FIG. 4  is a circuit diagram showing an internal configuration of a ferroelectric memory device according to a second embodiment of the present invention; 
       FIG. 5  is a circuit diagram showing an internal configuration of a ferroelectric memory device according to a third embodiment of the present invention; 
       FIG. 6  is a cross-sectional view of the memory cell array according to the second embodiment; 
       FIG. 7  is a layout view at the time of forming gate electrodes of the cell transistors CT 0  to CT 15  and those of the reset transistors RT 0  and RT 1 ; 
       FIG. 8  shows a pattern at the time of forming electrodes of the ferroelectric capacitors FC 0  to FC 15 ; 
       FIG. 9  shows a metal wiring pattern at the time of forming the plate lines PL 0  to PL 3 ; 
       FIG. 10  shows a metal wiring pattern at the time of forming local bit lines; 
       FIG. 11  shows a metal wiring pattern at the time of forming main bit lines; and 
       FIG. 12  shows a metal wiring pattern at the time of forming the word lines, the reset lines, and the plate lines. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Embodiments of the present invention will be explained below with reference to the accompanying drawings. The present invention is not limited to the embodiments. 
   First Embodiment 
     FIG. 1  is a circuit diagram showing an internal configuration of a ferroelectric memory device according to a first embodiment of the present invention. Each cell array CA includes a plurality of memory cells MCs arranged in a matrix on a semiconductor substrate. Each of the memory cells MCs includes a ferroelectric capacitor FC and a cell transistor CT. The ferroelectric capacitor FC includes a ferroelectric between a first electrode E 1  and a second electrode E 2 . A source of the cell transistor CT is connected to the first electrode E 1 , and a drain thereof is connected to one of bit lines BL 0 , BL 1 , /BL 0 , and /BL 1  via one of bit nodes BN 1  to BN 4  and one of selection transistors ST 1  to ST 4 . It is to be noted that reference symbols are given only to one memory cell MC and not given to the other memory cells MCs. Symbol “/ (bar)” means signal inversion. 
   Each of the bit lines BL 0 , BL 1 , /BL 0 , and /BL 1  is provided for the memory cells MCs arranged in a column direction. Each of word lines WL 0  to WLk is provided for the memory cell MCs arranged in a row direction, and connected to a gate of each memory cell MC. 
   The memory cells MCs are arranged in four columns CL 1  to CL 4 . The columns CL 1  and CL 2  are adjacent to each other and connected to a plate node PN 0  in common. The columns CL 3  and CL 4  are adjacent to each other and connected to a plate node PN 1  in common. The columns CL 1  and CL 2  constitute a column block CB 0 , and the columns CL 3  and CL 4  constitute a column block CB 1 . In this way, pairs of columns of the cell arrays CAs are divided into two column blocks CB 0  and CB 1 , respectively. Plate lines PL 0  and PL 1  are provided to correspond to the respective column blocks CB 0  and CB 1 . The plate line PL 0  is connected to the second electrodes E 2  of ferroelectric capacitors FC of the respective memory cells MCs within the column block CB 0  in common via the plate node PN 0 . The plate line PL 1  is connected to the second electrodes E 2  of ferroelectric capacitors FC within the column block CB 1  in common via the plate node PN 1 . 
   Bit nodes BN 1  to BN 4  are connected to the bit lines /BL 0 , /BL 1 , BL 0 , and BL 1  via selection transistors ST 1  to ST 4 , respectively. The bit nodes BN 1  and BN 2  are connected to the plate node PN 0  in common via reset transistors RT 1  and RT 2 , respectively. The bit nodes BN 3  and BN 4  are connected to the plate node PN 1  in common via reset transistors RT 3  and RT 4 , respectively. 
   A reset line RS 0  is connected to gates of the reset transistors RT 1  and RT 4 , and a reset line RS 1  is connected to gates of the reset transistors RT 2  and RT 3 . Namely, the reset lines RS 0  and RS 1  are provided to correspond to the two respective columns CL 1  and CL 2  within the column block CB 0 , and provided to correspond to the two respective columns CL 3  and CL 4  within the column block CB 1 . Moreover, the reset line RS 0  is connected to the gates of the two reset transistors RT 1  and RT 4  respectively provided in the two columns CL 1  and CL 4  which are respectively included in the two column blocks CB 0  and CB 1 . The reset line RS 1  is connected to the gates of the two reset transistors RT 2  and RT 3  respectively provided for the other two columns CL 2  and CL 3  which are respectively included the two column blocks CB 0  and CB 1 . 
   In the first embodiment, one of the bit lines BL 0  and /BL 0  transmits information data stored in the memory cells MCs whereas the other bit line /BL 0  or BL 0  transmits reference data. Further, one of the bit lines BL 1  and /BL 1  transmits information data stored in the memory cells MCs whereas the other bit line /BL 1  or BL 1  transmits reference data. The reference data has a potential between potentials of data “0” and data “1” and is generated by a reference data generation circuit (not shown). 
   The bit line BL 0  corresponding to the column block CB 0  is arranged near the column block CB 1 , and the bit line BL 1  corresponding to the column block CB 1  is arranged near the column block CB 0 . The bit line BL 0  is connected to the selection transistor ST 2  and the bit node BN 2  by a wiring crossing the bit line /BL 1 . The bit line /BL 1  is connected to the selection transistor ST 3  and the bit node BN 3  by a wiring crossing the bit line BL 0 . Namely, a positional relationship between the bit lines BL 0  and /BL 1  is inverse to a connection relationship therebetween in which the bit lines BL 0  and /BL 1  are connected to the column blocks CB 0  and CB 1 , respectively. In the first embodiment, potentials of inactive bit lines BLs are fixed and the bit lines BLs are employed as shielding lines. By doing so, interference noise generated between a pair of bit lines BLs used to read data can be cancelled. 
     FIG. 2  is a timing chart showing a data read operation performed by the ferroelectric memory device according to the first embodiment. In the first embodiment, it is assumed that a memory cell MC 12  specified by the word line WL 1  and the bit line /BL 0  is selected. 
   Before t 1 , the word lines WLs and the reset lines RS 0  and RS 1  are active (at high level). The cell transistors CTs and the reset transistors RT 1  to RT 4  are thereby all turned on. Due to this, the first electrode E 1  of each ferroelectric capacitor FC is shorted to the second electrode E 2  via the corresponding cell transistor CT and one of the reset transistors RT 1  to RT 4 , and the first electrode E 1  is made equal in potential to the second electrode E 2 . As a result, data in each of the ferroelectric capacitors FCs is held. 
   At t 1 , unselected word lines WLs other than the selected word line WL 1  are deactivated (made low level). By doing so, only the cell transistors CTs connected to the selected word line WL 1  are kept to be turned on, and the other transistors CTs are turned off. 
   At t 2 , the reset line RS 0  is deactivated. The reset transistors RT 1  and RT 4  thereby make bit nodes BN 1  and BN 4  disconnect from the plate nodes PN 0  and PN 1 , respectively. The reset transistors RT 2  and RT 3  connect the bit nodes BN 2  and BN 3  to the plate nodes PN 0  and PN 1 , respectively. That is, by driving the reset line RS 0 , one of the two columns in each of the column blocks CB 0  and CB 1 , i.e., the two columns CL 1  and CL 4  are selected. 
   At t 3 , the bit selection line BS 0  and the plate line PL 0  are activated. By activating the bit selection line BS 0 , the bit line /BL 0  is connected to the bit node BN 1 . Furthermore, by activating the plate line PL 0 , the column block CB 0  is selected and potential difference is generated between both ends of the ferroelectric capacitor FC of the memory cell MC 12 . At this moment, the reset line RS 1  is active, so that the reset transistor RT 2  shorts the bit node BN 2  to the plate node PN 0 . Accordingly, the potential difference caused by the plate line PL 0  is not applied to the ferroelectric capacitor FC of each of the memory cells MCs in the column CL 2 . As a result, the information data stored in the memory cell MC 12  is read to the bit line /BL 0 . 
   At this moment, the reset transistor RT 4  is turned off and the selection transistor ST 4  is turned on. Therefore, the electrode E 1  is connected to the bit line BL 1  and the electrode E 2  is connected to the plate line PL 1  in the ferroelectric capacitor FC of a memory cell MC 13  specified by the word line WL 1  and the bit line BL 1 . However, because of equal potential kept between the bit line BL 1  and the plate line PL 1 , no potential difference is generated between both ends of the ferroelectric capacitor FC of the memory cell MC 13 . 
   During a period from t 3  to t 4 , the reference data is transmitted to the bit line BL 0 . A sense amplifier compares a potential or current of the bit line /BL 0  with that of the bit line BL 0 , and detects the information data stored in the bit line /BL 0 . The read information data is output to outside via a buffer. 
   If the information data is “0”, the potential of the bit line /BL 0  is at low level. Therefore, during a period from t 4  to t 5 , the potential difference is given to the ferroelectric capacitor FC of the selected memory cell MC 12  while the plate line PL 0  is active (at high level). By doing so, the data “0” is rewritten to the selected memory cell MC 12 . 
   If the information data is “1”, the potential of the bit line /BL 0  is at high level. Therefore, during a period from t 5  to t 6 , a potential having a reversed polarity from that of a “0” writing potential is applied to the ferroelectric capacitor FC of the selected memory cell MC 12  while the plate line PL 0  is inactive (at low level). The data “1” is thereby rewritten to the selected memory cell MC 12 . 
   At t 6 , the bit selection line BS 0  is deactivated and the bit line /BL 0  is thereby disconnected from the bit node BN 1 . At t 7 , the reset line RS 0  is activated, and at t 8 , the word lines WLs other than the selected word line WL 1  are activated. 
   A data write operation performed by the ferroelectric memory device is similar to the data read operation from t 1  to t 4  shown in  FIG. 2 . Thereafter, during the period from t 4  to t 5 , if to-be-written data input from the outside differs from the read information data, the data stored in the bit line /BL 0  is inverted. A manner of inverting the data is indicated by broken lines in  FIG. 2 . A subsequent data rewrite operation and an operation from t 6  to t 8  are similar to those described above. 
   According to the first embodiment, during data writing or data reading, the plate line PL 0  or PL 1  selects one of the column blocks CB 0  and CB 1 , and potential is applied to the ferroelectric capacitors of the memory cells MC 2  within the selected column block CB 0  or CB 1  (CB 0  in the first embodiment). Moreover, the reset line RS 0  or RS 1  selects the column CL 1  or CL 2  (CL 1  in the first embodiment) in the selected column block CB 0 , and the reset transistor in the selected column is turned off. Thus, one of the columns CL 1  to CL 4  can be selected according to a combination of the selections. 
   According to the first embodiment, the plate line selects one column block and the reset line selects one column in the selected column block. However, the concept of the selections may be opposite. For example, the reset line may select one column block and the plate line may select one column within the selected column block. In this case, each of the columns CL 1  and CL 4  and the columns CL 2  and CL 3  shown in  FIG. 1  conceptually constitutes one column block. 
   Conventionally, to drive a cell array including memory cells in four columns, the sum of the number of plate lines and that of reset lines is equal to or greater than five. 
   According to the first embodiment, the sum of the number of plate lines and that of reset lines is four. Therefore, according to the first embodiment, it is possible to decrease the total number of plate lines and the reset lines of the ferroelectric memory device and to downsize the ferroelectric memory device. 
   Modification of First Embodiment 
   The first embodiment relates to a so-called 1T (Transistor)-1C (Capacitor) ferroelectric memory device. A modification of the first embodiment is an embodiment in which the first embodiment is applied to a 2T-2C ferroelectric memory device. In the 2T-2C ferroelectric memory device, paired bit lines BL 0  and /BL 0  transmit data at reversed polarities from each other, respectively. Likewise, paired bit lines BL 1  and /BL 1  transmit data at reversed polarities from each other, respectively. By doing so, one-bit data is detected from the paired bit lines BL 0  and /BL 0  and one-bit data is detected from the paired bit lines BL 1  and /BL 1 . In this case, the data stored in one of the paired bit lines BL 0  and /BL 0  refers to the data stored in the other bit line /BL 0  or BL 0  as reference data, and the other data refers to the data stored in one of the paired bit line BL 0  or /BL 0  as reference data. It is, therefore, possible to dispense with a reference data generation circuit. 
   An internal configuration of a cell array CA according to the modification is similar to that shown in  FIG. 1 . 
     FIG. 3  is a timing chart showing a data read operation performed by the ferroelectric memory device according to the modification. In the modification, it is assumed that a column block CB 0  is selected and that information data is read to the bit lines BL 0  and /BL 0 . The operation shown in  FIG. 3  differs from that shown in  FIG. 2  in that a reset line RS 1  operates similarly to a reset line RS 0  and that a bit selection line BS 1  operates similarly to a bit selection line BS 0 . Selection transistors ST 1  to ST 4  are thereby all turned on. In addition, reset transistors RT 1  to RT 4  are all turned off. While the plate line PL 1  is deactivated, the plate line PL 0  is activated. As a result, the column block CB 0  is selected. Two memory cells MCs connected to a word line WL 1  within the column block CB 0  are selected. From these selected memory cells MCs, data is transmitted to the bit lines BL 0  and /BL 0 , respectively. A sense amplifier (not shown) detects one of data read to the bit lines BL 0  and /BL 0 , while the other of the data read to the bit lines BL 0  and /BL 0  is set as the reference data. It is to be noted that the data stored in the memory cells MCs connected to the column CL 1  should have a reversed polarity from that of the data stored in the memory cells MCs connected to the column CL 2 . Likewise, the data stored in the memory cells MCs connected to the column CL 3  should have a reversed polarity from that of the data stored in the memory cells MCs connected to the column CL 4 . Accordingly, if data different from the read data is to be written during the data write operation, not only the data on the bit line /BL 0  but also the data on the bit line BL 0  are inverted. A manner of inverting the data is indicated by broken lines in  FIG. 3 . Because the other operations according to the modification are similar to those according to the first embodiment, they will not be described herein. The 2T-2C ferroelectric memory device according to the modification can attain the same advantages as those of the 1T-1C ferroelectric memory device according to the first embodiment. 
   Second Embodiment 
     FIG. 4  is a circuit diagram showing an internal configuration of a ferroelectric memory device according to a second embodiment of the present invention. According to the second embodiment, each of cell arrays CAs includes eight columns CL 1  to CL 8 . A configuration of each of memory cells MCs included in each of the columns CL 1  to CL 8  is similar to that of the memory cell MC according to the first embodiment. Further, configurations of column blocks CB 0  and CB 1  are similar to those of the column blocks CB 0  and CB 1  according to the first embodiment, respectively. 
   The configuration of the ferroelectric memory device according to the second embodiment is such that column blocks CB 2 , CB 3  and plate lines PL 2 , PL 3  are added to the ferroelectric memory device according to the first embodiment. The column block CB 2  includes the columns CL 5  and CL 6 . The columns CL 5  and CL 6  are connected to a plate node PN 2  in common and adjacent to each other. A drain of a cell transistor CT of each of the memory cells MCs in the column CL 5  is connected to a bit line /BL 2  via a bit node BN 5  and a selection transistor ST 5 . A second electrode E 2  of a ferroelectric capacitor FC of each of the memory cells MCs in the column CL 5  is connected to the plate node PN 2  in common. The drain of the cell transistor CT of each of the memory cells MCs in the column CL 6  is connected to a bit line BL 2  via a bit node BN 6  and a selection transistor ST 6 . The second electrode E 2  of the ferroelectric capacitor FC of each of the memory cells MCs in the column CL 6  is connected to the plate node PN 2  in common. 
   The column block CB 3  includes the columns CL 7  and CL 8 . The columns CL 7  and CL 8  are connected to a plate node PN 3  in common and adjacent to each other. The drain of the cell transistor CT of each of the memory cells MCs in the column CL 7  is connected to a bit line /BL 3  via a bit node BN 7  and a selection transistor ST 7 . The second electrode E 2  of the ferroelectric capacitor FC of each of the memory cells MCs in the column CL 7  is connected to the plate node PN 3  in common. The drain of the cell transistor CT of each of the memory cells MCs in the column CL 8  is connected to a bit line BL 3  via a bit node BN 8  and a selection transistor ST 8 . The second electrode E 2  of the ferroelectric capacitor FC of each of the memory cells MCs in the column CL 8  is connected to the plate node PN 3  in common. 
   The plate node PN 2  is connected to the plate line PL 2 , and the plate node PN 3  is connected to the plate line PL 3 . 
   Basically, the ferroelectric memory device according to the second embodiment operates similarly to that according to the first embodiment. In the second embodiment, one of plate lines PL 0  to PL 3  selects one of the column blocks CB 0  to CB 3 , and one of reset lines RS 0  and RS 1  selects one of the columns CLs within the selected column block CB. 
   Conventionally, to drive a cell array including memory cells in eight columns, the sum of the number of plate lines and that of reset lines is equal to or greater than nine. 
   According to the second embodiment, the sum of the number of plate lines and that of reset lines is six. Therefore, it is possible to decrease the total number of plate lines and the reset lines of the ferroelectric memory device and to downsize the ferroelectric memory device. 
   The second embodiment is applicable to both the 1T-1C ferroelectric memory device and the 2T-2C ferroelectric memory device, similarly to the first embodiment. 
   Third Embodiment 
     FIG. 5  is a circuit diagram showing an internal configuration of a ferroelectric memory device according to a third embodiment of the present invention. A configuration of each of cell arrays CAs may be similar to that of each cell array CA according to the second embodiment. However, each column blocks CB 0 -CB 3  includes different columns from the second embodiment. The column block CB 0  includes CL 1  and CL 4 . The column block CB 1  includes CL 2  and CL 3 . The column block CB 2  includes CL 5  and CL 8 . The column block CB 3  includes CL 6  and CL 7 . 
   Further, according to the third embodiment, differently from the second embodiment, the number of plate lines is two and that of reset line is four. The reset lines RS 0 -RS 3  corresponds to the column blocks CB 0 -CB 3 . The reset lines RS 0 -RS 3  connect to gates of the reset transistors RT 1  and RT 4 , RT 2  and RT 3 , RT 5  and RT 8 , RT 6  and RT 7 . The reset transistors RT 1  and RT 4  are provided for the column block CB 0 . The reset transistors RT 2  and RT 3  are provided for the column block CB 1 . The reset transistors RT 5  and RT 8  are provided for the column block CB 2 . The reset transistors RT 6  and RT 7  are provided for the column block CB 3 . One of the reset lines selects one of the four column blocks. 
   The plate line PL 0  is provided for the columns CL 1 , CL 2 , CL 5  and CL 6  respectively included in the different column blocks CB 0 -CB 3 . The plate line PL 0  connects to the second electrodes E 2  of the columns CL 1 , CL 2 , CL 5  and CL 6 . The plate line PL 1  is provided for the columns CL 3 , CL 4 , CL 7  and CL 8  respectively included in the different column blocks CB 0 -CB 3 . The plate line PL 1  connects to the second electrodes E 2  of the columns CL 3 , CL 4 , CL 7  and CL 8 . One of the plate lines selects a column included in the selected column block. That is, the role of the reset lines and the role of the plate lines in the third embodiment is reversed those in the second embodiment. 
   Bit selection lines BS 0  to BS 3  are provided to correspond to the respective reset lines RS 0  to RS 3 . For example, if the reset line RS 0  is selected, the bit selection line BS 0  is selected. Likewise, if the reset line RSi (i=1 to 3) is selected, the bit selection line BSi is selected. The bit node BNi (i=1 to 8) in the selected column CLi is connected to one bit line BL via the selection transistor STi. 
   According to the third embodiment, the sum of the number of plate lines and that of reset lines is six. Therefore, it is possible to decrease the total number of plate lines and the reset lines of the ferroelectric memory device and to downsize the ferroelectric memory device. 
   The third embodiment is applicable to both the 1T-1C ferroelectric memory device and the 2T-2C ferroelectric memory device, similarly to the first embodiment. 
   In the embodiments stated above, the plate lines PLs, the reset lines RSs, and the reset transistors RTs may be conceptually considered to function as a decoder DEC. Referring to  FIG. 1 , for example, the decoder DEC supplies two pieces of one-bit data (two-bit data in all) to one of the plate lines PLs and one of the reset lines RSs, respectively. The decoder DEC can thereby select a specific column CL. Referring to  FIG. 4 , the decoder DEC supplies two-bit data and one-bit data (three-bit data in all) to one of the plate lines PLs and one of the reset lines RSs, respectively. The decoder DEC can thereby select a specific column CL. Referring to  FIG. 5 , the decoder DEC supplies one-bit data and two-bit data (three-bit data in all) to one of the plate lines PLs and one of the reset lines RSs, respectively. The decoder DEC can thereby select a specific column CL. 
   The above-stated embodiments can be generalized as follows. 2 R  columns can be driven by 2 p  plate lines and 2 q  reset lines, where R, p, and q are natural numbers and satisfy R=p+q. 
     FIG. 6  is a cross-sectional view of the memory cell array CA according to the second embodiment shown in  FIG. 4 . Referring to  FIG. 6 ,  16  word lines WL 0  to WL 15 , the two reset lines RS 0  and RS 1 , and the four plate lines PL 0  to PL 3  are provided. The word lines WL 0  to WL 15  are electrically connected to gates G 0  to G 15  of cell transistors CT 0  to CT 15 , respectively. Ferroelectric capacitors FC 0  to FC 15  are provided to correspond to the respective cell transistors CT 0  to CT 15 . 
   The reset lines RS 0  and RS 1  are connected to gates RG 0  and RG 1  of reset transistors RT 0  and RT 1 , respectively. A main bit line BL 3  and a local bit line LBL 3  are provided between the word lines WL 0  to WL 15  and the ferroelectric capacitors FC 0  to FC 15 . 
     FIG. 7  is a layout view at the time of forming gate electrodes of the cell transistors CT 0  to CT 15  and those of the reset transistors RT 0  and RT 1 .  FIG. 7  corresponds to a plan view along a line  7 - 7  of  FIG. 6 . Furthermore,  FIG. 6  corresponds to a cross-sectional view taken along a line  6 - 6  of  FIG. 7 . It is to be noted, however, that bit line contacts and plate line contacts are not shown in  FIG. 7  because they are not formed yet at the time of forming the gate electrodes. 
   Gate electrodes G 0  to G 15  are formed on an active area AA. The gate electrodes G 0  to G 15  extend almost in parallel to the word lines WLs (orthogonally to the bit lines BLs). 
   In each of the columns CL 1 , CL 4 , CL 5  and CL 8  controlled by the reset line RS 0 , the area under the gate RG 1  of the reset transistor RT 1  corresponding to the reset line RS 1  is doped to make depletion type transistor. The columns CL 1 , CL 4 , CL 5  and CL 8  are thereby controlled by the reset line RS 0  irrespectively of the reset line RS 1 . On the other hand, in each of the columns CL 2 , CL 3 , CL 6  and CL 7  controlled by the reset line RS 1 , the area under the gate RG 0  of the reset transistor RT 0  corresponding to the reset line RS 0  is doped to make depletion type transistor. The columns CL 2 , CL 3 , CL 6  and CL 7  are thereby controlled by the reset line RS 1  irrespectively of the reset line RS 0 . 
     FIG. 8  shows a pattern at the time of forming electrodes of the ferroelectric capacitors FC 0  to FC 15 .  FIG. 8  corresponds to a plan view along a line  8 - 8  of  FIG. 6 .  FIG. 6  corresponds to a cross-sectional view taken along a line  6 - 6  of  FIG. 8 . It is to be noted, however, that bit line contacts and plate line contacts are not shown in  FIG. 8  because they are not formed yet at the time of forming the electrodes of the ferroelectric capacitors FC 0  to FC 15 . 
   A contact plug CP is provided in a central portion of each of the electrodes of the ferroelectric capacitors FC 0  to FC 15 . Lower electrodes of the ferroelectric capacitors FC 0  to FC 15  are connected to a diffusion layer on a semiconductor substrate via the respective contact plugs CPs. 
   Dummy capacitors DCs are provided between two adjacent memory cell arrays. The dummy capacitors DCs are formed in a space between the two adjacent memory cell arrays so as to reduce dimensional irregularities among the ferroelectric capacitors FC 0  to FC 15 . The dummy capacitors DCs do not at all function as circuit elements. 
     FIG. 9  shows a metal wiring pattern at the time of forming the plate lines PL 0  to PL 3 .  FIG. 9  corresponds to a plan view along a line  9 - 9  of  FIG. 6 .  FIG. 6  corresponds to a cross-sectional view taken along a line  6 - 6  of  FIG. 9 . Namely,  FIG. 6  shows only a cross section of the plate line PL 3 . 
   Metal layers M 1  of the plate lines PL 0  to PL 3  are formed to correspond to the column blocks CB 0  to CB 3 , respectively. Reference symbol VIA 1  denotes a contact connecting a drain layer of each cell transistor CT to the local bit line LBL 2 . 
     FIG. 10  shows a metal wiring pattern at the time of forming local bit lines LBL 0  to LBL 3  and /LBL 0  to /LBL 3 .  FIG. 10  corresponds to a plan view along a line  10 - 10  of  FIG. 6 .  FIG. 6  corresponds to a cross-sectional view taken along a line  6 - 6  of  FIG. 10 . Namely,  FIG. 6  shows a cross section of the local bit line LBL 3 . 
   The local bit lines LBL 0  to LBL 3  and /LBL 0  to /LBL 3  are connected to the contacts VIA 1  via contacts VIA 2 , and connected to the drain layer of each cell transistor CT via each contact VIA 1 . 
   Wirings WRs provided to be adjacent to the local bit lines LBL 0  to LBL 3  and /LBL 0  to /LBL 3  are applicable as various data lines. 
     FIG. 11  shows a metal wiring pattern at the time of forming main bit lines BL 0  to BL 3  and /BL 0  to /BL 3 .  FIG. 11  corresponds to a plan view along a line  11 - 11  of  FIG. 6 .  FIG. 6  corresponds to a cross-sectional view taken along a line  6 - 6  of  FIG. 11 . Namely,  FIG. 6  shows a cross section of the main bit line BL 3 . 
   The main bit lines BL 0  to BL 3  and /BL 0  to /BL 3  are connected to the contacts VIA 2  via contacts VIA 3 . 
   The local bit lines LBL 0  to LBL 3  and /LBL 0  to /LBL 3  shown in  FIG. 10  and the main bit lines BL 0  to BL 3  and /BL 0  to /BL 3  shown in  FIG. 11  are almost orthogonal to the word lines WLs. 
     FIG. 12  shows a metal wiring pattern at the time of forming the word lines WLs, the reset lines RSs, and the plate lines PLs.  FIG. 12  corresponds to a plan view along a line  12 - 12  of  FIG. 6 .  FIG. 6  corresponds to a cross-sectional view taken along a line  6 - 6  of  FIG. 12 . 
   The plate lines PL 0  to PL 3  are connected to plates PL 0  to PL 3  of a metal layer M 3  via contacts VIA 4 . 
   The word lines WL 0  to WL 15 , the reset lines RS 0  and RS 1 , and the plate lines PL 0  to PL 3  extend almost in parallel and almost orthogonally to the main bit lines BLs and /BLs and the local bit lines LBLs and /LBLs. 
   While the wiring patterns in a manufacturing process according to the second embodiment have been described, the ferroelectric memory devices according to the embodiments other than the second embodiment can be easily manufactured by changing the wiring patterns.