Abstract:
A semiconductor device is disclosed, which includes an n-channel MISFET including a first gate electrode and a first spacer formed on a side surface of the first gate electrode, the first spacer having a compressive stress; and a p-channel MISFET comprising a second gate electrode and a second spacer formed on a side surface of the second gate electrode, the second spacer having a compressive stress, wherein the compressive stress of the second spacer is smaller than the compressive stress of the first spacer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-217561, filed Jul. 26, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor device having CMISFET (Complementary Metal-Insulator-Semiconductor Field Effect Transistor) and a method of manufacturing the same, and more particularly to a semiconductor device in which stress is applied to an channel region of CMISFET and a method of manufacturing the same.  
         [0004]     2. Description of the Related Art  
         [0005]     As a measure for improving drive current in a CMIS circuit, application of stress to silicon of a channel region of MISFET has been well known.  
         [0006]     As a measure for improving drive current of a MISFET, a method of depositing a silicon nitride film on a gate electrode of the MISFET and applying stress to a channel region of the MISFET has been well known (Jpn. Pat. Appln. KOKAI Publication No. 2003-179157). However although this method is effective for the n-channel MISFET whose carrier is electron, this method has a problem that the mobility is deteriorated in the p-channel MISFET whose carrier is hole, thereby drive current drops.  
         [0007]     To improve the drive current of the CMIS circuit, improvement of the carrier mobility of the p-channel MISFET and n-channel MISFET has been required.  
       BRIEF SUMMARY OF THE INVENTION  
       [0008]     According to an aspect of the present invention, there is provided a semiconductor device comprising:  
         [0009]     an n-channel MISFET including a first gate electrode and a first spacer formed on a side surface of the first gate electrode, the first spacer having a compressive stress; and  
         [0010]     a p-channel MISFET comprising a second gate electrode and a second spacer formed on a side surface of the second gate electrode, the second spacer having a compressive stress, wherein  
         [0011]     the compressive stress of the second spacer is smaller than the compressive stress of the first spacer.  
         [0012]     According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:  
         [0013]     forming a gate electrode on a gate insulating film formed on a p-type semiconductor layer and a gate electrode on a gate insulating film formed on an n-type semiconductor layer;  
         [0014]     forming a first spacer having a compressive stress on a side surface of the gate electrode formed on the p-type semiconductor layer; and  
         [0015]     forming a second spacer having a compressive stress on a side surface of the gate electrode formed on the n-type semiconductor layer, the compressive stress of the second spacer being smaller than the compressive stress of the first spacer.  
         [0016]     According to a further aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:  
         [0017]     forming a gate electrode on a gate insulating film formed on a p-type semiconductor layer and a gate electrode on a gate insulating film formed on an n-type semiconductor layer;  
         [0018]     forming a first spacer having a compressive stress on side surfaces of the gate electrodes formed on the p-type and n-type semiconductor layers;  
         [0019]     removing the first spacer on the side surface of the gate electrode formed on the n-type semiconductor layer;  
         [0020]     forming a second spacer having a compressive stress on the side surface of the gate electrode formed on the n-type semiconductor layer and a side surface of the first spacer on the side surface of the gate electrode formed on the p-type semiconductor layer, the compressive stress of the second spacer being smaller than the compressive stress of the first spacer; and, removing the second spacer formed on the side surface of the first spacer on the side surface of the gate electrode formed on the p-type semiconductor layer. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0021]      FIG. 1  is a sectional view of a device structure in a step of a semiconductor device manufacturing method according to an embodiment of the present invention;  
         [0022]      FIG. 2  is a sectional view of a device structure in a step subsequent to the step of  FIG. 1 , of the semiconductor device manufacturing method according to the embodiment of the invention;  
         [0023]      FIG. 3  is a sectional view of a device structure in a step subsequent to the step of  FIG. 2 , of the semiconductor device manufacturing method according to the embodiment of the invention;  
         [0024]      FIG. 4  is a sectional view of a device structure in a step subsequent to the step of  FIG. 3 , of the semiconductor device manufacturing method according to the embodiment of the invention;  
         [0025]      FIG. 5  is a sectional view of a device structure in a step subsequent to the step of  FIG. 4 , of the semiconductor device manufacturing method according to the embodiment of the invention; and  
         [0026]      FIG. 6  is a sectional view of a device structure in a step subsequent to the step of  FIG. 5 , of the semiconductor device manufacturing method according to the embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]     A semiconductor device and a method of manufacturing the semiconductor device according to the embodiment of the present invention will be described with reference to the accompanying drawings.  
         [0028]     First, as shown in  FIG. 1 , a silicon oxide film is selectively embedded in a silicon substrate  11  to from a device separation insulating film  12 . A gate insulating film  13  composed of SiO 2  is deposited on the silicon substrate  11 . The gate insulating film  13  may be a film composed of other insulation material than SiO 2 . By ion implantation and annealing, an n-type silicon layer  11   a  in which a p-channel MISFET is formed at later steps and a p-type silicon layer  11   b  in which an n-channel MISFET is formed at later steps are formed in the silicon substrate  11 . A polycrystalline silicon film is deposited on the gate insulating film  13  by using LPCVD (Low Pressure Chemical Vapor Deposition) technology. A resist pattern, not shown, is formed on the polycrystal silicon film by using lithography technology. By dry etching technology with the resist pattern used as a mask, the polycrystalline silicon film is etched to form a gate electrode (second gate electrode)  14   a  on the n-type silicon layer  11   a  and a gate electrode (first gate electrode)  14   b  on the p-type silicon layer  11   b.  Then, the resist pattern is removed. Further, an oxide film, not shown, is formed in oxidative atmosphere.  
         [0029]     Next, by ion implantation technology, BF 2  is implanted into the n-type silicon layer  11   a  and the gate electrode  14   a  in the order of 10 14  cm −2 , and As is implanted into the p-type silicon layer  11   b  and the gate electrode  14   b  in the order of 10 14  cm −2 . Then, annealing is carried out in non-oxidative atmosphere.  
         [0030]     Next, as shown in  FIG. 2 , first spacers  15   a  and  15   b  of silicon nitride film are formed on side walls of the gate electrodes  14   a  and  14   b.  The first spacers  15   a  and  15   b  are formed by depositing a silicon nitride film on the silicon substrate by use of LPCVD technology, and then etching back the deposited silicon nitride film by use of dry etching technology. When the silicon nitride film is formed, an impurity concentration of the silicon nitride film may be controlled to change the stress of the silicon nitride film.  
         [0031]     Next, as shown in  FIG. 3 , by removing the first spacer  15   a  formed on the side wall of the gate electrode  14   a  on the n-type silicon layer  11   a,  to thereby expose the side wall of the gate electrode  14   a.  To remove the first spacer  15   a,  a resist pattern covering the gate electrode  14   b  and the first spacer  15   b  is formed over the p-type silicon layer  11   b  by lithography technology, and the first spacer  15   a  formed on the gate electrode  14   a  is removed with this resist pattern used as a mask, by using wet etching technology. After the removing of the first spacer  15   a,  the resist pattern is removed.  
         [0032]     Next, as shown in  FIG. 4 , second spacers  16   b  and  16   a  of silicon oxide are formed on the side wall of the first spacer  15   b  on the p-type silicon layer  11   b  and on the side wall of the gate electrode  14   a  on the n-type silicon layer  11   a.  To form the second spacers  16   b  and  16   a,  a silicon oxide film is deposited over the silicon substrate by using LPCVD technology, and then the deposited silicon oxide film is etch-backed by use of the dry etching technology. As a result, a laminated film of the first spacer  15   b  and second spacer  16   b  is formed on the side wall of the gate electrode  14   b  on the p-type silicon layer  11   b,  and at the same time, the second spacer  16   a  is formed on the side wall of the gate electrode  14   a  on the n-type silicon layer  11   a.  Compression stress of the silicon oxide film forming the second spacer is smaller than that of the silicon nitride film forming the first spacer.  
         [0033]     Next, as shown in  FIG. 5 , the second spacer  16   b  formed on the side wall of the first spacer  15   b  on the p-type silicon layer  11   b  is removed. To remove the second spacer  16   b,  a resist pattern covering the gate electrode  14   a  and the second spacer  16   a  is formed over the n-type silicon layer  11   a  by using lithography technology, and then using this resist pattern as a mask, the second spacer  16   b  is removed by supplying a solution for etching the silicon oxide film to the substrate. Then, the resist pattern is removed.  
         [0034]     Subsequently, a resist pattern, not shown, covering the gate electrode  14   b  and the first spacer  15   b  is formed over the p-type silicon layer  11   b  by using lithography technology, and then using the resist pattern as a mask, P is implanted into the n-type silicon layer  11   a  in the order of 10 15  cm −2  by ion implantation technology to thereby form P +  diffusion regions  17  used as source/drain regions in the n-type silicon layer  11   a,  as shown in  FIG. 6 . Thereafter, the resist pattern is removed. Similarly, a resist pattern, not shown, covering the gate electrode  14   a  and the second spacer  16   a  is formed over the n-type silicon layer  11   a  by using lithography technology, and then using the resist pattern as a mask, B is implanted into the p-type silicon layer  11   b  in the order of 10 15  cm −2  by ion implantation technology to thereby form n +  diffusion regions  18  used as source/drain regions in the p-type silicon layer  11   b.  Thereafter, the resist pattern is removed.  
         [0035]     According to the described embodiment, as means for applying stress to the channel region of the MISFET, a stress of the side wall film material of the gate electrode is utilized. Thus, it is possible to avoid an over-etching at forming contacts to the source and drain regions. In a conventional dual stress liner technique, a contact liner film having a tensile stress is formed on the n-channel MISFET region and a contact liner film having a compressive stress is formed on the p-channel MISFET region. The contact liners are superposed on the border between the n-channel and p-channel MISFET regions, and thus the thickness of the contact liners is twice that of the non-superposed region. Hence, it is required to carry out an over-etching when forming contacts to the source and drain regions. At the etching, the silicide layers are also subject to etching to degrade the junction leakage characteristics.  
         [0036]     Also, according to the described embodiment, a silicon nitride film is used as the side wall film of the gate electrode of the n-channel MISFET, and a silicon oxide film is used as the side wall film of the gate electrode of the p-channel MISFET. Compression stress of silicon oxide is smaller than that of silicon nitride. As a consequence, the performance of the n-channel MISFET can be improved without deteriorating the performance of p-channel MISFET.  
         [0037]     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.