Abstract:
An N-level rectifier, wherein N is a number of voltage levels of the rectifier, includes an input; a plurality of switching devices connected in parallel, wherein the plurality of switching devices are connected to the input, wherein a number of the plurality of switching devices is equal to N−2; and a plurality of capacitors connected in series, wherein the plurality of capacitors are connected to the plurality of switching devices, wherein a number of the plurality of capacitors is equal to N−1, and wherein the plurality of capacitors are connected to an output of the N-level rectifier; wherein N is greater than three.

Description:
FIELD OF INVENTION 
     The subject matter disclosed herein generally relates to the field of multilevel rectifiers. 
     DESCRIPTION OF RELATED ART 
     Multilevel rectifiers are used to convert alternating current (AC) power to direct current (DC) power. Rectifiers may be employed in many types of power applications, such as aerospace or naval ship systems, adjustable-speeds drives, uninterruptible power supplies, utility interfaces with nonconventional energy sources such as solar photovoltaic systems or wind energy systems, battery energy storage systems, process technology such as electroplating or welding units, battery charging for electric vehicles, and for power supplies for telecommunication systems. Rectifiers may be built using solid-state devices such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), or gate-turn-off thyristors (GTOs). Reduction in the number of components needed to build a rectifier may reduce the price and complexity of the rectifier. A Vienna rectifier (see, for example, Kolar and Zach, “A Novel Three-Phase Utility Interface Minimizing Line Current Harmonics of High-Power Telecommunications Rectifier Modules”, IEEE Vol. 44 No. 4, p. 456, August 1997 for more information), is a rectifier topology that requires a relatively low number of components; however, the Vienna rectifier only offers three-level power conversion. 
     BRIEF SUMMARY 
     According to one aspect of the invention, an N-level rectifier, wherein N is a number of voltage levels of the rectifier, includes an input; a plurality of switching devices connected in parallel, wherein the plurality of switching devices are connected to the input, wherein a number of the plurality of switching devices is equal to N−2; and a plurality of capacitors connected in series, wherein the plurality of capacitors are connected to the plurality of switching devices, wherein a number of the plurality of capacitors is equal to N−1, and wherein the plurality of capacitors are connected to an output of the N-level rectifier; wherein N is greater than three. 
     Other aspects, features, and techniques of the invention will become more apparent from the following description taken in conjunction with the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
         FIG. 1  illustrates an embodiment of a 4-level rectifier having 2 switches per phase leg. 
         FIG. 2  illustrates an embodiment of a 5-level rectifier having 3 switches per phase leg. 
         FIG. 3  illustrates an embodiment of an N-level rectifier having N−2 switches per phase leg. 
         FIG. 4  illustrates an embodiment of a bidirectional switch. 
         FIG. 5  illustrates an embodiment of a 4-level rectifier having 2 switches per phase leg. 
         FIG. 6  illustrates an embodiment of a 5-level rectifier having 3 switches per phase leg. 
         FIG. 7  illustrates an embodiment of a bidirectional switch. 
         FIG. 8  illustrates an embodiment of a gate driver for a 4-level rectifier having 2 switches per phase leg. 
         FIG. 9  illustrates an embodiment of a gate driver for a 5-level rectifier having 3 switches per phase leg. 
         FIG. 10  illustrates an embodiment of a phase voltage waveform, line-line voltage waveform, sine-triangle comparison waveform, and switching waveforms for a 4-level rectifier having 2 switches per phase leg. 
         FIG. 11  illustrates an embodiment of a phase voltage waveform, line-line voltage waveform, sine-triangle comparison waveform, and switching waveforms for a 5-level rectifier having 3 switches per phase leg. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of systems and methods for a multilevel rectifier with N−2 switches, where N is the number of output voltage levels per phase leg, are provided, with exemplary embodiments being discussed below in detail. The number of levels provided by a rectifier determines the increment at which the voltage waveform output may be stepped; therefore, a higher number of levels gives a better voltage waveform output. The switches in the multilevel rectifier may comprise bidirectional switches, comprising multiple diodes, or reverse blocking switches. Reduction in the number of switches allows for reduction in the complexity of the multilevel rectifier itself, and in the circuitry required to operate the multilevel rectifier, including but not limited to gate drivers, digital signal processors (DSPs), or control pins. The N−2 switch per phase leg rectifier topology may be generalized to any desired number of levels. The N-level rectifier may have a reduced total harmonic distortion (THD) at relatively low common mode voltages with an increased number (N) of levels. The THD for a 3-level rectifier may show a 50% reduction over the THD of a 2-level rectifier; the THD for a 4-level rectifier may show a 33% reduction over the THD of a 3-level rectifier; and the THD for a 5-level rectifier may show a 25% reduction over the THD of a 4-level rectifier in some embodiments. 
       FIG. 1  illustrates an embodiment of a 4-level rectifier  100  having 2 switches per phase leg. 4-level rectifier  100  comprises input  101 , a series of diodes  102 A-F, a series of capacitors  104 A-C, switches  103 A-B connected between the diodes  102 A-F and capacitors  104 A-C, and output  105 . Switches  103 A-B may each comprise a bidirectional switch such as is discussed in further detail below with respect to  FIG. 4 . Each of switches  103 A-B has two inputs and one output, as illustrated by inputs  106 A-B and output  107  of switch  103 A. Each of the inputs of switches  103 A-B are connected between a respective pair of diodes  102 A-F, and the outputs of each of switches  103 A-B are connected between a respective pair of capacitors  104 A-C. 4-level rectifier  100  corresponds to a single phase leg. 
       FIG. 2  illustrates an embodiment of a 5-level rectifier  200  having 3 switches per phase leg. 5-level rectifier  200  comprises input  201 , a series of diodes  202 A-H, a series of capacitors  204 A-D, switches  203 A-C connected between the diodes  202 A-H and capacitors  204 A-D, and output  205 . Switches  203 A-C may each comprise a bidirectional switch such as is discussed in further detail below with respect to  FIG. 4 . Each of switches  203 A-C has two inputs and one output. The inputs of each of switches  203 A-C are connected between a respective pair of diodes  202 A-H, and the outputs of each of switches  203 A-C are connected between a respective pair of capacitors  204 A-D. 5-level rectifier  200  corresponds to single phase leg. 
       FIG. 3  illustrates an embodiment of a generalized N-level rectifier  300  having N−2 switches per phase leg. N-level rectifier  300  comprises an input (not shown), a series of diodes  302 A-(2N−2), a series of capacitors  304 A to  304 (N−1), switches  303 A to  303 (N−2) connected between the diodes  302 A to  302 (2N−2) and capacitors  304 A to  304 (N−1), and output  305 . Dashed lines  306  indicate the location of any additional diodes, switches, capacitors, and electrical connections that are present in N-level rectifier  300 . Switches  303 A to  303 (N−2) may each comprise a bidirectional switch such as is discussed in further detail below with respect to  FIG. 4 . Each of switches  303 A to  303 (N−2) has two inputs and one output. The inputs of each of switches  303 A to  303 (N−2) are connected between a respective pair of diodes  302 A to  302 (2N−2), and the outputs of each of switches  303 A to  303 (N−2) are connected between a respective pair of capacitors  304 A to  304 (N−1). N-level rectifier  300  corresponds to a single phase leg. 
       FIG. 4  illustrates an embodiment of a bidirectional switch  400 , which may comprise any of switches  103 A-B,  203 A-C, or  303 A-(N−2). Bidirectional switch  400  comprises switching element  401  and diodes  402 A-B connected between inputs  403 A-B and output  404 . Switching element  401  comprises a gate drive connection  405  that controls switching element  401 . The bidirectional switch  400  allows flow of current in both directions while blocking the voltages when reverse biased. In some embodiments, switches  103 A-B,  203 A-C, or  303 A-(N−2) may comprise reverse blocking switches in place of the bidirectional switch  400  of  FIG. 4 . 
       FIG. 5  illustrates an alternate embodiment of a 4-level rectifier  500  having 2 switches per phase leg. 4-level rectifier  500  comprises input  501 , diodes  502 A-B, a series of capacitors  504 A-C, switches  503 A-B connected between the input  501 , diodes  502 A-B, and capacitors  504 A-C, and output  505 . Switches  503 A-B may each comprise a bidirectional switch such as is discussed in further detail below with respect to  FIG. 7 . Each of switches  503 A-B has one input and one output, as illustrated by input  506  and output  507  of switch  503 A. The inputs of switches  503 A-B are connected to the input  501 , and the outputs of switches  503 A-B are connected between a respective pair of capacitors  504 A-C. 4-level rectifier  500  corresponds to a single phase leg. 
       FIG. 6  illustrates an embodiment of a 5-level rectifier  600  having 3 switches per phase leg. 5-level rectifier  600  comprises input  601 , diodes  602 A-B, a series of capacitors  604 A-D, switches  603 A-C connected between the input  601 , diodes  602 A-B, and capacitors  604 A-D, and output  605 . Switches  603 A-C may each comprise a bidirectional switch such as is discussed in further detail below with respect to  FIG. 7 . Each of switches  603 A-C has one input and one output. The inputs of each of switches  603 A-C are connected to the input  601 , and the outputs of each of switches  603 A-C are connected between a respective pair of capacitors  604 A-D. 5-level rectifier  600  corresponds to single phase leg. Similarly to the N-level rectifier  300  of  FIG. 3 , the topology of rectifiers  500  of  FIGS. 5 and 600  of  FIG. 6  may be generalized to any desired number of levels with the addition of further switches and capacitors, with N−2 switches and N−1 capacitors per level. 
       FIG. 7  illustrates an embodiment of a bidirectional switch  700 , which may comprise any of switches  503 A-B and  603 A-C. Bidirectional switch  700  comprises switching element  701  and diodes  702 A-D connected between input  703  and output  704 . Switching element  701  comprises a gate drive connection  705  that controls switching element  701 . The bidirectional switch  700  allows flow of current in both directions while blocking the voltages when reverse biased. In some embodiments, switches  503 A-B and  603 A-C may comprise reverse blocking switches in place of the bidirectional switch  700  of  FIG. 7 . 
       FIG. 8  illustrates an embodiment of a gate driver  800  for a 4-level rectifier having 2 switches per phase leg, such as rectifier  100  of  FIG. 1  and rectifier  500  of  FIG. 5 . Sinusoidal reference duty cycle  801  is connected to one of the inputs of each of differential amplifiers  803 A-C, and three level-shifted triangle inputs  802 A-C are connected to the remaining inputs of differential amplifiers  803 A-C, respectively. The outputs of differential amplifiers  803 A-C comprise a set of switching sequences, and are connected to the inputs of exclusive or (XOR) gate  805 A via inverters  804 A-B, respectively. The outputs of differential amplifiers  803 A-C are also connected to the inputs of XOR gate  805 B. The output  806 A of XOR gate  805 A may be connected to gate drive  405  (described in  FIG. 4 ) of switch  103 A of  FIG. 1 , or to gate drive  705  (described in  FIG. 7 ) of switch  503 A of  FIG. 5 . The output  806 B of XOR gate  805 B may be connected to gate drive  405  (described in  FIG. 4 ) of switch  103 B of  FIG. 1 , or to gate drive  705  (described in  FIG. 7 ) of switch  503 B of  FIG. 5 . Outputs  806 A-B comprise a minimum distortion four-level waveform. 
       FIG. 9  illustrates an embodiment of a gate driver  900  for a 5-level rectifier having 3 switches per phase leg, such as rectifier  200  of  FIG. 2  and rectifier  600  of  FIG. 6 . Sinusoidal reference duty cycle  901  is connected to one of the inputs of each of differential amplifiers  803 A-D, and four level-shifted triangle inputs  902 A-D are connected to the remaining inputs of differential amplifiers  903 A-D, respectively. The outputs of differential amplifiers  903 A-D comprise a set of switching sequences, which are recombined using a recombination sequence comprising AND gates  905 A-E, inverters  904 A-B, and inverters  906 A-B. The output of differential amplifier  903 B is connected to an input of AND gate  905 A via inverter  904 B, and the output of differential amplifier  903 D is connected to the other input of AND gate  905 A. The output of differential amplifier  903 A is connected to an input of AND gate  905 B via inverter  904 A, and the output of differential amplifier  903 C is connected to the other input of AND gate  905 B. The output of AND gate  905 A is connected to an input of AND gate  905 D and an in put of AND gate  905 C, and the output of AND gate  905 B is connected to an input of AND gate  905 E and an input of AND gate  905 C. The output of AND gate  905 C is connected via inverter  906 A to the other input of AND gate  905 D, and to the other input of AND gate  905 D via inverter  906 B. Output  907 A of AND gate  905 D may be connected to gate drive  405  (described in  FIG. 4 ) of switch  203 A of  FIG. 2 , or to gate drive  705  (described in  FIG. 7 ) of switch  603 A of  FIG. 6 . Output  907 B of AND gate  905 C may be connected to gate drive  405  (described in  FIG. 4 ) of switch  203 B of  FIG. 2 , or to gate drive  705  (described in  FIG. 7 ) of switch  603 B of  FIG. 6 . Output  907 C of AND gate  905 E may be connected to gate drive  405  (described in  FIG. 4 ) of switch  203 C of  FIG. 2 , or to gate drive  705  (described in  FIG. 7 ) of switch  603 C of  FIG. 6 . Outputs  907 A-C comprise a minimum distortion five-level waveform. 
       FIG. 10  illustrates embodiments of a phase voltage waveform, a line-line voltage waveform, a sine-triangle comparison waveform, and switching waveforms for a 4-level rectifier having 2 switches per phase leg, such as rectifier  100  of  FIG. 1  or rectifier  500  of  FIG. 5 . Waveform S-top is a switching signal for the first switch of the rectifier (i.e., switch  103 A or  503 A), and waveform S-bottom is a switching signal for the second switch (i.e., switch  103 B or switch  503 B).  FIG. 11  illustrates embodiments of a phase voltage waveform, a line-line voltage waveform, a sine-triangle comparison waveform, and switching waveforms for a 5-level rectifier having 3 switches per phase leg, such as rectifier  200  of  FIG. 2  or rectifier  600  of  FIG. 6 . Waveform S-top is a switching signal for the first switch of the rectifier (i.e., switch  203 A or  603 A), waveform S-middle is a switching signal for the second switch (i.e., switch  203 B or switch  603 B), and waveform S-bottom is a switching signal for the third switch (i.e., switch  203 C or switch  603 C). 
     The technical effects and benefits of exemplary embodiments include a multilevel rectifier having a reduced number of components and reduced complexity. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. While the description of the present invention has been presented for purposes of illustration and description, it is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications, variations, alterations, substitutions, or equivalent arrangement not hereto described will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. Additionally, while various embodiment of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.