Abstract:
Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit under 35 USC 119(e) of U.S. provisional application No. 62/144,611 filed Apr. 8, 2015, the contents of which are herein incorporated by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to the field of precision timing, and in particular to a digital phase locked loop arrangement with master clock redundancy, for example, for use in telecommunications. The invention also relates to a method of implementing master clock redundancy in a digital phase locked loop. 
       BACKGROUND OF THE INVENTION 
       [0003]    Most telecom/datacom systems are implemented with a number of digital/mixed signal integrated circuits (ICs), which require an accurate and stable clock source for normal operations. This clock is typically generated by a digital phase-locked loop (DPLL), which receives a recovered reference clock from a network port, cleans it from jitter and wander, and then synthesizes the frequencies required by different integrated circuits in the system. When the input reference clock is unavailable, the DPLL may also be operated in the free-run mode, wherein it continues to run without an input reference. 
         [0004]    The DPLL requires a stable master clock, which is generated from an external crystal oscillator (XO) or temperature compensated variants, such as a temperature compensated crystal oscillator (TCXO) or an oven controlled crystal oscillator (OCXO). 
         [0005]    In the case of master clock failure, the DPLL will instantly stop generating an output clock and the whole system will fail. XOs typically have a higher failure rate than ICs, and as such can dominate the overall failure rate of the whole system. 
       SUMMARY OF THE INVENTION 
       [0006]    Embodiments of the invention address the problem of master clock failure by using two or more redundant XOs. When the first XO that feeds the DPLL fails, another XO takes over. 
         [0007]    According to the present invention there is provided a digital phase locked loop arrangement with master clock redundancy, comprising: a plurality of master clock sources generating clock signals; a digital phase locked loop (DPLL) including at least one reference input and a digital controlled oscillator (DCO) driven by one of said plurality of master clock sources; clock monitors for monitoring the performance of said master clock sources; a first multiplexer for selecting one of said master clock sources to drive said DCO; and a controller programmed to control said multiplexer to switch said DCO from being driven by a previously selected one of said master clock sources to a newly selected one of said master clock sources upon loss of a clock signal from said previously selected master clock source or when the performance of said previously selected one of said master clock sources falls below a predetermined acceptable level. 
         [0008]    The master clock sources may be crystal oscillators, but they could also be other types of clock source, such as SAW oscillators, MEMS oscillators, atomic clock or any device capable of delivering clock signals with the desired stability. 
         [0009]    A digital controlled oscillator as defined herein means any device that uses a master clock and a digital representation of frequency and/or phase to generate an output clock. This includes gapped clock based implementations combined with an analog phase locked loop (APLL), or a straight fractional-N APLL, or a Digital-to-Time converter (DTC) used in a phase interpolator. 
         [0010]    Typically, the DPLL with have a plurality of reference inputs, of which one can be selected by an input multiplexer. The DPLL can however run in the free-run mode without using any reference input. 
         [0011]    Performance is defined herein as the ability of the crystal oscillators to perform their tasks in a satisfactory manner to enable the DPLL to perform within acceptable limits, for example, to maintain the required degree of frequency stability and accuracy. 
         [0012]    The DPLL can successfully recover from XO failure with minimum effect at the output clock so that devices timed from DPLL do not undergo any adverse effects (no bit errors). 
         [0013]    Embodiments of the invention detect not only when the first XO stops generating a clock but also when the XO drifts in frequency outside an allowed threshold. An example of such failure arises when the oven in an OCXO fails. In this case, the OCXO frequency will slowly drift from the nominal value as the OCXO cools down. 
         [0014]    Embodiments of the invention also compensates for any frequency difference between active and redundant XO during switchover, which will in turn minimize frequency change at the output of DPLL. 
         [0015]    According to another aspect of the present invention there is provided a digital phase locked loop arrangement with master clock redundancy, comprising: a plurality master clock sources generating clock signals; a digital phase locked loop (DPLL) including a digital controlled oscillator (DCO) driven by one of said plurality of master clock sources; clock monitors for monitoring the performance of said master clock sources; a first multiplexer for selecting one of said master clock sources to drive said DCO; and a controller programmed to control said multiplexer to switch said DCO from being driven by a previously selected one of said master clock sources to a newly selected one of said master clock sources upon loss of a clock signal from said previously selected master clock source or when the performance of said previously selected one of said master clock sources falls below a predetermined acceptable level. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    This invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:— 
           [0017]      FIG. 1  is top-level block diagram of a DPLL arrangement with master clock redundancy according an embodiment of the invention; 
           [0018]      FIG. 2  is an algorithm implemented by the state machine (block  111 ) shown in  FIG. 1 ; 
           [0019]      FIG. 3  is a timing diagram showing the switchover when the XO instantly fails; 
           [0020]      FIG. 4  is a timing diagram showing the switchover when the XO slowly drifts in frequency outside the predefined threshold; and 
           [0021]      FIG. 5  is a timing diagram showing the switchover when the XO instantly fails but the digital controlled oscillator (DCO) is fed from an analog phase locked loop (APLL) which multiplies the XO frequency. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0022]    Referring now to  FIG. 1 , the DPLL arrangement with master clock redundancy in accordance with an embodiment of the invention is shown. A DPLL  10  has an input reference selector circuit in the form of selection multiplexer  100 , which selects one of N input signals, Input Ref 1  to Input RefN in response to a selection signal sel 3 . The multiplexer  100  allows the DPLL to be locked to any of several independent reference signals. The DPLL  10  also comprises phase detector  101 , low pass filter  102 , adder  103  and digitally controlled oscillator (DCO)  104 . The output of the DCO  104  is fed back to the phase detector  101 . 
         [0023]    The DPLL  10  needs a stable master clock for normal operation. In this non-limiting example, crystal oscillators (XOs)  105 ,  106 ,  107  provide this clock via a selection multiplexer  112 , which is responsive to a selection sel 1 . Depending on the application, the selected XO clock can be directly used to drive the DCO  104  and other digital circuitry or first multiplied by an analog phase locked loop (APLL)  113 . For this purpose, a multiplexer  114  selects either the output of the multiplexer  112  or the output of an APLL  113  in response to a selection signal sel 2 . The multiplexer  114  would be set on the power up (only once) depending on frequency of XOs. If XOs are high frequency ones (for example, 100 MHz and above) the APLL  113  will be bypassed. If they are lower frequency (which much more common) the internal APLL is need to multiply frequency. 
         [0024]    The arrangement, including the assertion of selection signals sel 1 , sel 2 , is controlled by a controller  111  in the form of a state machine, which may be implemented in software in a processor. In the illustrated embodiment the controller  111  comprises central processing unit (CPU)  120 , input/output block  122 , and memory  124  containing a stored program to implement the functions of the state machine. 
         [0025]    During normal operation, the controller selects one of XOs  105 ,  106 ,  107  via selection signal sel 1  as active to drive the DPLL  10 . The remaining XO(s) are used for backup. 
         [0026]    Clock Monitors  108 ,  109 ,  110 , constantly measure and monitor the frequencies of the XOs and report them to the controller  111 . If the controller  111  determines that the frequency of the active XO  105 ,  106 ,  107  deviates by more than a configurable threshold (both positive and negative thresholds are included), for example exceeds or falls below a predetermined threshold, or fails entirely, the controller  111  will select a new XO via multiplexer  112 . At the same time, the controller  111  will apply a frequency correction to adder  113 , which will cancel out the frequency difference between the active and redundant XOs, thus minimizing any frequency change at the output of the DPLL  10 . The clock monitors  108 ,  109 ,  110  thus serve as performance monitors continually monitoring the performance of their associated crystal oscillators to output an event indication when their performance, in this case frequency stability, departs from a predetermined acceptable level. 
         [0027]    The clock monitors  108 ,  109 ,  110  operate in two different modes, selected by a switch  115 . In the first mode, any selected one of the input reference signals, Input Ref 1  . . . Input RefN, is used to monitor the master clock sources and only two XOs are required. Usually, the input signal that the reference DPLL is locked to is selected because it is usually the best one available. However, if another reference is available it could be used as well. 
         [0028]    In the second mode, three XOs use a majority voting system to determine which XO has failed, without the requirement to make use of one of the input reference signals. With these three clocks three cross measurements are performed. For example if XO 1  drifts outside the threshold, the clock monitor for XO 1  will signal a failure. However, we do not know if XO 1  drifted outside the range or the reference (XO 2 ) measure XO 1  drifted outside the range. To determine which one failed (XO 1  or XO 2 ), XO 2  is checked against XO 3 , and XO 1  is checked against XO 3 . If, for example, XO 1  is the faulty oscillator, it will also show a failure when checked against XO 3 , whereas XO 2  when checked against XO 3  will not show a failure, and XO 3  when checked against XO 1  will show a failure. 
         [0029]      FIG. 2  shows the operation of the state machine in the controller  111 . At step  150  a configurable threshold th is set. At step  151 , the state machine reads the measured frequencies F 1 ( n ), F 2 ( n ) and F 3 ( n ), and responsive to the selected input reference signal checks if one of them exceeds the configurable threshold at step  152 . Preferably, the state machine only returns a positive indication if the threshold is exceeded for a configurable monitoring time. 
         [0030]    If the answer is no, the process flow loops back to the start and a flag will be set to declare that failed XO can no longer be used. Also, an alarm will be generated to the system to report this failure to the operator/user. If the answer is yes, i.e. one of the XOs has exceeded the threshold check, a majority vote is applied at step  153  to determine which XO has failed. A determination is made as step  154  whether the failed XO is currently active (i.e. driving the DPLL). If the answer is no, the state machine will declare a failure of the identified backup XO at step  155  and loop back to the start. If answer is yes, the state machine will select at step  156  an alternate XO  105 ,  106 ,  107  as the active XO to drive the DPLL  104 . It will also compensate for the frequency difference between the failed XOs and the XO that takes over as the active XO. 
         [0031]      FIG. 3  shows a timing diagram of the situation that occurs when the active XO instantly fails and its frequency drops to zero at time t 0 . In this case the state machine  111  instantly switches to an alternative XO, determines the frequency difference D 12  between the new XO (XO 2 ) and the last stored good value for the previously active XO (XO 1 ), and applies this frequency difference to the DCO  104  with opposite polarity via adder  103  to cancel out the frequency disturbance at the output of the DPLL resulting from the frequency difference between the XOs. 
         [0032]      FIG. 4  shows a timing diagram of the situation that occurs when the active XO (XO 1 ) slowly drifts in frequency outside the predefined range. This type of failure might occur, for example, when the oven in an OCXO fails, causing frequency changes (typically increasing) as the OCXO cools down. If the XO used as a reference starts to drift, the threshold will move as well because the threshold is derived from the reference. The majority voting system decides whether or not to declare a failure. The state machine  111  switches to the alternate XO, in this case XO 2 , when the threshold for the XO XO 1  is crossed and applies the frequency difference D 12  with opposite polarity, via adder  103  to the DCO  104  at the same time. The frequency difference D 12  is defined as the difference between the crossed threshold value for XO 1  and the XO 2  frequency value, which is the measured frequency difference between XO 1  and XO 2  just before the frequency switch occurs. 
         [0033]      FIG. 5  shows a timing diagram in situations where the XO frequency is first multiplied by the APLL  113 , and then the output of APLL  113  is used as master clock for the DPLL  10 . When the active XO fails in this case, and the state machine switches between two XOs, the output frequency of APLL  113  will only change gradually, depending on the loop bandwidth of APLL  113 . Because the loop bandwidth is known, the state machine  111  will apply a frequency correction to mimic the response of the APLL  113  but with opposite polarity by determining the frequency change over time and applying the frequency change, with opposite polarity, via adder  103  to the DCO  104  contemporaneously with the changing output frequency of the APLL  113 . 
         [0034]    It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. For example, a processor may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included. The functional blocks or modules illustrated herein may in practice be implemented in hardware or software running on a suitable processor.