Abstract:
A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n&lt;m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.

Description:
This application is a Continuation of application Ser. No. 09/972,117, filed Oct. 5, 2001, which application(s) are incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention generally relates to a semiconductor integrated circuit device and a method of producing the same. More particularly, the present invention relates to a configuration of logic cells of a CMOS-type gate array and a method of producing functional blocks by using the logic cells. 
   2. Related Background Art 
   In recent years, semiconductor integrated circuit devices (hereinafter, referred to as an “LSI”) have tended toward higher integration and higher performance along with a finer process. This causes the development cost and development period of an LSI to increase. Under such circumstances, an LSI including gate array cells is suitable for the shortening of a development period and the reduction in cost or the flexible production, and finds wide applications, because such a method of producing an LSI can be designed with only wiring patterns by using CAD or the like. 
   Hereinafter, the configuration of a conventional gate array LSI will be described with reference to the drawings.  FIG. 9  is a sectional view showing a layout of conventional gate array cells. Reference numerals  940 A and  940 B denote CMOS-type base cells, respectively. Reference numeral  980  denotes N-channel transistor regions or P-channel transistor regions in the base cells  940 A and  940 B, and reference numeral  990  denotes gates. Wiring patterns are formed so as to connect the transistor regions  980  or the gates  990  to first wiring layers  201  through contact VIAs  101 , whereby logic cells are formed. 
   The logic cells  900 A and  900 B constituted as described above have an arbitrary number of connecting pins  954  for connecting the logic cells to each other and are connected to each other through contact VIAs  112 , second wiring layers  202 , contact VIAs  123 , and a third wiring layer  203 . If required, it is possible to form logic cells of multi-layered wiring by connecting the first wiring layers  201  and the second wiring layers  202  through the contact VIAs  112  and the second wiring layers  202  and the third wiring layer  203  through the contact VIAs  123 . In most cases, ordinary logic cells can be formed by using up to third wiring layers  203 . In this case, it is appreciated that the logic cells are connected by using further upper wiring layers. 
   In producing the above-described gate array cells, the process of producing up to the base cells  940 A and  940 B is completed when the logic design of an LSI starts and a mask for wiring layers is produced (master slice system). From then, the remaining wiring process can be carried out, which results in a shortened development period and a reduction in the design cost of an LSI. 
   However, the configuration of the conventional gate array LSI and a production method thereof have the following problems. 
   Multi-layered wiring tends to be increased in the number of the wiring layers along with a recent finer process. For example, as shown in  FIG. 9 , when a functional block  400  is designed with five wiring layers and the logic cells  900 A and  900 B composed of a gate array have three wiring layers including connections between the logic cells, the logic cell  900 B is connected to the functional block  400  through a contact VIA  134 , a fourth wiring layer  204 , a contact VIA  145 , a fifth wiring layer  205 , and a connecting pin  955 . 
   Therefore, the period of a wiring process increases, and when logic corrections are needed, the number of correction masks increases, which prevents the shortening of a development period and the reduction in design cost that are characteristics of a gate array LSI. 
   SUMMARY OF THE INVENTION 
   It is an object of the present invention to provide a configuration of a semiconductor integrated circuit device and a method of producing the same that can shorten the development period and reduce the development cost when a gate array-type semiconductor integrated circuit device becomes large in scale. 
   The semiconductor integrated circuit device of the present invention has a basic configuration including a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, wherein gate array type logic cells are composed of the base cells and the wiring layers. In order to solve the above-described problem, wiring within and between the logic cells is constituted by using only upper n (n&lt;m) wiring layers among the m wiring layers. Thus m is defined as the total number of the wiring layers used for forming the logic cells, constituting the wiring and so forth. 
   It is preferable that a connection cell having contact VIAs and wiring patterns disposed immediately above the contact VIAs and connected thereto are included in the lower (m−n) wiring layers, and the contact VIAs are disposed at positions corresponding to at least one grid of the base cells. 
   In the same way, a power supply cell including contact VIAs and wiring patterns connected to the contact VIAs and cells adjacent thereto also can be included in the lower (m−n) wiring layers, and the contact VIAs are disposed at positions corresponding to at least one grid of a power supply in the base cells. 
   In addition, a GND cell including contact VIAs and wiring patterns connected to the contact VIAs and cells adjacent thereto also can be included in the lower (m−n) wiring layers, and the contact VIAs are disposed at positions corresponding to at least one grid of a GND in the base cells. 
   In the above-described configuration, the semiconductor integrated circuit device also can be used by combining two or more kinds of connection cells, a power supply cell or a GND cell. 
   The method of producing a semiconductor integrated circuit device according to the invention is intended to produce the device having the above-mentioned configuration. The method includes preparing combinations LIB_K of the logic cells including the above-described connection cells. Each of the combinations LIB_K includes K connection cells in which K indicates one of integers from 1 to (m−n−1). The method further includes determining a layout of the elements for composing the device in the following manner. First, wiring layers used for wiring are determined and the combinations LIB_K including the connection cells corresponding to the determined wiring layers is selected. Then, an arrangement of the logic cells is determined, and after the logic cells roughly are wired, a wiring congestion degree is determined. Then, when the wiring congestion degree is higher or lower than a predetermined range, the logic cells are rearranged and roughly wired repeatedly by varying parameters of the wiring layers and selecting the combinations LIB_K for use again. When the wiring congestion degree is determined to be within an appropriate range, the logic cells are wired in detail. This allows the connection cells to be added or deleted automatically in accordance with the wiring congestion degree. 
   According to the method of producing a semiconductor integrated circuit device of the present invention having another configuration, a semiconductor integrated circuit device is produced that has a configuration in which any one, or a combination of two or more kinds of the connection cells, the power supply cell, or the GND cell is inserted into the lower (m−n) wiring layers and includes at least one functional block having a determined layout. Connection between the logic cells and the functional blocks, or between the functional blocks is conducted by using only the upper n (n&lt;m) wiring layers among m wiring layers. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a sectional view showing a layout of gate array cells of Embodiment 1. 
       FIG. 2  is a sectional view showing a layout of gate array cells of Embodiment 2. 
       FIGS. 3A to 3C  show a configuration of a connection cell in the gate array cells in  FIG. 2 :  FIG. 3A  is a plan view of a base cell;  FIG. 3B  is a plan view of a connection cell; and  FIG. 3C  is a plan view showing a stacked state of  FIGS. 3A and 3B . 
       FIG. 4  is a sectional view showing a layout of gate array cells of Embodiment 3. 
       FIGS. 5A to 5C  show a configuration of a power supply cell in the gate array cells in  FIG. 2 :  FIG. 5A  is a plan view of the base cell;  FIG. 5B  is a plan view of the power supply cell; and  FIG. 5C  is a plan view showing a stacked state of  FIGS. 5A and 5B . 
       FIG. 6  is a flow chart showing a method of producing an LSI of Embodiment 4. 
       FIG. 7  is a sectional view showing a configuration of wiring between functional blocks produced by a method of producing an LSI of Embodiment 5. 
       FIG. 8  is a plan view showing the configuration of wiring between the functional blocks in  FIG. 7 . 
       FIG. 9  is a sectional view showing a layout of conventional gate array cells. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   An LSI and a method of producing the same according to the present invention will be described by way of embodiments with reference to  FIGS. 1 to 8 . Components having the same configuration and function as those of the prior art shown in  FIG. 9  are denoted with the same reference numerals as those therein, and the description thereof will not be repeated here. 
   Embodiment 1 
     FIG. 1  is a sectional view showing a layout of an LSI of Embodiment 1. Logic cells  100 A and  100 B have a configuration in which second wiring layers  202  and third wiring layers  203  are added to the logic cells  900 A and  900 B in  FIG. 9 . First wiring layers  201  and second wiring layers  202 , and the second wiring layers  202  and third wiring layers  203 , are connected to each other through contact VIAs  112  and contact VIAs  123 , respectively. Connecting pins  954  are formed at the top portions. The logic cells  100 A and  100 B are connected to each other through contact VIAs  134 , fourth wiring layers  204 , contact VIAs  145 , and a fifth wiring layer  205   a . The logic cell  100 B is connected to a functional block  400  through a fifth wiring layer  205   b  and a connecting pin  955 . 
   As described above, only three wiring layers are disposed in the conventional logic cell regions, whereas five wiring layers are disposed in the regions of the logic cells  100 A and  100 B, and the logic cells  100 A and  100 B are formed by using up to the lower three wiring layers. By using the upper two wiring layers for connecting the logic cells to each other, a diffusion process up to the third wiring layer can be completed until the logic design of an LSI starts and a mask for the wiring layers is produced. Therefore, it becomes possible to prevent an increase in the production period for an LSI and the number of correction masks, caused by the increase of a number of wiring layers. 
   Embodiment 2 
     FIG. 2  is a structural view showing a layout of an LSI of Embodiment 2. In the present embodiment, in the regions of the logic cells  100 A,  100 B, and  100 C, since five wiring layers are arranged, and connection cells  200 A and  200 B are inserted into lower two layers, upper three wiring layers can be corrected. 
     FIG. 3B  shows a configuration of a connection cell  200  ( 200 A or  200 B in  FIG. 2 ). The connection cell  200  is composed of contact VIAs  220  ( 101  or  112  in  FIG. 2 ) and wiring patterns  230  ( 201 A or  202 B in  FIG. 2 ) disposed immediately above the contact VIAs  220  and connected thereto. The contact VIAs  220  are disposed at positions corresponding to arbitrary grids  210  of base cells  940  ( 940 A,  940 B, or  940 C in  FIG. 2 ) as shown in  FIG. 3A . In  FIG. 3A , reference numeral  240  denotes a power supply line and reference numeral  250  denotes a ground line.  FIG. 3C  shows a stacked state of the base cell  940  in  FIG. 3A  and the connection cell  200  in  FIG. 3B . The line A-A in  FIG. 3C  shows a position of a cross section shown in  FIG. 2 . 
   As shown in  FIG. 2 , in the logic cells  100 A,  100 B, and  100 C, the base cells  940 A,  940 B and  940 C are connected to the third wiring layers  203  through the connection cells  200 A and  200 B and the contact VIAs  123 , respectively. The logic cells  100 A and  100 C are provided with the connecting pins  954  on the top surfaces. The logic cells  100 A and  100 C are connected to each other through the contact VIAs  134 , the fourth wiring layers  204 , the contact VIAs  145 , and the fifth wiring layer  205 . 
   Embodiment 3 
     FIG. 4  shows a layout of an LSI of Embodiment 3. In the present embodiment, a power supply cell  300  is inserted for the purpose of strengthening a power supply line in accordance with previously calculated power consumption of a logic block. Thus, it becomes possible to arrange up to five wiring layers while only the upper three wiring layers are allowed to be corrected. 
     FIG. 5B  shows a configuration of the power supply cell  300 . The power supply cell  300  is composed of the contact VIAs  112  and a wiring pattern  302  connected to the contact VIAs  112  and cells adjacent thereto. The contact VIAs  112  are disposed at positions corresponding to at least one grid  210  in the power supply line  240  in the base cell  940  shown in  FIG. 5A .  FIG. 5C  shows a stacked state of the base cell  940  in  FIG. 5A  and the power supply cell  300  in  FIG. 5B . The line B-B in  FIG. 5C  indicates a position of a cross section shown in  FIG. 4 . 
   A GND cell also can be constituted in the same way as in the power supply cell  300 . The GND cell is composed of contact VIAs disposed at a grid of the GND in the base cell and wiring patterns connected to the contact VIAs and cells adjacent thereto, whereby the GND cell can be used in the same way as in the above-described power supply cell  300 . 
   In  FIG. 4 , the wiring patterns are connected to the cells adjacent thereto in the Y-direction. However, even when the wiring patterns are connected to the cells adjacent thereto in the X-direction, a similar function can be obtained. 
   Embodiment 4 
     FIG. 6  is a flow chart showing a method of producing an LSI and an automatic layout flow in the production process in Embodiment 4. According to the production method of the present embodiment, when the connection cells described in Embodiment 2 or 3 are inserted into the LSI of Embodiment 1, the connection cells automatically are added or deleted in accordance with a wiring congestion degree. 
   According to the method, combinations LIB_K of the logic cells including the connection cells are prepared. Each of the combinations LIB_K includes K connection cells (K indicates one of integers from 1 to (m−n−1)), in accordance with each of the number of connection cells to be inserted. For example, the combination LIB — 1 includes one connection cell, the combination LIB — 2 includes two connection cells, and the combination LIB_(m−n−1) includes (m−n−1) connection cells. In the production process, each of the combinations LIB_K thus prepared is selected for use. 
   First, a net list and a parameter file are input (Steps S 1  and S 2 ). Next, based on a value of the parameter file, wiring layers are determined and the combinations LIB_K appropriate for the wiring layers are selected for use (S 3 ). Then, logic cells are arranged (S 4 ), and roughly are wired (S 5 ). Here, the wiring congestion degree is determined (S 6 ). When the wiring congestion degree is higher or lower than a predetermined range, parameters of the wiring layers are varied (S 7 ) and the wiring layers are determined and the combinations LIB_K are selected again (S 3 ). Logic cells are arranged (S 4 ) and roughly wired (S 5 ). When the wiring congestion degree is determined to be within an appropriate range (S 6 ), the logic cells are wired in detail (S 8 ). Mask data is output based on the results (S 9 ). 
   As described above, a necessary wiring resource can be secured by automatically varying the number of layers of the connection cells, based on the wiring congestion degree (net/base cell, or the like) between the logic cells. 
   Embodiment 5 
     FIG. 7  shows a configuration of wiring between functional blocks produced by a method of producing an LSI of Embodiment 5. Connecting pins  951  and  952  of a logic block  403  in a gate array type LSI of the present embodiment are positioned above third wiring layers. However, connecting pins of an existing functional block  401  composed of five wiring layers and connecting pins of an existing functional block  402  composed of two wiring layers, for example, are not necessarily formed on the same layer as that of connecting pins  951  and  952  of the logic block  403 . Since the logic block  403  is designed last, when a gate array type LSI is designed, the design of the logic block  403  may cause the connection between the functional block  401  and the functional block  402  or the logic block  403  to be changed. Therefore, in the present embodiment, such a matter can be dealt with by specifying wiring layers in accordance with the logic block  403 , that is, by allowing inter-block wiring to be conducted in the upper three layers. 
   A specific example of the above wiring method will be described in which the functional blocks  401  and  402  are constituted in a first wiring layer and connecting pins  957  and  958  are connected. 
   First, as shown in  FIG. 8 , wiring prohibited regions  502  of lower two layers are provided around the functional blocks  401  and  402  formed on the silicon substrate  404 . In an inter-block wiring region  405  upper three wiring layers are used at portions where the wiring prohibited regions  502  cross the wiring. That is to say, as shown in  FIG. 7 , the inter-block wiring region  405  is wired by the first wiring layers  201 , the contact VIAs  112 , the second wiring layers  202 , the contact VIAs  123 , and the third wiring layer  203 . Reference numeral  501  in  FIG. 8  denotes layer transfer regions. 
   In the same way, a connection between a connecting pin  953  of the functional block  402  and a connecting pin  952  of the logic block  403 , and a connection between a connecting pin  956  of the functional block  401  and a connecting pin  951  of the logic block  403  also are made by using upper three wiring layers. 
   By using the above-described method of producing an LSI, when m wiring layers are included, it is possible to use n-th (n&lt;m) or above wiring layers in at least one portion, so that inter-block wiring is corrected in upper n wiring layers. 
   As described above, according to the present invention, logic cells can be connected by varying upper n wiring layers, although logic cells are connected by using all wiring layers in the prior art. Consequently, when logic or wiring of an LSI composed of multi-layered wiring should be varied, only a few mask corrections are needed, so that a development period can be shortened and the development cost can be reduced. 
   The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.