Abstract:
An audio codec control technique is provided with improved multichannel data ordering capabilities. An audio codec controller comprises a first interface unit for performing data transfer to and from an audio codec, a second interface unit for performing data transfer from an external memory, and a data buffer for buffering data received from the external memory via the second interface unit. The controller further comprises a capture register for receiving from the data buffer data requested by the audio codec, and temporarily storing the received data. The second interface unit is connected to receive temporarily stored data from the capture register. The operation of the audio codec controller may be done in several operational modes including 2, 4, and 6-channel full-rate and half-rate modes.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention generally relates to audio codec controllers such as AC (Audio Codec) &#39;97 controllers, and in particular to the data transfer between such controllers and an audio codec.  
           [0003]    2. Description of the Related Art  
           [0004]    Present computer systems such as personal computers are usually provided with audio capabilities and include sound cards and speakers. PC (Personal Computer) audio hardware and applications are advancing fast, and there are a lot of fascinating new applications, including 3D gaming with positional audio, DVD playback, internet telephony, voice-recognition software, and so on. Many of these new applications require expensive sound cards while other applications can be used with low cost hardware.  
           [0005]    Many motherboards include a specific sound chip on-board for providing built in audio capabilities. Other motherboards can provide such functionality without requiring the provision of a specific integrated circuit chip that does all the audio signal processing. Instead, such motherboards may include circuitry in compliance with the AC &#39;97 specification. The AC &#39;97 functionality may be performed by the chipset on the motherboard, e.g. by a southbridge device.  
           [0006]    The AC &#39;97 specification defines an audio codec architecture and digital interface which is specifically designed for implementing audio and modem I/O functionality in mainstream PC systems. In such architecture, an interface is provided that allows audio data to be processed in a rather inexpensive additional chip which includes an analog-to-digital converter together with some additional analog circuits. The real audio data processing is however done by the CPU (Central Processing Unit) of the computer system. An AC &#39;97 architecture is shown in FIG. 1. The system includes an audio codec controller  110  which is also referred to as digital controller hereafter, and a set of, e.g., two codecs  180 ,  190 . The codecs  180 ,  190  may be located on a circuit board or card  120 , and there may be a primary codec  180  and a secondary codec  190 . The codecs may be audio codecs, modem codecs, or combined audio/modem codecs, and both codecs  180 ,  190  may be provided in one or two physically separate integrated circuit chips.  
           [0007]    The codecs  180 ,  190  perform digital-to-analog and analog-to-digital conversion, mixing, and analog I/O for audio (or modem) purposes, and always function as slaves to the audio codec controller  110 . The controller is typically either a PCI (Peripheral Component Interconnect) accelerator or a controller that comes integrated within core logic chipsets. The digital link that connects the audio codec controller  110  to the codecs  180 ,  190  is a bi-directional, 5-wire, serial TDM (Time Division Multiplexing) format interface, referred to as AC-link. The AC-link supports connections between a single audio codec controller  110  and up to four codecs  180 ,  190 .  
           [0008]    The audio codec controller  110  is further connected to the host memory  100  of the computer system, e.g. by means of a PCI bus. In the audio codec controller  110 , there are respective interface controllers  130 ,  140  for controlling the data transfer at both interfaces. That is, the digital controller  110  comprises a bus master controller  130  and an AC-link interface controller  140 .  
           [0009]    As can be seen from FIG. 1, the audio codec controller  110  further comprises an input FIFO (first-in-first-out) buffer  150  and an output FIFO buffer  160  which are controlled by the FIFO controller  170 . The buffers  150 ,  160  store data relating to one of the two independent data streams of the incoming and outgoing traffic. That is, the bus master controller  130  accesses the host memory  100  to receive audio data needed by one of the codecs  180 ,  190 . The received data are stored in the output FIFO buffer  160  and are there made available to the AC-link interface controller  140  to be sent to the codec  180 ,  190 . The input FIFO buffer  150  performs the corresponding function with respect to the data stream which originates at the codecs  180 ,  190 .  
           [0010]    In such audio sub-systems, there may be more than two channels in use. Particularly in 6-channel configurations, there may be separate channels for audio left-front, right-front, left-rear, right-rear, center-front, and subwoofer. In such cases, the handling of the output FIFO buffer  160  by FIFO controller  170  becomes rather difficult, and in particular the AC-link interface controller  140  needs to be provided with complicated hardware circuitry for accessing the output FIFO buffer  160  when building the serial data for the AC-link. This may lead to significant circuit development and manufacturing costs.  
         SUMMARY OF THE INVENTION  
         [0011]    An improved audio codec control technique is provided where the data transfer in particular in audio multichannel conditions may be done more efficient and reliable.  
           [0012]    In one embodiment, an audio codec controller is provided that comprises a first interface unit for performing data transfer to and from an audio codec, a second interface unit for performing data transfer from an external memory, and a data buffer for buffering data received from the external memory via the second interface unit. The audio codec controller further comprises a capture register for receiving from the data buffer data requested by the audio codec, and temporarily storing the received data. The second interface unit is connected to receive temporarily stored data from the capture register.  
           [0013]    In another embodiment, an integrated circuit chip is provided that has audio codec control functionality. The integrated circuit chip comprises first interface circuitry for performing data transfer to and from an audio codec, second interface circuitry for performing data transfer from an external memory, and a data buffer for buffering data received from the external memory via the second interface circuitry. The integrated circuit chip further comprises a capture register for receiving from the data buffer data requested by the audio codec, and temporarily storing the received data. The second interface circuitry is connected to receive temporarily stored data from the capture register.  
           [0014]    In a further embodiment, there may be provided an audio codec control method. The method comprises receiving data from an external memory, buffering the receiving data in a data buffer, temporarily storing buffered data in a capture register in accordance with a request from an audio codec, and transferring temporarily stored data from the capture register to the audio codec independent of an operation of the data buffer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    The accompanying drawings are incorporated into and form a part of the specification for the purpose of explaining the principles of the invention. The drawings are not to be construed as limiting the invention to only the illustrated and described examples of how the invention can be made and used. Further features and advantages will become apparent from the following and more particular description of the invention, as illustrated in the accompanying drawings, wherein:  
         [0016]    [0016]FIG. 1 is a system diagram illustrating the components of a conventional AC &#39;97 system;  
         [0017]    [0017]FIG. 2 is a system diagram illustrating an AC &#39;97 compliant system according to an embodiment;  
         [0018]    [0018]FIG. 3 is a flowchart illustrating the main process of performing an audio-out data transfer according to an embodiment;  
         [0019]    [0019]FIG. 4 illustrates a sequence of data frames on the AC-link in a full-rate 2-channel configuration;  
         [0020]    [0020]FIG. 5 illustrates a sequence of data frames on the AC-link in a half-rate 2-channel configuration;  
         [0021]    [0021]FIG. 6 illustrates a sequence of data frames on the AC-link in a full-rate 4-channel configuration;  
         [0022]    [0022]FIG. 7 illustrates a sequence of data frames on the AC-link in a half-rate 4-channel configuration;  
         [0023]    [0023]FIG. 8 illustrates a sequence of data frames on the AC-link in a full-rate 6-channel configuration;  
         [0024]    [0024]FIG. 9 illustrates a sequence of data frames on the AC-link in a half-rate 6-channel configuration;  
         [0025]    [0025]FIG. 10 is a flowchart illustrating the process of operating an audio codec controller according to an embodiment; and  
         [0026]    [0026]FIG. 11 is a flowchart illustrating an example of the FIFO handling performed in the process of FIG. 10. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]    The illustrative embodiments of the present invention will be described with reference to the figure drawings wherein like elements and structures are indicated by like reference numbers.  
         [0028]    Referring now to the drawings and particularly to FIG. 2 which illustrates an audio system according to an embodiment, the system differs from that of FIG. 1 mainly in that a capture register  200  is provided in the audio-out data path. The capture register  200  is connected to the output FIFO buffer  160  to receive from the buffer data that were previously requested by one of the codecs  180 ,  190 . Further, the capture register  200  is connected to AC-link interface controller  140  to supply data that is temporarily stored in the capture register  200 , to the interface controller  140 . Thus, without requiring to modify the FIFO controller  170 , the provision of the capture register  200  may allow to efficiently perform a packet-oriented data transfer on the AC-link while still controlling the output FIFO buffer  160  on a sample-oriented basis. This will become more apparent from the more detailed description below showing examples of operational modes and operation methods in the audio codec controller  210  of FIG. 2.  
         [0029]    Several configurations of the audio sub-system of the present embodiment are possible for performing audio traffic as 2, 4 or 6-channel data stream. In the 2-channel mode, the primary codec  180  has two channels while a secondary codec  190  is either not existent or is in an idle mode. In the 4-channel version, the primary codec  180  may have four channels with the secondary codec  190  being not existent or idle. Alternatively, the primary codec  180  as well as the secondary codec  190  may each have two channels. Likewise, two different 6-channel versions may exist, one where the primary codec  180  has two channels and the secondary codec  190  four channels, and the other where the primary codec  180  has four channels and the secondary codec  190  two channels.  
         [0030]    The output FIFO buffer  160  may be sub-divided into six buffer units, each for storing data relating to one of the possible audio-out channels: left-front, right-front, left-rear, right-rear, center-front, and subwoofer. Alternatively, the output FIFO buffer  160  may store data received from the host memory  100  in much the same way as the data were stored in the host memory  100 . In the present embodiment, the output FIFO buffer  160  stores one sample for each channel, where a sample is represented by a word of 16 bits. As the audio codec controller  210  of the present embodiment supports 2, 4 and 6-channel configurations, the number of channels is even at any time so that any access to the output FIFO buffer  160  may be done in a double word manner. As one word represents one sample, the output FIFO buffer  160  is accessed on a sample-oriented basis. For the example of a 6-channel configuration, the following table shows the kind of capturing the data samples in the host memory  100  and the output FIFO buffer  160 :  
                                                       sample 2   sample 1           sample 4   sample 3           sample 6   sample 5           sample 2   sample 1           sample 4   sample 3           sample 6   sample 5                      
 
         [0031]    When preparing for the data transfer over the AC-link, the samples need to be reordered since the assignment of samples to time slots in the serial data stream to the codecs  180 ,  190  may differ from one multi-channel configuration to another one. An example of respective sample orders is shown in the table below:  
                                               audio       2-channel   4-channel   6-channel       channel   timeslot   configuration   configuration   configuration                   left front   3   1   1   1       right front   4   2   2   2       center front   6           3       left rear   7       3   5       right rear   8       4   6       subwoofer   9           4                  
 
         [0032]    As apparent therefrom, for a given 2, 4 or 6-channel audio stream the audio bus master controller  130  expects each sample compound to start with the left-front sample. However, the sample order then depends on the specific channel configuration. By providing the capture register  200 , any possible data ordering requirement can be easily accomplished in the different multi-channel applications, and the packet-oriented data transfer on the AC-link can be performed simply by multiplexing the temporarily stored, consistent data with respect to the time slots.  
         [0033]    Turning now to FIG. 3, the main process of performing the audio-out data transfer is depicted. In step  300 , the audio codec controller  210  receives a request from the primary or an (optional) secondary codec  180 ,  190  for audio samples. The requested samples are then read from the output FIFO buffer  160  into the capture register  200  (step  310 ). Finally, the samples are sent to the codec in step  330 .  
         [0034]    As apparent from flowchart of FIG. 3, there may be different operational modes which may influence the manner of how the requested data is sent to the codec. These operational modes may be a variable sample mode, a down sample mode etc. Moreover, the operational modes may be transfer modes differing in the number of supported channels or transfer rates. Then, the output FIFO buffer  160  may buffer the data received from the host memory  100  in at least two different configurations, where each configuration relates to one of the data transfer modes. The output FIFO buffer  160  may further buffer groups of audio data samples where the number of audio data samples in each group corresponds to the number of supported audio channels. Additionally, the sample pairs (double words) for the left-front/right-front, center-front/subwoofer, and left-rear/right-rear channels can be swapped each other by programming.  
         [0035]    As the audio codec controller  210  of the present embodiment may be operated in different operational modes, the process depicted in FIG. 3 includes a step  320  of determining the operational mode, and the sending step  330  is performed dependent on the determined mode.  
         [0036]    In another embodiment, the operational mode is loaded and configured by the driver at the very beginning of the process. Moreover, the step  320  of determining the operational mode may be performed before step  310  of reading the requested samples from the output FIFO buffer  160  into the capture register  200 . This allows for even making step  310  dependent on the determined operational mode.  
         [0037]    An example of how the sending of samples over the AC-link may be done dependent on an operational mode, will now be discussed with reference to FIGS.  4  to  9 .  
         [0038]    In these, figures, data transfer modes that differ in the supported transfer rates, are applied in 2, 4 and 6-channel configurations. In the full-rate transfer mode, all of the samples are sent in one frame. In the half-rate transfer mode, two frames are used with the left-front, center-front, and left-rear samples being transferred in one frame and the right-front, right-rear, and subwoofer samples being transferred in the following frame. In detail, FIG. 4 illustrates the case of 2-channel configuration where the data is transferred in full-rate mode. FIG. 5 is the corresponding diagram illustrating the half-rate mode, and FIGS. 6 and 7, and  8  and  9  relate to the 4-channel and 6-channel configurations, respectively.  
         [0039]    In the example of half-rate data transmissions, the capture register  200  is filled from the output FIFO buffer  160  with the audio samples of all channels of the respective configuration. The AC-link interface controller  140  is however caused to access the capture register  200  twice, for partially transferring the temporarily stored data in one frame, and then transferring the remaining samples in the following frame. That is, the capture register  200  allows a packet-oriented data transfer over the AC-link independent on the operation of the output FIFO buffer  160 .  
         [0040]    In the present embodiment, the AC-link interface controller  140  further allows for sending one-word, i.e. 16-bit, samples via the serial AC-link although the time slots are 20 bits wide. In this case, the 16-bit samples are transferred as the 16 most significant bits of each 20 bit slot, with the low order bits discarded for incoming data and filled with zeros for output data. Moreover, if there is an optional secondary codec  190  provided in the system, the AC-link interface controller  140  may assign input slots in a completely orthogonal manner, i.e. no two data slots at the same location will be valid on both codec signals.  
         [0041]    Turning now to FIG. 10, another embodiment of operating the audio codec controller  210  is depicted. In step  1000 , the controller  210  checks whether the codec  180 ,  190  is ready. If so, the valid slot requests are stored in step  1010  and the operational mode is determined in step  1020 . It is then checked in step  1030  whether samples are present in the capture register  200 . If no samples are present, a FIFO handling routine  1040  is performed for refilling the capture register  200 . Finally, one or more frames are sent to the codec  180 ,  190  dependent on the operational mode which was previously determined (step  1050 ).  
         [0042]    While the FIFO handling routine  1040  is depicted in the flowchart of FIG. 10 as being performed directly before sending the frames, the FIFO handling may also be done completely independently from the process shown in FIG. 10. Moreover, the FIFO handling routine may include a buffer under-run policy that guarantees that existing data will be held until the new data is available. Thus, for each new packet requested from the codec  180 ,  190 , a defined and stable data status is achievable without any data corruption and inconsistency for the codec.  
         [0043]    [0043]FIG. 11 shows an example of a FIFO handling routine. In step  1100 , the FIFO controller  170  determines whether the output FIFO buffer  160  has entered an under-run condition. If so, the bus master controller  130  requests new data from host memory  100  (step  1110 ), and the requested data is received in step  1120 .  
         [0044]    While the invention has been described with respect to the physical embodiments constructed in accordance therewith, it will be apparent to those skilled in the art that various modifications, variations and improvements of the present invention may be made in the light of the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. In addition, those areas in which it is believed that those of ordinary skill in the art are familiar, have not been described herein in order to not unnecessarily obscure the invention described herein. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrative embodiments, but only by the scope of the appended claims.