Abstract:
A transceiver in a full duplex communication system includes a hybrid circuit for transmitting a transmission signal or receiving a receive signal via the channel, the hybrid circuit includes an echo cancellation device for removing transmission signal components from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC is directly connected to the hybrid circuit for amplifying the processed receive signal, wherein a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation-in-part of U.S. application Ser. No. 10/709,935, filed Jun. 7, 2004, entitled “ECHO CANCELLATION DEVICE FOR FULL DUPLEX COMMUNICATION SYSTEMS”, which issued on Dec. 4, 2007, as U.S. Pat. No. 7,304,961, U.S. application Ser. No. 10/711,294, filed Sep. 8, 2004, entitled “ECHO CANCELLATION DEVICE FOR FULL DUPLEX COMMUNICATION SYSTEMS”, which issued on Dec. 11, 2007, as U.S. Pat. No. 7,307,965, U.S. application Ser. No. 10/904,338, filed Nov. 4, 2004, entitled “ECHO CANCELLATION DEVICE FOR FULL DUPLEX COMMUNICATION SYSTEMS”, which issued on Jun. 30, 2009, as U.S. Pat. No. 7,554,933, which are cooperated by reference herein. 
    
    
     BACKGROUND OF INVENTION 
     1. Field of the Invention 
     The present invention relates to a transceiver, and more particularly, to a transceiver for a full duplex communication system. 
     2. Description of the Prior Art 
     As technology advances, network applications have become more and more popular.  FIG. 1  depicts a simplified schematic diagram of a conventional transceiver  100  in a channel of a fast Ethernet device. The transceiver  100  comprises a hybrid circuit  115 , which is a three-end device. The transceiver  100  transmits a transmission signal Tx to the channel  110  via the hybrid circuit  115 . A receive signal Rx transmitted from the other end of the channel  110  mixes with the signal Tx to form a signal Rx+Tx. The hybrid circuit  115  comprises an echo canceller  130  for removing the components of the signal Tx from the signal Rx+Tx in the channel  110  in order to obtain the receive signal Rx. The transceiver  100  further comprises an analog front-end (AFE) circuit  140  coupled to the hybrid circuit  115  for receiving and processing the receive signal Rx. In practical applications, the hybrid circuit  115  further comprises a digital to analog converter (DAC)  120 . 
     However, an unavoidable parasitic capacitance effect in practical implementations is disregarded and therefore the echo effect of the transceiver  100  cannot be effectively reduced. Additionally, the open-loop output impedance of the hybrid circuit  115  is a finite resistance Ra and the input impedance of the AFE circuit  140  is a finite resistance Rb. Accordingly, the signal insertion loss is Ra/(Ra+Rb) and the equivalent output impedance of the stage prior to the AFE circuit  140  is Ra//Rb. The signal-to-noise ratio (SNR) of the receive signal Rx is thereby reduced. Therefore, the conventional transceiver  100  includes a unit gain buffer  170  prior to the AFE circuit  140  to provide a large input impedance and a tiny output impedance in order to drive the next stage, i.e., the AFE circuit  140 , and to prevent any signal from passing back from the AFE circuit  140  to the hybrid circuit  115 . 
     Furthermore, in order to increase the working frequency of the sample and hold circuit  160 , the conventional transceiver  100  also includes a unit gain buffer  180  between the AFE circuit  140  and a sample and hold circuit  160  to provide a small output impedance to reduce the equivalent resistance of the RC network. 
     The transceiver of the prior art utilizes unit gain buffers to drive next stages and this results in increased complexity and cost of the circuit, and the noise level and harmonic distortion of the active elements within are raised. Hence the signal quality decreases. 
     SUMMARY OF INVENTION 
     It is therefore an objective of certain claimed embodiments to provide a transceiver having simple circuit design to solve the above problem. 
     According to a preferred embodiment, a transceiver in a communication system is disclosed. The transceiver includes: a hybrid circuit coupled to a channel for transmitting a transmission signal and receiving a receive signal via the channel, the hybrid circuit having an echo cancellation device for removing the transmission signal from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC directly connected to the hybrid circuit for amplifying the processed receive signal, and a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground. 
     According to certain embodiments, the parasitic capacitance effect is minimized and the echo cancellation performance is optimized. Furthermore, no unit gain buffers are required to drive next stages so that the complexity, the cost, and the power consumption are reduced. In addition, the noise and harmonic distortion of active elements are decreased and the signal quality is improved. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a simplified schematic diagram of a transceiver in a channel of a fast Ethernet device according to the prior art. 
         FIG. 2  is a schematic diagram of a portion of the transceiver of  FIG. 1 . 
         FIG. 3  is a small signal model of the hybrid circuit of  FIG. 1 . 
         FIG. 4  is another small signal model of the hybrid circuit of  FIG. 1 . 
         FIG. 5  is a simplified schematic diagram of a transceiver according to a first embodiment of the present invention. 
         FIG. 6  is an equivalent circuit diagram of the transceiver of  FIG. 5 . 
         FIG. 7  is a simplified equivalent circuit diagram of another embodiment the transceiver of  FIG. 5 . 
         FIG. 8  is a simplified equivalent circuit diagram of a line driver. 
         FIG. 9  is a simplified schematic diagram of a transceiver according to a second embodiment of the present invention. 
         FIG. 10  is an equivalent circuit diagram of the transceiver of  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  depicts a small signal model of the hybrid circuit  115  of  FIG. 1 . In  FIG. 3 , the equivalent circuit of the DAC  120  is a current source Id, the equivalent circuit of the echo canceller  130  is a current source Ic, and Zo is the equivalent output impedance of the DAC  120 . In order to achieve echo cancellation for the AFE circuit  140 , the effect caused by the output of the current source Id must be canceled by the output of the current source Ic. From the small signal model shown in  FIG. 3 , the following formula can be obtained:
   Vi=−[IdZo +( Zo+Rp ) Ic]   (1) 
     In order to cancel the echo effect, Vi should equal 0, which satisfies:
 
 IdZo +( Zo+Rp ) Ic= 0  (2)
 
     From formula (2), it is known that the relationship between Ic and Id is: 
     
       
         
           
             
               
                 
                   Ic 
                   = 
                   
                     
                       
                         - 
                         Zo 
                       
                       
                         Rp 
                         + 
                         Zo 
                       
                     
                     ⁢ 
                     Id 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Adding an impedance Zi between an echo free point and a grounding point into  FIG. 3 , the small signal model of the hybrid circuit  115  shows in  FIG. 4 . At that moment, the following formula is obtained by solving KVL or KCL equations: 
     
       
         
           
             
               
                 
                   Vi 
                   = 
                   
                     
                       - 
                       
                         Zi 
                         ⁡ 
                         
                           [ 
                           
                             IdZo 
                             + 
                             
                               
                                 ( 
                                 
                                   Zo 
                                   + 
                                   Rp 
                                 
                                 ) 
                               
                               ⁢ 
                               Ic 
                             
                           
                           ] 
                         
                       
                     
                     
                       Rp 
                       + 
                       Zi 
                       + 
                       Zo 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Similarly, if Vi equals 0, it also satisfies formula (2):
 
 IdZo +( Zo+Rp ) Ic= 0  (2)
 
     And it also satisfies formula (3): 
     
       
         
           
             
               
                 
                   Ic 
                   = 
                   
                     
                       
                         - 
                         Zo 
                       
                       
                         Rp 
                         + 
                         Zo 
                       
                     
                     ⁢ 
                     Id 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     In other words, if the equivalent current source Ic satisfies formula (3), the echo effect can be completely cancelled, and the impedance Zi can be arbitrary. Accordingly, if the grounding point is replaced with a virtual ground, the above analysis is unchanged. 
     For the unavoidable parasitic capacitance effect of practical implementations in the present invention, the equivalent output impedance Zo is modified to being parallel connection with a load resistor Re, which consists of the matching resistor Rm and the equivalent resistor Rc of the channel, and a parasitical capacitor Ce. The effective output impedance Zo=Re//Ce can be represented as the following formula: 
     
       
         
           
             
               
                 
                   Zo 
                   = 
                   
                     Re 
                     
                       sReCe 
                       + 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     Substitute formula (5) into formula (3) to obtain the following formula: 
     
       
         
           
             
               
                 
                   Ic 
                   = 
                   
                     
                       
                         
                           - 
                           Re 
                         
                         
                           Rp 
                           + 
                           Re 
                           + 
                           sReRpCe 
                         
                       
                       ⁢ 
                       Id 
                     
                     = 
                     
                       
                         H 
                         ⁡ 
                         
                           ( 
                           s 
                           ) 
                         
                       
                       · 
                       Id 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     From formula (6), the relationship between Ic and Id is actually a low pass transfer function H(s). 
       FIG. 5  depicts a schematic diagram of a transceiver  500  of a full duplex communication system according to a first embodiment of the present invention. In the transceiver  500 , the AFE circuit  540  comprises a gain amplifier  542  for adjusting the amplitude of the receive signal to increase the signal gain; and a filter  544  coupled to the gain amplifier  542  for filtering noises or harmonic components of the signal outputted from the gain amplifier  542  and for driving the next stage. Preferably, the gain amplifier  542  is a programmable gain amplifier (PGA) and the filter  544  is an OP-RC filter. 
     The block H(s)  570  shown in  FIG. 6  is a low pass transfer function and can be implemented to satisfy formula (6) by either digital means or analog means. For example, a digital low pass filter can be employed to implement the block H(s). In another embodiment of the present invention, an RC network low pass filter is employed to implement the block H(s). A capacitor of the RC network low pass filter can be a metal stacked-layer capacitor or a parasitic capacitor, and a resistor of the RC network low pass filter can be a MOS transistor of which the resistance depends on the gate voltage. In a preferred embodiment of the present invention, a pull-up current source equivalent to the current source Ia in  FIG. 6  is employed to increase the DC level of Vi and the MOS transistors of the equivalent current source Ic can maintain the operation in the saturation region to avoid signal distortion. The echo cancellation performance of the transceiver  500  of the present invention is thereby improved. In practical implementations, the pull-up current source, which is the equivalent current source Ia can be a fixed current source or an adjustable current source, meaning that the output of the equivalent current source Ia can be a DC or an AC signal with a fixed DC level, or a DC or an AC signal with a DC level corresponding to the magnitude of the current source Ic. 
     As shown in the foregoing illustration, using the low pass filter  570  according to the present invention can minimize the echo effect of the transceiver  500 . 
     In the transceiver  500  of the present invention, the gain amplifier  542  of the AFE circuit  540  is implemented with an OP-RC architecture and the input impedance Zi of the gain amplifier  542  can be a resistor. One terminal of the input impedance Zi is coupled to a node A and the other terminal of the input impedance Zi is coupled to the echo free point of the transceiver  500 . The node A can be regarded as a virtual ground point due to the high loop gain property of the OP-RC architecture. According to the above analysis, the magnitude of the input impedance Zi does not affect the operation of echo cancellation of the low pass filter  570  and the echo canceller  530 . As a result, the ability of adjusting the gain of the gain amplifier  542  is substantially raised. In addition, since the gain amplifier  542  is implemented using the OP-RC architecture, a small output impedance is thereby obtained so that the gain amplifier  542  is an ideal driver stage to drive the next stage such as the filter  544 . Therefore, no unit gain buffer in the transceiver  500  is required to be an intermediate stage between the AFE circuit  540  and its preceding stage. The cost, complexity, power consumption, noise, and harmonic distortion are thereby reduced. 
     In a multi-channel communication system, cross talk easily happens in high frequency. Generally, in a full duplex communication system, the echo residue input to the AFE circuit  540  usually corresponds to high-frequency components. Therefore, the filter  544  is employed in the transceiver  500  to filter the echo residue corresponding to the high-frequency components. In one embodiment, the filter  544  is an OP-RC filter with a small output impedance and drives the next stage. If a sample and hold circuit  560  is configured following the filter  544  and prior to an analog to digital converter (ADC)  550 , the small output impedance of the filter  544  reduces the equivalent time constant of a RC network formed by the sample and hold circuit  560  and therefore the working frequency of the sample and hold circuit  560  is increased. 
     In practical implementations, the capacitance of the parasitic capacitor Ce, the resistance of resistor Rc equivalent to the channel, and the impedance of the matching resistor Rm change with the operating environment, temperature, manufacturing deviations, or other variations. In order to more precisely eliminate the echo, the transceiver  500  of the present invention further comprises an echo residue detector (not shown) coupled to the ADC  550  for detecting the echo residue received. The echo residue detector generates a control signal according to the detected echo residue and outputs the control signal to the low pass filter  570  to adjust the poles of the low pass transfer function H(s) for minimizing the echo residue.  FIG. 7  depicts a simplified equivalent circuit diagram of the above embodiment. 
     In the above embodiments, the hybrid circuit is assumed to operate in current mode. In fact, the concept and architecture of the present invention for eliminating echo can also be applied in a transceiver with a hybrid circuit that operates in voltage mode. 
       FIG. 8  depicts a simplified equivalent circuit diagram of a line driver. Vo′ is the output of the line driver, Rk is a matching resistance, Vo is a transmission signal to be transmitted via a channel, Re is an equivalent load resistor, and Ce is a parasitic capacitance. Considering the effect of the parasitic capacitance, the equivalent output impedance Zo of the line driver is the parallel connection of the load resistor Re and the parasitical capacitor Ce, i.e., Zo=Re//Ce. From the circuit diagram shown in  FIG. 8 , the following formula is obtained: 
     
       
         
           
             
               
                 
                   Vo 
                   = 
                   
                     
                       
                         Zo 
                         
                           Zo 
                           + 
                           Rk 
                         
                       
                       ⁢ 
                       
                         Vo 
                         ′ 
                       
                     
                     = 
                     
                       
                         
                           Re 
                           
                             Rk 
                             + 
                             Re 
                             + 
                             sReRkCe 
                           
                         
                         ⁢ 
                         
                           Vo 
                           ′ 
                         
                       
                       = 
                       
                         
                           h 
                           ⁡ 
                           
                             ( 
                             s 
                             ) 
                           
                         
                         · 
                         
                           Vo 
                           ′ 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
       FIG. 9  is a simplified schematic diagram of a transceiver  900  according to a second embodiment of the present invention. A hybrid circuit of the transceiver  900  comprises a line driver  920  for transmitting a transmission signal to the channel via a matching resistor Rk; a cancellation signal generator  930  coupled to the line driver  920  for generating a cancellation signal according to the transmission signal; and a cancellation module  942  coupled to the line driver  920  and the cancellation signal generator  930  for eliminating the echo caused by the transmission signal. 
     The cancellation signal generator  930  of the present invention generates the cancellation signal according to the signal Vo′ outputted from the line driver  920 . Then the cancellation signal is transmitted to the cancellation module  942 . 
       FIG. 10  depicts an equivalent circuit diagram of the transceiver  900  of the present invention. Preferably, the cancellation signal generator  930  is a RC-network low pass filter having a resistor Ra and a capacitor Ca. The cancellation signal generator  930  is used for generating a cancellation signal Va according to the signal Vo′ outputted from the line driver  920 . The cancellation signal Va is transmitted to an OP amplifier  950  of the cancellation module  942  via a resistor R 1 . The transmission signal Vo of the transceiver  900  is transmitted to the OP amplifier  950  via a resistor R 2 . In the cancellation module  942 , a resistor Rf with one end coupled to the input and the other end to the output of the OP amplifier  950  respectively is used for controlling the gain of the OP amplifier  950 . The OP amplifier  950  simultaneously performs low pass filtering and signal subtraction. As a result, the following formulas are obtained: 
     
       
         
           
             
               
                 
                   Va 
                   = 
                   
                     
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       
                         Ra 
                         + 
                         
                           R 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         + 
                         
                           sCaRaR 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                     
                     ⁢ 
                     
                       Vo 
                       ′ 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       Va 
                       · 
                       
                         Rf 
                         
                           R 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                     
                     + 
                     
                       Vo 
                       · 
                       
                         Rf 
                         
                           R 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                   = 
                   
                     - 
                     Vr 
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     Let Vr=0 and by combining the above-mentioned formulas (7), (8) and (9), the following formula is obtained: 
     
       
         
           
             
               
                 
                   
                     1 
                     
                       Ra 
                       + 
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         sCaRaR 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                   = 
                   
                     
                       - 
                       Re 
                     
                     
                       
                         ( 
                         
                           Re 
                           + 
                           Rk 
                           + 
                           sCeReRk 
                         
                         ) 
                       
                       ⁢ 
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     Thus, the echo can be completely cancelled when the two following formulas are satisfied:
 
CaRaR1=CeRkR2  (11)
 
     
       
         
           
             
               
                 
                   
                     Ra 
                     + 
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         
                           Rk 
                           Re 
                         
                         + 
                         1 
                       
                       ) 
                     
                     ⁢ 
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
     In practical implementations, no unit gain buffer is required to be configured between the hybrid circuit of the transceiver  900  and an OP-RC filter  944 . Similarly, the OP-RC filter  944  can easily drive a next stage, such as a sample and hold circuit, without an intermediate unit gain buffer and increases the working frequency of the sample and hold circuit. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.