Abstract:
A processing apparatus capable of reducing the size of the circuit, where in order to perform an operation “(A−B)×C”, provision is made of multiplexers  50   0  to  50   15  provided corresponding to each of all combinations of natural numbers i and j which receive as their inputs bit data A i , B i , and C j , output the bit data A i  when the C j  has the logical value “1”, and output the bit data B i when the C j  has the logical value “0”, and the bit data output from the multiplexers  50   0  to  50   15 , data obtained by shifting the complement data of 2 of the data B by exactly n bits toward the most significant bit, the data B and the carry data as the carrying from the lower significant bit are added for every bit so as to add the bit data output from the multiplexers  50   0  to  50   15  to the (i+j)th bit.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a processing apparatus and a method of the same. 2. Description of the Related Art 
     A processing apparatus which receives as its inputs positive binary data A, B, and C and performs an operation “(A−B)×C”, is known in the art. 
     Below, an explanation will be made of a processing apparatus of the related for performing the operation “(A−B)×C”. 
     FIG. 6 is a view of the configuration of the processing apparatus of the related for performing the operation “(A−B)×C”. 
     As shown in FIG. 6, the processing apparatus  1  has a subtracter  2  and a multiplier  3  and performs the operations “(A−B)×C” by using the 4-bit data A, B, and C. 
     The processing apparatus  1 , for example, performs the subtraction of the 4-bit data A and the 4-bit data B at the subtracter  2  and the multiplication of the signed 5-bit subtraction result Y and the 5-bit data C with a most significant bit (MSB) having a logical value “0” due to code expansion at the multiplier  3 . Then, the multiplication result of the multiplier  3  becomes the result of the operation “(A−B)×C”. 
     As the subtracter  2 , for example, as shown In FIG. 7. a ripple carry type adder comprised of full adders (FA)  10   0 ,  10   1 ,  10   2 , and  10   3  connected in series, is used. 
     In this subtracter  2 , “1” for finding a complement of 2 is Input to a Ci (Carry In) terminal of the full adder  10   1  performing the operation corresponding to the least significant bit (LSB). Further, the bit data A 0  to A 3  of the data A are Input to the full adders  10   0  to  10   3  and the bit data B 0  to B 3  of the data B are Input via inverters  11   0  to  11   3 . Then, bit data Y 0  to Y 3  of the 4-bit result Y are output from s terminals of the full adders  10   0  to  10   3  and bit data Y 4  indicating the sign of the subtraction result Y Is output from a CO (Carry Out) terminal of the full adder  10   3 . 
     Note that, as the full adders  10   1  to  10   3 , as shown In FIG. 8, use is made of a general full adder constituted by combining AND circuits  15   1 , and  15   2 , OR and  17   2 . At the full adders  10   1  to  10   3 , bit data input through an in 1  terminal, in 2  terminal, and Ci (Carry in ) terminal are added, the carry of the addition result Is output from the CO (Carry out) terminal, and sum data Is output from the S terminal. 
     Next, an explanation will be made of the configuration of the multiplier  3  shown In FIG.  6 . 
     FIG. 9 Is a view for explaining a complement multiplication of 2 according to the Baugh Wooly method adopted by the multiplier  3 . 
     A FIG. 10 is a view of the configuration of the multiplier  3  performing the complement multiplication of 2 shown in FIG.  9 . 
     As shown in FIG. 10, the multiplier  3  has a partial product adder circuit  20  and a final stage adder circuit  30 . 
     The partial product adder circuit  20  adopts the Wallace-tree method and has AND circuits  21   0  to  21   24 , full adders  22   1  to  22   13 , half adders  23   1  to  23   3 , and inverter circuits  24   1  to  24   11 . 
     Further, the final adder circuit  30  adopts the Ripple Carry method and has full adders  22   14  to  22   19  and half adders  23   4  and  23   5 . 
     Here, the full adders  22   14  to  22   19  have the configuration shown in FIG. 8 mentioned above. Further, as the half adders  23   1  to  23   3 , as shown in FIG. 11, provision is made of an AND circuit  15   3  and an XOR circuit  17   3 , data input through the in terminal and the in 2  terminal are added, the carry of the related addition result is output from the CO (Carry Out) terminal, and the sum data is output from the S terminal. 
     At the multiplier  3 , the AND circuits  21   1  to  21   24  of the partial product adder circuit  20  use the bit data Y 0 , Y 1 , Y 2 , Y 3 , and Y 4  of the subtraction result Y from the subtracter  2  and the bit data C 0 , C 1 , C 2 , C 3 , and 0 with an MSB having the logical value “0” due to code expansion for the partial products shown in FIG.  9 . Then, the partial products are added at the full adders  22   1  to  22   19  and the half adders  23   1  to  23   5  of the partial product adder circuit  20  and the final stage adder circuit  30  including a carry from a lower digit for every digit. By this, sum data output from the output terminal of the AND circuit  21   0  and s terminals of the half adders  23   1  and  23   4 , the full adders  22   14 ,  22   15 ,  22   16 ,  22   17 ,  22   18 , and  22   19 , and the half adder  23   5  become bit data S 0 , S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 , and S 9  of the 10-bit result S. 
     Summarizing the problem to be solved by the invention, in the processing apparatus  1  of the related art mentioned above, as shown in FIG.  7  and FIG. 10, there is a disadvantage that there are the full adders  10   0  to  10   3 , AND circuits  21   0  to  21   24 , full adders  22   1  to  22   19 , half adders  23   1  to  22   5 , and inverter circuits  24   1  to  24   11  and the size of the circuit becomes large. 
     Namely, in the processing apparatus  1 , as shown in FIG. 1, in order to perform the subtraction at the subtracter  2 , when using 4-bit data A and B, the result thereof becomes 5 bits, including the sign bit. As a result, at the multiplier  3 , it is necessary to perform the multiplication of 5 bits and the size of the circuit becomes large. 
     Further, in the processing apparatus  1  of the related art mentioned above, the critical path of the operation becomes the full adders  10   0  to  10   3 , half adder  23   4 , full adders  22   14 ,  22   15 ,  22   16 ,  22   17 ,  22   18 , and  22   19 , and the half adder  23   5 , so there is a disadvantage that the processing time becomes long. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a processing apparatus capable of reducing the size of the circuit performing the operation “(A−B)×C”. 
     Another object of the present invention is to provide a processing apparatus capable of shortening the processing time of the operation “(A−B)×C”. 
     According to a first aspect of the present invention, there is provided a processing apparatus for calculating “(A−B)×C” where the bit data A is constituted by the n-bit data of A i  (i=0, 1, . . . n−1), the bit data B is constituted by the n-bit data of B i  (i=0, 1, . . . n−1), and the bit data C is constituted by the n-bit data of C j  (j=0, 1, . . . n−1), said processing apparatus comprising: a bit data selecting means for receiving as input the bit data A i , B i , and C j , and outputting the bit data A i  when C j  equals to a first logical value or the bit data B i  when data C j  equals to a second logical value in response to data C j  with respect to all combinations of the natural numbers i and J and an adding means for adding the bit data output from the bit data selecting means to the (i+j)th bit for each bit of all combinations of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B. 
     The processing apparatus of the present invention performs the operation “(A−B)×C” based on the following equation (1):              S   =       (       ∑     j   =   0       j   =     n   -   1                ∑     i   =   0       i   =     n   -   1              ·     (         A   j     ·     C   j       |       B   i     ·       C   _     j         )           )     -       2   n     ×   B     +   B             (   1   )                                
     That is, in the processing apparatus of the present invention, each of the plurality of bit data selecting means outputs the bit data A i  when the input C j  is the logical value “1” and outputs the bit data B i  when C j  is the logical value “0” among the input bit data A i  and B i . 
     Next, the adding means adds the bit data output from the bit data selecting means to the (i+j)th bit by adding for each bit the bit data output from the bit data selecting means, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, the data B, and the carry data carried from a lower bit. 
     Preferably, it further provides with an inverted value generating means for inverting the bit data B 0 , B 1 , . . . , B i , . . . , B n−2 , and B n−1  to find the bit data B 0   − , B 1   − , . . . , B i   − , . . . , B n−2   − , and B n−1   − ; the adding means respectively adds the bit data B 1   − , . . . , B i   − , . . . , B n−1   − , found by the inverted value generating means to the (n+1)th, . . . , (n+i)th, . . . , (2n−1)th bits and adds the bit data B 0   −  and the logical value “1” to the n-th bit. 
     Preferably, the adding means adds the bit data B 0 , B 1 , . . . , B i , . . . , B n−2 , and B n−1  of the data B to the 0th, 1st, . . . , i-th, . . . , (n−2)th, and (n−1)th bits. 
     Preferably, the adding means outputs as the result of the addition (2n+1)bit data comprised of the bit data S 0 , S 1 , . . . , S 2n−1  and S 2n  and the bit data S 2n  shows the sign value. 
     Preferably, the bit data selecting means each has a first transmission gate which becomes conductive when the input bit data C i  is the logical value “1” and a second transmission gate which becomes conductive when the input bit data C i  is the logical value “0”. 
     According to a second aspect of the present invention, there is provided a processing method for calculating “(A−B)×C” where the bit data A is constituted by the n-bit data of A i  (i=0, 1, . . . n−1), the bit data B is constituted by the n-bit data of B i  (i=0, 1, . . . n−1), and the bit data C is constituted by the n-bit data of C j  (j=0, 1, . . . n−1), said processing method comprising the steps of: performing processing for receiving as input the bit data A i , B i , and C j , selecting the bit data A i  when data C j  equals to a first logical value or B i  when data C j  equals to a second logical value in response to the bit data C j  with respect to all combinations of the natural numbers i and j and adding the selected bit data to the (i+j)th bit for each bit of all combination of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects and features of the present invention will become more apparent from the following description of the preferred embodiments given with reference to the attached drawings, wherein: 
     FIG. 1 is a view of the configuration of a processing apparatus according to the present embodiment; 
     FIG. 2 is a view of the configuration of a multiplexer shown in FIG. 1; 
     FIG. 3 is a view for explaining a processing method adopted by the processing apparatus shown in FIG. 1; 
     FIG. 4 is a flow chart for explaining the operation of the processing apparatus shown in FIG. 1; 
     FIG. 5 is a view for explaining a concrete operation in the processing apparatus shown in FIG. 1; 
     FIG. 6 is a view of the configuration of the processing apparatus of the related art performing an operation “(A−B)×C”; 
     FIG. 7 is a view of the configuration of a subtracter shown in FIG. 6; 
     FIG. 8 is a view of the configuration of a full adder (FA) shown in FIG. 7; 
     FIG. 9 is a view for explaining a complement multiplication of 2 by the Baugh Wooly method adopted by the multiplier shown in FIG. 2; 
     FIG. 10 is a view of the configuration of the multiplier for performing the complement multiplication of 2 shown in FIG. 9; and 
     FIG. 11 is a view of the configuration of the half adder shown in FIG.  10 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Below, an explanation will be made of a processing apparatus according to an embodiment of the present invention and a method of the same. 
     FIG. 1 is a view of the configuration of a processing apparatus  40  for performing an operation “S=(A−B)×C” using the 4-bit data A, B, and C. 
     As shown in FIG. 1, the processing apparatus  40  has a partial product adder circuit  41  and a final stage adder circuit  42 . 
     The partial product adder circuit  41  has multiplexers  50   0  to  50   15  as the bit data selecting means of the present invention, full adders (FA)  52   1  to  52   10 , half adders (HA)  53   1  to  53   3 , inverter circuits  54   1  to  54   4 , input units  55  and  56 , and an output unit  57 . 
     The final stage adder circuit  42  has full adders  52   11 , to  52   16  and a half adder  53   4 . 
     The input unit  55  has A 0 , A 1 , A 2 , A 3 , B 0 , B 1 , B 2 , and B 3  terminals for receiving as their inputs bit data A 0 , A 1 , A 2 , A 3 , B 0 , B 1 , B 2 , and B 3 . 
     Here, the 4-bit data A is comprised by bit data A 0 , A 1 , A 2 , and A 3 , while the 4-bit data B is comprised by bit data B 0 , B 1 , B 2 , and B 3 . 
     The input unit  56  has C 0 , C 1 , C 2 , and C 3  terminals for receiving as input bit data C 0 , C 1 , C 2 , and C 3 . 
     Here, the 4-bit data C is comprised by the bit data C 0 , C 1 , C 2 , and C 3 . 
     The output unit  57  has S 0 , S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8  terminals for outputting bit data S 0 , S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 . 
     Here, the 9-bit data S is comprised by the bit data S 0 , S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 . 
     The multiplexers  50   0  to  50   15  find partial products P 0,0 , P 1,0 , P 0,1 , P 2,0 , P 1,1 , P 0,2 , P 3,0 , P 2,1 , P 1,2 , P 0,3 , P 3,1 , P 2,2 , P 1,3 , P 3,2 , P 2,3 , and P 3,3  defined by the following equation (2): 
     
       
         P ij =A i ·Cj|B i ·{overscore (C)} j (i=0˜3j=0˜3)  ( 2 ) 
       
     
     FIG. 2 is a view of the configuration of multiplexers  50   0  to  50   15 . 
     As shown in FIG. 2, the multiplexers  50   0  to  50   15  have inverters  70   1  to  70   4 , transmission gates  70   1  and  70   2 , an s terminal, an a terminal, a b terminal, and an o terminal. 
     At the multiplexers  50   0  to  50   15 , when the s terminal has a logical value “1”, the transmission gate  70   1  is turned off, the transmission gate  70   2  is turned on, and the level of the a terminal is output as the level of the o terminal. On the other hand, at the multiplexers  50   0  to  50   15 , when the s terminal has a logical value “0”, the transmission gate  70   1  is turned on, the transmission gate  70   2  is turned off, and the level of the b terminal is output as the level of the o terminal. 
     Namely, at the multiplexers  50   0  to  50   15 , a bit data A i  input to the a terminal is output from the o terminal when a bit data C j  has the logical value “1”, and a bit data B i  input to the a terminal is output from the o terminal when the bit data C j  has the logical value “0”. 
     Partial products P 0,0 , P 1,0 , P 0,1 , P 2,0 , P 1,1 , P 0,2 , P 3,0 , P 2,1 , P 1,2 , P 0,3 , P 3,1 , P 2,2 , P 1,3 , P 3,2 , P 2,3 , and P 3,3  calculated at the multiplexers  50   0  to  50   15  are added containing carries from the lower significant bits for every bit at full adders  52   1  to  52   16  and the half adders  53   1  to  53   4  so that they are added to an (i+j)th bit. By this, the operation “A×C+B×C − j” shown in the following equation (3) is performed.                  A   ×   C     +     B   ×     C   _         =       ∑     j   =   0       j   -   3              ∑     i   +   0       i   -   3              2     i   +   j       ·     P   ij                   (   3   )                                
     Here, as the full adders  52   1  to  52   16 , use is made of ones having the configuration shown in FIG. 8 mentioned before. Further, as the half adders  53   1  to  53   4 , use is made of ones having the structure shown in FIG. 11 mentioned before. 
     The inverter circuits  54   1 ,  51   2 , and  51   3  to  51   4  receive as their inputs the bit data B 0 , B 1 , B 2 , and B 3  and output the inverted bit data B 0   − , B 1   − , B 2   − , and B 3   − . 
     The operations at the inverter circuits  54   1  to  54   4  correspond to inversion operations for performing the operation “−2 4 ×B”. Further, by the addition carried out by inputting “1” to the Ci (Carry in) terminal of the full adder  52   6 , the “addition of 1” for performing the operation “−2 4 ×B” is carried out. 
     Further, bit data B 0  to B 3  are output to the in 2  terminals of the half adder  53   1 , full adder  52   1 , half adder  53   2 , and the full adder  52   4 . At the half adder  53   1 , full adder  52   1 , half adder  53   2 , and the full adder  52   4 , the operation of “+B j ” is carried out. 
     As mentioned above, by the full adders  52   1  to  52   16  and the half adders  53   1  to  53   4 , the operation of the following equation (4) is performed by adding the result of “A×C+B×C − ”, “−2 4 ×B”, and “B”.              S   =       (       ∑     j   =   0       j   =   3              ∑     i   =   0       i   =   3              2     i   +   j       ·     P   ij           )     -       2   4     ×   B     +   B             (   4   )                                
     Note that the operation of the above equation (3) is represented as shown in FIG.  3 . 
     Note that, in FIG. 3, the figures in parentheses indicate the reference numerals of the constituent elements of the processing apparatus  40  shown in FIG.  1  and indicate that the operation indicated adjoining this is found by the related constituent element or the data indicated adjoining this is input to the related constituent element. 
     Here, the above equation (4) is equivalent to the operation “S=(A−B)×C”. 
     Below, the fact that above equation (4) is equivalent to the operation “S=(A−B)×C” will be proved. 
     The operation “S=(A−B)×C” can be modified as in the following equation (5):                    S   =       (     A   -   B     )     ×   C                 =       A   ×   C     -     B   ×   C                   =       A   ×   C     +     B   ×     (     -   C     )                       (   5   )                                
     A complement x −  of 1 of a binary x is indicated by the following equation (6): 
     
       
         {overscore (x)}=1·x  (7) 
       
     
     Accordingly, when the above equation (6) is applied to “−C” of the above equation 5), the following equation (7) stands:                -   C     =       C   _            ∑     i   =   0       i   =   3            2   i                 (   7   )                                
     Further, when the above equation (5) is rewritten by using the above equation (7) and further modification is made, the result becomes the following equation (8):                    S   =       A   ×   C     +     B   ×     (       C   _     -       ∑     i   =   0       i   =   3            2   i         )                     =       A   ×   C     +     B   ×     C   _       -     Bx          ∑     i   =   0       i   =   3            2   i                       =       A   ×   C     +     B   ×     C   _          x        (       2   4     -   1     )                       =       A   ×   C     +     B   ×     C   _          x2   4     ×   B     +   B                   (   8   )                                
     Here, it is seen from above equation (8) and equation (3) that the operation “S=(A−B)×C” is equivalent to above equation (5). 
     Below, an explanation will be made of a connection configuration of the constituent elements of the processing apparatus  40  shown in FIG.  1 . 
     The a terminals of the multiplexers  50   1 ,  50   2 ,  50   5 , and  50   9  are connected to the A 0  terminal of the input unit  55 , and the b terminals thereof are connected to the B 0  terminal of the input unit  55 . 
     The a terminals of the multiplexers  50   1 ,  50   4 ,  50   8 , and  50   12  are connected to the A 1  terminal of the input unit  55 , and the b terminals thereof are connected to the B 1  terminal of the input unit  55 . 
     The a terminals of the multiplexers  50   3 ,  50   7 ,  50   11 , and  50   14  are connected to the A 2  terminal of the input unit  55 , and the b terminals thereof are connected to the B 2  terminal of the input unit  55 . 
     The a terminals of the multiplexers  50   6 ,  50   10 ,  50   13 , and  50   15  are connected to the A 3  terminal of the input  1 unit  55 , and the b terminals thereof are connected to the B 3  terminal of the input unit  55 . 
     The s terminals of the multiplexers  50   0 ,  50   1 ,  50   3 , and  50   6  are connected to the C 0  terminal of the input unit  56 . 
     The s terminals of the multiplexers  50   2 ,  50   4 ,  50   7 , and  50   10  are connected to the C 1  terminal of the input unit  56 . 
     The s terminals of the multiplexers  50   5 ,  50   8 ,  50   11 , and  50   13  are connected to the C 2  terminal of the input unit  56 . 
     The s terminals of the multiplexers  50   9 ,  50   12 ,  50   14 , and  50   15  are connected to the C 3  terminal of the input unit  56 . 
     The in terminal of the half adder  53   1  is connected to the o terminal of the multiplexer  50   0 , and the in 2  terminal thereof is connected to the B 0  terminal of the input unit  55 . 
     Further, the s terminal of the half adder  53   1  is connected to the S 0  of the output unit  57 , and the CO terminal thereof is connected to the in 2  terminal of the half adder  53   4 . 
     The in 1  of the full adder  52   1  is connected to the o terminal of the multiplexer  50   2 , the in 2  terminal thereof is connected to the o terminal of the multiplexer  50   1 , and the Ci terminal thereof is connected to the B 1  of the input unit  55 . 
     Further, the s terminal of the full adder  52   1  is connected to the in 1  terminal of the half adder  53   4 , and the CO terminal thereof is connected to the in 2  terminal of the full adder  52   11 . 
     The in 1  terminal of the half adder  53   2  is connected to the o terminal of the multiplexer  50   3 , and the in 2  terminal thereof is connected to the B 2  terminal of the input unit  55 . 
     Further, the s terminal of the half adder  53   2  is connected to the Ci terminal of the full adder  52   2 , and the C 0  terminal thereof is connected to the Ci terminal of the full adder  52   4 . 
     The in 1  terminal of the half adder  53   3  is connected to the o terminal of the multiplexer  50   9 , and the in 2  terminal thereof is connected to the o terminal of the multiplexer  50   8 . 
     Further, the s terminal of the half adder  53   3  is connected to the in 1  terminal of the full adder  52   3 , and the CO terminal thereof is connected to the in 2  terminal of the full adder  52   7 . 
     The full adder  52   5  is connected at its in 1  terminal to the o terminal of the multiplexer  50   12 , connected at its in 2  terminal to the o terminal of the multiplexer  50   11  and connected at its Ci terminal to the o terminal of the multiplexer  50   10 . 
     Further, the full adder  52   5  is connected at its s terminal to the in 1  terminal of the full adder  52   6  and connected at its CO terminal to the in 2  terminal of the full adder  52   9 . 
     The full adder  52   8  is connected at its in 1  terminal to the o terminal of the multiplexer  50   14 , connected at its in 2  terminal to the o terminal of the multiplexer  50   13 , and connected at its Ci terminal to the output terminal of the inverter  54   2 . 
     Further, the full adder  52   8  is connected at its s terminal to the in 1  terminal of the full adder  52   9  and connected at its CO terminal to the Ci terminal of the full adder  52   10 . 
     The full adder  52   2  is connected at its in 1  terminal to the o terminal of the multiplexer  50   5  and connected at its in 2  terminal to the multiplexer  50   4 . 
     Further, the full adder  52   2  is connected at its s terminal to the in 1  terminal of the full adder  52   11  and connected at its CO terminal to the in 2  terminal of the full adder  52   12 . 
     The full adder  52   3  is connected at its in 2  terminal to the o terminal of the multiplexer  50   7  and connected at its Ci terminal to the o terminal of the multiplexer  50   6 . 
     Further, the full adder  53   3 is connected at its s terminal to the in 1  terminal of the full adder  52   4  and connected at its CO terminal to the Ci terminal of the full adder  52   7 . 
     The in 2  terminal of the full adder  52   6  is connected the output terminal of the inverter  54   1 , and the logical value “1” is input to the Ci terminal thereof. 
     Further, the full adder  52   6  is connected at its s terminal to the in 1  terminal of the full adder  52   7  and connected at its CO terminal to the Ci terminal of the full adder  52   9 . 
     The full adder  52   1  is connected at its in 2  terminal to the output terminal of the inverter  54   3 . 
     Further, the full adder  52   10  is connected at its s terminal to the in 1  terminal of the full adder  52   15  and connected at its CO terminal to the in 2  terminal of the full adder  52   16 . 
     The full adder  52   4  is connected at its in 2  terminal to the B 3  terminal of the input unit  55 . 
     Further, the full adder  52   2  is connected at its s terminal to the in 1  terminal of the full adder  52   12  and connected at its CO terminal to the in 2  terminal of the full adder  52   13 . 
     The full adder  52   7  is connected at its s terminal to the in 1  terminal of the full adder  52   13  and connected at its CO terminal to the in 2  terminal of the full adder  52   14 . The full adder  52   9  is connected at its s terminal to the in 1  terminal of the full adder  52   14  and connected at its CO terminal to the in 2  terminal of the full adder  52   15 . 
     The half adder  53   4  is connected at its s terminal to the S 1  terminal of the output unit  57  and connected at its CO terminal to the Ci terminal of the full adder  52   11 . 
     The full adder  52   11  is connected at its s terminal to the S 2  terminal of the output unit  57  and connected at its CO terminal to the Ci terminal of the full adder  52   12 . 
     The full adder  52   12  is connected at its s terminal to the S 3  terminal of the output unit  57  and connected at its CO terminal to the Ci terminal of the full adder  52   13 . 
     The full adder  52   13  is connected at its s terminal to the S 4  terminal of the output unit  57  and connected at its CO terminal to the Ci terminal of the full adder  52   14 . 
     The full adder  52   14  is connected at its s terminal to the S 5  terminal of the output unit  57  and connected at its CO terminal to the Ci terminal of the full adder  52   15 . 
     The full adder  52   15  is connected at its s terminal to the S 6  terminal of the output unit  57  and connected at its CO terminal to the Ci terminal of the full adder  52   16 . 
     The full adder  52   16  is connected at its in 1  terminal to the output terminal of the inverter  54   4 , connected at its s terminal to the S 7  terminal of the output unit  57 , and connected at its CO terminal to the S 8  terminal of the output unit  57  via the inverter  54   5 . 
     Below, an explanation will be made of the operation of the processing apparatus  40  shown in FIG.  1 . 
     FIG. 4 is a flow chart for explaining the processing method in the processing apparatus  40 . 
     [Step S1] 
     Bit data A 0 , B 0 , A 1 , B 1 , A 2 , B 2 , A 3 , and B 3  are input to the A 0 , B 0 , A 1 , B 1 , A 2 , B 2 , A 3 , and B 3  terminals of the input unit  55 . Further, the bit data C 0 , C 1, C   2 , and C 3  are input to the C 0 , C 1 , C 2 , and C 3  terminals of the input unit  56 . 
     Then the selections of the bit data A 0  to A 3  and B 0  to B 3  at the multiplexers  50   0  to  50   15  shown below are simultaneously carried out, and the selected bit data are output to corresponding half adders and full adders. 
     Specifically, at the multiplexer  50   0 , when the bit data C 0  has the logical value “1”, the bit data A 0  is output from the o terminal to the in 1  terminal of the half adder  53   1 , while when the bit data C 0  has the logical value “0 ”, the bit data B 0  is output from the o terminal to the in 1  terminal of the half adder  53   1 . 
     At the multiplexer  50   1 , when the bit data C 0  has the logical value “1”, the bit data A 1  is output from the o terminal to the in 2  terminal of the full adder  52   1 , while when the bit data C 0  has the logical value “0”, the bit data B 1  is output from the o terminal to the in 2  terminal of the full adder  52   1 . 
     At the multiplexer  50   3 , when the bit data C 0  has the logical value “1”, the bit data A 2  is output from the o terminal to the in 1  terminal of the half adder  53   2 , while when the bit data C 0  has the logical value “0”, the bit data B 2  is output from the o terminal to the in 1  terminal of the half adder  53   2 . 
     At the multiplexer  50   6 , when the bit data C 0  has the logical value “1”, the bit data A 3  is output from the o terminal to the Ci terminal of the full adder  52   3 , while when the bit data C 0  has the logical value “0”, the bit data B 3  is output from the o terminal to the Ci terminal of the full adder  52   3 . 
     At the multiplexer  50   2 , when the bit data C 1  has the logical value “1”, the bit data A 0  is output from the o terminal to the in 1  terminal of the full adder  52   1 , while when the bit data C 1  has the logical value “0”, the bit data B 0  is output from the o terminal to the in 1  terminal of the full adder  52   1 . 
     At the multiplexer  50   4 , when the bit data C 1  has the logical value “1”, the bit data A 1  is output from the o terminal to the in 2  terminal of the full adder  52   2 , while when the bit data C 1  has the logical value “0”, the bit data B 1  is output from the o terminal to the in 2  terminal of the full adder  52   2 . 
     At the multiplexer  50   7 , when the bit data C 1  has the logical value “1”, the bit data A 2  is output from the o terminal to the in 2  terminal of the full adder  52   3 , while when the bit data C 1  has the logical value “0”, the bit data B 2  is output from the o terminal to the in 2  terminal of the full adder  52   3 . 
     At the multiplexer  50   10 , when the bit data C 1  has the logical value “1”, the bit data A 3  is output from the o terminal to the Ci terminal of the full adder  52   5 , while when the bit data C 1  has the logical value “0”, the bit data B 3  is output from the o terminal to the Ci terminal of the full adder  52   5 . 
     At the multiplexer  50   5 , when the bit data C 2  has the logical value “1”, the bit data A 0  is output from the o terminal to the in 1  terminal of the full adder  52   2 , while when the bit data C 2  has the logical value “0”, the bit data B 0  is output from the o terminal to the in 1  terminal of the full adder  52   2 . 
     At the multiplexer  50   8 , when the bit data C 2  has the logical value “1”, the bit data A 1  is output from the o terminal to the in 2  terminal of the half adder  53   3 , while when the bit data C 2  has the logical value “0”, the bit data B 1  is output from the o terminal to the in 2  terminal of the half adder  53   3 . 
     At the multiplexer  50   11 , when the bit data C 2  has the logical value “1”, the bit data A 2  is output from the o terminal to the in 2  terminal of the full adder  52   5 , while when the bit data C 2  has the logical value “0”, the bit data B 2  is output from the o terminal to the in 2  terminal of the full adder  52   2 . 
     At the multiplexer  50   13 , when the bit data C 2  has the logical value “1”, the bit data A 3  is output from the o terminal to the in 2  terminal of the full adder  52   8 , while when the bit data C 2  has the logical value “0”, the bit data B 3  is output from the o terminal to the in 2  terminal of the full adder  52   8 . 
     At the multiplexer  50   9 , when the bit data C 3  has the logical value “1”, the bit data A 0  is output from the o terminal to the in 2  terminal of the half adder  53   3 , while when the bit data C 3  has the logical value “0”, the bit data B 0  is output from the o terminal to the in 2  terminal of the half adder  53   3 . 
     At the multiplexer  50   12 , when the bit data C 3  has the logical value “1”, the bit data A 1  is output from the o terminal to the in 1  terminal of the full adder  52   5 , while when the bit data C 3  has the logical value “0”, the bit data B 1  is output from the o terminal to the in 1  terminal of the full adder  52   5 . 
     At the multiplexer  50   14 , when the bit data C 3  has the logical value “1”, the bit data A 2  is output from the o terminal to the in 1  terminal of the full adder  52   8 , while when the bit data C 3  has the logical value “0”, the bit data B 2  is output from the o terminal to the in 1  terminal of the full adder  52   8 . 
     At the multiplexer  50   15 , when the bit data C 3  has the logical value “1”, the bit data A 3  is output from the o terminal to the in 1  terminal of the full adder  52   1  while when the bit data C 3  has the logical value “0”, the bit data B 3  is output from the o terminal to the in 1  terminal of the full adder  52   10 . 
     Further, the bit data B 0  from the B 0  terminal of the input unit  55  is output to the in 2  terminal of the half adder  53   1 . 
     The bit data B 1  from the B 1  terminal of the input unit  55  is output to the Ci terminal of the full adder  52   1 . 
     The bit data B 2  from the B 2  terminal of the input unit  55  is output to the in 2  terminal of the half adder  53   2 . 
     The bit data B 3  from the B 3  terminal of the input unit  55  is output to the in 2  terminal of the full adder  52   4 . 
     Further, the bit data B 0  from the B 0  terminal of the input unit  55  is inverted at the inverter circuit  54   1 , and then output to the in 2  terminal of the full adder  52   6 . 
     The bit data B 1  from the B 1  terminal of the input unit  55  is inverted at the inverter circuit  54   2 , and then output to the Ci terminal of the full adder  52   8 . 
     The bit data B 2  from the B 2  terminal of the input unit  55  is inverted at the inverter circuit  54   3 , and then output to the in 2  terminal of the full adder  52   10 . 
     The bit data B 3  from the B 3  terminal of the input unit  55  is inverted at the inverter circuit  54   4 , and then output to the in 1  terminal of the full adder  52   16  of the final stage adder circuit  42   
     [Step S2] 
     At the half adder  53   1 , the addition of the bit data B 0  and the bit data from the multiplexer  50   0  is carried out, the sum data of the related addition results is output from the s terminal to the S 0  terminal, and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the half adder  53   4  of the final stage adder circuit  42 . 
     In the full adder  52   1 , the addition of the bit data B 1 , the bit data from the multiplexer  50   1  and the bit data from the multiplexer  50   2  is carried out, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the half adder  53   5  of the final stage adder circuit  42 , and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the full adder  52   11  of the final stage adder circuit  42 . 
     At the half adder  53   2 , the addition of the bit data B 2  and the bit data from the multiplexer  50   3  is carried out, the sum data of the related addition results is output from the s terminal to the Ci terminal of the full adder  52   2 , and the carry data of the related addition result is output from the Co terminal to the Ci terminal of the full adder  52   4 . 
     At the half adder  53   3 , the addition of the bit data from the multiplexer  50   8  and the bit data from the multiplexer  50   9  is carried out, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   3 , and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the full adder  52   7 . 
     At the full adder  52   5 , the addition of the bit data from the multiplexer  50   10 , the bit data from the multiplexer  50   11 , and the bit data from the multiplexer  50   12  is carried out, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   6 , and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the full adder  52   9 . 
     At the full adder  52   8 , the bit data B 1   −  from the inverter circuit  54   2 , the bit data from the multiplexer  50   13 , and the bit data from the multiplexer  50   14  are added, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   9 , and the carry data of the related addition result is output from the Co terminal to the Ci terminal of the full adder  52   10 . 
     Further, at the full adder  52   2 , the sum data from the half adder  53   2 , the bit data from the multiplexer  50   4 , and the bit data from the multiplexer  50   5  are added, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   11  of the final stage adder circuit  42 , and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the full adder  52   12  of the final stage adder circuit  42 . 
     At the full adder  52   3 , the bit data from the multiplexer  50   6 , the bit data from the multiplexer  50   7 , and the sum data from the half adder  53   3  are added, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   4 , and the carry data of the related addition result is output from the Co terminal to the Ci terminal of the full adder  52   7 . 
     At the full adder  52   6 , the addition of the logical value “1” input to the Ci terminal, the bit data B 1   −  from the inverter  54   1 , and the sum data from the s terminal of the full adder  52   5  is carried out, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   7 , and the carry data of the related addition result is output from the Co terminal to the Ci terminal of the full adder  52   9 . 
     At the full adder  52   10 , the carry data from the full adder  52   8 , the bit data B 2   −  from the inverter circuit  54   3 , and the bit data from the multiplexer  50   15  are added, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   15  of the final stage adder circuit  42 , and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the full adder  52   16 . 
     Further, at the full adder  52   4 , the addition of the carry data from the half adder  53   2 , the bit data B 3 , and the sum data from the full adder  53   3  is carried out, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   12  of the final stage adder circuit  42 , and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the full adder  52   13 . 
     At the full adder  52   7 , the carry data from the full adder  52   3 , the carry data from the half adder  53   3 , and the sum data from the full adder  52   6  are added, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   13  of the final stage adder circuit  42 , and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the full adder  52   14  of the final stage adder circuit  42 . 
     At the full adder  52   9 , the carry data from the full adder  52   6 , the carry data from the full adder  52   5 , and the sum data from the full adder  52   8  are added, the sum data of the related addition results is output from the s terminal to the in 1  terminal of the full adder  52   14  of the final stage adder circuit  42 , and the carry data of the related addition result is output from the Co terminal to the in 2  terminal of the full adder  52   15  of the final stage adder circuit  42 . 
     [Step S3] 
     At the final stage adder circuit  42 , the following processing is carried out. 
     First, at the half adder  53   4 , the addition of the carry data from the half adder  53   1  and the sum data from the full adder  52   1  is carried out, the sum data thereof is output from the S 1  terminal of the output unit  57  as the bit data S 1 , and the carry data thereof is output to the Ci terminal of the full adder  52   11 . 
     Next, at the full adder  52   11 , the carry data from the half adder  53   4 , the carry data from the full adder  52   1 , and the sum data from the full adder  52   2  are added, the sum data thereof is output from the S 2  terminal of the output unit  57  as the bit data S 2 , and the carry data thereof is output to the Ci terminal of the full adder  52   12 . 
     Next, at the full adder  52   12 , the carry data from the full adder  52   11 , the carry data from the full adder  52   2 , and the sum data from the full adder  52   4  are added, the sum data thereof is output from the S 3  terminal of the output unit  57  as the bit data S 3 , and the carry data thereof is output to the Ci terminal of the full adder  52   13 . 
     Next, at the full adder  52   13 , the carry data from the full adder  52   12 , the carry data from the full adder  52   4 , and the sum data from the full adder  52   7  are added, the sum data thereof is output from the S 4  terminal of the output unit  57  as the bit data S 4 , and the carry data thereof is output to the Ci terminal of the full adder  52   14 . 
     Next, at the full adder  52   14 , the carry data from the full adder  52   13 , the carry data from the full adder  52   7 , and the sum data from the full adder  52   9  are added, the sum data thereof is output from the S 5  terminal of the output unit  57  as the bit data S 5 , and the carry data thereof is output to the Ci terminal of the full adder  52   15 . 
     Next, at the full adder  52   15 , the carry data from the full adder  52   14 , the carry data from the full adder  52   9 , and the sum data from the full adder  52   0  are added, the sum data thereof is output from the S 6  terminal of the output unit  57  as the bit data S 6 , and the carry data thereof is output to the Ci terminal of the full adder  52   16 . 
     Next, at the full adder  52   16 , the carry data from the full adder  52   15 , the carry data from the full adder  52   10 , and the bit data B 3   −  from the inverter  54   4  are added, the sum data thereof is output from the S 7  of the output unit  57  as the bit data S 7 , and the carry data thereof is output via the inverter  54   5  from the S 8  terminal of the output unit  57  as the bit data S 8 . 
     Here, the bit data S 8  indicates the sign. When the bit data S 8  has the logical value “1”, it indicates that the data S of the result of the operation “(A−B)×C” is negative, while when the bit data S 8  has the logical value “0”, it indicates that the data S is positive. 
     Note that, when the bit data S 8  has the logical value “1”, the bit data S 0  to S 7  indicate the complement value of 2 of the result of the operation “(A−B)×C”. 
     In the processing apparatus  40  shown in FIG. 1, for example, as shown in FIG. 5, where data A (A 0 , A 1 , A 2 , A 3 )=(0, 0, 0, 1), B (B 0 , B 1 , B 2 , B 3 )=(0, 0, 1, 0) and C (C 0 , C 1 , C 2 , C 3 )=(1, 1, 1, 1) are input, data S (S 0 , S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 )=(0, 1, 0, 1, 1, 0, 1, 0, 0) is output. 
     As explained above, according, to the processing apparatus  40 , as shown in FIG. 1, the operation “(A−B)×C” can be carried out by the multiplexers  50   0  to  50   15 , full adders (FA)  52   1  to  52   16  half adder (HA)  53   1  to  53   4 , inverter circuits  54   1  to  54   4 , input units  55  and  56 , and the output unit  57 . It is not necessary to use the multiplier of 5 bits as in the processing apparatus  1  of the related art shown in FIG. 6, FIG. 7, and FIG. 10 mentioned above, thus the circuit size can be greatly reduced. 
     Further, according to the processing apparatus  40 , the critical path of the operation becomes the multiplexer  50   0 , half adders  53   1  and  53   4 , full adders  52   11 ,  52   12 ,  52   13 ,  52   14 ,  52   15 , and  52   16 , and the inverter circuit  54   5 , so the critical path can be shortened compared with the processing apparatus  1  of the related art mentioned above, and thus the operation time can be shortened. 
     The embodiment of the present invention is not limited to that mentioned above. 
     For example, in FIG. 1, a case where the operation “(A−B)×C” was carried out by using 4-bit data A, B, and C was exemplified, but the present invention can be applied also to a case where the operation “(A−B)×C” is carried out by using n-bit data A, B, and C for all integers n of 2 or more. 
     In this case, the operation is carried out based on the following equation (9).              S   =       (       ∑     j   =   0       j   =     n   -   1                ∑     i   =   0       i   =     n   -   1                2     i   +   j       ·     P   ij           )     -       2   n     ×   B     +   B             (   9   )                                
     In the above equation (9), the operation of the first term is carried out by the addition for every bit containing the carry data from the lower significant bit so as to select the bit data A i  when the bit data C j  has the logical value “1” by using the multiplexer as the bit data selecting means of the present invention, select the bit data B i  when the bit data C j  has the logical value “0”, and add the selected data to the (i+j)th bit. 
     Further, in the above equation (9), the operation of “−2 n ×B” is carried out by finding the complement of 2 of the data B by inverting the level of the data B, adding “1” to the LSB of this level-inverted data, and shifting the addition result by exactly n bits toward the MSB. The shift is realized by inputting for example bit data B 0  to B n−1  as the addition result to the adder for performing the addition corresponding to (n to 2n−1)th bits of the result. 
     Then, by adding the result of the first term of the above equation (9), the result of “−2 n ×B”, and the data B, the operation of the above equation (9) is carried out. 
     Summarizing the effect of the invention, as explained above, according to the processing apparatus of the present invention and the method of same, the time of the operation “(A−B)×C” can be shortened. 
     Further, according to the processing apparatus of the present invention, the size of the device for performing the operation “(A−B)×C” can be reduced. 
     While the invention has been described by reference to specific embodiments chosen for purposes of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention.