Abstract:
A CMOS input buffer supporting multiple I/O standards and having a pair of NMOS and PMOS differential receivers, each having a first input connected to an input pad and a second input connected to a reference voltage, a first multiplexer connected to the control terminal of the current sink of the NMOS differential receiver and having one input connected to the positive supply terminal, and a second multiplexer connected to the control terminal of the current source of the PMOS differential receiver and having one input connected to the negative supply terminal or ground. The buffer further includes an inverter connected to a combined output of the PMOS and NMOS differential receivers and having an output connected to the second input of the first and second multiplexer, and a configuration storage bit for selecting the desired inputs of the first and second multiplexer, thereby supporting high speed standards as well as general purpose standards while reducing static power dissipation.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     This invention relates to an input buffer architecture. More particularly, it relates to a CMOS input buffer and a method for supporting multiple I/O standards.  
         [0003]     2. Description of the Related Art  
         [0004]     Field Programmable Gate Arrays (FPGA) are frequently used for various applications and are therefore, interfaced with various devices operating at varied interfacing standards (e.g., LVTTL, LVCMOS, LVCMOS2, LVCMOS1.8, 1.5, 1.2, HSTL, SSTL, GTL, GTL+ etc.). Due to the vast and diverse field of applications of FPGAs, it becomes desirable to have their input circuits capable of receiving signals of different voltage swings in conformance with interfacing standards and convert them into core-acceptable voltage swings.  
         [0005]     Existing input circuits for FPGAs use multiple input buffers, each designed to support one or more compatible interface standards. Output of a desired input buffer is selected from a multiplexer and connected to the core. Such an input circuit shown in  FIG. 1  includes an input circuit  199 , which includes three input receivers  150 ,  140 ,  141  and a multiplexer  160 . Input receiver  150  is a Schmitt trigger having its input connected to an input pad  180  and having an output  190  connected to one of the inputs of multiplexer  160 . The input receiver  150  is structured to accept input voltage swings in general purpose interface environments like LVTTL, LVCMOS, LVCMOS2, LVCMOS1.8, LVCMOS1.5, and LVCMOS1.2.  
         [0006]     Input receivers  140  and  141  are NMOS type and PMOS type differential input receivers, respectively, each having one of their input coming from the input pad  180  and the other input connected to the reference voltage VREF. Their outputs  191  and  192  are also connected to one of the inputs of the multiplexer  160 . The input receiver  140  is compatible with input interface standards requiring higher reference voltages, like SSTL3 and SSTL2. The other input receiver  141  is compatible with input interface standards requiring lower reference voltages, like HSTL, GTL and GTLP.  
         [0007]     FIGS.  2 ( a ),  3  and  4  show the internal circuitry of the input receivers  150 ,  140  and  141  respectively. For ease of understanding, enable circuitry from each of the receivers is removed. Detailed explanation of the prior art can be found in U.S. Pat. No. 5,958,026 titled “Input/Output Buffer Supporting Multiple I/O Standards”.  
         [0008]     In the method employed in the existing input circuitry for FPGAs as shown in  FIGS. 1-4 , the first difficulty is with designing the Schmitt trigger. It is very difficult to design a Schmitt trigger that supports number of general purpose standards. This is because supporting a number of general purpose standards requires that maximum input voltage for logic low (V ilmax ) and minimum input voltage for logic high (V ihmin) ) of the Schmitt trigger be kept such that they satisfy V ilmax  and V ihmin  specifications of all the desired standards. In effect of this, maximum and minimum limits within which Schmitt trigger&#39;s trip point must remain, becomes tighter, and therefore variation in operating conditions (PVT) easily makes the trip point to move outside the limits. So a Schmitt trigger that supports one standard nicely may not be working well for other desired standards.  
         [0009]     For an example, a Schmitt trigger shown in  FIG. 2 ( a ) is sized to support general-purpose standards, namely, 5V CMOS, LVTTL, LVCMOS, LVCMOS-2.5V, LVCMOS-1.8, LVCMOS-1.5V and LVCMOS-1.2V. The limits for its trip-point variation for a given standard are set by V ilmax  and V ihmin  specification of the standard. Table 1 shows the V ihmin  and V ilmax  specifications of the desired standards. It is to be noted that power supply VCCI of the Schmitt trigger  150  can vary with standard, which is also specified in Table 1. For details JEDEC standard of corresponding general purpose standard can be referred.  
                                                         TABLE 1                                   Standards   Vilmax   Vihmin   VCCI                                        5 V CMOS   1.0   3.5   3.3           LVTTL   0.8   2.0   3.3           LVCMOS   0.8   2.0   3.3           LVCMOS-2.5 V   0.7   1.7   2.5           LVCMOS-1.8 V   0.63   1.17   1.8           LVCMOS-1.5 V   0.52   0.97   1.5           LVCMOS-1.2 V   0.42   0.78   1.2                      
 
         [0010]     FIGS.  2 ( b ) through  2 ( d ) show the variation in trip point of a Schmitt trigger with different operating conditions for general-purpose standards. All the characteristic curves of Schmitt trigger  150  are plotted for the output  190  against the input  197 . Each figure has three curves, one at a typical condition while other two are at extreme conditions, SF (Slow models for NMOS, Fast Models for PMOS, temperature and power supply are best) and FS (Fast models for NMOS, Slow models for PMOS and temperature and supply voltage are the worst).  
         [0011]      FIG. 2 ( b ) shows Schmitt trigger&#39;s characteristic curves for a nominal 3.3 volt VCCI supply. In this case, Schmitt trigger supports 5V CMOS, LVTTL and LVCMOS standards. Curve  3 . 3 _typ is plotted for typical operating conditions and curves  3 . 3 _fs and  3 . 3 _sf are plotted for two extreme operating conditions. It can be seen that extreme curves are within the V ihmin  and V ilmax  limits marked in the figure. So in this case, the Schmitt trigger is operating within the specifications of 5V CMOS, LVTTL and LVCMOS standards.  
         [0012]      FIG. 2 ( c ) shows Schmitt trigger&#39;s characteristic curves for nominal 2.5 volt and 1.8V VCCI supplies supporting LVCMOS-2.5V, LVCMOS-1.8V standards respectively. Similar to  FIG. 2 ( b ), curves for typical and extreme operating conditions are plotted. In the case of LVCMOS-2.5V, extreme curves are within the V ihmin  and V ilmax  limits but for the LVCMOS-1.8V case extreme curves move outside the V ihmin  and V ilmax  limits. So in this case, the Schmitt trigger is operating within the specifications of LVCMOS-2.5V but violates the specifications of LVCMOS-1.8V.  
         [0013]      FIG. 2 ( d ) shows Schmitt trigger characteristic curves for nominal 1.5 volt and 1.2V VCCI supplies supporting LVCMOS-1.5, LVCMOS-1.2 standards respectively. Similar to  FIG. 2 ( c ), curves for typical and extreme operating conditions are plotted. Here both LVCMOS-1.5V and LVCMOS-1.2V, extreme curves move outside the V ihmin  and V ilmax  limits. So in this case the Schmitt trigger violates specifications of both LVCMOS-1.5V and LVCMOS-1.2V standards.  
         [0014]     From the example, it is apparent that a Schmitt trigger designed to support a number of general-purpose standards, supports some of the standards nicely but violates specification of others. It is also to be noted that, even though performing within the specification, a large variation in trip point is not desirable, as it will be affecting the duty cycle and the quality of the signal.  
         [0015]     Secondly, it is desirable to have a single input receiver circuitry capable of supporting most of the interfacing standards, instead of having a number of receivers in parallel and then selecting the output of the desired one.  
       BRIEF SUMMARY OF THE INVENTION  
       [0016]     The disclosed embodiments of the present invention provide a CMOS input buffer supporting multiple IO standards having reduced layout area. It is desired to provide an input buffer that supports general-purpose logic inputs as well as high-speed inputs. In addition, a circuit is provided that generates the reference voltage for the case of general-purpose standards internally.  
         [0017]     Optimally, the disclosed embodiments provide a circuit that reduces variations in the receiver&#39;s trip point with varying operating conditions as the reference voltage is generated internally, and to provide a circuit whose frequency of operation is highly improved. Ideally, the duty cycle and quality of the signal are maintained.  
         [0018]     In accordance with one embodiment of the present invention, a CMOS input buffer supporting multiple I/O standards is provided that includes a pair of NMOS and PMOS differential receivers each having one input connected to the input pad and the second input connected to a reference voltage; a first multiplexer connected to the control terminal of the current sink of said NMOS differential receiver, having one input connected to the negative supply terminal/ground; a second multiplexer connected to the control terminal of the current source of said PMOS differential receiver, having one input connected to the positive supply terminal; an inverter connected to the combined output of said PMOS and NMOS differential receivers having its output connected to the second input of said first and second multiplexer; and a configuration storage bit for selecting the desired inputs of said first and second multiplexer, thereby supporting high speed standards as well as general purpose standards, while reducing static power dissipation.  
         [0019]     The CMOS input buffer in accordance with the foregoing embodiment preferably supports an internally generated reference voltage, and it supports FPGA and other programmable devices.  
         [0020]     The said PMOS and NMOS differential receivers are configured to support general purpose standards to minimize static power dissipation and reduce susceptibility to different processes and conditions.  
         [0021]     In accordance with another embodiment of the present invention also provides a method for supporting multiple IO standards for a CMOS input buffer that includes the steps of applying the input signal simultaneously to one input of an NMOS and a PMOS differential receiver; supplying a reference voltage to the second input of each of said NMOS and said PMOS differential receiver; combining and inverting the outputs of said NMOS and said PMOS differential receivers; multiplexing the control input of the current sink/source of each of said NMOS and said PMOS differential receiver between a supplied positive/negative supply voltage and said inverted output; and selecting the supplied positive/negative supply voltage in case of high-speed interface, while selecting said inverted output for standard logic signal.  
         [0022]     In accordance with another embodiment of the invention, an input buffer is provided that includes a signal input to receive an input signal; a reference voltage input to receive a reference voltage; an output node to receive output signals; a control circuit configured to generate a control signal to select whether the input buffer will support one of general purpose standards and high speed standards; a first differential amplifier coupled to the signal input, to the reference input, and to the output node, a control input coupled to an output of the control circuit, and a feedback input coupled to an output terminal that is coupled to the output node; and a second differential amplifier coupled to the signal input, to the reference input, and to the output node, a control input coupled to an output of the control circuit, and a feedback input coupled to an output terminal that is coupled to the output node.  
         [0023]     In accordance with another embodiment of the invention, a circuit for interfacing devices operating at various standards and speeds is provided that includes at least one input buffer that includes first and second differential amplifiers each having a first input for receiving an input signal and a second input for receiving a reference voltage, and a control input for receiving a control signal, the first and second differential amplifiers functioning as conventional differential comparator to support high speed standards in response to a control signal at a first level and configured to support general standards in response to the control signal at a second level.  
         [0024]     In accordance with another embodiment of the invention, a method for interfacing devices operating at various speeds and standards is provided that includes receiving an input signal at first and second differential amplifiers; receiving a reference voltage at each of the first and second differential amplifiers; combining and inverting the outputs of the first and second differential amplifiers and feeding back the combined inverted outputs to the first and second differential amplifiers; and generating a control signal to the first and second differential amplifiers to operate as a conventional differential comparator to support high speed standards when the control signal is at a first level and to operate as differential amplifiers in support of general interfacing standards for a standard logic signal when the control signal is at a second level. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0025]     The disclosed embodiments of the present invention will now be described with reference to the accompanying drawings, wherein:  
         [0026]      FIG. 1  shows a block diagram of known input buffers.  
         [0027]      FIG. 2  ( a ) shows the circuit diagram of a known Schmitt trigger used in a buffer of  FIG. 1 .  
         [0028]      FIG. 2  ( b ) to  FIG. 2  ( d ) show the dc characteristics of the Schmitt trigger of  FIG. 2  ( a ).  
         [0029]      FIG. 3  shows the circuit diagram of an NMOS differential input receiver used in the buffer of  FIG. 1 .  
         [0030]      FIG. 4  shows the circuit diagram of a PMOS differential input receiver used in the buffer of  FIG. 1 .  
         [0031]      FIG. 5  shows the block diagram of an input buffer in accordance with the present invention.  
         [0032]      FIG. 6  shows the circuit diagram of an input buffer in accordance with the present invention.  
         [0033]      FIG. 7  shows the block diagram of a grouping of input buffers in accordance with the present invention.  
         [0034]      FIG. 8  ( a ) shows the circuit diagram of a basic reference voltage circuitry.  
         [0035]      FIG. 8  ( b ) to  FIG. 8  ( d ) show the dc characteristics of an input buffer of the present invention.  
         [0036]      FIG. 9 ( a ) and  FIG. 9 ( b ) show the comparison in the trip points of the present invention&#39;s input buffer and a known Schmitt trigger at extreme processes and temperature conditions respectively. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0037]      FIG. 5  shows the block diagram of an input buffer  500  in accordance with the present invention. The block  501  is the NMOS-type differential input receiver while block  502  is the PMOS-type differential input receiver. One of the inputs Din to the differential receivers comes from the input pad  100 . The other input is the reference voltage VREF. The output of  501  and  502  are connected together to the input of an inverter I 1 . The output of the inverter I 1  is Cin, which is the input signal to the core. A feedback is taken from the output Cin to blocks  501  and  502 . This is required to reduce power dissipation in the differential receivers when operating in a general purpose standards environment. The source of the reference voltage VREF is not shown here, but it can be given externally or can be generated internally within the chip.  
         [0038]     The configuration bit CB 1  decides whether the input buffer is configured to support general purpose standards like CMOS 5V, LVTTL, LVCMOS, LVCMOS2 etc. or various high speed standards like GTL, GTL+, HSTL, SSTL3, SSTL2 etc.  
         [0039]      FIG. 6  shows the circuit diagram of the input buffer in accordance with the present invention. In the NMOS differential amplifier of block  501 , the gates of NMOS devices N 1  and N 2  are connected to the two input signals Din and VREF, respectively. The source of N 1  and N 2  are connected together to the drain of N 3 . The drains of N 1  are connected to the gate of N 3  and also to the gates of PMOS devices P 5  and P 6 . The gates of P 5  and P 6  are connected to the drain of P 5  while their sources are connected to VDD. The drain of P 6  is connected to the OUT terminal. The drain of N 4  is connected to the source of N 3 , while its source is connected to the ground. The gate of N 4  is connected to the output of the multiplexer  10 , which passes either VDD, or output of buffer Cin depending on CB 1 .  
         [0040]     In the PMOS differential receiver of block  502 , the gates of PMOS P 1  and P 2  are connected to Din and VREF respectively. The drains of P 1  and P 2  are connected to the drains of N 5  and N 6  respectively. The drain of N 6  is connected to the OUT terminal of this receiver. The gates of N 5  and N 6  are connected together to the drain of N 5  while their sources are grounded. The source of P 1  and P 2  are connected together to the drain of P 3 . The gate of P 3  is connected to the drain of N 5 , while its source is connected to the source of P 4 . P 4  has its source connected to the VDD and gate connected to the output of the multiplexer  11 . The multiplexer  11  has the ground and Cin as its input while the configuration bit CB 1  is its control signal.  
         [0041]     The configuration bit CB 1  configures the input buffer to support multiple standards. When CB 1 =0, it supports various high-speed standards. On other hand when CB 1 =1, it supports various general-purpose standards.  
         [0042]     To understand the operation of the circuit, consider the following cases:  
         [0000]     1. CB 1 =0:  
         [0043]     When CB 1  is LOW, the output of multiplexer  10  and  11  is VDD and GND respectively. This will make N 4  and P 4  permanently ON. The two differential receivers  501  and  502  work as a conventional differential comparator.  
         [0044]     When Din is greater than VREF, the resistance of N 1  decreases while the resistance of P 1  increases. This will increase the current through the N 1  branch as compared to the N 2  branch, and similarly current through the P 2  branch becomes higher than in the P 1  branch. This will make the Out terminal at a HIGH logic. The inverter I 1  helps to achieve the CMOS logic levels. This makes Cin at LOW.  
         [0045]     On the other hand, when Din is less than VREF, the resistance of N 1  increases while the resistance of P 1  decreases. Due to this, the current through branch N 1  is less than that in N 2  branch and also current through the P 1  branch is higher than in the P 2  branch. This makes the output OUT at a LOW logic and Cin at a HIGH logic.  
         [0046]     Standards that require a lower VREF e.g., HSTL, GTL, GTL+, are implemented in the PMOS differential amplifier of block  502 , and in this case the NMOS differential amplifier only assists to improve the logic levels and switching speed. Standards that require a higher VREF e.g., SSTL2, SSTL3 etc., are mainly implemented in the NMOS differential amplifier  501  and the PMOS differential amplifier  502  will help in improving the switching speed and levels of the output.  
         [0000]     2. CB 1 =1  
         [0047]     In this mode of operation, the differential amplifiers are configured to support general-purpose standards. Depending upon the general purpose standard to be supported, the reference voltage VREF and power supply VDD of the differential amplifiers are given accordingly. Table 2 below shows the reference voltage and corresponding supply voltage to be given to support the desired standard.  
                                                 TABLE 2                                   Standards   VREF   VDD                                        5 V CMOS   1.5   3.3           LVTTL   1.5   3.3           LVCMOS   1.5   3.3           LVCMOS-2.5 V   1.25   2.5           LVCMOS-1.8 V   0.9   1.8           LVCMOS-1.5 V   0.75   1.5           LVCMOS-1.2 V   0.6   1.2                      
 
         [0048]     For a full swing CMOS input signal, a continuous static current is flowing through the differential amplifiers in normal configuration, in comparison to zero static current in the Schmitt trigger. To avoid this, the circuit is configured in such a way that power consumed in operation of these standards remains almost the same as that in the case of the Schmitt trigger.  
         [0049]     To hold a HIGH logic at the output OUT, the PMOS differential amplifier  502  is used, and at this time the NMOS differential amplifier  501  is cut off. On the other hand, the NMOS differential amplifier  501  holds a LOW logic, and at this moment the PMOS differential amplifier  502  is cut off. This type of operation ensures negligible static current flowing in the differential amplifiers for CMOS and TTL input swings and therefore reduces power dissipation. Detailed explanation of this operation is given in the following text.  
         [0050]     When CB 1  is HIGH, the output of the multiplexer  10  and  11  is connected to Cin.  
         [0051]     Consider the case when Din&gt;VREF. For this, OUT is HIGH and Cin=0. As Cin is LOW, N 4  is off while P 4  is ON. This puts the NMOS differential amplifier  501  in cut off, and therefore no static current will flow through it.  
         [0052]     In the PMOS differential amplifier  502 , for full swing input signals applied at input Din, (e.g., for 3.3V supply voltage, the input swing is from 0 to 3.3V) when Din is HIGH, P 1  is OFF, which results in a LOW gate voltage (Vtn) at N 5  and N 6 , where Vtn is NMOS&#39;s threshold voltage. As N 6  is in the sub threshold region, VDD will appear at the drain of N 6 , which is the OUT terminal. As P 1  and N 6  are off, negligible static current will flow through PMOS differential amplifier. By this way, HIGH logic is held at the output OUT without any static power dissipation. As OUT is HIGH, Cin is LOW. This keeps N 4  OFF and P 4  ON.  
         [0053]     Similarly, consider the case when Din&lt;VREF. For this, OUT is LOW and Cin is HIGH. As Cin is HIGH, P 4  is off while N 4  is ON. This makes PMOS differential amplifier  502  cut off, and therefore no static current will flow through it.  
         [0054]     In the NMOS differential amplifier  501 , for full swing input signals applied at input Din, when Din is LOW, N 1  will be OFF. This results in a HIGH gate voltage (VDD-Vtp) at P 5  and P 6 , where Vtp is PMOS&#39;s threshold voltage. As P 6  is in a sub threshold region, GND will be applied at the drain of P 6 , which is the OUT terminal. As N 1  and P 6  are off, negligible static current will flow through NMOS differential amplifier. By this way, a LOW logic is held at the output OUT without any static power dissipation. As OUT is LOW, Cin is HIGH. This keeps P 4  OFF and N 4  ON.  
         [0055]     Hence general-purpose standards are supported using differential amplifiers without any static power dissipation. The hysteresis can also be implemented in differential amplifiers so that various standards can be supported with improved noise margin.  
         [0056]     For a FPGA to support general-purpose standards, the reference voltage VREF can be given externally like other high-speed standards. But for general-purpose standards, the external reference voltage would be incompatible and undesirable, so VREF is generated internally. We can use one reference voltage generation circuitry for a group of input receivers.  FIG. 7  shows a group of input receivers  500  in which one reference generating circuitry Ref_Gen is used for every six receivers. Each receiver can be configured to receive the external reference VREFext or the internal reference VREFint through switches S 1  and S 2  respectively.  
         [0057]      FIG. 8  ( a ) shows the basic circuit Ref_Gen for reference voltage generation that is made up of resistances R and capacitor C. The variation in the reference voltage due to different processes and temperature conditions, generated through this circuitry is much smaller.  
         [0058]     FIGS.  8 ( b ) through  8 ( d ) show the variation in trip point of the input buffer  500  with operating conditions for different general-purpose standards. All the characteristic curves of input buffer  500  are plotted for output Cin against input Din. Each figure has three curves, one at typical condition while the other two are at extreme conditions, SF (Slow models for NMOS, Fast Models for PMOS, temperature and power supply are best.) and FS (Fast models for NMOS, Slow models for PMOS and temperature and supply voltage are the worst). The Ref_Gen circuit of  FIG. 8 ( a ) is used to generate the reference voltage.  
         [0059]      FIG. 8 ( b ) shows the present invention input buffer&#39;s characteristic curves for nominal 3.3 volt supply voltage. In this case, the input buffer supports 5V CMOS, LVTTL and LVCMOS standards.  
         [0060]      FIG. 8 ( c ) shows the input buffer&#39;s characteristic curves for nominal 2.5V and 1.8V supply voltage supporting LVCMOS2 and LVCMOS1.8V standards respectively.  
         [0061]     On other hand  FIG. 8 ( d ) shows the input buffer&#39;s characteristic curves for nominal 1.5V and 1.2V supply voltage supporting LVCMOS1.5 and LVCMOS1.2V IO standards respectively.  
         [0062]     In all the cases the extreme curves are well within the V ihmin  and V ilmax  limits marked in the figures. Moreover, the variation in the trip point for different processes and conditions are much less compared to that in previous Schmitt triggers.  
         [0063]      FIG. 9  shows the comparison in the trip points of the present invention&#39;s input buffer, which uses Ref_Gen circuitry for generating reference voltage VREF, and the previous Schmitt trigger at extreme processes and temperature conditions. For these curves, the supply voltage is a constant 3.3V. For one extreme SF, the models for NMOS are slow while the PMOS are fast and temperature is maximum, while for other extreme FS, the models for NMOS are fast while the PMOS are slow and the temperature is minimum. From the curves of the present invention input buffer  500 ,  FIG. 9 ( a ) and the previous Schmitt trigger  FIG. 9 ( b ), it is clear that the variation in the trip point of the input buffer of present invention is much less as compared to the variation in the trip point of the Schmitt trigger.  
         [0064]     With this design, a Schmitt trigger can be eliminated in the input buffer architecture. This will reduce the layout area and also increase the frequency of operation since the differential comparator is used for TTL and CMOS standards. Moreover, the input receiver is very less susceptible to the different processes and temperature conditions as differential amplifiers are normally symmetrically designed.  
         [0065]     It will be apparent that the use of internal reference voltage VREF int  is not limited to general-purpose standards and can also be used for high-speed standards. In the present invention, instead of having a number of receivers in parallel, input receiver circuitry is made more versatile, and thus avoids the need of an output selection multiplexer. To support general-purpose standards, the differential amplifier does not directly replace the Schmitt trigger. Instead, a unique connectivity is provided within the differential amplifier to avoid static power dissipation.  
         [0066]     All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.  
         [0067]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims and the equivalent thereof.