Abstract:
According to one non-limiting embodiment, a low conductive emission substrate includes a plurality of thin high dielectric strength insulating layers separated by a corresponding plurality of conductive layers, wherein one of the plurality of conductive layers is shorted to another one of the plurality of conductive layers.

Description:
BACKGROUND 
     This application relates to a multi-layer substrate for an electronic device, and more particularly to forming a low conductive emission substrate for an electronic device. 
     Electronic components, such as switches, can be formed on a die which can then be received on a substrate for inclusion in a larger electronic circuit. For example,  FIG. 1  schematically illustrates a first prior art multi-layer substrate  10  for an electrical component  12 , such as a die. The substrate includes a single conductive layer  14  and a single insulating layer  16  (or “dielectric layer”) formed on a ground structure  18 . The conductive layer  14  is formed on the insulating layer  16 , and receives the electrical component  12 . An effective parasitic capacitance  20  occurs between the conductive layer  14  and the ground structure  18  via the insulating layer  16 , and causes undesired electromagnetic conductive emission, or effective parasitic capacitance  20  to the ground structure  18 . Also, an undesired thickness of the insulating layer  16  prevents the substrate  10  from effectively facilitating a transfer of heat from the electrical component  12  to the ground structure  18 . 
       FIG. 2  schematically illustrates a second prior art substrate  40  that includes a plurality of insulating layers  42   a - e  separated by a plurality of conductive layers  44   a - d . The first insulating layer  42   a  has a thickness of 381 microns (15 mils), which is also undesirably thick. However, this substrate  40  still demonstrates the undesired electromagnetic conductive emission problem discussed above. 
     SUMMARY 
     An example low conductive emission substrate includes a plurality of thin high dielectric strength insulating layers separated by a corresponding plurality of conductive layers, wherein one of the plurality of conductive layers is shorted to another one of the plurality of conductive layers. 
     An example method of manufacturing a low conductive emission substrate includes forming a first insulating layer, forming a first conductive layer on the first insulating layer, forming a second insulating layer on the first conductive layer, and forming a second conductive layer on the second insulating layer. The method also includes electrically coupling the first conductive layer to the second conductive layer. 
     These and other features of the present invention can be best understood from the following specification and drawings, the following of which is a brief description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically illustrates a first prior art multi-layer substrate for an electrical component. 
         FIG. 2  schematically illustrates a second prior art multi-layer substrate for an electrical component. 
         FIG. 3  schematically illustrates a second multi-layer substrate for an electrical component. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     As discussed above,  FIG. 1  schematically illustrates a first, prior art multi-layer substrate  10  for an electrical component  12 , that exhibits an effective parasitic capacitance  20  and poor heat transfer from the electrical component  12  to the ground structure  18 . It is understood that the parasitic capacitance  20  effectively behaves as a capacitor but does not correspond to an actual capacitor. The substrate  40  illustrated in  FIG. 2  also exhibits this undesired parasitic capacitance. 
       FIG. 3  schematically illustrates a second multi-layer substrate  22  that is operable to accommodate the effective parasitic capacitance  20  and is operable to conduct heat from the electrical component  12  to the ground structure  18 . The substrate  22  includes a plurality of thin high dielectric strength insulating layers  16   a ,  16   b  separated by a corresponding plurality of conductive layers  14   a ,  14   b . The term “high dielectric strength” refers to a dielectric strength greater than 500 volts per mil (19.68 volts per micron). In one example “high dielectric strength” refers to a dielectric strength of at least approximately 15,876 volts per mil (6.25 volts per micron). As shown in  FIG. 3 , the substrate  22  includes ground structure  18 , a first insulating layer  16   a  formed on the ground structure  18 , and a first conductive layer  14   a  formed on the first insulating layer  16   a . The ground structure  18  could include any structure used for a ground connection, such as a ground plate. 
     As described above, an effective parasitic capacitance  20  occurs between the first conductive layer  14   a  and the ground structure  18  via the first insulating layer  16   a . To address the effective parasitic capacitance  20 , a second insulating layer  16   b  is formed on the first conductive layer  14   a , and a second conductive layer  14   b  is formed on the second insulating layer  16   b . The conductive layers  14   a ,  14   b  are electrically coupled via a connection  24  to form a second effective parasitic capacitance  26  between the second conductive layer  14   b  and the first conductive layer  14   a  via the second insulating layer  16   b . The second parasitic capacitance  26  negates the effects of the effective parasitic capacitance  20 , and provides a conductive emissions protection function by reducing electromagnetic emission to the ground structure  18 . In one example the substrate  22  is operable to reduce conductive emissions to a level 1,000 times less than that exhibited by substrate  10 . The substrate  22  may therefore be described as a low conductive emission substrate. 
     The electrical component  12  is received on the second conductive layer  14   b . In one example, the electrical component  12  corresponds to a MOSFET, JFET, or BJT switch which may be formed on a die. The layers  14   a ,  16   a  provide a “Faraday shield” due to the insulating effect they provide between the electrical component  12  and the ground structure  18 . 
     The insulating layers  16   a ,  16   b  may be formed using a pulsed laser deposition technique in which a laser is pulsed to form a thin layer of insulating material, or may be formed using an E-beam deposition process (in which an electron beam is used instead of a laser beam). In one example the insulating layers  16   a ,  16   b  have a thickness significantly less than 381 microns (15 mils). In one example the insulating layers  16   a ,  16   b  have a thickness of 1 micron (0.04 mils). In one example the insulating layers  16   a ,  16   b  have a thickness between 0.05-5.00 microns (0.0019-0.196 mils). Some example deposited materials for the insulating layers  16   a ,  16   b  include silicon carbide (“SiC”), silicon nitride (“Si 3 N 4 ”), silicon dioxide (“SiO 2 ”), aluminum nitride (“AlN”), aluminum oxide or alumina (“Al 2 O 3 ”), and hafnium dioxide or hafnia (“HfO 2 ”). One laser capable of forming the layers  16   a ,  16   b  is manufactured by BlueWave Semiconductors. Reducing a thickness of the layers  16   a ,  16   b  can improve the thermal conductivity of the substrate  22  to conduct heat from the electrical component  12  to the ground structure  18  efficiently. 
     The conductive layers  14   a ,  14   b  may also be formed using the pulsed laser deposition technique, the E-beam deposition technique, or a chemical vapor process. Some example deposited materials for the conductive layers  14   a ,  14   b  include copper, aluminum, nickel, and gold. The formation of thin conductive layers  14   a ,  14   b  can also help improve thermal conductivity between the electrical component  12  and the ground plate  18 . The laser deposition technique mentioned above results in a layer of material deposited in column-like formations. 
     Equation 1, shown below, may be used to calculate a capacitance. 
     
       
         
           
             
               
                 
                   C 
                   = 
                   
                     
                       
                         ɛ 
                         r 
                       
                       · 
                       
                         ɛ 
                         0 
                       
                       · 
                       A 
                     
                     d 
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
             
           
         
       
     
     where
         A is a surface area of a conductive layer;   d is a distance between conductive layer;   ∈ r  is a dielectric constant of a given material; and   ∈ 0  is the standard dielectric constant of air.       

     As shown in Equation 1, decreasing the distance between conductive layers  14   a ,  14   b  can undesirably increase the effective parasitic capacitance  20  of the multi-layer substrate  22 . However, by electrically coupling the conductive layers  14   a ,  14   b  via connection  24 , the effective parasitic capacitance  20  can be diminished. 
     Although a preferred embodiment of this invention has been disclosed, a worker of ordinary skill in this art would recognize that certain modifications would come within the scope of the claims. For that reason, the following claims should be studied to determine their true scope and content.