Abstract:
A plurality of variable gain amplifier stages are coupled by an attenuation circuit that receives a voltage input to be amplified. A control circuit activates each of the variable gain amplifier stages in a seamless manner in accordance with a control signal applied to a voltage control node, while maintaining no more than one of the stages active at any time. Fractions of the reference signal voltage level are set to define boundaries between control voltage level ranges of the amplifier stages. A unique control voltage level range is thus established for each amplifier stage. A control voltage hysteresis range can be provided to avoid oscillations between stages at the transition voltages.

Description:
TECHNICAL FIELD  
       [0001]     The present disclosure relates to variable gain amplifiers, more particularly to a wide dynamic range amplifier having a plurality of switched amplifier stages.  
       BACKGROUND  
       [0002]     A variety of circuit applications require high accuracy variable gain amplification over wide frequency bandwidths. For example, linear-in-db true power detectors have been needed for measurement and control of true electrical power over an operating frequency range from low frequency to as high as 2.5 GHz, with a 60 dB dynamic range. As these operating ranges continue to increase, challenges are presented to provide the required high accuracy amplification. A variable gain amplifier, operable over an extended frequency bandwidth should consume a minimum of power while maintaining high accuracy over a wide range of temperature variation.  
       SUMMARY OF THE DISCLOSURE  
       [0003]     The subject matter described herein fulfills the above-described needs. A plurality of variable gain amplifier stages are coupled by an attenuation circuit that receives a voltage input to be amplified. A control circuit activates each of the variable gain amplifier stages in a seamless manner in accordance with a control signal applied to a voltage control node, while maintaining no more than one of the stages active at any time. Fractions of the reference signal voltage level are set to define boundaries between control voltage level ranges of the amplifier stages. A unique control voltage level range is thus established for each amplifier stage.  
         [0004]     For each amplifier stage, a comparator is coupled by its first input to the voltage control node. A second attenuation circuit is coupled between a voltage reference node and a second input of each comparator. The second attenuation circuit nodes set the control voltage level boundary ranges. Each amplifier stage is activated in dependence upon an output from its corresponding comparator. The output of each comparator is coupled to a switch node, which can receive a switch activation signal to activate the corresponding amplifier stage at an activation input thereof.  
         [0005]     As the level of the control voltage is varied, a new one of the amplifier stages is activated when the level of the control voltage is within the control voltage level range for the new amplifier stage and the previously activated amplifier stage is deactivated. A seamless transition between activated stages takes place. To avoid transition oscillation, the voltage control node can be connected to the first input of each comparator through a respective impedance. A junction between the first input of each comparator and its respective impedance is then connected to a respective controlled switch that is activated by the switch node corresponding to the comparator to which it is coupled. When an amplifier stage is activated, the lower boundary level of the control voltage range for that amplifier stage is reduced by impedance inserted by the controlled switch activation. Amplifier stage transition hysteresis is thus provided.  
         [0006]     A logic circuit, having a plurality of outputs, is connected to each comparator output. One of the switch nodes is coupled directly to the output of one of the comparators, the remaining switch nodes being coupled to a respective output of the logic circuit. Each switch node also is coupled to a respective voltage level shift stage that can be activated in response to a received switch activation signal from the switch node. An input of each voltage level shift stage is coupled to a respective node of the second attenuation circuit. The voltage control node and the voltage level shift stages are coupled to a voltage to current converter circuit that produces a current control signal related to a shifted level of the voltage at the voltage control node.  
         [0007]     A circuit is provided to compensate for the effects of temperature. A multiplier has a first input coupled to the output of the voltage to current converter for receiving the current control signal, and a second input for receiving a temperature compensation signal. The multiplier output is coupled to an amplifier gain control circuit to provide a current control signal thereto that is adjusted for temperature.  
         [0008]     Additional advantages will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     Implementations of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.  
         [0010]      FIG. 1  is a block diagram of a multi-stage variable gain amplifier in accordance with the present invention.  
         [0011]      FIG. 2  is a diagram of a gain control characteristic of the variable gain amplifier of  FIG. 1 .  
         [0012]      FIG. 3  is a block diagram of a control scheme for the variable gain amplifier of  FIG. 1 .  
         [0013]      FIG. 4  is a block diagram for a variation of the block diagram of  FIG. 3  with a modification of the comparator input circuits. 
     
    
     DETAILED DESCRIPTION  
       [0014]     A multi-stage variable gain amplifier in accordance with the present invention is illustrated in the block diagram of  FIG. 1 . The amplifier is coupled between to a variable input voltage V IN  and produces an output signal at I OUT . A plurality of amplifier stages  10 , indicated as G 1 -G n , each have an output connected to I OUT . Each gain stage is a variable gain amplifier, such as any known amplifier having at least a limited range of gain control. V IN  is coupled to an attenuation circuit that comprises a plurality of series connected resistors  12 , with a junction between each pair of transistors connected to ground through a resistor  14 . The values of the resistors may be equal to each other or selected to provide a desired relationship between the voltage magnitudes at the junctions and V IN . The illustrated resistors are merely representative of any impedances that may serve a voltage dividing functionality. Preferably, a fixed series-shunt resistive attenuation is provided between any two amplifier stages.  
         [0015]     An input of amplifier stage G 1  is directly connected to V IN . Inputs of amplifier stages G 2 -G n  are connected to successive junctions at lower proportional voltage magnitudes. The gain of each amplifier stage is controlled by a respective gain control signal GC 1 -GC n . Each amplifier stage is turned on or off by a respective switch activation signal SWH 1 -SWH n . Only one gain stage is activated at any time. The switch activation signals are responsive to a variable analog control signal as described hereinafter. By seamlessly synchronizing the individual gain stages and the gain control of each stage throughout the range of the control signal, a much wider dynamic range of variable gain amplification can be obtained with wide operating frequency bandwidth at low power consumption.  
         [0016]     A desirable gain control characteristic in dB versus analog control voltage V ctl  is exemplified in  FIG. 2 . The gain response is linear in dB throughout the entire control voltage range. As shown, each of the gain stages is selected to be activated for a particular range of control voltage of 0.2 s. The maximum gain is produced at near zero control voltage, the gain decreasing in linear manner as the control voltage increases to a maximum. Amplifier stage G 1 , which is directly connected to the input voltage, outputs the greatest gain over a control voltage range of up to 0.2 volt. Each successive amplifier stage receives a more greatly attenuated input voltage and is activated at a higher control voltage range than the preceding stage. The boundaries of the control voltage range for the first amplifier stage are zero and 0.2 volt; for the second amplifier stage the control voltage range boundaries are 0.2 volt and 0.4 volt, etc. The ranges of gain and control voltage shown are merely illustrative, as the voltage magnitude of the control voltage range can be selected in accordance with the number of amplifier stages and the operating parameters of the stages.  
         [0017]      FIG. 3  is a block diagram illustrative of the activation and control scheme for operating amplifiers G n . For simplicity of illustration and explanation, three amplifier stages are considered. The number of stages used in any particular implementation can be increased to provide a desirable broader range of amplification. Switch activation signals SWH 1 -SWH 3  are produced in response to the outputs of respective comparators  18 . A negative input of each comparator is connected to the control voltage V ctl . A reference voltage V ref  is coupled to an attenuation circuit that comprises a plurality of series connected resistors  20  and ground. A junction of each resistor  20  is connected to a positive input of a respective one of the comparators  18 .  
         [0018]     For the described example of  FIG. 2 , the values of V ref  and resistors  20  are selected to provide voltage step differences of 0.2 volt at adjacent resistor junctions. The negative input of comparator for the first stage G 1 , which outputs the signal SWH 1 , receives the lowest reference voltage input, 0.2 volt. The comparator of each successive stage receives a higher reference voltage at its negative input. Each comparator will output a high signal until the control voltage exceeds the reference voltage applied to its positive input. A logic circuit  16  comprises logic elements  22  that receive inputs from the second and third stage comparators, respectively to produce switch activation signals SWH 2  and SWH 3 . Each logic circuit element  22  also receives an input from the comparator of the preceding stage and is designed to provide a high level switch activation signal only if the output of the preceding comparator is low and the output of its corresponding stage comparator is high. This operation ensures that only one amplifier stage is activated during a given control voltage range.  
         [0019]     Switch activation signals SWH 1 -SWH 3  are fed to a gain control setting current distributor  24 . Only one of the gain control signals GC 1 -GC 3  is output for the amplifier stage that corresponds to a high level switch activation signal received at the current distributor input. The gain control signals are produced in accordance with a current control signal I ctl  and a temperature compensation signal I ptat . The temperature compensation signal, which preferably is generated by a current source, is proportional to the absolute value of temperature. These signals are multiplied by multiplier  25  and applied as a compensated gain control signal to the current distributor.  
         [0020]     Current control signal I ctl  is output by differential voltage to current converter circuit  26 . This circuit has a first input V x  that is a shifted level of the reference voltage applied to the selected one of the comparators  18  and a second input that is a shifted level of the control voltage. The output signal of the voltage to current converter circuit  26  is related to the difference between the two input signals. A switched operational amplifier  28  is coupled to the reference voltage input of each comparator  18  to receive reference voltage V 1  for the first stage, reference voltage V 2  for the second stage, and reference voltage V 3  for the third stage. Switch activation signals SWH 1 -SWH 3  are coupled to respective inputs of the amplifiers  28 .  
         [0021]     As the control voltage is varied from zero to its maximum, such as exemplified in  FIG. 2 , the following operation occurs. In the control voltage range from zero to 0.2 volt, each of the outputs of comparators  18  will be at a high level. The logic circuit  16  permits only switch activation signal SWH 1  to be high. This high level signal is applied to the current distributor circuit to apply a gain control signal output at GC 1 . The high level SWH 1  signal is also applied to activate the operational amplifier  28  that corresponds to the first stage to output V 1  as V x . Current control signal I ctl , related to the difference between the two input signals to the voltage to current converter circuit  26 , is multiplied by the temperature compensation signal I ptat  and applied by the current distributor to produce the signal GC 1 . As the control signal is increased within the range for the first amplifier stage, the gain control signal will be varied, decreasing linearly as shown in  FIG. 2 .  
         [0022]     When the control voltage increases beyond 0.2 volt to the range of the second stage, the output of the first comparator will be low while the outputs of the remaining comparators are high. The logic circuit outputs a high level SWH 2  signal. SWH 3  and SWH 1  are low. The operational amplifier  28  that corresponds to the second stage is activated to output V 2  as V x . The current distributor circuit  24  is activated to apply a gain control signal output at GC 2 , which varies as the voltage control level increases until the higher second stage boundary range voltage of the second stage is reached. As the control voltage continues to increase, similar operation occurs for successive amplifier stages.  
         [0023]     Each of the operational amplifiers  28  continuously has applied to its input the appropriately shifted reference voltage for its corresponding gain stage. Likewise, one input to the current converter circuit  26  continuously receives a shifted V ctl . Upon a change of the logic circuit  22  output select signal output SWH responsive to a change in the control voltage range of V ctl , the appropriate operational amplifier  28  and gain stage GC are substantially simultaneously activated, thereby effecting an immediate transition to the next amplifier stage.  
         [0024]      FIG. 4  is a block diagram of a variation of the control scheme of  FIG. 3 . The comparator input circuits have been modified to assure that only one gain stage is on when the control voltage V ctl  is at or close to the transition voltage between any adjacent gain stages. For clarity of operation explanation, the comparators  18  have been further referenced as  18   a - 18   c  to correspond, respectively, to stages  1 - 3 . The control voltage input of each comparator  18  is coupled to the control voltage V ctl  through a resistor  30 . A controlled switch  32  is coupled between the comparator side of each resistor  30  and ground through a current source I OS . The control terminal of each switch  32  is coupled to one of the switch activation signals SWH 1 -SWH n  of the corresponding amplifier stage.  
         [0025]     Transitional operation is considered for the 0.2 volt range of control voltage for transition between stages in the example of  FIG. 2 . The reference voltage input at comparator  18   a  is 0.2 volt, at comparator  18   b  is 0.4 volt, an increases by 0.2 volt at each successive comparator. When the control voltage is below 0.2 volt it is lower than the reference voltage input at each of the comparators. The outputs of all comparators are at a high logic level. However, only switch activation signal SWH 1  is at a high level, as logic circuitry  16  precludes elevation of the higher stage switch activation signals. Only the first amplifier stage is in operation. The switch  32  of the first stage is active in response to the switch activation signal to provide a current path through resistor  30 . The voltage at the control (negative) input to comparator  18   a  is less than the control voltage by the voltage drop across resistor  30 .  
         [0026]     Transition to second stage operation will occur when the control input to comparator  18   a  rises to the transition boundary of 0.2 volt. At that time, V ct  is greater than 0.2 volt by the amount of the voltage drop across resistor  30 . The comparator output will change to a low logic level, switch activation signal SW 1  will change to a low logic level to turn off the first amplifier stage, and switch activation signal SW 2  will change to a high logic level to turn on the second amplifier stage. The switch  32  of the first amplifier stage will be deactivated to cease current flow in the series connected resistor  30 . In the absence of the resistive voltage drop, the voltage at the control input to comparator  18   a  jumps to V ctl . Operation will not transition back to the first amplifier stage until V ctl  falls below 0.2 volt. Thus, a control voltage hysteresis range is built in to avoid oscillations between stages at the boundary transition voltage. The same hysteretic transitional operation is provided at transitions between the other amplifier stages. The range of hysteresis can be changed by adjusting the current source I OS  and/or selecting a different value of resistance for resistors  30 .  
         [0027]     In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.