Abstract:
A method including receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a Divisional of co-pending patent application Ser. No. 13/244,626, filed Sep. 25, 2011, now allowed, the subject matter of which is incorporated herein by reference. 
     
    
     FIELD OF TECHNOLOGY 
       [0002]    This disclosure relates generally to methods and apparatus of limiting amplifiers. 
       BACKGROUND 
       [0003]    As is known, limiting amplifiers are widely used in optical communications. A limiting amplifier receives an input signal presenting a stream of binary data, amplifies the input signal into saturation with a high gain and outputs a substantially two-level output signal exhibiting the binary data. Limiting amplifiers preferably have a high gain so that they can amplify the input signal into saturation. At the same time, a limiting amplifier should have a sufficient speed to keep up with a rapid change in the input signal. In addition, as is common in many high-gain amplifiers, an offset at an input of a limiting amplifier needs to be properly handled; otherwise the offset may be amplified to an extent that the offset saturates a latter stage of the limiting amplifier regardless of the input signal. 
         [0004]    A conventional limiting amplifier  100  is depicted in  FIG. 1 . Limiting amplifier  100  comprises seven amplifier stages  110 - 170 , each receiving power from a power supply node V DD  and grounded to a ground node V SS , for receiving a differential input signal comprising two ends V i+  and V i  (hereafter V i+ /V i ) and outputting a differential output signal comprising two ends V o+  and V o  (hereafter V o+ /V o ). Limiting amplifier  100  further comprises a low pass filter (LPF)  190  for receiving the output signal V o+ /V o  and outputting a differential filtered signal comprising two ends V f+  and V f  (hereafter V f+ /V f ), and a feedback amplifier  180  for receiving the differential filtered signal V f+ /V f  and outputting a differential signal into two common nodes  111  and  112  that are shared with a first amplifier stage  110 . The seven amplifier stages  110 - 170  provide a high gain to the differential input signal V i+ /V i . However, there might be an offset at the input of first amplifier stage  110  that is also amplified by the high gain. LPF  190  comprises a pair of R-C network ( 191 - 192  and  193 - 194 ) to extract a low frequency component of the differential output signal V o+ /V o  that primarily originates from the offset. 
         [0005]    As a result, the differential filtered signal V f+ /V f  is basically an unwanted component of the output differential signal V o+ /V o . Feedback amplifier  180  receives the differential filtered signal V f+ /V f  , amplifies the differential filtered signal V f+ /V f  , and transmits the amplified output into the two nodes  111  and  112  with a polarity reversal. A negative feedback loop comprising amplifier stages  120 - 170 , LPF  190 , and feedback amplifier  180 , is thus formed. Due to LPF  190 , the negative feedback is effective only for the low frequency component of the differential output signal V o+ /V o  that primarily originates from the offset at the input of the limiting amplifier  100 . Due to the high gain nature of the negative feedback loop, the unwanted offset is effectively suppressed. The feedback amplifier  180 , however, increases loading at circuit nodes  111  and  112 , suppresses the amplification function of the first amplifier stage  110 , and slows down the overall speed of limiting amplifier  100 . 
         [0006]    What is desired is a limiting amplifier that utilizes a feedback scheme that does not slow down the overall speed of the limiting amplifier. 
       SUMMARY 
       [0007]    In one embodiment, an apparatus comprises a plurality of amplifier stages including a first amplifier stage and a last amplifier stage configured in a cascade arrangement, and a transconductance amplifier, wherein: the first amplifier stage is configured to receive an input signal; the last amplifier stage is configured to output an output signal; the transconductance amplifier is configured to receive a voltage signal from the last amplifier stage via a first resistor, and the transconductance amplifier is configured to output a current signal to an output node of the first amplifier stage via a second resistor in a negative feedback manner. A resistance of the first resistor is substantially greater than an output impedance of the last amplifier stage. A resistance of the second resistor is substantially greater than an output impedance of the first amplifier stage. The first amplifier stage is configured to receive power from a first power supply node. The transconductance amplifier is configured to receive power from a second power supply node. In an embodiment, a voltage potential of the second power supply node is higher than that of the first power supply node. 
         [0008]    In a second embodiment, a method comprises: receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage. In an embodiment, sensing the output signal comprises coupling to the output signal via a resistor of resistance substantially greater than an output impedance of the last amplifier stage. In an embodiment, injecting the current signal comprises coupling to the output node of the first amplifier stage via a resistor of resistance substantially greater than an output impedance of the first amplifier stage. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  shows a schematic diagram of a conventional limiting amplifier. 
           [0010]      FIG. 2  shows a schematic diagram of a limiting amplifier in accordance with an embodiment of the present invention. 
           [0011]      FIG. 3  shows a schematic diagram of an amplifier stage. 
           [0012]      FIG. 4  shows a schematic diagram of a transconductance amplifier. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    The following detailed description refers to the accompanying drawings which show, by way of illustration, various embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense. 
         [0014]    A limiting amplifier  200  in accordance with an embodiment of the present invention is depicted in  FIG. 2 . Limiting amplifier  200  includes a plurality of amplifier stages, for examples, seven amplifier stages  210 - 270 , each receiving power from a first power supply node V DD1  and grounded to a ground node V SS , for receiving a differential input signal comprising two ends V i+  and V i  (hereafter V i+ /V i ) and outputting a differential output signal comprising two ends V o+  and V o  (hereafter V o+ /V o ). Limiting amplifier  200  further comprises a transconductance amplifier  280 , a first resistor pair  291 - 292 , and a second resistor pair  293 - 294 . An input of transconductance amplifier  280  is coupled to the differential output signal V o+ /V o  via the first resistor pair  291 - 292 , resulting in a differential intermediate voltage signal comprising two ends V f+  and V f  (hereafter V f+ /V f ). Transconductance amplifies  280  amplifies the differential intermediate voltage signal V f+ /V f  into a differential current signal comprising two branches I o+  and I o  (hereafter I o+ /I o ). The differential current signal I o+ /I o  is injected into circuit nodes  211  and  212  via the second resistor pair  293 - 294 . Circuit nodes  211  and  212  are output nodes of the first amplifier stage  210 . Transconductance amplifier  280  receives power from a second power supply node V DD2  and is grounded to the ground node V SS . 
         [0015]    In an embodiment, the second power supply node V DD2  has a higher potential than the first power supply node V DD1.  Transconductance amplifier  280  has a bandwidth that is substantially narrower than a bandwidth of the input differential signal V i+ /V i . The seven amplifier stages  210 - 270  provide a high gain to the differential input signal V i+ /V i . However, there might be an offset at the input of the limiting amplifier  200  that is also amplified by the high gain, resulting in an unwanted component in the differential outputs signal V o+ /V o . 
         [0016]    Transconductance amplifier  280  indirectly receives the differential outputs signal V o+ /V o  via the first resistor pair  291 - 292 . The purpose of the first resistor pair  291 - 292  is to provide isolation between an output of the last amplifier stage  270  and the input of the transconductance amplifier  280  so that the transconductance amplifier  280  does not present a heavy load to the last amplifier stage  270 , lest it may slow down the last amplifier stage  270 . A resistance of the first resistor pair  291 - 292  must be substantially higher than an output impedance of the last amplifier stage  270  to fulfill the purpose of isolation. Since the bandwidth of transconductance amplifier  280  is substantially narrower than the bandwidth of the input differential signal V i+ /V i , transconductance amplifier  280  is effectively extracting a low frequency component of the differential output signal V o+ /V o  that is unwanted and primarily originates from an offset at the input of the limiting amplifier  200 . Transconductance amplifier  280  converts the low frequency component into current signal I o+ /I o  that is injected to circuit nodes  211  and  212  via the second resistor pair  293 - 294 , resulting in a negative feedback for the unwanted low frequency component. As a result, the unwanted low frequency component is effectively suppressed by a negative feedback loop comprising amplifier stages  220 - 270 , the first resistor pair  291 - 292 , the transconductance amplifier  280 , and the second resistor pair  293 - 294 . The purpose of the second resistor pair  293 - 294  is to a provide isolation between an output of the transconductance amplifier  280  and the circuit nodes  211  and  212  to prevent slow down of the first amplifier stage  210  due to the transconductance amplifier  280 . To provide sufficient isolation, a resistance of the second resistor pair  293 - 294  needs to be sufficiently large; this may lead to a large voltage drop across the second resistor pair  293 - 294 . The second power supply node V DD2  has a higher potential than the first power supply node V DD1  so as to ensure sufficient headroom for the current signal I o+ /I o  in spite of the large voltage drop across the second resistor pair  293 - 294  due to a large value of the second resistor pair  293 - 294 . 
         [0017]    An amplifier  300  suitable for embodying any one of the seven amplifier stages  210 - 270  of  FIG. 2  is depicted in  FIG. 3 . Amplifier  300  receives a differential input (comprising a “+” and a “ ” end) and outputs a differential output (comprising a “+” and a “ ” end). Amplifier  300  includes a differential pair having two NMOS (n-type metal-oxide semiconductor field effect transistors)  311  and  312  biased by a biasing current I b  from a current source embodied by a NMOS  310  receiving a biasing voltage VB at a gate terminal; and a resistor pair  321 - 322  serving as a load to the differential pair and also a path for receiving the power from the first power supply node V DD1.  Amplifier  300  is a typical amplifier well known in prior art and thus no detailed description on how it works is given here. 
         [0018]    A transconductance amplifier  400  suitable for embodying the transconductance amplifier  280  of  FIG. 2  is depicted in  FIG. 4 . Transconductance amplifier  400  includes two halves of identical circuits  401  and  402 . Half circuit  401  receives V f+ , generates an intermediate voltage V r+ , and outputs I o+ ; half circuit  402  receives V f  , generates an intermediate voltage V r  , and outputs I o . Half circuit  401  comprises a voltage follower comprising an operational amplifier  421  and a source follower comprising NMOS  431 , configured in a negative feedback configuration. The operational amplifier  421  has sufficiently large gain and therefore intermediate voltage V r+  will effectively follow V f+ , due to the negative feedback that forces the “ ” terminal voltage to track the “+” terminal voltage of the operational amplifier  421 . A capacitor  461  is used to provide frequency compensation for the voltage follower to ensure stability of the feedback loop. Capacitor  461  also fulfills low-pass filtering function that limits the bandwidth of the voltage follower. Half circuit  401  further includes a current source embodied by NMOS  411  biased by a biasing voltage VB′ for providing a constant current I′ b  to the circuit node of V r+ ; and a current mirror, having PMOS (p-type metal-oxide semiconductor field effect transistor)  441  configured in a diode-connected configuration and PMOS  451  configured in a common source configuration, for receiving an intermediate current I i+  from a drain terminal of NMOS  431  and mirroring I i+  into the output current  1   O+ . Half circuit  402  is identical to half circuit  401  and thus is not described in detail here. Half circuit  401  is coupled to half circuit  402  via a degeneration resistor  470  inserted between the two circuit nodes for V r+  and V r . For a low frequency signal of interest, V r+  effectively follows V f+  and V r  effectively follows V f  , resulting in a current I r  flowing between V r+  and V r  via the degeneration resistor  470 , where 
         [0000]      I r =(V r+  V r )/R≈(V f+  V fr )/R
 
         [0019]    Here, R denotes a resistance of the degeneration resistor  470 . 
         [0020]    Let the W/L (width to length) ratio of PMOS  451  be n times higher than that of PMOS  441 . Then the current mirror formed by PMOS  441  and  451  provides a current gain of n. Then I o+  can be approximated by the following equation: 
         [0000]      i I o+   =n·I   i+   ≈n·[I′   b +( V   f+    V   f )/ R]   
         [0021]    Likewise, I o  can be approximated by the following equation: 
         [0000]        I   o   =n+I   i   ≈n·[I′   b  ( V   f+    V   f )/ R]   
         [0022]    The differential output current is 
         [0000]        I   o+   I   o ≈2 n ·( V   f+    V   f )/ R  
 
         [0023]    The transconductance provided by the transconductance amplifier  400  is thus 
         [0000]        g   m ≡( I   o+    I   o )/( V   f+    V   f )=2 n/R  
 
         [0024]    The transconductance of transconductance amplifier  400 , therefore, can be adjusted by changing a value for resistor  470  or change W/L ratio for PMOS  441  (along with PMOS  442 , which is preferably identical to PMOS  441 ) or PMOS  451  (along with PMOS  452 , which is identical to PMOS  451 ). The bandwidth of transconductance amplifier  400  can be adjusted by changing a value for capacitor  461  (and also capacitor  462 , which is preferably identical to capacitor  461 ). 
         [0025]    Embodiments of operational amplifiers are well known to those of ordinary skill in the art and thus not described in detail here. 
         [0026]    Now refer back to  FIG. 2 . In embodiment  200  of  FIG. 2 , all seven amplifier stages  210 - 270  receives power from the first power supply node V DD1 . However, that is by way of example but not restriction. At the discretion of circuit designers, different number of stages may be used, and also different supply voltages may be used. The reason why transconductance amplifier  280  receives power from the second power supply node V DD2  that has a higher potential than that of V DD1  is to allow more headroom for the current signal I O+ /I O− . For that purpose, transconductance amplifier  280  needs to have a supply voltage higher than that of the first amplifier stage  210 , but not necessarily higher than that of any of the rest of the amplifier stages  220 - 270 . Furthermore, if the headroom for the current signal I O+ /I O−  is sufficient even if the transconductance amplifier  280  uses the same power supply as that of the first amplifier stage  210 , then one may even choose to use the same power supply voltage for both the transconductance amplifier  280  and the first amplifier stage. 
         [0027]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations and variations of the embodiments discussed herein. Various embodiments use permutations and/or combinations of embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description.