Abstract:
The present invention relates to a method for fabricating a capacitor in a semiconductor device; and, more particularly, to a method for fabricating a capacitor capable of stably forming a nitride layer on a lower electrode and obtaining improvements on stable capacitance and leakage current characteristics. The inventive method for fabricating a capacitor includes the steps of: forming a lower electrode on a substrate; forming a nitride-based first dielectric thin layer on the lower electrode; forming a second dielectric thin layer by depositing an Al 2 O 3  layer on the nitride-based first dielectric thin layer; forming a third dielectric thin layer on the second dielectric thin layer; and forming an upper electrode on the third dielectric thin layer.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method for fabricating an integrated circuit in a semiconductor device; and, more particularly, to a method for fabricating a capacitor in a semiconductor device.  
         DESCRIPTION OF RELATED ARTS  
         [0002]    As a degree of integration of a memory device, particularly, a dynamic random access memory (DRAM), increases progressively, a memory cell area that is a basic unit for storing information significantly decreases.  
           [0003]    The decrease in the memory cell area brings another reduction of an area for cell capacitance, thereby decreasing a sensing margin and a sensing speed. Moreover, there results in another problem of decreased durability for soft error that occurs due to α-particles. Therefore, it is necessary to develop a method for obtaining sufficient capacitance within a limited cell area.  
           [0004]    The capacitance of a capacitor is defined by the following mathematic equation.  
             C=ε·AS/d    Eq. 1  
           [0005]    Herein, ε, As and d denote a dielectric constant, an effective surface area of an electrode and a distance between the electrodes, respectively.  
           [0006]    Hence, there has been developed several approaches to increase the capacitance of the capacitor by increasing the surface area of the electrode, decreasing a thickness of a dielectric thin layer and increasing the dielectric constant.  
           [0007]    Among these approaches, it is firstly considered an approach of increasing the surface area of the electrode. Capacitors in various forms of a three-dimensional structure such as a concave, a cylinder, a multi-layered fin and so on are aimed to increase the effective surface area of the electrode within the limited area. However, as a degree of integration of a semiconductor device becomes extensively high, this approach confronts another limitation in that the effective surface area of the electrode cannot be increased sufficiently.  
           [0008]    Also, another approach of decreasing the thickness of the dielectric material to minimize the distance (d) between the electrodes is limited as well since leakage currents increase as the thickness of the dielectric thin layer gets decreased.  
           [0009]    Therefore, it is a recent trend in increasing mainly the dielectric constant of the dielectric thin layer, and thus, obtaining the sufficient capacitance of the capacitor. A traditionally fabricated capacitor uses a silicon oxide layer or a silicon nitride layer as a source for the dielectric thin layer. However, it is more increasingly used in today a capacitor with a metal-insulator-poly si (hereinafter referred as to MIS) structure wherein it uses a high-k dielectric material, e.g., Ta 2 O 5  as a dielectric thin layer.  
           [0010]    [0010]FIG. 1 is a cross-sectional view illustrating a typical method for fabricating a capacitor having a cylinder structure in a semiconductor device.  
           [0011]    Referring to FIG. 1, an inter-layer insulation layer  12  is formed on a substrate  10  previously constructed with an activation area  11 , and then, a contact hole that passes through the inter-layer insulation layer  12  and is contacted to the activation area  11  of the substrate  10  is formed. Subsequently, the contact hole is filled with a conductive material, forming a contact plug  13 . On top of the contact plug  13 , a capacitor insulation layer is formed as with the size for forming a capacitor.  
           [0012]    Next, the capacitor insulation layer is selectively etched to expose the contact plug  13  and form a capacitor hole.  
           [0013]    A polysilicon lower electrode  14  is formed inside the capacitor hole, and the capacitor insulation layer is then removed. After forming the polysilicon lower electrode  14 , a nitride layer  15  is formed by nitridating a surface of the polysilicon lower electrode  14  through the use of Si 3 N 4  plasma gas or a rapid thermal process.  
           [0014]    A Ta 2 O 5  layer is formed on the nitride layer  15  as a dielectric thin layer  16 , and an upper electrode  17  is overlaid subsequently.  
           [0015]    Herein, the surface of polysilicon lower electrode  14  is nitridated with use of the Si 3 N 4  plasma gas before forming the Ta 2 O 5  layer for forming the dielectric thin layer  16 . This prior nitridation is to prevent oxygen from penetrating into the polysilicon lower electrode  14  and oxidizing it while carrying out a thermal process in an atmosphere of oxygen in order to improve a dielectric constant.  
           [0016]    As a high degree of integration is progressively embodied in a semiconductor device, and particularly, as a capacitor has a three-dimensional structure in a concave form or a cylinder form, it is difficult to nitride the surface of the polysilicon lower electrode  14  with a constant thickness. That is, a typical plasma process or a rapid thermal process does not allow the nitride layer to be formed stably on the polysilicon lower electrode  14 .  
           [0017]    If the nitride layer is not formed properly, oxygen gets penetrated into the bottom structure of the capacitor, e.g., polysilicon lower electrode, and oxidizes the bottom structure. This problem eventually reduces a confidence level in the capacitor fabrication.  
         SUMMARY OF THE INVENTION  
         [0018]    It is, therefore, an object of the present invention to provide a method for fabricating a capacitor, wherein a nitride layer is stably formed on a lower electrode and sufficient capacitance and improved leakage current characteristics are obtained.  
           [0019]    In accordance with an aspect of the present invention, there is provided A method for fabricating a capacitor in a semiconductor device, including the steps of: forming a lower electrode on a substrate; forming a nitride-based first dielectric thin layer on the lower electrode; forming a second dielectric thin layer by depositing an Al 2 O 3  layer on the nitride-based first dielectric thin layer; forming a third dielectric thin layer on the second dielectric thin layer; and forming an upper electrode on the third dielectric thin layer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING(S)  
       [0020]    The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0021]    [0021]FIG. 1 is a cross-sectional view showing a typical method for fabricating a capacitor in a semiconductor device in accordance with the prior art; and  
         [0022]    [0022]FIG. 2 is a cross-sectional view showing a method for fabricating a capacitor in a semiconductor device in accordance with a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]    [0023]FIG. 2 is a cross-sectional view showing a method for fabricating a capacitor in a semiconductor device in accordance with a preferred embodiment of the present invention.  
         [0024]    With reference to FIG. 2, an inter-layer insulation layer  23  is formed on a substrate  20  previously constructed with an activation area  21 , and then, a contact hole that passes through the inter-layer insulation layer  23  and is contacted to the activation area  21  of the substrate  20  is formed. The contact hole is subsequently filled with a conductive material to form a contact plug  22 . A capacitor insulation layer is formed on top of the contact plug  22  as high as to form a capacitor. Herein, the capacitor insulation layer can use oxide layers such as undoped-silicate glass, phospho-silicate glass, boro-phospho silicate glass and so forth.  
         [0025]    Next, the capacitor insulation layer is selectively etched to expose the contact plug  22  and form a capacitor hole.  
         [0026]    Inside of the capacitor hole, a polysilicon layer for forming a lower electrode  24  is deposited till having a thickness in a range from about 100 Å to about 500 Å, and a native oxide layer formed on the polysilicon layer is removed by cleaning a surface of the polysilicon layer with use of HF or a buffer oxide etchant (hereinafter referred as to BOE). At this time, it is possible to use NH 4 OH, H 2 O 2  and H 2 O 2  (SC-1) with a ratio of NH 4 OH:H 2 O 2 :H 2 O 2  is 1:4:20.  
         [0027]    It is also alternatively possible to form the lower electrode  24  by doping PH 3  in an atmosphere of N 2  at a temperature ranging from about 500° C. to about 700° C. after depositing a doped polysilicon layer in a thickness ranging from about 50 Å to about 300 Å and a undoped polysilicon layer in a thickness ranging from about 50 Å to about 300Å. Subsequently, the capacitor insulation layer is removed.  
         [0028]    An enhanced furnace nitride (hereinafter referred as to EFN) process is performed to form a first nitride layer  25  in a form of Si 3 N 4  on the polysilicon lower electrode  24 . Immediately after the EFN process, a thermal process is performed in an atmosphere of NH 3  gas under an in-situ environment wherein a temperature and a pressure are maintained within a range from about 500° C. to about 800° C. and a range from about 1 Torr to 30 Torr, respectively. Then, the NH 3  gas is used again to deposit a second nitride layer  26  at the above mentioned temperature. The first and the second nitride layers  25  and  26  become a first dielectric thin layer with a deposited thickness in a range from about 5 Å to about 50 Å. Herein, the EFN process is a process that nitrides a surface of a lower electrode in a form of Si 3 N 4  through a thermal process at a furnace and subsequently applies NH 3  gas at the identical temperature as applied for the former thermal process under an in-situ environment to form double nitride layers eventually.  
         [0029]    In a previous technology in 0.1 μm gate line-width, a rapid thermal process (hereinafter referred as to RTP) or a plasma process is generally employed to form a nitride layer for preventing oxygen from penetrating into a lower electrode and other bottom structures of the semiconductor device. At this time, a thickness of an oxide layer (hereinafter referred as to T ox ) for obtaining a predetermined capacitance should be greater than about 40.8 Å. On the other hand, in case of applying the EFN process for forming the nitride layer, it is possible to obtain a specifically desired size of capacitance as long as the T ox  is greater than about 34 Å.  
         [0030]    Also, if a N 2 O plasma process is carried out again after the EFN process, it is also possible to obtain a specifically desired size of capacitance although the T ox  is greater than about 30 Å. However, a leakage current characteristic is often more negatively pronounced than before after applying the N 2 O plasma process. That is, the nitride layer is formed on the lower electrode, and then, the Ta 2 O 5  layer is deposited thereon as a dielectric thin layer. The N 2 O plasma process is subsequently proceeded after the deposition, and this application of the N 2 O plasma process provides a specifically desired size of capacitance even if a thickness of the dielectric thin layer is reduced compared to the application of other processes, e.g., approximately 30 Å in the technology of 0.1 μm gate line-width.  
         [0031]    Despite of this provided advantage, the application of N 2 O plasma process aggravates the leakage current characteristic of the capacitance. Therefore, the present invention employs a method for depositing triple dielectric thin layers by depositing an Al 2 O 3  layer instead of applying the N 2 O plasma process.  
         [0032]    Next, the Al 2 O 3  layer of which leakage current characteristic is good is deposited as a second dielectric thin layer  27  on the first dielectric thin layer including the first and the second nitride layers  25  and  26  till having a thickness ranging from about 20 Å to about 100 Å by using an atomic layer deposition (hereinafter referred as to ALD) process.  
         [0033]    In more details with respect to the Al 2 O 3  layer deposition for forming the second dielectric thin layer  27 , a temperature of a wafer is set to be in a range from about 200° C. to about 500° C. and a pressure of a reaction chamber is maintained within a range from about 0.1 Torr to about 1 Torr. Also, (CH 3 ) 3 Al gas and NH 3  gas are used as a source gas and a transportation gas, respectively. The (CH 3 ) 3 Al gas is supplied with the NH 3  gas for about 0.1 second to about several seconds, e.g., 10 seconds, so as to be absorbed on the substrate  20 . Then, N 2  gas is flowed thereon for several seconds, e.g. from about 0.1 second to about 10 seconds, so that unreacted (CH 3 ) 3 Al gas are purged.  
         [0034]    Next, H 2 O gas that is a main source for supplying oxygen is flowed to the substrate  20  for about 0.1 second to several seconds, e.g., 10 seconds, and the N 2  gas is successively flowed for several seconds, e.g., from about 0.1 second to about 10 seconds so as to purge the unreacted H 2 O gas.  
         [0035]    The ALD process as described above is repeatedly applied until obtaining a desired thickness and forms the second dielectric thin layer  27 .  
         [0036]    In continuous to the ALD process for forming the second dielectric thin layer  27 , a third dielectric thin layer  28  is formed by depositing a Ta2O5 layer on the second dielectric thin layer  27  with a thickness ranging from about 30 Å to about 100 Å. At this time, a temperature and a pressure are maintained within a range from about 200° C. to about 500° C. and from about 0.1 Torr to about 1.0 Torr, respectively. Ta(C 2 H 5 O) 5  and O 2  are especially used to form the Ta 2 O 5  dielectric layer. Herein, O 2  is used as a reactant gas. Also, the third dielectric thin layer  28  can use high-k dielectric materials such as (Ba,Sr)TiO 3  or ferroelectric materials such as (pb,Zr)TiO 3 , (Pb,La)(Zr,Ti)O 3 , SrBi 2 Ta 2 O 9 , Bi 4−x La x Ti 3 O 12  and so forth.  
         [0037]    After forming the third dielectric thin layer  28 , a thermal process is performed at a furnace maintained with a temperature arranged from about 500° C. to about 800° C. in an atmosphere of N 2 O or O 2 .  
         [0038]    A subsequent chemical vapor deposition (CVD) process is applied to deposit consecutively a TiN layer and a polysilicon layer on the third dielectric thin layer  28  for forming an upper electrode  29 . Then, an activation annealing process is proceeded at a furnace maintained with a temperature ranging from about 500° C. to about 700° C. in an atmosphere of N 2  gas.  
         [0039]    Accordingly, depositing the triple dielectric thin layers of the nitride layer, the Al 2 O 3  layer and the Ta 2 O 5  layer on the polysilicon lower electrode improves a dielectric constant of the capacitance and the leakage current characteristic by omitting the N 2 O plasma process, which aggravates the leakage current characteristic.  
         [0040]    Furthermore, the use of Al 2 O 3  layer as a dielectric thin layer increases clearly the dielectric constant, and thus, pronouncedly decreases the T ox  of the capacitor. As seen from the above, in accordance with the preferred embodiment of the present invention, it is ultimately possible to fabricate a highly integrated capacitor with the high dielectric constant and the enhanced leakage current characteristic.  
         [0041]    While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.