Abstract:
A method and apparatus for performing voltage-mode sample and hold functions while avoiding nonlinear charge injection. The method comprises oversampling an input signal and sampling an error signal, not the input signal directly, and through signal processing causing the error signal to be reduced to low amplitude. First order and higher order voltage-mode sample and hold circuitry embodiments are provided.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/124,680, filed Mar. 16, 1999. 
    
    
     TECHNICAL FIELD 
     This disclosure generally relates to electronic systems and more particularly, to the design of high linearity sample-and hold circuitry. 
     BACKGROUND 
     Some sample and hold (S/H) circuitry utilizes switched capacitors. The opening and closing of switches produces nonlinear charge injection effects. These nonlinear charge injection effects can be a problem in the design of high linearity sample-and hold circuitry. Careful control over impedances seen by the sampling switches are often needed. However, careful control over impedances can be difficult to maintain due to variations in common-mode voltages and other parameters such as over process and temperature extremes. 
     A method and apparatus for performing voltage-mode sample and hold functions with high linearity is desired. 
     SUMMARY 
     This disclosure provides a method and apparatus for performing voltage-mode sample and hold functions while avoiding nonlinear charge injection. The method comprises oversampling an input signal and sampling an error signal, not the input signal directly, and through signal processing causing the error signal to be reduced to low amplitude. First order and higher order voltage-mode sample and hold circuitry embodiments are provided. 
    
    
     DESCRIPTION OF DRAWINGS 
     These and other features and advantages of the invention will become more apparent upon reading the following detailed description and upon reference to the accompanying drawings. 
     FIG. 1 shows a voltage-mode sample and hold circuitry with a single switched capacitor integrator; and 
     FIG. 2 shows a voltage-mode sample and hold circuitry with a higher order switched capacitor filter in a single-ended design style. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows an embodiment of a first order voltage-mode sample and hold circuitry system. Input signal enters the first order voltage-mode sample and hold circuit  100  at node V i . The signal travels through a resistor R 1  and enters the inverting terminal of a operational amplifier (“op amp”)  110 . The output of op amp  110  is sampled by the switched capacitor integrator  120 . The non-inverting input of op amp  110  is connected to ground. 
     The switched capacitor integrator  120  receives an input at node V s . The output V op  of the switched capacitor integrator  120  is feedback by path  130  through the resistors R 2  and R F  into the inverting terminal of the op amp  110 . The signal at node V s  is referred to as the error signal and is given by V s =−(R F /R 1 )*V i −(R F /R 2 )*V op . During operation of circuit  100 , the feedback operation of the circuit works to drive the error signal at node V s  to approximately zero when the input signal is sufficiently oversampled. This results in V op ≈V i  at the sampling instants (i.e., when Φ 1  opens each cycle). 
     The switched capacitor integrator  120  has a switched capacitor  140  and an integrator  150 . One terminal of the switched capacitor C 1  is connected to switches Φ 1 d and Φ 2 d; the other terminal of the switched capacitor C 1  is connected to switches Φ 1  and Φ 2 . In one embodiment, switches Φ 1 d and Φ 1  are operable to close in response to generation of a clock signal Φ 1  and switches Φ 2 d and Φ 2  are operable to close in response to generation of a clock signal Φ 2 . The switched capacitor C 1  samples the signal from Vs when the switches Φ 1 d and Φ 1  are closed, and dumps the charge thereon to a charge summing node V n  after the switches Φ 1 d and Φ 1  are opened and when switches Φ 2 d and Φ 2  are closed. 
     The integrator  150  comprises an op amp  155  and a charge accumulating capacitor C 2 . The capacitor C 2  is connected between the output of the op amp  155  and the inverting input of op amp  155 . The inverting input of the op amp  155  comprises the charge summing node V n . The non-inverting input thereof is connected to ground. The output of the integrator  150  is V op . 
     In another embodiment, a voltage follow amplifier (not shown) with a gain of approximately +1 may be placed at a position  180  in circuit  100 . This voltage follow amplifier may serve as a buffer at the output of the integrator  150 . 
     The circuit  100  comprises a discrete-time op amp modeled with a single pole. The number of poles in a transfer function is equal to the number of independent energy-storing elements, e.g. capacitors, in the network. An independent capacitor is one to which an arbitrary voltage can be assigned independent of all other capacitor voltages. 
     The discrete-time op amp is placed in feedback and the circuit  100  has a transfer function as shown in equation (1):                  V   o       V   i       =             -     R   F            C   1           R   1          C   1                         z     -   1           1   -       (     1   -         R   F          C   1           R   2          C   2           )          z     -   1                     (   1   )                                
     where z −1 =e Ts ; T is the sampling period; s=Jω. Hence, the DC gain, where ω=0, z −1 =1, is −R 2 /R 1 , with a single pole response in the z domain. In other words, if the signal bandwidth is restricted to frequencies much lower than the sampling rate (i.e., highly oversampled), then z≈1 and V o /V i  approaches −R 2 /R 1 ; the circuit  100  is then insensitive to forward gain. 
     The transfer function from V i  to V s  is given by equation (2):                  V   s       V   i       =           -     R   F         R   1                       (     1   -     z     -   1         )         1   -       (     1   -         R   F          C   1           R   2          C   2           )          z     -   1                     (   2   )                                
     At DC, where ω=0, z −1 =1, the transfer function, V s /V i =0. The magnitude of V s  goes to zero as the input frequency approaches DC or is close to DC. 
     This system shares some common features with a delta-sigma(ΔΣ) modulator, except that the present system does not have a quantizer and a continuous-time difference stage before the sampling operation occurs. An attractive property common to both the present system and the ΔΣ structures is that of noise-shaping. Although the system of FIG. 1 does not have quantization noise injected as a conventional ΔΣ modulator does, the principle of noise-shaping can be exploited to reduce the effects of output-referred nonlinearity of the switched capacitor integrator  120 . The nonlinearity can be modeled as an additive “noise” source at the integrator output, even though the noise really has only signal harmonics. As in the case of a ΔΣ modulator, increased oversampling leads to reduced output “noise” and thus higher resolution. 
     In FIG. 1, the sampling operation from the Φ 1  switch can cause nonlinear charge injection. However, this nonlinearity has the property that the harmonic distortion produced by the nonlinearity drops as the amplitude at node V s  drops. If the amplitude of V s  drops by a factor α, the harmonic distortion caused by the nonlinear charge injection will typically drop by a factor larger than α. Thus, if the maximum amplitude of V s  can be held at some low level, then the total system harmonic distortion will be lower than if V s  is allowed to have a higher maximum amplitude. 
     The amplitude of V s  can be limited by oversampling the input signal with the feedback error signal, which in z domain tends to cause the input to get closer and closer to DC, e.g. z≈1, proportional to the system sampling rate. As a result of this error signal feedback, the zero at DC in the V s /V i  transfer function attenuates the input more. This results in a lower and lower maximum amplitude for V s  as the sampling rate is increased with a constant frequency, constant amplitude input signal. High-order harmonics are typically so low in amplitude that they are considered negligible, while low order harmonics are still attenuated by the noise-shaping. 
     Reduction of V s  provides insensitivity to input-referred integrator nonlinearity, a characteristic not shared by conventional ΔΣ modulators. The reason for this difference from a ΔΣ is seen in the characteristic of the integrator input signal. In a conventional ΔΣ modulator, this signal is the difference between the slowly varying analog input and a high speed output pulse train, yielding a high speed, widely varying integrator input. In FIG. 1, however, the integrator input is given by V s , which is seen to have amplitude approaching zero as oversampling increases. This results in a sampled-data virtual ground node. 
     In a preferred embodiment, the closed-loop gain V o /V i  is selected to be approximately 0dB for desired linearity results. 
     The system illustrated in FIG. 1 can easily be extended to a fully differential architecture. FIG. 2 shows another embodiment featuring a higher order switched capacitor filter in place of the single switched capacitor integrator of FIG.  1 . Errors can be reduced further by increasing the order of the structure. This adds more zeros in the error transfer function, which can then be placed at or near DC to obtain higher resolution at the same oversampling ratio. 
     In FIG. 2, the input signal enters the higher order voltage-mode sample and hold circuit  200  at node V i . The signal travels through a resistor R 1  and enters the inverting terminal of the op amp  110 . The output of op amp  110  is sampled by the higher order switched capacitor filter  220 . The higher order switched capacitor filter  220  may include multiple stages of switch capacitor integrators. 
     The higher order switched capacitor filter  220  receives an input at node V s . The output V op  of the higher order switched capacitor filter  220  is feedback by path  130  through the resistors R 2  and R F  into the inverting terminal of the op amp  110 . The signal of node V s  is referred to as the error signal. Node V s  has two inputs, namely, the input signal V i  and the output signal V op . During operation of circuit  200 , the error signal is sampled allowing it to be reduced to low amplitude which improves the linearity of the system. 
     In general, the switched capacitor filter selected has a high gain in the spectral region where the input signal is expected to reside. In the previous embodiment, as shown in FIG. 1, a single integrator is used. This integrator has high gain for frequencies near DC and thus is useful for performing sample and hold functions of signals in the DC region. FIG. 2 illustrates a higher order system using a switched capacitor filter which may have high gain in some bandpass spectral region. This filter can be used in a sample and hold system for signals limited to those frequencies in the passband of the bandpass filter. 
     Higher order structures using multiple stages can provide higher performance at lower oversampling ratios. Such systems have zeros in the transfer functions from V i  to each internal node in the sample and hold switched capacitor filter where sampling occurs, so that the amplitude of each of these node voltages is forced low in the spectral band of interest. This causes the use of a higher order switched capacitor filter to yield even higher linearity (e.g., lower system harmonic distortion) for a lower oversampling ratio. 
     Although only a few embodiments have been described in detail above, those having ordinary skill in the art will certainly understand that many modifications are possible in the preferred embodiment without departing from the teachings thereof.