Abstract:
A flat memory cell read only memory is disclosed. A flat cell ROM array is formed on a substrate. This array is formed by a plurality of sub-arrays. In each sub-array, a plurality of first buried diffusion regions are planted into the substrate. A insulating layer covers on the substrate. A plurality of wordlines and metal bitlines are formed on the insulating layer. The wordlines are vertically buried to the diffusion region. A flat FET array is installed in a section between the lower sides of two adjacent buried diffusion regions and word lines. Four block selecting lines are used to control the selection of the memory cell selecting transistors for reading a selecting memory cell. Commonly used metal bitlines and transistors of a minimum number are used to read data. Therefore, it has the advantages of rapidly reading, small size, high density and lower power consumption.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a read only memory, and especially to flat memory cell read only memory for reading data quickly. 
     BACKGROUND OF THE INVENTION 
     Currently, in designing integrated circuit (IC), speed, size, power, cost and manufacturing process are main considerations. Most of IC designs require to reduce power supply and size, and have a preferred speed. In prior art, there are several read only memories for reading memory cell data are developed. One is a flat memory cell read only memory. 
     In a flat memory cell field effect transistor, at first, since the width of the polysilicon wordline determines the channel width of the field effect transistor instead of the length of the channel so that a polysilicon wordline is formed by the concept of the extremity of the manufacturing process. Furthermore, since the central section of the ROM has no field oxide layer formed by heating growth, and thus there is no defect of the channel reduction due to bird&#39;s beak effect. Therefore, flat memory cell read only memory has a dense memory cell array. Other than the size of the memory cells, the size of the ROM array is affected by the circuit of the ROM memory cells and the peripheral circuits. 
     Therefore, for ROM, an optimum method is to confine the number of transistors for reading the ROM and properly using the surface area of a semiconductor, thereby providing small size and easy manufacturing semiconductor elements. Comparing with other designing ways, the use of flat memory cause that each ROM has a very small area. 
     The prior art flat memory cell read only memory, such as U. S. Pat. No. 5, 117,389, “Flat Memory Cell Read Only Memory Integrated Circuit”, in that selecting transistors of block selecting word lines BWL N , selecting transistors of polysilicon wordlins SWL N , selecting transistors of left side selecting lines SBL N , and selecting transistors of right side selecting lines SBR N  are required to read data of ROM memory cells. In the design, at least four transistors are required to read data of the ROM memory cells. Therefore, the operation time is long and speed is low. There are many transistors required for reading data of the memory cells. This will affect the size of the memory array, while other generated peripheral circuits will also affect the size of the whole array. These are defects of the U. S. patent. 
     SUMMARY OF THE INVENTION 
     Accordingly, the primary object of the present invention is to provide a flat memory cell read only memory, wherein commonly used metal bitlines and transistors of a minimum number are used to read data. Therefore, it has the advantages of rapidly reading, small size, high density and lower power consumption. 
     Another object of the present invention is to provide a flat memory cell read only memory, wherein straight metal lines are used to read data of metal bitlines so as to have a high density layout and has a dense memory cell array. 
     To achieve the object, the flat memory cell read only memory of the present invention includes a plurality of sub-arrays. Each sub-array utilizes a plurality of diffusion area, insulating layers, memory cell selecting transistors, for a plurality of metal bitlines, polysilicon word lines, memory cells, and four block selecting lines for reading data on the memory cell. 
     The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the circuit layout of the ROM array of the present invention. 
     FIG. 2 is a circuit schematic view of the ROM array of the present invention. 
     FIG. 3 is a circuit schematic view of the memory cells C 10  of the present invention. 
     FIG. 4 is a circuit schematic view of the memory cells C 11  of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In order that those skilled in the art can further understand the present invention, a description will be described in the following in details. However, these descriptions and the appended drawings are only used to cause those skilled in the art to understand the objects, features, and characteristics of the present invention, but not to be used to confine the scope and spirit of the present invention defined in the appended claims. In the present invention, a first buried diffusion region  10  is used to achieve a high density ROM array. Referring to FIG. 1, in the present invention, a flat cell ROM array is formed on a substrate. This array is formed by a plurality of sub-arrays. In each sub-array, a plurality of first buried diffusion regions  10  are planted into the substrate. Part of the buried diffusion bitline in the substrate is formed with even diffusion lines  12  and odd diffusion lines  14 . The substrate is formed with an insulating layer (not shown) of thin oxide. Then, a plurality of polysilicon word lines  18  and a plurality of metal bitlines  16  are installed on the insulating layer so as to be formed with a field effect transistor. The polysilicon wordline  18  cuts off the first buried diffusion region  10 . A plurality of memory cells are arranged at two adjacent first buried diffusion regions  10  and below the polysilicon word lines  18 . 
     Further, a plurality of second buried diffusion regions  22  are formed on the substrate so that the second buried diffusion regions  22  are spaced with respect to the odd diffusion lines  14 . The second buried diffusion regions  22  are connected to the metal bitlines  16  through contact windows  24 . A first memory cell selecting line pair is formed on the insulating layer, which includes first block selecting lines  26  and second block selecting lines  28 . The two cut off the even diffusion line  12  and second buried diffusion region  22  so that between two adjacent even diffusion lines  12  and adjacent second buried diffusion regions  22  and the region below the first block selecting line  26  and second block selecting line  28  are formed with memory cell selecting transistors  30  and  32  so that the gates of the memory cell selecting transistors  30  and  32  are alternatively coupled to the first block selecting line  26  and second block selecting line  28 . On the substrate at positions with respect to the second buried diffusion region  22  are installed with a plurality of third buried diffusion regions  34 . The third buried diffusion regions  34  are spaced to be correspondent to the even diffusion lines  12 . The third buried diffusion regions  34  are connected to the metal bitlines  16  through the contact windows  36 . A second memory cell selecting line pair is installed on the insulating layer, which includes third block selecting lines  38  and fourth block selecting lines  40 . The two cut off the odd diffusion lines  14  and third buried diffusion regions  34  so that between two adjacent odd diffusion lines  14  and adjacent third buried diffusion regions  34  and the region below the third block selecting line  38  and fourth block selecting line  40  are formed with memory cell selecting transistors  42  and  44  so that the gates of the memory cell selecting transistors  42  and  44  are alternatively coupled to the third block selecting line  38  and fourth block selecting line  40 . 
     FIG. 2 is a schematic view of the circuit of the ROM array of FIG.  1 . As shown in the figures, this ROM array includes a plurality of sub-array block (i−1, i, i+1) where i represents the number of the sub-array in a ROM array circuit. i th  block of the ROM array includes a plurality of memory cell selecting transistors. A block selecting line (BS) for selecting a proper transistor for reading, such as a first block selecting line (BS 1   i ) for reading memory cell selecting transistors A 1 , A 2 , and A 3 ; a second block selecting line (BS 2   i ) for reading memory cell selecting transistors B 1 , B 2 , and B 3 ; a third block selecting line BS 3   i ) for reading memory cell selecting transistors D 1 , D 2 , and D 3 ; a fourth block selecting line (BS 3   i ) for reading memory cell selecting transistors E 1 , E 2 , and E 3  are used. The drain of each memory cell selecting transistor is electrically connected to a metal—diffusion contact window. For example, the memory cell selecting transistors A 1  , A 2 , A 3  are connected to the metal bitlines BL 0 , BL 2 , BL 4 . The source of each memory cell selecting transistor is connected to the buried diffusion bitlines (BN). For example, each source is connected to the buried diffusion bitline (BN). For example, the sources of the memory cell selecting transistors A 1 , A 2  and A 3  are connected to the buried diffusion bit lines BN 00 , BN 20 , BN 40 . Odd buried diffusion bitlines (BN 01 , BN 11 , BN 21 , BN 31  . . . ) are electrically coupled to the memory cell selecting transistors D 1 , E 1 , D 2 , E 2 , D 3 , E 3  . . . The sub-array includes a plurality of buried diffusion bitlines BN 00 , BN 01 , BN 10 , BN 11 , BN 20 , BN 21 , . . . which are connected to the memory cell selecting transistors and are installed with a plurality of polysilicon word lines WLO˜WLn vertical to the buried diffusion bitlines for defining ROM array so that the buried diffusion bitlines as sources of the first ROM memory cells C 00 , C 01 , C 02 , C 03  . . . and drains of second ROM memory cells C 10 , C 11 , C 12 , C 13  . . . Each of memory cell selecting transistors A 1 , A 2 , and A 3  are connected to the second block selecting lines BS 1   i−1 , BS 1   i , BS 1   i−1  of the metal—diffusion contact windows. The others are structured similarly. 
     The even buried diffusion bitlines BN 00 , BN 10 , BN 20 , BN 30 , . . . are connected to the whole metal datalines by the metal—diffusion contact window through the memory cell selecting transistors A 1 , B 1 , A 2 , B 2  . . . The odd buried diffusion bitlines BN 01 , BN 11 , BN 21 , BN 31 , are connected to the whole metal datalines by the metal—diffusion contact window through the memory cell selecting transistors C 1 , D 1 , C 2 , D 2  . . . The middle—positioned C 00 , C 01 , . . . , C 10 , C 11 , . . . ˜Cn 0  . . . and other regions are used as gates/channel regions of flat memory cell transistors for storing data, thereby, forming the storage units of the ROM memory cells. 
     The operation of the flat memory cell ROM of the present invention will be described hereinbelow. Referring to FIG. 2, the ROM is used in data reading. One of the BS 1  and BS 2  is matched to one of the BS 3  and BS 4 . One of the memory cell signals of the two memories between two adjacent bitlines is selected. With reference to FIG. 3, a schematic view for reading a memory cell C 10  is illustrated. At first, the selected bitlines at two sides of the memory cell C 10  are connected to a ground (GND) and SA, i.e., BL 0  is grounded, and BL 1  is connected to SA. Besides, the same high voltage is applied to the BS 1 , BS 3  and WL 1  for opening related transistors A 1  and D 1  and memory cell C 10 . The BS 2  and BS 4  and word lines unselected are set with a low signal, thereby, the current from SA flowing through the memory cell selecting transistor D 1 , memory cell C 10  and memory cell selecting transistor A 1  to the ground end GND so as to achieve the object of reading data in memory cell C 10 . 
     When reading data in memory cell C 11 , referring to FIG. 4, the bitlines at two sides of the memory cell C 10  are connected to GND and SA, namely, BL 1  is grounded and BL 1  is connected to SA. Then, the same high voltage is applied to BS 2 , BS 3  and WL 1  for opening related transistors B 1 , D 1  and C 11 . The other unselected BS 1 , BS 4  and word lines are set with a low signal. Thereby the object of reading data in the memory cell C 11  is achieved. The reading way and principle of other memory cells are identical to above two embodiments, and thus the details will not be described herein. 
     Since in the present invention, the insulating layer is utilized so that the metal lines of the whole ROM may be formed with a straight line without needing to consider other factors. The whole metal bitlines BL and polysilicon word lines WL are deposited on the substrate with a straight line shape. Each metal bitline are commonly used by two adjacent buried diffusion bitlines. Therefore, a high density is achieved and the memory cell array is very dense. Furthermore, in the present invention, only three transistors are used in reading data, therefore, the reading speed, size and power consumption of ROM can achieve an optimum effect. 
     Although the present invention has been described with reference to the preferred embodiments, it will be understood that the invention is not limited to the details described thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.