Abstract:
A method of forming a bond pad structure is provided. The method includes forming a first conductive layer over a substrate and depositing a first dielectric layer over the first conductive layer. The first dielectric layer is patterned to form a contiguous planar path substantially parallel to a top surface of the substrate. Patterning the first dielectric layer includes defining a dielectric region of the first dielectric layer surrounded by a portion of the contiguous planar path, and forming a first via hole in the dielectric region. The contiguous planar path and the via hole are filled with a conductive material. The conductive material in the contiguous planar path forms a second conductive layer, and the contiguous planar path extends from a first lateral side wall of the second conductive layer to a second lateral sidewall of the second conductive layer. A bond pad is formed over the second conductive layer, and the bond pad is electrically connected to the second conductive layer.

Description:
CROSS REFERENCE 
       [0001]    This application is a Divisional application of Ser. No. 13/463,433, filed May 3, 2012, which in turn is a Divisional application of Ser. No. 12/026,312, filed Feb. 5, 2008, now U.S. Pat. No. 8,178,980, entitled “Bond Pad Structure,” the entire disclosures of both are incorporated herein by reference in their entirety. 
     
    
     BACKGROUND 
       [0002]    This disclosure relates generally to integrated circuits, and more particularly to a bond pad structure. 
         [0003]    Integrated circuits are typically formed on a substrate such as a semiconductor wafer. Bond pads (or bonding pads) are included on the substrate. A bond pad provides an interface to an integrated circuit device through which an electrical connection to the device may be made. Conventional techniques may be used to provide a connection from a package terminal to an integrated circuit using the bond pad such as, thermocompression or thermosonic wire bonding, flip chip techniques, and other techniques known in the art. 
         [0004]    Interconnection techniques can cause mechanical stress to the bond pad structure and surrounding areas, for example, from the placement of a ball or wedge in wire bonding or a bump in flip chip techniques onto the bond pad. Additionally, in an electrical test procedure, a bond pad may be used to provide connection to an underlying integrated circuit device in order to analyze the device. The contact of a test probe during the test procedure can also cause mechanical stress to the bond pad structure. The stress from bonding, electrical test, as well as from other possible stress sources, may cause damage to the bond pad structure as well as the underlying layers. Examples of types of damage that may occur include cracking and delayering. The stress is particularly critical as semiconductor technology progresses because layers underlying the bond pad area, for example, interlayer dielectrics having a low dielectric constant, are becoming more and more fragile. 
         [0005]    As such, an improved bond pad structure is desired. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
           [0007]      FIG. 1  is a sectional view of an embodiment of a bond pad structure. 
           [0008]      FIG. 2  is a corresponding top view of an embodiment of the bond pad structure of  FIG. 1 . 
           [0009]      FIG. 3  is a sectional view of an alternative embodiment of a bond pad structure. 
           [0010]      FIG. 4  is a corresponding top view of an embodiment of the bond pad structure of  FIG. 3 . 
           [0011]      FIG. 5  is a top view of an embodiment of a bond pad structure including a conductive network. 
           [0012]      FIG. 6  is a top view of an embodiment of a bond pad structure including a conductive network and conductive plugs. 
           [0013]      FIG. 7  is a sectional view of an alternative embodiment of a bond pad structure. 
           [0014]      FIG. 8  is a corresponding top view of an embodiment of the bond pad structure of  FIG. 7 . 
           [0015]      FIG. 9  is a flow chart of an embodiment of a method of fabricating a bond pad structure. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Additionally, descriptive terms such as upper/lower, top/bottom, and vertical/horizontal are used for ease of description and do not provide any limitation to an absolute direction. For example, an upper layer and a lower layer may indicate a respective relationship relative to a substrate or integrated circuit formed on a substrate, rather than absolute direction. 
         [0017]    Referring now to  FIG. 1 , illustrated is an embodiment of a bond pad structure (e.g., a bond pad and bond pad connections)  100 . The bond pad structure  100  may be formed on a substrate including an integrated circuit or portion thereof. The substrate typically includes conductive, insulative, and semiconductor layers patterned to form an integrated circuit. The substrate may include an interconnect structure (e.g., multilayer interconnect (MLI) or a plurality of conductive traces and interlayer dielectric) to which the bond pad structure  100  is electrically connected. In an embodiment, the bond pad structure  100  includes a circuit under pad (CUP) structure. In a CUP structure, a bond pad may be disposed over active circuitry of an integrated circuit, or portion thereof. In an embodiment, the bond pad structure  100  is a CUP structure and is disposed over the input/output (I/O) cell of an integrated circuit. Advantages of CUP include shortening the conductors, thus decreasing their resistance and capacitance which may reduce the parasitic capacitance of the integrated circuit, and saving space. 
         [0018]    The bond pad structure  100  includes a lower conductive layer  110 , an intermediate conductive layer  130 , an upper conductive layer  140 , dielectric layers  120  and  125 , passivation layers  150  and  170 , and a bond pad  160 . The lower conductive layer  110  may be electrically connected to and/or be a portion of, an interconnect structure (e.g., an MLI). The intermediate conductive layer  130  is disposed on the lower conductive layer  110  and the upper conductive layer  140  disposed on the intermediate conductive layer  130  such that the intermediate conductive layer  130  interposes the lower conductive layer  110  and the upper conductive layer  140 . The intermediate conductive layer  130  provides an electrical connection between the upper conductive layer  140  and the lower conductive layer  110 . In an embodiment, the lower conductive layer  110 , the intermediate conductive layer  130 , and/or the upper conductive layer  140  include copper. Examples of other materials suitable for use in the conductive layers  110 ,  130 , and/or  140  include aluminum, aluminum/silicon/copper alloy, metal silicide (such as nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, and combinations thereof. 
         [0019]    The upper conductive layer  140 , the lower conductive layer  110 , and/or the intermediate conductive layer  130  are illustrated as continuous structures of conductive material. In particular, the bond pad structure  100  includes the intermediate conductive layer  130  as a solid layer (e.g., pad) of conductive material. In other words, being a solid layer, the conductive density (e.g., the percentage of conductive material as compared to non-conductive material (e.g., dielectric)) of the intermediate conductive layer  130  is approximately 100%. Though the intermediate conductive layer  130  as illustrated includes a continuous, conductive structure, other embodiments are possible. For example, an intermediate layer may include any configuration of contiguous, conductive structure(s). A configuration of contiguous, conductive structure(s) may include a continuous structure, adjacent structures, and/or structures in close contact. 
         [0020]    The upper conductive layer  140  is electrically coupled to the bond pad  160 . In an embodiment, the bond pad  160  includes aluminum or aluminum alloy. Other examples of material suitable for the bond pad  160  include metals, metal alloys, metal silicides, and/or combinations thereof. The bond pad  160  may include one or more layers of conductive material (e.g., barrier layers). In one embodiment, the bonding pad has a horizontal dimension ranging between about 20 microns and about 200 microns for electrical testing (e.g., probe) and bonding. 
         [0021]    The intermediate conductive layer  130  provides an electrical connection between the upper conductive layer  140  and the lower conductive layer  110 . In effect, the intermediate conductive layer  130  provides an electrical connection between the bond pad  160  and an interconnect structure of an integrated circuit or portion thereof formed on the substrate. Conventionally, in place of the intermediate conductive layer  130 , a via array may be used to provide electrical connection to a bond pad. However, use of a via array may allow bonding stress to result in de-layering. The intermediate conductive layer  130  may provide for improved distribution of mechanical stress as compared to the via array. In the illustrated embodiment, the interface of the intermediate conductive layer  130  and the upper conductive layer  140  is 100% conductive material. However, other embodiments are possible including, for example, the bond pad structure  300 , described with reference to  FIG. 3 . 
         [0022]    The bond pad structure  100  also includes the dielectric layers  120  and  125 . In an embodiment, the dielectric layers  120  and  125  are unitary (e.g., a single dielectric layer). Examples of material suitable for the dielectric layers  120  and/or  125  include silicon oxide, a material having a low dielectric constant such as a dielectric constant (k) less than about 2.5 (e.g., extra low k (ELK)), silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), undoped silica glass (USG), carbon doped silicon oxide (SiOC), Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable materials. In an embodiment, the dielectric layer  120  includes ELK. The ELK layer may have a dielectric constant (k) of approximately 2.5. In an embodiment, the dielectric layer  125  includes USG. 
         [0023]    The bond pad structure  100  also includes the passivation layers  150  and  170 . The passivation layers  150  and/or  170  may include silicon oxide, silicon nitride, silicon oxynitride, and/or other suitable materials. The openings in the passivation layers  150  and  170  expose the bond pad  160  providing a bonding area  180 . The bonding area  180  includes the area of the bond pad  160  available for bonding, for example, for placement of a ball, wedge, or bump. 
         [0024]    Referring now to  FIG. 2 , illustrated is a top view of the bond pad structure  100  including a passivation opening  190  and a conductive area  195 . The passivation opening  190  illustrates the opening of passivation layers  150  and  170 , described above with reference to  FIG. 1 . The conductive area  195  illustrates the presence of the lower conductive layer  110 , the intermediate conductive layer  130 , the upper conductive layer  140 , and/or the bond pad  160 . As illustrated by  FIGS. 2 and 3 , in an embodiment, the intermediate conductive layer  130  laterally extends wider than the passivation  170  and  150  openings. 
         [0025]    Referring now to  FIGS. 3 and 4 , illustrated is an embodiment of a bond pad structure  300 . The bond pad structure  300  is similar to the bond pad structure  100 , described above with reference to  FIG. 1 , except as described herein. For example, similar to the bond pad structure  100 , the bond pad structure  300  may include a CUP structure. The bond pad structure  300  however includes an intermediate layer  330  interposed between the lower conductive layer  110  and the upper conductive layer  140 . The intermediate layer  330  provides electrical connection between the lower conductive layer  110  and the upper conductive layer  140 . The intermediate layer  330  includes a conductive network  330   a  and a plurality of spacers  330   b . The conductive network  330   a  includes a contiguous, conductive structure. In an embodiment, the conductive network  330   a  is a continuous, conductive structure. The spacers  330   b  may be of uniform or non-uniform dimensions. 
         [0026]    In an embodiment, the conductive network  330   a  includes copper. Examples of other materials suitable for inclusion in the conductive network  330   a  include aluminum, aluminum/silicon/copper alloy, metal silicide (such as nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, and combinations thereof. The spacers  330   b  include a dielectric material. The spacers  330   b  may include the same dielectric composition as the dielectric layer  125 . In an embodiment, the spacers  330   b  include USG. Examples of other materials suitable for inclusion in the spacers  330   b  include silicon oxide, a material having a low dielectric constant such as a dielectric constant less than about 2.5, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide (SiOC), Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable materials. In an embodiment, one or more conductive plugs may be formed in vias in the spacers  330   b , such as described in reference to  FIG. 6 . 
         [0027]    The conductive network  330   a  may include any configuration of conductive material such that an electrical connection is provided between the upper conductive layer  140  and the lower conductive layer  110 . As such, the conductive network  330   a  provides a conductive path from an upper interface (e.g., with the upper conductive layer  140 ) to a lower interface (e.g., with the lower conductive layer  110 ) (e.g., the layer is vertically continuous). The conductive network  330   a  may be configured as a mesh configuration, a lattice configuration, a grid configuration, and/or a plurality of conductive lines (e.g., stripes). In an embodiment, the intermediate layer  330  includes a contiguous conductive network  330   a . In a further embodiment, conductive network  330   a  is continuous conductive structure such that an uninterrupted path of conductive material may be traced from one sidewall of the intermediate layer  330  to the other sidewall of the intermediate layer  330  (e.g., horizontally continuous). It should be noted that the terms horizontal and vertical are not meant to imply a direction but a relative position with respect to the upper and lower conductive layers  140  and  110 . The intermediate layer  330  includes a conductive density of approximately 20% to 100%. In other words, the percentage of conductive material (e.g., in the conductive network  330   a ) in relation to non-conductive (e.g., in the spacers  330   b ) is between approximately 20% and 100%. In an embodiment, approximately 20% to 100% of the surface area of the interface between the intermediate layer  330  and the upper and/or lower conductive layers  110  and/or  140  includes the conductive network  330   a.    
         [0028]      FIG. 4  illustrates a top view of the bond pad structure  300 . The top view illustrates a passivation opening  390 , a conductive area  395 , and the intermediate conductive layer  330  including the conductive network  330   a  and the spacers  330   b . The passivation opening  390  refers to the opening of passivation layers  150  and  170 . The conductive area  395  refers to the presence of the lower conductive layer  110 , the upper conductive layer  140 , and/or the bond pad  160 . As illustrated by  FIGS. 3 and 4 , in an embodiment, the intermediate conductive layer  330  including the conductive network  330   a  extends beyond the passivation opening  390 . 
         [0029]    Referring now to  FIGS. 5 and 6  illustrated are top views of embodiments of portions of bond pad structures. In particular a bond pad structure  500 , illustrated in  FIG. 5 , and a bond pad structure  600 , illustrated in  FIG. 6 , are illustrative of exemplary embodiments of the intermediate layer  330 . The bond pad structures  500  and  600  illustrate the passivation opening  390  and the conductive area  395 , described above with reference to  FIG. 4 . Also illustrated are the conductive network  330   a  and the spacers  330   b . The bond pad structure  500  includes the conductive network  330   a  which is a continuous, conductive structure including a mesh configuration. The bond pad structure  600  illustrates also the intermediate layer  330  including the conductive network  330   a  having a mesh configuration. In the bond pad structure  600 , a plurality of conductive plugs  610  are formed in vias of the spacers  330   b . The conductive plugs  610  may provide electrical connection between the upper conductive layer  140  and the lower conductive layer  110 . Each of the conductive plugs  610  may be a discrete structure. The bond pad structures  500  and  600  are intended for illustrative purposes only and not intended to be limiting in any manner. Though illustrated as including conductive networks including a mesh structure being a continuous, conductive structure, other embodiments may include any contiguous, conductive structure or structures. For example, in one embodiment, the intermediate layer may include a plurality of structures (e.g., conductive lines such as stripes, or a plurality of matrix configurations) being contiguous, conductive structures such that one or more conductive structures are adjacent. 
         [0030]    Referring now to  FIGS. 7 and 8 , illustrated is an embodiment of a bond pad structure  700 . The bond pad structure  700  is similar to the bond pad structure  100  except as herein described. For example, similar to the bond pad structure  100  of  FIG. 1 , the bond pad structure  700  may include a CUP structure. The bond pad structure  700  includes the lower conductive layer  110 , the intermediate conductive layer  130 , and the upper conductive layer  140  similar to as described above with reference to  FIG. 1 . Though illustrated as including the intermediate conductive layer  130  having a conductive density of 100% (e.g., solid pad), in other embodiments, the bond pad structure  700  includes an intermediate layer such as the intermediate layer  330 , described above with reference to  FIGS. 3 ,  4 ,  5 , and  6 . The intermediate layer may have a conductive density less than 100% and may include any configuration of a contiguous, conductive structure. The bond pad structure  700  includes a bond pad  710 . The bond pad  710  is connected to the upper conductive layer  140  by conductive studs  710   a  in the periphery area of the bond pad  710 . The passivation layer  150  is formed under a portion of the bond pad  710 . 
         [0031]    Referring in particular to  FIG. 8 , illustrated is a top view of the bond pad structure  700  including a conductive area  740 , a first passivation opening  720 , and a second passivation opening  730 . The conductive area  740  illustrates from a top view the presence of the lower conductive layer  110 , the intermediate conductive layer  130 , the upper conductive layer  140 , and/or the bond pad  710 . The first passivation opening  720  illustrates the opening in the passivation layer  150 . The second passivation opening  730  illustrates the passivation layer  170  opening. 
         [0032]    Referring now to  FIG. 9 , illustrated is a flowchart of one embodiment of a method  900  used to form a bond pad structure. The method  900  may form a bond pad structure such as the bond pad structures  100 ,  300 ,  500 ,  600 , and/or  700  described herein. It is understood that additional steps may be provided before, during, and after the method  900 , and some of the steps described below can be replaced or eliminated, for additional embodiments of the method. The method  900  begins at step  910  where an integrated circuit or portion thereof is formed, or partially formed, on a substrate. The substrate may be a semiconductor wafer such as silicon wafer. Alternatively, the substrate may include other elementary semiconductor materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide, an alloy semiconductor material such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide, and/or other substrate compositions known in the art. 
         [0033]    The integrated circuit is formed using, for example, conductive layers, semiconductive layers, and insulative layers disposed on the substrate. In one embodiment, a multilayer interconnect (MLI) structure is formed including conductive lines (vias and contacts) and interlayer dielectric (ILD) layers. The formed bond pad structure, described below with reference to step  945 , provides electrical contact to devices, including the interconnect structure, from outside of the substrate, e.g., from package terminal. The conductive lines of the interconnect structure may include materials such as aluminum, aluminum/silicon/copper alloy, metal silicide, copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide (such as, nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof), and/or other suitable materials. The interconnect structure may be formed by processes including physical vapor deposition (or sputtering), chemical vapor deposition (CVD), plating, and/or other suitable processes. Other manufacturing techniques used to form the interconnect structure may include photolithography processing and etching to pattern the materials for vertical (via and contact) and horizontal connects (conductive line), and may be followed by an etchback or chemical mechanical polish (CMP) process. Still other manufacturing processes such as thermal annealing may be used to form metal silicide on the substrate included in the MLI. 
         [0034]    The ILD layers of the MLI may include materials such as, silicon oxide, a low dielectric constant such as a dielectric constant less than about 2.5, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), USG, fluoride-doped silicate glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable materials. The dielectric layers may be formed by techniques including spin-on, CVD, and/or other suitable processes and may be followed by an etchback or CMP process. The interconnect structure may be formed in an integrated process such as a damascene process or lithography/plasma etching process. 
         [0035]    The method  900  then proceeds to step  915  where a lower conductive layer and dielectric layer are formed. The lower conductive layer and dielectric layer may be formed in a manner substantially similar to the interconnect structure, described above with reference to step  910 . The lower conductive layer may be substantially similar to the lower conductive layer  110  described above with reference to  FIGS. 1-8 . The dielectric layer may be substantially similar to the dielectric layer  120  also described above with reference to  FIGS. 1-8 . In an embodiment, the dielectric layer and the lower conductive layer may be formed simultaneously with a layer of the interconnect structure and/or be a portion of the interconnect structure. 
         [0036]    The method  900  then proceeds to step  920  where a dielectric layer is formed. The dielectric layer may be substantially similar to the dielectric layer  125  described above with reference to  FIGS. 1 ,  3 , and  7 . The dielectric layer may be formed by techniques including spin-on, CVD, or other suitable processes and which may be followed by an etchback or CMP process. 
         [0037]    The method  900  then proceeds to step  925  where the dielectric layer formed in step  920  is patterned. The dielectric layer may be patterned using conventional photolithography techniques. The dielectric layer may be patterned such that an intermediate conductive layer may be formed on the lower conductive layer. The patterning may provide for an intermediate conductive layer to be formed to include a solid conductive layer, such as intermediate conductive layer  130 , or it may include conductive network and spacer areas such as the intermediate conductive layer  330 . In an embodiment, the dielectric layer is patterned to provide vias in the spacer areas. The patterning may be performed using techniques such as photolithography processes including forming photoresist layers, bake processes, exposure processes, development processes; wet or dry etch processes; and/or other suitable processing. 
         [0038]    The method  900  then proceeds to step  930  where an intermediate layer may be formed on the patterned dielectric layer. The intermediate layer includes a contiguous, conductive structure(s). In an embodiment, the intermediate layer includes a continuous, conductive structure. The intermediate conductive layer may be substantially similar to the intermediate conductive layer  130  and/or the intermediate layer  330  described above with reference to  FIGS. 1-8 . Examples of possible configurations of contiguous conductive structures that may be included in the intermediate layer include a solid layer, a matrix configuration(s), a plurality of stripes, and/or other possible configurations. 
         [0039]    In an alternative embodiment of the method  900 , a solid conductive layer is formed overlying the lower conductive layer. The conductive layer may be etched to form a conductive network and thus removing the conductive layer from the associated spacer areas. A dielectric layer may then be deposited onto the conductive layer and in the associated spacer areas. The dielectric layer may then be etched-back and/or processed using CMP such that the dielectric fills the spacer areas. Any combination of the above processes and/or other processes known in the art may be suitable to form the intermediate conductive layer. 
         [0040]    The method  900  then proceeds to step  935  where the upper conductive layer is formed. The upper conductive layer may be substantially similar to the upper conductive layer  140  described above in reference to  FIGS. 1 ,  3 , and  7 . The upper conductive layer may be formed using processes known in the art such as those described above with reference to forming the interconnect structure of step  910 . 
         [0041]    The method  900  then proceeds to step  940  where a passivation layer is formed. The passivation layer may be substantially similar to the passivation layer  150  described above with reference to  FIGS. 1 ,  3 , and  7 . The passivation layer may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The passivation layer may be formed by CVD, plasma enhanced chemical vapor deposition (PECVD), spin-coating, and/or other suitable techniques. The passivation layer is patterned and etched such that a bond pad may be formed in an opening created in the passivation layer. 
         [0042]    The method  900  then proceeds to step  945  where a bond pad is formed. The bond pad may be substantially similar to the bond pad  160  and/or the bond pad  710  described above with reference to  FIGS. 1 ,  3 , and  7 . The bond pad may include a plurality of layers including, for example, barrier layers. The bond pad may be formed using deposition techniques such as, sputtering, CVD, plating, and/or other suitable processes. In an embodiment, the bond pad includes aluminum. Examples of other materials that may be included in the bond pad are titanium, tantalum, copper, tungsten, combinations thereof including alloys, and/or other suitable conductive materials. 
         [0043]    The method  900  then proceeds to step  950  where an additional passivation layer is formed. The passivation layer may be substantially similar to the passivation layer  170  described above with reference to  FIGS. 1 ,  3 , and  7 . The passivation layer may include material compositions and/or be formed in a manner substantially similar to the passivation layer formed in step  940 . 
         [0044]    The method  900  then proceeds to step  955  where the passivation layer formed in step  955  is opened to expose the bond pad and provide for a bonding region. The passivation layer may be patterned to provide an opening using a series of processing steps including photolithography and etching as known in the art. 
         [0045]    The method  900  may continue to an electrical test procedure (e.g., probe test) where contact is made to the exposed bonding pad(s) by the testing probes for various electrical evaluations. The method  900  may also continue to provide for an integrated circuit (e.g., die) to be wired to a chip package using various wire bonding techniques such as thermocompression bonding or thermosonic bonding, resulting in a ball or wedge bond at the formed bond pad. Other bonding techniques may be alternatively utilized (e.g., placement of a bump for flip chip packaging). 
         [0046]    Thus, the present disclosure provides a device including a first conductive layer; a second conductive layer on the first conductive layer; and a bond pad on the second conductive layer. A connective layer interposes the first and second conductive layer. The connective layer includes a contiguous, conductive structure. In an embodiment, the connective layer is entirely conductive material (e.g., a conductive pad or solid layer). In an embodiment, the contiguous conductive structure includes a matrix configuration of conductive material. At least one spacer may interpose the contiguous conductive structure (e.g., the matrix). In an embodiment, the spacer includes dielectric material. In a further embodiment, a plurality of conductive plugs is formed in the spacer. In an embodiment, a continuous conductive structure is provided and one or more spacers may interpose the continuous conductive structure. 
         [0047]    The present disclosure also provides a device including a substrate; a first conductive layer formed on the substrate; and a second conductive layer formed on the first conductive layer. An intermediate layer interposes and electrically couples the first and second conductive layers. The conductive density of the intermediate layer is greater than approximately 20%. The intermediate layer includes a continuous structure of conductive material. In an embodiment, the continuous structure may be a matrix. In an embodiment, the conductive density of the intermediate layer is between 20 and 100%. 
         [0048]    A method of forming a bond pad structure is also provided. The method includes forming a first conductive layer and forming a second conductive layer on the first conductive layer. A connecting layer is formed between the first and second conductive layer and electrically couples the first and second conductive layers. Forming the connecting layer includes forming a contiguous conductive structure. 
         [0049]    The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.