Abstract:
An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.

Description:
BACKGROUND 
     The present invention relates to semiconductor manufacturing, and more specifically, to fabrication of interposers. 
     An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection. 
     In microelectronics, a three-dimensional integrated circuit (3D IC) is an integrated circuit manufactured by stacking silicon wafers and/or dies and interconnecting them vertically using through-silicon vias (TSVs) so that they behave as a single device to achieve performance improvements at a reduced power and smaller footprint than conventional two dimensional processes. 3D IC is just one of a host of 3D integration schemes that exploit the z-direction to achieve electrical performance benefits. They can be classified by their level of interconnect hierarchy at the global (package), intermediate (bond pad) and local (transistor) level. In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs), monolithic 3D ICs; 3D heterogeneous integration; and 3D systems integration. 
     BRIEF SUMMARY 
     An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a cross sectional view of a base layer after the formation of holes through the base layer, according to an example embodiment; 
         FIG. 2  depicts a cross sectional view of placement of a capacitor in the holes in the base layer, according to an example embodiment; 
         FIG. 3  depicts a cross sectional view of formation of a laminate layer and conductive layer, according to an example embodiment; 
         FIG. 4  depicts a cross sectional view of creating a conductive pattern in the conductive layer, according to an example embodiment; 
         FIG. 5  depicts a cross sectional view of formation of via holes through the conductive pattern, base layer, and laminate layer, according to an example embodiment; 
         FIG. 6  depicts a cross sectional view of creating conductive vias in the via holes, according to an example embodiment; 
         FIG. 7  depicts a cross sectional view of joining a interposer to a die, according to an example embodiment; and 
         FIG. 8  depicts a cross sectional view of joining the interposer to a substrate, according to an example embodiment. 
     
    
    
     Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, dimensions of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements. 
     DETAILED DESCRIPTION 
     Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments. 
     For purposes of the description hereinafter, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. The term substantially, or substantially similar, refer to instances in which the difference in length, height, or orientation convey no practical difference between the definite recitation (e.g. the phrase sans the substantially similar term), and the substantially similar variations. In one embodiment, substantial (and its derivatives) denote a difference by a generally accepted engineering or manufacturing tolerance for similar devices, up to, for example, 10% deviation in value or 5° deviation in angle. 
     In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention. 2.5 and 3D technologies are one mechanism of increasing chip performance. In such technologies, the thickness of the die is a contributing factor in performance. Thus, removing unnecessary structures in the die, and specifically the wiring of the die, can lead to a thinner die and increased performance. Structures such as deep trench capacitors, which serve to dampen power fluctuations, may add to unnecessary thickness of the die, and may accomplish the same goals when placed in other places in a microelectronics package. 
     Referring to  FIG. 1 , through holes  105  may be created in the base layer  100 . The base layer  100  may be a dielectric material, an organic material or silicon. Non-limiting examples of the dielectric material include, for example, epoxy, polyphenylether, polyphenyloxide, oxides, nitrides, oxynitrides of silicon, and combinations thereof. Oxides, nitrides and oxynitrides of other elements are also envisioned. The material in the base layer  100  may be selected, or tuned, so the coefficient of thermal expansion (CTE) of the material matches, or is sufficiently similar, to the CTE of a substrate or die that may be subsequently attached. In addition, the base layer  100  may include crystalline or non-crystalline dielectric material. In one embodiment, the base layer  100  may have a thickness, in some embodiments, ranging from about 400 μm to about 800 μm. 
     The through holes  105  may be created using mechanical, chemical or laser techniques. The through holes  105  may be spaced such that they align with the placement of vias in subsequent steps. In an embodiment, the alignment may be between power and ground vias, and for processors may be concentrated in the center of the interposer. In one embodiment, a mechanical punch or drill may be used to create the through hole  105 , starting on one surface of the base layer  100 , and extending to the opposite surface of the base layer  100 . Additional embodiments may use techniques such as laser ablation, or patterning and etching away the unpatterned portions of the base layer  100 . Through holes  105  should be big enough to support the placement of any desired electrical components, such as a capacitor, resistor or inductor. Further, through holes  105  may have a width from about 100 to about 1000 μm. 
     Referring to  FIG. 2 , a capacitor  110  may be placed in the through hole  105 . The capacitor includes a conductive structure  112  located on each side of a dielectric layer  115 . The capacitor  110  may be oriented such that the conductive structure  112  and dielectric layer  115  are parallel, or substantially parallel, to the through hole  105 , and perpendicular to the surface of base layer  100 . The conductive structure  112  may be made of any conductive material such as, for example, copper, aluminum, tungsten, or any other suitable material. The dielectric layer  115  may be made of any suitable dielectric material such as, for example, epoxy, polyphenylether, polyphenyloxide, and oxides, nitrides or oxynitrides of silicon. Further, while capacitor  110  is depicted as having 2 conductive structures  112  separated by a dielectric layer  115 , it should be noted that the depiction is for simplicity, and other capacitor geometries are contemplated. For example, multi-layered capacitors (such as multi-layer ceramic capacitors) and decoupling capacitors may be used. Further, it should be noted that capacitor  110  may instead be a resistor or inductor, depending on system requirements. 
     Referring to  FIG. 3 , a laminate layer  120  may be deposited on both sides of the base layer  100 , and may encase the capacitor  110 . Subsequently, a conductive layer  130  may be formed on the laminate layer  120 . The laminate layer  120  may be made of any suitable organic material such as, for example, an epoxy laminate. The laminate layer  120  may be deposited using any number of techniques such as, for example, spin coating to B-stage adhesive lamination. The conductive layer  130  may be made of any conductive material such as, for example, copper, aluminum, tungsten, or any other suitable material. The conductive layer  130  may be deposited using any number of techniques such as, for example, electroplating. 
     Referring to  FIG. 4 , conductive layer  130  is patterned and etched, forming conductive pattern  133 . The pattern applied, and thus created as conductive pattern  133 , may be as conductive pads or a redistribution layer (RDL), which may aid in subsequent bonding or electrical distribution. In one embodiment, a photolithographic pattern may be applied to the surface of the conductive layer  130 , and an anisotropic process, such as, for example, reactive ion etching (RIE) or plasma etching, may be used to remove the unpatterned material, leaving conductive pattern  133 . In another embodiment, laser ablation may be used to remove unwanted portions of the conductive layer  130 , leaving conductive pattern  133 . 
     Referring to  FIG. 5 , via holes  107  may be formed through the base layer  100 , the laminate layer  120  and the conductive pattern  133 . The via holes may be patterned in such a way that they correspond to electrical connections on a die and substrate that will subsequently be attached. In one embodiment, the via holes  107  may be formed using a photolithography process followed by an anisotropic etching process such as reactive ion etching (RIE) or plasma etching. In another embodiment, the via holes  107  may be formed using laser ablation techniques. 
     Referring to  FIG. 6 , conductive vias  140  may be formed, and an interposer  10  is created. Formation of the conductive vias  140  may be performed using a plating process for filling via holes  107 . The conductive vias  140  may be formed from a metallic material such as, for example, copper, aluminum, tungsten, or any other suitable material. 
     Referring to  FIG. 7 , interposer  10  may be connected to a die  200 , such as, for example, a processor, memory, etc. In one embodiment, the die  200  may be connected to the interposer  10  using electrical connection  210 . Electrical connection  210  may be any material capable of forming an electrical and mechanical connection between the die  200  and interposer  10 . In one example embodiment, electrical connection  210  may be a series of solder bumps that have undergone a reflow process (e.g. melting and fusing), joining the die  200  and interposer  10 . This may be performed by depositing the solder bumps above the conductive via  140 , and using thermal compression to allow for reflow of the solder bumps in order to create an electromechanical connection. In such embodiments, the conductive vias  140  (and thus solder bumps) would be aligned with conductive wiring (not shown) located in the substrate  300 . In an example embodiment, electrical connection  210  may be the only physical connection between the die  200  and interposer  10  (i.e. no underfill is used). This may be accomplished in instances where the CTE for the die  200  and interposer  10  are the same, or sufficiently similar such that the unwanted properties would not arise (e.g. stress causing warpage or fracture from differences in CTE). In such embodiments, removal of die  200  without damage to either the die  200 , or interposer  10  may be accomplished. 
     Referring to  FIG. 8 , interposer  10  may be connected to a substrate  300 , such as a package substrate. The substrate  300  may be an additional die (similar to die  200 ), or a package substrate. This may be performed by depositing the solder bumps above the conductive via  140 , and using thermal compression to allow for reflow of the solder bumps in order to create an electromechanical connection. In such embodiments, the conductive vias  140  (and thus solder bumps) would be aligned with conductive wiring (not shown) located in the substrate  300 . In embodiments where the substrate  300  is a package substrate with a CTE that does not match the interposer  10 , a curable non-conductive polymeric underfill material is dispensed onto the substrate  300  adjacent to the chip and is drawn into the gap by capillary action, forming underfill layer  350 . The underfill material provides environmental protection, and mechanically locks together the interposer  10  and the die  200  so that differences in thermal expansion of the two materials do not break the solder fused connection  330 . The underfill material may comprise one or more polymerizable monomers, polyurethane prepolymers, constituents of block copolymers, and constituents of radial copolymers, initiators, catalysts, cross-linking agents, stabilizers, and the like. Such materials polymeric materials contain molecules that are chained or cross-linked to form a strong bonding material as they are cured and hardened. 
     Following the connection, interposer  10  may allow current to flow between the substrate  300  and die  200 . The interposer  10  may be connected to the front side of the die  200 , or alternatively may be attached to the back side of the die  200  and form electrical connections through TSVs located throughout the die  200 . The introduction of capacitor  110  may allow for dampening of power noise (e.g. fluctuations in voltage or amperage), by attenuating the flow of charge into, or out of, the die  200 . Additionally, by bringing the capacitor  110  closer to the die, loop inductance for the system is reduced, which improves the dampening of the power noise. Further, by matching the CTE of the die  200  and interposer  10 , underfill is not required to secure the joinder, and thus the separation of the die  200  and interposer  10  can be performed with little or no damage to either. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable other of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.