Abstract:
I describe and claim an improved digital-to-analog conversion device and method. The device comprises a current supply circuit to generate a plurality of control currents responsive to a plurality of digital signals. An input voltage generating circuit is adapted to generate a plurality of input voltages responsive to the digital signals and the control currents. And a plurality of operational amplifiers is adapted to output a plurality of analog signals responsive to the input voltages.

Description:
BACKGROUND OF THE INVENTION 
     This application claims priority from Korean Patent Application No. 10-2004-0061955 filed on Aug. 6, 2004, which we incorporate by reference. 
     1. Field of the Invention 
     The field of the invention relates to a digital-to-analog conversion device and, more particularly, to a fixed offset digital-to-analog conversion device and method. 
     2. Description of the Related Art 
     A digital-to-analog conversion (DAC) device converts a digital input signal into an analog signal with a voltage level corresponding to the digital input signal. The converted analog signal may be used in various semiconductor devices performing digital to analog conversion. An example of a conventional DAC is disclosed in U.S. Pat. No. 5,212,482, titled Digital-To-Analog Converter Having An Externally Selectable Output Voltage Range, issued Mar. 18, 1993 to Tetsuo Okuyama. 
       FIG. 1  is a circuit diagram of a conventional DAC  10 . Referring to  FIG. 1 , the DAC  10  includes an input voltage generating circuit  11  and operational amplifiers (OP AMPs)  12  and  13 . The input voltage generating circuit  11  includes a plurality of NMOS transistors NM 1  through NM 9 . The input voltage generating circuit  11  generates input voltages Vin and Vinb on output nodes D 1  and D 2  in response to digital code signals B 0  through B 2  and B 0 B through B 2 B, respectively. The OP AMPs  12  and  13  generate output voltages Vout and Voutb, respectively, in response to the input voltages Vin and Vinb, respectively, and a reference voltage Vref. The OP AMP  12  supplies a current I 1  to the input voltage generating circuit  11  via a resistor R 0 . The OP AMP  13  supplies a current I 2  to the input voltage generating circuit  11  via a resistor R 1 . Resistors R 0  and R 1  may form a feedback loop corresponding to OP AMPs  12  and  13 , respectively. The OP AMPs  12  and  13  have input offset voltages Vos 1  and Vos 2 , respectively, where the input offset voltages Vos 1  and Vos 2  may be determined according to Equation 1. 
     
       
         
           
             
               
                 
                   
                     
                       Vos 
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                       ⁢ 
                       1 
                     
                     = 
                     
                       
                         I 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       
                         G 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       Vos 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                     = 
                     
                       
                         I 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                       
                         G 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                   
                 
               
               
                 
                   Equation 
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                   ⁢ 
                   1 
                 
               
             
           
         
       
     
     As shown in Equation 1, the input offset voltages Vos 1  and Vos 2  are proportional to the currents I 1  and I 2 , respectively, and inversely proportional to the gain G 1  of the OP AMP  12 , and the gain G 2  of the OP AMP  13 . Since the input offset voltages Vos 1  and Vos 2  act as offsets (errors) of the output voltages Vout and Voutb, when the input offset voltages Vos 1  and Vos 2  increase, the offsets of the output voltages Vout and Voutb also increase. 
     The magnitude of the currents I 1  and I 2  supplied by OP AMPs  12  and  13 , respectively, varies according to the digital code signals B 0  through B 2  and B 0 B through B 2 B input to the input voltage generating circuit  11 . Specifically, when the number of NMOS transistors turned on in response to the digital code signals B 0  through B 2  increases, the magnitude of current I 1  increases. Likewise, when the number of NMOS transistors turned on in response to the digital code signals B 0 B through B 2 B increases, the magnitude of current I 2  increases. Since the magnitude of current OP AMPs  12  and  13  can supply to the input voltage generating circuit  11  is limited, the situation may arise when the OP AMPs  12  and  13  cannot sufficiently supply currents I 1  and I 2  to the input voltage generating circuit  11 . Accordingly, the input voltage generating circuit  11  may generate the input voltages Vin and Vinb that do not correspond to the digital code signals B 0  through B 2  and B 0 B through B 2 B, causing the offsets of the output voltages Vout and Voutb to increase. Thus, in conventional DAC  10 , the offsets of the output voltages Vout and Voutb change with changes to the digital code signals B 0  through B 2  and B 0 B through B 2 B. 
     SUMMARY OF THE INVENTION 
     The present invention provides a digital-to-analog conversion device to generate an analog signal with a fixed offset regardless of changes in a digital input signal. The device includes a current supply circuit to generate a plurality of control currents responsive to a plurality of digital signals, an input voltage generating circuit to generate a plurality of input voltages responsive to the digital signals and the control currents, and a plurality of operational amplifiers to output a plurality of analog signals responsive to the input voltages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features and advantages of the present invention will become more apparent with a detailed description of the exemplary embodiments referencing the attached drawings. 
         FIG. 1  is a circuit diagram of a conventional DAC. 
         FIG. 2  is a circuit diagram of a DAC according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  is a circuit diagram of a DAC  100  according to an embodiment of the present invention. Referring to  FIG. 2 , the DAC  100  includes an input voltage generating circuit  110 , OP AMPs  120  and  130 , a bias circuit  140 , and a current supply circuit  150 . The input voltage generating circuit  110  includes a plurality of voltage generating circuits VG 1 –VGK. Each of the plurality of voltage generating circuits VG 1 –VGK may be a differential amplifier including NMOS transistors N 1 , N 2 , and N 3  where NMOS transistor N 3  acts as a current source for controlling operation of the NMOS transistors N 1  and N 2 . Output ports of the plurality of voltage generating circuits VG 1 –VGK are coupled to input nodes ID 1  and ID 2 , where the output ports may be coupled in parallel. In an embodiment, the drains of the NMOS transistors N 1  and N 2  of each of the plurality of voltage generating circuits VG 1 –VGK are coupled to the input nodes ID 1  and ID 2 , respectively. The plurality of voltage generating circuits VG 1 –VGK generate input voltages VI and VIB on the input nodes ID 1  and ID 2  by drawing input currents I n   1  and I n   2  to a ground in response to digital code signals C 0 –CK and C 0 B–CKB, which may be complementary to each other. The input currents I n   1  and I n   2  may be complementary to each other. Digital code signals C 0 –CK and digital code signals C 0 B–CKB may be complementary to each other. 
     The OP AMP  120  includes a resistor R 0  coupled between an output terminal of the OP AMP  120  and an inverse terminal of the OP AMP  120 . Resistor R 0  may form a negative feedback loop corresponding to OP AMP  120 . The inverse terminal of the OP AMP  120  is coupled to the input node ID 1  through a resistor R 2 . Likewise, the OP AMP  130  includes a resistor R 1  coupled between an output terminal of the OP AMP  130  and an inverse terminal of the OP AMP  130 . Resistor R 1  may form a negative feedback loop corresponding to OP AMP  130 . The inverse terminal of the OP AMP  130  is coupled to the input node ID 2  through a resistor R 3 . In an embodiment, the resistances of the resistors R 2  and R 3  are smaller than the resistances of the resistors R 0  and R 1 . 
     A reference voltage Vref is provided to the non-inverse terminals of the OP AMPs  120  and  130 . The OP AMPs  120  and  130  generates output voltages VO and VOB, respectively, in response to the reference voltage Vref and the input voltages VI and VIB, respectively. OP AMPs  120  and  130  generate additional currents I a   1  and I a   2  provided to the resistors R 0  and R 1 , respectively. 
     The bias circuit  140  generates a bias voltage Vb in response to a control signal CTL. In an embodiment, the bias circuit  140  may be a diode-connected NMOS transistor. 
     The current supply circuit  150  includes a reference current source circuit  151  and a current source circuit  152 . The reference current source circuit  151  includes a PMOS transistor Pb and NMOS transistors Nb 1  and Nb 2 . The reference current source circuit  151  is enabled or disabled in response to the bias voltage Vb. The reference current source circuit  151  generates a predetermined reference current I r  when it is enabled. When the current capacities of the NMOS transistors Nb 1  and Nb 2  in the reference current source circuit  151  are changed, a magnitude of the reference current I r  is also changed. 
     The current source circuit  152  includes a plurality of current source circuits CS 1 –CSK, each forming a current mirror with the reference current source circuit  151 . The plurality of current source circuits CS 1 –CSK are coupled to output nodes OD 1  and OD 2 . The current source circuits CS 1 –CSK may be coupled to output nodes OD 1  and OD 2  in parallel. Each of the plurality of current source circuits CS 1  through CSK may be a differential amplifier including PMOS transistors P 1 , P 2 , and P 3 , where PMOS transistor P 3  supplies an internal voltage VDD to the PMOS transistors P 1  and P 2 . In an embodiment, the source of the PMOS transistor P 3  is coupled to the internal voltage VDD, the gate of the PMOS transistor P 3  is coupled to a gate of the PMOS transistor Pb of the reference current source circuit  151 , and the drain of the PMOS transistor P 3  is coupled to the sources of the PMOS transistors P 1  and P 2 . The digital code signals C 0 –CK and C 0 B–CKB are coupled to gates of the PMOS transistors P 1  and P 2 . Drains of the PMOS transistors P 1  and P 2  are coupled to the output nodes OD 1  and OD 2  through resistors R 4  and R 5 , respectively. In an embodiment, the resistances of the resistors R 4  and R 5  are smaller than the resistances of the resistors R 0  and R 1 . The resistors R 0  through R 5  may prevent glitches generated on the output voltages VO and VOB when the digital code signals C 0 –CK and C 0 B–CKB are changed. 
     The plurality of current source circuits CS 1 –CSK generates currents I c   1 –I c K and I c   1 B–I c KB in response to the digital code signals C 0 –CK and C 0 B–CKB, respectively. The currents I c   1 –I c K and I c   1 B–I c KB may be complementary to each other. Accordingly, control currents I p   1  and I p   2 , obtained by respectively summing the currents I c   1 –I c K and I c   1 B–I c KB, are provided to the resistors R 0  and R 1 , respectively, where the input currents I n   1  and I n   2  are obtained by adding the additional currents I a   1  and I a   2  to the control currents I p   1  and I p   2 . In an embodiment, the magnitudes of the additional currents I a   1  and I a   2  are smaller than the magnitudes of the input currents I n   1  and I n   2 . 
     An operation of the DAC  100  will now be described in detail. The bias circuit  140  generates the bias voltage Vb in response to the control signal CTL. The input voltage generating circuit  110  and the current supply circuit  150  are enabled in response to the bias voltage Vb. The digital code signals C 0 –CK and C 0 B–CKB are provided to the input voltage generating circuit  110  and the current supply circuit  150 . For example, assume that the input voltage generating circuit  110  includes three voltage generating circuits VG 1 –VG 3  and the current source circuit  152  includes three current source circuits CS 1 –CS 3 , where the value of digital code signals C 0 –C 2  is ‘101’ and the value of digital code signals C 0 B–C 2 B is ‘010’. 
     In response to the digital code signals C 0 –C 2 , NMOS transistors N 1  of the voltage generating circuits VG 1  and VG 3  are turned on, and a NMOS transistor N 1  of the voltage generating circuit VG 2  is turned off. NMOS transistor N 2  of the voltage generating circuit VG 2  is turned on and NMOS transistors N 2  of the voltage generating circuits VG 1  and VG 3  are turned off in response to the digital code signals C 0 B through C 2 B. In response to the digital code signals C 0  through C 2 , a PMOS transistor P 1  of the current source circuit CS 2  is turned on, and PMOS transistors P 1  of the current source circuits CS 1  and CS 3  are turned off. PMOS transistors P 2  of the current source circuits CS 1  and CS 3  are turned on and a PMOS transistor P 2  of the current source circuit CS 2  is turned off in response to the digital code signals C 0 B through C 2 B. The PMOS transistor P 1  of the current source circuit CS 2  provides a current Ic 2  to the output node OD 1  through the resistor R 4 , and the PMOS transistors P 2  of the current source circuits CS 1  and CS 3  provide currents I c   1 B and I c   3 B to the output node OD 2  through the resistor R 5 . The magnitude of the control current I p   1  is equal to the magnitude of the current I c   2 , and the magnitude of the control current I p   2  is equal to a sum of the magnitudes of the currents I c   1 B and  1   c   3 B. The OP AMPs  120  and  130  may generate the additional currents I a   1  and I a   2 . Accordingly, the input currents I n   1  and I n   2  including the control currents I p   1  and I p   2  and the additional currents I a   1  and I a   2  are provided to the input voltage generating circuit  110  through the resistors R 0  and R 2 , and R 1  and R 3 , respectively. 
     Since the input currents I n   1  and I n   2  are formed in part by generating the control currents I p   1  and I p   2  in the current supply circuit  150 , the magnitude of current supplied by the OP AMPs  120  and  130  may be reduced. Accordingly, input offset voltages Vs 1  and Vs 2  decrease, and thus offsets of the output voltages VO and VOB decrease. Since the control currents I p   1  and I p   2  comprise the majority of the input currents I n   1  and I n   2 , the output voltages VO and VOB include fixed offsets irrelevant to a change in value of the digital code signals C 0 –CK and C 0 B–CKB. The input offset voltages Vs 1  and Vs 2  are shown according to Equation 2 
     
       
         
           
             
               
                 
                   
                     
                       Vs 
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                       ⁢ 
                       1 
                     
                     = 
                     
                       
                         
                           I 
                           a 
                         
                         ⁢ 
                         1 
                       
                       
                         G 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       Vs 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                     = 
                     
                       
                         
                           I 
                           a 
                         
                         ⁢ 
                         2 
                       
                       
                         G 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                   
                 
               
               
                 
                   Equation 
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                   2 
                 
               
             
           
         
       
     
     In Equation 2, G 1  indicates a gain of the OP AMP  120 , and G 2  indicates a gain of the OP AMP  130 . Since the input offset voltages Vs 1  and Vs 2  are determined by the additional currents I a   1  and I a   2  as opposed to input currents I n   1  and I n   2 , the input offset voltages Vs 1  and Vs 2  are smaller. 
     As described above, a DAC according to an embodiment of the present invention can output an analog signal having a fixed offset irrelevant to a change of a digital input signal. 
     While the present invention has been described with reference to exemplary embodiments, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.