Abstract:
A power shut-off and recovery circuit for data communication devices is provided. The power shut-off and recovery circuit has a power control circuit for polling a plurality of ports. The power control circuit determines how many of the ports are in an operational mode and compares the number of active ports to a predetermined number of ports. If the number of active ports is less than the predetermined number of ports, the power control circuit de-asserts an ENABLE signal. If the number of active ports is greater than or equal to the predetermined number of ports, the power control circuit asserts the ENABLE signal. A source transfer circuit is provided for selectively disengaging the data communication device from a power source in response to the ENABLE signal. The power control circuit re-polls all the ports and updates the ENABLE signal accordingly.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to data communication devices, and in particular, to a power shut-off and recovery circuit for use with data communication devices. 
     2. Background Art 
     Computer networks facilitate communication between individuals, businesses, and other entities. Computer networks include communication devices that support the communication of data from a sender to a receiver or data terminal. These communication devices include hubs that join communications lines together in a star configuration, routers that make decisions about which of several paths network traffic (in the form of data packets) will follow, repeaters that copy electrical signals from one Ethernet to another to extend the transmission distance, and bridges that connect two or more networks and forward packets among them. 
     FIG. 1 illustrates a conventional network system which includes a communication device, which can be a hub, a repeater, a router or a bridge. The communication device has a plurality of ports PORT0, PORT1, PORT2 . . . PORTN through which communication lines can be connected to a corresponding number of data terminals DT0, DT1, DT2 . . . DTN. 
     One disadvantage with conventional communication devices is that they are powered twenty-four hours-a-day even though the network is actually in use for only a specific number of hours during the day. In other words, since a communication device is only used when two or more users (i.e., data terminals) communicate via the communication device, the communication device is typically not used except during office hours. Unfortunately, these communication devices do not have any shut-off and recovery mechanism. This leads to two drawbacks. First, by keeping these communication devices on and powered continuously, the maintenance costs (e.g., electricity costs) for these devices increase, and power and energy are unnecessarily wasted. Second, by continuously powering these devices twenty-four hours-a-day, seven days a week, the electronic parts in these devices experience a shorter life than parts in a device that is powered only periodically. In other words, continuous and prolonged operation makes these communication devices more susceptible to damage from over-heating, wear, and device failure. 
     Thus, there still remains a need for a power shut-off and recovery mechanism for data communication devices so that unnecessary power consumption is curbed, and the life of the communication device is lengthened. 
     SUMMARY OF THE INVENTION 
     It is one object of the present invention to provide a power shut-off and recovery circuit that automatically shuts off a communication device when a first predetermined condition is met. 
     It is a further object of the present invention to provide a power shut-off and recovery circuit that automatically turns on a communication device when a second predetermined condition is met. 
     It is another object of the present invention to provide a power shut-off and recovery circuit that reduces wasteful and unnecessary power consumption by a communication device. 
     It is yet another object of the present invention to provide a power shut-off and recovery circuit that increases the life of a communication device. 
     To accomplish the objectives set forth above, the present invention provides a power shut-off and recovery circuit for conserving energy and increasing the life of a communication device. The power shut-off and recovery circuit has a signal detection circuit coupled to the ports of the communication device for detecting activity on the port and generating a first signal indicative of the activity. The power shut-off and recovery circuit further includes a power control circuit, coupled to the signal detection circuit, for receiving the first signal, and for selectively asserting an ENABLE signal based on the first signal. A source transfer circuit is coupled to receive the ENABLE signal for selectively engaging and disengaging a power source from the communication device based on the ENABLE signal. 
     In operation, the power control circuit determines how many of the ports are in an operational mode and compares the number of active ports to a predetermined number of ports. If the number of active ports is less than the predetermined number of ports, the power control circuit de-asserts an ENABLE signal which is normally used to power the communication device. If the number of active ports is greater than or equal to the predetermined number of ports, the power control circuit continues to asserts the ENABLE signal. The power control circuit re-polls all the ports continuously, or after a period of time, and updates the ENABLE signal accordingly. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simple block diagram of a conventional network system that includes a communication device and a plurality of data terminals. 
     FIG. 2 is a block diagram illustrating how the power shut-off and recovery circuit of the present invention is implemented with a network system. 
     FIG. 3 illustrates a first embodiment of the power shut-off and recovery circuit of FIG. 2. 
     FIG. 4 illustrates a second embodiment of the power shut-off and recovery circuit of FIG. 2. 
     FIG. 5 illustrates a third embodiment of the power shut-off and recovery circuit of FIG. 2. 
     FIG. 6 illustrates a fourth embodiment of the power shut-off and recovery circuit of FIG. 2. 
     FIG. 7 is a flow-chart illustrating the operation of the power shut-off and recovery circuit of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following description, for purposes of explanation and not limitation, specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In certain instances, detailed descriptions of well-known or conventional data processing techniques, hardware devices and circuits are omitted so as to not obscure the description of the present invention with unnecessary detail. 
     FIG. 2 illustrates a communication network system, such as a local area network (LAN) or similar system, in which the power shut-off and recovery circuit 10 of the present invention can be implemented. The system includes a communication device 14, the power shut-off and recovery circuit 10, and a plurality of data terminals DT0, DT1, DT2 . . . DTN. The communication device 14 has a plurality of ports 40, such as PORT --  0, PORT --  1, PORT --  2, . . . PORT --  N through which the corresponding data terminals DT0, DT1, DT2, . . . , DTN can communicate via the transmission and reception of signals, such as RX --  0, RX --  1, RX --  2, . . . , RX --  n, that correspond to the correspondingly numbered port 40 and data terminal DT. The communication device 14 can be, but is not limited to, a repeater, router, collecting tray, multiple coupling port installation, or switching hub. 
     The signals RX are also transmitted to a signal detection circuit 22 in the power shut-off and recovery circuit 10, which functions to detect the presence of signals RX from each port 40, and which provides these signals RX to a power control circuit 30. The power control circuit 30 determines whether there are at least two data terminals DT that are currently communicating via the communication device 14. If there are fewer than two data terminals DT that are currently communicating via the communication device 14, the power control circuit will transmit an ENABLE signal to a source transfer circuit 34 to cut off the power supply Vcc to the communication device 14 to cause the communication device 14 to shut off. The power control circuit 30 is continuously powered, and will periodically detect the presence of signals RX from the ports 40. As a result, once signals RX are detected from at least two ports 40, thereby indicating that two or more data terminals DT are seeking to communicate via the communication device 14, the power control circuit 30 will cause the source transfer circuit 34 to re-connect the power supply Vcc to the communication device 14. 
     FIG. 3 is a block diagram illustrating a first embodiment of the power shut-off and recovery circuit 10a of the present invention. In this embodiment, the communication device 14 is a collecting tray, although this is a non-limiting example intended for illustrative purposes only. The shut-off and recovery circuit 10a includes a multiplexer (MUX) 18a, a signal detection circuit 22a, a latch circuit 26a, a power control circuit 30a, and a source transfer circuit 34a. As explained above, the communication device 14 interfaces with the data terminals DT in the network and includes a plurality of ports 40, such as PORT --  0, PORT --  1, PORT --  2, . . . , PORT --  N. Each port 40 provides a signal, such as RX --  0, RX --  1, RX --  2, . . . , RX --  N, that corresponds to the correspondingly numbered port. These signals RX can represent communication and data signals from the data terminal DT to the communication device 14. The MUX 18a includes a plurality of pass transistors 44a, with each pass transistor 44a having a drain electrode, a source electrode, and a gate electrode. The gate electrode of each pass transistor 44a receives control signals, such as BE --  0, BE --  1, . . . , and BE --  N, from the power control circuit 30a, which will be described in greater detail hereinafter. Based on the control signal BE, the pass transistor 44a selectively couples the drain electrode to the source electrode. Therefore, only one of the selected signals (BE --  0, BE --  1, . . . , or BE --  N) is active at any one time so that there is only one signal connection on the connection between the MUX 18a and the signal detection circuit 22a. 
     The signal detection circuit 22a is coupled to the MUX 18a and detects whether a port 40 has an active signal. Each port 40 has an operational mode and an inactive mode. When in the operational mode, the port 40 is receiving active signals RX from the corresponding data terminal DT. When in the inactive mode, the port 40 does not receive any signals RX. When a signal RX is selectively passed through the MUX 18a and is detected, the signal detection circuit 22a generates a pulse at its output and provides the pulse to the latch circuit 26a. When no signal is passed through the MUX 18a, the signal detection circuit 22a remains in a low logic level. The signal detection circuit 22a can be implemented with an amplifier, a comparator, or other similar circuit component. 
     The latch circuit 26a includes a clock input CLK coupled to the signal detection circuit 22a, a D input coupled to a first predetermined voltage (such as Vcc), a Q output coupled to a Q input of the power control circuit 30a, and a CR input for receiving a CLEAR signal from the power control circuit 30a. Upon receipt of a clock pulse CLK, the output of the latch circuit 26a transitions from a logic-low level to a logic-high signal. The output signal remains at a logic-high level until it is reset by the CLEAR signal. The latch circuit 26a can be implemented, for example, in the form of a D-type flip-flop (with clear), and functions primarily to synchronize the receipt of the signals RX from the signal detection circuit 22a. 
     The power control circuit 30a, which is coupled to the MUX 18a, the latch circuit 26a, and the source transfer circuit 34a, selectively asserts an ENABLE signal based on the number of active ports 40 detected. In other words, the power control circuit 30a determines the operational mode of each of the ports 40 and employs the ENABLE signal to selectively turn the data communication device 14 on or off based on the number of ports 40 that are in the operational mode. As described in greater detail below in connection with FIG. 7, if less than two ports 40 are in the operational mode, the power control circuit 30a automatically de-asserts the ENABLE signal to shut the data communication device 14 off. As explained hereinafter, the ENABLE signal is employed to engage or disengage a power source (e.g., a power voltage signal Vcc) from the collecting tray 14. The power control circuit 30a (and the other power control circuits 30 described below) can be implemented by a programmable logic device, microcontroller, or a controller realized as a monolithic integrated circuit. The power control circuits 30 will include a processor and built-in software that carries out the signal detection, power shut-off and power recovery functions described in greater detail below. 
     The source transfer circuit 34a selectively connects a power supply voltage, such as Vcc, to the communication device 14 based on the ENABLE signal. In other words, the source transfer circuit 34a selectively engages the power source Vcc to the data communication device 14 in response to the logic level of the ENABLE signal. The source transfer circuit 34a can be implemented in the form of a simple relay operating to turn on or off a connection between the power supply Vcc and the communication device 14. Alternatively, the source transfer circuit 34a can have a power transistor having a gate electrode coupled to the power control circuit 30a for receiving the ENABLE signal, a drain electrode coupled to receive the power voltage Vcc, and a source electrode coupled to the communication device 14. 
     FIG. 4 is a block diagram illustrating a second embodiment of the power shut-off and recovery circuit 10 of the present invention. In this embodiment, the power shut-off and recovery circuit 10b is essentially the same as that illustrated in FIG. 3, except that the latch 26a has been omitted. As a result, the same numeral designations used for the circuit 10a of FIG. 3 are also used for the circuit 10b of FIG. 4 to represent the same components and elements, except that the designations end in an &#34;a&#34; for the circuit 10a of FIG. 3 and end in a &#34;b&#34; for the circuit 10b of FIG. 4. The latch 26a has been omitted, so that the output of the signal detection circuit 22b is directly connected to the Q input of the power control circuit 30b. The latch 26a can be omitted in cases where the processor of the power control circuit 30 operates at a sufficiently fast speed to receive the incoming signals RX, which are typically received at a fast rate. Otherwise, a latch 26a is needed to latch the incoming signals RX and to synchronize the receipt or input of these signals RX. 
     FIG. 5 is a block diagram illustrating a third embodiment of the power shut-off and recovery circuit of the present invention. In this embodiment, the communication device 14 is a multiple coupling port installation. The power shut-off and recovery circuit 10c includes a signal detection block 50 having a plurality of signal detection circuits 22c, a latch block 52 having a plurality of latch circuits 26c, a source transfer circuit 34c, and a power control circuit 30c. The communication device 14 includes a plurality of ports 40. Each port 40 is coupled to a corresponding signal detection circuit 22c in block 50, which is in turn coupled to a corresponding latch circuit 26c in block 52. When a signal detection circuit 22c detects activity on the associated port 40, the signal detection circuit 22c generates a pulse and provides the pulse to the corresponding latch circuit 26c. The corresponding latch circuit 26c, in response to the received pulse, asserts an output signal and provides the output signal to a corresponding input D0, . . . , DN of the power control circuit 30c. The power control circuit 30c reads and stores the output signal and then asserts the CLEAR signal to reset the latch circuits 26a. Based on the stored output signals, the power control circuit 30c determines whether to disengage the power source Vcc from the communication device 14 and asserts or de-asserts the ENABLE signal. Unlike the first embodiment 10a, which reads and stores the activity of each port 40 in a serial fashion, this embodiment can read and store the activity on each port 40 in a parallel or simultaneous fashion. In other words, the state of the ports 40 can be detected at the same time, instead of one port at a time as in the first embodiment. 
     The source transfer circuit 34c selectively connects a power supply voltage, such as Vcc, to the communication device 14 based on the logical state of the ENABLE signal provided by the power control circuit 30c, operating in the same manner as source transfer circuit 34a described above. 
     In comparing the first and third embodiments 10a and 10c, respectively, the first embodiment 10a is less expensive than the third embodiment 10c because fewer signal detection circuits 22 and latches 26 are provided, but the parallel processing of the signals RX in the third embodiment 10c renders it faster than the serial processing of the signals RX in the first embodiment 10a. 
     FIG. 6 is a block diagram illustrating a fourth embodiment of the power shut-off and recovery circuit 10 of the present invention. In this embodiment, the power shut-off and recovery circuit 10d is essentially the same as that illustrated in FIG. 5, except that the latches 26c have been omitted. As a result, the same numeral designations used for the circuit 10c of FIG. 5 are also used for the circuit 10d of FIG. 6 to represent the same components and elements, except that the designations end in an &#34;c&#34; for the circuit 10c of FIG. 5 and end in a &#34;d&#34; for the circuit 10d of FIG. 6. The omission of the latches 26c is based on the same principles explained above in connection with embodiment 10b of FIG. 4. 
     The operation of the power shut-off and recovery circuit 10 of FIGS. 2-6 is now described in connection with the flowchart of FIG. 7. The power control circuit 30 in each power shut-off and recovery circuit 10 controls the operation of the circuit 10, and is continuously powered by the voltage source Vcc (see FIG. 2), so it can be programmed to detect the status of the ports, either on a continuous or a periodic basis, and to determine whether the communication device 14 should be turned on or off. Referring to FIG. 7, in step 60, the power control circuit 30 provides power to the communication device 14 to turn it on for a period of time. Thereafter, in step 62, the status of all ports is checked. This step is accomplished in a slightly different manner for the different embodiments. For example, in the first embodiment 10a, the power control circuit 30 will initially assert the signals BE --  0, BE --  1, . . . , and BE --  N, one at a time, starting with BE --  0 and ending with BE --  N, and provide each BE signal to the respective pass transistor 44a. If the port 40 corresponding to the pass transistor 44a of the BE --  0 signal is active, then the signal detection circuit 22a detects the activity and sends a pulse to the clock port of the latch circuit 26a. The latch circuit 26a then generates a logic-high signal and provides the output signal to the power control circuit 30a. The power control circuit 30a reads and stores the received output of the latch circuit 26a, and the power control circuit 30a clears the latch circuit 26a by employing the CLEAR signal. This is repeated for each port 40 until all ports 40 are polled. The second embodiment 10b operates in a similar manner, except that the output of the signal detection circuit 22b is provided directly to the power control circuit 30b. 
     In the third embodiment 10c, all the signals RX --  0, RX --  1, . . . , RX --  N from all the ports 40 are provided in parallel to the corresponding signal detection circuits 22c, each of which detects the activity and sends a pulse to the clock port of the corresponding latch circuit 26c. Each latch circuit 26c then generates a logic-high signal and provides the output signal to the power control circuit 30c. The power control circuit 30c reads and stores the received output of the latch circuits 26c, and the power control circuit 30a clears the latch circuits 26a by employing the CLEAR signal. The fourth embodiment 10d operates in a similar manner, except that the outputs of the signal detection circuits 22d are provided directly and simultaneously to the power control circuit 30d. 
     After all the ports have been polled, the power control circuit 30 determines the number of ports 40 that are in the operational mode. If it is determined that the number of active ports 40 is two or more, then in step 64, the power control circuit 30 continues to assert the ENABLE signal that causes the source transfer circuit 34 to provide power supply voltage to the communication device 14, and processing returns to step 62 to check the status of the ports 40 again. However, if there is only one port 40 in the operational mode, then in step 66, the power control circuit 30 of the present invention de-asserts (i.e., turns off) the ENABLE signal which causes the source transfer circuit 34 to disengage the communication device 14 from the power source Vcc. Processing returns to step 62 to check the status of the ports 40 again. The status of the ports 40 can be checked again immediately, or after a predetermined time period. 
     Finally, if none of the ports 40 are in the operational mode, then in step 68, the power control circuit 30 of the present invention de-asserts (i.e., turns off) the ENABLE signal which causes the source transfer circuit 34 to disengage the communication device 14 from the power source Vcc. Processing then proceeds to step 70, in which the status of the ports 40 is checked again, either immediately after a predetermined time period. During this subsequent check, one of three situations will be detected. First, if the number of active ports 40 increases to two or more, then processing proceeds to step 64, where the power control circuit 30 asserts the ENABLE signal to provide power supply voltage Vcc to turn on the communication device 14. Processing then returns to step 62 to check the status of the ports 40 again. Second, if there is now one active port 40, this means that a new user has logged on to the network system, so processing proceeds to step 72, where the power control circuit 30 asserts the ENABLE signal to provide power supply voltage Vcc to turn on the communication device 14 to allow the user to log-in to the network system. Processing then returns to step 62 to check the status of the ports 40 again. Third, if there are still no active ports 40, then in step 74, the power control circuit 30 continues to de-assert (i.e., turns off) the ENABLE signal, and processing returns to step 70 to check the status of the ports 40 again, either immediately or after a predetermined time period. 
     Thus, the present invention provides a power shut-off and recovery circuit 10 that operates to shut off the communication device 14 whenever there is no need to have it on. The power shut-off and recovery circuit 10 further operates to monitor the status of the ports 40 either continuously or periodically, and to turn the communication device 14 on again if there are sufficient users in the network. The shut-off of the communication device 14 when it is not in use conserves energy and increases the operation life of the communication device 14. 
     Although certain components, subsystems, and blocks have been described above as including certain elements, it will be appreciated by those skilled in the art that such disclosures are non-limiting, and that different elements, or combinations thereof, can be provided for such components, subsystems, and blocks without departing from the spirit and scope of the present invention. 
     It will be recognized that the above described invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the disclosure. Thus, it is understood that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.