Abstract:
Control method and power controller suitable for a switched mode power supply with a power switch are provided. An ON time of the power switch is recorded. An estimated OFF time is provided based on the ON time. The estimated OFF time is in positive correlation with the ON time. The power switch is turned ON after the elapse of the estimated OFF time.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the priority benefits of U.S. provisional application Ser. No. 61/429,188, filed on Jan. 03, 2011. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
     
    
     BACKGROUND 
       [0002]    The present disclosure relates generally to switched-mode power supplies, especially to QR-similar power supplies. 
         [0003]    Almost each electronic product needs a power supply to convert electric energy of power sources such as batteries or power grid lines into a power source specifically suitable to its own core circuit. Conversion efficiency, among other factors, is an important issue that circuit designers must concern. 
         [0004]    Quadrature-resonance (QR) mode power supplies could reduce the switching loss of a power switch. The conversion efficiency of QR mode power supplies are, in theory and in practice, excellent in comparison with other power supplies, such that QR mode power supplies are welcome in the art, especially in high power applications. 
         [0005]      FIG. 1  illustrates a conventional QR mode power supply  8 . Converter  10  shows a boost topology. QR mode power controller  18  switches power switch  15  to control energization or de-energization of primary winding PRM. Feedback circuit  20  detects the voltage at output node OUT and generates feedback signal V FB  at feedback node FB of QR mode power controller  18 . 
         [0006]      FIG. 2  shows some waveforms of signals in  FIG. 1 , wherein, from top to bottom, gate signal V GATE  represents the voltage at node GATE; voltage signal V ZCD  represents the voltage at zero current detection node ZCD; current sense signal V CS  represents the voltage at current sense node CS; signal V CN  represents the voltage at connection node CN; and current signal I PRM  represents the current flowing through primary winding PRM. 
         [0007]    QR mode power controller  18  controls ON time T ON  of power switch  15 , meaning the time period when power switch  15  performs a short circuit, based on feedback signal V FB . Off time T OFF , when power switch  15  performs an open circuit, is controlled according to the detection at zero current detection node ZCD. For example, at the moment of zero current detection time t ZCD , QR mode power controller  18  detects voltage signal V ZCD  drops across 0 volt, and this crossing is deemed as an indication that the de-energization of primary winding PRM and auxiliary winding AUX is completed. A delay time after zero current detection time t ZCD , QR mode power controller  18  turns on power switch  15  and starts ON time T ON  of a following switch cycle. 
         [0008]    What an ideal QR mode power controller  18  expects to achieve is that, when power switch  15  is turned ON, signal V CN  is locating at or around a valley to reduce the switching loss of power switch  15 . 
       SUMMARY 
       [0009]    Embodiments of the present invention provide a control method suitable for a switched mode power supply with a power switch. An ON time of the power switch is recorded. An estimated OFF time is provided based on the ON time. The estimated OFF time is in positive correlation with the ON time. The power switch is turned ON after the elapse of the estimated OFF time. 
         [0010]    Embodiments of the present invention provide a QR-similar power controller. A QR-similar timing generator asserts a QR-similar setting signal to turn on a power switch after an estimated OFF time when the power switch is switched from an ON state to an OFF state. The estimated OFF time is generated by the QR-similar timing generator based on an ON time of the power switch, and the estimated OFF time is in positive correlation with the ON time. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  illustrates a conventional QR mode power supply; 
           [0013]      FIG. 2  shows some waveforms of signals in  FIG. 1 ; 
           [0014]      FIG. 3  enlarges portions of signal V CN  and current signal and illustrates their relationships in timing; 
           [0015]      FIG. 4  shows a QR-similar power supply according to embodiments of the invention; 
           [0016]      FIG. 5  exemplifies internal circuitry of a QR-similar power controller; 
           [0017]      FIG. 6A  shows a clock timing generator; 
           [0018]      FIG. 6B  illustrates clock frequency f CYC-C  in connection with feedback signal V FB ; 
           [0019]      FIG. 7A  shows a QR-similar timing generator; 
           [0020]      FIG. 7B  illustrates clock frequency f CYC-QRS  in connection with feedback signal V FB ; 
           [0021]      FIG. 8  illustrates clock frequency f CYC  in connection with feedback signal V FB ; 
           [0022]      FIG. 9  shows a delay device; and 
           [0023]      FIG. 10  illustrates waveforms of signals in  FIG. 5 ,  FIG. 7A  and  FIG. 9 . 
       
    
    
     DETAILED DESCRIPTION 
       [0024]      FIG. 3  enlarges portions of signal V CN  and current signal I PRM  and illustrates their relationships in timing. 
         [0025]    As shown in  FIG. 3 , cycle time T CYC  is consisted of ON time T ON  and OFF time T OFF , which has two parts: discharge time T DIS  and ring time T RNG . Discharge time T DIS  refers to the time for primary winding PRM to de-energize completely, or the elapse time when current signal I PRM  decreases to 0 A from its maximum value. After the completion of the de-energization of primary winding PRM, primary winding PRM and the parasitic capacitor at connection node CN compose an LC resonance circuit, such that signal V CN  starts oscillating and dropping. A well-designed QR mode power controller shall turn ON a power switch after ring time T RNG  during which signal V CN  oscillates from a top to a valley. 
         [0026]    It can be derived that, as for an ideal QR mode power supply, discharge time T DIS  is in proportion to ON time T ON  and ring time T RNG  is in proportional to an oscillation period of the parasitic LC resonance circuit. Accordingly, cycle time T CYC  could be presented by the following equation I. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           T 
                           CYC 
                         
                         = 
                           
                          
                         
                           
                             T 
                             ON 
                           
                           + 
                           
                             T 
                             OFF 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             T 
                             ON 
                           
                           + 
                           
                             T 
                             DIS 
                           
                           + 
                           
                             T 
                             RNG 
                           
                         
                       
                     
                   
                   
                     
                       
                         
                           = 
                             
                            
                           
                             
                               T 
                               ON 
                             
                             + 
                             
                               
                                 K 
                                 1 
                               
                               * 
                               
                                 T 
                                 ON 
                               
                             
                             + 
                             
                               
                                 K 
                                 2 
                               
                               * 
                               
                                 sqrt 
                                  
                                 
                                   ( 
                                   
                                     
                                       L 
                                       PRM 
                                     
                                     * 
                                     
                                       C 
                                       CN 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         , 
                       
                     
                   
                 
               
               
                 I 
               
             
           
         
       
     
         [0000]    wherein, K 1  and K 2  are two constants, sqrt() represent the function of square root, L PRM  represents the inductance of primary winding PRM, C CN  represents the equivalent capacitance at node CN. If a power supply operates to have a cycle time T CYC  as shown in equation I, it operates substantially in QR mode. 
         [0027]    In the art, zero current detection time t ZCD  is detected and a delay time is predetermined to decide the end of OFF time T OFF . The actual discharge time T DIS  and ring time T RNG  are not detected or generated. Therefore, operation in QR mode is achieved probably instead of accurately. 
         [0028]    An embodiment of this invention discloses a QR-similar power supply, which detects no zero current detection time t ZCD  and operates in QR mode with considerable accuracy. 
         [0029]      FIG. 4  shows a QR-similar power supply  60  according to embodiments of the invention, wherein those same or similar to  FIG. 1  are comprehensible to those skilled in the art, and are not detailed for brevity. Unlike  FIG. 1 , QR-similar power supply  60  has QR-similar power controller  61  having no zero current detection node ZCD, but delay setting node RIN instead, connected to resistor  63 . QR-similar power controller  61  could be formed on a monolithic chip with pins of VCC, GND, GATE, CS, RIN, and FB. 
         [0030]      FIG. 5  exemplifies internal circuitry of QR-similar power controller  61 . Feedback signal V FB  at feedback node FB substantially controls, via buffer  68 , voltage-dividing resistors, and comparator  88 , the peak voltage of current sense signal V CS  and ON time T ON  as well. Clock generator  62  generates pulse signal, periodically setting SR register  82  and determining the beginning of ON time T ON , which equals to the ending of OFF time T OFF  in the previous switch cycle. 
         [0031]    Clock generator  62  has QR-similar timing generator  66  and clock timing generator  64 , whose outputs O 1  and O 2  both are connected to AND gate  65 . Output of AND gate  65  is connected to not only S terminal of SR register  82 , but also the reset node of clock timing generator  64 . Because of the existence of AND gate  65 , the later of asserted QR-similar setting signal S QRS  output from QR-similar timing generator  66  or asserted clock setting signal S C  output from clock timing generator  64  sets SR register  82  to turn ON power switch  15  and resets clock timing generator  64 . 
         [0032]      FIG. 6A  shows clock timing generator  64 . According to feedback signal V FB , voltage-controlled current source  70  determines its output current and the slope of ramp signal V RAMP  as well. At the time when ramp signal V RAMP  exceed reference voltage V REF1 , a comparator asserts clock setting signal S C  at its output O 1 . The reset node of clock timing generator  64 , if “1” in logic, renders the discharge of a capacitor and ramp signal V RAMP  is reset to be 0 volt. 
         [0033]    If clock setting signal S C  were directly forwarded to the reset node in  FIG. 6A , clock timing generator  64  becomes a clock generator, whose clock frequency f CYC-C  in connection with feedback signal V FB  is exemplified in  FIG. 6B , where, if feedback voltage V FB  is lower than reference voltage V REF2 , clock frequency is substantially at a minimum; if feedback signal V FB , exceeds reference voltage V REF3 , it is substantially at a maximum; and, if feedback signal V FB  is between reference voltages V REF2  and V REF3 , it varies linearly along with feedback signal V FB . 
         [0034]      FIG. 7A  shows QR-similar timing generator  66 . The voltage gain of amplifier  72  is one, such that amplifier  72  duplicates ramp signal V RAMP  at its output. At the moment when gate signal V GATE  switch power switch  15  from an ON state to an OFF state, sample/hold circuit  76  samples ramp signal V RAMP  and keeps the record in capacitor  77  as sampled record V SAM . In a way, sampled record V SAM  represents or records ON time T ON . Amplifier  74 , whose voltage gain is K, larger than 1, amplifies sampled record V SAM  to generate discharge target value V TAR  (=K*V SAM ). At the moment when ramp signal V RAMP  exceeds discharge target value V TAR , comparator  78  asserts completion signal S DISE . It takes ON time T ON  for ramp signal V RAMP  to ramp up from 0V to sampled record V SAM . Accordingly, estimated discharge time T DISE  for ramp signal V RAMP  to ramp up from sampled record V SAM  to discharge target value V TAR  can be expressed by the following equation II. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           T 
                           DISE 
                         
                         = 
                           
                          
                         
                           
                             
                               ( 
                               
                                 
                                   V 
                                   TAR 
                                 
                                 - 
                                 
                                   V 
                                   SAM 
                                 
                               
                               ) 
                             
                             / 
                             
                               V 
                               SAM 
                             
                           
                           * 
                           
                             T 
                             ON 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             ( 
                             
                               K 
                               - 
                               1 
                             
                             ) 
                           
                           * 
                           
                             
                               T 
                               ON 
                             
                             . 
                           
                         
                       
                     
                   
                 
               
               
                 II 
               
             
           
         
       
     
         [0000]    Accordingly, the combination of sample/hold circuit  76 , amplifier  74  and comparator  78  represents as a discharge time generator that asserts completion signal S DISE  to indicate the completion of de-energization after estimated discharge time T DISE , which is in proportion to ON time T ON  as shown in equation II. 
         [0035]    Delay device  84  provides delay time T DLY , which could be determined by resistor  63  connected at delay setting node RIN. Delay time T DLY  after completion signal S DISE  is asserted, delay device  84  asserts QR-similar setting signal S QRS . 
         [0036]    If QR-similar setting signal S QRS  were directly forwarded to the reset node of clock timing generator  64 , the combination of QR-similar timing generator  66  and clock timing generator  64  performs as another clock generator, whose clock frequency f CYC-QRS  in connection with feedback signal V FB  is exemplified in  FIG. 7B . The higher feedback signal V FB , the longer ON time T ON , the longer estimated discharge time T DISE , the slower clock frequency f CYC-QRS . Cycle time T CYC-QRS , the inverse of clock frequency f CYC-QRS , can be expressed by the following equation III. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           T 
                           
                             CYC 
                              
                             
                               - 
                             
                              
                             QRS 
                           
                         
                         = 
                           
                          
                         
                           
                             T 
                             ON 
                           
                           + 
                           
                             T 
                             OFFE 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             T 
                             ON 
                           
                           + 
                           
                             T 
                             DISE 
                           
                           + 
                           
                             T 
                             DLY 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             T 
                             ON 
                           
                           + 
                           
                             
                               ( 
                               
                                 K 
                                 - 
                                 1 
                               
                               ) 
                             
                             * 
                             
                               T 
                               ON 
                             
                           
                           + 
                           
                             T 
                             DLY 
                           
                         
                       
                     
                   
                 
               
               
                 III 
               
             
           
         
       
     
         [0000]    Here in this embodiment, estimated OFF time T OFFE  provided is the summation of delay time T DLY  and estimated discharge time T DIS , and is in positive correlation with ON time T ON . In other words, the longer ON time T ON , the longer estimated OFF time T OFFE . As long as K and delay time T DLY  are properly designed, equation III will be equivalent to equation I, such that the timings for QR-similar timing generator  66  to switch ON or OFF a power switch will be substantially the same with those required for operating in ideal QR mode. 
         [0037]    If needed, a device (no shown) might be provided to limit the minimum of clock frequency f CYC-QRS . In other words, in one embodiment, clock frequency f CYC-QRS  cannot be lower than a predetermined minimum frequency f CYC-QRS-MIN . 
         [0038]    Because of the existence of AND gate  65 , for a fixed feedback signal V FB , clock generator  62  of  FIG. 5  will provide clock frequency f CYC , which is the less of clock frequency f CYC-QRS  in  FIG. 7B  or clock frequency f CYC-C  in  FIG. 6B , and the result is demonstrated in  FIG. 8 . When feedback signal V FB  is relatively high, clock generator  62  provides timings similar with those required for operating in ideal QR mode. When feedback signal V FB  is relatively low, clock generator  62  provides clock frequency f CYC  substantially decreasing with the decrease of feedback signal V FB , enhancing conversion efficiency for light load. 
         [0039]      FIG. 9  illustrates delay device  84 , whose IN node receive completion signal S DISE  to provide delay time T DLY . In one embodiment, QR-similar power controller  61  is formed on a monolithic chip with delay setting pin RIN. Resistor  63  could be outside the monolithic chip and determines both current I SET  and delay time T DLY . The operation and the theory of delay device  84  are comprehensible to persons skilled in the art and are not detailed for brevity. 
         [0040]      FIG. 10  illustrates waveforms of signals in  FIG. 5 ,  FIG. 7A  and  FIG. 9 , where signal V RMP  is the voltage at capacitor  89 ; and V THR  is a predetermined voltage. The relationships between the signals in  FIG. 10  can be derived from the previous teaching based on  FIGS. 5 ,  7 A and  9  by persons skilled in the art, such that they are not detailed here for brevity. 
         [0041]    Although a booster power converter is shown as an embodiment of the invention, this invention is not limited to, but could be applied to buck converters, flyback converters and the like. 
         [0042]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.