Abstract:
A method and an apparatus for suppressing errors reported by an error check function of a circuit. The method and apparatus utilizes a shifter to provide an enablement bit for the error reporting. An error is reported only if the enablement bit is set such that it allows the error to be latched through the circuit.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates generally to computer architectures and, more particularly, to a method and an apparatus for performing error checking enablement in a computer.  
           [0003]    2. Description of Related Art  
           [0004]    Upon initialization, electronic components, such as processors, generally perform self-tests on power-up, which is commonly referred to as power-on-reset (POR). The POR typically involves setting latches within the processor to known states, such as logical zeros. After coming out of POR, error-checking logic verifies that the condition of certain signals, i.e., latches, is as expected. The error-checking logic reports an error condition if the circuits do not match the expected values.  
           [0005]    Many latches, however, are connected in a serial fashion within a pipeline, and may require two or more clock cycles before reaching a known valid state (in other words, invalid states may exist in the latches directly after coming out of POR). In order to verify the operation of these circuits, therefore, additional logic and/or circuitry is required to prevent an error condition from being reported prior to the complete initialization of the circuit. Furthermore, the additional logic and/or circuitry usually creates additional problems, such as debugging problems, and/or requires additional resources, such as a validity bit.  
           [0006]    Therefore, there is a need for a method and a system to selectively enable post-POR error checking in order to suppress false errors.  
         SUMMARY  
         [0007]    The present invention provides a method and an apparatus for suppressing false errors of one or more circuits by selectively enabling error checkers. The method and apparatus utilizes a shifter to shift an enable bit at the rate at which the one or more circuits become initialized. Errors are suppressed if the value from the shifter corresponding to the clock cycle the one or more circuits are initialized is not enabled. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:  
         [0009]    [0009]FIG. 1 is a schematic of a typical error-checking system that embodies the present invention;  
         [0010]    [0010]FIG. 2 is a schematic of a typical circuit that may be tested by the present invention; and  
         [0011]    [0011]FIG. 3 is a schematic of a shifter that embodies features of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0012]    In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning the operation and the implementation of electrical components, such as latches and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the skills of persons of ordinary skill in the relevant art.  
         [0013]    It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are implemented in hardware in order to provide the most efficient implementation. Alternatively, the functions may be performed by a processor, such as a computer or an electronic data processor, in accordance with code, such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.  
         [0014]    Referring to FIG. 1 of the drawings, the reference numeral  100  generally designates an error-checking system embodying features of the present invention. The error-checking system  100  generally comprises one or more circuits  110 , each of which is coupled to an error check logic component  112 . The circuits  110 , as will be discussed in greater detail below with reference to FIG. 2, generally comprises one or more electrical components, such as a latch, buffers, and/or the like. The present disclosure discusses the present invention in terms of a latch for purposes of illustration only and, therefore, the present invention should not be limited to latches in any manner. The use of the present invention with other electrical components is considered obvious to one of ordinary skill in the art upon a reading of the present disclosure and, therefore, will not be discussed in greater detail except insofar as is necessary to adequately describe the present invention.  
         [0015]    Preferably, the circuits  110  are configurable to multiple-modes, such as a scan mode and a functional mode, and accepts data accordingly. For example, FIG. 1 illustrates that the circuits  110  each have two inputs, a reset value, e.g., a ‘0’, and a known bit stream, such as ‘1, 0, . . . , 1’. Upon configuring the circuits  110  to operate in the scan mode, the reset value is latched into the circuits to initialize the circuit  110 . Upon configuring the circuits  110  to operate in a functional mode, however, the known bit stream is latched into the circuits  110 . It should be noted that the values of ‘0’ and ‘1, 0, . . . , 1’ are used for illustrative purposes only and that other values may be utilized. Furthermore, it should be noted that the known bit stream may be any value that is known by the error check logic components  112 , such as random variables, values produced by a separate logic component, values from a previous cycle, and the like.  
         [0016]    Error check logic components  112  are configured to receive one or more signals from the respective circuits  110 , to compare the received signals with an expected valid value, and to indicate whether the received signals match the expected valid values. Preferably, the error check logic components  112  output a logic ‘1’ to indicate an error, and a logic ‘0’ to indicate a successful match. Alternatively, other values, such as a logic ‘0’ to indicate an error, and a logic ‘1’ to indicate a successful match, may be used to indicate similar states.  
         [0017]    The output of the error check logic components  112  are coupled to logic ANDs  116  to receive the indication of whether the received signals match the expected values. The logic ANDs  116  are also coupled to a corresponding cycle enable bit of a shifter  114 , which is discussed in further detail below with reference to FIG. 3. The shifter  114  is configured to accept as input an error-checker-suppressing value, such as a logic ‘0’, in the scan port, which is enabled when the circuits  110  are configured to operate in the scan mode, and an error-checker-enablement value, such as a logic ‘1’, in the data port, which is enabled when the circuits  110  are configured to operate in the functional mode. As will be discussed below, the output of the shifter  114  is initialized to all zeroes during the scan mode. Upon switching to the functional mode, logic ones are propagated through the shifter such that only the first cycle&#39;s error-check enable bit will be set, i.e., a logic ‘1’, in the first cycle; only the first cycle&#39;s error-check enable bit and the second cycle&#39;s error-check enable bit are set in the second cycle, and so on. Therefore, the error-check logics&#39; values will only be set if the circuitry has had an opportunity to propagate the expected valid values.  
         [0018]    [0018]FIG. 2 is a schematic diagram depicting circuitry that may be tested, discussed above with respect to the circuits  110  (FIG. 1), in accordance with a preferred embodiment of the present invention. Accordingly, the circuits  110  may comprise one or more latches  210 . Each of the latches  210  are configured to comprise a scan port, which is enabled during the scan mode of the circuit  110 , and a data port, which is enabled during the functional mode of the circuit  110 . Preferably, the scan ports are utilized to initialize the latches  210  to a logic ‘0’ during a scan mode. Additionally, the data ports are utilized to capture data from circuits from within the machine for the error checking. The output of each latch is coupled to the error check logic component  112  as described above. Furthermore, additional logic and circuitry (not shown) may be included within the circuits  110 ; particularly, it is expected that the output of each latch  210  may be attached to additional circuitry/logic prior to being sent to the error check logic  112 .  
         [0019]    [0019]FIG. 3 is a schematic diagram depicting circuitry that may be utilized as a shifter, discussed above with respect to the shifter  114  (FIG. 1), in accordance with a preferred embodiment of the present invention. Accordingly, the shifter  114  preferably comprises a series of latches  310 , the number of latches preferably matching the number of cycles necessary to propagate the expected valid values throughout the circuitry being tested. As will be appreciated by one skilled in the art, the latches  310  are configured such that each latch will be initialized to a logic ‘0’ during the scan mode and logic ‘1’s will be propagated through the latches on each clock cycle upon entering the functional mode. The output of each latch  310  is coupled to the logic ANDs  116  and to the inputs of the next latch.  
         [0020]    It is understood that the present invention can take many forms and embodiments. Accordingly, several variations may be made in the foregoing without departing from the spirit or the scope of the invention. For example, the polarity and/or meaning of individual bits may be reversed, additional logic and/or circuitry may be added, and the like.  
         [0021]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered obvious and desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.