Abstract:
A decoder apparatus for selecting column lines of a CMOS imager pixel array is disclosed. The decoder apparatus is made up of at least one first decoder and at least one set of second decoders, each set being associated with respective first decoder. The first decoder decodes a first portion of an address representing a desired pixel array column and, depending on the results of the first decoding operation, selectively enables the associated second decoder set which decodes a second portion of the address to select a column line..

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to complementary metal oxide semiconductor (CMOS) imagers, and more particularly to a decoder apparatus for use with CMOS imagers.  
         BACKGROUND OF THE INVENTION  
         [0002]    There are a number of different types of semiconductor based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices, hybrid focal arrays, etc. CCD technology is often employed for image acquisition and enjoys a number of advantages which makes it the preferred technology, particularly for small size imaging applications. CCDs are capable of large formats with small pixel size and they employ low noise charge domain processing techniques.  
           [0003]    However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, exhibit destructive readout over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there have been some attempts to integrate on-chip signal processing with CCD arrays, these attempts have not been entirely successful.  
           [0004]    CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes a certain amount of time. CCD arrays may also suffer from incomplete charge transfer from pixel to pixel which results in image smear.  
           [0005]    Because of the inherent limitations in CCD technology, there is an interest in complimentary metal oxide semiconductor (CMOS) imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.  
           [0006]    Some of the advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD because standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.  
           [0007]    Among the challenges to employing CMOS for imager applications, is creating a structure which scales well but yet does not increase power consumption. One problem with conventional CMOS imagers is that pixel density cannot be increased on a CMOS chip without increasing power consumption due to increases in the size of the required decoder structure. A conventional approach to decoding an address space is to generate each address with an individual decoder. Consequently, as an address space increases, the decoder size increases as well since the number of bits requiring decoding increases. In the case of image sensors, the width of the decoder is fixed (decided by bit-size or number of pixels), and the only existing approach to add more bits into the decoder is to increase the decoder size which results in increases to the silicon area within which it can be implemented. Increases in silicon area brings with it increases in parasitic capacitance which results in slower circuits and increased power consumption. Consequently, a new approach to decoding an address space is needed for CMOS imagers to enable designers to increase address space while reducing power consumption and silicon area usage.  
         BRIEF SUMMARY OF THE INVENTION  
         [0008]    A decoder apparatus for use with a CMOS imager pixel array is disclosed. The decoder apparatus is made up of at least one first decoder and a plurality of second decoders associated with each first decoder. The first decoder decodes a first portion of an address representing a desired pixel array column and, depending on the results of the first decoding operation, enables a subset of second decoders which decode a second portion of the address to select a particular column for pixel signal readout. Since only one subset of second decoders is enabled at a time power is reduced. In addition, the die area required to integrate the first and second decodes is less than the area required to integrate a single decoder for a given address size.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    The above and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.  
         [0010]    [0010]FIG. 1 shows a simplified block diagram of a decoder apparatus, in accordance with an exemplary embodiment of the invention;  
         [0011]    [0011]FIG. 2 shows a simplified block diagram of the combined decoder of the FIG. 1 decoder apparatus;  
         [0012]    [0012]FIG. 3 shows a simplified block diagram of a portion of a CMOS imager pixel array coupled to the decoder apparatus of FIG. 1; and 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]    In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical or procedural changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention.  
         [0014]    [0014]FIG. 1 shows a simplified block diagram of a hierarchical decoder apparatus, in accordance with an exemplary embodiment of the invention. The hierarchical decoder apparatus decodes and enables the selection of an individual column address (co 10  . . . co 115 ) within a CMOS pixel array based upon its receiving a first plurality of bits representing the most significant bits (MSBs) of a desired column address at an input MSB address bus  33  and a second plurality of bits representing the least significant bits (LSBs) of the desired column address at an input LSB address bus  35 .  
         [0015]    The apparatus first decodes the MSBs of the desired column address at input bus  33  in a first MSB decoder  31  and, if the MSBs match the MSBs of pixel column addresses accessible by the decoder  31 , then the apparatus enables a set of a second decoders  37  which decode the LSBs of the desired column address at input bus  35 . The decoder set  37  contains a plurality of individual second decoders, one for each of the column lines col 0  . . . col 15 . Thus, at first, only a first group of MSBs are decoded. Once the first group of MSBs are identified by MSV decoder  31 , then the MSB decoder  31  enables the associate set  37  of LSB decoders for column selection. Once the LSBs are decoded, the desired pixel array column represented by the MSBs and LSBs may be accessed (for pixel signal read out).  
         [0016]    In the implementation illustrated in FIG. 1, the decoder apparatus is coupled to a MSB bus  33  carrying six (6) MSBs of the 10 bit column address. These are bits  4 - 9  of the pixel column address. The first block select decoder  31  decodes the MSBs and determines whether the decoded MSBs match the MSBs for the group of column addresses accessible by decoder  31 . If there is a match, the block select decoder  31  transmits a column enable signal to the decoder set  37  via signal line  15 .  
         [0017]    Upon receiving the column enable signal, the decoders of decoder set  37  decode the four (4) LSBs of the 10-bit column address received on LSB bus  35  and identifies one of the  16  column lines  41  (co 10  . . . co 115 ) accessible via enabled decoder set  37 . Thereafter, the desired pixel array column line is accessed. For an address space of 1024 columns, the FIG. 1 decoder apparatus is replicated  64  times as depicted in FIG. 3 (64×16=1024). Thus each of the replicated decoder circuits of FIG. 1 is a block decoder which is able to decode one of the  16  column lines of that block.  
         [0018]    Turning to FIG. 2, a schematic diagram of the combined decoder set  37  is depicted. Decoder set  37  receives inputs from the LSB bus  35  and also receives the column enable signal from the block decoder ( 31  of FIG. 1) via signal line  15 , as described above in connection with FIG. 1. Each input bit (e.g., bits  0 - 3 ) of the incoming LSBs of the desired column address is receivable by each individual decoder  13  within the decoder set  37 . Further, each individual decoder  13  is configured to receive the column enable signal received by the combined decoder  37  via signal line  15 . As a result, , when a column enable signal is present, the desired one of the  16  column lines (e.g., col 0 -col 15 ) of the pixel array  45  (of FIG. 3) is activated and accessible. If the column enable signal is absent for a particular block, then the decoder set  37  for that block remains disabled, thereby reducing overall power consumption.  
         [0019]    Referring again to FIG. 3, the replicated FIG. 1 decoder apparatus is coupled to a CMOS pixel array, in accordance with an exemplary embodiment of the invention. As described above, for an address space of 1024 columns,  64  FIG. 1 decoders are required. Each of the decoder sets  37  is coupled to  16  column lines of the pixel array  45 . Each decoder set  37  is coupled to a respective block decoder  31 . Each block decoder  31  receives the MSBs from the MSB bus  33  and for a given combination of MSBs, one of the block decoders  31  transmits a column select enable signal and transmits the same to its associated decoder set  37 . Also depicted as being coupled to the pixel array  45  is a row decoder  43 .  
         [0020]    It should be noted that while a decoder apparatus for decoding a column address of a CMOS imager pixel array  45  has been described, pixel rows in a CMOS imager can also be selected one at a time using the FIG. 1- 3  decoder apparatus.  
         [0021]    The CMOS imager, including the decoder apparatus of the invention, may be manufactured using any known techniques available in the art and is not limited to the specific circuit schematic layouts described in connection with the figures. For example, although a specific number of column lines are depicted in the invention, such numbers are only for exemplary purposes and the invention is not limited thereto. Further, while a specific number of bits have been designated as the MSBs and LSBs of the column address, it should be readily apparent that any other number of bits can be selected as the MSBs and LSBs. Accordingly, the invention is not limited by the description above but is only limited by the scope of the appended claims.