Abstract:
A system and method for providing power to a set of logic cards that enables approximately twice as much power to be supplied to the logic cards than would normally be available using conventional power supply systems and methods. The system includes a system backplane having a split power plane, wherein each half of the split power plane receives power from a separate power supply circuit. Preferably, the power supply circuits comprise circuit portions of a power entry module (PEM), which typically is connected to a pair of service points provided by a DC or an AC power source. The PEM and system backplane include circuitry to enable a single backplane to be powered by two separate power supplies, thereby providing the system backplane and the set of logic cards with approximately twice as much power than could normally be provided by a single service point. To facilitate this capability, the PEM includes circuitry for detecting the power supplied by each of its power supply circuits and for automatically shutting down power supply to the system backplane in the event of a detected failure condition, such as an undervoltage condition on one or both of the power supplies, and a voltage differential between the power supplies that exceeds a predetermined threshold. The system and method also provides for the use of a second PEM that is used in situations requiring a redundant power supply system.

Description:
FIELD OF THE INVENTION 
     The present invention generally pertains to the field of power supplies, and more particularly concerns a power system that supplies power to a system backplane having a split power plane. 
     BACKGROUND OF THE INVENTION 
     In telecommunications (telco) environments, it is important that the various switching systems used to transfer calls and data across communication networks be provided with a constant power supply, regardless of external conditions, such as power failures. As a result, many telecommunications (telco) environments provide battery power sources rather than AC power sources, although AC power sources may be used to provide a DC supply to the telco equipment with a battery backup for emergency situations. 
     Because many telco companies have been in operations for decades, the power provided at various power distribution panels within their facilities were often designed and built many years ago, when much of the telco switching equipment required less power. For example, many telco environments provide a maximum of 60 A of current at their power distribution panels. As a result, the maximum power that can delivered to a switching device from the existing distribution panels is limited. 
     As an option, new switching equipment could be wired directly to a battery source and be physically located close to the battery source to meet the Bellcore power distribution requirements of the equipment. However, this leads to a very expensive and time-consuming installation, as it requires significant changes to the telco facility. 
     SUMMARY OF THE INVENTION 
     A system and method are described for supplying power to electronic systems, such as telco switching systems, in a manner that enables approximately twice as much power to be supplied to the electronic system than would normally be available using conventional power supply systems and methods. The power supply system includes a system backplane having a split power plane, wherein each half of the split power plane receives power from a separate power supply circuit. Preferably, the power supply circuits comprise circuit portions of a common power entry module (PEM), which typically will receive input power from a pair of service points provided by a DC such as a battery source or an AC/DC power conversion source. The PEM and system backplane include circuitry to enable a single backplane to be powered by two separate power supplies, thereby providing the system backplane and any connected logic cards with approximately twice as much power than could normally be provided by a single service point. To facilitate this capability, the PEM includes circuitry for detecting the power supplied by each of its power supply circuits and for automatically shutting down power supply to the system backplane in the event of a detected failure condition, such as an undervoltage condition on one or both of the power supplies, and a voltage differential between the power supplies that exceeds a predetermined threshold. 
     The system and method also provides for the use of a second PEM that is used in situations requiring a redundant power supply system. In this configurations, two power supply circuits, one from each PEM, are used to supply power to each half of the system backplane, thereby forming two sets of power supply circuits. This is facilitated, in part, by connecting each set of power supply circuits together in a diode ORed manner, whereby adequate power will be provided to a given half of the system backplane as long as at least one of the power supply circuits in particular set is operating normally. 
     Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example and not limitations in the figures of the accompanying drawings, in which like references indicate similar elements, and in which: 
     FIG. 1 is a schematic diagram illustrating an embodiment of the present invention in which two power entry modules (PEMS) are used to redendantly supply power to a single system backplane with a split power plane; 
     FIG. 2 is an isometric view of a PEM in accord with the PEMs of FIG. 1; 
     FIG. 3 is a schematic diagram of a PEM illustrating internal circuitry for detecting failure conditions and automatically shutting down power supply to the system backplane upon detection of such conditions; 
     FIG. 4 is a schematic diagram illustrating a voltage differential detection circuit; 
     FIG. 5 is a schematic diagram illustrating an under-voltage detection circuit; and 
     FIG. 6 is a schematic diagram illustrating a circuit for activating a remote trip coil for shutting down power to the system backplane. 
    
    
     DETAILED DESCRIPTION 
     A split-backplane power supply scheme is described that enables telco switching equipment that requires large amounts of power to be used with existing power distribution panels in telco facilities. The split-backplane scheme enables a single switching device/system to be supplied concurrently from multiple power sources, thereby lowering the amperage requirement for each of the power sources. In order to implement this strategy, various detection circuits are described to ensure that undesired power conditions do not occur at the split-backplane. For example, an undesired power condition occurs if power is supplied to only one-half of a split-backplane, while the other half does not receive power. Under this situation, the transceiver circuitry of logic cards connected to the backplane may be damaged. 
     One embodiment of the invention is depicted in FIG.  1 . In this configuration, power is provided from a set of redundant battery power sources “A” and “B.” A single power source with multiple service points could be used, and the power sources could be batteries or other DC sources, such as AC-powered DC power supplies, as well as AC sources. Each service point provides up to 60 amps of current at −48 volts DC, corresponding to a current limit typically available at the distribution panels of many telco facilities. 
     Power from battery source A is received by a first DC power entry module (PEM), labeled “PEM A,” through a pair of terminal blocks  10  and  12 . Terminal blocks  10  and  12  preferably comprise 3-position, 75 amp rated terminal blocks. Similarly, power from battery source B is received by a second DC PEM labled “PEM B” through terminal blocks  14  and  16 . Each PEM includes a pair of substantially identical power supply conditioning circuits, wherein the conditioning circuits for PEM A are labeled “PEM-A 1 ” and “PEM-A 2 ,” and the conditioning circuits for PEM B are labeled “PEM-B 1 ” and “PEM-B 2 .” 
     The function provided by each of PEMS A and B is identical. Accordingly, the following will describe additional details of PEM A, which will be understood to also apply to PEM B, and the references corresponding to components of each of the PEMs is labeled with a suffix of “A” or “B” in FIG. 1, as appropriate. The −48 V from each of the entry points from power source A is routed to respective poles  18 A and  19 A of a double-pole 50 amp magnetic circuit breaker. The two poles on the circuit breaker are mechanically interlocked, forming an interlocked circuit breaker  21 A. Each of the poles of interlocked circuit breaker  20 A comprises a 50 amp series trip coil, while one of the poles includes an auxiliary switch  21 A. The other pole has a remote voltage trip coil, similar to a relay trip coil, the operation of which is explained below. Auxiliary switch  21 A is wired in series to the remote voltage coil so that the remote coil becomes de-energized once activated to trip. 
     The load side of each of circuit breaker poles  18 A and  20 A is connected to a respective EMI filter  22 A and  23 A, followed by respective “ORing” diodes  24 A and  25 A. The anode side of each of Oring diode  22 A,  23 A is connected to a respective “D-Sub” output connector  26 A,  27 A that provides output power to one-half side of a system backplane  28  via respective power cables  30 A and  31 A and connectors  32 A and  33 A. Preferably, each of connectors  26 A,  27 A,  32 A and  33 A provide multiple pins for power supply and signal feedback purposes, further details of which are provided below. 
     System backplane  28  supplies power to and couples signals to and from circuitry in sets of logic cards  34  and  36 , which are contained within an electronic equipment rack  38 , via backplane connectors  40  and  41 , and card connectors  42  and  43 . Logic cards  34  and  36  provide switching circuitry for performing telco switching functions. System blackplane  28  comprises a multilayer circuit board in which the power distribution routing is split into two halves, labled  44  and  46 , while the signal routing for connecting the circuitry of logic cards  34  and  36  are contiguous across the backplane. In addition, system backplane  28  includes fuses  48  and  50  to protect logic cards  34  and  36  for overcurrent conditions, and each of the logic cards includes protection circuitry for similar purposes (not shown). 
     PEM A comprises a first power source, while PEM B comprises a redundant power source. Accordingly, power routing circuitry is included in system backplane  28  and the PEMs to enable concurrent operation of the redundant power sources. In particular, this circuitry includes a pair of diodes  52  and  53  in system backplane  28  and ORing diodes  24 A,  24 B,  25 A and  25 B in the PEMs. The ORing diodes enable power to be supplied from the redundant power sources, whereby if one of the power sources failed, the other power source will still provide adequate power to system backplane  28 , and both PEMs A and B may be connected to system backplane  28  without affecting the operation of the other PEM. A single PEM can be used to supply power to system backplane  28  if redundancy is not required. 
     A detailed isometric drawing corresponding to an exemplary mechanical configuration of a PEM is shown in FIG. 2, with the suffixes of the reference numerals removed. Note that the mechanically interlocked circuit breaker  20  further includes an activation lever to enable someone to manual disable power from being delivered by the PEM. 
     There are various, problems associated with supplying a single backplane with power from multiple power sources. In the configuration of FIG. 1, a primary problem occurs if only one-half of the backplane is provided with power, while the other half is not. This scenario can occur, for example, if the battery feeds become inactive, power cables get disconnected, or one of the power planes fails in a shorted condition. The result of having power to only one half of the backplane is that the plug-in cards (e.g., cards  34  and  36 ) with power will be interfaced to the pluin cards without power via common connections on system backplane  28 . This may cause damage to transceivers and the interface logic on the cards. In order to prevent such occurences, the PEMS are designed to detect when the have inadequate input supply power, or their power output falls below an accepted range, whereupon power to both planes of system backplane  28  is immediately removed. 
     To address these problems, PEMs A and B include circuitry to detect under-voltage and voltage differential conditions, whereby if either an under-voltage or differential condition is sensed, both PEMs are automatically shut down to remove power from system backplane  28 . As shown in FIG. 3, these circuits are shown as a differential detection circuit  54  and an under-voltage detection circuit  56 . Further details of both circuits  54  and  56  are described below. 
     Each of differential detection circuit  54  and under-voltage detection circuit  56  receives a pair of input signals comprising a −48 volt A 1  sense signal  58  and a −48 volt A 2  sense signal  60 . −48 volt A 1  sense signal  58  is connecteed on system backplane  28  via a jumper  62  to the −48 volt power input provided by battery service A 1 , while −48 volt A 2  sense signal  60  is connected on the system backplane via a jumper  64  to the −48 volt power input provided by battery service A 2 . In addition, differential detection circuit  54  produces an output control signal  66  and under-voltage detection circuit  56  produces an output control signal  68  that are received by a trip coil drive circuit  70  to activate a remote trip coil  72  to trip interlocked circuit breaker  21 . 
     Each PEM also provides four discrete power supply voltages: Vee, 24V, Vdd, and 5V. Vee is generated by diode ORing −48 volt inputs A 1  and A 2 , as depicted by diodes  70  and  72  in the Figure. Vee is used to reference the circuitry to the lowest potential as well as providing a source voltage for generating the other power supply voltages. The 24V power supply (not shown in FIG.  3 ), is generated by regulating the circuit GND down to 24VDC above the Vee potential level. The 24V power supply preferably comprises a linear supply used to energize the remote trip coil. Normally, the power supply does not provide any output power. However, if a failure of one of 48V services A 1  or A 2  is detected at system backplane  28 , the 24V power supply provides  1 A of output power to remote trip coil  68  long enough (e.g., &lt;30 mS) to trip circuit breaker  21 . Further details of the 24V power supply circuit are described below. Vdd is a reference voltage supply that is 5V below the GND potential (i.e., a −5V supply). The 5V power supply is a reference supply voltage that is 5V above the Vee potential. 
     A schematic diagram of an exemplary circuit  74  corresponding to differential voltage detection circuit  54  is shown in FIG.  4 . Circuit  74  receives 48V A 1  sense signal  58  and −48V A 2  sense signal  60  as inputs. Each of the input signals are tied to a common ground through a resistor R 1 , and are connected in series with a resistor R 2 . Preferably, R 1  comprises a pair of 2.2K ohm resistors in parallel, and R 2  comprises a pair of 470 ohm resistors in series. The inputs are connected to opposite sides of a bridge circuit comprising four diodes D 1 , D 2 , D 3 , and D 4 . The bridge circuit further includes an opto-isolator  76 , a zener reference  78 , a 1K resistor R 2 , and a 1 uF capacitor C,. Preferably, zener reference  78  comprises a Linear Technologies LT1431 programmable reference. The output of opto-isolator  76  is connected to output signal  66 , which is coupled to Vee through a 10k resistor R 4 , and includes a filter comprising a 10K resistor R 5  connected in series and a 0.1 uF capacitor C 2  tied between output signal  66  and Vee. 
     Circuit  74  operates in the following manner. Zener reference  78  is set to a predetermined reference level that is a few volts below the desired voltage differential set point. For example, for a 26 volt differential set point, zener reference  78  should be set to 20.3 volts. If a difference between the voltage levels of the −48V A 1  and A 2  sense signals exceeds the predetermined reference level, opto-isolator  76  is activated, creating a drive current on output signal  66 , which will activate trip coil  72  through the use of trip coil drive circuit  70 , as explained below. 
     An exemplary circuit  80  for sensing under-voltage conditions and for preventing such conditions from being detected during normal power-up and power-down conditions in accord with under-voltage detection circuit  56  is shown in FIG.  5 . The primary sensing elements of circuit  80  comprise a plurality of hysteresis-type comparators  82 ,  84 ,  86 ,  88 ,  90 ,  92 , and  94 , which are preferably provided by means of quad comparators  96  and  98 . Each of quad comparators  96  and  98  include a reference voltage output that is preferably set at 1.22 volts (Vdd) (i.e., relative to Vdd, which is set at −5 volts nominally). The 1.22 (Vdd) reference voltage is received at the non-inverting inputs of comparators  82 ,  84 ,  90 ,  92 , and  94 , and the inverting inputs of comparators  86  and  88 . Exemplary quad comparators that may be used in circuit  80  include an LTC1444 quad comparator manufactured by Linear Technologies. 
     Circuit  80  includes multiple diodes for signal conditioning purposes, including diodes D 5 , D 6 , D 7 , D 8 , D 9 , D 10 , D 11 , D 12 , D 13 , D 14 , and D 15 , and further includes resistors R 6 , R 7 , R 8 , R 9 , R 10 , R 11 , R 12 , R 13 , R 14 , R 15 , R, 16 , R 17 , R 18 , R 19 , R 20 , R 21 , and R 22 . Preferably, resistors R 6  and R 7  are 86.6 Kohm, resistors R 8 , R., and R 14  are 90.9 Kohm, resistors R 10 , R 11 , R 12 , R 13 , R 5 , R 17 , R 19 , R 21 , and R 22  are 10 Kohm, resistors R 16  and R 18  are 2 Mohms, and resistor R 20  is 5 Kohm. As will be recognized by those skilled in the art, resistors R 10 , R 11 , R 12 , and R 13  comprise a voltage divider network, while diodes D 9 , D 10 , D 11 , and D 12  comprise a set of clamping diodes. 
     Circuit  80  operates in the following manner. Under normal operating conditions, i.e., when the voltage level −48V A 1  and A 2  sense signals is approximately −48V, the voltage appearing at the inverting terminals of comparators  82 ,  84 , and  94  is approximately Vdd, or 0V (Vdd). Accordingly, the output of each of these comparators is set such that the output of an opto-isolator  100  is deactivated under normal conditions. In contrast, if either of −48V A 1  and/or A 2  sense signals falls below a threshold voltage level of approximately −36.5 V, the voltage level at the inverting terminals of comparators  82  and/or  84 , as appropriate, will exceed the 1.22 V (Vdd) reference voltage, and the output of one or both of the comparators will be set such that the output of opto-isolator  100  is activated, thereby setting a trip condition on output signal  68 . 
     It is desired to disable sensing of under-voltage condition during normal power-up and power-down operations. During power-up, the voltage senses on A 1  and A 2  will be less than the threshold voltage level, setting the outputs of comparators  82  and  84 , which are commonly tied together. This would normally cause a trip condition. However, note that the inverting input of comparator  94  is is tied to Vdd through a 47 uF capacitor C 3 , and tied to ground through a 10K resistor R 22 , and the output of comparator  94  is tied to the control side of opto-isolator  100 . As a result, when the PEM is powered up, capacitor C 3  discharges for approximately six seconds, thereby preventing opto-isolator  100  from being activated. If only one of the PEM&#39;s −48V DC outputs is enabled during a power-up condition, this condition will be detected by differential detection circuit  54 . 
     Circuit  80  also disables under-voltage sensing during power-down conditions. Normally, this will not be necessary, since a powering down a PEM will merely comprise opening a DC breaker, thereby shutting off input power to the PEM, which will immediately remove power received by logic cards  34  and  36 . However, in the case of an AC source, a trip condition might occur upon shutdown. This condition is prevented by the combination of comparators  86 ,  88 , and  90 . Since resistors R 8  and R 9  have higher resistances than resistors R 6  and R 7  (90.9K vs. 85.6K), comparators  86  and  88  will detect an under-voltage conditions at a higher voltage level than comparators  82  and  84 . The outputs of comparators  86  and  88  are commonly tied to the input of comparator  90 , while the output of comparator  90  is tied to the control side of opto-isolator  100 . As a result, during a power-down condition, the output of comparator  90  will be set so as to deactivate the undervoltage sensing provided by comparators  82  and  84 . 
     An exemplary circuit  102  that may be implemented for trip coil drive circuit  70  is shown in FIG.  6 . Circuit  102  comprises an operational amplifier (op amp)  104 , transistors  106  and  108 , and a diode D 15 . The circuit additionally includes a plurality of resistors, including resistors R 23  (1 Kohm), R 24  (470 ohm), R 25  (10 K ohm), R 26  (940 ohm), and R 27  (10 Kohm). 
     Circuit  102  operates as follows. An input signal, corresponding to output signals  66  and  68  is received at the non-inverting input of op amp  104 , while the inverting input of op amp  104  is tied to Vee through 1 K resistors R 23 . Note that each of signals  66  and  68  is produced by respective opto-isolators  76  and  100 . As a result, when the opto-isolators are deactivated (i.e., a non-trip condition), signals  66  and  68  comprise a high impedance, and the output of op amp  104  is set such that transistor  106  is not turned on. This will also shut off transistor  108 , causing the low side of remote trip coil  72  to float, thereby disabling the remote trip coil. In contrast, if a trip condition appears on either or both of signals  66  and  68 , op amp  104  produces an output that activates transistor  106 , which then activates transistor  108 , causing the low side of remote trip coil  72  to be connected to Vee, thereby producing a voltage differential across remote trip coil  72 , which will activate the trip coil, causing interlocked circuit breaker  20 A to be tripped. Upon being tripped, auxiliary switch  21 A with be opened, thereby deactivating remote trip coil  72 . 
     Numerous types of circuits commonly used to activate relay coils or other devices with similar loads may be used in place of circuit  102 . For instance, remote trip coil  72  coil be activated by a relay circuit, or a power MOSFET or similar type of high-power solid-state switch. 
     In the foregoing specification, the invention has been described with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention a set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.