Abstract:
An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates generally to integrated circuit architecture, and more particularly to a re-configurable integrated circuit architecture that uses analog and digital building blocks to build a mixed-mode integrated system. 
       BACKGROUND 
       [0002]    Mixed mode electronic systems that use analog and digital building blocks in the industry may use programmable logic devices (PLD), complex programmable logic devices (CPLD), and/or field programmable gate arrays (FPGA) to implement the digital functional portion of the mixed mode electronic system by programming the configuration switches in the programmable devices. However, the analog functions of the mixed mode electronic system, which are interfacing, controlling or being controlled by the digital functions, usually are specific and are not re-configurable. Moreover, these analog functions are not suitable to be integrated on the same silicon with digital programmable devices because of the noise that the digital portion will inject into the common substrate. Thus, currently-existing programmable analog functions are expensive, specific to limited applications, and are mostly used for prototyping applications. Presently, existing programmable mixed mode integrated devices use pre-defined or pre-configured analog functions combined with a routing matrix that is suitable for digital signals to route the analog signals, and a digital programmable array similar to a PLD, FPGA, DSP, or Micro Controller function. The routing matrix uses CMOS pass gates to route and connect the analog signals between the analog functions. These metal oxide semiconductor (CMOS) pass gates, which are not suitable for passing analog signals with different frequencies and amplitudes limit the operating range of the analog functions and will also make it more prone to noise. 
         [0003]    Therefore, there is a need in the art for a programmable mixed mode architecture that integrates analog and digital functions and resolves the noise issue injected by the digital portion. 
       SUMMARY 
       [0004]    The present invention provides a new way of routing, mixing, or connecting the analog signal without limiting their performance. It also makes the analog functions programmable and re-configurable to various analog functions. 
         [0005]    In one aspect of the invention, a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, an analog interconnect array, and a programmable digital portion. The input cells are configured to program various analog functions. The output cells are configured to provide digital and/or analog outputs corresponding to the programmed analog functions. The interconnect array mixes and directs the programmed analog functions into signals indicative of the analog functions. The array selectively provides the signals to the plurality of analog output cells. In one embodiment, the programmable digital portion includes a programmable logic device, Field programmable Gate array, macrocells, and a Phase Lock Loop (PLL). 
         [0006]    In another aspect of the invention, the analog portion includes a plurality of analog input cells, a plurality of analog output cells, and a current sensing array. The analog input cells provide a plurality of predefined analog functions. The analog output cells generate digital and/or analog signals corresponding to the predefined analog functions. The current sensing array converts predefined analog functions from the plurality of analog input cells into current signal, mixes and directs the current signal, converts the current signal into voltage signal, and selectively provides the voltage signal to the plurality of analog output cells. 
         [0007]    Other features and advantages of the present invention should be apparent from the following description, which illustrates, by way of example, the principles of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  illustrates a mixed-mode integrated circuit architecture in accordance with an exemplary embodiment of the present invention. 
           [0009]      FIG. 2  illustrates a programmable analog current sensing interconnect array according to an exemplary embodiment of the present invention. 
           [0010]      FIG. 3  is a schematic diagram of a re-configurable analog input cell according to an embodiment of the present invention. 
           [0011]      FIG. 4  is a schematic diagram of a programmable analog output cell according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    In recognition of the above-stated problems associated with existing mixed-mode integrated circuit architectures, embodiments for re-configurable analog devices and functions are described. In particular, following exemplary embodiments integrate digital and analog functions with re-configurable digital and analog arrays into a mixed-mode integrated circuit architecture. The analog functions include analog input cells, analog output cells, and an analog interconnect current sensing matrix. Furthermore, the mixed mode architecture enables integration of various mixed-mode systems without separating analog circuits/functions from digital functions. Consequently, for purposes of illustration and not for purposes of limitation, the exemplary embodiments of the invention are described in a manner consistent with such use, though clearly the invention is not so limited. 
         [0013]    A mixed-mode integrated circuit architecture  100  in accordance with an exemplary embodiment of the present invention is illustrated in  FIG. 1 . In the exemplary embodiment, the mixed-mode architecture  100  includes an analog portion  110  and a digital portion  160 . The analog portion  110  includes four re-configurable analog input cells  112 - 118 , four programmable analog output cells  120 - 126 , and a programmable analog interconnect current sensing array  150 . However, the analog portion  110  may be configured with any appropriate number of cells and/or current sensing arrays to implement the mixed-mode circuit in a similar design. The re-configurable analog input cell  112 - 118  enables programming of several analog functions using switches. The programmable analog output cell  120 - 126  processes the current output signal of the interconnect current sensing array  150  to a digital signal appropriate for interfacing with the digital array  162 . 
         [0014]    The analog portion  110  further includes programmable voltage reference generator  102  that generates voltage references, which are accessible to the re-configurable input/output cells  112 - 126  and direct analog input ports  148  coupled to the analog interconnect current sensing array  150 . The direct analog input ports  148  are used to input analog signals that do not require processing by the analog input cells  112 - 118 . 
         [0015]    The digital portion  160  may include a programmable logic array  162 , a phase lock loop (PLL)  166 , a clock generator  168 , and macro-cells  164  with digital inputs/outputs that meet various interfacing standards. In the exemplary embodiment, the programmable logic array  162  includes 44 input elements ( 22  non-inverted and 22 inverted input signals). Eight of the input elements are coupled to the analog output cells  120 - 126 , and the other 36 input elements are coupled to 18 external digital input pins. However, the programmable logic array  162  may be implemented using the architecture similar to the conventional architecture of programmable logic devices (PLD), field programmable gate arrays (FPGA), and/or other similar architectures. PLL  166  receives a reference frequency from an oscillator that is multiplied and phase-lock looped by the PLL block to provide high clock frequency and synchronization of the signals in the macro-cells  164 . In some embodiments, the PLL  166  may be multiplexed with an external clock in the clock generator  168  to enable operation of each output macro-cell  164  from a different clock source if desired. The clock generator  168  includes clock drivers and a multiplexer. The drivers receive the PLL output and drive the macrocells  164  of the programmable logic array  162 . The multiplexer enables receipt of the clock signal from an external source by bypassing the PLL  166 . 
         [0016]    In an alternative embodiment, the programmable analog interconnect current sensing array  150  of the analog portion  110  is configured to operate with conventional pre-defined input and output cells. However, unlike the conventional design of the array, the interconnect array  150  of the alternative embodiment converts the output of the input cell from voltage to current so that crosstalk and noise coupling between different analog signals from different input cells are substantially reduced. 
         [0017]    In a further embodiment, the analog input cells  112 - 118  and the analog output cells  120 - 126  of the analog portion operate in conjunction with a conventional design of the interconnect array. Hence, the output signal from the input cell is not converted from voltage to current, and the input signal to the output cell need not be converted to voltage. Although this configuration may introduce some crosstalk and noise coupling, the advantages of the programmability of the input and output cells can be realized. 
         [0018]    A programmable analog current sensing interconnect array  150  according to an exemplary embodiment of the present invention is shown in  FIG. 2 . The interconnect array  150  enables connection of the analog input cells  112 - 118  to the analog output cells  120 - 126 . Signals from the analog input cells  112 - 118  representing the programmed analog functions are converted to current and directed to the desired output cells by programming the volatile/non-volatile configuration switches of the interconnect array  150 . The processed signals are then transmitted to the analog output cell(s)  120 - 126  through an operational amplifier  210 ,  212 , or  214  that acts as a current-to-voltage converter. 
         [0019]    In the exemplary embodiment, a voltage-to-current converter circuit  202  in the interconnect array  150  converts the output signal from input cell A into current. This voltage-to-current converter circuit  202  includes operational amplifiers and transistor switches. Voltage-to-current converter  204  operates in similar manner with input cell B. Thus, by converting the analog signals from voltage into current, the analog interconnect array  150  substantially reduces crosstalk and noise coupling between different analog signals from different analog input cells. 
         [0020]    The array  150  may also be used as a mixer for the different analog circuits/signals generated from two or more re-configurable analog input cells by operating the analog interconnect array  150  in a current mode. For example, by turning on both switches SW 1  and SW 2  in the same column as output cell A, the analog signals generated from the two re-configurable input cells (i.e., input cell A and input cell B) are mixed in current before being passed to the selected analog output cell (i.e., output cell A). The array may further be used as a splitter by directing a current signal into more than one output cell. For example, by turning on both switches SW 1  and SW 3 , the analog signal generated from input cell A is directed into both output cell A and output cell B. 
         [0021]    The analog interconnect array  150  also allows analog inputs that require no processing by the input cell to enter the analog array  150  through a voltage-to-current converter circuit. The converted analog inputs may then be mixed with other analog signals and directed to one or more analog output cells. 
         [0022]      FIG. 3  is a schematic diagram of a re-configurable analog input cell  300  according to an embodiment of the present invention. In the illustrated embodiment, the input cell  300  includes transistors SW 14 , SW 15 , capacitors C 1 , C 2 , adjustable resistors AR 1 -AR 4 , configuration switches SW 1 -SW 17 , and an operational amplifier  304 . The configuration switches SW 1 -SW 17  are controlled by volatile/non-volatile memory cells. The configuration switches may be selected or deselected to configure the input cell into desired analog functions. 
         [0023]    Table 1 shows the configuration switches SW 1 -SW 17  that may be turned on to generate the listed analog functions in accordance with an exemplary embodiment. For example, a unity gain non-inverting amplifier may be configured by turning on switches SW 2  an SW 14 . Other analog circuits/functions, such as an integrator, a difference amplifier, a differentiator, a comparator, a reference voltage generator, configurable/adjustable gain amplifier, and a current-to-voltage amplifier, may also be configured by turning on an appropriate combination of switches as listed in Table 1. The list, however, is provided for illustrative purposes only. Other circuits/functions can be generated using different combinations of configuration switches. For example, switches SW 14  and SW 15  may also be used to generate a sample-and-hold circuit. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Re-configurable Analog Functions 
               
             
          
           
               
                 Functions 
                 Configuration Switches 
               
               
                   
               
               
                 Unity Gain Amplifier 
                 SW2, SW15 
               
               
                 Integrator 
                 SW3, SW4, SW6, SW8, SW10 
               
               
                 Difference 
                 SW4, SW6, SW9, SW10, SW11, SW7 
               
               
                 Differentiator 
                 SW4, SW5, SW8, SW10 
               
               
                 Comparator 
                 SW14, SW15 
               
               
                 Voltage Reference 
                 SW2, SW13 
               
               
                 Gain Amplifier 
                 SW4, SW15, SW16 
               
               
                 Current-to-Voltage Converter 
                 SW4, SW14, SW17 
               
               
                   
               
             
          
         
       
     
         [0024]    In the illustrated embodiment of  FIG. 3 , the output  310  of an analog input cell  300  is coupled to the interconnect array  150  through a voltage-to-current converter  312 . However, the output  310  of the analog input cell  300  may also be coupled directly to the interconnection matrix  404  of the adjacent analog output cell  400  (i.e., bypass path to the output cell) and/or to the input multiplexer  302  of another analog input cell (i.e., bypass path to another input cell). Hence, by providing a bypass path from the input cell to the output cell, a direct analog input cell function translation may be made to the output without going through the analog interconnect array  150 . Further, by providing a bypass path from the output of an input cell to the input of another input cell, programmability of the analog input cell  300  may be enhanced by cascading different or similar functional blocks. For example, if input cell A is configured as a gain amplifier with a gain of 10, and input cell B is configured also as a gain amplifier with a gain of 10, by cascading the two input cells, a gain amplifier with a gain of 100 can be achieved. Other functions such as filters may also be configured by cascading input cells 
         [0025]      FIG. 4  is a schematic diagram of a programmable analog output cell  400  according to an embodiment of the invention. In the illustrated embodiment, the output cell  400  includes a current-to-voltage converter  402 , a 2×2 interconnect matrix  404 , a 2:2 multiplexer  410 , a 10:1 multiplexer  406 , a 2:1 multiplexer  408 , and an output comparator  414 . The 2×2 interconnect matrix  404  directs the input signal (e.g., signal from the interconnect array  150  or directly from the input cell through the bypass path) to the analog output  416  and/or to the input multiplexer  410  of the output comparator  414 . The 10:1 multiplexer  406  directs one of the 10 reference values into the 2:1 multiplexer  408 , which is used to pass a reference voltage or the output of the operational amplifier  402  to the output comparator  414 . The 2×2 multiplexer  410  directs the selected reference voltage and the selected input signal to the output comparator  414 . Furthermore, the comparator  414  converts the analog signal into digital signal for interface with a digital array  162 . The output comparator  414 , in combination with the 2:2 multiplexer  410 , can compare any combination between the operational amplifier output  420 , the selected reference voltage  422 , and the output  424  of the adjacent input cell. It should also be noted that the output cell  400  allows the input signal to be outputted as analog signal through an op-amp  412  to the analog output  416 . This provides the architecture with the flexibility of being configured as providing analog functions and/or analog functions interfacing with digital functions. Sizes of the matrix and the multiplexers used in the exemplary embodiment are for illustrative purposes only. Hence, the sizes may be adjusted appropriately to configure the interface between the analog portion  110  and the digital portion  160  of the mixed-mode architecture  100 . 
         [0026]    There has been disclosed herein embodiments for re-configurable analog devices and functions used in a mixed-mode integrated circuit architecture  100 . The analog devices include re-configurable analog input cells  112 - 118 , programmable analog output cells  120 - 126 , and a programmable interconnect array  150 . The input cells  112 - 118  enable programming of a desired analog function using configuration switches SW 1 -SW 17 . The interconnect array  150  converts the output signal of the analog input cells  112 - 118  from voltage to current, and processes the converted signal(s) by mixing/splitting. Once the signal(s) has been processed, the interconnect array  150  converts the signal(s) from current to voltage, and directs the signal(s) to the output cell(s)  120 - 126 . The output cells  120 - 126  enable routing of the signals to a comparator  414  for conversion to digital signal. 
         [0027]    While specific embodiments of the invention have been illustrated and described, such descriptions have been for purposes of illustration only and not by way of limitation. The present invention should therefore not be seen as limited to the particular embodiment described herein, but rather, it should be understood that the present invention has wide applicability with respect to mixed-mode integrated circuit architecture generally. Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the embodiments may be practiced without some of these specific details. In other instances, well-known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present invention. For example, although the details for implementing the programmable digital array are not provided herein, it is understood that conventional programmable arrays, such as programmable logic devices (PLD), field programmable gate arrays (FPGA), or even microprocessors, may be used. Accordingly, all modifications, variations, or equivalent arrangements and implementations that are within the scope of the attached claims should therefore be considered within the scope of the invention.