Abstract:
A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V t  &#39; ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V t1  ions over the entire device.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to manufacture of a MOSFET device and more particularly to improved channel doping. 
     2. Description of Related Art 
     For circuit performance optimization, a different threshold voltage V t  or different channel doping is required. In general, one extra mask is required to implement such circuit performance optimization. 
     FIG. 1A shows a prior art device 100 with a Vt&#39; mask 28 and an active area 34 with a polysilicon gate 35. FIG. 1B shows a prior art device 200 with an active area 37 with another polysilicon gate 36. In FIGS. 1A and 1B an aspect of a typical prior art process for getting a different V t  is illustrated. Device 200 is a normal device with threshold voltage V t1  and device 100 is another device with a threshold voltage V t2 , V t1  ≠V t2 . In general device 100 needs an extra V t  &#39; mask 28 and ion implantation to get a different V t  as provided with device 200. 
     FIGS. 3A to 3H show cross sectional views of a prior art process of fabrication of a semiconductor device on a silicon substrate 10 in which a P-well 12 and an N-well 14 in an N or P-sub 11 have been formed by a conventional process, with only the P-well 12 shown in FIGS. 3F and 3H. 
     Referring to FIGS. 3A and 3B, a blanket silicon dioxide (Pad oxide) layer 16 is deposited over the entire device followed by a silicon nitride (Si 3  N 4 ) layer (18, 18&#39;, 18&#34; which silicon nitride layer is patterned into Si 3  N 4  structures 18, 18&#39;, 18&#34; to be used as a mask in forming active layer patterning. 
     In FIGS. 3C and 3D, a photoresist mask 20 has been formed over the N-well 14 portions of the product of FIGS. 3A and 3B, and then a NMOS field implantation of ions 22 is made in the P-well 12 producing dopant 13 in the surface of the P-well 12 aside from the Si 3  N 4  structures 18 and 18&#39;. 
     In FIGS. 3E and 3F, a device similar to that in FIGS. 3C and 3D is shown with a slightly different scale, after the photoresist mask 20 has been removed. A field oxidation process is performed producing FOX structures 25, 25&#39;, 25&#34; followed by stripping of the remaining portions of the silicon nitride layer 18, 18&#39;, 18&#34; on the surface of the device. Then a V t1  blanket ion implantation with ions 24 is performed producing dopant 15 in the surface of the P-well 12 between the FOX structures 25, 25&#39;, 25&#34;. There are P-regions 27 beneath FOX structures 25, 25&#39;, 25&#34; formed during ion implantation 22 and field oxidation step. 
     In FIGS. 3G and 3H, the product of FIGS. 3E and 3F is covered with a V t  &#39; photoresist mask 28 on the right side leaving the space between one pair of FOX structures 25, 25&#39; exposed and the other space between FOX structures 25&#39;, 25&#34; covered. The exposed region between FOX structures 25 and 25&#39; is then implanted with a V t  &#39; ion implant of ions 26 yielding a V t  dose of ions 17 where V t2  =V t1  +V t  &#39;, which is greater than V t1  which is the value for the ions 15 under the second photoresist layer. 
     The photoresist mask 28 is then removed. Then the conventional process is followed including the polysilicon gate CMOS process, PAD oxide 16 is removed, gate oxidation, polysilicon gate definition, source/drain implant and backend process contact, metallization, passivation, etc. as is well known by those skilled in the art. 
     FIGS. 4A-4C show cross sectional views of another prior art process of fabrication of another semiconductor device. In FIGS. 4A and 4B, a P-well 12 and an N-well 14 have been formed by a conventional process, whereas in FIG. 4C, the N-well is absent from the view which is of larger scale. 
     FIG. 4A shows a substrate 10 with an N or P-sub 11, a P-well 12 and an N-well 14 formed by a conventional process and a field oxidation process has been performed leaving FOX structures 25, 25&#39;, 25&#34; and 25&#34;&#39;. The structure is covered with gate oxide layer 16 between the FOX structures 25, 25&#39;, 25&#34; and 25&#34;&#39;. 
     In FIG. 4B, a photoresist mask 31 has been formed over the N-well 14 portions of the product of FIG. 4A, and then a field implantation of B11 ions 29 at between about 120 keV and 200 keV is made into the P-well 12 leaving a dose of ions 27 under FOX structures 25, 25&#39; and part of FOX structure 25&#34; and ions 35 between FOX structures 25 and 25&#39; and between structures 25&#39; and 25&#34;. 
     In FIG. 4C, the N-well 14 is absent from the view which is of a larger scale with the thickness retained low for convenience of illustration. The product of FIG. 4C has a V t1  blanket ion implantation 15 Performed thereon. Next the device in FIG. 4C is covered with a V. t  photoresist 32 on the right side leaving the space between one pair of FOX structures 25 and 25&#39; exposed and the other space between FOX structures 25&#39; and 25&#34; covered. The exposed region is then implanted with a V t  &#39;ion implant of ions 30 yielding a V t  dose of ions 15 and 17 where V t  =V t1  +V t  &#39;, which is greater than V t1  which is the value under the second photoresist layer 32 between FOX structures 25&#39; and 25&#34;. 
     The photoresist mask 32 is then removed, leaving the silicon dioxide gate oxide layer 16 above the region of P-well 12 containing Vt&#39; ions 15 between FOX regions 25&#39; and 25&#34;. 
     The photoresist mask 32 is then removed. Then the conventional process is followed including the polysilicon gate CMOS process, PAD oxide 16 is removed, gate oxidation, polysilicon gate definition, source/drain implant and backend process contact, metallization, passivation, etc. as is well known by those skilled in the art. 
     SUMMARY OF THE INVENTION 
     An object of this invention, is to obtain different threshold voltages V T  with a process which does not include the extra masking step of the prior art to provide a process which is simple and cost effective. 
     A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation and ion implantation of V t  &#39; ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V t1  ions over the entire device. 
     Preferably, the V t  &#39; ion implant dopant selected from the group consisting of B 11  and BF 2  is applied at a range of energies from about 10 keV to about 80 keV is possible with a range of doses from about 5×10E11 cm -2  to about 5×10E12 cm -2 . 
     Preferably, the V t1  ion implant dopant selected from the group consisting of B 11  and BF 2  is applied at a range of energies from about 10 keV to about 80 keV, with a range of doses from about 8×10E11 cm -2  to about 5×10E12 cm -2 . 
     Preferably, the V t1  ion implant dopant selected from the group consisting of P 31  and As+ is applied at a range of energies from about 30 keV to about 120 keV, with a range of doses from about 5×10E11 cm -2  to about 5×10E12. 
     Preferably, the field implant comprises B 11  dopant is applied at a range of energies from about 120 keV to about 200 keV. 
     It is further preferred that the mask is formed over a portion of the separate region leaving the periphery of the one separate region exposed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which: 
     FIG. 1A shows a prior art device with a Vt&#39; mask and an active area with a polysilicon gate. 
     FIG. 1B shows a prior art device 200 with an active area with another polysilicon gate. 
     FIGS. 2A and 2B show devices in accordance with this invention including a semiconductor substrate with a field implant mask (or Vt&#39; mask) and an active area with a polysilicon gate. 
     FIGS. 3A to 3H show cross sectional views of a prior art process of fabrication of a semiconductor device on a silicon substrate in which a P-well and an N-well in an N or P-sub have been formed by a conventional process, with only the P-well shown in FIGS. 3E, 3F, 3G and 3H. 
     FIGS. 4A-4C show cross sectional views of another prior art process of fabrication of another semiconductor device. 
     FIGS. 5A-5C show cross sectional views of a process in accordance with this invention of fabrication of another semiconductor device on a silicon substrate. 
     FIG. 6A shows a polysilicon gate over an active area with a source S and a drain D. 
     FIG. 6B shows the layout in accordance with this invention including a field implant mask smaller than the active area by the dimension δ. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     With the process changes and layout modifications in accordance with this invention, different threshold voltages V T  are achieved without the extra masking step of the prior art. Accordingly the process is simplified and cost effective. 
     The field implant mask (such as mask 63 in FIG. 5B, described below) is under sized to address the field leakage issue. The active edge should be covered by field implantation, otherwise there would be a leakage path passing through the field edge without covering the field implant region (such as FIG. 6A described below). 
     FIGS. 2A and 2B show devices in accordance with this invention including a semiconductor substrate with a field implant mask (or Vt&#39; mask) and an active area with a polysilicon gate. 
     FIGS. 2A shows a device 40 including a semiconductor substrate with a different field implant mask 63 (or Vt&#39; mask) as described above in connection with FIG. 1A and an active area 64 with a polysilicon gate 68. 
     FIG. 2B shows a device 140 including a semiconductor substrate without a field implant mask (or Vt&#39; mask) and an active area 67 with a polysilicon gate 66. 
     FIGS. 5A-5C show cross sectional views of a process in accordance with this invention of fabrication of another semiconductor device on a silicon substrate 40 in which a P-well 42 and an N-well 44 in an N or P-sub 41, etc. (any type of semiconductor substrate is satisfactory) have been formed by a conventional process, with only the P-well 42 shown in FIGS. 5B and 5C. P-well 42 and an N-well 44 were formed previously by a conventional process. In FIG. 5C, the N- well 44 is excluded from view for convenience of illustration since the scale of FIG. 5C is enlarged with comparison to FIGS. 5A and 5B. The same Vt1 implant is made into the N-Well active region as in prior art FIGS. 3A to 3H and 4A to 4C. 
     A field oxidation was previously performed leaving FOX structures 55, 55&#39;, 55&#34; and 55&#34;&#34; as shown in FIG. 5A. In the region 70 in the P-well 42 between one pair of FOX structures 55 and 55&#39;, the surface of the silicon dioxide (Pad oxide) 46 is exposed and in another region 72 in the P-well 42 between FOX structures 55&#39; and 55&#34; is mostly covered by mask 63. 
     In FIG. 5B, NMOS photoresist mask 63 has been formed over the N-well 14 portions of the product of FIG. 5A between one pair of FOX structures 55&#34; and 55&#34;&#34;. In addition, unlike FIG. 4B a supplemental photoresist mask 63&#39; comprising a &#34;V t  &#39;&#34; photoresist mask is formed above the right side of the P-well 42. In the region 70 in the P-well 42 between one pair of FOX structures 55 and 55&#39;, the surface of the gate oxide 46 is exposed and in another region 72 in the P-well 42 between FOX structures 55&#39; and 55&#34; is mostly covered by mask 63. Since the mask 63 is also formed over a portion of the P-well 42, it forms a different threshold device. For example, referring to FIGS. 2A and 2B, device 72 receives a V t1  implant and device 70 receives the combination of a V t1  implant and V t  &#39; implant, so the threshold V t  is different. 
     Then a field implantation of B 11  dopant ions 51 at 120 keV to about 200 keV is made into regions 70 and 72 in the P-well 42. A dose of ions 57 is formed under the FOX regions 55, 55&#39; and 55&#34;, where they are exposed and the ions in regions 70 and 72 reach deep into the P-well 42 in the active region due to the high energy. Ions 65 are injected deep in the active region due to the higher energy of a field implantation 51. In this process, the exposed region is implanted with a threshold implantation V t  &#39; of dopant 52. 
     Note that it is critical that the mask 63 over the region 72 the P-well 42 is undersized compared to the masks employed in FIGS. 3G and 3H and FIG. 4C with the two mask process to permit the P- field to stay under the FOX region to prevent leakage. There are P- regions 57 beneath FOX structures 55, 55&#39;, 55&#34; formed during ion implantation Vt&#39; 51 because 120 keV to about 200 keV can have an extend through the field oxide structures. 
     Following the field implantation, a V t  &#39; dopant 52 is applied at a preferred dose of 2×10E12 cm -2  of B 11  or BF 2  dopant at a preferred energy of 20 or 60 keV, respectively, to provide a far higher level of doping. A range of energies from about 10 keV to about 80 keV is possible. A range of doses from about 5×10E11 cm -2  to about 5×10E12 cm -2  is possible. 
     In FIG. 5C, the product of FIG. 5B has a V t1  blanket ion implantation of ions 53 performed thereon, again yielding two levels of threshold voltage. The V t1  blanket dopant is applied at a preferred dose of about 3.5×10E12 cm -2  of BF 2  dopant at a preferred energy of 60 keV to provide a far higher level of doping. A range of energies from about 10 keV to about 80 keV is possible. A range of doses from about 8×10E11 cm -2  to about 5×10E12 cm -2  is possible. An alternative V t1  dopant 53 is P 31  or As+ with a range of energies from about 30 keV to about 120 keV and a range of doses from about 5×10E11 cm -2  to about 5×10E12. In the region 70 there is a V t  dose of ions where V t  =V t1  +V.sub. t &#39;, which is different from V t1 , which is the value in region 72 which was under the supplemental photoresist mask 63 with the single masking layer in FIG. 5B. 
     FIG. 6A shows a polysilicon gate 66 over an active area 67 with a source S and a drain D. A FOX region 68 is juxtaposed with the source. The NMOS field implantation is performed to form a P- layer under the P- well field oxide to increase the NMOS field threshold and to prevent the surface inversion from causing a leakage path illustrated by &#34;a&#34; in FIG. 6A. 
     FIG. 6B shows the layout in accordance with this invention including a field implant mask 63 smaller than the active area 64 by the dimension δ. This small mask design is defined herein as an Active Under Size Mask (e.g. 0.3 μm≦δ1.0 μm) to mask the low threshold area, like FIG. 5B. 
     After the threshold implant, the steps of the standard manufacturing process follows. 
     The prior art process require two masking layers for the NMOS field mask and the V t  &#39; mask. On the other hand, the instant invention employs a single masking layer. Because of the reduction in the number of processing steps, the process of this invention is simple and cost effective. 
     An analogous product comprising a PMOS device with an N-well is equally suitable, manufactured in accordance with the process of this invention. 
     In summary, referring to FIG. 5B it is critical that the mask 63 over the region 72 the P-well 42 is undersized as compared to the masks employed in FIGS. 3G and 3H and FIG. 4C with the two mask process. The undersized mask permits merging the P-well field mask and Vt&#39; mask. 
     While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.