Abstract:
An LDO regulator is arranged to provide regulation with a pass device, a cascode device, a level shifter, an error amplifier, and a tracking voltage divider. The error amplifier is arranged to sense the output voltage and provide an error signal to the pass device via the level shifter. The level shifter changes the DC level of the error signal such that the pass device is isolated from damaging voltages. The cascode device is arranged to increase the impedance between the output node and the pass transistor such that the LDO regulator can sustain input voltages that exceed process limits without damage. The cascode device is biased by the tracking voltage divider. The tracking voltage divider adjusts the biasing to the cascode device such that a decreased input voltages result in lower impedance, and increased input voltages result in higher impedance.

Description:
FIELD OF THE INVENTION 
     The present invention is generally related to voltage regulators. More particularly, the present invention is related to a low drop-out voltage regulator that is tolerant to input voltages that exceed the maximum permissible voltage of the individual pass transistors. 
     BACKGROUND OF THE INVENTION 
     Voltage regulators are often used to provide a relatively constant voltage source to other electronic circuits. Some regulators are limited in their effectiveness in a particular application. For example, some regulators have a high “drop-out” voltage. A “drop-out” voltage is the minimum voltage difference between the input voltage and the output voltage that is necessary to maintain proper regulation. Large drop-out voltages result in wasted power, and raise the minimum power supply requirements for maintaining regulation. 
     A low drop-out regulator (hereinafter referred to as an “LDO regulator”) is useful in applications where it is desired to maintain a regulated voltage that is sufficiently close to the input voltage. For example, LDO regulators are useful in battery-powered applications where the power supply voltage is exceedingly low. 
     A typical LDO regulator ( 400 ) is shown in FIG.  4 . The LDO regulator ( 400 ) includes a PMOS transistor (MP 40 ), a first resistor (R 41 ), a second resistor (R 42 ), and a voltage control block ( 410 ). The PMOS transistor (MP 40 ) has a drain that is connected to an output terminal (VREG), a gate that is connected to node N 40 , and a source that is connected to an input voltage (VIN). The first resistor (R 41 ) is series connected between the output terminal (VREG) and node N 41 . The second resistor (R 42 ) is series connected between node N 41  and a circuit ground (GND). The voltage control block ( 410 ) has three input terminals (VIN, VREF, SENSE) and an output terminal (PCTL). In the voltage control block ( 410 ), the first input terminal (VIN) is connected to the input voltage (VIN), the second input terminal (VREF) is connected to a reference voltage (VREF), and the third input terminal (SENSE) is connected to node N 41 . The output terminal (PCTL) of the voltage control block ( 410 ) is connected to node N 40 . 
     A load (ZL) is connected to the output terminal (VREG) of the LDO regulator ( 400 ). The LDO regulator ( 400 ) controls the gate of the PMOS transistor (MP 40 ) to ensure that regulation of the output voltage (VREG) is maintained. The voltage control block ( 410 ) monitors the SENSE input terminal and controls the gate of the PMOS transistor (MP 40 ) through the PCTL output terminal. Resistors R 41  and R 42  form a resistor divider that produces a signal that is related to the regulated output voltage (VREG). When the SENSE input terminal and the reference signal (VREF) are substantially the same, the LDO is properly maintaining regulation of the output voltage to the load (ZL). 
     SUMMARY OF THE INVENTION 
     Briefly stated, the present invention is related to an LDO regulator that provides regulation of an output voltage at an output node. The LDO regulator includes a pass device, a cascode device, a level shifter, an error amplifier, and a tracking voltage divider. The error amplifier is arranged to sense the output voltage and provide an error signal to the pass device via the level shifter. The level shifter changes the DC level of the error signal such that the pass device is isolated from damaging voltages. The cascode device is arranged to increase the impedance between the output node and the pass transistor such that the LDO regulator can sustain input voltages that exceed process limits without damage. The cascode device is biased by the tracking voltage divider. The tracking voltage divider adjusts the biasing to the cascode device such that a decreased input voltages result in lower impedance, and increased input voltages result in higher impedance. 
     A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a low drop-out voltage regulator; 
     FIG. 2 is a schematic diagram of another low drop-out voltage regulator; and 
     FIG. 3 is a schematic diagram of a biasing and protection circuit that is employed by the low drop-out regulator that is illustrated in FIG. 2, arranged in accordance with the present invention. 
     FIG. 4 is a schematic diagram of a conventional low drop-out voltage regulator. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active or passive, that are coupled together to provide a desired function. 
     The present invention is generally related to low drop-out voltage regulators (LDOs). Transistors in the LDO are manufactured according to a particular semiconductor processing technology. Example semiconductor processing technologies include field effect transistors (FETs) such as metal oxide semiconductor FETs (MOSFETs), bipolar junction transistors (BJTs), or a combination of FETs and BJTs. Transistors for each semiconductor process are evaluated according to many destructive tests to determine the limits of reliable operation. In one example, a FET is evaluated to determine a maximum gate voltage before the gate-oxide layer begins to breakdown. In another example, a FET is evaluated to determine a maximum voltage across the source and drain before the FET reaches destructive breakdown. In still another example, a BJT has a maximum collector-emitter voltage before the BJT reaches destructive breakdown. 
     FIG. 1 is a schematic diagram of an exemplary low drop-out voltage regulator ( 100 ) that is arranged in accordance with the present invention. LDO  100  includes a level shifter circuit ( 110 ), a tracking voltage divider circuit ( 120 ), a bias and protection circuit ( 130 ), an error amplifier ( 140 ), a reference circuit ( 150 ), two resistors (R 1 , R 2 ), and two transistors (T 1 , T 2 ). 
     Level shifter circuit  110  is coupled to node N 1 , node N 6 , and node N 7 . Tracking voltage divider circuit  120  is coupled to node N 0 , node N 1 , node N 8 , and node N 9 . Bias and protection circuit  130  is coupled to node N 0 , node N 1 , and node N 9 . Error amplifier  140  is coupled to node N 4 , node N 5 , node N 6 , and node N 9 . Reference circuit  150  is coupled to node N 0 , node N 5 , and node N 9 . Resistor R 1  is coupled between node N 3  and node N 4 . Resistor R 2  is coupled between node N 0  and node N 4 . Transistor T 1  is coupled to node N 1 , node N 2 , and node N 7 . Transistor T 2  is coupled to node N 2 , node N 3 , and node N 8 . 
     Low drop-out voltage regulator  100  is arranged to provide an output voltage (VOUT) at node N 3  in response to an input voltage (VIN) that is received at node N 1 . Transistor T 1  and T 2  are arranged to operate as pass transistors in the low drop-out voltage regulator ( 100 ). Transistor T 1  is responsive to a first control signal (CTL 1 ) that is received from node N 7 . Transistor T 2  is responsive to a second control signal (CTL 2 ) that is received from node N 8 . Resistors R 1  and R 2  are arranged to divide the output voltage (VOUT) to provide a sense signal (SNS) at node N 4 . Reference circuit  150  is arranged to provide a reference signal (REF) at node N 5 . Error amplifier  140  is arranged to provide an error signal (ERR) in response to the sense signal and the reference signal. Level shifter circuit  110  is arranged to provide the first control signal (CTL 1 ) in response to the error signal (ERR). Tracking voltage divider circuit  120  is arranged to provide the second control signal (CTL 2 ). Regulation is achieved when the reference signal (REF) and the sense signal (SNS) are equal. The output voltage (VOUT) is approximately determined as: VOUT≈VREF*[1+(R 1 /R 2 )]. 
     Bias and protection circuit  130  is arranged to ensure that the tracking voltage divider  120 , error amplifier  140 , and reference circuit  150  are properly initialized such that the regulation process is started. The bias and protection circuit  130  is also arranged to ensure that the tracking voltage divider  120 , error amplifier  140 , and reference circuit  150  are protected from voltages that exceed the process limit. 
     One process limit for transistor T 1  (e.g., the drain-source breakdown voltage) is approximately determined by the voltage drop between nodes N 1  and N 2 . Similarly, a process limit for transistor T 2  (e.g., the drain-source breakdown voltage) is approximately determined by the voltage drop between nodes N 2  and N 3 . Transistor T 2  is arranged to operate as a protection device that limits the voltage at node N 2  such that transistor T 1  does not exceed the process limit. 
     The conductivity of transistor T 1  changes according to control signal CTL 1 . Level shifter  110  is arranged to change the DC level of the error signal (ERR) such that the control signal CTL 1  does not exceed another process limit for transistor T 1  (e.g., the gate-oxide breakdown voltage). The conductivity of transistor T 2  changes according to control signal CTL 2 . Control signal CTL 2  is arranged to track changes in input voltage VIN such that transistor T 2  limits the voltage associated with node N 2 , whereby the voltage across transistor T 1  is limited to prevent exceeding the process limit. 
     FIG. 2 is a schematic diagram of another exemplary low drop-out voltage regulator ( 200 ) that is arranged in accordance with the present invention. LDO  200  includes ten transistors (T 1 -T 10 ), eight resistors (R 1 -R 8 ), two controlled current sources (I 1 -I 2 ), and a capacitor (C 3 ). Similar components and connections from FIG. 1 are labeled identically in FIG.  2 . 
     Transistor T 1  includes a source that is coupled to node N 1 , a gate that is coupled to node N 7 , and a drain that is coupled to node N 2 . Transistor T 2  includes a source that is coupled to node N 2 , a gate that is coupled to node N 8 , and a drain that is coupled to node N 3 . Resistor R 1  is coupled between nodes N 3  and N 4 . Resistor R 2  is coupled between nodes N 4  and N 0 . Transistor T 3  includes a source that is coupled to node N 8 , a gate that is coupled to node N 25 , and a drain that is coupled to node N 0 . Resistor R 3  is coupled between nodes N 8  and N 25 . Capacitor C 3  is coupled between nodes N 25  and N 0 . Resistor R 4  is coupled between nodes N 1  and N 8 . Controlled current source I 1  is coupled between nodes N 8  and N 0 . Resistor R 5  is coupled between nodes N 1  and N 26 . Transistor T 6  includes a source that is coupled to node N 26 , a gate that is coupled to node N 28 , and a drain that is coupled to node N 27 . Resistor R 6  is coupled between nodes N 27  and N 0 . Current source I 1  is coupled between nodes N 21  and N 0 . Transistor T 4  includes a source that is coupled to node N 21 , a gate that is coupled to node N 4 , and a drain that is coupled to node N 22 . Transistor T 5  includes a source that is coupled to node N 21 , a gate that is coupled to node N 5 , and a drain that is coupled to node N 23 . Transistor T 7  includes a source that is coupled to node N 23 , a gate that is coupled to node N 26 , and a drain that is coupled to node N 7 . Transistor T 8  includes a source that is coupled to node N 22 , a gate that is coupled to node N 26 , and a drain that is coupled to node N 24 . Resistor R 7  is coupled between nodes N 1  and N 7 . Resistor R 8  is coupled between nodes N 1  and N 24 . Transistor T 9  includes a source that is coupled to node N 1 , a gate that is coupled to node N 24 , and a drain that is coupled to node N 7 . Transistor T 10  includes a source that is coupled to node N 1 , and a gate and drain that are coupled to node N 24 . 
     The bias and protection circuit ( 130 ) from FIG. 1 is arranged to provide the biasing signals (BIASN, BIASP) to nodes N 28  and N 29  in FIG.  2 . The reference circuit ( 150 ) from FIG. 1 is arranged to provide the reference signal (REF) to node N 5  in FIG.  2 . 
     The functions of error amplifier  140  and level shifter  110  are provided by transistors T 4 , T 5 , T 7 -T 10 , resistors R 7 -R 8 , and current source I 1 . Transistors T 4 -T 5  and current source I 1  are arranged to operate as a differential pair. The differential pair is responsive to a sense signal (SNS) at node N 4 , and a reference signal (REF) at node N 5 . Transistors T 9  and T 10  are arranged to operate as a current mirror circuit that is arranged to provide a reflected current from transistor T 9  to node N 7  in response to a current that is provided to transistor T 10  at node N 24 . Transistors T 7 -T 8  are arranged to operate as cascode devices that isolate the current mirror devices from the drains of transistors T 4  and T 5 . Thus, the cascode devices act as level shifters between nodes N 22  to N 24 , and nodes N 23  to N 7 . Transistor T 6  provides a current to resistor R 5  in response to BIASP. A signal is provided to node N 26  that is approximately determined by VIN−I(T 6 )*R 5 . Transistor T 6 , and resistors R 5  and R 6  are arranged to operate as a cascode bias for transistors T 7 -T 8 . 
     Resistor R 4  and current source  12  in FIG. 2 replace tracking voltage divider circuit  120  from FIG.  1 . Resistor R 4  generates a voltage drop that is approximately determined by VIN−I 2 *R 4 . Bias and protection circuit  130  is arranged to provide the bias signal (BIAS) such that current source I 2  provides a current that is relatively constant (e.g., as long as the transistors are non-saturated). The voltage associated with control signal CTL 2  is responsive to the input voltage such that control signal CTL 2  increases when VIN increases, and decreases when VIN decreases (e.g., V(CTL 2 )≈V(VIN)−I 2 *R 2 ). When VIN drops below a limit (determined by I 2 *R 4 ), the voltage associated with control signal CTL 2  will collapse to the circuit ground potential (e.g., 0V). The impedance associated with transistor T 2  increases when the voltage associated with control signal CTL 2  increases (e.g., transistor T 2  begins to turn “off”). The impedance associated with transistor T 2  decreases when the voltage associated with control signal CTL 2  decreases (e.g., transistor T 2  begins to turn “on”). Transistor T 1  is isolated from the voltage associated with the output signal (VOUT), by transistor T 2 , when the input signal (VIN) increases such that transistor T 1  is protected from excessive voltages. 
     In one example, current source I 2  and resistor R 4  are arranged to provide a biasing limit that is associated with a drain-source breakdown voltage in a particular semiconductor process. When the input voltage (VIN) increases above the biasing limit, control signal CTL 2  will increase accordingly such that the drain-source voltage across transistor T 1  does not exceed the process limit. Values for the biasing limit of transistor T 1  will change for different semiconductor processes such that current source I 2  and resistor R 4  will be need to be adjusted. 
     Transistor T 3 , resistor R 3 , and capacitor C 3  are arranged to operate as a clamp circuit. At steady-state operation, capacitor C 3  is fully charged and the voltage at nodes N 8  and N 25  is substantially identical. During fast transients in the input signal (VIN), the voltage associated with node N 8  instantaneously changes such that transistor T 3  becomes forward biased. The voltage associated with node N 8  is clamped while transistor T 3  is forward biased. After the transient event has subsided, capacitor C 3  once again is charged to the same voltage as node N 8  and transistor T 3  is deactivated. 
     Resistors R 7  and R 8  are arranged to maintain transistors T 1  in an OFF state (or deactivated) when the input voltage is initially applied to the circuit. The error amplifier circuit transistors (e.g., T 4 , T 5 , T 7 -T 10 ) may be initially inoperable or in an unknown condition. Since node N 7  is a control node for transistor T 1  it is preferred that node N 7  start in a known condition. While the error amplifier is inoperable, the resistors will initially define nodes N 24  and N 7  to be the same as the input voltage. Transistor T 1  is deactivated while node N 7  and node N 1  have the same voltage (e.g., VGS 1 ≈0). After the error amplifier circuit begins to operate, the error amplifier will employ feedback from the output voltage to properly define the control signal for transistor T 1 . 
     FIG. 3 is a schematic diagram of a biasing and protection circuit ( 300 ) that is arranged in accordance with the present invention. The biasing and protection circuit ( 300 ) may be arranged for use by the low drop-out regulator that is illustrated in FIG.  2 . The biasing and protection circuit includes a shunt regulator circuit and a bias current generator circuit. The shunt regulator circuit includes a resistor (R 31 ), and a zener circuit (Z 31 ). The bias current generator circuit includes a resistor (R 32 ), a capacitor (C 31 ), and seven transistors (M 31 -M 37 ). 
     Resistor R 31  is coupled between VIN and node N 31 . Zener circuit Z 31  is coupled between node N 31  and GND. Resistor R 32  is coupled between node N 34  and GND. Capacitor C 31  is coupled between nodes N 31  and N 32 . Transistor M 31  includes a source and gate that are coupled to node N 32 , and a drain that is coupled to node N 31 . Transistor M 32  includes a source that is coupled to GND, and a gate and drain that are coupled to node N 32 . Transistor M 33  includes a source that is coupled to GND, a gate that is coupled to node N 32 , and a drain that is coupled to node N 33 . Transistor M 34  includes a source that is coupled to node N 34 , a gate that is coupled to node N 35 , and a drain that is coupled to node N 33 . Transistor M 35  includes a source that is coupled to GND, and a gate and drain that are coupled to node N 34 . Transistor M 36  includes a source that is coupled to node N 31 , and a gate and drain that are coupled to node N 33 . Transistor M 37  includes a source that is coupled to node N 31 , a gate that is coupled to node N 33 , and a drain that is coupled to node N 35 . 
     Resistor R 31  is arranged to operate as a protection device that limits the current in the shunt regulator. The voltage at node N 31  increases until zener circuit Z 31  is activated. Zener circuit Z 31  is arranged to clamp the voltage associated with node N 31 . Although zener circuit Z 31  is illustrated symbolically as a zener diode, other shunt regulator circuits that are arranged to selectively clamp the voltage associated with node N 31  are considered within the scope of the present invention. 
     Transistors M 34 -M 37  and resistor R 32  are arranged to operate as a supply-independent biasing circuit. Transistors M 36  and M 37  form a first current mirror that is arranged to provide a 1:1 current ratio. Transistors M 34  and M 35  form a second current mirror that is arranged to provide a 1:X current ratio, where X is a scaling factor between the transistors. Current is provided to resistor R 32 , which generates a voltage drop. The voltage drop is added to the threshold voltage of transistor M 34 , so that a difference between the gate to source voltages of transistors M 34  and M 35  is provided across resistor R 32 . 
     Transistors M 31 -M 33  are arranged to inject a startup current into node N 33  such that the biasing current generator is initialized into proper operation. Transistor M 31  is arranged to provide a leakage current to node N 32 . Capacitor C 31  is arranged to couple a fast transient signal to node N 32  when VIN changes rapidly. The signals at node N 32  provide currents that are reflected to transistor M 33  by transistor M 32 , which is a diode-connected device. 
     In light of the above description, it is understood and appreciated that the circuits shown in FIG.  1 -FIG. 3 may be redesigned such that the p-type MOS transistors are replaced with n-type MOS transistors, and vice-versa. For example transistors T 1  and T 2  in FIG. 2 are shown as p-type MOS devices that are referenced to a high supply (VIN) relative to ground. In another example, transistors T 1  and T 2  may be replaced with n-type MOS transistors that are referenced to a low supply (VIN), where the high supply corresponds to the circuit ground. Additionally, it is understood and appreciated that the design may be further arranged to operate using other field effect transistor types including, but not limited to JFET transistors, GaAsFET transistors, and the like. 
     The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.