Abstract:
A system and method for testing multiple-input-multiple-output (MIMO) devices under test (DUTs) with multiple radio frequency (RF) signal testers. Each tester receives one or more RF signals from one or more of the DUTs, and the testers are mutually coupled in a ring such that successive ones receive a trigger input signal from an upstream tester and provide a trigger output signal to a downstream tester. Each tester is responsive to its input trigger signal and its one or more RF signals by providing its output trigger signal such that its output trigger signal has an asserted state initiated in response to an assertion of its input trigger signal and a transcending of a predetermined magnitude by at least one of the one or more RF signals.

Description:
TECHNICAL FIELD 
     The present invention relates generally to systems and methods for testing electronic equipment. More particularly, it relates to improvements in systems and methods for testing wireless signal transceivers using test platforms consisting of hardware, firmware and/or software components. 
     BACKGROUND 
     Many of today&#39;s handheld devices make use of wireless “connections” for telephony, digital data transfer, geographical positioning, and the like. Despite differences in frequency spectra, modulation methods, and spectral power densities, the wireless connectivity standards use synchronized data packets to transmit and receive data. In general, all of these wireless capabilities are defined by industry-approved standards (e.g. IEEE 802.11 and 3GPP LTE) which specify the parameters and limits to which devices having those capabilities must adhere. 
     At any point along the device-development continuum, it may be necessary to test and verify that a device is operating within its standards&#39; specifications. Most such devices are transceivers, that is, they transmit and receive wireless RF signals. Specialized systems designed for testing such devices typically contain subsystems designed to receive and analyze device-transmitted signals (e.g., vector signal analyzers or VSAs) and to send signals (e.g., vector signal generators or VSGs) that subscribe to the industry-approved standards so as to determine whether a device is receiving and processing the wireless signals in accordance with its standard. 
     In testing wireless devices that employ multiple input/multiple output (MIMO) technology, the most accurate testing will simulate real-world environments. Thus, if a MIMO device has two antennas, two transmitters and two receivers (e.g., a 2×2 MIMO device), the most accurate testing would involve doing receive signal (RX) testing using two VSGs and transmit signal (TX) testing using two VSAs, plus some means of synchronizing the VSA and VSG operations. 
     When such single VSA/VSG testers are used to test TX functions of a device under test (DUT), the TX signals are sampled one at a time by the VSA using a multiplexing or switching scheme. Thus, one is unable to fully simulate the environment where multiple TX signals are transmitted simultaneously. 
     One can, in fact, simulate real-world environments using testers equipped with multiple VSAs and VSGs, and synchronization. And, it could be possible to build up such a test capability by using two or more single VSA/VSG testers to create a N×N MIMO test capability (where N≧2). However, the concatenation of such testers is not trivial. There are triggering issues that must be resolved in order to have the combination simulate real-world MIMO conditions. For example, each tester must have the ability to trigger the others as the DUT may not use all transmitters it has available. 
     Therefore, a system and method designed to support routine concatenation of single VSA/VSG test systems which provides an expandable triggering capability would provide a faster, simpler means for combining such testers while offering more accurate simulation of real-world MIMO environments and conditions. Furthermore, since MIMO is not limited to 4×4, having dedicated trigger lines for each tester is less desirable than have a scalable solution that permits one to add new testers as the N-level of N×N MIMO increases. 
     SUMMARY 
     A system and method for testing multiple-input-multiple-output (MIMO) devices under test (DUTs) with multiple radio frequency (RF) signal testers. Each tester receives one or more RF signals from one or more of the DUTs, and the testers are mutually coupled in a ring such that successive ones receive a trigger input signal from an upstream tester and provide a trigger output signal to a downstream tester. Each tester is responsive to its input trigger signal and its one or more RF signals by providing its output trigger signal such that its output trigger signal has an asserted state initiated in response to an assertion of its input trigger signal and a transcending of a predetermined magnitude by at least one of the one or more RF signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a functional block diagram of a system for testing MIMO signal transceivers with multiple RF signal testers in accordance with one embodiment of the presently claimed invention. 
         FIG. 2  is a functional block diagram of trigger signal circuitry for providing synchronized trigger signals used in the system of  FIG. 1  in accordance with one embodiment of the presently claimed invention. 
     
    
    
     DETAILED DESCRIPTION 
     The invention will now be described with reference to the drawing figures, in which like reference numerals refer to like elements throughout. The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that the term “signal” may refer to one or more currents, one or more voltages, or a data signal. 
     Referring to  FIG. 1 , a system  100  for testing multiple MIMO devices with multiple RF signal testers includes signal testers  102  (e.g., N signal testers  102   a ,  102   b , . . . ,  102   n ) and a corresponding number of signal routing circuits or devices  108  (e.g., signal switches having a pole  108   d  and a throw  108   g ,  108   a  for each RF signal) for coupling via RF signal cables  111  to the N signal ports  110   p  of the DUT  110 . As discussed in more detail below, a reference signal source  114  can also be included for provided reference signals  115  for the testers  102  (e.g., for frequency synchronization within and among the testers  102 ). 
     As is well known in the art, each tester  102  typically includes a signal source in the form of a vector signal generator (VSG)  104  and a signal analyzer in the form of a vector signal analyzer (VSA)  106 , both of which are controlled by internal control circuitry (not shown) and often by external control signals  117   a  provided by an external controller, such as a personal computer (not shown). Similarly, switch control signals  117   b  are provided to the signal switches  108  so as to route signals  105  from the VSGs  104  to the DUT  110  and signals from the DUT  110  to the VSAs  106 , as appropriate for the test sequences. These control signals can also be provided by an external controller, or, alternatively, by control circuitry (not shown) within the testers  102 . 
     The testers  102  also include RF signal ports  104   gr ,  106   ar  via which VSG signals  105  are provided and incoming DUT signals  109  for the VSAs  106  are received. The VSAs  106  also include trigger signal input ports  106   ti  and trigger signal output ports  106   to  (discussed in more detail below). The first VSA  106   a  receives its trigger input signal  107   n  from the last VSA  106   n  and provides its trigger output signal  107   a  to the next downstream VSA  106   b . At the other end, the last tester  102   n  receives its trigger input signal from the last upstream tester and provides its output trigger signal  107   n  back to the first tester  102   a . Accordingly, the trigger signals  107  are connected in a form of continuous loop from upstream to downstream testers and back again. 
     The reference signals  115  provided by the reference signal source  114  (e.g., a temperature compensated crystal oscillator) provide a common frequency/timing reference and global synchronization for the testers  102 . When receiving an input signal  109  originating from one of the signal ports  110   p  of the DUT  110 , a trigger output signal  107  is generated by that tester  102  for use as a trigger input signal for its neighboring downstream tester  102 , as discussed above. As a result, the detection of a DUT signal  109  by the VSA  106  of an individual tester  102  will initiate a trigger signal that will be propagated through the trigger signal loop among all testers  102 . This trigger signal prompts each VSA  106  to capture any DUT signal  109  present at its RF input signal port  106   ar . Accordingly, depending upon which tester receives its DUT signal  109  first, any of the concatenated testers  102  can act as the VSA trigger master initiating a triggered response among all testers  102 . 
     As will be readily appreciated, this continuous loop of trigger signal connections can be scaled for an arbitrary number of testers  102 . Further, while an exemplary embodiment involves initiation of this trigger signal by detection of the rising edge of an incoming RF signal  109  (e.g., when a signal power detector indicates the transcending of the input signal magnitude beyond a predetermined magnitude threshold) the initial trigger for the trigger signal loop can be initiated in other ways, such as by a free running trigger signal initiated by software within a tester  102 , by a downlink as in the case of a WCDMA, CDMA, EVDO or LTE system, or in accordance with the externally generated control signals  117   a.    
     Referring to  FIG. 2 , in accordance with an exemplary embodiment, trigger signal circuitry for generating the trigger output signal to be made available at the trigger signal output port  106   to  includes RF signal detection circuitry  120  and signal combining (e.g., “OR”) circuitry  124 , as well as timing circuitry  122 . The incoming RF signal  109  received via the RF signal input signal port  106   ar  serves as a received RF signal  107   ar  for detection by the RF signal detection circuitry  120 . The resulting detection signal  121  (e.g., indicative of a signal voltage magnitude or signal power level of the input signal  107   ar ) is provided to the combining circuit  124  and a timing circuit  122   b . Similarly, the loop trigger signal  107 , received via the trigger signal input port  106   ti , serves as the internal trigger input signal  107   ti  that is provided to the signal combining circuit  124  and another timing circuit  122   a.    
     In accordance with a preferred embodiment, the combining circuit  124  provides a trigger output signal  125  that is initiated in response to the first assertion of the two input signals  107   ti ,  121 , thereby initiating the synchronized triggering of the testers  102  as discussed above. 
     The timing circuits  122  compare these internal trigger signals  107   ti ,  121  with the external reference signal  115  to provide timing signals  123  that can be used for post-processing compensation of the captured RF signals  109  performed by the VSAs  106 . For example, the timing circuits  122  can provide a capability for comparing the two trigger signals  107   ti ,  121  against the reference signal  115  to determine relative timing differences against that common reference signal  115 . This will allow post-processing compensation of the data captures in order to properly align the events in time during the data analysis that follows. For example, the timing signals  123  can provide a reference point in time for compensation of the placement of the captured data signal in the time domain. In other words, after the results have been captured, due to delays around the loop, the relative starting point of the captured signal, in time, may need to be compensated so that its juxtaposition vis-à-vis concurrent MIMO signals is accurate. Without such compensation, the loop would provide triggering but the concurrent capture points in the time domain may be skewed. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.