Abstract:
A method of forming ohmic contacts on a light emitting diode that features a surface treatment of a substrate includes exposing a surface of a p-type gallium nitride layer to an acid-containing solution and a buffered oxide etch process. A quantum well is formed in a gallium nitride substrate and a layer of p-type gallium nitride is deposited over the quantum well. The surface of the p-type gallium nitride is exposed to an acid-containing solution and then a buffered oxide etch process is performed to provide an etched surface. A metal stack including a layer of silver disposed between layers of platinum is then deposited.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The invention is directed to light emitting diodes and in particular to ohmic contacts for light emitting diodes. 
         [0002]    One technique for measuring the efficiency of light emitting diodes (LEDs) is by determining the luminance per watt. The luminance provided by light emitting diodes is dependent upon several factors such as internal quantum efficiencies, as in the case of an injected carrier not being converted to a photon, or extraction efficiency, as in the case of a small fraction of photons being successfully extracted from the light emitting diode as opposed to being lost to internal absorption. To realize high efficiency LEDS, both of these issues need to be addressed. The potential gain from improving extraction efficiency, however, is likely to be greater and simpler to accomplish than the gains from improving internal efficiency. 
         [0003]    One technique to improve light extraction of visible light nitride LEDs, such as Gallium Nitride (GaN) LEDs, is achieved through use of high reflectivity metallurgies which are typically mounted to one side of the LED. GaN based devices typically require ohmic contact formation as a means of establishing electrical contact to the device with minimal impact on the operating voltage of the device. Thus, the high reflectivity metallurgies are typically employed in the ohmic contact and attached to a p-type GaN layer of the LED. One common approach is to use a silver containing layer in the ohmic contact. Silver is desirable, because of its high reflectance. The difference in the work function between silver and the other materials from which the LED is fabricated has been problematic. For example, it is widely accepted that metals with high work functions form the best contacts for p-type semiconductor materials, while metals with low work functions form the best contacts for n-type semiconductor materials. However, surface contamination of the metal semiconductor interface may degrade the ohmic contact performance of metals. Contamination layers at the interface may produce an unforeseen electronic state that may degrade the efficiency of the LED. 
         [0004]    There is a need, therefore, to provide improve ohmic contact techniques for LEDs. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    This invention is directed to a method of forming ohmic contacts on a light emitting diode that features a surface treatment of a substrate that includes exposing a surface of a layer p-type gallium nitride to an acid-containing solution and a buffered oxide etch process. To that end, the method includes forming a quantum well in a gallium nitride substrate, depositing a layer of p-type gallium nitride upon said quantum wells, exposing a surface of said p-type gallium nitride to an acid-containing solution, forming a cleaned surface; subjecting said cleaned surface to a buffered oxide etch process, forming an etched surface; and generating, upon said etched surface, a metal stack including a layer of silver disposed between layers of platinum. These and other embodiments are discussed further below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is a cross-sectional view of a single light emitting diode manufactured in accordance with the present invention; 
           [0007]      FIG. 2  is a flow diagram showing the steps used to manufacture the light emitting diode shown in  FIG. 1 ; 
           [0008]      FIG. 3  is a cross-sectional view showing a substrate upon which the light emitting diode shown in  FIG. 1  is produced; 
           [0009]      FIG. 4  is a cross-sectional view showing the substrate in  FIG. 3  with a p-type gallium arsenide layer disposed thereon; 
           [0010]      FIG. 5  is a simplified cross-sectional view of the substrate shown in  FIG. 4  having a patterned photo resist layer deposited thereon; 
           [0011]      FIG. 6  is a simplified cross-sectional view of the substrate shown in  FIG. 4  having a plurality of metal layers deposited thereupon; 
           [0012]      FIG. 7  is a cross-section view of the substrate shown in  FIG. 6  after being subjected to a lift-off process that removed the photo resist; and 
           [0013]      FIG. 8  is a simplified cross-sectional view of the substrate shown in  FIG. 6 , scored-regions formed thereon. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0014]    Referring to  FIG. 1 , shown is a light emitting diode  10  manufactured in accordance with the present invention that includes a substrate  12  formed of n-type gallium nitride GaN. An active layer  14  is formed upon substrate. Active layer  14  may comprise a single quantum well or multiple quantum wells, with 2-10 quantum wells. A layer of p-type gallium nitride  16  is formed upon quantum wells  14 . A metal stack  18  is positioned upon layer  16  and is comprised of three separate metal layers, shown as  20 ,  22  and  24 . Layers  20  and  24  are formed from platinum and layer  22  is formed from silver. 
         [0015]    Substrate  12  may have a large-surface orientation within ten degrees, within five degrees, within two degrees, within one degree, within 0.5 degree, or within 0.2 degree of (0 0 0 1), (0 0 0 −1), {1 −1 0 0}, {1 1 −2 0}, {1 −1 0.+−.1}, {1 −1 0.+−.2}, {1 −1 0.+−.3}, {2 0 −2.+−.1}, or {1 1 −2.+−.2}. In one specific embodiment, the substrate has a semipolar large-surface orientation, which may be designated by (hkil) Bravais-Miller indices, where i=−(h+k), 1 is nonzero and at least one of h and k are nonzero. The substrate may have a dislocation density below 10.sup.4 cm.sup.−2, below 10 3  cm −2 , or below 10 2  cm −2 . Substrate  12  may have an optical absorption coefficient below 100 cm10 −1 , below 50 cm −1  or below 5 cm −1  at wavelengths between about 465 nm and about 700 nm. The nitride base crystal may have an optical absorption coefficient below 100 cm −1 , below 50 cm −1  or below 5 cm −1  at wavelengths between about 700 nm and about 3077 nm and at wavelengths between about 3333 nm and about 6667 nm. The surface of substrate  12  may have a dislocation density below 10 5  cm −2  and is substantially free of low-angle grain boundaries, or tilt boundaries, over a length scale of at least 3 millimeters. Substrate  12  may be doped with any suitable n-type dopants from group VI and group IV atoms, e.g., sulfur, selenium, tellurium, silicon, germanium. In the present embodiment, substrate  12  is doped with Si and O to dope our GaN, providing a dopant concentration of approximately of 3 E18 cm−3. 
         [0016]    Active layer  14  may comprise of InGaN wells and GaN barrier layers. In other embodiments, the well layers and barrier layers comprise Al w In x Ga 1-w-x N and Al y In z Ga 1-y-z N, respectively, where 0≦w,x,y,z,w+x,y+z≦1, where w&lt;u, y and/or x&gt;v, z so that the bandgap of the well layer(s) is less than that of the barrier layer(s) and the n-type substrate. The well layers and barrier layers may each have a thickness between about 1 nm and about 20 nm. In another embodiment, active layer  14  comprises a double heterostructure, with an InGaN or Al w In x Ga 1-w-x N and Al y In z Ga 1-y-z N layer about 20 nm to about 500 nm thick surrounded by GaN or Al y In z Ga 1-y-z N layers, where w&lt;u, y and/or x&gt;v, z. The composition and structure of the active layer are chosen to provide light emission at a preselected wavelength. Active layer  14  may be left undoped (or unintentionally doped) or may be doped n-type or p-type. Active layer  14  is formed upon substrate  12  using standard processing techniques. 
         [0017]    Layer  16  may be doped with any suitable p-type dopant, such as those from group II or IV atoms, e.g., magnesium, zinc, cadmium, silicon, germanium. In the present example, layer is doped with magnesium to provide a dopant concentration of approximately 1e20 cm −3 . 
         [0018]    Referring to  FIGS. 2 and 3 , substrate  12  is doped with n-type dopants using well known techniques, at step  100 . At step  102 , active layer  14  is formed upon substrate  12  using well known techniques. Following formation of active layer  14 , p-type gallium nitride layer  16  is formed thereupon, shown in  FIG. 4 , at step  104  of  FIG. 2 . At step  106  surface of layer is exposed to an acid-containing cleaning solution. The cleaning solution consists essentially of 15% of nitric acid by weight, 27% of hydrochloric acid by weight and 58% of water by weight. This provides cleaned surface  26 . 
         [0019]    Referring to both  FIG. 2  and  FIG. 5 , at step  108  a patterned photo resist layer  28  is formed upon cleaned surface  26 . Layer  28  has a shape of a battlement leaving portions  30  of cleaned surface  26 , with segments  32  of photo resist material being present between adjacent portions  30 . Following formation of patterned photo resist layer  28 , substrate  12  regions  30  and segments  32  are exposed to a buffered oxide etch process, at step  110 . To that end, substrate  12  dipped into a solution consisting essentially of 2% hydrofluoric acid by weight and 8.75% ammonium fluoride by weight, with the rest being water. At step  112 , three metal layers are sequentially deposited upon portions and segments  32 . Specifically, a platinum layer  34  is deposited, followed by deposition of a silver layer  36 . Another platinum layer  38  is deposited upon silver layer  36 . 
         [0020]    Referring to  FIG. 2 , at step  114  a lift-off process is undertaken to remove segments  38  and the portions of layers  34 ,  36  and  38  in superimposition therewith, leaving a plurality of spaced-apart metal stacks  40 . As a result, regions  42 , shown in  FIG. 7 , of exposed substrate  12  remain between adjacent metal stacks  40 . 
         [0021]    Referring to both  FIGS. 2 and 8 , at step  116 , a recess  44  is formed in regions  42 , using desired techniques, such as laser etching. Recesses  44  compromise the structural integrity of substrate  42  so that the same may be segmented to produce light emitted diode  10 , shown in  FIG. 1 . 
         [0022]    It should be understood that the description recited above is an example of the invention and that modifications and changes to the examples may be undertaken which are within the scope of the claimed invention. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements, including a full scope of equivalents.