Abstract:
A method of fabricating an integrated circuit. A thin liner ( 110, 210, 310 ) is deposited over dielectric layer including within a trench ( 108 ) and/or via ( 106 ). The thin liner ( 110, 210, 310 ) smoothes the sidewalls of the trench ( 108 ) and/or via ( 106 ) and reduces resistivity. The thin liner may comprise an organic or inorganic dielectric ( 110 ) or metal ( 210,310 ). A copper interconnect structure ( 116, 216, 316 ) is then formed over the thin liner ( 110, 210, 310 ).

Description:
FIELD OF THE INVENTION  
         [0001]    The invention is generally related to the field of fabricating copper interconnects in semiconductor devices and more specifically to a reducing copper line resistivity.  
         BACKGROUND OF THE INVENTION  
         [0002]    As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects due to the significantly lowered resistivity of copper versus aluminum. The resistivity of copper is less than 1.8 μΩ-cm for copper lines wider than 0.5 μm in linewidth. However, the value increases rapidly as the copper line/via dimension decreases. At 0.20 μm linewidth, the copper line resistivity was measured to be 2.15 μΩ-cm. The increase in copper resistivity is expected to accelerate as the dimension continues to shrink. Simulations indicate that the copper resistivity will surpass aluminum resistivity of 2.8 μΩ-cm at the 0.08 μm technology. FIG. 1 displays the simulation results that show how quickly the resistivity rises as linewidth decreases using current copper interconnect approaches.  
         SUMMARY OF THE INVENTION  
         [0003]    The invention reduces copper line resistivity by smoothing trench and via sidewalls. After the via and/or trench etches, the rough sidewalls are smoothed by depositing a thin layer of liner material. If desired, a directional etch may follow the deposition to remove liner material from the horizontal surfaces. Processing continues to form the copper interconnect with any desired barrier layers.  
           [0004]    An advantage of the invention is providing a copper interconnect with reduced line resistivity for deep sub-quarter micron devices.  
           [0005]    This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    In the drawings:  
         [0007]    [0007]FIG. 1 is a graph of a theoretical prediction of resistivity versus copper linewidth;  
         [0008]    [0008]FIG. 2 is a graph of maximum % resistivity change due to sidewall roughness versus copper linewidth;  
         [0009]    FIGS.  3 A- 3 C are cross-sectional drawings of a copper interconnect structure with sidewall smoothing formed according to a first embodiment of the invention;  
         [0010]    FIGS.  4 A- 4 D are cross-sectional drawings of a copper interconnect structure with sidewall smoothing formed according to a second embodiment of the invention; and  
         [0011]    FIGS.  5 A- 5 D are cross-sectional drawings of a copper interconnect structure with sidewall smoothing formed according to a third embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0012]    One major cause of increased copper resistivity in a narrow trench is electron scattering from the sidewalls. Electron mean free path in copper is around 400 Å. When the narrow copper linewidth becomes comparable to the electron mean free path, the effect of electron scattering from the sidewalls becomes significant. FIG. 2 illustrates in theory the resistivity increase in percentage of copper line with very rough sidewalls compared to copper lines with perfectly smooth sidewalls. The contribution of sidewall scattering to copper resistivity becomes more and more when the copper linewidth decreases. The contribution from sidewall scattering can be as high as 30% for a 0.1 μm linewidth. The sidewall roughness has to be controlled in order to keep the overall copper resistivity low.  
         [0013]    The sidewalls of the trench and via are rough after the trench and via etches and ashes. The problem will become more severe when some low k dielectric materials are used. The rough sidewalls promote electron scattering.  
         [0014]    Electron scattering results in high resistivity. Therefore, it is desirable to repair the rough sidewalls to make them smooth before copper is deposited in the trenches and vias.  
         [0015]    The embodiments of the invention described below repair the rough sidewalls by depositing a thin layer of liner material. The embodiments are described in conjunction with a dual damascene process. It will be apparent to those of ordinary skill in the art having reference to the specification that the benefits of the invention may be applied generally to forming narrow copper lines.  
         [0016]    The first embodiment of the invention will now be discussed with reference to FIGS.  3 A- 3 D. A semiconductor body  100  is processed through formation of trench  108  and vias  106 . Semiconductor body  100  typically comprises a silicon substrate having transistors and other elements formed therein.  
         [0017]    An interlevel dielectric (ILD)  102  is formed over semiconductor body  100 . IMD (intrametal dielectric)  104  is formed over ILD  102 . An etchstop layer (not shown) may optionally be placed between ILD  102  and IMD  104 . Suitable dielectrics for ILD  102  and IMD  104 , such as silicon dioxides, fluorine-doped silicate glass (FSG), organo-silicate glass (OSG), hydrogen silesquioxane (HSQ), and/or other low k and porous low k materials, are known in the art. The invention is believed to be especially beneficial for low k and porous low k materials.  
         [0018]    A via  106  is etched in ILD  102  and a trench  108  is etched in IMD  104 . Via  106  is used to connect to underlying metal interconnect layers, such as copper interconnect  105 . Trench  108  is used to form the metal interconnect layer. The via and trench etches and ashes (pattern strips) leave a rough surface on the sidewalls of the via  106  and trench  108 , as shown in FIG. 3A.  
         [0019]    A thin dielectric liner  110  is deposited over IMD  104  and ILD  102  including on the sidewalls of via  106  and trench  108 , as shown in FIG. 3B. The size of trench  108  and via  106  may need to be adjusted to account for the thickness of dielectric liner  110 . The thickness of thin dielectric liner  110  is in the range of 5-100 Å. Liner  110  may comprise either an organic dielectric or inorganic dielectric. For example, liner  110  may comprise silicon dioxide or suitable low k dielectric materials. Various deposition methods such as chemical vapor deposition (CVD), atomic layer CVD (ALCVD), physical vapor deposition (PVD), or spin-on may be used.  
         [0020]    Referring to FIG. 3C, a directional etch is performed to remove portions of dielectric liner  110  located at the bottom of via  106  to open the via to the underneath metal,  105 , while leaving the sidewalls intact. Some roughening at the bottom of trench  108  may occur during the directional etch. However, this is not expected to significantly increase resistivity. An etch that is highly selective to the underneath dielectric  104  is desired. Dielectric liner  110  provides a smooth sidewall on the trench  108  and via  106 .  
         [0021]    After the directional etch, processing may continue with standard barrier  112  and seed deposition, copper fill  114 , and chemical mechanical polish to form copper interconnect  116 . The resulting copper interconnect structure  116  is shown in FIG. 3D.  
         [0022]    The second embodiment of the invention will now be discussed with reference to FIGS.  4 A- 4 D. As in the first embodiment, semiconductor body  100  is processed through formation of trench  108  and vias  106 . Semiconductor body  100  typically comprises a silicon substrate having transistors and other elements formed therein.  
         [0023]    An interlevel dielectric (ILD)  102  is formed over semiconductor body  100 . IMD (intrametal dielectric)  104  is formed over ILD  102 . An etchstop layer (not shown) may optionally be placed between ILD  102  and IMD  104 . Suitable dielectrics for ILD  102  and IMD  104 , such as silicon dioxides, low-k and porous low-k materials are known in the art.  
         [0024]    A via  106  is etched in ILD  102  and a trench  108  is etched in IMD  104 . Via  106  is used to connect to underlying metal interconnect layers, such as copper interconnect  105 . Trench  108  is used to form the metal interconnect layer. The via and trench etches and ashes (pattern strips) leave a rough surface on the sidewalls of the via  106  and trench  108 , as shown in FIG. 4A.  
         [0025]    A thin metal liner  210  is deposited over IMD  104  and ILD  102  including on the sidewalls of via  106  and trench  108 , as shown in FIG. 4B. The size of trench  108  and via  106  may need to be adjusted to account for the thickness of metal liner  210 . The thickness of thin metal liner  210  is in the range of 5-100 Å. Suitable materials include: Ti, TiN, Ta, TaN, WN, WC, TiSiN, TaSiN, etc. Various deposition methods such as CVD, ALCVD, and PVD may be used.  
         [0026]    Referring to FIG. 4C, a directional etch is performed to remove portions of metal liner  210  located on the horizontal surface, while leaving the sidewalls intact. Some roughening at the bottom of trench  108  may occur during the directional etch. However, this is not expected to significantly increase resistivity. Good etch selectivity to the underneath dielectric  104  is desired. Metal liner  210  provides a smooth sidewall on the trench  108  and via  106 . Due to the smooth sidewalls, a similar reduction in resistivity to that of the first embodiment is expected.  
         [0027]    After the directional etch, processing may continue with standard barrier  112  and seed deposition, copper fill  114 , and chemical mechanical polish to form copper interconnect  216 . The resulting copper interconnect structure  216  is shown in FIG. 4D.  
         [0028]    The third embodiment of the invention will now be discussed with reference to FIGS.  5 A- 5 D. As in the first embodiments, semiconductor body  100  is processed through formation of trench  108  and vias  106 . Semiconductor body  100  typically comprises a silicon substrate having transistors and other elements formed therein.  
         [0029]    An interlevel dielectric (ILD)  102  is formed over semiconductor body  100 . IMD (intrametal dielectric)  104  is formed over ILD  102 . An etchstop layer (not shown) may optionally be placed between ILD  102  and IMD  104 . Suitable dielectrics for ILD  102  and IMD  104 , such as silicon dioxides, fluorine-doped silicate glass (FSG), organo-silicate glass (OSG), hydrogen silesquioxane (HSQ), and/or other low k and porous low-k materials are known in the art.  
         [0030]    A via  106  is etched in ILD  102  and a trench  108  is etched in IMD  104 . Via  106  is used to connect to underlying metal interconnect layers, such as copper interconnect  105 . Trench  108  is used to form the metal interconnect layer. The via and trench etches and ashes (pattern strips) leave a rough surface on the sidewalls of the via  106  and trench  108 , as shown in FIG. 5A.  
         [0031]    A thin metal liner  310  is deposited over IMD  104  and ILD  102  including on the sidewalls of via  106  and trench  108 , as shown in FIG. 5B. The size of trench  108  and via  106  may need to be adjusted to account for the thickness of metal liner  110 . The thickness of thin metal liner  110  is in the range of 5-100 Å. Suitable materials include: Ti, TiN, Ta, TaN, WN, WC, TiSiN, TaSiN, etc. Various deposition methods such as CVD, ALCVD, and PVD may be used.  
         [0032]    In this embodiment, a directional etch is not performed. The excess liner material on IMD  104  is removed during the subsequent copper CMP process. Metal liner  310  provides a smooth sidewall on the trench  108  and via  106 .  
         [0033]    Processing may then continue with standard barrier  311  and seed deposition. However, if metal liner  310  can also satisfy the copper barrier criteria (good copper diffusion blocking efficiency, good adhesion, low resistivity, etc), the additional barrier layer may be omitted. Trench  108  and via  104  are then filled with copper by, for example, an electrochemical deposition (ECD) process, as shown in FIG. 5C. Chemical-mechanical polishing is then used to remove the excess copper fill  114 , barrier  311  and metal liner  310  from the above the top surface of IMD  104 , resulting in copper interconnect  316 . The resulting copper interconnect structure  316  is shown in FIG. 5D. In the third embodiment, the metal barrier layer and the metal liner layer can be switched if better smoothness, adhesion, convenience, etc. can be achieved. It means if necessary, the barrier layer can be deposited first followed by the metal liner and Cu fill.  
         [0034]    While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.