Abstract:
A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to electronic circuits, and, more particularly, to programmable glitch filters.  
         BACKGROUND OF THE INVENTION  
         [0002]    Digital circuit designs use the binary signal levels logic 0 and logic 1. These signals may also be referred to as logic LOW and logic HIGH, respectively. A glitch is an unwanted transition in the logic level (either LOW or HIGH). This effects the performance of digital circuits since storage elements (e.g., flip-flops) change their logic state on either a LOW to HIGH or HIGH to LOW logic transition. A glitch is illustrated in FIG. 1.  
           [0003]    The most conventional method of suppressing glitches in digital circuits on printed circuit boards (PCBs), for example, is by using an RC circuit. One example of a glitch suppression mechanism including an RC circuit is shown in FIG. 2A. The step input to the RC circuit (at point X) is shown in FIG. 2B. The re sponse of the circuit is illustrated in FIG. 2C, and the waveform at the output of the buffer (at Z) is shown in FIG. 2D. When a step input (shown in FIG. 2B) is given to the RC circuit (at X of FIG. 2A), the response of the circuit (at Y, shown in FIG. 2C) can be mathematically represented by the following equation (1):  
             V   o   =V   i (1 −e   −t/RC )  (1)  
           [0004]    where t is time in seconds, R is resistance in ohms and C is capacitance in farads.  
           [0005]    The glitch suppression technique using an RC circuit can be employed both for positive and negative glitches. The glitch suppression mechanism for positive glitches is shown in FIGS. 3A to  3 C, and the glitch suppression mechanism for negative glitches is shown in FIGS. 4A to  4 C. The values of R and C are to be selected such that for maximum glitch width the response of the RC circuit does not cross the threshold of the buffer.  
           [0006]    A waveform with positive glitch is shown in FIG. 3A. This waveform is input to the RC circuit (point X in FIG. 2A). The response of the RC circuit to the input waveform (at Y in FIG. 2A) is shown in FIG. 3B. The glitch free signal (at Z in FIG. 2A) is shown in FIG. 3C. A waveform with negative glitch is shown in FIG. 4A. This waveform is input to the RC circuit (point X in FIG. 2A). The response of the RC circuit to the input waveform (at Y in FIG. 2A) is shown in FIG. 3B. The glitch free signal (at Z in FIG. 2A) is shown in FIG. 4C.  
           [0007]    Glitch suppression by delay elements is the most widely used glitch suppression for application specific integrated circuit (ASIC) applications. A large number of patents exist on glitch suppression using delay elements. A typical glitch suppression mechanism is discussed below with reference to figures from Japanese patent number  4 , 287 , 512 . The glitch suppression mechanism for positive glitches disclosed in the patent is shown in FIGS. 6A to  6 E. The glitch suppression mechanism for negative glitches is shown in FIGS. 7A to  7 E.  
           [0008]    This prior art circuit essentially uses an SR (Set-Reset) flip-flop. The SR flip-flop is realized using two NAND gates NAND 1  and NAND 2 . The component DELBUF acts as a delay buffer. The delay buffer delays the input signal (signal at A in FIG. 5) by a fixed amount. The delay buffer is selected such that the delay inserted by it is equal to a maximum glitch width that is to be suppressed.  
           [0009]    [0009]FIG. 6A shows a waveform having a positive glitch. FIG. 6B shows the output of the delay buffer. The waveforms at the S and R inputs of the SR flip-flop are shown in FIGS. 6C and 6D, respectively. The output glitch free waveform is shown in FIG. 6E. FIG. 7A shows a waveform having a negative glitch. FIG. 7B shows the output of the delay buffer. The waveforms at the S and R inputs of the SR flip-flop are shown in FIGS. 7C and 7D respectively. The output glitch free waveform is shown in FIG. 7E.  
           [0010]    A prior art programmable glitch filter from U.S. Pat. No. 5,289,060 is shown in FIG. 8. The filter includes an SR flip-flop. The output of the flip-flop Q is set to logic 1 only when S is 1 and R is 0. Q is set to logic 0 only when S is at 0 and R is at 1. When S and R are at 0, the same logic state is maintained. A logic 1 on S and R is not allowed.  
           [0011]    A programmable delay buffer (represented as “PROGRAMMABLE DELAY” in FIG. 8) provides a delay which is programmable to a pre-determined value. This block delays the input signal at A to a programmable value. The incrementally delayed outputs of the programmable delay are fed to the AND gate and the bubbled AND gate (BAND) (the inputs of this logic element are first inverted and then logically ANDed). The output of the AND gate is 1 only when all the inputs are at logic 1. The output of the BAND gate is at logic 1 only when all the inputs are at logic 0.  
           [0012]    The glitch suppression mechanism for positive pulses is shown in FIGS. 9A to  9 E. FIG. 9A shows the waveform having positive glitches. FIG. 9B shows the waveform after maximum programmed delay at In. The output of the AND gate is shown in FIG. 9C, and the output of the BAND gate is shown in FIG. 9D. The glitch free output present at Q of SR flip-flop is shown in FIG. 9E.  
           [0013]    The glitch suppression mechanism for negative pulses is shown in FIGS. 10A to  10 E. FIG. 10A shows the waveform having negative glitches. FIG. 10B shows the waveform after a maximum programmed delay at In. The output of the AND gate is shown in FIG. 10C, and the output of the BAND gate is shown in FIG. 10D. The glitch free output present at Q of the SR flip-flop is shown in FIG. 10E.  
           [0014]    The above prior art devices all use a delay element to delay the signal. The delay signal and the original signal are compared. The output of the glitch filter is assigned to the input only when both the inputs have same value. The delay elements are implemented using buffers, and the existing glitch suppression techniques work fine for glitches of small pulse widths (i.e., tens of ns). Yet, if the glitch width is on the order of a few hundreds of microseconds or a few milliseconds, glitch suppression using the above techniques become very difficult. This is mainly because implementing a delay element to delay the signal by a few hundred microseconds may be very difficult.  
         SUMMARY OF THE INVENTION  
         [0015]    An object of this invention is to obviate the above drawbacks and provide a programmable glitch filter which can suppress glitch width on the order of a few hundred microseconds or a few milliseconds.  
           [0016]    This and other objects, features and advantages of the invention are provided by a glitch filter including storage means for storing a current state, which is the output of the filter. The output of the storage means is connected to one input of a state comparator, and the other input of the state comparator is connected to the input signal. A programmable clock delay means, which may provide a required duration independent of the technology of implementation, is connected between the state comparator and the storage means. The arrangement of the glitch filter may be such that the input signal is stored as the new current state in the storage means only if the input signal changes and then remains unchanged for the programmed duration.  
           [0017]    The means for providing a programmable clock delay may include a counter for counting clock pulses to provide a time delay. A control input of the counter may be connected to the output of the state comparator. Further, an output of the counter may be connected to one input of a digital delay comparator. The other input of the delay comparator may receive a digital value corresponding to the maximum glitch width to be filtered. Also, an output of the delay comparator may be connected to the input of the storage means. The counter may be enabled if the input to the glitch filter is not equal to the output of the storage means, and the counter may be initialized when the input of the glitch filter is equal to the output of the storage means.  
           [0018]    A multiplexer may be provided at the output of the storage means which also receives the input signal at an input thereof and the programmable digital value for the desired maximum glitch width at its control input. An arrangement of the multiplexer is such that when the programmed digital value is zero, the input signal is fed to the output of the multiplexer. Also, when the value is not zero, the storage means output is fed to the output of the multiplexer. The number of bits used for the counter and the digital delay comparator depends upon the desired range of programmable digital values necessary for maximum glitch width.  
           [0019]    A method aspect of the invention for filtering glitches includes storing a current state, which is the final output, and comparing the current state with the input signal. Further, a programmable delay is enabled whenever the input signal is different from the stored current state, and the programmable delay is initialized whenever the input signal is the same as the stored current state. The method may also include making the stored current state equal to the input signal if the programmed delay is complete.  
           [0020]    More specifically, the programmable delay may be obtained by counting clock pulses, comparing the counted clock pulses with a digital value corresponding to the maximum glitch width, and generating a signal indicating completion of programmed delay when the counted clock pulses become equal to the digital value. The counting may be enabled only if the input signal is not equal to the stored output state, and counting may be initialized whenever the input signal is equal to the stored output state. Also, the filtering of glitches may be enabled when the digital value for desired glitch width is non-zero, and it may be disabled when the digital value is zero. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    The invention will now be described with reference to the accompanying drawings, in which:  
         [0022]    [0022]FIG. 1 is a timing diagram illustrating a glitch;  
         [0023]    [0023]FIG. 2A is a schematic diagram of a conventional RC circuit for suppressing glitches according to the prior art;  
         [0024]    [0024]FIGS. 2B, 2C and  2 D are timing diagrams showing the step input in the RC circuit of FIG. 2A, response of the RC circuit and the waveform at the output of the buffer, respectively;  
         [0025]    [0025]FIGS. 3A to  3 C are timing diagrams showing glitch suppression mechanisms for positive glitches for the RC circuit of FIG. 2A;  
         [0026]    [0026]FIGS. 4A to  4 C are timing diagrams showing the glitch suppression mechanism for negative glitches for the RC circuit of FIG. 2A;  
         [0027]    [0027]FIG. 5 is a schematic diagram of a prior art glitch suppression device described in Japanese Patent No. 4,287,512 using delay elements for an ASIC application;  
         [0028]    [0028]FIGS. 6A to  6 E are timing diagrams showing the glitch suppression mechanism for positive glitches for the ASIC application of FIG. 5;  
         [0029]    [0029]FIGS. 7A to  7 E are timing diagrams illustrating the glitch suppression mechanism for negative glitches for the ASIC application of FIG. 5;  
         [0030]    [0030]FIG. 8 is a schematic diagram showing a prior art programmable glitch filter described in U.S. Pat. No. 5,289,060;  
         [0031]    [0031]FIG. 9A to  9 E are timing diagrams showing the glitch suppression mechanism for positive pulses of the programmable glitch filter of FIG. 8;  
         [0032]    [0032]FIGS. 10A to  10 E are timing diagrams illustrating the glitch suppression mechanism for negative pulses of the programmable glitch filter of FIG. 8;  
         [0033]    [0033]FIG. 11 is a schematic block diagram of a programmable glitch filter according to the invention;  
         [0034]    [0034]FIG. 12 is a schematic block diagram showing the programmable glitch filter of FIG. 11 in further detail;  
         [0035]    [0035]FIG. 13 is a schematic diagram showing the state comparator of FIG. 11 in further detail;  
         [0036]    [0036]FIG. 14 is a schematic diagram showing the programmable clock delay of FIG. 11 in further detail;  
         [0037]    [0037]FIG. 15 is a schematic diagram showing the counter of FIG. 14 in further detail;  
         [0038]    [0038]FIG. 16 is a schematic diagram showing the digital delay comparator of FIG. 14 in further detail;  
         [0039]    [0039]FIG. 17 is a schematic diagram showing the storage element of FIG. 11 in further detail;  
         [0040]    [0040]FIG. 18 is a timing diagram illustration operation the programmable glitch filter of FIG. 11 for positive glitches; and  
         [0041]    [0041]FIG. 19 is a timing diagram illustrating operation the programmable glitch filter of FIG. 11 for positive glitches. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0042]    As noted above, FIGS.  1  to  10 E describe prior art devices and techniques. The present invention will now be explained more fully with reference to FIGS.  11  to  17 . Referring to FIG. 11, a state comparator (SC) receives the input signal at one input. It also receives the current output state from the output of a storage element (SE) at its other input. Whenever the input signal is different from the current stored state, the output of the state comparator (SC) activates a counter control signal to enable a programmable clock delay circuit (PCD). The programmable clock delay circuit (PCD) begins counting clock pulses received at its clock input.  
         [0043]    The programmable clock delay circuit (PCD) also receives a required value of maximum glitch width at its program input. If the counter control signal remains active for a number of clock pulses equal to the required value of maximum glitch width, the change state output from the programmable clock delay circuit (PCD) is activated. This causes the storage element (SE) to change its state to the value of the input signal, which also changes the output of the filter.  
         [0044]    At this point the current stored state becomes equal to the input signal, which causes state comparator (SC) to deactivate the counter control and thereby initialize the programmable delay circuit (PCD). If the input signal does not remain stable for the duration of the number of clock pulses equal to the required value of maximum glitch width, the counter control is deactivated by the state comparator (SC). This is done to initialize the programmable clock delay circuit (PCD) before the change state output can become active. Hence, a glitch (which is a change of state before the programmed value of delay) will not cause the storage element (SE) to change its state and, therefore, the output remains the same.  
         [0045]    Turning now to FIG. 12, a multiplexer (M) is added at the output of the storage element (SE). The multiplexer (M) receives the output of the storage element (SE) at one of its inputs while the other input receives the input signal. The control input of the multiplexer (M) is connected to the desired value of maximum glitch width. If the desired value of the maximum glitch width is zero, the multiplexer (M) connects the input signal directly to the output of the filter, thereby suppressing the glitch filtering. If, however, the maximum glitch width value is not zero, the multiplexer (M) connects the output of storage element (SE) to the output of the filter and thereby enables the filtering operation.  
         [0046]    The state comparator (SC) is shown more particularly in FIG. 13. This circuit is a simple two-input exclusive-or gate (XOR) which receives the input signal and the stored current state at its two inputs. The exclusive-OR gate (XOR) generates the counter control signal at its output whenever the two inputs are unequal.  
         [0047]    Referring now to FIG. 14, the internal structure of the programmable clock delay circuit (PCD) is shown. A digital counter (C) receives the counter control signal at its enable input, a clock signal at its clock input, and a reset signal at its reset input. The digital value representing the current count value of the counter is connected to one input of a digital delay comparator (DDC). Further, the digital value corresponding to the clock count for the desired maximum glitch width is received at the other input of the digital delay comparator (DDC). The counter control signal is then activated, and the counter is enabled and counts clock pulses received at its clock input. When the count value becomes equal to the corresponding count for desired maximum glitch width, the digital delay comparator (DDC) activates the change state signal.  
         [0048]    The internal structure of the digital counter (C) is further illustrated in FIG. 15. When counter_control is at logic 0, the output of AND gates AN 0  to AN 7  is at logic 0 and count_value is loaded with 0x00 on every rising clock edge. When counter_control is at logic 1, the output of the adder ADDER is shifted into the into D flip-flops DF 0  to DF 7  on every rising clock edge. The adder increments the current count_value by one. This is done by feeding the count value and 0x01 to the inputs of the adder. The count value +1 is assigned to the count value on every rising clock edge. Hence, the counter increments the count value on every rising clock edge when counter_control is at logic 1, and count_value is loaded with 0x00 on every rising clock edge when counter_control is at logic 0.  
         [0049]    The internal structure of the digital delay comparator (DDC) is shown in FIG. 16. The bit  0  of count_value and noise_suppression_width is fed to XNOR 0 , bit  1  to XNOR 1 , and so on. Change_state is at logic 1 only when count_value and noise_suppression_width are equal. Otherwise, it is at logic 0. Furthermore, the internal structure of the storage element (SE) is shown in FIG. 17. The output of DFF toggles on rising clock edges only when change_state is at logic 1. Otherwise, the same logic state is maintained at the output of DFF.  
         [0050]    Operation of the programmable glitch suppression filter is shown in FIG. 18. In the example, the value of noise_suppression_width is assumed to be 4, which suppresses a glitch whose maximum width is 5 clock cycles. When there is a glitch of 3 clock cycles, counter_control is HIGH for three cycles and the count is counted up to a value of 3. When the glitch disappears, counter_control goes to logic 0 and count_value is loaded with 0. The output state remains unchanged.  
         [0051]    When the data changes (for the second time in FIG. 18), counter_control goes to logic 1. Count_value increments on every rising clock edge. When the count_value reaches 4, change_state is also forced to logic 1. This toggles the logic state of data_out. Data_out now changes to logic 0. Since the logic state on data_in and data_out is the same, counter_control is forced to logic 0 and the counter_value is loaded with 0 on every rising clock edge. An example for a negative glitch may be seen in FIG. 19, in which the circuit operates exactly the same way as for positive glitch, described above.  
         [0052]    It may be noted that the programmable glitch filter functions as follows. The filter requires a fast clock (typically at least 5 times faster than the signal transitions, for example). When the filter is initialized or turned on, power on all the internal variables counter_control, change_state, and data_out are set to zero. To enable the filtering, noise suppression width &lt;7:0&gt; (which is a binary data bus) must have a value other than zero.  
         [0053]    When noise suppression_width &lt;7:0&gt; is zero, data_in is fed to filtered_data_out and filtering is disabled. The storage element has a state machine inside it which changes the logic state of data_out only when change_state is 1. The programmable delay is enabled only when counter_control is at logic 1. If the counter_control is at logic 0, the programmable delay is initialized on every rising clock edge.  
         [0054]    The change_state signal is forced to logic 1 only when the logic state on the input signal remains different from the state of data_out for a time which is equal to that held in noise_suppression width&lt;7:0&gt;. Counter_control is at logic 1 only when the logic state on data_in and data_out is different. Otherwise, it is 0. The data input to the filter should be synchronous to the system clock. The asynchronous data is to be synchronized before being fed to this module.