Abstract:
A circuit capable of providing electrostatic discharge (ESD) protection, the circuit comprising a first set of power rails comprising a first high power rail and a first low power rail, a first interface circuit between the first set of power rails, the first interface circuit having at least one gate electrode, a first ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, and a second ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, the first ESD device and the second ESD device being configured to maintain a voltage level at the at least one gate electrode of the first interface circuit at approximately a ground level when ESD occurs.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/825,152, filed Sep. 11, 2006. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to electrostatic discharge (ESD) protection and, more particularly, to circuits for providing ESD protection in a multi-power domain. 
     A semiconductor integrated circuit (IC) is generally susceptible to electrostatic discharge (ESD), which may damage or destroy the IC. ESD generally refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a relatively large amount of current passes through a part of the IC. The current surge may exceed what the IC can normally tolerate and may cause undesirable impact to the IC&#39;s operation or damage the IC or its components. To prevent ESD damages, many ICs have ESD protection circuit or circuits and may rely on different approaches of ESD protection for different applications. 
     In a large electronic system having multiple sub-systems, such as in a computer system, there are generally a number of power supplies providing different power levels. The sub-systems, such as ICs and chips in the system, often require separate power supplies with different voltages. And interface circuits may exist to provide communications of signals between two sub-systems. However, interface circuits between the sub-systems, if not properly protected, are susceptible to damages by ESD.  FIG. 1  is an exemplary circuit diagram of a conventional multi-power system  10  with interface circuits. Referring to  FIG. 1  as an example, the system  10  includes rail-to-rail ESD clamp circuits  11  and  12  for ESD protection. However, when ESD occurs, because power supplies in the system  10  remain floating, a p-type metal-oxide-semiconductor (“PMOS”) transistor Mp is turned on and supplies an ESD current I ESD  toward an n-type metal-oxide-semiconductor (“NMOS”) transistor Mn of an interface device  15 . The ESD current may damage or degrade the gate oxide of the NMOS transistor Mn. According to the example, ESD can easily occur in a system having multiple power supplies, and it may be desirable to provide ESD protection circuits to protect interface circuits from being damaged by ESD. Furthermore, it is necessary that the ESD clamp circuits meet the requirements of different power voltages. 
     BRIEF SUMMARY OF THE INVENTION 
     Examples of the present invention may provide a circuit capable of providing electrostatic discharge (ESD) protection, the circuit comprising a first set of power rails comprising a first high power rail and a first low power rail, a first interface circuit between the first set of power rails, the first interface circuit having at least one gate electrode, a first ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, and a second ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, the first ESD device and the second ESD device being configured to maintain a voltage level at the at least one gate electrode of the first interface circuit at approximately a ground level when ESD occurs. 
     Some examples of the present invention may provide a circuit capable of providing electrostatic discharge (ESD) protection that comprises a first set of power rails further comprising a first high power rail and a first low power rail, a second set of power rails further comprising a second high power rail and a second low power rail, a first interface circuit between the first set of power rails further comprising at least one gate electrode, a second interface circuit between the second set of power rails further comprising an output connected to the at least one gate electrode, and an ESD device further comprising a terminal connected to the at least one gate electrode of the first interface circuit, the ESD device being capable of pulling a voltage level at the at least one gate electrode to a relatively grounded level in response to an ESD stress occurring on the second high power rail as one of the first set of power rails being relatively grounded, or occurring on the first high power rail as one of the second set of power rails being relatively grounded. 
     Examples of the present invention may also provide a circuit capable of providing electrostatic discharge (ESD) protection that comprises a first set of power rails further comprising a first high power rail and a first low power rail, a second set of power rails further comprising a second high power rail and a second low power rail, a first interface circuit between the first set of power rails further comprising a gate electrode and a first terminal, a second interface circuit between the second set of power rails further comprising an output connected to the gate electrode, the second interface circuit being capable of pulling a voltage level at the gate electrode to that of the second low power rail in response an ESD stress, and an ESD device further comprising a terminal connected to the first terminal of the first interface circuit, the ESD device being capable of pulling a voltage level at the first terminal to that of the first low power rail or the second low power rail. 
     Examples of the present invention may further provide a circuit capable of providing electrostatic discharge (ESD) protection that comprises a first set of power rails further comprising a first high power rail and a first low power rail, a second set of power rails further comprising a second high power rail and a second low power rail, a first interface circuit between the first set of power rails further comprising a gate electrode, a second interface circuit between the second set of power rails further comprising an output connected to the gate electrode, and an ESD device further comprising a silicon-controlled rectifier (SCR) and a transistor capable of triggering the SCR in response to an ESD stress occurring on one of the first high power rail and the second high power rail. 
     Additional features and advantages of the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. 
       In the drawings: 
         FIG. 1  is a circuit diagram of a conventional multi-power system; 
         FIG. 2A  is a circuit diagram of an ESD protection circuit consistent with an example of the present invention; 
         FIG. 2B  is a circuit diagram of an ESD protection circuit consistent with another example of the present invention; 
         FIG. 2C  is a circuit diagram of an ESD protection circuit consistent with yet another example of the present invention; 
         FIG. 2D  is a circuit diagram of an ESD protection circuit consistent with still another example of the present invention; 
         FIG. 2E  is a circuit diagram of an ESD protection circuit consistent with yet still another example of the present invention; 
         FIG. 3A  is a circuit diagram of an ESD protection circuit consistent with an example of the present invention; 
         FIG. 3B  is a circuit diagram of an ESD protection circuit consistent with another example of the present invention; 
         FIG. 3C  is a circuit diagram of an ESD protection circuit consistent with yet another example of the present invention; 
         FIG. 3D  is a circuit diagram of an ESD protection circuit consistent with still another example of the present invention; 
         FIG. 3E  is a circuit diagram of an ESD protection circuit consistent with yet still another example of the present invention; 
         FIG. 4A  is a circuit diagram of an ESD protection circuit consistent with an example of the present invention; 
         FIG. 4B  is a circuit diagram of an ESD protection circuit consistent with another example of the present invention; and 
         FIG. 4C  is a circuit diagram of an ESD protection circuit consistent with yet another example of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
       FIG. 2A  is a circuit diagram of an ESD protection circuit  20  consistent with an example of the present invention. Referring to  FIG. 2A , the ESD protection circuit  20  includes a first ESD clamp circuit  21 , a second ESD clamp circuit  22 , a third ESD clamp circuit  23  and a fourth ESD clamp circuit  24 . ESD clamp circuits  21 ,  22  and  23  provide rail-to-rail ESD protection. The first ESD clamp  21 , connected between a VDD 1  rail and a VSS 1  rail, is capable of protecting a first interface circuit  27  from an ESD stress. The second ESD clamp circuit  22  is connected between the VSS 1  rail and a VSS 2  rail. The third ESD clamp circuit  23 , connected between a VDD 2  rail and the VSS 2  rail, is capable of protecting a second interface circuit  28  from an ESD stress. The ESD clamp circuit  22  includes, for example, at least one diode. The fourth ESD clamp circuit  24  is capable of protecting a PMOS transistor  28   p  and an NMOS transistor  28   n  of the second interface circuit  28  from gate oxide damage due to an ESD current flowing from a PMOS transistor  27   p  of the first interface circuit  27 . Although in the present example each of the first interface circuit  27  and the second interface circuit  28  includes at least one inverter, skilled persons in the art will understand that the interface circuits  27  and  28  may include other devices. 
     The fourth ESD clamp circuit  24  further includes an NMOS transistor  24   n  and a PMOS transistor  24   p . The NMOS transistor  24   n  includes a gate and a bulk, both of which (not numbered) are connected to the VSS 2  rail, a source (not numbered) connected to a node G between an output of the first interface circuit  27  and an input of the second interface circuit  28 , and a drain (not numbered) connected to the VDD 2  rail. Skilled persons in the art will understand that the source and drain terminals of a MOS transistor may be exchangeable. Since the gate of the NMOS transistor  24   n  is connected to the VSS 2  rail, the NMOS transistor  24   n  is turned off during normal operation and therefore does not adversely affect the normal system operation. The PMOS transistor  24   p  includes a gate (not numbered) connected to the VDD 2  rail, a source and a bulk, both of which (not numbered) are connected to the node G, and a drain (not numbered) connected to the VSS 2  rail. Since the gate of the PMOS transistor  24   p  is connected to the VDD 2  rail, the PMOS transistor  24   p  is turned off during normal operation. 
     If an ESD stress occurs on the VDD 1  rail and the VDD 2  rail is relatively grounded, an ESD current (not shown) is conducted by the ESD clamp circuits  21 ,  22  and  23  from the VDD 1  rail through the VSS 1  and VSS 2  rails to the VDD 2  rail. Since the ESD current flows through the VSS 2  rail, the voltage level of VSS 2  is greater than that of the grounded VDD 2 . Furthermore, since the gate and source of the NMOS transistor  24   n  are connected to the VSS 2  and VDD 2  rails, the NMOS transistor  24   n  is turned on due to a significant gate-to-source voltage. The voltage level at the node G, i.e., Vg, is pulled to the grounded VDD 2  level. As a result, the risk of gate oxide damage due to a large stress at the gate of the PMOS transistor  28   p  is avoided. 
     If an ESD stress occurs on the VDD 1  rail and the VSS 2  rail is relatively grounded, an ESD current (not shown) is conducted by the ESD clamp circuits  21  and  22  from the VDD 1  rail through the VSS 1  rail to the VSS 2  rail. Since VDD 2  is floating, the PMOS transistor  24   p  is turned on. The voltage level of Vg is pulled to the grounded VSS 2 . 
       FIG. 2B  is a circuit diagram of an ESD protection circuit  20 - 1  consistent with another example of the present invention. Referring to  FIG. 2B , the ESD protection circuit  20 - 1  is similar to the ESD protection circuit  20  illustrated in  FIG. 2A  except the addition of resistors R 1 , R 2  and R 3 . The first resistor R 1  is connected between the output of the first interface circuit  27  and the input of the interface circuit  28 . The second resistor R 2  is connected between the source of the PMOS transistor  28   p  and the VDD 2  rail. The third resistor R 3  is connected between the source of the NMOS transistor  28   n  and the VSS 2  rail. 
     Given that the PMOS transistor  24   p  has a channel resistance R 4 , the resistors R 1 , R 4  and R 3  form a first voltage ladder. Due to voltage division, the voltage at the tap node G, i.e., Vg, is reduced as compared to that without the resistors R 1  and R 3 . As a result, the NMOS transistor  28   n  is further protected against an ESD stress on the VDD 1  rail as the VSS 2  rail is relatively grounded. Similarly, given that the NMOS transistor  24   n  has a channel resistance R 5 , the resistors R 2 , R 5  and R 1  form a second voltage ladder. Due to voltage division, the voltage at a tap node S, i.e., Vs, is reduced as compared to that without the resistors R 2  and R 1 . As a result, the PMOS transistor  28   p  is further protected against an ESD stress on the VDD 1  rail as the VDD 2  rail is relatively grounded. 
       FIG. 2C  is a circuit diagram of an ESD protection circuit  20 - 2  consistent with yet another example of the present invention. Referring to  FIG. 2C , the ESD protection circuit  20 - 2  is similar to the ESD protection circuit  20 - 1  illustrated in  FIG. 2B  except a PMOS transistor  25   p  and an NMOS transistor  25   n , which replace the resistors R 2  and R 3  illustrated in  FIG. 2B , respectively. Each of the PMOS transistor  25   p  and the NMOS transistor  25   n  is turned on during normal operation of the system, and functions to serve as a resistor in response to an ESD stress. 
       FIG. 2D  is a circuit diagram of an ESD protection circuit  20 - 3  consistent with still another example of the present invention. Referring to  FIG. 2D , the ESD protection circuit  20 - 3  is similar to the ESD protection circuit  20 - 1  illustrated in  FIG. 2B  except a self-biased current trigger (“SBCT”) circuit  26 . The SBCT circuit  26  includes an NMOS transistor  26   n  and the second ESD clamp circuit  22 . The NMOS transistor  26   n  includes a gate (not numbered) connected to the VSS 1  rail through a resistor (not numbered). During normal operation of the system, the NMOS transistor  26   n  is turned off. During an ESD stress, the gate of the NMOS transistor  26   n  is biased due to an ESD current flowing through the second ESD clamp circuit  22 . The NMOS transistor  26   n  is turned on, which pumps the source of the NMOS transistor  28   n , reducing the gate to source voltage of the NMOS transistor  28   n  and in turn lowering the risk of gate oxide damage. The SBCT circuit and the pumping structure have been disclosed in U.S. Provisional Application Ser. No. 60/824,795, entitled “CDM ESD Protection Circuit Using Self-Biased Current Trigger Technique and Pumping Source Mechanism”, filed Sep. 7, 2006 by Shih-Hung Chen and Ming-Dou Ker, the same inventors of the present application. The disclosure of the above application is herein incorporated by reference. 
       FIG. 2E  is a circuit diagram of an ESD protection circuit  20 - 4  consistent with yet still another example of the present invention. Referring to  FIG. 2E , the ESD protection circuit  20 - 4  is similar to the ESD protection circuit  20 - 3  illustrated in  FIG. 2D  except the addition of another SBCT circuit  29 . The SBCT circuit  29  protects the PMOS transistor  28   p  from gate oxide damage. 
       FIG. 3A  is a circuit diagram of an ESD protection circuit  30  consistent with an example of the present invention. Referring to  FIG. 3A , the ESD protection circuit  30  includes ESD clamp devices  31   p ,  31   n ,  32   p  and  32   n , a first inverter  31 , a first RC network including a resistor R 31  and a capacitor C 31 , a second inverter  32 , and a second RC network including a resistor R 32  and a capacitor C 32 . The ESD clamp device  31   p  includes a gate (not numbered) connected to an output of the first inverter  31 , a source and a bulk, both of which (not numbered) are connected to the VDD 1  rail, and a drain (not numbered) connected to the source of the PMOS transistor  27   p . The ESD clamp device  31   n  includes a gate (not numbered) connected to an input of the first inverter  31 , a source and a bulk, both of which (not numbered) are connected to the VSS 1  rail, and a drain (not numbered) connected to the source of an NMOS transistor  37   n . The ESD clamp device  32   p  includes a gate (not numbered) connected to an output of the second inverter  32 , a source and a bulk, both of which (not numbered) are connected to the VDD 2  rail, and a drain (not numbered) connected to a drain (not numbered) of the ESD clamp device  32   n . The ESD clamp device  32   n  further includes a gate (not numbered) connected to the output of the second inverter  32 , and a source and a bulk, both of which (not numbered) are connected to the VSS 1  rail. 
     Each of the first RC network and the second RC network has a delay constant longer than the duration of ESD pulses and shorter than the rising time of a system signal. In one example, the delay constant is in the order of micro seconds relative to ESD pulses in the order of nanoseconds and a system signal in the order of mini seconds. 
     During normal operation of the system, a node A maintains at a high voltage level due to the shorter delay constant, which turns on the ESD clamp devices  31   p  and  31   n . Similarly, a node D maintains at a high voltage level due to the shorter delay constant, which turns on the ESD clamp device  32   p  and turns off the ESD clamp device  32   n . As a result, the ESD clamp devices  31   p ,  31   n ,  32   p  and  32   n  do not adversely affect the normal system operation. 
     During an ESD stress, the node A maintains at a low voltage level due to the longer delay constant, which turns off the ESD clamp devices  31   p  and  31   n . Similarly, the node D maintains at a low voltage level due to the longer delay constant, which turns off the ESD clamp device  32   p  and turns on the ESD clamp device  32   n . If an ESD stress occurs on the VDD 1  rail and the VDD 2  rail is relatively grounded, given the voltage level on the VDD 2  rail being approximately zero, the voltage level on the VDD 1  rail, i.e., V VDD1 , is calculated as follows.
 
 V   VDD1   =V   hA   +V   hB   +V   hC   +I   ESD  ( R   A   +R   B   +R   C )
 
     wherein V hA , V hB , and V hC  are the holding voltages of the ESD clamp circuits  21 ,  22  and  23 , respectively, I ESD  is an ESD current conducted through the ESD clamp circuits  21 ,  22  and  23 , and R A , R B  and R C  are the resistances of the ESD clamp circuits  21 ,  22  and  23 , respectively. 
     Likewise, the voltage levels on the VSS 1  and VSS 2  rails, i.e., V VSS1  and V VSS2 , are respectively calculated as follows.
 
 V   VSS1   =V   hB   +V   hC   +I   ESD  (R B   +R   C )
 
 V   VSS2   =V   hC   +I   ESD  R C  
 
     Since during the ESD stress the gates (not numbered) of a PMOS transistor  37   p  and the NMOS transistor  37   n  are connected to a floating power source, the PMOS transistor  37   p  is turned on and the NMOS transistor  37   n  is turned off. Consequently, an NMOS transistor  27   n  is turned on and the voltage level at a node B, i.e., V B , is pulled to V VSS1 , which is smaller than V VDD1  by (V hA +I ESD  R A ). As compared to the circuit  10  illustrated in  FIG. 1  wherein the NMOS transistor Mn is exposed to V VDD1 , the risk of gate oxide damage to the NMOS transistor  28   n  is alleviated. Similarly, the voltage level at a node C, i.e., V C , is also pulled to V VSS1 . 
     Furthermore, if an ESD stress occurs on the VDD 2  rail and the VDD 1  rail is relatively grounded, given the voltage level on the VDD 1  rail being approximately zero, the voltage level on the VDD 2  rail, i.e., V VDD2 , is calculated as follows.
 
 V   VDD2   =V   hC   +V   hB   +V   hA   +I   ESD  (R C   +R   B   +R   A )
 
     Likewise, the voltage levels on the VSS 2  and VSS 1  rails, i.e., V VSS2  and V VSS1 , are respectively calculated as follows.
 
 V   VSS2   =V   hB   +V   hA   +I   ESD  (R B   +R   A )
 
 V   VSS1   =V   hA   +I   ESD    R   A  
 
     Since ESD clamp device  32   p  is turned off and the ESD clamp device  32   n  is turned on, the voltage level V C  is pulled to V VSS1 , which is smaller than V VDD2  by (V hC +V hB +I ESD  (R C +R B )). As compared to the circuit  10  illustrated in  FIG. 1  wherein the PMOS transistor Mp is exposed to V VDD2 , the risk of gate oxide damage to the PMOS transistor  28   p  is alleviated. Similarly, the voltage level V B  is also pulled to V VSS1 . 
       FIG. 3B  is a circuit diagram of an ESD protection circuit  30 - 1  consistent with another example of the present invention. Referring to  FIG. 3B , the ESD protection circuit  30 - 1  is similar in structure to the ESD protection circuit  30  illustrated in  FIG. 3A  except inverters  33  and  34 . The inverter  33  is connected between the input of the inverter  31  and the gate of the ESD clamp device  31   p . The inverter  34  is connected between the input of the inverter  32  and the NMOS  32   n . The inverters  33  and  34 , disposed closer to the ESD clamp device  31   p  and the ESD clamp device  32   n , respectively, may help enhance the driving efficiency. 
       FIG. 3C  is a circuit diagram of an ESD protection circuit  30 - 2  consistent with yet another example of the present invention. Referring to  FIG. 3C , the ESD protection circuit  30 - 2  is similar to the ESD protection circuit  30 - 1  illustrated in  FIG. 3B  except an ESD clamp device  32   n - 1 , which includes a source (not numbered) connected to the VSS 2  rail. If an ESD stress occurs on the VDD 1  rail and the VDD 2  rail is relatively grounded, the voltage levels at the nodes B and C are respectively pulled to V VSS1  and V VSS2 . 
       FIG. 3D  is a circuit diagram of an ESD protection circuit  30 - 3  consistent with still another example of the present invention. Referring to  FIG. 3D , the ESD protection circuit  30 - 3  is similar to the ESD protection circuit  30 - 1  illustrated in  FIG. 3B  except that the gate (not numbered) of an ESD clamp device  35   n  is connected to the VSS 2  rail through a resistor R. The ESD clamp device  35   n , the resistor R and the ESD clamp circuit  22  form an SBCT circuit  35 . 
       FIG. 3E  is a circuit diagram of an ESD protection circuit  30 - 4  consistent with yet still another example of the present invention. Referring to  FIG. 3E , the ESD protection circuit  30 - 4  is similar to the ESD protection circuit  30 - 1  illustrated in  FIG. 3B  except that an ESD clamp device  36   p  replaces the ESD clamp device  32   n . The ESD clamp device  36   p  includes a PMOS transistor  36   p  further including a gate (not numbered) connected to an input of the inverter  34 . 
       FIG. 4A  is a circuit diagram of an ESD protection circuit  40  consistent with an example of the present invention. Referring to  FIG. 4A , the ESD protection circuit  40  includes a PMOS-triggered silicon-controlled rectifier (“SCR”), which further includes a PMOS transistor  38   p  integrated with an SCR  38   s . The PMOS transistor  38   p  includes a gate (not numbered) connected to the input of the inverter  31 . The SCR  38   s  includes an anode (P+ region) connected to the VDD 1  rail and a cathode (N+ region) connected to the VSS 2  rail. During normal operation, the PMOS transistor  38   p  is turned off. In response to an ESD stress, the PMOS transistor  38   p  is turned on to trigger the SCR  38   s  to conduct an ESD current from the VDD 1  rail to the VSS 2  rail, or vice versa. The MOS-triggered SCR circuit has been disclosed in, for example, U.S. Pat. No. 6,008,684 to Ker et al., one of the inventors of the present application. The disclosure of the above application is herein incorporated by reference. 
       FIG. 4B  is a circuit diagram of an ESD protection circuit  40 - 1  consistent with another example of the present invention. Referring to  FIG. 4B , the ESD protection circuit  40 - 1  includes an NMOS-triggered SCR, which further includes an NMOS transistor  41   n  integrated with an SCR  41   s . The NMOS transistor  41   n  includes a gate (not numbered) connected to an output of an inverter  40 . The SCR  41   s  includes an anode (P+ region) connected to the VDD 1  rail and a cathode (N+ region) connected to the VSS 2  rail. During normal operation, the NMOS transistor  41   n  is turned off. In response to an ESD stress, the NMOS transistor  41   n  is turned on to trigger the SCR  41   s  to conduct an ESD current from the VDD 1  rail to the VSS 2  rail, or vice versa. 
       FIG. 4C  is a circuit diagram of an ESD protection circuit  40 - 2  consistent with yet another example of the present invention. Referring to  FIG. 4C , the ESD protection circuit  40 - 2  is similar to the ESD protection circuit  40  illustrated in  FIG. 4A  except the addition of another PMOS-triggered SCR, which includes a PMOS transistor  42   p  integrated with an SCR  42   s . The PMOS transistor  42   p  includes a gate (not numbered) connected to the input of the inverter  32 . The SCR  42   s  includes an anode (P+ region) connected to the VDD 2  rail and a cathode (N+ region) connected to the VSS 1  rail. During normal operation, the PMOS transistor  42   p  is turned off. In response to an ESD stress, the PMOS transistor  42   p  is turned on to trigger the SCR  42   s  to conduct an ESD current from the VDD 2  rail to the VSS 1  rail, or vice versa. 
     It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims. 
     Further, in describing representative embodiments of the present invention, the specification may have presented the method and/or process of the present invention as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. In addition, the claims directed to the method and/or process of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the present invention.