Abstract:
Provided is related to a redundancy IO fuse circuit of a semiconductor device. The redundancy IO fuse circuit is advantageous to enhancing an overall processing speed of a redundancy operation by preventing a voltage drop by a threshold voltage due to an NMOS transistor, by reducing back bias effects, preventing a decrease of noise margins at an inverter connected to an IO bus, and by improving time delay property involved in current reduction according to variation of operation mode.

Description:
[0001]     This application relies for priority upon Korean Patent Application No. 2003-0069424 filed on Oct. 7, 2003, the contents of which are herein incorporated by reference in their entirety.  
       BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a redundancy IO (input/output) fuse circuit of a semiconductor device, and specifically, to a redundancy IO fuse circuit for overcoming signal delays arising from IO fuses employed in redundancy circuitry in a semiconductor device.  
         [0004]     2. Discussion of Related Art  
         [0005]     In a semiconductor device, it has been general to employ fuses in order to control IO (input/output) information to be repaired in a redundancy block. As a normal bit configuration of a semiconductor chip is ×8 or ×16, one repair line needs to be associated with four fuse boxes each of which includes a couple of fuses for setting high and low states.  
         [0006]      FIG. 1A  illustrates a conventional redundancy IO fuse circuit.  
         [0007]      FIG. 1B  is a circuit diagram of a region ‘A’ where a predetermined fuse is blown away in  FIG. 1A .  
         [0008]     Referring to  FIGS. 1A and 1B , the conventional redundancy IO fuse circuit includes first through fourth fuse boxes FB 1 ˜FB 4  for outputting a predetermined logic signal in accordance with states of an external repair signal REP and fuse cutoff, and first through fourth NMOS transistors N 1 ˜N 4 , connected between an external IO bus IOBUS and the first through fourth fuse boxes FB 1 ˜FB 4 , for transferring an IO information signal to the IO bus IOBUS in accordance with the external repair signal REP.  
         [0009]     The first fuse box FB 1  is constructed of a first fuse F 1  connected between an input terminal of the external repair signal REP and a drain node of the first NMOS transistor N 1 , and a second fuse connected between a ground voltage Vss and the drain node of the first NMOS transistor. The second through fourth fuse boxes FB 2 ˜FB 4  have the same structure with the first fuse box FB 1 , so will be omitted hereinafter.  
         [0010]     An operation of the conventional IO fuse circuit shown in  FIG. 1A  is as follows. First, a defect on a chipset is cured by means of a predetermined test procedure. While this, an alternative one of the first and second fuses F 1  and F 2  in the first through fourth fuse boxes FB 1 ˜FB 4  is cut off (or blown out). For example, if IO&lt;9&gt; is to be repaired, the second fuses F 2  each of the first and fourth fuse boxes FB 1  and FB 4  and the first fuses F 1  each of the second and third fuse boxes FB 2  and FB 3  are cut off to set an output of IO bus IOBUS&lt;0:3&gt; on ‘1001’.  
         [0011]     Therefore, when the repair signal REP becomes logically high, the first through fourth NMOS transistors N 1 ˜N 4  are turned on to output a logical-high signal of the repair signal REP or a logical-low signal of the ground voltage in accordance with fusing states from the first through fourth fuse boxes FB 1 ˜FB 4 . The output signal from the first through fourth fuse boxes FB 1 ˜FB 4  is transferred to the IO bus IOBUS&lt;0:3&gt; through the first through fourth NMOS transistors N 1 ˜N 4  that is being turned on.  
         [0012]     However, as illustrated in  FIG. 1B , when a power supply voltage Vcc is applied to the first NMOS transistor N 1  by the condition that the second fuse F 2  is cut off and the external repair signal REP is logically high, there is a problem as follows.  
         [0013]     First, it occurs a voltage drop by a threshold voltage of the NMOS transistor. Such a voltage drop causes the degradation of noise margins at an inverter connected to the IO bus, which is very disadvantageous to a low voltage chip operable under 1.8V of power supply voltage. Furthermore, the threshold voltage becomes higher due to a back bias effect of the NMOS transistor, making the noise margin of the inverter be degraded worse.  
         [0014]     In addition, increasing a bias level of the IO bus causes a current decrease therein by the operational property of the NMOS transistor turns to a saturation mode into a linear mode, which means it takes a longer time for charging nodes of the IO bus and thereby consumes time delays.  
         [0015]     Practically, a simulation result under the condition with Vcc=1.65V, slow skew, and 90° C. of temperature results in a transition time of 10 ns for changing the IO bus signal from low to high. And, it is difficult to obtain further improvement beyond about 1 ns although the NMOS transistor is enlarged in size. This time delay is regarded to as a very large value against an entire read/write time specification, acting as a serious factor degrading the performance of chip.  
       SUMMARY OF THE INVENTION  
       [0016]     The present invention is directed to a redundancy IO fuse circuit of a semiconductor device, capable of reducing a back bias drop by a threshold voltage of an NMOS transistor, preventing a decrease of noise margins, and improving time delay property involved in current reduction of the NMOS transistor.  
         [0017]     One aspect the present invention is to provide a redundancy Input/Output (IO) fuse circuit of a semiconductor device, including: a plurality of fuse boxes for outputting a predetermined logic signal in accordance with a repair signal and a fuse cutoff state; an inverter for outputting an inversed repair signal by receiving the repair signal; and a plurality of transmission gates for transferring the predetermined logic signal into an IO bus in accordance with the repair signal and the inversed repair signal.  
         [0018]     Another aspect of the present invention is to provide a redundancy IO fuse circuit of a semiconductor device, including: an inverter for inversing an external repair signal; a first fuse for transferring a ground voltage in accordance with a cutoff state; a second fuse for transferring a power supply voltage in accordance with a cutoff state; an NMOS transistor for transferring the ground voltage to an  10  bus in accordance with the repair signal; and a PMOS transistor for transferring the power supply voltage to the IO bus in accordance with the inversed repair signal provided from the inverter. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     A more complete understanding of the present invention may be had by reference to the following description when taken in conjunction with the accompanying drawings in which:  
         [0020]      FIG. 1A  illustrates a conventional redundancy IO fuse circuit;  
         [0021]      FIG. 1B  is a circuit diagram of a region A where a predetermined fuse is blown away in  FIG. 1A ;  
         [0022]      FIG. 2  illustrates a redundancy IO fuse circuit according to an embodiment of the present invention; and  
         [0023]      FIG. 3  illustrates a redundancy IO fuse circuit according to another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0024]     Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numerals refer to like elements throughout the specification.  
         [0025]      FIG. 2  illustrates a redundancy  10  fuse circuit according to an embodiment of the present invention.  
         [0026]     Referring to  FIG. 2 , the redundancy IO fuse circuit according to an embodiment of the present invention is comprised of an inverter I 10  for inversing a logic state of an external repair signal REP, first through fourth fuse boxes FB 10 ˜FB 40  for outputting a predetermined logic signal in accordance with states of the repair signal REP and fuse cutoff, and first through fourth transmission gates T 10 ˜T 40  for each transferring outputs of the first through fourth fuse boxes FB 10 ˜FB 40  into external IO buses IOBUS&lt;0:3&gt; in accordance with the repair signal REP and an inversed repair signal IREP by the inverter I 10 . The predetermined logic signal denotes logical high or logical low.  
         [0027]     The first fuse box FB 10  includes a first fuse F 10  connected between an input terminal of the repair signal REP and an output terminal of the first fuse box FB 10 , and a second fuse F 20  connected between a ground voltage Vss and the output terminal of the first fuse box FB 10 . The second through fourth fuse boxes FB 20 ˜FB 40  have the same structure with the first fuse box FB 10 . Here, the first fuse F 10  may be connected between a power supply voltage Vcc and the output terminal of the first fuse box FB 10 .  
         [0028]     The first transmission gate T 10  is connected between the IO bus (e.g., IOBUS&lt;1&gt;) and the output terminal of the first fuse box FB 10 , being constructed of an NMOS transistor controlled by the repair signal REP and a PMOS transistor controlled by the inversed repair signal IREP. The second through fourth transmission gates T 20 ˜T 40  have the same construction with the first transmission gate T 10 .  
         [0029]     Now will be described about an operation of the redundancy IO fuse circuit constituted as aforementioned according to an embodiment of the present invention.  
         [0030]     When the external repair signal REP becomes logically high, the first and fourth transmission gates T 10  and T 40  are turned on and the IO bus signal IOBUS&lt;0:3&gt;are determined to be assigned thereto in accordance with fuse cutoff states of the first and fourth fuse boxes FB 10  and FB 40 . In this embodiment, a time delay is not generated by the PMOS transistor during logically high, while by the NMOS transistor during locally low.  
         [0031]     For example, in order to transfer a logical-high signal to the IO bus IOBUS, the second fuse F 20  connected to the ground voltage Vss is cut off while the first fuse F 10  is maintained. When the external repair signal REP is applied with logically high thereto, the NMOS and PMOS transistors of the first transmission gates T 10  are turned on. Thus, the logical-high signal is transferred to the IO bus IOBUS by way of the first fuse F 10  of the first fuse box FB 10  and the first transmission gate T 10 . At this time, as the PMOS transistor transfers the power supply voltage to the IO bus without a voltage drop, there is no reduction of noise margin. Moreover, since the PMOS transistor is free from a back bias effect and normally operable in a saturation mode, a current decrease does not occur to let a switching time delay disappeared. As a result, it solves the problem due to the conventional NMOS transistor.  
         [0032]     In order to transfer a logical-low signal to the IO bus IOBUS, the first fuse F 10  connected to the input terminal of the repair signal REP is cut off while the second fuse F 20  is maintained. When the external repair signal REP is applied with logically high thereto, the NMOS and PMOS transistors of the first transmission gates T 10  are turned on. Thus, the logical-low signal is transferred to the IO bus IOBUS by way of the second fuse F 20  of the fuse box FB 10  and the first transmission gate T 10 . At this time, although the PMOS transistor cannot transfer the power supply voltage and there is a back bias effect, the NMOS transistor well transfers the logical-low signal to the IO bus. And, since the NMOS transistor is operable in a saturation mode, there is no switching time delay.  
         [0033]     According to a simulation result under the condition of Vcc=1.65V, slow skew, and 90° C. of temperature, it takes a transition time about 4 ns for changing the IO bus signal from low to high.  
         [0034]     As another embodiment of the present invention, it is available to connect PMOS transistors to fuses linked to the power supply voltage and to connect NMOS transistors to fuses linked to the ground voltage, which can reduce time delays.  
         [0035]      FIG. 3  illustrates a redundancy  10  fuse circuit according to another embodiment of the present invention.  
         [0036]     Referring to  FIG. 3 , the redundancy IO fuse circuit includes an inverter I 100  for inversing a logic state of the repair signal REP, first fuses F 100   a ˜F 100   d  for supplying the ground voltage Vss in accordance with their cutoff states, second fuses F 200   a ˜F 200   d  for supplying the power supply voltage Vcc in accordance with their cutoff states, NMOS transistors N 100   a ˜N 100   d  for transferring the ground voltage Vss to the IO buses IOBUS&lt;0:3&gt; in accordance with a logic state of the repair signal REP, and PMOS transistors P 200   a ˜P 200   d  for transferring the power supply voltage Vcc to the IO buses IOBUS&lt;0:3&gt; in accordance with a logic state of the inversed repair signal IREP.  
         [0037]     With the structure of the redundancy fuse circuit, when the repair signal REP is applied thereto after cutting away a target fuse of the fuses F 100   a ˜F 100   d  or F 200   a ˜F 200   d , the NMOS and PMOS transistors are turned on to transfer voltage states, which are connected to fuses that are not cut off, into IO buses IOBUS corresponding thereto.  
         [0038]     In general, as a normal semiconductor chip is operable with a bit configuration of ×8 or ×16, one repair line needs to be associated with four fuse boxes. Therefore, the redundancy IO fuse circuit according to another embodiment of the present invention, as shown in  FIG. 3 , is constructed as such including the inverter I 100  for inversing a logic state of the repair signal REP, the first fuses F 100   a ˜F 100   d  for supplying the ground voltage Vss in accordance with their cutoff states, the second fuses F 200   a ˜F 200   d  for supplying the power supply voltage Vcc in accordance with their cutoff states, the NMOS transistors N 100   a ˜N 100   d , connected to the first fuses F 100   a ˜F 100   d , for transferring the ground voltage Vss to the IO buses IOBUS&lt;0:3&gt; in accordance with a logic state of the repair signal REP, and the PMOS transistors P 200   a ˜P 200   d , connected to the second fuses F 200   a ˜F 200   d , for transferring the power supply voltage Vcc to the IO buses IOBUS&lt;0:3&gt; in accordance with a logic state of the inversed repair signal IREP.  
         [0039]     Consequently, it is possible to reduce a transition time from low to high by a half approximately rather than the case of only using NMOS transistors. The transmission gates employed in the fuse boxes according to the present invention lessens a bias voltage drop by a threshold voltage of an NMOS transistor, prevents a decrease of noise margins due to the voltage drop, and improves the time delay property involved in current reduction of the NMOS transistor.  
         [0040]     In summary, the present invention can reduce a bias voltage drop by a threshold voltage of an NMOS transistor, and a back bias effect.  
         [0041]     Further, the present invention prevents a decrease of noise margins at an inverter connected to an IO bus.  
         [0042]     Moreover, the present invention also enhances a redundancy operation speed by improving the time delay property involved in current reduction of the NMOS transistor in accordance with a change of device operation mode.  
         [0043]     Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention.