Abstract:
A method for routing IP packets with IPSec AH authentication is disclosed. The method includes locating overlay edge routers between private domains and their associated NAT routers. Outbound packets from a source private domain are modified by its overlay edge router to include IPSec AH authorization data computed using IP source and destination addresses that match a packet&#39;s final source and destination IP address upon final NAT translation immediately prior to delivery to a host of a destination private domain.

Description:
FIELD 
       [0001]    Embodiments of the present invention relate to network security. 
       BACKGROUND 
       [0002]    Internet Protocol security (IPSec) is a protocol suite that provides mechanisms for authenticating and encrypting data flowing within a network such as a Virtual Private Network (VPN). 
         [0003]    Authentication Header (AH) and Encapsulating Security Payload (ESP) are wire-level protocols provided by IPSec to authenticate (AH) and encrypt (ESP) data. AH may be used in tunnel mode or transport mode. 
         [0004]    Transport mode provides a secure connection between two endpoints as it encapsulates the payload portion of Internet Protocol (IP) packets sent over the secure connection. With tunnel mode, the entire IP packet is encapsulated thereby to provide a virtual secure hop between the two endpoints. 
         [0005]      FIG. 1A  shows the contents of an IP datagram  100  that has undergone IPSec AH authentication to include an AH header.  FIG. 1B  shows the components of the AH header  102  in greater detail. It will be seen that the AH Header  102  includes authentication data  104 . The data  104  is usually a cryptographic hash-based message authentication code computed over nearly all fields of the original IP packet save for those that are modified in transit. The fields modified in transit include TTL and header checksum.  FIG. 1C  shows the IP datagram  100  with the fields that are protected by AH Authentication shaded. The data  104  carries an integrity check value (ICV) which may be a MD5 or SHA-1 hash. 
         [0006]    Network Address Translation (NAT) is a technology that is used to map a range of private addresses to and from a (usually) smaller set of public addresses. This reduces the demand for routable public IP space. NAT devices work by modifying IP headers associated with an IP datagram on the fly. In particular the source and/or destination IP addresses are changed. When a source or header IP address is changed, it forces a recalculation of the header checksum. This has to be done anyway, because the NAT device typically serves as one “hop” in the path from source to destination, and this requires the decrement of the TTL (Time To Live) field. However, as noted above since the TTL and header checksum fields are always modified in flight, AH knows to excludes them from coverage, but this does not apply to the IP addresses. These are included in the integrity check value, and any modification will cause the check to fail when verified by the recipient.  FIG. 1D  shows the IP datagram  100  with the fields that are modified by NAT shaded and  FIG. 1E  shows the IP datagram  100  with the fields that are broken by NAT shaded. 
         [0007]    Because the ICV incorporates a secret key which is unknown by intermediate parties, the NAT router is not able to recalculate the ICV, making NAT incompatible with IPSec AH authentication. 
       SUMMARY 
       [0008]    According to a first aspect of the invention, a method for routing IP packets with IPSec AH authentication is disclosed. The method includes locating overlay edge routers between private domains and their associated NAT routers. Outbound packets from a source private domain are modified by its overlay edge router to include IPSec AH authorization data computed using IP source and destination addresses that match a packet&#39;s final source and destination IP address upon final NAT translation immediately prior to delivery to a host of a destination private domain. 
         [0009]    Other aspects of the invention will be apparent from the detailed description below. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0010]      FIG. 1A  shows the contents of a IP packet. 
           [0011]      FIG. 1B  shows the IPSec AH Header in greater detail. 
           [0012]      FIG. 1C  shows the fields of the IP packet that are protected by IPSec AH authentications. 
           [0013]      FIG. 1D  shows the fields of the IP packet that are modified by a Network Address Translation (NAT) device. 
           [0014]      FIG. 1E  shoes the fields of the IP packet that are broken by NAT. 
           [0015]      FIG. 2A  shows a network setup for transmitted packets from a Host A to a Host B across NAT devices. 
           [0016]      FIG. 2B  shows the network setup of  FIG. 2A  modified by the creation of an overlay domain (OD) to facilitate packet transmission from the Host A to the Host B with IPsec AH authentication across the NAT devices, in accordance with one embodiment of the invention. 
           [0017]      FIG. 3  shows steps by an overlay router to prepare an IP packet from transmission, in accordance with one embodiment of the invention. 
           [0018]      FIG. 4  shows the fields of an IP packet as modified by the process of  FIG. 3 . 
           [0019]      FIG. 5  shows the steps in created an integrity check value (ICV) in accordance with one embodiment of the invention. 
           [0020]      FIG. 6  shows the IP datagram of  FIG. 3  as modified by a router R 2 . 
           [0021]      FIG. 7  shows a high-level block diagram for an overlay controller (OC), in accordance with one embodiment of the invention. 
           [0022]      FIG. 8  shows a high-level block diagram of hardware for a router, in accordance with one embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block or flow diagram form only in order to avoid obscuring the invention. Accommodate 
         [0024]    Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearance of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments. 
         [0025]    Moreover, although the following description contains many specifics for the purposes of illustration, anyone skilled in the art will appreciate that many variations and/or alterations to the details are within the scope of the present invention. Similarly, although many of the features of the present invention are described in terms of each other, or in conjunction with each other, one skilled in the art will appreciate that many of these features can be provided independently of other features. Accordingly, this description of the invention is set forth without any loss of generality to, and without imposing limitations upon, the invention. 
         [0026]    Broadly, embodiments of the present invention teach extending IPSec AH Authentication to NAT device so that IPSec AH authentication may be used to protect IP packets that traverse a NAT device. 
         [0027]    To understand embodiments of the invention, consider the network setup  200  shown in  FIG. 2  which will be used to illustrate how IP packets from a Host A within a private network  202  located behind a NAT router  204  can be encrypted with IPSec AH authentication and delivered to Host B within a private domain  206  located behind a NAT router  208  via an intermediate transport network  210  such as the Internet. 
         [0028]    In one embodiment, an overlay domain such as is described in is co-pending US Patent Application NO. xx/xxx,xxx, which is incorporated herein by reference, is created to facilitate routing with the network setup  200 . The overlay domain may include a plurality of overlay edge routers (OERs) each coupled to an overlay controller (OC). The overlay controller (OC) orchestrates secure overlay routing based on defined policy and control logic. Communications between the overlay controller (OC) and the overlay edge routers (OERs) are facilitated by an overlay protocol (OP) which runs over secure DTLS connections through a core transport network. Each overlay edge router (OER) is defines an edge not that is located at the boundary of the overlay domain. All overlay edge routers (OERs) connect directly with each other over the core transport network via IPSec tunnels. 
         [0029]      FIG. 2A  shows the network setup  200  with elements of the overlay domain. As will be seen said elements include overlay edge routers (OERs) R 1 , R 2 , and overlay controller (OC)  212 . The overlay edge router (OER) R 1  is positioned between the Host A and the NAT router  204 , whereas the overlay edge router (OER) is positioned between the Host B and the NAT router  208 . In use, the router R 1  learns the private IP address (IPA) of the Host A and communicates it to the overlay controller (OC)  212  via the overlay protocol (OP). In a similar manner, the router R 2  learns the private IPA of the Host B and communicates it to the overlay controller (OC)  212  via the overlay protocol (OP). 
         [0030]      FIG. 3  is a workflow drawing showing the steps involved in the transmission of IP packets from the Host A to the Host B, in accordance with one embodiment based on the overlay domain shown in  FIG. 2A .The steps is the workflow are performed by the router R 1  Referring to  FIG. 3 , the steps include the following processing blocks: 
         [0031]      300 : R 1  receives an IP packet bound for a target host device (Host B) from a source host device (Host A). 
         [0032]      302 : R 1  determines the private IPA of the last hop overlay edge router (R 1 ). This is done via the overlay protocol (OP) wherein the overlay controller (OC) communicates the same to R 1  via a DTLS control channel established through the network  210 . 
         [0033]      304 : R 1  calculates the authentication data based on the public IP address of R 1  and the private IP address R 2 . This is illustrated in  FIG. 5  which shows the steps in produced the authentication data. Referring to  FIG. 5  at block  500  the full IP packet with src IP address=public IPA of R 1  and dst IP address=private IP address of R 2  is received. At block  502  a hash function is used to transform the full IP packet in a hash digest or integrity check value (ICV) which is output at  504 . 
         [0034]      306 : R 1  adds the authentication data into the AH header portion of the IP Packet 
         [0035]      308 : R 1  inserts the original IP and UDP headers into the IP packet. This means that the private IPA of R 1  is the source IP address and the public IPA of R 2  is the destination IP address as is shown in  FIG. 4  which shows the IP packet  100  as modified by R 1   
         [0036]      310 : R 1  transmits the IP packet. 
         [0037]    When the packet arrives at R 2  it would have been modified through NAT so that its outer header will have the public IPA of R 1  as the source and the private IPA of R 2  as the destination. This can be seen from  FIG. 6 , which shows the IP packet as modified by NAT and received at the Host B. Thus, when the Host B computes the ICV based on the packet contents it would match the ICV computed at block  304 . 
         [0038]      FIG. 7  shows an example of hardware  700  that may be used to implement the overlay controller (OC), in accordance with one embodiment. The hardware  700  may includes at least one processor  702  coupled to a memory  704 . The processor  703  may represent one or more processors (e.g., microprocessors), and the memory  704  may represent random access memory (RAM) devices comprising a main storage of the hardware, as well as any supplemental levels of memory e.g., cache memories, non-volatile or back-up memories (e.g. programmable or flash memories), read-only memories, etc. In addition, the memory  704  may be considered to include memory storage physically located elsewhere in the hardware, e.g. any cache memory in the processor  702 , as well as any storage capacity used as a virtual memory, e.g., as stored on a mass storage device. 
         [0039]    The hardware also typically receives a number of inputs and outputs for communicating information externally. For interface with a user or operator, the hardware may include one or more user input output devices  706  (e.g., a keyboard, mouse, etc.) and a display  708 . For additional storage, the hardware  700  may also include one or more mass storage devices  710 , e.g., a Universal Serial Bus (USB) or other removable disk drive, a hard disk drive, a Direct Access Storage Device (DASD), an optical drive (e.g. a Compact Disk (CD) drive, a Digital Versatile Disk (DVD) drive, etc.) and/or a USB drive, among others. Furthermore, the hardware may include an interface with one or more networks  712  (e.g., a local area network (LAN), a wide area network (WAN), a wireless network, and/or the Internet among others) to permit the communication of information with other computers coupled to the networks. It should be appreciated that the hardware typically includes suitable analog and/or digital interfaces between the processor  712  and each of the components, as is well known in the art. 
         [0040]    The hardware  700  operates under the control of an operating system  714 , and executes application software  716  which includes various computer software applications, components, programs, objects, modules, etc. to perform the techniques described above. 
         [0041]    In general, the routines executed to implement the embodiments of the invention, may be implemented as part of an operating system or a specific application, component, program, object, module or sequence of instructions referred to as “computer programs.” The computer programs typically comprise one or more instructions set at various times in various memory and storage devices in a computer, and that, when read and executed by one or more processors in a computer, cause the computer to perform operations necessary to execute elements involving the various aspects of the invention. Moreover, while the invention has been described in the context of fully functioning computers and computer systems, those skilled in the art will appreciate that the various embodiments of the invention are capable of being distributed as a program product in a variety of forms, and that the invention applies equally regardless of the particular type of machine or computer-readable media used to actually effect the distribution. Examples of computer-readable media include but are not limited to recordable type media such as volatile and non-volatile memory devices, USB and other removable media, hard disk drives, optical disks (e.g., Compact Disk Read-Only Memory (CD ROMS), Digital Versatile Disks, (DVDs), etc.), flash drives among others. 
         [0042]      FIG. 8  shows a block diagram of hardware  800  for routes R 1  and R 1 , in accordance with one embodiment of the invention. Referring to  FIG. 8 , the hardware  800  includes a routing chip  804  coupled to a forwarding chip  808 . The routing chip  804  performs functions such as path computations, routing table maintenance, and reachability propagation. Components of the routing chip include a CPU or processor  804 , which is coupled to a memory  806 . The memory stores instructions to perform the methods disclosed herein. The forwarding chip is responsible for packet forwarding along a plurality of line interfaces  810   
         [0043]    Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that the various modification and changes can be made to these embodiments without departing from the broader spirit of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than in a restrictive sense.