Abstract:
The disclosure relates to a method for detecting an attack in an electronic microcircuit, comprising: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a countermeasure method for protecting sensitive data circulating in an electronic microcircuit, against attacks which aim is to discover these data. It also relates to a microcircuit portable device such as a chip card, implementing the method. 
         [0003]    2. Description of the Related Art 
         [0004]    Sensitive data may be in particular encryption or decryption keys, and more generally cryptographic data used or elaborated during cryptographic calculations, such as intermediate data of such calculations, and identifiers desired to be kept secret. 
         [0005]    Microcircuit devices using sensitive data are sometimes subjected to attacks which aim is to determine these data. Among the known attacks, the attacks of SPA (Simple Power Analysis) or DPA (Differential Power Analysis) type consist in taking numerous current and voltage measures coming in and going out of the microcircuit during a program execution or data processing by the microcircuit, with different input data. The measures obtained are used by a statistical analysis to deduce therefrom protected data, processed or used by the microcircuit. For the same aim, the attacks of EMA (Electromagnetic Analysis) and DEMA (Differential Electromagnetic Analysis) type are based on the analysis of the electromagnetic radiation emitted by the microcircuit. 
         [0006]    Attacks by fault injection are also known, which consist in introducing disturbances into the microcircuit when it executes for example sensitive algorithms such as cryptographic algorithms, or which aim is to trigger the execution of a downloading routine emitting on a port the data it memorizes. Such disturbance may be made by applying to the microcircuit one or more brief flashes for example by a laser beam, or one or more voltage peaks to one of the contacts thereof. 
         [0007]    So as to fight against these attacks, which are various by nature, numerous solutions, very different from one another, have been brought. The disclosure more particularly relates those which aim is to detect attacks by fault injection. 
         [0008]    Various detection techniques have been implemented so as to fight against these attacks. Thus, it is known to duplicate in a microcircuit the circuits to be protected, and to compare the data supplied by the duplicated circuits. If a difference appears in the data supplied, it means that the microcircuit has been subjected to an attack by fault injection. This detection technique reveals to be demanding in terms of circuit size and electrical consumption. 
         [0009]    It is also known to insert into a microcircuit several local detectors reacting to a lighting flash by supplying an active detection signal. This solution does not really allow sensitive circuits of the microcircuit to be protected from a fault injection, unless a great number of local detectors are provided, which induce a significant additional cost in terms of circuit size and electrical consumption. 
       BRIEF SUMMARY 
       [0010]    One embodiment is a countermeasure device for protecting circuits handling secret data against attacks by fault injection. One embodiment is able to detect a fault injection in particular by applying brief flashes or voltage peaks to the microcircuit. One embodiment is a countermeasure device that does not substantially increase the complexity or electrical consumption or the microcircuit. 
         [0011]    Some embodiments relates to a method for detecting an attack in an electronic microcircuit, comprising: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, and forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well. According to one embodiment, the method comprises activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage. 
         [0012]    According to one embodiment, the detection signal is activated as soon as the voltage between the ground terminal and a ground of the substrate crosses the threshold voltage. 
         [0013]    According to one embodiment, the threshold voltage is adjusted at a value higher than a variation range of the ground voltage at the ground terminal of the data processing circuit in normal operation, taking into account a ground bias voltage in relation to the ground of the substrate. 
         [0014]    According to one embodiment, the detection signal is activated as soon as the voltage between the power supply terminal and a ground of the substrate goes below the threshold voltage. 
         [0015]    According to one embodiment, the threshold voltage is adjusted at a value lower than a variation range of the power supply voltage of the data processing circuit in normal operation. 
         [0016]    According to one embodiment, the ground terminal of the data processing circuit is linked to the ground terminal of the substrate through a resistor or a bias circuit supplying a bias voltage to the ground terminal of the data processing circuit. 
         [0017]    According to one embodiment, the method comprises forming several data processing circuits in the substrate, each data processing circuit being formed in a first well, and in a second well electrically isolating from the substrate the first well with an embedded well, each data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and forming a detection circuit for each data processing circuit, each detection circuit supplying an active detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage. 
         [0018]    According to one embodiment, the method comprises forming for each data processing circuit of a bias circuit supplying a bias voltage to the ground terminal of the data processing circuit. 
         [0019]    According to one embodiment, the method comprises supplying an active consolidated detection signal if at least one of the detection signals is active. 
         [0020]    Some embodiments also relate to a microcircuit comprising a data processing circuit, comprising power supply and ground terminals, the ground terminal being formed in a first well electrically isolated from the substrate, by a second well and an embedded well According to one embodiment, the processing circuit is associated to a detection circuit to activate a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage, the microcircuit being configured to implement the method such as previously defined. 
         [0021]    According to one embodiment, the ground terminal of the data processing circuit is linked to the ground terminal of the substrate through a resistor or a bias circuit supplying a bias voltage to the ground terminal to the data processing circuit. 
         [0022]    According to one embodiment, the microcircuit comprises several data processing circuits, each comprising power supply and ground terminals, each ground terminal being formed in an isolated well, each processing circuit being associated to a detection circuit supplying an active detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage. 
         [0023]    According to one embodiment, the microcircuit comprises a logic circuit receiving all the detection signals, and supplying an active consolidated detection signal if at least one of the detection signals is active. 
         [0024]    According to one embodiment, the microcircuit comprises for each data processing circuit a bias circuit supplying a bias voltage to the ground terminal of the data processing circuit. 
         [0025]    Some embodiments also relate to a microcircuit portable device comprising a microcircuit such as previously defined. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0026]    Embodiments of the disclosure will be described hereinafter, in relation with, but not limited to the appended figures wherein: 
           [0027]      FIG. 1  schematically shows a cross-section of a substrate in which an integrated circuit is formed, 
           [0028]      FIG. 2  shows on a scale different voltage levels to be considered in an analysis of the integrated circuit operation, 
           [0029]      FIGS. 3A and 3B  are variation curves as a function of time, of voltages in the integrated circuit when it is subjected to a brief flash, 
           [0030]      FIG. 4  is a schematic top view of the integrated circuit, according to one embodiment, 
           [0031]      FIG. 5  schematically shows a power supply circuit of the integrated circuit, 
           [0032]      FIG. 6  schematically shows a bias circuit of a local ground of a circuit of the integrated circuit, 
           [0033]      FIG. 7  shows a circuit for detecting fault injection, according to one embodiment, 
           [0034]      FIG. 8  shows a circuit for detecting fault injection, according to another embodiment, 
           [0035]      FIG. 9  shows a flip-flop of the detection circuit of  FIG. 7  or  8 . 
           [0036]      FIG. 10  is a chip card according to one embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0037]      FIG. 1  shows an integrated circuit IC comprising a substrate SUB in a semiconductor material of P-type conductivity in which a circuit ISC is formed. The substrate SUB comprises a P+ doped region SBS forming a substrate connection connected to a substrate ground SGnd. The circuit ISC comprises an embedded region NISO of N-type conductivity and a well NW of N-type conductivity formed in the substrate until reaching the region NISO. The well NW is formed so as to encircle an area of the substrate thus forming a well PW of P-type conductivity. The well PW is thus isolated from a main portion of the substrate SUB by the region NISO and well NW. The region NISO forms with the well PW a capacitance CIW, and with the main portion of the substrate SUB a capacitance CIS. The presence of the capacitances CIW, CIS allows the noise on the ground SGnd of the substrate SUB and the electromagnetic radiation emitted by the circuit to be reduced, in particular in the band from 800 MHz to 1 GHz. 
         [0038]    The well NW comprises N+ doped regions NS 1 , NS 2  forming well connections intended to receive the power supply voltage Vdd of the circuit. The well NW also comprises P+ doped regions DP, SP forming the drain and the source of a P-channel CMOS transistor comprising a gate GP formed above an area forming the transistor channel, between the source SP and drain DP regions. The well PW comprises a P+ doped region PWS forming a well connection intended to be connected to the ground and two N+ doped regions SN, DN forming the source and the drain of a N-channel CMOS transistor comprising a gate GN formed above an area between the source SN and drain DN regions. Each of the gates GP, GN comprise a conductive layer overlying a thin dielectric layer on the substrate. The areas between a P+ doped region and a N+ doped region comprise a trench filled in with an isolating material (not shown), formed in the substrate to isolate the P+ doped regions from the N+ doped regions. The drain DN, DP and source SN, SP regions of the transistors, form with the wells NW and PW capacitances CPN, CNP. In the example of  FIG. 1 , the N-channel and P-channel transistors are interconnected so as to form an inverter. Thus, the source SP receives the power supply voltage Vdd, and the source SN is connected to the ground connection PWS. An input In of the inverter is connected to the gates SN and SP, and an output Out of the inverter is connected to the drains DN, DP. 
         [0039]    The ground connection PWS of the well PW forms a local ground LGnd of the circuit ISC which may be connected to the ground of the substrate SGnd, or receive a bias voltage in relation thereto. 
         [0040]      FIG. 2  shows on a scale different voltage values and ranges to be considered in the integrated circuit IC operation. The scale of  FIG. 2  comprises, from the top of the scale, voltage ranges GB, VDO, LGO, LGR then SGO at the bottom of the scale. The voltage range GB delineates the variations of the power supply voltage Vdd resulting from variations of the integrated circuit performances linked to variations of the ambient temperature and variations of the manufacturing conditions of the integrated circuit. The voltage range VDO delineates the variations of the voltage Vdd as a function of the extent of the integrated circuit activity. The range VDO corresponds to the drop of the voltage Vdd in the internal resistors of the integrated circuit. The range LGO delineates the variations of the bias voltage of the local ground of the circuit ISC as a function of the extent of the integrated circuit IC activity. The range LGR delineates the maximum adjusting extent of the voltage Vgb of the local ground of the circuit ISC. The range SGO delineates the variations of the voltage of the substrate SUB ground as a function of the extent of the integrated circuit IC activity. 
         [0041]    The extent of the range LGR may be chosen so that the voltage difference between the ranges VDO and LGO is superior or equal to the sum of the minimum voltages making it possible to guarantee the switching of the N-channel and P-channel transistors of the integrated circuit IC, i.e. the sum of the threshold voltages Vtn of a N-channel transistor and Vtp of a P-channel transistor, to which an overdrive of around 10% is added. 
         [0042]    The maximum extent of the adjusting range of the voltage Vgb of the local ground LGnd may be chosen so as to take into account different voltages relative to the integrated circuit IC operation and features. Thus, the maximum extent of the adjusting range of the bias voltage Vgb may be chosen so as to comply with the threshold voltages of a N-channel transistor and a P-channel transistor of the integrated circuit IC, with the power supply voltage Vdd and with the voltage drops which occur in the circuits of the integrated circuit when they are active. The voltages taken into account are considered with an error margin linked to performance variations of the integrated circuit resulting from ambient temperature variations or process corners of the integrated circuit. 
         [0043]    In the 90 nm integration technology, the rated power supply voltage is of around 1.3 V (with a possible difference of 10%). At the top of the scale of  FIG. 2 , the ranges GB and VDO have spreads of around 70 mV and 50 mV. The spreads of the threshold voltages Vtp and Vtn are on average of 500 mV and 475 mV. A voltage range of around 1025 mV should therefore be provided to allow the N-channel and P-channel transistors of the circuit ISC to switch. The ranges LGO and SGO have spreads of 50 mV and 25 mV. Therefore there is around 50 mV (with a possible difference of 10%) for the adjusting range LGR of the voltage Vgb. In the 0.18 μm integration technology, the adjusting range of the voltage Vgb may have an extent of 100 to 200 mV. 
         [0044]      FIGS. 3A ,  3 B show variation curves as a function of time of the power supply voltage Vdd (curves CV 1 , CV 2 ) and the voltage Vgb of the local ground LGnd (curves CV 3 , CV 4 ). In normal operation, the voltage Vdd (curve CV 1 ) varies between a maximum value when the circuit ISC is inactive and a minimum value Vdm. The voltage area between the voltages Vdm and VdM corresponds to the range VDO in  FIG. 2 . In normal operation, the voltage Vgb (curve CV 3 ) varies between a minimum value Vgm when the circuit ISC is inactive and a maximum value VgM when the circuit is active. The voltage area between the voltages Vgm and VgM corresponds to the range LGO in  FIG. 2 . 
         [0045]    In the event of overvoltage for example caused by a lighting flash such as a laser shot on the circuit ISC or by a voltage peak applied to a contact pad of the circuit, a high current appears between the power supply source Vdd and the local ground LGnd of the circuit ISC. This high current results from the fact that parasitic bipolar transistors tend to initiate a latch-up. On the other hand, the presence of the embedded region NISO minimizes the effect of other parasitic bipolar transistors, preventing a high current from establishing between the local ground LGnd of the circuit ISC and the ground of the substrate SGnd. Consequently, little current passes between the power supply source Vdd and the ground of the substrate SGnd. The curves CV 2  and CV 4  show the effect of the high current on the power supply Vdd and local ground Vgb voltages. In the curve CV 2 , the voltage Vdd drops significantly down to a voltage VdS (more than twice the width of the range VDO). In the curve CV 4 , the voltage Vgb increases rapidly until reaching a relatively high voltage peak VgS (more than twice the width of the range LGO). 
         [0046]      FIG. 4  shows the integrated circuit IC, according to one embodiment. In  FIG. 4 , the integrated circuit IC comprises several circuits formed in the substrate SUB, including several circuits ISC 1 , ISC 2 , ISC 3  to be protected by a countermeasure device. The integrated circuit IC comprises a global power supply circuit GPC supplying to the various circuits of the integrated circuit, including the circuits ISC 1 , ISC 2 , ISC 3 , the power supply voltage Vdd in relation to the ground of the substrate SGnd, from an external power supply voltage Vps. 
         [0047]    According to one embodiment, each of the circuits ISC 1 , ISC 2 , ISC 3  comprises a well of P-type conductivity PW 1 , PW 2 , PW 3  encircled by a well of N-type conductivity NW 1 , NW 2 , NW 3 , and isolated from the rest of the substrate SUB by an embedded isolating region NISO 1 , NISO 2 , NISO 3 . Each of the circuits ISC 1 , ISC 2 , ISC 3  comprises a local ground connection LG 1 , LG 2 , LG 3  and may be coupled to a bias circuit LGB 1 , LGB 2 , LGB 3  supplying a voltage Vgb 1 , Vgb 2 , Vgb 3  of the local ground LG 1 , LG 2 , LG 3  in relation to the ground of the substrate SGnd. Thus, each circuit ISC 1 , ISC 2 , ISC 3  may be powered by a power supply voltage equal to Vdd−Vgb&lt;i&gt; (where i is equal to 1, 2 or 3). As each circuit ISC 1 , ISC 2 , ISC 3  is isolated from the main portion of the substrate, the voltages Vgb 1 , Vgb 2 , Vgb 3  may be different at a given time when the circuits ISC 1 , ISC 2 , ISC 3  are all active. The circuits LGB 1 , LGB 2 , LGB 3  may consist of a simple resistor of some Ohms linking the local ground LG 1 , LG 2 , LG 3  to the ground of the substrate SGnd. 
         [0048]    According to one embodiment, each circuit ISC 1 , ISC 2 , ISC 3  is coupled to a detection circuit DET 1 , DET 2 , DET 3  to detect an attack of the circuit by a fault injection and supply an active detection signal DS 1 , DS 2 , DS 3  in the event of a detection of such an attack. To that end, the detection circuit is configured to detect a voltage peak exceeding a determined threshold TH between the voltages VgM and VgS, in the voltage Vgb of the local ground LGnd, or a drop of the power supply voltage Vdd exceeding a determined threshold TH 1  between the voltages VdS and Vdm. In the example of  FIG. 4 , each detection circuit DET 1 , DET 2 , DET 3  is connected between the output of the power supply circuit GPC and the ground of the substrate SGnd, and is connected to the local ground terminal LG 1 , LG 2 , LG 3  of one of the circuits ISC 1 , ISC 2 , ISC 3 . The integrated circuit IC may in addition comprise a logic circuit LG, for example comprising an OR logic gate, receiving all the detection signals DS 1 , DS 2 , DS 3 , and supplying an active consolidated detection signal CDS if at least one of the signals DS 1 , DS 2 , DS 3  is active, revealing the detection of an attack of the integrated circuit IC by fault injection. 
         [0049]    The circuits DET 1 , DET 2 , DET 3  thus allow a fault injection to be detected on the whole substrate surface occupied by each of the circuits ISC 1 , ISC 2 , ISC 3 , above the wells NISO 1 , NISO 2 , NISO 3 . 
         [0050]      FIG. 5  shows an example of power supply circuit GPC of the integrated circuit IC. The circuit GPC comprises two N-channel MOS transistors T 1 , T 2 , two resistors R 1 , R 2 , a comparator CP and a step-up voltage circuit BPMP. The drain of the transistors T 1 , T 2  receives the external voltage Vps. The source of the transistor T 1  is linked to the substrate ground SGnd through the resistors R 1  and R 2  connected in series. The junction node ND between the resistors R 1 , R 2  is connected to a direct input of the comparator CP. The comparator CP comprises an inverting input receiving a constant reference voltage Vref, for example fixed at 0.8 V. The output of the comparator is connected to an input of the circuit BPMP. The output of the circuit BPMP is connected to the gates of the transistors T 1 , T 2 . The source of the transistor T 2  supplies the power supply voltage Vdd. The circuit BPMP for example made by a charge pump, supplies a voltage equal to Vdd+Vtn, where Vtn is the threshold voltage of the transistors T 1 , T 2 . The comparator CP regulates the voltage Vdd by keeping the voltage at the node ND substantially equal to the voltage Vref. The value of the voltage Vdd is defined by the values of the resistors R 1 , R 2 . 
         [0051]      FIG. 6  shows an embodiment of each of the bias circuits LGB 1 , LGB 2 , LGB 3 . In  FIG. 6 , the circuit LGB comprises a resistor R 3 , a comparator CP 1  and a current source CS. The current source CS is powered by the voltage Vdd and supplies a current Iref equal to a reference voltage Vref divided by a resistor (not shown). The voltage Vref is substantially constant, i.e. in particular independent of the ambient temperature of the integrated circuit IC and the manufacturing conditions thereof. The voltage Vref may be for example supplied by a bandgap reference circuit. The comparator CP 1  is powered between the power supply voltage Vdd and the substrate ground SGnd. The resistor R 3  is connected in series between the current source CS and the ground. The junction node N 1  between the current source and the resistor R 3  is connected to a direct input of the comparator CP 1 . The output of the comparator CP 1 , which supplies the voltage Vgb to a ground terminal LG (terminal LG 1 , LG 2 , LG 3  of the circuit ISC 1 , ISC 2 , ISC 3 ), is looped to the inverting input thereof. Thus, the comparator CP 1  regulates the voltage Vgb by keeping it equal to the voltage at the node N 1 . The voltage Vgb supplied by the circuit LGB may therefore be calculated using the following equation: 
         [0000]        Vgb=R 3 I ref= V ref R 3 /R   (1)
 
         [0052]    where R is a resistor such that Vref=Iref R. The circuit LGB has the advantage of not being sensitive to variations of the power supply voltage Vdd which may occur in particular when the integrated circuit IC is active due to voltage drops in the internal resistors of the circuit IC and in the event of attack by fault injection. 
         [0053]    The resistor R 3  may be adjustable to adjust the local ground voltage Vgb. In the 90 nm technology with the power supply voltage Vdd fixed at 1.3 V, and if Vref is fixed at 0.1 V and if Vgb is adjustable between 1 and 50 mV, then the ratio R 3 /R of the values of the resistors R 3  and R is adjustable between 1/100 and ½. Conventionally, the adjustable resistor R 3  may be made using several resistors connected in series, a switch being mounted in parallel of each resistor mounted in series, each switch being controlled by a bit of a control word. 
         [0054]    One embodiment of a detection circuit is shown in  FIG. 7 . In  FIG. 7 , the detection circuit DETC comprises two resistors R 4 , R 5  a capacitor C 1 , a comparator CP 2  and a flip-flop FF. The comparator CP 2  is powered between the power supply voltage Vdd and the substrate ground SGnd. The capacitor C 1  is connected between the source of the voltage Vdd and the ground SGnd to filter or decrease the possible variations of the voltage Vdd. A direct input of the comparator CP 2  is connected to the ground terminal LG (terminal LG 1 , LG 2 , LG 3  of the circuit ISC 1 , ISC 2 , ISC 3 ). The resistors R 4 , R 5  are connected in series between a reference voltage source Vref and the ground of the substrate SGnd. The junction node N 2  between the two resistors R 4 , R 5  is connected to an inverting input of the comparator CP 2 . The output of the comparator CP 2  is connected to an input of the flip-flop FF which outputs a detection signal DS. The flip-flop FF is for example of RS type to supply a logic signal at 0 as long as the output signal of the comparator is at 0 and a logic signal at 1 as soon as a signal different from zero appears in output of the comparator CP 2 . The state of the flip-flop FF may be reset at 0 using a reset signal RST supplied to a reset input of the flip-flop. The capacitor C 1  has a capacitance sufficient to maintain the voltage Vdd in the event of a voltage drop the sufficient time for the detection. 
         [0055]    The circuit DETC supplies a logic signal DS indicating an attack (for example at 1) as soon as a voltage difference appears between the local ground voltage Vgb and the ground of the substrate SGnd, higher than a threshold voltage TH. The threshold voltage TH is defined by the resistors R 4 , R 5  and the reference voltage Vref. Thus, the threshold voltage TH may be determined using the following formula: 
         [0000]        TH=V ref/(1 +R 4 /R 5)  (2)
 
         [0056]    The resistors R 4  and R 5  may be chosen so that the threshold voltage TH is as low as possible above the voltage VgM or the range LGO ( FIGS. 3B and 2 ) to obtain a high detection sensitivity while avoiding the risk of false detection. One of the two resistors R 4 , R 5 , for example the resistor R 5  may be adjustable to adjust the threshold voltage TH as a function of the local ground voltage Vgb supplied by the bias circuit LGB to obtain a determined detection sensitivity.  FIGS. 2 and 3B  indicate an adjusting range of the threshold voltage TH located above the adjusting range LGO of the voltage Vgb and between the voltages VgM and VgS.  FIG. 3B  shows that a compromise is to be found for the threshold TH 1 , knowing that by increasing the detection sensitivity, the risk of false detection is increased. 
         [0057]    When the signal DS indicates an attack, any adapted measure may be taken, given that indicating an error may reveal an attack of the integrated circuit IC. Thus, the integrated circuit may, in the event of error detection, for example reset, definitely block, erase the memory thereof or only the sensitive data it memorizes, etc. 
         [0058]      FIG. 8  shows a detection circuit DETC′, according to another embodiment. In  FIG. 8 , the circuit DETC′ differs from the circuit DETC in that it is configured to connect, not to the local ground terminal of the circuit ISC 1 , ISC 2 , ISC 3 , but to the power supply terminal VS (corresponding to VS 1 , VS 2  or VS 3  in  FIG. 4 ) thereof. The circuit DETC′ differs from the circuit DETC in that the inverting input of the comparator CP 2  is connected to the terminal VS and the power supply voltage source Vdd is linked to the voltage source Vref through resistors R 6  and R 7  connected in series. The junction node N 3  between the resistors R 6 , R 7  is connected to the direct input of the comparator CP 2 . 
         [0059]    The circuit DETC′ supplies a logic signal DS indicating an attack (for example at 1) as soon as a voltage difference appears between the power supply voltage at the terminal VS and the power supply voltage Vdd at the output of the circuit GPC, lower than a threshold voltage TH 1 . The threshold voltage TH 1  is defined by the resistors R 6 , R 7  and the voltages Vdd and Vref. Thus, the threshold voltage TH 1  may be calculated using the following formula: 
         [0000]        TH 1 =V ref+( Vdd−V ref)/(1 +R 6 /R 7)  (3)
 
         [0060]    The resistors R 6  and R 7  may be chosen so that the threshold voltage TH 1  is as high as possible below the voltage Vdm or the range VDO ( FIGS. 3A and 2 ) to obtain a high detection sensitivity while avoiding the risk of false detection. One of the two resistors R 6 , R 7 , for example the resistor R 7  may be adjustable to adjust the threshold voltage TH 1  as a function of the power supply voltage Vdd supplied by the power supply circuit GPC to obtain a determined detection sensitivity.  FIG. 3B  indicates an adjusting range of the threshold voltage TH 1  located between the voltages VdS and Vdm.  FIG. 3B  shows that a compromise is to be found for the threshold TH 1 , knowing that by increasing the detection sensitivity, the risk of false detection is increased. 
         [0061]      FIG. 9  shows a conventional example embodiment of the flip-flop FF. The flip-flop FF comprises two logic gates NOR 1 , NOR 2  of NOR type. The output of each gate NOR 1 , NOR 2  is connected to an input of the other gate. The gate NOR 1  comprises an input connected to an input of the flip-flop FF (connected to the output of the comparator CP 2 ) and the gate NOR 2  comprises an input receiving a reset signal RST from the flip-flop. The output of the gate NOR 2  is linked to the output of the flip-flop. 
         [0062]    It will be clear to those skilled in the art that the present disclosure is susceptible of various embodiments and applications. In particular, the disclosure is not limited to an integrated circuit comprising several wells isolated from the main portion of substrate. All the process circuits of the integrated circuit may be formed in one isolated well and one well encircling the isolated well. 
         [0063]    The disclosure is not limited either to the circuits described for detecting an attack by lighting flash or voltage peaks applied to contact pads of the integrated circuit. Any other circuit making it possible to detect a voltage peak crossing a threshold voltage in the power supply voltage or the ground voltage (isolated from the substrate) of a processing circuit of the integrated circuit may be adapted. 
         [0064]    A microcircuit portable device according to one embodiment is shown in  FIG. 10 . In particular, the microcircuit portable device is a chip card CC that includes a support S that typically would be made of plastic, as is typical for chip cards. The chip card CC also includes an integrated circuit such as the integrated circuit IC described above. Those skilled in the art will understand that a microcircuit portable device according to the present disclosure can be implemented using any portable device with a processor that is desired to be protected from hacking attempts. 
         [0065]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.