Abstract:
A semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the second metal layer having a separation allowing for the second metal layer to be positioned above distal ends of the first metal layer. The semiconductor package also including a third metal layer formed over the second metal layer, and the third metal layer having a separation allowing for the third metal layer to be positioned above distal ends of the first metal layer, a trench defined by the separation of the third metal layer and second metal layer, and extending through the third metal layer and the second metal layer to expose the first metal layer, and a bonding ball located within the trench.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2014-0078681, filed on Jun. 26, 2014, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Various embodiments generally relate to a semiconductor package, and more particularly, to the structure of a pad which connects a semiconductor device and an external pin. 
         [0004]    2. Related Art 
         [0005]    These days, the electronic industry trends to manufacture products with high reliability at reduced costs in such a way as to accomplish light weight, miniaturization, high speed operation, multi-functionality and high performance. A package assembly technology is considered to be one of the most important technologies for achieving the purposes involved in designing such products. 
         [0006]    The package assembly technology is a technology that focuses on protecting a semiconductor chip, formed with integrated circuits, from external circumstances. The package assembly technology is also a technology that focuses on easily mounting the semiconductor chip to a substrate, through a wafer assembly process, so as to secure the operational reliability of the semiconductor chip. 
         [0007]    In the conventional art, packages are manufactured by cutting a wafer to separate individual semiconductor chips from one another and then performing a packaging process for the individual semiconductor chips. However, the packaging process includes in itself a number of unit processes. These unit processes may include processes for chip attachment, wire bonding, molding, trimming and forming. In the conventional package manufacturing method in which the packaging process should be performed for the respective semiconductor chips, a problem may be encountered. The problem encountered often deals with the substantially long times required for packaging all of the semiconductor chips when considering the number of semiconductor chips which are obtained from one wafer. 
         [0008]    In this situation, recently, the technology of wafer level chip scale packages has been suggested. In wafer level chip scale packages assembly is not performed with individual semiconductor chips separated from one another, rather a redistribution work and formation of ball-shaped external connection terminals are performed at a wafer level. Then the individual semiconductor chips are separated. 
         [0009]    What follows is a brief description concerning a method for manufacturing the wafer level chip scale packages. First, a wafer is first formed, then a first insulation layer is formed to expose bonding pads disposed on the top surfaces of semiconductor chips, and finally redistribution lines are formed on the first insulation layer to be individually connected with the bonding pads. 
         [0010]    Then, a second insulation layer is formed on the first insulation layer and the redistribution lines in such a way as to partially expose the redistribution lines, and external connection terminals such as solder balls are attached to the redistribution lines which are exposed. Thereafter, the wafer formed with the external connection terminals is cut to a chip level completing the manufacture of the wafer level chip scale packages. 
         [0011]    In a semiconductor device, pads serve as parts which are connected with external wires. In this regard, in the case of performing wire bonding for the semiconductor device, a fail may occur in that the junction surface of a pad may be disconnected during the process of working on the semiconductor device. 
         [0012]    For example, in the case of applying a flip chip, the bonding portion of a ball structure is connected with a pad. However, when filling a mold during a packaging process, the ball is likely to be disconnected from the pad. Also, even in the case of connecting a pad through the use of wire bonding, the pad and a wire are likely to be disconnected from each other. 
         [0013]    A wire bonding process is a process that involves connecting bonding pads of a semiconductor chip and leads of a lead frame by using wires. This wire bonding process allows the electrical characteristics of the semiconductor chip to be transferred to a circuit board. 
         [0014]    In the bonding process, a fail may generally occur due to poor adhesion between a wire and a bonding pad or a lead, a crack by an interlayer stress, absorption of moisture, or a peel-off. That is to say, in the case of electrically connecting elements in a semiconductor package through wire bonding, electrical connections may become unstable due to bending, protrusion and snapping of bonding wires. 
       SUMMARY 
       [0015]    In an embodiment, a semiconductor package may include: a first metal layer configured for use as a bonding pad; a second metal layer formed over the first metal layer, and separated to be positioned on both sides in view of the first metal layer; a third metal layer formed over the second metal layer, and separated to be positioned on both sides in view of the first metal layer; and a trench defined through the third metal layer and the second metal layer to expose the first metal layer, and having buried therein a bonding ball. 
         [0016]    In an embodiment, a semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the second metal layer having a separation allowing for the second metal layer to be positioned above distal ends of the first metal layer. The semiconductor package also including a third metal layer formed over the second metal layer, and the third metal layer having a separation allowing for the third metal layer to be positioned above distal ends of the first metal layer, a trench defined by the separation of the third metal layer and second metal layer, and extending through the third metal layer and the second metal layer to expose the first metal layer, and a bonding ball located within the trench. 
         [0017]    In an embodiment, a semiconductor package may include a first metal layer, and a second metal layer configured for use as a bonding pad and formed over the first metal layer. The semiconductor package may also include a plurality of third metal layer parts formed over the second metal layer, and separated from one another by gaps. The semiconductor package may include a pad open region exposing the second metal layer through spaces defined between the plurality of third metal layer parts, and a bonding ball configured to bury the pad open region. 
         [0018]    In an embodiment, a semiconductor package may include a first metal layer used as a bonding pad, a plurality of second metal layer parts formed over the first metal layer, and separated from one another by a predetermined gap. The semiconductor package may also include a plurality of third metal layer parts formed over the second metal layer parts, and separated from one another by a preselected gap. The semiconductor package may include a pad open region exposing the first metal layer through spaces defined between the plurality of third metal layer parts and between the plurality of second metal layer parts, and a bonding ball positioned to bury the pad open region. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  is a view illustrating a representation of a semiconductor package. 
           [0020]      FIG. 2  is a view illustrating an example of a representation of a semiconductor package in accordance with an embodiment. 
           [0021]      FIGS. 3   a  to  3   d  are views illustrating an example of a representation of a semiconductor package in accordance with an embodiment. 
           [0022]      FIGS. 4   a  and  4   b  are views illustrating an example of a representation of a semiconductor package in accordance with an embodiment. 
           [0023]      FIG. 5  illustrates a block diagram of an example of a representation of a system employing the semiconductor package in accordance with the embodiments discussed above with relation to  FIGS. 1-4 . 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    Hereinafter, a semiconductor package will be described below with reference to the accompanying drawings through various examples of embodiments. 
         [0025]    Various embodiments may generally relate to a semiconductor package, and more particularly, to a technology for possibly improving the structure of a pad which connects a semiconductor device and an external pin. 
         [0026]    Various embodiments may be directed to the technology of changing the structure of a pad junction surface. For example, the pad junction surface may be widened, thereby reducing electrical resistance and perhaps strengthening the physical junction between a pad and a bonding ball. 
         [0027]      FIG. 1  is a view illustrating a representation of a semiconductor package. 
         [0028]    A semiconductor package may include a first metal layer M 1 , contact lines M 2 C, a second metal layer M 2 , contact lines M 3 C, a third metal layer M 3 , an insulation layer  100 , and a bonding ball  110 . 
         [0029]    The second metal layer M 2  connected with the contact lines M 2 C may be formed over the first metal layer M 1 . The first metal layer M 1  may be separated or divided in such a way as to be positioned on both sides of the third metal layer M 3 . The first metal layer M 1  may be separated into two distinct parts or more. The first metal layer M 1  may be formed over either the distal ends or both ends of the third metal layer M 3 . Each separated section of the first metal layer M 1  may be connected with the respective contact lines M 2 C. The contact lines M 2 C may connect the first metal layer M 1  to the second metal layer M 2 . The contact lines M 2 C may connect the first metal layer M 1  to the second metal layer M 2  forming contact nodes. 
         [0030]    The third metal layer M 3  connected with the contact lines M 3 C may be formed over the second metal M 2 . The second metal layer M 2  may be separated or divided in such a way as to be positioned on both sides of the third metal layer M 3 . The second metal layer M 2  may be divided into two distinct parts or more. The second metal layer M 2  may be formed over either the distal ends or both ends of the third metal layer M 3 . Each separated section of the second metal layer M 2  may be connected with the respective contact lines M 3 C. The contact lines M 3 C may connect the third metal layer M 3  to the second metal layer M 2 . The contact lines M 3 C may connect the third metal layer M 3  to the second metal layer M 2  forming contact nodes. The insulation layer  100  and the bonding ball  110  are formed on or above the third metal layer M 3 . 
         [0031]    The third metal layer M 3  may be exposed through the insulation layer  100 . The third metal layer M 3  may include a bonding pad. An external connection terminal such as the bonding ball  110  may be attached to the exposed portion of the third metal layer M 3  while being formed on portions of the insulation layer  100  which adjoins the exposed portion of the third metal layer M 3 . The depth of a trench in which the bonding ball  110  is buried between the opposite portions of the insulation layer  100  to be connected with the third metal layer M 3  is designated by the reference symbol A as illustrated in  FIG. 1 . 
         [0032]      FIG. 2  is a view illustrating an example of a representation of a semiconductor package in accordance with an embodiment. 
         [0033]    A semiconductor package in accordance with an embodiment may include a first metal layer M 1 , contact lines M 2 C, a second metal layer M 2 , contact lines M 3 C, a third metal layer M 3 , an insulation layer  200 , and a bonding ball  210 . 
         [0034]    The second metal layer M 2  may be connected with the contact lines M 2 C and may be formed over the first metal layer M 1 . The contact lines M 2 C may be formed on both sides of the first metal layer M 1 , and are connected with portions of the second metal layer M 2 , respectively. The contact lines M 2 C may be formed on distal ends of the first metal layer M 1 , and may be connected with portions of the second metal layer M 2 , respectively. Portions of the second metal layer M 2  may be spaced apart from other portions of the second metal layer M 2 . The second metal layer M 2  may be divided into two distinct portions or more. 
         [0035]    The third metal layer M 3  may be connected with the contact lines M 3 C and may be formed over the second metal layer M 2 . The second metal layer M 2  may be separated or divided in such a way as to be positioned on both sides of the first metal layer M 1 . The second metal layer M 2  may be formed over either the distal ends or both ends of the first metal layer M 1 . Each separated section of the second metal layer M 2  may be connected with the respective contact lines M 2 C. The contact lines M 2 C may connect the first metal layer M 1  to the second metal layer M 2 . The contact lines M 2 C may connect the first metal layer M 1  to the second metal layer M 2  forming contact nodes. 
         [0036]    The third metal layer M 3  may be separated or divided in such a way as to be positioned on both sides of the first metal layer M 1 . The third metal layer M 3  may be divided into two distinct portions or more. The third metal layer M 3  may be formed over either the distal ends or both ends of the first metal layer M 1 . Each separated section of the third metal layer M 3  may be connected with the respective contact lines M 3 C. The contact lines M 3 C may connect the third metal layer M 3  to the second metal layer M 2 . The contact lines M 3 C may connect the third metal layer M 3  to the second metal layer M 2  forming contact nodes. The insulation layer  200  may be formed on or above the third metal layer M 3 . 
         [0037]    The first metal layer M 1  may be underlying beneath the insulation layer  200 , the third metal layer M 3  and the second metal layer M 2 . The first metal layer M 1  which is underlying may be exposed through the insulation layer  200 , the third metal layer M 3  and the second metal layer M 2 . The insulation layer  200 , the third metal layer M 3  and the second metal layer M 2  may be overlying above the first metal layer M 1 . The first metal layer M 1  may include or comprise a bonding pad. 
         [0038]    A trench  220  may be defined by the insulation layer  200 , the third metal layer M 3  and the second metal layer M 2 , and may be formed in such a way as to expose the first metal layer M 1 . An external connection terminal such as for example a bonding ball  210  may be inserted into the trench  220 . The bottom surface of the bonding ball  210  may be attached to the first metal layer M 1 . The side surfaces of the bonding ball  210  may be connected with the surfaces of the second metal layer M 2  and the third metal layer M 3 . The side surfaces of the bonding ball  210  may also be connected with the side surfaces of the second metal layer M 2  and the side surfaces of the third metal layer M 3  created by the separations in the respective layers. 
         [0039]    The depth of the trench  220  which is defined through the insulation layer  200 , the third metal layer M 3  and the second metal layer M 2  and in which the bonding ball  210  is buried to be connected with the first metal layer M 1  is designated by the reference symbol B. In an embodiment illustrated in  FIG. 2 , the depth B of the trench  220 , in which the bonding ball  210  is buried, may be deeper than the depth A discussed above and illustrated in  FIG. 1 . 
         [0040]    In an embodiment, the trench  220  may be defined by the separation between both the second metal layer M 2  and the third metal layer M 3 , each layer divided and positioned on both sides of the first metal layer M 1 , in such a way as to expose the first metal layer M 1  lying lowermost. The bonding ball  210  may be buried in the trench  220 , and may be in contact with the first metal layer M 1 . 
         [0041]    The bonding ball  210  may be buried relatively deep in the trench  220 . Thus, the probability of the bonding ball  210  being disconnected, when for example introducing a material for molding a package, may be decreased. Further, in the cases where the bonding ball  210  is buried relatively deep in the trench  220  an additional advantage may be provided in that resistance may be reduced. This may be because the contact area between the bonding ball  210  and the metal layers M 1 , M 2  and M 3  is increased when compared to the cases where junction is made two-dimensionally. 
         [0042]    Moreover, in the cases of wire bonding, in the conventional art, the first metal layer M 1  is likely to be pushed and lifted by a bonding pressure. However, in an embodiment, since the first metal line M 1  is secured not to be pushed leftward or rightward because of the defined area of the trench  220  between the second metal layer M 2  and the third metal layer M 3 , a more stable junction between a wire and the first metal layer M 1  may be possible. 
         [0043]      FIGS. 3   a  to  3   d  are views illustrating an example of a representation of a semiconductor package in accordance with an embodiment.  FIG. 3   a  is a cross-sectional view taken along the line A-A′ of  FIG. 3   b . Also,  FIG. 3   a  may be a cross-sectional view taken along the line B-B′ of  FIG. 3   c . Further,  FIG. 3   a  may be a cross-sectional view taken along the line C-C′ of  FIG. 3   d.    
         [0044]    A semiconductor package in accordance with an embodiment may include a first metal layer M 1 , contact lines M 2 C, and a second metal layer M 2 . The semiconductor package may also include a plurality of contact lines M 3 C_ 1  to M 3 C_ 4 , a plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E, a pad open region  300 , and an insulation layer  310 . 
         [0045]    The second metal layer M 2  may be connected with the contact lines M 2 C and may be formed over the first metal layer M 1 . The second metal layer M 2  may include a bonding pad. The first metal layer M 1  may be separated or divided in such a way as to be positioned on both sides of the second metal layer M 2 . Each separated section of the first metal layer M 1  may be connected with the respective contact lines M 2 C. The contact lines M 2 C may connect the first metal layer M 1  to the second metal layer M 2 . The contact lines M 2 C may connect the first metal layer M 1  to the second metal layer M 2  forming contact nodes. 
         [0046]    The plurality of contact lines M 3 C_ 1  to M 3 C_ 4  are formed on the second metal layer M 2 . The plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E, the number of which corresponds to the number of the plurality of contact lines M 3 C_ 1  to M 3 C_ 4 , may be formed on the plurality of contact lines M 3 C_ 1  to M 3 C_ 4 . The second metal layer M 2  may be formed in a type of a single line such that the plurality of contact lines M 3 C_ 1  to M 3 C_ 4  may be arranged on the second metal layer M 2 . 
         [0047]    The plurality of contact lines M 3 C_ 1  to M 3 C_ 4  may be formed on the second metal layer M 2  in such a way as to be separated from one another by a predetermined gap. The plurality of contact lines M 3 C_ 1  to M 3 C_ 4 , which are formed to be separated from one another by the predetermined gap, define a plurality of slits in the cross-sectional view. The plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E may be formed on the plurality of contact lines M 3 C_ 1  to M 3 C_ 4  to be correspondingly connected with the plurality of contact lines M 3 C_ 1  to M 3 C_ 4 . The insulation layer  310  may be formed on the third metal layer parts M 3 A and M 3 B which are disposed at outermost sides among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E. 
         [0048]    The pad open region  300  may be defined between the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E and between the plurality of contact lines M 3 C_ 1  to M 3 C_ 4  in such a way as to expose the second metal layer M 2 . The pad open region  300  may be defined by the spaces between the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E and between the plurality of contact lines M 3 C_ 1  to M 3 C_ 4 . An external connection terminal such as a bonding ball may be buried in the pad open region  300 . 
         [0049]    In the pad open region  300 , the bottom surface of the bonding ball may be connected to the exposed portions of the second metal layer M 2 . Further, the bonding ball may be connected with the side surfaces of the third metal layer parts M 3 A and M 3 B which are disposed at the outermost sides among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E and with both side surfaces and the top surfaces of the third metal layer parts M 3 D and M 3 E which are disposed centrally among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E. 
         [0050]    In the cases where the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E and the plurality of contact lines M 3 C_ 1  to M 3 C_ 4  are formed in the shape of prominences and depressions as illustrated in  FIG. 3   a , the stable junction of the bonding ball may be possible since a contact area over which the bonding ball is connected is increased. 
         [0051]      FIG. 3   b  is the plan view of  FIG. 3   a . In an embodiment, as illustrated in  FIG. 3   b , the two third metal layer parts M 3 A and M 3 B, which are disposed at the outermost sides among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E, may be disposed as a type of line configuration. Moreover, the two third metal layer parts M 3 D and M 3 E, which are disposed centrally among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E, may be disposed as a type of lines parallel or substantially parallel to the third metal layer parts M 3 A and M 3 B. The third metal layer parts disposed centrally M 3 D and M 3 E among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E may be disposed on the corresponding first contact nodes M 3 C_ 3  and M 3 C_ 4 , and may be arranged in lines. 
         [0052]    The thicknesses of the third metal layer parts M 3 A and M 3 B may be the same with each other. The thicknesses of the third metal layer parts M 3 D and M 3 E may be the same with each other. The third metal layer parts M 3 A and M 3 B may be thicker than the third metal layer parts M 3 D and M 3 E. 
         [0053]      FIG. 3   c  is the plan view of  FIG. 3   a  and illustrates an embodiment. In an embodiment, referring to  FIG. 3   c , the two third metal layer parts M 3 A and M 3 B, which are disposed at the outermost sides among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E, may be disposed as a type of lines. Moreover, the two third metal layer parts M 3 D and M 3 E, which are disposed centrally among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E, may be disposed as a type of square, rectangle or quadrangle. The square, rectangle, or quadrangle may have openings therein as illustrated in for example  FIG. 3C . It may be that the two third metal layer parts M 3 D and M 3 E, which are separately illustrated on the cross-sectional view, are connected with each other on the plan view. The third metal layer parts disposed centrally M 3 D and M 3 E among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E may be disposed on the corresponding first contact nodes M 3 C_ 3  and M 3 C_ 4 , and may be arranged to form substantially the shape of a quadrangle as illustrated, for example, in  FIG. 3   c.    
         [0054]      FIG. 3   d  is the plan view of  FIG. 3   a  and illustrates an embodiment. In an embodiment, referring to  FIG. 3   d , the two third metal layer parts M 3 A and M 3 B, which are disposed at the outermost sides among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E, may be disposed as a type of lines. Moreover, the third metal layer parts M 3 D and M 3 E, which are disposed centrally among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E, may be disposed as a type of mesh-shaped lattice. The third metal layer parts disposed centrally M 3 D and M 3 E among the plurality of third metal layer parts M 3 A, M 3 B, M 3 D and M 3 E may be disposed on the corresponding first contact nodes M 3 C_ 3  and M 3 C_ 4 , and may be arranged to form substantially the shape of a mesh-shaped lattice as illustrated, for example, in  FIG. 3   d.    
         [0055]      FIGS. 4   a  and  4   b  are views illustrating an example of a representation of a semiconductor package in accordance with an embodiment.  FIG. 4   a  is a cross-sectional view taken along the line D-D′ of  FIG. 4   b.    
         [0056]    The semiconductor package according to an embodiment of  FIG. 4   a  may include a first metal layer M 1 , a plurality of contact lines M 2 C_ 1  to M 2 C_ 3 , a plurality of second metal layer parts M 2 _ 1  to M 2 _ 3 , a plurality of contact lines M 3 C_ 5  to M 3 C_ 7 , and a plurality of third metal layer parts M 3 _ 1  to M 3 _ 3 . The semiconductor package may also include a pad open region  400 , an insulation layer  410 , and a bonding ball  420 . 
         [0057]    The plurality of contact lines M 2 C_ 1  to M 2 C_ 3  may be formed on the first metal layer M 1 . The plurality of contact lines M 2 C_ 1  to M 2 C_ 3  may be formed on the first metal layer M 1  in such a way as to be separated from one another by a predetermined gap. The plurality of contact lines M 2 C_ 1  to M 2 C_ 3 , which are formed to be separated from one another by the predetermined gap, define a plurality of slits in the cross-sectional view. 
         [0058]    The plurality of second metal layer parts M 2 _ 1  to M 2 _ 3 , the number of which corresponds to the number of the plurality of contact lines M 2 C_ 1  to M 2 C_ 3 , are formed on the plurality of contact lines M 2 C_ 1  to M 2 C_ 3 . The first metal layer M 1  may comprise a bonding pad. The first metal layer M 1  may be formed as a type of a single line such that the plurality of contact lines M 2 C_ 1  to M 2 C_ 3  may be arranged on the first metal layer M 1 . 
         [0059]    The plurality of contact lines M 3 C_ 5  to M 3 C_ 7  may be formed on the plurality of second metal layer parts M 2 _ 1  to M 2 _ 3 . The plurality of third metal layer parts M 3 _ 1  to M 3 _ 3 , the number of which corresponds to the number of the plurality of contact lines M 3 C_ 5  to M 3 C_ 7 , may be formed on the plurality of contact lines M 3 C_ 5  to M 3 C_ 7 . 
         [0060]    The plurality of contact lines M 3 C_ 5  to M 3 C_ 7  may be formed on the plurality of second metal layer parts M 2 _ 1  to M 2 _ 3  in such a way as to be separated from one another by a preselected gap. The plurality of contact lines M 3 C_ 5  to M 3 C_ 7 , which are formed to be separated from one another by the preselected gap, define a plurality of slits in the cross-sectional view. The plurality of third metal layer parts M 3 _ 1  to M 3 _ 3  are formed on the plurality of contact lines M 3 C_ 5  to M 3 C_ 7  to be correspondingly connected with the plurality of contact lines M 3 C_ 5  to M 3 C_ 7 . The insulation layer  410  may be formed on the third metal layer parts M 3 _ 1  and M 3 _ 2  which are disposed at outermost sides among the plurality of third metal layer parts M 3 _ 1  to M 3 _ 3 . 
         [0061]    The contact lines M 2 C_ 1  to M 2 C_ 3  may connect the first metal layer M 1  to the second metal layers M 2 _ 1  to M 2 _ 3 , respectively. The contact lines M 2 C_ 1  to M 2 C_ 3  may connect the first metal layer M 1  to the second metal layers M 2 _ 1  to M 2 _ 3  forming contact nodes. The contact lines M 3 C_ 5  to M 3 C_ 7  may connect the second metal layer parts M 2 C_ 1  to M 2 C_ 3  to the third metal layer parts M 3 _ 1  to M 3 _ 3 , respectively. The contact lines M 3 C_ 5  to M 3 C_ 7  may connect the second metal layer parts M 2 C_ 1  to M 2 C_ 3  to the third metal layer parts M 3 _ 1  to M 3 _ 3  forming contact nodes. 
         [0062]    The pad open region  400  may be defined between the plurality of third metal layer parts M 3 _ 1  to M 3 _ 3 , between the plurality of contact lines M 3 C_ 5  to M 3 C_ 7 , between the plurality of second metal layer parts M 2 _ 1  to M 2 _ 3 , and between the plurality of contact lines M 2 C_ 1  to M 2 C_ 3  in such a way as to expose the first metal layer M 1 . An external connection terminal such as the bonding ball  420  may be buried in the pad open region  400 . 
         [0063]    In the pad open region  400 , the bottom surface of the bonding ball  420  may be connected to the exposed portions of the first metal layer M 1 . The side surfaces of the plurality of third metal layer parts M 3 _ 1  to M 3 _ 3 , the plurality of contact lines M 3 C_ 5  to M 3 C_ 7 , the plurality of second metal layer parts M 2 _ 1  to M 2 _ 3  and the plurality of contact lines M 2 C_ 1  to M 2 C_ 3  may be connected with the bonding ball  420 . The bonding ball  420  may be formed to cover the top surface of the third metal layer part M 3 _ 3  which is disposed centrally. 
         [0064]    In the cases where the plurality of third metal layer parts M 3 _ 1  to M 3 _ 3 , the plurality of contact lines M 3 C_ 5  to M 3 C_ 7 , the plurality of second metal layer parts M 2 _ 1  to M 2 _ 3  and the plurality of contact lines M 2 C_ 1  to M 2 C_ 3  are formed in the shape of prominences and depressions as illustrated in  FIG. 4   a , the stable junction of the bonding ball  420  may be possible since a contact area over which the bonding ball  420  is connected is increased. 
         [0065]      FIG. 4   b  is the plan view of  FIG. 4   a . In an embodiment, referring to  FIG. 4   b , the two third metal layer parts M 3 _ 1  and M 3 _ 2 , which are disposed at the outermost sides among the plurality of third metal layer parts M 3 _ 1  to M 3 _ 3 , may be disposed on the contact lines M 3 C_ 5  and M 3 C_ 6  and may be arranged to form lines as, for example, illustrated in  FIG. 4   b.    
         [0066]    Moreover, the one third metal layer part M 3 _ 3 , which is disposed centrally among the plurality of third metal layer parts M 3 _ 1  to M 3 _ 3 , may be disposed in the type of a line parallel to or substantially parallel to the third metal layer parts M 3 _ 1  and M 3 _ 2 . The thicknesses of the third metal layer parts M 3 _ 1  and M 3 _ 2  may be the same with each other, and the third metal layer part M 3 _ 3  may be formed thinner than the third metal layer parts M 3 _ 1  and M 3 _ 2 . 
         [0067]    As is apparent from the above descriptions, according to the embodiments, the structure of a pad junction surface may be changed to be wide, whereby electrical resistance may be reduced and the physical junction between a pad and a bonding ball may be strengthened. 
         [0068]    The semiconductor package discussed above (see  FIGS. 1-4 ) are particular useful in the design of memory devices, processors, and computer systems. For example, referring to  FIG. 5 , a block diagram of a system employing the semiconductor packages in accordance with the embodiments are illustrated and generally designated by a reference numeral  1000 . The system  1000  may include one or more processors or central processing units (“CPUs”)  1100 . The CPU  1100  may be used individually or in combination with other CPUs. While the CPU  1100  will be referred to primarily in the singular, it will be understood by those skilled in the art that a system with any number of physical or logical CPUs may be implemented. 
         [0069]    A chipset  1150  may be operably coupled to the CPU  1100 . The chipset  1150  is a communication pathway for signals between the CPU  1100  and other components of the system  1000 , which may include a memory controller  1200 , an input/output (“I/O”) bus  1250 , and a disk drive controller  1300 . Depending on the configuration of the system, any one of a number of different signals may be transmitted through the chipset  1150 , and those skilled in the art will appreciate that the routing of the signals throughout the system  1000  can be readily adjusted without changing the underlying nature of the system. 
         [0070]    As stated above, the memory controller  1200  may be operably coupled to the chipset  1150 . The memory controller  1200  may include at least one semiconductor package as discussed above with reference to  FIGS. 1-4 . Thus, the memory controller  1200  can receive a request provided from the CPU  1100 , through the chipset  1150 . In alternate embodiments, the memory controller  1200  may be integrated into the chipset  1150 . The memory controller  1200  may be operably coupled to one or more memory devices  1350 . In an embodiment, the memory devices  1350  may include the at least one semiconductor package as discussed above with relation to  FIGS. 1-4 , the memory devices  1350  may include a plurality of word lines and a plurality of bit lines for defining a plurality of memory cell. The memory devices  1350  may be any one of a number of industry standard memory types, including but not limited to, single inline memory modules (“SIMMs”) and dual inline memory modules (“DIMMs”). Further, the memory devices  1350  may facilitate the safe removal of the external data storage devices by storing both instructions and data. 
         [0071]    The chipset  1150  may also be coupled to the I/O bus  1250 . The I/O bus  1250  may serve as a communication pathway for signals from the chipset  1150  to I/O devices  1410 ,  1420  and  1430 . The I/O devices  1410 ,  1420  and  1430  may include a mouse  1410 , a video display  1420 , or a keyboard  1430 . The I/O bus  1250  may employ any one of a number of communications protocols to communicate with the I/O devices  1410 ,  1420 , and  1430 . Further, the I/O bus  1250  may be integrated into the chipset  1150 . 
         [0072]    The disk drive controller  1450  (i.e., internal disk drive) may also be operably coupled to the chipset  1150 . The disk drive controller  1450  may serve as the communication pathway between the chipset  1150  and one or more internal disk drives  1450 . The internal disk drive  1450  may facilitate disconnection of the external data storage devices by storing both instructions and data. The disk drive controller  1300  and the internal disk drives  1450  may communicate with each other or with the chipset  1150  using virtually any type of communication protocol, including all of those mentioned above with regard to the I/O bus  1250 . 
         [0073]    It is important to note that the system  1000  described above in relation to  FIG. 5  is merely one example of a system employing the semiconductor package as discussed above with relation to  FIGS. 1-4 . In alternate embodiments, such as cellular phones or digital cameras, the components may differ from the embodiments illustrated in  FIG. 5 . 
         [0074]    While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor package described herein should not be limited based on the described embodiments.