Abstract:
An image input apparatus which includes a connection unit capable of connecting with a detachable storage medium; a storage unit that stores a program for controlling the image input apparatus; a bus communicably coupled with the storage unit and the connection unit; a container unit adapted to contain the detachable storage medium; a detecting unit adapted to detect when a cover on the container unit is open; and a control unit configured to use the bus to access the detachable storage medium or the storage unit. When the detecting unit detects that the cover is open, the image input apparatus disables access from the control unit to the storage unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority from Japanese Patent Application No. 2003-369220 filed Oct. 29, 2003, which is hereby incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an image input apparatus, such as a digital camera, to which an external recording medium is removably attachable, and a control method therefore.  
         [0004]     2. Description of Related Art  
         [0005]     In a conventional digital camera, an interface circuit such as a buffer is provided between a system bus and a socket for a memory card, as disclosed in Japanese Laid-Open Patent Application No. 2000-295508. The interface circuit is configured to connect the memory card to the system bus. The system bus is included in a control system to which a microprocessor and memories, such as a ROM and a RAM, are connected. The interface circuit is composed mainly of a bus transceiver and has the function of preventing noise from being transmitted to the system bus. This noise occurs when a power source for the memory card is turned off for the purpose of saving electric power or when operation modes of the memory card are changed or when the memory card is inserted or removed while being supplied with electric power.  
         [0006]     However, since the interface circuit has various components, sufficient space for mounting these components is required. This causes an increase in size of the system and an increase in cost thereof.  
         [0007]     Furthermore, in cases where, in the above-described digital camera, the control system is composed of one integrated circuit, an interface circuit is also required between the memory card and a system bus included in the integrated circuit in order to prevent the turning-off of the power source for the memory card or the insertion or extraction of the memory card with power supplied from affecting the system bus. This necessitates that the integrated circuit be provided with data bus pins for the memory card in addition to pins for devices such as a ROM. Therefore, the integrated circuit is required to have a large number of pins. As a result, the integrated circuit becomes larger, thereby causing an increase both in system size and in cost of the integrated circuit.  
         [0008]     Japanese Laid-Open Patent Application No. Hei 10-97357 discloses a system for coping with this problem. In that technology, in a system in which a PC card (PCMCIA card) is used as the memory card, a data bus and an address bus for the PC card are coupled to a data bus and an address bus of the system together with a ROM, a RAM, etc. During a period of time when the state of card detection terminals of the PC card is changing, the operation of a CPU of the system is caused to temporarily stop. Accordingly, it is possible to eliminate the influence of noise caused by insertion or extraction of the PC card.  
         [0009]     However, it is difficult to detect all of the noise caused by insertion or extraction of the memory card (PC card) by using the card detection terminals of the PC card. For example, if the power source terminals of the PC card have deteriorated, the PC card&#39;s power source may be shut off before the insertion or extraction of the PC card detection terminals is detected. In this case, the data bus level is made low by the PC card power shut off such that data output from a memory element is accidentally changed. In this instance, if the CPU is in the process of reading out instructions from the ROM, the instructions read out by the CPU may be erroneous thus resulting in a system crash (system hang up).  
       SUMMARY OF THE INVENTION  
       [0010]     An object of the present invention is to overcome one or more of the disadvantages of conventional image input apparatuses.  
         [0011]     Accordingly, one advantage of the image input apparatus (e.g., digital camera) of the present invention is that system crashes due to noise signals caused when a removable recording medium is detached are prevented. Another advantage is that smaller system units can be produced at reduced cost.  
         [0012]     In an aspect of the present invention, an image input apparatus includes a connection unit capable of connecting with a detachable storage medium; a storage unit that stores a program for controlling the image input apparatus; a bus communicably coupled with the storage unit and the connection unit; a container unit adapted to contain the detachable storage medium; a detecting unit adapted to detect when a cover on the container unit is open; and a control unit configured to use the bus to access the detachable storage medium or the storage unit, wherein when the detecting unit detects that the cover is open, the control unit disables access from the control unit to the storage unit.  
         [0013]     In another aspect of the present invention, a control method for an image input apparatus including a connection unit capable of connecting with a detachable storage medium, a storage unit that stores a program for controlling the image input apparatus, a bus communicably coupled with the storage unit and the connection unit, a container unit adapted to contain the detachable storage medium, and a control unit configured to use the bus to access the detachable storage medium or the storage unit, the control method comprising steps of detecting that a cover on the container unit is open, and when it is detected that the-cover is open, disabling access from the control unit to the storage unit.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0015]      FIG. 1  is a block diagram showing the construction of a digital camera according to a first embodiment of the invention.  
         [0016]      FIG. 2  shows an example of address assignment provided by the system LSI of  FIG. 1 .  
         [0017]      FIG. 3  is a flow chart illustrating the procedures of operation control in a normal mode of the digital camera shown in  FIG. 1 .  
         [0018]      FIG. 4  is a flow chart illustrating the procedures of operation control in the normal mode of the digital camera shown in  FIG. 1 .  
         [0019]      FIG. 5  is a flow chart illustrating the procedures of interrupt processing in the digital camera shown in  FIG. 1 .  
         [0020]      FIG. 6  illustrates processing (performed when the cover of the container portion of the memory card is open) based on a second program stored in a DRAM of the digital camera of  FIG. 1 .  
         [0021]      FIG. 7  is a perspective view showing the relationship between a cover detection switch  18  and the cover  30 , which is provided at an aperture portion (container portion) for insertion and extraction of the memory card  7 .  
         [0022]      FIG. 8  is a block diagram showing the construction of a digital camera according to a second embodiment of the invention.  
         [0023]      FIG. 9  is a flow chart illustrating the procedures of operation control in a normal mode of the digital camera according to the second embodiment.  
         [0024]      FIG. 10  is a flow chart illustrating the procedures of operation control in the normal mode of the digital camera according to the second embodiment.  
         [0025]      FIG. 11  illustrates the procedures for setting or resetting a ROM access inhibition flag in the second embodiment.  
         [0026]      FIG. 12  is a block diagram showing the construction of a digital camera according to a third embodiment of the invention.  
         [0027]      FIG. 13  is a flow chart illustrating the procedures of operation control in a normal mode of the digital camera according to the third embodiment.  
         [0028]      FIG. 14  is a flow chart illustrating the procedures of operation control in the normal mode of the digital camera according to the third embodiment.  
         [0029]      FIG. 15  is a block diagram showing the construction of a digital camera according to a fourth embodiment of the invention.  
         [0030]      FIG. 16  shows connection signals between various components including the communication control IC  304  and the memory card controller  13  of  FIG. 15 .  
         [0031]      FIG. 17  is a diagram showing the transition of operation of an arbitration portion  303  shown in  FIG. 15 .  
         [0032]      FIG. 18  is a diagram showing signal waveforms occurring around the arbitration portion  303  shown in  FIG. 17 .  
         [0033]      FIG. 19  illustrates procedures associated with open and closed states of the cover in the digital camera of  FIG. 15 . 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0034]     Embodiments of the invention will be described in detail below with reference to the drawings.  
       First Embodiment  
       [0035]      FIG. 1  is a block diagram showing the construction of a digital camera, which is an example of an image input apparatus according to a first embodiment of the invention.  
         [0036]     The digital camera according to the first embodiment is composed of a system in which a ROM (Read Only Memory) and a DRAM (Dynamic Random Access Memory) have respective separate buses. Since the DRAM control signal requires higher timing constraints (to increase access speed) relative to that of the ROM, the DRAM bus is often provided separately from the ROM bus.  
         [0037]     More specifically, as shown in  FIG. 1 , the digital camera includes a system LSI  24  which constitutes a control system thereof. The system LSI  24  has two buses, i.e., a CPU bus  1  and an image bus  2 . To the CPU bus  1  are connected a CPU  3 , a memory controller  5 , a memory card controller  13 , a ROM controller  15 , an I/O (input/output interface)  25  and an interrupt controller  26 . The CPU  3  serves as a bus master for the CPU bus  1 . The CPU bus  1  is used to transfer data in response to a data transfer request from the CPU  3 . To the image bus  2  are connected the memory controller  5 , an image capture controller  10  and a display controller  12 . The image capture controller  10  and the display controller  12  serve as bus masters for the image bus  2 . The image bus  2  is used to transfer data in response to a data transfer request from the image capture controller  10  or the display controller  12 . Data transfer requests from the image capture controller  10  and the display controller  12  are arbitrated by an arbitration portion  17 .  
         [0038]     The memory controller  5  receives respective DRAM access requests from the CPU bus  1  and the image bus  2 , forms an access signal to a DRAM  6  while arbitrating the DRAM access requests, and performs data writing in the DRAM  6  or data reading from the DRAM  6 . The DRAM  6  stores work data used for executing programs, stores image data captured by the digital camera and stores image data for display on a display  11 .  
         [0039]     When gaining access to a ROM bus  20 , the ROM controller  15  or the memory card controller  13  is given a bus use right according to an arbitration performed by an arbitration portion  14 . Then, one of the ROM controller  15  and the memory card controller  13  to which the bus use right is given is enabled to use the ROM bus  20  via a multiplexer  16 . This enables the ROM controller  15  to access a ROM  4  or enables the memory card controller  13  to access a memory card  7 . The ROM  4  has a program stored therein for execution by the CPU  3  to control the digital camera. The memory card  7  is used to mainly store image files obtained by a shooting operation of the digital camera. The memory card  7  is connectable to the ROM bus  20  via a socket  8 , which is configured such that the memory card  7  is removably attachable to the socket  8 . The socket  8  is directly connected to the ROM bus  20  without any interface circuit such as a buffer. In addition, a data bus of the memory card  7  for use in the digital camera is composed of data lines, address lines and control lines of 16 bits. The memory card  7  is supplied with electric power from a card power source  27  via the socket  8 .  
         [0040]     To the I/O  25  are connected a mode switch  21  for allowing a user to select an operation mode of the digital camera, an operation switch  22  for allowing the user to input instructions to the digital camera, a shutter switch  23  for instructing the digital camera to start a shooting operation, and a cover detection switch  18 . The cover detection switch  18  is configured to detect an open or closed state of a cover  30  provided on a container portion  31  (as shown in  FIG. 7 ) used for receiving the memory card  7 . The CPU  3  determines whether the cover  30  is open or closed on the basis of an output of the cover detection switch  18 .  
         [0041]     The interrupt controller  26  receives an interrupt request signal from each module of the digital camera. Then, the interrupt controller  26  processes the interrupt request signal on the basis of predetermined setting values and outputs the processed signal. The output of the interrupt controller  26  is supplied to an interrupt request input terminal of the CPU  3 . This enables each module to send an interrupt request to the CPU  3 . Accordingly, when the cover detection switch  18  has detected the open state of the cover  30 , this detection enables an interrupt request signal to be generated and supplied to the CPU  3 .  
         [0042]     The image capture controller  10  is a circuit for generating digital image data by processing a digital image signal obtained from an image capture sensor  9 . The image capture sensor  9  converts an object image formed by a lens  19  into an electrical signal. The electrical signal is converted into a digital signal by an AD converter  28  and is then supplied to the image capture controller  10 .  
         [0043]     The display controller  12  generates a digital image signal from digital image data stored in the DRAM  6 . The generated digital image signal is converted into an analog image signal by a DA converter  29  and is then supplied to the display  11 . The display  11  is composed of a color liquid crystal display panel, etc., and is configured to display thereon an image represented by the analog image signal.  
         [0044]     As described above, in the digital camera according to the first embodiment, the ROM  4  and the memory card  7  are directly connected to the ROM bus  20 . Therefore, the ROM  4  and the memory card  7  do no have respective separate buses. A single bus, i.e., the ROM bus  20 , is used both for the ROM  4  and the memory card  7 . In addition, any external integrated circuit, such as a bus transceiver, is not provided between the socket  8  (the memory card  7 ) and the ROM bus  20 . Accordingly, a digital camera is provided in which the space for mounting components is reduced and in which cost reduction is attained.  
         [0045]     On the other hand, the system LSI  24  is provided with two buses, i.e., the CPU bus  1  and the image bus  2 . The reason for this is as follows.  
         [0046]     When a user pushes the shutter switch  23 , the digital camera is required to capture an object image formed on the image capture sensor  9  at that time. That is, the system LSI  24  should take in image data from the image capture sensor  9 .  
         [0047]     In addition, when an image is reproduced and displayed on the display  11 , the image displayed on the display  11  should not be distorted in any case. That is, the system LSI  24  should transfer data to the display controller  12 .  
         [0048]     Therefore, during a shooting operation or during a reproduction operation for image data, with regard to access to the DRAM  6  associated with execution of a program by the CPU  3 , access by the image capture controller  10  or the display controller  12  has priority.  
         [0049]     In the digital camera according to the first embodiment, in order not to lower the processing speed of the CPU  3  even in the above situation, the CPU bus  1  connected to the ROM  4  and the image bus  2  connected to the DRAM  6  are provided separately from each other. Accordingly, even when the digital camera is recording captured image data on the DRAM  6  or when it is transmitting image data to the display  11 , the CPU  3  fetches instructions from the ROM  4  without being hindered by access to the DRAM  6 . Therefore, lowering of the processing speed of the CPU  3  is kept to the minimum.  
         [0050]     As described above, in the digital camera according to the first embodiment, the ROM  4  and the memory card  7  are arranged to be connected to one and the same bus, i.e., the CPU bus  1 . Then, in the case of the first embodiment, when a power source for the memory card  7  is shut off or when the memory card  7  is removed, access to the ROM  4  is prevented, as will be described below.  
         [0051]     The positional relationship between the cover detection switch  18  and the cover  30  provided on the opening portion (container portion  31 ) for insertion and extraction of the memory card  7  is described below with reference to  FIG. 7 .  FIG. 7  is a perspective view showing the positional relationship between the cover detection switch  18  and the cover  30  provided on the opening portion (container portion  31 ) for insertion and extraction of the memory card  7 .  
         [0052]     The container portion  31  for receiving the memory card  7  is provided in the side portion of a digital camera body  32 , as shown in  FIG. 7 . The cover  30  on the container portion  31  can open and close to receive and remove the memory card  7  thereof The open or closed state of the cover  30  is detected by the cover detection switch  18 , as described above. The cover detection switch  18  is disposed inside the digital camera body  32  and is configured to output a detection signal indicative of the open or closed state of the cover  30 .  
         [0053]     Operation of the digital camera according to the first embodiment is described below with reference to FIGS.  2  to  6 .  FIG. 2  is a diagram showing an example of address assignment provided by the system LSI  24  shown in  FIG. 1 .  FIGS. 3 and 4  are flow charts illustrating the procedures of operation control in a normal mode of the digital camera shown in  FIG. 1 .  FIG. 5  is a flow chart illustrating the procedures of interrupt processing in the digital camera shown in  FIG. 1 .  FIG. 6  is a flow chart illustrating the procedures of processing based on a second program stored in the DRAM  6  shown in  FIG. 1 , i.e., processing performed when the cover  30  of the container portion  31  for the memory card  7  is open.  
         [0054]     In the system LSI  24 , each block connected to the CPU bus  1  decodes an address and performs an operation, such as register write or register read, with respect to access to the address assigned thereto. The assignment of these addresses is, for example, as shown in  FIG. 2 .  
         [0055]     In the case of the first embodiment, there are two exemplary programs for controlling the digital camera. One is a program for controlling the operation of the digital camera in a normal mode. This program is stored in the ROM  4 . The leading address of this program is assigned to 0×00000000. The other program is stored in the DRAM  6  and is executed when the cover  30  for the memory card  7  is open. Since the DRAM  6  is a non-volatile memory, the program stored in the DRAM  6  is transferred from the ROM  4  immediately after the system power source is turned on. The leading address of the program stored in the DRAM  6  is assigned to 0×40000000. In addition, areas for storing captured images and display images, a video RAM area for storing images to be displayed on the display  11 , etc., are set on the DRAM  6 .  
         [0056]     Operation control in a normal mode in the digital camera according to the first embodiment is described below with reference to FIGS.  3  to  5 . The procedures shown in  FIGS. 3 and 4  are performed by the CPU  3  in accordance with the program stored in the ROM  4  for controlling the operation of the digital camera in the normal mode.  
         [0057]     At step S 100 , when the digital camera is powered on, the CPU  3  checks the operation mode set by the mode switch  21  at step S 101 , as shown in  FIG. 3 . The operation mode settable by the mode switch  21  includes a shooting mode for performing a shooting operation and an image display mode for causing image files stored in the memory card  7  to be displayed on the display  11 . If the operation mode as set is the shooting mode, the CPU  3  waits for the shutter switch  23  to be operated at step S 110  shown in  FIG. 4 . If the shutter switch  23  is activated by the user, the CPU  3  performs the shooting operation at step S 111 . In the shooting operation, an object image formed by the lens  19  is converted into an electrical signal by the image capture sensor  9 . The electrical signal is converted into a digital image signal by the AD converter  28  and is then supplied to the image capture controller  10 . The image capture controller  10  performs processing, such as image processing and data compression, on the supplied digital image signal and then temporarily stores the processed digital image signal in the DRAM  6 .  
         [0058]     Then, at step S 112 , the CPU  3  checks to determine if a media access inhibition flag is already set. The media access inhibition flag is a flag indicating that access to the memory card  7  is inhibited. In this instance, since the media access inhibition flag is not yet set, the CPU  3  proceeds to step S 113 . At step S 113 , the CPU  3  transfers image data stored in the DRAM  6  to the memory card  7  in units of a predetermined data amount, such as one sector, and writes the image data in the memory card  7 .  
         [0059]     At step S 114 , the CPU  3  checks to determine if all the image data stored in the DRAM  6  have been written in the memory card  7 . If writing of all the image data is not yet completed, the CPU  3  returns to the above step S 112  and repeats processing beginning with the step S 112 . If it is determined during the process of this loop processing (at step S 112 ) that the media access inhibition flag has been set, the CPU  3  proceeds to step S 115 . At step S 115 , the CPU  3  resets the media access inhibition flag and returns the process to step S 101 . This causes writing of image data in the memory card  7  to be suspended at the above step S 112 .  
         [0060]     If it is determined at step S 114  that writing of all the image data has been completed, the CPU  3  returns the process to the above step S 101 .  
         [0061]     If it is determined at step S 101  that the image display mode is selected as the operation mode, the CPU  3  waits for the operation switch  22  to be operated by the user at step S 102 . In this case, the operation switch  22  is assumed to be operated by the user so as to designate an image to be displayed. If the operation switch  22  is operated by the user, the CPU  3  starts reading out an image file designated by the user.  
         [0062]     Then, at step S 103 , the CPU  3  checks to determine if the media access inhibition flag is already set. If it is determined at step S 103  that the media access inhibition flag is not yet set, the CPU  3  proceeds to step S 104 . At step S 104 , the CPU  3  performs reading of the image file from the memory card  7 . Reading of the image file is performed by transferring a data file stored in the memory card  7  to the DRAM  6  in units of predetermined data size. At step S 105 , the CPU  3  checks to determine if reading, i.e., transfer to the SRAM  6 , of all data of the image file has been completed. If it is determined at step S 105  that reading of all data of the image file has not yet been completed, the CPU  3  returns to the above step S 103  and repeats processing beginning with the step S 103 . If it is determined during the process of transfer of image data or before transfer of image data (at step S 103 ) that the media access inhibition flag has been set, the CPU  3  proceeds to step S 107 . At step S 107 , the CPU  3  resets the media access inhibition flag and returns the process to the above step S 101 . This causes reading of the image file to be suspended.  
         [0063]     If it is determined at step S 105  that reading of all data of the image file has been completed, the CPU  3  proceeds to step S 106 . At step S 106 , the CPU  3  decompresses, on the DRAM  6 , compressed image data read out to the DRAM  6  and transfers the decompressed image data to the display controller  12 . The display controller  12  transfers the transferred image data to the display  11  via the DA converter  29 . This causes an image represented by the image file read out from the memory card  7  to be displayed on the display  11 .  
         [0064]     In addition to the program corresponding to the flow charts of  FIGS. 3 and 4 , a program to be executed when an interrupt request signal is detected is stored in the ROM  4 . The interrupt controller  26  receives interrupt request signals from individual blocks. The interrupt request signals include inputs from the I/O  25 . One of the inputs from the I/O  25  is an interrupt request signal that becomes active when the cover  30  for the memory card  7  is opened. If any one of the interrupt request signals is detected, the CPU  3  causes the process to skip to interrupt processing. In the interrupt processing, more specifically, as shown in  FIG. 5 , the CPU  3  first starts processing at step S 120 . At the next step S 121 , the CPU  3  causes the process to jump to 0×40000000, which is the leading address of the second program stored in the DRAM  6 . Then, at step S 122 , the CPU  3  exits from this processing.  
         [0065]     Processing to be performed according to the second program stored in the DRAM  6 , i.e., processing to be performed when the cover  30  of the container portion  31  for the memory card  7  is open, is described below with reference to  FIG. 6 .  
         [0066]     If the open state of the cover  30  of the container portion  31  for the memory card  7  is detected, the CPU  3  starts processing at step S 130 , as shown in  FIG. 6 . At step S 132 , the CPU  3  sets the media access inhibition flag. Accordingly, access to the memory card  7  is inhibited.  
         [0067]     Then, at step S 133 , the CPU  3  causes a message indicative of the open state of the cover  30  to be displayed on the display  11 . For example, a message “Cover is Open” is displayed on the display  11 . This display notifies the user that the cover  30  is open and that the digital camera is suspending processing such as access to the memory card  7 , image capturing and image display.  
         [0068]     At step S 134 , the CPU  3  checks to determine if the cover  30  has been closed, on the basis of a detection signal from the cover detection switch  18 . If the cover  30  is in the open state, the CPU  3  proceeds to step S 135 . At step S 135 , the CPU  3  checks to determine if a power source voltage is above a predetermined value. If yes, the CPU  3  proceeds to step S 136 , where the CPU  3  checks to determine if the temperature inside the digital camera is within a predetermined range. If temperature is within the predetermined range, the CPU  3  returns the process to the above step S 134 .  
         [0069]     If it is determined at the step S 135  that the power source voltage is not above the predetermined value, or if it is determined at the step S 136  that temperature inside the digital camera is not within the predetermined range, the CPU  3  proceeds to step S 138 . At step S 138 , the CPU  3  shuts off the power source of the digital camera, and, at step S 139 , brings the process to an end.  
         [0070]     If cover  30  is closed at step S 134 , the CPU  3  exits processing at step S 137  and returns from the second program to the interrupt processing process (step S 120  of  FIG. 5 ) of the first program. Accordingly, the CPU  3  program counter returns to instructions that were previously executed upon detection of an interrupt request, and the CPU  3  then continues processing. However, since the media access inhibition flag remains set, if the cover  30  is opened during access to the memory card  7  by the first program, access to the memory card  7  is suspended. Thus, until the cover  30  is closed, the CPU  3  executes the program stored in the DRAM  6  and does not access the ROM  4 . Consequently, even when noise occurs at the ROM bus  20  when the memory card  7  is removed, the digital camera operation remains relatively unaffected.  
         [0071]     Furthermore, since read or write access to memory card  7  is processed in predetermined data units (e.g., per sector), the total time corresponding to the data unit is required. The total time is measured from when the cover  30  is opened to when access to the memory card  7  actually ends. However, this time is at least several milliseconds because extraction of the memory card  7  is performed manually by the user. Accordingly, memory access for every unit can be completed within at least several milliseconds.  
         [0072]     As described above, in the digital camera according to the first embodiment, as long as the cover  30  of the container portion  31  for the memory card  7  is open, the CPU  3  is prevented from accessing the ROM  4 . Therefore, even if an unexpected signal, for example, noise, is caused at the ROM  4  by insertion or extraction of the memory card  7 , the CPU  3  does not access the ROM  4 , so that the system remains stable and does not crash or hang up. Accordingly, the memory card  7  and the ROM  4  can have one and the same bus in common without using any integrated circuit, such as a bus transceiver. As a result, a reduction in size and cost of the digital camera can be realized.  
         [0073]     It should be noted that the first embodiment can be implemented with image input apparatuses other than digital cameras (for example, digital video cameras, camera integrated mobile phones and camera integrated portable terminals).  
       Second Embodiment  
       [0074]     A second embodiment of the invention is described below with reference to FIGS.  8  to  11 .  FIG. 8  is a block diagram showing the construction of a digital camera which is an example of an image input apparatus according to the second embodiment.  FIGS. 9 and 10  are flow charts illustrating the procedures of operation control in a normal mode of the digital camera according to the second embodiment.  FIG. 11  is a flow chart illustrating the procedures of processing for setting or resetting a ROM access inhibition flag in the second embodiment.  
         [0075]     As shown in  FIG. 8 , in the second embodiment, a card power source  201  is connected to the I/O  25  and supply of electric power from the card power source  201  to the memory card  7  is controlled by the CPU  3  and the entire program stored in the ROM  4  (operation control programs in the normal mode) is transferred to the DRAM  6 . In the second embodiment, the same blocks as those shown in  FIG. 1  are denoted by the same reference numerals and are omitted from the following discussion.  
         [0076]     Operation control in the normal mode of the digital camera according to the second embodiment is described below with reference to  FIGS. 9 and 10 . The procedures shown in  FIGS. 9 and 10  are performed by the CPU  3  in accordance with the program stored in the ROM  4  for controlling the operation in the normal mode of the digital camera.  
         [0077]     If the power source of the digital camera is turned on at step S 201 , the CPU  3  first transfers a program stored in the ROM  4  to the DRAM  6  at step S 202 , as shown in  FIG. 9 . In this regard, however, user interface images, such as icon images, for use in a menu, etc., to be displayed for the user at the time of shooting or image display are not transferred to the DRAM  6 . This is because an area for storing image data in the DRAM  6  is required to be kept large, so that the number of shootable frames in a continuous shooting operation or the switching speed of images in an image display mode can be increased. At step S 203 , the CPU  3  causes the process to jump to the program transferred to the DRAM  6 . After this, the CPU  3  begins to acquire instructions from the DRAM  6  and not from the ROM  4  although in exceptional cases, the CPU  3  may acquire instructions from the ROM  4 . For example, in cases where a menu is displayed on the display  11 , user interface images, such as icon images, for use in displaying the menu are transferred from the ROM  4  to the DRAM  6  on a case-by-case basis. The reason for this is as follows. Since the data size of a user interface image such as an icon image is relatively large, if all of the various icon images, for example, are previously transferred to the DRAM  6 , the free space of the DRAM  6  becomes small. In such a situation that the free space of the DRAM  6  is small, the number of shootable frames in a continuous shooting operation, for example, becomes small, thereby lowering the performance of the digital camera. Therefore, user interface images, such as icon images, for use in displaying a menu are normally stored in the ROM  4 , although required images may be transferred to the DRAM  6  when needed.  
         [0078]     At step S 204 , the CPU  3  checks to determine which of the shooting mode and the image display mode is selected as the operation mode in response to the operation of the mode switch  21 . If the shooting mode is selected, the CPU  3  proceeds to step S 212  shown in  FIG. 10 . At step S 212 , the CPU  3  checks to determine if a ROM access inhibition flag is already set. The ROM access inhibition flag is a flag indicating that access to the ROM  4  is inhibited in the case where the cover  30  of the container portion  31  for the memory card  7  is open. If it is determined at step S 212  that the ROM access inhibition flag is not set as the cover  30  is not open, the CPU  3  proceeds to step S 213 . At step S 213 , the CPU  3  transfers user interface images to be displayed on the display  11  from the ROM  4  to a video RAM area of the DRAM  6 . This causes the user interface images to be displayed on the display  11 . Specifically, to prevent data read out from the ROM  4  from changing due to noise caused at the ROM bus  20  by insertion or extraction of the memory card  7  during access to the ROM  4 , the user interface images may be transferred from the ROM  4  to the DRAM  6  in the case where the ROM access inhibition flag is not set.  
         [0079]     At step S 214 , the CPU  3  checks to determine if the shutter switch  23  has been operated. If the shutter switch  23  has been operated, the CPU  3  proceeds to step S 215 . At step S 215 , the CPU  3  performs a shooting operation. After completion of the shooting operation, the CPU  3  proceeds to step S 216 . At step S 216 , in order to transfer compressed image data stored in the DRAM  6  to the memory card  7 , the CPU  3  checks to determine if the memory card  7  is currently mounted on the socket  8 . The socket  8  is provided with a card detection terminal. The CPU  3  makes the above check by using the card detection terminal. If it is determined at step S 216  that the memory card  7  is currently mounted on the socket  8 , the CPU  3  proceeds to step S 217 . At step S 217 , the CPU  3  transfers image data stored in the DRAM  6  to the memory card  7  in units of a predetermined data amount, and writes the image data in the memory card  7 . At step S 218 , the CPU  3  checks to determine if all of the image data have been transferred to the memory card  7 . If all of the image data have not yet been transferred to the memory card  7 , the CPU  3  returns the process to the above step S 216 , and repeats processing beginning with the step S 216 . If it is determined at step S 218  that transfer of all of the image data to the memory card  7  has been competed, the CPU  3  returns the process to the above step S 204 . If, at step S 216 , the memory card  7  is removed during the process of transferring the image data from the DRAM  6  to the memory card  7 , the CPU  3  returns the process to the above step S 204 , thereby suspending writing of data in the memory card  7 .  
         [0080]     If it is determined at the above step S 212  that the ROM access inhibition flag is already set, the CPU  3  proceeds to step S 219 . At step S 219 , the CPU  3  causes a message indicative of the open state of the cover  30  to be displayed on the display  11 . Then, the CPU  3  returns the process to the above step S 204 .  
         [0081]     If it is determined at the above step S 204  that the image display mode is selected, the CPU  3  proceeds to step S 205 . At step S 205 , the CPU  3  checks to determine if the ROM access inhibition flag is already set. If the ROM access inhibition flag is not yet set, the CPU  3  proceeds to step S 206 . At step S 206 , the CPU  3  transfers user interface images from the ROM  4  to the DRAM  6 . The user interface images inform the user of an operation method of the digital camera. The user interface images are displayed on the display  11  after being transferred to the video RAM area of the DRAM  6 .  
         [0082]     Then, at step S 207 , the CPU  3  waits for the operation switch  22  to be operated by the user. In this case, the operation switch  22  is assumed to be operated by the user so as to designate a predetermined image file recorded on the memory card  7  to be displayed on the display  11 . If the operation switch  22  is operated by the user, the CPU  3  proceeds to step S 208 . At step S 208 , the CPU  3  checks to determine if the memory card  7  is currently mounted, by using the card detection terminal provided in the socket  8 . If the memory card  7  is currently mounted, the CPU  3  proceeds to step S 209 . At step S 209 , the CPU  3  reads out an image file recorded on the memory card  7  and transfers the read-out image file to the video RAM area of the DRAM  6 . Transfer of the image file is performed by transferring data in units of a predetermined data amount. Then, at step S 210 , the CPU  3  checks to determine if reading of the image file has been completed. If reading of the image file has not yet been completed, the CPU  3  returns the process to the above step S 208  and repeats processing beginning with the sep S 208 . If reading of the image file has been completed, the CPU  3  proceeds to step S 211 . At step S 211 , the CPU  3  drives and controls the display controller  12  to cause the read-out image file to be displayed on the display  11 .  
         [0083]     If it is determined at the above step S 208  that the memory card  7  has been removed during the process of transferring the image file, the CPU  3  returns the process to the above process S 204 , thereby suspending reading of the image file from the memory card  7 .  
         [0084]     If it is determined at the above step S 205  that the ROM access inhibition flag is already set, the CPU  3  proceeds to step S 219  shown in  FIG. 10 . At step S 219 , the CPU  3  causes a message indicative of the open state of the cover  30  to be displayed on the display  11 . Then, the CPU  3  returns the process to the above step S 204 .  
         [0085]     Processing for setting or resetting of the ROM access inhibition flag is now described below with reference to  FIG. 11 .  
         [0086]     If the cover  30  of the container portion  31  for the memory card  7  is opened when the digital camera is in the operative condition, opening of the cover  30  is detected by the cover detection switch  18 . Then, an interrupt request signal is supplied from the interrupt controller  26  to the CPU  3 . In response to the interrupt request signal, the CPU  3  starts interrupt processing at step S 230 , as shown in  FIG. 11 . At step S 231 , in order to again confirm the open or closed state of the cover  30 , the CPU  3  checks to determine if the cover  30  is open, on the basis of a detection signal from the cover detection switch  18 . If the cover  30  is open, the CPU  3  proceeds to step S 232 . At step S 232 , the CPU  3  sets the ROM access inhibition flag. Then, at step S 233 , the CPU  3  exits from this processing and returns to processing performed before the start of interrupt processing.  
         [0087]     If closing of the cover  30  is detected by the cover detection switch  18 , an interrupt request signal is supplied from the interrupt controller  26  to the CPU  3 . In response to the interrupt request signal, the CPU  3  starts interrupt processing at step S 230 , as shown in  FIG. 11 . At step S 231 , in order to again confirm the open or closed state of the cover  30 , the CPU  3  checks the cover  30  using a detection signal from the cover detection switch  18 . If the cover  30  is closed, the CPU  3  proceeds to step S 241 . At step S 241 , the CPU  3  resets the ROM access inhibition flag. Then, at step S 233 , the CPU  3  exits from this processing and returns to processing performed before the start of interrupt processing.  
         [0088]     If the cover  30  of the container portion  31  for the memory card  7  is opened during the process of transferring the image data, access to the ROM  4  cannot be suspended unless access for one unit is completed. This is because access to the ROM  4  is performed in units of a predetermined data amount, for example, one icon image. However, since opening of the cover  30  to remove the memory card  7  is manually performed by the user, a length of time of at least several milliseconds is required for this operation. Therefore, access to the ROM  4  can be inhibited before the memory card  7  is removed.  
         [0089]     Note that the control of data transfer from the ROM  4  to the DRAM  6  can be performed by using the DMA controller  31 . In this case, the DMA controller  31  is activated by the CPU  3 . The CPU  3  confirms the set or reset state of the ROM access inhibition flag before activating the DMA controller  31 . If the ROM access inhibition flag is already set, the CPU  3  investigates the cause of setting of the ROM access inhibition flag. If the ROM access inhibition flag has been set due to the open state of the cover  30  of the container portion  31  for the memory card  7 , a message indicative of such a cause is displayed on the display  11  so as to request the user to close the cover  30 . If the ROM access inhibition flag has been set due to the shut-off of a power source for the memory card  7 , the supply of electric power from the card power source  201  to the memory card  7  is started. Then, after confirming that the cover  30  has been closed and electric power is being supplied to the memory card  7 , the CPU  3  activates the DMA controller  31 . This enables data transfer from the ROM  4  to the DRAM  6  to be attained.  
         [0090]     In accordance with the second embodiment of the digital camera, the entire operation control program for use in the normal mode is transferred to the DRAM  6 . In addition, even in cases where the ROM  4  is accessed to fetch user interface images, access to the ROM  4  is inhibited when the memory card  7  is removed. Accordingly, the system of the digital camera can be prevented from hanging up due to noise caused by insertion or extraction of the memory card  7 . In addition, since any device, such as a bus transceiver, is not required between the memory card  7  and the ROM bus  20 , a reduction in size and cost of the digital camera can be realized.  
         [0091]     It should be noted that as in the first embodiment, the second embodiment can also be implemented with image input apparatuses other than digital cameras (for example, digital video cameras, camera integrated mobile phones and camera integrated portable terminals).  
       Third Embodiment  
       [0092]     A third embodiment of the invention is described below with reference to FIGS.  12  to  14 . FIGS.  12  to  14  are flow charts illustrating the procedures of operation control in a normal mode of a digital camera which is an example of an image input apparatus according to the third embodiment. The third embodiment has the same construction as that of the second embodiment, which is, therefore, omitted from the following discussion.  
         [0093]     In the third embodiment, when the cover  30  is closed in the normal mode, power supply to the memory card  7  is started.  
         [0094]     When a power source of the digital camera is turned on, the CPU  3  starts processing at step S 251 , as shown in  FIG. 12 . Then, at step S 291 , the CPU  3  checks for the open or closed state of the cover  30  of the container portion  31  for the memory card  7  on the basis of a detection signal from the cover detection switch  18 . If the cover  30  is in the open state, the CPU  3  proceeds to step S 292 . At step S 292 , the CPU  3  causes a message prompting a user to close the cover  30  to be displayed on the display  11 , and returns the process to the step S 291 .  
         [0095]     If the cover  30  is in the closed state, the CPU  3  proceeds to step S 252 . At step S 252 , the CPU  3  transfers a camera control program stored in the ROM  4  to the DRAM  6 . At the next step S 253 , the CPU  3  causes a program execution address to jump to the leading address of the program on the DRAM  6 . Then, at step S 254 , the CPU  3  shuts off power supply to the memory card  7  by controlling the card power source  201  via the I/O  25 .  
         [0096]     At the next step S 270 , the CPU  3  checks for the operation mode selected by the mode switch  21 . If the shooting mode is selected as the operation mode, the CPU  3  proceeds to step S 293  shown in  FIG. 14 . At step S 293 , the CPU  3  checks for the open or closed state of the cover  30  of the container portion  31  for the memory card  7 . If the cover  30  is in the open state, the CPU  3  proceeds to step S 294 . At step S 294 , the CPU  3  causes a message prompting the user to close the cover  30  to be displayed on the display  11 , and returns the process to the step S 293 .  
         [0097]     If the cover  30  is in the closed state, the CPU  3  proceeds to step S 256 . At step S 256 , the CPU  3  supplies electric power to the memory card  7  by controlling the card power source  201  via the I/O  25 . At the next step S 257 , the CPU  3  transfers user interface images from the ROM  4  to the DRAM  6 . The user interface images are images used to display, in a user-friendly manner, parameters required at the time of shooting, for example, aperture, shutter speed, white balance, etc. The user interface images are transferred to the video RAM area of the DRAM  6  so as to be displayed on the display  11 . At step S 258 , the CPU  3  shuts off power supply to the memory card  7  by controlling the card power source  201  via the I/O  25 . The CPU  3  temporarily supplies electric power to the memory card  7  when transferring data from the ROM  4  to the DRAM  6 , otherwise, the memory card  7  causes the ROM bus  20  to go low. When electric power is being supplied to the memory card  7 , the ROM bus  20  is kept at high level unless read access to the memory card  7  is performed, so that access to the ROM  4  can be performed.  
         [0098]     At the next step S 259 , the CPU  3  waits for the shutter switch  23  to be operated by the user. If the user has operated the shutter switch  23 , the CPU  3  proceeds to step S 260 . At step S 260 , the CPU  3  performs a shooting operation. Then, at step S 261 , the CPU  3  starts power supply to the memory card  7 .  
         [0099]     At the next step S 262 , the CPU  3  checks to determine if the memory card  7  has been removed from the socket  8 , by using a card detection terminal provided on the socket  8 . If the memory card  7  has not been removed, the CPU  3  proceeds to step S 263 . At step S 263 , the CPU  3  transfers image data stored in the DRAM  6  to the memory card  7  in units of a predetermined data amount. At the next step S 264 , the CPU  3  checks to determine if transfer of image data to the memory card  7  has been completed. If transfer of all of the image data to the memory card  7  has not yet been completed, the CPU  3  returns the process to the step S 262  and repeats processing beginning with the step S 262 . If transfer of all of the image data to the memory card  7  has been completed, the CPU  3  returns the process to the above step S 254  and repeats processing beginning with the step S 254 .  
         [0100]     If the memory card  7  has been removed during the process of transferring data to the memory card  7  (at step S 262 ), the CPU  3  proceeds to step S 280  shown in  FIG. 13 . At step S 280 , the CPU  3  causes a message indicating that the memory card  7  is not mounted to be displayed on the display  11 , and returns the process to the above step S 254 . This causes writing of data in the memory card  7  to be suspended.  
         [0101]     If it is determined at the above step S 270  (shown in  FIG. 12 ) that the operation mode selected by the mode switch  21  is the image display mode, the CPU  3  proceeds to step S 295 . At step S 295 , the CPU  3  checks for the open or closed state of the cover  30  of the container portion  31  for the memory card  7 . If the cover  30  is in the open state, the CPU  3  proceeds to step S 296 . At step S 296 , the CPU  3  causes a message prompting the user to close the cover  30  to be displayed on the display  11 , and returns the process to the step S 295 .  
         [0102]     If the cover  30  is in the closed state, the CPU  3  proceeds to step S 271  shown in  FIG. 13 . At step S 271 , the CPU  3  supplies electric power to the memory card  7  by controlling the card power source  201  via the I/O  25 . Then, at step S 272 , the CPU  3  transfers user interface images stored in the ROM  4  to the DRAM  6 . These user interface images are images used to display an operation method, such as a method for changing image files displayed in the image display mode, together with an image on the display  11 .  
         [0103]     At the next step S 273 , the CPU  3  shuts off power supply to the memory card  7 . The CPU  3  temporarily supplies electric power to the memory card  7  when transferring data from the ROM  4  to the DRAM  6 , otherwise, the ROM bus  20  comes into a high-impedance state, thereby enabling access to the ROM  4 . Then, at step S 274 , the CPU  3  waits for the operation switch  23  to be operated by the user. This operation by the user is performed to give instructions for display of an image or display of the next image. In this instance, it is assumed in the following discussion that the user gives instructions for display of an image.  
         [0104]     If instructions for display of an image are given by the user, the CPU  3  proceeds to step S 275 . At step S 275 , the CPU  3  starts power supply to the memory card  7 . Then, at step S 276 , the CPU  3  checks to determine if the memory card  7  has been removed, on the basis of the card detection terminal provided on the socket  8 . If the memory card  7  has not been removed, the CPU  3  proceeds to step S 277 . At step S 277 , the CPU  3  reads out an image file recorded on the memory card  7  and transfers the read-out image file to the video RAM area of the DRAM  6 . This transfer of the image file is performed in units of a predetermined data amount.  
         [0105]     At the next step S 278 , the CPU  3  checks to determine if reading of the image file has been completed. If this reading has not yet been completed, the CPU  3  returns the process to the step S 276 . If reading of the image file has been completed, the CPU  3  proceeds to step S 279 . At step S 279 , the CPU  3  drives the display controller  12  so as to display the read-out image on the display  11 , and returns the process to the above step S 254 .  
         [0106]     If the memory card  7  has been removed during the process of reading out the image file (at step S 276 ), the CPU  3  proceeds to step S 280 . At step S 280 , the CPU  3  causes a message indicating that the memory card  7  is not mounted to be displayed on the display  11 , and returns the process to the above step S 254 .  
         [0107]     As described above, in the digital camera according to the third embodiment, if the need to read out user interface images or the like from the ROM  4  arises, power supply to the memory card  7  starts before the start of access to the ROM  4 . When reading of data from the ROM  4  has been completed, power supply to the memory card  7  stops. Accordingly, when electric power is not being supplied to the memory card  7 , the problem wherein the memory card  7  makes the ROM bus  20  go low, thereby causing data read out from the ROM  4  to become erroneous, can be avoided.  
         [0108]     Furthermore, in the digital camera according to the third embodiment, when the memory card  7  is removed, access to the ROM  4  is inhibited. Accordingly, the system of the digital camera can be prevented from hanging up due to noise caused by insertion or extraction of the memory card  7 .  
         [0109]     It should be noted that, similarly to the first embodiment, the third embodiment can also be implemented with image input apparatuses other than digital cameras (for example, digital video cameras, camera integrated mobile phones and camera integrated portable terminals).  
       Fourth Embodiment  
       [0110]     A fourth embodiment of the invention is described below with reference to FIGS.  15  to  19 .  FIG. 15  is a block diagram showing the construction of a digital camera, which is an example of an image input apparatus according to the fourth embodiment.  FIG. 16  shows connection signals between various components including the communication control IC  304  and the memory card controller  13  of  FIG. 15 .  FIG. 17  is a diagram showing the transition of operation of an arbitration portion  303  shown in  FIG. 15 .  FIG. 18  is a diagram showing signal waveforms occurring around the arbitration portion  303  shown in  FIG. 17 .  FIG. 19  is a flow chart illustrating the procedures of processing associated with the open and closed states of the cover  30  in the digital camera shown in  FIG. 15 .  
         [0111]     Among other components, the fourth embodiment provides a system LSI  305  and a communication control IC  304  as shown in  FIG. 15 .  
         [0112]     More specifically, the communication control IC  304  is an integrated circuit for performing communication with an external device (not shown) via a communication line  306  and for performing transfer of data received from the external device or data to be transmitted to the external device with the system LSI  305 . The communication control IC  304  performs communication with the external device in compliance with a standard, such as IEEE1394 or USB2.0. In addition, the communication control IC  304  has a data input/output port and a control signal port for data transfer with the system LSI  305 .  
         [0113]     The system LSI  305  includes, among others, an external DMA controller  301 , a multiplexer  302  and an arbitration portion  303 . The external DMA controller  301  is connected to the CPU bus  1  and serves as a control circuit for directly transferring data between the external device and the DRAM  6 . The multiplexer  302  selects data and address buses of the external DMA controller  301  or data and address buses of the memory card controller  13  and connects the selected buses to an external bus  307 . The arbitration portion  303  conducts arbitration of a data transfer request between the external DMA controller  301  and the memory card controller  13 . Further, the arbitration portion  303  fetches a detection signal from the cover detection switch  18  and supplies the detection signal to the interrupt controller  26 .  
         [0114]     The connection signals between various components including the communication control IC  304  and the memory card controller  13  is now described in detail below with reference to  FIG. 16 .  
         [0115]     The communication control IC  304  outputs a signal DMAREQ indicative of a communication request, which is supplied to the external DMA controller  301 . The external DMA controller  301  outputs a communication acknowledge signal DMAACK, a write strobe signal WR and a read strobe signal RD, which are supplied to the communication control IC  304 .  
         [0116]     The memory card controller  13  outputs a chip enable signal CE, a write strobe signal WR and a read strobe signal RD, which are supplied to the socket  8  and the memory card  7 . In addition, a card detection signal CD (hereinafter referred to as the “signal CD”) exists at the memory card  7 . The signal CD is connected to ground inside the memory card  7 . The signal CD is connected to the memory card controller  13  via the socket  8  and is connected, between them, to a power source via a resistor, i.e., is pulled up. Accordingly, the signal CD as viewed from the memory card  7  is low when the memory card  7  is mounted on the socket  8 , and is high when the memory card  7  is not mounted.  
         [0117]     The arbitration portion  303  is a circuit for conducting arbitration of a right of use of the external bus  307  between the external DMA controller  301  and the memory card controller  13 . The external DMA controller  301  outputs a right-of-use-of-bus request signal EXDMAREQ, which is supplied to the arbitration portion  303 . The arbitration portion  303  outputs a use-of-bus grant signal EXDMAGRNT, which is supplied to the external DMA controller  301 . In addition, the memory card controller  13  outputs a right-of-use-of-bus request signal CARDREQ, which is supplied to the arbitration portion  303 . The arbitration portion  303  also outputs a use-of-bus grant signal CARDGRNT, which is supplied to the memory card controller  13 . Further, the arbitration portion  303  receives a detection signal COVEROPEN from the cover detection switch  18 .  
         [0118]     Buses including address and data buses of the external DMA controller  301  and the memory card controller  13  are connected to the multiplexer  302 . The multiplexer  302  selects the buses of one of the external DMA controller  301  and the memory card controller  13  and connects the selected buses to the external bus  307 . The external bus  307  is connected to the address and data buses of the memory card  7  via the address and data buses of the communication control IC  304  and the socket  8 .  
         [0119]     Operation of the arbitration portion  303  is described below with reference to  FIGS. 17 and 18 .  
         [0120]     When both operations of the external DMA controller  301  and the memory card controller  13  are under suspension, the arbitration portion  303  comes into an idle state (step S 301  shown in  FIG. 17 ). The communication control IC  304  controls communication of data with an externally connected communication line (IEEE1394, USB2.0 or the like) or another external system connected to the communication line. Further, the communication control IC  304  generates a signal DMAREQ depending on conditions of communication with another system, for example, when data transmitted from another system exists in a data buffer within the communication control IC  304 .  
         [0121]     When receiving the signal DMAREQ from the communication control IC  304  at time A shown in  FIG. 18 , the external DMA controller  301  generates the signal EXDMAREQ to the arbitration portion  303 . If, at step S 301  shown in  FIG. 17 , the signal EXDMAREQ is true (logical “1”), the signal CARDREQ is false (logical “0”) and the signal COVEROPEN is false, the state of the arbitration portion  303  proceeds to step S 302 . At step S 302 , the signal EXDMAGRNT becomes true, so that the external DMA controller  301  is given a right of use of the external bus  307 .  
         [0122]     The external DMA controller  301  controls the multiplexer  302  to cause the data bus of the external DMA controller  301  to be connected to the external bus  307 , and performs transmission or receiving of data while asserting the signal DMAACK. Once transmission or receiving of data is attained, the external DMA controller  301  makes the signal EXDMAREQ false. Accordingly, the state of the arbitration portion  303  returns to step S 301 .  
         [0123]     If the CPU  3  starts access to the memory card  7  before the above-described DMA (direct memory access) is completed, the memory card controller  13  makes the signal CARDREQ true at a point of time B shown in  FIG. 18  and outputs this signal to the arbitration portion  303 . In response to the signal CARDREQ, the state of the arbitration portion  303  proceeds from step S 301  to step S 303 . Accordingly, the arbitration portion  303  makes the signal CARDGRNT true at time C and outputs this signal to the memory card controller  13 . The memory card controller  13  recognizes that a right of use of bus is granted to the memory card  7 , and performs access to the memory card  7 . In accessing the memory card  7 , the memory card controller  13  makes a signal CE true and outputs this signal to the memory card  7 , thereby bringing the memory card  7  into a selected state. In this state, the memory card controller  13  makes the signal WR or RD true and outputs this signal to the memory card  7  to perform transmission or receiving of data. When one occurrence of access to the memory card  7  has been attained, the memory card controller  13  changes the signal CARDREQ from the true state to the false state. Accordingly, the arbitration portion  303  makes the signal CARDGRNT false and comes into the idle state (step S 301 ).  
         [0124]     If the external DMA controller  301  makes the signal EXDMAREQ true and outputs this signal to the arbitration portion  303  during the process of access to the memory card  7 , the arbitration portion  303  ends access to the memory card  7  and comes into the idle state (step S 301 ). Then, the state of the arbitration portion  303  proceeds to step S 302 . Accordingly, the signal EXDMAGRNT becomes true at time D shown in  FIG. 18 , so that a right of use of the external bus  307  is given to the external DMA controller  301 .  
         [0125]     The external DMA controller  301  controls the multiplexer  302  to cause the data bus of the external DMA controller  301  to be connected to the external bus  307 , and performs transmission or receiving of data while asserting the signal DMAACK. After transmission or receiving of data is attained, the external DMA controller  301  makes the signal EXDMAREQ false.  
         [0126]     If, in this state, the cover  30  of the container portion  31  for the memory card  7  is opened, the signal COVEROPEN becomes true. In addition, in this state, it is assumed that the communication control IC  304  makes the signal DMAREQ true and outputs this signal to the external DMA controller  301  at time E shown in  FIG. 18 . Accordingly, the external DMA controller  301  makes the signal EXDMAREQ true and outputs this signal to the arbitration portion  303 .  
         [0127]     In the above case, the arbitration portion  303  recognizes that the signal EXDMAREQ has become true. However, since the signal COVEROPEN is true, the arbitration portion  303  does not grant a right of use of bus, and maintains the idle state (step S 301 ). After that, if the user closes the cover  30  of the container portion  31  for the memory card  7 , the signal COVEROPEN becomes false at time F shown in  FIG. 18 . In this instance, since the signal EXDMAREQ is true and the signal CARDREQ is false, the state of the arbitration portion  303  proceeds to step S 302 . In addition, the arbitration portion  303  makes the signal EXDMAGRNT true at time G shown in  FIG. 18 , and grants a right of use of bus to the external DMA controller  301 . Accordingly, the external DMA controller  301  performs data transfer with the communication control IC  304 . After that, the external DMA controller  301  makes the signal EXDMAREQ false, so that the state of the arbitration portion  303  returns to the idle state (step S 301 ).  
         [0128]     Processing associated with the open and closed states of the cover  30  in the digital camera according to the fourth embodiment is described below with reference to  FIG. 19 .  
         [0129]     Referring to the flow chart of  FIG. 19  according to the fourth embodiment, at step S 331 , the CPU  3  first checks to determine if the cover  30  is open, on the basis of a detection signal from the cover detection switch  18 . If the cover  30  is open, the CPU  3  proceeds to step S 332 . At step S 332 , the CPU  3  causes a message indicative of the open state of the cover  30  to be displayed on the display  11 , and exits from this processing. If it is determined at step S 331  that the cover  30  is closed by the user, the CPU  3  proceeds to step S 341 . At step S 341 , the CPU  3  erases the message displayed on the display  11 , and exits from this processing.  
         [0130]     As described above, in the digital camera according to the fourth embodiment, data transfer with respect to the communication control IC  304  and data transfer with respect to the memory card  7  can be performed by using one data bus. Accordingly, even if noise is caused at the external bus  307  by insertion or extraction of the memory card  7 , any circuit does not access the external bus  307 . Therefore, no data error occurs in communication with the communication control IC  304 .  
         [0131]     Furthermore, since the CPU  3  does not suspend its operation during the time when the cover  30  is open, the digital camera can continue its processing operation during the time when the cover  30  is open. Accordingly, a more reliable digital camera that is less prone to failure can be provided.  
         [0132]     It should be noted that the fourth embodiment can also be implemented with image input apparatuses other than digital cameras (for example, digital video cameras, camera integrated mobile phones and camera integrated portable terminals).  
       Other Embodiments  
       [0133]     The present invention can also be achieved by providing a system or apparatus with a storage medium (or a recording medium) that stores a program code of software for realizing any one the functions of the above-described embodiments, and causing a computer (or a CPU, MPU or the like) of the system or apparatus to read the program code from the storage medium and then to execute the program code. In this case, the program code itself read from the storage medium realizes the novel functions of the embodiments, and a storage medium storing the program code constitutes the invention. Furthermore, besides the program code read by the computer being executed to realize the functions of the above-described embodiments, the present invention includes an OS (operating system) or the like running on the computer performing an actual process in whole or in part according to instructions of the program code to realize the functions of the above-described embodiments.  
         [0134]     Moreover, the present invention also includes a CPU or the like contained in a function expansion board inserted into the computer or in a function expansion unit connected to the computer, the function expansion board or the function expansion unit having a memory in which the program code read from the storage medium is written, the CPU or the like performing an actual process in whole or in part according to instructions of the program code to realize the functions of the above-described embodiments.  
         [0135]     The above-described embodiments are merely exemplary of the present invention, and are not to be construed to limit the scope of the present invention.  
         [0136]     The scope of the present invention is defined by the scope of the appended claims, and is not limited to only the specific descriptions in this specification. Furthermore, all modifications and changes belonging to equivalents of the claims are considered to fall within the scope of the present invention.