Abstract:
A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This patent application claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2007-0019753, filed Feb. 27, 2007, the contents of which are hereby incorporated by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present general inventive concept relates to semiconductor fabrication apparatuses and methods of forming a semiconductor device using the same, and more particularly, to semiconductor fabrication apparatuses to perform semiconductor etching and deposition processes and methods of forming the semiconductor device using the same. 
         [0004]    2. Description of the Related Art 
         [0005]    Typically, semiconductor devices are fabricated using a semiconductor substrate and a material layer. Here, the semiconductor devices may be configured to correspond to predetermined regions of the semiconductor substrate, respectively, thereby having electrical characteristics corresponding to the material layer. The material layer may be formed by performing a semiconductor deposition process on the semiconductor substrate. The predetermined region of the semiconductor substrate may be formed by performing a semiconductor photolithography process on the semiconductor substrate. After performing of the semiconductor photolithography and deposition processes, the semiconductor substrate may be exposed to a semiconductor etching process together with the material layer to form semiconductor devices. 
         [0006]    However, the semiconductor etching process may be performed to expose a main surface of the semiconductor substrate through a material layer, and form residues of the material layer in a bevel region of the semiconductor substrate. The residues of the material layer are different in number depending on characteristics of the semiconductor etching process and formed in the bevel region of the semiconductor substrate. The residues of the material layer may be transferred from the bevel region of the semiconductor substrate to the main surface of the semiconductor substrate to electrically short-circuit semiconductor devices through the semiconductor etching process or subsequent semiconductor fabrication processes after performing the semiconductor etching process. 
         [0007]    A method of preventing occurrence of residues of an insulating layer (corresponding to a material layer) in a bevel region of the semiconductor substrate is disclosed in Japanese Patent Laid-open Publication No. 2002-334879, filed by Fukata Shinichi et al. According to Japanese Patent Laid-open Publication No. 2002-334879, an insulating layer covering a peripheral region and a bevel region of a semiconductor substrate is formed. A passivation layer is formed in the bevel region of the semiconductor substrate to be disposed on the insulating layer. An interconnection groove is formed in the insulating layer by performing a semiconductor etching process on the insulating layer to expose the semiconductor substrate. The passivation layer protects the insulating layer in the bevel region of the semiconductor substrate during the etching process and prevents occurrence of the residues of the insulating layer in the bevel region of the semiconductor substrate. 
         [0008]    However, the method disclosed in Japanese Patent Laid open Publication No. 2002-334879 includes performing a semiconductor deposition process twice in different places of a semiconductor fabrication line not to make residues of the insulating layer in the bevel region of the semiconductor substrate. The two-time semiconductor deposition processes are performed using techniques of chemical vapor deposition (CVD) and organic material coating. Thus, the semiconductor substrate has to be moved to semiconductor fabrication apparatuses disposed in different places to perform the semiconductor deposition process twice. Thus, the method according to Japanese Patent Laid-open Publication No. 2002-334879 may prolong a processing time for forming the interconnection groove relating to the residues of the insulating layer, thereby increasing production cost of the semiconductor device. 
       SUMMARY OF THE INVENTION 
       [0009]    The present general inventive concept provides a semiconductor fabrication apparatus to perform semiconductor etching and deposition processes at an edge of a semiconductor substrate by depositing the semiconductor substrate at a proper position. 
         [0010]    The present general inventive concept also provides a method of forming a semiconductor device using a semiconductor fabrication apparatus to perform semiconductor etching and deposition processes at an edge of a semiconductor substrate to shorten a moving line of the semiconductor fabrication process. 
         [0011]    The present general inventive concept also provides a semiconductor fabrication apparatus and method of forming a semiconductor device using the same, which is suitable to perform semiconductor etching and deposition processes at an edge of a semiconductor substrate. 
         [0012]    Additional aspects and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept. 
         [0013]    The foregoing and/or other aspects and utilities of the general inventive concept may be achieved by providing a semiconductor fabrication apparatus including a lower body to perform semiconductor etching and deposition processes. The lower body has lower and middle electrodes. The lower electrode is formed to have a larger diameter than a diameter of the middle electrode concentrically aligned to the lower electrode. An upper body is disposed on the lower body. The upper body has an upper electrode and a gas induction housing. The upper electrode is formed to have a larger diameter than a diameter of the gas induction housing concentrically aligned to the upper electrode. The upper, middle and lower electrodes are electrically connected to one another. The gas induction housing and the middle electrode project from the upper and lower electrodes to be disposed to face each other. Intensity of an electrical field between the upper, middle and lower electrodes gradually decreases toward an edge between the gas induction housing and the middle electrode from the edge between the upper electrode and the lower electrode. 
         [0014]    The foregoing and/or other aspects and utilities of the general inventive concept may also be achieved by providing a method of forming a semiconductor device, the method including using a semiconductor fabrication apparatus to perform semiconductor etching and deposition processes. The semiconductor fabrication apparatus has lower and upper bodies facing each other to sequentially dispose gas tubes, an upper electrode and a gas induction housing in the upper body, and to dispose middle and lower electrodes in the lower body from top to bottom. In addition, a semiconductor substrate is prepared to be inserted into the semiconductor fabrication apparatus. The semiconductor substrate is mounted on the middle electrode. Etching process gases are injected between the upper and lower electrodes. An etching power recipe is set to the upper, middle and lower electrodes to perform a semiconductor etching process on the semiconductor substrate. After performing the semiconductor etching process, the etching process gases are removed from between the upper and lower electrodes. Subsequently, deposition process gases are injected between the upper and lower electrodes. A deposition power recipe is set to the upper, middle and lower electrodes to perform a semiconductor deposition process on the semiconductor substrate. The etching and deposition process gases are converted into plasma corresponding thereto and the plasma is disposed along an edge of the semiconductor substrate during the semiconductor etching and deposition processes, according to the etching and deposition power recipes. 
         [0015]    The foregoing and/or other aspects and utilities of the general inventive concept may also be achieved by providing a method of a semiconductor fabrication apparatus, the method including providing a lower body having lower and middle electrodes having first and second diameters, respectively, providing an upper body disposed on the lower body, and having an upper electrode and a gas induction housing having third and fourth diameters, respectively, and electrically connecting the upper, middle, and lower electrodes such that intensity of an electrical field among the upper, middle, and lower electrodes gradually decreases toward an edge between the gas induction housing and the middle electrode from an edge between the upper electrode and the lower electrode. 
         [0016]    The foregoing and/or other aspects and utilities of the general inventive concept may also be achieved by providing a semiconductor fabrication apparatus including a plurality of electrodes electrically connected to each other to form electrical fields, a substrate receiving portion disposed on one of the electrodes to receive a semiconductor substrate, and gas tubes disposed on one or more of the electrodes to transfer etching and deposition process gases to be converted into plasma, wherein the plasma is formed along an edge of the semiconductor substrate corresponding to intensities of the electrical fields. 
         [0017]    The plurality of electrodes may be aligned with each other along a center line. 
         [0018]    The plurality of electrodes may have a diameter and at least one of the respective diameters may be larger than the other diameters. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    These and/or other aspects and utilities of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which: 
           [0020]      FIG. 1  is a schematic view illustrating a semiconductor fabrication apparatus according to an embodiment of the present general inventive concept. 
           [0021]      FIGS. 2 to 8  are schematic views illustrating a method of forming a semiconductor device using the semiconductor fabrication apparatus of  FIG. 1  according to an exemplary embodiment of the present general inventive concept, respectively. 
           [0022]      FIG. 9  is a graph illustrating characteristics of semiconductor etching and deposition processes of the semiconductor fabrication apparatus of  FIG. 1 . 
           [0023]      FIGS. 10 to 16  are schematic views illustrating a method of forming a semiconductor device using the semiconductor fabrication apparatus of  FIG. 1  according to another exemplary embodiment of the present general inventive concept, respectively. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0024]    Reference will now be made in detail to embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept by referring to the figures. 
         [0025]    Semiconductor fabrication apparatus to perform semiconductor etching and deposition processes of the present general inventive concept will now be described in detail with reference to the accompanying drawings. 
         [0026]      FIG. 1  is a schematic view illustrating a semiconductor fabrication apparatus according to an embodiment of the present general inventive concept. 
         [0027]    Referring to  FIG. 1 , the semiconductor fabrication apparatus  80  according to the present embodiment includes a lower body  74 . The lower body  74  has a lower electrode  65 , an insulating housing  55  and a middle electrode  45 . The middle electrode  45  has a same center as the lower electrode  65 . The lower electrode  65  may have a larger diameter than the middle electrode  45 . The insulating housing  55  is disposed between the lower electrode  65  and the middle electrode  45 . The insulating housing  55  may electrically isolate the lower electrode  65  and the middle electrode  45  from each other and have a cooling system to thermally stabilize the middle electrode  45 . The middle electrode  45 , the insulating housing  55  and the lower electrode  65  separately have top surfaces, which are disposed at different levels from one another, respectively. The middle electrode  45  may be formed to be surrounded by the insulating housing  55  which may be formed to be surrounded by the lower electrode  65 . 
         [0028]    An upper body  25  is disposed on the lower body  74 . The upper body  25  has first and second gas tubes  3  and  6 , an upper electrode  9  and a gas induction housing  13 . The gas induction housing  13  and the upper electrode  9  have the same center. The upper electrode  9  may have a larger diameter than the gas induction housing  13 . The center of the upper electrode  9  and the gas induction housing  13  may be disposed on the same line as the center of the middle electrode  45  and the lower electrode  65 . The gas induction housing  13  has a strip-shaped gas inducer  19  along a sidewall of the induction housing  13 . The gas induction housing  13  may have hole-shaped gas inducers (not illustrated) along the sidewall of the induction housing  13 . Turning over bottom and top surfaces of the upper body  25  (as illustrated in dotted lines), the gas induction housing  13  has gas holes  16  in its surface facing the middle electrode  45 . 
         [0029]    The gas induction housing  13  and the middle electrode  45  project from the upper electrode  9  and the lower electrode  65  to face each other. The middle electrode  45  has a different diameter from the gas induction housing  13 . To this end, the middle electrode  45  may have a smaller diameter than the gas induction housing  13 . The middle electrode  45  may have a larger diameter than the gas induction housing  13 . Alternatively, the middle electrode  45  may have a same diameter as the gas induction housing  13 . The first and second gas tubes  3  and  6  are disposed on an upper electrode. The first gas tube  3  is in communication with gas holes  16  through the upper electrode  9  and the gas induction housing  13 . When the gas induction housing  13  has a strip-shaped gas inducer  19 , the second gas tube  6  is in communication with the gas inducer  19  through the upper electrode  9  and the gas induction housing  13 . When the gas induction housing  13  has hole-shaped gas inducers, the second gas tube  6  may be in communication with the gas inducers through the upper electrode  9  and the gas induction housing  13 . 
         [0030]    Referring again to  FIG. 1 , the semiconductor fabrication apparatus  80  includes upper, middle and lower electrodes  9 ,  45  and  65 , and may perform etching and deposition processes. An etching power recipe is set to the upper, middle and lower electrodes  9 ,  45  and  65  to correspond to the semiconductor etching process. According to the semiconductor etching process, the upper, middle and lower electrodes  9 ,  45  and  65  may be electrically connected to one another. The upper and lower electrodes  9  and  65  have a same polarity in the etching power recipe. A portion of the etching power recipe may ground the upper and lower electrodes  9  and  65 , and apply radio frequency (RF) power  34  to the middle electrode  45 . The remaining etching power recipe may apply bias power  36  to the upper and lower electrodes  9  and  65  to generate a higher electrical potential than the middle electrode  45 . 
         [0031]    In order to correspond to the semiconductor deposition process, a deposition power recipe is set to the upper, middle and lower electrodes  9 ,  45  and  65 . The upper and lower electrodes  9  and  65  have the same polarity in the deposition power recipe. A portion of the deposition power recipe may ground the upper and lower electrodes  9  and  65 , and apply RF power  34  to the middle electrode  45 . The remaining deposition power recipe may apply bias power  36  to the upper and lower electrodes  9  and  65  to generate a higher electrical potential than the middle electrode  45 . The semiconductor deposition process may have different RF power  34  or bias power  36  than the semiconductor etching process. On the other hand, a different deposition power recipe may be set to the upper, middle and lower electrodes  9 ,  45  and  65  to correspond to the semiconductor deposition process. The upper and lower electrodes  9  and  65  may have the same polarity in the different deposition power recipe. The different deposition power recipe may ground the upper and lower electrodes  9  and  65 , and apply the RF power  34  to the lower electrode  45 . Intensities of an electrical field between the upper, middle and lower electrodes  9 ,  45  and  65  are gradually reduced toward an edge between the gas induction housing  13  and the middle electrode  45  from an edge between the upper and lower electrodes  9  and  65 . 
         [0032]    Next, methods of forming a semiconductor device using semiconductor fabrication apparatus to perform semiconductor etching and deposition processes of the present general inventive concept will be described with reference to the drawings. 
         [0033]      FIGS. 2 to 4  schematically illustrate a method of forming a semiconductor device according to an exemplary embodiment of the present general inventive concept. 
         [0034]    Referring to  FIGS. 2 and 4 , according to an exemplary embodiment of the present general inventive concept, a semiconductor substrate  93  is prepared as illustrated in  FIG. 2 . The semiconductor substrate  93  has main surfaces on upper and bottom sides thereof, and a bevel region  91  connecting the main surfaces at an edge thereof. The main surfaces refer to a top surface  90  and a bottom surface  92  respectively corresponding to the upper side and the lower side of the semiconductor substrate  93 . The semiconductor substrate  93  has a semiconductor chip formation region  98  on the top surface thereof as illustrated in  FIG. 4 . The semiconductor chip formation region  98  may be formed in plural along rows and columns of the semiconductor substrate  93 . The semiconductor chip formation region  98  may correspond to a semiconductor chip through semiconductor pre- and post-processes, which are well known to those skilled in the art. 
         [0035]    A material layer  94  is formed on the semiconductor substrate  93  as illustrated in  FIG. 3 . The material layer  94  may be formed to cover the top surface  90 , the bevel region  91  and the bottom surface  92  of the semiconductor substrate  93 . The material layer  94  may be formed to fully cover the top surface  90  and the bevel region  91  of the semiconductor substrate  93 , and partially cover the bottom surface  92  thereof. The material layer  94  may be formed of an insulating and/or conductive material. A mask pattern  96  is formed on the material layer  94  as illustrated in  FIG. 3 . The mask pattern  96  may be formed to expose the material layer  94  disposed around an edge of the semiconductor substrate  93 . The mask pattern  96  may be formed using a photoresist. The mask pattern  96  may be formed of a material having a different etch rate from the semiconductor substrate  93  and the material layer  94 . 
         [0036]    Upon checking relative positions of the material layer  94 , the mask pattern  96  and the semiconductor chip formation region  98  through a check point “A” of  FIG. 3 , the top surface  90 , bevel region  91  and bottom surface  92  of the semiconductor substrate  93  are covered with the material layer  94  as illustrated in  FIG. 4 . The material layer  94  also covers the semiconductor chip formation region  98  disposed on the top surface  90  of the semiconductor substrate  93 . The semiconductor chip formation region  98  may be spaced a predetermined distance apart from an edge exclusion region on wafer (EEW) L 1  that is well known to those skilled in the art as illustrated in  FIG. 4 . Here, the mask pattern  96  may be formed to extend from a central region to the EEW L 1  of the semiconductor substrate  93  as illustrated in  FIG. 4 . The mask pattern  96  may be formed between the bevel region  91  and the semiconductor chip formation region  98 . 
         [0037]      FIGS. 5 to 8  are schematic views illustrating a method of forming a semiconductor device using the semiconductor fabrication apparatus of  FIG. 1  according to an exemplary embodiment of the present general inventive concept, respectively. 
         [0038]    Referring to  FIGS. 1 and 5 , a semiconductor substrate  93  according to an exemplary embodiment is inserted into the semiconductor fabrication apparatus  80  of  FIG. 1 . The semiconductor fabrication apparatus  80  has upper and lower bodies  25  and  74  opposite to each other. Toward a lower side from an upper side of the semiconductor fabrication apparatus  80 , the upper body  25  includes first and second gas tubes  3  and  6 , an upper electrode  9  and a gas induction housing  13 , and the lower body  74  includes middle and lower electrodes  45  and  65 . The lower electrode  65  has a larger diameter than the middle electrode  45 . The upper electrode  9  has a larger diameter than the gas induction housing  13 . The gas induction housing  13  has a different diameter from the middle electrode  45 . The gas induction housing  13  may be the same as the middle electrode  45 . Here, the semiconductor substrate  93  may be mounted on the middle electrode  45 . The semiconductor substrate  93  may be disposed on the middle electrode  45  to be out of an edge of the middle electrode  45  in all directions extending from the center of the middle electrode  45 . The semiconductor fabrication apparatus  80  may perform semiconductor etching and deposition processes on the semiconductor substrate  93  using the upper and lower bodies  25  and  74 . 
         [0039]    Meanwhile, the first and second gas tubes  3  and  6  may be disposed on a top surface of the upper electrode  9 , and the gas induction housing  13  may be disposed on the bottom surface of the upper electrode  9  as illustrated in  FIG. 1  or  5 . The gas induction housing  13  has a strip-shaped gas inducer  19  along a sidewall of the induction housing  13 , and gas holes  16  in a surface thereof facing the middle electrode  45  as illustrated in  FIG. 1 . The first gas tube  3  is in communication with the gas holes  16  through the upper electrode  9  and the gas induction housing  13 , and the second gas tube  6  is in communication with the gas inducer  19  through the upper electrode  9  and the gas induction housing  13 . Alternatively, the gas induction housing  13  may have hole-shaped gas inducers (not illustrated) along the sidewall of the induction housing  13 , and gas holes  16  in the respective surface facing the middle electrode  45 . The first gas tube  3  may be connected to the gas holes  16  through the upper electrode  9  and the gas induction housing  13 , and the second gas tube  6  may be in communication with the hole-shaped gas inducers through the upper electrode  9  and the gas induction housing  13 . 
         [0040]    To perform the semiconductor etching process, etching process gases G 1  and G 2  are injected into the semiconductor fabrication apparatus  80  through the first and second gas tubes  3  and  6  as illustrated in  FIG. 5 . One etching process gas G 1  is released between the upper and lower electrodes  9  and  65  through the gas holes  16  as illustrated in  FIG. 5 . The one etching process gas G 1  may be a reactive gas. The other etching process gas G 2  is released between the upper and lower electrodes  9  and  65  through the second gas tube  6  and the gas inducer  19  of the gas induction housing  13 . The other etching process gas G 2  may be a carrier gas or an additive gas. When the gas induction housing  13  has hole-shaped gas inducers, the one etching process gas G 1  may be released between the upper and lower electrodes  9  and  65  through the gas holes  16  of the gas induction housing  13 . The other etching process gas G 2  may be released between the upper and lower electrodes  9  and  65  through the second gas tube  6  and the gas inducers of the gas induction housing  13 . 
         [0041]    Referring to  FIGS. 5 and 6 , an etch power recipe is set to the upper, middle and lower electrodes  9 ,  45  and  65 . In the etch power recipe, the upper and lower electrodes  9  and  65  may be electrically connected to each other to have the same polarity. A portion of the etch power recipe may ground the upper and lower electrodes  9  and  65 , and apply RF power  34  to the middle electrode  45 . The RF power  34  may form a plasma  104  between the upper, middle and lower electrodes  9 ,  45  and  65  using the etch process gases G 1  and G 2  as illustrated in  FIG. 5 . The plasma  104  may be formed around the edge of the semiconductor substrate  93 . That is, the plasma  104  may be formed adjacent to the edge of the semiconductor substrate  93 . The plasma  104  may have a volume gradually decreasing toward an edge between the gas induction housing  13  and the middle electrode  45  from an edge between the upper and lower electrodes  9  and  65 . 
         [0042]    The remaining etch power recipe may apply bias power  36  to the upper and lower electrodes  9  and  65  to form a higher electrical potential than the middle electrode  45  as illustrated in  FIG. 5 . The bias power  36  may generate electrical fields F 1  and F 2  between the upper and middle electrodes  9  and  45 , so as to allow the plasma  104  to face toward the semiconductor substrate  93  corresponding to intensities of the electrical fields F 1  and F 2  during the semiconductor etching process. Accordingly, the semiconductor etching process may be performed to etch a material layer  94  using a mask pattern  96  as an etch mask. After the performance of the semiconductor etching process, the mask pattern  96  may continuously remain on the material layer  94  to expose the semiconductor substrate  93  as illustrated in  FIG. 6 . 
         [0043]    Referring to  FIGS. 5 and 7 , when the edge of the semiconductor substrate  93  is enlarged through a check point “A” of  FIG. 6 , residues  113 ,  116  and  119  of the material layer  94  may be viewed in an EEW L 1  of the semiconductor substrate  93  by the semiconductor etching process as illustrated in  FIG. 6 . The residues  113 ,  116  and  119  of the material layer  94  may be formed on the top and bottom surfaces of the semiconductor substrate  93  in addition to the EEW L 1  of the semiconductor substrate  93 . After the performance of the semiconductor etching process, the etching process gases G 1  and G 2  are removed from a space between the upper and lower electrodes  9  and  65 . The etching process gases G 1  and G 2  may be vented out of the apparatus  80  via a ventilation pump of the semiconductor fabrication apparatus  80  which is well know to those skilled in the art. Subsequently, to perform the semiconductor deposition process, deposition process gases G 3  and G 4  are injected into a space between the upper and lower electrodes  9  and  65  as illustrated in  FIG. 5 . The deposition process gases G 3  and G 4  may be applied to the semiconductor fabrication apparatus  80  through the first and second gas tubes  3  and  6 . One deposition process gas G 3  is released between the upper and lower electrodes  9  and  65  through gas holes  16  of the gas induction housing  13  as illustrated in  FIG. 5 . The one deposition process gas G 3  may be a reactive gas. The one deposition process gas G 3  may be formed of at least one element, which is different from or the same as that of the one etching process gas G 1 . 
         [0044]    The other deposition process gas G 4  is released between the upper and lower electrodes  9  and  65  through the second gas tube  6  and the gas inducer  19  of the gas induction housing  13  as illustrated in  FIG. 5 . The other deposition process gas G 4  may be a carrier gas or an additive gas. The other deposition process gas G 4  may be formed of at least one element different from that of the etching process gas G 2 . The other deposition process gas G 4  may be formed of at least one element which is the same as that of the other etching process gas G 2 . In contrast, the other deposition process gas G 4  may not be injected between the upper and lower electrodes  9  and  65 . When the gas induction housing  13  has hole-shaped gas inducers, the one deposition process gas G 3  may be released between the upper and lower electrodes  9  and  65  through the first gas tube  3  and the gas holes  16  of the gas induction housing  13 . The other deposition process gas G 4  may be released between the upper and lower electrodes  9  and  65  through the second gas tube  6  and the gas inducers of the gas induction housing  13 . 
         [0045]    Referring back to  FIGS. 5 and 7 , a deposition power recipe is set to the upper, middle and lower electrodes  9 ,  45  and  65 . In the deposition power recipe, the upper and lower electrodes  9  and  65  may be electrically connected to each other to have the same polarity. A portion of the deposition power recipe may ground the upper and lower electrodes  9  and  65 , and apply RF power  34  to the middle electrode  45 . Here, the RF power  34  may form plasma  108  between the upper, middle and lower electrodes  9 ,  45  and  65  as illustrated in  FIG. 5 . The plasma  108  may be formed along an edge of the semiconductor substrate  93 . That is, the plasma  108  may be formed adjacent to the edge of the semiconductor substrate  93 . The plasma  108  may have a volume gradually decreasing toward the edge between the gas induction housing  13  and the middle electrode  45  from the edge between the upper and lower electrode  9  and  65 . The RF power  34  of the semiconductor deposition process may be the same as that of the semiconductor etching process. The RF power  34  of the semiconductor deposition process may be different than that of the semiconductor etching process. 
         [0046]    The remaining deposition power recipe may apply bias power  36  to the upper and lower electrodes  9  and  65  to form a higher electrical potential than the middle electrode  45  as illustrated in  FIG. 5 . The bias power  36  of the semiconductor deposition process may be different than that of the semiconductor etching process. The bias power  36  of the semiconductor deposition process may be the same as that of the semiconductor etching process. The bias power  36  may generate electrical fields F 3  and F 4  between the upper and middle electrodes  9  and  45  to form the plasma  108  toward the semiconductor substrate  93  corresponding to the intensities of the electrical fields F 3  and F 4  during the semiconductor etching process. Alternatively, a different deposition power recipe may be set to the upper, middle and lower electrodes  9 ,  45  and  65 . The upper and lower electrodes  9  and  65  may be electrically connected to have the same polarity in the different deposition power recipe. The different power recipe may ground the upper and lower electrodes  9  and  65 , and apply RF power  34  only to the middle electrode  45 . 
         [0047]    Referring to  FIGS. 5 ,  7  and  8 , during the performance of the semiconductor deposition process, a passivation layer  125  is formed on the semiconductor substrate  93  by the deposition power recipe or the different deposition power recipe using the mask pattern  96  as a mask. The passivation layer  125  may be formed along the edge of the semiconductor substrate  93  as illustrated in  FIG. 7 . After the performance of the semiconductor deposition process, the mask pattern  96  is removed from the semiconductor substrate  93  as illustrated in  FIG. 8 . The passivation layer  125  may be formed to fully cover the EEW L 1  and partially cover the top and bottom surfaces of the semiconductor substrate  93  as illustrated in  FIG. 8 . Accordingly, the passivation layer  125  may be formed in the EEW L 1  to cover the residues  113 ,  116  and  119  of the material layer  94 . 
         [0048]      FIG. 9  is a graph illustrating characteristics of semiconductor etching and deposition processes of a semiconductor fabrication apparatus of  FIG. 1 . 
         [0049]    Referring to  FIG. 9 , whether the semiconductor deposition process can be performed using the semiconductor fabrication apparatus for the semiconductor etching process can be confirmed with reference to the graph of  FIG. 9 . The graph is illustrated in “Industrial Plasma Engineering Vol. 2. J. Reece Roth. IOP. p 583-p 584.” The graph illustrates a relationship between the semiconductor etching and deposition processes of the semiconductor fabrication apparatus according to a ratio of etching process gases and a magnitude of bias power. The etching process gases include a CF series gas as a reactive gas, and H 2  and O 2  gases as additive gases. The bias power is an electrical potential applied to the semiconductor substrate, and the electrical potential is represented as a relative ratio between the upper electrode (anode) and the lower electrode (cathode). Here, the semiconductor fabrication apparatus may exhibit semiconductor etching and deposition characteristics depending on a ratio of the etching process gases and a magnitude of the bias power. Thus, the semiconductor fabrication apparatus may perform the semiconductor deposition process using different etching process gases illustrated in the graph as a deposition process gas together with the semiconductor etching process. Accordingly, the present embodiment provides semiconductor fabrication apparatus  80  to perform the semiconductor etching and deposition processes based on the graph of  FIG. 9 . 
         [0050]      FIGS. 10 to 16  are schematic views illustrating a method of forming a semiconductor device using the semiconductor fabrication apparatus of  FIG. 1  according to another exemplary embodiment of the present general inventive concept, respectively. 
         [0051]      FIGS. 10 to 12  are schematic views illustrating a method of forming a semiconductor device according to another exemplary embodiment of the present general inventive concept. 
         [0052]    Referring to  FIGS. 10 and 12 , according to another exemplary embodiment of the present general inventive concept, a semiconductor substrate  93  is prepared as illustrated in  FIG. 10 . The semiconductor substrate  93  has main surfaces on upper and lower sides thereof, and a bevel region  91  connecting the main surfaces at its edge. The main surfaces refer to a top surface  90  and a bottom surface  92  respectively corresponding to the upper and lower sides of the semiconductor substrate  93 . The semiconductor substrate  93  has a semiconductor chip formation region  98  as illustrated in  FIG. 12 . The semiconductor chip formation region  98  may be formed plural along rows and columns of the semiconductor substrate  93 . The semiconductor chip region  98  may correspond to a semiconductor chip through semiconductor pre- or post-processes well known to those skilled in the art. 
         [0053]    A material layer  94  is formed on the semiconductor substrate  93  as illustrated in  FIG. 11 . The material layer  94  may be formed to cover the top surface  90 , the bevel region  91  and the bottom surface  92 . The material layer  94  may be formed to fully cover the top surface  90  and the bevel region  91  of the semiconductor substrate  93 , and partially cover the bottom surface  92  thereof. The material layer  94  may be formed of an insulating and/or conductive material. When a check point “B” of  FIG. 11  is enlarged, the material layer  94  may be viewed to cover the top surface  90 , bevel region  91  and bottom surface  92  of the semiconductor substrate  93  as illustrated in  FIG. 12 . The material layer  94  may cover the semiconductor chip formation region  98 . The semiconductor chip formation region  98  may be spaced by a predetermined distance apart from an EEW L 1  well known to those skilled in the art as illustrated in  FIG. 12 . 
         [0054]      FIGS. 13 to 16  are schematic views illustrating a method of forming a semiconductor device using the semiconductor fabrication apparatus of  FIG. 1  according to another exemplary embodiment of the present general inventive concept. 
         [0055]    Referring to  FIGS. 1 and 13 , a semiconductor substrate  93  is put into the semiconductor fabrication apparatus  80  of  FIG. 1 . The semiconductor fabrication apparatus  80  includes lower and upper bodies  74  and  25 . Toward a lower side from an upper side of the semiconductor fabrication apparatus  80 , the upper body  25  has first and second gas tubes  3  and  6 , an upper electrode  9  and a gas induction housing  13 , and the lower body  74  has middle and lower electrodes  45  and  65 . The lower electrode  65  has a larger diameter than the middle electrode  45 . The upper electrode  9  has a larger diameter than the gas induction housing  13 . The gas induction housing  13  has a different diameter than the middle electrode  45 . The gas induction housing  13  may have the same diameter as the middle electrode  45 . Here, the semiconductor substrate  93  may be mounted on the middle electrode  45 . The semiconductor substrate  93  may be disposed on the middle electrode  45  to be out of an edge of the middle electrode  45  extending in all directions from the center of the middle electrode  45 . The semiconductor fabrication apparatus  80  may perform semiconductor etching and deposition processes on the semiconductor substrate  93  using the upper and lower bodies  25  and  74 . 
         [0056]    Meanwhile, the first and second gas tubes  3  and  6  may be disposed on a top surface of the upper electrode  9 , and the gas induction housing  13  may be disposed on a bottom surface of the upper electrode  9  as in  FIG. 1  or  13 . The gas induction housing  13  has a strip-shaped gas inducer  19  along a sidewall of the induction housing  13  and gas holes  16  in a surface thereof facing the middle electrode  45 . The first gas tube  3  is in communication with the gas holes  16  through the upper electrode  9  and the gas induction housing  13 , and the second gas tube  6  is in communication with the gas inducer  19  through the upper electrode  9  and the gas induction housing  13 . Alternatively, the gas induction housing  13  may have hole-shaped gas inducers (not illustrated) along the sidewall of the induction housing  13 , and gas holes  16  in the surface facing the middle electrode  45 . The first gas tube  3  may be in communication with the gas holes  16  through the upper electrode  9  and the gas induction housing  13 , and the second gas tube  6  may be in communication with the hole-shaped gas inducers through the upper electrode  9  and the gas induction housing  13 . 
         [0057]    In order to perform the semiconductor etching process, etching process gases G 5  and G 6  are inserted into the semiconductor fabrication apparatus  80  through the first and second gas tubes  3  and  6  in  FIG. 13 . The one etching process gas G 5  is released between the upper and lower electrodes  9  and  65  through the first gas tube  3  and the gas holes  16  of the gas induction housing  13  as illustrated in  FIG. 13 . The one etching process gas G 5  may be a reactive gas. The other etching process gas G 6  is released between the upper and lower electrode  9  and  65  through the second gas tube  6  and the gas inducer  19  of the gas induction housing  13  in  FIG. 13 . The other gas etching process gas G 6  may be a carrier gas or an additive gas. When the gas induction housing  13  has hole-shaped gas inducers, the one etching process gas G 5  may be released between the upper and lower electrodes  9  and  65  through the first gas tube  3  and the gas holes  16  of the gas induction housing  13 . The other etching process gas G 6  may be released between the upper and lower electrodes  9  and  65  through the second gas tube  6  and the gas inducers of the gas induction housing  13 . 
         [0058]    Referring to  FIGS. 13 and 14 , an etching power recipe is set to upper, middle and lower electrodes  9 ,  45  and  65 . In the etching power recipe, the upper and lower electrodes  9  and  65  may be electrically connected to each other to have the same polarity. A portion of the etching power recipe may ground the upper and lower electrodes  9  and  65 , and apply RF power  34  to the middle electrode  45 . Here, the RF power  34  may form plasma  134  between the upper, middle and lower electrodes  9 ,  45  and  65  using the etching process gases G 5  and G 6 . The plasma  134  may be formed along the edge of the semiconductor substrate  93 . That is, the plasma  134  may be formed adjacent to the edge of the semiconductor substrate  93 . The plasma  134  may have a volume gradually decreasing toward an edge between the gas induction housing  13  and the middle electrode  45  from an edge between the upper and lower electrodes  9  and  65 . 
         [0059]    The remaining etching power recipe may apply a bias power  36  to the upper and lower electrodes  9  and  65  to generate a higher electrical potential than the middle electrode  45  as illustrated in  FIG. 13 . The bias power  36  may generate electrical fields F 5  and F 6  between the upper and middle electrodes  9  and  45  to form the plasma  134  toward the semiconductor substrate  93  corresponding to intensities of the electrical fields F 5  and F 6  in the semiconductor etching process. Accordingly, the semiconductor etching process may be performed to etch the material layer  94  existing within a range of forming the plasma  134  of the etching process gases G 5  and G 6  by the etching power recipe. The material layer  94  may be formed to expose the edge of the semiconductor substrate  93  as illustrated in  FIG. 14 . 
         [0060]    Referring to  FIGS. 13 and 15 , when the edge of the semiconductor substrate  93  is enlarged through the check point “B” of  FIG. 14 , residues  143 ,  146  and  149  of the material layer  94  may be viewed in an EEW L 1  of the semiconductor substrate  93  as illustrated in  FIG. 15 . The residues  143 ,  146  and  149  of the material layer may be formed on the top and bottom surfaces of the semiconductor substrate  93  including the EEW L 1  of the semiconductor substrate  93  by the semiconductor etching process. After the performance of the semiconductor etching process, the etching process gases G 5  and G 6  are removed from a space between the upper and lower electrodes  9  and  65 . The etching process gases G 5  and G 6  may be vented out of the semiconductor fabrication apparatus  80  through a ventilation pump of the apparatus  80  well known to those skilled in the art. Subsequently, in order to perform the semiconductor deposition process, deposition process gases G 7  and G 8  are injected between the upper and lower electrodes  9  and  65  in  FIG. 13 . The deposition process gases G 7  and G 8  may be injected into the semiconductor fabrication apparatus  80  through the first and second gas tubes  3  and  6 . The one deposition process gas G 7  is released between the upper and lower electrodes  9  and  65  through the first gas tube  3  and the gas holes  16  of the gas induction housing  13  as illustrated in  FIG. 13 . The one deposition process gas G 7  may be a reactive gas. The one deposition process gas G 7  may be formed of at least one element different from or the same as the one etching process gas G 5 . 
         [0061]    The other deposition process gas G 8  is released between the upper and lower electrodes  9  and  65  through the second gas tube  6  and the gas inducer  19  of the gas induction housing  13  as illustrated in  FIG. 13 . The other deposition process gas G 8  may be a carrier gas or an additive gas. The other deposition process gas G 8  may be formed of at least one element that is different from or the same as the other etching process gas G 6 . Alternatively, the other deposition process gas G 8  may not be injected between the upper and lower electrodes  9  and  65 . When the gas induction housing  13  has hole-shaped gas inducers, the one deposition process gas G 7  may be released between the upper and lower electrodes  9  and  65  through the first gas tube  3  and the gas holes  16  of the gas induction housing  13 . The other deposition process gas G 8  may be released between the upper and lower electrodes  9  and  65  through the second gas tube  6  and the hole-shaped gas inducers of the gas induction housing  13 . 
         [0062]    Referring back to  FIGS. 13 and 15 , a deposition power recipe is set to the upper, middle and lower electrodes  9 ,  45  and  65 . In the deposition power recipe, the upper and lower electrodes  9  and  65  may be electrically connected to each other to have the same polarity. A portion of the deposition power recipe may ground the upper and lower electrodes  9  and  65 , and apply the RF power  34  to the middle electrode  45 . Here, the RF power  34  may generate the plasma  138  between the upper, middle and lower electrodes  9 ,  45  and  65  as illustrated in  FIG. 13 . The plasma  138  may be generated along the edge of the semiconductor substrate  93 . That is, the plasma  138  may be formed adjacent to the edge of the semiconductor substrate  93 . The plasma  138  may have a volume gradually decreasing toward the edge between the gas induction housing  13  and the middle electrode  45  from the edge between the upper and lower electrodes  9  and  65 . The RF power  34  of the semiconductor deposition process may be different than that of the semiconductor etching process. The RF power  34  of the semiconductor deposition process may be the same as that of the semiconductor etching process. 
         [0063]    The remaining deposition power recipe may apply the bias power  36  to the upper and lower electrodes  9  and  65  to have a higher electrical potential than the middle electrode  45  as illustrated in  FIG. 13 . The bias power  36  of the semiconductor deposition process may be different than that of the semiconductor etching process. The bias power  36  of the semiconductor deposition process may be the same as that of the semiconductor etching process. The bias power  36  may generate electrical fields F 7  and F 8  between the upper and middle electrodes  9  and  45  to form the plasma  138  toward the semiconductor substrate  93  corresponding to the intensity of the electrical fields F 7  and F 8  during the semiconductor etching process. Alternatively, another deposition power recipe may be set to the upper, middle and lower electrodes  9 ,  45  and  65 . The upper and lower electrodes  9  and  65  may be electrically connected to each other to have the same polarity. The deposition power recipe may ground the upper and lower electrodes  9  and  65 , and apply the RF power  34  only to the middle electrode  45 . 
         [0064]    Referring to  FIGS. 13 ,  15  and  16 , a passivation layer  155  may be formed on the semiconductor substrate  93  existing in a range of forming the plasma  138  of the deposition process gas using the deposition power recipe or the different deposition power recipe during the performance of the semiconductor deposition process. The passivation layer may be formed along the edge of the semiconductor substrate  93 . After the performance of the semiconductor deposition process, the passivation layer  155  may be formed to fully cover the EEW L 1 , and partially cover the top and bottom surfaces of the semiconductor substrate  93 . Accordingly, the passivation layer  155  may be formed in the EEW L 1  to cover the residues  143 ,  146  and  149  of the material layer  94 . 
         [0065]    As described above, various embodiments of semiconductor fabrication apparatus performing semiconductor etching and deposition processes and methods of forming a semiconductor device using the same are provided. Accordingly, during the performance of the semiconductor etching and deposition processes, a semiconductor substrate is disposed at a predetermined position to shorten a moving line of the semiconductor fabrication process resulting in a decrease in production cost of the semiconductor device. 
         [0066]    Although various embodiments of the present general inventive concept have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.