Abstract:
A light beam is cyclically deflected by a rotating light deflector to scan an object such as an information storage medium. The scanning beam is detected by a light sensor located outside of the scanning region for synchronizing primary scanning. A plurality of n clock signals C 1  through C n  are successively generated by the delay element from an image scanning clock signal and a reference clock signal having the same frequency as that of the image scanning clock signal. One of the clock signals C 1  through C n  is selected as the image scanning clock signal dependent on the output signal from the light sensor. Dependent on the tap-to-tap delay error of the delay element: ±α%, the maximum error of an image scanning position: 1/N pixel, and the period of the image scanning clock signal: T 0 , Δt 0  which meets a prescribed condition is selected as a tap-to-tap delay time of the delay element.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a method of generating image scanning clock signals in an optical scanning device. 
     There have been known optical scanning devices in which a light beam is cyclically deflected by a rotating light deflector such as a rotating polygonal mirror or a hologram grating disc for writing information on or reading recorded information from an object such as an information storage medium. 
     When the light beam such as a laser beam is deflected by the rotating light deflector into a scanning beam, the scanning beam is focused as a spot on the information storage medium, which may be an original document carrying information to be read out or a photoconductive photosensitive body on which information is to be written or recorded. While the information storage medium is being scanned with the scanning beam spot, the information is read from or written on the information storage medium by the scanning beam spot modulated by an image scanning clock signal at the rate of one pixel per clock pulse. 
     The scanning of the information storage medium with the scanning beam is referred to as &#34;primary scanning&#34;. While the information storage medium is subject to the primary scanning, it is fed in a direction normal to the direction of the primary scanning. This feeding movement of the information storage medium is referred to as &#34;secondary scanning&#34;. 
     As can readily be understood, positions where respective primary scanning cycles are started should be aligned with each other in the secondary scanning direction in order to write and read information properly. If such starting positions for the primary scanning were not aligned in the secondary scanning direction, then an image reconstructed from the read-out signals would be distorted in the readout mode, or an image signal error known as &#34;jitter&#34; would be produced in the write mode. 
     It has been general practice to align the primary scanning starting positions in the secondary scanning direction by positioning a light sensor outside of the primary scanning region, detecting the scanning beam prior to each of the primary scanning cycles, and synchronizing the primary scanning cycles. 
     One way of bringing the primary scanning cycles into synchronism is to use an image scanning clock signal. More specifically, the instant the scanning beam is detected by the light sensor, the pulses of the image scanning clock signal start being counted up to a preset number m, for example, and the primary scanning cycle is started from a position in which the pulse number m+1 is reached. The image scanning clock signal is continuously generated at all times. The output signal from the light sensor, which serves as a reference for synchronizing the primary scanning cycles, is subject to variations in signal interval due for example to different mechanicam accuracies of the rotating light deflector. Dependent on whether the light sensor output signal is generated when the clock signal is high or low, the time to start the primary scanning cycle can deviate at most one clock pulse from the detection of the scanning beam with the light sensor, resulting in a scanning error. 
     When the time to start the primary scanning cycle deviates at most one clock pulse from the detection of the scanning beam with the light sensor, the primary scanning starting position varies at most one pixel. There is a method capable of reducing the largest variation of the primary scanning starting position to a 1/N pixel (N is a natural number), and this method will hereinafter be referred to as a &#34;1/N method&#34;. 
     To carry out the &#34;1/N method&#34;, on which the present invention is based, a delay element is required, and it is theoretically assumed that the delay element has no delay error between its taps, or no tap-to-tap delay error. 
     If there were no delay error between the taps of the delay element, the value N could be as large as desired, and the variation of the primary scanning starting position would theoretically be reduced to as small an extent as desired. However, since there is always a tap-to-tap delay error in an actual delay element, the value of N is at most 3 in the presence of such a tap-to-tap delay error. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method of generating image scanning clock pulses in an optical scanning device, the method being based on the 1/N method and capable of effectively reducing any variation in primary scanning starting positions in view of a tap-to-tap delay error of a delay element. 
     According to the present invention, a delay element is used which has a tap-to-tap delay error α(%)≦33. The tap-to-tap delay error can experimentally be predetermined. 
     A light beam is cyclically deflected by a rotating light deflector to scan an object such as an information storage medium. The scanning beam is detected by a light sensor located outside of the scanning region for synchronizing primary scanning. 
     A plurality of n clock signals C 1  through C n  are successively generated by the delay element from an image scanning clock signal and a reference clock signal having the same frequency as that of the image scanning clock signal. One of the clock signals C 1  through C n  is selected as the image scanning clock signal dependent on the output signal from the light sensor. The phase difference between the clock signals C 1  through C n  is established as a tap-to-tap delay time Δt 0  of the delay element. Because of a tap-to-tap delay error, the actual phase difference Δt is not constant but varies. It is assumed that the period of the image scanning clock signal is expressed as T 0  and the maximum positional error of a primary scanning starting position is a 1/N pixel where N is a natural number. 
     In view of the presence of the error α, Δt 0  or successive phase delays of the clock signals C 1  through C n   at the time α=0, are of significance as designing values. According to the present invention, a most appropriate value for Δt 0  is selected dependent on α, T 0 , and 1/N as follows: 
     The value of Δt 0  which meets: ##EQU1## in the range of 5≦n≦2+(100/α), and ##EQU2## when ##EQU3## in the range of 5≦n≦2+(100/α), and ##EQU4## when ##EQU5## is selected as the tap-to-tap delay time of the delay element. 
     The above and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of illustrative example. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1(A) thorugh (E) are diagrams explanatory of a method according to the present invention; 
     FIGS. 2 through 5 are diagrams explanatory of the 1/N method serving as the basis for the present invention; and 
     FIG. 6 is a diagram explanatory of the method of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention is based on the 1/N method. Therefore, the 1/N method will first be described in detail with reference to FIGS. 2 through 5. 
     In the 1/N method, n clock signals C 1  through C n  with their phase differences delayed successively by Δt 0  are produced by a delay element from an image scanning clock signal and a reference clock signal of the same frequency as that of the image scanning clock signal, the phase difference between the clock signals C 1 , C n  being smaller than one period of the image scanning clock signal, and one of the clock signals C 1  through C n  is selected dependent on the output signal from a light sensor and used as the image scanning clock signal. The value Δt 0  is treated as a constant since it is assumed in the 1/N method that there is no tap-to-tap delay error in the delay element. 
     As shown in FIG. 2, a reference clock signal C 0  is generated by a reference clock generator 12, the reference clock signal C 0  having a period T 0  and a frequency 1/T 0  which is the same as that of an image scanning clock signal. 
     The reference clock signal C 0  is applied to a delay element 14 which then produces clock signals C 1  through C n  each having the period T 0 . 
     As illustrated in FIG. 3, the clock signals C 1  through C n  are successively delayed Δt 0  in phase. The phase difference S between the clock signals C 1 , C n  is therefore expressed as (n-1)Δt 0 , which must be smaller than one period of the image scanning clock signal, i.e., S=(n-1)Δt 0  &lt;T 0 . This requirement will be described later on. The clock signals C 1  through C n  are then applied to a latch circuit 15, as shown in FIG. 2. 
     When a light sensor 10 detects a scanning beam, it applies an output signal to the latch circuit 15, which is responsive to the leading edge of the applied signal for latching the clock signals C 1  through C n  and issuing output signals Q 1  through Q n  and Q 1  through Q n . 
     The output signals Q i  (i=1 through n), Qi (i=1 through n) are 1, 0, respectively, when the latched clock signals C i  (i=1 through n) are high, and are 0, 1, respectively, when the latched clock signals C i  (i=1 through n) are low. 
     The output signals Q i , Q i  (i=1 through n) from the latch circuit 15 are applied to a clock selector 16 which is also suppied with the clock signals C 1  through C n  from the delay element 14. Based on the applied signals C i , Q i , Q i  (i=1 through n), the clock selector 16 selects one of the clock signals C 1  through C n  according to a certain formula, and issues the selected clock signal as an image scanning clock signal CS. Clock pulses of the image scanning clock signals CS are counted by a counter 20. When a predetermined number of clock pulses are counted by the counter 20, a primary scanning cycle is started by a scanning beam. 
     One example in which n=6 will be described below. 
     It is assumed that the delay element 14 issues clock signals C 1  through C 6  as shown in FIG. 4. If the light sensor 10 generates an output signal A, then the clock signals C 1  through C 6  as latched by the leading edge of the output signal A are high, low, low, low, high, and high, respectively. Therefore, the output signals from the latch circuit 15 are as follows: Q 1  =1, Q 1  =0, Q 2  =0, Q 2  =1, Q 3  =0, Q 3  =1, Q 4  =0, Q 4  =1, Q 5  =1, Q 5  =0, Q 6  =1, Q 6  =0. 
     The clock selector 16 produces an output signal Q i  ·Q i+1  or Q i  ·Q i+1  from the signals Q i , Q i . The status of the signals when i=6 is shown in the following table: 
     
         ______________________________________i       Q.sub.i       --Q.sub.i                       Q.sub.i ·  --Q.sub.i+1______________________________________1       1             0     12       0             1     03       0             1     04       0             1     05       1             0     06       1             0     0______________________________________ 
    
     This table indicates that the value of Q i  ·Q i+1  is 1 only when i=1 and is 0 when i is of the other values. This means that the leading edge of the output signal A from the light sensor 10 is present within the time period Δt 0  after the clock signal C 1  goes high and before the clock signal C 2  goes high, as clearly be seen from FIG. 4. 
     The jth clock signal C i+j  counting from the value of i at which Q i  ·Q i+1  becomes 1 (i=1 in the example of FIG. 4) is selected as the image scanning clock signal CS. Selection of the value of J is a matter of design choice. In the example of FIG. 4, the value of J is selected as 3, and the clock signal C 4  is selected as the image scanning clock signal when the output signal A from the light sensor 10 is as illustrated. Therefore, one clock signal is selected dependent on the output signal from the light sensor 10. 
     The requirement S=(n-1)Δt 0  &lt;T 0 , i.e., the phase difference between the clock signals C 1 , C n  be smaller than one period of the image scanning clock signal, will be described. If this requirement were not met in the example of FIG. 4, e.g., if the last clock signal were C&#39; 6  instead of C 6 , then Q 6  =0, Q 6  =1, and hence Q 5  ·Q 6  =1. Therefore, Q i  ·Q i+1  would be 1 for both i=1 and i=5. Thus, the output signal A of the light sensor 10 and the clock signals C 1  through C 6  would not be uniquely interrelated, with a resulting error. 
     The requirement S=(n-1)Δt 0  &lt;T 0  is consequently to determine the time at which the output signal is to be issued from the light sensor uniquely in relation to the clock signals C 1  through C n . 
     When selecting the image scanning clock signal CS in the foregoing manner, the maximum variation in time from the detection of the scanning beam with the light sensor up to the starting of the primary scanning is Δt 0 , and since (n-1)Δt 0  &lt;T 0 , ##EQU6## Whereas the starting position for a primary scanning cycle could deviate at most one pixel if the 1/N method were not relied upon, the maximum variation can be reduced to a 1/N pixel or less according to the 1/N method. 
     The clock selector which, on the assumption of j=3, selects the third clock signal C i+3  from the value of i at which Q i  ·Q i+1  =1 can be implemented by a combination of AND gates and an OR gate as shown in FIG. 5. 
     The 1/N method has been outlined as described above. 
     It has been assumed in the above description that the successive phase difference Δt 0  between the n clock signals C 1  through C n  produced from the delay element 14 is constant. However, an actual delay element is subject to a tap-to-tap delay error α(%). Even if the tap-to-tap delay time is set to Δt 0 , therefore, the phase delay varies in the range of Δt=Δt 0  ±α·(Δt 0  /100) due to the tap-to-tap delay error when the n clock signals C 1  through C n  are produced. In the presence of the tap-to-tap delay error, the 1/N method is theoretically inaccurate and the upper limit for the value of N in the 1/N method is at most N=3 as described above. 
     If N≧3, the tap-to-tap delay error α becomes α≦33% from the formulas: ##EQU7## 
     According to the present invention, N≧3 since any positional variation in primary scanning starting positions are supposed to be smaller than a 1/3 pixel, and therefore a delay element in which the tap-to-tap deley error ±α(%) is α≦33 is employed. 
     A method according to the present invention will be described in detail. 
     Designated in FIG. 6 at C 1 , C 2 , . . . , C n  are clock signals produced from the delay element, A an output signal from the light sensor, and CS an image scanning clock signal, as with FIG. 3. The clock signals C 1  through C n  have the same frequency 1/T 0  as that of the image scanning clock signal CS. 
     The phase delays Δt between the clock signals C 1 , C 2 , . . . , C n  are not constant but vary within an error range due to a tap-to-tap delay error α. Denoted at S 0  at a phase difference between the clock signals C 1  and C n , and T 0  -S 0  is expressed as ΔT E , which can be T 0  -(n-1)Δt 0  if the error α is 0. 
     The third clock signal C i+3  counting from the value of i at which Q i  ·Q i+1  -1 is selected as the image scanning clock signal (Inasmuch as the leading edge of the output signal A is positioned between the positive-going edges of the clock signals C 2 , C 3  in FIG. 6, Q i  ·Q i+1  =1  for i=2, and hence 2+3=5. Therefore, the clock signal C 5  is selected as the image scanning clock signal). 
     It is assumed that the time difference between the leading edge of the output signal A and the image scanning clock signal CS is DT, the maximum and minimum values thereof being DTL and DTS, respectively, and T 0  /Δt 0  =K which is a delay time setting coefficient. 
     The above symbols are summarized as follows, with units indicated in parentheses: 
     T 0  (ns) . . . the period of the image scanning clock signal; 
     Δt (ns) . . . the delay time (successive phase delays of the clock signals); 
     ±α(%) . . . the tap-to-tap delay error of the delay element; 
     n . . . the number of the clock signals, 
     ΔT E  (ns) . . . the time between the clock signals C n , C 1  ; 
     S 0  . . . the phase difference between the clock signals C 1 , C 1 , ΔT E  =T 0  -S 0  ; 
     DT . . . the time between the leading edge of the output signal of the light sensor and the image scanning clock signal; 
     DTL . . . the maximum value of DT; 
     DTS . . . the minimum value of DT; 
     K=T 0  /Δt 0  . . . the delay time setting coefficient; 
     Δt 0  . . . the delay time when there is no error. 
     In order to uniquely determine the value of i at which Q i  ·Q i+1  =1, the condition of S 0  &lt;T 0  is required to be met, or stated otherwise, the condition of ΔT E  &gt;0  should be met. 
     In view of the tap-to-tap delay error ±α(%), the relationship 
     
         (1-α/100)Δt.sub.0 ≦Δt≦(1+α/100) Δt.sub.0 
    
     is established. 
     There are (n-1)Δt&#39;s between the clock signals C 1  and C n , and it is assumed that there are a Δt&#39;s which are Δt≧Δt 0  and bΔt&#39;s which are Δt≦Δt 0 , among these (n-1)Δt&#39;s, with a+b=n-1. Since S 0  =ΣΔt, 
     
         ΔT.sub.E =T.sub.0 -S.sub.0 =T.sub.0 -{(1+α/100)a+(1-α/100)b}Δt.sub.0        (1) 
    
     Since the variations in the primary scanning starting positions correspond to variations in DT, the line synchronizing accuracy E in optical scanning is expressed by: ##EQU8## Because ΔT E  must always be positive, 
     
         T.sub.0 &gt;{(1+α/100)a+(1-α/100)b}Δt.sub.0 (3) 
    
     from the equation (1). 
     As T 0  /Δt 0  =K, 
     
         K&gt;(1+α/100)a+(1-α/100)b 
    
     The value of the righthand side of the above inequality is at maximum when a=n-1 and b=0. In view of this, 
     
         K&gt;(n-1)(1+α/100)                                     (4) 
    
     Where the image scanning clock signal CS is selected as shown in FIG. 6, DTM (the maximum value of DTL-DTS) which gives the maximum value to E is given as follows: ##EQU9## The value of ΔDT is maximum when a=n-2, b=1. Therefore, ##EQU10## The value of ΔDT is maximum when a=2, b=n-3. ##EQU11## 
     Since T 0  /Δt 0  =K, the line synchronizing accuracy E and the delay time setting coefficient K are interrelated as follows, using the equations (2) and (8) through (12): ##EQU12## The equations (13) and (16) are the same as each other and the equations (14) and (17) are the same as each other. 
     In FIGS. 1(I) through (V), the curves 1--1, 1-1A, 1-1B, and 1-1C are represented by the equations (13), (16), the curves 1-2, 1-2A, 1-2B, 1-2C, and 1-2D by the equations (14), (17), and the curves 1-3, 1-3A, and 1-3B by the equation (15). 
     In view of the equation (4), the thicker portions of the curves in FIGS. 1(I) through 1(III) indicate the line synchronizing accuracies under the respective conditions. 
     In FIG. 1(I), the point P 10  represents K=n+(α/100), and the point P 12  represents K=(n-1){(1+(α/100)}. FIG. 1(I) shows the curve in the range of 
     
         5≦n&lt;2+100/α 
    
     for 0&lt;α≦33. The maximum value Emax of the line synchronizing accuracy at this time is: ##EQU13## 
     FIG. 1(II) shows the curve in the range of 2+(100/α)≦n. In FIG. 1(II), the point P 14  indicates K=(n-1){1+(α/100)} and the point P 16  indicates K=n+(α/100). At this time, Emax for 0&lt;α≦33 is expressed by: ##EQU14## when (n-1)(1+α/100)&lt;K. 
     FIG. 1(III) shows the curve 1-3B is present in the range 2≦n≦4. In FIG. 1(III), the point P 18  indicates K=n+{(6-n)α/100}, the point P 20  indicates K=n+{(4-n)α/100}, and the point P 22  indicates K=(n-1){1+(α/100)}. Since a≧3, b≧2 in the equation (15), the curve 1-3B is not present in the range of 2≦n≦4, and Emax at this time is given by the equation (18). 
     Now, the condition under which Emax≦(1/N)×100 for 5≦n&lt;2+(100/α) and 2+(100/α)≦n in FIGS. 1(I) and 1(II) will be determined below. When this condition is met, the positional error of the primary scanning starting position is 1/N of one pixel or less. 
     Reference will be made to FIGS. 1(IV) and 1(V) for determining the above condition. 
     FIG. 1(IV) shows the curve in the range of 5≦n&lt;2+(100/α). The points P 24 , P 26 , P 28 , and P 30  indicate ##EQU15## respectively, where E is Emax/100. 
     The condition which meets Emax≦(1/N)×100 in the equation (18) is: ##EQU16## 
     FIG. 1(V) shows the curve in the range of 2+(100/α)≦n. Providing E=Emax/100, the point P 32   indicates ##EQU17## and the point P 34  indicates K=(n-1){1+(α/100)}. 
     The condition which meets Emax≦(1/N)×100 in the equation (19) is: ##EQU18## 
     Since Δt 0  =T 0  /K, this relationship is used, and the expressions (20), (21), (22) are modified into the following expressions (23), (24), (25), respectively: ##EQU19## Therefore, Δt 0  which meets the expression (23) when 1/N and α meet ##EQU20## in the range of 5≦n&lt;2+(100/α), which meets the expression (24) when 
     
         2/(n-1)≦1/N 
    
     is met in the range of 5≦n&lt;2+(100/α), and which meets the expression (25) when 
     
         2α/α+100)≦1/N&lt;1 
    
     is met in the range of 2+(100/α)≦n, should be selected as a tap-to-tap delay time of the delay element. By aligning the primary scanning starting positions with the image scanning clock signal thus produced, any positionan error of the primary scanning starting positions can be reduced to a 1/N pixel or smaller. 
     EXAMPLE 
     An example of the present invention will be described below. A reference clock signal having an image scanning clock frequency of 5 MHz and a clock period of T 0  =200 ns was generated, and α=10%, n=10, and a maximum line synchronizing accuracy of 1/5 pixel or less were selected as design conditions. 
     Since n=10 and α=10, the relationship ##EQU21## is met, and hence from the relationship (24), the condition to be met by Δt 0  is: 
     
         19.76 (ns)&lt;Δt.sub.0 &lt;19.83 (ns)                      (26) 
    
     Since Emax is minimum when K=n+(α/100)=10.1 as is clear from FIG. 1(IV), 19.80 (ns) may be selected as Δt 0  (=T 0  /K). By selecting the actual tap-to-tap delay time Δt 0  of the delay element to be 19.80 (ns), any positional variation of the primary scanning starting positions could be 1/5 pixel or smaller. 
     With the method of the present invention, therefore, any error or positional variation of the primary scanning starting positions can be reduced effectively at all times regardless of the presence of a tap-to-tap delay error in a delay element, and therefore the optical scanning can be of increased accuracy. 
     Although a certain preferred embodiment has been shown and described, it should be understood that many changes and modifications may be made therein without departing from the scope of the appended claim.