Abstract:
Embodiments relate to apparatuses, systems and methods for testing high-frequency receivers. In an embodiment, a method includes integrating a pulse train generator and a receiver in an integrated circuit; generating a pulse train by the pulse train generator and applying the pulse train to an input of the receiver; measuring at least one property of the pulse train; and determining at least one characteristic of the receiver using the at least one property of the pulse train. In an embodiment, an integrated circuit includes a receiver, and a pulse train generator configured to generate a pulse train and apply the pulse train to an input of the receiver, wherein at least one characteristic of the receiver can be determined using at least one measured property of the pulse train.

Description:
TECHNICAL FIELD 
     The invention relates generally to receiver circuitry and more particularly to the testing of high-frequency receiver circuitry after production and in situ. 
     BACKGROUND 
     Conventionally, integrated millimeter-wave receivers, such as those used in automotive radar at 77 GHz, are tested either after production using expensive probe stations and measurement equipment or only indirectly via other measurements at low frequencies. The former is costly and time inefficient, while the latter provides only a general indication of circuit performance rather than an oft-desired thorough characterization. 
     While the integration of test signal sources on chip has been proposed, such a solution can be imperfect because the properties of the test signal vary with process variations and are not known exactly. Therefore, it can be difficult to obtain precise measurements, and a need for accurate and cost-effective testing remains. 
     SUMMARY OF THE INVENTION 
     Embodiments relate to apparatuses, systems and methods for testing high-frequency receivers. In an embodiment, a method comprises integrating a pulse train generator and a receiver in an integrated circuit; generating a pulse train by the pulse train generator and applying the pulse train to an input of the receiver; measuring at least one property of the pulse train; and determining at least one characteristic of the receiver using the at least one property of the pulse train. 
     In an embodiment, an integrated circuit comprises a receiver, and a pulse train generator configured to generate a pulse train and apply the pulse train to an input of the receiver, wherein at least one characteristic of the receiver can be determined using at least one measured property of the pulse train. 
     In an embodiment, a system comprises an integrated circuit comprising a receiver, and a pulse train generator comprising an inverter chain having a gate delay, wherein the pulse train generator is configured to generate a pulse train and apply the pulse train to an input of the receiver and an input of a low pass filter, wherein an average voltage of the pulse train is measurable at an output of the low pass filter; and a baseband processor couplable to an output of the receiver to receive an output signal from the receiver and configured to determine a characteristic of the receiver based on the output signal, the average voltage and the gate delay. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which: 
         FIG. 1  is a diagram of a pulse train according to an embodiment. 
         FIG. 2  is a block diagram of a circuit according to an embodiment. 
         FIG. 3  is a diagram of a pulse train according to an embodiment. 
         FIG. 4  is a pulse train spectrum graph according to an embodiment. 
         FIG. 5  is a pulse train spectrum graph according to an embodiment. 
         FIG. 6  is a block diagram of a test configuration according to an embodiment. 
         FIG. 7  is a block diagram of a circuit according to an embodiment. 
         FIG. 8  is a block diagram of a circuit according to an embodiment. 
         FIG. 9  is a block diagram of a test configuration according to an embodiment. 
     
    
    
     While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
     DETAILED DESCRIPTION 
     Embodiments relate to test signal generators and methods for testing high frequency receivers. The test signal generator circuit and the receiver to be tested can be integrated on the same integrated circuit. In an embodiment, the circuit is intended for testing receivers after production, such as in frontend and/or backend test, as well as in the application. A goal is to provide accurate testing of receiver performance at low cost and without the need for expensive test equipment. This is especially pertinent to receivers in the millimeter wave range (e.g., for automotive radar applications that operate at 77 GHz), for which conventional testing requires significant effort. While the examples herein will generally be discussed in the context of radar applications, such as automotive, operating at 77 GHz, other frequencies and/or applications can be used in various embodiments. 
     The invention addresses the problems related to testing integrated receivers by generating a well-defined test signal on chip. The test signal is generated by a pulse train generator integrated with the receiver in an integrated circuit in an embodiment. The test signal is applied to a receiver input, such as in production testing or in the receiver application in situ, and provides a characterization of receiver performance, such as gain, noise figure and frequency response, with improved accuracy in embodiments. In one embodiment, the test signal comprises a pulse train with low duty cycle that contains harmonics up to the millimeter wave range. 
       FIG. 1  depicts an example pulse train  100  with period τ and pulse duration T. To obtain precise measurements, it is desired to know the exact value of T. 
       FIG. 2  depicts an embodiment of a circuit  200  for generating pulse train  100 . A clock signal CLK is applied to a first input of an AND gate  202 . Clock signal CLK is also applied to an inverter chain  204  comprising three inverters  204   a ,  204   b ,  204   c . Each inverter  204   a - c  delays clock signal CLK by a small amount of time, corresponding to the gate delay of the respective inverter  204   a - c . The delayed clock signal CLK is then applied to the second input of AND gate  202  that generates the pulse train V pulse    206 , with the pulse duration T ( FIG. 1 ) of V pulse    206  determined by the overall gate delay of inverter chain  204 . 
     The gate delay is an important figure of merit in semiconductor technologies. Therefore, ring oscillators are usually part of the Process Control Monitoring (PCM) structures that are included on every manufactured wafer because ring oscillators include an inverter chain that allows the gate delay to be measured. PCM structures typically are placed at several different locations on each wafer. Ring oscillator gate delay measurements show only very little variation across the wafer, as is discussed, for example, in Boeck et al., 3.3  ps SiGe Bipolar Technology , IEEE (2004), which is incorporated herein by reference in its entirety. Therefore, the gate delay measured at these existing PCM structures provides accurate information about the pulse duration T of circuit  200 . 
     Referring to  FIG. 3 , when the pulse duration T and period t of signal  100  are known it is possible to obtain information about the pulse amplitude by measuring the average voltage V AVG  of the pulse train  100 . Average voltage V AVG  can be derived by low-pass filtering pulse train  100 . Once pulse duration T and average voltage V AVG  are known, the resulting amplitude of the test signal  100  is also known, thereby providing for precise receiver characterization. 
     The envelope of the spectrum of a pulse train corresponds to a sin(x)/x function, and the amplitude of the spectral lines reaches a first null at a frequency of 1/T. State-of-the-art semiconductor processes typically achieve gate delays below 4 picoseconds (ps). Therefore, referring to  FIG. 4 , it is possible to generate pulses of sufficiently short duration to have the first null  402  at frequencies of 100 GHz or greater. This means that spectral lines of sufficient amplitude are available in the automotive radar band at 77 GHz. The bottom portion of  FIG. 4  illustrates this point in a zoomed-in section of the spectrum around 77 GHz. 
     Alternatively, it is possible to use wider pulses, such that the operating frequency of the device under test lies between the first and second nulls  502 ,  504  as shown in  FIG. 5 . Although the first null  502  is below the desired operating frequency of 77 GHz, the spectrum remains sufficient in the range of 77 GHz, which can be seen in the bottom portion of  FIG. 5 . In fact, the spectrum is somewhat flat at 77 GHz and does not have significant variation, which is preferred in testing. 
       FIG. 6  depicts an example implementation of an embodiment. A test signal generator  602  is integrated together with the receiver depicted here as device under test  604  in an integrated circuit (IC)  605 . In an embodiment, test signal generator  602  is implemented as circuit  200  depicted in  FIG. 2 . A test signal is applied to the input of receiver (device under test)  604  and to a low-pass filter  606 . At the output of filter  606 , the average voltage of the pulse train can be measured by a voltmeter  608 . A baseband processing unit  610  is implemented in embodiments to characterize the output signal of device under test  604 . Gain and noise figures of device under test  604  can be determined accurately because the characteristics of the test signal originating from test signal generator  602  are known precisely from measurements of the average voltage V AVG  by voltmeter  608  and gate delay as described above. 
       FIG. 7  depicts an embodiment of a test signal generator  700  with a selectable number of inverter stages  702 . A multiplexer  704  is added to inverter chain  702 . Depending on the state of a select signal  706 , a different number of inverter stages, three or five in the embodiment depicted, is used. This allows for varying the pulse duration T and therefore the frequency characteristics of the test signal, similar to the embodiments of  FIGS. 4 and 5 . 
       FIGS. 8 and 9  depict an embodiment in which the value of the gate delay, and thereby the pulse duration T, is not derived from measurements of PCM structures but individually for each device under test. This leads to a further increase in measurement accuracy and allows for receiver testing even if no PCM data are available. 
       FIG. 8  shows how the gate delay of the inverter stages in pulse train generator  800  can be measured. Depending on the Select_RO signal  802 , the input of the first inverter stage  804   a  of inverter chain  804  is either connected to the clock signal CLK or to the output of the last inverter stage  804   b , via multiplexer  806 . When the output of the last stage  804   b  is used as input, inverter chain  804  functions as a ring oscillator. The output signal of the ring oscillator (inverter chain  804 ) is available at V_RO, and the gate delay can be determined by measuring the frequency of the signal at V_RO by a frequency counter  902  as depicted in  FIG. 9 . When multiplexer  806  applies clock signal CLK to the input of inverter chain  804 , circuit  800  operates as a pulse train generator similar to circuit  200  of  FIG. 2 . 
     Embodiments thereby provide efficient and less expensive test implementations for high frequency receivers, including automotive and other radar receivers operating at 77 GHz, by integrating a test signal generator with the receiver in an integrated circuit. Characteristics of the signal generated by the test signal generator can be well-defined, in part through the use of existing on-wafer structures. Accurate testing can thereby be accomplished at reduced cost and complexity when compared to conventional high frequency receiver testing. 
     Various embodiments of systems, devices and methods have been described herein. These embodiments are given only by way of example and are not intended to limit the scope of the invention. It should be appreciated, moreover, that the various features of the embodiments that have been described may be combined in various ways to produce numerous additional embodiments. Moreover, while various materials, dimensions, shapes, implantation locations, etc. have been described for use with disclosed embodiments, others besides those disclosed may be utilized without exceeding the scope of the invention. 
     Persons of ordinary skill in the relevant arts will recognize that the invention may comprise fewer features than illustrated in any individual embodiment described above. The embodiments described herein are not meant to be an exhaustive presentation of the ways in which the various features of the invention may be combined. Accordingly, the embodiments are not mutually exclusive combinations of features; rather, the invention may comprise a combination of different individual features selected from different individual embodiments, as understood by persons of ordinary skill in the art. 
     Any incorporation by reference of documents above is limited such that no subject matter is incorporated that is contrary to the explicit disclosure herein. Any incorporation by reference of documents above is further limited such that no claims included in the documents are incorporated by reference herein. Any incorporation by reference of documents above is yet further limited such that any definitions provided in the documents are not incorporated by reference herein unless expressly included herein. 
     For purposes of interpreting the claims for the present invention, it is expressly intended that the provisions of Section 112, sixth paragraph of 35 U.S.C. are not to be invoked unless the specific terms “means for” or “step for” are recited in a claim.