Abstract:
A serializer including a pull-up unit configured to pull up an output node, and a plurality of data select units configured to receive a plurality of input data signals. Each data select unit includes a pull-up device configured to pull up the output node in response to a corresponding input data signal, and a pull-down device configured to pull down the output node in response to the corresponding input data signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 USC §119 to Korean Patent Application No. 2006-15977, filed on Feb. 20, 2006 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    This disclosure relates to a semiconductor memory device, and more particularly to a serializer and a method of converting parallel data with a low frequency into serial data with a high frequency. 
         [0004]    2. Description of the Related Art 
         [0005]    Generally, a high-speed transfer mode converting low-speed parallel data into high-speed serial data is used in network systems in order to transfer data at high speeds. 
         [0006]    In a memory system, a parallel bus structure that has a wide bandwidth is typically used as a bus structure between a processor and a semiconductor memory in order to transfer a large amount of data. Since an operating speed of a semiconductor memory is lower than that of a processor, a processing speed of the entire memory system is also low. 
         [0007]    A bus system having a wider bandwidth is needed in order to increase a processing speed between a processor and a semiconductor memory while maintaining an operating speed of the semiconductor memory. As a bandwidth becomes wider, the number of input/output (I/O) pins of a semiconductor memory device is also increased, sometimes by as much as hundreds of pins. Thus, a cost of a semiconductor memory device may be increased. High numbers of I/O pins are needed for high speed, high capacity and high performance, and thus manufacturing costs may be increased. 
         [0008]    Therefore, in the field of semiconductor memory, active research on data serializing technologies that convert parallel data into serial data is being conducted in order to increase data transfer speeds between a memory and a processor. 
         [0009]    A data serializing device in a semiconductor memory device is manufactured by complementary metal-oxide semiconductor (CMOS) circuit design technologies. 
         [0010]    In a semiconductor memory device, a CMOS circuit technology is used in converting eight bits of parallel data having a differential form into ten bits of serial data. Ten branch circuits that respectively include one p-type MOS (PMOS) transistor as a pull-up device and one n-type MOS (NMOS) transistor as a pull-down device are coupled to an output node. When input data corresponds to a logic high, a voltage of the output node becomes a logic low rapidly through the branch circuits including NMOS transistors. However, when input data corresponds to a logic low, a voltage of the output node becomes a logic high relatively slowly because large parasitic capacitances generated from the ten branch circuits are charged by one small PMOS transistor. Imbalance between a rising transition time and a falling transition time at the output node causes a skew so that a data transfer speed may be decreased. 
         [0011]    For a semiconductor memory device, a method for diminishing parasitic capacitances includes reducing the number of pull-down devices connected to an output node by half to raise a pull-up speed. 
         [0012]    For a semiconductor memory device, another method of balancing between pull-up characteristics and pull-down characteristics at an output node equalizes the number of pull-up devices and pull-down devices. 
         [0013]      FIG. 1  is a circuit diagram illustrating a conventional serializer. 
         [0014]    Referring to  FIG. 1 , the serializer includes PMOS transistor MP 1  between a supply voltage VDD and an output node N 0 . A gate of the PMOS transistor MP 1  is provided with a bias voltage Vb. A voltage of the output node N 0  is pulled up by the bias voltage Vb through the PMOS transistor MP 1  with a predetermined current driving capability. 
         [0015]    Four pull-down circuits PDC 1 , PDC 2 , PDC 3  and PDC 4  are coupled in parallel between the output node N 0  and a ground voltage VSS. A first pull-down circuit PDC 1  includes serially coupled NMOS transistors MN 1 , MN 2  and MN 3 . A first clock signal CLK 1  is applied to a gate of the NMOS transistor MN 1 , a second clock signal CLK 2  is applied to a gate of the NMOS transistor MN 2 , and first input data IN 1  is applied to a gate of the NMOS transistor MN 3 . A second pull-down circuit PDC 2  includes serially coupled NMOS transistors MN 4 , MN 5  and MN 6 . The second clock signal CLK 2  is applied to a gate of the NMOS transistor MN 4 , a third clock signal CLK 3  is applied to a gate of the NMOS transistor MN 5 , and second input data IN 2  is applied to a gate of the NMOS transistor MN 6 . A third pull-down circuit PDC 3  includes serially coupled NMOS transistors MN 7 , MN 8  and MN 9 . The third clock signal CLK 3  is applied to a gate of the NMOS transistor MN 7 , a fourth clock signal CLK 4  is applied to a gate of the NMOS transistor MN 8 , and third input data IN 3  is applied to a gate of the NMOS transistor MN 9 . A fourth pull-down circuit PDC 4  includes serially coupled NMOS transistors MN 10 , MN 11  and MN 12 . The fourth clock signal CLK 4  is applied to a gate of the NMOS transistor MN 10 , the first clock signal CLK 1  is applied to a gate of the NMOS transistor MN 11 , and fourth input data IN 4  is applied to a gate of the NMOS transistor MN 12 . The NMOS transistors MN 1  through MN 12  are manufactured to have a higher current driving capability with respect to the PMOS transistor MP 1 . 
         [0016]      FIG. 2  is a timing diagram illustrating operations of the serializer in  FIG. 1 . 
         [0017]    Referring to  FIG. 2 , each of the four clock signals CLK 1 , CLK 2 , CLK 3  and CLK 4  have identical periods and are 90 degrees out of phase with each other. A phase of the second clock signal CLK 2  is delayed as much as 90 degrees with respect to that of the first clock signal CLK 1 , a phase of the third clock signal CLK 3  is delayed as much as 90 degrees with respect to that of the second clock signal CLK 2 , and a phase of the fourth clock signal CLK 4  is delayed as much as 90 degrees with respect to that of the third clock signal CLK 3 . The first input data IN 1  is synchronized with a rising edge of the first clock signal CLK 1 , the second input data IN 2  is synchronized with a rising edge of the second clock signal CLK 2 , the third input data IN 3  is synchronized with a rising edge of the third clock signal CLK 3 , and the fourth input data IN 4  is synchronized with a rising edge of the fourth clock signal CLK 4 . 
         [0018]    The first input data IN 1  is transferred to the output node N 0  while the first and second clock signals CLK 1  and CLK 2  are turned on, the second input data IN 2  is transferred to the output node N 0  while the second and third clock signals CLK 2  and CLK 3  are turned on, the third input data IN 3  is transferred to the output node N 0  while the third and fourth clock signals CLK 3  and CLK 4  are turned on, and the fourth input data IN 4  is transferred to the output node N 0  while the fourth and first clock signals CLK 4  and CLK 1  are turned on. 
         [0019]    Thus, when input data is a logic high, although the PMOS transistor MP 1  is turned on, one of the pull-down circuits PDC 1 , PDC 2 , PDC 3  and PDC 4  including the NMOS transistors, which have higher current driving capability with respect to the PMOS transistor MP 1 , is turned on so that the voltage of the output node N 0  is pulled down to the ground voltage VSS in synchronization with the clock signal. 
         [0020]    However, when input data is a logic low, although one of the pull-down circuits PDC 1 , PDC 2 , PDC 3  and PDC 4  is selected by the clock signal, the pull-down circuits PDC 1 , PDC 2 , PDC 3  and PDC 4  are turned off so that the voltage of the output node N 0  is pulled up only by the PMOS transistor MP 1  that is turned on. 
         [0021]    As a result, a rising transition time may be longer than a falling transition time at the output node N 0 . In addition, a falling edge is synchronized with the clock signal, but a rising edge is not synchronized with the clock signal. Imbalance between a rising transition time and a falling transition time of serialized data may cause data skew. 
       SUMMARY 
       [0022]    An embodiment includes a serializer including a pull-up unit configured to pull up an output node, and a plurality of data select units configured to receive a plurality of input data signals. Each data select unit includes a pull-up device configured to pull up the output node in response to a corresponding input data signal, and a pull-down device configured to pull down the output node in response to the corresponding input data signal. 
         [0023]    An embodiment includes a method of converting parallel data into serial data including for each bit of the parallel data: enabling a pull-up driver to pull up a first node for each such bit in response to a first state of the bit, and enabling a pull-down driver to pull down the first node in response to a second state of the bit. The method also includes sequentially coupling each first node for each bit to an output node in response to a plurality of clock signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIG. 1  is a circuit diagram illustrating a conventional serializer. 
           [0025]      FIG. 2  is a timing diagram illustrating operations of the serializer in  FIG. 1 . 
           [0026]      FIG. 3  is a circuit diagram illustrating an example of a serializer according to an embodiment. 
           [0027]      FIG. 4  is a timing diagram illustrating operations of the serializer in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    Embodiments will be described more fully with reference to the accompanying drawings. Embodiments may, however, take many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the following claims to those skilled in the art. Like reference numerals refer to like elements throughout this application. 
         [0029]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0030]    It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). 
         [0031]    The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0032]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0033]      FIG. 3  is a circuit diagram illustrating an example of a serializer according to an embodiment. The serializer includes a pull-up unit PU 0 , and data select units DS 1 , DS 2 , DS 3  and DS 4 . The pull-up unit PU 0  includes PMOS transistor MP 0  coupled between a first supply voltage VDD and an output node N 0 . A voltage of the output node N 0  can be pulled up to the first supply voltage VDD by the PMOS transistor MP 0  with a first current driving capability. 
         [0034]    The data select units DS 1 , DS 2 , DS 3  and DS 4  are commonly coupled to the output node N 0 . Input data IN 1 , IN 2 , IN 3  and IN 4  are sequentially selected by clock signals CLK 1 , CLK 2 , CLK 3  and CLK 4 . 
         [0035]    When input data corresponds to a first state, the voltage of the output node N 0  may be pulled down to a second supply voltage VSS (for example, a ground voltage) by the data select units DS 1 , DS 2 , DS 3  and DS 4  with a higher current capability with respect to the first current driving capability. When input data corresponds to a second state, the voltage of the output node N 0  may be pulled up to the first supply voltage VDD by the pull-up unit PU 0 . The second state corresponds to a logic low and the first state corresponds to a logic high. 
         [0036]    A first data select unit DS 1  includes a first active path AP 1 , a second active path AP 2 , a first pull-down device PD 1 , and a first pull-up device PU 1 . The first active path AP 1  includes NMOS transistors MN 1  and MN 2  that are coupled in series between the output node N 0  and a first node N 1 . A third clock signal CLK 3  is applied to the NMOS transistor MN 1  and a second clock signal CLK 2  is applied to the NMOS transistor MN 2 . The second active path AP 2  includes PMOS transistors MP 1  and MP 2  that are coupled in series between the output node N 0  and the first node N 1 . A fourth clock signal CLK 4  is applied to the PMOS transistor MP 1  and a first clock signal CLK 1  is applied to the PMOS transistor MP 2 . The first pull-up device PU 1  includes PMOS transistor MP 3  receiving first input data IN 1 . The first pull-down device PD 1  includes NMOS transistor MN 3  receiving the first input data IN 1 . 
         [0037]    A second data select unit DS 2  includes a third active path AP 3 , a fourth active path AP 4 , a second pull-down device PD 2 , and a second pull-up device PU 2 . The third active path AP 3  includes NMOS transistors MN 4  and MN 5  that are coupled in series between the output node N 0  and a second node N 2 . The fourth clock signal CLK 4  is applied to the NMOS transistor MN 4  and the third clock signal CLK 3  is applied to the NMOS transistor MN 5 . The fourth active path AP 4  includes PMOS transistors MP 4  and MP 5  that are coupled in series between the output node N 0  and the second node N 2 . The first clock signal CLK 1  is applied to the PMOS transistor MP 4  and the second clock signal CLK 2  is applied to the PMOS transistor MP 5 . The second pull-up device PU 2  includes PMOS transistor MP 6  receiving second input data IN 2 . The second pull-down device PD 2  includes NMOS transistor MN 6  receiving the second input data IN 2 . 
         [0038]    A third data select unit DS 3  includes a fifth active path AP 5 , a sixth active path AP 6 , a third pull-down device PD 3 , and a third pull-up device PU 3 . The fifth active path AP 5  includes NMOS transistors MN 7  and MN 8  that are coupled in series between the output node N 0  and a third node N 3 . The first clock signal CLK 1  is applied to the NMOS transistor MN 7  and the fourth clock signal CLK 4  is applied to the NMOS transistor MN 8 . The sixth active path AP 6  includes PMOS transistors MP 7  and MP 8  that are coupled in series between the output node N 0  and a third node N 3 . The second clock signal CLK 2  is applied to the PMOS transistor MP 7  and the third clock signal CLK 3  is applied to the PMOS transistor MP 8 . The third pull-up device PU 3  includes PMOS transistor MP 9  receiving a third input data IN 3 . The third pull-down device PD 3  includes NMOS transistor MN 9  receiving the third input data IN 3 . 
         [0039]    A fourth data select unit DS 4  includes a seventh active path AP 7 , an eighth active path AP 8 , a fourth pull-down device PD 4 , and a fourth pull-up device PU 4 . The seventh active path AP 7  includes NMOS transistors MN 10  and MN 11  that are coupled in series between the output node N 0  and a fourth node N 4 . The second clock signal CLK 2  is applied to the NMOS transistor MN 10  and the first clock signal CLK 1  is applied to the NMOS transistor MN 11 . The eighth active path AP 8  includes PMOS transistors MP 10  and MP 11  that are coupled in series between the output node N 0  and the fourth node N 4 . The third clock signal CLK 3  is applied to the PMOS transistor MP 10  and the fourth clock signal CLK 4  is applied to the PMOS transistor MP 11 . The fourth pull-up device PU 4  includes PMOS transistor MP 12  receiving a fourth input data IN 4 . The fourth pull-down device PD 4  includes NMOS transistor MN 12  receiving the fourth input data IN 4 . 
         [0040]      FIG. 4  is a timing diagram illustrating operations of the serializer in  FIG. 3 . The first active path AP 1  is turned on while the second and third clocks CLK 2  and CLK 3  are logic high and the second active path AP 2  is turned on while the fourth and first clocks CLK 4  and CLK 1  are logic low so that a voltage of the first node N 1  is transferred to the output node N 0 . When the first input data IN 1  is a logic high, the voltage of the output node N 0  may be pulled down to the second supply voltage VSS by NMOS transistor MN 3  through the first active path AP 1 . When the first input data IN 1  is a logic low, the voltage of the output node N 0  may be rapidly pulled up to the first supply voltage VDD by both PMOS transistor MP 0  and PMOS transistor MP 3 . Thus, first data D 1  may be output at an output terminal OUT. 
         [0041]    The third active path AP 3  is turned on while the fourth and third clocks CLK 4  and CLK 3  are logic high and the fourth active path AP 4  is turned on while the first and second clocks CLK 1  and CLK 2  are logic low so that a voltage of the second node N 2  is transferred to the output node N 0 . When the second input data IN 2  is a logic high, the voltage of the output node N 0  may be pulled down to the second supply voltage VSS by NMOS transistor MN 6  through the third active path AP 3 . When the second input data IN 2  is a logic low, the voltage of the output node N 0  may be rapidly pulled up to the first supply voltage VDD by both PMOS transistor MP 0  and PMOS transistor MP 6 . Thus, second data D 2  may be output at the output terminal OUT. 
         [0042]    The fifth active path AP 5  is turned on while the first and fourth clocks CLK 1  and CLK 4  are logic high and the sixth active path AP 6  is turned on while the second and third clocks CLK 2  and CLK 3  are logic low so that a voltage of the third node N 3  is transferred to the output node N 0 . When the third input data IN 3  is a logic high, the voltage of the output node N 0  may be pulled down to the second supply voltage VSS by NMOS transistor MN 9  through the fifth active path AP 5 . When the third input data IN 3  is a logic low, the voltage of the output node N 0  may be rapidly pulled up to the first supply voltage VDD by both PMOS transistor MP 0  and PMOS transistor MP 9 . Thus, third data D 3  may be output at the output terminal OUT. 
         [0043]    The seventh active path AP 7  is turned on while the second and first clocks CLK 2  and CLK 1  are logic high and the eighth active path AP 8  is turned on while the third and fourth clocks CLK 3  and CLK 4  are logic low so that a voltage of the fourth node N 4  is transferred to the output node N 0 . When the fourth input data IN 4  is a logic high, the voltage of the output node N 0  may be pulled down to the second supply voltage VSS by NMOS transistor MN 12  through the seventh active path AP 7 . When the fourth input data IN 4  is a logic low, the voltage of the output node N 0  may be rapidly pulled up to the first supply voltage VDD by both PMOS transistor MP 0  and PMOS transistor MP 12 . Thus, fourth data D 4  may be output at the output terminal OUT. Thus, for each input data IN 1 -IN 4 , a respective PMOS transistor, MP 3 , MP 6 , MP 9 , and MP 12 , and the PMOS transistor MP 0  pull up the output node N 0 . 
         [0044]    In the described embodiments of the present invention, the voltage of the output node N 0  may be pulled up rapidly through two active paths so that a rising transition time of an output signal may be decreased in synchronization with a clock signal. Similarly, the voltage of the output node N 0  may be pulled down through two active paths so that a falling transition time may be also decreased. Accordingly effects of parasitic capacitances coupled to the output node N 0  are reduced. 
         [0045]    Although only four data select units have been described above, any number of data select units can be similarly coupled. 
         [0046]    As mentioned above, the serializer and the method of converting parallel data into serial data according to example embodiments of the present invention may reduce data skew and increase operating speed by pulling a voltage of an output node up rapidly in synchronization with a clock signal. 
         [0047]    While embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the scope of the following claims.