Abstract:
An analog-to-digital converter circuit includes: a plurality of sample-and-hold circuits configured to sample an analog signal; an analog-to-digital converter configured to convert the analog signal held by each of the plurality of sample-and-hold circuits into a digital signal; and a control circuit configured to output a control signal, wherein a pair of sample-and-hold circuits among the plurality of sample-and-hold circuits sample an analog signal in a first period and hold an analog signal sampled by another pair of sample-and-hold circuits in a second period prior to the first period based on the control signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of priority from Japanese Patent Application No. 2009-264642 filed on Nov. 20, 2009, the entire contents of which are incorporated herein by reference. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    The embodiments discussed herein relate to an analog-to-digital converter circuit. 
         [0004]    2. Description of Related Art 
         [0005]    A communication reception circuit may include a plurality of analog-to-digital converter (ADC) circuits for converting an analog input signal into a digital signal. For example, a radio reception circuit may include a quadrature detection circuit for down-converting a high-frequency input signal with a local-frequency signal and performing quadrature detection upon the down-converted signal, and an ADC circuit for converting an analog I signal and an analog Q signal, which have been extracted by the quadrature detection circuit, into a digital I signal and a digital Q signal, respectively. 
         [0006]    Japanese Laid-open Patent Publication Nos. H3-220917 and 2006-54684 disclose related techniques. 
       SUMMARY 
       [0007]    According to one aspect of the embodiments, an analog-to-digital converter circuit includes: a plurality of sample-and-hold circuits configured to sample an analog signal; an analog-to-digital converter configured to convert the analog signal held by each of the plurality of sample-and-hold circuits into a digital signal; and a control circuit configured to output a control signal, wherein a pair of sample-and-hold circuits among the plurality of sample-and-hold circuits sample an analog signal in a first period and hold an analog signal sampled by another pair of sample-and-hold circuits in a second period prior to the first period, based on the control signal. 
         [0008]    Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning by practice of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  illustrates an exemplary ADC circuit; 
           [0010]      FIG. 2  illustrates an exemplary ADC circuit; 
           [0011]      FIG. 3  illustrates an exemplary operation of an ADC circuit; 
           [0012]      FIG. 4  illustrates an exemplary sample-and-hold circuit; 
           [0013]      FIG. 5  illustrates an exemplary ADC; 
           [0014]      FIG. 6  illustrates an exemplary ADC circuit; 
           [0015]      FIG. 7  illustrates an exemplary sample-and-hold circuit group; and 
           [0016]      FIG. 8  illustrates an exemplary operation of an ADC circuit. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0017]    An analog-to-digital converter (ADC) circuit includes a sample-and-hold circuit for sampling and holding an analog input signal and an analog-to-digital converter (ADC) for converting a sampled analog signal into a digital signal. An ADC circuit for an analog I signal and an ADC circuit for an analog Q signal may be provided set in parallel to each other. 
         [0018]    When a common ADC circuit is used, a plurality of sample-and-hold circuits sample and hold analog input signals and the common ADC circuit time-divisionally converts the sampled analog input signals into digital output signals. Conversion from an analog signal into a digital signal is performed in a plurality of cycles. 
         [0019]      FIG. 1  illustrates an exemplary ADC circuit. An ADC circuit  10  includes a first pair of analog input terminals for receiving first analog input signals VIPA and VIMA, which are I signals, and a first ADC circuit ADCU 1  for converting the first analog input signals VIPA and VIMA into a digital output signal DOA and outputting the digital output signal DOA. The first analog input signals VIPA and VIMA may be a differential signal. 
         [0020]    Furthermore, the ADC circuit  10  includes a second pair of analog input terminals for receiving second analog input signals VIPB and VIMB corresponding to Q signals and a second ADC circuit ADCU 2  for converting the second analog input signals VIPB and VIMB into a digital output signal DOB and outputting the digital output signal DOB. The second analog input signals VIPB and VIMB may be a differential signal. 
         [0021]    The first ADC circuit ADCU 1  includes a first sample-and-hold circuit SH 1  for sampling and holding the first analog input signals, an analog-to-digital converter ADC 1  for converting analog input signals VOPA and VOMA into a digital signal, and a timing control circuit Timing- 1  for supplying control clock signals CLKadc and CLKsh in synchronization with a clock CLK. The second ADC circuit ADCU 2  includes a second sample-and-hold circuit SH 2  for sampling and holding the second analog input signals, an analog-to-digital converter ADC 2  for converting analog input signals VOPB and VOMB into a digital signal, and a timing control circuit Timing- 2  for supplying the control clock signals CLKadc and CLKsh in synchronization with the clock CLK. 
         [0022]    The ADC circuit  10  illustrated in  FIG. 1  includes the first ADC circuit ADCU 1  for I signals and the second ADC circuit ADCU 2  for Q signals. The first ADC circuit ADCU 1  samples an analog input signal in a first clock cycle. In a second clock cycle, the sample-and-hold circuit SH 1  holds the analog input signal, and the first ADC circuit ADCU 1  converts the held analog input signal into a digital signal. The second ADC circuit ADCU 2  samples an analog input signal in the first clock cycle. In the second clock cycle, the sample-and-hold circuit SH 2  holds the analog input signal, and the second ADC circuit ADCU 2  converts the held analog input signal into a digital signal. For example, every two clock cycles an analog input signal is sampled and held, and the sampled and held analog input signal is converted into a digital signal. When the first ADC circuit ADCU 1  and the second ADC circuit ADCU 2  are pipeline ADC circuits, the digital output signals DOA and DOB may be output from the first ADC circuit ADCU 1  and the second ADC circuit ADCU 2  respectively, after clock cycles corresponding to the number of pipelines elapse. 
         [0023]    The ADC circuit  10  illustrated in  FIG. 1  includes the first sample-and-hold circuit SH 1  and the analog-to-digital converter ADC 1  for I signals, and includes the second sample-and-hold circuit SH 2  and the analog-to-digital converter ADC 2  for Q signals. 
         [0024]    In order to reduce an area, a common ADC circuit may be provided for the sample-and-hold circuits SH 1  and SH 2 . In a first clock cycle, the sample-and-hold circuit SH 1  samples the analog input signals VIPA and VIMA and the second sample-and-hold circuit SH 2  samples the analog input signals VIPB and VIMB. In second and third clock cycles, the sample-and-hold circuit SH 1  holds the analog input signals VIPA and VIMA, the sample-and-hold circuit SH 2  holds the analog input signals VIPB and VIMB, and the common ADC circuit converts the held analog input signals into digital signals. Analog input signals may be sampled and held and the sampled and held analog input signals may be converted into digital signals every three clock cycles. An analog-to-digital conversion speed may be reduced. 
         [0025]      FIG. 2  illustrates an exemplary ADC circuit. An ADC circuit  20  illustrated in  FIG. 2  includes a sample-and-hold circuit group  26  including three sample-and-hold circuits SH 1 , SH 2 , and SH 3 , and a common ADC  23  for the three sample-and-hold circuits. 
         [0026]    For example, in each odd-numbered clock cycle, a pair of sample-and-hold circuits is selected from among the first sample-and-hold circuit SH 1 , the second sample-and-hold circuit SH 2 , and the third sample-and-hold circuit SH 3 , and the selected pair of sample-and-hold circuits samples the first analog input signals VIPA and VIMA and the second analog input signals VIPB and VIMB. For example, one of the selected sample-and-hold circuits holds a first analog input signal in an even-numbered clock cycle. The other one of the selected sample-and-hold circuits holds a second analog input signal in an odd-numbered clock cycle next to the even-numbered clock cycle. The held analog input signals are input into the common ADC  23  as outputs VOP and VOM of the sample-and-hold circuit SH. In each clock cycle, the common ADC  23  converts the held first or second analog input signal into a digital signal. In the case of a pipeline ADC circuit, the converted digital output signals DOA and DOB may be output after clock cycles corresponding to the number of pipelines elapse. 
         [0027]    In the ADC circuit  20  illustrated in  FIG. 2 , the first analog input I signals VIPA and VIMA are input into a first pair  21 A of input terminals and the second analog input Q signals VIPB and VIMB are input into a second pair  21 B of input terminals. The first and second analog input signals may be differential signals. A selector  22  selects a pair of sample-and-hold circuits from among three sample-and-hold circuits, the sample-and-hold circuits SH 1 , SH 2 , and SH 3 . The first analog input signals are input from the first pair  21 A of input terminals into the selected pair of sample-and-hold circuits, and the second analog input signals are input from the second pair  21 B of input terminals into the selected pair of sample-and-hold circuits. 
         [0028]    Every clock cycle, the common ADC  23  alternately converts the first and second analog input signals held by one of the sample-and-hold circuits SH 1 , SH 2 , and SH 3  into a digital signal and outputs the converted digital signal. A demultiplexer  24  converts a serial digital output signal DO output from the common ADC  23  into parallel signals. The first digital output signal DOA and the second digital output signal DOB are output from output terminals  27 A and  27 B, respectively. A timing control circuit  25  generates a control clock signal CLKsel, CLKsh, or CLKadc in synchronization with the clock CLK and supplies it to the selector  22 , the sample-and-hold circuits SH 1 , SH 2 , and SH 3 , the common ADC  23 , or the demultiplexer  24 . 
         [0029]      FIG. 3  illustrates an exemplary operation of an ADC circuit. The operation illustrated in  FIG. 3  may be performed by the ADC circuit illustrated in  FIG. 2 . Referring to  FIG. 3 , SH 1 , SH 2 , and SH 3  may represent operations of the sample-and-hold circuits SH 1 , SH 2 , and SH 3  illustrated in  FIG. 2 , respectively. ADC first-stage output may represent a first-stage output of the common ADC  23  having a pipeline configuration, and DOA and DOB may represent digital output signals. 
         [0030]    In a clock cycle CK 1 , the sample-and-hold circuits SH 1  and SH 2  are selected from among three sample-and-hold circuits, the sample-and-hold circuits SH 1 , SH 2 , and SH 3 , and sample a first analog input signal I 1  and a second analog input signal Q 1 , respectively. In a next clock cycle CK 2 , the sample-and-hold circuit SH 1  holds the first analog input signal I 1  and outputs the first analog input signal I 1  to output terminals VOP and VOM. At that time, the second sample-and-hold circuit SH 2  is not in a sampling state and a holding state, and stores the second analog input signal Q 1 . The common ADC  23  converts the held first analog input signal I 1  into a digital signal. 
         [0031]    In a next clock cycle CK 3 , a first-stage circuit in the common ADC  23  outputs a digital signal I 1 . In the clock cycle CK 3 , the second sample-and-hold circuit SH 2  enters the holding state, holds the second analog input signal Q 1 , and outputs the second analog input signal Q 1  to the output terminals VOP and VOM. The common ADC  23  converts the held second analog input signal Q 1  into a digital signal. In the clock cycle CK 3 , the sample-and-hold circuits SH 3  and SH 1  sample a first analog input signal I 2  and a second analog input signal Q 2 , respectively. In the clock cycle CK 3 , one of the three sample-and-hold circuits holds the analog input signal sampled in the clock cycle CK 1 , and the other two of the three sample-and-hold circuits individually sample the first and second analog input signals. As a result, a sampling period is reduced, and an analog-to-digital conversion speed is increased. 
         [0032]    In a clock cycle CK 4 , the first-stage circuit in the common ADC  23  outputs a digital signal Q 1 . In the clock cycle CK 4 , the third sample-and-hold circuit SH 3  holds the first analog input signal I 2  sampled in the clock cycle CK 3 . The common ADC  23  converts the held first analog input signal I 2  into a digital signal. 
         [0033]    In a clock cycle CK 5 , for example, like in the clock cycle CK 3 , the first-stage circuit in the common ADC  23  outputs a digital signal I 2  and the sample-and-hold circuit SH 1  holds the second analog input signal Q 2  and outputs the second analog input signal Q 2  to the output terminals VOP and VOM. The common ADC  23  starts analog-to-digital conversion. The sample-and-hold circuits SH 2  and SH 3  sample a first analog input signal I 3  and a second analog input signal Q 3 , respectively. 
         [0034]    An operation in each of clock cycles CK 6  and CK 8  may be substantially the same as or similar to that in, for example, the clock cycle CK 4 , and an operation in each of clock cycles CK 7  and CK 9  may be substantially the same as or similar to that in, for example, the clock cycle CK 5 . 
         [0035]    The common ADC  23  has a four-stage pipeline configuration, and outputs a digital signal four clock cycles after starting analog-to-digital conversion. The common ADC  23  alternately performs analog-to-digital conversion upon the first analog input signal I and the second analog input signal Q, and alternately outputs the first digital output signal I and the second digital output signal Q. In a clock cycle CK 8 , digital output signals corresponding to the analog input signals I 1  and Q 1  that have been sampled in the clock cycle CK 1  are output as the digital output signals DOA and DOB, respectively. In a clock cycle CK 10 , digital output signals corresponding to the analog input signals I 2  and Q 2  that have been sampled in the clock cycle CK 3  are output as the digital output signals DOA and DOB, respectively. 
         [0036]    In the odd-numbered clock cycles CK 1 , CK 3 , CK 5 , CK 7 , and CK 9 , a pair of sample-and-hold circuits selected from among the first sample-and-hold circuit SH 1 , the second sample-and-hold circuit SH 2 , and the third sample-and-hold circuit SH 3  samples the first and second analog input signals. In the even-numbered clock cycles CK 2 , CK 4 , CK 6 , CK 8 , and CK 10 , one of the sample-and-hold circuits included in the pair holds the first analog input signal. In odd-numbered clock cycles next to the even-numbered clock cycles, the other one of the sample-and-hold circuits included in the pair holds the second analog input signal. In each clock cycle, the common ADC  23  converts the held first or second analog input signal into a digital signal. Every two clock cycles, two analog input signals are sampled by three sample-and-hold circuits SH. In each clock cycle, the common ADC  23  performs analog-to-digital conversion and outputs a digital output signal. 
         [0037]      FIG. 4  illustrates an exemplary sample-and-hold circuit.  FIG. 4  illustrates a sample mode φ 1  and a hold mode φ 2  of a sample-and-hold circuit SHn. 
         [0038]    A sample-and-hold circuit includes sampling capacitors C P1  and C M1 , a differential output amplifier AMP, a pair of first switches SW P  and SW M , a second switch SW C , and a pair of third switches SW IP  and SW IM . The pair of the first switches SW P  and SW M  individually couples input terminals for differential input signals VIP and VIM or output terminals for differential output signals VOP and VOM to the sampling capacitors C P1  and C M1 . The second switch SW C  couples an electrode XP of the sampling capacitor C P1  and an electrode XM of the sampling capacitor C M1  to a reference voltage VC. The pair of the third switches SW IP  and SW IM  individually couples the electrodes XP and XM to input terminals (+,−) of the amplifier AMP. A switched capacitor circuit may include the sampling capacitors C P1  and C M1  and a group of switches SW P , SW M , SW C , SW IP , and SW IM . 
         [0039]    In the sample mode φ 1 , the pair of the first switches SW P  and SW M  individually couples one electrode of each of the sampling capacitors C P1  and C M1  to the input terminals. The second switch SW C  couples the other electrodes XP and XM of the sampling capacitors C P1  and C M1  to the reference voltage VC. Voltages VIP-VC and VIM-VC are applied to the sampling capacitors C P1  and C M1 , respectively, so that an electric charge is stored in the sampling capacitors C P1  and C M1 . Each of the sampling capacitors C P1  and C M1  samples an analog input signal. 
         [0040]    In the hold mode φ 2 , the pair of the first switches SW P  and SW M  individually couples one electrode of each of the sampling capacitors C P1  and C M1  to the output terminals. The second switch SW C  is in an off (open) state. The pair of the third switches SW IP  and SW IM  individually couples the other electrodes XP and XM of the sampling capacitors C P1  and C M1  to input terminals of the amplifier AMP. The amplifier AMP drives output voltages VOP and VOM so as to set the voltages of the other electrodes XP and XM to the reference voltage VC. As a result, the output voltages VOP and VOM are substantially the same as input voltages VIP and VIM, respectively. The amplifier AMP may output the analog input signals VIP and VIM to the output terminals VOP and VOM, respectively. 
         [0041]    For example, when the switches SW P , SW M , SW C , SW IP , and SW IM  are in the open state and an electric charge is stored in the sample capacitors, another mode different from the sample mode and the hold mode illustrated in  FIG. 4  may be set. 
         [0042]    The sample-and-hold circuit SHn may include a circuit different from the circuit illustrated in  FIG. 4 . For example, the sample-and-hold circuit SHn may include a first capacitor between an input terminal of the amplifier illustrated in  FIG. 4  and an analog input terminal and a second capacitor between the input terminal of the amplifier and an output terminal. At the time of sampling, an analog input voltage may be applied to the first capacitor. At the time of holding, a reference voltage may be applied to the first capacitor. 
         [0043]      FIG. 5  illustrates an exemplary ADC. As illustrated in  FIG. 2 , an ADC circuit includes the sample-and-hold circuit group  26  including three sample-and-hold circuits SH 1 , SH 2 , and SH 3 , and an ADC  23  for converting differential output signals VOP and VOM (VOP-VOM) into a digital signal. The ADC  23  includes four conversion stages Stage 1  to Stage 4 , delay flip flops  231  to  236  for storing outputs DOUT 0  to DOUT 2  of the conversion stages, and a digital computation circuit  237 . 
         [0044]    The conversion stage Stage 1  includes a 1.5-bit ADC, a DAC  240 , a subtracter  238 , and an amplifier  239 . The 1.5-bit ADC converts a differential analog input signal OUT 0  (VOP-VOM) into the digital signal DOUT 0  that is a 1.5-bit signal. The DAC  240  generates a positive reference voltage +Vref, a negative reference voltage −Vref, or 0 V in accordance with the digital signal DOUT 0 . The subtracter  238  subtracts the output of the DAC  240  from the differential analog input signal OUT 0 . The amplifier  239  doubles the output of the subtracter  238 . 
         [0045]    For example, the 1.5-bit ADC detects whether the differential analog input signal OUT 0  has a gray area voltage (output 01) close to ±0 V, which is a middle value between the reference voltages −Vref and +Vref, a voltage (output 10) higher than the gray area voltage, or a voltage (output 00) lower than the gray area voltage, and outputs 00, 01, or 10 as the output DOUT 0 . When the output DOUT 0  is 00, the DAC  240  outputs the voltage −Vref. When the output DOUT 0  is 01, the DAC  240  outputs 0 V. When the output DOUT 0  is 10, the DAC  240  outputs the voltage +Vref. When the output DOUT 0  that is an output of the 1.5-bit ADC is 00, an output OUT 1  may be a voltage obtained by adding the reference voltage Vref to the input signal OUT 0  and doubling a result of the addition. When the output DOUT 0  is 01, the output OUT 1  may be a voltage obtained by doubling the input signal OUT 0 . When the output DOUT 0  is 10, the output OUT 1  may be a voltage obtained by subtracting the reference voltage Vref from the input signal OUT 0  and doubling a result of the subtraction. 
         [0046]    The conversion stage Stage 2  calculates the lower-order digital signal DOUT 1  corresponding to the output OUT 1  of the conversion stage Stage 1 . The circuit configuration of the conversion stages Stage 2 , Stage 3 , and Stage 4  may be substantially the same as or similar to that of the conversion stage Stage 1 , and may output a 2-bit (1.5-bit) digital signal. 
         [0047]    The outputs DOUT 0 , DOUT 1 , DOUT 2 , and DOUT 3  of the conversion stages Stage 1 , Stage 2 , Stage 3 , and Stage 4  are transferred via the delay flip-flops  231  to  236  in synchronization with the clock signal CLKadc, and are input into the digital computation circuit  237  three clock cycles later. The outputs DOUT 0  to DOUT 3  may also be input into the digital computation circuit  237  contemporaneously. The digital computation circuit  237  performs computation on the 2-bit digital outputs DOUT 0  to DOUT 3  so as to output a 5-bit digital output D 0 . A computation method used in a 1.5-bit ADC may be used. 
         [0048]    As illustrated in  FIG. 3 , in the clock cycle CK 3 , the most significant digital output of the signal I 1  is output as the output DOUT 0  of the first conversion stage Stage 1 . Although not illustrated, in the clock cycles CK 4 , CK 5 , and CK 6 , the lower-order 2-bit (1.5-bit) digital outputs of the signal I 1  are output as the outputs DOUT 1 , DOUT 2 , and DOUT 3  of the subsequent conversion stages Stage 2 , Stage 3 , and Stage 4 , respectively. In the clock cycle CK 4 , the most significant 2-bit (1.5-bit) digital output of the signal Q 1  is output as the output DOUT 0  of the first conversion stage Stage 1 . Although not illustrated, in the clock cycles CK 5 , CK 6 , and CK 7 , the lower-order digital outputs of the signal Q 1  are output as the outputs DOUT 1 , DOUT 2 , and DOUT 3  of the subsequent conversion stages Stage 2 , Stage 3 , and Stage 4 , respectively. 
         [0049]    In the clock cycles CK 8  and CK 9 , the demultiplexer  24  outputs in parallel the digital output signals DOA and DOB corresponding to the input signals I 1  and Q 1  that have been serially input. Subsequently, every two clock cycles, the digital output signals DOA and DOB corresponding to input signals I 2  and Q 2 , I 3  and Q 3 , and so on, are output in parallel. 
         [0050]    For example, a 1-bit, 2-bit, or n-bit ADC may be used. The DAC  240  generates an analog voltage in accordance with the digital output DOUT of the ADC. The pipeline ADC  23  may include an ADC and a DAC. 
         [0051]    The common ADC  23  may include a flash ADC or a successive approximation ADC. These ADCs may perform analog-to-digital conversion in each clock cycle. 
         [0052]      FIG. 6  illustrates an exemplary ADC circuit. The ADC circuit  10  illustrated in  FIG. 6  includes the analog input terminals  21 A and  21 B, the selector  22 , the sample-and-hold circuit group  26 , the common ADC  23 , the demultiplexer  24 , and the timing control circuit  25 . The sample-and-hold circuit group  26  included in the ADC circuit illustrated in  FIG. 6  includes switched capacitor circuits SC 1 , SC 2 , and SC 3  and a differential output amplifier  28 . The differential output amplifier  28  may be a common differential output amplifier for the switched capacitor circuits SC 1 , SC 2 , and SC 3 . 
         [0053]    The sample-and-hold circuit group  26  included in the ADC circuit illustrated in  FIG. 2  includes the sample-and-hold circuits SH 1 , SH 2 , and SH 3 . Each of the sample-and-hold circuits SH 1 , SH 2 , and SH 3  includes a switched capacitor circuit and a differential output amplifier. In the sample-and-hold circuit group  26  included in the ADC circuit illustrated in  FIG. 6 , a common differential output amplifier is provided. The common differential output amplifier time-divisionally performs a holding operation every clock cycle for three switched capacitor circuits. 
         [0054]      FIG. 7  illustrates an exemplary sample-and-hold circuit group. The sample-and-hold circuit group illustrated in  FIG. 7  may be the sample-and-hold circuit group  26  in the ADC circuit illustrated in  FIG. 5 . The sample-and-hold circuit group illustrated in  FIG. 7  includes the first switched capacitor circuit SC 1 , the second switched capacitor circuit SC 2 , the third switched capacitor circuit SC 3 , and the differential output amplifier  28 . 
         [0055]    The configuration of the switched capacitor circuits SC 1 , SC 2 , and SC 3  may be substantially the same as or similar to that of the sample-and-hold circuit illustrated in  FIG. 4 . The first switched capacitor circuit SC 1  includes sampling capacitors C P11  and C M11 , a pair of first switches SW P1  and SW M1  for individually coupling input terminals for differential input signals VIP 1  and VIM 1  or output terminals for the differential output signals VOP and VOM to the sampling capacitors C P11  and C M11 , a second switch SW C1  for coupling an electrode XP 1  of the sampling capacitor C P11  and an electrode XM 1  of the sampling capacitor C M11  to the reference voltage VC, and a pair of third switches SW IP1  and SW IM1  for individually coupling the electrodes XP 1  and XM 1  to input terminals ZP and ZM of the differential output amplifier  28 . The configuration of the switched capacitor circuits SC 2  and SC 3  may be substantially the same as or similar to that of the switched capacitor circuit SC 1 . 
         [0056]    For example, the first switched capacitor circuit SC 1  and the second switched capacitor circuit SC 2  may be in the sample mode and the third switched capacitor circuit SC 3  may be in the hold mode. In the first switched capacitor circuit SC 1 , the first switches SW P1  and SW M1  couple one electrode of each of the sampling capacitors C P11  and C M11  to the input signals VIP 1  and VIM 1 , respectively, and the second switch SW C1  couples the other electrodes of the sampling capacitors C P11  and C M11  to the reference voltage VC. In the second switched capacitor circuit SC 2 , first switches SW P2  and SW M2  connect one electrode of each of the sampling capacitors C P12  and C M12  to input signals VIP 2  and VIM 2 , respectively, and a second switch SW C2  couples the other electrodes of the sampling capacitors C P12  and C M12  to the reference voltage VC. Analog input voltages VIP 1 -VC, VIM 1 -VC, VIP 2 -VC, and VIM 2 -VC are applied to the sampling capacitors C P11 , C M11 , C P12 , and C M12 , respectively, so that an electric charge is stored in these sampling capacitors. A sampling capacitor samples an analog input signal. 
         [0057]    In the third switched capacitor circuit SC 3 , first switches SW P3 , SW M3 , SW IP3 , and SW IM3  individually couple one electrode of each of the sampling capacitors C P13  and C M13  to the output signals VOP and VOM and individually couple the other electrode XP 3  of the sampling capacitor C P13  and the other electrode XM 3  of the sampling capacitor C M13  to input terminals ZP and ZM of the differential output amplifier  28 . The third switched capacitor circuit SC 3  enters the hold state, and analog input signals sampled by the sampling capacitors C P13  and C M13  are output from the differential output amplifier  28 . 
         [0058]    Each of the first switched capacitor circuit SC 1  and the second switched capacitor circuit SC 2  samples an analog input signal. The third switched capacitor circuit SC 3  and the differential output amplifier  28  hold the sampled analog input signals as the output signals VOP and VOM. 
         [0059]    The configuration of the common ADC  23  included in the ADC circuit  10  illustrated in  FIG. 6  may be substantially the same as or similar to that of the common ADC  23  illustrated in  FIG. 5 , for example. 
         [0060]      FIG. 8  illustrates an exemplary operation of an ADC circuit.  FIG. 8  illustrates operational states of the switched capacitor circuits SC 1 , SC 2 , and SC 3 , a digital output signal DOUT 0  of a first conversion stage in the common ADC  23 , and a digital output signals DOA and DOB. 
         [0061]    In the clock cycle CK 1 , the switched capacitor circuits SC 1  and SC 2  sample the first analog input signal I 1  and the second analog input signal Q 1 , respectively. In the clock cycle CK 2 , the switched capacitor circuit SC 1  in the hold state outputs the sampled first analog input signal I 1  to the output terminals VOP and VOM of the differential output amplifier  28 . At that time, the switched capacitor circuit SC 2  is not in the sample state and the hold state, and three switches included therein are in the open state. The common ADC  23  receives the first analog input signal I 1  from the differential output amplifier  28  and starts analog-to-digital conversion. 
         [0062]    In the clock cycle CK 3 , a first-stage circuit in the common ADC  23  outputs the digital signal I 1 . In the clock cycle CK 3 , the switched capacitor circuit SC 2  in the hold state outputs the sampled second analog input signal Q 1  to the output terminals VOP and VOM of the differential output amplifier  28 . The common ADC  23  receives the second analog input signal Q 1  and starts analog-to-digital conversion. In the clock cycle CK 3 , the switched capacitor circuits SC 3  and SC 1  sample the first analog input signal I 2  and the second analog input signal Q 2 , respectively. In the clock cycle CK 3 , while one of three switched capacitor circuits holds the analog input signal sampled in the clock cycle CK 1 , the remaining switched capacitor circuits individually sample new first and second analog input signals. A sampling period may be reduced and an analog-to-digital conversion speed may be increased. 
         [0063]    In the clock cycle CK 4 , the first-stage circuit in the common ADC  23  outputs the digital signal Q 1 . In the clock cycle CK 4 , the third switched capacitor circuit SC 3  outputs the first analog input signal I 2  sampled in the clock cycle CK 3  to the differential output amplifier  28 . The common ADC  23  receives the first analog input signal I 2  and starts analog-to-digital conversion. 
         [0064]    Similar to the clock cycle CK 3 , in the clock cycle CK 5 , the first-stage circuit in the common ADC  23  outputs the digital signal I 2  and the switched capacitor circuit SC 1  is in the hold state. The differential output amplifier  28  outputs the second analog input signal Q 2  to the output terminals VOP and VOM, and the common ADC  23  starts analog-to-digital conversion. The switched capacitor circuits SC 2  and SC 3  sample the first analog input signal I 3  and the second analog input signal Q 3 , respectively. 
         [0065]    An operation in the clock cycles CK 6  and CK 8  may be substantially the same as or similar to that in the clock cycle CK 4 . An operation in the clock cycles CK 7  and CK 9  may be substantially the same as or similar to that in the clock cycle CK 5 . 
         [0066]    The common ADC  23  has a four-stage pipeline configuration, and outputs a digital signal four clock cycles after starting analog-to-digital conversion. The common ADC  23  alternately performs analog-to-digital conversion upon a first analog input signal I and a second analog input signal Q and alternately outputs a first digital output signal I and a second digital output signal Q. In the clock cycle CK 8 , digital output signals corresponding to the analog input signals I 1  and Q 1  sampled in the clock cycle CK 1  are output as the output signals DOA and DOB, respectively. In the clock cycle CK 10 , digital output signals corresponding to the analog input signals I 2  and Q 2  sampled in the clock cycle CK 3  are output as the output signals DOA and DOB, respectively. 
         [0067]    In the odd-numbered clock cycles CK 1 , CK 3 , CK 5 , CK 7 , and CK 9 , a pair of switched capacitor circuits selected from among the first switched capacitor circuit SC 1 , the second switched capacitor circuit SC 2 , and the third switched capacitor circuit SC 3  samples the first and second analog input signals. In the even-numbered clock cycles CK 2 , CK 4 , CK 6 , CK 8 , and CK 10 , one of the switched capacitor circuits included in the pair holds the first analog input signal. In odd-numbered clock cycles next to the even-numbered clock cycles, the other one of the switched capacitor circuits included in the pair holds the second analog input signal. In each clock cycle, the common ADC  23  converts the first or second analog input signal into a digital signal. Three switched capacitor circuits SC are provided, and two analog input signals are sampled every two clock cycles. In each clock cycle, the common ADC  23  converts a sampled analog input signal into a digital output signal and outputs the digital output signal. 
         [0068]    Example embodiments of the present invention have now been described in accordance with the above advantages. These examples are merely illustrative of the invention. Many variations and modifications will be apparent to those skilled in the art.