Abstract:
An integrated circuit includes a master circuit operating at a first frequency for controlling slave circuits operating at a second frequency. The integrated circuit uses registers for eliminating difficulties arising from different and independent frequencies of the master and slave circuits.

Description:
FIELD OF THE INVENTION 
     The invention relates to the field of integrated circuits, and, more particularly, to an integrated circuit having at least two circuits operating at independent frequencies. 
     BACKGROUND OF THE INVENTION 
     A master circuit designates a circuit that may control at least one other circuit, called a slave circuit. The slave circuit performs according to instructions dictated by the master circuit. For example, a state machine may be used to produce control sequences for logic circuits that have specific functions, e.g., counters, memories, and arithmetic logic units. These control sequences may or may not be conditional. 
     Conventionally, the state machine enables the performance of a sequence of operations for producing control signals for controlling a slave circuit. The frequency of operations of the state machine is generally controlled by a clock signal f 1 . In general, the state machine sends logic commands to the slave circuits by a control bus to which a sequencer and the slave circuits are connected. The logic commands include writing or reading information on a data bus. It is also possible that the sequencer may send a command to a particular slave circuit operating at a frequency f 2  for carrying out at least one operation in parallel. 
     In general, the state machine does not verify whether a particular slave circuit has received the command to be performed. Accordingly, the state machine limits itself, for example, to sending a command during a time interval in which the state machine is sure that the slave circuit will receive this command. 
     When the state machine and the slave circuit are synchronous, the state machine may send a command having a determined duration corresponding to a certain number of clock cycles. The synchronization between the state machine and the slave circuit makes it possible to ensure efficient reception. Synchronous refers to when the clock frequencies f 1  and f 2  are identical to or multiples of one another with respect to the clock signals originating from the same clock. 
     In contrast, when the clock frequency f 1  of the state machine and the clock frequency f 2  of the slave circuit are not synchronous, the reception of the control signal by the slave sequencer may become random. This could lead to malfunctioning of the integrated circuit. Not synchronous, i.e., asynchronous, refers to when the respective clock signals are different or undergo significant fluctuations during operation. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to prevent malfunctioning of an integrated circuit comprising at least one master circuit and one slave circuit operating at independent respective frequencies. 
     The integrated circuit comprises a master circuit having a clock input for receiving a first clock signal originating from a first clock circuit, and an output for providing a control signal. The control signal is activated during an active edge of the first clock signal. A slave circuit has a control input and a clock input for receiving a second clock signal originating from a second clock circuit. The second clock circuit is independent of the first clock circuit. The integrated circuit further comprises a first register having a clock input for receiving the second clock signal, a data input for storing the control signal during an active edge of the second clock signal, and an output is connected to the control input of the slave circuit. During an active edge of the second clock signal, the first register stores the control signal produced by the master circuit and provides the stored control signal. The signal delivered by the first register is synchronized with the second clock signal. 
     Preferably, the integrated circuit comprises a second register having a clock input for receiving the clock signal, a data input is connected to the output of the first register for storing the control signal during an active edge of the clock signal, and an output. The master circuit further comprises an information input connected to the output of the second register for receiving the control signal to deactivate the control signal at the output of the master circuit when the control signal received becomes active. 
     To interrupt sending of the control signal to the slave circuit, the input of the second register is connected to the output of the first register for storing the control signal received by the slave circuit during an active edge of the first clock signal. The second register delivers the stored control signal to the master circuit. The use of the two registers eliminates the difficulties caused by different and independent clock frequencies. Furthermore, the master circuit receives a return of the transmission of its control signal by the second register and the information input. This makes it possible to ascertain that the slave circuit has actually received the control signal. 
     According to another embodiment, the circuit further comprises a third register having a clock input for receiving the clock signal, a data input is connected to the output of the master circuit for storing the control signal during an active edge of the clock signal, and an output is connected to the input of the first register. The third register is connected between the first register and the master circuit. A fourth register has a clock input for receiving the clock signal, a data input is connected to the output of the first register for storing the stopping signal, and an output is connected to the input of the second register. The fourth register is connected between the first and second registers. 
     This arrangement primarily makes it possible to prevent a condition known as metastability, i.e., having only a slight margin of stability. This condition occurs during fast transitions of logic states on signals present at the input of the register. The signal at the input of the register must be stabilized and must be presented sufficiently in advance so that the register can store the signal during an active edge of the clock of the register. Otherwise, the stored signal is always erroneous which may lead to malfunctioning of the integrated circuit. 
     According to yet another embodiment, the circuit further comprises an inverter having one input and one output, wherein the input is connected to the output of the first register. The output of the first register is connected to the control input of the slave circuit. A logic gate has two inputs and one output, wherein a first input is connected to the input of the first register. A second input is connected to the output of the inverter. A fifth register has a clock input for receiving the clock signal. An input is connected to the output of the logic gate for storing the control signal, and an output is connected to the control input of the master circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features and advantages of the present invention will become apparent from the detailed description of the invention which follows, when considered in light of the accompanying drawings in which: 
     FIG. 1 shows an integrated circuit, according to the present invention; 
     FIG. 2 shows a first embodiment using third and fourth registers, according to the present invention; and 
     FIG. 3 shows a second embodiment using a logic gate and an inverter, according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to FIG. 1, the integrated circuit C comprises a master circuit  1 , a slave circuit  2 , first and second clock circuits H 1  and H 2 , and first and second registers R 1  and R 2 . The master circuit  1  is, for example, a state machine and the slave circuit  2  is, for example, a counter. The first and second clock circuits H 1  and H 2  respectively provide first and second clock signals Ck 1  and Ck 2  at one output. The frequencies of the clock signals originate from two totally independent clock circuits. 
     The master circuit  1  has a clock input for receiving the clock signal Ck 1 , an information input and a control output for providing a control signal. The first register R 1  has a data input connected to the control output of the master circuit  1 , a clock input is connected to the output of the second clock circuit H 2  for receiving the second clock signal Ck 2 , and one output. The slave circuit  2 , i.e., the counter, has one control input connected to the output of the first register R 1 , and one clock input is connected to the output of the second clock circuit H 2  for receiving the clock signal Ck 2 . 
     As shown in FIG. 1, the circuit C also has a second register R 2  having a clock input connected to the output of the first clock circuit H 1  for receiving the first clock signal Ck 1 . An input is connected to the output of the first register R 1 . An output is connected to the information input of the master circuit  1 . The first and second registers R 1  and R 2 , for example, are D type flip-flop circuits well known to those skilled in the art. 
     As indicated above, the master circuit  1  may send a control signal, for example, so that the slave circuit  2  performs an operation in parallel. The control signal is activated during an active edge of the first clock signal Ck 1 . In this example, the control signal could be a synchronous zero resetting command that has to be received only once. When the frequency of the clock signal Ck 1  is greater than the frequency of the clock signal Ck 2 , the first register R 1  stores and provides the control signal to the slave circuit  2  during a first active edge of the second clock signal Ck 2 . 
     Then, the second register R 2  stores the control signal received by the slave circuit  2  and provides the control signal to the information input of the master circuit  1 . This is done during a first active edge of the first clock signal Ck 1 , wherein the first active edge immediately follows the first active edge of the second clock signal Ck 2 . The first register R 1  enables the control signal sent by the master circuit  1 , which operates at a first frequency, to be synchronized with the clock signal Ck 2  of the slave circuit  2 . 
     During a second active edge of the first clock signal Ck 1 , the master circuit  1  interrupts the sending of the control signal after having received the control signal at the information input. Thus, during a second active edge of the second clock signal Ck 2 , the first register R 1  no longer receives the control signal from the master circuit  1 . The second active edge immediately follows the second active edge of the first clock signal Ck 1 . It can be observed that, in this first case, the control signal has been received by the slave circuit  2  only during one cycle of the second clock signal Ck 2 . The frequency of the first clock signal Ck 1  is greater than the frequency of the second clock Ck 2 . 
     FIG. 2 shows the circuit C of FIG. 1 modified according to a first embodiment of the invention. The modified circuit C comprises a third register R 3  having a clock input for receiving the clock signal Ck 2 . A data input is connected to the output of the master circuit  1  for storing the control signal during an active edge of the clock signal Ck 2 . An output is connected to the input of the first register R 1 . The third register R 3  thus sets up the connection between the master circuit  1  and the first register R 1 . 
     Still referring to FIG. 2, a fourth register R 4  has been added. The fourth register R 4  has a clock input connected to the output of the first clock circuit H 1  for receiving the clock signal Ck 1 , an input is connected to the output of the first register R 1  for storing the stop signal, and an output is connected to the input of the second register R 2 . This sets up a connection between the first and second registers R 1  and R 2 . The third and fourth registers R 3  and R 4  are, for example, D type flip-flop circuits well known to those skilled in the art. 
     The circuit C of FIG. 2 operates the same way as the circuit of FIG.  1 . The addition of the third and fourth registers R 3  and R 4  eliminating possible stability problems at the inputs of the master circuit  1  and slave circuit  2 . Stability problems are due to a change in states that occurs at active edges of the clock signal. 
     When a register R 1  or R 2  stores and provides an unstabilized signal during an active edge of the clock signal, the output of the register initially provides oscillations and then becomes stabilized on a logic state 0 or 1 in a random manner primarily determined by the internal construction of the register. This may influence operation of the circuit that follows the register. The third and fourth registers R 3  and R 4  thus limit the influence of the registers R 1  or R 2  on the master circuit  1  and the slave circuit  2 . 
     The second and fourth registers R 2  and R 4  produce delays during the transmission of the control signal. Arrangements must therefore be made for the slave circuit  2  to receive the control signal during two clock cycles of the second clock signal Ck 2 . This is done with a delay by one clock cycle of the second clock signal Ck 2  with respect to the circuit of FIG.  1 . 
     In relation to FIG. 3, the circuit C 1  comprises a master circuit  1 , a slave circuit  2 , first and second clock circuits H 1  and H 2 , first and fifth registers R 1  and R 5 , an inverter  3  and a logic gate  4 . The master circuit  1  is, for example, a state machine and the slave circuit  2  is, for example, a counter. The first and second clock circuits H 1  and H 2  respectively provide first and second clock signals Ck 1  and Ck 2  at an output. The frequencies of the clock signals are derived from two independent clock circuits. 
     The master circuit  1  has a clock input connected to the output of the first clock circuit H 1  for receiving the clock signal Ck 1 , and a control output for sending a control signal. The first register R 1  has a data input connected to the control output of the master circuit  1 . A clock input is connected to the output of the second clock circuit H 2  for receiving the second clock signal Ck 2 . The inverter  3  has an input connected to the output of the first register R 1 , and an output. The logic gate  4  has two inputs and one input. A first input is connected to the input of the first register R 1 , and a second input is connected to the output of the inverter  3 . 
     The fifth register R 5  has an input connected to the output of the logic gate  4 , a clock input is connected to the output of the second clock output H 2  for receiving the second clock signal Ck 2 , and an output. The slave circuit  2  comprises a data input connected to the output of the fifth register R 5 , and a clock input is connected to the output of the second clock circuit H 2  for receiving the second clock signal Ck 2 . The logic gate  4  is an AND type gate and the first and fifth registers are, for example, D type flip-flop circuits. 
     When the control signal sent by the master circuit is activated on an active edge of the clock signal Ck 1 , the first input of the logic gate  4  passes into a logic state 1. Furthermore, since the output of the first register R 1  is in a logic state 0, the output of the inverter is in the logic state 1. Therefore, the output of the logic gate  4  is in a logic state 1. 
     During a first active edge of the second clock signal Ck 2 , the register R 1  stores and provides the control signal to the input of the inverter  3 . The register R 5  stores and provides the logic signal  1  corresponding to the logic state of the output of the logic gate  4  to the control input of the slave circuit. During a second active edge of the second clock signal Ck 2 , the output of R 1  is in a logic state 1. Therefore, the output of the inverter is in a logic state 0. The fifth register R 5  stores and provides a logic state 0. Thus, the command is transmitted only during a clock cycle of the second clock signal Ck 2 . 
     The arrangement of FIG. 3 is particularly beneficial when the frequency of the clock signal Ck 1  is less than the frequency of the clock signal Ck 2 . Alternative embodiments are also possible. For example, the AND type logic gate  4  may be replaced by an OR type logic gate if the control signal is active in the low state. It must be noted that the previous embodiments also operate when the frequencies of the clock signals Ck 1  and Ck 2  are derived from the same clock circuit. Furthermore, although the value is lower, the frequencies of the clock signals may be identical or may be multiples of one another.