Abstract:
An array substrate is described. The array substrate with a polarity inversion of drive voltage signal in a plurality of data lines comprises a plurality of gate line sets being sequentially arranged, wherein each gate line set comprises two gate lines having an odd gate line and an even gate line respectively; a plurality of data line sets being sequentially arranged and vertically interlaced with the gate line sets, wherein each data line set comprises two data lines having an odd data line and an even data line respectively; wherein a plurality of sub-pixels are sequentially disposed between two adjacent gate line sets, connection positions of a portion of sub-pixels to the odd gate line and the even gate line in one gate line set respectively are changed in a predetermined amount of data line spaced apart.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    Field of Invention 
         [0002]    The present invention relates to a technical field of a liquid crystal display (LCD) apparatus, LCD panel, LCD array substrate and driving method using the same, and more particularly to a thin film transistor (TFT) LCD apparatus, TFT-LCD panel, TFT-LCD array substrate and driving method using the same. 
         [0003]    Description of Prior Art 
         [0004]    Conventionally, a manufacturing cost reduction is a critical issue of the LCD&#39;s manufacturing procedure. A data line sharing (DLS) mechanism is commonly used wherein the number of gate lines is doubled and the number of data lines is halved to diminish the amount of source driver for thus lowering the costs. 
         [0005]    Regarding a driving method of conventional LCD panel, since the switch frequency of the data line polarity using a column inversion is lower, the power consumption of the driving manner is reduced and widely used.  FIG. 1  is a schematic view of a TFT-LCD with a data line sharing (DLS) mechanism and column inversion in the prior art. G_ 1  to G_ 8  represent the serial numbers of the gate lines and D_ 1  to G_ 5  represent the serial numbers of the data lines. Each region enclosed by a dashed line is defined as a sub-pixel wherein the positive and negative signs in the sub-pixels represent the polarities of the driving voltage. The sub-pixel polarity of one data line in a column is opposite the sub-pixel polarity in the left or right data line related the one data line, which is defined as a column inversion manner. 
         [0006]      FIG. 1  is a conventional red-green-blue (RGB) structure. When the RGB structure is operated with the DLS mechanism, the electrical potential of common electrode E_cm will drift in some color mixing frames, e.g. cyan color frame formed by green and blue colors, thereby causing poor display quality, e.g. crosstalk, since the capacitor coupling is formed by liquid crystal capacitance and storage capacitance between sub-pixel electrode E_pixel and common electrode E_cm.  FIG. 2 a    is a schematic signal waveform of the data lines in  FIG. 1  when the display panel is in a color-mixing status. In a cyan color frame formed by green and blue colors, the level of common electrode E_cm is 7V (voltage) wherein the positive polarity voltage of the gray level L 255  is 14V and the negative polarity voltage is 0V. In  FIGS. 1 and 2 , data line D_ 2  is composed of green sub-pixels G and blue sub-pixels B in a direct current signal waveform with a negative polarity voltage 0V. The data line D_ 3  has positive polarity wherein when the odd data lines are switched on, the voltage written into the red sub-pixel is common voltage 7V and the even data lines are switched on, the voltage written into the green sub-pixel is 14V. In the data line D_ 4 , when the odd data lines are switched on, the voltage written into the blue sub-pixel is 0V and the even data lines are switched on, the voltage written into the red sub-pixel is common voltage 7V. However, the waveform of data lines D_ 3  and D_ 4  from low level to high level or vice versa are similar, as shown in dashed line regions. In this case, when the data signal is written to the sub-pixel electrode E_pixel, the liquid crystal capacitor C_lc and storage capacitor C_st related to the common electrode E_cm generates a coupling capacitance therebetween so that electrical potential of the common electrode E_cm is drifted. In  FIG. 2 a   , when the signal levels in data lines D_ 3  and D_ 4  are changed from low to high, the common voltage in the whole column sub-pixels pulls high. On the contrary, when the signal levels in data lines D_ 3  and D_ 4  are changed from high to low, the common voltage in the whole column sub-pixels pulls low. Thus, the changed common voltage is unstable, which may downgrade the display quality due to crosstalk effect. As shown in  FIG. 2 b   , when a white display region  200  is added to a color-mixing background region, the brightness of the background regions  201  in the lateral sides of the white display region  200  is different from the brightness in the region  202 . 
         [0007]      FIG. 3  is a schematic view of a conventional display panel with white, red, green and blue (WRGB) sub-pixels. When the WRGB display panel shown a pure color,  FIG. 3  has the same problem as  FIG. 2 b   , thereby causing crosstalk. As shown  FIG. 4 , when a white display region  400  is added to a color-mixing background region, the brightness of the background regions  401  in the lateral sides of the white display region  200  is different from the brightness in the region  402 . 
       SUMMARY OF THE INVENTION 
       [0008]    Therefore, one objective of the present invention is to provide a thin film transistor (TFT) LCD apparatus, TFT-LCD panel, TFT-LCD array substrate and driving method using the same to solve the problem of crosstalk. 
         [0009]    Based on the above objective, the present invention sets forth an array substrate with a polarity inversion of drive voltage signal in a plurality of data lines. The array substrate comprises: a plurality of gate line sets being sequentially arranged, wherein each gate line set comprises two gate lines which are composed of an odd gate line and an even gate line respectively; a plurality of data line sets being sequentially arranged and vertically interlaced with the gate line sets, wherein each data line set comprises two data lines which are composed of an odd data line and an even data line respectively; wherein a plurality of sub-pixels are sequentially disposed between two adjacent gate line sets, connection positions of a portion of sub-pixels to the odd gate line and the even gate line in one gate line set respectively are changed in a predetermined amount of data line spaced apart so that the portion of sub-pixels in each same row are connected to the odd gate line and the even gate line respectively in the one gate line set, and wherein each sub-pixel is connected to one gate line and one data line respectively by way of a switch unit, and a polarity of the drive voltage signal of the sub-pixels with same color type in two adjacent data lines is inverted each other. 
         [0010]    In one embodiment, an array substrate with a polarity inversion of drive voltage signal in a plurality of data lines comprises: a plurality of gate line sets being sequentially arranged, wherein each gate line set comprises two gate lines which are composed of an odd gate line and an even gate line respectively; a plurality of data line sets being sequentially arranged and vertically interlaced with the gate line sets, wherein each data line set comprises two data lines which are composed of an odd data line and an even data line respectively; wherein a plurality of sub-pixels are sequentially disposed between two adjacent gate line sets, connection positions of a portion of sub-pixels to the odd gate line and the even gate line in one gate line set respectively are changed in a predetermined amount of data line spaced apart so that the portion of sub-pixels in each same row are connected to the odd gate line and the even gate line respectively in the one gate line set, and a polarity of the drive voltage signal of the sub-pixels with same color type in two adjacent data lines is inverted each other. 
         [0011]    Preferably, each sub-pixel is connected to one gate line and one data line respectively by way of a switch unit. 
         [0012]    Preferably, the switch unit is a thin film transistor comprising a gate electrode connected to one gate line, a source electrode connected to one data line, and a drain electrode connected to one sub-pixel. 
         [0013]    Preferably, a polarity of the drive voltage signal of the sub-pixels with same color type in two adjacent data lines is inverted each other. 
         [0014]    Preferably, the sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, which are sequentially arranged. 
         [0015]    The present invention can prevent the electrical potential of the common electrode from drifting due to the coupling effect of the sub-pixel in order to increase the stability of electrical potential of the common electrode in the DLS mechanism and improve the display quality. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a schematic view of an LCD with a conventional data line sharing (DLS) mechanism and column inversion; 
           [0017]      FIG. 2 a    is a schematic signal waveform of the data lines in  FIG. 1  when the display panel is in a color-mixing status; 
           [0018]      FIG. 2 b    is a schematic view of a display region with the color-mixing status in  FIG. 2   a;    
           [0019]      FIG. 3  is a schematic view of a conventional display panel with white, red, green and blue (WRGB) sub-pixels; 
           [0020]      FIG. 4  is a schematic view of crosstalk between data lines on the display panel; 
           [0021]      FIG. 5  is a schematic view of an LCD panel according to one embodiment of the present invention; 
           [0022]      FIG. 6 a    is a schematic signal waveform of the data lines in  FIG. 5  when the display panel is in the color-mixing status according to one embodiment of the present invention; 
           [0023]      FIG. 6 b    is a schematic view of a display region with the color-mixing status in  FIG. 6 a    according to one embodiment of the present invention; 
           [0024]      FIG. 7  is a schematic view of an LCD panel according to another embodiment of the present invention; and 
           [0025]      FIG. 8  is a schematic signal waveform of the data lines in  FIG. 7  when the display panel is in the color-mixing status according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0026]    The following embodiments refer to the accompanying drawings for exemplifying specific implementable embodiments of the present invention. Furthermore, directional terms described by the present invention, such as upper, lower, front, back, left, right, inner, outer, side, etc., are only directions by referring to the accompanying drawings, and thus the used directional terms are used to describe and understand the present invention, but the present invention is not limited thereto. 
         [0027]    In the drawings, the same reference symbol represents the same or a similar component. 
         [0028]    Please refer to  FIG. 5 , which is a schematic view of an LCD panel according to one embodiment of the present invention. The LCD panel includes five gate line sets, but not limited, in a sequentially horizontal arrangement and five data lines, but not limited, in a sequentially vertical arrangement. Each gate line set includes two gate lines, e.g. G_ 1  and G_ 2 , G_ 3  and G_ 4 , G_ 5  and G_ 6 , G_ 7  and G_ 8 , and G_ 9  and G_ 10  wherein the odd gate lines are G_ 1 , G_ 3 , G_ 5 , G_ 7  and G_ 9  and the even gate lines are G_ 2 , G_ 4 , G_ 6 , G_ 8  and G_ 10 . The data lines include odd data lines D_ 1 , D_ 3  and D_ 5  and even data lines D_ 2  and D_ 4 . A plurality of red sub-pixels R, green sub-pixels G and blue sub-pixels B are sequentially disposed between two adjacent gate line sets. In  FIG. 5 , the red sub-pixels are electrically connected to the gate lines G_ 3  and G_ 4  and one side of the data line D_ 1 . For an example of data line D_ 1 , the red sub-pixel R is connected to gate line G_ 3  and data line D_ 1  by way of a switch unit, e.g. thin film transistor T. The gate electrode E_gate of TFT is connected to gate line G_ 3 , the source electrode E_source of TFT is connected to data line D_ 1 , and drain electrode E_drain of TFT is connected to red sub-pixel R. The rest of sub-pixels in  FIG. 5  are electrically connected to gate lines and data lines respectively based on the red sub-pixel with gate line G_ 3  and data line D_ 1 . In the interlaced node of the gate line set G_ 3  and G_ 4  and data line D_ 2 , the sub-pixel in the left-hand side of data line D_ 2  is connected to the gate line G_ 3  and the sub-pixel in the right-hand side of data line D_ 2  is connected to the gate line G_ 4 . In other words, two adjacent gate lines in the gate line set are interlaced in at least one data line interval, e.g. every other data line. That is, the connection positions of the two adjacent gate lines are exchanged once in every one data line spaced apart. For example, the gate line set G_ 1  and G_ 2  includes an interlaced node between data lines D_ 1  and D_ 2 . When passing D_ 1 , G_ 1  is disposed above the G_ 2 , and when passing D_ 2 , G_ 2  is disposed above the G_ 1 . 
         [0029]      FIG. 6 a    is a schematic signal waveform of the data lines in  FIG. 5  when the display panel is in the color-mixing status according to one embodiment of the present invention. Similar to  FIG. 2 a   , the data line D_ 2  in  FIG. 5  is composed of green sub-pixels G and blue sub-pixels B in a direct current signal waveform with a negative polarity voltage 0V. The data line D_ 3  includes positive polarity voltage wherein when the odd data lines are switched on, the voltage written into the green sub-pixel is voltage 14V (gray level L 255 ) and the even data lines are switched on, the voltage written into the red sub-pixel is common voltage 7V (gray level LO) under a cyan color frame. Similarly, in the data line D_ 4 , when the odd data lines are switched on, the voltage written into the blue sub-pixel is negative polarity voltage 0V (gray level L 255 ) and the even data lines are switched on, the voltage written into the red sub-pixel is common voltage 7V, e.g. negative polarity voltage. 
         [0030]    In  FIG. 6 a   , the signal voltages of the data lines D_ 2  and D_ 3  are switched at the same time but two switch directions of the signal voltages is opposite wherein one switch direction is from high to low and the other is from low to high. The coupling effect between liquid crystal C_lc and storage capacitance C_st along the two switch directions is formed but the capacitance coupling effect along the two switch directions is balanced due to counteraction. Thus, the electrical potential of the common electrode E_cm will not be drifted to be stable, thereby improving the display quality of the LCD panel. As shown in  FIG. 6 b   , when a white frame  600  is added to a color-mixing background, the background regions  601  around the white frame  600  has the same brightness. 
         [0031]    Please refer to  FIG. 7 , which is a schematic view of an LCD panel according to another embodiment of the present invention. The LCD panel includes five gate line sets, but not limited, in a sequentially horizontal arrangement and five data lines, but not limited, in a sequentially vertical arrangement. Each gate line set includes two gate lines, e.g. G_ 1  and G_ 2 , G_ 3  and G_ 4 , G_ 5  and G_ 6 , G_ 7  and G_ 8 , and G_ 9  and G_ 10 . The odd gate lines are G_ 1 , G_ 3 , G_ 5 , G_ 7  and G_ 9  and the even gate lines are G_ 2 , G_ 4 , G_ 6 , G_ 8  and G_ 10 . The data lines include odd data lines D_ 1 , D_ 3  and D_ 5  and even data lines D_ 2  and D_ 4 . A plurality of red sub-pixels R, green sub-pixels G and blue sub-pixels B are sequentially disposed between two adjacent gate line sets. In  FIG. 7 , the red sub-pixels are electrically connected to the gate lines G_ 3  and G_ 4  and one side of the data line D_ 1 . For an example of data line D_ 1 , the red sub-pixel R is connected to gate line G_ 3  and data line D_ 1  by way of a switch unit, e.g. thin film transistor T. The gate electrode E_gate of TFT is connected to gate line G_ 3 , the source electrode E_source of TFT is connected to data line D_ 1 , and drain electrode E_drain of TFT is connected to red sub-pixel R. The rest of sub-pixels in  FIG. 7  are electrically connected to gate lines and data lines respectively based on the red sub-pixel with gate line G_ 3  and data line 
         [0032]    D_ 1 . The LCD panel in  FIG. 7  is similar to that in  FIG. 5 . In the interlaced node of the gate line set G_ 3  and G_ 4  and data line D_ 2 , the sub-pixel in the left-hand side of data line D_ 2  is connected to the gate line G_ 4  and the sub-pixel in the right-hand side of data line D_ 2  is connected to the gate line G_ 3 . In the interlaced node of the gate line set G_ 3  and G_ 4  for data lines D_ 3  and D_ 4 , the sub-pixels in the left-hand side of data line D_ 3  and D_ 4  are connected to the gate line G_ 3  and the sub-pixels in the right-hand side of data lines D_ 3  and D_ 4  are connected to the gate line G_ 4 . In other words, two adjacent gate lines in the gate line set are interlaced in every two data lines for data lines D_ 3  and D_ 4  in  FIG. 7 . That is, the positions of the two adjacent gate lines are exchanged once in every two data lines spaced apart. For example, the gate line set G_ 1  and G_ 2  includes an interlaced node between data lines D_ 1  and D_ 2 . When passing D_ 1  and D_ 2 , G_ 1  is disposed above the G_ 2 . When G_ 1  and G_ 2  are between D_ 2  and D_ 3 , an interlaced mode is formed. When passing D_ 3  and D_ 4 , G_ 2  is disposed above the G_ 1 . When G_ 1  and G_ 2  are between D_ 4  and D_ 5 , another interlaced mode is formed. 
         [0033]      FIG. 8  is a schematic signal waveform of the data lines in  FIG. 5  when the display panel is in the color-mixing status according to one embodiment of the present invention. The data lines D_ 2  and D_ 4  are composed of blue sub-pixels B and white sub-pixels W in a direct current signal waveform with a negative polarity voltage 7V (gray level L 0 ). The data line D_ 1  has positive polarity voltage wherein when the odd data lines are switched on, the voltage written into the red sub-pixel is 14V and the even data lines are switched on, the voltage written into the green sub-pixel is 7V. The data line D_ 3  has positive polarity voltage wherein when the odd data lines are switched on, the voltage written into the green sub-pixel is common voltage 7V and the even data lines are switched on, the voltage written into the red sub-pixel is 14V. In  FIG. 8 , the signal voltages of the data lines D_ 1  and D_ 3  are switched at the same time but two switch directions of the signal voltages is opposite wherein one switch direction is from high to low and the other is from low to high. The coupling effect between liquid crystal C_lc and storage capacitance C_st along the two switch directions is formed but the capacitance coupling effect along the two switch directions is balanced due to counteraction. The electrical potential of the common electrode E_cm will not be drifted in a stable status, thereby improving the display quality of the LCD panel. 
         [0034]    The present invention uses the array substrate in  FIG. 5  and  FIG. 7  in the LCD apparatus and LCD panel for preventing the electrical potential of the common electrode from drifting due to the coupling effect between the sub-pixel electrodes in order to improve the display quality of the LCD apparatus. 
         [0035]    The present invention can prevent the electrical potential of the common electrode from drifting due to the coupling effect of the sub-pixel in order to increase the stability of electrical potential of the common electrode in the DLS mechanism and improve the display quality. 
         [0036]    As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrative rather than limiting of the present invention. It is intended that they cover various modifications and similar arrangements be included within the spirit and scope of the present invention, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.