Abstract:
Current feedback amplifiers circuits that generate common mode (CM) and/or differential mode (DM) currents are provided herein. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Description:
PRIORITY CLAIMS  
       [0001]     This application is a continuation of U.S. patent application Ser. No. 11/593,288, filed Nov. 6, 2006, which is a continuation of U.S. Pat. No. 7,132,860, filed Mar. 17, 2005, which application claims priority under 35 U.S.C. 119(e) to the following provisional applications: U.S. Provisional Patent Application No. 60/611,771 filed Sep. 21, 2004; and U.S. Provisional Patent Application No. 60/554,150, filed Mar. 18, 2004. Each of the above applications is incorporated herein by reference.  
       RELATED APPLICATIONS  
       [0002]     This application is related to the following commonly invented and commonly assigned patents: U.S. Pat. No. 7,132,859, entitled “Common-Mode Current Feedback Amplifiers,” filed Mar. 17, 2005; and U.S. Pat. No. 7,116,132, entitled “Current Feedback Amplifiers with separate Common-Mode and Differential-Mode Inputs,” filed Mar. 17, 2005. Each of the above applications is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0003]     Embodiments of the present invention relate to current feedback amplifiers, including common-mode current feedback amplifiers, differential-mode current feedback amplifiers, a combinations thereof.  
       BACKGROUND  
       [0004]      FIG. 1A  is a macro level diagram of a basic current feedback amplifier (CFA)  100 .  FIG. 1B , which is a high level circuit diagram, will be used to describe the basic operation of the current feedback amplifier (CFA)  100 , which can be modeled as two ideal voltage buffers  106  and  108 , a complementary pair of current mirrors  110  and  112  and feedback and gain resistors R F  and R G . When a voltage is applied to the non-inverting input  102 , it is immediately buffered to the inverting input  104 . Assuming a standard non-inverting op-amp configuration, this voltage causes a change in the current flowing through the feedback and gain resistors R F  and R G . The input voltage buffer  106  must supply this current; therefore the current must flow through the current mirrors  110  and  112  and is duplicated, causing a ΔI to be applied to a high-impedance node  114 . This current, flowing into the high impedance node  114 , causes a change in voltage that is then transferred to the CFA output  116  by the second buffer  108 . The key thing to focus on in this case is that the amplifier&#39;s operation depends on correctly sensing and mirroring the change in current caused by the initial change in input voltage. This creates the “current feedback” nature of the amplifier.  
         [0005]     Referring now to  FIG. 2 , a symmetrical pair of CFAs, labeled  100   a  and  100   b , are hooked up in a standard differential gain configuration to form a differential amplifier circuit  200 . Standard analysis using the concept of half-circuits leads to the ability to analyze the differential circuit in terms of two signal paths, one for differential-mode signals and one for common-mode signals (hereafter referred to as DM and CM, respectively). Any arbitrary input to the amplifier circuit  200  can be expressed as a sum of DM and CM components. Half-circuits  300   a  and  300   b  are shown explicitly in  FIG. 3 .  
         [0006]     It is immediately apparent that the DM and CM signal paths will have different voltage gains and different loading effects, and that therefore optimizing the amplifier circuit  200  for one of the paths will inevitably compromise optimal performance on the other path. More generally it may be desirable to send completely different signals on the DM and CM signal paths. It may also be desirable to cancel out part or all of either the CM or DM signals. Therefore, the ability to tune the CM and DM paths independently is desirable.  
       SUMMARY  
       [0007]     Current feedback amplifiers (CFAs) are beneficial because they provide for a large slew rate at small supply currents, and because their bandwidths are insensitive to closed-loop gains. Embodiments of the present invention are directed to CFA circuits that generate CM currents. Embodiments of the present invention are also related to CFA circuits that generate DM currents. Further embodiments of the present invention are related to fully differential CFA circuits with separate CM and DM inputs. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and insensitive bandwidth, with independent control of DM and CM signals.  
         [0008]     Further embodiments, and the features, aspects, and advantages of the present invention will become more apparent from the detailed description set forth below, the drawings and the claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1A  is a macro level diagram of a basic CFA.  
         [0010]      FIG. 1B  is a high level circuit diagram that is useful for describing the basic operation of a CFA.  
         [0011]      FIG. 2  is a high level circuit diagram showing a symmetrical pair of CFAs hooked up in a standard differential gain configuration to form a differential configuration of two amplifiers.  
         [0012]      FIGS. 3A and 3B  are high level circuit diagrams of two half-circuits that provide the ability to analyze the differential circuit of  FIG. 2  in terms of two signal paths, one for DM signals and one for CM signals.  
         [0013]      FIGS. 4A and 4B  are high level circuit diagrams illustrating common-mode (CM) current feedback amplifier circuits that amplify common-mode (CM) signals using the generation of CM currents.  
         [0014]      FIG. 5  is a high level circuit diagram illustrating differential-mode (DM) current feedback amplifier circuit that amplifies differential-mode (DM) signals using the generation of DM currents.  
         [0015]      FIG. 6  shows circuitry implementing the diagram of  FIG. 4A  using bipolar transistors, according to an embodiment of the present invention.  
         [0016]      FIG. 7  shows circuitry implementing the diagram of  FIG. 5  using bipolar transistors, according to an embodiment of the present invention.  
         [0017]      FIG. 8  shows circuitry implementing a fully differential current feedback amplifier (CFA) circuit with separate common-mode (CM) and differential-mode (DM) inputs, according to an embodiment of the present invention.  
         [0018]      FIG. 9  shows circuitry for implementing a partial cancellation differential-mode (DM) current feedback amplifier circuit, according to an embodiment of the present invention.  
         [0019]      FIGS. 10A-10D  show various circuitry for generating sums and differences of current using current mirrors.  
         [0020]      FIG. 11  shows circuitry that generates CM and DM currents using multiple buffer currents, but with less current mirrors than shown in  FIG. 8 , according to an embodiment of the present invention.  
         [0021]      FIG. 12  shows circuitry for implementing a hybrid CFA/VFA, according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0022]     As mentioned above, it is a desired to have the ability to tune the CM and DM paths of an amplifier circuit independently. One possible way to address this issue is with independent compensation of DM and CM signals, as described in U.S. patent application Ser. No. 10/657,447 (Attorney Docket No. ELAN-01098US1), entitled “Common-Mode and Differential-Mode Compensation for Operational Amplifier Circuits,” filed Sep. 8, 2003, which is incorporated by reference herein. The aforementioned Patent Application addresses the problem of CM vs. DM stability, but does not explicitly provide for separate control of the DM &amp; CM voltages.  
         [0023]     A more effective and traditional scheme is to use a fully differential op-amp architecture. An example of such an approach would be the standard folded-cascode voltage-feedback differential amplifier. However, the standard folded-cascode voltage-feedback differential amplifier does not provide the unique advantages of a CFA architecture, such as insensitivity of bandwidth to closed-loop gain and large slew rate at small supply currents.  
         [0024]     In order to make a CM or DM current-feedback loop, by definition there should exist the ability to generate currents that are proportional to either the sum or difference of the input signals. These currents then become the inputs to the current mirrors of a CFA configuration. Adding and subtracting currents is possible with the use of parallel currents and current mirrors.  FIGS. 4A and 5  are high level circuit diagrams illustrating how the CM and DM currents can be generated, in accordance with embodiments of the present invention. Implementations of  FIGS. 4A and 5  are discussed below, respectively, with reference to  FIGS. 6 and 7 . Other implementations are also within the spirit and scope of the present invention.  
         [0025]     Referring now to  FIG. 4A , input voltage buffers  406   a  and  406   b  of two CFAs  400   a  and  400   b  are configured such that supply currents are split into two equal parts. The CFA  400   a  includes an input voltage buffer  406   a , a pair of current mirrors  410   a  and  412   a , and an output buffer  408   a . When a voltage is applied to a non-inverting input  402   a  of the input voltage buffer  406   a , it is immediately buffered to an inverting input  404   a . A feedback resistor R F  connects the OUTA to IN−A (in a similar fashion as shown in  FIG. 1B ), and a feedback resistor R F  connects the OUTB to IN−B. Assuming a standard non-inverting op-amp configuration, this voltage causes a change in the current flowing through the feedback resistors, and optional gain resistors. The input voltage buffer  406   a  must supply this current; therefore it must flow through current mirrors  410   a  and  412   a  and is duplicated, causing a ΔI to be applied to a high-impedance node  414   a . This current, flowing into the high impedance node  414   a , causes a change in voltage that is then transferred to a first output  416   a  (OUTA) by an output buffer  408   a . CFA  400   b , which includes elements labeled in a similar manner (but with the suffix “b” instead of “a”) operates in a similar manner to CFA  400   a . Also shown in  FIG. 4A  are optional gain resistors R G .  
         [0026]     By wiring ½ of the supply current I A  of buffer  406   a  in parallel with ½ of the supply current I B  from the opposite buffer  406   b , a CM current is generated. Explicitly, with the inputs denoted A and B, and the current generated by the two inputs buffers  406   a  and  406   b  labeled I A  and I B , respectively, then the current sensed by each of the CFA&#39;s  400   a  and  400   b  can be expressed as I CM =½(I A +I B ). This is the definition of a CM signal; if A and B are equal then I CM =I A =I B , whereas if A and B are DM, that is to say equal in magnitude but opposite in phase, I A =−I B  and I CM =0. Accordingly, the circuit of  FIG. 4A  admits and amplifies CM signals, and rejects DM signals. The various currents generated by each input buffer  406   a  and  406   b , such as ½ (I A +I B ), are proportional to a difference between an input voltage signal provided to a non-inverting input of the amplifier circuit (formed by the input buffer) and a fraction of its associated output voltage signal.  
         [0027]     The circuit of  FIG. 4A  shows two single-ended inputs, labeled IN+A and IN+B, that will in general not be equal to each other. Therefore, there may be a DM signal that needs to be cancelled out in order to provide CM operation. However, a CM input signal can be guaranteed by shorting together input nodes  402   a  (IN+A) and  402   b  (IN+B). By doing so, the two independent inputs are replaced with a single input which is inherently CM. In such a case, the currents and voltages of the CFA  400   a  and the CFA  400   b  would be identical, and therefore portions of the circuit can be eliminated without loss of functionality. For example, the input buffer  406   b  can be eliminated. This may be desirable in order to reduce the design&#39;s complexity and cost. The resulting circuit, with input buffer  406   b  eliminated, is shown in  FIG. 4B .  
         [0028]     Referring now to FIG.,  5 , in a similar manner as in  FIG. 4A , input voltage buffers  506   a  and  506   b  of two CFAs  500   a  and  500   b  are configured such that supply currents are split into two equal parts. The various currents generated by each input buffer  506   a  and  506   b , such as ½I A , are proportional to a difference between an input voltage signal provided to a non-inverting input of the amplifier circuit (formed by the input buffer) and a fraction of its associated output voltage signal.  FIG. 5  demonstrates the generation of DM currents by using current mirrors to invert ½ of the buffer current before it is added together. This means that the current sensed can now be expressed as I DM =½(I A −I B ). When A and B are CM, then I DM  will equal zero, whereas when A and B are DM, I A =−I B  and therefore I DM =I A =−I B . Accordingly, the circuit of  FIG. 5  admits and amplifies DM signals, and rejects CM signals. In the specific embodiment shown in  FIG. 5 , eight current mirrors  510   a ,  520   a ,  512   a ,  522   a ,  510   b ,  520   b ,  522   b  and  512   b  are used. A first group of the current mirrors (i.e., current mirrors  510   a ,  512   a ,  510   b  and  512   b ) are used for adding currents together, and providing the added currents to high impedance nodes (i.e., nodes  514   a  and  514   b ). A second group of the current mirrors ( 520   a ,  522   a ,  520   b  and  522   b ) are used to provide mirrored versions of currents to the first group of current mirrors where they can be added as appropriate. A feedback resistor R F  (not shown, for simplicity) connects the OUTA to IN−A (in a similar fashion as shown in  FIGS. 1B and 4A ), and a feedback resistor R F  (not shown, for simplicity) connects the OUTB to IN−B.  
         [0029]      FIGS. 6 and 7  show implementations, according to embodiments of the present invention, of the concepts of  FIGS. 4A and 5 , respectively. Bipolar transistors and non-degenerate current mirrors are used for simplicity. However, it is within the scope of the present invention that the bipolar transistors shown in the Figures can be replaced with other transistors, such as but not limited to, metal-oxide semiconductor (MOS), metal semiconductor (MES) or field effect (FET) transistors with similar behavior. Additionally, the use of alternative types of current mirrors are within the spirit and scope of the present invention, as would be appreciated by one or ordinary skill in the art.  
         [0030]     Referring to  FIG. 6 , the input voltage buffer  406   a  is shown as including NPN transistor Q 2   a  and PNP transistor Q 4   a  having common bases forming the non-inverting input IN+A of the input voltage buffer  406   a , which is applied to the non-inverting input IN+A of the CFA  400   a . The NPN transistor Q 2   a  has its collector connected to a power supply rail Vcc, and its emitter connected through a current source I 2   a  to a power supply rail Vee. The PNP transistor Q 4   a  has its collector connected to the power supply rail Vee, and its emitter connected through a current source I 1   a  to the power supply rail Vcc. The emitters of NPN transistor Q 8   a  and PNP transistor Q 12   a  form the output  404   a  of the input voltage buffer  406   a , which is applied to the inverting input IN−A of the CFA  400   a . NPN transistor Q 8   a  and PNP transistor Q 12   a  are connected in an emitter follower configuration with the collector of transistor Q 8   a  connected to an input terminal of the current mirror  410   a , and the collector of transistor Q 12   a  connected to an input terminal of the current mirror  412   a . The outputs of the current mirrors  410   a  and  412   a  are connected to form the gain node  414   a . The gain node  414   a  is connected to an input of the output buffer  408   a . The output  416   a  of the output buffer  408   a  forms the output OUTA of the CFA  400   a.    
         [0031]     The input voltage buffer  406   a  also includes NPN transistor Q 6   a  and PNP transistor Q 10   a , which are connected in a similar manner as transistors Q 8   a  and Q 12   a . More specifically, NPN transistor Q 6   a  and PNP transistor Q 10   a  are also connected in an emitter follower configuration, with their emitters connected to the emitters of transistors Q 8   a  and Q 12   a , which form the inverting input IN−A of the CFA  400   a . However, rather than the collectors of transistors Q 6   a  and Q 10   a  being connected, respectively, to the inputs of current mirrors  410   a  and  412   a , the collector of transistor Q 6   a  is connected to the input of current mirror  410   b , and the collector of transistor Q 10   a  is connected to the input of current mirror  412   b . In the above manner, the collector of transistor Q 8   a  provides ½I A  to the input of current mirror  410   a , which also receives ½I B  provided by the collector of transistor Q 6   b . The collector of transistor Q 6   a  provides ½I A  to the input of current mirror  410   b , which also receives ½I B  provided by the collector of transistor Q 8   b.    
         [0032]     The input voltage buffer  406   b , which provides the non-inverting input IN+B and the inverting input IN−B, includes a similar topology as buffer  406   a . Accordingly, buffer  406   b  is labeled in the same manner as buffer  406   a  (except the suffix “a” is replaced with the suffix “b”), and thus need not be described in additional detail. As mentioned above, alternative topologies for the buffers can be used, while still being within the scope of the present invention.  
         [0033]     The current mirror  410   a  is shown as including PNP transistors Q 14   a  and Q 16   a  having their bases connected together and their emitters connected together. The collector of transistor Q 14   a , which is connected to its base, forms an input of the current mirror  410   a . The collector of transistor Q 16   a  forms an output of the current mirror  410   a . In this embodiment, the input of the current mirror  410   a  receives current ½I A  from input voltage buffer  406   a , and current ½I B  from input voltage buffer  406   b , and thus receives ½(I A +I B ), and provides that current to high impedance node  414   a . The other current mirrors  410   b ,  412   a  and  412   b  are shown as being implemented in a similar manner, and thus need not be described in detail. As mentioned above, alternative topologies for the current mirrors can be used, while stilling being within the scope of the present invention. The operation of the circuit of  FIG. 6  was described above in the description of  FIG. 4A .  
         [0034]     Referring now to  FIG. 7 , the input voltage buffers  506   a  and  506   b  are shown as being implemented in a similar manner as buffers  406   a  and  406   b  in  FIG. 6 , and are thus labeled in a similar manner. Further, current mirrors  510   a ,  512   a ,  510   b , and  512   b  are shown as being implemented in a similar manner as currents mirrors  410   a ,  412   a ,  410   b  and  412   b , and thus are labeled in a similar manner. The remaining current mirrors  520   a ,  522   a ,  520   b  and  522   b  are also shown as being implemented in a similar manner, and thus need not be described in additional detail. The operation of the circuit of  FIG. 7 , was described above in the description of  FIG. 5 .  
         [0035]     Embodiments of the present invention are also directed to combinations of the CM and DM types of current generators that were described above with reference to  FIGS. 4-7 . These current generators can be combined, in accordance with embodiments of the present invention, to obtain whatever mix of CM and DM control desired. Below, there is a discussion of specific architectures that can be obtained, in accordance with embodiments of the present invention.  
         [0000]     Architectures and Implementations:  
         [0036]     Embodiments of the present invention are also directed to architectures that include combinations of current feedback, voltage feedback, CM and DM signals. Embodiments of the present invention are also directed to implementations of such architectures. In the implementations described below, bipolar transistors are shown. However, alternative types of transistors, such as but not limited to, metal-oxide semiconductor (MOS) or metal semiconductor (MES) transistors with similar behavior, can be used, and are thus within the spirit and scope of the present invention, as would be appreciated by one or ordinary skill in the art. As with  FIGS. 5-7 , for simplicity, the external feedback and gain resistors are not shown in  FIGS. 8-10 .  
         [0000]     The Fully Differential CFA:  
         [0037]     By implementing two independent input stages, one using the CM current-generating strategy and the other using the DM current generator strategy, the generated currents can be added together to create classic fully differential functionality, where the DM and CM can be independently and simultaneously controlled.  
         [0038]      FIG. 8  demonstrates a straightforward implementation of a fully differential CFA circuit, including DM input buffers  806   a  and  806   b , output buffers  808   a  and  808   b , current mirrors  810   a ,  812   a ,  820   a ,  822   a ,  810   b ,  812   b ,  820   b  and  822   b , and an independent CM input buffer  806   c . The input buffers&#39; supply current is explicitly duplicated by the use of parallel output devices, and the signal-inverting current mirrors are explicit and separate from the gain-stage mirrors of the rest of the amplifier. Note the use of simple current mirrors and buffers, but of course actual designs might use fancier topologies such as degenerated Wilson mirrors, or mirrors using emitter inputs and both sexes of transistor, etc.  
         [0039]     As mentioned above in the discussion of  FIGS. 4A and 4B , a CM input signal can be guaranteed by shorting together input nodes  402   a  and  402   b . By doing so, the two independent inputs are replaced with a single input which is inherently CM. In such a case, the currents and voltages of the CFA  400   a  and the CFA  400   b  would be identical, and therefore portions of the circuit can be eliminated without loss of functionality to reduce the design&#39;s complexity and cost (e.g., in  FIG. 4A , input buffer  406   b  can be eliminated). The fully differential architecture of  FIG. 8  demonstrates this principle in operation. The input labeled “IN_CM” goes into the buffer  806   c , which provides identical (and thus, CM) currents into both sides of the circuit. CM feedback is provided using current feedback resistors R F , which presents the output of buffer  806   c  with the average of the two output voltages (outputs of buffers  808   a  and  808   b ). Meanwhile, differential signals are provided by the input buffers  806   a  and  806   b  together with current mirrors  810   a ,  812   a ,  810   b  and  822   b . The output of this circuit will be a sum of the DM and CM signals: (OUTA−OUTB)=GAIN_DM*(IN+DM−IN−DM); and ½(OUTA+OUTB)=GAIN_CM*(IN_CM), where GAIN_DM and GAIN_CM are the closed-loop gains of the differential and common mode feedback loops, respectively. The GAIN_DM and GAIN_CM are set by feedback resistors R F  and optional gain resistor R G .  
         [0000]     The “Partially Cancelled” CFA:  
         [0040]     By using the scheme of  FIG. 5 , but not canceling the current 100%, the CM current signal can be attenuated with respect to the DM signal, in accordance with an embodiment of the present invention. For example, if the current mirrors used to invert the signal in  FIG. 5  were to have a current gain of 2:1, rather than 1:1, then the canceling signal would be equal to ½ of ½ the input buffer current, and I total (A)=½I A −¼I B =¾I DM +¼I CM . Therefore, the effective transconductance and gain of the DM will about three times as much as the CM. If independent control of the CM is not required and the desire is simply to damp out an undesired CM signal, this scheme (an embodiment of which is shown in  FIG. 9 ) is simpler and less costly to implement than the fully differential strategy mentioned above. Note that it is possible to just as easily implement partial CM so that the DM is attenuated with respect to the CM.  
         [0041]     Referring now to  FIG. 9 , the partial cancellation embodiment is shown as including input buffers  906   a  and  906   b , multiple output current mirrors  910   a ,  910   b ,  912   a  and  912   b , and output buffers  908   a  and  908   b .  FIG. 9  demonstrates an embodiment whereby the differential current is generated without the need for separate buffer output devices and current mirrors, thus saving component count and overall cost. Instead, the main gain mirrors of the amplifier, which now have multiple outputs, perform the task of duplicating and inverting the supply signal. The potential drawback to this embodiment is that the input currents to the gain mirrors of each amplifier are now coupled as follows:  
         [0042]     I. I IN (A)=I A +K•I IN (B)  
         [0043]     II. I IN (B)=I B +K•I IN (A)  
         [0044]     III. Where K is the current gain of the extra output on the gain mirror  
         [0045]     Assuming the presence of a CM signal such that I A =I B =I CM , and solving for I IN , I IN =I CM •(1+K)/(1−K 2 ). Therefore, when total cancellation of the differential mode is attempted, K→1 and I IN →∞, which is an undesirable result. Therefore, this circuit will be limited to “partially cancelled” CFA&#39;s as described above.  
         [0046]     More specifically, when comparing  FIG. 9  to  FIG. 6 , it can be seen that the input buffer  906   a  is implemented without transistors Q 8   a  and Q 12   a , and the input buffer  906   b  is implemented without transistors Q 8   b  and Q 12   b . Thus, the currents produced by the buffer  906   b  are not halved, causing IA (not ½IA) to be provided to the input of the current mirror  910   a , and −IA (not −½IA) to be provided to the input of the current mirror  912   a . The various currents generated by each input buffer  906   a  and  906   b , such as I A  and I B , are proportional to a difference between an input voltage signal provided to a non-inverting input of the amplifier circuit (formed by the input buffer) and a fraction of its associated output voltage signal.  
         [0047]     To create a second output for each current mirror, an additional transistor is added to each current mirror. For example, in current mirror  910   a , a transistor Q 17   a  is added, with its base connected to the bases of transistors Q 16   a  and Q 14   a , its emitter connected to the emitters of transistors Q 16   a  and Q 14   a , and its collector forming the second output of the current mirror. The first output of the current mirror  910   a  (the collector of transistor Q 16   a ) outputs IA, and the second output of the current mirror  910   a  (the collector of transistor Q 17   a ) outputs K•IA, where K, which is less than 1, is dependent on the size of the transistor Q 17   a.    
         [0000]     Various Implementations for Generating Sums and Differences of Current  
         [0048]     The above discussed circuit of  FIG. 8  presented an implementation of a fully differential CFA architecture. Alternative schemes for generating sums and differences of currents using current mirrors are also within the scope of the present invention. Such alternative schemes use both the input &amp; output of a mirror.  FIGS. 10A-10D  demonstrate various implementations of this concept. In all cases, currents combined in parallel at the input side of a current mirror add together, while currents taken away from the output side serve to subtract from the total output current.  
         [0049]      FIG. 10A  presents a basic current mirror  1010 A, showing three currents being added together (IN 1 , IN 2 , IN 3 ) and two currents being subtracted from the output (OUT 1 , OUT 2 ). The total output current will be given approximately by: 
   IOUT=IN 1+ IN 2+ IN 3− OUT 1− OUT 2  
         [0050]     Any number of currents could be combined in such a fashion. The limitation of  FIG. 10A  is that the output node of the mirror (in this implementation, the collector of the output transistor Q 4 ) may experience large variations in voltage, and this may disrupt the correct functioning of output current source OUT 1 , OUT 2 , etc.  
         [0051]     In order to avoid this effect, a slightly more complicated current mirror  1010 B with degeneration resistors (RD) attached to the emitters (of transistors Q 14  and Q 16 ), as shown in  FIG. 10B , can be employed. This circuit is superior in that variations on the output voltage of the current mirror do not affect the voltage seen by the subtracting current sources at the output. Note that the input currents can be added in a similar fashion, at the emitter terminal of the input transistor Q 14 , as demonstrated with IN 3 . This circuit has the drawback that the currents through the transistors will no longer match precisely, and therefore some nonlinearity may be introduced.  
         [0052]     This problem can be ameliorated with an additional cascode transistor Q 15 , as demonstrated in the modified Wilson current mirror  1010 C of  FIG. 10C .  
         [0053]     Finally, both a cascode transistor Q 15  on the output and degeneration resistors RD could be used, with inputs &amp; outputs connected at a number of possible nodes as shown in the current mirror  1010 D of  FIG. 10D .  
         [0054]     This is not an exhaustive list of possibilities, but shows some of the more common current mirrors typically implemented in integrated circuits. Accordingly, one of ordinary skill in the art will understand that alternative current mirror circuits can be used for adding and subtracting currents, while still being within the spirit and scope of the present invention.  
         [0000]     Alternative Fully Differential CFA  
         [0055]     The circuit of  FIG. 11  implements a fully differential CFA using cascoded Wilson current mirrors (which were discussed above with reference to  FIG. 10C ), in accordance with an embodiment of the present invention. Rather than using an extra set of current mirrors to generate inverted currents, as in  FIG. 8 , the circuit of  FIG. 11  uses direct subtraction via connection to the outputs of the main gain mirrors.  
         [0056]     The embodiment of  FIG. 11  includes input buffers  1106   a  and  1106   b , cascoded Wilson current mirrors  1110   a ,  1112   a ,  1110   b  and  1112   b , output buffers  1108   a  and  1108   b , and CM input buffer  1106   c .  FIG. 11  demonstrates an embodiment for generating CM and DM signal currents that require multiple buffer currents, but does not require additional current mirrors. The subtraction function required for DM operation is performed by taking away current from the output of the gain-node current mirrors, rather than trying to inject the correct phase into the input. The benefit is once again a reduction of the circuitry required. A second potential benefit is that this scheme may allow higher frequency operation, since there is no additional phase shift added by extra current mirror stages. A potential drawback could be that since this architecture involves connecting extra circuitry to the gain node side of the current mirrors, it could result in decreased gain and/or greater nonlinearity which should be compensated for. However, so long as these issues are appropriately addressed,  FIG. 11  provides an excellent implementation.  
         [0000]     Hybrid CFA/VFA Combinations:  
         [0057]     There is no particular reason that there is a requirement to use a CFA input for both CM and DM signals. It is possible, for example, to use the DM CFA input of  FIG. 5 , but generate a common-mode signal using a (somewhat modified) standard differential pair. This would make the DM a CFA, and the CM a voltage feedback amplifier (VFA). There are various reasons why this may be desirable. For example, there may be no need for the special characteristics of a CFA for the CM. For another example, it might be desirable to have a small voltage offset or bias current on the CM, or perhaps the CFA requirement for an external feedback resistor is undesirable. The VFA input might be simpler and less costly to implement.  FIG. 12  shows a block diagram of such a hybrid voltage-feedback/current-feedback design.  
         [0058]     The circuit of  FIG. 12 , which implements a hybrid CFA/VFA, is shown as using the simple degenerated mirrors of  FIG. 10 (B). It also demonstrates a voltage-controlled common-mode feedback circuit, to demonstrate that the differential and common-mode portions of the overall architecture can be combined with other types of amplifier architecture in hybrid circuits.  
         [0059]     Referring now to  FIG. 12 , in this particular example the CM circuit of  FIG. 10  has been replaced with a voltage feedback circuit (VFC), while the DM circuit is similar to that used in  FIG. 11 . The new CM circuitry performs the same task as before, namely providing identical currents to the left and right halves of the circuit. However, rather than using a voltage buffer as an input stage, the CM circuit of  FIG. 12  uses a differential pair circuit  1250   c . The CM current is therefore dependent on the difference between the voltage at the IN_CM input node and the voltage at a CM feedback node  1252   c . This means that the CM circuit is now operating in a voltage-feedback mode rather than the current-feedback mode of  FIG. 11 . Of particular note in  FIG. 12  is the fact that the differential pair circuit  1250   c  has multiple outputs. Additionally, in  FIG. 12 , the two pairs of outputs are connected such that at steady state, the currents will be balanced equally in both sides of the differential pair circuit  1250   c , which is a desirable condition for optimal voltage-feedback operation.  
         [0060]     Specifically, the differential pair circuit  1250   c  is shown as including four NPN transistors labeled Q 52   c , Q 54   c , Q 56   c  and Q 58   c . The bases of transistors Q 52   c  and Q 54   c  are connected together and form the CM input (CM_IN)  1202   c . The emitters of transistor Q 52  and Q 54 , which are connected together, are connected through a current source Ic to the rail voltage VEE. The bases of transistors Q 56   c  and Q 58   c , which are connected together, form a second input  1204   c  of the differential pair circuit  1250   c , which is connected to OUTA and OUTB by feedback resistors R F . The bases of transistors Q 56   c  and Q 58   c , which are connected together, are connected through the current source Ic to the rail voltage VEE. Transistors Q 52   c  and Q 54   c  provide the CM voltage-feedback current, while transistors Q 56   c  and Q 58   c  remove CM current from (or provide a current of opposite polarity to) the high-impedance nodes  1214   a  and  1214   b , and therefore at steady state the current through all four transistors Q 52   c , Q 54   c , Q 56   c  and Q 58   c  should be equal. One of ordinary skill in the art would appreciate that the differential pair circuit  1250   c  could be implemented in other manners that are also within the spirit and scope of the present invention.  
         [0061]     For convenience, identical or similar components in the various Figures have been labeled in a similar manner (i.e., the last two number are the same). For example, one of the input buffers is labeled  406   a  in  FIGS. 4 and 6 ,  506   a  in  FIGS. 5 and 7 ,  806   a  in  FIG. 8, 906   a  in  FIG. 9, 1106   a  in  FIG. 11 , and  1206   a  in  FIG. 12 . For another example, one of the high impedance nodes is labeled  414   a  in  FIGS. 4 and 6 ,  514   a  in  FIGS. 5 and 7 ,  814   a  in  FIG. 8, 914   a  in  FIG. 9, 1114   a  in  FIG. 11 , and  1214   a  in  FIG. 12 . This labeling is useful for understanding similarities, and differences, between the various embodiments.  
         [0062]     The forgoing description is of the preferred embodiments of the present invention. These embodiments have been provided for the purposes of illustration and description, but are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to a practitioner skilled in the art. Embodiments were chosen and described in order to best describe the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention. Slight modifications and variations are believed to be within the spirit and scope of the present invention. It is intended that the scope of the invention be defined by the following claims and their equivalents.