Abstract:
An electronic memory system includes a memory array of a number of pair of bitlines comprising a true bitline and a complementary bitline. A first normal cell connects to the true bitline (BT 0 ) and a second normal cell connects to the complementary bitline (BC 0 ). A first reference cell connects to the true bitline and a second reference cell connects to the complementary bitline. A clock generates timing pulses including short circuiting-equalization pulses and selectively provides reference potential pulses in a reference potential mode of operation. A sense amplifier has a true terminal connected to the true bitline and a complementary terminal connected to the complementary bitline. An equalization short circuiting circuit connects to the clock and to the true bitline and the complementary bitline for short circuiting the true bitline and the complementary bitline together in response to the short circuiting pulses to equalize the electric potential thereon as a function of short circuiting-equalization. A precharge circuit connects at least one of the true bitline and the complementary bitline to an electrical potential selected from a higher voltage or low voltage reference potential in response to a precharge equalization clock pulse from the clock generator.

Description:
BACKGROUND 
   In the operation of DRAM (Dynamic Random Access Memory) devices, it is required to maintain data stored in a charge storage cell for a maximum retention period without performing a refresh operation in order to offer high availability and low power consumption. When competing with Static RAM (SRAM) devices, it is also desirable to offer high performance with the same DRAM design. In the current state of the art there are DRAM designs that offer either high retention times for the stored data or high performance. The following art describes a scheme for offering both high retention times for the stored data and high performance with a single circuit configuration. Conventional mid-level sensing schemes precharge the bitlines to mid-level potentials such as VDD/2, VDD/3, or VDD/X (where VDD is power supply voltage and X is a number greater than 1) and offer good retention times for the stored data. Rail sensing schemes precharge the bitlines to VDD or ground (hereinafter referred to as GND) and offer good performance. 
   When one uses a GND sensing scheme during the precharge time, all the bitlines of the DRAM are precharged to GND. Although a GND precharge sensing scheme can support a wider operating range and provides more overdrive during amplification and more precharge than conventional VDD/2 sensing, it has the problem that it consumes more power. When considering signal development, charge transfer does not begin until the Word-Line voltage is greater than the bitline voltage by the amplitude of a threshold voltage (Vt). This is critical for a longer word-line that will have significant slew rate, e.g. a 1 Volt/nanosecond slew introduces an extra 750 picosecond delay for VDD/2 precharge (equal to about 1.5V). Although GND sense circuits require reference cells (1.5% 16 Megabyte area), they also offer static and dynamic bitline balancing and provide an excellent interlock for sense amplifier timing generation. However, a GND precharge scheme suffers from the problem of degraded retention characteristics for a stored ‘1’, where the drain to source voltage of the storage transistor is the worst case for leakage current through the storage transistor. 
   Other prior art includes U.S. Pat. No. 4,816,706 of Dhong et al. entitled “Sense Amplifier with Improved Bitline Precharging for Dynamic Random Access Memory”, and U.S. Pat. No. 6,577,548 of Barth et al. entitled “Self timing interlock circuit for embedded DRAM.” 
   Sense Amplifiers are described in J. E. Barth et al. “Embedded DRAM design and architecture for the IBM 0.11-m ASIC offering” IBM J. RES. &amp; DEV. VOL. 46 No. 6 pages 675–689 (November 2002). 
   When one stores a data value of “1” on the storage node of a deep trench capacitor of a memory cell, the drain-source voltage is at level of the supply potential VDD. During the precharge mode, the leakage through the weak channel of the cell transistor is strongly dependent on both the gate-source voltage and the drain-source voltage. Therefore, in a GND sensing scheme, the retention characteristic for a data value of “1” is degraded. 
   Alternatively, if a VDD sensing scheme is employed for a DRAM, the data value of “0” data retention characteristic of a data value of “0” is degraded by a large degree of leakage. To compensate for such a large degree of leakage, more frequent refresh operations are needed, but frequent performance of a refresh operation has dual disadvantages. The first disadvantage is that data retention functions consume excessive power required to refresh the memory cell. The second disadvantage is that memory availability is degraded because it is inaccessible during the time consumed by performance of the increased number of refresh cycles. 
   Therefore, both of the above GND and VDD sensing schemes, which present the problem of high cell leakage during the precharge condition, are not suitable for low power applications, even if such schemes show better performance and design robustness regardless of power supply voltage. 
   Use of mid-level sensing such as VDD/2 or VDD/X (where X is a number greater than 1) provides better cell leakage characteristics. With a mid-level sensing scheme, the data retention characteristic of a data value of “1” is improved because the gate-source voltage of the cell transistor is negative. The degree of data retention of a data value of “0” is also better than that for a VDD sensing scheme because source-drain voltage of the cell transistor is dropped from VDD to (VDD−VDD/2 or VDD/X). Also, the degree of data retention of a data value of “0” is not an issue because another leakage source compen-sates for the cell channel leakage from the bitline to the storage node of the storage capacitor. Although mid-level sensing offers better retention characteristics, performance thereof falls short of objectives. 
   We have discovered that the best way to solve this problem is to retain the benefits of each of the above-described sensing schemes. Accordingly, the present invention employs hybrid precharge schemes wherein a bitline level is switched from mid-level during a self-refresh, data retention mode of operation to a GND or a VDD sensing scheme during a mission mode of operation. Thus in accordance with this invention a dual precharge scheme is provided. From now on, we designate two operation modes which are the mission mode and the data retention mode. The mission mode is a real data access mode. The data retention mode is just to keep the data without sending or receiving data while running as a low power mode. The bitline precharge level during the mission mode of operation is the same as required for the sensing scheme regardless of precharge or active mode. However, during the self-refresh, data retention mode, the bitline precharge level is maintained around VDD/X, making the gate-source voltage (VDD/X) and reducing the voltage drop across the cell transistor. 
   This invention provides a new bitline precharge scheme which combines two well known schemes to extend the data retention time during the self-refresh, data retention mode of the memory array and to improve performance during mission mode. 
     FIG. 1  shows a prior art combination of a clock  24  and a Mid-Level (e.g. VDD/2 or VREFX) sense amplifier system  10  with a related timing diagram shown in  FIG. 2  and a clock  24 . Sense amplifier system  10 , which is implemented with eleven MOSFET devices, includes a true bitline BT 0 , a complementary bitline BC 0 , a sense amplifier SA including four FETs, plus seven other FETs, normal cells NC 0 /NC 1 , a true bitline capacitor CT, a complementary bitline capacitor CC, and a VREFX-short-circuiting precharge circuit ESR which short circuits true bitline BT 0  to complementary bitline BC 0  and simultaneously connects both of them to the precharge potential VREFX, i.e. precharge voltage. 
   The clock  24  provides three signals to the sense amplifier system  10  including a precharge signal ESP supplied to the VREFX-short-circuiting precharge circuit ESR on a reference potential signal line ERL, a SETN signal on N clock line LN, and a SETP signal on P clock line LP. 
   Line  11  supplies the system  10  with a precharge potential VREFX, which has a mid-level voltage between the voltage of the power supply voltage VDD and GND (ground). 
   There are three connections to the true bitline BT 0  at nodes  1 T,  3 T, and  4 T. Similarly there are three connections to the complementary bitline BC 0  at nodes  1 C,  3 C, and  4 C. The nodes  4 T and  4 C are connected via true bitline BT 0  and the complementary bitline BC 0  to the negative and positive terminals respectively of sense amplifier SA and the potentials on nodes  4 T and  4 C are amplified to VDD or GND by the operation of sense amplifier SA producing an output through those negative and positive terminals as will be well understood by those skilled in the art. 
   Wordline WLA is connected via node  60  to the gate electrode (hereinafter gate) of NFET N 15  of true normal cell NC 0 . True normal cell NC 0  comprises a storage capacitor CS 0  and NFET N 15 . The NFET N 15  has its gate connected via node  60  to wordline WLA, its source connected to the true bitline BT 0  at node  1 T, and its drain connected via a storage node SN 0  to the node of true storage capacitor CS 0 . Complementary normal cell NC 1  comprises a complementary storage capacitor CS 1  and NFET N 14 . NFET N 14  has its gate connected via node  61  to wordline WLB, its source connected to complementary bitline BC 0  at node  1 C and its drain connected via a storage node SN 1  to the node of the complementary storage capacitor CS 1 . The opposite terminals of storage capacitors CS 0  and CS 1  connect via node  52  to GND. 
   True bitline BT 0  is also connected via node  1 T to a terminal of true bitline capacitor CT connected at its other end to GND. Complementary bitline BC 0  is connected through node  1 C to one terminal of complementary bitline capacitor CC, that is also connected at its other end via node  52  to GND. 
   The nodes  4 T and  4 C are connected via true bitline BT 0  and the complementary bitline BC 0  to the negative and positive inputs respectively of the sense amplifier SA and the potentials on node  4 T or node  4 C are alternatively amplified to VDD or GND by the operation of the sense amplifier SA during operation of the system  10 . That is to say that when node  4 T is amplified to VDD, node  4 C is amplified to GND and that when node  4 T is amplified to GND, node  4 C is amplified to VDD. 
   The VREFX-short-circuiting precharge circuit ESR includes NFETs N 2 , N 4 , and N 3 . All three equalization NFETs N 2 , N 3 , and N 4  of the VREFX short-circuiting precharge circuit ESR have their gates connected via node  51  to be turned ON when they receive the precharge signal ESP on the reference potential precharge line ERL. 
   The drain of the centrally located short-circuiting NFET N 3  is connected via node  3 T to the true bitline BT 0  and its source connected to the complementary bitline BC 0  so that NFET N 3  conducts, it short circuits the true bitline BT 0  to the complementary bitline BC 0 . 
   NFET N 2  has its drain connected to the true bitline BTO via node  3 T, and its source connected to the reference precharge source VREFX via node  58  and line  11 . NFET N 4  has its source connected to the complementary bitline BC 0  via node  3 C and its drain connected to the voltage source VREFX via node  58  and line  11 . 
   When NFETs N 2  and N 4  are ON when precharge signal ESP turns ON, they connect true bitline BT 0  and the complementary bitline BC 0  to the reference precharge source VREFX via node  58  and line  11 . At the same time, the NFET N 3  short circuits the lines BT 0  and BC 0  together. The result is that the potentials on true bitline BT 0  and complementary bitline BC 0  equalize rapidly. 
   In operation, the reference potential equalization line ERL is connected to clock  24  to receive the short circuiting (reference potential) precharge signal ESP which is shown in the signal timing diagram of  FIG. 2 . During an equalization phase of operation of the system  10  from time tl to time ta in each cycle the reference potential precharge signal ESP from clock  24  is applied on the reference potential equalization line ERL to circuit ESR to raise the gate of NFET N 3  turning it ON to provide a short circuit connection between the true bitline BT 0  and the complementary bitline BC 0 . At the same time precharge signal ESP is applied to the gates of NFETS N 2 /N 4  which turns them ON so that they interconnect the true bitline BT 0  to the complementary bitline BC 0  to charge or discharge both of them to the potential of the reference voltage source VREFX via node  58  and line  11 . 
   Preferably the sense amplifier SA shown in  FIG. 1  is a conventional cross-coupled circuit made of two inverters. The input and output are cross connected simultaneously, i.e. the output of one inverter is connected to the input of the other inverter and vice versa. When sense amplifier SA is turned on, the nodes  4 T and  4 C which are tied to the terminals of the sense amplifier SA are alternatively amplified to VDD or GND. The true bitline BT 0  and complementary bitline BC 0  are two of the inputs of the inverter. The inputs and outputs of the inverter are cross connected simultaneously, i.e. the output of one inverter is connected to the input of the other inverter and vice versa. When the sense amplifier SA is turned on, one of the nodes  4 T and  4 C tied to the sense amplifier SA is amplified to potential VDD with the other one of the nodes  4 T and  4 C being at the opposite potential, i.e. GND, as will be well understood by those skilled in the art. 
   The particular sense amplifier SA shown in  FIG. 1  is a cross coupled sense amplifier SA which includes PFET P 0  and PFET P 1  and two NFETs N 0 /N 1 . The gates of FETs P 0  and N 0  connect to node  4 C. The drains of FETs P 0  and N 0  connect to node  4 T. The gates of FETs P 1  and N 1  connect to node  4 T. The drains of FETs P 1  and N 1  connect to node  4 C. The sources of PFETs P 0 /P 1  connect via node  54  to the source of PFET P 2 , with its drain is connected to potential VDD, and its gate connected to receive the SETN input signal on line LN from clock  24 . The sources of NFETs N 0 /N 1  connect via node  55  to the drain of the NFET N 5 , with its source connected to ground potential, and its gate connected to receive the SETP input signal on line LP from clock  24 . 
   Referring to  FIG. 1  and  FIG. 2 , the SETN signal on clock line LN from clock  24  connects to the gate of PFET P 2  which turns ON gate potential VDD to line SNL, which line SNL connects to node  54 . The result is that the SETN signal on line LN activates the gate of NFET P 2  which gates voltage VDD to node  54  via the input line SNL to the sense amplifier SA. In turn node  54  is adapted to connect voltage VDD to the sources of PFETS P 0  and P 1  of sense amplifier  54  when the SETN signal turns on PFET P 2 . Thus, the PFET P 2  is adapted to connect voltage VDD to node  54  of sense amplifier SA when PFET P 2  receives the on SETN signal on line LN from the clock  24 . 
   The SETP signal on line LP from clock  24  connects to the gate of NFET N 5  which gates voltage GND to node  55  via the source drain circuit of NFET N 5  and the line SPL. In turn node  55  is adapted to connect GND potential to the sources of NFETS N 0  and N 1  of sense amplifier SA  54 , when the SETP signal on line LP turns on NFET N 5 . Thus, NFET N 5  is adapted to connect GND potential to node  55  of the sense amplifier SA when NFET N 5  receives the SETP signal on line LP from the clock  24 . 
   The drains of FETs P 0  and N 0  are connected via node  4 T to the bitline BT 0  as are the gates of FETs P 1  and N 1 . The drains of FETs P 1  and N 1  are connected via node  4 C to complementary bitline BC 0  as are the gates of FETs P 0  and N 0 . The sources of PFETs P 0 /P 1  are connected via node  54  to the source of the PFET P 2 , the drain of which is connected to potential VDD, and the gate of which is connected to line LN to receive the SETN input signal. The sources of NFETs N 0 /N 1  are connected via node  55  to the drain of the NFET N 5 , the source of which is connected to GND, and the gate of which is connected to line LP to receive the SETP input signal. 
   Operation of the Mid-Level Sense Amplifier System 
   Referring again to the equalization circuit ESR in  FIG. 1 , the source/drain circuit of the NFET N 2  is connected via node  3 T between the true bitline BT 0  and VREFX (via node  58  and line  11 .) The source/drain circuit of NFET N 4  is connected between the complementary bitline BC 0  via node  3 C and VREFX (via node  58  and line  11 ). 
   When it is ON, the source/drain circuit of NFET N 3  short circuits the true bitline BT 0  (via node  3 T) to the complementary bitline BC 0  (via node  3 C.) 
   In summary, (referring again to  FIG. 1  and  FIG. 2 ) when precharge signal ESP is ON from time t 0  to tb, from tk to tB and from tK to tb as the cycle repeats, NFETs N 2 /N 3 /N 4  conduct short circuiting nodes  3 T and  3 C together and connecting them to the precharge voltage VREFX through line  11 , node  58  and NFETs N 2  and N 4  thereby equalizing the charge on true bitline BT 0  and complementary bitline BC 0  at the precharge voltage VREFX. 
   The VDD/2 sense amplifier circuit  10  of  FIG. 1  is an example of an embodiment in which a conventional DRAM sensing scheme is employed known as a “mid-level VDD/X sensing scheme”, in which both a true bitline BT 0  and complementary bitline BC 0  are precharged to a value VREFX, e.g. approximately halfway (VDD/2) between a logic “1” voltage VDD and a logic “0” voltage GND, during a precharge interval by connection through line  11 , node  58  and NFETs N 2  and N 4 . 
   At time tb in  FIG. 2  the true normal cell NC 0  turns ON when a positive pulse RWA (which lasts until time tk) passes from wordline WLA via node  60  to the gate of NFET N 15  thereby coupling the true normal cell capacitor CS 0  to the precharged true bitline BT 0  via the source/drain circuit of NFET N 15  and node  1 T. Then, the result is that the voltage on true bitline BT 0  increases or decreases slightly, depending on the value of the bit previously stored in the true normal cell capacitor CS 0  of the true normal cell NC 0 , thus creating a differential with respect to the complementary bitline BC 0  which still remains at VREFX because the complementary normal cell NC 1  is OFF because signal RWB on line WLB in  FIG. 2  is low continuously until time tB. 
   Alternatively, at time tB the complementary normal cell NC 1  turns ON when a pulse RWB′ (which lasts until time tK) passes from wordline WLB via node  61  to the gate of NFET N 14 , coupling capacitor CS 1  to the precharged complementary bitline BT 1  via the source/drain circuit of NFET N 14  and node  1 C. Then, as a result the voltage on complementary bitline BC 0  increases or decreases slightly, depending on the value of the bit stored in the capacitor CS 1  of complementary normal cell NC 1 , thus creating a differential with respect to the true bitline BC 0  which still remains at VREFX because the true normal cell NC 0  is OFF, as signal RWA is continuously OFF in  FIG. 2  from time tk to time tL. 
   Referring again to  FIG. 2 , line LN from the clock  24 , provides the SETN signal to gate of PFET P 2  (that is normally positive except from time tf to tj and from time tF to tJ in  FIG. 2 .) When PFET P 2  is ON it connects potential VDD to line SNL to node  54  of the sense amplifier SA. Line LP from the clock  24  provides the SETP signal to the gate of NFET N 5  (which is normally negative except from time tf to tj and from time tF to tJ in  FIG. 2 .) 
   The sources of NFET N 0  and NFET N 1  are connected to node  55 , which connects via Set P Line SPL to the drain of the NFET N 5 , the source of which connects to GND. The gate of the NFET N 5  is connected to receive the SETP pulse to turn ON during the time intervals from time tf to tj and from time tF to tJ in  FIG. 2  in response to the SETP signal, thereby lowering node  55  to GND via source/drain circuit of the NFET N 5  during that interval. 
   The result is that the sense amplifier SA is energized during the time intervals from tf to tj and from time tF to tJ when the node  54  connects to VDD and node  55  connects to GND when the SETN pulse on the sense amplifier signal line SETN is down, so the PFET P 2  conducts, and the SETP pulse on the sense amplifier enable line SETP is positive, so the NFET N 5  conducts, connecting GND potential to node  55 . 
   True Bitline Cycle and Complementary Bitline Cycle 
   Equalization and Precharge Cycles 
   In  FIG. 2 , the system  10  goes through normal access and precharge cycles. From time t 0  to time tk, the system  10  also goes through the normal access for NC 0  and precharge cycle. Then from time tk to tL, the system  10  also goes through the normal access for NC 1  and precharge cycle. 
     FIG. 3  shows a prior art combination of a clock  34  and a GND sense system  20  that operates as indicated by the signal timing diagram shown in  FIG. 4 . The system  20  is a modification of the mid-level (VDD/X) sense amplifier circuit  10  of  FIG. 1 , which is modified to include a reference cell RC 0 , a reference cell RC 1  and an equalization circuit ESG, which is connected to ground instead of the precharge potential VREFX. The true normal cell NC 0  and the complementary normal cell NC 1  are the same as in  FIG. 1 , as is the sense amplifier SA. The clock is modified since it must produce different timing signals in response to input signal  22 . 
   The reference cell RC 0  has inputs connected to line Q 0  and word line WL 0  from the clock  34 . The reference cell RC 1  has inputs connected to word line WL 1  and line Q 1  from the clock  34 . 
   Reference cell RC 0  includes NFET N 6 , NFET N 7 , and a true bitline reference cell capacitor C 0 . The input line Q 0  from clock  34  connects to the gate of NFET N 6 . The input line WL 0  signal from clock  34  connects to the gate of NFET N 7 . The drains of NFET N 6  and NFET N 7  connect via node  56  to the node of capacitor C 0 , the other terminal of which connects to GND. The source of NFET N 7  connects via node  2 T to the true bitline BT 0 . The source of NFET N 6  connects via line  11  and node  59  to the reference potential input VREFX. 
   Reference cell RC 1  includes NFET N 8 , NFET N 9 , and a complementary bitline reference cell capacitor C 1 . The input line Q 1  from clock  34  connects to the gate of NFET N 9 . The drains of NFET N 8  and NFET N 9  connect via node  57  to the node of capacitor C 1 , the other terminal of that connects to GND. The source of NFET N 8  connects via node  2 C to complementary bitline BT 0 . The source of NFET N 9  connects via line  11  and node  59  to the reference potential input VREFX 
   Access of NC 1  and Precharge 
   The voltage on capacitor C 0  in the reference cell RC 0  is charged when signal REQ 0  on line Q 0  is high from time t 0  to tc and from time th to tL remaining on until time tc on the next cycle. When line Q 0  is high, it turns NFET N 6  ON which connects the voltage on VREFX via line  111  and node  59 , the source drain circuit of NFET N 6  and node  56  to node of capacitor C 0 . The charge on capacitor C 0  in reference cell RC 0  is transferred to the true bitline when the signal RWL 0  on line WL 0  is high from time tb to time th, thereby turning ON NFET N 7  to provide a reference potential from capacitor C 0  via node  56 , the source drain circuit of NFET N 7  and node  2 T. 
   The RWL 0  signal on line WL 0  turns ON at time tb and OFF at time th instead of remaining on. 
   From time t 0  to time tB the RWL 1  signal on line WL 1  remains OFF so the charge on capacitor C 1  is not connected to the complementary bit line, and there is no interaction through RC 1  with bitline. 
   Access of NC 2  and Precharge 
   The voltage on capacitor C 1  in the reference cell RC 1  is charged from time t 0  to time tB when signal REQ 1  on line Q 1  is high, thereby turning on NFET N 9  that connects the voltage on VREFX via line  11 , node  59 , the source drain circuit of NFET N 9 , and node  57  to the node of capacitor C 1 . The charge on capacitor C 1  in the reference cell RC 1  is transferred to the true bitline when the signal RWL 1  on line WL 1  is high from time tB to time tH, thereby turning ON NFET N 8  to provide a precharge of the reference potential from capacitor C 1  via the source drain circuit of NFET N 8  and node  2 C 
   The RWL 1  signal on line WL 1  turns ON at time tB and OFF at time tH instead of remaining on. 
   From time tk to time tL the RWL 0  signal on line WL 0  remains OFF so the charge on capacitor C 0  is not connected to the true bit line BT 0 , and there is no interaction through RC 0  with bitline. 
   Referring to  FIGS. 3 and 4 , with respect to the reference cell RC 0 , the mid-level potential source VREFX is cyclically connected to charge the capacitor C 1  via NFET N 6  because line Q 0  receives a variable REQ 0  potential which turns the gate of NFET  6  OFF at time tc and ON at time th cyclically. Next, the node  56  is cyclically connected to node  2 T via NFET N 7  because line WL 0  receives a variable RWL 0  potential which turns the gate of NFET  8  OFF at time tc and turns it ON at time th cyclically in synchronism with REQ 0 . 
   At times indicated in  FIG. 4 , the mid-level potential source VREFX is connected to charge the capacitor C 1  via line  11 , node  59 , and NFET N 9  when the signal REQ 1  supplied on line Q 1  to the gate of the NFET  9  is ON which turns ON the NFET  9  except from time tB to tH. Next, the node  57  is connected to node  2 C via NFET N 8  because signal RWL 1  on line WL 1  to the gate of NFET  7  is ON from time tB to tH cyclically in synchronism with signal REQ 1 . 
   Clock  34  provides a short circuiting-precharge signal ESP to the equalization circuit ESG via line EQL and node  51 . The equalization circuit ESG includes the NFET N 3  which short circuits true bitline BT 0  and complementary bitline BC 0  together as in  FIG. 1 , but circuit ESG connects through the source drain circuits of NFETs N 2  and N 4  and node  52  to GND instead of VREFX. 
   Clock  34  also provides the SETN signal on clock line LN, and a SETP signal on clock line LP differently from clock  24  in  FIG. 1  in that the SETP signal on line LP is always connected to GND in the system  20 , since the NFET N 5  has been omitted from the circuit. The SETP input line LP′ is shown for purposes of explanation since it is redundant in view of the direct connection of node  55  to GND. 
   Equalization of Charge on Bitlines 
   When the precharge signal ESP on line EQL is ON from time t 0  to ta, the NFETs N 2 /N 3 /N 4  are ON and conduct bringing nodes  3 T and  3 C together, connecting nodes  3 T and  3 C to ground via node  52  and NFETs N 2  and N 4  thereby equalizing charge on true bitline BT 0  and complementary bitline BC 0  at the reference voltage VREFX. As with the embodiment of  FIG. 1 , NFET N 3  short circuits lines BT 0  and BC 0  together when NFET N 3  is conducting. Thus the short circuiting precharge signal ESP on line EQL both short circuits and grounds true bitline BT 0  and complementary bitline BC 0  during the time interval tl to ta. 
   The GND sense amplifier system  20  includes sense amplifier SA plus ten additional MOSFETs but there are significant differences. First the NFET N 5  has been eliminated. Second, when the equalization circuit ESG is turned ON by the precharge signal ESP on lie EQL, the circuit ESG connects the true bitline BT 0  and the complementary bitline BC 0  to ground (GND) instead of a mid-level potential (VDD/X). The sense amplifier SA shown in  FIG. 2  can be identical to the sense amplifier SA shown in  FIG. 1  or can be modified to include another equivalent sense amplifier circuit as will be well understood by those skilled in the art. 
   In the case of the sense amplifier circuit  20  of  FIG. 2 , the SETP input, and NFET N 5  are omitted from the sense amplifier system  20 . Instead the SPL input line to the sense amplifier SA is permanently connected to ground GND. Moreover, both the source of the equalization NFET N 2  and the drain of the equalization NFET N 4  are now connected to GND via the node  52 , i.e. not to the mid-level potential source VREFX, unlike circuit  20  of  FIG. 1 . 
   As in  FIG. 1 , the drain of equalization NFET N 3  remains connected via node  3 T to the drain of equalization NFET N 2  and to true bitline BT 0 . Similarly, the sources of equalization NFET N 4  NFET N 3  remain connected via node  3 C to the complementary bitline BC 0 . 
   In operation, referring to the signal timing diagram of  FIG. 4  at the times indicated thereby, the mid-level potential source VREFX is connected to charge the capacitor C 2  via NFET N 9  when line  19  receives a positive REQ 1  pulse turning on the gate of NFET  9 . At times when signal REQ 0  on line Q 0  is high as indicated by  FIG. 4 , the mid-level potential source VREFX is connected to charge the capacitor C 1  via NFET N 6  because the positive REQ 0  pulse on the gate of NFET  6  turns it ON. 
   In  FIG. 4 , from time tl to time ta, the REQ 0  signal on line  16  is ON turning ON the NFET N 6  gate, thereby charging the reference cell capacitor C 1  to the VREFX potential of the reference voltage source on line  11 . At time ta the REQ 0  signal turns OFF, turning OFF NFET N 6  from time ta to ti. An instant later, at time tb, the reference wordlines RWL 0  begins to rise and reaches the fully ON state at time tc. 
   The input line  19  connects the REQ 1  signal on line RWL 1  (which is ON except from times tB to tK) to the gate of NFET N 9  to turn it ON, thereby charging reference cell capacitor C 2  to the VREFX potential of the reference voltage source on line  11 , in  FIG. 4  when the Reference EQualize signal REQ 0  is ON. 
   The word line WL 1  connects the first wordline signal RWL 1  to the gate of NFET N 8  thereby maintaining NFET N 7  OFF continuously, so the capacitor C 2  does not transfer charge to the complementary bitline BC 0 . 
   However, there is a reversal of the REQ 0 /RWL 0  signals with the REQ 1 /RWL 1  so that the REQ 1 /RWL 1  signals rise and fall as shown for the REQ 0 /RWL 0  signals in  FIG. 4  after time tB. In particular, RWL 0  is OFF continuously and REQ 0  is ON continuously from time tl to time TK, so the sense amplifier system  20  operates to charge the complementary bitline BC 0  to voltage VREFX from capacitor C 1 , when the voltage on line WL 1  is raised in response to turning ON of the signal RWL 1 ; etc. 
   In contrast with  FIG. 1 , from time t 1  to ta, the grounding precharge signal ESP on equalization-and-grounding line EQL connects via node  51  to the gates of the equalization NFETs N 2 /N 3 /N 4  to turn those equalization NFETs ON. However, as indicated above, equalization NFETs N 2 /N 3 /N 4  of a grounding-short-circuiting equalization circuit ESG connect true bitline BT 0  and complementary bitline BC 0  via nodes  3 T and  3 C respectively to GND via source drain circuits of the equalization NFETs N 2 /N 3 /N 4 , prior to turning ON the gate of NFET N 7  when signal RWL 0  on line WL 0  begins to rise at time tb. 
   For performance reasons, the GND sensing scheme of  FIGS. 3 and 4  precharges the bitline pair BT 0 /BC 0  to GND before a read operation between time t 0  and time ta and in  FIG. 4  starting at time tk by turning ON the grounding equalization signal ESP connected via node  51  and equalization-and-grounding line EQL to raise the gates of equalization NFETs N 2 /N 3 /N 4  to turn those equalization NFETs ON, thus connecting both bitline BT 0  and complementary bitline BC 0  via nodes  3 T and  3 C to GND via source drain circuits of the three equalization NFETs N 2 /N 3 /N 4  of grounding-short-circuiting equalization circuit ESG. 
   Because of the precharging to GND, lines  17 / 18  for reference wordlines pulses RWL 0 /RWL 1  are needed to place a reference voltage VREFX e.g., (Vread 1 −Vread 0 )/2) on either the true bitline BT 0  or the complementary bitline BC 0  in order to be able to read a 0 bit. Typically this is accomplished by placing VREFX (approximately VDD/2) in the reference cell via a precharge device, and selecting a reference word line RWL 1  on the opposing bitline BC 0  coupled to the selected word-line RWL 0 . 
   For example, from time t 0  to time tb in  FIG. 4  the signal REQ 0  is ON causing the line Q 0  to turn ON the NFET N 6  in reference cell RC 0  in  FIG. 3  connecting reference voltage VREFX to capacitor C 0  from terminal VREFX via node  59 . 
   In addition to power savings, use of a VDD/X voltage such as VDD/2 reduces drain-source voltage Vds of the array device in the precharge state; and subsequently a VDD/X voltage such as VDD/2 reduces array device off current. That results in extended retention times and further decreases power consumption. To provide simultaneously a low power retention mode and a high performance active mode, it is desirable to enable the sense amplifier to operate in either a VDD/X precharge or GND precharge mode. 
   SUMMARY OF THE INVENTION 
   The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings. 
   In accordance with this invention, an electronic memory system includes a memory array of a number of pair of bitlines comprising a true bitline and a complementary bitline. A first normal cell connects to the true bitline (BT 0 ) and a second normal cell connects to the complementary bitline (BC 0 ). A first reference cell connects to the true bitline and a second reference cell connects to the complementary bitline. A clock generates timing pulses including short circuiting-equalization pulses and reference potential pulses in a reference potential mode of operation. A sense amplifier has a true terminal connected to the true bitline and a complementary terminal connected to the complementary bitline. An equalization short circuiting circuit connects to the clock and to the true bitline and the complementary bitline for short circuiting the true bitline and the complementary bitline together in response to the short circuiting pulses to equalize the electric potential thereon as a function of short circuiting-equalization. A precharge circuit connects at least one of the true bitline and the complementary bitline to a electrical potential selected from a higher voltage or low voltage reference potential in response to a precharge equalization clock pulse from the clock generator. 
   Preferably, there are dual precharge levels, one for normal access, mission mode and the other for data retention, self refresh mode; and the precharge levels are changed dynamically from mission mode to data retention, self-refresh mode. Preferably, two sets of transistors are used to supply two different precharge levels. Preferably, one precharge level is supplied by VREFX, power supply voltage for precharging reference cells. Preferably, the other precharge level is supplied by the same power supply for precharging the true bitline and the complementary bitline during mission mode to ground. Preferably, one precharge level is supplied by shunting true bitline and the complementary bitline during precharge cycle without any additional power supply voltage for precharging. Preferably, one precharge level is supplied through the reference cell that is used in mission mode operation to the true bitline and the complementary bitline during a precharge cycle without any additional means to provide a precharge voltage. 
   In accordance with another aspect of this invention a memory array includes a number of pairs of bitlines with a pair comprising a true bitline and a complementary bitline. A first normal cell connects to the true bitline and a second normal cell connects to the complementary bitline. A first reference cell connects to the true bitline and a second reference cell connects to the complementary bitline. A clock generates timing pulses including short circuiting-equalization pulses and reference potential pulses in a reference potential mode of operation. A sense amplifier having a true terminal connects to the true bitline and a complementary terminal connects to the complementary bitline. Equalization short circuiting means connects to the clock and to the true bitline and the complementary bitline for short circuiting the true bitline and the complementary bitline together in response to the short circuiting pulses to equalize the electric potential thereon as a function of short circuiting-equalization and connecting the bitlines to either ground or a reference voltage. Dual precharge circuit means precharges in a normal access mission mode which is a data access mode operation and precharges in a data retention, self-refresh mode operation. 
   Further in accordance with this invention, a method is provided for operating an electronic memory system including a memory array which includes a number of pairs of bitlines including a true bitline and a complementary bitline, a first normal cell connected to the true bitline and a second normal cell connected to the complementary bitline, a first reference cell connected to the true bitline and a second reference cell connected to the complementary bitline, a clock for generating timing pulses including short circuiting-equalization pulses and for selectively providing reference potential pulses in a reference potential mode of operation, a sense amplifier having a true terminal connected to the true bitline and a complementary terminal connected to the complementary bitline. Provide equalization short circuiting means connected to the clock and to the true bitline and the complementary bitline for short circuiting the true bitline and the complementary bitline together in response to the short circuiting pulses to equalize the electric potential thereon as a function of short circuiting-equalization; and provide precharge circuit means for connecting at least one of the true bitline and the complementary bitline to a electrical potential selected from a higher voltage or low voltage reference potential in response to a precharge equalization clock pulse from the clock generator. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which: 
       FIG. 1  shows a prior art combination of a clock and a Mid-Level sense amplifier system as indicated by the Self-Refresh, data retention mode timing diagram shown in  FIG. 2   
       FIG. 3  shows a prior art combination of a clock and a GND sense system that operates in accordance with the signal timing diagram shown in  FIG. 4 . 
       FIG. 5  shows a combination of a clock and a bi-mode sense amplifier system designed in accordance with this invention comprising a modification of the Mid-Level sense amplifier of  FIG. 1  and the GND precharge system of  FIG. 3 . The reference cell is used for the bitline precharge function. 
       FIG. 6A  shows the signal timing diagrams of the GND precharge for the mission modes of operation of the circuit of  FIG. 5 . 
       FIG. 6B  shows the signal timing diagram of the mid-level (VDD/X) precharge for the data retention, self-refresh, mode of operation of the circuit of  FIG. 5 . 
       FIG. 7  is a schematic diagram of a second embodiment of the present invention in which a combination of a clock and a bi-mode sense amplifier system includes a MOSFET dual precharge circuit, which shows a modification of the system as shown in  FIG. 5 . 
       FIG. 8  shows the signal timing diagram of wordline, equalization signal, equalization pulse, true bitline, and complementary bitline potentials applied to and generated in the circuit of  FIG. 7 . 
       FIG. 9  is a schematic diagram of a third embodiment of the present invention in which a combination of a clock and a bi-mode sense amplifier system includes a MOSFET dual precharge circuit, which show a modification of the system as shown in  FIG. 7 . 
       FIG. 10  shows the timing diagram and signal level of signals for the system of  FIG. 9 . 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   FIRST EMBODIMENT 
     FIG. 5  shows a combination of clock  44  and the bi-mode sense amplifier system  30  designed in accordance with this invention comprising a combination of features of the Mid-Level sense amplifier of  FIG. 1  and the GND precharge system of  FIG. 3  during the first phase of operation in which a true bitline normal cell NC 0  and a complimentary bitline reference cell RC 1  are activated to connect the storage capacitor CS 0  to the true bitline BT 0  in response to a true wordline pulse RWA on true wordline WLA. The true normal cell NC 0  and the complementary normal cell NC 1  are the same as in  FIG. 1 . The reference cell RC 0  and the reference cell RC 1  are the same as in  FIG. 3 . The reference cell RC 0  and the reference cell RC 0  and the reference cell RC 1  are the same as in  FIG. 3 . The reference cell in this embodiment is used as the bitline precharge purpose. 
     FIG. 6A  shows the signal timing diagrams of the GND precharge for the mission modes of operation of the circuit of  FIG. 5 . In addition,  FIG. 6B  shows the signal timing diagram of the mid-level (VDD/X) precharge for the data retention, self-refresh, mode of operation of the circuit of  FIG. 5 . 
   The system  30  of  FIG. 5  operates in accordance with an alternative phase of operation in which the complementary bitline normal cell NC 1  and a true bitline reference cell RC 0  are activated to connect the storage capacitor C 1  to the complementary bitline BC 0  in response to a complementary wordline pulse RWB′ on the complementary wordline WLB from t 0  to tl, the complementary bitline normal cell NC 0  and a true bitline reference cell RC 1  are activated to connect the storage capacitor C 0  to true bitline BT 0  in response to a complementary wordline pulse RWA′ on the complementary wordline WLA. 
   As stated above,  FIG. 5  shows a combination of the clock  44  and the bi-mode sense amplifier system  30  designed in accordance with this invention comprising a modification of Mid-Level sense amplifier  10  of  FIG. 1  and the GND precharge system  20  of  FIG. 3 . 
   The bi-mode sense amplifier system  30  includes a sense amplifier SA plus eleven other FETs, so that there are four more FETs than in  FIG. 1  and there is one more FET than in the system of  FIG. 3 . Moreover, the clock  44  has been modified to provide the alternative pulse sequences seen in  FIG. 5 . The sense amplifier SA shown in  FIG. 5  is preferably identical to the sense amplifier SA shown in  FIG. 1 , but it can be modified to include another equivalent sense amplifier circuit as will be well understood by those skilled in the art. In the bi-mode sense amplifier system  30 , as contrasted with system  10  in  FIG. 1  and system  20  of  FIG. 2 , the connection line  11  has been disconnected from the NFETs N 2  and N 4  in a modified equalization short-circuiting and grounding circuit EM. The line ERL from the clock  24  of  FIG. 1  has been replaced in  FIG. 5  by the separate connection lines P 0 , ESL, and P 1  from clock  44  for signals EGP 0 , ESP, and EGP 1  respectively. In other words the clock  44  has been modified to produce separate outputs to the separate connection lines P 1 , ESL, and P 0 . The modifications permit the  FIG. 5  system  30  to be versatile in that it is capable of operating in both the mid-level for self-refresh or data retention mode and the GND precharge for mission mode as a function of particular clock signals generated by the clock  44 . 
   In the bi-mode sense amplifier system  30  of  FIG. 5  (as in  FIG. 1 ), during the data retention mode, when the LP signal causes the NFET N 5  to conduct, it connects node  55  to GND via line SPL. Thus node  55  and line SPL are separated from GND by the source/drain circuit of the NFET N 5  to prevent current burn in the Mid-Level (VDD/2) data retention mode, or self-refresh mode of operation of the bi-mode system  30 , that is controlled by timing pulses from clock  44  in the timing diagram of  FIG. 6B . 
   The equalization short circuiting control signal line ESL for equalization pulses ESP from the clock  44  is connected to NFET N 3  of the modified equalization short-circuiting and grounding circuit EM. The equalization control signal lines P 1  and P 0  for equalization-and-grounding pulses EGP 0  and EGP 1  from clock  44  are connected respectively to NFETs N 2  and N 4  of the modified equalization short-circuiting and grounding circuit EM. The equalization-and-grounding pulses EGP 0 /ESP/EGP 1  are separated and EGP 0 /EGP 1  are kept low to disable GND precharge in the mid-level data retention mode whereas the equalization signal ESP from the clock  44  is actively controlled to shorten BT and BC as shown in the signal timing diagram of  FIG. 6B . 
   In the bi-mode grounding and/or short-circuiting equalization system  30  of  FIG. 5 , the equalization-and-grounding pulses EGP 0  and EGP 1  are supplied on lines P 0  and P 1  to gates of NFET N 2  and NFET N 4  respectively and short-circuiting signal ESP is supplied on line ESL to the gate of NFET N 3 . When operating in the mid-level VDD/X self-refresh, data retention mode, the grounding equalization signals EQP 0  and EQP 1  remain OFF as shown by the timing diagrams in  FIG. 6B , whereas the short-circuiting signal ESP is ON from time t 0 (tl) to time ta(tA) in each cycle of operation. On the other hand, when operating in the GND, mission mode of  FIG. 6A , all of the equalization signals EQP 0 , EQP 1  and EQP are ON from time t 0 (tl) to time ta(tA). This change in the equalization timing signals is a factor in a switch between the mid-level VDD/X self-refresh, data retention mode and the mission mode operation of bi-mode sense amplifier  30  of  FIG. 5 . 
   Gating a mid-level potential VREFX onto the source/drain circuits of equalization short-circuiting circuit ESR in  FIG. 1  or a ground potential GND onto the source/drain circuits grounding-short-circuiting equalization circuit ESG in  FIG. 3 , unacceptably degrades GND prechage performance. Instead, in  FIG. 5  bi-modal sense amplifier system, a mid-level potential VREFX is applied to the bitlines by altering the Reference Wordline Decode system and utilizing either the reference cells RC 0 /RC 1  as the bitline precharge device for bitline BT 0  or bitline BC 0  respectfully. 
   Referring to the circuit  30  of  FIG. 5  and the timing diagram in  FIG. 6B  of the mid-level VDD/X self refresh, or data retention mode of operation, during a precharge cycle from t 0  to tb; from ti to tB and from tl to tb, both reference word-lines WL 0  and WL 1  which supply signals RWL 0  and RWL 1  and both reference equalize controls signals REQ 0  and REQ 1  on lines Q 0  and Q 1  are active, providing the mid-level potential VREFX to the bitlines via reference cells RC 0  and RC 1 . During each active cycle (which follows the precharge cycle e.g. from time tb to tk and tB to tL) of mid-level VDD/X data retention mode, the reference word-line signals RWL 0 , RWL 1  and reference wordline equalization signals REQ 0 , REQ 1  on lines Q 0  and Q 1  in  FIG. 5  are selectively controlled as shown in  FIG. 6B  to provide VDD/X to bitlines BT and BC. When accessing NC 0  from time tB to tL by activation signal RWA on line WLA, the signals RWL 0  and REQ 1  on lines WL 0  and Q 1  are disabled while the clock  44  keeps signals RWL 1  and REQ 0  on lines WL 1  and Q 0  “High”. Thus, keeping signal RWL 1  “High” can balance the bitline capacitors between lines BT 0  and BC 0 . 
   Reference cells RC 0  and RC 1  are used in conjunction with clock signals from the clock  44  to provide the bitline precharge function. The signal REQ 0  on line Q 0  is ON except from time tb to time ti. The signal RWL 0  on line WL 0  is ON from time tB to time tl. The signal REQ 1  on line Q 1  is ON except from time tB to time tl. The signal RWL 1  on line WL 1  is ON from time tb to time ti. When the bi-mode sense amplifier  30  of  FIG. 5  is operating in the mission mode, the unselected signal RWL 1  on  FIG. 5  reference word-line WL 1  is OFF continuously until time tB in  FIG. 6A . The signal RWL 0  on selected wordline WL 0  is OFF from time t 0  to time tb and transitions to ON from time tb to time tc remaining ON from time tc to time ti and transitioning to OFF at time ti, remaining OFF until time tb in the next cycle. On the other hand, the reference wordline equalize control signal REQ 0  on line EQ 0  is ON from time tl to time tb transitioning to the inactive OFF state starting from time tb to time tc. It remains OFF from time tc to time ti when it transitions to ON at time ti. It remains ON until time tb in the next cycle. This transition provides the dynamic bitline balancing desired to offset the active word-line coupling. Thus signals REQ 0  and RWL 0  have complementary waveforms with one being ON while the other is OFF. In the mission modes of  FIG. 5 , the signal RWL 1  is OFF continuously and the signal REQ 1  is ON continuously. 
   SECOND EMBODIMENT 
     FIG. 7  is the schematic diagram of a second embodiment of the present invention in which a combination of a clock  64  and a bi-mode sense amplifier system  40  includes dual precharge circuits, which is a modification of the bi-mode sense amplifier system as shown in  FIG. 5 . The true normal cell NC 0  and the complementary normal cell NC 1  are the same as in  FIG. 1 . Reference cell RC 0  and reference cell RC 1  are the same as in  FIG. 3 . 
     FIG. 7  is a schematic diagram of the combination of a clock  64  a dual precharge circuit  40  which includes a sense amplifier SA, plus thirteen other MOSFETs or two more FETs than for  FIG. 5 . The sense amplifier SA can be identical to the sense amplifier SA shown in  FIG. 1  or can be modified to include another equivalent sense amplifier circuit. 
     FIG. 8  shows the signal timing diagram of wordline, equalization signal, equalization pulse, true bitline and complementary bitline potentials applied to and generated in the circuit of  FIG. 7 . 
   In  FIG. 7 , as in  FIG. 5 , the MOSFET system  40  includes wordlines WLA/WLB, reference wordlines RWL 0 /RWL 1 , reference wordline equalization-and-grounding lines REQ 0 /REQ 1 , a bitline BT 0 , a complementary bitline BC 0 , a sense amplifier SA with SNL and SPL input lines thereto, a SETN input on line LN for actuating PFET P 2  to connect voltage VDD to the SNL input line to sense amplifier SA via node  54 , a SETP input for actuating NFET N 5  to connect sense amplifier SA via node  55  and the SPL input line to ground potential. Also there is a reference voltage source VREFX which has a value between the voltage of the power supply voltage VDD and ground (reference potential). In addition there is a true normal cell NC 0  which includes an NFET N 15  and a storage capacitor CS 0 . A complementary normal cell NC 1  includes an NFET N 14  and a storage capacitor CS 0 . A true bitline reference cell includes NFETs N 6 /N 7  and capacitor C 1 . A complementary normal cell NC 1  includes NFETs N 8 /N 9  and capacitor C 2 . 
   The embodiment of the invention shown in  FIG. 7  is different from the embodiment of  FIG. 5  in that system  40  includes a VREFX equalization circuit ESR including equalization NFETs N 2 , N 3  and N 4  which is similar to or possibly identical to the VREFX equalization circuit ESR shown in  FIG. 1 . Unlike the embodiment of  FIG. 5 ,  FIG. 7  employs VREFX-short-circuiting equalization circuit ESR of  FIG. 1  which comprises three equalization NFETs N 2 , N 3  and N 4  which have their gates connected via node  51  to be turned ON when they receive the reference potential equalization pulse ERP on the reference potential equalization line ERL as described above with respect to  FIG. 1 . 
   The embodiment of the invention shown in  FIG. 7  is also different from what is shown in previous drawings herein as it includes an additional equalization circuit comprising an equalization-and-grounding circuit EG which includes to two discharge NFETs N 11  and N 12 . 
   The source of the NFET N 11  is connected to node  3 T. The source of the NFET N 12  is connected to node  3 C. The drains of the two discharge NFETs N 11 /N 12  are connected to GND via node  52 . The gates of two discharge NFETs N 11 /N 12  of the equalization-and-grounding circuit EG are connected via node  63  to be turned ON when they receive equalization-and-grounding pulses EGP from the clock  64  on the equalization-and-grounding line EGL discharging the capacitors CT and CC. When the equalization-and-grounding pulses EGP on line EGL are connected to the gates of the two discharge NFETs N 11 /N 12  their source drain circuits conduct thereby connecting the nodes  3 T and  3 C to GND and short circuiting them together which discharges complementary bitline BC 0  and true bitline BT 0 , thereby equalizing the potential thereon at GND potential. 
   Mission Mode of Operation 
   Referring to  FIG. 8  in the mission mode of operation there are two positive equalization-and-grounding pulses EGP generated on equalization-and-grounding line EGL. The EGP pulses are generated for the purpose of discharging true bitline BT 0  and complementary bitline BT 0  to ground GND. The EGP pulses are generated in the mission mode from time t 0 –t 1  and from time t 6 –t 8 . During those time periods, those pulses cause equalization grounding circuit EG to operate in response to an equalization-and-grounding pulses EGP connected thereto on the equalization-and-grounding line EGL via node  63  to energize the gates of the two discharge NFETs N 11 /N 12 . The result is that when the equalization-and-grounding pulse EGP on equalization-and-grounding line EGL is high, NFETs N 11 /N 12  turn ON thereby discharging both true bitline capacitor CT and complementary bitline capacitor CC by connect-ing nodes  3 T and  3 C via source drain circuits of discharging NFETs N 11 /N 12  to GND so that both plates of true bitline capacitor CT and complementary bitline capacitor CC are at or near GND potential in response to each equalization-and-grounding pulse EGP on equalization-and-grounding line EGL. 
   When at time t 1 , the first equalization-and-grounding pulse EGP on equalization-and-grounding line EGL goes to its OFF state and both wordline WL and RWL 1  are ON, then cell access starts. The true bitline BT 0  and complementary bitline BC 0  change their voltages from times t 1  to t 3  following stored voltages on storage capacitor CS and complementary bitline reference cell capacitor CC respectively. The voltage levels V 2  on both true bitline BT 0  and V 1  on complementary bitline BC 0  are maintained until time t 4  when true bitline BT 0  rises towards a maximum value V 3  and complementary bitline BC 0  drops towards voltage V 4 . 
   The voltages V 3 /V 4  are reached on the true bitline BT 0  and the complementary bitline BC 0  respectively at time t 5  and are maintained until time t 6  when a second equalization-and-grounding pulse EGP is applied to equalization-and-grounding line EGL causing the voltage on the true bitline BT 0  and the complementary bitline BC 0  to reach GND once again at time t 7  remaining at that level until the end of the mission mode cycle. 
   At time t 1  the wordline WLA and reference wordline RWL 1  are turned ON and remain on until time t 6  when both wordline WLA and line RWL 1  are turned OFF simultaneously with the rise of equalization-and-grounding pulse EGP on line EGL. During the self-refresh precharge time from t 1  to t 4 , reference wordline equalizing signal REQ 1  is turned OFF but line RWL 1  raises the gate of NFET N 9  which conducts so that the reference cell node of complementary bitline reference cell capacitor C 2  which was refreshed previously charges line BC 0  to the reference potential V 1  (VREFX). 
   When at time t 12 , each of the equalization-and-grounding pulses EGP on the equalization-and-grounding line EGL returns to an OFF state and both signal RWA wordline on line WLA and signal RWL 1  are ON, then cell access starts. The true bitline BT 0  and the complementary bitline BC 0  change their voltages from times from times t 13  to t 14  following the stored voltages on storage capacitor CS and complementary bitline reference cell capacitor CC respectively. The voltage levels V 2 /V 1  on both BT 0  and BC 0  are maintained until times t 4 /t 15  when the true bitline BT 0  begins to rise to a maximum value V 3  and complementary bitline BC 0  begins to drop to voltage V 4 . 
   During operation in the mission mode the reference potential equalization pulse ERP remains off continuously from t 0  to t 8  so that the true bitline BT 0  and the complementary bitline are never charged to VREFX, when the system of  FIG. 7  is operating in the mission mode. 
   Data Retention or Self-Refresh Mode of Operation 
   Referring again to  FIG. 8  operation in the self-refresh mode starts at time t 8 . At times t 8 , t 12 , and t 21  in the self-refresh mode of operation, the equalization-and-grounding pulse EGP on line EQL is OFF or turns OFF so that the VREFX power source is disconnected from both true bitline line BT 0  and complementary bitline line BC 0 , since there is no conduction through NFETs N 2 , N 3  and N 4  of the VREFX equalization circuit ESR nor is there equalization of voltage on the true bitline BT 0  and the complementary bitline BC 0 . 
   From time t 8  to t 10  and from time t 17  to t 19 , when the reference potential equalization pulse ERP on the reference potential equalization line ERL is high to enable the precharge process during two periods, when the signal RWA on the wordline signal on line RWL 1  is turned OFF, the potential on the gates of all three of the NFETs N 2 , N 3  and N 4  (of the VREFX equalization circuit ER) rises causing them to conduct. The NFET N 3  turns on creating a short circuit between the true bitline BT 0  to the complementary bitline BC 0  equalizing the voltage thereon by transferring the charge between the true bitline capacitor CT and a complementary bitline capacitor CC. At the same time the NFETs N 2  and N 4  connect the true bitline BT 0  and the complementary bitline BC 0  via node  58  and line  11  to the voltage of VREFX for the purpose of charging the true bitline BT 0  and complementary bitline BC 0  to the voltage of VREFX. The equalizing charge flows through line  11 , nodes  59 ,  58 ′ and  58 , the source/drain circuits of NFETs N 2  and N 4 , then through nodes  5 T and  5 C and the complementary bitline BC 0 , true bitline BT 0  to change the charge on capacitors CT and CC during the equalization phase of operation. Thus the reference potential equalization pulse ERP on the reference potential equalization line ERL adjusts the precharges on true bitline capacitor CT and complementary bitline capacitor CC by raising the potential on both true bitline BT 0  and complementary bitline BC 0  to a voltage VREFX where it is maintained from time t 9  to t 10  and from time t 18  to t 19  in response to pulses EGP that begin at times t 8 , and t 17  in  FIG. 8 . The precharge power supply for voltage VREFX can be the same power as that which is applied to the same voltage regulator as that supplies a voltage level to the reference cells. 
   In the self-refresh mode, at times t 10  and t 19 , the reference potential equalization pulse ERP on reference potential equalization line ERL turns OFF disconnecting VREFX power from both true bitline line BT 0  and complementary bitline line BC 0 , by terminating conduction through NFETs N 2 /N 3 /N 4  of the VREFX equalization circuit ESR and thereby again terminating the equalization of voltage on true bitline BT 0  and complementary bitline BC 0 . 
   Simultaneously, with the end of the reference potential equalization pulse ERP at times t 10  and t 19 , the gates of the two discharging NFETs N 11 /N 12  of equalization-and-grounding circuit EG receive equalization-and-grounding pulses EGP via node  63  from the equalization-and-grounding line EGL. Referring to  FIG. 8 , the pulses EGP on equalization-and-grounding line EGL continue in the self-refresh mode first from time t 10  to t 12  and later from time t 19  to t 21 . Equalization-and-grounding pulses EGP are generated for the purpose of discharging the true bitline BT 0  and the complementary bitline BC 0  and capacitors CT and CC to ground. The result is that when an equalization-and-grounding pulse EGP on line EGL is high, the discharging NFETs N 11 /N 12  discharge both the true bitline capacitor CT and the complementary bitline capacitor CC by connecting the nodes  3 T and  3 C via source drain circuits of the discharging NFETs N 11 /N 12  to ground GND. Thus both plates of the true bitline capacitor CT and both plates of the complementary bitline capacitor CC are at or near ground potential in response to each discharge pulse signal EGP on equalization-and-grounding line EGL. 
   Simultaneously, at times t 10  and t 19  with the turning off of reference potential equalization pulse ERP, clock  64  generates an equalization-and-grounding pulse EGP on equalization-and-grounding line EGL that raises the potential on the gates of grounding/discharge NFETs N 11 /N 12  thereby discharging both of true bitline line BT 0  and complementary bitline line BC 0  to GND, which a short time ago had been precharged to VREFX from times t 9  to t 10  and from times t 18  to t 19 . Shortly after times t 10  and t 19  at times t 11  and t 20 , true bitline BT 0  and complementary bitline BC 0  have discharged to GND. 
   At time t 12 , wordline WLA and reference wordline RWL 1  turn ON and remain ON until time t 17  when both wordline WLA and line RWL 1  turn OFF simultaneously with the rise of the equalization-and-grounding pulse EGP on line EGL. During the self-refresh precharge time from t 8  to t 12 , reference wordline equalizing signal REQ 1  is turned ON which raises the gate of NFET N 9  which conducts so that the reference cell node of complementary bitline reference cell capacitor C 2  is refreshed by charging it to the reference potential VREFX. 
   From times t 12  to t 17  in the self-refresh mode the signal RWA on wordline WLA is up, raising the gate of NFET N 15  in the normal cell NC 0  to turn it on so the true bitline BT 0  which has been amplified to the “1” data voltage V 2  (VDD/X) from ground voltage GND, at time t 13 , charges the storage capacitor CS 0  to voltage V 2  (VDD/X). This amplification is done by the bitline sense amplifier SA. At the same time the complementary bitline BC 0  is charged to voltage V 1 . 
   When at time t 12 , each of the equalization-and-grounding pulse EGP on the equalization-and-grounding line EGL returns to an OFF state and both signal RWA wordline on line WLA and signal RWL 1  are ON, then cell access starts. True bitline BT 0  and complementary bitline BC 0  change their voltages from times from times t 13  to t 14  following the stored voltages on storage capacitor CS and complementary bitline reference cell capacitor CC respectively. The voltage levels V 2 /V 1  on both BT 0  and BC 0  are maintained times t 4 /t 15  when the true bitline BT 0  begins to rise to a maximum value V 3  and complementary bitline BC 0  begins to drop to voltage V 4 . 
   The voltages V 3 /V 4  are reached at time t 16  and are maintained until time t 17  when the second reference potential equalization signal ERP is applied to reference potential equalization line ERL causing the voltages on true bitline BT 0  and complementary bitline BC 0  to converge on VREFX once again by the operation of the VREFX equalization circuit ESR as described above. In a similar manner and voltages V 3 /V 4  are reached at time t 16  and are maintained until time t 17  in the self-refresh mode. 
   During self-refresh mode the cycle of from t 10  to t 17  and from time t 19  to t 21  the reference potential equalization pulse ERP remains off. The bitline precharge level drops from VREFX to GND dynamically from time t 10  to time t 12  and from time t 19  to time t 21 . 
   THIRD EMBODIMENT 
     FIG. 9  is a schematic diagram of a third embodiment of the present invention in which a bi-mode sense amplifier system includes a MOSFET dual precharge circuit, which show a modification of the system as shown in  FIG. 7 . The true normal cell NC 0  and the complementary normal cell NC 1  are the same as in  FIG. 1 . The reference cell RC 0 , and the reference cell RC 1  are all the same as in  FIG. 3   
     FIG. 9  shows a modification of the circuit of  FIG. 7  including a clock  84  and a system  50 . System  50  includes fourteen transistors and four capacitors. The circuit inside the sense amplifier block SA can be identical to the sense amplifier SA shown in  FIG. 1  or can be modified to include another equivalent sense amplifier circuit. Instead of the three equalization NFETs N 2 , N 3  and N 4  of the VREFX reference potential equalization circuit ESR in  FIG. 7  that are tied to operate in response to the equalization signal on line EQS, in  FIG. 8  there is a shorting equalization circuit ES which includes only one NFET N 3 . The shorting-equalization circuit ES is connected to operate in response to shorting-equalization pulse ESP on shorting-equalization line ESL to equalize the voltages on true bitline BT 0  and complementary bitline BC 0 . 
   During the active cycle time of self refresh mode from time t 16 –t 17 , true bitline BC 0  and complementary bitline BC 0  are amplified to V 3 =VDD/2 and V 4 =GND or V 4 =GND and V 3 =VDD/2 by sense amplifier SA. 
   During the precharge time of self refresh mode from time t 8  to t 10  and t 17  to t 19  in  FIG. 10 , the true bitline BT 0  and complementary bitline BC 0  are kept at voltage VDD/2 (instead of VREFX) without any power supply by shunting, i.e. short circuiting true bitline BT 0  and complementary bitline BC 0  together. The reason that the voltage is VDD/2 is that the one true bitline capacitor CT will have been at GND and the other bitline capacitor CC will have been at the potential VDD or vice versa, so the average of those two voltages is ½ VDD, i.e. VDD/2. 
     FIG. 10  shows the timing diagram and signal levels for the system of  FIG. 9 . The roles and timing of all of the signals are same as in  FIG. 8  except for the precharge level during the refresh mode. 
   While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.