Abstract:
Techniques are disclosed for employing a set of stream processors to greatly accelerate common video encoding and transcoding tasks, with the goal of making these tasks run at a reasonable rate on off-the-shelf hardware. Stream processors are most commonly found in the graphics processing unit (GPU), a commodity piece of computer hardware used to generate images for display. Embodiments of the invention are particularly advantageous to accelerate video encoding and transcoding tasks in which the blocks being processed have dependencies on their neighboring blocks.

Description:
RELATED APPLICATIONS 
     This application claims priority from U.S. Provisional Application No. 60/964,340 filed Aug. 9, 2008 and incorporated herein by this reference. 
    
    
     COPYRIGHT NOTICE 
     Copyright© 2007-2008 Elemental Technologies, Inc. A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever provided under at least 37 CFR §1.71(d). 
     TECHNICAL FIELD 
     Digital video processing, namely compression, decompression and transcoding especially using stream processors of a GPU. 
     BACKGROUND 
     Processing compressed digital video requires an enormous amount of computational horsepower. Modern central processing units (CPUs) are not keeping up with the demand for horsepower, resulting in the slow processing of video compression and processing tasks. This result has different ramifications for different users. For high-end professionals and broadcast infrastructure applications, specialized hardware is currently used. This hardware is produced in low volumes and thus tends to be expensive. On the other hand, for video editing hobbyists and average consumers, it is unusual to purchase expensive hardware to augment an off-the-shelf personal computer. Instead, these users rely entirely on the computer&#39;s CPU to sequentially perform the tasks. This runs much slower than real-time, causing the user to wait long periods of time for basic operations like converting a video file from one format to another. 
     Moving to a parallel architecture has the potential to accelerate many of these tasks. However, significant parallelization is difficult to achieve because block-based codec algorithms require some serialization due to the requirement for neighbor blocks to have been coded prior to the current block. Multiple blocks cannot be processed at the same time because each relies on information from neighboring blocks, which may not have been processed yet. Operations such as intra prediction, motion estimation and compensation, and deblocking are just a few examples of block-based algorithm calculations which rely on neighboring blocks. Utilizing stream processor architectures with conventional algorithms provides no performance increase for these operations. 
     The need remains therefore for improvements in video processing to achieve improvements in performance, especially speed, while leveraging relatively low-cost hardware. Several preferred examples of the present application will now be described with reference to the accompanying drawings. Various other examples of the invention are also possible and practical. This application may be exemplified in many different forms and should not be construed as being limited to the examples set forth herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a conceptual diagram of a region of a coded video frame illustrating neighboring 16×16 macroblocks. 
         FIG. 2  is a conceptual diagram of the region of  FIG. 1  illustrating macroblock X partitioning into 4×4 sub-blocks. 
         FIG. 3  is a conceptual diagram of the frame of  FIG. 1  illustrating a low-angle sweep order consistent with one embodiment of the invention. 
         FIG. 4  is a conceptual diagram illustrating 45-degree sweep technique consistent with an alternative embodiment of the invention. 
         FIG. 5  is a conceptual illustration of processing predictions and transforms using two kernels; one sweep for prediction, and 8 sweeps for transforms. 
         FIG. 6  is a simplified block diagram a processor array showing multiple blocks of processors arranged for SIMD operations. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Block based video compression, especially H.264, takes advantage of correlations of any given block to surrounding neighbor blocks by predicting a block based on the neighbor blocks. 1  Intra-frame prediction is calculated generally in the following manner (we will describe the process for luma blocks, but chroma is processed in a similar fashion). A prediction (for the current block) is formed based on previously encoded neighboring blocks in a reconstructed frame. 2  This block is subtracted from the current block prior to encoding, and for the luma case may be formed for each 16×16 macroblock or 4×4 partitions inside the macroblock. In the 4×4 partitioning case, there are 9 optional prediction modes that can be applied, while in the 16×16 macroblock case, there are 4 optional modes. The difference between the actual block and the prediction is called the residual macroblock, and the residual is what is encoded and sent to a decoder. A similar process is applied to every macroblock of the frame. Inter-frame prediction works in a similar manner, but the prediction is based on motion from previously encoded frames.  1  ITU-T Recommendation H.264; a video coding standard. Also called Advanced Video Coding or “AVC”. 2  Reconstructed frame is the one that is currently being encoded. It becomes the reference frame for the next picture. 
     To illustrate the intra-frame prediction 16×16 pixel macroblock case, see  FIG. 1 . Macroblock X is the macroblock under analysis for best compression. Surrounding macroblocks A ( 102 ), D ( 103 ), and B ( 104 ) are used for the four different prediction options, which are listed on the right, namely: Vertical, Horizontal, DC, and Plane. For example, in the Vertical mode, the bottom row of pixels  108  from Macroblock B are extended downward and compared with the pixels in Macroblock X. The Sum of Absolute Differences (SAD), or the Sum of Absolute Transform Differences (SATD) is computed, and then these results are compared with the results of the other three prediction options. Using the option that has the lowest difference (SAD or SATD) will result in the highest compression ratio. Thus, the best match is chosen as the predictor for the current Macroblock X. Further details of these prediction modes are known. SATD has been shown to give the best resulting compression, but for simplicity of explanation, we will refer to SAD. It is used by way of illustration and not limitation. 
     To illustrate the 4×4 block partitioning case, see  FIG. 2 . Macroblock X has now been divided up into 16 4×4 sub-blocks. Each sub-block preferably uses pixels from the left and top sides to predict the contents of the current sub-block using the SAD metric. For example, in horizontal prediction mode, the four pixels to the left from block A′ ( 202 ) will be used to calculate the SAD for block X′  201  by replicating those pixels horizontally across by 4 pixels creating a 16 pixel block. This process may be repeated for one or more of the other eight prediction modes, and the option that generates the lowest SAD (or other selected metric) will be selected. The 4×4 Luma Prediction Modes are: (1) Vertical, (2) Horizontal, (3) DC, (4) Diagonal Down-Left, (5) Diagonal Down-Right, (6) Vertical-Right, (7) Horizontal-Down, (8) Vertical-Left, and (9) Horizontal-Up. 
     To obtain the best compression performance, the Sum of Absolute Differences must be performed for each prediction mode for the 16×16 macroblock and for the 4×4 sub-block. Implementation of these calculations on a sequential processor such as a CPU processes each macroblock in raster scan order (i.e. from left to right, processing row 0, then row 1, row 2, etc). 
     Inter-frame block prediction requires searching each block of pixels for a matching block of pixels closest to the predicted motion vector in any cached reference frame. Again. SAD or SATD is used to find the best matching block. This process is called motion estimation and is a valuable tool in video compression. Motion is highly correlated to neighboring blocks and thus the predicted motion vector is calculated with neighboring block motion vectors, thus creating yet another dependency on neighboring blocks from the block currently being encoded. Moreover, macroblocks may be partitioned at least four different ways and motion compensated either as one 16×16 macroblock partition, two 16×8 partitions, two 8×16 partitions or four 8×8 partitions. In the 8×8 mode, each of the four sub-macroblocks may be further split in four ways. There are many possible combinations, and a separate motion vector is required for each partition or sub-macroblock, all of which presents an imposing processing challenge to meet reasonable timing constraints. 
     After predictions are calculated, the next step in video compression is transforming the residuals into a frequency representation of the data (such as DCT) and then quantizing the high frequency content away before entropy encoding of the result. These processes as well are computationally expensive. We have discovered techniques to improve parallelism of these kinds of processes. 
     Accordingly we disclose herein various implementations that enable efficient processing of macroblocks with neighboring block dependencies, utilizing highly parallel stream processing architectures. Various embodiments will offer tradeoffs between compression efficiency and parallelism. To illustrate, our examples focus on a modern block-based image compression format variously known as H.264, Advanced Video Codec (AVC), or MPEG-4 Part 10. For the purposes of this document, we will use “AVC” to refer to the format. 
     There are several computationally-intensive portions of the AVC compression or decompression processes where the current block being processed has dependency on neighboring blocks. We mentioned several of these processes above. Specifically, these include block predictions (inter- and intra-frame) and the block transforms (which include the forward DCT transform, quantizing, inverse quantizing, and inverse DCT transform of each block). One aspect of the present invention addresses these processes using any stream processor-based architecture that includes a mechanism for scheduling software threads to run on any of the available processors, and in which data can be shared among blocks of processors for SIMD (single instruction, multiple data) type of execution. For example, the most commonly available stream processor architectures are those implemented on commercially available graphics processing units (GPUs) such as those from NVIDIA of Santa Clara, Calif. Commercially available units offer, for example, 64 or 128 processor cores. 
       FIG. 6  is a simplified block diagram one example of a processor array showing multiple blocks of processors arranged for SIMD operation. The illustrated array contains one or more groups of homogeneous multipurpose SIMD multiprocessors that are designed to operate on highly parallel problems where many processors can work in parallel. Each multiprocessor or block of processors contains one or more SIMD (Single Instruction Multiple Data) processors, and also contains a memory cache (illustrated as RAM but may be other types of cache) enabling fast access and communication between each SIMD processor in the multiprocessor. There is also, in the illustrated embodiment, a random access memory (RAM) shared by all multiprocessors in the array, that may be used to store the video frames, macroblock coefficient data, macroblock metadata, and multiprocessor instructions. There is also illustrated a sequencer and memory arbiter to automatically and efficiently select processors to execute a set of instructions. 
     In one presently preferred embodiment, predictions and transforms are solved using stream processors as illustrated conceptually in  FIG. 3 . In processing the frame of  FIG. 3 , for example, a block of SIMD processors is allocated for each macroblock, and N threads of software run on each block of processors to generate the predictions, residuals, and SADs, and all transforms and inverse transforms for 256 pixels (16×16) of luma data. Thus the total number of threads running concurrently may be up to N times the number of allocated blocks of processors. Another similar block of SIMD processors are allocated to process each chroma macroblock in a similar manner. 
     The integer N (number of threads) will vary, depending on the particular implementation and the specific process running at a given time. In some cases, N may be a multiple of 32. We have discovered that N=64 is a preferred arrangement for each phase of the encoding: prediction, transforms, and reconstruction. Each phase of the encoding may have a different allocation of the threads to the problem. In the case of the DCT calculation, for example, each thread preferably calculates the matrix multiplication for 4 pixels (first a column of 4 pixels, then a row). 
     The threads and their respective tasks are divided up so that they do not conflict with each other during calculations. To illustrate, a 16×16 block may be partitioned into 16 4×4 blocks, each sub-block having 4 rows and 4 columns. There are thus 64 columns of 4 pixels, and one thread may be applied to each column for parallel execution. 
     Each phase of the codec must allocate threads in a similar manner, but each is unique in what each thread does and how many pixels are being operated on, and the number of processors available. 
     Sweep Processing a Full Frame 
     Allocated blocks of stream processors process a frame of video in a “sweeping” manner—a term we used to describe techniques for ordering the processing in order to maintain the neighbor dependencies required to code each block. For example,  FIG. 3  illustrates “sweep processing” of a frame of 5×5 macroblocks. This frame will be fully encoded with 12 processing sweeps. The sweep number is shown in the center of each macroblock. Each macroblock with the same sweep number will be processed concurrently by separately allocated SIMD processor blocks. 3  Thus, in sweep 2 for example, the two macroblocks located at row, column (0,2) and (1,0) are processed concurrently. A first set of SIMD processors are allocated to process macroblock (0,2) and a second set of processors are allocated to process macroblock (1,0). In sweep 4, where parallelism is maximized, there are three blocks of SIMD processors blocks processing three macroblocks concurrently. In one embodiment, there may be 64 threads applied to prediction calculations, as explained above, for each block. If the implementation hardware has sufficient resources, there may be 4×64 or 256 threads running on the processor concurrently during a sweep that includes four macroblocks.  3  Processor “blocks” refers to a set of processors; not to be confused with macroblocks of sample data. 
     The frame depicted in  FIG. 3  also contains blocks that have 4×4 prediction mixed with those that are 16×16. 4×4 predicted blocks (or other sub-blocks) may be processed with another sweep inside the macroblock within the larger sweep as shown in block  301 . In other words, each sub-block itself can be processed using the sweep concept that processes selected groups of pixels concurrently using multiple threads. 
       FIG. 3  shows a full “low-angle” implementation; this allows all prediction mode possibilities to be computed. The dark shade is the current sweep and shows how 4×4 blocks can be processed at the same time as 16×16 blocks. Instead of processing macroblocks in raster scan order, a diagonal sweep is performed. In the first sweep, only Macroblock (0,0) is processed. In the second sweep, Macroblock (1,0) is processed. In the third sweep, however, Macroblocks (2,0) and (0,1) are processed (because there are multiple processors available, more than one macroblock can be processed at the same time). In the fourth sweep (number “3” in the drawing), Macroblocks (0,3) and (1,2) are processed. In the fifth sweep, Macroblocks (4,0), (3,1), and (2,0) are processed. This pattern continues for all the macroblocks in the image. 
     Parallelism continues to increase as the resolution increases; for example, for a 1080 p (1920×1080) resolution image, the speedup over a conventional implementation is 32 times. Once the transformed coefficients have been calculated and the reconstructed frame complete, the run-length encoded coefficients are sent to the CPU to complete the serial entropy encoding which is the final step in video compression. 
     In an alternative embodiment, a 45-degree diagonal sweep implementation may also be utilized as depicted in  FIG. 4 . In this implementation, two of the nine 4×4 prediction modes are not supported (mode 3, diagonal down-left and mode 7, vertical-left) and thus compression efficiency is compromised slightly. However, as there are fewer horizontal blocks that need to be processed before each new vertical row begins, the total number of sweeps is reduced (8 in this case vs. 12 for the other). 
     In the first sweep, Macroblock (0,0) is processed. In the second sweep, Macroblocks (1,0) and (0,1) are processed. In the third sweep, Macroblocks (2,0), (1,1), and (0,2) are processed, and so on. Again, the pattern continues until all the macroblocks in the image are processed. Using this diagonal method instead of the low-angle method results in a 36% increase in performance relative to the low-angle method, and 43 times faster than a conventional implementation. 
     Prediction Kernel Processing 
     Another way to gain more parallelism is to process the predictions and the transforms in two steps and allocate processors differently in each step. In this case, some minor compression efficiency is lost as the predictions are being made on a different set of data. A best-guess prediction can be made for all blocks in complete parallel without using a sweep by comparing the prediction block to the input block instead of the reconstructed reference block. 
     Motion vectors can also be found by searching in a window around the current block without using the predicted motion vector. This technique increases the overall speed of processing at the expense of compression efficiency by allowing more threads to run concurrently to select the proper prediction. This prediction selection for each block is then sent to the transform kernel (described below) which may be processed in a sweep as described previously to produce the coefficients used in the entropy encoding. 
     This technique is illustrated conceptually in  FIG. 5 . All blocks in the frame  501  are predicted in one step, including motion estimation for all blocks and 4×4 sub-partitions. Preferably all blocks are being processed in parallel utilizing as many processors as are available in that step. (Recall that in one “sweep” a separate set of processors is allocated to process each macroblock.) The order here is not critical; blocks may be processed out of order or in random order within a given sweep processing step. Macroblock (3,3) ( 503 ) is shown with a motion vector that was found to be a the best prediction in this example. 
     The results of the prediction kernel (prediction modes, prediction type, and motion vectors) for each block are then sent to a transform kernel. As illustrated in sample frame  502 , the transform kernel also applies a sweep processing technique and calculates the final coefficients to be sent to the CPU for entropy encoding. A diagonal sweep is illustrated. Any macroblock predicted using inter-frame prediction (such as the macroblock at (3,3)) can also be processed in sweep 0 because there is no dependence on neighboring macroblocks, only reference frames are required which have already been processed. As above, sets of processors are allocated, for example in a GPU, to each macroblock for processing. This technique dramatically increases parallelism and processing speed especially for P and B frames due to better use of the processors and more threads executing concurrently. 
     During a transcode operation such as MPEG2 to H.264, motion vectors from the original encoding may be available for cueing the motion estimation process. In this case, compression efficiency is gained as the previously coded motion vectors offer a good starting point for the motion estimation algorithms and are likely to be closer to the predicted motion vector resulting in less bits being used to encode it. 
     Thus we have seen that  FIG. 5  is a conceptual diagram showing processing a video frame in two steps employing a prediction kernel and a transform kernel. The prediction kernel preferably decides all prediction modes, types, and motion vectors for the frame as described above. The transform kernel preferably computes the forward DCT transform, quantized transform, inverse quantized transform and the reverse DCT. 
     The methods disclosed above can be applied to any block-based video compression system that requires information from neighboring blocks before a current block is processed. Beside intra-frame block prediction (the example described above), other processes to which various embodiments can be applied advantageously include motion estimation, in-loop deblocking, and rate control. In addition to AVC/H.264, many block-based codecs utilize these algorithms including VC-1, MPEG-2, Flash (or On2), and other video compression standards. 
     Digital Processors, Software and Memory Nomenclature 
     As explained above, the invention preferably is carried out by a digital computing system, for example a CPU working in tandem with a GPU. More specifically, by the term “digital computing system” we mean any system that includes at least one digital processor and associated memory, wherein the digital processor can execute instructions or “code” stored in that memory. (The memory may store data as well.) A digital processor includes but is not limited to a microprocessor, multi-core processor, DSP (digital signal processor). GPU, processor array, network processor, etc. A digital processor (or many of them) may be embedded into an integrated circuit such as a GPU. In other arrangements, one or more processors may be deployed on a circuit board (motherboard, daughter board, rack blade, etc.). Processors often form part of a larger device such as a laptop or desktop computer, a PDA, cell phone, iPhone PDA, Blackberry® PDA/phone, or indeed virtually any electronic device. The concepts of the present invention may be deployed to advantage in many of these various environments. Preferably, the methods may be implemented in software stored in memory, further defined below. In a GPU, processors may be arranged in groups, for example eight processors, for SIMD operation. One example of a multiprocessor array is illustrated in  FIG. 6 . 
     Digital memory, further explained below, may be integrated together with a processor, for example RAM or FLASH memory embedded in an integrated circuit CPU. GPU or the like. In other examples, the memory comprises a physically separate device, such as an external disk drive, storage array, or portable FLASH key fob. In such cases, the memory becomes “associated” with the digital processor when the two are operatively coupled together, or in communication with each other, for example by an I/O port, network connection, etc. such that the processor can read a file stored on the memory. Associated memory may be “read only” by design (ROM) or by virtue of permission settings, or not. Other examples include but are not limited to WORM, EPROM, EEPROM, FLASH, etc. Those technologies often are implemented in solid state semiconductor devices. Other memories may comprise moving parts, such a conventional rotating disk drive. All such memories are “machine readable” in that they are readable by a compatible digital processor. Many interfaces and protocols for data transfers (data here includes software) between processors and memory are well known, standardized and documented elsewhere, so they are not enumerated here. 
     Storage of Computer Programs 
     As explained above, the present invention preferably is implemented or embodied in computer software (also known as a “computer program” or “code”; we use these terms interchangeably). In some embodiments, we described program “threads” which are relatively simple programs. Multiple program threads typically can be executed concurrently in a block of SIMD processors, each processor in the block executing the same code on a different set of data. See  FIG. 6 . We also referred to a prediction kernel, and a transform kernel, each of which is a program. Programs, or code, are most useful when stored in a digital memory that can be read by one or more digital processors. We use the term “computer-readable storage medium” (or alternatively, “machine-readable storage medium”) to include all of the foregoing types of memory, as well as new technologies that may arise in the future, as long as they are capable of storing digital information in the nature of a computer program or other data, at least temporarily, in such a manner that the stored information can be “read” by an appropriate digital processor. By the term “computer-readable” we do not intend to limit the phrase to the historical usage of “computer” to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, we use the term to mean that the storage medium is readable by a digital processor or any digital computing system as broadly defined above. Such media may be any available media that is locally and/or remotely accessible by a computer or processor, and it includes both volatile and non-volatile media, removable and non-removable media, embedded or discrete. 
     Computer Program Product 
     Where executable code has been stored in a machine-readable storage medium for distribution, we may refer to that storage medium as a “computer program product.” For example, a portable digital storage medium may be used as a convenient means to store and transport (deliver, buy, sell, license) a computer program. Historically, this method was often used for retail point-of-sale delivery of packaged (“shrink wrapped”) programs. Examples of such storage media include without limitation CD-ROM and the like. Such a CD-ROM, containing a stored computer program, thus would be an example of a “computer program product.” In other cases, disks, tape, or other machine-readable storage media are used for distributing software from the owner or creator to an OEM for installation in the OEM&#39;s products, for example, to install embedded code into a video card or GPU prior to sale of that product. That “master” disk is again a computer program product. The receiving OEM typically would be licensed by the owner to make and distribute copies of the code in embedded form. Each such product then includes the code stored in machine-readable media, although generally the end product would not be considered a “computer program product” as the embedded code is not intended for subsequent transfer or installation in another product. 
     It will be obvious to those having skill in the art that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. The scope of the present invention should, therefore, be determined only by the following claims.