Abstract:
A signal processing system for absorbing asynchronism between a video signal and an audio signal which is caused when a PCM audio signal is to be recorded together with the video signal on a helical scan-type tape recorder. When the video signal and the audio signal are recorded on the same track, a recording band width of the audio signal should be narrow. A sample pattern is provided which assures rapid pull-in for both data clock reproduction and carrier reproduction, when the audio signal is modulated by QPSK or when Q-QPSK modulation is used.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a technique for recording and reproducing digital audio signal by a helical scan type video tape recorder together with a video signal. 
     2. Description of Prior Art 
     In a conventional helical scan type video tape recorder, a servo system is designed to synchronize with a vertical synchronization signal of a video signal. Accordingly, if a digital signal having a sampling frequency of 48 kHz, for example, is to be recorded together with the video signal, the number of samples of a digital signal in one vertical period is given by 
     
         48 K/59.94=800.8 
    
     Accordingly, a method has been proposed (JP-A-61-233472) in which a data frame which can contain 800+α samples in one vertical period is secured, the digital signal is sectioned by a period at which a vertical synchronization signal is synchronized with a sampling frequency of the digital signal to form one data frame, and it is recorded together with a rate signal representing the number of samples in one data frame. Assuming now that n samples of data are recorded in one frame, dummy data of &#34;0&#34; pattern is recorded for the remaining 800+α-n samples of data in order to keep the record rate constant. 
     The above prior art digital signal recording/reproducing apparatus is explained with reference to drawings. 
     FIG. 3 shows a configuration of the prior art digital signal recording/reproducing apparatus. In FIG. 3, numeral 21 denotes an input terminal for a digital information signal, numeral 22 denotes a time axis converter, numeral 23 denotes an encoder, numeral 24 denotes a format controller, numeral 25 denotes a modulator, numeral 26 denotes a recording amplifier, numeral 27 denotes a rotating head, numeral 28 denotes a reproducing amplifier, numeral 29 denotes a demodulator, numeral 30 denotes a reverse-formatting controller, numeral 31 denotes a decoder, numeral 32 denotes a time axis reverse converter, numeral 33 denotes an output terminal for a digital information signal, numeral 34 denotes a switch, and a, b, and c respectively denote a head switching signal, a first rate discrimination signal and a second rate discrimination signal. 
     The operation of the above prior art digital signal recording/reproducing apparatus is now explained. 
     The digital information signal having a sampling frequency of 48 kHz applied to the input terminal 21 is sectioned in the time axis converter 22 by a period at which the head switching signal a synchronized with a vertical synchronization signal of the video signal is synchronized by a sampling clock so that it is divided into 800 or 801 samples of data frame Hereinafter, they are called frame A and frame B, respectively. Since the head switching signal is used as a reference, an average number of samples in one data frame is given by 
     
         48 K/59.94=800.8 
    
     In the frame A, dummy data is inserted to make the number of samples conform to that of the frame B. A first rate discimination signal b is produced as information representing the number of samples in one data frame. The data output of the time axis converter 22 is interleaved by the encoder 23, and redundant data for error correction is added The output of the encoder 23, together with the first rate discrimination signal b, are converted to a predetermined record format by the formatting controller 24 which compresses it into data period for each data frame In an ample period, a fixed pattern having a number of inverted edges after data modulation is produced by the formatting controller 24 so that the demodulator 31 can quickly pull in the clock synchronized with the recorded data in the reproduction mode. FIG. 10 shows a conceptual view of the ample period and the data period. The modulator 25 modulates the output of the formatting controller by 8-10 conversion or NRZ conversion, and the modulated data is supplied to the rotating head 27 through the recording amplifier 26 and the switch 34, and recorded on a magnetic tape. 
     In the reproduction mode, the signal reproduced by the rotating head 27 is supplied to the demodulator 29 through the switch 34 and the reproducing amplifier 28, and processed in the reverse manner by the demodulator 29, reverse-formatting controller 30, decoder 31 and time axis reverse converter, and a digital information signal is produced at the output terminal 33. The reverse-formatting controller 30 detects from the reproduced signal a second rate discrimination signal c which represents the number of samples in one data frame, and the reverse-time axis converter 32 determines the data frame as either A or B based on the second rate discrimination signal c and carries out the reverse-time axis conversion. 
     FIG. 4 shows a configuration of the reverse-time axis converter 32. In FIG. 4, numeral 41 denotes a buffer memory, numeral 42 denotes a frequency divider, numeral 43 denotes a phase comparator, numeral 44 denotes a low-pass filter and numeral 45 denotes a voltage controlled oscillator. 
     The operation of the time axis reverse converter 32 is explained with reference to FIG. 4. The digital information signal which has been error-corrected and decoded by the decoder 31 is temporarily stored in the buffer memory 41. The frequency divider 42 receives the second rate discriminator c and frequency-divides the output clock of the voltage controlled oscillator 45 by 801 for the data frame B and by 800 for the data frame A. The phase comparator 43 compares phases of the head switching signal a and the output of the frequency divider 42 and produces a voltage proportional to the phase difference. The low-pass filter 44 eliminates a high frequency component and the voltage controlled oscillator 45 has its oscillation frequency controlled by the output voltage of the low-pass filter 44. The digital information signal is read from the buffer memory 41 by the output clock of 48 kHz from the voltage controlled oscillator 45 reproduced by the phase synchronization loop comprising the frequency divider 42, the phase comparator 43, the low-pass filter 44 and the voltage controlled oscillator 45. 
     In the above conventional digital signal recording/reproducing apparatus, when the vertical synchronization signal of the video signal is at 59.94 Hz, the number of samples in one data frame is 800 or 801 in principle. However, since the reproduced video signal of the VTR includes jitter, the vertical synchronization signal deviates from 59.94 Hz and the error amounts up to 0.5% as the damping is repeated. If the digital signal is recorded together with such a video signal, the number of samples in one data frame may assume one of the following multiple values ##EQU1## As a result, the rate information needs several bits to represent the multi-value information. 
     When the information thus recorded is reproduced, if the rate discrimination signal representing the number of samples is misdetected, for example, if the data frame having 800 samples is misdetected as the data frame having 801 samples, dummy data is included in the output digital audio data so that noise is generated. 
     In the time axis reverse converter, the phase synchronization loop for reproducing the sampling clock of 48 kHz of the digital data includes the frequency divider which has a large frequency division factor of around 800. As a result, a high loop gain is not attained and a phase pull-in time is long. 
     In addition, a band restriction condition is imposed because the recorded output of the digital signal recording/reproducing apparatus is recorded in the same track as the video signal track by frequency multiplexing or overwriting. Where a four-phase phase modulation (QPSK) or an offset four-phase phase modulation (O-QPSK) is used and a band-pass filter is used in the reproduction mode to pass only the predetermined frequency components to effect QPSK or O-QPSK demodulation, the following problems arise. 
     Assuming that f c  is a carrier frequency for the QPSK or O-QPSK modulation, f s  is a sampling frequency of digital data to be modulated, f c  ±f B  is a band-pass width of the band-pass filter (FIG. 5a) and an ample pattern is an all-&#34;1&#34; pattern, the band width after the modulation is given by ##EQU2## (FIG. 5b). When ##EQU3## the reproduced waveform cannot be extracted by the band-pass filter for the QPSK or O-QPSK demodulation because of group delay and phase distortion around a cutoff point of the band-pass filter. The QPSK or O-QPSK demodulation can be well attained if the ample pattern is an all-&#34;0&#34; pattern (which is all-&#34;1&#34; or all-&#34;0&#34; pattern after the NRZI conversion) because a spectrum after the modulation is that shown in FIG. 5c. However, the data clock is not reproduced because there is no reversal edge of a bit boundary in the reproduced data after the demodulation. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention provide a digital signal recording/reproducing apparatus which can simultaneously record a video signal and a digital signal in a helical scan type tape recorder while it absorbs asynchronism of the digital signal even if a vertical synchronization frequency of the video signal deviates from 59.94 Hz, and which, in the reproduction mode, if the discrimination of the rate discrimination signal which represents the number of samples, in one data frame is highly reliable and a misdiscrimination of the rate discrimination signal is made, processes data by regarding that data frame as a data frame having a minimum number of samples so that the generation of noise due to output of the dummy data is prevented even if the number of samples in one data frame is misdiscriminated. 
     It is another object of the present invention to provide a digital signal recording/reproducing apparatus having an ample pattern which is suitable for the QPSK or O-QPSK demodulation and for reproduction of a clock signal synchronized with the data after the demodulation. 
     It is another object of the present invention to provide a phase synchronization loop for reproducing a sampling clock of a time axis reverse converter, in which a phase pull-in time at the start of a circuit is short even if a frequency division factor is large. 
     In order to achieve the above objects, the digital signal recording/reproducing apparatus of the present invention comprises a time axis converter for receiving a digital information signal having an inherent sampling frequency, sectioning the digital information signal by a predetermined period related to a vertical synchronization signal of the video signal to form the digital information signal of each predetermined period into data frame having one of at least two numbers of samples, sequentially outputting data frames having the smaller number of samples with dummy data being added thereto in order to match the number of samples to the maximum number of samples, and producing a rate discrimination signal representing the number of samples of the digital information signal in the data frame; an encoder for receiving the data output of the time axis converter, interleaving the data output and adding error correction redundant data to the data output; a formatting controller for adding a header word including synchronization signal, block address and rate discrimination signal to each of m data blocks in one data frame; a reverse formatting controller for detecting m rate discrimination signals from m header words in one data frame; a discriminator for determining majority of the m rate discrimination signals, determining the number of samples in the data frame, and when the result of the majority process is questionable, outputting the smallest number of samples; and a time axis reverse converter for conducting a reverse process to that of the time axis converter in accordance with the output of the discriminator. 
     The formatting controller produces a predetermined fixed pattern during a predetermined period (ample period) including a switching point of a head of a helical scan type tape recorder and time-compresses the m data block header word during a period (data period) other than the ample period. The modulator includes a serial/parallel converter for converting the output of the formatting controller to 2-bit parallel data, first and second NRZI converters for NRZI-converting the 2-bit output of the serial/parallel converter, and a QPSK modulator for phase-modulating the outputs of the first and second NRZI converters by four-phase modulation or offset four-phase modulation. The predetermined fixed pattern is a repetitive pattern of n bits in which one odd bit and one even bit are &#34;1&#34; and the remaining bits are &#34;0&#34;. 
     The time axis reverse converter comprises a phase synchronization loop for receiving the head switching signal of the helical scan type tape recorder and the number of samples of the data frame discriminated by the reverse formatting controller and producing a read clock, and a buffer memory for receiving the digital information signal having error thereof corrected by the decoder and outputting it at a timing of the read clock produced by the phase synchronization loop. The phase synchronization loop comprises a phase comparator for comparing phases of the head switching signal and the output signal of the frequency divider, an out-of-phase detector for detecting when a phase error between the head switching signal and the frequency divider output signal is larger than a predetermined level, a low-pass filter for limiting a band of the output of the phase comparator, a voltage controlled oscillator having an oscillation frequency thereof controlled by the output voltage of the low-pass filter for supplying the oscillation frequency to the frequency divider, the frequency divider for frequency-dividing the output of the voltage controlled oscillator by a frequency division factor determined by the number of samples of the data frame discriminated by the reverse formatting controller, and a clear controller for the frequency divider. 
     According to the present invention: 
     (1) The absorption ability to the asynchronism of the digital data for the video signal is high, the reliability of the rate discrimination signal in the reproduction mode is high, and the generation of noise due to introduction of the dummy data into the output digital signal is prevented even if the rate discrimination signal is misdiscriminated. 
     (2) The ample pattern which is suitable for the QPSK or O-QPSK demodulation and for the data clock reproduction after the demodulation is attained. 
     (3) In the time axis reverse converter, when the phase of the head switching pulse deviates significantly from the phase of the frequency divider output, the out-of-phase detector detects the out-of-phase condition, clears the count of the frequency divider, and releases the clear at the next phase lock point. Accordingly, the phase pull-in time is reduced. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a configuration of a first embodiment of a digital signal recording/reproducing apparatus of the present invention, 
     FIG. 2 shows a configuration of a discriminator of the first embodiment, 
     FIG. 3 shows a configuration of a prior art digital signal recording/reproducing apparatus, 
     FIG. 4 is a recording conceptual view, 
     FIG. 5 (a-d) shows a frequency spectrum chart, 
     FIG. 6 shows a configuration of a second embodiment of the digital signal recording/reproducing apparatus of the present invention, 
     FIG. 7 shows a configuration of a time axis reverse converter in the first embodiment, 
     FIG. 8 shows a configuration of phase comparator, out-of-phase detector and frequency divider, 
     FIG. 9 shows a timing chart for explaining an operation of the phase comparator, out-of-phase detector and frequency divider, 
     FIG. 10 shows data format of reproduced data, and 
     FIG. 11 shows recording conceptual view of one data frame. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a configuration of a first embodiment of a digital signal recording/reproducing apparatus of the present invention. In FIG. 1, numeral 1 denotes an input terminal for a digital information signal having an inherent sampling frequency, and numeral 2 denotes a time axis converter which sections the input digital information signal by a predetermined period related to a vertical synchronization signal of a video signal to form the digital information signal into data frames having at least two different numbers of samples for each predetermined period, sequentially outputs data frames having dummy data added thereto for the data frames having smaller numbers of samples so that the number of samples matches to that of the data frame having the maximum number of samples, and produces a rate discrimination signal representing the number of samples of the digital information signal in each data frame. 
     Numeral 3 denotes an encoder which receives the data output from the time axis converter 1 and interleaves the data output and adds error correction redundant data to the data output, numeral 4 denotes a formatting controller which adds a header word including a synchronization signal, a block address and the rate discrimination signal to each of m data block in each data frame, numeral 5 denotes a modulator which modulates the output of the formatting control circuit 4 by a predetermined modulation rule, numeral 6 denotes a recording amplifier, numeral 7 denotes a rotating head, numeral 8 denotes a reproducing amplifier, numeral 9 denotes a demodulator, numeral 10 denotes a reverse formatting control circuit for detecting m rate discrimination signals from m header words in one data frame, numeral 11 denotes a decoder, numeral 13 denotes a discriminator which determines majority of the m rate discrimination signals to determine the number of samples in the data frame, and if the result of the majority decision is questionable, outputs the minimum number of samples, numeral 12 denotes a time axis reverse converter which carries out the reverse process to that of the time axis converter 2 in accordance with the discrimination result, numeral 14 denotes a digital information signal output terminal, numeral 15 denotes a switch, and a, b, c, d and e denote head switching pulse, first, second and third rate discrimination signals, and parity check error detection signal, respectively. 
     FIG. 2 shows a configuration of the discriminator 13 of the first embodiment of the digital signal recording/reproducing apparatus. In FIG. 2, numeral 131 denotes an input terminal for the second rate discrimination signal c, numeral 132 denotes a first counter, numeral 133 denotes a second counter, numeral 134 denotes a first comparator, numeral 135 denotes an input terminal for the parity check error detection signal e, numeral 136 denotes a third counter, numeral 137 denotes a second comparator, numeral 138 denotes an AND gate, and numeral 139 denotes an output terminal for the third rate discrimination signal d. 
     The operation of the above digital signal recording/reproducing apparatus is now explained with reference to FIGS. 1 and 2. 
     The digital information signal having a sampling frequency of 48 kHz, applied to the input terminal 1 is sectioned to data frames having 800+α samples or 800-β samples, by making reference to the head switching pulse a. As discussed in connection with the prior art, when the reproduced signal of the VTR is to be recorded as a video signal together with the digital information signal, the period of the vertical synchronization signal of the video signal includes a deviation of up to 0.5% in the worst condition. Thus, the head switching pulse a generated from the vertical synchronization signal of the video signal also includes a period error of 0.5%. Assuming that absorption ability to the period error of the head switching pulse is higher than 0.5%, for example 1%, than α and β should be selected such that ##EQU4## The data frames having 800+α samples and 800-β samples are called frame A and frame B, respectively. The 1-bit first discrimination signal b which represents the number of samples is &#34;1&#34; for the frame A and &#34;0&#34; for the frame B. The encoder 3 processes in the same manner as that of the prior art apparatus. The formatting control circuit 4 adds a header word including synchronization signal, block address, 1-bit rate discrimination bit, ID code and parity check code to each of the m data block in each data frame. The rate discrimination bit is &#34;1&#34; for the frame A, and &#34;0&#34; for the frame B. The parity check code represents the result of a predetermined logical operation for the block address and the ID code. The data output of the formatting controller 4 is supplied to the rotating head 7 through the modulator 5, the recording amplifier 6 and the switch 15 and recorded on a magnetic tape. 
     FIG. 11 shows a recording conceptual view of one data frame recorded on the magnetic tape. One data frame comprises m=135 data blocks. Assuming that one sample of the digital information signal comprises 16 bits, six samples can be recorded in one data block in two channels. For the frame A, 6 samples ×135=810 samples are recorded. For the frame B, dummy data is written in the three blocks having block addresses 0, 1 and 2, and 6 samples ×(135-3)=792 samples are recorded. 
     In the reproduction mode, the signal reproduced by the rotating head 7 is supplied to the reverse formatting controller 10 through the switch 15, the reproducing amplifier 8 and the demodulator 9. The reverse formatting controller 10 detects the header word and the rate discrimination bit in the header word to produce the second rate discrimination signal c. It also detects the block address, the ID code and the parity check word in the header word. If the result of the predetermined logical operation for the block address and the ID code does not match to the parity check word, it produces a &#34;0&#34; signal, and if it matches, it produces a &#34;1&#34; signal, as the parity check error detection signal e. The discriminator 13 determines majority of the m second rate discrimination signals c and parity check error detection signals e for each data frame to produce the third rate discrimination signal d. The data output from the reverse formatting controller 10 and the decoder 11 is processed in the time axis reverse converter 12 by the third rate discrimination signal d in the reverse manner to that of the time axis converter 2. 
     The operation of the discriminator 13 is explained below. FIG. 2 shows a configuration of the discriminator 13. In FIG. 2, the number ml of &#34;1&#34; second rate discrimination signals of m second rate discrimination signals c in each data frame is counted by the first counter 132, and the number m 0  of &#34;0&#34; signals is counted by the second counter 133. When the parity check error detection signal e is &#34;1&#34;, the second rate discrimination signal is not counted. The first comparator 134 compares m 1  and m 0 , and if m 1  &gt;m 0 , it produces an &#34;1&#34; output, and if m 1  ≦m 0 , it produces a &#34;0&#34; output. The third counter 136 counts the number of &#34;1&#34; bits in the m parity check error detection signals in each data frame. The second comparator 137 produces a &#34;0&#34; output if the count of the third counter 136 is larger than a predetermined value x. The outputs of the first comparator 134 and the second comparator 137 are logically operated by the AND gate 138 which produces the third rate discrimination signal d at the output terminal 139. 
     In accordance with the present embodiment, the numbers of &#34;0&#34; bits and &#34;1&#34; bits in the m second rate discrimination signals in each data frame are counted and the majority logic is conducted. Accordingly, a highly reliable third rate discrimination signal can be produced. If the number of times of the parity check errors in one data frame exceeds the predetermined number x, it is determined that the result of majority logic is questionable and the &#34;0&#34; third discrimination signal is forcibly produced by the AND gate 138. As a result, even if the rate is misdiscriminated, the introduction of the dummy data into the output digital information signal is prevented, and an audio signal with less noise can be reproduced. 
     While 800+α samples and 800-β samples in one data frame are used and the rate discrimination signal is a one-bit signal in the above embodiment, four numbers of samples may be used and the rate discrimination signal may be a 2-bit signal. 
     FIG. 6 shows a configuration of a second embodiment of the digital signal recording/reproducing apparatus of the present invention. In FIG. 6, numeral 201 denotes an input terminal for digital data, numeral 202 denotes a selector which receives a data pattern to be recorded and a fixed symbol pattern and switches them at a predetermined timing, numeral 203 denotes a serial/parallel converter for converting the output of the selector 202 to 2-bit parallel data, numerals 204 and 205 denote first and second NRZI converters for converting the 2-bit output of the serial/parallel converter 203 to NRZI codes, numerals 207 and 208 denote first and second balanced modulators for modulating the outputs of the first and second NRZI converters 204 and 205 by carriers having a 90° phase difference supplied from a first 90° phase shifter to attain four-phase modulation or offset four-phase modulation, numeral 109 denotes an adder for adding the outputs of the first and second balanced modulators, numeral 210 denotes a recording amplifier for amplifying the output of the adder 209, numeral 211 denotes a switch for selectively supplying the output of the recording amplifier to a pair of magnetic heads 212 on a rotating cylinder through a rotary transformer, numeral 213 denotes a reproducing amplifier for amplifying the signal reproduced by the magnetic head 212 when the signal recorded on the magnetic tape is reproduced, numeral 214 denotes an equalizer for equalizing the output of the reproducing amplifier 213, numeral 215 denotes a band-pass filter which receives the output of the equalizer 214 and passes a predetermined band around the center of the carrier frequency, numerals 216 and 217 denote first and second synchronous detectors which receive the output of the band-pass filter 215 and decode the four-phase modulated signal or the offset four-phase modulated signal, numeral 219 denotes a carrier reproducing circuit, numerals 220 and 221 denote first and second level detectors for detecting two output levels synchronously detected by two reproduced carriers having a 90° phase difference supplied from a second 90° phase shifter, numerals 223 and 224 denote first and second NRZ converters for NRZ-converting the outputs of the first and second level detectors 220 and 221, numeral 225 denotes a parallel/serial converter which receives the outputs of the first and second NRZ converters 223 and 224 and converts them to a serial signal, numeral 226 denotes a digital data output terminal, and numeral 227 denotes a reproduced data output terminal. Da and Db denote the outputs of the first and second NRZI converters 204 and 205, and Da&#39; and Db&#39; denote the outputs of the first and second level detectors 220 and 221. 
     The operation of the above digital signal recording/reproducing apparatus is now explained with reference to FIG. 6. 
     Digital data applied to the digital data input terminal 201 at a predetermined timing is supplied to the selector 202, which selects the input B during the preample period. It selects the digital data during the data period. A fixed symbol pattern (ample pattern) applied to the input B may be a repetitive pattern of 8 bits (11000000). The output of the selector 202 is supplied to the serial/parallel converter 203 which outputs odd-numbered bits to I and even-numbered bit to Q. The outputs I and Q of the serial/parallel converter 203 are applied to the first and second NRZI converters 204 and 205, respectively, for NRZI conversion. The first balanced modulator 207 balance-modulates the carrier phase-shifted by the first 90° phase shifter 206 with the output of the first NRZI modulator 204. The second balanced modulator 208 balance-modulates the carrier f c  with the output of the second NRZI modulator 205. The outputs of the first and second balanced modulators 207 and 208 are mixed by the adder 209 and the mixed signal is recorded on a magnetic tape through the recording amplifier 210, switch 211 and magnetic head 212. 
     In the reproduction mode, the data recorded on the magnetic tape is supplied to the equalizer 214 through the magnetic head 212, switch 211 and reproducing amplifier 213 so that it is equalized in a predetermined manner. The band-pass filter 215 passes only a predetermined band width f c  +f B  around the frequency f c , of the output from the equalizer 214. The first synchronous detector 216 synchronously detects the output of the band-pass filter 215 with the output of the carrier regenerator 219 which oscillates at the same reproducing carrier frequency as the frequency f c  and which has been phase-shifted by the second 90° phase shifter 218. The second synchronous detector 217 synchronously detects with the output of the carrier regenerator 219. The outputs of the first and second synchronous detectors 216 and 217 are supplied to the carrier regenerator 219 as phase error information. The outputs of the first and second synchronous detectors 216 and 217 are also supplied to the first and second level detectors 220 and 221 which reshape the waveforms and produce two different demodulation axis signals Da&#39; and Db&#39;. The signal Db&#39; is supplied to the data clock reproducing circuit 222 which reproduces the data clock by using the reversal edge of the signal Db&#39; as phase information. The signals Da&#39; and Db&#39; are supplied to the first and second NRZ converters 223 and 224 for NRZ conversion, and the outputs thereof are parallel-to-serial converted by the parallel/serial converter 226, the output of which is supplied to the digital data output terminal 226. 
     During the ample period, the fixed symbol pattern (11000000) which has been QPSK or O-QPSK modulated is recorded. Accordingly, the band width after the modulation spreads as shown in FIG. 4c. The band does not spread to a cutoff point of the band-pass filter 115 and a good demodulated signal is produced. In the output Db&#39; of the second level detector 121, there are four possible demodulated signals Db&#39;=±Da or ±Db depending on the lock phase of the reproduced carrier. Since a &#34;1&#34;  bit is present at the odd-numbered bit and the even-numbered bit, respectively, in the fixed symbol pattern (11000000), the signals Da and Db each have one several point for every four bits so that the reversal edge can always be detected. 
     Accordingly, during the preample period, the carrier and data clock can be simultaneously reproduced in a good manner. 
     FIG. 7 shows a configuration of the time axis reverse converter 12 in the first embodiment of the digital signal recording/reproducing apparatus of the present invention. In FIG. 7, numeral 301 denotes a phase comparator, numeral 302 denotes an out-of-phase detector, numeral 303 denotes a low-pass filter, numeral 304 denotes a voltage controlled oscillator, numeral 305 denotes a frequency divider, and numeral 306 denotes a buffer memory. 
     The operation of the above time axis reverse converter is now explained. 
     The phase comparator 301 produces a voltage proportional to a phase difference between the head switching signal and the output of the frequency divider 305. A high frequency component thereof is eliminated by the low-pass filter 303. The voltage controlled oscillator 304 has the oscillation frequency thereof controlled by the output voltage of the low-pass filter 303, and the frequency divider 305 frequency-divides the output of the voltage controlled oscillator 304. The frequency division factor of the frequency divider 305 is determined by the third rate discriminator by the number of data in one data field. When the out-of-phase detector 302 detects out-of-phase, the count of the frequency divider 305 is cleared, and the clear is released at the next phase lock point so that the count of the frequency divider 305 is resumed. 
     The operation of the phase comparator 301, out-of-phase detector 302 and frequency divider 305 is now explained in further detail. The detailed configuration of the phase comparator 301, out-of-phase detector 301 and frequency divider 305 is shown in FIG. 8. Numeral 310 denotes an edge detector, numeral 311 denotes a clock pulse generator, numeral 312 denotes an SR flip-flop, numeral 313 denotes an SR flip-flop, numeral 314 denotes an f-scale counter, numeral 315 denotes an coincidence detector, numeral 316 denotes an coincidence detector, numeral 317 denotes an SR flip-flop, numeral 318 denotes a D flip-flop, numeral 319 denotes a D flip-flop, numeral 320 denotes a frequency divider counter, numeral 321 denotes a coincidence detector, numeral 322 denotes a coincidence detector, numeral 323 denotes a coincidence detector, numeral 324 denotes an inverter, numeral 325 denotes an AND gate, numeral 326 denotes a NAND gate, numerals 327 and 328 denote resistors, and numeral 329 denotes an SR flip-flop. 
     FIG. 9 shows a timing chart for explaining the operation of the phase comparator 301, out-of-phase detector 302 and frequency divider 305. The operation of the phase comparator 301, out-of-phase detector 302 and frequency divider 305 is explained with reference to FIGS. 8 and 9. 
     As the edge detector 310 detects the edge of the head switching signal, it sets the SR flip-flop to enable the counter 314 and resets the SR flip-flop 313 to render the phase reference signal to &#34;L&#34;. When the SR flip-flop 312 is set, the counter 314 starts to count the clock pulse generated by the clock pulse generator 311. When the count of the f-scale counter 314 reaches a preset count i, the coincidence detector 316 detects it to reset has the SR flip-flop 317 and renders the out-of-phase detection window to &#34;L&#34;. When the count of the f-scale counter 314 reaches a preset count h, the coincidence detector 315 detects it and set the SR flip-flop 313 to render the phase reference to &#34;H&#34;. When the f-scale counter 314 counts f and produces a carry CA, it sets the SR flip-flop 317 to render the out-of-phase detection window to &#34;H&#34; and resets the SR flip-flop 312 to stop the count of the f-scale counter. 
     On the other hand, the frequency divider counter 320 counts the clock generated by the voltage controlled oscillator. When the count reaches the preset count j, the coincidence detector 323 detects it and resets the SR flip-flop 329 to render the phase window to &#34;L&#34;. When the count reaches a preset count k, it sets the SR flip-flop 329 to render the phase window to &#34;H&#34;. When the count reaches the frequency division factor (, the coincidence detector 321 detects it and clears the frequency divider counter 320. The frequency division factor l is equal to the number of data in one data frame, which is determined by the third rate discrimination signal d. 
     In this manner, the phase reference and phase window are defined and they are supplied to the circuit comprising the inverter 324, AND gate 325, NAND gate 326 and resistors 327 and 328 to produce the phase comparator output. If the phase of the phase window advances to the rising edge (phase lock point) of the phase reference, the &#34;L&#34; period of the phase comparator output is extended, and if the phase of the phase window retards, the &#34;H&#34; period is extended. 
     The out-of-phase detection window which is the output of the SR flip-flop 317 is latched in the D flip-flop 318 by the frequency divider output. As a result, the rising edge of the frequency divider output goes beyond the &#34;L&#34; section of the out-of-phase window. As the phase of the frequency divider output greatly deviates from the phase lock point, the frequency divider counter 320 is cleared and the clear is released at the next rising edge of the phase reference. As a result, the point at which the frequency divider output rises when the frequency divider counter 320 next counts (approaches to the next phase lock point. 
     Thus, the phase pull-in time at the start of operation can be reduced even with the phase synchronizing loop circuit which has a frequency divider of a large frequency division factor in the feedback loop.