Abstract:
An arbiter that includes a phase comparator receiving two input signals. The outputs of the phase comparator are propagated to a first SR type flip-flop. The outputs of the first SR type flip-flop are propagated to a second SR type flip-flop. The outputs of the second SR type flip-flop indicate which of the two input. signals changed first. The phase comparator can enter a metastable state. The first flip-flop reduces the magnitude of signal swing away from the power supply rails caused by the metastable state. The second flip-flop prevents any signal swing away for a power supply rail is not propagated to an output.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to digital electronic circuits and more particularly to digital integrated circuits that determine which signal arrived first. 
     BACKGROUND OF THE INVENTION 
     Arbiters are used in digital electronics to determine which signal arrived first. This function has many uses in modem electronics. Some of the se uses include resource arbitration where two devices compete for a single resource (such as a memory, or signal bus) by sending a signal to an arbiter. The arbiter determines which device signaled for the resource first, and may then award that device use of that resource. Another example of the usefulness of arbiters is for phase comparison. An arbiter, since it indicates which of two signals arrived first, is useful as a phase comparator. An excellent example of this application is disclosed in a U.S. Pat. No. 6,323,714, titled SYSTEM AND METHOD FOR DESKEWING SYNCHRONOUS CLOCKS IN A VERY LARGE SCALE INTEGRATED CIRCUIT, which is hereby included by reference for all that is disclosed therein. This patent is commonly owned by the assignee of the present document and was filed in the United States Patent and Trademark Office on about the same day as the present application. 
     One problem with arbiters in general is the occurrence of a metastable condition. If both signals arrive together or very close together, the arbiter will generally enter a metastable state. When this occurs, the outputs may move to voltage levels that are not valid logic levels. These voltage levels may be called metastable voltage levels. This condition may last for an arbitrary period of time. Another problem that may arise is that some arbiter circuits may have outputs that can oscillate when the inputs oscillate. In other words, the outputs may not be steady between arbitrations. Both of these conditions, non-valid logic levels and oscillating outputs, can cause problems with the circuitry that receives them. 
     Accordingly, there is a need for a way to realize an arbiter that maintains a steady output state between arbitrations and yet never propagates a metastable voltage level to its outputs. 
     SUMMARY OF THE INVENTION 
     In a preferred embodiment, the invention provides an arbiter that maintains stability between arbitrations without propagating metastable voltage levels. This arbiter is well suited for fabrication in monolithic integrated circuits as well as other circuit technologies. In addition, the preferred embodiment is implemented using a complementary metal oxide semiconductor (CMOS) devices. CMOS devices and processes are commonly used in many VLSI or other integrated circuit designs, so this embodiment may be used in these devices. 
     The arbiter of the present invention includes a phase comparator receiving two input signals. The outputs of the phase comparator are propagated to a first SR type flip-flop. The outputs of the first SR type flip-flop are propagated to a second SR type flip-flop. The outputs of the second SR type flip-flop indicate which of the two input signals changed first. 
     Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of an arbiter according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The arbiter of the present invention includes a phase comparator receiving two input signals. The outputs of the phase comparator are propagated to a first SR type flip-flop. The outputs of the first SR type flip-flop are propagated to a second SR type flip-flop. The outputs of the second SR type flip-flop indicate which of the two input signals changed first. If the two inputs to the phase comparator change at the same time and the same rate it causes the phase comparator to go into a metastable state. During the metastable state, the outputs of the phase comparator leave a good logic voltage level and change together until the metastable condition ends. When the metastable condition ends, one output of the phase comparator goes to one logic state and the other output goes to the other logic state. 
     The outputs of the phase comparator are propagated to a first SR type flip-flop. When the outputs of the phase comparator change together during a metastable state, the outputs of the first SR type flip-flop will either not change at all or will only change by an amount that is less than the amount of change required to cause the second SR type flip-flop to change its outputs. This is because of the feedback inherent in an SR type flip-flop which causes SR type flip-flops to have hysteresis. Thus, the non-good logic levels output by the phase comparator during a metastable state do not propagate to the output of the arbiter of the present invention. 
     FIG. 1 is a schematic diagram of a CMOS arbiter  100  according to the present invention. Input signals IN 1  and IN 2  are input to phase comparator  102 . These signals are normally at a low logic level and the arbiter  100  functions to determine which of these signals transitions to a high logic level first. The outputs of phase comparator  102  are signals C 1  and C 2 . These signals are normally both at a high logic level until at least one of the inputs IN 1  and IN 2  begins to transition. If IN 1  transitions before IN 2 , then output C 1  falls to a low logic level. Likewise, if IN 2  transitions before IN 1 , then output C 2  falls to a low logic level. If both IN 1  and IN 2  transition at the same time, then phase comparator  102  enters a metastable state and both C 1  and C 2  fall together until the metastable condition ends at which time one of the two signals will continue to fall all the way to a low logic level and the other will rise back to a high logic level. 
     Signals C 1  and C 2  are input to the first SR type flip-flop  104 . SR flip-flop  104  is constructed from two cross-coupled NAND gates G 1 A and G 2 A. The outputs of SR flip-flop  104  are signals I 1  and I 2 . These signals are input to SR type flip-flop  106 . SR flip-flop  106  is constructed from two cross-coupled NAND gates G 1 B and G 2 B. The outputs of SR flip-flop  106  are signals O 1  and O 2 . 
     In non-metastable operation, when C 1  falls to a low logic level and C 2  remains at a high logic level, signal I 1  will transition to a high logic level if it was originally low, or remain at a high logic level if it was originally high and signal I 2  will transition to a low logic level if it was originally high, or remain at a low logic level if it was originally low. This ending condition, I 1  at a high logic level and I 2  at a low logic level, ensures that O 2  is low and O 1  is high. This indicates that IN 1  changed before IN 2 . 
     Likewise, when C 2  falls to a low logic level and C 1  remains at a high logic level, signal I 2  will transition to a high logic level if it was originally low, or remain at a high logic level if it was originally high and signal I 1  will transition to a low logic level if it was originally high, or remain at a low logic level if it was originally low. This ending condition, I 2  at a high logic level and I 1  at a low logic level, ensures that O 1  is low and O 2  is high. This indicates that IN 2  changed before IN 1 . 
     When C 1  and C 2  fall together during a metastable condition, the feedback provided by I 1  and I 2  to the other inputs of NAND gates G 1 A and G 2 A prevents SR flip-flop  104  from changing state. When both C 1  and C 2  are reasonably close to a strong low logic level, it may cause the one of I 1  and I 2  that is at the low logic level to begin to swing away from that low logic level. At the same time, this swing away from the low logic level may cause the other one of I 1  and I 2  that is at the high logic level to swing away from that high logic level. However, the amount that these metastable voltages swing away from the logic level they were at is not enough to change the output of SR flip-flop  106 . Accordingly, no intermediate or metastable logic levels propagate to the outputs O 1  and O 2  until the metastable condition resolves. When the metastable condition resolves, O 1  and O 2  may make clean transitions to new logic levels, or stay the same, depending on how the metastable condition resolved. 
     The phase comparator  102  of the preferred embodiment as shown in FIG. 1 is now described. Input IN 1  is connected to the gate of n-channel MOSFET (NFET) MN 1 A. Input IN 1  is also connected to the gates of p-channel MOSFETs (PFETs) MP 2 A and MP 1 B. Input IN 2  is connected to the gate of NFET MN 1 B. Input IN 2  is also connected to the gates of PFETs MP 2 B and MP 1 A. 
     The source of MP 1 A is connected to a positive supply voltage, VDD. The drain of MP 1 A is connected to the source of MP 2 A. The drain of MP 2 A is connected to the drains of MN 1 A and PFET MP 3 A, and the gates of PFET MP 3 B and NFET MN 2 B. This node is also output C 1  of comparator  102 . The source of MN 1 A is connected to the drain of NFET MN 2 A. The source of MN 2 A is connected to a negative supply voltage, GND. The source of MP 3 B is connected to a positive supply voltage, VDD. 
     The source of MP 1 B is connected to a positive supply voltage, VDD. The drain of MP 1 B is connected to the source of MP 2 B. The drain of MP 2 B is connected to the drains of MN 1 B and PFET MP 3 B, and the gates of PFET MP 3 A and NFET MN 2 A. This node is also output C 2  of comparator  102 . The source of MN 1 B is connected to the drain of NFET MN 2 B. The source of MN 2 B is connected to a negative supply voltage, GND. The source of MP 3 A is connected to a positive supply voltage, VDD. 
     From the foregoing it will be apparent that the invention provides a novel and advantageous signal arbiter. This arbiter maintains stability between arbitrations without propagating metastable voltage levels. This arbiter is well suited for fabrication in monolithic integrated circuits as well as other circuit technologies. The preferred embodiment is implemented using a complementary metal oxide semiconductor (CMOS) devices. However, since the basic building blocks used in the present invention comprise a phase comparator and flip-flops that exist in one form or another in almost all process and circuit technologies, it may also be implemented in other circuit technologies such a NMOS or bipolar integrated circuits. 
     Although a specific embodiment of the invention has bee described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The invention is limited on by the claims.