Abstract:
A method of forming a semiconductor device includes separating a semiconductor gate body from the outer surface of the substrate by a gate insulator layer, forming a conductive drain region in the outer surface of the substrate and spaced apart from the gate conductor body, and forming a conductive source region in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The method also includes depositing a metal buffer layer over the conductive source region and conductive drain region, depositing a metal layer over the metal buffer layer, and reacting the metal layer and metal buffer layer with the conductive source region and conductive drain region to form respective first and second silicide regions.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    Semiconductor device fabrication often utilizes a salicide process. A salicide process is a self-aligned silicidation process. In a silicidation process, a metal, such as titanium, is placed into contact with silicon and heated. Heating of the titanium and silicon causes the silicon and titanium to combine to form a silicide compound. Silicidation is conventionally used to provide a conductive contact between silicon in a semiconductor device and a metal contact, which may be connected to a conductive lead. The resulting silicon-silicide-metal combination provides less contact resistance than provided with a direct metal-to-silicon contact. Large contact resistance is generally detrimental to the performance of a semiconductor device. A silicidation process is self-aligned, or a salicide process, when masking is not required to deposit the metal used to form the silicide compound.  
           [0002]    A problem with the use of titanium in a silicide compound is that titanium silicide suffers from size effects. As the volume of a titanium silicide region in a semiconductor device decreases, its contact resistance increases. Thus, as semiconductor devices shrink, particularly the length of a gate in a semiconductor device, the use of titanium silicide may become unacceptable due to resulting high contact resistances. Because of the susceptibility to size effects of titanium silicide, cobalt and nickel are sometimes used as alternatives. In contrast to titanium silicide, cobalt silicide and nickel silicide do not suffer size effects and have a relatively constant resistance for varying volumes of the resulting silicide compound.  
           [0003]    Although the use of cobalt or nickel in a silicidation process offers benefits over the use of titanium, their use is not without disadvantages. For example, the use of cobalt or nickel can result in current leakage into the silicon substrate. Such current leakage can be detrimental. In addition, the use of cobalt or nickel, although providing relatively constant contact: resistance for varying volumes of silicide, has resulted in greater than expected contact resistances.  
         SUMMARY OF THE INVENTION  
         [0004]    Accordingly, a need has arisen for a semiconductor device having reduced contact resistance and low leakage and method of construction for such a device. The present invention recognizes that current leakage arising from the use of cobalt or nickel in a silicidation process may be attributed to spiking of either cobalt or nickel into the silicon substrate. The present invention also recognizes that such spiking may be attributed to a rough interface between the cobalt silicide or the nickel silicide and the silicon substrate in a silicide process. The present invention additionally recognizes that the higher than expected contact resistances resulting from the use of either cobalt or nickel in the silicide process may be attributed to native oxide residing on the surface of the formed silicide. Such native oxide results in degradation of the contact formed in the silicide process. Such degradation results in higher than expected contact resistance.  
           [0005]    The present invention provides a semiconductor device and method of construction that addresses shortcomings of prior devices and methods. According to one aspect of the invention, a method for constructing a semiconductor device includes separating a semiconductor gate body from the outer surface of the substrate by a gate insulator layer, forming a conductive drain region in the outer surface of the substrate and spaced apart from the gate conductor body, and forming a conductive source region in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The method also includes depositing a metal buffer layer over the conductive source region and conductive drain region, depositing a metal layer over the metal buffer layer, and reacting the metal layer and metal buffer layer with the conductive source region and conductive drain region to form respective first and second silicide regions.  
           [0006]    According to another aspect of the invention, a semiconductor device includes a semiconductor gate body separated from the outer surface of the substrate by a gate insulator layer, a conductive drain region formed in the outer surface of the substrate and spaced apart from the gate conductor body, and a conductive source region formed in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The semiconductor device also includes a first silicide region overlying the conductive drain region, a second silicide region overlying the conductive source region. The first and second silicide regions comprise a silicide selected from the group consisting of CoZr y Si x , CoHf y Si x , NiZr y Si x , and NiHf y Si x , where “y” is less than one.  
           [0007]    The invention provides several technical advantages. For example, one embodiment of the invention provides a method for constructing a semiconductor device that results in a device having reduced contact resistance and low leakage but that incorporates advantages associated with the use of cobalt or nickel to form silicide regions overlying portions of the semiconductor device. Such advantages include a relatively constant contact resistance for varying gate lengths, which is particularly important as device sizes shrink.  
           [0008]    Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in connection with the accompanying drawings in which:  
         [0010]    [0010]FIG. 1 a  through if are simplified cross-sectional views of a semiconductor structure in various states of fabrication according to one embodiment of the invention;  
         [0011]    [0011]FIGS. 2 a  through  2   d  are simplified cross-sectional views of portions of FIGS. 1 a  through  1   f , illustrating formation of a silicide region according to the teachings of the invention; and  
         [0012]    [0012]FIG. 2 e  is a simplified cross-sectional view of a portion of a semiconductor device showing formation of a silicide region according to conventional techniques.  
     
    
     DETAILED DESCRIPTION OF INVENTION  
       [0013]    Embodiments of the present invention and its advantages are best understood by referring to FIGS. 1 a  through  2   e  of the drawings, like numerals being used for like and corresponding parts of the various drawings.  
         [0014]    [0014]FIG. 1 a  illustrates a semiconductor device  10  during an initial state of construction after formation of a source region  14  and a drain region  16  in a substrate  12  and after formation of a gate body  18  overlying an oxide layer  20 . Also illustrated in FIG. 1 a  are thick field oxide regions  22  utilized to isolate the resulting transistor from adjacent semiconductor devices. Source region  14 , drain region  16 , gate body  18 , oxide layer  20 , and field oxide regions  22  may be formed according to conventional techniques.  
         [0015]    One example of a conventional technique for forming the semiconductor device  10  illustrated in FIG. 1 a  is described below. In this example, substrate  12  is a P-type silicon substrate; however, substrate  12  could be an N-type substrate. Thick field oxide regions  22  are formed by local oxidation of silicon using a process such as that shown in Havemann, et al. U.S. Pat. No. 4,541,167, issued Sep. 17, 1985 and assigned to the assignee of this application. Substrate  12  is then subjected to a thermal oxidation in a steam environment for approximately 7 minutes at a temperature of approximately 850° C. to form oxide layer  20  as shown in FIG. 1 a . Oxide layer  20  may be grown to a thickness of approximately 3 to 10 nanometers, however, other thicknesses for oxide layer  20  may be used. A polysilicon layer is then deposited, patterned and etched using conventional photolithographic techniques to form polysilicon gate body  18 . An example thickness of polysilicon gate body is approximately 400 nanometers. Appropriate ions  19  are then implanted, self-aligned to form source region  14  and drain region  16 . For a P-type substrate, appropriate ions include phosphorous ions and arsenic ions. An example implantation includes implantation of arsenic ions at a density of approximately  
         [0016]    [0016] 3 × 10   5  ions per square centimeter and an energy of approximately 150 kiloelectron volts. A second ion implantation of phosphorous ions having a density of approximately 4×10 14  ions per square centimeter and an energy level of approximately 85 kiloelectron volts may also be incorporated.  
         [0017]    A channel region is defined within substrate  12  between source region  14  and drain region  16 . Although particular details of one example of the formation of source region  12 , drain region  14 , gate body  18 , oxide layer  20 , and field oxide regions  22  have been provided, other methods and techniques may be utilized without departing from the scope of the present invention.  
         [0018]    [0018]FIG. 1 b  illustrates semiconductor device  10  after formation of a gate oxide layer  24  and sidewall spacers  26   25  and  28 . Gate oxide layer  24  is formed by patterning and etching oxide layer  20  using conventional photolithographic techniques. Sidewall spacers  26  and  28  provide separation between a silicide that will be formed over source and drain regions  14 ,  16  and gate body  18 , which is conductive. Sidewall spacers  26  and  28  may be formed, for example, by depositing a conformal layer of TEOS oxide over semiconductor device  10  and anisotropically etching the TEOS oxide layer, leaving sidewall spacers  26  and  28 . Sidewall spacers  26  and  28  may alternatively be formed prior to implantation of ions  19  to form source region  14  and drain region  16 .  
         [0019]    [0019]FIG. 1 c  illustrates the deposition of a thin buffer layer  30  of metal. Thin buffer layer  30  will act as a buffer layer between silicon in source region  12 , drain region  14 , and gate body  18  and a metal layer during formation of silicide regions in semiconductor device  10 . As described in greater detail below, zirconium and hafnium are both particularly suitable metals for thin buffer layer  30 ; however, other suitable metals may be used without departing from the teachings of the present invention. Thin buffer layer  30  is deposited outwardly from semiconductor device  10  to a thickness of approximately 1 to 5 nanometers. Thin buffer layer  30  resists spiking during the formation of a silicide and also contributes to low contact resistance between a resulting silicide and a metal contact. Although particular thicknesses for thin buffer layer  30  have been described, other thicknesses for thin buffer layer  30  may be utilized. However, thin buffer layer  30  should be sufficiently thin to prevent the formation of a second silicide layer in addition to a silicide layer formed primarily from a metal layer  32 .  
         [0020]    Metal layer  32  is illustrated disposed outwardly over thin buffer layer  30 . Metal layer  32  is provided for reaction with silicon in source region  14 , drain region  16 , and gate body  18  to produce silicide regions for establishing an electrical connection with metal contacts. Such silicide regions provide lower contact resistance between a metal contact and the silicon in source region  14 , drain region  16 , or gate body  18  than would occur with a direct contact between a metal contact and the silicon in source region  14 , drain region  16 , or gate body  18 . Metal layer  32  may be formed from any suitable metal that is a different metal from that used for thin buffer layer  30 ; however, cobalt and nickel are both particularly advantageous metals for use in metal layer  32 . Both cobalt silicide and nickel silicide do not suffer size effects traditionally associated with the use of titanium to form a silicide compound. Therefore, the use of such materials allows for reduced contact resistances, which are particularly important as the size of semiconductor devices decrease. Metal layer  32  is deposited to a thickness in the range of 5 nanometers to 40 nanometers; however, other thicknesses for layer  32  may be used without departing from the scope of the present invention.  
         [0021]    [0021]FIG. 1 d  illustrates semiconductor device  10  after reaction of metal layer  32  with thin buffer layer  30  and the silicon in source region  14 , drain region  16 , and gate body  18 . Due to the reaction of these materials, a silicide region  34  is formed overlying source region  14 , and a silicide region  36  is formed overlying drain region  16 . In addition, a silicide region  38  is formed overlying gate body  18 . Silicide regions  34 ,  36 , and  38  are formed by heating of semiconductor device  10  such that the metal in metal layer  32  may react with the silicon in source region  14 , drain region  16 , and gate body  18 , as well as the metal in thin buffer layer  30  to form a silicide. According to one embodiment, such an anneal occurs at a temperature in the range of 450° C. to 850° C. for a time period of 10 seconds to 100 seconds. In addition to this anneal, a second anneal could be performed with similar temperature and time conditions to cause further reaction of the materials.  
         [0022]    Because different metals are used within metal layer  32  and thin buffer layer  30 , a silicide compound is formed within silicide regions  34 ,  36 , and  38  incorporating each metal. With thin buffer layer  30  being thinner than metal layer  32 , the metal in metal layer  32  will form a majority silicide within silicide regions  34 ,  36 , and  38  and the metal within thin buffer layer  30  will form a minority silicide within silicide regions  34 ,  36 , and  38 . An example of the resulting compound in silicide regions  34 ,  36 , and  38  formed according to the teachings of the present invention is CoZr y Si x , where “x” represents the ratio of silicon atoms to cobalt atoms and “y” is less than one and represents the ratio of zirconium atoms to cobalt atoms. Other examples of compounds comprising silicide regions  34 ,  36 , and  38  include CoHf y si x , NiZr y Si x , and NiHf y Si x , where “x” represents the ratio of silicon atoms to either cobalt or nickel atoms and “y” is less than one and represents the ratio of either the number of hafnium atoms or zirconium atoms to the number of cobalt or nickel atoms.  
         [0023]    [0023]FIG. 1 e  illustrates semiconductor device  10  after additional processing steps associated with removing thin buffer layer  30  and metal layer  32 . After formation of silicide regions  34 ,  36 , and  38 , the unreacted metals in metal layer  32  and thin buffer layer  30  may be selectively removed through the use of an etchant that does not attack the silicide in silicide regions  34 ,  36 , and  38 , silicon substrate  12 , or field oxide regions  22 . An example of such an etchant is a mixture of H 2 O 2  and H 2 SO 4 .  
         [0024]    [0024]FIG. 1 f  illustrates semiconductor device  10  after formation of metal contacts  62  and  64 . After etching of metal layer  32  and thin buffer layer  30 , a dielectric layer  60  is deposited. Contact holes are then opened to expose portions of silicide regions  34  and  36  overlying source region  14  and drain region  16 , respectively. An example method for exposing portions of silicide regions  34  and  36  is photolithographic masking and etching. After exposing portions of silicide regions  34  and  36 , metal is deposited into the contact holes to form metal contacts  62  and  64 . Metal contacts  62  and  64  therefore provide a conductive path to source region  14  and drain region  16 . A metal contact may also be formed for connection to silicide region  38 .  
         [0025]    The use of a thin buffer layer  30  provides several benefits. First, if zirconium or hafnium is used, because zirconium oxide and hafnium oxide both have high heats of formation, zirconium and hafnium are good oxide reduction materials. For example, zirconium oxide has a. heat of formation of approximately −360 kJ/mole and hafnium oxide has a heat of formation of approximately −380 kJ/mole. By comparison, silicon dioxide has a heat of formation of approximately −300 kJ/mole. Because zirconium and hafnium are good oxide reduction materials, native oxide formed on the surface of the resulting silicide in silicide regions  34 ,  36 , and  38  is reduced. Reduction of native oxide on the surface silicide regions  34 ,  36 , and  38  eliminates the problem of higher than expected contact resistance due to native oxide formation.  
         [0026]    Furthermore, as described in greater detail in conjunction with FIGS. 2 a  through  2   d , the use of thin buffer layer  30  provides a smooth interface of the resulting silicide with the underlying silicon, such as the silicon in drain region  14 , source region  16 , and gate region  18 . Because these interfaces are smooth, the likelihood of spiking is reduced, and therefore current leakage is reduced. Providing of a smooth interface of silicide regions  34 ,  36 , and  38  with the underlying silicon is described in greater detail in conjunction with FIGS. 2 a  though  2   e.    
         [0027]    [0027]FIG. 2 a  illustrates an enlarged view of gate body  18 , which is formed from silicon. Overlying gate body  18  is thin buffer layer  30 . For simplicity of description, thin buffer layer  30  is assumed to comprise hafnium in FIGS. 2 a  through  2   d . Overlying thin buffer layer  30  is metal layer  32 . Also for simplicity of description, metal layer  32  is assumed to comprise cobalt in FIGS. 2 a  through  2   d . Silicon in gate body  18  reacts with cobalt in metal layer  32  and hafnium in thin buffer layer  30  to produce silicide region  38 . Thin layer  30  of hafnium provides beneficial properties for the resulting silicide region  38 , as described below. The below description is also applicable to formation of silicide regions  34  and  36  overlying source region  14  and drain region  16 .  
         [0028]    [0028]FIG. 2 b , illustrates the diffusion of silicon atoms, represented by arrows  40 , into metal layer  32  and the diffusion of the cobalt atoms, represented by arrows  42 , into gate body  18 . Conventionally, a silicidation process forms a rough silicide layer such as silicide layer  152  illustrated in FIG. 2 e . However, thin layer  30  provides a diffusion buffer between the silicon in gate body  18  and the cobalt in metal layer  32  to prevent the formation of a rough silicide layer. The prevention of such a rough silicide layer resists spiking, which could otherwise result in current leakage.  
         [0029]    Silicon atoms  40  diffuse toward metal layer  32  and cobalt atoms  42  diffuse toward gate body  18  in response to an annealing step. An example anneal is a rapid thermal anneal having a temperature range of 450° C. to 850° C. and a duration of 10 seconds to 100 seconds. As silicon atoms  40  and cobalt atoms  42  begin to diffuse, thin buffer layer  30  transforms into an amorphous layer  44  of, in this example, hafnium, cobalt, and silicon.  
         [0030]    [0030]FIG. 2 c  illustrates the formation of a smooth silicide layer  46  of cobalt silicide during the above-described annealing step. Because the rate of diffusion along a grain boundary within a polycrystalline material, such as the silicon in gate body  18  is different than diffusion within a single grain of material within a polycrystalline material, diffusion through a polycrystalline material tends to form a rough interface, such as interface  154  illustrated in FIG. 2 e . In contrast, an amorphous material has no grain boundary, therefore the rate of diffusion within an amorphous material, such as layer  44 , is more uniform. Thus, forming amorphous layer  44  before the formation of layers  46  and  52  which have a polycrystalline structure, makes a resulting interface  54  smooth. As annealing continues, additional silicon atoms  40  and cobalt atoms  42  diffuse into amorphous layer  44  to form a silicide. As annealing continues, hafnium silicide becomes a minority silicide and cobalt silicide becomes a majority silicide within a uniform and smooth polycrystalline silicide layer  52  formed between the silicon gate body  18  and metal layer  32 . The resulting structure is illustrated in FIG. 2 d.    
         [0031]    The resulting structure in FIG. 2 d  provides an interface  54  between gate body  18  and silicide layer  52  that is smooth enough to eliminate leakage due to spiking of silicide into gate body  18 . Therefore, the use of thin buffer layer  30  in combination with metal layer  32  results in a structure that does not suffer leakage problems due to a rough interface between the silicide and the silicon. Such rough interfaces are conventionally found in silicide processes utilizing cobalt or nickel.  
         [0032]    [0032]FIG. 2 e  depicts a rough interface  154  that may be formed in a silicide process not incorporating a thin buffer layer, such as thin buffer layer  30 . As illustrated, a rough silicide layer  152  is disposed between a metal layer  132  and a gate body, such as gate body  18 . Rough interface  154  is formed between gate body  18  and silicide layer  152 , which could lead to spiking and leakage. Such spiking is avoided in the above-described process incorporating the teachings of the present invention.  
         [0033]    Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.