Abstract:
Timing information is transmitted over a network by sending time-stamped packets between a transmitter and receiver. The time-stamped packets are used to compute an estimate of the frequency deviation between the transmitter clock and the receiver clock. The local receiver clock is periodically updated to match the transmitter clock based on the estimate, which is preferably a least squares estimate. A multiple window approach is employed to increase update speed.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates to the transfer of timing information over packet networks, and more particularly to a method wherein timestamps are sent from the transmitter to the receiver to enable synchronization of the receiver. 
       BACKGROUND OF THE INVENTION 
       [0002]    In order to send time sensitive information, such as voice and video data, over asynchronous networks, some means must be employed or transferring timing information between the transmitting and receiving end. Timing-over-Packet (ToP) technology enables accurate timing and synchronization to be distributed across asynchronous packet infrastructures, allowing carriers to confidently support time-critical services over packet networks. 
         [0003]    A network including ToP technology is shown in  FIG. 1 . The transmitter side includes a digital controlled oscillator (DCO) referenced to a local oscillator at the transmitter. The center frequency (CF) of the DCO at the transmitter side is set by a digital word. The output of the DCO depends on the set center frequency and the frequency of the local oscillator at the transmitter side. A time stamp n tx , which is the phase of master DCO clock, is transmitted to the receiver, which also contains a DCO referenced to a local oscillator at the receiver and set at the same center frequency CF as the transmitter. However, if the frequency of the local oscillator at the receiver is different from the frequency of the local oscillator at the transmitter, the output of the DCO at the receiver will be different from the output of the DCO at the transmitter. The objective is to make the output frequency of the DCO at the receiver the same as the output frequency of the DCO at the receiver. This is achieved by adjusting the center frequency of the receiver DCO to take into account the difference in local oscillator frequencies. 
         [0004]    At receiver side, the processor compares the transmitter time stamp with a local generated time stamp from the receiver DCO. The difference in time stamp, which is called transit time, is used to adjust receiver center frequency of the receiver DCO so that it will be synchronized with the master DCO. 
         [0005]    To minimize the impact on data transmission, the transmission rate for timing packets, i.e. packets with time stamp information, has to be limited so that it is much smaller than the network data rate. In order to provide an accurate update of the receiver DCO, a large amount of data needs to be collected, and at a low transmission rate, this can take considerable time. 
       SUMMARY OF THE INVENTION 
       [0006]    The invention computes an estimate of the frequency deviation by an accurate method, such as the least squares method or the recursive least square method. 
         [0007]    Thus, in accordance with one aspect of the invention there is provided a method of transferring timing information over a network between a transmitter and receiver, comprising generating a clock signals with a first digital controlled oscillator having a set center frequency at the transmitter based on a local oscillator at the transmitter; generating clock signals at the receiver with a digital controlled oscillator having a set center frequency based on a local oscillator at the receiver; sending time-stamped packets derived from the local transmitter clock to the receiver; creating time-stamped packets at the receiver containing timing information derived from the local receiver clock; processing said time-stamped packets to compute an estimate of the frequency deviation between the transmitter clock and the receiver clock; adjusting the center frequency of the digital controlled oscillator at the receiver so that it is synchronized with the digital controlled oscillator at the receiver, and wherein an overlapping multi-window approach is adopted wherein data adjustment blocks compute frequency adjustments from timing data accumulating during overlapping time intervals, and the data adjustment blocks take turns to output frequency adjustment data for the digital controlled oscillator at the receiver every TIM time intervals, where T is the time required to collect enough data to make an adjustment with a single adjustment block, and M is the number of adjustment blocks. 
         [0008]    The novel method in accordance with the invention allows the local clock to track the reference clock through unknown network with minimum error. The Least Square method is an effective solution for a general unknown network delay distribution as it is very robust and accurate 
         [0009]    Embodiments of the invention use a multi-window least squares approach to solve the problem. Multiple over-lapped windows are used for information collection. The DCO is updated when one of data collection windows reaches its full capacity. The other data windows are compensated when DCO is updated. 
         [0010]    In accordance with another aspect of the invention there is provided an apparatus for updating the set frequency of a digital controlled oscillator at a receiver for timing recovery in an asynchronous packet network, comprising: a plurality of data accumulation blocks for accumulating timing data from time-stamped packets transmitted through a packet network from a transmitter; a plurality of adjustment blocks for computing an estimate of the frequency deviation from said accumulated timing data; and an updater for periodically updating said set frequency based on said computed estimate to synchronize said digital controlled oscillator at the receiver with a digital controlled oscillator at the transmitter; and wherein the data adjustment blocks are configured to compute frequency adjustments from timing data accumulating during overlapping time intervals, and the data adjustment blocks are configured to take turns to output frequency adjustment data for the digital controlled oscillator at the receiver every TIM time intervals, where T is the time required to collect enough data to make an adjustment with a single adjustment block, and M is the number of adjustment blocks. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which: 
           [0012]      FIG. 1  is a block diagram of a timing-over-pact synchronization system; 
           [0013]      FIG. 2  is block diagram of a ToP processor implementing a Least Squares solution; 
           [0014]      FIG. 3  is block diagram of a ToP processor implementing an over-lapped Least Squares solution; 
           [0015]      FIG. 4  is a graph helpful in understanding the data adjustment after a DCO update; and 
           [0016]      FIG. 5  is block diagram of a ToP processor implementing a multi-stage over-lapped Least Squares solution. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0017]    The general expression for the time stamps can be expressed as: 
         [0000]        n   tx   =k·T·f   tx , 
         [0000]        n   rx =( k·T+Δ   k )· f   rx +Φ 
         [0000]    where n tx  and n rx  are time stamps of packet at transmitter and receiver side respectively, with f tx  and f rx  as the respective DCO frequencies. T is the time interval between two consecutive timing packets and k is the index. If Δ k  is the network delay and Φ is the initial phase offset between the transmitter DCO and the receiver DCO, the transit time is the difference between n tx  and n rx . 
         [0018]    This transit time can be expressed as: 
         [0000]        n   tx   n   rx   =k·T· ( f   tx   −f   rx )+Δ k   ·f   rx +Φ 
         [0000]    where y k =n tx −n rx  is the transit time, 
         [0000]    
       
         
           
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         [0000]    is the frequency deviation of interest, (10 6 ·α is the deviation of the local clock in ppm), x k =k·T·f tx  is the transmitter timestamp, and v k =Δ k ·f rx +Φ is the noise containing the network delay as the noise source. Since f tx  remains relatively constant with only a small change during a DCO update, v k  mostly represents the network delay variation with a phase offset. The estimate can now be reduced to 
         [0000]        y   k   =α·x   k +v k    
         [0019]    In order to adjust the DCO frequency, it is important to estimate α, in which case the required DCO frequency adjustment is α·f tx ) which is given by the expression 
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         [0020]    Assuming N items of data are collected, the solution is 
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         [0021]    A processor for implementing this solution is shown in  FIG. 2 . The DCO at the transmitter side is nominally set at the same center frequency CF as the DCO at the receiver side. Due to the difference in local oscillator frequencies at the transmitter and receiver, the output frequencies of the DCOs will be slightly different. In accordance with embodiments of the invention, the nominal center frequency CF at the receiver is adjusted prior to input to the DCO at the receiver so that the receiver DCO output frequency is the same as the transmitter DCO output frequency. 
         [0022]    In  FIG. 2 , data accumulation block  10  receives inputs n tx  and n rx  and outputs N, S x , S 2x , S xy  and S y  to DCO adjustment block  12 , where S x =Σ(x k ), S xy =Σ(x k y k ), S 2x =Σ(x k   2 ) and S y =Σ(y k ). Input n rx  is subtracted from input n tx  by subtractor  14  to derive the difference n tx −n rx , which is the transit time for the time stamped packets. The data accumulation block also includes counter  16  for counting the number of data items N, delay units  18 , and reset input  20 , as well as adders  22  and multipliers  24 . The DCO adjustment block outputs the result a to multiplier  26 , where it is multiplied by the set center frequency (CF) in multiplier  26 , passed through adder  28  with delay circuit  30  providing delayed feedback, and fed to the DCO as the adjusted DCO center frequency CF′. 
         [0023]    The data accumulation block  10  collects every timing packet with transmitter timestamp and receiver timestamp, and updates S x , S y , S xy  and S 2x . The number of data collected is stored in the main counter  32 . When the main counter  32  reaches a pre-set time limited (T), DCO adjustment value is calculated with the number of collected data in that time interval (N). In the meantime, the main counter  32  is reset to zero and all memories and the data counter in the data accumulation block  10  are reset to zero. 
         [0024]    When the network traffic is heavy and the network delay has a large variation, more data is required for an accurate clock estimation, which means that the clock update takes a longer time. This is especially true if the timing packet is only transmitted at a low rate. In order to update the DCO more often while maintaining the same window size, an embodiment of the invention employs a novel multi-window approach, which is shown in  FIG. 3 . 
         [0025]    In  FIG. 3 , there are two data accumulation blocks  101 ,  102  and two DCO adjustment blocks  12   1 ,  12   2 . When the main counter  32  reaches the time limit, the two DCO adjustment blocks  10   1 ,  10   2  takes turns to make DCO adjustments based on the output of 1 bit counter  34 , which alternates between selecting DCO adjustment block  12   1  and DCO adjustment block  12   2  through selection unit  36 . The data accumulation blocks  10   1 ,  10   2  are reset alternately. 
         [0026]    If each DCO update requires time interval T to make an accurate DCO adjustment with enough timing packets being collected, the DCO adjustment can be done with double speed, i.e., adjusted every T/2 time interval. When DCO adjustment block  12   1  is in the process of adjusting DCO with information collected by data accumulation block  10   1  in the past time interval T, data accumulation block  10   2  only accumulates information from its first T1=T/2 of time interval, and vice verse. 
         [0027]    When DCO adjustment block  12   1  calculates the DCO adjustment, data accumulation block  10   1  will be reset, but data accumulation block  10   2  is half way through data collection, which means that it has different frequency deviation before and after that time. Thus, adjustment has to be made for variables in the data accumulation blocks. Let the transit time and transmitter time stamp relationship be 
         [0000]    
       
      
       y 
       k 
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         [0000]    before adjustment and 
         [0000]        y   k =α 1   ·x   k   +v   k +b 
         [0000]    after adjustment as shown in  FIG. 4 . 
         [0028]    In order to match the previous collected data to the later data, some adjustments have to be made to S y  and S xy . (S x  and S 2x  will be unaffected). For a known DCO adjustment α 1 −α, the adjustments for S y  and S xy  are: 
         [0000]        S   y   =S   y +(α 1 −α)( S   x   −T   1 ) 
         [0000]        S   xy   =S   xy +(α 1 −α)( S   2x   −T   1   ·S   x ) 
         [0000]    where T 1  is the time elapsed during the data collection of S y , S xy , S x  and S 2x  in units of transmitter time stamp. T 1  can also be obtained by taking the difference between the largest time stamp value in S x  and the smallest one. 
         [0029]    Blocks  38   1  and  38   2  update the respective data accumulation blocks accordingly. 
         [0030]    From  FIG. 4 , it will be seen that without compensation, the next frequency estimate will be larger than the accurate value because the phase slope is still positive even the local DCO frequency is already accurate after T 1 . This will cause phase overshooting and the estimated frequency swing around the true values for a long time. Or even worse, in some cases frequency convergence will never be reached. 
         [0031]    A similar scheme to that described with reference to  FIG. 3  can be extended to a multi-windows approach, where M overlapping windows are employed. Such a scheme, which is shown in  FIG. 5 , increases the DCO update speed by M times while maintaining the same estimate window size for data collection. 
         [0032]    In the embodiment shown in  FIG. 5 , there are M data accumulation blocks  10   1 ,  10   2 , . . .  10   M ) M data adjustment blocks  12   1 ,  12   2  . . .  12   M ) M variable adjustment units  38   1  . . .  38   M , and DCO adjustment selection block  40  for selecting an output from one of the DCO adjustment blocks  12   1 ,  12   2  . . .  12   M . 
         [0033]    The embodiment shown in  FIG. 5  works in a similar manner to the embodiment described with reference to  FIG. 3 , except the selection block selects the appropriate data adjustment block  12   1 ,  12   2  . . .  12   M  for output to use for adjustment of the DCO. 
         [0034]    When the main counter  32  reaches time limit T/M, the secondary counter  42 , which has an output m that counts from 1 to M, controls selects DCO adjustment block  12   m  to update the DCO. Its corresponding data accumulation block  10   m  is also updated. At that time, all memories in the data accumulation m are reset and other data accumulation blocks update their S y  and S xy  because of the DCO adjustment (as shown in  FIG. 4 ). In this scheme, the DCO adjustment will be based on a block of timing packets collected in the time interval T. As a result, the DCO will be updated M times faster. 
         [0035]    The described embodiments provide a low cost implementation of timing-over-packet technology, while offering network synchronization with accurate frequency estimates and fast DCO updates. Embodiments of the invention also offer fast and accurate lock without overshooting. The method can be extended to other accurate estimate methods, such as the recursive least square estimate method. 
         [0036]    It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. For example, a processor may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included.