Abstract:
Novel methods and apparatus to enhance thermal performance of IC packages are disclosed. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions. In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.

Description:
FIELD OF INVENTION  
         [0001]    The present invention generally relates to the field of electronic device manufacturing. More specifically, the present invention relates to techniques for enhancing thermal performance of integrated circuit (IC) packages.  
         BACKGROUND OF INVENTION  
         [0002]    As integrated circuit fabrication technology improves, manufacturers are able to integrate additional functionality onto a single silicon substrate. As the number of these functionalities increases, however, so does the number of components on a single chip. Additional components add additional signal switching, in turn, creating more heat. Also, the complexity of these devices poses a further thermal problem where different regions on a same die may have operationally significant differences in temperature.  
           [0003]    Thermal expansion differences have been a fundamental problem facing the semiconductor industry. The different temperature regions on the same die intensify the thermal expansion problems. During normal operation, a semiconductor device is expected to survive a fairly wide range of temperature fluctuations. While undergoing these fluctuations, if a portion of the device expands and contracts at one rate while another portion of the same device moves at vastly different rates, a great deal of stress can be generated within the combined structure. These stresses can produce failures within the components themselves or at any of the interfaces between these components.  
           [0004]    Accordingly, performance and reliability of an IC package depends, among other things, on temperature uniformity across the circuits on a die. Temperature differences between portions of the die circuit may lead to timing problems and clock speed reductions (thereby slowing the speed of a chip). This in turn can degrade performance of the chip. In some cases, such problems may lead to soft errors where a chip may provide a wrong result without totally failing or producing any error messages.  
           [0005]    An additional problem stems from the fact that different regions of a same die may change their thermal behavior over time. In other words, a region that may be hot at a first point in time may be considered cold at a later point, whereas an adjacent region that may have been cold at the first point in time may be hot at the later point.  
           [0006]    A current approach in electronic cooling is to provide the best thermal path for the heat being generated within the circuitry of the IC package. As a result, areas of the die that either produce less power, or are inactive at a given time, stay significantly cooler than the areas with the maximum power generation. This causes an elevated temperature difference across the die, thereby exasperating the thermal non-uniformity issues. Removing additional heat from the “hot” spots is impractical because the heat path used is often near its best price/performance considerations already.  
         SUMMARY OF INVENTION  
         [0007]    The present invention includes novel methods and apparatus to enhance thermal performance of IC packages. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions.  
           [0008]    In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.  
           [0009]    In a yet a different embodiment, the thermal conductivity of the thermal enhancement material increases as the temperature effecting the thermal enhancement material increases.  
           [0010]    In a further embodiment, the thermal conductivity of the thermal enhancement material decreases as the temperature effecting the thermal enhancement material decreases.  
           [0011]    In a different embodiment, an apparatus for enhancing thermal uniformity across a semiconductor device is disclosed. The apparatus includes the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. A thermal enhancement material is located substantially adjacent to the first and second thermal regions.  
           [0012]    In an additional embodiment, the semiconductor device is a device selected from a group comprising a die, an IC, a processor, and an ASIC.  
           [0013]    In yet a further embodiment, the thermal enhancement material is in close proximity to at least one of the first and second thermal regions.  
           [0014]    In yet a different embodiment, the thermal enhancement material is located within a thermal path of the semiconductor device.  
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0015]    The present invention may be better understood and its numerous objects, features, and advantages made apparent to those skilled in the art by reference to the accompanying drawings in which:  
         [0016]    [0016]FIG. 1A illustrates an exemplary partial cross-sectional view of a device  100  in accordance with an embodiment of the present invention;  
         [0017]    [0017]FIG. 1B illustrates an exemplary partial cross-sectional view of a device  150  in accordance with an embodiment of the present invention;  
         [0018]    [0018]FIG. 2 illustrates an exemplary top view of a device  200  in accordance with an embodiment of the present invention;  
         [0019]    [0019]FIG. 3 illustrates an exemplary partial cross-sectional view of a device  300  in accordance with an embodiment of the present invention; and  
         [0020]    [0020]FIG. 4 illustrates an exemplary partial cross-sectional view of a device  400  in accordance with an embodiment of the present invention. 
     
    
       [0021]    The use of the same reference symbols in different drawings indicates similar or identical items.  
       DETAILED DESCRIPTION  
       [0022]    In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.  
         [0023]    Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.  
         [0024]    [0024]FIG. 1A illustrates an exemplary partial cross-sectional view of a device  100  in accordance with an embodiment of the present invention. A substrate  102  is attached to a die  104 . A lid  106  is attached to the die  104  via a lid attach  108  (where TIM 1  stands for thermal interface material  1 ). The lid  106  is attached to a heat sink  110  via a heat sink attach  112  (where TIM 2  stands for thermal interface material  2 ). The heat sink  110  is envisioned to be constructed using material including copper and/or aluminum with or without vapor chambers or heat pipes, for example, inside of the base, and the like. The heat sink  110  may dissipate heat generated by circuitry present on, for example, the die  104 . The heat sink  110  is attached to a bolster plate  114  via connector(s)  116 . The bolster plate  114  is envisioned to provide structural support for the device  100 . The bolster plate  114  may be attached to a socket  118  via a printed circuit board (PCB)  120 . The socket  118  may be attached to the PCB  120  via solder balls (not shown). In an embodiment, it is envisioned that socket  118  may hold a package (e.g., including the substrate, die, lid attach, and/or lid). The device  100  may be utilized as a lidded design for any semiconductor device including an integrated circuit, a processor, an application specific integrated chip (ASIC) and the like.  
         [0025]    [0025]FIG. 1B illustrates an exemplary partial cross-sectional view of a device  150  in accordance with an embodiment of the present invention. A substrate  102  is attached to a die  104 . A heat sink  110  is attached to the die  104  via a heat sink attach  112  (where TIM 0  stands for thermal interface material  0 ). The heat sink  110  may dissipate heat generated by circuitry present on, for example, the die  104 . The heat sink  110  is attached to a bolster plate  114  via connector(s)  116 . The bolster plate  114  is envisioned to provide structural support for the device  150 . The bolster plate  114  may be attached to a socket  118  via a printed circuit board (PCB)  120 . The socket  118  may be attached to the PCB  120  via solder balls (not shown). In an embodiment, it is envisioned that socket  118  may hold a package (e.g., including the substrate, die, lid attach, and/or lid). The device  150  may be utilized as a lidless design for any semiconductor device including an integrated circuit, a processor, an application specific integrated chip (ASIC) and the like.  
         [0026]    [0026]FIG. 2 illustrates an exemplary top view of a device  200  in accordance with an embodiment of the present invention. The device  200  includes a semiconductor device  108  with regions  202 ,  204 ,  206 , and  208 . Each of the regions ( 202 - 208 ) may have different temperatures at a given time. The region  208  illustrates that in certain embodiments select regions ( 204  and  206  in this case) may overlap. For example, the region  204  may be hotter than a region  206 , but because of their proximity the region  208  may be hotter than the region  206  but cooler than the region  204 .  
         [0027]    In this example, it is envisioned that the region  204  may be where relatively more signal switching is done in the semiconductor device  108  (for example, the floating point unit of a processor performing floating point operations), whereas the region  206  may be a cache area (where less signal switching is performed for the given floating point operations). For this example, in accordance with an embodiment of the present invention, it is envisioned that to provide thermal uniformity across the device  200 , less heat may be removed from the region  206  than the region  204 , resulting in a lower thermal differential between these regions. Similarly, the lower thermal differential can result in the region  208  having a temperature closer to both the regions  204  and  206 .  
         [0028]    [0028]FIG. 3 illustrates an exemplary partial cross-sectional view of a device  300  in accordance with an embodiment of the present invention. The device  300  includes the semiconductor device  108  with a thermal enhancement material  310  disposed thereon. The thermal enhancement material  310  can be any material that changes its thermal conductivity in response to temperature changes. For example, if the temperature of the thermal enhancement material  310  is raised, so will its thermal conductivity (whereas its thermal resistance will be decreased) and vice versa. In one embodiment, the thermal enhancement material  310  is placed as close to the substrate  102  or die  104  (and/or the semiconductor device  108 ) as possible. This close proximity is envisioned to improve the thermal and mechanical coupling between the semiconductor device  108  and the thermal enhancement material  310 .  
         [0029]    In an embodiment, the thermal enhancement material  310  may be thin film deposited on the semiconductor device  108  through melting and resolidification. As illustrated in FIG. 3, the thermal enhancement material  310  may conform to the shape of the semiconductor device  108 . It is envisioned that the thermal enhancement material  310  may be a thin film, paste, grease, Tyco metallized particles interconnect (MPI), and the like. It is envisioned that according to an embodiment of the present invention, the thermal enhancement material  310  may be located within a thermal path of the semiconductor device  108 .  
         [0030]    Also, in certain embodiments, the thermal enhancement material  310  may be implemented as a device. In an embodiment, such a device, instead of a film, may be implemented as a layer of a material placed between the chip and the thermal spreader or a heat sink, that has a relatively low Young&#39;s Modulus (i.e. soft and high thermal conductivity). Then, as temperature is increased in a given zone, so would the thickness of the layer, thus squeezing the device and reducing thermal contact resistances at both interfaces (chip and heat spreader or heat sink); whereas in a cold zone, the expansion is relatively less and, hence, the thermal contact resistance is higher (i.e., less squeezing). In an embodiment, another possibility would be a thin (about 50 to 100 μm) “black box” layer that changes its thermal conductivity internally by a mechanism in accordance with its temperature to meet the thermal conductivity/temperature requirements.  
         [0031]    [0031]FIG. 4 illustrates an exemplary partial cross-sectional view of a device  400  in accordance with an embodiment of the present invention. The device  400  includes the semiconductor device  108  with thermal enhancement materials  410   a - e  disposed thereon. It is envisioned that the thermal enhancement materials  41   0   a - e  may be implemented utilizing different materials.  
         [0032]    In one embodiment, such material may be selected so that higher temperature regions are closer to material with a high thermal conductivity and select cooler regions are more proximate to material with a changing thermal conductivity (as described above with respect to the thermal enhancement material  310 ). Additionally, each of the thermal enhancement materials  410   a - e  may be surrounded with other materials with, for example, a lower coefficient of thermal expansion (CTE) to limit physical movements associate with thermal expansion. Also, even though FIG. 4 illustrates the thermal enhancement materials  410   a - e  laterally adjacent to each other, it is envisioned that the thermal enhancement materials  410   a - e  may be implemented with vertically adjacent materials (with differing thermal behaviors) to enhance thermal performance of the device  400 .  
         [0033]    The foregoing description has been directed to specific embodiments. It will be apparent to those with ordinary skill in the art that modifications may be made to the described embodiments, with the attainment of all or some of the advantages. For example, the techniques discussed herein may be applied to any type of heat sensitive device. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the spirit and scope of the invention.