Abstract:
An advanced video coding and decoding chip and a method with an optimized processing sequence for the sub-blocks, each including 4×4 pixels, of a macroblock in a discrete cosine transform (DCT) and an inverse DCT are disclosed, wherein the compression hardware and the reconstruction hardware execute the compression and the reconstruction of at least part of a field in parallel.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority of China Patent Application No. 201410765102.2, filed on Dec. 11, 2014, the entirety of which is incorporated by reference herein. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an advanced video coding and decoding chip and method, and it particularly relates to H.264 high-resolution video recording, compression, and release. 
         [0004]    2. Description of the Related Art 
         [0005]    H.264, introduced in part 10 of MPEG-4, is an advanced video format and is mature in the use of video compression and codecs, and is gradually being used widely in many applications like those for videoconferencing, video surveillance, consumer electronics, and so on that demand high-resolution and real-time video coding. Therefore, how to optimize H.264 encoder hardware to achieve high-resolution and real-time video transmission is a popular topic. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    Advanced video coding and decoding technology with coding speed optimization is disclosed, which dramatically improves the coding speed of H.264 encoder hardware. 
         [0007]    An advanced video coding and decoding chip in accordance with an exemplary embodiment of the disclosure comprises discrete cosine transform (DCT) hardware and inverse DCT hardware. The DCT hardware performs DCT on residual values of a transformation advanced sub-block before performing DCT on residual values of a transformation overtaken sub-block. The transformation advanced sub-block is one of the sub-blocks, numbered from 0 to 15, of a macroblock and the transformation overtaken sub-block is one of the sub-blocks numbered lower than the transformation advanced sub-block within the macroblock. The inverse DCT hardware performs inverse DCT on inverse-quantized transform coefficients of the transformation advanced sub-block before performing inverse DCT on inverse-quantized transform coefficients of the transformation overtaken sub-block. Furthermore, the DCT hardware performs DCT on residual values of the transformation advanced sub-block and the inverse DCT hardware performs inverse DCT on inverse-quantized transform coefficients of a parallel executed sub-block in parallel. The parallel executed sub-block is one of the sub-blocks numbered lower than the transformation advanced sub-block within the macroblock. 
         [0008]    An advanced video coding and decoding method in accordance with an exemplary embodiment of the disclosure comprises: using discrete cosine transform (DCT) hardware to perform DCT on residual values of a transformation advanced sub-block before performing DCT on residual values of a transformation overtaken sub-block, wherein the transformation advanced sub-block is one of the sub-blocks, numbered from 0 to 15, of a macroblock, and the transformation overtaken sub-block is one of the sub-blocks numbered lower than the transformation advanced sub-block within the macroblock; using inverse DCT hardware to perform inverse DCT on inverse-quantized transform coefficients of the transformation advanced sub-block before performing inverse DCT on inverse-quantized transform coefficients of the transformation overtaken sub-block; and, using the DCT hardware to perform DCT on residual values of the transformation advanced sub-block when using the inverse DCT hardware to perform inverse DCT on inverse-quantized transform coefficients of a parallel executed sub-block, wherein the parallel executed sub-block is one of the sub-blocks numbered lower than the transformation advanced sub-block within the macroblock. 
         [0009]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0011]      FIG. 1  depicts how an advanced video coding and decoding chip  100  is used in different applications; 
           [0012]      FIG. 2  is a block diagram depicting the internal hardware of the advanced video coding and decoding chip  100  in accordance with an exemplary embodiment of the disclosure; 
           [0013]      FIG. 3  includes a left picture illustrating a conventional sequence for processing sub-blocks within a macroblock, and a right picture illustrating an optimized sequence for performing DCT and inverse DCT on the sub-blocks in accordance with an exemplary embodiment of the disclosure; and 
           [0014]      FIG. 4  depicts hardware timing diagrams, the upper timing diagram corresponding to the conventional sequence illustrated in the left picture of  FIG. 3  and the lower timing diagram corresponding to the optimized sequence illustrated on the right picture of  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    The following description is of several exemplary embodiments carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0016]      FIG. 1  depicts how an advanced video coding and decoding chip  100  is used in different applications. The advanced video coding and decoding chip  100  may be fabricated by a system-on-chip (SOC) technology for advanced video coding and decoding like H.264. The advanced video coding and decoding chip  100  may retrieve video data from a high-definition multimedia interface (HDMI)  102 , a YPbPr input  104 , a multiple CVBS input  106 , an SCART input  108 , an RGB input  110 , a hybrid tuner  112 , an USB 3.0 input  114 , an RJ45 input  116  and so on, and stores the encoded and compressed video into a storage device  118 . The advanced video coding and decoding chip  100  may further recover a high-definition video from the compressed video, and the high-definition video is displayed on the display  120 . 
         [0017]      FIG. 2  is a block diagram depicting the internal hardware of the advanced video coding and decoding chip  100  in accordance with an exemplary embodiment of the disclosure. A macroblock with 16×16 pixels and containing 16 sub-blocks each having 4×4 pixels is introduced as an encoding unit. There are two types of coding algorithms: intra prediction coding; and inter prediction coding. The intra prediction coding generates predicted pixels P from the pixels within the current field F(n). As for the inter prediction coding, a reconstructed field F′(n−1), also known as a reference field, of the previous field is also taken into account to generate the predicted pixels P. Residual values D(n) are calculated from the difference between the predicted pixels P and the current field F(n). The residual values D(n) are transformed into transform coefficients C by DCT hardware  202  and quantization hardware  204 . The DCT hardware  202  processes the sub-blocks within a macroblock in an optimized sequence. Then, the transform coefficients C are transformed into an advanced video coding stream  208  by entropy coding hardware  206 . Furthermore, the transform coefficients C are further converted by inverse quantization hardware  210  and inverse DCT hardware  212  to generate reconstructed residual values D′(n). The inverse DCT hardware  212  also processes the sub-blocks within the macroblock in the optimized sequence. The residual values D′(n) are added back to the predicted pixels P to form reconstructed pixels μF(n). The reconstructed pixels μF′(n) are processed by deblocking filter hardware  214  and thereby a reconstructed field F′(n) is reconstructed as a reference field for the next coding field. 
         [0018]    As mentioned above, the DCT hardware  202  and the inverse DCT hardware  212  of  FIG. 2  process the sub-blocks within a macroblock in an optimized sequence. The DCT hardware  202  operated in accordance with the optimized sequence is about a “transformation” scheme while the inverse DCT hardware  212  operated in accordance with the optimized sequence is about a “reconstruction” scheme. With respect to the optimized sequence that the hardware  202  and  204  process the sub-blocks in one macroblock, the quantization (performed by hardware  204  and  210 ) of the sub-blocks in the macroblock may be operated in the same optimized sequence.  FIG. 3  illustrates an optimized sequence of processing sub-blocks within a macroblock for DCT (about the “transformation” scheme) and inverse DCT (about the “reconstruction” scheme) in the right picture in accordance with an exemplary embodiment of the disclosure. In the left picture of  FIG. 3 , a conventional sequence of processing sub-blocks within a macroblock for DCT and inverse DCT is illustrated. The 16 sub-blocks (each having 4×4 pixels) are further divided into an upper left part (containing the sub-blocks numbered from 0 to 3 and arranged in the upper left side, upper right side, lower left side and lower right side of the upper left part in order), an upper right part (containing the sub-blocks numbered from 4 to 7 and arranged in the upper left side, upper right side, lower left side and lower right side of the upper right part in order), a lower left part (containing the sub-blocks numbered from 8 to 11 and arranged in the upper left side, upper right side, lower left side and lower right side of the lower left part in order), and a lower right part (containing the sub-blocks numbered from 12 to 15 and arranged in the upper left side, upper right side, lower left side and lower right side of the lower right part in order). Referring to the left picture of  FIG. 3 , the conventional sequence from the number 0 sub-block to the number 15 sub-block in order is for DCT (about the “transformation” scheme) and inverse DCT (about the “reconstruction” scheme) on the sub-blocks within a macroblock. Referring to the right picture of  FIG. 3 , the optimized sequence is:
       0→1→2→ 4→3 →5→ 8→6→9→7 →10→ 12→11 →13→14→15,
 
which is different from the conventional sequence from the number 0 sub-block to the number 15 sub-block in order. The underlined numbers are the difference between the optimized sequence and the conventional sequence. According to the optimized sequence shown in the right picture of  FIG. 3 , each sub-block with 4×4 pixels is transformed/reconstructed when the left, upper and upper right sub-blocks corresponding thereto have been transformed/reconstructed. For example, before transforming/reconstructing the number 3 sub-block, the upper sub-block (numbered ‘1’), the left sub-block (numbered ‘2’) and the upper right sub-block (numbered ‘4’) with respect to the number 3 sub-block have been transformed/reconstructed already. The other sub-blocks all are transformed/reconstructed in accordance with the same concept.
       
 
         [0020]    DCT performed on one sub-block is based on the reconstructed values of the corresponding left sub-block and upper sub-block or even the upper right sub-block. However, in accordance with the optimized sequence shown in the right picture of  FIG. 3 , the “transformation” scheme (corresponding to the operations of the DCT hardware  202 ) and “reconstruction” scheme (corresponding to the operations of the DCT hardware  212 ) for some series of sub-blocks may be performed in parallel. 
         [0021]      FIG. 4  depicts hardware timing diagrams, the upper timing diagram corresponding to the conventional sequence illustrated in the left picture of  FIG. 3  and the lower timing diagram corresponding to the optimized sequence illustrated on the right picture of  FIG. 3   
         [0022]    According to the conventional sequence shown in the left picture of  FIG. 3  for processing the sub-blocks of one macroblock, after the DCT (about the “transformation” scheme) of the number 0 sub-block is finished, the DCT (about the “transformation” scheme) still cannot be performed on the number 1 sub-block until the inverse DCT (about the “reconstruction” scheme) on the number 0 sub-block is finished. The DCT on the number 2 sub-block depends on the reconstruction values of the number 0 and number 1 sub-blocks. Therefore, the DCT (about the “transformation” scheme) on the number 2 sub-block is allowed to be performed after the inverse DCT (about the “reconstruction” scheme) on the number 1 sub-block has been finished. The DCT on the number 3 sub-block depends on the reconstruction values of the number 1 and number 2 sub-blocks. Therefore, the DCT (about the “transformation” scheme) on the number 3 sub-block is allowed to be performed after the inverse DCT (about the “reconstruction” scheme) on the number 2 sub-block has been finished. In this manner, as shown in the upper timing diagram of  FIG. 4 , the DCT calculations (about the “transformation” scheme) performed on the sub-blocks numbered from 0 to 15 are interlaced with the inverse DCT calculations (about the “reconstruction” scheme) performed on the sub-blocks numbered from 0 to 15. 
         [0023]    According to the optimized sequence shown in the right picture of  FIG. 3  for processing the sub-blocks of one macroblock, the “transformation” scheme and the “reconstruction” scheme for the macroblock may be at least partially performed in parallel. Referring to the lower timing diagram of  FIG. 4 , the DCT on the number 4 sub-block may be performed right after finishing the DCT on the number 2 sub-block because of the available reconstruction value of the number 1 sub-block. The DCT on the number 3 sub-block may be performed right after finishing the DCT on the number 4 sub-block because of the available reconstruction value of the number 2 sub-block. Likewise, there are other series of consecutively DCT processed sub-blocks. As shown, the DCT calculations on the number 4, 3, 5, 8, and 6 sub-blocks (about the “transformation” scheme) are performed in parallel with the inverse DCT calculations on the number 2, 4, 3, 5, and 8 sub-blocks (about the “reconstruction” scheme). The DCT calculations on the number 7, 10, 12, 11 and 13 sub-blocks (about the “transformation” scheme) are performed in parallel with the inverse DCT calculations on the number 9, 7, 10, 12 and 11 sub-blocks (about the “reconstruction” scheme). Based on the optimized sequence, the coding speed is increased. As indicated by the arrow, when the hardware using the optimized sequence completes the calculations, the number 11 sub-block is just starting to be processed in the upper timing diagram. 
         [0024]    In other exemplary embodiments, there may be some modifications made on the optimized sequence illustrated in the right picture of  FIG. 3 . 
         [0025]    Referring back to  FIG. 2 , the DCT hardware  202  may perform DCT on residual values D(n) of a transformation advanced sub-block before performing DCT on residual values D(n) of a transformation overtaken sub-block. The transformation advanced sub-block is one of the sub-blocks, numbered from 0 to 15, of a macroblock and the transformation overtaken sub-block is one of the sub-blocks numbered lower than the transformation advanced sub-block within the macroblock. The inverse DCT hardware  212  performs inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the transformation advanced sub-block before performing inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the transformation overtaken sub-block. Furthermore, the DCT hardware  202  performs DCT on residual values D(n) of the transformation advanced sub-block and the inverse DCT hardware  212  performs inverse DCT on inverse-quantized transform coefficients (output from  210 ) of a parallel executed sub-block in parallel. The parallel executed sub-block is one of the sub-blocks numbered lower than the transformation advanced sub-block within the macroblock. Any optimized sequence with the aforementioned concept of the transformation advanced sub-block, transformation overtaken sub-block and parallel executed sub-block may be considered within the scope of the invention. 
         [0026]    Another exemplary embodiment of the disclosure is described in this paragraph. The DCT hardware  202  performs DCT on residual values D(n) of the number 4 sub-block before performing DCT on residual values D(n) of a number 3 sub-block, and the inverse DCT hardware  212  performs inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the number 4 sub-block before performing inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the number 3 sub-block. The DCT hardware  202  performs DCT on residual values D(n) of the number 4 sub-block and the inverse DCT hardware  212  performs inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the number 2 sub-block in parallel. The DCT hardware  202  performs DCT on residual values D(n) of the number 3 sub-block and the inverse DCT hardware  212  performs inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the number 4 sub-block in parallel. 
         [0027]    Another exemplary embodiment of the disclosure is described in this paragraph. The DCT hardware  202  performs DCT on residual values D(n) of the number 12 sub-block before performing DCT on residual values D(n) of a number 11 sub-block, and the inverse DCT hardware  212  performs inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the number 12 sub-block before performing inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the number 11 sub-block. The DCT hardware  202  performs DCT on residual values D(n) of the number 12 sub-block and the inverse DCT hardware  212  performs inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the number 10 sub-block in parallel. The DCT hardware  202  performs DCT on residual values D(n) of the number 11 sub-block and the inverse DCT hardware  212  performs inverse DCT on inverse-quantized transform coefficients (output from  210 ) of the number 12 sub-block in parallel. 
         [0028]    Any technique using the aforementioned concept in advanced video coding and decoding is within the scope of the invention. The invention further involves advanced video coding and decoding methods, which are not limited to any specific hardware architecture. 
         [0029]    While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.