Abstract:
A low input-current-harmonic three-phase three-level boost rectifier includes an input stage for receiving a three-phase input voltage in relation to a neutral node and an output stage adapted to couple to at least one load. The rectifier further includes one or more switching converter stages, each having a plurality of serially-connected switches coupled to the neutral node, one of the serially-connected switches operating with a fixed duty cycle while the other of the serially-connected switches operating with a variable duty cycle, the fixed duty cycle being a substantially 50% duty cycle and the variable duty cycle being less than or equal to a substantially 50% duty cycle. The serially-connected switches are coupled to clamping diodes and clamping capacitors. The rectifier further includes one or more controllers adapted to vary the switching frequency and/or duty cycle of the plurality of switches based on at least one of a condition of the at least one load or the input voltage and includes one or more decoupling stages, each including one or more inductive elements adapted to inductively decouple the output stage from at least one of the one or more switching converter stages.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation-in-part of copending U.S. patent application (“Copending Application”), Ser. No. 13/362,620, entitled “THREE-PHASE SOFT-SWITCHED PFC RECTIFIERS,” by Jang and Jovanović, filed on Jan. 27, 2012, and assigned the attorney docket number 36977-320233. The Copending Application is hereby incorporated by reference herein in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention generally relates to front-end rectifiers with power-factor correction (PFC). In particular, the present invention relates to three-phase, three-level PFC rectifiers. 
         [0004]    2. Discussion of the Related Art 
         [0005]    In power converters, achieving a high efficiency in high-voltage applications is a major design challenge that requires an optimized reduction of conduction and switching losses through a careful selection of the converter topology and switching device characteristics. Specifically, a higher voltage-rated semiconductor switch exhibits larger conduction and switching losses, as compared to a counterpart with a lower voltage rating. In this context, a semiconductor switch may be any switching device, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated-Gate Bipolar Transistors), a BJT (Bipolar Junction Transistors), a SiC (Silicon-Carbide) or a GaN (Gallium-Nitride). 
         [0006]    Generally, switching losses can be reduced and even eliminated using resonant or soft-switching techniques. However, there are only limited approaches for reducing conduction losses. In fact, once the topology and the switches with the lowest conduction losses for the required voltage rating are selected, further decrease in conduction loss is possible only by modifying the topology to utilize switches with a lower voltage rating. Multilevel converters—whose switches operate with a voltage stress that is much less than the input and output voltages—are naturally suitable for high-voltage applications. 
         [0007]    The Copending Application describes a new, three-phase, two-switch, zero-voltage switching (ZVS), discontinuous conduction mode (DCM), PFC boost rectifier that achieves a low input-current total harmonic distortion (THD). In that PFC boost rectifier, all the switches operate under ZVS conditions, without using additional soft-switching circuitry. One implementation of the PFC rectifier of the Copending Application is shown in  FIG. 1 . As shown in  FIG. 1 , the PFC boost rectifier includes Y-connected capacitors C 1 , C 2 , and C 3 , which create virtual neutral node N. Virtual neutral node N has the same electrical potential as the power source&#39;s neutral terminal that is not physically available for connection in a three-wire power system. Since virtual neutral node N is connected to the node between switches S 1  and S 2  and also to the node between output capacitors C O1  and C O2 , the electrical potentials of these nodes are the same as the electrical potential of the neutral terminal in the balanced three-phase power source. 
         [0008]    In addition, by connecting virtual neutral node N directly to the node between switches S 1  and S 2 , decoupling of the three input currents is achieved. In such a decoupled circuit, the current in each of boost inductors L 1 , L 2  and L 3  depends only on the corresponding phase voltage, which reduces the THD and increases the power factor (PF). Specifically, bridge diodes D 1 -D 6  allow only the currents in phases with positive phase voltages to flow through switch S 1 , when switch S 1  is turned on, and allow only the currents in phases with negative phase voltages to flow through switch S 2 , when switch S 2  is on. Therefore, the boost inductor corresponding to a phase in a positive voltage half-line cycle carries positive current when switch S 1  is on, while the boost inductor corresponding to a phase in a negative voltage half-line cycle carries negative current when switch S 2  is on. During the time when switch S 1  is off, the stored energy in the boost inductor connected to the positive phase voltage is delivered to capacitor C R , whereas the stored energy in the boost inductor connected to the negative phase voltage is delivered to capacitor C R  during the time when switch S 2  is off. Because the voltage between either terminal of capacitor C R  and virtual neutral node N abruptly changes with a high rate (i.e., a large dV/dt value) during each switching cycle, coupled inductor L C  is connected between “flying” capacitor C R  and the output voltage V O  to isolate output voltage V O  from these fast high-voltage transitions that usually produce unacceptable common-mode electromagnetic interference (EMI) noise. As shown in  FIG. 1 , with coupled inductor L C , the node between output capacitors C O1  and C O2  can be directly connected to virtual neutral node N, which makes the output common-mode noise very low. Moreover, because of coupled inductor L C , parallel operations of multiple rectifiers are also possible. 
         [0009]    To facilitate cross-reference between the figures and the detailed description, like elements are assigned like reference names or numerals. 
       SUMMARY 
       [0010]    The present invention extends PFC and ZVS operations of the switches in the rectifier of  FIG. 1  to three-level rectifiers that can utilize switches with a lower voltage rating and, consequently, a lower conduction loss. 
         [0011]    According to one embodiment of the present invention, three-phase, three-level PFC rectifier topologies utilize switches with a lower voltage rating and offer improved performance over the prior art because of lower conduction losses. In one preferred embodiment, an input stage consists of three boost inductors L 1 , L 2 , and L 3  coupled to the three-phase input terminals and capacitors C 1 , C 2 , and C 3  connected in a Y or “star” configuration. Common node N of the capacitors is connected to a node between serially-connected switch pairs S 1 -S 2  and S 3 -S 4  and also to a node between serially connected output split capacitors C O1  and C O2 . A node between serially-connected switches S 1 -S 2  is connected to output capacitor C O1  through clamping diode D C1 . A node between serially-connected switches S 3 -S 4  is connected to output capacitor C O2  through clamping diode D C2 . Capacitor C R , which resets the currents in the boost inductors, is connected across serially connected switches S 1 -S 4  and output V O  by coupled or non-coupled inductor L C . 
         [0012]    The rectifiers of the present invention offer a low THD in the input currents and a high PF. The rectifiers provide high efficiency power conversion using soft-switching techniques over a wide load range. This high efficiency is achieved by operating the boost inductors in DCM and by controlling the output voltages in the rectifiers using variable-frequency control. In addition, the PFC rectifiers of the present invention exhibit a reduced common-mode noise and possess automatic balancing of split capacitors C O1  and C O2 , when serially-connected downstream converters are employed. 
         [0013]    In one implementation, galvanic isolation between the input signal and the output signal is achieved using transformer TR, instead of coupled inductor L C . At the secondary side of transformer TR, rectifiers D O1  and D O2  and output filter including inductor L O  and capacitor C O  are coupled between the secondary winding of transformer TR and output voltage V O . By employing additional phase-shift or PWM control, the isolated implementations can tightly control their output voltages. Circuits may also be interleaved to increase their power handling capabilities and reduce their input or output current and voltage ripples. 
         [0014]    The present invention is better understood upon consideration of the following detailed description and the accompanying figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  shows a three-phase, two-switch, ZVS, PFC DCM boost rectifier. 
           [0016]      FIG. 2  shows a three-phase three-level ZVS PFC DCM boost rectifier, according to an embodiment of the present invention. 
           [0017]      FIGS. 3(   a )- 3 ( c ) each show, under one of three different control schemes, gating waveforms of switches S 1 -S 4  of  FIG. 2  during a switching cycle, according to an embodiment of the present invention. 
           [0018]      FIG. 4  shows a simplified model of the circuit in  FIG. 2 , annotated with reference directions of currents and voltages, according to an embodiment of the present invention. 
           [0019]      FIGS. 5(   a )- 5 ( n ) show topological stages illustrating voltages and currents in the model of  FIG. 4  during a switching cycle, according to an embodiment of the present invention. 
           [0020]      FIG. 6  shows the key waveforms in the model of  FIG. 4 , according to an embodiment of the present invention. 
           [0021]      FIG. 7  shows a three-phase three-level ZVS PFC DCM boost rectifier with two independent loads, according to an embodiment of the present invention. 
           [0022]      FIG. 8  shows a three-phase three-level ZVS PFC DCM boost rectifier with two independent inductors, according to an embodiment of the present invention. 
           [0023]      FIG. 9  shows a three-phase three-level ZVS PFC DCM boost rectifier with a blocking capacitor between a virtual neutral node and the node between two split output capacitors, according to an embodiment of the present invention. 
           [0024]      FIG. 10  shows a three-phase three-level ZVS PFC DCM boost rectifier in which snubber capacitors C S1 , and C S4  are connected in parallel to switches S 1  and S 4 , according to one embodiment of the present invention. 
           [0025]      FIG. 11  shows three-phase three-level ZVS PFC DCM boost rectifiers supporting parallel or interleaved operations, according to an embodiment of the present invention. 
           [0026]      FIG. 12  shows interleaved three-phase three-level ZVS PFC DCM boost rectifiers including DC current blocking capacitor C B , according to an embodiment of the present invention. 
           [0027]      FIG. 13  shows interleaved three-phase three-level ZVS PFC DCM boost rectifiers including DC current blocking capacitors C B1  and C B2  and input filter capacitor sets C 1 -C 3  and C 4 -C 6 , according to an embodiment of the present invention. 
           [0028]      FIG. 14  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with two transformers and an additional phase-shift control scheme, according to an embodiment of the present invention. 
           [0029]      FIG. 15  shows gating waveforms of switches S 1 -S 8  of the circuit in  FIG. 14  during a switching cycle, according to an embodiment of the present invention. 
           [0030]      FIG. 16  shows another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifiers with two transformers and an additional phase-shift control scheme, according to an embodiment of the present invention. 
           [0031]      FIG. 17  shows gating waveforms of switches S 1 -S 8  of the circuit in  FIG. 16  during a switching cycle, according to an embodiment of the present invention. 
           [0032]      FIG. 18  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with transformer TR and split flying capacitors C R1  and C R2 , according to an embodiment of the present invention. 
           [0033]      FIG. 19  shows gating waveforms of switches S 1 -S 4  in the circuit of  FIG. 18  during a switching cycle, according to an embodiment of the present invention. 
           [0034]      FIG. 20  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with a transformer and clamping diodes coupled to a node between split flying capacitors, according to an embodiment of the present invention. 
           [0035]      FIG. 21  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with an auxiliary boost converter that uses the leakage inductances of the coupled inductor as auxiliary boost inductors, according to an embodiment of the present invention. 
           [0036]      FIG. 22  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with an auxiliary boost converter having auxiliary boost inductors L H1  and L H2 , according to an embodiment of the present invention. 
           [0037]      FIG. 23  shows another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with an auxiliary boost converter that uses the leakage inductances of the coupled inductor as auxiliary boost inductors, according to an embodiment of the present invention. 
           [0038]      FIG. 24  shows yet another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with an auxiliary boost converter having auxiliary boost inductors L H1  and L H2 , according to an embodiment of the present invention. 
           [0039]      FIG. 25  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with a full-bridge primary configuration and transformers TR 1  and TR 2 , according to an embodiment of the present invention. 
           [0040]      FIG. 26  shows another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with a full-bridge primary configuration and a transformer, according to an embodiment of the present invention. 
           [0041]      FIG. 27  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with coupled two half-bridge primary configuration and series connected two transformers, according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0042]      FIG. 2  is a block diagram of a three-phase, three-level ZVS PFC DCM low input-current-harmonic boost rectifier according to an embodiment of the present invention. The input stage of the circuit in  FIG. 2  includes boost inductors L 1 , L 2 , and L 3  coupled to capacitors C 1 , C 2 , and C 3  connected in a Y (“star”) configuration. The input stage of the circuit may also include an EMI filter (not shown in  FIG. 2 ) at the three-phase input terminals. The common node N of capacitors C 1 , C 2 , and C 3  is connected to a node between serially-connected switch pairs S 1 -S 2  and S 3 -S 4  and also to a node between split output capacitors C O1  and C O2 . The node between serially-connected switches S 1 -S 2  is connected to output capacitor C O1  through clamping diode D C1 , so that the voltage across switch S 2  is clamped to the voltage across capacitor C O1 , which is preferably one half of output voltage V O . The node between serially-connected switches S 3 -S 4  is connected to output capacitor C O2  through clamping diode D C2  and the voltage across switch S 3  is also clamped to one-half of output voltage V O , preferably. Clamping capacitor C C  is connected across split output capacitors C O1  and C O2 , and is pre-charged to its steady-state average voltage of one-half of the output voltage through the loop consisting of capacitor C O2 , the body diode of switch S 2 , pre-charge resistor R PR , and a winding of coupled inductor L C . Capacitor C R  which resets the boost inductor currents is connected across serially-connected pairs of switches S 1 -S 2  and S 3 -S 4 , and is decoupled from output voltage V O  by inductor L C . The average voltage across capacitor C R  is equal to output voltage V O  since the average voltage across the windings of L C  is zero. The voltages across switches S 1  and S 4  are clamped to the difference in voltage across capacitor C R  and C C  by the body diodes of switch S 4  and switch S 1 . Since this difference in voltage is equal to one-half of output voltage V O , the voltage across each of the four switches S 1 -S 4  in the circuit in  FIG. 2  is one-half of output voltage V O . Generally, any kind of switch that is capable of conducting current in both directions and blocking voltage in one direction with an antiparallel diode (e.g., a MOSFET or an IGBT) is suitable for this application. 
         [0043]    The Y-connected capacitors C 1 , C 2 , and C 3  create virtual ground node N, i.e., a node with the same electrical potential as the input (source) voltage neutral wire that is not physically available or connected in a three-wire power system. By connecting virtual neutral node N directly to the nodes between switch pairs S 1 -S 2  and S 3 -S 4 , decoupling of the three input currents is achieved. In such a decoupled circuit, the current in each of boost inductors L 1 , L 2  and L 3  depends only on the corresponding phase voltage, which reduces the THD and increases the PF. Specifically, in the circuit in  FIG. 2 , bridge diodes D 1 -D 6  allow only a positive input voltage to deliver currents through series connected switches S 1  and S 2  when these switches are turned on and a negative input voltage to deliver currents through series connected switches S 3  and S 4  when these switches are turned on. The switches may each be turned on at a substantially zero voltage across the switches. Therefore, any boost inductor in a phase with a positive voltage half-line cycle carries positive current when switches S 1  and S 2  are on, while any boost inductor in a phase with a negative voltage half-line cycle carries negative current when switches S 3  and S 4  are turned on. During the time when switches S 1  and S 2  are turned off, the stored energy in the boost inductor connected to the positive phase voltage is delivered to capacitor C R , while the stored energy in the boost inductor connected to the negative phase voltage is delivered to capacitor C R  during the time when switches S 3  and S 4  are turned off. 
         [0044]    Because in every switching cycle the voltage across capacitor C R  changes rapidly (i.e., with a large dV/dt value), coupled inductor L C  connects between “flying” capacitor C R  and output voltage V O  to isolate output voltage V O  from these fast high-voltage transitions that usually produce unacceptable common-mode EMI noise. With coupled inductor L C , the output common-mode noise is very low, as the noise is confined to the S 1 -S 2 -S 3 -S 4 -C R  loop. Moreover, because coupled inductor L C  provides impedance between output voltage V O  and switches S 1 -S 4 , parallel or interleaving operations of multiple rectifiers are possible. 
         [0045]    To achieve a low input-current THD, high PF, and soft-switching of switches S 1 -S 4  over a wise load range, the circuit in  FIG. 2  must operate in DCM with a low-bandwidth output-voltage control scheme. This control scheme can be implemented in a variety of ways.  FIG. 3(   a ) shows gating waveforms for controlling switches S 1 -S 4  in  FIG. 2  under a variable switching-frequency control scheme. Under the variable-frequency control scheme of  FIG. 3(   a ), switch pairs S 1 -S 2  and S 3 -S 4  are switched in a complementary fashion, with a small dead time t d  between their commutation instants to enable the switch pair that is about to turn on to achieve ZVS. Since dead time t d  is very small in comparison with switching period T S , the effect of the dead time on the duty cycle is negligible, i.e., the duty cycle of each switch pair is approximately 50%. 
         [0046]      FIG. 3(   b ) shows a second control scheme for switches S 1 -S 4  of  FIG. 2 . Under this second control scheme, switches S 1  and S 4  are switched at a constant frequency in a complementary fashion with a small dead time in-between, i.e., each switch operates at an approximate 50% duty cycle. Switches S 2  and S 3 , whose turn-on instants are synchronized with the turn on instants of S 1  and S 4 , respectively, are each pulse-width modulated to provide regulation of output voltage V O . 
         [0047]      FIG. 3(   c ) shows a third alternative control scheme for switches S 1 -S 4  of  FIG. 2 . Under this third control scheme, in each of switch pairs S 1 -S 4  and S 2 -S 3 , the switches within the switch pair are switched at a constant frequency in a complementary fashion with a fixed duty cycle of approximately 50%. The control scheme provides a phase shift between the switching instants of the S 1 -S 4  pair and the corresponding switching instants of the S 2 -S 3  pair. In this phase-shift control scheme, the output voltage is zero when the phase shift is zero and reaches a maximum when the phase shift is 180 0  (i.e., when the phase shift is T S /2). 
         [0048]    The control schemes illustrated in  FIGS. 3(   a )-( c ) may be used in a combination. Namely, the variable switching frequency control scheme of  FIG. 3(   a ) can be used in any combination with the constant frequency PWM control scheme of  FIG. 3(   b ), or with the phase-shift control scheme of  FIG. 3(   c ), to limit the switching frequency range. For example, in the output voltage-regulated converter of  FIG. 2 , the switching frequency increases as the load decreases. Thus, the frequency range can be reduced by a variable switching-frequency control scheme at full and medium loads, while switching over to a constant frequency control scheme at lighter loads. 
         [0049]      FIG. 4  shows a simplified model of the circuit of  FIG. 2 , annotated with reference directions of currents and voltages, according to an embodiment of the present invention. To simplify analysis, ripple voltages of the input and output filter capacitors in  FIG. 2  (i.e., capacitors C 1 , C 2 , C 3 , C O1  and C O2 ) are considered negligible in this model, so that the voltage across the input and output filter capacitors can be represented by constant-voltage source V AN , V BN , V CN , V O1 , and V O2 . Also, in the on state, the semiconductor switches exhibit zero resistance (i.e., they are short circuits). However, the output capacitances of the switches are not neglected in this model. Coupled inductor L C  in  FIG. 2  is modeled as a two-winding ideal transformer with magnetizing inductance L M  and leakage inductances L LK1  and L LK2 . In this model, the average voltage across flying capacitor C R  is substantially equal to output voltage V O =V O1 +V O2  and the average voltage across clamping capacitor C C  is substantially equal to one half of output voltage V O . The reference directions of currents and voltages in  FIG. 4  correspond to a 60-degree segment of the line cycle (i.e., when V AN &gt;0, V BN &lt;0, and V CN &lt;0). 
         [0050]      FIGS. 5(   a )- 5 ( n ) show topological stages illustrating voltages and currents in the model of  FIG. 4  during a switching cycle, according to an embodiment of the present invention.  FIG. 6  shows the key waveforms in the model of  FIG. 4 , according to an embodiment of the present invention. 
         [0051]    The waveforms of the gating signals of switches S 1 -S 4  in  FIG. 6  show that the control scheme used combines a variable-frequency control scheme and a constant-frequency phase-shift control scheme. In  FIG. 6 , switches S 1  and S 4  operate in a complementary manner. Likewise, switches S 2  and S 3  operate in a complementary manner. In either case, a short dead time is provided between the commutation instants (i.e., each switch operates with a fixed duty cycle of approximately 50%). This gating strategy enable ZVS in the switches that are about to turn on. To regulate output voltage V O  in the presence of input voltage and output load variations, a variable switching frequency control scheme is employed. However, to limit the control-frequency range and the consequential switching losses, the variable-frequency control scheme is assisted by a phase-shift control scheme at light loads or high input voltage, or both. 
         [0052]    In the model of  FIG. 4 , the minimum frequency occurs when both a full load and the minimum input voltage are present, while duty cycle is set substantially at 50%. The maximum frequency occurs when a light load and maximum input voltage are present, while duty cycle is set below 50%. If necessary, the rectifier of the present invention can operate in a controlled burst mode or pulse skip mode at no load or at a very light load, to avoid operation at an unnecessarily high switching frequency. Other control strategies could also be applied to this circuit, including constant-frequency PWM control and phase-shift control as shown in  FIGS. 3(   b ) and  3 ( c ) discussed above. 
         [0053]    Referring to  FIGS. 5(   a ) and  6 , before switch S 2  is turned off at t=T 1 , inductor current i L1  flows through closed switches S 1  and S 2 . The slope of inductor current i L1  is equal to V AN /L 1  and the peak of the inductor current at t=T 1  is approximately 
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         [0000]    where V AN  is line-to-neutral voltage and DT S  is the portion of the switching period T S  during which switches S 1  and S 2  are both closed (i.e., D is the effective duty cycle). Because the dead time between the turning-off of switch S 1  and the turning-on of switch S 4  is very short relative to switching period T S , the effect of the dead time is neglected in Equation (1). During the period between times T O  and T 1 , current i O1  decreases at a rate of −V O1 /(L M +L LK1 ) while current i O2  increases at a rate of (V CR −V O1 )/(L M +L LK2 ). Magnetizing current i M  is the difference between currents i O1  and i O2 . 
         [0054]    The magnetizing inductance value of coupled inductor L M  is selected to be sufficiently large, such that its ripple current does not significantly affect rectifier operation. As shown in  FIG. 2 , the windings of inductor L C  are coupled in such a way as to cancel the magnetic fluxes from the differential current of the two windings, so that the large magnetizing inductance can be achieved by a small gap in the core without saturation. Since the ripples in currents i O1  and i O2  are considered negligible in this model, further discussion is omitted, although the ripple currents are still shown in the topological stages in  FIG. 5 . 
         [0055]    At t=T 1 , switch S 2  turns off, inductor current i L1  begins to charge the parasitic output capacitance of switch S 2  ( FIG. 5(   b )). As the sum of the voltages across switches S 2  and S 3  is clamped to clamping capacitor voltage V CC , the output capacitance of switch S 3  discharges at the same rate as the output capacitance of switch S 2  is being charged until the output capacitance of switch S 2  is fully charged and clamping diode D C1  starts to conduct at t=T 2 , as shown in  FIG. 5(   c ) and  FIG. 6 . Shortly after t=T 2 , switch S 3  turns on under ZVS condition. 
         [0056]    During interval [T 2 , T 3 ], because clamping diode D C1  is forward biased, inductor current i L1  linearly decreases. The slope of inductor current i L1  is equal to (V AN −V O1 )/L 1  and the inductor current at t=T 3  is approximately 
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         [0057]    At t=T 3 , when switch S 1  turns off, inductor current i L1  begins charging the output capacitance of switch S 1 , as shown in  FIG. 5(   d ). Because the sum of the voltages across switches S 1  and S 4  is clamped to the voltage difference between flying capacitor voltage V CR  and clamping capacitor voltage V CC , the output capacitance of switch S 4  discharges at the same rate as the output capacitance of switch S 1  is charged, until the output capacitance of switch S 4  is fully discharged and the anti-parallel body diode of switch S 4  starts to conduct at t=T 4 , as shown in  FIG. 5(   e ) and  FIG. 6 . At t=T 5 , switch S 4  turns on a ZVS condition and inductor current i L1  is commutated from the antiparallel body diode of switch S 4  to the switch, as illustrated in  FIG. 5(   f ). Because the body diode of switch S 4  is forward biased and switch S 3  is switched on, inductor currents i L2  and 4 3  begin to linearly increase after t=T 4 . At t=T 5 , switch S 4  turns on under a ZVS condition and inductor currents i L2  and i L3  are commutated from the antiparallel body diode of switch S 4  to the switch, as illustrated in  FIG. 5(   f ), until inductor current i L1  decreases to zero at t=T 6 . To maintain DCM operation, the minimum voltage V CR (MIN)  across “flying” capacitor C R , which is equal to output voltage V O , is provided by: 
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         [0000]    where V AN-PK  is the peak line-to-neutral voltage. 
         [0058]    During the T 4 -T 6  interval, because inductor currents i L2  and i L3  both flow in an opposite direction from inductor current i L1 , the average current through switches S 3  and S 4  is reduced, resulting in reduced power losses in the switches. 
         [0059]    During the period between t=T 6  and t=T 7 , inductor currents i L2  and i L3  continue to flow through switches S 3  and S 4 , as illustrated in  FIG. 5(   g ). As shown in  FIG. 6 , the slopes of inductor currents i L2  and i L3  during this period are equal to −V BN /L 2  and −V CN /L 3 , respectively. The peaks of the inductor currents at the moment when switch S 3  turns off at t=T 7  are approximately 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    Therefore, as seen from Equations (1), (3), and (4), the peak inductor current is proportional to its corresponding input voltage, as long as duty cycle D is substantially constant during one half of the line cycle. 
         [0060]    After switch S 3  turns off at t=T 7 , inductor currents i L2  and i L3  start to simultaneously charge the output capacitance of switch S 3  and discharge the output capacitance of switch S 2 , as shown in  FIG. 5(   h ), until t=T 8 , when the output capacitance of switch S 3  is fully charged and clamping diode D C2  starts to conduct at t=T 8 , as shown in  FIG. 5(   i ) and  FIG. 6 . After t=T 8 , switch S 2  turns on under a ZVS condition. 
         [0061]    At time t=T 8 , because clamping diode D C2  is forward biased, inductor currents i L2  and i L3  begin to linearly increase until inductor current i L3  reaches zero at time t=T 9 . The slopes of inductor currents i L2  and i L3  are equal to (−V BN +V O2 )/L 2  and (−V CN +V O2 )/L 3 , respectively. Inductor current i L2  at t=T 10 , when switch S 4  turns off, is approximately 
         [0000]    
       
         
           
             
               
                 
                   
                     
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         [0062]    At t=T 10 , when switch S 4  turns off, inductor current i L2  starts to charge the output capacitance of switch S 4 , as shown in  FIG. 5(   k ). Because the sum of the voltages across switches S 1  and S 4  is clamped to the voltage difference between flying capacitor voltage V CR  and clamping capacitor voltage V CC , the output capacitance of switch S 1  discharges at the same rate as the output capacitance of switch S 4  is being charged, until the output capacitance of switch S 1  is fully discharged and the anti-parallel body diode of switch S 1  starts to conduct at t=T 11 , as shown in  FIG. 5(   l ) and  FIG. 6 . At t=T 12 , switch S 1  turns on under a ZVS condition and inductor currents i L2  is commutated from the antiparallel body diode of switch S 1  to the switch itself, as shown in  FIG. 5(   m ). At this time, because switches S 1  and S 2  are both on, inductor current i L1  begins to linearly increase after t=T 11 . During period T 12 -T 13 . increasing inductor current i L2 , continues to flow through switches S 1  and S 2 , as shown in  FIG. 5(   m ). Finally, after inductor current i L2  reaches zero at t=T 13 , a new switching cycle begins, as shown in  FIG. 5(   n ). 
         [0063]    The harmonic content of the average inductor currents i L1 -i L3  shown in  FIG. 6  is dominated by the 3 rd  harmonic. However, as the neutral wire in a three-wire power system is not available (or not connected), the phase currents cannot contain the triplen harmonics (the 3 rd  harmonic and the odd multiples of the 3rd harmonic). As a result, the circuit of the present invention exhibits a very low THD and a high PF, as the remaining harmonics contribute less than 1-2% of total current distortion. 
         [0064]    A PFC rectifier of the present invention may be implemented in many ways. For example,  FIG. 7  shows an implementation supporting independent loads R 1  and R 2 . Since the two-switch rectifier automatically balances the voltages across output capacitors C O1  and C O2 , no additional voltage-balancing circuit is required. Natural voltage-balancing is achieved because in the circuit in  FIG. 7 , the average voltages across switch pairs  S   1 -S 2  and S 3 -S 4  are equal to voltages V O1  and V O2  across capacitors C O1  and C O2 , respectively, as the average voltages across the windings of inductor L C  are zero. The average voltages of switch pairs S 1 -S 2  and S 3 -S 4  are equal to V CR /2, so that V O1 =V O2 =V CR /2. 
         [0065]    Alternatively, the circuits of the present invention may also be implemented using independent inductors L C1  and L C2 , as shown in  FIG. 8 , or with blocking capacitor C B , as shown in  FIG. 9 . By coupling blocking capacitor C B  between virtual neutral node N and output capacitors C O1  and C O2  ( FIG. 9 ), low frequency currents circulating between virtual neutral node N, switches S 2  and S 3  and the common node between capacitors C O1  and C O2  can be reduced. 
         [0066]      FIG. 10  shows an embodiment in which snubber capacitors C S1  and C S4  are connected in parallel with switches S 1  and S 4 . By adding snubber capacitors C S1  and C S4 , turn-off losses in switches S 1  and S 4  can be significantly reduced. 
         [0067]      FIG. 11  shows a circuit of the present invention that combines two sub-circuits (“PFC stages”) which operate in parallel or are interleaved, in accordance with one embodiment of the present invention. The PFC stages in  FIG. 11  each include an input portion of the circuit similar to that shown in  FIG. 2  (from the three-phase input voltage up to coupled inductor L C ). In parallel operation, switches S 1 , S 2 , S 5 , and S 6  are driven by a first gating signal, while switches S 3 , S 4 , S 7 , and S 8  are driven by a second gating signal that is complementary the first gating signal. In an interleaved operation, switches S 1 , S 2 , S 7 , and S 8  are driven by the first gating signal, while switches S 3 , S 4 , S 5 , and S 6  are driven by the second gating signal. The parallel and interleaved operations are made possible by coupled inductors L C1  and L C2 , which provide decoupling impedances between the output portion and the switches. 
         [0068]      FIG. 12  shows an interleaved three-phase three-level ZVS PFC DCM boost rectifier including DC current blocking capacitor C B , according to one embodiment of the present invention. By including blocking capacitor C B , a DC current circulating between the common nodes of switches S 2 , S 3 , S 6 , and S 7  and the common node of output capacitors C O1  and C O2  can be prevented. 
         [0069]      FIG. 13  shows an interleaved three-phase three-level ZVS PFC DCM boost rectifier including DC current blocking capacitors C B1  and C B2  and input filter capacitor sets C 1 -C 3  and C 4 -C 6 , according to one embodiment of the present invention. 
         [0070]      FIG. 14  shows three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier including transformers TR, and TR 2  and an additional phase-shift control scheme. A tightly controlled output voltage can be achieved without additional switches, when two isolated PFC rectifiers are connected in parallel. As shown in  FIG. 14 , transformers TR 1  and TR 2  replace coupled inductors L C1  and L C2  of  FIG. 13 . On the secondary side of transformers TR 1  and TR 2 , rectifiers D O1 -D O4  and the output filter formed by inductor L O  and capacitor C O  are coupled between the serially-connected secondary windings of transformers TR 1  and TR 2  and output voltage V O . Furthermore, using an additional phase-shift or PWM control scheme, the isolated circuits connected to the primary windings of transformers TR 1  and TR 2  can tightly control the output voltages to minimize unnecessary voltage ripples. 
         [0071]      FIG. 15  shows gating waveforms of switches S 1 -S 8  for the circuit of  FIG. 14 . Switches S 1  and S 2  of the first PFC stage turn on before switches S 7  and S 8  of the second PFC stage turn off. This phase shift between the two set of switches creates PWM voltage waveforms V P1  and V P2  across the primary windings of transformers TR 1  and TR 2 , as shown in  FIG. 15 . Switches S 2 , S 3 , S 6 , and S 7  turn off slightly earlier than switches S 1 , S 4 , S 5 , and S 8  turn off, which ensures that the switch voltages be clamped to one-half of the output voltage V O . Switches S 1 -S 8  operate with a slowly varying switching frequency and near 50% duty cycle to achieve high PF and low THD, while the phase shift is used to tightly regulate the output voltage. 
         [0072]      FIG. 16  shows another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with two transformers and an additional phase-shift control scheme. The circuit of  FIG. 16  is implemented using clamping diodes D C1  and D C2  that connect both the node between switches S 1  and S 2  and the node between switches S 3  and S 4  to the common node between split flying capacitors C R1  and C R2 , so as to clamp the voltages across switches S 1  and S 4 , respectively. The circuit of  FIG. 16  is also implemented with the secondary windings of transformers TR 1  and TR 2  connected in series to provide current sharing. 
         [0073]      FIG. 17  shows gating waveforms of switches S 1 -S 8  for the circuit in  FIG. 16 . Switches S 1  and S 2  of the first PFC stage turn on before switches S 7  and S 8  of the second PFC stage turn off. The phase shift between the two switching instants creates PWM voltage waveforms V P1  and V P2  across the primary windings of transformers TR 1  and TR 2 , as shown in  FIG. 17 . Switches S 1 , S 4 , S 5 , and S 8  turn off slightly earlier than switches S 2 , S 3 , S 6 , and S 7  turn off, which ensures that the switch voltages are clamped to one-half of output voltage V O . 
         [0074]    Generally, most off-line power supplies of today have two cascaded stages—a front-end PFC rectifier stage and an output isolated dc-dc converter stage. As a result, although the output voltage of the front-end PFC rectifier contains rectified line frequency voltage ripples, the secondary isolated dc-dc converter stage can regulate its output voltage by its own high-frequency bandwidth feedback control. A single-stage approach combines the functions of the two cascaded stages. As a result, a single-stage rectifier should achieve PFC as well as tight regulation of the output voltage. 
         [0075]      FIG. 18  shows a single-stage rectifier with an isolated output. The primary side of the isolated circuit of  FIG. 18  is similar to the circuit of  FIG. 2 , except that the circuit in  FIG. 18  includes flying capacitors C R1  and C R2  and additional transformer TR that has a primary winding and a center-tap secondary winding. On the secondary side of transformer TR, rectifiers D O1  and D O2  and output filter components L O  and C O  are coupled between the secondary winding of transformer TR and output voltage V O . To achieve high PF and low THD, the switching frequency of switches S 1 -S 4  are kept nearly constant during a half cycle of the line frequency. To keep the switching frequency substantially constant, a low-pass filter may be included in the path of the frequency-control feedback loop. As a result, the bandwidth of the frequency control feedback loop is lower than the line frequency, which produces significant voltage ripples across flying capacitor C R1  and C R2  at rectified line frequency (e.g., six times higher frequency than the fundamental frequency of the line). However, a tight regulation of the output voltage is achieved by an additional a high-pass filter in the path of the phase-shift or PWM high-band-width control feedback loop. 
         [0076]      FIG. 19  shows gating waveforms of switches S 1 -S 4  for the circuit of  FIG. 18 . The gating signals of switches S 1  and S 4  are phase shifted with respect to the corresponding gating signals of switches S 2  and S 3 . This phase shift creates PWM voltage waveforms across the primary windings of transformer TR. Switches S 1 -S 4  operate with a slowly varying switching frequency and near 50% duty cycle to achieve high PF and low THD, while the variation of the phase shift is used to tightly regulate the output voltage. 
         [0077]      FIG. 20  shows another three-phase, three-level single-stage isolated ZVS PFC DCM boost rectifier with a transformer and an additional phase-shift control scheme. The circuit is implemented by connecting clamping diodes D C1  and D C2  to the node between split flying capacitors C R1  and C R2 , so as to clamp the voltages across switches S 1  and S 4 , respectively. 
         [0078]      FIG. 21  shows yet another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with an auxiliary boost converter that consists of switch S H  and diodes D H1  and D H2 . The leakage inductances of coupled inductor L C  serve as a boost inductor for the auxiliary boost converter. The auxiliary boost converter begin operating immediately after the tree-phase input voltage goes to zero, to extend the output voltage regulation time. 
         [0079]      FIG. 22  shows another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with an auxiliary boost converter that consists of switch S H , diodes D H1  and D H2 , and auxiliary boost inductors L H1  and L H2 . 
         [0080]      FIG. 23  shows yet another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with an auxiliary boost converter that consists of switch S H , diodes D H1 -D H3 , and auxiliary boost inductors L H1  and L H2 . In  FIG. 23 , series diode D H1  of  FIG. 22  that connects between input bridge diodes D 1 -D 3  and switch S 1  has been eliminated. This approach is desirable for applications that require high efficiency operation. The leakage inductances of coupled inductor L C  serve as a boost inductor of the auxiliary boost converter. 
         [0081]      FIG. 24  shows another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with an auxiliary boost converter that consists of switch S H , diodes D H1 -D H4 , and auxiliary boost inductors L H1  and L H2 . 
         [0082]      FIG. 25  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with switches S 1 -S 8  and an isolated output, according to one embodiment of the present invention. The primary side of the isolated circuit in  FIG. 25  is similar to the circuit of  FIG. 2 , except that the circuit has split flying capacitors C R1  and C R2 , auxiliary switches S 5 -S 8 , additional clamping diodes D C3  and D C4 , and series connected transformers TR 1  and TR 2  each consisting of a primary winding and a center-tap secondary winding. On the secondary side of transformers TR 1  and TR 2 , rectifiers D O1 -D O4  and output filter components L O1 , L O2  and C O  are coupled between the secondary windings of transformers TR 1  and TR 2  and the output. Blocking capacitor C B  is connected in series with transformers TR 1  and TR 2  to eliminate any DC current through the primary windings of the transformers. The controller operates main switches S 1 -S 4  and auxiliary switches S 5 -S 8  to achieve frequency and phase-shift control, using the gating signal waveforms in  FIGS. 15 and 17 . The isolated single-stage implementation can achieve a tight control of its output voltage in addition to high PF and low THD. 
         [0083]      FIG. 26  shows another three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with switches S 1 -S 8  and an isolated output, according to an embodiment of the present invention. The primary side of the isolated circuit in  FIG. 26  is similar to the circuit of  FIG. 2 , except for split flying capacitors C R1  and C R2 , auxiliary switches S 5 -S 8 , additional clamping diodes D C3  and D C4 , and transformer TR that consists of a primary winding and a center-tap secondary winding. On the secondary side of transformer TR, rectifiers D O1 -D O2  and output filter components L O  and C O  are coupled between the secondary windings of transformer TR and output voltage V O . Blocking capacitor C B  is connected in series with transformer TR to eliminate any dc current flowing through the primary windings of transformer TR. 
         [0084]      FIG. 27  shows a three-phase three-level single-stage isolated ZVS PFC DCM boost rectifier with coupled half-bridge primary configurations and series connected transformers TR 1  and TR 2 , according to one embodiment of the present invention. 
         [0085]    Although the isolated circuits shown in  FIGS. 14-27  show the output circuit with a center-tap secondary winding of the transformer and two output diodes, the output circuit may also be implemented using any known output rectifier topology, such as the current doubler rectifier, the full-bridge rectifier, the half-bridge with voltage doubler capacitors, within the scope of the present invention. In addition, a synchronous rectifier can be employed instead of low-voltage diode rectifiers.