Abstract:
A computer readable medium stores a program causing a computer to execute a process for error recovery. The process includes: when an error is detected during transfer of dummy data for maintaining a link, executing device reset to recover from the error, and monitoring whether or not another error occurs during an error monitoring period starting from the device reset; when the other error occurs during the error monitoring period, executing the device reset to recover from the other error, monitoring whether or not still another error occurs during the error monitoring period starting from the device reset; counting number of the successive error monitoring periods in each of which the error occurs; and judging an error occurrence state based on a result of the counting.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    This invention relates to a computer readable medium storing an error recovery program, an error recovery apparatus, an error recovery method and a computer system. 
         [0003]    2. Related Art 
         [0004]    There is a system such as an optical communication system, which does not respond to a data communication request rapidly unless any data communications is always conducted for maintaining a communication link even when effective data is not being transferred. In such a system, an error may occur in a transmission path even when effective data is not being transferred. 
       SUMMARY 
       [0005]    According to an aspect of the invention, a computer readable medium stores a program causing a computer to execute a process for error recovery. The process includes: when an error is detected during transfer of dummy data for maintaining a link, executing device reset to recover from the error, and monitoring whether or not another error occurs during an error monitoring period starting from the device reset; when the other error occurs during the error monitoring period, executing the device reset to recover from the other error, monitoring whether or not still another error occurs during the error monitoring period starting from the device reset; counting number of the successive error monitoring periods in each of which the error occurs; and judging an error occurrence state based on a result of the counting. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Exemplary embodiments will be described in detail below with reference to the accompanying drawings wherein: 
           [0007]    In the accompanying drawings: 
           [0008]      FIG. 1  is a block diagram to show a computer system according to a first exemplary embodiment of the invention; 
           [0009]      FIG. 2  is a drawing to show the configuration of an interrupt request register in  FIG. 1 ; 
           [0010]      FIG. 3  is a flowchart to show the whole operation of the computer system according to the first exemplary embodiment of the invention; 
           [0011]      FIG. 4  is a flowchart to show the whole operation of the computer system according to the first exemplary embodiment of the invention; 
           [0012]      FIG. 5  is a flowchart to show the whole operation of the computer system according to the first exemplary embodiment of the invention; 
           [0013]      FIG. 6  is a flowchart to show the operation of a host computer according to the first exemplary embodiment of the invention; 
           [0014]      FIG. 7  is a timing chart to show the operation of the host computer according to the first exemplary embodiment of the invention; 
           [0015]      FIG. 8  is a block diagram to show a computer system according to a second exemplary embodiment of the invention; 
           [0016]      FIG. 9  is a drawing to show the configuration of an interrupt request register in  FIG. 8 ; and 
           [0017]      FIG. 10  is a flowchart to show the operation of a host computer according to the second exemplary embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
     First Exemplary Embodiment 
       [0018]      FIG. 1  is a block diagram to show a computer system  1  according to a first exemplary embodiment of the invention. This computer system  1  includes a host computer  2  serving as an error recovery apparatus and a semiconductor disk unit  4  serving as external storage device connected to the host computer  2  by a serial interface  3  of PCI Express (registered trademark). Although one external storage device is connected to the host computer  2  in  FIG. 1 , two or more external storage devices may be connected thereto. 
         [0019]    The host computer  2  has an application program  20  such as a document processing program, an operating system (OS)  21 , a file system  22  built in the OS  21 , and a device driver  23  for controlling the semiconductor disk unit  4 . The application program  20 , the OS  21 , the file system  22 , and the device driver  23  are stored in an HDD, and are executed by a CPU (not shown). The device driver  23  may be input into the host computer  2  from a recording medium such as a CD-ROM or may be input into the host computer  2  through a network such as the Internet. 
         [0020]    If an error occurs while effective data is being transferred or while dummy data for maintaining the link is being transferred, the device driver  23  performs error recovery processing as shown in flowcharts of  FIGS. 4 to 6  described later. As shown in  FIG. 1 , the device driver  23  includes a monitoring unit  23   a,  a recovery processing unit  23   b  and a judging unit  23   c.    
         [0021]    The semiconductor disk unit  4  includes a semiconductor disk (SSD) controller  40 , memory controllers  42 A and  42 B connected to the SSD controller  40  by an internal bus  41 , and memories  43 A and  43 B. The memories  43 A and  43 B serve as semiconductor memory and are connected to the memory controllers  42 A and  42 B. 
         [0022]    The memories  43 A and  43 B may be volatile memory such as DRAM or SRAM or nonvolatile memory. Two pairs of the memory controllers  42 A,  42 B and the memories  43 A,  43 B are used in  FIG. 2 . However, the invention is not limited to the two pairs. 
         [0023]    The internal bus  41  is implemented as an optical bus. The optical bus includes an optical waveguide, an incidence optical fiber optically coupled with the light-incidence end face of the optical waveguide, an emission optical fiber optically coupled with the light-emission end face of the optical waveguide, an electric-optic converter placed on the incidence side of the incidence optical fiber, and a photoelectric converter placed on the emission side of the emission optical fiber. The internal bus  41  is not limited to an optical bus and may be implemented as electric signal lines. 
         [0024]    The SSD controller  40  includes a register group  410  and an unconditional interrupt generating section  420 . The register group  410  includes registers such as a DMA register  411  in which information concerning DMA (direct memory access) (e.g., source address, destination address and data length) is set and an interrupt request register  412  in which an interrupt request is set. The unconditional interrupt generating section  420  generates an unconditional interrupt based on contents of the interrupt request register  412 . 
         [0025]      FIG. 2  shows the interrupt request register  412 . The interrupt request register  412  includes an error interrupt bit  412   a,  an unconditional interrupt bit  412   b,  a transfer completion interrupt bit  412   c  and a reserved bit  412   d.    
       Operation of First Exemplary Embodiment 
       [0026]    Next, the operation of the system  1  will be described with reference to  FIGS. 3 to 6 .  FIG. 6  is a flowchart to show the operation of the host computer  2 . 
       (1) Transfer of Effective Data 
       [0027]      FIG. 3  is a flowchart of the whole system  1  for transferring effective data (reading data). 
         [0028]    When the application program  20  of the host computer  2  makes a file read request through the file system  22 , the device driver  23  writes into the register of the SSD controller  40  to set information concerning DMA such as the source address and instructs the SSD controller  40  to start DMA transfer. 
         [0029]    The SSD controller  40  sets the information concerning DMA in the DMA register  411  of the register group  410  and sends a data read request to the memory controller  42  according to the data transfer start instruction from the device driver  23 . Dummy data for maintaining the link is also transmitted and received between the SSD controller  40  and the memory controller  42  through the internal bus  41  while effective data is not being transferred. 
         [0030]    The memory controller  42  reads data from the memory  43  and transfers the read data to the SSD controller  40 . The SSD controller  40  transfers the read data directly to a memory of the host computer  2  (DMA transfer). When the transfer is completed, the SSD controller  40  writes “1” into the transfer completion interrupt bit  412   c  of the interrupt request register  412  and interrupts the device driver  23  (transfer termination). 
         [0031]    Next, as shown in  FIG. 6 , when the device driver  23  reads the interrupt request register  412  (S 100 ) and confirms that the interrupt is performed the semiconductor disk unit  4  (home device) (YES at S 110 ), the device driver  23  sets clear of the transfer termination interrupt in the SSD controller  40  (S 120 ). The SSD controller  40  clears the transfer completion interrupt bit  412   c  of the interrupt request register  412 . 
         [0032]    The device driver  23  determines whether or not the interrupt is an error interrupt (S 130 ). If the device driver  23  determines that the interrupt is not an error interrupt (NO at S 130 ), the device driver  23  determines whether or not the interrupt is a data transfer completion interrupt (S 140 ). If the interrupt is a data transfer completion interrupt (YES at S 140 ), the device driver  23  notifies disk read completion to the file system  22 , which then notifies file read completion to the application program  20  (S 150 ). Then, the device driver  23  clears number of retries (S 160 ), and the interrupt processing is completed. 
       (2) If an Error Occurs during Transfer of Effective Data 
       [0033]    If an error occurs during transfer of effective data, the SSD controller  40  writes “1” into the error interrupt bit  412   a  of the interrupt request register  412 . When the device driver  23  reads the interrupt request register  412  (S 100 ) and confirms that the interrupt is an interrupt of the home device (YES at S 110 ), the device driver  23  sets clear of the error interrupt in the SSD controller  40  (S 120 ). The SSD controller  40  clears the error interrupt bit  412   a  of the interrupt request register  412 . 
         [0034]    The device driver  23  (the monitoring unit  23   a ) determines whether or not the interrupt is an error interrupt (S 130 ). If the device driver (the monitoring unit  23   a ) determines that the interrupt is an error interrupt (YES at S 130 ), the device driver  23  (the judging unit  23   c ) determines whether or not the number of retries is equal to or less than a predetermined value (S 170 ). If the device driver  23  (the judging unit  23   c ) determines that the number of retries is equal to or less than the predetermined value (YES at S 170 ), the device driver  23  (the judging unit  23   c ) increments the number of retries (S 180 ) and then the device driver  23  (the recovery processing unit  23   b ) executes device reset, namely, recovers from the error state (S 190 ). By executing the reset device, the registers of the register group  410  are cleared. 
         [0035]    Next, the device driver  23  determines whether or not data is being transferred at present (S 200 ). If the device deriver  23  determines that data is being transferred (YES at S 200 ), the device driver  23  executes data resending processing (S 210 ). The interrupt processing is completed. 
         [0036]    If an error occurs again after the data is resent, the steps S 100 , S 110 , S 120 , S 130 , S 170 , S 180 , S 190 , S 200  and S 210  are repeatedly executed. If the number of successive resending times (retries) during the data transfer exceeds the predetermined value (NO at S 170 ), the device driver  23  notifies a fatal error (S 220 ). As the notification of a fatal error, for example, an LED lamp may be lighted, a message may be displayed on a display, an alarm sound may be produced by a buzzer, or a voice message may be output from a loudspeaker. 
       (3) If an Error Occurs during Transfer of Dummy Data for Maintaining the Link (Error during Data Transfer from Memory Controller  42  to SSD Controller  40 ) 
       [0037]      FIG. 4  is a flowchart of the whole system  1  if an error occurs during transfer of dummy data for maintaining the link from the memory controller  42  to the SSD controller  40 . 
         [0038]    If an error occurs during transfer of dummy data for maintaining the link from the memory controller  42  to the SSD controller  40  and the SSD controller  40  detects the error, the SSD controller  40  writes “1” into the error interrupt bit  412   a  of the interrupt request register  412  and interrupts the device driver  23  (error occurrence). 
         [0039]    When the device driver  23  reads the interrupt request register  412  (S 100 ) and confirms that the interrupt is an interrupt of the home device (YES at S 110 ), the device driver  23  sets clear of the error interrupt in the SSD controller  40  (S 120 ). The SSD controller  40  clears the error interrupt bit  412   a  of the interrupt request register  412 . 
         [0040]    The device driver  23  (the monitoring unit  23   a ) determines whether or not the interrupt is an error interrupt (S 130 ). If the device driver  23  (the monitoring unit  23   a ) determines that the interrupt is an error interrupt (YES at S 130 ), the device driver  23  (the judging unit  23   c ) determines whether or not the number of retries is equal to or less than a predetermined value (S 170 ). If the number of retries is equal to or less than the predetermined value (YES at S 170 ), the device driver  23  (the recovery processing unit  23   b ) resets the device (S 190 ). By executing the device reset, the registers of the register group  410  are cleared. 
         [0041]    After resetting the device, the device driver  23  (the recovery processing unit  23   b ) performs error recovery processing and determines whether or not data is being transferred at present (S 200 ). If data is not being transferred at present (NO at S 200 ), the device driver  23  sets an unconditional interrupt in the SSD controller  40  (S 230 ). The SSD controller  40  writes “1” into the unconditional interrupt bit  412   b  of the interrupt request register  412 . 
         [0042]    The SSD controller  40  interrupts the device driver  23  (unconditional interrupt; an interrupt made by software (CPU) independently from a status of a hardware will be referred to as the “unconditional interrupt”). When the device driver  23  reads the interrupt request register  412  (S 100 ) and confirms that the interrupt is an interrupt of the home device (YES at S 110 ), the device driver  23  sets clear of the unconditional interrupt in the SSD controller  40  (S 120 ). The SSD controller  40  clears the unconditional interrupt bit  412   b  of the interrupt request register  412 . 
         [0043]    At this time, the interrupt processing is completed. However, since “1” is set in the unconditional interrupt bit  412   b,  the interruption processing is performed again. The other interruption processing will be described below. 
         [0044]    After the device reset (S 190 ), if an error occurs before the device deriver  23  reads the interrupt request register  412 , the device driver  23  (the monitoring unit  23   a ) determines the interrupt as the error interrupt (Yes at S 130 ). In this case, if the number of retries is equal to or less than the predetermined value (Yes at S 170 ), the device driver  23  (the judging unit  23   c ) increments the number of retries (S 180 ), (the recovery processing unit  23   b ) executes device reset (S 190 ) and sets the unconditional interrupt (S 230 ). That is, if an error occurs within a predetermined period (until the interrupt request register is read out; may be referred to as an “error monitoring period”) from the device reset (S 190 ), the device driver  23  reads the interrupt request register  412 , clears the interrupt (S 120 ), confirms that the number of retries is equal to or less than the predetermined value (YES at S 170 ), increments the number of retries (S 180 ), executes device reset (S 190 ), and sets the unconditional interrupt (S 230 ). 
         [0045]    If the number of retries exceeds the predetermined value (NO at S 170 ), the device driver  23  notifies a fatal error (S 220 ) as described above. 
         [0046]    On the other hand, if no error occurs after the device reset is executed (S 190 ) and before the interrupt request register is read out (S 100 ), the device driver  23  (the monitoring unit  23   a ) determines the interrupt as the error interrupt (No at S 130 ). In this case, the device driver  23  determines that the interrupt is not data transfer completion interrupt (No at S 140 ), clears the number of retries (S 160 ) and completes the interrupt processing. 
       (4) If an Error Occurs during Transfer of Dummy Data for Maintaining the Link (Error during Data Transfer from SSD Controller  40  to Memory Controller  42 ) 
       [0047]      FIG. 5  is a flowchart of the whole system  1  if an error occurs during transfer of dummy data for maintaining the link from the SSD controller  40  to the memory controller  42 . If an error occurs during transfer of dummy data for maintaining the link from the SSD controller  40  to the memory controller  42  and the memory controller  42  detects the error, the memory controller  42  notifies the error to the SSD controller  40 . The SSD controller  40  writes “1” into the error interrupt bit  412   a  of the interrupt request register  412 . The subsequent operation is similar to that previously described with reference to  FIG. 4  and therefore, will not be discussed again. 
         [0048]      FIG. 7  is a timing chart of the case where three successive errors occur during transfer of dummy data for maintaining the link. In  FIG. 7 , the “error monitoring period” is a period from the device reset to the reading out of the interrupt request register  412 . 
         [0049]    If error E 1  occurs during transfer of dummy data for maintaining the link, the device driver  23  (the recovery processing unit  23   b ) executes performs recovery processing from the error E 1 . The “recovering processing” includes performing of the device reset and setting of the unconditional interrupt. 
         [0050]    The device driver  23  executes the interrupt processing from occurrence of an error interrupt caused by the error E 1  to the completion of the recovery processing from the error E 1 . The device driver  23  performs the interrupt processing by accessing the interrupt request register  412  determining and the interrupt request set in the interrupt request register  412 . Access to the interrupt request register  412  is made to wait until preceding interrupt processing (access) is completed. When the interrupt processing is completed, the device driver  23  performs the unconditional interrupt and performs next interrupt processing. 
         [0051]    If an error E 2  occurs within the predetermined period from the device reset (error monitoring period) to the reading out of the interrupt request register  412 , the device driver  23  executes the device reset again, executes the recovery processing from the error E 2 , and sets the unconditional interrupt. 
         [0052]    Further, if error E 3  occurs within the predetermined period from the device reset to the reading out of the interrupt request register  412 , the device driver  23  executes the device reset again, executes the recovery processing from the error E 3 , and sets the unconditional interrupt. 
         [0053]    If still another error does not occur within the predetermined period from the device reset to reading out of the interrupt request register  412 , the device driver terminals the error monitoring. 
         [0054]    Thus, if more than one error monitoring period in which an error occurs continues and the setup number (counted number) of the error monitoring periods exceeds a predetermined value, the device driver  23  notifies a fatal error. If the number of the successive error monitoring periods is equal to or less than the predetermined value, the device driver  23  determines that no fatal error occurs. 
       Second Exemplary Embodiment 
       [0055]      FIG. 8  is a block diagram of a computer system according to a second exemplary embodiment of the invention. The second exemplary embodiment differs from the first exemplary embodiment in that it is also provided with a cooling fan  47  installed in a semiconductor disk unit  4  for emitting heat in the unit  4  to the outside, a power unit  48  for supplying power to the components of the semiconductor disk unit  4 , and a monitor section  46  for monitoring the drive state of the cooling fan  47  and the power unit  48 . When the cooling fan  47  stops, when power supply from the power unit  48  stops, when the supplied voltage drops, etc., the monitor section  46  sends notification of the error occurring in the cooling fan  47  or the power unit  48  to an SSD controller  40  as an unrecoverable fatal error. 
         [0056]    As an anomaly in the semiconductor disk unit  4 , any other anomaly of a rise in the unit temperature, etc., may be monitored in addition to the anomalies of the cooling fan  47  and the power unit  48 . 
         [0057]    An interrupt request register  412  includes an error interrupt bit  412   a,  an unconditional interrupt bit  412   b,  a transfer completion interrupt bit  412   c,  a reserved bit  412   d,  a cooling fan error interrupt bit  412   e,  and a power error interrupt bit  412   f.    
       Operation of Second Exemplary Embodiment 
       [0058]      FIG. 10  is a flowchart to show the operation of a host computer  2 . When the monitor section  46  detects an anomaly in the cooling fan  47  or the power unit  48 , it sends notification of the anomaly to the SSD controller  40 . “1” is written into the cooling fan error interrupt bit  412   e  or the power error interrupt bit  412   f  of the interrupt request register  412 , and a device driver  23  is interrupted. 
         [0059]    When the device driver  23  reads the interrupt request register  412  (S 100 ) and checks that the interrupt is an interrupt of the home device (YES at S 110 ), the device driver  23  sets clear of the error interrupt for the SSD controller  40  (S 120 ). The SSD controller  40  clears the error interrupt bit  412   a  of the interrupt request register  412 . 
         [0060]    The device driver  23  determines whether or not the interrupt is an error interrupt (S 130 ) and if the interrupt is an error interrupt (YES at S 130 ), the device driver  23  determines whether or not the number of retries is equal to or less than a predetermined value (S 170 ) and if the number of retries is equal to or less than the predetermined value (YES at S 170 ), the device driver  23  executes device reset (S 190 ) As the reset device is executed, registers in a register group  410  are cleared. 
         [0061]    After device reset is executed, recovery processing from the error is performed. After waiting for a predetermined error recovery time, the device driver  23  determines whether or not data is being transferred at present (S 200 ). Since the recovery processing from the error contains power check and cooling fan check, longer recover time than that in the first exemplary embodiment is required. 
         [0062]    If data is not being transferred at present (NO at S 200 ), the device driver  23  sets an unconditional interrupt (S 230 ). The SSD controller  40  writes “1” into the unconditional interrupt bit  412   b  of the interrupt request register  412 . If data is being transferred at present (YES at S 200 ), the data is resent (S 210 ). 
         [0063]    If the interrupt is not an error interrupt (NO at S 130 ), whether or not the interrupt is a power error interrupt or a cooling fan error interrupt is determined (S 131 ). If the interrupt is not a power error interrupt or a cooling fan error interrupt (NO at S 131 ), whether or not the interrupt is a data transfer completion interrupt is determined (S 140 ). If the interrupt is a data transfer completion interrupt (YES at S 140 ), notification of disk read completion is sent to a file system  22 , which then sends notification of file read completion to an application program  20  (S 150 ), the number of retries is cleared (S 160 ), and the interrupt processing terminates. 
         [0064]    If the interrupt is a power error interrupt or a cooling fan error interrupt (YES at S 131 ), the device driver  23  sends notification of a fatal error (S 220 ) as in the first exemplary embodiment. 
       Other Embodiments 
       [0065]    It is to be understood that the invention is not limited to the above-described specific embodiments thereof and various modifications and changes may be made without departing from the spirit and the scope of the invention. 
         [0066]    In the exemplary embodiments described above, the error recovery processing is implemented as software, but the whole or a part of the error recovery processing may be implemented as hardware. 
         [0067]    In the exemplary embodiments described above, the error recovery processing performed when an error or an anomaly occurs in the semiconductor disk unit has been described, but the invention can also be applied in a similar manner if a transmission error occurs on the serial interface.