Abstract:
In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

Description:
RELATED APPLICATIONS 
       [0001]    This application is related to co-pending, commonly owned U.S. patent application Ser. No. 13/______, attorney docket NVID-PSC 120850, filed Jun. 4, 2013, entitled “Handshaking Sense Amplifier,” to Gotterba and Wang and to U.S. patent application Ser. No. 13/______, attorney docket NVID-PSC 120852, filed Jun. 4, 2013, entitled “Pipelined One Cycle Throughput for Single-Port 6T RAM,” to Wang and Gotterba. Both applications are hereby incorporated herein by reference in their entireties for all purposes. 
     
    
     FIELD OF INVENTION 
       [0002]    Embodiments of the present invention relate to the field of integrated circuit design and operation. More specifically, embodiments of the present invention relate to systems and methods for three state latches. 
       BACKGROUND 
       [0003]    The term “latch” conventionally is used to refer to or to describe an electronic circuit that has two stable states and may be used to store a value, e.g., a single bit of information. Latches may be used for a wide variety of circuit applications, including, for example, in finite state machines, as counters and for synchronizing signals. If more than two states, e.g., more than one bit of information, are required, it is common to combine two or more latches to represent the desired number of states. 
         [0004]    Unfortunately, such multiple-latch circuits suffer from several deleterious drawbacks. For example, a multiple-latch circuit generally requires additional circuitry surrounding the latches to “interpret” the combined state of the latches, and to control the state changes of the multiple latches. Such additional circuitry may slow down the operation of the multiple-latch circuit. In addition, a multiple-latch circuit is less deterministic than a single latch. For example, while any single latch may be in a known state, a multiple-latch circuit may be in a variety of transitory states. For example, one latch of a multiple-latch circuit may operate faster than another, completing a state transition prior to another latch changing state. Additionally, the state of one latch may depend on the state of another latch, and thus cannot change until the other latch has completed its transition. Further, the state-control logic surrounding the multiple latches requires a finite time to command, control and/or report a combined state of the multiple latches, further introducing times at which a state of a multiple-latch circuit is indeterminate. 
       SUMMARY OF THE INVENTION 
       [0005]    Therefore, what is needed are systems and methods for three state latches. What is additionally needed are systems and methods for three state latches that store more than two states in a single latch circuit. A further need is for systems and methods for three state latches that store more than two states in a single latch circuit in a deterministic manner. A still further need exists for systems and methods for three state latches that are compatible and complementary with existing systems and methods of integrated circuit design, manufacturing and test. Embodiments of the present invention provide these advantages. 
         [0006]    In accordance with a first embodiment of the present invention, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs. 
         [0007]    In accordance with another embodiment of the present invention, an electronic circuit includes n pairs of cascaded logical gates, wherein each of the n pairs of cascaded logical gates includes a first logical gate comprising n−1 first gate inputs and one first gate output, and a second logical gate comprising two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other pairs of cascaded gates. The value of n is greater than two. The pairs of cascaded gates may be rendered as a single OR-AND-Invert (OAI) gate. 
         [0008]    In accordance with a further embodiment of the present invention, an electronic circuit includes a single latch circuit. The single latch circuit includes a first OR-AND-Invert gate having an output coupled to an OR input of a second OAI gate and to an OR input of a third OAI gate. The second OR-AND-Invert gate has an output coupled to an OR input of the first OAI gate and to an OR input of the third OAI gate. The third OR-AND-Invert gate has an output coupled to an OR input of the first OAI gate and to an OR input of the second OAI gate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Unless otherwise noted, the drawings are not drawn to scale. 
           [0010]      FIG. 1A  illustrates an exemplary three state latch, in accordance with embodiments of the present invention. 
           [0011]      FIG. 1B  illustrates an exemplary truth table for a three state latch, in accordance with embodiments of the present invention. 
           [0012]      FIG. 1C  illustrates a logical equivalence between a combination of OR and NAND gates and an OAI gate. 
           [0013]      FIG. 2A  illustrates an exemplary four state latch, in accordance with embodiments of the present invention. 
           [0014]      FIG. 2B  illustrates an exemplary truth table for a four state latch, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it is understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be recognized by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention. 
       Three State Latch 
       [0016]    It is to be appreciated that the term “three state” as used herein does not refer to, and is not analogous to the term “Tri-State®,” a registered trademark of Texas Instruments, Inc., of Dallas, Tex. As is known to those of skill in the art, a Tri-State® device includes conventional “high” and “low” outputs, as well as a high impedance, or “hi-Z,” output state. Embodiments in accordance with the present invention store three (or more) states in a single latch. 
         [0017]      FIG. 1A  illustrates an exemplary three state latch  100 , in accordance with embodiments of the present invention. Three state latch  100  comprises three inputs,  131  A,  132  B and  133  C, and three outputs,  121  X,  122  Y and  123  Z. Three state latch  100  comprises three two-input NAND gates  101 ,  102  and  103 , and three two-input OR gates,  111 ,  112  and  113 . 
         [0018]      FIG. 1B  illustrates an exemplary truth table  150  for three state latch  100  of  FIG. 1A , in accordance with embodiments of the present invention. Setting input  131  A,  132  B or  133  C to zero forces the corresponding output  121  X,  122  Y or  123  Z to one. For example, setting input  133  C to zero forces output  123  Z to one. Similarly, setting an input to one forces the corresponding output to zero if any other input is zero. 
         [0019]    If all inputs  131  A,  132  B and  133  C are set to one, then the output of latch  100  will retain the state it had last, as indicated by the last row of truth table  150 . The “star” notation, e.g., “X*,” indicates previous state of the output signal line. For example, if inputs  131  A and  132  B are set to one, and input  133  C is set to zero, outputs  121  X and  122  Y will be zero, and output  123  Z will be set to one. Changing input  133  C from zero to one will result in all inputs set to one, and the outputs will retain their previous state. In this example, outputs  121  X and  122  Y will be zero, and output  123  Z will be set to one. In accordance with embodiments of the present invention, which ever input is the last to transition from zero to one will have its output remain one. 
         [0020]    It is appreciated that embodiments in accordance with the present invention offer several advantages in comparison to a three state circuit based on multiple conventional, e.g., two-state, latches. For example, there are no transitory states. In addition, embodiments in accordance with the present invention may operate asynchronously, e.g., with unclocked handshaking signals. Further, further, embodiments in accordance with the present invention generally require fewer gates, less die area and are thus less expensive in comparison to the conventional art. Still further, embodiments in accordance with the present invention will generally operate faster, e.g., with fewer gate delays, than under the conventional art. For example, in accordance with embodiments of the present invention, the worst case delay from input to output is two gate delays. 
         [0021]    It is appreciated that three state latch  100  ( FIG. 1 ) may be constructed from instances of an “OR-AND-INVERT” (“OAI”) gate structure, which is logically (but not physically) equivalent to the illustrated pairs of cascaded gates. For example, symbolic gates  111  and  101  together represent an OR gate  111 , followed by an AND gate followed by inversion, e.g., NAND gate  101 . In accordance with embodiments of the present invention, a three state latch may be formed from an “AND-OR-INVERT” (“AOI”) gate structure, with inversion of the truth table. Such embodiments are considered within the scope of the present invention. 
         [0022]    Latch  100  of  FIG. 1A  is presented schematically as a logical combination of OR and NAND gates. Each pair of OR and NAND gates may be rendered as a single OR-AND-Invert (OAI) gate with an equivalent logical function.  FIG. 1C  illustrates a logical equivalence between a combination of OR and NAND gates  198 , e.g., as illustrated in  FIG. 1A , and an OAI gate  199 . While logically equivalent, e.g., gates  198  and gate  199  have the same truth table, it is appreciated that there are physical differences between two separate, cascaded gates as illustrated in  198  and a single OAI gate  199 . For example, OAI gate  199  will generally comprise fewer transistors, less die area, and operate faster and at less power consumption, in comparison to the  198  structure. For example, OAI gate  199  produces an output in a single gate delay, whereas gates  198  may generally be expected to require two gate delays to propagate a signal. 
         [0023]    Accordingly, embodiments in accordance with the present invention may utilize an OAI gate structure, e.g., OAI gate  199 , or an AOI gate structure. However, the schematic representations presented herein illustrate the logical function of the separate gates. For example, all inputs of OAI gate  199  do not have the same logical function, and hence schematics utilizing the logical function of the separate gates represent a preferred approach to illustrate aspects of the present invention. With reference to  FIG. 1C , inputs A and B are referred to as OR inputs of the OAI gate  199 , and its schematic equivalent  198 . Input C is referred to as a NAND input. 
         [0024]    In addition, in accordance with embodiments of the present invention, latches with an arbitrary number of inputs may be formed by “widening” the first part of the gate, e.g., the OR gate in the exemplary OAI gate structure. For example, to form a four-input latch, the OR gates of  FIG. 1A  should be changed to be three input gates. 
         [0025]      FIG. 2A  illustrates an exemplary four state latch  200 , in accordance with embodiments of the present invention. Four state latch  200  comprises four inputs,  231  A,  232  B,  233  C and  234  D, and four outputs,  221  X,  222  Y,  223  Z and  224  W. Four state latch  200  comprises four two-input NAND gates  201 ,  202 ,  203  and  204 , and four three-input OR gates,  211 ,  212 ,  213  and  214 . 
         [0026]      FIG. 2B  illustrates an exemplary truth table  250  for four state latch  200  of  FIG. 2A , in accordance with embodiments of the present invention. Setting input  231  A,  232  B,  233  C or  234  D to zero forces the corresponding output  221  X,  222  Y,  223  Z or  224  W to one. For example, setting input  233  C to zero forces output  223  Z to one. 
         [0027]    If all inputs  231  A,  232  B,  233  C and  234  D are set to one, then the output of latch  200  will retain the state it had last, as indicated by the last row of truth table  250 . The “star” notation, e.g., “X*,” indicates previous state of the output signal line. For example, if inputs  231  A,  232  B, and  233  C are set to one, and input  234  D is set to zero, outputs  221  X,  222  Y and  223  Z will be zero, and output  224  W will be set to one. Changing input  234  D from zero to one will result in all inputs set to one, and the outputs will retain their previous state. In this example, outputs  221  X,  222  Y and  223  Z will be zero, and output  224  W will be set to one. In accordance with embodiments of the present invention, which ever input is the last to transition from zero to one will have its output remain one. 
         [0028]    As illustrated in three state latch  100  of  FIG. 1A  and four state latch  200  of  FIG. 2A , all outputs are cross coupled to logic accepting the other inputs. For example, with respect to four state latch  200  of  FIG. 2A , output  221  X is coupled to OR gate  212 , a part of the logic accepting input  232  B, is coupled to OR gate  213 , a part of the logic accepting input  233  C, and is coupled to OR gate  214 , a part of the logic accepting input  234  D. Accordingly, the first gate of each stage should have inputs for the number of states (stages) minus one. 
         [0029]    Embodiments in accordance with the present invention provide systems and methods for three state latches. In addition, embodiments in accordance with the present invention provide systems and methods for three state latches that store more than two states in a single latch circuit. Further, embodiments in accordance with the present invention provide systems and methods for three state latches that store more than two states in a single latch circuit in a deterministic manner. Still further, embodiments in accordance with the present invention provide systems and methods for three state latches that store more than two states in a single latch circuit that are compatible and complementary with existing systems and methods of integrated circuit design, manufacturing and test. 
         [0030]    Various embodiments of the invention are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the invention should not be construed as limited by such embodiments, but rather construed according to the below claims.