Abstract:
The present invention provides a method and apparatus for detecting a continuous current of a switching current. A current signal is produced in response to a switching current of the magnetic device. By sampling the waveform of the current signal in response to the enabling of a switching signal, a first current signal and a second current signal are generated. A continuous current signal is produced according to the first current signal and the second current signal. The continuous current signal is corrected to the continuous current of the switching current.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to switching control circuit, and more particularly, to a switching control circuit of a magnetic device. 
         [0003]    2. Description of Related Art 
         [0004]    Switching control circuits have been widely used in power conversion.  FIG. 1  shows a power converter including a controller  50  for generating a switching signal S W  to regulate the output of the power converter in response to a feedback signal V FB . The switching signal S W  drives a power transistor  20  for switching a transformer  10 . The transformer  10  is connected to an input voltage V IN  of the power converter. The energy of the transformer  10  is transferred to the output voltage V O  of the power converter through a rectifier  40  and a capacitor  45 . A resistor R S  is connected in series with the power transistor  20  to generate a current signal V I  in response to a switching current I P  of the transformer  10 . The current signal V I  is coupled to the controller  50  to control the power converter. The power converter may be operated in a discontinuous current mode (DCM) when the magnetic device such as the transformer  10  is fully discharged before the start of the switching cycle. If the switching signal S W  is enabled before the transformer  10  is fully discharged, the power converter may be operated in a continuous current mode (CCM). A continuous current may be retained in the transformer when the power converter operated in the CCM.  FIG. 2  shows a CCM waveform of the switching current I P , in which the continuous current I A  represents the energy stored in the transformer  10 . A current I B  is the energy that is further charged into the transformer  10  during the on time TON of this switching cycle. The continuous current I A  stands for a major energy transfer of the transformer  10 . The object of the present invention is to develop a method and apparatus to measure the continuous current I A  of the switching current I P . 
       SUMMARY OF THE INVENTION 
       [0005]    The present invention provides a method and apparatus for detecting a continuous current of a switching current. A switching control circuit generates a switching signal to switch a magnetic device. The switching signal includes a minimum on time. A current sense circuit is coupled to generate a current signal in response to a switching current of the magnetic device. A signal generation circuit is developed to generate a first sample signal and a second sample signal in response to the enabling of the switching signal. A detection circuit is coupled to the current signal to generate a first current signal and a second current signal in response to the first sample signal and the second sample signal respectively. A continuous current signal is produced in the detection circuit according to the first current signal and the second current signal. The continuous current signal is corrected to the continuous current of the switching current. The level of the continuous current signal is equal to the first current signal minus the differential of the first current signal and the second current signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The accompanying drawings are included to provide further understanding of the invention, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
           [0007]      FIG. 1  shows a circuit diagram of a power converter. 
           [0008]      FIG. 2  shows switching current waveform operated in a continuous current mode. 
           [0009]      FIG. 3  is a view of a controller according to an embodiment of the present invention. 
           [0010]      FIG. 4  is a view of a signal generation circuit according to an embodiment of the present invention. 
           [0011]      FIG. 5  is a circuit diagram of a pulse generator. 
           [0012]      FIG. 6  is a view of a detection circuit according to an embodiment of the present invention. 
           [0013]      FIG. 7  shows signal waveforms of the controller according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0014]      FIG. 3  shows the circuit of the controller  50 , which includes a switching circuit  60  for generating the switching signal S W  in response to a signal I PS . An oscillation circuit  55  is developed to generate an oscillation signal PLS. The oscillation signal PLS is connected to an inverter  58  to generate the signal I PS . The switching circuit  60  includes a flip-flop  70 , an NAND gate  67 , an AND gate  75  and a comparator  65 . The flip-flop  70  is utilized to generate the switching signal S W  through the AND gate  75 . The input of the AND gate  75  is connected to the output of the flip-flop  70 . Another input of the AND gate  75  is connected to the signal I PS  to limit the maximum on time of the switching signal S W . The flip-flop  70  is enabled in response to the signal I PS . The switching signal S W  is coupled to a signal generation circuit  100  to generate a blanking signal BLK and sample signals S 1  and S 2  in response to the switching signal S W . The blanking signal BLK ensures a minimum on time of the switching signal S W  when the switching signal S W  is enabled. The blanking signal BLK is connected to the input of the NAND gate  67 . The output of the NAND gate  67  is coupled to reset the flip-flop  70 . Another input of the NAND gate  67  is connected to the output of the comparator  65 . The positive input of the comparator  65  is coupled to receive the current signal V I . The negative input of the comparator  65  is coupled to receive the feedback signal V FB  for the feedback loop control. Furthermore, a detection circuit  200  is coupled to receive the current signal V I , the oscillation signal PLS, and sample signals S 1  and S 2  to generate a continuous current signal S A . 
         [0015]      FIG. 4  shows the signal generation circuit  100 . The switching signal S W  is coupled to the input of pulse generators  110 ,  120  and  130 . The pulse generator  110  generates the blanking signal BLK through an inverter  115 . Pulse generators  120  and  130  generate the sample signals S 1  and S 2  respectively. The blanking signal BLK and sample signals S 1 , S 2  are thus generated in response to the enabling of the switching signal S W . The sample signal S 1  is a pulse signal with a first period T 1 . The sample signal S 2  is a pulse signal with a second period T 2 . The pulse width of the blanking signal BLK is longer than the pulse width of the sample signal S 2 . The pulse width of the sample signal S 2  is longer than the pulse width of the sample signal S 1 . 
         [0016]      FIG. 5  shows the circuit of pulse generators. A constant current-source  320 , a transistor  310 , a capacitor  315 , an inverter  324 , and an NOR gate  235  develop the pulse generator to generate an output pulse signal OUT in response to the rising edge of an input signal IN. The current of the constant current-source  320  and the capacitance of the capacitor  315  determine the pulse width of the output pulse signal OUT. 
         [0017]      FIG. 6  is a view of the detection circuit  200  according to an embodiment of the present invention. A capacitor  215  is coupled to receive the current signal V I  though a switch  210 . A capacitor  225  is coupled to receive the current signal V I  though a switch  220 . The switch  220  is controlled by the sample signal S 1 . The switch  210  is controlled by the sample signal S 2 . The capacitor  225  is therefore coupled to sample-and-hold the current signal V I  to generate a signal V 1  during the first period T 1  after the enabling of the switching signal S W . The capacitor  215  is coupled to sample-and-hold the current signal V I  to generate a signal V 2  during the second period T 2  after the enabling of the switching signal S W . An operational amplifier  230 , a transistor  232  and a resistor  231  form a voltage-to-current converter to generate a current I 232  according to the signal V 2 . Transistors  234  and  235  develop a first current mirror to generate a current signal I 2  according to the current I 232 . 
         [0018]    An operational amplifier  240 , a transistor  242  and a resistor  241  form another voltage-to-current converter to generate a current I 242  according to the signal V 1 . Transistors  244 ,  245  and  246  develop a second current mirror to generate a current signal I 1  and a current I 245  according to the current I 242 . Transistors  260  and  261  form a third current mirror to receive the current I 245  and generate a current I 261 . The magnitude of the current I 261  is designed same as the magnitude of the current signal I 1 . The transistor  261  is further coupled to receive the current signal I 2  to generate a delta signal according to the differential of the first current signal I 1  and the second current signal I 2  Transistors  262  and  263  develop a fourth current mirror to receive the delta signal and generate a current I 263 . The transistor I 263  is further coupled to receive the current signal I 1 . The current signal I 1  and the current I 263  produce a differential signal coupled to a resistor  251  to generate a voltage signal V 251 . A capacitor  275  is coupled to sample the voltage signal V 251  through a switch  270  to generate the continuous current signal S A . The switch  270  is controlled by a sample signal S P . The oscillation signal PLS produces the sample signal S P  through a pulse generator  300 . 
         [0019]    The continuous current signal S A  is therefore generated according to the first current signal I 1  and the second current signal I 2 , in which the continuous current signal S A  is corrected to the continuous current of the switching current I P . The continuous current signal S A  is equal to the first current signal I 1  minus the differential of the first current signal I 1  and the second current signal I 2 . It can be shown as, 
         [0000]    
       
         
           
             
               
                 
                   
                     S 
                     A 
                   
                   = 
                   
                     
                       [ 
                       
                         
                           I 
                           1 
                         
                         - 
                         
                           ( 
                           
                             
                               I 
                               2 
                             
                             - 
                             
                               I 
                               1 
                             
                           
                           ) 
                         
                       
                       ] 
                     
                     × 
                     
                       R 
                       251 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     S 
                     A 
                   
                   = 
                   
                     
                       [ 
                       
                         
                           
                             V 
                             1 
                           
                           
                             R 
                             241 
                           
                         
                         - 
                         
                           ( 
                           
                             
                               
                                 V 
                                 2 
                               
                               
                                 R 
                                 231 
                               
                             
                             - 
                             
                               
                                 V 
                                 1 
                               
                               
                                 R 
                                 241 
                               
                             
                           
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                       ] 
                     
                     × 
                     
                       R 
                       251 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   
                     S 
                     A 
                   
                   = 
                   
                     k 
                     × 
                     
                       [ 
                       
                         
                           V 
                           1 
                         
                         - 
                         
                           ( 
                           
                             
                               V 
                               2 
                             
                             - 
                             
                               V 
                               1 
                             
                           
                           ) 
                         
                       
                       ] 
                     
                   
                 
               
               
                 
                   ( 
                   3 
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         [0020]    wherein R 231 , R 241  and R 251  are the resistance of resistors  231 ,  241  and  251  respectively and k is a constant. 
         [0021]      FIG. 7  shows signal waveforms. The signal generation circuit  100  generates sample signals S 1  and S 2  in response to the switching signal S W . The sample signal S 1  includes the first period T 1 . The sample signal S 2  has the second period T 2 . The detection circuit  200  samples the current signal V I  during the first period T 1  to generate the signal V 1 . Sampling the current signal V I  during the second period T 2  generates the signal V 2 . The continuous current signal S A  is determined according to the signal V 1  and V 2 . 
         [0022]    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.