Abstract:
A reference voltage generator circuit for generating a reference voltage and outputting the voltage from an output terminal comprises a constant current source circuit having a current mirror circuit, for outputting a reference voltage; and first and second current-voltage converter circuits connected in parallel to an output of the constant current source circuit, wherein the second current-voltage generator circuit outputs a reference voltage lower than a bandgap voltage.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of Invention  
         [0002]     The present invention relates to reference voltage generator circuits and, particularly, to a reference voltage generator circuit with less power voltage dependency and temperature dependency.  
         [0003]     2. Description of Related Art  
         [0004]     A bandgap reference voltage generator circuit is known as a reference voltage generator circuit with less power voltage dependency and temperature dependency. In the bandgap reference voltage generator circuit, an output reference voltage is fixed to about 1.25V, which is a bandgap voltage. Recently, low-voltage semiconductor devices have been developed. Conventional bandgap reference voltage generator circuits are incapable of generating a reference voltage of less than 1.25V.  
         [0005]     Japanese Unexamined Patent Application Publication No. 11-045125 proposes a low-level reference voltage generator circuit. It introduces an improved structure of the bandgap reference voltage generator circuit.  FIG. 8  shows a basic structure of the reference voltage generator circuit according to this conventional art, and  FIG. 9  shows a circuit diagram. In this circuit, an output current from a first current source circuit  11  and an output current from a second current source circuit  12  are added together in a current adder circuit  13 . A current-voltage converter circuit  14  converts the sum of the currents into a voltage, thereby creating a reference voltage Vref.  
         [0006]     As shown in  FIG. 9 , the first power source circuit  11  includes a first current path and a second current path between a power voltage VDD and a ground potential Vss, and a first differential amplifier  11 . The first current path has a PMOS transistor P 11  and a diode D 11 . The source of the PMOS transistor P 11  is connected to the power voltage VDD and the drain is connected to the anode of the diode D 11 . The cathode of the diode D 11  is connected to the ground potential. The second current path has a PMOS transistor P 12 , a resistor R 11 , and a diode D 12 . The source of the PMOS transistor P 12  is connected to the power voltage VDD and the drain is connected to one end of the resistor R 11 . The other end of the resistor R 11  is connected to the anode of the diode D 12 . The cathode of the diode D 12  is connected to the ground potential. The inverting input terminal of the first differential amplifier Amp 11  is connected to the drain of the PMOS transistor P 11 , and the non-inverting input terminal of the first differential amplifier Amp 11  is connected to the drain of the PMOS transistor P 12 . Output from the first differential amplifier Amp 11  is supplied to the gates of the PMOS transistors P 11  and P 12 .  
         [0007]     The second current source circuit  12  includes a third current path and a second differential amplifier Amp 12 . The third current path has a PMOS transistor P 15  and a resistor R 12 . The source of the PMOS transistor P 15  is connected to the power voltage VDD and the drain is connected to one end of the resistor R 12 . The other end of the resistor R 12  is connected to the ground potential. The inverting input terminal of the second differential amplifier Amp 12  is connected to the drain of the PMOS transistor P 11 , and the non-inverting input terminal of the second differential amplifier Amp 12  is connected to the drain of the PMOS transistor P 15 . Output from the second differential amplifier Amp 12  is supplied to the gate of the PMOS transistor P 15 .  
         [0008]     The current adder circuit  13  has a PMOS transistor P 13  and a PMOS transistor P 14 . The source of the PMOS transistor P 13  is connected to the power voltage VDD, the gate is connected to the output of the first differential amplifier Amp 11 , and the drain is connected to a reference voltage output terminal  15 . The source of the PMOS transistor P 14  is connected to the power voltage VDD, the gate is connected to the output of the second differential amplifier Amp 12 , and the drain is connected to the reference voltage output terminal  15 . The current-voltage converter circuit  14  has a resistor R 13 . One end of the resistor R 13  is connected to the reference voltage output terminal  15  and the other end is connected to the ground potential Vss.  
         [0009]     The PMOS transistors P 11 , P 12 , and P 13  constitute a current mirror circuit. The current I 01  flowing through each of these PMOS transistors is thus equal. Further, the PMOS transistors P 14  and P 15  constitute a current mirror circuit. The current I 02  flowing through each of these transistors is thus equal.  
         [0010]     The current flowing through the resistor R 13  of the current-voltage converter circuit  14  is equal to the sum of the currents I 01  and I 02 . The current I 01  is the current through the PMOS transistor P 13  and I 02  is the current through the PMOS transistor P 14 .  
         [0011]     The reference current I 01  of the first current source is given by: 
 
I 01 =(R 11 ) −1 (kT/q)1 nM   (1) 
 
         [0012]     The reference current I 02  of the second current source is given by: 
 
I 02 =Vf(R 12 ) −1    (2) 
 
 where the PMOS transistors P 11 , P 12 , P 13 , P 14 , and P 15  have the same size (W/L ratio) and designed to have the same operating characteristics, the diode D 12  is composed of the M-number of diodes D 11  connected in parallel, and a forward voltage of the diode D 11  is Vf. 
 
         [0014]     The output reference voltage Vref is given by: 
 
Vref=R 13 (I 01 +I 02 )   (3) 
 
         [0015]     Substitution of Eq.(1) and (2) into Eq.(3) yields: 
 
Vref=(R 13 /R 12 ){(R 12 /R 11 )(kT/q)1 nM+Vf}  (4) 
 
         [0016]     Since Eq. (4) has no term of power voltage VDD, there is no power voltage dependency. Further, since (kT/q) has positive temperature dependency and Vf has negative temperature dependency, the temperature dependency can be eliminated by appropriately setting the ratio of resistances. The circuit shown in  FIG. 9  generates a low level of reference voltage based on Eq.(4).  
         [0017]     The circuit shown in  FIG. 9  has two differential amplifiers and two power source circuits. The number of elements is thereby large to undesirably increase a circuit area and current consumption.  
       SUMMARY OF THE INVENTION  
       [0018]     The present invention has been accomplished to solve the above problems. To this end, according to one aspect of the present invention, there is provided a reference voltage generator circuit for generating a reference voltage and outputting the voltage from an output terminal comprising a constant current source circuit having a current mirror circuit for outputting a reference voltage and first and second current-voltage converter circuits connected in parallel to an output of the constant current source circuit, wherein the second current-voltage generator circuit outputs a reference voltage lower than a bandgap voltage.  
         [0019]     The above and other objects, features and advantages of the present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]      FIG. 1  is a block diagram showing the structure of a reference voltage generator circuit according to the present invention;  
         [0021]      FIG. 2  is a circuit diagram showing a reference voltage generator circuit according to a first embodiment of the invention;  
         [0022]      FIG. 3  is a graph showing a simulation result of the first embodiment;  
         [0023]      FIG. 4  is a circuit diagram of a reference voltage generator circuit according to a second embodiment of the invention;  
         [0024]      FIG. 5  is a graph showing a simulation result of the second embodiment;  
         [0025]      FIG. 6  is a circuit diagram of a reference voltage generator circuit according to a third embodiment of the invention;  
         [0026]      FIG. 7  is a graph showing a simulation result of the third embodiment;  
         [0027]      FIG. 8  is a block diagram showing the structure of a reference voltage generator circuit according to a conventional art; and  
         [0028]      FIG. 9  is a circuit diagram showing a reference voltage generator circuit according to the conventional art. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]      FIG. 1  is a block diagram showing a reference voltage generator circuit according to the present invention. The reference voltage generator circuit of the present invention has a constant current source circuit  1 , a first current-voltage converter circuit  2 , and a second current-voltage converter circuit  3 . A reference voltage generator circuit can generate a voltage lower than a bandgap voltage if it has first and second current-voltage converter circuits.  
         [0030]      FIG. 2  is a circuit diagram showing a reference voltage generator circuit according to a first embodiment of the invention.  FIG. 3  is a graph showing a Simulation Program with Integrated Circuit Emphasis (SPICE) simulation result of the circuit of  FIG. 2 . The first embodiment will be explained hereinafter with reference to  FIG. 2 .  
         [0031]     The reference voltage generator circuit of the first embodiment has the constant current source circuit  1 , the first current-voltage converter circuit  2 , and the second current-voltage converter circuit  3 . The constant current source circuit  1  is composed of current mirror circuits. The first and second current-voltage converter circuits  2  and  3  divide the current outputted from the constant current source circuit  1  and convert each of the divided currents into a voltage.  
         [0032]     The constant current source circuit  1  has NMOS transistors M 1 , M 2 , and PMOS transistors M 3 , M 4 , M 5 , and a resistor R 1 . The sources of the PMOS transistors M 3 , M 4 , M 5  are each connected to a power voltage VDD, and the gates of those are each connected to the drain of the PMOS transistors M 4 . The drain and gate of the NMOS transistor M 1  are connected to the drain of the PMOS transistor M 3 , and the source is connected to a ground potential. The drain of the NMOS transistor M 2  is connected to the drain of the PMOS transistor M 4 , the gate is connected to the gate of the NMOS transistor M 1 , and the source is connected to one end of the resistor R 1 . The other end of the resistor R 1  is connected to the ground potential Vss. Each pair of the PMOS transistors M 3  and M 4 , M 4  and M 5 , and the NMOS transistors M 1  and M 2  constitutes a current mirror circuit. A current I ∘  flowing through each of the transistors is thereby equal.  
         [0033]     The first current-voltage converter circuit  2  has a resistor R 2  and a diode D 1 . One end of the resistor R 2  is connected to the drain of the PMOS transistor M 5 , and the other end is connected to the anode of the diode D 1 . The cathode of the diode D 1  is connected to the ground potential. A current αI ∘  flows through the first current-voltage converter circuit  2 . The current αI ∘  is a current divided from a constant current I ∘ . The constant current I ∘  is a current flowing through the PMOS transistor M 5  of the constant current generator circuit  1 .  
         [0034]     The second current-voltage converter circuit  3  has a resistor R 3 . One end of the resistor R 3  is connected to the drain of the PMOS transistor M 5  and the other end is connected to the ground potential Vss. A current (1−α) I ∘  flows through the second current-voltage converter circuit  2 . The current (1−α) I ∘  is the rest of the current divided from the constant current I ∘ . A connection node between the drain of the PMOS transistor M 5  of the constant current source current  1 , and the first and second current-voltage converter circuits  2  and  3  is an output terminal  5  of a reference voltage Vref. The reference voltage Vref is outputted from the output terminal  5 .  
         [0035]     The PMOS transistors M 3 , M 4 , and M 5  have the same characteristics and the same size (W/L ratio: L is a gate channel length and W is a gate width). The NMOS transistor M 2  is composed of the N-number of NMOS transistors M 1  connected in parallel. The NMOS transistor M 2  thus operates in a subthreshold region.  
         [0036]     If a constant current through each transistor is I ∘ , a current through the first current-voltage converter circuit  2  is αI ∘ , a current through the second current-voltage converter circuit  3  is (1−α) I ∘ , and a forward direction voltage of the diode D 1  is VF, the constant current I ∘  is given by: 
 
I ∘ =(R 1 ) −1 (kT/q)1 nN   (5) 
 
 The reference voltage Vref is given by:  
             Vref   =       α   ⁢           ⁢     I   o     ⁢   R2     +   VF             (   6   )                       ⁢     =       (     1   -   α     )     ⁢     I   o     ⁢   R3               (   7   )             
 
 Rearrangement of Eq.(6) and (7) gives: 
 
α=[I ∘ R 3 −VF]/[I ∘ (R 2 +R 3 )]  (8) 
 
 Substitution of Eq.(8) into Eq.(6) yields: 
 
Vref=R 3 (R 2 +R 3 ) −1 {(R 2 /R 1 )(kT/q)1 nN+VF}  (9) 
 
 Differentiation of Eq. (9) with respect to temperature T yields: 
 
ΔVref/ΔT=R 3 (R 2 +R 3 ) −1 {(R 2 /R 1 )(kT/q)1 nN+ΔVF/ΔT}  (10) 
 
         [0041]     Since Eq. (9) indicating a reference voltage has no term of power voltage VDD, it has no power voltage dependency. Further, a given low level of reference voltage can be obtained by appropriately setting a resistance value. In Eq.(10), the temperature characteristics of VF have negative temperature dependency, which is about −2 mV/° C. Thus, setting an appropriate ratio of the resistors R 1  and R 2  allows eliminating the temperature dependency.  
         [0042]     The first embodiment is now explained with specific numerical values.  
         [0043]     Setting values in this embodiment are as follows: The ratio of the resistors are: R 1 , R 2 =12R 1 , R 3 =1.7R 1 , The ratio N of the transistors M 1  and M 2  is: N=11, The forward voltage and temperature characteristics of the diode D 1  are: 
 
VF=0.53(V), ΔVF/ΔT=−2.48(mV/° C.), kT/q=26(mV). 
 
         [0044]     Substitution of the above setting values into Eq.(9) and (10) gives: 
 
Vref=0.8V, ΔVref/ΔT=0. 
 
         [0045]      FIG. 3  shows a SPICE simulation result for confirmation of the above. The simulation is conducted under the following conditions:  
         [heading-0046]     Threshold variation of each transistor: ±25%  
         [heading-0047]     Temperature: −40° C., 25° C., 120° C.  
         [heading-0048]     A reference voltage Vref with respect to a power voltage under the above conditions is calculated. As indicated in  FIG. 3 , the reference voltage Vref=0.8V and ΔVref/ΔT=0 when the power voltage is 0.9V and above.  
         [0049]     In the first embodiment, the first and second current-voltage converter circuits  2  and  3  are connected in parallel to the drain of the PMOS transistor M 5  of the constant current circuit  1 . The constant current circuit  1  has current mirror circuits and outputs a constant current. The outputted constant current is divided into two currents to be inputted into the first and second current-voltage converter circuits  2  and  3 . The currents flowing through the first and second current-voltage converter circuits  2  and  3  are each converted into a voltage, thereby obtaining a reference voltage of a lower level than a bandgap voltage.  
         [0050]     A second embodiment of the present invention is explained hereinafter with reference to  FIGS. 4 and 5 .  FIG. 4  shows a circuit diagram of the second embodiment, and  FIG. 5  shows a SPICE simulation result of the circuit. The second embodiment allows obtaining a reference voltage that is still lower than the voltage obtained in the first embodiment. The circuit of the second embodiment shown in  FIG. 4  is different from the circuit of the first embodiment in the second current-voltage converter circuit. In the second embodiment, the resistor R 3  of the second current-voltage converter circuit shown in  FIG. 2  is divided into two resistors. Thus, the second current-voltage converter circuit  4  has resistors R 31  and R 32  connected in series. The output terminal  5  of the reference voltage Vref is a connection node between the resistors R 31  and R 32 . The other elements in  FIG. 4  are the same as those in  FIG. 2 . The same elements are denoted by the same reference symbols and redundant description is omitted.  
         [0051]     Following from Eq.(9), a reference voltage Vref obtained in the circuit structure shown in  FIG. 4  is given by: 
 
Vref=R 32 (R 2 +R 31 +R 32 ) −1 {(R 2 /R 1 )(kT/q)1 nN+VF}  (10) 
 
 Substitution of R 32 =(5/3)R 31  into Eq.(10) yields: Vref=0.5V 
 
         [0053]      FIG. 5  shows a SPICE simulation result of the second embodiment for confirmation. The conditions of the simulation are the same as those in the first embodiment. As indicated in  FIG. 5 , the reference voltage is Vref=0.5V and ΔVref/ΔT=0 when the power voltage is 0.9V and above. The value of Vref=0.5V is lower than the reference voltage Vref in the first embodiment.  
         [0054]     The second embodiment divides the resistor of the second current-voltage converter circuit. By setting the connection between the divided resistors as the reference voltage output terminal, it is possible to obtain a still lower reference voltage than the reference voltage obtained in the first embodiment.  
         [0055]      FIG. 6  is a circuit diagram showing a third embodiment of the invention.  FIG. 7  is a graph showing the time to generate a reference voltage. The first and second embodiments require several msec to generate a reference voltage after power-on. The third embodiment allows reducing the elapsed time to generate a reference voltage.  
         [0056]     The circuit of the third embodiment has a startup circuit  6  in addition to the circuit shown in  FIG. 4 . The other elements in  FIG. 6  are the same as those in  FIG. 4 , and the same elements are denoted by the same reference symbols and redundant description is omitted.  
         [0057]     The startup circuit  6  has a NMOS transistor M 6  and PMOS transistors M 7  and M 8 . The gate of the NMOS transistor M 6  receives a reference voltage as a control signal, and the source is connected to a ground potential Vss. The source of the PMOS transistor M 7  is connected to a power voltage VDD, the gate is connected to the drain of the NMOS transistor M 6 , and the drain is connected to the drain of the NMOS transistor M 1  in the constant current source circuit  1 . The source of the PMOS transistor M 8  is connected to the power voltage VDD, the gate is connected to the gate of the PMOS transistor M 4  in the constant current source circuit  1 , and the drain is connected to the drain of the NMOS transistor M 6 .  
         [0058]     Normally, in reference voltage generator circuits, a constant current starts flowing after power is turned on. Hence, reference voltage generator circuits have a transistor with low current supply capacity. The transistors M 1  to M 5  shown in  FIG. 6  also have low current supply capacity. Thus, it takes several msec to generate a reference voltage after power is on. The current supply capacity of each transistor of the startup circuit  6  in the third embodiment is set as follows. The PMOS transistor M 7  has high current supply capacity for high-speed operation. The PMOS transistor M 8  has low current supply capacity. The NMOS transistor M 6  has very low current supply capacity. The size of each transistor is determined according to target current supply capacity.  
         [0059]     The operation of the startup circuit  6  is explained below. At the time of power-on, all connection nodes of circuit elements are at ground potential. As the power voltage increases, the connection nodes are charged by the transistors M 3 , M 4 , M 5 , M 7 , and M 8 , of which sources are connected to the power voltage. Since the transistors M 3 , M 4 , and M 5  in the constant current source circuit  1  have low current supply capacity, the charge speed is low. On the other hand, the gate of the PMOS transistor M 7  in the startup circuit  6  is connected to the ground potential via junction capacitance and overlap capacitance of the NMOS transistor M 6 . Since the PMOS transistor M 7  has high current supply capacity, the charge speed is high. As a result, the PMOS transistor M 7  drastically raises the gate voltage of the transistors M 1  and M 2  in the constant current source circuit  1 . In this way, the startup circuit  6  allows each connection node to quickly reach an operating voltage. This allows the reference voltage generator circuit to quickly enter stable operation.  
         [0060]     When a reference voltage is generated, it is supplied to the gate of the NMOS transistor M 6 . The reference voltage is smaller than a bandgap voltage. The NMOS transistor M 6  is set to have very low current supply capacity, and the voltage supplied to its gate is also small. Thus, very low current flows through the NMOS transistor M 6 . The drain voltage of the NMOS transistor M 6  thereby increases to turn off the PMOS transistor M 7 . With the PMOS transistor M 7  turned off, the startup circuit  6  ceases to affect the constant current source circuit  1 . Further, since the gate of the NMOS transistor M 6  receives a reference voltage that is lower than a bandgap voltage, it is not necessary to greatly reduce the W/L of the transistor, which allows reducing the layout area. Furthermore, since the current flowing through the NMOS transistor M 6  is very small, current consumption of the startup circuit  6  is negligible. By adding the startup circuit with a small layout area and low power consumption, it is possible to obtain a reference voltage generator circuit with a short risetime after power-on.  FIG. 7  shows the time to generate a reference voltage. The second embodiment with no startup circuit takes several msec to generate a reference voltage. The third embodiment with the startup circuit  6 , on the other hand, immediately generates a reference voltage.  
         [0061]     Though the third embodiment explains the case where the startup circuit is added to the second embodiment, the startup circuit may be added to the first embodiment.  
         [0062]     From the invention thus described, it will be obvious that the embodiments of the invention may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended for inclusion within the scope of the following claims.