Abstract:
A hot carrier lifetime of a MOS transistor is estimated depending on a hot carrier lifetime model expressed as t·∝I sub   −m ·I d   m−2  where t is a lifetime, I sub  is a substrate current, I d  is a drain current, and m is a fitting parameter. When hot carrier degradation of the MOS transistor is simulated, a parameter Age representing cumulative stress quantity with respect to the MOS transistor is calculated by a model formula expressed as Age ∝∫[I sub   m ·I d   2−m ]dt where t is time. As a result, a lifetime under a condition to cause maximum hot carrier degradation is estimated accurately, and a lifetime in actual use can be estimated accurately. Moreover, a hot carrier lifetime parameter can be calculated in a short time with small numbers of transistors.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method of estimating a lifetime concerning hot carrier degradation of a MOS transistor, more specifically, it relates to improvement of accuracy in lifetime estimation. The present invention relates to also a method of simulating circuit characteristic degradation caused by hot carrier degradation of a MOS transistor, more specifically, it relates to improvement of simulation accuracy.  
         BACKGROUND OF THE INVENTION  
         [0002]    The size of MOS transistors has been reduced considerably with a trend toward high density, high integration and miniaturization of semiconductor integrated circuit devices. With the miniaturization trend, especially due to the decreasing channel length, hot carrier degradation has been a critical problem, since the degradation will affect the reliability of a MOS transistor. Hot carrier degradation refers to a phenomenon that highly energized electrons and positive holes (hereinafter ‘hot carrier’) are generated by a high electric field at a drain end of a MOS transistor, which will degrade the characteristics of a gate oxide film. This hot carrier degradation includes plural degradation modes. When the degradation relates to a condition to cause a maximum substrate current, a drain current is decreased over time for any of N-type or P-type MOS transistor. As a result, the delay time of the circuit is increased over time. When the delay reaches a certain degree, a timing error occurs at a time of input/output of signals in the interior of the semiconductor integral circuit or between the circuit and outside, and this causes malfunction of an entire system in which the semiconductor integrated circuit is assembled.  
           [0003]    Regarding the hot carrier degradation, hot carrier reliability has been evaluated by a stress acceleration experiment under a DC condition with respect to the MOS transistor. And product reliability has been provided by optimizing a production process to satisfy the hot carrier evaluation standard.  
           [0004]    A hot carrier lifetime model used in such a hot carrier reliability evaluation is as follows. Hot carrier degradation of a MOS transistor is evaluated by, for example, ΔI d /I d , and this is a ratio of a drain current variation ΔI d  to an initial drain current I d . Under a static hot carrier stress condition by a DC (direct current), the hot carrier degradation rate ΔI d /I d  is represented by the following formula (1).  
             ΔI   d   /I   d   =A·t   n   (1) 
           [0005]    Here, t denotes a hot carrier stress time, while characters ‘A’ and ‘n’ are regarded as coefficients depending on a transistor manufacturing process and a stress condition.  
           [0006]    If a transistor lifetime τ is defined as a stress time required for a variation rate of drain current to reach (ΔI d /I d ) f , a formula (2) is obtained from the formula (1). For example, time t when (ΔI d /I d ) f =10% is defined as a lifetime τ.  
           (Δ I   d   /I   d ) f   =A·τ   n   (2) 
           [0007]    In a typical stress acceleration experiment for a MOS transistor, DC stress is applied to a transistor so that the transistor lifetime reaches a variation rate (ΔI d /I d ) f  defined by the formula (2) within a measureable time period, that is, from 1 second to about 100,000 seconds. Then, a drain current of the transistor is measured to calculate a transistor lifetime from ΔI d /I d  in a linear region or a saturation region.  
           [0008]    The following stress voltage application method is used in a stress acceleration experiment during a hot carrier reliability evaluation. Every gate voltage V g  is determined at a condition where the hot carrier degradation rate is maximized with respect to each of plural drain voltages V d  used for the acceleration experiment. In other words, each of the gate voltages V g  causes a maximum substrate current I sub  under a respective drain current. At this time, one gate voltage is set for each drain voltage. In this way, a transistor lifetime is calculated under a condition that the degradation rate is maximized with respect to an arbitrary drain voltage.  
           [0009]    A method of evaluating hot carrier reliability of a MOS transistor is described in IEEE Electron Device Lett., vol. 4, pp. 111-113, April 1983 by E. Tanaka et al. According to the description, the lifetime τ of a MOS transistor is calculated by using an empirical model represented by the following formula (3).  
           τ∝( I   sub   /W ) −m   (3) 
           [0010]    In this formula, W denotes a gate width and I sub  denotes a substrate current.  
           [0011]    [0011]FIG. 6 shows a method of estimating a lifetime based on this empirical model. In FIG. 6, each black dot  21  denotes a measured value of the lifetime, and a line  22  denotes a regression line of lifetime estimation. Numeral  23  denotes a maximum substrate current value for a unit gate width in actual use, and  24  denotes an estimated lifetime in actual use. For a lifetime estimation, a logarithm of I sub /W is used to enter a horizontal axis of a graph, and a logarithm of T is used to enter the vertical axis so that the measured values  21  for a lifetime are plotted. Next, the regression line  22  is fitted to the measured values  21  by using a least squares method. The maximum substrate current  23  for a unit gate width in actual use is also measured separately. The preliminary fitted regression line  22  is used to obtain a lifetime  24  corresponding to the maximum substrate current  23  in actual use, and this is determined as an estimated lifetime in actual use. Hot carrier reliability evaluation is executed by observing whether the lifetime  24  satisfies a hot carrier evaluation standard, e.g., whether the lifetime  24  satisfies a standard of at least 10 years.  
           [0012]    Recently however, such a conventional hot carrier evaluation standard has been difficult to satisfy in the hot carrier reliability evaluation under the DC condition. For solving this problem, a recently developed technique provides product reliability by a simulation of hot carrier degradation for a semiconductor integrated circuit (hereinafter “circuit reliability simulation”). A circuit reliability simulator simulates a circuit operation subsequent to hot carrier degradation by using a hot carrier lifetime model and a SPICE parameter after degradation, and the simulation is based on calculated values of voltage and current at every terminal of every transistor which are calculated by a circuit simulator SPICE. Typical simulators are BERT developed at the University of California, Berkeley (R. H. Tu et al., “Berkeley reliability tools-BERT,” IEEE Trans. Compt.-Aided Des. Integrated Circuits &amp; Syst., vol.12, no.10, pp.1524-1534, October 1993), and BTABERT (a commercial version of BERT). This circuit reliability simulation technique is used for estimating degraded or malfunctioning parts in a semiconductor integrated circuit and measures against the degradation or malfunction are taken during designing, so that reliability assurance or reliability design is possible.  
           [0013]    An example of simulation methods concerning hot carrier degradation of a MOS transistor is described in IEEE Trans. Electron Devices, vol.35, pp.1004-1011, July 1988 by Kuo et al. A hot carrier lifetime model applied to this circuit reliability simulator is as follows. According to Kuo et al., a lifetime τ of a MOS transistor is represented by an empirical formula (4) using a hot carrier lifetime model.  
           τ=((Δ I   d   /I   d ) f ) 1/n   ·H·W·I   sub   −m   ·I   d   m−1   (4) 
           [0014]    In the formula, W denotes a gate width, H denotes a coefficient depending on a condition for manufacturing a transistor, I sub  denotes a substrate current, and m denotes an index relating to an impact ionization and interface level formation.  
           [0015]    A coefficient A in a hot carrier lifetime model is represented by a formula (5) that is derived from the formulas (2) and (4).  
             A= (( W·H ) −1   ·I   sub   m   ·I   d   1−m ) n   (5) 
           [0016]    Therefore, a formula (6) is derived from the formulas (1) and (5).  
             ΔI   d   /I   d =(( W·H ) −1   ·I   sub   m   ·I   d   1−m   ·t ) n   (6) 
           [0017]    When Age is defined for convenience as in the following formula (7), the formula (6) can be rewritten into a formula (8).  
           Age=( W·H ) −1   ·I   sub   m   ·I   d   1−m   ·t   (7) 
           Δ I   d   /I   d =(age) n   (8) 
           [0018]    In the formula (7), ‘Age’ represents a stress quantity from a start of hot carrier stress to a time t in a hot carrier lifetime model. For a physical aspect of view, it represents a total quantity of hot carrier having energy of at least a critical energy to generate damage in a MOS transistor.  
           [0019]    The parameters n, H and m used in the formulas (4)-(8) are regarded as hot carrier lifetime parameters. These hot carrier lifetime parameters are functions of vertical electric field strength at a drain end where the hot carrier is generated. Therefore, these parameters are represented as functions of a gate-drain voltage V gd .  
           [0020]    [0020]FIGS. 7A and 7B show a method of simulating characteristics after degradation by using a ΔI d  model. A simulation method using a ΔI d  model is described in IEEE Trans. Electron Devices, vol. 40, pp.2245-2254, December 1993 by Quader et al.  
           [0021]    [0021]FIGS. 7A and 7B are equivalent circuit diagrams showing a method of simulating hot carrier degradation of a MOS transistor. In FIGS. 7A and 7B,  25  denotes a fresh MOS transistor before stress application, and  26  denotes a variable current source. FIG. 7A shows a drain current I d  flowing in a fresh MOS transistor before stress application. FIG. 7B shows a drain current I d ′ flowing in a MOS transistor after hot carrier degradation. It is shown that the drain current flowing in the transistor changes from the initial drain current I d  by ΔI d .  
           [0022]    As shown in the following formula (9), a drain current I d ′ after degradation is simulated by adding degradation ΔI d  of a drain current to a fresh drain current I d  before stress application.  
             I   d   ′=I   d ( V   d   , V   g )+Δ I   d (Age,  V   d   , V   g )  (9) 
           [0023]    ΔI d  is a function of Age as stress quantity from the start of hot carrier stress to a time t, as well as a function of a drain voltage V d  and a gate voltage V g . For calculating Age under a dynamic stress condition by AC (alternating current) in a circuit, the formula (7) is rewritten into the following formula (10) as an integral form about time for calculation.  
           Age=∫[( W·H ) −1   ·I   sub   m   ·I   d   1−m   ]dt   (10) 
           [0024]    In this simulation, ΔI d  is represented by an equivalent circuit prepared by adding a variable current source  26  shown in FIG. 7B to a source-drain of an initial MOS transistor. At this time, a transistor parameter to calculate the initial drain current is not changed.  
           [0025]    [0025]FIG. 8 is a flow chart to show a process to simulate hot carrier degradation of a MOS transistor according to a conventional technique. In this flow chart, a step S 1  includes sub-steps S 1   a -S 1   g  to extract an unknown parameter in the formulas (9) and (10) with respect to a hot carrier lifetime model by a preliminary measuring experiment.  
           [0026]    In the sub-step S 1   a,  a model formula I sub =g(V g , V d ) is determined to fit to measurement data of plural substrate currents I sub  in a preliminary measuring experiment, so that the substrate current I sub  in the formula (10) is determined. Here, V g  denotes a gate voltage, and V d  denotes a drain voltage. An example of a method for determining a substrate current I sub  is described in IEEE Electron Device Lett., vol. EDL-5, pp.505-507, December 1984 by Chan et al.  
           [0027]    The sub-steps S 1   b -S 1   d ′ are for extracting hot carrier lifetime parameters in a preliminary measuring experiment. In the sub-step S 1   b , a stress voltage is applied to a MOS transistor, and a hot carrier lifetime defined by the formula (2) is measured. For applying the stress voltage, a gate voltage V g  is set so that a gate-drain voltage V gd =V g −V d  is constant with respect to plural drain voltages V d . In this method, typically plural numbers of V gd  are set, and also gate voltages V g =V d +V gd  corresponding to the plural V gd  are set with respect to every drain voltage V d . In the following sub-step S 1   c ′, coefficient n is extracted as a function of V gd  by a comparison between the empirical formula (1) and data concerning measurement points in a DC stress experiment for the sub-step S 1   b.  Similarly in the sub-step S 1   d ′, an index m and a coefficient H are extracted as functions of V gd  by a comparison between the empirical formula (4) and data concerning measuring points in a DC stress experiment for the sub-step S 1   b.    
           [0028]    Sub-steps S 1   e -S 1   g  are for determining a fresh drain current I d  before stress application and degradation ΔI d  of the drain current in the formula (9) for a ΔI d  model. In the sub-step S 1   e,  transistor parameters such as carrier mobility and a flat-band voltage are extracted. Such parameters are used for determining fresh drain current I d (V d , V g ) before stress application. BSIM (Berkeley Short-Channel IGFET Model) is used for a model to determine such a fresh drain current I d (V d , V g ). The BSIM is described in detail in IEEE J. Solid-State Circuits, vol.SC-22, pp.558-566, August 1987 by Sheu et al. Subsequently in the sub-step S 1   f  DC stress is applied to the transistor. In the sub-step S 1   g , ΔI d  model parameters are extracted before and after the DC stress application. The drain current degradation ΔI d (Age, V d , V g ) is determined by the ΔI d  model parameters. The ΔI d  model is described by Quader et al. in relation to NMOS. PMOS is described in JP-A-08-64814.  
           [0029]    The transistor parameters should be extracted before DC stress application so that actual transistor characteristics before the stress application coincide with simulated transistor characteristics. The ΔI d  model parameters should be extracted before and after the DC stress application so that the actual drain current degradation ΔI d  before and after the stress application coincides with the simulated drain current degradation ΔI d .  
           [0030]    The step S 2  includes sub-steps S 2   a -S 2   d  so that a reliability simulator simulates hot carrier degradation of a transistor in accordance with parameters extracted in the step S 1  and also with the formulas (9) and (10).  
           [0031]    In the sub-step S 2   a , a drain current is simulated by transistor parameters before stress application, where the parameters have been extracted in the prior sub-step S 1   e.  In the sub-step S 2   b,  a substrate current is simulated on the basis of a substrate current model formula I sub =g(V g , V d ) determined by the S 1   a.  In the sub-step S 2   c ′, Age, which represents degradation of each transistor based on the formula (10), is calculated by time-integrating functions of a drain current I d  and a substrate current I sub  in a circuit. At this time, the drain current I d  simulated in the sub-step S 2   a , the substrate current I sub  simulated in the sub-step S 2   b , and hot carrier lifetime parameters H and m calculated in the sub-step S 1   d ′, are used. In the sub-step S 2   d , hot carrier degradation of the transistor is simulated by using the formula (9) on the basis of the Age.  
           [0032]    The following is a detailed explanation of a method of extracting hot carrier lifetime parameters H and m for a hot carrier lifetime model. FIG. 9 is an explanatory view of a method of extracting hot carrier lifetime parameters H and m. FIG. 9 relates to a plot for calculating hot carrier lifetime parameters H and m included in the empirical formula (4) using a hot carrier lifetime model. In FIG. 9, the vertical axis is a logarithmic scale of a value τ·I d /W calculated from a lifetime τ in a DC stress experiment, a drain current I d  during a stress and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio I sub /I d  when I sub  is a substrate current during a stress and I d  is a drain current. Numeral  27  denotes data concerning a plurality of measurement points in a DC stress experiment, and  28  denotes a line fitted with respect to data concerning the measurement points. The MOS transistor lifetime τ is measured under plural gate-drain voltage V gd  conditions, e.g., under three conditions of V gd =0.0, −1.0, and −2.0V, so that data  27  for plural measurement points are obtained. In this manner, a line  28 , fitted by a least squares method with respect to data  27  concerning the measurement points, is obtained. Hot carrier parameters H and m are obtained respectively from an intercept and a gradient of the line  28 . By executing this method for plural V gd , the hot carrier lifetime parameters H and m in a hot carrier lifetime model can be calculated as functions of V gd .  
           [0033]    The above description is about a conventional method of estimating lifetime of hot carrier degradation of a MOS transistor, and a conventional method of simulating degradation in circuit characteristics caused by the hot carrier degradation. However, these methods can cause the following problems.  
           [0034]    First, a lifetime under a condition for causing a maximum hot carrier degradation rate can be estimated to be longer than an actual lifetime in a method of estimating a lifetime of the hot carrier degradation of a MOS transistor. In such a method, it is hypothesized that a gate voltage causing maximum hot carrier degradation coincides with a gate voltage causing a maximum substrate current. In an empirical model (3), degradation is maximized as well at a gate voltage causing a maximum substrate current. Actually however, some processes for manufacturing transistors have maximum degradation at a gate voltage lower than a gate voltage causing a maximum substrate current. Therefore, lifetime in actual use can be shortened depending on a condition to use the MOS transistor as opposed to a lifetime corresponding to the maximum substrate current estimated according to this model. This results in a problem that the quality assurance of the product cannot be provided properly.  
           [0035]    Concerning a method of simulating circuit characteristic degradation caused by the hot carrier degradation, numbers of transistors are required to calculate hot carrier lifetime parameters, and this method will take a long period of time. A DC stress experiment should be executed by setting plural gate voltages V g  in order to keep a gate-drain voltage V gd =V g −V d  to be constant with respect to plural drain voltages V d , so that the index m and the coefficient H in the empirical formula (4) representing a conventional hot carrier lifetime model are extracted as functions of V gd . In this case, total numbers of stress voltage conditions are increased considerably. For example, about three conditions for a drain voltage, and about five conditions for a gate-drain voltage are required, which results in about 15 stress voltage conditions. Moreover, since the results of the DC stress experiment vary, plural (e.g., about three) transistors are required for every voltage condition in order to obtain sufficiently accurate results. As a result, about 45 transistors will be required. In addition to that, these transistors should be produced under an identical process condition. Since prototypes are produced repeatedly while altering the process condition during a process development, it is difficult to prepare such large numbers of transistors under an identical process condition. Moreover, measurement of 45 transistors under 15 voltage conditions will take about 10 days with ordinary equipment and staff. As a result, it is difficult to provide prompt feedback to the product designing. Since the product is designed in parallel with the process development, substantially an actual process development has not carried out a step of extracting a hot carrier lifetime parameter to simulate reliability in order to realize product reliability at the time of designing. As a result, a standard of process reliability evaluation with an excessive reliability margin is applied for quality assurance. It is difficult to meet such a reliability evaluation standard while providing high transistor performance.  
           [0036]    The cause of requiring numbers of transistors and long period of time for an experiment to calculate a hot carrier lifetime parameter is that a conventional hot carrier lifetime model represented with the formula (4) is insufficient for the purpose. Such a conventional hot carrier lifetime model is based on a hypothesis that hot carrier degradation is caused by a hot carrier of either a positive hole or an electron having energy of at least a critical energy required for generating damage to a MOS transistor, and that a hot carrier lifetime is inversely proportional to a yield of the one hot carrier. In this model, no functional forms are provided with respect to dependence of a gate-drain voltage V gd  of the hot carrier lifetime parameters H and m. Therefore, a DC stress experiment should be performed by setting plural gate voltages V g  with respect to plural drain voltages V d  in order to measure the V gd  dependence of the parameters H and m.  
         SUMMARY OF THE INVENTION  
         [0037]    In order to solve the above-identified problems, the present invention provides a method of estimating lifetime of hot carrier degradation of a MOS transistor, so that the lifetime is estimated with accuracy under a condition for causing a maximum hot carrier degradation rate, and thus, the present invention provides proper quality assurance for a product.  
           [0038]    The present invention enables calculating a hot carrier lifetime parameter in a short time by using a small number of transistors in a method of simulating circuit characteristic degradation caused by hot carrier degradation in order to provide product reliability at a time of designing, and to provide high transistor performance.  
           [0039]    For the above-mentioned purposes, a method of estimating a lifetime of a semiconductor device according to the present invention is characterized in that a hot carrier lifetime is estimated depending on a hot carrier lifetime model:  
           τ∝ I   sub   −m   ·I   d   m−2   
           [0040]    where τ is a lifetime, I sub  is a substrate current, I d  is a drain current, and m is a fitting parameter.  
           [0041]    The above-described hot carrier lifetime model according to the present invention reflects the fact that hot carrier degradation occurs due to two kinds of hot carriers of an electron and a positive hole having an energy of at least a critical energy required for generating damage to a MOS transistor, and that the hot carrier lifetime is inversely proportional to a product of a yield of these two hot carriers. According to this model, a model formula representing a hot carrier lifetime takes not either the conventional formulas (3) or (4) but the following formula (11).  
           τ=((Δ I   d   /I   d ) f ) 1/n   ·H·W   2   ·I   sub   −m   ·I   d   m−2   (11) 
           [0042]    The model formula (11) is distinguished from the conventional model formula (4) in that the formula (11) adopts a functional form of (exponent of I d )=−(exponent of I sub )−2, while the conventional formula adopts (exponent of I d )=−(exponent of I sub )−1. The difference is caused by the fact that a hot carrier lifetime is inversely proportional to a yield of one kind of hot carrier in a conventional technique, while the same lifetime is inversely proportional to a yield of two kinds of hot carriers in the present invention.  
           [0043]    It was confirmed by a comparison with measured values of N-type and P-type MOS transistors that a model of the present invention corresponds well to a measured value, and V gd  dependence of the hot carrier lifetime parameters H and m is decreased considerably. The reason is considered to be that the model of the present invention reflects accurately a mechanism of hot carrier degradation of a MOS transistor. In a conventional model, V gd  dependence of the hot carrier lifetime parameters H and m is increased. The reason is considered to be that such a model failed to reflect accurately a mechanism of hot carrier degradation of a MOS transistor.  
           [0044]    In the above-mentioned method of estimating a lifetime of a semiconductor device, a minimum value of a hot carrier lifetime in actual use can be estimated from a substrate current and a drain current under a use condition. More specifically, the method of estimating lifetime of hot carrier degradation according to the present invention is executed in the following manner. First, the hot carrier lifetime parameters H and m in the formula (11) are calculated as constants based on measured values in a stress acceleration experiment. These parameters and formula (11) are used for obtaining a condition for causing maximum hot carrier degradation in actual use based on measured values of a substrate current I sub  and a drain current I d  in actual use, and a hot carrier lifetime at that time also is obtained. Thus obtained lifetime is applied as an estimated lifetime in actual use.  
           [0045]    A method of simulating the reliability of a semiconductor device according to the present invention is characterized in that a parameter Age representing cumulative stress quantity relating to a MOS transistor is calculated on the basis of the following formula for simulating hot carrier degradation of the MOS transistor:  
           Age∝∫[ I   sub   m   ·I   d   2−m   ]dt   
           [0046]    where t is time, I sub  is a substrate current, I d  is a drain current, and m is a fitting parameter.  
           [0047]    For example, calculation is performed by using the following formula (12) as a functional form for time in place of the formula (10) in a method of simulating circuit characteristic degradation caused by hot carrier degradation of a MOS transistor.  
           Age=∫[( W   2   ·H ) −1   ·I   sub   m   ·I   d   2−m   ]dt   (12) 
           [0048]    In extraction of hot carrier lifetime parameters, hot carrier lifetime parameters H and m are calculated as constants based on measured values in a stress acceleration experiment. Here, the model formula (12) of the present invention is distinguished from the conventional model formula (10) in that the model formula (12) adopts a functional form of (exponent of I d  exponent)=2−(exponent of I sub ), while the conventional formula adopts (exponent of I d )=1−(exponent of I sub ). The difference reflects the fact that a hot carrier lifetime is inversely proportional to a yield of one kind of hot carrier in a conventional technique, while the same lifetime is inversely proportional to a yield of two kinds of hot carriers in the present invention. The hot carrier lifetime parameters H and m are identical to those in a model formula (11) for a hot carrier lifetime. V gd  dependence is considerably lowered, and thus, sufficient simulation accuracy can be obtained even if the parameters are applied as constants.  
           [0049]    This model formula (11) is obtained in the following manner. This model formula (11) is derived from a lucky electron model (IEEE Electron Devices, vol. ED-32, pp. 375-385, February 1985) and a hypothesis composing a physical logic of the present invention, i.e., “hot carrier degradation occurs due to two kinds of hot carriers of an electron and a positive hole having energy of at least a critical energy required for generating damage to a MOS transistor, and the hot carrier lifetime is inversely proportional to a product of a yield of these two kinds of hot carriers”.  
           [0050]    For NMOS, I e , I h , and I sub  are represented respectively by formulas (13), (14), and (15), in which I e  is an electron yield having energy of at least a critical energy required for generating damage to a MOS transistor, I h  is a yield of a positive hole having energy of at least a critical energy, and I sub  is a substrate current.  
             I   e   =I   d  exp(−Φ e   /qλ   e   E   m )  (13)  
             I   h   =I   sub  exp(−Φ h   /qλ   h   E   m )  (14)  
             I   sub   =I   d  exp(−Φ e1   /qλ   e   E   m )  (15) 
           [0051]    Here, I d  is a drain current, I sub  is a substrate current, Φ e  is a critical energy of an electron required for generating damage, Φ h  is a critical energy of a positive hole required for generating damage, Φ e1  is a critical energy of an electron required for impact ionization, λ e  is an electron mean free path, λ h  is a mean free path of a positive hole, and E m  is a maximum channel electric field strength. When a lifetime τ is hypothesized as being inversely proportional to a product of I e /W and I h /W, and qE m  is deleted by applying the formulas (13), (14) and (15), the following formula (16) is obtained. In this case, I e /W is a yield per unit gate width of an electron having energy of at least a critical energy, and I h /W is a yield of a positive hole having energy of at least a critical energy.  
                   τ   ∝                  W   2     /     (       I   e     ·     I   h       )                   =                    W   2     /     (       I   d     ·     I   sub       )            exp        [       (         Φ   h     /     λ   h       +       Φ   e     /     λ   e         )     /     qE   m       ]                     =                    W   2     /     (       I   d     ·     I   sub       )              (       I   sub     /     I   d       )     ⋀   -                                [       (         Φ   h     /     λ   h       +       Φ   e     /     λ   e         )     /     (       Φ   ei     /     λ   e       )       ]                   (   16   )                               
 
           [0052]    As a result of replacement as shown in the following formula (17),  
             m =(Φ h /λ h +Φ e /λ e )/(Φ e1 /λ e )+1  (17) 
           [0053]    a formula (18) is obtained from the formula (16).  
           τ∝( W/I   d ) 2 ( sub   /I   d ) −m   (18) 
           [0054]    When the parameter H is determined considering the formula (2), the model formula (11) representing a hot carrier lifetime of the present invention is obtained.  
           [0055]    The way to derive the conventional formula (4) is described below in order to explain why the exponents of I d  are different between the conventional model formula (4) and the model formula (11). The conventional model formula (4) depends on a hypothesis that hot carrier degradation occurs only due to an electron having energy of at least a critical energy required for generating damage to a MOS transistor, and that a hot carrier lifetime is inversely proportional to a yield of this hot carrier. When this hypothesis is adopted, a formula (19) corresponding to the formula (16) is obtained as follows.  
                   τ   ∝                  W   2     /     I   e                   =                    W   2     /     I   d            exp        (         Φ   e     /   q                     λ   h          E   m       )                     =                    W   2     /       I   d          (       I   sub     /     I   d       )         ⋀     -                [     (       Φ   e     /     Φ   ei       )     ]                       (   19   )                               
 
           [0056]    As a result of replacement as shown in the following formula (20),  
             m= 101     e /Φ ei   (20) 
           [0057]    a formula (21) is obtained from the formula (19).  
           τ∝ W/I   d ( I   sub   /I   d ) −m   (21) 
           [0058]    As mentioned above, there is a difference in the exponents of I d  between the model formula (18) of the present invention and the conventional model formula (21). A difference in formation of model formulas reflects the difference in the hypothesis about what the lifetime is inversely proportional to.  
           [0059]    For PMOS, I e , I h , and I sub  are represented respectively by formulas (22), (23), and (24), in which I e  is an electron yield having energy of at least a critical energy required for generating damage to a MOS transistor, I h  is a yield of a positive hole having energy of at least a critical energy, and I sub  is a substrate current.  
             I   e   =I   sub  exp(−Φ e   /qλ   e   E   m )  (22)  
             I   h   =I   d  exp(−Φ h   /qλ   h   E   m )  (23)  
             I   sub   =I   d  exp(−Φ hi   /qλ   h   E   m )  (24) 
           [0060]    Here, I d  is a drain current, I sub  is a substrate current, Φ e  is a critical energy of an electron required for generating damage, Φ h  is a critical energy of a positive hole required for generating damage, Φ hi  is a critical energy of a positive hole required for impact ionization, λ e  is an electron mean free path, λ h  is a mean free path of a positive hole, and E m  is a maximum channel electric field strength. When a lifetime τ is hypothesized as being inversely proportional to a product of I e /W and I h /W, and qE m  is deleted by applying the formulas (22), (23) and (24), the following formula (25) is obtained. In this case, I e /W is a yield per unit gate width of an electron having energy of at least a critical energy, and I h /W is a yield of a positive hole having energy of at least a critical energy.  
                   τ   ∝                  W   2     /     (       I   e     ·     I   h       )                   =                    W   2     /     (       I   d     ·     I   sub       )            exp        [       (         Φ   h     /     λ   h       +       Φ   e     /     λ   e         )     /     qE   m       ]                     =                    W   2     /     (       I   d     ·     I   sub       )              (       I   sub     /     I   d       )     ⋀   -                                [       (         Φ   h     /     λ   h       +       Φ   e     /     λ   e         )     /     (       Φ   hi     /     λ   h       )       ]                   (   25   )                               
 
           [0061]    When the above formula is rewritten as follows,  
             m= (Φ h /λ h +Φ e /λ e )/(Φ hi /λ h )+1  (26) 
           [0062]    a formula (18) similar to that of NMOS is obtained from the formula (25). When the parameter H is determined considering the formula (2) as in the case of NMOS, the model formula (11) representing a hot carrier lifetime of the present invention is obtained.  
           [0063]    The formula (12) for calculating Age, which is used in a method of simulating circuit characteristic degradation caused by hot carrier degradation of a MOS transistor of the present invention, is derived from a comparison with the formula (8) after parameters A and τ are deleted from the formulas (11) together with the formulas (1) and (2).  
           [0064]    In the model formula (11) of the present invention, the gate-drain voltage V gd  dependence of the hot carrier lifetime parameter is extremely small for N-type and P-type MOS transistors. Therefore, even if it is used as a constant, a lifetime can be estimated accurately in a wide range of voltage. As a result, in a method of estimating lifetime of hot carrier degradation of a MOS transistor of the present invention, a voltage condition for causing a maximum degradation rate and the lifetime, i.e., a lifetime in actual use, can .be estimated accurately from a measured value under a small number of stress voltage conditions and a drain current I d  and a substrate current I sub  in actual use. This serves to provide proper quality assurance of the product.  
           [0065]    Since the hot carrier lifetime parameters H and m are constants in a method of simulating circuit characteristic degradation caused by hot carrier degradation of a MOS transistor according to the present invention, the hot carrier lifetime parameters H and m can be obtained from measured values taken under a small numbers of stress voltage conditions. For example, typically three conditions are used for a drain voltage, and one condition of a gate voltage V g  causing a maximum substrate current I sub  with respect to each drain voltage. In such a case, only about three conditions will be required for the stress voltage conditions. Since results of a DC stress experiment vary, plural numbers of (e.g., about three) transistors should be used for each voltage condition in order to obtain sufficient accuracy. Even so, only about nine transistors are required. In other words, the number of transistors can be decreased considerably from the numbers of 45 in a conventional technique. When about 9 transistors of the same process conditions are prepared for measurement under three voltage conditions, it will take only 2 days with ordinary equipment and staff. Therefore, a prompt feedback to the product designing can be provided. This enables extracting hot carrier lifetime parameters during a process development and to perform reliability simulation in order to provide product reliability at a time of designing. Therefore, it is not necessary to apply a process reliability evaluation standard having an excessive reliability margin for the purpose of quality assurance. In this way, the present invention can satisfy a reliability evaluation standard and also realize high transistor performance.  
           [0066]    In the above-mentioned method of simulating reliability of a semiconductor device, the fitting parameter m can be a function of a gate-drain voltage, so that a simulation with higher accuracy can be performed.  
           [0067]    Alternatively the fitting parameter m can be used as a function of the substrate voltage, so that a simulation with a high accuracy is obtainable even when the substrate voltage dependence of the hot carrier degradation is not negligible.  
           [0068]    Furthermore in the above-mentioned method of simulating reliability of the semiconductor device, measurement data is plotted by using a logarithmic scale of a value τ·(I d /W) 2  calculated from a lifetime τ in a DC stress experiment, a drain current I d  during a stress, and a gate width W of the MOS transistor to enter a vertical axis and by using a logarithmic scale of a ratio I sub /I d  when I sub  is a substrate current during stress and I d  is a drain current, so that a fitting parameter m is obtained from a gradient of a line fitted with respect to the plot. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0069]    [0069]FIG. 1 is an explanatory view to show a method of estimating lifetime on the basis of a hot carrier lifetime model in an embodiment of the present invention.  
         [0070]    [0070]FIG. 2 is an explanatory view to show a method of calculating a hot carrier lifetime in actual use according to an embodiment of the present invention.  
         [0071]    [0071]FIG. 3 is a flow chart to show a method of simulating circuit characteristic degradation in an embodiment of the present invention.  
         [0072]    [0072]FIG. 4 is an explanatory view to show a method of extracting a hot carrier lifetime parameter as a constant in an embodiment of the present invention.  
         [0073]    [0073]FIG. 5 is an explanatory view to show a method of extracting a hot carrier lifetime parameter as a function of a gate-drain voltage in an embodiment of the present invention.  
         [0074]    [0074]FIG. 6 is an explanatory view to show a conventional method of estimating a lifetime.  
         [0075]    [0075]FIGS. 7A and 7B are equivalent circuit diagrams to show a conventional method of simulating hot carrier degradation of a MOS transistor.  
         [0076]    [0076]FIG. 8 is a flow chart to show a conventional method process of simulating hot carrier degradation of a MOS transistor.  
         [0077]    [0077]FIG. 9 is an explanatory view to show a conventional method of extracting a hot carrier lifetime parameter. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0078]    Embodiments according to the present invention are further explained below by referring to the drawings.  
         [0079]    [0079]FIG. 1 shows a method of estimating a lifetime based on a hot carrier lifetime model formula (11) according to the present invention. FIG. I is an explanatory view to show a method of extracting hot carrier lifetime parameters H and m in a hot carrier lifetime model of the present invention. In FIG. 1, the vertical axis is a logarithmic scale of a value τ·(I d /W) 2  calculated from a lifetime τ in a DC stress experiment, a drain current I d  during a stress, and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio I sub /I d , where I sub  is a substrate current during a stress and I d  is a drain current. Black dots  1  denote data concerning plural measurement points in the DC stress experiment, and  2  denotes a line fitted with respect to the data concerning the measurement points. Numeral  3  denotes a value of I sub /I d  causing a maximum degradation, and  4  denotes a maximum value of I sub /I d  in actual use. Numeral  5  denotes a value on the fitting line with respect to the I sub /I d  value  3  causing maximum degradation, and  6  denotes a value on the fitting line with respect to the I sub /I d  maximum value  4  in actual use.  
         [0080]    A method mentioned below is used to apply stress voltage for a stress acceleration experiment in a hot carrier reliability evaluation. A gate voltage V g  used in the method is a voltage causing a maximum substrate current I sub  with respect to plural drain voltages V d  used in the acceleration experiment. At this time, one gate voltage is set for every drain voltage. Accordingly, a line  2  is obtained by fitting on the basis of a least squares method with respect to data  1  concerning plural measurement points. Based on the intercept and gradient of the line  2 , hot carrier lifetime parameters H and m are obtained respectively as constants.  
         [0081]    From these hot carrier lifetime parameters and the model formula (11), a value  3  of I sub /I d  causing maximum degradation and a value  5  on a fitting line at the I sub /I d  causing maximum degradation are obtained. The value  3  of I sub /I d  causing maximum degradation is smaller than a maximum value  4  of I sub /I d  in actual use. The value  5  on a fitting line at the I sub /I d  causing maximum hot carrier degradation is larger than a value  6  on the fitting line with respect to a maximum value of I sub /I d  in actual use.  
         [0082]    [0082]FIG. 2 shows a method to obtain a condition to cause maximum hot carrier degradation in actual use, and to obtain a hot carrier lifetime at that time. FIG. 2 is an explanatory view to show a method of calculating a lifetime in actual use depending on measurement values of transistor characteristics. In FIG. 2, the horizontal axis is a gate voltage, the left vertical axis is a logarithmic scale of a drain current and a substrate current, and the right vertical axis is a logarithmic scale of a lifetime. A curve  7  denotes a drain current I d , a curve  8  denotes a substrate current I sub  and a curve  9  denotes a calculation value of the lifetime. Numeral  10  denotes a gate voltage causing maximum hot carrier degradation, and  11  denotes an estimated value of lifetime in actual use. In this method, the gate voltage V g  is changed under the maximum drain voltage V ddmax  in actual use with respect to the transistor so as to measure the drain current  7  and the substrate current  8 . The calculation value  9  is obtained from these measured values, the previously calculated hot carrier lifetime parameters H and m, and the model formula (11). The gate voltage V g  to cause the minimum calculation value of lifetime is the gate voltage  10  causing the maximum hot carrier degradation, and the lifetime is determined as the estimated value  11  of lifetime in actual use. In this way, the condition to cause the maximum hot carrier degradation in actual use is obtained so as to obtain the hot carrier lifetime at that time. By using this for the estimated lifetime in actual use, a hot carrier lifetime under a condition to cause the maximum hot carrier degradation can be obtained.  
         [0083]    [0083]FIG. 3 is a flow chart showing a method process of simulating circuit characteristic degradation according to the present invention. In the flow chart, a step S 1  includes sub-steps S 1   a -S 1   g  to extract unknown parameters in the formulas (9) and (12) by using a preliminary measuring experiment.  
         [0084]    In the sub-step S 1   a , in order to determine a substrate current I sub  in the formula (10), a model formula I sub =g(V g , V d ) is determined to fit with a plurality of substrate current I sub  measurement data in the preliminary measuring experiment. Here, V g  represents a gate voltage, and V d  represents a drain voltage. A method of determining a substrate current I sub  is described in IEEE Electron Device Lett., vol. EDL-5, pp.505-507, December 1984 by Chan et al.  
         [0085]    The sub-steps S 1   b -S 1   d  serve to extract hot carrier lifetime parameters by a preliminary measuring experiment. In the sub-step S 1   b , stress voltage is applied to a MOS transistor in order to measure a hot carrier lifetime defined in the formula (2). For applying the stress voltage, a gate voltages V g  causing a maximum substrate current I sub  is used with respect to plural drain voltage V d . At this time, one gate voltage is set for every drain voltage. In the subsequent sub-step S 1   c , a coefficient n is extracted as a constant by a comparison between the empirical formula (1) and data concerning plural measurement points in a DC stress experiment in the sub-step S 1   b . Similarly in the sub-step S 1   d , an index m and a coefficient H are extracted as constants by a comparison between the empirical formula (11) and data concerning plural measurement points in a DC stress experiment of the sub-step S 1   b.    
         [0086]    The sub-steps S 1   e -S 1   g  serve to determine a fresh drain current I d  before applying stress and drain current degradation ΔI d  in the formula (9) for a ΔI d  model. In the sub-step S 1   e , transistor parameters, such as a flat band voltage and carrier mobility to determine fresh drain current I d (V d , V g ) before stress application, are extracted. BSIM (Berkeley Short-Channel IGFET Model) can be used for a model to determine such a fresh drain current I d (V d , V g ). Details of the BSIM method are described in IEEE J. Solid-State Circuits, vol. SC-22, pp. 558-566, August 1987 by Sheu et al. In the subsequent sub-step S 1   f , a DC stress is applied to the transistor. In the sub-step S 1   g , ΔI d  model parameters before and after DC stress application are extracted. The drain current degradation ΔI d  (Age, V d , V g ) is determined from this ΔI d  model parameter. The ΔI d  model concerning NMOS is described by the above-mentioned Quader et al. PMOS is described in JP-A-08-64814.  
         [0087]    Transistor parameters should be extracted before the DC stress application in order to bring actual transistor characteristics before the stress application to coincide with the simulated transistor characteristics. Similarly, the ΔI d  model parameters should be extracted before and after the DC stress application in order to bring actual drain current degradation ΔI d  after the stress application to coincide with the simulated drain current degradation ΔI d .  
         [0088]    A step S 2  includes sub-steps S 2   a -S 2   d  in which a reliability simulator simulates hot carrier degradation of a transistor in accordance with the parameters extracted in the step S 1  and the formulas (9) and (12).  
         [0089]    In the sub-step S 2   a , a drain current is simulated by the transistor parameters before stress application, and the parameters have been extracted in the sub-step S 1   e.  In the sub-step S 2   b , a substrate current is simulated by the substrate current model formula I sub =g(V g , V d ) determined by the S 1   a.  In the sub-step S 2   c , Age, which represents degradation of every transistor on the basis of the formula (12), is calculated by time integration of a function of a drain current I d  and substrate current I sub  in a circuit. At this time, a drain current I d  simulated in the sub-step S 2   a , a substrate current I sub  simulated in the sub-step S 2   b , and hot carrier lifetime parameters H and m calculated in the sub-step S 1   d,  are used. In the sub-step S 2   d , hot carrier degradation of the transistor is simulated based on the Age, by using the formula (9).  
         [0090]    The following is a detail about a method of extracting the hot carrier lifetime parameters H and m on the basis of a hot carrier lifetime model. FIG. 4 is an explanatory view to show a method of extracting hot carrier lifetime parameters H and m as constants. FIG. 4 shows a plot to calculate the hot carrier lifetime parameters H and m included in the empirical formula (11) using a hot carrier lifetime model. In FIG. 4, the vertical axis is a logarithmic scale of a value τ·(I d /W) 2  calculated from a lifetime τ in a DC stress experiment, a drain current I d  during a stress, and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio I sub /I d  where I sub  is a substrate current during a stress and I d  is a drain current. Numeral  12  denotes data concerning plural measurement points in a DC stress experiment, and  13  denotes a line fitted with respect to the data  12  concerning the measurement points.  
         [0091]    For measuring a lifetime τ of a MOS transistor, for example, three kinds of drain voltage conditions, and a gate voltage V g  condition causing a maximum substrate current I sub  with respect to each drain voltage are prepared, and three transistors are measured under each voltage condition. Accordingly, the data  12  concerning nine measurement points are obtained. A line  13  is obtained by performing a fitting on the basis of a least squares method with respect to the data  12  for the nine measurement points. The fitted line  13  has a gradient of −m. From an intercept and the gradient of the line  13 , hot carrier lifetime parameters H and m in the model formula (11) of the present invention can be obtained respectively as constants. Since the hot carrier lifetime parameters are constants, the measurement values in the model of the present invention can be decreased to nine, while a conventional model requires as many as 45 measurement values. As a result, the model of the present invention takes only about two days for extracting hot carrier lifetime parameters with ordinary equipment and staff, while a conventional model takes about 10 days with the same equipment and staff. In this manner, the present invention can shorten the extraction period considerably.  
         [0092]    In the calculation to obtain hot carrier lifetime parameters according to the present invention, accuracy of the extracted parameters can be improved by applying the vertical axis to τ·(I d /W) 2 . For example, using τ·(I d /W)·(I sub /W) to enter the vertical axis is equivalent mathematically or physically. In this case, the gradient of the fitted line is −(m−1). However in this method, I sub  is included both in the horizontal axis and vertical axis. This increases variations in data concerning the measurement points to be plotted, and accuracy of the extracted hot carrier lifetime parameters degrades. Therefore, using τ·(I d /W) 2  to enter the vertical axis is effective to extract hot carrier lifetime parameters with a high accuracy as indicated in the present invention.  
         [0093]    In general, hot carrier lifetime parameters H and m can be provided with sufficient accuracy for use by extracting parameters as constants and by calculating Age. When a further accurate simulation is required, the hot carrier lifetime parameters H and m of the model formula (11) are extracted as functions of gate-drain voltage V gd , and in addition to that, Age of the model formula (12) can be calculated as a function of the gate-drain voltage V gd  at a time of simulating circuit characteristic degradation. In such a case, a stress voltage is applied by setting a gate voltage V g  so that the gate-drain voltage V gd =V g −V d  becomes constant with respect to plural drain voltages V d  in the sub-step S 1   b  shown in the flow chart of FIG. 3 to indicate a method process of simulating circuit characteristic degradation according to the present invention. Generally in this method, plural V gd  are set and a gate voltage V g =V d +V gd  corresponding to the preliminarily set plural V gd  with respect to the every drain voltage V d  are also set. In the sub-step S 1   d,  an index m and a coefficient H are extracted as functions of V gd  by a comparison between the model formula (11) and the data concerning plural measurement points in the DC stress experiments of the sub-step S 1   b . In the sub-step S 2   c,  Age that represents degradation of each transistor is calculated based on the formula (12) by using the index m and coefficient H as functions of V gd .  
         [0094]    The following explanation is about a method of extracting hot carrier lifetime parameters H and m as functions of a gate-drain voltage V gd  in a hot carrier lifetime model according to the present invention. FIG. 5 is an explanatory view to show a method of extracting hot carrier lifetime parameters H and m as functions of a gate-drain voltage in a hot carrier lifetime model according to the present invention. FIG. 5 indicates a plot to calculate the hot carrier lifetime parameters H and m included in the empirical formula (11) using a hot carrier lifetime model. In FIG. 5, the vertical axis is a logarithmic scale of a value τ·(I d /W) 2  calculated on the basis of a lifetime τ in a DC stress experiment, a drain current I d  during a stress, and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio I sub /I d  where I sub  is a substrate current during the stress, and I d  is a drain current. Numeral  14  denotes data concerning plural measurement points in a DC stress experiment, and  15  denotes a line fitted with respect to the data  14  concerning the measurement points.  
         [0095]    The lifetime τ of the MOS transistor is measured under plural conditions of gate-drain voltages V gd , for example, three conditions of V gd =0.0, −1.0, and −2.0V, so that data  14  concerning plural measurement points are obtained. A line  15  is obtained by performing a fitting on the basis of a least squares method with respect to the data  14  for the plural measurement points. From the intercept and the gradient of the line  15 , hot carrier lifetime parameters H and m can be obtained respectively. Similarly, hot carrier lifetime parameters H and m can be obtained as functions of plural V gd  in a hot carrier lifetime model.  
         [0096]    When a substrate voltage dependence of the hot carrier degradation is not negligible, hot carrier lifetime parameters H and m in the model formula (11) are extracted as functions of the substrate voltage V b , while Age in the model formula (12) can be calculated as a function of the substrate voltage V b  at a time of simulating circuit characteristic degradation. In such a case, stress voltage is applied by setting plural V b  with respect to plural drain voltages V d  in the sub-step S 1   b  shown in the flow chart of FIG. 3 to indicate a method process of simulating circuit characteristic degradation according to the present invention. In the sub-step S 1   d , an index m and a coefficient H are extracted as functions of V b  by a comparison between the model formula (11) and the data concerning plural measurement points in the DC stress experiment of the sub-step S 1   b . In the sub-step S 2   c,  Age that represents degradation of each transistor is calculated based on the formula (12) by using the index m and coefficient H as functions of V b .  
         [0097]    In a MOS transistor, plural degradation modes can exist depending on stress voltages or stress temperatures. In such a case, drain current I d ″ after degradation is simulated in accordance with a formula (12) including one or plural Age′ corresponding to other degradation modes, in place of a drain current I d ′ after degradation represented by a model formula (9) of the present invention.  
           I   d   ″=I   d ( V   d   , V   g )+Δ I   d (Age, Age′,  V   d   , V   g )  (9) 
         [0098]    In the methods of estimating a lifetime or simulating circuit characteristic degradation in the embodiment of the present invention, the processes are programmed wholly or partly, and performed automatically by computers. Alternatively, the methods can be performed manually when automatic performance is not available.  
         [0099]    As mentioned above, a lifetime in actual use can be estimated accurately according to the method of estimating lifetime of hot carrier degradation of a MOS transistor in the present invention, and thus, quality assurance of the product can be provided properly. As a result, the reliability of products on the market will be improved.  
         [0100]    In the method of simulating reliability according to the present invention, an experiment to obtain hot carrier lifetime parameters can be carried out with small numbers of transistors, and thus, prompt feedback to product designing will be available. Reliability simulation can be performed by extracting hot carrier lifetime parameters during a process development, so that the product reliability can be provided at the time of designing. Accordingly, products having high performance and high reliability can be developed in a short period and produced on a large scale.  
         [0101]    The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.