Abstract:
The present invention provides a substrate treating method including the steps of joining a one-side surface of a substrate to be treated to a support substrate, treating the substrate to be treated in the condition where the substrate to be treated is supported by the support substrate, and removing the support substrate from the substrate to be treated. The step of joining the substrate to be treated to the support substrate includes melting a joint bump formed on the substrate to be treated so as to join the substrate to be treated to the support substrate, and the step of removing the support substrate from the substrate to be treated includes polishing the support substrate so as to remove the support substrate.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
       [0001]    The present invention contains subject matter related to Japanese Patent Application JP 2006-144893 filed in the Japanese Patent Office on May 25, 2006, the entire contents of which being incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to a substrate treating method for treating a substrate to be treated, such as a semiconductor substrate, in the condition where the substrate to be treated is supported by a support substrate, and a method of manufacturing a semiconductor apparatus by use of the substrate treating method. 
         [0003]    In recent years, attendant on the demand for enhancement of the performances of electronic apparatuses and for reductions in the thickness and size of electronic apparatuses, the integration density and mounting density of electronic parts have been enhanced progressively, and semiconductor apparatuses of the MCM (Multi-Tip Module) or SIP (System-In-Package) type using the flip chip mounting have been coming to constitute a main stream. This kind of semiconductor apparatuses include those based on a configuration in which the flip chip mounting of a second semiconductor chip on a first semiconductor chip is adopted. 
         [0004]      FIG. 3  is a sectional view showing a general configuration of this kind of semiconductor apparatus in the past. The semiconductor apparatus shown includes a first semiconductor chip  1  and a second semiconductor chip  2 . The second semiconductor chip  2  is mounted on a substantially central area of a principal surface of the first semiconductor chip  1  by flip chip mounting in which a plurality of bumps  3  are used. In the periphery of the first semiconductor chip  1 , a plurality of electrode pads  4  are formed in the manner of surrounding the region where the second semiconductor chip  2  is mounted. In addition, a dam  5  is provided between the chip mounting area and the forming region of the electrode pads  4 , on the principal surface of the first semiconductor chip  1 . The dam  5  is formed in a rectangular frame-like shape in plan view on the inner side of the forming region of the electrode pads  4  in such a manner as to surround the chip mounting region. Besides, the gap between the first semiconductor chip  1  and the second semiconductor chip  2  is filled with an underfill material  6 . 
         [0005]    The related-art semiconductor apparatus configured as above is adhered onto a mounting substrate  7  through an adhesive material layer  8  as shown in  FIG. 3 , and then electrical connection between the electrode pads  4  on the first semiconductor chip  1  and lands  9  on the mounting substrate  7  is made through bonding wires  10 . 
         [0006]    In recent years, in relation to such semiconductor apparatuses of the MCM or SIP type, there has been a demand for a higher signal processing speed, a smaller mounting area, and the like. Specifically, the semiconductor apparatus mounted by the wire bonding system shown in  FIG. 3  has the problem of a delay in signal transfer due to the wiring length of the bonding wires  10  and the problem of securing the mounting area necessary for laying around the bonding wires  10 . 
         [0007]    In view of this, a configuration may be adopted in which, as schematically shown in  FIG. 4 , the first semiconductor chip  1  is provided with vias (through electrodes)  11  to establish inter-layer connection between the bumps  3  joined to the second semiconductor chip  2  on the upper layer side and bumps  12  joined to the mounting substrate  7  on the lower layer side. This configuration is very advantageous because it is thereby possible to simultaneously realize a higher signal processing speed and a smaller mounting area. 
         [0008]    For forming the vias, it may be necessary to reduce the thickness of the wafer, in order to realize a shorter processing time and a reduced pitch. For thinning the wafer, back grinding has been practiced. Thus, as a method of forming vias, there has been known a method in which vias are buriedly formed from the face side of a wafer, and thereafter the back side of the wafer is ground so that terminal surfaces of the vias are exposed to the exterior (see Japanese Patent Laid-open No. 2004-241479). 
         [0009]    Meanwhile, as the wafer thickness is reduced, the wafer becomes more liable to warp, and it becomes more difficult to handle the wafer. In view of this, it may be necessary to adhere a support substrate to the face side of the wafer, thereby enhancing the supportability of the wafer, and to appropriately remove the support substrate from the substrate to be treated, after the treatment of the substrate to be treated is completed. 
         [0010]    As above-mentioned, the adhesive for adhesion between the support substrate and the wafer is necessary to have good temporary fixation performance for enduring the processing of the wafer and good stripping property for removal thereof after completion of the wafer processing. In relation to the technology of peeling (removing) the adhesive, there have been proposed, for example, a method of removing the adhesive by dissolution in a solvent, and a method of lowering the adhesiveness of the adhesive by irradiation with UV rays (see Japanese Patent Laid-open No. 2003-171624 and Japanese Patent Laid-open No. 2005-191550). 
         [0011]      FIGS. 5A to 5J  are step sectional views illustrating a method of manufacturing a semiconductor apparatus as a first related-art example. 
         [0012]    First, as shown in  FIG. 5A , there is prepared a wafer  100  in which a device layer  102  including semiconductor devices such as transistors, wirings  103 , an insulating layer  104 , and the like is formed on the face side of a substrate body (semiconductor substrate)  101  composed of silicon. Electrode pads  105  in conduction with parts of the wiring layer  103  are formed on the face side of the device layer  102 , and a buried conductor layer  106 P in conduction with parts of the wiring layer  103  is formed on the face side of the substrate body  101 . 
         [0013]    Next, as shown in  FIG. 5B , solder bumps  107  are formed on the electrode pads  105  on the face side of the device layer  102 . Subsequently, as shown in  FIG. 5C , an adhesive is applied to the whole surface area of the device layer  102  inclusive of the solder bumps  107  to form an adhesive material layer  108 , and a support substrate  109  is adhered onto the adhesive material layer  108 . The support substrate  109  is composed of a glass substrate or silicon substrate provided therein with a plurality of through-holes  109   a  for supplying a stripping liquid. 
         [0014]    Subsequently, as shown in  FIG. 5D , in the condition where the wafer  100  is supported by the support substrate  109 , the back side of the substrate body  101  is ground so as to thin the substrate body  101  to a predetermined thickness, and to expose tip portions  106   a  of the vias (buried conductor layer)  106  from the back side of the thinned substrate body  101   t . Incidentally, though simplifiedly shown in the figure, the thinned substrate body  101   t  is in practice formed to be thicker than the device layer  102 , and the support substrate  109  is in practice formed to be thicker than the substrate body  101   t . In addition, in  FIG. 5D  and the latter figures, the wafer  101  is shown in the upside-down state (as compare with its posture in the former figures). 
         [0015]    Thereafter, as shown in  FIG. 5E , an insulating film  111  is formed on the back side of the substrate body  101   t , and external connection terminals  112  are formed on the tip portions  106   a  of the vias  106 . Then, as shown in  FIG. 5F , semiconductor chips  113  are mounted on the external connection terminals  112  by flip chip mounting; thereafter, as shown in  FIG. 5G , an underfill layer  114  is formed in the mounting areas of the semiconductor chips  113 . 
         [0016]    Next, as shown in  FIG. 5H , the support substrate  109  is released (peeled) from the adhesive material layer  108 . The support substrate  109  is released (peeled) by supplying a stripping liquid (e.g., alcohol) via the plurality of through-holes  109   a  formed in the inside of the support substrate  109  to thereby dissolve the adhesive material layer  108 . Then, as shown in  FIG. 5I , the adhesive material layer  108  is dissolved away, and thereafter the wafer  100  is diced on a chip basis, whereby semiconductor apparatuses  100 A of a chip-on-chip structure having the vias (through electrodes)  106  as shown in  FIG. 5J  are manufactured. 
         [0017]    In the next place,  FIGS. 6A to 6I  are step sectional views illustrating a method of manufacturing a semiconductor apparatus as a second related-art example. Incidentally, in the figures, the portions corresponding to those in the first related-art example described above are denoted by the same symbols as used above, and detailed descriptions of these portions will be omitted. 
         [0018]    In this example of the related art, the steps of forming solder bumps  107  on the face side of a wafer  100  and thereafter adhering a support substrate are the same as those in the first related-art example ( FIGS. 6A to 6C ). It should be noted that this example differs from the first related-art example in that the support substrate  119  is adhered to the face side of the wafer  100  through an adhesive material layer  118  formed of an adhesive of which the adhesiveness is deteriorated by irradiation with UV rays. The support substrate  119  is composed of a glass substrate which is transparent to UV rays. 
         [0019]    Then, like in the first related-art example, the steps of thinning a substrate body  101  ( FIG. 6D ), forming external connection terminals  112  ( FIG. 6E ), mounting semiconductor chips  113  ( FIG. 6F ), and forming an underfill layer  114  ( FIG. 6G ) are conducted. Thereafter, the step of irradiating the adhesive material layer  118  with UV rays through the support substrate  119  to thereby release (peel) the support substrate  119  from the wafer  100  is carried out ( FIG. 6H ). Then, the wafer  100  is diced on a chip basis, whereby semiconductor devices  100 A of the chip-on-chip structure having the vias (through electrodes)  106  as shown in  FIG. 6I  are manufactured. 
       SUMMARY OF THE INVENTION 
       [0020]    As has been mentioned above, the adhesive material  108 ,  118  for adhesion between the wafer  100  and the support substrate  109 ,  119  is necessary to have good temporary fixation performance for enduring the processing of the wafer and good stripping property for removal thereof after completion of the wafer processing. In the above-mentioned examples of the related art, therefore, an adhesive soluble in organic solvents or an adhesive of which the adhesive force can be lowered by irradiation with UV rays has been used to form the adhesive material layer  108 ,  118 . 
         [0021]    However, these adhesives are generally low in heat resistance, and a lowering in the adhesiveness or stripping property thereof would be generated when they are heated to above the heat resisting temperature thereof. This leads to the problem that a high-temperature treatment above the heat resisting temperature of the adhesive material layer  108 ,  118  is not applied during the wafer processing. 
         [0022]    For example, in the case of an insulating film such as an SiO 2  film, the film quality is more excellent and the adhesion of the film to a silicon substrate is better as the film forming temperature is higher. However, such a high-temperature treatment is not applied to a substrate supported on a support substrate by adhesion as above-mentioned, so that it would be necessary to adopt a low-temperature film forming process such as low-temperature CVD process. As a result, in the step of forming the insulating film  111  on the back side of the substrate body  101   t  ( FIG. 5E ,  FIG. 6E ), it would be difficult to secure reliability of the insulating film  111 . In addition, in the step of joining the semiconductor chips  113  ( FIG. 5F ,  FIG. 6F ), it would be necessary to use a low-temperature solder meltable below the heat resisting temperature of the adhesive material layer  108 ,  118 , causing restrictions in selection of materials. 
         [0023]    Besides, the above-mentioned adhesive material layers  108 ,  118  are low not only in heat resistance but also in chemical resistance; therefore, they have the problem that the chemical or the method for treating them without causing damage thereto, such as dissolution and denaturing deterioration, would be limited. Particularly, the adhesive material layer  108  is low in resistance to resist stripping liquids which contain such a solvent as PGMEA (Propylene Glycol Monomethyl Ether Acetate), ECA (Ethyl Cellosolve Acetate), etc. Therefore, there is the problem that in the step of patterning the insulating film  111  or in the step of forming the external connection terminals  112  ( FIG. 5E ), the method for treating the pattern resist would be restricted (e.g., dipping is not conducted). 
         [0024]    Thus, there is a need for a substrate treating method, and a method of manufacturing a semiconductor apparatus, by which a substrate can be appropriately supported without using an adhesive material layer necessary for having good temporary fixation performance and good stripping property (removability) and by which a support substrate can be removed appropriately. 
         [0025]    According to one embodiment of the present invention, a substrate treating method includes the steps of joining a one-side surface of a substrate to be treated to a support substrate, treating the substrate to be treated in the condition where the substrate to be treated is supported by the support substrate, and removing the support substrate from the substrate to be treated. The step of joining the substrate to be treated to the support substrate includes melting a joint bump formed on the substrate to be treated so as to join the substrate to be treated to the support substrate, and the step of removing the support substrate from the substrate to be treated includes polishing the support substrate so as to remove the support substrate. 
         [0026]    In the one embodiment of the present invention, the joining between the support substrate and the substrate to be treated is conducted by fusing of the joining bump(s) formed on the substrate to be treated, and the removal of the support substrate is conducted by polishing the support substrate, so that an adhesive having good temporary fixation performance and good stripping property (removability) necessary in the related art can be unnecessitated. This ensures that the processing of the substrate to be treated can be carried out without restrictions as to the heat resisting temperature or the chemical resistance of an adhesive. Therefore, it is possible, for example, to form an insulating film excellent in adhesion and to stably pattern the terminal surfaces. 
         [0027]    In addition, by use of the substrate treating method according to the one embodiment of the present invention, a semiconductor apparatus of a chip-on-chip structure in which a semiconductor chip on the lower layer side is provided with vias (through electrodes) for inter-layer connection can be manufactured with high accuracy and high reliability. 
         [0028]    According to another embodiment of the present invention, a method of manufacturing a semiconductor apparatus includes the steps of: fabricating a plurality of first semiconductor chips each provided on a surface thereof with a bump for external connection; joining the plurality of first semiconductor chips to a support substrate through the bumps; filling the spaces between the plurality of first semiconductor chips with an insulating material so as to form a pseudo-wafer on the support substrate; polishing the pseudo-wafer so as to reduce the thickness of each of the first semiconductor chips; forming an external connection terminal electrically connected to the bump, on the back side of each of the first semiconductor chips; mounting second semiconductor chips on the external connection terminals; removing the support substrate by polishing so as to expose the bumps; and dicing the pseudo-wafer on a chip basis. 
         [0029]    The plurality of first semiconductor chips are produced by dicing the common semiconductor wafer on a chip basis. In view of this, when acceptable chips selected from among the produced individual chips are used as the semiconductor chips to be bump-bonded onto the support substrate, it is possible to contrive an enhanced yield of the semiconductor apparatus manufactured. 
         [0030]    The formation of the vias in the first semiconductor chips can be carried out during or after the thinning step conducted in the condition where the first semiconductor chips are supported by the support substrate. In this case, when the spaces (clearances) between the plurality of first semiconductor chips mounted on the support substrate are filled with an insulating material to obtain the first semiconductor chips in a pseudo-wafer, the plurality of first semiconductor chips can be simultaneously thinned by polishing the pseudo-wafer, and it is possible to contrive an appropriate polishing treatment through maintaining flatness of the polished surface. 
         [0031]    As for the method of forming the vias during the step of thinning the first semiconductor chips, a buried conductor layer electrically connected to the bumps is preliminarily formed at a wafer level stage, and tip port ions of the buried conductor layer are exposed from the back side of the chips at the time of thinning the chips. Then, the terminal surfaces thus exposed are treated, to thereby form the external connection terminals to be joined to the second semiconductor chips on the upper layer side. 
         [0032]    The removal of the support substrate by polishing is carried out after the second semiconductor chips are mounted on the first semiconductor chips. In this case, when the second semiconductor chips are preliminarily sealed with a sealing resin layer, it is possible to stably support the laminate of the first and second semiconductor chips prepared in the form of the pseudo-wafer at the time of polishing. In addition, the joining bumps exposed upon the removal of the support substrate can, as they are, be used as external terminals. 
         [0033]    Thus, according to the substrate treating method according to the one embodiment of the present invention, the supporting of the substrate to be treated by the support substrate and the removal of the support substrate from the substrate to be treated can be carried out appropriately, without using an adhesive necessary for having good temporary fixation performance and good stripping property (removability). 
         [0034]    In addition, according to the method of manufacturing a semiconductor apparatus according to the another embodiment of the present invention, a semiconductor apparatus of the chip-on-chip structure in which the vias (through electrodes) for inter-layer connection can be manufactured with high accuracy and high reliability. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0035]      FIGS. 1A and 1B  are step sectional views for illustrating a method of manufacturing a semiconductor apparatus according to a first embodiment of the present invention; 
           [0036]      FIGS. 1C and 1D  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the first embodiment of the present invention; 
           [0037]      FIGS. 1E and 1F  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the first embodiment of the present invention; 
           [0038]      FIGS. 1G and 1H  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the first embodiment of the present invention; 
           [0039]      FIGS. 1I and 1J  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the first embodiment of the present invention; 
           [0040]      FIGS. 1K and 1L  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the first embodiment of the present invention; 
           [0041]      FIGS. 2A and 2B  are step sectional views for illustrating a method of manufacturing a semiconductor apparatus according to a second embodiment of the present invention; 
           [0042]      FIGS. 2C and 2D  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the second embodiment of the present invention; 
           [0043]      FIGS. 2E and 2F  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the second embodiment of the present invention; 
           [0044]      FIGS. 2G and 2H  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the second embodiment of the present invention; 
           [0045]      FIGS. 2I and 2J  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the second embodiment of the present invention; 
           [0046]      FIGS. 2K and 2L  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the second embodiment of the present invention; 
           [0047]      FIG. 3  is a sectional view schematically showing a configuration example of a semiconductor apparatus of the chip-on-chip structure; 
           [0048]      FIG. 4  is a sectional view schematically showing another configuration example of a semiconductor apparatus of the chip-on-chip structure; 
           [0049]      FIGS. 5A to 5D  are step sectional views for illustrating a method of manufacturing a semiconductor apparatus according to a first related-art example; 
           [0050]      FIGS. 5E to 5G  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the first related-art example; 
           [0051]      FIGS. 5H to 5J  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the first related-art example; 
           [0052]      FIGS. 6A to 6D  are step sectional views for illustrating a method of manufacturing a semiconductor apparatus according to a second related-art example; 
           [0053]      FIGS. 6E to 6G  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the second related-art example; and 
           [0054]      FIGS. 6H and 6I  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus according to the second related-art example. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0055]    Now, some embodiments of the present invention will be described below referring to the drawings. In each of the embodiments below, an example in which the present invention is applied to the manufacture of a semiconductor apparatus of the chip-on-chip structure will be described. 
       First Embodiment  
       [0056]      FIGS. 1A to 1L  are step sectional views for illustrating the method of manufacturing a semiconductor apparatus of the chip-on-chip structure according to a first embodiment of the present invention. 
         [0057]    First, as shown in  FIG. 1A , there is prepared a wafer W 1  in which a device layer  22  including semiconductor devices, such as transistors, wiring  23 , an insulating layer  24 , and the like is formed on the face side of a substrate body (semiconductor substrate)  21  composed of silicon. The wafer W 1  corresponds to the “substrate to be treated” in the embodiment of the present invention. 
         [0058]    A plurality of electrode pads  25  electrically connected to parts of the wiring  23  are disposed on the face side of the device layer  22 , and bumps  27  are formed on the electrode pads  25 . The bumps  27  may be composed, for example, solder bumps, and function as “joining bumps” in the embodiment of the present invention which are joined to a support substrate  29  described later. 
         [0059]    The device layer  22  is preliminarily provided therein with a buried conductor layer  26 P formed of copper, for example. The buried layer  26 P is formed to have a predetermined depth (e.g., 200 μm or less) such as not to penetrate the substrate body  21 , and are electrically connected to the electrode pad  25  (and, hence, to the bumps  27 ) through parts of the wiring  23 . Incidentally, the periphery of the buried conductor layer  26 P is covered with an insulating film formed, for example, of SiO 2 , for electrical insulation from the substrate body  21 . 
         [0060]    Then, as shown in  FIG. 1B , the wafer W 1  is diced on a chip basis, to produce a plurality of semiconductor chips  20 A shown in the figure. The semiconductor chip  20 A corresponds to the “first semiconductor chip” in the embodiment of the present invention. 
         [0061]    Next, as shown in  FIG. 1C , a plurality of the semiconductor chips  20 A produced as above are joined onto the support substrate  29  through the bumps  27 . The support substrate  29  is preliminarily provided with dummy terminals  28  correspondingly to the array pitch of the bumps  27  on the semiconductor chips  20 A, and the bumps  27  are fused to the dummy terminals  28 , whereby the semiconductor chips  20 A are integrally fixed onto the support substrate  29 , with their back side up. The joining of the semiconductor chips  20 A to the support substrate  29  is conducted by the same technique as that of general flip chip bonding, so that this step can be carried out by use of an existing mounter equipment. 
         [0062]    The support substrate  29  is formed of a material having a coefficient of thermal expansion comparable to that of the substrate body  21 , i.e., is composed of a glass substrate, a silicon substrate, or the like. The thickness of the support substrate  29  is not particularly limited. Preferably, however, the support substrate  29  is formed in a thickness on such a level as to secure a rigidity sufficient for handling thereof at the time of thinning a pseudo-wafer, which is obtained by filling the spaces (clearances) between the semiconductor chips  20 A with an insulating material as will be described later. For example, the thickness is not less than 700 μm. 
         [0063]    Subsequently, as shown in  FIG. 1D , the gap between each semiconductor chip  20 A and the support substrate  29  after the flip chip bonding is filled with an underfilling resin, to form an underfill layer  30 . As the underfilling resin, there can be used a thermoplastic resin, such as epoxy resin, which is used for general flip chip bonding. 
         [0064]    Next, as shown in  FIG. 1E , the spaces (clearances) between the semiconductor chips  20 A joined onto the support substrate  29  are filled with an insulating material  31 , to form a pseudo-wafer Wp flattened on the upper side. The pseudo-wafer Wp is formed, for example, by use of a wafer molding technology used for producing a wafer level CSP (Chip Size Package). As the insulating material  31 , a wafer molding resin used for the wafer level CSP or the like is used. 
         [0065]    Since the semiconductor chips  20 A assembled into the pseudo-wafer as above-mentioned can be handled in the wafer state in the subsequent processings, an existing processing equipments can be used as they are. In addition, when acceptable chips selected preliminarily through electrical measurement are used as the semiconductor chips  20 A to be joined to the support substrate  29  and they are assembled into the pseudo-wafer by a wafer molding technology, the pseudo-wafer can be subjected to the subsequent processings as a wafer in which acceptable chips are arranged. This promises an enhanced productivity and an enhanced yield. 
         [0066]    Next, as shown in  FIG. 1F , the pseudo-wafer Wp formed on the support substrate  29  is polished so as to thin the substrate body  21  for each semiconductor chip  20 A, and to expose tip portions  26   a  of the vias  26  (the buried conductor layer  26 P) from the back side of the thinned substrate body  21   t.    
         [0067]    In this step, for example, the substrate body  21  is polished together with the insulating material  31  until the tip portions  26   a  of the vias  26  are exposed from the back side (polished surface) of the substrate body  21 , and thereafter chemical etching is applied to the back side of the substrate body  21   t  so as to protrude the tip portions  26   a  of the vias  26 . In addition, the structure in which the spaces (clearances) between the semiconductor chips  20 A mounted are filled with the insulating material  31  ensures that the polished surface can be kept flat (planar), and the thinning of the plurality of semiconductor chips  20 A can be carried out simultaneously, appropriately, and stably. Incidentally, as the polishing method, any of known polishing technologies such as back grinding (BGR) and chemical mechanical polishing (CMP) can be used either singly or in combination. 
         [0068]    Subsequently, as shown in  FIG. 1G , a predetermined insulating treatment, for example, formation of an insulating film  32 , is applied to the back side of each semiconductor chip  20 A, and external connection terminals  33  are formed on the tip portions  26   a  of the vias  26 . The external connection terminal  33  is electrically connected to the bump  27  through the via  26 , the wiring  23 , and the electrode pad  25 . The formation of the external connection terminals  33  can be carried out by use of a re-wiring technology for wafer level CSP or a wiring technology in semiconductor process. 
         [0069]    Next, as shown in  FIG. 1H , second semiconductor chips  20 B are mounted onto the external connection terminals  33  on the (first) semiconductor chips  20 A. A plurality of bumps  36  are preliminarily formed on the mounting surface of each semiconductor chip  20 B, and the semiconductor chip  20 B is joined onto the external connection terminals  33  by flip flop bonding through the bumps  36 . 
         [0070]    Thereafter, as shown in  FIG. 1I , an underfill layer  34  is formed between the first semiconductor chips  20 A and the second semiconductor chips  20 B which are joined to each other. As the resin material constituting the underfill layer  34 , for example, the same material as that of the underfill layer  30  described referring to  FIG. 1D  above can be used. 
         [0071]    Next, as shown in  FIG. 1J , a sealing layer  35  is formed on the pseudo-wafer Wp, to fill up the spaces (clearances) between the mounted second semiconductor chips  20 B with the resin constituting the sealing layer  35 , whereby the upper surface of the pseudo-wafer Wp is made flat (planar). The sealing layer  35  can be formed, for example, by the wafer molding technology used in the wafer level CSP. As the resin constituting the sealing layer  35 , for example, a molding resin for wafer level CSP can be used. In addition, with the sealing layer  35  thus formed, semiconductor apparatuses having a stack structure of the first and second semiconductor chips  20 A and  20 B can be obtained in the form of pseudo-wafer on the support substrate  29 . Incidentally, the sealing layer  35  may be polished so as to thin the second semiconductor chips  20 B, if necessary. 
         [0072]    Subsequently, as shown in  FIG. 1K , the support substrate  29  is removed from the pseudo-wafer Wp. The removal of the support substrate  29  is carried out by polishing the support substrate  29  by use of BGR or CMP. The step of removing the support substrate  29  is conducted until the bumps  27  of the first semiconductor chips  20 A are exposed from the lower surface of the pseudo-wafer Wp. In this case, since the upper surface of the pseudo-wafer Wp has been made flat (planar) by the presence of the sealing layer  35 , the pseudo-wafer Wp can be supported stably and appropriately by support jigs in a polishing equipment, whereby an appropriate polishing treatment of the support substrate  29  can be promised. 
         [0073]    The bumps  27  can later be used as connection terminals for a mounting substrate (not shown). Besides, since the periphery of each of the bumps  27  is supported by the underfill layer  30 , the step of exposing the bumps  27  during the removal of the support substrate  29  by polishing can be performed appropriately. 
         [0074]    Finally, as shown in  FIG. 1L , the pseudo-wafer Wp deprived of the support substrate  29  is diced on a chip basis, to produce semiconductor apparatuses  20  having a three-dimensional stack structure of the first and second semiconductor chips  20 A and  20 B. 
         [0075]    In the semiconductor apparatus  20 , electrical connection between the second semiconductor chip  20 B and the first semiconductor chip  20 A and electrical connection between the second semiconductor chip  20 B and the bumps  27  are realized through the vias  26  formed in the first semiconductor chip  20 A. Besides, in the semiconductor apparatus  20 , an armor package for protecting the first and second semiconductor chips  20 A and  20 B is composed of both the insulating material  31  covering the periphery of the first semiconductor chip  20 A and the sealing layer  35  covering the periphery of the second semiconductor chip  20 B. 
         [0076]    As has been described above, according to the present embodiment, the joining of the semiconductor chips  20 A to the support substrate  29  is carried out by fusing (fusion bonding) of the joining bumps  27  formed on the semiconductor chips  20 A, and the removal of the support substrate  29  is carried out by polishing of the support substrate  29 . Therefore, the adhesive having good temporary fixation performance and good stripping property (removability) which has been necessary in the related art can be unnecessitated. As a result, processings of the semiconductor chips  20 A can be carried out without being restricted by the heat resisting temperature or chemical resistance of an adhesive, which enables formation of an insulating film  32  excellent in adhesion, for example, and stable patterning ( FIG. 1G ) of the external connection terminals  33 . This ensures that the semiconductor apparatus  20  of the chip-on-chip structure in which the vias  26  for inter-layer connection are formed in the semiconductor chip  20 A on the lower layer side can be manufactured with high accuracy and high reliability. 
         [0077]    In addition, according to this embodiment, the first semiconductor chips  20 A are produced by dicing the common semiconductor wafer W 1  on a chip basis, and acceptable chips selected from among the produced individual chips an be used as the semiconductor chips  20 A bump-bonded onto the support substrate  29 . Therefore, it is possible to manufacture the semiconductor apparatus  20  in an enhanced yield. 
       Second Embodiment  
       [0078]    Now, a second embodiment of the present invention will be described below. 
         [0079]      FIGS. 2A to 2L  are step sectional views for illustrating a method of manufacturing a semiconductor apparatus of the chip-on-chip structure according to the second embodiment of the present invention. Incidentally, in the figures, the portions corresponding to those in the first embodiment above are denoted by the same symbols as used above, and detailed descriptions of these portions will be omitted. 
         [0080]    First, as shown in  FIG. 2A , there is prepared a wafer W 2  in which a device layer  22  including semiconductor devices, such as transistors, wiring  23 , an insulating layer  24 , and the like is formed on the face side of a substrate body (semiconductor substrate)  21  composed of silicon. A plurality of electrode pads  25  electrically connected to parts of the wiring  23  are disposed on the face side of the device layer  22 , and bumps  27  are formed on the electrode pads  25 . Then, the wafer W 2  is diced on a chip basis, to produce first semiconductor chips  20 C. 
         [0081]    Here, the wafer W 2  in this embodiment differs from the wafer W 1  in the first embodiment above in that the buried conductor layer for forming the vias (through electrodes) is not formed in the inside of the substrate, and vias (through electrodes)  26  are separately formed after the step of thinning the semiconductor chips  20 C described later ( FIG. 2G ). 
         [0082]    Next, as shown in  FIG. 2C , the plurality of semiconductor chips  20 C thus produced are joined onto a support substrate  29  through the bumps  27 . The support substrate  29  is preliminarily provided with dummy terminals  28  correspondingly to the array pitch of the bumps  27  on the semiconductor chips  20 C, and the bumps  27  are fused (fusion-bonded) to the dummy terminals  28 , whereby the semiconductor chips  20 C are integrally fixed onto the support substrate  29 , with their back side up. 
         [0083]    Subsequently, as shown in  FIG. 2D , the gap between each of the flip chip bonded semiconductor chips  20 C and the support substrate  29  is filled with an underfilling resin, to form an underfill layer  30 . Next, as shown in  FIG. 2E , the spaces between the mounted semiconductor chips  20 C joined onto the support substrate  29  are filled with an insulating material  31 , to form a pseudo-wafer Wp of which the upper surface is made flat (planar). 
         [0084]    With the semiconductor chips  20 C thus obtained in the pseudo-wafer, they can be handled in the wafer state in the subsequent processings, so that existing processing equipments can be used as they are. In addition, when acceptable chips preliminarily selected through electrical measurement are used as the semiconductor chips  20 C to be joined to the support substrate  29  and the pseudo-wafer is obtained by a wafer molding technology, the pseudo-wafer can be subjected to the subsequent processings as a wafer in which acceptable chips are arranged. This promises an enhanced productivity and an enhanced yield. 
         [0085]    Next, as shown in  FIG. 2F , the pseudo-wafer Wp formed on the support substrate  29  is polished, to thin the substrate body  21  of each of the semiconductor chips  20 C. Then, as shown in  FIG. 2G , vias (through electrodes)  26  penetrating the thinned substrate body  21   t  and connected to the predetermined wiring  23  at ends thereof are formed from the back side of the substrate body  21   t . The vias  26  can be formed by a method in which inter-layer contact holes are formed by a dry process such as plasma etching, and thereafter insulation of the inside wall surfaces of the holes and formation of conductor platings of copper or the like are carried out. Further, a predetermined insulating treatment such as forming of an insulating film  32  is applied to the back side of the semiconductor chips  20 C, and external connection terminals  33  are formed on tip portions of the vias  26 . The external connection terminal  33  is electrically connected to the bump  27  through the via  26 , the wiring  23 , and the electrode pad  25 . 
         [0086]    Next, as shown in  FIG. 2H , second semiconductor chips  20 B are mounted onto the external connection terminals  33  on the (first) semiconductor chips  20 C. A plurality of bumps  36  are preliminarily formed on the mounting surface of each semiconductor chip  20 B, and the semiconductor chip  20 B is joined onto the external connection terminal  33  by flip chip bonding through the bumps  36 . Thereafter, as shown in  FIG. 2I , an underfill layer  34  is formed between the first semiconductor chip  20 C and the second semiconductor chip  20 B joined to each other. 
         [0087]    Next, as shown in  FIG. 2J , a sealing layer  35  is formed on the pseudo-wafer Wp, and the spaces between the mounted second semiconductor chips  20 B are filled with a resin constituting the sealing layer  35 , whereby the upper surface of the pseudo-wafer Wp is made flat (planar). With the sealing layer  35  thus formed, semiconductor apparatuses of the stack structure of the first and second semiconductor chips  20 C and  20 B can be assembled in the form of a pseudo-wafer on the support substrate  29 . Incidentally, the sealing layer  29  may be polished so as to thin the second semiconductor chips  20 B, if necessary. 
         [0088]    Subsequently, as shown in  FIG. 2K , the support substrate  29  is removed from the pseudo-wafer Wp. The removal of the support substrate  29  is carried out by polishing the support substrate  29  by use of the BGR or CMP technology. The step of removing the support substrate  29  is conducted until the bumps  27  of the first semiconductor chips  20 C are exposed from the lower surface of the pseudo-wafer Wp. In this case, since the upper surface of the pseudo-wafer Wp is made flat (planar) by the presence of the sealing layer  35 , the pseudo-wafer Wp can be supported stably and appropriately by supporting jigs in a polishing equipment, which promises appropriate polishing of the support substrate  29 . 
         [0089]    The bumps  27  can later be used as connection terminals for a mounting substrate (not shown). In addition, since the periphery of each of the bumps  27  is supported by the underfill layer  30 , the step of exposing the bumps  27  during the removal of the support substrate  29  can be carried out appropriately. 
         [0090]    Finally, as shown in  FIG. 2L , the pseudo-wafer Wp deprived of the support substrate  29  is diced on a chip basis, to produce semiconductor apparatuses of a three-dimensional stack structure of the first and second semiconductor chips  20 C and  20 B. In the semiconductor apparatus  20 , electrical connection between the second semiconductor chip  20 B and the first semiconductor chip  20 C and electrical connection between the second semiconductor chip  20 B and the bumps  27  are realized through the vias  26  formed in the first semiconductor chip  20 C. Besides, in the semiconductor apparatus  20 , an armor package for protecting the first and second semiconductor chips  20 C and  20 B is composed of both the insulating material  31  covering the periphery of the first semiconductor chip  20 C and the sealing layer  35  covering the periphery of the second semiconductor chip  20 B. 
         [0091]    By the method of manufacturing a semiconductor apparatus  20  according to this embodiment, also, the same effects as those of the first embodiment above can be obtained. 
         [0092]    While the embodiments of the present invention have been described above, the invention naturally is not limited to the embodiments, and various modifications are possible based on the technical thought of the invention. 
         [0093]    For example, while an example in which the present invention is applied to the manufacture of a semiconductor apparatus  20  of the chip-on-chip structure has been described in the above embodiments, the invention is not limited to the example. The invention applicable also to a step of thinning a substrate to be treated on a wafer level by back grinding, a step of mounting devices onto the substrate to be treated, and the like steps. 
         [0094]    Besides, while the manufacture of a semiconductor apparatus in which first and second semiconductor chips are stacked has been described as an example in the above embodiments, the number of semiconductor chips stacked may be further increased. In that case, vias (through electrodes) for inter-layer connection formed for a semiconductor chip on the lower layer side can be formed in the same manner as in the above embodiment. 
         [0095]    It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alternations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalent thereof.