Abstract:
An electrostatic discharge (ESD) protection circuit is disclosed for preventing a pad-to-pad ESD charge. The protection circuit for each pad of an integrated circuit comprises a current dissipation module with an N-type MOSFET connected in parallel with a bipolar junction transistor (BJT) wherein the drain of the MOSFET and the collector of the BJT are connected to a first common node and the source of the MOSFET and the emitter of the BJT are connected to a second common node connectable to a second operating voltage. A diode string is connected to a first pad at its anode end having a total forward voltage drop more than a first operating voltage and with its cathode end connected to the body of the MOSFET, the base of the BJT, and to the second common node through a resistor.

Description:
BACKGROUND OF THE DISCLOSURE  
       [0001]     The present disclosure relates generally to integrated circuit (IC) design, and more particularly to a method for protecting the core circuitry of an integrated circuit (IC) from damage that may be caused by electrostatic discharge (ESD). A gate oxide of any metal-oxide-semiconductor (MOS) transistor, in an integrated circuit, is most susceptible to damage. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than operating voltage. It is understood that a regular operating voltage is 5.0, 3.3, 3.1 volts, or lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current are extremely small. So, it is of critical importance to discharge any static electric charge, as it builds up, before it accumulates to a damaging voltage.  
         [0002]     ESD is only a concern to an integrated circuit before it is installed into larger circuit assembly, such as a printed circuit board (PCB), and before the PCB is connected to an operating power. This susceptible period includes production, storage, transport, handling, and installation. After the power is supplied, the power supplies and the structures can easily absorb or dissipate electrostatic charges.  
         [0003]     ESD protection circuitry is typically added to ICs at the bond pads. The pads are the connections to the IC, to or from outside circuitry, for all electric power supplies, electric grounds, and electronic signals. Such added circuitry must allow normal operation of the IC. That means that the protection circuitry is effectively isolated from the normally operating core circuitry because it blocks current flow through itself to ground or any other circuit or pad. In an operating IC, electric power is supplied to a VCC pad, electric ground is supplied to a VSS pad, electronic signals are supplied from outside to some pads, and electronic signals generated by the core circuitry of the IC are supplied to other pads for delivery to external circuits and devices. In an isolated, unconnected, IC, all pads are considered to be electrically floating, or of indeterminant voltage. In most cases, that means that the pads are at ground, or zero voltage.  
         [0004]     ESD can arrive at any pad. This can happen, for example, when a person touches some of the pads on the IC. This is the same static electricity that may be painfully experienced by a person who walks across a carpet on a dry day and then touches a grounded metal object. In an isolated IC, ESD acts as a brief power supply for one or more pads, while the other pads remain floating, or grounded. Because the other pads are grounded, when ESD acts as a power supply at a randomly selected pad, the protection circuitry acts differently than it does when the IC is operating normally. When an ESD event occurs, the protection circuitry must quickly become current conductive so that the electrostatic charge is conducted to VSS ground and thus dissipated before damaging voltage builds up.  
         [0005]     ESD protection circuitry, therefore, has two states. In a normally operating IC, ESD protection circuitry appears invisible to the IC by blocking current through itself and thus having no effect on the IC. In an isolated, unconnected IC, ESD protection circuitry serves its purpose of protecting the IC by conducting an electrostatic charge quickly to VSS ground before a damaging voltage can build up. What is needed is an improved ESD protection circuit.  
       SUMMARY OF THE DISCLOSURE  
       [0006]     An electrostatic discharge (ESD) protection circuit is disclosed for preventing a pad-to-pad ESD charge. The protection circuit for each pad of an integrated circuit comprises a current dissipation module with an N-type MOSFET connected in parallel with a bipolar junction transistor (BJT) wherein the drain of the MOSFET and the collector of the BJT are connected to a first common node and the source of the MOSFET and the emitter of the BJT are connected to a second common node connectable to a second operating voltage. A diode string is connected to a first pad at its anode end having a total forward voltage drop more than a first operating voltage and with its cathode end connected to the body of the MOSFET, the base of the BJT, and to the second common node through a resistor. When the ESD charge causes a voltage on the first pad to surpass the total forward voltage drop of the diode string, the ESD charge injects a direct current to the base of the BJT so as to enhance the dissipation of the ESD charge and wherein the diode string keeps the voltage on the first pad between the first and second operating voltages.  
         [0007]     Various aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the disclosure.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1A  illustrates an electrostatic discharge protection circuitry in accordance with a first example of the present disclosure.  
         [0009]      FIG. 1B  illustrates an example of electric current pathway in accordance with the first example of the present disclosure.  
         [0010]      FIG. 2  illustrates a current-voltage graph in accordance with one example of the present disclosure.  
         [0011]      FIG. 3A  illustrates an electrostatic discharge protection circuitry in accordance with a second example of the present disclosure.  
         [0012]      FIG. 3B  illustrates an example of electric current pathway in accordance with the second example of the present disclosure. 
     
    
     DETAILED DESCRIPTION  
       [0013]     The present disclosure provides an IC with an ESD protection circuitry that is inert during normal operation of the IC and active when the IC is unconnected. The ESD protection circuitry acts, by means of a diode string, to clamp a positive ESD charge on a bondpad to a voltage just above an operating voltage VDD and to switch on a parallel combination of an N-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET) and a bipolar transistor to dissipate the charge harmlessly. The bipolar transistor may be parasitic or constructed. The drive for the dissipating transistors lowers the threshold voltage and the snapback voltage. Two examples of the application of the diode string are presented.  
         [0014]     In a first example, as illustrated in  FIG. 1A , an electrostatic discharge (ESD) protection circuit  100  is connected to a bondpad, or pad  102 , of an integrated circuit (IC). In a typical circuit, such a pad may be connected to an external electric power supply VDD, an external electric ground VSS, an external electronic input signal source, or an internal electronic output signal source. Here, VDD is shown to be supplied internally from another source, and VSS is shown to be supplied internally to five locations from another source. The IC is susceptible to electrostatic discharge damage before it is installed into a larger circuit assembly, such as a printed circuit board (PCB), and before the PCB is connected to operating power. This susceptible period includes production, storage, transport, handling, and installation. ESD protection circuitry is connected to each pad. In an isolated, unconnected IC, all pads are considered to be at ground or VSS voltage level.  
         [0015]     The anode of a diode  104  is connected to pad  102 . The cathode of diode  104  is connected to the drain  106  of an N-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET)  108 , to the drain  110  of a P-channel metal-oxide-semiconductor field-effect-transistor (PMOSFET)  112 , and to VDD. A resistor  114  is connected between VDD and an NMOS capacitor  116  to form a RC module  117 . The other side of NMOS capacitor  116  is connected to VSS. A connection runs from a node  118  between the resistor  114  and the NMOS capacitor  116  to the gate  120  of PMOSFET  112  and to the gate  122  of an NMOSFET  124 . Together, PMOSFET  112  and NMOSFET  124  form a complementary MOS (CMOS) inverter  125 , with the drain  126  of NMOSFET  124  connected to the source  128  of PMOSFET  112  and the source  130  of NMOSFET  124  connected to VSS. From a node  132  between PMOSFET  112  and NMOSFET  124 , a connection runs to the gate  134  of NMOSFET  108 . The source  136  of NMOSFET  108  is connected to VSS. Pad  102  is also connected to a diode string  137  having a plurality of diodes connected in series. For example, the cathode of diode  138  is connected to the anode of a diode  140 , the cathode of diode  140  is connected to the anode of a diode  142 , and the cathode of diode  142  is connected to a node  144  and to the body  146  of NMOSFET  108 . Three diodes are shown in the string as one example, but there can be any number of diodes connected in series as long as the diode string serves the purpose of clamping the ESD. A resistor  148  is connected between the cathode of diode  142  and VSS. A bipolar transistor  150  is connected in parallel with NMOS  108  so that the emitter, base, and collector of bipolar transistor  150  are connected respectively to source  136 , body  146 , and drain  106  of NMOSFET  108 . The bipolar function can be performed by either an inherent parasitic bipolar transistor or an actual bipolar transistor constructed by any well-known technology. In addition, the cathode of a diode  152  is connected to pad  102 , and the anode is connected to VSS.  
         [0016]     In operation, pad  102  is a part of an IC such as a VDD, VSS, or an input or an output pin that varies in a voltage range between VDD and VSS. Since the voltage at pad  102  does not rise above VDD or fall below VSS, diode  104 , connected between pad  102  and VDD, and diode  152 , connected between pad  102  and VSS, do not conduct. After starting up the IC, node  118  is charged to VDD and no current flows through resistor  114 . So, voltage VDD is delivered to the gate  120  of PMOSFET  112  and the gate  122  of NMOSFET  124  in the inverter. Therefore, VSS is delivered to the gate  134  of NMOSFET  108 , and NMOSFET  108  is always turned off. Body  146  may receive influence from the pad  102  through the diode string  137 . The diode count is chosen such that the sum of the forward voltage drops across all the diodes is just larger than VDD. The minimum number of diodes necessary is selected such that the protection function will commence before any damage occurs. Therefore, no signal from the pad within the normal voltage range between VDD and VSS reaches the body  146  of NMOSFET  108 , and NMOSFET  108  remains off at all times in normal operation. NMOSFET  108  is designed to conduct electrostatic charges to ground VSS when challenged by a positive ESD. However, in normal operation, both the gate  134  input and the body  146  input hold NMOSFET  108  securely off so that it has no effect on the normal operation of the IC.  
         [0017]     When a positive ESD arrives at a randomly selected pad  102 , the ESD acts as a power supply applying positive voltage to that pad. When the voltage suddenly begins to rise at pad  102 , current flows through diode  104  as the voltage rises above the forward voltage drop of diode  104  and that current begins to charge the drain  106  of NMOSFET  108 , the drain  110  of PMOSFET  112 , and the node that is VDD in normal operation. Current begins to flow through resistor  114  so that the voltage at node  118  begins to rise. As node  118  is still at a relatively low value, the inverter output voltage at node  132  is nearly as high as the drain  106  of NMOSFET  108 . So NMOSFET  108  is driven into conduction almost immediately, and the ESD charge starts to dissipate through NMOSFET  108  to VSS. Also, as the ESD voltage at pad  102  rises above VDD, the voltage almost immediately surpasses the sum of the forward drops of the diode string and current begins to flow through the diode string  137  to the body of NMOSFET  108  and through resistor  148  to VSS. The current through resistor  148  builds a voltage at node  144 , which sustains the current into the body  146  of NMOSFET  108 . That current into the body of NMOSFET  108  acts as a base current for bipolar transistor  150 . Therefore, bipolar transistor  150  is also driven into conduction almost immediately, conducting a current I ce , which is a multiple (beta) of the base current. This is effective whether this is the inherent parasitic bipolar transistor or an actual constructed bipolar transistor. This adds to the dissipation of the ESD charge to VSS. Now, both NMOSFET  108  and bipolar transistor  150  are dissipating static charge. This continues until the voltage at node  118  reaches a switching threshold of the inverter  125 . Then the inverter switches off NMOSFET  108 . If ESD voltage is still rising at pad  102 , then the current is still supplied through the diode string  137  to drive bipolar transistor  150 , which continues to dissipate any remaining ESD charge to VSS so that the voltage at pad  102  remains clamped at or below the sum of the forward diode voltage drops of the diode string. The ESD charge is thus dissipated to VSS while the voltage at pad  102  is clamped to a value, only slightly above VDD, which is safe for the core circuitry of the IC. In short, the ESD charge dissipates from pad  102  through diode  104  and through the parallel combination of NMOS  108  and bipolar transistor  150  through VSS to ground.  
         [0018]      FIG. 1B  illustrates electric current pathways when a positive ESD arrives at the pad  102  in accordance with the first example of the present disclosure. With reference to both  FIGS. 1A and 1B ,  FIG. 1B  includes two ESD protection circuits  100 , the top circuit of which is zapped by a positive ESD. The pad of the bottom circuit is connected to ground. If the pad of the top circuit is not connected to ground, the ESD charge is first dissipated to a VSS connection of the top circuit, as represented by pathways  154  and  155 . Since the VSS connection of the top circuit is commonly connected, as represented by a common connection  156 , to a VSS connection of the bottom circuit, whose pad is connected to ground, the ESD charge will travel from the VSS connections of the top circuit to the VSS of the bottom circuit. The ESD charge then travels through a pathway  158  via the diode  152  before it is finally dissipated through ground.  
         [0019]     When a negative ESD arrives at the randomly selected pad  102 , the negative voltage can only build up to the forward voltage drop across diode  152 . Negative static charge is dissipated at this low voltage to VSS through diode  152 . The core circuitry of the IC is thus easily protected.  
         [0020]      FIG. 2  presents a current-voltage graph that illustrates the benefit of the positive triggering base current from pad  102  in the case of a positive ESD. The vertical axis, I ce , is the collector-to-emitter current of the bipolar transistor  150 , whereas the horizontal axis, V ce , is the collector-to-emitter voltage. The triggering base current arrives from pad  102 , through diodes  138 ,  140  and  142  to the node  144  and the body  146  of NMOSFET  108 . The body  146  of NMOSFET  108  is also the base of bipolar transistor  150 . The dissipation current, or Id, that is the triggering base current multiplied by beta, is higher than a dissipation current that is attained in a conventional design without the diode string triggering. Therefore, the triggering base current drives the bipolar transistor  150  hard enough such that the threshold voltage is lowered from Vt to Vt′, while the snapback voltage is lowered from Vs to Vs′, thereby allowing a more efficient dissipation of the ESD charge.  
         [0021]     In a second example as illustrated in  FIG. 3A , the ESD protection circuitry is constructed of the same components as in  FIG. 1A . However, in  FIG. 3A , the diode string  137  from the bondpad or pad  102  is connected to node  132  at the gate  134  of NMOSFET  108 , instead of to the body  146  of NMOSFET  108 . Current through the diode string  137  that results from a positive ESD is not available to drive bipolar transistor  150 . Instead, the positive ESD charge at pad  102  drives a current through the diode string  137  to charge the capacitance of the gate  134  of NMOSFET  108 . Once NMOSFET  108  is turned on, the ESD charge will dissipate through NMOSFET  108  to VSS. Concurrently, positive charge at the gate  134  of NMOSFET  108  will induce a hole current into the body  146 , thereby causing a gate current which triggers a much larger current I ce  through the collector and emitter of the bipolar transistor  150 , thereby further dissipating the ESD charge. Therefore, the ESD charge dissipates from pad  102  through diode  104  and through a combination of NMOSFET  108  and bipolar transistor  150  to VSS, which may further be grounded as shown in  FIG. 1B .  
         [0022]     When a negative ESD arrives at pad  102 , the negative voltage can only build up to the forward voltage drop across diode  152 . The operation is the same as in the first example. Negative static charge is dissipated at this low voltage to ground VSS through diode  152 . The core circuitry of the IC is thus easily protected. The ESD charge dissipates from pad  102  through diode  152  to ground VSS.  
         [0023]     Although the positive triggering current from pad  102  is connected to the node  132  at the gate  134  of NMOSFET  108 , there is still a benefit of lowering both the threshold voltage and the snapback voltage because gate  134  is still now driven harder. This effect is similar to the situation as illustrated in  FIG. 2 .  
         [0024]      FIG. 3B  illustrates an electric current pathway when a positive ESD arrives at the pad  102  in accordance with the second example of the present disclosure. With reference to both  FIGS. 3A and 3B ,  FIG. 3B  includes two ESD protection circuits  300 , the top circuit of which is zapped by a positive ESD. The pad of the bottom circuit is connected to ground. If the pad of the top circuit is not connected to ground, the ESD charge is first dissipated to a VSS connection of the top circuit, as represented by a pathway  302 . Since the VSS connection of the top circuit is commonly connected, as represented by a common connection  304 , to a VSS connection of the bottom circuit, whose pad is connected to ground, the ESD charge will travel from the VSS of the top circuit to the VSS of the bottom circuit. The ESD charge then travels through a pathway  306  via the diode  152  before it is finally dissipated to ground.  
         [0025]     The above disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components, and processes are described to help clarify the invention. These are, of course, merely examples and are not intended to limit the invention from that described in the claims.  
         [0026]     While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention, as set forth in the following claims.