Abstract:
Embodiments of DC power related systems and methods including a topology and devices to enable DC powered or driven constant current devices to be connected in a parallel configuration while maintaining a series connection internal to the devices.

Description:
TECHNICAL FIELD 
     Various embodiments described herein relate to direct current (DC) topologies having an AC or DC source and related devices. 
     BACKGROUND INFORMATION 
     In order to reduce wiring costs and ease installation it may be desirable to connect one or more DC powered or driven devices in a series string that is powered from a single source. The present invention provides a topology and devices to enable DC powered or driven constant current devices to be connected in a parallel configuration while maintaining a series connection internal to the devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a parallel coupled DC driven systems architecture according to various embodiments. 
         FIG. 2  is a block diagram of a parallel DC system according to various embodiments. 
         FIG. 3  is a block diagram of a DC driven or powered device or fixture according to various embodiments. 
         FIG. 4  is a block diagram of a parallel DC power system interface according to various embodiments. 
         FIG. 5  is a block diagram of a parallel DC power system interface according to various embodiments. 
         FIG. 6  is a block diagram of another parallel DC power system interface according to various embodiments. 
         FIG. 7  is a block diagram of another parallel DC power system interface according to various embodiments. 
         FIG. 8  is a block diagram of another parallel DC power system interface according to various embodiments. 
         FIG. 9A  is a block diagram of an open circuit detector according to various embodiments. 
         FIG. 9B  is a block diagram of another open circuit detector according to various embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of AC or DC powered topology-DC output architecture  10  that includes several parallel DC systems  14 A,  14 B,  14 C and a constant or variable direct current (DC) driver  12 . In an embodiment each parallel DC system  14 A,  14 B,  14 C may be electrically coupled in parallel to the constant or variable DC driver  12 . The power source  21  may provide alternating current (AC) power or DC power to the constant or variable DC driver  12  via lines  20 A,  20 B. The driver  12  may provide the first DC device  14 A direct current power via lines  22 A,  22 B. 
     In an embodiment each parallel DC system may provide DC power to a coupled DC driven device  60  ( FIG. 2 ) and two lines  22 C,  22 D where another parallel DC system  14 B,  14 C or final feedback loop  24  ( FIG. 1 ) may be coupled to the lines  22 C,  22 D. The parallel DC systems  14 A,  14 B,  14 C create a serial coupling between each respective DC driven device  60  while having a user perceived parallel coupling,  22 C,  22 D,  22 E,  22 F where lines  22 A,  22 C,  22 E provide a serial path between respective DC driven device  60  (for each system  14 A,  14 B,  14 C) and line  24 ,  22 F,  22 D, and  22 B complete the serial path to the DC driver  12 . 
     In an embodiment a DC driven device  60  may be a solid state lighting (SSL) fixture  70  ( FIG. 3 ). The SSL fixture  70  may include one or more Light Emitting Diodes (LED)  74 A,  74 B,  74 C, electro-luminance (EL), or other low voltage DC lighting device. An LED fixture may include an LED lighting strip, lighting tile, lighting unit, module, array, channel letter sign kit, channel light, border light kit, channel letter lighting system, border tube kit, Class 2 lighting system, Class 2 lighting assembly, Class 2 lighting strip, Class 2 illumination module, or Class 2 fixture. 
     In an embodiment the DC driver  12  may be an alternating current (AC) to DC converter. The DC driver  12  may receive the AC signal  21  and generate a constant DC current-limited, a constant voltage-limited signal, or a power-limited DC signal on lines  22 A,  22 B for one or more parallel DC systems  14 A,  14 B,  14 C. In an embodiment the DC driver  12  circuitry may generate a Class 1 signal or Class 2 signal as defined by the National Electric Code (NEC) Article 725. 
     As defined by the NEC, Article 725, a Class 1 limited-power source circuit is limited to 30 volts and 1,000 volt-amperes and a Class 2 limited-power source circuit is limited to 30 volts, 100 volt-amperes, and 8 amperes. It is noted that Class 2 circuits are not considered a danger to personnel and may not require an electrician to install wiring between Class 2 limited-power source circuit and a device, e.g., parallel DC systems  14 A,  14 B,  14 C as a function of the DC driver  12  classification. 
     In an embodiment the DC driver  12  may be at large distance from the first parallel DC system  14 A, up to a first maximum predetermined distance apart. Similarly a parallel DC system  14 A,  14 B,  14 C may be located at large distance from the next parallel DC system  14 A,  14 B,  14 C, in an embodiment up to a second, shorter maximum predetermined distance apart. Accordingly a first parallel DC system  14 A,  14 B,  14 C may be located at a central location relative to other parallel DC systems  14 A,  14 B,  14 C and the DC driver  12 . The DC driver  12  may also conform to other standards. In an embodiment the DC driver  12  maximum volt-amperes output level may be at least twice a parallel DC system  14 A,  14 B,  14 C maximum volt-amperes output level. 
       FIG. 2  is a block diagram of a parallel DC system  14 A,  14 B,  14 C according to various embodiments. The system  14 A,  14 B,  14 C may include a polarity converter and controller  30  and a DC power driven device  60 . The polarity converter and controller  30  may receive a positive DC signal on either  22 A,  22 B and couples the power to line  22 C,  22 D. The polarity converter and controller  30  may feed the DC signal to the DC power driven device  60  via lines  16 A and  16 B and ensures that the polarity is in the proper direction, regardless of the input power polarity. The polarity converter and controller  30  may also include an open circuit detector  50  ( FIG. 4 ) where the open circuit detector  50  may bypass the DC power driven device  60  when an open circuit is detected. 
     In an embodiment the polarity converter and controller  30  may enable a parallel DC system user or installer to connect either  22 C or  22 D to either connection of a parallel DC system  14 B. In such an embodiment the parallel DC system  14 A,  14 B,  14 C may be coupled by an installer or user without polarity consideration or determination similar to common AC power driven devices or apparatus. The open circuit detector  50  ensures that a DC power driven device  60  failure in a parallel DC system  14 A,  14 B,  14 C of architecture  10  does not cause other parallel DC systems  14 A,  14 B,  14 C to be effected. 
       FIG. 3  is a block diagram of a DC driven or powered device or fixture  70  according to various embodiments. The fixture  70  may be a solid state lighting (SSL) fixture  70 . The SSL fixture  70  includes Light Emitting Diodes (LED)  74 A,  74 B,  74 C and a printed circuit board (PCB)  72 . The LEDs  74 A,  74 B,  74 C may be electrically coupled to the PCB  72 . The PCB  72  may receive a DC power signal on lines  16 A,  16 B and supply a conditioned signal to each LED  74 A,  74 B,  74 C. The SSL fixture  70  may include an LED lighting strip, lighting tile, lighting unit, module, array, channel letter sign kit, channel light, border light kit, channel letter lighting system, border tube kit, Class 2 lighting system, Class 2 lighting assembly, Class 2 lighting strip, Class 2 illumination module, or Class 2 fixture. 
       FIG. 4  is a block diagram of a parallel polarity converter and controller  30  according to various embodiments. The polarity converter and controller  30  may include a polarity converter or module  40  and an open circuit detector or module  50 . The polarity converter  40  may switch or change the polarity of a received DC signal as necessary. The polarity converter  40  may receive a positive DC signal on either  22 A,  22 B and ensure that the proper polarity DC signal is coupled to the DC power driven device  60  via lines  16 A and  16 B. The polarity converter  40  may feed the DC signal to lines  22 C,  22 D for connection to another parallel DC system,  14 A,  14 B,  14 C. The open circuit detector  50  may bypass a coupled DC power driven device  60  when an open circuit is detected. 
       FIG. 5  is a block diagram of a polarity converter and controller  30  according to various embodiments. The polarity converter and controller  30  may include a switch-polarity converter or module  80 , a controller  90 , and an open circuit detector or module  50 . The controller  90  may determine whether the polarity is reversed and direct the operation of one or more switches of the switch—polarity converter  80  accordingly. The switch-polarity converter  80  may switch or change the polarity of a received DC signal as directed by the controller  90 . The switch-polarity converter  80  may receive a positive DC signal on either  22 A,  22 B and ensure that the proper polarity DC signal is coupled to the DC power driven device  60  via lines  16 A and  16 B. The switch-polarity converter  80  may feed the DC signal to lines  22 C,  22 D for connection to another parallel DC system,  14 A,  14 B,  14 C. The open circuit detector  50  may bypass a coupled DC power driven device  60  when an open circuit is detected. 
       FIG. 6  is a block diagram of another parallel DC power interface  100  according to various embodiments. As shown in  FIG. 6  the interface  100  includes a relay coil,  112  with two sets of contacts,  116 ,  118 , a relay controller  110 , a diode  114 , and an open circuit detector  50 . In operation the open circuit detector  50  is normally open unless an open circuit is detected across lines  16 A,  16 B and then the open circuit detector  50  forms a signal path between  22 A and  22 C to bypass lines  16 A,  16 B. 
     In an embodiment the relay contacts  116 ,  118  are double pole-double throw contacts and are shown in a normally closed state where a positive DC signal is provided to line  22 A and passed to a device  60  via lines  16 A,  16 B and then to  22 C when the device  60  is not open circuited. In such a state a voltage developed across a device  60  coupled to lines  16 A,  16 B, and through the normally closed contacts of  116 ,  118  is applied to the open circuit detector module  50  and across the series string of the diode  114 , relay coil  112 , and relay controller module  110 . 
     When the polarity of an applied voltage provides a positive polarity DC signal on line  22 A the diode  114  is reverse biased and accordingly no voltage is developed across the relay coil  112 . In such a condition and in an embodiment relay contacts  116 ,  118  remain in their normally closed state (since the relay coil  112  is not energized). Accordingly, current may flow from line  22 A through the normally closed relay  118  contact, to a DC device coupled to lines  16 A,  16 B, through the normally closed relay contact  116  and to line  22 C. For the last parallel DC device  14 A,  14 B,  14 C, a jumper  24  ( FIG. 1 ) may be coupled to lines  22 C,  22 D. In such an embodiment current may be returned to input line  22 B to complete a circuit. 
     In the condition where a negative DC signal is applied at input terminal or line  22 A with respect to input terminal or line  22 B, diode  114  may be forward biased and the relay coil  112  may be energized. In an embodiment the relay contacts  118 ,  116  may switch to the normally open position. In this manner, the positive DC signal becomes connected from input line  22 B, through the line  22 D and through a jumper  24  (at the last parallel DC device  14 C) to line or terminal  22 C. In such an embodiment the positive DC voltage is connected to the normally open position of contacts  118  to line  16 A and to the anode of a device  60  coupled to line  16 A,  16 B. The current may propagate through the device  60 , and the normally open position of contacts  116  via line  16 B back to the input line or terminal  22 A. Accordingly the interface  100  may ensure that a DC voltage of the appropriate polarity is always applied to a device  60  connected to lines  16 A,  16 B. 
     In the interface  100  embodiment when a desired polarity DC voltage is applied to lines  22 A,  22 B, a reverse DC voltage condition may never exist across lines  16 A,  16 B since the normally closed contacts of  116 ,  118  are connected. When a reverse polarity DC signal is applied to lines  22 A,  22 B, the relay coil  112  needs to energize before the contacts  116 ,  118  switch to the normally open position and apply the correct polarity across lines  16 A,  16 B. The relay coil  112  may energize in about or less than 20 ms. During this time, the polarity of the connection to lines  16 A,  16 B may not be correct. Once the relay is energized and the contacts have changed state, the correct voltage will be applied to lines  16 A,  16 B. Also the relay coil (when energized) reduces the current applied to a device  60  on lines  16 A,  16 B. In an embodiment a balancing load may be added to the interface  1000  to provide a constant load regardless of the applied polarity. Further as the device&#39;s  60  load or resistance changes, the relay coil  112  resistance may also change. The interface  100  may also have losses on the order of 0.3 W and an efficiency of about 97% for a 10 watt device  60 . 
       FIG. 7  is a block diagram of another parallel DC power interface  120  according to various embodiments. As shown in  FIG. 7  the interface  120  includes a relay  112  with a single set of contacts  118 , a relay controller  110 , a diode  114 , a second relay  132  with a single set of contacts  116 , a second relay controller  130 , a second diode  134 , and an open circuit detector  50 . In operation the open circuit detector  50  is normally open unless an open circuit is detected across lines  16 A,  16 B and then the open circuit detector  50  forms a signal path between  22 A and  22 B to bypass lines  16 A,  16 B. Interface  120  operates similarly to interface  100  in an embodiment but further includes the second relay controller  130 , the second diode  134 , the second relay  132 , with the contacts  116  connected to the normally open position. Accordingly, either the relay coil  112  or relay coil  132  will energize to complete a circuit as a function of the applied DC voltage signal polarity applied to lines  22 A,  22 B. 
     Interface  120  may not apply a reverse polarity signal to a device  60  coupled to lines  16 A,  16 B due to the additional relay coil  132  and the connection to the normally open contact  116 . In the interface  120  embodiment a balancing load is not needed since a relay coil  112  or relay coil  132  will always be energized. As the device&#39;s  60  load or resistance changes, the relay coil  112  or  132  resistance may also change. The interface  70  may also have losses on the order of 0.3 W and an efficiency of about 97% for a 10 watt device  60 . 
       FIG. 8  is a block diagram of another parallel DC power interface  140  according to various embodiments. The interface  140  includes an open circuit detector  50 , first switching circuit  150 , and second switching circuit  160 . The circuit  150  performs the effective function of relay  118 , relay coil  112 , and diode  114  and circuit  160  performs the effective function of relay  116 , relay coil  132 , and diode  134 . The circuit  150  includes three MOSFETs  142 A,  142 B,  142 C, a diode  146 , and several resistors  144 A to  144 E. The circuit  160  also includes three MOSFETs  162 A,  162 B,  162 C, a diode  166 , and several resistors  164 A to  164 E. The interface  140  has insignificant current loses compared to interfaces  100 ,  120 . 
     Similar to interface  120 , for the last parallel DC device  14 A,  14 B,  14 C, a jumper  24  ( FIG. 1 ) may be coupled to lines  22 C,  22 D. In such an embodiment current may be returned to input line  22 B to complete a circuit when the polarity of an applied voltage provides a positive polarity DC signal on line  22 A. In an embodiment the interface  140  a first switch element  150  includes an N channel MOSFET  142 A with a body diode and a P channel MOSFET  142 B with a body diode connected in series with a device  60  coupled to lines  16 A,  16 B. The MOSFETs  142 A,  142 B body diodes may conduct and permit current to flow into the device  60  when the MOSFETS  142 A,  142 B are not operating. 
     In an embodiment current may pass from input terminal or line  22 A through the P channel MOSFET  142 B body diode, through a device  60  coupled to lines  16 A,  16 B, to the N channel MOSFET  142 A body diode and returning through terminal or line  22 C. The developed or applied voltage may generate a voltage across the gate and source of the N channel MOSFET  142 A and turns on the MOSFET  142 A. At the same time, the gate of the N channel MOSFET  142 C may be turned on, which may apply a voltage potential to the gate of the P channel MOSFET  142 B. In an embodiment, MOSFET  142 A,  142 C, and  142 B may then operate when a positive bias DC signal is applied to lines  22 A,  22 B. Similarly when the applied voltage bias at lines  22 A,  22 B is negative, the circuit  160  may operate in the same manner as circuit  150 . 
     In an embodiment the MOSFETs  142 ,  162  may be replaced by Bipolar transistors in place of MOSFET devices in this design but will yield higher losses and lower operating efficiencies. In addition each MOSFET may be replaced by a series connection of two MOSFETS. Such an embodiment may increase operating losses but may provide additional device  60  protection. 
       FIGS. 9A and 9B  are block diagrams of open circuit detectors  170 ,  180  according to various embodiments. The detector  170 ,  180  may enable devices  60  connected to other parallel DC systems  14 A,  14 B,  14 C to operate when another device  60  of a parallel DC systems  14 A,  14 B,  14 C is open circuited. In an embodiment an open circuit voltage detector  170 ,  180  may be a crowbar overvoltage detector. Further, the quiescent current of the open circuit voltage detection  170 ,  180  may be ideally low in an embodiment. 
     As shown in  FIG. 9A  the open circuit detector  170  may include a rectifier bridge  178 , a Silicon Controlled Rectifier (SCR)  172 , a resistor  174 , and a breakdown diode  176 . The open circuit detector  180  may include a rectifier bridge  188 , Silicon Controlled Rectifier (SCR)  182 A, voltage reference diode  182 B, resistors  184 A to  184 F, and a PNP transistor  186 . 
     The modules may include hardware circuits, single- or multi-processor circuits, memory circuits, software program modules and objects, firmware, and combinations thereof, as desired by the architect of the parallel DC system  14 A,  14 B,  14 C and as appropriate for particular implementations of various embodiments. The apparatus and systems of various embodiments may be useful in applications other than generating DC signals. They are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein. Although the inventive concept may include embodiments described in the exemplary context of one or more electrical standards, the claims are not so limited. Additional information regarding the NEC standards and other electrical standards may be found in common literature available to one of skill in the art. 
     The accompanying drawings that form a part hereof show, by way of illustration and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. 
     Such embodiments of the inventive subject matter may be referred to herein individually or collectively by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept, if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. 
     The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted to require more features than are expressly recited in each claim. Rather, inventive subject matter may be found in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.