Abstract:
Disclosed herein is a device that includes a semiconductor substrate, a check circuit and a through-substrate via. The check circuit includes a check line formed over the semiconductor substrate and including first and second parts each extending in a first direction and a third part extending in a second direction that crosses the first direction, the first and second parts being opposite to each other, the third part connecting one end of the first part with one end of the second part, a charge circuit coupled to a one end of the check line, and a comparator coupled to the other end of the check line at a first input node thereof. The through-substrate via penetrates through the semiconductor substrate and is located in an area that is between the first and second parts of the check line.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device, and particularly to a semiconductor device equipped with a penetrating electrode which is so provided as to pass through a semiconductor chip. 
         [0003]    2. Description of Related Art 
         [0004]    Storage capacity required for semiconductor memory devices such as DRAM (Dynamic Random Access Memory) has been growing year by year. To satisfy the requirement, in recent years, a memory device called multi-chip package has been proposed. In the multi-chip package, a plurality of memory chips are stacked. However, in the case of the multi-chip package, wires that connect each memory chip and a package substrate are necessary. Therefore, it is difficult to stack many memory chips. 
         [0005]    On the other hand, in recent years, a semiconductor device of a type in which a plurality of memory chips with penetrating electrodes are stacked has been proposed (See Japanese Patent Application Laid-Open No. 2005-136187). In the semiconductor device of the type, among penetrating electrodes provided on each memory chip, the penetrating electrodes that are provided on the same plane position when seen from a stacking direction are electrically short-circuited. Therefore, even if the number of chips stacked increases, the number of electrodes connected to the package substrate does not increase. Thus, it is possible to stack a larger number of memory chips. 
         [0006]    When semiconductor chips with penetrating electrodes are stacked, bump electrodes that are provided on upper and lower chips need to be in accurate contact with each other. Accordingly, compared with an operation of stacking chips in the multi-chip package, more accurate positioning is required. As for a device used to stack semiconductor chips having penetrating electrodes, the device disclosed in Japanese Patent Application Laid-Open No. 2006-49417 is known. 
         [0007]    However, when the semiconductor chips are stacked, even as accurate positioning is carried out, the bonding strength between the semiconductor chips could be uneven if the semiconductor chips are warped. In such a case, there is the possibility that the bump electrodes, which should be originally bonded together, come off from each other, possibly lowering the reliability of products. 
       SUMMARY 
       [0008]    In one embodiment, there is provided a semiconductor device that includes: a semiconductor substrate including an electrode forming area; a plurality of through-substrate vias each penetrating through the semiconductor substrate and disposed in the electrode forming area; a check line arranged to pass through the electrode forming area; a charge circuit connected to one end of the check line to supply a first potential to the check line; a reset circuit connected to the other end of the check line to supply a second potential different from the first potential to the check line; and a determination circuit that determines a voltage of the other end of the check line. 
         [0009]    In another embodiment, there is provided a semiconductor device that includes: a semiconductor substrate including an electrode forming area; a plurality of through-substrate vias each penetrating through the semiconductor substrate and disposed in the electrode forming area; a multi-level wiring structure formed on the semiconductor substrate in the electrode forming area, the multi-level wiring structure including a plurality of wiring layers; a check line used to detect whether the multi-level wiring structure is cracked; and a determination circuit outputting a determination signal that takes a first logic level when the check line indicates that the multi-level wiring structure is cracked, and outputting the determination signal that takes a second logic level different from the first logic level when the check line indicates that the multi-level wiring substructure is not cracked. 
         [0010]    In still another embodiment, there is provided a device that includes: a semiconductor substrate, a first check circuit and a first through-substrate via. The first check circuit includes a first check line formed over the semiconductor substrate and including first and second parts each extending in a first direction and a third part extending in a second direction that crosses the first direction, the first and second parts being opposite to each other, the third part connecting one end of the first part with one end of the second part; a first charge circuit coupled to a one end of the check line; and a first comparator coupled to the other end of the first check line at a first input node thereof. The first through-substrate via penetrates through the semiconductor substrate and is disposed in a first area that is between the first and second parts of the first check line. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a schematic cross-sectional view of a semiconductor device an embodiment of the present invention; 
           [0012]      FIGS. 2A to 2C  are diagram for explaining the various types of penetrating electrodes TSV provided in a core chip; 
           [0013]      FIG. 3  is a cross-sectional view of a penetrating electrode TSV 1 ; 
           [0014]      FIG. 4  is a schematic plan view showing the layout of the interface chip IF; 
           [0015]      FIG. 5  is a schematic plan view showing the layout of the core chips CC 1  to CC 3 ; 
           [0016]      FIG. 6  is a block diagram showing the circuit configuration of essential parts of the interposer IP and the interface chip IF; 
           [0017]      FIG. 7  is a block diagram showing the circuit configuration of essential parts of the core chips CC 1  to CC 3 ; 
           [0018]      FIG. 8  is a circuit diagram of the crack check circuits  200  formed in the interface chip IF; 
           [0019]      FIG. 9  is a schematic plan view for explaining the layout of the check line  201 ; 
           [0020]      FIG. 10  is a schematic plan view for explaining the layout of the check line  201  in the interface chip IF; 
           [0021]      FIG. 11  is a timing chart for explaining the operation of the crack check circuits  200 ; and 
           [0022]      FIG. 12  is a circuit diagram of crack check circuits  200  according to a modification. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0023]    Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments. 
         [0024]    Referring now to  FIG. 1 , the semiconductor device  10  of the embodiment has a structure in which the following components are stacked: four core chips CC 0  to CC 3 , which have the same functions and are produced with the use of the same production mask; one interface chip IF, which is produced with the use of a different production mask from that of the core chips CC 0  to CC 3 ; and one interposer IP. The core chips CC 0  to CC 3  and the interface chip IF are semiconductor chips for which a silicon substrate is used, and are stacked by a face-down manner on the interposer IP. The face-down manner means a method of mounting semiconductor chips in such a way that principal surfaces on which electronic circuits such as transistors are formed face downward, or that the principal surfaces face the interposer IP&#39;s side. 
         [0025]    However, the semiconductor device of the present invention is not limited to the above structure. The semiconductor chips each may be stacked by a face-up method. The face-up method means a method of mounting semiconductor chips in such a way that principal surfaces on which electronic circuits such as transistors are formed face upward, or that the principal surfaces face a side opposite to the interposer IP&#39;s side. Alternatively, the semiconductor chips stacked by the face-down manner, and the semiconductor chips stacked by the face-up manner may exist together. 
         [0026]    The core chips CC 1  to CC 3  and the interface chip IF other than the core chip CC 0  placed on the top layer are provided with large numbers of penetrating electrodes TSV that pass through a silicon substrate. The penetrating electrodes may be called penetration electrodes, through-vias, or through-substrate vias. In areas that overlap with the penetrating electrodes TSV when seen from a stacking direction in planar view, top-surface bumps FB are provided on the principal-surface sides of the chips, and back-surface bumps BB are provided on the back-surface sides of the chips. The back-surface bumps BB of a semiconductor chip placed on a lower layer are bonded to the top-surface bumps FB of a semiconductor chip placed on an upper layer. In this manner, the semiconductor chips that are adjacent to each other in the vertical direction are electrically connected. 
         [0027]    According to the present embodiment, the reason why no penetrating electrode TSV is provided on the top-layer core chip CC 0  is because there is no need to form a bump electrode on the back-surface side of the core chip CC 0  as the chips are stacked by the face-down manner. If no penetrating electrode TSV is provided on the top-layer core chip CC 0  as described above, the top-layer core chip CC 0  can be made thicker than the other core chips CC 1  to CC 3  to increase the mechanical strength of the core chip CC 0 . Alternatively, a penetrating electrode TSV may be provided on the top-layer core chip CC 0 . In this case, all the core chips CC 0  to CC 3  can be produced by the same process. 
         [0028]    The core chips CC 0  to CC 3  are semiconductor chips made by removing the so-called front-end section, which serves as an interface with the outside, from circuit blocks contained in a typical SDRAM (Synchronous Dynamic Random Access Memory) that operates alone. In other words, the core chips CC 0  to CC 3  are memory chips on which only circuit blocks belonging to the back-end section are integrated. Among the circuit blocks contained in the front-end section, there are a parallel-to-serial conversion circuit, which performs parallel-to-serial conversion of input/output data between a memory cell array and a data input/output terminal, a DLL (Delay Locked Loop) circuit, which controls an input/output timing of data, and the like. 
         [0029]    Meanwhile, the interface chip IF is a semiconductor chip on which only circuit blocks of the front-end section are integrated, among circuit blocks contained in a typical SDRAM that operates alone. The interface chip IF functions as a common front-end section for the four core chips CC 0  to CC 3 . All accesses from the outside are conducted through the interface chip IF, and inputting and outputting of data are performed through the interface chip IF. 
         [0030]    The interposer IP is a circuit board made of resin. On aback surface IPb thereof, a plurality of external terminals (solder balls) SB are formed. The interposer IP ensures the mechanical strength of the semiconductor device  10  and functions as a redistribution substrate to expand an electrode pitch. That is, substrate electrodes  91  that are formed on a top surface IPa of the interposer IP are led out to the back surface IPb via through-hole electrodes  92 ; rewiring layers  93  that are provided on the back surface IPb are designed to expand the pitch of the external terminals SB. The areas of the top surface IPa of the interposer IP where no substrate electrode  91  is formed are covered with resist  90   a . The areas of the back surface IPb of the interposer IP where no external terminal SB is formed are covered with resist  90   b .  FIG. 1  shows only five external terminals SB. However, a large number of external terminals is actually provided. The layout of the external terminals SB is the same as that of a SDRAM determined by the standard. Accordingly, an external controller can handle the external terminals SB as those of one SDRAM. 
         [0031]    The gaps between the core chips CC 0  to CC 3  and interface chip IF stacked are filled with underfill  94 . In this manner, the mechanical strength is ensured. The gap between the interposer IP and the interface chip IF is filled with NCP (Non-Conductive Paste)  95 . The entire package is covered with mold resin  96 . In this manner, each chip is physically protected. 
         [0032]    When the penetrating electrodes TSV provided in the core chips CC 0  to CC 3  are two-dimensionally viewed from a lamination direction, that is, viewed from an arrow A shown in  FIG. 1 , most of the penetrating electrodes TSV are short-circuited from the penetrating electrodes TSV of other layers provided at the same position. That is, as shown in  FIG. 2A , the vertically disposed penetrating electrodes TSV 1  that are provided at the same position in plain view are short-circuited, and one wiring line is configured by the through silicon via TSV 1 . The penetrating electrodes TSV 1  that are provided in the core chips CC 0  to CC 3  are connected to internal circuits  4  in the core chips, respectively. Accordingly, input signals (command signal, address signal, etc.) that are supplied from the interface chip IF to the penetrating electrodes TSV 1  shown in  FIG. 2A  are commonly input to the internal circuits  4  of the core chips CC 0  to CC 3 . Output signals (data etc.) that are supplied from the core chips CC 0  to CC 3  to the penetrating electrodes TSV 1  are wired-ORed and input to the interface chip IF. 
         [0033]    Meanwhile, as shown in  FIG. 2B , the a part of the penetrating electrodes TSV are not directly connected to the penetrating electrode TSV 2  of other layers provided at the same position in plain view but are connected to the penetrating electrode TSV 2  of other layers through the internal circuits  5  provided in the core chips CC 0  to CC 3 . That is, the internal circuits  5  that are provided in the core chips CC 0  to CC 3  are cascade-connected through the penetrating electrode TSV 2 . This kind of penetrating electrode TSV 2  is used to sequentially transmit predetermined information to the internal circuits  5  provided in the core chips CC 0  to CC 3 . As this information, a select signal SELCC to be described below is exemplified. 
         [0034]    Another part of the penetrating electrodes TSV is short-circuited from the penetrating electrode TSV of other layer provided at the different position in plain view, as shown in  FIG. 2C . With respect to this kind of penetrating electrodes group TSV 3 , internal circuits  6  of the core chips CC 0  to CC 3  are connected to the penetrating electrodes TSV 3   a  provided at the predetermined position P in plain view. Thereby, information can be selectively input to the internal circuits  6  provided in the core chips. As this information, defective chip information is exemplified. 
         [0035]    As such, three types of penetrating electrodes TSV 1  to TSV 3  shown in  FIGS. 2A to 2C  are provided in the core chips CC 0  to CC 3 . As described above, most of the penetrating electrodes TSV are of a type shown in  FIG. 2A , and an address signal and a command signal, and the like are supplied from the interface chip IF to the core chips CC 0  to CC 3 , through the penetrating electrode TSV 1  of the type shown in  FIG. 2A . Read data and write data are input to and output from the interface chip IF through the penetrating electrode TSV 1  of the type shown in  FIG. 2A . Meanwhile, the penetrating electrodes TSV 2  and TSV 3  of the types shown in  FIGS. 2B and 2C  are used to provide individual information to the core chips CC 0  to CC 3  whereas the core chips CC 0  to CC 3  have the same structure as one another. 
         [0036]    Turning to  FIG. 3 , the penetrating electrode TSV 1  is so provided as to pass through a silicon substrate  80 , an interlayer insulation film  81 , which is provided on a top surface of the silicon substrate  80 , and a passivation film  83 , which is provided on a back surface of the silicon substrate  80 . Although not specifically limited, the penetrating electrode TSV 1  is made of Cu (copper). The top surface of the silicon substrate  80  serves as a device formation surface on which devices such as transistors and a multi-level wiring structure including wiring layers L 1  to L 4  are formed. Around the penetrating electrode TSV 1 , insulation rings  82  are provided to insulate the penetrating electrode TSV 1  from a transistor region. Instead of providing the insulation ring  82 , an insulation film such as silicon oxide film can be provided on the inner wall of a through-substrate via that is to be filled by the penetrating electrode TSV. 
         [0037]    An end portion of the penetrating electrode TSV 1  that is closer to the back surface of the silicon substrate  80  is covered with a back-surface bump BB. In the core chips CC 1  to CC 3 , the back-surface bumps BB are in contact with the top-surface bumps FB provided on upper-layer core chips CC 0  to CC 2 , respectively. In the interface chip IF, the back-surface bumps BB are in contact with the top-surface bumps FB provided on the core chip CC 3 . Although not specifically limited, the back-surface bumps BB are made of SnAg solder, which covers the surfaces of the penetrating electrodes TSV 1  made of Cu (copper). The top-surface bump FB is connected to an end portion of the penetrating electrode TSV 1  via interconnection pads M 1  to M 4 , which are provided respectively as the wiring layers L 1  to L 4 , and a plurality of through-hole conductors TH 1  to TH 3 , which connect the interconnection pads. In the core chips CC 1  to CC 3 , the top-surface bumps FB are in contact with the back-surface bumps BB provided on the lower-layer core chips CC 2  and CC 3  and the interface chips IF, respectively. In the interface chip IF, the top-surface bumps FB are in contact with the substrate electrodes  91  on the interposer IP. Although not specifically limited, the top-surface bumps FB include a pillar portion  86  that is made of Cu (copper). A surface of the pillar portion  86  includes a structure in which layers of Ni (nickel) and Au (gold) are stacked. The diameter of the top-surface bumps FE and back-surface bumps BB is about 20 μm. 
         [0038]    According to the above configuration, the top-surface bumps FB and back-surface bumps BB that are provided at the same locations in planar view are being short-circuited via the penetrating electrodes TSV 1 . The pillar portion  86  of a top-surface bump FB is so provided as to pass through a passivation film  84 . A top surface of the passivation film  84  except a region where the top-surface bump FB is formed is covered with a polyimide film  85 . Incidentally, the connection to internal circuits not shown in the diagram is realized via interconnection lines (not shown), which are led out from the interconnection pads M 1  to M 3  provided as the wiring layers L 1  to L 3 . In the present specification, the wiring layers L 1  to L 4  and insulating films intervening therebetween may be referred to as a multi-level wiring structure. 
         [0039]    Incidentally, in the interface chip IF, the penetrating electrodes TSV 1  of such a kind are partially provided. The penetrating electrodes TSV 1  provided on the interface chip IF are used mainly for supplying power supply potential VDD or VSS. 
         [0040]    Most of the penetrating electrodes TSV formed in the interface chip IF are connected to backside bumps BB formed in the same positions when seen in a plan view, but not to surface bumps FB formed in the same positions when seen in a plan view. Although not shown in the drawings, such type of penetrating electrodes TSV are configured so that some of the through hole electrodes TH 1  to TH 3  are missing. 
         [0041]    Turning to  FIG. 4 , the interface chip IF includes circuit forming areas  11  to  13  which extend in the X direction. The circuit forming area  11  is arranged along one side L 11  in the Y direction. The circuit forming area  12  is arranged along the other side L 12  in the Y direction. The circuit forming area  13  is arranged in the center in the Y direction. Various circuit blocks are formed in the circuit forming areas  11  to  13 , including a command decoder, a DLL circuit, a control logic circuit, and an internal voltage generation circuit. 
         [0042]    Penetrating electrode forming areas  21  and  22  are formed between the circuit forming areas  11  and  13  and between the circuit forming areas  12  and  13 , respectively. The penetrating electrode forming areas  21  and  22  are areas where a plurality of penetrating electrodes TSV formed to run through the interface chip IF are regularly arranged. In the present embodiment, the penetrating electrodes formed in each of the penetrating electrode forming areas  21  and  22  are grouped into eight groups. Note that all the penetrating electrodes formed in the penetrating electrode forming areas  21  and  22  need not necessarily be regularly arranged. 
         [0043]    A test pad forming area  31  is formed between the circuit forming area  11  and the penetrating electrode forming area  21 . A test pad forming area  32  is formed between the circuit forming area  12  and the penetrating electrode forming area  22 . The test pad forming areas  31  and  32  are areas where a plurality of test pads TP are formed. The test pads TP are terminals for tester probes to be put into contact with when performing a test in a wafer state. 
         [0044]    Turning to  FIG. 5 , each of the core chips CC 1  to CC 3  includes four memory cell arrays MA 0  to MA 3 . Of these, the memory cell arrays MA 0  and MA 1  are arranged along one side L 21  in the Y direction. The memory cell arrays MA 2  and MA 3  are arranged along the other side L 22  in the Y direction. The memory cell arrays MA 0  to MA 3  are areas where a large number of memory cells are formed in a matrix. 
         [0045]    A peripheral circuit area  40  is arranged between the memory cell arrays MA 0  and MA 1  and the memory cell arrays MA 2  and MA 3 . Various circuit blocks are formed in the peripheral circuit area  40 , including an address decoder, a timing control circuit, and an internal voltage generation circuit. 
         [0046]    A penetrating electrode forming area  51  is formed between the memory cell arrays MA 0  and MA 1  and the peripheral circuit area  40 . A penetrating electrode forming area  52  is formed between the memory cell arrays MA 2  and MA 3  and the peripheral circuit area  40 . The penetrating electrode forming areas  51  and  52  are areas where a plurality of penetrating electrodes TSV are formed to penetrate through the corresponding core chip CC 1 , CC 2 , or CC 3 . The penetrating electrodes TSV are located in planar positions coincident with those of the penetrating electrodes TSV formed in the interface chip IF. Consequently, when the core chips CC 0  to CC 3  and the interface chip IF are stacked, the backside bumps BB of lower chips are joined to the surface bumps FB of upper chips. 
         [0047]    A test pad forming area  60  is further formed between the memory cell arrays MA 0  and MA 1  and the penetrating electrode forming area  51 . The test pad forming area  60  is an area where a plurality of test pads TP are formed. 
         [0048]    In the penetrating electrode forming areas  21 ,  22 ,  51 , and  52  shown in  FIGS. 4 and 5 , a plurality of penetrating electrodes TSV are formed to penetrate through the semiconductor substrate  80 . The multi-level wiring structure shown in  FIG. 3  is also formed on the semiconductor substrate  80  in the penetrating electrode forming areas  21 ,  22 ,  51 , and  52 . As described above, the multi-level wiring structure is a stack of a plurality of wiring layers and insulation films formed on the top and bottom of the wiring layers. It will be understood that such a multi-level wiring structure is also formed on the semiconductor substrate outside the penetrating electrode forming areas  21 ,  22 ,  51 , and  52 . In the process of stacking the core chips CC 0  to CC 3  and the interface chip IF, the penetrating electrodes TSV are subjected to high stress. This can produce cracks in the multi-level wiring structure on the penetrating electrode forming areas  21 ,  22 ,  51 , and  52 . 
         [0049]    Cracks have various shapes. In the depth direction, some cracks may extend from the uppermost passivation film  84  to the lowermost interlayer insulation film  81 . In the planar direction, some may run across an area corresponding to several to several tens of penetrating electrodes TSV. If such cracks occur, wiring in the cracked portions may be broken to make the chip malfunction. The causes of crack-based malfunctions have conventionally been difficult to identify, whereas the present embodiment can easily identify the causes as will be described later. 
         [0050]    Turning to  FIG. 6 , the interposer IP has external terminals including an address terminal  101 , a command terminal  102 , a clock terminal  103 , and a data terminal  104 . All such external terminals are connected to the interface chip IF, but not directly to the core chips CC 0  to CC 3 . The interposer IP also includes a data strobe terminal, a calibration terminal, a power supply terminal, and the like, which are omitted from the diagram. 
         [0051]    The address terminal  101  is supplied with an address signal ADD. The address signal ADD is latched into an address latch circuit  111  in the interface chip IF. The address signal ADD latched into the address latch circuit  111  is supplied to the core chips CC 0  to CC 3  via penetrating electrodes TSV. 
         [0052]    The command terminal  102  is supplied with a command signal CMD. The command signal CMD is decoded by a command decoder  112  in the interface chip IF, whereby an internal command ICMD is generated. The internal command ICMD is supplied to the core chips CC 0  to CC 3  via penetrating electrodes TSV and to a DFT circuit  120  and a test clock generator  121  in the interface chip IF. The DFT circuit  120  and the test clock generator  121  are circuit blocks to be activated when the internal command ICMD indicates a test command. 
         [0053]    The clock terminal  103  is supplied with a clock signal CLK. The clock signal CLK is supplied to a clock generator  113 . The clock generator  113  generates an internal clock signal ICLK based on the clock signal CLK, and supplies the internal clock signal ICLK to various circuit blocks including the test clock generator  121 . 
         [0054]    The data terminal  104  is a terminal for inputting and outputting data DQ. The data terminal  104  is connected to a data input/output circuit  114 . Write data supplied to the data input/output circuit  114  through the data terminal  104  is transferred to the core chips CC 0  to CC 3  via penetrating electrodes TSV. Read data read from the core chips CC 0  to CC 3  is output to the data terminal  104  through the data input/output circuit  114 . 
         [0055]    The interface chip IF further includes a plurality of crack check circuits  200 . The crack check circuits  200  are circuits for checking the multi-level wiring structure on the penetrating electrode forming areas  21  and  22  shown in  FIG. 4  for cracks. The reason why a plurality of crack check circuits  200  are provided is to divide the penetrating electrodes TSV arranged in the penetrating electrode forming areas  21  and  22  into a plurality of groups and detect the presence or absence of a crack in each group. In the present invention, more than one crack check circuit  200  need not necessarily be provided. The provision of the crack check circuits  200  for the respective groups allows an evaluation of which part of the penetrating electrode forming areas  21  and  22  is cracked. 
         [0056]    As has been described with reference to  FIG. 4 , in the present embodiment, the penetrating electrodes TSV formed in each of the penetrating electrode forming areas  21  and  22  are grouped into eight groups. In other words, the penetrating electrodes TSV are grouped into a total of 16 groups. The crack check circuits  200  are allocated for the respective 16 groups. The crack check circuits  200  operate based on a test command TCMD output from a command generator  123 . A specific circuit configuration of the crack check circuits  200  will be described later. 
         [0057]    The command generator  123  shown in  FIG. 6  is activated by a select signal SELIF output from the DFT circuit  120 , and activates a plurality of test commands TCMD in succession based on an output signal from a decoder  122 . The decoder  122  is a circuit that decodes three bits of command signals T 0  to T 2  supplied from the DFT circuit  120 . The command signals T 0  to T 2  are also supplied to the core chips CC 1  to CC 3  via penetrating electrodes TSV. 
         [0058]    Detection signals S output from the crack check circuits  200  are supplied respectively to shift registers  210 . The shift registers  210  latch the detection signals S from the corresponding crack check circuits  200  in response to the test commands TCMD, and serially output the detection signals S in synchronization with a test clock signal TCLK. The output detection signals S are output to outside through a data selector  124  and the data input/output circuit  114 . The test clock signal TCLK is a signal generated by the test clock generator  121 . The test clock signal TCLK is supplied to the command generator  123 , and to the core chips CC 1  to CC 3  via penetrating electrodes TSV. The data selector  124  is a circuit that selects either the detection signals S generated inside the interface chip IF or detection signals S transferred from the core chips CC 1  to CC 3  based on the test commands TCMD. 
         [0059]    Turning to  FIG. 7 , the core chips CC 1  to CC 3  include the memory cell arrays MA 0  to MA 3 . Each of the memory cell arrays MA 0  to MA 3  includes a plurality of word lines WL and a plurality of bit lines BL, at intersections of which are arranged memory cells MC. For the sake of simplicity,  FIG. 7  shows only one word line WL, one bit line BL, and one memory cell MC connected thereto. 
         [0060]    The word lines WL are selected by a row decoder  301 . The row decoder  301  selects the word lines WL based on the address signal ADD (row address) supplied from the interface chip IF via the penetrating electrodes TSV. The bit lines BL are connected to respective corresponding sense amplifiers in a sense amplifier row  303 . The sense amplifiers are selected by a column decoder  302  based on the address signal ADD (column address) supplied from the interface chip IF via the penetrating electrodes TSV. With such a configuration, read data read from the memory cell arrays MA 0  to MA 3  is transferred to the interface chip IF via the penetrating electrodes TSV. Write data supplied from the interface chip IF via the penetrating electrodes TSV is written into the memory cell arrays MA 0  to MA 3 . 
         [0061]    Like the interface chip IF, the core chips CC 1  to CC 3  each include a plurality of crack check circuits  300 . The crack check circuits  300  are circuits for checking the multi-level wiring structure on the penetrating electrode forming areas  51  and  52  shown in  FIG. 5  for cracks. The reason why a plurality of crack check circuits  300  are provided is that the penetrating electrodes TSV arranged in the penetrating electrode forming areas  51  and  52  are divided into a plurality of groups. The crack check circuits  300  can thus evaluate which part of the penetrating electrode forming areas  51  and  52  is cracked. 
         [0062]    The crack check circuits  300  operate based on various test commands TCMD output from a command generator  323 . The command generator  323  is activated by a select signal SELCC supplied from the DFT circuit  120  in the interface chip IF, and activates various test commands TCMD in succession based on an output signal from a decoder  322 . The decoder  322  is a circuit that decodes the three bits of command signals T 0  to T 2  supplied from the DFT circuit  120 . The select signal SELCC is transferred from the lower core chip CC 3  to the upper core chip CC 1  in succession via the penetrating electrodes TSV 2  shown in  FIG. 2B , whereby the command generators  323  in the core chips CC 1  to CC 3  are activated in succession. 
         [0063]    Detection signals S output from the crack check circuits  300  are supplied respectively to shift registers  310 . The shift registers  310  latch the detection signals S from the corresponding crack check circuits  300  in response to the test commands TCMD, and serially output the detection signals S in synchronization with the test clock signal TCLK. The output detection signals S are supplied to the interface chip IF via the penetrating electrodes TSV, and output to outside through the data selector  124  and the data input/output circuit  114  in the interface chip IF. The test clock signal TCLK is supplied from the interface chip IF via the penetrating electrodes TSV. 
         [0064]    In the examples shown in  FIGS. 6 and 7 , the detection signals S are transferred by using the dedicated penetrating electrodes TSV. Alternatively, the detection signals S may be transferred by using other penetrating electrodes TSV that are unused during a check operation, such as the penetrating electrodes TSV intended for data DQ. The same applies for the penetrating electrodes TSV that are used to transfer the command signals T 0  to T 2 . 
         [0065]    The core chip CC 0  lying at the uppermost layer has no penetrating electrode TSV, and thus need not include the crack check circuits  300  or the relevant circuits. Since the core chips CC 0  to CC 3  are preferably fabricated by using the same manufacturing masks, the core chip CC 0  in fact includes the crack check circuits  300  and the relevant circuits. The core chip CC 0  is also joined by using surface bumps FB, so that cracks can occur in the areas where the surface bumps FB are formed. To perform a check operation using the crack check circuits  300  formed in the core chip CC 0  is thus effective. 
         [0066]    A configuration of the crack check circuits  200  formed in the interface chip IF will be explained with reference to  FIG. 8 . The crack check circuits  300  formed in the core chips CC 1  to CC 3  have the same circuit configuration as that of the crack check circuits  200  shown in  FIG. 8 . 
         [0067]    As shown in  FIG. 8 , the crack check circuits  200  each include check line  201 , a charge circuit  202  which is connected to one end  201   a  of the check line  201 , and a reset circuit  203  which are connected to the other end  201   b  of the check line  201 , a determination circuit  204 , and a retention capacitor  205 . The check line  201  is constituted by a wiring layer (s) included in the multi-level wiring structure on the penetrating electrode forming areas  21  and  22 . As shown in  FIG. 8 , the check line  201  winds to avoid hitting penetrating electrodes TSV. The charge circuit  202  includes a P-channel MOS transistor. When a charge signal CEN that is one of the test commands TCMD is activated to a high level, the charge circuit  202  supplies a power supply potential VDD to the one end  201   a  of the check line  201 . The reset circuit  203  includes an N-channel MOS transistor. When a reset signal RST that is one of the test commands TCMD is activated to a high level, the reset circuit  203  supplies a ground potential VSS to the other end  201   b  of the check line  201 . The potential of the other end  201   b  of the check line  201  is temporarily retained by the retention capacitor  205 . 
         [0068]    The determination circuit  204  includes a comparator having a positive input node (+) and a negative input node (−). The positive input node (+) is connected to the other end  201   b  of the check line  201 . The negative input node (−) is supplied with a reference voltage Vref. The reference voltage Vref is generated by a reference voltage generation circuit  206  in response to an enable signal REFEN, one of the test commands TCMD. The reference voltage Vref is set to an intermediate level between the power supply potential VDD and the ground potential VSS. The output signal of the determination circuit  204  is taken into a latch circuit  207 . An output signal of the latch circuit  207  is a detection signal S. If the other end  201   b  of the check line  201  has a potential higher than the reference voltage Vref, the detection signal S becomes a high level. If the other end  201   b  of the check line  201  has a potential lower than the reference voltage Vref, the detection signal S becomes a low level. 
         [0069]    As shown in  FIG. 9 , the check line  201  includes wiring portions  201   x  extending in the X direction and wiring portions  201   y  extending in the Y direction. The wiring portions  201   x  adjoin the penetrating electrodes TSV in the Y direction when seen in a plan view. The wiring portions  201   y  adjoin the penetrating electrodes TSV in the X direction when seen in a plan view. By such winding, the check line  201  can be laid out over a wider range on the penetrating electrode forming areas  21  and  22 , which facilitates detecting the occurrence of cracks. The wiring portions  201   x  and the wiring portions  201   y  are preferably, though not limited to, formed as different wiring layers. For example, the wiring portions  201   x  may be formed as the wiring layer L 3  shown in  FIG. 3 , and the wiring portions  201   y  may be formed as the wiring layer L 4  shown in  FIG. 3 . Such configuration facilitates the layout of the check line  201 . 
         [0070]    Turning to  FIG. 10 , in the present embodiment, the penetrating electrodes TSV arranged in the penetrating electrode forming areas  21  and  22  are grouped into 16 groups (BLK 0  to BLK 15 ). The check line  201  and the relevant circuits  202  to  207  are provided for each group. In other words, there are 16 crack check circuits  200 . The command generator  123  supplies the test commands TCMD to the 16 crack check circuits  200  in common. The 16 crack check circuits  200  therefore simultaneously perform a check detection operation and simultaneously output the detection signals S. The detection signals S retained in the shift registers  210  are serially output to the data selector  124  in synchronization with the test clock signal TCLK. 
         [0071]    As described above, the plurality of crack check circuits  200  within the chip operate simultaneously. On the other hand, the crack check circuits  200  and  300  of different chips operate sequentially. The reason is to prevent a conflict between the detection signals S output from the shift registers  210  and  310 . Which chip to perform a crack detection operation is selected by the select signals SELIF and SELCC output from the DFT circuit  120 . For example, crack detection operations may be performed in order of the interface chip IF and the core chips CC 3 , CC 2 , and CC 1 , and the detection signals S may be output in that order. As described above, the core chip CC 0  may also perform a crack detection operation. 
         [0072]    An operation of the crack check circuits  200  will be explained with reference to  FIG. 11 . The same applies for the operation of the crack check circuits  300  included in the core chips CC 1  to CC 3 . 
         [0073]    Suppose that a crack check circuit  200  enters a test mode for performing a crack detection operation. Initially, the determination circuit  204  is activated, the latch circuit  207  is reset, and the enable signal REFEN is activated to a low level (time t 1 ). This activates the reference voltage generation circuit  206 , and the reference voltage Vref is supplied to the negative input node (−) of the determination circuit  204 . 
         [0074]    Next, the reset signal RST is temporarily set to a high level, whereby the potential of the check line  201  is reset to the ground potential VSS (time t 2 ). Next, the charge signal CEN is activated to a high level, whereby the one end  201   a  of the check line  201  is connected to the power supply potential VDD (time t 3 ). If the check line  201  is not broken, a potential  201 V at the other end of the check line  201  rises as shown by the waveform OK. If the check line  201  is broken, the potential  201 V at the other end of the check line  201  remains at the ground potential VSS as shown by the waveform NG. Such a state is maintained for a predetermined time before the output signal of the determination circuit  204  is latched into the latch circuit  207  at time t 4 . At time t 5 , the enable signal REFEN and the charge signal CEN are deactivated to end a series of crack detection operations. 
         [0075]    The detection signal S latched into the latch circuit  207  is then transferred to the shift register  210  and output to outside in synchronization with the test clock signal TCLK. 
         [0076]    After such an operation, a detection signal S of high level shows that the check line  201  is not broken, i.e., the corresponding penetrating electrode forming area is not cracked. On the other hand, a detection signal S of low level shows that the check line  201  can be broken, i.e., the corresponding penetrating electrode forming area can be cracked. Since the detection signals S are serially output to outside, it is possible to evaluate which area of which chip is cracked. 
         [0077]    As described above, according to the present embodiment, if the multi-level wiring structures on the penetrating electrode forming areas  21 ,  22 ,  51 , and  52  are cracked, which area of which chip is cracked can be evaluated without disassembling the stacked core chips CC 0  to CC 3  and interface chip IF. 
         [0078]      FIG. 12  is a circuit diagram of crack check circuits  200  according to a modification. A plurality of crack check circuits  200  shown in  FIG. 12  are provided for a single group of penetrating electrodes TSV, not one for a single group of penetrating electrodes TSV. In other words, a group is subdivided into a plurality of subgroups, and a crack check circuit  200  is allocated for each subgroup. Such a configuration can identify a cracked area in more detail, thereby allowing more detailed evaluation. 
         [0079]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. 
         [0080]    For example, according to each of the above-described embodiments, there has been described a semiconductor device of a type in which the interface chip IF and the core chips CC 0  to CC 3  are stacked. However, the present invention is not limited to the above type. Accordingly, the type and number of semiconductor chips stacked are not specifically limited. Moreover, the technical concept of the present invention is realized not only in the situation where a plurality of semiconductor chips are stacked, but also in a single semiconductor chip that has not yet been stacked. The reason is that even a semiconductor chip that has not yet been stacked can achieve the above-described advantageous effects in the subsequent stacking process. Therefore, the scope of the present invention is not limited to the stacked semiconductor device.