Abstract:
An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims the benefit of U.S. provisional application entitled “LOW LEAKAGE POWER ESD CLAMP”, Ser. No. 60/940,467, filed May 29, 2007, and the benefit of U.S. provisional application entitled “LOW LEAKAGE POWER ESD CLAMP”, Ser. No. 60/956,132, filed on Aug. 16, 2007, which are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to an ESD protection device, and more particularly to an SCR-based ESD protection device. 
         [0004]    2. Description of the Related Art 
         [0005]    Electrostatic discharge (ESD) damage has become one of the main reliability concerns facing integrated circuit (IC) products. Particularly, when scaled down to the deep sub-micron regine, integrated circuits become more vulnerable to ESD stress. Semiconductor controlled rectifier (SCR) devices had been used as an ESD protection device to protect complementary metal oxide semiconductor (CMOS) integrated circuit against damage. The SCR devices have the advantage of low holding voltage, which results in less power dissipation in the SCR devices under the ESD event than other ESD protection devices, such as thin oxide NMOS, or diode, in the CMOS technologies. Thus, the SCR devices can sustain much higher ESD voltage with a smaller layout area. 
         [0006]    MOS transistors and SCR devices are both efficient protection devices, however, the MOS transistors are widely used in the industry. This is because the SCR device used for an ESD protection in deep submicron CMOS technologies has the latch-up issue. 
         [0007]    Thus, it is desired to provide a novel SCR device structure with lath-up free to protect integrated circuits in low operating voltage application. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    One exemplary embodiment of an ESD protection device comprises a substrate, a first doping region, a first MOS transistor structure, a second MOS transistor structure, a sixth doping region, and a first well region. The first doping region is formed in the substrate and encloses an active region, wherein the first doping region is coupled to a first node. The first MOS transistor structure is on the internal of the active region and comprises a second doping region, a third doping region, and a first gate. The second doping region is formed in the substrate and comprises a first portion and a second portion, wherein the second doping region is coupled to the first node. The third doping region is formed in the substrate. The first gate is formed on the substrate and between the second portion of the second doping region and the third doping region. 
         [0009]    The second MOS transistor structure is on the internal of the active region and comprises a fourth doping region, a fifth doping region, and a second gate. The fourth doping region is formed in the substrate and comprises a first portion and a second portion, wherein the fourth doping region is coupled to a second node. The fifth doping region is formed in the substrate. The second gate is formed on the substrate and between the first portion of the fourth doping region and the fifth doping region. The third doping region is near the second portion of the fourth doping region, and the fifth doping region is near the first portion of the second doping region. The sixth doping region is formed in the substrate and on one side of the first and second MOS transistor structures, wherein the sixth doping region is coupled to the second node. The first well region is on the internal of the active region and formed in the substrate and under one part of the third doping region, one part of the fifth doping region, the fourth doping region, and the sixth doping region. 
         [0010]    Another exemplary embodiment of an ESD protection device comprises a substrate, first to sixth doping regions, first and second gates, and a first well region. The first doping region is formed in the substrate and coupled to a first node. The second doping region is formed in the substrate and encloses the first doping region, wherein the second doping region comprises a first portion and a second portion and is coupled to the first node. The third doping region is formed in the substrate and encloses the first portion of the second doping region, wherein the third doping region has a first open. The first gate is formed on the substrate and between the first portion of the second doping region and the third doping region. The fourth doping region is formed in the substrate and encloses the second portion of the second doping region, wherein the fourth doping region has an second open corresponding to the first open. The fifth doping region is formed in the substrate and comprises a first portion and a second portion, wherein the first portion of the fifth doping region encloses the third doping region, and the second portion thereof encloses the fourth doping region. The second gate is formed in the substrate and between the second of the fifth doping region and the fourth doping region. The sixth doping region is formed in the substrate and encloses the fifth doping region, wherein the fifth and sixth doping regions are coupled to a second node. The first well region is formed in the substrate and under the first doping region, the second doping region, one part of the third doping region, and one part of the fourth doping region. 
         [0011]    Another exemplary embodiment of an ESD protection device comprises a first SCR and an ESD detection circuit. The first SCR is coupled between a high voltage source and a ground. The ESD detection circuit detects whether an ESD event occurs. When the ESD detection circuit detections that the ESD event occurs, the ESD detection circuit provides a first voltage and a second voltage to the first SCR, so that the first SCR provides a first discharging path. 
         [0012]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0014]      FIG. 1  is a top view of an exemplary embodiment of an SCR semiconductor structure of an ESD protection device; 
           [0015]      FIGS. 2A-2B  are sectional views along lines AA′ and BB′ in  FIG. 1 ; 
           [0016]      FIG. 3  shows the equivalent circuit of the SCR of the ESD protection device; 
           [0017]      FIG. 4  is a top view of another exemplary embodiment of an SCR semiconductor structure of an ESD protection device; 
           [0018]      FIG. 5  is a top view of another exemplary embodiment of an SCR semiconductor structure of an ESD protection device; 
           [0019]      FIG. 6  is a top view of another exemplary embodiment of an SCR semiconductor structure of an ESD protection device; and 
           [0020]      FIG. 7  shows an exemplary embodiment of an ESD protection device. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0022]      FIG. 1  and  FIGS. 2A-2B  are top view and sectional views along lines AA′ and BB′ of an exemplary embodiment of a semiconductor controlled rectifier (SCR) semiconductor structure of an ESD protection device. Referring to  FIG. 1  and  FIGS. 2A-2B , an SCR  1  of an ESD protection device comprises a P-type substrate (P-sub)  10 , N-type well regions (N-well)  11  and  12 , P+ doping regions  13 - 15 , N+ doping regions  16 - 19 , isolation structures  20  and  21 , and gates G 10  and G 11 . The P+ doping regions  13  is formed in the substrate  10  and encloses an active region. The ESD protection device constitutes at least two MOS transistor structures in the active region. The isolation structure  21  is formed in the substrate and surrounded along the internal of the P+ doping region  13 . The N-type well region  11  is formed in the substrate  10  and encloses the P+ doping region  13 . The N+ doping region  19  is formed in the N-type well region  11 . The isolation structure  20  is formed in the substrate  10  and between the P+ doping region  13  and the N-type well region  11 . 
         [0023]    In this embodiment, the SCR  1  comprises two MOS transistor structures. One MOS transistor structure comprises the N+ doping regions  16  and  17  and the gate G 10 , the other comprises the P+ doping regions  14  and  15  and the gate G 11 . The N+ doping region  16  is formed in the substrate  10  and comprises a first portion and a second portion. The N+ doping region  17  is formed in the substrate and near the second portion potion of the N+ doping region  16 . The gate G 10  is formed on the substrate  10  and between the second portion of the N+ doping region  16  and the N+ doping region  17 . The P+ doping region  14  is formed in the substrate  10  and near the first portion of the N+ doping region  16 . The P+ doping region  15  is formed in the substrate  10  and comprises a first portion and a second portion. The second portion of the P+ doping region  15  is near the N+ doping region  17 . The gate G 11  is formed on the substrate  10  and between the first portion of the P+ doping region  15  and the P+ doping region  14 . The well region  12  is formed in the substrate  10  and under one part of the P+ doping region  14 , one part of the N+ doping region  17 , the P+ doping region  15 , and the N+ doping region  18 . The N+ doping region  18  is formed in the substrate  10  and on one side of these two MOS transistor structures. Referring to  FIGS. 2A-2B , the P+ doping region  13  and the N+ doping region  16  are coupled to a node N 20 , and the P+ doping region  15  and the N+ doping region  18  are coupled to a node N 21 . 
         [0024]      FIG. 3  shows the equivalent circuit of the ESD protection device. The ESD protection device comprises the SCR  1  of  FIG. 1  and an ESD detection circuit  30 . According to above semiconductor structure, the N+ doping regions  16  and  17  and the gate G 10  constitutes an NMOS transistor  31 , and the N+ doping regions  16  and  17  respectively serve as a source and a drain of the NMOS transistor  31 . The P+ doping regions  14  and  15  and the gate G 11  constitutes a PMOS transistor  32 , and the N+ doping regions  14  and  15  respectively serve as a drain and a source of the PMOS transistor  32 . 
         [0025]    Referring to  FIGS. 2A-2B  and  FIG. 3 , the P+ doping region  15 , the N-type well region  12 , and the P-type substrate  10  constitute an equivalent P-type BJT transistor  22 . The N-type well  12 , the P-type substrate  10 , and the N+ doping region  16  constitutes an equivalent N-type BJT transistor  23 , and the N+ doping region  17 , the P-type substrate  10 , and the N+ doping region  16  constitutes an equivalent N-type BJT transistor  24 . As shown in  FIG. 3 , the N-type BJT transistors  23  and  24  are represented by an equivalent N-type BJT transistor  33 . The equivalent resistance of the N-type well region  12  is represented by R WELL , while the equivalent resistance of the P-type substrate  10  is represented by R SUB . 
         [0026]    Referring to the equivalent circuit in  FIG. 3 , the source of the PMOS transistor  32  is coupled to the node N 21 , and a drain thereof is coupled to a node N 30 . An emitter of the P-type BJT transistor  22  is coupled to the node N 21 , a collector thereof is coupled to the node N 30 , and a base thereof coupled to a node N 31 . The equivalent resistance R WELL  is coupled between the nodes N 21  and N 31 . A collector of the N-type BJT transistor  33  is coupled to the node N 31 , an emitter thereof is coupled to the node N 20 , and a base thereof is coupled to the N 30 . The drain of the NMOS transistor  31  is coupled to the node N 31 , and the source thereof is coupled to the node N 20 . 
         [0027]    Referring to  FIG. 3 , the ESD detection circuit  30  is coupled between the nodes N 20  and N 21  and detects whether an ESD event occurs. In this embodiment, the node N 20  is coupled to a ground GND, and the node N 21  is coupled to a high voltage source VDD. In normal mode, the ESD detection circuit provides a low voltage and a high voltage respectively to the gates G 10  and G 11  to turn off the MOS transistors  31  and  32 . When detecting that the ESD event occurs, the ESD detection circuit  30  provides a high voltage and a low voltage respectively to the gates G 10  and G 11  to turn on the MOS transistors  31  and  32 , so that the SCR  1  provides a discharging path. 
         [0028]      FIG. 4  is a top view of another exemplary embodiment of an SCR semiconductor structure of an ESD protection device. Referring to  FIG. 4 , an active region of an SCR  4  comprises two portions  40  and  41  according to a division line CC′. The portion  40  of the SCR  4  has the same semiconductor structure as the active region of the SCR  1 . The portion  41  is symmetrical to the portion  40  based on the division line CC′. Thus, the SCR  4  comprises four MOS transistor structures. 
         [0029]      FIG. 5  is a top view of another exemplary embodiment of an SCR semiconductor structure of an ESD protection device. Referring to  FIG. 5 , an active region of an SCR  5  comprises two portions  50  and  51  according to a division line DD′. The portion  50  of the SCR  5  has the same semiconductor structure as the active region of the SCR  1 . The semiconductor structure of the active region of the SCR  1  is rotated 180 degrees to serve as the portion  51 . Thus, the SCR  5  comprises four MOS transistor structures. 
         [0030]      FIG. 6  is a top view of another exemplary embodiment of an SCR of an ESD protection device. Referring to  FIG. 6 , an SCR  6  comprises a P-type substrate, N-type well regions  61  and  62 , P+ doping regions  63 - 65 , N+ doping regions  66 - 69 , isolation structures  70  and  71 , and gates G 60  and G 61 . The N+ doping region  66  is formed in the substrate. The P+ doping region  63  is formed in the substrate and encloses the N+ doping region  66 . The P+ doping region  63  comprises a first portion and a second portion. The P+ doping region  64  is formed in the substrate and encloses the first portion of the P+ doping region  63 . The gate G 60  is formed on the substrate and between the first portion of the P+ doping region  63  and the P+ doping region  64 . The N+ doping region  67  is formed in the substrate and encloses the second portion of the P+ doping region  63 . Referring to  FIG. 6 , the P+ doping region  64  has an open, and the N+ doping region  67  has an open corresponding to the open of the P+ doping region  64 . 
         [0031]    The N+ doping region  68  is formed in the substrate and comprises a first portion and a second portion. The first portion of the N+ doping region  68  encloses the P+ doping region  64 , and the second portion thereof encloses the N+ doping region  67 . The gate G 61  is formed in the substrate and between the second portion of the N+ doping region  68  and the N+ doping region  67 . The P+ doping region  65  is formed in the substrate and encloses the N+ doping region  68 . The isolation structure  70  is formed in the substrate and between the N+ doping region  68  and the P+ doping region  65 . The N-type well region  62  is formed in the substrate and encloses the P+ doping region  65 . The isolation structure  71  is formed in the substrate and between the N-type well region  62  and the P+ doping region  65 . The N+ doping region  69  is formed in the N-type well region  62 . The N-type well region  61  is formed in the substrate and under the N+ doping region  66 , the P+ doping region  63 , one part of the P+ doping region  64 , and one part of the N+ doping region  67 . Moreover, the P+ doping region  63  and the N+ doping region  66  are coupled to one node, and the P+ doping region  65  and the N+ doping region  68  are coupled to the other node. 
         [0032]    According to the structure of the SCR  6 , there are four MOS transistor structures to form four MOS transistors. The P+ doping regions  63  and  64  and the gate G 60  constitute two MOS transistors, and the N+ doping regions  67  and  68  and the gate G 61  constitute the other two MOS transistors. When the SCR  6  is applied with an ESD detection circuit, such as the ESD detection circuit  30  of  FIG. 3 , the node coupled to the P+ doping region  63  and the N+ doping region  66  is coupled to a high voltage source, and the node coupled to the P+ doping region  65  and the N+ doping region  68  is coupled to a ground. The sectional views along lines EE′ and FF′ in  FIG. 6  are the same as the sectional views of  FIGS. 2A and 2B , respectively. 
         [0033]    Each of the above SCRs  1 ,  4 ,  5  and  6  can be coupled between an I/O pad and a ground GND. Referring to  FIG. 7 , an ESD protection device  7  comprises an ESD detection circuit  75 , SCRs  72   a - 72   b , and a diode  73 . The SCR  72   a  is coupled between a high voltage source VDD and a ground GND, and the SCR  72   b  is coupled between an I/O pad  74  and the ground GND. The SCRss  72   a - 72   b , have the same equivalent circuit, and each of the SCRs  72   a - 72   b  has the same semiconductor structure as the SCR  1 ,  4 ,  5 , or  6 . For example, each of the SCRs  72   a - 72   b  has the same structure as the SCR  1 . The diode  73  is coupled between the I/O pad  74  and the ESD detection circuit  75 . 
         [0034]    The ESD detection circuit  75  is coupled between the high voltage source VDD and the ground GND and detects whether an ESD event occurs. In normal mode, the ESD detection circuit  75  provides a low voltage and a high voltage respectively to the gates G 10  and G 11  of the SCRs  72   a - 72   b  to turn off the MOS transistors  31  and  32  thereof. When detecting that the ESD event occurs, the ESD detection circuit  75  provides a high voltage and a low voltage respectively to the gates G 10  and G 11  of the SCRs  72   a - 72   b  to turn on the MOS transistors  31  and  32  thereof, so that each of the SCRs  72   a - 72   b  provides a discharging path. 
         [0035]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.