Abstract:
The invention relates to a thin film capacitor with a carrier substrate, at least two interdigitated electrodes, and a dielectric. A staggered arrangement of at least one interdigitated electrode below the dielectric with respect to an interdigitated electrode above the dielectric results in a breakdown-resistant thin film capacitor which can be manufactured in the same production process as a standard monolayer capacitor.

Description:
BACKGROUND OF THE INVENTION 
   The invention relates to a thin film capacitor which comprises a carrier substrate, at least two interdigitated electrodes, and at least one dielectric. 
   Dielectric materials with high dielectric constant values (ε r &gt;50) are used for achieving high capacitance values in capacitors of small dimensions. Dielectrics with ε r &gt;50 at dielectric thicknesses of 50 nm to 2 μm are made by means of thin film processes in the manufacture of of thin film capacitors. An inexpensive method which is used for depositing thin layers with ε r &gt;50 is a wet chemical thin film method such as, for example, the sol-gel method. The lower electrode in a thin film capacitor is made of a non-noble metal such as, for example, aluminum or copper, or a noble metal, for example silver, a silver alloy, or platinum. For the upper electrode, noble metals such as, for example, platinum, silver, silver alloys, or NiCr/gold are used, as for the lower electrode, or alternatively non-noble metals such as, for example, aluminum, nickel, or copper. These are applied by means of thin film processes such as, for example, sputtering or chemical deposition from the gas phase. The electrodes are structured by means of lithographical processes in combination with wet or dry etching steps. Suitable carrier substrate materials are Si wafers, glass or ceramic materials. A protective layer is used for protecting the capacitor construction, for example an organic layer and/or an inorganic layer provided in a printing process or a thin film process. The capacitors are further provided with current supply contacts, either individually or in rows. 
   This state of the art technology is quite capable of producing inexpensive thin film capacitors which comply with standard specifications. The layer thicknesses of approximately one micrometer, however, do not suffice if higher operating voltages U rated  (50 V, 100 V and higher) are to be accommodated in conjunction with increased life requirements for low capacitance values of a few picofarad in high-frequency applications. 
   A higher breakdown resistance is found in so-called interdigitated capacitors whose electrodes have a finger-like arrangement. The finger shapes of these interdigitated electrodes and their interlocking arrangement together with the superimposed dielectric form the actual capacitor. The capacitance value of such an arrangement is a function of the finger interspacing, the length of the overlaps, the thickness of the dielectric, the dielectric constant values of the substrate and of the dielectric, and the thickness of the electrodes. The finger interspacing in fact determines the breakdown resistance and the resulting admissible operating voltage of the capacitor type. 
   A capacitor arrangement with interdigitated electrodes is known from publication no. 07283076 A from “Patent Abstracts of Japan”, wherein several interdigitated electrode layers are present one above the other so as to enhance the capacitance value still further. The interdigitated electrodes of a capacitor unit all lie in one plane, and a dielectric is present between every two adjoining electrode levels. A disadvantage of the arrangement of the electrodes in one plane is that the full thickness of the dielectric is not utilized for contributing to the capacitance of the capacitor. 
   SUMMARY OF THE INVENTION 
   The invention has for its object to develop an improved thin film capacitor with interdigitated electrodes and a high breakdown resistance. 
   This object is achieved in a thin film capacitor comprising a carrier substrate, at least two interdigitated electrodes, and at least one dielectric, which is characterized in that at least one interdigitated electrode is arranged below the dielectric and at least one interdigitated electrode is arranged above the dielectric. 
   The layers of the dielectric contribute to the capacitance behavior of the capacitor when the interdigitated electrodes are positioned above and below the dielectric. 
   A preferred embodiment provides that the interdigitated electrode above the dielectric is positioned staggered with respect to the interdigitated electrode below the dielectric. 
   The staggered arrangement achieves that the dielectric is permeated more evenly by the electric field, and accordingly higher capacitance values can be attained, all other parameters remaining the same. 
   A further preferred embodiment is characterized in that the dielectric comprises a plurality of layers. 
   It is possible through the use of multiple layers, for example double, triple, or quadruple layers, to compensate for the unfavorable temperature behavior of some dielectric materials and to improve the temperature dependence of the capacitance value of the thin film capacitor. 
   In a preferred embodiment, the dielectric comprises a ferroelectric ceramic material. 
   Ferroelectric ceramic materials have a high relative dielectric constant ε r  annnd allow for high capacitance values in small dimensions. 
   It is furthermore preferred that a barrier layer is provided on the carrier substrate. 
   Reactions with the dielectric or short-circuits can be avoided by means of a barrier layer in the case of substrates having a rough surface, for example Al 2 O 3 . 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
       FIG. 1  is a diagram of the construction of a thin film capacitor with two interdigitated electrodes, and 
       FIG. 2  is a diagram of the construction of a thin film capacitor with three interdigitated electrodes. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In  FIG. 1 , a thin film capacitor comprises a carrier substrate  1  which is made, for example, from a ceramic material, a glass-ceramic material, a glass material, or silicon. A barrier layer, for example made from SiO 2 , TiO 2 , Al 2 O 3  or ZrO 2 , is provided on the carrier substrate  1 . On this barrier layer  2  there is a first interdigitated electrode  4  which comprises, for example, Al,
     Al doped with Cu,   Cu,   W,   Pt,   Ni,   Pd,   Pd/Ag,   TiW/Al,   Ti/Pt,   Ti/Ag,   Ti/Ag/TiIr,   Ti/Ag x Pt 1-x  (0≦x≦1)   Ti/Ag/Pt x Al 1-x  (0≦x≦1),   Ti/Ag x Pt 1-x /Ir (0≦x≦1),   Ti/Ag/(Ir/IrO x ) (0≦x≦2),   Ti/Ag/Ru x Pt 1-x  (0≦x≦1),   Ti/Pt x Al 1-x /Ag/Pt y Al 1-y  (0≦x≦1, 0≦y≦1),   Ti/Ag/Pt y (RhO x ) 1-y  (0≦x≦2, 0≦y≦1),   Ti/Ag/Pt x Rh 1-x  (0≦x≦1),   Ti/Ag x Pt 1-x /(Ir/IrO y ) (0≦x≦1, 0≦y≦2),   Ti/Ag x Pt 1-x /Pt y Al 1-y  (0≦x≦1, 0≦y1),   Ti/Ag/Ti,   Ti/Ni/ITO or   NiCrAl/Ni, Ni x Cr y Al z /Ni (0≦x≦1, 0≦y≦1, 0≦z≦1).
 
A dielectric  3  having a high relative dielectric constant ε r &gt;20 is provided on the lower interdigitated electrode  4 . The dielectric  3  may comprise, for example, Pb(Zr x Ti 1-x )O 3  (0≦x≦1) with and without excess lead,
   (Pb,Ba)(Mg ⅓ Nb ⅔ ) x (Zn ⅓ Nb ⅔ ) y Ti z O 3  (0≦x≦1, 0≦y≦1, 0≦z≦1),   Ba 1-x Sr x TiO 3  (0≦x≦1),   Pb 1-1.5y La y (Zr x Ti 1-x )O 3  (0≦x≦1, 0≦y≦0.2),   SrTi 1-x Zr x O 3  (0≦x≦1),   (Zr,Sn)TiO 4 ,   Ta 2 O 5  with Al 2 O 3  dopants,   Pb 1-αy La y TiO 3  (0≦y≦0.3, 1.3≦x≦1.5),   (Pb,Ca)TiO 3 ,   BaTiO 3  with and without dopants,   Ba 2 Ti 9 O 20 ,   CaSm 2 Ti 5 O 14 ,   TiZr 0.8 Sn 0.2 O 4 ,   Ba 2 Ti 8.53 Zr 0.50 Mn 0.01 O 20 ,   SrZr x Ti 1-x O 3  (0≦x≦1) with and without Mn dopants,   BaZr x Ti 1-x O 3  (0≦x≦1),   Ba 1-y Sr y Zr x Ti 1-x O 3  (0≦x≦1, 0≦y≦1),   SrTiO 3  doped with, for example, La, Nb, Fe or Mn,   (BaTiO 3 ) 0.18-0.27 +(Nd 2 O 3 ) 0.316-0.355 +(TiO 2 ) 0.276-0.355 +(Bi 2 O 3 ) 0.025-0.081 +x ZnO,   CaZrO 3 ,   CaTiO 3 +CaTiSiO 5 ,   (Sr,Ca)(TiZr)O 3 ,   (Sr,Ca,M)(Ti,Zr)O 3  (M=Mg or Zn),   (Sr,Ca,Cu,Mn,Pb)TiO 3 +Bi 2 O 3 ,   BaO—TiO 2 —Nd 2 O 3 —Nb 2 O 5 ,   (Ba,Ca)TiO 3 +Nb 2 O 5 , Co 2 O 3 , MnO 2 ,   TiO 2 ,   BaO—PbO—Nd 2 O 3 —TiO 2 ,   Ba(Zn,Ta)O 3 ,   BaZrO 3 ,   Nd 2 T 2 O 7 ,   PbNb x (Zr 0.6 Sn 0.4 ) 1-y Ti y )) 1-x O 3  (0≦x≦0.9, 0≦y≦1),   Pb(Mg ⅓ Nb ⅔ )O 3 ] x —[PbTiO 3 ] 1-x  (0≦x≦1),   (Pb,Ba,Sr)(Mg ⅓ Nb ⅔ ) x Ti y (Zn ⅓ Nb ⅔ ) 1-x-y O 3  (0≦x≦1, 0≦y≦1), x+y≦1)   a) Pb(Mg ½ W ½ )O 3      b) Pb(Fe ½ Nb ½ )O 3      c) Pb(Fe ⅔ W ⅓ )O 3      d) Pb(Ni ⅓ Nb ⅔ )O 3      e) Pb(Zn ⅓ Nb ⅔ )O 3      f) Pb(Sc ½ Ta ½ )O 3  
 
as well as combinations of the compounds a) to f) with PbTiO 3  and Pb(Mg ⅓ Nb ⅔ )O 3 . An upper interdigitated electrode  5  is provided on the dielectric  3 , which electrode comprises, for example, Al,
   Al doped with Cu,   cu,   W,   Pt,   Ni,   Pd,   Pd/Ag,   TiW/Al,   Ti/Pt,   Ti/Ag,   Ti/Ag/TiIr,   Ti/Ag x Pt 1-x  (0≦x≦1),   Ti/Ag/Pt x Al 1-x  (0≦x≦1),   Ti/Ag x Pt 1-x /Ir (0≦x≦1),   Ti/Ag/(Ir/IrO x ) (0≦x≦2),   Ti/Ag/Ru x Pt 1-x  (0≦x≦1),   Ti/Pt x Al 1-x /Ag/Pt y Al 1-y  (0≦x≦1, 0≦y≦1),   Ti/Ag/Pt y (RhO x ) 1-y  (0≦x≦2, 0≦y≦1),   Ti/Ag/Pt x Rh 1-x  (0≦x≦1),   Ti/Ag x Pt 1-x /(Ir/IrO y ) (0≦x≦1, 0≦y≦2),   Ti/Ag x Pt 1-x /Pt y Al 1-y  (0≦x≦1, 0≦y≦1),   Ti/Ag/Ti,   Ti/Ni/ITO or   Ni x Cr y Al z /Ni (0≦x≦1, 0≦y≦1, 0≦z≦1)   

   Alternatively, the dielectric  3  may comprise multiple layers, for example double, triple, or quadruple layers. 
   In addition, a multiple layer structure may be implemented with three or more interdigitated electrodes in staggered arrangement. 
     FIG. 2  shows such a multiple layer arrangement with three staggered interdigitated electrodes  41 ,  42 , and  51 , and two dielectrics  31  and  32 . In this embodiment of the thin film capacitor according to the invention, a first dielectric  31  is disposed over a first interdigitated electrode  41 , over this a second interdigitated electrode  51  covered by a second dielectric layer  32 , and a third interdigitated electrode  42 . The first interdigitated electrode  41  and the third interdigitated electrode  42  are connected in parallel. 
   Embodiments of the invention which represent examples of how the invention may be realized in practice will now be explained in detail below. 
   Embodiment 1: 
   A carrier substrate  1  of glass is provided with a barrier layer  2  of TiO 2 . A lower interdigitated electrode  4  of Ti/Pt is provided on this barrier layer  2 . A dielectric  3  of BaTiO 3  is disposed over the lower interdigitated electrode  4 . An upper interdigitated electrode  5  of Pt is provided on said dielectric  3 . 
   Embodiment 2: 
   A carrier substrate  1  of glass is provided with a barrier layer  2  of TiO 2 . A lower interdigitated electrode  4  of Ti/Pt is provided on this barrier layer  2 . A dielectric  3  of Pb(Zr 0.53 T 0.47 )O 3  doped with lanthanum is disposed over the lower interdigitated electrode  4 . An upper interdigitated electrode  5  of Pt is provided on said dielectric  3 . 
   Standard monolayer capacitors are also manufactured in the same manufacturing process. The results of three tests are summarized in Table 1 below. 
   
     
       
             
           
             
             
             
             
             
           
             
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Standard Monolayer Capacitor with 20 V/μm and 13 nF/mm 2   
             
           
        
         
             
                 
               Test 1 
               Test 2 
               Test 3 
               Average 
             
             
                 
                 
             
           
        
         
             
               Rel. Dielectric Constant 
               1120 
               1060 
               1070 
               1083 
             
             
               ε r   
             
             
               Dielectric [μm] 
               0.754 
               0.784 
               0.702 
               0.747 
             
             
               Op. Voltage U rated  [V] 
                 
                 
                 
               15 
             
             
                 
             
           
        
       
     
   
                                 TABLE 2               Parameters for the interdigitated electrodes                                    Number of Fingers:   12           Number of Gaps:   11           Length of Finger Overlap [μm]:   850           Total Overlap Length [μm]:   9350                        
Table 3 shows the average capacitance values C and the operating voltages U rated  for thin film capacitors with interdigitated electrodes (parameters in accordance with Table 2) and a lanthanum-doped PZT dielectric (layer thicknesses in accordance with Table 1).
 
   
     
       
             
           
             
             
             
           
             
             
             
           
         
             
               TABLE 3 
             
           
           
             
                 
             
             
               Average Capacitance Values C of Thin Film Capacitors with Interdigitated 
             
             
               Electrodes and Lanthanum-Doped PZT Dielectric Layers. 
             
           
        
         
             
               Finger Interspacing [μm] 
               Capacitance C [pF] 
               Op. Voltage U rated  [V] 
             
             
                 
             
           
        
         
             
               10 
               6.3 
               200 
             
             
               5 
               10.8 
               100 
             
             
               3 
               17.5 
               60