Abstract:
A solid-state imaging apparatus has an imaging unit which is partly shielded against incident light to produce an optically shielded signal. A memory unit is provided for storing the optically shielded signal as a dark state signal during one horizontal scanning period. A line defect signal representative of a line defect present in the imaging unit is stored in the memory unit during the one horizontal scanning period. An optical signal of the imaging unit and a dark state signal stored in the memory unit during the one horizontal scanning period are subtracted so that the line defect signal contained in the optical signal of the imaging unit and the dark state signal are cancelled out to produce a signal having no line defect.

Description:
BACKGROUND OF THE INVENTION 
     Generally, a solid-state imaging apparatus such as an image pickup apparatus or an image sensor is constituted by a light receiving section for picking up an optical image signal and a shifting section for shifting a picked-up image signal. If various defects incident to the manufacturing process of the solid-state imaging apparatus take place in the light receiving section or the shifting section, black or white lines in the form of a black and white stripe pattern is displayed on the screen, thereby degrading the quality a picture reproduced thereon. When the light receiving section is constituted by PN photodiodes, for example, the defective picture is thought due to a large leakage in the PN photodiode which results from defects in a diffused layer caused in the manufacturing process. The large leakage causes excessive carriers to flow into shifting stages via transfer MOS transistors connected thereto and in addition, the excessive carriers prevailing in one stage of the shifting section immigrate into adjacent stages, resulting in a so-called overflow. If the overflow carriers prevail in the shifting section in one column, the one column is displayed as a white line on the screen. 
     When the shifting section is constituted by charge transfer devices such as a BBD or CCD device, irregularities in the thickness of an insulating oxide film or formation of pinholes in the insulating oxide film may be produced in the manufacturing process. The pinholes thus formed in the insulating film cause the transfer pulse voltage to be sent to the shifting stage as a spurious information signal. The spurious information signal is added to optical information and displayed as a defective black or white line on the screen. 
     Various approaches have been tried to improve the manufacturing process in order to eliminate the defective stripe pattern on the screen incident to the manufacting a process, however difficulties in obtaining a high yield rate of production of the solid-state imaging apparatus have been encountered as such an apparatus occupies a much larger area, e.g., several to ten square mm, than other IC circuits. Accordingly, for correcting the stripe pattern it has also been proposed to employ an external circuit which detects the position of a line defect and corrects the same. This method uses an ROM (Read Only Memory) for storing the position and size of a line defect. More particularly, the size of the line defect is quantized into a digital value and stored in the ROM. Then, a portion of an image signal corresponding to the position of the line defect and the information from the ROM are differentiated to correct the line defect. This method is, however, disadvantageous as it requires the provision of separate ROMs for separate devices and a complicated external circuit. 
     Essentially, a solid-state imaging apparatus is a finely fabricated, large-area integrated circuit device and if subjected to defects in the light receiving section caused in the manufacturing process, it suffers from line defects such as white lines or black lines displayed on the screen. 
     Line defects are displayed as black or white lines on the screen even when the light receiving section of the solid-state imaging apparatus is not irradiated with light. If the solid-state imaging apparatus is provided with a light receiving section for picking up an optical signal representative of an optical object which is usually converted into an electric signal and a light shielded section shielded from the incident light, it is possible to obtain a signal representative of the line defect through the light shielded section and a signal representative of a mixture of optical signal and line defect through the light receiving section. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of this invention to provide a solid-state imaging apparatus which can eliminate a line defect signal contained in an optical signal from a light receiving section by reading out, upon reading out of the optical signal from the light receiving section, the difference between the optical signal and the line defect signal which has been derived from a signal from the light shielded section and stored in a memory unit during reading out of the optical signal. 
     In the solid-state imaging apparatus, the received optical image signals which are produced by a two-dimensional image pick-up surface of the apparatus are taken out as a time sequential signal by horizontally and vertically scanning, the picked-up optical signals representative of the object being read out sequentially on a time basis. According to the invention, the solid-state imaging apparatus comprises a light receiving section for picking up the optical signal and a light shielded section for shielding the incident light. During the initial phase of the vertical scanning, signals from the light shielded section are transferred to a memory unit and stored therein as line defect signals. Then, during the horizontal scanning of the light receiving section, the memory unit is also scanned and signals of the light receiving section and the memory unit are differenced to correct the line defect. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a first embodiment of the invention which incorporates a shift register for horizontal scanning. 
     FIG. 2 is a wave-form chart to show clock signals and essential wave-forms in the embodiment of FIG. 1. 
     FIG. 3 is a schematic diagram of a second embodiment of the invention which incorporates charge coupling devices for horizontal scanning. 
     FIG. 4 is a wave-form chart to show clock signals and essential wave-forms in the embodiment of FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a first preferred embodiment of the invention will be described. A solid-state imaging apparatus as schematically shown in FIG. 1 generally comprises an imaging unit 1 including a light receiving section (image pickup section) and a light shielded section 2 comprising optically-shielded photodiodes to be described later, a scanning register 3 for generating sequential scanning pulses, and a differential amplifier 4 for producing the difference between a photoelectric signal and a signal stored in a capacitor to be described later. Of photodiodes D 11  to D n5  constituting the imaging unit, the photodiodes of groups D 11  to D 15 , D 21  to D 25 , . . . , D n1  to D n5  are respectively arranged in columns in a photodiode array. Photodiodes D 11  to D 14 , D 21  to D 24  . . . D n1  to D n4  are in the light receiving section of imaging unit while photodiodes D 15  to D n5  are in the light shielded section 2. Vertical shifting sections L 1  to L n  comprise BBDs. Each vertical shifting section includes the same number of stages as that of the photodiodes in one group. Photoelectric signals from each of the photodiode groups D 11  to D 15 , D 21  to D 25  . . . , D n1  to D n5  are simultaneously transferred to the stages of each of the vertical shifting sections, and the vertical shifting section shifts vertically the photoelectric signals transferred thereto. Transistors T r11  to T rn7  are MOS transistors, MOS transistors T r11 , T r21  . . . , T rn1  are coupled together with their gates connected in common to a clock line a, and when timing pulses are applied to the clock line a, the photoelectric signals from the vertical shifting sections L 1  to L n  are stored in gate capacitances (not shown) of MOS transistors T r13 , T r23 , . . . , T rn3 . MOS transistors T r12 , T r22 , . . . , T rn2  are coupled together with their gates connected in common to a clock line b, and when timing pulses are applied to the clock line b, power supply voltage from a power supply line V cc1  is applied via the MOS transistors T r12 , T r22 , . . . , T rn2  to the gate capacitances of MOS transistors T r13 , T r23 , . . . , T rn3  and stored therein. MOS transistors T r14 , T r24 , . . . , T rn4  and T r17 , T r27 , . . . , T rn7  are connected at their gates to the scanning register 3, and transistors are sequentially turned on such as T r14  and T r17  →T r24  and T r27  →. . . →T rn4  and T rn7 . MOS transistors T r15 , T r25 , . . . , T rn5  are coupled together with their gates connected in common to a clock line c and upon application of pulses to the clock line c, the signals stored in the gate capacitors of the MOS transistors T r13 , T r23 , . . . , T rn3  are transferred to capacitors C 1 , C 2 , . . . , C n  and stored and held therein. Symbols V cc1 , V cc2  and V cc3  designate power supply lines. 
     An operational description will be given of the solid-state imaging apparatus of FIG. 1 with reference to a wave-form chart as shown in FIG. 2. At first, clock pulses φ v1  and φ v2  are sequentially applied to the imaging unit 1 of the solid-state imaging apparatus. In particular, pulses p of the clock pulses φ v1  and φv 2  are timed to transfer photoelectric signals from the photodiodes D 11  to D n5  to the stages of the vertical shifting sections L 1  to L n , and the photoelectric signals are delivered out of the respective vertical shifting sections L 1  to L n  one by one in parallel at timing of pulses q, leaving the imaging unit 1 of the solid-state imaging apparatus. These output signals are timed to clock pulse a&#39; applied to the clock line a so as to be stored in the gate capacitances of the MOS transistors T r13 , T r23 , . . . , T rn3 . In advance of such reading, charges at the gate capacitances of the MOS transistors T r13 , T.sub. r23, . . . , T rn3  are required to be reset by applying clock pulse b&#39; to the clock line b each one horizontal scanning period. After the storing of the signals from the optically shielded photodiodes D 15 , D 25 , . . . , D n5  in the light shield section 2 in the gate capacitance of the MOS transistors T r13 , T r23 , . . . , T rn3 , they are transferred to the capacitors C 1 , C 2 , . . . , C n  and stored therein by applying clock pulse c&#39; to the clock line c. It is to be noted that in place of one line or row of the optically shielded photodiode array as exemplified in the foregoing embodiment, two lines of shielded photodiode arrays may be arranged in the case of interlace scanning. 
     In this manner, in response to the first timing signal, only the signals from the optically shielded photodiodes are transferred to the capacitors C 1 , C 2 , . . . , C n  from the vertical shifting sections and these remain stored during one field or frame of the screen. Thereafter, as the clock pulses a&#39; and b&#39; are applied to the clock lines a and b each one horizontal scanning period, photo-information from the imaging unit 1 of the solid-state imaging apparatus is stored in the gate capacitances of the MOS transistors T r13 , T r23 , . . . , T rn3 . On the other hand, start pulse d is applied to the scanning register 3 each one horizontal scanning period so that clock pulses e and e can be fed to the scanning register 3. Then, the scanning register 3 sequentially produces drive pulses which are connected to turn on the pairs of MOS transistors T r14  and T r17 , T r24  and T r27 , . . . , T rn4  and T rn7  sequentially. When the pair of MOS transistors T r14  and T r17  are turned on, the photoelectric signal stored in the gate capacitances of the MOS transistor T r13  is sent to the positive terminal of the differential amplifier 4 and the signal of the optically shielded photodiode which has been stored in the capacitor C 1  is sent to the negative terminal of the differential amplifier 4, thus causing the differential amplifier 4 to produce a difference output. Assuming now that uniform defective charge is present on the respective stages of vertical shifting section L 1 , the sum of the photoelectric signal and defect signal is stored in the gate capacitance of the MOS transistor T r13  and only the defect signal is stored in the capacitor C 1 . Accordingly, the differential amplifier 4 produces the output containing the photoelectric signal alone. Next, with the MOS transistors T r24  and T r27  turned on, the differential amplifier 4 produces only the photoelectric signal output as in the case of the MOS transistors T r14  and T r17  being turned on. By repeating the above operation, a series of signals removed of the defect signal can be delivered out of the differential amplifier 4 when the MOS transistors T rn4  and T rn7  are finally turned on. 
     To detail the operation set forth above, reference is made to pulses f and g as shown in FIG. 2. It is assumed that defect is present on only one of the vertical shifting sections L 1  to L n . Then, during the first one horizontal scanning, i.e., period T 1 , a signal in the form of pulse f is derived from the optically shielded photodiodes in the shield section 2, leaving the imaging unit 1 of the solid-state imaging apparatus. Because of complete absence of the photoelectric signal during period T 1 , only one defect signal r is produced from the imaging unit. During the subsequent one horizontal scanning, i.e., period T 2 , signal s is added to a photoelectric signal at a portion of the pulse f corresponding to the defect signal r. The same operation repeats during periods T 3 , T 4 , . . . . In accordance with the invention, since the defect signal produced during period T 1  is stored in the capacitors C 1  to C n  and subjected to subtraction by signals produced during period T 2  and ensuing periods, a signal g removed of the defect signal can be obtained from the differential amplifier 4. 
     The invention can be implemented by using a charge transfer device such as a CCD or BBD in the horizontal scanning circuit. 
     A second embodiment as shown in FIG. 3 uses charge transfer devices such as a CCD in the horizontal scanning circuit. In FIG. 3, the same elements as those in FIG. 1 are designated by the same reference numerals and not detailed herein. There are shown MOS transistors T r18 , T r28 , . . . and T rn8 , T r19 , T r29 , . . . and T rn9 , T r1a , T r2a , . . . and T rna , T r1b , T r2b , . . . and T rnb , and T r1c , T r2c , . . . and T rnc , charge coupled devices CC1 and CC2 for horizontal scanning, and clock lines h to l. The MOS transistors T r18 , T r28 , . . . , T rn8  are adapted to control transfer of image signals from the imaging unit to the charge coupling device CC1. Pairs of MOS transistors T r1a  and T r1b , T r2a  and T r2b , . . . , T rna  and T rnb  are connected in source follower manner. DC voltage is applied to the clock line k to control current flowing through the transistors T r1b , T r2b , . . . , T rnb . The source-follower transistors are connected to a power supply through clock line j. 
     The vertical shift in the imaging unit is driven by clock pulses φ v1  and φv 2  as in FIG. 1. The charge coupled devices CC1 and CC2 are driven by clock pulses φ H1  and φ H2 . Signal charges are transferred, under the control of the transistors T r19 , T r29 , . . . , T rn9 , from the device CC1 to capacitors C 1 , C 2 , . . . C n  and stored therein. The transistors T r1c , T r2c , . . . , T rnc  constitute a control gate for connecting outputs of the source-follower transistor pairs T r1a  and T r1b , . . . , T rna  and T rnb  to the device CC2. 
     The imaging apparatus of FIG. 3 operates as will be described with reference to a wave-form chart shown in FIG. 4. Description will first be given of the operation during period T 1  which is in advance of driving the vertical shifting sections. The device CC1 is always kept operating. Since there is no pulse applied to the clock line h during period T 1 , the device CC1 maintains the state in the absence of input signals, i.e., high level state. On the other hand, the transistors T r19 , T r29 , . . . T rn9  are turned on by pulse i&#39; during period T 1  so that the capacitors C 1 , C 2 , . . . , C n  for storing signals are reset to high level. 
     Also, during period T 1 , no pulse l&#39; is applied to the clock line l to disable the transistors T r1c , T r2c , . . . , T rnc  and the device CC2 thus receiving no input signals is also reset to high level. 
     During subsequent period T 2 , the vertical shifting sections L 1 , L 2 , . . . , L n  initially send output signals. The output signal corresponds to a dark state signal from the optically shielded photodiodes as shown in FIG. 3. 
     During period T 2 , pulses h&#39;, i&#39; and l&#39; are applied to the clock lines h, i and l to turn on the transistors T r18  to T rn8 , T r19  to T rn9  and T r1c  to T rnc . As a result, the output signals of the imaging unit are sent to the device CC1 via the transistors T r18  to T rn8  and the signal charges are stored in the capacitors C 1  to C n  through the transistors T r19  to T rn9 . The charges thus stored and the capacitances of capacitors C 1  to C n  determine gate potentials of the transistors T r1a  to T rna , and charges are sent to the device CC2 in accordance with the gate voltages via the transistors T r1c  to T rnc . The dark state signal is representative of a line defect signal due to white and black lines in the imaging unit. 
     The signal from the light shield section 2 does not remain in the device CC1 and during timing period T 2 , the devices CC1 and CC2 produce outputs m and n as shown in FIG. 4. The outputs m and n are differentiated at the differential amplifier 4 to produce therefrom a signal 0 representative of only the line defect. During period T 3 , photoelectric signals in the imaging unit are vertically shifted. Then, pulse h&#39; is applied to the clock line h and image signals are allowed to come into the device CCD1. The image signal contains a line defect signal but in the absence of pulse i&#39;, the charged state of the capacitors C 1  to C n  remains unchanged. Pulse l&#39; is, however, applied to the clock line l during period T 3  and only the line defect signal under the dark state is again sent to the device CC2. During period T 3 , output signals of the devices CC1 and CC2 are passed through the differential amplifier 4 so that output n of the CC2 representative only of the line defect signal and output m of the CC1 representative of the image signal containing the line defect signal are differentiated, thereby producing only an image signal 0 as shown in FIG. 4. The charged state of the capacitors C 1  to C n  is changed by applying pulse i&#39; to the clock line i at the beginning of every one frame. 
     As described above, according to the invention, the solid-state imaging apparatus per se is so constructed that the line defects due to manufacturing process can be corrected and high quality images can be produced.