Abstract:
In some embodiments, vertical controlled side chip connection for 3D processor package is presented. In this regard, an apparatus is introduced having a substrate, a substantially horizontal, in relation to the substrate, integrated circuit device coupled to the substrate, and a substantially vertical, in relation of the substrate, integrated circuit device coupled to the substrate and adjacent to one side of the substantially horizontal integrated circuit device. Other embodiments are also disclosed and claimed.

Description:
FIELD OF THE INVENTION 
       [0001]    Embodiments of the present invention generally relate to the field of integrated circuit packaging and, more particularly, to vertical controlled side chip connection for 3D processor package. 
       BACKGROUND OF THE INVENTION 
       [0002]    Computing devices are expected to have more and more features and be available in ever smaller form factors. This raises problems such as finding space to route traces along a printed circuit board (PCB) and integrating functionality into silicon integrated circuit devices. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which: 
           [0004]      FIG. 1  is a graphical illustration of a cross-sectional view of an integrated circuit package with vertical controlled side chip connections, in accordance with one example embodiment of the invention; 
           [0005]      FIG. 2  is a graphical illustration of a cross-sectional view of an alternate integrated circuit package with vertical controlled side chip connections, in accordance with one example embodiment of the invention; 
           [0006]      FIG. 3  is a graphical illustration of an overhead view of an alternate integrated circuit package with vertical controlled side chip connections, in accordance with one example embodiment of the invention; and 
           [0007]      FIG. 4  is a block diagram of an example electronic appliance suitable for implementing vertical controlled side chip connection for 3D processor package, in accordance with one example embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention. 
         [0009]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. 
         [0010]      FIG. 1  is a graphical illustration of a cross-sectional view of an integrated circuit package with vertical controlled side chip connections, in accordance with one example embodiment of the invention. As shown, integrated circuit package  100  includes one or more of vertical chip stack  102 , main chip stack  104 , vertical chip  106 , substrate  108 , vertical substrate  110 , vertical chips  112 - 116 , surface activated bond  118 , die backside metallization (DBM) connection  120 , die active metal layer  122 , DBM routing and/or pad  124 , through silicon via (TSV)  126 , wirebond  128 , underfill and solder bump connection  130 , and DBM surface activated bond  132 . 
         [0011]    Vertical chip stack  102  represents a group of integrated circuit devices, for example multi-core microprocessors, flash memory, network controllers, graphics controllers, etc., which are connected to and vertically aligned in relation with substrate  108 . Vertical chip stack  102  may be fabricated separately with vertical chips  112 - 116  coupled with vertical substrate  110  through conventional methods before being rotated and placed on substrate  108 . Vertical chip stack  102  may be coupled (electrically as well as mechanically) with substrate  108  and/or main chip stack  104 . In one embodiment, a surface activated bond  118  is formed between conductive surfaces on vertical substrate  110  and substrate  108 . In one embodiment, die backside metallization (DBM) connection  120  couples vertical chips  112  and  114 . DBM routing and/or pad  124  is coupled to die active metal layer  122  through through silicon via (TSV)  126 . In one embodiment, vertical chip stack  102  is electrically coupled with main chip stack  104  through wirebond  128 . The electrical connection between vertical chip stack  102  and main chip stack  104  may be used for power or data transmission. 
         [0012]    Main chip stack  104  represents horizontally stacked integrated circuit devices of all types. 
         [0013]    Substrate  108  provides mechanical support and signal routing for attached integrated circuit devices. In one embodiment substrate  108  is a multi-layer organic substrate. In another embodiment, substrate  108  is a ceramic substrate. 
         [0014]    Vertical chip  106  may be coupled with substrate  108  through solder bump connection  130  with or without underfill support and by main chip stack  104  through any electrical interconnection including but not limited to DBM surface activated bond  132 . 
         [0015]      FIG. 2  is a graphical illustration of a cross-sectional view of an alternate integrated circuit package with vertical controlled side chip connections, in accordance with one example embodiment of the invention. As shown, integrated circuit package  200  includes one or more of main die stack  202 , vertical die  204 , vertical die  206 , substrate  208 , DBM surface activated bond  210 , solder bump connections  212 , wirebond  214 , surface activated bond  216 , die backside metallization (DBM) connection  218 , through silicon via (TSV) connection  220 , die active metal layer  222  and DBM routing and/or pad  224 . 
         [0016]    Main die stack  202  is comprised of horizontally stacked integrated circuit devices joined by multiple connections. Some chips in main die stack  202  are connected through die backside metallization (DBM), such as die backside metallization (DBM) connection  218 . Die active metal layer  222  is connected to the DBM routing and/or pad through through silicon via (TSV)  220 . 
         [0017]    Vertical die  204  is coupled with main die stack  202  through surface activated bond  210  and is coupled with substrate  208  through wirebond  214 . 
         [0018]    Vertical die  206  is coupled with main die stack  202  through interconnection between solder bump connections  212  and DBM routing and/or pad  224 . Vertical die  206  is coupled with substrate  208  through surface activated bond  216 . 
         [0019]      FIG. 3  is a graphical illustration of an overhead view of an alternate integrated circuit package with vertical controlled side chip connections, in accordance with one example embodiment of the invention. As shown, integrated circuit package  300  includes substrate  302 , main die stack  304  and vertical devices  306 - 312 . While connections are not shown in  FIG. 3  for simplicity, main die stack  304  includes any number of integrated circuit devices horizontally stacked on substrate  302 . Vertical devices  306 - 312  are vertically adjacent to all four sides of main die stack  304 . Vertical devices  306 - 312  may have electrical and/or mechanical connections to substrate  302  and/or main die stack  304 . 
         [0020]      FIG. 4  is a block diagram of an example electronic appliance suitable for implementing vertical controlled side chip connection for 3D processor package, in accordance with one example embodiment of the invention. Electronic appliance  400  is intended to represent any of a wide variety of traditional and non-traditional electronic appliances, laptops, desktops, servers, cell phones, wireless communication subscriber units, wireless communication telephony infrastructure elements, personal digital assistants, set-top boxes, or any electric appliance that would benefit from the teachings of the present invention. In accordance with the illustrated example embodiment, electronic appliance  400  may include one or more of processor(s)  402 , memory controller  404 , system memory  406 , input/output controller  408 , network controller  410 , and input/output device(s)  412  coupled as shown in  FIG. 4 . Processor(s)  402 , or other integrated circuit components of electronic appliance  400 , may be integrated into packages described previously as an embodiment of the present invention. 
         [0021]    Processor(s)  402  may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, processors(s)  402  are Intel® compatible processors. Processor(s)  402  may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system. 
         [0022]    Memory controller  404  may represent any type of chipset or control logic that interfaces system memory  406  with the other components of electronic appliance  400 . In one embodiment, the connection between processor(s)  402  and memory controller  404  may be referred to as a front-side bus. In another embodiment, the connection between processor(s)  402  and memory controller  404  may be a serial point-to-point connection. 
         [0023]    System memory  406  may represent any type of memory device(s) used to store data and instructions that may have been or will be used by processor(s)  402 . Typically, though the invention is not limited in this respect, system memory  406  will consist of dynamic random access memory (DRAM). In one embodiment, system memory  406  may consist of Rambus DRAM (RDRAM). In another embodiment, system memory  406  may consist of double data rate synchronous DRAM (DDRSDRAM). 
         [0024]    Input/output (I/O) controller  408  may represent any type of chipset or control logic that interfaces I/O device(s)  412  with the other components of electronic appliance  400 . In one embodiment, I/O controller  408  may be referred to as a south bridge. In another embodiment, I/O controller  408  may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003. 
         [0025]    Network controller  410  may represent any type of device that allows electronic appliance  400  to communicate with other electronic appliances or devices. In one embodiment, network controller  410  may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller  410  may be an Ethernet network interface card. 
         [0026]    Input/output (I/O) device(s)  412  may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance  400 . 
         [0027]    In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form. 
         [0028]    Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.