Abstract:
An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the interface apparatus to be programmed to operate as a transmitter or a receiver with selectable device interface modes. When operating as a transmitter, the interface apparatus combines and compresses the system data bus, clocks, and control signals to match the available width of the parallel data bus. When operating as a receiver, the interface receives signals from the parallel data bus and restores the original signals which were combined and compressed. The device interface modes are selectable to be compatible in different device and circuit configurations.

Description:
TECHNICAL FIELD  
       [0001]     The present invention is related to integrated circuits. More specifically, the present invention is a system and method for interfacing a number of data, clock, and control lines with a parallel bus.  
       BACKGROUND ART  
       [0002]     Serial interfaces are widely employed for the exchange of digital data between electronic circuits and devices. Some advantages of the serial interface include low pin and wire count for the interconnection medium, low susceptibility to electromagnetic interference (EMI), and low power consumption. A popular application for a serial digital interface (SDI) is the connection of a host computer or processor with an imaging device, a display device such as a Liquid Crystal Display (LCD), or a camera. The SDI provides a means for data exchange between the devices, enabling, for example, the transfer of an image from a camera to a personal computer for sharing, archiving, or modification.  
         [0003]     Before data can be shared across a serial link, the data must be formatted into a configuration which matches the particular protocol specifications for the link, and then passed to a serializer modulator circuit. The serializer modulator accepts data in discrete units, typically bytes or words, and translates the data into a series of bits which are conveyed sequentially across the interconnection medium. At the receiving end of the medium, a deserializer demodulator accepts the series of bits and recombines them to recreate the original sequence of data units. The action of the serializer modulator is typically placed under control of a system clock, which determines the rate at which data units are converted by the serializer into a bit sequence and subsequently sent over the interconnection medium. Similarly, the deserializer demodulator accepts the bit sequence at the rate sent by the serializer modulator, and passes the recreated data to the system at a rate controlled by a synchronization clock. In some cases, a clock signal is sent as part of the serial data conveyed by the interface, either embedded within the serialized data, or by means of a separate line dedicated to the clock signal.  
         [0004]     The construction of serializer/deserializer (SERDES) circuits is well known in the art. The usual method of interfacing an electronic circuit to the modulator and demodulator circuits within the SERDES is to provide separate interface circuits for a transmit interface and a receive interface. These separate interface circuits each usually communicate with the modulator and demodulator circuits by means of a parallel bus. Furthermore, the interface circuits are typically specific to an intended application. That is, an interface circuit may be designed to convey only 8-bit data or only 16-bit data. In addition, the circuits are usually configured to accommodate a single mode of operation. For example, if the interface is designed to send a clock signal in addition to the data, the circuit cannot be operated without the included clock signal.  
         [0005]     It is generally desirable to maximize the performance of a serial interface in terms of bit rate, power consumption, or other performance attributes. One method of achieving this objective is to reduce the number of bits which must be sent over the interface by employing data compression. Often times, data compression is accomplished by software means or by dedicated circuitry to implement a compression algorithm.  
         [0006]     What is needed, therefore, is an apparatus and method for interfacing a host circuit to a parallel bus which extends the art by providing both transmit and receive capability, configuration flexibility, and data compression within a single circuit. Additionally, incorporation of data compression enables the possibility of using Return-To-Zero (RTZ) or Return-To-One (RTO) formats for the serial data. This, in turn, opens up a wider range of transmission techniques including Pulse Width Modulation (PWM) and derivatives thereof. In this manner, the usefulness of serial interfaces is enhanced. It will also be appreciated by those skilled in the art that such a capability has other application to data transfer both within and between electronic circuits and devices for example, providing a method of increasing an effective bandwidth of an on-chip parallel bus, while increasing the flexibility and options for interfacing circuit blocks to the parallel bus.  
       SUMMARY OF THE INVENTION  
       [0007]     The invention is an apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus. By setting configuration bits the interface apparatus may be programmed to operate as a transmitter or a receiver with selectable device interface modes. When operating as a transmitter, the interface apparatus combines and compresses the system data bus, clocks, and control signals to match the available width of the parallel data bus. When operating as a receiver, the interface receives signals from the parallel data bus and restores the original signals which were combined and compressed. The device interface modes are selectable to be compatible with different device and circuit configurations. In an exemplary embodiment of the invention, the interface apparatus is configured to operate in a microprocessor mode suitable for interfacing a graphical display with a microprocessor, and in an imager mode suitable for interfacing a camera with a microprocessor.  
         [0008]     In the discussions which follow, an interface block operating in the transmit mode may also be referred to as a transmit block. Analogously, an interface block operating in the receive mode may also be referred to as a receive block. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a block diagram of a serializer/deserializer system which utilizes the present invention.  
         [0010]      FIG. 2   a  is a block diagram of the present invention configured to transmit data in a microprocessor mode.  
         [0011]      FIG. 2   b  is a block diagram of the present invention configured to transmit data in an imager mode.  
         [0012]      FIG. 2   c  is a block diagram of the present invention configured to receive data in a microprocessor mode.  
         [0013]      FIG. 2   d  is a block diagram of the present invention configured to receive data in an imager mode.  
         [0014]      FIG. 3  is a timing diagram illustrating an operating configuration of a loopback mode in accordance with the present invention.  
         [0015]      FIG. 4  is a data pass through synchronization pipeline according to an exemplary embodiment of the present invention.  
         [0016]      FIG. 5  is a block diagram of a microprocessor system which utilizes the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]     With reference to  FIG. 1 , a serializer/ deserializer system  100  utilizing an exemplary embodiment of the present invention comprises an interface block  110 , a clock divider  140 , a demodulator  160 , and a modulator  170 . The interface block  110  is further comprised of a configurable interface  120  and a configuration block  130 . Data signals D[15:0] are connected to the interface block  110  and include a data bus which is used as a 16-bit data bus when operating the interface in a microprocessor mode. Alternately, the data signals D[7:0] are used as an 8-bit data bus when operating the interface in an imager mode, with the remaining data signal lines D[15:8] providing a general purpose input/output (GPIO) capability.  
         [0018]     A first chip select signal/horizontal sync signal shared line CS 1 /HS is connected to the configurable interface  120  providing a connection for a first chip select signal CS 1  when operating the interface in the microprocessor mode and providing a connection for a horizontal sync signal HS when operating the interface in the imager mode. A second chip select signal CS 2  is connected to the configurable interface  120 , providing means for sending and receiving the second chip select signal CS 2  when operating the interface in the microprocessor mode.  
         [0019]     A register select signal/pixel clock signal shared line RS/PCLK is connected to the configurable interface  120  providing a connection for a register select signal RS which is used to distinguish between display data and command data when operating the interface in the microprocessor mode. When operating the interface in the imager mode, the register select signal/pixel clock signal shared line RS/PCLK provides a connection for a pixel clock signal PCLK.  
         [0020]     A processor clock signal/vertical sync signal shared line ECLK/VS is connected to the configurable interface  120  providing a connection for a processor clock signal ECLK when operating the interface in the microprocessor mode, and providing a connection for a vertical sync signal VS when operating the interface in the imager mode. A serial clock signal is connected to the configuration block  130 . The serial clock signal may be utilized for the capture, resynchronization, or output of the serial data signal. A serial data signal is coupled to the configuration block  130  to provide means for setting and reading configuration bits which set the operating characteristics of the interface.  
         [0021]     A system clock signal is connected to the clock divider  140  which divides the system clock frequency by a factor of two in the exemplary embodiment. The divided system clock is connected to the demodulator  160  and the modulator  170 . The clock divider  140  is also connected to the serial interface clock signal CTXRX which is sent over the interconnection medium if required by the selected operating mode.  
         [0022]     The configurable interface  120  is connected to the demodulator  160  by an input parallel data bus  150 A, and to the modulator  170  by an output parallel data bus  150 B. In the exemplary embodiment, the input parallel data bus  150 A and the output parallel data bus  150 B each have a bus width of 18 bits. It will be appreciated by those skilled in the art that it is possible to design a data bus with a bi-directional signaling capability. Thus, in alternate embodiments of the present invention, input parallel data bus  150 A and output parallel data bus  150 B may share signal lines.  
         [0023]     Attention is now directed to  FIG. 2   a,  a block diagram of the interface block  110  configured to transmit data in the microprocessor mode according to the exemplary embodiment of the present invention. The configurable interface  120  further comprises a data synchronize/concatenate block  210  operating in a data pass through pipeline mode, a clock compress and synchronize/ regenerate block  220  operating in a clock/control signal compress and synchronize pipeline mode. When the interface block  110  is configured to transmit data in the microprocessor mode, information is received from a microprocessor by means of the data signals D[15:0], the register select signal RS, the first chip select signal CS 1 , the second chip select signal CS 2 , and the processor clock signal ECLK, for a total of 20 bits. The received information from the microprocessor is converted to 18-bit parallel data conveyed by the output parallel data bus  150 B.  
         [0024]     The configuration bits determine whether the interface block  110  is using the processor clock signal (ECLK) or a combination of the first chip select signal (CS 1 ) and the second chip select signal (CS 2 ) as a data capture clock. The configuration bits also determine whether the first chip select signal CS 1 , the second chip select signal CS 2 , and the processor clock signal ECLK are active high or active low.  
         [0025]     A data capture clock is selected to be either a rising edge or a falling edge of the processor clock signal ECLK, the first chip select signal CS 1 , or the second chip select signal CS 2 . Seventeen bits of data comprising data signals D[15:0] and register select signal RS are captured by the data synchronize/concatenate block  210  with the data capture clock, synchronized, and sent to a modulator by the output parallel data bus  150 B.  
         [0026]     The processor clock signal ECLK, the first chip select signal CS 1 , and the second chip select signal CS 2  are also captured by the clock compress and synchronize/regenerate block  220  with the data capture clock to indicate that valid data are in a synchronization pipeline to be discussed in greater detail with regard to  FIG. 4 , infra.  
         [0027]     When operating in the microprocessor mode, the interface block  110  encodes the first chip select signal CS 1 , the second chip select signal CS 2 , and processor clock signal ECLK into one bit of data. The one bit of data indicates which chip select is active. If neither the first chip select signal CS 1  nor the second chip select signal CS 2  is active, or if there is no active processor clock signal ECLK, then no data are transmitted across the serial link. The processor clock signal ECLK and the first and second chip select signals CS 1  and CS 2  are regenerated on the receiving unit using the system clock and delay elements, producing timing compatible with the external interface.  
         [0028]     The clock compress and synchronize/regenerate block  220  provides an 18 th  bit of data to the output parallel data bus  150 B. The 18 th  bit of data is a compression of the processor clock signal ECLK, the first chip select signal CS 1 , and the second chip select signal CS 2 . These signals signify the occurrence of a valid data cycle, and further indicate whether the processor is communicating with a first circuit associated with the first chip select signal CS 1  or with a second circuit associated with the second chip select signal CS 2 . Since the processor clock signal ECLK, the first chip select signal CS 1 , and the second chip select signal CS 2  are regenerated by a receive block, the information to be conveyed is which chip select signal is active. This is accomplished by setting the logic level of the 18 th  bit as follows: If the first chip select signal CS 1  is active, the 18 th  bit is set low; if the second chip select signal CS 2  is active, the 18 th  bit is set high.  
         [0029]     A clock signal is connected to the interface block  110  to provide a timing reference for data capture, data synchronization, and data output, to be explained, infra. A data ready signal is coupled to the interface block  110 . In the transmit mode, the data ready signal indicates that valid data are present on the output parallel data bus  150 B.  
         [0030]     Attention is now directed to  FIG. 2   b,  a block diagram of the interface block  110  configured to transmit data in the imager mode according to the exemplary embodiment of the present invention. The data synchronize/concatenate block  210  is further comprised of a first data cycle capture block  215 A, and a second data cycle capture block  215 B, each capable of capturing eight bits of data. When the interface block  110  is configured to transmit data in the imager mode, information is received from an imager by means of the eight data signal lines D[7:0], the horizontal sync signal HS, the vertical sync signal VS, and the pixel clock signal PCLK, for a total of 11 bits per data cycle. Information is captured from the imager in two data cycles and converted to 18-bit parallel data conveyed to a modulator by the output parallel data bus  150 B. The capture of two data cycles enables efficient use of the available data bandwidth by exploiting the full 18-bit data path available in microprocessor mode. The data capture clock is configured to be either a rising edge or a falling edge of the pixel clock PCLK. Sixteen bits of data are captured with two successive data capture clocks by the first data cycle capture block  215 A and the second data cycle capture block  215 B, synchronized, and sent to the modulator.  
         [0031]     The horizontal sync signal HS and the vertical sync signal VS are also captured with the data capture clock to indicate that valid data are in the synchronization pipeline ( FIG. 4 ). The horizontal sync signal HS and the vertical sync signal VS are sent once for every two data captures, thereby eliminating two data bits from the data to be sent. The horizontal sync signal HS and the vertical sync signal VS which are sent comprise the 17 th  and 18 th  bits of data on the output parallel data bus  150 B. The pixel clock signal PCLK is not sent but instead is regenerated by a receive block. The imager is configured to transfer bursts of data, stopping when the horizontal sync signal HS or the vertical sync signal VS are inactive. The interface block  110  takes advantage of breaks between the horizontal sync signal HS and the vertical sync signal VS: One 18-bit word with the horizontal sync signal HS low and the vertical sync signal VS set to a current value is sent across the link to signify the end of a horizontal sync signal HS burst. Subsequent data are not transferred when the horizontal sync signal HS is low to save power.  
         [0032]     Those skilled in the art will appreciate that the principle of capturing successive data cycles can be extended to capture more than two data cycles which may or may not be consecutive and that the output parallel data bus need not be constrained to a width of 18 bits in order to practice the present invention.  
         [0033]     Attention is now directed to  FIG. 2   c,  a block diagram of the interface block  110  configured to receive data in the microprocessor mode according to the exemplary embodiment of the present invention. In the microprocessor mode of operation, an 18-bit word received from the input parallel data bus  150 A is used to recover 20 signals comprising the data signals D[15:0], the register select signal RS, the first chip select signal CS 1 , the second chip select signal CS 2 , and the processor clock signal ECLK. In the receive mode, the data ready signal indicates that valid data are present on the input parallel data bus  150 A. The data signals D[15:0] and the register select signal RS are recovered by connecting corresponding signals from the input parallel data bus  150 A, thereby accounting for  17  of the  18  available signals. The processor clock signal ECLK, the first chip select signal CS 1 , and the second chip select signal CS 2  are recovered by the clock compress and synchronize/regenerate block  220  operating in a regenerate mode using the 18 th  bit from the input parallel data bus  150 A. The format of the processor clock signal ECLK, the first chip select signal CS 1 , and the second chip select signal CS 2  after recovery is determined by the configuration bits. Since only one bit is used to represent the processor clock signal ECLK, the first chip select signal CS 1 , and the second chip select signal CS 2  in combination, the signals may be regenerated in a different format than was used to encode the signals in the transmit block. The setup and hold timing of the processor clock signal ECLK, the first chip select signal CS 1 , and the second chip select signal CS 2  with relation to each other and to the data signals D[15:0] and with relation to the register select signal RS is recreated to be compatible with a destination microprocessor attached to the interface block  110 .  
         [0034]     Attention is now directed to  FIG. 2   d,  a block diagram of the interface block  110  configured to receive data in the imager mode according to the exemplary embodiment of the present invention. In the imager mode of operation, an 18-bit word received from the input parallel data bus  150 A is used to recover the signals comprising two sequential imager cycles of eight data signals D[7:0], the vertical sync signal VS, the horizontal sync signal HS, and the pixel clock signal PCLK, for a total of 22 bits of original data. The data signals D[7:0] are recovered by the data pass through/concatenate block  210  by storing 16 bits from the input parallel data bus  150 A corresponding to the desired data and transferring the stored bits out of the data synchronize/concatenate block  210  in two consecutive groups of eight bits. The clock compress and synchronize/regenerate block  220  recovers the vertical sync signal VS, the horizontal sync signal HS, and the pixel clock signal PCLK. The 17 th  and 18 th  bits from the input parallel data bus  150 A are used to recover the vertical sync signal VS and the horizontal sync signal HS. The pixel clock signal PCLK is regenerated using the system clock. The polarity of the vertical sync signal VS, the horizontal sync signal HS, and the pixel clock signal PCLK are determined by the configuration bits. Since the pixel clock signal PCLK is regenerated in the clock compress and synchronize/regenerate block  220 , its polarity and behavior, e.g., continuous or burst operation, may be different than employed at the transmit block.  
         [0035]     Attention is now directed to  FIG. 3 , a timing diagram illustrating the relationship between signals when the present invention is operating in a loopback mode commonly employed for the purpose of self-testing. The loopback mode illustrated corresponds to the system configured in the microprocessor mode of operation. The timing diagram is the product of a simulation of the internal logic of the serializer/deserializer system  100  ( FIG. 1 ). The simulation was performed with commercial logic simulators known as Verilog®-NC and Verilog®-XL and manufactured by Cadence Design Systems, Inc., San Jose, Calif., USA. Data values are presented in  FIG. 3  in hexadecimal notation. According to common practice known to those skilled in the art, an “X” indicates an unknown value. An asterisk “*” indicates the existence of a known value with insufficient space on the graphical display to represent the number. A hatch pattern “\\\” indicates a binary (single bit) signal with an unknown value.  
         [0036]     The top of the timing chart in  FIG. 3  shows the system clock ( FIG. 1 ) and the divided system clock (system clock/ 2 ). A signal LOOPBACK ENABLE shows the state of a loopback configuration bit. When LOOPBACK ENABLE is asserted HI (logic high) as shown in  FIG. 3 , the interface block  110  automatically switches from the transmit mode to the receive mode and back for on-chip loopback testing.  
         [0037]     In on-chip loopback testing, the interface block  110  switches from transmit to receive mode one serial clock cycle after it raises the data ready signal (FIGS.  2 A-D) and remains in receive mode for four system clock cycles: At event A 3  in  FIG. 3 , the data ready signal is observed to transition from logic low to high approximately concurrent with a rising edge of the serial clock. Signals D[15:0] IN, which represent the data signals D[15:0]  FIG. 2   a ) operating in the input mode, are latched by a data capture register to be discussed in greater detail with regard to  FIG. 4 , infra. The data capture process is initiated by input signals ECLK, CS 1 , or CS 2  when the interface is in the transmit mode. In the example shown the value associated with the signals D[15:0] IN at the time of capture is hexadecimal 0×1234; in 16-bit binary notation this value is 0001001000111000. The captured data appear as signal DATA_CAP[15:0], and are observed to equal the hexadecimal value 0×1234 after event A 3  occurs. After the data are captured they are resynchronized and converted to an 18-bit number by appending RS and a combined ECLK, CS 1 , and CS 2  signal. The resynchronized data appear in  FIG. 3  as the signal DATA_RESYNC[17:0] with hexadecimal value 0×48d0, corresponding to the 18-bit binary number 000100100011100000. The resynchronized data are passed to a data output register to be discussed in greater detail with regard to  FIG. 4 , infra. The data appear as signal 18BITOUT which corresponds to the parallel data signal in  FIG. 2A . The data from the signal 18BITOUT are sent to the modulator  170  ( FIG. 1 ) by means of the output parallel data bus  150 B ( FIGS. 1, 2A ) and subsequently looped back to the demodulator  160  ( FIG. 1 ). The DATA READY signal indicates that the 18-bit data are ready for the serializer block.  
         [0038]     After a time period t 1 , corresponding to one serial clock cycle, event B 3  occurs. At event B 3  a deserializer function control signal DSER transitions from low to high. Concurrently, a serializer function control signal SER transitions from high to low. The changes in the deserializer function control signal DSER and the serializer function control signal SER transition the interface block  110  from the transmit mode to the receive mode.  
         [0039]     During a time period t 2 , the demodulator  160  ( FIG. 1 ) deserializes the loopback data. An event C 3  signals the completion of this operation by transitioning a signal DMOD_VALID from low to high. The event C 3  indicates the presence of valid data on the input parallel data bus  150 A ( FIGS. 1, 2C ) as represented by the signal 18BITIN. Reference to  FIG. 3  and 18BITIN shows that the data value after the event C 3  is hexadecimal 0×48d0, corresponding to the loopback data provided to the modulator  160  ( FIG. 1 ). The two least significant bits are stripped from the data and used to recreate RS, ECLK, CS 1 , and CS 2 . The remaining sixteen bits comprise the signal D[15:0] OUT, which represent the data signals D[15:0] ( FIG. 2   c ) operating in the output mode. Reference to  FIG. 3  shows that the signal D[15:0] OUT has the value of hexadecimal 1234 during the period of operation corresponding to the receive mode, illustrating correct recovery of the original data.  
         [0040]     It is to be noted that during the receive interval identified in  FIG. 3 , the signals ECLK IN and ECLK OUT appear similar. During this portion of the loopback mode, the signals ECLK IN and ECLK OUT are tied together at a pad. During the transmit intervals identified in  FIG. 3 , the signals ECLK IN and ECLK OUT may differ, while the system is in a serialization mode and receiving data to the microprocessor.  
         [0041]     The receive mode persists for the time period t 3  shown in  FIG. 3 , corresponding to four system clock cycles, as described supra. At the end of the time period t 3 , an event D 3  occurs. At the event D 3  the deserializer function control signal DSER transitions from high to low. Concurrently, the serializer function control signal SER transitions from low to high. The changes in the deserializer function control signal DSER and the serializer function control signal SER transition the interface block  110  from the receive mode to the transmit mode.  
         [0042]     A unique aspect to the loopback configuration is the use of the same registers for both transmit and receive modes. In loopback designs known in the prior art, transmit and receive paths are activated simultaneously; thus, separate registers are employed for the transmit and the receive functions.  
         [0043]     With reference to  FIG. 4 , an exemplary three stage data pass through synchronization pipeline  400  is an alternative conceptual view of the configurable interface  120  ( FIG. 1 ) which includes a data capture register  410 , a data capture/resynchronization register  420 , a data out register  430 , a data capture signal line  440 , a data capture/resynchronization signal line  450 , and intervening logic blocks  460 A-E. The data capture/resynchronization register  420  is connected to the data capture register  410  and to the data out register  430 . A pipeline data in signal is connected to the data capture register  410  and conveys a plurality of input signals to the data capture register  410  which latches the input signals on an edge of a capture clock signal. The latched input signals are later clocked out of the data capture register on a subsequent edge of the capture clock signal and conveyed by the data capture signal line  440  to an input of the data capture/resynchronization register  420 . The signals applied to the input of the data capture/resynchronization register  420  are latched on an edge of a sync clock signal, and later clocked out on a subsequent edge of the sync clock signal and conveyed by the data capture/resynchronization signal line  450  to an input of the data out register  430 . The signals applied to the input of the data out register  430  are latched on an edge of the sync clock signal, and later clocked out on a subsequent edge of the sync clock signal, forming a pipeline data out signal. To save implementation area for the interface block  110  (FIGS.  1 ,  2 A- 2 D) on a silicon die, the same three stage data pass through synchronization pipeline  400  is employed for all operating modes of the interface. When operating the interface block  110  in imager mode, the three stage data pass through synchronization pipeline  400  is also used for regeneration of the horizontal sync signal HS, the vertical sync signal VS, and the pixel clock signal PCLK. When operating the interface block  110  in the microprocessor mode, the three stage data pass through synchronization pipeline  400  is also used for regeneration of the first chip select signal CS 1 , the second chip select signal CS 2 , and processor clock signal ECLK. Skilled artisans will appreciate that the data capture register  410 , the data capture/resynchronization register  420 , and the data out register  430  may each be comprised further of multiple registers according to the number of data signals which are processed, the illustration of each as a single register being a simplification to demonstrate the essential elements of the present invention without obscuration. It is to be further appreciated that the intervening logic blocks  460 A-E represent the potential incorporation of logic circuits and functions commonly employed to facilitate the distribution and control of signals in a digital circuit.  
         [0044]     Appropriate selection of the capture clock signal and the sync clock signal enable the interface block  110  to recover the signals which are not sent over serial link. The following table summarizes the relationship between the operating mode, signals, and clocks employed by the exemplary embodiment of the present invention:  
                                                   Pipeline       Pipeline               Data In   Capture   Data Out       Operating Mode   Signals   Clock   Signals   Sync Clock                   Microprocessor   D[15:0],   CS1, CS2,   18 bits   System       Transmit   RS, CS1,   or ECLK   to the   clock           CS2,       output           ECLK       parallel                   data bus                   150B       Microprocessor   18 bits   From   D[15:0],   System       Receive   from the   demodulator   RS, CS1,   clock           input   160   CS2,           parallel       ECLK           data bus           150A       Imager   D[7:0],   PCLK   18 bits   System       Transmit   VS, HS       to the   clock                   output                   parallel                   data bus                   150B       Imager Receive   18 bits   From   D[7:0],   Regenerated           from the   demodulator   VS, HS   PCLK           input   160           parallel           data bus           150A                  
 
         [0045]     In the exemplary embodiment, the data cycles from the microprocessor are asynchronous to the system clock, but may be received at the same frequency as the system clock. The data cycles from the imager interface are also asynchronous to the system clock, but may be received at twice the frequency of the system clock. The interface block  110  captures the data and synchronizes it to the system clock transferring it to the modulator  170  ( FIG. 1 ). To enable the synchronization, the system clock may be doubled and the doubled system clock is used for the synchronization pipeline. Eighteen bits of data are sent to the transmit block with a synchronous signal that indicates the data are ready.  
         [0046]     When the interface block  110  is in the receiving mode, it is assumed that the data are received asynchronously to the system clock. Because of the delay from the transmit block, the delay of the data link, and the asynchronous nature of the receive block, the 18-bit parallel data are assumed to be asynchronous to the system clock, but may be received at the same frequency as the system clock. The phase relationship of the received data and the system clock is indeterminate. The interface block captures the 18-bit data once per system clock cycle and synchronizes it to the system clock before regenerating the encoded signals which were not sent explicitly over the link. To enable the synchronization, the system clock may be doubled for use with the synchronization pipeline.  
         [0047]     Attention is now directed to  FIG. 5 , a microprocessor system  500  according to the exemplary embodiment of the present invention further including a microprocessor  510 , a first display  520 , a second display  530 , a camera  540 , and a first, second, third, and fourth instance of a serializer/deserializer  550 A-D. The first, second, third, and fourth instance of the serializer/deserializer  550 A-D are specific embodiments of the serializer/deserializer system  100  ( FIG. 1 ). The microprocessor  510  further includes a memory port  512  for supplying display data and a camera interface  514  for receiving image data. A clock signal line CLK conveying a system clock operating at, for example, 19.2 MHz is coupled to the instances of the serializer/deserializer  550 A-D and to the camera  540 .  
         [0048]     A mode number appearing in association with each instance of the serializer/deserializer  550 A-D indicates the operating configuration, according to the following table: 
        Mode 00: microprocessor mode, receive     Mode 01: microprocessor mode, transmit     Mode 10: imager mode, transmit     Mode 11: imager mode, receive        
 
         [0053]     A conceptual boundary  560  separates the microprocessor system  500  into two portions: a first portion devoted to data processing comprising the microprocessor  510 , and a second portion devoted to image acquisition and display, comprising the first display  520 , the second display  530 , and the camera  540 . The two portions separated by the conceptual boundary  560  are linked by microprocessor serial data lines  570 , imager serial data lines  580 , and clock line  590  connecting the instances of the serializer/deserializer  550 A-D. It will be appreciated by those skilled in the art that the two portions of the imaging system may be physically separate and distinct devices, for example a personal computer linked to an image display and capture unit by a serial cable, or the two portions of the imaging system may be integrated on a single circuit board, a single package module, or even a single semiconductor substrate.  
         [0054]     It is to be further appreciated by those skilled in the art that an alternative embodiment can be constructed in which clock line  590  is rendered unnecessary by embedding the clock signal in the transmitted serial data originating in the first instance of the serializer/deserializer  550 A and recovering the clock signal from the received serial data in the second instance of the serializer/deserializer  550 B.  
         [0055]     A transmit block and a receive block linked by a serial interconnection are usually both configured by the appropriate configuration bits to operate in the same device interface mode; i.e., the microprocessor mode or the imager mode. All other configuration bits may be set differently on the transmit block and the receive block. For example, the transmit block in the first instance of the serializer/deserializer  550 A may be configured to interface in the microprocessor mode using an ECLK write mode, active high. The corresponding receive block in the second instance of the serializer/deserializer  550 B may be configured to interface in the microprocessor mode using a CS write mode, active low. The capability to vary configuration bit settings between the transmit block and the receive block allows for flexibility in choosing how devices connect to the blocks.  
         [0056]     The memory port  512  of the microprocessor  510  is connected to the first instance of the serializer/deserializer  550 A by the data signal lines D[15:0], the register select signal RS, the first chip select signal CS 1 , the second chip select signal CS 2 , and the processor clock signal ECLK. The second instance of the serializer/deserializer  550 B is connected to the first display by the data signal lines D[15:0], the register select signal RS, the first chip select signal CS 1 , and the processor clock signal ECLK. The second instance of the serializer/deserializer  550 B is connected to the second display by the data signal lines D[15:0], the register select signal RS, the second chip select signal CS 2 , and the processor clock signal ECLK. The first instance of the serializer/deserializer  550 A and the second instances of the serializer/deserializer  550 B are connected across the conceptual boundary  560  by the microprocessor serial data lines  570  and the clock line  590 .  
         [0057]     The camera  540  is connected to the third instance of the serializer/deserializer  550 C by the vertical sync signal VS, the horizontal signal HS, data signals D[7:0], and the pixel clock PCLK. The third instance of serializer/deserializer  550 C is connected across the conceptual boundary  560  to the fourth instance of the serializer/deserializer  550 D by the imager serial data lines  580 . The fourth instance of the serializer/deserializer  550 D is coupled to the camera interface  514  of microprocessor  510  by the horizontal sync signal HS, the vertical sync signal VS, data signals D[7:0], and the pixel clock PCLK.  
         [0058]     The following tables summarize the signals sent across the conceptual boundary  560  by the serial links and whether the signals are explicitly sent or are regenerated the second instance of the serializer/deserializer  550 B for the microprocessor link and the fourth instance of the serializer/deserializer  550 D for the imager link.  
                                                 Imager Link                Signal   Sent (S) or               Name   Regenerated (R)   Description                       D[7:0]   S   8-bit data bus           VS   S   Vertical sync           HS   S   Horizontal sync           PCLK   R   Pixel clock (19.2 MHz)                      
 
         [0059]    
       
         
               
             
               
               
               
               
             
           
               
                   
               
               
                   
               
               
                 Microprocessor Link 
               
             
          
           
               
                   
                 Signal 
                 Sent (S) or 
                   
               
               
                   
                 Name 
                 Regenerated (R) 
                 Description 
               
               
                   
                   
               
               
                   
                 D[15:0] 
                 S 
                 16-bit data bus 
               
               
                   
                 RS 
                 S 
                 Register select: distinguishes 
               
               
                   
                   
                   
                 display and command data 
               
               
                   
                 CS1 
                 S 
                 Chip select for first display 
               
               
                   
                 CS2 
                 R 
                 Chip select for second display 
               
               
                   
                 ECLK 
                 R 
                 Processor clock 
               
               
                   
                   
               
             
          
         
       
     
         [0060]     The interface block  100  (FIGS.  1 ,  2 A-D) is highly configurable, allowing the microprocessor system  500  to connect multiple microprocessor and imager interfaces. The configuration allows the polarity of each interfaced signal to be inverted and also allows the format of the microprocessor control signals to be changed.  
         [0061]     In the transmit mode, the interface block  110  ( FIG. 1 ) accepts data in the imager mode from the 8-bits of data signals D[7:0], by the vertical sync signal VS, the horizontal signal HS, and the pixel clock PCLK connected to the third instance of serializer/deserializer  550 C, and accepts data in the microprocessor mode from the data signal lines D[15:0], the register select signal RS, the first chip select signal CS 1 , the second chip select signal CS 2 , and the processor clock signal ECLK connected to serializer/deserializer  550 A. The signals accepted by the first instance of the serializer/deserializer  550 A and the third instance of the serializer/deserializer  550 C are serialized 18 bits at a time. The interface block  110  ( FIGS. 1, 2B ) within the third instance of the serializer/deserializer  550 C, combines the data from two data transfers and reduces the total number of bits from 22 to 18 with no loss of information. The interface block  110  ( FIGS. 1, 2A ) within the first instance of the serializer/deserializer  550 A reduces the number of signals from 20 to 18 with no loss of information.  
         [0062]     The interface block  110  translates the 20 input signals in the microprocessor mode or the two blocks of eleven input signals in the imager mode into an 18-bit word to be transmitted, thereby compressing the signals before transmission. The control signals and data are encoded such that the information can be regenerated on the receiving system. The encoding allows the control signals and data to be regenerated into another format on the receiving system with no additional circuitry.  
         [0063]     In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the specific number and function of the input signals, the width of the output bus, and the choice of signals to be compressed, regenerated, or explicitly conveyed may all be varied within the present invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.