Abstract:
Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional application of U.S. patent application Ser. No. 13/724,623, filed Dec. 21, 2012, which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices in digital circuitry. In particular, the NVR and NVSR devices of the invention can directly load non-volatile digital information into the registers for fast and constantly referencing. 
         [0004]    2. Description of the Related Art 
         [0005]    In digital circuitry, registers and shift registers are broadly applied for storing small amount digital information for fast and constantly referencing. A common property of computer programs is locality of reference: the same values are often accessed repeatedly and frequently used values held in registers improve performance. This is what makes fast registers meaningful in contrast to the general data accessed from the main memory units. For building the register and shift register in a digital circuitry the main static memory element of the conventional register and shift register is usually constructed by a pair of cross-connected MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) invertors  111  and  112  as the circuit schematics shown in  FIG. 1 . As the digital representation of core voltage V DD  for “1” and ground voltage V SS  for “0” in digital circuitry, one bit of stored digital information is sensed by the voltage potentials at the output node Q of the crossed inverters  111  and  112  in the register device as in  FIG. 1 . The digital information stored in a plurality of registers can be directly read out from their outputs in parallel. Or reducing the numbers of each individual output nodes to a single output node of a series of registers, the shift registers are designed to shift the digital data from one register to the next neighbor register by a clock sequence. The series bits of digital information stored in shift registers are sequentially sent out from the output port of the lead register. 
         [0006]    Registers are normally measured by the number of bits they can hold, for example, an “8-bit register” or a “32-bit register”. Registers are also categorized as processor registers and memory registers according to their applications for Computing Process Unit (CPU) and memory units, respectively. A processor often contains several kinds of registers classified accordingly to their content or instructions. For example, floating point and constant registers store floating point numbers and numerical constants; vector registers hold data for vector processing done by single instruction multiple data; conditional registers hold truth values often used to determine whether some instructions should or should not be executed; control and status registers are applied for program counters, instruction registers and program status words. Meanwhile the memory registers such as buffer register, data registers, address registers, and type range registers fetch data from RAM (Random Addressable Memory). 
         [0007]    Although the data inside the conventional registers and shift registers can be fast and constantly accessed, the stored data disappear after the chip power is turned off, that is, the stored data in the conventional registers and shift registers are volatile. When a digital circuitry is turned on, the initial data in the registers must be loaded either from an on-chip non-volatile memory unit such as ROM (Read Only Memory) and EEPROM (Electrical Erasable Programmable Read Only Memory), or from external memory units. The conventional data fetching process for registers would require the time to read out the data from a memory unit and the time to load the fetched data into the registers, resulting in performance degradation. The data fetch process also requires more chip power from the non-volatile memory sensing circuitry. Therefore, it will be very desirable for registers to load non-volatile data directly without going through the conventional data fetching process from non-volatile memory units to improve the performance of register and to save chip power from non-volatile memory data sensing. 
         [0008]    In this invention, we have developed Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) based on the previously developed Non-Volatile Static Random Access Memory (U.S. patent application Ser. No. 13/206,270, the disclosure of which is incorporated herein by reference in its entirety). The NVR and NVSR of the invention can directly load non-volatile data from semiconductor non-volatile memory elements to their correspondent static memory elements (cross-connected inverters) without going through a readout process from a non-volatile memory. When a digital circuitry embedded with the NVR and NVSR is “on”, the non-volatile data are immediately loaded to the correspondent static memory elements in the registers. The data in the NVR and NVSR are then ready for fast and constantly referencing for the digital circuitry. 
       SUMMARY OF THE INVENTION 
       [0009]    According to an embodiment, an N-type Non-Volatile Register (NVR) cell  200  consists of a static memory element  210 , an N-type semiconductor non-volatile memory element  220 , and an N-type reset MOSFET  230  shown in  FIG. 2 . Two cross-connected MOSFET inverters MP 0 -MN 0    211  and MP 1 -MN 1    212  form the static memory element  210 . The data output terminal Q is located at the node  214  between MP 1  and MN 1  of the inverter  212 . The source and drain electrodes of the N-type reset MOSFET  230  are connected to the ground voltage V SS  and the output node Q respectively. The gate electrode  231  of the N-type MOSFET  230  is the input terminal for a “reset” signal to reset the output node Q to the ground voltage potential V SS . A first source/drain electrode and a second source/drain electrode of the N-type semiconductor non-volatile memory element  220  are connected to the node  213  between MP 0  and MN 0  of inverter  211  and an external terminal D  221 , respectively. The control gate of the N-type semiconductor non-volatile memory element  220  is connected to an external terminal CG  222 . 
         [0010]    In the operations of the NVR cell  200 , the non-volatile data “0” and “1” are represented by the programmed high threshold voltage state V thH  and the erased low threshold voltage V thL  of the N-type semiconductor non-volatile memory element  220  respectively. When a control gate voltage bias V CG  for V thH &gt;V CG &gt;V thL  is applied to the control gates of a plurality of the N-type semiconductor non-volatile memory elements  220  through the external terminal CG  222  with the second source/drain electrodes connected to the external terminal D applied with the ground voltage V SS , the N-type semiconductor non-volatile memory elements at low threshold voltage state V thL  are “on” to pull down the voltage potentials at the nodes  213  of the inverters  211  to the ground voltage V SS . While the N-type semiconductor non-volatile memory elements at high threshold voltage state V thH  are “off” to retain the voltage potentials at the nodes  213  of the inverters  211 . 
         [0011]    Upon digital circuit power-on for loading the non-volatile data to a plurality of NVR cells, a “reset” signal of the digital “high” voltage V DD  is initially applied to the gate electrodes  231  of the N-type MOSFET devices  230  to reset the voltage potentials at the output nodes Q  214  to the ground voltage V SS  (“0”) and the voltage potentials at the complementary nodes  213  to the digital “high” voltage V DD . After the reset procedure, the set procedure takes place by applying a control gate voltage bias V CG  for V thH &gt;V CG &gt;V thL  to the control gate electrodes and the ground voltage V SS  to the second source/drain electrodes of N-type semiconductor non-volatile memory elements  220  respectively. Consequently the N-type semiconductor non-volatile memory elements at the low threshold voltage state V thL  are then “on” to pull down the initial voltage V DD  to the ground voltage V SS  at the complementary nodes  213  leading to the voltage potential at the output nodes Q  214  changed from the ground voltage V SS  (“0”) to the digital “high” voltage V DD  (“1”). The non-volatile data “1” stored in the N-type non-volatile memory elements with the low threshold voltage are then loaded into their correspondent static memory elements with digital data “1” in NVR cells. Meanwhile since the N-type semiconductor non-volatile memory elements at high threshold voltage state V thH  are “off” to retain the initial voltage potential V DD  at the complementary nodes  213 , the voltage potentials at the output nodes Q  214  remain the same ground voltage V SS  (“0”). The non-volatile data “0” stored in the N-type non-volatile memory elements with the high threshold voltage are then equivalent to the initial digital value “0” in their correspondent static memory elements in NVR cells. Therefore, the set procedure completes loading the non-volatile data from the non-volatile memory elements into their correspondent static memory elements in NVR cells. 
         [0012]    After the non-volatile data are loaded to the static memory elements in a plurality of NVR cells, the digital data information can be referenced either directly from the output node Q of each individual NVR cell in parallel or from a single output port in series by a clock sequence as for the conventional shift registers. The schematic of a NVSR cell  300  where two transmission gate devices  340  and  350  are added to the register is shown in  FIG. 3 . When a “high” clock signal and its “low” complementary signal are applied to the node  360  and node  361 , the digital signals at the input node  341  of the transmission gate device  340  are passed to the output node  342  connected to the gate of inverter  311  and propagated to the output node  352  of inverter  312  with the transmission gate device  350  “off” to disconnect the output signal at the output node  352  from the gate of inverter  311 . When the clock signal goes “low”, the transmission gate  340  is “off” to cut off the input signal (at the input node  341 ) and the transmission gate  350  is “on” to latch the digital value in the cross-connected inverters  311  and  312 . 
         [0013]      FIG. 4   a  shows the schematic of a P-type non-volatile register cell according to the invention. A P-type non-volatile register cell  400   a  consists of a static memory element  410 , a P-type semiconductor non-volatile memory element  420 , and a P-type reset MOSFET  430  as shown in  FIG. 4   a . The P-type semiconductor non-volatile memory element  420  can be programmed to a high threshold voltage state V thH  (toward more positive) by injecting electrons to the storing material and erased to a low threshold voltage state V thL  (toward more negative) by removing the stored electrons or slightly injecting holes. The non-volatile data “0” and “1” are represented by the high threshold voltage state V thH  and the low threshold voltage state V thL , respectively. A first source/drain electrode and a second source/drain electrode of the P-type semiconductor non-volatile memory element  420  are connected to the node  413  between MP 0  and MN 0  of inverter  411  and an external terminal S  421 , respectively. When a digital “high” voltage V DD  is applied to the control gate electrode  422 , the external terminal S  421 , and the well electrode  423  of the P-type semiconductor non-volatile memory element  420 , the P-type semiconductor non-volatile memory element with high threshold voltage state V thH  is always “on” to pass V DD  to pull up the complementary node  413 , resulting in ground voltage potential V SS  at the register output node Q  414 . The P-type semiconductor non-volatile memory element with low threshold voltage V thL  is “off” with gate, source, and well electrodes biased at the digital “high” voltage V DD  as the standard P-type MOSFET operation. The P-type semiconductor non-volatile memory element in the high threshold voltage state can be turned off by applying a control gate voltage V CG &gt;V thH  with source and well electrodes biased at the digital “high” voltage V DD . 
         [0014]    Upon digital circuit power on for loading the non-volatile data to the P-type NVR cells  400   a,  a “reset” signal, the digital “low” voltage V SS , is initially applied to the gate electrodes  431  of the P-type MOSFET devices  430  to reset the voltage potentials at the output nodes Q  414  to the digital “high” voltage V DD  (“1”) and the voltage potentials at the complementary nodes  413  to the digital “low” voltage V SS . After the reset procedure, the set procedure takes place by applying the digital “high” voltage bias V DD  to the control gate electrodes, the second source/drain electrodes, and well electrodes of the P-type semiconductor non-volatile memory elements  420  respectively. Consequently the P-type semiconductor non-volatile memory elements at the high threshold voltage state V thH  are then “on” to pull up the initial ground voltage V SS  to the voltage V DD  at the complementary nodes  413  leading to the voltage potential at the output node Q  414  changed from the digital “high” voltage V DD  (“1”) to the ground voltage V SS  (“0”). The non-volatile data “0” stored in the P-type non-volatile elements in the high threshold voltage state are then loaded into their correspondent static memory elements with digital data “0” in NVR cells  400   a . Meanwhile since the P-type semiconductor non-volatile memory elements at the low threshold voltage state V thL  are “off” to retain the initial ground potential V SS  at the complementary nodes  413 , the voltage potentials at the output nodes Q  414  remain the same digital “high” voltage V DD  (“1”). The non-volatile data “1” stored in the P-type non-volatile elements with the low threshold voltage states are then equivalent to the initial digital value “1” in their correspondent static memory elements in NVR cells. Therefore, the set procedure completes loading the non-volatile data from the non-volatile memory elements to their correspondent static memory elements in NVR cells. 
         [0015]    After the non-volatile data are loaded to the static memory elements in a plurality of NVR cells, the digital data information can be referenced either directly from the output node Q of each individual NVR cell in parallel or from a single output port in series by a clock sequence as for the conventional shift registers. The schematic of a NVSR cell  400   b  where two transmission gate devices  440  and  450  are added to the register is shown in  FIG. 4   b . When a “high” clock signal and its “low” complementary signal are applied to the node  460  and node  461 , the digital signals at the input node  441  of the transmission gate device  440  are passed to the output node  442  connected to the gate of inverter  411   b  and propagated to the output node  452  of inverter  412   b  with the transmission gate device  450  “off” to disconnect the output signal at the output node  452  from the gate of inverter  411   b.  When the clock signal goes “low”, the transmission gate  440  is “off” to cut off the input signal (at the input node  441 ) and the transmission gate  450  is “on” to latch the digital value in the cross-connected inverters  411   b  and  412   b.    
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiment of the present invention, in which: 
           [0017]      FIG. 1  shows the schematic of the static memory element in the conventional register. 
           [0018]      FIG. 2  shows the schematic of an N-type non-volatile register cell according to this invention. 
           [0019]      FIG. 3  shows the schematic of an N-type non-volatile shift register cell according to this invention. 
           [0020]      FIG. 4   a  shows the schematic of a P-type non-volatile register cell according to this invention. 
           [0021]      FIG. 4   b  shows the schematic of a P-type non-volatile shift register cell according to this invention. 
           [0022]      FIG. 5  shows the schematic of an N-bit Non-Volatile register (NVR) according to an embodiment of the invention. 
           [0023]      FIG. 6  shows the timing sequence for the operations of the N-bit NVR. 
           [0024]      FIG. 7  shows the schematic of an N-bit Non-Volatile Shift Register (NVSR) according to an embodiment of the invention. 
           [0025]      FIG. 8  shows the timing sequence for the operations of the N-bit NVSR. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and element changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure. 
         [0027]    According to a preferred embodiment of an N-bit NVR  500 , a number of NVR cells  200  equal to N are arranged in a row as shown in  FIG. 5 . The digital power rails forming the positive voltage line V DD    501  and ground voltage line V SS    505  are connected to the V DD  terminals and V SS  terminals of the NVR cells  200  respectively. For the NVR cells  200  in the N-bit NVR  500 , the gates of N-type MOSFET devices  230  are connected to form a reset line  502  and the control gates of the N-type semiconductor non-volatile memory elements  220  are connected to form a CG line  503 . The second source/drain electrodes of the N-type semiconductor non-volatile memory elements  220  are connected altogether to form a D line  504 . The N-bit register data output in parallel from the terminals Qi, for i=1 . . . N. 
         [0028]      FIG. 6  shows the timing sequence of the operations of the N-bit NVR. Upon the completion of chip power on reset for a digital circuitry, all the NVR cells  200  in the N-bit NVR  500  are reset to an initial value “0” (V SS  at the output nodes Qi of NVR cells  200 ) by applying a voltage pulse with amplitude V DD  for nanoseconds to the reset line  502 . To load non-volatile data from the non-volatile memory elements  220  to their correspondent static memory elements  210  in the N-bit NVR  500 , the CG line  503  is applied with a voltage pulse V CGH  for V thH &gt;V CGH &gt;V thL  for a duration of several nanoseconds while the D line  504  is attached to the ground voltage V SS . The non-volatile memory elements with the low threshold voltage V thL  (having the non-volatile data “1”) are “on” to set data “1” in their correspondent static memory elements in the “N” NVR cells. Meanwhile the non-volatile memory elements with high threshold voltage V thH  (having the non-volatile data “0”) are “off” to retain the initial data “0” in their correspondent static memory elements in the “N” NVR cells. After the set process, the N-bit NVR  500  loaded with the stored non-volatile data are ready for fast and constant referencing. 
         [0029]    In a preferred embodiment of an N-bit NVSR  700 , a number of NVSR cells  300  equal to N are arranged in a row in  FIG. 7 . The digital power rails forming the positive voltage line V DD    701  and ground voltage line V SS    705  are connected to the V DD  terminal and V SS  terminal of each NVSR cell  300 , respectively. For the NVSR cells  300  in the N-bit NVSR  700 , the gates of N-type MOSFET devices  330  are connected to form a reset line  702  and the control gates of the N-type semiconductor non-volatile memory elements  320  are connected to form a CG line  703 . The second source/drain electrodes of the N-type semiconductor non-volatile memory elements  320  are connected to form a D line  704  The first clock signals φ 1    711  and its complementary signal /φ 1    712  are applied to the transmission gates of the odd numbers of NVSR cells and the second clock signals φ 2    721  and its complementary signal /φ 2    722  are applied to the transmission gates of the even numbers of NVSR cells in the N-bit NVSR  700 . The series data output Q  730  of the N-bit NVSR  700  is the output node of the N th  NVSR cell. 
         [0030]      FIG. 8  shows the timing sequence of the operations the N-bit NVSR. Upon the completion of chip power on reset for a digital circuitry, all the NVSR cells  300  in the N-bit NVSR  700  are reset to an initial value “0” (V SS  at all the output nodes  352  of NVSR cells  300 ) by applying a voltage pulse with amplitude V DD  for nanoseconds to the reset line  702 . To load non-volatile data from the non-volatile memory elements  320  to their correspondent static memory elements  310  in the N-bit NVSR  700 , the CG line  703  is applied with a voltage pulse V CGH  for V thH &gt;V CGH &gt;V thL  for a duration of several nanoseconds while with D line  704  attached to the ground voltage V SS . The non-volatile memory elements with the low threshold voltage V thL  (having the non-volatile data “1”) are “on” to set data “1” in their correspondent static memory elements in the “N” NVSR cells  300 . Meanwhile the non-volatile memory elements with the high threshold voltage V thH  (having the non-volatile data “0”) are “off” to retain the initial data “0” in their correspondent static memory elements in the “N” NVSR cells  300 . After the set process, the loaded non-volatile data can be shifted out in series by activating the two clock signal sequences φ 1  and φ 2  separated by half cycle as shown in  FIG. 8 . The non-volatile data is sequentially sensed at the output node Q  730  of the N-bit NVSR  700 . 
         [0031]    The aforementioned description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations of non-volatile memory elements including the types of non-volatile memory device made of different charge storing material and the types of reset transistors will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.