Abstract:
A resistive random access memory utilizing gate induced drain leakage current as the read operation current and the write operation current and a method of operation the same, wherein the resistive random access memory including a plurality of arrayed memory cells, a plurality of bit-lines and a plurality word-lines, each memory cell including: a switching resistor having a first terminal and a second terminal, the first terminal of the switching resistor being connected to one bit-line; and a MOSFET being connected to the second terminal and having a gate, a source, a drain and a substrate, the gate being connected to one word-line, the read operation current and the write operation current of the memory cell being gate induced drain leakage current of the MOSFET. The RRAM array presented in this invention has superior scalability for resistors as well as transistors, which leads to a memory array with higher density.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims the priority of Chinese Patent Application No. 200910194782.6, entitled “A resistive random access memory and the method of operating the same”, and filed Aug. 28, 2009, the entire disclosure of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to integrated circuit, and particularly relates to a resistive random access memory and the method of operating the same. 
         [0004]    2. Description of Prior Art 
         [0005]    Recently, a new-type of non-volatile memory technology, the resistive random access memory (RRAM), has attracted much attention due to its high density, non-volatile storage, fast write and read, compatible with CMOS process, and low power consumption. The resistor in an RRAM cell has bi-stable resistance states with good retention and is switchable between states when a large enough voltage or current pulse (or power pulse) is applied. 
         [0006]    The RRAM includes an array of memory cells organized in rows and columns as illustrated in  FIG. 1 , where a memory cell  100  includes a switching resistor  101  and a select transistor  102  (as referred to as 1T1R cell). The select transistor  102  is assumed an n-type MOSFET (or briefly as n-MOS) for selecting the memory cell  100  to perform the read/write operations. The switching resistor  101  has two terminals, one of which is connected to a bit-line  103 , and the other is connected to the drain of the select transistor  102 . The gate of the select transistor  102  is connected to a word-line  104 , and the source of the select transistor  102  is grounded. The bi-stable resistance states of the switching resistor  101  represent the digital data ‘1’ and ‘0’ as corresponding to the high and low resistance states respectively. 
         [0007]      FIG. 2  illustrates a conventional method of operating the RRAM in  FIG. 1 . The method includes a write operation and a read operation. 
         [0008]    During the write operation of the selected memory cell, a high voltage V H  (+Vcc) is applied to the bit-line  103 . The select transistor  102  (n-MOS) can be turned on by applying a voltage (+Vcc) on the gate of the select transistor  102  through the word-line  104 , then a large current flows through the switching resistor  101  and the resistance state of the switching resistor  101  can be changed depending on the magnitude of current and pulse duration. The resistance state of the switching resistor  101  can be changed into a low resistance state (referred to as SET operation), or reversely, into a high-resistance state (referred to as RESET operation). It should be noted that by controlling the transient pulse parameter (e.g. height and duration), the RESET operation (to write “1”) and SET operation (to write “0”) can be intentionally performed (not shown in the waveforms of word-line voltage and resistor current in  FIG. 2 ). 
         [0009]    During the read operation on the selected memory cell, a lower voltage V L  (˜0.05 v to 1 v) is applied to the bit-line  103 . Then the select transistor  102  is turned on by applying a voltage (+Vcc) to the word-line  104 . The voltage across the switching resistor  101  is small enough to avoid disturb on the resistance state of the resistor  101  and also large enough for the sense amplifier to detect the current through the resistor  101 . The stored data in the memory cell  100  is determined by the current measured in sense amplifier, e.g. a larger current represents data ‘0’ (corresponding a smaller resistance) and a smaller current represents data ‘1’ (corresponding to a larger resistance) Typically, the ratio of larger to smaller current shall be &gt;5. 
         [0010]    During the write operation of a selected memory cell, those un-selected cells (on the same bit-line  103 ) experience gate-induced-drain-leakage (GIDL) current flowing through resistors and transistor&#39;s drain into the ground due to the bias at gate (i.e. 0 v for un-selected word-lines) and +Vcc at the selected bit-line. Thus, in the conventional RRAM, the GIDL current continuously flowing through the switching resistor and results in disturb and degraded data retention time, . . . etc. 
         [0011]    An illustration of the mechanism of GIDL current in an n-MOS is shown in  FIG. 3 , with components (a) and (b) included in GIDL current. Component (a) is based on the classical model of GIDL related to the holes generated at the interface between the gate oxide and n-type lightly doped drain (LDD) extension, and subsequently flowing toward the p-well (or substrate).  FIG. 3   a  illustrates how the vertical field (perpendicular to the interface of gate oxide and LDD region) results in band-bending of the LDD region and subsequent band-to-band tunneling (BTBT) of valence band electrons into the depleted n +  drain (i.e. holes generated at the interface). The generated holes will flow toward the p-well due to the electrical field from the reverse biased n +  drain to p-well junction. As shown in  FIG. 3   b , component (b) is related to the hole generation in the bulk near the interface through the reverse biased n+ drain to p-well junction by valence band electron BTBT if the channel doping is high. This valence band electron BTBT current (component (b)) is based on the same mechanism as the well-known “Zener” diode break-down. In 45 nm CMOS node and beyond, the channel doping is significantly high, thus the component (b) is dominating than component (a). While, at earlier CMOS nodes (e.g. 0.25 um and earlier), the channel doping is not high enough, and the component (a) could be dominating. As shown in  FIG. 3   a  (for n-MOS), the drain to gate bias V gd  needs to be negative enough to result in enough band-bending slightly larger than the band-gap (Eg), in this way the BTBT mechanism for components (a) and (b) is triggered. Similarly, in p-type MOSFET (or briefly as p-MOS), electrons occur at the interface of p +  drain by BTBT of holes under “off” bias and GIDL current of electrons flows toward n-well. As well known, GIDL current can be enhanced by various techniques, e.g. eliminating spacer and LDD implant, reversing the doping polarity of poly gate, . . . etc. 
         [0012]    It should be noted that the source and drain in MOSFET are typically the same in structure, thus the GIDL current will occur at the source side also as long as Vgs&lt;0 v (for n-MOS), though the original study of the BTBT current was based on the leakage current observed at the drain side and it is traditionally referred to as the gate-induced-“drain”-leakage (GIDL) current. 
         [0013]    Various approaches have been proposed in the prior art for suppressing the GIDL phenomena in MOSFET, e.g. increasing the thickness of the gate oxide, reducing LDD doping, less overlap area between gate oxide and LDD, . . . etc. However, there are very few studies toward how to enhance and utilize the GIDL current of the MOSFET for useful device operation. 
       SUMMARY OF THE INVENTION 
       [0014]    An objective is to provide a resistive random access memory (RRAM) utilizing the GIDL current as the operating current for read and write operations. 
         [0015]    A further objective is to provide a method of operating the RRAM in the invention. 
         [0016]    From the first aspect of the present invention, the RRAM includes a plurality of memory cells in an array, a plurality of bit-lines and a plurality of word-lines, each memory cell comprising: a switching resistor having a first terminal and a second terminal, the first terminal of the switching resistor being connected to one bit-line; and a MOSFET being connected to the second terminal and having a gate, a source, a drain and a substrate, the gate being connected to one word-line, the read and write operation current of the memory cell being the GIDL current of the MOSFET. 
         [0017]    From the second aspect of the present invention, the method of operating the RRAM includes a write operation and a read operation. During the write operation, the method comprises steps of: applying a first voltage to the bit-line; applying a second voltage to the word-line to trigger GIDL current pulse through the switching resistor for resistance change (i.e. writing data to the memory cell). During the read operation, the method comprises steps of: applying a third voltage to the bit-line; applying a fourth voltage to the word-line to trigger GIDL current through the switching resistor for measuring the resistance (i.e. reading data stored in memory cell). Typically, the GIDL current in read operation is at least 10× smaller than in write operation to avoid “read disturb”. 
         [0018]    Many benefits can be achieved by way of the present invention over conventional techniques. For example, the power consumption of select transistors can be reduced by utilizing GIDL current as the read and write operation current, the RRAM array presented in this invention has superior scalability for resistors and leads to a memory with higher density. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  is a schematic diagram of a conventional RRAM array. 
           [0020]      FIG. 2  illustrates a conventional pulse scheme for operating the RRAM in  FIG. 1 . 
           [0021]      FIG. 3  illustrates the mechanism of GIDL current in an n-type MOSFET. 
           [0022]      FIG. 3   a  illustrates how the vertical field results in band-bending at drain side and subsequent valence electrons tunnel into the n +  drain by band-to-band tunneling (BTBT) mechanism. 
           [0023]      FIG. 3   b  illustrates the hole generation in the bulk near the interface through the reverse biased n+ drain to p-well junction. 
           [0024]      FIG. 4  is the schematic diagram of a first RRAM according to an embodiment of the present invention. 
           [0025]      FIG. 5   a  illustrates the write operation (of the first method) on the first RRAM. 
           [0026]      FIG. 5   b  is a flow chart of the write operation (of the first method) according to the present invention. 
           [0027]      FIG. 6   a  illustrates the read operation (of the first method) on the first RRAM. 
           [0028]      FIG. 6   b  is a flow chart of the read operation (of the first method) according to the present invention. 
           [0029]      FIG. 7  shows the pulse scheme (for the first method) of operating the first RRAM. 
           [0030]      FIG. 8  is the schematic diagram of a second RRAM according to an embodiment of the present invention. 
           [0031]      FIG. 9   a  illustrate the write operation (of the second method) on the second RRAM. 
           [0032]      FIG. 9   b  is a flow chart of the write operation (of the second method) according to the present invention. 
           [0033]      FIG. 10   a  illustrates the read operation (of the second method) on the second RRAM. 
           [0034]      FIG. 10   b  is a flow chart of the read operation (of the second method) according to the present invention. 
           [0035]      FIG. 11  shows the pulse scheme (for the second method) of operating the second RRAM. 
           [0036]      FIG. 12  is the schematic diagram of a third RRAM according to an embodiment of the present invention. 
           [0037]      FIG. 13   a  illustrates the write operation (of third method) on the third RRAM. 
           [0038]      FIG. 13   b  is a first flow chart of the write operation (of the third method) according to the present invention. 
           [0039]      FIG. 14   a  illustrates the read operation (of the third method) on the third RRAM. 
           [0040]      FIG. 14   b  is a first flow chart of the read operation (of the third method) according to the present invention. 
           [0041]      FIG. 15  shows pulse scheme (for the third method) of operating the third RRAM. 
           [0042]      FIG. 16   a  illustrates the write operation (of the fourth method) on the third RRAM. 
           [0043]      FIG. 16   b  is a second flow chart of the write operation (of the fourth method) according to the present invention. 
           [0044]      FIG. 17   a  illustrates the read operation (of the fourth method) on the third RRAM. 
           [0045]      FIG. 17   b  is a second flow chart of the read operation (of the fourth method) according to the present invention. 
           [0046]      FIG. 18  shows new pulse scheme (for the fourth method) of operating the third RRAM. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0047]    GIDL current is generally regarded as a negative effect in MOSFETs, therefore, various approaches have been proposed in the prior art for suppressing the GIDL in MOSFETs. The present invention provides a method of operating a resistive random access memory (RRAM) by utilizing the GIDL current in MOSFETs. 
         [0048]    As previously described in the background, a MOSFET at the off-state in circuits may have GIDL current flowing through the drain to well (or substrate) when the gate is biased at off-state. The GIDL current in MOSFET can be maximized by reversing the doping type of the poly-gate (i.e. n +  doped poly-gate for a p-MOS, or p +  doped poly-gate for a nMOS), or selectively removing the spacer and adding extra LDD implant dose (by using extra masking steps). Thus the GIDL currents of the select transistor can be large enough and useful for the read/write operation of the switching resistor. 
         [0049]    Our invention provides several embodiments of resistive random access memory (RRAM) and the method of operating the same. The details are in below. 
         [0050]    Referring to  FIG. 4 , the first RRAM of the present invention includes a plurality of memory cells in array with bit-lines and word-lines. Each memory cell comprises a switching resistor  100  and a select transistor  200  and is referred to as 1T1R cell. The switching resistor  100  comprises a first terminal and a second terminal. The first terminal of the switching resistor  100  is connected to a bit-line  300 , and the second terminal of the switching resistor  100  is connected to the select transistor  200 . The select transistor  200  is a MOSFET and has a gate, a source, and a drain. The gate of the select transistor  200  is connected to a word-line  400 . The read and write operation current is the GIDL current of MOSFET. 
         [0051]    One of the source or drain of the MOSFET is connected to the switching resistor  100  (and the other one can be left un-connected or floating as in  FIG. 4 ). As a better way, the source and drain of the MOSFET can be connected together (not shown in  FIG. 4 ) so that GIDL current generated from both the drain and source sides can contribute together as a larger current through the switching resistor  100  during write and read operations. 
         [0052]    The select transistor  200  is assumed an n-type MOSFET for illustrations in the text. During the read or write operation, the gate (word-line  400 ) of select transistor is biased negatively (e.g. −Vcc/2) than the drain/source (bit-line  300 ), so that the GIDL current through the selected MOSFET is produced. It should be noted that the word-line bias is always lower than the threshold voltage (Vt) of the n-MOS during operations, so that there is no inversion channel between the source and the drain. Additionally, if the select transistor  200  is a p-MOS, then the RRAM cell also performs well with proper reversing the bias polarity, e.g. the gate is biased more positive than the drain/source for triggering the GIDL current in p-MOS. For simplicity, the details of memory cell operations using p-MOS as select transistor is not repeated here for simplicity. 
         [0053]    It should be noted that the switching resistor  100  has bi-stable resistance states and it can be switchable. The resistive states are sensed by measuring the current through the switching resistor  100  at a fixed bias and comparing with respect to a reference current (provided by periphery circuits) in sense-amplifier. 
         [0054]    Based on the first RRAM of the present invention, a first method of operating the first RRAM is described below, which includes a write operation and a read operation. 
         [0055]      FIG. 7  illustrates the pulse waveforms for the first method of operating the first RRAM.  FIG. 5   a  illustrates how the “write” current I W  flows through the switching resistor  100 , the n+ drain, and into the p-type substrate of the select transistor  200  during the write operation (of the first method).  FIG. 5   b  is a flow chart of the write operation (of the first method) according to the present invention. Referring to  FIGS. 5   a ,  5   b  and  7 , the write operation of the first method comprises the following steps: 
         [0056]    Step S 110 , a first voltage V H  (+Vcc/2) is applied to the bit-line  300  to produce a large enough voltage across the drain and the substrate of the select transistor  200 . 
         [0057]    The source of the select transistor  200  is connected to ground. 
         [0058]    Step S 111 , a second voltage pulse is applied to the gate of the select transistor  200  through the word-line  400  for a short duration (˜us to &lt;1 ms). This voltage pulse on gate (or the selected word-line) is negative going from 0 v to −Vcc/2, so that a large enough write current pulse I w  flows and triggers the resistance change of the switching resistor  100 . It should be noted that the magnitude of the write current pulse I w  can be adjusted to be larger if the gate pulse is more negative with larger magnitude. 
         [0059]    Those un-selected word-lines and un-selected bit-lines are biased at 0 v. Regarding those un-selected memory cells, their worst bias from gate to drain is −Vcc/2 and only occur on those cells at the same bit line or word line (as those of the selected cell) and no serious degradation to resistors. (Note that the un-selected cells in conventional RRAM experience the worst bias of Vcc and trigger significant GIDL current to degrade the resistance states). According to an embodiment of the present invention, a high resistance state of the switching resistor  100  represents data ‘1’ and a low resistance state represents data ‘0’ correspondently. 
         [0060]      FIG. 6   a  illustrates the read operation (of the first method) on the first RRAM.  FIG. 6   b  is a flow chart of the read operation (of the first method) according to the present invention. With reference to  FIGS. 6   a ,  6   b  and  7 , the read operation of the first method comprises the following steps: 
         [0061]    Step S 120 , a third voltage V L  is applied to the bit-line  300  to produce a small voltage difference between the drain and substrate of the select transistor  200 . 
         [0062]    Typical V L  is in the range of 0.05 v to 1 v and it shall be properly selected so that the GIDL current is large enough for sense amplifier and small enough to avoid disturb on the resistance. 
         [0063]    Step  121 , a fourth voltage pulse is applied to the gate of the select transistor  200  through the word-line  400  for a short duration (˜us to &lt;1 ms). This voltage on gate (or selected word-line) is negative going (from 0 v to −Vcc/2) so that a large enough read current is resulted for sense amplifier to determine the stored data in the switching resistor  100 . The sense amplifier simply compares the read current with respect to a reference current. 
         [0064]    A larger read current (I R ) with respect to the reference current corresponds to a low resistance state of the switching resistor  100  and defined as data ‘0’; while a smaller I R  corresponds to a high resistance state and defined as data ‘1’. 
         [0065]      FIG. 8  is the schematic diagram of a second RRAM according to an embodiment of the present invention. Reference to  FIG. 8 , the second RRAM of the present invention includes a plurality of memory cells arranged in array with bit-lines and word-lines. Each memory cell includes: a switching resistor  100  having a first terminal and a second terminal, the first terminal of the switching resistor  100  being connected to a bit-line  300 ; a reference resistor  500  having a third terminal and a fourth terminal, the third terminal of the reference resistor  500  being connected to a bit-line  300 ; a MOSFET  200   a  having a gate, a source, and a drain and being connected to the second terminal of the switching resistor  100  and the fourth terminal of the reference resistor  500 , the gate being connected to a word-line  400 . The operation current of the read and the write operation current of the memory cell is GIDL current of the MOSFET  200 . 
         [0066]    It should be noted that the value of the reference resistor  500  is constant within the range of the switching resistor. 
         [0067]    Otherwise, the source of the MOSFET  200   a  is connected to the second terminal of the switching resistor  100   a , and the drain of the MOSFET  200   a  is connected to the fourth terminal of the reference resistor  500 . The substrate of the MOSFET  200   a  is connected to ground. 
         [0068]    The MOSFET  200   a  is assumed an n-type MOSFET. In read or write operations, the voltage applied to the gate (or the word-line  400 ) is always less than the threshold voltage (Vt) of the MOSFET  200   a , so that there is no inversion channel formed between the drain and the source during read and write operations. It is well-known that the Vt of MOSFET can be adjusted to be high by larger channel dopant concentration. 
         [0069]    The switching resistor  100  has bi-stable resistance states, which can be altered by the current pulse flowing in the switching resistor  100 . 
         [0070]    Based on the second RRAM of the present invention, a second method of operating the first RRAM is described below, which includes a write operation and a read operation. 
         [0071]      FIG. 11  is a pulse scheme of the second method of operating the second RRAM.  FIG. 9   a  illustrates the write operation (of the second method) on the second RRAM.  FIG. 9   b  is a flow chart of the write operation (of the second method) according to the present invention. Referring to  FIGS. 9   a ,  9   b  and  11 , the write operation of the second method comprises the following steps: 
         [0072]    Step  210 , a first voltage V H  (+Vcc/2) applied to the bit-line  300  to produce a large enough voltage difference across the drain and the substrate of the MOSFET  200   a.    
         [0073]    The source of the select transistor  200  is connected to ground. 
         [0074]    Step  211 , a second voltage pulse is applied to the gate of the MOSFET  200   a  through the word-line  400  for a short duration (˜us to &lt;1 ms). This voltage pulse on gate (or selected word-line) is negative going from 0 v to −Vcc/2, so that a large enough write current pulse I w  is resulted for triggering resistance changes of the switching resistor  100 . It should be noted that the write current pulse I w  can be adjusted to be larger if the gate bias is more negative with larger magnitude. 
         [0075]    The bias of un-selected word-line is Vcc/2 and it should be less than the Vt of the MOSFET  200   a . According to an embodiment of the present invention, a high resistance state of the switching resistor  100  represents data ‘1’ and a low resistance state represents data ‘0’ correspondently. During the write operation, the reference resistor  500  is not degraded and its resistance remains constant. 
         [0076]      FIG. 10   a  illustrates the read operation (of the second method) on the second RRAM.  FIG. 10   b  is a flow chart of the read operation (of the second method) according to the present invention. With reference to  FIGS. 10   a ,  10   b  and  11 , the read operation of the second method comprises the following steps: 
         [0077]    Step  220 , a third voltage V L  (0.05 v to 1 v) is applied to the bit-line  300  to produce a small voltage difference between the drain and the substrate of the MOSFET  200   a . It shall be properly selected so that the GIDL current is large enough for sense amplifier to detect and small enough to avoid disturb on the resistance. 
         [0078]    Step  221 , a fourth voltage pulse is applied to the gate of the select transistor  200  through the word-line  400  for a short duration (˜us to &lt;1 ms). This voltage pulse on gate (or selected word-line) is negative going from 0 v to −Vcc/2, so that a large enough read current is resulted for sense amplifier to determine the stored data in the switching resistor  100 . The sense amplifier simply compares the read current through the switching resistor with respect to the reference current through the reference resistor  500  in each cell. 
         [0079]    A larger read current (I R ) than the reference current corresponds to a low resistance state of the switching resistor  100  and defined as data ‘0’; while a smaller I R  corresponds to a high resistance state and defined as data ‘1’ 
         [0080]    As described above, the first and the second RRAM are the type of one transistor and one resistance (referred to as 1T1R cell). The following RRAM are the type of one transistor and two resistances (referred to as 1T2R cell). 
         [0081]      FIG. 12  is the schematic diagram of a third RRAM according to an embodiment of the present invention. Referring to  FIG. 12 , the third RRAM of the present invention includes a plurality of memory cells arranged in array with bit-lines and word-lines. Each memory cell comprises: a first switching resistor  101 , a second switching resistor  102  and a MOSFET  200   c . The first switching resistor  101  includes a first terminal and a second terminal, the first terminal of the first switching resistor  101  is connected to a first bit-line  301 , and the second terminal of the first switching resistor  101  is connected to the MOSFET  200   c . The second switching resistor  102  includes a third terminal and a fourth terminal, the third terminal of the second switching resistor  102  is connected to a second bit-line  302 , and the fourth terminal of the second switching resistor  102  is connected to the MOSFET  200   c . The MOSFET  200   c  includes a gate, a source, and a drain. The gate is connected to a word-line  400 . The GIDL currents at the drain and source of MOSFET  200   c  are used for read and write operations of the memory cell. 
         [0082]    It is noted that the source of the MOSFET  200   c  is connected to the second terminal of the first switching resistor  101 , the drain of the MOSFET  200   c  is connected to the fourth terminal of the second switching resistor  102 , and the substrate of the MOSFET  200   c  is connected to ground. 
         [0083]    The MOSFET  200   c  is assumed an n-type MOSFET. In read or write operation, the voltage applied to the gate (or the word-line  400 ) is always less than the Vt of the MOSFET  200   c , so that there is no inversion channel formed between the drain and the source during the read and write operations. 
         [0084]    The first switching resistor  101  and the second switching resistor  102  have bi-stable resistance states, and their resistance states can be sensed by comparing the current flowing through the first switching resistor  101  or the second switching resistor  102  with respect to a reference current. 
         [0085]    Based on the third RRAM of the present invention, a third method of operating the third RRAM is described below, which includes a write operation and a read operation. 
         [0086]      FIG. 15  shows a pulse scheme of the third method of operating the third RRAM.  FIG. 13   a  illustrates the write operation (of the third method) on the third RRAM.  FIG. 13   b  is a flow chart of the write operation (of the third method) according to the present invention. Referring to  FIGS. 13   a ,  13   b  and  15 , the write operation of the third method comprises the following steps: 
         [0087]    Step S 310 , a first voltage V H  (+Vcc/2) is applied to the first bit-line  301  or the second bit-line  302  to produce a large enough voltage difference between the first bit line  301  and the substrate of the MOSFET  200   c  or between the second bit line  302  and the substrate of the MOSFET  200   c.    
         [0088]    In this embodiment, the write operation of the first switching resistor  101  and the second switching resistor  102  can be independently performed in sequential manner. For example, if the first switching resistor  101  is selected to perform the write operation, the first voltage V H  is applied to the first bit-line  301  and 0 v is applied to the second bit line  302 . After completion of the write operation of the first switching resistor, then the second switching resistor can start to perform the write operation by biasing the second bit-line to V H  and the first bit-line is biased to 0 v. 
         [0089]    Step  311 , a second voltage pulse is applied to the gate of the MOSFET  200   c  through the word line  400  for a short duration (˜us to &lt;1 ms). This voltage pulse on gate (or the selected word-line) is negative going (from 0 v to −Vcc/2), so that a large enough write current pulse I w  is resulted for triggering the resistance change of the switching resistor  101 . It should be noted that the write current pulse I w  can be adjusted to be larger if the gate bias is more negative with larger magnitude 
         [0090]    The bias of un-selected word line is 0 v and it should be less than the Vt of the MOSFET  200   c . According to an embodiment of the present invention, a high resistance state of the first or the second switching resistor ( 101  or  102 ) represents data ‘1’ and a low resistance state represents data ‘0’ correspondently. Thus, all four binary conditions (00, 01, 10, and 11) or 2-bits data can be stored in one memory cell. 
         [0091]      FIG. 14   a  illustrates the read operation (of the third method) on the third RRAM.  FIG. 14   b  is a flow chart (of the third method) according to the present invention. Referring to  FIGS. 14   a ,  14   b  and  15 , the first read operation of the third method comprises the following steps: 
         [0092]    Step S 320 , a third voltage V L  (0.05 v to 1 v) is applied to the first bit-line  301  and the second bit-line  302 . It shall be properly selected so that the GIDL current is large enough for sense amplifier and small enough to avoid disturb on the resistance. 
         [0093]    Step  321 , a fourth voltage pulse is applied to the gate of the select transistor  200   c  through the word-line  400  for a short duration (˜us to &lt;1 ms). This voltage pulse on gate (or selected word-line) is negative going from 0 v to −Vcc/2, so that a large enough read current is resulted for sense amplifier to determine the stored data in the switching resistors  101  and  102  simultaneously. The read currents through the switching resistors  101  and  102  (I R1  and I R2 ) in each respective bit-line are compared in sense amplifier with respect to a reference current respectively. The reference current is provided from periphery circuit. 
         [0094]    A high resistance state of the first or the second switching resistor ( 101  or  102 ) represents data ‘1’ and a low resistance state represents data ‘0’ correspondently. Thus, all four conditions (00, 01, 10, and 11) or 2-bits data in the memory cell can be determined or read. 
         [0095]    As previously described in the third method of operating the third RRAM, the GIDL currents in switching resistors ( 101  and  102 ) are measured by respective sense amplifiers during the read operation. If the resistance state of the first switching resistor  101  always keeps opposite to the second switching resistor  102  during write operation, then only one sense amplifier is needed by simply comparing the read current in resistor  101  and  102 , i.e. the state of I R1 &gt;I R2  represents data ‘1’ and the state of I R2 &gt;I R1  represents data ‘0’. 
         [0096]    Based on the third RRAM of the present invention, a fourth method of operating the third RRAM is described below, which includes a write operation and a read operation. 
         [0097]      FIG. 18  shows the pulse scheme of the fourth method of operating the third RRAM.  FIG. 16   a  illustrates the write operation (of the fourth method) on the third RRAM during the write operation.  FIG. 16   b  is a flow chart of the write operation (of the fourth method) according to the present invention. The write operation of the fourth method comprises the following steps: 
         [0098]    Step S 410 , the memory cell is initialized to the same state, e.g. all resistors are at high resistance state (or “1”). 
         [0099]    Step  411 , a first voltage V H  (+Vcc/2) is applied to the first bit line  301  and a second voltage is applied to the word-line  400  to form a large GIDL current pulse, and the resistance state of the first switching resistor  101  is changed to low resistance state (“0”), then a pair of data “01” is stored in the cell. Similarly, a pair of data “10” can be stored in the 1 st  and 2 nd  resistors. 
         [0100]      FIG. 17   a  illustrates the read operation (of fourth method) on the third RRAM during the read operation.  FIG. 17   b  is a flow chart of the read operation (of the fourth method) according to the present invention. Referring to  FIGS. 17   a ,  17   b  and  18 , the read operation (of the fourth method) comprises the following steps: 
         [0101]    Step S 420 , a third voltage V L  (0.05 v to 1 v) is applied to the first bit-line  301  and the second bit line  302 . 
         [0102]    Step S 421 , the V g  is applied to the gate of the MOSFET  200   c  through the word-line  400 . The GIDL current of flowing through the first switching resistor  101  defines I R1 , while the GIDL current of flowing through the second switching resistor  102  defines I R2 . Because the resistance state of the first switching resistor  101  is always in the opposite to the resistance state of the second switching resistor, therefore, if I R1 &gt;I R2 , then the stored data is ‘1’, and similarly, if I R2 &gt;I R1 , then the stored data is ‘0’. 
         [0103]    As should be understood, the present invention is not limited to the switching resistor as illustrated; the switching resistor also includes the phase change resistor. 
         [0104]    The present invention has been described in conjunction with the preferred embodiments which, however, do not limit the invention. Various modifications and supplements may be made to the preferred embodiments by the ordinary skill in the art without departing from the spirit and scope of invention as set forth in the appended claims.