Abstract:
Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least one of the one or more layers, annealing at least a portion of the semiconductor device, and removing a substantial portion of the one or more layers, using one or more etching processes.

Description:
[0001]     This is a Divisional application of Ser. No.: 10/319,734 filed Dec. 12, 2002, which is presently pending. 
     
    
     BACKGROUND  
       [0002]     As part of the fabrication process for semiconductor devices such as integrated circuits (ICs), devices residing on a wafer typically undergo a heat treating or thermal annealing process, which may follow formation of one or more gate structures and implantation or doping of the wafer, for example. Annealing may serve several purposes, including physical repair of the silicon lattice structure following doping, and activation of the dopant.  
         [0003]     Laser annealing is one particular annealing process that may be utilized in the fabrication of semiconductor devices, and may provide rapid annealing of selected portions of a semiconductor device. Laser annealing may be performed using many different techniques, including pulsed and stepped laser annealing. Laser annealing provides heating of selected portions of a silicon wafer, rather than heating of the entire wafer to a uniform temperature as in alternative annealing methods.  
         [0004]     Present state of the art annealing methods such as laser annealing may result in uneven heating or temperature non-uniformity of surfaces of a semiconductor device, due at least in part to varying topographies or topologies of a device that are created during the fabrication process, and the nature of laser light being somewhat pattern dependent. For example, the topography of a semiconductor device may vary across the surface of the device. A surface on top of a substrate, in an area between two gates, may be in a lower relative vertical position than a top surface of a gate, for example. Because the topography differs among these surface points, a laser used in an annealing process may be absorbed or reflected differently depending on the pattern of the surface being irradiated. This may result in uneven heating among these surface points, which may result, for example, in the production of undesirable physical characteristics in a semiconductor device. A need exists, therefore, of a method and apparatus of reducing these thermal effects.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     The subject matter regarded as embodiments of the claimed subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. Embodiments of the claimed subject matter, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:  
         [0006]      FIG. 1   a  is an illustration of a silicon substrate with devices formed thereon;  
         [0007]      FIG. 1   b  is a illustration of a silicon substrate with devices formed thereon, wherein one or more devices has a layer formed thereon;  
         [0008]      FIG. 2   a  is a illustration of a silicon substrate with devices formed thereon, wherein one or more devices has a first layer formed thereon; and  
         [0009]      FIG. 2   b  is a illustration of a silicon substrate with devices formed thereon, wherein one or more devices have a first layer and a second layer formed thereon.  
     
    
     DETAILED DESCRIPTION  
       [0010]     Embodiments of the claimed subject matter may comprise a capping layer for a semiconductor device and a method of fabrication. As mentioned previously, during fabrication of a device such as a semiconductor device, one or more fabrication processes may result in the production of a partially fabricated device with varying topologies and/or topographies. This may result in uneven heating of one or more areas of the device when undergoing heating processes such as laser annealing, due at least in part to these variations, and the tendency of laser light to be pattern dependent. More specifically, laser light tends to be coherent, meaning, for example, that the reflectivity of laser light may vary as light is exposed to devices of various patterns. In operation, and in the context of topography variation, surface points on a device that form a particular topography relative to other surface points on the device may be over-heated, due at least in part on the laser being absorbed more or reflected less than other areas. Overheating may result in the altering the material properties of a device and eventual formation of salicide, and/or softening of surface materials and/or sub-surface materials. Softening may lead to deformation of the semiconductor device surface, and may prevent or reduce the capacity to form abrupt junctions on the semiconductor device, as just an example.  
         [0011]     Just as topography differs among surface points, topology may also differ among surface points. In this regard, a device substrate may include sections having different optical, chemical and/or electrical properties. For example, a substrate may include a substrate section, a source/drain region, and a gate oxide area, for example. Surface points on top of these materials may have a similar topography, but the topology differs, which affects how the surface points react to heat. Specifically, those surface points in respect of which the surface materials and/or sub-surface materials have relatively lower melting points may be over-heated, in comparison to surface points having a relatively higher melting point. Differences in the thermal conductivity of various materials can also result in an uneven heating of the surfaces, due at least in part to the different amounts of energy absorbed in different regions of the device. In this context, a semiconductor device may alternatively be referred to as a transistor or an integrated circuit (IC).  
         [0012]     Embodiments of the claimed subject matter may comprise a capping layer for a semiconductor device, and a method of fabrication. The method may comprise forming a capping layer comprising a first and second layer, wherein the first layer is formed on at least a portion of the top surface of a semiconductor device, a second layer is formed on at least a portion of the first layer, and the second layer is substantially planarized prior to annealing at least a portion of the device.  
         [0013]     It is worthy to note that any reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the claimed subject matter. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.  
         [0014]     Numerous specific details may be set forth herein to provide a thorough understanding of the embodiments of the claimed subject matter. It will be understood by those skilled in the art, however, that the embodiments of the claimed subject matter may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the embodiments of the claimed subject matter. It can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the claimed subject matter.  
         [0015]     Referring now in detail to the drawings wherein like parts are designated by like reference numerals throughout, there is illustrated in  FIG. 1   a  a semiconductor device that may be configured to incorporate at least one embodiment of the claimed subject matter, and may comprise, for example, a partially formed metal oxide semiconductor (MOS) based transistor. Shown in  FIG. 1   a  is a partially formed transistor for an integrated circuit. As is well-known, integrated circuits are usually manufactured on silicon or other semiconductor substrates. An integrated circuit may be comprised of millions of transistors such as partially formed transistor  100  of  FIG. 1   a . Devices such as partially formed transistor  100  typically include a substrate  108 , which may comprise silicon, for example. A gate dielectric  106  is typically formed on the substrate, and may comprise silicon dioxide or other dielectric material, for example. Gate  102  is typically formed on the gate dielectric. Gate  102  is formed from an electrically conductive material, such as a metal or polysilicon based material, for example. Spacers  110  may be formed on the sides of the gate  102  and gate dielectric  106 , and may be formed from a dielectric material. Spacers  110  may serve the purpose of separating the gate components from other components that will be formed proximate to the gate  102  during a later fabrication process, for example. One or more components such as source/drain regions (not shown) may be at least partially formed by doping and subsequent annealing. Embodiments of semiconductor devices such as transistors may vary, and the above-described device is provided for illustrative purposes. Fabrication of a semiconductor device such as partially formed transistor  100  is well known in the art, and may vary from the above-described method and still be in accordance with the claimed subject matter.  
         [0016]     The topography of device  100  varies across the device. For example, the top surface  116  of substrate  108  is in a lower relative vertical position than the top surface  114  of gate  102 . Because the topography differs among these top surfaces, methods of thermally treating devices such as device  100  may result in uneven heating among these surfaces. Just as topography differs among surfaces, topology may also differ among surfaces. Top surfaces  114  and  116  represent two surfaces having different topologies in respect of the surface materials and/or sub-surface materials used to form the structures embodying the top surfaces. Because the topology, including heat conduction characteristics of the underlying layers, may differ among these surfaces, methods of thermally treating devices such as device  100  may result in uneven heating among these surfaces, as described previously.  
         [0017]     During the formation of a semiconductor device, and prior to a heat treating process such as annealing, a layer  112  may be formed or deposited on at least a portion of one or more top surfaces of a device such as partially formed transistor  101  of  FIG. 1   b . Layer  112  may be comprised of material that may have a higher melting point that one or more materials comprising device  101 , such as a metal, for example. During a subsequent heat treating process, one or more components of a device that has a layer  112  formed or deposited thereon may begin to soften, but layer  112  may retain its shape and stiffness and may not soften, depending on the particular material used to form layer  112 . This may result, for example, in device  101  retaining its shape during thermal treating. However, as will be shown in greater detail later, this will not serve to reduce the problems encountered due to the tendency of laser light to be pattern dependent, and the resulting uneven heating resulting from varying topographies of a device. Specifically, uneven heating of the device and the problems associated with uneven heating may still result from laser annealing, even with the layer  112  formed on the device.  
         [0018]      FIG. 2   a  and  FIG. 2   b  illustrate utilization of one embodiment of a capping layer in accordance with the claimed subject matter. Shown in  FIG. 2   a  is partially fabricated transistor  200 , which may be structurally similar to partially formed transistor  100  of  FIG. 1 . Partially formed transistor  200  may be embodied on a silicon wafer (not shown). Partially formed transistor  200  may include a substrate  208 , which may comprise silicon, for example. A gate dielectric  206  is typically formed on the substrate, and may comprise silicon dioxide or other dielectric material, for example. Gate  202  is typically formed on the gate dielectric. Gate  202  is formed from an electrically conductive material, such as a metal or polysilicon based material, for example. Spacers  210  may be formed on the sides of the gate  202  and gate dielectric  206 , and may be formed from a dielectric material. A portion of the substrate  208  may be implanted with dopant (not shown). One or more heat treating processes may be utilized to activate the dopant. Formed on at least a portion of one or more surfaces of partially formed transistor  200  is a first layer  218 .  
         [0019]     First layer  218  may be comprised of one or more materials, or a combination of materials. In an embodiment, first layer  218  may include silicon dioxide (SiO 2 ). In another embodiment, first layer  218  may include silicon nitride (Si 3 N 4 ). In another embodiment, first layer  218  may include a combination of silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ). It will, of course, be understood that the claimed subject matter is not limited in this respect, but may comprise any material capable of being deposited one or more surfaces of a device such as partially formed transistor  200 , that exhibits desirable properties, such as a particular reflectivity, heat conduction, heat capacity or reactivity, as just a few examples. Additionally, first layer  218  may be formed by any number of methods, including chemical vapor deposition (CVD), one or more sputter processes, growing, or any number of other well known methods that may be incorporated for forming a layer such as first layer  218  on a surface, for example.  
         [0020]     In one embodiment, first layer  218  is formed on a substantial amount of the exposed surfaces of partially formed transistor  200 . The material comprising the first layer is selected based on a number of characteristics, which may include melting point, shape retention, or light absorption properties, and the ability to maintain mechanical and structural integrity during irradiation, for example. In this embodiment, first layer may comprise a silicon dioxide layer deposited by use of chemical vapor deposition, wherein the layer is deposited on a substantial portion of the exposed surfaces of partially formed transistor  200  to a thickness in the approximate range of 0.001 micron to 0.1 micron, for example, and may be formed to a substantially uniform thickness, for example, although the claimed subject matter is not so limited. A second layer may be subsequently formed on the top surface  222  of first layer  218 , as described in more detail in reference to  FIG. 2   b.    
         [0021]     Shown in  FIG. 2   b  is partially fabricated transistor  201 , which may be structurally similar to partially formed transistor  200  of  FIG. 2   a , but with a second layer  220  formed thereon. Partially formed transistor  201  may be embodied on a silicon wafer (not shown). Partially formed transistor  201  may include a substrate  208 , which may comprise silicon, for example. A gate dielectric  206  is typically formed on the substrate, and may comprise silicon dioxide or other dielectric material, for example. Gate  202  is typically formed on the gate dielectric. Gate  202  is formed from an electrically conductive material, such as a metal or polysilicon based material, for example. Spacers  210  may be formed on the sides of the gate  202  and gate dielectric  206 , and may be formed from a dielectric material. A portion of the substrate  208  may be implanted with dopant (not shown). One or more heat treating processes may be utilized to activate the dopant. Second layer  220  may be formed on at least a portion of the top surface  222  of first layer  218 .  
         [0022]     Second layer  220  may be comprised of one or more materials, or a combination of materials. In an embodiment, second layer  220  may include tungsten, titanium, tantalum, or one or more metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), for example. It is important to note, however, that the claimed subject matter is not limited in this respect, but may comprise any material capable of being deposited one or more surfaces of a device such as partially formed transistor  201  that exhibits desirable properties, such as a particular reflectivity, heat conduction, heat capacity or reactivity, and the ability to be planarized, as just a few example. Additionally, second layer  220  may be formed by any number of methods, including chemical vapor deposition (CVD), one or more sputter processes, growing, or any number of other well known methods that may be incorporated for forming a layer such as first layer  220  on a surface.  
         [0023]     In one embodiment, first layer  220  is formed on a substantial amount of the top surface  222  of first layer  218 . The material comprising the first layer is selected based on a number of characteristics, which may include melting point, shape retention, or light absorption properties, and the ability to maintain mechanical and structural integrity during irradiation or planarization, for example. In this embodiment, second layer  220  may comprise a titanium layer deposited by use of chemical vapor deposition, wherein the layer is deposited on a substantial portion of the top surface  222  of first layer  218 , and is formed to a thickness substantially greater than the thickness of first layer  218 . For example, first layer may have an approximate thickness of 0.1 micron, and second layer may be formed on the first layer to an approximate thickness of 1 micron, although, of course, the claimed subject matter is not so limited. When formed, the top surface  224  of second layer  220  may be substantially planar, although the claimed subject matter is not so limited. For example, one or more processes may be performed on a substantial portion of the top surface  224  of second layer  220 , resulting in top surface  224  being substantially planar.  
         [0024]     In one embodiment, after forming second layer  220 , one or more chemical mechanical processes may be used to substantially planarize the top surface  224  of second layer  220 , such as mechanical polishing or a wet etch, for example. This may result in the top surface  224  of second layer  220  being substantially planar. In this particular embodiment, after undergoing one or more chemical mechanical processes such as mechanical polishing, surface  224  may be substantially planar, and partially formed transistor  201  may undergo one or more thermal treating processes such as laser annealing. As described previously, laser light may be pattern dependent, and variations in the topography of a surface being annealed may cause differing portions of the surface to absorb more heat than others, which may result in overheating or underheating of particular areas. However, when a substantially planar surface, such as the top surface  224  of second layer  220  undergoes a laser annealing process, there are no substantial variations in topography, and the device  201  may be capable of absorbing laser light substantially evenly. This may result in one or more portions of device  201  being subjected to even heating in a thermal treating process, and as a result, many undesirable characteristics of uneven heating described previously may be abated.  
         [0025]     In one embodiment, it may be desirable to remove a portion of one or more layers formed on a device such as device  201  after one or more annealing processes. Removal may be by any number of methods, but it is envisioned that for the above-described first and second layers, a second layer  220  may be substantially removed prior to any removal of first layer  218 . In one embodiment, second layer  220  may be comprised of a metal nitride (e.g. titanium nitride). In this embodiment, removal may be accomplished by incorporating a hydroxide- or sulfuric acid/oxidant based chemistry that may etch at least a portion of second layer  220 . However, it is important to note that removal is not limited to a wet etch process or to use of a hydroxide or a sulfuric acid/oxidant based chemistry, but any removal process that results in the removal of a substantial portion of the second layer  220  is in accordance with the claimed subject matter.  
         [0026]     Removal of a substantial portion of the first layer  218  may be accomplished in a similar manner to that used in the removal of the second layer  220 . For example, in one embodiment, first layer  218  may be comprised of silicon dioxide (SiO 2 ). In this embodiment, removal may be accomplished by incorporating a hydroxide- or sulfuric acid/oxidant based chemistry that may etch at least a portion of first layer  218 . However, it is important to note that removal is not limited to a wet etch process or to use of a hydroxide or a sulfuric acid/oxidant based chemistry, but any removal process that results in the removal of a substantial portion of the first layer  218  is in accordance with the claimed subject matter.  
         [0027]     It can be appreciated that the embodiments may be applied to the formation of any semiconductor device wherein annealing may be desirable. Certain features of the embodiments of the claimed subject matter have been illustrated as described herein, however, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. Additionally, while several functional blocks and relations between them have been described in detail, it is contemplated by those of skill in the art that several of the operations may be performed without the use of the others, or additional functions or relationships between functions may be established and still be in accordance with the claimed subject matter. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the embodiments of the claimed subject matter.