Abstract:
A method of initiating a reset sequence for a MEMS capacitive microphone. The method includes monitoring an output of a microphone and detecting a mute condition in the output of the microphone indicative of a fault condition. The method also includes activating a timing circuit. The timing circuit is configured to indicate when a certain time period since the initiation of the timing circuit has elapsed. Upon expiration of the time period indicated by the timing circuit, a microphone reset sequence is initiated.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/782,149, filed on Mar. 14, 2013, the entire contents of which are incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to MEMS capacitive microphones and processing systems for the same. MEMS capacitive microphones operate utilizing conservation of charge. A high impedance switch network, usually consisting of two anti-parallel diodes with a MOS transistor in parallel with the diodes, is used to apply a fixed charge across two plates of a capacitor. When the microphone is initially turned on the MOS transistor is switched on allowing a DC voltage to be put on one plate of the capacitor while the other plate is held at a different electrical potential. When the capacitor is fully charged (typically within 10&#39;s of milliseconds) the MOS transistor is switched off and the capacitor is left with a fixed charge across the two plates. When sound pressure waves impinge on the moveable plate of the capacitor, the capacitance changes and, because the charge is fixed across the capacitor, the voltage increases or decreases proportionally to the amount of change in capacitance induced by the incident sound pressure. 
       SUMMARY 
       [0003]    When very large acoustic signals (acoustic overload signals) hit the membrane, they can cause a voltage excursion large enough to push the diodes towards a forward bias in the high impedance (HIZ) network. Once either diode becomes forward biased, charge is lost from the two plates of the capacitor and a new voltage is present across the plates of the capacitor. If this voltage loss is large enough, it can cause problems for the preamplifier that is buffering or amplifying the signal voltage. Depending on the design of the amplifier, the output stage can become current or voltage limited with a large enough input signal, or the common mode range of the amplifier can be exceeded, where both cases will cause the amplifier to fail. 
         [0004]    For MEMS microphones with a sense capacitance on the order of 1 pF, the high-impedance network needs to be on the order of 100 s of Terra-ohms in order to meet the low noise requirements from the biasing element of the microphone. With a 1 pF sensor and 10 Terra-ohm impedance the RC time constant for the system is 10 seconds. If a large acoustic signal causes a significant voltage excursion at the sense node, then the amplifier can voltage or current limit, preventing the amplifier from processing further acoustic signals while the HIZ network returns to its initial state over possible 10&#39;s of seconds, corresponding to the RC time constant of the HIZ. During this time the microphone is perceived to mute since it is no longer reproducing sound. 
         [0005]    In one embodiment, the invention provides a microphone system that includes a capacitive microphone diaphragm and a pre-amplifier for outputting a signal indicative of acoustic pressure (i.e., sound) on the microphone diaphragm. A comparator is configured to monitor the output of the pre-amplifier, and to detect a mute condition in the pre-amplifier output that is indicative of a fault condition. The system also includes a timing circuit. The timing circuit is configured to receive input from the comparator when the mute condition is detected and monitor the duration of the mute condition. When the duration of the mute condition exceeds a defined reset threshold (i.e., a certain period of time), a microphone reset sequence is initiated. 
         [0006]    The system allows for acoustic overload signals to be processed while present, but would trigger a power on reset for the HIZ network/module if the amplifier becomes voltage or current limited for a given amount of time. The comparator is used to detect whether the amplifier is voltage or current limited. With the introduction of a circuit block with a large time constant that can be reset, the output of the comparator can be used to allow the timing block to run while the microphone is muted. If the microphone comes out of a mute condition, the comparator would no longer detect the mute condition and the timing block would be reset. During acoustic overload signals, the timing block would be periodically reset as the amplifier rails out or current limits and then comes back into operation. With the periodic reset of the timing block it will not run long enough for its long time constant to trigger a reset signal to the HIZ network/module. If the amplifier gets stuck in a voltage or current limited state (e.g., when the diode(s) has become forward biased), then the timing block will run until its long time constant triggers a reset signal for the HIZ network/module. In this system, the time constant of the timing circuit has to be set so that it is longer than a minimum frequency periodic signal which should be processed. In most applications where one would want to have a low frequency corner less than 100 Hz this would require the time constant for the reset circuit to be over 10 milliseconds. 
         [0007]    In another embodiment, the invention provides a method of initiating a reset sequence for a MEMS capacitive microphone. The method includes monitoring an output of a microphone and detecting a mute condition in the output of the microphone indicative of a fault condition. The method also includes activating a timing circuit. The timing circuit is configured to indicate when a certain time period since the initiation of the timing circuit has elapsed. Upon expiration of the time period indicated by the timing circuit, a microphone reset sequence is initiated. 
         [0008]    Other aspects of the invention will become apparent by consideration of the detailed description and accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a block diagram of a reset circuit for a MEMS capacitive microphone. 
           [0010]      FIG. 2  is a flowchart of a method for initiating a reset sequence for a MEMS capacitive microphone having the reset circuit of  FIG. 1 . 
           [0011]      FIG. 3  is a graph of the waveforms generated by a MEMS capacitive microphone including the reset circuit of  FIG. 1 . 
           [0012]      FIG. 4  is a block diagram of an RC timing circuit for a MEMS capacitive microphone. 
           [0013]      FIG. 5  is a graph of the output of the amplifier and the “AMP COMP OUT” component of the circuit of  FIG. 3 . 
           [0014]      FIG. 6  is a block diagram of a timing circuit including a current onto capacitor configuration. 
           [0015]      FIG. 7  is a block diagram of a timing circuit including a D flip-flop clock divider. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    Before any embodiments of the invention are explained in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the following drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. 
         [0017]      FIG. 1  is a block diagram of a MEMS capacitive microphone system  100 . The microphone system  100  includes a capacitive microphone sensor  110 , a HIZ network/power-on reset module  120 , an amplifier  130 , a comparator  140 , and a timing circuit  150 . The comparator  140  detects any mute conditions on the output of the amplifier  130  and feeds the timing circuit  150  with a logic signal when a mute condition is detected. The timing circuit  150  outputs a power-on-reset signal to the HIZ/POR module  120  when the mute comparator has indicated a mute condition for a defined period of time. 
         [0018]      FIG. 2  illustrates a method of initiating a power-on reset when a mute condition is detected. When the microphone is powered on, the mute comparator  140  monitors the output of the amplifier  130  (step  201 ) and determines whether a mute condition arising from an acoustic overload signal is present (step  203 ). As long as no mute condition is detected, the output of the comparator  140  keeps the timing circuit  150  in a deactivated state (step  205 ). 
         [0019]    When the mute comparator  140  detects the mute condition  313 , it sends a logic signal to the timing circuit  150  to activate the timing circuit  150  (step  207 ). The timing circuit  150  then runs until expiration or until the mute condition is removed. Upon expiration of a defined period of time (step  209 ), the timing circuit  150  provides a POR enable signal to the HIZ/POR module  120 . In response to receiving the POR enable signal, the HIZ/POR module  120  initiates a new power-on-reset sequence (step  211 ). 
         [0020]      FIG. 3  provides a series of timing diagrams that illustrate and example of the operation of the microphone system  100  according to the method of  FIG. 2 .  FIG. 3  shows the time-based signals of the amplifier output  301  and the power-on-enable output  303  (provided from the timing circuit  150  to the HIZ/POR module  120 ).  FIG. 3  also illustrates the time  305  during which the power-on reset sequence is active by the HIZ/POR module  120 . When the microphone is first powered on at 0 ms, an initial power-on-reset (POR)  307  is performed by the HIZ/POR module  120 . As such, the power-on-reset output  305  illustrated in  FIG. 3  is high from 0 to 2 ms. There is no acoustic stimulus applied to the microphone system from 2 ms until 20 ms. Therefore, the amplifier output from 2 ms to 20 ms remains at its biased baseline output (i.e., 1V) as indicated by reference numeral  309 . As long as no mute condition is detected, the timing circuit  150  remains inactive as shown in timing diagram  303  from 0 ms to 41 ms. 
         [0021]    However, as indicated in timing diagram  301 , an acoustic overload is applied to the microphone system from 20 ms to ˜40 ms and, as a result, the amplifier output is current limited at the peaks and voltage limited (at 0V) at the troughs of the output signal (shown as  311  in timing diagram  301 ). When the acoustic overload is removed at ˜40 ms, the amplifier output exhibits a large DC offset which prevents it from processing a signal. Hence, a mute condition  313  is present on the amplifier output from ˜40 ms to 41 ms. When the mute condition  313  has been present for a defined period of time (e.g., ˜1 ms), the timing circuit  150  provides a POR enable signal  315  to the HIZ/POR module  120 . In response to the POR enable signal  315 , the HIZ/POR module  120  initiates another power-on reset sequence  317  from ˜41 ms to ˜42 ms. After the power-on-reset sequence  317  is performed, the amplifier produces a normal output  319  in response to acoustic pressures that do not produce an acoustic overload condition. 
         [0022]      FIG. 4  shows one embodiment of a timing circuit  401  that can be implemented as the timing circuit in the microphone system  100  of  FIG. 1 . The time constant for the timing circuit  401  is set by the resistor  403  and the capacitor  405 . The voltage on the capacitor  405  is provided to a comparator  407  where it is compared to a reference voltage  408 . When the amplifier  130  is in normal operation (i.e., no mute condition present), the output of the mute comparator  140  is held high which, in turn, holds a switch  409  in a closed position creating a short circuit between the terminals of the capacitor  405 . In this state, the comparator  407  determines that voltage on the capacitor  405  is less than the reference voltage  408  and produces a low “POR Enable” output to the HIZ/POR module  120 . 
         [0023]    However, when the amplifier mute comparator  140  detects a mute condition, the output of the mute comparator  140  goes low, causing the switch  409  to open. When the switch is opened and the short circuit is removed, the capacitor  405  begins to charge and the voltage on the capacitor  405  begins to exponentially rise. When the voltage on the capacitor  405  surpasses the reference voltage  408 , the output of the comparator  140  switches to high, sending an “POR Enable” signal to the HIZ/POR module  120  and initiating a power-on-reset sequence. 
         [0024]    As discussed above, the mute comparator provides “high” output signal whenever a “non-limited” output signal is detected from the amplifier. As such, in the presence of an acoustic overload signal with positive and negative edges (as shown by the amplifier output waveform  500  of  FIG. 5 ), the mute comparator output  407  will toggle between high and low (as shown by the mute comparator output waveform  501 ). This toggling between high and low causes the timing circuit  150  to be periodically reset. When the amplifier  130  is in a normal operating region the output of the mute comparator will be high, thus disabling the timing circuit  150 . When the amplifier  130  is either voltage or current limited, the output of the mute comparator will be low, enabling the timing circuit  150 . However, because the timing circuit requires that the output of the mute comparator be held low (indicating a mute condition) for a defined period of time before the POR Enable signal is generated, the sporadic voltage and current limiting caused by an acoustic overload does not trigger a power-on reset until the acoustic overload affects the charge on the capacitor (i.e., forward bias) resulting in a sustained mute condition. 
         [0025]      FIG. 6  shows another embodiment of a timing circuit  601 . In this example, the timing circuit  601  is current controlled such that the time constant of the timing circuit  601  is set by the current  603  flowing onto the capacitor  605 . Like the example of  FIG. 4 , the voltage on the capacitor  605  is provided to a comparator  607  where it is compared to a reference voltage  608 . When the output of the mute comparator  140  is high (indicating a normal amplifier output), a switch  609  is closed and creates a short-circuit between the terminals of the capacitor  605 . However, when the output of the mute comparator  140  goes low (indicating a mute condition), the switch  609  is opened and the constant current applied by the current controlled circuit  603  causes a linear increase in the voltage on the capacitor  605 . Once the voltage on the capacitor  605  exceeds the reference voltage  408 , the comparator  607  provides the POR Enable signal to the HIZ/POR module  120 . 
         [0026]      FIG. 7  illustrates yet another embodiment of a timing circuit  701 . In this example, the time constant is set by a clock divider  703  implemented with a series of D flip-flops  705 —more specifically, the time constant for this construction is set by the timing of a master clock for the timing circuit and the number of clock divisions (n) (i.e., the number of D flip-flops included in the series of D flip-flops). When the amplifier  130  is in normal operation, the output of the mute comparator  140  is high and a clear signal  707  is applied to the D flip flops  705 . The clear signal prevents the D flip-flops in the clock divider  703  from changing state. As such, in this state, the clock divider  703  does not operate and does not send a logic signal to the HIZ/POR module  120  enabling a power-on-reset. 
         [0027]    However, when the mute comparator  140  detects a mute condition, the output goes low and the clock divider  703  begins to divide. On the first clock cycle, the output of the first D-flip flop  705  changes state. Because this output is coupled to the next D flip-flop, the output of the next D flip-flop changes state on the next clock cycle. As long as the output of the mute comparator  140  remains low, each clock cycles causes another subsequent D flip-flop in the series of D flip-flops to change state until the final flip-flop  709  in the divider toggles and sends the POR Enable signal to the HIZ/POR module  120  enabling a power-on-reset. 
         [0028]    In the presence of an acoustic overload signal with positive and negative edges, the output of the mute comparator  140  will be nominally high. However, it will go low when the amplifier  130  either voltage or current limits at the peak of the acoustic signal. If the acoustic waveform transitions and causes the amplifier  130  to limit in the other direction, the transition will cause the mute comparator&#39;s  140  output to briefly go high in the transition region, therefore resetting each D flip-flop in the clock divider  703 . 
         [0029]    Thus, the invention provides, among other things, a system and method for allowing acoustic overload signals to be reproduced and to reset the microphone if a mute condition is detected. Various features and advantages of the invention are further illustrated in the attached figures.