Abstract:
In some embodiments, a fabrication method comprises: forming a structure that has one or more substrates, wherein the one or more substrates are either a single substrate or a plurality of substrates bonded together, wherein the structure comprises a non-electronically-functioning component which includes at least a portion of the one or more substrates and/or is attached to the one or more substrates; wherein the one or more substrates include a first substrate which has: a first side, an opening in the first side, and a conductor in the opening; wherein the method comprises removing material from the structure so that the conductor becomes exposed on a second side of the first substrate. In some embodiments, the second side is a backside of the first substrate, and the exposed conductor provides backside contact pads. In some embodiments, the fabrication method comprises: forming a structure comprising a first substrate which has: a first side, an opening in the first side, and a conductor in the opening; removing material from the structure so that the conductor becomes exposed on a second side of the first substrate; wherein removing of the material comprises removing the material from a first portion of the second side of the first substrate to cause the first portion to be recessed relative to a second portion of the second side of the first substrate.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   The present application is a division of U.S. patent application Ser. no. 09/791,977 filed Feb. 22, 2001 now U.S. Pat. 6,717,254, incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   The present invention relates to devices having substrates with openings passing through the substrates and conductors in the openings. Some-devices of the invention incorporate non-electronically-functioning components. Examples include micro-electro-mechanical systems (MEMS) and other micro-structure-technology (MST) structures. 
   Integrated circuit fabrication technology has been used to create micro-electro-mechanical and micro-electro-optical structures. Examples of such structures include relays, micropumps, and optical devices for fingerprint recognition.  FIG. 1  illustrates one such structure  120  formed on a semiconductor die (“chip”)  130 . The die contains electronic circuitry (not shown) and interconnect lines (not shown) which couple the structure  120  to contact pads  140 . The die has been fabricated in a batch process with other such dies on a semiconductor wafer. After the die was separated from the wafer by dicing, bond wires  150  were bonded to the contact pads  140  and lead frame pins  160 . Then the lead frame was encapsulated into a ceramic substrate  170 , with pins  160  protruding from the substrate. Another substrate  180  was bonded to substrate  170  to protect the die and the structure  120 . If the structure  120  is an optical device (e.g. a mirror or an optical sensor), the substrate  180  is made of a suitable transparent material, e.g. glass. 
   Improved fabrication techniques and structures suitable for such devices are desirable. It is also desirable to increase the mechanical strength of devices with or without non-electrically functioning components. 
   SUMMARY 
   Some embodiments of the present invention combine techniques for fabricating micro-electro-mechanical and micro-electro-optical structures with backside contact fabrication technology used for vertical integration and described in PCT publication WO 98/19337 (TruSi Technologies, LLC, May 7, 1998). 
   The invention is not limited to such embodiments. In some embodiments, a fabrication method comprises:
         forming a structure that has one or more substrates, wherein the one or more substrates are either a single substrate or a plurality of substrates bonded together, wherein the structure comprises a non-electronically-functioning component which includes at least a portion of the one or more substrates and/or is attached to the one or more substrates;   wherein the one or more substrates include a first substrate which has: a first side, an opening in the first side, and a conductor in the opening;   wherein the method comprises removing material from the structure so that the conductor becomes exposed on a second side of the first substrate.       

   In some embodiments, the second side is a backside of the first substrate, and the exposed conductor provides backside contact pads. The front side of the first substrate can be bonded to another substrate or substrates which protect the non-electronically-functioning component during processing, including the processing that exposes the conductor. The component is also protected during dicing. The other substrate or substrates can be transparent as needed in the case of an optical component. The other substrate or substrates can be closely positioned to the component to reduce optical distortion. Also, small system area can be achieved. 
   In some embodiments, the fabrication method comprises: 
   forming a structure comprising a first substrate which has: a first side, an opening in the first side, and a conductor in the opening; 
   removing material from the structure so that the conductor becomes exposed on a second side of the first substrate; 
   wherein removing of the material comprises removing the material from a first portion of the second side of the first substrate to cause the first portion to be recessed relative to a second portion of the second side of the first substrate. 
   The resulting structure may or may not have a non-electronically-functioning component. In some embodiments, the first substrate is thicker at the second portion than at the first portion. The thicker second portion improves the mechanical strength of the structure. 
   Other features and advantages of the invention are described below. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a vertical cross-sectional view of a prior art device having a micro-electro-mechanical or micro-electro-optical structure. 
       FIGS. 2A ,  2 B, and  3 - 16  are vertical cross-sectional views of devices with non-electronically-functioning components at different stages of fabrication according to the present invention. 
       FIGS. 17 and 18  are bottom views of devices having non-electronically-functioning components according to the present invention. 
       FIGS. 19-25  are vertical cross-sectional views of devices having non-electronically-functioning components at different stages of fabrication according to the present invention. 
       FIG. 26  is a bottom view of a device with non-electronically-functioning components according to the present invention. 
       FIGS. 27-29  are vertical cross-sectional views of devices with non-electronically-functioning components at different stages of fabrication according to the present invention. 
   

   DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 2A  illustrates miniature structures  120  fabricated in and/or on a wafer  210 . Structures  120  include optical, mechanical, magnetic, and/or other kinds of non-electronically-functioning components. Non-electronically-functioning components may or may not have electronic circuitry (e.g. transistors), but their operation includes functionality not present in traditional electronic circuitry. For example, a non-electronically-functioning component may have to move or deform during operation. Examples of such components are diaphragms of micropumps and moving parts of micro-mechanical switches. The component may emit and/or sense visible or invisible light (electromagnetic radiation). See J. E. Gulliksen, “MST vs. MEMS: WHERE ARE WE?”,  Semiconductor Magazine , October 2000, Vol. 1, No. 10. The component may be a mirror or a lens. Such components may be present in devices for fingerprint recognition, optical disc readers, bar code readers, or other MEMS and MST structures. A component may interact with an external magnetic field. The invention is not limited to any particular kind of components. The invention provides techniques that may be used with components not yet invented. 
   The non-electronically-functioning components of structures  120  may include parts of substrate  210 . The components may also include released components, i.e. components originally manufactured on another substrate (not shown) and then released from that substrate. See e.g. U.S. Pat. No. 6,076,256 (released mirrors). 
   Structures  120  can be coupled to circuitry  220  fabricated in and/or on substrate  210 . Circuitry  220  may be used in operation of the non-electronically-functioning components. The circuitry may control the components or receive signals indicative of the state of the components. Circuitry  220  may include amplifiers, filters, or any other electronic circuitry. Substrate  210  can be made from a suitable semiconductor material, for example, silicon. In some embodiments, circuitry  220  contains only interconnect lines. In some of these embodiments, substrate  210  is made from a non-semiconductor material, for example, a dielectric polymer or glass. 
   Circuitry  220  and/or structures  120  are connected to contact structures  230 . One structure  230  is shown on a larger scale in FIG.  2 B. Structures  230  can be fabricated as described, for example, in PCT publication WO 98/193 37 (TruSi Technologies, LLC, May 7, 1998); U.S. application Ser. No. 09/083,927, filed May 22, 1998 (now U.S. patent no. 6,184,060); and U.S. application Ser. No. 09/456,225, filed Dec. 6, 1999 (now U.S. patent no. 6,322,903); all of which are incorporated herein by reference. Briefly, vias  260  are etched in substrate  210 . Insulator  270  is formed in the vias. Conductor  280  (for example, metal) is formed over the insulator  270 . Optionally, another material  290  is formed over the conductor  280  to fill the vias 
   Insulator  270  can be omitted if wafer  210  is made from an insulating material. Also, the vias can be filled with conductor  280 . 
   Structures  120 , circuitry  220 , and contact structures  230  can be fabricated in any order. For example, circuitry  220  can be made first, contact structures  230  can be made next, and the structures  120  can be made last. Alternatively, the steps forming the elements  230 ,  220 , 120  can be interleaved, and the same steps can be used to form more than one of these elements. 
     FIG. 3  shows a wafer  310  which will be bonded to wafer  210 . Cavities  320  have been formed in the wafer. Alignment marks (not shown) can be formed on substrate  310  on the same or opposite side as cavities  320 . In one embodiment, wafer  310  is glass polished on top and bottom. In some embodiments, wafers  310  and  210  are made of the same material (for example, silicon) to match their thermal expansion coefficients. 
   Cavities  320  and the alignment marks can be formed by conventional processes. See for example, U.S. Pat. No. 6,097,140 (glass etch). 
   Wafers  310 ,  210  are bonded together (FIG.  4 ). Structures  120  become positioned in cavities  320 . The wafers can be bonded by conventional techniques, for example, with an adhesive or a glass frit in vacuum. Before the adhesive is deposited, and even before the structures  120  are attached to wafer  210 , portions of wafer  210  can be covered with an insulating material to insulate the wafer from the adhesive. 
   The wafers can also be bonded by solder bonding, eutectic bonding, thermocompression, with epoxy, and by other techniques, known or to be invented. 
   Then the backside  210 B of wafer  210  (the side opposite to the side bonded to wafer  310 ) is processed to expose the contacts  280 C formed by the conductor  280  at the bottom of vias  260 . This processing can be performed by methods described in U.S. patent application Ser. No. 09/456,225 (now U.S. Pat. No. 6,322,903) and PCT application WO 98/19337. According to one such method, substrate  210  and insulator  270  are etched by an atmospheric pressure plasma etch to expose the contacts  280 C. Then an insulator  520  ( FIG. 6 ) is grown selectively on silicon  210  but not on conductor  280 . 
   According to another method, after the conductor  280  has been exposed by the etch of substrate  210  and insulator  270 , the structure is turned upside down (FIG.  7 ), and insulator  520  is deposited by a spin-on or spraying process and then cured. Insulator  520  can be polyimide, glass, or some other flowable material (for example, a flowable thermosetting polymer.) The top surface of layer  520  is substantially planar, or at any rate the layer  520  is thinner over contact structures  230  than elsewhere. In some embodiments, layer  520  does not cover the contacts  280 C. If needed, layer  520  can be etched with a blanket etch to adequately expose the contacts  280 C (e.g., if insulator  520  covered the contacts). The etch does not expose the substrate  210 . The resulting wafer stmcture is like that of  FIG. 6   
   According to another method, the etch of substrate  210  exposes the insulator  270  but not the conductor  280 . See FIG.  8 . Insulator  270  protrudes from the substrate surface. The wafer structure is turned upside down (FIG.  8 ), and insulating layer  520  is formed as described above in connection with FIG.  7 . Layer  520  is thinner over the contact structures  230  than elsewhere. In some embodiments, layer  520  does not cover the contact structures. If needed, layer  520  can be etched with a blanket etch to adequately expose the insulator  270  (FIG.  9 ). Then insulator  270  is etched selectively to insulator  520  to expose the conductor  280 . In some embodiments, insulator  270  is silicon dioxide and insulator  520  is polyimide. The resulting wafer structure is like that of FIG.  6 . 
   One advantage of the processes of  FIGS. 5-9  is that no photolithography is required. Other techniques, including techniques involving photolithography, can also be used. 
   The wafer structure is diced into individual chips  1010  (FIG.  10 ). The structures  120  are protected by the substrates  210 ,  310  during dicing. 
   Chips  1010  can be attached to a wiring substrate (not shown), for example, a printed circuit board (PCB). Contacts  280 C can be directly attached to the wiring substrate using flip chip technology. See the aforementioned U.S. patent application Ser. No. 09/456,225. Alternatively, chips  1010  can be turned upside down, with the contacts  280 C facing up, and the chips can be wire bonded to a lead frame and packaged using conventional technology. Ball grid arrays, chip scale packages, and other packaging technologies, known or to be invented, can be used. 
   Advantageously, after wafers  210 , 310  have been bonded together, the structures  120  and circuitry  220  are protected by the two wafers. The area is small because the substrate  310  does not extend around the substrate  210  as in FIG.  1 . Cavities  320  can be made shallow so that the substrate  310  can be positioned close to structures  120 . This is advantageous for optical applications because optical distortion is reduced. Further, since substrate  310  is placed directly on substrate  210 , precise positioning of substrate  310  relative to structures  120  is facilitated. 
   For optical applications, substrate  310  can be covered by non-reflective coatings. Cavities  320  can be filled with refractive index matching materials. Lenses can be etched in substrate  310 . 
   Substrate  310  may contain electronic circuitry coupled to structures  120  and/or circuitry  220 . Substrate  310  can be fabricated from insulating or semiconductor materials. U.S. patent application Ser. No. 09/456,225 describes some techniques that can be used to connect circuitry in substrate  310  to circuitry  220 . 
     FIG. 11  illustrates an embodiment in which the backside contacts are redistributed along the backside  210 B of wafer  210  to obtain an area matched package. After the stage of  FIG. 4 , mask  1110  is formed on the backside  210 B of substrate  210  and photolithographically patterned. Optionally, before the mask is formed, substrate  210  can be thinned from backside  210 B, but the insulator  270  does not have to be exposed. The thinning can be performed by mechanical grinding, plasma etching, or other methods, known or to be invented. 
   Substrate  210  and insulator  270  are etched selectively to mask  1110  to expose contact portions  280 C of conductor  280  on backside  210 B (FIG.  12 ). Suitable etching processes are described above in connection with FIG.  5 . Then mask  1110  is stripped, and insulating layer  520  ( FIG. 13 ) is formed selectively on backside  210 B of substrate  210  but not on conductor  280 . See the description above in connection with FIG.  6 . 
   Conductive layer  1410  (FIG.  14 ), for example, a metal suitable for integrated circuit bond pads, is deposited and patterned on the wafer backside to provide conductive pads  1410 C and conductive lines connecting these pads to conductor  280 . Then a suitable insulator  1510  ( FIG. 15 ) is deposited and patterned to expose the conductive pads  1410 C. 
   Then the wafer structure is diced (FIG.  16 ). Pads  1410 C of the resulting chips  1010  can be attached directly to a wiring substrate, for example, a PCB. The bottom view of a single chip  1010  is shown in FIG.  17 .  FIG. 17  also shows an outline of mask  1110  of FIG.  11 . 
   One advantage of the embodiment of  FIGS. 11-17  is as follows. The position of contact structures  230  is limited by the layout of circuitry  220  and structures  120 . For example, the contact structures  230  may have to be restricted to the periphery of chips  1010 . Since contacts  280 C are not directly attached to a wiring substrate, their size can be reduced. The size of contact pads  1410 C is sufficiently large to allow direct attachment to a wiring substrate, but the position of contact pads  1410 C is not restricted by circuitry  220  and structures  120 . The chip area can therefore be smaller. 
   In  FIG. 18 , the mask  1110  has four extensions  1110 E extending to the boundary (e.g. corners) of chip  1010 . These extensions increase the mechanical strength of the chip. The extensions may come as close, or closer, to the chip boundary as the contacts  280 C. In some embodiments, the extensions reach the chip boundary and merge with the extensions on the adjacent chips. The extensions may extend between the contacts. More or fewer than four extensions can be provided. 
   The extensions can be formed in structures that do not have non-electronically-functioning components. 
   In another embodiment, the wafer structure is processed to the stage of  FIG. 6  by any of the methods described above in connection with  FIGS. 5-9 . Then conductive layer  1410  ( FIG. 19 ) is deposited and patterned on backside  210 B over insulator  520  to form contact pads  1410 C and conductive lines connecting the contact pads to conductor  280 , as described above in connection with FIG.  14 . Mask  1110  is not used. Then insulator  1510  is deposited and patterned to expose the contact pads  1410 C, as described above in connection with FIG.  15 . 
   The wafer structure is tested and diced to form individual chips  1010  (FIG.  20 ). 
     FIG. 21  illustrates alternative processing of wafer  310 . No cavities are etched in the wafer. Stand-off features  2110  are formed on the wafer surface. Features  2110  can be formed by depositing an appropriate material and patterning the material photolithographically, or by silk-screen printing, or by dispensing the material using a needle, or by other techniques, known or to be invented. Suitable materials include epoxy, thermosetting polymers, glass frit. 
   Wafer  210  is processed as in FIG.  3 . Then wafers  310 ,  210  are aligned and bonded as shown in FIG.  22 . Stand-off features  2110  are bonded to wafer  210 . Structures  120  are located between the stand-off features. Then the wafer structure is processed by any of the methods described above in connection with  FIGS. 5-20 . 
   In the embodiment of  FIG. 22 , material  2110  is used to fill the vias  260 . Material  290  that fills the vias in  FIG. 2B  is absent in  FIG. 22 , or is used to fill the vias only partially. Material  2110  is not fully hardened when the wafers are bonded. Material  2110  fills the vias  260  during the bonding process. The bonding is performed in vacuum to make it easier for the material  2110  to fill the vias  260 . 
   In some embodiments in which the bonding process starts before the material  2110  is hardened, spacers are formed on wafer  310  or  210 , or both, to maintain a minimum distance between the two wafers to prevent the wafer  210  from damaging the structures  120 . The spacers can be fixed hard features formed on the wafers. Alternatively, the spacers can be hard balls  2120  floating in material  2110 . The balls can be made of glass, resin, or some other suitable material (possibly a dielectric). Balls  2120  maintain the minimum distance between the wafers  310 , 210  when the wafers are bonded together. An exemplary diameter of balls  2120  is 10-30 μm. The diameter is determined by the distance to be maintained between the two wafers. See U.S. Pat. No. 6,094,244, issued Jul. 25, 2000. 
   In some embodiments, the stand-off features  2110  completely surround the structures  120  and maintain the vacuum in the regions in which the structures  120  are located. The vacuum helps to hermetically isolate the structures  120  when the ambient pressure increases to atmospheric pressure. The strength of the bond between the two wafers is also improved. 
   In some embodiments, the material  2110  is deposited on wafer  210  rather than wafer  310 . 
   In some embodiments, the material  2110  covers and contacts the structures  120 . 
   In some embodiments, the material  2110  is hardened before the wafers are bonded, and is not used to fill the vias  260 . 
   In  FIG. 23 , structures  120  do not protrude from the top surface of substrate  210 . No cavities or stand-off features are made on wafer  310 . This provides close positioning between the substrate  310  and structures  120 . This is particularly advantageous if the structures  120  have optical components. 
   In  FIGS. 24-26 , at least some of the contact structures  230  are positioned on the chip boundaries (on the dicing lines). In other respects, fabrication can proceed according to any method described above in connection with  FIGS. 5-23 .  FIG. 24  illustrates the wafer structure processed as in FIG.  4 .  FIG. 25  illustrates the structure after dicing.  FIG. 26  is a bottom view of a resulting chip  1010 . One advantage of placing the contact structures  230  on the chip boundaries is reduced area. Also, the contact structures  230  can be contacted on a side of the chip, especially if the material  290  is conductive or is omitted. If the wafer structure is processed as in  FIG. 16  or  20 , contacts  1410 C are available on the backside while contact structures  230  can be contacted on the sides. In some embodiments, the large width of vias  260  in which the contact structures are formed allows the vias to be etched by an isotropic etching process. Isotropic etching can be less expensive than anisotropic etching. 
   In some embodiments, the vias  260  are filled with material  2110 , as in FIG.  22 . 
   In  FIGS. 24-26 , the wafer  310  is as in FIG.  21 . In other embodiments with contact structures  230  on the chip boundaries, wafer  310  is as in  FIG. 3  or  23 . 
   In  FIG. 27 , cavities  2710  have been formed in wafer  310  on the top side along the dicing lines. Cavities  2710  can be formed before or after the wafers  310 , 210  are bonded together. Cavities  2710  can extend the whole length of the dicing lines, or can be scattered along the dicing lines in any pattern.  FIG. 28  shows the structure after dicing. Cavities  2710  reduce the stress during dicing and also reduce the time that the structure is exposed to the stress. The dicing damage is therefore less. This is particularly advantageous if substrate  310  is a transparent substrate used for optical purposes, since damage to substrate  310  can cause optical distortion. 
   Cavities  2710  can be used in conjunction with any of the structures and processes described above in connection with  FIGS. 2-26 . 
   Structures  120  can be manufactured using multiple wafers. In the example of  FIG. 29 , structures  120  include portions of wafer  210  and of wafers  2904  bonded to the front side of wafer  210 . Examples of such structures include micropumps. See for example U.S. Pat. No. 6,116,863 issued Sep. 12, 2000, entitled “Electromagnetically Driven Microactuated Device and Method of Making the Same”. In  FIG. 29 , passages  2910  in wafer  310  represent the pumps&#39; inlets and outlets. During fabrication, the wafers  2904  and the front side of wafer  210  are processed as needed to manufacturer the structures  120 . Wafers  210 ,  2904  are bonded together. Wafer  310  is processed as needed (for example, to form cavities  320  of  FIG. 3 , or stand-off features  2110  of  FIG. 24 , or passages  2910 ). Then wafer  310  is bonded to the top wafer  2904 . After that, fabrication proceeds as described above in connection with  FIGS. 4-28 . The backside of wafer  210  is processed to expose the contact structures  230 . The wafer backside in  FIG. 29  is as in  FIG. 19 , but other processes described above can also be used.  FIG. 29  shows the structure after dicing. 
   The embodiments described above illustrate but do not limit the invention. The invention is not limited to any particular materials, processes, dimensions, layouts, or to any particular types of structures  120 . Structures  120  may have mechanical components, that is, components that move during operation. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.