Abstract:
A display panel includes a first row line, a second row line, a first column line, a first transistor, and a second transistor. The second row line is parallel to the first row line. The first column line is vertical to the first row line and the second row line. The first transistor includes a first terminal, a second terminal, and a first control terminal coupled to the first row line. The second transistor includes a third terminal coupled to the first column line, a fourth terminal coupled to the first terminal, and a second control terminal coupled to the second row line.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a display panel, and in particular to a display panel with a plurality of pixel units. 
         [0003]    2. Description of the Related Art 
         [0004]      FIG. 1  is a schematic diagram of a conventional display panel. The display panel  10  comprises gate lines G 1 ˜G n , source lines S 1 ˜S m , and pixel units P 11 ˜P mn . Each set of one gate line and one source line intersecting to each other is used to control a pixel unit. For example, the gate line G 1  and source line S 1  intersect to each other and control the pixel unit P 11 . 
         [0005]    The equivalent circuit of the pixel units comprises the transistors T 11 ˜T mn , the storage capacitors Ccs 11 ˜Ccs mn , and the liquid crystal capacitors Clc 11 ˜Clc mn . Such a connection can turn all the transistors on the same line (i.e. positioned on the same gate line) on or off using a scan signal, such that the video signals are written into the corresponding pixel units through source lines. 
         [0006]    Taking a 1024×768 display panel as an example, since each pixel unit comprises three sub-pixels (R, G and B sub-pixels), the display panel needs 1024×3 source lines for controlling all the pixel units. 
         [0007]    The number of the pixel units is directly proportional to the resolution of display panel. When the resolution of the display panel is higher, the numbers of the pixel units and the source lines as well are required to be increased. 
         [0008]    Display panel  10  comprises various source drivers (not shown), each controlling a plurality of source lines. When the number of the source lines is increased, not only the aperture ratio of display panel  10  is reduced but also the number of source drivers is increased, causing the higher cost and volume of the display panel  10  and the smaller usable area space of the display panel  10 . 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    Display panels are provided. An exemplary embodiment of a display panel comprises a first row line, a second row line, a first column line, a first transistor and a second transistor. The second row line is parallel to the first row line. The first column line is vertical to the first row line and the second row line. The first transistor comprises a first terminal, a second terminal, and a first control terminal coupled to the first row line. The second transistor comprises a third terminal coupled to the first column line, a fourth terminal coupled to the first terminal, and a second control terminal coupled to the second row line. 
         [0010]    Display devices are also provided. An exemplary embodiment of a display device comprises a row driving unit, a column driving unit, and a display panel. The row driving unit provides a first row signal and a second row signal. The column driving unit provides a first column signal. The display panel comprises a first row line, a second row line, a first column line, a first transistor, and a second transistor. The first row line receives the first row signal. The second row line is parallel to the first row line and receives the second row signal. The first column line is vertical to the first row line and the second row line, and receives the first column signal. The first transistor comprises a first terminal, a second terminal, and a first control terminal coupled to the first row line. The second transistor comprises a third terminal coupled to the first column line, a fourth terminal coupled to the first terminal, and a second control terminal coupled to the second row line. 
         [0011]    Pixel structures are also provided. An exemplary embodiment of a pixel structure comprises a first row line, a second row line, a third row line, a first column line, a first transistor, a second transistor, a third transistor, and a fourth transistor. The second row line is parallel to the first row line. The third row line is parallel to the first row line. The first column line is vertical to the first row line and the second row line. The first transistor comprises a first terminal, a second terminal, and a first control terminal coupled to the first row line. The second transistor comprises a third terminal coupled to the first column line, a fourth terminal coupled to the first terminal, and a second control terminal coupled to the second row line. The third transistor comprises a fifth terminal, a sixth terminal, and a third control terminal coupled to the second row line. The fourth transistor comprises a seventh terminal coupled to the first column line, an eighth terminal coupled to the fifth terminal, and a fourth control terminal coupled to the third row line. During a first period, the first row line and the second row line are simultaneously enabled and a first data signal is transmitted to the first transistor and the second transistor through the first column line. During a second period, the second row line is enabled and a second data is transmitted to the second transistor through the first column line. During a third period, the second row line and the third row line are simultaneously enabled and a third data signal is transmitted to the second transistor, the third transistor, and the fourth transistor through the first column line. During a fourth period, the third row line is enabled and a fourth data is transmitted to the fourth transistor through the first column line. During a fifth period, the second row line is enabled and a fifth data is transmitted to the second transistor through the first column line. 
         [0012]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, where: 
           [0014]      FIG. 1  is a schematic diagram of a conventional display panel; 
           [0015]      FIG. 2  is a schematic diagram of an exemplary embodiment of a display device, according to the present invention; 
           [0016]      FIGS. 3 to 9  are schematic diagrams of another exemplary embodiment of a display device, according to the present invention; 
           [0017]      FIG. 10  is a schematic diagram of an exemplary embodiment of pixel units, according to the present invention; and 
           [0018]      FIG. 11  is a timing diagram of an exemplary embodiment of a driving method, according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0020]      FIG. 2  is a schematic diagram of an exemplary embodiment of a display device, according to the present invention. The display device comprises a column driving unit  22 , a row driving unit  24 , and a display panel  26 . The column driving unit  22  provides a plurality of column signals, such as a plurality of data signals, and the row driving unit  24  provides a plurality of row signals, such as a plurality of scan signals. The display panel  26  comprises the gate lines (row lines) G 0 ˜G n  for receiving the column signals, the source lines (column line) S 1 ˜S m-1  for receiving the row signals, and the pixel units P 11 ˜P mn . 
         [0021]    In this embodiment, the even source lines (shown by dashed lines in  FIG. 2 ) are omitted. Each of the transistors originally coupled to an even source line is changed to couple with one transistor of a neighboring pixel unit. If the two adjacent transistors coupled to the same source line are coupled to two different gate lines, respectively. 
         [0022]    For clarity, only the pixel units P 11  and P 21  are shown and given as an example. The pixel unit P 11  comprises a transistor T 11 , a storage capacitor Ccs 11 , a liquid crystal capacitor Clc 11 , and the pixel unit P 21  comprises a transistor T 21 , a storage capacitor Ccs 21 , and a liquid crystal capacitor Clc 21 . 
         [0023]    Since the source and drain of a transistor are determined according to the direction of current, the two terminals of the transistor are represented by “source/drain” or “drain/source.” 
         [0024]    A source/drain of the transistor T 11  is coupled to the source line S 1 . A gate of the transistor T 11  is coupled to the gate line G 1 . The storage capacitor Ccs 11  is coupled between a drain/source of the transistor T 11  and a common line com 1 . The liquid crystal capacitor Clc 11  is coupled between the drain/source of the transistor T 11  and a common line com 2 . The level of the common line com 1  differs from that of the common line com 2 . 
         [0025]    A source/drain of the transistor T 21  is coupled to the drain/source of the transistor T 11 . A gate of the transistor T 21  is coupled to the gate line G 0 . The storage capacitor Ccs 21  is coupled between a drain/source of the transistor T 21  and the common line com 1 . The liquid crystal capacitor Clc 21  is coupled between the drain/source of the transistor T 21  and the common line com 2 . 
         [0026]      FIG. 3  is a schematic diagram of another exemplary embodiment of a display device, according to the present invention. For clarity, only adjacent pixel units  32  and  34  are shown. A source/drain of the transistor  322  is coupled to the source line S 1 . A gate of the transistor  322  is coupled to the gate line G 0 . Transistor  342  comprises a source/drain coupled to a drain/source of the transistor  322 , a drain/source, and a gate coupled to the gate line G 1 . The storage capacitor  324  is coupled between the drain/source of the transistor  322  and the common line com 1 . The liquid crystal capacitor  326  is coupled between the drain/source of the transistor  322  and the common line com 2 . The storage capacitor  344  is coupled between the drain/source of the transistor  342  and the common line com 1 . The liquid crystal capacitor  346  is coupled between the drain/source of the transistor  342  and the common line com 2 . 
         [0027]      FIG. 4  is a schematic diagram of another exemplary embodiment of a display device. For clarity, only adjacent pixel units  42  and  44  are shown. A source/drain of the transistor  442  is coupled to the source line S 2 . A gate of the transistor  442  is coupled to the gate line G 1 . The transistor  422  comprises a source/drain coupled to a drain/source of the transistor  442 , a drain/source, and a gate coupled to the gate line G 0 . The storage capacitor  424  is coupled between the drain/source of the transistor  422  and the common line com 1 . The liquid crystal capacitor  426  is coupled between the drain/source of the transistor  422  and the common line com 2 . The storage capacitor  444  is coupled between the drain/source of the transistor  442  and the common line com 1 . The liquid crystal capacitor  446  is coupled between the drain/source of the transistor  442  and the common line com 2 . 
         [0028]      FIG. 5  is a schematic diagram of another exemplary embodiment of a display device. For clarity, only adjacent pixel units  52  and  54  are shown. A source/drain of the transistor  542  is coupled to the source line S 2 . A gate of the transistor  542  is coupled to the gate line G 0 . The transistor  522  comprises a source/drain coupled to a drain/source of the transistor  542 , a drain/source, and a gate coupled to the gate line G 1 . The storage capacitor  524  is coupled between the drain/source of the transistor  522  and the common line com 1 . The liquid crystal capacitor  526  is coupled between the drain/source of the transistor  522  and the common line com 2 . The storage capacitor  544  is coupled between the drain/source of the transistor  542  and the common line com 1 . The liquid crystal capacitor  546  is coupled between the drain/source of the transistor  542  and the common line com 2 . 
         [0029]      FIG. 6  is a schematic diagram of another exemplary embodiment of a display device, according to the present invention. For clarity, only adjacent pixel units  62  and  64  are shown. A source/drain of the transistor  622  is coupled to the source line S 1 . A gate of the transistor  622  is coupled to the gate line G 1 . Transistor  642  comprises a source/drain coupled to a drain/source of the transistor  622 , a drain/source, and a gate coupled to the common line com 1 . The storage capacitor  624  is coupled between the drain/source of the transistor  622  and the common line com 1 . The liquid crystal capacitor  626  is coupled between the drain/source of the transistor  622  and the common line com 2 . The storage capacitor  644  is coupled between the drain/source of the transistor  642  and the common line com 1 . The liquid crystal capacitor  646  is coupled between the drain/source of the transistor  642  and the common line com 2 . 
         [0030]      FIG. 7  is a schematic diagram of another exemplary embodiment of a display device, according to the present invention. For clarity, only adjacent pixel units  72  and  74  are shown. A source/drain of the transistor  722  is coupled to source line S 1 . A gate of the transistor  722  is coupled to the common line com 1 . The transistor  742  comprises a source/drain coupled to a drain/source of the transistor  722 , a drain/source, and a gate coupled to the gate line G 1 . The storage capacitor  724  is coupled between the drain/source of the transistor  722  and the common line com 1 . The liquid crystal capacitor  726  is coupled between the drain/source of the transistor  722  and the common line com 2 . The storage capacitor  744  is coupled between the drain/source of the transistor  742  and the common line com 1 . The liquid crystal capacitor  746  is coupled between the drain/source of the transistor  742  and the common line com 2 . 
         [0031]      FIG. 8  is a schematic diagram of another exemplary embodiment of a display device, according to the present invention. For clarity, only adjacent pixel units  82  and  84  are shown. A source/drain of the transistor  842  is coupled to the source line S 2 . A gate of the transistor  842  is coupled to the gate line G 1 . The transistor  822  comprises a source/drain coupled to a drain/source of the transistor  842 , a drain/source, and a gate coupled to the common line com 1 . The storage capacitor  824  is coupled between the drain/source of the transistor  822  and the common line com 1 . The liquid crystal capacitor  826  is coupled between the drain/source of the transistor  822  and the common line com 2 . The storage capacitor  844  is coupled between the drain/source of the transistor  842  and the common line com 1 . The liquid crystal capacitor  846  is coupled between the drain/source of the transistor  842  and the common line com 2 . 
         [0032]      FIG. 9  is a schematic diagram of another exemplary embodiment of a display device, according to the present invention. For clarity, the only pixel units  92  and  94  are shown. A source/drain of the transistor  942  is coupled to the source line S 2 . A gate of the transistor  942  is coupled to the common line com 1 . The transistor  922  comprises a source/drain coupled to a drain/source of the transistor  942 , a drain/source, and a gate coupled to the gate line G 1 . The storage capacitor  924  is coupled between the drain/source of the transistor  922  and the common line com 1 . The liquid crystal capacitor  926  is coupled between the drain/source of the transistor  922  and the common line com 2 . The storage capacitor  944  is coupled between the drain/source of the transistor  942  and the common line com 1 . The liquid crystal capacitor  946  is coupled between the drain/source of the transistor  942  and the common line com 2 . 
         [0033]      FIG. 11  is a timing diagram of an exemplary embodiment of a driving method for the pixel units shown in  FIG. 10 , which is similar to the display device in  FIG. 2 . The principle operation of the driving method is described as follows. 
         [0034]    During period T 1  in  FIG. 11 , the gate lines G 0  and G 1  are simultaneously enabled such that the storage capacitors and the liquid crystal capacitors of the pixel units  102  and  104  are charged through the source line S 1 , and the storage capacitors and the liquid crystal capacitors of the pixel units  106  and  108  are charged through the source line S 3 . 
         [0035]    During period T 2  in  FIG. 11 , the only gate line G 1  is enabled such that the storage capacitor and the liquid crystal capacitor of the pixel unit  102  are charged through the source line S 1 , and the storage capacitor and the liquid crystal capacitor of the pixel unit  106  are charged through the source line S 3 . 
         [0036]    During period T 3  in  FIG. 11 , the gate lines G 1  and G 2  are simultaneously enabled such that the storage capacitors and the liquid crystal capacitors of the pixel units  102 ,  112  and  114  are charged through the source line S 1 , and the storage capacitors and the liquid crystal capacitors of the pixel units  106 ,  116 , and  118  are charged through the source line S 3 . 
         [0037]    During period T 4  in  FIG. 11 , the only gate line G 2  is enabled such that the storage capacitor and the liquid crystal capacitor of the pixel unit  112  are charged through the source line S 1 , and the storage capacitor and the liquid crystal capacitor of the pixel unit  116  are charged through the source line S 3 . 
         [0038]    During period T 5 , the only gate line G 1  is enabled such that the storage capacitor and the liquid crystal capacitor of the pixel unit  102  are charged through the source line S 1 , and the storage capacitor and the liquid crystal capacitor of the pixel unit  106  are charged through the source line S 3 . 
         [0039]    The storage capacitors and the liquid crystal capacitors of the pixel units  102  to  108  and  112  to  118  store voltage according to the driving method. Since the driving method involves the operations of three adjacent gate lines G 0 -G 3 , all the gate lines can be divided into various groups, each comprising three gate lines, such that all the storage capacitors and the liquid crystal capacitors can be charged by way of the disclosed driving method. 
         [0040]    Since the even source lines can be omitted, the aperture ratio of the display panel of the invention increases and the number of the source driver decreases. Furthermore, more usable space on the display panel is created. 
         [0041]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.