Abstract:
A semiconductor device has: a semiconductor substrate formed with a number of semiconductor elements; a first interlayer insulating film formed above the semiconductor substrate and having a first wiring recess; a first copper wiring embedded in the first wiring recess; a second interlayer insulating film having a second wiring recess, the second interlayer insulating film including a copper diffusion preventing layer formed on the first copper wiring and the first interlayer insulating film, an oxide film formed on the copper diffusion preventing layer, and an organic insulating resin layer formed on the oxide film; and a second copper wiring embedded in the second wiring recess. A semiconductor device having copper wiring layers and organic insulating resin layers with less separation and its manufacture method are provided.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
         [0001]    This application is based on Japanese Patent Application No. 2002-168187, filed on Jun. 10, 2002, the entire contents of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    A) Field of the Invention  
           [0003]    The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having multilevel copper wiring layers and its manufacture method.  
           [0004]    B) Description of the Related Art  
           [0005]    The integration degree and operation speed of large scale integrated circuits are becoming increasingly high. As the integration degree becomes higher, semiconductor elements such as transistors constituting an integrated circuit is made more compact. A compact semiconductor element improves the operation speed. A delay time by wiring regulates the operation speed of a large scale integrated circuit. A wiring delay time depends on the wiring resistance and parasitic capacitance. Reducing the wiring resistance and parasitic capacitance is desired.  
           [0006]    Low resistance of wiring is realized by the main wiring material of Cu having a lower resistance than Al. Wiring material having a resistance lower than Cu is practically difficult.  
           [0007]    As semiconductor elements are made fine, the number of semiconductor elements fabricated on one semiconductor chip increases. The number of wiring lines is increased in order to interconnect a number of semiconductor elements. As the number of power supply lines and signal lines increases, the number of wiring layers increases. High density of wiring lines increases a wiring capacity.  
           [0008]    In order to shorten a wiring delay time, the wiring capacitance is required to be lowered. The material of interlayer insulating films for conventional Cu wiring layers is silicon oxide, F-doped silicate glass (FSG) or the like. An interlayer insulating film made of material having a smaller specific dielectric constant is desired to lower the wiring capacitance.  
           [0009]    In order to lower a wiring capacitance, organic insulating material having a low specific dielectric constant has been proposed as the material of an interlayer insulating film. One example of organic materials, SiLK (Trademark: Dow Chemical), has a specific dielectric constant of 2.65. As compared to SiO 2  having a specific dielectric constant of 4.2, the capacitance can be lowered by about 40%.  
           [0010]    After organic insulating material is coated in a liquid state, it is necessary to perform heat treatment at a temperature of about 400° C. for example. Organic insulating material has generally a large thermal expansion coefficient. The thermal expansion coefficient of SiO 2  is about 0.6 ppm, whereas that of SiLK is about 69 ppm. After the heat treatment is performed to form an insulating film, large tensile stress is generated at a room temperature.  
           [0011]    [0011]FIG. 2 shows an example of the structure of a large scale integrated circuit having interlayer insulating films made of organic insulating material. In the surface layer of a silicon substrate  10 , an element separation trench is formed and insulating material such as silicon oxide is embedded to form a shallow trench isolation (STI)  11 . On the surface of an active region defined by STI, a gate G of a MOS transistor is formed. In this way a transistor is formed. Necessary ions are implanted into the silicon substrate and other necessary processes are performed.  
           [0012]    On the surface of the semiconductor substrate  10 , an insulating layer  18  of a silicon oxide series such as phosphosilicate glass (PSG) is formed. Contact holes are formed and conductive material is filled in to form conductive plugs  19 . After the surface of the insulating film is planarized, an SiC layer  20 , a SILK layer  22  and an SiC layer  23  are laminated to form a first interlayer insulating film. For example, the SiC layer  20  is about 50 nm thick, the SiLK layer  22  is about 450 nm, and the SiC layer  23  is about 50 nm. In this interlayer insulating film, wiring trenches and via holes for connection to the underlying wiring layer are formed and a first wiring layer  29  made of copper as its main component is embedded.  
           [0013]    After the surface of the first interlayer insulating film is planarized, an SiC layer  30 , a SiLK layer  32  and an SiC layer  33  similar to those described above are formed to form a second interlayer insulating film. In the second interlayer insulating film, wiring trenches and connection via holes are formed and a second wiring layer  39  made of copper as its main component is embedded. Similarly, a third interlayer insulating film is formed by a lamination of an SiC layer  40 , a SiLK layer  42  and an SiC layer  43  and a third wiring layer  49  is embedded. A fourth interlayer insulating film is formed by a lamination of an SiC layer  50 , a SiLK layer  52  and an SiC layer  53  and a fourth wiring layer  59  is embedded. An SiC layer  60  is formed on the surface of the fourth wiring layer as a copper diffusion preventing layer.  
           [0014]    With this structure, peel-off or separation is likely to occur between the lower layers of the interlayer insulating films, i.e., copper diffusion preventing SiC layers  20 ,  30 ,  40  and  50  and the overlaid organic insulating resin layers  22 ,  32 ,  42  and  52 . If the number of wiring layers is increased, separation is more likely to occur.  
           [0015]    Separation does not occur between the SiC layer used as a hard mask and the underlying organic insulating resin layer. This may be ascribed to an improved surface quality of the organic insulating resin layer because the surface is exposed to plasma when the SiC layer is formed by plasma CVD.  
         SUMMARY OF THE INVENTION  
         [0016]    It is an object of the invention to provide a semiconductor device having copper wiring layers and organic insulating resin layers with less separation and its manufacture method.  
           [0017]    It is another object of the invention to provide a semiconductor device having a multilevel wiring structure and high reliability and being capable of high speed operation.  
           [0018]    According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate formed with a number of semiconductor elements; a first interlayer insulating film formed above the semiconductor substrate and having a first wiring recess; a first copper wiring embedded in the first wiring recess; a second interlayer insulating film having a second wiring recess, the second interlayer insulating film including a copper diffusion preventing layer formed on the first copper wiring and the first interlayer insulating film, an oxide film formed on the copper diffusion preventing layer, and an organic insulating resin layer formed on the oxide film; and a second copper wiring embedded in the second wiring recess.  
           [0019]    According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of: (A) forming a first interlayer insulating film above a semiconductor substrate formed with a number of semiconductor elements; (B) forming a first wiring recess through the first interlayer insulating film; (C) embedding a first copper wiring in the first wiring recess; (D) forming a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film covering the first copper wiring and including a copper diffusion preventing layer, a first oxide film and an organic insulating resin layer in this order from a bottom; (E) forming a second wiring recess through the second interlayer insulating film; and (F) embedding a second copper wiring in the second wiring recess.  
           [0020]    The oxide film has the function of an adhesion layer between the copper diffusion preventing layer and organic insulating resin layer. Since the oxide film exists, separation is not likely to occur. Since the oxide film has a high specific dielectric constant, a wiring capacity increases if it is made thick. The oxide film has preferably a thickness of 5 to 20 nm.  
           [0021]    As above, even if an organic insulating resin layer is used as the interlayer insulating film, it becomes possible to suppress separation. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    [0022]FIGS. 1A to  1 K are schematic cross sectional views illustrating the processes of manufacturing a semiconductor device according to an embodiment of the invention.  
         [0023]    [0023]FIG. 2 is a schematic cross sectional view showing the structure of a semiconductor device according to related art. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]    An embodiment of the invention will be described with reference to the accompanying drawings.  
         [0025]    As shown in FIG. 1A, an element separation trench is formed in the surface layer of a silicon substrate  10  and insulating material such as silicon oxide is embedded to form a shallow trench isolation (STI)  11 . If necessary, before or after STI is formed, ions are implanted to form desired well regions in the surface layer of the silicon substrate  10 .  
         [0026]    An insulated gate electrode G is formed on the surface of the silicon substrate  10 . The insulated gate electrode G is made of a lamination of a gate oxide film  14 , a polysilicon gate electrode  15  and a silicide electrode  16 . Side wall spacers  17  of silicon oxide or the like are formed on the side walls of the insulated gate electrode G. Desired ions are implanted into the silicon substrate on both sides of the gate electrode G before and after the side wall spacers  17  are formed, to thereby form source and drain regions with extensions. A CMOS transistor structure is formed by forming n- and p-channel transistors.  
         [0027]    After the transistor structure is formed, a phosphosilicate glass (PSG) layer  18  is formed on the surface of the silicon substrate  10  by CVD, and the surface of this layer is planarized. Contact holes are formed through the PSG layer  18  and conductive plugs  19  made of a TiN barrier layer and a CVD W layer are filled in the contact holes. An unnecessary conductive layer on the surface of the PSG layer  18  is removed by chemical mechanical polishing (CMP) or the like.  
         [0028]    Semiconductor elements and interconnect electrodes may be formed by any one of known manufacture methods. For example, the element separation regions may be formed by local oxidation of silicon (LOCOS) instead of STI. Pocket regions may be formed for a transistor. Instead of PSG, other oxide films or the like may be used. The barrier metal layer may be a lamination of a Ti layer, a TiN layer, a TaN layer and the like. The conductive plug may be made of silicon or the like.  
         [0029]    After the conductive plug  19  is formed, an SiC layer  20  having a thickness of about 30 nm is formed on the surface of the PSG layer  18 , covering the conductive plug  19 . The SiC layer  20  is formed by plasma CVD under the conditions of a pressure of 1.8 torr and a substrate temperature of 400° C. while Si(CH 3 ) 4  of 500 sccm and CO 2  of 2500 sccm are flowed as source gasses.  
         [0030]    After the SiC layer  20  is formed, an SiO 2  layer  21  as an adhesion layer is formed to a thickness of about 20 nm.  
         [0031]    For example, the SiO 2  layer  21  is grown by plasma CVD under the conditions of an RF power of 320 W, a pressure of 4.5 torr and a substrate temperature of 400° C. while SiH 4  of 32 sccm, N 2 O of 480 sccm and N 2  of 4500 sccm are flowed as source gasses. The oxide film may be formed by other methods such as sputtering. By inserting an oxide film between an SiC layer and an organic insulating resin layer, adhesion can be improved.  
         [0032]    The surface of the SiC layer is hydrophobic and the surface of the oxide is hydrophilic. Hydrophilic property and improved adhesion may be ascribed to OH bonds formed on the surface of the oxide. The SiC layer  20  and SiO 2  layer  21  provide the functions of a protective layer for a semiconductor element, an etch stopper layer and the like.  
         [0033]    After the SiO 2  layer  21  is formed, an organic insulating resin layer  22  is formed on the surface of the SiO 2  layer. For example, the organic insulating resin layer  22  is made of SILK (registered trade mark) available from the Dow Chemical Company and has a thickness of about 450 nm. The organic insulating resin layer is formed by coating liquid of organic insulating resin, for example, by spin coating, baking it for 90 seconds at 320° C. to evaporate solvent and stabilize the resin, and thereafter performing a curing process for 30 minutes at 400° C. in an N 2  atmosphere. The hardening process changes triple coupling of C to a benzene ring so that the resin is chemically stabilized.  
         [0034]    Materials other than SiLK may be used for the organic insulating resin layer, such as FLARE (registered trademark) available from the Honeywell Electronic Materials Company. The organic insulating resin layer of FLARE is formed by spin coating followed by a heat treatment process, similar to the layer of SiLK.  
         [0035]    On the organic insulating resin layer  22 , a dual hard mask layer is formed by CVD. The dual hard mask layer is made of an SiC layer  23  of about 50 nm thick and an SiO 2  layer  24  of 100 nm thick. The growth condition of the SiC layer  23  is the same as that of the SiC layer  20 . The growth condition of the SiO 2  layer  24  is a faster deposition speed than that for the SiO 2  layer  21 . For example, the SiO 2  layer  24  is formed under the conditions of an RF power of 455 W, a pressure of 5 torr and a substrate temperature of 400° C. while SiH 4  of 130 sccm, N 2 O of 636 sccm and N 2  of 2000 sccm are flowed as source gasses.  
         [0036]    As shown in FIG. 1B, a photo resist layer is coated on the SiO 2  layer  24 , exposed and developed to form a photo resist pattern PR 1 . The photo resist pattern PR 1  has openings corresponding to a wiring pattern. By using the photo resist pattern PR 1  as a mask, the SiO 2  layer  24  is etched. For example, the SiO 2  layer  24  having a thickness of about 100 nm is dry-etched by using CF 4 /O 2 /Ar as etchant gas. The photo resist pattern is thereafter removed.  
         [0037]    [0037]FIG. 1C is a schematic cross sectional view showing the substrate structure after etching. As shown, the SiO 2  layer  24  is selectively etched and trench openings  25  are formed which define the plan shape of a wiring pattern.  
         [0038]    As shown in FIG. 1D, after the pattern of the SiO 2  layer  24  is formed, a new photo resist layer is coated on the whole surface of the substrate, exposed and developed to form a photo resist pattern PR 2 . The photo resist pattern PR 2  has openings corresponding to via holes. By using the photo resist pattern PR 2  as a mask, the SiC layer  23  and organic insulating resin layer  22  are etched.  
         [0039]    First, the SiC layer  23  is dry-etched by using, for example, CH 2 F 2 /O 2 /N 2  as etching gas. If there is mask misalignment and the SiO 2  layer  24  is exposed in the opening, both the SiO 2  layer  24  and SiC layer  23  are etched.  
         [0040]    Next, the organic insulating resin layer  22  is dry-etched by using, for example, NH 3 /Ar/N 2  as etching gas. During etching of the organic insulating layer  22 , the photo resist pattern PR 2  is also etched. After the photo resist pattern PR 2  is etched, the patterned SiC layer  23  is used as the mask.  
         [0041]    [0041]FIG. 1E is a schematic cross sectional view showing the substrate structure after etching. As shown, via holes  26   x  reach the surfaces of the underlying SiO 2  layer  21 . Organic insulating resin can be etched at a high selection ratio relative to an inorganic insulating layer such as an SiC layer and an oxide film.  
         [0042]    As shown in FIG. 1F, by using the SiO 2  layer  24  as a mask, the SiC layer  23  of about 50 nm thick is etched. The etching condition of the SiC layer  23  is the same as that described earlier for etching this layer  23  for example. The SiC layer  23  is etched to have a wiring trench shape. At this time, the mask SiO 2  layer  24  and the SiO 2  layer  21  exposed on the via hole bottom are slightly etched.  
         [0043]    Next, by using the SiO 2  layer  24  and SiC layer  23  as a mask, the organic insulating resin layer  22  is etched to a depth of about 200 nm for example. The etching condition of the organic insulating resin layer  22  is the same as that described earlier for etching this layer  22  for example.  
         [0044]    Thereafter, by using the organic insulating resin layer  22  as a mask, the SiO 2  layer  21  and SiC layer  20  exposed at the via hole bottom are etched. At this time, the top surface of the SiO 2  layer  24  is partially etched.  
         [0045]    [0045]FIG. 1G is a schematic cross sectional view showing the substrate structure after etching. As shown, a wiring trench  27  is formed to a depth of 200 nm of the organic insulating resin layer  22 , and a via hole  26  is formed at the deeper position so that the surface of the conductive plug  19  is exposed. This wiring recess is buried with a barrier metal layer and a copper layer to form dual damascene copper wiring.  
         [0046]    As shown in FIG. 1H, a Ta layer as a barrier metal layer is deposited on the whole substrate surface to a thickness of about 25 nm by sputtering. On the Ta layer, a Cu layer is deposited to a thickness of about 100 nm. The Ta layer functions as a barrier metal layer and the overlaid Cu layer functions as a seed layer for Cu plating. After the seed layer is formed, a Cu layer is deposited by electrolytic plating to form a wiring layer  29   x.    
         [0047]    As shown in FIG. 1I, an unnecessary conductive layer over the interlayer insulating film is removed by chemical mechanical polishing (CMP). Since the SiC layer has a high selection ratio of CMP, CMP is performed by using the SiC layer  23  as a stopper. This CMP removes the SiO 2  layer  24 . The substrate surface after CMP exposes the copper wiring layer  29  and SiC layer  23 .  
         [0048]    As shown in FIG. 1J, covering the copper wiring layer  29 , a copper diffusion preventing SiC layer  30  is deposited on the SiC layer  23  to a thickness of about 50 nm by plasma CVD. For example, this plasma CVD is performed under the conditions of a pressure of 1.8 torr and a substrate temperature of 400° C. while Si(CH 3 ) 4  of 500 sccm and CO 2  of 2500 sccm are flowed as source gasses.  
         [0049]    Next, on the SiC layer  30 , an SiO 2  layer  31  as an adhesion layer is deposited to a thickness of about 20 nm by plasma CVD. The SiO 2  layer  31  improves the surface state of the copper diffusion preventing layer  30  and enhances adhesion. The SiO 2  layer  31  is formed in a better state on the hydrophobic surface of the copper diffusion preventing SiC layer  30  and forms a hydrophilic surface. On this hydrophilic surface, an organic insulating resin layer can be coated in a better state and with an improved adhesion.  
         [0050]    The silicon oxide layer as an adhesion layer may not be a pure silicon oxide layer. A silicon oxide layer with additive may be used as an adhesion layer. The adhesion silicon oxide layer does not have the copper diffusion preventing function and has a high specific dielectric constant of about 4.2 or higher. It is therefore preferable to form the adhesion silicon oxide layer thin so long as it provides the function of the adhesion layer. It is preferable to form the silicon oxide layer of 5 nm to 200 nm thick as the adhesion layer.  
         [0051]    The slower deposition speed is set as the plasma CVD condition for the silicon oxide layer  31 . For example, the silicon oxide layer  31  is formed under the conditions of an RF power of 320 W, a pressure of 4.5 torr and a substrate temperature of 400° C. while SiH 4  of 32 sccm and N 2 O of 480 sccm are flowed as source gasses and N 2  of 4500 sccm is flowed as carrier gas.  
         [0052]    After the SiO 2  layer  31  is deposited, an organic insulating resin layer  32  is formed. An SiC layer  33  and an SiO 2  layer  34  are deposited as a hard mask layer. In this manner, the second interlayer insulating film is formed. The oxide film and SiC layer are preferably formed at a temperature of 500° C. or lower because there is the organic insulating resin layer. Above-mentioned plasma CVD and the like meet this condition.  
         [0053]    The structure shown in FIG. 1J has the organic insulating resin layer still not formed with a wiring layer as shown in FIG. 1A. Processes similar to those shown from FIG. 1B to FIG. 1I are performed so that the second wiring layer can be formed. By repeating similar processes, the structure having a desired number of wiring layers can be formed.  
         [0054]    [0054]FIG. 1K shows the structure of four wiring layers.  
         [0055]    The second interlayer insulating film is made of a lamination of an SiC layer  30 , an SiO 2  layer  31 , an organic insulating resin layer  32 , an SiC layer  33  and an SiO 2  layer (not shown). A wiring recess is formed and a second wiring layer  39  is embedded. An unnecessary wiring layer is removed by CMP and an oxide film  34  is removed. In this manner, the second wiring layer is formed.  
         [0056]    The third interlayer insulating film is made of a lamination of an SiC layer  40 , an SiO 2  layer  41 , an organic insulating resin layer  42 , an SiC layer  43  and an SiO 2  layer (not shown). A wiring recess is formed and a third wiring layer  49  is embedded. CMP is performed to expose the surface of the SiC layer  43 . Similarly, the fourth interlayer insulating film is made of a lamination of an SiC layer  50 , an SiO 2  layer  51 , an organic insulating resin layer  52 , an SiC layer  53  and an SiO 2  layer (not shown). A fourth wiring layer is formed by using a copper wiring layer  59 . If the fourth wiring layer is the highest level layer, an SiC layer  60  as a copper diffusion preventing layer is formed on the surface of the fourth wiring layer.  
         [0057]    As described above, a multilevel wiring structure is formed by using organic insulating resin layers of material having a low specific dielectric constant such as SiLK. An oxide film as an adhesion layer is inserted between the organic insulating resin layer and underlying copper diffusion preventing layer. The oxide film functions as a separation or peel-off preventing layer.  
         [0058]    Scratch tests were conducted. The result of scratch tests was 13.07 gF when the oxide film was not inserted. The result of scratch tests was 14.12 gF when an SiO 2  layer was inserted between the organic insulating resin layer and underlying SiC layer. Adhesion can be improved and separation of the interlayer insulating film can be suppressed.  
         [0059]    Although the SiC layer is used as the copper diffusion preventing layer in the embodiment, an SiN layer or an SiCN layer may also be used as the copper diffusion preventing layer.  
         [0060]    The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It is apparent that various modifications, improvements, combinations, and the like can be made by those skilled in the art.