Abstract:
To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor device provided with multi-level interconnects and a manufacturing method thereof.  
           [0003]    In particular, the invention relates to a semiconductor integrated circuit device having multi-level interconnects with low parasitic capacitance and operated at high speed of several hundreds of MHz or more and a manufacturing method thereof.  
           [0004]    2. Description of Related Art  
           [0005]    In a semiconductor integrated circuit device operated at high speed of several hundreds of MHz or more, signal propagation delay due to parasitic capacitance in multi-level interconnects is significant.  
           [0006]    [0006]FIG. 1 is a schematical plan view of multi-level interconnects. Reference numeral  1  denotes a semiconductor substrate,  4  a lower level interconnect,  14  a via, and  24  a higher level interconnect. Normally, adjacent level interconnects are laid out in directions crossing perpendicularly to each other. This means that the area to face each other is small between higher level and lower level interconnects. As a result, parasitic capacitance between adjacent interconnects in a level is generally larger than that between interconnects in different levels, and exert more influence on signal propagation delay. Accordingly, attempts have been made to reduce parasitic capacitance between the adjacent interconnects in a level by replacing the insulating film material (silicon oxide film (specific dielectric constant: k˜4) and silicon nitride film (k˜7)) between adjacent interconnects in a level with insulating film material with lower dielectric constant.  
           [0007]    Methylsiloxane type film is one of the low dielectric constant film (k˜about 3 or lower). This is a film having Si—CH 3  bond and Si—O—Si bond as main components. In addition, Si—H bond or Si—C—Si bond may be contained. There are the following methods to form the film: spin-coating and chemical vapor deposition (CVD). In the spin-coating, oligomer solution containing methylsiloxane (spin-on glass (SOG)) is deposited by spin-coating, and then is cured. In the CVD, a gas containing Si—CH 3  bond reacts with oxidizing gas in a CVD chamber. The advantageous feature of methylsiloxane type film is that it has high heat-resistant property and is stable in heat treatment (up to 450° C.) in the manufacturing process of multi-level interconnects.  
           [0008]    However, when high-pressure oxygen plasma treatment is performed on methysiloxane type film, the film is deteriorated due to oxygen radicals in the plasma and absorbs moisture, and the quality of the film such as electrical characteristics is deteriorated. For this reason, conventional type patterning method cannot be used, in which a resist mask is removed by high-pressure oxygen plasma treatment after transferring the pattern.  
           [0009]    A first method to solve this problem is disclosed in Japanese Patent Application 151102/1988, which describes the use of low-pressure oxygen plasma to remove the resist. According to this method, deterioration of the quality of methylsiloxane type film is suppressed. This is because oxygen ions in the low-pressure oxygen plasma modify the surface of the methylsiloxane type film to fine silicon oxide, and this surface layer protects inner part of the film from oxygen radicals.  
           [0010]    There is a second method to prevent deterioration of the quality when the resist is removed, and this is disclosed in JP-A-87502/1999. It is a method to transfer resist pattern to hard mask, and after removing the resist in advance, the methylsiloxane type film is etched using the hard mask.  
           [0011]    [0011]FIG. 2 to FIG. 4 each represents a cross-sectional view showing of a manufacturing process to explain the second method. On a methylsiloxane type film  6 , a hard mask material  8  such as silicon nitride is deposited. A silicon oxide film  27 , and further, a resist  9  are formed on it, and the resist is patterned by lithography (FIG. 2). After etching the silicon oxide film  27  using the resist mask  9 , the resist  9  is removed (FIG. 3). In this case, the methylsiloxane type film  6  is covered with the hard mask material  8 , and it is not exposed to oxygen plasma, and hence, it is not deteriorated. After transferring the pattern to the hard mask  8 , the silicon oxide film  27  is removed. Then, using the hard mask  8 , the methylsiloxane type film  6  is patterned (FIG. 4).  
           [0012]    According to the first method as described above, it is not possible to form a hole pattern or a trench pattern with high aspect ratio (depth over diameter or depth over trench width) . When the aspect ratio increases, the number of ions impinging on the pattern side-wall surface is decreased. As a result, surface passivation layer is not formed on the methylsiloxane type film and its quality is deteriorated. In practical application, this method is effective only in the case where the aspect ratio &lt;3.  
           [0013]    When the methylsiloxane type film is fabricated by the second method as described above, shoulder portion of the hard mask  8  collapses diagonally as shown in FIG. 4 (faceting). In case low resistance copper wire is used as the lower level interconnect  4 , an etching stopper  5  on the surface of the interconnect must be etched (FIG. 5). As the etching stopper  5 , silicon nitride film, silicon carbide film, etc. are used. Under the etching condition to etch the etching stopper  5 , both the hard mask  8  and the methylsiloxane type film  6  are etched at the similar rate as the etching stopper  5 . As a result, faceting of the hard mask  8  occurs more remarkably (FIG. 6). When there is a portion where the hard mask  8  completely disappears, faceting occurs on the methylsiloxane type film  6  underneath. Further, the faceting is expanded in argon sputter-etching, which is performed as pre-treatment (cleaning) of the next metal deposition (FIG. 7).  
           [0014]    The first problem caused by the faceting is that sputtered dielectrics  98  are deposited on pattern bottom in case of argon sputter-etching, and this results in via-connection failure. The faceting prior to the sputter-etching increases the amount of the sputtered dielectrics, so increases the via-connection failure.  
           [0015]    The second problem caused by the faceting is that buried metals  14  in the pattern are not completely separated from each other, and this causes short-circuit failure (FIG. 8).  
         SUMMARY OF THE INVENTION  
         [0016]    It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant without causing via-connection failure and short circuit failure due to faceting even when lower level interconnects are covered with etching stopper.  
           [0017]    According to an aspect of the method for manufacturing a semiconductor device of the present invention, inter-level dielectrics for forming holes for vias or trenches for interconnects are fabricated as layered films of a methylsiloxane type film and a different insulating film formed on the film, and the layered films are processed using a hard mask. As a result, hole pattern or trench pattern is transferred to the hard mask using a resist, and the resist is then removed. In this case, deterioration of the quality of the methylsiloxane type film can be prevented because the methylsiloxane type film is covered with the insulating film.  
           [0018]    Also, when a hole or a trench is formed on the layered films, it is possible to prevent transfer of the faceting of the hard mask to the methylsiloxane type film because the insulating film is formed between the methylsiloxane type film and the hard mask. Thus, the first and the second problems as described above can be overcome. By setting the etching rate of the insulating film to ⅓ or less of that of the hard mask, the insulating film acts as a hard mask for the methylsiloxane type film, and the higher effects can be obtained. As an example of the material for the insulating film, it is effective to use silicon oxide film because it can suppress the increase of parasitic capacitance between the interconnects.  
           [0019]    Further, in case the dual damascene process in which holes for vias or trenches for interconnects are formed at the same time, layered films of methylsiloxane type film, a different insulating film and a hard mask are deposited on the similar layered films, and then the hole and the trench are formed at the same time. In this case, the insulating film prevents quality deterioration caused by removal of the resist on the methylsiloxane type film under the insulating film, and also the transfer of the faceting of the hard mask to the methylsiloxane type film can be prevented. In case of the dual damascene process in which trench pattern is transferred to the higher level hard mask and hole pattern is transferred to the lower level hard mask, the resist used for patterning of the lower level hard mask is removed by low-pressure oxygen plasma treatment, and quality deterioration of the methylsiloxane type film formed on the lower level hard mask can be suppressed.  
           [0020]    In case the etching stopper is formed on the lowermost layer of the inter-level dielectrics, the hard mask on the exposed portion is removed at the same time when the hole is formed on the etching stopper. As a result, it is possible to reduce parasitic capacitance between the multi-level interconnects.  
           [0021]    According to an aspect of a semiconductor device of the present invention, inter-level dielectrics with dual damascene interconnects formed on it are made as layered films comprising a first methylsiloxane type film, a first insulating film, a hard mask, a second methylsiloxane type film, and a second insulating film in this order from below, and the manufacturing method as described above can be applied. The decrease of production yield caused by via-connection failure or short-circuit failure of multi-level interconnects can be prevented, and a semiconductor integrated circuit device to be operated at high speed of several hundreds of MHz or more can be manufactured at lower cost.  
           [0022]    Other and further objects, features and advantages of the invention will appear more fully from the following description.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]    A preferred form of the present invention illustrated in the accompanying drawings in which:  
         [0024]    [0024]FIG. 1 is a schematical plan view of conventional type multi-level interconnects;  
         [0025]    [0025]FIG. 2 is a cross-sectional view showing a process for manufacturing conventional type multi-level interconnects;  
         [0026]    [0026]FIG. 3 is a cross-sectional view showing a process for manufacturing conventional type multi-level interconnects;  
         [0027]    [0027]FIG. 4 is a cross-sectional view showing a process for manufacturing conventional type multi-level interconnects;  
         [0028]    [0028]FIG. 5 is a cross-sectional view showing a manufacturing process to explain problems in the conventional example;  
         [0029]    [0029]FIG. 6 is a cross-sectional view showing a manufacturing process to explain problems in the conventional example;  
         [0030]    [0030]FIG. 7 is a cross-sectional view showing a manufacturing process to explain problems in the conventional example;  
         [0031]    [0031]FIG. 8 is a cross-sectional view showing a manufacturing process to explain problems in the conventional example;  
         [0032]    [0032]FIG. 9 is a cross-sectional view of a manufacturing process of a first embodiment of the present invention;  
         [0033]    [0033]FIG. 10 is a cross-sectional view of a manufacturing process of a first embodiment of the present invention;  
         [0034]    [0034]FIG. 11 is a cross-sectional view of a manufacturing process of a first embodiment of the present invention;  
         [0035]    [0035]FIG. 12 is a cross-sectional view of a manufacturing process of a first embodiment of the present invention;  
         [0036]    [0036]FIG. 13 is a cross-sectional view of a manufacturing process of a first embodiment of the present invention;  
         [0037]    [0037]FIG. 14 is a plan view showing a process for manufacturing the first embodiment of the present invention;  
         [0038]    [0038]FIG. 15 is a cross-sectional view of a process for manufacturing the first embodiment of the present invention;  
         [0039]    [0039]FIG. 16 is a cross-sectional view of a process for manufacturing the first embodiment of the present invention;  
         [0040]    [0040]FIG. 17 is a cross-sectional view of a process for manufacturing the first embodiment of the present invention;  
         [0041]    [0041]FIG. 18 is a plan view of a process for manufacturing the first embodiment of the present invention;  
         [0042]    [0042]FIG. 19 is a cross-sectional view of a process for manufacturing the first embodiment of the present invention;  
         [0043]    [0043]FIG. 20 is a plan view of a process for manufacturing the first embodiment of the present invention;  
         [0044]    [0044]FIG. 21 is a diagram showing relationship between sputter-etched thickness before deposition of vias and interconnects and via-connection yield of vias;  
         [0045]    [0045]FIG. 22 is a cross-sectional view of a process for manufacturing a second embodiment of the present invention;  
         [0046]    [0046]FIG. 23 is a cross-sectional view of a process for manufacturing the second embodiment of the present invention;  
         [0047]    [0047]FIG. 24 is a cross-sectional view of a process for manufacturing the second embodiment of the present invention;  
         [0048]    [0048]FIG. 25 is a cross-sectional view of a process for manufacturing the second embodiment of the present invention;  
         [0049]    [0049]FIG. 26 is a cross-sectional view of a process for manufacturing the second embodiment of the present invention;  
         [0050]    [0050]FIG. 27 is a cross-sectional view of a process for manufacturing the second embodiment of the present invention;  
         [0051]    [0051]FIG. 28 is a cross-sectional view of a process for manufacturing a third embodiment of the present invention;  
         [0052]    [0052]FIG. 29 is a cross-sectional view of a process for manufacturing the third embodiment of the present invention;  
         [0053]    [0053]FIG. 30 is a plan view of a process for manufacturing the third embodiment of the present invention;  
         [0054]    [0054]FIG. 31 is a cross-sectional view of a process for manufacturing the third embodiment of the present invention;  
         [0055]    [0055]FIG. 32 is a plan view of a process for manufacturing the third embodiment of the present invention;  
         [0056]    [0056]FIG. 33 is a cross-sectional view of a process for manufacturing the third embodiment of the present invention;  
         [0057]    [0057]FIG. 34 is a cross-sectional view of a process for manufacturing the third embodiment of the present invention;  
         [0058]    [0058]FIG. 35 is a cross-sectional view of a process for manufacturing the third embodiment of the present invention; and  
         [0059]    [0059]FIG. 36 is a cross-sectional view of a process for manufacturing the third embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
     Example 1  
       [0060]    [0060]FIG. 9 to FIG. 20 each represents a cross-sectional view or a plan view of a process for manufacturing a first embodiment of a semiconductor device of the present invention, in which single damascene process is applied for forming multi-level interconnects.  
         [0061]    As shown in FIG. 9, a first inter-level dielectric film  2  is formed on a silicon substrate  1  where a device component is fabricated. Then, a contact hole is opened, and titanium nitride is buried by CVD method. By chemical-mechanical polishing, the metal outside the hole is removed, and a contact plug  3  is formed. In the figure, a MOS transistor is shown as a device component.  
         [0062]    Next, as shown in FIG. 10, a second inter-layer dielectric  12  is formed, and a trench for a first level interconnect is fabricated. Sputter-etching is performed for the time as long as a 20-nm-thick blanket silicon oxide film is removed. Titanium nitride and copper are thinly formed by sputtering. Further, copper plating is performed to bury the trench with layered films of a barrier metal film  4   a  comprising titanium nitride and a copper film  4   b . Further, by chemical-mechanical polishing, titanium nitride and copper outside the trench were removed, and first-level interconnects  4   a  and  4   b  were formed. A plan view of the process in this stage is shown in FIG. 11. Here, FIG. 10 is a cross-sectional view along the line A-B in FIG. 11. The relationship between this cross-sectional view and the top view is the same in the description given below.  
         [0063]    Next, as shown in FIG. 12, a silicon nitride film was formed in thickness of 50 nm by plasma CVD method as an etching stopper  5  of the first level interconnect. Then, 300-nm-thick organic SOG film was coated as a methylsiloxane type film  6 , and this was cured in nitrogen ambient at 425° C. Further, by plasma CVD method, a silicon oxide film  7  was formed in thickness of 100 nm, and a silicon nitride film  8  was formed in thickness of 100 nm as a hard mask  8 .  
         [0064]    Next, as shown in FIG. 13, reactive ion etching was performed using a resist  9  as mask, and via pattern was transferred from the resist  9  to the hard mask  8 . In this etching process, it is necessary to stop the etching at the silicon oxide film  7  without exposing the lower level organic SOG film as shown in the plan view of FIG. 14. There is no need to stop the etching exactly at the upper surface of the silicon oxide film  7  as shown in FIG. 13, and there is no problem even when the silicon oxide film is etched to some extent.  
         [0065]    Then, as shown in FIG. 15, the resist  9  was removed by ICP type asher, and reactive ion etching was performed using the silicon nitride film  8  as hard mask, and etching was performed on the silicon oxide film  7  and the organic SOG film  6 . In this etching process, etching selectivity or selection ratio of the silicon oxide and the organic SOG film to the silicon nitride was 10. By this etching process, film thickness of the hard mask was turned to 60 nm.  
         [0066]    Next, as shown in FIG. 16, the space inside the hole was cleaned using wet solution, and the etching stopper  5  was removed by etching, and upper surface of the first level interconnects  4   a  and  4   b  were exposed. In this case, almost the entire hard mask on upper portion of the pattern disappeared. When the upper surfaces of the first level interconnects  4   a  and  4   b  were exposed, the hard mask  8  may remain. However, it is preferable to remove it in the etching process by over-etching in order to reduce parasitic capacitance between interconnects.  
         [0067]    Further, as shown in FIG. 17, sputter-etching was performed for the time as long as a 20-nm-thick blanket silicon oxide film is removed, and titanium nitride and copper were thinly formed by sputtering. Then, by copper plating, layered films of the barrier metal film  4   a  comprising titanium nitride and the copper film  4   b  was buried in the hole. Further, by chemical-mechanical polishing, titanium nitride and copper were removed, and vias  14   a  and  14   b  were formed. A plan view of the process in this stage is shown in FIG. 18.  
         [0068]    Then, as shown in FIG. 19, the procedure of FIG. 12 to FIG. 18 was repeated, and second level interconnects  24   a  and  24   b  were formed. Reference numeral  15  denotes a silicon nitride film as an etching stopper,  16  is an organic SOG film as methylsiloxane type film,  17  a silicon oxide film,  24   a  titanium nitride used as barrier metal film, and  24   b  a copper layer. A plan view of the process in this stage is shown in FIG. 20. This process is different from the process shown in FIG. 12 to FIG. 18 in that film thickness of the organic SOG film  16  is as thin as 200 nm and that hole pattern of vias is changed to trench pattern of the second level interconnects.  
         [0069]    In the semiconductor device of Example 1 as formed above, yield of the multilevel interconnects was evaluated. As a result, via connection yield of 0.25 μm diameter vias and insulation yield of 0.25 μm spacing interconnects were both 95% or more, and no decrease of yield due to faceting was observed.  
         [0070]    Further, the process from FIG. 12 to FIG. 20 of Example 1 was repeated, and 3-level interconnects were formed, and capacitance between adjacent wires of the second level interconnects was measured. Effective dielectric constant between the adjacent wires thus obtained was 3.3.  
         [0071]    In the above Example, silicon nitride film was used as hard mask, but this may contain Si—H bond in addition to the main component. Also, the film may replace silicon carbide film or may contain Si—H bond or Si—CH 3  bond in addition to the main component of silicon carbide film.  
         [0072]    In the above Example, the organic SOG film was used as methylsiloxane film, while Si—H bond or Si—C—Si bond may be contained in addition to the main components of Si—CH 3  bond and Si—O—Si bond. Also, the film may be formed by CVD method instead of coating method. Or, oligomer solution mixed with organic polymer may be coated in advance, and organic polymer may be decomposed and removed by curing, and low density organic SOG thus prepared may be used.  
         [0073]    The materials of the hard mask and methylsiloxane film are the same in the examples as described below.  
         [0074]    The effect of sputter-etching length is shown in FIG. 21. Here, the samples were the same as that shown above except for the length of sputter-etching. The sputter-etching length is represented by the sputter-etched thickness, which is the decrease in thickness when the sputter-etching for the same length is applied to a blanket silicon-oxide film.  
       Example 2  
       [0075]    [0075]FIG. 22 to FIG. 27 each represents a cross-sectional view or a plan view of a manufacturing process of a semiconductor device in Example 2 of the present invention where dual damascene process is applied for formation of multi-level interconnects. In this Example, the process from FIG. 9 to FIG. 14 is the same as in Example 1.  
         [0076]    After the process of FIG. 13, the resist  9  was removed as shown in FIG. 22. A second organic SOG film was coated as a methylsiloxane film  16  in thickness of 200 nm, and this was cured under nitrogen ambient at 425° C. Further, a second silicon oxide film  17  was formed in thickness of 100 nm by plasma CVD method, and a silicon nitride film was formed in thickness of 150 nm as a second hard mask  18 .  
         [0077]    Next, as shown in FIG. 23, reactive ion etching was performed using a second resist  19  as mask, and the second level interconnect pattern was transferred to the second hard mask  18 . In this etching process, it is necessary to stop the etching in the second silicon oxide film  17  without exposing lower level second organic SOG film  16  as shown in the plan view of FIG. 24. There is no need to stop the etching exactly on the upper surface of the second silicon oxide film  17  as shown in FIG. 23. The second silicon oxide film may be etched if the second organic SOG film  16  is not exposed.  
         [0078]    Next, as shown in FIG. 25, the resist  19  was removed by ICP type asher, and reactive ion etching was performed using the second silicon nitride film  18  and the first silicon nitride film  8  as hard masks, and etching was performed on the first silicon oxide film  7  and the second silicon oxide film  17  as well as the first organic SOG film  6  and the second organic SOG film  16 . In this etching process, etching selectivity of the silicon oxide and the organic SOG to silicon nitride was 10. By this etching process, film thickness of the exposed portion of each of the first hard mask  8  and the second hard mask  18  was turned to 60 nm. As a result, via holes were formed in the layered film of the first organic SOG film  6  and the first silicon oxide film  7 . Also, a trench for the second level interconnect was formed in the layered film of the second organic SOG film  16  and the second silicon oxide film  17 .  
         [0079]    Next, as shown in FIG. 26, the spaces in the hole and the trench were cleaned using wet solution, and etching was performed on the etching stopper  5 . In this case, exposed portions of the first hard mask  8  and the second hard mask  18  almost completely disappeared. The hard masks  8  and  18  on the exposed portions may remain after the etching stopper  5  on the upper surface of the first level interconnects  4   a  and  4   b  is completely removed. However, it is preferable to completely remove them by over-etching because parasitic capacitance between interconnects can be reduced.  
         [0080]    Further, as shown in FIG. 27, sputter-etching was performed for 20 nm as measured using blanket silicon oxide film, and titanium nitride and copper were thinly formed by sputtering. Then, by copper plating, layered films of a barrier metal film  34   a  comprising titanium nitride and a copper film  34   b  were buried in the hole and the trench. Further, by chemical-mechanical polishing, titanium nitride and copper outside the hole and the trench were removed. Consequently, vias  34   a  and  34   b , and interconnects  34   a  and  34   b  were fabricated in the layered films.  
         [0081]    On the multi-level interconnects of the Example 2 thus prepared, the yield was evaluated. As a result, via connection yield of 0.25 μm diameter vias and insulation yield of 0.25 μm spacing interconnects were both 95% or more, and no decrease of yield due to faceting was observed.  
         [0082]    Further, by repeating the process from FIG. 12 to FIG. 14 of Example 1 and the process from FIG. 22 to FIG. 27 of Example 2, 3-level interconnects were formed, and capacitance between adjacent interconnects of the second level interconnects was measured. Effective dielectric constant of the adjacent wires thus obtained was 3.6. The increase of effective dielectric constant compared with Example 1 is attributed to the fact that the silicon nitride film  8  for the first hard mask of 100 nm in thickness remains in the inter-level dielectrics.  
       Example 3  
       [0083]    [0083]FIG. 28 to FIG. 36 each represents a cross-sectional view or a plan view of a manufacturing process of a semiconductor device in Example 3 of the present invention where dual damascene process is applied for formation of multi-level interconnects. In this example, the processes from FIG. 9 to FIG. 12 are the same as in Example 1.  
         [0084]    After the process of FIG. 12, as shown in FIG. 28, a second organic SOG film  16  was coated in thickness of 200 nm as a methylsiloxane film  16 , and this was cured in nitrogen ambient at 425° C. Further, by plasma CVD method, a second silicon oxide film  17  was formed in thickness of 100 nm, and a silicon nitride film was formed in thickness of 100 nm as a second hard mask  18 .  
         [0085]    Next, as shown in FIG. 29, reactive ion etching was performed using a first resist  19  as mask, and the pattern of the second level interconnects was transferred to the second hard mask  18 . In this etching process, it is necessary to stop the etching in the second silicon oxide film  17  without exposing the second organic SOG film  16  as shown in the plan view of FIG. 30. There is no need to stop the etching exactly on the upper surface of the second silicon oxide film  17  as shown in FIG. 29. The second silicon oxide film  17  may be removed to some extent if the second organic SOG film  16  is not exposed.  
         [0086]    Next, as shown in FIG. 31, the first resist  19  was removed by ICP type asher, and the second resist  9  was formed and patterned using lithography. Then, via hole pattern was transferred to the second silicon oxide film  17  and the second organic SOG film  16 . In this etching process, it is necessary to etch the first hard mask completely. There is no need to stop the etching exactly on the upper surface of the first silicon oxide film  7  in FIG. 31, and the first silicon oxide film  7  and the first organic SOG film  6  may be etched to some extent.  
         [0087]    Next, as shown in FIG. 33, low-pressure reactive ion etching was performed using oxygen at the pressure of 10 mTorr, and the second resist  9  was removed. Under this condition, aspect ratio of the hole formed in the second organic SOG film  16  and the second silicon oxide film  17  was 3 or less in a hole pattern of 0.25 μm in diameter. By removing the second resist  9  at low pressure, the quality deterioration did not occur in the second organic SOG film  16 .  
         [0088]    Further, as shown in FIG. 34, reactive ion etching was performed using the second silicon nitride film  18  and the first silicon nitride film  8  as hard mask, and etching was performed on the first silicon oxide film  7  and the second silicon oxide film  17  as well as the first organic SOG film  6  and the second organic SOG film  16 . In this etching process, etching selectivity of the silicon oxide film and the organic SOG to silicon nitride was 10. By this etching process, film thickness of the exposed portions of the first hard mask  8  and the second hard mask  18  was turned to 60 nm. As a result, via-holes were formed in the layered films of the first organic SOG film  6  and the first silicon oxide film  7 . Also, trench was formed in the layered films of the second organic SOG film  16  and the second silicon oxide film  17 .  
         [0089]    Next, as shown in FIG. 35, the surface of the holes and the trenches were cleaned using wet solution, and etching was performed on the etching stopper  5 . In this case, exposed portions of the first hard mask  8  and the second hard mask  18  disappeared almost completely. If upper surfaces of the first level interconnects  4   a  and  4   b  are exposed, there is no problem even when the hard masks  8  and  18  of the exposed portions may remain. However, if it is completely removed, it is possible to reduce parasitic capacitance between the interconnects.  
         [0090]    Further, as shown in FIG. 36, sputter-etching was performed for the time as long as a 20-nm-thick blanket silicon oxide film is removed, and titanium nitride and copper were formed thinly by sputtering. Then, by copper plating, layered films of a barrier metal film  34   a  comprising titanium nitride and a copper film  34   b  were buried in the hole and the trench. Further, by chemical-mechanical polishing, titanium nitride outside the hole and the trench were removed. Consequently, vias  34   a  and  34   b , and interconnects  34   a  and  34   b  were fabricated in the layered films.  
         [0091]    On the multi-level interconnects of Example 3 thus prepared, the yield was evaluated. As a result, via connection yield of 0.25 μm diameter vias and insulation yield of 0.25 μm spacing interconnects were both 95% or more, and no decrease of yield due to faceting was observed.  
         [0092]    In the above examples, description has been given on the case where titanium nitride was used as barrier metal film, while the invention is not limited to these examples, and film of nitride of refractory metal such as tantalum nitride, tungsten nitride, etc. may be used.  
         [0093]    According to the present invention, it is possible to prevent via-connection failure and short failure in multi-level interconnects.  
         [0094]    The foregoing invention has been described in terms of preferred embodiments. However, those skilled, in the art will recognize that many variations of such embodiments exist. Such variations are intended to be within the scope of the present invention and the appended claims.