Abstract:
A semiconductor chip includes a plurality of pads; a plurality of interface circuits connected with the plurality of pads, respectively; an internal circuit connected with the plurality of interface circuits; and a transfer circuit connecting the plurality of interface circuits with each other in response to a test mode signal. One of the plurality of pads is a selected pad when the pad is probed, at least one remaining pad is a non-selected pad, one of the plurality of interface circuits corresponding to the selected pad is a selected interface circuit, and at least one remaining interface circuit is a non-selected interface circuit. The internal circuit is tested by using the selected pad, the selected interface circuit, the transfer circuit, and the non-selected interface circuit without using the non-selected pads.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor chip having a pad used for testing an internal circuit.  
         [0003]     2. Description of the Related Art  
         [0004]     In a process of manufacturing a semiconductor device, a large number of circuit elements are formed on a semiconductor wafer, and a plurality of semiconductor chips having internal circuits are cut out from the semiconductor wafer. The internal circuit includes a memory circuit, a fuse circuit and a CPU. The semiconductor chip is test by a tester having a probe card and a measuring circuit, to test the electric property of the internal circuit.  
         [0005]     As the result of the test, the semiconductor chip of good quality is shipped. In the semiconductor chip of the defective semiconductor chips which has a defect in a memory circuit, a redundancy process is carried out to replace a defective memory cell with a redundant memory cell by using a fuse circuit. Thus, the defective semiconductor chip is changed to a good quality semiconductor chip. Defective semiconductor chips are discarded.  
         [0006]     A semiconductor chip has a plurality of pads. When the semiconductor chip is tested, the pads on the semiconductor chip are probed with a probe card. In this case, the probed pads are not required to be all of the pads in the semiconductor chip. Preferably, the necessarily minimum number of the pads is desirable. For this reason, when the probed pad is defined as a probing pad P 0  and the non-probed pad is defined as a non-probing pad P 1 , the operation check of the internal circuit for the probing pad P 0  is carried out by probing the probing pad P 0 , and the operation check of the internal circuit for the non-probing pad P 1  is carried out by using a test mode and then probing the probing pad P 0 . This will be described with reference to  FIG. 1 .  
         [0007]      FIG. 1  shows the configuration of a semiconductor chip  101 . The semiconductor chip  101  contains an internal data bus  160 , a test interface circuit  140 , a non-test interface circuit  141 , selector circuits  150  and  151  and a test circuit  190  in addition to the probing pad P 0  and the non-probing pad P 1 . Also, an internal circuit  180  of the semiconductor chip  101  includes a memory circuit (not shown), a fuse circuit (not shown) and a CPU (Central Processing Unit) (not shown). The internal circuit is connected to the internal data bus  160 . The internal data bus  160  includes a test internal bus and a non-test internal bus. The test internal bus includes an internal input bus N 0  and an internal output bus N 0 ′, and the non-test internal bus includes an internal input bus N 1  and an internal output bus N 1 ′.  
         [0008]     The test interface circuit  140  contains an input circuit  110 , an input protection resistor  120  and an output circuit  130 . The input circuit  110  is connected to the input protection resistor  120  and the selector circuit  150 . The input protection resistor  120  is connected to the probing pad P 0 . The output circuit  130  is connected to the selector circuit  150 , the input protection resistor  120  and the probing pad P 0 . The non-test interface circuit  141  contains an input circuit  111 , an input protection resistor  121  and an output circuit  131 . The input circuit  111  is connected to the input protection resistor  121  and the selector circuit  151 . The input protection resistor  121  is connected to the non-probing pad P 1 . The output circuit  131  is connected to the selector circuit  151 , the input protection resistor  121  and the non-probing pad P 1 .  
         [0009]     A test apparatus  102  includes the probe card and measuring device, as described above. The probing pad P 0  is probed with the probe card. For example, the test apparatus  102  checks the memory circuit of the internal circuit  180  for a write operation and a read operation. Also, the test circuit  190  sends a test mode signal T 100  indicating a low level to the selector circuits  150  and  151 , when the test apparatus  102  carries out the operation check of the internal circuit for the probing pad P 0 . In this case, the selector circuit  150  connects the input circuit  110  and the internal input bus N 0  and connects the output circuit  130  and the internal output bus N 0 ′. The test circuit  190  sends the test mode signal T 100  indicating a high level to the selector circuits  150  and  151 , when the test apparatus  102  carries out the operation check of the internal circuit for the non-probing pad P 1 . In this case, the selector circuit  151  connects the input circuit  110  and the internal input bus N 1  through the selector circuit  150  and connects the output circuit  130  and the internal output bus N 1 ′ through the selector circuit  150 . The test apparatus  102  outputs a probe signal such as a clock signal, to check the operation of the internal circuit. At this time, the test apparatus  102  checks the operation of the internal circuit for (A) the probing pad P 0  and checks the operation of the internal circuit for (B) the non-probing pad P 1 . This will be described by using  FIG. 1 .  
         [0010]     The operation check in the (A) case will be described below.  
         [0011]     The test apparatus  102 , when checking the operation of the internal circuit for the probing pad P 0 , sends a first probe signal to the probing pad P 0 . For example, the first probe signal indicates the high level in a first period and indicates the low level in a next period. The first probe signal of the high level includes a write command and a write data as a test data, and the first probe signal of the low level includes a read command.  
         [0012]     Also, the test circuit  190  sends the test mode signal T 100  of the low level to the selector circuits  150  and  151 . Since the test mode signal T 100  indicates the low level, the selector circuit  150  connects the input circuit  110  and the internal input bus N 0  and connects the output circuit  130  and the internal output bus N 0 ′.  
         [0013]     At first, the test apparatus  102  sends the write command including an address to the probing pad P 0 . The input circuit  110  of the test interface circuit  140  receives the write command sent to the probing pad P 0  through the input protection resistor  120  and outputs the write command through the selector circuit  150 , the internal input bus N 0  and the internal data bus  160  to the memory circuit of the internal circuit  180 .  
         [0014]     Next, the test apparatus  102  sends the write data to the probing pad P 0 . The input circuit  110  of the test interface circuit  140  receives the write data sent to the probing pad P 0  through the input protection resistor  120  and outputs the write data through the selector circuit  150 , the internal input bus N 0  and the internal data bus  160  to the memory circuit of the internal circuit  180 . The write data is written to the memory cell corresponding to the address included in the write command, among the plurality of memory cells of the memory circuit in the internal circuit  180 .  
         [0015]     Next, the test apparatus  102  sends the read command including the address to the probing pad P 0 . The input circuit  110  of the test interface circuit  140  receives the read command sent to the probing pad P 0  through the input protection resistor  120  and outputs the read command through the selector circuit  150 , the internal input bus N 0  and the internal data bus  160  to the memory circuit in the internal circuit  180 . At this time, the stored data is read out from the memory cell corresponding to the address included in the read command among the plurality of memory cells of the memory circuit in the internal circuit  180 . The read data is sent from the internal circuit  180  through the internal data bus  160 , the internal output bus N 0 ′ and the selector circuit  150  to the test interface circuit  140 . The output circuit  130  of the test interface circuit  140  outputs the read data through the probing pad P 0  to the test apparatus  102 .  
         [0016]     Consequently, the test apparatus  102  compares the write data and the read data as the test result in the first probe signal, and if they are coincident with each other, generates the test result indicating the good quality, and if they are not coincident with each other, generates the test result indicating the bad quality. In this way, according to the conventional semiconductor chip, the test apparatus  102  can check the operation of the internal circuit for the probing pad P 0 .  
         [0017]     The operation check in the (B) case will be described below.  
         [0018]     The test apparatus  102 , when checking the operation of the internal circuit for the non-probing pad P 1 , sends a second probe signal to the probing pad P 0 . For example, the second probe signal indicates the high level in the first period and indicates the low level in the next period. The second probe signal of the high level includes the write command and the write data, and the second probe signal of the low level includes the read command. Also, the test circuit  190  sends a test mode signal T 100  of the high level to the selector circuits  150  and  151 . Since the test mode signal T 100  indicates the high level, the selector circuit  151  connects the input circuit  110  and the internal input bus N 1  and connects the output circuit  130  and the internal output bus N 1 ′ through the selector circuit  150 .  
         [0019]     At first, the test apparatus  102  sends the write command including the address to the probing pad P 0 . The input circuit  110  of the test interface circuit  140  receives the write command sent to the probing pad P 0  through the input protection resistor  120  and outputs the write command through the selector circuits  150  and  151 , the internal input bus N 1  and the internal data bus  160  to the memory circuit of the internal circuit  180 .  
         [0020]     Next, the test apparatus  102  sends the write data to the probing pad P 0 , The input circuit  110  of the test interface circuit  140  receives the write data sent to the probing pad P 0  through the input protection resistor  120  and outputs the write data through the selector circuits  150  and  151 , the internal input bus N 1  and the internal data bus  160  to the memory circuit of the internal circuit  180 . The write data is written to the memory cell corresponding to the address included in the write command among the plurality of memory cells of the memory circuit in the internal circuit  180 .  
         [0021]     Next, the test apparatus  102  sends the read command including the address to the probing pad P 0 . The input circuit  110  of the test interface circuit  140  receives the read command sent to the probing pad P 0  through the input protection resistor  120  and outputs the read command through the selector circuits  150  and  151 , the internal input bus N 1  and the internal data bus  160  to the memory circuit in the internal circuit  180 . At this time, the read data is read from the memory cell corresponding to the address included in the read command among the plurality of memory cells of the memory circuit in the internal circuit  180 . The read data is sent from the memory circuit in the internal circuit  180  through the internal data bus  160 , the internal output bus N 1 ′ and the selector circuits  151 ,  150  to the test interface circuit  140 . The output circuit  130  of the test interface circuit  140  outputs the read data through the probing pad P 0  to the test apparatus  102 .  
         [0022]     Consequently, the test apparatus  102  compares the write data and the read data as the test result in the second probe signal, and if they are coincident with each other, generates the test result indicating the good quality, and if they are not coincident with each other, generates the test result indicating the bad quality. In this way, according to the conventional semiconductor chip, the test apparatus  102  can check the operation of the internal circuit for the non-probing pad P 1 .  
         [0023]     However, in the conventional semiconductor chip, although the defect in the test interface circuit  140  can be tested, it is impossible to test a defect in the non-test interface circuit  141 . When the test apparatus  102  checks the operation of the internal circuit corresponding to the probing pad P 0 , if the write data and the read data are coincident with each other, this indicates that the test interface circuit  140  is normal. Thus, it is possible to test the defect in the test interface circuit  140 . On the other hand, when the test apparatus  102  checks the operation of the internal circuit for the non-probing pad P 1 , even if the write data and the read data are coincident with each other, this does not indicate whether or not the non-test interface circuit  141  is normal. Therefore, it is impossible to test the defect in the non-test interface circuit  141 .  
         [0024]     In conjunction with the above description, semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-P2000-124278A) in which a scribe line having no influence on a chip size is used to improve an integration rate, a small number of pins are used to efficiently test a wafer, and the test time of the wafer is reduced. This semiconductor device is intended to collectively test a plurality of semiconductor chips formed on the semiconductor wafer. A cut region of the semiconductor chip contains a wafer test pad for making the test pins of adjacent semiconductor chips in contact with each other and probing them, a controller for determining whether or not the semiconductor chip connected to the wafer test pad is normal; and a control pad for inputting a control signal to control the controller. The controller carries out a comparison test of an expectation value, for the respective semiconductor chips connected adjacently to the wafer test pad, in accordance with the control signal inputted to the control pad, and judges whether or not the semiconductor chip is normal, in accordance with whether the expectation value is matched or unmatched.  
         [0025]     Also, Japanese Laid Open Patent Application (JP-P2004-85526A) describes a semiconductor device, which is used for a system-in-package and attains an output buffer circuit that can drive an output pad with an optimally driving power, in a usual operation mode and a test operation mode. This semiconductor device has first and second output buffers coupled to the output pad. The first output buffer is activated in the usual operation mode, and set to an output high impedance state in the test operation mode, and drives the output pad with a first driving power in accordance with an inner signal on the activation. The second output buffer is activated in the test operation mode, and set to the output high impedance state in the usual operation mode, and drives the output pad with a second driving power greater than the first driving power in accordance with the inner signal at the time of the activation.  
         [0026]     Also, Japanese Laid Open Patent Application (JP-P2001-210685A) describes a testing system which can test a semiconductor chip in a short time without using any expensive tester. The testing system carries out an electric test of the semiconductor chip formed on a semiconductor wafer. This is provided with a probe card, a test circuit and a controller. On the probe card, a conductive needle is placed correspondingly to the arrangement of electrode pads in the semiconductor chip, and it is connected to the test circuit. The test circuit is provided in the probe card and tests the semiconductor chip on the basis of a program. The controller rewrites the program in the test circuit and stores the test result outputted from the test circuit.  
       SUMMARY OF THE INVENTION  
       [0027]     In an aspect of the present invention, a semiconductor chip includes a plurality of pads; a plurality of interface circuits connected with the plurality of pads, respectively; an internal circuit connected with the plurality of interface circuits; and a transfer circuit connecting the plurality of interface circuits with each other in response to a test mode signal. One of the plurality of pads is a selected pad when the pad is probed, at least one remaining pad is a non-selected pad, one of the plurality of interface circuits corresponding to the selected pad is a selected interface circuit, and at least one remaining interface circuit is a non-selected interface circuit. The internal circuit is tested by using the selected pad, the selected interface circuit, the transfer circuit, and the non-selected interface circuit without using the non-selected pads.  
         [0028]     A portion of the internal circuit associated with the selected pad is tested by using the selected pad and the selected interface circuit, and a portion of the internal circuit associated with the non-selected pad is tested by using the selected pad, the selected interface circuit, the transfer circuit, and the non-selected interface circuit corresponding to the non-selected pad.  
         [0029]     Also, each of the plurality of interface circuits may-include an output circuit connected with a corresponding one of the plurality of pads and the internal circuit; a protection circuit connected with the corresponding pad and the output circuit; and an input circuit connected with the protection circuit and the internal circuit. The transfer circuit may be connected with a node between the protection circuit and the input circuit in each of the plurality of interface circuits.  
         [0030]     In this case, a test data may be supplied to the selected pad and transferred to the internal circuit through the protection circuit and the input circuit in the selected interface circuit, and a response data corresponding to the test data from the internal circuit may be transferred to the selected pad through the output circuit in the selected interface circuit.  
         [0031]     In addition, the test data may be transferred from the selected pad to the internal circuit through the protection circuit in the selected interface circuit, the transfer circuit, and the input circuit in the non-selected interface circuit, and the response data may be transferred from the internal circuit to the selected pad through the output circuit, and the protection circuit in the non-selected interface circuit, the transfer circuit, and the protection circuit in the selected interface circuit.  
         [0032]     Also, the transfer circuit may include a specific node; and a MOS transistor provided for each of the plurality of interface circuits to connect the specific node and the node between the protection circuit and the input circuit in the interface circuit. The test mode signal may be supplied to the transfer circuit such that the MOS transistor provided for the selected interface circuit is turned off when a portion of the internal circuit associated with the selected interface circuit is tested, and the MOS transistors provided for the selected interface circuit and the non-selected interface circuit are turned on when a portion of the internal circuit associated with the non-selected interface circuit is tested.  
         [0033]     Also, the semiconductor chip may further include a latch circuit provided between each of the plurality of interface circuits and the internal circuit to latch the test data and the response data corresponding to the test data.  
         [0034]     In another aspect of the present invention, a method of testing a semiconductor chip, is achieved by providing a semiconductor chip which comprises: a plurality of pads, a plurality of interface circuits connected with the plurality of pads, respectively, an internal circuit connected with the plurality of interface circuits, and a transfer circuit selectively connecting the plurality of interface circuits with each other, wherein one of the plurality of pads is a selected pad when the pad is probed, at least one remaining pad is a non-selected pad, one of the plurality of interface circuits corresponding to the selected pad is a selected interface circuit, and at least one remaining interface circuit is a non-selected interface circuit; and by testing the internal circuit by using the selected pad, the selected interface circuit, the transfer circuit, and the non-selected interface circuit without using the non-selected pads.  
         [0035]     Here, the testing may be achieved by supplying a test data to the selected pad; by testing a portion of the internal circuit associated with the selected interface circuit with the test data through the selected pad and the selected interface circuit; and by testing a portion of the internal circuit associated with the non-selected interface circuit with the test data through the selected pad, the selected interface circuit, the transfer circuit, and the non-selected interface circuit corresponding to the non-selected pad.  
         [0036]     Also, the testing a portion of the internal circuit associated with the selected interface circuit may be achieved by sending a test data from the selected pad to the internal circuit through a protection circuit and an input circuit in the selected interface circuit; by receiving a response data corresponding to the test data transferred from the internal circuit to the selected pad through an output circuit in the selected interface circuit; and by comparing the test data and the response data.  
         [0037]     Also, the testing a portion of the internal circuit associated with the non-selected interface circuit may be achieved by sending from the selected pad to the internal circuit through the protection circuit in the selected interface circuit, the transfer circuit, and the input circuit in the non-selected interface circuit; by receiving the response data transferred from the internal circuit to the selected pad through an output circuit, and a protection circuit in the non-selected interface circuit, the transfer circuit, and the protection circuit in the selected interface circuit; and by comparing the test data and the response data.  
         [0038]     Also, the transfer circuit may include a specific node; and a MOS transistor provided for each of the plurality of interface circuits to connect the specific node and the interface circuit. The testing a portion of the internal circuit associated with the selected pad may be achieved by turning off the MOS transistor provided for the selected interface circuit to disconnect the selected interface circuit from the non-selected interface circuit when the portion of the internal circuit associated with the selected interface circuit is tested. The testing a portion of the internal circuit associated with the non-selected pad may be achieved by turning of the MOS transistors provided for the selected interface circuit and the non-selected interface circuit to connect the non-selected interface circuit with the selected interface circuit when the portion of the internal circuit associated with the non-selected interface circuit is tested.  
         [0039]     The method may be achieved by further latching the test data outputted from the input circuit in the selected interface circuit to supply the test data to the portion of the internal circuit associated with the selected interface circuit; and by latching the response data corresponding to the test data from the interface circuit.  
         [0040]     The method may be achieved by further latching the test data outputted from the input circuit in the non-selected interface circuit to supply the test data to the portion of the internal circuit associated with the non-selected interface circuit; and by latching the response data corresponding to the test data from the interface circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0041]      FIG. 1  shows a configuration of a conventional semiconductor chip;  
         [0042]      FIG. 2  is a diagram showing a plurality of semiconductor chips formed on a semiconductor wafer according to a first embodiment of the present invention;  
         [0043]      FIG. 3  shows the configuration of the semiconductor chip according to the first embodiment of the present invention;  
         [0044]      FIGS. 4A  to  4 D are timing charts showing the operation of the semiconductor chip according to the first embodiment of the present invention;  
         [0045]      FIG. 5  shows the configuration of the semiconductor chip according to a second embodiment of the present invention;  
         [0046]      FIGS. 6A  to  6 G are timing charts showing the operation of the semiconductor chip according to the second embodiment of the present invention;  
         [0047]      FIG. 7  shows the configuration of the semiconductor chip according to s third embodiment of the present invention; and  
         [0048]      FIGS. 8A  to  8 E are timing charts showing the operation of the semiconductor chip according to the third embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0049]     Hereinafter, a semiconductor chip of the present invention will be described in detail with reference to the attached drawings.  
       First Embodiment  
       [0050]      FIG. 2  is a diagram showing a plurality of semiconductor chips formed on a semiconductor wafer according to the first embodiment of the present invention. The semiconductor chip according to the first embodiment is quadrangular and has a plurality of pads. The plurality of pads are grouped into a first pad group, a second pad group, a third pad group and a fourth pad group. The first pad group is provided on a side X 1  on the semiconductor chip. The second pad group is provided on a side X 2  opposite to the side X 1  on the semiconductor chip. The third pad group is provided on a side Y 1  orthogonal to the sides X 1  and X 2 . The fourth pad group is provided on a side Y 2  opposite to the side Y 1 .  
         [0051]     When the semiconductor chip is tested, the pads on the semiconductor chip are probed with a probe card. In this case, all of the pads on the semiconductor chip are not necessarily tested. Preferably, the necessarily minimum number of the pads is tested. Also, in order to test the large number of the semiconductor chips at the same time, probing all of the pads on the four sides on the semiconductor chip is difficult because of the performances of tools. Thus, only the pads existing on two of the four sides on the semiconductor chip are probed. For this reason, when the probed pads are defined as probing pads P 0  and the pads that are not probed is defined as non-probing pads P 1 , the probing pads P 0  indicate the pads of the first and second pad groups, and the non-probing pads P 1  indicate the pads of the third and fourth pad groups. In this case, the operation check of a portion of the internal circuit for the probing pad P 0  is carried out by probing the probing pads P 0 , and the operation check of a portion of the internal circuit for the non-probing pad P 1  is carried out by using a test mode and probing the probing pads P 0 . This will be described below with reference to  FIG. 3 .  
         [0052]      FIG. 3  shows the configuration of the semiconductor chip  1  according to the first embodiment of the present invention. The semiconductor chip  1  contains an internal circuit  80 , an internal data bus  60 , a test output circuit  40 , a non-test interface circuit  41 , a transferring circuit  50  and a test circuit  90 . The internal circuit  80  of the semiconductor chip  1  includes a memory circuit (not shown), a fuse circuit (not shown) and a CPU (Central Processing Unit) (not shown). The semiconductor chip  1  is tested by a test apparatus  2 . The testing system is composed of this semiconductor chip  1  and the test apparatus  2 .  
         [0053]     The internal circuit  80  is connected to the internal data bus  60 . The internal data bus  60  includes a test internal bus and a non-test internal bus. The test internal bus includes an internal input bus N 0  and an internal output bus N 0 ′, and the non-test internal bus includes an internal input bus N 1  and an internal output bus N 1 ′. The test interface circuit  40  contains an input circuit  10 , an input protection circuit  20  and an output circuit  30 . The input circuit  10  is connected to the input protection circuit  20  and the internal input bus N 0 . The input protection circuit  20  is connected to the probing pad P 0 . The output circuit  30  is connected to the internal output bus N 0 ′, the input protection circuit  20  and the probing pad P 0 . The non-test interface circuit  41  contains an input circuit  11 , an input protection circuit  21  and an output circuit  31 . The input circuit  11  is connected to the input protection circuit  21  and the internal input bus N 1 . The input protection circuit  21  is connected to the non-probing pad P 1 . The output circuit  31  is connected to the internal output bus N 1 ′, the input protection circuit  21  and the non-probing pad P 1 .  
         [0054]     The transferring circuit  50  is provided between the test interface circuit  40  and the non-test interface circuit  41 . This transferring circuit  50  has transistors Tr 0  and Tr 1 , which are MOS transistors, and capacitors C, C 0  and C 1 . A test mode signal T 0  is supplied from the test circuit  90  to gates of the transistors Tr 0  and Tr 1  to control their active or inactive states. One terminal of the transistor Tr 0  is connected to a node between the input circuit  10  and the input protection circuit  20 . One terminal of the transistor Tr 0  is connected to a node between the input circuit  10  and the input protection circuit  20 , and the other terminal of the transistor Tr 0  is connected to a node N. One terminal of the transistor Tr 1  is connected to the node N and the other terminal of the transistor Tr 1  is connected to a node between the input circuit  11  and the input protection circuit  20 . The capacitor C 0  is connected between the one terminal of the transistor Tr 0  and the ground, the capacitor C is connected between the node N and the ground, and the capacitor C 1  is connected between the other terminal of the transistor Tr 1  and the ground.  
         [0055]     The test apparatus  2  includes a probe card and a measuring device; which are not shown, and controls the test circuit  90 . For example, the test apparatus  2  controls the test circuit  90  by sending control data or instructions to the test circuit  90  in advance or when the probe card is pushed against the pads. The probing pad P 0  is probed with the probe card. For example, the test apparatus  2  checks the memory circuit of the internal circuit  80  for the operation check in a write operation and a read operation.  
         [0056]     When the transistors Tr 0  and Tr 1  are N-channel MOS transistors, the test circuit  90  supplies the test mode signal T 0  of a low level to the gates of the transistors Tr 0  and Tr 1  in the operation check of a portion of the internal circuit  80  for the probing pad P 0 . In this case, the transistors Tr 0  and Tr 1  are turned off, and the transferring circuit  50  does not connect the test interface circuit  40  and the non-test interface circuit  41 . The test circuit  90  supplies the test mode signal T 0  of a high level to the gates of the transistors Tr 0  and Tr 1 , in the operation check of a portion of the internal circuit for the non-probing pad P 1 . In this case, the transistors Tr 0  and Tr 1  are turned on, and the transferring circuit  50  connects the test interface circuit  40  and the non-test interface circuit  41 .  
         [0057]     Also, the test apparatus  2  outputs control signals for controlling input/output of the test interface circuits  40  and  41 . When the memory circuit of the internal circuit  80  is DRAM (Dynamic Random Access Memory), DQM 0  and DQM 1  for controlling typical input/output of the DRAM are exemplified as the control signal. When the control signal DQM 0  is outputted to the test interface circuit  40 , the test apparatus  2  outputs the control signal DQM 1  to the non-test interface circuit  41 . The control signal is not limited to the DQM, and if the control signal can individually control the input/output, any control signal can be used.  
         [0058]     The test apparatus  2  outputs a probe signal such as a clock signal, to check the operation of the internal circuit  80 . At this time, the test apparatus  2  checks the operation of the portion of the internal circuit  80  for (A) the probing pad P 0 , and checks the operation of the portion of the internal circuit for (B) the non-probing pad P 1 . This will be described below with reference to  FIGS. 3 and 4 A to  4 D.  FIGS. 4A  to  4 D are timing charts when data is sent from the test apparatus  2  to the probing pad P 0 .  
         [0059]     The operation check in the (A) case will be described below. When checking the operation of the portion of the internal circuit  80  for the probing pad P 0 , the test apparatus  2  sends the test probe signal corresponding to the control signal DQM 0  to the probing pad P 0  between timings a-c, c-e, . . . . Between the timings a-c, the test probe signal indicates a high level in a first period between the timings a-b and indicates a low level in a second period between the timings b-c. When of the high level, the test probe signal includes a write command and a write data as a test data DQ, and when of the low level, the test probe signal includes a read command. Also, the test circuit  90  supplies the test mode signal T 0  of the low level to the gates of the transistors Tr 0  and Tr 1  between the timings a-c in response to an external command or a command from the test apparatus  2 . Since the test mode signal T 0  indicates the low level, the transistors Tr 0  and Tr 1  are not turned on.  
         [0060]     At first, between the timings a-b, the test apparatus  2  sends the write command including an address to the probing pad P 0 . The input circuit  10  of the test interface circuit  40  receives the write command sent to the probing pad P 0  through the input protection circuit  20  in response to the control signal DQM 0 , and outputs the write command to the memory circuit in the internal circuit  80  through the internal input bus N 0  and the internal data bus  60 .  
         [0061]     Next, between the timings a-b, the test apparatus  2  sends the write data as the test data DQ to the probing pad P 0 . The input circuit  10  of the test interface circuit  40  receives the write data sent to the probing pad P 0  through the input protection circuit  20  in response to the control signal DQM 0 , and outputs the write data to the memory circuit in the internal circuit  80  through the internal input bus N 0  and the internal data bus  60 . The write data is written to the memory cell corresponding to the address included in the write command, among the plurality of memory cells of the memory circuit in the internal circuit  80 .  
         [0062]     Next, between the timings b-c, the test apparatus  2  sends the read command including the address to the probing pad P 0 . The input circuit  10  of the test interface circuit  40  receives the read command through the probing pad P 0  and the input protection circuit  20  in response to the control signal DQM 0 , and outputs the read command to the memory circuit in the internal circuit  80  through the internal input bus N 0  and the internal data bus  60 . At this time, as a test response data to the test data DQ, the stored data is read out from the memory cell corresponding to the address included in the read command, among the plurality of memory cells of the memory circuit in the internal circuit  80 . The read data is sent from the memory circuit in the internal circuit  80  to the test interface circuit  40  through the internal data bus  60  and the internal output bus N 0 ′. The output circuit  30  of the test interface circuit  40  outputs the read data to the test apparatus  2  through the probing pad P 0  in response to the control signal DQM 0 .  
         [0063]     Consequently, the test apparatus  2  compares the write data serving as the test data DQ and the read data serving as the test response data, for the test between the timings a-c. If they are coincident with each other, the test apparatus  2  generates the test result of the good result. On the other hand, if they are not coincident with each other, the test apparatus  2  generates a test result of a bad result. The test interface circuit  40  outputs the write data sent to the probing pad P 0  from the test apparatus  2 , through the internal input bus N 0  and the internal data bus  60  to the memory circuit in the internal circuit  80 , and outputs the read data sent through the internal data bus  60  and the internal output bus N 0 ′ from the memory circuit in the internal circuit  80 , through the probing pad P 0  to the test apparatus  2 . Thus, when the write data and the read data are coincident with each other, it is indicated that the test interface circuit  40  is normal. In this way, according to the semiconductor chip based on the first embodiment of the present invention, the test apparatus  2  can check the operation of the portion of the internal circuit  80  for the probing pad P 0  and can inspect the defect in the test interface circuit  40 .  
         [0064]     The operation check in the (B) case will be described below. When checking the operation of the portion of the internal circuit for the non-probing pad P 1 , the test apparatus  2  sends a non-test probe signal corresponding to the control signal DQML to the probing-pad P 0  between the timings c-e. Between the timings c-e, the non-test probe signal indicates the high level in the first period between the timings c-d, and indicates the low level in the second period between the timings d-e. The non-test probe signal of the high level includes the write command and the write data as the test data DQ (referred to as a non-test data DQ) for the non-probing pad P 1 . The non-test probe signal of the low level includes the read command.  
         [0065]     Also, the test circuit  90  sends the test mode signal T 0  of the high level to the gates of the transistors Tr 0  and Tr 1  between the timings c-e in accordance with the command from the outside or test apparatus  2 . Since the test mode signal T 0  indicates the high level, the transistors Tr 0  and Tr 1  are turned on.  
         [0066]     At first, between the timings c-d, the test apparatus  2  sends the write command including the address to the probing pad P 0 . The input circuit  11  of the non-test interface circuit  41  receives the write command through the probing pad P 0  and the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50  in response to the control signal DQM 1 , and outputs the write command to the memory circuit in the internal circuit  80  through the internal input bus N 1  and the internal data bus  60 .  
         [0067]     Next, between the timings c-d, the test apparatus  2  sends the write data as the non-test data DQ to the probing pad P 0 . The input circuit  11  of the non-test interface circuit  41  receives the write data through the probing pad P 0 , the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50  in response to the control signal DQM 1 , and outputs the write data to the memory circuit in the internal circuit  80  through the internal input bus N 1  and the internal data bus  60 . The write data is written to the memory cell corresponding to the address included in the write command, among the plurality of memory cells of the memory circuit in the internal circuit  80 .  
         [0068]     Next, between the timings d-e, the test apparatus  2  sends the read command including the address to the probing pad P 0 . The input circuit  11  of the non-test interface circuit  41  receives the read command through the probing pad P 0 , the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50  in response to the control signal DQM 1 , and outputs the read command to the memory circuit in the internal circuit  80  through the internal input bus N 1  and the internal data bus  60 . At this time, as the non-test response data to the non-test data DQ, the stored data is read out from the memory cell corresponding to the address included in the read command, among the plurality of memory cells of the memory circuit in the internal circuit  80 . The read data is sent from the memory circuit in the internal circuit  80  to the non-test interface circuit  41  through the internal data bus  60  and the internal output bus N 1 ′. The output circuit  31  of the non-test interface circuit  41  outputs the read data to the test apparatus  2  through the input protection circuit  21 , the transferring circuit  50 , the input protection circuit  20  of the test interface circuit  40  and the probing pad P 0  in response to the control signal DQM 1 .  
         [0069]     Consequently, the test apparatus  2  compares the write data serving as the non-test data DQ and the read data serving as the non-test response data, for the test between the timings c-e. If they are coincident with each other, the test apparatus  2  generates a test result indicating the good chip, and if they are not coincident with each other, the test apparatus  2  generates the test result indicating the bad chip. Also, the non-test interface circuit  41  outputs the write data sent from the test apparatus  2  to the probing pad P 0  through the internal input bus N 1  and the internal data bus  60  to the memory circuit in the internal circuit  80 , and outputs the read data sent from the memory circuit in the internal circuit  80  through the internal data bus  60  and the internal output bus N 1 ′ through the transferring circuit  50 , the test interface circuit  40  and the probing pad P 0  to the test apparatus  2 . Thus, if the write data and the read data are coincident with each other, it is indicated that the non-test interface circuit  41  is normal. In this way, in the semiconductor chip according to the first embodiment of the present invention, the test apparatus  2  can check the operation of the portion of the internal circuit for the non-probing pad P 1  and can inspect the defect in the non-test interface circuit  41 .  
         [0070]     From the above-mentioned description, in the semiconductor chip according to the first embodiment of the present invention, when the test apparatus  2  checks the operation of the portion of the internal circuit for the probing pad P 0 , if the write data and the read data are coincident with each other, the test apparatus  2  represents that the test interface circuit  40  is normal. Thus, the test apparatus  2  can check the operation of the portion of the internal circuit  80  for the probing pad P 0  and can inspect the defect in the test interface circuit  40  connected to the probing pad P 0 .  
         [0071]     Also, according to the semiconductor chip based on the first embodiment of the present invention, when the test apparatus  2  checks the operation of the portion of the internal circuit for the non-probing pad P 1 , if the write data and the read data are coincident with each other, this represents that the non-test interface circuit  41  is normal. Thus, the test apparatus  2  can checks the operation of the portion of the internal circuit for the non-probing pad P 1  and can inspect the defect in the non-test interface circuit  41  connected to the non-probing pad P 1 .  
         [0072]     Thus, in the semiconductor chip accordance to the first embodiment of the present invention, the test apparatus  2  can check the operation of the portion of the internal circuit for each of the plurality of pads and can inspect the defect in the interface circuit connected to each pad.  
       Second Embodiment  
       [0073]     The first embodiment was described under the two systems for the test data DQ and the non-test data DQ. However, in the second embodiment, there are M non-test data DQ (M is an integer of  1  or more), and one probing pad P 0  is used to control the (M+1) systems composed of the test data DQ and the M non-test data DQ. The second embodiment will be described with regard to a case where M is 2, namely, the case of the 3 systems will be described. Here, the description overlapping with that of the first embodiment is omitted.  
         [0074]      FIG. 5  shows the configuration of the semiconductor chip  1  according to the second embodiment of the present invention. The foregoing non-probing pad includes the non-probing pad P 1  serving as a first non-probing pad and a non-probing pad P 2  serving as a second non-probing pad. The foregoing non-test internal bus includes a first non-test internal bus and a second non-test internal bus. The first non-test internal bus includes an internal input bus N 1  and an internal output bus N 1 ′, and the second non-test internal bus includes an internal input bus N 2  and internal output bus N 2 ′ The foregoing non-test interface circuit includes a first non-test interface circuit  41  and a non-test interface circuit  42 . In this case, the non-test interface circuit  42  has an input circuit  12 , an input protection circuit  22  and an output circuit  32 . The input circuit  12  is connected to the input protection circuit  22  and the internal input bus N 2 . The input protection circuit  22  is connected to the non-probing pad P 2 . The output circuit  32  is connected to the internal output bus N 2 ′, the input protection circuit  22  and the non-probing pad P 2 .  
         [0075]     The transferring circuit  50  is provided between the test interface circuit  40  and each of the non-test interface circuits  41  and  42 . The transferring circuit  50  has a transistor Tr 2 , which is a MOS transistor, and a capacitor C 2 . Test mode signals T 0 , T 1  and T 2  are supplied from the test circuit  90  to the gates of the transistors Tr 0 , Tr 1  and Tr 2  to indicate their active or inactive states. One terminal of the transistor Tr 2  is connected to the node N and the other terminal of the transistor Tr 2  is connected to a node between the input circuit  12  and the input protection circuit  22 . The capacitor C 2  is connected between the node and ground.  
         [0076]     The foregoing non-test probe signal includes a first non-test probe signal and a second non-test probe signal. The first and second non-test probe signals will be described later. If the transistors Tr 0 , Tr 1  and Tr 2  are the N-channel M 0 S transistors, the test circuit  90  sends the test mode signals T 0 , T 1  and T 2  of to the low level the gates of the transistors Tr 0  and Tr 1  and Tr 2  when the test apparatus  2  carries out the operation check of the portion of the internal circuit for the probing pad P 0 . In this case, the transistors Tr 0 , Tr 1  and Tr 2  are turned off, and the transferring circuit  50  does not connect the test interface circuit  40  and the non-test interface circuits  41  and  42 . The test circuit  90  sends the test mode signals T 0 , T 1  of the high level as a first test mode signal to the gates of the transistors Tr 0  and Tr 1 , when the test apparatus  2  carries out the operation check of the portion of the internal circuit for the non-probing pad P 1 . In this case, the transistors Tr 0  and Tr 1  are turned on, and the transferring circuit  50  connects the test interface circuit  40  and the non-test interface circuit  41 . The test circuit  90  sends the test mode signals T 0  and T 2  of the high level as a second test mode signal to the gates of the transistors Tr 0  and Tr 2 , when the test apparatus  2  carries out the operation check of the portion of the internal circuit for the non-probing pad P 2 . In this case, the transistors Tr 0  and Tr 2  are turned on, and the transferring circuit  50  connects the test interface circuit  40  and the non-test interface circuit  42 .  
         [0077]     Also, the test apparatus  2  outputs the control signal to the test interface circuits  40 ,  41  and  42 . When outputting the control signal DQM 0  to the test interface circuit  40 , the test apparatus  2  outputs the control signal DQM 1  to the non-test interface circuits  41  and  42 . The test apparatus  2  outputs the probe signal such as the clock signal in order to check the operation of the portion of the internal circuit. At this time, the test apparatus  2  checks: (A) the operation of the portion of the internal circuit for the probing pad P 0 ; (B) the operation of the portion of the internal circuit for the non-probing pad P 1 ; and (C) the operation of the portion of the internal circuit for the non-probing pad P 2 . This will be described below with reference to  FIGS. 5 and 6 A to  6 G.  FIGS. 6A  to  6 G are timing charts when the test apparatus  2  sends a data to the probing pad P 0 .  
         [0078]     Here, since the operation check in the (A) case is identical to that of the first embodiment, its description is omitted.  
         [0079]     The operation check in the (B) case will be described below.  
         [0080]     When checking the operation of the portion of the internal circuit for the non-probing pad P 1 , the test apparatus  2  sends the first non-test probe signal corresponding to the control signal DQM 1  to the probing pad P 0  between timings c-e. Between the timings c-e, the first non-test probe signal indicates the high level in a first period between the timings c-d and indicates the low level in a second period between the timings d-e. The first non-test probe signal of the high level includes the write command and the write data as a first test data DQ (referred to as a first non-test data DQ) for the non-probing pad P 1 . The first non-test probe signal of the low level includes the read command. Also, the test circuit  90  sends the test mode signals T 0  and T 1  of the high level as the first test mode signal to the gates of the transistors Tr 0  and Tr 1  between the timings c-e in accordance with the command from the outside or test apparatus  2 . Since the first test mode signals T 0  and T 1  indicate the high level, the transistors Tr 0  and Tr 1  are turned on.  
         [0081]     At first, between the timings c-d, the test apparatus  2  sends the write command including the address to the probing pad P 0 . The input circuit  11  of the non-test interface circuit  41  receives the write command sent to the probing pad P 0  through the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50  in response to the control signal DQM 1 , and outputs the write command to the memory circuit in the internal circuit  80  through the internal input bus N 1  and the internal data bus  60 .  
         [0082]     Next, between the timings c-d, the test apparatus  2  sends the write data that is the first non-test data DQ to the probing pad P 0 . The input circuit  11  of the non-test interface circuit  41  receives the write data sent to the probing pad P 0  through the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50 , in response to the control signal DQM 1 , and outputs the write data to the memory circuit in the internal circuit  80  through the internal input bus N 1  and the internal data bus  60 . The write data is written to the memory cell corresponding to the address included in the-write command, among the plurality of memory cells of the memory circuit in the internal circuit  80 .  
         [0083]     Next, between the timings d-e, the test apparatus  2  sends the read command including the address to the probing pad P 0 . The input circuit  11  of the non-test interface circuit  41  receives the read command sent to the probing pad P 0  through the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50 , in response to the control signal DQM 1 , and outputs the read command to the memory circuit in the internal circuit  80  through the internal input bus N 1  and the internal data bus  60 . At this time, as the first non-test response data to the first non-test data DQ, the stored data is read out from the memory cell corresponding to the address included in the read command, among the plurality of memory cells of the memory circuit in the internal circuit  80 . The read data is sent from the memory circuit in the internal circuit  80  to the non-test interface circuit  41  through the internal data bus  60  and the internal output bus N 1 ′. The output circuit  31  of the non-test interface circuit  41  outputs the read data to the test apparatus  2  through the input protection circuit  21 , the transferring circuit  50 , the input protection circuit  20  of the test interface circuit  40  and the probing pad P 0 , in response to the control signal DQM 1 .  
         [0084]     Consequently, the test apparatus  2  compares the write data serving as the first non-test data DQ and the read data serving as the first non-test response data, for the test between the timings c-e. If they are coincident with each other, this generates the test result indicating the good sample, and if they are not coincident with each other, the test apparatus  2  generates the test result indicating a bad chip. Also, the non-test interface circuit  41  outputs the write data sent to the probing pad P 0  from the test apparatus  2  to the memory circuit in the internal circuit  80  through the internal input bus N 1  and the internal data bus  60 , and outputs the read data sent through the internal data bus  60  and the internal output bus N 1 ′ from the memory circuit in the internal circuit  80 , through the transferring circuit  50 , the test interface circuit  40  and the probing pad P 0  to the test apparatus  2 . Thus, if the write data and the read data are coincident with each other, the non-test interface circuit  41  represents that it is normal. In this way, according to the semiconductor chip according to the second embodiment of the present invention, the test apparatus  2  can check the operation of the portion of the internal circuit for the non-probing pad P 1  and can inspect the defect in the non-test interface circuit  41 .  
         [0085]     The operation check in the (C) case will be described below. When checking the operation of the portion of the internal circuit for the non-probing pad P 2 , the test apparatus  2  sends the second non-test probe signal corresponding to the control signal DQM 1  to the probing pad P 0  between timings e-g. Between the timings e-g, the second non-test probe signal indicates the high level in a first period between the timings e-f and indicates the low level in a second period between the timings f-g. The second non-test probe signal of the high level includes the write command and the write data as a second test data DQ (referred to as a second non-test data DQ) for the non-probing pad P 2 . The second non-test probe signal of the low level includes the read command.  
         [0086]     Also, the test circuit  90  sends the test mode signals T 0  and T 2  of the high level as the second test mode signal to the gates of the transistors Tr 0  and Tr 2  between the timings e-g in accordance with the command from the outside or test apparatus  2 . Since the second test mode signals T 0  and T 2  indicate the high level, the transistors Tr 0  and Tr 2  are turned on.  
         [0087]     At first, between the timings e-f, the test apparatus  2  sends the write command including the address to the probing pad P 0 . The input circuit  12  of the non-test interface circuit  42  receives the write command sent to the probing pad P 0  through the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50 , in response to the control signal DQM 1 , and outputs the write command to the memory circuit in the internal circuit  80  through the internal input bus N 2  and the internal data bus  60 .  
         [0088]     Next, between the timings e-f, the test apparatus  2  sends the write data that is the second non-test data DQ to the probing pad P 0 . The input circuit  12  of the non-test interface circuit  42  receives the write data sent to the probing pad P 0  through the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50 , in response to the control signal DQM 1 , and outputs the write data to the memory circuit in the internal circuit  80  through the internal input bus N 2  and the internal data bus  60 . The write data is written to the memory cell corresponding to the address included in the write command, among the plurality of memory cells of the memory circuit in the internal circuit  80 .  
         [0089]     Next, between the timings f-g, the test apparatus  2  sends the read command including the address to the probing pad P 0 . The input circuit  12  of the non-test interface circuit  42  receives the read command sent to the probing pad P 0  through the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50 , in response to the control signal DQM 1 , and outputs the read command to the memory circuit in the internal circuit  80  through the internal input bus N 2  and the internal data bus  60 . At this time, as the second non-test response data to the second non-test data DQ, the stored data is read from the memory cell corresponding to the address included in the read command, among the plurality of memory cells of the memory circuit in the internal circuit  80 . The read data is sent from the memory circuit in the internal circuit  80  to the non-test interface circuit  42  through the internal data bus  60  and the internal output bus N 2 ′. The output circuit  32  of the non-test interface circuit  42  outputs the read data to the test apparatus  2  through the input protection circuit  22 , the transferring circuit  50 , the input protection circuit  20  of the test interface circuit  40  and the probing pad P 0 , in response to the control signal DQM 1 .  
         [0090]     Consequently, the test apparatus  2  compares the write data serving as the second non-test data DQ and the read data serving as the second non-test response data, for the test between the timings e-g. If they are coincident with each other, the test apparatus  2  generates the test result indicating a good chip, and if they are not coincident with each other, the test apparatus  2  generates the test result indicating a bad chip. Also, the non-test interface circuit  42  outputs the write data sent to the probing pad P 0  from the test apparatus  2 , through the internal input bus N 2  and the internal data bus  60  to the memory circuit in the internal circuit  80 , and outputs the read data sent through the internal data bus  60  and the internal output bus N 2 ′ from the memory circuit in the internal circuit  80 , through the transferring circuit  50 , the test interface circuit  40  and the probing pad P 0  to the test apparatus  2 . Thus, if the write data and the read data are coincident with each other, the non-test interface circuit  42  represents that it is normal. In this way, according to the semiconductor chip based on the second embodiment of the present invention, the test apparatus  2  can check the operation of the portion of the internal circuit for the non-probing pad P 2  and can inspect the defect in the non-test interface circuit  42 .  
         [0091]     From the above-mentioned description, according to the semiconductor chip in the second embodiment, in addition to the effect of the first embodiment, one probing pad P 0  can be used to control the (M+1) systems composed of the test data DQ and the M non-test data DQ. Thus, according to the semiconductor chip of the present invention, the number of the times when the test apparatus  2  probes the pads can be reduced over the first embodiment.  
       Third Embodiment  
       [0092]     In the first embodiment, the test interface circuit  40  can take them in serial between the timings c-e for the operation check in the (B) case, although taking the test data DQ and the non-test data DQ through one probing pad P 0  at a same time. In the third embodiment, a case of M=1, namely, a case of the two systems will be described, and the description overlapping with that in the first and second embodiments is omitted.  
         [0093]      FIG. 7  shows the configuration of the semiconductor chip  1  according to the third embodiment of the present invention. The semiconductor chip  1  contains a test latch circuit  70 , a non-test latch circuit  71  and an inverter INV. The test latch circuit  70  is provided between the test interface circuit  40  and the test internal bus and connected to the input circuit  10  of the test interface circuit  40  and the internal input bus N 0 . The non-test latch circuit  71  is provided between the non-test interface circuit  41  and the non-test internal bus and connected to the input circuit  11  of the non-test interface circuit  41  and the internal input bus N 1 . The test apparatus  2  periodically outputs the clock signal to the test latch circuit  70  and the non-test latch circuit  71 .  
         [0094]     If the transistors Tr 0  and Tr 1  are the N-channel MOS transistors, the test circuit  90  sends the test mode signal T 0  of the low level to the gates of the transistors Tr 0  and Tr 1  and the non-test latch circuit  71 , when the test apparatus  2  carries out the operation check of the portion of the internal circuit  80  for the probing pad P 0 . Simultaneously, the test circuit  90  sends the test mode signal T 0  of the low level through the inverter INV to the test latch circuit  70 .  
         [0095]     The test circuit  90  sends the test mode signal T 0  of the high level to the gates of the transistors Tr 0  and Tr 1  and the non-test latch circuit  71 , when the test apparatus  2  carries out the operation check of the portion of the internal circuit for the non-probing pad P 1 . Simultaneously, the test circuit  90  sends the test mode signal T 0  of the high level through the inverter INV to the test latch circuit  70 .  
         [0096]     Here, the operation check in the (B) case is described by using  FIGS. 7 and 8 A to  8 E.  FIGS. 8A  to BE are timing charts when the data is sent from the test interface circuit  40  to the probing pad P 0 .  
         [0097]     When checking the operation of the portion of the internal circuit for the probing pad P 0 , the test apparatus  2  sends the test probe signal corresponding to the control signal DQM 0  to the probing pad P 0  between the timings c-d. The test probe signal includes the write command, the write data serving as the test data DQ, and the read command, as mentioned above. Also, the test circuit  90  sends the test mode signal T 0  of the low level to the gates of the transistors Tr 0  and Tr 1  between the timings c-d, in accordance with the command from the outside or test apparatus  2 . Since the test mode signal T 0  indicates the low level, the transistors Tr 0  and Tr 1  are not turned on.  
         [0098]     Between the timings c-d, the test apparatus  2  sends the write data serving as the test data DQ to the probing pad P 0 . The input circuit  10  of the test interface circuit  40  receives the write data sent to the probing pad P 0  through the input protection circuit  20 , in response to the control signal DQM 0 , and outputs the write data to the test latch circuit  70 . The test latch circuit  70  latches the write data from the input circuit  10  and outputs the write data to the memory circuit in the internal circuit  80  through the internal input bus N 0  and the internal data bus  60  in response to a clock signal CLK. As the test response data to the test data DQ, when the read data for the write data is read from the memory circuit in the internal circuit  80 , it is sent to the test interface circuit  40  through the internal data bus  60  and the internal output bus N 0 ′. The output circuit  30  of the test interface circuit  40  outputs the read data to the test apparatus  2  through the probing pad P 0  in response to the control signal DQM 0 .  
         [0099]     When checking the operation of the portion of the internal circuit for the non-probing pad P 1 , the test apparatus  2  sends the non-test probe signal corresponding to the control signal DQM 1  to the probing pad P 0  between the timings d-e. The non-test probe signal includes the write command, the write data serving as the test data DQ (referred to as the non-test data DQ) for the non-probing pad P 1 , and the read command, as mentioned above. Also, the test circuit  90  sends the test mode signal T 0  of the high level to the gates of the transistors Tr 0  and Tr 1  between the timings d-e, in accordance with the command from the outside or test apparatus  2 . Since the test mode signal T 0  indicates the high level, the transistors Tr 0  and Tr 1  are turned on.  
         [0100]     Between the timings d-e, the test apparatus  2  sends the write data serving as the non-test data DQ to the probing pad P 0 . The input circuit  11  of the non-test interface circuit  41  receives the write data sent to the probing pad P 0  through the input protection circuit  20  of the test interface circuit  40  and the transferring circuit  50 , in response to the control signal DQM 1 , and outputs the write data to the non-test latch circuit  71 . The non-test latch circuit  71  latches the write data from the input circuit  11  and outputs the write data to the memory circuit in the internal circuit  80  through the internal input bus N 1  and the internal data bus  60  in response to the clock signal CLK. As the non-test response data to the non-test data DQ, when the stored data is read out from the memory circuit in the internal circuit  80 , it is sent to the non-test interface circuit  41  through the internal data bus  60  and the internal output bus N 1 ′. The output circuit  31  of the non-test interface circuit  41  outputs the read data to the probing pad P 0  through the input protection circuit  21 , the transferring circuit  50 , the input protection circuit  20  of the test interface circuit  40  and the probing pad P 0  in response to the control signal DQM 1 .  
         [0101]     Consequently, the test apparatus  2  compares the write data serving as the test data DQ and the read data serving as the test response data, for the test between the timings c-d. If they are coincident with each other, the test apparatus  2  generates the test result indicating the good sample, and if they are not coincident with each other, the test apparatus  2  generates the test result indicating the bad sample. The test apparatus  2  compares the write data serving as the non-test data DQ and the read data serving as the non-test response data, for the test between the timings d-e. If they are coincident with each other, the test apparatus  2  generates the test result indicating the good sample, and if they are not coincident with each other, the test apparatus  2  generates the test result indicating the bad sample. In this way, in the semiconductor chip according to the third embodiment of the present invention, one probing pad P 0  can be used to capture the test data DQ and the non-test data DQ in serial.  
         [0102]     From the above-mentioned description, according to the semiconductor chip of the present invention, in addition to the effects of the first and second embodiments, one probing pad P 0  can be used to take the test data DQ and the non-test data DQ in serial. Thus, according to the semiconductor chip of the present invention, the test time when the test apparatus  2  tests the semiconductor chip can be reduced over the first and second embodiments.  
         [0103]     As mentioned above, in the semiconductor chip of the present invention, the operation of the portion of the internal circuit can be checked for each of the plurality of pads, and the defect in the interface circuit connected to each of the pads can be tested.