Abstract:
A processor having a unidirectional rotator configured to shift or rotate data in one direction is disclosed. The processor also includes a control unit having logic configured to modify a shift value specified by a registered-based shift, or rotate, instruction in an opposite direction, the modified shift value being usable by the rotator to shift, or rotate, the data in the one direction, and thereby, generate the same result as if the data in the rotator had otherwise been shifted, or rotated, in the opposite direction by the shift value originally specified by the registered-based instruction. The control unit is further configured to bypass the logic and provide to the rotator a shift value specified by a register-based instruction to shift, or rotate, the data in the one direction.

Description:
FIELD  
       [0001]     The present disclosure relates generally to processors, and more specifically, to register-based shifts for a unidirectional rotator.  
       BACKGROUND  
       [0002]     Processors are used extensively today in almost every electronic application. The processor controls the execution of program instructions, arithmetic functions, and access to memory and peripherals. In the simplest form, the processor executes program instructions by performing one or more arithmetic functions on data stored in memory. The arithmetic functions performed by the processor may vary depending upon the particular application. One type of arithmetic function that is commonly performed by the processor is a shifting or rotating operation. The shifting or rotating operation may be performed by a rotator and associated logic. A rotator is an arrangement of multiplexer elements that have their inputs and outputs connected together in such a way that the data is shifted down the line in response to a program instruction calling for a shift operation.  
         [0003]     The specific shifting operation called for by the program instruction may vary. For example, the program instruction may require a logical shift wherein the data is moved a discrete number of bit positions with the excess bits being discarded and the result being padded with zeros. An arithmetic shift is similar to a logical shift except the sign bit is extended to the left in a right shift operation and zeros are added to the lower-order bit positions in a left shift operation.  
         [0004]     A rotator may also be used to execute program instructions calling for a rotate operation. A rotate operation is similar to the shift operation, except that the rotate operation is circular. When a rotate instruction is implemented, the bits that are shifted out one end of the rotator are returned on the other end. Like shift instructions, rotate instructions can be to the left or right.  
         [0005]     Because program instructions for shift and rotate operations can be bi-directional, some processors incorporate a discrete left rotator and a right rotator. However, incorporating both may consume additional power and require more area or space. Accordingly, there is a need in the art for a processor based rotator that can execute shift and rotate instructions in both the left and right directions. The processor based rotator should be configured to minimize the latencies of the shifting and rotating operations.  
       SUMMARY  
       [0006]     One aspect of a processor is disclosed. The processor includes a unidirectional rotator configured to shift or rotate data in one direction, and a control unit having logic configured to modify a shift value specified by a registered-based shift, or rotate, instruction in an opposite direction, the modified shift value being usable by the rotator to shift, or rotate, the data in the one direction, and thereby, generate the same result as if the data in the rotator had otherwise been shifted, or rotated, in the opposite direction by the shift value originally specified by the registered-based instruction. The control unit is further configured to bypass the logic and provide to the rotator a shift value specified by a register-based instruction to shift, or rotate, the data in the one direction.  
         [0007]     Another aspect of a processor is disclosed. The processor is a n-bit unidirectional rotator configured to shift or rotate data in one direction, and a control unit having logic configured to modify a shift value m specified by a registered-based shift, or rotate, instruction in an opposite direction, the modified shift value being usable by the rotator to shift, or rotate, the data in the one direction by (n−m). The control unit is further configured to bypass the logic and provide to the rotator a shift value specified by a register-based shift, or rotate, instruction in the one direction.  
         [0008]     One method of performing a shift or rotate operation using a unidirectional rotator configured to shift or rotate data in one direction is disclosed. The method includes retrieving a shift value specified by a registered-based shift, or rotate, instruction in the one direction, and bypassing logic and providing to the rotator the retrieved shift value. The logic is configured to modify a shift value specified by a registered-based shift, or rotate, instruction in an opposite direction, the modified shift value being usable by the rotator to shift, or rotate, the data in the one direction, and thereby, generate the same result as if the data in the rotator had otherwise been shifted, or rotated, in the opposite direction by the shift value originally specified by the registered-based instruction,  
         [0009]     Another method of performing a shift or rotate operation using a n-bit unidirectional rotator configured to shift or rotate data in one direction is disclosed. The method includes retrieving a shift value specified by a registered-based shift, or rotate, instruction in the one direction, and bypassing logic and providing to the rotator the retrieved shift value. the logic is configured to modify a shift value specified by a registered-based shift, or rotate, instruction in an opposite direction, the modified shift value being usable by the rotator to shift, or rotate, the data in the one direction by (n−m).  
         [0010]     It is understood that other embodiments of the present disclosure will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown and described only various embodiments by way of illustration. As will be realized, other and different embodiments are possible and the several details contained herein are capable of modification in various other respects, all without departing from the spirit and scope of the present disclosure. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0011]     These, as well as other features will now become clear from a review of the following detailed description of illustrative embodiments and the accompanying drawings wherein:  
         [0012]      FIG. 1  is a simplified block diagram illustrating an example of a processor:  
         [0013]      FIGS. 2A-2C  are graphical illustrations showing the operation of a rotator in a processor; and  
         [0014]      FIG. 3  is a flow chart diagram illustrating the operation of a control unit in a processor. 
     
    
     DETAILED DESCRIPTION  
       [0015]     The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present disclosure and is not intended to represent the only embodiments in which the present disclosure may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present disclosure.  
         [0016]      FIG. 1  is a simplified block diagram illustrating an example of a processor  100 , or other computational system, capable of processing, retrieving and storing information. The processor  100  may be a stand-alone component, or alternatively, embedded in a device such as a computer, wireless telephone, personal digital assistant (PDA), digital camera, game console, or any other computational device. The processor  100  may be a microprocessor or other processing entity. In one embodiment, the processor  100  may be an embedded RISC microprocessor.  
         [0017]     The primary function of the processor  100  is to execute program instructions by performing a host of operations on data. The data may be retrieved and stored in register files  102  in general purpose memory internal to the processor  100 . The register files  102  are high-speed registers used for temporarily storing data from external memory. They provide low-latency access to data required by the processor  100 . The number of registers  102  (commonly referred to collectively as a general register file) is specified by the processor architecture. Each register is accessible by an execution unit  104  to enable the processor  100  to read data from one or more selected registers, execute on the data, and write the result to a selected register.  
         [0018]     The execution unit  104  uses an ALU (Arithmetic/Logic Unit), or other computational entities, to perform all mathematical operations of the processor  100 . It is generally comprised of complex circuitry that performs various functions including addition, subtraction, multiplication, division, and other calculations. The execution unit  104  may also be used to shift or rotate data. The shifting and rotating functions can be performed with a unidirectional rotator  106  and associated logic (not shown) in the execution unit  104 .  
         [0019]     The rotator  106  shown in  FIG. 1  will be described as a unidirectional rotator capable of shifting or rotating data any number of positions to the right. Those skilled in the art will readily appreciate the functionality of the rotator  106  described throughout this disclosure extends to unidirectional rotators that shift or rotate data to the left.  
         [0020]     The operation of the rotator will be illustrated with reference to  FIGS. 2A- 2C , In  FIG. 2A , the contents of an 8-bit rotator  202  is shown. The data in the 8-bit rotator may be rotated to the right by 2-bits, with the results shown in  FIG. 2B . Referring to  FIGS. 2B and 2C , one can readily see that a rotate right operation by 2-bits produces the same result as a rotate left operation by 6-bits. In other words, a rotator capable of rotating data in one direction can be used to emulate the rotation of data in the opposite direction. Thus, a rotate left operation by m-bits in a n-bit unidirectional rotator can be performed by rotating the data right by (n−m)-bits.  
         [0021]     A shift operation may be performed by first rotating the data by the appropriate amount in the rotator and then discarding the appropriate bits. The unoccupied bit-positions may be padded with zeros, or in the case of a arithmetic shift right operation, the sign-bit may be extended to the left into the unoccupied bit positions. For example, a shift left operation by m-bits may be performed by rotating the data in the rotator by (n−m)-bits to the right, discarding the m-LSBs, and padding the m-LSB bit-positions with zeros. A shift right operation by m-bits may be performed by rotating the data in the rotator by m-bits to the right, discarding the m-MSBs, and padding the M-MSB bit-positions with zeros. In the case of a arithmetic shift right operation, the sign-bit may be extended left into the M-MSB bit-positions in the rotator.  
         [0022]     Returning to  FIG. 1 , the operation of the execution unit  104  is controlled by program instructions stored in an instruction cache  108 . The instruction cache  108  is small high speed memory on the processor  100 . It provides temporary high speed storage for program instructions fetched from external memory. The program instructions are provided to a decoder  110  and the decoded instructions used to activate the execution unit  104  to perform mathematical operations.  
         [0023]     Program instructions generally comprise of two parts: the op-code and the operand field. The op-code specifies the operation to be performed by the execution unit  104 , such as add, subtract, store, rotate, shift, etc. The operand field provides more detail about the operation specified by the op-code. For example, in the case of a shift operation, the operand field indicates which register in the general register file  102  contains the data to be shifted, the direction of the shift, and the number of bit positions to shift the data. In this example, the operand field may call for the data in a first register to be shifted to the right by m-bits. Alternatively, the operand field may call for the data in a first register to be shifted by an amount specified in a second register. The former program instruction is commonly referred to as an “instruction-based shift,” and the latter program instruction referred to as a “register-based shift.” 
         [0024]     A control unit (not shown) is responsible for directing the flow of program instructions and data within the processor. One of the control unit&#39;s many functions is to provide the data specified in the operand field of a arithmetic instruction to the execution unit  104 . The data may be provided from any source depending on the architecture of the processor. For example, the data may be in the general register file  102 , cache, or other memory. In some instances, the data may be in the pipeline  122  of the execution unit  104 , and therefore, must be retrieved by the control unit and fed back to the input of the execution unit  104 . The control unit may employ certain logic that allows it to recover data early from any stage in the pipeline  122 . The control unit is generally implemented with a complex arrangement of decoders, multiplexers, and associated logic. In  FIG. 1 , the decoder  110 , multiplexers  112 ,  118 , latch  114 , and shift correction logic  116  form part of the control unit.  
         [0025]     In addition to controlling the flow of data into the execution unit  104 , the control unit is also responsible for providing the op-code of the program instructions in the instruction cache  108  to the multiplexer  118  in the execution unit  104 . The multiplexer  118  is used to switch the output of the rotator  106 , or some other computational function  120 , down the pipeline  122  before the control unit stores the result in the general register file  102 . In the case of an instruction-based shift or rotate instruction, the operand field is routed through the multiplexer  112  and provided to the rotator  106  to tell it how many bit-positions to shift the data. The decoder  110 , or other entity, may be used to convert a left shift, or rotate, to a right shift, or rotate, instruction by modifying the shift amount by (n−m).  
         [0026]     The decoding function just described is well suited for instruction-based shifts or rotates because the instructions are available in the instruction cache  108  well in advance of execution by the processor  100 . However, in the case of register-based shifts, or rotates, certain latencies can be experienced if the data specifying the shift amount for a current shift or rotate instruction is not in the general file register  102 , but somewhere in the pipeline  122  of the execution unit  104 .  
         [0027]     In at least one embodiment of the processor  100 , the control unit may be configured to efficiently process registered-based shift and rotate instructions. For example, the function of modifying the shift value for a shift or rotate instruction may be performed by the control unit, rather than the decoder  110 , for a registered-based shift, or rotate, instruction. More specifically, the operand field for a registered-based shift, or rotate, instruction may provided to the control unit. The control unit locates the shift value specified by the operand field, either in the general file register  102  or the pipeline  122  of the execution unit, and delivers the shift value to the input of the latch  114  through the multiplexer  112 . Once the data is delivered to the input of the latch  114 , the control unit determines whether to load the data into the execution unit  104  on the following clock cycle, or first modify the shift value.  
         [0028]     The process of delivering the shift value to the execution unit for a shift or rotate instruction will be described with reference to  FIGS. 1 and 3 . The control units determines whether the instruction is registered-based or instruction-based in step  302 . If the control unit determines that the instruction is instruction-based, then the shift value is provided to the execution unit  104  in block  304 , and the execution unit  104  shifts or rotates the data in the rotator to the right by an amount specified by the shift value in block  305 . The shift value may have been modified previously by the decoder  110 , or some other entity, if the instruction-based shift or rotate instruction was to the left.  
         [0029]     If the control unit determines that the instruction is a registered-based instruction, then it determines whether the registered-based instruction calls for a right or left shift, or rotate, operation in block  306 . If the control unit determines the instruction calls for a right shift, or rotate, operation, then the shift value is provided to the execution unit  104  in block  304 , and the execution unit  104  shifts or rotates the data in the rotator to the right by an amount specified by the shift value in block  305 .  
         [0030]     If the control unit determines that instruction is a registered-based instruction to the left, then the shift value is provided to the shift correction logic  116  in block  307 . In block  308 , the shift value is modified by (n−m), where n is the size of the rotator  106  and m is the shift value. The modified shift value is provided to the execution unit  104  in block  304 , and the execution unit  104  shifts or rotates the data in the rotator to the right by an amount specified by the shift value in block  305 .  
         [0031]     The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.  
         [0032]     The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in the terminal, or elsewhere. In the alternative, the processor and the storage medium may reside as discrete components in the terminal, or elsewhere.  
         [0033]     The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the full scope consistent with the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” All structural and functional equivalents to the elements of the various embodiments described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”