Abstract:
Methods and apparatus for aligning the transmitters of two or more bidirectional ports of an integrated circuit (IC), particularly an application-specific IC (ASIC) or field-programmable gate array (FPGA). Misalignment of two or more transmitters is determined by the IC itself without the use of external test equipment. Receivers of the bidirectional ports whose transmitters are to be aligned are used by the IC to detect misalignment. Any misalignment of the receivers is also determined and either eliminated or taken into account when aligning the associated transmitters. Variants for ICs with and without internal loop-back capability and for ICs with and without differential outputs are described.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to the field of high-speed data communications, and in particular, to the processing of data in multiple parallel data streams.  
       BACKGROUND INFORMATION  
       [0002]     Whenever multiple, parallel data streams clocked at a first lower rate are to be temporally multiplexed into one or more serial data streams of a higher rate, or whenever multiple data streams at some rate need to be available with a well-defined temporal phase relationship (e.g., before entering a digital-to-analog converter), it is important to temporally align the multiple, lower-rate, data streams. Often, the multiple data streams are generated inside an integrated circuit (IC), such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The generation of the lower speed parallel data streams within an IC, i.e., in the IC “fabric” or “core,” will typically be clocked in accordance with an internal clock of correspondingly lower frequency (R IC ). The multiple, lower speed parallel data streams are provided by the IC fabric to corresponding high-speed transmitters of the IC for high-speed (R IO ) serial output to external circuitry. While the transmitters of an IC are typically synchronized with each other on a time scale corresponding to R IC , they are not necessarily synchronized with each other on the much finer time scale corresponding to R IO .  
         [0003]     The serialization carried out at each transmitter of the IC is typically at a substantially higher clock rate (e.g., R IO =10 GHz) than is available in the IC core (e.g., R IC =250 MHz). Each port will typically include circuitry to generate the higher rate clock based on the lower-rate core clock distributed to all ports by the core. As such, the different ports will have their own high speed clocks which will have the same frequency, but will not necessarily be in phase. In fact, the phase relationship among the various high speed clocks will generally be random and can change whenever the IC is powered up or re-programmed (in the case of an FPGA). This is due to the fact that the system and signal characteristics at the IC core clock frequency R IC  are low-speed relative to Rio; in particular, signal rise times, pulse shapes, and device switching thresholds are representative of signals at R IC  rather than of signals at R IO . As a result, using a low-speed, low-bandwidth clock signal, it is difficult to reliably synchronize multiple high-speed signals at R IO .  
         [0004]      FIG. 1  illustrates the nature of the problem described above.  FIG. 1  shows a portion of a cycle of the low-rate internal IC clock signal  10  (at R IC ) with a region of uncertainty  10   a  within which the clock signal may fall. The synchronization of the high-rate Rio clock to the low-rate R IC  clock will depend on the crossing of the low-rate clock through some threshold  12 . The threshold  12  will also have a region of uncertainty  12   a  surrounding it. The overlap of the uncertainty regions  10   a  and  12   a  delimits a temporal range of uncertainty  20  over which the synchronization can occur. The range of uncertainty  20  may span several cycles of the high-speed IO clock signal (RIO), shown in  FIG. 1  as signal  25 , thus leading to misalignments of several bits.  
         [0005]     As a result, data streams may be output by the IC with substantial temporal skew, or “inter-bit shift” amongst them. Instead of transitioning from one state to another synchronously, i.e., in “alignment,” the data streams will typically transition at different times and are said to be “misaligned.” 
         [0006]     A solution to this alignment problem has been the use of parallel interface alignment protocols such as SFI-4 or SFI-5. This, however, requires that the device that receives the parallel data streams (e.g., a TDM multiplexer) is also equipped with such an interface, which may not always be the case in practice, and which may even be technically impossible.  
       SUMMARY OF THE INVENTION  
       [0007]     In an exemplary embodiment, the present invention provides a scheme for the temporal alignment of multiple parallel data streams transmitted by different transmitters of a circuit, in particular an integrated circuit (IC) such as an ASIC or FPGA. The method can be automated and does not require external measurement and control devices. The alignment functionality or portions thereof can be implemented as part of the IC itself.  
         [0008]     An exemplary method of aligning multiple transmitters of a circuit comprises the step of first aligning receivers that are associated with the transmitters. Once the receivers are aligned, data streams with the same test pattern are sent from the circuit core to the transmitters and looped-back via the respective receivers for reception by respective receive buffers. The contents of the receive buffers are compared to determine any misalignment between the transmitters. The amount of the misalignment is then used to pre-shift the transmitted data streams so as to offset the misalignment.  
         [0009]     In a further exemplary embodiment, data stream alignment is carried out by first looping-back a test pattern via a first transmitter, to a receiver associated with a second transmitter, into a receive buffer coupled to the receiver. The same test pattern is then looped-back via the second transmitter and the receiver to the receive buffer. A comparison of the contents of the receive buffer after the second loop-back with the contents of the receive buffer after the first loop-back is used to determine the extent of the misalignment of the two transmitters, which can then be used to bring the two transmitters into alignment.  
         [0010]     These and other features and aspects of the present invention are described more fully below. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  illustrates the cause of synchronization uncertainty when generating high-speed signals from a low-speed signal.  
         [0012]      FIGS. 2A and 2B  are schematic representations of a portion of an integrated circuit showing two transceiver ports during first and second portions, respectively, of an exemplary alignment method in accordance with the present invention.  
         [0013]      FIG. 3  is a schematic representation of a portion of an integrated circuit showing two transceiver ports during an exemplary alignment method in accordance with the present invention, wherein the transceiver ports lack loop-back capability.  
         [0014]      FIG. 4  is a schematic representation of a portion of an integrated circuit showing two transceiver ports during an exemplary alignment method in accordance with the present invention, wherein the transceiver ports lack differential outputs.  
         [0015]      FIG. 5  shows an exemplary embodiment of an arrangement for the alignment of more than two ports in accordance with the present invention.  
         [0016]      FIGS. 6A and 6B  are schematic representations of a portion of an integrated circuit showing two transceiver ports during a further exemplary alignment method in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0017]     An exemplary embodiment of a method in accordance with the present invention for temporally aligning the outputs of an integrated circuit will now be described with reference to  FIGS. 2A and 2B , which show two transceiver ports  101  and  102  of an integrated circuit  100  during first and second portions of the method, respectively. Initially, only two ports A and B are shown for simplicity, with the alignment of more than two ports described further below.  
         [0018]     As is common in ASIC and FPGA designs, each transceiver port  101  ( 102 ) has a pair of differential outputs, TXAn and TXAp (TXBn and TXBp) and a pair of differential inputs RXAn and RXAp (RXBn and RXBp). Each transceiver port  101  ( 102 ) may also have a loop-back capability whereby the state of its differential outputs TXAn and/or TXAp (TXBn and/or TXBp) can be looped-back via its inputs RXAn and/or RXAp (RXBn and/or RXBp) while any signals applied externally to the inputs may be ignored.  
         [0019]     In the exemplary embodiment of  FIGS. 2A and 2B , the inputs RXAp/n and RXBp/n of the ports  101  and  102 , respectively, are coupled to receiver buffers  103  and  104 , respectively. The receive buffers  103  and  104  are preferably of the same width (N bits). Each bidirectional port also has a transmit buffer (TX buffer A  106 , TX Buffer B  108 ) associated with its transmitter. The transmit buffers  106  and  108  are also preferably of the same width (N bits).  
         [0020]     In the configuration of  FIG. 2A , a pre-defined test pattern TP 1  is loaded in parallel from the fabric core of the IC  100  into the transmit buffer (TX Buffer A)  106  associated with the transceiver port A. Data is loaded into the TX Buffer A  106  in parallel at a first clock rate CLK 1  (e.g., RIC=250 MHz) and serially read out of the TX Buffer A at a second, higher clock rate CLK 2 A that is N times faster than CLK 1  (e.g., RIO=10 GHz, with N=40). CLK 2 A is generated in a conventional way from CLK 1  (e.g., such as by frequency multiplication). The test pattern is preferably random and with the preferred pattern length depending on the overall amount of pattern shift uncertainty, i.e. the sum of all uncertainties to be handled in one step of the algorithm. In an exemplary embodiment, the test pattern is 2N bits long (e.g., 80 bits).  
         [0021]     The test pattern TP 1  is looped-back by the port A (i.e., TXAp/n−&gt;RXAp/n) to receive buffer A  103 . The uninverted output of the port A, TXAp, is also coupled (internally or externally) to the uninverted input of the port B, RXBp, thereby causing the test pattern TP 1  to be sent simultaneously to receive buffer B  104 . The test pattern TP 1  is shifted serially into receiver buffer B  104  in accordance with a clock CLK 2 B, which has the same frequency as CLK 2 A and is generated from CLK 1  but which has an uncertain phase relationship with CLK 1  and with CLK 2 A.  
         [0022]     After the test pattern TP 1  has been clocked out of the TX buffer A  106  and into the receive buffers  103  and  104 , a determination of the misalignment of the receive paths of the ports A and B can be performed by comparing the contents of the RX buffers  103  and  104 . Such a comparison can be carried out, for example, by an exclusive-OR (XOR) operation in which the corresponding bits of the RX buffers A and B ( 103  and  104 ) are XOR′ed together. If the comparison indicates that the contents of the RX buffers A and B are not the same (i.e., XOR=1), the contents of at least one of the buffers (e.g., RX buffer B) are bit-wise rotated and compared to the contents of the other buffer until equality is achieved (i.e., XOR=0). The number of bits by which the contents of the RX buffers were rotated relative to each other is thus indicative of the misalignment of the two receive paths. This number, which will be referred to as the receive path misalignment (RPM), is saved and is used whenever the buffers are re-filled and read again, to compensatingly rotate the contents of one or both of the receive buffers A and B relative to each other so as to bring the two receive paths into alignment.  
         [0023]     In an alternative embodiment, if the first comparison of the RX buffers A and B indicates a misalignment (i.e., XOR=1), the RPM can be determined by turning off the loop-back within port A; (i) bit-wise rotating the test pattern TP 1 ; (ii) loading the rotated test pattern into the TX buffer A  106 ; (iii) shifting the rotated test pattern out of TX buffer A  106 ; (iv) looping it back to the RX buffer B  104 ; (v) comparing the contents of the RX buffers A and B; and repeating the aforementioned steps i-v until the contents of RX buffer B match those of RX buffer A. The total amount by which the test pattern TP 1  has been rotated until the match occurs is thus indicative of the RPM.  
         [0024]     In yet a further exemplary embodiment, the comparison of the RX buffers A and B and the determination of the RPM can be carried out, for example, in software. In such an embodiment, the software can read the contents of the RX buffers A and B in search of the test pattern and determine the position of the test pattern in each buffer. The number of bits between the positions is thus indicative of the RPM.  
         [0025]     Once the receive paths of the ports A and B have been aligned as described above, a second procedure, to be described now with reference to  FIG. 2B , is carried out to align the transmit paths of the ports A and B. As shown by the dashed lines in  FIG. 2B , a test pattern TP 2  is loaded into TX buffer A  106  and into TX buffer B  108 . The contents of TX buffer A are clocked out serially at CLK 2 A and looped-back to RX buffer A  103  and the contents of TX buffer B are clocked out serially at CLK 2 B and looped-back to RX buffer B  104 . The steps of loading, clocking-out TX buffer A, and clocking-in RX buffer A, are preferably carried out simultaneously with the loading, clocking-out of TX buffer B, and clocking-in of RX buffer B, respectively, so as to save time, but is not a necessity. (Also, although not shown in  FIG. 2B , the connection between TXAp and RXBp shown in  FIG. 2A  can be maintained during the second, transmit alignment procedure, since the receiver of port B, being in loop-back mode, would ignore the signal from port A anyway.)  
         [0026]     Where the receive paths have already been aligned as described above in connection with  FIG. 2A , the data streams received at the RX buffers A and B ( 103 ,  104 ) during the transmit alignment procedure contain information about any misalignment that may exist between the transmit paths, i.e., the transmit path misalignment (TPM). To determine whether a misalignment exists, the contents of the RX buffers A and B can be compared such as by XOR′ing their corresponding bits, with a XOR=1 indicating a misalignment. The TPM can be determined by iteratively rotating the data in one of the RX buffers A, B (e.g., one bit at a time) until the XOR combination between the two RX buffers A, B equals 0. The number of rotations required yields the misalignment between the transmitted data streams (i.e., the TPM). Once this misalignment has been determined, it can be used to pre-shift the user data before it is transmitted, thereby aligning the transmitted user data streams of the two transmitters to some desired bit shift.  
         [0027]     In an alternative embodiment, if the first comparison of the RX buffers A and B indicates a misalignment (i.e., XOR=1), the TPM can be determined by (i) bit-wise rotating the test pattern TP 2 ; (ii) loading the rotated test pattern TP 2  into the TX buffer B  108 ; (iii) shifting the rotated test pattern out of TX buffer B; (iv) looping it back to the receive buffer B  104 ; (v) comparing the contents of RX buffer B to those of RX buffer A  103 ; and repeating the aforementioned steps i-v until the contents of the RX buffers A and B are the same. The total amount by which the test pattern TP 2  has been rotated until the match occurs is thus indicative of the TPM.  
         [0028]     In yet a further exemplary embodiment, the comparison of the RX buffers A and B and the determination of the TPM can be carried out, for example, in software. In such an embodiment, the software can read the contents of the RX buffers A and B in search of the test pattern TP 2  and determine the position of the test pattern in each buffer. The number of bits between the positions is thus indicative of the TPM.  
         [0029]     Where the receive path misalignment RPM has been determined and saved, as described above in connection with  FIG. 2A , it is unnecessary to actually align the receive paths before performing the transmit path alignment described with respect to  FIG. 2B . In this case, the contents of the RX buffers A and B after the procedure of  FIG. 2B  will reflect a combined receive and transmit path misalignment (i.e., RPM+TPM). Once this combined misalignment is determined (e.g., by the aforementioned iterative, XOR comparison of RX buffers), the TPM can be determined by subtracting the RPM from the combined misalignment. The TPM can then be used to pre-shift one or more of the bit streams of the ports A and B to cancel the TPM so that they will be transmitted in alignment.  
         [0030]     As can be appreciated by one of ordinary skill in the art, portions of the above-described alignment procedures can be implemented in hardware (e.g., in the IC itself), in software, or a combination of both. For example, the comparison and bit-wise rotation of the contents of the RX buffers A and B can either be performed using logic on the IC or in a software routine that reads the RX buffers and processes their contents.  
         [0031]     As shown in  FIGS. 2A and 2B , loop-back from the transmitter to the receiver of a transceiver port ( 101 ,  102 ) can be implemented internally to the IC. Where the IC lacks an internal loop-back capability, however, loop-back can be implemented external to the IC, as illustrated in  FIG. 3 . In the embodiment shown, a splitter  205  is used to couple TXAp to RXAp and to RXBp, allowing implementation of the receive path alignment procedure described above with reference to  FIG. 2A . A further splitter  206  is used to couple TXBp and TXAp to RXBp, thereby allowing implementation of the transmit path alignment procedure described above with reference to  FIG. 2B . Note, however, that because the transceiver ports A and B lack the internal loop-back capability, their respective receivers are not capable of ignoring signals applied to them externally. As such, when carrying out the transmit path alignment procedure, test pattern TP 2  is loaded into TX buffer A  106 , clocked-out of TX buffer A, and looped-back and clocked-in to RX buffer A while port B remains inactive. Once this has been completed, test pattern TP 2  is then loaded into TX buffer B  108 , clocked-out of TX buffer B, and looped-back and clocked-in to RX buffer B while port A remains inactive (i.e., the contents of RX buffer A reflect the prior loop-back of test pattern TP 2  into RX buffer A). The contents of RX buffers A and B can then be compared, as described above, to determine the transmit path misalignment.  
         [0032]     The above embodiments assume the use of transceiver ports  101 ,  102  with differential outputs (e.g., TXAp, TXAn). For those cases in which the transceivers lack the internal loop-back capability and do not have differential outputs, an alternative arrangement, such as that illustrated in  FIG. 4 , can be used. In the exemplary arrangement of  FIG. 4 , a splitter  207  is inserted between the transceiver  101  output TXA and the splitter  205 , with one output of the splitter  207  providing the output data and the other output of the splitter being coupled to the input of the splitter  205  for the loop-back to receiver inputs RXA and RXB. An additional splitter  208  is provided at the transceiver  102  output TXB, with one output of the splitter  208  providing the output data and the other output of the splitter being coupled to the input of the splitter  206  for the loop-back to input RXB.  
         [0033]     The various splitters  205 - 208  mentioned above can be implemented in a known way, such as with standard, “6 dB” or “50:50” power splitters, for example, as long as the inputs coupled to the splitter outputs receive a signal larger than the required minimum input level.  
         [0034]      FIG. 5  shows an exemplary embodiment of an arrangement for the alignment of more than two ports. In the arrangement of  FIG. 5 , ports are aligned pair-wise; i.e., ports A and B are aligned first, then ports B and C, and so on. For ports lacking internal loop-back and/or differential outputs, the configurations described above with reference to FIGS.  3  and  4  can be readily applied to the arrangement of  FIG. 5 , as can be appreciated by one of ordinary skill in the art.  
         [0035]      FIGS. 6A and 6B  show an arrangement for aligning two ports A and B without first aligning their receive paths. In a further exemplary embodiment of a method of the present invention, a test pattern is first loaded into the TX buffer A  106  from the IC fabric and serially shifted to the output TXAp of port  101  in accordance with the clock CLK 2 A. The test pattern is looped-back to input RXBp and serially shifted into RX buffer B  104  in accordance with clock CLK 2 B. After the test pattern has been shifted out of the TX buffer A  106 , the contents of the RX buffer B are placed in temporary storage  105 . The IC fabric then loads the same test pattern to the TX buffer B  108  which is then serially shifted to the output TXBp of port  102  in accordance with the clock CLK 2 B. The port  102  is configured to loop-back the test pattern to the RX buffer B  104 .  
         [0036]     After the test pattern has shifted out of the TX buffer B  108 , the contents of the RX buffer B are compared to the contents of the temporary storage  105 . If the contents of the RX buffer B are the same as that of the temporary storage  105 , a determination is made that the transmitters of ports A and B are in alignment. If the contents are not the same, the test pattern is shifted by one bit, reloaded into the TX buffer B  108  and shifted out of TX buffer B and into RX buffer B  104  via the internal loop-back. The contents of the RX buffer  104  are then compared again to the temporary storage  105  and the above process is repeated until a match is attained. For a test pattern that is 2N bits long, up to 2N different versions of the test pattern (each version shifted by one bit relative to the previous version) can be looped-back until a match is found. Once there is a match, a determination can be made of the extent of the misalignment (i.e., the TPM) between the transmit paths of ports A and B, the TPM being equivalent to the amount by which the test pattern was shifted to attain the aforementioned match. The TPM can then be used to compensatingly pre-shift the contents of at least one of the TX buffers A and B to bring the ports into alignment.  
         [0037]     Note that in the embodiment of  FIGS. 6A and 6B , port A need not be bidirectional since there is no need for the port A to have a receiver in order to carry out the alignment method.  
         [0038]     In an alternative embodiment, the extent of the misalignment (i.e., the TPM) between the transmit paths of ports A and B can be determined by iteratively rotating the contents of at least one of the RX buffer B  104  and the temporary storage  105  and comparing the two until a match is attained. The number of bits by which the contents of the RX buffer B  104  were rotated relative to each other until the match is achieved is thus indicative of the misalignment of the two transmit paths.  
         [0039]     In yet a further exemplary embodiment, the comparison of the temporary storage and the RX buffer B and the determination of the TPM can be carried out, for example, in software. In such an embodiment, the software can read the contents of the temporary storage and the RX buffer B in search of the test pattern and determine the position of the test pattern in each. The number of bits between the positions is thus indicative of the TPM.  
         [0040]     For ports lacking a loop-back capability and/or differential outputs, the configurations described above with reference to  FIGS. 3 and 4  can be readily applied to the arrangements of  FIGS. 6A and 6B , as can be appreciated by one of ordinary skill in the art.  
         [0041]     It is understood that the above-described embodiments are illustrative of only a few of the possible specific embodiments which can represent applications of the invention. Numerous and varied other arrangements can be made by those skilled in the art without departing from the spirit and scope of the invention.