Abstract:
An improved master-slave flip-flop that is characterized by a novel clock generator. The improved flip-flop preserves the true master-slave relationship by ensuring a two step latching process is executed by non-overlapping clocks. The clock generator features an inverter in combination with a current limiter. The current limiter has the effect of shifting the trip point of the inverter such that non-overlapping clocks may be derived from a single master clock signal or a master clock signal and its complement.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to digital computer systems and specifically to digital computer systems which rely on master-slave latches or flip-flops. The invention provides an apparatus and method for generating quickly slewing clock signals with non-overlapping duty cycles from a master clock that has relatively slow rise and fall times. 
     2. Description of the Prior Art 
     Referring to FIG. 1, the current state of the art describes a master-slave latch combination in which data is clocked into the master latch  20  and slave latch  40  through a two sets of gating transistor pairs  10  and  30 , respectively, by a master clock CLK and its complement  CLK   1 . D indicates the input data and Q represents the static state output of D after proper latching by the master latch  20  and the slave latch  40 . The master clock signal CLK and its complement  CLK  are depicted in FIG.  2 . 
       1  The conventional method to indicate a complementary signal is to overline the signal. However, due to a word processing limitation, following this convention is not possible. Thus, in the text of this application the symbol for a complementary signal is set for as the signal underlined (e.g.  CLK ).  
     When properly operating, the master clock CLK goes from low to high, the gating transistor pair  10  is conducting and data is permitted to pass into the master latch  20 . Also at this time, because the clock signals are inverted at gating transistor pair  30 , this transistor pair is switched off and data is not permitted to pass into the slave latch  40 . 
     When the master clock CLK reverses state, i.e. from high to low, the first gating transistor pair  10  ceases to conduct. However, the second gating transistor pair  30  begins conducting and the data which was latched into the master latch  20  is now permitted to pass into the slave latch  40 . After a brief propagation delay, the data is latched and stable at output Q. 
     Thus, when the master-slave latch is operating properly, latching occurs in two separate, discrete steps. These two steps provides for stable data at output Q. However, a problem arises during slow rise and fall times of the master clock CLK. 
     The problem during the clock transition characterized by relatively slow rise and fall times is that both gating transistor pairs  10  and  30  may be partially conducting at the same time. This will result in the data racing through the master-slave latch pair  20  and  40  without achieving a steady state. This occurs when the two step process described above is circumvented because of overlapping master clock signals as a result of relatively slow rise and fall times. Therefore, a need existed to provide a master-slave latch pair with non-overlapping clock signals to permit proper latching of data in a two step process for master-slave latches. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a master-slave flip-flop which prevents data from racing through the device without being properly latched. 
     It is another object of the present invention to provide a master-slave flip-flop which prevents partial conduction of the gating transistor pairs. 
     It is another object of the present invention to provide an improved clock generator which produces non-overlapping clock signals from a master clock signal. 
     It is another object of the present invention to combine the non-overlapping clock signals provided by the improved clock generators with gating transistor pairs and master-slave latches to preserve the two, discrete latching steps of a master-slave flip-flop. 
     In accordance with one embodiment of the present invention, an improved master-slave flip-flop comprises a master gating transistor pair, a master latch coupled to the master gating transistor pair, a slave gating transistor pair coupled to the master latch, a slave latch coupled to the slave gating transistor pair, a clock generator coupled to the master gating transistor pair, a second clock generator coupled to the master gating transistor pair, a third clock generator coupled to the slave gating transistor pair, and a fourth clock generator coupled to the slave gating transistor pair. 
     In accordance with another embodiment of the present invention, a clock generator is comprised of a current limiter and an inverter coupled to the current limiter. Furthermore, the current limiter may be implemented as a current mirror. 
     In accordance with another embodiment of the present invention the trip point of the inverter is adjusted by means of the current limiter or by geometrical manipulation of the CMOS devices which comprise the inverter. 
     In accordance with another embodiment of the present invention, non-overlapping clocks may be derived from a single master clock signal by the clock generators. 
     In accordance with another embodiment of the present invention, non-overlapping clocks may be derived from a single master clock signal and the complement of the master clock signal. 
     The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified diagram of a master-slave latch pair. 
     FIG. 2 illustrates a master clock and complement with relatively slow rise and fall times. 
     FIG. 3 is a block diagram of the present invention. 
     FIGS. 4A,  4 B,  4 C and  4 D are various embodiments of the clock generator in the present invention which rely on a master clock signal and its complement. 
     FIGS. 5A and 5B illustrate the clock generator implemented by a current mirror. 
     FIGS. 6A and 6B illustrate how the present invention shifts the trip point of an inverter. 
     FIGS. 7 is a timing diagram of the non-overlapping clock signals derived from complementary master clock signals. 
     FIGS. 8A and 8B illustrate an alternative embodiment of the clock generators in the present invention using a single master clock signal without its complement. 
     FIG. 9 is a timing diagram of the non-overlapping clock signals derived from a single master clock signal. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 3, an improved master-slave flip-flop with non-overlapping clocks  100  is shown. The invention is comprised of a master gating transistor pair  10 , a master latch  20 , a slave gating transistor pair  30 , a slave latch  40  and four independent clock generators  101 - 104 . Input data D occurs at the input side of master gating pair  10  and output Q occurs at the output of slave latch  40 . 
     Referring to FIGS. 4A,  4 B,  4 C and  4 D, simplified diagrams of the clock generators  101 - 104  are shown comprising of a current limiter  110  coupled to a two transistor inverter  120 . The current limiter  110  may be positioned either on the power side of the transistor pair as shown in FIGS. 4A and 4B, i.e. in series with the P-channel device as depicted by  101  and  102 ; or on the ground potential side of the transistor pair as shown in FIGS. 4C and 4D, i.e in series with the N-channel device as depicted by  103  and  104 . The input may be either the master clock CLK, as in FIGS. 4A and 4C or the complementary master clock  CLK , as in FIGS. 4B and 4D. The phase shift in the CLK versus  CLK  input will simply result in a comparable phase shift in the output of the inverter  120 . 
     The purpose of the current limiter  110  is to shift the trip point of the transistor pair  120  from what is normally the approximate midpoint between V DD  and V SS . As shown in FIGS. 6A and 6B, the trip point (V T ) is conventionally defined as the point where V IN =V OUT . However, depending on the positioning of the current limiter  110 , the new trip point will approximate either V TN  (V T′ in FIG. 6A) or V DD −V TP (V T″  in FIG.  6 B). Where V TN  is the threshold voltage of the N-channel transistor and V TP  is the threshold voltage of the P-channel transistor. 
     The current limiter  110  may be implemented in a variety of fashions. In the preferred embodiment, the current limiter  110  is implemented via a current mirror  111  as shown in FIGS. 5A and 5B. FIG. 5A illustrates the current mirror  111  in series with and directly connected to the P-channel device. FIG. 5B illustrates the current mirror  111  in series with and directly connected to the N-channel device. 
     Other embodiments of a current limiter may include components beyond a current mirror to effectively limit current. However, simple resistor networks are typically not preferred because of resulting inefficiencies in the fabrication process. 
     However, other implementations of adjusting the trip point of the inverter other than the current mirror include geometrical manipulation of the inverter N-channel and P-channel length/width ratio as part of the fabrication process. In this implementation the length/width ratios of the transistors are manipulated in the fabrication process. Additional fabrication techniques to adjust the trip point of the inverter such as doping and ion implantation may also be employed. 
     The following relates the function of the current limiter  110  to the shift in the trip point V T . Referring to FIG. 4A, disregarding the presence of the current limiter  110  and where the gain of the P-channel transistor is equal to the gain of the N-channel transistor for the inverter  120 , then the trip point can be expressed as: 
     
       
         V T =(V TN +(V DD −V TN ))/2=(V DD )/2  (1) 
       
     
     Thus, in the absence of a current limiter  110 , the trip point is approximately half of the supply voltage V DD . Gain is defined as the width to length ratio of the transistor multiplied by a constant. If the gain of the N- and P-channel transistors are not equal then the denominator of equation (1) becomes more complicated in the form of 1+(k P /k N ) 0.5 , where k P  and k N  are the gain ratios of the P- and N-channel transistors, respectively. Thus, it becomes intuitive that shifting the trip point can be accomplished by altering the gain ratios as between the N- and P-channel transistors. The gain ratios k P , and k N , are determined by the length/width ratios of the respective transistors as well as by fabrication parameters. However, if the gain ratios are equal, then the denominator of equation (1) is simply 1+(1) 0.5 , or 2. 
     At this point the current limiter  110  is introduced into the circuit and the relationship between current and the trip point V T  is explained. Assuming that both the N- and P-channel transistors  120  are in saturation, the well known saturated current equation for a MOS transistor is given as: 
       I   D =( k/ 2)*(V GS −V TH ) 2   (2) 
     Where, I D  is the current at the drain, k is the gain factor, V GS  is the gate-source voltage and V TH  is the threshold voltage. 
     For a current limiter  110  in series with and directly connected to the P-channel transistor, as depicted in FIGS. 4A and 4B, the N-channel transistor is the relevant device for determining the new trip point because the N-channel transistor is without a current limitation between the output node  130  and the lower rail  140 . The P-channel device is not relevant in determining the new trip point for FIGS. 4A and 4B because the current limiter  110  is in series with the P-channel transistor and both the current limiter  110  and P-channel device are located between the upper rail V DD    150  and the output node  130 . Thus, the P-channel device&#39;s contribution to the new trip point is regulated by the current limiter  110 . The current for the N-channel transistor is expressed as follows. 
     
       
           I   N   =I   LIM =( k   N /2)(V IN −V TN ) 2   (3) 
       
     
     Where I N  is equal to the current through the N-channel transistor. I LIM  is the current provided by the current limiter  110 . At the trip point I N =I LIM . k N  is the gain factor of the N-channel transistor, V IN  is the input voltage and V TN  is the threshold voltage of the N-channel device. Rearranging terms, and identifying V IN  as the desired trip point, we have: 
     
       
         V T =V IN =((2 *   LIM )/ k   N ) 0.5 +V TN   (4) 
       
     
     Thus, if the current I LIM  is limited to a small amount, then: 
     
       
         V T ≈V TN   (5) 
       
     
     This equation (5) is reflected in FIG. 6A, where the trip point is shifted to V T , which is approximately VTN, by means of the current limiter  110  in series with the P-channel transistor. 
     In the case of the current limiter  110  in series with and directly connected to the N-channel transistor, as depicted in FIGS. 4C and 4D, the equations are as follows: 
     
       
           I   P   =I   LIM =( k   P /2)(V IN −V DD −|V TP |) 2   (6) 
       
     
     Where I P  is equal to the current through the P-channel transistor. I LIM  is the current provided by the current limiter  110 . At the trip point I P =I LIM . k P  is the gain factor of the P-channel transistor, V IN  is the input voltage and V TP  is the threshold voltage of the P-channel device. Rearranging terms, and once again identifying V IN  as the desired trip point, we have: 
      V T =V IN =((2 *I   LIM )/ k   P ) 0.5 +V DD −|V TP |  (7) 
     Thus, if the current I LIM  is limited to a small amount then: 
     
       
         V T ≈V DD −|V TP |  (8) 
       
     
     This equation (8) is reflected in FIG. 6B, where the trip point is shifted to V T″  which is approximately V DD −|V TP | by means of the current limiter  110  in series with the N-channel transistor. 
     FIG. 7 illustrates the operation of the present invention from a timing diagram perspective. CLK is the master clock and is the input parameter to clock generator  101  as shown in FIG.  4 A. C 1  is the output of clock generator  101 . Note that the trip point for C 1  has shifted to V TN  because of the current limiter  110  in series with the P-channel device. CLK is also the input parameter to clock generator  103  as depicted in FIG. 4C.  C 2    is the output of clock generator  103 . Note that the trip point for  C 2    has shifted to V DD −|V TP | because of the current limiter  110  in series with the N-channel device. 
     Turning next to the clocks generated by the complementary master clock  CLK .  CLK  is the input parameter to clock generator  102  as shown in FIG.  4 B. C 2  is the output of clock generator  102 . Note that the trip point for C 2  has shifted to V TN  because of the current limiter  110  in series with the P-channel device. Further note that C 1  and C 2  are non-overlapping clocks for an active high signal.  CLK  is also the input parameter to clock generator  104  as depicted in FIG. 4D.  C 1    is the output of clock generator  102 . Note that the trip point for  C 1    has shifted to V DD −|V TP | because of the current limiter  110  in series with the N-channel device. Further note that  C 1    and  C 2    are non-overlapping clocks for an active low signal. 
     Referring to FIG. 3, C 1  and  C 1    are applied to the gating transistor pair  10 . C 2  and  C 2    are applied to the gating transistor pair  30 . Thus, by having non-overlapping clocks at the gating transistor pairs  10  and  30 , the two discrete latching process of the master-slave device is preserved because the non-overlapping clocks ensure that the incoming data D must first be latched into the master latch before it can be latched into the slave latch. 
     Referring to FIGS. 8A and 8B, where like numerals represent like elements, an alternative embodiment of the present invention is shown which relies on a single master clock CLK, as opposed to the complementary signals CLK &amp;  CLK , to produce the non-overlapping synthesized clocks: C 1 ,  C 1   , C 2  &amp;  C 2   . In FIG. 8A, the clock generators  101  and  104 , with current limiters  110  and the two transistor inverters  120 , are as previously described. The clock generator  104  is connected to the output of clock generator  101  which is the derived clock C 1 . The output of clock generator  104  is  C 1   . 
     Similarly, in FIG. 8B, clock generator  102  is connected to the  C 2    output of clock generator  103 . Thus the output of clock generator  102  is the complement of  C 2   , which is the derived non-overlapping clock C 2 . Therefore, a more robust, yet simpler and more flexible approach is to derive C 1 ,  C 1   , C 2  and  C 2    from a common or single master clock CLK. 
     Referring to FIG. 9, the timing diagrams of the single CLK input and the non-overlapping clock outputs of the clock generators illustrated in FIGS. 8A and 8B are shown. Thus, the result is the same as illustrated in FIG. 7, where C 1 ,  C 1   , C 2  and  C 2    are derived from a combination of CLK and  CLK . 
     The invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention.