Abstract:
Disclosed herein is a storage device including: a communication execution unit configured to be capable of controlling an operation state between a communication-enabled state in which data communication is possible and a pause state in which data communication is impossible; a buffer configured to store data transmitted and received by the communication execution unit; a memory configured to be capable of storing data; a memory controller configured to carry out data input and output between the memory and the buffer; and a communication controller configured to make the communication execution unit operate if data communication is carried out, and make the communication execution unit take a pause if data communication is not carried out. The communication controller switches the operation state of the communication execution unit between the communication-enabled state and the pause state in data communication depending on a data processing state of the buffer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a storage device such as a memory card and a storage system. 
         [0003]    2. Description of the Related Art 
         [0004]    The memory card is removably loaded in electronic apparatus and can store data relating to data processing of the electronic apparatus. 
         [0005]    For example, when being loaded in a camera, the memory card can store data of images captured by the camera, and so forth. 
         [0006]    As the interface between such a memory card and electronic apparatus, PCI Express is available (refer to Japanese Patent Laid-Open No. 2006-221453 and U.S. Patent Application Publication No. 2008/0288798). 
         [0007]    PCI Express is to transfer data at high speed by serial data communication and is suitable for data transfer of an image composed of a large number of pixels and a moving image. 
       SUMMARY OF THE INVENTION 
       [0008]    However, in PCI Express, a clock signal of a high frequency is used in order to realize the high-speed serial data communication. 
         [0009]    Therefore, possibly the power consumption will become higher if a serial data communication system such as PCI Express is used for the interface. 
         [0010]    For example if PCI Express is employed for the interface with a memory card in mobile apparatus driven by a battery, possibly influence will be given to the continuous use time of the mobile apparatus and the life of the battery. 
         [0011]    As just described, the interface of low power consumption is demanded in the storage device such as a memory card. 
         [0012]    According to a first embodiment of the present invention, there is provided a storage device including a communication execution unit configured to be capable of controlling an operation state between a communication-enabled state in which data communication is possible and a pause state in which data communication is impossible, and a buffer configured to store data transmitted and received by the communication execution unit. The storage device further includes a memory configured to be capable of storing data, a memory controller configured to carry out data input and output between the memory and the buffer, and a communication controller configured to make the communication execution unit operate if data communication is carried out, and make the communication execution unit take a pause if data communication is not carried out. The communication controller switches the operation state of the communication execution unit between the communication-enabled state and the pause state in data communication depending on the data processing state of the buffer. 
         [0013]    In the storage device according to the first embodiment of the present invention, the communication execution unit to carry out data communication switches between the communication-enabled state and the pause state in data communication depending on the data processing state of the buffer. The switching to the pause state reduces the power consumption of the communication execution unit in the data communication. 
         [0014]    According to a second embodiment of the present invention, there is provided a storage system including electronic apparatus that executes data processing and a storage device that is removably loaded in the electronic apparatus and stores data relating to data processing of the electronic apparatus. The storage device includes a communication execution unit configured to be capable of controlling an operation state between a communication-enabled state in which data communication with the electronic apparatus is possible and a pause state in which data communication is impossible, and a buffer configured to store data transmitted and received by the communication execution unit to and from the electronic apparatus. The storage device further includes a memory configured to be capable of storing data, a memory controller configured to carry out data input and output between the memory and the buffer, and a communication controller configured to make the communication execution unit operate if data communication with the electronic apparatus is carried out, and make the communication execution unit take a pause if data communication is not carried out. The communication controller switches the operation state of the communication execution unit between the communication-enabled state and the pause state in data communication with the electronic apparatus depending on the data processing state of the buffer. 
         [0015]    The embodiments of the present invention can realize an interface of low power consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a block diagram of the hardware of a memory card according to an embodiment of the present invention; 
           [0017]      FIG. 2  is a schematic configuration diagram of a camera system in which the memory card of  FIG. 1  is used; 
           [0018]      FIG. 3  is an explanatory diagram of the communication system of PCI Express; 
           [0019]      FIG. 4  is an explanatory diagram of the communication protocol of PCI Express; 
           [0020]      FIG. 5  is an explanatory diagram of the communication packet of PCI Express; 
           [0021]      FIG. 6  is a state transition diagram of a component of PCI Express; 
           [0022]      FIG. 7  is one example of a communication sequence chart of switching of the operation state from L0 to L1; 
           [0023]      FIG. 8  is one example of a communication sequence chart of switching of the operation state from L0 to L0s; 
           [0024]      FIG. 9  is one example of a communication sequence chart of switching of the operation state from L1 to L0; 
           [0025]      FIG. 10  is one example of a communication sequence chart of switching of the operation state from L0s to L0; 
           [0026]      FIG. 11  is an explanatory diagram of the memory space relating to control of the operation state dependent on the state of a buffer in a write access period; 
           [0027]      FIG. 12  is a flowchart of state control in the write access period; 
           [0028]      FIG. 13  is an explanatory diagram showing one example of time change in the amount of not-yet-processed write data in the buffer in the write access period; 
           [0029]      FIG. 14  is an explanatory diagram of the memory space relating to control of the operation state dependent on the state of the buffer in a read access period; 
           [0030]      FIG. 15  is a flowchart of state control in the read access period; 
           [0031]      FIG. 16  is an explanatory diagram showing one example of time change in the amount of not-yet-processed read data in the buffer in the read access period; 
           [0032]      FIG. 17  is a block diagram of the hardware of a memory card according to a first modification example; and 
           [0033]      FIG. 18  is a block diagram of the hardware of a memory card according to a second modification example. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0034]    An embodiment of the present invention will be described below in association with the drawings. The order of the description is as follows.
   1. Configurations of Memory Card and Camera Device (Host Apparatus)   2. Communication System of PCI Express   3. Power Supply Management of PCI Express   4. Power Supply Management in Period of Write Access by Host Apparatus   5. Power Supply Management in Period of Read Access by Host Apparatus   
 
       [Configurations of Memory Card  1  and Camera Device  2 ] 
       [0040]      FIG. 1  is a block diagram of the hardware level of a memory card  1  according to the embodiment of the present invention. 
         [0041]    The memory card  1  of  FIG. 1  has a card interface unit (C_I/F)  11 , a control register (REG)  12 , a buffer (BUF)  13 , a memory controller (M_CTRL)  14 , and a non-volatile memory (NV_MEM)  15 . 
         [0042]    The memory card  1  communicates with electronic apparatus in accordance with the standards of PCI Express. 
         [0043]      FIG. 2  is a schematic configuration diagram of a camera system  3  in which the memory card  1  of  FIG. 1  is used. 
         [0044]    The camera system  3  of  FIG. 2  has the memory card  1  of  FIG. 1  and a camera device  2  as host apparatus. 
         [0045]    The camera device  2  of  FIG. 2  has an imaging unit (CAM)  21 , an operating unit (KEY)  22 , a display unit (DISP)  23 , a CPU (Central Processing Unit)  24 , a memory (MEM)  25 , a host interface unit (H_I/F)  26 , and a system bus  27  to connect these units to each other. 
         [0046]    The camera device  2  is driven by a battery (BAT)  28 . 
         [0047]    The imaging unit  21  has a CMOS (Complementary Metal Oxide Semiconductor) sensor, a CCD (Charge Coupled Device Image Sensor), or the like. 
         [0048]    The imaging unit  21  creates image data of a moving image or a still image and outputs a signal including the image data to the CPU  24 . 
         [0049]    The operating unit  22  has an imaging button, arrow keys, etc. 
         [0050]    The operating unit  22  outputs a signal corresponding to the operated key to the CPU  24 . 
         [0051]    The display unit  23  has a TFT (Thin Film Transistor) display, an organic EL (Electro-Luminescence) display, or the like. 
         [0052]    A video signal is input to the display unit  23  from the CPU  24 , so that the display unit  23  displays the image of the video signal. 
         [0053]    The memory  25  stores a program executed by the CPU  24  and data. 
         [0054]    The CPU  24  reads the program stored in the memory  25  to execute the program. 
         [0055]    Thereby, the controller of the camera device  2  is realized in the CPU  24 . 
         [0056]    The controller manages and controls the imaging unit  21 , the display unit  23 , the host interface unit  26 , and so forth. 
         [0057]    The host interface unit  26  has a slot compliant with the connection standards of PCI Express. 
         [0058]    The memory card  1  of  FIG. 1  is removably loaded in this slot. 
         [0059]    The CPU  24  in the camera device  2  carries out imaging of e.g. a still image or a moving image and writes the image data of the obtained image to the memory card  1 . At this time, the CPU  24  in the camera device  2  makes write access to the memory card  1 . 
         [0060]    The CPU  24  may make the write access to the memory card  1  in units of a predetermined amount of data. 
         [0061]    Furthermore, the camera device  2  reads image data from the memory card  1  and displays an image on the display unit  23  for example. At this time, the CPU  24  in the camera device  2  makes read access to the memory card  1 . 
         [0062]    The CPU  24  may make the read access to the memory card  1  in units of a predetermined amount of data. 
         [0063]    The non-volatile memory  15  in  FIG. 1  is a non-volatile semiconductor memory such as a NAND flash memory or a NOR flash memory. 
         [0064]    The non-volatile memory  15  stores write data of the camera device  2  and so forth. 
         [0065]    The buffer  13  is a semiconductor memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory). 
         [0066]    The buffer  13  temporarily stores write data to be written to the non-volatile memory  15  or read data read out from the non-volatile memory  15 . 
         [0067]    The memory controller  14  is connected to the non-volatile memory  15 , the buffer  13 , and the card interface unit  11 . 
         [0068]    When being instructed to store write data by the card interface unit  11 , the memory controller  14  reads the write data from the buffer  13  and stores the write data in the non-volatile memory  15 . 
         [0069]    When being instructed to read out data by the card interface unit  11 , the memory controller  14  reads the specified read data from the non-volatile memory  15  and stores the read data in the buffer  13 . 
         [0070]    To the control register  12 , a command is written by the host apparatus via the card interface unit  11 . 
         [0071]    The card interface unit  11  communicates with the host apparatus by a communication system compliant with the communication standards of PCI Express. 
         [0072]    The card interface unit  11  is connected to the control register  12 , the buffer  13 , and the memory controller  14 . 
         [0073]    The card interface unit  11  manages the processing of the whole of the memory card  1  and executes processing corresponding to the command written to the control register  12 . 
         [0074]    For example, when a write command is written to the control register  12 , the card interface unit  11  writes, to the buffer  13 , write data received from the host apparatus. 
         [0075]    Furthermore, the card interface unit  11  outputs, to the memory controller  14 , a signal to instruct the memory controller  14  to store the write data. 
         [0076]    In addition, for example when a read command is written to the control register  12 , the card interface unit  11  outputs, to the memory controller  14 , a signal to instruct the memory controller  14  to read out data. 
         [0077]    The card interface unit  11  reads read data from the buffer  13  to output the read data to the host apparatus. 
       [Communication System of PCI Express] 
       [0078]    The communication system based on PCI Express will be described below. 
         [0079]      FIG. 3  shows a first component  31  and a second component  32  communicating with each other by PCI Express. 
         [0080]    The first component  31  corresponds to e.g. the camera device  2  as the host apparatus in the example of  FIG. 1  and  FIG. 2 . 
         [0081]    The second component  32  corresponds to the card interface unit  11  of the memory card  1 . 
         [0082]    Data and a clock signal are input to the first component  31  and the second component  32 . 
         [0083]    The clock signal can be generated by a clock generating circuit (not shown). 
         [0084]    The first component  31  and the second component  32  are connected to each other by e.g. two pairs of differential transmission lines (differential signal line pairs). These two pairs of differential transmission lines are called lane. 
         [0085]    In PCI Express, it is also possible to connect two components  31  and  32  to each other by plural lanes. 
         [0086]    For example, in transmission of data from the first component  31  to the second component  32 , the first component  31  outputs a packet of serial data to the second component  32  via one differential transmission line pair. 
         [0087]    The second component  32  receives the packet from this one differential transmission line pair to acquire the data. 
         [0088]    The second component  32  transmits a packet of serial data to the first component  31  via the other differential transmission line pair. The clock signal is superimposed on the serial data. 
         [0089]      FIG. 4  is an explanatory diagram of a communication protocol realized in two components  31  and  32  of  FIG. 3  for data transmission by PCI Express. 
         [0090]    In  FIG. 4 , as functions realized in the first component  31 , a software layer  33 , a transaction layer  34 , a data link layer  35 , a physical layer  36 , and a mechanical layer  37  are represented. 
         [0091]    Also in the second component  32 , the software layer  33 , the transaction layer  34 , the data link layer  35 , the physical layer  36 , and the mechanical layer  37  are realized. 
         [0092]      FIG. 5  is an explanatory diagram of the data structure of a packet transmitted/received between two components  31  and  32  of  FIG. 4 . 
         [0093]    The packet of  FIG. 5  is configured by framing character data  41 , sequence number data  42 , header data  43 , actual data  44 , ECRC data  45 , LCRC data  46 , and framing character data  47 . 
         [0094]    The software layer  33  in  FIG. 4  utilizes data transmission by PCI Express. 
         [0095]    The software layer  33  is e.g. a photographing controller of a camera to write a captured still image or moving image to the memory card  1 . 
         [0096]    Upon generation of the actual data  44  desired to be communicated, the software layer  33  starts transaction. 
         [0097]    The transaction layer  34  performs packetization by adding a header and ECRC to the actual data  44  input from the software layer  33 , to create a transaction layer packet (TLP). 
         [0098]    The TLP is transmitted to the other transaction layer  34 . 
         [0099]    The other transaction layer  34  that has received the TLP detects an error in the actual data  44  by using the ECRC. 
         [0100]    The data link layer  35  adds the sequence number data  42  and the LCRC data  46  to the TLP input from the transaction layer  34 , to create a data link layer packet (DLLP). 
         [0101]    The DLLP is transmitted to the other data link layer  35 . 
         [0102]    The other data link layer  35  detects an error in the TLP by using the LCRC data  46 . 
         [0103]    Furthermore, if the sequence number data  42  received by the other data link layer  35  is not in the predetermined order, the data link layer  35  makes the other data link layer  35  retransmit a DLLP of this sequence number data  42  if an error in the TLP is detected. 
         [0104]    The physical layer  36  adds framing characters to the DLLP created by the data link layer  35 , to create a physical layer packet (PLP) in  FIG. 5 . 
         [0105]    The PLP is transmitted to the other physical layer  36 . 
         [0106]    Furthermore, the physical layer  36  transmits/receives a control signal such as an ordered set to/from the other physical layer  36  according to need. Examples of the ordered set include an electrical idle ordered set. 
         [0107]    In the case of rendering the transmission line electrical idle, first the physical layer  36  transmits the electrical idle ordered set to the other physical layer  36 . Thereafter, the physical layer  36  sets the differential transmission line pair for sending to the state corresponding to the electrical idle ordered set, to render the transmission line electrical idle. Thereby, the communication state of the component is set to the pause state. 
         [0108]    The physical layer  36  has e.g. plural input/output ports to which the respective differential transmission line pairs are connected, analog buffers of the respective input/output ports, a SerDes circuit for an 8b/10b codec, and so forth. 
         [0109]    The SerDes circuit converts parallel data to be transmitted to serial data. Furthermore, the SerDes circuit converts received serial data to parallel data. 
         [0110]    The physical layer  36  transmits, to the other physical layer  36 , the physical layer packet in  FIG. 5  created by the physical layer  36 , an ordered set, and so forth. 
         [0111]    For example, the physical layer  36  transmits the data of the physical layer packet in  FIG. 5  from the left-side data in sequence. 
         [0112]    The data of the physical layer packet in  FIG. 5  is transmitted as a signal of serial data from the differential transmission line pair for sending. 
         [0113]    The mechanical layer  37  has a connector (not shown) and so forth. 
       [Power Supply Management of PCI Express] 
       [0114]      FIG. 6  is a transition diagram of the operation state of each component of  FIG. 3 . 
         [0115]    Examples of the operation state of the component of PCI Express include an L0 state, an L0s state, and an L1 state. 
         [0116]    The components  31  and  32  communicating with each other by PCI Express switch the operation state by active state power management (ASPM). 
         [0117]    The L0 state is the communication-enabled state in which data communication can be carried out. 
         [0118]    The L0s state and the L1 state are the standby state (pause state), and the L1 state is the state of a deeper pause compared with the L0s state. 
         [0119]    In the L0s state, the link between the components by plural lanes is in the electrically-idle state. A clock signal is input to the respective components, and a PLL circuit of the SerDes circuit and so forth is fed with power and operates. 
         [0120]    The time of restoration from the L0s state to the L0 state is e.g. several hundreds of nanoseconds to several microseconds. 
         [0121]    In the L1 state, the link between the components is in the electrically-idle state. In the L1 state, the power feed is not stopped. 
         [0122]    The time of restoration from the L1 state to the L0 state is e.g. several microseconds to several tens of microseconds. 
         [0123]    In the restoration from the L1 state to the L0 state, the component becomes the recovery state from the L1 state and then is restored to the L0 state from the recovery state. 
         [0000]    [Switching Operation from L0 to L1] 
         [0124]    The components  31  and  32  control the operation state depending on the packet reception status and so forth. 
         [0125]      FIG. 7  is one example of a sequence chart of switching of the operation state of the host apparatus ( 2 ) and the memory card  1  from L0 to L1. 
         [0126]    In the state switching from L0 to L1, the transaction layer  34  of the memory card  1  stops transmission of a new packet, and the data link layer  35  repeatedly transmits a request for the state switching from L0 to L1 (step ST 1 ). 
         [0127]    Upon receiving the switching request, the data link layer  35  of the host apparatus ( 2 ) transmits a switching acknowledgement (ACK) or a non-acknowledgement (NAK) depending on its own communication state (step ST 2 ). 
         [0128]    Furthermore, if the switching acknowledgement is transmitted, the transaction layer  34  prohibits transmission of a new packet. 
         [0129]    If the switching acknowledgement is received, the data link layer  35  of the memory card  1  stops, and the physical layer  36  transmits an electrical idle ordered set (step ST 3 ). 
         [0130]    Upon receiving the electrical idle ordered set, the physical layer  36  of the host apparatus ( 2 ) stops the communication. 
         [0131]    Furthermore, the physical layer  36  transmits an electrical idle ordered set (step ST 4 ). 
         [0132]    Thereby, the operation state of two components  31  and  32  is switched from L0 to L1. 
         [0133]    In the pause state of L1, the physical layer  36 , the data link layer  35 , and the transaction layer  34  stop. 
         [0000]    [Switching Operation from L0 to L0s] 
         [0134]      FIG. 8  is one example of a sequence chart of switching of the operation state of the host apparatus ( 2 ) and the memory card  1  from L0 to L0s. 
         [0135]    In the state switching from L0 to L0s, the physical layer  36  of the memory card  1  transmits an electrical idle ordered set (step ST 11 ) and enters the pause state. 
         [0136]    Upon receiving the electrical idle ordered set, the physical layer  36  of the component as the host apparatus ( 2 ) enters the pause state. 
         [0137]    In the pause state of L0s, only the physical layer  36  stops. 
         [0138]    The components  31  and  32  of PCI Express need to be switched from the L0 state to the L0s state if an idle period for seven microseconds or longer has occurred. 
         [0139]    Therefore, the respective components  31  and  32  have a timer (not shown) and measure the idle period by this timer. 
         [0140]    In contrast, in the standards of PCI Express, the implementer can decide the condition for switching to the L1 state. 
         [0141]    Thus, the respective components  31  and  32  do not need to use the timer for the switching to the L1 state. 
         [0000]    [Switching Operation from L1 to L0] 
         [0142]      FIG. 9  is one example of a sequence chart of switching of the operation state of the host apparatus ( 2 ) and the memory card  1  from L1 to L0. 
         [0143]    In the state switching from L1 to L0, the physical layer  36  inactivates the electrical idle. 
         [0144]    After the inactivation of the electrical idle, one component transmits a TS 1  ordered set to the other component a predetermined number of times and transmits a TS 2  ordered set to the other component a predetermined number of times (steps ST 21  and ST 23 ). 
         [0145]    The other component also transmits the TS 1  ordered set to one component a predetermined number of times and transmits the TS 2  ordered set to one component a predetermined number of times (steps ST 22  and ST 24 ). 
         [0146]    Specifically, after the inactivation of the electrical idle, each component starts the transmission of the TS 1  ordered set. Each component continues the transmission of the TS 1  ordered set until receiving eight TS 1  or TS 2  ordered sets consecutively. 
         [0147]    Upon receiving eight TS 1  or TS 2  ordered sets consecutively, the operation of each component is switched to transmission of the TS 2  ordered set. Each component continues the transmission of the TS 2  ordered set until receiving eight TS 2  ordered sets consecutively and ending the transmission of 16 TS 2  ordered sets after reception of one TS 2  ordered set. 
         [0148]    By the TS 1  ordered set and the TS 2  ordered set, the components exchange a COM symbol, a link symbol, a lane symbol, data for training, etc. 
         [0149]    Next, upon ending the transmission of the TS 2  ordered set, one component transmits a packet of idle data to the other component a predetermined number of times (step ST 25 ). 
         [0150]    The packet of idle data is transmitted to the data link layer  35  and the transaction layer  34  of the other component by the data link layer  35  or the transaction layer  34  of one component. 
         [0151]    All of the data of this packet have to be zero. 
         [0152]    The other component also transmits a packet of idle data to one component a predetermined number of times, upon ending the transmission of the TS 2  ordered set (step ST 26 ). 
         [0153]    Specifically, each of the components that have ended the transmission of the TS 2  ordered set starts the transmission of the idle data. Each component continues the transmission of the idle data until receiving eight idle data consecutively and ending the transmission of 16 idle data after reception of one idle data. 
         [0154]    Thereby, the operation state of two components  31  and  32  is restored from L1 to L0 via the recovery state. 
         [0000]    [Switching Operation from L0s to L0] 
         [0155]      FIG. 10  is one example of a sequence chart of switching of the operation state of the host apparatus ( 2 ) and the memory card  1  from L0s to L0. 
         [0156]    In the pause state of L0s, only the physical layer  36  stops. 
         [0157]    In the state switching from L0s to L0, the physical layer  36  of one component transmits predetermined ordered sets (FTS ordered set and SKP ordered set) after being restored from the stop state (step ST 31 ). 
         [0158]    Upon receiving these ordered sets, the physical layer  36  of the other component is restored from the pause state. 
       [Access to Memory Card  1  by Host Apparatus] 
       [0159]    Descriptions will be made below about the operation of the memory card  1  when the camera device  2  as the host apparatus makes write access or read access to the memory card  1 . 
         [0160]    In the write access, the card interface unit  11  receives data from the host apparatus and writes the data to the buffer  13 . The memory controller  14  reads data from the buffer  13  and writes the data to the non-volatile memory  15 . 
         [0161]    In the read access, the memory controller  14  reads data from the non-volatile memory  15  and writes the data to the buffer  13 . The card interface unit  11  reads data from the buffer  13  and transmits the data to the host apparatus. 
         [0162]    The card interface unit  11  enters the standby state (e.g. L1) in the write access or the read access. 
       [Power Supply Management in Period of Write Access by Host Apparatus] 
       [0163]      FIG. 11  is an explanatory diagram of the memory space of the buffer  13  in  FIG. 1 . 
         [0164]    As shown in  FIG. 11 , for pause control in the write access, a write upper-limit threshold (Th_wfull) and a write lower-limit threshold (Th_wemp) are set relative to the total buffer amount (Buf) of the buffer  13 . 
         [0165]    The write upper-limit threshold and the write lower-limit threshold may be stored in e.g. the non-volatile memory  15 . 
         [0166]    The write upper-limit threshold is the upper-limit threshold at which control to take a pause in data writing to the buffer  13  by the card interface unit  11  is started. 
         [0167]    The card interface unit  11  shifts to the standby state (e.g. L1) when the amount of not-yet-processed write data in the buffer  13  surpasses this write upper-limit threshold. 
         [0168]    The write lower-limit threshold is the lower-limit threshold at which control to restart the data writing to the buffer  13  by the card interface unit  11  is started. 
         [0169]    The card interface unit  11  is restored from the standby state when the amount of not-yet-processed write data in the buffer  13  becomes smaller than this write lower-limit threshold. 
         [0170]    In the write access, the card interface unit  11  monitors the remaining storage capacity of the buffer  13  and switches its own operation state based on the write upper-limit threshold and the write lower-limit threshold. 
         [0171]    For example, when the amount of not-yet-processed write data in the buffer  13  surpasses the write upper-limit threshold in the write access, the card interface unit  11  sets its own operation state to the standby state (e.g. L0s) until the amount of not-yet-processed data becomes smaller than the write lower-limit threshold. 
         [0172]      FIG. 12  is a flowchart of the state control carried out by the card interface unit  11  in  FIG. 1  during the write access. 
         [0173]    Upon writing of a write command to the control register  12  by the host apparatus, the memory card  1  starts processing of writing to the non-volatile memory  15 . 
         [0174]    The card interface unit  11  receives packetized write data from the host apparatus (step ST 41 ). 
         [0175]    The card interface unit  11  writes the received write data to the buffer  13 . 
         [0176]    Upon receiving the packetized write data, the card interface unit  11  determines whether or not reception of all of the write data in this one time of write access has been completed (step ST 42 ). 
         [0177]    If the reception of all of the write data has been completed, the card interface unit  11  carries out control to switch its own operation state from the L0 state to the standby state (step ST 43 ). 
         [0178]    For example, in the case of the switching to the L1 state, the card interface unit  11  executes the communication processing of  FIG. 7  with the component of the host apparatus and switches its own operation state from the L0 state to the L1 state. 
         [0179]    In the case of the switching to the L0s state, the card interface unit  11  executes the communication processing of  FIG. 8  with the component of the host apparatus and switches its own operation state from the L0 state to the L0s state. 
         [0180]    Thereafter, the card interface unit  11  in the standby state waits for the end of the operation of writing to the non-volatile memory  15 , and determines that the write processing is ended (step ST 44 ). 
         [0181]    The card interface unit  11  may end the write processing after being restored to L0. 
         [0182]    If it is determined by the card interface unit  11  in the step ST 42  that the reception of all of the write data has not been completed, the card interface unit  11  determines whether or not the amount of not-yet-processed write data in the buffer  13  is equal to or larger than the write upper-limit threshold (step ST 45 ). 
         [0183]    Specifically, for example, the card interface unit  11  reads the free space of the buffer  13  and subtracts the free space from the total buffer amount of the buffer  13 , to determine whether or not the capacity obtained by the subtraction is equal to or larger than the write upper-limit threshold. 
         [0184]    If the amount of not-yet-processed write data in the buffer  13  is not equal to or larger than the write upper-limit threshold, the card interface unit  11  enters the state of waiting for reception of the next write data (step ST 41 ). 
         [0185]    If the amount of not-yet-processed write data in the buffer  13  is equal to or larger than the write upper-limit threshold, the card interface unit  11  carries out control to switch its own operation state from the L0 state to the standby state (step ST 46 ). 
         [0186]    For example, in the case of the switching to the L0s state, the card interface unit  11  executes the communication processing of  FIG. 8  with the component of the host apparatus and switches its own operation state from the L0 state to the L0s state. 
         [0187]    In the case of the switching to the L1 state, the card interface unit  11  executes the communication processing of  FIG. 7  with the component of the host apparatus and switches its own operation state from the L0 state to the L1 state. 
         [0188]    Thereafter, the card interface unit  11  monitors the buffer  13 . The card interface unit  11  repeatedly determines whether or not the amount of not-yet-processed write data in the buffer  13  has become equal to or smaller than the write lower-limit threshold (step ST 47 ). 
         [0189]    If the amount of not-yet-processed write data in the buffer  13  has become equal to or smaller than the write lower-limit threshold, the card interface unit  11  carries out control to switch its own operation state from the standby state to the communication-enabled L0 state (step ST 48 ). 
         [0190]    Specifically, the card interface unit  11  executes the communication processing of  FIG. 9  or  FIG. 10  with the component of the host apparatus and switches its own operation state from the standby state to the L0 state. 
         [0191]    If the card interface unit  11  returns to the communication-enabled L0 state, it is in the state of waiting for reception of the next write data. 
         [0192]      FIG. 13  is an explanatory diagram showing one example of time change in the amount of not-yet-processed write data in the buffer  13  under the control of  FIG. 12 . 
         [0193]    In  FIG. 13 , the abscissa indicates the time and the ordinate indicates the amount of not-yet-processed write data in the buffer  13 . 
         [0194]    Under the control of  FIG. 12 , the amount of not-yet-processed write data in the buffer  13  in one time of write access rises from zero at a writing start time T 0  to the write upper-limit threshold. 
         [0195]    This is because the speed of the communication between the card interface unit  11  and the host apparatus is higher than the speed of reading of write data from the buffer  13  by the memory controller  14  for writing of the data to the non-volatile memory  15 . 
         [0196]    In general, the speed of data writing to a flash memory is not high. 
         [0197]    If the amount of not-yet-processed write data in the buffer  13  reaches the write upper-limit threshold at a time T 1 , the card interface unit  11  switches from the operating state (L0) to the standby state at a time T 2  after transition latency. 
         [0198]    Even after the switching of the card interface unit  11  to the standby state, the memory controller  14  writes the write data in the buffer  13  to the non-volatile memory  15 . 
         [0199]    Thus, the amount of not-yet-processed write data in the buffer  13  begins to decrease. 
         [0200]    Furthermore, the card interface unit  11  switched to the standby state monitors the buffer  13 . 
         [0201]    If the amount of not-yet-processed write data in the buffer  13  becomes equal to or smaller than the write lower-limit threshold at a time T 3 , the card interface unit  11  switches to the operating state (L0) at a time T 4  after return latency. 
         [0202]    The card interface unit  11  switched to the operating state restarts reception of write data from the host apparatus at a time T 5  after data transfer latency and writes the data to the buffer  13 . 
         [0203]    Thereby, the amount of not-yet-processed write data in the buffer  13  begins to rise again. 
         [0204]    In this manner, the card interface unit  11  switches between the operating state and the standby state in one time of write access. 
         [0205]    The amount of not-yet-processed write data in the buffer  13  increases and decreases on the basis of the write upper-limit threshold and the write lower-limit threshold. 
         [0206]    Therefore, the buffer  13  does not get full with not-yet-processed write data. 
         [0207]    The provision of the write upper-limit threshold is because of implementation reasons. 
         [0208]    For example, it is preferable to provide this write upper-limit threshold if an implementation problem occurs, such as impossibility of transition to the standby state during the period when the buffer  13  is full with not-yet-processed write data and data transfer from the card interface unit  11  is stopped. 
         [0209]    In contrast, the write upper-limit threshold does not have to be provided if the state in which the buffer  13  is full with not-yet-processed write data causes no implementation problem. 
         [0210]    The memory controller  14  processes write data in the buffer  13  in one time of write access. 
         [0211]    However, due to the control based on the write lower-limit threshold, exhaustion of not-yet-processed write data in the buffer  13  does not occur. 
         [0212]    Furthermore, the empty state of the buffer  13  does not occur also in the period until return from the standby state to L0. 
         [0213]    As a result, the memory controller  14  can process write data in the buffer  13  continuously during one time of write access. 
       [Power Supply Management in Period of Read Access by Host Apparatus] 
       [0214]      FIG. 14  is an explanatory diagram of the memory space of the buffer  13  in  FIG. 1 . 
         [0215]    As shown in  FIG. 14 , for pause control in the read access, a read upper-limit threshold (Th_rfull) and a read lower-limit threshold (Th_remp) are set relative to the total buffer amount (Buf) of the buffer  13 . 
         [0216]    The read upper-limit threshold and the read lower-limit threshold may be stored in e.g. the non-volatile memory  15 . 
         [0217]    The read lower-limit threshold is the lower-limit threshold at which control to take a pause in data reading from the buffer  13  by the card interface unit  11  is started. 
         [0218]    The card interface unit  11  shifts to the standby state (e.g. L1) when the amount of not-yet-processed read data in the buffer  13  becomes smaller than this read lower-limit threshold. 
         [0219]    The read upper-limit threshold is the upper-limit threshold at which control to restart the data reading from the buffer  13  by the card interface unit  11  is started. 
         [0220]    The card interface unit  11  is restored from the standby state when the amount of not-yet-processed read data in the buffer  13  surpasses this read upper-limit threshold. 
         [0221]    In the read access, the card interface unit  11  monitors the remaining storage capacity of the buffer  13  and switches its own operation state based on the read upper-limit threshold and the read lower-limit threshold. 
         [0222]    For example, when the amount of not-yet-processed read data in the buffer  13  becomes smaller than the read lower-limit threshold in the read access, the card interface unit  11  sets its own operation state to the standby state (e.g. L0s) until the amount of not-yet-processed data surpasses the read upper-limit threshold. 
         [0223]      FIG. 15  is a flowchart of the state control carried out by the card interface unit  11  in  FIG. 1  during the write access. 
         [0224]    Upon writing of a read command to the control register  12  by the host apparatus, the memory card  1  starts processing of reading from the non-volatile memory  15 . 
         [0225]    The card interface unit  11  instructs the memory controller  14  to perform reading. 
         [0226]    The memory controller  14  reads out data from the non-volatile memory  15  and writes the data to the buffer  13 . 
         [0227]    The card interface unit  11  determines whether or not the amount of remaining data to be transferred is equal to or larger than a predetermined value (Th_remain) (step ST 51 ). 
         [0228]    As this predetermined value, e.g. a value larger than the read upper-limit threshold is employed. 
         [0229]    Making the determination relating to this value can prevent the occurrence of the deadlock state in which the card interface unit  11  waits for accumulation of data whose amount is equal to or larger than the read upper-limit threshold although only data whose amount is smaller than the read upper-limit threshold remains. 
         [0230]    If the amount of remaining data to be transferred is equal to or larger than the predetermined value, the card interface unit  11  starts transition to the standby state (step ST 52 ). 
         [0231]    The card interface unit  11  executes the communication processing of  FIG. 7  or  FIG. 8  with the component of the host apparatus and switches its own operation state to the standby state. 
         [0232]    Thereafter, the card interface unit  11  monitors the buffer  13 . 
         [0233]    The card interface unit  11  repeatedly determines whether or not the amount of not-yet-processed read data in the buffer  13  has become equal to or larger than the read upper-limit threshold (step ST 53 ). 
         [0234]    If the amount of not-yet-processed read data in the buffer  13  has become equal to or larger than the read upper-limit threshold, the card interface unit  11  carries out control to switch its own operation state from the standby state to the communication-enabled L0 state (step ST 54 ). 
         [0235]    Specifically, the card interface unit  11  executes the communication processing of  FIG. 9  or  FIG. 10  with the component of the host apparatus and switches its own operation state from the standby state to the L0 state. 
         [0236]    Upon returning to the communication-enabled L0 state, the card interface unit  11  reads read data from the buffer  13  and transmits the data to the host apparatus (step ST 55 ). 
         [0237]    Furthermore, the card interface unit  11  monitors the buffer  13 . 
         [0238]    The card interface unit  11  determines whether or not the amount of not-yet-processed read data in the buffer  13  has become equal to or smaller than the read lower-limit threshold (step ST 56 ). 
         [0239]    The card interface unit  11  reads read data from the buffer  13  and transmits the data to the host apparatus until the amount of not-yet-processed read data in the buffer  13  becomes equal to or smaller than the read lower-limit threshold. 
         [0240]    If the amount of not-yet-processed read data in the buffer  13  becomes equal to or smaller than the read lower-limit threshold, the card interface unit  11  returns to the step ST 51  and determines whether or not the amount of remaining data to be transferred is equal to or larger than the predetermined value (Th_remain). 
         [0241]    If the amount of remaining data to be transferred is equal to or larger than the predetermined value, the card interface unit  11  repeats the processing from the step ST 52  to the step ST 56 . 
         [0242]    If the amount of remaining data to be transferred has decreased to be smaller than the predetermined value, the card interface unit  11  continues the processing of transfer of read data to the host apparatus (step ST 57 ). 
         [0243]    The card interface unit  11  determines whether or not all of the data relating to the request have been transferred (step ST 58 ). 
         [0244]    The card interface unit  11  reads read data from the buffer  13  and transmits the data to the host apparatus until the transfer of all of the data relating to the request has been ended. 
         [0245]    Upon ending the transfer of all of the data relating to the request, the card interface unit  11  ends the read processing. 
         [0246]    The card interface unit  11  may end the read processing after being switched to the standby state. 
         [0247]      FIG. 16  is an explanatory diagram showing one example of time change in the amount of not-yet-processed read data in the buffer  13  under the control of  FIG. 15 . 
         [0248]    In  FIG. 16 , the abscissa indicates the time and the ordinate indicates the amount of not-yet-processed read data in the buffer  13 . 
         [0249]    Under the control of  FIG. 15 , the card interface unit  11  enters the standby state if the amount of remaining data to be accessed and transferred is equal to or larger than the predetermined value Th_remain. 
         [0250]    Thus, the amount of not-yet-processed read data in the buffer  13  rises from zero at a reading start time T 10  to the read upper-limit threshold. 
         [0251]    This is because the card interface unit  11  has become the standby state due to the processing of the step ST 52  at the timing of the read processing start. 
         [0252]    If the amount of not-yet-processed read data in the buffer  13  reaches the read upper-limit threshold at a time T 11 , the card interface unit  11  switches from the standby state to the operating state (L0) at a time T 12  after return latency. 
         [0253]    The card interface unit  11  switched to the operating state starts transmission of read data at a time T 13  after data transfer latency. 
         [0254]    Thereby, the amount of not-yet-processed read data in the buffer  13  begins to decrease. 
         [0255]    The card interface unit  11  monitors the buffer  13  while transferring read data in the buffer  13  to the host apparatus. 
         [0256]    If the amount of not-yet-processed read data in the buffer  13  becomes equal to or smaller than the read lower-limit threshold at a time T 14 , the card interface unit  11  switches from the operating state (L0) to the standby state at a time T 15  after transition latency. 
         [0257]    In this manner, the card interface unit  11  switches between the operating state and the standby state in one time of read access. 
         [0258]    The amount of not-yet-processed read data in the buffer  13  increases and decreases on the basis of the read upper-limit threshold and the read lower-limit threshold. 
         [0259]    The not-yet-processed read data in the buffer  13  is not exhausted and not completely fills the buffer  13 . 
         [0260]    In the case of a system in which the empty state of the buffer  13  in reading causes no problem, the read lower-limit threshold does not have to be provided. 
         [0261]    The card interface unit  11  processes read data in the buffer  13  in each round of the communication-enabled period. 
         [0262]    Due to the control based on the read lower-limit threshold, exhaustion of not-yet-processed read data in the buffer  13  does not occur. 
         [0263]    Thus, the empty state of the buffer  13  does not occur also in the period until transition from L0 to the standby state. 
         [0264]    As a result, the card interface unit  11  processes read data in the buffer  13  continuously in each round of the communication-enabled period. 
         [0265]    Furthermore, the provision of the read upper-limit threshold can prevent the buffer  13  from being completely filled in the periods of the return latency and the data transfer latency. 
         [0266]    This can eliminate the influence given to the read speed of the memory card  1  by the latency until return from the standby state to L0 and the start of data transmission. 
         [0267]    As described above, in the present embodiment, the card interface unit  11  is made to take a pause if the capacity of the buffer  13  is insufficient in the period of write access by the camera device  2  as the host apparatus. 
         [0268]    The card interface unit  11  intermittently operates during this write access period. 
         [0269]    Thus, in the present embodiment, the power consumption during the write access period can be reduced. 
         [0270]    Furthermore, because the card interface unit  11  operates based on the communication system of PCI Express, by which high-speed serial data communication is carried out, the effect of the reduction in the power consumption is large. 
         [0271]    Furthermore, the card interface unit  11  monitors the capacity of the buffer  13 . The card interface unit  11  enters the pause state if the amount of not-yet-processed write data surpasses the write upper-limit threshold, and is restored from the pause state to the communication-enabled state if the amount of not-yet-processed write data becomes smaller than the write lower-limit threshold. 
         [0272]    That is, in the present embodiment, not-yet-processed write data is left in the buffer  13  although the card interface unit  11  is made to intermittently operate during the write access period. 
         [0273]    Thus, the memory controller  14  carries on the write processing continuously during the write access period. 
         [0274]    Consequently, in the present embodiment, the effective write speed is not lowered in the processing of writing to the storage device. 
         [0275]    The camera device  2  as the host apparatus can make write access at the effective write speed limited by the processing of writing to the non-volatile memory  15  by the memory controller  14 . 
         [0276]    In contrast, for example it would also be possible to employ a configuration in which, differently from the present embodiment, the card interface unit  11  measures e.g. the communication-absent period by a timer irrespective of the state of the buffer  13  and switches from the operating state to the standby state in response to the elapse of the communication-absent period. 
         [0277]    However, if a timer is used in this manner, switching to the standby state in the period of write access by the host apparatus is substantially difficult, and thus the large effect of reduction in the power consumption can not be achieved. 
         [0278]    Furthermore, even if the communication-absent period of the timer is shortened so that switching to the standby state may be allowed in the period of write access by the host apparatus, the buffer gets empty immediately after transition to the standby state and the memory controller  14  enters the state of waiting for the next write data in some cases. 
         [0279]    In this case, the time until the end of processing of the write data by the memory controller  14  is extended by this waiting time, so that the effective write speed of the memory controller  14  is lowered. 
         [0280]    Furthermore, in the present embodiment, the card interface unit  11  is made to take a pause in the state in which the amount of not-yet-processed read data in the buffer  13  is small in the period of read access by the camera device  2  as the host apparatus. 
         [0281]    The card interface unit  11  intermittently operates during this read access period. 
         [0282]    Thus, in the present embodiment, the power consumption during the read access period can be reduced. 
         [0283]    Furthermore, the card interface unit  11  monitors the capacity of the buffer  13 . The card interface unit  11  is restored from the pause state if the amount of not-yet-processed read data surpasses the read upper-limit threshold, and takes a pause if the amount of not-yet-processed read data becomes smaller than the read lower-limit threshold. 
         [0284]    That is, in the present embodiment, the memory controller  14  continuously writes read data to the buffer  13  also in the period when the card interface unit  11  takes a pause. 
         [0285]    Consequently, in the present embodiment, the effective read speed in the processing of reading from the memory card  1  is not lowered. 
         [0286]    The camera device  2  as the host apparatus can make read access at the effective read speed limited by the processing of reading to the buffer  13  by the memory controller  14 . 
         [0287]    As described above, in the present embodiment, in the memory card  1  that performs data transmission/reception with the host apparatus by using the PCI Express I/F, the power consumption during the access period of the host apparatus can be reduced without the lowering of the effective read/write speed of the memory card  1 . 
         [0288]    Furthermore, in the present embodiment, irrespective of the magnitude of the read/write speed of the non-volatile memory  15 , the components can operate adaptively to this speed. 
         [0289]    Specifically, if the non-volatile memory  15  whose read/write speed is low is used, the standby period of the PCI Express I/F is adaptively extended. 
         [0290]    Furthermore, if the non-volatile memory  15  whose read/write speed is high is used, automatic adjustment is so carried out that the standby period is shortened. 
         [0291]    In this manner, in the present embodiment, the power consumption can be reduced adaptively to the read/write speed of the non-volatile memory  15 . 
         [0292]    The above-described embodiment is an example of preferred embodiments of the present invention. However, the present invention is not limited thereto, but various modifications or changes can be made without departing from the gist of the present invention. 
         [0293]    For example, in the above-described embodiment, the card interface unit  11  in the memory card  1  has the component function to communicate with the host apparatus ( 2 ) and the power supply management function based on monitoring of the buffer  13 . 
         [0294]    As another configuration, for example, the communication control function of the card interface unit  11  based on monitoring of the buffer  13  may be provided separately from the card interface unit  11 , and the card interface unit  11  may have only the component function to communicate with the host apparatus. 
         [0295]    As further another configuration, for example, the card interface unit  11  may include the buffer  13  as a built-in unit as shown in  FIG. 17 . 
         [0296]    In the case of  FIG. 17 , the memory controller  14  is connected to the card interface unit  11  and accesses the buffer  13  in the card interface unit  11 . 
         [0297]    Alternatively, as shown in  FIG. 18 , the buffer  13  as a built-in unit may be included in the memory controller  14 . 
         [0298]    In the case of  FIG. 18 , the card interface unit  11  is connected to the memory controller  14  and accesses the buffer  13  in the memory controller  14 . 
         [0299]    In the above-described embodiment, the memory card  1  has a flash memory as the non-volatile memory  15 . 
         [0300]    Alternatively, for example, the storage device may have another semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a RAM (Random Access Memory), or may have a hard disc drive or the like. 
         [0301]    The above-described embodiment is an example of the camera system  3  in which the memory card  1  is utilized by the camera device  2 . 
         [0302]    As another configuration, for example, the memory card  1  can be utilized by electronic apparatus such as a camcorder device, a sound recording device, a personal computer device, a cellular phone, a PDA (Personal Digital Assistant), and a navigation device. 
         [0303]    The above-described embodiment is an example in which PCI Express using a clock signal for communication is utilized for the communication interface between the memory card  1  and the host apparatus. 
         [0304]    As another configuration, for example, a USB (Universal Serial Bus) interface, a wireless communication interface, or another interface may be utilized for the communication interface between the memory card  1  and the host apparatus. 
         [0305]    The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-040460 filed in the Japan Patent Office on Feb. 25, 2010, the entire content of which is hereby incorporated by reference. 
         [0306]    It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.