Abstract:
A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.

Description:
[0001]    This application is a divisional application claiming priority to Ser. No. 11/679,862, filed Feb. 28, 2007. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates generally to spacers for FETs (Field Effect Transistors) and more particularly to the formation of spacers for FinFETs. 
       BACKGROUND OF THE INVENTION 
       [0003]    In a conventional fabrication process of a FinFET (Fin Field Effect Transistor), it is desirable to form spacers on side walls of the gate electrode region of the FinFET while keeping the side walls of the fin region exposed to the surrounding ambient. Therefore, there is a need for a method for forming spacers on side walls of the gate electrode region while keeping the side walls of the fin region exposed to the surrounding ambient. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention provides a structure fabrication method, comprising providing a structure which includes (a) a substrate, (b) a device block on top of the substrate, and (c) a conformal spacer layer on top of both the substrate and the device block, wherein the device block comprises a first side wall and a second side wall, and wherein the first side wall is not parallel to the second side wall; bombarding the conformal spacer layer with particles in directions parallel to the first side wall but not parallel to the second side wall resulting in (i) damaged regions of the conformal spacer layer on the second side wall and (ii) undamaged regions of the conformal spacer layer on the first side wall; and then removing the damaged regions of the conformal spacer layer from the second side wall without removing the undamaged regions of the conformal spacer layer from the first side wall. 
         [0005]    The present invention provides a method for forming spacers on side walls of the gate electrode region while keeping the side walls of the fin region exposed to the surrounding ambient. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0006]      FIGS. 1A-1F  show a fabrication process for forming a first semiconductor structure, in accordance with embodiments of the present invention. 
           [0007]      FIGS. 2A-2C  show a fabrication process for forming a second semiconductor structure, in accordance with embodiments of the present invention. 
           [0008]      FIGS. 3A-3F  show a fabrication process for forming a third semiconductor structure, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0009]      FIGS. 1A-1F  show a fabrication process for forming a first semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process for forming the first semiconductor structure  100  starts with an SOI (Silicon-On-Insulator) substrate  110 + 120 + 130 . The SOI substrate  110 + 120 + 130  comprises a silicon layer  110 , a silicon dioxide layer  120  on top of the silicon layer  110 , and a silicon layer  130  on top of the silicon dioxide layer  120 . 
         [0010]    Next, with reference to  FIG. 1B , in one embodiment, a hard mask layer  140  is formed on top of the SOI substrate  110 + 120 + 130 . More specifically, the hard mask layer  140  can comprise silicon nitride. The hard mask layer  140  can be formed by CVD (Chemical Vapor Deposition) of silicon nitride on top of the SOI substrate  110 + 120 + 130 . 
         [0011]    Next, in one embodiment, the hard mask layer  140  and the silicon layer  130  are patterned resulting in a hard mask region  140 ′ and a fin region  130 ′, respectively, as shown in  FIG. 1C . More specifically, the hard mask layer  140  and the silicon layer  130  can be patterned using lithographic and etching processes. 
         [0012]    Next, with reference to  FIG. 1C , in one embodiment, gate dielectric layers (not shown) are formed on side walls  132 ′ of the fin region  130 ′. The gate dielectric layers can comprise silicon dioxide. The gate dielectric layers can be formed by thermally oxidizing exposed surfaces of the fin region  130 ′. It should be noted that, in  FIGS. 1C through 1F , the gate dielectric layers are not shown for simplicity. 
         [0013]    Next, with reference to  FIG. 1D , in one embodiment, a gate electrode region  150  is formed on top of the semiconductor structure  100  of  FIG. 1C . The gate electrode region  150  can comprise poly-silicon. The gate electrode region  150  can be formed by (i) depositing a poly-silicon layer (not shown) on top of the semiconductor structure  100  of  FIG. 1C  and (ii) patterning the deposited poly-silicon layer using lithographic and etching processes resulting in the gate electrode region  150  of  FIG. 1D . In one embodiment, the fin region  130 ′ runs in a direction  131 , whereas the gate electrode region  150  runs in a direction  151 , wherein the direction  131  is perpendicular to the direction  151 . 
         [0014]    Next, with reference to  FIG. 1E , in one embodiment, a spacer layer  160  is formed on top of the semiconductor structure  100  of  FIG. 1D . More specifically, the spacer layer  160  can comprise silicon nitride. The spacer layer  160  can be formed by CVD of silicon nitride on top of the semiconductor structure  100  of  FIG. 1D . FIG.  1 Ei shows a top-down view of the semiconductor structure  100  of  FIG. 1E , whereas FIG.  1 Eii shows a cross-section view of the semiconductor structure  100  of  FIG. 1E  along a plane defined by a line  1 Eii- 1 Eii. 
         [0015]    Next, with reference to  FIGS. 1E ,  1 Ei, and  1 Eii, the spacer layer  160  is bombarded with ions in directions defined by arrows  170   a  and  170   b . The directions  170   a  and  170   b  (i) are parallel to the side walls  152  ( FIG. 1D ) of the gate electrode region  150  and (ii) make an angle of 45° with the top surface  122  of the silicon dioxide layer  120 . In one embodiment, the spacer layer  160  is bombarded with argon ions. More specifically, the argon ions are accelerated in an electric field (not shown) such that the ion penetration depth  164  is equal to a thickness  162  of the spacer layer  160  times square root of two. It should be noted that the ion bombardment should not penetrate the gate electrode region  150  and the fin region  130 ′. As a result, only spacer regions of the spacer layer  160  that are on side walls of the gate electrode region  150  and the fin region  130 ′ that are parallel to the directions  170   a  and  170   b  are not damaged (undamaged) by the bombarding ions. These undamaged regions are shown in  FIG. 1F  as spacer regions  164   a ,  164   b ,  162   a , and  162   b.    
         [0016]    Next, in one embodiment, the damaged spacer regions of the spacer layer  160  are removed resulting in the semiconductor structure  100  of  FIG. 1F . The damaged spacer regions can be removed by anisotropic etching. The anisotropic etching is selective to the undamaged spacer regions  164   a ,  164   b ,  162   a , and  162   b  of the spacer layer  160  resulting in the undamaged spacer regions  164   a ,  164   b ,  162   a , and  162   b  remaining on side walls of the gate electrode region  150  and the fin region  130 ′. It should be noted that the top surfaces of the undamaged spacer regions  162   a  and  162   b  are coplanar with the top surface  156  of the gate electrode region  150 . In an alternative embodiment, the damaged spacer regions of the spacer layer  160  are isotropically etched selectively to the undamaged spacer regions  164   a ,  164   b ,  162   a , and  162   b  of the spacer layer  160 . As a result of inevitable over etching, the removal of the damaged spacer regions also results in the removal of the gate dielectric layers beneath the damaged spacer regions. 
         [0017]    Next, in one embodiment, conventional steps can be performed on the semiconductor structure  100  of  FIG. 1F  to form a transistor (not shown). More specifically, extension and halo regions (not shown) are formed in the fin region  130 ′ using ion implantation. Next, second spacer regions (not shown) are formed on side walls of the spacer regions  162   a  and  162   b , and no spacer is formed on side walls  132 ′ of the fin region  130 ′. The second spacer regions can be formed in a manner similar to the manner in which the spacer regions  162   a  and  162   b  are formed on the side walls  152  ( FIG. 1D ) of the gate electrode region  150 . Next, source/drain regions (not shown) are formed in the fin region  130 ′. The source/drain regions can be formed by ion implantation in the directions  170   a  and  170   b.    
         [0018]    In summary, after the removal the damaged spacer regions of the spacer layer  160 , the undamaged spacer regions  162   a  and  162   b  of the spacer layer  160  remain on side walls  152  ( FIG. 1D ) of the gate electrode region  150 , whereas the side walls  132 ′ of the fin region  130 ′ are exposed to the surrounding ambient. In other words, the spacer regions  162   a  and  162   b  are formed on side walls  152  of the gate electrode region  150 , and no spacer is formed on side walls  132 ′ of the fin region  130 ′. After that, conventional steps can be performed on the semiconductor structure  100  of  FIG. 1F  to form a transistor. 
         [0019]      FIGS. 2A-2C  show a fabrication process for forming a second semiconductor structure  200 , in accordance with embodiments of the present invention. More specifically, the fabrication process for forming the second semiconductor structure  200  starts with the semiconductor structure  200  of  FIG. 2A , wherein the semiconductor structure  200  of  FIG. 2A  is similar to the semiconductor structure  100  of  FIG. 1E . The formation of the semiconductor structure  200  of  FIG. 2A  is similar to the formation of the semiconductor structure  100  of  FIG. 1E . 
         [0020]    Next, in one embodiment, the spacer layer  160  is anisotropically etched (e.g., using dry etching) resulting in a spacer region  262  on side walls of (i) the gate electrode region  150 , (ii) the fin region  130 ′, and (iii) the hard mask region  140 ′ as shown in  FIG. 2B . FIG.  2 Bi shows a top-down view of the semiconductor structure  200  of  FIG. 2B , whereas FIG.  2 Bii shows a cross-section view of the semiconductor structure  200  of  FIG. 2B  along a plane defined by a line  2 Bii- 2 Bii. 
         [0021]    Next, with reference to  FIGS. 2B ,  2 Bi, and  2 Bii, the spacer region  262  is bombarded with ions in directions defined by arrows  270   a  and  270   b . The directions  270   a  and  270   b  (i) are parallel to side walls  152  ( FIG. 1D ) of the gate electrode region  150  and (ii) make an angle of 45° with the top surface  122  of the silicon dioxide layer  120 . In one embodiment, the spacer region  262  is bombarded with argon ions. More specifically, the argon ions are accelerated in an electric field (not shown) such that the ion penetration depth  264 ′ is equal to a thickness  262 ′ of the spacer region  262  times square root of two. It should be noted that the ion bombardment should not penetrate the gate electrode region  150  and the fin region  130 ′. As a result, only regions of the spacer region  262  that are on side walls of the gate electrode region  150  and the fin region  130 ′ that are parallel to the directions  270   a  and  270   b  are not damaged (undamaged) by the bombarding ions. These undamaged spacer regions are shown in  FIG. 2C  as spacer regions  264   a ,  264   b ,  266   a , and  266   b.    
         [0022]    Next, in one embodiment, the damaged regions of the spacer region  262  are removed resulting in the semiconductor structure  200  of  FIG. 2C . The damaged spacer regions can be removed by anisotropic (vertical) etching. The anisotropic etching is selective to the undamaged spacer regions of the spacer region  262  resulting in the semiconductor structure  200  of  FIG. 2C . As a result of inevitable over etching, the removal of the damaged spacer regions also results in the removal of the gate dielectric layers beneath the damaged spacer regions. Alternatively an isotropic etch can be used to selectively remove the damaged portions of the spacer. 
         [0023]    Next, in one embodiment, conventional steps can be performed on the semiconductor structure  200  of  FIG. 2C  to form a transistor (not shown). More specifically, extension and halo regions (not shown) are formed in the fin region  130 ′ using ion implantation. Next, second spacer regions (not shown) are formed on side walls of the spacer regions  264   a  and  264   b , and no spacer is formed on side walls  132 ′ of the fin region  130 ′. The second spacer regions can be formed in a manner similar to the manner in which the spacer regions  264   a  and  264   b  are formed on the side walls  152  of the gate electrode region  150 . Next, source/drain regions (not shown) are formed in the fin region  130 ′. The source/drain regions can be formed by ion implantation in the directions  270   a  and  270   b.    
         [0024]    In summary, after the removal the damaged regions of the spacer region  262 , the undamaged spacer regions  264   a  and  264   b  of the spacer region  262  remain on side walls  152  ( FIG. 1D ) of the gate electrode region  150 , whereas the side walls  132 ′ of the fin region  130 ′ are exposed to the surrounding ambient. In other words, the spacer regions  264   a  and  264   b  are formed on side walls  152  of the gate electrode region  150 , and no spacer is formed on side walls  132 ′ of the fin region  130 ′. After that, conventional steps can be performed on the semiconductor structure  200  of  FIG. 2C  to form a transistor. 
         [0025]      FIGS. 3A-3F  show a fabrication process for forming a third semiconductor structure  400 , in accordance with embodiments of the present invention. More specifically, the fabrication process for forming the third semiconductor structure  400  starts with the semiconductor structure  400  of  FIG. 3A , wherein the semiconductor structure  400  of  FIG. 3A  is similar to the semiconductor structure  100  of  FIG. 1D . The formation of the semiconductor structure  400  of  FIG. 3A  is similar to the formation of the semiconductor structure  100  of  FIG. 1D . 
         [0026]    Next, with reference to  FIG. 3B , in one embodiment, a first spacer layer  460  is formed on top of the semiconductor structure  400  of  FIG. 3A . More specifically, the first spacer layer  460  can comprise silicon nitride. The first spacer layer  460  can be formed by CVD of silicon nitride on top of the semiconductor structure  400  of  FIG. 3A . 
         [0027]    Next, with reference to  FIG. 3C , in one embodiment, a second spacer layer  480  is formed on top of the first spacer layer  460  such that the thickness of the first spacer layer  460  is greater than the thickness of the second spacer layer  480 . More specifically, the second spacer layer  480  can comprise silicon dioxide. The second spacer layer  480  can be formed by CVD of silicon dioxide on top of the first spacer layer  460 . FIG.  3 Ci shows a top-down view of the semiconductor structure  400  of  FIG. 3C , whereas FIG.  3 Cii shows a cross-section view of the semiconductor structure  400  of  FIG. 3C  along a plane defined by a line  3 Cii- 3 Cii. 
         [0028]    Next, with reference to  FIGS. 3C ,  3 Ci, and  3 Cii, the second spacer layer  480  is bombarded with ions in directions defined by arrows  470   a  and  470   b . The directions  470   a  and  470   b  (i) are parallel to the side walls  152  of the gate electrode region  150  and (ii) make an angle of 45° with the top surface  122  of the silicon dioxide layer  120 . In one embodiment, the second spacer layer  480  is bombarded with argon ions. More specifically, the argon ions are accelerated in an electric field (not shown) such that the ion penetration depth is equal to a thickness of the second spacer layer  480  times square root of two. It should be noted that the ion bombardment should not penetrate the gate electrode region  150  and the fin region  130 ′. As a result, only regions of the second spacer layer  480  that are on planes that are parallel to the directions  470   a  and  470   b  (i.e., on the planes that are parallel to the side walls  152  of the gate electrode region  150 ) are not damaged (undamaged) by the bombarding ions. These undamaged spacer regions are shown in  FIG. 3D  as spacer regions  484   a ,  484   b ,  482   a , and  482   b . It can be considered that (i) the spacer regions  482   a  and  482   b  are on side walls  152  of the gate electrode region  150  and (ii) the damaged spacer regions of the second spacer layer  480  are on side walls  132 ′ of the fin region  130 ′. 
         [0029]    Next, in one embodiment, the damaged spacer regions of the second spacer layer  480  are removed resulting in the semiconductor structure  400  of  FIG. 3D . The damaged spacer regions can be removed by isotropic etching. The isotropic etching is selective to (i) the undamaged spacer regions  484   a ,  484   b ,  482   a , and  482   b  of the second spacer layer  480  and (ii) the first spacer layer  460 . 
         [0030]    Next, in one embodiment, the first spacer region  460  is isotropically etched until the side walls  132 ′ ( FIG. 3E ) of the fin region  130 ′ are exposed to the surrounding ambient resulting in the semiconductor structure  400  of  FIG. 3E . The isotropic etching is selective to the spacer regions  484   a ,  484   b ,  482   a , and  482   b . As a result, after the isotropic etching of the first spacer region  460 , spacer regions  462   a  and  462   b  of the first spacer region  460  (shown in  FIG. 3F ) remain on side walls of the gate electrode region  150 , and no spacer remains on side walls  132 ′ of the fin region  130 ′. 
         [0031]    Next, with reference to  FIG. 3E , in one embodiment, the spacer regions  484   a ,  484   b ,  482   a , and  482   b  are removed resulting in the semiconductor structure  400  of  FIG. 3F . The spacer regions  484   a ,  484   b ,  482   a , and  482   b  can be removed by isotropic etching. The isotropic etching is selective to spacer regions  462   a ,  462   b ,  464   a , and  464   b  (shown in  FIG. 3F ). 
         [0032]    Next, in one embodiment, conventional steps can be performed on the semiconductor structure  400  of  FIG. 3F  to form a transistor (not shown). More specifically, extension and halo regions (not shown) are formed in the fin region  130 ′ using ion implantation. Next, second spacer regions (not shown) are formed on side walls of the spacer regions  462   a  and  462   b , and no spacer is formed on side walls  132 ′ of the fin region  130 ′. The second spacer regions can be formed in a manner similar to the manner in which the spacer regions  462   a  and  462   b  are formed on the side walls  152  of the gate electrode region  150 . Next, source/drain regions (not shown) are formed in the fin region  130 ′. The source/drain regions can be formed by ion implantation in the directions  470   a  and  470   b.    
         [0033]    In summary, after the removal of the spacer regions  484   a ,  484   b ,  482   a , and  482   b , the spacer regions  462   a ,  462   b ,  464   a , and  464   b  remain on side walls  152  of the gate electrode region  150 , whereas the side walls  132 ′ of the fin region  130 ′ are exposed to the surrounding ambient. In other words, the spacer regions  462   a  and  462   b  are formed on side walls of the gate electrode region  150 , and no spacer is formed on side walls  132 ′ of the fin region  130 ′. 
         [0034]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.