Abstract:
A column repair circuit of a semiconductor memory device including a plurality of memory cell array blocks each having the different number of wordlines comprises a predecoder, a block selector, a unit selector and a fuse means. The predecoder decodes a row address. The block selector generates block selecting signals to select the memory cell array blocks. The unit selector generates unit selecting signals to select a size of a row corresponding to the selected memory cell array. The fuse means generates a column repair control signal activated when a column repair is performed on the selected memory cell array block. The column repair circuit performs a column repair operation by a memory cell array block unit, thereby improving column repair efficiency and reducing the number of column repair fuses.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention generally relates to a column repair circuit for repairing a failed cell, and more specifically, to a column repair circuit for performing a column repair operation on memory cell array blocks each having the different number of wordlines.  
           [0003]    2. Description of the Prior Art  
           [0004]    Generally, in a semiconductor memory device, defective cells are replaced with redundancy memory cells.  
           [0005]    When at least one of normal memory cells connected to a column selecting line is defective, a column repair circuit replaces the column selecting line with a redundancy column selecting line. That is, memory cells connected to column selecting lines connected to at least one defective memory cell are replaced with redundancy memory cells connected redundancy column selecting lines.  
           [0006]    [0006]FIG. 1 is a diagram illustrating a structure of a memory including memory cell array blocks each having the different number of wordlines. Here, 128M memory cell array block is exemplified.  
           [0007]    Generally, a DRAM that has a 128M memory cell array block structure is configured to have four 32M banks.  
           [0008]    Each 32M bank comprises two groups, and each group comprises 6 memory cell array blocks.  
           [0009]    Here, 6 memory cell array blocks included in one group are shown.  
           [0010]    In order to increase cell density by reducing the number of bitline sense amplifiers arranged between memory cell array blocks, one memory cell array block is arranged to have 704 or 640 wordlines.  
           [0011]    A DRAM comprises a column repair circuit for repairing the failed when a column failure occurs in a memory cell array block,.  
           [0012]    However, although one memory cell array block is arranged to have 704 or 640 wordlines, the column repair operation is performed by 512 wordlines.  
           [0013]    As shown in FIG. 2 a , when a column failure occurs in a second block in the memory cell array block of FIG. 1, the column repair operation is performed only on the third block. Thereafter, as shown in FIG. 2 b , when a burn-in test, a reliability test and an application test performed on the rest  512  wordlines and a column failure happens, an additional column repair line is required for the column failure of the same block, which results in degradation of repair efficiency.  
         SUMMARY OF THE INVENTION  
         [0014]    Accordingly, it is an object of the present invention to perform a repair operation on each memory cell array block, thereby improving the repair efficiency.  
           [0015]    It is another object of the present invention to perform a repair operation on each memory cell array block, thereby reducing the number of column repair fuses.  
           [0016]    In an embodiment, a column repair circuit of a semiconductor memory device including a plurality of memory cell array blocks each having the different number of rows comprises a predecoder, a block selector, a unit selector and a fuse means. The predecoder decodes a row address. The block selector generates block selecting signals to select the memory cell array blocks in response to output signals from the predecoder. The unit selector generates unit selecting signals to select a size of a row corresponding to the selected memory cell array in response to a refresh mode signal, a row repair control signal, a row repair identifying signal, a row active signal and the block selecting signals. The fuse means generates a column repair control signal activated in response to a column repair test signal and the unit selecting signals when a column repair is performed on the selected memory cell array block. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 is a diagram illustrating a structure of a memory including memory cell array blocks each having the different number of wordlines.  
         [0018]    [0018]FIG. 2 a  is a diagram illustrating a column repair operation when a column failure occurs in the memory of FIG. 1.  
         [0019]    [0019]FIG. 2 b  is a diagram illustrating a column repair operation when a column failure occurs in a test after the column repair operation of FIG. 2 a.    
         [0020]    [0020]FIG. 3 is a block diagram of a column repair circuit according to an embodiment of the present invention.  
         [0021]    [0021]FIGS. 4 a  to  4   c  are circuit diagram of a block selector of FIG. 3.  
         [0022]    [0022]FIGS. 5 a  to  5   c  are circuit diagram of a unit selector of FIG. 3.  
         [0023]    [0023]FIG. 6 is a circuit diagram of a repair detector of FIG. 3.  
         [0024]    [0024]FIG. 7 is a circuit diagram of a group selecting signal generator of FIG. 3.  
         [0025]    [0025]FIG. 8 is a circuit diagram of a fuse unit of FIG. 3.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]    The present invention will be described in detail with reference to the accompanying drawings.  
         [0027]    [0027]FIG. 3 is a block diagram of a column repair circuit according to an embodiment of the present invention. Here, a DRAM having a 128M memory cell array block structure is exemplified.  
         [0028]    In the DRAM having 128M memory cell array block structure, the whole memory cell is configured to be quartered. That is, the memory cell comprises four 32M banks.  
         [0029]    Each 32M bank comprises 2 groups, and each group comprises 6 memory cell array blocks.  
         [0030]    Here, a column repair circuit on 3 memory cell array blocks in one group including 6 memory cell array blocks is shown because a column repair circuit on the rest  3  memory cell array blocks has the same structure. 3 memory cell array blocks are configured to have 704, 640 and 704 wordlines, respectively. In the configuration of row addresses, the upper 6 bit row addresses AX&lt;0:5&gt; is to select wordlines, and the rest bit row address AX&lt;6:B&gt; is to select memory cell array blocks.  
         [0031]    In an embodiment, the column repair circuit comprises a predecoder  10 , a block selector  20 , a unit selector  30 , a row repair detector  40 , a group selector  50  and a fuse unit  60 .  
         [0032]    The predecoder  10  decodes row addresses AX&lt;6:A&gt;.  
         [0033]    The block selector  20  outputs a block selecting signal BS 6 A&lt;0:2&gt; for selecting a memory cell array block in response to output signals LAX 678 &lt;0:7&gt; and LAX 9 A&lt;0:2&gt; from the predecoder  10 .  
         [0034]    The unit selector  30  outputs a unit selecting signal  9 AYF&lt;0:2&gt; to determine whether a repair operation is performed on column lines of the selected memory cell array block to have 704 or 640 wordlines in response to a row repair identifying signal WLSTRWE, a row repair control signal RWEZ 23 , a refresh mode signal REFZ, a first row active signal RAST 10  and a block selecting signal BS 6 A&lt;0:2&gt;. Here, the row repair identifying signal WLSTRWE becomes at a high level when the block has a row repair line. The row repair control signal RWEZ 23  becomes at a high level when the row is repaired. The refresh mode signal REFZ becomes at a low level in a refresh mode. The first row active signal RAST 10  becomes at a high level when the row is active.  
         [0035]    The row repair detector  40  outputs the row repair control signal RWEZ 23  and the row repair identifying signal WLSTRWE in response to a first row repair selecting signal PRWEZ 02 , a second row repair selecting signal PRWEZ 13  and a second row active signal WLSTD. Here, the first row repair selecting signal PRWEZ 02  becomes at a low level when a row repair of a second memory cell array block is selected. The second row repair selecting signal PRWEZ 13  becomes at a low level when a row repair of a fifth memory cell array block is selected. The second row active signal WLSTD is delayed for a delay time until a row repair flag signal is generated through a row fuse box.  
         [0036]    The group selector  50  outputs a group selecting signal BYF&lt;0&gt; in response to a group selecting address RA 11 B, a refresh mode signal REFZ, a first row active signal RAST 10  and the row repair identifying signal WLSTRWE.  
         [0037]    The fuse unit  60  outputs a column repair control signal YRENB for controlling a column corresponding to a fuse of a memory cell array block to be repaired in response to a precharge signal YREDST, a column repair test signal YREDTM, the first row repair selecting signal PRWEZ 02 , a unit selecting signal  9 AYF&lt;0:2&gt; and the group selecting signal BYF&lt;0&gt;. Here, the precharge signal YREDST becomes at a low level in a standby state, and the column repair test signal YREDTM becomes at a high level when a column repair is tested.  
         [0038]    [0038]FIGS. 4 a  to  4   c  are circuit diagram of the block selector  20  of FIG. 3. Here, the block selector  20  comprises block selecting signal generators  21 ,  22  and  23  for generating block selecting signals BS 6 A&lt;0:2&gt; to select a corresponding memory cell array block.  
         [0039]    [0039]FIG. 4 a  is a circuit diagram of the block selecting signal generator  21  for generating a first block selecting signal to select a first memory cell array block.  
         [0040]    The first block selecting signal generator  21  comprises NOR gates NOR 1  and NOR 2 , a NMOS transistor NM 1 , a PMOS transistor PM 1  and inverters INV 1  and INV 2 . The NOR gate NOR 1  performs an NOR operation on output signals LAX 678 &lt;0:2&gt; from the predecoder  10 . The NMOS transistor NM 1  has a gate to receive an output signal LAX 9 A&lt;1&gt; from the predecoder  10 , thereby activating the NOR gate NOR 1 . The PMOS transistor PM 1  has a gate to receive the output signal LAX 9 A&lt;1&gt; from the predecoder  10 , thereby initializing an output terminal of the NOR gate NOR 1  to a high level. The inverter INV 1  inverts an output signal from the NOR gate NOR 1 . The NOR gate NOR 2  performs an NOR operation on the output signal LAX 9 A&lt;0&gt; from the predecoder  10  and an output signal from the inverter INV 1 . The inverter INV 2  inverts an output signal from the NOR gate NOR 2  to output the first block selecting signal BS 6 A&lt;0&gt;.  
         [0041]    If the first row repair unit selecting signal LAX 9 A&lt;0&gt; is at a high level or one of the output signals LAX 678 &lt;0:2&gt; from the predecoder  10  is at a high level and the second row repair unit selecting signal LAX 9 A&lt;1&gt; is at a high level, the first block selecting signal BS 6 A&lt;0&gt; to select a first memory cell array block becomes at a high level to activate the first memory cell array. Here, the first row repair unit selecting signal LAX 9 A&lt;0&gt; becomes at a high level when a first unit having 512 row wordlines is selected. The second row repair unit selecting signal LAX 9 A&lt;1&gt; becomes at a high level when a second unit having 512 row wordlines is selected.  
         [0042]    Meanwhile, if the second row repair unit selecting signal LAX 9 A&lt;1&gt; is at a low level, the PMOS transistor PM 1  is turned on to set an output terminal of the NOR gate NOR 1  as a high level regardless of the output signals LAX 678 &lt;0:2&gt; from the predecoder  10 . AS a result, the state of the first block selecting signal BS 6 A&lt;0&gt; is determined by that of the first row repair unit selecting signal LAX 9 A&lt;0&gt;.  
         [0043]    [0043]FIG. 4 b  is a circuit diagram of the block selecting signal generator  22  for generating a second block selecting signal to select a second memory cell array block.  
         [0044]    The second block selecting signal generator  22  comprises an upper detector  24 , a lower detector  25  and a logic combination unit  26 . The upper detector  24  detects when an upper portion of the memory cell array block is selected. The lower detector  25  detects when a lower portion of the memory cell array block is selected. The logic combination unit  26  performs a logic operation on output signals from the upper detector  24  and the lower detector  25  to output the second block selecting signal BS 6 A&lt;1&gt;.  
         [0045]    The upper detector  24  comprises NOR gates NOR 3  and NOR 4 , NMOS transistors NM 2  and NM 3 , PMOS transistors PM 2  and PM 3  and an NAND gate ND 1 . The NOR gate NOR 3  performs an NOR operation on output signals LAX 678 &lt;3:5&gt;. The NMOS transistor NM 2  has a gate to receive the output signal LAX 9 A&lt;1&gt; from the predecoder  10 , thereby activating the NOR gate NOR 3 . The PMOS transistor PM 2  has a gate to receive the output signal LAX 9 A&lt;1&gt; from the predecoder  10 , thereby initializing an output terminal of the NOR gate NOR 3  to a high level. The NOR gate NOR 4  performs an NOR operation on output signals LAX 678 &lt;3:4&gt; from the predecoder  10 . The NMOS transistor NM 3  has a gate to receive the output signal LAX 9 A&lt;1&gt; from the predecoder  10 , thereby activating the NOR gate NOR 4 . The PMOS transistor PM 3  has a gate to receive the output signal LAX 9 A&lt;1&gt; from the predecoder  10 , thereby initializing an output terminal of the NOR gate NOR 4  to a high level. The NAND gate ND 1  performs an NAND operation on output signals from the NOR gates NOR 3  and NOR 4 .  
         [0046]    The lower detector  25  comprises NOR gates NOR 5  and NOR 6 , NMOS transistors NM 4  and NM 5 , PMOS transistors PM 4  and PM 5  and an NAND gate ND 2 . The NOR gate NOR 5  performs an NOR operation on output signals LAX 678 &lt;3:5&gt; from the predecoder  10 . The NMOS transistor NM 4  has a gate to receive an output signal LAX 9 A&lt;2&gt;, thereby activating the NOR gate NOR 5 . The PMOS transistor PM 4  has a gate to receive the output signal LAX 9 A&lt;2&gt; from the predecoder  10 , thereby initializing an output terminal of the NOR gate NOR 5  to a high level. The NOR gate NOR 6  performs an NOR operation on output signals LAX 678 &lt;6:7&gt; from the predecoder  10 . The NMOS transistor NM 5  has a gate to receive the output signal LAX 9 A&lt;2&gt; from the predecoder  10 , thereby activating the NOR gate NOR 6 . The PMOS transistor PM 5  has a gate to receive the output signal LAX 9 A&lt;2&gt; from the predecoder  10 , thereby initializing an output terminal of the NOR gate NOR 6  to a high level. The NAND gate ND 2  performs an NAND operation on output signals from the NOR gates NOR 5  and NOR 6 .  
         [0047]    The logic combination unit  26  comprises an NOR gate NOR 7  and an inverter INV 3 . The NOR gate NOR 7  performs an NOR operation on output signals DET&lt;0:1&gt; from the upper detector  24  and the lower detector  25 . The inverter INV 3  inverts an output signal from the NOR gate NOR 7 .  
         [0048]    The upper detector  24  outputs a high level signal DET&lt;0&gt; if the second row repair unit selecting signal LAX 9 A&lt;1&gt; is at a high level and one of the output signals LAX 678 &lt;3:7&gt; from the predecoder  10  is at a high level.  
         [0049]    If the second row repair unit selecting signal LAX 9 A&lt;1&gt; is at a low level, the PMOS transistors PM 2  and PM 3  are turned on to set output terminals of the NOR gate NOR 3  and NOR 4  as a high level regardless of the output signals LAX 678 &lt;3:7&gt; from the predecoder  10 . As a result, the output signal DET&lt;0&gt; from the NAND gate ND 1  becomes at a low level.  
         [0050]    The lower detector  25  outputs a high level signal DET&lt;1&gt; if a third row repair unit selecting signal LAX 9 A&lt;2&gt; is at a high level and one of the output signals LAX 678 &lt;0:4&gt; from the predecoder  10  is at a high level. Here, the third row repair unit selecting signal LAX 9 A&lt;2&gt; becomes at a high level when a third unit having 512 wordlines is selected.  
         [0051]    If the third row repair unit selecting signal LAX 9 A&lt;2&gt; is at a low level, the PMOS transistors PM 4  and PM 5  are turned on to set output terminals of the NOR gates NOR 5  and NOR 6  as a high level regardless of the output signals LAX 678 &lt;0:4&gt; from the predecoder  10 . As a result, the output signal DET&lt;1&gt; from the NAND gate ND 2  becomes at a low level.  
         [0052]    If one of the output signals DET&lt;0:1&gt; from the upper detector  24  and the lower detector  25  becomes at a high level, the second block selecting signal BS 6 A&lt;1&gt; outputted from the logic combination unit  26  becomes at a high level to activate the second memory cell array block.  
         [0053]    If the output signals DET&lt;0:1&gt; from the upper detector  24  and the lower detector  25  become all at a low level, the second block selecting signal BS 6 A&lt;1&gt; outputted from the logic combination unit  26  becomes at a low level to inactivate the second memory cell array block.  
         [0054]    [0054]FIG. 4 c  is a circuit diagram of the block selecting signal generator  23  for generating a third block selecting signal to select a third memory cell array block.  
         [0055]    The third block selecting signal generator  23  comprises NOR gates NOR 8  and NOR 9 , an NMOS transistor NM 6 , a PMOS transistor PM 6  and inverters INV 4  and INV 5 . The NOR gate NOR 8  performs an NOR operation on output signals LAX 678 &lt;5:7&gt; from the predecoder  10 . The NMOS transistor NM 6  has a gate to receive the output signal LAX 9 A&lt;2&gt;, thereby activating the NOR gate NOR 8 . The PMOS transistor PM 6  has a gate to receive the output signal LAX 9 A&lt;2&gt; from the predecoder  10 , thereby initializing an output terminal of the NOR gate NOR 8  to a high level. The inverter INV 4  inverts an output signal from the NOR gate NOR 8 . The NOR gate NOR 9  performs an NOR operation on an output signal LAX 9 A&lt;3&gt; from the predecoder  10  and an output signal from the inverter INV 4 . The inverter INV 5  inverts an output signal from the NOR gate NOR 9  to output a block selecting signal BS 6 A&lt;2&gt;.  
         [0056]    If a fourth row repair unit selecting signal LAX 9 A&lt;3&gt; is at a high level or one of the output signals LAX 678 &lt;5:7&gt; from the predecoder  10  is at a high level and the signal LAX 9 A&lt;2&gt; representing the third unit having 512 wordlines is at a high level, the third block selecting signal BS 6 A&lt;2&gt; becomes at a high level to activate the third memory cell array block. Here, the fourth row repair unit selecting signal LAX 9 A&lt;3&gt; becomes at a high level when a fourth unit consisting of 512 wordlines is selected.  
         [0057]    If the third row repair unit selecting signal LAX 9 A&lt;2&gt; is at a low level, the PMOS transistor PM 6  is turned on to set an output terminal of the NOR gate NOR 8  as a high level. As a result, the state of the third block selecting signal BS 6 A&lt;2&gt; is determined by that of the fourth row repair unit selecting signal LAX 9 A&lt;3&gt;.  
         [0058]    [0058]FIGS. 5 a  to  5   c  are circuit diagram of the unit selector  30  of FIG. 3. Here, the unit selector  30  comprises unit selecting signal generators  31 ,  32  and  33  for generating unit selecting signals  9 AYF&lt;0:2&gt; to select a corresponding row unit (for example, 704 or 640 wordlines).  
         [0059]    [0059]FIG. 5 a  is a circuit diagram of the unit selecting signal generator  31  for generating a first unit selecting signal  9 AYF&lt;0&gt; to select a row repair unit of a first memory cell array block of the unit selector  30  of FIG. 3.  
         [0060]    The first unit selecting signal generator  31  comprises inverters INV 6 , INV 7  and INV 8 , NOR gates NOR 10 , NOR 11  and NOR 12  and an NAND gate ND 3 . The inverter INV 6  inverts the first block selecting signal BS 6 A&lt;0&gt;. The NOR gate NOR 10  performs an NOR operation on an output signal from the inverter INV 6  and the row repair identifying signal WLSTRWE. The NOR gate NOR 11  has one input terminal to receive an output signal from the NOR gate NOR 10  and the other input terminal connected to a ground voltage. The NAND gate ND 3  performs an NAND operation on the refresh mode signal REFZ and the first row active signal RAST 10 . The NOR gate NOR 12  performs an NOR operation on output signals from the NOR gate NOR 11  and the NAND gate ND 3 . The inverters INV 7  and INV 8  invert output signals from the NOR gate NOR 12  sequentially.  
         [0061]    [0061]FIG. 5 b  is a circuit diagram of the unit selecting signal generator  32  for generating a second unit selecting signal  9 AYF&lt;1&gt; to select a row repair unit of a second memory cell array block of the unit selector  30  of FIG. 3.  
         [0062]    The second unit selecting signal generator  32  comprises inverters INV 9 , INV 10  and INV 11 , NOR gates NOR 13 , NOR 14 , NOR 15  and an NAND gate ND 4 . The inverter INV 9  inverts the second block selecting signal BS 6 A&lt;1&gt;. The NOR gate NOR 13  performs an NOR operation on an output signal from the inverter INV 9  and the row repair identifying signal WLSTRWE. The NOR gate NOR 14  performs on the row repair control signal RWEZ 23  and an output signal from the NOR gate NOR 13 . The NAND gate ND 4  performs an NAND operation on the refresh mode signal REFZ and the first row active signal RAST 10 . The NOR gate NOR 15  performs an NOR operation on output signals from the NOR gate NOR 14  and the NAND gate ND 4 . The inverters INV 10  and INV 11  invert output signals from the NOR gate NOR 15  sequentially.  
         [0063]    [0063]FIG. 5 c  is a circuit diagram of the unit selecting signal generator  33  for generating a third unit selecting signal  9 AYF&lt;2&gt; to select a row repair unit of a third memory cell array block of the unit selector  30  of FIG. 3.  
         [0064]    The third unit selecting signal generator  33  comprises inverters INV 12 , INV 13  and INV 14 , NOR gates NOR 16 , NOR 17  and NOR 18  and an NAND gate ND 5 . The inverter INV 12  inverts the third block selecting signal BS 6 A&lt;2&gt;. The NOR gate NOR 16  performs an NOR operation on an output signal from the inverter INV 12  and the row repair identifying signal WLSTRWE. The NOR gate NOR 17  has one input terminal to receive an output signal from the NOR gate NOR 16  and the other input terminal connected to a ground voltage. The NAND gate ND 5  performs an NAND operation on the refresh mode signal REFZ and the first row active signal RAST 10 . The NOR gate NOR 18  performs an NOR operation on output signals from the NOR gate NOR 17  and the NAND gate ND 5 . The inverters INV 13  and INV 14  invert output signals from the NOR gate NOR 18  sequentially.  
         [0065]    Hereinafter, the operation of the unit selector  30  is described.  
         [0066]    If the refresh mode signal REFZ is at a low level, that is, in a refresh mode, or if the first row active signal RAST 10  is at a low level, a column fuse is not used. As a result, the unit selecting signals  9 AYF&lt;0:2&gt; become all at a low level.  
         [0067]    If the row repair identifying signal WLSTRWE becomes at a high level, the block selecting signal BS 6 A&lt;0:2&gt; selected by an external address is ignored. As a result, since the second memory cell array block has a row repair, the first unit selecting signal  9 AYF&lt;0&gt; and the third unit selecting signal  9 AYF&lt;2&gt; become all at a low level. However, if the row repair control signal RWEZ 23  becomes at a high level, the second unit selecting signal  9 AYF&lt;1&gt; becomes at a high level.  
         [0068]    [0068]FIG. 6 is a circuit diagram of the repair detector  40  of FIG. 3.  
         [0069]    The row repair detector  40  comprises NAND gates ND 6  and ND 7 , inverters INV 15  and INV 16  and a delay unit  41 . The NAND gate ND 6  performs an NAND operation on the first row repair selecting signal PRWEZ 02  and the second row repair selecting signal PRWEZ 13 . The inverter INV 15  inverts an output signal from the NAND gate ND 6 . The inverter INV 16  inverts an output signal from the inverter INV 15  to output the row repair control signal RWEZ 23 . The delay unit  41  delays the second row active signal WLSTD for a predetermined time. The NAND gate ND 7  performs an NAND operation on output signals from the inverter INV 15  and the delay unit  41  to output the row repair identifying signal WLSTRWE.  
         [0070]    Here, the delay unit  41  comprises inverters INV 17 ˜INV 22  connected in series, and NMOS-type capacitors C 1 , C 2  and C 3  connected to output terminals of the inverters INV 17 , INV 19  and INV 21 .  
         [0071]    Hereinafter, the operation of the row repair detector  40  is described.  
         [0072]    If one of the first row repair selecting signal PRWEZ 02  and the second row repair selecting signal PRWEZ 13  is at a low level, the row repair control signal RWEZ 23  becomes at a high level.  
         [0073]    If one of the first row repair selecting signal PRWEZ 02  and the second row repair selecting signal PRWEZ 13  becomes at a low level, the row repair identifying signal WLSTRWE becomes at a high level regardless of the second row active signal WLSTD.  
         [0074]    If both of the first row repair selecting signal PRWEZ 02  and the second row repair selecting signal PRWEZ 13  are at a high level, the state of the row repair identifying signal WLSTRWE is determined by that of the second row active signal WLSTD.  
         [0075]    [0075]FIG. 7 is a circuit diagram of the group selecting signal generator  50  of FIG. 3 for generating the first group selecting signal BYF&lt;0&gt; to select three upper memory cell array blocks out of 6 memory cell array blocks.  
         [0076]    The group selector  50  comprises inverters INV 23 ˜INV 26 , NOR gates NORl 9 ˜NOR 21  and an NAND gate ND 8 . The inverter INV 23  inverts a group selecting address RA 11 B. The NOR gate NOR 19  performs an NOR operation on an output signal from the inverter INV 23  and the row repair identifying signal WLSTRWE. The inverter INV 24  inverts the first row repair selecting signal PRWEZ 02 . The NOR gate NOR 20  performs an NOR operation on output signals from the NOR gate NOR 19  and the inverter INV 24 . The NAND gate ND 8  performs an NAND operation on the refresh mode signal REFZ and the first row active signal RAST 10 . The NOR gate NOR 21  performs an NOR operation on output signals from the NOR gate NOR 20  and the NAND gate ND 8 . The inverters INV 25  and INV 26  invert output signals from the NOR gate NOR 21  sequentially to output the group selecting signal BYF&lt;0&gt;. The group selecting address RA 11 B becomes at a high level when a row address AX&lt;B&gt; for selecting three upper of lower memory cell array block groups out of 6 memory cell array block is at a low level Hereinafter, the operation of the group selector  50  is described.  
         [0077]    IF the row repair identifying signal WLSTRWE becomes at a high level and the block selecting address RA 11 B becomes at a high level, the output signal from the NOR gate NOR 19  becomes at a low level.  
         [0078]    Here, if the refresh mode signal REFZ becomes at a high level and the first row active signal RAST 10  becomes at a high level, the output signal from the NAND gate ND 8  becomes at a low level. IF the first row repair selecting signal PRWEZ 02  becomes at a low level, the output signal from the NOR gate NOR 20  becomes at a low level. Thus, the output signal from the NOR gate NOR 21  becomes at a high level.  
         [0079]    As a result, the first group selecting signal BYF&lt;0&gt; for selecting  3  upper memory cell array blocks out of 6 memory cell array blocks is activated to a high level.  
         [0080]    The other group selector for generating a second group selecting signal BYF&lt;1&gt; to select  3  lower memory cell array blocks out of 0.6 memory cell array blocks is not explained because the group selector has the same structure as that of the other group selector  50 .  
         [0081]    [0081]FIG. 8 is a circuit diagram of the fuse unit  60  of FIG. 3. FIG. 8 shows a fuse unit of 3 upper memory cell array blocks out of 6 memory cell array blocks. In case of 3 lower memory cell array blocks, a fuse unit is configured to have the same structure as that of a fuse block  61  comprising fuses connected to an output terminal of the fuse block  61  so as to be activated by the second group selecting signal BYF&lt;1&gt;.  
         [0082]    The fuse unit  60  comprises a fuse block  61 , a latch unit  62 , an NAND gate ND 9  and inverters INV 27  and INV 28 . The fuse block  61 , activated by the first group selecting signal BYF&lt;0&gt;, represent a repair operation in response to unit selecting signals  9 AYF&lt;0:2&gt;. In a row active state, the PMOS transistor PM 6  sets an output terminal N 1  of the fuse block  61  to a high level in response to the precharge signal. The latch unit  62  maintains a potential of the output terminal N 1  of the fuse block  61 . The inverter INV 27  inverts the column repair test signal YREDTM. The NAND gate ND 9  performs an NAND operation on an output signal from the latch unit  62  and on output signal from the inverter INV 27 . The inverter INV 28  inverts an output signal from the NAND gate ND 8  to output the column repair control signal YRENB.  
         [0083]    Here, the fuse block  61  comprises fuses FS 1 , FS 2  and FS 3 , and NMOS transistors NM 6 ˜NM 9 . The fuses FS 1 , FS 2  and FS 3  are connected to the output terminal N 1  in parallel. The NMOS transistors NM 7 , NM 8  and NM 9  have drains connected to the fuses FS 1 , FS 2  and FS 3 , sources connected in common, and gates to receive the unit selecting signal  9 AYF&lt;0:2&gt;, respectively. The NMOS transistor NM 6  has a drain connected to the common source of the NMOS transistors NM 7 , NM 8  and NM 9 , a source connected to a ground voltage, and a gate to receive the first group selecting signal BYF&lt;0&gt;.  
         [0084]    The latch unit  62  comprises inverters INV 29  and INV 30 . An input terminal of the inverter INV 29  is connected to an output terminal of the inverter INV 30  while an input terminal of the inverter  30  is connected to an output terminal of the inverter INV 29 .  
         [0085]    When a column repair of a memory cell array block is used, the column repair control signal YRENB is maintained at the high level. However, when the column repair is not used, the column repair control signal YRENB is discharged to a low level.  
         [0086]    In this way, a column repair is used by a unit consisting of 640 or 704 wordlines instead of 512 wordlines, that is, by a memory cell array block unit. In other words, a wordline is used in each memory cell array block. As a result, the number of fuses can be reduced, thereby preventing mis-operation due to use of fuses.  
         [0087]    As described above, a column repair circuit according to an embodiment of the present invention prevents a column failure, which results from a repair operation performed only on a partial column in one memory cell array block, because each memory cell array block having the different number of wordlines is repaired by a unit of blocks.  
         [0088]    Additionally, since column repair fuses are used by a memory cell array block unit in the column repair circuit, the number of column repair fuses can be reduced, thereby preventing mis-operation due to use of fuses.