Abstract:
A gamma reference voltage generating circuit and a display device including the same are disclosed. The gamma reference voltage generating circuit includes a first voltage follower which receives a first reference voltage generated by a first digital-to-analog converter and outputs a first gamma reference voltage, an nth voltage follower which receives a second reference voltage generated by a second digital-to-analog converter and outputs an nth gamma reference voltage, where n is a natural number equal to or greater than 3, a resistor string for dividing the first gamma reference voltage and the nth gamma reference voltage, and second to (n−1)th voltage followers which receives the first gamma reference voltage and the nth gamma reference voltage divided by the resistor string and outputs second to (n−1)th gamma reference voltages.

Description:
This application claims the priority benefit of Korean Patent Application No. 10-2013-0169471 filed on Dec. 31, 2013, which is incorporated herein by reference for all purposes as if fully set forth herein. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     Embodiments of the invention relate to a gamma reference voltage generating circuit and a display device including the same. 
     2. Discussion of the Related Art 
     Various flat panel displays (FPDs), which may replace cathode ray tubes (CRTs) with disadvantageous weight and volume, have been developed. Examples of the flat panel displays include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display. Most of the flat panel displays have been put to practical use and have been selling. 
     In the flat panel displays, the liquid crystal display represents a gray scale by controlling a light transmittance of a liquid crystal layer included in a display panel depending on a magnitude of a driving voltage applied to the display panel. Further, the organic light emitting display represents a gray scale by controlling an amount of current flowing in an organic light emitting diode depending on a magnitude of a driving voltage applied to a display panel. 
     In general, a gray scale means that an amount of light, which a person perceives through his or her eyes, is divided in stages. According to Weber&#39;s law, human eyes respond nonlinearly to brightness of light. Because of this, when a person perceives changes in brightness of light through his/her eye and linearly measures the changes in the brightness of light within a limited bit depth (for example, k-bit) per channel, he/she does not smoothly feel the brightness of light and perceives the intermittent change in the brightness of light. Thus, the brightness of light needs to be nonlinearly decoded, so as to achieve the optimum image quality within the limited bit depth. For this, a process for matching driving characteristics of the display panel and characteristics perceived through human eyes is required. The matching process is called a gamma correction. A gamma correction method generally includes setting a plurality of gamma reference voltages based on the driving characteristics of the display panel, dividing each of the set gamma reference voltages, and compensating for a gamma value of each of input digital video data. 
     The gamma reference voltages are generated by using voltage followers, which are respectively connected to reference voltages generated by a plurality of digital-to-analog converters (DACs), or by connecting the voltage followers to voltages divided by a resistor string. The voltage followers stabilize the reference voltages and output final gamma reference voltages. The voltage followers implemented as buffers induce an overcurrent due to a difference between slew rates of chips at the moment that the gamma reference voltages are changed. 
     For example, when a slew rate of a first voltage follower is less than a slew rate of a second voltage follower, a change rate of the voltage in a process for changing a first gamma reference voltage gamma 1  and a second gamma reference voltage gamma 2  is shown in  FIG. 1 . Namely, as shown in  FIG. 1 , because a change rate of the first gamma reference voltage gamma 1  is less than a change rate of the second gamma reference voltage gamma 2  in a voltage change period Tt, there is a dramatic change in a difference between the first gamma reference voltage gamma 1  and the second gamma reference voltage gamma 2  at a resistance node between the first and second gamma reference voltages gamma 1  and gamma 2  Thus, overcurrent is instantaneously generated at a node of an output resistance. 
     SUMMARY OF THE INVENTION 
     Embodiments of the invention provide a gamma reference voltage generating circuit and a display device including the same capable of preventing an overcurrent from being generated at an output node of the gamma reference voltage generating circuit. 
     In one aspect, a gamma reference voltage generating circuit comprises a first voltage follower configured to receive a first reference voltage generated by a first digital-to-analog converter and output a first gamma reference voltage, an nth voltage follower configured to receive a second reference voltage generated by a second digital-to-analog converter and output an nth gamma reference voltage, where n is a natural number equal to or greater than 3, a resistor string configured to divide a voltage difference between the first gamma reference voltage and the nth gamma reference voltage, and second to (n−1)th voltage followers configured to receive the first gamma reference voltage and the nth gamma reference voltage divided by the resistor string and output second to (n−1)th gamma reference voltages. 
     In another aspect, a gamma reference voltage generating circuit comprises a first voltage follower receiving a first reference voltage from a first digital-to-analog converter and generating a first gamma reference voltage based on the first reference voltage, and a plurality of other voltage followers each generating a gamma reference voltage, where one or more of the gamma reference voltages output from said other voltage followers are generated based on the first gamma reference voltage output from the first voltage follower. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: 
         FIG. 1  illustrates a phenomenon, in which an overcurrent is induced in a gamma voltage change period; 
         FIG. 2  shows a display device according to an exemplary embodiment of the invention; 
         FIG. 3  shows a gamma reference voltage generating circuit according to a first embodiment of the invention; 
         FIG. 4  is an equivalent circuit diagram of a gamma reference voltage generating circuit shown in  FIG. 3 ; 
         FIG. 5  shows changes in a gamma reference voltage in a voltage change period; 
         FIG. 6  shows a gamma reference voltage generating circuit according to a second embodiment of the invention; 
         FIG. 7  shows a gamma reference voltage generating circuit according to a third embodiment of the invention; and 
         FIG. 8  shows a gamma reference voltage generating circuit according to a fourth embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. It will be paid attention that detailed description of known arts will be omitted if it is determined that the arts can mislead the embodiments of the invention. 
     Embodiments of the invention will be described using an organic light emitting display as an example of a display device, to which a gamma reference voltage generating circuit according to the embodiments of the invention is applied. Other display devices, for example, a liquid crystal display may be used. 
       FIG. 2  shows an organic light emitting display according to an exemplary embodiment of the invention. 
     As shown in  FIG. 2 , the organic light emitting display according to the embodiment of the invention includes a display panel  10 , on which a plurality of pixels P are arranged in a matrix form, a data driver  14 , a gate driver  13 , a timing controller  12 , and a gamma reference voltage generating circuit  15 . 
     The display panel  10  includes the plurality of pixels P and displays an image based on a gray scale represented by each pixel P. The pixels P are arranged on each of first to mth horizontal lines of the display panel  10  at uniform distance therebetween and thus are arranged in the matrix form on the display panel  10 . 
     The plurality of pixels P are respectively arranged at crossings between data lines DL and gate lines GL, which cross each other. Each pixel P includes an organic light emitting diode OLED, a driving transistor Tdr, a switching transistor Tsw, and a storage capacitor Cst. The driving transistor Tdr and the switching transistor Tsw may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor layer. The oxide TFT is advantageous to an increase in the size of the display panel  10  when considering an electron mobility, a process deviation, etc. However, the embodiment of the invention is not limited thereto. For example, the semiconductor layer of the TFT may be formed of amorphous silicon or polycrystalline silicon. 
     The organic light emitting diode OLED emits light by a driving current received from the driving transistor Tdr. The organic light emitting diode OLED includes an anode electrode, a cathode electrode, and an organic compound layer of a multi-layered structure between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer HIL, a hole transport layer HTL, a light emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. The anode electrode of the organic light emitting diode OLED is connected to a source electrode of the driving transistor Tdr, and the cathode electrode of the organic light emitting diode OLED is connected to a low potential driving voltage VSS. 
     The driving transistor Tdr controls the driving current applied to the organic light emitting diode OLED using a gate-source voltage of the driving transistor Tdr. For this, a gate electrode of the driving transistor Tdr is connected to an input terminal of a data voltage Vdata, a drain electrode of the driving transistor Tdr is connected to an input terminal of a driving voltage VDD, and the source electrode of the driving transistor Tdr is connected to the low potential driving voltage VSS. 
     The switching transistor Tsw is connected to the data line DL and the gate line GL. The switching transistor Tsw supplies a data signal to the driving transistor Tdr and the storage capacitor Cst in response to a gate signal received from the gate line GL. 
     The timing controller  12  controls driving timing of the data driver  14  and driving timing of the gate driver  13 . For this, the timing controller  12  rearranges digital video data RGB received from the outside in conformity with a resolution of the display panel  10  and supplies the rearranged digital video data RGB to the data driver  14 . The timing controller  12  generates a data control signal DDC for controlling operation timing of the data driver  14  and a gate control signal GDC for controlling operation timing of the gate driver  13  based on timing signals, such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a dot clock DCLK, and a data enable signal DE. Further, the timing controller  12  supplies switch control signals S_ON and S_OFF for controlling operation timings of first and second switches of the gamma reference voltage generating circuit  15  to the gamma reference voltage generating circuit  15 . 
     The data driver  14  drives the data lines DL. For this, the data driver  14  converts the digital video data RGB received from the timing controller  12  into an analog data voltage based on the data control signal DDC and supplies the analog data voltage to the data lines DL. The data driver  14  receives a gamma reference voltage from the gamma reference voltage generating circuit  15  and converts the digital video data RGB into an analog signal. 
     The gate driver  13  drives the gate lines GL. The gate driver  13  generates the gate signal using the gate control signal GDC received from the timing controller  12 . The gate control signal GDC includes a gate start pulse GSP indicating a start scan line, on which a scan operation starts, a gate shift clock GSC for sequentially shifting the gate start pulse GSP, and a gate output enable signal GOE indicating an output of the gate driver  13 . 
     The gamma reference voltage generating circuit  15  outputs first to nth gamma reference voltages gamma 1  to gammaN through the voltage division. The gamma reference voltage generating circuit  15  prevents an overcurrent from being generated in a process for changing the first to nth gamma reference voltages gamma 1  to gammaN. 
     Various embodiments of the gamma reference voltage generating circuit  15  are described below. 
       FIG. 3  shows a gamma reference voltage generating circuit according to a first embodiment of the invention.  FIG. 4  is an equivalent circuit diagram showing first to ninth gamma reference voltages gamma 1  to gamma 9  applied to a resistor string  140  of the data driver  14 . 
     As shown in  FIGS. 3 and 4 , the gamma reference voltage generating circuit according to the first embodiment of the invention includes first and second digital-to-analog converters (DACs) DAC 1  and DAC 2 , first and second current buffers  111  and  112 , a gamma buffer unit  130 , and a resistor string  120 . 
     The first DAC DAC 1  includes an internal resistor string (not shown) and divides a low potential voltage GND and a high potential voltage VDD to output a first reference voltage Vref 1 . In the same manner as the first DAC DAC 1 , the second DAC DAC 2  outputs a second reference voltage Vref 2 . 
     The first current buffer  111  enhances an output current of the first DAC DAC 1 , and the second current buffer  112  enhances an output current of the second DAC DAC 2 . 
     The gamma buffer unit  130  includes first to ninth voltage followers GMA 1  to GMA 9 . The first voltage follower GMA 1  is connected to an output terminal of the first DAC DAC 1 . The first voltage follower GMA 1  receives the first reference voltage Vref 1  and outputs the first gamma reference voltage gamma 1  In this instance, the first gamma reference voltage gamma 1  may be a gamma reference voltage for representing an uppermost gray level. The ninth voltage follower GMA 9  is connected to an output terminal of the second DAC DAC 2 . The ninth voltage follower GMA 9  receives the second reference voltage Vref 2  and outputs the ninth gamma reference voltage gamma 9  In this instance, the ninth gamma reference voltage gamma 9  may be a gamma reference voltage for representing a lowermost gray level. 
     The resistor string  120  is formed between the first and ninth voltage followers GMA 1  and GMA 9  and divides the first gamma reference voltage gamma 1  and the ninth gamma reference voltage gamma 9  The second to eighth voltage followers GMA 2  to GMA 8  are respectively connected to nodes between first to eighth resistors R 1  to R 8 . 
     In this instance, as shown in  FIG. 5 , because the first voltage follower GMA 1  has a low slew rate, a change rate of the first gamma reference voltage gamma 1  has a slow slope in an output voltage change period Tt. The second gamma reference voltage gamma 2  is an output voltage of the second voltage follower GMA 2  having a high slew rate, but an input voltage of the second gamma reference voltage gamma 2  is an output voltage of the first voltage follower GMA 1  having the low slew rate. Therefore, a change rate of the second gamma reference voltage gamma 2  is less than the change rate of the first gamma reference voltage gamma 1  in the output voltage change period Tt. 
     Namely, the second gamma reference voltage gamma 2  does not reverse a potential of the first gamma reference voltage gamma 1  in the output voltage change period Tt, and changes based on changes of the first gamma reference voltage gamma 1  Thus, a potential difference between a first node n 1  and a second node n 2  corresponding to both terminals of a ninth resistor R 11  of the data driver  14  is stably maintained even when the first and second gamma reference voltages gamma 1  and gamma 2  are changed. Therefore, an overcurrent is not induced. 
     In the same manner as the second gamma reference voltage gamma 2 , because the eighth gamma reference voltage gamma 8  is an output voltage of the eighth voltage follower GMA 8  following the ninth gamma reference voltage gamma 9 , a change rate of the eighth gamma reference voltage gamma 8  has a slow slope in the output voltage change period Tt. As a result, the first to ninth gamma reference voltages gamma 1  to gamma 9  according to the first embodiment of the invention may prevent overcurrent from being induced in ninth to sixteenth resistors R 11  to R 18  because of a difference between slew rates of the first to ninth voltage followers GMA 1  to GMA 9 . 
       FIG. 6  shows a gamma reference voltage generating circuit according to a second embodiment of the invention. Structures and components identical or equivalent to those illustrated in the first embodiment are designated with the same reference numerals in the second embodiment of the invention, and a further description may be briefly made or may be entirely omitted. 
     The gamma reference voltage generating circuit according to the second embodiment of the invention includes first and second DACs DAC 1  and DAC 2 , first and second current buffers  111  and  112 , a gamma buffer unit  230 , a resistor string  220 , and first and second switches SW 1  and SW 2 . 
     The first switch SW 1  is connected to a first resistor R 1  of the resistor string  220  and connects the first resistor R 1  to an output terminal of a first voltage follower GMA 1  or an output terminal of the first DAC DAC 1 . 
     The first switch SW 1  receives the switch control signals S_ON and S_OFF from the timing controller  12  and determines a connection position of the first resistor R 1  in response to the switch control signals S_ON and S_OFF. The first switch SW 1  receives the switch-on signal S_ON in an output voltage change period Tt of the first DAC DAC 1  and connects the first resistor R 1  to the output terminal of the first voltage follower GMA 1 . Further, the first switch SW 1  receives the switch-off signal S_OFF in an output voltage hold period Th of the first DAC DAC 1  and connects the first resistor R 1  to the output terminal of the first DAC DAC 1 . 
     The second switch SW 2  is connected to an eighth resistor R 8  of the resistor string  220  and connects the eighth resistor R 8  to an output terminal of a ninth voltage follower GMA 9  or an output terminal of the second DAC DAC 2 . 
     The second switch SW 2  receives the switch control signals S_ON and S_OFF from the timing controller  12  and determines a connection position of the eighth resistor R 8  in response to the switch control signals S_ON and S_OFF. The second switch SW 2  receives the switch-on signal S_ON in an output voltage change period Tt of the second DAC DAC 2  and connects the eighth resistor R 8  to the output terminal of the ninth voltage follower GMA 9 . Further, the second switch SW 2  receives the switch-off signal S_OFF in an output voltage hold period Th of the second DAC DAC 2  and connects the eighth resistor R 8  to the output terminal of the second DAC DAC 2 . 
     Namely, in the output voltage change period Tt, a second voltage follower GMA 2  follows an output voltage of the first voltage follower GMA 1 , and an eighth voltage follower GMA 8  follows an output voltage of the ninth voltage follower GMA 9 . Thus, the gamma reference voltage generating circuit according to the second embodiment of the invention may prevent overcurrent from being induced by a difference between slew rates of the voltage followers GMA 1  to GMA 9  in the output voltage change period Tt. 
     In this instance, the output voltage of the first voltage follower GMA 1  may include a riffle. When the second voltage follower GMA 2  follows the output voltage of the first voltage follower GMA 1  including the riffle, all of second to eighth gamma reference voltages gamma 2  to gamma 8  are affected by the riffle. Thus, in the output voltage hold period Th, the second voltage follower GMA 2  follows an output voltage of the first DAC DAC 1 , and the eighth voltage follower GMA 8  follows an output voltage of the second DAC DAC 2 . 
       FIG. 7  shows a gamma reference voltage generating circuit according to a third embodiment of the invention. Structures and components identical or equivalent to those illustrated in the first and second embodiments are designated with the same reference numerals in the third embodiment of the invention, and a further description may be briefly made or may be entirely omitted. 
     The gamma reference voltage generating circuit according to the third embodiment of the invention includes first to ninth DACs DAC 1  to DAC 9 , a first current buffer  111 , and a gamma buffer unit  330 . 
     The first DAC DAC 1  divides a low potential voltage GND and a high potential voltage VDD to output a first reference voltage Vref 1 . The second to ninth DACs DAC 2  to DAC 9  divide the low potential voltage GND and the first reference voltage Vref 1  to respectively output second to ninth reference voltages Vref 2  to Vref 9 . 
     A first voltage follower GMA 1  receives the first reference voltage Vref 1  from the first DAC DAC 1  and outputs a first gamma reference voltage gamma 1  In the same manner as this, second to ninth voltage followers GMA 2  to GMA 9  respectively output second to ninth gamma reference voltages gamma 2  to gamma 9 . 
     Because the second DAC DAC 2  receives the first gamma reference voltage gamma 1  as a high potential bias, the second DAC DAC 2  may prevent overcurrent from being induced by a difference between slew rates of the first voltage follower GMA 1  and the second voltage follower GMA 2 . In the same manner as this, because the third to ninth DACs DAC 3  to DAC 9  receive the first gamma reference voltage gamma 1  as the high potential bias, the third to ninth DACs DAC 3  to DAC 9  may prevent overcurrent from being induced at output nodes. 
       FIG. 8  shows a gamma reference voltage generating circuit according to a fourth embodiment of the invention. Structures and components identical or equivalent to those illustrated in the first to third embodiments are designated with the same reference numerals in the fourth embodiment of the invention, and a further description may be briefly made or may be entirely omitted. 
     The gamma reference voltage generating circuit according to the fourth embodiment of the invention includes first to ninth DACs DAC 1  to DAC 9 , a first current buffer  111 , a gamma buffer unit  430 , and first to eighth switches SW 1  to SW 8 . 
     The first switch SW 1  is formed at a high potential bias input terminal ‘c’ of the second DAC DAC 2  and is turned on or off so as to selectively receive a high potential voltage VDD or a first gamma reference voltage gamma 1 . 
     Similar to this, the second to eighth switches SW 2  to SW 8  are respectively formed at high potential bias input terminals ‘c’ of the third to ninth DACs DAC 3  to DAC 9  and are turned on or off so as to selectively receive the high potential voltage VDD or the first gamma reference voltage gamma 1 . 
     The first to eighth switches SW 1  to SW 8  receive the switch control signals S_ON and S_OFF from the timing controller  12  and determines voltage supply sources, to which the high potential bias input terminals ‘c’ are connected. The first to eighth switches SW 1  to SW 8  receive the switch-on signal S_ON in an output voltage change period Tt, are respectively connected to terminals ‘b’, and receive the first gamma reference voltage gamma 1  Further, the first to eighth switches SW 1  to SW 8  receive the switch-off signal S_OFF in an output voltage hold period Th, are respectively connected to terminals ‘a’, and receive the high potential voltage VDD. 
     Namely, the second to ninth DACs DAC 2  to DAC 9  follow an output voltage of the first voltage follower GMA 1  in the output voltage change period Tt. Thus, the second to ninth DACs DAC 2  to DAC 9  may prevent overcurrent from being induced by a difference between slew rates of the voltage followers GMA 1  to GMA 9  in the output voltage change period Tt. 
     Further, because the second to ninth DACs DAC 2  to DAC 9  receive the high potential voltage VDD in the output voltage hold period Th, second to ninth gamma reference voltages gamma 1  to gamma 9  are not affected by a riffle included in the first gamma reference voltage gamma 1 . 
     In the embodiment of the invention, voltage followers having a high slew rate follow the output voltage of a voltage follower having a low slew rate and receive the output voltage of the voltage follower having the low slew rate as its input voltage. Therefore, an embodiment of the invention may prevent overcurrent from being induced at the output node by the difference between the slew rates of the voltage followers. 
     Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.