Abstract:
A method of evaluating a PLL built-in circuit includes outputting an applied pattern signal from a test equipment synchronized with a system clock signal received by the test equipment, dividing the applied pattern signal into M/N frequencies by a frequency divider, wherein M and N are positive integers. The method further includes inputting the divided pattern signal into the PLL built-in circuit, inputting an output pattern signal outputted from the PLL built-in circuit into the test equipment and caring the output pattern signal with the applied pattern signal so as to evaluate the PLL built-in circuit. In the above method, M and N are set in a manner that a frequency of the output pattern signal from the PLL built-in circuit is substantially equal to a frequency of the system clock signal.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a PLL (Phase Locked Loop) built-in semiconductor integrated circuit (hereinafter, referred to as PLL built-in circuit), specifically to an evaluation method of a PLL built-in circuit, an evaluation system of a PLL built-in circuit, and a PLL built-in circuit containing a frequency divider. 
     Conventional test equipment stores a test pattern formed by combining an applied pattern outputted during a test and an expected pattern being an output of a normal tested device corresponding to the applied pattern in a memory. The test equipment operates on the basis of a system clock of a predetermined frequency. Generally, the PLL built-in circuit includes a PLL circuit and an F/F (Flip-Flop) circuit. 
     During a test, the test equipment inputs the applied pattern to the PLL built-in circuit synchronously with the system clock. Since the PLL circuit of the PLL built-in circuit operates at the speed of N times the system clock frequency, the output pattern of the PLL circuit switches at the frequency of N times the frequency of the applied pattern, and the output pattern of the F/F circuit (the output pattern of the PLL built-in circuit) also switches at the frequency of N times the frequency of the applied pattern. Receiving the output pattern from the PLL built-in circuit, the test equipment cares the output pattern with the expected pattern provided in advance, and thereby evaluates the PLL built-in circuit. 
     The first conventional evaluation method cares the output pattern with the expected pattern, at a timing of one time in one phase of the applied pattern outputted from the test equipment. 
     The second conventional evaluation method cares the output pattern with the expected pattern, at a timing of four times in one phase of the applied pattern outputted from the test equipment. 
     However, in the first conventional evaluation method, although the output pattern changes four times in one phase of the applied pattern, the care is executed only one time in one phase, which means that only one-fourth the number of the output pattern is cared; accordingly, the evaluation result involves a low reliability. And, the first conventional evaluation method executes the care only for one-fourth the number of the output pattern, and the evaluation of speed and access time of the PLL built-in circuit is impossible accordingly. 
     In the second conventional evaluation method, the care is executed four times in one phase of the applied pattern, but the number of the test pattern (combination of the applied pattern and the expected pattern) becomes four times the number with the case of the first conventional evaluation method, and in consequence the testing time becomes N times. 
     SUMMARY OF THE INVENTION 
     The invention may provide an evaluation method of a PLL built-in circuit, an evaluation system of a PLL built-in circuit, and a PLL built-in circuit that allow various characteristic evaluations without increasing test patterns with high reliability of the evaluation results. 
     A method of evaluating a PLL built-in circuit according the present invention includes outputting an applied pattern signal from a test equipment synchronized with a system clock signal received by the test equipment, dividing the applied pattern signal into M/N frequencies by a frequency divider, wherein M and N are positive integers. The method further includes inputting the divided pattern signal into the PLL built-in circuit, inputting an output pattern signal outputted from the PLL built-in circuit into the test equipment and caring the output pattern signal with the applied pattern signal so as to evaluate the PLL built-in circuit. In the method according to the present invention, M and N are set in a manner that a frequency of the output pattern signal from the PLL built-in circuit is substantially equal to a frequency of the system clock signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram that explains an evaluation method (or an evaluation system to implement this evaluation method) of a PLL built-in circuit relating to the first embodiment of the present invention; 
     FIG. 2 is a time chart that explains the evaluation method of a PLL built-in circuit relating to the first embodiment; 
     FIG. 3 is a block diagram that explains an evaluation method (or an evaluation system to implement this evaluation method) of a PLL built-in circuit relating to the second embodiment of the invention; 
     FIG. 4 is a time chart that explains the evaluation method of a PLL built-in circuit relating to the second embodiment; 
     FIG. 5 is a block diagram that explains an evaluation method (or an evaluation system to implement this evaluation method) of a PLL built-in circuit relating to the third embodiment of the invention; 
     FIG. 6 is a time chart that explains the evaluation method of a PLL built-in circuit relating to the third embodiment; 
     FIG. 7 is a time chart that explains another example of the evaluation method of a PLL built-in circuit relating to the third embodiment; 
     FIG. 8 is a block diagram that explains an evaluation method (or an evaluation system to implement this evaluation method) of a PLL built-in circuit relating to the fourth embodiment of the invention; and 
     FIG. 9 is a time chart that explains the evaluation method of a PLL built-in circuit relating to the fourth embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram that explains an evaluation method (or an evaluation system to implement this evaluation method) of a PLL built-in semiconductor integrated circuit (hereunder, referred to as PLL built-in circuit)  4  relating to the first embodiment of the invention. FIG. 2 is a time chart that explains the evaluation method of the PLL built-in circuit  4  relating to the first embodiment. 
     The evaluation method of the PLL built-in circuit  4  relating to the first embodiment is carried out by an evaluation system  1  illustrated in FIG.  1 . The evaluation system  1  includes test equipment  2  and a  1 /N-frequency divider  3 . 
     The test equipment  2  holds in a memory a test pattern formed by combining an applied pattern P 1  outputted during the test and an expected pattern being the output of a normal tested device corresponding to the applied pattern P 1 . The test equipment  2  operates on the basis of the system clock of a predetermined frequency. 
     The  1 /N frequency divider  3  divides the frequency of the applied pattern P 1  outputted from the test equipment  2  synchronously with the system clock into.  1 /N (N: positive integer) to generate an applied pattern P 4 , which is inputted to the PLL built-in circuit  4  being the tested device. Here, the value of N is set in such a manner that the frequency of an output pattern P 3  outputted from the PLL built-in circuit  4  becomes equal to the frequency of the system clock of the test equipment  2 . 
     The PLL built-in circuit  4  includes a PLL (Phase Locked Loop) circuit  5  and an F/F (Flip-Flop) circuit  6 . The PLL circuit  5  outputs a signal P 2  whose frequency is N times the frequency of the applied pattern P 4 . The F/F circuit  6  outputs the output pattern P 3  having the same frequency as that of the signal P 2  outputted from the PLL circuit  5 . In the first embodiment, N is equal to 4. However, N can take on an integer other than 4 (for example, any of 2, 3, 5, 6, . . . ). 
     During the test, the test equipment  2  outputs the applied pattern P 1  synchronously with the system clock; the  1 /N frequency divider  3  divides the frequency of the applied pattern P 1  into  1 /N to generate the applied pattern P 4 , which is inputted to the PLL built-in circuit  4 . The PLL circuit  5  of the PLL built-in circuit  4  operates at N times the speed of the system clock frequency to output the pattern P 2 , and the output pattern P 3  from the F/F circuit  6  is inputted to the test equipment  2 . The output pattern P 3  switches at the same frequency as that of the applied pattern P 1 . Receiving the output pattern P 3  from the PLL built-in circuit  4 , the test equipment  2  cares the output pattern P 3  with the expected pattern provided in advance at the timing illustrated by CARE in FIG. 2, and thereby evaluates the PLL built-in circuit  4 . 
     As described above, according to the evaluation method or the evaluation system relating to the first embodiment, the frequency of the applied pattern P 1 is divided into  1 /N to generate the applied pattern P 4 , which is applied to the PLL built-in circuit  4 , and the frequency of the output pattern P 3  from the PLL built-in circuit  4  is brought in coincidence with the frequency of the system clock of the test equipment  2 ; accordingly, if the test equipment  2  executes an evaluation synchronously with the system clock, the evaluation (CARE in FIG. 2) will become possible at each period of the output pattern P 3  from the PLL built-in circuit  4 . Consequently, in comparison to the conventional evaluation system (refer to FIG. 11) that executes only one evaluation to the plural periods of the output pattern P 3  from the PLL built-in circuit, the evaluation system of this embodiment achieves a higher reliability of the evaluation result of the PLL built-in circuit  4 . 
     According to the evaluation method or the evaluation system relating to the first embodiment, the frequency of the applied pattern P 1  is divided into  1 /N, which is applied to the PLL built-in circuit  4 , and the frequency of the output pattern P 3  from the PLL built-in circuit  4  is brought in coincidence with the frequency of the system clock of the test equipment  2 ; accordingly, the number of the test pattern formed by combining the applied pattern P 1  and the expected pattern being the output pattern of a normal tested device corresponding to the applied pattern P 1  can be reduced to  1 /N in comparison to the conventional system in FIG. 12, and the testing time can be shortened. Also, the reduction in the number of the test pattern will simplify the description of the test pattern, which facilitates various evaluations including a speed evaluation and access time evaluation. 
     FIG. 3 is a block diagram that explains an evaluation method of a PLL built-in circuit  14  (or an evaluation system to implement this evaluation method or a PLL built-in circuit to enable this evaluation method) relating to the second embodiment of the invention. FIG. 4 is a time chart that explains the evaluation method of the PLL built-in circuit  14  relating to the second embodiment. 
     The evaluation method of the PLL built-in circuit  14  relating to the second embodiment is carried out by an evaluation system  11  illustrated in FIG.  3 . The evaluation system  11  includes test equipment  12  and a  1 /N-frequency divider  13  incorporated in the PLL built-in circuit  14 . 
     The test equipment  12  holds in a memory a test pattern formed by combining an applied pattern P 1  outputted during the test and an expected pattern being the output of a normal tested device corresponding to the applied pattern P 1 . The test equipment  12  operates on the basis of the system clock of a predetermined frequency. 
     The  1 /N frequency divider  13  incorporated in the PLL built-in circuit  14  divides the frequency of the applied pattern P 1  outputted from the test equipment  12  synchronously with the system clock into  1 /N (N:positive integer) to generate an applied pattern P 4 , which is inputted to a PLL circuit  15 . Here, the value of N is set in such a manner that the frequency of an output pattern P 3  outputted from the PLL built-in circuit  14  becomes equal to the frequency of the system clock of the test equipment  12 . 
     The PLL built-in circuit  14  includes the PLL circuit  15 , an F/F circuit  16 , and an input line selecting circuit  18 . The input line selecting circuit  18  switches the output signal (namely, the input signal to the PLL circuit  15 ) into a signal having passed through the  1 /N frequency divider  13  during the test, or a signal having bypassed the  1 /N frequency divider  13  during the normal operation. The input line selecting circuit  18  switches the signal inputted to the PLL circuit  15  according to a selection signal inputted to a terminal  17 . The PLL circuit  15  outputs a signal that the frequency of the input signal thereto is multiplied by N. The F/F circuit  16  outputs the output pattern P 3  having the same frequency as that of the signal P 2  outputted from the PLL circuit  15 . In the second embodiment, N is equal to 4. However, N can take on an integer other than  4  (for example, any of 2, 3, 5, 6, . . . ). 
     During the test, the test equipment  12  outputs the applied pattern P 1  synchronously with the system clock; the  1 /N frequency divider  13  incorporated in the PLL built-in circuit  14  divides the frequency of the applied pattern P 1  into  1 /N to generate the applied pattern P 4 , which is inputted to the PLL circuit  15 . The PLL circuit  15  operates at N times the speed of the system clock frequency to output the pattern P 2  and the output pattern P 3  from the F/F circuit  16  is inputted to the test equipment  12 . The output pattern P 3  switches at the same frequency as that of the applied pattern P 1 . Receiving the output pattern P 3  from the PLL built-in circuit  14 , the test equipment  12  cares the output pattern P 3 with the expected pattern provided in advance at the timing illustrated by CARE in FIG. 4, and there by evaluates the PLL built-in circuit  14 . 
     As described above, according to the evaluation method, the evaluation system, or the PLL built-in circuit relating to the second embodiment, the frequency of the applied pattern P 1  is divided into  1 /N to generate the applied pattern P 4 , which is applied to the PLL circuit  15 , and the frequency of the output pattern P 3  from the PLL built-in circuit  14  is brought in coincidence with the frequency of the system clock of the test equipment  12 ; accordingly, if the test equipment  12  executes an evaluation synchronously with the system clock, the evaluation (CARE in FIG. 4) will become possible at each period of the output pattern P 3  from the PLL built-in circuit  14 . Consequently, in comparison to the conventional evaluation system (FIG. 11) that executes only one evaluation to the plural periods of the output pattern P 3  from the PLL built-in circuit, the evaluation system of this embodiment achieves a higher reliability of the evaluation result of the PLL built-in circuit  14 . 
     According to the evaluation method, the evaluation system, or the PLL built-in circuit relating to the second embodiment, the frequency of the applied pattern P 1  is divided into  1 /N, which is applied to the PLL circuit  15 , and the frequency of the output pattern P 3  from the PLL built-in circuit  14  is brought in coincidence with the frequency of the system clock of the test equipment  12 ; accordingly, the number of the test pattern formed by combining the applied pattern P 1 and the expected pattern being the output pattern of a normal tested device corresponding to the applied pattern P 1  can be reduced to  1 /N in comparison to the conventional method in FIG. 12, and the testing time can be shortened. Also, the reduction in the number of the test pattern will simplify the description of the test pattern, which facilitates various evaluations including a speed evaluation and access time evaluation. 
     According to the evaluation method, the evaluation system, or the PLL built-in circuit relating to the second embodiment, the PLL built-in circuit  14  incorporates the frequency divider  13 , which makes it possible to enhance the reliability of the evaluation result and to shorten the testing time of the PLL built-in circuit without changing the conventional testing environments (test equipment  42  in FIG.  10 ), and to facilitate various evaluations including a speed evaluation and access time evaluation. 
     FIG. 5 is a block diagram that explains an evaluation method of a PLL built-in circuit  24  (or an evaluation system to implement this evaluation method) relating to the third embodiment of the invention. FIG. 6 is a time chart that explains the evaluation method of the PLL built-in circuit  24  relating to the third embodiment, and FIG. 7 is a time chart that explains another example of the evaluation method of the PLL built-in circuit  24  relating to the third embodiment. 
     The evaluation method of the PLL built-in circuit  24  relating to the third embodiment is carried out by an evaluation system  21  illustrated in FIG.  5 . The evaluation system  21  includes test equipment  22  and an M/N frequency divider  23 . 
     The test equipment  22  holds in a memory a test pattern formed by combining an applied pattern P 1  outputted during the test and an expected pattern being the output of a normal tested device corresponding to the applied pattern P 1 . The test equipment  22  operates on the basis of the system clock of a predetermined frequency. 
     The M/N frequency divider  23  divides the frequency of an applied pattern P 1  outputted from the test equipment  22  synchronously with the system clock into M/N (M, N: positive integer) to generate an applied pattern P 4 , which is inputted to the PLL built-in circuit  24  being a tested device. Here, the values of M and N are set in such a manner that the frequency of an output pattern P 3  outputted from the PLL built-in circuit  24  becomes equal to the frequency of the system clock of the test equipment  22 . 
     The PLL built-in circuit  24  includes a PLL circuit  25  and an F/F circuit  26 . The PLL circuit  25  outputs a signal P 2  whose frequency is N times the frequency of the applied pattern P 4 . The F/F circuit  26  operates at a  1 /M frequency of the clock generated by the PLL circuit  25 . In FIG. 6, M, N are equal to 2, 4, respectively. In FIG. 7, M, N are equal to 3, 4, respectively. However, M and N are able to take on the other integers. 
     During the test, the test equipment  22  outputs the applied pattern P 1  synchronously with the system clock; the M/N frequency divider  23  divides the frequency of the applied pattern P 1  into M/N to generate the applied pattern P 4 , which is inputted to the PLL built-in circuit  24 . The PLL circuit  25  of the PLL built-in circuit  24  operates at N times the speed of the system clock frequency to output the pattern P 2 , and the frequency of the pattern P 2  is divided into  1 /M by the F/F circuit  26  to generate the output pattern P 3 , which is inputted to the test equipment  22 . The output pattern P 3  switches at the same frequency as that of the applied pattern P 1 . Receiving the output pattern P 3  from the PLL built-in circuit  24 , the test equipment  22  cares the output pattern P 3 with the expected pattern provided in advance at the timing illustrated by CARE in FIG. 6, or at the timing illustrated by CARE in FIG. 7, and thereby evaluates the PLL built-in circuit  24 . 
     As described above, according to the evaluation method or the evaluation system relating to the third embodiment, the frequency of the applied pattern P 1  is divided into M/N to generate the applied pattern P 4  which is applied to the PLL built-in circuit  24 , and the frequency of the output pattern P 3  from the PLL built-in circuit  24  is brought in coincidence with the frequency of the system clock of the test equipment  22 ; accordingly, if the test equipment  22  executes an evaluation synchronously with the system clock, the evaluation (CARE in FIG. 6 or FIG. 7) will become possible at each period of the output pattern P 3  from the PLL built-in circuit  24 . Consequently, in comparison to the conventional evaluation system (FIG. 11) that executes only one evaluation to the plural periods of the output pattern P 3  from the PLL built-in circuit, the evaluation system of this embodiment achieves a higher reliability of the evaluation result of the PLL built-in circuit  24 . 
     According to the evaluation method or the evaluation system relating to the third embodiment, the frequency of the applied pattern P 1  is divided into M/N, which is applied to the PLL built-in circuit  24 , and the frequency of the output pattern P 3  from the PLL built-in circuit  24  is brought in coincidence with the frequency of the system clock of the test equipment  22 ; accordingly, the number of the test pattern formed by combining the applied pattern P 1  and the expected pattern being the output pattern of a normal tested device corresponding to the applied pattern P 1  can be reduced to  1 /N in comparison to the conventional method in FIG. 12, and the testing time can be shortened. Also, the reduction in the number of the test pattern will simplify the description of the test pattern, which facilitates various evaluations including a speed evaluation and access time evaluation. 
     FIG. 8 is a block diagram that explains an evaluation method of a PLL built-in circuit  34  (or an evaluation system to implement this evaluation method or a PLL built-in circuit to enable this evaluation method) relating to the fourth embodiment of the invention. FIG. 9 is a time chart that explains the evaluation method of the PLL built-in circuit  34  relating to the second embodiment. 
     The evaluation method of the PLL built-in circuit  34  relating to the fourth embodiment is carried out by an evaluation system  31  illustrated in FIG.  8 . The evaluation system  31  includes test equipment  32  and an M/N frequency divider  33  incorporated in the PLL built-in circuit  34 . 
     The test equipment  32  holds in a memory a test pattern formed by combining an applied pattern P 1  outputted during the test and an expected pattern being the output of a normal tested device corresponding to the applied pattern P 1 . The test equipment  32  operates on the basis of the system clock of a predetermined frequency. 
     The M/N frequency divider  33  incorporated in the PLL built-in circuit  34  divides the frequency of the applied pattern P 1  outputted from the test equipment  32  synchronously with the system clock into M/N (M, N: positive integer) to generate an applied pattern P 4 , which is inputted to a PLL circuit  35 . Here, the value of M and N are set in such a manner that the frequency of an output pattern P 3  outputted from the PLL built-in circuit  34  becomes equal to the frequency of the system clock of the test equipment  32 . 
     The PLL built-in circuit  34  includes the PLL circuit  35 , an F/F circuit  36 , and an input line selecting circuit  38 . The input line selecting circuit  38  switches the output signal (namely, the input signal to the PLL circuit  35 ) into a signal having passed through the M/N frequency divider  33  during the test, or a signal having bypassed the M/N frequency divider  33  during the normal operation. The input line selecting circuit  38  switches the signal inputted to the PLL circuit  35  according to a selection signal inputted to a terminal  37 . The PLL circuit  35  outputs a signal that the frequency of the input signal thereto is multiplied by N. The F/F circuit  36  operates at a  1 /M frequency of the clock generated by the PLL circuit  35 . In FIG. 9, M, N are equal to 2, 4, respectively. However, M and N can take on the other integers. 
     During the test, the test equipment  32  outputs the applied pattern P 1  synchronously with the system clock; the M/N frequency divider  33  incorporated in the PLL built-in circuit  34  divides the frequency of the applied pattern P 1  into M/N to generate the applied pattern P 4 , which is inputted to the PLL circuit  35 . The PLL circuit  35  operates at N times the speed of the system clock frequency to output the pattern P 2  and the output pattern P 3  from the F/F circuit  36  is inputted to the test equipment  32 . The output pattern P 3  switches at the same frequency as that of the applied pattern P 1 . Receiving the output pattern P 3  from the PLL built-in circuit  34 , the test equipment  32  cares the output pattern P 3  with the expected pattern provided in advance, and thereby evaluates the PLL built-in circuit  34 . 
     As described above, according to the evaluation method, the evaluation system, or the PLL built-in circuit relating to the fourth embodiment, the frequency of the applied pattern P 1  is divided into M/N to generate the applied pattern P 4  which is applied to the PLL circuit  35 , and the frequency of the output pattern P 3  from the PLL built-in circuit  34  is brought in coincidence with the frequency of the system clock of the test equipment  32 ; accordingly, if the test equipment  32  executes an evaluation synchronously with the system clock, the evaluation (CARE in FIG. 9) will become possible at each period of the output pattern P 3  from the PLL built-in circuit  34 . Consequently, in comparison to the conventional evaluation system (FIG. 11) that executes only one evaluation to the plural periods of the output pattern P 3  from the PLL built-in circuit, the evaluation system of this embodiment achieves a higher reliability of the evaluation result of the PLL built-in circuit  34 . 
     According to the evaluation method, the evaluation system, or the PLL built-in circuit relating to the fourth embodiment, the frequency of the applied pattern P 1  is divided into M/N, which is applied to the PLL circuit  35 , and the frequency of the output pattern P 3  from the PLL built-in circuit  34  is brought in coincidence with the frequency of the system clock of the test equipment  32 ; accordingly, the number of the test pattern formed by combining the applied pattern P 1  and the expected pattern being the output pattern of a normal tested device corresponding to the applied pattern P 1  can be reduced to  1 /N in comparison to the conventional method in FIG. 12, and the testing time can be shortened. Also, the reduction in the number of the test pattern will simplify the description of the test pattern, which facilitates various evaluations including a speed evaluation and access time evaluation. 
     According to the evaluation method, the evaluation system, or the PLL built-in circuit relating to the fourth embodiment, the PLL built-in circuit  34  incorporates the frequency divider  33 , which makes it possible to enhance the reliability of the evaluation result and to shorten the testing time of the PLL built-in circuit without changing the conventional testing environments (test equipment  42  in FIG.  10 ), and to facilitate various evaluations including a speed evaluation and access time evaluation. 
     As the embodiments thus described, according to the evaluation method of the PLL built-in circuit set forth in claim  1 , or the evaluation system of the PLL built-in circuit set forth in claim  3 , the frequency of the applied pattern is divided into M/N, which is applied to the PLL built-in circuit, and the frequency of the output pattern from the PLL built-in circuit is brought in coincidence with the frequency of the system clock of the test equipment; therefore, if the test equipment executes an evaluation synchronously with the system clock, the evaluation will become possible at each period of the output pattern from the PLL built-in circuit. Consequently, in comparison to the conventional evaluation system (FIG. 11) that executes only one evaluation to the plural periods of the output pattern from the PLL built-in circuit, the evaluation method or the evaluation system of the invention is able to enhance the reliability of the evaluation result of the PLL built-in circuit. 
     According to the evaluation method of the PLL built-in circuit set forth in claim  1 , or the evaluation system of the PLL built-in circuit set forth in claim  3 , the frequency of the applied pattern is divided into M/N, which is applied to the PLL built-in circuit, and the frequency of the output pattern from the PLL built-in circuit is brought in coincidence with the frequency of the system clock of the test equipment; therefore, the number of the test pattern formed by combining the applied pattern and the expected pattern being the output pattern of a normal tested device corresponding to the applied pattern can be reduced to  1 /N in comparison to the conventional system in FIG. 12, and the testing time can be shortened. Also, the reduction in the number of the test pattern will simplify the description of the test-pattern, which facilitates various evaluations including a speed evaluation and access time evaluation. 
     According to the evaluation method of the PLL built-in circuit set forth in claim  2 , or the evaluation system of the PLL built-in circuit set forth in claim  4 , the frequency of the applied pattern is divided into M/N by the frequency divider incorporated in the PLL built-in circuit, which is applied to the PLL built-in circuit, and the frequency of the output pattern from the PLL built-in circuit is brought in coincidence with the frequency of the system clock of the test equipment; therefore, if the test equipment executes an evaluation synchronously with the system clock, the evaluation will become possible at each period of the output pattern from the PLL built-in circuit. Consequently, in comparison to the conventional evaluation system in FIG. 11 that executes only one evaluation to the plural periods of the output pattern from the PLL built-in circuit, the evaluation method or the evaluation system of the invention is able to enhance the reliability of the evaluation result of the PLL built-in circuit. 
     According to the evaluation method of the PLL built-in circuit set forth in claim  2 , or the evaluation system of the PLL built-in circuit set forth in claim  4 , the frequency of the applied pattern is divided into M/N by the frequency divider incorporated in the PLL built-in circuit, which is applied to the PLL built-in circuit, and the frequency of the output pattern from the PLL built-in circuit is brought in coincidence with the frequency of the system clock of the test equipment; therefore, the number of the test pattern formed by combining the applied pattern and the expected pattern being the output pattern of a normal tested device corresponding to the applied pattern can be reduced to  1 /N in comparison to the conventional system in FIG. 12, and the testing time can be shortened. Also, the reduction in the number of the test pattern will simplify the description of the test pattern, which facilitates various evaluations including a speed evaluation and access time evaluation. 
     According to the PLL built-in circuit set forth in claim  5 , the frequency of the applied pattern is divided into M/N by the frequency divider incorporated in the PLL built-in circuit, which is applied to the PLL built-in circuit, and the frequency of the output pattern from the PLL built-in circuit can be brought in coincidence with the frequency of the system clock of the test equipment; therefore, if the test equipment executes an evaluation synchronously with the system clock, the evaluation will become possible at each period of the output pattern from the PLL built-in circuit. Consequently, in comparison to the conventional evaluation system (FIG. 11) that executes only one evaluation to the plural periods of the output pattern from the PLL built-in circuit, the PLL built-in circuit of the invention is able to enhance the reliability of the evaluation result. 
     According to the PLL built-in circuit set forth in claim  5 , the frequency of the applied pattern is divided into M/N by the frequency divider incorporated in the PLL built-in circuit, which is applied to the PLL built-in circuit, and the frequency of the output pattern from the PLL built-in circuit can be brought in coincidence with the frequency of the system clock of the test equipment; therefore, the number of the test pattern formed by combining the applied pattern and the expected pattern being the output pattern of a normal tested device corresponding to the applied pattern can be reduced to  1 /N in comparison to the conventional system in FIG. 12, and the testing time can be shortened. Also, the reduction in the number of the test pattern will simplify the description of the test pattern, which facilitates various evaluations including a speed evaluation and access time evaluation. 
     According to the evaluation method of the PLL built-in circuit set forth in claim  2 , the evaluation system of the PLL built-in circuit set forth in claim  4 , or the PLL built-in circuit set forth in claim  5 , the PLL built-in circuit incorporates the frequency divider, which achieves enhancing the reliability of the evaluation result and shortening the testing time of the PLL built-in circuit without changing the conventional testing environments (test equipment  42  in FIG.  10 ), and also facilitating various evaluations including a speed evaluation and access time evaluation.