Abstract:
A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.

Description:
TECHNICAL FIELD 
     The present disclosure relates to CMOS semiconductor devices with improved shallow trench isolation. The present disclosure is particularly applicable to semiconductors 22 nanometer (nm) technology nodes and beyond. 
     BACKGROUND 
     Adverting to  FIG. 1 , as reductions in device scaling continue, spacing between PMOS and NMOS diffusions  101  and  103  shrinks, causing increasing leakage between NMOS diffusion  103  and N-well  105  and between PMOS diffusion  101  and P-well  107 . The leakage is particularly problematic for bulk CMOS devices at the 22 nm technology node and beyond. One critical leakage path  109  occurs in the 6-Transistor SRAM cell (shown with two PMOS devices  111  and  113  and two NMOS devices  115  and  117 ), though similar leakage problems occur in logic devices, IO devices, and other types of circuits. In the exemplary SRAM cell, the minimum spacing between NMOS and PMOS diffusions  101  and  103  has shrunk from 80 nm to 60 nm to 46 nm for the 45 nm-node, 32 nm-node, and 22 nm-node, respectively, thereby resulting in the failure of conventional shallow trench isolation (STI) to provide adequate isolation for 22 nm-node devices or smaller. For example, as illustrated in  FIG. 2 , under certain conditions, the N+/P-well/N-well bipolar transistor could be turned on if the P-well/N-well junction is forward biased (shown at  201 ), and, therefore, causes significant leakage through a path ( 203 ) underneath the STI region  205  between NMOS  207  and PMOS  29 , all on bulk p substrate  211 . 
     One conventional technique for reducing leakage across isolation wells is to increase the doses in the base region of the parasitic bipolar transistor. By increasing the N-well and P-well doses, the base Gummel number G B  increases, where 
                 G   B     =       ∫   0   W     ⁢         n   i   2       n   iB   2       ⁢           ⁢       N   B       D   B       ⁢     ⅆ   x           ,         
with n i  equal to the intrinsic carrier density, n iB  equal to the effective intrinsic carrier density in the base of the bipolar transistor, N B  equal to the base doping concentration, and D B  equal to the base diffusion coefficient. Therefore, according to classic bipolar junction transistor (BJT) theory, the leakage through the parasitic BJT is suppressed. However, this method requires higher well implant doses, which increases the capacitance at the P+/N-well and N+/P-well junctions, thereby degrading the performance of the MOSFET.
 
     Attempts have also been made to increase the STI trench depth from the conventional 225 nm to 265 nm at the critical N-well/P-well boundary. The extra 40 nm of STI leads to a wider base region of the parasitic BJT, resulting in a higher Gummel number, thereby improving isolation and reducing leakage current by 2 orders of magnitude. However, for 22 nm-node devices, the high aspect ratio (depth versus opening size) of about 6 makes the STI trench etch and fill process difficult, causing partially filled STI voids and other defects, which cause significant yield issues. For smaller devices, the aspect ratio will increase even further. 
     A need therefore exists for methodology enabling the formation of a CMOS device that can effectively suppress leakage current across isolation wells without etching and filling STI regions with extremely high aspect ratios, and for the resulting devices. 
     SUMMARY 
     An aspect of the present disclosure is an improved method of fabricating a semiconductor including an extended STI region. 
     Another aspect of the present disclosure is a semiconductor device including an extended STI region. 
     Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims. 
     According to the present disclosure, some technical effects may be achieved in part by a method of fabricating a semiconductor device, the method comprising: forming a recess in a silicon substrate; implanting oxygen into the silicon substrate below the recess; filling the recess with an oxide; and annealing the oxygen implanted silicon. 
     Aspects of the present disclosure include forming a liner on the sides and bottom of the recess before implanting oxygen. Further aspects include forming a capping layer on the substrate prior to forming the recess; and forming the recess in the capping layer and the substrate. Another aspect includes chemical mechanical polishing (CMP) the oxide subsequent to annealing; and removing the capping layer. Additional aspects include forming the recess by etching to a depth of 225 nanometers (nm). Other aspects include implanting oxygen to a depth of 20 nm to 50 nm below the recess. Further aspects include annealing at a temperature of 1200° C. to 1400° C. Another aspect includes implanting oxygen at an energy of 5 keV to 20 keV. Other aspects include implanting oxygen at a dose of 1E16 cm 2  to 1E17 cm 2 . Additional aspects include depositing a liner of silicon nitride at a thickness of 2 nm to 3 nm. 
     Another aspect of the present disclosure is a semiconductor device comprising: a silicon substrate; an N+ diffusion in a P-well formed in the substrate; a P+ diffusion in an N-well formed in the substrate, closely spaced from the N+ diffusion; a shallow trench isolation (STI) region between the N+ and P+ diffusions, wherein the STI region comprises: a recess in the substrate to a depth of 225 nm; a liner on the sides and bottom of the recess; an oxide filling the remainder of the recess; and a silicon oxide extension region extending 20 nm to 50 nm below the recess. 
     Aspects include a semiconductor device including the silicon oxide extension region being formed by: implanting oxygen ions in the recess prior to filling with oxide; and annealing the oxygen implanted silicon. Further aspects include the spacing between the N+ and P+ diffusions being less than 60 nm. Other aspects include the liner comprising silicon nitride at a thickness of 2 nm to 3 nm. 
     Another aspect of the present disclosure is a method of fabricating a semiconductor device, the method comprising: forming an N+ diffusion in a P-well in a silicon substrate; forming a P+ diffusion in an N-well in the substrate, closely spaced from the N+ diffusion; forming a recess in the substrate to a depth of 225 nm; forming a liner on the sides and bottom of the recess; implanting oxygen into the substrate through the bottom of the recess; filling the recess with an oxide; and annealing the oxygen implanted silicon. 
     Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which: 
         FIG. 1  schematically illustrates a prior art 6-Transistor SRAM cell; 
         FIG. 2  schematically illustrates a N+/P-well/N-well bipolar transistor of the 6-Transistor SRAM cell of  FIG. 1 ; 
         FIGS. 3A through 3H  schematically illustrate sequential steps of a method in accordance with an exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.” 
     The present disclosure addresses and solves the current leakage problem attendant upon forming a 22 nm-node or smaller CMOS device. In accordance with embodiments of the present disclosure, the STI region is extended downward into the silicon substrate by implanting oxygen through the STI recess and annealing the oxygen implanted silicon. Consequently, the STI region is extended without forming holes or voids during the oxide fill process. Therefore, current leakage is reduced without creating defects and yield issues. 
     Methodology in accordance with embodiments of the present disclosure includes forming a recess in a silicon substrate, forming a liner on the sides and bottom of the recess, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. 
     Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     A process for fabricating a semiconductor device in accordance with an embodiment of the present disclosure is illustrated in  FIGS. 3A through 3H . Adverting to  FIG. 3A , a pad silicon nitride (SiN) capping layer  301  is formed on a silicon substrate  303 , with a thermal oxide liner  305  therebetween. SiN capping layer  301  may be deposited at a thickness of 55 nm. Thermal oxide liner  305  may be formed at a thickness of 5 nm. 
     As illustrated in  FIG. 3B , STI recesses  307 A and  307 B are formed in substrate  303 , by a conventional method. Recesses  307 A may be, for example, inside wells, whereas recesses  307 B may be formed at critical leakage paths, such as at well boundaries. STI recesses  307 A and  307 B may be etched to a depth of 225 nm, for a total depth (including the oxide liner  305  and SiN capping layer  301 ) of 280 nm. 
     As shown in  FIG. 3C , a thin liner  309 , e.g., of SiN, may be conformally deposited over the entire wafer at a thickness of 2 nm to 3 nm. Liner  309  may be formed, for example, of iRAD SiN, which has excellent step coverage and uniformity. Liner  309  will protect the sidewalls of STI trenches  307 B near PMOS and NMOS diffusions close to the top surface of substrate  303  during later ion implantation. 
     Adverting to  FIG. 3D , a photoresist  311  is formed and lithographically patterned to form openings over STI trenches  307 B at critical leakage paths, such as at well boundaries, where extra isolation is required. For STI features not at critical leakage paths, STI trenches  307 A may be filled and covered with photoresist  311  to prevent the STI regions from being deepened, so that the well resistance will not be reduced. Then, oxygen, i.e., O +  ions  313 , are ion implanted in the substrate below STI trenches  307 B to form oxygen implanted silicon regions  315 . The oxygen may be implanted with a multiple energy implant. The implant energy may range from 5 keV to 20 keV, which is significantly lower than the 70 keV to 200 keV required for a conventional separation by implantation of oxygen (SIMOX) process for forming a buried oxide layer under the active silicon layer. Similarly, implant doses may range from 1E16 cm 2  to 1E17 cm 2 , as opposed to doses of at least 5E17 cm 2  for SIMOX formation. Doped silicon regions  315  may be formed to a depth of 20 to 40 nm, for example 40 nm, below the bottom of STI trenches  307 B. 
     After oxygen implantation is complete, photoresist  311  may be removed, and STI trenches  307 A and  307 B may be filled with an oxide  317 , substantially by conventional STI processing. The result of the oxide fill is illustrated in  FIG. 3E . 
     As illustrated in  FIG. 3F , a high temperature thermal anneal, for example at a temperature of 1200° C. to 1400° C., in an inert ambient is performed to convert the oxygen implanted silicon  315  to silicon dioxide  315 ′. 
     Adverting to  FIG. 3G  the STI oxide  317  is chemical mechanical polished (CMP), stopping on SiN capping layer  301 . Then, the remaining SiN capping layer  301  is removed, for example by wet etching, as illustrated in  FIG. 3H . The PMOS and NMOS devices may then be formed on silicon substrate  303 , separated by the extended STI regions. 
     The embodiments of the present disclosure can achieve several technical effects, including suppressed leakage current across isolation wells without etching and filling STI regions with extremely high aspect ratios, thereby avoiding STI voids and other defects. The present disclosure enjoys industrial applicability in any of various types of highly integrated semiconductor devices such as SRAMs, logic devices, and IO devices, particularly 22 nanometer (nm) node devices and beyond. 
     In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.