Abstract:
An array substrate of a liquid crystal display device includes a substrate, a plurality of gate lines disposed on the substrate, a plurality of data lines disposed perpendicular to the gate lines, a plurality of storage capacitors each having at least a first electrode disposed parallel to a corresponding gate line, a plurality of switching devices each electrically connected with the corresponding gate line and a corresponding data line, and a plurality of pixel electrodes each overlapping a portion of an n th  storage capacitor and a portion of a (n−1) th  storage capacitor.

Description:
[0001]    This application claims the benefit of Korean patent application No. 2000-56225, filed Sep. 25, 2000 in Korea, which is hereby incorporated by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a liquid crystal display (LCD) device, and more particularly to a liquid crystal display device having thin film transistors (TFTs).  
           [0004]    2. Discussion of the Related Art  
           [0005]    Currently, LCD devices of light weight, thin design, and low power consumption are used in office automation equipment and video units, for example. These LCD devices typically use optical anisotropy of a liquid crystal, wherein thin, long liquid crystal molecules are manipulated for orientation alignment. The alignment direction of the liquid crystal molecules is controlled by application of an electric field to the liquid crystal molecules. When the alignment direction of the liquid crystal molecules are properly adjusted, the liquid crystal is aligned and light is refracted along the alignment direction of the liquid crystal molecules to display image data.  
           [0006]    Presently, an active matrix (AM) LCD having a plurality of thin film transistors (TFTs) and pixel electrodes are arranged in shape of an array matrix is proposed because of its high resolution and superiority in displaying moving images. Each of the plurality of TFTs serve to switch a corresponding pixel to transmit incident light. Since amorphous silicon is relatively easy formed on large, inexpensive glass substrates, amorphous silicon thin film transistors (a-Si:H TFTs) are widely used. Alternatively, polysilicon (poly-Si) TFTs having polysilicon active layers have recently been developed to function as switching devices for the LCD devices. Since electron mobility of polysilicon is 100 to 200 times higher than the electron mobility of amorphous silicon, polysilicon TFTs exhibit superior response times. Polysilicon TFTs further exhibit superior stability against temperature and light, and circuits for driving the polysilicon TFTs can be formed on the same substrate where the polysilicon TFTs are formed.  
           [0007]    [0007]FIGS. 1 and 2 show a conventional array substrate  1  having a polysilicon TFT.  
           [0008]    In FIG. 2, a buffer layer  20  made of silicon oxide, for example, is formed on a substrate  10 . A TFT active layer  31 , a source region  32 , a drain region  33 , and a storage portion  35  including side portions  35   b  and  35   c,  and a capacitor active layer  35   a  formed of polysilicon, are formed on the buffer layer  20 . The source region  32 , the drain region  33 , and the side portions  35   b  and  35   c  of the storage portion  35  are doped with impurities. A gate insulating layer  40  is formed to cover the TFT active layer  31  and the capacitor active layer  35   a,  and a gate electrode  52  and a capacitor electrode  55  are formed respectively over the TFT active layer  31  and the capacitor active layer  35   a.  The gate electrode  52  is integrally connected with a gate line  51   a.  The storage portion  35  and the capacitor electrode  55  comprise a storage capacitor “C.” An interlayer-insulating layer  60  formed of silicon oxide or silicon nitride is formed to cover the gate electrode  52  and the capacitor electrode  55 . The interlayer-insulating layer  60  includes a first contact hole  61  and a second contact hole  62  that expose the source region  32  and the drain region  33 , respectively.  
           [0009]    A data line  71 , a source electrode  72 , and a drain electrode  73  are formed of a conductive material such as metal, for example, on the interlayer insulating layer  60 . The data line  71  perpendicularly crosses gate lines  51   a  and  51   b,  thereby defining a pixel region “P.” The source electrode  72  integrally protrudes from the data line  71 , and the drain electrode  73  is disposed opposite to the source electrode  71  with the gate electrode  52  centered therebetween. The source and drain electrode  72  and  73  are respectively connected with the source and drain region  32  and  33  via the first and second contact holes  61  and  62 .  
           [0010]    A passivation layer  80  covers an overall surface of the substrate  10  where the above-described layers are formed. A third contact hole  81  is formed through the passivation layer  80 , thereby exposing the drain electrode  73 . A pixel electrode  91  is formed on the passivation layer  80  and electrically contacts the drain electrode  73  via the third contact hole  81 . In the above-described structure, the capacitor electrode  55  and the storage portion  35  of the storage capacitor “C” are independently formed in the pixel region “P,” and a bias voltage is applied to the capacitor active layer  35   a  such that the capacitor active layer  35   a  is always turned on.  
           [0011]    [0011]FIGS. 3A to  3 D, show a fabrication method for the conventional array substrate  1  shown in FIG. 2.  
           [0012]    In FIG. 3A, the buffer layer  20  formed of silicon oxide is disposed on the substrate  10 . Then, a polysilicon layer  30  is formed on the buffer layer and subsequently patterned. A laser annealing method, a metal induced crystallization (MIC) method, a solid phase crystallization (SPC) method, or a direct deposition method may be applied to form the polysilicon layer  30 . In the laser annealing method, the substrate is heated to a temperature of about 250° C. (degrees. C.), and an excimer laser beam is applied to an amorphous silicon layer formed on the substrate. In the MIC method, metal is deposited on an amorphous silicon layer, to function as a crystallization seed. In the SPC method, an amorphous silicon layer is heat-treated at a high temperature for a long time. Generally, in both the MIC and SPC methods, an amorphous silicon layer is deposited and recrystallized to form the polysilicon layer  30 . When the amorphous silicon layer is recrystallized to form the polysilicon layer, heat is produced, thereby activating alkali ions, such as K+ and Na+, of the substrate  10 . At this point, the buffer layer  20  separates the polysilicon layer  30  from the substrate  10 , thereby providing protection from the activated alkali ions of the substrate  10 .  
           [0013]    In FIG. 3B, an insulating layer made of silicon oxide or silicon nitride and a metal layer are sequentially deposited and patterned to form the gate electrode  52 , the capacitor electrode  55 , and the gate insulating layer  40  on the polysilicon layer  30 . Then, the polysilicon layer  30  is subjected to ion doping such that portions of the polysilicon layer  30 , except for portions under the gate electrode  52  and the capacitor electrode  55 , are doped. Due to the ion-doping, contact resistance increases between the polysilicon layer  30  and a metal layer forming the source and drain electrodes  72  and  73 , which will be formed in a later process.  
           [0014]    After the polysilicon layer  30  is doped, it is divided into extrinsic regions  32 ,  33 ,  35   b,  and  35   c  and intrinsic pure regions  31  and  35   a.  The extrinsic regions  32  and  33  respectively serve as the source region and the drain region, and the intrinsic region  31  serves as the TFT active layer. For the ion doping, a source gas may include atoms selected from Group III or Group V materials. If a source gas containing atoms of Group V materials is used to form the doped source and drain regions  32  and  33 , the source and drain regions  32  and  33  become n-type silicon. If a source gas containing atoms of Group III materials are used, the source and drain regions  32  and  33  become p-type silicon.  
           [0015]    In FIG. 3C, silicon oxide or silicon nitride is deposited to cover the surface of the substrate  10  and is subsequently patterned to form the interlayer insulating layer  60  to include the first and second contact holes  61  and  62 . The first and second contact holes  61  and  62  expose the source region  32  and the drain region  33 , respectively. At this point, the gate electrode  52  and the capacitor electrode  55  are completely covered by the interlayer insulating layer  60 , thereby providing electrical insulation from the source and drain electrode  72  and  73 , which will be formed in a later process.  
           [0016]    In FIG. 3D, metal is deposited and subsequently patterned to form the data line  71 , the source electrode  72 , and the drain electrode  73 . The data line  71  orthogonally crosses the gate lines  51   a  and  51   b  (in FIG. 1), and the source and drain electrodes  72  and  73  contact the source and drain regions  32  and  33  via the first and second contact holes  61  and  62 , respectively.  
           [0017]    Returning to FIG. 2, the passivation layer  80  is formed to cover the surface of the substrate  10  where the source and drain electrodes  72  and  73  are formed. At this point, the passivation layer  80  is patterned such that the third contact hole  81  is formed therethrough to expose a contact portion of the drain electrode  73 . Then, a transparent conductive material is deposited on the passivation layer  80  and subsequently patterned, thereby forming the pixel electrode  91 . The pixel electrode  91  is disposed in the pixel region “P” defined by the gate lines  51   a  and  51   b  and the data line  71 , and is electrically connected with the contact portion of the drain electrode  73  via the third contact hole  81 .  
           [0018]    In the above-described array substrate shown in FIG. 1, although the pixel electrode  91  overlaps the gate line  51   b  and the data line  71  to increase an aperture ratio, an interval is conventionally interposed between the pixel electrode  91  and the gate line  51   a,  which are disposed in the same pixel region “P.” The interval between the pixel electrode  91  and the gate line  51  a minimizes any capacitive coupling. Accordingly, if the pixel electrode  91  is spaced apart from the gate line  51   a  by an interval of 2 to 3 μm (micrometer), any induced parasitic capacitance is decreased, thereby creating a uniform displaying quality and decreasing any associated cross-talk.  
           [0019]    However, the interval causes misalignment of some liquid crystal molecules (not shown) that are disposed near the interval. The misalignment of the liquid crystal molecules results in a deterioration of the display quality. Therefore, a black matrix (not shown) is usually used to shield the interval and for preventing light from passing through the interval. However, the black matrix deteriorates the aperture ratio and increases power consumption of the LCD device.  
         SUMMARY OF THE INVENTION  
         [0020]    Accordingly, the present invention is directed to an array substrate and a fabrication method thereof that substantially obviate one or more of problems due to limitations and disadvantages of the related art.  
           [0021]    An object of the present invention is to provide an array substrate of a LCD device having high aperture ratio, low parasitic capacitance, and high storage capacitance.  
           [0022]    Another object of the present invention is to provide a LCD device with improved display quality.  
           [0023]    Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
           [0024]    To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an array substrate of a liquid crystal display device includes a substrate, a plurality of gate lines disposed on the substrate, a plurality of data lines disposed perpendicular to the gate lines, a plurality of storage capacitors each having at least a first electrode disposed parallel to a corresponding gate line, a plurality of switching devices each electrically connected with the corresponding gate line and a corresponding data line, and a plurality of pixel electrodes each overlapping a portion of an n th  storage capacitor and a portion of a (n−1) th  storage capacitor.  
           [0025]    In another aspect, a method of fabricating an array substrate for a liquid crystal display device includes steps of forming a first insulating layer on a substrate, forming a polysilicon layer on the first insulating layer, sequentially forming a second insulating layer and a first metal layer on the polysilicon layer, the first metal layer including a gate line, a gate electrode, and a capacitor electrode, doping portions of the polysilicon layer, forming a third insulating layer to cover the first metal layer and the doped portions of the polysilicon layer, the third insulating layer including contact holes exposing the doped portions of the polysilicon layer, forming a second metal layer on the third insulating layer, the second metal layer including at least a data line and a connecting electrode each electrically contacting the doped portions of the polysilicon layer via the contact holes, forming a fourth insulating layer to cover the second metal layer, wherein a portion of the connecting electrode is through the fourth insulating layer, and forming a pixel electrode on the fourth insulating layer, the pixel electrode electrically contacting the connecting electrode, an end portion of the pixel electrode overlapping a portion of the capacitor electrode.  
           [0026]    In another aspect, a fabrication method for a liquid crystal display device includes steps of forming a first metal layer on a substrate, the first metal layer including at least a gate line, a gate electrode, and a first capacitor electrode, forming a gate insulating layer to cover the first metal layer, forming a silicon layer on the gate insulating layer, forming an ohmic contact layer on the silicon layer, forming a second metal layer on the ohmic contact layer, the second metal layer including at least a source electrode, a drain electrode, and a second capacitor electrode, forming a passivation layer to cover the second metal layer, the passivation layer including at least a contact hole exposing a portion of the second capacitor electrode; and forming a pixel electrode on the passivation layer, the pixel electrode electrically connected to the second capacitor electrode via the contact hole, wherein an end of the pixel electrode overlaps a portion of the first capacitor electrode.  
           [0027]    In another aspect, an array substrate of a liquid crystal display device includes a substrate, a plurality of gate lines disposed on the substrate, a plurality of data lines disposed perpendicular to the gate lines, a plurality of storage capacitors each having at least a first electrode disposed parallel to a corresponding gate line and a second electrode disposed parallel to a corresponding data line, a plurality of switching devices each electrically connected with the corresponding gate line and a corresponding data line, and a plurality of pixel electrodes each electrically connected with a second electrode of one of the plurality of storage capacitors, wherein the second electrode includes first and second portions each disposed opposing the first electrode.  
           [0028]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:  
         [0030]    [0030]FIG. 1 is a plan view showing an array substrate of a LCD device according to the related art;  
         [0031]    [0031]FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1;  
         [0032]    [0032]FIG. 3A to  3 D are cross-sectional views showing a sequence of fabricating the array substrate of FIG. 1;  
         [0033]    [0033]FIG. 4 is a plan view showing an exemplary array substrate of a LCD device according to the present invention;  
         [0034]    [0034]FIG. 5 is a cross-sectional view taken along line V-V of FIG. 4;  
         [0035]    [0035]FIGS. 6A to  6 D are cross-sectional views showing an exemplary sequence of fabricating an array substrate of FIG. 4;  
         [0036]    [0036]FIG. 7 is a plan view showing another exemplary array substrate of a LCD device according to the present invention;  
         [0037]    [0037]FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. 7;  
         [0038]    [0038]FIG. 9 is a plan view showing another exemplary array substrate of a LCD device according to the present invention;  
         [0039]    [0039]FIG. 10 is a cross-sectional view taken along line X-X of FIG. 9;  
         [0040]    [0040]FIG. 11 is a plan view showing another exemplary array substrate of a LCD device according to the present invention; and  
         [0041]    [0041]FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 11. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0042]    Reference will now be made in detail to the preferred embodiment of the present invention, which is illustrated in the accompanying drawings.  
         [0043]    [0043]FIG. 4 is a plan view showing an exemplary array substrate  100  of a LCD device according to the present invention, and FIG. 5 is a cross-sectional view taken along line V-V of FIG. 4.  
         [0044]    In FIGS. 4 and 5, a buffer layer  120  made of silicon oxide, for example, may be formed on a substrate  110 . A TFT active layer  131 , a source region  132 , a drain region  133 , and a storage portion  135  formed of polysilicon, may be formed on the buffer layer  120 . The storage portion  135  may include a capacitor active layer  135   a,  a first side portion  135   b,  and a second side portion  135   c.  The source region  132 , the drain region  133 , and the first and second side portions  135   b  and  135   c  of the storage portion  135  may be made of doped polysilicon layers.  
         [0045]    A gate insulating layer  140  may be formed to cover the TFT active layer  131  and the capacitor active layer  135   a,  and a gate electrode  152  and a capacitor electrode  155  may be formed over the TFT active layer  131  and the capacitor active layer  135   a  , respectively. The gate electrode  152 , the TFT active layer  131 , and the source and drain regions  132  and  133  may comprise a switching device “S,” with the storage portion  135  and the capacitor electrode  155  comprising a storage capacitor “C.” The gate electrode  152  may be orthogonal to and integrally connected with a gate line  151   a.  An interlayer-insulating layer  160  may be formed of silicon oxide or silicon nitride, for example, to cover the gate electrode  152  and the capacitor electrode  155 . The interlayer-insulating layer  160  may include a first contact hole  161 , a second contact hole  162 , and a third contact hole  163  that expose contact portions of the source region  132 , the drain region  133 , and the second side portion  135   c  of the storage portion  135 , respectively.  
         [0046]    A data line  171  and a connecting electrode  174  may be formed of a conductive material such as metal, for example, formed on the interlayer insulating layer  160 . The data line  171  perpendicularly crosses gate lines  151   a  and  151   b.  Moreover, the data line  171  may be electrically connected with a contact portion of the source region  132  via the first contact hole  161 . The connecting electrode  174  may be electrically connected with a contact portion of the drain region  133  and the second side portion  135   c  of the storage portion  135 , respectively, via the second and third contact holes  162  and  163 .  
         [0047]    A passivation layer  180  may be formed to cover a surface of the substrate  110  where the above-described layers are formed. A fourth contact hole  181  may be formed passing through the passivation layer  180 , thereby exposing a contact portion of the connecting electrode  174  that is disposed over the second side portion  135   c  of the storage portion  135 . First to third pixel electrodes  191   a  to  191   c  may be formed on the passivation layer  180 .  
         [0048]    The first and second pixel electrodes  191   a  and  191   b  may be separated by an interval  190  disposed over the capacitor electrode  155 . The second pixel electrode  191   b  electrically contacts a contact portion of the connecting electrode  174  via the fourth contact hole  181  such that the second pixel electrode  191   b  receives signals from the gate line  151   a  to serve as a “present” pixel electrode. The first pixel electrode  191   a  receives signals from another gate line (not shown) to serve as a “next” pixel electrode, and the third pixel electrode  191   a  receives signals from the gate line  151   b  to serve as a “previous” pixel electrode. Accordingly, in the present exemplary array substrate, a pixel region “P” is surrounded by the capacitor electrode  155 , a “previous” capacitor electrode  156 , and the data line  171 .  
         [0049]    The second pixel electrode  191   b,  serving as the “present” pixel electrode, may overlap edge portions of the capacitor electrode  155 , the capacitor electrode  156 , and the data line  171 . Moreover, since the second pixel electrode  191   b  may overlap the gate line  151   b,  there exists no interval between the gate line  151   b  and the pixel electrode  191   b,  thereby achieving a higher aperture ratio. Furthermore, though some parasitic capacitive coupling may be induced between the second pixel electrode  191   b  and the gate line  151   b,  since the second pixel electrode  191   b  receives signals from the gate line  151   a  and not the gate line  151   b,  the parasitic capacitive coupling has little effect on display quality. On the contrary, the parasitic capacitive coupling induced between the second pixel electrode  191   b  and the capacitor electrode  156  may provide additional storage capacitance, thereby providing the same effect as increasing the capacitance of the storage capacitor “C.” 
         [0050]    [0050]FIGS. 6A to  6 D show an exemplary fabrication method for the array substrate  100  shown in FIG. 5 according to the present invention.  
         [0051]    In FIG. 6A, the buffer layer  120  may be formed of silicon oxide, for example, on the substrate  110 , and then, a polysilicon layer  130  may be formed thereon and subsequently patterned. To form the polysilicon layer  130 , an amorphous silicon layer may be deposited and recrystallized on the buffer layer  120 . Since, the buffer layer  120  separates the polysilicon layer  130  from directly contacting the substrate  110 , degradation of the polysilicon layer  130  may be avoided during recrystallization.  
         [0052]    In FIG. 6B, an insulating layer made of silicon oxide or silicon nitride, for example, and a metal layer are sequentially deposited and subsequently patterned to form the gate electrode  152 , the capacitor electrode  155 , and the gate insulating layer  140  on the polysilicon layer  130 . Then, ion doping may be applied to the polysilicon layer  130  such that portions of the polysilicon layer  130 , except for portions under the gate electrode  152  and the capacitor electrode  155 , are doped. After ion doping, the polysilicon layer  130  may be divided into extrinsic regions  132 ,  133 ,  135   b,  and  135   c  and intrinsic regions  131  and  135   a.  The extrinsic regions  132  and  133  may serve as the source region and the drain region, respectively, and the intrinsic region  131  may serve as the TFT active layer. Further, the other extrinsic regions  135   b,    135   c  and the other intrinsic region  135   a  may comprise the storage portion  135 .  
         [0053]    In FIG. 6C, silicon oxide or silicon nitride may be deposited to cover a surface of the substrate  110  and subsequently patterned to form the interlayer insulating layer  160  and the first to third contact holes  161  and  163 . The first to third contact holes  161  and  163  expose contact portions of the source region  132 , the drain region  133 , and the second side portion  135   c  of the storage portion  135 , respectively.  
         [0054]    In FIG. 6D, a metal material may be deposited and patterned to form the data line  171  and the connecting electrode  174 . The data line  171  may perpendicularly cross the gate lines  151   a  and  151   b  (in FIG. 4) and contact a portion of the source region  132  via the first contact hole  161 . The connecting electrode  174  may contact a portion of the drain region  133  and the second side portion  135   c  of the storage portion  135 , respectively, via the second and third contact holes  162  and  163 .  
         [0055]    Returning to FIG. 5, the passivation layer  180  may be formed to cover a surface of the substrate  110  where the data line  171  and the connecting electrode  174  are formed. Then, the passivation layer  180  may be patterned, thereby forming the fourth contact hole  181  to expose the portion of the connecting electrode  174  disposed over the third contact hole  163 . Next, a transparent conductive material may be deposited on the passivation layer  180  and subsequently patterned to form the first and second pixel electrode l 91   a  and  191   b.  The first and second pixel electrodes l 91   a  and l 91   b  may be separated from each other by the interval  190  interposed therebetween and disposed over the capacitor electrode  155 . The second pixel electrode  191   b  may contact the connecting electrode  174  via the fourth contact hole  181 . In addition, the second pixel electrode  191   b  may overlap edge portions of the data line  171  and the capacitor electrode  155  and at least a portion of the gate line  151   b.  The first pixel electrode  191   a  may overlap another edge portion of the capacitor electrode  155  and at least a portion of the gate line  151   a  that applies signals to the second pixel electrode  191   b.    
         [0056]    In the above-described exemplary array substrate of the present invention, instead of forming a source electrode and a drain electrode, the source and drain regions  132  and  133  may be disposed around the TFT active layer  131  and contact the data line  171  and the connecting electrode  174 , respectively. Alternatively, the source and drain electrodes may be additionally formed connecting with the data line  131  and the connecting electrode  174 , respectively, and may contact the source and drain regions  132  and  133 , respectively.  
         [0057]    As described above, the first and second pixel electrodes  191   a  and  191   b  may be separated from each other by the interposed interval  190  disposed over the capacitor electrode  155 . Since the second pixel electrode  191   b  overlaps the gate line  151   b  and not the gate line  151   a,  any parasitic capacitive coupling decreases and the capacitance of the storage capacitor “C” and the aperture ratio increase.  
         [0058]    In the above-described exemplary array substrate of the present invention, the connecting electrode  174  may be made of the same material as the data line  171  that contacts the drain region  133  and the second pixel electrode  191   b  for transmitting signals between the drain region  133  and the second pixel electrode  191   b.  However, a doped polysilicon layer may be used to transmit signals from the drain region  133  to the second pixel electrode  191   b,  thereby achieving a higher aperture ratio.  
         [0059]    [0059]FIG. 7 is a plan view showing another exemplary array substrate  200  of a LCD device according to the present invention, and FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. 7.  
         [0060]    In FIGS. 7 and 8, a buffer layer  120  made of silicon oxide, for example, may be formed on a substrate  110 . A TFT active layer  131 , a source region  132 , a drain region  133 , and a storage portion  135  formed of polysilicon, may be formed on the buffer layer  120 . The storage portion  135  may include a capacitor active layer  135   a,  a first side portion  135   b,  and a second side portion  135   c.  The source region  132 , the drain region  133 , and the first and second side portions  135   b  and  135   c  of the storage portion  135  may be doped with impurities.  
         [0061]    A gate insulating layer  140  may be formed to cover the TFT active layer  131  and the capacitor active layer  135   a,  and a gate electrode  152  and a capacitor electrode  155  may be formed over the TFT active layer  131  and the capacitor active layer  135   a,  respectively. The gate electrode  152  may be orthogonal to and integrally connected with a gate line  151   a.  The storage portion  135  and the capacitor electrode  155  may comprise a storage capacitor “C.” An interlayer-insulating layer  160  may be formed of silicon oxide or silicon nitride, for example, to cover the gate electrode  152  and the capacitor electrode  155 . The interlayer-insulating layer  160  may include a first contact hole  161  and a second contact hole  162 , which expose contact portions of the source region  132  and the second side portion  135   c  of the storage portion  135 , respectively.  
         [0062]    A data line  171  and a connecting electrode  274  may be formed of a conductive material such as metal, for example, on the interlayer insulating layer  160 . The data line  171  may perpendicularly cross gate lines  151   a  and  151   b.  Moreover, the data line  171  may be electrically connected with a contact portion of the source region  132  via the first contact hole  161 . The connecting electrode  274  may be disposed over the second side portion  135   c  of the storage portion  135 , and electrically connected with the second side portion  135   c  via the second contact hole  162 .  
         [0063]    A passivation layer  180  may be formed to cover a surface of the substrate  110  where the above-described layers are formed. A third contact hole  181  may be formed passing through the passivation layer  180 , thereby exposing a contact portion of the connecting electrode  274 . A first pixel electrode  191   a  and a second pixel electrode  191   b  may be formed on the passivation layer  180 . The first and second pixel electrodes  191   a  and  191   b  may be separated from each other by an interposed interval  190  disposed over the capacitor electrode  155 . The second pixel electrode  191   b  may overlap the gate line  151   b  and an edge portion of the capacitor electrode  155 .  
         [0064]    Since the interposed interval  190  is disposed over the capacitor electrode  155 , the exemplary array substrate  200  may benefit from the same advantages as those of the exemplary array substrate  100  (in FIG. 4). Moreover, since the doped side portions of the polysilicon layer are used to transmit signals from the drain region  133  to the second pixel electrode  191   b,  the exemplary array substrate  200  provides a higher aperture ratio. However, if doped polysilicon is used to transmit signals, more response delay may occur.  
         [0065]    [0065]FIG. 9 is a plan view showing another exemplary array substrate  300  of a LCD device according to the present invention, and FIG. 10 is a cross-sectional view taken along line X-X of FIG. 9.  
         [0066]    In FIG. 10, a connecting electrode  374  made of metal, for example, may be implemented to improve response quality. The connecting electrode  374  may electrically connect a drain region  133  with a second pixel electrode  191   b.  Moreover, the second pixel electrode  191   b  may contact the connecting electrode  374  that is disposed over a capacitor electrode  155 , thereby improving the aperture ratio.  
         [0067]    In FIGS. 9 and 10, a buffer layer  120  made of silicon oxide, for example, may be formed on a substrate  110 . A TFT active layer  131 , a source region  132 , a drain region  133 , and a storage portion  135  formed of polysilicon, may be formed on the buffer layer  120 . The storage portion  135  may include a capacitor active layer  135   a,  a first side portion  135   b,  and a second side portion  135   c.  The source region  132 , the drain region  133 , and the first and second side portions  135   b  and  135   c  of the storage portion  135  may be doped with impurities.  
         [0068]    A gate insulating layer  140  may be formed to cover the TFT active layer  131  and the capacitor active layer  135   a,  and a gate electrode  152  and a capacitor electrode  155  may be formed over the TFT active layer  131  and the capacitor active layer  135   a,  respectively. The gate electrode  152  may be orthogonal to and integral with a gate line  151   a.  The storage portion  135  and the capacitor electrode  155  may comprise a storage capacitor “C.” An interlayer-insulating layer  160  may be formed of silicon oxide or silicon nitride, for example, to cover the gate electrode  152  and the capacitor electrode  155 . The interlayer-insulating layer  160  may include a first contact hole  161  and a second contact hole  162 , which expose contact portions of the source region  132  and the drain region  133 , respectively.  
         [0069]    A data line  171  and a connecting electrode  374  may be formed of a conductive material such as metal, for example, on the interlayer insulating layer  160 . The data line  171  may perpendicularly cross gate lines  151   a  and  151   b.  Moreover, the data line  171  may be electrically connected with a contact portion of the source region  132  via the first contact hole  161 , and the connecting electrode  374  may be electrically connected with contact portions of the drain region  133  via the second contact hole  162 .  
         [0070]    A passivation layer  180  may be formed to cover a surface of the substrate  110  where the above-described layers are formed. A third contact hole  181  may be formed passing through the passivation layer  180 , thereby exposing a contact portion of the connecting electrode  374  disposed over the capacitor electrode  155 . A first pixel electrode  191   a  and a second pixel electrode  191   b  may be formed on the passivation layer  180 , and the first and second pixel electrodes  191   a  and  191   b  may be separated from each other by an interposed interval  190  disposed over the capacitor electrode  155 . The second pixel electrode l 91   b  may overlap the previous gate line  151   b  and an edge portion of the capacitor electrode  155 .  
         [0071]    Although the above-described examples of the present invention implement polysilicon active layers, pixel structures may be implemented with amorphous silicon active layers.  
         [0072]    [0072]FIG. 11 is a plan view showing another exemplary array substrate  400  of a LCD device according to the present invention, and FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 11.  
         [0073]    In FIGS. 11 and 12, a gate line  221 , a gate electrode  222  protruding from the gate line  221 , and a first capacitor electrode  225  disposed parallel to the gate line may all be formed of metal, for example, on a substrate  210 . A gate insulating layer  230  made of silicon oxide or silicon nitride, for example, may be disposed covering the gate line  221 , the gate electrode  222 , and the first capacitor electrode  225 . A first silicon layer  241  and a second silicon layer  245  may be disposed on the gate insulating layer  230 . A first ohmic contact layer  252  and a second ohmic contact layer  255  may be disposed on the first and second silicon layers  241  and  245 , respectively. The first and second ohmic contact layer  252  and  255  may be made of a doped amorphous silicon, for example. A data line  261 , a source electrode  262 , and a drain electrode  263  may be disposed on the first ohmic contact layer  252 , and a second capacitor electrode  265  may be disposed on the second ohmic contact layer  255 . The data line  261  may perpendicularly cross the gate line  221 , and the source electrode  262  may be integrally connected with the data line  261 . The drain electrode  263  may be spaced apart from the source electrode  262  with the gate electrode centered on therebetween, and may be electrically connected with the second storage electrode  265 . The gate electrode  221 , the source electrode  262 , the drain electrode  263 , the first silicon layer  241 , and the first ohmic contact layer  252  may comprise a switching device “S.” The first capacitor electrode  225 , the second capacitor electrode  265 , the second ohmic contact layer  255 , and the second silicon layer  245  may comprise a storage capacitor “C.” A passivation layer  270  may be disposed to cover the data line  261 , the source and drain electrodes  262  and  263 , and the second capacitor electrode  265 . A contact portion of the second capacitor electrode  265  may be exposed through the passivation layer  270  via a contact hole  271 .  
         [0074]    A first pixel electrode  281   a  and a second pixel electrode  281   b  may be disposed on the passivation layer  270 , and an interval  290  between the first and second pixel electrodes  281   a  and  281   b  may be disposed over the second capacitor electrode  265 . The first and second pixel electrodes  181   a  and  181   b  may be separated from each other by the interval  290  interposed therebetween, and the interval may be disposed over the second capacitor electrode  265 . The second pixel electrode  181   b  may overlap a gate line  221   a  and an edge portion of the second capacitor electrode  265 . Furthermore, the second pixel electrode  181   b  may contact the second capacitor electrode  265  via the contact hole  281 .  
         [0075]    It will be apparent to those skilled in the art that various modifications and variation can be made in the method of manufacturing a thin film transistor of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.