Abstract:
Techniques for shaping the drive signal of a mixing device to overcome a characteristic capacitance of the control terminal of the mixing device and reduce the time the mixing device is in an intermediate state between its on and off states.

Description:
BACKGROUND 
     Mixers may be employed in a wide variety of electronic systems. For example, mixers may be used for frequency conversion in a variety of systems including radio systems. Examples of mixing devices that may be employed in a mixer include varieties of field effect transistors (FETs) and bipolar junction transistors (BJTs). 
     A mixing operation in a mixer may include periodically switching a mixing device between its two conductions states. For example, an FET or BJT mixing device may be periodically switched between its on state and its off state during a mixing operation. 
     A mixing device may be switched between its on and off states by applying a periodic drive signal to a control terminal of the mixing device. For example, a sine wave or square wave drive signal may be applied across the gate and the source of an FET mixing device to periodically switch the FET between its on and off states. Similarly, a sine wave or square wave drive signal may be applied to across the base and the emitter of a BJT mixing device to periodically switch the BJT between its on and off states. 
     A control terminal of a mixing device may exhibit electrical characteristics that hinder the switching of the mixing device between its on and off states. For example, the gate of an FET or the base of a BJT may have a characteristic capacitance. The characteristic capacitance of a mixing device may rise as the voltage on the control terminal of the mixing device rises toward a threshold voltage level that switches the mixing device to its on state. The rising characteristic capacitance may limit the speed at which a mixing device may be switched between its on and off states, thereby increasing the time that the mixing device is in an intermediate state between its on and off states. Unfortunately, an increase in the amount of time spent in an intermediate state between its on and off states may cause a mixing device to exhibit an increase in signal loss and signal distortion. 
     SUMMARY OF THE INVENTION 
     Techniques are disclosed for shaping the drive signal of a mixing device to overcome a characteristic capacitance of the control terminal of the mixing device and reduce the time the mixing device is in an intermediate state between its on and off states. The present techniques may be used to reduce the square wave corner rounding caused by device control terminal capacitance while simultaneously providing a temperature compensated optimal DC bias for the mixing device control terminal. 
     Other features and advantages of the present invention will be apparent from the detailed description that follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is described with respect to particular exemplary embodiments thereof and reference is accordingly made to the drawings in which: 
         FIG. 1  shows a mixer according to the present teachings; 
         FIG. 2  illustrates the voltage at the control terminal of a mixing device according to the present teachings; 
         FIG. 3  shows embodiments of a bias circuit and a switching circuit according to the present teachings. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a mixer  10  according to the present teachings. The mixer  10  includes a transistor Q 1  that functions as a mixing device. The control terminal of the transistor Q 1  is driven by a square-wave generator  30 . In one embodiment, the transistor Q 1  is an FET and its control terminal is its gate. Alternatively, the transistor Q 1  may be a BJT and its control terminal its base. 
     The mixer  10  includes a bias circuit  20  and a switching circuit  22  that provide drive shaping according to the present techniques. The bias circuit  20  generates a voltage at a node  50  that sets the maximum voltage level that may be obtained at the gate of the transistor Q 1  (node  54 ). The bias circuit  20  is arranged so that the voltage level at the node  50  temperature tracks with the changes in the voltage (Vf) at which the gate of the transistor Q 1  begins to draw forward electrical current. The switching circuit  22  senses the output signal of the square-wave generator  30  at a node  52  and switches on to provide electrical current into the gate of the transistor Q 1  to overcome the characteristic capacitance of the gate of the transistor Q 1  as the voltage at the gate of the transistor Q 1  reaches its maximum value as set by the bias circuit  20 . 
       FIG. 2  illustrates the voltage (Vg 1 ) at the gate of the transistor Q 1 . The overall voltage Vg 1  over time forms a square-wave that is clamped to the voltage level (V 50 ) at the node  50 . As the voltage Vg 1  rises the characteristic capacitance of the gate of the transistor Q 1  rises. The dotted line shows the rounding of the square-wave voltage at the gate of the transistor Q 1  that would otherwise occur in the absence of circuitry according to the present techniques. Instead, at time t 1  the switching circuit  22  switches on and provides electrical current into the gate of the transistor Q 1 , thereby causing a faster rise in Vg 1  as illustrated by the solid line. 
       FIG. 3  shows embodiments of the bias circuit  20  and the switching circuit  22  according to the present teachings. The bias circuit  20  includes a voltage source  32 , a resistor R 3 , a transistor Q 3 , and a capacitor C 3 . The switching circuit  22  includes a resistor R 2 , a transistor Q 2 , and a capacitor C 2 . 
     The voltage source  32  and the resistor R 3  together provide a source that injects electrical current into the gate of the transistor Q 3 . The transistor Q 3  may be a junction FET, e.g. a pHEMT. The gate of the transistor Q 3  forms a diode with its channel. This yields a voltage at the gate of the transistor Q 3  that is at or near its gate Vf. This is used to set the maximum voltage that may be obtained at the gate of the transistor Q 1 . This prevents excessive current consumption by the transistor Q 1 . The resistor R 3  is selected to have a relatively large resistance value (e.g. 5K Ohm) so that the transistors Q 1  and Q 3  consume relatively small amounts of electrical current. The selection of a relatively large value for R 3  provides a voltage at the gate of the transistor Q 3  (Vg 3 ) representing the threshold voltage for gate conduction of both of the transistors Q 3  and Q 1 . 
     The transistor Q 3  may be formed using the same process technology that is used to form the transistor Q 1 . The transistor Q 3  may be substantially smaller than the transistor Q 1 . 
     The transistor Q 2  in the switching circuit  22  switches the voltage on the gate of the transistor Q 3  to the gate of the transistor Q 1  at the time the square-wave voltage reaches its maximum. The transistor Q 2  like the transistor Q 1  is driven by the output of the square-waved generator  30  but through the capacitor C 2  which is substantially smaller (e.g. 0.1 pF) than the capacitor C 1  (e.g. 5 pF) at the gate of the transistor Q 1 . A rise in the voltage at the node  52  causes a large dv/dt current in the capacitor C 2  as a consequence of the rapid change in voltage at the node  52  from the square-wave generator  30 . This creates a current pulse into the gate of the transistor Q 2 , switching it on, and causing the gate of the transistor Q 1  to have the same voltage as the gate of the transistor Q 3 . The boost in charge, particularly charge that is stored in the capacitor C 3  which is a relatively large capacitor (e.g. 10 pF), provides charge to the gate of the transistor Q 1  and overcomes its increasing capacitance at the peak of the square-wave drive signal. 
     When the square-wave drive signal from the square-wave generator  30  falls, the transistor Q 2  quickly switches off so that it provides no substantial resistance to the fall of Vg 1 . 
     Given that the transistor Q 3  is a smaller version of the transistor Q 1  and that they are formed with the same process technology, the gate Vf of the transistor Q 3  temperature tracks with the gate Vf of the transistor Q 1 . Vg 3  is temperature compensated because the gate conduction threshold voltage for the transistors Q 3  and Q 1  track each other over temperature. Vg 3  is a desirable square wave drive maximum voltage because it is the maximum gate voltage for the transistor Q 1  that will not result in substantial gate current. The capacitor C 3  increases the instantaneous current delivery capability of the bias circuit  20  and is selected to be large enough to meet the required current of the gate of the transistor Q 1 . 
     The size of the transistor Q 2  may be chosen large enough to convey the required current from the capacitor C 3  to the gate of Q 1 —but no larger. The capacitor C 2  and the resistor R 2  are chosen to permit proper operation of transistor Q 2  according to the period of the drive waveform from the square-wave generator  30 . 
     The current source function of the resistor R 3  may be replaced with any number of more sophisticated active current sources. 
     The transistors Q 1 -Q 3  may be FETs or BJTs. Examples include a junction FET (JFET), a metal-semiconductor FET (MESFET), a high electron mobility transistor (HEMT), a pseudo-morphic high electron mobility transistor (pHEMT), a metal-oxide-semiconductor FET (MOSFET), and a homo-junction/hetero-junction transistor (HBT). 
     The mixer  10  benefits from a relatively high conversion efficiency and linearity in frequency mixing operations in comparison with prior mixers. In addition, the mixer  10  provides a high performance mixing operations with less local oscillator input power, or less DC power, or both, in comparison to prior mixers. 
     The foregoing detailed description of the present invention is provided for the purposes of illustration and is not intended to be exhaustive or to limit the invention to the precise embodiment disclosed. Accordingly, the scope of the present invention is defined by the appended claims.