Abstract:
Techniques pertaining the designs of memory controller are disclosed. According to one aspect of the present invention, a memory controller reduces delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller thereof. In one embodiment, the memory controller employs four IO ports, two inverters, six edge triggers and a multiplexer. By feeding back an inverted clock signal and utilizing the rising and filing edges of the clock signal, the delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller are considerably reduced or minimized.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the area of memory controller, more particularly, related to a double data rate (DDR) synchronous dynamic random access memory (SDRAM) controller. 
     2. Description of Related Art 
     DDR SDRAM (called as DDR memory herein) as a high-capacity, high-density and high-speed memory has been widely used in various chips. Main difference between the DDR memory and a previous generation SDRAM (called as SDRAM herein) is that the DDR memory can transfer data at the rising and falling edge of the clock, but the SDRAM only can transfer data at the rising edge of the clock. Furthermore, a clock frequency of the DDR memory is from 133 MHz to 200 MHz, but a clock frequency of the SDRAM is lower than 133 MHz. 
     High-speed clock and faster data transfer rate make a DDR memory controller more difficult in design. A delay difference of a data strobe signal DQS of the DDR memory relative to a clock signal DCLK of the DDR memory controller may be more than 5 ns when the DDR memory works at a maximum working temperature (125 degree Celsius) and a minimum working temperature (−40 degree Celsius) respectively. 
       FIG. 1  is a circuit diagram schematically showing a conventional DDR memory controller connected with a DDR memory. 
     The DDR memory controller includes a number of IO ports. Each IO port has a tri-state terminal PAD interacting with the DDR memory. When the IO port is used as an output port, an input signal of a terminal I of the IO port is outputted via the tri-state terminal PAD. When the IO port is used as an input port, an output signal of a terminal C of the IO port is inputted from the tri-state terminal PAD. The DDR memory controller includes a pair of edge triggers (e.g. D flip-flops) DFF 1  and DFF 2  and an inverter INV. Each edge trigger has a clock terminal CK, an input terminal D and an output terminal Q. 
     A clock signal DCLK of the DDR memory controller is provided to the inverter INV that inverts the clock signal DCLK and outputs an inverted clock signal INV_DCLK to the terminal I of the IO port IO 1 . The IO port IO 1  outputs the inverted clock signal INV_DCLK to a clock terminal CK of the DDR memory via the tri-state terminal PAD thereof. 
     A data strobe terminal DQS of the DDR memory is coupled to the tri-state terminal PAD of the IO port IO 3 . The terminal C of the IO port IO 3  is coupled to the clock terminal CK of the edge trigger DFF 1 . A data terminal DQn of the DDR memory is couple to the tri-state terminal PAD of the IO port IO 2 . The terminal C of the IO port IO 2  is coupled to the input terminal D of the edge trigger DFF 1 . The edge trigger DFF 1  is provided to sample the read data DQn on the falling edge and/or the rising edge of the data strobe DQS′ inputted from the data strobe terminal DQS and output the sampled read data DQ_S 1  via the output terminal Q thereof. 
     The clock terminal CK of the edge trigger DFF 2  is coupled to the clock signal DCLK of the DDR memory controller, and the input terminal D of the edge trigger DFF 2  is couple to the output terminal Q of the edge trigger DFF 1 . The edge trigger DFF 2  is provided to sample the read data DQ_S 1  on the falling edge and/or the rising edge of the clock signal DCLK and output the sampled read data DQ_S 2  via the output terminal Q thereof. 
     It can be seen that the read data DQ_S 1  is obtained by using the data strobe DQS′ as the sampling clock, and the data DQ_S 2  is obtained by sampling the read data DQ_S 1  according to the clock signal DCLK. The delay of the clock signal DQS′ relative to the clock signal DCLK is caused by: 
     an output delay Tpat_out of the IO port, which is often 4.5 ns at the maximum working temperature and 2.5 ns at the minimum working temperature; 
     an accessing time Tac of the DDR memory, which is often 5 ns at the maximum working temperature and 2 ns at the minimum working temperature; 
     an input delay Tpat_in of the IO port, which is often 2.5 ns at the maximum working temperature and 1.5 ns at the minimum working temperature; and 
     an inverting delay T INV  of the inverter INV, which is half of cycle of the clock signal. 
     The above delays are taken as examples for explanation and not all delays are taken into consideration. In practice, other factors may also affect the delay of the data strobe DQS′ relative to the clock signal DCLK. Hence, a certain design margin should be considered. 
     It is assumed that the clock frequency of the clock signal DCLK is 166 MHz, the delay of the data strobe DQS′ relative to the clock signal DCLK is about 15 ns at the maximum working temperature, and the delay of the clock signal DQS′ relative to the clock signal DCLK is about 9 ns at the maximum working temperature. The delay difference of the data strobe DQS′ relative to the clock signal DCLK of the DDR memory controller may be more than 6 ns at the maximum working temperature and the minimum working temperature. As a result, the DDR memory controller obtains the valid read data DQ_S 2  in the difference clock cycles at the maximum working temperature and the minimum working temperature. It has to employ extra software to control the data read operation of the DDR memory controller according to a current working temperature. Thus, a burden of center processing unit is increased, an extra temperature detector is needed, and a reliability of read data is reduced. 
     Thus, improved techniques for memory controller are desired to overcome the above disadvantages. 
     SUMMARY OF THE INVENTION 
     This section is for the purpose of summarizing some aspects of the present invention and to briefly introduce some preferred embodiments. Simplifications or omissions in this section as well as in the abstract or the title of this description may be made to avoid obscuring the purpose of this section, the abstract and the title. Such simplifications or omissions are not intended to limit the scope of the present invention. 
     In general, the present invention is related to designs of memory controller. According to one aspect of the present invention, a memory controller reduces delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller thereof. In one embodiment, the memory controller employs four IO ports, two inverters, six edge triggers and a multiplexer. By feeding back an inverted clock signal and utilizing the rising and filing edges of the clock signal, the delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller are considerably reduced or minimized. 
     Many objects, features, and advantages of the present invention will become apparent upon examining the following detailed description of an embodiment thereof, taken in conjunction with the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
         FIG. 1  is a circuit diagram schematically showing a conventional DDR memory controller connected with a DDR memory; 
         FIG. 2  is a circuit diagram schematically showing a DDR memory controller connected with a DDR memory according to one embodiment of the present invention; 
         FIG. 3A  is a timing diagram schematically showing sampling operations of edge triggers DFF 31  and DFF 32  shown in  FIG. 2 ; and 
         FIG. 3B  is a timing diagram schematically showing a sampling operation of an edge trigger DFF 4  shown in  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The detailed description of the present invention is presented largely in terms of procedures, steps, logic blocks, processing, or other symbolic representations that directly or indirectly resemble the operations of devices or systems contemplated in the present invention. These descriptions and representations are typically used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. 
     Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams or the use of sequence numbers representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations in the invention. 
     Embodiments of the present invention are discussed herein with reference to  FIGS. 1-3 . However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes only as the invention extends beyond these limited embodiments. 
       FIG. 2  is a circuit diagram schematically showing a DDR memory controller  200  coupled to a DDR memory  202  according to one embodiment of the present invention. The DDR memory controller  200  comprises four IO ports IO 1 , IO 2  IO 3  and IO 4 , two inverters INV 1  and INV 2 , six edge triggers DFF 1 , DFF 2 , DFF 31 , DFF 32 , DFF 4  and DFF 5  and a multiplexer MUX. Each edge trigger has an input terminal D, an output terminal Q and a clock terminal CK. The multiplexer MUX has a pair of input terminals A and B, an output terminal Y and a control terminal S 0 . 
     A clock signal DCLK of the DDR memory controller  200  is provided to the inverter INV 1 . The inverter INV 1  inverts the clock signal DCLK and outputs an inverted clock signal INV_DCLK to a clock terminal CK of the DDR memory  202  via the IO port IO 1 . 
     A data strobe DQS of the DDR memory  202  is provided to the clock terminal CK of the edge trigger DFF 1  via the IO port IO 3 . A read data DQn of the DDR memory  202  is provided to the input terminal D of the edge trigger DFF 1 . The output terminal Q of the edge trigger DFF 1  is coupled to the input terminals D of the edge triggers DFF 31  and DFF 4 . The edge trigger DFF 1  is provided to sample the read data DQn on the falling edge and/or the rising edge of the data strobe DQS′ and output the sampled read data DQ_S 1  to the edge triggers DFF 31  and DFF 4 . 
     The clock signal provided to the DDR memory  202  is fed back to the DDR memory controller  200  via the IO port  104 . The clock signal FB_CLK fed back to the DDR memory controller  200  is coupled to the clock terminals CK of the edge triggers DFF 32  and DFF 31 , and the input terminal D of the edge triggers DDF 5 . The inverter INV 2  inverts the clock signal FB_CLK and outputs an inverted clock signal FB_INV_CLK to the clock terminal CK of the edge trigger DFF 4 . 
     The edge trigger DFF 31  is provided to sample the read data DQ_S 1  on the falling edge and/or the rising edge of the clock signal FB_CLK and output the sampled read data to the edge trigger DFF 32 . The edge trigger DFF 32  is provided to sample the data outputted from the edge trigger DFF 31  on the falling edge and/or the rising edge of the clock signal FB_CLK and output the sampled read data FB_S 1  to the input terminal A of the multiplexer MUX. The edge trigger DFF 4  is provided to sample the read data DQ_S 1  on the falling edge and/or the rising edge of the clock signal FB_INV_CLK and output the sampled read data FB_S 2  to the input terminal B of the multiplexer MUX. 
     The clock signal DCLK is coupled to the clock terminal CK of the edge trigger DFF 5 . The output terminal Q of the edge trigger DFF 5  is coupled to the control terminal S 0  of the multiplexer MUX. The edge trigger DFF 5  is provided to sample the clock signal FB_CLK on the falling edge and/or the rising edge of the clock signal DCLK and output a control signal MUX_SEL to the control terminal S 0  of the multiplexer MUX. 
     The output terminal Y of the multiplexer MUX is coupled to the input terminal D of the edge trigger DFF 2 . The multiplexer MUX is provided to output one of the read data FB_S 1  and the read data FB_S 2  to the edge trigger DFF 2  according to the control signal MUX_SEL from the edge trigger DFF 5 . For example, when S 0 =1, the multiplexer MUX outputs the read data FB_S 2  from the input terminal B; when S 0 =0, the multiplexer MUX outputs the read data FB_S 1  from the input terminal A. 
     The clock signal DCLK is coupled to the clock terminal CK of the edge trigger DFF 2 . The edge trigger DFF 2  is provided to sample the read data from the multiplexer MUX and output the sampled read data DQ_S 2 . 
     Referring to  FIG. 5 , a delay T m1  of the clock signal FB_CLK relative to the clock signal INV_CLK is: T m1 =Tpat_out+Tpad_in, and a delay T m2  of the sampling clock DQS′ of the read data DQ_S 1  relative to the clock signal INV_CLK is: T m2 =Tpat_out+Tac+Tpad_in. Tpat_out is an output delay of the IO port, which is 4.5 ns at the maximum working temperature and is 2.5 ns at the minimum working temperature. Tac is an accessing time of the DDR memory, which is 5 ns at the maximum working temperature and is 2 ns at the minimum working temperature. Tpat_in is an input delay of the IO port, which is 2.5 ns at the maximum working temperature and is 1.5 ns at the minimum working temperature. 
     It is assumed that the clock frequency of the clock signal DCLK is 166 MHz, a delay of the clock signal FB_CLK relative to the clock signal DCLK is 7 ns at the minimum working temperature and is 10 ns at the maximum working temperature. The edge trigger DFF 5  samples the clock signal FB_CLK according to the clock signal DCLK. When the delay of the clock signal FB_CLK relative to the clock signal DCLK is less than 9 ns, the edge trigger DFF 5  outputs a low level as the control signal MUX_SEL, and the multiplexer outputs the read data FB_S 1 . When the delay of the clock signal FB_CLK relative to the clock signal DCLK is larger than 9 ns, the edge trigger DFF 5  outputs a high level as the control signal MUX_SEL, and the multiplexer outputs the read data FB_S 2 . In other words, the multiplexer MUX outputs the read data FB_S 2  in the higher working temperature and outputs the read data FB_S 1  in the lower working temperature. 
     Referring to  FIG. 3A , a delay of the read data DQ_S 1  relative to the clock signal FB_CLK is 2 ns (less than a clock cycle T) at the minimum working temperature, the edge trigger DFF 31  samples the read data DQ_S 1  at the sampling point f 0  according to the clock signal FB_CLK, and the edge trigger DFF 32  samples the outputted data of the edge trigger DFF 31  at the sampling point f 0 ′ according to the clock signal FB_CLK. Referring to  FIG. 3B , a delay of the read data DQ_S 1  relative to the clock signal FB_INV_CLK is larger than 3 ns (larger than 0.5T and less than 1.5T) at the maximum working temperature, the edge trigger DFF 4  samples the read data DQ_S 1  at the sampling point f 1  according to the clock signal FB_INV_CLK. 
     The clock signal FB_INV_CLK at the maximum working temperature delays one more clock cycle T (the inverting delay T INV  0.5T, more delay of Tpat_out+Tpad_in 0.5T) than the clock signal FB_CLK at the minimum working temperature. The data FB_S 1  is delayed by one clock cycle T because the data sampled by the clock signal FB_CLK is sampled again by the edge trigger DFF 32 . Thereby, the read data FB_S 1  at the minimum working temperature and the read data FB_S 2  at the maximum working temperature may be outputted to the edge trigger DFF 2  almost simultaneously. 
     At the minimum working temperature, the delay of the read data DQ_S 2  relative to the clock signal DCLK is: T m1 +0.5T+2T=4 ns+3 ns+12 ns=19 ns. At the maximum working temperature, the delay of the read data DQ_S 2  relative to the clock signal DCLK is: T m1 +0.5T+1.5T=7 ns+3 ns+9 ns=19 ns. Thus, the edge trigger DFF 2  samples the read data in a common sampling cycle (18 ns to 24 ns) in all temperature range. 
     To ensure that the edge trigger DFF 2  samples the read data in the common sampling cycle in all temperature range, the following equations should be satisfied:
 
 m*T&lt;DL   l1 &lt;( m+ 1)* T;  
 
 m*T+DL   r   &lt;DL   h1   &lt;DL   r +( m+ 1)* T;  
 
 DL   l   =DL   l2 +( m+ 2)* T;  
 
 DL   h   =DL   h2 +( m+ 1)* T+DL   r ,
 
where m is a natural number, T is a clock cycle, DL l1  is a delay of the read data DQ_S 1  relative to the sampling clock of the edge trigger DFF 31  at the minimum temperature, DL h1  is a delay of the read data DQ_S 1  relative to the sampling clock of the edge trigger DFF 31  at the maximum temperature, DL r  is a delay of the sampling clock of the edge trigger DFF 4  relative to the sampling clock of the edge trigger DFF 31 , DL l  is a delay of the input data of the edge trigger DFF 5  relative to the sampling clock of the edge trigger DFF 5  at the minimum temperature, DL h  is a delay of the input data of the edge trigger DFF 5  relative to the sampling clock of the edge trigger DFF 5  at the maximum temperature, DL l2  is a delay of the sampling clock of the edge trigger DFF 4  relative to the clock signal DCLK at the minimum temperature, DL h2  is a delay of the sampling clock of the edge trigger DFF 4  relative to the clock signal DCLK at the maximum temperature.
 
     The present invention has been described in sufficient details with a certain degree of particularity. It is understood to those skilled in the art that the present disclosure of embodiments has been made by way of examples only and that numerous changes in the arrangement and combination of parts may be resorted without departing from the spirit and scope of the invention as claimed. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description of embodiments.