Abstract:
The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
       [0001]    This application is a National Phase Patent Application and claims priority to and benefit of International Application Number PCT/CN2011/082457, filed on Nov. 18, 2011, which claims priority to and benefit of Chinese Patent Application Number 201110190786.4, filed on Jul. 8, 2011, the entire disclosure of which are incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-scale integration (ULSI) circuit fabrication technology. 
       BACKGROUND OF THE INVENTION 
       [0003]    A semiconductor fabrication technology, as the most rapidly developing technology in the 20th century, is gradually applied into the whole industry production. The semiconductor technology plays a huge role in a modern life. At the same time of pursuing excellent performance of a semiconductor electronic product such as a mobile phone and a computer, it is also desired that the product has a smaller volume, occupies a smaller space, and is more portable and more easily-operated. Therefore, under the 
         [0004]    Moore&#39;s Law, the whole semiconductor industry is being aimed towards a high integration degree, a low power consumption and a high performance. As a feature size is gradually reduced, how to deal with an increasingly serious short channel effect and a series of accompanied deteriorations of device performance will become a key focus of the whole semiconductor industry in the future. 
         [0005]    From a conventional planar field effect transistor to an ultra-thin bulk field effect transistor and then to a transistor of a multi-gate and surrounding-gate structure, in order to seek for a better gate control ability and to suppress the short channel effect and a drain-induced barrier lowering effect, there are emerging a lager number of semiconductor devices with new structures. Among them, a one-dimensional nanowire surrounding-gate structure field effect transistor gradually draws more and more attention due to an excellent gate control ability and an advantage in terms of mobility. If the one-dimensional nanowire surrounding-gate structure field effect transistor may be vertically arranged into an array by using a conventional semiconductor fabrication technology, the integration degree of a chip may be further increased, and a production cost may be greatly reduced. However, the conventional vertical silicon nanowire field effect transistor has a limitation. On one hand, since a size of a drain closes to a size of a channel, a large parasitic resistance may be caused and the speed and performance of the transistor may be adversely affected. Therefore, reducing the adverse influence of parasitic resistance by improving a process is a concern of the vertical silicon nanowire transistor. On the other hand, a difficulty in achieving the vertical silicon nanowire field effect transistor lies in a self-alignment of the source/drain and a gate. Due to a vertical structure, in the fabrication of the vertical silicon nanowire field effect transistor, the self-alignment can not be achieved by firstly defining a gate structure and then performing implantation for the source/drain as for a planar field effect transistor. 
       SUMMARY OF THE INVENTION 
       [0006]    An object of an embodiment of the present invention is to provide a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, and the object is achieved by the following technical solutions. 
         [0007]    Solution 1: A fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, includes the following steps. 
         [0008]    a) Defining an active region and forming a LOCOS isolation 
         [0009]    A main object of the step a) is to define a pattern of the active region by using a silicon oxide, silicon nitride film as a hard mask, so as to achieve an isolation between devices and prevent an interference therebetween. This step particularly includes the following steps: 
         [0010]    i. depositing a silicon oxide, a silicon nitride over a silicon substrate as a hard mask, by using a low pressure chemical vapor deposition process; 
         [0011]    ii. defining the pattern of the active region by performing a photolithography process; 
         [0012]    iii. etching the silicon nitride by an anisotropic dry etching method and removing the silicon oxide by an etching process through an BHF solution, so as to transfer the pattern onto the hard mask; 
         [0013]    iv. removing a photoresist; 
         [0014]    v. forming a silicon oxide by an oxyhydrogen oxidation to form the LOCOS isolation; 
         [0015]    vi. removing the silicon nitride by performing an etching process using a hot concentrated phosphoric acid solution; 
         [0016]    vii. removing the silicon oxide by performing an etching using a BHF solution. 
         [0017]    b) Fabricating the vertical silicon nanowire having a large drain so as to reduce a parasitic resistance of the drain 
         [0018]    A main object of the step b) is to form a vertical silicon pillar having a large diameter and a top support structure by performing a photolithography process and a dry etching process twice and includes the following steps: 
         [0019]    i. depositing a first silicon oxide layer and a first silicon nitride layer as a hard mask, by performing a low pressure chemical vapor deposition process; 
         [0020]    ii. defining a lateral bar as a support structure for a drain to be formed subsequently, by performing a photolithography process; 
         [0021]    iii. etching the first silicon nitride layer, the first silicon oxide layer and the silicon substrate by using an anisotropic dry etching process; 
         [0022]    iv. depositing a second silicon nitride layer as a sidewall structure by using a low pressure chemical vapor deposition process; 
         [0023]    v. etching the second silicon nitride by using an anisotropic dry etching process; 
         [0024]    vi. etching the silicon to form a silicon bar by using an anisotropic dry etching process; 
         [0025]    vii. performing a photolithography process to protect a middle region of the silicon bar, which is to be formed as a device region of the vertical silicon nanowire to be formed subsequently; 
         [0026]    viii. etching the silicon by using an isotropic dry etching process to suspend the silicon bar which are not protected by a photoresist; 
         [0027]    ix. removing the photoresist. 
         [0028]    c) Further reducing a size of the nanowire to form a vertical silicon nanowire having a diameter of about 10 nm, while remaining a large area of pattern used for the drain on top of the vertical silicon nanowire, so as to reduce the parasitic resistance of the drain 
         [0029]    A main object of the step c) is to further reduce the size of the vertical silicon pillar to form the vertical silicon nanowire by using an isotropic wet etching process and a sacrifice oxidation process. Also, a cross-section of the vertical silicon pillar is changed to approximately be a circle, so that a better characteristic can be obtained. The step c) further includes the following steps: 
         [0030]    i. performing an isotropic wet etching process on the silicon pillar to further reduce the size of the vertical silicon pillar; 
         [0031]    ii. performing a dry oxygen oxidation to form a vertical silicon nanowire having a diameter of about 10 nm, and forming a second silicon oxide layer; 
         [0032]    iii. removing a silicon oxynitride formed during the dry oxygen oxidation by performing a wet etching process; 
         [0033]    iv. removing the first silicon nitride layer and the second silicon nitride layer formed by the low pressure chemical vapor deposition process by performing a wet etching; 
         [0034]    v. removing the second silicon oxide layer formed by the dry oxygen oxidation and the first silicon oxide layer formed by the low pressure chemical vapor deposition, by performing a wet etching process. 
         [0035]    d) Defining and doping a source/drain region and a channel region of the vertical silicon nanowire 
         [0036]    A main object of the step d) is to form a flat silicon oxide isolation layer and a polysilicon gate layer by using a chemical mechanical polishing process, so that to define the source/drain region and channel region of the vertical silicon nanowire field effect transistor, wherein a thickness of a film, which is the remained polysilicon gate after being subject to an isotropic dry etching process, is a desired channel length. Also, a doping process is performed. The step d) further includes the following steps: 
         [0037]    i. performing an ion implantation for the source/drain, with an implantation angle perpendicular to a surface of the silicon substrate, and performing an annealing process; 
         [0038]    ii. depositing a third silicon oxide layer by using a low pressure chemical vapor deposition process, and performing a planarization of the silicon oxide by using a chemical mechanical polishing (CMP) process; 
         [0039]    iii. performing a photolithography process to protect a field oxygen region; 
         [0040]    iv. etching the third silicon oxide layer to a certain thickness by performing a wet etching, as an isolation layer of the gate material and the source; 
         [0041]    v. removing a photoresist; 
         [0042]    vi. forming a gate oxide layer by a dry oxygen oxidation; 
         [0043]    vii. deposting a polysilicon by a low pressure chemical vapor deposition, and performing a planarization of the polysilicon by using a chemical mechanical polishing (CMP) process; 
         [0044]    viii. performing an ion implantation process on the polysilicon and performing an annealing process ; 
         [0045]    ix. performing a photolithography to define a gate region, then etching the polysilicon by using an anisotropic dry etching process, and removing a photoresist; 
         [0046]    x. etching the polysilicon to a certain thickness by using an isotropic wet etching to form the gate and a gate lead-out; 
         [0047]    xi. depositing a fourth silicon oxide layer by using a low pressure chemical vapor deposition, and performing a planarization of the silicon oxide by using a chemical mechanical polishing (CMP) process; 
         [0048]    xii. performing a photolithography process to protect the field oxygen region; 
         [0049]    xiii. etching the fourth silicon oxide layer by using a wet etching process until the silicon is exposed to form an isolation layer of the gate material and the drain; 
         [0050]    xiv. removing a photoresist. 
         [0051]    e) Forming a contact hole and a metal interconnection 
         [0052]    A main object of the step e) is to lead out the source/drain and the gate, so as to facilitate a test and a setup of a large-scale integrated circuit. The step e) further includes the following steps: 
         [0053]    i. performing a photolithography process to form the contact hole for the source and the gate; 
         [0054]    ii. etching the silicon oxide by using an anisotropic dry etching process; 
         [0055]    iii. etching the silicon oxide by using a BHF solution; 
         [0056]    iv. removing a photoresisit; 
         [0057]    v. sputtering a metal; 
         [0058]    vi. performing a photolithography process to form a lead out for a metal interconnection; 
         [0059]    vii. etching the metal by using an anisotropic dry etching process; 
         [0060]    viii. removing a photoresist; 
         [0061]    ix. performing an alloying process. 
         [0062]    The embodiment of the present invention may also implement the ion implantation for the source/drain by the following: after forming the LOCOS isolation of the silicon substrate, firstly performing an ion implantation process to the substrate to implement the doping the source/drain and the channel, so that an accumulative vertical silicon nanowire field effect transistor (Junctionless MOSFET) can be obtained. 
         [0063]    Solution 2. A fabrication method of an accumulative vertical silicon nanowire field effect transistor includes the following steps. 
         [0064]    a) Defining an active region over a silicon substrate and forming a LOCOS isolation 
         [0065]    b) Fabricating a vertical silicon nanowire by performing a photolithography process and a dry etching process twice to form a vertical silicon pillar having a large diameter and a top support structure 
         [0066]    The step b) particularly includes the following steps: 
         [0067]    i. performing an ion implantation process on the substrate to implement doping of a source/drain and a channel; 
         [0068]    ii. depositing a first silicon oxide layer and a first silicon nitride layer as a hard mask, by using a low pressure chemical vapor deposition process; 
         [0069]    iii. performing a photolithography process to define a lateral bar as a support structure for a drain to be formed later; 
         [0070]    iv. etching the first silicon nitride layer, the first silicon oxide layer, and the silicon substrate by using an anisotropic dry etching process; 
         [0071]    v. depositing a second silicon nitride layer as a sidewall structure by using a low pressure chemical vapor deposition process; 
         [0072]    vi. etching the second silicon nitride layer by using an anisotropic dry etching process; 
         [0073]    vii. etching the silicon substrate by using an anisotropic dry etching process to form a silicon bar; 
         [0074]    viii. performing a photolithography process to protect a middle region of the silicon bar, which is to be formed as a device region of the vertical silicon nanowire to be formed later; 
         [0075]    ix. etching the silicon substrate by using an isotropic dry etching process to suspend the silicon bar unprotected by a photoresist; 
         [0076]    x. removing the photoresist. 
         [0077]    c) Further reducing the size of the nanowire to form a vertical silicon nanowire having a diameter of about 10 nm, while remaining a large area of pattern used for the drain on top of the vertical silicon nanowire, so as to reduce the parasitic resistance of the drain 
         [0078]    The step c) particularly includes the following steps: 
         [0079]    i. etching the silicon by using an isotropic wet etching process to further reduce the size of the silicon pillar; 
         [0080]    ii. performing a dry oxygen oxidation to form the vertical silicon nanowire having a diameter of about 10 nm, and forming a second silicon oxide layer; 
         [0081]    iii. removing a silicon oxynitride formed during the dry oxygen oxidation by performing a wet etching process; 
         [0082]    iv. removing the first silicon nitride layer and the second silicon nitride layer formed through the low pressure chemical vapor deposition process by performing a wet etching process; 
         [0083]    v. removing the second silicon oxide layer formed through the dry oxygen oxidation and the first silicon oxide layer formed through the low pressure chemical vapor deposition, by performing a wet etching process. 
         [0084]    d) Defining and doping a source/drain region and a channel region of the vertical silicon nanowire 
         [0085]    The step d) particularly includes the following steps: 
         [0086]    i. depositing a third silicon oxide layer by using a low pressure chemical vapor deposition process, and performing a planarization of the silicon oxide by using a chemical mechanical polishing (CMP) process; 
         [0087]    ii. performing a photolithography process to protect a field oxygen region; 
         [0088]    iii. etching the third silicon oxide layer to a certain thickness by performing a wet etching process, as an isolation layer of the gate material and the source; 
         [0089]    iv. removing a photoresist; 
         [0090]    v. forming a gate oxide layer by a dry oxygen oxidation; 
         [0091]    vi. depositing a polysilicon by a low pressure chemical vapor deposition, and performing a planarization of the polysilicon by using a chemical mechanical polishing (CMP) process; 
         [0092]    vii. performing an ion implantation on the polysilicon and performing an annealing process; 
         [0093]    viii. performing a photolithography process to define a gate region, and then etching the polysilicon using an anisotropic dry etching process, and removing a photoresist; 
         [0094]    ix. etching the polysilicon to a certain thickness by using an isotropic wet etching to form the gate and a gate lead-out; 
         [0095]    x. depositing a fourth silicon oxide layer by using a low pressure chemical vapor deposition, and performing a planarization of the silicon oxide by using a chemical mechanical polishing (CMP) process; 
         [0096]    xi. performing a photolithography to protect the field oxygen region; 
         [0097]    xii. etching the fourth silicon oxide layer by using a wet etching process until the silicon is exposed to form an isolation layer of the gate material and the drain; 
         [0098]    xiii. removing a photoresist. 
         [0099]    e) Forming a contact hole and a metal interconnection 
         [0100]    The embodiment of the present invention has the following technical effects. 
         [0101]    Firstly, as compared with the conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by an embodiment of the present invention can provide a good ability of suppressing a short channel effect due to the excellent gate control ability caused by its one-dimensional structure, and can reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, due to the novel vertical structure, an area of the transistor is further reduced and an integration degree of an IC system is increased. Therefore, the transistor of the present invention can be more suitable for a future circuit desired for low power consumption. It is particularly noted that, it is difficult to form a large source/drain structure in the conventional vertical silicon nanowire field effect transistor, so that parasitic resistance of the source/drain is large, thereby a speed of the transistor may be significantly affected. However, based on the vertical silicon nanowire field effect transistor formed by an embodiment of the present invention, an area of the source/drain is increased, thus the parasitic resistance of the source/drain can be effectively reduced, and performance of the transistor is improved. Finally, another difficulty in terms of the process of the vertical silicon nanowire field effect transistor is that the source/drain and the channel have different doped impurities, and it is difficult to achieve a self-alignment of the source/drain and the gate structure. An embodiment of the present invention provides an accumulative transistor, so that the source/drain and the channel have identical doping impurities, thereby the above problem can be well obviated. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0102]      FIGS. 1-5  are schematic diagrams showing a process flow of fabricating a accumulative vertical silicon nanowire filed effect transistor proposed by an embodiment of the present invention. The process flow is briefly described as followings. 
           [0103]    In  FIG. 1 , an active region is defined, and a LOCOS isolation is formed, wherein, in  FIG. 1A  a silicon oxide and a silicon nitride are deposited over a silicon substrate as a hard mask by using a low pressure chemical vapor deposition process; in  FIG. 1B , a LOCOS isolation is implemented by an oxyhydrogen oxidation process;  FIG. 10  is a diagram showing a structure after the hard mask is removed by a wet etching process. 
           [0104]    In  FIG. 2 , the vertical silicon nanowire is fabricated to have a large drain so as to reduce the parasitic resistance of the source/drain, wherein, in  FIG. 2A , a hard mask bar formed of a silicon oxide and a silicon nitride is formed as a support structure for the drain to be formed later;  FIG. 2B  is a diagram showing a structure after the silicon is etched by using an anisotropic dry etching process; in  FIG. 2C , a silicon nitride sidewall is formed;  FIG. 2D  is a diagram showing a structure after the silicon is etched by using a anisotropic dry etching process; in  FIG. 2E , a photolithography process is performed to protect an middle region of the silicon bar, which is used as a device region of the vertical silicon nanowire to be formed later; in  FIG. 2F , the silicon is etched by using an isotropic dry etching process to suspend the silicon bar unprotected by a photoresist. 
           [0105]    In  FIG. 3 , a size of the nanowire is further reduced to form the vertical silicon nanowire having a diameter of about 10 nm, and a large area of pattern used for the drain on top of the vertical silicon nanowire is remained to reduce the parasitic resistance of the drain, wherein, in  FIG. 3A , the silicon is etched by an HNA solution to further reduce the size of the nanowire;  FIG. 3B  is a diagram showing a structure after the size of a silicon pillar is further reduced by performing an sacrifice oxidation and the silicon oxide, the silicon nitride are removed by a wet etching process. 
           [0106]    In  FIG. 4 , a source/drain region and a channel region of the vertical silicon nanowire are defined and doped, wherein, in  FIG. 4A , an ion implantation is performed on the source/drain with an implantation angle perpendicular to a surface of the silicon substrate, and an annealing process is performed; in  FIG. 4B , a silicon oxide is deposited by using a low pressure chemical vapor deposition process, and a photolithography process is performed to protect a field oxygen region after implementing a planarization of the silicon oxide with a chemical mechanical polishing (CMP) process; in  FIG. 4C , the silicon oxide is etched to a certain thickness by using a BHF solution, to be used as an isolation layer of the gate material and the source; in  FIG. 4D , a photoresist is removed; in  FIG. 4E , a gate dielectric and a gate lead-out are formed; in  FIG. 4F , a silicon oxide is deposited again by using a low pressure chemical vapor deposition process, and a photolithography process is performed to protect a field oxygen region after performing a planarization of the silicon oxide by using a chemical mechanical polishing (CMP) process; in  FIG. 4C , the silicon oxide is etched to a certain thickness by using a BHF solution, as an isolation layer of the gate material and the drain; in  FIG. 4H , a photoresist is removed. 
           [0107]    In  FIG. 5 , a contact hole and a metal interconnection are formed, wherein, in  FIG. 5A , the contact hole for the gate and the source are formed. In  FIG. 5B , a lead out for the metal interconnection is formed. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0108]    Hereinafter, an embodiment of the present invention will be described in more detail with reference to drawings and a specific embodiment. Herein, it is provided a solution for a process of a vertical silicon nanowire field effect transistor having a low parasitic resistance according to an embodiment of the present invention. However, the description does not limit the scope of the present invention by any way. 
         [0109]    The vertical silicon nanowire field effect transistor having a channel length of about 90 nm and a diameter of about 10 nm is fabricated by the following steps. 
         [0110]    1. A silicon oxide of 300 Å is deposited by using a low pressure chemical vapor deposition process. 
         [0111]    2. A silicon nitride of 1000 Å is deposited by using a low pressure chemical vapor deposition process. 
         [0112]    3. A photolithography process is performed to define an active region. 
         [0113]    4. The silicon nitride of 1000 Å is etched by using an anisotropic dry etching process. 
         [0114]    5. The silicon oxide of 300 Å is etched by using a BHF solution for over-etching for 5 s, as shown in  FIG. 1A . 
         [0115]    6. A photoresist is removed. 
         [0116]    7. A silicon oxide of 5000 Å is grown by using an oxyhydrogen oxidation process, so as to form a LOCOS isolation, as shown in  FIG. 1B . 
         [0117]      8 . The silicon nitride of 1000 Å is etched by using a hot concentrated phosphoric acid. 
         [0118]    9. The silicon oxide of 300 Å is etched by using a BHF solution, as shown in  FIG. 10 . 
         [0119]    10. A silicon oxide of 300 Å is deposited by using a low pressure chemical vapor deposition process. 
         [0120]    11. A silicon nitride of 1000 Å is deposited by using a low pressure chemical vapor deposition process. 
         [0121]    12. A photolithography process is performed to define a lateral bar having a width of 2000 Å, which is used as a support structure for a drain to be formed subsequently. 
         [0122]    13. The silicon nitride of 1000 Å is etched by an anisotropic dry etching process. 
         [0123]    14. The silicon oxide of 300 Å is etched by an anisotropic dry etching process, as shown in  FIG. 2A . 
         [0124]    15. The silicon is etched by 4000 Å through an anisotropic dry etching process. 
         [0125]    16. A photoresist is removed, as shown in  FIG. 2B . 
         [0126]      17 . A silicon nitride of 1000 Å is deposited by a low pressure chemical vapor deposition process. 
         [0127]    18. The second silicon nitride layer of 1000 Å is etched by an anisotropic dry etching process, as shown in  FIG. 2C . 
         [0128]    19. The silicon is etched by 1000 Å through an anisotropic dry etching process, as shown in  FIG. 2D . 
         [0129]    20. Å photolithography is preformed to protect a middle region of the silicon bar of 3000 Å, which is a region of the vertical silicon nanowire field effect transistor to be formed subsequently, as shown in  FIG. 2E . 
         [0130]    21. The silicon is etched by 1000 Å through an isotropic dry etching process to suspend the silicon bar unprotected by a photoresist. 
         [0131]    22. The photoresist is removed, as shown in  FIG. 2F . 
         [0132]    23. The silicon is etched by 1000 Å with an HNA solution to further reduce a size of a vertical silicon pillar, as shown in  FIG. 3A . 
         [0133]    24. A silicon oxide of 800 Å is formed by a dry oxygen oxidation to further reduce the size of the vertical pillar, so that the vertical pillar becomes the vertical silicon nanowire having the diameter of about 10 nm. 
         [0134]    25. The silicon oxynitride is removed by performing an etching process using a HF solution rinsing for 40 s. 
         [0135]    26. The silicon nitride of 1000 Å is removed by performing an etching process using a hot concentrated phosphoric acid solution. 
         [0136]    27. The silicon oxide formed by a sacrifice oxidation process and the previously-deposited silicon oxide of 1000 Å are removed by performing an etching process using a BHF solution to over-rinsing for 5 s, as shown in  FIG. 3B . 
         [0137]    28. An ion implantation, in which an implantation energy is 50 keV, a dose is 4e15 cm −2 , and an implantation angle is perpendicular to a surface of a silicon wafer, is performed to implant As into a source and the drain, and an annealing is performed for 5 s at RTP 1050 degree, as shown in  FIG. 4A . 
         [0138]    29. A silicon oxide of 1 μm is deposited by a low pressure chemical vapor deposition process, and a planarization of the silicon oxide is performed by a chemical mechanical polishing (CMP) process. 
         [0139]    30. A photolithography process is performed to protect a field oxygen region, as shown in  FIG. 4B . 
         [0140]    31. The silicon oxide is etched to a certain thickness by using a BHF solution, and the silicon oxide of 2000 Å is remained as an isolation layer of a gate and the source, as shown in  FIG. 4C . 
         [0141]    32. A photoresist is removed, as shown in  FIG. 4D . 
         [0142]    33. A gate oxide layer of 50 Å is formed by a dry oxygen oxidation. 
         [0143]    34. A polysilicon of 8000 Å is deposited by a low pressure chemical vapor deposition, and a planarization of the polysilicon is performed by a chemical mechanical polishing (CMP) process. 
         [0144]      35 . An ion implantation, in which an implantation energy is 50 keV, a dose is 5 e 15 cm −2 , and an implantation angle is perpendicular to the surface of the silicon wafer, is performed to implant As into the polysilicon, and an annealing is performed for 5 s at RTP 1050 degree. 
         [0145]    36. A photolithography process is performed to define a gate region structure. 
         [0146]    37. The polysilicon is etched by 6000 Å through an anisotropic dry etching process until the silicon oxide is etched. 
         [0147]    38. A photoresist is removed. 
         [0148]    39. The polysilicon is etched to a certain thickness by using an HNA solution, and the polysilicon with a thickness of 900 Å is remained as a gate and a lead-out for the gate, as shown in  FIG. 4E . 
         [0149]    40. A silicon oxide of 7000 Å is deposited by using a low pressure chemical vapor deposition process, and a planarization of the polysilicon is performed by a chemical mechanical polishing (CMP) process. 
         [0150]    41. A photolithography process is performed to protect the field oxygen region, as shown in  FIG. 4F . 
         [0151]    42. The silicon oxide is etched to a certain thickness by using a BHF solution, and the silicon oxide of 2000 Å is remained as an isolation layer of the gate material and the drain, as shown in  FIG. 4G . 
         [0152]    43. A photoresist is removed, as shown in  FIG. 4H . 
         [0153]    44. A photolithography process is performed to form a contact hole for the source and the gate. 
         [0154]    45. The silicon oxide is etched by 5000 Å through an anisotropic dry etching process. 
         [0155]    46. The silicon oxide is etched by 500 Å by using a BHF solution. 
         [0156]    47. A photoresist is removed, as shown in  FIG. 5A . 
         [0157]    48. A metal Ti/AI with a thicknesses of 700 Å/1 μm is sputtered. 
         [0158]    49. A photolithography process is performed to form a lead-out for a metal interconnection. 
         [0159]    50. The metal Al/Ti with the thickness of 1 μm/700 Å is etched by using an anisotropic dry etching process. 
         [0160]    51. A photoresist is removed. 
         [0161]    52. An alloying process at 430 degree is performed for 30 min, as shown in  FIG. 5B . 
         [0162]    The embodiment described above is not used to limit the present invention, those skilled in the art of the field can make various changes and modifications without departing from the spirit and the scope of the present invention, and the scope of the present invention is defined by the scope of the appended claims.