Abstract:
A prescalar using the fractional division theory. The prescalar is a critical circuit in a phase-locked loop based frequency synthesizer to provide a high frequency operation. The prescalar is also an important subassembly. Using four translucent circuits and one divisor selection circuit, a two mode frequency divider synchronously divided by ⅘ is synthesized to synthesize the fraction function. The load capacitance can be effectively reduced. Meanwhile, a reset TSPC flip flop can be designed to effectively and quickly perform the reset operation, and to assemble a two mode frequency divider synchronously divided by {fraction (16/13)}. The invention uses standard 0.25 μm CMOS fabrication process to obtain a maximum operation frequency of 6 GHz under a 2V operation voltage. The chip system integration can thus be enhanced.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates in general to a prescalar. More particularly, the invention relates to prescalar using fraction division theory. 
     2. Description of the Related Art 
     A conventional prescalar comprises a two mode frequency divider synchronously divided by ⅘ and a circuit non-synchronously divided by 16. The minimum amplitude signal output by a bias control oscillator can be converted into a large pushable digital logic signal. At the front end of the circuit, an input amplifier is typically installed. While adapting such high speed logic in dynamic logic, the maximum operation frequency is not restricted by the operation speed of the logic circuit, but the frequency response of the input amplifier. When the frequency response of input amplifier is directly determined by the load capacitor, that is, by the input capacitance load of the logic circuit portion of the prescalar, the synchronous frequency divider is normally constructed of three circuits divided by 2. That, the synchronous frequency divider includes three flip flops. For the input amplifier, the load is the clock load of the three flip flops. 
     SUMMARY OF THE INVENTION 
     The invention provides a prescalar using fraction division theory. An input amplifier only drives one divided-by-2 circuit, that is, the load thereof is a clock load of a single flip flop. Therefore, a higher frequency response of the input amplifier can be obtained compared to the conventional structure. As a result, the maximum operation frequency of the prescalar can be enhanced. 
     The invention uses a divided-by-2 circuit divided and a synchronously divided-by-{fraction (2/2.5)} two mode frequency divider to replace the conventional two mode frequency divided by ⅘, and a non-synchronously divided-by-{fraction (16/13)} two mode frequency divider and an input amplifier. The divided-by-{fraction (2/2.5)} two mode frequency divider synchronously comprises a divisor selection circuit, a plurality translucent circuits and a synthesized divided-by-{fraction (2/2.5)} logic circuit. The non-synchronously divided-by-{fraction (16/13)} two mode frequency divider comprises a reset flip flop, an erase flip flop and a reset control logic NOR gate. 
     The divisor selection circuit of the two mode frequency divider synchronously divided by {fraction (2/2.5)} comprises a first to a sixth transistors. The first transistor comprises a gate coupled to an input terminal IN. A drain of the second transistor is coupled to a source of the first transistor. A drain of the fourth transistor is coupled to the source of the first transistor. The drain of the third transistor is coupled to a source of the second transistor. A drain of the fifth transistor is coupled to a source of the fourth transistor. A source region of the third transistor is coupled to a source of the fifth transistor. A drain of the sixth transistor is coupled to a source of the fifth transistor. A gate of the sixth transistor is coupled to the input terminal. A source of the sixth transistor is coupled to ground. 
     The translucent circuits of the synchronously divided-by-{fraction (2/2.5)} two mode frequency divider comprises the seventh to the thirty-second transistors. A drain of the eighth transistor is coupled to a source of the seventh transistor. A gate of the tenth transistor is coupled to the drain of the eighth transistor. A drain of the ninth transistor is coupled to a source of the eighth transistor. A gate of the ninth transistor is coupled to a gate of the seventh transistor. A source of the ninth transistor is grounded. A gate of the eleventh transistor is coupled to a gate of the eighth transistor. A drain of the eleventh transistor is coupled to a source of the tenth transistor. A drain of the twelfth transistor is coupled to a source of the eleventh transistor. A source of the twelfth transistor is grounded. A gate of the twelfth transistor is coupled to the drain of the eighth transistor. A gate of the thirteenth transistor is coupled to the drain of the twelfth transistor. A drain of the fourteenth transistor is coupled to a source of the thirteenth transistor. A gate of the fourteenth transistor is coupled to the gate of the eleventh transistor. A gate of the fifteenth transistor is coupled to the gate of the thirteenth transistor. A source of the fifteenth transistor is grounded. A gate of the sixteenth transistor is coupled to the drain of the fourteenth transistor. A gate of the seventeenth transistor is coupled to a gate of the fourteenth transistor. A drain of the seventeenth transistor is coupled to a source of the sixteenth transistor. A gate of the eighteenth transistor is coupled to the drain of the fourteenth transistor. A source of the eighteenth transistor is grounded. A drain of the eighteenth transistor is coupled a source of the seventeenth transistor. A gate of the nineteenth transistor is coupled to a drain of the eighteenth transistor. A drain of the twentieth transistor is coupled to a source of the nineteenth transistor. A gate of the twentieth transistor is coupled to the gate of the seventeenth transistor. A gate of the twenty-first transistor is coupled to the gate of the nineteenth transistor. A source of the twenty-first transistor is coupled to ground. A gate of the twenty-second transistor is coupled to the drain of the twentieth transistor. A gate of the twenty-third transistor is coupled to the gate of the twentieth transistor. A drain of the twenty-third transistor is coupled to a source of the twenty-second transistor. A gate of the twenty-fourth transistor is coupled to the drain of the twentieth transistor. A source of the twenty-fourth transistor is connected to ground. A drain of the twenty-fourth transistor is coupled to a source of the twenty-third transistor. A drain of the twenty-fifth transistor is coupled to a drain of the twenty-fourth transistor. A gate of the twenty-fifth transistor is coupled to ground. A gate of the twenty-sixth transistor is coupled to a drain of the twenty-fifth transistor. A drain of the twenty-seventh transistor is coupled to a source of the twenty-sixth transistor. A gate of the twenty-seventh transistor is coupled to the gate of the twenty-third transistor. A gate of the twenty-eighth transistor is coupled to the gate of the twenty-sixth transistor. A source of the twenty-eighth transistor is coupled to ground. A gate of the twenty-ninth transistor is coupled to drain of the twenty-seventh transistor. A gate of the thirtieth transistor is coupled to the gate of the twenty-seventh transistor. A drain of the thirtieth transistor is coupled to a source of the twenty-ninth transistor. A gate of the thirty-first transistor is coupled to the drain of the twenty-seventh transistor. A source of the thirty-first transistor is coupled to ground. A drain of the thirty-first transistor is coupled to a source of the thirtieth transistor. A drain of the thirty-second transistor is coupled to the drain of the thirty-first transistor. A gate of the thirty-second transistor is coupled to the gate of the twenty-fifth transistor. A source of the thirty-second transistor is grounded. 
     The synthesized divided-by-{fraction (2/2.5)} logic circuit of the synchronously-divided-by-{fraction (2/2.5)} two mode frequency divider comprises a first NAND logic gate, a second NAND logic gate, a third NAND logic gate, a multiplexer and a NOT logic gate. The second NAND logic gate comprises a second input terminal coupled to an output terminal of the first NAND logic gate. An output terminal of the third NAND logic gate is coupled to a second input terminal of the second NAND logic gate. An output terminal of the multiplexer is coupled to a first output terminal of the third NAND logic gate. A first terminal of the NOT logic gate is coupled to a second input terminal fo the third NAND logic gate. 
     The non-synchronously divided-by-{fraction (16/13)} two mode frequency divider comprises a first flip flop to a fifth flip flop and a NOR logic gate. The first flip flop comprises a first input terminal to a first output terminal thereof A first input terminal of the second flip flop is coupled to its first output terminal. A second input terminal of the second flip flop is coupled to a second input terminal of the first flip flop. A SET terminal of the second flip flop is coupled to a SET terminal of the first flip flop. A first input terminal of the third flip flop is coupled to a first output terminal of the third flip flop. A second input terminal of the third flip flop is coupled to a second output terminal of the second flip flop. A CLR terminal of the third flip flop is coupled to the SET terminal of the second flip flop. A first input terminal of the fourth flip flop is coupled to a first output terminal of the fourth flip flop. A second input terminal of the fourth flip flop is coupled to the second output terminal of the third flip flop. A SET terminal of the fourth flip flop is coupled to the CLR terminal of the third flip flop. A second output terminal of the fourth flip flop is coupled to the output terminal (OUT). The NOR logic gate comprises a first input terminal coupled to the second output terminal of the first flip flop, a second input terminal coupled to the second output of the second flip flop, a third input terminal coupled to the second output terminal of the third flip flop. The NOR logic gate further comprises a fourth input terminal coupled to the second input terminal of the fourth flip flop. The fifth flip flop has a SET terminal coupled to the output terminal of the NOR logic gate, a second input terminal coupled to the second input terminal of the first flip flop. A PRESET terminal of the fifth flip flop is coupled to the SET terminal of the fourth flip flop. 
     According to the above structure, the prescalar provided by the invention comprises a two mode frequency divider synchronously divided by {fraction (2/2.5)} to replace the two mode frequency divider divided by ⅘ used in the conventional structure. Together with a two mode frequency divider nonchronously divided by {fraction (13/16)}, if the circuit is divided by 64, the divided-by-{fraction (2/2.5)} circuit has to be divided by 2, so that the divided-by-{fraction (16/13)} circuit has to be the divided-by-16 mode. With the aids of the divided-by-2 circuit, the total divisor is 64. If the circuit is to be divided by 65, the circuit divided by {fraction (2/2.5)} is set at divided-by-2.5 mode, and the circuit divided by {fraction (16/13)} is set at divided-by-13 mode. With the assistance of the circuit divided by 12.5, the total divisor is 65. 
     Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a prescalar using fractional division according to the invention; 
     FIG. 2 shows a circuit diagram of a prescalar that uses the fractional division and comprises a synchronously divided-by-2.5 two mode frequency divider and a non-synchronously divided-by-{fraction (13/16)} two mode frequency divider according to the invention; 
     FIG. 3 shows the divided-by-2.5 clock diagram and the waveform composite graph of the divided-by-2.5 clock of the prescalar using fractional division theory; 
     FIG. 4 shows the divided-by-2 clock diagram and the waveform composite graph of the divided-by-2 clock of the prescalar using fractional theory; and 
     FIG. 5 shows the sequence of the divided-by-13 function of the prescalar using the fractional division theory according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The prescalar using fractional division theory provided by the invention comprises an input amplifier  200 , a divided-by-2 circuit  400 , a synchronously divided-by-{fraction (2/2.5)} two mode frequency divider  600 , and a non-synchronously divided-by-{fraction (13/16)} two mode frequency divider  800 . The input amplifier only needs to drive one divided-by-2 circuit  400 , that is, the load is a clock load of a single flip flop. Therefore, the input amplifier can have a higher frequency response to enhance the maximum operation speed of the prescalar. 
     FIG. 1 is a block diagram of the prescalar using fraction division theory. The input amplifier  200  amplifies a signal to an operable digital level of the prescalar. The input amplifier  200  is coupled to the divided-by-2  400  which divides the input digital level signal by 2. A divided-by-2 signal is output. The divided-by-2 circuit  400  is coupled to the synchronously divided-by-{fraction (2/2.5)} two mode frequency divider  600 . The divided-by-2 signal is then divided by {fraction (2/2.5)}, so that a divided-by-{fraction (2/2.5)} signal is output. The synchronously divided-by-{fraction (2/2.5)} two mode frequency divider  600  is coupled to the non-synchronously divided-by-{fraction (16/13)} two mode frequency divider  800 , so that the divided-by-{fraction (2/2.5)} signal is divided by {fraction (16/13)}, and a divided-by-{fraction (16/13)} signal is output. 
     FIG. 2 shows a circuit diagram of the synchronously divided-by-{fraction (2/2.5)} two mode frequency divider  600  and the non-synchronously divided-by-{fraction (13/16)} two mode frequency divider  800 . The synchronously divided-by {fraction (2/2.5)} two mode frequency divider  600  comprises a divisor selection circuit  620 , four translucent circuit  640  and a synthesized divided-by-{fraction (2/2.5)} logic circuit  660 . The divided-by-signal input terminal (IN) is coupled to the divisor selection circuit  620 . When the input divisor selection signal MCI is 0, the whole circuit is divided by 4. When the input divisor selection signal is 1, the whole circuit is divided by 5 and coupled to the four translucent circuits  640  which show the waveform signal in each node. The divisor signal and the four translucent signals are used to synthesize a new synchronously divided-by-⅘ two mode frequency divider, and then coupled to the synchronously divided-by-{fraction (2/2.5)} two mode frequency divider  660  to obtain the divided-by-{fraction (2/2.5)} waveform required by the divided-by-{fraction (2/2.5)} for the waveform signal synthesis at each node of the translucent circuits  640 . The non-synchronously divided-by-{fraction (16/13)} two mode frequency divider  800  is coupled to the synthesized divided-by-{fraction (2/2.5)} logic circuit  660 . The synthesized divided-by-{fraction (2/2.5)} waveform is divided by 16 or 13 to output a waveform after being divided. 
     In FIG. 2, the divisor selection circuit  620  comprises a first transistor  10  to a sixth transistor  20 . Each transistor comprises a gate, a drain and a source. The gate of the first transistor  10  is coupled to an input terminal IN. The drain of the second transistor  12  is coupled to the source of the first transistor  10 . The drain of the fourth transistor  16  is coupled to the source of the first transistor. The drain of the third transistor  14  is coupled to the source of the second transistor  12 . The drain of the fifth transistor  18  is coupled to the source of the fourth transistor  16 . The source of the third transistor  14  is coupled to the fifth transistor  18 . The drain of the sixth transistor  20  is coupled to the source of the fifth transistor  18 . The gate of the sixth transistor  20  is coupled to the input terminal IN of the divided-by-2 circuit  400 . The source of the sixth transistor  20  is grounded. 
     The translucent circuits  640  as shown in FIG. 2 comprises a seventh transistor  22  to a thirty-second transistor  72 . Each of the transistors  22  to  72  comprises a gate, a drain and a source. The gate of the seventh transistor  22  is coupled to the source of the first transistor  10  of the divisor selection circuit  620 . The drain of the eighth transistor  24  is coupled to the source of the seventh transistor  22 . The gate of the eighth transistor  24  is coupled to the gate of the first transistor  10  of the divisor selection circuit  620 . The gate of the tenth transistor is coupled to the drain of the eighth transistor  24 . The drain of the ninth transistor  26  is coupled to the source of the eighth transistor  24 . The gate of the ninth transistor  26  is coupled to the gate of the seventh transistor  22 . The source of the ninth transistor  26  is grounded. The gate of the eleventh transistor  30  is coupled to the gate of the eighth transistor  24 . The drain of the eleventh transistor  30  is coupled to the source of the tenth transistor  28 . The drain of the twelfth transistor  32  is coupled to the source of the eleventh transistor  30 . The source of the twelfth transistor is grounded. The gate of the twelfth transistor  32  is coupled to the drain of the eighth transistor  24 . The gate of the thirteenth transistor  34  is coupled to the drain of the twelfth transistor  32 . The drain of the fourteenth transistor  36  is coupled to the source of the thirteenth transistor  34 . The gate of the fourteenth transistor  36  is coupled to the gate of the eleventh transistor  30 . The gate of the fifteenth transistor  38  is coupled to the gate of the thirteenth transistor  34 . The source of the fifteenth transistor  38  is coupled to ground. The gate of the sixteenth transistor  40  is coupled to the drain of the fourteenth transistor  36 . The gate of the seventeenth transistor  42  is coupled to the gate of the fourteenth transistor  36 . The drain of the seventeenth transistor  42  is coupled to the source of the sixteenth transistor  40 . The gate of the eighteenth transistor  44  is coupled to the drain  36  of the fourteenth transistor  36 . The source of the eighteenth transistor  44  is grounded. The drain of the eighteenth transistor  44  is coupled to the source of the seventeenth transistor  42 . The gate of the nineteenth transistor  46  is coupled to the drain of the eighteenth transistor  44 . The drain of the twentieth transistor  48  is coupled to the source of the nineteenth transistor  46 . The gate of the twentieth transistor  48  is coupled to the gate of the seventeenth transistor  42 . The gate of the twenty-first transistor  50  is coupled to the gate of the nineteenth transistor  46 . The source of the twenty-first transistor  50  is grounded. The gate of the twenty-second transistor  52  is coupled to the drain of the twentieth transistor  48 . The gate of the twenty-third transistor  54  is coupled to the gate of the twentieth transistor  48 . The drain of the twenty-third transistor  54  is coupled to the source of the twenty-second transistor  52 . The gate of the twenty-fourth transistor  56  is coupled to the drain of the twentieth transistor  48 . The source of the twenty-fourth transistor  56  is grounded. The drain of the twentieth transistor  56  is coupled to the source of the twentieth transistor  54 . The drain of the twenty-fifth transistor  58  is coupled to the drain of the twenty-fourth transistor  56 . The gate of the twenty-fifth transistor  58  is coupled to the gate of the twelfth transistor  32 . The source of the twenty-fifth transistor  58  is coupled to ground. The gate of the twenty-sixth transistor  60  is coupled to the drain of the twenty-fifth transistor  58 . The drain of the twenty-seventh transistor  62  is coupled to the source  60  of the twenty-sixth transistor  60 . The gate of the twenty-seventh transistor  62  is coupled to the gate of the twenty-third transistor  54 . The gate of the twenty-eighth transistor  64  is coupled to the gate of the twenty-sixth transistor  60 . The source of the twenty-eighth transistor  64  is coupled to the gate of the fifth transistor  18  in the divisor selection circuit  620 . The gate of the twenty-ninth transistor  66  is coupled to the drain of the twenty-seventh transistor  62 . The gate of the thirtieth transistor  68  is coupled to the gate of the twenty-ninth transistor  66 . The gate of the thirty-first 
     transistor  70  is coupled to the drain of the twenty-seventh transistor  62 . The source of the thirty-first transistor  70  is grounded. The drain of the thirty-first transistor  70  is coupled to the source of the thirtieth transistor  68 . The drain of the thirty-second transistor  72  is coupled to the drain of the thirty-first transistor  70 . The gate of the thirty-second transistor  72  is coupled to the gate of the twenty-fifth transistor  58 . The source of the thirty-second transistor  72  is coupled to ground. The drain of the thirty-second transistor  72  is further coupled to the gate of the third transistor  14  of the divisor selection circuit  620 . 
     The synthesized divided-by-{fraction (2/2.5)} logic circuit  660  comprises a first NAND logic gate  80 , a second NAND logic gate  82 , a third NAND logic gate  84 , a multiplexer  88  and a NOT logic gate  86 . Each of the first, second and third NAND logic gates has a first input terminal, a second terminal and an output terminal. The first input terminal of the first NAND logic gate  80  is coupled to the drain of the twenty-fifth transistor  58  of the translucent circuit  640 . The second input terminal of the first NAND logic gate  80  is coupled to the drain of the eighteenth transistor  44 . The first input terminal of the second NAND logic gate  82  is coupled to the output terminal of the first NAND logic gate  80 . The output terminal of the third NAND gate is coupled to the second input terminal of the second NAND logic gate  82 . The multiplexer  88  comprises a first input terminal, a second input terminal, an output terminal and a control signal (MC). The first input terminal of the multiplexer  88  is coupled to the drain of the twelfth transistor  32 . The second input terminal of the multiplexer  88  is coupled to the gate of the twelfth transistor  32 . The output terminal of the multiplexer  88  is coupled to the first input terminal of the third NAND logic gate  84 . The NOT logic gate  86  comprises an input terminal and an output terminal. The input terminal of the NOT logic gate  86  is coupled to the second input terminal of the second NAND logic gate  80 , and the output terminal of the NOT gate  86  is coupled to the second input terminal of the second NAND logic gate  84 . 
     The non-synchronously divided-by-{fraction (16/13)} two mode frequency divider  800  comprises a first flip flop  90  to a fifth flip flop  100  and a NOR logic gate  98 . The first flip flop  90  comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal and a SET terminal. The first input terminal and the first output terminal of the first flip flop  90  are coupled to each other. The second input terminal of the first flip flop  90  is coupled to the output terminal of the second NAND logic gate  82  of the synthesized divided-by-{fraction (2/2.5)} logic circuit  660 . The second flip flop  92  comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal and a SET terminal. The first input terminal and the first output terminal of the second flip flop  92  are coupled to each other. The second input terminal of the second flip flop  92  is coupled to the second output terminal of the first flip flop  90 . The SET terminal of the second flip flop  92  is coupled to the SET terminal of the first flip flop  90 . The third flip flop  94  comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal and a CLR terminal. The first input terminal and the first output terminal of the third flip flop  94  are coupled to each other. The second input terminal of the third flip flop  94  is coupled to the second output terminal of the second flip flop  92 . The CLR terminal of the third flip flop  94  is coupled to the SET terminal of the second flip flop  92 . The fourth flip flop  96  comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal and a SET terminal. The first input and output terminals of the fourth flip flop  96  are coupled to each other. The second input terminal of the fourth flip flop  96  is coupled to the second input terminal of the third flip flop  94 . The SET terminal of the fourth flip flop  96  is coupled to the CLR terminal of the third flip flop  94 . The second output terminal of the fourth flip flop  96  is coupled to the output terminal (Out) of the second NAND logic gate  82 , that is, the output terminal of the non-synchronously divided-by{fraction (16/13)} two mode frequency divider  660 . The NOR logic gate  98  comprises a first input terminal, a second input terminal, a third input terminal, a fourth input terminal and an output terminal. The first input terminal of the NOR logic gate  98  is coupled to the second output terminal of the first flip flop  90 . The second input terminal of the NOR logic gate  98  is coupled to the second output terminal of the second flip flop  92 . The third input terminal of the NOR logic gate  98  is coupled to the second output terminal of the third flip flop  94 . The fourth input terminal of the NOR logic gate  98  is coupled to the second output terminal of the fourth flip flop  96 . The fifth flip flop  100  comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a SET terminal and a PRESET terminal. The SET terminal of the fifth flip flop  100  is coupled to the output terminal of the NOR logic gate  98 . The second input terminal of the fifth flip flop  100  is coupled to the second input terminal of the first flip flop  90 . The PRESET terminal of the fifth flip flop  100  is coupled to the SET terminal of the fourth flip flop  96 . 
     When the divisor selection signal MC 1  is 0, the whole circuit performs a divided-by-4 operation. The divided-by-4 signal appears at the major signal nodes denoted as a, b, c, d, e, f, g, h, i. However, the waveform at each of the signal nodes is different. When the input divisor selection signal MC 1  is 1, the whole circuit is divided by 5. A divided-by-5 signal appears at the nodes a, b, c, d, e, f, g, h, i. Again, the waveform at each node is different from others. 
     As the waveform at each node is different from others, different node signal is used to synthesize the fractional division output. Referring to FIG. 3, the clock diagram and the divided-by-2.5 waveform synthesis diagram are shown. This is a signal periodic waveform during the divided-by-5 operation of the synchronously divided-by-⅘. Therefore, it is known that due to the characteristics of the translucent circuits  640 , the waveform at each node has a delay compared to the waveform of its previous node. The required rising edge of the synthesized divided-by-2.5 signal can be obtained. If the rising edge at the node a is the first rising edge of the output divided-by-2.5 signal, the descending edge of the node e can generate the second rising edge required by the divided-by-2.5 signal. The switch between these two signals can be selected by the h node signal. Similarly, referring to FIG. 4, the clock diagram and the divided-by-2 waveform synthesis are shown. This is a signal periodic waveform of the synchronously divided-by-⅘ two mode frequency divider. It can be observed that the nodes of a and f can synthesize the rising edges of these two signals, and the switch can of these two node signals can be selected by the node h. Thus, the synthesized divided-by-{fraction (2/2.5)}  600  is used to synthesize the divided-by-{fraction (2/2.5)} waveform. 
     The non-synchronously divided-by-{fraction (16/13)} comprises a first, second and fourth flip flops  90 ,  92  and  62  as the reset flip flops. The third flip flop  94  included thereby is used as an erase flip flop. The NOR logic gate  98  is a reset control logic NOR gate. When the input external control signal MC-bar is 1, the output of the NOR logic gate  98  is set for not resetting all the time. Therefore, the non-synchronously divided-by-{fraction (16/13)} two mode frequency divider  800  operates at a normal divided-by-16 function. The operation theory can be referred to FIG. 5, which illustrates the sequence of the divided-by-13 function for the non-synchronously divided-by-{fraction (16/13)} two mode frequency divider  800 . When Q 2 -Q 5  are counted to 0, and Z=1, the circuit is not directly reset. However, the next flip flop is used to buffer the reset signal. The circuit is reset while the next clock approaches. The reset signal Reset will remains for a period, and the reset operation has to be reset into 2 instead of 1. The divisor can thus be obtained correctly. 
     According to the above, the prescalar provided by the invention uses a divided-by-2 circuit and a synchronously divided-by-{fraction (2/2.5)} two mode frequency divider to replace the conventional structure of the divided-by-⅘ two mode frequency divider. The input amplifier needs only drive one divided-by-2 circuit. The load is thus a clock load of a single flip flop, so that the frequency response of the input amplifier is increased. The maximum operation frequency of the prescalar is thus increased. 
     Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.