Abstract:
A line trouble detecting circuit comprises a peak detecting circuit, a first comparison circuit, a bottom detecting circuit, a bottom detecting circuit, a second comparison circuit, and a signal keeping circuit. 
     The peak detecting circuit detects a peak voltage of amplitude of the one of the differential signal. The first comparison circuit compares an output of the peak detector and a first reference voltage. The bottom detecting circuit detects bottom voltage of the amplitude of the one of the differential signal. The second comparison circuit compares an output of the bottom detecting circuit and a second reference voltage. The signal keeping circuit keeps a signal from the first comparison circuit or the second comparison circuit.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention is to be applied to a differential transmission line composed of two transmission lines for which impedance control is required. 
         [0003]    2. Description of related Art 
         [0004]    In a differential transmission line, the effect of the common mode input noise is reduced by individually transmitting differential signals to two signal lines. An example of a configuration using a differential transmission line is a configuration in which an optical transceiver and a media converter are connected. A media converter is disposed at an input and output port of a router (IP switch) or a bridge (L2 switch). There are configurations in which a media converter and a router or bridge are integrated, and an optical transceiver and a media converter are integrated. 
         [0005]    The relationship between an optical transceiver, a differential transmission line, and a transmission apparatus such as a media converter is shown in  FIG. 1 . An optical transceiver  1 , a transmission apparatus  2  such as a media converter, terminating resistors  3   a  to  3   d , transmission lines  4   a ,  4   b ,  5   a , and  5   b , an optical receiving circuit  11 , an optical transmitting circuit  12 , a light-receiving device  11   a , and a light-emitting device  12   a  are shown. 
         [0006]    Light received by the light-receiving device  11   a  is amplified by the optical receiving circuit  11  and is then output to the transmission lines  4   a  and  4   b  as differential signals. A signal having a polarity opposite to that of a signal passing through the transmission line  4   a  is provided for the transmission line  4   b . A differential transmission line  4  is achieved by providing such differential signals for the transmission lines  4   a  and  4   b . The impedance of the transmission line  4   a  is made to match that of the transmission line  4   b  by the terminating resistors  3   a  and  3   b  and the ground. The impedance-matched transmission lines  4   a  and  4   b  are connected to the transmission apparatus  2 . 
         [0007]    The differential signals output from the transmission apparatus  2  are provided for the impedance-matched transmission lines  5   a  and  5   b . A differential transmission line  5  is composed of the transmission lines  5   a  and  5   b . The impedance matching is performed by the terminating resistors  3   a  and  3   b  connected to the transmission lines  5   a  and  5   b  and the ground. The differential signals transmitted from the transmission lines  5   a  and  5   b  are input into the optical transmitting circuit  12 . The transmitting circuit  12  causes the light-emitting device  12   a  such as a laser to emit light on the basis of the received differential signals. 
       SUMMARY OF THE INVENTION 
       [0008]    According to an aspect of an embodiment, a line trouble detecting circuit detects a line trouble of a differential pair. The differential pair transmits a differential signal with a first line and a second line earthed via termination resistors, respectively. 
         [0009]    The line trouble detecting circuit comprises a peak detecting circuit, a first comparison circuit, a bottom detecting circuit, a second comparison circuit, and a signal keeping circuit. The peak detecting circuit detects a peak voltage of amplitude of the one of the differential signal. The first comparison circuit compares an output of the peak detector and a first reference voltage. The bottom detecting circuit detects bottom voltage of the amplitude of the one of the differential signal. The second comparison circuit compares an output of the bottom detecting circuit and a second reference voltage. The signal keeping circuit keeps a signal from the first comparison circuit or the second comparison circuit. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a diagram showing a relationship between an optical transceiver, a differential transmission line, and a transmission apparatus. 
           [0011]      FIG. 2  is a diagram showing examples of a fault occurring at terminating resistors  3   a  and  3   b  disposed between a differential transmission line and the ground. 
           [0012]      FIG. 3  is a diagram showing characteristics obtained when a terminating resistor is short-circuited. 
           [0013]      FIG. 4  is a diagram showing characteristics obtained when the connection between a terminating resistor and the ground is disconnected. 
           [0014]      FIG. 5  is a diagram showing a specific configuration of a line fault detection circuit. 
           [0015]      FIG. 6  is a diagram showing a specific configuration of each of peak detecting circuit and an amplitude detection circuit. 
           [0016]      FIG. 7  is a diagram showing signal output waveforms of individual blocks included in the line fault detection circuit. 
           [0017]      FIG. 8  is a diagram showing signal output waveforms of individual blocks included in the line fault detection circuit. 
           [0018]      FIG. 9  is a diagram showing a specific configuration of a line fault detection circuit. 
           [0019]      FIG. 10  is a diagram showing characteristics of the line fault detection circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0020]    This embodiment is to be applied to a differential transmission line composed of two transmission lines for which impedance control is required. 
         [0021]    It is an object of the embodiment is to provide a technique for detecting a line fault even when the line fault occurs at a terminating resistor that is disposed between a line and the ground so as to achieve impedance matching of a differential transmission line composed of two transmission lines for which impedance control is required. 
         [0022]    Embodiments will be described with reference to the accompanying drawings. A configuration according to an embodiment is illustrative, and the present invention is not limited to this configuration. 
         [0023]    Examples of a fault detected in the present invention will be described with reference to  FIGS. 2 ,  3 , and  4 . Examples of a fault occurring at the terminating resistors  3   a  and  3   b  which are disposed between the differential transmission line and the ground are shown in  FIG. 2 . In  FIG. 2 , the same reference numerals are used for components having the same functions as those of  FIG. 1  so as to avoid repeated explanation.  FIG. 2(   a ) shows an example in which the terminating resistor  3   a  is broken and the differential transmission line is directly connected to the ground.  FIG. 2(   b ) shows an example in which the connection between the terminating resistor  3   a  and the ground is broken at  3   c .  FIG. 3  shows characteristics obtained when the terminating resistor is short-circuited as shown in  FIG. 2(   a ).  FIG. 3(   a ) shows a signal transmitted from the receiving circuit to the transmission line  4   a  of the differential transmission line  4  in  FIG. 2 .  FIG. 3(   b ) shows a state in which a signal whose amplitude is inverted and whose phase is shifted occurs due to signal reflection at the point of the ground.  FIG. 3(   c ) shows a signal input into the transmission apparatus  2  shown in  FIG. 2 . The signal shown in  FIG. 3(   c ) is a signal obtained by combining the signal shown in  FIG. 3(   a ) which is transmitted through the transmission line  4   a  and the signal shown in  FIG. 3(   b ) which is returned due to the reflection.  FIG. 3(   d ) shows an eye pattern obtained in a normal state.  FIG. 3(   e ) shows an eye pattern obtained when the terminating resistor  3   a  is short-circuited as shown in  FIG. 2(   a ). As is apparent from  FIGS. 3(   c ) and  3 ( e ), the entire signal level decreases compared with that of the original signal, and eye apertures are narrowed. Accordingly, the occurrence of such a fault can be detected by detecting a decrease in a peak voltage in the center potion of the eye pattern.  FIG. 4  shows characteristics obtained when the connection between the terminating resistor and the ground is broken as shown in  FIG. 2(   b ).  FIG. 4(   a ) shows a signal transmitted from the receiving circuit to the transmission line  4   a  of the differential transmission line  4  in  FIG. 2 .  FIG. 4(   b ) shows a state in which a signal whose level decreases at the terminating resistor  3   a  and whose phase is shifted occurs.  FIG. 4(   c ) shows a signal input into the transmission apparatus  2  shown in  FIG. 2 . The signal shown in  FIG. 4(   c ) is a signal obtained by combining the signal shown in  FIG. 4(   a ) which is transmitted through the transmission line  4   a  and the signal shown in  FIG. 4(   b ).  FIG. 4(   d ) shows an eye pattern obtained in a normal state.  FIG. 4(   e ) shows an eye pattern obtained when the connection between the terminating resistor and the ground is broken as shown in  FIG. 2(   b ). As is apparent from  FIGS. 4(   c ) and  4 ( e ), the entire signal level increases compared with that of the original signal, and eye apertures are narrowed due to the change in the phase. Accordingly, the occurrence of such a fault can be detected by detecting an increase in a peak voltage in the center portion of the eye pattern. 
       First Embodiment  
       [0024]    As is apparent from the above-described characteristics of the voltage waveforms, the occurrence of a fault at a terminating resistor can be detected by disposing at an end portion of a differential amplitude transmission line a circuit for detecting whether the level of a voltage in the center portion of an eye pattern is higher or lower than usual. The specific configuration of a line fault detection circuit using the above-described principles is shown in  FIG. 5 . In  FIG. 5 , the same reference numerals are used for components having the same functions as those of  FIG. 1  so as to avoid repeated explanation. Referring to  FIG. 5 , a line fault detection circuit  600  for detecting a line fault in a first line of the differential transmission line shown in  FIG. 1  and a line fault detection circuit  500  for detecting a line fault in a second line of the differential transmission line shown in  FIG. 1  are shown. The line fault detection circuits  500  and  600  have peak detecting circuits  510  and  610 , first comparing circuits  530  and  630 , trough detecting circuits  520  and  620 , second comparing circuits  540  and  640 , and signal maintaining circuits  550  and  650 , respectively. In the line fault detection circuits  500  and  600 , the circuits having the same names have the same functions. Individual circuit will be therefore described in the following using the line fault detection circuit  500 . 
         [0025]    [Peak Detecting Circuit] 
         [0026]    The peak detecting circuit  510  has an input point that is a connection point between the second line and the terminating resistor  3   b . The peak detecting circuit  510  removes a bias component included in a signal voltage and outputs a signal amplitude. The specific circuit configuration thereof will be described later with reference to  FIG. 6 . 
         [0027]    [First Comparing Circuit] 
         [0028]    The first comparing circuit  530  compares the output of the peak detecting circuit  510  with a first voltage  531  that is a reference voltage. More specifically, the first comparing circuit  530  is configured with an operational amplifier. The output of the peak detecting circuit  510  is input into the non-inverting input terminal of the operational amplifier. The first reference voltage  531  is input into the inverting input terminal of the operational amplifier. When the output of the peak detecting circuit  510  is larger than the value of the first reference voltage  531 , a voltage is output from the output terminal of the operational amplifier. The first reference voltage  531  is set to a voltage higher than a voltage output from the optical receiving circuit  11 . By performing such a voltage setting, when the fault shown in  FIG. 2(   b ) occurs and the signal shown in  FIG. 4  occurs in the second transmission line  4   b , it can be determined that a fault has occurred. The output of the first comparing circuit  530  is input into the signal maintaining circuit  550 . 
         [0029]    [Trough Detecting Circuit] 
         [0030]    Like the peak detecting circuit  510 , the trough detecting circuit  520  has an input point that is a connection point between the second line and the terminating resistor  3   b . The trough detecting circuit  520  includes a signal inverting circuit  521 , a switch  522 , and an amplitude detection circuit  523 . The signal inverting circuit  521  inverts a signal voltage input into the trough detecting circuit  520 . The output of the signal inverting circuit  521  is input into the switch  522 . The switch  522  passes the output of the signal inverting circuit  521  when the level of a signal passing through the first line is low. Furthermore, the switch  522  interrupts the output of the signal inverting circuit  521  when the level of the signal passing through the first line is high. The output of the switch  522  is input into the amplitude detection circuit  523 . The amplitude detection circuit  523  removes a bias component included in the signal voltage output from the switch  522 , and outputs a signal amplitude. The specific circuit configuration thereof will be described later with reference to  FIG. 6 . The output of the amplitude detection circuit  523  is input into the second comparing circuit. 
         [0031]    [Second Comparing Circuit] 
         [0032]    The second comparing circuit  540  compares the output of the trough detecting circuit  520  (the output of the amplitude detection circuit  523 ) with a second voltage  541  that is a reference voltage. More specifically, the second comparing circuit  540  is configured with an operational amplifier. The output of the trough detecting circuit  520  is input into the non-inverting input terminal of the operational amplifier. The second reference voltage  541  is input into the inverting input terminal of the operational amplifier. When the output of the trough detecting circuit  520  is higher than the value of the second reference voltage  531 , a voltage is output from the output terminal of the operational amplifier. The second reference voltage  541  is set to a voltage lower than a voltage output from the optical receiving circuit  11 . By performing such a voltage setting, when the fault shown in  FIG. 2(   a ) occurs and the signal shown in  FIG. 3  occurs in the second transmission line  4   b , it can be determined that a fault has occurred. The output of the second comparing circuit  540  is input into the signal maintaining circuit  550 . 
         [0033]    [Signal Maintaining Circuit] 
         [0034]    The signal maintaining circuit  550  receives the outputs of the first comparing circuit  530  and the second comparing circuit  540 . More specifically, signals output from the first comparing circuit  530  and the second comparing circuit  540  are input into an OR gate  551 . The OR gate  551  sets the output thereof to a high level when receiving high-level signals from the first comparing circuit  530  and the second comparing circuit  540 . The output of the OR gate  551  is input into a flip-flop circuit  552 . The flip-flop circuit  552  maintains the high-level output of the OR gate  551  and transmits the maintained high-level output. 
         [0035]    [Peak Detecting Circuit and Amplitude Detection Circuit] 
         [0036]    The specific configuration of the peak detecting circuit and the amplitude detecting circuit is shown in  FIG. 6 . The peak detecting circuit  510  and the amplitude detection circuit  523  are configured with the same circuit. The circuit includes a first diode  700  whose cathode is connected to the input terminal of the peak detecting circuit  510  or the amplitude detection circuit  523  and a second diode  701  whose anode is connected to the input terminal of the peak detecting circuit  510  or the amplitude detection circuit  523 . The anode of the first diode  700  is connected to the ground. The cathode of the second diode  701  serves as an output terminal of the peak detecting circuit or the amplitude detection circuit. When a reverse bias is applied to the first diode  700 , a bias component included in an input signal voltage is connected to the ground potential, whereby an amplitude value of the input voltage can be obtained as an output voltage value. 
         [0037]    [Fault Detection Process in  FIG. 2(   a )] 
         [0038]      FIG. 7  is a diagram describing a process of detecting the fault shown in  FIG. 2(   a ). Waveforms shown in  FIG. 7  will be described using the corresponding blocks shown in  FIG. 5 . Voltage waveforms  71   a  to  78   a  are obtained when the fault shown in  FIG. 2(   a ) occurs. 
         [0039]    The voltage waveform  71   a  is output from the receiving circuit  11 . The voltage waveform  72   a  denotes a voltage at the connection point between the second line and the terminating resistor  3   b . The voltage waveform  72   a  is input into the signal inverting circuit  521  included in the trough detecting circuit  520 , so that the voltage waveform  73   a  is output. The voltage waveform  74   a  denotes a signal passing through the first line. When the level of the voltage waveform  74   a  is low, the switch  522  is turned on and a voltage signal is output from the signal inverting circuit  521  to the amplitude detection circuit  523 . When the level of the voltage waveform  74   a  is high, the switch  522  is turned off and no voltage is input into the amplitude detection circuit  523 . The waveform  75   a  denotes a voltage output waveform of the switch  522 . A voltage represented by the voltage output waveform  75   a  is input into the amplitude detection circuit  523 . The amplitude detection circuit  523  removes a bias voltage component from the voltage output waveform  75   a  so as to obtain only an amplitude component and outputs the obtained voltage output waveform  76   a . The voltage output waveform  76 a is input into the non-inverting input terminal of the second comparing circuit  540 . The second comparing circuit  540  compares a voltage represented by the voltage output waveform  76   a  with the second reference voltage  541 , and outputs the voltage output waveform  77   a . The voltage output waveform  77   a  is input into the flip-flop circuit  552  via the OR gate  551 . The flip-flop circuit  552  maintains the received signal, and outputs the voltage output waveform  78   a.    
         [0040]    Voltage waveforms  71   b  to  78   b  are obtained when the fault shown in  FIG. 2(   a ) does not occur. The voltage waveform  71   b  is output from the receiving circuit  11 . The voltage waveform  72   b  denotes a voltage at the connection point between the second line and the terminating resistor  3   b . The voltage waveform  72   b  is input into the signal inverting circuit  521  included in the trough detecting circuit  520 , so that the voltage waveform  73   b  is output. The voltage waveform  74   b  denotes a signal passing through the first line. When the level of the voltage waveform  74   b  is low, the switch  522  is turned on and a voltage signal is output from the signal inverting circuit  521  to the amplitude detection circuit  523 . When the level of the voltage waveform  74   a  is high, the switch  522  is turned off and no voltage is input into the amplitude detection circuit  523 . The waveform  75   b  denotes a voltage output waveform of the switch  522 . A voltage represented by the voltage output waveform  75   b  is input into the amplitude detection circuit  523 . Since the voltage represented by the voltage output waveform  75   b  does not vary, the voltage is connected to the ground potential. Accordingly, the amplitude detection circuit  523  outputs nothing as shown in the voltage output waveform  76   b . The voltage output waveform  76   b  is input into the non-inverting input terminal of the second comparing circuit  540 . The second comparing circuit  540  compares a voltage represented by the voltage output waveform  76   b  with the second reference voltage  541 . Since the level of the voltage output waveform  76   b  is lower than that of the second reference voltage  541 , the second comparing circuit  540  outputs nothing. The voltage output waveform  77   b  having no signal is input into the flip-flop circuit  552  via the OR gate  551 . 
         [0041]    [Fault Detection Process in  FIG. 2(   b )] 
         [0042]      FIG. 8  is a diagram describing a process of detecting the fault shown in  FIG. 2(   b ). Waveforms shown in  FIG. 8  will be described in the following using the corresponding blocks shown in  FIG. 5 . Voltage waveforms  81   a  to  85   a  are obtained when the fault shown in  FIG. 2(   b ) occurs. 
         [0043]    The voltage waveform  81   a  is output from the receiving circuit  11 . The voltage waveform  82   a  denotes a voltage at the connection point between the second line and the terminating resistor  3   b . The voltage waveform  82   a  is input into the peak detecting circuit  510 , so that the voltage waveform  83   a  is output. The peak detecting circuit  510  removes a bias voltage component from the voltage output waveform  82   a  so as to obtain only an amplitude component and outputs the obtained voltage output waveform  83   a . The voltage output waveform  83   a  is input into the non-inverting input terminal of the first comparing circuit  530 . The first comparing circuit  530  compares a voltage represented by the voltage output waveform  83   a  with the first reference voltage  531 , and outputs the voltage output waveform  84   a . The voltage output waveform  84   a  is input into the flip-flop circuit  552  via the OR gate  551 . The flip-flop circuit  552  maintains the received signal, and outputs the voltage output waveform  85   a.    
         [0044]    Voltage waveforms  81   b  to  85   b  are obtained in a normal state in  FIG. 2(   b ). The voltage waveform  81   b  is output from the receiving circuit  11 . The voltage waveform  82   b  denotes a voltage at the connection point between the second line and the terminating resistor  3   b . The voltage waveform  82   b  is input into the peak detecting circuit  510 , so that the voltage waveform  83   b  (no signal) is output. The peak detecting circuit  510  removes a bias voltage component from the voltage waveform  82   b . However, since an amplitude component does not vary in the voltage waveform  82   b , the peak detecting circuit  510  outputs no voltage. Accordingly, in the subsequent circuits, no signal is output. 
         [0045]    Thus, the first embodiment has been described with reference to the line fault detection circuit  500 . A difference between the line fault detection circuits  500  and  600  is that the line fault detection circuit  500  detects a fault in the second line and the line fault detection circuit  600  detects a fault in the first line. Accordingly, in the line fault detection circuit  500 , the voltage of the second line is input into the peak detecting circuit  510  and the signal inverting circuit  521  included in the trough detecting circuit  520 . In the line fault detection circuit  600 , the voltage of the first line is input into the peak detecting circuit  610  and a signal inverting circuit  621  included in the trough detecting circuit  620 . 
       Second Embodiment  
       [0046]    As is apparent from the voltage waveforms shown in  FIGS. 3 and 4 , if a fault occurs at a terminating resistor, a voltage value different from a usual voltage value is obtained regardless of whether the terminating resistor is short-circuited or disconnected. Here, it is assumed that the other line is in a normal state. The line fault can be detected by comparing voltage conditions of lines. The specific configuration of a line fault detection circuit for comparing voltage conditions of lines is shown in  FIG. 9 . The line fault detection circuit includes first voltage amplitude detecting circuit, second voltage amplitude detecting circuit, first comparing circuit, second comparing circuit, third comparing circuit, and signal maintaining circuit. The configurations of these circuits will be individually described in the following. In  FIG. 9 , the same reference numerals are used for components having the same functions as those of  FIG. 1  so as to avoid repeated explanation. 
         [0047]    [First Voltage Amplitude Detecting Circuit] 
         [0048]    First voltage amplitude detecting circuit  810  is configured with the circuit shown in  FIG. 6 . A voltage is input from the first line  4   a  to an input portion of the first voltage amplitude detecting circuit  810 . A bias potential included in the voltage waveform that has been input threreinto is removed, and an amplitude voltage is then output. 
         [0049]    [Second Voltage Amplitude Detecting Circuit] 
         [0050]    A second voltage amplitude detecting circuit  820  is configured with the circuit shown in  FIG. 6 . A voltage is input from the second line  4   b  to an input portion of the second voltage amplitude detecting circuit  820 . A bias potential included in the voltage waveform that has been input thereinto is removed, and an amplitude voltage is then output. 
         [0051]    [First Comparing Circuit] 
         [0052]    First comparing circuit  830  is configured with an operational amplifier. The output of the first voltage amplitude detecting circuit is input into the non-inverting input terminal of the operational amplifier. The output of the second voltage amplitude detecting circuit is input into the inverting input terminal of the operational amplifier. The operational amplifier compares values of voltages output from the first voltage amplitude detecting circuit and the second voltage amplitude detecting circuit, and outputs the comparison result from the output terminal thereof. The output characteristics of the output terminal are shown in  FIG. 10 . 
         [0053]    [Second Comparing Circuit] 
         [0054]    Second comparing circuit  840  is configured with an operational amplifier. The output of the first comparing circuit is input into the non-inverting input terminal of the operational amplifier. A first reference voltage is input into the inverting input terminal of the operational amplifier. The value of the first reference voltage is a value of a voltage V 1  shown in  FIG. 10 . When the voltage of the first comparing circuit is larger than the first reference voltage V 1 , a voltage is output from the output terminal of the second comparing circuit  840 . 
         [0055]    [Third Comparing Circuit] 
         [0056]    Third comparing circuit  850  is configured with an operational amplifier. The output of the first comparing circuit is input into the inverting input terminal of the operational amplifier. A second reference voltage is input into the non-inverting input terminal of the operational amplifier. The value of the second reference voltage is a value of a voltage V 2  shown in  FIG. 10 . When the voltage of the first comparing circuit is lower than the second reference voltage V 2 , a voltage is output from the output terminal of the third comparing circuit  850 . 
         [0057]    [Signal Maintaining Circuit] 
         [0058]    Signal maintaining circuit  860  receives the outputs of the second comparing circuit  840  and the third comparing circuit  850 . More specifically, signals output from the second comparing circuit  840  and the third comparing circuit  850  are input into an OR gate  861 . When the OR gate  861  receives high-level signals from the second comparing circuit  840  and the third comparing circuit  850 , it sets the output thereof to a high level. The output of the OR gate  861  is input into a flip-flop circuit  862 . The flip-flop circuit  862  maintains the high-level output of the OR gate  861 , and transmits the maintained output. 
         [0059]    According to the present invention, a line fault can be detected by comparing a voltage waveform of a line with a reference voltage even when the line fault occurs at a terminating resistor that is disposed between the line and the ground so as to achieve impedance matching of a differential transmission line composed of two transmission lines for which impedance control is required. Furthermore, a line fault can be detected by comparing voltage waveforms of lines. 
         [0060]    According to the present embodiments, a line fault can be detected even when the line fault occurs at a terminating resistor that is disposed between a line and the ground so as to achieve impedance matching of a differential transmission line composed of two transmission lines for which impedance control is required.