Abstract:
A surface roughening method for an embedded semiconductor chip structure is proposed. The method includes providing a carrier board with an opening and mounting a semiconductor chip in the opening of the carrier board, the semiconductor chip having a plurality of electrode pads; and performing a surface roughening process on a surface of the electrode pads of the semiconductor chip, so as to form a rough structure on a surface of the semiconductor chip exposed by the opening of the carrier board. Thus, adhesion between the chip and a dielectric layer is improved during subsequently forming circuit build-up layers on the roughened surface of the semiconductor chip and on the surface of carrier board.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates generally to a surface roughening method for an embedded semiconductor chip structure, and more particularly to a method for roughening a surface of a semiconductor chip which is stably mounted to a carrier board.  
         [0003]     2. Description of Related Art  
         [0004]     Referring to  FIG. 1 , a conventional embedded semiconductor chip package structure is shown. The package structure comprises: a heat spreader  102  having at least a recess portion  104 ; a semiconductor chip  114  mounted in the recess portion  104  via its non-active surface  118  by an adhesive layer  120 ; and a circuit structure  122  formed on the heat spreader  102  and the semiconductor chip  114 .  
         [0005]     Since no surface roughening method is adopted in the above package structure, dc-lamination is easy to occur to the semiconductor chip  114  mounted in a substrate. To solve this problem, a surface roughening process such as a micro-etch process is usually performed on a die comprising a plurality of semiconductor chips. Thereby, a plurality of semiconductor chips with rough surface structure can be obtained. Afterwards, a cutting process can be performed to separate the plurality of the semiconductor chips from each other. Then, one of the semiconductor chips having the roughed structure can be mounted to the beat spreader  102  to increase the bonding force between the semiconductor chip and the circuit structure.  
         [0006]     However, while roughening surface of the plurality of semiconductor chips of a die by a micro-etch process, the roughened surface of the semiconductor chips often becomes uneven because the die immerged in an etching solution is large in size or too many dies are immerged in the etching solution. In addition, since the surface roughening process is generally performed after the die has been thinned, such problems as die break and die scratch are easy to occur to such a thinned die. Furthermore, it needs long time to separate a semiconductor chip having rough surface structure from a die and mount it to a heat spreader, and accordingly the rough surface of the semiconductor chip may be oxidized, which adversely affects the reliability of a subsequent process.  
       SUMMARY OF THE INVENTION  
       [0007]     Accordingly, it is an objective of the present invention to provide a surface roughening method for an embedded semiconductor chip structure, through which a uniformly rough structure can be formed on a surface of the embedded semiconductor chip.  
         [0008]     It is another objective of the present invention to provide a surface roughening method for an embedded semiconductor chip structure, through which a subsequent fabricating process can be performed directly on the roughened surface of the semiconductor chip so as to avoid oxidization of the roughened surface.  
         [0009]     A further objective of the present invention is to provide a surface roughening method for an embedded semiconductor chip structure, which can increase fabrication throughput and improve product yield.  
         [0010]     In order to attain the objectives mentioned above and the others, a surface roughening method for an embedded semiconductor chip structure according to a first embodiment of the present invention comprises the steps of: providing a carrier board with an opening, a semiconductor chip being mounted in the opening of the carrier board; and performing a surface roughening process on a surface of the semiconductor chip, so as to form a rough structure on the surface of the semiconductor chip exposed by the opening of the carrier board.  
         [0011]     In another embodiment of the present invention, a surface roughening method for an embedded semiconductor chip structure comprises the steps of: providing a carrier board with an opening, a semiconductor chip being mounted in the opening of the carrier board; and performing a surface roughening process on a surface of the semiconductor chip and a surface of the carrier board, so as to form a rough structure on the surface of the semiconductor chip exposed by the opening of the carrier board and on the surface of the carrier board.  
         [0012]     The surface roughening method according to the previous embodiments of the present invention can be selectively applied on the surface of the semiconductor chip or on both the surface of the semiconductor chip and the surface of the carrier board. After performing the surface roughening process, a circuit build-up process can be performed on the roughened surface of the semiconductor chip and the carrier board.  
         [0013]     Furthermore, the surface roughening process can be selectively applied onan active surface and/or a non-active surface of the semiconductor chip, and the carrier board can be one of a metal board, a circuit board or a dielectric board.  
         [0014]     According to the present invention, because the surface roughening process is performed after the semiconductor chip is stably mounted to the carrier board, a uniformly rough structure can be achieved on surface of the semiconductor chip. Meanwhile, the conventional problems such as chip surface oxidization, die break and die scratch can be prevented. Further, since a circuit build-up process can be directly performed on the rough structure, the fabrication throughput is increased and the product yield is improved. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0015]      FIG. 1  is a sectional diagram showing a conventional embedded semiconductor chip package structure;  
         [0016]      FIGS. 2A  to  2 C are sectional diagrams showing a surface roughening method for an embedded semiconductor chip structure according to a first embodiment of the present invention;  
         [0017]      FIGS. 3A and 3B  are sectional diagrams showing a surface roughening method for an embedded semiconductor chip structure according to a second embodiment of the present invention; and  
         [0018]      FIG. 4  is a sectional diagram showing a surface roughening method for an embedded semiconductor chip structure according to a third embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0019]     The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.  
         [0020]      FIGS. 2A  to  2 C show a surface roughening method for an embedded semiconductor chip structure according to a first embodiment of the present invention.  
         [0021]     Referring to  FIG. 2A , a carrier board  20  with an opening  200  is provided. The carrier board  20  can be a dielectric board, a metal board or a circuit board of a single-layer or multi-layer structure. The opening  200  can be a through hole penetrating through the carrier board  20 . Alternatively, the opening  200  can have a recess structure without penetrating through the carrier board  20 .  
         [0022]     Referring to  FIG. 2B , a semiconductor chip  21  having an active surface  21   a  and a non-active surface  21   b  is mounted in the opening  200  of the carrier board  20  with its active surface  21   a  exposed from the opening  200  of the carrier board  20 . Therein, the active surface  21   a  of the semiconductor chip  21  has a plurality of electrode pads  21   c . Afterwards, different surface roughening processes are performed at different areas of the active surface  21   a  of the semiconductor chip  21 , wherein, the surface  211  of the electrode pads  21   c  is roughened through an oxide process, a brown oxide process or a micro-etch process. The area  212  outside the electrode pads  21   c  such as passivation layer of the semiconductor chip  21  is roughened through a plasma etching process, a plasma desmearing process or a reactive ion etching process. Thereby, different rough structures are formed on the semiconductor chip  21 .  
         [0023]     In the present embodiment, the semiconductor chip  21  is roughened through a micro-etch process by using an etching solution comprising H 2 SO 4  and H 2 O 2  such that a rough structure can be formed on surface of the semiconductor chip  21  corresponding to the opening  200  of the carrier board  20 . Preferably, the depth of the rough structure is ranged between 0.2 μm and 2.5 μm.  
         [0024]     Referring to  FIG. 2C , a circuit build-up structure  22  is formed on surfaces of the carrier board  20  and the active surface  21   a  of the semiconductor chip  21 , wherein the roughened surface of the active surface  21   a  provides a preferred bonding force between the active surface  21   a  and the circuit build-up structure  22 .  
         [0025]     It should be noted that the non-active surface  21   b  of the semiconductor chip  21  can also be roughened if a circuit or dielectric layer build-up structure needs to be formed on the non-active surface  21   b . In addition, the semiconductor chip  21  can be partially received by the opening  200  of the carrier board  20  so as to increase the roughening surface of the semiconductor chip  21 . Furthermore, the etching solution is not limited to the above mentioned solution. The etching solution can be such as an acidic solution, a basic solution or an acidic-basic solution.  
         [0026]     Therefore, through the above surface roughening process on surface of a semiconductor chip mounted to a carrier board, a uniformly rough structure can be formed on the surface of the semiconductor chip. Thus, a circuit build-up process can directly be performed on the uniformly rough structure so as to increase fabrication throughput and improve product yield. Also, the conventional problems such as die break, die scratch and rough surface oxidization are prevented.  
         [0027]      FIGS. 3A and 3B  show a surface roughening method for an embedded semiconductor chip structure according to a second embodiment of the present invention. In the present embodiment, not only the surface of the semiconductor chip is roughened, the surface of the carrier board is also roughened so as to simplify the fabricating process and increase bonding area for a subsequent circuit build-up process.  
         [0028]     Referring to  FIG. 3A , a carrier board  30  with an opening  300  is provided. The carrier board  30  can be a dielectric board, a metal board or a circuit board of a single-layer or multi-layer structure. The opening  300  can be a through hole penetrating through the carrier board  30 . Alternatively, the opening  300  can be a recess without penetrating through the carrier board  30 . A semiconductor chip  31  having an active surface  31   a  and a non-active surface  31   b  is mounted in the opening  300  of the carrier board  30  with its active surface  31   a  exposed from the opening  300  of the carrier board  30 . Afterwards, different surface roughening processes are performed on the active surface  31   a  of the semiconductor chip  31  and surface of the carrier board  30 , wherein, the surface  311  of the electrode pads  31   c  is roughened through an oxide process, a brown oxide process or a micro-etch process. The area  312  outside the electrode pads  31   c  such as passivation layer of the semiconductor chip  31  and the surface  301  of the carrier board  30  are roughened through a plasma etching process, a plasma desmearing process or a reactive ion etching process. Thereby, different rough structures are formed. Of course, the non-active surface  31   b  of the semiconductor chip  31  can also be roughed if needed.  
         [0029]     Referring to  FIG. 3B , a circuit build-up structure  32  is formed on surfaces of the carrier board  30  and the active surface  31   a  of the semiconductor chip  31 . The roughened surfaces of the active surface  31   a  and the carrier board  30  efficiently increase the bonding force between the circuit build-up structure  32  and the active surface  31   a , and between the circuit build-up structure  32  and the carrier board  30 .  
         [0030]     Referring to  FIG. 4 , a surface roughening method according to a third embodiment of the present invention is shown. A circuit board  30 ′ with a circuit layer is used as the carrier board  30 . The surface  311  of the electrode pads  31   c  and the circuit  301 ′ of the circuit board  30 ′ are roughened through an oxide process, a brown oxide process or a micro-etch process. The area  312  outside the electrode pads  31   c  such as passivation layer of the semiconductor chip  31  and the dielectric surface  301  of the carrier board are roughened through a plasma etching process, a plasma desmearing process or a reactive ion etching process. Thereby, different rough structures are formed so as to form a circuit build-up layer  32  thereon subsequently.  
         [0031]     According to the present invention, since both surfaces of the semiconductor chip and the carrier board can be roughened, a large efficient bonding area can be provided for the subsequent circuit build-up process, thereby strengthening the adhesion force of the circuit build-up structure. In addition, because the surface roughening process is performed after the semiconductor chip is stably mounted to the carrier board and the circuit build-up process is performed directly on the rough structure formed in the surface roughening process, conventional problems such as chip surface oxidization, die break and die scratch can be prevented, thereby increasing the fabrication throughput and the product yield.  
         [0032]     The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention, i.e., other changes still can be implemented in the present invention. For example, for those circuit boards that have very similar component layout, sometimes a single masking board may be used by simply blocking those unwanted openings. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.