Abstract:
The present invention is made to improve the conventional analog processing that is easily affected by variations in semiconductor processing. This invention provides a wobble signal processing apparatus that can reduce the circuit scale and the power consumption as well as improve the quality of signal processing. The wobble signal processing apparatus of the present invention digitally processes a part that has conventionally been processed by an analog system, and further a PRML circuit is provided to implement error detection, whereby the circuit scale and the power consumption is reduced. This improves the detection of a signal that is inputted to the wobble signal processing apparatus.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a signal processing system in the technology of digital signal processing for optical discs (recording media).  
         BACKGROUND OF THE INVENTION  
         [0002]    In conventional wobble signal processing apparatus, means for processing signals by an analog system are utilized (see, for example, Japanese Examined Patent Publication No. Hei.6-19898). As methods for phase-modulating wobbles on tracks by these conventional wobble signal processing apparatus, methods such as BPSK, DPSK, and QPSK have been proposed.  
           [0003]    However, the analog processing of the conventional wobble signal processing apparatus is easily affected by processing variations in the semiconductor processing and, for example, the resistance or capacitance value may deviate from the set value by several to dozens percent. In addition, deviation of a supply voltage value in the power supply unit may cause a fatal problem in the analog system that requires a fine set value. For example, when a filter parameter such as the cutoff frequency of a BPF or LPF deviates, the filter characteristics are deteriorated. When the power supply value of an analog unit cannot obtain a set value with stability, the supply voltage characteristics vary, and then the filter characteristics are deteriorated. Further, as the delay amount varies in the analog system, a circuit for phase compensation is required, thereby adversely increasing the circuit scale and the power consumption.  
         SUMMARY OF THE INVENTION  
         [0004]    The present invention has for its object to provide a wobble signal processing apparatus that can reduce the circuit scale and the power consumption, and improve the quality of signal processing.  
           [0005]    Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the spirit and scope of the invention will be apparent to those of skill in the art from the detailed description.  
           [0006]    According to a 1st aspect of the present invention, there is provided a wobble signal processing apparatus comprising: a pickup for reading information recorded on an optical disc medium on/from which data can be recorded/reproduced; a WBL binarization circuit for smoothing edges of a wobble binary signal that is read by the pickup; a FEP (Front End Processor) for performing band limitation and gain control to a wobble signal that is read by the pickup; an ADC (Analog-to-Digital Converter) for converting the wobble signal outputted from the FEP into a digital signal; an address detection circuit for detecting an ADIP (Address In Pre-Groove) signal as address information of the data on the basis of the digital signal outputted from the ADC; a waveform shaping circuit for generating a wobble binary signal waveform on the basis of a RF signal that is read by the pickup; a phase control circuit for controlling the phase of the wobble binary signal outputted from the WBL binarization circuit with referring to the waveform generated by the waveform shaping circuit; and a PLL (Phase Locked Loop) circuit that is connected to the phase control circuit, for generating a sync clock on the basis of the phase controlled data, and the address detection circuit and said waveform shaping circuit being digitally configured. Therefore, the apparatus can be constructed in a smaller circuit scale with relative to the conventional apparatus, whereby the power consumption can be suppressed. Further, detection and correction of the phase shift can be performed properly, thereby improving the quality of signal processing.  
           [0007]    According to a 2nd aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the waveform shaping circuit includes a BPF (Band Pass Filter) as a digital filter, and the digital filter is constituted by an IIR (Infinity Impulse Response) digital filter having a reset function of initializing the digital filter when the digital filter characteristics are divergent. Therefore, even when the output value of the digital filter diverges, the digital filter can be initialized, thereby to stabilize the system.  
           [0008]    According to a 3rd aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the address detection circuit includes a LPF (Low Pass Filter) as a digital filter, and the digital filter is constituted by an IIR digital filter having a reset function of initializing the digital filter when the digital filter characteristics are divergent.  
           [0009]    According to a 4th aspect of the present invention, in the wobble signal processing apparatus of the 2nd or 3rd aspect, the digital filter calculates an optimum tap coefficient value, stores the optimum tap coefficient value in a storage unit that is externally provided, and performs following filtering utilizing the optimum tap coefficient value stored in the storage unit. Therefore, it is unnecessary to calculate the optimum tap coefficient value at each time, whereby the operation time can be reduced and the filtering can be performed effectively.  
           [0010]    According to a 5th aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the address detection circuit comprises: a digital filter for filtering the output from the ADC; and a PRML (Partial Response Maximum Likelihood) circuit for correcting errors in the signal outputted from the digital filter, and detecting the ADIP signal using the corrected signal. Therefore, even when any problem arises for some reason such as noises or phase delay, the ADIP signal can be accurately detected.  
           [0011]    According to a 6th aspect of the present invention, in the wobble signal processing apparatus of the 5th aspect, a PRML system that is implemented by the PRML circuit is a PR(a,b) system.  
           [0012]    According to a 7th aspect of the present invention, in the wobble signal processing apparatus of the 6th aspect, parameter values in the PR(a,b) system have a relationship of a=b.  
           [0013]    According to an 8th aspect of the present invention, in the wobble signal processing apparatus of the 5th aspect, the PRML circuit switches a sampling method between a peak sampling method and an offset sampling method.  
           [0014]    According to a 9th aspect of the present invention, in the wobble signal processing apparatus of the 8th aspect, the PRML circuit performs the sampling in a cycle of 8 T.  
           [0015]    According to a 10th aspect of the present invention, in the wobble signal processing apparatus of the 5th aspect, the PRML circuit performs a standardized Euclidean distance algorithm in a computing circuit of a Viterbi decoder by the PRML system.  
           [0016]    According to an 11th aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the address detection circuit comprises: a first digital filter for filtering the output from the ADC; a phase control circuit for controlling the phase of the wobble binary signal outputted from the WBL binarization circuit with referring to the signal outputted from the first digital filter, and outputting a phase controlled signal; a multiplier for multiplying the signal outputted from the first digital filter by the phase controlled signal; a second digital filter for filtering an output from the multiplier; an edge smoothing circuit for binarizing the signal outputted from the first digital filter, and smoothing edges of the binarized signal, thereby generating a clock for outputting the ADIP signal; and a binarization circuit for binarizing the signal outputted from the second digital filter in accordance with the clock that is outputted from the edge smoothing circuit, and outputting the ADIP signal.  
           [0017]    According to a 12th aspect of the present invention, in the wobble signal processing apparatus of the 1st or 11th aspect, the phase control circuit obtains a phase difference between the wobble binary signal and the wobble signal that has passed through the digital filter, and controls the phase by delaying the wobble binary signal.  
           [0018]    According to a 13th aspect of the present invention, in the wobble signal processing apparatus of the 12th aspect, the phase control circuit corrects a phase shift by performing counter processing to clock delay information previously obtained.  
           [0019]    According to a 14th aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the address detection circuit comprises: a digital filter for filtering the output from the ADC; and a DSV (Digital Sum Value) calculator for digitally processing the output from the digital filter by dividing the same with a predetermined threshold value, thereby detecting the ADIP signal.  
           [0020]    According to a 15th aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the address detection circuit comprises: a digital filter for filtering the output from the ADC; a binarization circuit for binarizing the output from the digital filter; and a counter circuit for counting the number of +1 and the number −1 in the signal outputted from the binarization circuit, and the ADIP signal is detected on the basis of the count values of the counter circuit.  
           [0021]    According to a 16th aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the ADC has a 7-bit resolution.  
           [0022]    According to a 17th aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the FEP further includes an AGC (Auto Gain Control) circuit for performing automatic amplitude control when the amplitude of the ADIP section is decreased or increased due to crosstalk in the optical disc medium. Thereby, the system can be operated with stability.  
           [0023]    According to an 18th aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, the pickup further includes an aperture ratio decision unit for deciding the degree of distortion of the waveform that is read from the optical disc medium, and controls the diameter of a beam spot of a pickup laser on the basis of the decided degree of distortion of the waveform, thereby controlling the degree of signal component extraction. Thereby, the system can be operated with stability.  
           [0024]    According to a 19th aspect of the present invention, in the wobble signal processing apparatus of the 1st aspect, this apparatus operates in accordance with the sync clock that is supplied from the PLL circuit, and the sync clock is adaptively changed according to an angular velocity of the disc. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    [0025]FIG. 1 is a block diagram illustrating a construction of a wobble signal processing apparatus according to a first embodiment of the present invention.  
         [0026]    [0026]FIG. 2 is a diagram illustrating a construction of a bilinear transformation LPF, which constitutes an address detection circuit according to the present invention.  
         [0027]    [0027]FIG. 3 is a diagram illustrating a construction of a backward difference LPF, which constitutes the address detection circuit according to the present invention.  
         [0028]    FIGS.  4 ( a ) to  4   d ) are waveform diagrams for explaining an ADIP signal detection process by the wobble signal processing apparatus according to the first embodiment.  
         [0029]    [0029]FIG. 5 is a diagram illustrating a construction of a BPF, which constitutes a waveform shaping circuit according to the present invention.  
         [0030]    [0030]FIG. 6 is a diagram illustrating a construction of a phase control circuit according to the present invention.  
         [0031]    [0031]FIG. 7 is a diagram illustrating a construction of a pickup according to the present invention.  
         [0032]    [0032]FIG. 8 is a block diagram illustrating a construction of a wobble signal processing apparatus according to a second embodiment of the present invention.  
         [0033]    FIGS.  9 ( a ) to  9 ( g ) are waveform diagrams for explaining an ADIP signal detection process by the wobble signal processing apparatus according to the second embodiment.  
         [0034]    [0034]FIG. 10 is a block diagram illustrating a construction of a wobble signal processing apparatus according to a third embodiment of the present invention.  
         [0035]    [0035]FIG. 11 is a block diagram illustrating another construction of the wobble signal processing apparatus according to the third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0036]    Hereinafter, embodiments of the present invention will be described with reference to the figures. The embodiments shown herein are exemplary only, and the invention is not limited to these embodiments.  
       Embodiment 1  
       [0037]    A wobble signal processing apparatus according to a first embodiment of the present invention will be described.  
         [0038]    [0038]FIG. 1 is a block diagram illustrating a construction of the wobble signal processing apparatus according to the first embodiment. In this figure, the wobble signal processing apparatus according to the first embodiment is constituted by a pickup  101 , a FEP (Front End Processor)  102 , an ADC (Analog-to-Digital Converter)  103 , an address detection circuit  104 , a WBL binarization circuit  105 , a waveform shaping circuit  106 , a phase control circuit  107 , and a PLL circuit  108 .  
         [0039]    The pickup  101  outputs a wobble signal (hereinafter, referred to as a WBL signal) read from a recording medium to the FEP  102 , a wobble binary signal (hereinafter, referred to as a WBL binary signal) to the WBL binarization circuit  105 , and a RF signal to the waveform shaping circuit  106 , respectively. The pickup  101  may include an aperture ratio decision unit  73  for deciding the degree of distortion of the waveform that is read from an optical disc medium  71 , as shown in FIG. 7. With the pickup  101  having the aperture ratio decision unit  73  shown in FIG. 7, when the output waveform is distorted and is hard to read, the spot diameter of a pickup laser  72  is adjusted in accordance with a control signal  74  that is outputted from the aperture ratio decision unit  73 , thereby adjusting the signal component extraction degree.  
         [0040]    The FEP  102  performs band limitation and gain control to the inputted WBL signal. It is assumed here that the FEP  102  includes an AGC (Auto Gain Control) that performs an automatic amplitude control when the amplitude of an ADIP (Address In Pre-Groove) section is decreased or increased due to crosstalk in the recording medium.  
         [0041]    The ADC  103  converts the analog signal outputted from the FEP  102  to a digital signal. It is assumed here that the bit resolution is 7 bits.  
         [0042]    The address detection circuit  104  is constituted by a digital filter  109  and a PRML (Partial Response Maximum Likelihood) circuit  110 . This address detection circuit  104  receives the digital signal outputted from the ADC  103 , and processes the signal by a digital system to detect an ADIP signal. It is assumed here that the digital filter  109  is a LPF (Low pass filter) that implements an IIR (Infinity Impulse Response) digital system.  
         [0043]    The WBL binarization circuit  105  smoothes edges of the WBL binary signal outputted from the pickup  101 .  
         [0044]    The waveform shaping circuit  106  is constituted by a digital filter  111 . The circuit  106  receives the RF signal read by the pickup  101  and performs digital signal processing to generate a WBL binary signal waveform. The digital filter  111  herein is a BPF (Band pass filter) that implements the IIR-digital system.  
         [0045]    The phase control circuit  107  controls the phase of the WBL binary signal outputted from the WBL binarization circuit  105  with referring to the waveform outputted from the waveform shaping circuit  106 , and outputs a phase control signal.  
         [0046]    The PLL (Phase Locked Loop) circuit  108  generates a sync clock on the basis of the phase control signal that is outputted from the phase control circuit  107 .  
         [0047]    Next, the operation of the wobble signal processing apparatus according to the first embodiment will be described. Here, the wobble signal processing apparatus according to the first embodiment operates in accordance with the sync clock that is inputted from the PLL circuit  108  to the respective circuits, and the sync clock is adaptively changed according to the angular velocity of the disc. Clocks such as WBLPLLOK, WCLK, CLKTCH, CLKSYS are employed as the sync clock.  
         [0048]    Initially, an ADIP signal detection process by the FEP  102 , the ADC  103 , and the address detection circuit  104  in the wobble signal processing apparatus according to the first embodiment will be described.  
         [0049]    When the FEP  102  receives a WBL signal inputted from the pickup  101 , the FEP  102  performs band limitation and gain control to the inputted WBL signal, and outputs the resultant signal to the ADC  103 . When the amplitude of an ADIP (Address In Pre-Groove) section is decreased or increased due to crosstalk in the recording medium, the AGC in the FEP  102  performs an automatic amplitude control to realize stable signal outputting.  
         [0050]    When the ADC  103  receives the WBL signal outputted from the FEP  103 , the ADC  103  converts the analog WBL signal to a digital signal.  
         [0051]    The WBL signal that has been converted in the digital signal by the ADC  103  is inputted to the address detection circuit  104 , and then the address detection circuit  104  performs digital signal processing to detect an ADIP signal.  
         [0052]    Hereinafter, the operation of the address detection circuit  104  will be described in more detail.  
         [0053]    Initially, the digital filter  109  of the address detection circuit  104  will be described with reference to FIGS. 2 and 3. The digital filter shown in FIGS. 2 and 3 is a LPF that implements the IIR digital system. FIGS. 2 and 3 each show an example of the construction of the digital filter  109  according to the first embodiment. When the digital filter  109  is to be mounted, either of the digital filters shown in FIGS. 2 and 3 may be employed to construct the digital filter  109 .  
         [0054]    [0054]FIG. 2 is a diagram illustrating a construction of the digital filter as a component of the address detection circuit according to the present invention.  
         [0055]    The IIR digital LPF as shown in FIG. 2 comprises coefficient units (multipliers)  21 , adders  22 , a subtractor  23 , and registers  24 . The LPF is constituted by multiplication between input data and a tap coefficient value, and it performs an arithmetic operation according to a bilinear transformation method. Here, the tap coefficient in the digital filter  109  is automatically calculated, for example, by optimization based on a LMS method (least mean square method). When the automatically calculated tap coefficient is stored in a storage unit that is externally provided and the following filtering is performed utilizing the tap coefficient that is stored in the storage unit, there is no need to calculate the optimum tap coefficient each time, whereby the operation time can be reduced and the filtering can be performed efficiently.  
         [0056]    In this figure, X n  denotes an input signal and Y n  denotes an output signal. When the input signal is X n  and the output signal is Y n , the transfer function H(s) and the output signal Y n  are represented by [Formula 1].  
                 H        (   s   )       =       ω     0   2           s   2     +         ω   0     Q        s     +     ω     0   2                  
          (         where                     ω   0     Q       =       2      π                   f   c         q   1         ,     S   =       2   T     ×       1   -   D       1   +   D             )          
            Y   n     =       1   c          {           ω   0     2          X   n       +     2          ω   0     2          X     n   -   1         +         ω   0     2          X     n   -   2         +     BY     n   -   1       -     AY     n   -   2         }              
          (         where                 A     =       4     T   2       -       2        ω   o           q   1        T       +     ω     0   2           ,     B   =       8     T   2       -     2        ω     0   2             ,     
          C   =       4     T   2       +       2        ω   0           q   1        T       +     ω     0   2           ,       ω   0     =     2      π                   f   c           )             [     Formula                 1     ]                               
 
         [0057]    where f c  is the cutoff frequency, q l  is the cutoff characteristics value, and T is the operation frequency (channel rate).  
         [0058]    Further, RST in the figure denotes a reset signal that is inputted to the digital filter  109  from outside, and this reset signal implements a reset function for initializing the digital filter  109 . This reset function is provided because the IIR filter has filtering characteristics that may be divergent, as shown in a reference document “Digital signal processing” (written by Shigeo Tsujii, SHOKODO, pp. 66-77). When the output value of the digital filter  109  diverges, the digital filter  109  is reset by the reset signal, thereby to stabilize the system.  
         [0059]    [0059]FIG. 3 is a diagram illustrating a construction of the digital filter as a component of the address detection circuit according to the present invention.  
         [0060]    The IIR digital LPF as shown in FIG. 3 comprises coefficient units (multipliers)  31 , an adder  32 , a subtractor  33 , and registers  34 . This LPF is constituted by multiplication between input data and a tap coefficient value, and performs an arithmetic operation according to a backward difference method. The tap coefficient value in the digital filter  109  is automatically calculated, for example, by the optimization based on the LMS method (least mean square method). When the automatically calculated tap coefficient is stored in a storage unit that is externally provided and the following filtering is performed utilizing the tap coefficient stored in the storage unit, there is no need to calculate the optimum tap coefficient each time, whereby the operation time can be reduced and the filtering can be performed efficiently.  
         [0061]    In FIG. 3, X n  denotes an input signal, and Y n  denotes an output signal. When the input signal is X n  and the output signal is Y n , the transfer function H(s) and the output signal Y n  is represented by the following [Formula 2].  
                 H        (   s   )       =         ω     0   2           S   2     +         ω   0     Q        S     +     ω     0   2                (         where                     ω   0     Q       =       2      π                   f   c         q   1         ,     S   =       1   -   D     T         )              
            Y   n     =         B   A          X   n       +       C   A          Y     n   -   1         -       1   A            Y     n   -   2            
     (         where                 A     =     1   +         ω   0        T       q   1       +         ω   0     2          T   2           ,     B   =         ω   0     2          T   2         ,     C   =     2   +       ω     0   T         q   1           ,       ω   0     =     2      π                   f   c           )                   [     Formula                 2     ]                               
 
         [0062]    where f c  is the cutoff frequency, q 1  is the cutoff characteristics value, and T is the operation frequency (channel rate).  
         [0063]    Further, similarly in FIG. 2, RST in FIG. 3 denotes a reset signal that is inputted to the digital filter  109  from outside, and this reset signal implements a reset function for initializing the digital filter  109 . The reset function is provided because the IIR filter has filtering characteristics that may be divergent, as shown in the reference document “Digital signal processing” (written by Shigeo Tsujii, SHOKODO). When the output value of the digital filter diverges, the digital filter  109  can be initialized by the reset signal, thereby to stabilize the system.  
         [0064]    Next, the PRML circuit  110  as a component of the address detection circuit  104  will be described, with reference to FIG. 4.  
         [0065]    [0065]FIG. 4 are waveform diagrams for explaining the ADIP detection process in the wobble signal processing apparatus according to the first embodiment. FIG. 4( a ) shows a WBL signal that is inputted to the digital filter  109 . FIG. 4( b ) shows a signal outputted from the digital filter  109 . FIG. 4( c ) shows offset samples that are obtained by offset sampling by the PRML circuit  110 . FIG. 4( d ) shows peak samples that are obtained by peak sampling by the PRML circuit  110 .  
         [0066]    The PRML circuit  110  corrects errors in the output signal from the digital filter  109 , and detects an ADIP signal using the corrected signal. As shown in figures, smoothing of phase demodulation points and noise removal is performed by the digital filter  109 , and the signal outputted from the digital filter  109  is sampled in a cycle of 8 T, so as to be matched with the PR(1,1) system. In this case, the sampling method is switched between the peak sampling method and the offset sampling method.  
         [0067]    Then, the sample points that are sampled so as to be matched with the PR(1,1) system are decoded by a Viterbi decoder to perform error correction. Even when any problem arises for some reason as noises or phase delay, this error correction implements an accurate ADIP detection. In the ADIP detection process, 4 T consecutive sample points among the corrected values are considered as an ADIP section.  
         [0068]    The PRML circuit  110  in the wobble signal processing apparatus according to the first embodiment samples data in the cycle of 8 T, to perform the error correction by the PR(1,1) system. However, when the PR coefficient is properly set, like in a case where the error correction is performed by a PR(a,b) system in which the relationship between “a” and “b” is a=b, the above-mentioned effect can be obtained.  
         [0069]    Next, the clock generation process by the WBL binarization circuit  105 , the waveform shaping circuit  106 , the phase control circuit  107 , and the PLL circuit  108  in the wobble signal processing apparatus according to the first embodiment will be described.  
         [0070]    The WBL binarization circuit  105  smoothes edges of the WBL binary signal that is outputted from the pickup  101 , and outputs the smoothed signal to the phase control circuit  107 . The digital filter  111  that constitutes the waveform shaping circuit  106  receives a RF signal that is read by the pickup  101 , then digitally processes the input signal to generate a WBL binary signal waveform, and outputs the obtained waveform to the phase control circuit  107 .  
         [0071]    Then, the smoothed WBL binary signal outputted from the WBL binarization circuit  105  and the WBL binary signal waveform outputted from the waveform shaping circuit  106  are inputted to the phase control circuit  107 . The phase control circuit  107  controls the phase of the WBL binary signal outputted from the WBL binarization circuit  105  with referring to the waveform outputted from the waveform shaping circuit  106 , and outputs the phase controlled signal to the PLL circuit  108 .  
         [0072]    The PLL circuit  108  receives the phase controlled signal outputted from the phase control circuit  107 , and generates a sync clock that is synchronized with this phase controlled signal.  
         [0073]    Hereinafter, the construction of the digital filter  111  that constitutes the waveform shaping circuit  106  will be described in more detail with reference to FIG. 5.  
         [0074]    [0074]FIG. 5 is a diagram illustrating a construction of the digital filter that constitutes the waveform shaping circuit according to the present invention.  
         [0075]    The BPF that implements the IIR digital system as shown in FIG. 5 comprises coefficient units (multipliers)  51 , adders  52 , a subtractor  53 , and registers  54 . The BPF is constituted by multiplication between input data and a tap coefficient value, and it performs an arithmetic operation by the bilinear transformation method. The tap coefficient in this digital filter  109  is automatically calculated, for example, by optimization according to the LMS method (least mean square method). When the automatically calculated tap coefficient is stored in a storage unit that is externally provided and the following filtering is performed utilizing the tap coefficient stored in the storage unit, there is no need to calculate the optimum tap coefficient each time, whereby the operation time can be reduced and the filtering can be performed effectively.  
         [0076]    In this figure, X n  denotes an input signal and Y n  denotes an output signal. When the input signal is X n  and the output signal is Y n , the transfer function H(s) and the output signal Y n  are represented by following [Formula 3].  
                 H        (   s   )       =           ω   0     Q        S         S   2     +         ω   0     Q        S     +     ω     0   2                  
          (         where                     ω   0     Q       =       2      π                   f   c         q   1         ,     S   =       2   T     ×       1   -   D       1   +   D             )          
            Y   n     =         B       A   2     +   B   +   C            X   n       -       B       A   2     +   B   +   C            X     n   -   2         -         2        (       A   2     -   C     )           A   2     +   B   +   C            Y     n   -   1         -           A   2     -   B   +   C         A   2     +   B   +   C              Y     n   -   2            
     (         where                 A     =     2      π                   f   c         ,     B   =       2      A         q   1        T         ,     C   =     4     T   2           )                   [     Formula                 3     ]                               
 
         [0077]    where f c  is the cutoff frequency, q 1  is the cutoff characteristics value, and T is the operation frequency (channel rate).  
         [0078]    Further, RST in FIG. 5 denotes a reset signal that is inputted to the digital filter  111  from outside, and this signal implements a reset function of initializing the digital filter  111 . This reset function is provided because the IIR filter has filtering characteristics that may be divergent, as shown in the reference document “Digital signal processing” (written by Shigeo Tsujii, SHOKODO). When the output value of the digital filter  111  diverges, the digital filter  111  is initialized by the reset signal, thereby to stabilize the system.  
         [0079]    Next, the construction of the phase control circuit  107  will be described in more detail with reference to FIG. 6.  
         [0080]    [0080]FIG. 6 is a diagram illustrating a construction of the phase control circuit according to the present invention.  
         [0081]    As shown in the figure, the smoothed WBL binary signal outputted from the WBL binarization circuit  105  and the WBL binary signal waveform outputted from the digital filter  111  are inputted to the phase control circuit  107 , as well as an error edge and a phase position error are supplied by arithmetic with a PC or the like, to the phase control circuit  107 .  
         [0082]    As the WBL binary signal outputted from the WBL binarization circuit  105  and the WBL binary signal waveform outputted from the digital filter  111  are not in phase, the phase control circuit  107  performs phase control. The phase control circuit  107  calculates a difference in phase between the WBL binary signal and the WBL signal that has passed through the digital filter, and controls the phase by delaying the WBL binary signal using registers. More specifically, initially a digital filter output edge counter  61  counts the number of edges, and the count value is compared with a comparison value that is previously set in the comparator  62 . When a predetermined condition is not met, the circuit is held by a hold counter  63 , while when the predetermined condition is met, data is outputted from a delay circuit  64  that consists of a predetermined number of register stages, thereby performing the phase control.  
         [0083]    The phase control circuit as shown in FIG. 6 controls the phase difference using the delay circuit  64 , while since the circuit is digitally configured, the phase difference can be corrected by executing the counter processing using clock delay information that has been previously obtained. When the counter process is executed in this way, the construction of the delay circuit  64  in the phase control circuit as shown in FIG. 6 can be simplified, whereby the circuit scale can be reduced.  
         [0084]    As described above, according to the wobble signal processing apparatus of the first embodiment, the address detection circuit is constituted by the digital filter and the PRML circuit, and the waveform shaping circuit is constituted by the digital filter, and further the ADIP signal detection process and the clock signal generation process are implemented by the digital system, whereby the circuit scale, the parameter variations, and the power consumption can be reduced, as well as the possibility of defective products that may occur at the manufacturing steps can be decreased.  
       Embodiment 2  
       [0085]    A wobble signal processing apparatus according to a second embodiment of the present invention will be described.  
         [0086]    [0086]FIG. 8 is a block diagram illustrating a construction of the wobble signal processing apparatus according to the second embodiment. In this figure, the wobble signal processing apparatus according to the second embodiment comprises a pickup  101 , a FEP  102 , an ADC  103 , an address detection circuit  201 , a WBL binarization circuit  105 , a waveform shaping circuit  106 , a phase control circuit  107 , and a PLL circuit  108 .  
         [0087]    The wobble signal processing apparatus of the second embodiment is different from the above-mentioned wobble signal processing apparatus of the first embodiment in the construction of the address detection circuit, and the same components as those in the wobble signal processing apparatus of the first embodiment are denoted by the same references.  
         [0088]    The address detection circuit  201  comprises a digital filter  109 , a phase control circuit  202 , a multiplier  203 , a LPF  204 , an edge smoothing circuit  205 , and a binarization circuit  206 . The digital filter  109  is a LPF that is the same as the digital filter  109  described in the first embodiment and implements the IIR digital system.  
         [0089]    The phase control circuit  202  controls the phase of the WBL binary signal outputted from the WBL binarization circuit  105  with referring to the waveform outputted from the digital filter  109 , and outputs a phase controlled signal.  
         [0090]    The multiplier  203  multiplies the output signal from the digital filter  109  by the phase controlled signal obtained by the phase control circuit  202 , and outputs the result of the multiplication to the LPF  204 .  
         [0091]    The LPF  204  is a LPF that has the same construction as the digital filter  109  and implements the IIR digital system, and it attenuates the signal outputted from the multiplier  203  by cutting off the signal that is higher than the cutoff frequency, and outputs the signal that is lower than the cutoff frequency to the binarization circuit  206 .  
         [0092]    The edge smoothing circuit  205  generates a clock for outputting an ADIP signal by smoothing edges of the signal that is obtained by binarizing the digital filter output. When the digital filter output is binarized, a phase delay corresponding to the digital filter output occurs, and there arise a need that the edge smoothing circuit  205  makes the delayed signal in phase with the edges that have been smoothed by the WBL binarization circuit  105 .  
         [0093]    The binarization circuit  206  binarizes the signal outputted from the LPF  204  in accordance with the clock outputted from the edge smoothing circuit  205 , and generates an ADIP signal.  
         [0094]    Next, the operation of the wobble signal processing apparatus according to the second embodiment will be described. The wobble signal processing apparatus of the second embodiment operates in accordance with a sync clock that is inputted from the PLL circuit  108  to the respective circuits, and the clock is adaptively changed according to the angular velocity of the disc. Here, clocks such as WBLPLLOK, WCLK, CLKTCH, CLKSYS are employed as the sync clock.  
         [0095]    Hereinafter, the ADIP detection process by the FEP  102 , the ADC  103 , and the address detection circuit  201  in the wobble signal processing apparatus according to the second embodiment will be described.  
         [0096]    [0096]FIG. 9 are waveform diagrams for explaining the ADIP signal detection process by the wobble signal processing apparatus according to the second embodiment.  
         [0097]    [0097]FIG. 9( a ) shows an example of a WBL signal that is read by the pickup  101 . This WBL signal is subjected to band limitation and gain control by the FEP  102 , converted into a digital signal by the ADC  103 , and then inputted to the digital filter  109 . This input signal is filtered by the digital filter  109 , and a digital filter output signal as shown in FIG. 9( c ) is outputted.  
         [0098]    The phase control circuit  202  controls the phase of the WBL binary signal (FIG. 9( b )) outputted from the binarization circuit  105  with referring to the digital filter output signal shown in FIG. 9( c ), and outputs a phase controlled signal to the multiplier  203 .  
         [0099]    Then, the multiplier  203  multiplies the digital filter output signal (FIG. 9( c )) outputted from the digital filter  109  by the phase controlled signal (FIG. 9( d )) outputted from the phase control circuit  202 , and outputs a multiplier output signal as shown in FIG. 9( e ) to the LPF  204 .  
         [0100]    The LPF  204  filters the multiplier output signal, and generates a LPF output signal as shown in FIG. 9( f ). The LPF output signal is inputted to the binarization circuit  206  and binarized so as to be in phase with the clock that is generated by the edge smoothing circuit  205 , resulting in an ADIP signal as shown in FIG. 9( g ).  
         [0101]    Here, the clock signal generation processing by the WBL binarization circuit  105 , the waveform shaping circuit  106 , the phase control circuit  107 , and the PLL circuit  108  of the wobble signal processing apparatus according to the second embodiment is the same as that in the wobble signal processing apparatus according to the first embodiment.  
         [0102]    As described above, according to the wobble signal processing apparatus of the second embodiment, the address detection circuit is constituted by the digital filter, the phase control circuit, the LPF, the edge smoothing circuit, and the binarization circuit, and the waveform shaping circuit is constituted by the digital filter, and further the ADIP signal detection process and the clock signal generation process are implemented a digital system. Therefore, the circuit scale, the parameter variations, and the power consumption can be reduced, as well as the possibility of defective products which may occur at the manufacturing steps can be decreased.  
         [0103]    Here, the wobble signal processing apparatus according to the second embodiment is provided with the phase control circuit  202  and the phase control circuit  107  separately as shown in FIG. 8. However, because the phase control circuit  202  has the same construction as that of the phase control circuit  107  described in the first embodiment, when the circuit is actually designed, the wobble signal processing apparatus according to the second embodiment can be implemented with one phase control circuit.  
       Embodiment 3  
       [0104]    A wobble signal processing apparatus according to a third embodiment of the present invention will be described.  
         [0105]    [0105]FIG. 10 is a block diagram illustrating a construction of a wobble signal processing apparatus according to the third embodiment of the present invention. In this figure, the wobble signal processing apparatus comprises a pickup  101 , a FEP  102 , an ADC  103 , an address detection circuit  301 , a WBL binarization circuit  105 , a waveform shaping circuit  106 , a phase control circuit  107 , and a PLL circuit  108 .  
         [0106]    The wobble signal processing apparatus according to the third embodiment is different from the wobble signal processing apparatus of the first embodiment in the construction of the address detection circuit, and the same components as those in the wobble signal processing apparatus of the first embodiment are denoted by the same references.  
         [0107]    The address detection circuit  301  is constituted by a digital filter  109  and a DSV (Digital Sum Value) calculator  302 . The digital filter  109  is an IIR digital LPF that is the same as the digital filter  109  which has been described in the first embodiment.  
         [0108]    The DSV calculator  302  digitally processes the output from the digital filter by dividing a rectangular wave with a threshold value, and detects an ADIP signal.  
         [0109]    Next, the operation of the wobble signal processing apparatus according to the third embodiment will be described. Here, the wobble signal processing apparatus of the third embodiment operates in accordance with a sync clock that is inputted from the PLL circuit  108  to the respective circuits. The clock is adaptively changed according to the angular velocity of the disc. Clocks such as WBLPLLOK, WCLK, CLKTCH, CLKSYS are employed as the sync clock.  
         [0110]    Hereinafter, an ADIP detection process in the wobble signal processing apparatus-according to the third embodiment will be described. The operations of the pickup  101 , the FEP  102 , and the ADC  103  are the same as those in the wobble signal processing apparatus according to the first or second embodiment.  
         [0111]    A WBL signal is converted into a digital signal by means of the pickup  101 , the FEP  102  and the ADC  103 , and the digital signal is inputted to the address detection circuit  301 . In the address detection circuit  301 , the signal is digitally processed and an ADIP signal is detected.  
         [0112]    Hereinafter, the operation of the address detection circuit  301  will be described in more detail.  
         [0113]    In the address detection circuit  301 , the inputted WBL signal is initially filtered by the digital filter  109 , and the output of the digital filter is inputted to the DSV calculator  302 .  
         [0114]    The DSV calculator  302  that has received the digital filter output digitally processes the output by dividing a rectangular wave of the digital filter output with a threshold value, and detects an ADIP signal. More specifically, the output of the digital filter  109  is converted into −1, 0, and +0, and the numbers of −1 and +1 are counted. When the count of +1 or the count of −1 reaches a predetermined threshold value, this is outputted as an ADIP signal.  
         [0115]    Here, the clock signal generation process by the WBL binarization circuit  105 , the waveform shaping circuit  106 , the phase control circuit  107 , and the PLL circuit  108  in the wobble signal processing apparatus according to the third embodiment is the same as that in the wobble signal processing apparatus according to the first embodiment.  
         [0116]    As described above, according to the wobble signal processing apparatus of the third embodiment, the address detection circuit is constituted by the digital filter and the DSV calculator, and the waveform shaping circuit is constituted by the digital filter, and further the ADIP signal detection process and the clock signal generation process are implemented digitally, whereby the circuit scale, the parameter variations, and the power consumption can be reduced, as well as the possibility of defective products that may occur at the manufacturing steps can be decreased.  
         [0117]    The wobble signal processing apparatus according to the third embodiment is provided with the DSV calculator  302 . However, the DSV calculator  302  can be replaced with a binarization circuit  402  and a counter circuit  403  as shown in FIG. 11. In this case, a binary signal that is outputted from the binarization circuit  402  is inputted to the counter circuit  403 , and the counter circuit  403  counts +1 or −1. When the count of +1 or −1 reaches a predetermined threshold value, this is outputted as an ADIP signal.