Abstract:
An on/off control circuit is provided that controls the application of power to a device. The effectiveness of the on/off control circuit is optimized with regard to cost, power consumption, component life, and utility. An R-C circuit is used to provide a time-delayed turn-on, and turn-off, of the device being controlled, accompanied by a latch that retains the on/off state and controls the coupling of a power source to the device being controlled. The latch is configured as a data flip-flop (DFF) with a clocking signal that is controlled by the time-delayed switch input. The flip-flop has an inverted output signal as its input, thereby providing a toggled on/off operation. The latch also includes an independent reset input, thereby allowing an independent turn-off operation by power management controllers within the device being controlled. In the quiescent state, the preferred embodiment consumes less than half a microWatt of power.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to the field of electronic circuits and devices, and in particular to a circuit and device that provides a low-power, low-cost, on/off control for power supplies within devices, with configurable delay characteristics.  
           [0003]    2. Description of Related Art  
           [0004]    Most switches that control the application of power within a device are mechanical contact switches that connect a battery or other power source to a power supply, such as a voltage regulated supply.  
           [0005]    Complex electronic devices, such as computers, include electronic on/off control switches, wherein the mechanical switch that a user operates provides an input to an electronic circuit, and this electronic circuit provides the connection between the power source and the device&#39;s power supply. In this manner, other control schemes can be used to provide on/off control, by providing other inputs to the electronic circuit. These on/off control circuits also often provide a delayed turn-off, which require the depression of the mechanical on/off switch for an extended duration before power is disconnected from the device, to avoid inadvertent power shut-offs which could cause the loss of data. Providing a delayed turn-off is a fairly simple design task, because while the device is turned on, power is available for running timer circuits, activating shutdown procedures, and so on.  
           [0006]    A common problem in portable, low-power, devices is the unintentional turn-on of the device, when the user inadvertently activates a mechanical switch, which can substantially shorten the useful battery life. The useful battery life can also be shortened by unintentionally leaving the device turned on after use. Another problem is the over-use, or over-frequent use, of the on/off switch, because the frequent application and removal of power causes undue stress on the components within the device, causing premature failure.  
           [0007]    Timing circuits, similar to those used in conventional on/off control circuits, can be used to provide a delayed turn-on of the device, to prevent unintentional activations, but such circuits require active components that will consume power, particularly during each unintentional activation. Also, the cost of conventional on/off control switches often precludes their use in low-cost devices, or low-profit-margin devices, such as cellular telephones.  
         BRIEF SUMMARY OF THE INVENTION  
         [0008]    It is an object of this invention to provide an on/off control circuit that reduces the likelihood of inadvertent turn-on of a device. It is a further object of this invention to provide an on/off control circuit that draws minimal current in the quiescent state. It is a further object of this invention to provide an on/off control circuit that is usable by other functional elements within the device being controlled. It is a further object of this invention to provide an on/off control circuit that minimizes the stress on components within the circuit, and within the device being controlled.  
           [0009]    These objects, and others, are achieved using a variety of techniques designed to optimize the effectiveness of an on/off control circuit. The effectiveness of the on/off control circuit is optimized with regard to cost, power consumption, component life, and utility. An R-C circuit is used to provide a time-delayed turn-on, and turn-off, of the device being controlled, accompanied by a latch that retains the on/off state and controls the coupling of a power source to the device being controlled. The latch is configured as a data flip-flop (DFF) with a clocking signal that is controlled by the time-delayed switch input. The flip-flop has an inverted output signal as its input, thereby providing a toggled on/off operation. The latch also includes an independent reset input, thereby allowing an independent turn-off operation by power management controllers within the device being controlled. In the quiescent state, the preferred embodiment consumes less than half a microWatt of power. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein:  
         [0011]    [0011]FIG. 1 illustrates an example block diagram of an on/off control circuit in accordance with this invention.  
         [0012]    [0012]FIG. 2 illustrates an example block diagram of an on/off control circuit with independent turn-off control in accordance with this invention.  
         [0013]    [0013]FIG. 3 illustrates an example block diagram of an on/off control circuit that includes interfaces for external switch controls in accordance with this invention.  
         [0014]    [0014]FIG. 4 illustrates an example block diagram of a controlled device with an on/off control circuit in accordance with this invention. 
     
    
       [0015]    Throughout the drawings, the same reference numerals and symbols indicate similar or corresponding features or functions.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    [0016]FIG. 1 illustrates an example block diagram of an on/off control circuit  100  in accordance with this invention. The circuit  100  is configured to control a switch Q 3  that couples a power source Vbat to a device being controlled (not shown), via the illustrated Power Out node. In a preferred embodiment, an R-C filter R 5 -C 1  filters transients on the power source Vbat from affecting the circuit  100 , although the circuit  100  may be powered directly from Vbat.  
         [0017]    The initial condition of the circuit  100  is as follows. The resistor-capacitor combination of R 7 -C 3  causes the data flip-flop (DFF) U 2  to initialize to a clear, or reset, state, wherein the Q output is asserted to a logic-low level. The logic-low Q output drives the inverter U 1 B to a logic high state, which turns off the switch Q 3  by bringing it to a non-conductive state, thereby decoupling Vbat from the Power Out node.  
         [0018]    A push-button switch S 1  controls the turn-on, turn-off, operation of the circuit  100 , as follows. In a quiescent state, when switch S 1  is in the open state, the capacitor C 1  is charged to a voltage level equal to Vbat, via resistors R 5  and R 6 . This voltage on C 1  drives the output of the inverter U 1 A to a logic low state.  
         [0019]    The data input to the DFF U 2  is the inversion of its output Q, via the inverter U 1 B. This data input will be clocked to the output Q on a low-to-high transition of the output of the inverter U 1 A, causing the output Q to change state (toggle) with each low-to-high transition.  
         [0020]    When the switch S 1  is closed, the capacitor C 1  discharges through resistor R 9  toward a voltage level of Vbat*(R 9 /(R 9 +R 5 +R 6 ). The speed of discharge is determined by the RC time constant R 9 *C 1 . When the capacitor C 1  discharges to the lower trigger level of the inverter U 1 A, the output of the inverter U 1 A is driven high, causing a low-to-high transition on the clock input of the DFF U 2 . As illustrated, the inverter U 1 A is preferably a Schmitt trigger device, to prevent multiple transients as the input voltage transitions through the lower trigger level, and to provide a “re-enabling” delay to prevent over-frequent transitions, as discussed further below. To effect the transition, the aforementioned voltage level Vbat*(R 9 /(R 9 +R 5 +R 6 ) must be below the lower trigger level of the inverter U 1 A. The low-to-high transition on the clock input to the DFF U 2  causes the output Q to rise to a logic-high level, which causes the inverter U 1 B to be driven low, causing the switch Q 3  to conduct, thereby coupling Vbat to the Power Out node.  
         [0021]    Note that if the switch S 1  is released prior to the low-to-high transition on the clock input to the DFF U 2 , the capacitor C 1  begins to recharge to the Vbat level, via the resistors R 5 -R 6 . Thus, inadvertent short-duration closures of switch S 1  will not cause the circuit  100  to turn-on the controlled device, because the switch Q 3  will remain in the non-conducting state. In accordance with this invention, the switch S 1  must be closed for a duration that is proportional to the RC time constant R 9 *C 1 . The actual turn-on duration is determined by the trigger level of the device U 1 A, the ratio of R 9 /(R 9 +R 5 +R 6 ), and the capacitance C 1 , as in known in the art. Using a conventional Schmitt trigger having a lower trigger level of ½ the supply voltage, a delay of up to five seconds is achievable by using a capacitance C 1  of five microfarads, and a one megohm resistor R 9 . Note also that a re-closure of the switch S 1  will continue the discharge of C 1 , from whatever recharged voltage level the capacitor C 1  has reached. Thus, assuming that the time delay provided by (R 5 +R 6 )*C 1  is relatively long, an intermittent release of switch S 1  will not cause a ‘restart’ of the timing delay.  
         [0022]    In one preferred embodiment, the components that are contained within the dashed box that is identified as circuit  100  are encapsulated in a 5-pin module that can be used in a variety of applications. By encapsulating the circuit  100  as shown, a designer of the device that is being controlled merely selects a value of the capacitor C 1  to determine the on/off delay time, and provides a switch Q 3  suitable for the expected current draw of the device being controlled.  
         [0023]    When the switch S 1  is released, the capacitor C 1  again charges toward Vbat. When it transitions above the upper trigger level of the inverter U 1 A, the output of the inverter U 1 A is again driven low. Note that only after the output of the inverter U 1 A is driven low can a low-to-high transition occur at the clock input of the DFF U 2 . Thus, until the output of the inverter U 1 A is driven low, repeated closures of the switch S 1  will have no effect on the state of the DFF U 2 , and therefore no effect on the current conduction state of the device Q 3 . When the inverter U 1 A is driven low, the DFF U 2  is re-enabled to provide a toggle of the device Q 3  when the switch S 1  is again closed. In this manner, the circuit  100  prevents over-frequent on/off state changes, thereby reducing the stress on components within the device being controlled. The time to reach the upper trigger level of the inverter U 1 A, is determined by the trigger level of the device U 1 A, and the values of R 5 , R 6 , and C 1 , as well as the discharge voltage level Vbat*(R 9 /(R 9 +R 5 +R 6 ), as is known in the art. Using a conventional Schmitt trigger device U 1 A, the re-enabling delay of the illustrated circuit configuration of FIG. 1 is about a second or two.  
         [0024]    After the DFF U 2  is re-enabled, a subsequent closure of the switch S 1  again starts the discharge of the capacitor C 1 . When the voltage on the capacitor C 1  reaches the lower trigger level of the inverter U 1 A, the DFF U 2  will toggle to its opposite state, thereby turning off the switch Q 3 . In this manner, closures of the switch S 1  for the aforementioned on/off delay period, after the aforementioned re-enabling period, will toggle the switch Q 3  from conducting, to non-conducting, to conducting, and so on.  
         [0025]    Note that the resistance R 9  is in series with the switch S 1 , and is typically at least a hundred kilohms. This high series resistance allows the use of a switch S 1  that has a relatively high contact resistance, thereby increasing the expected life, and reducing the expected cost, of the switch S 1 .  
         [0026]    [0026]FIGS. 2 and 3 illustrate example alternative embodiments, using the principles discussed above with regard to FIG. 1 for providing a controlled on/off delay and protection against over-frequent changes of state of the Power Out signal.  
         [0027]    [0027]FIG. 2 illustrates an example block diagram of an on/off control circuit  200  with independent turn-off control and other features in accordance with this invention. A switch Q 2  is provided for resetting the DFF U 2  to a clear (output Q low) state, independent of the status of the clock or data inputs to the DFF U 2 . This clear state drives the output of the inverter U 1 B to a logic-high state, thereby placing the switch Q 3  into a non-conducting state and decoupling the power source from the device being controlled. In a preferred embodiment, the switch Q 2  is typically controlled by a power-management function within the device being controlled. In this manner, an automatic shut-off function can be provided to prevent battery discharge while the device is not being actively used. The switch Q 2 , or another switch in parallel to switch Q 2  may also be provided as a ‘reset’ button for forcing the on/off control circuit  100  to a known power-off state. The values of R 4  and C 3  are not critical to this design. Capacitor C 3  is provided to prevent unwanted resets of the DFF U 2  by noise signals, and resistor R 4  is provided to minimize the current draw when the device Q 2  conducts, and to provide an R-C time delay, with capacitor C 3 , for this turn-off control. This R-C time delay facilitates, for example, coupling the input of the device Q 2  to a voltage fault monitor, to disconnect the device if a low voltage is detected for a predefined duration corresponding to the R-C time delay.  
         [0028]    Also illustrated in FIG. 2 is a diode-resistor combination D 1 -R 8  that provides for providing different turn-on and turn-off delays for the switch S 1 . When the DFF U 2  is in the off-state (switch Q 3  non-conducting), the output Q is low. When switch S 1  is closed while the DFF U 2  is in the off-state, the diode D 1  will be placed in the forward conduction state, because of the voltage on capacitor C 1 , and the resistor R 8  will be placed in parallel to the discharge resistor R 9 . When the DFF U 2  is in the on-state, the output Q is high, and a closure of the switch S 1  will not place the diode D 1  in the forward conduction state, and the resistor R 8  will not be placed in parallel to the discharge resistor R 9 . Therefore, the turn-on delay will be dependent upon the parallel resistance of resistors R 8  and R 9 , while the turn-off delay will be dependent upon the resistor R 9 , and not R 8 . In this manner, different turn-on and turn-off delays can be accommodated. Note that if a longer turn-on time than turn-off time is desired, the orientation of the diode D 1  is reversed.  
         [0029]    [0029]FIG. 3 illustrates an example block diagram of an on/off control circuit  300  that includes additional interfaces for external switch controls in accordance with this invention. A switch Q 1  is provided in parallel to the switch S 1  and resistor R 9  discharge path, to allow for electronic control of the switch Q 3 , via the control circuit  300 . The value of the resistor R 2  will determine the on/off delay time via the switch Q 1 , in the same manner that the resistor R 9  determines the delay times for switch S 1 , discussed above.  
         [0030]    Also illustrated in FIG. 3 are available output signals Qout and its inverse Qoutb, as well as key status signal KB 0 , KB 1 . The outputs Qout and Qoutb provide the current on/off status of the circuit  100 , and the key status signals KB 0  and KB 1  provide the current status of the switch S 1 , via a selector switch U 3 . Preferably, the select input S to the switch U 3  is high impedance, so as not to affect the discharge time constant provided by resistor R 9 . These outputs are provided for use by the device being controlled, as illustrated in FIG. 4.  
         [0031]    [0031]FIG. 4 illustrates an example block diagram of a controlled device  400  with an on/off control circuit  300  in accordance with this invention. The controlled device  400  may be, for example, a cellular telephone device that is configured for optimal on/off control performance.  
         [0032]    The on/off control circuit  300  controls the coupling between a battery  410  and a multi-function regulated power supply  420  that distributes power to a variety of functional blocks  430  within the device. For example, in the cellular telephone example, separate regulated voltages are provided for: General Purpose Input/Output, Digital Signal Processing, Analog; and RF module functions. In a PDA device, separate controlled voltages may be provided to the processor, the display, and the memory, to efficiently manage the power utilization.  
         [0033]    To minimize unnecessary power consumption, the device  400  includes a control block  440  that provide for automated turn-on or turn-off of the device, via the on/off and off control input signals to the on/off control circuit  300 . The automated turn-on allows, for example, a periodic turn-on of the device, to periodically check for messages. To provide an automated turn-on, however, the device  440  will draw power from the battery  410  directly, as illustrated by the dashed line between the battery  410  and the device  440 . Automated turn-off can be provided without this direct connection to the battery  410 , because the on/off control device will be in the on state, and power will be provided to the device via the Power Out connection to the device&#39;s power supply  420 . The independent off control of the on/off control  300  is typically connected to a watch-dog-timer function in the control block  440 , to automatically disconnect the power from the device if the device enters a ‘hung’ or ‘crashed’ state. The watch-dog-timer is configured to be automatically reset periodically during the normal operation of the device, and times-out only if the normal operation is affected, and the automatic reset does not occur. Alternatively, the off-control may be connected to a not-easy-to-accidentally-access switch that can be activated manually to force a shutdown of the device.  
         [0034]    Other functional blocks  450 ,  460  may be configured to operate in dependence upon the state of the on/off control  300 , or the state of the switch S 1 . For example, a warning message may be provided when the switch S 1  is depressed to turn the device off; or, an indicator light may be included to provide visual feedback when the switch S 1  is activated, before the device is turned on. Additionally, the switch S 1  can be configured to provide multiple functions, wherein via the keyboard matrix  460 , a depression and release of the switch S 1  in less than the turn-off duration is interpreted as a particular other signal, such as a momentary-break function that activates an illumination of a display, and so on.  
         [0035]    The foregoing merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are thus within its spirit and scope. For example, although the example circuit of FIGS.  1 - 3  are illustrated as DC control circuits, the use of a Triac device as the switch Q 3  will permit the switching of an AC load, as well. Both bipolar and MOSFET technologies may be used for providing the power switch Q 3 . Other switching devices, such as solenoids and relays may also be used as the switch Q 3 , although such devices may not be suitable for low-cost, low-power applications. Also note that the voltage being switched by the switch Q 3  need not be the same voltage source that provides the Vbat supply voltage to the circuit  100 . Thus, for example, a small button battery can be provided as the source of Vbat, and a larger capacity voltage source can be the voltage that is coupled and decoupled to the device being controlled, via the switch Q 3 . Also, alternative configurations than those illustrated may be employed. For example, the switch S 1  and resistor R 9  (and likewise switch Q 1  and resistor R 2 ) may be configured to charge the capacitor C 1 , rather than discharge it. These and other system configuration and optimization features will be evident to one of ordinary skill in the art in view of this disclosure, and are included within the scope of the following claims.