Abstract:
A semiconductor device, includes: a field-effect transistor that configures a charge-pump circuit; and a supporting substrate that supports the field-effect transistor so that the field-effect transistor provided on the supporting substrate becomes warpable in a channel direction.

Description:
[0001]     Applicant hereby claims priority from JP 2005-081152 filed on Mar. 22, 2005, which is hereby incorporated by reference in its entirety.  
       BACKGROUND  
       [0002]     1. Technical Field  
         [0003]     The present invention relates to a semiconductor device and a booster circuit. In particular, the invention relates to a device that is applied to a method for improving the mobility of transistors used in a charge-pump circuit.  
         [0004]     2. Related Art  
         [0005]     Along with the progress of semiconductor manufacturing process in recent years, the denser integration and more function multiplication of semiconductor integrated circuits have been being accelerated, and the power supply voltage inside a semiconductor integrated circuit has been becoming lower. In addition, accompanied by the more function multiplication of semiconductor integrated circuits, the embedding of various power supplies, including high-voltage power supplies, has also been increasing. For example, non-volatile memories such as flash memories, EEPROMs, etc. and driver ICs of indicating elements such as liquid crystal, etc. require a high voltage of 10 V or more. Therefore, as a booster circuit for generating such a high voltage, a charge-pump method that enables an easy embedding into semiconductor integrated circuits has been employed in place of a switching regulator method using coils, etc. As such a charge-pump method, Dickson charge-pump circuits are generally used, as disclosed in an example of related art: JP-A-2004-328901.  
         [0006]     In the above charge-pump circuit, however, the substrate terminals of transistors need to be grounded for the purpose of latchup prevention. Therefore, transistors configuring a charge-pump circuit need to have a high breakdown voltage. Since such a configuration raises the internal impedance of a charge-pump circuit, there has been a problem of the degradation of conversion efficiency.  
       SUMMARY  
       [0007]     An advantage of the invention is to provide a semiconductor device and a booster circuit that can improve the conversion efficiency at the time of voltage boosting, while maintaining a high breakdown voltage of transistors.  
         [0008]     According to a first embodiment of the invention, a semiconductor device includes: a field-effect transistor that configures a charge-pump circuit; and a supporting substrate that supports the field-effect transistor so that the field-effect transistor provided on the supporting substrate becomes warpable in the channel direction.  
         [0009]     With the above semiconductor device, a stress can be applied to the channel region of a field-effect transistor so as to warp the channel region of the field-effect transistor. Therefore, the mobility of a field-effect transistor can be improved and the transconductance of a field-effect transistor can also be increased, which makes it possible to reduce the internal impedance of a charge-pump circuit even in the case of using a high-breakdown-voltage transistor for the purpose of latchup prevention. As a result, the conversion efficiency at the time of voltage boosting can be improved and therefore various power supplies, including high-breakdown-voltage power supplies, can be embedded into semiconductor integrated circuits, while lowering the level of power supply voltage inside semiconductor integrated circuits.  
         [0010]     Further, in the semiconductor device according to the first embodiment of the invention, it is preferable that the field-effect transistor includes: a semiconductor layer that is formed on the supporting substrate; a well that is formed on the semiconductor layer; a gate electrode that is provided on the well; a source layer that is provided on one side of the gate electrode and formed on the well; a drain layer that is provided on the other side of the gate electrode and formed on the well; and a backgate contact that is provided on the well and couples the well to the source layer.  
         [0011]     With the above configuration, the well potential can be brought into accordance with the source potential, leading to an effective latchup prevention even in the case where N-channel field-effect transistors and P-channel field-effect transistors coexist on the same substrate.  
         [0012]     Further, according to a second embodiment of the invention, a booster circuit includes: a first N-channel field-effect transistor, wherein a first pulse is inputted to a gate; a first P-channel field-effect transistor that is serially coupled to the first N-channel field-effect transistor, wherein the first pulse is inputted to a gate; a second N-channel field-effect transistor, wherein a gate is coupled to a drain of the first N-channel field-effect transistor; a second P-channel field-effect transistor that is serially coupled to the second N-channel field-effect transistor; a third N-channel field-effect transistor, wherein a second pulse, which has the opposite phase to the first pulse, is inputted to a gate and a source is coupled to a drain of the second N-channel field-effect transistor; a third P-channel field-effect transistor that is serially coupled to the third N-channel field-effect transistor, wherein a source is coupled to a source of the second N-channel field-effect transistor and the second pulse is inputted to a gate; a fourth N-channel field-effect transistor wherein a gate is coupled to a drain of the third N-channel field-effect transistor and a source is coupled to a source of the second N-channel field-effect transistor; a fourth P-channel field-effect transistor that is serially coupled to the fourth N-channel field-effect transistor, wherein: a gate is coupled to a drain of the third P-channel field-effect transistor, a source is coupled to the source of the third P-channel field-effect transistor, and a drain is coupled to a source of the first P-channel field-effect transistor; a first capacitor that is coupled to the drain of the second N-channel field-effect transistor, whereto the first pulse is inputted; a second capacitor that is coupled to a drain of the fourth N-channel field-effect transistor, whereto the second pulse is inputted; and a supporting substrate, on which the first to fourth N-channel field-effect transistors; the first to fourth P-channel field-effect transistors; and the first and second capacitors are provided, that supports the first to fourth N-channel field-effect transistors and the first to fourth P-channel field-effect transistors so that each of the first to fourth N-channel field-effect transistors and the first to fourth P-channel field-effect transistors becomes warpable in the channel direction.  
         [0013]     With the above booster circuit, the channel region of a field-effect transistor that is used in a charge-pump circuit can be warped, which improves the mobility of the field-effect transistor. Therefore, the transconductance of the field-effect transistor can also be increased, which makes it possible to reduce the internal impedance of a charge-pump circuit even in the case of using a high-breakdown-voltage transistor for the purpose of latchup prevention. As a result, the conversion efficiency of a charge-pump circuit can be improved.  
         [0014]     Further, in the booster circuit according to the second embodiment of the invention, each of the first to fourth N-channel field-effect transistors includes: a semiconductor layer that is formed on the supporting substrate; a P-well that is formed on the semiconductor layer; a first gate electrode that is provided on the P-well; an N-type source layer that is provided on one side of the first gate electrode and formed on the P-well; an N-type drain layer that is provided on the other side of the first gate electrode and formed on the P-well; and a first backgate contact that is provided on the P-well and couples the P-well to the N-type source layer. Further, each of the first to fourth P-channel field-effect transistors includes: a semiconductor layer that is formed on the supporting substrate; an N-well that is formed on the semiconductor layer; a second gate electrode that is provided on the N-well; a P-type source layer that is provided on one side of the second gate electrode and formed on the N-well; a P-type drain layer that is provided on the other side of the second gate electrode and formed on the N-well; and a second backgate contact that is provided on the N-well and couples the N-well to the P-type source layer.  
         [0015]     With the above configuration, the well potential can be brought into accordance with the source potential, leading to an effective latchup prevention even in the case where N-channel field-effect transistors and P-channel field-effect transistors coexist on the same substrate.  
         [0016]     Furthermore, in the booster circuit according to the second embodiment of the invention, lower electrodes of the first and second capacitors are configured of a P-type impurity diffusion layer that configures the sources/drains of the first to fourth P-channel field-effect transistors; and upper electrodes of the first and second capacitors are configured of a polycrystalline silicon layer that configures the gates of the first to fourth P-channel field-effect transistors.  
         [0017]     With the above configuration, the first and second capacitors can be formed at a time in forming the first to fourth P-channel field-effect transistors, which makes it possible to configure a charge-pump circuit while controlling the complexity of manufacturing process. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.  
         [0019]      FIG. 1  is a circuit diagram showing an example configuration of a single section of a booster circuit to which a first embodiment of the invention is applied.  
         [0020]      FIG. 2  is a plan view showing a layout pattern of the booster circuit in  FIG. 1 .  
         [0021]      FIG. 3  is a cross section showing an example configuration of a field-effect transistor with a backgate terminal.  
         [0022]      FIGS. 4A  to  4 D are waveform diagrams showing the output waveforms of the booster circuit in  FIG. 1 .  
         [0023]      FIG. 5  is a diagram showing a method for warping a field-effect transistor according to a second embodiment of the invention. 
     
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0024]     Embodiments of a semiconductor device and a booster circuit according to the invention will now be described with reference to the accompanying drawings.  
         [0025]      FIG. 1  is a circuit diagram showing an example configuration of a booster circuit to which a first embodiment of the invention is applied.  
         [0026]     In  FIG. 1 , the source of an N-channel field-effect transistor M 1  is coupled to an LDVV terminal; and the source of a P-channel field-effect transistor M 2  is coupled to a VDDORP terminal. Further, the drain of the N-channel field-effect transistor M 1  and the drain of the P-channel field-effect transistor M 2  are coupled to a PHIA terminal. Furthermore, the gate of the N-channel field-effect transistor M 1  and the gate of the P-channel field-effect transistor M 2  are coupled to a PHI terminal. In the foregoing configuration, the substrate potential of the N-channel field-effect transistor M 1  is coupled to the source of the N-channel field-effect transistor M 1 ; and the substrate potential of the P-channel field-effect transistor M 2  is coupled to the source of the P-channel field-effect transistor M 2 .  
         [0027]     Also, the source of an N-channel field-effect transistor M 5  is coupled to an LDVV terminal; and the source of a P-channel field-effect transistor M 6  is coupled to a VDDO terminal. Further, the drain of the N-channel field-effect transistor M 5  and the drain of the P-channel field-effect transistor M 6  are coupled to a PHIARP terminal. Furthermore, the gate of the N-channel field-effect transistor M 5  and the gate of the P-channel field-effect transistor M 6  are coupled to a PHIRP terminal. In the foregoing configuration, the substrate potential of the N-channel field-effect transistor M 5  is coupled to the source of the N-channel field-effect transistor M 5 ; and the substrate potential of the P-channel field-effect transistor M 6  is coupled to the source of the P-channel field-effect transistor M 6 .  
         [0028]     Also, the sources of N-channel field-effect transistors M 3  and M 4  are coupled to an LDVV terminal; and the sources of P-channel field-effect transistors M 7  and M 8  are coupled to an HVDD terminal. Further, the drain of the N-channel field-effect transistor M 3  and the drain of the P-channel field-effect transistor M 7  are coupled to a VDDO terminal; and the drain of the N-channel field-effect transistor M 4  and the drain of the P-channel field-effect transistor M 8  are coupled to a VDDORP terminal. Furthermore, the gate of the N-channel field-effect transistor M 3  is coupled to a PHIA terminal; the gate of the N-channel field-effect transistor M 4  is coupled to a PHIARP terminal; the gate of the P-channel field-effect transistor M 7  is coupled to the VDDORP terminal; and the gate of the P-channel field-effect transistor M 8  is coupled to the VDDO terminal.  
         [0029]     In the above configuration, the substrate potential of the N-channel field-effect transistor M 3  is coupled to the source of the N-channel field-effect transistor M 3 ; the substrate potential of the N-channel field-effect transistor M 4  is coupled to the source of the N-channel field-effect transistor M 4 ; the substrate potential of the P-channel field-effect transistor M 7  is coupled to the source of the P-channel field-effect transistor M 7 ; and the substrate potential of the P-channel field-effect transistor M 8  is coupled to the source of the P-channel field-effect transistor M 8 .  
         [0030]     Further, the PHI terminal is coupled to the drain of the N-channel field-effect transistor M 3  via a capacitor C 1 ; and the PHIRP terminal is coupled to the drain of the N-channel field-effect transistor M 4  via a capacitor C 2 .  
         [0031]      FIG. 2  is a plan view showing a layout pattern of the booster circuit in  FIG. 1 .  
         [0032]     In  FIG. 2 , a semiconductor substrate has N-wells NW 2 ; NW 6 ; NW 7 ; NW 8 ; NW 11  and NW 12 , and P-wells PW 1 ; PW 3 ; PW 4  and PW 5 . Further, the N-channel field-effect transistors M 1 , M 3 , M 4  and M 5  in  FIG. 1  are respectively formed on the P-wells PW 1 , PW 3 , PW 4  and PW 5 ; the P-channel field-effect transistors M 2 , M 6 , M 7  and M 8  in  FIG. 1  are respectively formed on the N-wells NW 2 , NW 6 , NW 7  and NW 8 ; and the capacitors C 1  and C 2  in  FIG. 1  are respectively formed on the N-wells NW 11  and NW 12 .  
         [0033]     That is, on the P-well PW 1 , a gate electrode G 1  is provided, sandwiched by N-type impurity diffusion layers N 1  and N 1 ′ that are formed on the P-well PW 1 . Further, on the P-well PW 3 , a gate electrode G 3  is provided, sandwiched by N-type impurity diffusion layers N 3  and N 3 ′ that are formed on the P-well PW 3 . Furthermore, on the P-well PW 4 , a gate electrode G 4  is provided, sandwiched by N-type impurity diffusion layers N 4  and N 4 ′ that are formed on the P-well PW 4 . Furthermore, on the P-well PW 5 , a gate electrode G 5  is provided, sandwiched by N-type impurity diffusion layers N 5  and N 5 ′ that are formed on the P-well PW 5 .  
         [0034]     Also, on the N-well NW 2 , a gate electrode G 2  is provided, sandwiched by P-type impurity diffusion layers P 2  and P 2 ′ that are formed on the N-well NW 2 . Further, on the N-well NW 6 , a gate electrode G 6  is provided, sandwiched by P-type impurity diffusion layers P 6  and P 6 ′ that are formed on the N-well NW 6 . Furthermore, on the N-well NW 7 , a gate electrode G 7  is provided, sandwiched by P-type impurity diffusion layers P 7  and P 7 ′ that are formed on the N-well NW 7 . Furthermore, on the N-well NW 8 , a gate electrode G 8  is provided, sandwiched by P-type impurity diffusion layers P 8  and P 8 ′ that are formed on the N-well NW 8 .  
         [0035]     Further, on the N-well NW 11 , an upper electrode U 1  is provided with a P-type impurity diffusion layer L 1 , which is formed on the N-well NW 11 , opposing the upper electrode U 1 . Furthermore, on the N-well NW 12 , an upper electrode U 2  is provided with a P-type impurity diffusion layer L 2 , which is formed on the N-well NW 12 , opposing the upper electrode U 2 .  
         [0036]     In addition, N-type impurity diffusion layers B 2 , B 6 , B 7 , B 8 , B 11  and B 12  are formed on the respective periphery of the N-wells NW 2 , NW 6 , NW 7 , NW 8 , NW 11  and NW 12 . Further, P-type impurity diffusion layers B 1 , B 3 , B 4  and B 5  are formed on the respective periphery of the P-wells PW 1 , PW 3 , PW 4  and PW 5 .  
         [0037]     Besides, the N-type impurity diffusion layer N 1 , the P-type impurity diffusion layer P 2 ′, and the gate electrode G 3  are coupled to one another via a lower wiring layer H 1 . Further, the gate electrodes G 1  and G 2 , the P-type impurity diffusion layer L 1 , and the PHI terminal are coupled to one another via a lower wiring layer H 2 ; and the N-type impurity diffusion layer B 11  is coupled to the lower wiring layer H 2  via a backgate contact K 11 . Furthermore, the N-type impurity diffusion layer N 5 , the P-type impurity diffusion layer P 6 ′, and the gate electrode G 4  are coupled to one another via a lower wiring layer H 3 ; and the N-type impurity diffusion layer B 2  is coupled to the lower wiring layer H 3  via a backgate contact K 2 . Furthermore, the N-type impurity diffusion layer N 3 ′, the P-type impurity diffusion layer P 7 , the gate electrode G 8 , and the upper electrode U 1  are coupled to one another via a lower wiring layer H 4 . Furthermore, the gate electrodes G 5  and G 6 , the P-type impurity diffusion layer L 2 , and the PHIRP terminal are coupled to one another via a lower wiring layer H 5 ; and the N-type impurity diffusion layer B 12  is coupled to the lower wiring layer H 5  via a backgate contact K 12 . Furthermore, the P-type impurity diffusion layer P 6  is coupled to a lower wiring layer H 6 ; and the N-type impurity diffusion layer B 6  is coupled to the lower wiring layer H 6  via a backgate contact K 6 . Furthermore, the N-type impurity diffusion layer N 1 ′ is coupled to a lower wiring layer H 7 ; and the P-type impurity diffusion layer B 1  is coupled to the lower wiring layer H 7  via a backgate contact K 1 . Furthermore, the N-type impurity diffusion layer N 5 ′ is coupled to a lower wiring layer H 8 ; and the P-type impurity diffusion layer B 5  is coupled to the lower wiring layer H 8  via a backgate contact K 5 . Furthermore, the LVDD terminal is coupled to a lower wiring layer H 9 . Furthermore, the N-type impurity diffusion layer N 4  is coupled to a lower wiring layer H 10 ; and the P-type impurity diffusion layer B 4  is coupled to the lower wiring layer H 10  via a backgate contact K 4 . Further, the N-type impurity diffusion layer N 4 ′, the P-type impurity diffusion layer P 8 , the gate electrode G 7 , and the upper electrode U 2  are coupled to one another via a lower wiring layer H 11 . Furthermore, the P-type impurity diffusion layers P 7 ′ and P 8 ′ are coupled to each other via a lower wiring layer H 12 ; and the N-type impurity diffusion layers B 7  and B 8  are respectively coupled to the lower wiring layer H 12  via backgate contacts K 7  and K 8 . Further, the N-type impurity diffusion layer N 3  is coupled to a lower wiring layer H 13 ; and the P-type impurity diffusion layer B 3  is coupled to the lower wiring layer H 13  via a backgate contact K 3 .  
         [0038]     In addition, the lower wiring layers H 4  and H 6  are coupled to each other via an upper wiring layer H 21 . Further, the lower wiring layers H 3 , H 6  and H 11  are coupled to one another via an upper wiring layer H 22 . Furthermore, the lower wiring layers H 7 , H 8 , H 9 , H 10  and H 13  are coupled to one another via an upper wiring layer H 23 . Furthermore, the lower wiring layer H 12  and the HVDD terminal are coupled to each other via an upper wiring layer H 24 .  
         [0039]     In the above configuration, the N-channel field-effect transistors M 1 ; M 3 ; M 4  and M 5 , and the P-channel field-effect transistors M 2 ; M 6 ; M 7  and M 8  can be mounted on a supporting substrate so that the N-channel field-effect transistors M 1 ; M 3 ; M 4  and M 5 , and the P-channel field-effect transistors M 2 ; M 6 ; M 7  and M 8  can be warped in the channel direction.  
         [0040]     By employing the above configuration, a stress can be applied to the channel region of a field-effect transistor so as to warp the channel region of the field-effect transistor. Therefore, the mobility of a field-effect transistor can be improved and further the transconductance of a field-effect transistor can also be increased, which makes it possible to reduce the internal impedance of a charge-pump circuit even in the case of using a high-breakdown-voltage transistor for the purpose of latchup prevention. As a result, the conversion efficiency at the time of voltage boosting can be improved and therefore various power supplies, including high-voltage power supplies, can be embedded into semiconductor integrated circuits, while lowering the level of power supply voltage inside semiconductor integrated circuits.  
         [0041]     Further, by respectively coupling the N-type impurity diffusion layers B 2 , B 6 , B 7  and B 8  to the P-type impurity diffusion layers P 2 , P 6 , P 7 ′ and P 8 ′ via the backgate contacts K 2 , K 6 , K 7  and K 8 , while respectively coupling the P-type impurity diffusion layers B 1 , B 3 , B 4  and B 5  to the N-type impurity diffusion layers N 1 ′, N 3 , N 4  and N 5 ′ via the backgate contacts K 1 , K 3 , K 4  and K 5 , the well potential can be brought into accordance with the source potential. Therefore, even in the case where the N-channel field-effect transistors M 1 ; M 3 ; M 4  and M 5 , and the P-channel field-effect transistors M 2 ; M 6 ; M 7  and M 8  coexist on the same substrate, an effective latchup prevention can be applied.  
         [0042]     In addition, the lower wiring layers H 1  to H 13  and the upper wiring layers H 21  to H 24  can be configured of Al wire; the gate electrodes G 1  to G 8  and the upper electrodes U 1  and U 2  can be configured of polycrystalline silicon layer; and the P-type impurity diffusion layers L 1  and L 2  can be used as lower electrodes of the capacitors C 1  and C 2 .  
         [0043]     With the above configuration, the capacitors C 1  and C 2  can be formed at a time in forming the P-channel field-effect transistors M 2 , M 6 , M 7  and M 8 , which makes it possible to configure a charge-pump circuit while controlling the complexity of manufacturing process.  
         [0044]      FIG. 3  is a cross section showing an example configuration of a field-effect transistor with a backgate terminal. In addition, in  FIG. 3 , the N-channel field-effect transistor M 1  shown in  FIG. 2  is taken as an example.  
         [0045]     In  FIG. 3 , the N-well NW 1  is formed on a semiconductor substrate  21 . In addition, as the material of the semiconductor substrate  21 , Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, etc. can be used, for example. Further, on the N-well NW 1 , the gate electrode G 1  is formed via a gate insulation film  22 ; and side walls are formed on the sides of the gate electrode G 1 . Furthermore, on the P-well PW 1 , the N-type impurity diffusion layers N 1  and N 1 ′, which are provided on both sides of the gate electrode G 1 , are formed via an LDD layer. Furthermore, on the periphery of the N-well NW 1 , the P-type impurity diffusion layer B 1  is formed. Furthermore, on the gate electrode G 1 , an interlayer insulation film  24  is formed. On the interlayer insulation film  24 , the lower wiring layer H 1 , which is coupled to the N-type impurity diffusion layer N 1 , and the lower wiring layer H 7 , which couples the N-type impurity diffusion layer N 1 ′ to the P-type impurity diffusion layer B 1 , are formed.  
         [0046]      FIGS. 4A  to  4 D are waveform diagrams showing the output waveforms of the booster circuit in  FIG. 1 .  
         [0047]     In  FIG. 4 , a pulse signal having, for example, a duty ratio of 0.5 and an amplitude of 3 V is inputted to the PHI terminal; and another signal having the opposite phase to the signal that is inputted to the PHI terminal is inputted to the PHIRP terminal. Further, a pulse signal having, for example, a duty ratio of 0.5 and an amplitude of 3 V is inputted to the PHIA terminal; and another signal having the opposite phase to the signal that is inputted to the PHIA terminal is inputted to the PHIARP terminal. Furthermore, the LVDD terminal is rated at 3 V; and the HVDD terminal is rated at 6 V, for example. In addition, a charge of 3 V is stored in the capacitor C 2 ; and no charge is stored in the capacitor C 1 .  
         [0048]     When the PHI terminal is rated at 0 V, the N-channel field-effect transistor M 1  is turned off; and the P-channel field-effect transistor M 2  is turned on. Further, when the PHI terminal is rated at 0 V, the PHIRP terminal is rated at 3 V. Therefore, the potential of the capacitor C 2  is raised by 3 V to make the VDDORP terminal rated at 6 V. Furthermore, when the VDDORP terminal is rated at 6 V, the PHIA terminal is rated at 6 V because the P-channel field-effect transistor M 2  is on. Therefore, the N-channel field-effect transistor M 3  is turned on. Furthermore, when the N-channel field-effect transistor M 3  is turned on, the LVDD terminal is rated at 3 V and the PHI terminal is rated at 0 V. Therefore, the VDDO terminal is rated at 3 V and a charge of 3 V is stored in the capacitor C 1  with the application of the voltage of 3 V. Furthermore, when the VDDO terminal is rated at 3 V, the P-channel field-effect transistor M 8  is turned on to make the HVDD terminal rated at 6 V.  
         [0049]     Next, when the PHI terminal is rated at 3 V, the PHIRP terminal is rated at 0 V. Therefore, the N-channel field-effect transistor M 5  is turned off and the P-channel field-effect transistor M 6  is turned on. Further, when the PHIRP terminal is rated at 0 V, the PHI terminal is rated at 3 V. Therefore, the potential of the capacitor C 1  is raised by 3 V to make the VDDO terminal rated at 6 V. Furthermore, when the VDDO terminal is rated at 6 V, the PHIARP terminal is rated at 6 V because the P-channel field-effect transistor M 6  is on, which makes the N-channel field-effect transistor M 4  turned on. Furthermore, when the N-channel field-effect transistor M 4  is turned on, the LVDD terminal is rated at 3 V and the PHIRP terminal is rated at 0 V. Therefore, the VDDORP terminal is rated at 3 V and a charge of 3 V is stored in the capacitor C 2  with the application of the voltage of 3 V. Furthermore, when the VDDORP terminal is rated at 3 V, the P-channel field-effect transistor M 7  is turned on to make the HVDD terminal rated at 6 V.  
         [0050]     As a result, by inputting a pulse signal having an amplitude of 3 V to the booster circuit shown in  FIG. 1 , a voltage of 6 V can be derived. Further, by coupling N sets of the booster circuit shown in  FIG. 1 , the input voltage can be boosted by N times. Under the above circumstances, the conversion efficiency of a charge-pump circuit, which is approximately 60 to 70% in normal cases, can be improved up to 80% by using field-effect transistors as the N-channel field-effect transistors M 1 , M 3 , M 4  and M 5  and the P-channel field-effect transistors M 2 , M 6 , M 7  and M 8 . Therefore, a logic circuit and a booster circuit that are activated at a low voltage can be integrated in one chip, which makes it possible to incorporate a logic circuit into non-volatile memories such as EEPROMs, etc. and driver ICs of indicating elements such as liquid crystal, etc., which require a high voltage of 10 V or more. Thus, the denser integration and more function multiplication of semiconductor integrated circuits can be promoted.  
         [0051]      FIG. 5  is a diagram showing a method for warping a field-effect transistor according to a second embodiment of the invention.  
         [0052]     In  FIG. 5 , a field-effect transistor T has a gate electrode G, as well as a source layer S and a drain layer D, which sandwich the gate electrode G. Further, a source contact C 1  and a drain contact C 2  are respectively formed on the source layer S and the drain layer D. Furthermore, the field-effect transistor T is mounted on a film substrate F so that the channel direction of the field-effect transistor T accords with the warpage direction of the film substrate F.  
         [0053]     In the above configuration, by warping the film substrate F, the channel region of the field-effect transistor T can be warped, which improves the mobility of the field-effect transistor T. Therefore, the transconductance of the field-effect transistor T can also be increased, which makes it possible to reduce the internal impedance of a charge-pump circuit even in the case of using a high-breakdown-voltage transistor as the field-effect transistor T for the purpose of latchup prevention. As a result, the conversion efficiency at the time of voltage boosting can be improved.  
         [0054]     In addition, by using the film substrate F, on which the field-effect transistor T is mounted, as a label of a wine bottle, etc., the film substrate F can be kept warped, which enables the activation of the field-effect transistor T at a high transconductance.