Abstract:
An equalizer is provided. The equalizer comprises a frequency domain a minimum-mean square-error (MMSE) decision feedback equalization (DFE) block having a backward filter co-efficient (BFC) feature adapted to operate in a single carrier environment.

Description:
FIELD OF THE INVENTION  
       [0001]    The present invention relates generally to an application in a digital television system, more specifically the present invention relates to a novel equalizer for single carrier terrestrial digital television receiver. 
       BACKGROUND  
       [0002]    Single carrier terrestrial digital television (DTV) systems are deployed in the countries such as Unite States (ATSC or Advanced Television Systems Committee), China (DMB-T/H or Digital Multimedia Broadcasting Terrestrial/Handheld), Canada, and other countries. Note that the China DTV standard is partially single carrier. 
         [0003]    Single carrier DTV receiver is using DFE (Decision feedback equalizer) to combat the multipath interference introduced in the broadcast transmission of TV signals. Antenna Diversity has been successfully used in multi-carrier (i.e. OFDM, or Orthogonal Frequency Domain Multiplex) transmission systems, such as DVB-T for Europe DTV and ISDB-T for Japan DTV systems. However, antenna diversity has not been effectively used for single carrier DTV systems. Instead of using MRC (maximum ratio combining) technique for the antenna diversity in multi-carrier (OFDM) systems, single carrier DTV receivers usually use selective combining techniques. 
         [0004]    United States Published patent application number 20090161748 entitled MMSE-DFE EQUALIZATION WITH ANTENNA DIVERSITY FOR MOBILE DTV to Wang, which is hereby incorporated herein by reference, describes a decision feedback equalizer having a feedback filter and K feed forward filter branches. Each of the K feed forward filter branches receives an input signal from a corresponding one of a plurality of channels associated with a corresponding one of a plurality of antennas, where K&gt;1. Each of the K feed forward filter branches provides an output. Those outputs will be selectively chosen based on a threshold scheme described by the inventor for selective combining. However, Wang teaches space diversity with selective combining. 
         [0005]    In terrestrial digital television (DTV) broadcasting, it is known that severe frequency selective fading is one of the major sources of signal degradation. Multipath effect as a cause of this frequency selective fading is known in that multiple copies of the transmitted signal travel to the receiver through different paths. It is further known that Multipath effects intersymbol interference (ISI) at the receiver level resulting in data errors if no effective equalization is performed. Multipath is more profound in the context of indoor and mobile DTV where the receiver is installed inside a room or in a vehicle adapted to move in that the receiver is a non-fixed point receiver. 
         [0006]    It is known that in the non-fixed point receiver context, the wireless channel varies and becomes uncorrelated over a short period of time. Deep fades occur more frequently than in the fixed point context. Recently, linear equalization techniques, based on the zero-forcing (ZF) constraint or the minimum mean squared error (MMSE) criterion, have been extensively investigated. Due to mathematical tractability and desirable simplicity of the ZF or MMSE, both techniques have been widely documented in the wireless communication literature. 
         [0007]    The challenge is to design a robust equalizer for indoor and/or mobile applications. One of the solutions is to use a nonlinear decision-feedback equalizer (DFE). A DFE has been shown to have significant performance advantages over linear equalizers. Further, the DFE has simplicity as compared to the discouraging complexity of optimum nonlinear equalizers. For practical purposes, some form of updating process, such as the least mean square (LMS) and the recursive least squares (RLS) algorithms, is used to update decision-feedback equalizers for changing channel conditions. However, when there is a precipitous fade, the tracking loops of decision-feedback equalizers may lose lock, resulting in a convergence problem (divergence of the receiving system). If divergence occurs, errors will propagate throughout the data stream until the equalizer is reinitialized. The consequence of this error propagation is serious for decision-feedback equalizer receivers due to their inherent error propagation deficiencies. 
         [0008]    An alternative to using the above mentioned adaptive algorithms (LMS, RLS), there is direct coefficient calculation algorithms based on block data processing for fast adapt to the channels profile change. See “Block Channel Equalization in the Frequency Domain” by F. Pancaldi, et al, which is hereby incorporated herein by reference, IEEE Transactions on Communications, Volume 53, Issue 3, March 2005 Page(s): 463-471. In which channel equalization algorithms processing a block of the received signal and operating in the frequency domain are described in a unifying framework. First, minimum mean-square error linear and decision-feedback equalizers are derived, and a synthesis technique based on the well-known Levinson-Durbin algorithm is proposed for the latter. Then, iterative linear and decision-feedback equalization algorithms for turbo processing are devised. Performance results for both uncoded and coded phase-shift keying transmissions show the efficacy of the proposed equalization techniques and their superiority over other existing frequency-domain equalization strategies. However, Panacaldi teaches only single channel B dfe  and uses a known algorithm. 
         [0009]    This class of block equalizers for single carrier DTV receiver requires channel estimation before equalization. There are many channel estimation algorithms that can be used for this purpose. In this invention, we assume the channel estimation has been done. 
         [0010]    Another promising solution to indoor and mobile DTV receivers is to employ antenna diversity at the receiver. Theoretically, as long as two antennas are separated by more than half a wavelength, the channel characteristics of the two paths are independent. Hence, the probability of concurrent deep fades is small. When one channel fades, accurate symbol decisions can still be obtained from the other channel, so that the update process can continue without divergence. Thus, system performance is significantly improved with joint operation of the multiple antennas. However, the spectrum of the terrestrial DTV is allocated in within 900 MHz, the wavelength is longer than one feet. The physical dimension limitation on a receiver may not be able to accommodate multiple antennae with space diversity requirements. 
         [0011]    Therefore, it is desirous to have multiple tuners for either one antenna receiver, or multiple antennae and using the tuner&#39;s independent noise characteristic, and to have maximum ratio combining for the multiple tuner inputs, and to have Minimum Mean Square Error Decision Feedback Equalizer to remove multipath interference for single carrier terrestrial digital television receiver. 
       SUMMARY OF THE INVENTION  
       [0012]    A method and device for block channel equalization having superposition diversity feature for single carrier transmission system are provided. In the present invention, we referred to Superposition Diversity as Super Diversity. 
         [0013]    A method and device for an improved block channel equalization in the frequency domain having minimum mean square error decision feedback equalizer (MMSE-DFE) with reduced implementation complexity are provided. 
         [0014]    A method and device for block channel equalization using multiple tuners having a novel maximum ratio combining (MRC) and minimum mean square error (MMSE) featured for Super Diversity are provided. 
         [0015]    A single or multiple antennae digital receiver with Super Diversity gain is provided. 
         [0016]    A single or multiple antennae terrestrial television (DTV) with Super Diversity gain is provided. 
         [0017]    A single carrier terrestrial television (DTV) receiver having a single antenna or multiple antennae and a block channel equalization having a novel maximum ratio combining (MRC) and minimum mean square error (MMSE) features is provided. 
         [0018]    A single carrier communication receiver with maximum ratio combining (MRC) and minimum mean square error (MMSE) features for Super Diversity is provided. 
         [0019]    A single carrier communication receiver with MRC, and DFE features for Super Diversity is provided. 
         [0020]    A single carrier terrestrial television (DTV) receiver having a block channel equalization and minimum mean square error (MMSE) features is provided. 
         [0021]    An equalizer is provided. The equalizer comprises a frequency domain a minimum-mean square-error (MMSE) decision feedback equalization (DFE) block having a backward filter co-efficient (BFC) feature adapted to operate in a single carrier environment. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0022]    The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention. 
           [0023]      FIG. 1A  is a first example of a first receiver in accordance with some embodiments of the invention. 
           [0024]      FIG. 1B  is a second example of a first receiver in accordance with some embodiments of the invention. 
           [0025]      FIG. 2  is an example of a maximum ratio combiner (FD-MRC-DFE) in accordance with some embodiments of the invention. 
           [0026]      FIG. 3  is an example of a maximum ratio combiner (FE-MRC-EQ) in accordance with some embodiments of the invention. 
           [0027]      FIG. 4  shows the computation of CE(k). 
           [0028]      FIG. 5  further shows the computation of CE(k). 
           [0029]      FIG. 6  shows the computation of MR(k). 
           [0030]      FIG. 7  shows the computation of R(k) 
           [0031]      FIG. 8  shows the computation of U(k). 
           [0032]      FIG. 9  shows the computation of F(k). 
           [0033]      FIG. 10  shows the computation of R(k). 
           [0034]      FIG. 11  is a diagram for computing MRC. 
           [0035]      FIG. 11A  is a first detailed diagram depicting part of  FIG. 11 . 
           [0036]      FIG. 11A-1  is a generic diagram of  FIG. 11A . 
           [0037]      FIG. 11B  is a second detailed diagram depicting part of  FIG. 11 . 
           [0038]      FIG. 11B-1  is a generic diagram of  FIG. 11B . 
       
    
    
       [0039]    Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention. 
       DETAILED DESCRIPTION  
       [0040]    Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method steps and apparatus components related to carrier recovery, symbol/timing recovery, frequency down conversion, baseband signal filter, frame synchronization, and channel estimation for the received multiple channel signals from either single or multiple antennae with multiple tuners and then using channel decoder to overcome bad data or error in a coding context. Accordingly, the apparatus components and method steps have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. 
         [0041]    In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. 
         [0042]    Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing: the term “including” should be read as mean “including, without limitation” or the like; the term “example” is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; and adjectives such as “conventional,” “traditional,” “normal,” “standard,” and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass conventional, traditional, normal, or standard technologies that may be available now or at any time in the future. Likewise, a group of items linked with the conjunction “and” should not be read as requiring that each and every one of those items be present in the grouping, but rather should be read as “and/or” unless expressly stated otherwise. Similarly, a group of items linked with the conjunction “or” should not be read as requiring mutual exclusivity among that group, but rather should also be read as “and/or” unless expressly stated otherwise. 
         [0043]    It will be appreciated that embodiments of the invention described herein may be comprised of one or more conventional processors and unique stored program instructions that control the one or more processors to implement, channel estimation for received multiple channel signals. The non-processor circuits may include, but are not limited to, a radio receiver, a radio transmitter, signal drivers, clock circuits, power source circuits, and user input devices. As such, these functions may be interpreted as steps of a method to equalize the received multiple channel signals. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used. Thus, methods and means for these functions have been described herein. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation. 
         [0044]    The present invention contemplates a wireless receiver not only used in DTV systems, but also used in such wireless systems as a personal digital assistant (PDA), a mobile PC, an Internet PC, a cell phone, or any WiMax or LTE device, as well as any mobile indoor device. 
         [0045]    Referring to  FIG. 1A , an example of a first receiver  100  in accordance with some embodiments of the invention is shown. A received signal is received by antenna  102 . As can be seen, receiver  100  is a single antenna receiver such as a single antenna digital TV receiver with multiple tuners. In turn, a first tuner  104  processes the received signal. The tuner  104  generate its proprietary signal to noise ratio based upon the tuner&#39;s noise characteristics. The received signal, with tuner&#39;s noise characteristics, is subjected to preprocessing  106 . Preprocessing comprises down conversion, carrier recovery, symbol/timing recovery, base-band signal filter, frame synchronization, Signal to Noise Ratio (SNR) and channel estimation. After preprocessing, the respective signal  105 , along with its time domain channel estimation information  107  are separately input into a FD-MRC-DFE (i.e. Frequency Domain Maximum Ratio Combining Decision Feedback Equalizer) block  108 . The output thereof is further subjected to down stream processing including Forward Error control (FEC)  110 , etc. This forms the first signal path  112 . 
         [0046]    Similarly, for a second signal path  114 , the received signal is received by antenna  102 . In turn, a second tuner  118  processes the received signal. The tuners  118  generate its proprietary signal to noise ratio (SNR) based upon the tuner&#39;s noise characteristics. The received signal, with its noise characteristics, is subjected to preprocessing  120 . Preprocessing comprises down conversion, carrier recovery, symbol/timing recovery, base-band signal filter, frame synchronization, Signal to Noise Ratio (SNR) and channel estimation. After preprocessing, the respective signal along with its time domain channel estimation information are separately input into a FD-MRC-DFE: Frequency Domain Maximum Ratio Combining Decision Feedback Equalizer block  108 . The output thereof is further subjected to down stream processing including Forward Error Correction (FEC)  110 , etc. This forms the second signal path  114 . Note that only three paths are shown. However, in practice, up to N (N being a natural number, with N greater than or equal to 2) paths may be formed. 
         [0047]    Therefore, generically, of the Nth path  116 , the received signal is received by antenna  102 . In turn, a first tuner  122  processes the received signal. The tuners  122  generate its proprietary signal to noise ratio based upon the tuner&#39;s noise characteristics. The received signal, with its noise characteristics, is subjected to preprocessing  124 . Preprocessing comprises down conversion, carrier recovery, symbol/timing recovery, base-band signal filter, frame synchronization, Signal to Noise Ratio (SNR) and channel estimation. After preprocessing, the respective signal  123 , with its time domain channel estimation information  125  are separately input into a FD-MRC-DFE: Frequency Domain Maximum Ratio Combining Decision Feedback Equalizer block  108 . The output thereof is further subjected to down stream processing including Forward Error control (FEC)  110 , etc. 
         [0048]    Referring to  FIG. 1B , an example of a second receiver  200  in accordance with some embodiments of the invention is shown. A received signal is received by a plurality of antennae comprising a set of N antennae (N being a natural number, with N greater than or equal to 2). Each antenna has its own tuner. Each antenna forms its own signal path. 
         [0049]    A first tuner  204  processes the received signal. The tuners  204  generate its proprietary signal to noise ratio based upon the tuner&#39;s noise characteristics. The received signal, with its noise characteristics, is subjected to preprocessing  206  including, for example, Carrier recovery, symbol/timing recovery, down conversion, baseband filter, frame synchronization, Signal to Noise Ratio (SNR) channel estimation . . . , etc. After preprocessing, the respective signal  205  with its time domain channel estimation information  207  are input into a frequency domain maximum ratio combining-decision feedback equalizer block  108 . The output thereof is further subjected to down stream processing including Forward Error control (FEC)  110 , etc. This forms the first signal path  212 . 
         [0050]    Similarly, for a second signal path  2022 , the received signal is received by antenna  2022 . In turn, a second tuner  218  processes the received signal. The tuners  218  generate its proprietary signal to noise ratio based upon the tuner&#39;s noise characteristics. The received signal, with its noise characteristics, is subjected to preprocessing  220  (ex. Carrier recovery, symbol/timing recovery, down conversion, baseband filter, frame synchronization, channel estimation, etc). After preprocessing, the respective signal with its time domain channel estimation information are input into a frequency domain maximum ratio combining-decision feedback equalizer block  108 . The output thereof is further subjected to down stream processing including Forward Error control (FEC)  210 , etc. This forms the second signal path  212 . Note that only three paths are shown. However, in practice, up to N (N being a natural number, with N greater than or equal to 2) paths may be formed. 
         [0051]    Therefore, generically, of the Nth path  2024 , the received signal is received by antenna  2024 . In turn, a first tuner  222  processes the received signal. The tuners  222  generate its proprietary signal to noise ratio based upon the tuner&#39;s noise characteristics. The received signal, with its noise characteristics, is subjected to preprocessing  224 . Preprocessing comprises down conversion, carrier recovery, symbol/timing recovery, base-band signal filter, frame synchronization, Signal to Noise Ratio (SNR) and channel estimation. After preprocessing, the respective signal  223 , with its time domain channel estimation information  225  are separately input into a frequency domain maximum ratio combining-decision feedback equalizer block  108 . The output thereof is further subjected to down stream processing including Forward Error control (FEC)  210 , etc. 
         [0052]    Referring to  FIG. 2 , is a first example of a frequency domain maximum ration combining decision feedback equalizer block  108  of either  FIG. 1A , or  FIG. 1B  is shown. Received multiple channel signals  302  are fed into a frequency domain maximum ratio combiner equalizer (FD-MRC-EQ)  304 . Received multiple channel signals  302  are denoted by r 1−n . a predetermined threshold value  305  is also fed into FD-MRC-EQ  304 . The output of maximum ratio combiner-feedback decision equalizer  304  is fed into adder  306 . The sum of adder  306  is input into the decision device  308 . The output  310  of slicer or decision device  308  is fed down stream for further processing. Output  310  is fed back into a backward filter  312 . The negative output of backward filter  312  is fed to adder  306 . Channel estimation information  314 , also denoted as CE(1−n), is fed to frequency domain maximum ratio combiner equalizer  304  as well as a minimum mean square backward filter coefficient (BFC) calculator  316 . A SNR value is also fed into BFC  316 . The output  307  of  316  is fed to the frequency domain maximum ratio combiner equalizer  304 , as well as partially fed to a backward filter  312 . The feed into FD-MRC-EQ  304  comprises a first vector having size m (m being a natural number). The feed into  312  comprises a second vector having size m−1. In other words, the first element of the first vector is not included in the second vector. To put the above in mathematical terms {tilde over (v)}{tilde over (v 1 )}=(bfc 1 , . . . , bfc m ) and {tilde over (v)}{tilde over (v 2 )}=(bfc 2 , . . . , bfc m ). 
         [0053]    BFC stands for Backward Filter Coefficient calculation based on channel estimation (ce) of the multiple channel signals (r). 
         [0054]    FD-MRC-EQ stands for Frequency Domain Maximum Ration Combining EQualizer received multiple channel signals  302  comprises a plurality of received multiple channel signals (r 1 , r 2 , . . . , r N ). 
         [0055]    Channel estimation information  314  comprises a plurality of channel estimation of multiple channels (ce 1 , ce 2 , . . . , ce N ). 
         [0056]    bfc stands for backward filter co-efficient value. 
         [0057]    Referring to  FIG. 3 , an example of a frequency domain maximum ratio combiner equalizer (FD-MRC-EQ)  304  of  FIG. 2  is shown. Received multiple channel signals  302  are respectively subjected to Fourier transform into frequency domain via a set of N fast Fourier transformers (FFT)  402 . Similarly, Channel estimation information  314  are respectively subjected to Fourier transform into frequency domain via a set of N (N being a natural number greater than or equal to 2) fast Fourier transformers (FFT)  404 . Further, the set of backward filter co-efficients (bfc) is subjected to Fourier transformation into frequency domain via a single fast Fourier transformers (FFT)  406 . The output of  402 ,  404 , and  406  are all input into a maximum ratio combiner (MRC)  408 . The output of MRC  408  is transformed back into the time domain by an inverse Fourier transformer (IFFT)  410 . 
         [0058]    The driving of MRC are as follows. 
         [0059]    Referring to  FIGS. 4-5 , the computation of CE(k) is shown. each element is first multiplied with its own complements and then added up. 
         [0000]      CE (k) =CE( k ) 1 CE( k ) 1 *+ . . . +CE( k ) m CE( k ) m *=Σ i=1   m =CE i ( k )CE i *( k )
 
         [0060]    Where CE i (k) is one of the channel estimations in frequency domain representation with i ranging from  1  to m, with m denoting the number of tuners. 
         [0061]    Where k=1, . . . , N which span the FFT length. 
         [0062]    Similarly 
         [0063]    (1) The first method: 
         [0064]    Referring to  FIG. 6 , the computation of MR(k) is shown 
         [0000]    
       
         
           
             
               
                 
                   
                     M 
                      
                     
                         
                     
                      
                     
                       
                         R 
                         1 
                       
                        
                       
                         ( 
                         k 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         
                           CE 
                           1 
                           * 
                         
                          
                         
                           ( 
                           k 
                           ) 
                         
                       
                       
                         CE 
                          
                         
                           ( 
                           k 
                           ) 
                         
                       
                     
                      
                     
                       BFC 
                        
                       
                         ( 
                         k 
                         ) 
                       
                     
                   
                 
               
             
             
               
                 ⋮ 
               
             
             
               
                 
                   
                     M 
                      
                     
                         
                     
                      
                     
                       
                         R 
                         m 
                       
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                         ( 
                         k 
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                   = 
                   
                     
                       
                         
                           CE 
                           m 
                           * 
                         
                          
                         
                           ( 
                           k 
                           ) 
                         
                       
                       
                         CE 
                          
                         
                           ( 
                           k 
                           ) 
                         
                       
                     
                      
                     
                       BFC 
                        
                       
                         ( 
                         k 
                         ) 
                       
                     
                   
                 
               
             
           
         
       
     
         [0065]    Note MR i (k) may be truncated in order to limit the maximum value to a fixed number for reducing the noise enhancement effect. In other words, a predetermined value is set as the upper limit. Otherwise, the upper limit may be infinity. 
         [0066]    Referring to  FIG. 7 , the computation of R(k) is shown. 
         [0000]    
       
         
           
             
               R 
                
               
                 ( 
                 k 
                 ) 
               
             
             = 
             
               
                 ∑ 
                 
                   i 
                   = 
                   1 
                 
                 m 
               
                
               
                 
                   
                     R 
                     i 
                   
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                     ( 
                     k 
                     ) 
                   
                 
                 * 
                 M 
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                     R 
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         [0067]    As can be seen, there is only a single BFC value for i=1, . . . , m. 
         [0068]    Referring to  FIG. 8 , the computation of U(k) is shown. the formula is listed below. 
         [0000]    
       
         
           
             
               U 
                
               
                 ( 
                 k 
                 ) 
               
             
             = 
             
               
                 1 
                 
                   CE 
                    
                   
                     ( 
                     k 
                     ) 
                   
                 
               
                
               
                 BFC 
                  
                 
                   ( 
                   k 
                   ) 
                 
               
             
           
         
       
     
         [0069]    Note U(k) may be truncated in order to limit the maximum value to a fixed number for reducing the noise enhancement effect. In other words, a predetermined value is set as the upper limit. Otherwise, the upper limit may be infinity. 
         [0070]    Referring to  FIG. 9 , the computation of F(k) is shown. The formula is listed below. 
         [0000]    
       
         
           
             
               F 
                
               
                 ( 
                 k 
                 ) 
               
             
             = 
             
               
                 ∑ 
                 
                   i 
                   = 
                   1 
                 
                 m 
               
                
               
                 
                   
                     R 
                     i 
                   
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                     k 
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                 · 
                 
                   
                     CE 
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         [0071]    Referring to  FIG. 10 , the computation of R(k) is shown. the formula is listed below. 
         [0000]        R ( k )= U ( k ) F ( k ) 
         [0072]    Wherein k=[1 . . . N] N being the length of FFT. 
         [0073]    The following is the code associated with computing for BFC. Part of the computation is shown in  FIGS. 11 ,  11 A-B, etc. 
         [0074]    Referring to  FIG. 11 , two sets of registers, REG and reg, are provided. Each set consists of N (being a natural number) registers with N being the length of FFT. A set of N−1 DE elements are provided. A CS element is provided. The flows are as shown. In other words, for CS, ‘a’ and ‘b’ feed thereinto. The output of CS is c and s respectively. An r also feeds back into REG 1 . ‘a’ also goes into its respective DE. ‘d’ gets out of its respective DE. ‘e’ feeds backward one element its respective DE. Note for reg N , a zero is padded in. 
         [0075]    Referring to  FIG. 11A , internal structure of CS is shown. ‘a’ and its compliment ‘a*’ is multiplied to get |a| 2  and ‘b’ and its compliment ‘b*’ is multiplied to get |b| 2 . In turn, both are summed to get |a| 2 +|b| 2 . then the result is square-rooted √{square root over (|a| 2 +|b| 2 )}. In turn, ‘c’, ‘r’, and ‘s’ are derived. Also refer to code lines  18 - 20 . 
         [0076]    Referring to  FIG. 11A-1 , a holistic view of  FIG. 11A  is shown. The inputs are a and b, the outputs are c, r, and s for block CS. 
         [0077]    Referring to  FIG. 11B , internal structure of DE is shown. ‘a’ is multiplied with ‘c’ and ‘s*’ respectively in both a first multiplier and a second multiplier. ‘c’ is multiplied with ‘a’ and ‘b’ respectively in both a first multiplier and a fourth multiplier. ‘s’ is first transformed to ‘s*’ and multiplied with ‘a’ and ‘b’ respectively in both a second multiplier and a third multiplier. ‘b’ is multiplied with ‘c’ and ‘s’ respectively in both a third multiplier and a fourth multiplier. The product of the first and third multiplier are summer to derive ‘d’. The product of the second and fourth multiplier are summer to derive ‘e’. Also refer to code lines  23 - 24 . 
         [0078]    Referring to  FIG. 11B-1 , a holistic view of  FIG. 11B  is shown. The inputs are a, c, s, and b, the outputs are d, and e for block DE. 
         [0079]    The process is iterated as described in code lines  15 - 16 ,  22 , and  29  by a system clock, which is NOT described or shown, until the resultant bfc, as code line  38 , is generated. 
         [0080]    The following is the code associated with  FIG. 11 . Note that under multiple tuner situations, a single set of bfc is used. 
         [0000]    
       
         
               
               
             
               
               
               
             
               
               
             
           
               
                   
               
             
             
               
                 1 
                 Parameter definitions: 
               
               
                 2 
                 chNum: the number of channel estimations (ce). 
               
               
                 3 
                 chLength: the maximum length of all the channel estimations (ce). 
               
               
                 4 
                 M: the number of backward filter coefficient 
               
               
                 5 
                 nsr: the square root of the noise to signal ratio (predetermined) 
               
               
                 6 
                 Initialization of the registers: 
               
               
                 7 
                 sa0 (1,chLength) = 0 
               
               
                 8 
                 sa (1:chNum,1:chLength) = 0; 
               
               
                 9 
                 sa0(1) = sqrt(nsr); 
               
               
                 10 
                 for k = 1:chNum 
               
               
                 11 
                   sa(k,1:chLength) = conj(ch(k,:)); 
               
               
                 12 
                 end 
               
               
                 13 
                 r1 = sa0(1); 
               
               
                 14 
                 Iterative process: Refer to Fig.11 
               
             
          
           
               
                 15 
                 for i = 1:M; 
                 -- iteration for the each bfc 
               
               
                 16 
                  for j = 1:chNum 
                 -- iteration for the multiple channel 
               
             
          
           
               
                 17 
                   if sa(j,1) ~= 0 
               
               
                 18 
                    r = sqrt(sa0(1)*sa0(1) + sa(j,1)*conj(sa(j,1))); 
               
               
                 19 
                    C = sa0(1)/r1; 
               
               
                 20 
                    S = conj(sa(j,1))/r1; 
               
               
                 21 
                    sa0(1) = r1; 
               
               
                 22 
                    for k = 2:chLength 
               
               
                 23 
                     sa0(k) = C*sa0(k)+S*sa(j,k); %for parallel processing 
               
               
                 24 
                     sa(j,k) = −conj(S)*sa0(k) + C*sa(j,k); 
               
               
                 25 
                    endfor line 22 
               
               
                 26 
                   endif line 17 
               
               
                 27 
                  endfor line 16 
               
               
                 28 
                  if i &lt; M 
               
               
                 29 
                    for j = 1:chNum 
               
               
                 30 
                    for k = 2:chLength 
               
               
                 31 
                     sa(j,k−1) = sa(j,k); 
               
               
                 32 
                    end for line 30 
               
               
                 33 
                    sa(j,chLength) = 0; 
               
               
                 34 
                    end for line 29 
               
               
                 35 
                  end if lin 28 
               
               
                 36 
                 endfor line 15 
               
               
                 37 
                 The result of the bfc 
               
               
                 38 
                 Bfc(1:chLength) = conj(sa0(1:chLength))/r1; 
               
               
                   
               
             
          
         
       
     
         [0081]    The present invention contemplates the use of Superposition Diversity. Superposition Diversity technique is more general than Space Diversity technique, which is commonly used in the communication and DTV receivers for multi-carrier systems. Similar to Space Diversity, Superposition Diversity technique uses multiple copies of the received signals. The difference between Space Diversity and Superposition Diversity is that Space Diversity requires the multiple copies of the received signal to have independent channel characteristics and noise characteristics. On the other hand, Superposition Diversity requires only the independent noise characteristics for the multiple copies of the received signal. From the device implementation point of view, Space Diversity DTV receivers need multiple antennae with multiple tuners and Superposition Diversity DTV receivers only need multiple tuners with either a single antenna, or multiple antennae. The Super Diversity technique is not limited to DTV receivers. It can be used for any single carrier transmission communication systems. 
         [0082]    In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.