Abstract:
A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is removed by heating.

Description:
BACKGROUND OF THE INVENTION 
     A probe mark is left on bond pads after chip probe (CP) sorting. This probe mark will be enlarged during the integrated circuit (IC) assembly wafer die-sawing due to a so-called “Galvanic effect,” i.e. an electrochemical reaction on the bond pad during the die-sawing. This may: expose the bond pad under-layer which has a great impact on the subsequent wire bonding process; degrade the wire bond integrity; and lead to assembly yield loss. 
     This probe mark enlargement is especially so and more serious for the larger 12-inch wafers since longer die-sawing is required for the larger area of the 12 inch-wafer. To minimize this exacerbated problem for the larger 12-inch wafers conventionally, attempts are made to shorten the 12-inch wafer die-saw process time although sometimes this is not possible. 
     U.S. Pat. No. 6,335,224 B1 to Peterson et al. discloses protection of microelectronic devices during packaging. 
     U.S. Pat. No. 6,297,561 B1 to Liu et al. discloses a semiconductor chip. 
     U.S. Pat. No. 6,251,694 B1 to Liu et al. discloses a method of testing and packaging a semiconductor chip. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of one or more embodiments of the present invention to provide a method of protecting bond pads during die-sawing. 
     Other objects will appear hereinafter. 
     It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is removed by heating. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which: 
         FIGS. 1 to 5  schematically illustrate a preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Information Known to the Inventors—Not to be Considered Prior Art 
     The following is information known to the inventors and is not to necessarily be considered prior art for the purposes of the present invention. 
     Re the Galvanic effect, in the presence of a suitable electrolyte (moisture), corrosion will occur (Al 2 Cu as the cathode, Al an the anode). The corrosion of aluminum proceeds around the Al 2 Cu particles leading to the formation of pits until the Al 2 Cu particles become electrically isolated from the surrounding metal:
 
2Al+3Cu 2+ →2Al 3+ +3Cu
 
As the wafer is continually dipped in deionized water (DI), this galvanic cell reaction would continue to proceed. Eventually dredging the base of copper (Cu) nucleus and leave a hole in the pads.
 
Initial Structure— FIG. 1 
 
     As shown in  FIG. 1 , a structure  10  has an uppermost conductive portion  12  formed thereover that is electrically connected to a bond pad  18  by conductive via structures  14  within a dielectric layer  16 . A patterned passivation layer  20  is formed over the dielectric layer  16  and over the bond pad  18 . Patterned passivation layer  20  includes an opening  21 , exposing a portion of bond pad  18 . 
     Structure  10  is preferably a silicon or germanium substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer. 
     Uppermost conductive portion  12  is preferably comprised of copper, aluminum, or an aluminum-copper alloy and is more preferably aluminum. 
     Conductive via structures  14  are preferably comprised of copper or tungsten (W) and is more preferably tungsten. 
     Bond pad  18  is preferably comprised of copper or aluminum and is more preferably aluminum and has a thickness of preferably from about 0.5 to 2.0 μm. 
     Dielectric layer  16  is preferably comprised of silicon oxide. 
     Passivation layer  20  is preferably comprised of silicon oxide or silicon nitride and is more preferably silicon nitride. 
     Passivation layer opening  21  has a base width of preferably from about 40 to 100 μm and more preferably from about 40 to 60 μm. 
     Probe  22  Positioning for Chip Probe Sorting— FIG. 2   
     As shown in  FIG. 2 , a probe  22  is positioned onto a portion of the bond pad  18  for chip probe sorting. After chip probe sorting, the bond pad  18  has a probe mark  24  formed on the upper portion of the bond pad  18  that is generally caused by the probe tip scratching the pad surface. 
     Probe Mark  24 — FIG. 3   
     As shown in  FIG. 3 , probe  22  is removed after chip probe sorting leaving probe mark  24  which removes a portion of the bond pad  18  but does not expose the underlying conductive via structures  14  or the uppermost conductive portion  12 . 
     Formation of Bond Pad Protection Layer  26 — FIG. 4   
     As shown in  FIG. 4 , the inventors have discovered that by forming an bond pad protection layer  26  over the probe marked bond pad  18 ′ and the passivation layer  20 , the probe mark  24  will not be enlarged due to the subsequent IC assembly die-sawing by the “Galvanic effect” (see above). The bond pad protection layer  26  is preferably comprised of an organic material (as will be used for illustrative purposes hereafter) and insulates the surface of the probe marked bond pad  18 ′ and thus prevents the otherwise “Galvanic effect” enlargement of the probe mark  24 . 
     The bond protection layer  26  is preferably organic so that it vaporizes upon heating (see below). 
     Organic bond pad protection layer  26  is preferably applied by a curtain-print, spread or spin-coat method and more preferably by a spin coat method. 
     Organic bond pad protection layer  26  is formed to a thickness of preferably from about 1000 to 50,000 Å and more preferably from about 10,000 to 20,000 Å and is preferably comprised of benzitriazoles or benzimidazoles and is more preferably benzimidazoles. 
     Post IC Assembly Wafer Die-Sawing— FIG. 5   
       FIG. 5  illustrates the structure of  FIG. 4  after IC assembly wafer die-sawing and demonstrates that the probe mark  24  is not enlarged in the probe marked bond pad  18 ′. 
     The organic bond pad protection layer  26  will be vaporized during the subsequent die mount and epoxy cure process (high temperature, i.e. a temperature greater than about 175° C.) so that the wire bond process and wire bond integrity will not be impacted. Moreover, the assembly yield loss due to the probe mark  24  can be resolved and minimized. 
     While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.