Abstract:
A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The present invention relates to a memory control circuit and a memory control method.  
         [0003]     2. Description of the Related Art  
         [0004]      FIG. 21  depicts a configuration of a typical memory. A memory  50  can read and write up to L bits of data specified by an A-bit address. Two methods are conceivable to store various data with different data widths as shown in  FIG. 22  into the memory  50 .  
         [0005]     In one method, as shown in  FIG. 23 , each piece of data is stored at one address (see, e.g., Japanese Patent Application Laid-Open Publication No. 1994-266614). In the other method, as shown in  FIG. 24 , a plurality of data with different data widths is packed into the memory  50 .  
         [0006]     However, if the method shown in  FIG. 23  is used, when storing data with a data width less than L bits, an unused data area (invalid data area) is generated, which deteriorates the usage efficiency of the memory. If the method shown in  FIG. 24  is used, although the invalid data area is not generated and the usage efficiency of the memory  50  is improved, processes of packing and unpacking data are needed before writing data into the memory  50  and after reading data from the memory  50 , which increases a processing load.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention was conceived in view of the above situations and it is therefore the object of the present invention to provide a memory control circuit and a memory control method that enable reading and writing of various data with different data widths without causing deterioration of usage efficiency of a memory and increase of a processing load.  
         [0008]     In order to achieve the above object, according to a major aspect of the present invention there is provided a memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing the first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.  
         [0009]     The data output circuit may include: an output data sorting circuit that sorts the plurality of pieces of divided data, each being the k-bit data, output from the m memories, in the order of the nth to mth memory and the first to (n−1)th memories, and outputs the sorted plurality of pieces of divided data, based on the start-position specification address; and an output data selecting circuit that selects the divided data corresponding to the data width of the data from m pieces of the divided data output from the output data sorting circuit, and outputs the selected divided data.  
         [0010]     The output data selecting circuit may include: m logical product circuits (first to mth logical circuits), to which each of the m pieces of the divided data output from the output data sorting circuit is input sequentially; and a mask data input circuit that inputs one logical value for outputting the divided data to the second to (D/k)th logical product circuits, and inputs the other logical value for masking the divided data to be output to the (D/k+1)th to mth logical product circuits, based on the data width of the data.  
         [0011]     The start-position specification address may be a low-order j bits of the A-bit address.  
         [0012]     The other features of the present invention will become apparent from the following description of this specification and the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     To understand the present invention and the advantages thereof more thoroughly, the following description should be referenced in conjunction with the accompanying drawings, in which:  
         [0014]      FIG. 1  depicts a configuration of a memory control circuit of an embodiment of the present invention;  
         [0015]      FIG. 2  depicts an example of data stored in memories M 0  to Mm−1;  
         [0016]      FIG. 3  is a truth table of operation of a selector S 0 ;  
         [0017]      FIG. 4  is a truth table of operation of a decoder  12 ;  
         [0018]      FIG. 5  is a truth table of operation of selectors S 1  to S 3 ;  
         [0019]      FIG. 6  depicts a specific example of a memory control circuit  1  shown in  FIG. 1 ;  
         [0020]      FIG. 7  is a truth table of operation of a decoder  31 ;  
         [0021]      FIG. 8  depicts a relationship between WD_LENGTH input to the input IN of the decoder  12  and a data width;  
         [0022]      FIG. 9  is a truth table of operation of the decoder  12  in a memory control circuit  1   a;    
         [0023]      FIG. 10  is a truth table of operation of the selector S 1  in the memory control circuit  1   a;    
         [0024]      FIG. 11  is a truth table of operation of selectors S 2   a  to S 2   d;    
         [0025]      FIG. 12  is a truth table of operation of selectors S 3   a  to S 3   d;    
         [0026]      FIG. 13  depicts an example of data allocation when a head address of read data is No. 4n;  
         [0027]      FIG. 14  depicts an example of data allocation when a head address of read data is No. 4n+1;  
         [0028]      FIG. 15  depicts an example of data allocation when a head address of read data is No. 4n+2;  
         [0029]      FIG. 16  depicts an example of data allocation when a head address of read data is No. 4n+3;  
         [0030]      FIG. 17  depicts an example of data allocation when a head address of write data is No. 4n;  
         [0031]      FIG. 18  depicts an example of data allocation when a head address of write data is No. 4n+1;  
         [0032]      FIG. 19  depicts an example of data allocation when a head address of write data is No. 4n+2;  
         [0033]      FIG. 20  depicts an example of data allocation when a head address of write data is No. 4n+3;  
         [0034]      FIG. 21  depicts a configuration of a typical memory;  
         [0035]      FIG. 22  depicts an example of various data with different data widths;  
         [0036]      FIG. 23  depicts a method of storing each piece of data into one address; and  
         [0037]      FIG. 24  depicts a method of packing a plurality of data with different data widths into a memory.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0038]     From the contents of the description and the accompanying drawings, at least the following details will become apparent.  
         [0039]     ==Configuration of Memory Control circuit== 
         [0040]      FIG. 1  depicts a configuration of a memory control circuit of an embodiment of the present invention. A memory control circuit  1  is a circuit that controls read/write of data for m memories M 0  to Mm−1 which are k-bit wide, for example, and includes an adder  11 , a decoder  12 , selectors S 0  to S 3 , and AND circuits A 1  to Am−1.  
         [0041]      FIG. 2  depicts an example of data stored in the memories M 0  to Mm−1. As shown in  FIG. 2 , a data width of the stored data is an integral multiple of k bits up to L bits. The number of the memories M 0  to Mm−1 is “m” and m=L/k. Although a data format is left-aligned as shown in  FIG. 2  in this embodiment, the data format is not limited to left-aligned and can be other formats such as right-aligned.  
         [0042]     For example, an A-bit address bus ADDRESS receives input of an address [A− 1 : 0 ] for specifying data stored in the memories M 0  to Mm−1. The input A of the selector S 0  receives input of the high-order A-j bits [A− 1 :j] (hereinafter, “first specification address”) of the A-bit address. The input B of the selector S 0  receives an address (hereinafter, “second specification address”) obtained by adding one to the first specification address with the adder  11 . The input SEL of the selector S 0  receives input of the low-order j bits [j− 1 :] (hereinafter, “start-position specification address”) of the A-bit address.  
         [0043]     The start-position specification address indicates from which one of the m memories M 0  to Mm−1 the data with various data widths shown in  FIG. 2  are stored, and the number of bits is “j”, which is 2 j−1 &lt;m≦2 j . Either the first specification address or the second specification address is output based on the start-position specification address from the outputs Y 0  to Ym−2 of the selector S 0  and is input to the address inputs A of the memories M 0  to Mm. The address input A of the memory Mm−1 receives input of the first specification address.  
         [0044]      FIG. 3  is a truth table of the operation of the selector S 0 . As shown in  FIG. 3 , for example, if a value of the input SEL of the selector S 0  is “0” (decimal number), the outputs Y 0  to Ym−2 are the first specification address (input A). If a value of the input SEL is “1” (decimal number), the outputs Y 1  to Ym−2 are the first specification address (input A) and the output Y 0  is the second specification address (input B). Similarly, if a value of the input SEL is “p” (decimal number), the outputs Yp to Ym−2 are the first specification address (input A) and the outputs Y 0  to Yp−1 are the second specification address (input B). If a value of the input SEL is “m−1” (decimal number), all the outputs Y 0  to Ym−2 are the second specification address (input B).  
         [0045]     The input IN of the decoder  12  receives input of WD_LENGTH indicated by j-bit [j− 1 : 0 ], for example. This WD_LENGTH is a value indicating a data width of the data shown in  FIG. 2  and is represented by how many times the data are larger than k bits. For example, if the data are k×q-bit wide data shown in  FIG. 2 , the value of WD_LENGTH is “q−1”(decimal number). The data width of the data shown in  FIG. 2  may directly be used as WD_LENGTH. For example, in the case of k×q-bit wide data, the value of WD_LENGTH may be “k×q”. However, the number of bits of WD_LENGTH can be reduced when indicated by how many times the data are larger than k bits, as shown in this embodiment.  
         [0046]      FIG. 4  is a truth table of operation of the decoder  12 . As shown in  FIG. 4 , for example, if a value of the input IN of the decoder  12  is “r” (decimal number), the outputs Y 1  to Yr are “1” and the outputs Yr+1 to Ym−1 are “0”. That is, the number of memories necessary for storing the data shown in  FIG. 2  among the memories M 0  to Mm−1 is obtained by adding one to the number of “1s” in the outputs Y 1  to Ym−1.  
         [0047]     The selector S 1  enables read/write of the necessary memories among the memories M 0  to Mm−1 based on the start-position specification address and the outputs Y 1  to Ym−1 of the decoder  12 . The input INO of the selector S 1  receives input of “1”, and the inputs IN 1  to INm−1 receive the outputs Y 1  to Ym−1 from the decoder  12 . The outputs /Y 0  to /Ym−1 of the selector S 1  output the inputs IN 0  to INm−1 sorted and inverted based on the start-position specification address input to the input SEL, which are input to the input /CS for enabling read/write of the memories M 0  to Mm−1.  
         [0048]      FIG. 5  is a truth table of operation of selectors S 1  to S 3 . As shown in  FIG. 5 , for example, if a value of the input SEL of the selector S 1  is “0” (decimal number), the outputs /Y 0  to /Ym−1 are /IN 0  to /INm−1. For example, a data width is k×3 bits, /Y 0  to /Y 2  are “0”; /Y 3  to /Ym−1 are “1”; and the memories M 0  to M 2  become the readable/writable state. Similarly, if a value of the input SEL is “s” (decimal number), /IN 0  to /INm−1 are output in the order of the outputs /Ys to /Ym−1 and /Y 0  to /Ys−1. If a data width is k×q bits, q memories become the readable/writable state in the order of the memories Ms to Mm−1 and M 0  to Ms−1.  
         [0049]     The selector S 2  is a circuit that sorts and outputs k-bit data (divided data) read from the memories M 0  to Mm−1. The inputs IN 0  to INm−1 sequentially receive input of the data outputs Q (k-bit) of the memories M 0  to Mm−1. The input SEL of the selector S 2  receives input of the start-position specification address. The outputs Y 0  to Ym−1 of the selector S 2  output data obtained by sorting the input IN 0  to INm−1 based on the start-position specification address.  
         [0050]     As shown in the truth table of  FIG. 5 , if a value of the input SEL of the selector S 2  is “0” (decimal number), the outputs /Y 0  to /Ym−1 are the inputs /IN 0  to /INm−1, respectively. Similarly, if a value of the input SEL is “t” (decimal number), the inputs /IN 0  to /INm−1 are sorted and output in the order of the outputs /Yt to /Ym−1 and /Y 0  to /Yt−1.  
         [0051]     The output Y 0  of the selector S 2  is connected to the high-order k bits of a read data bus READ_DATA of L bits [L− 1 : 0 ], for example, and the outputs Y 1  to Ym−1 are connected to the remaining L-k bits of the read data bus through the AND circuits A 1  to Am−1, respectively. The AND circuits A 1  to Am−1 receive the outputs Y 1  to Ym−1 from the decoder  12 . Therefore, if a data width is k×q bits, since the outputs Y 1  to Yq−1 from the decoder  12  are “1” and Yq to Ym−1 are “0”, the AND circuits Aq to Am−1 perform zero-clear (zero-mask) of Yq to Ym−1 after the k×q bits among the L-bit data configured by the outputs Y 0  to Ym−1. As a result, the read data with a data width of k bits to L bits are output to the data bus READ_DATA.  
         [0052]     The selector S 3  is a circuit that divides the k-bit to L-bit write data on the L-bit write data bus WRITE_DATA [L− 1 : 0 ] into k-bit data to sort and output the divided data based on the start-position specification address. IN 0  to INm−1 of the selector S 3  receive input of the data (divided data) formed by dividing the write data for every k bits sequentially from the highest order. The inputs IN 0  to INm−1 are sorted based on the start-position specification address and are output as the outputs Y 0  to Ym−1 to the input D of the memories M 0  to Mm−1.  
         [0053]     As shown in the truth table of  FIG. 5 , if a value of the input SEL of the selector S 3  is “0” (decimal number), the outputs /Y 0  to /Ym−1 are the inputs /IN 0  to /INm−1, respectively. Similarly, if a value of the input SEL is “t” (decimal number), the inputs /IN 0  to /INm−1 are sorted and output in the order of the outputs /Yt to /Ym−1 and /Y 0  to /Yt−1.  
         [0054]     The adder  11  and the selector S 0  correspond to an address input circuit of the present invention; the selector S 3  corresponds to a data input circuit of the present invention; the selector S 2 , the decoder  12 , and the AND circuits A 1  to Am−1 correspond to the data output circuit of the present invention; and the decoder  12  and the selector S 1  correspond to a memory selecting circuit of the present invention.  
         [0055]     The selector S 2  corresponds to an output data sorting circuit of the present invention, and the decoder  12  and the AND circuits A 1  to Am−1 correspond to an output data selecting circuit of the present invention. The AND circuits A 1  to Am−1 correspond to a logical product circuit of the present invention, and the decoder  12  corresponds to a mask data input circuit of the present invention.  
         [0056]     =Operation Description with Specific Examples= 
         [0057]     Operation of the memory control circuit  1  will be described with specific examples.  FIG. 6  depicts a specific example of the memory control circuit  1  shown in  FIG. 1 . A memory control circuit  1   a  is a circuit that controls four 8-bit wide memories M 0  to M 3  (k=8, m=4), a data width of the readable/writable data is 8 bits to 32 bits (in every 8 bits). The number of bits for selecting the memories M 0  to M 3  is “j”, which is j=2 because of the relationship of 2 j−1 &lt;m≦2 j .  
         [0058]     In the memory control circuit  1   a , a decoder  31  and selectors  32  to  34  configure the selector S 0  shown in  FIG. 1 . The selectors S 2   a  to S 2   d  configure the selector S 2  shown in  FIG. 1 , and the selectors S 3   a  to S 3   d  configure the selector S 3  shown in  FIG. 1 . D-flip-flops  41  to  45  are disposed for retaining data.  
         [0059]     The input IN of the decoder  31  receives input of the low-order two bits [ 1 : 0 ] (start-position specification address) of 32-bit address [ 31 : 0 ]. A value corresponding to the start-position specification address is output from the outputs Y 0  to Y 2  of the decoder  31 . The selector  32  receives the output Y 0  from the decoder  31 , outputs the input A (high-order 30 bits of the address: the first specification address) if the output Y 0  of the decoder  31  is “0”, for example, and outputs the input B (high-order 30 bits of the address +1: the second specification address) if the output Y 0  of the decoder  31  is “1”, for example. The selectors  33 ,  34  also output the first specification address or the second specification address depending on the outputs Y 1 , Y 2  from the decoder  31 .  
         [0060]      FIG. 7  is a truth table of operation of the decoder  31 . As shown in  FIG. 7 , if a value of the input IN of the decoder  31  is “0” (decimal number), all the outputs Y 0  to Y 2  are “0”. In this case, the selectors  32  to  34  output the first specification address. If a value of the input IN of the decoder  31  is “1” (decimal number), the outputs Y 1  and Y 2  are “0” and the output Y 0  is “1”. In this case, the selectors  33  and  34  output the first specification address, and the selector  32  outputs the second specification address. If a value of the input IN of the decoder  31  is “2” (decimal number), the output Y 2  is “0”, and the outputs Y 0  and Y 1  are “1”. In this case, the selector  34  outputs the first specification address, and the selectors  32  and  33  output the second specification address. If a value of the input IN of the decoder  31  is “3” (decimal number), all the outputs Y 0  to Y 2  are “1”. In this case, the selectors  32  to  34  output the second specification address.  
         [0061]      FIG. 8  depicts a relationship between WD_LENGTH input to the input IN of the decoder  12  and a data width. As shown in  FIG. 8 , a data width is a value obtained by adding one to WD_LENGTH and multiplying by eight (data width=8 bits×(WD_LENGTH+1)).  FIG. 9  is a truth table of operation of the decoder  12  in the memory control circuit  1   a . As shown in  FIG. 9 , if a value of the input IN of the decoder  12  is “0” (decimal number), all the outputs Y 1  to Y 3  are “0”. If a value of the input IN of the decoder  12  is “1” (decimal number), the outputs Y 2  and Y 3  are “0” and the output Y 1  is “1”. If a value of the input IN of the decoder  12  is “2” (decimal number), the output Y 3  is “0”, and the outputs Y 1  and Y 2  are “1”. If a value of the input IN of the decoder  12  is “3” (decimal number), all the outputs Y 1  to Y 3  are “1”.  
         [0062]      FIG. 10  is a truth table of operation of the selector S 1  in the memory control circuit  1   a . As shown in  FIG. 10 , if the start-position specification address (low-order two bits [ 1 : 0 ] of the 32-bit address) input to the input SEL is “0” (decimal number), values obtained by inverting IN 0  to IN 3  are output in the order of the outputs /Y 0  to /Y 3 . If the input SEL is “1” (decimal number), values obtained by inverting IN 0  to IN 3  are output in the order of the outputs /Y 1  to /Y 3  and /Y 0 . If the input SEL is “2” (decimal number), values obtained by inverting IN 0  to IN 3  are output in the order of the outputs /Y 2 , /Y 3 , /Y 0 , and /Y 1 . If the input SEL is “3” (decimal number), values obtained by inverting IN 0  to IN 3  are output in the order of the outputs /Y 3 , /Y 0  to /Y 2 .  
         [0063]      FIG. 11  is a truth table of operation of the selectors S 2   a  to S 2   d  in the memory control circuit  1   a . As shown in  FIG. 11 , if the start-position specification address (low-order two bits [ 1 : 0 ] of the 32-bit address) input to the input SEL is “0” (decimal number), the output (R 31 - 24 ) of the selector S 2   a  is data output from the memory M 0 ; the output (R 23 - 16 ) of the selector S 2   b  is data output from the memory M 1 ; the output (R 15 - 8 ) of the selector S 2   c  is data output from the memory M 2 ; and the output (R 7 - 0 ) of the selector S 2   d  is data output from the memory M 3 .  
         [0064]     That is, if the start-position specification address is “0” (decimal number), the read data are output in the order of the memories M 0  to M 3 . As shown in the truth table of  FIG. 11 , if the start-position specification address is “1” (decimal number), the read data are output in the order of the memories M 1  to M 3  and M 0 . If the start-position specification address is “2” (decimal number), the read data are output in the order of the memories M 2 , M 3 , M 0 , and M 1 . If the start-position specification address is “3” (decimal number), the read data are output in the order of the memories M 3  and M 0  to M 2 .  
         [0065]      FIG. 12  is a truth table of operation of the selectors S 3   a  to S 3   d . As shown in  FIG. 12 , if the start-position specification address (low-order two bits [ 1 : 0 ] of the 32-bit address) input to the input SEL is “0” (decimal number), the output (W 31 - 24 ) of the selector S 3   a  is the high-order eight bits [ 31 : 24 ] of the write data; the output (W 23 - 16 ) of the selector S 3   b  is the next eight bits [ 23 : 16 ] of the write data; the output (W 15 - 8 ) of the selector S 3   c  is the further next eight bits [ 15 : 8 ] of the write data; and the output (W 7 - 0 ) of the selector S 3   d  is the low-order eight bits [ 7 : 0 ] of the write data.  
         [0066]     That is, if the start-position specification address is “0” (decimal number), the data (divided data) formed by dividing the write data for every eight bits are output sequentially from the highest order to the memories M 0  to M 3 . As shown in the truth table of  FIG. 12 , if the start-position specification address is “1” (decimal number), the divided data are output sequentially from the highest order to the memories M 1  to M 3  and M 0 . If the start-position specification address is “2” (decimal number), the divided data are output sequentially from the highest order to the memories M 2 , M 3 , M 0 , and M 1 . If the start-position specification address is “3” (decimal number), the divided data are output sequentially from the highest order to the memories M 3 , M 0  to M 2 .  
         [0067]     The reading/writing (READ/WRITE) operation of the memory control circuit  1   a  will be specifically described.  
         [0068]     (1) READ (head address: No. 4n)  
         [0069]      FIG. 13  depicts an example of data allocation when a head address of read data is No. 4n. If the head address of read data is No. 4n, the low-order two bits [ 1 : 0 ] of the 32-bit address are “0” (decimal number). Therefore, all the outputs Y 0  to Y 2  of the decoder  31  are “0”, and the selectors  32  to  34  output the first specification address. That is, No. n is input to the address inputs A of the memories M 0  to M 3 .  
         [0070]     If the data width of the read data is 32 bits, WD_LENGTH is “3” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “1”. Therefore, all the outputs /Y 0  to /Y 3  of the selector S 1  are “0” and all the memories M 0  to M 3  become readable. Data at No. n in the memories M 0  to M 3  are output from the data outputs Q. These data output from the memories M 0  to M 3  are data at Nos. 4n to 4n+ 3  in the entire address space of the memories M 0  to M 3 . The data read from the memories M 0  to M 3  are sequentially output from the selectors S 2   a  to S 2   d . Since all the outputs Y 1  to Y 3  of the decoder  12  are “1”, the data read from the memories M 1  to M 3  are not cleared by the AND circuits A 1  to A 3 . As a result, 32-bit wide data are output to the read data bus READ_DATA.  
         [0071]     If the data width of the read data is 24 bits, WD_LENGTH is “2” (decimal number). In this case, the outputs Y 1  and Y 2  are “1” and the output Y 3  is “0” in the decoder  12 . Therefore, since the outputs /Y 0  to /Y 2  are “0” and the output /Y 3  is “1” in the selector S 1 , the memories M 0  to M 2  become readable and the memory M 3  becomes unreadable. As a result, the outputs (R 7 - 0 ) of the selector S 2   d  become invalid data, and the AND circuit A 3  performs zero-clear of the invalid data to output 24-bit wide left-aligned data to the read data bus READ_DATA.  
         [0072]     If the data width of the read data is 16 bits, WD_LENGTH is “1” (decimal number). In this case, the output Y 1  is “1” and the outputs Y 2  and Y 3  are “0” in the decoder  12 . Therefore, since the outputs /Y 0  and /Y 1  are “0” and the outputs /Y 2  and /Y 3  are “1” in the selector S 1 , the memories M 0  and M 1  become readable and the memories M 2  and M 3  become unreadable. As a result, the outputs (R 15 - 8 , R 7 - 0 ) of the selectors S 2   c  and S 2   d  become invalid data, and the AND circuits A 2  and A 3  perform zero-clear of the invalid data to output 16-bit wide left-aligned data to the read data bus READ_DATA.  
         [0073]     If the data width of the read data is 8 bits, WD_LENGTH is “0” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “0”. Therefore, since the output /Y 0  is “0” and the outputs /Y 1  to /Y 3  are “1” in the selector S 1 , the memory M 0  becomes readable and the memories M 1  to M 3  become unreadable. As a result, the outputs (R 23 - 16 , R 15 - 8 , R 7 - 0 ) of the selectors S 2   b  to S 2   d  become invalid data, and the AND circuits A 1  to A 3  perform zero-clear of the invalid data to output  8 -bit wide left-aligned data to the read data bus READ_DATA.  
         [0074]     (2) READ (head address: No. 4n+1)  
         [0075]      FIG. 14  depicts an example of data allocation when a head address of read data is No. 4n+1. If the head address of read data is No. 4n+1, the low-order two bits [ 1 : 0 ] of the 32-bit address are “1” (decimal number). Therefore, since the output Y 0  is “1” and the outputs Y 1  and Y 2  are “0” in the decoder  31 , the selectors  33 ,  34  output the first specification address and the selector  32  outputs the second specification address. That is, No. n is input to the address inputs A of the memories M 1  to M 3 , and No. n+1 is input to the address input A of the memory M 0 .  
         [0076]     If the data width of the read data is 32 bits, WD_LENGTH is “3” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “1”. Therefore, all the outputs /Y 0  to /Y 3  of the selector S 1  are “0” and all the memories M 0  to M 3  become readable. Data at No. n in the memories M 1  to M 3  and data at No. n+1 in the memory M 0  are output from the data outputs Q. These data output from the memories M 1  to M 3  and M 0  are data at Nos. 4n+1 to 4n+4 in the entire address space of the memories M 0  to M 3 . The data read from the memories M 1  to M 3  and M 0  are sequentially output from the selectors S 2   a  to S 2   d . Since all the outputs Y 1  to Y 3  of the decoder  12  are “1”, the data read from the memories M 2 , M 3 , and M 0  are not cleared by the AND circuits A 1  to A 3 . As a result, 32-bit wide data are output to the read data bus READ_DATA.  
         [0077]     If the data width of the read data is 24 bits, WD_LENGTH is “2” (decimal number). In this case, the outputs Y 1  and Y 2  are “1” and the output Y 3  is “0” in the decoder  12 . Therefore, since the outputs /Y 1  to /Y 3  are “0” and the output /Y 0  is “1” in the selector S 1 , the memories M 1  to M 3  become readable and the memory M 0  becomes unreadable. As a result, the outputs (R 7 - 0 ) of the selector S 2   d  become invalid data, and the AND circuit A 3  performs zero-clear of the invalid data to output 24-bit wide left-aligned data to the read data bus READ_DATA.  
         [0078]     If the data width of the read data is 16 bits, WD_LENGTH is “1” (decimal number). In this case, the output Y 1  is “1” and the outputs Y 2  and Y 3  are “0” in the decoder  12 . Therefore, since the outputs /Y 1  and /Y 2  are “0” and the outputs /Y 3  and /Y 0  are “1” in the selector S 1 , the memories M 1  and M 2  become readable and the memories M 3  and M 0  become unreadable. As a result, the outputs (R 15 - 8 , R 7 - 0 ) of the selectors S 2   c  and S 2   d  become invalid data, and the AND circuits A 2  and A 3  perform zero-clear of the invalid data to output 16-bit wide left-aligned data to the read data bus READ_DATA.  
         [0079]     If the data width of the read data is 8 bits, WD_LENGTH is “0” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “0”. Therefore, since the output /Y 1  is “0” and the outputs /Y 2 , /Y 3 , and /Y 0  are “1” in the selector S 1 , the memory M 1  becomes readable and the memories M 2 , M 3 , and M 0  become unreadable. As a result, the outputs (R 23 - 16 , R 15 - 8 , R 7 - 0 ) of the selectors S 2   b  to S 2   d  become invalid data, and the AND circuits A 1  to A 3  perform zero-clear of the invalid data to output 8-bit wide left-aligned data to the read data bus READ_DATA.  
         [0080]     (3) READ (head address: No. 4n+2)  
         [0081]      FIG. 15  depicts an example of data allocation when a head address of read data is No. 4n+2. If the head address of read data is No. 4n+2, the low-order two bits [ 1 : 0 ] of the 32-bit address are “2” (decimal number). Therefore, since the outputs Y 0  and Y 1  are “1” and the output Y 2  is “0” in the decoder  31 , the selector  34  outputs the first specification address and the selectors  32 ,  33  output the second specification address. That is, No. n is input to the address inputs A of the memories M 2  and M 3 , and No. n+1 is input to the address inputs A of the memories M 0  and M 1 .  
         [0082]     If the data width of the read data is 32 bits, WD_LENGTH is “3” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “1”. Therefore, all the outputs /Y 0  to /Y 3  of the selector S 1  are “0” and all the memories M 0  to M 3  become readable. Data at No. n in the memories M 2 , M 3  and data at No. n+1 in the memories M 0 , M 1  are output from the data outputs Q. These data output from the memories M 2 , M 3 , M 0 , and M 1  are data at Nos. 4n+2 to 4n+5 in the entire address space of the memories M 0  to M 3 . The data read from the memories M 2 , M 3 , M 0 , and M 1  are sequentially output from the selectors S 2   a  to S 2   d . Since all the outputs Y 1  to Y 3  of the decoder  12  are “1”, the data read from the memories M 3 , M 0 , M 1  are not cleared by the AND circuits A 1  to A 3 . As a result, 32-bit wide data are output to the read data bus READ_DATA.  
         [0083]     If the data width of the read data is 24 bits, WD_LENGTH is “2” (decimal number). In this case, the outputs Y 1  and Y 2  are “1” and the output Y 3  is “0” in the decoder  12 . Therefore, since the outputs /Y 2 , /Y 3 , and /Y 0  are “0” and the output /Y 1  is “1” in the selector S 1 , the memories M 2 , M 3 , and M 0  become readable and the memory M 1  becomes unreadable. As a result, the outputs (R 7 - 0 ) of the selector S 2   d  become invalid data, and the AND circuit A 3  performs zero-clear of the invalid data to output 24-bit wide left-aligned data to the read data bus READ_DATA.  
         [0084]     If the data width of the read data is 16 bits, WD_LENGTH is “1” (decimal number). In this case, the output Y 1  is “1” and the outputs Y 2  and Y 3  are “0” in the decoder  12 . Therefore, since the outputs /Y 2  and /Y 3  are “0” and the outputs /Y 0  and /Y 1  are “1” in the selector S 1 , the memories M 2  and M 3  become readable and the memories M 0  and M 1  become unreadable. As a result, the outputs (R 15 - 8 , R 7 - 0 ) of the selectors S 2   c  and S 2   d  become invalid data, and the AND circuits A 2  and A 3  perform zero-clear of the invalid data to output 16-bit wide left-aligned data to the read data bus READ_DATA.  
         [0085]     If the data width of the read data is 8 bits, WD_LENGTH is “0” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “0”. Therefore, since the output /Y 2  is “0” and the outputs /Y 3 , /Y 0 , and /Y 1  are “1” in the selector S 1 , the memory M 2  becomes readable and the memories M 3 , M 0 , and M 1  become unreadable. As a result, the outputs (R 23 - 16 , R 15 - 8 , R 7 - 0 ) of the selectors S 2   b  to S 2   d  become invalid data, and the AND circuits A 1  to A 3  perform zero-clear of the invalid data to output 8-bit wide left-aligned data to the read data bus READ_DATA.  
         [0086]     (4) READ (head address: No. 4n+3)  
         [0087]      FIG. 16  depicts an example of data allocation when a head address of read data is No. 4n+3. If the head address of read data is No. 4n+3, the low-order two bits [ 1 : 0 ] of the 32-bit address are “3” (decimal number). Therefore, since all the outputs Y 0  and Y 3  of the decoder  31  are “1”, the selectors  32  to  34  output the second specification address. That is, No. n is input to the address input A of the memory M 3 , and No. n+1 is input to the address inputs A of the memories M 0  and M 2 .  
         [0088]     If the data width of the read data is 32 bits, WD_LENGTH is “3” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “1”. Therefore, all the outputs /Y 0  to /Y 3  of the selector S 1  are “0” and all the memories M 0  to M 3  become readable. Data at No. n in the memory M 3  and data at No. n+1 in the memories M 0  to M 2  are output from the data outputs Q. These data output from the memories M 3  and M 0  to M 2  are data at Nos. 4n+3 to 4n+6 in the entire address space of the memories M 0  to M 3 . The data read from the memories M 3  and M 0  to M 2  are sequentially output from the selectors S 2   a  to S 2   d . Since all the outputs Y 1  to Y 3  of the decoder  12  are “1”, the data read from the memories M 0  to M 2  are not cleared by the AND circuits A 1  to A 3 . As a result, 32-bit wide data are output to the read data bus READ_DATA.  
         [0089]     If the data width of the read data is 24 bits, WD_LENGTH is “2” (decimal number). In this case, the outputs Y 1  and Y 2  are “1” and the output Y 3  is “0” in the decoder  12 . Therefore, since the outputs /Y 3 , /Y 0 , and /Y 1  are “0” and the output /Y 2  is “1” in the selector S 1 , the memories M 3 , M 0 , and M 1  become readable and the memory M 2  becomes unreadable. As a result, the outputs (R 7 - 0 ) of the selector S 2   d  become invalid data, and the AND circuit A 3  performs zero-clear of the invalid data to output 24-bit wide left-aligned data to the read data bus READ_DATA.  
         [0090]     If the data width of the read data is 16 bits, WD_LENGTH is “1” (decimal number). In this case, the output Y 1  is “1” and the outputs Y 2  and Y 3  are “0” in the decoder  12 . Therefore, since the outputs /Y 3  and /Y 0  are “0” and the outputs /Y 1  and /Y 2  are “1” in the selector S 1 , the memories M 3  and M 0  become readable and the memories M 1  and M 2  become unreadable. As a result, outputs (R 15 - 8 , R 7 - 0 ) of the selectors S 2   c  and S 2   d  become invalid data, and the AND circuits A 2  and A 3  perform zero-clear of the invalid data to output 16-bit wide left-aligned data to the read data bus READ_DATA.  
         [0091]     If the data width of the read data is 8 bits, WD_LENGTH is “0” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “0”. Therefore, since the output /Y 3  is “0” and the outputs /Y 0  to /Y 2  are “1” in the selector S 1 , the memory M 3  becomes readable and the memories M 0  to M 2  become unreadable. As a result, the outputs (R 23 - 16 , R 15 - 8 , R 7 - 0 ) of the selectors S 2   b  to S 2   d  become invalid data, and the AND circuits A 1  to A 3  perform zero-clear of the invalid data to output 8-bit wide left-aligned data to the read data bus READ_DATA.  
         [0092]     (5) WRITE (head address: No. 4n)  
         [0093]      FIG. 17  depicts an example of data allocation when a head address of write data is No. 4n. If the head address of write data is No. 4n, the low-order two bits [ 1 : 0 ] of the 32-bit address are “0” (decimal number). Therefore, all the outputs Y 0  to Y 2  of the decoder  31  are “0”, and the selectors  32  to  34  output the first specification address. That is, No. n is input to the address inputs A of the memories M 0  to M 3 .  
         [0094]     If the data width of the write data is 32 bits, WD_LENGTH is “3” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “1”. Therefore, all the outputs /Y 0  to /Y 3  of the selector S 1  are “0” and all the memories M 0  to M 3  become writable. The 32-bit write data are divided into 8-bit data from the highest order, input through the selectors S 3   a  to S 3   d  to the data inputs D in the order of the memories M 0  to M 3 , and stored at No. n in each memory. These data stored in the memories M 0  to M 3  are data at Nos. 4n to 4n+3 in the entire address space of the memories M 0  to M 3 .  
         [0095]     If the data width of the write data is 24 bits, WD_LENGTH is “2” (decimal number). In this case, the outputs Y 1  and Y 2  are “1” and the output Y 3  is “0” in the decoder  12 . Therefore, since the outputs /Y 0  to /Y 2  are “0” and the output /Y 3  is “1” in the selector S 1 , the memories M 0  to M 2  become writable and the memory M 3  becomes unwritable. As a result, the high-order 24-bit data on the write data bus WRITE_DATA are divided into 8-bit data from the highest order, input through the selectors S 3   a  to S 3   c  to the data inputs D in the order of the memories M 0  to M 2 , and stored at No. n in each memory.  
         [0096]     If the data width of the write data is 16 bits, WD_LENGTH is “1” (decimal number). In this case, the output Y 1  is “1” and the outputs Y 2  and Y 3  are “0” in the decoder  12 . Therefore, since the outputs /Y 0  and /Y 1  are “0” and the output /Y 2  and /Y 3  are “1” in the selector S 1 , the memories M 0  and M 1  become writable and the memories M 2  and M 3  become unwritable. As a result, the high-order 16-bit data on the write data bus WRITE_DATA are divided into 8-bit data from the highest order, input through the selectors S 3   a  and S 3   b  to the data inputs D in the order of the memories M 0  and M 1 , and stored at No. n in each memory.  
         [0097]     If the data width of the write data is 8 bits, WD_LENGTH is “0” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “0”. Therefore, since the output /Y 0  is “0” and the outputs /Y 1  to /Y 3  are “1” in the selector S 1 , the memory M 0  becomes writable and the memories M 1  to M 3  become unwritable. As a result, the high-order 8-bit data on the write data bus WRITE_DATA are input through the selector S 3   a  to the data input D of the memory M 0  and stored at No. n.  
         [0098]     (6) WRITE (head address: No. 4n+1)  
         [0099]      FIG. 18  depicts an example of data allocation when a head address of write data is No. 4n+1. If the head address of write data is No. 4n+1, the low-order two bits [ 1 : 0 ] of the 32-bit address are “1” (decimal number). Therefore, since the output Y 0  is “1” and the outputs Y 1  and Y 2  are “0” in the decoder  31 , the selectors  33 ,  34  output the first specification address and the selector  32  outputs the second specification address. That is, No. n is input to the address inputs A of the memories M 1  to M 3 , and No. n+1 is input to the address input A of the memory M 0 .  
         [0100]     If the data width of the write data is 32 bits, WD_LENGTH is “3” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “1”. Therefore, all the outputs /Y 0  to /Y 3  of the selector S 1  are “0” and all the memories M 0  to M 3  become writable. The 32-bit write data are divided into 8-bit data from the highest order, input through the selectors S 3   a  to S 3   d  to the data inputs D in the order of the memories M 1  to M 3  and M 0 , and stored at No. n in the memories M 1  to M 3  and at No. n+1 in the memory M 0 . These data stored in the memories M 0  to M 3  are data at Nos. 4n+1 to 4n+4 in the entire address space of the memories M 0  to M 3 .  
         [0101]     If the data width of the write data is 24 bits, WD_LENGTH is “2” (decimal number). In this case, the outputs Y 1  and Y 2  are “1” and the output Y 3  is “0” in the decoder  12 . Therefore, since the outputs /Y 1  to /Y 3  are “0” and the output /Y 0  is “1” in the selector S 1 , the memories M 1  to M 3  become writable and the memory M 0  becomes unwritable. As a result, the high-order 24-bit data on the write data bus WRITE_DATA are divided into 8-bit data from the highest order, input through the selectors S 3   b  to S 3   d  to the data inputs D in the order of the memories M 1  to M 3 , and stored at No. n in each memory.  
         [0102]     If the data width of the write data is 16 bits, WD_LENGTH is “1” (decimal number). In this case, the output Y 1  is “1” and the outputs Y 2  and Y 3  are “0” in the decoder  12 . Therefore, since the outputs /Y 1  and /Y 2  are “0” and the output /Y 3  and /Y 0  are “1” in the selector S 1 , the memories M 1  and M 2  become writable and the memories M 3  and M 0  become unwritable. As a result, the high-order 16-bit data on the write data bus WRITE_DATA are divided into 8-bit data from the highest order, input through the selectors S 3   b  and S 3   c  to the data inputs D in the order of the memories M 1  and M 2 , and stored at No. n in each memory.  
         [0103]     If the data width of the write data is 8 bits, WD_LENGTH is “0” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “0”. Therefore, since the output /Y 1  is “0” and the outputs /Y 2 , /Y 3 , and /Y 0  are “1” in the selector S 1 , the memory M 1  becomes writable and the memories M 2 , M 3 , and M 0  become unwritable. As a result, the high-order 8-bit data on the write data bus WRITE_DATA are input through the selector S 3   b  to the data input D of the memory M 1  and stored at No. n.  
         [0104]     (7) WRITE (head address: No. 4n+2)  
         [0105]      FIG. 19  depicts an example of data allocation when a head address of write data is No. 4n+2. If the head address of write data is No. 4n+2, the low-order two bits [ 1 : 0 ] of the 32-bit address are “2” (decimal number). Therefore, since the outputs Y 0  and Y 1  are “1” and the output Y 2  is “0” in the decoder  31 , the selector  34  outputs the first specification address and the selectors  32  and  33  output the second specification address. That is, No. n is input to the address inputs A of the memories M 2  and M 3 , and No. n+1 is input to the address inputs A of the memories M 0  and M 1 .  
         [0106]     If the data width of the write data is 32 bits, WD_LENGTH is “3” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “1”. Therefore, all the outputs /Y 0  to /Y 3  of the selector S 1  are “0” and all the memories M 0  to M 3  become writable. The 32-bit write data are divided into 8-bit data from the highest order, input through the selectors S 3   a  to S 3   d  to the data inputs D in the order of the memories M 2 , M 3 , M 0 , and M 1 , and stored at No. n in the memories M 2  and M 3  and at No. n+1 in the memories M 0  and M 1 . These data stored in the memories M 0  to M 3  are data at Nos. 4n+2 to 4n+5 in the entire address space of the memories M 0  to M 3 .  
         [0107]     If the data width of the write data is 24 bits, WD_LENGTH is “2” (decimal number). In this case, the outputs Y 1  and Y 2  are “1” and the output Y 3  is “0” in the decoder  12 . Therefore, since the outputs /Y 2 , /Y 3 , and /Y 0  are “0” and the output /Y 1  is “1” in the selector S 1 , the memories M 2 , M 3 , and M 0  become writable and the memory M 1  becomes unwritable. As a result, the high-order 24-bit data on the write data bus WRITE_DATA are divided into 8-bit data from the highest order, input through the selectors S 3   c , S 3   d , and S 3   a  to the data inputs D in the order of the memories M 2 , M 3 , and M 0 , and stored at No. n in the memories M 2  and M 3  and at No. n+1 in the memory M 0 .  
         [0108]     If the data width of the write data is 16 bits, WD_LENGTH is “1” (decimal number). In this case, the output Y 1  is “1” and the outputs Y 2  and Y 3  are “0” in the decoder  12 . Therefore, since the outputs /Y 2  and /Y 3  are “0” and the output /Y 0  and /Y 1  are “1” in the selector S 1 , the memories M 2  and M 3  become writable and the memories M 0  and M 1  become unwritable. As a result, the high-order 16-bit data on the write data bus WRITE_DATA are divided into 8-bit data from the highest order, input through the selectors S 3   c  and S 3   d  to the data inputs D in the order of the memories M 2  and M 3 , and stored at No. n in each memory.  
         [0109]     If the data width of the write data is 8 bits, WD_LENGTH is “0” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “0”. Therefore, since the output /Y 2  is “0” and the outputs /Y 3 , /Y 0 , and /Y 1  are “1” in the selector S 1 , the memory M 2  becomes writable and the memories M 3 , M 0 , and M 1  become unwritable. As a result, the high-order 8-bit data on the write data bus WRITE_DATA are input through the selector S 3   c  to the data input D of the memory M 2  and stored at No. n.  
         [0110]     (8) WRITE (head address: No. 4n+3)  
         [0111]      FIG. 20  depicts an example of data allocation when a head address of write data is No. 4n+3. If the head address of write data is No. 4n+3, the low-order two bits [ 1 : 0 ] of the 32-bit address are “3” (decimal number). Therefore, all the outputs Y 0  to Y 2  of the decoder  31  are “1”, and the selectors  32  to  34  output the second specification address. That is, No. n is input to the address input A of the memory M 3 , and No. n+1 is input to the address inputs A of the memories M 0  to M 2 .  
         [0112]     If the data width of the write data is 32 bits, WD_LENGTH is “3” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “1”. Therefore, all the outputs /Y 0  to /Y 3  of the selector S 1  are “0” and all the memories M 0  to M 3  become writable. The 32-bit write data are divided into 8-bit data from the highest order, input through the selectors S 3   a  to S 3   d  to the data inputs D in the order of the memories M 3  and M 0  to M 2 , and stored at No. n in the memory M 3  and at No. n+1 in the memories M 0  to M 2 . These data stored in the memories M 0  to M 3  are data at Nos. 4n+3 to 4n+6 in the entire address space of the memories M 0  to M 3 .  
         [0113]     If the data width of the write data is 24 bits, WD_LENGTH is “2” (decimal number). In this case, the outputs Y 1  and Y 2  are “1” and the output Y 3  is “0” in the decoder  12 . Therefore, since the outputs /Y 3 , /Y 0 , and /Y 1  are “0” and the output /Y 2  is “1” in the selector S 1 , the memories M 3 , M 0 , and M 1  become writable and the memory M 2  becomes unwritable. As a result, the high-order 24-bit data on the write data bus WRITE_DATA are divided into 8-bit data from the highest order, input through the selectors S 3   d , S 3   a , and S 3   b  to the data inputs D in the order of the memories M 3 , M 0 , and M 1 , and stored at No. n in the memory M 3  and at No. n+1 in the memories M 0  and M 1 .  
         [0114]     If the data width of the write data is 16 bits, WD_LENGTH is “1” (decimal number). In this case, the output Y 1  is “1” and the outputs Y 2  and Y 3  are “0” in the decoder  12 . Therefore, since the outputs /Y 3  and /Y 0  are “0” and the output /Y 1  and /Y 2  are “1” in the selector S 1 , the memories M 3  and M 0  become writable and the memories M 1  and M 2  become unwritable. As a result, the high-order 16-bit data on the write data bus WRITE_DATA are divided into 8-bit data from the highest order, input through the selectors S 3   d  and S 3   a  to the data inputs D in the order of the memories M 3  and M 0 , and stored at No. n in the memory M 3  and at No. n+1 in the memory M 0 .  
         [0115]     If the data width of the write data is 8 bits, WD_LENGTH is “0” (decimal number). In this case, all the outputs Y 1  to Y 3  of the decoder  12  are “0”. Therefore, since the output /Y 3  is “0” and the outputs /Y 0  to /Y 2  are “1” in the selector S 1 , the memory M 3  becomes writable and the memories M 0  to M 2  become unwritable. As a result, the high-order 8-bit data on the write data bus WRITE_DATA are input through the selector S 3   d  to the data input D of the memory M 3  and stored at No. n.  
         [0116]     The memory control circuit  1 ,  1   a  of the embodiment of the present invention has been described as above. The memory control circuit  1 ,  1   a  can store various data with different data widths without generating invalid data on a memory. That is, the various data with different data widths can be read and write without deteriorating the usage efficiency of the memory. Since processes of packing and unpacking data are not needed before writing data into the memory or after reading data from the memory, a processing load is not increased.  
         [0117]     The above embodiment is for the purpose of facilitating the understanding of the present invention and does not limit the interpretation of the present invention. The present invention may be changed/altered without departing from the spirit thereof and the present invention includes the equivalents thereof.  
         [0118]     Although a memory storing the beginning of data is selected by using the low-order j bits of the A-bit address in the embodiment, the present invention is not limited to the low-order j bits, and the high-order j bits or discontinuously selected j bits can be used.