Abstract:
A method is provided for testing a non-programmable non-volatile memory which does not require the writing or erasing of any cells and permits the testing of all normal memory cells. Testing occurs from the device I/O pins and is useful in cases where EPROM memory cells have been bulk erased and placed within an ultraviolet-opaque package. The non-volatile memory is of the type having memory banks of rows and columns. Each bank must have address decoders and means for changing addresses between banks. A separate auxiliary cell or row of cells in a state different from the non-programmed state is provided. An address is supplied for the auxiliary cells and then for the normal cells and the interval between addressing the normal cells and the appearance of an output signal is measured and compared with a predetermined fixed limit. If the limit is exceeded, the address is identified as that of a weak cell whose speed does not meet product specifications. In suitably equipped memories, the addresses of weak cells can be recorded and redundant cell groups substituted as replacements.

Description:
DESCRIPTION 
     1. Technical Field 
     The present invention relates to methods for testing memory cells particularly in non-volatile memories such as EPROM&#39;s. 
     2. Background Art 
     Under certain manufacturing procedures it is often necessary to test an EPROM after it has been bulk erased and sealed in a UV-opaque package for shipment from the factory. The unprogrammed EPROM is difficult to test since programming is to be avoided. 
     A variety of test approaches have been proposed, most requiring additional memory cells or cell groups which are not part of the regular memory array and which can be programmed for limited testing of circuits shared with normal memory cells, i.e. a statistical sampling method. U.S. Pat. Nos. 4,920,515 and 4,862,418 are recent examples of this approach. Another partial solution has been the addition of circuits used to measure thresholds of normal memory cells without causing permanent change of state. This approach is exemplified by the teachings of U.S. Pat. Nos. 4,956,816, 4,779,272 and 4,393,475. Though leakage current and stray capacitance can be monitored by such techniques, additional circuits are needed and the assurance of a completely tested memory cell is lacking. 
     Doyle, in U.S. Pat. No 5,031,152 places a programmable latch at the output of a non-volatile memory cell, programs the latch, and allows the erased memory cell to reset the latch thereby demonstrating an ability to perform that part of the memory cell&#39;s task. But even the Doyle test circuit requires the addition of at least one circuit per sense amplifier. 
     One particular problem arises when it is desired to test the read access time for each EPROM in the array, to achieve higher reliability than in the statistical approach. After a first EPROM transistor in a LOW state is accessed, the read access time is the time delay in which the memory output follows the access request. When all of the transistors are LOW, there is ambiguity in determining this time delay. 
     What is needed is a method for testing the operability and read access delay time of normal memory cells without the addition of a large number of throwaway memory cells or special testing circuits. 
     It is an object of the present invention to provide a method for testing the normal memory cells of a non-volatile memory without writing or erasing any cell, without adding a large number of throwaway cells or cell groups, and by adding a minimum of additional circuitry. 
     It is a further object of this invention to provide a method for testing all normal cells and cell groups for both operability and for speed. 
     SUMMARY OF THE INVENTION 
     The above objects have been met by a method which provides a non-volatile memory having rows and columns of memory cells in a first memory state, an auxiliary transistor cell or row or bank or dummy cell in a second memory state, distinguishable from the first state, and at least one sense amplifier providing a memory output. Each memory cell in the first state is associated with a time delay between the cell&#39;s being addressed while in the first state and the cell&#39;s producing a memory output. The memory output of an addressed cell in the first state is a first logic level. The memory output when addressing the auxiliary cell, row, bank or dummy cell is a second logic level. Memory cells are tested by first addressing the alternate cell so that memory output is at the second logic level. Then a cell or row or column in the main array is addressed and the delay from enabling to appearance of the first logic level at the memory output is measured. The measurement is compared with a limit representing a maximum acceptable delay. If the limit is exceeded, the address is recorded and identified as a weak cell. In this manner it is possible to test one hundred percent of the normal memory cells in an efficient manner. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing an apparatus for the practiced the present invention. 
     FIG. 2 is a waveform diagram showing a portion of the operation of the apparatus of FIG. 1. 
     FIG. 3 is a block diagram of a second embodiment of the invention of FIG. 1. 
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     With reference to FIG. 1 there is shown non-volatile memory 10, upon which may be practiced the present invention. Memory 10 has a memory bank 12 having rows and columns of addressable memory cells, of which cell 26 is an example. Memory 10 has at least one sense amplifier 16 producing a signal OUT on memory output line 18. Memory 10 receives ADDRESS signals on lines 20. These are connected as inputs to an address decoder 14 for producing a plurality of row select signals, an example of which is shown on line 22, and a plurality of column select signals, as for example the signal on line 24. These individual select signals are used to address predetermined rows and columns of normal memory cells. Address decoder 14 receives an enable input from inverter 30 in response to a TEST signal on input line 28. A selected cell, such as cell 26, produces an output which is amplified by sense amplifier 16, producing the output signal OUT on memory output line 18. 
     When address decoder 14 addresses an alternate cell, such as a dummy cell, not shown, an output signal OUT will be at a second logic level. When an address is applied to address decoder 14 and the input signal TEST is negated, the address decoder is enabled and select signals such as those on line 22 and 24 are generated selecting a cell to be tested, such as cell 26 of FIG. 1. All the normal memory cells, such as cell 26, are in a first state. When memory cells in a first state are selected, after an interval of time output signal OUT will be at a first logic level. The length of this interval is inversely proportional to a time delay of the selected cell. If the resulting interval is less than or equal to a predetermined fixed limit, the cell is said to have passed its test. If, on the other hand, the resulting interval is greater than the fixed limit, the cell has failed its test and the address which resulted in the cell&#39;s selection is identified as a weak cell--the address itself is referred to as the weak cell even though it is technically the address of a weak cell. In memories which are equipped with means for doing so, the address of a weak cell is recorded and a redundant row or column substituted in its place. 
     FIG. 2 shows several signal waveforms associated with the practice of the method of the present invention upon the apparatus of FIG. 1. The vertical axis of the diagram is used to represent a logic level for each of the three waveforms. The horizontal axis is used to represent time which increases from left to right. The top waveform represents the input signal TEST of FIG. 1. Initially shown at a HIGH logic level 30, it switches at time t 0 , depicted by falling waveform 32, to a LOW logic level 34 at which level it remains. The middle waveform represents an input to sense amplifier 16 of FIG. 1. The signal SA begins at a LOW logic level 36 and, after an interval of time, begins to rise passing through a switching threshold 38 at time t 1 , continuing to rise to a HIGH logic level 40 at which it remains. The bottom waveform represents output signal OUT of FIG. 1. It is shown at the left side of FIG. 2 at a false logic level 42. At time t 1  it changes level at transition 44 and thereafter remains at a true logic level 46. 
     The waveforms depicted in FIG. 2 are related to one another by the behavior of elements of memory 10 during an interval beginning just before input signal TEST goes LOW at t 0 , initiating a memory cell selection cycle, and continuing beyond the end of the cycle at time t 1 . When TEST changes from true to false at t 0 , address decoder 14 of FIG. 1 begins a process of decoding an address, ultimately producing, in the example of FIG. 1, select signals on lines 22 and 24. The simultaneous appearance of select signals on these two lines results in the selection of cell 26 of FIG. 1. At a point in time intermediate between time t 0  and time t 1 , a signal SA at the input to sense amplifier 16 of FIG. 1 begins to rise from a LOW level 36 toward a HIGH level 40. At a level 38 of signal SA which corresponds to a switching threshold of sense amplifier 16, the output of the sense amplifier, OUT, will switch from a previously LOW level 42 to a HIGH level 46 thereby producing an output on line 18 of FIG. 1. 
     If the interval of time between t 0  and t 1  is less than or equal to the predetermined fixed limit, cell 26 will have passed its test. If on the other hand the above described interval of time exceeds the fixed limit, the address which resulted in the selection of cell 26 will be identified as a weak cell. By repeating this process with each of the cells or cell groups of memory bank 12 of FIG. 1, all the cells can be tested without a need to write into any normal or dummy cell or to erase any cell. 
     An exemplary testing method includes the following steps: (1) providing an apparatus suitable for the practice of the method such as that depicted in FIG. 1 and described above; (2) disabling addressing--in the example of FIG. 1 by asserting the TEST signal; (3) applying an address to the address decoder--in the present example by applying the address to the ADDRESS lines 20 of the apparatus of FIG. 1; (4) enabling address decoding--in the present example by negating the TEST signal; (5) measuring the length of the interval from the enabling of address decoding to the time of the appearance of an output--in the present example, measuring from time t 0  to the appearance of a true logic level at signal OUT at time t 1  ; (6) comparing the resulting measurement with the predetermined fixed limit and if the measurement is less than or equal to the limit, concluding that the cell has passed the test, but if the measurement exceeds the limit, declaring the address of the cell as a weak cell. 
     The validity of a test of this type arises from the fact that the ability of an addressed cell, previously in a first state, to produce the signal SA of FIG. 2 at the input to sense amplifier 16 of FIG. 1, resulting in an output OUT on line 18 of FIG. 1 within the predetermined fixed limit provides an acceptable assurance that the cell can be read at a speed guaranteed by the device specifications. Further, the testing method allows the testing of all the memory cells or cell groups without the addition of apparatus beyond that needed to disable and enable address decoding. 
     FIG. 3 is a block diagram of a second apparatus upon which the present invention may be practiced. Non-volatile memory 50 includes at least two memory banks 52 and 54. Each memory bank has its own address decoder 60 and 62, and at least one sense amplifier 68 and 80. The outputs of each sense amplifier are connected to separate data inputs of a selector 56 whose output is controlled by a select signal generated by, for example exclusive-OR gate 76. The selector output provides memory output signal OUT on line 58. The address decoders 60 and 62 for each memory bank receive all the address signals except the most significant address signal on input lines 64. These signals are referred to as the LSB&#39;s to indicate that they do not include the most significant bit of the address. The address signal corresponding to the most significant address bit is referred to as the MSB and is received on input line 66. Signal MSB is applied directly to the enable input of address decoder 62 for the second memory bank 54. Signal MSB is inverted by inverter 74 and the resulting signal is applied to the enable input of address decoder 60 for the first memory bank 52. With such a connection, the first memory bank 52 will respond to addresses for which the MSB is a 0 while the second memory bank 54 will respond to addresses for which the MSB is a 1. Thus for example, if each memory bank is capable of responding to 1024 different addresses, the first memory bank 52 will respond to addresses 0 through 1023 while the second memory bank 54 will respond to addresses 1024 through 2047. The exclusive-OR gate 76, used to select the sense amplifier whose output will provide output signal OUT on line 58, receives inputs from MSB and an input signal TEST received on input line 84. In normal memory operation, TEST remains at a LOW logic level or line 84 simply remains unconnected. Under these conditions, the output of gate 76 is equal to the logic level of MSB. When the logic level of MSB is LOW, the output 78 of sense amplifier 68 is selected to provide output signal OUT. This selection corresponds to the fact that when the logic level of MSB is LOW, address decoder 60 is enabled producing row and column select signal 70 to the first memory bank 52. Address decoder 62 is disabled. Alternatively, when the logic level of MSB is HIGH, address decoder 60 is disabled and address decoder 62 is enabled generating row and column select signals 72 to the second memory bank 54. The output 82 of sense amplifier 80 is selected to produce the output signal OUT on line 58. 
     Thus it can be seen that the MSB 66 can be used to enable or disable the output of the address decoders 60 and 62. But the disabling of one address decoder assures the enabling of the other address decoder as can be seen in FIG. 3. Under normal operating conditions, the selector 56 will select the output of the sense amplifier receiving an input from the memory bank whose address decoder is enabled. When the MSB 66 is being used to disable the address decoder for a given memory bank, we do not want the other memory bank, which is enabled, to produce an output on line 58. Therefore the TEST signal is provided to reverse the meaning of signal MSB as it relates to output selection. When the logic level of signal TEST is false, MSB selects the output of the memory bank whose address decoder is enabled. But when the logic level of signal TEST is HIGH, the meaning of MSB with respect to selection of memory output is inverted by the action of the exclusive-OR gate 76. While the logic level of TEST is HIGH, MSB selects the output of the second memory bank 54 when MSB is 0, and selects the output of the first memory bank 52 when MSB is 1. This result is the reverse of the normal action of MSB with respect to output selection, but is useful during testing as will be seen. 
     An application of the testing method of the present invention to the apparatus of FIG. 3 includes the following steps: (1) addressing a cell or cell group in one of the memory banks, assuming for this example the first memory bank 52 and applying the LSB&#39;s to lines 64; (2) changing address decoder 60 by making the logic level of signal MSB be 1; (3) overriding output selection to select the output of the first memory bank 52 by asserting input signal TEST; (4) making MSB a 0 to enable address decoder 60 and negating signal TEST to maintain selection of the output of the first memory bank 52; (5) measuring the length of the interval between the time of enabling the address decoder 60 and the appearance of an output on line 58; (6) comparing the length of the measured interval with a predetermined fixed limit and if the length is less than or equal to the limit, declaring that the addressed cell or cell group has passed the test, and if the length exceeds the limit, declaring address of the cell or cell group to be a weak cell; (7) repeating the steps from step (1) using a different address until testing of the first memory bank is completed, then reversing the logic level of signal MSB in all steps and repeating the steps from step (1) until testing of the second memory bank is completed. 
     The additional steps of recording addresses of weak cells and substituting redundant rows or columns as necessary are to be included for memories having such capabilities. 
     The details of address decoder enabling and output selection and override discussed above with respect to use of the invention with the apparatus of FIG. 3 can be easily modified for alternative addressing and selection configuration. The steps which are present in any application of the invention include: switching address decoding for the memory bank being tested; selecting the output of the memory bank being tested; addressing the cell or cell group to be tested; enabling the address decoding for the memory bank being tested; measuring the delay from address enabling to appearance of an output; comparing the measurement with the limit and taking appropriate follow up action.