Abstract:
A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level including conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. application Ser. No. 12/411,944, filed Mar. 26, 2009 entitled METHOD FOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT which application claims the priority benefit of French patent application number 08/52035, filed on Mar. 28, 2008, entitled METHOD FOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT, which is hereby incorporated by reference to the maximum extent allowable by law. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an integrated circuit and, more specifically, to a method for forming interconnection levels of an integrated circuit. 
         [0004]    2. Discussion of the Related Art 
         [0005]    Integrated circuits are comprised of a large number of electronic components which are formed in and on a semiconductor wafer. To properly connect these components, several interconnection levels form the upper portion of the integrated circuits. Each interconnection level comprises conductive tracks. Vias are formed to connect conductive tracks of different interconnection levels. 
         [0006]      FIG. 1  is a cross-section view of an example of the stack of several interconnection levels (N i , N i+1 , N i+2 . . . ) of an integrated circuit, level N 1  being the interconnection level closest to the electronic components. 
         [0007]    Each interconnection level N i  comprises a portion M i  in which are formed conductive tracks  10 , located above a portion V i  in which are formed vias  12  of contact between tracks of adjacent levels (currently, the vias of interconnection level N 1  are of a different nature than the vias of the other levels). In this drawing, the cross-section plane is such that the tracks are cut widthwise, so that conductive tracks  10  appear to be of same cross-section area as vias  12 . Vias  12  enable properly connecting two conductive tracks  10  located in two neighboring interconnection levels. As an example, tracks  10  and vias  12  may be made of copper. A dielectric material  14  separates tracks  10  from one another and vias  12  from one another. 
         [0008]    Nowadays, electronic components formed in integrated circuits operate at higher and higher frequencies. The frequency increase results in an increase in the values of the stray capacitances which form between the different conductive portions. Further, the continuous miniaturization of electronic components results in a decrease in the size of conductive tracks and a decrease in distances between tracks and between vias, which also increases the values of stray capacitances. Stray capacitances may disturb significantly the operation of a circuit. It is thus desired to decrease as much as possible such stray capacitances and, for this purpose, so-called “low-k” dielectric materials having very low relative permittivities, typically smaller than 3, are used between the different conductive portions. 
         [0009]    However, the porosity of dielectric material  14  poses various problems. Especially, the copper of conductive tracks  10  diffuses more easily into porous dielectric materials than into non-porous dielectric materials. To limit such a diffusion, it is particularly useful to form, between two neighboring interconnection levels, a layer  16  which, conventionally, stops the diffusion of conductive material from an interconnection level to the dielectric material of the upper interconnection level and which forms an etch stop layer. Vias  12  cross layer  16 . As an example, layer  16  may be made of silicon-carbon nitride (SiCN). It has also been provided to form a barrier layer (not shown) around the conductive tracks and the vias, this layer being made of a conductive material capable of avoiding the diffusion of the conductive material present in an interconnection level towards the porous dielectric material of the same interconnection level. This barrier layer is, for example, formed of tantalum and of tantalum nitride. 
         [0010]    Further, on manufacturing of the stack of interconnection levels, various etch and/or polishing and cleaning operations are carried out in liquid or gas phase. Contaminating products may thus penetrate into the pores of the porous dielectric material during these operations. This may cause an alteration of the porous material or an increase in its relative permittivity, which limits the advantage of using such a porous material. 
         [0011]    A way to restore the characteristics of the porous material comprises performing, after having formed each interconnection level, an anneal to eliminate the contaminating products present in the porous dielectric material. 
         [0012]      FIG. 2  is a cross-section view illustrating a stack of two interconnection levels N i  and N i+1 . This drawing illustrates the result obtained after having carried out a chem./mech. polishing step (CMP) on the structure and an anneal step aiming at eliminating the contaminating products present in interconnection level N i+1 . The conductive tracks of the two interconnection levels are shown lengthwise in cross-section view. 
         [0013]    Interconnection level N i  comprises conductive tracks  20  surrounded with a porous dielectric material  22 . The bottom and the walls of conductive tracks  20  are covered with a thin barrier layer  24  of a material avoiding the diffusion of conductive material from conductive tracks  20  to porous dielectric material  22 . A thin layer  26  of a material avoiding the diffusion of conductive material from conductive tracks  20  to interconnection level N i+1 , for example, made of SiCN, extends above interconnection level N i . Interconnection level N i+1 , which comprises conductive tracks  28  connected by vias  30  to conductive tracks  20  of interconnection level N i  is formed above thin layer  26 . A porous dielectric material  32  separates conductive tracks  28  from one another and vias  30  from one another. The walls and the bottom of conductive tracks  28  and of vias  30  are covered with a thin barrier layer  34  of a conductive material. Interconnection levels N i  and N i+1  may be obtained by different known methods. 
         [0014]    On forming of interconnection level N i+1 , the etch and/or polishing and cleaning steps cause the contamination of porous dielectric material  32 . An additional step, where an anneal of the structure is performed to enable evaporation of the contaminants, is then carried out. As an example, this anneal step may be carried out at a temperature of approximately 300° C. for approximately 30 minutes. This anneal needs to be performed before deposition of a layer homologous to layer  26  which would create a barrier against the evaporation of contaminants. 
         [0015]    In  FIG. 2 , arrows  36  illustrate the evacuation, during the anneal, of the contaminating products present in porous dielectric material  32 . Although the anneal enables eliminating the contaminating products present in porous dielectric material  32 , it should be noted that it also causes the expansion of the conductive material of conductive tracks  28 . This expansion modifies the upper surface of conductive tracks  28  and makes it rough. Problems, for example, in terms of reliability, may then arise when another interconnection level is desired to be formed on the upper surface of interconnection level N i+1 . Further, since porous dielectric material  32  is not protected on its upper surface, it is contaminated again by the contact with the air, especially by water vapor, when the structure is taken out of the furnace in which the anneal has been performed. This recontamination is illustrated in  FIG. 2  by arrows  38 . 
         [0016]    To limit the expansion of the conductive material, the anneal temperature may be decreased. However, a decrease in the anneal temperature causes an increase in the duration of this anneal and decreases its efficiency. 
       SUMMARY OF THE INVENTION 
       [0017]    At least one embodiment of the present invention aims at providing a method for forming interconnection levels of an integrated circuit enabling avoiding at least some of the problems of prior art methods. 
         [0018]    Thus, an embodiment of the present invention provides a method for forming interconnection levels of an integrated circuit, comprising the steps of: 
         [0019]    (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; 
         [0020]    (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; 
         [0021]    (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and 
         [0022]    (d) annealing the structure. 
         [0023]    According to an embodiment of the present invention, an anneal step is performed before each repetition at step (c). 
         [0024]    According to an embodiment of the present invention, step (a) of formation of an interconnection level comprises the steps of: 
         [0025]    forming a layer of a porous dielectric material; 
         [0026]    forming an oxide layer, then a titanium nitride layer on the layer of porous dielectric material; 
         [0027]    forming openings in the titanium nitride layer and in an upper portion of the oxide layer at the level of the desired conductive tracks; 
         [0028]    forming holes in the oxide layer and in an upper portion of the layer of porous dielectric material at the level of the desired vias; 
         [0029]    etching, outside the areas covered with the titanium nitride layer, until the bottom of the holes reaches the conductive tracks of the lower interconnection level; 
         [0030]    forming a conductive material in the etched portion; and 
         [0031]    removing the materials located above the layer of porous dielectric material. 
         [0032]    According to an embodiment of the present invention, the step of forming holes and the step of etching outside the areas covered by the titanium nitride layer are etch steps in the presence of argon and of C 4 F 8 . 
         [0033]    According to an embodiment of the present invention, the removal of the materials located above the layer of porous dielectric material is performed by chem./mech. polishing (CMP). 
         [0034]    According to an embodiment of the present invention, the layers of non porous insulating material are made of silicon-carbon nitride (SiCN) and the conductive tracks and the vias are made of copper. 
         [0035]    An embodiment of the present invention provides an integrated circuit comprising a stack of interconnection levels, each interconnection level comprising conductive tracks, conductive tracks of different interconnection levels capable of being connected by vias, the conductive tracks and the vias being separated by porous dielectric materials, non-porous insulating layers crossed by the vias being formed on the different interconnection levels, said non-porous insulating layers comprising openings located on portions of porous dielectric materials. 
         [0036]    According to an embodiment of the present invention, the porous dielectric materials have thicknesses ranging between 100 and 250 nm. 
         [0037]    According to an embodiment of the present invention, the layers of non-porous insulating material are made of silicon-carbon nitride (SiCN) and the conductive tracks and the vias are made of copper. 
         [0038]    According to an embodiment of the present invention, the openings in the non-porous insulating layers have dimensions greater than 70 nm. 
         [0039]    The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0040]      FIG. 1 , previously described, is a cross-section view of several interconnection levels of an integrated circuit; 
           [0041]      FIG. 2 , previously described, illustrates the result obtained after having performed an anneal on an interconnection level N i+1 ; and 
           [0042]      FIGS. 3A to 3I  are cross-section views illustrating steps of a method for manufacturing a stacking of interconnection levels according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0043]    For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of integrated circuits, the various drawings are not to scale. 
         [0044]      FIGS. 3A to 3I  are cross-section views illustrating results of steps of a method for manufacturing a stack of interconnection levels according to an embodiment of the present invention.  FIGS. 3A to 3G  are drawn along a first cross-section plane and  FIGS. 3H and 31  along a second cross-section plane. 
         [0045]    In  FIG. 3A , it is started from a structure in which an interconnection level N i  has already been formed. Interconnection level N i  comprises conductive tracks  40 , two of these tracks being shown lengthwise in cross-section view in  FIG. 3A . As an example, conductive tracks  40  may be made of copper. Vias (not shown) may also be formed to connect conductive tracks  40  to tracks of lower level. Conductive tracks  40  are separated by a porous dielectric material  42 . The walls and the bottom of conductive tracks  40  are covered with a thin barrier layer  44  of a conductive material which prevents the diffusion of copper from conductive tracks  40  to porous dielectric material  42 . Above interconnection level N i  is formed a non-porous thin insulating layer  46 , for example, made of SiCN, which prevents the diffusion of copper from tracks  40  to interconnection level N i+1  which will be formed above insulating layer  46 . 
         [0046]    According to an aspect of the present invention, non-porous insulating layer  46  comprises openings  48  located above portions of porous dielectric material  42 , a single one of openings  48  being shown in  FIG. 3A . Openings  48  are formed above portions of interconnection level N i  having a low density of conductive tracks  40 . 
         [0047]    At the step illustrated in  FIG. 3B , a thicker layer of porous dielectric material  50  has been formed on thin non-porous insulating layer  46 . As an example, layer  50  of porous dielectric material may be obtained by introducing a pore-forming agent into a thick layer of non-porous dielectric material, then reacting the pore-forming agent, for example, by anneal, to eliminate the pore-forming agent and form the pores of the porous dielectric material. On top of layer  50  of porous dielectric material is formed a stack of two layers  52  and  54  which behave as masks in subsequent steps. As an example, layer  52  is a deposited silicon oxide layer and layer  54  is a titanium nitride layer (TiN). 
         [0048]    At the step illustrated in  FIG. 3C , openings  56  have been formed in titanium nitride layer  54 , these openings extending slightly into oxide layer  52 . The contour of openings  56  defines the contour of the conductive tracks which will be formed in interconnection level N i+1 . As an example, openings  56  may be formed by depositing a resist on titanium nitride layer  54 , by appropriately insolating and etching this resist, and by etching layers  52  and  54 . Layer  52  is only partially etched to avoid any direct contact between the resist and porous dielectric material  50  during the next step. 
         [0049]    At the step illustrated in  FIG. 3D , holes  58  which cross oxide layer  52  and an upper portion of layer  50  of porous dielectric material have been formed in openings  56 . Holes  58  define the contour of the vias which will be formed in interconnection layer N i+1 . Holes  58  may be obtained, by means of an adapted mask, by a physico-chemical etching performed in the presence of argon and of C 4 F 8 . Further, a hydrofluoric acid (HF) cleaning step is carried out after the etching. During the etching and the cleaning, contaminating products (for example, fluorine) penetrate into the pores of porous dielectric material  50 , as illustrated in  FIG. 3D  by arrows  60 . 
         [0050]    At the step illustrated in  FIG. 3E , an etching of the portion of oxide layer  52  and of layer  50  of porous dielectric material which are not protected by titanium nitride layer  54  has been performed. As an example, this etching may again be a physico-chemical etching in the presence of argon and of C 4 F 8 , followed by a cleaning with hydrofluoric acid. This etch step enables forming the contour of the conductive tracks and of the vias of interconnection level N i+1 . It is performed so that holes  58  cross thin SiCN layer  46  and that they reach conductive tracks  40  of interconnection level N i . In the same way as in the previous etch step, contaminating products penetrate into porous dielectric material  50 , during the etching and the cleaning, as indicated by arrows  62  in  FIG. 3E . 
         [0051]    At the step illustrated in  FIG. 3F , the space created in the previous etch step has been filled with a conductive material to form conductive tracks  64  and vias  65  of interconnection level N i+1 . The conductive material of conductive tracks  64  and of vias  65  may be copper, and the metallization is carried out so that the copper fills the spaces contacting conductive track inductive material avoiding the diffusion of copper from conductive layers  64  and vias  65  to the neighboring porous dielectric material  50  may be formed before the metallization. 
         [0052]    At the step illustrated in  FIG. 3G , a chem./mech. polishing (CMP) for removing the excess copper and tantalum nitride  66  located above layer  50  of porous dielectric material, as well as titanium nitride layer  54  and oxide layer  52 , has been carried out. In the same way as in the etch steps, during the polishing step and the subsequent cleaning step, contaminating products may penetrate into porous dielectric material  50 , as illustrated in  FIG. 3G  by arrows  68 . 
         [0053]      FIGS. 3H to 3I  illustrate subsequent steps of the manufacturing method according to an embodiment of the present invention, in a cross-section plane different from that of  FIGS. 3A to 3G . In these drawings, all conductive tracks appear lengthwise in cross-section view and the different barrier layers (especially  44  and  66 ) have not been shown for the simplification. 
         [0054]      FIG. 3H  illustrates a structure substantially identical to that of  FIG. 3G . In this drawing, interconnection levels N i  and N i+1  comprise several conductive tracks  40 ,  64  and several vias  65 . Above interconnection level N i+1  is formed a non-porous insulating layer  70 , for example, made of SiCN. 
         [0055]    According to an aspect of the present invention, non-porous insulating layer  70  comprises openings  72  above portions of porous dielectric material  50 . In  FIG. 3H , a single one of openings  72  is shown. Openings  72  are formed above portions of interconnection level N i+1  having a low density of conductive tracks  64 . 
         [0056]    At the step of  FIG. 3I , an interconnection level N i+2  has been formed on thin SiCN layer  70 . Interconnection level N i+2  may be formed in the same way as interconnection level N i+1 . Interconnection level N i+2  comprises conductive tracks  74  and vias  76 , the tracks and vias being separated by a porous dielectric material  78 . 
         [0057]    On top of interconnection level N i+2  is formed a thin non-porous insulating layer  80 , for example, made of SiCN, which comprises openings  82  above portions of porous dielectric material  78 . In  FIG. 3I , a single one of openings  82  has been shown. In the same way as for openings  48  and  72 , openings  82  are formed above portions of interconnection level N i+2  with a low density of conductive tracks. 
         [0058]    Preferably, after the forming of each opening  48 ,  72 , and  82  in SiCN layers  46 ,  70 , and  80  on interconnection levels N i , N i+i , and N i+2 , an anneal of the structure enabling evaporation of the contaminating products present in the porous dielectric materials, respectively  42 ,  50  and  78 , of these levels, is performed. 
         [0059]    In  FIG. 3I , the circulation of contaminating products during an anneal intended to eliminate contaminating products from interconnection level N i+2  has been shown. The contaminating products present in layer  78  of porous dielectric material tend to evaporate and to come out through opening  82 , as shown by arrows  84 . It should be noted that the contaminating products go round vias  76  of interconnection level N i+2 . Further, this anneal also allows for contaminating products present in the lower levels to migrate upwards in the structure, from level to level, via openings  48 ,  72  formed in non-porous insulating layers  46 ,  70 , as shown by arrows  86 , and to escape from the structure through openings  82  of non-porous insulating layer  80 . 
         [0060]    Non-porous insulating layers  46 ,  70 , and  80  covering conductive tracks  40 ,  64 , and  74  prevent the expansion of the conductive material of these tracks. This enables annealing at temperatures higher than those currently used and thus enables better evacuation of contaminating products. Further, the recontamination of the porous dielectric material after the anneal steps only occurs in regions with a low density of conductive materials, which does not increase stray capacitances in remote regions with a high density of conductive tracks. 
         [0061]    Non-porous insulating layers  46 ,  70 , and  80  may be made of any non-porous insulating material, but they will preferably be made of silicon-carbon nitride SiCN, this material stopping the passing of contaminating products and also avoiding diffusion of the material of conductive tracks  40 ,  64 , and  74  towards the porous dielectric material of the upper levels. 
         [0062]    As an example, layers  42 ,  50 ,  78  of porous dielectric material have thicknesses ranging between 100 and 250 nm. As an example also, the openings may have dimensions, sides or diameters greater than 70 nm. 
         [0063]    Specific embodiments of the present invention have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, it should be understood that the anneal steps may be carried out after having formed several interconnection levels. Two interconnection levels or more may for example be formed before performing an anneal to evacuate the contaminating products from these two levels. A longer anneal step may also be provided once all interconnection levels have been formed to enable evaporation of the contaminating products remaining in the different interconnection levels. 
         [0064]    Openings  48 ,  72 , and  82  may be formed above one another or in shifted fashion, as shown in  FIG. 3I . 
         [0065]    Further, a specific method for forming an interconnection level comprising tracks and vias has been described, in which the conductive material of the tracks and vias is formed in a single step. It should be understood that the tracks and vias of each interconnection level may be formed separately and by any known method. 
         [0066]    As an example, porous dielectric material  42 ,  50 ,  78 , may be “BDIIx”, a material sold by Applied Materials. 
         [0067]    Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. 
         [0068]    Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.