Abstract:
An NMOS field effect transistor may be utilized to drive the memory cell of a phase change memory. As a result, the leakage current may be reduced dramatically.

Description:
BACKGROUND  
         [0001]    This invention relates generally to electronic memories and particularly to electronic memories that use phase change material.  
           [0002]    Phase change materials may exhibit at least two different states. The states may be called the amorphous and crystalline states. Transitions between these states may be selectively initiated. The states may be distinguished because the amorphous state generally exhibits higher resistivity than the crystalline state. The amorphous state involves a more disordered atomic structure. Generally any phase change material may be utilized. In some embodiments, however, thin-film chalcogenide alloy materials may be particularly suitable.  
           [0003]    The phase change may be induced reversibly. Therefore, the memory may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter, or vice versa, in response to temperature changes. In effect, each memory cell may be thought of as a programmable resistor, which reversibly changes between higher and lower resistance states. The phase change may be induced by resistive heating.  
           [0004]    Existing phase change memories have leakage currents. Thus, there is a need to reduce the leakage current of existing phase change memories. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    [0005]FIG. 1 is a schematic depiction of one embodiment of the present invention; and  
         [0006]    [0006]FIG. 2 is a system diagram of one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0007]    Referring to FIG. 1, a phase change memory array  10  may include a plurality of conductive lines or columns  12 , including the columns  12   a  through  12   c , and a plurality of rows  14  including the rows  14   a  through  14   c . At the intersection of each row  14  and each column  12  is a memory element or memory cell  16 .  
         [0008]    Each cell  16  may include a phase change memory element  18 , a resistor  20 , and an n-type metal oxide semiconductor (NMOS) select gate  22 . Examples of phase change memory material include, but are not limited to, chalcogenide element(s) compositions of the class of tellerium-germanium-antimony (TexGeySbz) material or GeSbTe alloys, although the scope of the present invention is not limited to just these. Alternatively, another phase change material may be used whose electrical properties (e.g., resistance, capacitance, etc.) may be changed through the application of energy such as, for example, light, heat, or electrical current. In this particular embodiment, chalcogenide layer  10  may have a thickness ranging from about 300 to 600 Å. When appropriate potential is applied to a conductive line such as a word line  14 , the NMOS select gate  22  may be turned on, allowing a connection for current flow through a ground connection that includes the memory element  18 . The memory element  18  may be coupled to a word line  12 .  
         [0009]    The phase change memory element  18  may be heated to a high temperature to amorphisize the material and reset the memory element (e.g., program  0 ). Heating the volume of memory material to a lower crystallization temperature crystallizes the material and sets the memory element (e.g., program  1 ). It is to be appreciated that the association of reset and set with amorphous and crystalline material, respectively, is a convention and that at least an opposite convention may be adopted. It is also to be appreciated from this example that the volume of memory material can be partially set or reset by varying the current flow and duration through the volume of memory material.  
         [0010]    In the reset state when the phase change memory element  18  is in the amorphous or a less conductive state, the bitline  12   b , which may be considered in this example the selected bitline, provides the reset current, and the bitlines  12   a  and  12   c  adjacent thereto have zero volts in one embodiment. At the same time, assuming the cell  16   e  is the selected cell, the word line  14   b  has the potential V dd  and the adjacent word lines  14   a  and  14   c  have zero volts.  
         [0011]    Similarly, in the set state, when the phase change material is in the more conductive state, the bitline  12   b  carries the set current while the adjacent bitlines  12   a  and  12   c  carry zero volts. The word line  14   b  with the selected cell  16   e  has the voltage V dd  while the adjacent word lines  14   a  and  14   c  may be zero volts in one embodiment. The voltage V dd  may be a supply voltage.  
         [0012]    To read the memory cell, the read current occurs on the selected bitline  12   b  while the adjacent bitlines have zero volts. The selected word line  14   b  has the potential V dd  and the adjacent word lines  14   a  and  14   c  have zero volts.  
         [0013]    Thus, in one embodiment of the present invention, the memory array  10  has a dedicated ground. However, the biasing may be reversed, but in such case, the entire array  10  is biased.  
         [0014]    The isolation between adjacent word lines along the adjacent bitlines  12  may be provided by a trench isolation or a polysilicon field plate isolation, as two examples. A source line runs parallel to each word line  14  and is shared between two adjacent word lines  14 . Each source line may be contacted periodically every four, eight, or sixteen bits to the metal ground line, depending on how much voltage drop along the source line is acceptable.  
         [0015]    Generally, the select device  22  current drive may match or exceed the reset current of the phase change memory cell  18 .  
         [0016]    However, the word lines  14  do not need metal straps because they generally do not carry large current in some embodiments. Generally, a single metal layer will be sufficient in some embodiments.  
         [0017]    In some embodiments, a processor-based system may be implemented which includes a processor  50  coupled to a bus  52 . The bus  52 , in turn, may be coupled to the phase change memory  10  and a wireless interface  54  in one embodiment. The processor  50  may be a general purpose processor or a digital signal processor, to mention two examples.  
         [0018]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.