Abstract:
The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device, and in particular, relates to a semiconductor device having a high voltage MOSFET with very low on-resistance and method for fabricating the same. 
         [0003]    2. Description of the Related Art 
         [0004]    Bipolar-CMOS-LDMOSs (BCDs) have been widely used in power management integrated circuit (PMIC) applications. BCD technology integrates bipolar, complementary metal-oxide-semiconductor (CMOS) and laterally diffused metal-oxide-semiconductor (LDMOS) technology into one chip. In a BCD device, a bipolar device is used to drive high currents, a CMOS provides low power consumption for digital circuits, and a LDMOS device provides high voltage (HV) handling capabilities. 
         [0005]    LDMOS devices are widely used in day to-day applications. On-resistance is an important factor that is directly proportional to the power consumption of an LDMOS device. As the demand for power savings and better performance of electronic devices increase, manufacturers have continuously sought to reduce the leakage and on-resistance (R on ) of LDMOS devices. However, the reduction of on-resistance is closely related to the high off-state breakdown voltage. Specifically, reducing the on-resistance leads to a substantial drop of the high off-state breakdown voltage. Thus, a conventional LDMOS device is able to deliver a high off-state breakdown voltage but fails to provide low on-resistance. 
         [0006]    An LDMOS device includes a drift region, and a body region. It has been observed that the on-resistance of the conventional LDMOS device decreases when the dopant concentration of the drift region increases. However, the high off-state breakdown voltage of the LDMOS decreases as the doping concentration increases. 
         [0007]    Thus, an improved semiconductor device and a method for fabricating the same are needed. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    An exemplary embodiment of a semiconductor device includes: semiconductor device, comprising: a substrate having a first conductivity type, comprising: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type. 
         [0009]    Another exemplary embodiment, wherein the body and drift regions are formed in an epitaxial layer of the substrate and the gate dielectric layer is formed over the epitaxial layer of the substrate. 
         [0010]    An exemplary embodiment of a method for fabricating a semiconductor device includes: providing a semiconductor substrate of a first conductivity type; implanting a dopant of a first conductivity type into the substrate to define a body region; implanting a dopant of a second conductivity type, into the substrate to define a drift region adjacent to the body region; forming a multiple reduced surface field (RESURF) structure in the drift region; forming a gate dielectric layer over the substrate; forming a source region in the body region; and forming a drain region in the drift region; wherein the first conductivity type is opposite to the second conductivity type. 
         [0011]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0013]      FIG. 1  is cross-sectional view of a conventional LDMOS device; 
           [0014]      FIG. 2   a - 2   c  are schematic views showing a LDMOS device in accordance with embodiments of the present disclosure; 
           [0015]      FIG. 3   a - 3   b  illustrate a method for forming a LDMOS device in accordance with embodiments of the present disclosure; 
           [0016]      FIG. 4   a - 4   b  illustrate a method for forming a multiple reduced surface field (RESURF) structure of a LDMOS device in accordance with embodiments of the present disclosure; 
           [0017]      FIG. 5   a - 5   h  illustrate various configurations of a LDMOS device with a RESURF structure in accordance with different embodiments of the present disclosure; and 
           [0018]      FIGS. 5   a - 5   e  illustrate schematic views showing a LDMOS device in accordance with embodiments of the present disclosure; 
           [0019]      FIGS. 6   a - 6   d  illustrate a method for forming the step gate dielectric structure in accordance with an exemplary embodiment; 
           [0020]      FIGS. 7   a - 7   d  illustrate a method for forming the step gate dielectric structure in accordance with another exemplary embodiment; 
           [0021]      FIG. 8  illustrate a LDMOS device having a multiple RESURF structure and a step gate dielectric structure in accordance with an exemplary embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0022]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0023]    The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice the invention. 
         [0024]    Referring to  FIG. 1 , a cross-sectional view of a conventional LDMOS device  100  is illustrated. The LDMOS device  100  comprises a substrate  110  having, a body region  122  and a drift region  124  formed in the substrate  110 . The substrate  110  further comprises a plurality of shallow trench isolations (STIs)  130  formed therein. In the LDMOS device  100 , the current from the source region  150  to the drain region  160  flows by a devious path as shown as the dotted line in  FIG. 1  due to the obstruction of the STI  130  in between the source and drain regions  150 ,  160 . The deviation of the current path results in a high on-resistance of the LDMOS device  100 . 
         [0025]      FIGS. 2   a - 5   e  illustrate a step-by-step procedure for fabricating a semiconductor device  200  in accordance with embodiments of the present disclosure. 
         [0026]      FIGS. 2   a - 2   d  illustrate the formation of a body region and a drift region of the semiconductor device  200  in accordance with an embodiments of the present disclosure. Referring to  FIG. 2   a , a substrate  210  having a first conductivity type is provided. The substrate  210  may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or the like. In some embodiments, the substrate  210  may have a first conductivity type of p-type, such as a boron doped substrate. In other embodiments, the substrate  210  may have a first conductivity type of n-type, such as a phosphor or arsenic substrate. Any other suitable substrates may also be used. 
         [0027]    Referring to  FIG. 2   b , a mask layer  20  is formed over the substrate  210 . The mask layer  20  may be a patterned photoresist layer or a hard mask layer such as a silicon nitride or a silicon oxynitride layer or the like. After the mask layer  20  is formed, a doping process  300  is performed to selectively dope a dopant of a first conductivity type, into the semiconductor substrate  210  to define a body region  212 . In some exemplary embodiments, the concentration of the substrate  210  may be greater than that of the body region  212 . For example, when the body region  212  is p-type, the substrate  210  may be heavily doped p-type (P+). The mask layer  20  is then removed after the body region  212  is formed. 
         [0028]    Referring to  FIG. 2   c , another mask layer  30  is formed over the substrate  210 . The mask layer  30  may be a patterned photoresist layer or a hard mask layer such as a silicon nitride or a silicon oxynitride layer or the like. A doping process  400  is performed to selectively dope a dopant of a second conductivity type, into the semiconductor substrate  210  to define a drift region  214 . In some embodiments, the second conductivity type is different from the first conductivity type. 
         [0029]    In some embodiments, the drift region  214  may be a wide area formed prior to the formation of the body region  212 . After the drift region  214  is formed, the body region  212  is formed in the drift region by an implantation process, as shown as  FIG. 3   a . 
         [0030]    In some embodiments, an epitaxial layer may be optionally formed over the substrate  210  and the body and drift regions are formed in the epitaxial. Referring to  FIG. 3   b , an epitaxial layer  220  of the first conductivity type is formed on the substrate  210 . Moreover, the semiconductor substrate  210  has a doping concentration larger than that of the epitaxial layer  220 . For example, when the first conductivity type is n-type, the semiconductor substrate  210  may be a heavily doped n-type (N+) semiconductor substrate  210 , while the epitaxial layer  220  may be a lightly doped n-type (N−) epitaxial layer. The epitaxial layer  220  may be formed by epitaxial growth to a thickness ranging from 3 um to 10 um. In such embodiments, the body region  222  and the drift region  224  are form in the epitaxial layer  220 . The formation body and drift regions  222  and  224  is similar to that of the body and drift regions  212  and  214 , and hence is not discussed herein to avoid repetition. 
         [0031]    After the body region  222  and the drift region  224  are formed, a procedure for forming a multiple reduced surface field (RESURF) structure, is then performed. 
         [0032]      FIGS. 4   a - 4   b  illustrate the formation of a multiple reduced surface field (RESURF) structure, in accordance with various embodiments of the present disclosure. Referring to  FIG. 3   a , a mask layer  40  is formed on the semiconductor substrate  210  (or the epitaxial layer  220  if exists) to expose an area to be defined as the multiple RESURF region. The mask layer  40  may be a patterned photoresist layer or a hard mask layer such as a silicon nitride or a silicon oxynitride layer or the like. A plurality of ion implantation processes  500  is then performed to form a multiple RESURF structure  230 . In some embodiments, the RESURF structure  230  is formed in the drift region  214  (or  224 ) Referring to  FIG. 4   b , after the multiple RESURF structure is formed, the mask layer  40  is removed and an annealing process is performed to activate the implanted ions. 
         [0033]    Various configurations of the RESURF structure  230  are illustrated in  FIGS. 5   a - 5   h  in accordance with exemplary embodiments of the present disclosure. Referring to  FIG. 5   a , a cross-sectional view of the RESURF structure  230  is illustrated in accordance with an exemplary embodiment of the present disclosure. The RESURF structure  230  is a multi-layered consisting of a plurality of first ion regions  230   a  and a plurality of second ion regions  230   b . The RESURF structure  230  is configured alternately, with the plurality of first ion regions  230   a  and the plurality of second ion regions  230   b  in a vertical direction. The conductivity types of the first and the second ion regions  230   a  and  230   b  are different from each other. In the embodiment, the conductivity type of the plurality of first ion regions  230   a  is the first conductivity type corresponding to the body region  222  and the conductivity type of the plurality of second ion regions  230   b  is the second conductivity type corresponding to the drift region  214 . In another embodiment, the conductivity type of the plurality of first ion regions  230   a  is the second conductivity type and the conductivity type of the plurality of second ion regions  230   b  is the first conductivity type. 
         [0034]    A cross-sectional view of the RESURF structure  230  in accordance with another exemplary embodiment of the present disclosure is illustrated in  FIG. 5   b . Referring to  FIG. 4   b , the RESURF structure  230  is a multi-layered structure consisting of a plurality of first ion regions  230   a  of the first conductivity type and a plurality of second ion regions  230   b  of the second conductivity type. The RESURF structure  230  is configured by alternating the plurality of first ion regions  230   a  and the plurality of second ion regions  230   b  in a first lateral direction x. The conductivity types of the first and the second ion regions  230   a  and  230   b  are different from each other. In the embodiment, the conductivity type of the plurality of first ion regions  230   a  is the first conductivity type corresponding to the body region  212  and the conductivity type of the plurality of second ion regions  230   b  is the second conductivity type corresponding to the drift region  214 . In another embodiment, the conductivity type of the plurality of first ion regions  230   a  is the second conductivity type and the conductivity type of the plurality of second ion regions  230   b  is the first conductivity type. 
         [0035]    Referring to  FIG. 5   c , a 3-dimensional perspective view of the RESURF structure  230  is illustrated in accordance with yet another exemplary embodiment of the present disclosure. The RESURF structure  230  is a multi-layered structure consisting of a plurality of first ion regions  230   a  and a plurality of second ion regions  230   b . The RESURF structure  230  is configured by alternating the plurality of first ion regions  230   a  and the plurality of second ion regions  230   b  in a second lateral direction y. The conductivity types of the first and the second ion regions  230   a  and  230   b  are different from each other. In the embodiment, the conductivity type of the plurality of first ion regions  230   a  is the first conductivity type corresponding to the body region  212  and the conductivity type of the plurality of second ion regions  230   b  is the second conductivity type corresponding to the drift region  214 . In another embodiment, the conductivity type of the plurality of first ion regions  230   a  is the second conductivity type and the conductivity type of the plurality of second ion regions  230   b  is the first conductivity type. 
         [0036]    Referring to  FIG. 5   d , a cross-sectional view of the RESURF structure  230  is illustrated in accordance with a further exemplary embodiment of the present disclosure. The RESURF structure  230  is a multi-layered structure formed by alternating first ion layers  232  and second ion layers  234 . The first ion layers  232  are formed of the plurality of first ion regions  230   a . In another embodiment, the first ion layers  232  may be formed of the plurality of second ion regions  230   b . The plurality of second ion layers  234  are composed of regions by alternating the plurality of first ion regions  230   a  and the plurality of second ion regions  230   b  in the first lateral direction x. The conductivity types of the first and the second ion regions  230   a  and  230   b  are different from each other. In the embodiment, the conductivity type of the plurality of first ion regions  230   a  is the first conductivity type corresponding to the body region  212  and the conductivity type of the plurality of second ion regions  230   b  is the second conductivity type corresponding to the drift region  214 . In yet another embodiment, the conductivity type of the plurality of first ion regions  230   a  is the second conductivity type and the conductivity type of the plurality of second ion regions  230   b  is the first conductivity type. 
         [0037]    In an embodiments, RESURF structure  230  is a multi-layered structure formed by alternating the plurality of first ion regions  230   a  and the plurality of second ion regions  230   b  in the lateral direction x as well as a vertical direction, as shown in  FIG. 5   e . The conductivity types of the first and the second ion regions  230   a  and  230   b  are different from each other. In the embodiment, the conductivity type of the plurality of first ion regions  230   a  is the first conductivity type corresponding to the body region  212  and the conductivity type of the plurality of second ion regions  230   b  is the second conductivity type corresponding to the drift region  214 . In another embodiment, the conductivity type of the plurality of first ion regions  230   a  is the second conductivity type and the conductivity type of the plurality of second ion regions  230   b  is the first conductivity type. 
         [0038]    Referring to  FIG. 5   f , a 3-dimensional perspective of the RESURF structure  230  is illustrated in accordance with an exemplary embodiment of the present disclosure. The RESURF structure  230  is a multi-layered structure formed by alternating first ion layers  232  and second ion layers  234  in the first lateral direction x. The first ion layers  232  are composed of regions formed by alternating the plurality of first ion regions  230   a  and the plurality of second ion regions  230   b  in the second lateral direction y. The plurality of second ion layers  234  are formed by implanting the plurality of first ion regions  230   a . In another embodiment, the plurality of second ion layers may be formed of the plurality of second ion regions  230   b . The conductivity types of the first and the second ion regions  230   a  and  230   b  are different from each other. In the embodiment, the conductivity type of the plurality of first ion regions  230   a  is the first conductivity type corresponding to the body region  212  and the conductivity type of the plurality of second ion regions  230   b  is the second conductivity type corresponding to the drift region  214 . In yet another embodiment, the conductivity type of the plurality of first ion regions  230   a  is the second conductivity type and the conductivity type of the plurality of second ion regions  230   b  is the first conductivity type. 
         [0039]      FIG. 5   g  shows a 3-dimensional perspective view of the RESURF structure  230  in accordance with an exemplary embodiment of the present disclosure. The RESURF structure  230  is a multi-layered structure formed by alternating first ion layers  232  and second ion layers  234  in the second lateral direction y. The first ion layers  232  are composed of regions formed by alternating the plurality of first ion regions  230   a  and the plurality of second ion regions  230   b  in the first lateral direction x. The plurality of second ion layers  234  are formed of the plurality of first ion regions  230   a . In another embodiment, the plurality of second ion layers  234  are formed of the plurality of second ion regions  230   b . The conductivity types of the first and the second ion regions  230   a  and  230   b  are different from each other. In the embodiment, the conductivity type of the plurality of first ion regions  230   a  is the first conductivity type corresponding to the body region  212  and the conductivity type of the plurality of second ion regions  230   b  is the second conductivity type corresponding to the drift region  214 . In yet another embodiment, the conductivity type of the plurality of first ion regions  230   a  is the second conductivity type and the conductivity type of the plurality of second ion regions  230   b  is the first conductivity type. 
         [0040]    In an embodiment, RESURF structure  230  is a structure formed by alternating the plurality of first ion regions  230   a  and the plurality of second ion regions  230   b  in the lateral direction y as well as a vertical direction, as shown in  FIG. 5   h . The conductivity types of the first and the second ion regions  230   a  and  230   b  are different from each other. In the embodiment, the conductivity type of the plurality of first ion regions  230   a  is the first conductivity type corresponding to the body region  212  and the conductivity type of the plurality of second ion regions  230   b  is the second conductivity type corresponding to the drift region  214 . In another embodiment, the conductivity type of the plurality of first ion regions  230   a  is the second conductivity type and the conductivity type of the plurality of second ion regions  230   b  is the first conductivity type. 
         [0041]    Although various configurations of the multiple RESURF structure  230  in accordance with embodiments are discussed, it should be understood, however, that the present invention is not limited to the configurations shown in  FIGS. 5   a - 5   h.  To the contrary, it is intended to cover various modifications and similar arrangements. For example, the number of the ion regions or layers of the multiple RESURF structure may be more or less than that of the RESURF structures  230  shown in  FIGS. 5   a - 5   h  and the thickness or size of each ion regions or layers of the multiple RESURF structure may be various as long as a shorter current path from the source region to the drain region is provided. Additionally, the multiple RESURF structures of  FIGS. 5   a - 5   h  may also be formed in the drift region  224  of the epitaxial layer as shown in  FIG. 3   b.    
         [0042]    A gate dielectric structure  280  with a step formed on the edge thereof will be discussed in accordance to embodiments of the present disclosure. 
         [0043]      FIGS. 6   a - 6   d  illustrate a step-to-step procedure for forming the step gate dielectric structure  280  in accordance with an exemplary embodiment. 
         [0044]    Referring to  FIG. 6   a , a first gate dielectric layer  270  is formed on the semiconductor substrate  210  (or the epitaxial layer  220  if exists). The first gate dielectric layer  270  comprises silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics, other suitable dielectric materials, or combinations thereof. High-k dielectrics may comprise metal oxides, for example, oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. The first gate dielectric layer  270  may be formed by an ordinary process known in the art, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. The first gate dielectric layer  270  may have a thickness from about 400 angstroms to 5000 angstroms. The gate dielectric layer  270  may cover both of the body region  212  and the drift region  214  (or  222  and  224 ). 
         [0045]    Referring to  FIG. 6   b , an etching process  600  is performed to remove a portion of the first gate dielectric layer  270  using a mask layer  50  to form a step  270   a  on at least one edge of the first gate dielectric layer  270  (as shown in  FIG. 6   c ). The mask layer  50  may be a patterned photoresist layer or a hard mask layer such as a silicon nitride or a silicon oxynitride layer or the like. The etching process  600  may be a dry etching process or a wet etching process. Although the step  270   a  shown in  FIG. 6   c  is in a cliff-shape, it should be realized that the step  270   a  may also be in a rounded-shape or any other suitable shapes. The mask layer  42  is then removed after the step is formed on the edge of the first gate dielectric layer  270 . 
         [0046]    Referring to  FIG. 6   d , a second gate dielectric layer  272  having a thickness thinner than the thickness of the first gate dielectric layer  270  is formed on the semiconductor substrate  210  (or the epitaxial layer  220  if exists). The first gate dielectric layer  270  and the second gate dielectric layer  272  are associated together form the step gate dielectric structure  280 . The second gate dielectric layer  272  adjoins the step  270   a  of the first gate dielectric  270 . The thickness of the second gate dielectric layer  272  is about 30 angstroms to 1000 angstroms. The same processes for forming the first gate dielectric layer  270  may be used to form the second gate dielectric layer, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. The second gate dielectric layer  272  may be formed of a material similar to the first gate dielectric layer  270 , for example, silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics, other suitable dielectric materials, or combinations thereof. 
         [0047]      FIGS. 7   a - 7   d  illustrate a step-to-step procedure for forming the step gate dielectric structure  280  in accordance with another exemplary embodiment. 
         [0048]    Referring to  FIG. 7   a , first gate dielectric layer  270  is formed on the semiconductor substrate  210  (or the epitaxial layer  220  if exists). The first gate dielectric layer  270  comprises silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics, other suitable dielectric materials, or combinations thereof. High-k dielectrics may comprise metal oxides, for example, oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. The first gate dielectric layer  270  may be formed by an ordinary process known in the art, such as Local Oxidation of Silicon (LOCOS), other depositions (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation), or combinations thereof. The gate dielectric layer  270  may cover both of the body region  212  and the drift region  214  (or  222  and  224 ). 
         [0049]    Referring to  FIG. 7   b , a mask layer  60  with at least one opening  60   a  is formed on the first gate dielectric layer  270  to selectively expose a portion of the first gate dielectric layer  270 . The opening  60   a  may be formed by an etching process. 
         [0050]    Referring to  FIG. 7   c , a thermal growth process  700  is applied to the exposed portion of the first gate dielectric layer  270  in the opening  60   a . The portion of first gate dielectric layer  270 , where the thermal growth process  700  applied to, expands to a greater thickness. In some embodiments, a second thermal growth process may be optionally performed to develop a further expansion of the first gate dielectric layer  270 . The expanded portion the first gate dielectric layer  270  may have aa thickness of about ______-______. In some embodiments, a portion of the first gate dielectric layer  270  expands into the substrate  210  (or the epitaxial layer  220  if exists), as shown as  FIG. 7   c.    
         [0051]    Referring to  FIG. 7   d , the mask layer  60  and a portion of the first gate dielectric layer  270  are removed to form a step gate dielectric structure  280 . 
         [0052]    After the step gate dielectric structure is formed. A process for forming source and drain regions is performed. Referring to  FIG. 8 , a source region  250  is formed in the body region  222  and a drain region  260  is formed. The source and drain regions  250  and  260  may be formed by a doping process commonly used in the art, such as an ion implantation process. 
         [0053]    Features that are commonly found in a conventional semiconductor device such as an inter-layer dielectric (ILD) layer  290 , source/drain electrodes  252  and  262 , and a gate electrode  282  are formed to complete the formation of the semiconductor device  200 . Referring to  FIG. 5   e , the interlayer dielectric (ILD) layer  290  may be formed covering the semiconductor device  200  with contact holes exposing the source/drain regions  250  and  260 . It is noted that depending on the design of a device, the number of the contact hole may be two or more. The gate electrode  282  may include a single layer or multilayer structure formed on the gate dielectric structure  280 . The gate electrode  282  may be formed of a material comprises metal, doped polysilicon, or combination thereof. The gate electrode  282  may be formed using a process such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), other suitable processes, or combinations thereof. The source electrode  252  is formed on the source region  250  and the drain electrode  262  is formed on the drain region  260 . 
         [0054]    The disclosed embodiments provide at least the following advantages over the conventional LDMOS device. First, step gate dielectric structure  280  provides a shorter path (as shown as the dotted line in  FIG. 8 ) for the current to flow from the source region  250  to the drain region  260 , which may lead to a low on-resistance (R on ) of the semiconductor device  200 . Second, due the design of multiple RESURF structure  230 , the breakdown voltage level may be maintained while reducing the on-resistance of the semiconductor device  200 . 
         [0055]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.