Abstract:
A low power linear feedback shift register includes an ordered set of register steps including memory devices. Enabling devices enable a single current memory device at every shift operation. Each register step includes a lower power memory device consuming a minimum amount of power when disabled, and a feedback device, an output terminal thereof being connected to an input terminal of the memory device, the feedback device having first and second input terminals connected to an output terminal of the memory device and an output terminal of a second subsequent memory device, respectively, in the set. The output terminal of each memory device is connected to a selection device, selecting at every shift operation the output terminal of a first subsequent memory device following the current memory device being enabled at the current shift operation.

Description:
This application claims priority under 35 U.S.C. §§ 119 and/or 365 to 9801781-7 filed in Sweden on May 18, 1998; the entire content of which is hereby incorporated by reference. 
    
    
     The present invention relates to shift registers and more particularly to low power linear feedback shift registers. 
     BACKGROUND 
     Linear feedback shift registers (LFSR) are used in many different electronic apparatuses such as computers, calculators, personal organisers mobile phones etc. 
     A register is normally used as a storage for a set of information, usually a binary word. Conventionally, an n-bit register is an ordered set of n flip-flops used to store an n-bit word. Each bit of the word is stored in a separate flip-flop. Registers where the words or data transferred to or from the register in parallel are usually designed with D latches or D flip-flops. A widely used register design organized to allow left- or right-shift operations of the stored information is called a shift register. An n-bit shift register may consist of n D flip-flops each of which is connected to its left and/or right neighbour. Data may be entered 1 bit at a time at one end of the register and may be read 1 bit at a time from the other end, which is called serial input-output. A right shift of a D flip-flop shift register is achieved by enabling the clock input of each flip-flop. 
     A problem with the above mentioned prior art shift register designs is that when they are used in applications or apparatuses, such as mobile phones, where power consumption is critical, the power consumption in the flip-flops in the shift registers is a considerable portion of the total power consumption in the current apparatus. 
     However, U.S. Pat. No. 5,295,174 discloses a shifting circuit having lower power consumption and a shift register employing the same. The shift register comprises a plurality of latch circuits, a multiplexer for selecting outputs of the latch circuits in sequence, and a clock control circuit for generating clocks used for controlling selection timings of the multiplexer, wherein the timing for selecting the output of a certain latch circuit is delayed with respect to the latch timing of the certain latch circuit by a predetermined timing. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an improved linear feedback shift register (LFSR) reducing the power consumption problem. 
     This is accomplished by a low power linear feedback shift register according to the invention, using memory means such as flip-flops not consuming power when they are disabled. The register does not shift any bits but still generates the same sequence as a conventional linear feedback shift register. 
     The register comprises enabling means enabling a single current memory means at every shift operation, register steps, each comprising a low power memory means consuming a minimum of power when it is disabled, and feedback means of each step. Each memory means is connected to selection means, selecting at every shift operation the output terminal of a first subsequent memory means following the current memory means being enabled at the current shift operation. 
     Another object of the present invention is to provide said enabling means. 
     Still another object of the invention is to provide said selection means. 
     An advantage of the low power linear feedback shift register according to the invention is the reduction in power consumption. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order to explain the invention in more detail and the advantages and features of the invention preferred embodiments will be described in detail below, reference being made to the accompanying drawings, in which 
     FIG. 1 is a schematical block diagram of a prior art linear feedback shift register (LFSR), a first flip-flop of which is updated with a feedback value, 
     FIG. 2 is a schematical block diagram of the shift register (LFSR) in FIG. 1 in further detail, 
     FIG. 3 is a schematical block diagram of a first modification of the shift register (LFSR) in FIG. 2, 
     FIG. 4 is a schematical block diagram of a second modification of the shift register (LFSR) in FIG. 2, 
     FIG. 5 is a schematical block diagram of an embodiment of a shift register (LFSR) according to the invention, 
     FIG. 6 shows a low power one-hot coded FSM, and 
     FIG. 7 shows an embodiment of a multiplexer of the shift register in FIG. 5 controlled by a one-hot coded FSM. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A conventional prior art 7-position shift register comprising seven flip-flops  1 - 7  connected in series is shown in FIG.  1  and in further detail in FIG.  2 . The shift register is provided with a simple feedback by means of an EXOR (Exclusive-OR) gate E having first and second input terminals connected to the output terminal of the second flip-flop  2  and seventh flip-flop  7 , respectively. An output terminal of the EXOR gate E is connected to an input terminal of the first flip-flop  1 , an output of which is connected to an output terminal or u 1  of the register. This kind of shift register is called a linear feedback shift register (LFSR). 
     In the following description, numerous specific details, such as the number of positions in the register or the feedback polynomial, are provided in order to give a more thorough description of the present invention. It will be obvious for those skilled in the art that the present invention may be practiced without these specific details. Some well-known features are not described in detail so as not to make the present invention unclear. 
     Considering a steady state for the register in FIG. 2, when the register is to be updated, each flip-flop  2 - 7  is updated with the value on the output terminal of the flip-flop in the preceding position. However, in the first position the flip-flop  1  is updated with the feedback value from the output terminal of the EXOR gate E. 
     A low power LFSR according to the invention is accomplished by a conversion of the conventional prior art LFSR illustrated in FIG.  2 . 
     A first step of the conversion is illustrated in FIG. 3, in which the feedback is arranged one step to the left and, hence, an output terminal of an EXOR gate E 7  is connected to an input terminal of the seventh flip-flop  7 . Further, the EXOR gate E 7  has first and second input terminals connected to the output of the flip-flop  2  and the flip-flop  7 , as described. Consequently, the output terminal of the flip-flop  7  is connected to the output terminal u 1  of the register. The output value from the output terminal u 1  in the modified LFSR shown in FIG. 3 corresponds to the output value of the output terminal u 1  in the conventional prior art LFSR illustrated in FIG. 2 after a one bit right shift operation. Additionally, each flip-flop  1 - 7  is provided with an enable input connection en 1 -en 7 , respectively, in order to control which flip-flop to be updated. Additionally, each flip-flop  1 - 7  has a clock input connection, not shown in the drawings. 
     In a second step of the conversion illustrated in FIG. 4, an output terminal of another EXOR gate E 6  is connected to an input terminal of the flip-flop  6 , the output terminal thereof being connected to the output terminal u 1  of the register, and the EXOR gate E 6  has first and second input terminals connected to the output of the flip-flop  1  and the flip-flop  6 , respectively. This second feedback is necessary since the bit values in the register are not really shifted. The output value from the output terminal u 1  in the modified LFSR shown in FIG. 4 is the output value from flip-flop  6  and corresponds to the output value of the output terminal u 1  in the conventional prior art LFSR illustrated in FIG. 2 after a another right bit shift operation. 
     However, in order to choose the correct output terminal, i.e the output terminal of the sixth flip-flop  6 , two input terminals of a selection means such as a MUX (Multiplexer) M 1  is connected to the output terminals of the two flip-flops  6  and  7 . In order to provide a correct output value after a first “shift” operation the flip-flop  6  is enabled and the output value on the flip-flop  7  is allowed to pass the MUX M 1 , and after a second “shift” operation the output of the flip-flop  6  is allowed to pass the MUX M 1 . 
     A completely converted conventional LFSR, i.e. an embodiment of a low power 7-step LFSR according to the present invention is shown in FIG.  5 . The LFSR comprises seven flip-flops  1 - 7 , seven EXOR gates E 1 -E 7  for the feedback arrangements, and a MUX M 1  provided with seven input terminals data 1 -data 7  from the flip-flops and an output terminal u 1 . During a first shift operation the enable input of flip-flop  1  is activated via the enable input e 1  and the MUX M 1  allows the output data 2  from the flip-flop  2  to pass as the current output value u 1 . A second shift operation involves an activation of the enable input e 2  of the flip-flop  2  and the MUX M 1  allows the output data 3  from the flip-flop  3  to pass as the current output value u 1  and so on for every step. 
     Thus, only one of the flip-flops in the LFSR register according to the invention is enabled or activated during each shift operation, and as a result the low power LFSR according to the invention generates the same output bit sequence as a conventional LFSR. This lower flip-flop activity causes less power loss and, further, the longer the shift register and the smaller the feedback the more efficient is the low power LFSR according to the invention. 
     In a register of an arbitrary length n having a feed-back polynomial of the same degree as the present feedback, the LFSR comprises n flip-flops  1 −n, n EXOR gates E 1 -En for the feedback arrangements, and a MUX M 1  provided with n input terminals data 1 -datan and an output terminal u 1 . If i=n−1 . . . 1, during a first shift operation the enable input of flip-flop i is activated via the enable input and the MUX M 1  allows the output data(i+1) from the flip-flop i+1 to pass as the current output value u 1 . However, if i=n a shift operation involves an activation of the enable input of the flip-flop n and the MUX M 1  allows the output datal from the flip-flop  1  to pass as the current output value u 1 . 
     In order to generate the enable signals to the flip-flops, one after the other, enabling means such as a low power one-hot coded finite state machine (fsm) with n steps is used. An n-step fsm comprises n flip-flops F 1 -Fn and n NOR gates N 1 -Nn. 
     Each flip-flop in the fsm has a clock input connection, not shown in the drawings, an enable input connection {overscore (en)} (activated by a 0 value), a data input connection d, and a data output connection q. If i=1 . . . n, the data output connection d of a flip-flop Fi is connected to a first input terminal of a NOR gate Ni, an output terminal thereof being connected to the enable input connection {overscore (en)} of the flip-flop Fi, the data input terminal of the flip-flop F(i−1) (Fn if i=1), and a second input of the NOR gate N(i−1) (Nn if i=1). The output terminal of the flip-flop Fi is also connected to the enable input eni (en 1 -en 7 ) of the flip-flop i in the low power LFSR according to the invention. 
     An embodiment of a 7-step fsm for connection to and control of the low-power LFSR illustrated in FIG. 5 is shown in FIG.  6 . The 7-step fsm comprises seven flip-flops F 1 -F 7  and seven NOR gates N 1 -N 7  connected as described above. 
     The fsm is also used to control the MUX M 1 . An embodiment of the MUX M 1  is shown in FIG.  7 . It comprises seven AND gates A 1 -A 7  and four OR gates O 1 -O 4 . The main function of the MUX M 1  is that the enable signal en 1  causes the data 2  to be the current output signal on u 1  and en 2  causes the data 3  to be the current output signal on u 1  and so on until en 7  which causes the datal to be the current output signal on u 1 . 
     Thus, it should be apparent that the present invention provides an LFSR that fully satisfies the aims and advantages set forth above. Although the invention has been described in conjunction with specific embodiments thereof, alternatives, modifications and variations are apparent to those skilled in the art. 
     For example, a conventional LFRS as shown in FIGS. 1 and 2 may have a different feedback polynomial such as and additional EXOR gate having first and second input terminals connected to the output of the flip-flop  6  and the flip-flop  7 . Instead of the output terminal of flip-flop  7  an output terminal of the additional EXOR gate is connected to the second input terminal of the EXOR E. A conversion of the LFSR provided with this different feedback polynomial into a low power LFSR according to the invention is accomplished by a similar conversion of the conventional prior art LFSR as described for the conventional LFSR shown in FIGS. 1 and 2, in which memory means such as flip-flops not consuming power when they are disabled are used, and wherein the register does not shift any bits but still generates the same sequence as the conventional linear feedback shift register. However, in one embodiment of an LFSR provided with this different feedback polynomial another seven EXOR gates are needed for the design.