Abstract:
A Class D amplifier device with reduced power consumption uses a passive RC network. The output of the RC network directly feeds a comparator resulting in increased efficiency. The RC network is configured to perform several functions, including the low pass filtering of the feedback signal to remove high frequency/high amplitude clock components and provides a DC path from its output to reduce duty cycle errors. Additionally, the input signal receives low pass filtering, creating a generally flat frequency response. Finally,the clock signal is filtered to generate a triangle wave of good linearity and appropriate amplitude.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims priority of U.S. Provisional Patent Application No. 60/284,444 filed on Apr. 18, 2001 entitled “Class D Amplifier with Passive RC Network,” and the teachings are incorporated herein by reference. 
     
    
     
       TECHNICAL FIELD OF THE INVENTION  
         [0002]    The present invention relates to an efficient audio signal amplifier and, more specifically, to a Class D amplifier using a passive resistive-capacitive (RC) network. More specifically, the present invention relates to Class D amplifier device utilizing a passive RC network that reduces current consumption and increases efficiency. The use of selectable output stages also reduces current consumption.  
         BACKGROUND OF THE INVENTION  
         [0003]    Class D amplifiers are in widespread use for a variety of applications. In audio applications, for example, the Class D amplifier has become an attractive alternative for applications that require high efficiency and low distortion. U.S. Pat. No. 4,689,819 to Killion describes the use of a Class D amplifier in a hearing aid application. In hearing aid applications, a premium is placed on the ability of the device to operate as close as possible to distortion free while maintaining suitable levels of amplifier performance.  
           [0004]    A problem associated with prior art Class D amplifier devices is the use of active feedback loops that utilize substantial amounts of power. FIG. 1 illustrates a prior art class D amplifier circuit, denoted as  10 , wherein a traditional feedback loop is established between the output and the input using an error amplifier. Essentially, circuit  10  uses an output stage  12  with an H-bridge output stage delivering output  14  that, in turn, drives load  16 . The output signal  14  is coupled to the feedback loop  16  comprising of feedback impedance  18  which forms an input to error amplifier  20 . The use of error amplifier  20  in a class D amplifier circuit, such as circuit  10 , is well known in the industry. The output of the error amplifier  20  is fed to a comparator circuit  22  which, in turn, is driven by the  391  wave generator  24  which provides a clock signal for operating the output stage  12 , and specifically for controlling the duty cycle of the output stage  12 . Thus, the input signal  26  and feedback signal  16  are summed and provided to the error amplifier  20  which controls the stability of the circuit  10  and amplitude of the output signal  14  as a function of the feedback impedance  18  over the input impedance  28 .  
           [0005]    In a Class D amplifier circuit, such as circuit  10 , the input and feedback signals are normally summed in an amplifier, such as error amplifier  20 . This increases power consumption since the amplifier  20  is an active device requiring current to operate. Moreover, since the output stage  12  is always operating, power consumption at the output can be significant even for small signals outside the audible range. Accordingly, a Class D amplifier device with reduced internal power consumption would provide numerous advantages.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention provides a Class D amplifier device with reduced power consumption. Essentially, power consumption is minimized by the use of a passive RC network. The output of the RC network directly feeds a comparator resulting in increased efficiency for low power audio applications. The RC network is configured to perform several functions, including the low pass filtering of the feedback signal to remove high frequency/high amplitude clock signals. In addition, the RC network provides a DC path from its output to reduce duty cycle errors. Additionally, the input signal receives low pass filtering, creating a generally flat frequency response. Finally, the clock signal is filtered to generate a triangle wave of good linearity and appropriate amplitude.  
           [0007]    According to another embodiment, the present invention provides a Class D amplifier device with selectable output stages having gate drives that activate, depending on the load impendance and signal level, and therefore optimize current consumption and efficiency. By separating the gate drives into upper and lower stages, only those that are enabled corresponding to a suitable signal level amplitude are active, limiting consumption by other gate drive circuits in the output stage.  
           [0008]    A technical advantage of the present invention is reduced current consumption by the driving stage in a Class D amplifier circuit.  
           [0009]    Another technical advantages of the present invention is increased efficiency by the use of a passive RC network to generate the appropriate drive signals to the output. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    For a better understanding of the invention including its features, advantages and specific embodiments, reference is made to the following detailed description along with accompanying drawings in which:  
         [0011]    [0011]FIG. 1 is a circuit block diagram of a prior art Class D amplifier circuit;  
         [0012]    [0012]FIG. 2 is a circuit block diagram of a Class D amplifier using a passive RC network, according to the invention;  
         [0013]    [0013]FIG. 3 is a detailed circuit diagram of the passive RC network suitable for use in a Class D amplifier, according to the invention;  
         [0014]    [0014]FIG. 4 illustrates the selectable output stages and gate drive circuit according to the invention;  
         [0015]    [0015]FIG. 5 shows one of N parallel stages and a timing diagram illustrating the operation of the stage, according to the invention; and  
         [0016]    [0016]FIG. 6 shows the use of a pulse conditioner for generating suitable clock signals in a Class D amplifier. Corresponding references in the detailed description correspond to like parts in the figures unless otherwise indicated. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]    While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts which can be embodied in a wide variety of specific contexts.  
         [0018]    With reference now to the figures and in particular to FIG. 2, therein is shown a Class D amplifier circuit  50 , according to the invention. The output stage  52  of the amplifier  50  is an H-bridge that generates output  54  to driving load  56 . The load  56 , for example, can comprise any suitable audio component, such as a speaker. In one application, the Class D amplifier circuit  50  is utilized in a hearing aid application wherein power consumption efficiency is a premium and the load  56  comprises a miniaturized speaker of the type found in modem hearing aids.  
         [0019]    The output  54  is fed back in a feedback loop to passive RC network  60 . Essentially, the RC network  60  acts to sum the feedback signal  62 , input signal  64  and clock signal  66  and provides an output  68  which drives the comparator  70 . The output of the comparator  70  is a pulse width modulated waveform  72  which drives the data input of the pulse conditioner  74 . FIG. 6 illustrates a suitable circuit design for the pulse conditioner  74 .  
         [0020]    The fact that the Class D amplifier circuit  50  utilizes a passive RC network  60  means that less power is consumed, resulting in higher efficiency for the application in which the circuit  50  is utilized. Also, the output stage  52  includes enable signals  80  which, as described below with reference to FIG. 4, further increases the efficiency by decreasing current consumption of the circuit  50 .  
         [0021]    With reference now to FIG. 3, therein is shown a detailed circuit schematic diagram of the passive RC network  60 , according to the invention. The passive RC network  60  includes a triangle wave generator circuit  80 , low pass filter  82  applied to the input signal  64 A,  64 B, low pass filter  84  applied to the feedback signal  62 A,  62 B and DC feedback circuit  86 . This design provides the RC network  60  the ability to perform several functions. First, the feedback signal  62 A,  62 B (non-inverted and inverted, respectively) are filtered by the low pass filter  84  in order to eliminate any high frequency/high amplitude clock components and to attenuate the feedback signal  62 A,  62 B relative to the input signal  64 A,  64 B. Next, the DC feedback section  86  provides a DC path with minimal attenuation from the feedback input  62  to the output  68  of the passive RC network  60 .  
         [0022]    In addition, since low pass filtering of the feedback signal  62 A,  62 B also affects the high end of the audio band, the low pass filter  82  is provided for filtering of the input signal  64 A,  64 B in order to produce a relatively flat frequency response. Finally, the clock signal  66 A,  66 B is low pass filtered with filter  80  in order to generate a triangle wave having good linear characteristics and the appropriate amplitude.  
         [0023]    Therefore, the passive RC network  60  is capable of performing the functions of an active amplifier without the excessive current consumption required by an active amplifier. The reason to choose a Class D amplifier instead of a more traditional Class A or Class AB is a possibility of achieving higher efficiency. In this regard, a relatively large part of the total internal current consumption is used by the output stage, such as output stage  12 , especially if the transistors in the H-bridge are driven from a double voltage to reach a low resistance at low supply voltages. As seen in FIG. 4, the output stage  52  provides the ability of disabling a portion of the outputs by placing them in high impedance state. If, for instance, the output stage  52  is divided into two parallel stages with ⅓ and ⅔ of the total driving capability in separate enable signals, three different levels of power consumption and driving capability are available.  
         [0024]    The output stage  52  includes N number of P gate drives and N number of N gate drives,  100   1N ,  102   1N , respectively. Enable signals  104  are provided to allow for selectably engaging the desired stage. The level of the input signal or output signal are used to control the output stage (taking into account the load impedance). The selection may be static based on low impedance or dynamic, depending on a combination of load impedance and output level. At low output levels, the saved internal current consumption with low driving capability can offset the reduced efficiency due to higher voltage drops over the transistors.  
         [0025]    Besides the internal current consumption, the on resistance in the output switches is critical for efficiency and should ideally be zero. This, of course, is not possible, but the resistance should at least be small compared to the load resistance. Even this requirement can be difficult to meet in applications where the supply voltage can drop to voltages not much higher than the threshold voltage of the switch transistors in the output stage. Either very large output transistors driven by the supply voltage are used, or smaller transistors driven by voltages larger than the supply voltage. In the latter case, the NMOS thresholds are low enough so the low-side switches can be driven directly from the supply voltage while the PMOS transistors used as high-side switches is driven by a doubled supply voltage because of their higher threshold voltages.  
         [0026]    When driving PMOS transistors manufactured in an N-well process with doubled supply voltage, the gate voltage will be driven below the substrate voltage so no NMOS transistors can be connected directly to the gate. Instead, as shown in FIGS. 5 a  and  5   b,  the gate is capacitively driven from a clock swinging between VSS and 2*VDD. To define the DC level after the capacitor, the gate is held at VDD by a transistor when the clock is high and is left floating while the clock is low and the PMOS transistor is on. Since the gate is always clocked with a high frequency, leakage currents will not change the operating point significantly.  
         [0027]    With a dynamic circuit driving the gates in the output stage, there is a potential problem at start-up. Initially, the PMOS output transistors will not conduct until the comparator has generated enough clock cycles for the voltage doubler to get started. This will cause both of the complementary outputs to be close to the negative supply voltage. With a DC feedback from the outputs to the comparator to control duty cycle errors, the comparator will see a DC level at the negative supply as well. If the comparator common mode range can&#39;t handle this, the output will be stuck and no clocks to the output stage will be generated so the circuit can start. A comparator with a PMOS input stage may eliminate this problem, but in many cases, the PMOS thresholds are higher than NMOS thresholds, so for low voltage operation, NMOS transistors are often the best choice. With the function of the pulse width modulator in mind, it is safe to say that at the peak of the triangle wave, the output should always have one known state, and the opposite state at the bottom of the triangle wave unless the circuit is clipping. Therefore, the additional circuit of FIG. 6 can be used to override the comparator output at these moments and force the signal to the output stage to pulse once per clock period. The triangle wave is generated by low pass filtering the clock, so the two peaks correspond to the two edges of the clock. An edge detector generates the two override pulses.  
         [0028]    While the invention has been described with regard to specific and illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments as well as other embodiments of the invention will become apparent to persons skilled in the art upon reference to the description and is intended that such variations be encompassed and included within the meaning and scope of the invention.