Abstract:
A level shifter includes first and second P-type TFTs for latching a level of first and second output nodes, first and second N-type TFTs for setting the level of the first and second output nodes, and a drive circuit. The drive circuit includes third to eighth N-type TFTs providing, in response to rising and falling edges of an input signal, a voltage higher than a threshold voltage of the first and second N-type TFTs, between the gate and source of the first and second N-type TFTs, and includes first and second capacitors and a resistor element. Accordingly, even if an amplitude voltage of an input signal is smaller than the threshold voltage of the first and second N-type TFTs, the level shifter operates normally.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to amplitude conversion circuits. In particular, the present invention relates to an amplitude conversion circuit for changing an amplitude of a signal.  
           [0003]    2. Description of the Background Art  
           [0004]    [0004]FIG. 27 is a block diagram showing a configuration of a part of a conventional cellular phone that is involved in image display.  
           [0005]    Referring to FIG. 27, the cellular phone includes a control LSI  71  which is a MOST (MOS transistor) integrated circuit, a level shifter  72  which is also a MOST integrated circuit, and a liquid crystal display  73  which is a TFT (thin-film transistor) integrated circuit.  
           [0006]    Control LSI  71  generates a control signal for liquid crystal display  73 . The control signal has an H or logical high level of 3 V and an L or logical low level of 0 V. Although a large number of control signals are actually generated, it is herein assumed, for convenience of description, that one control signal is generated. Level shifter  72  converts the logic level of the control signal supplied from control LSI  71  to generate an internal control signal. The internal control signal has an H level of 7.5 V and an L level of 0 V. Liquid crystal display  73  presents an image according to the internal control signal from level shifter  72 .  
           [0007]    [0007]FIG. 28 is a circuit diagram showing a configuration of level shifter  72 . Referring to FIG. 28, level shifter  72  includes P-channel MOS transistors  74  and  75  and N-channel MOS transistors  76  and  77 . P-channel MOS transistors  74  and  75  are connected between a node N 71  of a power supply potential VCC (7.5 V) and output nodes N 74  and N 75  respectively, and have respective gates connected to output nodes N 75  and N 74  respectively. N-channel MOS transistors  76  and  77  are connected respectively between output nodes N 74  and N 75  and a node of a ground potential GND, and have respective gates receiving input signals VI and /VI.  
           [0008]    Here, it is supposed that input signals VI and /VI respectively have L level (0 V) and H level (3 V) while output signals VO and /VO respectively have H level (7.5 V) and L level (0 V). Then, MOS transistors  74  and  77  are turned on while MOS transistors  75  and  76  are turned off.  
           [0009]    In this state, input signal VI is raised from L level (0 V) to H level (3 V) and input signal /VI is lowered from H level (3 V) to L level (0 V). Then, N-channel MOS transistor  76  is turned on first to cause the potential on output node N 74  to decrease. When the potential on output node N 74  decreases below the potential determined by subtracting the absolute value of a threshold voltage of P-channel MOS transistor  75  from power supply potential VCC, P-channel MOS transistor  75  is turned on to start increase of the potential on output node N 75 . The increasing potential on output node N 75  decreases the source-gate voltage of P-channel MOS transistor  74  and accordingly increases the ON resistance value of P-channel MOS transistor  74 , and the potential on output node N 74  further decreases. The circuit thus operates in positive feedback manner so that output signals VO and /VO have L level (0 V) and H level (7.5 V) respectively and the level converting operation is completed.  
           [0010]    A level shifter disclosed for example in Japanese Patent Laying-Open No. 11-145821 has P-channel MOS transistors  74  and  75  with respective gates both connected to one output node N 74  or N 75 .  
           [0011]    As discussed above, the conventional level shifter  72  operates on the precondition that N-channel MOS transistor  76  is turned on in response to rising of input signal VI from L level (0 V) to H level (3 V). In order to render N-channel MOS transistor  76  conductive, the threshold voltage of N-channel MOS transistor  76  must be H level (3 V) or less of input signal VI.  
           [0012]    The threshold voltage of a commonly used semiconductor LSI is easily set at 3V or less. However, there is a considerable difference in the threshold voltage between low-temperature polysilicon TFTs included in the liquid crystal display, which makes it difficult to set the threshold voltage of the TFTs at 3 V or less. Then, as shown in FIG. 27, level shifter  72  constituted of high-withstand-voltage MOS transistors is provided between control LSI  71  and liquid crystal display  73  to change the logic level of the signal.  
           [0013]    However, the cost of level shifter  72  thus provided adds to the system cost, resulting in increase of the system cost.  
         SUMMARY OF THE INVENTION  
         [0014]    One object of the present invention is to provide an amplitude conversion circuit and a semiconductor device using the amplitude conversion circuit which normally operates even if a voltage amplitude of an input signal is smaller than the threshold voltage of an input transistor.  
           [0015]    An amplitude conversion circuit according to the present invention converts a first signal with an amplitude corresponding to a first voltage into a second signal with an amplitude corresponding to a second voltage higher than the first voltage, and includes first and second transistors of a first conductivity type, third and fourth transistors of a second conductivity type, and a drive circuit. The first and second transistors have respective first electrodes both receiving the second voltage, respective second electrodes connected respectively to first and second output nodes for providing the second signal and a complementary signal of the second signal, and respective input electrodes connected respectively to the second and first output nodes. Respective first electrodes of the third and fourth transistors are connected respectively to the first and second output nodes. The drive circuit is driven by the first signal and a complementary signal of the first signal, provides, in response to a leading edge of the complementary signal of the first signal, a third voltage higher than the first voltage between an input electrode and a second electrode of the third transistor to turn on the third transistor, and provides, in response to a leading edge of the first signal corresponding to a trailing edge of the complementary signal of the first signal, the third voltage between an input electrode and a second electrode of the fourth transistor to turn on the fourth transistor. Thus, in response to the leading or trailing edge of the first signal, the third voltage which is higher than the threshold voltage of the third and fourth transistors is supplied between the input electrode and the second electrode of the third or fourth transistor. A normal operation is accordingly accomplished even if the amplitude of the first signal is smaller than the threshold voltage of the third and fourth transistors.  
           [0016]    Another amplitude conversion circuit according to the present invention converts a first signal with an amplitude corresponding to a first voltage into a second signal with an amplitude corresponding to a second voltage higher than the first voltage, and includes first and second transistors of a first conductivity type, third and fourth transistors of a second conductivity type, and a drive circuit. The first and second transistors have respective first electrodes both receiving the second voltage, respective second electrodes connected respectively to first and second output nodes for providing a second signal and a complementary signal of the second signal, and respective input electrodes both connected to the second output node. Respective first electrodes of the third and fourth transistors are connected to the first and second output nodes respectively. The drive circuit is driven by the first signal and a complementary signal of the first signal, provides, in response to a leading edge of the complementary signal of the first signal, a third voltage higher than the first voltage between an input electrode and a second electrode of the third transistor to turn on the third transistor, and provides, in response to a leading edge of the first signal corresponding to a trailing edge of the complementary signal of the first signal, the third voltage between an input electrode and a second electrode of the fourth transistor to turn on the fourth transistor. In this way, in response to the leading or trailing edge of the first signal, the third voltage which is higher than the threshold voltage of the third and fourth transistors is supplied between the input electrode and the second electrode of the third or fourth transistor. A normal operation is accordingly accomplished even if the amplitude of the first signal is smaller than the threshold voltage of the third and fourth transistors.  
           [0017]    The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    [0018]FIG. 1 is a block diagram showing a configuration of a part of a cellular phone that is involved in image display according to one embodiment of the present invention.  
         [0019]    [0019]FIG. 2 is a circuit diagram showing a configuration of a level shifter shown in FIG. 1.  
         [0020]    FIGS.  3  to  26  are circuit diagrams each showing a modification of the embodiment.  
         [0021]    [0021]FIG. 27 is a block diagram showing a configuration of a part of a conventional cellular phone that is involved in image display.  
         [0022]    [0022]FIG. 28 is a circuit diagram showing a configuration of a level shifter shown in FIG. 27. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    [0023]FIG. 1 is a block diagram showing a configuration of a part of a cellular phone that is involved in image display according to one embodiment of the present invention.  
         [0024]    Referring to FIG. 1, the cellular phone includes a control LSI  1  which is a MOST integrated circuit and a liquid crystal display  2  which is a TFT integrated circuit. Liquid crystal display  2  includes a level shifter  3  and a liquid crystal display unit  4 .  
         [0025]    Control LSI  1  generates a control signal for liquid crystal display  2 . The control signal has its H level of 3 V and its L level of 0 V. Although a large number of control signals are actually generated, it is assumed here for convenience of description that one control signal is generated. Level shifter  3  changes the logic level of the control signal from control LSI  1  to generate an internal control signal. The internal control signal has its H level of 7.5 V and its L level of 0 V. Liquid crystal display unit  4  presents an image according to the internal control signal from level shifter  3 .  
         [0026]    [0026]FIG. 2 is a circuit diagram showing a configuration of level shifter  3 . Referring to FIG. 2, level shifter  3  includes P-type TFTs  5  and  6 , N-type TFTs  7 - 14 , capacitors  15  and  16 , and a resistor element  17 . P-type TFTs  5  and  6  are connected between a node N 1  of a power supply potential VCC (7.5 V) and output nodes N 5  and N 6  respectively and have respective gates connected to output nodes N 6  and N 5 . Signals on respective output nodes N 5  and N 6  are output signals VO and /VO of level shifter  3 . N-type TFT  7  is connected between nodes N 5  and N 7 , having its gate connected to a node N 11 . N-type TFT  8  is connected between nodes N 6  and N 8 , having its gate connected to a node N 13 . Nodes N 7  and N 8  are respectively provided with an input signal VI and a complementary signal /VI thereof.  
         [0027]    Resistor element  17  and N-type TFTs  9  and  10  are connected in series between node N 1  of power supply potential VCC and a node of ground potential GND. The gate of N-type TFT  9  is connected to its drain (node N 9 ) and the gate of N-type TFT  10  is connected to its drain. N-type TFTs  9  and  10  each constitute a diode device and, resistor element  17  and N-type TFTs  9  and  10  constitute a constant potential generating circuit. When the resistance value of resistor element  17  is made sufficiently large (e.g. 100 MΩ) while the ON resistance value of N-type TFTs  9  and  10  is made sufficiently small relative to the resistance value of resistor element  17 , node N 9  has its potential V 9  equal to 2VTN (V 9 =2VTN), where VTN represents the threshold potential of the N-type TFTs.  
         [0028]    N-type TFT  11  is connected between node N 1  of power supply potential VCC and node N 11  and has its gate receiving potential V 9  on node N 9 . N-type TFT  12  is connected between nodes N 11  and N 12  and has its gate connected to node N 11 . N-type TFT  12  constitutes a diode element. Capacitor  15  is connected between nodes N 11  and N 12 . Node N 12  receives input signal /VI.  
         [0029]    N-type TFT  13  is connected between node N 1  of power supply potential VCC and node N 13  and has its gate receiving potential V 9  on node N 9 . N-type TFT  14  is connected between nodes N 13  and N 14  and has its gate connected to node N 13 . N-type TFT  14  constitutes a diode element. Capacitor  16  is connected between nodes N 13  and N 14 . Node N 14  receives input signal VI.  
         [0030]    Level shifter  3  operates as described below. It is now supposed that input signals VI and /VI have 3 V and 0 V respectively. As N-type TFT  11  operates in source-follower manner, potential V 11  on node N 11  is represented by: V 11 =2VTN−VTN=VTN. Diode-connected N-type TFT  12  has its threshold potential of VTN and thus almost no current flows from node N 1  of power supply potential VCC to node N 11 . N-type TFT  7  has its gate potential V 11  equal to VTN and its source potential of 3V, and thus N-type TFT  7  is turned off. Capacitor  15  is charged to threshold voltage VTN.  
         [0031]    As described below, potential V 13  on node N 13  is charged to VTN or higher and node N 8  has 0 V, and thus N-type TFT  8  is turned on. Then, output node N 6  has the potential (0 V) on input node N 8 , P-type TFT  5  is turned on, and output node N 5  has power supply potential VCC. Accordingly, P-type TFT  6  is turned off and no current flows between node N 1  of power supply potential VCC and input node N 8 .  
         [0032]    It is then supposed that input signal VI is lowered from 3 V to 0 V and input signal /VI is raised from 0 V to 3 V. The change of the potential of input signal /VI is transmitted via capacitor  15  by capacitive coupling to node N 11  to raise potential V 11  on node N 11 . When capacitor  15  has a capacitance value which is sufficiently larger than a capacitance value of a parasitic capacitance (not shown) of node N 11 , potential V 11  on output node N 11  is represented by: V 11 ≈VTN+ΔVI=VTN+3 V, where ΔVI represents the amplitude of input signals VI and /VI and is 3 V. Since the potential on the source (node N 7 ) of N-type TFT  7  is equal to 0 V, the gate-source voltage of N-type TFT  7  is equal to VTN+3 V, and N-type TFT  7  is turned on. Consequently, the potential on node N 5  has 0 V to turn on P-type TFT  6 .  
         [0033]    The potential change from 3 V to 0 V of input signal VI is transmitted via capacitor  16  by capacitive coupling to node N 13  to decrease potential V 13  on node N 13 . Suppose that input signals VI and /VI change at short intervals. As potential V 13  on node N 13  that has not been decreased is represented by V 13 =VTN+3 V, decreased potential V 13  is represented by V 13 =VTN+3 V−3 V=VTN. Next, suppose that input signals VI and /VI change at longer intervals. Potential V 13  on node N 13  that is a potential raised by the capacitive coupling decreases with passage of time. Accordingly, potential V 13  on node N 13  is smaller than VTN which is a potential value when the input signals change at short intervals, by the decreased amount of potential. In this case, N-type TFT  13  is turned on to raise potential V 13  on node N 13  to VTN.  
         [0034]    Gate potential V 13  of N-type TFT  8  is thus equal to VTN and the source potential (node N 8 ) thereof is equal to 3 V, which turns off N-type TFT  8 . The potential on output node N 6  is thus 7.5 V and P-type TFT  5  is turned off. Output nodes N 5  and N 6  are thus equal to 0 V and 7.5 V respectively. In this way, the logic level is converted from 3 V to 7.5 V.  
         [0035]    According to this embodiment, in response to the falling edge of input signal VI, voltage VTN+3 V is supplied between the gate and source of N-type TFT  7 , where VTN is the threshold voltage of N-type TFT  7  and 3 V corresponds to the amplitude voltage of input signal /VI. Thus, even if the amplitude voltage (3 V) of input signal /VI is smaller than threshold voltage VTN of N-type TFT  7 , level shifter  3  normally operates. It is accordingly possible to constitute one liquid crystal display  2  (TFT integrated circuit) by level shifter  3  and liquid crystal display unit  4 . The number of components is thus decreased to lower the system cost as compared with the conventional system in which level shifter  52  and liquid crystal display  53  are separately provided.  
         [0036]    Although a power supply current transiently flows in the course of operation, the current does not directly flow through components except for resistor element  17  and N-type TFTs  9  and  10 . Resistor element  17  has a large resistance value and thus only a slight current flows. Then, level shifter  3  consumes a considerably small power.  
         [0037]    Instead of TFTs  5 - 14  of this embodiment, MOS transistors may be used. In this case, the level shifter operates even if the amplitude of input signals VI and /VI is smaller than the threshold voltage of a MOS transistor.  
         [0038]    In addition, instead of the TFT which is an insulated gate field effect transistor, another type of field effect transistor may be used.  
         [0039]    Various modifications of the embodiment are now described. A level shifter  20  shown in FIG. 3 includes N-type TFTs  12  and  14  with respective sources grounded. According to this modification, the current through N-type TFTs  12  and  14  is not directed to input nodes N 12  and N 14  but to the node of ground potential GND. Only a small drive power is required for input signals VI and /VI.  
         [0040]    A level shifter  21  shown in FIG. 4 includes P-type TFTs  5  and  6  having respective sources receiving a power supply potential VCC (7.5 V), an N-type TFT  11  having its drain receiving a positive power supply potential VCC′ different from power supply potential VCC, and a resistor element  17  having one electrode (which is not the electrode connected to node N 9 ) receiving a power supply potential VCC″ which is different from power supply potentials VCC and VCC′. According to this modification, potentials V 9 , V 11  and V 13  on respective nodes N 9 , N 11  and N 13  are prevented from changing, the change being caused by noises generated on the node of power supply potential VCC for example.  
         [0041]    A level shifter  22  shown in FIG. 5 includes a resistor element  17  constituted of a P-type TFT  23 . Specifically, P-type TFT  23  is connected between a node N 1  of power supply potential VCC and a node N 9  and has its gate connected to a node of ground potential GND. The resistance value per unit area of the resistor element constituted of the TFT is greater than the resistance value per unit area of a resistor element constituted of a diffusion layer. Then, according to this modification, the area occupied by the resistor element can be reduced. The same effect is achieved if resistor element  17  is constituted of an N-type TFT having its gate receiving power supply potential VCC.  
         [0042]    A level shifter  24  shown in FIG. 6 additionally includes N-type TFTs  25  and  26 . N-type TFT  25  is connected between nodes N 5  and N 7  and has its gate connected to a node N 6 . N-type TFT  26  is connected between nodes N 6  and N 8  and has its gate connected to node N 5 . When input signals VI and /VI have H and L levels respectively and output signals VO and /VO have H and L levels respectively, N-type TFT  25  is turned off and N-type TFT  26  is turned on and output nodes N 5  and N 6  are kept at H and L levels respectively. When input signals VI and /VI change to L and H levels respectively and output signals VO and /VO change to L and H levels respectively, N-type TFT  25  is turned on and N-type TFT  26  is turned off and output nodes N 5  and N 6  are kept at L and H levels respectively.  
         [0043]    If input signals VI and /VI change at considerably long intervals, potentials V 11  and V 13  of respective nodes N 11  and N 13  both could be equal to threshold voltage VTN of the N-type TFTs, resulting in an inverted potential relation between output nodes N 5  and N 6 . N-type TFTs  25  and  26  are provided for avoiding such an inverted potential relation between output nodes N 5  and N 6  and serve to fix the potential on output nodes N 5  and N 6  regardless of potentials V 11  and V 13  on nodes N 11  and N 13 .  
         [0044]    A level shifter  27  shown in FIG. 7 includes N-type TFTs  25  and  26  of level shifter  24  shown in FIG. 6, that have respective sources connected to the node of ground potential GND. According to this modification, the current through N-type TFTs  25  and  26  is not directed to input nodes N 7  and N 8  but to the node of ground potential GND. Only a small drive power is required for input signals VI and /VI.  
         [0045]    A level shifter  30  shown in FIG. 8 includes N-type TFTs  7  and  8  of level shifter  3  shown in FIG. 2 that have respective sources both connected to the node of ground potential GND. According to this modification, the current through N-type TFTs  7  and  8  is not directed to input nodes N 7  and N 8  but to the node of ground potential GND, so that only a small drive power is required for input signals VI and /VI.  
         [0046]    A level shifter  31  shown in FIG. 9 includes N-type TFTs  7 ,  8 ,  25  and  26  of level shifter  27  shown in FIG. 7 that have respective sources connected to nodes of ground potential GND. According to this modification, current through N-type TFTs  7 ,  8 ,  25  and  26  is directed not to input nodes N 7  and N 8  but to the nodes of ground potential GND. Thus, further smaller drive power is merely required for input signals VI and /VI.  
         [0047]    A level shifter  32  shown in FIG. 10 includes P-type TFTs  5  and  6  of level shifter  3  shown in FIG. 2 that have respective gates both connected to a node N 5 . P-type TFTs  5  and  6  constitute a current mirror circuit. Current of the same current value flows through P-type TFTs  5  and  6 . When input signals VI and /VI have L and H levels respectively and N-type TFTs  7  and  8  are turned on and off respectively, current of the same current value as that flowing through TFTs  5  and  7  flows through P-type TFT  6  to accomplish differential amplification. Output nodes N 5  and N 6  have L and H levels respectively. According to this modification, the effect of amplitude conversion that is the same as the effect of level shifter  3  is achieved.  
         [0048]    A level shifter  33  shown in FIG. 11 includes P-type TFTs  5  and  6  of level shifter  24  shown in FIG. 6 that have respective gates both connected to a node N 5 . According to this modification, the same effect as that of level shifter  24  in FIG. 6 is achieved.  
         [0049]    A level shifter  34  shown in FIG. 12 includes N-type TFTs  7  and  8  of level shifter  32  shown in FIG. 10 that have respective sources both grounded. According to this modification, the current through N-type TFTs  7  and  8  is directed not to input nodes N 7  and N 8  but to the node of ground potential GND. Then, only a small drive power is necessary for input signals VI and /VI.  
         [0050]    A level shifter  35  shown in FIG. 13 includes N-type TFTs  7 ,  8 ,  25  and  26  of level shifter  33  shown in FIG. 11 that have respective sources being grounded. According to this modification, the current through N-type TFTs  7 ,  8 ,  25  and  26  is directed not to input nodes N 7  and N 8  but to the node of ground potential GND. Then, only a small drive power is necessary for input signals VI and /VI.  
         [0051]    According to a modification shown in FIG. 14, a constant potential generating circuit  36  including a resistor element  17  and N-type TFTs  9  and  10  is provided to be shared by a plurality of level shifters  38 ,  39  . . . . A capacitor  37  for making potential stable is connected between an output node N 9  of constant potential generating circuit  36  and a node of ground potential GND. Increase of the area of resistor element  17  is necessary for increasing the resistance value of resistor element  17 . According to this modification, however, constant potential generating circuit  36  is provided to be shared by a plurality of level shifters  38 ,  39 , . . . , which means that the overall circuit occupies a reduced area.  
         [0052]    A level shifter  40  shown in FIG. 15 additionally includes P-type TFTs  41  and  42  as compared to level shifter  3  shown in FIG. 2. P-type TFT  41  is connected between the drain of P-type TFT  5  and output node N 5  and has its gate connected to node N 1 . P-type TFT  42  is connected between the drain of P-type TFT  6  and output node N 6  and has its gate connected to node N 13 . When input signal /VI is raised from 0 V to 3 V, potential V 11  on node N 11  is VTN+3 V and accordingly P-type TFT  41  is turned off while N-type TFT  7  is turned on and output node N 5  has a potential of 0 V. At this time, as P-type TFT  41  is turned off, no current flows from node N 1  of power supply potential VCC to output node N 5 , which helps the potential on output node N 5  to decrease to 0 V. When input signal /VI is lowered from 3 V to 0 V, potential V 11  on node N 11  becomes VTN so that N-type TFT  7  is turned off while P-type TFT  41  is turned on and the potential on output node N 5  increases to 7.5 V.  
         [0053]    Further, when input signal VI is raised from 0 V to 3 V, potential V 13  on node N 13  is VTN+3 V so that P-type TFT  42  is turned off while N-type TFT  8  is turned on and the potential on output node N 6  is 0 V. At this time, as P-type TFT  42  is turned off, no current flows from node N 1  of power supply potential VCC to output node N 6 , which helps the potential on output node N 6  to decrease to 0 V. When input signal VI is lowered from 3 V to 0 V, potential V 13  on node N 13  becomes VTN so that N-type TFT  8  is turned off while P-type TFT  42  is turned on and the potential on output node N 6  increases to 7.5 V. According to this modification, decrease of respective potentials on output nodes N 5  and N 6  to 0 V is promoted, and accordingly the amplitude of input signals VI and /VI is reduced and the margin of the amplitude of input signals VI and /VI is increased.  
         [0054]    Revel shifters  45 - 55  in respective FIGS.  16 - 26  correspond respectively to level shifters  20 - 22 ,  24 ,  27 ,  30 - 35  in respective FIGS.  3 - 13 , and each additionally include P-type TFTs  41  and  42 . These modifications also achieve the same effect as that of level shifter  40  shown in FIG. 15.  
         [0055]    Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.