Abstract:
A system and method for utilizing a multi-probe tester to test an electrical device having a plurality of contact pads. Multi-probe tester test probes and electrical device contact pads are arrayed in a common distribution pitch, and a means for masking test probes masks at least one test probe, thereby preventing the at least one test probe from returning a test result to the testing apparatus. In one embodiment the means for masking test probes is a mask membrane physically preventing at least one test probe from making contact with the electrical device. In another embodiment, the means for masking is at least one software command configured to cause an input from at least one test probe to be disregarded during a test routine. Another embodiment features both mask membrane and software command probe masking.

Description:
FIELD OF THE INVENTION  
       [0001]     Methods and systems for testing electrical devices. More particularly, high throughput electrical test methods and systems for complex multi-chip computer system modules MCM&#39;s, more particularly step and repeat cluster probe testing of complex multilayer ceramic (MLC) substrates.  
       BACKGROUND OF THE INVENTION  
       [0002]     An important trend in the electronics industry today is the use of multi-chip modules (MCMs). Simply defined, a MCM has multiple integrated circuits (ICs) packaged on an insulting substrate that interconnects the ICs and provides external connections. MCMs create functional islands using both custom and standard chips that can help provide improved system performance and smaller size and weight, while offering a cost-effective solution for many applications.  
         [0003]     One example of a high-performance MCM multichip substrate is the IBM Corporation S/390™ product line.  FIGS. 1 and 2  illustrate both form-factor and design information on one embodiment  102  of an S/ 390  MCM. The MCM  102  comprises a plurality of individual chips  110 . The chips  110  are formed through a multilayer thick-film technology with a glass-ceramic/copper-metallurgy system. Top surface metallurgy (TSM) “Control Collapse Chip Connection” (C4) pads  124  are arrayed on a top surface  104  of the chip  110 . Copper conductors  120  are utilized to form circuitry within the chips  110 , said conductors  120  connected to the TSM C4 pads  124  and to bottom surface metallurgy (BSM) I/O pads  122  on the bottom surface  106  on the MCM  102 .  
         [0004]     The build process for these MCM substrates  102  is highly complex, and electrical testing is performed at several points during the fabrication sequence to minimize the capture time for the detection of unrepairable defects, to drive repair actions, and for the assurance of outgoing-part quality. It is known in the prior art to use capacitive and/or resistive techniques to detect line and via opens and shorts between MCM features. One example is the IBM Corporation-developed electronic module test (EMT™) methodology is used to screen substrates for such latent defects as line neckdowns and via abnormalities, which could lead to opens when used in the field. One means for performing capacitive or resistive test methodology is by using “Step-and-Repeat Cluster-Probe” tester architecture.  
         [0005]      FIGS. 3 and 4  provide an illustration of a typical prior art step and repeat cluster probe tester apparatus  200 , wherein two buckling beam cluster probe arm testers  202  are used to “step” onto each chip  110  of the MCM  102 . A pogo-pin array  212  is brought into electrical contact with the BSM I/O pads  122  of the MSM substrate  110 . The two buckling-beam probe arms  202  have a footprint that matches or partially matches with the top surface  104  of each chip  110 . Each cluster probe arm  202  has a plurality of “buckling beam” probes  304 , wherein each TSM C4 pad  124  is brought into compressive contact with a buckling beam probe  304 . The cluster probe tester apparatus  200  control system  204  then indicates a series of tests according to its “tool application program” (TAP). Net (electrical-circuit) configurations are programmed, and testing is executed by the control system  204  via the use of a commercial switching matrix and test engine. The test is highly efficient, with thousands of net tests being executed during one probe move. When a series of tests are complete, the probe arms  202  “step” over to another chip  110  and “repeats” the same test sequence for that chip  110 .  
         [0006]     However, prior art step-and-repeat cluster-probe testing efficiency has limitations. This mode of testing requires a repeatable C4 pattern that can be stepped with a fixed pad pitch at the level being tested with limits on subfield adjacency to allow for the cluster-probe-beam support structure. As conventionally used in the computer device industry, the term “pitch” refers to the distribution within an array of commonly spaced contact pads or clustered test probes: for example, a “10 mil pitch” may refer to an array of pads with adjacent pads spaced  10  mils from each other, wherein the  10  mil spacing may be specified as a center-to-center spacing or side-to-side spacing dimension. As it is common and desirable for an MCM to comprise chips with a plurality of divergent C4 patterns and/or footprint dimensions, the prior art cluster probe tester cannot efficiently test many MCM&#39;s.  
         [0007]     Specifically, where smaller footprint chips reside with larger footprint chips on the same MCM, a prior art step-and-repeat probe must cover the larger footprint as a minimum test footprint, which is then repeated for each chip on the MCM regardless of footprint size. Thus when the cluster probe tester tests the smaller footprint some tester contacts are driven into contact with surrounding non-circuitized substrate, or with surrounding circuitry beyond the smaller chip footprint. These surrounding regions commonly have surface depth dimensions divergent from that of the chip, which may cause failure of the cluster probe to correctly interface the chip C4 pads, may cause damage to the surrounding substrate, or may cause the creation of residual debris by an extra the interaction of probe beams with the MCM on smaller chip sites. The removal of residual debris is a significant and expensive problem for large-scale MCM production.  
         [0008]     Prior art methods for testing MCM&#39;s that have non steppable C4 pattern include “Full Cluster Probe Test” and “Flying Probe Test methods.” The Full Cluster Probe Test uses a probe that covers the entire MCM surface C4 pattern comprising all of the chips at once and performs a single step test. This is a high throughput electrical test method, but it requires a huge resource investment on tester and probe. One exemplary MCM may require a probe with approximately 50,000 points and a series of automatic micro adjustment mechanisms. The product-specific manufacturing costs for such a full cluster probe test is enormous, perhaps in the neighborhood of five to six million dollars, and therefore not practical.  
         [0009]     The Flying Probe Test tests one net at a time, wherein a single test probe is positioned by a precision x,y table and is put in contact with the MCM C4 pads via a z-motion actuation. This method is most appropriate for latent defect testing of glass-ceramic and thin-film wiring using EMT electronics and for opens/shorts testing at levels in thin films where product design features do not allow cluster probing or for high volume products. Advantages include the absence of significant product-specific fit-up costs and minimal lead time to manufacturing operations. However, disadvantages occur from multi-hour cycle times when used on complex MCM substrates with very high net counts and the resulting high operational costs and high number of required testers to provide the necessary capacity. This method does not require big investment on tooling, but it is a low throughput test method and cannot handle high volume production and is therefore not practical for large scale MCM production.  
         [0010]     What is needed is a high throughput electrical test method for complex MCM&#39;s. Specifically, what is needed is a test method that utilizes a conventional Step and Repeat Cluster Probe Tester to test complex MCM&#39;s that do not have a normal step-able C4 pattern: MCM&#39;s comprising chips that have different sizes, sharing a common pitch but with divergent C4 footprints with non-repeating C4 patterns.  
       SUMMARY OF THE INVENTION  
       [0011]     A system and method for utilizing a multi-probe tester to test an electrical device having a plurality of contact pads. Multi-probe tester test probes and electrical device contact pads are arrayed in a common distribution pitch, and a means for masking test probes masks at least one test probe, thereby preventing the at least one test probe from returning a test result to the testing apparatus. In one embodiment the means for masking test probes is a mask membrane physically preventing at least one test probe from making contact with the electrical device. In another embodiment, the means for masking is at least one software command configured to cause an input from at least one test probe to be disregarded during a test routine. Another embodiment features both mask membrane and software command probe masking. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a set of top plan of an MCM.  
         [0013]      FIG. 2  is a side sectional view of a chip residing on the MCM of  FIG. 1 .  
         [0014]      FIG. 3  is a side perspective illustration of a prior art step and repeat cluster probe tester apparatus.  
         [0015]      FIG. 4  is a side sectional view of a typical buckling beam cluster probe tester, illustrated stepping on an array of typical C4 features.  
         [0016]      FIG. 5  is a top plan view of a mask according to the present invention.  
         [0017]      FIG. 6  is a top plan view of a mask and frame assembly according to the present invention positioned upon a MCM with cluster probe tester and MCM footprints superimposed.  
         [0018]      FIG. 7  is a side view of a mask and frame assembly according to the present invention positioned upon an MCM substrate.  
         [0019]      FIG. 8  is a top detail plan view of a mask aperture and MCM chip from  FIG. 6 .  
         [0020]      FIG. 9  is a side sectional view of a cluster probe tester, mask and MCM according to the present invention 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]     The present invention is a test method and system that utilizes “masking” methods with a conventional Step and Repeat Cluster Probe Tester to test complex MCM&#39;s comprising different size chips sharing a common pitch but with divergent C4 footprints with non-repeating C4 patterns. These types of complex MCM&#39;s thus have surface features that are not appropriate for testing through a normal stepable C4 pattern.  
         [0022]     Referring now to  FIG. 5 , a self-locate mask  400  according to the present invention is shown. The mask provides a template that exposes only the chip features to be tested through a plurality of mask apertures  402 . Each aperture  402  has a shape designed to expose only those chip areas to be tested to the cluster probe arm  202 . For example, it is readily apparent from the drawings that aperture  402   a  has a much smaller opening area than that of  402   b.    
         [0023]     One embodiment of the mask  400  is manufactured from a sheet of Kapton™, made by Dupont, Inc., with thickness of from about 2 to about 3 mils. However, many other thin, flexible and resilient materials may be suitable for the mask (such as Mylar), and the invention is not limited to the present embodiment.  
         [0024]     The present mask  400  may also define frame alignment apertures  404 . These small apertures  404  are formed to receive alignment dowels  406 , which project from a self-locating frame  500 . It is preferred that the mask  400  placed on the alignment frame  500  through alignment with the dowels  406 , then firmly affixed to the frame  500  through an adhesive means. Once the adhesive means is set the dowels  406  are preferably removed from the mask  400  and frame  500 . Then the assembly of the frame  500  and mask  400  may be quickly applied and removed from a corresponding MCM  510  being tested, enabling improved efficiencies in testing time requirements. One embodiment of the frame  500  is plastic; however any light-weight rigid frame material is suitable, and the invention is not limited to the present embodiment.  
         [0025]      FIG. 6  is a top plan view of an assembly  501  of the mask  400  and frame  500  positioned upon a complex MCM  502  according to the present invention.  FIG. 7  is a side view of the assembly  501 , and  FIG. 8  is a top detail plan view of a mask aperture  402   a  and MCM chip  510   a  from  FIG. 6 . Vertical interior frame surfaces  572  rest against MCM exterior substrate vertical surfaces  571 , and horizontal bottom frame surfaces  574  rest against MCM substrate top surfaces  573 , wherein these surface interactions cause the frame  500  to be aligned upon the MCM substrate  502 , and accordingly the mask  400  apertures  402  with the chips  510 . As illustrated the superimposed cluster probe tester footprint  520  is the same for each “step and repeat” test iteration for each chip  510 . What is new is that the mask  400  prevents unwanted cluster probe  304  contact with regions beyond the mask apertures  402  by providing a physical barrier. The probes  304  located outside the mask aperture  402  define an excluded footprint  822  of mask contact points  824  which are brought into contact with the mask upper surface  410 . Only the probes  304  located within the aperture  402  define a contact array  826  that contacts the chip  510   a,  and in particular the TSM pads  124  located thereupon. This prevents damage to MCM regions surrounding specific chips  502 ; the creation of debris through undesirable probe  304  contact with surrounding substrate  502  materials; and false test results from the inadvertent testing of surrounding circuit features that should be excluded during the test sequence.  
         [0026]     Where the mask is made from Kapton™ or other non-conductive materials, then the probes  304  contacting the mask surface  410  will not form an electrical connection to any other circuit point, and thus false electrical connection test results will be prevented. Although this mask behavior is preferred, the mask surface  510  may also be comprised of conductive materials: for example, wiring (not shown) may be present on the mask surface  510  to from selective probe  310  electrical connections. Alternatively, regions of the mask (not shown) may also be selectively conductive, if required for testing requirements. Thus the present invention is not restricted to non-conductive mask surface  410  materials.  
         [0027]     The TSM pads  124  typically have a diameter of about 4 mils, although the present invention is adaptable to other diameters.  
         [0028]      FIG. 9  depicts another embodiment of the present invention. A Kapton™ mask  600  is shown deployed upon an MCM  602  top surface. The mask  600  forms an aperture  604 , through which a chip  610  projects. A buckling beam cluster probe tester  620  is shown “stepped” onto the mask  600  and chip  610 , wherein cluster probes  640  are brought into contact with the chip  610  and mask  600 . Probes  640   x  make an electrical connection with TSM pads  624 , and probes  640   z  contact the mask  600 .  
         [0029]     An advantage of a typical buckling beam cluster probe tester  620  is that the “buckling beam” probes  640  are configured to exert a constant or maximum force over a range of probe travel and corresponding compressive deflection. Any MCM cluster probe array must typically allow for 3 mils of travel to account for typical MCM surface feature depth differences. In order to accommodate the thickness of the Kapton™ mask  600  of the present embodiment, as well as the MCM  602  surface feature depth differences, it is preferred that the beam probes  640  utilized with the present invention accommodate about 6 plus mils of travel differential between the probes  640   x  in compressive electrical connection with the TSM pads  624  and the probes  640   z  in compressive contact the mask  600 . However, other buckling beam probes (not illustrated) with a larger or smaller range of travel per constant or maximum compressive force output may be utilized with the present invention, and the invention is not limited to the exemplary embodiments described herein. What is important is that the forces exerted by the probes  640  do not vary greatly over the travel differential: once a beam  640  is buckled, additional travel does not exert substantially more force upon either the MCM  602  or mask  620 , thus enabling masks of a thickness within the range of travel adaptable for use with invention.  
         [0030]     In another embodiment of the invention a method of programming a cluster probe tool application program (TAP) is provided. Configuration mask commands are input into the TAP. When present in the test data these mask commands isolate extra probe beams  304  by creating “don&#39;t care” terminals on the product  510  being tested. The input switches for masked addresses are deactivated so connections from the output terminal to them cannot cause an error in a short scan and avoid putting out invalid “open” result addresses for the extra probe beams. Exemplary commands are “SH” (Reset All Masks); “SA” (Reset All Masks at specified electronic address and higher); “SB” (Reset mask at all other addresses); and “SU” (Set mask at specified electronic address).  
         [0031]     As is well known in the art, step and repeat cluster probe “probe points”  304  used to contact the TSM C4 pads  124  are assigned electronic addresses by the TAP. Where the probe points  304  shown in  FIG. 4  may be labeled in a consecutive fashion with labels  304   a  through  304   k,  an exemplary address table may read as follows:  
                                   Electronic Address   Probe Point                   00001   304a       00002   304b       00003   304c       00004   304d       00005   304e       00006   304f       00007   304g       00008   304h       00009   304i       00010   304j       00011   304k;                  
 
         [0032]     where the electronic address are matrix address corresponding to specific probe points  304 .  
         [0033]     For a “Shorts Scan” of an MCM using a prior art cluster probe tester, if there is a short between probe points  304   a  and  304   b,  and these probes are within an area surrounding the chip  510  and therefore not in contact with the chip  510  TSM C4 pads  124 , the tester may nevertheless detect and report a short during the shorts scan. Thus a “false” short caused by conductive debris deposited upon a mask surface on the MCM may be reported as a circuit failure However, if we wish to avoid a specific probe point short test, according to the present invention we may enable the mask bit at matrix address 00001 by the “set mask command”: 
        Test Command=SU00001.        
 
         [0035]     Now when the cluster probe “shorts scan” test is run the short between probe points  304   a  and  304   b  would not be found. In a similar fashion, for an “Opens Detection” test, according to the present invention unused electronic addresses are disabled by using the SU command for each probe point to be disregarded.  
         [0036]     It is preferred that the commands are input to the TAP corresponding to each chip  510  appearing on the MCM  502 . Thus, specific commands are correlated to the specific mask apertures: for example, some commands are input for a test sequence operating upon aperture  402   a;  and other set of commands for aperture  402   b;  a third set of commands for aperture  402   c.    
         [0037]     In one embodiment of the present invention  15  mask commands are available for TAP input, however the present invention may be practiced with more or less commands. Cluster probe tester TAP&#39;s are unique to each testing apparatus, with each manufacturer utilizing its own proprietary TAP. The present invention may be adapted to be practiced with any TAP by the manufacturer, or by an end user with the cooperation of the manufacturer. Referring again to  FIG. 3 , an embodiment of the invention described above may be tangibly embodied in a in a computer program residing on a computer-readable medium or carrier  224 . The medium  224  may comprise one or more of a fixed and/or removable data storage device such as a floppy disk or a CD-ROM, or it may consist of some other type of data storage or data communications device. The computer program may be loaded into the memory  222  to configure the processor  220  of the cluster probe tester apparatus  200  control system  204  for execution. The computer program comprises instructions which, when read and executed by the processor  220  causes the processor  220  to perform the steps necessary to execute the steps or elements of the present invention.  
         [0038]     In one embodiment of the present invention, one cluster probe design covers all signal nets for all five different chips.  
         [0039]     Alternatively, the present invention may be practiced with the TAP command sets alone without any physical mask element. In this embodiment commands are input into the TAP to prevent false test results, without the need for a physical masking element to provide a physical mask barrier: undesired connections or test results are disregarded through the TAP.  
         [0040]     While preferred embodiments of the invention have been described herein, variations in the design may be made, and such variations may be apparent to those skilled in the art of testing electronic devices, as well as to those skilled in other arts. The materials identified above are by no means the only materials suitable for the manufacture of the embodiments described herein, and substitute materials will be readily apparent to one skilled in the art. The scope of the invention, therefore, is only to be limited by the following claims.