Abstract:
A bus driving circuit includes a majority voter unit for comparing the number of logic high level bits with the number of logic low level bits among a predetermined number of bits of data; a latch unit for latching a first output signal in response to the compared result; and a flip-flop unit for latching the predetermined number of bits of data in synchronization with the clock; and a selection unit for selecting one of the latched data of the flip-flop unit and an inverted output of the latched data of the flip-flop unit according to the first output signal.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a bus driving circuit; and, more particularly, to a bus driving circuit for reducing simultaneous switching noise output (SSO) and power consumption by using a clocked voter circuit capable of high-speed data transfer.  
       DESCRIPTION OF RELATED ARTS  
       [0002]      FIG. 1  is a block diagram showing a codec (encoder/decoder) circuit included in a conventional bus driving circuit disclosed in the reference “A 50% noise reduction interface using low-weight coding” (Nakamura, K.; Horowitz, M. A.; VLSI Circuits, 1996).  
         [0003]     Referring to  FIG. 1 , an analog majority voter included in the codec circuit generates a sign signal SIGN if an 8-bit data is inputted to the analog majority voter. The codec circuit uses an exclusive OR gate in order to synchronize an output of the analog majority voter with a clock CLK.  
         [0004]      FIG. 2  is a schematic circuit diagram showing the analog majority voter shown in  FIG. 1 .  
         [0005]     As shown in  FIG. 2 , the analog majority voter receives a plurality of outputs X 0  to X 7  from an internal logic circuit to thereby determine which one of the two logic states, i.e., a logic high level and a logic low level, is more frequent than the other among the plurality of outputs. For instance, if the number of logic high levels is equal to or greater than 4 among 8-bit data received from the internal logic circuit, the sign signal SIGN is outputted as a logic high level. On the other hand, if the number of logic high levels is smaller than 4, the sign signal SIGN is outputted as a logic low level.  
         [0006]     According to the sign signal SIGN, a selection circuit selects to thereby output an unimpaired data or an inverted data. However, since the conventional bus driving circuit uses the analog majority voter as a majority voter, the conventional bus driving circuit is disadvantageous for high-speed operation.  
       SUMMARY OF THE INVENTION  
       [0007]     It is, therefore, an object of the present invention to provide a bus driving circuit for reducing a simultaneous switching noise output (SSO) and power consumption by using a clocked voter circuit capable of high-speed data transfer in a dynamic random access ram (DRAM) or a graphic DRAM which requires a high-speed data rate.  
         [0008]     In accordance with an aspect of the present invention, there is provided a bus driving circuit, including: a majority voter unit for comparing the number of logic high level bits with the number of logic low level bits among predetermined number of bits of data; a latch unit for latching a first output signal in response to the compared result; and a flip-flop unit for latching the predetermined number of bits of data in synchronization with the clock; and a selection unit for selecting one of the latched data of the flip-flop unit and an inverted output of the latched data of the flip-flop unit according to the first output signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0010]      FIG. 1  is a block diagram showing a codec (encoder/decoder) circuit included in a conventional bus driving circuit;  
         [0011]      FIG. 2  is a schematic circuit diagram showing an analog majority voter shown in  FIG. 1 ;  
         [0012]      FIG. 3  is a schematic circuit diagram depicting a bus driving circuit in accordance with a preferred embodiment of the present invention; and  
         [0013]      FIG. 4  is a symbol diagram showing a latch unit shown in  FIG. 3 .  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]     Hereinafter, a bus driving circuit in accordance with the present invention will be described in detail referring to the accompanying drawings.  
         [0015]      FIG. 3  is a schematic circuit diagram depicting a bus driving circuit in accordance with a preferred embodiment of the present invention.  
         [0016]     As shown, the bus driving circuit includes majority voters  100  and  300 , an input terminal control unit  200 , a precharge unit  400 , a latch unit  500 , an enable unit  600 , an RS latch unit  700 , a D-flip flop DFF, a multiplexer  800  and a data bus inversion (DBI) flag pin  900 .  
         [0017]     Herein, the majority voter  100  includes a plurality of n-type metal oxide semiconductor (NMOS) transistors N 1  to N 8 . The plurality of NMOS transistors N 1  to N 8  are connected between the latch unit  500  and the enable unit  600  in order to receive an 8-bit data D&lt;7:0&gt; through each gate terminal. The input terminal control unit  200  includes an NMOS transistor N 9  connected between the latch unit  500  and the enable unit  600 . The NMOS transistor N 9  receives a power supply voltage through a gate of the NMOS transistor N 9  so that the NMOS transistor N 9  is constantly turned on.  
         [0018]     The majority voter  300  includes a plurality of NMOS transistors N 10  to N 17 . The plurality of NMOS transistors N 10  to N 17  are connected between the latch unit  500  and the enable unit  600  in order to receive an inverted 8-bit data /D&lt;7:0&gt; through each gate terminal. The precharge unit  400  includes a plurality of p-type metal oxide semiconductor (PMOS) transistors P 1  to P 3  in order to receive a clock CLK through a commonly coupled gate terminal.  
         [0019]     Herein, the PMOS transistor P 1  is connected between the power supply voltage and a voltage Va. Similarly, the PMOS transistor P 2  is connected between the power supply voltage and a voltage Vb. The PMOS transistor P 3  is connected between gates of PMOS transistors P 4  and P 5 .  
         [0020]     The latch unit  500  includes the PMOS transistors P 4  and P 5  and NMOS transistors N 18  and N 19 . Herein, the PMOS transistor P 4  and the NMOS transistor N 18  are connected in series between the power supply voltage and the majority voter  100  in order to receive the voltage Vb through a commonly coupled gate terminal. The PMOS transistor P 5  and the NMOS transistor N 19  are connected in series between the power supply voltage and the majority voter  300  in order to receive the voltage Va through a commonly coupled gate terminal.  
         [0021]     The enable unit  600  includes NMOS transistors N 20  and N 21  connected in series among the majority voters  100  and  300  and a ground voltage. Herein, the NMOS transistor N 20  receives the clock CLK through a gate of the NMOS transistor N 20 . A gate of the NMOS transistor N 21  receives the power supply voltage so that the NMOS transistor N 21  is constantly turned on.  
         [0022]     The RS latch unit  700  includes RS latch-type NAND gates ND 1  and ND 2  in order to generate output signals Q and Qb having an opposite phase after latching the voltage Va and Vb.  
         [0023]     The D-flip flop DFF flip flops the 8-bit data D&lt;0:7&gt; in synchronization with the clock CLK in order to output the flip flopped signal to a buffer BUF and an inverter IV 2 .  
         [0024]     The multiplexer  800  selects one of an output of the buffer BUF and an output of the inverter IV 2  according to the output signal Q in order to generate an output data D 1 &lt;0:7&gt;.  
         [0025]     The DBI  900  receives the output signal Qb through a flag pin to output an inverted signal to a data bus of an external chip set.  
         [0026]      FIG. 4  is a symbol diagram showing the latch unit  500  shown in  FIG. 3 .  
         [0027]     As shown, the latch unit  500  can be symbolized by a cascoded circuit structured by inverters IV 3  and IV 4 . The inverters IV 3  and IV 4  respectively invert the voltages Va and Vb.  
         [0028]     An operation of the bus driving circuit is described below in detail referring to  FIGS. 3 and 4 .  
         [0029]     The enable unit  600  enables the majority voters  100  and  300  and the input terminal control unit  200  when the NMOS transistor N 20  is turned on in response to an activation of the clock CLK. Herein, the NMOS transistor N 21  is constantly in the turned on state because the gate of the NMOS transistor N 21  receives the power supply voltage.  
         [0030]     The input terminal control unit  200  is constantly turned on since the power supply voltage is supplied to the gate of the NMOS transistor N 9 . The input terminal control unit  200  is provided to an input terminal of the majority voter  100  to thereby prevent a meta stable state. Herein, at the meta stable state, the number of ‘0’s is equal to the number of ‘1’s among the 8-bit data D&lt;7:0&gt;.  
         [0031]     Thereafter, the 8-bit data D&lt;7:0&gt; including ‘0’ or ‘1’ is inputted to the majority voter  100  through the NMOS transistors N 1  to N 8 . The inverted 8-bit data /D&lt;7:0&gt; including ‘0’ or ‘1’ inverted by the inverter IV 1  is inputted to the majority voter  300  through the NMOS transistors N 10  to N 17 .  
         [0032]     The D-flip flop DFF flip flops the 8-bit data D&lt;7:0&gt; and outputs the flip flopped data in synchronization with the clock CLK. The buffer BUF buffers the output of the D-flip flop DFF so that the buffered signal is inputted to the multiplexer  800 . The inverter IV 2  inverts the output of the D-flip flop DFF so that the inverted signal is inputted to the multiplexer  800 . Herein, a delay time generated while a signal is passed through the D-flip flop DFF and the inverter IV 2  is the same as a delay time generated while a signal is passed through the majority voters  100  and  300  and the RS latch unit  700 .  
         [0033]     While the conventional bus driving circuit uses an exclusive OR gate for a synchronization with the clock CLK, in accordance with the present invention, the latch unit  500  and the precharge unit  400  are provided to the majority voters  100  and  300  so that the majority voters  100  and  300  are directly synchronized with the clock CLK.  
         [0034]     That is, the majority voters  100  and  300  operated by the clock CLK respectively receive the 8-bit data D&lt;7:0&gt; and the inverted 8-bit data /D&lt;7:0&gt; from an internal logic circuit in order to determine which one of the two logic states is more frequent than the other. For instance, if the number of logic low levels is equal to or greater than 4 among the received 8-bit data D&lt;7:0&gt; or the inverted 8-bit data /D&lt;7:0&gt;, a high level signal is outputted to the latch unit  500 . On the other hand, if the number of logic high levels is smaller than 4, a high level signal is outputted to the latch unit  500 .  
         [0035]     Thereafter, the latch unit  500  rapidly changes levels of the voltages Va and Vb to a high level or a low level. Herein, since the latch unit  500  includes the cascoded inverters IV 3  and IV 4 , the voltages Va and Vb can be changed rapidly. That is, when the voltage Va is a high level, the NMOS transistor N 19  is turned on so that the voltage Vb becomes a low level according to the output of the majority voter  300 . When the voltage Vb is at a high level, the voltage Va becomes a low level according to the output of the majority voter  100 . Herein, when the clock CLK is inactivated as a low level, all the PMOS transistors P 1  to P 3  included in the precharge unit  400  are turned on so that the voltage Va and Vb are precharged to the power supply voltage level.  
         [0036]     Thereafter, the output of the latch unit  500  is inputted to the RS latch unit  700 . Then, the output signal Qb of the RS latch unit  700  is inputted to the DBI flag pin  900 . The output signal Q is inputted to the multiplexer  800 .  
         [0037]     Therefore, the multiplexer  800  selects one of the output of the buffer BUF and the output of the inverter IV 2  according to the output signal Q in order to output the selected signal as the output data D 1 &lt;0:7&gt;.  
         [0038]     That is, when the voltage Va is a high level and the voltage Vb is a low level, the multiplexer  800  selects the output of the inverter IV 2  according to the output signal Q in order to output the output data D 1 &lt;0:7&gt; as an inverted data. On the other hand, when the voltage Va is a low level and the voltage Vb is a high level, the multiplexer  800  selects the output of the buffer BUF according to the output signal Q in order to output the output data D 1 &lt;0:7&gt; as an non-inverted data.  
         [0039]     For instance, when the 8-bit data D&lt;0:7&gt; is [01110011], the number of ‘1’s is more frequent than that of ‘0’s. Accordingly, the voltage Va is a low level and the voltage Vb is a high level. The output signal Q of the RS latch unit  700  is inputted to the multiplexer  800  and the output signal Qb is inputted to the DBI  900  and, thus, it is detected that the output data D 1 &lt;0:7&gt; outputted from the multiplexer  800  is an non-inverted data.  
         [0040]     As above-mentioned, in accordance with the present invention, a simultaneous switching noise output (SSO) and a power consumption of a bus driving circuit can be reduced by using the clocked voter circuit capable of high-speed data transfer.  
         [0041]     The present application contains subject matter related to Korean patent application No. 2005-91684 and 2005-117123 filed in the Korean Patent Office on Sep. 29, 2005 and Dec. 2, 2005, respectively, the entire contents of which being incorporated herein by reference.  
         [0042]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.