Abstract:
The present invention relates to integrated circuits. In particular, it relates to an IC comprising a receiving stage for receiving an input signal, an output stage for generating an output signal having a larger voltage range than the input signal and a level shifter. Embodiments of the invention provide a structure and a method for fabricating the IC wherein the level shifter is incorporated within the IC to improve reliability of the IC.

Description:
BACKGROUND 
   In an integrated circuit (IC), it is not uncommon for both high and low voltage devices to be included on the same IC. For example, the IC may include 1.5V digital core device and 6V high voltage devices. The supply voltages for such 1.5V and 6V devices are 0.95V (DV DD ) and 3.4V (V H ), respectively. 
   Level shifters are used to transform a digital core device or transistor digital power supply (DV DD ) voltage signal to a high power device or transistor power supply (V H ) voltage signal.  FIG. 1  shows a conventional level shifter for transforming a DV DD  voltage signal to a V H  voltage signal. As shown, the level shifter includes an input stage  101  and an output stage  103 . The input stage receives an input voltage V in  and generates an output voltage V out . V in  is a DV DD  voltage signal having a voltage range of about 0-0.95V while V out  is a V H  voltage signal having a voltage range of about 0-3.5V. 
   The various stages of the level shifter employ 6V high voltage devices with a V H  supply source. Devices typically have a minimum ‘turn on’ threshold voltage (Vth) of about 15% of the supply voltage, i.e., for 6V high voltage devices, this equates to approximately 0.9V. As such, V in  has about a 5% margin to switch on the 6V devices. Taking into consideration temperature fluctuation as well as process variations, such a small margin can lead to situations where the high voltage devices fail to switch on, rending the level shifter inoperable. 
   From the foregoing, it is desirable to provide an improved level shifter for transforming a low voltage range signal to a high voltage range signal. 
   SUMMARY 
   The present invention relates to level shifters used in integrated circuits. In one aspect of the invention, an IC with an input stage for receiving input signal with a first input voltage range further comprises three stages for generating an output signal having a second voltage range. The second stage in the aforementioned three stages of this IC decreases the magnitude of the first stage voltage to the third stage voltage to improve reliability. 
   In another aspect of the invention, a method of fabricating a semiconductor device is presented. The method includes providing an input stage for receiving an input signal having a first voltage range, and an output stage for generating an output signal having a second voltage range. The input stage has three stages with the first stage being coupled to a high voltage source and the third stage being coupled to a low voltage source and the second or intermediate stage decreases the magnitude of the first stage voltage to the third stage voltage to improve reliability. 
   These and other objects, along with advantages and features of the present invention herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a conventional level shifter; 
       FIG. 2  illustrates a robust level shifter in accordance with one embodiment of the invention; and 
       FIG. 3  illustrates simulated waveform results in accordance with one embodiment of the invention. 
   

   DESCRIPTION 
   Embodiments generally relate to ICs. The ICs can be any type of IC, for example dynamic or static random access memories, signal processors, or system-on-chip devices. The ICs can be incorporated into, for example, consumer electronic products, such as computers, cell phones, and personal digital assistants (PDAs). Embodiments can also relate to other types of applications. One embodiment relates to a level shifter. The level shifter, for example, is incorporated into an IC. 
     FIG. 2  shows an embodiment of a level shifter  200 . As shown, the level shifter comprises input and output stages  210  and  260 . The input stage receives an input signal V in . The input signal comprises a first voltage range from, for example, 0-V 1 . The input stage generates an output signal. In one embodiment, the output signal comprises a second voltage range, for example, from 0-V 2 . V 1  in one embodiment is equal to DV DD  while V 2  is equal to V H . DV DD , for example, may be the power supply for digital core devices or transistors of the IC while V 2  may be the power supply for high power devices or transistors. DV DD , for example, may be equal to about 0.95V and V H , for example, may be equal to about 3.4V. Other values for DV DD  and V H  are also useful. 
   The input stage, in one embodiment, comprises first and second current paths  212  and  214 . Providing the input stage with other number of current paths may also be useful. The first and second current paths may be separated into first, second or intermediate and third stages  220 ,  230  and  240 . In one embodiment, the first stage comprises first transistors M 9  and M 10 . The first transistors comprise high voltage transistors, for example, 6V transistors. In one embodiment, the first transistors are p-type field effect transistors (pFETs). Other types of transistors, such as n-type field effect transistors (nFETs) or a combination of pFETs and nFETs, are also useful. As shown, the first transistors have a first terminal coupled to V H , the power supply for high voltage transistors. The first transistors have gate terminals that are cross coupled to second terminals of the first transistors. 
   The third stage comprises third transistors M 1  and M 2  disposed in the first and second current paths. In accordance with one embodiment of the invention, the third transistors comprise low power transistors. As shown, the third transistors are low voltage nFETs. However, other types of transistors, such as pFETs or a combination of pFET and nFET, are also useful. In one embodiment, an inverter  248  is provided to invert V in  (V inB ) to the third transistor gate terminal in the second current path. The second terminals of the third transistors are commonly coupled to ground (V SS ). 
   The intermediate stage is disposed between the first and third stages. The first terminals of the intermediate stage are coupled to the first stage and the second terminals are coupled to the third stage. In one embodiment, the second stage comprises second transistors in the first and second current paths. The second stage serves to decrease the voltage received from the first stage at the first terminals and provides the reduced voltage to the third stage at the second terminals. The second stage, in one embodiment, reduces the voltage to an intermediate voltage (V int ). V int  is equal to a voltage between V H  and DV DD . In one embodiment, V int  is sufficiently reduced to improve reliability of the third transistors. For example, the intermediate stage reduces the voltage to the third stage to below about 1.65V for 1.5V transistors. Decreasing the voltage in the third stage to other values is also useful. 
   In one embodiment, the intermediate stage comprises a combination of high and low voltage transistors M 3 -M 8  in the first and second current paths. As shown, second transistors M 5 -M 8  may be high voltage transistors configured in a diode connection. In one embodiment, second transistors M 7  and M 8  have their gate terminals coupled to V H  while M 5  and M 6  have their gate terminals coupled to respective first or drain terminals. In another embodiment, second transistors M 3  and M 4  are low voltage transistors having their gate terminal coupled to DV DD . Other combinations of second transistors to achieve the desired voltage to third stage are also useful. For example, the number of diode-connected transistors M 5  and M 6  may be increased in order to achieve a greater reduction at the second terminal. 
   As an example, the standard operating voltage for 1.5V transistors is 1.5V±10%. This means that the voltage on the drain terminals of the low voltage transistors should be lowered down to 1.65V or less. Second transistors M 3 -M 8  are used to reduce the voltage to the third stage. The gate terminals of second transistors M 7  and M 8  are connected to V H . 
   As such, the maximum voltage at nodes N 3  and N 4  will be equal to about V H -Vth_DG, where Vth_DG is the threshold voltage of a high voltage device. Second transistors M 5  and M 6  are diode-connected transistors which are used to further lower down the level of voltage passing through M 5  and M 6 . Thus the maximum voltage at node N 1  and N 2  will be further reduced to V H −Vth_DG−Vth_DG. The gates of second transistors M 3  and M 4  are connected to DV DD . Second transistors M 3  and M 4  are also used to reduce the level of voltage passing through M 3  and M 4 . 
   Thus the maximum voltage level at nodes N 1 X and N 2 X will be DV DD -Vth_nfet where Vth_nfet is the threshold voltage of a low-voltage device (e.g., 1.5V device in this case). 
   When V in =0V and V inB =DV DD , third transistor M 1  is turned off and third transistor M 2  is turned on. The drain to source voltage (V DS ) of second transistor M 3  is equal to about V H −Vth_DG×2−(DV DD −Vth_nfet), which is about 1V in current design at the worst case. The V DS  of second transistor M 4  is zero. The drain to gate voltage |V DG | of second transistor M 3  is equal to about V H −Vth_DG×2−DV DD , which for example can be about 0.8V at the worst case. The |V DG | of second transistor M 4  can be equal to about DV DD . When V in =DV DD  and V inB =0V, third transistor M 2  is turned off and third transistor M 1  is turned on. The V DS  of second transistor M 4  is V H −Vth_DG×2−(DV DD −Vth_nfet), which is about 1V in current design at the worst case. The V DS  of second transistor M 3  is zero. The |V DG | of second transistor M 4  is V H −Vth_DG×2−DV DD , which for example can be about 0.8V at the worst case. The |V DG | of the second transistor M 3  is DV DD . 
   In one embodiment, the output stage comprises an inverter circuit. The inverter circuit can comprise high voltage transistors M 11  and M 12 . In one embodiment, M 12  comprises a p-type transistor and M 11  comprises an n-type transistor. The first terminal of M 12  is coupled to V H . The second terminal of M 12  is coupled to the first terminal of M 11  while the second terminal of M 11  is coupled to V SS . The gate terminals of M 11  and M 12  are commonly coupled to the second terminal of M 10  of the first input stage. Other configurations of the output stage are also useful. 
     FIG. 3  shows simulated voltage waveforms of a level shifter in accordance with one embodiment. The level shifter was simulated at different temperature conditions. In particular, waveforms  301  show voltage characteristics of the level shifter at −40° C. and waveforms  302  show voltage characteristics of the level shifter at 125° C. The DV DD  and V H  are not changed for both temperature conditions. 
   In both cases, the voltage drop V DS  across M 3  (or M 4 ) does not exceed the upper limit of the operating range of the transistor which is 1.5V+10%, thus demonstrating robustness of the present invention as well as the capability to work under ‘worst case’ situations. Worst case refers to process parameters which are shifted to Fast-N-Fast-P corner. Under such conditions, voltage stress on the drain &amp; gate-oxide of M 3  (or M 4 ) is at its largest. 
   In particular, the threshold voltage Vth changes with temperature. For example, Vth increases as temperature is reduced. The extreme worst case is when V in  is at ultra low voltage with process parameters shifted to fast corner under low temperature. As process is shifted to fast corner, Vth is increased. When temperature is reduced at fast corner, Vth is increased further. Thus the margin to turn on the device becomes smaller and critical under such conditions. In conventional level shifters, Vth can be higher than V in , causing turn on failure for the device. This results in non operability of the level shifter. In contrast to conventional applications, the present invention prevents the possibility of Vth from being higher than V in  without increasing stress on the gate oxide of the device. 
   As apparent from  FIG. 3 , the present invention provides a reliable level shifter which can be implemented without the use of native devices, such as those which have a negative or zero V th . This results in reduced manufacturing cost since no additional mask or process steps are needed. 
   Furthermore, using low voltage devices as third transistors and lowering the voltage across the third transistors results in a larger operating window. In addition, this larger operating window is achieved without incurring high voltage stress on the drain and gate oxide of the low voltage devices, increasing the lifespan of the devices. 
   The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of the equivalency of the claims are intended to be embraced therein.