Abstract:
A DRAM stack capacitor and a fabrication method thereof has a first capacitor electrode formed of a conductive carbon layer overlying a semiconductor substrate, a capacitor dielectric layer and a second capacitor electrode. The first capacitor electrode is of crown shape geometry and possesses an inner surface and an outer surface. The DRAM stack capacitor features the outer surface of the first capacitor electrode as an uneven surface.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor and a fabrication method thereof, and in particularly relates to a dynamic random access memory (DRAM) stack capacitor and a fabrication method thereof. 
         [0003]    2. Description of the Related Art 
         [0004]    Conventionally, various methods for increasing the capacitance of the dynamic random access memory stack capacitor have been proposed. 
         [0005]    For example, in U.S. Pub. No. 2007/0001208, a dynamic random access memory stack capacitor and a fabrication method thereof are disclosed. In the fabrication method, a sacrificial dielectric layer is used to form a crown-shaped capacitor electrode made of conductive carbon. Because the capacitor electrode possesses inner and outer surfaces, the effective area of the capacitor electrode is larger so that capacitance increases. As shown in  FIG. 1 , the dynamic random access memory stack capacitor includes a semiconductor substrate  1 , an etching stop layer  3 , a lower capacitor electrode  6 , a capacitor dielectric layer  9 , and an upper capacitor electrode  8 . The etching stop layer  3  includes a conductive region  2  for electrically connecting the stack capacitor to the semiconductor substrate  1 . 
         [0006]    A novel dynamic random access memory stack capacitor and a fabrication method thereof, which further raises the effective area of the capacitor electrode for increasing capacitance, is thus desirable. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    In one embodiment of the invention, a fabrication method for a dynamic random access memory stack capacitor is disclosed. The fabrication method comprises the steps of: disposing a plurality of semi-spherical grains on sidewalls of an opening in a sacrificial layer over a substrate; filling the opening with a first conductive material; removing the sacrificial layer and the semi-spherical grains to form a first electrode, wherein a plurality of arc-shape cavities are formed on an outer surface of the first electrode; forming a dielectric layer on the first electrode; and forming a second conductive material over the first electrode to form a second electrode. 
         [0008]    In another embodiment of the invention, a structure of a dynamic random access memory stack capacitor is also disclosed. The structure comprises a substrate, a conductive layer on the substrate, a lower electrode on the conductive layer, an upper electrode on the lower electrode, and an insulting layer interposed between the upper and lower electrodes. Specifically, the structure features the formation of a plurality of arc-shaped cavities on an outer surface of the first electrode. 
         [0009]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0011]      FIG. 1  is cross section of a fabrication method for a conventional DRAM stack capacitor; and 
           [0012]      FIG. 2˜9  are cross sections of an embodiment of a method for fabricating a DRAM stack capacitor according to the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0014]    One embodiment discloses a fabrication method for a dynamic random access memory stack capacitor according to the invention. 
         [0015]    As shown in  FIG. 2 , an etching stop layer  3  and a sacrificial dielectric layer  4  having an opening  10  is formed on a semiconductor substrate  1  in sequence. Typically, the semiconductor substrate  1  is made up of a silicon wafer including metal layers (not shown), interlayer dielectric layers (not shown) and other elements (for example, a metal oxide semiconductor field effect transistor). The etching stop layer  3  uses materials such as silicon nitride. The sacrificial dielectric layer  4  uses materials such as silicon dioxide. The formation of the etching stop layer  3  includes typical deposition processes. The sacrificial dielectric layer  4  having an opening  10  is formed, for example, by typical photolithography processes. The etching stop layer  3  has a conductive region  2  which is exposed via the opening  10 , and the conductive region  2  is typically made up of TiSi x , CoSi x , NiSi x , or doped semiconductor materials. 
         [0016]    As shown in  FIG. 3 , a layer  12  of semi-spherical grains is then formed covering the sacrificial dielectric layer  4  and the sidewalls and bottom of the opening  10 . The layer  12  of semi-spherical grains uses materials such as silicon, and the formation thereof includes a typical epitaxy processes. 
         [0017]    As shown in  FIG. 4 , a typical photolithograph process or an etching process is performed on the layer  12  of semi-spherical grains to leave a pattern  12 ′ of semi-spherical grains on the sidewalls of the opening  10 . For example, a photoresist material (not shown) is used to fill the opening  10  and to cover the surface of the sacrificial. dielectric layer  4 . Thereafter, the photoresist material is patterned, and the photoresist material outside the opening  10  is then removed. Next, the layer  12  of semi-spherical grains is partly removed except for the part remaining on the sidewalls of the opening  10  i.e. the pattern  12 ′ of semi-spherical grains. Each semi-spherical grain of the pattern  12 ′ has a diameter between 5 and 50 nm. 
         [0018]    As shown in  FIG. 5 , a conductive material  14  is utilized to fill the opening  10  and to cover the surface of the sacrificial dielectric layer  4 . The conductive material  14 , for example, is conductive carbon. Due to the deposition process of the conductive material  14 , a void  16  is thus formed within the opening  10 . 
         [0019]    A recess etching process is performed to open the void  16  within the opening  10  and to remove the conductive material from the surface of the sacrificial dielectric layer  4 , thus, the residual conductive material covering the pattern  12 ′ of semi-spherical grains and the bottom of the opening  10  serves as a first capacitor electrode  14 ′ (i.e. the lower electrode). The recess etching process is performed using oxygen or argon plasma, for example. 
         [0020]    As shown in  FIG. 7 , the sacrificial dielectric layer  4  is removed to expose the surface (i.e. the outer surface) of the first capacitor electrode  14 ′ possessing the pattern  12 ′ of semi-spherical grains and a portion of the surface of the etching stop layer  3 . The removal of the sacrificial dielectric layer  4  includes an etching process. 
         [0021]    As shown in  FIG. 8 , the pattern  12 ′ of semi-spherical grains on the outer surface of the first capacitor electrode  14 ′ is then removed, thus, leaving a wavy surface on the outer surface of the first capacitor electrode  14 ′. That is, arc-shaped cavities are formed on the outer surface of the first capacitor electrode  14 ′. The formation increases the effective area of the outer surface of the first capacitor electrode  14 ′, thus, leading to increased capacitance. 
         [0022]    As shown in  FIG. 9 , a capacitor dielectric layer and a second capacitor electrode  18  (i.e. the upper capacitor) are formed on the exposed surfaces of the first capacitor electrode  14 ′ and the etching stop layer  3  in sequence. The first capacitor electrode  14 ′, the capacitor dielectric layer and the second capacitor electrode  18  constitute a capacitor. The capacitor dielectric layer can be high dielectric constant materials, such as Al 2 O 3 , Ta 2 O 5 , TiO 2  or ferroelectrics, and the formation thereof can be by chemical vapor deposition. The second capacitor electrode  18  can use materials such as metal or conductive carbon, and the metal materials can be Pt, Ir, Ru, or Pd. The formation of the second capacitor electrode  18  includes chemical vapor deposition, physical vapor deposition or reactive ion sputtering. In other embodiments, the second capacitor electrode  18  can use metal oxide such as IrO 2  or RuO 2 . 
         [0023]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.