Abstract:
Provided is a structure for testing a NAND flash memory including a first string select transistor for controlling transfer of a voltage inputted via a first bit line; a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program or erase state depending on a voltage inputted thereto; a second string select transistor for controlling transfer of a voltage inputted via a second bit line; a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program or erase state depending on a voltage inputted thereto; and a measurement pad connected to a point where the first or second string select transistor and the flash memory cell are connected.

Description:
BACKGROUND  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a structure for testing a NAND flash memory and a method of measuring a channel voltage of the NAND flash memory using the same and, more particularly, to a structure for testing a NAND flash memory having a structure capable of measuring a channel voltage, and a method of measuring the channel voltage of the NAND flash memory using the same.  
           [0003]    2. Discussion of Related Art  
           [0004]    Recently, there is an increasing demand for semiconductor memory devices that are electrically programmed and erased and on which data can be stored without being erased even in a state where the power is not supplied. Further, in order to develop a large-capacity memory device capable of storing a large quantity of data, a high-integration technology of the memory cell has been developed. For this, there was proposed a NAND type flash memory device in which a plurality of memory cells are serially connected to form a single string and a plurality of the strings constitute a single memory cell array.  
           [0005]    The flash memory cells of the NAND flash memory device include a current path formed between the source and drain on a semiconductor substrate, and a floating gate and a control gate that are connected over the semiconductor substrate with an insulator intervened between them. Further, the program operation of the flash memory cell is performed by making a source region of the memory cell and the semiconductor substrate, i.e., a bulk region grounded, applying a positive high voltage (program voltage; Vpp, for example 15V to 20V) to the control gate, and a voltage for a program (for example, 5 to 6V) to the drain of the memory cell, in order to generate hot carriers. The hot carriers are generated as electrons of the bulk region are accumulated on the floating gate due to an electric field of the high voltage (Vpp) applied to the control gate and charges supplied to the drain region are continuously accumulated.  
           [0006]    The erase operation of the flash memory cell is simultaneously performed in a sector unit sharing the bulk region, by applying a negative high voltage (erase voltage; Vera, for example −10V) to the control gate and applying a given voltage (for example 5V) to the bulk region to cause fowler-nordheim tunneling (F-N tunneling). F-N tunneling causes the electrons accumulated on the floating gate to be discharged toward the source region, so that the flash memory cells has distribution of the erase threshold voltage ranging from about 1V to 3V.  
           [0007]    The memory cell the threshold voltage of which was increased by the program operation looks turned off since current is prevented from being injected from the drain region to the source region upon the read operation. The cell the threshold voltage of which was lowered by the erase operation looks turned on since current is injected from the drain region to the source region.  
           [0008]    [0008]FIG. 1 is a layout view showing a conventional NAND flash memory.  
           [0009]    First to sixteenth cell regions Cell- 1  to Cell- 16  where cells are formed are positioned in a longitudinal direction with them spaced apart. Each of the cell regions is positioned to increase in a horizontal direction. Further, active regions A 1  and A 2  where the cells are formed are positioned in the longitudinal direction so that they intersect the respective cell regions. Drain select lines DSL 1  and DSL 2  are positioned at an upper side of the first cell region Cell- 1  in the longitudinal direction wherein the drain select lines are positioned to increase in the horizontal direction. The drain select line DSL 2  is also used in another upper array. Further, source select lines SSL 1  and SSL 2  are positioned at a lower side of the sixteenth cell region Cell- 16  in the longitudinal direction wherein the source select lines are positioned to increase in the horizontal direction. The source select line SSL 2  is also used in another lower array. Drain contacts D 1  and D 2  are formed at regions where between—the drain select lines DSL 1  and DSL 2  and the active regions A 1  and A 2  are intersecting. Source contact S 1  and S 2  are formed at regions where between—the source select lines SSL 1  and SSL 2  and the active regions A 1  and A 2  are intersecting.  
           [0010]    [0010]FIG. 2 is a schematic cross-sectional view of the NAND flash memory taken along lines A-A in FIG. 1.  
           [0011]    A field oxide film  20  is formed in a semiconductor substrate  10  wherein a triple well is formed. First to sixteenth cells c 1  to c 16  are formed at the semiconductor substrate  10  between the field regions  20 . A transistor d for selecting a string is formed at the left side of the first cell c 1  wherein a gate of the transistor d is connected to the drain select line DSL 1 . A transistor s for connecting to a common source line is formed at the right side of the sixteenth cell c 16  wherein a gate of the transistor s is connected to the source select line SSL 1 .  
           [0012]    [0012]FIG. 3 is a circuit diagram of the NAND flash memory shown in FIG. 1.  
           [0013]    The first to sixteenth cells c 1  to c 16  are serially connected in a first string st 1 . A drain of the first cell c 1  is connected to a first bit line b 1  through the string select transistor d. A source of the sixteenth cell c 16  is connected to a common source line S 1  through the source select transistor s. A second string st 2  has the same structure to the first string st 1 .  
           [0014]    Upon a program operation, a voltage of 0V is applied to selected bit lines and Vcc is applied to non-selected bit lines. Further, a voltage (Vpgm) of, for example, 18V is applied to selected word lines, a voltage of, for example, 4.5V is applied to the drain select lines DSL and a voltage of 0V is applied to the source select lines SSL, respectively. A voltage (Vpass) of, for example, 10V is applied to non-selected word lines. The cells that are selected according to these voltage conditions are programmed. However, if Vcc is applied to non-selected strings, i.e., strings for which a program is inhibited so as to prevent program disturbance, Vpass is applied to non-selected word lines and Vpgm is applied to selected word lines, cells in the non-selected string perform a self-boosting operation. At this time, the voltage applied to the string is referred to as a channel boosting voltage, which is usually kept about 6V to 8V. Program disturbance depends on whether the channel voltage is high or low.  
           [0015]    [0015]FIG. 4 is an equivalent circuit diagram of the non-selected string for calculating the channel boosting voltage.  
           [0016]    Referring to FIGS. 3 and 4, the channel boosting voltage can be calculated as follows.  
           [0017]    In case of a 16 cell array, the channel boosting voltage (Vch) is: 
           Vch=15 K (Vpass−Vchini)−Vthl+ K (Vpgm-Vchini-Vth2)+Vchini-Ileak*Tpw/Ctot 
           [0018]    where,  K =Cono*Cox/(Ctot*(Cono+Cox))=Cini/Ctot 
           [0019]    Vchini (transfer bit line voltage)=Vcc−Vt 13  select (threshold voltage of a select transistor)  
           [0020]    Vth1: Threshobld voltage of non-selected cells  
           [0021]    Vth2: Threshold voltage of selected cells  
           [0022]    Ileak: String leakage current  
           [0023]    Cono: ONO capacitance  
           [0024]    Cox: Capacitance of tunnel oxide films  
           [0025]    Ctot: Total capacitance  
           [0026]    The boosting channel voltage calculated by the above equation is about 1 to 9V, which may differ depending on a program condition.  
           [0027]    Such a boosting channel voltage plays an important role in deciding cell characteristics. This serves as an important factor in analyzing program disturbance. As this boosting channel voltage can be obtained only through calculation in the prior art, there is a significant difference between an actual value and a calculated value. In a real program, an electric field (Eox) of the tunnel oxide film that causes program disturbance in the program inhibit cell becomes Eox=(Vpgm−Vch+Vth 0 )Kg/Tox.  
           [0028]    where, Vth 0 ; Initial voltage  
           [0029]    Kg: ONO coupling ratio  
           [0030]    Tox: Thickness of a tunnel-oxide film  
           [0031]    As described above, the boosting channel voltage becomes an important factor of program disturbance as a variable of Eox. However, there is a problem that analysis of program disturbance is difficult since the method for measuring the boosting channel voltage is not so easy.  
         SUMMARY OF THE INVENTION  
         [0032]    The present invention is contrived to solve the aforementioned problems. The present invention is directed to a method capable of measuring a boosting channel voltage of a NAND flash memory and the NAND flash memory for realizing the same.  
           [0033]    According to one aspect of the present invention, there is provided a structure for testing a NAND flash memory, comprising a first string select transistor for controlling transfer of a voltage inputted via a first bit line; a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program or erase state depending on a voltage inputted thereto; a second string select transistor for controlling transfer of a voltage inputted via a second bit line; a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program or erase state depending on a voltage inputted thereto; and a measurement pad connected to a point where the first or second string select transistor and the flash memory cell are connected.  
           [0034]    According to another aspect of the present invention, there is provided a method of testing a NAND flash memory, including the steps of providing the above-mentioned structure for testing the NAND flash memory; selecting the first or second string, wherein a voltage of 0V is applied to a selected string and Vcc is applied to a non-selected string, while applying a program voltage to control gates of all the flash memory cells in a column to be programmed in the selected string, a pass voltage to control gates of remaining flash memory cells, a first gate voltage to a gate of the string select transistor, and a voltage of 0V to the source select transistor; and measuring a voltage between the measurement pad and a source line. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0035]    The above and other objects, features and advantages of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0036]    [0036]FIG. 1 is a layout view showing a conventional NAND flash memory;  
         [0037]    [0037]FIG. 2 is a cross-sectional view of the NAND flash memory taken along lines A-A in FIG. 1;  
         [0038]    [0038]FIG. 3 is a circuit diagram of the NAND flash memory shown in FIG. 1;  
         [0039]    [0039]FIG. 4 is an equivalent circuit diagram illustrating a program-inhibit bit line in FIG. 3;  
         [0040]    [0040]FIG. 5 is a layout view showing a NAND flash memory according to a first embodiment of the present invention;  
         [0041]    [0041]FIG. 6 is a cross-sectional view of the NAND flash memory taken along lines B-B in FIG. 5;  
         [0042]    [0042]FIG. 7 is a circuit diagram of the NAND flash memory shown in FIG. 5;  
         [0043]    [0043]FIG. 8 is a layout view showing a NAND flash memory according to a second embodiment of the present invention;  
         [0044]    [0044]FIG. 9 is a circuit diagram of the NAND flash memory shown in FIG. 8;  
         [0045]    [0045]FIG. 10 is a layout view showing a NAND flash memory according to a third embodiment of the present invention;  
         [0046]    [0046]FIG. 11 is a cross-sectional view of the NAND flash memory taken along lines A-A in FIG. 10;  
         [0047]    [0047]FIG. 12 is a circuit diagram of the NAND flash memory shown in FIG. 10;  
         [0048]    [0048]FIG. 13 is a layout view showing a NAND flash memory according to a fourth embodiment of the present invention; and  
         [0049]    [0049]FIG. 14 is a circuit diagram of the NAND flash memory shown in FIG. 13. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0050]    The present invention will now be described in detail in connection with preferred embodiments with reference to accompanying drawings.  
         [0051]    [0051]FIG. 5 is a layout view showing a NAND flash memory according to a first embodiment of the present invention.  
         [0052]    First to sixteenth cell regions Cell- 1  to Cell- 16  where cells are formed are positioned in a longitudinal direction with them spaced apart. Each of the cell regions is positioned to increase in a horizontal direction. Further, active regions A 1  and A 2  where the cells are formed are positioned in the longitudinal direction so that they intersect the respective cell regions. Drain select lines DSL 1  and DSL 2  are positioned at an upper side of the first cell region Cell- 1  in the longitudinal direction wherein the drain select lines are positioned to increase in the horizontal direction. The drain select line DSL 2  is also used in another upper array. Further, source select lines SSL 1  and SSL 2  are positioned at a lower side of the sixteenth cell region Cell- 16  in the longitudinal direction wherein the source select lines are positioned to increase in the horizontal direction. The source select line SSL 2  is also used in another lower array. Drain contacts D 1  and D 2  are formed at regions where between—the drain select lines DSL 1  and DSL 2  and the active regions A 1  and A 2  are intersecting. Source contact S 1  and S 2  are formed at regions where between—the source select lines SSL 1  and SSL 2  and the active regions A 1  and A 2  are intersecting.  
         [0053]    Furthermore, a contact K for measuring a boosting channel voltage is formed at a region where between—the drain select line DSL 1  and the first cell region Cell- 1  and the second active region A 2  are intersecting. Also, a metal line L 1  for drawing out the contact K and a metal pad P 1  are, formed.  
         [0054]    [0054]FIG. 6 is a cross-sectional view of the NAND flash memory taken along lines B-B in FIG. 5.  
         [0055]    A field oxide film  20  is formed in a semiconductor substrate  10  wherein a triple well is formed. First to sixteenth cells c 1  to c 16  are formed at the semiconductor substrate  10  between the field regions  20 . A transistor d for selecting a string is formed at the left side of the first cell c 1  wherein a gate of the transistor d is connected to the drain select line DSL 1 . A transistor s for connecting to a common source line is formed at the right side of the sixteenth cell c 16  wherein a gate of the transistor s is connected to the source select line SSL 1 .  
         [0056]    In addition, a contact K for exposing a common diffusion region K 1  of the first cell c 1  and the string select transistor —the gate of the string select transistor is connected to the drain select line DSL 1  —is formed.  
         [0057]    [0057]FIG. 7 is a circuit diagram of the NAND flash memory shown in FIG. 5.  
         [0058]    The first to sixteenth cells c 1  to c 16  are serially connected in a first string st 1 . A drain of the first cell c 1  is connected to a first bit line b 1  through the string select transistor d. A source of the sixteenth cell c 16  is connected to a common source line S 1  through the source select transistor s. A second string st 2  has the same structure to the first string st 1 . Further, the metal line L 1  is drawn out from a point where the string select transistor d of the bit line b 2  for Which the program is inhibited and the first cell c 1  are connected.  
         [0059]    A method of measuring the channel boosting voltage will now be described.  
         [0060]    For a program, a voltage of 0V is applied to selected bit lines and Vcc is applied to non-selected bit lines. Also, a voltage (Vpgm) of, for example, 18V is applied to selected word lines, a voltage of, for example, 4.5V is applied to the drain select lined DSL 1  and a voltage of 0V is applied to the source select lined SSL 1 . In addition, a voltage (Vpass) of, for example, 10V is applied to non-selected word lined. In this state, if the voltage between the metal line L 1  and the common source line is measured, the channel boosting voltage can be obtained.  
         [0061]    [0061]FIG. 8 is a layout view showing a NAND flash memory according to a second embodiment of the present invention.  
         [0062]    First to sixteenth cell regions Cell- 1  to Cell- 16  where cells are formed are positioned in a longitudinal direction with them spaced apart. Each of the cell regions is positioned to increase in a horizontal direction. Further, active regions A 1  and A 2  where the cells are formed are positioned in the longitudinal direction so that they intersect the respective cell regions. Drain select lines DSL 1  and DSL 2  are positioned at an upper side of the first cell region Cell- 1  in the longitudinal direction wherein the drain select lines are positioned to increase in the horizontal direction. The drain select line DSL 2  is also used in another upper array. Further, source select lines SSL 1  and SSL 2  are positioned at a lower side of the sixteenth cell region Cell- 16  in the longitudinal direction wherein the source select lines are positioned to increase in the horizontal direction. The source select line SSL 2  is also used in another lower array. Drain contacts D 1  and D 2  are formed at regions where between—the drain select lines DSL 1  and DSL 2  and the active regions A 1  and A 2  are intersecting. Source contact S 1  and S 2  are formed at regions where between—the source select lines SSL 1  and SSL 2  and the active regions A 1  and A 2  are intersecting.  
         [0063]    Furthermore, a contact g for measuring a boosting channel voltage is formed at a region where between—the source select line SSL 1  and the sixteenth cell region Cell- 16  and the second active region A 2  are intersecting. Also, a metal line L 2  for drawing out the contact g and a metal pad P 2  are formed.  
         [0064]    [0064]FIG. 9 is a circuit diagram of the NAND flash memory shown in FIG. 8.  
         [0065]    The first to sixteenth cells c 1  to c 16  are serially connected in a first string st 1 . A drain of the first cell c 1  is connected to a first bit line b 1  through the string select transistor d. A source of the sixteenth cell c 16  is connected to a common source line S 1  through the source select transistor s. A second string st 2  has the same structure to the first string st 1 . Further, the metal line L 2  is drawn out from a point where the source select transistor s of the bit line b 2  for which a program is inhibited and the sixteenth cell c 16  are connected.  
         [0066]    A method of measuring the channel boosting voltage will now be described.  
         [0067]    For a program, a voltage of 0V is applied to selected bit lines and Vcc is applied to non-selected bit lines. Also, a voltage (Vpgm) of, for example, 18V is applied to selected word lines, a voltage of, for example, 4.5V is applied to the drain select line DSL 1  and a voltage of 0V is applied to the source select lines SSL. In addition, a voltage (Vpass) of, for example, 10V is applied to non-selected word lines. In this state, if the voltage between the metal line L 2  and the common source line is measured, the channel boosting voltage can be obtained.  
         [0068]    [0068]FIG. 10 is a layout view showing a NAND flash memory according to a third embodiment of the present invention.  
         [0069]    First to sixteenth cell regions Cell- 1  to Cell- 16  where cells are formed are positioned in a longitudinal direction with them spaced apart. Each of the cell regions is positioned to increase in a horizontal direction. Further, active regions A 1  and A 2  where the cells are formed are positioned in the longitudinal direction so that they intersect the respective cell regions. Drain select lines DSL 1  and DSL 2  are positioned at an upper side of the first cell region Cell- 1  in the longitudinal direction wherein the drain select lines are positioned to increase in the horizontal direction. The drain select line DSL 1  is also used in another upper array. Further, source select lines SSL 1  and SSL 2  are positioned at a lower side of the sixteenth cell region Cell- 16  in the longitudinal direction wherein the source select lines are positioned to increase in the horizontal direction. The source select line SSL 2  is also used in another lower array. Drain contacts D 1  and D 2  are formed at regions where between—the drain select lines DSL 1  and DSL 2  and the active regions A 1  and A 2  are intersecting. Source contact S 1  and S 2  are formed at regions where between—the source select lines SSL 1  and SSL 2  and the active regions A 1  and A 2  are intersecting.  
         [0070]    Furthermore, a third contact g 3  for measuring a boosting channel voltage is formed at a region where between—the drain select line DSL 2  and the first cell region Cell- 1  and the second active region A 2  are intersecting. Also, a metal line L 3  for drawing out the third contact g 3  is formed.  
         [0071]    Furthermore, a fourth contact g 4  for measuring the boosting channel voltage is formed at a region where between—the drain select line DSL 1  and the first cell region Cell- 1  and the second active region A 1  are intersecting. Also, a metal line L 4  for drawing out the fourth contact g 4  is formed.  
         [0072]    [0072]FIG. 11 is a cross-sectional view of the NAND flash memory taken along lines A-A in FIG. 10.  
         [0073]    A field oxide film  20  is formed in a semiconductor substrate  10  wherein a triple well is formed. First to sixteenth cells c 1  to c 16  are formed at the semiconductor substrate  10  between the field regions  20 . A transistor d for selecting a string is formed at the left side of the first cell c 1  wherein a gate of the transistor d is connected to the drain select line DSL 1 . A transistor s for connecting to a common source line is formed at the right side of the sixteenth cell c 16  wherein a gate of the transistor s is connected to the source select line SSL 1 .  
         [0074]    Further, a contact g 3  for exposing a common diffusion region K 3  of the first cell c 1  and the string select transistor—the gate of the string select transistor is connected to the drain select line DSL 1 —is formed.  
         [0075]    [0075]FIG. 12 is a circuit diagram of the NAND flash memory shown in FIG. 10.  
         [0076]    The first to sixteenth cells c 1  to c 16  are serially connected in a first string st 1 . A drain of the first cell c 1  is connected to a first bit line b 1  through the string select transistor d. A source of the sixteenth cell c 16  is connected to a common source line S 1  through the source select transistor s. A second string st 2  has the same structure to the first string st 1 . Further, the metal line L 3  is drawn out from a point where the string select transistor d of the bit line b 2  for which a program is inhibited and the first cell c 1  are connected. The metal line L 4  is drawn out from a point where the string select transistor d of the bit line b 1  that is selected for a program and the first cell c 1 . The metal line L 3  is connected to a measurement pad Q through the first PMOS transistor P 1  and the metal line L 4  is connected to a measurement pad Q through the second PMOS transistor P 2 . Each of the first and second PMOS transistors P 1  and P 2  is turned on depending on a voltage applied to its gate electrode. At this time, a HVNOS transistor may replace the PMOS transistor.  
         [0077]    A method of measuring the channel boosting voltage will now be described.  
         [0078]    For a program, a voltage of 0V is applied to selected bit lines and Vcc is applied to non-selected bit lines. Also, a voltage (Vpgm) of, for example, 18V is applied to selected word lines, a voltage of, for example, 4.5V is applied to the drain select line DSL 1  and a voltage of 0V is applied to the source select lines SSL. In addition, a voltage (Vpass) of, for example, 10V is applied to non-selected word lines. In this state, if the voltage between. the measurement pad Q 2  and the common source line is measured in a state where the first PMOS transistor P 1  is turned off while the second PMOS transistor P 2  is turned on, the channel boosting voltage can be obtained.  
         [0079]    [0079]FIG. 13 is a layout view showing a NAND flash memory according to a fourth embodiment of the present invention.  
         [0080]    First to sixteenth cell regions Cell- 1  to Cell- 16  where cells are formed are positioned in a longitudinal direction with them spaced apart. Each of the cell regions is positioned to increase in a horizontal direction. Further, active regions A 1  and A 2  where the cells are formed are positioned in the longitudinal direction so that they intersect the respective cell regions. Drain select lines DSL 1  and DSL 2  are positioned at an upper side of the first cell region Cell- 1  in the longitudinal direction wherein the drain select lines are positioned to increase in the horizontal direction. The drain select line DSL 2  is also used in another upper array. Further, source select lines SSL 1  and SSL 2  are positioned at a lower side of the sixteenth cell region Cell- 16  in the longitudinal direction wherein the source select lines are positioned to increase in the horizontal direction. The source select line SSL 2  is also used in another lower array. Drain contacts D 1  and D 2  are formed at regions where between—the drain select lines DSL 1  and DSL 2  and the active regions A 1  and A 2  are intersecting. Source contact S 1  and S 2  are formed at regions where between—the source select lines SSL 1  and SSL 2  and the active regions A 1 , and A 2  are intersecting.  
         [0081]    Furthermore, a contact g 5  for measuring a boosting channel voltage is formed at a region where between—the source select line SSL 1  and the sixteenth cell region Cell- 16  and the second active region A 2  are intersecting. A metal line L 5  for drawing out the contact g 5  is formed. Also, a contact g 6  for measuring the boosting channel voltage is formed at a region where between—the source select line SSL 1  and the sixteenth cell region Cell- 16  and the second active region A 1  are intersecting. A metal line L 6  for drawing out the contact g 6  is formed.  
         [0082]    [0082]FIG. 14 is a circuit diagram of the NAND flash memory shown in FIG. 13.  
         [0083]    The first to sixteenth cells c 1  to c 16  are serially connected in a first string st 1 . A drain of the first cell c 1  is connected to a first bit line b 1  through the string select transistor d. A source of the sixteenth cell c 16  is connected to a common source line S 1  through the source select transistor s. A second string st 2  has the same structure to the first string st 1 . Further, the metal line L 5  is drawn out from a point where the source select transistor s of the bit line b 2  for which a program is inhibited and the sixteenth cell c 16  are connected. The metal line L 6  is drawn out from a point where the source select transistor s of the bit line b 1  that is selected for a program and the sixteenth cell c 1  are connected. The metal line L 5  is connected to a measurement pad Q through the first PMOS transistor P 3 . The metal line L 6  is connected to the measurement pad Q through the second PMOS transistor P 4 . Each of the first and second PMOS transistors P 3  and P 4  is turned on depending on a voltage applied to its gate electrode.  
         [0084]    A method of measuring the channel boosting voltage will now be described.  
         [0085]    For a program, a voltage of 0V is applied to selected bit lines and Vcc is applied to non-selected bit lines. Also, a voltage (Vpgm) of; for example, 18V is applied to selected word lines, a voltage of, for example; 4.5V is applied to the drain select line DSL 1  and a voltage of 0V is applied to the source select lines SSL. In addition, a voltage (Vpass) of, for example, 10V is applied to non-selected word lines. In this state, if the voltage between the measurement pad Q 2  and the common source line is measured in a state where the first PMOS transistor P 3  is turned off while the second PMOS transistor P 4  is turned on, the channel boosting voltage can be obtained.  
         [0086]    At this time, a HVNMOS transistor may replace the first and second PMOS transistors.  
         [0087]    According to present invention described above, it is possible to simply measure the boosting channel voltage of the NAND flash memory.  
         [0088]    Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention.