Abstract:
The ability to repair defective cells in a memory array, by replacing those cells with redundant cells, is improved using a redundant memory line control circuit that employs two types of redundancy programming. Most, or all, redundant memory lines can be programmed while the memory array is in a wafer state by, e.g., cutting laser fuses. But at least one memory line can be programmed subsequent to device packaging (“post repair”) using, e.g., commands that cut electric fuses. Preferably, the redundant memory line(s) that are reserved for post repair are selectable among the same redundant memory lines that can be programmed using laser fuses. This allows all redundant memory lines to be available for laser repair, if needed, but also allows a redundant memory line to be selected for post repair after it has been determined that that redundant memory line is defect-free. This increases the likelihood that a device will be repairable, and yet does not unnecessarily waste redundant memory lines by pre-dedicating them to laser or post repair.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention pertains generally to semiconductor memory device repair structures and repair methods, and more particularly to post-repair structures and methods.  
           [0003]    2. Description of the Related Art  
           [0004]    Semiconductor memory devices, e.g., Dynamic Random Access Memory (DRAM) devices, contain a plurality of memory cells arranged in a row/column array. Each memory cell typically stores one bit of information. The array contains row signal lines, and column signal lines arranged perpendicular to the row lines. A memory cell is placed at each intersection of a row line and a column line. Concurrently addressing the array row line and the array column line that connect to a particular memory cell accesses that memory cell.  
           [0005]    Most uses for semiconductor memory devices require that 100% of the memory cells, row lines, and column lines be operational. In practice, many—even most—main memory cell arrays on a given wafer may fail to achieve 100% operability. Consequently, most device designs incorporate a relatively small redundant array of memory cells that can be substituted for a limited number of defective cells.  
           [0006]    In one common design, the redundant array is configured in redundant columns of memory cells, each connected to a redundant column line that crosses the main memory cell array row lines. Each redundant column line can therefore be substituted for a main memory cell array column found to have one or more defective cells. Each time a column of the main array is addressed, a redundancy control block compares the column address to the defective column address. When the defective column is addressed, the redundancy control block selects the redundant column associated with that defective column address instead.  
           [0007]    A redundancy scheme that replaces defective rows with redundant rows is also in use. Some devices contain redundant rows and redundant columns, with associated circuitry.  
           [0008]    Before a redundancy control block and its associated redundant column/row can be used, the defective line address must be programmed into the control block. To facilitate programming, the redundancy control block contains a fuse block. While the semiconductor memory device is in a wafer state, the main memory array is tested and defective cells are located. Considering, e.g., column replacement, a redundancy control block and redundant column are selected to replace a given defective column. The address of the defective column is set in the redundancy control block by selectively cutting fuses in the fuse block to represent that column address. Fuses are generally programmed using a laser beam to physically sever each fuse to be cut.  
         SUMMARY OF THE INVENTION  
         [0009]    Although most memory array defects are detectable during wafer state testing, some defects may arise—or first become apparent—after a memory device is packaged. For such defects, the ability to repair the memory array after packaging may make the difference between a saleable unit and a scrap unit.  
           [0010]    The repair of array defects after packaging is referred to as a post-repair capability. Laser-cut fuses do not have post-repair capability, as the packaging material prevents laser targeting and fuse cutting. In contrast, the described embodiments all contain a post-repair capability that uses electrically programmable fuse blocks. Such fuse blocks can be programmed after device packaging, using special programming command signaling applied to the device&#39;s normal package connections.  
           [0011]    Although post-repair redundancy is attractive because it allows the correction of defects that arise during packaging, such redundancy does have drawbacks. The post-repair redundancy control block and associated electrical programming circuitry require much more circuit area than a laser-cut fuse redundancy control block. Therefore, the cost of using electrically cut fuses rather than laser-cut fuses, in terms of wafer surface area, may outweigh the benefit of a post-repair capability.  
           [0012]    In a first aspect of this description, a semiconductor memory device is disclosed. The memory device contains a dual-mode redundancy circuit that blends the advantages of wafer-state (e.g., laser-cut) fuse programming with the advantages of post-repair programming. This circuit contains a plurality of redundant memory lines (e.g., additional column or row lines, each addressing redundant cells). Each redundant memory line is associated with an attendant redundancy control block. The majority of the redundant control blocks contain laser fuse blocks, and can only be programmed prior to assembly of the memory device into a package. At least one of the redundant control blocks, however, contains an electrically programmable fuse block, and is capable of being programmed after assembly of the memory device into a package. Accordingly, such a device allows a dual-cycle repair method: most device repairs are made in the wafer state, with more economical laser fuse blocks; a small number of electrical fuse blocks are available and addressable after package assembly, however, in a post-repair mode, in case, e.g., packaging-related defects occur.  
           [0013]    The above design has some redundant memory lines dedicated for laser repair, and some redundant memory lines dedicated for post repair. If a redundant memory line that is dedicated for post repair is itself defective, post repair becomes impossible. This is true even if good redundant laser-repair memory lines remain unused, as those lines cannot be used for post repair.  
           [0014]    Thus, in a second aspect, a dual-mode redundancy circuit contains circuitry for increasing the likelihood that post repair can be effected. Generally, this circuitry allows a wafer-state address-storage-unit (e.g., a laser fuse block) to be associated with a redundant line. In a second configuration, this circuitry allows a post-repair address-storage-unit (e.g., an electric fuse block) to be associated with the same redundant line. Thus, a semiconductor memory device employing this type of dual-mode redundancy allows additional repair flexibility. For instance, during wafer-state testing, by default each redundant line may be associated with a laser fuse block. One defect-free redundant memory line is designated, during testing, for use in post repair. That redundant memory line is associated with the post-repair address-storage-unit, making it available for use in post repair.  
           [0015]    In a related method, the semiconductor device has multiple redundant memory lines, each associated with a laser fuse/comparator. Main and redundant memory lines are tested to determine which lines are defective and which are defect-free. For each defective main memory line, a defect-free redundant memory line is designated, and the laser fuse/comparator associated with that redundant memory line is configured to replace the defective main memory line. When at least one defect-free redundant memory line remains undesignated after this step, at least one remaining defect-free redundant memory line is designated for use in post repair. The post-repair-designated redundant memory line is associated with a post-repair comparator instead of its associated laser fuse/comparator, and is then available for post repair. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    The embodiments may be best understood with reference to the attached drawings in which:  
         [0017]    [0017]FIG. 1 contains a block diagram for a semiconductor memory device according to an embodiment of the invention;  
         [0018]    [0018]FIG. 2 contains a block diagram for a first embodiment of a dual-mode repair circuit;  
         [0019]    [0019]FIG. 3 shows additional circuit detail for the redundancy control blocks of FIG. 2;  
         [0020]    [0020]FIGS. 4, 5, and  6  show additional circuit details for the electric fuse block and address comparator of FIG. 2;  
         [0021]    [0021]FIG. 7 contains a block diagram for a second embodiment of a dual-mode repair circuit, having means for associating an electric fuse block with one of several redundant columns;  
         [0022]    [0022]FIG. 8 shows additional circuit details for the redundancy control blocks of FIG. 7;  
         [0023]    [0023]FIG. 9 illustrates a detailed circuit diagram for the post-repair control blocks of FIG. 7;  
         [0024]    [0024]FIG. 10 plots the waveform diagram of a power-up signal that is input to the post-repair control block of FIG. 9;  
         [0025]    [0025]FIG. 11 illustrates an alternate embodiment for the post-repair control blocks of FIG. 4;  
         [0026]    [0026]FIGS. 12 and 13 contain a repair circuit block diagram and post-repair control block circuit diagram for a third embodiment of a dual-mode repair circuit, with electrical fuse post-repair blocks;  
         [0027]    [0027]FIG. 14 contains a block diagram for a fourth embodiment of a dual-mode repair circuit with two separate post-repair electric fuse blocks, either of which can be associated with any redundant memory line;  
         [0028]    [0028]FIG. 15 contains a block diagram for a fifth embodiment of a dual-mode repair circuit, with redundancy control blocks having the capability to override a failed prior repair attempt; and  
         [0029]    [0029]FIG. 16 illustrates an embodiment of the redundancy control block of FIG. 15. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0030]    [0030]FIG. 1 illustrates a block diagram for a semiconductor memory device  20 —in this case a synchronous DRAM (SDRAM)—according to a first embodiment. Briefly, a main cell array  30  and redundant column cell array  32  are served by row and column circuitry. The column circuitry comprises sense amplifiers  34  and column decoder  50 . Column decoder  50  selects, for each column address CA, the column (bit) line(s) that will be read/written to. Within column decoder  50 , redundant memory line control circuit  100  determines when a redundant column will be substituted for a main column, based on column address CA and column select enable CSLEN.  
         [0031]    The row circuitry comprises row decoder  40  and row address multiplexer  42 . Row decoder  40  selects, for each row address RA, which row (word) line will be activated. Row select enable RSLEN indicates when RA is valid. Although no redundant row lines and circuitry are shown in device  20 , such may exist and would be similar to redundant array  32  and control circuit  100 . Note that RA has two sources, channeled through multiplexer  42 : external row addresses, supplied through address register  80 ; and refresh row addresses, supplied from refresh counter  46 , under the control of refresh controller  44 .  
         [0032]    Circuit input and output occurs through three register sets. Command register  70  receives command signals, such as activate word line, read, write, precharge, auto-refresh, load mode register, etc., over a command bus CMD from, e.g., an external memory controller (not shown). Address register  80  receives address signals ADD[0:m] over an address bus from the memory controller. And data I/O register  90  connects to bi-directional data lines DQ[0:w].  
         [0033]    Command decoder  60  interprets received commands and generates appropriate control signals to the other memory device blocks. Mode register set (MRS)  62  can receive device settings over address bus ADD when a load mode register command is received on the CMD bus. In general, the MRS is used to define SDRAM operational parameters such as burst type, burst length, latency, etc. In the preferred embodiments, one function of the MRS is to set the fuse units in an electrical fuse box to an address supplied on the ADD bus, when a special command is received on the CMD bus.  
         [0034]    Although more advanced features exist in many memory devices to which the present invention is applicable, the preceding description describes the basic features common to most SDRAM devices capable of supporting an embodiment of the present invention. Those features of device  20  that are particularly pertinent to the embodiments will now be explored in further detail.  
         [0035]    [0035]FIG. 2 contains a block diagram of a basic dual-mode redundant column control circuit  100 , according to a first embodiment of the invention. Referring to FIG. 2, redundant column control circuit  100  has an electric fuse box  110 , an address comparator  120 , an electric redundancy control block  131 , laser redundancy control blocks  132  through  13 n, and RCSL (redundant column select) generators  141  through  14 n.  
         [0036]    Redundant column control circuit  100  controls access to n redundant columns in redundant cell array  32  (FIG. 1). One of the n redundant columns is selected, instead of a defective main array column, when a corresponding redundancy column selection signal (RCSLi, i=1˜n) is asserted by an RCSL generator  14 i. Each of the RCSL generators is activated in response to a corresponding RCSL enable signal (RCSLENi, i=1˜n) from a redundancy control block. Each RCSL generator  14 i (i=1˜n) can be implemented using two serially connected inverters (not shown).  
         [0037]    [0037]FIG. 3 shows circuit detail for laser redundancy control blocks  132  to  13 n, as well as for electric redundancy control block  131 . Each laser redundancy control block contains a laser fuse box and address comparator (i.e., a laser fuse/comparator)  150 . A laser beam can cut selected fuses in the laser fuse box during wafer stage repair operations. Thereafter, laser fuse/comparator  150  compares column addresses CA to the defective column address stored in the laser fuse box, and asserts OUT when CA matches the stored address. NAND gate  152 , together with serial inverter  154 , generates RCSLENi according to an AND operation—when both OUT and CSLEN (column select enable) are asserted, RCSLENi will also be asserted, and therefore redundant column i will be selected.  
         [0038]    Electric redundancy control block  131  contains a NAND gate  160  with a serial inverter  162  to generate RCSLEN 1  according to an AND operation—when both EN and CSLEN are asserted, RCSLEN 1  will also be asserted, and therefore redundant column  1  will be selected.  
         [0039]    EN is an output of address comparator  120 , and is asserted when CA matches ECA (FIG. 2). ECA is an electrically stored defective column address from electric fuse box  110 . Thus whereas redundant column lines  2  through n can only be programmed during wafer stage repair, redundant column line  1  can be programmed at any time, e.g., during a post-repair operation.  
         [0040]    [0040]FIGS. 4 and 5 illustrate one embodiment of electric fuse box  110 . Referring first to FIG. 4, electric fuse box  110  contains a plurality of electric fuse units ( 31 a,  31 i, i=0˜k) with buffered outputs. Each electric fuse unit holds one bit of data. Fuse unit  31  a holds bit OUTa, which, after buffering, becomes a master access signal MA that indicates whether the electric fuse box has been programmed. Fuse unit  31 i, i=0˜k, holds OUTi, which, after buffering, becomes an electric column address signal bit ECAi.  
         [0041]    Mode register set (MRS)  62  (FIG. 1) generates the programming inputs (MRSA, MRSCA 0  to MRSCAk) to fuse box  110  in response to an external command. Each electric fuse unit is initially fabricated in a first state, e.g., representing an unset address bit. If a given MRS programming input is asserted, the corresponding electric fuse unit is set to a second state, e.g., representing a set address bit. Thus to program fuse box  110 , MRS  62  places the address of the column under repair on MRSCA 0 -k to program that address, and asserts MRSA to program the master access bit.  
         [0042]    [0042]FIG. 5 is a detailed circuit diagram for one embodiment of an electric fuse unit  31 i (i =a, 0˜k). Each electric fuse unit  31 i has first and second fuses (F 1 , F 2 ), first through fifth NMOS transistors (N 1 ˜N 5 ), and first and second PMOS transistors (P 1 , P 2 ). The drains of NMOS transistors N 1  and N 2 , the drain of PMOS transistor P 1 , the gate of PMOS transistor P 2 , and the gate of NMOS transistor N 3  each connect to a first node  411 . The gate of PMOS transistor P 1 , the gate of NMOS transistor N 2 , the drains of NMOS transistors N 3  and N 4 , and the drain of PMOS transistor P 2  each connect to a second node  412 . The signal present at the second node also forms an output signal (OUT). Each NMOS transistor source is grounded; the sources of P 1  and P 2  connect to VDD, respectively, through fuse devices F 1  and F 2 . The drain of N 5  connects to the source of P 1 .  
         [0043]    Fuse unit  31 i is fabricated such that the resistance of fuse F 2  is larger than the resistance of fuse F 1 . Accordingly, with both fuses intact, node  412  (also tied to OUT) is driven to a logic low condition and node  411  is driven to a logic high condition when the fuse unit is powered.  
         [0044]    A first input signal (MRS 1 ), which is normally in a low state, is input to the gates of NMOS transistors N 1  and N 4 . Input signal MRS 1  is used to test whether or not fuse F 1  is cut, as will be explained shortly.  
         [0045]    A second input signal (MRS 2 ) is input to the gate of transistor N 5 . Input signal MRS 2  is used to electrically cut fuse F 1 . If input signal MRS 2  is set to a “high” logic level, NMOS transistor N 5  is turned on, causing a transient current—large enough to burn fuse F 1 —to flow through fuse F 1 . As fuse F 1  is cut, transistor N 5  also drops the potential at the source of transistor P 1 , and therefore at node  411  as well. As the voltage at node  411  decreases, transistor P 2  is turned on and transistor N 3  is turned off, raising the voltage at node  412 . This in turn tends to turn on transistor N 2 , reinforcing the decreasing voltage at node  411  and the increasing voltage at node  412  until OUT switches to a high logic level.  
         [0046]    After programming, input signal MRS 1  can be used to determine whether the fuse F 1  was fully cut by the assertion of input signal MRS 2 . In a test mode, MRS 1  is momentarily taken to a high state to pull both node  411  and node  412  to a low state. If fuse F 1  has been severed, node  412  recovers to a high state when MRS 1  is taken back to a low state. If fuse F 1  has not been severed, node  411  recovers to a high state when MRS 1  is taken back to a low state.  
         [0047]    Following the assertion/deassertion of MRS 1 , the repaired address line is tested. If the test is unsuccessful, it is assumed that one or more fuses was not completely cut, and therefore the redundant column was not successfully substituted for the defective column. In such a case, the electrical programming and testing steps can be repeated in order to reattempt fuse cutting.  
         [0048]    [0048]FIG. 6 is a detailed diagram for one embodiment of address comparator  120  of FIG. 2. Address comparator  120  has a plurality of comparing units ( 51 i, i=0˜k), and a plurality of AND logic gates (logic gates  520 ,  522 , and  524  shown). Each AND gate is formed using a NAND gate with an inverter at its output.  
         [0049]    Each comparing unit  51 i (i=0˜k) performs a one-bit XNOR function. Comparing unit  51  i receives an electrical repair address bit (ECAi, i=0˜k) and a corresponding external address bit (CAi, i=0˜k), and compares the two bits. If the two bits are at the same logic level, the comparing unit  51 i outputs a high logic level signal. If the two bits are different, the comparing unit  51 i outputs a low logic level signal.  
         [0050]    The output signal from each comparing unit  51 i (i=0˜k) and the master signal (MA) are ANDed and output as an electric repair activation signal (EN). Therefore, when signals output from all comparing units  510  through  51 k are a “high” logic level—and the master access signal is also “high”—the electric repair activation signal (EN) is asserted.  
         [0051]    The redundant column control circuit shown in FIGS.  2 - 6 , and described above, provides improved repair capability as compared to a laser-fuse-only redundancy scheme, since one redundant column is reserved for post repair. At the same time, this embodiment capitalizes on the recognition that most array defects are present and detectable during wafer stage repair, by driving most redundant columns with more economical laser-fuse control circuitry.  
         [0052]    One condition that the embodiment of FIG. 2 cannot correct for is a failure in the redundant column associated with the electric redundancy control block  131 . Were this redundant column to be defective, post repair would be impossible, even if one or more of redundant columns  2  through n were defect-free and unused. In contrast, the second embodiment increases the likelihood that post repair will be possible, by allowing the potential selection of one of several redundant columns for association with electrical redundancy control signals. Preferably, then, a defect-free redundant column can be allocated to post-repair after wafer fabrication. And also preferably, each defect-free redundant column can be, in the alternative, allocated to laser repair.  
         [0053]    [0053]FIG. 7 illustrates redundant column control circuit  200  of the second embodiment. Although similar to FIG. 2 in some ways, FIG. 7 contains post-repair control blocks  251  to  25 n, different redundancy control blocks  231  to  23 n, and control signal differences. These differences will be further explored with reference to FIGS.  7 - 10 . In short, each redundancy control block  23 i has laser fuse functionality, but can be configured to respond to the electric repair activation signal (EN). Thus no one redundant column is unconditionally fabricated for post-repair—all redundant columns can be used for laser fuse repair, if needed, and a defect-free redundant column can be associated, after wafer fabrication, with the post-repair electric fuse circuitry. This flexibility can provide for efficient use of defect-free redundant memory lines in a mix of wafer-stage and post-repair operations.  
         [0054]    Like redundant column control circuit  100  of FIG. 2, control circuit  200  of FIG. 7 has an electric fuse box ( 210 ) that can be set using the mode register set to a desired post repair column address. Address comparator  220  compares address ECA from electric fuse box  210  to column address CA, and asserts EN when ECA and CA match (and master signal MA indicates that ECA is valid).  
         [0055]    Whereas in FIG. 2 only the electric redundancy control block  131  receives EN from the electrical repair address comparator  120 , each redundancy control block  231  to  23 n in FIG. 7 receives EN from address comparator. Each redundancy control block  23 i also receives column address CA, and a control signal CSi from a corresponding post-repair control block  25 i. CSi determines whether redundancy control block  23 i responds to EN, or uses CA in conjunction with a laser fuse/comparator within redundancy control block  23 i to perform redundant column selection. In a typical usage, a fuse will be cut in one (and only one) of post-repair control blocks  25 i to assert a corresponding CSi signal line, indicating the redundant column that will be used for post repair (if needed).  
         [0056]    [0056]FIG. 8 illustrates the internal circuitry of a redundancy control block  23 i. Each redundancy control block  23 i (i=1˜n) outputs a redundancy activation signal (RCSLENi, i =1˜n) to a corresponding RCSL generator  24 i (i=1˜n, FIG. 7). Each redundancy control block  23 i has a laser-repair-processing part  610  for laser repair, and a post-repair-processing part  620  for post repair.  
         [0057]    The laser-repair-processing part  610  contains a laser fuse box  611 , an address comparator  612 , and a first logic unit  613 .  
         [0058]    The laser fuse box  611  has a plurality of fuses that can be cut by a laser beam. By selectively cutting laser fuses with a laser, the laser fuse box is programmed to generate an address LCA indicating a main array column in which a defective cell occurred.  
         [0059]    Like address comparator  220 , address comparator  612  asserts an output signal (OUT) when LCA and an external address (CA) match.  
         [0060]    Logic unit  613  ORs OUT with control signal CSi to generate a first logic signal TS 1 . Thus if post-repair control block  25 i has not asserted CSi (meaning redundancy control block  23 i has not been selected for post repair), TS 1  replicates OUT. But if CSi is asserted, indicating that this is a post-repair block, OUT is overridden, and TS 1  will be asserted regardless of the state of OUT.  
         [0061]    The post-repair-processing part  620  has an inverter  621  and a second logic unit  622 . Inverter  621  generates CSi#, an inverted version of CSi. Second logic unit  622  ORs CSi# with electric repair activation signal EN from electric fuse address comparator  220  to generate a second logic signal TS 2 . Thus if post-repair control block  25 i has asserted CSi, indicating that this is a post-repair block, TS 2  replicates EN. But if CSi is deasserted, EN is overridden, and TS 2  will be asserted regardless of the state of EN. Thus it is evident that redundancy control block  23 i will respond to only one of comparator  612  output signal OUT and electric repair activation signal EN, this selection depending on the state of CSi.  
         [0062]    A third logic unit  631  is shared by laser-repair-processing part  610  and post-repair-processing part  620 . The third logic unit  631  ANDs the first and second logic signals (TS 1 , TS 2 ) together with a column selection signal (CSLEN), and then outputs the redundancy activation signal (RCSLENi, i=1˜n).  
         [0063]    When a read or write command is received by the semiconductor memory device, an external column address CA (specifying the main array column to be accessed) accompanies the command. When the main column specified by CA has not been repaired, no repair fuse box (laser or electrical) will contain that address. When the main column specified by CA has been replaced with a redundant column during wafer-stage laser-fuse repair, that column address will have been stored in laser fuse box  611  of one of redundancy control blocks  23 i. And when the main column specified by CA has been replaced with a redundant column during post-repair, that column address will have been stored in electric fuse box  210 . CA is supplied to the address comparator  612  of each redundancy control block  23 i, as well as to electric fuse address comparator  220  (FIG. 7). Each address comparator compares CA to its stored address (laser-fuse address LCA for a comparator  612 , electric fuse address ECA for comparator  220 ). For a defective but repaired main column, one of the address comparators will detect a match for CA, and will assert its output signal (OUT for a comparator  612 , EN for comparator  220 ). If the main column specified by CA has not been repaired, no comparator will assert its output signal.  
         [0064]    The first or primary mode of operation for each redundancy control circuit  23 i responds to a laser-fuse-programmed repair address. In this mode, CSi is deasserted, TS 1  responds to OUT, and TS 2  is always asserted. Thus when CA and LCA match—and CSLEN is asserted, indicating a column select output is appropriate—redundant column select signal RCSLENi is asserted. Otherwise, RCSLENi remains deasserted.  
         [0065]    The alternate mode of operation for redundancy control circuit  23 i responds to the electric-fuse-programmed repair address. In this mode, CSi is asserted, TS 1  is always asserted, and TS 2  responds to EN. Thus when CA and ECA are matched by address comparator  220 —and CSLEN is asserted, indicating a column select output is appropriate—redundant column select signal RCSLENi is asserted. Otherwise, RCSLENi remains deasserted.  
         [0066]    In the embodiment of FIG. 7, at most one of redundancy control blocks  23 i will be set in the alternate mode of operation. All other redundancy control blocks are set to the primary mode of operation. Which control block  23 i is set in the alternate mode of operation is determined by the state of post-repair control blocks  25 i. Essentially, each post-repair control block  25 i contains a fuse or other settable element. For instance, FIG. 9 contains a circuit diagram for one post-repair control block embodiment.  
         [0067]    In FIG. 9, a post-repair control block  25 i contains a post-repair fuse  710 . Post-repair fuse  710  is a laser fuse that can be cut during wafer stage testing to change the state of control signal CSi. That is, when post-repair fuse  710  is left intact, CSi will remain at a low logic level, and when post-repair fuse  710  is cut, CSi attains a high logic level.  
         [0068]    Post-repair control block  25 i contains, in addition to fuse  710 , two PMOS transistors P 3  and P 4 , one NMOS transistor N 6 , and two inverters  712  and  714 . PMOS transistors P 3  and P 4  each have a source connected to VDD and a drain connected to one end of fuse  710  (node  810 ). NMOS transistor N 6  has its source connected to ground and its drain connected to the opposite end of fuse  710 .  
         [0069]    Node  810  also connects to the input of inverter  712 . Node  812  connects the output of inverter  712  with both the input of inverter  714  and the gate of PMOS transistor P 4 . The output of inverter  714  is taken as the control signal CSi.  
         [0070]    The input signal to post-repair control blocks  25 i is a power-up signal VCCH. The waveform of power-up signal VCCH is shown in FIG. 10. Power-up signal VCCH is at a low logic level when power is first supplied to the semiconductor memory device (time T 1 ), and transitions to a high logic level once the power supply level reaches a predetermined level (at time T 2 ). Power-up signal VCCH is supplied to the gates of transistors P 3  and N 6 .  
         [0071]    Post-repair control block  25 i operates as follows. First, consider control block  25 i with post-repair control fuse  710  cut. When the semiconductor memory device first powers on (time T 1 , FIG. 10), VCCH remains at a low logic level, turning on transistor P 3 . Since fuse  710  is cut, node  810  charges towards VDD. Node  810  will eventually be recognized by inverter  712  as a logic high level, driving node  812  to a low logic level and CSi to a high logic level.  
         [0072]    At time T 2  on FIG. 10, the power-up signal (VCCH) switches to a high logic level. Although setting VCCH to a high logic level turns off PMOS transistor P 3 , by this time the low logic level at node  812  has turned on PMOS transistor P 4 , thus maintaining the high logic level at node  810 —and a high logic level for the control signal CSi.  
         [0073]    Now consider the case where post-repair control fuse  710  is intact at power-up. In this state, node  810  initially attains a high logic level, as when fuse  710  is cut. But when power-up signal VCCH switches to a high logic level, transistor N 6  is turned on, transistor P 3  is turned off, and node  810  discharges toward ground. Inverter  712  senses a low logic level on node  810  and takes node  812  to a high logic level, turning off P 4 . Inverter  714  outputs a low logic level for control signal CSi.  
         [0074]    With this embodiment, the redundant column line i that will be available for post repair is preferably selected while the device is in a wafer state. For instance, the redundant column lines can be tested to determine a redundant memory line that is defect-free. The defect-free redundant memory line is then designated for use in post repair. The designated memory line is associated with the post-repair address comparator  220  by cutting the laser fuse  710  in the post-repair control block associated with that memory line.  
         [0075]    Also preferably, the selection of a redundant memory line for use in post repair can be accomplished in conjunction with a wafer stage laser fuse repair operation. For example, the main and redundant column lines can be tested at the wafer stage to determine which lines are defective and which are defect-free. For each defective main array column line, a defect-free redundant memory line is designated, and the laser fuse box  611  (FIG. 8) associated with that redundant memory line is programmed with the address of that defective main array column line. Then, when all defective main memory lines have been repaired and defect-free redundant memory lines remain undesignated, one of those remaining defect-free redundant memory lines is designated for use in post repair. The designated redundant memory line is associated with the post-repair address comparator  220  by cutting the laser fuse  710  in the post-repair control block associated with that memory line.  
         [0076]    Subsequently, the memory device is packaged and subjected to a second test. If a memory column is found to be defective in the packaged state, repair is attempted by issuing a command that causes mode register set  260  to set electric fuse box  210  with the defective column&#39;s address. If a post-repair block  25 i was available after laser repair and designated for post repair, post repair should be possible.  
         [0077]    Although it is preferable to select a column for post repair during wafer stage test and programming, other embodiments are possible. For instance, FIG. 11 illustrates an alternate post-repair control circuit embodiment  27 i that allows selection of a column for post repair through a bonding pad  830 . In one state, bond pad  830  is left disconnected. NMOS transistors N 7 , N 8 , N 9  pull node  820  low, causing inverters  720  and  722  to register a low logic level for CSi. In an alternate state, bond pad  830  is connected to VDD, thus setting node  820  and CSi to a high logic level. To set CSi high and select a given redundant column for post repair, bond pad  830  could be wire-bonded to a VDD pad during wire bonding. Alternately, bond pad  830  could be wire-bonded to a lead on a chip carrier, and that lead could be connected to VDD, external to the device, to select the corresponding redundant column for post repair.  
         [0078]    Another alternate selection embodiment is illustrated in FIGS. 12 and 13. This embodiment allows selection, after packaging, of a redundant column for association with post-repair comparator  220 . In FIG. 12, each post-repair control block  28 i (i=1˜n) is electrically programmable through a corresponding control line MRSPRCi from mode register set  290 . To associate a given post-repair control block  28 i with electric fuse box address comparator  220 , a command is issued with an address that asserts the control line MRSPRCi, thus cutting an electrical fuse in post-repair control block  28 i and causing control signal CSi to become asserted.  
         [0079]    In this embodiment, one difficulty may be in determining which redundancy control blocks  23 i (and corresponding column lines) are still available and defect-free. To alleviate this problem, each post-repair control block  28 i contains a laser fuse that will prevent the electrical fuse in that post-repair control block  28 i from being cut. Thus, during wafer stage programming, as each redundancy control block  23 i is used for laser repair, a laser fuse in the corresponding post-repair control block  28 i is also cut to prevent electrical programming of that post-repair control block. When a given redundant column is found to be defective, the laser fuse in the corresponding post-repair control block  28 i can also be cut to prevent electrical programming of that post-repair control block.  
         [0080]    Then, during post repair of a defective column, selection and electrical fuse cutting of a post-repair control block  28 i is attempted for a first value of i. If, after this first selection, the defective column has not been repaired, it can be assumed that post-repair control block  28 i was disabled. A new value of i is selected, and the process is repeated, until either a successful repair is completed, or all values of i have been unsuccessfully used, at which time post repair has failed.  
         [0081]    [0081]FIG. 13 illustrates one possible circuit useful as post-repair control block  28 i. Fuse  730  is an electrical fuse. Control block  28 i operates similar to control block  25 i (FIG. 9), in that, with fuse  730  intact, CSi is at a low logic level after power-up, and with fuse  730  blown, CSi is at a high logic level after power-up. To cut fuse  730 , MRSPRCi is asserted, turning on transistor P 7  and causing a large transient current to flow through fuse  730 . Note that this current also flows through fuse  740 , and therefore fuse  740  should be designed to handle this current without blowing first.  
         [0082]    To prevent the programming of control block  28 i to a high logic level, fuse  740  is laser cut. When fuse  740  is cut, a transient current through fuse  730  will not be generated when MRSPRCi is asserted.  
         [0083]    Although the preceding embodiments have illustrated circuits that allow a single post-repair operation, the invention is not so limited. For instance, FIG. 14 contains a block diagram for a repair circuit embodiment  900  capable of performing two post-repair operations. Repair circuit  900  has redundancy control blocks  931  through  93 n, RCSL generators  941  through  94 n, and post-repair control blocks  951  through  95 n, similar to the post-repair circuit  200  shown in FIG. 7. However, repair circuit  900  has two electric fuse boxes  911  and  912  and two address comparators  921  and  922 , unlike the post-repair circuit  200 .  
         [0084]    The two electric fuse units,  911  and  912 , are separately programmable through mode register set signals MRS 1  and MRSCAi. Note that one mode register set signal can be used by the electric fuse units to gate the remaining mode register set signals, such that each electric fuse unit can be programmed independently.  
         [0085]    Fuse unit  911  generates a first electric column address ECA 1 , and fuse unit  912  generates a second electric column address ECA 2 . Address comparator  921  compares CA with ECA 1  and asserts a first enable signal EN 1  when a match is detected. Address comparator  922  compares CA with ECA 2  and asserts a second enable signal EN 2  when a match is detected.  
         [0086]    The first and second enable signals (EN 1 , EN 2 ) are input to the redundancy control blocks  931  through  93 n.  
         [0087]    The redundancy control blocks  931  through  93 n may perform laser repair or post-repair according to the control signals (CSi, i=1˜n) from the post-repair control blocks  951  through  95 n, and the first and second electric repair activation signals (EN 1 , EN 2 ). In circuit  900 , however, each control signal CSi comprises two signal lines: one signal line CSi- 1  is paired with EN 1 , and the other signal line CSi- 2  is paired with EN 2 . Redundancy control block  93 i will function as a laser repair block when CSi- 1  and CSi- 2  are both at a low logic level. Redundancy control block  93 i will function as a post-repair control block, responding to repair address ECA 1 , when CSi- 1  is at a high logic level and CSi- 2  is at a low logic level. And redundancy control block  93 i will function as a post-repair control block, responding to repair address ECA 2 , when CSi- 1  is at a low logic level and CSi- 2  is at a high logic level.  
         [0088]    To generate two control signals, each post-repair block  95 i contains two laser fuses and two sets of circuitry similar to that shown in FIG. 9.  
         [0089]    [0089]FIG. 15 contains a block diagram for a variation on the repair circuit embodiment  200  of FIG. 12. This embodiment allows correction of two possible failure cases that cannot be corrected by the FIG. 12 embodiment. The first failure case is a column that has been laser repaired, but the repair column associated with the laser repair has subsequently failed. The second failure case is a column that has been designated as a post-repair column, but after this repair attempt it is discovered that the designated post-repair column is faulty. In either case, the FIG. 12 embodiment cannot enact a further repair of that specific address with a different redundant column, as two different repair columns would be activated by that address.  
         [0090]    To cover these failure cases, the FIG. 15 embodiment extends the concept of the post repair control block override. The concept is further applied between redundancy control blocks. As shown, redundancy control block  291 , generates an override signal OVR 1  to redundancy control block  292 ; redundancy control block  292  generates an override signal OVR 2  to redundancy control block  292 , and this pattern repeats down to redundancy control block  29 n. Any redundancy control block receiving a low logic level on its input override signal performs two functions in response: one, it passes the low logic level down to the next redundancy control block on its own generated override signal; two, it blocks its own RCSLEN signal from being asserted, even if an address match exists that would otherwise cause that RCSLEN signal to be asserted. A redundancy control block will also assert its own generated override signal when not blocked, and an address match occurs with its programmed address.  
         [0091]    In practice, with this embodiment redundancy control blocks  29 i and post repair control blocks  28 i can be used starting from block n, and proceeding upward towards block  1 . For example, assume that during laser repair, several defective columns are repaired—the last of which is repaired by laser-programming a given repair address RA 3  into redundancy control block  293 , leaving redundancy control blocks  292  and  291  available for post repair (post repair control blocks  283  through  28 n are accordingly disabled during laser repair, as described previously). Redundancy control block  293  asserts RCSLEN 3  whenever CA equals RA 3  and CSLEN is enabled.  
         [0092]    Then, after packaging and during post repair testing, a failure is detected for address RA 3 . This most likely means that a failure has occurred on the redundant column associated with redundant control block  293 . But the post repair test cannot tell that this address has already been repaired once, and so it attempts to repair the address again. Address RA 3  is first programmed into electric fuse box  210 . The repair system then attempts to program post repair control block  28 n, but this block was disabled during laser repair, and so the attempt was unsuccessful. The repair system attempts to program control block  28 (n−1), etc., up to control block  282 , before it successfully programs a post repair control block. CS 2  transitions to a logic high level once programming is complete.  
         [0093]    Now, when column RA 3  is tested, CA matches ECA. Thus EN and CS 2  are both asserted, and control block  292  asserts RCSLEN 2  to selects its associated redundant column. Concurrently, redundancy control block transitions its override signal OVR 2  to a low logic level. Redundancy control block  293 , sensing that OVR 2  is now at a low logic level, blocks RCSLEN 3  from being asserted, even though its own internal address comparator detects a match.  
         [0094]    Taking this example one step further, it is also possible that the repair column associated with RCSL 2  is defective. Thus despite the electric post repair, a defect (perhaps a different defect) still occurs when column RA 3  is tested. The post repair system has one more post repair control block,  281 , to use, and so it programs post repair control block  281 . Now, both CS 1  and CS 2  are asserted. When CA equals RA 3 , redundancy control blocks  291 ,  292 , and  293  sense an internal address match. But block  291 , having priority with its OVR 1  signal, blocks redundancy control block  292  from asserting RCSLEN 2  (block  292  in turn blocks redundancy control block  293 ).  
         [0095]    [0095]FIG. 16 illustrates one example of a redundancy control block  29 i that accomplishes the functions just described. Laser fuse box  611  and address comparator  612  function as described previously with respect to FIG. 8. Logic unit  613  NORs OUT with control signal CSi to generate a first logic signal TS 1 #. Second logic unit  622  NORs CSi# with electric repair activation signal EN to generate a second logic signal TS 2 #. NOR gate  641  takes TS 1 # and TS 2 # as inputs, and produces an input to a third logic unit  631 . The other inputs to logic unit  631  are CSLEN and OVR(i−1). Logic unit  631  ANDs these three signals together to produce the column select enable signal RCSLENi. Note that when OVR(i−1) is at a logic low level, it effectively inhibits the assertion of RCSLENi.  
         [0096]    Two additional logic gates are used to create the output override signal OVRi. Inverter  642  inverts OVR(i−1). NOR gate  643  accepts (as inputs) the output of NOR gate  641  and the output of inverter  642 . The output of NOR gate  643  forms the output override signal OVRi. During operation, OVRi is forced low whenever OVR(i−1) is low. OVRi is also forced low if both TS 1 # and TS 2 # are low, indicating that redundancy control block  29 i has detected an address match.  
         [0097]    Many variations on the illustrated embodiments are possible. For instance, the association between redundancy control blocks and redundant memory lines could have multiple possible configurations. Where some redundancy control blocks have dual-mode (wafer-stage laser fusing and post-repair programming) capability, this capability need not extent to all redundancy control blocks. Likewise, where two post-repair address/compare units are present, one of the address/compare units can be programmable among a subset of the redundancy control blocks, and the other unit can be programmable among a mutually exclusive subset—thus alleviating the need for multiple-fuse post-repair control blocks and multiple CSi signal lines. The post-repair control blocks need not have a 1:1 correspondence with the redundancy control blocks—for instance, three fuses could be used to generate seven unique CSi signals (and one no-select case) using decoding logic.  
         [0098]    The redundancy lines may be redundancy columns arranged in the column direction, redundancy rows arranged in the row direction, or both. If the redundancy lines are redundancy columns, defective columns are replaced, and if the redundancy lines are redundancy rows, defective rows are replaced.