Abstract:
A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V dd . Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V tn  as in the prior art. The boosting capacitors are charged by V dd , thus eliminating drift tracking problems associated with clock boosting sources and V dd . A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Description:
RELATED APPLICATIONS 
     This application is a divisional of Ser. No. 09/178,977 filed Oct. 26, 1998, now U.S. Pat. No. 6,055,201 which is a Continuation of Ser. No. 08/921,579 filed Sep. 2, 1997, now U.S. Pat. No. 5,828,620 which is a File Wrapper Continuation of Ser. No. 08/418,403 filed Apr. 7, 1995 now abandoned, which is a Continuation of Ser. No. 08/134,621 filed Oct. 12, 1993 now U.S. Pat. No. 5,406,523, which is a Divisional of Ser. No. 07/680,994 filed Apr. 5, 1991 now U.S. Pat. No. 5,267,201 which relates to United Kingdom Application Nos. 9107110.0 filed Apr. 5, 1991 and 9007791.8 filed Apr. 6, 1990, the entire teachings of which are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to dynamic random access memories (DRAMs) and in particular to a boosted word line power supply charge pump and regulator for establishing word line voltage. 
     BACKGROUND TO THE INVENTION 
     High density commercial DRAMS typically use capacitive pump voltage boosting circuits for providing sufficiently high voltage to drive DRAM word lines. Regulation of the voltage has been poor, and danger exists of generating voltages above the limits imposed by reliability requirements of the device technology and thus of damaging transistors to which the voltage is applied. Such circuits, where a supply voltage of V dd  is present, generate a maximum achievable voltage of 2V dd −V tn  where V tn  is the threshold voltage of an N-channel field effect transistor (FET). 
     DESCRIPTION OF THE PRIOR ART 
     FIG. 1 illustrates a voltage boosting circuit according to the prior art and FIG. 2 illustrates clock signal waveforms used to drive the circuit. 
     A pair of N-channel transistors  1  and  2  are cros;-coupled to form a bistable flip-flop, the sources of the transistors being connected to voltage rail V dd . The drain of each transistor, is connected to the gate of the respective other transistor, and form nodes 3 and 4 which are connected through corresponding N-channel transistors  5  and  6  configured as diodes, to one terminal of a capacitor  7 . The other terminal of capacitor  7  is connected to ground. 
     A clock source is connected through an inverter  8  and via capacitor  9  to node 4, and another clock source is connected through an inverter  10  through capacitor  11  to node 3. 
     The clock source voltage at the output of inverter  8  is shown as waveform φ 2 , varying between voltages V dd  and V ss , and the clock source output at the output of inverter  10  is shown as waveform φ 1 , varying between the voltages V dd  and V ss . 
     The output terminal of the circuit supplies the voltage V pp  at the junction of the capacitor  7  and transistors  5  and  6 . 
     Operation of the above-described circuit is well known. As the levels of φ 1  and φ 2  vary as shown in FIG. 2, capacitors  9  and  11  alternately charge between V ss  and V dd  and discharge to capacitor  7 . The maximum achievable voltage at the output terminal is 2V dd −V tn , where V tn  is the threshold of operation of either of transistors  5  or  6 . 
     It should be noted that the external supply voltage V dd  can vary between limits defined in the device specification, and also as a result of loading, both static and dynamic of other circuits using the same supply. The threshold voltage V tn  is sensitive to variations in semiconductor processing, temperature and chip supply voltage, and this contributes to significant variation in the boosted supply. Finally the boosted V pp  supply itself varies as a function of load current drawn from capacitor  7 . Therefore the voltage at the output terminal, which is supposed to provide a stable word line voltage can vary substantially from the ideal. For example, if V dd  is excessively high, this can cause the output voltage to soar to a level which could be damaging to word line access transistor gate insulation, damaging the memory. If V dd  is low, it is possible that insufficient output voltage could be generated to drive the memory cell access transistors, making memory operation unreliable. 
     SUMMARY OF THE PRESENT INVENTION 
     The present invention is a circuit for providing an output voltage which can be used to drive memory word lines which can be as high as 2V dd ; it does not suffer the reduction of V tn  of the prior art circuit. Thus even if V dd  is low, the word line driving voltage even in the worst case would be higher than that of the prior art, increasing the reliability of operation of the memory. 
     The above is achieved by fully switching the transistors in a boosting circuit, rather than employing N-channel source followers as “diodes”. This eliminates reduction of the boosting voltage by V tn . 
     Another embodiment of the invention is a circuit for detecting the required word line driving voltage and for regulating the voltage boosting pump by enabling the pump to operate if the boosted voltage is low, causing the word line driving voltages to increase, and inhibiting the pump if the voltage reaches the correct word line voltage. This is achieved by utilizing a sample transistor which matches the memory cell access transistor which is to be enabled from the word line. The word line driving voltage is applied to the sample transistor, and when it begins to conduct current indicating that its threshold of operation has been reached, a current mirror provides an output voltage which is used in a feedback loop to inhibit operation of the voltage pump. Since the sample transistor is similar to the memory access transistor, the exactly correct word line driving voltage is maintained. 
     Thus accurate regulation of the boosted word line voltage is produced, without the danger of transistor damaging voltages. Because once the correct word line driving voltage is reached, the voltage pump is inhibited, there is no additional power required to charge voltage boosting capacitors higher than this point, saving power. Since the voltage that is exactly that required is generated, improved reliability is achieved because double boot-strap voltages on the chip are eliminated. The circuit is thus of high efficiency. 
     The first and second embodiments are preferred to be used together, achieving the advantages of both. 
     The same basic design could also be employed as a negative substrate back-bias voltage (V bb ) generator. 
     An embodiment of the invention is a boosted voltage supply comprising a D.C. voltage supply terminal, first and second capacitors, the first capacitor having one terminal connected to ground and its other terminal to an output terminal, switching apparatus for connecting one terminal of the second capacitor alternately between the voltage supply terminal and ground and connecting the other terminal of the second capacitor alternately between the voltage supply terminal and the output terminal, whereby a boosted voltage regulated to the D.C. voltage supply is provided at the output terminal. 
     Another embodiment of the invention is a dynamic random access (DRAM) word line supply comprising an increasing voltage supply for the word line for connection to the word line from time to time, a memory cell access transistor for connecting a memory cell capacitor to a bit line having a gate connected to the word line, a sample transistor similar to the memory cell access transistor, apparatus for applying the voltage supply to the sample transistor for turning on the sample transistor at a supply voltage related to the characteristics of the sample transistor, and apparatus for inhibiting increase of the voltage supply upon turn-on of the sample transistor, whereby a voltage supply having a voltage level sufficient to turn-on the memory cell access transistor is provided for connection to the word line. 
    
    
     BRIEF INTRODUCTION TO THE DRAWINGS 
     A better understanding of the invention will be obtained by reference to the detailed description below, in conjunction with the following drawings, in which: 
     FIG. 1 is schematic diagram of a prior art voltage boosting circuit, 
     FIG. 2 illustrates clock waveforms used to drive the circuit of FIG. 1, 
     FIG. 3 is a schematic diagram of an embodiment of the present invention, 
     FIG. 4 illustrates clock signal waveforms used to operate the circuit of FIG. 3, 
     FIG. 5 is a schematic diagram of a boosted clock generator, and 
     FIG. 6 is a partly schematic and partly block diagram illustration of another embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     With reference to FIG. 3, a capacitor  15  is connected in a series circuit between ground and through an N-channel field effect transistor FET  16 , configured as a diode, with gate and drain connected to a voltage source V dd . Transistor  16  charges capacitor  15  to V dd  with an N-channel threshold (V tn ) of V dd  upon startup. 
     A first pair of transistors formed of N-channel FET  17  and P-channel FET  18  are connected with their source-drain circuits in series between the junction of transistor  16  and capacitor  15  and V dd , the source of transistor  18  being connected with its substrate to the junction of transistor  16  and capacitor  15 . That junction forms the output  19  of the circuit, where the voltage V pp , the word line supply, is provided. 
     A second pair of transistors, one being P-channel FET  20  and one being N-channel FET  21  have their source-drain circuits connected in series between the voltage supply V dd  and ground. The source of transistor  20  is connected to voltage supply V dd  with its substrate. A second capacitor  22  is connected between the junctions of the two pairs of transistors. 
     While the above-described circuit would operate in a manner to be described below to generate a voltage 2V dd  at the output  19 , it provides only a half wave boosting function, and should significant current be drawn, the voltage could drop. In order to provide a full wave boosting function, an additional circuit is included as follows. 
     A third pair of transistors comprising N-channel FET  23  and P-channel FET  24  have their source-drain circuits connected in series between V dd  and the output terminal  19 , the source of transistor  24  being connected to the output terminal with its substrate. A fourth pair of FETs comprised of P-channel FET  24  and N-channel FET  25  have their source-drain circuits connected in series between V dd  and ground, the source of transistor  24  being connected to V dd  with its substrate. A third capacitor  27  is connected between the junctions of the third and fourth pairs of transistors. 
     Clock sources are applied to the gates of the various transistors as follows: φ 1  to the gate of transistor  25 , /φ 1  to the gate of transistor  20 , φ 2  to the gate of transistor  21 , and /φ 2  to the gate of transistor  26 . 
     Boosted clock signals are applied to the gates of the various transistors as follows: φ 1 + to the gate of transistor  23 , /φ 1  to the gate of transistor  18 , φ 2 + to the gate of transistor  17  and /φ 2 + to the gate of transistor  24 . 
     A schematic of a clock generator is shown in FIG.  5 . P-channel transistors  51  and  52  are cross-coupled to form a bistable flip-flop, the sources and substrates of the transistors being connected to the V pp  output  19 , the gate of transistor  52  being connected to the drain of transistor  51  and the gate of transistor  51  being connected to the drain of transistor  52 . N-channel transistor  53  has its source-drain circuit connected between the drain of transistor  51  and ground and N-channel transistor  54  has its source-drain circuit connected between the drain of transistor  52  and ground. The clock φ 1  is applied to the gate of transistor  54  and the clock /φ 1  is applied to the gate of transistor  53 . 
     When the clock φ 1  goes high, transistor  54  is enabled and the junction of transistors  52  and  54  is pulled to ground, enabling transistor  51  which passes V pp  to the junction of transistors  51  and  53 . This is the clock φ 1 +, boosted to V pp . When the clock φ 1  goes low, and /φ 1  goes high, transistor  54  is inhibited and transistor  53  is enabled and the junction of transistors  51  and  53  (φ 1 +) is pulled to ground. This enables transistor  52  which passes V pp  to the junction of transistors  52  and  54 , the clock /φ 1 + output. 
     A similar circuit (not shown) provides boosted clocks φ 2 + and /φ 2 +. 
     FIG. 4 illustrates the clock signal logic levels and timing which are applied to the various gates, and reference is made thereto for the explanation below. 
     In operation, at initialization, capacitor  15  is charged through the N-channel FET diode  16  from V dd , charging it up to V dd −V tn . The circuit then goes through a number of cycles to charge up reservoir capacitor  15  to the required level. The following discussion describes the voltages and charge transfers occurring in the pump circuit once the V pp  level has almost reached the desired level, and is sufficient to fully turn on an N-channel transistor with its source at V dd . 
     Now considering the switching circuit for capacitor  27  to the left of diode  16 , and the waveforms of FIG. 4, φ 1  and /φ 1 + go high, enabling transistors  23  and  25 . Capacitor  27  charges to the level of V dd . Transistors  23  and  25  are then inhibited, ceasing conduction at the end of the φ 1  pulse. 
     After a discrete period of time, /φ 2  and /φ 2 + go low and transistors  24  and  26  are enabled. The capacitor terminal which was connected to V dd  becomes connected to output terminal  19  and the other, negative terminal of capacitor  27  becomes connected to V dd . If capacitance C R  ( 15 ) was equal to 0, the voltage from the positive terminal of capacitor  27 , at terminal  19  to ground would be equal to the initial voltage on capacitor  27  plus the voltage V dd  to ground, i.e. 2V dd . However, reservoir capacitor C R  ( 15 ) typically has a large value so that the voltage step at node 19 will be attenuated to (C S /(C S +C R ))*(2V dd −V pp ), where C R  and C S  are the values of capacitors  15  and  22  or  27  respectively. Thus the pump can attain a maximum level of 2V dd . 
     The voltage pulses /φ 2  and /φ 2 + then go high, inhibiting transistors  23  and  25 , and after a discrete period of time φ 1  and /φ 1 + go high again, reconnecting capacitor  27  between V dd  and ground. Again it charges, and as capacitor  27  is alternately switched between V dd  and ground and output terminal  19  and V dd , the voltage between terminal  19  and ground rises to 2V dd . 
     A similar function occurs with capacitor  22 . When the clock voltage /φ 1  and /φ 1 + go low, capacitor  27  is connected between terminal  19  and V dd  through transistors  20  and  18 . When the clock voltages φ 2  and φ 2  + go high, capacitor  22  is connected between V dd  and ground via transistors  17  and  21 , charging capacitor  22  to the voltage V dd . Thus, while capacitor  27  is being charged between V dd  and ground, capacitor  22  is connected between output terminal  19  and V dd  through FETs  20  and  18 , due to the phase and polarity of the clock signals /φ 1 . The two capacitors  27  and  22  thus alternately charge and boost the voltage on capacitor  15 . 
     The clock signals φ 1 , φ 2 , /φ 1  and /φ 2  have similar amplitudes, and vary between V dd , a logic 1, and a V ss , a logic zero. 
     The clock signals φ 1 +, φ 2 +, φ 1 + and /φ 2 + have similar amplitudes, and vary between V pp , a logic 1, and V ss  (ground), and logic 0. 
     It should be noted that the capacitors  15 ,  22  and  27  charge from the main voltage supply V dd , and not from the clock sources. This allows the clock sources to have reduced power supply requirements, since they drive only the gates of the FETs which have minimal capacitance. This is in contrast to the prior art boosting circuit in which the clock sources supply the charge required for capacitors  9  and  11  (FIG.  1 ), and thus supply the current required to boost the voltage, indirectly supplying part of the word line current. 
     In addition, since the voltage boosting current is not routed through an FET configured as a diode, as in the prior art circuit, there is no reduction of the boosting voltage by a threshold of conduction voltage V tn  as in the prior art. 
     Since non-overlapping clocks are used, the boosting current will not flow between the output terminal  19  and V dd . This also prevents charge from leaking away from the capacitor  15  during switching. 
     It is preferred that the N-channel transistor substrates should all be connected to a voltage V ss  or V bb  which is below V ss  (ground) in this embodiment. The connection of the substrates of the P-channel transistors  24  and  18  to V pp  avoids forward biasing of the P-channel tubs. 
     Turning now to FIG. 6, a word line supply is shown. A word line voltage source such as provided on lead  29  is connected through a word line decoder  30  to a word line  31 . A memory cell access transistor  32  has its gate connected to the word line, and its source-drain circuit connected to a bit line  33  and to a memory cell bit storage capacitor  34 . The capacitor is referenced to the cell plate reference voltage V ref . 
     In operation of the above well-known circuit, if a voltage V pp  on lead  29  is&#39;supplied through a word line decoder  30  to a word line  31 , which voltage is applied to the gate of transistor  32 , the bit storage charge capacitor  34  is connected to bit line  33  through transistor  32 . The charge stored on capacitor  34  is thereby transferred to bit line  33 . 
     The circuit of FIG. 6 provides a word line voltage regulator. A sample transistor  35  is fabricated similar to word line access transistor  32 . It thus exhibits the same characteristics, including similar thresholds of conduction. 
     The source of transistor  35  is connected to the voltage supply V dd  and the drain is connected through a P-channel transistor  36  to the word line voltage source lead  29 . The gate of transistor  36  is connected to its drain. 
     A P-channel transistor  37  mirrors the current in transistor  36  having its gate connected to the gate and drain of transistor  36 , its source connected to the word line voltage source lead  29  and the drain connected to the drain of N-channel transistor  38 , which has its other source connected to ground (V ss ), and its gate connected to V dd , to operate in the linear region as a resistor. 
     Transistors  36  and  37  form a current mirror of current passing through transistor  36 . When V pp  rises to the point at which transistor  35  begins to conduct, a similar current is conducted through transistor  38 . A positive voltage appears between the junction of transistors  37  and  38  and ground. This voltage is used as a feedback voltage to inhibit the generation of additional increase in voltage of V pp  on lead  29 . 
     Since transistor  35  is similar to transistor  32 , the exactly correct V pp  sufficient to turn on transistor  32  is set. 
     The voltage V pp  at lead  29  can be provided by means of a pump in accordance with the prior art, or preferably the voltage pump  39  described with reference to FIGS. 3 and 4 above. Either the prior art pump or the pump in accordance with the present invention is driven by an oscillator  40 , which provides the clock signals, e.g. φ 1 , φ 2 , /φ 1  and /φ 2 . Oscillator  44  has an inhibit input, which stops its operation upon receipt of an inhibit signal. 
     The feedback voltage from the current mirror is applied via a pair of serially connected inverters  41  and  42  to the inhibit input of oscillator  44 . Actually, any even number of inverters could be used. Therefore when transistor  35  begins conduction, signifying that the correct word line (and transistor  32 ) driving voltage V pp  has been reached, the feedback voltage to the inhibit input of oscillator  44  shuts oscillator  44  down, causing cessation of the charging of the capacitors in the voltage boosting circuits, and cessation of increasing of the voltage V pp . 
     The voltage regulator described above thus eliminates the boosting of V pp  if it is not required, and only allows the voltage boosting circuit to boost the voltage to the level required by the word line, i.e. cell access transistors. This saves power and provides protection to the cell access transistors, increasing reliability of the memory. The dangerous double boot-strap circuits boosting voltage to about 2V dd  which were previously found on the chip are thus eliminated, and voltage stress is minimized. 
     Narrow channel transistors can have higher than expected threshold voltages under back-bias conditions, and the present regulator which actually measures the memory cell access transistor turn-on voltage provides the exact word line supply voltage, neither too low nor too high. The combined embodiments of FIGS. 3 and 5 thus provide a substantially more reliable word line voltage, resulting in a more reliable memory, with reduced power requirements. 
     A person understanding this invention may now conceive of alternative structures and embodiments or variations of the above. All of those which fall within the scope of the claims appended hereto are considered to be part of the present invention.