Abstract:
A signal level detector is disclosed, in which the noise tolerance of the signal detection is enhanced without increasing power consumption of the circuit. The signal detector includes two amplifiers, whose gain is fixed but different from each other, a switch to select the output of one of the amplifiers, a peak hold to hold the selected output and a comparator to compare the output of the peak hold with the level corresponding to loss-of-signal level. The switch responds to the compared result. In the invention, the two amplifiers have the same arrangement of the trans-conductance amplifier but only the resistance of the emitter coupling resistor is different.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a level detector for an input signal, in particular, the invention relates to a level detector usable in an optical receiver circuit. 
         [0003]    2. Related Background Art 
         [0004]    Conventional signal detector and a system to process the detected signal are comprised of a variable gain amplifier, another variable gain amplifier to provide a reference, two peak hold each configured in the downstream of respective variable gain amplifiers, and a hysteresis comparator to compare outputs of these two outputs of the peak holds. A Japanese Patent Application published as H08-015584A has disclosed such signal detector. The Signal detector disclosed therein adjusts the gain of variable gain amplifiers by following the level corresponding to the loss of signal (hereafter denoted as LOS). Because the comparator shows the hysteresis, the noise tolerance of the level detector may be secured. 
         [0005]    However, the conventional level detector needs a wide linearity or the variable gain amplifier even at a level close to reset the LOS status for the variable gain amplifier is usually necessary to be wide linearity. In order to enhance the noise tolerance, the wide dynamic range in the linearity is necessary, which makes hard to accomplish by the variable gain amplifier without increasing the power consumption of the amplifier. The present invention is to provide a technique to enhance the noise tolerance in the signal level detector without increasing the power consumption. 
       SUMMARY OF THE INVENTION 
       [0006]    The signal level detector according to the present invention includes two amplifiers each receiving an input signal, a switch to select one of outputs of the first and second amplifiers, a peak hold to hold an output of the switch, that is, one of the outputs of two amplifiers selected by the switch, and a comparator that compares the output of the peak hold with a reference corresponding to the LOS threshold. The signal level detector of the invention has a feature that two amplifiers that receive the input signal have the same circuit arrangement but different voltage gain and the switch selects one of the outputs of the amplifiers by responding to the output of the comparator. 
         [0007]    The level detector of the invention switches the amplifiers with different gain to each other by responding to the output of the comparator that corresponds to the LOS status, which may show the hysteresis performance for the LOS status. Because the switch makes only one of the amplifiers active and the other amplifier inactive, the power consumption of the detector does not increase. 
         [0008]    Two amplifiers of the present detector each has a feature that the circuit arrangement thereof is a type of a trans-conductance amplifier with a pair of differential transistors, a pair of source transistors each connected to one of differential transistors, and a emitter coupling resistor connected between the emitters of the differential transistors, or connected between the collectors of the source transistors. In the present level detector, only the resistance of the emitter coupling resistor is different from the resistance of the emitter coupling resistor of the other amplifier. The LOS alarm output from the comparator controls the active or the inactive status of two trans-conductance amplifiers by turning on or turning off the source transistors. Because one of the amplifier not selected by the LOS alarm signal becomes inactive, the power consumption of the level detector does not increase even through the level detector includes two amplifiers. 
         [0009]    Two trans-conductance amplifiers have common load resistors, that is, the differential transistors of two amplifiers are connected in parallel with respect to their load resistors. Accordingly, the output amplitude of two trans-conductance amplifiers become equal to a value determined by the resistance of the load resistor multiplied by a current determined by the source transistors. Because the size of the source transistors of two trans-conductance amplifiers is same to each other, the magnitude of the output signal of the trans-conductance amplifiers becomes equal but the voltage gain thereof is different because the emitter coupling resistor has resistance different in respective trans-conductance amplifiers. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0010]    The foregoing and other purposes, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: 
           [0011]      FIG. 1  is a block diagram of a signal level detector according to an embodiment of the present invention; 
           [0012]      FIG. 2  is a circuit diagram of a hysteresis controller implemented in the signal level detector of the present invention; and 
           [0013]      FIGS. 3A to 3C  show examples of the operation of the signal detector, where  FIG. 3A  is a behavior of an input signal,  FIG. 3B  is an alarm status responding to the input signal shown in  FIG. 3A , and  FIG. 3C  explains a mechanism of the hysteresis control. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0014]    Next, preferred embodiment according to the present invention will be described as referring to accompanying drawings. In the description of the drawings, the same numerals or the symbols will refer to the same elements without overlapping explanations. 
         [0015]      FIG. 1  is a circuit diagram of a level detector  1  according to an embodiment of the present invention. The level detector  1  decides whether the optical input level is under the LOS status or not by using the hysteresis characteristic, and comprises a signal input terminal  2 , two amplifiers,  3  and  4 , a signal output terminal  5 , a hysteresis controller  6 , two peak holds,  7   a  and  7   b,  a reference  8 , a comparator  9  and an alarm terminal  10 . The first amplifier  3  receives a signal from, for instance a trans-impedance amplifier ordinary provided in an optical receiver, and outputs an amplified signal V 1  to the second amplifier  4  and the hysteresis controller  6 . The second amplifier  4  may operate as a limiting amplifier whose output saturates at a preset level able to be processed in, for instance a clock data recovery unit ordinarily provided in the downstream of the output terminal  5 . 
         [0016]    The hysteresis controller  6  includes two amplifiers,  6   a  and  6   b,  configured in parallel with respect to the input thereof and a switch  6   c.  Respective outputs of the amplifiers,  6   a  and  6   b,  are brought to the terminals of the switch  6   c.  The switch  6   c  may select one of the outputs of the amplifiers,  6   a  and  6   b,  and transmit the selected output to one of the peak hold  7   a.    
         [0017]    The peak hold  7   a  detects a peak level of one of the outputs selected by the switch  6   c,  and generates a first detected signal V 2  to the comparator  9 . The other peak hold  7   b  has substantially same configuration with that of the first peak hold  7   a.  The second peak hold  7   b  detects a peak level of the reference  8  and transmits the peak level V 3  thus detected to the comparator  9 . 
         [0018]    The comparator  9  compares the first peak level V 2  output from the first peak hold  7   a  with the second peak level V 3  output from the second peak hold  7   b,  and generates an alarm V 4  that corresponds to the decision for the input level of the level detector  1  and has only two logical levels of “1” and “0”, refer to  FIG. 3B . Specifically, when the signal V 1  is less than a preset level corresponding to the reference  8 , which means that the optical input level is in the LOS state, the alarm V 4  becomes logical “1”, while, the signal V 1  is greater than or equal to the preset level, the alarm V 4  takes the logical level of “0”. This alarm V 4  is not only output from the alarm terminal but sent to the switch  6   c.    
         [0019]    The switch  6   c,  when it receives the alarm V 4  with the logical level of “1” from the comparator  9 , which means that the optical input level changes from the SD state to the LOS state, changes the selection of the output to be transmitted to the first comparator  7   a  from the first amplifier  6   a  to the second amplifier  6   b.  On the other hand, when the switch  6   c  receives the alarm V 4  with the level “0”, which means that the optical input level changes from the LOS state to the SD state, the switch changes the output of the second amplifier  6   b  to the first amplifier  6   a.    
         [0020]    The switch  6   c  shown in  FIG. 1  is schematically illustrated so as to show only the function to select the output of two amplifiers,  6   a  and  6   c.  The arrangement of the switch  6   c  is not restricted to those shown in  FIG. 1 ; accordingly, the description presented below assumes that the function of the switch  6   c  makes only one of the amplifiers,  6   a  and  6   c,  active. In such an arrangement, the output of the amplifiers,  6   a  and  6   c,  may be directly connected to the input of the peak hold  7   a  without passing the switch  6   c  as shown in  FIG. 2 . 
         [0021]    The gain of the first amplifier  6   a  is set to be greater than the gain of the second amplifier  6   b.  The upper limit of the input signal V 1  for the amplifier, where the upper limit means the largest threshold in the range where the amplifier may linearly operate, is set to a value corresponding to the LOS asserting level k 1 , refer to  FIGS. 3A and 3C . While, the LOS de-asserting level k 2  is set to be greater than the LOS asserting level k 1 , and a difference between these levels is identical with an amount of the hysteresis of the level detector  1 . 
         [0022]    Next will describe a detail of the hysteresis controller  6 .  FIG. 2  is a circuit diagram of the hysteresis controller  6 , which comprises the first amplifier section  6   a,  the second amplifier section  6   b  and the switch section,  64   a  and  64   b.  The hysteresis controller  6  further provides two input terminals, INP and INN, two output terminals, OUTP and OUTN. The input terminals, INP and INN, are each connected to the outputs of the amplifier  3  shown in  FIG. 1  to receive the signal V 1  from the amplifier  3 . The outputs, OUTP and OUTN, are each connected to the input of the peak hold  7   a.  The signal V 1  input from the terminals, INP and INN, is amplified by one of the amplifier units,  6   a  and  6   c , and only one of the amplified signal is appeared in the output terminals, OUTP and OUTN. 
         [0023]    The first amplifier section  6   a  includes a trans-conductance amplifier  61   a  that is comprised of a differential unit  62   a  including a pair of transistors, Q 1   a  and Q 2   a,  called as the differential pair and an emitter coupling resistor R 3   a;  and a current source  63   a  including two transistors, Q 3   a  and Q 4   a,  called as the source transistors and two emitter resistors, R 4   a  and R 5   a.  The first transistor Q 1   a  receives the signal V 1  in the positive phase thereof from the terminal INP, while, the second transistor Q 2   a  receives the signal V 1  in the negative phase from the terminal INN. The first transistor Q 1   a  has a load resistor R 1  connected to the power supply Vcc, while the second transistor Q 2   a  has another load resistor R 2  also connected to the power supply Vcc; and the collector of respective transistors, Q 1   a  and Q 2   a,  are coupled with the terminals, OUTP and OUTN. 
         [0024]    The base of the source transistors, Q 3   a  and Q 3   b,  each receives the reference Vb through the switch  64   a;  the emitter of these transistors are grounded through respective resistors, R 4   a  and R 5   a;  while, the collectors thereof are connected to the emitter of corresponding transistors, Q 1   a  and Q 2   a.  Between the collectors are connected with the emitter coupling resistor R 3   a.  The other trans-conductance amplifier  61   b  has the same arrangement with that of the first trans-conductance amplifier  61   a  except for the resistance of the emitter coupling resistor, R 3   a  and R 3   b;  and the base of the source transistors, Q 3   b  and Q 4   b,  receive the reference Vb through the other switch  64   b.  The function of the common emitter resistor, R 3   a  and R 3   b,  will be described below in detail. 
         [0025]    Two switches,  64   a  and  64   b,  operate complementarily, that is, when the signal V 4  provided from the comparator  9  is set to the logical level “1” that means the optical input is in the LOS state, one of the switches,  64   a  and  64   b,  provides the reference Vb to the base of the source transistors, while, the other switch grounds the base of the other source transistors. 
         [0026]    Assuming that the first trans-conductance amplifier  61   a  has the same arrangement with those of the second trans-conductance amplifier  61   b,  that is, the size of the differential transistors, Q 1   a  and Q 2   a,  have the same size with the other differential transistors, Q 1   b  and Q 2   b;  the source transistors, Q 3   a  and Q 4   a,  have the same size with the other source transistors, Q 3   b  and Q 4   b;  and the emitter resistors, R 4   a  and R 5   a , have the same resistance with the emitter resistors, R 4   b  and R 5   b;  then, the differential gain of the trans-conductance amplifier,  61   a  and  62   a,  are given by: 
         [0000]        A   V   (61a) =2× R 1/{2× V   T   /I   0   +R 3 a}, and    
         [0000]        A   V   (61b) =2× R 1/{2× V   T   /I   0   +R 3 b},    
         [0000]    where V T  and I 0  are the thermal voltage defined by kT/q (k: Boltzmann constant, T: absolute temperature, q: electric charge) and the current flowing from the emitter of the differential transistor to the corresponding source transistor. Here, the thermal voltage V T  becomes about 25 mV at room temperature. Because the first and second trans-conductance amplifiers,  61   a  and  61   b,  are substantially the differential circuit, two load resistors, R 1  and R 2 , have the same resistance and two emitter resistors, R 4   a  and R 5   a , have the same resistance. Moreover, according to the assumption above where two trans-conductance amplifiers,  61   a  and  62   a,  have the same configuration, four emitter resistors, R 4   a  to R 5   b,  have the same resistance. 
         [0027]    In two equations above, only the resistance of the emitter coupling resistor, R 3   a  and R 3   b,  is different. Therefore, the voltage gain of the trans-conductance amplifier,  61   a  and  61   b,  may be adjusted only by setting the resistance of the emitter coupling resistor, R 3   a  and R 3   b . On the other hand, the amplitude of the signal output from the terminals, OUTP and OUTN, is determined by the product of the resistance of the load resistor, R 1  and R 2 , and the current flowing therein. As described above, the current flowing four paths from the emitter of the differential transistors to the source transistors is the same magnitude of I 0 . Accordingly, the output amplitude of the amplifier,  6   a  or  6   b,  becomes equal to 2×I 0 ×(R 1  or R 2 ) in spite of different voltage gains. Thus, the hysteresis controller  6  according to the present embodiment may switch two amplifiers,  6   a  and  6   b,  with different voltage gain responding to the LOS status without increasing the power consumption, which enables to set an enough hysteresis width. 
         [0028]    Next will describe the operation of the level detector  1  as referring to  FIGS. 3A to 3C .  FIGS. 3A and 3B  show an example of the time behavior of the signal V 1  input to the hysteresis controller  6  and a response of the LOS alarm V 4  output from the comparator  9 , respectively. In a period S 1  until an instant T 1 , the signal V 1  monotonically decreases and becomes less than the LOS de-asserting level k 2 , but still exceeds the. LOS asserting level k 1 . The output V 4  keeps the status “0” that corresponds to the signal detect (SD) and the peak hold  7   a  receives the output of the first amplifier  6   a.    
         [0029]    At an instant T 1 , the signal V 1  becomes equal to the LOS asserting level k 1  and the output V 4  turns to the logical level “1” corresponding to the LOS status. Then the switch  6   c  switches the input provided to the peak hold  7   a  from the output of the first amplifier  6   a  to the second amplifier  6   b . In a period S 3  from an instant T 1  to another instant T 2 , the signal V 1  further decreases, during which the output V 4  of the comparator  9  remains the level “1”. In a period S 4  from an instant T 2  to another instant T 3 , the signal V 1  increases but remains a status less than the LOS de-asserting level k 2 , which means that the output V 4  is still kept in the level “1”. During the period of S 3  and S 4 , the peak hold  7   a  receives the output of the second amplifier  6   b.  At an instant T 3 , the signal V 1  becomes equal to the LOS de-asserting level k 12 , then the output V 4  of the comparator turns to the level “0”, which changes the input of the peak hold  7   a  from the output of the second amplifier  6   b  to that of the first amplifier  6   a.    
         [0030]      FIG. 3C  explains the time behaviors of the signal V 1  input to the hysteresis controller  6  and the output V 2  thereof provided to the peak hold  7   a.  During the period S 1 , the output V 2  decreases on the transition curve G 1  of the first amplifier  6   a  until the output V 2  becomes equal to a level denoted as V 3  output from the second peak hold  7   b,  in which the output V 4  of the comparator  9  shows the SD state “0”. 
         [0031]    When the signal V 1  becomes equal to the LOS asserting level k 1 , the switch  6   c  switches the input of the peak hold  7   a  from the output of the first amplifier  6   a  to that of the second amplifier  6   b  responding the output V 4  from the level “0” to the other level “1”, then the output V 2  of the peak hold  7   a  jumps to the point P 2  at step S 2 . After step S 2 , the output V 2  further decreases on the transition curve G 2  of the second amplifier at step S 3  to reach the point P 3 . At step S 4 , the output V 2  monotonically increases on the transition curve of the second amplifier  6   b  and until it reaches the point P 4 . The output V 4  of the comparator  9  is kept in the level “1” during the steps of S 3  and S 4 . When the output V 1  reaches the LOS de-asserting level k 2  at the point P 4 , the switch  6   c  switches the input of the peak hold  7   a  from the output of the second amplifier  6   b  to that of the first amplifier  6   a,  then the output V 2  of the peak hold  7   a  jumps from the point P 4  on the transition curve G 2  of the second amplifier  6   b  to the point P 5  on the curve G 1  of the first amplifier  6   a.  The slope of the transition curves, G 1  and G 2 , corresponds to the voltage gain of respective amplifiers, that is, the voltage gain of the first amplifier  6   a  is greater than that of the second amplifier  6   b.    
         [0032]    Thus, the level detector  1  according to the present embodiment may show the hysteresis characteristic by switching two amplifiers,  6   a  and  6   b,  with respective different voltage gain different from each other depending of the LOS status. Because two amplifiers,  6   a  and  6   b,  have substantially same circuit arrangement whose power consumption is also the same; accordingly, the level detector  1  of the embodiment may realize an enough hysteresis characteristic in detecting the LOS status without increasing or changing the power consumption. 
         [0033]    The difference in the voltage gain between two amplifiers,  6   a  and  6   b,  may be simply performed by setting the resistance of the emitter coupling resistors,  3   a  and  3   b . Further, the dynamic range where the voltage gain shows a linear characteristic is also simply determined by the resistance of the emitter coupling resistor,  3   a  and  3   b.  Thus, in the level detector  1  of the embodiment, a preferable performance with an enough hysteresis range may be compatible with the dynamic range of the voltage gain of the amplifier. 
         [0034]    Conventionally, a differential amplifier may show a wide dynamic range in the voltage gain thereof by increasing resistance of the load resistor, R 1  and R 2 , or by increasing the current I 0  flowing therein. However, the former technique to increase the resistance is hard to follow a high-speed signal over 10 Gb/s, while, the later technique incurs the increase in the power consumption. The present level detector  1  may show the wide hysteresis characteristic only by adjusting the resistance of one resistor. 
         [0035]    While there has been illustrated and described what are presently considered to be example embodiments of the present invention, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the invention. Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims.