Abstract:
An apparatus and method for accessing a cache memory. In a cache memory, an address is received that includes a set field and a partial tag field, the set field and the partial tag field together including fewer bits than necessary to uniquely identify a region of memory equal in size to a cache line of the cache memory. The set field is decoded to select one of a plurality of storage units within the cache memory, each of the plurality of storage units including a plurality of cache lines of the cache memory. The partial tag field is compared to a plurality of previously stored partial tags that correspond to the plurality of cache lines within the selected one of the plurality of storage units to determine if the partial tag field matches one of the plurality of previously stored partial tags. If the one of the previously stored partial tags matches the partial tag field, one of the plurality of cache lines that corresponds to the one of the plurality of previously stored partial tags is output.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of data processing and more particularly to method and apparatus for caching data in a data processing system. 
     BACKGROUND OF THE INVENTION 
     Cache memories are relatively small, high-speed memories used to reduce memory access time in modern computer systems. The idea is to store data from frequently accessed regions of system memory in cache memory so that subsequent accesses to the cached regions will not incur the full system memory access time, but the shorter cache access time instead. A memory transaction that accesses cache memory instead of system memory is called a cache hit, and the cache “hit rate” is a fundamental metric of cache design. 
     FIG. 1 illustrates a prior art cache memory  12  that includes a data store  14  and a tag store  16 . In effect, the cache memory  12  is a data buffer in which each entry in the data store  14  is mapped to a region of system memory by a corresponding entry in the tag store  16 . When an address is asserted to system memory, set and tag fields within the address are used to determine whether an entry in the cache memory  12  is mapped to the region of system memory sought to be accessed. The set field (sometimes called an index) is decoded to select an entry in the data store  14  and a corresponding entry in the tag store  16 . An address value, called a “tag,” is output from the selected tag store entry and compared with the tag field of the asserted address. If the tag field of the asserted address matches the tag output from the selected tag store entry, a cache hit is signaled to indicate that the selected entry in the data store is mapped to the region of system memory sought to be accessed. In the case of a memory read operation, a cache line (i.e., the unit of information in a cache) is output from the selected entry in the data store and returned to the requestor. Low order bits of the input address may be used to select a sub-portion of the cache line according to the width of the transfer path to the requestor and the width of data that can be handled by the requester. Write requests are handled similarly, except that data is written to the selected entry in the data store  14 . 
     The cache memory  12  is referred to as a direct mapped cache because only one cache line is stored in the cache for each possible value of the set field. That is, system memory is directly mapped to the cache based on the set field so that there is only one tag field in the tag store  16  per value of the set field. One undesirable consequence of direct mapping is that a cache miss will occur in response to each new memory address for which the set field, but not the tag field, matches a previously asserted address. Thus, if a sequence of memory accesses are directed to system memory addresses that have the same set fields but different tag fields, a significant number of cache misses will occur and data from the different system memory addresses will be frequently swapped into and out of the cache memory  12 ; a phenomenon called “thrashing.” An alternate mapping scheme, called multiple-way, set associative mapping, is used to avoid this sort of thrashing. 
     FIG. 2 illustrates a prior-art four-way, set associative cache memory  26  in which each set field is mapped to as many as four system memory addresses. Instead of a single data store, there are four data stores ( 28 A- 28 D), called “data ways,” and instead of a single tag store, there are four tag stores ( 30 A- 30 D), called “tag ways.” In effect, the direct mapped operation described above occurs in parallel for each of the four data ways and four tag ways. When a memory address is received, the set field is used to select a respective cache line from each of the four data ways and also to select a respective tag from each of the four tag ways. Each of the selected tags is compared against the tag field of the input cache address to generate a corresponding tag way hit signal. The tag way hit signals are input to hit logic  31  which asserts or deasserts a cache hit signal based on whether any of the tag way hit signals indicates a match. Assuming a cache hit, the hit logic generates a data way select signal that indicates which of the tag ways contains the tag matching the tag field of the input address. The data way select signal is supplied to a multiplexer  32  to select the source of the cache line output to be the data way that corresponds to the tag way containing the tag matching the tag field. 
     Because the same set field is associated with multiple tag addresses in a multiple-way, set associative cache memory, the type of thrashing that can occur in direct mapped caches is usually avoided. Consequently, a multiple-way, set associative cache tends to achieve a higher hit rate than a direct mapped cache having the same sized data store. The higher hit rate is not without cost, however, because the increased logic required to generate the way select signal and to select one of the plurality of set-field-selected cache lines increases the overall time required to output a cache line. This is in contrast to a direct mapped cache which outputs a cache line as quickly as the set field can be decoded and the selected cache line can be driven onto the return data path. 
     SUMMARY OF THE INVENTION 
     An apparatus and method for accessing a cache memory are disclosed. A memory address is asserted that includes a set field and a tag field that together uniquely identify a region of system memory equal in size to a cache line in a cache memory. A partial tag field that includes less than all bits in the tag field is compared against a partial tag entry stored in the cache memory. A cache line is output from the cache memory if the partial tag field matches the partial tag entry. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which: 
     FIG. 1 illustrates a prior art cache memory that includes a data store and a tag store; 
     FIG. 2 illustrates a prior-art four-way, set associative cache memory; 
     FIG. 3 depicts a way-predicting cache memory according to one embodiment; 
     FIG. 4 illustrates a way predictor according to one embodiment; 
     FIG. 5 illustrates a processor that includes a way predicting cache; and 
     FIG. 6 illustrates a cache replacement strategy for a way predicting cache memory according to one embodiment. 
    
    
     DETAILED DESCRIPTION 
     A multiple-way cache memory is disclosed in which way selection is performed in parallel with set field decoding to reduce the amount of time required to output a cache line. To speed the way selection operation, a partial tag field that includes only a subset of the bits of a full tag field is compared to previously stored partial tags to select one of a plurality of data ways. Because only a subset of the full tag field is used to select a data way, the way selection is speculative in nature and is therefore referred to as a way prediction. The hit signal and data output in response to the way prediction are also speculative in nature and are accordingly referred to as a speculative hit signal and speculative data, respectively. 
     Because the way selection is performed in parallel with the set field decoding and because the way selection time is reduced by virtue of the partial tag field comparison, speculative data can usually be output from the cache data store substantially faster than with prior art cache memories that perform full tag field comparison, followed by a multiplexed routing of one of a plurality of data way outputs to the cache memory output. This and other intended advantages of the present invention are described below. 
     FIG. 3 depicts a way-predicting cache memory  50  according to one embodiment. The cache data store  47  is arranged as a sequence of words  48 A- 48 C that each include four data ways (e.g., WAY 0 -WAY 3  in cache word  48 A). The four data ways in each word  48 A- 48 C are each used to store a respective cache line. A set field decoder  56  is provided to decode the set field  41  of each incoming cache address  10  and to assert a word select signal on one of a plurality of word select lines  51 A- 51 C indicated by the decoded set field. A plurality of way predictors  45 A- 45 C, one for each word  48 A- 48 C in the cache data store  47 , is provided to compare a partial tag field  43  of the cache address  10  against previously stored partial tags. If a match is detected in a way predictor, the way predictor outputs one of a plurality of way select signals  57  to indicate which data way within a cache word  48 A- 48 C corresponds to the partial tag that resulted in the match. Each of the plurality of word select lines  51 A- 51 C is coupled to a respective group of way select gates  61 A- 61 C for a corresponding cache word  48 A- 48 C of the data store  47 . Consequently, if a partial tag match occurs in a way predictor that corresponds to a cache word that is also selected by a word select signal from the set field decoder, one of the data ways in the word will be selected and the cache line therein will be output as speculative data  53 . 
     Each cache address asserted by the requester is an N-bit address that includes an M-bit set field  41  and an N−M bit tag field  42 . The full address asserted by the requestor may include additional low order bits that resolve a unit of data smaller than a cache line. The M-bit set field  41  is applied to the set field decoder  56 , while a partial tag field  43  (i.e., K bits of the tag field  42 , where K&lt;(N−M)) is applied to each of a plurality of way predictors  45 A- 45 C. To emphasize that less than all the bits of the tag field  42  are used to form the partial tag field  43 , the full tag field  42  is illustrated as being input to the cache memory in FIG. 3, with the unused bits of the tag field  42  (i.e., N−(M+K) bits) being not connected. This is not necessary, of course, and in a preferred embodiment, only the set field  41  and the partial tag field  43  of the cache address  10  are input to the cache memory. In one embodiment, the K bits of the partial tag field form a continuous address with the set field (i.e., the least significant bit of the partial tag is one position of significance higher than the most significant bit of the set field). In alternate embodiments, the K bits of the partial tag field  43  may be taken from other bit positions within the tag field  42 . As discussed above, the set field decoder  56  decodes the incoming set  41  and asserts one of the word select lines  51 A- 51 C in response. Concurrently with the decode operation in the set field decoder  56 , each of the way predictors  45 A- 45 C compares the partial tag field  43  against previously stored partial tags to determine whether there is a match. Each way predictor  45 A- 45 C outputs a plurality of way select signals  57  to a respective group of way select gates  61 A- 61 C so that, as described above, if a partial tag match occurs in a way predictor  45 A- 45 C for which the corresponding word line  51 A- 51 C is enabled, the data way indicated by the partial tag match will be selected and the cache line therein will be output as speculative data  53 . Because the decode operation in the set field decoder  56  is performed concurrently with the partial tag compare operation in the way predictors  45 A- 45 C, both the set field  41  and the partial tag field  43  are effectively provided as address inputs to the cache data store  47 . This is in contrast to prior art devices in which the set field  41  alone is used to address a plurality of data ways and way enable signals are applied at second stage of the cache output to select one of a plurality of cache lines output from the data ways. 
     Still referring to FIG. 3, the way enable signals  59  asserted to the respective data ways of the cache data store  47  are logically combined in a speculative hit circuitry  49  to determine whether a hit has occurred. If so, the speculative hit circuitry  49  asserts a speculative hit signal  55 . In one embodiment, the inputs to the speculative hit circuitry  49  are the way enable signals  59  applied to each of the words  48 A- 48 C of the cache data store  47  and are therefore labeled “WORDn/WAY SELECT [0-3]” in FIG. 3 (WORDn refers to cache words 0 through 2 M −1). In an alternate embodiment, the signals supplied to the speculative hit circuitry  49  may be generated by different logic circuits such as combinatorial logic circuits within the individual way predictors  45 A- 45 C (e.g., by ORing the way select signals together and then  45 A- 45 C (e.g., by ORing the way select signals together and then ANDing the OR&#39;d result with the corresponding word select line), or elsewhere in the way predicting cache  50 . 
     FIG. 4 illustrates a way predictor  45  according to one embodiment. The way predictor  45  includes a plurality of partial tag registers  71 A- 71 D (four, in this exemplary embodiment). A partial tag (PTAG) is stored in each partial tag register  71 A- 71 D and is output to an input of a corresponding one of a plurality of comparators  73 A- 73 D. The other input of each comparator  73 A- 73 D is coupled to receive the partial tag field  43 . If, in a given comparator  73 A- 73 D, a partial tag field  43  is determined to match the partial tag stored in a partial tag register  71 A- 71 D, the comparator asserts a way select signal  57 . The partial tag registers  71 A- 71 D within a given way predictor  45  are prevented from containing duplicate partial tag values so that at most one of the way select signals  57  is asserted by the way predictor  45  at a time. 
     The partial tag field  43  is supplied to each of the partial tag registers  71 A- 71 D so that the partial tag register can be reloaded with a new partial tag. The replacement strategy used to load new values into the partial tag registers  71 A- 71 D within a way predictor  45  and into the data ways within the cache data store  47  is discussed below. 
     FIG. 5 illustrates a processor  90  that includes a way predicting cache  50  according to the above-described embodiment. When the processor core  80  asserts a virtual address on an address path  86  within the processor  90 , the way predicting cache  50  receives at least the set field  41  and partial tag field  43  of the virtual address  86  and issues a speculative hit signal  55  and speculative data  53  (if there is a speculative hit) in response. The processor core  80  receives the speculative data  53  via a data path  84  and may begin processing the speculative data  53  through a pipeline for eventual use in an instruction execution. If the way predicting cache  50  is used as an instruction cache, the speculative data  53  may include an instruction (or a number of instructions) for execution in the processor core  80 . If the way predicting cache  50  is used as a data cache, the speculative data  53  may include data to be operated on during instruction execution in the processor core  80 . If the way predicting cache  50  is used as a combined data and instruction cache, the speculative data  53  may include instructions, data or both instructions and data to be processed in the processor core  80 . 
     At the same time that the way predicting cache  50  operates to determine whether a speculative hit  55  has occurred, a translation look aside buffer  81  (TLB) is used to convert the virtual address  86  to a physical memory address  88 . The physical address is supplied to hit/miss circuitry  83  which includes a full physical address tag that corresponds to each partial tag in the way predicting cache  50 . As a result, sometime (e.g., several clock cycles) after a speculative hit signal  55  is output by the way-predicting cache, the hit/miss logic compares the tag field of the physical address  88  of the access request against physical address tags to determine whether an actual hit or miss has occurred. An actual hit or miss is signaled to the processor core  80  by a hit/miss signal  87 . 
     If an actual hit has occurred, then the processing performed on the speculative data  53  in the intervening time between output of the speculative data  53  from the way-predicting cache  50  and the assertion of the hit/miss signal  87  by the hit/miss circuitry  83  is validated. Otherwise, the speculative hit signal  55  is determined to have been a false hit signal and the speculative data  53  is determined to have been false data. In that event, the way predicting cache  50  is loaded with new data via the data path  84  (e.g., from system memory or from another cache memory in response to the physical address  88  asserted by the TLB  81 ) and with a corresponding partial tag from the virtual address  86 . Similarly, if the speculative hit signal  55  is not asserted initially (i.e., the virtual address  86  misses the way-predicting cache), then the way predicating cache  50  is loaded with a new partial tag from the virtual address  86  and with new data obtained via the data path  84 . 
     It will be appreciated that the benefit of advanced data output from the way-predicting cache becomes more pronounced as the percentage of correct speculative hits (i.e., speculative hits that are not ultimately determined to be false) is increased. Accordingly, it is desirable to increase the partial tag size to a size that achieves a relatively high percentage of correct speculative hits, but that does not introduce significantly longer comparison delay than the set field decode delay. According to one embodiment, it is found that by using a partial tag that includes the number of bits necessary to resolve the number of ways in a given cache word (e.g., log 2 (no. ways)) plus three or four additional bits, a sufficiently high percentage of correct speculations can be achieved to realize the benefit of the advanced data output of the way-predicting cache. For example, in one embodiment, a five-bit partial tag is used to generate speculative hit information for a cache having four data ways per cache word (e.g., a five-bit partial tag field out of a complete tag field of twenty or more bits). In alternate embodiments, the number of bits in the partial tag may vary from the number of bits necessary to resolve the number of ways per cache word to any number of bits that is fewer than the number of bits in the complete tag field. 
     FIG. 6 illustrates a cache replacement strategy for a way predicting cache memory according to one embodiment. Starting at decision block  101 , if a speculative hit has occurred in response to a memory access request, then decision block  103  is entered to determine if an actual hit has occurred. If an actual hit has occurred, then the memory access request actually hit the way predicting cache and no replacement of data or partial tags is necessary. If, at decision block  101 , a speculative hit is not detected, then at block  105 , the cache line in the least recently used way of the cache word indicated by the set field decoder (e.g., element  56  of FIG. 3) is replaced. Referring to FIG. 5, for example, the data returned on the data path  84  is input to the way predicting cache memory and stored in the least recently used data way. According to one embodiment, a least-recently-used bit (LRU bit) is associated with each data way in the cache data store to indicate that the data way (and its corresponding partial tag register) is to be overwritten with new data if a miss occurs. One LRU bit is set per group of data ways that form a given cache word. When a miss occurs on the data ways of a selected cache word, the data way indicated by its LRU bit to be the least recently used data way within the cache word is updated with new data, and another data way within the cache word is selected to be the new least-recently-used data way and its associated LRU bit is set. In one embodiment, referred to as a pseudo-least-recently-used technique, the selection of the new least-recently-used data way is predetermined by combinatorial logic based on the previous least-recently used data way. In an alternate embodiment, referred to as a true least recently-used technique, LRU bits associated with the data ways of a given cache word indicate not only the least recently used data way, but also the next least recently used data way and so forth to the most recently used data way. In this arrangement, the relative usage order of the different data ways is evaluated by combinatorial logic to identify a new least-recently-used data way after the existing least recently used data way is updated with new data. Still referring to FIG. 6, at block  107 , the partial tag that corresponds to the least recently used way of the cache word indicated by the set field decoder is replaced with a partial tag that corresponds to the cache line stored in the cache data store in block  105 . At block  109 , the least recently used indicator for the cache word indicated by the set field decoder is updated. 
     If it is determined at block  103  that, despite the speculative hit indicated by the way predicating cache memory, a cache miss has occurred, then the cache line in the data way indicated by the false way enable signal (i.e., the way enable signal giving rise to the false speculative hit) is replaced at block  111 . At block  113 , the partial tag that caused the false way signal is replaced with the partial tag that corresponds to the replacement cache line. At block  115 , the least recently used indicator for the cache word used to supply the speculative data is updated. 
     Although a cache replacement strategy based on specific least recently used techniques has been described, other least recently used techniques and cache replacement techniques other than least recently used techniques may be used in alternate embodiments. 
     In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly to be regarded in an illustrative rather than a restrictive sense.