Abstract:
A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a divisional application from U.S. application Ser. No. 14/677,404 filed Apr. 2, 2015, the disclosure of which is incorporated by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to integrated circuits and, in particular, to junction field effect transistor (JFET) devices fabricated using fins with vertical junctions. 
       BACKGROUND 
       [0003]    The prior art teaches the formation of integrated circuits which utilize one or more junction field effect transistor (JFET) devices. The JFET device includes a junction formed under a gate conductor. Rather than use an insulated gate, as is conventional MOSFET-type devices, a field is applied by the junction acting as a gate. Current flows between the source and drain regions in a doped semiconductor region located under the gate. Through application of a voltage to the gate conductor, a region of depleted charge forms in the doped semiconductor region so as to pinch off the conducting path and restrict the flow of current. Because of the lack of available mobile charge, the depletion region behaves as an insulating structure. 
         [0004]    The conventional JFET device is an attractive circuit for use in analog designs. The device is simple to form and operate. However, such JFET devices suffer from a noted drawback in that short channel effects are difficult to control. Additionally, the typical manufacture of JFET devices is incompatible with mainstream CMOS fabrication techniques. There is accordingly a need in the art to address the foregoing and other issues to provide a JFET device of improved configuration and operation, wherein manufacture of the device is compatible with CMOS techniques. 
       SUMMARY 
       [0005]    In an embodiment, an integrated circuit transistor device comprises: a semiconductor substrate; a region within the semiconductor substrate doped with a first conductivity-type dopant; a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the first conductivity-type dopant; a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the first conductivity-type dopant; and a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with a second conductivity-type dopant. 
         [0006]    In an embodiment, a method comprises: implanting dopant of a first conductivity-type in a semiconductor substrate to form a first doped region; patterning the first doped region to define a fin having a first end and having a second end and having sidewalls between said first and second ends; implanting dopant of the first conductivity-type in the semiconductor substrate to form a second doped region in contact with the first end of the fin; epitaxially growing first semiconductor material to form a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the first conductivity-type dopant; and epitaxially growing second semiconductor material to form a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with a second conductivity-type dopant. 
         [0007]    In an embodiment, an integrated circuit comprises: a semiconductor substrate; a first region within the semiconductor substrate doped with a first conductivity-type dopant; a second region within the semiconductor substrate doped with a second conductivity-type dopant; a first fin of semiconductor material having a first end in contact with said first region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the first conductivity-type dopant; a second fin of semiconductor material having a first end in contact with said second region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the second conductivity-type dopant; a first epitaxial region in contact with the second end of the first fin of semiconductor material, said first epitaxial region doped with the first conductivity-type dopant; a second epitaxial region in contact with the second end of the second fin of semiconductor material, said second epitaxial region doped with the second conductivity-type dopant; a third epitaxial region in contact with sidewalls of the first fin of semiconductor material, said third epitaxial region doped with the second conductivity-type dopant; and a fourth epitaxial region in contact with sidewalls of the second fin of semiconductor material, said fourth epitaxial region doped with the first conductivity-type dopant. 
         [0008]    In an embodiment, a method comprises: patterning a semiconductor substrate doped with a first conductivity-type to define a fin having a first end and having a second end and having sidewalls between said first and second ends; implanting dopant of the first conductivity-type in the semiconductor substrate to form a source region in contact with the first end of the fin; epitaxially growing first semiconductor material to form a drain region in contact with the second end of the fin of semiconductor material, said drain region doped with the first conductivity-type dopant; and epitaxially growing second semiconductor material to form a gate region in contact with sidewalls of the fin, said gate doped with a second conductivity-type dopant. 
         [0009]    In an embodiment, a method comprises: defining a plurality of fins of a first conductivity-type, each fin supported at a first end by a support substrate and having a second end and having sidewalls between said first and second ends; doping the support substrate at the first ends of the plurality of fins with the first conductivity-type to define a source region in contact with the first ends of the plurality of fins; epitaxially growing semiconductor material on the sidewalls of the plurality of fins to form a gate region for each fin; epitaxially growing semiconductor material at the second ends of the plurality of fins to form a drain region for each fin; and forming electrical contacts to the source region, the gate regions and the drain regions. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which: 
           [0011]      FIGS. 1-15C  illustrate process steps in the formation of a vertical junction FinFET device, and in particular a plurality of such devices in a CMOS implementation. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    Reference is now made to  FIGS. 1-15C  which illustrate the process steps in the formation of a vertical junction FinFET device. It will be understood that the drawings do not necessarily show features drawn to scale. 
         [0013]      FIG. 1  shows a conventional bulk semiconductor substrate  10  including an area  12  which is reserved for the formation of first polarity (n-channel) devices (NFET) and an area  14  which is reserved for the formation of second, opposite, polarity (p-channel) devices (PFET). A silicon dioxide (SiO 2 ) layer  16  is deposited, for example using a chemical vapor deposition (CVD) process, on the substrate  10  with a thickness of, for example, approximately 3 nm. Using lithographic techniques well known to those skilled in the art, area  14  is blocked off with an implant mask and an implant of n-type dopants (such as, for example, arsenic or phosphorous) is made in area  12  to define an n-type region  18 . This implant may, for example, provide the region  18  with a dopant concentration of 1×10 18  to 5×10 18  at/cm 3 . Using lithographic techniques well known to those skilled in the art, area  12  is blocked off with an implant mask and an implant of p-type dopants (such as, for example, boron) is made in area  14  to define a p-type region  20 . This implant may, for example, provide the region  20  with a dopant concentration of 1×10 18  to 5×10 18  at/cm 3 . The regions  18  and  20  have a depth, for example, of 50-80 nm. 
         [0014]      FIG. 2  shows the deposit of a silicon nitride (SiN) layer  22  over the silicon dioxide layer  16 . This deposition may be made, for example, using a chemical vapor deposition (CVD) process to provide layer  22  with a thickness of 30-50 nm. This silicon nitride layer  22  forms a hard mask. 
         [0015]    A lithographic process as known in the art is then used to define a plurality of fins  40  from the doped material of the regions  18  and  20 . The hard mask is patterned to leave mask material  24  at the desired locations of the fins  40 . An etching operation is then performed through the mask to open apertures  42  in the regions  18  and  20  of the substrate  10  on each side of each fin  40 . The result of the etching process is shown in  FIG. 3  with each fin  40  having a first end at the substrate and a distal second end. Each fin  40  may have a height (h) of 50-80 nm. In a preferred embodiment, the etch which defines the fins  40  extends to the full depth of the regions  18  and  20 . In each of the areas  12  and  14 , the fins  40  may have a width (w) of 6-15 nm and a pitch (p) of 20-50 nm. 
         [0016]    Next, the area  14  is blocked off (reference  50 ) and an implant  52  of n-type dopants (such as, for example, arsenic or phosphorous) is made in area  12  of the substrate  10  to define an n-type source region  54  in contact with the first ends of the fins  40  in area  12 . This implant  52  may, for example, provide the source region  54  with a dopant concentration of 1×10 20  to 5×10 20  at/cm 3  which is in excess of the dopant concentration in each of the fins  40  located above the source region  54 . The result is shown in  FIG. 4 . The blocking mask (reference  50 ) is then removed. 
         [0017]    Next, the area  12  is blocked off (reference  60 ) and an implant  62  of p-type dopants (such as, for example, boron) is made in area  14  of the substrate  10  to define a p-type source region  64  in contact with the first ends of the fins  40  in area  14 . This implant  62  may, for example, provide the source region  64  with a dopant concentration of 1×10 20  to 5×10 20  at/cm 3  which is in excess of the dopant concentration in each of the fins  40  located above the source region  64 . The result is shown in  FIG. 5 . The blocking mask (reference  60 ) is then removed. 
         [0018]    A shallow trench isolation (STI) structure  70  is then formed in the substrate  10  to separate the areas  12  and  14 . The STI structure  70  may, for example, comprise silicon oxide material which fills a trench formed in the substrate  10 . This insulation material further covers the source regions  54  and  64  in a layer  72  to locally insulate bottom portions of the fins  40  from each other. The local insulation layer  72  may, for example, have a thickness of 20-30 nm (thus leaving about 35-50 nm of each fin  40  exposed). The STI structure  70  may have a depth of approximately 200 nm. 
         [0019]    A silicon nitride liner  80  is then deposited to cover the fins  40 . The deposition may, for example, be made using an atomic layer deposition (ALD) process. The liner  80  may, for example, have a thickness of 2-6 nm. The result is shown in  FIG. 7 . 
         [0020]    Next, the area  14  is blocked off (reference  90 ), the liner  80  is removed from the fins  40  in the area  12  (using any suitable wet or dry etch technique) to expose the sidewalls of the fins  40 , and an epitaxial growth process as known in the art is performed to grow a silicon or silicon-germanium (SiGe) gate structure  92  from and in contact with the exposed sidewall surfaces of each fin  40 . As the fins  40  in area  12  are of n-type, the epitaxially grown gate structures  92  are of p-type to form a p-n junction at the fin sidewalls. Preferably, the epitaxial growth is in situ doped with a suitable p-type dopant such as, for example, boron. The gate structures  92  may, for example, have a dopant concentration of 1×10 20  to 5×10 20  at/cm 3 . The result of the epitaxial growth process is shown in  FIG. 8 . The blocking mask (reference  90 ) is then removed. 
         [0021]    Next, the area  12  is blocked off (reference  94  including a new silicon nitride liner (not explicitly shown) on the gate structures  92 ), the liner  80  is removed from the fins  40  in the area  14  (using any suitable wet or dry etch technique) to expose the sidewalls of the fins  40 , and an epitaxial growth process as known in the art is performed to grow a silicon or silicon-carbide (SiC) gate structure  96  from and in contact with the exposed sidewall surfaces of each fin  40 . As the fins  40  in area  14  are of p-type, the epitaxially grown gate structures  96  are of n-type to form a p-n junction at the fin sidewalls. Preferably, the epitaxial growth is in situ doped with a suitable n-type dopant such as, for example, arsenic. The gate structures  96  may, for example, have a dopant concentration of 1×10 20  to 5×10 20  at/cm 3 . The result of the epitaxial growth process is shown in  FIG. 9 . The blocking mask (reference  94 , with the included silicon nitride liner) is then removed. 
         [0022]    A layer  100  of an insulating material is then deposited on the substrate to height which at least exceeds the height of the mask material  24  present on top of each fin  40 . The deposition process may, for example, comprise a chemical vapor deposition (CVD) of silicon dioxide. A chemical mechanical polishing is then performed to planarize a top surface of the layer  100  to a level which is coplanar with a top of the mask material  24 . The result is shown in  FIG. 10 . 
         [0023]    For the fins  40  in the area  12 , the mask material  24  (remaining patterned portions of layers  16  and  22 ) is selectively removed to form openings  102  which expose the top surface at the distal second end of each fin  40 . Prior to removal, a liner of silicon nitride (not explicitly shown) may be deposited using an atomic layer deposition (ALD) process in the area  14 . The removal of the mask material  24  in area  12  may be accomplished using a selective etch (such as, for example, a hot phosphoric acid etch). The result is shown in  FIG. 11 . 
         [0024]    An epitaxial growth process as known in the art is then performed to grow a silicon or silicon-carbide (SiC) drain structure  110  from and in contact with the exposed top surface of each fin  40 . As the fins  40  in area  12  are of n-type, the epitaxially grown drain structures  110  are also of n-type. Preferably, the epitaxial growth is in situ doped with a suitable n-type dopant such as, for example, phosphorous. The drain structures  110  may, for example, have a dopant concentration of 1×10 20  to 5×10 20  at/cm 3  which is in excess of the dopant concentration for the fins  40  in area  12 . The result of the epitaxial growth process is shown in  FIG. 12 . 
         [0025]    For the fins  40  in the area  14 , the mask material  24  (remaining patterned portions of layers  16  and  22 ) is selectively removed to form openings  104  which expose the top surface at the distal second end of each fin  40 . Prior to removal, a liner of silicon nitride (not explicitly shown) may be deposited using an atomic layer deposition (ALD) process in the area  12 . The removal of the mask material  24  in area  14  may be accomplished using a selective etch (such as, for example, a hot phosphoric acid etch). The result is shown in  FIG. 13 . 
         [0026]    An epitaxial growth process as known in the art is then performed to grow a silicon or silicon-germanium (SiGe) drain structure  112  from and in contact with the exposed top surface of each fin  40 . As the fins  40  in area  14  are of p-type, the epitaxially grown drain structures  112  are also of p-type. Preferably, the epitaxial growth is in situ doped with a suitable p-type dopant such as, for example, boron. The drain structures  112  may, for example, have a dopant concentration of 1×10 20  to 5×10 20  at/cm 3  which is in excess of the dopant concentration for the fins  40  in area  14 . The result of the epitaxial growth process is shown in  FIG. 14 . 
         [0027]    A premetal dielectric (PMD) layer  120  is then deposited on top of the layer  100  of an insulating material. The layer  120  may, for example, comprise silicon dioxide deposited using a chemical vapor deposition process to a thickness of 50-500 nm. Electrical contacts  122  to the gate structures  92  and  94 , the source regions  54  and  64  and the drain regions  110  and  112  are them formed using conventional etch and fill techniques known to those skilled in the art. The metal used for the contacts  122  may, for example, comprise tungsten. The contacts  122  for the gate structures  92  and  94  may be offset from the contacts  122  for the source regions  54  and  64  and the drain regions  110  and  112  as shown in  FIGS. 15A-15C . 
         [0028]    The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.