Abstract:
A data driving circuit and method for an organic light emitting diode display. Data lines transmit first digital data in a first cycle, and subsequent digital data in a second cycle. A D/A converter electrically connected to the data lines converts the first digital data to first analog data, and converts the subsequent digital data to second analog data. Each analog sampling storage circuit electrically coupled to the D/A converter, in the first cycle, stores the first analog data, in the second cycle, outputs the first analog data and stores the second analog data, and in a third cycle, outputs the second analog data.

Description:
BACKGROUND 
   The present invention relates to a data driving circuit for an organic light emitting diode display, and more particularly, to a data driving circuit with a single D/A converter. 
   Digital data drivers for conventional organic light emitting displays normally use a storage register (digital latch), as a line buffer to store digital video signal in a signal cycle. 
     FIGS. 1A and 1B  show a conventional 6-bit digital data driving scheme  10 , in which binary bits of digital video data are loaded sequentially during a horizontal scan cycle. First, through data lines R[ 5 ]˜B[ 0 ], binary bits of digital video data are written to corresponding first latches  11 , all controlled by a sampling signal applied by a shift register SRn. Next, through data lines R[ 5 ]˜B[ 0 ], subsequent digital video data of binary bits are written to corresponding first latches  21 , all controlled by a sampling signal applied by a shift register SRn+1. Similarly, all the digital video data for a horizontal scan cycle is respectively stored into first latches. When the line buffer signal “LB” is asserted, all bits of digital video data stored in first latches  11  and  21  are written to the second latches  12 ,  22  and transmitted to the digital-to-analog converters DAC-Rn, DAC-Gn, DAC-Bn at the same time. 
   Data bit number increases with resolution, and the number of area-consuming storage registers and the number of digital-to-analog converters also increase. In the conventional layout of a digital driving circuit, when a data bit number increases with resolution, the number of storage registers and the number of the digital-to-analog converters also increase, and make layout more difficult due to limited horizontal layout area. 
   SUMMARY 
   It is an object of the present invention to provide a data driving circuit comprising data lines, a D/A converter and a plurality of analog sampling storage circuits. The data lines transmit first digital data in a first cycle, and subsequent digital data in a second cycle. The D/A converter electrically connected to the data lines converts the first digital data to first analog data, and the subsequent digital data to second analog data. Each analog sampling storage circuit electrically coupled to the D/A converter, in the first cycle, stores the first analog data, in the second cycle, outputs the first analog data and stores the second analog data, and in a third cycle, outputs the second analog data. 
   An organic light emitting diode display is also provided, comprising pixels, a scan driving circuit and a data driving circuit. The pixels are arranged in columns and rows. The scan driving circuit selects a row of pixels in sequence. The data driving circuit comprises data lines, a D/A converter and a plurality of analog sampling storage circuits. The data lines transmit first digital data in a first cycle, and subsequent digital data in a second cycle. The D/A converter electrically connected to the data lines converts the first digital data to first analog data, and converts the subsequent digital data to second analog data. Each analog sampling storage circuit electrically coupled to the D/A converter, in the first cycle, stores the first analog data, in the second cycle, outputs the first analog data and stores the second analog data, and in a third cycle, outputs the second analog data. 
   A driving method for an organic light emitting diode display is also provided. In a first cycle, first digital data is converted to first analog data, which is then stored. In a second cycle, subsequent digital data is converted to second analog data for storage and the first analog data is output to a pixel. The second analog data is output in a third cycle. 
   A detailed description is given in the following with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
       FIG. 1A  and  FIG. 1B  show a conventional digital data driving circuit; 
       FIG. 2  illustrates an organic light emitting display; 
       FIG. 3  is a block circuit diagram of a data driving circuit of an embodiment of the invention; 
       FIG. 4  shows a detailed circuit of a data driving circuit of an embodiment of the invention shown in  FIG. 3 ; and  FIG. 5  is a timing diagram of the data driving circuit of an embodiment of the invention. 
   

   DETAILED DESCRIPTION 
     FIG. 2  shows an organic light emitting diode display  200 , comprising an active matrix array  201  with a plurality of pixels arranged in columns and rows, a scan driving circuit  202  sequentially selecting one row of pixels of the active matrix array  201 , and a data driving circuit  203  outputting data to corresponding pixels. 
     FIG. 3  is a block diagram of the data driving circuit  203  in  FIG. 2 , comprising a plurality of data driving lines DL 1 ˜DLm, a D/A converter  3 , a plurality of analog sampling storage circuits  4 _ 1 ˜ 4 _m, and a plurality of pixels  6 _ 1 ˜ 6 _m. 
   The D/A converter  3  is coupled to the data lines DL 1 ˜DLm converting digital data to corresponding analog data. The analog sampling storage circuits  4 _ 1 ˜ 4 _m are coupled to the D/A converter  3 . Hereinafter, ENB is an enabling signal and XENB represents the reverted signal of ENB. One enabling sampling signal among SR_n+1˜SR_n+m turns on one of the analog sampling storage circuits  4 _ 1 ˜ 4 _m to sample the analog data transmitted from the D/A converter  3  and to drive a corresponding pixel with a stored signal sampled during the last horizontal scan cycle. There are two identical, parallel-operating storage schemes in one analog sampling storage circuit. One samples and the other performs a driving operation. For example, during a horizontal scan cycle A, in which ENB is asserted and XENB is therefore disserted, the first storage sampling storage circuit  4 _ 1  samples incoming analog data I_DAC 1  and at the same time drives a corresponding pixel with the stored signal sampled during the last horizontal scan cycle. During the next horizontal scan cycle B, in which ENB is disserted and XENB asserted, the first storage sampling storage circuit  4 _ 1  samples incoming analog data I_DAC 2  and at the same time drives the corresponding pixel with the stored signal sampled during the last horizontal scan cycle. 
     FIG. 4  shows a detailed circuit of a data driving circuit of one embodiment of the invention shown in  FIG. 3 . In  FIG. 4 , 6-bit Data D 0 ˜D 5  are transmitted to a 6-bit D/A converter  3  through signal lines DL 1 ˜DL 6 . The data driving circuit  203  comprises two analog sampling circuits  4 _ 1  and  4 _ 2 . 
   The analog sampling storage circuit  4 _ 1  comprises a transistor MP 2  as a current recorder between a voltage source VDD and a D/A converter  3 . A switch SW 6  (the sixth switch) is between the gate of the transistor MP 2  and the drain of the transistor MP 2 , and a switch SW 5  (the fifth switch) is between the drain of the transistor MP 2  and the D/A converter  3 . When the sampling signal SR_n+1 is asserted, the switches SW 5  and SW 6  are turned on to create current from the D/A converter  3  through transistor MP 2 . The gate voltage of the transistor MP 2  records and represents current therethrough and accordingly records the current through the D/A converter  3 . Two storage capacitors C 1  and C 2  are coupled between a voltage source VDD and a first node in parallel, both sampling and storing the gate voltage of MP 2 . A switch SW 1  (the first switch) is between the storage capacitor C 1  and the first node N 1 . A switch SW 3  (the third switch) is between the storage capacitor C 2  and the first node N 1 . Controlled by either ENB or XENB, the switch SW 1  is turned on while the switch SW 3  is turned off, and vice versa. A transistor MP 1  between the voltage source VDD and a pixel  6 _ 1  has a gate coupled to the storage capacitor C 1  through a switch SW 2  (the second switch) and coupled to the storage capacitor C 2  through a switch SW 4  (the fourth switch). The voltage on either the storage capacitor C 1  or the storage capacitor C 2  causes the transistor MP 1  to generate a corresponding current and drive a corresponding pixel. Controlled by either ENB or XENB, the switch SW 2  is turned on while the switch SW 4  is turned off, and vice versa. Note that SW 1  and SW 4  are turned on simultaneously by the same control signal, ENB, and SW 2  and SW 3  are turned on simultaneously by another control signal, XENB. 
   The analog sampling storage circuit  4 _ 2  comprises transistors MP 3  and MP 4 , two storage capacitors C 3  and C 4 , and switches SW 7 –SW 12 , the same as analog sampling storage circuit  4 _ 1 . Thus, its description is omitted here. 
     FIG. 5  illustrates a timing diagram of the data driving circuit  203 . Only operation and timing of analog sampling storage circuit  4 _ 1  are presented. First, in a cycle A (the first cycle), digital data D 0 ˜D 5  (first digital data) are transmitted to the D/A converter  3  through corresponding the data lines DL 1 ˜DL 6  to convert to corresponding analog data I_DAC 1  (first analog data), such as current data as an example. Next, the sampling signal SR_n+1 is asserted to turn on the switches SW 5  and SW 6 . The first signal ENB is asserted to-turn on the switches SW 1  and SW 4 . The gate voltage of MP 2 , representing the analog data I_DAC 1 , is sampled and written to the storage capacitor C 1  through switches SW 5 , SW 6  and SW 1 . 
   In a cycle B (the second cycle), the first signal ENB is de-asserted, turning off switches SW 1  and SW 4 , and the second signal XENB asserted, turning on switches SW 2  and SW 3 . The sampled voltage on the storage capacitor C 1 , representing analog data I_DAC 1 , is sent to the gate of the transistor MP 1  through turned-on SW 2  to generate corresponding analog data I_DATA 1  to a pixel  6 _ 1 . At the same time, bits of subsequent digital data, D 0 D 5  (second digital data) are written into D/A converter  3  to convert to corresponding analog data I_DAC 2  (second analog data). When the switches SW 5  and SW 6  are turned on according to the sampling signal SR_n+1, the analog data I_DAC 2  (second analog data) is written to the storage capacitor C 2  through turned-on SW 3 , and not to the storage capacitor C 1  since SW 1  is turned off. 
   In cycle C (the third cycle), the first signal ENB is asserted to turn on switches SW 1  and SW 4 . The voltage on the storage capacitor C 2 , representing the analog data I_DAC 2 , is coupled to the gate of the transistor MP 1  to generate corresponding analog data I_DATA 2  to the pixel  6 _ 1 . 
   The operation of the analog storage circuit  4 _ 2  is the same as analog storage circuit  4 _ 1 , with the difference that the switches SW 11  and switch SW 12  are turned on when sampling signal SR_n+2 is asserted in a corresponding cycle. 
   One of the switches may be a transistor or transmission gate. 
   While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.