Abstract:
There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a semiconductor design technology; and, more particularly, to an internal voltage generating circuit for maintaining a stable high voltage level because of a fast response time.  
       DESCRIPTION OF RELATED ART  
       [0002]     In semiconductor memory devices, an internal voltage generating circuit receives an external voltage VDD to generate various levels of an internal voltage.  
         [0003]     With a low voltage and a low power consumption of the semiconductor memory devices, internal voltage generating circuits are increasingly employed in DRAMs.  
         [0004]     Meanwhile, since the voltages used in the semiconductor memory devices are internally generated, many attempts have been made to generate stable internal voltages regardless of ambient temperature, process, or pressure.  
         [0005]      FIG. 1  is a block diagram of a conventional internal voltage generating circuit.  
         [0006]     Referring to  FIG. 1 , the conventional internal voltage generating circuit includes a level detector  10 , an oscillator  20 , a first pumping control signal generator  32 , a second pumping control signal generator  34 , a first charge pump  42 , and a second charge pump  44 . The first and second charge pumps  42  and  44  positively pump an external voltage VDD to generate a high voltage VPP higher than the external voltage VDD. The level detector  10  detects a level of the high voltage VPP. The oscillator  20  generates a periodic signal OSC in response to a detection signal PPE of the level detector  10 . The first pumping control signal generator  32  generates a plurality of pumping control signals for controlling a driving of the first charge pump  42  in response to the periodic signal OSC. The second pumping control signal generator  34  generates a plurality of pumping control signals for controlling a driving of the second charge pump  44  in response to an inverted periodic signal.  
         [0007]     In such an internal voltage generating circuit, when the level of the high voltage VPP decreases, its level decrease is detected through the level detector  10  and then the charge pumps  42  and  44  are driven by the oscillator  20  and the first and the second pumping control signal generators  32  and  34 . Therefore, the high voltage VPP is maintained to a constant level.  
         [0008]      FIG. 2  is a circuit diagram of the level detector  10  shown in  FIG. 1 .  
         [0009]     Referring to  FIG. 2 , the level detector  10  includes a voltage divider  12  and a differential amplifier  14 . The voltage divider  12  is configured with serially connected resistors to divide the high voltage VPP. The differential amplifier  14  amplifiers a level difference between an output voltage of the voltage divider  12  and a reference voltage VREF to output the detection signal PPE.  
         [0010]     When the output voltage of the voltage divider  12  is lower than the reference voltage VREF, the level detector  10  outputs the detection signal PPE of a logic high level, and otherwise, the level detector  10  outputs the detection signal of a logic low level.  
         [0011]      FIG. 3  is a circuit diagram of the oscillator  20  shown in  FIG. 1 .  
         [0012]     The oscillator  20  includes a first inverter chain  22 , a NAND gate ND 1 , and a second inverter chain  24 .  
         [0013]     The first inverter chain  22  delays and inverts the periodic signal OSC to generate a feedback periodic signal. The NAND gate ND 1  receives the feedback periodic signal and the detection signal PPE. The second inverter chain  24  delays and inverts an output signal of the NAND gate ND 1  to generate the periodic signal OSC.  
         [0014]     The oscillator  20  is controlled by the detection signal PPE to generate the periodic signal OSC. That is, when the detection signal PPE is a logic high level, the oscillator  20  generates the periodic signal OSC that is toggled at a constant period. On the contrary, when the detection signal PPE is a logic low level, the oscillator  20  generates a logic low level signal as the periodic signal OSC.  
         [0015]      FIG. 4  is a circuit diagram of the first pumping control signal generator  32  shown in  FIG. 1 .  
         [0016]     Since the second pumping control signal generator  34  has the same circuit configuration as the first pumping control signal generator  32 , the first pumping control signal generator  32  alone will be described below.  
         [0017]     Referring to  FIG. 4 , the first pumping control signal generator  32  includes a first to a fourth delay units  32   a ,  32   b ,  32   c  and  32   d , and a signal generating unit  32   e.    
         [0018]     The first to the fourth delay units  32   a ,  32   b ,  32   c  and  32   d  are connected in series to output delay periodic signals T 1 , T 2 , T 3  and T 4  by delaying a signal outputted from a previous stage of a corresponding delay unit. That is, the first delay unit  32   a  receives the periodic signal OSC to output the first delay periodic signal T 1 , and the second delay unit  32   b  delays an output of the first delay unit  32   a  to output the second delay periodic signal T 2 . The third delay unit  32   c  delays an output of the second delay unit  32   b  to output the third delay periodic signal T 3 . The fourth delay unit  32   d  delays an output of the third delay unit  32   c  to output the fourth delay periodic signal T 4 . The signal generating unit  32   e  receives the first to the fourth delay periodic signals T 1 , T 2 , T 3  and T 4  to output a plurality of pumping control signals OSC_T 1 , OSC_T 2 , OSCB_T 1 , OSCB_T 2 , PACP 0 , PCAP 1  and PCAP 2 .  
         [0019]      FIG. 5  is an operational waveform of the first pumping control signal generator  32  shown in  FIG. 4 .  
         [0020]     Referring to  FIG. 5 , the first to the fourth delay units  32   a ,  32   b ,  32   c  and  32   d  generate the first to the fourth delay periodic signal T 1 , T 2 , T 3  and T 4  having a different delay time from the periodic signal OSC. The signal generating unit  32   e  generates a plurality of pumping control signals OSC_T 1 , OSC_T 2 , OSCB_T 1 , OSCB_T 2 , PCAP 0 , PCAP 1  and PCAP 2  through a logic combination of the first to the fourth delay periodic signals T 1 , T 2 , T 3  and T 4  so as to drive the first charge pump  42 . Activation periods of the pumping control signals OSC_T 1 , OSC_T 2 , OSCB_T 1 , OSCB_T 2 , PCAP 0 , PCAP 1  and PCAP 2  are not overlapped with one another.  
         [0021]     As described above, the first and the second pumping control signal generators  32  and  34  have the same circuit configuration, while the second pumping control signal generator  34  receives the inverted periodic signal. Accordingly, the second pumping control signal generator  34  generates a plurality of pumping control signals having a phase difference of 180° from the signals shown in  FIG. 5 .  
         [0022]      FIG. 6  is a circuit diagram of the first charge pump  42  shown in  FIG. 1 .  
         [0023]     The first and second charge pumps  42  and  44  have the same circuit configuration.  
         [0024]     The first charge pump  42  generates the high voltage VPP by pumping the external voltage VDD in response to the pumping control signals OSC_T 1 , OSC_T 2 , OSCB_T 1 , OSCB_T 2 , PCAP 0 , PCAP 1  and PCAP 2 . Therefore, detailed operations from a time point ‘a’ in  FIG. 5  will be described below.  
         [0025]     First, since the pumping control signal PCAP 0  has a ground voltage VSS level of a logic low level, a node TRN_CTR 0  is set to (VDD-Vt).  
         [0026]     Then, when the pumping control signal PCAP 0  changes to a VDD level of a logic high level, the node TRN_CTR 0  is set to (2VDD-Vt) by a capacitor C 1 . Accordingly, NMOS transistors NM 1 , NM 2  and NM 3  are turned on in response to a voltage of the node TRN_CTR 0 , so that nodes BT 1 , T 1 B and TRN_CTR 1  increase to the VDD level.  
         [0027]     The pumping control signal OSC_T 1  changes from the high level to the low level. An NMOS transistor NM 4  is turned off in response to the pumping control signal OSC_T 1 , so that a node T 1 HB is opened from the ground voltage VSS supply.  
         [0028]     The pumping control signal OSCB_T 2  is set to a logic high level, so that a node T 2 HB is grounded with the ground voltage VSS supply. A node T 2 B is set to (VDD-Vt).  
         [0029]     Then, the pumping control signal PCAP 1  changes to a logic high level, so that the node BT 1  increases to 2VDD.  
         [0030]     Also, since the pumping control signal OSCB_T 1  changes to a logic high level, the node T 1 B increases to 2VDD and thus an NMOS transistor NM 5  and a PMOS transistor PM 1  are turned on. Accordingly, the node TRN_CTR 0  is set to the VDD level by the NMOS transistor NM 5  and the node T 1 HB increases to 2VDD by the PMOS transistor PM 1 .  
         [0031]     A capacitor C 2  having one terminal connected to the node T 1 HB pumps the node TRN_CTR 1  to 3VDD by 2VDD of the node T 1 HB. Therefore, the NMOS transistor NM 6  is turned on in response to the voltage of the node TRN_CTR 1 , so that a level of the node BT 2  is 2VDD equal to that of the node BT 1 .  
         [0032]     Then, the pumping control signal OSCB_T 2  changes to a logic low level. An NMOS transistor NM 7  is turned off so that the node T 2 HB is opened from the ground voltage VSS supply. An NMOS transistor NM 8  is turned on in response to the voltage of the node TRN_CTR 1  and thus the node TRN_CTR 2  increases to 2VDD.  
         [0033]     Thereafter, the pumping control signal PCAP 2  changes to a logic high level. A capacitor C 3  having one terminal receiving the pumping control signal PCAP 2  pumps the node BT 2  to 3VDD.  
         [0034]     The pumping control signal OSC_T 2  changes to a logic high level. The node T 2 B increases to 2VDD by a capacitor C 4  having one terminal receiving the pumping control signal OSC_T 2 . A level of the node T 2 HB is 2VDD equal to that of the node T 2 B by the PMOS transistor PM 2  turned on in response to the increased level of the node T 2 B. Therefore, the node TRN_CTR 2  is pumped to 4VDD by a capacitor C 5  having one terminal receiving the voltage of the node T 2 HB.  
         [0035]     Accordingly, an NMOS transistor NM 9  is turned on in response to the voltage of the node TRN_CTR 2 , so that 3VDD at the node BT 2  is outputted as the high voltage VPP.  
         [0036]     As described above, the first charge pump  42  positively pumps the external voltage VDD three times in response to the pumping control signals OSC_T 1 , OSC_T 2 , OSCB_T 1 , OSCB_T 2 , PCAP 0 , PCAP 1  and PCAP 2 , and then is outputted as the high voltage VPP.  
         [0037]     The second charge pump  44  receives the signals from the second pumping control signal generator  34  that outputs the pumping control signals with a phase difference of 180° from the output signals of the first pumping control signal generator  32 . Therefore, the first charge pump  42  supplies the high voltage while the first charge pump  42  is not driven.  
         [0038]     Consequently, the high voltage VPP is alternately supplied from the first and second charge pumps  42  and  44 .  
         [0039]     In the operation of the internal voltage generating circuit, it is assumed that threshold voltages of the MOS transistors are Vt.  
         [0040]     Meanwhile, the problem that the conventional internal voltage generating circuit cannot stably maintain the high voltage VPP will be described below with reference to  FIG. 7 .  
         [0041]     Referring to  FIG. 7 , a large amount of a high voltage is dissipated in a memory region at a time point when a word line WL is activated and deactivated by an active command ACT and a precharge command PCG.  
         [0042]     When the VPP level decreases lower than a reference voltage VREF, the conventional internal voltage generating circuit detects the decreased level to increase a supply of the high voltage VPP. Therefore, a response time becomes long and the VPP level is unstable.  
         [0043]     As described above, the level of the high voltage is not maintained stably, and if the level of the high voltage changes depending on the internal operation, noise is generated in cell data when a semiconductor memory device uses the high voltage in the word line, reducing the operational reliability of the device.  
       SUMMARY OF THE INVENTION  
       [0044]     It is, therefore, an object of the present invention to provide an internal voltage generating circuit for providing a stable high voltage by making a response time short.  
         [0045]     In accordance with an aspect of the present invention, there is provided an internal voltage generating circuit including: a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.  
         [0046]     In accordance with another aspect of the present invention, there is provided a semiconductor memory device for stably supplying a high voltage including: a charge pump unit for generating a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; an oscillator for generating a periodic signal in response to a driving signal, without detecting a level change of the high voltage; a pumping control signal generating unit for generating the pumping control signals for outputting the pumping control signals to the charge pump unit based on the periodic signal; and a supply driving control unit for receiving the periodic signal to generate the supply driving control signal to the charge pump unit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0047]     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0048]      FIG. 1  is a block diagram of a conventional internal voltage generating circuit;  
         [0049]      FIG. 2  is a circuit diagram of a level detector shown in  FIG. 1 ;  
         [0050]      FIG. 3  is a circuit diagram of an oscillator shown in  FIG. 1 ;  
         [0051]      FIG. 4  is a circuit diagram of a first pumping control signal generator shown in  FIG. 1 ;  
         [0052]      FIG. 5  is an operational waveform of the first pumping control signal generator shown in  FIG. 4 ;  
         [0053]      FIG. 6  is a circuit diagram of a first charge pump shown in  FIG. 1 ;  
         [0054]      FIG. 7  is a graph for explaining problems of the conventional internal voltage generating circuit;  
         [0055]      FIG. 8  is a block diagram of an internal voltage generating circuit in accordance with a first embodiment of the present invention;  
         [0056]      FIG. 9  is a block diagram of an internal voltage generating circuit in accordance with a second embodiment of the present invention;  
         [0057]      FIG. 10  is a circuit diagram of a pumping control signal generator shown in  FIG. 8 ;  
         [0058]      FIG. 11A  is a circuit diagram of an output control signal generator shown in  FIG. 8 ;  
         [0059]      FIG. 11B  is a circuit diagram of a level shifter shown in  FIG. 8 ;  
         [0060]      FIG. 12  is a circuit diagram of a charge pump shown in  FIG. 8 ; and  
         [0061]      FIG. 13  is an operational waveform of the internal voltage generating circuit shown in  FIG. 8 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0062]     Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, which is set forth hereinafter.  
         [0063]      FIG. 8  is a block diagram of an internal voltage generating circuit in accordance with a first embodiment of the present invention.  
         [0064]     Referring to  FIG. 8 , the internal voltage generating circuit includes a pumping control signal generator  100 , a charge pump  200 , and a supply driving controller  300 . The charge pump  200  positively pumps an external voltage VDD to generate a high voltage VPP higher than the VDD level. The pumping control signal generator  100  generates a plurality of pumping control signals for driving the charge pump  200  when an active command ACT is applied. The supply driving controller  300  receives the active command ACT and controls a supply of the high voltage VPP of the charge pump  200 .  
         [0065]     The supply driving controller  300  includes an output control signal generator  320  for receiving the active command ACT to generate an output control signal BB, and a level shifter  360  for shifting a level of the output control signal BB.  
         [0066]     Also, the charge pump  200  includes a supply driver configured with PMOS transistors to supply the high voltage VPP.  
         [0067]     In this embodiment, the internal voltage generating circuit positively pumps the external voltage VDD when the active command ACT is applied, and generates the high voltage VPP. That is, the internal voltage generating circuit supplies the high voltage VPP much more in response to the active command ACT, before a large amount of a current is rapidly dissipated in a memory region when the active command ACT is applied. Therefore, the level of the high voltage VPP can be maintained stably.  
         [0068]      FIG. 9  is a block diagram of an internal voltage generating circuit in accordance with a second embodiment of the present invention.  
         [0069]     Referring to  FIG. 9 , the internal voltage generating circuit includes an oscillator  400 , a pumping control signal generator  500 , a charge pump  600 , and a supply driving controller  700 .  
         [0070]     The charge pump  600  positively pumps an external voltage VDD to generate a high voltage VPP higher than the VDD level. The oscillator  400  generates a periodic signal OSC in response to an active command ACT. The pumping control signal generator  500  generates a plurality of pumping control signals P 1 , P 2 , P 3  and BT 0  for controlling a driving of the charge pump  600  in response to the periodic signal OSC. The supply driving controller  700  controls a supply of the high voltage VPP of the charge pump  600  in response to the periodic signal OSC.  
         [0071]     Compared with the first embodiment shown in  FIG. 8 , the internal voltage generating circuit shown in  FIG. 9  further includes the oscillator  400 . When the active command ACT is applied, the oscillator  400  generates the periodic signal OSC for a predetermined time. The pumping control signal generator  500  and the supply driving controller  700  are driven in response to the periodic signal OSC. By controlling the period of the periodic signal OSC and the generating time of the period, the driving time of the charge pump  600  can be controlled.  
         [0072]     In the case of the first embodiment, because the charge pump  200  is driven only when the active command ACT is applied, the internal voltage generating circuit in accordance with the first embodiment of the present invention can be used when the drivability is large enough to compensate for the internal current consumption. Also, the internal voltage generating circuit in accordance with the second embodiment of the present invention can be used by controlling the period of the periodic signal OSC according to an amount of the consumed high voltage VPP and a driving amount of the charge pump  600 .  
         [0073]     At this point, the active command ACT means a command that causes the elements to consume a large amount of the high voltage VPP. When the internal voltage generating circuit is used in the semiconductor memory device, the precharge command is also applied. Therefore, the internal voltage generating circuit can also be driven when the precharge command PCG is applied.  
         [0074]     In the second embodiment, the only difference from the first embodiment is that the oscillator  400  is further provided. Therefore, the configuration and operation of the internal voltage generating circuit shown in  FIG. 10  will be described below.  
         [0075]      FIG. 10  is a circuit diagram of the pumping control signal generator  100  shown in  FIG. 8 .  
         [0076]     Referring to  FIG. 10 , the pumping control signal generator  100  includes a first delay unit  120  for inverting and delaying the active command ACT to output a first delay signal, a second delay unit  140  for delaying the first delay signal to output a second delay signal, a third delay unit  160  for inverting and delaying the first delay signal to output a third delay signal, and a signal generating unit  180  for generating a plurality of pumping control signals P 1 , P 2 , P 3  and BT 0  for controlling a driving of the charge pump  200  through a logic combination of the first to the third delay signals.  
         [0077]     The first delay unit  120  is an inverter chain configured with three inverters, the second delay unit  140  is an inverter chain configured with six inverters, and the third delay unit  160  is an inverter chain configured with five inverters.  
         [0078]     The signal generating unit  180  includes a NAND gate ND 2  receiving the first and the second delay signals, inverters I 1  and I 2  for inverting an output signal of the NAND gate ND 2  to output the pumping control signals P 1  and P 2 , a buffer  182  for buffering the third delay signal to output the pumping control signal BT 0 , a NAND gate ND 3  receiving the first and second delay signals, and an inverter I 3  for inverting an output signal of the NAND gate ND 3  to output the pumping control signal P 3 .  
         [0079]     When the active command ACT has a logic low level, the pumping control signal generator  100  outputs the pumping control signals P 1 , P 2  and P 3  of a logic high level and the pumping control signal BT 0  of a logic low level.  
         [0080]     Meanwhile, when the active command ACT has a logic high level, the pumping control signal generator  100  outputs the pumping control signal BT 0  of a logic high level and the pumping control signals P 1 , P 2  and P 3  of a logic low level.  
         [0081]      FIG. 11A  is a circuit diagram of the output control signal generator  320 .  
         [0082]     Referring to  FIG. 11A , the output control signal generator  320  includes an inverter I 4  for inverting the active command ACT, a delay unit  322  for delaying an output signal of the inverter I 4 , and a NOR gate NR 1  for receiving the output signals of the inverter I 4  and the delay unit  322  to output the output control signal BB.  
         [0083]     When the active command ACT is activated to a logic high level, the output control signal generator  320  activates the output control signal BB to a logic high level after a time delay of the delay unit  322 . On the contrary, when the active command ACT is deactivated to a logic low level, the output control signal generator  320  activates the output control signal BB to a logic low level.  
         [0084]      FIG. 11B  is a circuit diagram of the level shifter  360  shown in  FIG. 8 .  
         [0085]     Referring to  FIG. 11B , the level shifter  360  includes an inverter I 5  for inverting the output control signal BB, a differential amplifier  362  receiving the output control signal BB and an inverted output control signal, an inverter I 6  for inverting an output signal of the differential amplifier  362  to output the supply driving control signal TRB having a swing width in the range from the high voltage VPP level to the ground voltage VSS level.  
         [0086]     When the output control signal BB is a logic low level, the level shifter  360  outputs the supply driving control signal TRB of the VPP level, that is, the logic high level. When the output control signal BB is a logic high level, the level shifter  360  outputs the supply driving control signal TRB of the ground voltage VSS level, that is, the logic low level.  
         [0087]      FIG. 12  is a circuit diagram of the charge pump  200  shown in  FIG. 8 .  
         [0088]     Referring to  FIG. 12 , in the charging pump  220 , a capacitor C 6  has one terminal receiving the pumping control signal P 1 . An NMOS transistor NM 10  has a drain and a gate connected to the external voltage VDD supply, and a source connected to the other terminal of the capacitor C 6 . An NMOS transistor NM 11  has a drain connected to the external voltage VDD supply, and a source and a gate connected to the other terminal of the capacitor C 6 . A capacitor C 7  has one terminal receiving the pumping control signal P 2 . An NMOS transistor NM 12  has a drain and a gate connected to the external voltage VDD supply, and a source connected to the other terminal connected to the capacitor C 7 . An NMOS transistor NM 13  has a drain connected to the external voltage VDD supply, and a source and a gate connected to the other terminal of the capacitor C 7 . A capacitor C 8  has one terminal connected to the pumping control signal BT 0 . An NMOS transistor NM 14  has a gate connected to the other terminal of the capacitor C 7 , and a drain-source path between the external voltage VDD supply and the other terminal of the capacitor C 8 . A PMOS transistor PM 3  has a gate receiving the pumping control signal P 3  and a source-drain path between the other terminal of the capacitor C 8  and the node B 1 . An NMOS transistor NM 15  has a gate connected to the external voltage VDD supply and a drain-source path between the node B 1  and the node B 2 . An NMOS transistor NM 16  has a gate receiving the pumping control signal P 3  and a drain-source path between the node B 2  and the ground voltage VSS supply. A capacitor C 9  has one terminal connected to the node B 1 . An NMOS transistor NM 17  has a gate connected to the other terminal of the capacitor C 6  and a drain-source path between the external voltage VDD supply and the other terminal of the capacitor C 9 . A PMOS transistor PM 4  has a gate receiving the supply driving control signal TRB and outputs a voltage of the other terminal of the capacitor C 9  as the high voltage VPP.  
         [0089]     An operation of the internal voltage generating circuit in accordance with the first embodiment of the present invention will be described below with reference to FIGS.  10  to  12 .  
         [0090]     First, when the active command ACT is not activated, the pumping control signal generator  100  outputs the pumping control signals P 1 , P 2  and P 3  of a logic high level and the pumping control signal BT 0  of a logic low level in response to the periodic signal OSC. The supply driving controller  300  outputs the supply driving control signal TRB of a logic high level.  
         [0091]     Accordingly, the NMOS transistors NM 14  and NM 17  of the charge pump  200  are turned on by the capacitors C 6  and C 7  receiving the pumping control signals P 1  and P 2 , so that the nodes BT 1  and BT 2  are precharged to the VDD level. The PMOS transistor PM 4  is turned off in response to the supply driving control signal TRB, so that the voltage of the node BT 2  is not outputted as the high voltage VPP.  
         [0092]     When the active command ACT is applied, the pumping control signal generator  100  changes the pumping control signal BT 0  to a logic high level and the pumping control signals P 1 , P 2  and P 3  to a logic low level.  
         [0093]     Thus, the NMOS transistors NM 17  and NM 14  are turned off by the capacitors C 6  and C 7  receiving the pumping control signals P 1  and P 2 , so that the nodes BT 1  and Bt 2  are isolated from the VDD supply.  
         [0094]     The node BT 1  increases to 2VDD by the capacitor C 8  receiving the pumping control signal BT 0 , and the PMOS transistor PM 3  is turned on in response to the pumping control signal P 3 , so that the node B 1  becomes 2VDD equal to that of the node BT 1 .  
         [0095]     Accordingly, the node BT 2  is pumped to 3VDD by the capacitor C 9 , one terminal of which is connected to the node B 1 . The PMOS transistor PM 4  is turned on in response to the activated supply driving control signal TRB, so that 3VDD applied to the node BT 2  is outputted as the high voltage VPP.  
         [0096]     In the case of the internal voltage generating circuit in accordance with the second embodiment of the present invention, if the active command ACT is not applied, the oscillator  400  deactivates the periodic signal OSC to a logic low level. Thus, the pumping control signal generator  500 , the supply driving controller  700 , and the charge pump  600  are deactivated. When the active command ACT is applied, the oscillator  400  activates the periodic signal OSC to a logic high level. Therefore, the charge pump  600  outputs the high voltage VPP by pumping the external voltage VDD in response to the control signals P 1 , P 2 , P 3 , BT 0  and TRB outputted from the activated pumping control signal generator  500  and the activated supply driving controller  700 .  
         [0097]     In the above operation, it is assumed that threshold voltages of the MOS transistors are Vt.  
         [0098]      FIG. 13  is an operational waveform of the internal voltage generating circuit shown in  FIG. 8 .  
         [0099]     Referring to  FIG. 13 , a large of a current is dissipated in a memory region at a time point when a wordline WL is activated by the active command ACT, and a time point when a wordline WL is deactivated by a precharge command PCG.  
         [0100]     As described above, since the high voltage VPP is supplied at the large drivability, the level of the high voltage VPP can be stably maintained.  
         [0101]     Therefore, the internal voltage generating circuit supplies in advance the high voltage at the large drivability when applying the command causing a large current consumption inside the device. Thus, even when the current is substantially consumed by the command, the level of the high voltage can be stably maintained. Unlike the prior art in which the high voltage is supplied after the detection of the level decrease, an amount of a current supply is previously increased before the current is consumed, thus reducing the response time.  
         [0102]     In addition, compared with the prior art, the internal voltage generating circuit in accordance with the present invention occupies a smaller area.  
         [0103]     In the above embodiments, the active command is exemplarily described because the semiconductor memory device using the internal voltage generating circuit consumes a large amount of a current when the active command is applied. That is, other driving signals expected to consume a large amount of a current can be applied instead of the active command. Therefore, the present invention is not limited by the driving signal for driving the internal voltage generating circuit.  
         [0104]     As described above, before a large amount of a current is consumed by the command, an amount of a current supply is increased. Therefore, the response time is reduced to thereby maintain a high voltage stably. In addition, the occupied area can be reduced.  
         [0105]     The present application contains subject matter related to Korean patent application No. 2005-36564, filed in the Korean Intellectual Property Office on Apr. 30, 2005, the entire contents of which is incorporated herein by reference.  
         [0106]     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.