Abstract:
An output circuit comprises first and second transistors connected in series between a first voltage source and an second voltage source such that the first and second transistors are turned on and turned off respectively in response to an input logic signal and a logic inversion thereof, third and fourth transistors connected in series between a third voltage source and fourth voltage source such that the third and fourth transistors are turned on and turned off respectively in response to the logic inversion of the input logic signal and the input logic signal, first and second power transistors connected in series between a fifth voltage source and a sixth voltage source such that the first power transistor is turned on in response to the turning-on of the first transistor and turned off in response to the turning-on of the second transistor, the second power transistor is turned on in response to the turning-on of the third transistor and turned off in response to the turning-on of the fourth transistor, wherein there are provided a first drive control circuit for detecting the turning-on of the second power transistor and disabling the turning-on of the first transistor with a delay such that the turning-on of the first transistor is prohibited for a predetermined interval even after the second power transistor is turned on following a turned off state and a second drive control circuit for detecting the turning-on of the first power transistor and disabling the turning-on of the third transistor with a delay such that the turning-on of the third transistor is prohibited for a predetermined time interval even after the first power transistor is turned on following a turned off state.

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to driver circuits for driving analog devices, and in particular to a high power digital output circuit for producing high power digital signals that drive an analog device such as audio-speaker via a suitable filtering circuit. 
     The use of digital power amplifiers is spreading for example in the audio amplifiers because of the high quality sound obtained from such digital systems. By using the digital power amplifiers, one can eliminate the analog signal processing from the entire audio system except for the final stage for driving the audio speakers. Thereby, an ideal reproduction or processing of the audio signals is achieved without being hampered by the distortion or noise pertinent to the analog audio systems. Such a digital power amplifier is particularly suited for reproducing the audio signals from the digital signal source such as the digital audio disc players or digital tape recorders that produce the output audio signals in the form of digital data. 
     FIG. 1 shows an example of such a digital audio system. 
     Referring to FIG. 1, a digital signal source 1 supplies a digital output signal to a demodulator 3 via an optical fiber cable 2. The demodulator 3 reproduces, in response, a pulse code modulation (PCM) signal that is supplied to a converter 4 for conversion to a pulse width modulation (PWM) signal. The converter 4 produces the foregoing PWM signal and a logic inversion thereof simultaneously in correspondence to the PCM signal supplied thereto, and supplies the same to a digital driver circuit 5 that is the subject matter of the present invention. The digital driver circuit 5, in turn, drives output circuits 6a and 6b each comprising a pair of high power MOS transistors connected in series between a voltage source V CC  and the ground V EE . The output circuits 6a and 6b are driven complementary such that when the circuit 6a produces an output current with a voltage of V CC , the output circuit 6b produces a ground level voltage V EE , and such that when the circuit 6b produces an output current with the voltage of V CC , the output circuit 6a produces the ground level voltage. 
     The output circuits 6a and 6b drive a speaker 8 via respective low pass filters 7a and 7b that smooths the pulse width modulation signals supplied thereto from the output circuits 6a and 6b. Thereby, a high power amplitude modulation signal of which amplitude changes about a level of V CC  /2 is obtained at the speaker 8. 
     FIG. 2 shows the construction of the conventional driver circuit 5 including the MOS output circuits 6a and 6b. 
     Referring to FIG. 2, there are provided drive circuits 1a and 1b respectively connected to input terminals T i1  and T i2  to which a PWM signal D and its logic inversion D are supplied. The drive circuit 1a has an output terminal connected to a base of a bipolar transistor T r3 , while the drive circuit 1b has an output terminal connected to a base of another bipolar transistor T r4 . The transistors Tr 3  and Tr 4  are connected in series between the voltage source V CC  and the ground level V EE  such that the transistor Tr 3  has a collector connected to the voltage source V CC  and an emitter connected to a collector of the transistor Tr 4 . The transistor Tr 4 , on the other hand, has an emitter connected to the ground V EE . Similarly, there are provided drive circuits 1c and 1d respectively connected to input terminals T i3  and T i4  to which the inverted PWM signal D and the non-inverted PWM signal D are supplied respectively, wherein the drive circuit 1c has an output terminal connected to a base of a bipolar transistor Tr 5 , the drive circuit 1d has an output terminal connected to a base of another bipolar transistor Tr 6 . The transistors Tr 5  and Tr 6  are connected in series between the voltage source V CC  and a ground level V EE  such that the transistor Tr 5  has a collector connected to the voltage source V CC  and an emitter connected to a collector of the transistor Tr 6 . On the other hand, the transistor Tr 6  has an emitter connected to the ground V EE . 
     The output circuit 6a or 6b includes power MOS transistors Tr 1  and Tr 2  connected in series between the voltage source V CC  and V EE  such that the MOS transistor Tr 1  has a drain connected to the voltage source V CC , a source connected to the drain of the MOS transistor Tr 2 , while the MOS transistor Tr 2  has a source connected to the ground V EE . Further, the transistor Tr 1  has a gate connected to a node n 1  where the emitter of the bipolar transistor Tr 3  and the collector of the bipolar transistor Tr 4  are connected with each other, the transistor Tr 2  has a gate connected to another node n 2  where the emitter of the transistor Tr 5  and the collector of the transistor Tr 6  are connected with each other. The output of the circuit 6a or 6b is obtained from an output terminal T 0  that is connected to a node n 3  where the source of the transistor Tr 1  is connected to the drain of the transistor Tr 2 . 
     In this conventional driver circuit 5, the transistors Tr 3  and Tr 4  are turned on and turned off in the complementary manner in response to the complementary input signals D and D such that when the transistor Tr 3  is turned on, the transistor Tr 4  is turned off and vice versa. Similarly, the transistors Tr 5  and Tr 6  are turned on and turned off complementary in response to the complementary input signals D and D such that when the transistor Tr 5  is turned on, the transistor Tr 6  is turned off and vice versa. Thus, when the transistor Tr 3  is turned on in response to the high level signal at the input terminal T i1 , the transistor Tr 4  is turned off in response to the low level signal at the input terminal T i2 . Thereby, a high level signal appears at the node n 1  and the MOS transistor Tr 1  is turned on in response thereto. At the same time to the high level signal at the input terminal T i1 , there appear a low level signal at the input terminal T i3  and a high level signal at the input terminal T i4 , and the transistor Tr 5  is turned off while the transistor Tr 6  is turned on. Thereby, a low level signal appears at the node n 2 , and the transistor Tr 2  is turned off in response thereto. Thus, a large output current is obtained at the output terminal T 0  When the logic state of the signals at the input terminals T i1  -T i4  is inverted, on the other hand, the transistor Tr 3  is turned off, the transistor Tr 4  is turned on, the transistor Tr 5  is turned on, and the transistor Tr 6  is turned off. As a result, the transistor Tr 1  is turned off and the transistor Tr 2  is turned on. Thereby, the output terminal T 0  is grounded and no output current obtained therefrom. By smoothing the PWM output current at the output terminal T 0  by the filtering circuits, one obtains the desired output current. 
     In this conventional driver circuit 5, there exists a problem in that, when the gate voltage of the transistors Tr 1  and Tr 2  is inverted, there may appear a situation where both of the transistors Tr 1  and Tr 2  are turned on momentarily, depending on the characteristic of the transistors Tr 1  and Tr 2 . When this occurs, a feed-through current flows from the voltage source V CC  to the ground, and such a feed-through current causes a distortion in the reproduced audio signal and increases the power consumption of the amplifier. The distortion in the reproduced audio signal of course deteriorates the quality of the reproduced sound while the problem of increased power consumption causes a serious problem in the battery driven systems such as a portable audio system. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide a novel and useful digital driver circuit wherein the foregoing problems are eliminated. 
     Another and more specific object of the present invention is to provide a digital driver circuit for driving an analog device by an analog output signal in response to a digital input signal with a large output power, wherein the distortion in the obtained analog signal is eliminated. 
     Another object of the present invention is to provide a digital driver circuit for driving an analog device in response to a digital input signal, wherein the power consumption is improved. 
     Another object of the present invention is to provide a driver circuit for producing a digital power output, comprising first and second power MOS transistors connected in series between first and second voltage sources for producing a digital power output at an output terminal connected to an intermediate node between the first and second power MOS transistors, first and second bipolar transistors connected in series between third and fourth voltage sources with an intermediate node connected to the gate of the first power MOS transistor for driving the same, third and fourth bipolar transistors connected in series between fifth and sixth voltage sources with an intermediate node connected to the gate of the second power MOS transistor for driving the same, a first driver circuit supplied with an input digital data for driving the first bipolar transistor, a second driver circuit supplied with a logic inversion of the input digital data for driving the second bipolar transistor, a third driver circuit supplied with the logic inversion of the input digital data for driving the third bipolar transistor, a fourth driver circuit supplied with the input digital data for driving the fourth bipolar transistor, a first control transistor for disabling the first bipolar transistor selectively in response to an input signal to the fourth bipolar transistor, a second IU control transistor for disabling the third bipolar transistor selectively in response to an input signal to the second bipolar transistor, a first delay circuit for delaying the input signal to the first control transistor, and a second delay circuit for delaying the input signal to the second control transistor. According to the present invention, the simultaneous turning-on of the first and second power MOS transistors is eliminated by disabling the first or third bipolar &amp;transistors with a timing such that the first bipolar transistor remains disabled for a while even when the first driver circuit tries to enable the first bipolar transistor in response to the input data thereto, or such that the third bipolar transistor remains disabled for a while even when the third driver circuit tries to enable the third bipolar transistor in response to the input data thereto. More specifically, there appears a delay when the first and second power MOS transistors are turned on. It should be noted that the first power MOS transistor is turned on by the first bipolar transistor and turned off by the second bipolar transistor. Similarly, the second power MOS transistor is turned on by the third bipolar transistor and turned off by the fourth bipolar transistor. Thereby, the problem of feed-through current flowing through the first and second power MOS transistors is eliminated and the power consumption of the digital driver circuit is improved. 
     Another object of the present invention is to provide a digital driver circuit for producing a digital power output, comprising first and second power MOS transistors connected in series between first and second voltage sources for producing a digital power output at an output terminal connected to an intermediate node between the first and second power MOS transistors, first and second bipolar transistors connected in series between third and fourth voltage sources with an intermediate node connected to the gate of the first power MOS transistor for driving the same, third and fourth bipolar transistors connected in series between fifth and sixth voltage sources with an intermediate node connected to the gate of the second power MOS transistor for driving the same, a first driver circuit supplied with an input digital data for driving the first bipolar transistor, a second driver circuit supplied with a logic inversion of the input digital data for driving the second bipolar transistor, a third driver circuit supplied with the logic inversion of the input digital data for driving the third bipolar transistor, a fourth driver circuit supplied with the input digital data for driving the fourth bipolar transistor, a first control transistor supplied with the gate voltage of the second power MOS transistor as an input signal for disabling the first bipolar transistor selectively in response thereto, a second control transistor supplied with the gate voltage of the first power MOS transistor as an input signal for disabling the third bipolar transistor selectively in response thereto, wherein the threshold voltages of the first and second control transistors are set lower than the threshold voltage of the first and second power MOS transistors such that the first bipolar transistor is disabled before the second power MOS transistor is turned on, and such that the third bipolar transistor is disabled before the first power MOS transistor is turned on. According to the present invention, the simultaneous turning-on of the first and second power MOS transistors is avoided similarly, and the problem of excessive power consumption of the driver circuit is eliminated. 
     Other object and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the construction of a digital audio system to which the present invention is applicable; 
     FIG. 2 is a block diagram showing a conventional digital driver circuit that is used in the audio system of FIG. 1; 
     FIG. 3 is a block diagram showing the principle of the present invention according to a first embodiment; 
     FIG. 4 is another block diagram showing the principle of the present invention according to a second embodiment; 
     FIG. 5 is a detailed circuit diagram showing the driver circuit according to the first embodiment of the present invention; 
     FIGS. 6(A)-6(J) are diagrams showing the timing of operation of various transistors in the circuit of FIG. 5; 
     FIG. 7 is a circuit diagram showing a modification of the first embodiment; 
     FIG. 8 is a detailed circuit diagram showing the driver circuit according to the second embodiment of the present invention; 
     FIGS. 9(A)-9(D) are diagrams showing the timing of operation of various transistors in the circuit of FIG. 8; and 
     FIG. 10 is a modification of the circuit of FIG. 8. 
    
    
     DETAILED DESCRIPTION 
     First, the principle of the present invention will be described with reference to FIGS. 3 and 4, wherein FIG. 3 shows the principle for the first embodiment and FIG. 4 shows the principle for the second embodiment. 
     Referring to FIG. 3 showing the construction that is substantially identical with the construction of FIG. 2, there is provided a first control transistor TC 1  that absorbs the base current to the transistor Tr 3  when activated. This first control transistor TC 1  has a collector connected to the base of the transistor Tr 3  and an emitter connected to the ground V EE . The transistor TC 1  further has a base connected to the base of the bipolar transistor Tr 6  via a first inverter circuit 12a. Thereby, the transistor TC 1  is driven in response to the base voltage of the transistor Tr 6  with a delay caused by the inverter circuit 12a. When turned on, the transistor TC 1  turns off the transistor Tr 3  even when the drive circuit 11a has produced an output current for turning on the transistor Tr 3 . Similarly, there is provided a second control transistor TC 2  such that the transistor TC 2  has a collector connected to the base of the transistor Tr 5  and an emitter connected to the ground V EE . The transistor TC 2  further has a base connected to the base of the transistor Tr 4  via a second inverter circuit 12b and is activated in response to the base voltage of the transistor Tr 4  with a delay caused by the circuit 12b. Thereby, when the transistor Tr 4  is turned on in response to the output of the drive circuit 11b, the transistor TC 2  disables the transistor Tr 5  after a delay caused by the inverter circuit 12b. 
     For example, when the logic level of the input data D changes from the high level to the low level, the level of the input signal supplied to the input terminals T i1  and T i4  changes from the high level to the low level and the level of the input signal supplied to the input terminals T i2  and T i3  changes from the low level to the high level. In response thereto, the drive circuits 11a and 11d produce the high level signal while the drive circuits 11b and 11c produce the low level signal. In response to the low level output of the drive circuit 11b, the transistor Tr 4  is immediately turned off. Similarly, the transistor Tr 2  is turned off in response thereto. 
     On the other hand, the base voltage of the transistor TC 1  remains high even after the logic level of the input signals to the input terminals T i1  -T i4  has changed, because of the delay caused by the inverter 12a. Thereby, the transistor TC 1  remains turned on for a while and then turned off. During the interval wherein the transistor TC 1  is turned on, the transistor Tr 3  is turned off because of the diverting of the base current to the ground via the transistor TC 1 . Thus, the voltage at the node n 1  is held low during this interval and the power MOS transistor Tr 1  remains in the turned off state. Only when the transistor TC 1  is turned off after the foregoing interval has elapsed, the transistor Tr 3  is turned on and the power MOS transistor Tr 1  is turned on. 
     Similarly, the base voltage of the transistor TC 2  remains low for a while even after the foregoing transition has occurred in the input signals to the input terminals T i1  -T i4 . Only when the interval corresponding to the delay that is caused by the inverter circuit 12b has elapsed, the transistor TC 2  is turned off. Thereby, the transistor TC 2  is turned off and then turned on. However, this operation of the transistor TC 2  does not cause substantial change in the operation of the circuit 10, as the transistor Tr 5  is turned off in response to the low level input at the input terminal T i3 . Thus, the voltage level at the node n 2  is held at the low level throughout the interval in which the level at the input terminal T i3  is low, and the power MOS transistor Tr 2  is turned off. 
     In the foregoing operation, it will be noted that there appears a moment in which both the transistors Tr 1  and Tr 2  are turned off before the transistor Tr 1  is turned on and the output current obtained from the output terminal T 0 . Thereby, the waste current flowing from the voltage source V CC  to the ground V EE  is positively prevented. 
     The above operation holds true also for the case where the level at the input terminals T i1  and T 14  changes from the high level to the low level and the level at the input terminals T i2  and T i3  changes from the low level to the high level. As the operation for this case is easily derived from the foregoing explanation, further description will be omitted. 
     FIG. 4 shows the principle of the second embodiment of which description will be made later in detail. 
     In this embodiment, the voltage at the node n 1  is detected by a control transistor TC 4  that has a collector connected to the base of the transistor Tr 5  and an emitter connected to the ground. More specifically, there is provided a voltage divider DIV1 connected across the node n 1  and the ground, and the transistor TC 4  has a base connected to a node of the voltage divider DIV1 wherein a resistor Rx and a resistor Ry are connected with each other. Similarly, there is provided another control transistor TC 3  having a collector connected to the base of the transistor Tr 3  and an emitter connected to the ground. The transistor TC 3  further has a base connected to a voltage divider DIV2 that is connected across a node n 2  and the ground. More specifically, the voltage divider DIV2 includes resistors Rx&#39; and Ry&#39; that are connected in series between the node n 2  and the ground, and the base of the transistor TC 3  is connected to a node in the voltage divider DIV2 wherein the resistors Rx&#39; and Ry&#39; are connected with each other. 
     The transistor TC 3  has a threshold level that is substantially smaller than the threshold level of the power MOS transistor Tr 2  and the transistor TC 4  has a threshold level that is substantially smaller than the threshold level of the power MOS transistor Tr 1 . Thereby, the transistor TC 3  is turned on when the power MOS transistor Tr 2  is turned on with a timing such that the transistor TC 3  is turned on before the transistor Tr 2  is turned on. Similarly, when the power transistor Tr 1  is turned on, the transistor TC 4  is turned on before the transistor Tr 1  is actually turned on. In response to the turning on of the transistor TC 3 , the transistor Tr 3  is turned off and the power MOS transistor Tr 1  is turned off before the power MOS transistor Tr 2  is turned on. Similarly, in response to the turning on of the transistor TC 4 , the transistor Tr 5  is turned off and the power MOS transistor Tr 2  is turned off before the power MOS transistor Tr 1  is turned on. Thereby, the simultaneous turning on of the power MOS transistors Tr 1  and Tr 2  is positively prevented and the waste current flowing from the voltage source V CC  to the ground is effectively eliminated. 
     Next, the first embodiment of the present invention will be described in detail with reference to FIG. 5. 
     Referring to FIG. 5, the drive circuit now represented as a circuit 10 includes a first drive part 2a for driving the power MOS transistor Tr 1  and a second drive part 2b for driving the power MOS transistor Tr 2 . In the first drive part 2a, an input signal D at the input terminal T i1  is supplied to a base of an NPN transistor Tr 11  that has a collector connected to the voltage source V CC  via a constant current source 3a and an emitter connected to the ground V EE . The transistor Tr 11  drives the transistor Tr 3  via an NPN transistor Tr 12  that forms a Darlington&#39;s pair with the transistor Tr 3 . There, the transistor Tr 12  has a base connected to the collector of the transistor Tr 11 , a collector connected to the voltage source V CC  and an emitter connected to a base of the transistor Tr 3 . Further, there is provided a diode D to connect the emitter and the base of the transistor Tr 12 , with the anode terminal connected to the emitter of the transistor Tr 12  and the cathode terminal connected to the base of the transistor Tr 12 . 
     Similarly, there is provided an NPN transistor Tr 13  having a base connected to an input terminal T i2  via a resistor R 2  for receiving the input signal D, a collector connected to the voltage source V CC  via a constant current source 3b, and an emitter connected to the ground. The transistor Tr 13  drives the transistor Tr 4  via an NPN transistor Tr 15  that forms a Darlington&#39;s connection with the transistor Tr 4 . Thus, the transistor Tr 15  has a collector connected to the collector of the transistor Tr 4 , an emitter connected to the base of the transistor Tr 4  and a base connected to the collector of the transistor Tr 13 . Further, the collector of the transistor Tr 15  is connected to the emitter of the transistor Tr 12  via a resistor R1 and the emitter of the transistor Tr 15  is connected to the ground via a resistor R5. In addition to the drive transistor Tr 13 , there is provided another drive transistor Tr 14  that has a base connected to the input terminal T i2  via a resistor R3, a collector connected to the base of the transistor Tr 4  and an emitter connected to the ground V EE . 
     A similar construction is provided for the drive part 2b, wherein transistors Tr 21  -Tr 25  are provided in correspondence to the transistors Tr 11  -Tr 15 , respectively. 
     Thus, the second drive part 2b includes an NPN transistor Tr 21  having a base connected to the input terminal T i3  for receiving the input signal D a collector connected to the voltage source V CC  via a constant current source 3a and an emitter connected to the ground V EE . The transistor Tr 21  drives the transistor Tr 5  via an NPN transistor Tr 22  that forms a Darlington&#39;s pair with the transistor Tr 5 . There, the transistor Tr 22  has a base connected to the collector of the transistor Tr 21 , a collector connected to the voltage source V CC  and an emitter connected to a base of the transistor Tr 5 . Further, there is provided a diode D to connect the emitter and the base of the transistor Tr 22 , with the anode terminal connected to the emitter of the transistor Tr 22  and the cathode terminal connected to the base of the transistor Tr 22 . 
     Similarly, there is provided an NPN transistor Tr 23  having a base connected to an input terminal T i4  via a resistor R7 for receiving the input signal D, a collector connected to the voltage source V CC  via a constant current source 3b, and an emitter connected to the ground. The transistor Tr 23  drives the transistor Tr 6  via an NPN transistor Tr 25  that forms a Darlington&#39;s connection with the transistor Tr 6 . Thus, the transistor Tr 25  has a collector connected to the collector of the transistor Tr 6 , an emitter connected to the base of the transistor Tr 6  and a base connected to the collector of the transistor Tr 23 . Further, the collector of the transistor Tr 25  is connected to the emitter of the transistor Tr 22  via a resistor R6 and the emitter of the transistor Tr 25  is connected to the ground via a resistor R9. In addition to the drive transistor Tr 23 , there is provided another drive transistor Tr 24  that has a base connected to the input terminal t i4  via a resistor R8, a collector connected to the base of the transistor Tr 6  and an emitter connected to the ground V EE . 
     In order to achieve the object of the present invention and avoid the simultaneous turning on of the power MOS transistors Tr 1  and Tr 2 , there is provided a bipolar transistor Tr 18  having a base connected to the base of the transistor Tr 15  via a resistor R4. The transistor Tr 18  further has a collector connected to the voltage source V CC  via a constant current source 3c and an emitter connected to the ground. Thereby, the transistor Tr 18  is turned on in response to the base voltage of the transistor Tr 15 , and the level of the collector of the transistor Tr 18  is lowered with a delay pertinent to the operation of the transistor Tr 18 . The transistor Tr 18  in turn drives another NPN transistor Tr 17  that has a base connected to the collector of the transistor Tr 18 , a collector connected to the base of the transistor Tr 22  and an emitter connected to the ground. Thereby, the transistor Tr 17  is turned off when the transistor Tr 18  is turned on and turned on when the transistor Tr 18  is turned off. When turned on, the transistor Tr 17  absorbs the base current of the transistors Tr 22  and Tr 5  either directly or via the diode D, and the transistors Tr 22  and Tr 5  are both turned off irrespective of whether the voltage level at the collector of the transistor Tr 21  is high or not. 
     Similarly, the drive part 2b includes a bipolar transistor Tr 28  having a base connected to the base of the transistor Tr 25  via a resistor R10. The transistor Tr 28  further has a collector connected to the voltage source V CC  via a constant current source 3c&#39; and an emitter connected to the ground. Thereby, the transistor Tr 28  is turned on in response to the base voltage of the transistor Tr 25 , and the level of the collector of the transistor Tr 28  is lowered with a delay pertinent to the operation of the transistor Tr 28 . The transistor Tr 28  in turn drives another NPN transistor Tr 27  that has a base connected to the collector of the transistor Tr 28 , a collector connected to the base of the transistor Tr 12  and an emitter connected to the ground. Thereby, the transistor Tr 27  is turned off when the transistor Tr 26  is turned on and turned on when the transistor Tr 26  is turned off. When turned on, the transistor Tr 27  absorbs the base current of the transistors Tr 12  and Tr 3  either directly or via the diode D, and the transistors Tr 12  and Tr 3  are both turned off irrespective of whether the voltage level at the collector of the transistor Tr 11  is high or not. 
     FIGS. 6(A)-6(J) show the timing of the foregoing operation for various parts of the circuit 10, wherein FIG. 6(A) shows the input data D supplied to the input terminals T i1  and T i4  while FIG. 6(B) shows the input data D supplied to the input terminals T i2  and T i3  FIG. 6(C). on the other hand shows the timing of turning-off and turning-on of the transistors Tr 25  and Tr 6  caused in response to the signal D at the input terminal T i4 . As can be seen in FIG. 6(C), the turning-off and turning-on of the transistors Tr 25  and Tr 6  occur substantially coincident to the rising edge and the falling edge of the input signal D, respectively. 
     FIG. 6(D), on the other hand, shows the timing of the turning-on and turning-off of the transistor Tr 27  that are caused in response to the base voltage of the transistor Tr 25 . As will be noted in FIG. 6(D), there appears a delay in the turning-on and turning-off of the transistor Tr 27 , and such a delay is caused by the delay in the operation of the transistor Tr 28  that detects the base voltage of the transistor Tr 25  and drives the transistor Tr 27 . When the input signal D has returned to the low level in corresponding to the trailing edge of the waveform of FIG. 6(A), the transistor Tr 23  is turned off and the voltage level at the collector of the transistor Tr 23  becomes high. In response thereto, the transistor Tr 28  is turned on and the transistor Tr 27  is turned off after a delay as shown in FIG. 6(D). 
     As the transistor Tr 27  diverts the base current of the transistors Tr 12  and Tr 3  to the ground when turned on, the transistors Tr 12  and Tr 3 , being turned off in response to the high level state of the input signal D, remains in the turned-off state for a while as shown in FIG. 6(E), even when the input signal D has returned to the low level state at the trailing 10 edge of FIG. 6(A). Thereby, the turning-on of the power MOS transistor Tr 1  does not occur until the transistors Tr 12  and Tr 3  are turned on in response to the turning-off of the transistor Tr 27  as shown in FIG. 6(F). It should be noted that the transistor Tr 1  is turned off immediately in response to the rising edge of the input signal D of FIG. 6(A) in coincidence with the falling edge of the input signal D as shown in FIG. 6(F) under the control of the transistors Tr 13  -Tr 15  and the transistor Tr 4 . 
     FIG. 6(G) shows the state of the transistors Tr 15  and Tr 4 . As can be seen, the turning-on and turning-off of these transistors occur substantially in synchronization with the input signals D and D of FIGS. 6(A) and 6(B). FIG. 6(H), on the other hand, shows operation of the transistor Tr 17  that is caused in response to the base voltage of the transistor Tr 15 . As can be seen in FIG. 6(H), there appears a delay in the operation of the transistor Tr 17  with respect to the signals D and D of FIGS. 6(A) and 6(B) due to the delay in the operation of the transistor Tr 16  that actually drives the transistor Tr 17 . 
     FIG. 6(I) shows the operation of the transistors Tr 22  and Tr 5  that is caused in response to the input signal D at the input terminal T i3  As shown in FIG. 6(I), the transistors Tr 22  and Tr 5  are held in the turned-off state as long as the transistor Tr 17  is turned on. First when the transistor Tr 17  is turned off, the transistors Tr 22  and Tr 5  are turned on, and turned off subsequently in response to the rising edge of the signal D of FIG. 6(B). In response to the operation of the transistors Tr 22  and Tr 5 , the power MOS transistor Tr 2  is turned on and turned off as shown in FIG. 6(J). By comparing FIG. 6(F) showing the operation of the power MOS transistor Tr 1  and FIG. 6(J) showing the operation of the power MOS transistor Tr 2 , one can see that there appears an interval wherein both the transistors Tr 1  and Tr 2  are turned off in correspondence to the delay caused by the transistors Tr 18  and Tr 28 , and the simultaneous turning on of the power MOS transistors Tr 1  and Tr 2  is eliminated as explained with reference to FIG. 3. 
     FIG. 7 shows a modification of the circuit of FIG. 5 wherein the feed-through current within the drive parts 2a and 2b is eliminated. 
     In the modification of FIG. 7, there is provided an NPN transistor Trx between the base of the transistor Tr 12  and the ground for absorbing the base current when turned on. The transistor Trx has a base connected to the base of the transistor Tr 15  and driven in response to the base voltage of the transistor Tr 15 . In other words, the transistor Trx is turned on when transistor Tr 15  is turned on. Thus, in response to the turning on of the transistor Tr 15 , the transistor Trx absorbs the base current of the transistor Tr 12  and hence the base current of the transistor Tr 3  and the simultaneous turning-on of the transistors Tr 12  and Tr 15  is positively eliminated. Thereby, the feed-through current through the transistors Tr 12  and Tr 15  is eliminated and the power consumption of the system is further improved. 
     FIG. 8 shows the detailed circuit diagram for the second embodiment corresponding to FIG. 4. 
     In this circuit, the gate voltage of the MOS transistor Tr 1  is detected by an NPN transistor Tr 31   via a voltage divider circuit that includes a series connection of resistors R 31  and R 32 . The transistor Tr 31  has a collector connected to the base of the transistor Tr 22  and an emitter connected to the ground. Thus, in response to the increase in the gate voltage of the MOS transistor Tr 1  that causes the MOS transistor Tr 1  to turn on, the transistor Tr 31  is turned on and turns off the transistors Tr 22  and Tr 5 , and hence the power MOS transistor Tr 2 . Similarly, there is provided an NPN transistor Tr 32  that detects the gate voltage of the MOS transistor Tr 2  via a voltage divider circuit that includes a series connection of resistors R 33  and R 34 . The transistor Tr 32  has a collector connected to the base of the transistor Tr 12  and an emitter connected to the ground and turns off the transistors Tr 12  and Tr 3  and hence the transistor Tr 1  in response to the increased gate voltage of the transistor Tr 2 . 
     FIGS. 9(A)-9(D) show the timing of operation of the circuit of FIG. 8, wherein FIG. 9(A) shows the transition of the gate voltage of the power MOS transistor Tr 1  detected at a node TOa while FIG. 9(C) shows the transition of the gate voltage of the power MOS transistor Tr 2  detected at a node TOb. In FIG. 9(A), the threshold level for the turning-on and turning-off of the power MOS transistor Tr 1  is represented by VTHA. Similarly, the threshold level of the power MOS transistor Tr 2  is represented in FIG. 9(C) by VTHB 
     There, the threshold level for the operation of the transistor Tr 31  is set lower than the threshold level of the MOS transistor Tr 1  as shown in FIG. 9(A) by a line V ra . Similarly, the threshold level for the operation of the transistor Tr 32  is set lower than the threshold level of the MOS transistor Tr 2  as shown in FIG. 9(C) by a line V rb . Thereby, the transistor Tr 31  is turned on with the transition of the voltage level at the node TOa from the low level (V EE  ) to the high level (V CC ) before the transistor Tr 1  is turned on, as shown by the rising edge of the waveform of FIG. 9(B) that shows the operation of the transistor Tr 3l . Similarly, when the voltage level at the node TOb increases from the low level (V EE ) to the high level (V CC ), the transistor Tr 32  is turned on first as shown by the rising edge of FIG. 9(D) showing the operation of the transistor Tr 32 , and the turning-on of the power MOS transistor Tr 2  occurs after the transistor Tr 32  has turned on. 
     As long as the transistor Tr 32  is turned on, the turning-on of the power MOS transistor Tr 1  is prohibited. Thus, the transistor Tr 1  is turned off by the transistor Tr 32  before the transistor Tr 2  is turned on. Similarly, as long as the transistor Tr 31  is turned on, the turning-on of the power MOS transistor Tr 2  is prohibited. Thus, the transistor Tr 2  is turned off by the transistor Tr 31  before the transistor Tr 1  is turned on. Thereby, the simultaneous turning-on of the power MOS transistors Tr 1  and Tr 2 , that may occur in the actual circuit due to the variation in the circuit constants or threshold of the transistors, is positively prevented, and the problem of waste current flowing through the transistors Tr 1  and Tr 2  is eliminated. 
     FIG. 10 shows a modification of the circuit of FIG. 8 for eliminating the feed-through current in the drive parts 2a and 2b. In this circuit, too, the NPN transistor Trx is provided similar to the circuit of FIG. 7. Thereby, one can improve the power consumption of the output circuit further, although the effect of the improvement appears more significant by preventing the simultaneous turning-on of the power MOS transistors Tr 1  and Tr 2  as set forth in the first and second embodiments. 
     By using the output circuit of any of FIGS. 5, 7, 8 and 9, one can reduce the power consumption of the digital audio system of FIG. 1 and improve the quality of the sound obtained form the system. Further, the application of the present output circuit is by no means limited to the digital audio systems. For example, the present invention may be used for driving electric motors or electromagnetic actuators with the similar preferable effect of reduced power consumption. 
     Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention.