Abstract:
A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling.  
           [0003]    2. Description of the Related Art  
           [0004]    As is known, integration of electronic devices in a single wafer of semiconductor material requires particular solutions in order to decrease the effects of electromagnetic coupling due to the capacitances and mutual parasitic inductances that may form between the regions in which the active and/or passive components and the substrate of the wafer are made. These capacitances and mutual parasitic inductances, in fact, alter the characteristics of the devices and lead to an increase in the overall power dissipation. In addition, the problem of electromagnetic coupling with the substrate is particularly significant in the case of pure passive components, i.e., of those components that are designed to have a behavior of an exclusively capacitive, inductive, or resistive type in a wide frequency band.  
           [0005]    The solutions so far proposed envisage the use of dielectric passivation layers which separate the regions comprising the components from the substrate. However, the fabrication processes currently available present limits which, in practice, do not enable formation of dielectric layers having satisfactory characteristics of insulation.  
           [0006]    One first solution, for example, lies in growing a thermal-oxide layer of a thickness of a few micron on a surface of the wafer. In this case, however, the time required for carrying out the oxidation step is extremely long, on account of the low diffusiveness of the reagents, and the process is too slow to be exploited at an industrial level. Alternatively, it has been proposed to use thick layers of deposited oxide, which can be made in slightly shorter times. However, the improvement that is obtained is not yet sufficient and, moreover, the dielectric characteristics of the deposited oxide are inferior to those of the thermal oxide.  
           [0007]    According to a different solution, silicon-on-insulator (SOI) semiconductor wafers are used, namely wafers incorporating a layer of buried oxide which separates the substrate from a monocrystalline- or polycrystalline-silicon region in which the components are formed. SOI wafers first of all present the disadvantage of being very costly, in so far as their preparation requires the use of complex processes; in the second place, the buried-oxide layers of SOI wafers currently available are not sufficiently thick to guarantee adequate electromagnetic insulation between the substrate and the components.  
           [0008]    A further solution involves the fabrication of dielectric layers made of polymeric material. In this way, it is possible to reach even very high thicknesses and ones that are sufficient for reducing electromagnetic coupling considerably. In addition, it is possible to make passive devices suspended over the substrate (the so-called “air-bridge” devices), with the aim, above all, of minimizing the parasitic couplings of a capacitive type. The fabrication of thick polymeric layers is, however, disadvantageous because it requires the use of technologies and processing steps that are not standard in the sector of micro-electronics. Also in this case, then, the production cost of the device is very high. In addition, air-bridge devices cannot be passivated, entail the use of cavity packagings and are far from easy to reproduce.  
           [0009]    The problem of electromagnetic coupling, then, afflicts particularly the inductors, so much so that they are not normally integrated on semiconductor wafers. In fact, precisely on account of the electromagnetic coupling between the turns and the substrate, at present it is not possible to produce inductors with a high figure of merit. On the other hand, recourse to alternative solutions, such as the use of highly resistive substrates, the formation of cavities that underlie the inductors, or recourse to techniques of three-dimensional lithography has the drawbacks already described (non-standard technologies or technologies that are not compatible with the fabrication of integrated circuits, high costs, packaging, etc.).  
         BRIEF SUMMARY OF THE INVENTION  
         [0010]    An embodiment of the present invention provides a process for manufacturing a semiconductor wafer that will produce integrated electronic devices with improved electromagnetic decoupling.  
           [0011]    According to an embodiment of the present invention provides a process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling. The process for manufacturing a integrated electronic component and a structure for electromagnetic decoupling in a semiconductor substrate region of a wafer. The process includes the steps of forming a plurality of first mutually adjacent trenches in the semiconductor substrate region. The plurality of adjacent trenches are open on a first face of the wafer and have a depth and a width to define walls of the trench. The walls of the trenches are oxidized to partially fill the trenches so as to form an insulating structure of a dielectric material. The insulating structure is structured to extend through the wafer and be exposed to both the top and bottom surfaces of the wafer by removing a portion of the semiconductor substrate of the wafer between the insulating structure and bottom of the wafer.  
           [0012]    The resulting circuit structure provides for electrically and magnetically separated regions on the top surface of the wafer for forming integrated circuits, high power components or passive components. Alternatively, integrated circuits can be formed on the top surface in either insulating structure or the semiconductor substrate region and on the bottom surface of the wafer. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)  
       [0013]    For a better understanding of the present invention, some embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, in which:  
         [0014]    [0014]FIG. 1 is a cross-sectional view of a wafer of semiconductor material, in an initial fabrication step according to a first embodiment of the present invention;  
         [0015]    [0015]FIG. 2 is a top plan view of the wafer of FIG. 1 in a subsequent fabrication step;  
         [0016]    [0016]FIG. 3 is a cross-sectional view of the wafer of FIG. 2 according to a plane of trace III-III;  
         [0017]    [0017]FIG. 4 is the same view as FIG. 3, in a subsequent step of fabrication of the wafer;  
         [0018]    [0018]FIG. 5 is a top plan view of the wafer of FIG. 4;  
         [0019]    [0019]FIG. 6 is the same view as FIG. 4, in a subsequent step of fabrication of the wafer;  
         [0020]    [0020]FIG. 7 is a top plan view of the wafer of FIG. 6;  
         [0021]    FIGS.  8 - 11  show the same view as FIG. 6, in successive steps of fabrication of the wafer;  
         [0022]    [0022]FIG. 12 is a top plan view of the wafer of FIG. 11;  
         [0023]    [0023]FIG. 13 is the same view as FIG. 11, in a subsequent step of fabrication of the wafer;  
         [0024]    [0024]FIG. 14 is a top plan view of a wafer of semiconductor material, in an initial fabrication step, in a second embodiment of the present invention;  
         [0025]    [0025]FIG. 15 is a cross-sectional view of the wafer of FIG. 14 according to a plane of trace XV-XV;  
         [0026]    [0026]FIG. 16 shows the same view as FIG. 15, in a subsequent step of fabrication of the wafer;  
         [0027]    [0027]FIG. 17 is a top plan view of the wafer of FIG. 16;  
         [0028]    FIGS.  18 - 20  show the same view as FIG. 16, in subsequent steps of fabrication of the wafer; and  
         [0029]    FIGS.  21 - 23  are cross-sectional views of a wafer of semiconductor material in successive fabrication steps, in a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]    In the embodiment described hereinafter, the process that forms the subject of the present invention is used for the fabrication of an inductor with a high figure of merit. This must not, however, be considered in any way limiting, since the process can be advantageously used for the fabrication of devices of various kinds, whether active or passive.  
         [0031]    With reference to FIGS.  1 - 13 , a wafer  1  of semiconductor material, such as monocrystalline silicon, comprises a substrate  2  having a doping density of, for example, 10 19  atoms/cm 3 .  
         [0032]    Initially, a deep trench etch is performed. For this purpose, an oxide layer is deposited on a first face  4  of the wafer  1  and is then defined by means of a photolithographic process, so as to form a trench mask  5 , which leaves partially uncovered a region  7  in which an insulating region will have to be subsequently formed (FIG. 1). Next (FIGS. 2 and 3), the regions  7  of the wafer  1  that have been left uncovered by the trench mask  5  are etched anisotropically as far as a pre-set depth D (for example, 100 μm), preferably by means of plasma etching. The trench mask  5  is then removed. In greater detail, in this step a plurality of mutually adjacent rectilinear trenches  9  having a depth D and a width W of, for instance, 2.5 μm are formed. The rectilinear trenches  9  are open on a first face  4  of the wafer  1 , extend parallel to one another, and define, in pairs, walls  8  that are set alongside one another and have a thickness S equal to the width W, so as to form a grid  10 , which preferably has, in plan view, a rectangular or square envelope. In addition, the walls  8  and the rectilinear trenches  9  extend without any interruption between the opposite sides of the grid  10 , except for an edge portion  10   a  and a central portion  10   b  of the grid  10  as shown in FIG. 2. In particular, during the trench-etching step, a first annular trench  11  and a second annular trench  12 , which also have a width W and a depth D, are opened in the edge portion  10   a  and in the central portion  10   b , respectively, of the grid  10 . The first annular trench  11  and the second annular trench  12  internally delimit a first conductive region  14  and a second conductive region  15 , respectively, which are continuous and have a diameter of, for example, 80 μm. In addition, the first annular trench  11  and second annular trench  12  interrupt the walls  8  and the rectilinear trenches  9  formed in the edge portion  10   a  and in the central portion  10   b  of the grid  10 .  
         [0033]    Next (FIGS. 4 and 5), a thermal-oxidation step is carried out, in which the walls  8  are completely oxidized. Since the thermal oxide grows substantially for one half inside the silicon and for one half outwards, and since, moreover, the width W of the trenches  9 ,  11 ,  12  is equal to the thickness S of the walls  8 , in this step the rectilinear trenches  9  and the annular trenches  11 ,  12  are completely filled with silicon dioxide. During the thermal-oxidation step, also a superficial oxide layer is formed, which is subsequently removed, so as to uncover the first face  4  of the wafer  1  and, in particular, the first conductive region  14  and second conductive region  15 . In this way, inside the wafer  1  there is formed a silicon-dioxide insulating structure  17  having a substantially parallel-pipedal shape. In particular, the insulating structure  17  has a height equal to the depth D of the trenches  9 ,  11 ,  12  and, in plan view, has a shape which substantially coincides with the envelope of the grid  10 . In addition, the insulating structure  17  is traversed, in a direction orthogonal to the first face  4 , by the first conductive region  14  and second conductive region  15 , which form respective through conductive vias.  
         [0034]    Using standard processing steps, in a way known to a person skilled in the art, integrated circuits  18 , here schematically represented by active and passive components as shown in FIG. 6, are then formed in the substrate  2 , in the proximity of the face  4 .  
         [0035]    Next, a germ  21  of conductive material, for instance copper, is deposited on the first face  4  of the wafer  1 , so as to coat it completely for a thickness of approximately 100-200 nm and to set in contact the first conductive region  14  and the second conductive region  15  (FIG. 6). Then a resist layer is deposited on the germ layer  21  and is defined so as to form a matrix  24  having a spiral-shaped opening  25 . In particular, the opening  25  forms a predetermined number of turns and has an outer end  25   a , in a position corresponding to the first conductive region  14 , and an inner end  25   b , in a position corresponding to the second conductive region  15  (FIG. 7).  
         [0036]    Next, a copper inductor  26  is galvanically grown inside the opening  25 , in contact with uncovered portions  21 ′ of the germ layer  21  (FIG. 8). Preferably, a cross section of the inductor  26  has a first dimension L 1 , which is perpendicular to the first face  4  of the wafer  1 , greater than a second dimension L 2 , which is parallel to the first face  4 .  
         [0037]    The matrix  24  is then removed, and portions  21 ″ of the germ layer  21  that are not covered by the inductor  26  are selectively removed, as shown in FIG. 9. Preferably, a dry etch is carried out in this step, since it is easier to control and less sensitive to possible variations in the etching time.  
         [0038]    At the end of this step, the wafer  1  comprises the monocrystalline-silicon substrate  2 , the insulating structure  17 , formed inside the substrate  2  and surfacing on the first face  4 , the integrated circuits  18 , and the inductor  26 .  
         [0039]    Next, the wafer  1  is turned upside down (FIG. 10), and a first portion  2 ′ of the substrate  2 , which is comprised between the insulating structure  17  and a second face  20  of the wafer  1  set opposite to the first face  4 , is completely removed by milling. At the end of this milling step, then, the insulating structure  17  and the first conductive region  14  and second conductive region  15  are exposed and on a surface formed from the second face  20 ′ set opposite to the first face  4  (FIG. 11). In greater detail, the insulating structure  17  is surrounded by a residual portion  2 ″ of the substrate  2 , and the thickness of the wafer  1  is substantially equal to the depth D. In addition, the conductive regions  14 ,  15 , which traverse the insulating structure  17  throughout in a direction orthogonal to the first face  4 , are electrically insulated from the residual portion  2 ″ of the substrate  2 . Consequently, also the inductor  26 , which is carried entirely by the insulating structure  17  and is directly connected only to the conductive regions  14 ,  15 , is electrically insulated from the residual portion  2 ″ of the substrate  2 . In addition, in the embodiment of the invention here described, the inductor  26  and the electronic circuits  18  are formed on one and the same face of the wafer  1 , namely on the first face  4 .  
         [0040]    Next (FIGS. 11 and 12), on the second face  20 ′ of the wafer  1 , conductive lines  29  are formed for supplying the inductor  26  through the first conductive region  14  and second conductive region  15 . In greater detail, an adhesive layer of conductive material is deposited and defined so as to form tracks  31 , one of which forms a contact with the first conductive region  14  and the other with the second conductive region  15 . Next, by pressing metal material, projecting contacts or “bumps”  32  are formed, which adhere to the tracks  31 . Finally, the wafer  1  is turned upside down again for possible processing steps (for example, the wafer  1  may be bonded to another wafer—not shown—by means of the bumps  32 , according to a so-called “wafer-bonding technique”).  
         [0041]    In one variant of the process that forms the subject of the present invention, the inductor  26  is englobed in an insulating layer  35  of dielectric material, for example silicon dioxide, which is deposited before the conductive lines  29  are formed (FIG. 13).  
         [0042]    According to another variant, the inductor  26  and the integrated circuits  18  are formed on the opposite faces  4 ,  20 ′ of the wafer  1 . In this case, the wafer  1  is milled immediately after the insulating structure  17  has been formed and before fabrication of the integrated circuits  18  and the inductor  26 .  
         [0043]    The process described herein affords the advantages illustrated in what follows. First, the insulating structure  17 , which is made of thermal oxide, has itself excellent dielectric characteristics which enable decoupling of the inductor  26  from the conductive portions of the wafer  1 , such as residual portion  2 ″ of the substrate  2 . In addition, the substrate  2 ′ that underlies the insulating structure  17  is completely removed, and hence no dispersions nor inductive couplings linked to eddy currents can occur, which, instead, are normally present when there remains a conductive substrate. Also electromagnetic coupling between the conductive lines  29  and the inductor  26  is substantially absent, in so far as the thickness of the insulating structure  17  is very large (in the example, 100 μm).  
         [0044]    Second, for forming the insulating structure  17 , standard processing steps for manufacturing integrated circuits are exclusively used. Consequently, the process is, on the one hand, compatible with the fabrication of integrated circuits in the residual portion  2 ″ of the substrate  2 , and, on the other, has a contained cost and acceptable execution times. In particular, for forming the insulating structure  17  no prolonged oxidation steps are required, since it is sufficient to erode the walls  8  and fill the trenches  9 ,  11 ,  12 , which have a thickness of a few micron.  
         [0045]    In addition, because of the high decoupling of the insulating structure  17 , it is possible to fabricate integrated inductors having a high figure of merit and small overall dimensions.  
         [0046]    According to an embodiment of the invention, the process is used for the fabrication of a power device, in particular a bipolar transistor, integrated in a wafer of semiconductor material together with other active and passive electronic components.  
         [0047]    As shown in FIGS.  14 - 19 , a wafer  40  of monocrystalline silicon, for example of N type conductivity, comprises a substrate  41 , which is initially opened by means of a deep trench etch, to form a plurality of trenches  42  set alongside one another. The trenches  42 , which have a depth D′ of, for instance, 100 μm, are substantially developed along respective concentric closed polygonal lines, preferably forming squares or rectangles. The trenches  42  are open on a first face  44  of the wafer  40 , and in pairs define walls  43 . The trenches  42  and the walls  43  respectively have a width W′ and a thickness S′ which are equal to one another (e.g., 2.5 μm) and form a frame-like grid  45  (FIGS. 14 and 15).  
         [0048]    Next, the walls  43  are completely oxidized by thermal oxidation. Since the width W′ of the trenches  42  is equal to the thickness S′ of the walls  43 , and, as mentioned previously, the thermal oxide substantially grows for one half inside the silicon of the walls  43  and for one half on the interior of the trenches  42 , in this thermal oxidation step, the trenches  42  are completely filled with silicon dioxide (FIGS. 16 and 17), and the walls  43  are substantially composed of silicon dioxide Consequently, at the end of thermal oxidation, a silicon-dioxide insulating structure  45  is formed, which has a frame-like shape and has a height substantially equal to the depth D′ and a total width X of the sum of the widths and thicknesses of the trenches  42  and walls  43 , respectively, as shown in FIG. 16.  
         [0049]    Next, the wafer  40  undergoes processing steps that are standard in the micro-electronics industry for the fabrication of integrated electronic components. In particular (FIG. 18), in an internal conductive region  46 , delimited by the insulating structure  45 , a power transistor  48  is formed, here of a lateral bipolar type, and in an external conductive region  47 , which surrounds the insulating structure  45 , a driving circuit  50  for driving the power transistor  48  is formed, the said circuit being here schematically represented by means of active and passive electronic components. The power transistor  48  may be fabricated as described hereinafter. Initially, a P-type well, designed to form the base  51  of the power transistor  48 , is formed in the internal conductive portion  46 . Next, inside the base  51  an N + -type emitter region  52  is formed and, at the same time, a collector region  53  is formed, which is also of the N +  type and is embedded in the internal conductive region  46  alongside the base  51 . A silicon-dioxide insulation layer  55  is then grown thermally, which is selectively etched above the base  51 , the emitter region  52 , and the collector region  53 . Finally, respective base contacts  56 , emitter contacts  57 , and collector contacts  58  are formed in the openings thus obtained.  
         [0050]    The wafer  40  is then turned upside down (FIG. 19) and is milled, so as to remove completely a portion  41 ′ of the substrate  41  comprised between the insulating structure  45  and a second face  49  of the wafer  40 , which is set opposite to the first face  44 . The structure shown in FIG. 20 is thus obtained, where the wafer  40  has been turned upside down again. In practice, at the end of this step the insulating structure  45  separates the internal conductive portion  46  and the external conductive portion  47  of the wafer  40  from one another, insulating them electrically and magnetically.  
         [0051]    According to another embodiment of the invention, which will be illustrated hereinafter with reference to FIGS.  21 - 23 , a monocrystalline-silicon wafer  60 , comprising a substrate  61 , is initially etched by means of a deep trench etch (FIG. 21). In this step, trenches  62  are formed, which are adjacent to one another and define in pairs conductive walls  63 . In addition, the trenches  62 , which in the present case are rectilinear, are open on a first face  65  of the wafer  60 , have a depth D″ of, for instance 100 μm, and a width W″ not smaller than a thickness S″ of the conductive walls  63 . Preferably the aspect ratio W″/S″ between the width W″ of the trenches  62  and the thickness S″ of the conductive walls  63  is between 1 and 2.  
         [0052]    Next (FIG. 22), the wafer  60  is thermally oxidized. In this step, the conductive walls  63  oxidize completely, forming insulating walls  66 , and the trenches  62  are partially filled with silicon dioxide. In fact, as explained previously, the thermal oxide grows substantially for one half inside the silicon and for one half outwards. In addition, the bottom walls  68  of the trenches  62  oxidize, and a base  69  is thus formed, which is also made of silicon dioxide and which connects the insulating walls  66  together at the bottom. In practice, at the end of the oxidation step, in the wafer  60  an insulating structure  70  is formed, which comprises the base  69 , from which the insulating walls  66  project cantilevered.  
         [0053]    In order to improve the decoupling properties of the insulating structure  70 , a dielectric layer  71 , for example of silicon dioxide, is next deposited on the first face  65  of the wafer  60  and fills the trenches  62 ′, closing them. Given that the depth of the trenches  62 ′ is much greater than their width, in this step the oxide deposited cannot fill the trenches  62 ′ completely. Buried air bubbles  73  may thus form, which do not adversely affect the insulation provided by the insulating structure  70  and by the dielectric layer  71 , as shown in FIG. 22.  
         [0054]    The dielectric layer  71  is then etched and removed from the first face  65  of the wafer  60 , which is uncovered again.  
         [0055]    The process is then completed, substantially as already described previously. In particular, integrated circuits  76 , schematically represented in FIG. 23 by means of active and passive components, are formed in the substrate  61 . An electrical component, for example an inductor  75 , is formed on top of the insulating structure  70 , and a portion  61 ″ of the substrate  61 , comprised between the insulating structure  70  and a second face  74  of the wafer  60 , set opposite to the first face  65 , is removed by milling.  
         [0056]    Finally, it is clear that modifications and variations may be made to the process described herein, without thereby departing from the scope of the present invention.  
         [0057]    In particular, the process may be used for the fabrication of electronic devices of a different type, such as MOS-type vertical power transistors.  
         [0058]    In addition, the insulating structure incorporated in the semiconductor wafer may have a different shape (for example, circular or annular) and may be formed starting from a grid of another type. For example, the grid could be made up of substantially square cells set alongside one another, having sides of approximately 8-10 μm and being delimited by walls having a thickness of approximately 5 μm. In addition, also the envelope of the grid, and hence the shape of the insulating structure, may be different from what is illustrated in the examples.  
         [0059]    All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.