Abstract:
A source driver for use in a display device having a shift register unit for sequentially activating output signals. The shift register unit includes a plurality of shift registers connected in series, wherein Nth shift register among the plurality of shift registers selects one of an output of a (N−1)th shift register and an output of a (N−A)th shift register according to a channel selection signal to thereby receive the selected signal, where A is a natural number which is greater than or equal to 2.

Description:
FIELD OF INVENTION 
     The present invention relates to a source driver for use in a thin film transistor-liquid crystal display (TFT-LCD); and, more particularly, to a source driver capable of adjusting the number of channels. 
     DESCRIPTION OF PRIOR ART 
       FIG. 1  is a block diagram showing a conventional thin film transistor-liquid crystal display (TFT-LCD). 
     As shown, the conventional TFT-LCD includes a timing control unit  100 ; a plurality of gate drivers, e.g.,  200 ; a plurality of source drivers, e.g.,  300 ; a TFT-LCD panel  400 ; and a voltage generator  500 . 
     The plurality of gate drivers are controlled by the timing control unit  100  in order to sequentially drive gate lines of the TFT-LCD panel  400 . Similarly, the plurality of source drivers are controlled by the timing control unit  100  to thereby drive source lines of the TFT-LCD panel  400  so that the TFT-LCD panel  400  display image data. 
     The TFT-LCD panel  400  includes a plurality of unit pixels arranged in a matrix form. Each of the unit pixels includes a thin film transistor T 1  and a capacitor C 1 . A source of the thin film transistor T 1  is connected to a source line operated by the source driver  300  and a gate of the thin film transistor T 1  is connected to a gate line operated by the gate driver  200 . 
     The timing control unit  100  controls the gate driver  200  to sequentially drive a corresponded gate line. The source driver  300  receives data outputted from the timing control unit  100  to thereby generate an analog signal and input the generated analog signal to a source line. In this manner, the TFT-LCD panel  400  displays image data. 
       FIG. 2  is a block diagram depicting the source driver  300 . 
     As shown, the source driver  300  includes a digital control unit  310 ; a register unit  320  for storing a digital data signal outputted from the digital control unit  310 ; a level shifter unit  330  for controlling a level of a signal outputted from the register unit  320 ; a digital to analog converter  340  for converting a digital signal outputted from the level shifter unit  330  to an analog signal; a analog bias unit  350 ; and a buffering unit  360  for buffering an output of the digital to analog converter  340  according to a bias generated by the analog bias unit  350  to thereby input the buffered signal to the source line. 
     The digital control unit  310  receives a source driver start pulse (SSP), a data clock and a digital data from the timing control unit  100  to thereby transfer the digital data to the register unit  320  and control the register unit  320 . 
     The register unit  320  includes a shift register unit  321 , a sampling register unit  322  and a holding register unit  323 . 
     Each digital data is stored to a sampling register by a shift register. The digital data stored in the sampling register is transferred to the digital to analog converter  340  through a holding register and a level shifter in response to a control signal LOAD outputted from the timing control unit  100 . 
     Herein, the register unit  320  is operated at a low voltage, e.g., 3.3V; however, the digital to analog converter  340  and the buffering unit  360  are operated at a high voltage, e.g., 6 to 12V. Therefore, the level shifter unit  330  controls a level of a signal outputted from the register unit  320 . 
     The digital to analog converter  340  includes a gamma reference unit  342  for making an input voltage nonlinear to thereby linearly display brightness of light; and a decoding unit  344  for selecting one of a plurality of gamma reference output signals outputted from the gamma reference unit  342  according to the digital signal outputted from the level shifter unit  330  to thereby output the selected signal as an analog signal. 
       FIG. 3  is a block diagram illustrating the shift register unit  321 . 
     As shown, the shift register unit  321  includes a plurality of flip-flops connected in series, i.e.,  321   a  to  321   e . Each flip-flop activates its output signal in response to an output of a preceding flip-flop. A first flip-flop, i.e.,  321   a  or  321   e , receives an output of the digital control unit  321 . 
     Meanwhile, according to a direction selection signal UP, the plurality of flip-flops are sequentially activated from  321   a  to  321   e  or from  321   e  to  321   a.    
       FIG. 4  is a schematic circuit diagram showing the flip-flop  321   a.    
     As shown, the flip-flop  321   a  includes a selection unit  1  for selecting one of a right input signal IR and a left input signal IL according to the direction selection signal UP; a flip-flop element  2  for receiving an output of the selection unit  1  in synchronization with a clock signal CLK; and a buffer unit  3  for buffering an output of the flip-flop element  2  to thereby generate a first active signal OUT and a second active signal SEQ. 
     The flip-flop element  2  receives one of the right input signal IR and the left input signal IL in synchronization with the clock signal CLK. Thereafter, the buffer unit  3  buffers the output of the flip-flop element  2  to thereby generate the first active signal OUT and a first active bar signal OUTB for activating each sampling register and the second active signal SEQ for activating a next flip-flop. 
     Meanwhile, since channels of the source driver are one-to-one matched to sub-pixels of a panel, the number of the channels included in the source driver is determined according to a resolution of the panel. For instance, when the resolution of a color panel is 1024×768, the number of column lines is 1024 and the number of sub-pixels is 3072 (=1024×3) Therefore, each source driver must include 384 channels on the assumption that 8 source drivers are included in the color panel. 
     Accordingly, a source driver having 384 channels can be used for only a color panel having a particular resolution, i.e., a resolution of 1024×768 or a resolution of integral multiple of 384. That is, since the channels included in the source driver are physically fixed, the source driver should be re-designed in order to be used in a color panel having another resolution. 
     SUMMARY OF INVENTION 
     It is, therefore, an object of the present invention to provide a source driver for controlling the number of channels using a software method. 
     In accordance with an aspect of the present invention, there is provided a source driver having a shift register unit for sequentially activating output signals, the shift register unit including a plurality of shift registers connected in series, wherein Nth shift register among the plurality of shift registers selects one of an output of a (N−1)th shift register and an output of a (N−A)th shift register according to a channel selection signal to thereby receive the selected signal, where A is a natural number which is greater than or equal to 2. 
     In accordance with another aspect of the present invention, there is provided a source driver having a shift register unit including a plurality of flip-flops each of which selects one of a first input data and a second input data in response to a first channel selection signal and a second channel selection signal and outputs the selected signal in synchronization with a clock signal, the source driver including: a first flip-flop for receiving a start signal as a fist and a second input data and for receiving a first control signal as a first and a second channel selection signals; a second flip-flop for receiving an output of the first flip-flop as a first and a second input data and for receiving a second control signal as a first and a second channel selection signals; a third flip-flop for receiving an output of the second flip-flop as a first and a second input data and for receiving a third control signal as a first and a second channel selection signals; a fourth flip-flop for receiving an output of the third flip-flop and the output of the second flip-flop as a first input data and a second input data respectively and for receiving a fourth control signal and the third control signal as a first channel selection signal and a second channel selection signal; a fifth flip-flop for receiving an output of the fourth flip-flop as a first and a second channel selection signals and for receiving an inverted second control signal as a first and a second channel selection signals; a sixth flip-flop for receiving an output of the fifth flip-flop and the output of the second flip-flop as a first input data and a second input data respectively and for receiving the second control signal and the inverted second control signal as a first channel selection signal and a second channel selection signal respectively; and a seventh flip-flop for receiving an output of the sixth flip-flop as a first and a second input data and for receiving the first control signal as a first and a second channel selection signals. 
     In accordance with further another aspect of the present invention, there is provided a source driver having a shift register unit including a plurality of flip-flops each of which selects one of a first input data and a second input data as a left input data and one of a third input data and a fourth input data as a right input data in response to a first channel selection signal and a second channel selection signal in order to select one of the left input data and the right input data according to a direction selection signal and output the selected signal in synchronization with a clock signal, the source driver including: a first flip-flop for receiving a start signal as a first and a second input data and for receiving an output of a second flip-flop and an output of a third flip-flop as a third input data and a fourth input data respectively and for receiving a first control signal as a first and a second channel selection signals; the second flip-flop for receiving an output of the first flip-flop as a first and a second input data and for receiving the output of the third flip-flop as a third and a fourth input data and for receiving a second control signal as first and a second channel selection signals; the third flip-flop for receiving the output of the second flip-flop and the output of the first flip-flop as a first input data and a second input data respectively and for receiving an output of a fourth flip-flop as a third and a fourth input data and for receiving the second control signal and an inverted second control signal as a first channel selection signal and a second channel selection signal respectively; and the fourth flip-flop for receiving the output of the third flip-flop as a first and a second input data and for receiving the start signal as a third and a fourth input data and for receiving the first control signal as a first and a second channel selection signals, wherein each of the first to the fourth flip-flops receives a same clock signal and a same direction selection signal. 
     In accordance with further another aspect of the present invention, there is provided a multi-channel shift register having a plurality of flip-flops connected in series, each of the flip-flops selects one of a first input data and a second input data in response to a first channel selection signal and a second channel selection signal and outputs the selected signal in synchronization with a clock signal, the multi-channel shift register including: a first flip-flop for receiving a start signal as a fist and a second input data and for receiving a first control signal as a first and a second channel selection signals; a second flip-flop for receiving an output of the first flip-flop as a first and a second input data and for receiving a second control signal as a first and a second channel selection signals; a third flip-flop for receiving an output of the second flip-flop as a first and a second input data and for receiving a third control signal as a first and a second channel selection signals; a fourth flip-flop for receiving an output of the third flip-flop and the output of the second flip-flop as a first input data and a second input data respectively and for receiving a fourth control signal and the third control signal as a first channel selection signal and a second channel selection signal; a fifth flip-flop for receiving an output of the fourth flip-flop as a first and a second channel selection signals and for receiving an inverted second control signal as a first and a second channel selection signals; a sixth flip-flop for receiving an output of the fifth flip-flop and the output of the second flip-flop as a first input data and a second input data respectively and for receiving the second control signal and the inverted second control signal as a first channel selection signal and a second channel selection signal respectively; and a seventh flip-flop for receiving an output of the sixth flip-flop as a first and a second input data and for receiving the first control signal as a first and a second channel selection signals. 
     In accordance with further another aspect of the present invention, there is provided a multi-channel shift register having a plurality of flip-flops each of which selects one of a first input data and a second input data as a left input data and one of a third input data and a fourth input data as a right input data in response to a first channel selection signal and a second channel selection signal in order to select one of the left input data and the right input data according to a direction selection signal and output the selected signal in synchronization with a clock signal, the multi-channel shift register including: a first flip-flop for receiving a start signal as a first and a second input data and for receiving an output of a second flip-flop and an output of a third flip-flop as a third input data and a fourth input data respectively and for receiving a first control signal as a first and a second channel selection signals; the second flip-flop for receiving an output of the first flip-flop as a first and a second input data and for receiving the output of the third flip-flop as a third and a fourth input data and for receiving a second control signal as first and a second channel selection signals; the third flip-flop for receiving the output of the second flip-flop and the output of the first flip-flop as a first input data and a second input data respectively and for receiving an output of a fourth flip-flop as a third and a fourth input data and for receiving the second control signal and an inverted second control signal as a first channel selection signal and a second channel selection signal respectively; and the fourth flip-flop for receiving the output of the third flip-flop as a first and a second input data and for receiving the start signal as a third and a fourth input data and for receiving the first control signal as a first and a second channel selection signals, wherein each of the first to the fourth flip-flops receives a same clock signal and a same direction selection signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram showing a conventional thin film transistor-liquid crystal display (TFT-LCD); 
         FIG. 2  is a block diagram depicting a source driver shown in  FIG. 1 ; 
         FIG. 3  is a block diagram illustrating a shift register unit shown in  FIG. 2 ; 
         FIG. 4  is a schematic circuit diagram showing a flip-flop shown in  FIG. 3 ; 
         FIG. 5  is a schematic circuit diagram showing a flip-flop for use in a shift register included in a source driver in accordance with a preferred embodiment of the present invention; 
         FIG. 6  is a block diagram showing a shift register embodied by using 7 single-direction flip-flops; 
         FIG. 7  is a block diagram showing a bi-directional multi-channel shift register embodied by using 4 flip-flops shown in  FIG. 5 ; 
         FIG. 8  is a block diagram showing a bi-directional multi-channel shift register unit in accordance with a third embodiment of the present invention; and 
         FIG. 9  is a block diagram showing a bi-directional multi-channel shift register included in the bi-directional multi-channel shift register unit shown in  FIG. 8 . 
     
    
    
     DETAILED DESCRIPTION OF INVENTION 
     Hereinafter, a source driver in accordance with the present invention will be described in detail referring to the accompanying drawings. 
       FIG. 5  is a schematic circuit diagram showing a flip-flop for use in a shift register included in a source driver in accordance with a preferred embodiment of the present invention. 
     As shown, the flip-flop includes an input data selection unit  520 ; a direction selection unit  540 ; a flip-flop element  560 ; and a buffer unit  580 . 
     The input data selection unit  520  outputs one of a first input data INL 1  and a second input data INL 2  as a left input data in response to a first channel selection signal OS 1  and a second channel selection signal OS 2 . The input data selection unit  520  also outputs one of a third input data INR 1  and a fourth input data INR 2  as a right input data in response to the first channel selection signal OS 1  and the second channel selection signal OS 2 . 
     The direction selection unit  540  selects one of the left input data and the right input data according to a direction selection signal UP and a direction selection bar signal UPB to thereby output the selected signal. 
     The flip-flop element  560  receives an output of the direction selection unit  540  in synchronization with a clock signal CLK. 
     The buffer unit  580  buffers an output of the flip-flop element  560  to thereby generate a first active signal OUT and a second active signal SEQ. 
     In detail, the input data selection unit  520  includes a first AND gate AD 1  for receiving the second input data INL 2  and the second channel selection signal OS 2 ; a second AND gate AD 2  for receiving the first input data INL 1  and the first channel selection signal OS 1 ; a third AND gate AD 3  for receiving the fourth input data INR 2  and the second channel selection signal OS 2 ; a fourth AND gate AD 4  for receiving the third input data INR 1  and the first channel selection signal OS 1 ; a first NOR gate NR 1  for generating the left input data by performing a logic NOR operation to and output of the first AND gate AD 1  and an output of the second AND gate AD 2 ; and a second NOR gate NR 2  for generating the right input data by performing a logic NOR operation to an output of the third AND gate AD 3  and an output of the fourth AND gate AD 4 . 
     The direction selection unit  540  includes a first switch SW 1  for transferring the left input data in response to the direction selection signal UP; a second switch SW 2  for transferring the right input data in response to the direction selection bar signal UPB; and a first inverter for inverting a voltage loaded on a node commonly coupled to an output of the first switch SW 1  and an output of the second switch SW 2 . 
     The buffer unit  580  includes a second and a third inverters I 2  and I 3  for delaying an output of the flip-flop element  560  to thereby generate the first active signal OUT; a fourth inverter I 4  for inverting the output of the flip-flop element  560 ; a seventh to a ninth inverters I 7  to I 9  for generating the second active signal SEQ by inverting and delaying an output of the fourth inverter I 4 ; and a fifth and a sixth inverters I 5  and I 6  for generating an inverted version of the first active signal OUT, i.e., a first active bar signal OUTB, by delaying the output of the fourth inverter I 4 . 
     Meanwhile, by using the above-described flip-flop, a multi-channel shift register, whose activation direction can be controlled, can be embodied. That is, the multi-channel shift register can be activated from left to right or from right to left. Therefore, in case of a shift register which is activated in a single direction, a flip-flop dose not need to receive the third input data INR 1  and the fourth input data INR 2 . Accordingly, a single-direction flip-flip does not need to include the third AND gate AD 3 , the fourth AND gate AD 4  and the second switch SW 2 . Further, the first and the second switches SW 1  and SW 2  for selecting one of the left input data and the right input data are not required. 
     An operation of the flip-flop shown in  FIG. 5  is described below. 
     The input data selection unit  520  outputs one of the first and the second input data INL 1  and INL 2  as the left input data and outputs one of the third and the fourth input data INR 1  and INR 2  as the right input data in response to the first and the second channel selection signals OS 1  and OS 2 . 
     Thereafter, the direction selection unit  540  selects one of the left input data and the right input data in response to the direction selection signal UP and inputs the selected signal to the flip-flop element  560 . Then, the flip-flop element  560  outputs the selected signal in synchronization with the clock signal CLK. 
     Thereafter, the buffer unit  580  receives an output of the flip-flop element  560  to thereby generate the first active signal OUT, the first active bar signal OUTB and the second active signal SEQ. 
     Herein, when the first channel selection signal OS 1  is in a logic high level, the input data selection unit  520  selects the first input data INL 1  in order to output the left input data and selects the third input data INR 1  in order to output the right input data. On the contrary, when the second channel selection signal OS 2  is in a logic high level, the input data selection unit  520  selects the second input data INL 2  in order to output the left input data and selects the fourth input data INR 1  in order to output the right input data. 
     When both the first and the second channel selection signals OS 1  and OS 2  are inactivated, an output of the flip-flop is inactivated. Therefore, in case that a shift register is embodied by using a plurality of the above-mentioned flip-flop, the number of output signals can be controlled according to the first and the second channel selection signals OS 1  and OS 2 . 
       FIG. 6  is a block diagram showing a shift register embodied by using  7  single-direction flip-flops. The shift register shown in  FIG. 6  is an exemplary shift register capable of controlling the number of output signals by using a control signal. Herein, it is assumed that the shift register is operated in a single-direction. 
     Referring to  FIG. 6 , the shift register includes a first to a sixth flip-flops  610  to  670 . 
     The first flip-flop  610  receives a start signal SP as a first input data IN 1  and a second input data IN 2  and also receives a power supply voltage VDD as a first channel selection signal OS 1  and a second channel selection signal OS 2 . The second flip-flop  620  receives an output signal SEQ from the first flip-flop  610  as a first input data IN 1  and a second input data IN 2  and also receives a third control bar signal/C as a first channel selection signal OS 1  and a second channel selection signal OS 2 . Herein, the third control bar signal/C is an inverted version of a third control signal C. 
     The third flip-flop  630  receives an output signal SEQ from the second flip-flop  620  as a first input data IN 1  and a second input data IN 2  and also receives a first control signal A as a first channel selection signal OS 1  and a second channel selection signal OS 2 . The fourth flip-flop  640  receives an output of the third flip-flop and an output of the second flip-flop as a first input data IN 1  and a second input data IN 2  respectively and also receives a first control signal A and a second control signal B as a first channel selection signal OS 1  and a second channel selection signal OS 2  respectively. 
     The fifth flip-flop  650  receives an output signal SEQ from the fourth flip-flop  640  as a first input data IN 1  and a second input data IN 2  and also receives the third control bar signal/C as a first channel selection signal OS 1  and a second channel selection signal OS 2 . The sixth flip-flop  660  receives an output of the fifth flip-flop  650  and the output of the first flip-flop  610  as a first input data IN 1  and a second input data IN 2  respectively and also receives the third control signal C and the third control bar signal/C as a second channel selection signal OS 2  and a first channel selection signal OS 1 . 
     The seventh flip-flop  670  receives an output of the sixth flip-flop  660  as a first input data IN 1  and a second input data IN 2  and also receives the power supply voltage VDD as a first channel selection signal OS 1  and a second channel selection signal OS 2 . 
     Meanwhile, the second to the fifth flip-flops  620  to  650  under bypass lines  680  and  690  are selectively inactivated according to the number of output signals being controlled by the first, the second and the third control signals A, B and C. That is, since a flip-flop activates its output signal in response to an output of a preceding flip-flop, an output of a flip-flop is transferred to a flip-flop located next to an inactivated flip-flop to thereby activate the flip-flop. 
     Herein, the first flip-flop  610 , the sixth flip-flop and the seventh flip-flop  670  are always activated regardless of the number of output signals by receiving the power supply voltage VDD as the first channel selection signal OS 1  and the second channel selection signal OS 2 . That is, since the first and the second channel selection signal OS 1  and OS 2  are always activated as a logic high level due to the power supply voltage VDD, the first flip-flop  610 , the sixth flip-flop and the seventh flip-flop  670  are always activated to be operated in response to the first input data IN 1  and the second input data IN 2 . 
     In addition, the first to the seventh flip-flops  610  to  670  receive a clock signal CLK in order to activate output signals OUT and SEQ. 
     Meanwhile, Table. 1 shows the number of output signals of the shift register according to the control signals inputted as the channel selection signals. 
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Number of output signals 
                 A 
                 B 
                 C 
                 /C 
               
               
                   
               
             
             
               
                 # 7 
                 H 
                 L 
                 L 
                 H 
               
               
                 # 5 
                 L 
                 H 
                 L 
                 H 
               
               
                 # 3 
                 L 
                 L 
                 H 
                 L 
               
               
                   
               
             
          
         
       
     
     When the number of output signals is 3, the third control signal C is in a logic high level and the other control signals, i.e., A, B and/C, are in a logic low level. Accordingly, the second to the fifth flip-flops  620  to  650  are inactivated. 
     When the number of output signals is 5, the second control signal B is in a logic high level and the first and the third control signals A and C are in a logic low level. Therefore, the third flip-flop  630  is inactivated. 
     In case that the number of output signals is 7, the first control signal A is in a logic high level and the second and the third control signals B and C are in a logic low level. Therefore, one of the first and the second channel selection signals OS 1  and OS 2  is in a logic high level. Accordingly, all of the first to the seventh flip-flops  610  to  670  are enabled to thereby activate output signals of the first to the seventh flip-flops  610  to  670 . 
     By using the above-mentioned method, not only the number of output signals but also multi-channels according to the bypass lines can be formed. 
     Meanwhile, the output signals of the shift registers are used as activation signals of sampling registers included in a sampling register unit (shown in  FIG. 2 ). Therefore, by controlling the number of output signals of the shift register, the number of channels of a source driver can be controlled. 
     Accordingly, by using the above-mentioned shift register for the source driver, the number of channels of the source driver can be controlled according to a control signal. 
       FIG. 7  is a block diagram showing a bi-directional multi-channel shift register embodied by using 4 flip-flops shown in  FIG. 5 . The number of output signals of the bi-directional multi-channel shift register can be controlled according to a control signal. 
     As shown, the bi-directional multi-channel shift register includes a first to a fourth flip-flops  720  to  780 . 
     The first flip-flop  720  receives a start signal SP as a first input data INL 1  and a second input data INL 2 . The first flip-flop  720  also receives an output signal SEQ of the second flip-flop  740  and an output signal SEQ of the third flip-flop  760  as a third input data INR 1  and a fourth input data INR 2  respectively. The second flip-flop  740  receives an output signal SEQ of the first flip-flop  720  as a first input data INL 1  and a second input data INL 2  and also receives the output signal SEQ of the third flip-flop  760  as a third input data INR 1  and a fourth input data INR 2 . 
     The third flip-flop  760  receives the output signal SEQ of the second flip-flop  740  and an output signal SEQ of the first flip-flop  720  as a first input data INL 1  and a second input data INL 2  respectively. The third flip-flop  760  also receives an output signal SEQ of the fourth flip-flop  780  as a third input data INR 1  and a fourth input data INR 2 . The fourth flip-flop  780  receives the output signal SEQ of the third flip-flop  760  as a first input data INL 1  and a second input data INL 2 . The fourth flip-flop  780  also receives the start signal SP as a third input data INR 1  and a fourth input data INR 2 . 
     Herein, a control signal en is inputted to a first channel selection signal OS 1  and a second channel selection signal OS 2  of the second flip-flop  740 . The third flip-flop  760  receives the control signal en and a control bar signal/en as a first channel selection signal OS 1  and a second channel selection signal OS 2  respectively. 
     Meanwhile, the first flip-flop  720  receives a power supply voltage VDD as a first channel selection signal OS 1  and a second channel selection signal OS 2 . Likewise, the fourth flip-flop  780  receives the power supply voltage VDD as a first channel selection signal OS 1  and a second channel selection signal OS 2 . Therefore, the first and the second flip-flops  720  and  780  activate output signals according to input signals regardless of the control signals. 
     In addition, each of the first to the fourth flip-flops  720  to  780  receives a clock signal CLK a first direction selection signal UP and a second direction selection signal UPB. 
     Meanwhile, a multi-channel shift register includes 4 flip-flops, and all the 4 flip-flops are activated when the control signal en is in a logic high level, and thus 4 output signals are outputted. On the contrary, when the control signal en is in a logic low level, 3 output signals are outputted since the second flip-flop  740  is inactivated. 
     An operation of the bi-directional multi-channel shift register is described below. 
     It is assumed that the output signals of the flip-flops included in the bi-directional multi-channel shift register are sequentially activated from left to right and the control signal en and the first direction selection signal UP are respectively in a logic low level and a logic high level. 
     When the start signal SP is activated, the first flip-flop  720  receives the start signal SP in synchronization with the clock signal CLK to thereby activate output signals SEQ and OUT. However, output signals SEQ and OUT of the second flip-flop  740  are inactivated by the control signal en. 
     Thereafter, the third flip-flop  760  receives the output signal SEQ of the first flip-flop  720  as the second input data INL 2  in response to the control signal en in synchronization with the clock signal CLK to thereby activate output signals OUT and SEQ. Similarly, the fourth flip-flop  780  receives the output signal SEQ of the third flip-flop  760  in synchronization with the clock signal CLK in order to activate output signals OUT and SEQ. 
     Meanwhile, when the first direction selection signal UP is in a logic low level, the output signals of the flip-flops included in the bi-directional multi-channel shift register are activated from right to left receiving the third input data INR 1  and the fourth input data INR 2 . 
       FIG. 8  is a block diagram showing a bi-directional multi-channel shift register unit in accordance with a third embodiment of the present invention. 
     In case that a source driver is embodied by using the bi-directional multi-channel shift register unit shown in  FIG. 8 , the source driver has three different number of output signals, i.e.,  384 ,  414  and  420 . 
       FIG. 9  is a block diagram showing a bi-directional multi-channel shift register included in the bi-directional multi-channel shift register unit shown in  FIG. 8 . 
     Referring to  FIGS. 8 and 9 , the bi-directional multi-channel shift register unit includes a plurality of shift registers connected in series. Herein, each of the plurality of shift registers includes 4 flip-flops. 
     Meanwhile, since each flip-flop controls three channels, each shift register controls 12 channels. Therefore, when all of the shift registers are activated, 420 channels are activated. In case that two registers are inactivated, 414 channels are activated since 6 channels are inactivated. When 6 shift registers are inactivated, 384 channels are activated since 36 channels are inactivated. The different numbers of channels are substantial to be applied to various resolutions of a display product such as a liquid crystal display (LCD). 
     Meanwhile, the source driver including the multi-channel shift register in accordance with the present invention can control the number of channels by using a control signal. That is, according to the prior art, after a conventional source driver is manufactured, the conventional source driver is required to be full-ware revised in order to change the channel sections when the number of channels is not compatible with a resolution of a thin film transistor-LCD (TFT-LCD). However, the channel sections of the source driver according to the present invention can be changed by revising a metal-line layer without revising other layers under a contact. 
     Accordingly, the source driver in accordance with the present invention can be applied to various active matrix displays such as the TFT-LCD and an organic light emitting display (OLED). 
     The present application contains subject matter related to Korean patent application No. 200-, filed in the Korean Patent Office on, 2004, the entire contents of which being incorporated herein by reference. 
     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.