Abstract:
This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.

Description:
CLAIM OF PRIORITY 
     This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 60/943,879 filed Jun. 14, 2007. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The technical field of this invention is logical hierarchy partitioning of designs at asynchronous clock boundaries to enable aggressive power management. 
     BACKGROUND OF THE INVENTION 
     It is a widely used design practice to designing intellectual property (IP) electronic modules with multiple asynchronous clock domains. This practice permits designers to meet performance requirements of each clock domain independently. This also eases the timing closure problem because each clock domain can be treated independently for optimization, clock tree synthesis and timing closure. 
     Providing multiple asynchronous clock domains enables clock-gating each domain independently to save dynamic power. In peripheral IPs the core clock can be clock gated when there is no data to be exchanged with the external world. The input/output (IO) clock can be kept on to generate a core/CPU interrupt on detection of incoming packet data from the external world. 
     With shrinking process geometries, static/leakage power has become a major contributor to total power consumption. Such static power can be kept low by operating at a lower supply voltage. Since lowering the voltage reduces how fast the circuit can operate, it is important to operate the device at a supply voltage that is just enough to meet the performance requirements. This voltage gives the best power solution without compromising performance. 
     The asynchronous boundary inside the peripheral IP also provides an opportunity to save on leakage power by creating separate voltage domains for each of the asynchronous clock domains. Existing electronic design automation (EDA) tools require that each asynchronous clock domain must be enclosed by a distinct logical hierarchy, which subsequently becomes a voltage island. Each voltage island can then be separately optimized in operating voltage and frequency to meet the power and performance goals. 
     In many systems some of these voltage islands may be un-used for long periods of time. These voltage islands can be independently powered off using power switches on the chip to save on both leakage and dynamic power. 
     Designs with multiple asynchronous clock domains can be exploited to: 
     1. Meet performance requirements of each domain independently; 
     2. Save dynamic power by clock-gating each domain independently; 
     3. Save static power by supplying each domain in a voltage island an optimum supply voltage; and 
     4. Save power by shutting off power to a voltage island when not used. 
     Legacy IPs are typically designed to meet only the first design objective. Thus they may not have these asynchronous clock boundaries along logical hierarchies. To meet the other objectives, the circuit should be partitioned along the asynchronous clock domain boundaries and logical hierarchies should be created which then can be mapped to voltage islands. 
     SUMMARY OF THE INVENTION 
     This invention uses the capabilities of existing EDAs, such as Synopsys Design Compiler, to group logic pertaining to each clock domain into separate logic hierarchies. This invention does necessary logic cloning, level shifter and isolation cell insertion to completely isolate the timing paths to be within the respective hierarchies. The partition methodology involves: register grouping; inputs and clock gate grouping; and logic duplication. This invention is easily portable across any EDA synthesis tool and is scalable across process technologies. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other aspects of this invention are illustrated in the drawings, in which: 
         FIG. 1  is a flow chart illustrating the steps of this invention; 
         FIG. 2  illustrates an original circuit example used to explain the operation of this invention; 
         FIG. 3  illustrates an intermediate state of this invention following grouping; 
         FIG. 4  illustrates an intermediate state of this invention following logic duplication; 
         FIG. 5  illustrates an intermediate state of this invention following logic hierarchy creation; 
         FIG. 6  illustrates an intermediate state of this invention following creation of new connections; 
         FIG. 7  illustrates an intermediate state of this invention following redundant logic removal; and 
         FIG. 8  illustrates an intermediate state of this invention following level shifter and isolation cell insertion. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       FIG. 1  illustrates the partition method  100  of this invention. Partition method  100  begins with an input of the synthesized netlist of the circuit. Partition method  100  includes grouping  110 , logic duplication  120  and level shifter/isolation cell insertion  131 . Grouping  110  includes register grouping  111  and input and clock gate grouping  112 . Logic duplication  120  includes duplicate cells identification  121 , duplicate logic hierarchy creation  122 , new hierarchy connections  123 , redundant logic removal  124  and level shifter isolation cell insertion  125 . Each of these steps will be described in detail below. 
       FIG. 2  illustrates an example circuit to which this invention is applicable. Design module desA  200  of  FIG. 2  is a memory controller. Module desA  200  has two asynchronous clock domains: aclk and bclk. The clock domain aclk uses the core side interface clock. This is typically a clock ratio divided from the CPU clock. Clock domain bclk uses the memory interface clock. 
     This example makes the following assumptions. The core side voltage is V DD . The IO side voltage is V DD1 . The IO side voltage is V DD1  is switchable ON/OFF for power consumption control. 
     Module  200  includes flip-flops A  211 , B  212 , C  213 , D  214  and E  215  clocked by the core side interface clock aclk. Module  200  includes flip-flops F  216  and G  217  clocked by the memory interface clock bclk. Module  200  includes combinatorial logic c 1   221 , c 2   222 , c 3   223 , c 4   224  and c 5   225 . 
     The goal of partitioning desA module  200  and creating a logical hierarchy desA_aclk  280  ( FIG. 8 ) for aclk is to enable advanced power consumption control. To meet this goal: all timing paths from aclk to aclk are contained only within desA_aclk hierarchy; all timing paths from aclk to bclk pass through desA_aclk hierarchy only once; and all timing paths from bclk to aclk pass through desA_aclk hierarchy only once. 
     Module desA  200  has no hierarchies which clearly isolate aclk and bclk domains. There are hierarchies which contain both aclk and bclk registers. Some combinational logic such as logic c 1   221  to c 5   225  are shared between synchronous logic paths (aclk to aclk, bclk to bclk) and asynchronous logic paths (aclk to bclk, bclk to aclk). 
     In the modified module  280  ( FIG. 8 ) all aclk timing paths are totally enclosed within the desA_aclk hierarchy. All bclk timing paths are at the top level. Shared combinational logic such as c 1   221  to c 5   225  have been cloned to isolate the respective timing paths. The clock domain desA can be mapped to the V DD1  voltage domain and the clock domain desA_aclk can be mapped to the V DD  voltage domain. Level shifters are inserted for signals crossing from V DD  to V DD1  to translate the voltages and isolation cells from V DD1  to V DD . This ensures that when V DD1  is turned OFF, the inputs to the V DD  voltage domain are not left floating and that proper logic values are driven. 
     Returning to  FIG. 1 , register grouping  111  creates a logic hierarchy of all registers of a particular domain. Since the registers for each clock domain are not contained in a single hierarchy, the circuit design is first flattened. Registers along with fanin and fanout cones are grouped together and a new hierarchy desA_aclk is created. 
     Inputs and clock gates grouping  112  inputs of the newly created hierarchy desA_aclk. This hierarchy desA_aclk is inspected to see which inputs are at the module top level. For each of these inputs, the entire combinational cloud from the module input to the corresponding connection at the newly created hierarchy desA_aclk needs to be grouped into the aclk domain. All clock gates in the circuit which control aclk registers are also added to the desA_aclk hierarchy. 
       FIG. 3  illustrates the intermediate state following grouping  110 . Intermediate circuit  230  includes newly created hierarchy  231 . 
     Logic duplication  120  follows grouping  110 . Grouping  110  creates a new hierarchy desA_aclk  231  which comprises of all aclk registers and associated fanin and fanout combinational logic. From a timing perspective, all aclk to aclk timing paths such as A  211  to D  214 , B  212  to E  215  and C  213  to E  215  illustrated in  FIG. 2  are completely self-contained within the desA_aclk  231  hierarchy. The inputs to aclk timing paths are also completely within desA_aclk  231  hierarchy. Combinational logic on aclk to bclk paths such as B  212  to G  217  and C  213  to G  217  in  FIG. 2  are also inside desA_aclk  231  hierarchy. Timing paths from bclk to bclk which do not feed into or receive inputs from aclk are at the top level only. They do not traverse through the desA_aclk  231  hierarchy. Paths from bclk to bclk such as F to G traverse through desA_aclk hierarchy since they either feed into or receive inputs from aclk registers. These cross the boundary of desA_aclk  231  while entering and leaving the hierarchy causing voltage domain crossings. Since these paths are synchronous, they should be avoided. This is done by duplicating logic in the bclk domain (top level) discussed below. 
     Logic duplication  120  includes the following steps: duplicate cell identification  121 ; duplicate logic hierarchy creation  122 ; connections to new hierarchy  123 ; redundant logic removal  124 ; and level shifter and isolation cell insertion  125 . 
     Duplicate cell identification  121  involves a backward traversal from the outputs of desA_aclk  231  and recursively marks combinational cells on the path until all inputs of a combinational cell go back to aclk registers. The steps for accomplishing this are as follows. The method creates a list of all top level output ports of desA  200 . The method changes the design level to desA_aclk  231 . The method creates a collection $endpoints of all outputs at desA_aclk  231  hierarchy. The method filters out ports from this collection which are directly connected to top level output ports. For each $endpoint, the method gets the driving pin. The method checks what other pins are there in the fanout of the driving pin. If the driving pin is driving a top level output port, then the method stops processing that endpoint further. This filters out all outputs of desA_aclk  231  which are not driving a bclk register and hence need no duplication. The method gets the driving cell name for the driving pin and checks if the cell has processed user attribute set. This attribute is set later in the method. If the driving cell is a sequential cell (an aclk flip-flop), then the method stops processing at that endpoint. If the driving cell is a combinational cell, then the cell should be duplicated. The method appends the cell name to the list of duplicable cells. A new attribute PROCESSED is created on this cell. PROCESSED is set to true to indicate that this cell has been processed and marked for duplication and should not be processed again. This avoids large run-times for cells that exist in fanin cones of multiple output ports (endpoints). For this cell which is marked for duplication the logic duplication algorithm is run on each of its input pins. 
       FIG. 4  illustrates the steps in duplicate cell identification  121  of this example. Method  100  traverses backwards from output port of desA_aclk  231  and finds gate c 5   225  ( FIG. 1 ). Gate c 5   225  is a combinational cell and not driving any top level output and hence c 5   225  is marked for duplication. This is illustrated as step  1   241  in  FIG. 4 . The method next traverses backwards from the inputs of gate c 5   225  and finds gates c 3   223  and c 4   224 , which again being combinational cells are marked for duplication. This is step  2   242 . The inputs of c 4   224  are not parsed further since they are either driven by flip-flop D  214  or from primary port. 
     The inputs of c 3   223  are traversed. This finds the combinational cell c 2   222  and which is marked for duplication. The other input of c 3   223  is driven by flip-flop A  211  and is thus ignored. This is also step  2   242  in  FIG. 4 . 
     The inputs of c 2   222  inputs are traversed. This locates combinational cell c 1   221  which is marked for duplication. The other input of c 2   222  is driven by flip-flop C and is thus ignored. This is step  3   243  in  FIG. 4 . 
     The inputs of c 1   221  are traversed. It is determined that these inputs are driven by respective flip-flops A  211  and B  212 . This ends the recursive search for that particular output. This is marked as step  4   244 . 
     Method  100  next duplicates the logic hierarchy creation in step  122 . A new hierarchy desA_bclk_duplicates  251  ( FIG. 5 ) is created within desA_aclk  231  containing the cells marked for duplication. At the top level, a new instance of these cells  252  is created with desA_bclk_duplicates as the reference name. Duplicates  252  contains all the cells that have been duplicated. The cells within the newly created hierarchy at top level are already connected to each other. Those pins of the cells that are driven by aclk flip-flops become the ports of the newly created hierarchy. The intermediate results are illustrated in  FIG. 5 . 
     New hierarchy connections step  123  compares the ports of desA_aclk  231  and desA_bclk_duplicates  250  and prepares following lists. The list $new_hier_only_in_ports includes the input ports of desA_bclk_duplicates  252  which are not ports of desA_aclk  231 . In this example, these ports are the inputs of c 1   221 , c 2   222 , c 3   223  and c 4   224 . New ports are created for these inputs at the desA_aclk level and connections made. For these the net name will be same as the port name. Connections are made at the top level from each newly created ports of desA_aclk  231  to the corresponding port of desA_bclk_duplicates  252 . The list $new_hier_comm_in_ports includes the input ports of desA_bclk_duplicates  251  which are ports of desA_aclk  231 . Connections are made at the top level from each existing port of desA_aclk  231  to the corresponding port of desA_bclk_duplicates  252 . The list $new_hier_comm_out_ports includes the output ports of desA_bclk_duplicates  252  which are output ports of desA_aclk  231 . In our example, this is the output pin of c 5   225 . The output port from desA_aclk  231  is disconnected at top-level from the bclk flip-flop (dashed line  267  in  FIG. 6 ) and connected to the corresponding output port of desA_bclk_duplicates.  FIG. 6  illustrates lines  261 ,  262 ,  263 ,  264 ,  265  and  266  forming these new connections. The intermediate result is illustrated in  FIG. 6 . 
     Method  100  next implements redundant logic removal step  124 . The output after the duplicate hierarchy creation step  123  is functionally equivalent to our final desired output. However, duplicate hierarchy creation step  123  has cloned logic gates from desA_aclk  231  to desA_bclk_duplicates  252  and in the process created several logic gates in desA_aclk which are redundant and can be optimized. A simple top down compile gets rid of unused logic yielding the final netlist which meets our initial partition goals. This is shown in  FIG. 7 . Note that gates c 3   223 , c 4   224  and c 5   225  are determined to be redundant and removed at respective deletions  271 ,  272  and  273 . 
     Method  100  next performs level shifters and isolation cell insertion step  225 . Following logic duplication step, the newly created hierarchy desA_aclk contains aclk logic and bclk logic. The bclk logic is wholly at the top level. Level shifter cells  281 ,  282 ,  283  and  284  are inserted at the interface of desA_aclk boundary for all outputs of desA_aclk driving into bclk domain. Isolation cells such as isolation cell  291  are inserted at the interface of desA_aclk boundary for all inputs of desA_aclk being driven from bclk domain. This is illustrated in  FIG. 8 . 
     Method  100  creates a new logical hierarchy desA_aclk which will be mapped to V DD  voltage domain. The rest of the logic, which includes logic at top level and within desA_bclk_duplicates, will be mapped to V DD1  voltage domain. 
     Level shifter and isolation cell insertion step  125  inserts level shifters and isolation cells at all crossings between these voltage domains. Level shifter and isolation cell checks step  131  validates the entire partition methodology. This employs two levels of checks. 
     Level shifter and isolation cell checks step  131  performs timing checks. The original goal was to create a partition desA_aclk such that: all timing paths from aclk to aclk are contained only within desA_aclk hierarchy; all timing paths from aclk to bclk pass through desA_aclk hierarchy only once; and all timing paths from bclk to aclk pass through desA_aclk hierarchy only once. These conditions are translated into the following checks. For all timing paths starting from aclk flip-flop and ending in aclk flip-flops, step  131  ensures that there are no level shifters along the path. For all timing paths starting from bclk flip-flops and ending in bclk flip-flops, step  131  ensures that there are no level shifters along the path. For all timing paths starting from aclk flip-flops and ending in bclk flip-flops, step  131  ensures that there is only one level shifter along the path. For all timing paths starting from bclk flip-flops and ending in aclk flip-flops, step  131  ensures that there is only one isolation cell along the path. These checks are performed by checking a comprehensive list of timing paths for each category for presence of the correct type of cell. 
     Level shifter and isolation cell checks step  131  also performs structural checks. Structural checks are preferably performed using a third party power management tool. Specified inputs to this tool include the domain definitions and association with hierarchies. For the V DD  domain the hierarchy is desA_aclk. For the V DD1  domain the hierarchy is the rest of desA. Specified inputs to this tool include the power management cell types including the level shifters and isolation cells. Specified inputs to this tool include the voltage values for domains and rail voltage values for level shifter/isolation cell input and output pins. The tool checks the structure of the netlist to see if all level shifters and isolation cells are inserted at the power crossings.