Abstract:
A circuit designer may use computer-aided design (CAD) tools to implement an integrated circuit design. The CAD tools may include auto-pipelining capabilities to improve the performance of the integrated circuit design. Auto-pipelining may modify the number of pipeline registers in a path within a given range. A description of the integrated circuit design may include different implementation alternatives of a path each having a different number of pipeline registers, and the CAD tools may select one of these implementation alternatives. The CAD tools may further evaluate the performance of a particular implementation alternative and iteratively select a different implementation alternative until a given objective is met. The CAD tool may update a test environment according to the selected implementation alternative once the objective is met and validate the selected implementation alternative using the updated test environment.

Description:
BACKGROUND 
       [0001]    This invention relates to integrated circuit design and, more particularly, to verifiable automatic register pipelining of integrated circuit design descriptions at the register transfer level (RTL). 
         [0002]    Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which has led to performance increases. However, more recent technology nodes have seen a significant slow-down in the reduction of delays and thus a slow-down in the performance increase. 
         [0003]    Solutions such as register pipelining have been proposed to further increase the performance. During register pipelining, additional registers are inserted between synchronous elements, which lead to an increase in latency at the benefit of increased clock frequencies and throughput. However, performing register pipelining often involves spending significant time and effort because several iterations of locating performance bottlenecks, inserting or removing registers, and compiling the modified integrated circuit design are usually required. 
         [0004]    Situations frequently arise where a register pipelined integrated circuit design still exhibits an unsatisfactory performance after many iterations of inserting or removing registers because adding a pipeline register to a given path in a current iteration may obsolete the effects of having added a register to a different path during a prior iteration. 
         [0005]    The difficulty of performing register pipelining is further exacerbated by the facts that the latency in different paths or blocks may be related, that certain conditions such as reset removal may be latency dependent, and that verification related activities such as simulation may need to consider modifications to a test bench and a design-under-test (DUT) caused by register pipelining. 
       SUMMARY 
       [0006]    A design automation tool implemented on computing equipment to develop a circuit design for an integrated circuit may receive a command that defines a valid range for a number of pipeline registers and a circuit description that includes two implementations of a path. A first implementation of the path may include a first number of pipeline registers within the valid range, and a second implementation of the path may include a second number of pipeline registers. The circuit description may initially select the first implementation of the path. The design automation tool may still further select the second implementation of the path and record the selection of the second implementation of the path. 
         [0007]    It is appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or instructions on a computer readable medium. Several inventive embodiments of the present invention are described below. 
         [0008]    In certain embodiments, the above mentioned circuit description may select the first implementation of the path using a parameter that defines a default value and record the selection of the second implementation of the path by updating the parameter. 
         [0009]    If desired, the design automation tool may update a test bench. For example, the test bench may verify the circuit description with the second implementation instead of the first implementation of the path. The test bench may be updated using the recorded selection of the second implementation of the path. Additionally, a simulator tool may perform a simulation using the updated test bench, the circuit description, and the recorded selection. 
         [0010]    Further features of the invention, its nature and various advantages, will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a diagram of a circuit design system that may be used to design integrated circuits in accordance with an embodiment. 
           [0012]      FIG. 2  is a diagram of illustrative computer-aided design (CAD) tools that may be used in a circuit design system in accordance with an embodiment. 
           [0013]      FIG. 3  is a flow chart of illustrative steps for designing an integrated circuit in accordance with an embodiment. 
           [0014]      FIG. 4  is a flow chart of illustrative steps for designing an integrated circuit with auto-pipelining capabilities in accordance with an embodiment. 
           [0015]      FIG. 5  is a flow chart of illustrative steps for optimizing an integrated circuit with auto-pipelining capabilities in accordance with an embodiment. 
           [0016]      FIG. 6  is a diagram of an illustrative portion of an integrated circuit that receives signals from two register pipeline paths in accordance with an embodiment. 
           [0017]      FIG. 7  is a diagram of an illustrative path that includes two register pipelines separated by combinational logic in accordance with an embodiment. 
           [0018]      FIG. 8  is a flow chart of illustrative steps for performing auto-pipelining on a circuit design that includes a parallel multi-bit interconnection in accordance with an embodiment. 
           [0019]      FIG. 9  is a diagram of illustrative parallel paths with pipeline registers between combinational logic in accordance with an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Embodiments of the present invention relate to methods for using computer-aided design (CAD) tools, which are sometimes also referred to as design automation (DA) tools or electronic design automation (EDA) tools, for optimizing integrated circuit (IC) designs with register pipelining capabilities for implementation as integrated circuits. The integrated circuits may be any suitable type of integrated circuit, such as microprocessors, application-specific integrated circuits, digital signal processors, memory circuits, etc. If desired, the integrated circuits may be programmable integrated circuits that can be configured by a user to perform the functionality described in the integrated circuit design using programmable circuitry. The programmable circuitry can be configured by adjusting the settings of memory elements. 
         [0021]    Register pipelining refers to the process of inserting or removing a register between synchronous elements of an integrated circuit design. For instance, inserting a register between two synchronous elements of an integrated circuit design increases the latency between those two synchronous elements for the benefit of potentially increased clock frequencies and throughput. Register pipelining is a complicated design optimization method that may be very time consuming and expensive to implement as shown in the background section. Therefore, it would be desirable to automate the process of register pipelining in all design steps that may be affected by register pipelining (e.g., simulation). 
         [0022]    It will be obvious to one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments. 
         [0023]    An illustrative circuit design system  100  in accordance with the present invention is shown in  FIG. 1 . System  100  may be based on one or more processors such as personal computers, workstations, etc. The processor(s) may be linked using a network (e.g., a local or wide area network). Memory in these computers or external memory and storage devices such as internal and/or external hard disks may be used to store instructions and data. 
         [0024]    Software-based components such as computer-aided design tools  120  and databases  130  reside on system  100 . During operation, executable software such as the software of computer aided design tools  120  runs on the processor(s) of system  100 . Databases  130  are used to store data for the operation of system  100 . In general, software and data may be stored on any computer-readable medium (storage) in system  100 . Such storage may include computer memory chips, removable and fixed media such as hard disk drives, flash memory, compact discs (CDs), digital versatile discs (DVDs), blu-ray discs (BDs), other optical media, and floppy diskettes, tapes, or any other suitable memory or storage device(s). When the software of system  100  is installed, the storage of system  100  has instructions and data that cause the computing equipment in system  100  to execute various methods (processes). When performing these processes, the computing equipment is configured to implement the functions of the circuit design system. 
         [0025]    The computer aided design (CAD) tools  120 , some or all of which are sometimes referred to collectively as a CAD tool or an electronic design automation (EDA) tool, may be provided by a single vendor or by multiple vendors. Tools  120  may be provided as one or more suites of tools (e.g., a compiler suite for performing tasks associated with implementing a circuit design in a programmable logic device) and/or as one or more separate software components (tools). Database(s)  130  may include one or more databases that are accessed only by a particular tool or tools and may include one or more shared databases. Shared databases may be accessed by multiple tools. For example, a first tool may store data for a second tool in a shared database. The second tool may access the shared database to retrieve the data stored by the first tool. This allows one tool to pass information to another tool. Tools may also pass information between each other without storing information in a shared database if desired. 
         [0026]    Illustrative computer aided design tools  220  that may be used in a circuit design system such as circuit design system  100  of  FIG. 1  are shown in  FIG. 2 . 
         [0027]    The design process may start with the formulation of functional specifications of the integrated circuit design (e.g., a functional or behavioral description of the integrated circuit design). A circuit designer may specify the functional operation of a desired circuit design using design and constraint entry tools  264 . Design and constraint entry tools  264  may include tools such as design and constraint entry aid  266  and design editor  268 . Design and constraint entry aids such as aid  266  may be used to help a circuit designer locate a desired design from a library of existing circuit designs and may provide computer-aided assistance to the circuit designer for entering (specifying) the desired circuit design. 
         [0028]    As an example, design and constraint entry aid  266  may be used to present screens of options for a user. The user may click on on-screen options to select whether the circuit being designed should have certain features. Design editor  268  may be used to enter a design (e.g., by entering lines of hardware description language code), may be used to edit a design obtained from a library (e.g., using a design and constraint entry aid), or may assist a user in selecting and editing appropriate prepackaged code/designs. 
         [0029]    Design and constraint entry tools  264  may be used to allow a circuit designer to provide a desired circuit design using any suitable format. For example, design and constraint entry tools  264  may include tools that allow the circuit designer to enter a circuit design using truth tables. Truth tables may be specified using text files or timing diagrams and may be imported from a library. Truth table circuit design and constraint entry may be used for a portion of a large circuit or for an entire circuit. 
         [0030]    As another example, design and constraint entry tools  264  may include a schematic capture tool. A schematic capture tool may allow the circuit designer to visually construct integrated circuit designs from constituent parts such as logic gates and groups of logic gates. Libraries of preexisting integrated circuit designs may be used to allow a desired portion of a design to be imported with the schematic capture tools. 
         [0031]    If desired, design and constraint entry tools  264  may allow the circuit designer to provide a circuit design to the circuit design system  100  using a hardware description language such as Verilog hardware description language (Verilog HDL) or Very High Speed Integrated Circuit Hardware Description Language (VHDL). The designer of the integrated circuit design can enter the circuit design by writing hardware description language code with editor  268 . Blocks of code may be imported from user-maintained or commercial libraries if desired. 
         [0032]    After the design has been entered using design and constraint entry tools  264 , behavioral simulation tools  272  may be used to simulate the functional performance of the circuit design. If the functional performance of the design is incomplete or incorrect, the circuit designer can make changes to the circuit design using design and constraint entry tools  264 . The functional operation of the new circuit design may be verified using behavioral simulation tools  272  before synthesis operations have been performed using tools  274 . Simulation tools such as behavioral simulation tools  272  may also be used at other stages in the design flow if desired (e.g., after logic synthesis). The output of the behavioral simulation tools  272  may be provided to the circuit designer in any suitable format (e.g., truth tables, timing diagrams, etc.). 
         [0033]    Once the functional operation of the circuit design has been determined to be satisfactory, logic synthesis and optimization tools  274  may generate a gate-level netlist of the circuit design, for example using gates from a particular library pertaining to a targeted process supported by a foundry, which has been selected to produce the integrated circuit. Alternatively, logic synthesis and optimization tools  274  may generate a gate-level netlist of the circuit design using gates of a targeted programmable logic device (i.e., in the logic and interconnect resources of a particular programmable logic device product or product family). 
         [0034]    Logic synthesis and optimization tools  274  may optimize the design by making appropriate selections of hardware to implement different logic functions in the circuit design based on the circuit design data and constraint data entered by the logic designer using tools  264 . 
         [0035]    After logic synthesis and optimization using tools  274 , the circuit design system may use tools such as placement and routing tools  276  to perform physical design steps (layout synthesis operations). Placement and routing tools  276  are used to determine where to place each gate of the gate-level netlist produced by tools  274 . For example, if two counters interact with each other, the placement and routing tools  276  may locate these counters in adjacent regions to reduce interconnect delays or to satisfy timing requirements specifying the maximum permitted interconnect delay. The placement and routing tools  276  create orderly and efficient implementations of circuit designs for any targeted integrated circuit (e.g., for a given programmable integrated circuit such as a field-programmable gate array (FPGA).) 
         [0036]    Tools such as tools  274  and  276  may be part of a compiler suite (e.g., part of a suite of compiler tools provided by a programmable logic device vendor). In accordance with the present invention, tools such as tools  274 ,  276 , and  278  automatically take into account the effects of crosstalk between interconnects while implementing a desired circuit design. Tools  274 ,  276 , and  278  may also include timing analysis tools such as timing estimators. This allows tools  274  and  276  to satisfy performance requirements (e.g., timing requirements) before actually producing the integrated circuit. 
         [0037]    After an implementation of the desired circuit design has been generated using placement and routing tools  276  the implementation of the design may be analyzed and tested using analysis tools  278 . After satisfactory optimization operations have been completed using tools  220  and depending on the targeted integrated circuit technology, tools  220  may produce a mask-level layout description of the integrated circuit or configuration data for programming the programmable logic device. 
         [0038]    Illustrative operations involved in using tools  220  of  FIG. 2  to produce the mask-level layout description of the integrated circuit are shown in  FIG. 3 . 
         [0039]    As shown in  FIG. 3 , a circuit designer may first provide a design specification  302 . The design specification  302  may, in general, be a behavioral description provided in the form of an application code (e.g., C code, C++ code, SystemC code, etc.). In some scenarios, the design specification may be provided in the form of a register transfer level (RTL) description  306 . The RTL description may have any form of describing circuit functions at the register transfer level. For example, the RTL description may be provided using a hardware description language such as the Verilog hardware description language (Verilog HDL or Verilog), the SystemVerilog hardware description language (SystemVerilog HDL or SystemVerilog), or the Very High Speed Integrated Circuit Hardware Description Language (VHDL). Alternatively, the RTL description may be provided as a schematic representation. 
         [0040]    In general, the behavioral design specification  302  may include untimed or partially timed functional code (i.e., the application code does not describe cycle-by-cycle hardware behavior), whereas the RTL description  306  may include a fully timed design description that details the cycle-by-cycle behavior of the circuit at the register transfer level. 
         [0041]    In certain embodiments, design specification  302  or RTL description  306  may include path descriptions for one or more paths in the design. These path descriptions may include multiple implementations of the path, and each path description may include a predetermined number of pipeline registers. 
         [0042]    In certain embodiments, design specification  302  or RTL description  306  may include pipeline optimization constraints such as number of registers in a pipeline (e.g., a legal range for the number of registers or a set of allowable discrete numbers of registers), latency, throughput, or any combination thereof. For example, the design specification or the RTL description may include several implementation alternatives for the given path and a parameter that initially selects one of the implementation alternatives. 
         [0043]    Design specification  302  or RTL description  306  may also include target criteria such as area use, power consumption, delay minimization, clock frequency optimization, or any combination thereof. The pipeline optimization constraints and target criteria may be collectively referred to as constraints. 
         [0044]    Those constraints can be provided for individual paths, portions of individual paths, portions of a design, or for the entire design. For example, the constraints may be provided with the design specification  302 , the RTL description  306  (e.g., as a pragma or as an assertion), in a constraint file, or through user input (e.g., using the design and constraint entry tools  264  of  FIG. 2 ), to name a few. In certain embodiments, a given path may have more than one constraint associated with the path, and some of these constraints may be in conflict with each other e.g., a constraint received with the behavioral design specification for a given path may conflict with the constraint received with the RTL description and with a constraint received with a constraint file. In this scenario, a predetermined priority of constraints, which may be defined explicitly or resolved implicitly by CAD tools  220 , may determine which of the conflicting constraints is selected. For example, the constraint from the user or a configuration file may override the constraints received from other sources, and a constraint received with the RTL description may override a constraint received with the behavioral design specification. 
         [0045]    The constraints may target the entire circuit design or portions of the circuit design. For example, some constraints may be defined globally and thus be applicable to the entire circuit design. Other constraints may be assigned locally and thus be applicable only to the corresponding portions of the circuit design. Consider the scenario in which the circuit design is organized hierarchically. In this scenario, every hierarchical instance may include different assignments. In other words, multiple different constraints may target the same portion of the circuit design, and priorities may be defined explicitly or resolved implicitly by CAD tools  220 . For example, a constraint defined at a higher level of the design hierarchy may override a constraint at a lower level. Alternatively, a constraint defined at a lower level of the design hierarchy may override a constraint at a higher level, or individual levels of the design hierarchy may be given priority over other levels of design hierarchy. 
         [0046]    If desired, constraints may relate to each other. For example, a first constraint that specifies a first legal range for a number of registers in a first pipeline k may relate to a second constraint that specifies a second legal range for a number of registers in a second pipeline m. As an example, the first pipeline may have between one and five registers (i.e., 1&lt;=k&lt;=5) and the second pipeline may have between the number of registers in the first pipeline and five registers (i.e., k&lt;=m&lt;=5). 
         [0047]    Constraints included in design specification  302  or RTL description  306  may be conveyed to CAD tools  220  in the form of variables, parameters, compiler directives, macros, pragmas, or assertions, just to name a few. CAD tools  220  may use a constraint file, which may include a portion or all of the constraints. Such a constraint file may be included with design specification  302  or RTL description  306 . In some scenarios, a portion or all of the constraints may be embedded in the circuit design. Alternatively, the constraints may have been defined using the design and constraint entry tools  264  (see  FIG. 2 ). 
         [0048]    At step  304 , behavioral synthesis (sometimes also referred to as algorithmic synthesis) may be performed to convert the behavioral description into an RTL description  306 . Behavioral synthesis may select target path implementations for each of the paths in the behavioral design specification. Each selected target path implementation may be selected based on the pipeline optimization constraints and the target criteria of the design. Step  304  may be skipped if the design specification is already provided in form of an RTL description. 
         [0049]    At step  318 , behavioral simulation tools  272  may perform an RTL simulation of the RTL description, which may verify the functional performance of the RTL description. If the functional performance of the RTL description is incomplete or incorrect, the circuit designer can make changes to the HDL code (as an example). During RTL simulation  318 , actual results obtained from simulating the behavior of the RTL description may be compared with expected results. Consider again the scenario where the circuit design includes several implementation alternatives for a given path and a parameter that initially selects one of the implementation alternatives. In this scenario, the expected results may depend on the selected parameter setting for the target path implementation and provide different expected results based on this parameter setting and the corresponding selected target path implementation. The selected parameter setting for the target path implementation may be communicated to the CAD tools such that the selected number of registers in each target path implementation is reflected in the expected results. 
         [0050]    During step  308 , logic synthesis operations may generate gate-level description  310  using logic synthesis and optimization tools  274  from  FIG. 2 . If desired, logic synthesis operations may add or remove pipeline registers in selected paths according to the constraints that are included in design specification  302  or RTL description  306 . During step  312 , physical synthesis operations (e.g., place and route and optimization operations using for example placement and routing tools  276 ) may place and connect the different gates in gate-level description  310  in a preferred location on the targeted integrated circuit to meet given target criteria (e.g., minimize area and maximize routing efficiency or minimize path delay and maximize clock frequency or any combination thereof). Physical synthesis operation may add or remove registers in selected paths according to the constraints that are included in design specification  302  or RTL description  306 . The output of physical synthesis  312  is a mask-level layout description  316 . 
         [0051]    Circuit design system  100  may include timing estimator  314  (e.g., formed as part of optimization tools  274 , tools  276 , or tools  278 ) that may be used to estimate delays between synchronous elements of the circuit design. For example, timing estimator  314  may estimate delays between registers (e.g., based on the lengths of interconnects, intermediate combinational logic, etc.). The delays may, if desired, be estimated based on metrics such as slack (e.g., the difference between a required arrival time and the arrival time of a signal), slack-ratios, interconnect congestion, or other timing metrics. Circuit design system  100  may use the estimated delays to determine the locations of groups of circuitry while helping to ensure that delays satisfy timing requirements (e.g., critical path delay requirements) or other performance constraints. 
         [0052]    Timing estimator  314  may be configured to produce estimated delays that include adjustments for register pipelining. For example, paths that include register pipelining may be assigned an estimated delay value based on the number of registers used for register pipelining in that particular path (e.g., the estimated delay value may be calculated by dividing a delay value estimated for the path without register pipelining by the number of registers used for register pipelining). 
         [0053]    Consider the scenario in which a circuit design has a given path for which a maximum register pipeline depth and a minimum register pipeline depth have been defined. Consider further that the given path misses one or more target criteria. For example, timing estimator  314  may determine that a given path has a delay that is larger than the target delay specified for the path as one of the target criteria. Timing estimator  314  may detect that the given path has a larger delay before, during, and after logic synthesis  308  or before, during, and after physical synthesis  312 , which may include operations such as clustering, partitioning, placement, and routing, just to name a few. In this scenario and under the condition that the current register pipeline depth is smaller than the maximum register pipeline depth, logic synthesis  308  or physical synthesis  312  may add a register into the path, thereby increasing the register pipeline depth and potentially improving the performance of the given path. 
         [0054]    Similarly, consider that the given path meets all target criteria with a large margin. For example, timing estimator  314  may determine that a given path has a delay that is smaller than the target delay specified for the path as one of the target criteria. In this scenario and under the condition that the current register pipeline depth is greater than the minimum register pipeline depth, logic synthesis  308  or physical synthesis  312  may remove a register from the path, thereby decreasing the register pipeline depth and reducing the latency in the given path. 
         [0055]    A flow chart of illustrative steps for designing an integrated circuit with auto-pipelining capabilities is shown in  FIG. 4 . A circuit description containing a path description for a path including a plurality of path implementations is received during step  410 . Each of the plurality of path implementations is associated with a predetermined number of pipeline registers. At step  420 , a constraint defining one or more target criteria for the path may be received. A constraint defining one or more pipeline optimization constraints for the path may be received at step  430 . CAD tools such as logic synthesis and optimization tools  274  or placement and routing tools  276  from  FIG. 2  may select one of the plurality of path implementations as a target implementation of the path during step  440  and communicate the selected target path implementation during step  450  to the user, a CAD tool, or both. During step  460 , simulation tools such as behavioral simulation tools  272  of  FIG. 2  may perform a simulation using the circuit description and the selected target path implementation. 
         [0056]    The performance of the circuit description with the selected path (e.g., determined during timing analysis with analysis tools  278  of  FIG. 2 ) may miss given performance objectives thereby indicating a need for further optimizations. Illustrative steps for optimizing a circuit design with auto-pipelining capabilities are shown in  FIG. 5 . 
         [0057]    During step  510 , a circuit description with two or more paths may be received. Each path may have an initial number of registers and a predetermined set that contains allowable numbers of registers. 
         [0058]    Changing the number of registers in one path may require changing the number of registers in a second path thereby limiting the selection for the number of registers in that second path. Consider the scenario in which two paths feed the same combinational logic as illustrated in  FIG. 6 . A first signal may be produced by combinational logic  640  and propagate to combinational logic  660  through a first register pipeline in a first path having registers  610 A to  610 B. In combinational logic  660 , this first signal may be combined with a second signal that was produced by combinational logic  650  and propagated through a second register pipeline in a second path having registers  610 C to  610 D. 
         [0059]    Adding a register to the first register pipeline (e.g., between registers  610 A and  610 B) requires adding a register to the second register pipeline as well (and vice versa) to enable the combination of the first and second signals produced by combinational logic  640  and  650 , respectively, in combinational logic  660 . Similarly, removing a register from the first register pipeline requires removing a register from the second pipeline (and vice versa). 
         [0060]    In a different scenario, two paths each having a register pipeline may be arranged in series as illustrated in  FIG. 7 . In this scenario, a first signal produced by combinational logic  732  may be propagated through the first register pipeline in the first path having registers  720 A to  720 B. This first signal may be combined with other signals in combinational logic  734  and produce a second signal, which may be propagated through the second register pipeline in the second path having registers  720 C to  720 D to combinational logic  736 . Consider further that the total number of registers between combinational logic  732  and combinational logic  736  is required to be constant (e.g., the combined path may have a given latency requirement due to some industry standard). 
         [0061]    In this scenario, adding a register to the first register pipeline (e.g., between registers  720 A and  720 B) requires removing a register from the second register pipeline as well (and vice versa). Similarly, removing a register from the first register pipeline requires adding a register to the second register pipeline (and vice versa). 
         [0062]    In an alternative scenario, two or more paths may share at least a portion of a register pipeline (i.e., each of the two or more paths may pass through the same registers). This alternative scenario may be reduced to a scenario in which two or more paths are arranged in parallel and feed (or are fed by) the same nodes (i.e., the shared register pipeline) and all of these paths being arranged in series with the shared register pipeline. Thus, adding a register to one of the parallel paths requires adding a register to all other parallel paths, and removing a register from one of the parallel paths requires removing a register from all other parallel paths. Similarly, adding a register to the shared register pipeline or to all parallel paths may require removing a register from each of the parallel paths or the shared register pipeline if the total number of registers in each of the combined paths needs to be constant. Accordingly, removing a register from the shared register pipeline or all parallel paths may require adding a register to each of the parallel paths or the shared register pipeline if the total number of registers in each of the combined paths needs to be constant. 
         [0063]    After receiving the circuit description with the two paths and the set of allowable numbers of registers during step  510  of  FIG. 5 , the selection for the number of registers based on the sets of allowable numbers of registers may require further limitations. For example, in the event that the two paths feed the same logic as checked during step  512  (and illustrated above in connection with  FIG. 6 ) or in the event the two paths are in series as checked during step  516  (and illustrated above in connection with  FIG. 7 ) the selection of the number of registers may be limited accordingly during step  514 . 
         [0064]    During step  520 , a different number of registers may be selected for one or both paths. This selection may be based on the initial number of registers, the sets of allowable numbers of registers, and the eventual limitation determined during step  514 . A different circuit description including the modified paths may be created during step  530 . 
         [0065]    During steps  540 A and  540 B, the different circuit description and the circuit description with the initial number of registers in each path may be compiled, respectively (e.g., using CAD tools  220  of  FIG. 2 ). Performance results for the two compiled circuit descriptions may be determined during steps  550 A and  550 B, respectively (e.g., using analysis tools  278  of  FIG. 2 ). 
         [0066]    During step  565 , the two circuit descriptions may be ranked (e.g., based on the performance results determined during steps  550 A and  550 B), and one of the two circuit descriptions may be selected during step  570  (e.g., based on the ranking determined during step  565 ). 
         [0067]    If desired, the optimization may be performed in multiple iterations. In this case, the selected circuit description replaces the circuit description with the initial number of registers in each path and the next iteration starts with step  510 . 
         [0068]    A circuit design that includes a multi-bit interconnection may be optimized through auto-pipelining as illustrated in  FIG. 8 . An illustrative diagram of such a multi-bit interconnection with pipeline registers is shown in  FIG. 9 . Combinational logic  942  is connected with combinational logic  944  through an N-bit interconnection. Each bit of the N-bit interconnection may have a register pipeline. For example, the first bit of the N-bit interconnection may have registers  910 A to  910 B, the second bit may have registers  910 C to  910 D, etc. until the last bit, which may have registers  910 E to  910 D. 
         [0069]    As shown previously in the context of  FIG. 6 , an addition of a register to any of the N-bit interconnections may require the addition of a register to all other (N-1)-bit interconnections. Similarly, the removal of a register from any of the N-bit interconnections may require the removal of a register from all other (N-1)-bit interconnections. 
         [0070]    A CAD tool such as one of CAD tools  220  of  FIG. 2  (e.g., logic synthesis and optimization tools  274  or placement and routing tools  276 ) may receive a circuit description including a parallel multi-bit interconnection with a latency range limit on at least one interconnection of the multi-bit interconnection during step  842  of  FIG. 8 . At step  844 , an analysis tool (e.g., one of analysis tools  278  of  FIG. 2 ) may measure the performance of the received circuit description. 
         [0071]    During step  846 , a decision as to whether performance improvements are required may be made based on the measured performance results. In response to deciding that a performance improvement is required, the CAD tool may determine whether the current pipelining is below the upper latency limit (i.e., whether a register can be added to the current register pipeline) during step  852 . A decision may be made based on step  852  during step  862 . In response to deciding that the current pipelining is below the upper latency limit, the CAD tool may insert a register into each interconnection, record the register insertion, and measure performance results at step  864  before returning to step  846 . Steps  846 ,  852 ,  862 , and  864  may be repeated iteratively for as long as performance improvements are required and the current pipelining is below the upper latency limit. 
         [0072]    In the event that no performance improvements are required, the CAD tool may decide whether performance relaxation may be desired during step  848 . In response to deciding that a performance relaxation is desired (e.g., in an effort to decrease area), the CAD tool may determine whether the current pipelining is above the lower latency limit (i.e., whether a register can be removed from the current register pipeline) and whether there is at least one register in each interconnection during step  854 . A decision may be made based on step  854  during step  856 . In response to deciding that the current pipelining is above the lower latency limit and each interconnection has at least one register, the CAD tool may remove a register from each interconnection, record the register removal, and measure performance results at step  858  before returning to step  848 . Steps  848 ,  854 ,  856 , and  858  may be repeated iteratively for as long as performance relaxation is desired, the current pipelining is above the lower latency limit, and each interconnection has at least one register. 
         [0073]    The optimization of the circuit description with the multi-bit interconnection may terminate in response to deciding that no performance relaxation is required during step  848 , or that the current pipelining is not above the lower latency limit or that not all interconnections have at least one register during step  856 , or that the current pipelining is not below the upper latency limit during step  862 . Upon terminating the optimization of the circuit description, a simulator tool such as one of behavioral simulation tools  272  of  FIG. 2  may optionally simulate the circuit description with the recorded register insertions and/or register removals during step  868 . 
         [0074]    The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. The foregoing embodiments may be implemented individually or in any combination. 
         [0075]    The method and apparatus described herein may be incorporated into any suitable integrated circuit or system of integrated circuits. For example, the method and apparatus may be incorporated into numerous types of devices such as microprocessors or other ICs. Exemplary ICs include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPGAs), electrically programmable integrated circuits (EPLDs), electrically erasable programmable integrated circuits (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), just to name a few. 
         [0076]    The programmable integrated circuit described herein may be part of a data processing system that includes one or more of the following components; a processor; memory; I/O circuitry; and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable integrated circuit can be used to perform a variety of different logic functions. For example, the programmable integrated circuit can be configured as a processor or controller that works in cooperation with a system processor. The programmable integrated circuit may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable integrated circuit can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable integrated circuit may be one of the families of devices owned by the assignee. 
         [0077]    Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way. 
         [0078]    The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. The foregoing embodiments may be implemented individually or in any combination.