Abstract:
An improved high-voltage process is disclosed. In order to improve the performance in terms of breakdown voltage and to maintain the integrity of the STI structures, the thick gate oxide layer of the high-voltage device area is not etched back before a high-dosage ion doping process. One photo mask is therefore omitted.

Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates generally to the field of semiconductor fabrication and, more particularly, to a method of fabricating high-voltage metal-oxide-semiconductor (MOS) devices. 
   2. Description of the Prior Art 
   Integrated circuits (ICs) containing both high-voltage and low-voltage devices such as high/low voltage MOS transistor devices are known in the art. For example, the low-voltage device may be used in the control circuits as the high-voltage device may be used in electrically programmable read only memory (EPROM) or the driving circuits of the liquid crystal display devices. 
   Please refer to  FIG. 1  to  FIG. 7 .  FIGS. 1 to 7  are schematic, cross-sectional diagrams illustrating a method of fabricating a high-voltage NMOS device in accordance with the prior art. As shown in  FIG. 1 , a semiconductor substrate  10  is provided. The high-voltage NMOS device is formed within the high-voltage P well (HVPW)  12 . Shallow trench isolation (STI) structures  14  and  16  are formed in the semiconductor substrate  10 . The STI structure  14  defines a high-voltage device area  102 , which is further divided into two sub-areas  104  and  106  by STI structure  16 . 
   As shown in  FIG. 2 , an ion implantation process is carried out to form an N grade diffusion region  20  within the HVPW  12 . Subsequently, a pad oxide layer  22  and a pad nitride layer  24  are formed on the surface of the semiconductor substrate  10 . 
   As shown in  FIG. 3 , the entire high-voltage device area  102  is exposed by selectively etching away the pad oxide layer  22  and the pad nitride layer  24  within the high-voltage device area  102 . As shown in  FIG. 4 , a thick oxide layer  42  (about 850 angstroms for 32V or 42V device) is grown on the exposed semiconductor substrate  10  including sub-areas  104  and  106 . 
   As shown in  FIG. 5 , a polysilicon gate  52  is patterned on the thick oxide layer  42  of the sub-area  104 . The polysilicon gate  52  laterally extends to the STI structure  16 . 
   According to the prior art, a photo-mask is then employed to define a photoresist layer (not shown) over the semiconductor substrate  10 . The photoresist layer is used to protect the semiconductor substrate  10  except the high-voltage device area  102 . Using the photoresist layer and the polysilicon gate as a hard mask, a dry etching process is performed to etch the thick oxide layer  42 . 
   As shown in  FIG. 6 , when removing the thick oxide layer  42  within the high-voltage device area  102 , which is not covered by the polysilicon gate  52 , recessed areas  64  and  66  with hundreds of angstroms are simultaneously formed in the STI structures  14  and  16 , respectively. 
   As shown in  FIG. 7 , an N+ doping process is carried out to form, within the sub-area  104 , an N+ region  72  next to the polysilicon gate  52 , and to form, within the sub-area  106 , an N+ region  74 . The aforementioned recessed areas  64  and  66  adversely affect the doping profile of the N+ regions  72  and  74  as well as the performance of the high-voltage device. As specifically indicated in  FIG. 7 , through the recessed areas  64  and  66 , the N+ doping process also creates downwardly extended tails  72   a  and  74   a . As a result, the N+ region  74  is close to the junction  78  between the HVPW  12  and the N grade diffusion region  20 , and the breakdown voltage of the high-voltage device is therefore decreased. 
   In light of the above, there is a need in this industry to provide an improved method for fabricating high-voltage MOS devices. 
   SUMMARY OF INVENTION 
   It is therefore a primary object of the present invention to provide a method of fabricating high-voltage metal-oxide-semiconductor (MOS) devices, which is capable of solving the aforementioned problems. 
   Another object of the present invention is to provide a method of fabricating high-voltage MOS devices, which is compatible with low-voltage process. 
   According to the claimed invention, a method of fabricating a high-voltage metal-oxide-semiconductor (MOS) device includes the steps of: 
   (1) providing a semiconductor substrate comprising a high-voltage device area thereon and shallow trench isolation (STI) structure that further divides the high-voltage device area into a first sub-area and a second sub-area; 
   (2) implanting ions into the semiconductor substrate within the high-voltage device area to form a first doping region and a second doping region with a channel region defined therebetween; 
   (3) forming a pad oxide layer on the semiconductor substrate; 
   (4) depositing a pad nitride layer on the pad oxide layer; 
   (5) forming an opening in the pad nitride layer and the pad oxide layer, wherein the opening merely exposes a portion of the first sub-area of the high-voltage device area including the channel region; 
   (6) growing a first oxide layer on exposed the semiconductor substrate via the opening; 
   (7) stripping off remaining the pad nitride layer and the pad oxide layer; 
   (8) growing a second oxide layer on the first sub-area and on the second sub-area; 
   (9) forming a gate on the first oxide layer; and 
   (10) performing an ion implantation process, using the gate and the first oxide layer as an implant mask, to form a third doping region within the first doping region and a fourth doping region within the second doping region. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIGS. 1 to 7  are schematic, cross-sectional diagrams illustrating a method of fabricating a high-voltage MOS device in accordance with the prior art. 
       FIGS. 8 to 14  are schematic, cross-sectional diagrams illustrating a method of fabricating a high-voltage MOS device in accordance with one preferred embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   The present invention pertains to a high-voltage semiconductor process that is compatible with low-voltage process. One preferred embodiment of the present invention will be explained in detail with reference to  FIGS. 8 to 14 , wherein like elements, regions or layers are designated with like numerals. It is to be understood that the present invention is suited for NMOS, PMOS, and CMOS processes, although only exemplary NMOS process steps are demonstrated. 
   Please refer to  FIGS. 8 to 14 .  FIGS. 8 to 14  are schematic, cross-sectional diagrams illustrating a method of fabricating a high-voltage NMOS device in accordance with one preferred embodiment of the present invention. As shown in  FIG. 8 , a semiconductor substrate  10  is provided. The high-voltage NMOS device is formed within the high-voltage P well (HVPW)  12  of the semiconductor substrate  10 . Shallow trench isolation (STI) structures  114 ,  14  and  16  are formed in the semiconductor substrate  10 . The STI structure  114  is used to define a low-voltage device area  100 . The STI structure  14  is used to define a high-voltage device area  102 , which is further divided into two sub-areas  104  and  106  by STI structure  16 . A low-voltage device is to be formed within the low-voltage device area  100 . A high-voltage device is to be formed within the high-voltage device area  102 . A channel region and one source/drain region of the high-voltage device will be formed within the sub-area  104 , while the other source/drain region of the high-voltage device will be formed within the sub-area  106 . 
   As shown in  FIG. 9 , an ion implantation process is carried out to form spaced-apart N grade diffusion regions  20   a  and  20   b  within the HVPW  12 . Between the N grade diffusion region  20   a  and N grade diffusion region  20   b  is channel region  90 . The N grade diffusion region  20   a  borders the STI structure  16  and extends to the sub-area  104 . Subsequently, a pad oxide layer  22  and a pad nitride layer  24  are formed on the surface of the semiconductor substrate  10 . 
   As shown in  FIG. 10 , a lithographic and etching process is performed to form an opening  224  in the pad oxide layer  22  and pad nitride layer  24 , which merely exposes the channel region  90  and a portion of the N grade diffusion region  20   b  within the high-voltage device area  102 . At this phase, the sub-area  106  of the high-voltage device area  102  and the entire low-voltage device area  100  are still covered by the pad nitride layer  24 . 
   As shown in  FIG. 11 , a thermal process is performed. A thick gate oxide layer  42  is grown on the exposed semiconductor substrate  10  via the opening  224 . The thickness of the thick gate oxide layer  42  may be between 700 and 900 angstroms, for example, 850 angstroms. The thick gate oxide layer  42  covers the channel region  90  and a portion of the N grade diffusion region  20   b  that is adjacent to the channel region  90 . 
   As shown in  FIG. 12 , the remaining pad oxide layer  22  and pad nitride layer  24  are stripped off to expose the sub-area  106 , the low-voltage device area  100 , and the rest of the N grade diffusion region  20   b  within the sub-area  104 . Thereafter, another thermal process is carried out to grow a thin gate oxide layer  146  within the low-voltage device area  100  and a thin gate oxide layer  46  within the high-voltage device area  102 . 
   As shown in  FIG. 13 , a polysilicon gate  52  is patterned on the thick gate oxide layer  42  of the sub-area  104 . The polysilicon gate  52  laterally extends to the STI structure  16 . Simultaneously, a polysilicon gate  152  is patterned on the thin gate oxide layer  146 . 
   Finally, as shown in  FIG. 14 , using the polysilicon gate  52  and the thick gate oxide layer  42  as an implant mask, an N+ doping process is then carried out to form, within the sub-area  104 , an N+ region  72  next to the thick gate oxide layer  42 , and to form, within the sub-area  106 , an N+ region  74 . Simultaneously, N+ regions  174  are formed in the low-voltage device area  100 . 
   The present invention at least comprises the following advantages over the prior art method. First, according to this invention, there is no need to etch back the thick gate oxide layer  42  before the N+ doping process. The present invention method avoids the formation of recessed areas in the STI structures, which, as stated supra, adversely affect the performance of the high-voltage device in terms of breakdown voltage. Secondly, the present invention method is more cost-effective since one photo mask (for etching the thick gate oxide layer) is omitted. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.