Abstract:
In a process for fabricating a nonvolatile semiconductor memory of the tunneling type, when tunnel windows are formed in an oxide film on a semiconductor substrate, the oxide film is etched first by a dry etching process, then by a wet etching process. The dry etching process quickly removes most of the oxide material in the window areas, without enlarging the windows laterally, but stops short of the substrate, thereby avoiding damage to the substrate surface. The wet etching process takes the windows the rest of the way down to the semiconductor substrate surface. Since only a small amount of oxide needs to be wet-etched, lateral enlargement of the windows by the wet etching process can be tightly controlled, and small tunnel windows can be formed without the need for extravagantly sophisticated fabrication equipment.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method of fabricating a nonvolatile semiconductor memory of the type that writes and erases data by electron tunneling.  
         [0003]     2. Description of the Related Art  
         [0004]     A memory cell in this type of memory has a floating gate electrode, a control gate electrode, a thin gate oxide film that insulates the floating gate electrode from the silicon substrate of the cell, and a still thinner tunnel oxide film occupying a window in the gate oxide film. Data are written and erased by moving electrons into and out of the floating gate electrode through the thin tunnel oxide film. Common examples of memories with this structure include electrically erasable and programmable read-only memories (EEPROM).  
         [0005]     The tunnel oxide film in an EEPROM of this type is generally fabricated by photolithography and oxidation in the following steps: an oxide film with a thickness slightly less than the desired thickness of the gate oxide film is formed on the substrate; a resist mask with an opening is formed; the oxide film is wet-etched through the opening with hydrofluoric acid or buffered hydrofluoric acid to form the tunnel window; the resist mask is removed; the exposed substrate is cleaned and then thermally oxidized, forming the tunnel oxide film at the bottom of the tunnel window.  
         [0006]     Wet etching has the advantage of not damaging the substrate surface, so that a tunnel oxide film of good quality can be formed. However, wet etching also has the disadvantage of being isotropic: etching proceeds laterally, parallel to the substrate, as well as forward toward the substrate, so that the tunnel window becomes larger than the opening in the resist mask. To form a tunnel window of a given size, it is therefore necessary to use photolithographic equipment with a significantly higher resolution than the window dimensions.  
         [0007]     EEPROM circuits and other circuits comprising metal-oxide-semiconductor (MOS) transistors are often combined in the same device, the EEPROM memory cells and the MOS transistors having similar dimensions. An ongoing trend in semiconductor fabrication technology is to shorten the gate length of MOS transistors to increase their operating speed. Since the floating and control gates in the EEPROM memory cells are similarly shortened, the size of the tunnel windows in the EEPROM must be reduced to match the gate length of the MOS transistors. Because of the lateral expansion of the tunnel windows during wet etching, it becomes necessary to use photolithographic equipment with a higher resolution than is needed to form the MOS transistors. This is costly and inefficient, but it would also be costly and inefficient to use two different photolithographic processes: one to form the MOS transistors, and another to form the tunnel windows.  
         [0008]     In an EEPROM fabrication method described in Japanese Patent Application Publication No. 2002-100688, for example, (paragraphs 0016-0018 and  FIG. 3 ), instead of a wet etching process, a dry anisotropic plasma etching process is used to form the tunnel windows. This enables tunnel windows to be created with the same dimensions as the openings in the resist mask, so higher-resolution photolithographic equipment is not needed, but plasma etching damages the substrate surface. The tunnel oxide film formed on the substrate surface is therefore of poor quality and is susceptible to dielectric breakdown, which allows unwanted charge to leak between the floating gate and substrate when an electric field is applied from the control gate.  
       SUMMARY OF THE INVENTION  
       [0009]     An object of the present invention is to provide a fabrication method that can form minute tunnel oxide films of good quality in a nonvolatile semiconductor memory without lowering the manufacturing efficiency.  
         [0010]     The invented method of fabricating a nonvolatile semiconductor memory includes the conventional steps of forming an oxide film on the surface of a silicon substrate and forming a resist mask with an opening defining each desired tunnel window on the oxide film, but the size of the opening is only slightly smaller than the design size of the tunnel window.  
         [0011]     Next, the oxide film is etched through the openings by an anisotropic dry etching process, using the resist mask as an etching mask. This anisotropic dry etching process stops short of the silicon substrate, preferably at least five nanometers short, so that it does not damage the substrate surface.  
         [0012]     A wet etching process is then performed with the same resist mask to remove the oxide film down to the surface of the substrate. Since only a small thickness of oxide remains to be etched, the wet etching process is completed quickly and only a small amount of lateral etching takes place. The wet etching process leaves an undisturbed substrate surface on which a tunnel oxide film of high quality can be formed.  
         [0013]     The invented fabrication method is efficient because the openings in the resist mask have nearly the same dimensions as the tunnel windows, and can be formed by a photolithographic process of the same resolution as used to form gate electrodes and other circuit features. The invented fabrication method is also efficient in that most of the oxide in the tunnel windows can be removed by dry etching, which is faster than wet etching.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     In the attached drawings:  
         [0015]      FIG. 1  is a sectional view of an EEPROM memory cell manufactured by a process embodying the present invention;  
         [0016]      FIGS. 2A  to  2 F illustrate steps in a tunnel oxide film fabrication process embodying the present invention; and  
         [0017]      FIG. 3  is a graph showing time-dependent dielectric breakdown indices of the tunnel oxide film as a function of the film thickness left after dry etching. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     An embodiment of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.  
         [0019]     First Embodiment  
         [0020]     Referring to  FIG. 1 , an EEPROM cell  1  used in a nonvolatile semiconductor memory includes a silicon substrate  2  doped with a p-type impurity, a source  3  and a drain  4  formed in the silicon substrate  2  and doped with an n-type impurity, a gate oxide film  5  bridging the channel between the source  3  and drain  4 , a floating gate electrode  6  resting on the gate oxide film  5 , facing the silicon substrate  2  through the gate oxide film  5 , an insulating film  7  covering other surfaces of the floating gate electrode  6 , a control gate electrode  8  formed above the floating gate electrode  6 , separated from it by the insulating film  7  and functioning in the same way as the gate electrode of an ordinary MOS transistor, and a tunnel oxide film  9  disposed at the bottom of a window in the gate oxide film  5 . The tunnel oxide film  9  is a thin oxide film through which electrons can tunnel between the floating gate electrode  6  and the substrate  2 .  
         [0021]     A method of fabricating the tunnel oxide film  9  will be described with reference to  FIGS. 2A  to  2 F, which indicate the following additional features: a resist mask  11  formed by exposing and developing a photoresist coating on an oxide film  12  that becomes the gate oxide film  5 ; a circular or elliptical tunnel window area  13  (e.g., a circular area with a diameter of 0.4 to 0.45 μm) in which the tunnel oxide film  9  is formed; an opening  14  in the resist mask  11  inside the tunnel window area  13 ; and the tunnel window  15 , which has the same dimensions as the tunnel window area  13  and extends through the oxide film  12  or gate oxide film  5  down to the silicon substrate  2 .  
         [0022]     In the first fabrication step or process P 1  illustrated in  FIG. 2A , the oxide film  12  is formed by thermal oxidation of the surface of the silicon substrate  2 . The oxide film  12  is a thin layer of silicon dioxide (SiO 2 ), slightly thinner than the intended thickness of the gate oxide film.  
         [0023]     In the second process P 2  illustrated in  FIG. 2B , a layer of photoresist is coated onto the surface of the oxide film  12 , exposed to light through an optical mask (not shown), and developed to form the resist mask  11 . The opening  14  formed in the resist mask  11  defines the tunnel window area  13  in which the tunnel oxide film  9  will be formed, but the opening  14  is slightly smaller than the tunnel window area  13 .  
         [0024]     The third process P 3  illustrated in  FIG. 2C  is a dry etching process, more specifically an anisotropic plasma etching process, that etches the oxide film  12  below the opening  14  in the resist mask  11 . The duration of the process is controlled so that the etching stops short of the substrate  2 , leaving a thickness of five nanometers (5 nm) of oxide film  12  intact. The etching gas is a mixture of argon (Ar) supplied at a rate of one thousand standard cubic centimeters per minute (1000 sccm), carbon tetrafluoride (CF 4 ) supplied at 45 sccm, and trifluoromethane (CHF 3 ) supplied at 45 sccm. The plasma pressure is 1.6 torr and the radio-frequency (RF) power that ionizes the plasma is one hundred watts (100 W). The 5-nm remaining thickness of the oxide film  12  is adequate to protect the surface of the silicon substrate  2  from plasma damage at these etching conditions.  
         [0025]     The fourth process P 4  illustrated in  FIG. 2D  is a wet etching process that removes the remaining thickness of the oxide film  12  in the tunnel window area  13 . The etching fluid is dilute hydrofluoric acid or buffered hydrofluoric acid. This wet etching process is isotropic and proceeds downward and laterally by similar amounts, but because the remaining thickness of the oxide film  12  is only 5 nm, the etching process can be accurately controlled to stop when the surface of the silicon substrate  2  is exposed. The amount of lateral etching is thus also accurately controllable to give the completed tunnel window  15  dimensions matching the intended tunnel window area  13 .  
         [0026]     In the fifth process P 5  illustrated in  FIG. 2E , the resist mask  11  is removed by use of a stripping agent, and the exposed surfaces of the oxide film  12  and silicon substrate  2  are cleaned.  
         [0027]     The sixth process P 6  illustrated in  FIG. 2F  is a thermal oxidation process that oxidizes the surface of the silicon substrate  2  exposed at the bottom of the tunnel window  15  to form a thin film of silicon dioxide, this being the tunnel oxide film  9 . The surface of the silicon substrate at the interface with the oxide film  12  is also oxidized, increasing the thickness of the oxide film  12  to the intended gate oxide thickness, so that the oxide film  12  becomes the gate oxide film  5 .  
         [0028]     Following the process steps illustrated in  FIGS. 2A  to  2 F, the source  3  and drain  4  shown in  FIG. 1  are formed in the silicon substrate  2 , and the floating gate electrode  6 , insulating film  7 , and control gate electrode  8  are formed. The processes by which these elements are formed are well known; detailed descriptions will be omitted.  
         [0029]     Tests were carried out by the inventor to determine how the durability of the tunnel oxide film  9  varied depending on the thickness of the oxide film  12  left by the dry etching process P 3 . Oxide films  12  were etched under the conditions given in process P 3  for various times, selected to leave various oxide thicknesses. The remaining oxide was then removed by wet etching and tunnel oxide films were formed as in processes P 4  to P 6 . The tunnel oxide films were evaluated by the time-dependent dielectric breakdown (TDDB) method, and the times to dielectric breakdown were compared. The results are indicated by the graph in  FIG. 3 : the thickness of the oxide film  12  left in step P 3  is shown on the horizontal axis; the time until dielectric breakdown is indicated on the vertical axis by an index normalized so that the dielectric breakdown time for a remaining oxide thickness of 13.2 nm is equal to unity.  
         [0030]     As  FIG. 3  shows, when the remaining oxide thickness is less than 5 nm, the quality of the tunnel oxide film  9  decreases rapidly with decreasing oxide thickness left in process P 3 , as indicated by increasingly short dielectric breakdown times. When the remaining oxide thickness is greater than 5 nm, the tunnel oxide film  9  is stable and the dielectric breakdown time remains the same regardless of the remaining oxide thickness in process P 3 . This indicates that to avoid damage to the silicon surface in process P 3  and form a tunnel oxide film  9  of good quality in step P 6 , the remaining oxide thickness in step P 3  should be 5 nm or greater.  
         [0031]     It is also desirable for the etching depth in the dry etching process P 3  to be at least 80% of the thickness of the oxide film  12 . If the etching depth is less than 80%, the subsequent wet etching process P 4  will take significant time, wet etching being slower than dry etching, and the fabrication process will become inefficient. Longer wet etching times also lead to greater variability in the amount of lateral etching, making it difficult to control the size of the tunnel window  15  accurately. The desirable range of remaining oxide thickness is therefore from 5 nm to 20% the thickness of the oxide film  12 , with a value at or near 5 nm being most preferable.  
         [0032]     By using dry etching for the greater part of the tunnel window etching process and using wet etching only to remove the thin remaining oxide left by dry etching, the invented fabrication process can control the lateral expansion of the tunnel windows and form tunnel windows with sizes matching the gate lengths of MOS transistors, without having to resort to a costly and in some cases impractical photolithographic process capable of forming features significantly smaller than the gate lengths of the MOS transistors. EEPROM cells and MOS transistors of similar dimensions can accordingly be formed efficiently on a single wafer fabrication line.  
         [0033]     The invention also provides a way to form small tunnel windows quickly (by removing at least 80% of the oxide film by dry etching), without damaging the underlying silicon surface (by leaving at least 5 nm of the oxide film to be removed by wet etching), and without the need for photolithographic equipment having a resolution much higher than the tunnel window dimensions.  
         [0034]     The invention has been described through a single embodiment, but those skilled in the art will recognize that variations are possible within the scope of the invention, which is defined in the appended claims.