Abstract:
An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of semiconductor devices; more specifically, it relates to crackstops and methods of making crackstops. 
       BACKGROUND OF THE INVENTION 
       [0002]    Crackstops are structures fabricated along the perimeter of integrated circuit chips to prevent delamination of the various layers of the integrated circuit chip and other edge damage during singulation (otherwise known as dicing) of individual integrated circuit chips from a wafer on which multiple integrated circuit chips have been fabricated. The inventors have determined the protection provided by conventional crackstops has become less adequate as the dimensions of integrated circuit features has decreased and with the increasing use of low dielectric insulating materials. 
       SUMMARY OF THE INVENTION 
       [0003]    A first aspect of an embodiment of the invention is a method, comprising: (a) for one or more integrated circuit chips of an array of integrated circuit chips on a semiconductor substrate, forming a first or next wiring level over the substrate; (b) for predetermined first or next wiring levels of each integrated circuit chip of the one or more integrated circuit chips, forming a corresponding first or next void in the first or next wiring level, the first or next void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a subsequently formed wiring level stacked directly over but not contacting a void of a previously formed level; (c) repeating steps (a) and (b) multiple times to form in each integrated circuit chip of the one or more integrated circuit chips a respective crack stop comprising a stack of voids; and after (c), (d) dicing the array of integrated circuit chips into individual integrated circuit chips, each individual integrated circuit chip of the one or more integrated circuit chips including a respective crackstop. 
         [0004]    A second aspect of an embodiment of the invention is an integrated circuit chip, comprising: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0006]      FIGS. 1A through 1I  are cross-sections illustrating fabrication of a crackstop structure according to embodiments of the present invention; 
           [0007]      FIG. 2  is a detailed view of exemplary void formation in the crackstop structures of the embodiments of the present invention; and 
           [0008]      FIG. 3  is a plan view of integrated circuit chips prior to singulation according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0009]      FIGS. 1A through 1I  are cross-sections illustrating fabrication of a crackstop structure according to embodiments of the present invention. In  FIG. 1A , semiconductor substrate  100  includes a buried oxide (BOX) layer  105  between a semiconductor layer  110  and a supporting substrate  115 . In one example, semiconductor layer  110  and supporting substrate  115  comprise silicon. As illustrated, semiconductor substrate  100  is an example of a silicon-on-insulator (SOI) substrate. Other semiconductor substrates, such as bulk silicon substrates and silicon-germanium substrates may be substituted for SOI substrates. Regions of shallow trench isolation (STI)  120  have been formed in silicon layer  100  simultaneously forming silicon islands  125  which are completely surrounded along their perimeters by STI  120 . A contact layer  130  is formed in a region of silicon island  125  adjacent to top surfaces of the silicon islands. Formed on top surfaces  137  of contact layers  130  and on the top surface of STI  120  is a first dielectric layer  135 . In one example first dielectric layer  135  is silicon nitride. In one example first dielectric layer  135  is silicon nitride under internal tensile stress (e.g. about 1.5 GPa). In one example, first dielectric layer  135  is between about 50 nm and about 150 nm thick. In one example, contact layer  130  is a metal silicide. 
         [0010]    In  FIG. 1B , a trench  140  has been formed in first dielectric layer  135  over STI  120 . Trench  140  extends from a top surface  142  of first dielectric layer  135  to a top surface  143  of STI  120 . Trench  140  has a width W 1  and a height H 1  (where H 1  is equal to the thickness of first dielectric layer  135 . Alternatively, a thin layer (less than about 20% of the thickness of first dielectric layer  135 ) may be left in the bottom of trench  140 . In one example, the aspect ratio (H 1 /W 1 ) of trench  140  is equal to or greater than about 2. In one example, the aspect ratio (H 1 /W 1 ) of trench  140  is equal to or greater than about 3. In one example, trench  140  may be formed by applying a layer of photoresist to first dielectric layer  135 , exposing the photoresist to actinic radiation through a patterned photomask, developing the exposed photoresist, reactive ion etching (RIE) first dielectric layer  135  where it its not protected by the photoresist layer and then removing the photoresist layer. 
         [0011]      FIG. 1C , a second dielectric layer  145  is formed on a top surface  146  of first dielectric layer  135 . Because of the high aspect ratio of trench  140  (see  FIG. 1B ), second dielectric layer  145  does not fill or only partially fills trench  140  (see  FIG. 1B ) forming a void  140 A in first dielectric layer  135 . See discussion infra and  FIG. 2 . Contacts  150  are formed through first and second dielectric layers  135  and  145 . Contacts  150  extend from a top surface  147  of second dielectric layer to top surface  137  of contact layer  130 . Top surfaces  148  of contacts  150  are essentially coplanar with top surface  147  of second dielectric layer  145 . In one example second dielectric layer  145  comprises a high density plasma (HDP) oxide. An HDP oxide is an oxide formed in a high-density plasma chemical vapor (CVD) deposition process and is well know in the industry. In one example, HDP oxide is formed from mixture of oxygen and silane at a pressure of about 2 mTorr to about 10 mTorr in a plasma having an electron density of about 1E12/cm 2 . In one example second dielectric layer  145  is between about 200 nm and about 300 nm thick. First dielectric layer  135 , second dielectric layer  145  and contacts  150  comprise a contact level of an integrated circuit chip, which may also be considered a wiring level. Contacts  150  and void  140 A extend in concentric rings proximate to a perimeter of the integrated circuit chip. 
         [0012]    In  FIG. 1D , a third dielectric layer  155  is formed on top surface  147  of second dielectric layer  145 . Metal wires  160  are formed through third dielectric layer  155 . Wires  160  extend from a top surface  162  of third dielectric layer  155  to top surfaces  148  of contacts  150 . Top surfaces  163  of wires  160  are essentially coplanar with top surface  162  of third dielectric layer  155 . In one example, third dielectric layer  155  comprises one or more low K (dielectric constant) materials, examples of which include but are not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), SiLK™ (polyphenylene oligomer) manufactured by Dow Chemical, Midland, Tex., Black Diamond™ (methyl doped silica or SiO x (CH 3 ) y  or SiC x O y H y  or SiOCH) manufactured by Applied Materials, Santa Clara, Calif., organosilicate glass (SiCOH), and porous SiCOH. A low K dielectric material has a relative permittivity of about 2.4 or less. In one example, third dielectric layer  155  is between about 100 nm and about 200 nm thick. Third dielectric layer  155  and wires  160  comprise a first wiring level (or a second wiring level if contacts  150  are counted as wires) of the integrated circuit chip. Wires  160  extend in concentric rings proximate to a perimeter of the integrated circuit chip. 
         [0013]    In  FIG. 1E , a fourth dielectric layer  165  is formed on top surface  162  of third dielectric layer  155  and on top surfaces  163  of wires  160 . A trench  170  has been formed in fourth dielectric layer  165  aligned over void  140 A and over STI  120 . Trench  170  extends from top surface  167  of fourth dielectric layer  165  to top surface  162  of third dielectric layer  155 . Trench  170  has a width W 2  and a height H 2  (where W 2  is equal to the thickness H 2  of fourth dielectric layer  165 . Alternatively, a thin layer (less than about 20% of the thickness of fourth dielectric layer  165 ) may be left in the bottom of trench  170 . In one example, the aspect ratio (H 2 /W 2 ) of trench  170  is equal to or greater than about 2. In one example, the aspect ratio (H 2 /W 2 ) of trench  170  is equal to or greater than about 3. In one example, fourth dielectric layer  165  comprises silicon nitride or silicon carbide. In one example, fourth dielectric layer  165  is between about 25 and 75 nm thick. In one example, trench  170  may be formed by applying a layer of photoresist to fourth dielectric layer  165 , exposing the photoresist to actinic radiation through a patterned photomask, developing the exposed photoresist, RIE fourth dielectric layer  165  where it its not protected by the photoresist layer and then removing the photoresist layer. 
         [0014]    In  FIG. 1F , a fifth dielectric layer  175  is formed on top surface  167  of fourth dielectric layer  165 . Because of the high aspect ratio of trench  170  (see  FIG. 1E ), fifth dielectric layer  175  does not fill or only partially fills trench  170  (see  FIG. 1E ) forming a void  170 A in fourth dielectric layer  165 . See discussion infra and  FIG. 2 . In one example, fifth dielectric layer  175  comprises one or more of the low K dielectric materials listed supra. In one example, fifth dielectric layer  175  is between about 300 nm to about 400 nm thick. 
         [0015]    In  FIG. 1G , metal wires  180  are formed through fourth dielectric layer  175  and fifth dielectric layer  165 . Wires  180  extend from a top surface  184  of fifth dielectric layer  175  to top surfaces  168  of wires  160 . Top surfaces  182  of wires  180  are essentially coplanar with a top surface  184  of fifth dielectric layer  175 . Fifth dielectric layer  165 , sixth dielectric layer  175  and wires  180  comprise a second wiring level (or a third wiring level if contacts  150  are counted as wires) of the integrated circuit chip. Wires  180  extend in concentric rings proximate to a perimeter of the integrated circuit chip. 
         [0016]    In  FIG. 1H , a sixth dielectric layer  185  is formed on fifth dielectric layer  175 , a seventh dielectric layer  190  is formed on the sixth dielectric layer, wires  200  are formed through the sixth and seventh dielectric layers to wires  180  and a void  205 A is formed in the sixth dielectric layer aligned over voids  170 A and  140 A and STI  120 . Void  205 A is similarly formed as voids  140 A and  170 A by control of the aspect ration of a precursor trench formed in sixth dielectric layer  185 . In one example, sixth dielectric layer  185  comprises silicon nitride or silicon carbide. In one example, sixth dielectric layer  185  is between about 25 and 75 nm thick. In one example, seventh dielectric layer  190  comprises one or more of the low K dielectric materials listed supra. In one example, seventh dielectric layer  190  is between about 300 nm to about 400 nm thick. 
         [0017]    Sixth dielectric layer  185 , seventh dielectric layer  190  and wires  200  comprise a third (or a fourth wiring level if contacts  150  are counted as wires) and in this example, last wiring level of the integrated circuit chip. Wires  200  and void  205 A extend in rings proximate to a perimeter of the integrated circuit chip. Additional wiring levels (not illustrated in the drawings) similar to the second and third wiring levels may be formed between the first and second wiring levels. 
         [0018]    In  FIG. 1I , a terminal passivation level  215  is formed on seventh dielectric layer  190 . Terminal passivation level  215  comprise a first terminal dielectric layer  220  and a second terminal dielectric layer  225  Terminal pads (not shown) are formed in terminal passivation level  215  to the left of wires  200 ,  180 ,  160  and contacts  150 . In one example, first terminal dielectric layer  220  comprises silicon nitride or silicon carbide. In one example, first terminal dielectric layer  220  is between about 25 and 75 thick. In one example second terminal dielectric layer  225  comprises an N-doped silicon glass. A chip passivation layer  230  is formed on terminal level  215 . The terminal pads (not shown) are not covered by chip passivation layer  230 . Chip passivation layer  230  may comprise two or more layers. Chip passivation layer  230  may include an oxide layer, a silicon carbide layer, a polyimide layer and combination thereof. 
         [0019]    Also in  FIG. 1I , an edge  235  of a singulated chip has been formed by dicing. In one example, dicing is performed by sawing the wafer into individual chips. A peripheral region  240  of the singulated integrated circuit chip includes a crackstop  245 , an outer guard ring  250  and an inner guard ring  255 . Crackstop  245  includes voids  140 A,  170 A and  190 A aligned in a common plane  260  parallel to edge  235 . Voids  205 A,  170 A and  140 A are stacked (i.e., aligned) directly over each other but do not contact each other, there being a dielectric layer intervening between each of the voids. Edge  235  is perpendicular to a top surface of substrate  100 . Each of guard rings  250  and  255  includes a silicon island  125 , a contact layer  130 , a contact  150 , a wire  160 , a wire  180  and a wire  200 . Since integrated circuit chips generally have a square or rectangular footprint, there is a plane  260  for each of the four edges of the integrated circuit chip. 
         [0020]    Contacts  150  and wires  160  are single damascene contacts and wires formed by a single-damascene process. Wires  180  and  200  are dual-damascene wires formed by a dual damascene process. In one example, contacts  150  comprise tungsten. In one example, wires  160 ,  180  and  200  comprise a core of copper, a liner of tantalum over the copper core and a liner of tantalum nitride over the tantalum liner. The liners are formed on the sides and bottom of the trench the wire in as described infra. 
         [0021]    A damascene process is one in which wire trenches or via openings are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited on a top surface of the dielectric layer, and a chemical-mechanical-polish (CMP) process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the dielectric layer to form damascene wires (or damascene vias). When only a trench and a wire (or a via opening and a via) is formed the process is called single-damascene. 
         [0022]    A dual-damascene process is one in which via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. All via openings are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is deposited on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planar with the surface the dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias. 
         [0023]    In one example, not all wiring levels need to contain voids. In the present example of  FIGS. 1A through 1H , the wiring level comprising wires  160  and third dielectric layer  155  does not contain crackstop voids. Likewise either of crackstop voids  140 A or  170 A need not be formed. However the more levels having crackstop voids, the more effective crackstop  245  will be at preventing delamination and propagation of damage from edge  235  into the interior of the integrated circuit chip. By incorporating an additional dielectric layer between second dielectric layer  135  and third dielectric layer  155 , a crackstop void may be formed in this additional dielectric layer using the high aspect ratio trench technique described supra, so the wiring level comprising wires  160 , and third dielectric layer  155  may contain a crackstop void and the additional dielectric layer may contain a crackstop void. The actual determination of whether or not a wiring level is to contain a crackstop void is determined during the design of the integrated circuit chip as part of the design dataset and incorporated as features of the photomasks used during fabrication of the integrated circuit chip. 
         [0024]      FIG. 2  is a detailed view of exemplary void formation in the crackstop structures of the embodiments of the present invention. In  FIG. 2 , it can be seen that the material of second dielectric layer  145  coats sidewalls  265  and bottom  270  of trench  140  but the trench is not completely filled in forming the void  140 A. In other examples, bottom surface  270  may not be completely covered by the material of dielectric layer  145 . 
         [0025]      FIG. 3  is a plan view of integrated circuit chips prior to singulation according to embodiments of the present invention. In  FIG. 3 , a wafer  300  includes an array of un-singulated integrated circuit chips  305 . Chips  305  are separated by kerf regions  310 . An active region  315  of each integrated circuit chip is surrounded by crackstop  245  and outer and inner guard rings  250  and  255 . The heavy line indicates edge  235  of chip  305  after dicing along the dashed lines  320 . 
         [0026]    Thus, the embodiments of the present invention provide a crackstop having small horizontal dimensions and suitable for use with low-K inter-level dielectric materials. 
         [0027]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.