Abstract:
A semiconductor package exhibiting efficient placement of semiconductor leads in a micro lead frame design is provided. An integrated circuit die is bonded to the top surfaces of leads, thereby allowing the leads to partially reside under the die. As a result, surface area on the bottom surface of the semiconductor package is recaptured. The die can be further bonded a die paddle if so desired. One or more channels can be cut into the bottom surface of the package in order to separate first and second leads. Such channels allow separate leads to be fabricated from a single lead member which is subsequently cut.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     (Not Applicable) 
     STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT 
     (Not Applicable) 
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to integrated circuit chip package technology, and more particularly to a unique package design that facilitates the efficient placement of the leads therein. 
     Integrated circuit dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and an underlying substrate such as a printed circuit board (“PCB”). 
     Semiconductor packages employing micro lead frames (“MLF”) typically include a metal lead frame (often made from copper (Cu)), an integrated circuit die, bonding material to attach the integrated circuit die to the lead frame, bond wires which electrically connect pads on the integrated circuit die to individual leads of the lead frame, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package. 
     The lead frame is the central supporting structure of such packages. A portion of the lead frame is internal to the package, i.e., completely surrounded by the plastic encapsulant. Portions of the leads of the lead frame extend externally from the package or are partially exposed within the encapsulant material for use in electrically connecting the die to the underlying substrate. Due to the relatively short electrical path from the die to the lead, such MLF packages can exhibit improved electrical efficiency in comparison to conventional Quad Flat Package (“QFP”) designs. 
     One of the drawbacks associated with certain MLF semiconductor packages is the limited surface area available to accommodate leads. Modern integrated circuit dies often include larger numbers of input and output pads than previous dies. To accommodate these additional pads, increasing numbers of leads must also be provided with semiconductor packages. Unfortunately, conventional MLF designs typically require these leads to be located on the bottom surface of the semiconductor package around the perimeter of a die paddle portion of the lead frame. Thus, the limited surface area available for lead placement on such packages can significantly impact the number of leads provided. 
     The present invention addresses this problem by providing various chip on lead configurations (“COL”) which position portions of leads underneath the integrated circuit die, thereby allowing more efficient use of the semiconductor package bottom surface area. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is directed to a semiconductor package design that exhibits efficient placement of semiconductor leads within the limited surface area available on the bottom of such packages. 
     In one embodiment, an integrated circuit chip package is provided having an integrated circuit die bonded to portions of the top surfaces of leads. As a result of bonding the die to the leads rather than to only a separate die paddle, the leads are caused to partially reside under the die. As a result, surface area that would otherwise be consumed by the leads can be used for other leads, thus making the placement of leads in such a package more efficient. The die can be further bonded to a separate die paddle if so desired. 
     In another embodiment, one or more channels are provided in a bottom surface of the package, the channels effectively separating various sets of leads from each other. Such channels may be formed during the manufacture of such packages, allowing separate leads to be fabricated from a single, cut lead member. 
     Methods of manufacturing semiconductor chip packages exhibiting these features are also provided. These and other embodiments of the present invention, are discussed in more detail below. 
     The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These as well as other features of the present invention will become more apparent upon reference to the drawings wherein: 
         FIG. 1A  is a sectional view of a semiconductor package having multiple leads separated by channels; 
         FIG. 1B  is a bottom plan view of the semiconductor package of  FIG. 1A ; 
         FIG. 1C  is a bottom perspective view of the semiconductor package of  FIG. 1A ; 
         FIGS. 2A–E  are sectional views illustrating a method for manufacturing the semiconductor package of  FIG. 1A ; 
         FIG. 3  is a bottom plan view of a semiconductor package having first and second leads staggered in relation to each other; 
         FIG. 3A  is a bottom plan view showing a lead frame providing step in a method for manufacturing the semiconductor package of  FIG. 3 ; 
         FIG. 3B  is a bottom plan view showing an encapsulating step in a method for manufacturing the semiconductor package of  FIG. 3 ; 
         FIG. 3C  is a bottom plan view showing a channel formation step in a method for manufacturing the semiconductor package of  FIG. 3 ; 
         FIG. 4A  is a sectional view of a semiconductor package having first and second leads separated by two parallel channels; 
         FIG. 4B  is a bottom plan view of the semiconductor package of  FIG. 4A ; 
         FIG. 5A  is a sectional view of a semiconductor package having a die mounted flush with the bottom surface of the package; 
         FIG. 5B  is a bottom plan view of the semiconductor package of  FIG. 5A ; 
         FIG. 6A  is a sectional view of a semiconductor package having leads separated by a single channel; 
         FIG. 6B  is a bottom plan view of the semiconductor package of  FIG. 6A ; 
         FIGS. 7A–F  are views illustrating steps in a method for manufacturing the semiconductor package of  FIG. 6A ; 
         FIG. 8A  is a sectional view of a semiconductor package having leads separated by a single channel; 
         FIG. 8B  is a bottom plan view of the semiconductor package of  FIG. 8A ; 
         FIG. 9A  is a sectional view of a semiconductor package having a die pad and leads separated by two channels; 
         FIG. 9B  is a bottom plan view of the semiconductor package of  FIG. 9A ; 
         FIG. 10  is a sectional view of a semiconductor package having multiple dies attached to first and second leads; and 
         FIG. 11  is a sectional view of a semiconductor package having multiple stacked dies. 
     
    
    
     Common reference numerals are used throughout the drawings and detailed description to indicate like elements. 
     DETAILED DESCRIPTION OF THE INVENTION 
       FIGS. 1A–C  provide sectional, bottom, and perspective views of a semiconductor package having multiple leads separated by channels. As shown in the drawings, semiconductor package  100  includes a substantially planar die paddle  110 , a plurality of first leads  120 , a plurality of second leads  130 , an integrated circuit die  150  bonded to the die paddle  110 , and conductive wires  160  for electrically connecting the integrated circuit die  150  to the first and second leads  120  and  130 . Encapsulant  170  is provided for encapsulating die paddle  110 , leads  120  and  130 , integrated circuit die  150 , and conductive wires  160 . In addition, portions of leads  120  and  130  are exposed in an exterior surface of the encapsulant  170 . 
     Die paddle  110  includes substantially planar top and bottom surfaces  112  and  114 . Portions of bottom surface  114  are etched to form substantially planar partially etched surfaces  116 . As a result, the area of bottom surface  114  is reduced in relation to the area of top surface  112 . In one embodiment, the thickness of the die paddle  110  between top surface  112  and etched surface  116  is approximately 25˜75% of the thickness between top surface  112  and bottom surface  114 . Etched surface  116  serves to increase the bonding force between die paddle  110  and the encapsulant  170 , as well as to elongate the passage through which moisture must travel to permeate the interface between die paddle  110  and encapsulant  170 . As a result, the reliability of semiconductor package  100  is improved. 
     First leads  120  include opposed, substantially planar top and bottom surfaces  122  and  124 , respectively. The bottom surfaces  124  are also partially etched to form partially etched surfaces  126  and  127 . As illustrated in  FIGS. 1B–C , first leads  120  are arranged in a generally square pattern around the perimeter of die paddle  110 . Each of the first leads  120  is also separated from die paddle  110  at a predetermined distance. In another embodiment, the thickness of the first leads  120  between top surfaces  122  and etched surfaces  126  or  127  is approximately 25˜75% of the thickness of the first leads  120  between top surfaces  122  and bottom surfaces  124 . Etched surface  126  serves to increase the bonding force between the leads  120  and the encapsulant  170  as well as to elongate the passage through which moisture must travel to permeate the interface between the first leads  120  and encapsulant  170 . Etched surface  127  serves primarily to increase the bonding force between each first lead  120  and encapsulant  170 . 
     As illustrated in  FIGS. 1B–C , second leads  130  are also arranged in a generally square pattern. The second leads  130  are separated from and disposed outwardly of first leads  120 , and extend to respective ones of the four peripheral sides defined by the encapsulant  170 . The second leads  130  are separated from respective ones of the first leads  120  by a predetermined distance. In the package  100 , each of the second leads  130  is preferably aligned with a respective one of the first leads  120 . Second leads  130  each include opposed, substantially planar top and bottom surfaces  132  and  134 , respectively. The bottom surfaces  134  are partially etched to form partially etched surfaces  136 . Etched surfaces  136  serve primarily to increase the bonding force between the second leads  130  and encapsulant  170 . 
     Integrated circuit die  150  includes opposed, substantially planar top and bottom surfaces  152  and  154 , respectively. A plurality of bond pads  156  are formed on top surface  152 . Bottom surface  154  is bonded to top surface  112  of die paddle  110  by an adhesive  140 . It will be understood that the adhesive  140  (as well as the other adhesives described herein) may be an epoxy, adhesive film, or other adhesives known in the art. In one embodiment, the area of the bottom surface  154  of the integrated circuit die  150  is smaller than that of the top surface  112  of the die paddle  110 , thus allowing conductive wires  160  to easily bond to the edge of the top surface  112  of die paddle  110 . 
     As illustrated in  FIG. 1A , conductive wires  160  serve to connect bond pads  156  to top surfaces  122  of the first leads  120 , top surfaces  132  of the second leads  130 , and/or the top surface  112  of the die paddle  110 . Connecting the bond pads  156  to the top surface  112  of die paddle  110  permits ground signals of the integrated circuit die  150  to be transmitted to the die paddle  110 , thus improving the electrical efficiency of the package  100 . Although the first and second leads  120  and  130  are typically used for signaling or power, the first and second leads  120  and  130  may alternatively be used for grounding. Conductive wires  160  (as well as the other conductive wires described herein) can be fabricated from aluminum (Al), copper (Cu), gold (Au), silver (Ag), or other materials known in the art. 
     Die paddle  110 , first and second leads  120  and  130 , integrated circuit die  150 , and conductive wires  160  are encapsulated by the encapsulant  170 . The bottom surface  114  of die paddle  110  as well as the bottom surfaces  124  and  134  of the first and second leads  120  and  130  are exposed in an exterior surface of the encapsulant  170  (i.e., the bottom surface thereof). The encapsulant  170  (as well as the other encapsulants described herein) can comprise conventional epoxy molding compound, epoxy resin, or other materials known in the art. 
     Channels  180  having predetermined depths are formed in the encapsulant  170  between the first leads  120  and the second leads  130 , thus separating adjacent ends of the first and second leads  120  and  130  from each other. Specifically, channels  180  are formed between the partially etched surfaces  127  of the first leads  120  and the partially etched surfaces  136  of the second leads  130 . Thus, the channels  180  extend in a generally square pattern. In one embodiment, the depth of the channels  180  is slightly greater than the thickness of first and second leads  120  and  130 . As illustrated in  FIGS. 1B–C , four intersecting channels  180  can be provided that extend lengthwise along the bottom surface of the encapsulant  170  forming a quad-shaped pattern as indicated above. As illustrated in  FIG. 1A , side surfaces  128  and  138  adjacent to the partially etched surfaces  127  and  136  of leads  120  and  130  are exposed in an exterior surface of the encapsulant  170  within the channels  180 . Thus, channels  180  allow first and second leads  120  and  130  to be physically separated and electrically insulated from each other. Since bottom surfaces  124  and  134  the leads  120  and  130  lead are exposed in the lower surface of the encapsulant  170 , the number of input and output pads is maximized in the semiconductor package  100 . 
       FIGS. 2A–E  provide sectional views which illustrate an exemplary method for manufacturing the semiconductor package  100  of  FIG. 1A . As shown in  FIG. 2A , a die paddle  110  is provided having substantially planar top and bottom surfaces  112  and  114 , and a partially etched surface  116  of a predetermined depth formed at an edge of the bottom surface  114 . A plurality of first leads  120  are provided having substantially planar top and bottom surfaces  122  and  124 , and partially etched surfaces  126  and  127  of predetermined depths formed on bottom surfaces  124 . First leads  120  are separated from die paddle  110  by a predetermined distance. A plurality of second leads  130  are connected to respective ones of the first leads  120 , each second lead  130  having substantially planar top and bottom surfaces  132  and  134 , and a partially etched surface  136  of predetermined depth formed on bottom surface  132 . First and second leads  120  and  130  are initially joined together and held in place by a dam bar. When the first and second leads  120  and  130  are initially joined together, the partially etched surfaces  127  and  136  thereof are continuous. The dam bar (not shown) prevents the leads from easily bending. The dam bar is removed during a subsequent channel forming step to ensure that the first and second leads  120  and  130  are electrically insulated from each other in the finished semiconductor package  100 . As indicated above, while the first and second leads  120  and  130  are joined together, partially etched surfaces  127  and  136  are adjacent to each other, thus forming a continuous partially etched surface. 
       FIG. 2B  illustrates a die attaching step used in the manufacture of semiconductor package  100 . Bottom surface  154  of integrated circuit die  150  is bonded to the top surface  112  of die paddle  110  by adhesive  140 . 
       FIG. 2C  illustrates a wire bonding step used in the manufacture of semiconductor package  100 . Bond pads  156  are electrically connected to the top surfaces of the first leads  120 , second leads  130 , and die paddle  110  through the use of the conductive wires  160 . 
       FIG. 2D  illustrates an encapsulating step used in the manufacture of semiconductor package  100 . Die paddle  110 , first and second leads  120  and  130 , die  150 , and conductive wires  160  are encapsulated by encapsulant  170 . The encapsulant  170  protects these components from the external environment and allows the semiconductor package  100  to be mounted on external devices in a fixed shape. In addition, bottom surfaces  114 ,  124 , and  134  remain exposed in the bottom surface of the encapsulant  170 . 
       FIG. 2E  illustrates a channel forming step used in the manufacture of semiconductor package  100 . Channels  180  are formed between the first leads  120  and the second leads  130 , and pass through portions of the partially etched surfaces  127  and  136 . Portions of the encapsulant  170  and partially etched surfaces  127  and  136  are cut, thus forming channels  180 . It will be appreciated that channels  180  can be cut by lasers, blades, or other tools and/or methods known in the art. As a result of this cutting operation, first and second leads  120  and  130  are separated from each other. The bottom surfaces  124  and  134  of the severed first and second leads  120  and  130  are arrayed in columns and in rows at the lower surface of the encapsulant  170 , thereby maximizing the number of input and output pads in the semiconductor package  100 . 
     As indicated above, the width of channels  180  can be made smaller than that of the partially etched surface  127  or the partially etched surface  136  such that predetermined regions of the partially etched surfaces  127  and  136  are located in the inside of the encapsulant  170 , thereby increasing the bonding force between the encapsulant  170  and the first and second leads  120  and  130 . This width also allows any burrs generated by blade cutting the channels  180  to be minimized. As discussed above, the dam bar holding leads  120  and  130  is removed during the channel forming step to ensure that the first and second leads  120  and  130  are electrically insulated from each other. In one embodiment, the width of the dam bar is smaller than that of partially etched surfaces  126  and  127 , and channels  180 , thus facilitating its complete removal as a result of the cutting operation. 
       FIGS. 3–3C  illustrate a semiconductor package  200  having first and second leads staggered in relation to each other. Although package  200  of FIGS. of  3 – 3 C exhibits similarities to package  100  of  FIGS. 1A–B , differences between the packages  100  and  200  will be described below. 
     As shown in  FIG. 3 , a plurality of first leads  220  and a plurality of second leads  230  are staggered in relation to each other as viewed from the bottom surface of encapsulant  270 . It will be appreciated that the number of the first leads  220  illustrated within the perimeter of channels  280  is greater than the number of second leads  230  illustrated outside the channels  280 . In alternate embodiments, the reverse is also possible. 
     Similar to package  100 , partially etched surfaces (not shown) inside encapsulant  270  are formed in the first leads  220  adjacent to the channels  280 . Other partially etched surfaces (not shown) inside the encapsulant  270  are formed in the second leads  230  adjacent to channels  280 . 
     The staggered orientation of the first and second leads  220  and  230  makes easier the wire bonding of the die of package  200  (not shown) to the first and second leads  220  and  230 , allowing the conductive wires (not shown) used to bond the die with the leads  220  and  230  to be oriented in different directions relative to each other, thus reducing the length of wire required and susceptibility to shorting. The staggered orientation also increases the solder bonding force exhibited between package  200  and an external device (not shown). Since the first and second leads  220  and  230  are closely arrayed at the bottom surface of the encapsulant  270  in this orientation, the solder bonding force between the leads  220  and  230  and the external device increases. 
       FIG. 3A  illustrates a lead frame providing step used in the manufacture of semiconductor package  200 . Partially etched surfaces  227  and  236  are represented as deviant lines in  FIG. 3A . The leadframe is constructed in a manner wherein certain ones of the inner, first leads  220  transition into a pair of outer, second leads  230 , and certain ones of the outer, second leads  230  transition into a pair of inner, first leads  220 . The second leads  230  extend to respective ones of four peripheral sides or edges defined by the encapsulant  270 . In various embodiments, the first and second leads  220  and  230  extend in generally square patterns about the periphery of the die paddle  210 . As illustrated in  FIG. 3A , several of the first leads  220  are connected to connecting leads  219  of the die paddle  210  in order to support the die paddle  210 . In addition, the connecting leads  219  include partially etched surfaces which can be encapsulated in a subsequent step. 
     As also illustrated in  FIG. 3A , partially etched surfaces  227  and  236  are formed where the first and second leads  220  and  230  are joined and diverge. In one embodiment, partially etched surfaces  227  and  236  are flush or continuous with each other. 
       FIG. 3B  illustrates an encapsulating step used in the manufacture of semiconductor package  200 . After the leadframe has been encapsulated, partially etched surfaces  227  and  236  (represented as broken lines in  FIG. 3B ) between the first and second leads  220  and  230  are located inside encapsulant  270 . Accordingly, these partially etched surfaces  227  and  236  serve to improve the bonding force between first and second leads  220  and  230  and the encapsulant  270 . 
       FIG. 3C  illustrates a channel formation step used in the manufacture of semiconductor package  200 . Four intersecting channels  280  are formed in the bottom surface of encapsulant  270 . The channels  280  extend lengthwise along the bottom surface of encapsulant  270 , thus forming a quad-shaped pattern. In one embodiment, the width of the channels  280  is smaller than that of the partially etched surfaces  227  and  236  between the first leads  220  and the second leads  230 , thus ensuring that the bonding force between the first and second leads  220  and  230  and the encapsulant  270  is not weakened by the formation of the channels  280 . The depth of channels  280  is slightly greater than the thickness of the first and second leads  220  and  230 . 
       FIGS. 4A–B  illustrate a semiconductor package  300  having two parallel channels between first and second leads of the package. Semiconductor package  300  includes a plurality of first leads  320  having opposed, substantially planar top and bottom surfaces  322  and  324 , a plurality of second leads  330  having opposed, substantially planar top and bottom surfaces  332  and  334 , an integrated circuit die  350  having opposed, substantially planar top and bottom surfaces  352  and  354 , and a plurality of conductive wires  360  for electrically connecting the integrated circuit die  350  to the first and second leads  320  and  330 . Encapsulant  370  is also provided for encapsulating the first and second leads  320  and  330 , the integrated circuit die  350 , and the conductive wires  360 . In addition, portions of the first and second leads  320  and  330  are exposed in an exterior surface of the encapsulant  370  (i.e., the bottom surface thereof). 
     As illustrated in  FIG. 4B , the first leads  320  are arranged in a spaced, generally parallel pair of rows, with the first leads  320  of one row being aligned with respective ones of the first leads  320  of the remaining row. The first leads  320  of such rows are separated from each other at a predetermined distance. The bottom surfaces  324  of first leads  320  are partially etched to form partially etched surfaces  326  and  327  having a predetermined depth. 
     As also illustrated in  FIG. 4B , the second leads  330  are also segregated into a spaced, generally parallel pair of rows which are disposed outwardly of the rows of the first leads  320 . More particularly, each row of the second leads  330  is separated from a respective row of the first leads  320  by a predetermined distance, the second leads  330  of each row extending to a respective one of an opposed pair of sides of the encapsulant  370 . The second leads  330  of each row are aligned with respective ones of the first leads  320  of the row disposed closest thereto. The bottom surfaces  334  of second leads  330  are partially etched to form partially etched surfaces  336  having predetermined depths. 
     The bottom surface  354  of die  350  is placed upon and bonded to inner portions of the top surfaces  322  of the first leads  320  through the use of an adhesive  340 . A plurality of bond pads  356  formed at the top surface  352  of die  350  are connected to top surfaces  322  and  332  of first and second leads  320  and  330  by a plurality of conductive wires  360 . As seen in  FIG. 4A , the die  350  is sized relative to the first leads  320  so as to overlap those portions of the first leads  320  including the partially etched surfaces  326  formed therein. 
     As illustrated in  FIG. 4B , two channels  380  having predetermined depths are formed or cut in the bottom surface of the encapsulant  370 . Channels  380  are formed between the partially etched surfaces  327  of the first leads  320  and the partially etched surfaces  336  of the second leads  330 , thus physically separating and electrically insulating the first and second leads  320  and  330  from each other. In one embodiment, the channel depth is slightly greater than the thickness of the first and second leads  320  and  330 . As also illustrated in  FIG. 4B , the channels  380  extend in spaced, generally parallel relation to each other between respective ones of the corresponding rows of the first leads  320  and the second leads  330 . After channels  380  are formed, side surfaces  328  and  338  adjacent to the partially etched surfaces  327  and  336  of the first and second leads  320  and  330  are exposed in the encapsulant  370  within the channels  380 . 
       FIG. 5A  is a sectional view of a semiconductor package  400  having a die mounted flush with the bottom surface of the package  400 .  FIG. 5B  is a bottom view of the semiconductor package  400  of  FIG. 5A . As shown, semiconductor package  400  includes a plurality of first leads  420  having opposed, substantially planar top and bottom surfaces  422  and  424 , a plurality of second leads  430  having opposed, substantially planar top and bottom surfaces  432  and  434 , an integrated circuit die  450  having opposed, substantially planar top and bottom surfaces  452  and  454 , and a plurality of conductive wires  460  for electrically connecting the integrated circuit die  450  to the first and second leads  420  and  430 . Encapsulant  470  is also provided for encapsulating the first and second leads  420  and  430 , the integrated circuit die  450 , and the conductive wires  460 . In addition, portions of the first and second leads  420  and  430  are exposed in an exterior surface of the encapsulant  470 . 
     First leads  420  are symmetrically arrayed in a square or quadrangular pattern about the periphery of the die  450  and separated from each other at a predetermined distance. The bottom surfaces  424  of first leads  420  are partially etched to form partially etched surfaces  426  and  427  having predetermined depths. 
     As also illustrated in  FIG. 5B , the second leads  430  are also arranged in a square or quadrangular pattern outboard of the first leads  420 . The second leads  430  are separated from the first leads  420  by a predetermined distance, and extend to respective ones of the four peripheral sides or edges defined by the encapsulant  470 . As further shown in  FIG. 5B , the first and second leads  420  and  430  are provided in equal numbers, with each of the first leads  420  being aligned with a respective one of the second leads  430 . The bottom surfaces  434  of second leads  430  are partially etched to form partially etched surfaces  436  having predetermined depths. 
     As illustrated in  FIG. 5A , integrated circuit die  450  is located in the open area defined by the first leads  420  and is substantially flush with bottom surfaces  424  and  434  of the first and second leads  420  and  430 . 
     A plurality of bond pads  456  formed at the top surface  452  of die  450  are connected to top surfaces  422  and  432  of first and second leads  420  and  430  by a plurality of conductive wires  460 . 
     Channels  480  having predetermined depths are further formed in the bottom surface of the encapsulant  470  in a generally square pattern between the first leads  420  and the second leads  430 , thus separating the first and second leads from each other. Channels  480  are formed between the partially etched surfaces  427  of the first leads  420  and the partially etched surfaces  436  of the second leads  430 . The depth of the channels  480  is slightly larger than the thickness of first and second leads  420  and  430 . As illustrated in  FIG. 5B  and as indicated above, four intersecting channels  480  can be provided that extend lengthwise along the bottom surface of encapsulant  470  forming a quad-shaped pattern. As illustrated in  FIG. 5B , side surfaces  428  and  438  adjacent to the partially etched surfaces  427  and  436  of the first and second leads  420  and  430  are exposed in the encapsulant  470  within the channels  480 . Thus, channels  480  allow first and second leads  420  and  430  to be physically separated and electrically insulated from each other. Since bottom surfaces  424  and  434  of the first and second leads  420  and  430  are arrayed on the lower surface of the encapsulant  470  and exposed therein, the number of input and output pads is maximized in the semiconductor package  400 . 
       FIG. 6A  is a sectional view of a semiconductor package  500  having leads separated by a single channel.  FIG. 6B  is a bottom view of the semiconductor package  500  of  FIG. 6A . As shown, semiconductor package  500  includes a plurality of first leads  520  having opposed, substantially planar top and bottom surfaces  522  and  524 , a plurality of second leads  530  having opposed, substantially planar top and bottom surfaces  532  and  534 , an integrated circuit die  550  having opposed, substantially planar top and bottom surfaces  552  and  554 , and a plurality of conductive wires  560  for electrically connecting the integrated circuit die  550  to the first and second leads  520  and  530 . 
     Encapsulant  570  is also provided for encapsulating the first and second leads  520  and  530 , the integrated circuit die  550 , and the conductive wires  560 . In addition, bottom surfaces  524  and  534  of the first and second leads  520  and  530  are exposed in an exterior surface of the encapsulant  570  (i.e., the bottom surface thereof). 
     The first leads  520  are arranged in a spaced, generally parallel pair of rows which are separated from each other at a predetermined distance. The first leads  520  of each row are aligned with and extend in opposed relation to a respective one of the first leads  520  of the remaining row. The bottom surfaces  524  of first leads  520  are partially etched to form partially etched surfaces  527  having a predetermined depth. In addition, the top surfaces  522  of first leads  520  are partially etched to form partially etched surfaces  526  having a predetermined depth. 
     The second leads  530  are also segregated into a spaced, generally parallel pair of rows which extend to respective ones of an opposed pair of peripheral sides of the encapsulant  570 . The second leads  530  of each row are separated from a respective row of the first leads  520  by a predetermined distance. Additionally, the second leads  530  of each row are aligned with respective ones of the first leads  520  of the row disposed closest thereto. Thus, the first and second leads  520  and  530  are provided in equal numbers. The bottom surfaces  534  of second leads  530  are partially etched to include partially etched surfaces  336  having predetermined depths. 
     The bottom surface  554  of die  550  is placed upon and bonded to inner portions of the top surfaces  522  of the first leads  520  through the use of an adhesive  540 . A plurality of bond pads  556  formed at the top surface  552  of die  550  are connected to top surfaces  522  and  532  of first and second leads  520  and  530  by conductive wires  560 . 
     As illustrated in  FIGS. 6B and 7A , a die paddle  510  having a predetermined area interconnects the first leads  520 , and accommodates the integrated circuit die  550  so that it can be bonded in a stable manner to the first leads  520 . In one embodiment, die paddle  510  has the same thickness as the first leads  520  and is flush with the first leads  520 . As shown in  FIG. 7A , the die paddle  510  includes a partially etched surface  526  which extends into portions of each of the first leads  520 . 
     A single channel  580  having a predetermined depth is formed between those portions of the partially etched surface  526  extending into each of first leads  520 . Channel  580  serves to electrically insulate and physically/symmetrically separate the first leads  520  from each other. In one embodiment, the depth of channel  580  is selected to pass through a portion of the partially etched surface  526  without damaging integrated circuit die  550 . As a result of the formation of the channel  580 , a portion of the partially etched surface  526  remains in the inner end of each of the first leads  520 , thus resulting in each of the first leads  520  defining a partially etched surface  526  as indicated above. After channel  580  is formed, side surfaces  528  adjacent to the partially etched surfaces  526  of the first leads  520  are exposed in the encapsulant  570  within the channel  580 . 
       FIGS. 7A–F  are views illustrating steps in a method for manufacturing semiconductor package  500  of  FIG. 6A .  FIGS. 7A and 7B  illustrate plan and sectional views of a lead frame providing step used in the manufacture of semiconductor package  500  of  FIG. 6A . Die paddle  510  is provided having a partially etched surface  526  at its upper center portion, with first leads  520  extending from each of the opposed sides of the die paddle  510 . A predetermined part of the partially etched surface  526  is removed during a subsequent channel formation step (illustrated in  FIG. 7F ). As illustrated in  FIG. 7B , partially etched surface  526  is of a prescribed depth relative to the top surfaces  522  of first leads  520 . 
       FIG. 7C  illustrates a die attaching step used in the manufacture of semiconductor package  500  of  FIG. 6A . The bottom surface  554  of the integrated circuit die  550  is placed upon and bonded to the opposed end portions of the die paddle  510  and the top surfaces  522  of the first leads  520  through the use of an adhesive  540 . 
       FIG. 7D  illustrates a wire bonding step used in the manufacture of semiconductor package  500  of  FIG. 6A . The bond pads  556  of the integrated circuit die  550  are electrically connected to the top surfaces  522  and  532  of the first and second leads  520  and  530  through the use of conductive wires  560 . 
       FIG. 7E  illustrates an encapsulating step used in the manufacture of semiconductor package  500  of  FIG. 6A . First and second leads  520  and  530 , integrated circuit die  550 , and conductive wires  560  are encapsulated by the encapsulant  570 . The encapsulant  570  protects these components from the external environment and allows semiconductor package  500  to be mounted on external devices in a fixed shape. After the encapsulating step, bottom surfaces  524  and  534  of the first and second leads  520  and  530  are exposed in the bottom surface of the encapsulant  570 . 
       FIG. 7F  illustrates a channel forming step used in the manufacture of semiconductor package  500  of  FIG. 6A . A single channel  580  having a predetermined depth is formed between the first leads  520 , and passes through a portion of the partially etched surface  526 . As a result, facing first leads  520  are physically separated and electrically insulated from each other. In one embodiment, a substantial portion of die paddle  510  is removed as a result of the cutting of channel  580 . The width of channel  580  can be made smaller than that of partially etched surface  526  such that a predetermined region of the partially etched surface  526  is located on the inside of encapsulant  570 . As previously explained, the cutting operation is completed such that a portion of the partially etched surface  526  remains on the inner end of each of the first leads  520  as is seen in  FIG. 7F . The depth of channel  580  is preferably less than the thickness of the first leads  520  in order to prevent damage to integrated circuit die  510 . 
     As a result of these manufacturing steps, the first and second leads  520  and  530  can be arrayed on package  500  as illustrated in  FIG. 6B , thereby maximizing the number of input and output pads in the semiconductor package  500 . 
       FIG. 8A  is a sectional view of a semiconductor package  600  having leads separated by a single channel.  FIG. 8B  is a bottom view of the semiconductor package  600  of  FIG. 8A . It will be appreciated that the structure of package  600  is similar to the structure of package  500  described above. However, the die paddle  510  included in the semiconductor package  500  is not included in the semiconductor package  600 . Instead, in the semiconductor package  600 , integrated circuit die  650  is placed upon and bonded to top surfaces  622  of first leads  620  without the inclusion of a die paddle interconnecting the first leads  620 . Thus, in contrast to package  500 , first leads  620  of package  600  are not connected to a die paddle. 
       FIG. 9A  is a sectional view of a semiconductor package  700  having a die pad and leads separated by two channels.  FIG. 9B  is a bottom view of the semiconductor package  700  of  FIG. 9A . As shown, semiconductor package  700  includes a plurality of first leads  720  having opposed, substantially planar top and bottom surfaces  722  and  724 , a plurality of second leads  730  having opposed, substantially planar top and bottom surfaces  732  and  734 , a die pad  710  having opposed, substantially planar top and bottom surfaces  712  and  714 , an integrated circuit die  750  having opposed, substantially planar top and bottom surfaces  752  and  754 , and a plurality of conductive wires  760  for electrically connecting the integrated circuit die  750  to the first and second leads  720  and  730 . 
     Encapsulant  770  is also provided for encapsulating the first and second leads  720  and  730 , the die pad  710 , the integrated circuit die  750 , and the conductive wires  760 . In addition, bottom surfaces  714 ,  724 , and  734  of the leads  720  and  730  and die pad  710  are exposed in an exterior surface of the encapsulant  770  (i.e., the bottom surface thereof). 
     The first leads  720  are arranged in a spaced, generally parallel pair of rows which are separated from each other at a prescribed distance. The bottom surfaces  724  of first leads  720  are partially etched to form partially etched surfaces  727  having a predetermined depth. In addition, the top surfaces  722  of first leads  520  are partially etched to form partially etched surfaces  726  having a predetermined depth. 
     The second leads  730  are also segregated into a spaced, generally parallel pair of rows which are outboard of the first leads  720  and separated from a respective row of the first leads  720  by a predetermined distance, the second leads  730  extending to respective ones of an opposed pair of sides of the encapsulant  770 . The second leads  730  of each row are aligned with respective ones of the first leads  720  of the row disposed closest thereto. Thus, the first and second leads  720 ,  730  are provided in equal numbers. The bottom surfaces  734  of second leads  730  are partially etched to form partially etched surfaces  736  having a predetermined depth. 
     The top surface  712  of die pad  710  is also partially etched to form partially etched surfaces  716  having a predetermined depth. 
     The bottom surface  754  of die  750  is placed upon and bonded to the top surfaces  712  and  722  of the die pad  710  and first leads  720  through the use of an adhesive  740 . A plurality of bond pads  756  formed at the top surface  752  of die  750  are connected to top surfaces  722  and  732  of first and second leads  720  and  730  by conductive wires  760 . 
     Two channels  780  having predetermined depths are formed between the first leads  720  and the die paddle  710 , thus separating the first leads  720  from the die paddle  710 . In one embodiment, the channel depth is selected so as to sever portions of die paddle  710  and first leads  720  without damaging die  750 . As a result of forming channels  780 , side surfaces  718  and  728  adjacent to partially etched surfaces  716  and  726  of the die paddle  710  and the first leads  720  are exposed in the encapsulant  770  within the channels  780 . 
       FIG. 10  is a sectional view of a semiconductor package  800  having multiple dies attached to first and second leads. Semiconductor package  800  includes a plurality of first leads  820  having opposed, substantially planar top and bottom surfaces  822  and  824 , a plurality of second leads  830  having opposed, substantially planar top and bottom surfaces  832  and  834 , a plurality of third leads  890  having opposed, substantially planar top and bottom surfaces  892  and  894 , two integrated circuit dies  850  having substantially planar top and bottom surfaces  852  and  854 , and a plurality of conductive wires  860  for electrically connecting the integrated circuit dies  850  to the first, second, and third leads  820 ,  830 , and  890 . Encapsulant  870  is also provided for encapsulating the first, second, and third leads  820 ,  830 , and  890 , integrated circuit die  850 , and conductive wires  860 . In addition, portions of the first, second, and third leads  820 ,  830 , and  890  are exposed in an exterior surface of the encapsulant  870  (i.e., the bottom surface thereof). 
     The bottom surfaces  824  of first leads  820  are partially etched to form partially etched surfaces  826  and  827  having a predetermined depth. The bottom surfaces  834  of second leads  830  are also partially etched to form partially etched surfaces  836  having a predetermined depth. In addition, the bottom surfaces  894  of third leads  890  are partially etched to form partially etched surfaces  896  having a predetermined depth. 
     First leads  820  are arranged in a spaced, generally parallel pair of rows which are separated from each other at a predetermined distance, with each of the first leads  820  of one row being aligned with a respective one of the first leads  820  of the remaining row. The second leads are also segregated into a spaced, generally parallel pair of rows which are outboard of the rows of first leads  820 . In this regard, the rows of second leads  830  are separated from a respective row of the first leads  820  by a predetermined distance, with the second leads  830  of each row being aligned with respective ones of the first leads  820  of the row disposed closest thereto. In a similar fashion, the third leads  890  are also segregated into two generally parallel rows which are outboard of the rows of second leads  830  and separated from a respective row of the second leads  830  by a predetermined distance. The third leads  890  of each row are preferably aligned with respective ones of the second leads  830  of the row disposed closest thereto. Thus, the first, second and third leads  820 ,  830  and  890  are preferably provided in equal numbers. 
     The bottom surfaces  854  of dies  850  are placed upon and bonded to the top surfaces  822  and  832  of the first and second leads  820  and  830  through the use of an adhesive  840 . A plurality of bond pads  856  formed at the top surfaces  852  of dies  850  are connected to certain ones of the first, second and third leads  820 ,  820  and  890  by conductive wires  860 . 
     As illustrated in  FIG. 10 , three channels  880  having predetermined depths are formed in the bottom surface of the encapsulant  870 . Two of the channels  880  are formed between partially etched surfaces  837  of the second leads  830  and the partially etched surfaces  896  of the third leads  890 , thus physically separating and electrically insulating the second and third leads  830  and  890  from each other. A third channel  880  is formed between partially etched surfaces  826  of first leads  820 , thus physically separating and electrically insulating the first leads  820  from each other. In one embodiment, the channel depth is selected to be slightly larger than the thickness of the first, second or third leads  820 ,  830  or  890 . 
     As a result of forming channels  880 , side surfaces  828  of the first leads  820  as well as side surfaces  838  and  898  of second and third leads  830  and  890  are exposed in the encapsulant  870  within respective ones of the channels  880 . 
       FIG. 11  is a sectional view of a semiconductor package  900  having multiple stacked dies. It will be appreciated that the structure of package  900  is similar to the structure of package  100  described above. However, package  900  further includes an additional integrated circuit die. 
     As shown in  FIG. 11 , package  900  includes a first integrated circuit die  950  bonded to a top surface  912  of a die paddle  910  by an adhesive  940 . A second integrated circuit die  950 ′ is bonded to a top surface  952  of the first integrated circuit die  950  through the use of an adhesive  940 ′. The second integrated circuit die  950 ′ includes opposed, substantially planar top and bottom surfaces  952 ′ and  954 ′, and bond pads  956 ′ formed on the top surface  952 ′. Bond pads  956 ′ of the second integrated circuit die  950 ′ are electrically connected to the first and second leads  920  and  930  through the use of conductive wires  960 . 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.