Abstract:
A high-resolution apparatus and method provide direct digital measurement of electrical properties such as resistance, capacitance or inductance. An excitation signal derived from a high-frequency source is applied to a network containing an unknown device to produce a network output signal with an amplitude that corresponds to the electrical property to be measured. Amplitude variations in the network output signal are converted to corresponding phase variations in a third signal by adding the network output signal to a reference signal that is phase shifted by 90-degrees with respect to the excitation. The third signal is then applied to a phaselocked loop that employs the above-mentioned high-frequency source in combination with a pulse delete circuit to produce an output that multiplies phase information contained in the third signal by orders of magnitude. Conventional methods can then be used to measure the resulting greatly magnified phase changes corresponding to minute changes in the electrical properties of the device under test.

Description:
SPECIFICATION  
       [0001]    This is a continuation in part of application Ser. No. 09/563,295 filed May 3, 2000, and takes the benefit of provisional application No. 60/132,424 filed May 4, 1999, incorporated herein by reference. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention is concerned with measurement of physical phenomena, properties or conditions such as values of resistance, capacitance or inductance, for example, and is more particularly concerned with apparatus and methods for direct digital measurement of minute changes in electrical properties that correspond to changes in related physical phenomena such as mechanical strain, displacement or temperature, for example.  
         BACKGROUND  
         [0003]    Strain gages and resistive temperature sensors are inexpensive and have been widely used for decades for mechanical design, test and measurement. Various configurations of strain gages are widely employed to measure pressure, weight, torque and mechanical displacement in addition to the direct measurement of strain in engineering design and test. Far more widespread use of such sensors for monitoring, detection and warning of conditions that could, for example, indicate an impending failure has been impeded by the cost, and, to some extent, the size and complexity, of electronics required to convert resistance values to useful measurements. Similar considerations have also limited more extensive use of capacitance and inductance sensors.  
           [0004]    Measurements of physical phenomena that produce resistance or reactance changes typically employ a four-element Wheatstone bridge comprising a combination of one or more sensor elements with fixed-value passive components. Such a network is termed a quarter-, half- or full-bridge configuration depending upon whether one, two or all four of the elements are sensors. The Wheatstone bridge configuration is ideal for maximizing measurement sensitivity. This is accomplished by selecting component values to provide zero output for the unstressed or no-load condition, allowing the bridge output signal to be greatly amplified.  
           [0005]    In the prior art, a precisely-controlled, fixed DC voltage is applied to the Wheatstone bridge or other network containing the sensing elements. The output is then amplified, with additional circuitry employed to cancel DC offset errors introduced by the amplifier circuits. The amplified DC analog signal is then applied to an analog-to-digital converter to obtain a digital output. This approach involves considerable cost and complexity and is susceptible to errors due to lead length, noise pickup and other error sources such as ambient-temperature variations.  
           [0006]    It is often required to measure outputs from multiple independent sensors, either simultaneously or in a repeating sequence. Prior art teaches the use of analog multiplexers, sample-and-hold circuits, together with associated control circuits such as scan, trigger, and address decode to implement such multi-channel systems. This additional cost and complexity further limits more widespread use of low-cost passive sensors.  
         BRIEF SUMMARY OF THE INVENTION  
         [0007]    It is accordingly an object of the present invention to provide an apparatus and method for precise, high-resolution direct digital measurement of phenomena which produce changes in electrical properties such as resistance, capacitance and inductance.  
           [0008]    Another object of the invention to provide an apparatus and method of the above-described type capable of multiple independent, simultaneous measurements using a single reference oscillator and logic device.  
           [0009]    Another object of the invention is to minimize noise sensitivity in an apparatus and method of the above-described type by employing synchronous detection of low-frequency sensor signals to achieve extremely narrow noise bandwidth.  
           [0010]    Another object of the invention to provide an apparatus and method of the above-described type which is low in cost.  
           [0011]    Another object of the invention is to minimize errors due to temperature and voltage variations in an apparatus and method of the above-described type through the use of excitation and reference signals derived from a common source.  
           [0012]    It is a further object of the invention is to eliminate the need for DC offset correction by employing AC excitation.  
           [0013]    Briefly stated, the present invention provides high-accuracy, high-resolution apparatus, systems and methods that employ phase shifts in a fixed-frequency signal for measurement of electrical properties such as capacitance, inductance or resistance.  
           [0014]    In accordance with a preferred embodiment of the invention, two sinusoidal signals of identical frequency and 90 degrees out of phase are generated from a single reference oscillator. One is designated “excitation,” the other, “reference.” 
           [0015]    The excitation signal is applied to a network such as a Wheatstone bridge comprising both fixed-value components and one or more sensing elements. The values of the bridge components are preferably selected to provide minimum voltage output when the sensing elements are unstressed and an output level (amplitude) proportional to stress applied to the sensing elements when a stress such as a force or temperature change is applied.  
           [0016]    The output of the bridge is amplified and then applied as one input to a summing amplifier, the other input being the above-described reference signal. All signal levels are constrained to remain within the linear range of amplifier circuitry employed.  
           [0017]    As the amplified output of the Wheatstone bridge ranges from zero to a maximum amplitude equal to that of the reference signal, the phase θ of the summing amplifier output with respect to the reference signal will vary from 0° to 45°.  
           [0018]    High-resolution measurement of θ is accomplished by applying the summing amplifier output to a unique phaselocked loop mechanization to produce a loop output signal that multiplies phase changes in the summing amplifier output by orders of magnitude. In the loop, the input from the summing amplifier and the loop feedback signal are applied to a phase detector, the output of which is used to produce a loop output signal at a frequency that is a multiple of the summing amplifier input frequency. The loop output signal is used to delete pulses from the reference oscillator signal, which is at a much higher frequency than the loop output signal. The output of the pulse delete circuit is then applied to a divider, the output of which is equal in frequency to the summing amplifier input signal. The result of this arrangement is that phase changes in the summing amplifier input to the loop are multiplied in the loop output by the same constant used to divide down the output of the pulse delete circuit.  
           [0019]    The loop output signal is then compared with a signal at the same frequency derived from the reference oscillator using logic that converts cycle slips between the two signals into up/down counts. The resulting up/down counts can then be directly applied to an indicating device, recorder or to a microprocessor or microcontroller. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    The invention will be further described in conjunction with the accompanying drawings, which illustrate preferred and exemplary embodiments, and wherein:  
         [0021]    [0021]FIG. 1 is a block diagram of an apparatus for direct digital measurement of phenomena that produce changes in electrical resistance in accordance with the invention.  
         [0022]    [0022]FIG. 2 is a detailed block diagram of a FREQUENCY REFERENCE shown in FIG. 1.  
         [0023]    [0023]FIG. 3 is a schematic diagram of a BANDPASS FILTER shown in FIG. 1.  
         [0024]    [0024]FIG. 4 is a diagram, partly in block form and partly in schematic, of a SENSOR ANALOG CIRCUIT shown in FIG. 1.  
         [0025]    [0025]FIG. 5 is a schematic diagram of a VARIABLE GAIN AMPLIFIER shown in FIG. 4.  
         [0026]    [0026]FIG. 6 is a graph depicting the relationship between the measured phase angle and the relative amplitude of the amplified bridge output with respect to the reference signal.  
         [0027]    [0027]FIG. 7 is a schematic diagram of a FILTER/LIMITER shown in FIG. 1.  
         [0028]    [0028]FIG. 8 is a detailed block diagram of a PLL (phaselocked loop) shown in FIG. 1.  
         [0029]    [0029]FIG. 9 is An explanatory waveform diagram depicting certain timing relationships within the phaselocked loop.  
         [0030]    [0030]FIG. 10 is a detailed block diagram of a PULSE DELETE circuit employed in the phaselocked loop of FIG. 8.  
         [0031]    [0031]FIG. 11 is a detailed block diagram of the U/D CONVERTER of FIG. 1.  
         [0032]    [0032]FIG. 12 a  and FIG. 12 b  are schematic diagrams of Wheatstone bridge networks for inductance and capacitance measurement, respectively.  
         [0033]    [0033]FIG. 13 is a block diagram of apparatus for direct digital measurement of multiple independent phenomena that produce changes in electrical properties in accordance with the invention.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0034]    [0034]FIG. 1 is a block diagram of one embodiment of the invention. In a physical implementation, functions performed within the Frequency Reference  1 , PLL (phaselocked loop)  2  and U/D (up/down) Converter  3  are preferably combined within a single programmable logic device such as a field-programmable gate array (FPGA), application-specific integrated circuit (ASIC) or the like. The primary frequency source is a 20 MHz Clock  7 . Bandpass Filters  4 , Sensor Analog Circuit  5  and Filter/Limiter  6  comprise physically distinct analog circuits, the latter two comprising the Sensor Group  8 , enclosed within a dashed line in the figure.  
         [0035]    [0035]FIG. 2 is a detailed block diagram of Frequency Reference  1  (FIG. 1). The square-wave output of 20 MHz Clock  7  is used to synthesize four signals, which, together with the clock signal, comprise the five outputs of the Frequency Reference. These signals are used to implement the functions performed by the other blocks in FIG. 1.  
         [0036]    The 20 MHz. Clock  7  is a widely available commercial device. Its output is applied to Divide-by-501 circuit  9  followed by Divide-by-2 circuit  10 , both of conventional design, to produce Output #2 of approximately 19,960.08. Hz. The Divide-by-2 circuit  10  assures that Output #2 will be symmetrical (i.e., exactly 50 percent duty cycle).  
         [0037]    The output of Divide-by-501  9  is also applied to inverter  11  followed by Divide-by-2  12  to produce Output #3 in phase quadrature with Output #2 (i.e., the two signals are exactly 90 degrees out of phase).  
         [0038]    The output of Divide-by-501  9  is also applied to Divide-by-160 circuit  13 , then to Divide-by-2  14  to obtain symmetrical output #4 at approximately 124.75 Hz. The output of Divide-by-160  13  is also applied to inverter  15 , followed by Divide-by-2  16  to produce output #5 in phase quadrature with Output #4.  
         [0039]    Square wave outputs #4 and #5 are applied to identical Bandpass filters  4  (FIG. 1). FIG. 3 is a schematic diagram of a typical filter of this type.  
         [0040]    Again referring to FIG. 1, the sinusoidal outputs of Bandpass Filters  4  are then applied as inputs to Sensor Analog Circuit  5 . FIG. 4 is a detailed diagram of Sensor Analog Circuit  5  (FIG. 1), partly in schematic and partly in block form. The phase quadrature output of Bandpass Filter #2  4  (FIG. 1), designated “excitation,” is applied to Wheatstone Bridge  17  containing resistors R 1 , R 2 , R 3  and R 4 , at least one of which is a sensor element. The Wheatstone Bridge is a typical circuit configuration for measuring changes in resistance. The input voltage is applied at the junction of R 1  and R 3  relative to the junction of R 2  and R 4  (ground). The bridge output is measured from the junction of R 1  and R 2  to the junction of R 3  and R 4 . The bridge is said to be “balanced” when the ratio R 1 /R 2  is equal to the ratio of the parallel combination of R 3  and potentiometer P 2  divided by R 4 . In a balanced state, the bridge output is zero. Bridge component values are selected so that a balanced condition exists when the sensor is unstressed, permitting outputs resulting from minute sensor resistance changes to be greatly amplified to maximize measurement sensitivity. Potentiometer P 2  provides a means for fine balancing the output of Wheatstone Bridge  17 .  
         [0041]    Typically, one, two or all four resistors in the Wheatstone Bridge are sensor elements, designating the arrangement as a quarter, half, or full bridge, respectively.  
         [0042]    The output of Wheatstone Bridge  17  is applied to balanced amplifier  18 . A typical amplifier of this type consists of one half of a Burr Brown INA 2132, Dual Difference Amplifier, which contains internal laser-trimmed resistors to provide precise gain and high common mode rejection without the need for precision external resistors.  
         [0043]    The output of balanced amplifier  18  is then applied to Variable Gain Amplifier  19 , a typical design of which is shown in schematic form in FIG. 5. Variable Gain Amplifier  19  consists of fixed-gain, bandpass amplifier stage  20 , followed by gain control potentiometer P 1   21 , which is used to adjust the overall gain of the circuit. Potentiometer P 1   21  is followed by a second bandpass amplifier  22 .  
         [0044]    Again referring to FIG. 4, he output of Variable Gain Amplifier  19  is applied to one input of balanced difference amplifier  23 , which comprises the second half of previously-mentioned Burr Brown Dual Difference Amplifier INA 2132. The other input to Difference Amplifier  23  is the “in-phase” 124.75 Hz [0°] “Reference” input signal.  
         [0045]    The amplitude of inputs to difference amplifier  23  are constrained as follows:  
         [0046]    1) Gain control potentiometer P 1   21  (FIG. 5) is adjusted so that the maximum amplitude of the output of Variable Gain Amplifier  19  (FIG. 4) does not exceed the amplitude of the Reference signal to the other input to Difference Amplifier  23 , and  
         [0047]    2) The amplitude of both signals is such that Difference Amplifier  23  is always operating in its linear range.  
         [0048]    When these two conditions are met, the phase of the output signal of Difference Amplifier  23  relative to the Reference input will vary between 0° when the output of Variable Gain Amplifier  19  is equal to zero and  45 ° when the amplitude of both inputs to Difference Amplifier  23  are equal.  
         [0049]    The phase φ of the output of Difference Amplifier  23  relative to the Reference input is equal to the arctangent of the ratio of the amplitude of the two input signals, given by  
         φ= Arctan[E   VG   /E   ref ] 
         [0050]    where E VG  is the amplitude of the output of Variable Gain Amplifier  19 , and E ref  is the amplitude of the Reference input signal. This relationship is shown graphically in FIG. 6.  
         [0051]    The phase-shifted sine wave output of Difference Amplifier  23  (FIG. 4), which corresponds to the output of Sensor Analog Circuit  5  (FIG. 1), is then applied to Filter/Limiter  6  (FIG. 1). FIG. 7 is a schematic of a typical Filter/Limiter circuit of this type. The circuit consists of an active filter followed by a limiter comprising one stage of a 74ACT14 hex inverting Schmitt Trigger.  
         [0052]    Referring to FIG. 1, output of Filter/Limiter  6  is applied to phaselocked loop, PLL  2 . PLL  2  is a digital phaselocked loop, implemented entirely within the previously mentioned logic array (FPGA or ASIC). FIG. 8 shows the detailed logic flow within PLL  2  (FIG. 1). When the loop is locked, inputs to XOR (exclusive OR)  24  from Filter/Limiter  6  (FIG. 1) and Divide by 80,000  25  will be identical in frequency and 90 degrees out of phase, causing the output of XOR  24  to be high during 50 percent of each 124.75 Hz cycle.  
         [0053]    [0053]FIG. 9 shows the timing relationships among the inputs and output of XOR  24  and the outputs of AND #1  26  and AND #2  27  when the loop is locked. Due to the 90-degree phase relationship between the inputs to XOR  24 , its output alternates between high and low at quarter-cycle intervals. This permits bursts of the 125 kHz output of Divide by 160  28  to appear at the output of AND #1  26 . At lock, the number of pulses in each burst will average  
         (114 cycle)×(125,000  HZ )×(1/124.75  Hz )=250.5 pulses  
         [0054]    These bursts of pulses from AND #1  26  and the loop feedback signal from Divide by 80,000  25  are then applied to AND #2  27 . From FIG. 9, it can be seen that only one of the two bursts of pulses appearing at the output of AND #1  26  during each cycle is passed to Count Register  29 . Count Register  29  is preset to an initial value A 0  of 251 each cycle, so that, at lock, Count Register  29  will, on average, count to 501.5 (250.5+251). This value is transferred to Divide by Even M  30  each cycle, then reset to 251 to await the next burst from AND #2  27 . The current value of M is used to divide the 20 MHz Reference input to Divide by Even M  30 . The divisor M is forced to be an even number by ignoring its least significant bit (LSB). This prevents M from being exactly equal 501, which would produce a frequency at the output of the Divide by 80,000  25  exactly matching the input frequency, thereby causing the loop to converge to slightly different steady state phase errors depending upon whether the initial phase error is positive or negative.  
         [0055]    The output of Divide by Even M  30  is then applied to Divide-by-2  31 , which assures that the loop output will be a symmetrical.  
         [0056]    To close the phaselocked loop, the (approximately) 20,000 Hz output signal is applied to Pulse Delete Circuit  32 . This circuit removes exactly one pulse from the 10 MHz signal obtained by applying the 20 MHz Clock to Divide by 2  33  for each negative-to-positive transition of the delete rate (˜20 kHz) signal.  
         [0057]    Pulse Delete  32  (FIG. 8) is shown in detailed block diagram form in FIG. 10. After each pulse delete occurs, the input D flip-flop (FF 1 ) is reset via NAND  3  to wait for the next positive transition of the delete rate signal.  
         [0058]    Again referring to FIG. 8, the pulse train output of Pulse Delete  32  is applied to Divide-by-80,000  25  of conventional design. The output of Divide by 80,000  25  is a 124.75 Hz [(10,000,000−20,000)/80,000] signal with negligible jitter of just ±0.00225°.  
         [0059]    As previously stated, the condition of lock exists when the two signals applied to XOR  24  are 90 degrees out of phase. Any phase deviation from that condition will cause the total number of pulses in the burst delivered to Count Register  29  each cycle to increase (or decrease) from its nominal average value of 250.5, thereby causing the output frequency to decrease (or increase) accordingly to drive the phase of the output of Divide-by-80,000  25  toward lock.  
         [0060]    Referring to FIG. 1, the output of PLL  2  which is applied to U/D Converter  3  is the ˜20,000 Hz output of Divide by 2  31  (FIG. 8). Up and Down counts are obtained by counting cycle slips between the PLL output and Output #2 of Frequency Reference 1 (FIG. 1). For these two signals to be at precisely the same frequency, it is necessary that each be related to the 20 MHz Clock  7  by exactly the same factor. From FIG. 2 the frequency f 2  of Output #2 is given by  
           f   2 =20  MHz/ 1002  
         [0061]    At lock, the output of the Divide by 80,000  25  (FIG. 8) must match the frequency of Outputs #4 and #5 (FIG. 2), which are combined to produce the input to PLL  2  (FIG. 1) as previously described. To establish the relationship between the PLL output f 1  and the output of Divide by 80,000  25  (FIG. 8) it is only necessary to equate the relationship between the output of that circuit and the derivation of he Output #4 and #5 from the 20 MHz Clock,  
         (20  MHz/ 2 −f   1 )/80,000=20  MHz /(1002×160)  
         [0062]    Which simplifies to  
           f   1 =20  MHz/ 1002 =f   2    
         [0063]    [0063]FIG. 11 illustrates a preferred embodiment of the U/D Converter  3  (FIG. 1) including “D” flip-flops  34 , NAND gates  35 , Divide by  20  circuit  36  of conventional design, and XOR (exclusive OR) gates  37 , all of which are interconnected as shown. Although the circuit is shown and described in terms of conventional logic devices, it is preferably implemented within the previously described programmable logic array chip. The circuit provides a means for converting cycle slips between two signals at the same frequency to UP and DOWN counts.  
         [0064]    As shown above, the PLL output and Output #2 from Frequency Reference are locked to the same frequency, but with a varying phase relationship that corresponds to the quantity being measured. The arrangement of NAND gates  35  serves to prevent false triggering of counts due to noise or phase jitter.  
         [0065]    Each half-cycle phase change between the input signals produces a change in the output state of NAND  4 . A 1 MHz clock signal is produced by applying the output of  20  MHz Clock  7  (FIG. 1) to Divide-by-20  36 . This 1 MHz signal is used propagate the state of NAND  4  to flip-flops FF 4 , FF 5  and FF 6 , in sequence at  1  microsecond intervals. On each occurrence of a change in state of NAND  4 , the Q outputs of FF 5  and FF 6  will be different for one microsecond, causing a 1 microsecond positive “Count” pulse to appear at the output of XOR  1  for each half-cycle phase slip between the inputs.  
         [0066]    The quadrature 20 kHz output from Frequency Reference  1  (FIG. 1), Output #3, is used to clock the PLL output to the output of FF 3  so that the state of the PLL signal one quarter cycle before each transition of NAND  4  appears as one input to XOR 2 . The Q output of FF 4  provides the other input to XOR  2 . The direction of each count is then determined by whether the two inputs to FF 2  are different, causing the output of XOR 2  to be high (UP count), or the same, producing a low output from XOR  2  (DOWN count).  
         [0067]    A preferred embodiment of the invention has been described in terms of measurements performed on resistance sensors connected in a Wheatstone bridge network  17  (FIG. 4). Other embodiments employing capacitors, inductors and even combinations of passive components, either in a Wheatstone bridge or some other network configuration will be readily apparent to those skilled in the art. FIG. 12 depicts examples of inductance and capacitance Wheatstone bridge networks. Both the inductance version  38  and the capacitance version  39  employ resistors R 1  and R 2  and potentiometer P 1  in one leg of the bridge. This simplifies balancing the bridge and does not introduce a phase shift since the entire input signal e i  is applied across either purely resistive or purely inductive (or capacitive) elements.  
         [0068]    [0068]FIG. 13 depicts an embodiment of the invention useful for simultaneous measurement of outputs from multiple independent sensors. Only one 20 MHz Clock  7  (FIG. 1) is used. Likewise, previously described Bandpass Filters #1 and #2  4  (FIG. 1) are used just once in the multi-channel embodiment depicted in FIG. 13. The Frequency Reference  1  (FIG. 1), multiple PLLs (phaselocked loops)  2  (FIG. 1), and multiple U/D Converters  3  (FIG. 1) are all implemented within a single programmable logic device  40 , such as an ASIC or FPGA. A typical example of such a logic device is the Xilinx XCS30-3TQ144C, a 30,000-gate FPGA. Only the Sensor Group  8  (FIG. 1) is replicated for all channels. The Sensor Group  8  comprises the Sensor Analog Circuit  5  (FIG. 1) and Filter/Limited  6  (FIG. 1), both of which have been previously described.  
         [0069]    While preferred embodiments of the invention have been shown and described, these embodiments are to be considered exemplary rather than restrictive, and various modifications can be made without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims.