Abstract:
A digital controller for dc-dc switching converters can operate under light load conditions. The controller can be suitable for the use in switch-mode power supplies providing regulated output voltage for handheld devices and other low-power electronics. To create long time intervals, compared to the propagation time of digital logic a DPFM/DPAM can use a ring oscillator with two sets of delay cells and two signals racing around the ring.

Description:
CLAIM OF PRIORITY 
   This application claims priority from the following co-pending application, which is hereby incorporated in its entirety: U.S. Provisional Application No. 60/895,386 entitled: “DIGITAL PULSE FREQUENCY/PULSE AMPLITUDE (DPFM/DPAM) CONTROLLER FOR LOW-POWER SWITCHING-POWER SUPPLIES”, by Aleksandar Prodić, et al., filed Mar. 16, 2007, 

   BACKGROUND OF THE INVENTION 
   Digital control of low-power switching converters allows for numerous benefits including the ability to use digital design tools, flexibility in transferring to different implementation technology, and low sensitivity on external influences. 
   However, in battery-powered handheld devices, such as cell phones, digital still cameras (DSC), and personal data assistants (PDAs), analog controlled dc-dc switching converters are predominantly used. Among the main obstacles for successful digital implementation are lower switching frequency, compared to analog solutions, and the absence of low-power digital architectures that can support pulse-frequency modulation (PFM). The PFM results in significant efficiency improvement when the output load of a switch-mode power supply (SMPS) is light. In the handheld devices, to extend the battery life, the PFM is usually used when the supplied devices perform simple processing tasks or operate in stand-by mode. 
   In recent publications several low-power solutions that either support only digital pulse-width modulation control or combine a digital-pulse width modulator (DPWM) and an analog PFM have been presented. 
   The problem with analog implementation is that the analog controllers require relatively long design process and need to be almost completely redesigned each time implementation technology changes. As such, they are not suitable for monolithic integration with fast changing digital hardware, on which the majority of portable devices are based. Moreover, in the latest CMOS processes not all functional blocks of analog controllers can be implemented due to very limited supply voltages. 
   On the other hand, some DPFM are not suitable for low power switching converters either. To create a pulse-frequency modulated (PFM) signal, often characterized with short on and long off time intervals, some realizations use a high frequency clock and employs power-inefficient counters which make them unsuitable for low-power applications, where the overall efficiency of the SMPS is significantly affected by the power consumption of the controller. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a buck converter regulated by a DPFM/DPAM controller. 
       FIG. 2  illustrates a digital modulator of one embodiment of the present invention. 
       FIGS. 3-4  illustrate operation of a digital controller of one embodiment of the present invention. 
       FIG. 5  illustrates a chip layout of one embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   One challenge in designing a low-power digital pulse frequency modulator (DPFM) is the creation of long time intervals using very fast digital logic. Since the switching periods of SMPS operating in DPFM are several orders of magnitude larger than the propagation times of modern digital circuits, direct implementation of solutions used in DPWM architectures is impractical. Conventional ring oscillators would require several thousands of delay cells and huge on-chip area. On the other hand, counter-based DPFM architectures consume significant amount of power, especially when a large range of frequencies is required. 
   Some embodiments described below include a low-power digital pulse-frequency modulation/pulse-amplitude controller architecture that offers a solution for the previously mentioned problems and has the following unique characteristics. 
   The DPFM/DPAM controller can be fully realized using digital logic, allowing its implementation in the latest CMOS processes; 
   The DPFM/DPAM controller takes very small amount of power having a negligible effect on the overall SMPS efficiency; 
   The DPFM/DPAM can be implemented on a very small silicon area allowing economic implementation of the controller. This feature is extremely important in cost-sensitive portable applications. 
   Besides the operation as a pulse-frequency modulator, the DPFM/DPAM controller can also operate in a mode where both the switching frequency and transistor on-time are simultaneously changed to further optimize converter efficiency. This feature is not characteristic for other low-power control solutions. 
   A buck converter regulated by a DPFM/DPAM controller is shown in  FIG. 1 . This controller can operate as a conventional PFM system where the on-time of the transistor Q 1  is kept constant, while the switching frequency is changing, depending on the output load. At very light loads the switching frequency f sw =1/T sw  is low resulting in effectively small duty ratio value D=t on /T sw  and a slow transfer of the energy from the input source to the output. As the load increases the transistor switches more often providing more energy for the load. 
   In this specific implementation the control over the switching frequency is performed in a digital manner. The output voltage v out (t) is converted in its digital equivalent v out [n] using an analog-to-digital converter (A/D) and compared with the desired reference V ref [n]. The result of the comparison is a digital error signal e[n], whose value is positive if the output is smaller and negative when the regulated voltage exceeds the reference. The error signal is then processed by the compensator. The main task of this block is to create f sw [n] control signal which, through the DPFM/DPAM, regulates the switching frequency of the converter, in accordance with the following discrete-time control law:
 
 f   sw   [n]=f   sw   [n− 1 ]+a   sw   e[n]   (1)
 
where f sw [n] is the current value of the control signal, f sw [n−1] is the previous value of the control signal one switching cycle before and a sw  is a constant selected to provide stable converter operation. In this specific implementation the discrete-time control law was implemented with a compensator utilizing look-up tables. Compensator realization based on multiplier is also possible.
 
   It can be seen that a negative value of e[n] causes the switching frequency to decrease and when the error is positive the frequency increases. In addition, as described in following sections, this structure allows the transistor&#39;s on-time to be dynamically changed, through t on [n], setting the optimal t on  and f sw [n] for any given operating point. In PFM operation dynamic change of t on  time results in the dynamic change of the peak value of the inductor current, i.e. its amplitude, hence both amplitude and frequency can be changed. For that reason, the presented architecture is named digital pulse-frequency/pulse-amplitude modulator. 
   One embodiment of the present invention is a digital modulator  200  including a delay line  202  that sets the time on of an output signal of the digital modulator  200 ; and circuitry  204  to set the period of the output signal of the digital modulator  200 . The circuitry can include a ring oscillator  206  with slow delay cells  210  to use to set a positive edge of a pulse through the ring oscillator and fast delay cells  212  to set a negative edge of the pulse through the ring oscillator. The pulse width can narrow over time within the period. 
   The ring oscillator can allow for extended output periods for the digital modulator. Additionally, the speed of the pulse narrowing in the ring oscillator  206  can be adjustable to adjust the period. For example, the closer the slow delay is to the fast delay, the longer the output period. 
   The delay of at least one of the slow delay or fast delay cells can be adjustable to adjust the period. In one embodiment, the delay of the slow delay cells is adjustable to adjust the period. 
   The delay line  202  can be adjustable to adjust the time on of the output signals of the digital modulator. 
   The circuitry  204  can include another delay line  216  which can set the initial pulse width going into the ring oscillator  206 . The delay in this another delay line  216  can be adjustable. 
   The circuitry can include an end-of-race detector  214  that detects the end of the period and outputs a clk signal. The ring oscillator  206  can include SR latches connected to the fast and slow delay cells  212  and  210 . 
   The digital modulator can be a DPFM or a DPFM/DPAM. The signal-race based DPFM/DPAM architecture shown in  FIG. 2  allows creation of very long time intervals using fast digital logic and can be implemented with low power hardware. The DPFM operation can be based on the race of two signals around a ring oscillator where one signal starts first and the second signal, which propagates a little bit faster, starts a little bit later. Once the faster signal catches the first one the race is over. The period of the DPFM signal can be defined by the time difference between the start of the first signal and the end of the race. It should be noted that the duration of the race, i.e. switching period, is proportional to time spacing between the two signals and inversely proportional to the speed difference of the two signals, i.e. time delay of digital logic. 
   In one embodiment, four major functional blocks are used: two digitally programmable delay lines  216  and  202 , a digital block named End of Race detector  214  (EoR), and a ring oscillator  206  that can comprises SR latches  220  and two sets of delay cells  210  and  212 . In one embodiment, the cells  210  setting the SR latches are slower and programmable and inverting delay cells  212  have constant propagation time, which is smaller than that of the slow cells. The embodiment of  FIG. 2  has  3  digital inputs and start signal. The inputs f sw [n] and f pf [n] can change the switching frequency and the range of the range of frequencies over which this circuit operates, respectively. The third input, t on [n] can be used to control turn-on time of the transistor Q 1 . 
   An exemplary operation of an exemplary circuit is described below. The initial state of all the SR latches is zero. When a short-lasting start signal occurs two pulses are created a signal p(t) at the output of the programmable delay line, whose duration is inversely proportional to f sw [n] and signal c(t) that is used as the turn-on signal for the transistor Q 1 . The duration of this signal depends on the control value t on [n]. 
   The positive edge of p(t) sets the first SR latch of the ring to high. In turn, the output of the first SR latch will set the second SR latch, and the process of moving the rising edge through the ring oscillator will continue. This is illustrated in  FIG. 2  as a positive edge propagating on the upper track. When the negative edge of the p(t) occurs, the first latch will be reset to zero after being previously set by the positive edge. The transition of the first SR latch from high to low will reset the output of the second latch and, in the same manner the second latch will reset the third. This propagation of the negative edge will continue through the ring. It is shown as a negative edge going down the reset line. Hence, the positive and negative edge will start to chase each other around the SR latch ring. Because the delay of the set delay block is made to be slightly larger, after some time the negative edge will catch up the positive edge and all SR latches will be set to zero. This time instance is indicated with the end of the race detector (EoR) that creates a short clk pulse. The clk pulse is used to trigger both delay lines again and initiate the new racing circle. 
   The switching frequency of this DPFM can be controlled by changing the time distance between the rising edge and falling edges of p(t). The longer the distance between the edges is, the lower the switching frequency is. To provide additional adjustment of switching frequency f pf [n] signal is used. It sets the difference in speed between the cells and in that way regulates the range of switching frequencies. The smaller the difference between propagation times is the longer the race is. This system can be used for efficiency optimization, by selecting t on  time using delay line  202 , that for a given condition in the circuit always results in the minimum sum of the switching and conduction losses. 
   Slow digitally programmable delay cells can be implemented in multiple ways such as all-digital blocks or as digitally programmable current starved delay cells, which are more suitable for application-specific IC design. 
   Based on the diagrams shown in  FIGS. 1 and 2  an FPGA-based experimental controller was built around a buck converter. In addition, an application specific IC was designed and simulated. 
     FIG. 3  shows operation of the DPFM/DPAM in open loop, when the 5 most significant bits of the control signal f sw [n] are changing between a low and high value. It can be seen that the change of the control variable effectively changes the switching frequency.  FIG. 4  shows results of the closed loop operation of this system when the output load changes between 1 mA and 2 mA. It can be seen that the controller reacts on load change, by changing the control variable f sw [n], which in turns increases the switching frequency. Both of these experimental results verify functionality of the new invention. 
   To verify low power consumption and possibility of implementation on a small silicon area an application specific IC was designed in 0.18 CMOS technology, as a part of a larger controller IC, and simulated.  FIG. 5  and Table 1 show main characteristic of the DPFM/DPAM controller. It can be seen that it takes a very small silicon area of about 0.3 mm 2 , and consumes only 50 μA of current, when connected to a 1.8 V supply. 
   
     
       
             
           
             
             
             
           
         
             
               TABLE I 
             
           
           
             
                 
             
             
               Parameters of on-chip implemented DPFM/DPAM controller 
             
           
        
         
             
               Area 
               Frequency range 
               Current cons. 
             
             
                 
             
             
               0.03 mm 2   
               20 kHz to 250 kHz 
               50 μA 
             
             
                 
             
           
        
       
     
   
   The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.