Abstract:
A video imaging apparatus includes a source of a blanking signal that is indicative when a blanking interval occurs in a video signal. A delay circuit including a horizontal line counter is responsive to the blanking signal and to a signal at the horizontal rate for delaying the blanking signal by a multiple number of horizontal periods to generate a delayed signal. A dynamic focus voltage generator includes a switch responsive to the delayed signal for applying a dynamic focus voltage to a focus electrode, when the switch is at a first state, and for disabling the application of the dynamic focus voltage, when the switch is at a second state. An end time of the interval, during which the dynamic focus voltage is disabled, is determined in accordance with an output signal of the counter.

Description:
The invention relates to a beam landing distortion correction arrangement. 
     BACKGROUND 
     An image displayed on a cathode ray tube (CRT) may suffer from imperfections or distortions such as defocusing or nonlinearity that is incident to the scanning of the beam on the CRT. Such imperfections or distortions occur because the distance from the electron gun of the CRT to the faceplate varies markedly as the beam is deflected, for example, in the horizontal direction. Reducing the defocusing that occurs as the beam is deflected in the horizontal direction, for example, may be obtained by developing a dynamic focus voltage having a parabolic voltage component at the horizontal rate and applying the dynamic focus voltage to a focus electrode of the CRT for dynamically varying the focus voltage. It is known to derive the parabolic voltage component at the horizontal rate from an S-correction voltage developed in an S-shaping capacitor of a horizontal deflection output stage. 
     The CRT that employs dynamic focus may have internal wiring that places the dynamic focus voltage close to, for example, the blue electron gun. In normal operation, the proximity to the blue electron gun may not cause any problem. However, when a low current bias measurement is made in an automatic kine bias (AKB) circuit, during several video line times that immediately follow vertical retrace, referred to as the AKB measurement interval, stray coupling of the horizontal component of the dynamic focus voltage may introduce an error in the biasing of the cathode electrode of the blue electron gun. As a result, the bias of the blue electron gun may not track the bias of the green and red electron guns. This may lead to unacceptable background color temperature changes. 
     It may be desirable to remove the horizontal dynamic focus voltage component from the focus electrode, during the AKB measurement interval. Thereby, the undesirable coupling to the focus electrode is, advantageously, eliminated. It may be desirable to start disabling the dynamic focus voltage, prior to the AKB measurement interval, for preventing the occurrence of a transient condition in the dynamic focus voltage, during the AKB measurement interval. Therefore, the switch begins decoupling the dynamic focus voltage from the focus electrode, for example, close to the beginning time of the vertical blanking interval. 
     In a video display monitor, the time available for vertical retrace is a small portion of the vertical cycle. The addition of the AKB measurement interval following the end of the vertical blanking interval, disadvantageously, reduces the time available for vertical retrace. It may be desirable to allocate as much time as possible for the retrace interval for reducing the stress of the vertical deflection amplifier power transistor. Therefore, it may be desirable to reduce the tolerances of the end time of the interval, during which the dynamic focus voltage is disabled. This is so because, if the interval, during which the dynamic focus voltage is disabled, were to extend into the active video display interval, a portion of the visible scan line in the overlap region, disadvantageously, might appear not focused. On the other hand, if the interval, during which the dynamic focus voltage is disabled, were to end too early, the crosstalk of the dynamic focus voltage might cause an AKB error on one or more electron guns. 
     In accordance with an aspect of the invention, the end time of the interval, during which the dynamic focus voltage is disabled, is established accurately using a line timer or counter. The line timer or counter counts, for example, horizontal retrace pulses and produces a switch control signal for controlling the aforementioned dynamic focus voltage disabling switch. Advantageously, counting pulses provides more accurate measurement of the end of the interval, during which the dynamic focus voltage is disabled, than if such measurement were entirely dependent on tolerances of components such as resistors and capacitor. 
     A video imaging apparatus, embodying an inventive feature includes an amplifier responsive to a focus voltage correction signal for generating at an output of the amplifier a dynamic focus voltage component of a focus voltage that is coupled to the focus electrode. A switch is coupled in a signal path of the focus voltage correction signal for disabling the dynamic focus voltage component, during an automatic kine bias measurement interval of a deflection cycle. A source of a first signal indicative of an end time of a vertical blanking interval in the deflection cycle is provided. A synchronous time shifter is responsive to a clock signal and to the first signal for time shifting the first signal. The time-shifted first signal is coupled to the switch to control when the dynamic focus voltage is enabled. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B illustrate a horizontal deflection circuit output stage and a dynamic focus voltage generator, in accordance with an inventive feature. 
     FIG. 2 illustrates a delay circuit embodying an inventive feature. 
     FIGS. 3A-3B illustrate waveforms useful for explaining the operation of delay circuit  200  of FIG.  2 . 
     FIGS. 4A-4D illustrate additional waveforms useful for explaining the operation of delay circuit  200  of FIG. 2 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1A illustrates a horizontal deflection circuit output stage  101  of a television receiver having multi-scan frequency capability. Stage  101  is energized by a regulated power supply  100  that generates a supply voltage B+. A conventional driver stage  103  is responsive to an input signal  107   a  at the selected horizontal scanning frequency nf H . Driver stage  103  generates a drive control signal  103   a  to control the switching operation in a switching transistor  104  of output stage  101 . By way of example, a value of n=1 may represent the horizontal frequency of a television signal according to a given standard such as a broadcasting standard. The collector of transistor  104  is coupled to a terminal T 0 A of a primary winding T 0 W 1  of a flyback transformer T 0 . The collector of transistor  104  is also coupled to a non-switched retrace capacitor  105 . The collector of transistor  104  is additionally coupled to a horizontal deflection winding LY to form a retrace resonant circuit. The collector of transistor  104  is also coupled to a conventional damper diode  108 . Winding LY is coupled in series with a linearity inductor LIN and a non-switched trace or S 1  capacitor CS 1 . Capacitor CS 1  is coupled between a terminal  25  and a reference potential, or ground GND such that terminal  25  is interposed between inductor LIN and S-capacitor CS 1 . 
     Output stage  101  is capable of producing a deflection current iy. Deflection current iy has substantially the same predetermined amplitude for any selected horizontal scan frequency of signal  103   a  selected from a range of 2 f H  to 2.4 f H  and for a selected horizontal frequency of 1 f H . Controlling the amplitude of deflection current iy is accomplished by automatically increasing voltage B+ when the horizontal frequency increases, and vice versa, so as to maintain constant amplitude of deflection current iy. Voltage B+ is controlled by a conventional regulated power supply  100  operating in a closed-loop configuration via a feedback winding T 0 W 2  of transformer T 0 . The magnitude of voltage B+ is established, in accordance with a rectified, feedback flyback pulse signal FB having a magnitude that is indicative of the amplitude of current iy. A vertical rate parabola signal E-W is generated in a conventional way, not shown. Signal E-W is conventionally coupled to power supply  100  for producing a vertical rate parabola component of voltage B+ to provide for East-West distortion correction. 
     A switching circuit  60  is used for correcting a beam landing error such as linearity. Circuit  60  selectively couples none, only one or both of a trace or S-capacitor CS 2  and a trace or S-capacitor CS 3  in parallel with trace capacitor CS 1 . The selective coupling is determined as a function of the range of frequencies from which the horizontal scan frequency is selected. In switching circuit  60 , capacitor CS 2  is coupled between terminal  25  and a drain electrode of a field effect transistor (FET) switch Q 2 . A source electrode of transistor Q 2  is coupled to ground GND. A protection resistor R 2  that prevents excessive voltage across transistor Q 2  is coupled across transistor Q 2 . 
     A register  201  applies switch control signals  60   a  and  60   b . Control signal  60   a  is coupled via a buffer  98  to a gate electrode of transistor Q 2 . When control signal  60   a  is at a first selectable level, transistor Q 2  is turned off. On the other hand, when control signal  60   a  is at a second selectable level, transistor Q 2  is turned on. Buffer  98  provides the required level shifting of signal  60   a  to accomplish the above mentioned switching operation, in a conventional manner. 
     In switching circuit  60 , capacitor CS 3  is coupled between terminal  25  and a drain electrode of a FET switch Q 2 ′. FET switch Q 2 ′ is controlled by control signal  60   b  in a similar way that FET switch Q 2  is controlled by control signal  60   a . Thus, a buffer  98 ′ performs a similar function as buffer  98 . 
     A microprocessor  208  is responsive to a data signal  209   a  generated in a frequency-to-data signal converter  209 . Signal  209   a  has a numerical value that is indicative of the frequency of a synchronizing signal HORZ-SYNC or deflection current iy. Converter  209  includes, for example, a counter that counts the number of clock pulses, during a given period of signal HORZ-SYNC and generates word signal  209   a  in accordance with the number of clock pulses that occur in the given period. Microprocessor  208  generates a control data signal  208   a  that is coupled to an input of register  201 . The value of signal  208   a  is determined in accordance with the horizontal rate of signal HORZ-SYNC. Register  201  generates, in accordance with data signal  208   a , control signals  60   a  and  60   b  at levels determined by signal  208   a , in accordance with the frequency of signal HORZ-SYNC. Alternatively, the value of signal  208   a  may be determined by a signal  109   b  that is provided by a keyboard, not shown. 
     When the frequency of horizontal deflection current iy is 1 f H , transistors Q 2  and Q 2 ′ are turned on. The result is that both Scapacitors CS 2  and CS 3  are in-circuit S-capacitors that are coupled in parallel with non-switched S-capacitor CS 1  and establish a maximum S-capacitance value. When the frequency of horizontal deflection current iy is equal to or greater than 2 f H  and less than 2.14 f H , transistor Q 2  is turned off and transistor Q 2 ′ is turned on. The result is that S-capacitor CS 2  is decoupled from non-switched S-capacitor CS 1  and S-capacitor CS 3  is coupled to S-capacitor CS 1  to establish an intermediate S-capacitance value. When the frequency of horizontal deflection current iy is equal to or greater than 2.14 f H , transistors Q 2  and Q 2 ′ are turned off. The result is that S-capacitors CS 2  and CS 3  are decoupled from non-switched S-capacitor CS 1  and establish a minimum S-capacitance value. Deflection current iy in capacitor CS 1 , CS 2  or CS 3  produces an S-shaping parabolic voltage V 5 . 
     The total retrace capacitance formed by capacitor  105  does not change at the different scan frequencies. Therefore, the retrace interval has the same length at the different scan frequencies. The values of capacitors CS 1 , CS 2  and CS 3  are selected to produce parabolic voltage V 5  at different amplitudes at different scan frequencies. The different amplitudes of voltage V 5  are required because the retrace interval length is constant. 
     FIG. 1B illustrates a dynamic focus voltage generator  99 , embodying an inventive feature. Similar symbols and numerals in FIGS. 1A and 1B indicates similar items or functions. Voltage V 5  of 
     FIG. 1B has negative going retrace peaks. The peak to peak amplitude of parabolic voltage V 5  is about 60V at 16 KHz or 1 f H , 80V at 2 f H , and 125V at 2.4 f H . Parabola voltage V 5  is capacitively coupled via a capacitor C 4  to a resistor R 16 . 
     A controlled voltage divider or attenuator that includes resistor R 16  and a resistor CDS develops an attenuated parabolic voltage V 5 ′ at a terminal  120 . The attenuation of the voltage divider is determined by the state of conduction of cadmium sulfide photo resistor CDS that is a part of a photo-coupler PC 1 . Photo resistor CDS is responsive to light from a light emitting diode LED that is part of photo coupler PC 1 . The light from diode LED is responsive to a current from a darlington transistor Q 10 . Darlington transistor Q 10  and a darlington transistor Q 11  are coupled to each other and to a resistor R 19 , a resistor R 23  and a resistor R 24  to form a differential amplifier. The base of Darlington transistor Q 11  is coupled to a constant reference voltage of 3 volts derived from a 12V supply via resistive divider formed by a resistor R 11  and a resistor R 12 . 
     The DC component of voltage V 5 ′ is near 0 volts. The AC component is determined by resistors R 16  and CDS and a resistor R 17 . The value of resistor CDS is determined by the light energy from light emitting diode LED. The AC component of voltage VS′, a voltage V 5 ″, is coupled through a capacitor C 21  to the base of Darlington transistor Q 10  and to the cathode of a clamping diode D 6 . The negative peak of voltage V 5 ″ is held at −0.6 volts by clamping diode D 6 . The positive peak of voltage V 5 ″ will turn on Darlington transistor Q 10  when the level of +3 volts at the base of Darlington transistor Q 11  is exceeded. When Darlington transistor Q 10  turns on, current flows through diode LED and light flux is produced. This light flux acts on resistor CDS so as to reduce its resistive value, the amplitude of voltage V 5 ′ and the amplitude of voltage V 5 ″. The speed of response of the change of the resistive value of resistor CDS is very slow. This acts as a low pass filter in the negative feedback loop. As the positive peak value of V 5 ″ lowers to +3V, the on time of transistor Q 10  shortens and the average light energy from diode LED decreases until a balance is established. The positive peak amplitude of voltage V 5 ″ is then maintained at slightly greater than +3 volts. The peak-to-peak amplitude of voltages V 5 ″ and V 5 ′ is maintained at about 4 volts independent of input frequency or amplitude. 
     Drive voltage V 5 ′, developed at junction terminal  120  of resistors CDS and R 16 , is capacitively coupled through a capacitor C 23 , a resistor R 17  and a capacitor C 24  to a summing junction input terminal  121  of a focus amplifier  97 . The gain control action of resistor CDS regulates the voltage at terminal  121  to have equal peak-to-peak amplitude at each of the 1 f H , 2 f H  and 2.4 f H  rates. 
     Capacitor C 23  provides capacitive coupling for the horizontal parabola. A capacitor C 10  capacitively couples a vertical parabola V 8 , produced in a conventional manner, not shown, to terminal  121 . The direct current operating point of focus amplifier  97  is determined by a resistor R 5  and not by the parabolic signals, because the capacitive coupling eliminates a direct current component. Capacitor C 24  corrects a phase delay caused by a stray input capacitance, not shown, of amplifier  97  so that the horizontal focus correction is properly timed. 
     In amplifier  97 , a transistor Q 5  and a transistor Q 6  are coupled to each other to form a differential input stage. These transistors have very high collector current-to-base current ratio, referred to as beta, to increase the input impedance at terminal  121 . The base-emitter junction voltages of transistors Q 5  and Q 6  compensate each other and reduce direct current bias drift with temperature changes. Resistor R 11  and resistor R 12  form a voltage divider that is applied to a supply votage V 10  at +12V for biasing the base voltage of transistor Q 6  at about +3V. The value of an emitter resistor R 10  that is coupled to the emitters of transistors Q 5  and Q 6  is selected to conduct a maximum current of about 6 mA. This protects a high voltage transistor Q 20 . Transistor Q 20  is coupled to transistor Q 5  via a transistor Q 13  operating as a switch. Transistor Q 20  is coupled to transistor Q 5  via transistor Q 13  in a cascode configuration. Transistor Q 20  needs to be protected from being over-driven because transistor Q 20  can tolerate only up to 10 mA collector current. This is accomplished because amplifier  97  has high transconductance at a collector current of up to 6 mA and lower transconductance above 6 mA. The cascode configuration of transistors Q 20 , Q 13  and Q 5  isolates the Miller capacitance, not shown, across the collector-base junction of transistor Q 20 , thereby the bandwidth is increased. The cascode configuration also makes the amplifier gain independent of the low beta of high voltage transistor Q 20 . 
     A winding T 0 W 3  of transformer T 0  of FIG. 1A produces a stepped-up retrace voltage that is rectified in a diode D 12  and filtered in a capacitor C 13  to produce a supply voltage VSU for energizing dynamic focus voltage generator  99  of FIG.  1 B. An active pull up transistor Q 1  has a collector coupled to supply voltage VSU. A base pull-up resistor R 1  of transistor Q 1  is coupled to voltage VSU via a bootstrap or boosting arrangement that includes a diode D 7  and a capacitor C 26 . A diode D 5  is coupled in series with resistor R 1  and is coupled to the collector of transistor Q 20 . A diode D 4  is coupled between the emitter of transistor Q 1  at terminal  97   a  and the collector of transistor Q 20 . 
     During the negative peaks of the output waveform at terminal  97   a , diode D 7  clamps an end terminal of capacitor C 26  at the cathode of diode D 7  to the +1600V supply voltage VSU and transistor Q 20  pulls the other end terminal of capacitor C 16  to near ground potential. Transistor Q 1  is held off by the actions of diodes D 4  and D 5 . As the voltage at terminal  97   a  rises, the energy stored in capacitor C 26  is fed through resistor R 1  to the base of transistor Q 1 . The voltage across resistor R 1  is maintained high, and base current in transistor Q 1  also is maintained, even as the collector-to-emitter voltage across transistor Q 1  approaches zero. Therefore, transistor Q 1  emitter current is maintained. The output positive peak at terminal  97   a  can then be very near the +1600V supply voltage VSU without distortion. 
     A capacitance Cl represents the sum of the stray capacitance of focus electrode  17  and of the wiring. Active pull-up transistor Q 1  is capable of sourcing a current from terminal  97   a  to charge stray capacitance Cl. Pull-down transistor Q 20  is capable of sinking current via diode D 4  from capacitance Cl. Advantageously, the active pull up arrangement is used to obtain fast response time with lowered power dissipation. Amplifier  97  uses shunt feedback for the output at terminal  97   a  via a feedback resistor R 2 . Resistors R 17  and R 2  are selected to produce 1000V horizontal rate voltage at terminal  97   a . As a result, the voltage gain of amplifier  97  is several hundred. 
     Dynamic focus voltage components at the horizontal rate produced by voltage V 5  and at the vertical rate produced by voltage V 8  are capacitively coupled via a direct current blocking capacitor C 22  to a focus electrode  17  of a CRT  10  to develop a dynamic focus voltage FV. A direct current voltage component of voltage FV, developed by a voltage divider formed by a resistor R 28  and a resistor R 29 , is equal to 8 KV. 
     A periodic control signal V 13  is at a HIGH state, during vertical blanking and during, for example, four video line time that follow the vertical blanking, referred to as the AKB measurement interval, not shown. Signal V 13  is produced by a delay circuit  200 , embodying an inventive feature, that delays a conventional vertical blanking signal VERT-BLANK by a suitable number of video line times such as three or four. 
     FIGS. 3A-3B and  4 A- 4 D illustrate waveforms useful for explaining the operation of delay circuit  200  of FIG.  2 . The waveforms of FIGS. 4A-4D are shown with an expanded time base with respect to those of FIGS. 3A-3B. Similar symbols and numerals in FIGS. 1A,  1 B,  2 ,  3 A- 3 B and  4 A- 4 D indicate similar items or functions. 
     In the arrangement of FIG. 2, a conventional composite blanking signal COMP-BLANK of FIG. 3A is applied to a non-symmetrical integrator  203  that includes a resistor R 99  coupled to a capacitor C 99  of FIG.  2 . Resistor R 99  is coupled in parallel with a diode D 99  to provide the non-symmetry feature. Non-symmetrical integrator  203  is used to remove horizontal blanking pulses HB of FIG. 3A using a long time constant of resistor R 99  and capacitor C 99  while recovering A blanking lagging edge at time t 2  with a fast time constant of diode D 99  and capacitor C 99 . 
     To obtain signal COMP-BLANK, a conventional deflection processor  201  of the type TDA9151 generates a sandcastle signal SC coupled to a comparator  202  that removes a clamping pulse, not shown, from signal SC. The result is that signal COMP-BLANK of FIG. 3A is at a LOW state, during a vertical blanking interval VB and during a horizontal blanking pulses HB. On the other hand, when CRT blanking is not required, signal COMP-BLANK is at a HIGH state. 
     Integrator  203  of FIG. 2 filters out horizontal blanking pulses HB of FIG. 3A to produce a low-pass filtered signal VERT-BLANK of FIG.  3 B. Signal VERT-BLANK attains a LOW state at time t 1 , in accordance with a short delay produced by integrator  203  of FIG.  2 . Signal VERT-BLANK attains a HIGH state at time t 3  of FIG. 3B following a short delay time from an end time t 2  of FIG. 3A of vertical blanking interval VB. The delay time t 2 -t 3  is, advantageously, short because of the fast charging operation via diode  99  of FIG.  2  and is not significantly affected by tolerances of the components. 
     Signal VERT-BLANK is coupled to a data input  204   a  of a D-type flip-flop  204 . An inverted output  204   b  of flip-flop  204  is coupled to a data input  205   a  of a D-type flip-flop  204 . An output  205   b  of flip-flop  205  is coupled to a data input  206   a  of a D-type flip-flop  206 . An output  206   b  of flip-flop  206  is coupled to a data input  207   a  of a D-type flip-flop  207 . 
     An output  207   b  of flip-flop  207  and inverted output  204   b  of flip-flop  204  are coupled via a resistor  208  and a resistor  209 , respectively, to a junction terminal  210  to form a resistive logical OR function. A horizontal rate flyback pulse signal FLYB of FIG. 1A is coupled to a clock input terminal of each of flip-flops  204 - 207  of FIG.  2 . Flip-flops  204 - 207  form a four-stage shift register, clocked on the positive going leading edge of flyback pulse signal FLYB. Flip-flops  204 - 207  form a synchronous time shifter. 
     Flip-flop  204  produces a leading edge of signal V 13  at terminal  210  at time t 1  of FIG. 3C, close to a time t 0  of FIG. 3A, at the beginning time of vertical blanking interval VB. At time t 3  of FIG. 3B, that immediately follows the end time t 2  of vertical blanking interval VB of FIG. 3A, signal VERT-BLANK attains the HIGH state. The operation of flip-flops  204 - 207  of FIG. 2 is to maintain signal V 13  at the HIGH state, during an interval t 3 -t 4  of FIG.  3 C. Flip-flop  204  of FIG. 2 changes state when a first pulse FLYB(1) of signal FLYB of FIG. 4D occurs. Pulse FLYB(1) occurs following the trailing edge of signal VERT-BLANK at time t 3  of FIG.  4 B. When a fourth pulse FLYB(4) of signal FLYB of FIG. 4B occurs, following the state change in flip-flop  204  of FIG. 2, flip-flop  207  changes state and produces a trailing edge of signal V 13  at time t 4  of FIG.  4 C. Thus, because the delay time t 3 -t 4  is determined by signal FLYB that is accurately timed, the trailing edge of signal V 13  at time t 4  is, advantageously, tightly controlled. 
     Signal V 13  is coupled to the base of a switch transistor Q 15 . The collector of transistor Q 15  is coupled via a resistor R 27  to a junction terminal between the emitter of transistor Q 20  and the collector of transistor Q 13 . The collector of transistor Q 13  is coupled to the emitter of transistor Q 20  and the emitter of transistor Q 13  is coupled to the collector of transistor Q 5 . During vertical blanking and during the AKB measurement interval, transistor Q 13  is turned off by transistor Q 15  and blocks the flow of current from the collector of transistor Q 5  to the emitter of transistor Q 20 . 
     Emitter current for Q 20  is maintained during the AKB measurement interval via resistor R 27  and transistor Q 15 . Resistor R 27  is coupled between the emitter of transistor Q 20  and ground during the AKB measurement interval. During the AKB measurement interval, resistor R 27  has across it a constant voltage of about 11.3 volts. The value of resistor R 27  is chosen to cause a constant current in transistor Q 20  such that a voltage developed across resistor R 1  is equal to the difference between supply voltage VSU and the peak value of the dynamic focus voltage at terminal  97   a . This eliminates an undesired focus voltage transient and first video line misfocusing that could otherwise occur when the normal dynamic focus voltage starts after the AKB measurement interval. If resistor R 27  were not coupled to the emitter of transistor Q 20 , amplifier  97  output votage at terminal  97   a  would tend to reach the +1600V level of supply voltage VSU. However, the required peak of the waveform at terminal  97   a  is typically 1450V. If the amplifier output voltage at terminal  97   a  were to become 1600V, during the AKB measurement interval, a large transient would have occurred at the start of the first visible horizontal line, at the top of the picture. The transient, disadvantageously, would have caused the beginning portion of the first visible horizontal line, that occurs following the AKB measurement interval, to be defocused. 
     To prevent such large transient, the current in transistor Q 15 , which provides current path to transistor Q 20  through resistor R 27 , decreases the output voltage at terminal  97   a , during vertical blanking and during the AKB measurement interval. Transistor Q 20  acts as a current source and causes a voltage drop across resistor R 1 . During the AKB measurement interval, the dynamic focus voltage at terminal  97   a  is set to a level approximately equal to the peak of the summed horizontal and vertical parabolic components. Thereby, advantageously, focus voltage transient is significantly reduced, following the AKB measurement interval.