Abstract:
A method of making a substrate for a semiconductor package includes providing a laminated layer structure including a backing layer and a metal layer attached to the backing layer. A circuit layer is plated atop a first surface of the metal layer to form a circuit-on-metal structure. The circuit-on-metal structure is coupled to a dielectric layer by causing the dielectric layer to flow around the circuit layer to the first surface of the metal layer so that the circuit layer is embedded within the dielectric layer and the first surface of the metal layer is in direct contact with a first surface of the dielectric layer. The backing layer is then removed completely. The metal layer is then removed completely.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application entitled “CIRCUIT-ON-FOIL PROCESS FOR MANUFACTURING A LAMINATED SEMICONDUCTOR PACKAGE SUBSTRATE HAVING EMBEDDED CONDUCTIVE PATTERNS”, Ser. No. 11/166,005, filed Jun. 24, 2005, now U.S. Pat. No. 7,297,562, issued Nov. 20, 2007, which is a continuation-in-part of U.S. patent application entitled “INTEGRATED CIRCUIT SUBSTRATE HAVING LASER-EMBEDDED CONDUCTIVE PATTERNS AND METHOD THEREFOR”, Ser. No. 10/138,225 filed May 1, 2002, now U.S. Pat. No. 6,930,256, issued Aug. 16, 2005, and is also a continuation-in-part of U.S. patent application entitled “SEMICONDUCTOR PACKAGE SUBSTRATE HAVING A PRINTED CIRCUIT PATTERN ATOP AND WITHIN A DIELECTRIC AND A METHOD FOR MAKING A SUBSTRATE”, Ser. No. 11/045,402 filed Jan. 28, 2005, now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 10/138,225 filed May 1, 2002, now U.S. Pat. No. 6,930,256, issued Aug. 16, 2005, entitled “INTEGRATED CIRCUIT SUBSTRATE HAVING LASER-EMBEDDED CONDUCTIVE PATTERNS AND METHOD THEREFOR.” 
     All of the above-referenced U.S. patent applications have at least one common inventor and are assigned to the same assignee as this application. The specifications of the above-referenced patent applications are herein incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor packaging, and more specifically, to a laminated substrate having embedded conductive patterns for providing electrical inter-connection within an integrated circuit package. 
     BACKGROUND OF THE INVENTION 
     Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including “flip-chip”, ball grid array and leaded grid array among other mounting configurations. These configurations typically use a planar printed circuit etched on the substrate with bonding pads and the connections to the die are made by either wire bonding or direct solder connection to the die. 
     The resolution of the printed circuit is often the limiting factor controlling interconnect density. The above-incorporated patent applications disclose substrates and processes for making substrates having embedded conductors. 
     However, the embossing process described in the above-incorporated parent applications requires special tooling and has limitations on conductor size that are related to the material used for the dielectric. The laser-ablation processes described in the above-incorporated parent applications require a very high power laser in order to ablate the dielectric material and have consequent speed limitations that lower throughput. The ablation of the dielectric material also limits the possible conductor density because of the difficulties associated with cleanly ablating the dielectric material. 
     Therefore, it would be desirable to provide an embedded-conductor substrate manufacturing process having improved conductor density, manufacturing throughput and a low associated manufacturing cost. It would further be desirable to provide such a process that does not require a high power laser. 
     SUMMARY OF THE INVENTION 
     A semiconductor package substrate having embedded conductive patterns and a process for making the substrate generate channels that contain a circuit pattern beneath the surface of a substrate. The substrate is made by laminating a special metal layer into and onto a dielectric layer. The special metal layer includes at least two metal sub-layers: a substantially planar metal foil and a circuit pattern built-up on the film. After one or two circuit-on-film metal layers are bonded onto one or both sides of the dielectric layer, the metal layer is stripped down to the surface of the dielectric layer, leaving a circuit layer embedded within one or both sides of the substrate. 
     Vias can then be formed between multiple layers by laser ablating holes and filling them with metal. 
     The circuit-on-foil layer can be made by using a plating resist material that is then laser-ablated, yielding a negative circuit image. The regions between the ablated resist are filled by plating up metal and the resist is removed to yield a circuit-on-foil structure. Alternatively, the circuit-on-foil layer can be made by using a photo-sensitive plating resist material that is then laser-exposed and the exposed material is then removed and plated as described above. (The resist material can also be a negative photo-sensitive resist material in which case a positive circuit image is used.) 
     The foil that is used to make the circuit-on-foil layer can be a releasable foil having a copper backer layer such as those currently used for making laminated circuit board metal layers above the circuit board surface, or may be made by laminating or plating copper on a stainless steel plate to form a copper carrier layer. 
     The vias between layers can either be made by drilling from one side of the substrate through the embedded circuit to the embedded circuit on the opposite side, or may be made by drilling completely through the substrate. The holes are then filled with material. If one side of a double-sided assembly is left with metal film remaining above the surface of the dielectric, then the vias can be plated to that side via an electroplating process with the remaining metal film as an electrode. Subsequently, the metal film can be removed, leaving embedded circuits on each side of the substrate, with plated vias between the layers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1F  are pictorial diagrams depicting cross-sectional views of various stages in the preparation of a substrate in accordance with an embodiment of the present invention; 
         FIGS. 2A-2F  are pictorial diagrams depicting cross-sectional views of various further stages of preparation of a substrate in accordance with an embodiment of the present invention; 
         FIGS. 3A-3C  are pictorial diagrams depicting cross-sectional views of various further stages of preparation of a substrate in accordance with another embodiment of the present invention; 
         FIGS. 4A-4C  are pictorial diagrams depicting cross-sectional views of various stages of preparation of a substrate in accordance with another embodiment of the present invention; and 
         FIGS. 5A and 5B  are pictorial diagrams depicting semiconductor packages in accordance with embodiments of the present invention. 
     
    
    
     The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout. 
     DETAILED DESCRIPTION 
     The present invention concerns a process for making a semiconductor package substrate having a very thin structure. A foil is used to provide a carrier for a thin metal circuit layer that is built up on the foil and then embedded in a dielectric layer. The foil is removed subsequent to embedding the circuit layer leaving a dielectric layer with embedded circuits that reduce migration and manufacturing defect shorts between adjacent circuit features and reduce the overall height of the substrate. The foil can be a thin metal layer plated or gilded on to a stainless steel surface, as in the process well known for forming films for lamination onto printed wiring boards prior to etch formation of a circuit pattern. An alternative foil that can be used is a laminated foil/metal backing layer structure such as MICROTHIN foil produced by Oak-Mitsui division of Mitsui Kinzoku Group. MICROTHIN foil is first laminated to a supporting dielectric structure with the thin foil layer to which a circuit is to be added on the outside and the backing layer (carrier foil) laminated to the supporting dielectric structure. The circuit pattern is plated up on the laminate structure, the circuit pattern side of the laminate is embedded in a dielectric layer and then the metal backing layer and supporting dielectric are removed. 
     A novel process for forming the circuit pattern is also presented and can be used in the process mentioned above. The circuit pattern formation process uses a laser to ablate a plating resist material rather than ablating material of the dielectric layer or displacing the dielectric material by embossing, as is performed in the above-incorporated parent U.S. patent applications. The process of resist ablation can be extended to etching resist materials and can be used for formation of larger-thickness circuits such as printed wiring boards in addition to the formation of very thin semiconductor package substrates. 
     Referring now to the figures and in particular to  FIGS. 1A-1F , cross-sectional views illustrate a substrate manufacturing process in accordance with an embodiment of the present invention. A circuit-on-foil structure is used to form a very thin semiconductor package substrate in a novel process that permits embedding circuits beneath the top and/or bottom surface of a substrate. 
       FIG. 1A  shows a metal film layer  10 , which is generally copper, but may be another plating-compatible material, bonded temporarily to a stainless steel tool plate  12 . It should be understood that other materials may be used for plate  12 , provided that the strength of the attachment between metal film layer  10  and plate  12  is sufficiently strong to retain metal film layer  10  on plate  12  during processing, but permitting release of metal film layer once bonding of the film layer to a dielectric layer has been accomplished as illustrated below. 
       FIG. 1B  shows metal film layer  10  after a plating resist material  14  has been applied over the outer surface of metal film layer  10  and  FIG. 1C  illustrates the patterned plating resist material  14 A after ablation by an excimer laser that removes the plating resist material in regions  15  where a circuit pattern is to be formed atop metal film layer  10 . Alternatively, a photographic process can be used to form resist pattern  14 A as is used in traditional circuit processing where a photosensitive resist material  14  is applied and exposed using a mask and uniform illumination source or a scanning laser to expose resist material  14 . Then the photosensitive resist material is processed to remove the material not forming part of pattern  14 A. 
     After patterning, as shown in  FIG. 1D , metal is plated in circuit pattern regions  15  defined by resist pattern  14 A to form circuit pattern  16  and then the remaining resist pattern  14 A material is removed by machining or a chemical process, leaving a circuit-on-foil structure mounted atop tool plate  12  as shown in  FIG. 1E . 
     The semiconductor substrate of the present invention is then formed by bonding the circuit-on-foil structure to a dielectric layer  18  so that the circuit pattern  16  is embedded within dielectric layer  18  as shown in  FIG. 1F . The bonding may be performed by pressing the circuit-on-foil structure to a flowable dielectric such as a prepreg material and then UV-curing or otherwise fixing the material forming dielectric layer  18 , or alternatively by molding a curable, time-curing or molten dielectric material atop the circuit-on-foil structure. 
     After the circuit-on-foil structure has been bonded to dielectric layer  18 , further processing steps are applied as illustrated in  FIGS. 2A-2F . First, as illustrated in  FIG. 2A , the fabricated substrate is detached from tool plate  12 , and then metal foil  10  is removed by machining or etching, to yield a single-sided substrate as shown in  FIG. 2B . 
     The processing steps illustrated in  FIGS. 1B-1F  can be repeated to form a second circuit-on-film structure having a circuit pattern  16 A for forming the opposite side of a semiconductor package substrate, and then bonding the second circuit-on-film structure to the side of dielectric layer  18  opposing circuit pattern  16  to form a double-sided substrate as illustrated in FIG.  2 C, in which a metal film layer  10 A is left in place temporarily. 
     Via holes  17  may be laser-drilled or machined in dielectric layer  18  through circuit pattern  16  to the bottom side of circuit pattern  16 A as shown in  FIG. 2D  and then filled with metal paste or plated to form vias  18  that provide electrical connections between circuit pattern  16  and circuit pattern  16 A as shown in  FIG. 2E . Metal layer  10 A is left in place if a plating process is used and then removed as shown in  FIG. 2F , so that a common electrode for plating vias  18  is easily available. If a paste process is used, metal layer can be removed prior to paste processing or laser-drilling of via holes  17 . 
       FIG. 2F  shows the completed semiconductor package substrate as formed by the above-described process. The feature sizes accomplished in the illustrated substrate are less than 10 microns wide and the thickness of the circuit patterns may be less than five microns, yielding a very thin substrate. 
     An alternative via-forming process is illustrated in  FIGS. 3A-3C . As illustrated in  FIG. 3A , metal layer  10 A can be removed prior to the formation of via holes  17 A as illustrated in  FIG. 3B , and plating or paste-filling is then applied to form vias  18 A as shown in  FIG. 3C , with the only difference in resulting structure being the presence of via  18 A material extending through circuit pattern  16 A in contrast to the termination of vias  18  within dielectric layer  18  at or in the bottom side of circuit pattern  16 A as shown in  FIG. 2F . 
     Referring now to  FIGS. 4A-4C , various steps of an alternative process for making a semiconductor package substrate are depicted in accordance with an embodiment of the present invention. A laminated film such as the above-mentioned MICROTHIN laminate is provided as shown in  FIG. 4A , which includes a very thin (3 micron) copper film  40  attached to a copper backing layer  42  by an organic releasing agent  41 . The MICROTHIN laminate is temporarily laminated to a dielectric layer  43  in order to provide a backer for handling and processing. 
     It should be understood that in contrast to the method of the present invention, the typical use of the MICROTHIN product is to transfer a thin-film metal layer (film  40 ) to a dielectric for subsequent pattern formation by etching or for use in a semi-additive process where a circuit pattern is plated atop the thin metal film. In the present invention, the thin-film  40  is patterned with plated metal to form the circuit-on-foil structure first and then the circuit-on-foil structure is used to apply the circuit pattern within the dielectric. The temporary backing dielectric layer  43  is bonded to the copper backing layer  42  to provide even more support and backing rather than laminating film  40  onto a dielectric layer as in the pattern-formation technique mentioned above. 
       FIG. 4B  shows the substrate after bonding of a dielectric layer  48  to the circuit-on-foil layer that includes circuit pattern  46  and copper film  40  (still attached to copper backing layer  42  by releasing agent  41 , which is still laminated to dielectric layer  43 ). The formation of circuit pattern  46  and bonding of dielectric layer  48  are performed as described above with respect to  FIGS. 1B-1F , with the only difference being the substitution of the laminated film structure provided in  FIG. 4A  for the metal layer  10 /tool plate  12  combination shown in  FIG. 1A . 
     After the circuit-on-foil structure is bonded to dielectric layer  48 , dielectric layer  43 , copper backing layer  42  and releasing agent  41  are peeled off of the substrate, leaving the structure depicted in  FIG. 4C , which is essentially the same structure depicted in  FIG. 2A , and can be processed by the following steps described above for  FIGS. 2B-2C  to form a dual-layer structure and the steps described for  FIGS. 2D-2F  or  3 A- 3 C to form vias. 
     Referring now to  FIG. 5A , a semiconductor package in accordance with an embodiment of the present invention is depicted. A semiconductor die  54  is attached to substrate  50  using a bonding agent such as epoxy. While die  54  is depicted as mounted above substrate  50 , a die mounting recess may also be laser-ablated or otherwise provided in substrate  50 , reducing the package height. Electrical interconnects from die  54  are wire bonded with wires  56  to plated areas  52  atop the circuit pattern formed in substrate  50 , electrically connecting die  54  to circuit patterns  16  and vias  18 . External terminals  58 , depicted as solder balls, are attached to circuit pattern  16 A, which may be plated or unplated, providing a complete semiconductor package that may be encapsulated. 
     Referring now to  FIG. 5B , a semiconductor package in accordance with an alternative embodiment of the invention is depicted. Die  54 A is a “flip-chip” die that is directly bonded to a substrate  50 A via solder balls  56 A. External solder ball terminals  58  are provided as in the embodiment of  FIG. 5A . Substrate  50 A is fabricated in the same manner as substrate  50 , but may have a differing configuration to support the flip-chip die  54 A interconnect. 
     The above description of embodiments of the invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure and fall within the scope of the present invention.