Abstract:
A random access memory cell ( 10 ) comprises a first conductor line ( 12 ) and a second conductor line ( 14 ). A native device ( 16 ) is arranged to store charge. A high voltage threshold transistor ( 30 ) couples the native device to the first and second conductors.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to memory cells and more particularly relates to memory cells of reduced leakage.  
           [0002]    Dynamic random access memory (DRAM) implementation in deep sub-micron technology, such as &lt;0.13 micron technology, is becoming very challenging due to excessive leakage. DRAM cells incorporate a charge storage device. The voltage created by the charge represents a digital one or a digital zero depending on the value of the voltage. However, the charge leaks and must be periodically refreshed to a proper value. As the size of the cells decreases, the charge leakage becomes excessive and requires more frequent refreshing. The increased frequency of the refreshing cycle decreases memory performance. This invention addresses the problem and provides a solution.  
           [0003]    Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.  
         BRIEF SUMMARY OF THE INVENTION  
         [0004]    A random access memory cell made in accordance with one embodiment of the invention comprises a first conductor line, a second conductor line, a native device arranged to store charge and a transistor coupling the native device to the first conductor and the second conductor.  
           [0005]    By using this memory cell, the amount of charge leakage can be reduced to a degree previously unattainable. These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    [0006]FIG. 1 is a schematic diagram of a first form of memory cell made in accordance with the invention, including a first form of native device arranged to store charge.  
         [0007]    [0007]FIG. 2 is a schematic diagram of a second form of memory cell made in accordance with the invention, including a second form of native device arranged to store charge.  
         [0008]    [0008]FIG. 3 is a schematic diagram of an exemplary form of the native device shown in FIG. 1.  
         [0009]    [0009]FIG. 4 is a schematic diagram of an exemplary form of the native device shown in FIG. 2. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0010]    Referring to FIG. 1, one form of DRAM cell  10  made in accordance with the invention comprises a word line  12  and a bit line  14  arranged as shown. A native device  16  is used to store charge. In the FIG. 1 form of cell  10 , native device  16  comprises an NMOS transistor of the type shown in FIG. 3.  
         [0011]    Referring to FIG. 3, transistor  16  comprises a substrate  18  doped with p type material defining a surface  19 . Sections  20 ,  24  and  26  of the substrate are doped with different types of material. For example, section  20  is doped with p type material and sections  24  and  26  are doped with n type material. Each of sections  20 ,  24  and  26  is adjacent surface  19 . Section  20  comprises a substrate contact that is connected to a source of reference potential  22 , such as ground potential. A gate  28  is formed adjacent sections  24  and  26  as shown in a well known manner. Native devices have low threshold voltages by design, typically about 300 millivolts less than standard devices. As a result, charges stored on native devices increase due to the additional potential available for a given input voltage.  
         [0012]    Referring to FIG. 1, cell  10  also comprises a gating transistor  30  including a source  32 , a gate  34  and a drain  36  connected as shown. In particular, drain  36  is connected to gate  28  of native device  16 , gate  34  is connected to line  12  and source  32  is connected to line  14 .  
         [0013]    In the form of cell shown in FIG. 1, transistor  30  comprises a high voltage threshold (VT) NMOS type transistor. A high voltage threshold transistor allows for increased drive current during periods of high cell activity, and reduced off-state leakage current when the cell is idle for a period of time. A high voltage threshold transistor leaks less than a low voltage threshold transistor. Transistor  36  typically responds to a gate threshold voltage in the range of 350 to 450 millivolts and has a drive current of about 150 microamps/micron.  
         [0014]    By using transistor  16 , a sense amplifier (not shown) used with cell  10  may be designed to reduce the electric field across the drain/source pass gate of cell  10 . By reducing the electric field, subthreshold leakage is reduced. For example, a 100 millivolts of reduction in electric field decreases subthreshold leakage substantially.  
         [0015]    Referring to FIG. 2, a second form of DRAM cell  10  made in accordance with the invention comprises a word line  12  and a bit line  14  arranged as shown. A native device  16 A is used to store charge. In the FIG. 2 form of cell  10 , native device  16 A comprises a PMOS transistor of the type shown in FIG. 4.  
         [0016]    Referring to FIG. 4, device  16 A comprises a substrate  18 A doped with n type material defining a surface  19 A. Sections  20 A,  24 A and  26 A of the substrate are doped with different types of material. For example, section  20 A is doped with n type material and sections  24 A and  26 A are doped with p type material. Each of sections  20 A,  24 A and  26 A is adjacent surface  19 A. Section  20 A comprises a substrate contact that is connected to a source of reference potential  22 A, such as ground potential. A gate  28 A is formed adjacent sections  24 A and  26 A as shown in a well-known manner.  
         [0017]    Referring to FIG. 2, cell  10  also comprises a gating transistor  30 A including a source  32 A, a gate  34 A and a drain  36 A connected as shown. In particular, drain  36 A is connected to gate  28 A of native device  16 A, gate  34 A is connected to line  12  and source  32 A is connected to line  14 .  
         [0018]    In the form of cell shown in FIG. 2, transistor  30 A comprises a high voltage threshold (VT) PMOS type transistor. Transistor  36 A typically responds to a gate threshold voltage in the range of 350 to 450 millivolts and has a drive current of about 110-120 microamps/micron.  
         [0019]    By using transistor  16 A, a sense amplifier (not shown) used with cell  10  may be designed to reduce the electric field across the drain/source pass gate of cell  10 . By reducing the electric field, subthreshold leakage is reduced. For example, a 100 millivolts of reduction in electric field decreases subthreshold leakage substantially.  
         [0020]    While the invention has been described with reference to one or more preferred embodiments, those skilled in the art will understand that changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular step, structure, or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.