Abstract:
A memory system incorporates shared redundant memories and has a shared redundant memory architecture. The memory system includes a modified memory to be used as a shared redundant memory between memory systems. These memory systems may have several smaller memories forming a single logical memory or various memories in close proximity on an integrated circuit system. The shared redundancy is achieved by adding a comparator to the redundant element for comparing between the faulty address and the system address and performing a memory operation based on the comparator output. As the redundant memory operations are performed in parallel to the memory structures, setup and hold times are reduced. Shared redundancy also results in reduced integrated circuit area.

Description:
RELATED APPLICATION  
       [0001]     The present invention claims priority of India Patent Application No. 2023/Del/2005 filed Jul. 29, 2005, which is incorporated herein in its entirety by this reference.  
       FIELD OF THE INVENTION  
       [0002]     The present invention discloses a shared redundant memory architecture and memory system incorporating the same. Further, it also describes two different memory systems incorporating the redundant memory.  
       BACKGROUND OF THE INVENTION  
       [0003]     The increasing complexity of systems and semiconductor process is resulting in more defects in the System On Chip (SoC) design process. The yield of these SoCs is directly linked to the memories on the SoC as around 60-70% of the silicon area on the chip is covered by the memories. Different types of memories are used for various operations on chips, like storage, temporary calculations, synchronization, buffering etc. Due to such a large presence of memories on chip, the chip yield is directly linked to the memory yield and hence to the memory defect level. In the newer technologies the degree of defects in the memories have increased to a great extent due to shrinking dimensions. In this context neither controlled process nor design can help in improving the SoC&#39;s yield as shrinking gate lengths have resulted in newer processes where the defect levels have gone beyond the control of the process and design. The only method, which can still help in enhancing the yield of the SoC, is to repair the faulty cases by providing redundant parts.  
         [0004]     Many different types of redundant elements have been introduced in the previous inventions to deal with this problem. There are several proposed schemes for repairing faulty memories as well. These include providing redundancy for row, column, word, bit, soft memory or another piece of memory, which can be classified into two types: 
        1. The type-1 redundancy includes all the techniques which implement the redundancy inside the memory itself. Spare row, spare bit slice, or spare column redundancy can be put into this category.     2. The type-2 redundancy includes of techniques which provide redundancy as an external element to the memory. Spare memory, spare soft memory etc. can be put in this category.        
 
         [0007]     The problem with using the type-1 redundancy in memory system is that it results in modified timing characteristics (setup/hold/access/cycle). This type of redundancy also results in increased development cycle time for the memory compilers. For instance, it is observed that the column redundancy leads to increased repair time for the memory after power on. In the row redundancy, the setup and hold time of the memory are increased which puts a limit on the number of redundant rows allowed. The problem with the type-2 redundancy is seen in terms of the memory performance as the soft routed memories can be routed all round the SoC which results in unnecessary routing congestion. Also soft memories cannot be used for multi port memories as considerably more effort is required in designing multiport soft memories. The timing characteristics (setup/hold/access) of the memory are modified by the soft memories as well. The area is another concern as soft memories are made using standard cells in a standard cell library which take more area than ASIC memories. This puts a restriction on the number of redundant elements allowed on an ASIC. Even in a case where a hard memory of same type is used instead of the soft memory, there is a significant area overhead as besides the storage elements other logic blocks in a memory like address decoders, I/O sections etc. are also duplicated.  
         [0008]     At system level, memory redundancy results in another problem when there are several small memories on a chip. These small memories are either used to form a bigger memory or are used individually but in vicinity of each other on a chip. In such situations, the present techniques provide a redundant memory for each individual memory. But not all the memories fail on a wafer and it is observed that most of the time the redundant memories are wasted. Therefore putting redundancy for each memory is highly inefficient as it increases the overhead in terms of the memory area and fuse area and results in timing overhead as well. The redundant memories also impact the setup and hold times of the memories.  
         [0009]     Hence there is need for a memory system with redundant memories that reduces the area overhead in terms of silicon and fuse area. There is also need for memory system with redundant memories that do not affect the timing characteristics of the memory. Collectively there is also need to provide a shared redundancy from the total bit size point of view for all memories present on a chip. The present invention provides a memory system incorporating shared redundant elements for the memories on any SoC or Application Specific Integrated Circuit (ASIC). The present invention also provides a shared redundant memory architecture. In this context when there are several small memories on a SoC, two different embodiments of a modified redundant memory are provided for use as a shared redundant element for different memory systems. The number and type of shared redundant memories on a SoC depends on the interconnect architecture and number of the small memories.  
       SUMMARY OF THE INVENTION  
       [0010]     To obviate the drawbacks of the prior art the object of the instant invention is to provide memory system incorporating shared redundant memories and shared redundant memory architecture. A further object of the instant invention is to provide memory system to reduce area overhead for the fuse and redundant memory. Another object of the instant invention is to provide a memory system to eliminate the redundancy effects on the memory timing characteristics.  
         [0011]     To achieve the aforesaid objects the instant invention provides a memory system including at least one memory structure, each said memory structure receiving at least one input address and corresponding set of inputs for performing an operation on said memory structure, a fuse box for storing and transmitting faulty address information of said memory structures, wherein there is at least one shared redundant memory, each of said shared redundant memory receiving said input addresses and said corresponding set of inputs for associated memories in a said memory structure and the faulty address information from the fuse box for repairing faulty locations in said associated memories; and at least one output selector, each said output selector for selecting between data output of said shared redundant memory and each data output of said associated memories responsive to a first control signal from said shared redundant memory.  
         [0012]     Further, the instant invention also provides a shared redundant memory architecture including a comparator receiving a single input address and faulty address information for generating a first control signal for a memory system, a memory core receiving said first control signal for storing and retrieving data input for faulty address locations in repairable memories, an Input/Output (I/O) block for bidirectional data transmission in said memory core, and a first input selector receiving a data input and said enable input of said memory system for transmitting said data input to said I/O Block during write operation. 
     
    
     BRIEF DESCRIPTIONS OF THE DRAWINGS  
       [0013]     The present invention will now be described with the help of accompanying drawings, in which:  
         [0014]      FIG. 1  illustrates the block diagram for the type- 1  redundant memory architecture in accordance with the present invention;  
         [0015]      FIG. 2  illustrates type-1 memory system incorporating a shared redundant memory in accordance with the present invention;  
         [0016]      FIG. 3  illustrates the block diagram for the type-2 redundant memory in accordance with the present invention; and  
         [0017]      FIG. 4  illustrates type-2 memory system incorporating a shared redundant memory in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     The current invention provides new high-speed memory system with modified redundant memories which are shared between various memories on a chip. Additionally, in the present invention, two different embodiments of shared redundant memory are provided for use depending on the memory systems on the chip. These memory systems can be categorized as follows: 
        1. Type-1 memory systems: In type-1 memory system, there are several small memories combined together to form a single large memory.     2. Type-2 memory systems: In type-2 memory system, there are several unrelated memories for different purposes located in close proximity of each other.        
 
         [0021]     In both type-1 and type-2 systems, redundant memories are added to the system for purpose of repairing. The repair methodology/architecture is different from the existing techniques as the redundant memory is shared between various memories present on a SoC. However in order to henceforth differentiate normal memories from redundant memories, each of the memories (other than the redundant memories) in the memory systems will be referred to as repairable memories. Also, the redundant memory architecture is a little different for two different memory systems on the SoCs and henceforth these will be referred to as type-1 and type-2 redundant memories. Further, in both memory systems, it is assumed that the built-in self test (BIST) apparatus has tested all memory locations and programmed the Fault Address (FA) information in the fuse box.  
         [0022]     The redundant memory architecture of the instant invention is similar to the conventional memory architecture except for the read or write operation mechanism.  FIG. 1  illustrates the block diagram for the type-1 redundant memory. The redundant memory comprises a memory core  12 , a set of multiplexers  14 , Input/Output (I/O) section  13  and a comparator  11 . The comparator  11  receives the FA from the fuse box and the System Address (SA) from the external pins. The output of the comparator  11  is coupled to the memory core  12  and the data output of the memory core  12  is coupled to the I/O section  13 . A set of multiplexers  14  is added to the I/O section  13  of the redundant memory to select the repairable memory input as input to the redundant memory during a write operation. In another embodiment, a multiplexer may be added to the redundant memory architecture to select between the outputs of the redundant memory and the repairable memory for a read operation.  
         [0023]      FIG. 2  illustrates a type-1 memory system with a shared redundant memory  24  wherein N repairable memories  23  of size 2048×64 are combined to form a larger memory of size (N ×2048)×64 for an N=4 embodiment. The type-1 system in this embodiment comprises 4 repairable memories  23 , a 4-to-1 memory selection multiplexer  25 , 2-to-1 output selection multiplexer  26 , a decoder  22 , a fuse box  21  and a type-1 redundant memory  24 . The system address CSN (in this case the same signals CSN 1 - 4 , in this case SA) is connected to the address port of all repairable memories  23  and output of each repairable memory  23  is connected to the 4-to-1 memory selection multiplexer  25 . The log 2 N memory selection control inputs A (in this case  2 , A&lt;0:1&gt;) and other inputs are connected to the decoder  22 . The control output of the decoder  22  is connected at the control input of the 4-to-1 memory selection multiplexer  25 , the decoded SA is coupled to the repairable and redundant memories. The address FA from the fuse box  21  is also connected to the redundant memory  24 . Output of the redundant memory  24  and output of the 4-to-1 memory selection multiplexer  25  are connected to the 2-to-1 output selection multiplexer  26  and a control input HIT signal is coupled to the control node of the 2-to-1 output selection multiplexer  26 . Output Q of the 2-to-1 output selection multiplexer  26  is used as the output of a memory location in type-1 memory system.  
         [0024]     Hence, in the new architecture, a type-1 redundant memory  24  is added to the type-1 memory system as a shared redundancy instead of a redundant memory for each repairable memory  23 . As this modification reduces the number of required redundant elements, the overall area of a SoC is reduced. In the modified system, the read operation on a memory requires addition of an output selection multiplexer  26  and a shared redundant memory  24 . The memory address and memory selection control inputs A for a faulty location are first programmed in the fuse box and output from the fuse box is decoded by the decoder to generate a FA. FA along with SA are simultaneously fed to the redundant memory  24 . The comparator in the redundant memory  24  then compares the two addresses, and if they match, a HIT signal is generated. A high HIT signal indicates that the controls on SoC have tried to perform an operation on a faulty memory location in one of the repairable memories  23 . This HIT signal is used as a control input for multiplexers  14  for write operations on the redundant memory  24 . An write enable signal from external pins is passed to the redundant memory along with the date for write operation by multiplexers  14  in the redundant memory on receiving a high HIT control signal. For read operation on modified memory system, SA is simultaneously used as an input for all repairable memories  23  and the data output each of the repairable memories is passed to the memory selection multiplexer  25 . The memory selection multiplexer  25  is used to select the correct data output using the control input A from the decoder  22 . The data output from the redundant memory  24  and the memory selection multiplexer  25  are fed to the 2-to-1 output selection multiplexer  26 . Based on the HIT signal, one of the two inputs is selected as the output of the memory system. Hence, if there is a problem with a location in one of the repairable memories, a high HIT signal is generated and the operation is performed on a memory location in the redundant memory. The multiplexers  14 ,  25  and  26  at the output can be implemented as full custom or semi custom depending upon the need.  
         [0025]      FIG. 3  illustrates the block diagram of the type-2 redundant memory. The redundant memory architecture comprises a comparator  32 , a first set of multiplexers  31 , an I/O Section with a second set of multiplexers  34  and a memory core  33 . The first set of multiplexers  31  receive the data inputs DIN, memory selection inputs AIN, the input addresses CSN, write enable signals WENs and the system clocks for each of the repairable memories in type-2 system. The multiplexers  31  also receive the information regarding the faulty memory FM and the fault address information from the fuse box. The SA and DIN are decoded by the first set of multiplexers  31 . SA is coupled to the comparator  32  and DIN is coupled to the I/O section  34 . The comparator  32  generates a HIT signal which is connected to the memory core  33  for selecting a location within the shared memory for a read/write operation. The I/O section  34  is coupled to the memory core  33  and comprises a second set of multiplexers for write operation on the redundant memory.  
         [0026]      FIG. 4  illustrates the modified type-2 memory system embodiment comprising two repairable memories  42  in close proximity and a type-2 redundant memory  43  shared by the two repairable memories  42 . Besides these, the system also comprises a dedicated 2-to-1 output selection multiplexer  44  associated with each repairable memory  42 . The redundant memory receives the inputs of the repairable memories  42 (in this case, A 1 - 2 , CSN 1 - 2 , WEN 1 - 2 , D 1 - 2 ) and the system clocks. The comparator is connected to each of the 2-to-1 output selection multiplexer  44  associated with two repairable memories  42 . Besides the HIT signal, the 2-to-1 multiplexers  44  also receives the data output of the redundant memory  43  and the data output of associated repairable memory  42 .  
         [0027]     The working methodology in the system sharing type-2 redundant memories  43  is a bit different from the system sharing type-1 redundant memories  24 . In this case, a input addresses and other inputs of all repairable memories  42  are fed to the shared redundant memory  43  simultaneously. At the same time, the inputs for each repairable memory  42  are fed to the respective repairable memory  42 . In the redundant memory  42 , the inputs are multiplexed with the decoded outputs generated through the fuse box  41 . The fuse box  41  is programmed based on the FA in the repairable memories  42  and the select inputs are decoded. These select inputs decide which repairable memory inputs are used as the input to the redundant memory  43 . The comparison of SA with FA, generation of the HIT signals and write operation on the type-2 redundant memory location happen in similar fashion as in the type-1 redundant memory. However, during a read operation, the data output from the redundant memory Qred is generated and fed to two 2-to-1 output selection multiplexers  44 . If a faulty address is accessed in a repairable memory, for instance  42   a , the input data of the repairable memory  42   a  is fed to the shared redundant memory  43  and the high HIT signal is generated for the associated output selection multiplexer  44   a  (in this case, HIT 1 ). The connections (in this case, HIT 2 ) to the associated output multiplexer is kept low as only one repairable memory  44   a  has access to the redundant memory  43  at a given time. If more than one faulty repairable memories  42  are accessed, the inputs for other faulty repairable memories are subsequently fed to the redundant memory  43  and HIT signal is generated for each accessed faulty location. These HIT signals (HIT 1  or HIT 2 ) are used as the control signal for selecting between the data output Qred of the redundant memory  43  and the associated repairable memories  42  Q using output selection multiplexers  44 . As the redundant memory  43  is very small, the operating speed is very fast and hence, HIT signals can be generated for all accessed faulty locations before the read operation is completed on the repairable memories  42 . Hence, during a read operation, if the repairable memory  44   a  is faulty, a high HIT signal is generated and the HIT signal is transmitted as the control input to the multiplexer  44   a . As the timing penalty on the data output Q has to be reduced, the output selection multiplexers  44  are coupled to the memory  42 . This solution may result in additional routing congestion as the Q buses may have to be routed to the original memory. This puts a limitation on the usage of this method. However, the routing congestion can be decreased by careful placement and floorplanning of the shared redundant memory  43 .  
         [0028]     To keep the system simple and to save area, all memories are non-self timed memories. The memory cells as well as the core, in the redundant memory are exactly matched with the repairable memory. To further reduce the area requirements, the I/O section in the redundant memory is made non-self timed and a simple inverter is used instead of a sense amplifier for sensing the correct data on the bitlines. Further, as there are only few rows on the bitlines the access time can always be kept faster than the main repairable memory module. Also as the address comparison does not come into the critical path of the main memory, there is no impact on the address setup time and the hold time of the memory.  
         [0029]     Also, while the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. A person skilled in the art will understand two embodiments described herein are for the purpose of sharing the redundant memories in type-1 and type-2 memory systems. The person skilled in the art may also understand that with minor modifications to instant invention, the sharing methodology may be used with different memory systems. For example, in one of the embodiments, a group of repairable memories may share more than one redundant memories by modifying the redundant memory. In another embodiment, a dedicated redundant memory may be used with a single physical large memory resulting in reduced hold and setup time for memory system with redundant elements.  
         [0030]     While there have been described above the principles of the present invention in conjunction with specific components, circuitry and bias techniques, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.