Abstract:
An apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an exemplary embodiment, the apparatus comprises a delay element having an input coupled to the first clock signal and an output producing a delayed first clock signal. The delay element further includes a plurality of delay latches, having a second clock signal as a clock input thereto, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal. The data signal is captured by the receiving element when the receiving element is triggered by an edge of the delayed first clock signal.

Description:
BACKGROUND  
         [0001]    The present invention relates generally to data processing systems and, more particularly, to an apparatus and method for capturing source synchronous data.  
           [0002]    With the advent of high-speed, parallel data interfaces, traditional edge clocking techniques of providing “setup and hold” around a capturing clock edge have proven to be increasingly more difficult to implement. As a result, source synchronous designs have been utilized to reduce the variations in timing interface between communicating components in a computer system.  
           [0003]    In source synchronous clocking, the data and clock signals are initially synchronized at the transmitting logic components, thus eliminating from the transmitting logic components the burden of accurately centering a clock edge within a “data valid region”. However, various processing and environmental conditions can cause the clock edge to be skewed relative to the data at the receiving logic, thereby resulting in an uncertainty of the relationship between data and clock. The positioning of the clock within the data valid region has thus become the responsibility of the receiving components. Such accurate positioning can be difficult to achieve due to the wide range of process variations and the effect they have on circuit delays.  
           [0004]    During the transmission of data, a data cycle is defined wherein the first segment of the data cycle represents a “data uncertainty region”, with the remaining segment of the data cycle representing a “data valid region”. Ideally, the edge (rising or falling) of the clock signal should arrive at some point during the data valid window segment of the data cycle to ensure the correct capture of data by the receiving component. Accordingly, the clock signal may be intentionally delayed until after the data uncertainty region has passed. Unfortunately, the delay elements traditionally used to correctly position the clock signal edge also have process variations introduced therein. These process variations can cause the delay elements to vary by as much as ±50%, and result in the clock edge arriving too early (i.e., during the data uncertainty region of the present data cycle) or too late (i.e., during the data uncertainty window of the next data cycle). In such a situation, the whole purpose of implementing a clock signal delay element would be defeated.  
         BRIEF SUMMARY  
         [0005]    The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by an apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an exemplary embodiment, the apparatus comprises a delay element having an input coupled to the first clock signal and an output producing a delayed first clock signal. The delay element further includes a plurality of delay latches, having a second clock signal as a clock input thereto, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal. The data signal is captured by the receiving element when the receiving element is triggered by an edge of the delayed first clock signal.  
           [0006]    In preferred embodiment of the invention, the apparatus includes a first stage of four parallel connected delay latches, each of the first stage of four parallel connected delay latches having an input coupled to the first clock signal. A second stage of four parallel connected delay latches is also included, with each of the second stage of four parallel connected delay latches having an input coupled to a corresponding output of the first stage of four parallel connected delay latches. Each of the four parallel connected delay latches within the first and second stages has a second clock frequency of 2.5 times the frequency of the first clock signal, with the second clock signal being applied to each delay latch 90 degrees out of phase with respect to one another in the first and second stages. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:  
         [0008]    [0008]FIG. 1 is a timing diagram illustrating the relationship between clock and data signals, the clock and data signals initially being synchronized at a transmitting source;  
         [0009]    [0009]FIG. 2 is a schematic diagram of an existing delay circuit element used for delaying a clock signal, the clock signal used to center a clock within a data valid region;  
         [0010]    [0010]FIG. 3 is a schematic diagram illustrating an apparatus for capturing a data signal sent from a transmitting source to a receiving element, the apparatus including a delay element, according to one embodiment of the invention;  
         [0011]    [0011]FIG. 4 is a timing diagram illustrating the characteristics of the delay element and apparatus shown in FIG. 4;  
         [0012]    [0012]FIG. 5 is a schematic diagram of an alternative embodiment of the delay element and apparatus in FIG. 3; and  
         [0013]    [0013]FIG. 6 is a timing diagram illustrating the characteristics of the delay element and apparatus shown in FIG. 5. 
     
    
     DETAILED DESCRIPTION  
       [0014]    Referring to FIG. 1, there is shown a timing diagram  10  which illustrates the relationship between clock (TBC) and data (TX) signals in a source synchronous system, the signals being synchronized at the transmitting logic. In the example shown, the signals are transmitted within a source synchronous application such as a 2 gigabit/second Fibre Channel physical layer to link layer communication.  
         [0015]    As the synchronous data (TX) and clock (TBC) signals are propagated to their intended destination (receiving logic), a timing skew may occur as indicated earlier. The timing diagram  10  illustrates a “clock skew region” or a “data uncertainty region”  12 , and a “data valid region”  14  within a defined data cycle period  16 . For the application illustrated, the data cycle period  16  is 4.7 nanoseconds (ns), during which time 10 bits of data are transmitted. Within a given data cycle, therefore, a first portion of the 4.7 ns represents the “data uncertainty region”  12  and the remaining portion of the 4.7 ns represents the “data valid region”  14 . As an alternative to expressing these regions in units of nanoseconds, they may also be expressed in terms of bit times of delay, wherein a bit time is defined as: 
         Bit Time=Data Cycle Time/# of bits transmitted per Data Cycle 
         [0016]    For the above example, then, one bit time equals 4.7 ns÷10=0.47 ns, where each bit time represents 10% of the entire data cycle. In the 2 gigabit/second application, the data uncertainty region  12  is the first four bit times of the data cycle (1.88 ns), while the data valid region  14  is the last six bit times of the data cycle (2.82 ns).  
         [0017]    Due to the timing skew of the clock signal edge, it is assumed from a design standpoint that the edge may arrive anywhere from the beginning of the data uncertainty region  12  to the end of the data uncertainty region  12 . If the clock edge arrives early with respect to the data signal (TX), then the data must be captured no sooner than 4 bit times (1.88 ns) after the clock edge in order to ensure the data is captured within the data valid region  14 . Conversely, if the clock edge arrives late with respect to the data signal, then the data must be captured no later than 6 bit times (2.88 ns) after the clock edge. Therefore, a data capture window  18  of 2 bit times (2.88 ns−1.88 ns-0.94 ns) is established in which the data should be captured. From a design standpoint, it is desirable to capture the data at the midpoint of the data valid region  14 , or at about 5 bit times (2.35 ns) after the clock edge.  
         [0018]    Referring now to FIG. 2, a simplified schematic illustrates an existing approach for introducing the 5 bit time (2.35 ns) delay for the clock signal. A delay element  20 , such as an analog signal buffer, is coupled between the clock signal (TBC) and a receiving element  22 . The receiving element  22 , for example, may comprise a data capture latch (such as a D flip-flop), which receives the data signal. Hereinafter, the term “data capture latch” is used interchangeably with “receiving element”.  
         [0019]    As mentioned previously, however, the shortcoming of the approach shown in FIG. 2 lies in the process variations of the delay element  20 . For example, a±50% variation in the delay time of the clock edge could result in a large delay of about 7.5 bit times (3.5 ns) or a small delay of about 2.5 bit times (1.18 ns). In either case, the data could end up being captured in the data uncertainty region of the present data cycle or the data uncertainty region of the next data cycle. This being the case, the entire purpose of introducing a delay element  20  for the clock signal (TBC) is defeated.  
         [0020]    One possible solution to the aforementioned drawbacks is shown in FIG. 3. In lieu of the delay element  20  of FIG. 2, an apparatus  40  features an improved delay element  50 , comprising a plurality of edge-triggered delay latches  52  (designated individually by “dlylth”  1  through  5 ) serially connected between the original first clock signal (TBC) and the data capture latch  22 . Each delay latch  52  is triggered by a second clock signal designated by “10×clk”, the frequency of which is ten times faster than the original first clock signal (TBC). In essence, the original first clock signal (TBC) becomes a data signal to be propagated through the plurality of delay latches  52 . By the time the original first clock signal (TBC) is propagated through the delay latches  52  and is received by the data capture latch  22 , enough time has passed so that data capture latch  22  captures the data signal within the data valid region  14  of the data cycle. In a preferred embodiment, the delay latches  52  are D flip-flops.  
         [0021]    Because “10×clk” operates ten times faster than the original first clock signal (TBC), each successive delay latch  52  therefore provides a one bit time (0.47 ns) delay as the original first clock signal (TBC) is propagated therethrough. Recalling that the minimum delay needed to bypass the data uncertainty region  12  of the present data cycle  16  is 4 bit times (1.88 ns), a minimum of four delay latches  52  (triggered by “10×clk”) are therefore used. However, since “10×clk” and the first original clock signal (TBC) are asynchronous, a fifth delay latch (dlylth  5 ) is used to compensate for that factor. Thus, the overall delay produced by delay latches  52  will be between 4-5 bit times (1.88 ns-2.32 ns), depending upon the initial relationship between the original first clock signal (TBC) and “10×clk” at the first delay latch (dlylth  1 ).  
         [0022]    [0022]FIG. 4 is a timing diagram which illustrates the delay of the first original clock signal (TBC) as applied to the data capture latch  22  when using the delay latches  52  shown in FIG. 3. As can be seen, a 4-5 bit time delay of the original first clock signal (TBC) is sufficient to ensure that the data signal (TX) is not captured during the data uncertainty region  12 . In addition, the potential problem of an “over delay” is also avoided. While there may be some process variations associated with the final stage of the delay latches  52 , they are an order of magnitude smaller than the delay of the final stage itself. As such, the overall processing variations may cause a variation in time delay of about 300 picoseconds (ps).  
         [0023]    Although the embodiment of the apparatus  40  shown in FIG. 3 alleviates the aforementioned drawbacks of the existing delay element  20  in FIG. 2, the use of a 10×clock may, in some cases, be relatively costly to implement. Therefore, in accordance with a preferred embodiment of the invention, an alternative delay element  70  is shown in FIG. 5. As a substitute for serially connected delay latches  52  operated by a 10×clock, delay element  70  employs a configuration of two stages  72 ,  74  of parallel delay latches  76 . Each individual latch  76  within a given stage of parallel delay latches are clocked out of phase with one another. The phase relationship, the operational clock frequency, and the number of the parallel delay latches  76  used is determined by the number of bit times needed for the desired time delay. For an “N” bit time delay, then, each stage  72 ,  74  will have N latches  76  connected in parallel, while the operational clock frequency thereof will be 10/N times the original first clock speed. Finally, the N parallel latches  76  in a given stage  72 ,  74  will each be clocked 360/N degrees out of phase with one another.  
         [0024]    For a 4 bit time delay, therefore, there are 4 parallel connected latches in each stage. The operational clock frequency of each latch  76  is 2.5 times the original clock frequency, with each clock signal being 90 degrees out of phase with one another. It will thus be appreciated that, rather than a having single delay latch sampling the original clock signal (data) once every bit time, four delay latches sample the data every four bit times. But, since each of the four delay latches  76  are 90 degrees out of phase with one another, the net effect is that the data is sampled every bit time. The second stage  74  of parallel latches, connected in series with the first stage  76  of parallel latches, is used to provide the minimum bit-time separation for a data capturing clock signal sent directly to the data capturing latch  22 . For example, if the 180° clock signal were to catch the incoming original clock signal edge, the output of the second stage delay latch triggered by the 180° clock signal captures the desired 4 bit time delayed signal. It should also be noted that each latch in the second stage  74  of delay element  70  is triggered by a clock signal  78  propagated through the corresponding phase latch in the first stage.  
         [0025]    A final delayed clock signal  80  may be generated by a four-input NAND gate  82  or a four-input OR gate  84 , both of which are depicted in FIG. 5. In either case, the four inputs to the particular gate used are the outputs  86  of the four second stage  74  parallel delay latches  76 . The NAND gate  82  provides data capture at the falling edge of the original clock signal (TBC), while the OR gate  84  provides data capture at the rising edge of the original clock signal (TBC). Depending upon which edge of the clock signal is desired to trigger data capture, either the NAND gate  82  or the OR gate  84  may be used.  
         [0026]    [0026]FIG. 6 is a timing diagram which illustrates the delay performance of delay element  70  in FIG. 5. From the top part of FIG. 6, it is seen how a 4-phase clock operating at 2.5 times the speed of the original clock is a functional equivalent of a single phase clock operating at 10 times the speed of the original clock. Recalling that a 10× clock provides a rising (or falling) edge once every bit time, this function is also achieved once every bit time by one of the four phases. Finally, as shown in the bottom portion of FIG. 6, the desired delay in this instance is realized when the clock signal of the 0° phase latch of the second stage  74  is triggered 4-5 bit times after the original clock signal (TBC), thus ensuring the data is ultimately captured during the data valid window. It should be noted that any of the four phases of the 2.5×clock signal may be the one which produces the 4-5 bit time delay, depending upon the skew (if any) of the original clock signal (TBC).  
         [0027]    From the foregoing description, it is seen that by taking advantage of the precise nature of the time delay inherent in a clocked memory element (i.e., a latch), a more reliable delay element may be utilized when compensating for process variations in receiving logic. And, if the cost of using high speed clocks becomes a concern, it is also seen how a slower speed clock may be used in an alternative delay element scheme, as illustrated by the embodiment of FIG. 5.  
         [0028]    While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.