Abstract:
A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.

Description:
CLAIM OF PRIORITY 
       [0001]    This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 61/185,371 filed Jun. 9, 2009. 
     
    
     TECHNICAL FIELD OF THE INVENTION 
       [0002]    The technical field of this invention is a high-performance flop with multiplexer at the input. 
       BACKGROUND OF THE INVENTION 
       [0003]    The problem of invention is a high-performance flop with multiplexer built into the input. This combination virtually hides the delay of the multiplexer, reducing a level of logic on critical paths. For the Texas Instruments TMS320C6400 family of digital signal processors (DSPs) this combination yields approximately a 5% frequency improvement over not having this invention. 
         [0004]    There is a problem with circuits of this type. Such circuits typically present a problem of stuck-at fault visibility. In prior art, test pin itself was not observable. This yields stuck-at-fault coverage loss. Latest reliability targets require greater than 99% stuck-at-fault coverage. 
       SUMMARY OF THE INVENTION 
       [0005]    This invention is a multibit combined multiplexer and flip-flop circuit having a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for each of a plurality of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled a corresponding logical AND and said corresponding inverter. 
         [0006]    The input section of each bit circuit may include a scan input and a scan input pass gate. The flip-flop section of each bit circuit further includes a scan output. Each per bit control section receives a scan enable input signal. 
         [0007]    The input section of each bit circuit further includes a test input terminal and a test select input terminal. The test select input selects input of the test signal or the scan input. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0009]      FIG. 1  is a circuit diagram of a prior art two-input multiplexer/flip-flop; 
           [0010]      FIG. 2  is a circuit diagram of a prior art four-input multiplexer/flip-flop including a test input; 
           [0011]      FIG. 3  is a circuit diagram of a two-input multiplexer/flip-flop according to this invention; 
           [0012]      FIG. 4  is a circuit diagram of a four-input multiplexer/flip-flop including a test input according to this invention; 
           [0013]      FIG. 5  is a circuit diagram of a six-input multiplexer/flip-flop including a test input according to this invention; 
           [0014]      FIG. 6  is a block diagram illustrating the manner of sharing decode logic among four two-input multiplexers according to this invention; and 
           [0015]      FIG. 7  is a block diagram illustrating the manner of sharing decode logic among four four-input multiplexers according to this invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0016]      FIG. 1  illustrates a prior art two-input multiplexer/flip-flop  100 .  FIG. 1  illustrates a single bit circuit of what is generally a multi-bit circuit. Multiplexer/flip-flop  100  includes: input section  110  including pass gates  111 ,  112  and  114  and inverter  113 ; master flip-flop section  120  including controlled inverters  121  and  122 , inverter  123  and pass gate  124 ; slave flip-flop section  130  including inverters  131 ,  132 ,  134  and  135  and pass gate  133 ; and control section  140  including inverters  141 ,  142 ,  144 ,  145  and  148 , AND gates  143  and  147  and pass gate  146 . 
         [0017]    Input section  110  receives data inputs d 0  and d 1  and selection input s 0 . Pass gates  111  and  112  are driven by opposite polarities of selection input s 0  employing inverter  113 . Depending upon the digital state of selection input s 0 , one and only one of pass gates  111  and  112  are conducting the other pass gate in non-conducting. If pass gate  111  is conducting and pass gate  112  is non-conducting, then input section  110  selects input d 1 . If pass gate  112  is conducting and pass gate  111  is non-conducting, then input section  110  selects input d 0 . The selected input signal supplies the input of pass gate  114 . When conducting pass gate  114  couples the selected input to master flip-flop section  120 . 
         [0018]    Master flip-flop section  120  includes a latch formed by cross-coupled inverters  121  and  122 . Under the proper combination of input control signals the data from the selected data source d 0  or d 1  is stored in this latch. At the proper time in the cycle of clock clk pass gate  124  supplies the state of the master flip-flop to slave flip-flop section  130 . 
         [0019]    Slave flip-flop section  130  includes a gated latch formed of inverters  131  and  132  and pass gate  133 . Inverter  134  generates a q output of the state of the latch. Inverter  135  generates a scan output signal so of the opposite state of the latch. 
         [0020]    Control section  140  receives various input signal and generates control signals for pass gates  111 ,  112 ,  114 ,  124  and  133  and controlled inverters  121  and  122 . Control section  140  receives a clock signal clk, a scan enable signal se and a scan data input si. Inverter  141  generates an inverted clock signal clkz 1 . Inverter  142  generates an inverted scan enable signal sez. NAND gate  143  combines clkz 1  and sez to generate int 1 . Inverter  144  generates the inverse signal int 1   z.  The pair of signals int 1  and int 1   z  control pass gate  114  and controlled inverter  122 . NAND gate  147  combines clkz 1  and se to generate int 0 . Inverter  148  generates the inverse signal int 0   z.  The pair of signals in 01  and int 0   z  control pass gate  146  and controlled inverter  121 . Inverter  145  inverts scan data input si. Inverter  145  supplies pass gate  146  controlled by int 0  and int 0   z.  Depending upon the state of scan enable signal se only one of the paired signals int 0 /int 0   z  or int 1 /int 1   z  are active cycling with the clock signal clk. 
         [0021]    Two-input multiplexer/flip-flop  100  operates generally as follows. Select signal s 0  determines selection of either input d 0  or input d 1 . When in normal mode as selected by scan enable signal se, the selected signal is passed to master flip-flop section  120  and then to slave flip-flop section  130  where it becomes available at output q. When in scan mode as selected by scan enable signal se, scan input si is input to master flip-flop section  120 . This scan input is passed to slave flip-flop section  130  and becomes available at scan output so. Table 1 summarizes this operation. 
         [0000]                            TABLE 1               se   s0   Next Output                   0   0   d0       0   1   d1       1   X   si                    
When scan is enabled (se=1), two-input multiplexer/flip-flop  100  ignores the data inputs d 0  and d 1  whatever the state of select signal s 0  (s 0  is X or don&#39;t care) and stores scan input si.
 
         [0022]    There are several disadvantageous aspects of the two-input multiplexer/flip-flop  100 . This circuit has a longer than necessary setup time. Note that the input path of two-input multiplexer/flip-flop  100  includes two layers of pass gates. An input signal must pass a first pass gate layer at pass gate  111  or  112  and a second pass gate layer at pass gate  114 . This leads to a larger setup than necessary. These two layers of pass gates require a larger driver circuit. Such a larger driver circuit requires greater silicon area and results in more power consumption. These factors all lead to a disadvantageous circuit combination. 
         [0023]      FIG. 2  illustrates a prior art four-input multiplexer/flip-flop  200 .  FIG. 2  illustrates a single bit circuit of what is generally a multi-bit circuit. Multiplexer/flip-flop  200  includes: input section  210  including pass gates  211 ,  212 ,  213 ,  214 ,  216  and  217  and driver  215 ; master flip-flop section  220  is similar to master flip-flop section  120 ; slave flip-flop section  230  is similar to slave flip-flop section  130 ; and control section  240  including inverters  241 ,  242 ,  243 ,  244 ,  245 ,  246 ,  247 ,  249  and  251 , NOR gates  248  and  250 . 
         [0024]    Input section  210  receives data inputs d 0 , d 1 , d 2  and d 3 , selection signal pairs s 0 /s 0   z,  s 1 /s 1   z,  s 2 /s 2   z  and s 3 /s 3   z  and scan input si. Depending upon the state of the selection signal pairs s 0 /s 0   z,  s 1 /s 1   z,  s 2 /s 2   z  and s 3 /s 3   z  one of pass gates  211 ,  212 ,  213  and  214  passes the corresponding input signal d 3 , d 2 , d 1  or d 0 . The selection signals pairs s 0 /s 0   z,  s 1 /s 1   z,  s 2 /s 2   z  and s 3 /s 3   z  are controlled to open only one of the pass gates  211 ,  212 ,  213  and  214 . The selected input signal supplies the input of pass gate  216 . When conducting pass gate  216  couples the selected input to master flip-flop section  220 . This operation is very similar to that of input section  110  except that there are four inputs in input section  210  and they are uncoded as contrast to the coded input used in input section  110 . Pass gate  217  when enabled couples scan input s 1  to master flip-flop section  220 . 
         [0025]    Input section  210  further includes a testz input driving the gates of dual MOS transistor driver  215 . A signal upon the testz input forces master flip-flop section  220  into a predetermined state regardless of other inputs. This testz input enables test of multiplexer/flip-flop  200 . 
         [0026]    Master flip-flop section  220  is similar to master flip-flop section  120  and will not be described in detail. 
         [0027]    Slave flip-flop section  230  is similar to slave flip-flop section  130  and will not be described in detail. 
         [0028]    Control section  240  receives the control signals and generates corresponding signals used in multiplexer/flip-flop  200 . Control section  240  receives input signals clk, s 0 , s 1 , s 2 , s 3 , se and si and generates control signals for pass gates  211 ,  212 ,  213 ,  214 ,  216  and  217  and the controlled inverters in master flip-flop section  220  and slave flip-flop section  230 . Inverter  241  generates an inverted clock signal clkz 1 . Inverter  242  generates a further inverted clock signal clkb. Inverter  243  generates an inverted s 0  signal s 0   z.  Control signals s 0  and s 0   z  control the operation of pass gate  214 . Inverter  242  generates an inverted s 1  signal s 1   z.  Control signals s 1  and s 1   z  control the operation of pass gate  213 . Inverter  245  generates an inverted s 2  signal s 2   z.  Control signals s 2  and s 2   z  control the operation of pass gate  212 . Inverter  246  generates an inverted s 3  signal s 3   z.  Control signals s 3  and s 3   z  control the operation of pass gate  211 . Inverter  247  generates an inverted enable signal sez. NOR gate  248  combines clkz and se to generate clkd and inverter  249  generates its inverse clkdz. Signals clkd and clkdz control pass gate  216 . NOR gate  250  combines clk and sez to generate clks and inverter  251  generates its inverse clksz. Signals clks and clksz control pass gate  217 . 
         [0029]    Four-input multiplexer/flip-flop  200  operates generally as follows. Select signals s 0 , s 1 , s 2  and s 3  determine selection of either input d 0 , d 1 , d 2  or d 3 . When enabled by scan enable signal se, the selected signal is passed to master flip-flop section  220  and then to slave flip-flop section  230  where it becomes available at output q. Testz places master flip-flop  220  in a known state. Si when enabled by clks/clksz places master flip-flop  220  in a known state. 
         [0030]    There are several disadvantageous aspects of the four-input multiplexer/flip-flop  200 . As the case of two-input multiplexer/flip-flop  100  this circuit has a longer than necessary setup time. The input path of four-input multiplexer/flip-flop  200  includes two layers of pass gates. An input signal must pass a first pass gate layer at pass gate  211 ,  212 ,  213  or  214  and a second pass gate layer at pass gate  216 . This leads to a larger setup time than necessary. Such plural pass gate levels require a larger driver circuit. Such a larger driver circuit requires greater silicon area and results in more power consumption. These factors all lead to a disadvantageous circuit combination. 
         [0031]    Four-input multiplexer/flip-flop  200  includes an additional disadvantage. Four-input multiplexer/flip-flop  200  includes no provision for testing the testz input. Failure of the testz input cannot be detected in four-input multiplexer/flip-flop  200 . This is disadvantageous in requiring indirect diagnosis of faults in the testz input. 
         [0032]      FIG. 3  illustrates a two-input multiplexer/flip-flop  300  according to this invention.  FIG. 3  generally illustrates a single bit circuit of what is generally a multi-bit circuit. Two-input multiplexer/flip-flop  300  is a substitute for prior art two-input multiplexer/flip-flop  100 . Two-input multiplexer/flip-flop  300  includes: input section  310  including pass gates  311 ,  312  and  314  and inverter  313 ; master flip-flop section  320  is similar to master flip-flop section  120 ; slave flip-flop section  330  is similar to slave flip-flop section  130 ; per bit control section  340  including inverters  341 ,  342 ,  343  and  344 ; and shared control section  350  including inverters  351 ,  352  and  354  and NAND gates  353 ,  355 ,  356  and  357 . 
         [0033]    Input section  310  receives data inputs d 0  and d 1  and scan input si. Note that shared control section  350  receives selection input s 0 . Per bit control section  340  and shared control section  350  cooperate to generate the paired control signals s 0 _clk/s 0 _clkz, s 1 _clk/s 1 _clkz and se_clk/se_clkz. Paired control signals s 0 _clk/s 0 _clkz control pass gate  312 . Paired control signals s 1 _clk/s 1 _clkz control pass gate  311 . Pass gates  311  and  312  are driven by opposite polarities of selection input s 0 . Depending upon the digital state of selection input s 0 , one and only one of pass gates  311  and  312  is conducting the other pass gate in non-conducting. If pass gate  311  is conducting and pass gate  312  is non-conducting, then input section  310  selects input d 1 . If pass gate  312  is conducting and pass gate  311  is non-conducting, then input section  310  selects input d 0 . The selected input signal supplies the input of master flip-flop section  320 . Inverter  313  receives scan input s 1  and drives pass gate  314 . Pass gate  314  is controlled by the signal pair se_clk/se_clkz. Pass gate  314  when enabled supplies scan input si to master flop-flop section  320 . 
         [0034]    Master flip-flop section  320  is similar to master flip-flop section  120  and will not be described in detail. 
         [0035]    Slave flip-flop section  330  is similar to slave flip-flop section  130  and will not be described in detail. 
         [0036]    Per bit control section  340  operates in conjunction with shared control section  350 . Shared control section  350  receives input signals clk, se and s 0  for a set of similarly controlled bit circuits and generates intermediate control signals s 0 _clkz, s 1 _clkz, se_clkz and fb_clk. Per bit control section  340  of each bit circuit receives these intermediate signals and generates control signals s 0 _clk, s 1 _clk, se_clk and fb_clkz which control operation of two-input multiplexer/flip-flop  300 . 
         [0037]    Shared control section  350  includes inverters  351 ,  352  and  354  and NAND gates  353 ,  355 ,  356  and  357 . Inverter  351  receives clock signal clk and generates inverse clock signal clkz. Inverter  352  receives enable signal se and generates inverse enable signal sez. NAND gate  353  receives signal fb_clkz and selection signal s 0  and generates signal s 0 _clkz. Inverter  354  receives selection signal s 0  and supplies one input to NAND gate  355 . Another input of NAND gate  355  receives signal fb_clkz. NAND gate  355  generates signal s 1 _clkz. NAND gate  356  receives inputs scan enable signal se and inverted clock signal clkz and generates signal se clks. NAND gate  356  receives inverted scan enable signal sez and the inverted clock signal clkz and generates signal fb_clk. 
         [0038]    Per bit control section  340  includes inverters  341 ,  342 ,  343  and  344 . Inverter  341  receives signal s 0 _clkz and generates signal s 0 _clk. Inverter  342  receives signal s 1 _clkz and generates signal s 1 _clk. Inverter  343  receives signal se_clkz and generates signal se clk. Inverter  344  receives signal fb_clk and generates signal fb_clkz. 
         [0039]    Two-input multiplexer/flip-flop  300  operates generally as follows. Select signal s 0  determines selection of either input d 0  or input d 1 . When enabled by scan enable signal se, the selected signal is passed to master flip-flop section  120  and then to slave flip-flop section  130  where it becomes available at output q. Scan input si supplies master flip-flop section  320  when enabled by scan enable signal se. 
         [0040]    Two-input multiplexer/flip-flop  300  of this invention is advantageous over prior art two-input multiplexer/flip-flop  100 . The two layer pass gate input of prior art two-input multiplexer/flip-flop  100  is replaced by a single layer pass gate input in two-input multiplexer/flip-flop  300  of this invention. This reduction is pass gate layers is achieved by making input pass gates  311  and  312  of this invention controlled by clocked signal pairs s 0 _clk/s 0 _clkz and s 1 _clk/s 1 _clkz. This combines the input selection of pass gates  111  and  112  and the clocking of pass gate  114  in a single layer of pass gates. This results in reduced setup time, reduced driver size and reduced power consumption. 
         [0041]      FIG. 4  illustrates a four-input multiplexer/flip-flop  400  of this invention.  FIG. 4  illustrates a single bit circuit of what is generally a multi-bit circuit. Four-input multiplexer/flip-flop  400  includes: input section  410  including pass gates  411 ,  412 ,  413 ,  414 ,  416 ,  417  and  421 , driver  415  and inverter  419 ; master flip-flop section  430  is similar to master flip-flop section  120 ; slave flip-flop section  440  is similar to output section  130 ; per bit control section  450  including inverters  441 ,  442 ,  443 ,  444 ,  445  and  456  and pass gates  441 ,  442  and  445 ; and shared control section  460  including inverters  461  and  462  and NAND gates  463 ,  464 ,  465 ,  466 ,  467  and  468 . 
         [0042]    Input section  410  receives data inputs d 0 , d 1 , d 2  and d 3 , selection signal pairs s 0 _clk/s 0 _clkz, s 1 _clk/s 1 _clkz, s 2 _clk/s 2 _clkz and s 3 _clk/s 3 _clkz. Depending upon the state of the selection signal pairs s 0 _clk/s 0 _clkz, s 1 _clk/s 1 _clkz, s 2 _clk/s 2 _clkz and s 3 _clk/s 3 _clkzz one of pass gates  411 ,  412 ,  413  and  414  passes the corresponding input signal d 3 , d 2 , d 1  or d 0 . The selection signals pairs s 0 _clk/s 0 _clkz, s 1 _clk/s 1 _clkz, s 2 _clk/s 2 _clkz and s 3 _clk/s 3 _clkz are controlled to open only one of the pass gates  411 ,  412 ,  413  and  414 . The selected input signal supplies the input of master flip-flop section  430 . 
         [0043]    Input section  410  further includes a testz input driving the gates of dual MOS transistor driver  415 . A signal upon the testz input forces master flip-flop section  420  into a predetermined state regardless of other inputs. This testz input enables test of multiplexer/flip-flop  400 . 
         [0044]    Input section  410  further includes pass gate  416  receiving scan input signal si. Pass gate  417  receives test signal testz. Inverter  418  receives test active signal tc and generates its inverse. Pass gates  416  and  417  are driven by opposite polarities of test active signal tc. Depending on the signal level of test active signal tc only one of pass gates  416  or  417  is conducting. The output of pass gates  416  and  417  drive the input to inverter  419 . The output of inverter  419  drives the input of pass gate  420 . Pass gate  420  is controlled by the signal pair se_clk/se_clkz. Depending on the signal level of test active signal tc, one of initialization signal si or test signal testz is supplied to master flip-flop section  430 . 
         [0045]    Master flip-flop section  430  is similar to master flip-flop section  120  and will not be described in detail. 
         [0046]    Slave flip-flop section  440  is similar to slave flip-flop section  130  and will not be described in detail. 
         [0047]    Per bit control section  450  operates in conjunction with shared control section  460 . Shared control section  460  receives clock signal clk, scan enable signal se and selection signals s 0 , s 1 , s 2  and s 3  for a set of similarly controlled bit circuits and generates intermediate control signals s 0 _clkz, s 1 _clkz, s 2 _clkz, s 3 _clkz, se_clkz and fb_clk. Per bit control section  350  of each bit circuit receives these intermediate signals and generates control signals s 0 _clk, s 1 _clk, s 2 _clk, s 3 _clk, se_clk and fb_clkz which control operation of two-input multiplexer/flip-flop  400 . 
         [0048]    Shared control section  460  includes inverters  461  and  462  and NAND gates  463 ,  464 ,  465 ,  466 ,  467  and  468 . Inverter  461  receives clock signal clk and generates inverse clock signal clkz. Inverter  462  receives scan enable signal se and generates inverse scan enable signal sez. NAND gate  463  receives inverted clock signal clkz, inverted scan enable signal sez and selection signal s 0  and generates signal s 0 _clkz. NAND gate  464  receives inverted clock signal clkz, inverted scan enable signal sez and selection signal s 1  and generates signal s 1 _clkz. NAND gate  465  receives inverted clock signal clkz, inverted scan enable signal sez and selection signal s 0  and generates signal s 0 _clkz. NAND gate  466  receives inverted clock signal clkz, inverted scan enable signal sez and selection signal s 3  and generates signal s 3 _clkz. NAND gate  467  receives inputs scan enable signal se and inverted clock signal clkz and generates signal se clks. NAND gate  468  receives inverted scan enable signal sez and the inverted clock signal clkz and generates signal fb_clk. 
         [0049]    Per bit control section  450  includes inverters  451 ,  452 ,  453 ,  454 ,  455  and  456 . Inverter  451  receives signal s 0 _clkz and generates signal s 0 _clk. Inverter  452  receives signal s 1 _clkz and generates signal s 1 _clk. Inverter  453  receives signal s 2 _clkz and generates signal s 2 _clk. Inverter  454  receives signal s 3 _clkz and generates signal s 3 _clk. Inverter  455  receives signal se_clkz and generates signal se_clk. Inverter  456  receives signal fb_clk and generates signal fb_clkz. 
         [0050]    Four-input multiplexer/flip-flop  200  operates generally as follows. Select signals s 0 , s 1 , s 2  and s 3  determine selection of either input d 0 , d 1 , d 2  or d 3 . When enabled by scan enable signal se (scan disabled), the selected signal is passed to master flip-flop section  4300  and then to slave flip-flop section  440  where it becomes available at output q. Testz places master flip-flop  430  in a known state. Scan input si when enabled by clks/clksz supplies the input of master flip-flop  430 . 
         [0051]    Four-input multiplexer/flip-flop  400  has two advantages over prior art four-input multiplexer/flip-flop  200 . The first advantage is a reduction in the number of pass gate layers in input section  410 . Control of pass gates  411 ,  412 ,  413  and  414  by clocked versions of the enable signals enables use of a single pass gate level (pass gates  411 ,  412 ,  413  and  414 ) rather than the two pass gate levels (first  211 ,  212 ,  213  and  214  and second pass gate  216 ) of prior art four-input multiplexer/flip-flop  200 . This advantage is described above in conjunction with two-input multiplexer/flip-flop  300 . Four-input multiplexer/flip-flop  400  includes another advantage in the second testz input. Four-input multiplexer/flip-flop  400  provides a second input for the testz signal by muliplexing with scan input signal si. This second input enables testing the original test input. 
         [0052]      FIG. 5  illustrates a six-input multiplexer/flip-flop  500  of this invention.  FIG. 5  illustrates a single bit circuit of what is generally a multi-bit circuit. Six-input multiplexer/flip-flop  500  includes: input section  510  including pass gates  511 ,  512 ,  513 ,  514 ,  515 ,  516 ,  517 ,  518  and  522 , driver  517  and inverters  520  and  521 ; master flip-flop section  530  is similar to master flip-flop section  120 ; slave flip-flop section  540  is similar to output section  130 ; per bit control section  550  including inverters  551 ,  552 ,  553 ,  554 ,  555 ,  556 ,  557  and  558 ; and shared control section  460  including inverters  561  and  562  and NAND gates  563 ,  564 ,  565 ,  566 ,  567 ,  568 ,  560  and  570 . Six-input multiplexer/flip-flop  500  is very similar to four-input multiplexer/flip-flop  400  with the addition of two pass gates in input section  510 , two inverters in per bit control section  550  and two NAND gates in shared control section  560  to accommodate two additional inputs. Six-input multiplexer/flip-flop  500  includes the same advantages over the prior art as previously noted above in conjunction with four-input multiplexer/flip-flop  400 . 
         [0053]      FIG. 6  illustrates circuit  600  connecting plural two-input multiplexer/flip-flop sections  611 ,  612 ,  613  and  614  with shared control section  660 . Each of two-input multiplexer/flip-flop sections  611 ,  612 ,  613  and  614  receives a corresponding bit of two multibit signals a&lt;3:0&gt; and b&lt;3:0&gt; and generates a corresponding bit output q&lt;3:0&gt;. Each of two-input multiplexer/flip-flop circuits  611 ,  612 ,  613  and  614  and shared control section  660  receive the clock signal clk. Shared control section  660  also receives control signals s 0  and s 1  and scan enable signal se. Shared control section  660  generates intermediate signals s 0 _clkz, s 1 _clkz and se_clkx which are transmitted to each of the two-input multiplexer/flip-flop sections  611 ,  612 ,  613 ,  614 ,  615  and  616 . Two-input multiplexer/flip-flop section  611  receives scan input signal si. Each two-input multiplexer/flip-flop section  611 ,  612  and  613  passes a scan output so to the scan input si of a next two-input multiplexer/flip-flop section  612 ,  613  and  614 . 
         [0054]      FIG. 7  illustrates circuit  700  connecting plural four-input multiplexer/flip-flop sections  711 ,  712 ,  713  and  714  with shared control section  760 . Each of four-input multiplexer/flip-flop sections  711 ,  712 ,  713  and  714  receives a corresponding bit of four multibit signals a&lt;3:0&gt;, b&lt;3:0&gt;. c&lt;3:0&gt; and d&lt;3:0&gt; and generates a corresponding bit output q&lt;3:0&gt;. Each of four-input multiplexer/flip-flop circuits  711 ,  712 ,  713  and  714  and shared control section  760  receive the clock signal clk. Shared control section  760  also receives control signals s 0 , s 1 , s 2  and s 3  and an enable signal se. Shared control section  760  generates intermediate signals s 0 _clkz, s 1 _clkz, s 2 _clkz, s 3 _clkz and se_clkz which are transmitted to each of the four-input multiplexer/flip-flop sections  711 ,  712 ,  713  and  714 . Four-input multiplexer/flip-flop section  711  receives the scan input signal si. Each four-input multiplexer/flip-flop section  711 ,  712  and  713  passes a scan output so to the scan input si of a next two-input multiplexer/flip-flop section  712 ,  713  and  714 . Each of the four-input multiplexer/flip-flop sections  711 ,  712 ,  713  and  714  receives a test input testz and a test active signal tc. 
         [0055]    Table 2 lists a comparison of propertied of the prior art four-input multiplexer/flip-flop  200  illustrated in  FIG. 2  with those of four-input multiplexer/flip-flop  400  illustrated in  FIG. 4 . 
         [0000]    
       
         
               
               
               
             
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Prior Art 200 
                 Invention 400 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 clk2q1 
                 29.86 
                 29.85 
               
               
                   
                 clk2q0 
                 27.35 
                 27.90 
               
               
                   
                 setup1 
                 87.82 
                 54.71 
               
               
                   
                 setup0 
                 109.20 
                 65.59 
               
               
                   
                 hold0 
                 30.73 
                 24.04 
               
               
                   
                 hold1 
                 31.65 
                 31.84 
               
               
                   
                 BHT 
                 136.06 
                 95.44 
               
               
                   
                 Vx/V1 
                 100% 
                  69% 
               
               
                   
                 Fscaling 
                 100% 
                 143% 
               
               
                   
                 Average Leakage 
                 −9.20E−06 
                 −1.35E−05 
               
               
                   
                 Vx/V1 
                 100% 
                 147% 
               
               
                   
                 Average clock non- 
                 −1.28E−14 
                 −1.40E14  
               
               
                   
                 toggling power 
               
               
                   
                 Vx/V1 
                 100% 
                 109% 
               
               
                   
                   
               
             
          
         
       
     
         [0056]    In Table 2: clk2q1 and clk2q0 are the times from the rising edge of the clock signal clk until corresponding data d 1  or d 0  arrives on the q output of the circuit; setup0 and setup1 are the length of the interval before the rising clock edge of the clk signal the respective data inputs d 0  and d 1  must be present to be sensed; hold0 and hold1 are the respective hold times for inputs d 0  and d 1 ; BHT is the so-called black hole time which it the sum of the setup time and the clock to q time. The Vx/V1 rows are percentage comparisons with the prior art set to 100%. The Fscaling row shows the percentage improvement in BHT of this invention.