Abstract:
Controllers and related control methods for a switched mode power supply are disclosed. The switched mode power supply has an inductive device and a power switch connected in series. An output current estimator in a controller is configured for receiving a current-sense signal representing an inductor current flowing through the inductive device and a discharge-time signal indicating a discharge time of the inductive device. The output current estimator generates a charge current in response to the discharge-time signal and the current-sense signal, thereby the charge current substantially corresponding to an output current that the switched mode power supply outputs to a load. The charge current is limited not to exceed a maximum value. A current limiter is configured for limiting the current-sense signal when the charge current is the maximum value.

Description:
BACKGROUND 
       [0001]    The present disclosure relates generally to switched mode power supplies, and especially to power supplies capable of generating and employing signals estimating an output current to a load. 
         [0002]    A switched mode power supply commonly utilizes a power switch to control the current flowing through an inductive device. 
         [0003]    In comparison with other kinds of power supply, switched mode power supplies usually enjoy compact size and excellent conversion efficiency, and are accordingly popular in the art. 
         [0004]    Power supplies with flyback topology are welcome because they provide Galvanic isolation. Flyback topology employs a transformer to direct-current isolate input power lines electrically connected to an AC mains outlet from output power lines electrically connected to a load. A primary side commonly refers to the side where the circuits are connected to input power lines, and a secondary side refers to the side where the circuits are connected to output power lines. Secondary side control uses resistors or devices in the secondary side to directly sense the current flowing to a load or the voltage across the load. Output voltage and current regulation can be easily achieved using secondary side control in expense of extra power consumption as the device in the secondary side constantly consume electrical power all the time, probably lowering power conversion efficiency. US patent application publication US20100321956A1, which is incorporated herein by reference in its entirety, discloses several switched mode power supplies employing primary side control to regulate their output currents in the secondary side. US patent application publication US20100321956A1 could make the maximum output current from a switched mode power supply a constant, independent from the voltages at input power lines. 
         [0005]    Load compensation is a kind of skill to increase the output voltage of a power supply when an output current to a load increases, in order to compensate the voltage lost over the cables connected between a load and the power supply. One conventional method to achieve load compensation is by using a peak current through a transformer to represent the output current to a load and to adjust a target voltage that an output voltage of a power supply tends to approach. As known in the art, the peak current is so different from the output current and can hardly represent it. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0007]      FIG. 1  shows a switched mode power supply according to embodiments of the invention; 
           [0008]      FIG. 2  demonstrates some waveforms of the signals in  FIG. 1 ; 
           [0009]      FIG. 3  exemplifies the power controller in  FIG. 1 ; 
           [0010]      FIG. 4  exemplifies the output current estimator in  FIG. 3 ; 
           [0011]      FIG. 5A  demonstrates a relationship between the charge current I CHARGE  and voltage V M  according to embodiments of the invention; and 
           [0012]      FIG. 5B  demonstrates a relationship between the offset current I OFFSET  and charge current I CHARGE  according to embodiments of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    An embodiment of the invention has a controller in the primary side, which generates estimation signals in response to a current flowing through the primary winding of a transformer and a discharge time of the transformer. One of estimation signals is a charge current, generation method of which will be detailed to prove its representativeness of an output current of a power supply. By limiting the maximum value of the charge current, the output current can also be regulated to be no more than the maximum rating of the power supply. Furthermore, as the charge current accurately or considerably represents the output current, it can act as one input to generate an offset current for load compensation, obtaining a much-well-controlled result. 
         [0014]      FIG. 1  is a non-limiting switched mode power supply  10  according to embodiments of the invention, which employs primary side control. Bridge rectifier  20  performs full-wave rectification, converting the alternative-current (AC) power source from an AC mains outlet into a direct-current (DC) input power source V IN . The voltage of input power source V IN  could have an M-shaped waveform or be substantially a constant. Power controller  26  could be an integrated circuit with pins connected to peripheral devices. Via driving node GATE, power controller  26  periodically turns ON and OFF a power switch  34 . When power switch  34  is ON, a primary winding PRM of the transformer energizes. When it is OFF, the transformer de-energizes via a secondary winding SEC and an auxiliary winding AUX to build up an output power source V OUT  for load  24  and operation a power source V CC  for power controller  26 . Connected between load  24  and the secondary winding SEC are cables  38 , whose resistances are denoted by resistors therein. 
         [0015]    A voltage divider consisting of resisters  28  and  30  detects voltage drop V AUX  over the auxiliary winding AUX, to provide a feedback voltage signal V FB  to a feedback node FB of power controller  26 . When power switch  34  is OFF, the voltage drop V AUX  is a reflective voltage in proportion to the voltage drop across the secondary winding SEC. Based on feedback voltage signal V FB , power controller  26  controls the duty cycle of the power switch  34  accordingly. Via a current-sense node CS, power controller  26  detects current-sense voltage V CS , which represents the current I PRM  flowing through not only the current-sense resistor  36 , but also power switch  34  and primary winding PRM. 
         [0016]      FIG. 2  demonstrates some waveforms of the signals in  FIG. 1 . Driving signal V GATE  on the driving node GATE is 1 in logic to turn on the power switch  34 . The period of time when the power switch  34  is ON is named as ON time T ON , and that when the power switch is OFF is OFF time T OFF , as shown in  FIG. 2 . One cycle time T CYC  is equal to the combination of one ON time T ON  and one OFF time T OFF , shown in  FIG. 2 . During ON time T ON , the voltage drop V AUX  is negative, reflecting the voltage of the input power source V IN . Meanwhile, current-sense voltage V CS , which in a way represents the primary-winding current I PRM , increases over time as primary winding PRM energizes. At the moment when the power switch  34  is switched to be OFF, the secondary winding SEC starts generating the secondary-winding current I SEC , which decreases over time until the secondary winding SEC completely de-energizes. As shown in  FIG. 2 , The period of time when the secondary winding SEC is de-energizing or the secondary-winding current I SEC  is positive is named as discharge time I DIS . During discharge time T DIS , the voltage drop V AUX  is positive, substantially reflecting the voltage of the output power source V OUT . After the discharge time T DIS , the voltage drop V AUX  oscillates and converges to 0. In  FIG. 2 , discharge time T DIS  is only a portion of OFF time T OFF  because the switched mode power supply  10  is supposed to operate in discontinuous conduction mode (DCM). In case that the switched mode power supply  10  operates in continuous conduction mode (CCM), the discharge time T DIS  is about the same as the OFF time T OFF . 
         [0017]      FIG. 3  exemplifies the power controller  26  in  FIG. 1 . An oscillator  72  periodically sets the SR register  78  such that driving signal V GATE  becomes 1 in logic, starting ON time T ON . A sample and hold circuit  62  samples feedback voltage signal V FB  timely during the discharge time T DIS , and an error amplifier  68  compares a predetermined target voltage V TAR  with the output of sample and hold circuit  62  to generate compensation voltage V COM . When current-sense voltage V CS  exceeds compensation voltage V COM , comparator  74  resets the SR register  78 , starting OFF time T OFF , during which current-sense voltage V CS  suddenly drops to 0 as shown in  FIG. 2 . In other words, the compensation voltage V COM  controls the peak value of current-sense voltage V CS . 
         [0018]    A discharge time finder  64  is connected to feedback node FB, and by detecting the waveform of feedback voltage signal V FB  it provides a discharge-time signal S DIS , to indicate the duration of discharge time T  DIS . The discharge-time signal S DIS  is not necessary to be synchronous with the discharge time T DIS . In one embodiment for example, the discharge-time signal S DIS turns into 1 in logic later than the discharge time T DIS  starts and into 0 in logic later than the discharge time T DIS  ends, such that the duration when the discharge-time signal S DIS  is 1 is about equal to the duration of the discharge time T DIS . 
         [0019]    In response to the discharge-time signal S DIS  and the current-sense voltage V CS , an output current estimator  70  provides load representative V LC  to load compensation circuit  66 , where load representative V LC  corresponds to a charge current I CHARGE  which, as will be detailed later, is substantially in proportion to output current I OUT  to load  24  of  FIG. 1 . Load compensation circuit  66  generates an offset current I OFFSET  draining from the feedback node FB to ground during the discharge time T DIS . Generally, the larger the output current I OUT , the larger the charge current I CHARGE , the larger the offset current I OFFSET , the higher the voltage drop V AUX  to keep the output of the sample and hold circuit  62  substantially equal to the target voltage V TAR , the higher the output power source V OUT . Accordingly, load compensation circuit  66  could render the output power source V OUT  to be substantially equal to the equation of “I OUT *K 1 +K 2 *V TAR ”, where K 1  and K 2  are two constants. With proper resistance selection on resistors  28  and  30 , I OUT *K 1  could compensate the voltage drop across the cables  38  in  FIG. 1 , such that the load  24  receives a well-regulated power source with voltage of K 2 *V TAR . According, load compensation can be achieved precisely. 
         [0020]    Output current estimator  70  further provides limiting voltage V LIMIT  to comparator  76 . Once the current-sense voltage V CS  exceeds the limiting voltage V LIMIT , comparator  76  resets SR register  78 , ending ON time T ON  and starting OFF time T OFF . Limiting voltage V LIMIT  could control the peak value of current-sense voltage V CS . 
         [0021]      FIG. 4  exemplifies output current estimator  70 , which has a transconductor  90 , level shifters  92  and  94 , an update circuit  96 , an accumulation capacitor  98 , a switch  104 , a voltage-controlled current source  102 , and a CS peak voltage detector  100 . 
         [0022]    CS peak voltage detector  100  generates voltage V CS-PEAK  representing the peak value of the current-sense voltage V as . An embodiment of CS peak voltage detector  100  has been shown by  FIG. 10  in US patent application publication US20100321956A1. In some embodiments, the CS peak voltage detector  100  could be replaced by an average voltage detector exemplified by  FIG. 17  or  18  in US patent application publication US20100321956A1. Voltage-controlled current source  102  converts voltage V CS-PEAK  into a discharge current I DIS , which discharges the accumulation node ACC only when discharge-time signal S DIS  is 1 in logic. In other word, the discharge current I DIS  equivalently discharges the accumulation node ACC during the discharge time T DIS . Switch  104  shown in  FIG. 4  might be omitted in some other embodiments where the discharge-time signal S DIS  is used to activate or deactivate the voltage-controlled current source  102 . Voltage V M  on capacitor  99  is level-shifted to compare with a predetermined reference voltage V REF  by transconductor  90 , which accordingly outputs a charge current I CHARGE  charging the accumulation node ACC all the time. By sensing charge current I CHARGE , load representative V LC  is generated. Update circuit  96  samples feedback voltage V ACC  at the accumulation node ACC to update voltage V M , preferably once every cycle time T CYC . It does not matter when update signal S UPDATE  triggers the updating during one cycle time T CYC . In one embodiment, for example, the update signal S UPDATE  could be an equivalent to the driving signal V GATE , meaning the updating is performed at the moment when OFF time starts. Voltage V M  is kept as a constant until it is updated by update circuit  96  to become another constant. Level shifter  94  provides limiting voltage V LIMIT  in response to voltage V M . It can be derived that the charge current I CHARGE  stays uncharged if the voltage V M  is not changed. 
         [0023]    Similar to the analysis in US patent application publication US20100321956A1, if the charge current I CHARGE  is a constant and the feedback voltage V ACC  at the sampling moment when update circuit  96  performs sampling is the same as it was at the previous sampling moment, the charge current I CHARGE  is in proportion to the output current I OUT  outputted to the load  24 . To have the charge current I CHARGE  in proportion to the output current I OUT , the value of the feedback voltage V ACC  at the moment when the feedback voltage V ACC  is sampled must be the same, or stable. Update circuit  96 , level shifter  92 , and transconductor  90  together form a loop with a negative loop gain, and this loop eventually could stabilize the value of the feedback voltage V ACC  at the moment when the feedback voltage V ACC  is sampled. If the charge current I CHARGE  is larger than an expected value proportional to the output current I OUT , for example, the feedback voltage V ACC  becomes larger at the next sampling moment, voltage V M  increases when updated, such that the charge current I CHARGE  becomes less in the next cycle time, and vice versa. The charge current I CHARGE  could approach the expected value automatically. With an appropriate negative loop gain, regardless to what the charge current I CHARGE  initially is, voltage V M  could converge and the charge current I CHARGE  eventually be in proportion to the output current I OUT . 
         [0024]      FIG. 5A  demonstrates a relationship between the charge current I CHARGE  and voltage V M  according to embodiments of the invention. Voltage V M  controls the charge current I CHARGE  via level shifter  92  and tranconductor  90 . As shown in  FIG. 5A , the charge current I CHARGE  is never negative. When voltage V M  is below a predetermined voltage V REF-M  corresponding to the predetermined reference voltage V REF  in  FIG. 4 , the charge current I CHARGE  is about a maximum value, which is I MAX  shown in  FIG. 5A . 
         [0025]    When load  24  is modest or light, and output current I OUT  has not reached its maximum rating, voltage V M  should stay at somewhere above the predetermined voltage V REF1  in  FIG. 5A  and the charge current I CHARGE  is in proportion to the output current I OUT . Meanwhile, the power controller  26  (of  FIG. 3 ) performs constant output voltage control, regulating the output voltage V OUT . When load  24  is so heavy, the charge current  CHARGE  is fixed to I MAX , and voltage V M  is below the predetermined voltage V REF-M  in  FIG. 5A . In the meantime, if the output current I OUT  exceeds its maximum rating in proportion to I MAX , both voltage V M  and limiting voltage V LIMIT  decrease cycle by cycle until the limiting voltage V LIMIT  lowers the voltage V CS-PEAK  to make the output current I OUT  equal to its maximum rating. In other words, the power controller  26  could perform constant output current control when voltage V M  is below the predetermined voltage V RE-M . 
         [0026]    The transconductance of transconductor  90  substantially determines the range where voltage V M  would locate for constant output voltage control. The higher transconductance, the tighter range, the wider headroom for the feedback voltage V ACC  to operate properly. The transconductance cannot be too large nevertheless, because increasing transconductance also increases the negative loop gain, where an over-large negative loop gain could result in oscillation and unstable voltage V M . 
         [0027]      FIG. 5B  demonstrates a relationship between the offset current I OFFSET  and charge current I CHARGE  that the load compensation circuit  66  performs according to embodiments of the invention. In one embodiment, by mirroring the charge current I CHARGE  load representative V LC  and the offset current I OFFSET  could be generated. It is preferred in some embodiments that load compensation is not performed during light load or no load. Accordingly, when the charge current I CHARGE  is below a predetermined level I REF  shown in  FIG. 5B , the offset current I  OFFSET  is about 0A according to an embodiment of the invention. Otherwise, the offset current I OFFSET  has a linear relationship with the charge current I CHARGE  as the tilted, straight line  103  in  FIG. 5B  demonstrates. 
         [0028]    Output current estimator  70 , which employs only one internal loop with a negative loop gain, achieves two essential functions: providing the discharge current I CHARGE  substantially in proportion to output current I OUT , and controlling the output current I OUT  below or equal to its maximum rating. 
         [0029]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.