Abstract:
A method and device for controlling memory access in a computer system having at least two execution units, a buffer, in particular a cache being provided for each execution unit, and furthermore a switchover device and a comparison device being provided, the system switching between a performance mode and a compare mode, wherein in the performance mode each execution unit accesses the buffer assigned to it and in the compare mode both execution units access one buffer.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates a method and a device for comparing output data of at least two execution units of a microprocessor. 
       BACKGROUND INFORMATION 
       [0002]    Transient errors, triggered by alpha particles or cosmic radiation, are an increasing problem for integrated circuits. Due to declining structure widths, decreasing voltages and higher clock frequencies, there is an increased probability that a voltage spike, caused by an alpha particle or by cosmic radiation, will falsify a logic value in an integrated circuit. The effect can be a false calculation result. In safety-related systems, such errors must therefore be detected reliably. 
         [0003]    In safety-related systems, such as an ABS control system in a motor vehicle, in which malfunctions of the electronic equipment must be detected with certainty, redundancies for error detection are normally provided particularly in the corresponding control devices of such systems. Thus, for example, in conventional ABS systems, the complete microcontroller is duplicated in each instance, all ABS functions being calculated redundantly and checked for consistency. If a discrepancy appears in the results, the ABS system is switched off. 
         [0004]    Such processor units having at least two integrated execution units are also referred to as dual-core architectures or multi-core architectures. The different execution units (cores) execute the same program segment redundantly and in a clock-synchronized manner; the results of the two execution units are compared, and an error will then be detected in the comparison for consistency. 
         [0005]    Processors are equipped with caches to accelerate access to instructions and data. This is necessary in light of the ever-increasing volume of data, on the one hand, and in light of the increasing complexity of data processing using processors that operate at faster and faster speeds, on the other hand. A cache may be used to avoid to some extent the slow access to a large (main) memory, and the processor consequently does not have to wait for data to be provided. Both caches exclusively for instructions and caches exclusively for data are conventional, but also “unified caches,” in which both data and instructions are stored in the same cache. Systems having multiple levels (hierarchy levels) of caches are also conventional. Such multi-level caches are used to perform an optimal adjustment of the speeds between the processor and the (main) memory by using graduated memory sizes and various addressing strategies of the caches on the different levels. 
         [0006]    Caches are also used to avoid conflicts in accessing the system bus or memory bus in a multiprocessor system. In a multiprocessor system it is common to equip every processor with a cache, or in the case of multi-level caches with correspondingly more caches. 
         [0007]    In one conventional arrangement of caches in a switchable dual-core system, each of the two cores has one permanently assigned cache that the core accesses in the performance mode. In the compare mode, both cores access their respective cache. In addition to the fact that in the compare mode a datum is stored multiple times in the cache (separately for each execution unit), in particular the time required for a change from the performance mode to the compare mode is considerable. 
         [0008]    During this change, the state of the caches must be adapted. Only this ensures that in the compare mode a case in which one of the execution units involved in the comparison has a cache miss (requested datum is not stored in the cache and must be reloaded) and another a cache hit (requested datum is stored in the cache and does not need to be reloaded) does not arise. 
       SUMMARY 
       [0009]    Example embodiments of the present invention, in a multiprocessor system, avoid the disadvantages of conventional methods when using caches in a switchable multiprocessor system. A disadvantage in this context is that in conventional arrangements of caches, the caches must be synchronized in a costly way when a switchover from a performance mode to a compare mode occurs. 
         [0010]    For the switchover option between different modes of a multiprocessor system, such as the performance and the compare mode, it is advantageous if not every execution unit has its own cache, since in particular during the switchover to the compare mode a time-consuming adaptation of the cache would have to be carried out. This may be avoided to a great extent in the provided structures. 
         [0011]    In addition, it is advantageous if the sizes of the different caches for the different modes (compare or performance) can be adjusted to the requirements of the modes. Furthermore, it may be advantageous that in some modes the cache is dispensed with altogether, in particular if the bus access itself is not significantly slower than a cache access. 
         [0012]    A method for controlling memory access in a computer system having at least two execution units is described, a buffer, in particular a cache being provided for each execution unit, and furthermore a switchover device and a comparison device being provided, the system switching between a performance mode and a compare mode, wherein in the performance mode each execution unit accesses the buffer assigned to it and in the compare mode both execution units access one buffer. 
         [0013]    A method is described, wherein the buffer that is accessed by both execution units in the compare mode corresponds to the buffer of one execution unit. 
         [0014]    A method is described, wherein at least one additional buffer, in particular an additional cache, is provided, and in the compare mode both execution units access this additional buffer. 
         [0015]    A method is described, wherein at least one additional buffer is provided and the buffer that is accessed by both execution units in the compare mode is made up of the additional buffer and a buffer of an execution unit. 
         [0016]    A method is described, wherein in the compare mode only read access is permitted to the memory assigned to an execution unit. 
         [0017]    A method is described, wherein in the compare mode the comparison device compares information for consistency and in the event of deviation, an error is detected, and where an error occurs, an access to the buffer is prevented. 
         [0018]    A method is described, wherein in the compare mode the comparison device compares information for consistency and in the event of deviation, an error is detected, and where an error occurs, information in the buffer is invalidated or blocked. 
         [0019]    A method is described, wherein in the compare mode the comparison device compares information for consistency and in the event of deviation an error is detected, and where an error occurs, the computer system is started anew or restarted. 
         [0020]    A method is described, wherein in the compare mode the comparison device compares information for consistency and in the event of deviation an error is detected, and where an error occurs, at least one execution unit is started anew or restarted. 
         [0021]    A device for controlling a memory access in a computer system having at least two execution units is advantageously included, a buffer, in particular a cache being provided for each execution unit, and furthermore a switchover device and a comparison device being provided, the system switching between a performance mode and a compare mode, wherein a device is included that is designed such that in the performance mode each execution unit accesses the buffer assigned to it and in the compare mode both execution units access one buffer. 
         [0022]    A device is advantageously included, wherein the buffer that is accessed by both execution units in the compare mode corresponds to the buffer of one execution unit. 
         [0023]    A device is advantageously included wherein at least one additional buffer, in particular an additional cache, is provided, and in the compare mode both execution units access this additional buffer. 
         [0024]    A device is advantageously included, wherein at least one additional buffer is provided and the buffer that is accessed by both execution units in the compare mode is made up of the additional buffer and a buffer of an execution unit. 
         [0025]    A device is advantageously included, wherein the device is designed such that in the compare mode only read access is permitted to the memory assigned to an execution unit. 
         [0026]    A device is advantageously included, wherein the comparison device is designed such that it compares information for consistency in the compare mode and, in the event of a deviation, detects an error, and when an error occurs, prevents access to the buffer. 
         [0027]    A device is advantageously included, wherein the comparison device is designed such that it compares information for consistency in the compare mode and, in the event of a deviation, detects an error, and when an error occurs, invalidates or blocks information in the buffer. 
         [0028]    A device is advantageously included, wherein the comparison device is located between at least one execution unit and the buffers. 
         [0029]    A device is advantageously included, wherein the buffers are located between at least one execution unit and the comparison device. 
         [0030]    A device is advantageously included, wherein the switchover device and the comparison device are implemented as a switchover and comparator unit. 
         [0031]    Other features and aspects of example embodiments are described below with reference to the appended Figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0032]      FIG. 1  shows a system C 100  having two execution units, only one of which accesses a bus C 10  via a cache in the performance and compare mode. 
           [0033]      FIG. 2  shows a system C 100   c  having two execution units, both of which access bus C 10  via a cache in the performance and compare mode, only one of which, however, is used in the compare mode. 
           [0034]      FIG. 3  shows a system C 100   a  having two execution units, only one of which accesses bus C 10  via a cache in the performance mode. No cache is used in the compare mode. 
           [0035]      FIG. 4  shows a system C 200  having two execution units, both of which access bus C 10  via a cache in the performance and compare mode. In the compare mode, access to the bus occurs via a separate bus interface unit. 
           [0036]      FIG. 5  shows a system C 200   a  having two execution units, both of which access bus C 10  via a cache in the performance and compare mode. In the compare mode, access to the bus occurs via a separate cache and a separate bus interface unit. 
           [0037]      FIG. 6  shows a system C 300  having two execution units, both of which access bus C 10  via a cache in the performance and compare mode, only one of which, however, is used in the compare mode. The cache used in the compare mode uses internally different memories for its task, as a function of the current mode of system C 300 . 
           [0038]      FIG. 7  shows a system C 400  having two execution units, both of which access bus C 10  via a cache in the performance and compare mode, only one of which, however, is used in the compare mode. The cache used in the compare mode uses internally different memories for its task, as a function of the current mode of system C 400 . The relative sizes of these two memories to each other is controlled by a separate unit. 
           [0039]      FIG. 8  shows a system C 500  having two execution units that access bus C 10  via a cache unit. Depending on the mode of system C 500 , the memory accesses of the execution units are served differently. 
       
    
    
     DETAILED DESCRIPTION 
       [0040]    In the following, an execution unit may denote both a processor/core/CPU, as well as an FPU (floating point unit), a DSP (digital signal processor), a co-processor or an ALU (arithmetic logical unit). 
         [0041]    In some multiprocessor systems a cache is used only to avoid conflicts in the system bus and/or memory bus. If only one execution unit existed, then in this case no cache would be necessary since the memory is fast enough to serve the read requests of one execution unit. 
         [0042]      FIG. 1  shows a first variant of a multiprocessor system C 100  having two execution units C 110   a  and C 110   b  that may access a memory via a bus C 10 . A unit C 130  controls, depending on the mode of system C 100 , how bus C 10  is accessed. In the performance mode, a switch C 131  is closed and a switch C 132  open. Thus, execution unit C 110   b  accesses bus C 10  via a cache C 120  and a bus interface C 150 . Execution unit C 110   a  is connected directly to bus C 10  via a connection C 140 . If cache C 120  is dimensioned correctly, then memory accesses of execution unit C 110   b  are served primarily from C 120  so that an access to bus C 10  is only rarely necessary. The memory accesses of the execution unit C 110   a  always result in accesses to the bus C 10 . The bus is accessed via unit C 150  only when a memory access cannot be served via cache C 120 . If execution unit C 110   a  accesses bus C 10  at the same time via C 140 , a bus conflict occurs that must be resolved by the bus protocol. Since cache C 120  is not visible to the software, it is advantageous if unit C 120  listens in on bus C 10  (“bus snooping”) to see whether execution unit C 110   a  is modifying via C 140  a datum in the memory that is also located in cache C 120 . If this is the case, the relevant datum in C 120  must be replaced by the new datum or be marked as invalid. 
         [0043]    In the compare mode, switch C 132  is closed and switch C 131  open. Both execution units jointly access bus C 10  via cache C 120 . A comparator unit C 160  compares the output signals of both execution units and generates an error signal in the event of differences. Optionally, comparator unit C 160  may be connected to bus interface unit C 150  (not shown here) and prevent a write access if the output signals of the two cores differ. In the performance mode, unit C 160  is deactivated. The deactivation of the comparator unit may be achieved in different manners: Either a comparison by unit C 160  is not carried out; no signals for comparison are applied to unit C 160 ; or although the comparison takes place, the result is ignored. 
         [0044]    An example embodiment of the present invention is shown in  FIG. 2  by a system C 100   c . In this example embodiment, the elements from  FIG. 1  work in the same manner. However, in the performance mode, having a closed switch C 131 , execution unit C 100   a  accesses bus C 10  likewise via cache C 140   a  and bus interface C 140 . In the compare mode, both execution units C 110   a  and C 110   b  use cache C 120  via the then closed switch C 132 , while C 110   a  uses C 140   a  only in the performance mode. Both caches C 120  and C 140   a  may have different sizes and be accordingly optimized for the tasks adjusted in the different modes. 
         [0045]      FIG. 3  shows a further example embodiment of the present invention. In this instance, C 100   a  designates a multiprocessor system. Here, the switch C 133  is open in the performance mode and the switch C 134  is closed, and an execution unit C 110   b  accesses the bus C 10  via a cache C 120  and the bus interface unit C 150 . The other execution unit C 110   a  accesses bus C 10  directly via unit C 140 . In the compare mode, by contrast, switch C 133  is closed and C 134  is open; both execution units access bus C 10  directly via C 140 , and cache C 120  is not used. A comparator unit C 160  compares the output signals of both execution units and generates an error signal in the event of differences. Optionally, here too comparator unit C 160  may be connected to bus interface units C 140  (not shown here) and prevent a write access if the output signals of the two execution units differ. In the performance mode, unit C 160  is deactivated. The deactivation may be implemented in different ways, which have already been described. 
         [0046]    In an additional variant of the multiprocessor system, caches are also used only for avoiding conflicts in access to the memory bus.  FIG. 4  shows a multiprocessor system C 200  having two execution units C 210   a  and C 210   b  that, in different manners, may access a memory via bus C 10 . A unit C 230  controls, depending on the mode of system C 200 , how bus C 10  is accessed. In the performance mode, switches C 231  and C 234  are closed and switches C 232  and C 233  are open. Thus, execution unit C 210   a  accesses bus C 10  via a cache  240   a  using a bus interface C 250   a , and execution unit C 210   b  via a cache C 240   b  using a bus interface C 250   b . An access to bus C 10  is required only if the memory accesses cannot be served by the respective caches of the execution units. If other execution units access bus C 10  at the same time, a bus conflict occurs that must be resolved by the bus protocol. Since caches C 240   a  and C 240   b  are not visible to the software, it is advantageous if a datum that is written by one execution unit C 210   a , C 210   b  to the respective cache C 240   a , C 240   b  is likewise written immediately to the memory via the respective bus interface C 250   a , C 250   b  to bus C 10  (“write-through” strategy). 
         [0047]    Furthermore, it is advantageous if units C 240   a  and C 240   b  listen in on bus C 10  (“bus snooping”) (via C 250   a  and C 250   b  respectively) to see whether execution unit C 210   a  via C 250   a  or C 210   b  via C 250   b  modifies a datum in the memory that is also located in the cache of the other. If this is the case, the relevant datum in the affected cache must be replaced by the new datum or be marked as invalid. 
         [0048]    In the compare mode, switches C 232  and C 233  are closed and switches C 231  and C 234  are open. Both execution units jointly access bus C 10  via a cache C 260 . The caches (C 240   a , C 240   b ) are not used. A comparator unit C 220  compares the output signals of both execution units and generates an error signal in the event of differences. Optionally, comparator unit C 220  may be connected to a bus interface unit C 260  (not shown here) and prevent a write access if the output signals of the two execution units differ. In the performance mode, unit C 220  is deactivated. The deactivation may be implemented in different manners, which have already been described. 
         [0049]      FIG. 5  shows an additional example embodiment C 200   a  of the multiprocessor system, in which example embodiment in contrast to the example embodiment C 200 , shown in  FIG. 4 , an additional cache  270  has been inserted for the compare mode. The components from  FIG. 4  work in the same manner, as described above. In this system too, it is advantageous if a “write-through” strategy is used for all caches, and the consistency of the content of all caches is maintained through “bus snooping.” 
         [0050]    The previously described variants according to  FIGS. 4 and 5  may be extended to more than two execution units. In this case, one cache unit and one bus interface unit exist for each execution unit and are used in the performance mode. In the compare mode, all execution units access bus C 10  via bus interface unit C 260  (optionally using a cache C 270 ). 
         [0051]    An additional example embodiment of the present invention is shown in  FIG. 6 . Here too, processor unit C 300  is made up of at least two execution units C 310   a  and C 310   b  which each access a memory via a cache C 340   a ,  340   b  and a bus interface C 350   a , C 350   b  via bus C 10 . In the performance mode, a switch C 332  is open and a switch C 331  is closed in unit C 330 . In this configuration, execution unit C 310   a  accesses bus C 10  via cache C 340   a  and bus interface C 350   a , and execution unit C 310   b  via cache C 340   b  and bus interface C 350   b.    
         [0052]    In the compare mode, switch C 330  is closed and switch C 332  open in switchover unit C 331 . Now both execution units access bus C 10  via cache C 340   a  and bus interface C 350   a . Unit C 340   a  itself is in turn made up of two separate cache memories or cache areas C 341 , C 342  that are used for the caching. In the performance mode, only memory/area C 341  is used, while in compare mode memory/area C 342  is used for caching in addition to memory/area C 341 . In the compare mode, a comparator unit C 320  compares the output signals of both execution units and generates an error signal in the event of differences. Optionally, here too comparator unit C 320  may be connected to bus interface units C 350   a  (not shown here) and prevent a write access if the output signals of the two cores differ in the compare mode. In the performance mode, compare unit C 320  is deactivated, as was already described for comparator unit C 160 , shown in  FIG. 1 . 
         [0053]    In an additional example embodiment, unit C 340   a  may be constructed such that in the compare mode memory C 341  and C 342  are in fact used in conjunction as well, but only contents from memory C 342  may be removed and replaced by other contents in the compare mode. 
         [0054]    All example embodiments in the refinement of  FIG. 6  may be extended to more than two execution units. In this case, one cache unit and one bus interface unit exist for each execution unit and are used in the performance mode. In the compare mode, all execution units access bus C 10  via cache C 340   a  and bus interface unit C 350   a.    
         [0055]    An additional possible example embodiment of the present invention is shown in  FIG. 7 . Here too, the processor unit C 400  is made up of at least two execution units C 410   a  and C 410   b , which each access a memory via a cache (C 440   a ,  440   b ) and a bus interface (C 450   a , C 450   b ) to the bus  010 . 
         [0056]    In the performance mode, a switch C 432  is open and a switch C 431  is closed in unit C 430 . In this configuration, execution unit C 410   a  accesses bus C 10  via cache C 440   a  and bus interface C 450   a , and execution unit C 410   b  via cache C 440   b  and bus interface C 450   b.    
         [0057]    In the compare mode, switch C 432  is closed and switch C 431  open in switchover unit C 430 . Now both execution units access bus C 10  via cache C 440   a  and bus interface C 450   a . The unit C 440   a  itself is in turn made up of two separate cache memories or areas C 441 , C 442  that are used for the caching. In the performance mode, only memory/area C 441  is used, while in the compare mode memory/area C 442  is used for caching. The sum of the sizes of both memories/areas C 441 +C 442  is constant, but the ratio between the sizes of C 441  and C 442  is controlled by a unit C 443 . Through this unit C 443 , it is possible to modify the ratio during operation. 
         [0058]    In the compare mode, a comparator unit C 420  compares the output signals of both execution units and generates an error signal in the event of differences. Optionally, here too the comparator unit C 420  can be connected to the bus interface units C 450   a  (not shown here) and prevent a write access if the output signals of the two execution units differ in the compare mode. In the performance mode, unit C 420  is deactivated, as was described for comparator unit C 160  from  FIG. 1 . 
         [0059]    Unit C 440   a  may now be executed as follows while maintaining the function of unit C 443 :
   1. In the compare mode, both memories C 441  and C 442  are used for the cache.   2. In the compare mode, both memories C 441  and C 442  are used for the cache; however, only contents for memory C 442  being able to be removed in the compare mode and replaced by other contents.   
 
         [0062]    All example embodiments in the refinement of  FIG. 7  may be extended to more than two execution units. In this case, one cache unit and one bus interface unit exist for each execution unit and are used in the performance mode. In the compare mode, all execution units access bus C 10  via cache C 440   a  and bus interface C 450   a.    
         [0063]      FIG. 8  depicts a further example embodiment. At least two execution units C 510   a  and C 510   b  exist in a processor system C 500 . Both execution units are connected to a cache unit C 530 . This unit C 530  has one bus interface unit C 550   a , C 550   b  for each execution unit, via which an access to a memory via bus C 10  is possible. Cache unit C 530  has two cache memories (here C 531  and C 533  for C 510   a , and C 534  and C 536  for C 510   b ) for each connected execution unit. The sum of the sizes of these memory pairs is constant; during operation, however, the ratio may be changed via one unit in each instance (C 532  for C 531 , C 533  and C 535  for C 534 , C 536 ). 
         [0064]    In the performance mode, memory accesses by the execution units are always cached by the memory pair that is assigned to the execution unit. In the process, only one of the two cache memories is used (here C 531  for C 510   a , and C 534  for C 510   b ). If memory accesses by the execution unit cannot be served from the cache memory, the necessary bus accesses to C 10  are always done via the bus interface assigned to the execution unit (here C 550   a  for C 510   a , and C 550   b  for C 510   b ). In the performance mode, simultaneous accesses by execution units may also be served simultaneously via unit C 530 , unless a bus conflict occurs due to the simultaneous access to C 10 . 
         [0065]    In the compare mode, the memory accesses by the execution units are served by the cache memories that are not used in the performance mode (here C 533  and  536 ). Any bus interface may be used for a bus access. In the compare mode, a comparator unit C 520  compares the output signals of all execution units and generates an error signal in the event of differences. Optionally, here too comparator unit C 520  may be connected to bus interface units C 550   a , C 550   b  (not shown here) and prevent a write access if the output signals of the two cores differ in the compare mode. In the performance mode, unit C 520  is deactivated. It may be deactivated accordingly as in the comparator unit C 160  from  FIG. 1 . 
         [0066]    In an additional example embodiment, unit C 530  may be structured such that in the compare mode all cache memories (here C 531 , C 533 , C 534 , C 536 ) are used, but only the cache memory contents that are not used in the performance mode are discarded and replaced. 
         [0067]    For all implementations shown here by way of example, the switchover and comparator unit is always situated between the execution units and their associated caches. If a cache is used in the compare mode, this cache must be safeguarded by ECC or parity so that errors are detected in this instance also. Additionally, it is advantageous if a “write-through” strategy is used for the caches, and the consistency of the content of the caches is maintained through “bus snooping.”