Abstract:
A surface mount interconnection system provides a method and apparatus for mounting an auxiliary printed circuit board assembly directly to a main printed circuit board assembly without the use of leaded surface mount devices. A linear array of spaced-apart solder pads is arranged on an exposed surface of the substrate of both assemblies, with at least one of solder pad arrays being located adjacent an edge of its associated substrate. A selected plurality of aligned cooperating pairs of solder pads are electrically and mechanically interconnected by a solder ball reflowed to form a joint there between. The solder balls comprise a high melting temperature inner core and a low melting temperature outer solder core.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to apparatus for providing electrical connections to circuit boards and more particularly to providing electrical and mechanical interconnections between circuit boards. 
       BACKGROUND OF THE INVENTION 
       [0002]    The interconnection of circuit boards can pose problems with regards to cost and reliability as well as ease of assembly. With typical leaded parts header pins can be employed to eliminate connectors for reduced part count and reliability improvements. 
         [0003]    Manufacturing processes are progressing to using more surface mount components that are driving assembly to eliminate leaded parts in favor of surface mount technology. Product designs are struggling to change over to surface mount especially for connection systems that can be expensive and not have many options available. 
         [0004]    It is known to form a ball grid array package comprising an electronic assembly mounted to a substrate by solder bump interconnections. For example, an assembly with an encapsulated integrated circuit die may be mounted onto a mother board by solder bump interconnections. The substrate and assembly are parallel and spaced apart by a gap, with the solder bump interconnections disposed within the gap. The solder bump interconnections electrically and physically attach the substrate to the assembly via bond pads on the substrate and assembly. It has been proposed to form the interconnections using solder balls that include a polymeric core with a solder layer. The balls are placed on the pads, the substrate and assembly are aligned with the balls in between and then heated to reflow the solder. The core serves as spacer to assure minimal distance between the substrate and assembly. 
         [0005]    During operation, the solder bump interconnections may crack due to stresses induced by thermal expansion mismatch between the assembly and the substrate, severing the electrical connection between the electronic assembly and the substrate and causing failure of the package. The distance between the surface of the substrate and the surface of the electronic assembly is referred to as the standoff height. Increasing the standoff height reduces the stresses and creates a more reliable connection. Further, it is known to locate electrical components on the substrate below the electronic assembly. The components generate heat. Increasing the standoff height between the substrate and the assembly enhances the flow of air or other cooling fluid within the gap and improves cooling of the electrical components underlying the assembly. 
       SUMMARY OF THE INVENTION 
       [0006]    A surface mount interconnection system provides a method and apparatus for mounting an auxiliary printed circuit board assembly directly to a main printed circuit board assembly without the use of leaded surface mount devices. A linear array of spaced-apart solder pads is arranged on an exposed surface of the substrate of both assemblies, with at least one of solder pad arrays being located adjacent an edge of its associated substrate. A selected plurality of aligned cooperating pairs of solder pads are electrically and mechanically interconnected by a solder ball reflowed to form a joint there between. 
         [0007]    According to one aspect of the invention, at least some of the solder balls he comprise a high melting temperature inner core and a low melting temperature outer solder core. This arrangement provides enhanced structural support properties to the mechanical joint between the main printed circuit board assembly and the auxiliary printed circuit board assembly. 
         [0008]    To replace the header and/or two piece connection systems, there exist solder balls that can enable a vertical to horizontal circuit board interconnect. Solder balls that perform the electrical interconnection are picked and placed. They are typically about 1.6 mm in diameter. The vertical board will have solder balls reflowed at contact areas adjacent to an edge at the interface area to enable soldering to the horizontal circuit board. With solder paste applied to the interface contact points on the horizontal board the solder operation will reflow the solder and complete the desired circuit connection between the circuit boards. A small edge card style fixture can help position the vertical board and two error proofing tabs just outside the interface area can help locate the circuit boards and can help keep the circuit boards in position relative to one another until the soldering operation has been completed. 
         [0009]    In accordance with this invention, a method is provided for forming a Ball Grid Array package having increased standoff height. A substrate is provided which includes a plurality of first solder bond pads. A solder ball is disposed onto each first solder bond pad. The solder ball is formed of a core, made of a material that remains solid at solder reflow temperature, and is encapsulated within a reflowable solder layer. An electronic assembly is arranged overlying the substrate such that second bond pads on the assembly are in contact with solder balls, thereby forming an arrangement wherein the substrate and the assembly are in a parallel, spaced relationship with solder balls in between the first and second bond pads and is characterized by a first standoff height between the substrate and the assembly. The arrangement is heated to a temperature for a time effective to melt and reflow the solder. The molten solder wets the first and second bond pads and coalesces between the solid core and at least one of the bond pads to increase the standoff height. Upon cooling and solidification of the solder, the ball grid array package is characterized by a second standoff height greater than the first standoff height of the pre-reflow arrangement. 
         [0010]    These and other features and advantages of this invention will become apparent upon reading the following specification, which, along with the drawings, describes preferred and alternative embodiments of the invention in detail. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present invention will now be described, by way of example, with reference to the accompanying drawings, in which: 
           [0012]      FIG. 1 , is an exploded, perspective view of a first embodiment of the present invention wherein a horizontally disposed mother circuit board is illustrated juxtaposed for assembly with a vertically disposed daughter circuit board; 
           [0013]      FIG. 2 , is a broken detail view of the embodiment of  FIG. 1 , on an enlarged scale, wherein the mother and daughter circuit boards are pre-positioned in their respective assembled orientations prior to electrical and mechanical joining thereof; 
           [0014]      FIG. 3 , is a broken, detail view similar to  FIG. 2 , depicting post-interconnection of the mother and daughter circuit boards by solder reflow process, and the subsequent application of rigid, electrically insulative underfill material; 
           [0015]      FIG. 4 , is an exploded, perspective view of a second embodiment of the present invention wherein a mother circuit board is illustrated juxtaposed for assembly with an adjacent flexible daughter circuit board; 
           [0016]      FIG. 5 , is a perspective view of a third embodiment of the present invention wherein a daughter circuit board has a number of solder balls preassembled therewith by a “pick and place” process wherein the solder balls are adhered by an adhesive or solder reflowing process; 
           [0017]      FIGS. 6A , B and C, are perspective views of assembly process steps of the third embodiment wherein a solder pallet is provided ( FIG. 6A ), the solder pallet is prepositioned atop the mother circuit board to support the daughter circuit board normally thereto ( FIG. 6B ), and the solder pallet is removed from the completed mother-daughter circuit board assembly ( FIG. 6C ); and 
           [0018]      FIG. 7 , is an enlarged detail of a portion of  FIG. 6C  illustrating the solder joints affecting mechanical and electrical interconnection of the mother and daughter circuit boards. 
       
    
    
       [0019]    Although the drawings represent embodiments of the present invention, the drawings are not necessarily to scale and certain features may be exaggerated in order to illustrate and explain the present invention. The exemplification set forth herein illustrates an embodiment of the invention, in one form, and such exemplifications are not to be construed as limiting the scope of the invention in any manner. 
       DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0020]    Referring to  FIG. 1 , an electronic package  10  embodying the present invention is illustrated. The electronic package  10  comprises a main circuit board assembly  12  and an auxiliary circuit board assembly  14  adapted to be selectively electrically and mechanically joined. The main circuit board assembly  12  has a generally planer substrate  16 , such as a rigid printed circuit board (PCB), forming an exposed (upper) surface  18 . A linear array of spaced-apart solder pads  20   a - 20   f  is carried on the exposed surface  18  of substrate  16  along an axis designated X-X. Each solder pad  20  is electrically interconnected with various electrical components  22  by one or more conductive traces  24 . The solder pads  20   a - 20   f,  electrical components  22  and conductive traces  24  form a main or first sub-circuit assembly  26 . A pair of spaced-apart locating features  28  and  30 , such as shaped recesses are formed in the substrate  16 , opening into the exposed surface  18  near the array of solder pads  20   a - 20   f.  Each of the solder pads  20   a - 20   f  are preferably similarly configured (shaped and dimensioned), and adjacent solder pads  20   a - 20   f  are equally spaced from one another. 
         [0021]    The auxiliary circuit board assembly  14  has a generally planer substrate  32 , such as a rigid printed circuit board (PCB), forming an exposed (rightwardly facing) surface  34 . A linear array of spaced-apart solder pads  36   a - 36   f  is carried on the exposed surface  34  of substrate  32  along a designated axis Y-Y. Each solder pad  36  is electrically interconnected with various electrical components  38  by one or more conductive traces  40 . The solder pads  36   a - 36   f,  electrical components  38  and conductive traces  40  form an auxiliary or second sub-circuit assembly  42 . A pair of spaced-apart locating tabs  44  and  46 , such as shaped extensions are formed in the substrate  32 , extending (downwardly) from a bottom edge surface  48  normally adjacent the exposed surface  34  in slip fit engagement within locating features  28  and  30 , respectively. The array of solder pads  36   a - 36   f  are located at or very near the line of intersection of the exposed surface  34  and the bottom edge surface  48 . Each of the solder pads  36   a - 36   f  are preferably similarly configured (shaped and dimensioned), and adjacent solder pads  36   a - 36   f  are equally spaced from one another. 
         [0022]    Referring now to  FIGS. 2 and 3 , there is shown an arrangement of main circuit board assembly  12  and auxiliary circuit board assembly  14  combined for forming package  10 . Solder resist covers the exposed surfaces  18  and  34  of substrates  16  and  32 , respectively, carrier surface  26 , with the exception of the solder pads  20   a - 20   f  and  36   a - 36   f,  respectively. 
         [0023]    Referring to  FIGS. 1 and 2 , initial assembly steps for surface mounting the auxiliary circuit board  14  on the main circuit board  12  are illustrated. Preferably, the auxiliary circuit board assembly  14  and the main circuit board assembly  12  are separately preassembled. Thereafter, the auxiliary circuit board assembly  14  is prepositioned normally on the main circuit board assembly  12 , with the bottom edge surface  48  of the auxiliary circuit board substrate  32  abutting the exposed upper surface  18  of the main circuit board substrate  16 . The integral locating tabs  44  and  46  of the auxiliary circuit board assembly  14  are precisely slip-fit within the mating locating features  28  and  30 , respectively, formed in the substrate  16  of the main circuit board assembly  12 . 
         [0024]    Axis X-X defining the linear array of spaced-apart solder pads  20   a - 20   f  is disposed parallel to axis Y-Y defining the linear array of spaced-apart solder pads  36   a - 36   f.  Insodoing, the solder pads are aligned in cooperating pairs. For example, solder pads  36   a  and  20   a  are aligned as a cooperating pair illustrated in  FIG. 2 . Similarly, solder pads  36   b  and  20   b,    36   c  and  20   c,    36   d  and  20   d,    36   e  and  20   e,  and  36   f  and  20   f,  respectively, form cooperating pairs. 
         [0025]    Solder balls  50  are employed to selectively electrically interconnect cooperating pairs of solder pads  20  and  36  and to mechanically affix the auxiliary circuit board assembly  14  to the main circuit board assembly  12 . By selectively electrically interconnecting cooperating pairs of solder pads  20  and  36 , the sub-circuit assemblies  26  and  42  are electrically placed in-circuit, creating a composite circuit. Functionality of the composite circuit can be varied by selectively employing solder balls  50  at some or all of the cooperating pairs of solder pads  20  and  36 . For example, a first functionality can be achieved by placing a solder ball  50  at each cooperating pair of solder pads  20  and  36 . A second functionality can be achieved by placing a solder ball  50  on solder pads  20   a,    20   c,    20   d  and  20   f  only (as an example), and a third functionality can be achieved by placing a solder ball  50  on solder pads  20   a,    20   b,    20   e  and  20   f  only (as an example). Of course, employing solder balls  50  at fewer than all of the possible solder pad pairs will result in slightly reduced structural integrity. 
         [0026]    Each solder ball  50  can be formed of a homogenous composition. Preferably, each solder ball  50  comprises a core  52 , a solder layer  54  encapsulating the core  52 , and a solder wettable layer  56  disposed between core  52  and solder layer  54 . Solder layer  54  is coated on its exterior layer by a flux compound  58 . In a preferred embodiment, solder layer  54  is formed of a near eutectic alloy containing 63% tin and the balance lead. In the described embodiment, core  52  is formed of a polymeric material, preferably a di-vinylbenzene co-polymer. Alternately, the core may be formed of any suitable material that remains solid at solder reflow temperatures. Layer  56  is formed of a metal that is wet by molten solder. Suitable metals include copper or copper alloys, or nickel or nickel alloys. Suitable solder balls are commercially available from Indium Corporation under the trade designation Indium Sphereot. 
         [0027]    Referring to  FIG. 3 , after the substrate  14 , electronic assembly  16 , and solder balls  40  are arranged as depicted in  FIGS. 1 and 2 , the arrangement  10  is heated to a temperature of about 210 degrees C. for a time of about 30 seconds, effective to reflow the solder. During solder reflow the solder liquefies and wets the first solder or bond pad  20  and the second solder or bond pad  36  of each respective pair, at openings in solder resist layers. The solder resist layer is patterned to create an opening that exposes the solder pads  20  and  36 , allowing the top and side surfaces of the solder pads  20  and  36  to be wet with molten solder. While the solder layer  54  is in liquid form, the solid core  52  is drawn by surface tension from the position illustrated in  FIG. 2  to the position illustrated in  FIG. 3 , wherein the core  52  is displaced into tangential proximity to the exposed surfaces  18  and  34  of both substrates  16  and  32 , respectively, as illustrated by an arrow  67 . Upon cooling, the solder solidifies and bonds to the pairs of solder pads  20  and  36  to form the solder joint interconnections. When fixed in the position illustrated in  FIG. 3 , the core  52  serves as a web, mechanically reinforcing the substrates  16  and  32  in their respective positions illustrated in  FIG. 3 , as well as promoting electrical conductivity between respective solder pads  20  and  36 . The reformed solder  66  from the original solder layer  54  of  FIG. 2  also serves to structurally support the embodiment of  FIG. 3  and fully immerses the core  52 . 
         [0028]    After cooling of the solder joints, non-electrically conductive over-flow material  60  can provide a hermetic seal over the solder joints, as well as provide supplemental structural mechanical support of the substrates  16  and  32  in their respective positions illustrated in  FIG. 3 . 
         [0029]    Referring to  FIG. 2 , the solder pads  20   a - 20   f  have a central concave recess or locating pocket  62  formed therein. The pockets  60  are each dimensioned and located to facilitate precise manual placement of a solder ball  50  prior to the reflow process step. An adhesive layer  64  can be formed in the locating pocket  62  to temporarily retain a solder ball  50  therein. Alternatively, each solder ball  50  can have an outer adhesive coating to provide the same function. 
         [0030]    Referring to  FIG. 4 , an electronic package  68  embodying an alternative embodiment of the invention is illustrated. The electronic package  68  comprises a main circuit board assembly  70  and an auxiliary circuit board assembly  72  adapted to be selectively electrically and mechanically joined by direct surface mount. The main circuit board assembly  70  has a generally planer substrate  74 , such as a rigid printed circuit board (PCB), forming an exposed (upper) surface  76 . A linear array of spaced-apart solder pads  78  (only one illustrated) is carried on the exposed surface  76  of substrate  74  along an axis. Each solder pad  78  is electrically interconnected with various electrical components by one or more conductive traces. The solder pads  78 , electrical components and conductive traces form a main or first sub-circuit assembly  80 . A locating feature  82 , such as shaped recesses is formed in the substrate  74 , opening into the exposed surface  76  near the array of solder pads  78 . Each of the solder pads  78  are preferably similarly configured (shaped and dimensioned), and adjacent solder pads  78  are equally spaced from one another. 
         [0031]    The auxiliary circuit board assembly  72  has a generally planer substrate  84 , such as a flexible printed circuit board (PCB), forming an exposed (downwardly facing) surface  86 . A linear array of spaced-apart solder pads  88  is carried on the exposed surface  86  of substrate  84  along a designated axis. Each solder pad  88  is electrically interconnected with various electrical components by one or more conductive traces  90 . The solder pads  88 , electrical components and conductive traces  90  form an auxiliary or second sub-circuit assembly  92 . A pair of spaced-apart locating tabs  94 , affixed to substrate  84  by a rivet  96 , extend (downwardly) from a bottom edge surface  98  parallel to the exposed surface  76  of the substrate  74 , in slip fit engagement within locating features  82 . Each of the solder pads  88  are preferably similarly configured (shaped and dimensioned), and adjacent solder pads  88  are equally spaced from one another. 
         [0032]    Solder pads  78  have a recess  100  formed therein for locating a solder ball  102 , which is retained by an adhesive layer  104 . Similarly, solder pads  88  have a recess  106  formed therein for registering with a solder ball  102 . 
         [0033]    The electronic package  68  is assembled by manually selectively placing solder balls  102  in some or all of the recesses  100  of the main sub-circuit assembly solder pads  78 . Thereafter, the locating tabs  94  are registered with their corresponding locating features  82 , and the solder ball  102  is heated until it reflows, interconnecting the adjoining pairs of solder pads  78  and  88  in a spaced apart relationship. Upon re-solidification of the solder, the solder pads  78  and  88  having a solder ball  102  there between are mechanically and electrically joined. The pairs of solder pads  78  and  88  lacking a solder ball remain spaced apart by a spacing step  108  formed in the locating tab  94  and are thus, mechanically and electrically isolated. 
         [0034]    Referring to  FIGS. 5 ,  6   a - 6   c  and  7 , the process steps of forming an electronic package embodying a third alternative embodiment of the invention are illustrated. 
         [0035]    Referring to  FIG. 5 , a main circuit board assembly  110  has a generally planer substrate  112 , such as a rigid printed circuit board (PCB), forming an exposed (upper) surface  114 . A linear array of spaced-apart solder pads  116  is carried on the exposed surface  114  of substrate  112  along an axis designated Z-Z. Each solder pad  116  is electrically interconnected with various electrical components  118  by one or more conductive traces  120 . The solder pads  116 , electrical components  118  and conductive traces  120  form a main or first sub-circuit assembly  122 . A pair of spaced-apart locating features  124  and  126 , such as shaped edge abutments are formed in the substrate  112 , located near the array of solder pads  116 . Each of the solder pads  116  are preferably similarly configured (shaped and dimensioned), and adjacent solder pads  116  are equally spaced from one another. A solder ball  128  is manually adhesively prepositioned on each solder pad  116 . 
         [0036]    Referring to  FIG. 6   a , an assembly fixture  130  is provided for pre-positioning an auxiliary circuit board assembly on the main circuit board assembly  110  prior to soldering. The fixture  130  consists of a generally rectangular frame  132  including end wall portions  134  and side wall portions  136  configured to form an opening  138  dimensioned to precisely receive the main circuit board assembly  110  in a slip-fit. Inwardly directed locating tabs  140  are integrally formed on the end and side wall portions  134  and  136 , respectively, of the frame  132  to form vertically position the main circuit board assembly  110  within the frame  132 . A locating collar  142  is supported above one of the frame side wall portions  136  by two integrally formed stations  144 . The locating collar  142  forms a vertically opening through slot  146 . 
         [0037]    Referring to  FIG. 6   b , the main circuit board assembly  110  of  FIG. 5  is illustrated installed within the assembly fixture  130  of  FIG. 6   a . Furthermore,  FIG. 6   b  illustrates an auxiliary circuit board assembly  148  pre=positioned with respect to the main circuit board assembly  110  and supported in a vertical orientation by the locating collar  142 . 
         [0038]    The auxiliary circuit board assembly  148  has a generally planer substrate  150 , such as a rigid printed circuit board (PCB), forming an exposed surface  152 . A linear array of spaced-apart solder pads  154  is carried on the exposed surface  152  of substrate  150  along a designated axis. Each solder pad  154  is electrically interconnected with various electrical components  156  by one or more conductive traces  158 . The solder pads  154 , electrical components  156  and conductive traces  158  form an auxiliary or second sub-circuit assembly  162 . The array of solder pads  154  are located at or very near the axis Z-Z of the solder pads  116  of the main circuit board assembly. Each of the solder pads  154  are preferably similarly configured (shaped and dimensioned), and adjacent solder pads  154  are equally spaced from one another. 
         [0039]    As illustrated in  FIGS. 6   b  and  7 , the solder pads  154  of the auxiliary circuit board assembly  148  are in precise alignment with the solder pads  116  of the main circuit board assembly  110 . With the respective aligned pairs of solder pads  116  and  154  registered as illustrated in  FIG. 6   b , the solder balls  128  are heated until they reflow, converting solder balls  128  into joints  162 , as best illustrated in  FIGS. 6   c  and  7 . After the reflowed solder has cooled and congealed into joint  162 , the assembly fixture  130  is removed. Thereafter, the auxiliary circuit board assembly  148  is mechanically supported on the main circuit board assembly  110  exclusively by the solder joints  162 . As described in detail herein above, the solder joints  162  also serve to selectively interconnect the first and second sub circuit assemblies  122  and  160 . 
         [0040]    The following documents are deemed to provide a fuller disclosure of the inventions described herein and the manner of making and using same. Accordingly, each of the below-listed documents are hereby incorporated in the specification hereof by reference: 
         [0041]    U.S. Pat. No. 5,607,099 to S. Yeh et al. entitled “Solder Bump Transfer Device for Flip Chip Integrated Circuit Devices”. 
         [0042]    U.S. Pat. No. 5,896,271 to Eric D. Jensen et al. entitled “Integrated Circuit with a Chip On Dot and a Heat Sink”. 
         [0043]    U.S. Pat. No. 6,608,379 B2 to Youg K. Yeo et al. entitled “Enhanced Chip Scale Package for Flip Chips”. 
         [0044]    U.S. Pat. No. 6,710,438 B2 to Yong K. Yeo et al. entitled “Enhanced Chip Scale Package for Wire Bond Dies”. 
         [0045]    U.S. Pat. No. 7,118,940 B1 to Bruce A. Myers et al. entitled “Method of Fabricating an Electronic Package Having Underfill Standoff”. 
         [0046]    U.S. Pat. No. 7,733,659 B2 to Chris R. Snider et al. entitled “Lightweight Audio System for Automotive Applications and Method. 
         [0047]    U.S. Patent Application No.: 2007/0029669 A1 to Frank Stepniak et al. entitled “Integrated Circuit with Low-Stress Under-Bump Metallurgy”. 
         [0048]    U.S. Patent Application No.: 2007/0235217 A1 to Derek B. Workman entitled “Devices with Microjetted Polymer Standoffs”. 
         [0049]    U.S. Patent Application No.: 2009/0080169 A1 to Mark E. Webster et al. entitled “Method for Forming BGA Package with Increased Standoff Height”. 
         [0050]    It is to be understood that the invention has been described with reference to specific embodiments and variations to provide the features and advantages previously described and that the embodiments are susceptible of modification as will be apparent to those skilled in the art. 
         [0051]    Furthermore, it is contemplated that many alternative, common inexpensive materials can be employed to construct the basis constituent components. Accordingly, the forgoing is not to be construed in a limiting sense. 
         [0052]    The invention has been described in an illustrative manner, and it is to be understood that the terminology, which has been used is intended to be in the nature of words of description rather than of limitation. 
         [0053]    Obviously, many modifications and variations of the present invention are possible in light of the above teachings. For example, . . . It is, therefore, to be understood that within the scope of the appended claims, wherein reference numerals are merely for illustrative purposes and convenience and are not in any way limiting, the invention, which is defined by the following claims as interpreted according to the principles of patent law, including the Doctrine of Equivalents, may be practiced otherwise than is specifically described.