Abstract:
A reference voltage circuit having a high power supply rejection ratio, and can operate at low voltage is provided. The reference voltage circuit includes a bias circuit constructed such that a depletion type transistor ( 3 ) is connected in series to a power supply voltage supply terminal of a load circuit, an enhancement type MOS transistor ( 4 ) for detecting current through the load circuit to operate as a current source is connected to the load circuit, a depletion type MOS transistor ( 5 ) is connected in series to the transistor ( 4 ), and a gate terminal of the transistor ( 5 ) is connected to a source terminal of the transistor ( 5 ), in which the gate terminal of the depletion type transistor ( 3 ) is connected to the source terminal of the depletion type transistor ( 5 ).

Description:
[0001]     This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. JP2006-085728 filed Mar. 27, 2006, the entire content of which is hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor device, and more particularly, to a cascode circuit used for the purpose of decreasing output voltage fluctuations in response to power supply voltage fluctuations.  
         [0004]     2. Description of the Related Art  
         [0005]     In order to improve the power supply rejection ratio of an analog circuit, a method of adding a cascode circuit is conventionally widely used. Take as an example a reference voltage circuit, which is used to obtain stable output voltage in response to power supply voltage fluctuations and temperature changes. Conventionally, a circuit as illustrated in  FIG. 2  of Semiconductor Device for Reference Voltage (Japanese Examined Patent Publication No. Hei 7-74976) is used.  FIG. 2  illustrates an equivalent circuit. In the conventional reference voltage circuit, a source terminal of a depletion type MOS transistor  1  and a drain terminal of an enhancement type MOS transistor  2  are connected in series between a power supply voltage supply terminal  101  and a ground potential  100 , and respective nodes and their gate terminals are commonly connected. The node is used as a reference voltage output terminal  102  (hereinafter referred to as ED type reference voltage circuit). Insofar as the respective transistors operate in a saturation state, even if the voltage of the power supply voltage supply terminal  101  fluctuates, the reference voltage output terminal  102  is not affected by the voltage fluctuations.  
         [0006]     However, actually, the voltage of the reference voltage output terminal  102  fluctuates under the influence of channel length modulation effect of the depletion type MOS transistor  1 . Accordingly, it is difficult to construct a reference voltage circuit having a high power supply rejection ratio. In order to suppress the channel length modulation effect and to suppress the fluctuations of the power supply voltage within a short period from affecting the reference voltage, a circuit illustrated in  FIG. 3  is also used.  
         [0007]     In the reference voltage circuit as illustrated in  FIG. 3 , a depletion type MOS transistor  3  is provided between the reference voltage circuit and a power supply voltage supply terminal  101 . In the depletion type MOS transistor  3 A, a backgate terminal is used as a ground potential, and a bias voltages supply means  201  is connected to the gate terminal.  
         [0008]     The depletion type MOS transistor  3  operates as a so-called cascode circuit, and operates so that voltage supplied to an ED type reference voltage circuit  200  becomes constant against the voltage fluctuations of the power supply voltage supply terminal  101 .  FIG. 1  of Reference Voltage Circuit and Electronic Device (Japanese Patent Application Laid-open No. 2003-295957) illustrates an actual structure of the bias voltage supply means  201 .  FIG. 4  illustrates a circuit equivalent to  FIG. 1  of Japanese Patent Application Laid-open No. 2003-295957.  
         [0009]     The circuit is a reference voltage circuit having two channel reference voltage outputs. Paying attention to the ED type reference voltage circuit  200 , it can be thought that the depletion type MOS transistor  3 , which operates as the cascode circuit is connected to the ED type reference voltage circuit  200 , and the depletion type MOS transistor  3  is connected to the bias voltage supply means  201  including a depletion type MOS transistor  6 , an enhancement type MOS transistor  7 , and a depletion type MOS transistor  8 . Similarly, it can be estimated that the depletion type MOS transistor  8  is connected to a bias voltage supply means including the depletion type MOS transistor  1 , the enhancement type MOS transistor  2 , and the depletion type MOS transistor  3 .  
         [0010]     In recent years, because mobile devices are widely available and for other reasons, the needs for the realization of a lower power consumption circuit, which can operate for a longer time with a battery of the same capacitance, is increasing. Along with the above circumstances, a reference voltage circuit having a comparable or superior performance to that of that conventional one, and still can operate at lower voltage is advantageous.  
         [0011]     In the circuit as illustrated in  FIG. 4 , when backgate terminals of all the transistors are at the ground potential, consider the lowest operating voltage where no deterioration in the power supply rejection ratio is observed. To this end, all the transistors forming a circuit are required to perform the saturated operation.  
         [0012]     In this case, gate-source voltages of the depletion type MOS transistors  3  and  8  each become zero when the characteristics of the two ED type reference voltage circuits are the same, and the characteristics of the depletion type transistors  3  and  8  each operate as a cascode circuit are the same, respectively. Therefore, the lowest operating voltage VDD(min) is expressed as the following equation:
 
 V   DD (min)= V   ref   +|V   T2 ( V   SB2   =V   ref )|+| V   T3 ( V   SB3   =V   ref   +|V   T2 ( V   SB2   =V   ref )|)|,  (Equation 1)
 
 where V ref  is an output voltage of the reference voltage output terminal  102 , V T2 (V SB2 =V ref ) is a threshold voltage of the enhancement type MOS transistor  2  when the source-backgate voltage is V ref , and V T3 (V SB3 =V ref +|V T2 (V SB2 =V ref )|) is the threshold voltage of the MOS transistor  3  when the source-backgate voltage is V ref +|V T2 (V SB2 =V ref )|. 
 
         [0013]     When the power supply voltage becomes lower than V DD (min) expressed in Equation 1, the depletion type MOS transistors  3  and  8 , which operate as a cascode circuit operate in an unsaturation state, and thus, the output resistance becomes small and the power supply rejection ratio is considerably deteriorated.  
       SUMMARY OF THE INVENTION  
       [0014]     The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a reference voltage circuit and an electronic device using a cascode circuit having a comparable or superior power supply rejection ratio to that of a conventional circuit at lower operating voltage.  
         [0015]     In order to attain the above-mentioned object, according to an aspect of the present invention, a reference voltage circuit includes a bias voltage supply means which can apply voltage lower than a gate potential to a source potential of an N-channel depletion type MOS transistor that operates as a cascode circuit, or, which can apply voltage higher than the gate potential to the source potential of a P-channel depletion type MOS transistor that operates as a cascode circuit. By making small the absolute value of the lowest necessary voltage for the saturated operation of the transistor, the lowest operating voltage of a reference voltage circuit can be lowered without deteriorating the power supply rejection ratio.  
         [0016]     Further, according to the present invention, there is employed a structure, in which a control current source detects current through a circuit which operates as a load of the cascode circuit, and the current of the control current source is used to determine the bias voltage of the cascode circuit, and thus, bias voltage fluctuations due to variations in the process are suppressed.  
         [0017]     The reference voltage circuit according to the present invention can, compared with the conventional circuit, operate at lower power supply voltage without the deterioration of the power supply rejection ratio. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     In the accompanying drawings:  
         [0019]      FIG. 1  is a circuit diagram illustrating a first embodiment of a semiconductor device using a cascode circuit according to the present invention;  
         [0020]      FIG. 2  illustrates an example of the structure of a conventional reference voltage circuit;  
         [0021]      FIG. 3  illustrates an example of the structure of another conventional reference voltage circuit;  
         [0022]      FIG. 4  illustrates an example of the structure of still another conventional reference voltage circuit;  
         [0023]      FIG. 5  is a circuit diagram illustrating the first embodiment of the semiconductor device using a cascode circuit according to the present invention;  
         [0024]      FIG. 6  is a circuit diagram illustrating a second embodiment of a semiconductor device using a cascode circuit according to the present invention; and  
         [0025]      FIG. 7  is a circuit diagram illustrating a third embodiment of a semiconductor device using a cascode circuit according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
     Embodiment 1  
       [0026]      FIG. 1  is a circuit diagram illustrating a first embodiment of a semiconductor device using a cascode circuit according to the present invention. An N-channel depletion type transistor  1  and an N-channel enhancement type MOS transistor  2  forms an ED type reference voltage circuit  200 . An N-channel depletion type transistor  3  which operates as a cascode circuit is connected in series to the ED type reference voltage circuit  200 . An N-channel enhancement type MOS transistor  4  as a control current source is connected in parallel with the N-channel enhancement type MOS transistor  2 . An N-channel depletion type MOS transistor  5  having a gate terminal and a source terminal connected to each other is connected in series to the N-channel enhancement type MOS transistor  4 . Further, the source terminal of the N-channel depletion type MOS transistor  5  is connected to a gate terminal of the N-channel depletion type transistor  3 . The N-channel enhancement type MOS transistor  4  and the N-channel depletion type MOS transistor  5  form a bias voltage supply means  201  for supplying constant bias voltage to the N-channel depletion type transistor  3 , which operates as the cascode circuit.  
         [0027]     In the circuit described in the above, when the characteristics and the transconductance coefficients of the N-channel enhancement type MOS transistors  2  and  4 , and that of the N-channel depletion type MOS transistors  3  and  5  are the same, the source-backgate voltage - drain current characteristics of the respective depletion type transistors are the same, and the drain currents of the respective depletion type transistors are the same, and thus, the source potentials of the respective depletion type transistors are the same.  
         [0028]     Here, by making the transconductance coefficient of the N-channel enhancement type MOS transistor  4  larger than the transconductance coefficient of the N-channel enhancement type MOS transistor  2  by, for example, fixing the L length and making larger the W length, the source potential of the MOS transistor  5  can be made lower than the source potential of the N-channel depletion type MOS transistor  3 .  
         [0029]     Specifically, by making the transconductance coefficient of the N-channel depletion type MOS transistor  5  smaller than the transconductance coefficient of the N-channel depletion type MOS transistor  3 , the source potential of the N-channel depletion type MOS transistor  5  can be made lower than the source potential of the N-channel depletion type MOS transistor  3 .  
         [0030]     Alternatively, by implementing both of the above, the source potential of the N-channel depletion type MOS transistor  5  can be made lower than the source potential of the N-channel depletion type MOS transistor  3 .  
         [0031]     In the structure as described in the above, the lowest operating voltage V DD (min) is expressed as the following equation:
 
 V   DD (min)= V   ref   +|V   T2 ( V   SB2   =V   ref )|+| V   T3 ( V   SB3   =V   ref   +|V   T2 ( V   SB2   =V   ref )|)+ V   gs3 ,  (Equation 2)
 
 where V ref  is an output voltage of the reference voltage output terminal  102 , V T2 (V SB2 =V ref ) is a threshold voltage of the enhancement type MOS transistor  2  when the source-backgate voltage is V ref , V T3 (V SB3 =V ref +|V T2 (V SB2 =V ref )|) is a threshold voltage of the MOS transistor  3  when the source-backgate voltage is V ref +|V T2 (V SB2 =V ref )|, and V gs3  is a gate-source voltage of the MOS transistor  3 . 
 
         [0032]     In this case, because the source potential of the MOS transistor  5  is lower than the source potential of the N-channel depletion type MOS transistor  3 , V gs3 &lt;0, and thus, the lowest operating voltage V DD (min) can be made lower than that of a conventional configuration.  
         [0033]     Further, by using the cascode circuit according to the present invention as a source follower circuit as illustrated in  FIG. 5  in addition to using as the reference voltage circuit in  FIG. 1 , similar effects can be obtained.  
       Embodiment 2  
       [0034]      FIG. 6  is a circuit diagram illustrating a second embodiment of a semiconductor device using a cascode circuit according to the present invention.  
         [0035]     The circuit is structured such that N-channel depletion type transistors  10  and  3  which operate as cascode circuits are connected to an ED type reference voltage circuit  203  including an N-channel depletion type transistor  1 , an N-channel depletion type transistor  9 , an N-channel enhancement type MOS transistor  2 , and a group of resistances  11 .  
         [0036]     An N-channel enhancement type MOS transistor  4  as a control current source is connected in parallel with the group of resistances  11 . Further, An N-channel depletion type MOS transistor  5  having a gate terminal connected to a source terminal thereof is connected in series to the N-channel enhancement type MOS transistor  4 .  
         [0037]     Further, the source terminal of the N-channel depletion type MOS transistor  5  is connected to gate terminals of the N-channel depletion type transistors  10  and  3 , and the N-channel enhancement type MOS transistor  4  and the N-channel depletion type MOS transistor  5  form a bias voltage supply means  201  for supplying constant bias voltage to the N-channel depletion type transistors  10  and  3  which operate as the cascode circuits.  
         [0038]     In this circuit, also, by making the transconductance coefficient of the N-channel depletion type MOS transistor  5  smaller than the transconductance coefficient of the N-channel depletion type MOS transistor  3 , the source potential of the N-channel depletion type MOS transistor  5  can be made lower than the source potential of the N-channel depletion type MOS transistor  3 . In this construction, similarly to the case of Embodiment 1, the lowest operating voltage V DD (min) is expressed as Equation 2. Because the source potential of the MOS transistor  5  is lower than the source potential of the N-channel depletion type MOS transistor  3 , V gs3 &lt;0, and thus, the lowest operating voltage V DD (min) can be made lower than that of a conventional configuration.  
         [0039]     With regard to the relationship between transconductance coefficients of the transistors, constructions similar to those described in the first embodiment can obtain similar effects.  
       Embodiment 3  
       [0040]      FIG. 7  is a circuit diagram illustrating a third embodiment of a semiconductor device using a cascode circuit according to the present invention.  
         [0041]     Similarly to the case of the second embodiment, the circuit is constructed such that an N-channel depletion type transistor  3  which operates as a cascode circuit is connected to an ED type reference voltage circuit  203  including an N-channel depletion type transistor  1 , an N-channel depletion type transistor  9 , an N-channel enhancement type MOS transistor  2 , and a group of resistances  11 , and a gate of an N-channel depletion type transistor  10  which operates as a cascode circuit is connected to a source terminal of the N-channel depletion type transistor  3 .  
         [0042]     An N-channel enhancement type MOS transistor  4  as a control current source is connected in parallel with the group of resistances  11 . Further, An N-channel depletion type MOS transistor  5  having a gate terminal connected to a source terminal thereof is connected in series to the N-channel enhancement type MOS transistor  4 .  
         [0043]     Further, the source terminal of the N-channel depletion type MOS transistor  5  is connected to a gate terminal of the N-channel depletion type transistor  3 , and the N-channel enhancement type MOS transistor  4  and the N-channel depletion type MOS transistor  5  form a bias voltage supply means  201  for supplying constant bias voltage to the N-channel depletion type transistor  3  which operates as the cascode circuit.  
         [0044]     In this circuit, also, by making the transconductance coefficient of the N-channel depletion type MOS transistor  5  smaller than the transconductance coefficient of the N-channel depletion type MOS transistor  3 , the source potential of the N-channel depletion type MOS transistor  5  can be made lower than the source potential of the N-channel depletion type MOS transistor  3 . In this construction, similarly to the case of Embodiment 1, the lowest operating voltage VDD(min) is expressed as Equation 2. Because the source potential of the MOS transistor  5  is lower than the source potential of the N-channel depletion type MOS transistor  3 , V gs3 &lt;0, and thus, the lowest operating voltage V DD (min) can be made lower than that of a conventional configuration.