Abstract:
A network interface including: a medium access control device configured to operate at a first power state during an inactive power mode, and operate at a second power state during an active power mode; a physical layer device including (i) an energy detect module configured to detect energy on a medium during the inactive power mode, and (ii) an energy save module configured to time a first pre-determined period subsequent to the energy detect module detecting energy on the medium. The medium access control device is further configured to, subsequent to the energy detect module detecting energy on the medium, transition to the second power state of the active power mode, and communication with the medium access control device via the medium is enabled subsequent to expiration of the first pre-determined period.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 12/157,239 (Now U.S. Pat. No. 7,937,600), filed Jun. 9, 2008, which is a continuation of U.S. application Ser. No. 11/114,402 (Now U.S. Pat. No. 7,392,412), filed Apr. 26, 2005, which is a continuation-in-part of U.S. application Ser. No. 09/990,137 (Now U.S. Pat. No. 6,993,667), filed Nov. 21, 2001, which claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application No. 60/256,117, filed Dec. 15, 2000. The disclosures of the above applications are incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present invention relates to network devices, and more particularly to energy saving modules for network devices. 
     BACKGROUND 
     Referring now to  FIG. 1 , host devices  10 , such as computers, personal digital assistants (PDA&#39;s) and/or network enabled devices and/or appliances, commonly include a network interface  12  for communicating with other hosts or link partners over a medium. The network interface  12  draws power from a power source associated with the host device  10 . 
     Referring now to  FIG. 2 , the network interface  12  typically includes a host interface  14  that provides an interface to the host device  10 . A MAC device/buffer  18  includes logic that bridges a physical layer (PHY) device  20  and the host interface  14 . The PHY device  20  communicates with a wired or wireless medium  21 . In some implementations, the host interface  14  is compatible with a peripheral component interconnect (PCI) and/or PCI-Express (PCI-E) protocols. A regulator module  22  may be provided that receives a first voltage level from the host device  10  and converts the first voltage level to a second voltage level for use in the network interface  12 . 
     The power that is dissipated by the network interface  12  tends to cause undesirable heat generation. For portable host devices  10 , the power consumption of the network interface  12  also tends to reduce battery life of the host device  10 . 
     SUMMARY 
     In general, in one aspect, this specification describes a network interface including: a medium access control device configured to operate at a first power state during an inactive power mode, and operate at a second power state during an active power mode; a physical layer device including (i) an energy detect module configured to detect energy on a medium during the inactive power mode, and (ii) an energy save module configured to time a first pre-determined period subsequent to the energy detect module detecting energy on the medium. The medium access control device is further configured to, subsequent to the energy detect module detecting energy on the medium, transition to the second power state of the active power mode, and communication with the medium access control device via the medium is enabled subsequent to expiration of the first pre-determined period. 
     Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is a functional block diagram of host device and network interface according to the prior art; 
         FIG. 2  is a functional block diagram of the network interface of  FIG. 1  in further detail; 
         FIG. 3  is a functional block diagram of a network interface; 
         FIG. 4  is a functional block diagram of a network interface according to the present invention; 
         FIG. 5  is a state diagram of power management for a physical layer (PHY) device; and 
         FIG. 6  is a state diagram of power management for a medium access control (MAC) device and a host interface. 
     
    
    
     DETAILED DESCRIPTION 
     The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module and/or device refers to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. For purposes of clarity, the same reference numerals will be used to identify similar elements. References to logical one, true, and on are equivalent to each other, and references to logical zero, false, and off are equivalent to each other, unless otherwise noted. Parts or all of the invention may also be implemented with equivalent embodiments using logic that is inverted from that disclosed. 
     Referring now to  FIG. 3 , a block diagram of a network interface  23  is shown. A regulator module  24  has a power input  26  that receives power from the host device  10 . A plurality of regulator module outputs  28 - 1 ,  28 - 2 ,  28 - 3 , and  28 - 4  (collectively regulator module outputs  28 ) provide power to other modules of the network interface  12 . A host interface  30  provides bidirectional communication with the host device  10 . 
     A physical layer (PHY) device  34  includes an energy savings module (ESM)  36  and other PHY device modules  38 . The ESM  36  has an output  40  that switches at least some of the PHY device modules  38  between active and inactive power modes depending upon link status and activity. A medium access control (MAC) device  44  communicates with the host device  10  through the host interface  30 . The MAC device  44  also communicates with the PHY device  34  and receives a link status signal  46  indicating the presence or absence of a link. 
     Referring now to  FIG. 4 , an improved network interface  50  is shown connected to the host device  10 . A regulator module  52  has a power input  54  that receives power from the host device  10 . A clock module  55  generates at least first and second clock signals. The first or lower clock signal may be used to supply low voltage logic running during the inactive mode. The second or higher clock signal may be used during the active mode for higher speed logic. The clock module  55  may include a clock generator, a phase-locked loop (PLL), an oscillator and/or any other circuit to generate the two clock signals. To simplify  FIG. 4 , skilled artisans will appreciate that individual connections from the clock module  55  to components in the network interface are present but not shown. 
     The regulator module  52  has a plurality of regulator module outputs  56 - 1 ,  56 - 2 ,  56 - 3 , and  56 - 4  that are referred to collectively as the regulator module outputs  56 . The regulator module outputs  56 - 1 ,  56 - 2 ,  56 - 3  and  56 - 4  provide power to a PHY device  66 , a MAC device  62 , and a host interface  64 , respectively. 
     The PHY device  66 , the MAC device  62 , and the host interface  64  include one or more analog and/or digital modules. Analog modules can be powered during the active mode and either powered or not powered (0 volts) during the inactive mode. Analog modules that are not powered typically require settling time when transitioning back to the active mode. Digital modules can be powered at a second or higher voltage level during the active mode. Digital modules can be powered at a first or lower voltage level during the inactive mode to maintain logic states. Digital modules can receive a higher clock signal during the active mode and a lower clock signal (for logic that runs during the inactive mode) or no clock signal during the inactive mode. 
     One or more of the regulator module outputs  56  are individually switchable between two or more output voltages. In a some implementations, the regulator module outputs  56  are switchable between two non-zero voltages. The first voltage is selected to be sufficient to place the host interface  64  and the MAC device  62  in a standby condition to retain data. The second voltage is greater than the first voltage and is selected to allow the host interface  64 , the MAC device  62 , and a PHY device  66  to be fully operational. The PHY device  66  communicates with a medium  67 . For analog modules that are not powered, a third voltage or ground can be provided and/or a switched ground connection. A voltage selection signal  68  determines whether the first voltage or the second voltage is applied by each of the regulator module outputs  56  as will be described below. 
     The MAC device  62 , which may contain a data buffer, is in bidirectional communication with the host interface  64  and the PHY device  66 . The PHY device  66  selectively negotiates link parameters of a link. A link status signal  78  from the PHY device  66  provides the MAC device  62  with an indication of whether the PHY device  66  has established a link. 
     The ESM  58  includes one or more timers  82  and generates an energy signal that is used to indicate operational states of the network interface  50 . A first timer TMR 1  is reset when energy exceeding a predetermined threshold is detected by an energy detect module  76 . TMR 1  is used to limit the amount of time that the PHY device  66  attempts to establish a link after activity is detected and is subsequently not detected. When the link is lost, the PHY device  66  is powered down and the ESM  58  and the energy detect module  76  remain powered and monitor the medium for activity. When activity is detected, the PHY device  66  is powered up, TMR 1  is reset and the PHY device  66  attempts to establish a link. If the TMR 1  times out before a link is established, the PHY device  66  returns to the inactive mode. 
     The energy detect module  76  may be implemented by a low power comparator, which compares signals on the medium  67  to a threshold. The energy detect module  76  may alternatively include a digital input that is driven by an optics module that determines when a sufficient amount of optical energy is received. In some implementations, the PHY device  66  indicates link status. In some implementations, the PHY device  66  may include an autonegotiation module that negotiates link parameters and indicates link status, although the PHY device  66  need not include an autonegotiation module and/or be capable of autonegotiation. 
     A second timer TMR 2  is used by the PHY device  66  to periodically transition the inactive PHY device to active mode and transmit pulses such as link pulses. If two network devices or link partners have power save functionality, both devices may remain inactive for an indefinite period while listening for activity. Therefore, even if activity is not detected, the PHY device  66  is periodically powered up when TMR 2  times out and link pulses are sent. Upon receiving the link pulses, a link partner will detect activity, exit the inactive mode and attempt to establish a link. 
     Additional timers TMR 3  and TMR 4  are used to track time after state changes, which are described later herein, to provide settling times between selected state changes and/or sufficient time to complete processes. An energy signal provides an indication that a receive signal exceeds a threshold. The ESM  58  also generates the voltage selection signal  68 . 
     Referring now to  FIG. 5 , a state diagram  90  of the PHY device  66  is shown. Upon receiving a reset signal  92 , the regulator module outputs  56  are set to the first voltage and the PHY device  66  enters an ENERGY_DETECT state  94 . The ESM  58  sets the energy signal to false, thereby indicating that the PHY device  66  is waiting for activity on the medium. The PHY device  66  remains in a low power condition. TMR 2  is started. When TMR 2  expires, the PHY device  66  changes to a PULSE state  95 . In the PULSE states, TMR 5  is started, energy=0 and the PHY sends a pulse. If a signal is not detected, the PHY device transitions to a LINE_ACTIVE state  96 . Alternatively, if TMR 5  expires, the PHY returns to the ENERGY_DETECT state  94 . TMR 5  expires when the pulse is detected. When the energy detect module  76  detects activity as described above, the PHY device  66  changes to a LINE_ACTIVE state  96 . 
     In the LINE_ACTIVE state  96 , the ESM  58  changes the energy signal from false to true, indicating that activity has been detected. The receive signal starts TMR 1 . The false to true transition of the energy signal causes the ESM  58  to switch the regulator module outputs  56  to the second voltage. The PHY device  66  also attempts to establish a communication link. When the PHY device  66  establishes the communication link, as indicated by the link status signal  78 , it leaves the LINE_ACTIVE state  96  and enters a LINK_UP state  98 . 
     In the LINK_UP state  98 , the energy signal remains true. The PHY device  66  remains in the LINK_UP state  98  until it loses the communication link as indicated by the link status signal  78  changing from true to false. Upon losing the communication link the PHY device  66  leaves the LINK_UP state  98  and enters a POWERING_DOWN state  100 . 
     In the POWERING_DOWN state  100 , the PHY device  66  starts TMR 4  and changes the energy signal from true to false. The MAC device  62  responds to the link status signal  78  becoming false by preparing for the regulator module output  56 - 3  to return to the first voltage. TMR 4  expires after a predetermined time, which may be different from the predetermined time the PHY device returns to the ENERGY_DETECT state. 
     Discussion will now return to the LINE_ACTIVE state  96 . If the receive signal activity ceases and TMR 1  expires before the PHY device  66  establishes the communication link, the PHY device  66  will change to the POWERING_DOWN state  100 . 
     Referring now to  FIG. 6 , a state diagram  102  of the MAC device  62  and the host interface  64  is shown. Upon receiving the reset signal  92 , the regulator module outputs  56  are set to the first voltage and the MAC device  62  and the host interface  64  enter a LOW_VOLTAGE state  104 . The LOW_VOLTAGE state  104  allows the MAC device  62  and the host interface  64  to have lower leakage currents than when the regulator module outputs  56  are at the second voltage. When the energy signal  88  changes from false to true and/or link status changes to false, the ESM  58  increases the regulator module outputs  56 - 3  and  56 - 4  to the second voltage, thereby changing the MAC device  62  and the host interface  64  to a NORMAL_VOLTAGE state  106 . 
     Upon entering the NORMAL_VOLTAGE state  106 , the MAC device  62  and the host interface  64  are provided time to stabilize from the voltage increase TMR 3  is also started. When TMR 3  expires, the MAC device  62  and the host interface  64  change to a POWER_UP state  108 . 
     In the POWER_UP state  108 , the MAC device  62  and the host interface  64  are fully operational and the regulator module outputs  56  are at the second voltage. The MAC device  62  and the host interface  64  remain in the POWER_UP state  108  until the link status signal  78  changes from true to false. Upon link status signal  78  being changed, the MAC device  62  and the host interface  64  change to a POWER_DOWN state  110 . 
     Upon entering the POWER_DOWN state  110 , the MAC device  62  and the host interface  64  begin preparing for the regulator module lines  56 - 3  and  56 - 4  to return to the first voltage. For example, the MAC device  62  may prepare by emptying its buffer if so equipped, or by preparing other internal registers for the voltage change. TMR 6  is started. Upon expiration of TMR 6 , the ESM  58  switches the regulator module outputs  56 , thereby returning the MAC device  62  and the host interface  64  to the LOW_VOLTAGE state  104 . 
     Returning now to the NORMAL_VOLTAGE state  94 . If the PHY device  66  changes the energy signal  88  from true to false, then the MAC device  62  and the host interface  64  will transition to from the NORMAL_VOLTAGE state  106  directly to the POWER_DOWN state  110 . 
     Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.