Abstract:
A write driver circuit selectively provides write current through a write head in first and second opposite directions. First and second active devices are driven with first and second pre-drive signals. Third and fourth active devices are driven with third and fourth pre-drive signals. First and second pull-up resistances are provided respectively between the first and second active devices and a fixed voltage, and third and fourth pull-up resistances are provided respectively between the third and fourth active devices and the fixed voltage. A first capacitor is connected between the first active device and an intermediate point of the third pull-up resistance, and a second capacitor is connected between the second active device and an intermediate point of the fourth pull-up resistance.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to a driving circuit for the write head of a magnetic disk drive, and more particularly to a write driver employing capacitive boost to improve the switching performance of the circuit.  
           [0002]    Write driver circuits are employed to provide a write current through a write head in order to record information on a magnetic disk. The write driver circuit is operable to switch the direction of the write current in a pattern that represents data to be recorded, with the switching typically performed by a circuit configuration known in the art as an H-bridge. An H-bridge is characterized by four transistor switches or variations thereof, each forming a leg of the H, with the write head coil being connected to terminals across the center span of the H. Current is directed in a first direction through the write head by operating two semiconductor switches in opposite legs of the H-bridge, and current is directed in the opposite direction through the write head by operating the other two semiconductor switches.  
           [0003]    It is desirable for the H-bridge to switch the direction of the write current through the write head as quickly as possible, to enable a high data recording rate. The semiconductor switches of the H-bridge therefore need to be turned on as quickly as possible when they are to conduct current. One way to turn the semiconductor switches on quickly is to provide “overshoot” in the pre-drive signal that drives the transistor switches. Overshoot is defined as the amount by which the pre-drive signal exceeds its quiescent value, when a transition in write current direction is to occur. By overshooting the quiescent value when a transition is commanded, the transistor switches are turned on more quickly, decreasing the time required to switch the write current direction and increasing the rate at which data can be written. This overshoot in the pre-drive signal also causes the write current signal itself to exhibit some amount of overshoot, so that the pre-drive signal waveform and the write current waveform have similar shapes.  
           [0004]    There are several factors which can limit the ability of the write driver circuit to provide effective overshoot of the predriver signal. One of these factors is the limit on the pulled-up base voltage of the upper switches of the H-bridge. The bases of these switches (configured as emitter-follower transistors) are conventionally pulled up to the positive voltage supply by a resistor. When the emitter-follower is pulled up maximally, the collector-base junction is unbiased. There is potential to forward-bias this junction by as much as a diode (i.e., about 0.7 volts), since the base of the emitter-follower transistor can be boosted above the supply voltage by as much as a diode before the emitter-follower transistor saturates. It would therefore be desirable to provide a circuit that allows the base voltage of the switching transistor to be boosted to a higher value than is possible with conventional designs. Such a circuit, employing a capacitive boosting technique, is the subject of the present invention.  
         BRIEF SUMMARY OF THE INVENTION  
         [0005]    The present invention is a write driver circuit that selectively provides write current through a write head in first and second opposite directions. First and second active devices are driven with first and second pre-drive signals. Third and fourth active devices are driven with third and fourth pre-drive signals. First and second pull-up resistances are provided respectively between the first and second active devices and a fixed voltage, and third and fourth pull-up resistances are provided respectively between the third and fourth active devices and the fixed voltage. A first capacitor is connected between the first active device and an intermediate point of the third pull-up resistance, and a second capacitor is connected between the second active device and an intermediate point of the fourth pull-up resistance. As a result of the configuration of the present invention, the high frequency response of the circuit is improved. In addition, by controlling the relative amplitudes of the high and low frequency portions of the pre-drive signals, the voltage driving the third and fourth active devices can be boosted toward (and potentially above) the positive supply voltage, improving the switching speed of those devices and increasing the overshoot (and reducing the rise time) of the write current waveform. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    [0006]FIG. 1 is a schematic diagram of a prior art write circuit.  
         [0007]    FIGS.  2 A- 2 C are graphs of waveforms which occur in operation of the circuit of FIG. 1.  
         [0008]    [0008]FIG. 3 is a schematic diagram of a write circuit employing capacitive boost according to the present invention.  
         [0009]    FIGS.  4 A- 4 E are graphs of waveforms which occur in the operation of the circuit of FIG. 3.  
         [0010]    [0010]FIG. 5 is a diagram of an exemplary full circuit implementation of a write circuit employing capacitive boost according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0011]    [0011]FIG. 1 is a schematic diagram of prior art write circuit  10 . Write circuit  10  includes resistors R 1 , R 2 , R 3 , R 4 , R 5  and R 6 , transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 6 , current sources I 1  and I 2 , and inductive head  12  having inductance L H . Transistors Q 1  and Q 2  make up the upper switching portion of the circuit, while transistors Q 3 -Q 4  and Q 5 -Q 6  are configured as current mirrors to form the lower portion of the circuit. Transistors Q 1  and Q 2  each have a parasitic capacitance C P  which is represented schematically in FIG. 1.  
         [0012]    FIGS.  2 A- 2 C are graphs of waveforms which occur in operation of the circuit of FIG. 1. Current sources I 1  and I 2  provide current in an alternating fashion, as shown by waveforms  20  (FIG. 2A) and  22  (FIG. 2B), respectively. These currents result in a current flowing through one of transistors Q 1  and Q 2  and through head  12  (FIG. 1). Because of the parasitic capacitances of transistors Q 1  and Q 2  and their effect on frequency response, the current I HEAD  flowing through head  12  (shown by waveform  24 , FIG. 2C) takes time to transition between steady state values in opposite directions, known as the “rise time.” The frequency response of the emitter follower is governed by the following equation, which determines the effective pole of the frequency response:  
             f   =     1     2                 π                 R                   C   P                 (     Eq   .              1     )                               
 
         [0013]    where R is the value of the resistor connected to the base of the switching transistor and C P  is the parasitic capacitance of the transistor. For transistor Q 1 , the relevant resistor is R 1 , and for transistor Q 2 , the relevant resistor is R 2 . In most exemplary embodiments, resistors R 1  and R 2  are selected to have equal resistances and transistors Q 1  and Q 2  are selected to have equal parasitic capacitances, to preserve the symmetry of the circuit.  
         [0014]    In order to improve the frequency response of the emitter follower (that is, increase the frequency of the effective pole), either the resistance or parasitic capacitance must be reduced. It is not practical to reduce the parasitic capacitance, since the current-carrying capability of the transistor would be compromised. A reduction in the resistance is therefore desirable.  
         [0015]    [0015]FIG. 3 is a schematic diagram of write circuit  30  employing capacitive boost according to the present invention. Write circuit  30  includes resistors R A1 , R A2 , R B , R C1 , R C2 , R D , R E , R F , R G  and R H , transistors Q A , Q B , Q C , Q D , Q E , Q F , Q G  and Q H , capacitors C 1  and C 2 , current sources I A1 , I A2 , I B1 , I B2 , I DC1  and I DC2 , and head  12  having an inductance L H . Transistors Q A , Q B , Q C  and Q D  make up the upper switching portion of the circuit, while transistors Q E -Q F  and Q G -Q H  are configured as current mirrors to form the lower portion of the circuit to pull current through the write head. Transistors Q A , Q B , Q C  and Q D  have respective parasitic capacitances C PA , C PB , C PC  and C PD  which are represented schematically in FIG. 3.  
         [0016]    FIGS.  4 A- 4 E are graphs of waveforms which occur in operation of the circuit of FIG. 3. Current sources I A1 , I A2 , I B1  and I B2  are configured to provide pre-drive currents. Current sources I A1/A2  and I B1/B2  provide current in an alternating fashion, as shown by waveforms  40  (FIG. 4A),  42  (FIG. 4B),  44  (FIG. 4C) and  46  (FIG. 4D), respectively. The write current I HEAD  flowing through the write head is shown as waveform  48  (FIG. 4E).  
         [0017]    Referring again to FIG. 3, transistors Q C  and Q D  are configured as emitter-followers. Resistors R A1  and R C1  are selected to have a value of about 75% of the value of a conventional pull-up resistor (such as R 1  shown in FIG. 1). Transistors Q C  and Q D  therefore have good high frequency response, since the resistance is reduced (see Eq. 1). Current sources I DC1  and I DC2  provide a DC current to ensure that transistors Q C  and Q D  are always on. As a result, the signals at the emitters of transistors Q C  and Q D  accurately reflect the signal content of the input signals provided by current sources I A1  and I B1 .  
         [0018]    Series capacitors C 1  and C 2  pass the high frequency content of the signals at the emitters of transistors Q C  and Q D  on to node  32  between resistors R A2  and R B  (an intermediate point of the pull-up resistance) and to node  34  between resistors R C2  and R D  (an intermediate point of the pull-up resistance), respectively. Resistors R A2  and R C2  are selected to have values equal to the values of resistors R A1  and R A2  (about 75% of the value of a conventional pull-up resistor), and resistors R B  and R D  are elected to have a value of about 25% of the value of a conventional pull-up resistor. Since resistors R A2  and R B  are connected in series between the base of transistor Q A  and V CC , and resistors R C2  and R D  are connected in series between the base of transistor Q B  and V CC , the total pull-up resistance provided for transistors Q A  and Q B  is equal to the conventional pull-up resistance. However, the resistance that affects the frequency response of transistors Q A  and Q B  is only R B  and R D , respectively. Since R B  and R D  are only about 25% of the value of a conventional pull-up resistor, the effective pole of the frequency response of transistors Q A  and Q B  is about four times higher than in a conventional system.  
         [0019]    The preceding description has explained the improved frequency response of the circuit of FIG. 3. Capacitive boost of the voltage across head  12  may also be obtained by adjusting the signal waveforms provided by current sources I A1 , I A2 , I B1  and I B2 . Specifically, as shown in FIGS.  4 A- 4 D, the target write waveform is essentially decomposed into a boost (higher frequency) portion provided by current sources I A1  and I B1 , and a steady state (lower frequency) portion provided by current sources I A2  and I B2 . A greater percentage of the overshoot portion of the signal is assigned to the boost current source (I A1  and I B1 ), compared to the portion assigned to the steady state current source (I A2  and I B2 ). This is shown graphically in the disparate magnitudes of the overshoot portions and steady state portions of the waveforms shown in FIG. 4A- 4 D. As a result, the voltage at the bases of transistors Q A  and Q B  is level shifted toward (and potentially above) the positive supply voltage V CC . The total amount of level shifting that is possible is limited by the difference between the overshoot voltage of the write voltage waveform and the steady state voltage of the write voltage waveform, which is supply limited. The amount of level shifting is limited to about a diode (i.e., about 0.7 volts), at which point the emitter follower transistor would saturate. The circuit of the present invention improves the switching speed and frequency response of the system, as shown by the increased overshoot and faster switching of write current direction in waveform  48  of FIG. 4E (compared to waveform  24  of FIG. 2C).  
         [0020]    For the benefit of those skilled in the art, a mathematical explanation of the frequency response benefits of the present invention is also included. The frequency response associated with transistor Q C  driven by current source I A1 , is as follows:  
               V   A1     =       I   A1          R   A1            j                 ω                   C   1          R   A2         1   +     j                   ω        [         C   1          R   A2       +       C     P                 A            (       R   A2     +     R   B       )         ]         -       ω   2          C   1          R   A2          C     P                 A            R   B                     (     Eq   .              2     )                               
 
         [0021]    The frequency response associated with transistor Q A , driven by current source I A2 , is as follows:  
               V   A2     =         I   A2          (       R   A2     +     R   B       )              1   +     j                 ω                     C   1          (       R   A2                       R   B       )             1   +     j                   ω        [         C   1          R   A2       +       C   PA          (       R   A2     +     R   B       )         ]         -       ω   2          C   1          R   A2          C     P                 A            R   B                     (     Eq   .              3     )                               
 
         [0022]    By selecting the value of C 1  to be much greater than C PA , the equations can be approximated in a much simpler manner:  
               V   A1     ≈       I   A1          R   A1            j                 ω                   C   1          R   A2           (     1   +     j                 ω                   C   1          R   A2         )          (     1   +     j                 ω                   C   PA          R   B         )                   (     Eq   .              4     )                 V   A2     ≈         I   A2          (       R   A2     +     R   B       )              1   +     j                 ω                     C   1          (       R   A2                       R   B       )               (     1   +     j                 ω                   C   1          R   A2         )          (     1   +     j                 ω                   C   PA          R   B         )                   (     Eq   .              5     )                               
 
         [0023]    If the magnitude of the boost current source(provided by I A1 ) is made equal to the magnitude of the attenuation of the mid-band response of the steady state current source (provided by I A2 ), the summation of the two responses is simplified. The condition for this is given by: 
         I A1 R A1 =I A2 R B   (Eq. 6) 
         [0024]    When this condition is satisfied, the summation of Eq. 4 and Eq. 5 becomes:  
               V   H     ≈         I   A2          (       R   A2     +     R   B       )            1     1   +     j                 ω                   C   PA          R   B                     (     Eq   .              7     )                               
 
         [0025]    The frequency response is therefore that of a low pass filter whose cutoff frequency is equal to:  
               f     3                 d                 B       =     1     2                 π                   C   PA          R   B                 (     Eq   .              8     )                               
 
         [0026]    which improves the frequency response of the system by the ratio of R B  to (R A2 +R B ).  
         [0027]    [0027]FIG. 5 is a schematic diagram of an exemplary full circuit implementation of a write circuit employing capacitive boost according to the present invention. It should be understood that the circuit shown in FIG. 5 is shown to illustrate the best mode of practicing the invention, and should not be considered to limit the scope of the invention in any way. The portions of the circuit which functionally represent the capacitive boost components shown in FIG. 3 are labeled in order to simplify the understanding of the circuit. One skilled in the art will readily discern the operating characteristics of the overall circuit, in conjunction with the specification and drawings of the instant application and of U.S. application Ser. No. ______ (Docket No. V44.12-0152) filed on even date herewith for “Disk Drive Writer With Active Reflection Cancellation,” by J. Leighton, C. Elliott, M. O&#39;Brien, C. Rabe, N. Krenz, R. Wimmer and S. O&#39;Brien, which is assigned to the same assignee as the instant application, and is hereby incorporated by reference.  
         [0028]    Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Particularly, while some forms of the invention are described in the form of discrete devices, it is recognized that the circuit is preferably reduced to practice in the form of an integrated circuit (IC). Therefore, terms such as “device” and the like should be construed in their broadest contexts to include portions of ICs that are conveniently described as functional components, as well as discrete devices. Likewise, some forms of the invention are described in terms of logical gates and chips that could also be implemented by discrete devices, all within the scope and spirit of the present invention.