Abstract:
A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package having an embedded chip and a fabrication method thereof. 
         [0003]    2. Description of Related Art 
         [0004]    Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high performance. To meet the miniaturization requirement of semiconductor packages, wafer level packaging (WLP) technologies have been developed. 
         [0005]    U.S. Pat. No. 6,452,265 and No. 7,202,107 provide fabrication methods of wafer-level packages.  FIGS. 1A to 1E  are cross-sectional views showing a fabrication method of a semiconductor package  1  according to the prior art. 
         [0006]    Referring to  FIG. 1A , a thermal adhesive layer  11  is formed on a carrier  10 . 
         [0007]    Referring to  FIG. 1B , a plurality of chips  12  are disposed on the thermal adhesive layer  11 . Each of the chips  12  has an active surface  12   a  with a plurality of electrode pads  120  and an inactive surface  12   b  opposite to the active surface  12   a,  and the chips  12  are disposed on the thermal adhesive layer  11  via the active surfaces  12   a  thereof. 
         [0008]    Referring to  FIG. 1C , an encapsulant  13  is formed on the chips  12  and the thermal adhesive layer  11 . 
         [0009]    Referring to  FIG. 1D , the thermal adhesive layer  11  and the carrier  10  are removed to expose the active surfaces  12   a  of the chips  12 . 
         [0010]    Referring to  FIG. 1E , a circuit structure  14  is formed on the encapsulant  13  and the active surfaces  12   a  of the chips  12  and electrically connected to the electrode pads  120  of the chips  12 . 
         [0011]    However, when the chips  12  are disposed on the plate-shaped carrier  10  having the thermal adhesive layer  11 , it is difficult to align the chips  12  on the carrier, thus easily causing displacement of the chips  12  and reducing the product reliability. 
         [0012]    In addition, since the thermal adhesive layer  11  is adhesive, it may expand or contract due to its coefficient of thermal expansion (CTE) during the fabrication process, such that displacement of the chips  12  tends to occur. For example, during formation of the encapsulant  13 , the thermal adhesive layer  11  is softened by heat to cause displacement of the chips  12 . Consequently, the circuit structure  14  to be formed later cannot be precisely connected to the electrode pads  120  of the chips  12 , thereby resulting in poor electrical performance and product reliability. 
         [0013]    Therefore, how to overcome the above-described drawbacks has become critical. 
       SUMMARY OF THE INVENTION 
       [0014]    In view of the above-described drawbacks, the present invention provides a semiconductor package, which comprises: an encapsulant having a protruding portion; a chip embedded in the protruding portion of the encapsulant, wherein the chip has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, the active surface and the electrode pads being exposed from the protruding portion of the encapsulant; and a circuit structure formed on the encapsulant and the active surface of the chip and electrically connected to the electrode pads of the chip. 
         [0015]    The present invention further provides a fabrication method of a semiconductor package, which comprises the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion, wherein the chip has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, the chip being disposed on the releasing layer via the active surface thereof; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier so as to expose the active surface of the chip; and forming a circuit structure on the encapsulant and the active surface of the chip, wherein the circuit structure is electrically connected to the electrode pads of the chip. 
         [0016]    The present invention further provides a carrier for fabricating a semiconductor package, wherein the carrier has a concave portion and a releasing layer formed on a surface thereof. 
         [0017]    In an embodiment, the carrier can be made of glass or metal, and the releasing layer can be made of a hydrophobic material, an inorganic material or a polymer material. 
         [0018]    In an embodiment, a plurality of concave portions are provided and array arranged on the carrier such that the above-described method further comprises performing a singulation process after forming the circuit structure on the encapsulant and the active surface of the chip. 
         [0019]    In an embodiment, the carrier is removed first and then the releasing layer is removed. Alternatively, the carrier and the releasing layer can be removed simultaneously. 
         [0020]    In an embodiment, the circuit structure has at least a dielectric layer formed on the encapsulant and the active surface of the chip, a circuit layer formed on the dielectric layer and a plurality of conductive vias formed in the dielectric layer for electrically connecting the circuit layer and the electrode pads of the chip. Further, an insulating protection layer can be formed on the outermost dielectric layer of the circuit structure and have a plurality of openings therein such that portions of the circuit layer are exposed through the openings so as for conductive elements to be disposed thereon. 
         [0021]    Therefore, through the design of the concave portion on the carrier, the present invention facilitates alignment of the chip so as to prevent it from displacement that may otherwise impose difficulty in subsequent fabrication processes such as a circuit built-up process and reduce the product reliability. 
         [0022]    Further, since the releasing layer is not adhesive, the releasing layer does not expand or contract due to its CTE during the fabrication process, thereby avoiding displacement of the chip, facilitating subsequent fabrication processes and improving the product reliability. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0023]      FIGS. 1A to 1E  are schematic cross-sectional views showing a fabrication method of a semiconductor package according to the prior art; and 
           [0024]      FIGS. 2A to 2G  are schematic cross-sectional views showing a fabrication method of a semiconductor package according to the present invention, wherein FIG.  2 A′ is an upper view of  FIG. 2A  and FIG.  2 E′ shows another embodiment of  FIG. 2E . 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0025]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification. 
         [0026]    It should be noted that the drawings are only for illustrative purposes and not intended to limit the present invention. Meanwhile, terms such as ‘on’, ‘a’ etc. are only used as a matter of descriptive convenience and not intended to have any other significance or provide limitations for the present invention. 
         [0027]      FIGS. 2A to 2G  are schematic cross-sectional views showing a fabrication method of a semiconductor package  2  according to the present invention. 
         [0028]    Referring to FIGS.  2 A and  2 A′, a carrier  20  having a plurality of concave portions  200  is provided. In the present embodiment, the carrier  20  is made of glass or metal, and the concave portions  200  are array arranged on the carrier  20 . 
         [0029]    Referring to  FIG. 2B , a releasing layer  21  is formed on the carrier  20  and the concave portions  200 . 
         [0030]    In the present embodiment, the releasing layer  21  is made of a hydrophobic material, an inorganic material or a polymer material such as poly-para-xylylene (parylene), and formed through plasma-enhanced chemical vapor deposition (PECVD). 
         [0031]    The present invention replaces the conventional thermal adhesive material with the releasing layer  21  to reduce the fabrication cost. 
         [0032]    Referring to  FIG. 2C , a plurality of chips  22  are disposed on the releasing layer  21  in the concave portions  200 , respectively. Each of the chips  22  has an active surface  22   a  with a plurality of electrode pads  220  and an inactive surface  22   b  opposite to the active surface  22   a,  and the chips  22  are disposed on the releasing layer  21  via the active surfaces  22   a  thereof. 
         [0033]    The concave portions  200  facilitate alignment of the chips  22  so as to avoid displacement of the chips  22 . 
         [0034]    Further, since the releasing layer  21  is not adhesive, particularly to the carrier  20  made of glass, the releasing layer  21  does not expand or extract due to its CTE during the fabrication process, thereby avoiding displacement of the chips  22 . As such, a circuit structure to be formed in a subsequent circuit built-up process can be effectively and precisely electrically connected to the electrode pads  220  of the chips  22  such that the electrical performance and product reliability can be improved. 
         [0035]    Referring to  FIG. 2D , an encapsulant  23  is formed on the chips  22  and the releasing layer  21 . 
         [0036]    In the present embodiment, the encapsulant  23  is made of, but not limited to, polyimide (PI), and formed through coating. Alternatively, the encapsulant  23  can be formed through lamination or molding. 
         [0037]    Referring to  FIG. 2E , the releasing layer  21  and the carrier  20  are removed to expose the active surfaces  22   a  of the chips  22  and a plurality of protruding portions  230  of the encapsulant  23 . 
         [0038]    In the present embodiment, the carrier  20  is first removed from the releasing layer  21  and then the releasing layer  21  is removed from the encapsulant  23  and the chip  22 . 
         [0039]    In another embodiment, the releasing layer  21  can be removed from the encapsulant  23  and the chips  22  simultaneously with the carrier  20 , as shown in FIG.  2 E′. 
         [0040]    Referring to  FIG. 2F , a circuit built-up process is performed to form a circuit structure  24  on the encapsulant  23  and the active surfaces  22   a  of the chips  22 . Therein, the circuit structure  24  is electrically connected to the electrode pads  220  of the chips  22 . 
         [0041]    In the present embodiment, the circuit structure  24  has at least a dielectric layer  240 , a circuit layer  241  formed on the dielectric layer  240  and a plurality of conductive vias  242  formed in the dielectric layer  230  for electrically connecting the circuit layer  241  and the electrode pads  220  of the chips  22 . Therein, the number of the dielectric layers  240  can be multiple, and the number of the circuit layer  241  can be increased to meet circuit layout requirements of the semiconductor package. 
         [0042]    Subsequently, an insulating protection layer  25  is formed on the outermost dielectric layer  240  and a plurality of openings  250  are formed in the insulating protection layer  25  such that portions of the circuit layer  241  are exposed through the openings  250  so as for conductive elements  26  to be disposed thereon. The conductive elements  26  can be, but not limited to, solder balls, solder bumps or solder pins. 
         [0043]    Referring to  FIG. 2G  a singulation process is performed along cutting lines L of  FIG. 2F  so as to obtain a plurality of semiconductor packages  2 . 
         [0044]    The present invention further provides a semiconductor package  2 , which has: an encapsulant  23  having a protruding portion  230 ; a chip  22  embedded in the protruding portion  230 ; and a circuit structure  24  formed on the encapsulant  23 . 
         [0045]    The chip  22  has an active surface  22   a  with a plurality of electrode pads  220  and an inactive surface  22   b  opposite to the active surface  22   a,  and the active surface  22   a  and the electrode pads  220  are exposed from the protruding portion  230  of the encapsulant  23 . 
         [0046]    The circuit structure  24  is formed on the active surface  22   a  of the chip  22  and electrically connected to the electrode pads  220  of the chip  22 . The circuit structure  24  has at least a dielectric layer  240 , a circuit layer  241  formed on the dielectric layer  240  and a plurality of conductive vias  242  formed in the dielectric layer  240  for electrically connecting the circuit layer  241  and the electrode pads  220  of the chip  22 . 
         [0047]    Furthermore, an insulating protection layer  25  is formed on the outermost dielectric layer  240  of the circuit structure  24  and has a plurality of openings  250  formed therein such that portions of the circuit layer  241  are exposed through the openings  250  so as for conductive elements  26  to be disposed thereon. 
         [0048]    Therefore, through the design of the concave portions on the carrier, the present invention facilitates alignment of the chips so as to avoid displacement of the chips, thereby improving the product reliability. 
         [0049]    Also, since the releasing layer is not adhesive, it will not cause displacement of the chips. Therefore, the product reliability is further improved. 
         [0050]    The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.