Abstract:
A phase alignment circuit which will take a square wave of constant period but indeterminate duty cycle and will transform it into a square wave of equal period and deterministic duty cycle, e.g. 50%. The preferred embodiment alternately charges and discharges two equal capacitors, and passes the resulting ramp voltages through a comparator to produce a square wave output with a 50% duty cycle.

Description:
This is a divisional application of Ser. No. 09/154,058, filed Sep. 16, 1998, now U.S. Pat. No. 6,154,076, which, claims priority under 35 USC §119(e)(1) of provisional application 60/059,681, filed Sep. 17, 1997. 
    
    
     BACKGROUND AND SUMMARY OF THE INVENTION 
     The present invention relates to crystal-stabilized integrated circuit oscillators and more particularly to phase alignment circuits for these oscillators. 
     Crystal-controlled oscillators use the high Q of an electromechanical resonator (a quartz crystal) to stabilize an oscillating circuit at a desired frequency. Such circuits can achieve a frequency stability in the parts-per-million range, and there is no other practical way to achieve such a constant frequency reference in an integrated circuit. Crystal-controlled oscillators are therefore extremely important, and likely to remain so. 
     Crystal-controlled oscillators pose some difficulties in design, and one of these is start-up. A variety of startup circuits have been proposed; see e.g. B. Parzen, DESIGN OF CRYSTAL AND OTHER HARMONIC OSCILLATORS (1983), at page 415; Unkrich et al., “Conditions for Start-Up in Crystal Oscillators,” 17  IEEE J. Solid - State Circuits  87 (1982). 
     Other difficulties are present in the specific context of low-power CMOS oscillator implementations. Many portable applications are designed for low operating voltage and low power consumption, but also require the frequency stability of a crystal oscillator. To reduce power consumption, such low-power CMOS oscillator circuits are typically operated in the weak inversion regime (where gate voltages are only slightly greater than the threshold voltage). However, in the weak inversion regime the gain tends to be lower, and thus start-up is a particularly critical problem. See e.g. U.S. Pat. No. 5,546,055, which is hereby incorporated by reference. 
     Low-power crystal oscillators, such as those used in real-time clock circuits, put out a signal whose duty cycle depends upon a number of different factors, such as threshold voltage, supply voltage, crystal characteristics, parasitics, temperature, etc. A 50% duty cycle can be achieved by passing this signal through a divide-by-2 circuit, but this reduces the frequency to one half that of the crystal. 
     It is possible to achieve a 50% duty cycle at full frequency by doubling the crystal frequency and then dividing the doubled frequency by two. This solution is not economical; only a few frequencies of crystal are made in sufficient volume to obtain minimum price (e.g. 38.4 kHz, 32.768 kHz), so this option would be too expensive for common usage. 
     A 50% duty cycle is useful for many applications; particularly in switch-mode power converters. A 50% duty cycle is also desirable for digital circuitry which uses both clock edges. 
     Innovative Phase Alignment Circuit 
     The innovative circuit described below uses paired capacitors to take a square wave of constant period but indeterminate duty cycle and to transform it into a square wave of equal period and deterministic duty cycle, e.g. 50%. The preferred embodiment alternately charges and discharges two equal capacitors, and passes the resulting ramp voltages through a comparator to produce a square wave output with a 50% or other predetermined duty cycle. 
     The innovative circuit can also be controlled to produce virtually any desired duty cycle. The selectable duty cycle allows the innovative circuit to be used for special purpose devices, as well as for charge pumps, converters, specialty clocks, etc. Finally, the innovative circuit can be used as a clock multiplier. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein: 
     FIG. 1 shows a block diagram of a crystal oscillator and phase alignment circuit according to the preferred embodiment. 
     FIG. 2 shows a high-level circuit diagram according to the preferred embodiment. 
     FIG. 3 shows a detailed phase-alignment circuit according to the preferred embodiment. 
     FIG. 4 shows a crystal oscillator circuit connected to a phase alignment circuit according to the preferred embodiment. 
     FIG. 5 shows a timing diagram of certain signals of the innovative circuit. 
     FIG. 6 shows a block diagram of an alternative embodiment of the present invention. 
     FIG. 7 shows a timing diagram of certain signals of the innovative circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment (by way of example, and not of limitation), in which: 
     FIG. 1 shows a block diagram of a crystal oscillator and phase alignment circuit connected in series, according to the preferred embodiment. FIG. 4 shows a typical crystal oscillator circuit connected in series with a phase alignment circuit according to the preferred embodiment. 
     The innovative circuit uses current-controlled capacitors to phase-align a periodic input signal. Because the voltages generated across the capacitor pair are defined only by the currents used to charge and discharge them, they vary simultaneously with process and temperature variations. The duty cycle produced by the circuit is therefore largely independent of temperature and process variations. 
     FIG. 2 shows a high-level diagram of a circuit according to the preferred embodiment. In this figure, the input signal IN, e.g. from a crystal oscillator, is received by flip-flop X 3 , the noninverting output S of which is used to control switches S 1  and S 2 . S is also used as an input to XOR gate X 2 . 
     Current sources IC and ID are used to charge and discharge, respectively, the two capacitors C 1  and C 2 . In a preferred embodiment, IC and ID are equal. C 1  and C 2  may of course be charged and discharged by individual current sources, but for the sake of simplicity, a single IC and ID are shown to switch between C 1  and C 2 . 
     Suppose, at time t=0, that IN and S are high. At this time, S 1  is connected so that IC charges C 2 , and S 2  is connected so that ID discharges C 1 . Absent other factors, this state remains for one period of input signal IN. The next time that IN goes high, X 3  is triggered and S goes low. At this time, S 1  and S 2  reverse, so that C 1  is charging and C 2  is discharging. This process repeats, alternating the charging of C 1  and C 2 , with each period of IN. 
     Comparator X 1  compares the voltages across C 1  and C 2 , and its output is connected to XOR gate X 2 , along with signal S. The output of X 2 , signal R, is high when S is high and the voltage across C 2  is greater than the voltage across C 1 . Similarly, R is high when S is low and the voltage across C 1  is greater than the voltage across C 2 . 
     In the detailed diagram of the preferred embodiment, as shown in FIG. 3, a pair of capacitors C 1  and C 2  are used to generate two ramp waveforms VR 1  and VR 2 , which are shown in FIG.  5 . In this embodiment, we set C 1 =C 2 . A current source IC is used to charge the capacitors, and current sources ID 1  and ID 2  are used to discharge them. In the preferred embodiment, IC=ID 1 =ID 2 . 
     Circuit Startup 
     At startup, when time t=0, both VR 1  and VR 2  will equal zero. IC is connected to charge C 1  for a time equal to one period T of the incoming signal. In the preferred embodiment, the incoming signal is the output of a crystal oscillator circuit, but alternate embodiments provide for virtually any periodic input signal. 
     At time t=T, VR 1 =IC·T/C 1 , and VR 2 =0. 
     At this time. (t=T), IC is.connected to charge C 2  and ID 1  is connected to discharge C 1 . In this embodiment, the slopes of the two voltage waveforms are equal in magnitude, but have opposite sign, so the two voltages VR 1  and VR 2  will equal one another at time t=3/2*T, or in other words the two voltages will equal one another one half-period after the transition at time (t=T). This point can be detected by a comparator to generate an output signal having the desired duty cycle of 50%. As soon as this transition is achieved, C 1  is discharged to ground by a switch to reset it to zero. VR 2  continues to charge until it reaches a voltage of VR 2 =IC*T/C 2  at time t=2T; at this point, IC is switched to C 1  and ID 2  is switched to C 2 . The two ramp voltages will cross one another one half-period later. By swapping between the two capacitors, this process can be kept up indefinitely. 
     In this embodiment, M 1 /M 2  are the input pair of a comparator which compares the ramp voltages VR 1  and VR 2  present across capacitors C 1  and C 2 . The remainder of the comparator consists of transistors M 3 , M 4 , M 5 , M 6 , M 7  and M 8  and Schmitt trigger X 1 . The output of X 1  is high when VR 2 &lt;VR 1 . 
     Capacitors C 1  and C 2  are charged from current source IC and discharged by current sources ID 1  and ID 2  (which may be merged into one by the addition of a suitable switching network). IC=ID 1 =ID 2 . Charge/discharge currents IC, ID 1 , and ID 2  are controlled by switches M 13 , M 14 , M 15 , and M 16 , which in turn are driven by phase latch X 4 . The outputs of X 4  toggle once per period, so as to alternately charge and discharge capacitors C 1  and C 2 . 
     If the voltage at the output of XOR gate X 2  is low at the end of any period of signal IN, then the capacitor being discharged has not been fully reset and the circuit may not operate properly. A start-up circuit consisting of flip-flop X 5 , gate X 7 , and transistors M 11  and M 12  will ensure proper starting under all possible conditions. If the output of X 2  is low at the end of a period of IN, the inverting output of X 5  goes high. AND gate X 7  generates a positive going pulse which turns on both M 11  and M 12  and resets both C 1  and C 2 , thus restoring normal operations. The circuit may spontaneously begin to operate without this circuitry, but its addition will ensure deterministic startup in minimum time. 
     Flip-flop X 6  is used to delay the output until the second cycle after a reset, corresponding to point B in FIG.  5 . This ensures correct operation of the circuit, eliminating a potentially incorrect output during the first cycle of operation after a reset. 
     Transistors M 9  and M 10  detect if either capacitor charges to the rail, indicating that the input clock has halted. Invertor X 7  thus provides an indication of the loss of the input signal. This feature can be used to engage an alternate oscillator circuit, which may be useful during the long startup time characteristic of low-power crystal oscillator circuits. 
     The paired charge-discharge oscillators generate linear ramp voltages, as shown FIG.  5 . The preferred embodiment of the innovative circuit is used to produce ramp voltages VR 1  and VR 2 . Both initially start from zero, at point A. VR 1  then charges for one period T of the input signal, to reach point B. 
     Next, VR 1  is discharged at the same rate of slew at which it was charged, and VR 2  is simultaneously charged at this same slew rate. The two ramps will intercept each other at point C. The time elapsed from point B to point C is T/ 2 . 
     Next, VR 1  is discharged rapidly to ground to prepare for the next cycle of operation. Because VR 1  is discharged quickly, it soon reaches zero within a very small. percentage of error D, which would not necessarily occur if the ramp continued down with the previously determined slope. This technique eliminates the potential for the ramp waveforms to gradually rise off of ground because of incomplete capacitor discharge. It also ensures that the ramp waveforms start from a known and fixed voltage, thus minimizing errors in ramp height due to overshoot or undershoot. 
     The operation of the circuit then continues, with VR 1  and VR 2  swapping roles. 
     This innovative circuit provides significant advantages over the prior art, including (but not limited to): 
     The innovative circuit can produce duty cycles other than 50% by appropriately rationing IC and ID. The relationship between the duty cycle d and the charge and discharge currents IC and ID can be determined from the basic capacitor equation CV=IT. Looking at FIG. 7, we see that voltage VR 1  across capacitor C 1  increases from time t=0 to time t=T as: 
     
       
         VR 1 =IC·T/C 1   
       
     
     From time t=T to time t=T(1+d), voltage VR 1  varies as: 
     
       
         VR 1 =IC·T/C 1 −ID·(t−T)/C 1   
       
     
     and the voltage VR 2  across capacitor C 2  varies as: 
     
       
         VR 2 =IC·(t−T)/C 2   
       
     
     If, at time t=T(1+d), VR 1 =VR 2 , then 
     
       
         VR 1 =IC·T/C 1 −ID·dT/C 1   
       
     
     
       
         VR 2 =IC·dT/C 2   
       
     
     
       
         (IC·T−dID·T)/C 1 =dIC·T/C 2   
       
     
     
       
         (IC−dID)/C 1 =dIC/C 2   
       
     
     Since C 1 =C 2 , 
     
       
         IC−dID=dIC 
       
     
     
       
         d(IC+ID)=IC 
       
     
     
       
         d=IC/(IC+ID) 
       
     
     As this equation indicates, 0&lt;d&lt;1. In practice, the minimum duty cycle will be slightly greater than 0 and the maximum duty cycle will be slightly less than 1 due to switching delays and the time required to fully discharge the capacitors. 
     An additional function of the preferred embodiment allows the circuit to produce a signal which will indicate the loss of the clock which feeds it. This is useful because crystal oscillators are slow to start and therefore an auxiliary RC oscillator can be substituted until the crystal is up and running. Furthermore, more current can be diverted to the crystal to get it started. Similarly, this feature can be used to indicate that more current is needed to drive an RC oscillator during shutdown. 
     This function was previously implemented using separate, dedicated circuitry, which can be eliminated from the present phase alignment circuit because the present preferred embodiment can perform this function itself. To do so, it is simply necessary to determine if either ramp exceeds a threshold voltage which would not be reached in time T; this indicates no input clock signal has arrived. This function is implemented using transistors M 9  and M 10  in combination with inverter X 7 . If the ramp on either capacitor C 1  or C 2  goes too high, signal LOST will indicate an error condition. 
     As described above, the aligner circuit is sensitive to one edge, e.g. the rising edge, of the incoming signal, and each capacitor is alternately charged for one full period of the incoming signal. The circuit may also easily be used as a clock doubler by making the innovative circuit sensitive to both the rising and falling edges of the input signal, by means known to one of ordinary skill in the art. This would force each capacitor to charge for one half-period of the input signal, and the resulting output would be a doubled clock signal with the selected duty cycle. 
     Alternate Embodiment: Aligner and Clock Multiplier 
     According to an alternative embodiment, it is also possible to connect two of the innovative circuits in series with the input signal, with one circuit connected to align the phase of the input signal, and the other circuit connected to multiply the frequency of the phasealigned signal. A block diagram of such a circuit is shown in FIG. 6, in which an oscillator circuit is. connected to a phase alignment circuit according to the preferred embodiment. This circuit is in turn connected to a second circuit according to the preferred embodiment, which is configured as a frequency multiplier. 
     Alternate Embodiment: Variable Duty Cycle 
     According to a further alternative embodiment, the values of the current sources to one or both of the capacitors may be varied to produce an output signal having a duty cycle more or less that 50%, as the target application requires. Typical applications of such a feature include charge pumps and some digital circuits. 
     According to a disclosed class of innovative embodiments, there is provided a phase-aligned oscillator system, comprising an oscillator stage connected to produce a first periodic signal; and a. phase alignment stage connected to receive said first periodic signal, and connected to produce a second signal with a precisely defined duty cycle, said phase alignment stage being slaved to said oscillator stage. 
     According to another disclosed class of innovative embodiments, there is provided a phase-aligned crystal oscillator system, comprising an oscillator stage connected to produce a first AC signal; a phase alignment stage connected to receive said first AC signal, and connected to alternately charge and discharge each of a pair of capacitors at a first rate according to transitions in said AC signal, and connected to produce an output signal which varies according to the voltage across each of said pair of capacitors; and wherein when the voltage across each of said pair satisfies a predefined criteria, the rate of discharge of said discharging one of said pair of capacitors is increased. 
     According to another disclosed class of innovative embodiments, there is provided a phase-alignment circuit, comprising first, second, third, and fourth current sources; a first capacitor connected to be charged by said first current source at a first charge rate and discharged by said second current source according to an input signal; a second capacitor connected to be charged by said third current source at said third charge rate and discharged by said fourth current source; control logic connected to said current sources to charge said second capacitor and discharge said first capacitor according to transitions in said input signal, and to discharge said first capacitor at a second rate, which is faster than said first rate, after the voltage across said first capacitor has equalled the voltage across said second capacitor; an output stage connected to produce an output signal according to the voltage across said first and second capacitors; wherein said first and second capacitors are alternately charged and discharged according to said input signal. 
     According to another disclosed class of innovative embodiments, there is provided a method for stabilizing an input signal, comprising the steps of: (a) charging a first capacitor at a first rate; (b) detecting a transition of said input signal, and then discharging said first capacitor at said first rate and charging a second capacitor at said first rate; (c) detecting when the voltage across said first capacitor equals the voltage across said second capacitor, and thereafter discharging said first capacitor at a second rate which is faster than said first rate; (d) repeating steps (b)-(c), reversing said first and second capacitors; (e) comparing the voltage across said first and second capacitors and producing a corresponding stabilized output signal. 
     Modifications and Variations 
     As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given.