Abstract:
A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method for erasing flash memory, and more particularly, to a method for erasing flash memory without over erasing. 
         [0003]    2. Description of the Related Art 
         [0004]    In order to change data of the flash memory, the data within the flash memory should be erased first and then reprogrammed. U.S. Pat. No. 7,130,240 discloses a method for erasing sectors of a flash memory in sequence. However, such method is time-consuming and will not fulfill the current needs of the industry. 
         [0005]    In addition, as the memory capacity of the flash memory increases, the time needed to erase will increase. To solve such problem, a technique for simultaneously erasing the selected memory blocks is required. However, the well-known issue of “slow bits” residing in each sector, which represent unsuccessfully erased bits after an erasing action, tend to slow down the entire process and reduce the reliability of the flash memory. The slow bits need greater than normal durations of erasing action to completely erase. At the same time, caution is needed to avoid other normal bits being redundantly erased, or “over erased.” If normal bits are over erased, more time is needed to correct them, and sometimes it is impossible to recover data lost due to heavily over-erased sectors. U.S. Pat. No. 5,841,721 discloses a method to verify whether the erasure is successfully performed. To avoid over erasing, this method verifies the multiple sectors after one erasing action. However, this method will naturally consume a lot of time on erasing verification. For example, there is a flag for each block, and the flag indicates if the block is selected for erasure. Erasure is performed on all selected blocks that do not pass verification. However, if the selected block passes verification, the flag is reset and no further erasure is performed on this block. Verification is then performed on all selected and unsuccessfully erased blocks. If subsequent blocks pass verification, their flags are reset, and no further erasure is performed on these blocks. 
         [0006]    U.S. Pat. No. 5,954,828 and U.S. Pat. No. 6,222,772 disclose another type of erasing methodology, which allows a number of failing bits and therefore some slow bits can be ignored. However, such method can only be applied on fault tolerant applications. 
       SUMMARY OF THE INVENTION 
       [0007]    The above-mentioned problems are addressed by the present invention. The method of the present invention will be understood according to the disclosure of the following specification and drawings. 
         [0008]    According to one embodiment of the present invention, the method for erasing a flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially. 
         [0009]    According to another embodiment of the present invention, the method for erasing a flash memory comprises the steps of: simultaneously erasing selected multiple sectors of the flash memory; verifying bits of one sector upon a predetermined condition; continually erasing selected multiple sectors of the flash memory simultaneously if the verification does not satisfy a critical ending condition; stopping simultaneous erasing if the verification satisfies the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The invention will be described according to the appended drawings in which: 
           [0011]      FIG. 1  shows a hint diagram of the present invention; 
           [0012]      FIG. 2  shows a flow chart of the present invention; 
           [0013]      FIG. 3A  shows a flow chart before the critical ending condition is met; and 
           [0014]      FIG. 3B  shows a flow chart after the critical ending condition is met. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]      FIG. 1  shows a hint diagram of the present invention. To avoid over erasing, it is necessary to avoid erasing normal bits of the flash memory several times after the erasing action is done merely because slow bits in each sectors fail to pass the verification. Because each sector in a flash memory is manufactured with the same process, it can be reasonably assumed that the normal bits and slow bits in each sector are formed in the same normal distribution. Therefore, a threshold or critical ending condition such as 3σ=0.3% is set to represent the region in which the slow bits may reside, where a represents a variance of the normal distribution. 
         [0016]    In multiple sector erasure, erasing is commenced for all of the selected sectors. When most of the bits in the first sector that meets the critical ending condition have passed erasure verification, the other sectors will then stop erasing. Because the remainder of the unsuccessfully erased bits may include slow bits, the second step of the erasing action proceeds with the sequence of the selected sectors one by one. 
         [0017]      FIG. 2  shows a flow chart of the present invention. In step S 201 , after the test mode is entered, a critical ending condition of the multi-sector erasure is set. In step S 202 , the multiple sectors are erased simultaneously. The present invention does not continuously monitor the passing rate of the first sector, but rather waits for an asserting value of a first counter, which represents the number of erasing actions performed. Therefore, the present invention may save a lot of time in conducting verification. However, if the verification is entered and finds that the passing rate of the first sector meets the critical ending condition, the concurrent erasing action will be stopped. Otherwise, the steps S 202  and S 203  iterate. The ideal critical ending condition can be determined by experiment or experience, and the critical ending condition is not limited to the passing rate. The record related to the critical ending condition, such as voltage potential and how many times to conduct the erasing actions, can be applied when erasing the other flash memories. In step S 204 , the remainder of each of the multiple sectors is erased in sequence. For example, the remainder of the first sector is erased first. Next, the remainder of the second sector is erased; then the third sector, and so on. 
         [0018]      FIG. 3A  shows a flow chart of the present invention. In step S 301 , the Least Significant Bit (LSB) positions of the sectors to be erased are located. A flag is used to indicate whether or not the critical ending condition is met. In step S 302 , if the flag is reset, then the flow goes to  FIG. 3B ; otherwise the flow keeps going between steps S 303  and S 304  to verify the content of the continuous addresses. Once a failure is reported, step S 305  will erase all selected sectors. In step S 306 , a first counter is used to track the number of erasing actions performed. And if the number reaches a predetermined value such as “n,” step S 310  will verify all bits in the first sector, then step S 311  resets the first counter. In step S 312 , if the failing bit count is less than a predetermined value, such as 3σ, which represents a critical ending condition, then step S 313  resets the flag and goes back to step S 301 . In addition, a second counter tracks the number of failures. In step S 309 , if the content of the second counter reaches a maximum value, which represents a time-out signal, step S 322  will report an error. 
         [0019]      FIG. 3B  shows the flow chart after the critical ending condition is met. Between steps S 314  and S 315 , the remainder of the first sector only is continually verified until passing the test. Similarly, any failure during the test will increase the content of the second counter which tracks errors, as shown in step S 320 . If the content thereof reaches a maximum number, a time-out signal was asserted, as shown in step S 319 . If the first sector is verified successfully, then the process is applied to the second sector, then the third sector, and so on, as shown in steps S 318  and S 321 . 
         [0020]    The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.