Abstract:
A mixer having high linearity and an associated transconductor combining programmable gain amplifier and mixer functions are provided. The transconductor includes first and second resistors, a differential amplifier, first and second feedback circuits, and first and second transistors. A differential voltage signal is inputted to first and second input ends of the differential amplifier via the first and second resistors. The first and second feedback circuits are provided between a first output end and the first input end, and a second output end and the second input end of the differential amplifier, respectively. The first output end outputs a first output signal for controlling a first current passing through the first transistor. The second output end outputs a second output signal for controlling a second current passing through the second transistor. The first current and the second current determine a differential current.

Description:
This application claims the benefit of U.S. Provisional Application No. 60/975,519 filed Sep. 27, 2007, which is herein incorporated by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a transconductor used in a mixer, and more particularly, to a mixer having high linearity and programmable gain. 
     BACKGROUND OF THE INVENTION 
     A mixer is commonly used as a frequency converting component in a wireless transceiver.  FIG. 1  shows a conventional wireless transceiver  10 . The wireless transceiver  10  comprises filters  11  and  12 , programmable gain amplifiers  13  and  14 , mixers  15  and  16 , and a power amplifier  17 . Given a baseband input signal I, for example, the baseband input signal I is filtered by the filter  11  to remove unwanted frequency components, amplified or attenuated using the programmable gain amplifier  13 , and transmitted into the mixer  15 . The baseband input signal I is then converted to a radio frequency specified by standards according to an oscillation signal LO I  generated by a local oscillator (not shown). Finally, the converted signal is amplified by the power amplifier  17  so as to proceed with wireless transmission. In the wireless transceiver  10 , frequency conversion performed by the mixers  15  and  16  plays a crucial role in determining signal quality of the wireless transmission. 
       FIG. 2  shows a circuit diagram of a conventional mixer. A Gilbert mixer  20  comprises a transconductor  21 , a switch quad  22  and a load circuit  23 . The load circuit  23  includes loads  231  and  232 . The loads  231  and  232  each has one end thereof coupled to a voltage supply Vcc, and the other end thereof being an output end. The switch quad  22  comprises NMOS transistors M 3 , M 4 , M 5  and M 6 . The drains of M 3  and M 5  are coupled to one end of the load  231 . The drains of M 4  and M 6  are coupled to one end of the load  232 . In addition, the gates of M 3  and M 6  are coupled to each other, and the gates of M 4  and M 5  are coupled to each other. The gates of M 3  and M 4  may receive a local oscillator signal LO. The sources of M 3  and M 4  are coupled to form a first current path. The sources of M 5  and M 6  are coupled to form a second current path. 
     The transconductor  21  comprises NMOS transistors M 1  and M 2 . The drain of M 1  is coupled to the first current path of the switch quad  22 . The drain of M 2  is coupled to the second current path of the switch quad  22 . The gates of M 1  and M 2  receive voltage signals Vin +  and Vin − , respectively. The sources of M 1  and M 2  are coupled to each other. Between the source of M 1  and a ground terminal is an NMOS transistor MS. The gate of transistor MS is inputted with a constant voltage to facilitate the transistor MS in forming a current source. 
       FIG. 3  shows a schematic diagram of signals associated with the mixer  20 . The transconductor  21  converts a differential input voltage signal Vin, that is, Vin +  or Vin − , to a current signal Ib. When passing through the first current path and the second current path of the switch quad  22 , the current signal Ib is driven by the oscillator signal LO to generate a frequency-converted current signal. The frequency-converted current signal is next converted by the load circuit  23  to generate an output voltage at the output end. 
     The transconductor  21  consists of the NMOS transistors M 1  and M 2 , and therefore a voltage-current relationship of the transconductor  21  is a conic relationship rather than a linear relationship. To be more specific, the prior art mixer shown in  FIG. 2  is unsuitable for applications on mixers that are in need of high linearity, such as in Wireless Local Access Network (WLAN) transmitters and Code Division Multiple Access (CDMA) system transmitters. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing reasons, an object of the invention is to provide a mixer having high linearity and an associated transconductor, which minimize the non-linearity issue occurring in a transconductor of a conventional mixer. 
     Another object of the invention is to provide a mixer having high linearity and a programmable gain, and an associated transconductor, which together provide functions of a programmable gain amplifier and a mixer to reduce power consumption as well as die size. 
     A mixer according to the invention comprises a load circuit, a switch quad, and a transconductor. The switch quad is coupled to the load circuit, and comprises a first current path and a second current path. A node where the switch quad is coupled to the load circuit is an output end of the mixer. The transconductor comprises a first resistor and a second resistor; a differential amplifier comprising a first input end, a second input end, a first output end, and a second output end, wherein a differential voltage signal is inputted to the first input end and the second input end via the first resistor and the second resistor, respectively; a first feedback circuit, provided between the first output end and the first input end; a second feedback circuit, provided between the second output end and the second input end; a first transistor, having the drain thereof coupled to the first current path and the gate thereof coupled to the first output end of the differential amplifier, wherein the first output end outputs a first output signal for controlling a first current passing through the first transistor; and a second transistor, having the drain thereof coupled to the second current path and the gate thereof coupled to the second output end of the differential amplifier, wherein the second output end outputs a second output signal for controlling a second current passing through the second resistor. The first current and the second current determine a differential current. 
     A transconductor according to the invention for use in a mixer comprises a first resistor and a second resistor; a differential amplifier comprising a first input end, a second input end, a first output end, and a second output end, wherein a differential voltage signal is inputted to the first input end and the second input end via the first resistor and the second resistor, respectively; a first feedback circuit, provided between the first output end and the first input end; a second feedback circuit, provided between the second output end and the second input end; a first transistor, having the drain thereof coupled to the first current path and the gate thereof coupled to the first output end of the differential amplifier, wherein the first output end outputs a first output signal for controlling a first current passing through the first transistor; and a second transistor, having the drain thereof coupled to the second current path and the gate thereof coupled to the second output end of the differential amplifier, wherein the second output end outputs a second output signal for controlling a second current passing through the second resistor. The first current and the second current determine a differential current. 
     According to one embodiment of the invention, the first feedback circuit of the transconductor comprises a third transistor, which has the gate thereof coupled to the first output end of the differential amplifier and forms a first current mirror with the first transistor; and the second feedback circuit comprises a fourth transistor, which has the gate thereof coupled to the second output end of the differential amplifier and forms a second current mirror with the second transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  is a schematic diagram of a conventional wireless transmitter. 
         FIG. 2  is a circuit diagram of a conventional mixer. 
         FIG. 3  shows a schematic diagram of signals associated with a conventional mixer. 
         FIG. 4  shows a circuit diagram of a mixer according to a first embodiment of the invention. 
         FIG. 5  shows an equivalent circuit diagram of a differential small signal model according to the first embodiment. 
         FIG. 6  shows a circuit diagram of a mixer according to a second embodiment of the invention. 
         FIG. 7  shows a circuit diagram of a mixer according to a third embodiment of the invention. 
         FIG. 8  shows a circuit diagram of a mixer according to a fourth embodiment of the invention. 
         FIG. 9  shows a circuit diagram of a mixer according to a fifth embodiment of the invention. 
         FIG. 10  shows a circuit diagram of a mixer according to a sixth embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       FIG. 4  shows a circuit diagram of a mixer according to a first embodiment of the invention. A mixer  40  comprises a transconductor  41 , a switch quad  42  and a load circuit  43 . The load circuit  43  comprises the loads  431  and  432 . Each of the loads  431  and  432  has one end thereof coupled to a voltage supply Vcc, and the other end thereof being an output end. In the switch quad  42 , the sources of transistors M 11  and M 12  are coupled to form a first current path. The sources of transistors M 13  and M 14  are coupled to form a second current path. 
     The transconductor  41  comprises resistors R 1 , R 2 , RB, R 1 ′, R 2 ′ and RB′, a differential amplifier  413 , and current mirrors  411  and  412 . The current mirror  411  comprises NMOS transistors M 2  and M 4 . The transistors M 2  and M 4  have the drains thereof coupled to each other, and sources thereof coupled to ground. The drain of the transistor M 2  is a control current end of the current mirror  411 . The drain of the transistor M 4  is a mirror current end of the current mirror  411 . A length-width ratio of M 2  and M 4  is 1:N, where N is a positive number. In terms of operation, the gate of the transistor M 2  serves as an input end of the current mirror  411  to receive a control signal, which is an output signal from the positive output end of the amplifier  413 . Accordingly, a corresponding control current is generated at the control current end, which is the drain of the transistor M 2 ; whereas a mirror current is generated at the mirror current end, which is the drain of the transistor M 4 . Amplitude of the mirror current is N-fold of the control current. 
     Symmetrically, the current mirror  412  comprises NMOS transistors M 1  and M 3 . The transistors M 1  and M 3  have the drains thereof coupled to each other, and sources thereof coupled to ground. The drain of the transistor M 1  is a control current end of the current mirror  412 . The drain of the transistor M 3  is a mirror current end of the current mirror  412 . A length-width ratio of the transistors M 1  and M 3  is 1:N, where N is a positive number. In terms of operation, the gate of the transistor M 1  serves as an input end of the current mirror  411  to receive a control signal, which is an output signal from the negative output end of the amplifier  413 . Accordingly, a corresponding control current is generated at the control current end, which is the drain of the transistor M 1 ; whereas a mirror current is generated at the mirror current end, which is the drain of the transistor M 3 . Amplitude of the mirror current is N-fold of the control current. 
     The resistors R 1  and R 1 ′ have one end thereof coupled to the positive input end and the negative input end of the differential amplifier  413 , respectively, and the other end thereof for receiving an input differential voltage signal Vin. The resistor R 2  is coupled between the positive end of the differential amplifier  413  and the drain of the transistor M 2 . The resistor R 2 ′ is coupled between the negative end of the differential amplifier  413  and the drain of the transistor M 1 . The resistor RB is coupled between the drain of the transistor M 2  and a voltage supply VB. The resistor RB′ is coupled between the drain of the transistor M 1  and the voltage supply VB. The gates of the transistors M 2  and M 1  are coupled to the positive output end and the negative output end of the differential amplifier  413 , respectively. The drains of the transistors M 4  and M 3  are coupled to the first current path and the second current path of the switch quad  42 , respectively. Using control signals outputted from the positive output end and the negative output end of the differential amplifier  413 , the gates of the transistors M 4  and M 3  are controlled, respectively, so as to form a differential current by the currents passing through the transistors M 4  and M 3 . In the transconductor  41 , a first feedback circuit is formed between the positive output end and the positive input end of the differential amplifier  413 . The first feedback circuit includes the transistor M 2 , and the resistors RB and R 2 . A second feedback circuit is formed between the negative output end and the negative input end of the differential amplifier  413 . The second feedback circuit includes the transistor M 1 , and the resistors RB′ and R 2 ′. Both the first and second feedback circuits provide negative feedback to assist the transconductor  41  in providing linear transconductance, as to be described below. For the reason that the mixer  40  is a fully differential circuit, resistor R 1 =resistor R 1 ′, resistor R 2 =resistor R 2 ′, resistor RB=resistor RB′, transistor M 1 =transistor M 2 , and transistor M 3 =transistor M 4 . 
       FIG. 5  shows an equivalent circuit diagram of a differential small signal model of the first embodiment shown in  FIG. 4 . The voltage supply VB is regarded as ground, and the resistors RB and RB′ are combined as  2 RB. The circuit in  FIG. 5  is analyzed as follows: 
     Voltage of point C is: 
     
       
         
           
             
               V 
               C 
             
             = 
             
               
                 
                   V 
                   A 
                 
                 - 
                 
                   
                     i 
                     2 
                   
                   × 
                   
                     R 
                     2 
                   
                 
               
               = 
               
                 
                   V 
                   A 
                 
                 - 
                 
                   
                     
                       
                         V 
                         
                           i 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           n 
                         
                         + 
                       
                       - 
                       
                         V 
                         A 
                       
                     
                     
                       R 
                       1 
                     
                   
                   × 
                   
                     R 
                     2 
                   
                 
               
             
           
         
       
     
     Voltage of point D is: 
     
       
         
           
             
               V 
               D 
             
             = 
             
               
                 
                   V 
                   E 
                 
                 - 
                 
                   
                     i 
                     1 
                   
                   × 
                   
                     R 
                     2 
                   
                 
               
               = 
               
                 
                   V 
                   E 
                 
                 - 
                 
                   
                     
                       
                         V 
                         
                           i 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           n 
                         
                         - 
                       
                       - 
                       
                         V 
                         E 
                       
                     
                     
                       R 
                       1 
                     
                   
                   × 
                   
                     R 
                     2 
                   
                 
               
             
           
         
       
     
     Points A and E are two input ends of the differential amplifier  413 , hence a voltage V A  is considered the same as a voltage V E . 
     Therefore, 
     
       
         
           
             
               i 
               B 
             
             = 
             
               
                 
                   
                     V 
                     D 
                   
                   - 
                   
                     V 
                     C 
                   
                 
                 
                   2 
                   ⁢ 
                   
                     R 
                     B 
                   
                 
               
               = 
               
                 
                   
                     
                       
                         V 
                         
                           i 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           n 
                         
                       
                       
                         R 
                         1 
                       
                     
                     × 
                     
                       R 
                       2 
                     
                   
                   
                     2 
                     ⁢ 
                     
                       R 
                       B 
                     
                   
                 
                 = 
                 
                   
                     V 
                     
                       i 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       n 
                     
                   
                   × 
                   
                     
                       R 
                       2 
                     
                     
                       2 
                       ⁢ 
                       
                         R 
                         1 
                       
                       ⁢ 
                       
                         R 
                         B 
                       
                     
                   
                 
               
             
           
         
       
     
     In addition, i M2 =i 2 +i B  and i M1 =i 1 −i B , hence 
     
       
         
           
             
               
                 
                   Ib 
                   = 
                   
                     
                       i 
                       
                         M 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         4 
                       
                     
                     - 
                     
                       i 
                       
                         M 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         3 
                       
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     N 
                     ⁡ 
                     
                       ( 
                       
                         
                           i 
                           
                             M 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         - 
                         
                           i 
                           
                             M 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                       ) 
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     N 
                     ⁡ 
                     
                       ( 
                       
                         
                           i 
                           2 
                         
                         - 
                         
                           i 
                           1 
                         
                         + 
                         
                           2 
                           ⁢ 
                           
                             i 
                             B 
                           
                         
                       
                       ) 
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     N 
                     ( 
                     
                       
                         
                           
                             V 
                             
                               i 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               n 
                             
                             + 
                           
                           - 
                           
                             V 
                             A 
                           
                         
                         
                           R 
                           1 
                         
                       
                       - 
                       
                         
                           
                             V 
                             
                               i 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               n 
                             
                             - 
                           
                           - 
                           
                             V 
                             E 
                           
                         
                         
                           R 
                           1 
                         
                       
                       + 
                       
                         2 
                         ⁢ 
                         
                           V 
                           
                             i 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             n 
                           
                         
                         × 
                         
                           
                             R 
                             2 
                           
                           
                             2 
                             ⁢ 
                             
                               R 
                               1 
                             
                             ⁢ 
                             
                               R 
                               B 
                             
                           
                         
                       
                     
                     ) 
                   
                 
               
             
             
               
                 
                   = 
                   
                     Vin 
                     × 
                     
                       N 
                       ( 
                       
                         
                           1 
                           
                             R 
                             1 
                           
                         
                         + 
                         
                           
                             R 
                             2 
                           
                           
                             
                               R 
                               1 
                             
                             ⁢ 
                             
                               R 
                               B 
                             
                           
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
     
     As a result, the output current Ib and the input voltage Vin of the transconductor  41  show a linear relationship. To be more explicit, the transconductor  41  has linear transconductance. In addition, provided at least one of the resistors R 1 , R 2  and RB is a variable resistor, the transconductor  41  consequently has a programmable gain 
               N   (       1     R   1       +       R   2         R   1     ⁢     R   B           )     .         
Therefore, using the transconductor  41 , the mixer  40  is provided with high linearity and programmable gain, while being capable of performing functions of a mixer and a programmable gain amplifier to reduce power consumption and die size.
 
       FIG. 6  shows a circuit diagram of a mixer according to a second embodiment of the invention. A difference between a mixer  60  in  FIG. 6  from the mixer  40  in  FIG. 5  is the bias voltage configuration of the resistors RB and RB′. In a transconductor  61 , the resistor RB is coupled between the drain of the transistor M 2  and a current source Id, and the resistor RB′ is coupled between the drain of the transistor M 1  and the current source Id. In  FIG. 6 , if the mixer  60  is converted to an equivalent circuit in a differential small signal model, that is, the current source Id is regarded as a circuit breaker and the resistors RB and RB′ are combined to  2 RB, the equivalent circuit of the small signal model is the same as that of  FIG. 5 . As a result, in the second embodiment shown in  FIG. 6 , the output current Ib and the input voltage Vin of the transconductor  61  have a relationship identical to that of the first embodiment. In other words, the mixer  60  has high linearity and programmable gain. 
       FIG. 7  shows a circuit diagram of a mixer according to a third embodiment of the invention. A difference between a mixer  70  in  FIG. 7  from the mixer  40  in  FIG. 5  is the bias voltage configuration of the resistors RB and RB′. In a transconductor  71 , the resistors RB and RB′ are combined as a resistor  2 RB. The resistor  2 RB has one end thereof coupled to a node where the drain of the transistor M 2  is coupled to the current source I 1 , and the other end thereof coupled to a node where the drain of the transistor M 1  is coupled to the current source I 2 . Accordingly, if the mixer  70  in  FIG. 7  is converted to an equivalent circuit in a differential small signal model, that is, the current sources I 1  and I 2  are regarded as circuit breakers, the equivalent circuit of the small signal model is the same as that of  FIG. 5 . As a result, in the third embodiment shown in  FIG. 7 , the output current Ib and the input voltage Vin of the transconductor  71  have a relationship identical to that of the first embodiment. In other words, the mixer  70  has high linearity and programmable gain. 
       FIG. 8  shows a circuit diagram of a mixer according to a fourth embodiment of the invention. In  FIG. 8 , an implementing circuit of the differential amplifier  413  of the mixer  40  in  FIG. 4  is shown. The differential amplifier  413  in  FIG. 8  comprises a current source I 1 , NMOS transistors M 5  and M 6 , PMOS transistors M 7  and M 8 , resistors RF and RF′, and compensation capacitors C 1  and C 1 ′, Transistors M 8  and M 7  have the sources thereof coupled to the current source I 1 ; the gates thereof being the positive input end and negative input end of the differential amplifier  413 , respectively; and the drains thereof being the negative output end and positive output end of the differential amplifier  413 , respectively, and coupled to the input end of the current mirror  412  and the input end of the current mirror  411 , respectively. The drain of the transistor M 8  is coupled to the drain of the transistor M 5 . The drain of the transistor M 7  is coupled to the drain of the transistor M 6 . The gates of the transistors M 6  and M 5  are coupled to each other. The sources of the transistors M 6  and M 5  are both coupled to ground. The resistor RF is coupled between the gate and the drain of the transistor M 6 . The resistor RF′ is coupled between the gate and the drain of the transistor M 5 . The compensation capacitor C 1  is coupled between the drain of the transistor M 6  and ground. The compensation capacitor C 1 ′ is coupled between the drain of the transistor M 5  and ground. Accordingly, the differential amplifier  413  is allowed to function normally. For the reason that the differential amplifier  413  is a fully differential circuit, resistor RF=resistor RF′, capacitor C 1 =capacitor C 1 ′, transistor M 5 =transistor M 6 , and transistor M 7 =transistor M 8 . 
     In the differential amplifier  413  in  FIG. 8 , a common-mode voltage is accomplished by large resistors RF and RF′. An advantage of such implementation is that, by using self-bias, circuit operation stability is maintained without additionally connecting to a common-mode feedback circuit, so as to simply an entire circuit and lower hardware cost. Further, large resistors RF and RF′ may increase gain of the differential amplifier  413 . 
       FIG. 9  shows a circuit diagram of a mixer according to a fifth embodiment of the invention. In  FIG. 9 , an implementing circuit of the differential amplifier  413  of the mixer  70  in  FIG. 7  is shown. In  FIG. 9 , the implementing circuit of the differential amplifier  413  is identical to that of the amplifier  413  in  FIG. 8 . 
       FIG. 10  shows a circuit diagram of a mixer according to a sixth embodiment of the invention. In  FIG. 10 , an implementing circuit of the current sources  12  and  13  of the mixer  70  in  FIG. 9  is shown. Further, a common-mode feedback circuit is coupled to configure an operating point of a direct current outputted from the transconductor. In a mixer  90  in  FIG. 10 , a transconductor  91  comprises NMOS transistors M 10  and M 9  as the current I 2  and I 3 , respectively. An operational amplifier A 1  has an output end thereof coupled to the gates of the transistors M 10  and M 9 , the positive end thereof coupled to a coupling point of the resistors RB and RB′, and the negative end thereof for inputting a DC common-mode voltage VCM, so as to form a common-mode feedback circuit. 
     It is to be noted that the transconductor according to the first to sixth embodiments may be implemented in various circuits other than mixers, and therefore the various circuits are regarded as different versions within the invention. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not to be limited to the above embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.