Abstract:
The present invention proposes a multi-port memory device for preventing a degradation of a global data drive efficiency by turning off the switches which do not discharge a global data bus. The multi-port memory device includes a global data bus containing a plurality of bus lines; a plurality of banks including a transmitter and a receiver for exchanging a data with the global data bus; a plurality of ports including the transmitter and the receiver; a plurality of switches for selectively connecting the transmitter and the receiver with the global data bus; and a switching controller for generating a switch signal in response to a drive pulse and a data signal inputted to the transmitter, wherein the switch signal turns off the switches corresponding to the banks which are not discharging the global data bus.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a multi-port memory device; and, more particularly, to a multi-port memory device for performing an effective data transmission. 
   DESCRIPTION OF PRIOR ART 
   Most memory devices including DRAM contain a single port for exchanging data with a chipset. Herein, the single port usually includes a plurality of I/O pin sets. Meanwhile, a functional classification of the chipset and the memory device becomes more ambiguous; and, therefore, it is seriously considered to integrate the memory device and the chipset. In order to satisfy the integration, a multi-port memory device for directly exchanging data with peripheral devices such as a graphic device and a CPU is required. For implementing the multi-port memory device, every port in the multi-port memory device has access to every memory cell in the multi-port memory device. 
     FIG. 1  is a block diagram describing a 256M multi-port memory device disclosed in a commonly owned copending application, U.S. Ser. No. 10/750,156, filed on Dec. 31, 2003, entitled “MULTI-PORT MEMORY DEVICE”, which is incorporated herein by reference. 
   As shown, the 256M multi-port memory device includes a plurality of banks BANK 0  to BANK 15 , a plurality of row decoders RDEC, an controller  100 , a plurality of ports PORT 0  to PORT 7 , a first to fourth global data buses GIO_LU, GIO_RU, GIO_LD, and GIO_RD, a first and second global data bus connectors PR_U and PR_D, a plurality of transfer buses TBs, a plurality of transfer bus connectors TGs, a plurality of bus connectors TLs, and a plurality of data transfer units QTRXs. 
   Each of the banks BANK 0  to BANK 15  includes an 8K×2K DRAM, i.e., 16M DRAM, the row decoder RDEC, and a core circuit such as a sense amplifier and an equalizer which are necessary for general DRAM core area. Every four banks of the banks BANK 0  to BANK 15  are arranged in a row at a corresponding quadrant dividing the core area into four. In the concrete, there are included BANK 0 , BANK 2 , BANK 4 , and BANK 6  in a first quadrant placed in an upper left side of the core area. BANK 8 , BANK 10 , BANK 12 , and BANK 14  are in a second quadrant placed in an upper right side of the core area. BANK 1 , BANK 3 , BANK 5 , BANK 7  are in a third quadrant placed in a lower left side of the core area. BANK 9 , BANK 11 , BANK 13 , and BANK 15  are in a fourth quadrant placed in a lower right side of the core area. Meanwhile, it is advisable to arrange the two row decoders RDEC between each neighboring banks in the same quadrant. Further, a column of the banks BANK 0  to BANK 15  is divided into four segments. Thus, each of the four segments is constituted with 512 cells. 
   The controller  100  generates an internal command signal, an internal address signal, and a control signal to thereby control an operation of the memory device. The internal command signal includes an internal active command signal ACT, an internal precharge command signal PCG, an internal read command signal RD, and an internal write command signal WD. The internal address signal includes an active array address AAA, a precharge array address PAA, a read array address RAA, a write array address WAA, a row address RA, a read segment address RSA, and a write segment address WSA. The control signal includes transfer gate control signal TGC, a port/pipe register flag signal PRFG, a port/pipe register data driving signal DP, and a DRAM core test mode flag signal DTM. 
   The ports PORT 0  to PORT 7  are placed at the margin of a die. Every two ports of the ports PORT 0  to PORT 7  are arranged to each of the quadrants. In detail, PORT 0  and PORT 2  are in the first quadrant; PORT 4  and PORT 6  are in the second quadrant; PORT 1  and PORT 3  are in the third quadrant; PORT 5  and PORT 7  are in the fourth quadrant. Each of the ports PORT 0  to PORT 7  supports a serial I/O interface and communicates independently with a different target device such as a graphic chip. When the ports PORT 0  to PORT 7  support the serial I/O interface, every port has a plurality of pads corresponding to data, commands, and addresses, a plurality of pad buffers for buffering a signal transmitted to the pads, a decoder for decoding a data to be transmitted, an encoder for encoding a received data, and data transformer for transforming the serial received data into a parallel data or transforming the parallel data into a serial data. 
   The first to fourth global data buses GIO_LU, GIO_RU, GIO_LD, and GIO_RD are placed between the bank and the port of the corresponding quadrants, respectively. In detail, the first global data bus GIO_LU is in the first quadrant; the second global data bus GIO_RU is in the second quadrant; the third global data bus GIO_LD is in the third quadrant; the fourth global data bus GIO_RD is in the fourth quadrant. The first to fourth global data buses GIO_LU, GIO_RU, GIO_LD, and GIO_RD are 512-bit bidirectional data buses coupled to the banks and the ports of the corresponding quadrant and the first and the second global data bus connectors PR_U and PR_D. 
   Herein, the first global data bus GIO_LU and the second global data bus GIO_RU are connected through the first global data bus connector PR_U. The third global data bus GIO_LD and the fourth global data bus GIO_RD are connected through the second global data bus connector PR_D. The first and second global data bus connector PR_U and PR_D include 512 numbers of bidirectional pipe registers corresponding to the 512-bit global data buses. 
   The transfer bus TB is a local data bus connecting a bit line sense amplifier and the bus connectors TL of the corresponding bank. The number of lines of the transfer bus TB is corresponding to the number of cells in one segment, e.g., 512. The transfer bus TB is implemented with a differential bus. 
   The transfer bus connector TG is implemented with a plurality of MOS transistors. The number of the MOS transistors is corresponding to the number of lines of the transfer bus TB. Because the transfer bus TB is a differential bus, one transfer bus connector TG is implemented with 512 pairs of MOS transistors. Accordingly, the transfer bus connector TG is called a transfer gate. 
   One set of transfer latch is formed with 512 numbers of transfer latches. The bus connector TL includes 16 sets of transfer latches. Each transfer latch includes a first bus connecting circuit for a read operation and a second bus connecting circuit for a write operation. Herein, the first bus connecting circuit corresponding to an I/O sense amplifier of DRAM and includes a read sense amplifier for sensing and latching a read data on the transfer bus TB and a read driver for driving the latched read data into the global data bus of the corresponding quadrant. Further, the second bus connecting circuit corresponding to a write driver of DRAM includes a write latch for sensing and latching a write data on the global data bus and a write driver for driving a write data into the transfer bus TB. 
   The data transfer unit QTRX includes 512 numbers of transmitters QTX for transmitting a write data inputted to a corresponding port and 512 numbers of receivers QRX for receiving a read data inputted from the global data bus to thereby transmit to a corresponding port. 
   Besides, although not shown in  FIG. 1 , the 256M multi-port DRAM further includes a voltage generator, a test logic, and various pads including a clock pad (not shown). The voltage generator placed at the margin of the 256M multi-port DRAM receives an external voltage to thereby generate an internal voltage. The test logic is arranged between the ports corresponding to the first quadrant and the second quadrant and arranged between the ports corresponding to the third quadrant and the fourth quadrant. The pads are also placed at the margin of the 256M multi-port DRAM. 
   Further, each of the quadrants includes command lines for receiving the internal command signals and 2-bit address lines for receiving the internal address lines (not shown). The command lines and the address lines deliver from the controller  100  to the banks BANK 0  to BANK 15 . At each of left and right side of the controller  100 , a 4-bit transfer gate control line TGC&lt; 0 : 3 &gt; reaching from the controller  100  and to the transfer bus connector TG is exist (not shown). 
     FIG. 2  is a block diagram showing a relationship between the transfer bus and the segment, i.e., a column unit of the 256M multi-port DRAM shown in  FIG. 1 . 
   As shown, the 256M multi-port DRAM includes a memory cell array  200  and a bit line sense amplifier array  210 . Referring to a block denoted as A, one transfer bus pair TB&lt; 0 &gt; and TBb&lt; 0 &gt; of the memory cell array  200  are connected to four bit line sense amplifiers BLSA arranged upper and lower side of the memory cell array  200 . The four bit line sense amplifier BLSA are controlled by a segment select signal SGS&lt; 0 : 3 &gt;, respectively. Herein, the segment select signal SGS is corresponding to a column select signal of the conventional DRAM. In case of 2K column, when a predetermined row and a predetermined segment are selected at a time, 512 cells are selected and data of the 512 cells are transferred into the 512-bit transfer bus TB&lt; 0 : 511 &gt; corresponding to the 512 cells. 
   Each of transfer buses TB in the first quadrant is connected to a corresponding transfer bus TB in the third quadrant through the transfer gate TG. Herein, one set of the transfer gate is constituted with 512 transfer gates TG and eight sets of transfer gates TG are provided in the 256M multi-port DRAM. That is, the transfer gate is placed between two transfer buses TB, each corresponding to two banks arranged in the same column to thereby selectively connect the two transfer buses TB to each other. The transfer gate control signal TCG for controlling the transfer gate TG is generated in the controller  100 . 
   Hereinafter, an operation of the 256M multi-port DRAM is explained. 
     FIGS. 3A and 3B  are block diagrams describing a normal read path and a normal write path of the 256M multi-port DRAM, respectively. 
   Herein, the normal read and write paths refer to data paths of the read and the write operations occurred in same quadrant. For example, under the case of the normal read and write paths, the commands and addresses for the read or write operation inputted through a port in the first quadrant, i.e., the first port PORT 1  or the third port PORT 2 , are only able to access the memory cells in the first quadrant. 
   As shown in  FIG. 3A , when the 256M multi-port DRAM reads a 512-bit read data of a predetermined segment in the first bank BANK 0  through the first port PORT 0 , the commands and addresses relating to the read operation are inputted to the controller  100  in a form of packet through the first port PORT 0 . The controller  100  generates the internal active command signal ACT, the active array address AAA, and the row address RA corresponding to the first bank BANK 0  to thereby activate a predetermined row, i.e., a word line WL, in the first bank BANK 0 . Then, the controller  100  generates the read command signal RD, the read array address RAA, and read segment address RSA corresponding to the first bank BANK 0 . The bit line sense amplifier BLSA senses and amplifies the 512-bit read data of a segment corresponding to the read segment address RSA to thereby transfer the 512-bit read data to the pair of transfer bus TB and TBb. 
   Meanwhile, the bus connector TL of the first bank BANK 0  senses the 512-bit read data loaded on the pair of transfer bus TB and TBb and, then, transmits the 512-bit read data to the first global data bus GIO_LU. Subsequently, the 512-bit read data transmitted to the first global data bus GIO_LU is buffered in a read buffer of the first port PORT 0  after passing through the receiver QRX of the data transfer unit QTRX corresponding to the first port PORT 0 . The 512-bit read data in read buffer is transformed to packets of a predetermined size and serially transmitted to a target device connected to the first port PORT 0 . 
   Next, the controller  100  generates the internal precharge command signal PCG and the precharge array address PAA to thereby inactivates the word line WL. The transfer bus connector TG corresponding to the internal precharge command signal PCG and the precharge array address PAA is switched-off. Therefore, the transfer bus pair TB and TBb of the first bank BANK 0  and the transfer bus pair TB and TBb of the second band BANK 1  are disconnected. Herein, in  FIG. 3A , BL and BLb denote a bit line pair; T denotes a cell transistor; and C denotes a cell capacitor. 
   Hereinafter, a case which the 256M multi-port DRAM writes a 512-bit write data to a predetermined segment in the first bank BANK 0  through the first port PORT 0  is explained by referring  FIG. 3B . 
   As shown, after the commands and addresses relating to the write operation and the 512-bit write data are inputted to the controller  100  in a packet form through the first port PORT 0 , the controller  100  generates the internal active command signal ACT, the active array address AAA, and the row address RA corresponding to the first bank BANK 0  to thereby activate a predetermined row, i.e., a word line WL, in the first bank BANK 10 . Then, the controller  100  generates the internal write command signal WD, the write array address WAA, and the write segment address WSA corresponding to the first bank BANK 0 . 
   The 512-bit write data buffered in a write buffer of the first port PORT 0  is written to the segment corresponding to the write segment address WSA in accordance with a scheduling of the controller  100 . That is, the 512-bit write data transformed into a parallel data is loaded to the first global data bus GIO_LU through the transmitter QTX of the data transfer units QTRX. Then, the 512-bit write data is loaded to the pair of the transfer bus TB and TBb after passing through the bus connector TL of the first bank BANK 0 . Subsequently, the 512-bit write data loaded in the pair of the transfer bus TB and TBb is stored in 512 numbers of memory cells, i.e., the segment, by the bit line sense amplifier BLSA corresponding to the write segment address WSA. 
   Finally, the controller  100  generates the internal precharge command signal PCG and the precharge array address PAA to thereby inactivate the word line. 
     FIGS. 4A and 4B  are block diagrams describing a cross read path and a cross write path of the 256M multi-port DRAM, respectively. 
   Herein, the cross read and write paths refer to data paths of the read and the write operations occurred between different quadrants, respectively. For example, under the case of the cross read and write paths, it is possible to access the memory cells in the third quadrant for the commands, addresses, and data inputted through the first port PORT 0  in the first quadrant. 
   As shown in  FIG. 4A , when the 256M multi-port DRAM reads a 512-bit read data of a predetermined segment in the first bank BANK 0  through the second port PORT 1 , the whole operations are similar to that of the case of the normal read path. However, the transfer bus connector TG coupled between the first and the second banks BANK 0  and BANK 1  is switched-on and, therefore, the pair of the transfer bus TB and TBb of the first bank BANK 0  and the pair of the transfer bus TB and TBb of the second bank BANK 1  are connected to each other. The 512-bit read data is loaded to the transfer bus pair TB and TBb of the second bank BANK 1  and transmitted to a target device after passing through the bus connectors TL connected to the second bank BANK 1 , the third global data bus GIO_LD, the data transfer unit QTRX connected to the second port PORT 1 , and the second port PORT 1 . 
   Next, a case that the 256M multi-port DRAM writes a 512-bit write data to a predetermined segment in the first bank BANK 0  through the second port PORT 1  is explained, referring to  FIG. 4B . 
   As shown, the whole operations are similar to that of the normal write path. However, the transfer bus connector TG coupled between the first and the second banks BANK 0  and BANK 1  is switched-on; and, therefore, the transfer bus pair TB and TBb of the first bank BANK 0  and the pair of the transfer bus TB and TBb of the second bank BANK 1  are connected. In this case, the 512-bit write data inputted through the second port PORT 1  is loaded on the transfer bus pair TB and TBb of the first bank BANK 0  after passing through the data transfer unit QTRX connected to the second port PORT 1 , the third global data bus GIO_LD, the bus connectors TL connected to the second bank BANK 1 . The process thereafter is same with that of the normal write. 
   Meanwhile, when the data is transmitted between the first and the second global data buses GIO_LU and GIO_RU, the first and the second global data buses GIO_LU and GIO_RU are connected via the first global data bus connector PR_U. Further, when the data is transferred between the third and the fourth global data buses GIO_LD and GIO_RD, the third and the fourth global data buses GIO_LD and GIO_RD are connected through the second global data bus connector PR_D. 
   As abovementioned, every port PORT 0  to PORT 7  in the conventional 256M multi-port memory device can access to every segment in the conventional 256M multi-port memory device. Further, because each of the ports PORT 0  to PORT 7  accesses to the segment independently, the segment can be concurrently accessed by plural ports PORT 0  to PORT 7  as long as each of the first to the fourth global buses GIO_LU to GIO_RD are not used concurrently. Moreover, the data is inputted or outputted serially between the ports PORT 0  to PORT 7  and the target device and the 512-bit data is processed in parallel manner between the ports PORT 0  to PORT 7  and each quadrant of the core area. Thus, the present invention makes it possible to minimize a layout size, facilitate a package, and increase a bandwidth without causing a skew between data lines in a data bus. 
     FIG. 5  is a diagram showing a data transmitting structure of the 256M multi-port DRAM shown in  FIG. 1 . 
   As shown, the 256M multi-port DRAM includes a global data bus GIO for use in exchanging a data between an input/output interface, i.e., a port and a memory cell block, i.e., a bank. Further, the 256M multi-port DRAM also includes a data transfer units QTRX for receiving or transmitting a data between the global data bus GIO and the port and a bus connectors TL for receiving or transmitting a data between the global data bus GIO and the bank. 
     FIG. 6  is a block diagram describing a structure of the global data bus GIO shown in  FIG. 5 . 
   As shown, the 256M multi-port DRAM is divided into four quadrants QUADRANT_LU, QUADRANT_RU, QUADRANT_LD, and QUADRANT_RD. Each of the four quadrants has the same structure and operates independently. 
   Looking at the first quadrant QUADRANT_LU, the first global data bus GIO_LU is connected to four banks BANK 0 , BANK 2 , BANK 4 , and BANK 6 , two ports PORT 0  and PORT 2 , and the first global data bus connector PR_U. That is, seven blocks are connected to one global data bus. When a global data is shared by several blocks, it can be caused that a load of the global data increases and that a data interference occurs. 
     FIG. 7  is a block diagram showing a worst read case and a worst write case of the 256M multi-port DRAM shown in  FIG. 1 . 
   As shown, a single global data bus is provided with 512 bus lines and is formed with a hierarchical wiring structure. That is, a first metal wire and a second metal wire are provided for vertical and horizontal bus lines, respectively. Generally, a resistance of the first metal wire for the vertical bus line is higher than a resistance of the second metal wire for the horizontal bus line. 
   Meanwhile, length of the first metal wires connected to a single bank are different from one another. Therefore, a loading value of each bus line becomes different. The loading value also can be varied depending on a data transmit path as well as the difference of the length of the first metal wire. For example, the data transmit path between the first port PORT 0  and the seventh bank BANK 6  is the longest path in  FIG. 7 . Therefore, the loading value between the first port PORT 0  and the seventh bank BANK 6  has the largest value and, thus, the read or write operation occurring between the first port PORT 0  and the seventh bank BANK 6  becomes the worst read or write case. 
   As abovementioned, the 256M multi-port DRAM includes the 512-bit global data bus. When the number of the bus lines in the global data bus is more than 64-bit, a great amount of a current is consumed. 
   In order to reduce a problem caused by the great current consumption of the wide band global data bus, the applicant of the present application proposed a global data bus structure using a current sense method instead of a voltage drive method in U.S. Ser. No. 10/788,704. 
     FIG. 8  is a block diagram describing a data transfer unit QTRX and bus connector TL disclosed in a commonly owned copending application, U.S. Ser. No. 10/788,704, filed on Feb. 27, 2004, entitled “SEMICONDUCTOR MEMORY DEVICE”, which is incorporated herein by reference. 
   As shown, the bus connector TL and the data transfer unit QTRX are connected through the global data bus GIO. 
   A receiver RX of the bus connector TL is provided with two PMOS transistor P 1  and P 2 , three NMOS transistor N 1 , N 2 , and N 9 . First terminals of the first PMOS transistor P 1  and the second PMOS transistor P 2  are connected to a power voltage VDD. A second terminal and a gate of the first PMOS transistor P 1  are diode-connected to each other. A second terminal of the second PMOS transistor P 2  is connected to a first output terminal. A first terminal of the first NMOS transistor N 1  is connected with the second terminal of the first PMOS transistor P 1  at node A 1 . A second terminal of the first NMOS transistor N 1  is connected to the global data bus GIO. The first NMOS transistor N 1  and the second NMOS transistor N 2  receive a reference voltage VR through gates. A first terminal of the second NMOS transistor N 2  is connected to the first output terminal. The ninth NMOS transistor receives an evaluation signal EVAL 1  through a gate. A first terminal of the ninth transistor N 9  is connected to a second terminal of the second NMOS transistor N 2 ; and the second terminal of the ninth transistor N 9  is connected to the ground voltage VSS. 
   A transmitter TX of the bus connector TL is connected between a ground voltage VSS and the global data bus GIO and includes two NMOS transistors N 5  and N 6 . The fifth NMOS transistor N 5  receives a first data TX 1  through a gate; the sixth NMOS transistor N 6  receives a first drive pulse DP 1  through a gate. 
   The receiver QRX of the transfer unit QTRX is provided with two PMOS transistors P 3  and P 4 , three NMOS transistors N 3 , N 4 , and N 10 . First terminals of the third PMOS transistor P 3  and the fourth PMOS transistor P 4  are connected to the power voltage VDD. A second terminal and a gate of the third PMOS transistor P 3  are diode-connected to each other. A second terminal of the fourth PMOS transistor P 4  is connected to a second output terminal. A first terminal of the third NMOS transistor N 3  is connected with the second terminal of the third PMOS transistor P 3  at node A 2 . A second terminal of the third NMOS transistor N 3  is connected to the global data bus GIO. The third NMOS transistor N 3  and the fourth NMOS transistor N 4  receive the reference voltage VR through their gates. A first terminal of the fourth NMOS transistor N 4  is connected to the second output terminal. The tenth NMOS transistor N 10  receives a second evaluation signal EVAL 2  through a gate. A first terminal of the tenth transistor N 10  is connected to a second terminal of the fourth NMOS transistor N 4 ; and a second terminal of the tenth transistor N 10  is connected to the ground voltage VSS. 
   A transmitter QTX of the transfer unit QTRX is connected between the ground voltage VSS and the global data bus GIO and includes two NMOS transistors N 7  and N 8 . The seventh NMOS transistor N 7  receives a second data TX 2  through a gate; the eighth NMOS transistor N 8  receives a second drive pulse DP 2  through a gate. 
   The global data bus GIO, through actually implemented with a long metal wire, can be modeled with a resister R and a capacitor C which have equivalent value with the metal wire. 
   When the read operation RD is performed, a data is transmitted between the transmitter TX of the bus connector TL and the receiver QRX of the data transfer unit QTRX through the global data bus GIO. Meanwhile, when the write operation WT is performed, the data is transmitted between the transmitter QTX of the data transfer unit QTRX and the receiver RX of the bus connector TL through the global data bus GIO. 
   Abovementioned the read and the write operations are performed in a way that the transmitters TX and QTX charge or discharge the global data bus GIO in response to the first and the second data TX 1  and TX 2  and, then, the receivers RX and QRX sense a status of the global data bus GIO. 
   Meanwhile, a switch is placed between the bus connector TL and the global data bus GIO. The switch connects the global data bus GIO to one of a redundant column and a normal column according to a test result. 
     FIG. 9  is a waveform showing the read operation of the circuit shown in  FIG. 8 . 
   The first drive pulse DP 1 , synchronized with a clock, makes the first data TX 1 , activated into a logic level ‘H’, loaded into the global data bus GIO. The second evaluation signal EVAL 2  is activated into a logic level ‘H’ after a predetermined time has passed since the first drive pulse DP 1  is activated to thereby evaluate the first data TX 1  loaded into the global data bus GIO. Herein, the predetermined time is a time margin for charging or discharging the global data bus GIO. 
   If first data TX 1  inputted to the transmitter TX of the bus connector TL and the first drive pulse DP 1  are the logic level ‘H’, the fifth and sixth NMOS transistors N 5  and N 6  are turned on and, therefore, the global data bus GIO is discharged. After a voltage level of the node A 2  in the receiver QRX of the data transfer unit QTRX becomes lower than a threshold voltage VTH of the PMOS transistor, the third and fourth PMOS transistors P 3  and P 4  are turned on and, thus, an output DATA 2  from the receiver QRX of the data transfer unit QTRX becomes a logic level ‘H’. That is, the first data TX 1  having the logic level ‘H’ is correctly transmitted through the global data bus GIO. 
   Meanwhile, because a size of the fourth PMOS transistor P 4  is relatively larger than that of the tenth NMOS transistor N 10 , the output signal DATA 2  does not change into a logic level ‘L’ but shows a little fluctuation when the second evaluation signal EVAL 2  is the logic level ‘H’. 
   If the first data TX 1  with a logic level ‘L’ is inputted to the transmitter TX of the bus connector TL and the first drive pulse DP 1  is the logic level ‘H’, the global data GIO maintains a charged state. Therefore, the node A 2  in the data transfer unit QTRX is not discharged and, subsequently, the fourth PMOS transistor P 4  cannot drive the second output terminal into a logic level ‘H’. Then, when the second evaluation signal EVAL 2  becomes the logic level ‘H’, the tenth NMOS transistor N 10  is turned on and, therefore, the second output terminal is discharged. Thus, the output signal DATA 2  of outputted from the data transfer unit QTRX is a logic level ‘L’. That is, the first data TX 1  having the logic level ‘L’ is correctly transmitted through the global data bus GIO. 
   Referring to  FIG. 9 , the first drive pulse DP 1  is activated four times as the logic level ‘H’. Namely, the first data TX 1  is transmitted four times. In other words, the global data bus GIO is discharged only while the drive pulses DP 1  and DP 2  are in the logic level ‘H’. The global bus GIO is charged through the receiver RX in the bus connector TL and the receiver QRX in the data transfer unit QTRX. Because the first and the third NMOS transistors N 1  and N 3  receive the reference voltage VR and, therefore, are unstably turned on, the global data bus GIO is charged by the receivers RX and QRX during discharged in response to the drive pulses DP 1  and DP 2 . Therefore, sizes of the NMOS transistors N 5 , N 6 , N 7 , and N 8  in the transmitters TX and QTX, which perform a discharge of the global data bus GIO, are sufficiently large to compensate a current charge caused by the first and the third NMOS transistors N 1  and N 3 . 
     FIG. 10  is a block diagram showing a discharge procedure of the first global data bus GIO_LU in the  256 M multi-port DRAM shown in  FIG. 1 . 
   As shown, the first global data bus GIO_LU of the first quadrant in the 256M multi-port DRAM is connected to the four banks BANK 0 , BANK 2 , BANK 4 , and BANK 6 , two ports PORT 0  and PORT 2 , and the first global data bus connector PR_U. In each of the banks, a switch NMOS transistor exists between the bus connector TL and the global data bus GIO. The switch NMOS transistor is used as the switch shown in  FIG. 8 . The switch NMOS transistors in each bank BANK 0 , BANK 2 , BANK 4 , and BANK 6  respectively receive switch signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt; through each gate. The switch signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt; are always maintained a logic level ‘H’ and, therefore, the switch NMOS transistors are always turned on to thereby be connected with the first global data bus GIO_LU. 
   In order to transmit a data through the global data bus GIO, every block connected to the global data bus GIO should include a transmitter and a receiver coupled with the global data bus GIO. That is, the bus connector TL and the data transfer unit QTRX include the receivers RX and QRX and the transmitters TX and QTX, respectively. Though not illustrated, the first global data bus connector PR_U also includes a receiver and a transmitter. 
   As abovementioned, the receivers RX and QRX sense a data according to a state of the global data bus GIO and are served as a charge source for charging the global data bus GIO. 
   Referring to  FIG. 10 , the third bank BANK 2  transmits a data; the third port PORT 2  receives the data. In this case, the global data bus GIO is discharged by the transmitter TX in the third bank BANK 2  while a read drive pulse RDP&lt; 2 &gt;, activated when the read operation, is in a logic level ‘H’. A period when the read drive pulse RDP&lt; 2 &gt; is in the logic level ‘H’ is determined by an operational speed of the memory device. If the operation speed of the memory device is very high, the sector may be a several nano-seconds (ns). That is, the transmitter TX in the third bank BANK 2  should discharge the first global data bus GIO_LU within very short time. 
   Meanwhile, because the receivers RX and QRX charge the global data bus GIO even while the transmitter TX and QTX discharge the global data bus GIO, it is hard for the transmitter TX of the third bank BANK 2  to effectively discharge the global data bus GIO. The abovementioned problem also occurs at not only the write operation but also the read operation. 
   In order to solve the abovementioned problem, it is required that sizes of the NMOS transistors N 5  to N 8  in the transmitters TX and QTX are large to thereby discharge a sufficiently large amount of an electric charge of a short time. 
   However, as the size of the NMOS transistor is increased, a current consumption and a layout size are also increased. The problems caused by increasing the size of the transistor are deepened when the number of receivers connected to a single global data bus GIO is grown. Further, the problem leads a difficulty to a routing operation of the global data bus GIO. 
   SUMMARY OF THE INVENTION 
   It is, therefore, an object of the present invention to provide a multi-port memory device for improving a global data drive efficiency by turning off the switches which do not discharge a global data bus. 
   In accordance with an aspect of the present invention, there is provided a multi-port memory device including a global data bus containing a plurality of bus lines; a plurality of banks including a current sensing transmitter and a current sensing receiver, the transmitter and the receiver for exchanging a data with the global data bus; a plurality of ports including the transmitter and the receiver; a plurality of switches provided between the transmitters and the receivers in each of the banks and the bus line of the global data bus, the switch for selectively connecting the corresponding transmitter and the corresponding receiver with the global data bus; and a switching controller for generating a switch signal in response to a drive pulse and a data signal inputted to the transmitter, wherein the switch signal turns off the switches corresponding to the banks which are not discharging the global data bus. 
   In accordance with another aspect of the present invention, there is provided a multi-port memory device including a global data bus containing a plurality of bus lines; a plurality of banks including a current sensing transmitter and a current sensing receiver, the transmitter and the receiver for exchanging a data with the global data bus; a plurality of ports including the transmitter and the receiver; a plurality of switches provided between the transmitters and the receivers in each of the banks and the bus line of the global data bus, the switch for selectively connecting the corresponding transmitter and the corresponding receiver with the global data bus; a discharge signal generator for generating a discharge signal corresponding to each of the banks in response to a drive pulse and a data signal corresponding to each of the banks; and a switch signal generator for generating a switch signal by logically combining the discharge signal, wherein the switch signal turns off the switches corresponding to the banks which are not discharging the global data bus. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram describing a 256M multi-port memory device disclosed in a commonly owned copending application, U.S. Ser. No. 10/750,156, filed on Dec. 31, 2003, entitled “MULTI-PORT MEMORY DEVICE”, which is incorporated herein by reference; 
       FIG. 2  is a diagram showing a relationship between a transfer bus and a segment of the conventional 256M multi-port DRAM shown in  FIG. 1 ; 
       FIGS. 3A and 3B  are block diagrams describing a normal read path and a normal write path of the conventional 256M multi-port DRAM, respectively; 
       FIGS. 4A and 4B  are block diagrams describing a cross read path and a cross write path of the conventional 256M multi-port DRAM, respectively; 
       FIG. 5  is a diagram showing a data transmitting structure of the 256M multi-port DRAM shown in  FIG. 1 ; 
       FIG. 6  is a block diagram describing a structure of the global data bus GIO shown in  FIG. 5 ; 
       FIG. 7  is a block diagram showing a worst read case and a worst write case of the 256M multi-port DRAM shown in  FIG. 1 ; 
       FIG. 8  is a block diagram describing a data transfer unit QTRX and bus connector TL disclosed in a commonly owned copending application, U.S. Ser. No. 10/788,704, filed on Feb. 27, 2004, entitled “SEMICONDUCTOR MEMORY DEVICE”, which is incorporated herein by reference; 
       FIG. 9  is a waveform showing a read operation of the circuit shown in  FIG. 8 ; 
       FIG. 10  is a block diagram showing a discharge procedure of the first global data bus GIO_LU in the 256M multi-port DRAM shown in  FIG. 1 ; 
       FIG. 11  is a block diagram describing a switch control logic of a 256M multi-port DRAM in accordance with a preferred embodiment of the present invention; 
       FIG. 12  is a diagram depicting a discharge signal generator in accordance with an exemplary logic implementation; 
       FIG. 13  is a waveform demonstrating the read operation performed between the third bank BANK 2  and the third port PORT 2 ; 
       FIG. 14  is a diagram depicting a switch signal generator in accordance with an exemplary embodiment of the present invention; and 
       FIG. 15  is a wave form demonstrating an operation of a switch signal generator shown in  FIG. 11 . 
   

   DETAILED DESCRIPTION OF INVENTION 
   Hereinafter, a multi-port semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings. 
     FIG. 11  is a block diagram describing a switch control logic of a 256M multi-port DRAM in accordance with a preferred embodiment of the present invention. 
   As shown, the switch control logic generates switch signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt; for controlling switch NMOS transistors shown in  FIG. 10 . 
   Meanwhile, the switch control logic includes a discharge signal generator  1110  and a switch signal generator  1120 . The discharge signal generator  1110  receives drive pulses DP&lt; 0 &gt;, DP&lt; 2 &gt;, DP&lt; 4 &gt;, and DP&lt; 6 &gt; and data signals TX&lt; 0 &gt;, TX&lt; 2 &gt;, TX&lt; 4 &gt;, and TX&lt; 6 &gt; corresponding to banks BANK 0 , BANK 2 , BANK 4 , and BANK 6  to thereby output discharge signals C&lt; 0 &gt;, C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt;. The switch signal generator  1120  logically combines the discharge signals C&lt; 0 &gt;, C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt; to thereby generates the switch signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt; for turning off the switch NMOS transistors in the banks which does not actually discharge the first data bus GIO_LU. 
     FIG. 12  is a diagram depicting the discharge signal generator  1110  in accordance with an exemplary embodiment of the present invention. 
   As shown, the discharge signal generator  1110  is provided with four NAND gates NAND 1  to NAND 4 . Each of the four NAND gates NAND 1  to NAND 4  respectively receives a corresponding data signal TX and drive pulse DP to thereby output the discharge signal C. For example, the first NAND gate NAND 1  receives a first data signal TX&lt; 0 &gt; and a first drive pulse DP&lt; 0 &gt; to thereby output the first discharge signal C&lt; 0 &gt;. 
     FIG. 13  is a waveform demonstrating the read operation performed between the third bank BANK 2  and the third port PORT 2 . 
   First, the discharge signals C&lt; 0 &gt;, C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt; are a logic level ‘H’ before the read command corresponding to the banks, i.e., BANK 0 , BANK 2 , BANK 4 , and BANK 6 , connected to the first global data bus GIO_LU, is inputted. 
   After the read command corresponding to the third bank BANK 2  is inputted, the third drive pulse DP&lt; 2 &gt; is activated. If the third data TX&lt; 2 &gt; is a logic level ‘H’ during an activation sector of the third drive pulse DP&lt; 2 &gt;, the third discharge signal C&lt; 2 &gt; corresponding to the third bank BANK 2  becomes a logic level ‘L’. While the third discharge signal C&lt; 2 &gt; has the logic level ‘L’, the other discharge signals C&lt; 0 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt; keep a logic level ‘H’. 
   That is, the discharge signal gives information about which bank discharges the global data bus GIO and when the global data bus GIO is discharged. For example, the discharge signals C&lt; 0 &gt;, C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt; give the information which bank among the banks, i.e., BANK 0 , BANK 2 , BANK 4 , and BANK 6 , connected to the first global data bus GIO_LU discharges the first global data bus GIO_LU. 
     FIG. 14  is a diagram depicting the switch signal generator  1120  in accordance with an exemplary embodiment of the present invention. 
   As shown, the switch signal generator  1120  includes four NAND gates NAND 5  to NAND 8  and four inverters INV 1  to INV 4 . 
   Each of the four NAND gates NAND 5  to NAND 8  receives three discharge signals out of the discharge signals C&lt; 0 &gt;, C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt;. Further, every three inputs inputted to the NAND gates NAND 5  to NAND 8  has a different combination. That is, the NAND gate, among the NAND 5  to NAND 8 , for generating the switch signal receives the three discharge signals except for the discharge signal of the bank corresponding to the switch signal. For example, the sixth NAND gate NAND 6  for generating the third switch signal SW&lt; 2 &gt; receives the discharge signals C&lt; 0 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt;. However, the third discharge signal C&lt; 2 &gt; corresponding to the third bank BANK 2  is not inputted to the sixth NAND gate NAND 6 . 
   The inverters INV 1  to INV 4  respectively receives outputs of the NAND gates NAND 5  to NAND 8  to thereby output switch signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt;. For example, the fifth NAND gate NAND 5  receives three discharge signals, i.e., C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt;, and, then, the first inverter INV 1  receives the output of the fifth NAND gate NAND 5  to thereby output the first switch signal SW&lt; 0 &gt;. 
     FIG. 15  is a waveform demonstrating an operation of the switch signal generator  1120  shown in  FIG. 11 . 
   As abovementioned, the discharge signals C&lt; 0 &gt;, C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt; have initially logic level ‘H’ before the read command corresponding to the banks connected to the first global data bus GIO_LU, i.e., BANK 0 , BANK 2 , BANK 4 , and BANK 6 , is inputted. Therefore, the switch signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt; are logic level ‘H’. The switch NMOS transistors in the banks BANK 0 , BANK 2 , BANK 4 , and BANK 6  are turned on in response to the switch signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt;. 
   After the read command corresponding to the first bank BANK 0  is inputted, the first drive pulse DP&lt; 0 &gt; is activated into a logic level ‘H’. When the first data TX&lt; 0 &gt; becomes a logic level ‘H’ during an activation sector of the first drive pulse DP 1 , the first discharge signal C&lt; 0 &gt; becomes a logic level ‘L’. Meanwhile, the other discharge signals C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt; keep holds a logic level ‘H’. 
   As referring to  FIG. 14 , the switch signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt; are generated by logically multiplying three discharge signals except the discharge signal corresponding to its own bank. That is, the first switching signal SW&lt;O&gt; is generated from the discharge signals C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt;. Consequently, only the switch NMOS transistor of the first bank BANK 0 , actually discharging the first global data bus GIO_LU, is turned on during a discharge sector and, further, the other switch NMOS transistors are turned off. 
   After the discharge sector is over, the all discharge signals C&lt; 0 &gt;, C&lt; 2 &gt;, C&lt; 4 &gt;, and C&lt; 6 &gt; recover the logic level ‘H’ and, therefore, the all switching signals SW&lt; 0 &gt;, SW&lt; 2 &gt;, SW&lt; 4 &gt;, and SW&lt; 6 &gt; also recover the logic level ‘H’. Then, the switch NMOS transistors corresponding to the banks BANK 0 , BANK 2 , BANK 4 , and BANK 6  to thereby charge the first global data bus GIO_LU. 
   At the discharge sectors hereafter, only the switch NMOS transistor which actually discharges the global data bus GIO, is turned on and the other switch NMOS transistors are turned off. 
   In the abovementioned embodiment, because only the switch NMOS transistor of the bank, which actually discharges the global data bus GIO, is connected to the global data bus GIO, there exists only one charge source. Therefore, a sufficient charge can be achieved without increasing the size of the transistors in the transmitters TX and QTX. 
   In another embodiment, the present invention also can be applied to other multi-port memory devices having a RAM cell such as a static random access memory (SRAM). Further, the number of the multi-port memory device and the banks can be varied according to a capacity of the memory device and a chip size. Still further, transistors and logic gates used in the abovementioned embodiment can be changed according to a polarity of signals. 
   The present invention provides a multi-port memory device having a global data bus which is driven by sensing a current, the multi-port memory device is for reducing a power consumption by turning off the transistors which does not discharge the global data bus GIO, reducing a size of the transistor performing a discharge operation, and thereby reducing a chip size. 
   The present application contains subject matter related to Korean patent application No. 2005-27400, filed in the Korean Patent Office on Mar. 31, 2005, the entire contents of which being incorporated herein by reference. 
   While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.