Abstract:
A recursive type adder for calculating the sum of two operands. It is used to calculate the sum of two binary data numbers using adders in the form of integrated circuits, particularly for information processing systems wherein the adders constitute one of the fundamental operations of data processing. The invention is classified in the category of parallel-parallel type adders.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention concerns a recursive type adder for calculating the sum of two operands. 
     This invention is used to calculate the sum of two binary data numbers using adders in the form of integrated circuits, particularly for information processing systems wherein the adders constitute one of the fundamental operations of data processing. 
     The invention is classified in the category of parallel-parallel type adders. These allow addition of two operands A and B respectively comprised of binary data a 1 , a 2 , . . . , a n  and b 1 , b 2 , . . . , b n . The result is furnished in parallel binary form. 
     2. Description of the Related Art 
     Generally, a parallel-parallel adder comprises a complex association of interconnected elementary series adders. Each elementary adder receives two bits to be added, belonging to each of the operands or to the intermediate results effected by other elementary adders in the complex circuit. Each adder furnishes the binary result of one addition at one output but may also furnish, at two other outputs, two bits respectively termed propagation and generation bits. 
     The propagation bit P k  furnished by one adder AD k , of row k (full adder) in a range comprising K adders connected in series (1≦k≦K), conforms to the relation P k  =P k  ·P k-1 . . . P 1  with P k  =a k  ⊕b k . In known manner, ⊕ designates exclusive operator XOR. 
     a k  and b k  respectively denote the input bits from row k, to be added. 
     If the sum effected by each elementary adder AD k  of a row is designated by local addition, it is necessary to add two bits a k  and b k  belonging to the two operands A and B. Three situations may arise; 
     (1) if a k  =b k  =0 no carry is generated by the elementary adder and if a carry comes from the adders in a row lower than k which effect addition of lower weight bits, this carry is then &#34;trapped&#34; by added AD k . Thus, bit S k  of impulse 2K of the sum is a logic 1; 
     (2) if a k  =0 and b k  =1 or a k  =1 and b k  =0, then no carry is generated locally, but a carry coming of lower weight is propagated towards the adder in row k+1, and s k  =0. If not, s k  remains equal to 1; and 
     (3) if a k  =b k  =1, a carry is generated locally by adder AD and this carry is transmitted towards the adder of upper row k+1. 
     In the same manner, the local generation function g k  for adder AD k  of row k obeys the relation 
     
         g.sub.k =a.sub.k ·b.sub.k. 
    
     This relationship of logic &#34;·&#34; corresponds to the logical function AND. 
     The generative function G k  of an adder AD k  corresponds to an output bit of this adder, equal to 1, each time a carry appears after addition. Propagation function P k  corresponds to an output bit of this adder, equal to 1, when a carry originating from an adder of the preceding row (k-1) must be propagated to the adder in the following row (k+1). 
     Under these conditions, the base relation of carry r k , calculated by a rapid parallel adder of row k, is written 
     
         r.sub.k =g.sub.k +(P.sub.k ·r.sub.k-1). 
    
     In this equation the plus sign designates the logic operation OR. 
     The carry r k  is produced by the addition of the first k bits of the two operands. This equation is valid for any value of k. 
     The final calculation of the sum S k  is effected by a simple operator XOR 
     
         S.sub.k =P.sub.k ⊕r.sub.k-1. 
    
     In a series of k adders, r 1  IN designates the input carry applied to the first adder in the series, and r K  OUT designates the output carry of the last adder in the series. 
     Parallel adders functioning on this principle and using series of elementary adders of the &#34;full adder&#34; type are described, for example, in the following articles: 
     (1) the publication IEEE TRANSACTIONS ON COMPUTERS--VOLUME C31, NO. 3, March 1982, pages 260-264--in an article entitled &#34;Regular Layout for Parallel Adders&#34;; 
     (2) 1983--pages 10-16--in an article entitled &#34;Comparison of ALU Structures for VLSI Technology&#34;; 
     (3) the book entitled &#34;Circuits logiques de traitement numerique d&#39;information&#34; [&#34;Logic Circuits for Digital Information Processing&#34;]--CEPAUDES edition, ECOLE NATIONAL SUPERIEURE DE L&#39;AERONQUTIQUE ET DE L&#39;ESPACE [National College of Aeronautics and Space]--1979--Pages 185-289. 
     These publications describe complex circuits for elementary adders capable of effecting the sum of two binary operands. 
     The essential problem posed by complex adders comprised of &#34;full adders&#34; arises primarily from the fact that carrys are generated by certain adders and certain carrys must be propagated. Actually, any generation or propagation of a carry requires complex connections and supplementary circuits; in the case of an integrated circuit adder, these connections and these supplementary circuits affect not only the surface of the integrated circuit, but also its performance. 
     Among rapid parallel adders, one of the most frequently used is the &#34;carry select adder&#34;. In this type of adder, which comprises at least one series of elementary full adders, two parallel carry calculations are effected. The first calculation is effected with the hypothesis of an input carry being equal to 1, while the second calculation is effected with the hypothesis of an input carry equal to zero. Thus, during addition, it is not necessary to know in advance what is the carry coming from the preceding bits in order to effect addition of the subsequent bits. When the carry is effectively determined calculations effected in each of the hypotheses, the result corresponding to the valid hypothesis is selected in the time necessary for the addition. 
     This type of adder, while having the disadvantage of doubling a portion of the material, as two parallel calculations are performed with different hypotheses, has the advantage of increasing calculation speed. Actually, when the input carry in the first adders of the series is not known, it is possible to gain time by virtue of the two hypotheses described above, by effecting the adding calculations during the time it takes for the input carry to arrive at the input of the series of adders. 
     In general, parallel adders may be one of two types: &#34;repetitive&#34; and &#34;recursive&#34; type adders. In both types of adders, propagation of the carry is the essential problem. 
     In a repetitive type adder, an adder for n bits is constructed by adding an elementary cell (full adder) to an adder already comprising n-1 elementary cells connected in series. This structure translates the relation of recurrence of addition. To increase the propagation speed of this type of adder, it is necessary to optimize only one propagation path for the carry. The classic examples of this type of adder is the Manchester carry chain adder. 
     In a recursive type adder, an n bit adder is subdivided into two n/2 bit adders. In this type of adder, the carry propagation time is theoretically Log(n)T, where T designates the propagation time for an elementary cell. This recursive structure is used primarily in series adders permitting distribution of the necessary information to the different cells in optimal time. This type adder is often called a &#34;carry look ahead adder&#34;. 
     Generally, manufacturing these repetitive type adders requires less silicon, but they are slower than recursive type adders, which do use a great deal of silicon. 
     Besides repetitive and recursive embodiments, intermediate adaptations exist which are, in effect, compromise solutions. These compromise embodiments simultaneously take advantage of the repetitive aspect of adders because of its relatively few obstructions and the recursive aspect because of its speedy performance. 
     One of these known compromise embodiments is an optimal carry select adder. This embodiment consists of breaking the addition up into several segments. Hypotheses are formed for each of the segments, as indicated above, regarding the carry input for each segment. The carry input for each segment is determined more and more closely with the help of a series of cells which effect the logic operation g·r+p; in this relation, g denotes a carry bit and p is a bit which indicates whether or not there is propagation of the bit. This type of adder may be termed a &#34;g·r+p adder&#34;. 
     The adder wherein the carry input is equal to zero has for the carry output, the carry generated by the segment, designated by G t . 
     The adder wherein the carry input is equal to 1 has its own calculated carry as the carry output. The propagation bit is equal to 1 and is designated by P t  when there is propagation in the segment. If r in  designates the real carry entering a segment, the carry output r out  is obtained by the logic operation r OUT  =G t  +P t  ·r IN . 
     Calculations are performed in parallel in the different segments and optimizing an adder of this type depends upon the number of bits which each segment must calculate to render all the propagation paths critical in a series structure adder of predetermined hierarchy. The definitions of critical pathways, the series structure and the hierarchical levels are described in the publications previously cited. 
     In an optimal carry select adder, the number of elementary addition cells may be progressively increased in each new segment, so that the calculation time necessary for one segment is equal to that of the preceding segment, increased by the selection time of the carry. In this case the result is an optimal carry select adder. 
     Another known compromise embodiment is the use of a carry skip adder. This type of adder resembles the previous one in propagation of the carry. It differs from the preceding adder in that for each segment, only one repetitive type adder is used (comprising several elementary addition cells connected in series) wherein the input carry is the carry coming from the selection cell of the preceding carry. However, it is necessary to calculate the propagation function at each segment to control the corresponding selection cell. The name of this adder comes from the fact that the carry may be more quickly propagated, by a line parallel to the series adders and which is a far more rapid path than that which crosses the series of adders. 
     This adder has one disadvantage in relation to the preceding one: to render all its paths critical for the sum to be calculated as well as for the carry, when proceeding from low to high weight bits to be added, to increase the size of the segments (i.e., the number of elementary adders in series in each segment), then to decrease their size in the middle of the adder. Decreasing the size of the segments is actually compulsory so as to prevent the carry from being obtained too rapidly in relation to sum S. 
     In the optimal carry select adder, the size of the segments increases in linear progression. The time for selecting the sum varies with the hypothesis of a selection time equal to a propagation time across a full adder. In known manner, approximately n(n+1)/2 bits are calculated in time nT, n 2  /2 bits are calculated in nT and n bits are calculated in √2nT (T designating the time necessary to calculate the addition of two data bits). 
     In the optimal carry skip adder, the size of the segments increases in linear progression for the first half of bits to be added and then decreases in the same manner. It is said that for this type of adder, approximately n bits are calculated in a time equal to 2√nt. 
     Generally, these two embodiments behave asymptotically at radix 2 n, and if the optimal carry skip adder is slower than the optimal carry select adder, it is, on the other hand, more economical in terms of substrate required for manufacture. 
     Adders using a branching system (carry look ahead adders, for example), totally repetitive, occupy considerable space which increases by n log(n) (n being the number of respective data bits to be added), while totally repetitive embodiments are very slow. 
     Optimal embodiments, such as the carry skip adder or the carry select adder, are an interesting compromise but are not totally satisfactory: while they require about the same surface as a carry skip adder, they cannot attain the same speed as a carry select adder. 
     The goal of the invention is to overcome these disadvantages and particularly to achieve an adder which uses about the same space as a carry skip adder, while at the same time performing nearly as fast as a carry look ahead adder. 
     As will later be seen in detail, the adder which is the subject of the invention has a novel structure termed recursive which results in a considerably elevated speed/surface ratio. 
     SUMMARY OF THE INVENTION 
     The object of the invention is a recursive type adder for calculating the sum of two operands A and B respectively formed of binary data a 1 , a 2 , . . . a n  and b 1 , b 2 , . . . b n , of varying weights, operands A and B comprising a first and a second operand AL and BL respectively formed from the low weight data and a third and fourth operand AH and BH respectively formed from the high weight data, characterized by the fact that for a recursion level NH in the adder (NH being a whole number higher than or equal to 1) and for an order K of the adder (K being an integer defining a number of elementary addition cells in a level 1 adder), this adder designated as AD K   NH , recursively constructed of the following: 
     (1) a first adder AD K-1   NH  of order K-1 and level NH constructed in recursive fashion and comprising inputs respectively receiving the first and second low weight operands AL and BL, and a first and a second output respectively furnishing a sum operand SL from the first and second low weight operands AL and BL, and an output carry bit COUT for the sum effected; 
     (2) a second adder ADP K-1   NH-1  order K-1 and level NH-1 recursively constructed and comprising inputs respectively receiving the third and fourth high weight operands AH and BH, an input (CIN) connected to the second output (COUT) of the first adder, and a first, a second and a third output respectively furnishing a sum operand SH from the third and fourth high weight operands AH and BH, a carry propagation bit P corresponding to said sum and a carry generation bit G; 
     (3) a global carry selector (SE) comprising three inputs (C, G, P) respectively connected to the second output of the first adder and to the second and third outputs of the second adder, and an output providing a global output carry bit C OUT   NH  resulting from the logic OR operator 
     
         C.sub.OUT.sup.NH =G+P·COUT; 
    
     According to another characteristic of the invention, the second adder ADP K-1   NH-1  is constructed in recursive fashion and comprises; 
     (4) a third adder ADP K-2   NH-1  of order K-2 and level NH-2 comprising inputs respectively receiving operands AHL and BHL respectively comprised of low weight data from the third and fourth operands AH and BH, and a carry input (CIN) connected to the second output of the first adder to receive the output carry bit (COUT) of said first adder, and first, second and third outputs respectively furnishing a sum operand (SHL) from operands AHL and BHL received at the input, a carry generation bit (G1) and a carry propagation bit (P1) from the sum effected; 
     a first intermediate carry selector comprising three inputs respectively connected to the second output (COUT) of the first adder, to the second output (G1) of the third adder and to the third output (P1) of the third adder, said first carry selector furnishing at one output an output carry bit C1OUT conforming to the logic equation; 
     
         C1OUT=G1=P1·COUT; 
    
     (6) a fourth adder ADP K-2   NH-2  of order K-2 and level NH-2 comprising inputs respectively receiving operands AHH and BHH respectively comprised of high impulse data from the third and fourth operands, a carry input (C2IN) connected to the output of the first selector (SES) to receive the carry output bit (C1OUT) of said selector and of the first, second and third outputs respectively furnishing a sum operand (SHH) of operands (AHH and BHH) received at the input, a carry generation bit (G2) and a carry propagation bit (P2) of the sum effected; 
     (7) a second intermediate carry generation selector (SEC), comprising three inputs respectively connected to the second carry generation output (G1) of the third adder, to the second carry generation output (G2) of the fourth adder and to the third carry propagation output (P2) of the fourth adder, said second selector furnishing at one output corresponding to the third output of the second adder, carry generation bit (G) of said second adder, resulting from the logic OR operator 
     
         G=G2+P2·G1; 
    
     and 
     (8) a logic port of the &#34;AND&#34; type with two inputs respectively connected to the third propagation output (P2) of the fourth adder and to the third propagation output (P1) of the third adder, said logic port furnishing at the output corresponding to the second output of the second adder, output propagation bit P of said second adder, resulting from the logic multiplication P=P1·P2. 
     According to another characteristic, adder ADP K   1  of order K and level 1, recursively constructed from adder ADP K-1   NH-1  of order K-1 and level NH-1, capable of adding two by two bits from one level of data a i , a i+i , . . . , a i+j , a i+k , and b i , b i+1 , . . . b i+j , b i+k  of the two operands A and B is composed of: 
     (1) a succession of at least K elementary addition cells, of the &#34;full adder&#34; type, each cell (FA i+j ) of row i+j comprising two inputs to respectively receive a pair of bits such as (a i+j , b i+j ), an incoming carry input to receive a carry output bit (r i+j-1 ) furnished by a first outgoing carry output of a preceding elementary cell FA i+j-1  of the said succession, the incoming carry input of the first elementary cell of the said succession receiving a bit of 0 value and the outgoing carry output of the last elementary cell of the said succession furnishing a carry generation bit (G) for said succession, each elementary cell (FA i+j ) further comprising a second and a third output respectively furnishing a local addition bit s i+j  and a propagation bit p i+j , bits r i+j , s i+j  and p i+j  resulting from the logic operations ##EQU1## wherein &#34; &#34; is the AND operator, and &#34;+&#34; is the OR operator and &#34;⊕&#34; is the XOR operator. 
     (2) a logic carry calculating propagation unit (CP) for the adder P comprising inputs respectively connected to the third elementary cell propagation outputs (p i+j ) for furnishing at one output a propagation bit p i+k  for said adder ADP K   1  resulting from the logic operation 
     
         P.sub.i+k =P.sub.i+k ·P.sub.i+k-1 ·. . . ·p.sub.i+1 ·p.sub.i or 
    
     
         P.sub.i+k =P.sub.i+k-1 ·p.sub.i+k ; and 
    
     (3) a logic sum calculation unit (CS) comprising inputs respectively connected to two addition outputs of the elementary cells, to propagation outputs p i+j  =p i+j-1  ·p i+j , and an incoming carry input CIN connected to the outgoing carry output of the preceding adder, said sum calculation unit (CS) respectively furnishing on the outputs of the addition operands s i , . . . , s i+j , . . . , s i+  k calculated by adder ADP and resulting from the logic operation: 
     
         s.sub.i+j =s.sub.i+j ⊕(P.sub.i+j-1 ·CIN) with 
    
     
         P.sub.i-1 =1. 
    
     According to another characteristic, adder AD K   1  of order k and level 1 comprises an adder ADP K   1  of order K and level 1 wherein the input of the carry input (CIN) receives a bit (CIN) equal to 0. 
    
    
     Other characteristics and advantages of the invention will be apparent from the following description, taken in reference to the attached drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic representation of an adder AD K   NH  of level NH and order K, a recursive structure, in conformity with the invention; 
     FIG. 2 is a schematic representation of one of the adders ADP K-1   NH-1  of level NH-1 and order K-1, of recursive structure, belonging to the recursive structure adder of FIG. 1; 
     FIG. 3 is a schematic representation of an adder ADP K   1  of order K and row 1, belonging to the recursive structure adder of FIG. 1; 
     FIG. 4 is a schematic representation of an adder AD K   1  of order K and row 1 deduced from the adder AD K   1  of FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Recursive structure adder AD K   NH  schematically represented in FIG. 1, has a recursion level of NH and an order K. Order K corresponds to the number of elementary addition cells or full adders to comprise an adder of level NH=1. Level NH (NH being an integer) is actually the number of recursions necessary to construct an adder with a structure of level NH, from a structure of level NH-1, and so forth, up to level 1. Such adders have a branching structure, with the different branches comprising several series of full adders. 
     Adder AD K   NH  shown in this drawing allows calculation of the sum of two operands A and B respectively formed of binary data a 1 , a 2 , a i , a n  and b 1 , b 2 , b i , b n  (with 1≦i≦n) having different weights. These two operands may themselves comprise a first and a second operand AL and BL respectively formed of low weight binary data a i  and b i  and of third and fourth operands, AN and BH, respectively formed of the high weight binary data a i  and b i . 
     Adder AD K   NH  comprises, in recursive fashion, a first adder AD K-1   NH  of order K-1 and level NH, which is itself recursively constructed. Said first adder comprises inputs which respectively receive the first and second low weight operands AL and BL. A first input on said first adder furnishes operand SL resulting from the sum of low weight operands AL and BL received at the input. A second output of said first adder furnishes output carry bit COUT, resulting from the addition effected. 
     Adder AD K   NH  also comprises a second adder ADP K-1   NH-1  order K-1 and level NH-1, also constructed in recursive fashion. Said second adder comprises inputs which respectively receive the third and fourth operands AH and BH consisting of high weight data. One input CIN of this adder, called the &#34;incoming carry&#34;, is connected to the second output of the first adder AD K-1   NH-1 , to receive carry output bit COUT from the first adder. Said second adder ADP K-1   NH-1  also comprises a first input which furnishes a sum operand SH from the third and fourth operands AH and BH of the high weight data received at the input. A second output of said second adder furnishes carry propagation bit P, while a third output furnishes carry generation bit G resulting from the addition. 
     Finally, adder AD K   NH  comprises a carry selector SE. Said carry selector comprises three inputs 1, 2, 3 respectively connected to the second output of the first adder AD K-1   NH , and to the second and third outputs of the second adder ADP K-1   NH`  to respectively receive bits COUT, P and G. At one output, said carry selector furnishes global carry output bit C OUT   NH  from subject adder AD K   NH . 
     Said global output carry bit results from the logic OR operator C OUT   NH  =G+P·COUT effected by selector SE and wherein the plus sign designates an &#34;OR&#34; and the &#34;·&#34; designates a logic &#34;AND&#34;. 
     FIG. 2 is a more detailed schematic representation of the second adder ADP K-1   NH-1  of order k-1 and level NH-1 of FIG. 1. This drawing will lead to a greater understanding of the recursive structure of the adder of FIG. 1. The second adder ADP K-1   NH-1  which is shown in FIG. 2 is itself recursively constructed and comprises a third adder labelled ADP K-1   NH-1 , of order K-2 and level NH-2. Said third adder comprises inputs which respectively receive operands AHL and BHL respectively comprised of low weight data contained in third and fourth operands AH and BH. Carry bit CIN incoming from said third adder ADP K-1   NH-1  described above is connected to the second output of first adder AD K-1   NH  to receive carry output bit COUT from said first adder. 
     The third adder ADP K-2   NH-1  comprises a first, second and third output which respectively furnish a sum operand SHL from operands AHL and BHL received at the input, an outgoing carry generation bit G1 and an outgoing carry propagation bit P1 from the sum effected by said third adder. 
     The second adder ADP K-1   NH-1  also comprises a first intermediate carry selector SES comprising three inputs. These three inputs are respectively connected to the second output of the first adder AD K-1   NH  and to the second and third outputs of third adder ADP K-2   NH-1  to respectively receive bits COUT, G1 and P1. Said first intermediate carry selector SES furnishes at one input, carry output bit C1OUT for the addition effected by third adder ADP K-2   NH-1 . Said bit C1OUT results from the logic OR operator G1+P1·COUT effected by the first intermediate selector SES. As before, the plus sign &#34;+&#34; designates an &#34;OR &#34; and the &#34;·&#34;, a logic &#34;AND&#34;. 
     Finally, second adder ADP K-1   NH-1  comprises a fourth adder ADP K-2   NH-2  of order K-2 and level NH-2, a second intermediate selector SEC and a logic output port &#34;AND&#34;. 
     The fourth adder comprises inputs respectively receiving operands AHH and BHH respectively consisting of high weight data from the third and fourth operands AH and BH described above. Input C2IN of fourth adder ADP K-2   NH-1  is connected to the output of first intermediate selector SES to receive the carry output bit C1OUT furnished by said first intermediate selector. 
     The fourth adder also comprises first, second and third outputs which respectively furnish a sum operand SHH from input operands AHH and BHH, a carry generation bit G2 and a carry propagation bit P2 for the sum effected by said fourth adder. 
     Second intermediate selector SEC furnishes carry bit G, which is the carry output bit from second adder ADP K-1   NH-1 . Second selector SEC comprises three inputs respectively connected to the second generation output of third adder ADP K-2   NH-1 , to the second generation output of fourth adder ADP K-2   NH-2  and to the third propagation output of the fourth adder, to respectively receive bits G1, G2 and P2. Said second intermediate selector SEC furnishes at one carry generation output, which is also the second output of the second adder ADP K-1   NH-1 , carry generation bit G. Said bit results from the logic OR operator G=G2+P2·G1 effected by the second selector SEC wherein the plus sign &#34;+&#34; designates the logic operation &#34;OR&#34; and the &#34;·&#34; designates the logic operation &#34;AND&#34;. 
     The logic output port labeled ANDs comprises two inputs respectively connected to the third outputs of the third and fourth adders ADP K-2   NH-1  and ADP K-2   NH-2  for respectively receiving propagation bits P1, P2. Said logic port furnishes at one output, which corresponds to the second propagation output of second adder ADP K-1   NH-1 , propagation bit P. This bit is the result of the logic AND operator P=P1·P2. 
     FIG. 3 is a schematic representation of adder ADP K   1  of order K and level 1. Said adder is recursively obtained from adder ADP K-1   NH-1  of order K-1 and level NH-1. It is capable of adding two at a time, the bits in a segment of data a i , a i+1 , . . . , a i+j , . . . a i+k , and b i , b i+1 , . . . b i+j , . . . b i+k , from one segment of data from two operands A and B (i being between 1 and n). This adder comprises at least K elementary addition cells, of the &#34;full adder&#34; type. These cells are represented by FA i , FA i+1 , FA i+j , . . . FA i+k  in the drawing. Therefore, cell FA 1 , for example, comprises two inputs for respectively receiving bits a i  and b j . In the same manner, bits a j  and b j  are also applied to two inputs of cell FA i+j , while bits a K  and b K  are applied to two inputs of cell FA i+K . 
     Each elementary addition cell also comprises an incoming carry input for receiving an outgoing carry bit furnished by a first outgoing carry output from a preceding addition cell in the succession of cells. Therefore, the cell or full adder FA i+j  comprises an input E i+j  which receives an incoming carry bit coming from a first output of the preceding adder FA i+j-1  (not shown in the drawing). In the same manner, one input Ei+2 of adder FA i+2  receives an outgoing carry bit r i+1  from a first output of the preceding adder FA i+1 . 
     As will later be seen in detail, input E i  of incoming carry of first adder FA 1  of the succession receives a bit with a value of 0, while the output of the outgoing carry of the succession furnishes carry generation bit r i+k  =G to the succession of adders. 
     Each elementary cell such as FA i+j  also comprises a first and a second output which respectively furnish a local sum bit and a local propagation bit P i+j . 
     In known manner for cells of full adders or Full Adders, bits p i+j , r i+j , s i+j  result from the following logic operations: ##EQU2## In these operations, &#34;·&#34; indicates operator &#34;AND&#34;, &#34;⊕&#34; is the &#34;XOR&#34; operator and &#34;+&#34; is the &#34;OR&#34; operator. 
     Adder ADP K   1  shown in the drawing also comprises a logic unit CP for calculating the propagation of the carry for this adder. This unit comprises inputs which are respectively connected to the second and third outputs of the elementary cells FA i , FA i+1 , . . . FA i+j , . . . FA i+k . Thus, this unit receives the local sum bits s i , s i+1 , . . . s i+j , . . . s i+k , and the local propagation bits p i , p i+1 , . . . p i+k , . . . p i+k . At its output P it furnishes a carry propagation bit P=K for said adder AD PK   1 . This bit results from the logic AND operation: 
     
         P.sub.i+K =R.sub.i+k ·p.sub.i+K-1 ·. . . ·p.sub.i+1 ·p.sub.i 
    
     or even 
     
         P.sub.i+k =P.sub.i+K-1 ·P.sub.i+K 
    
     The &#34;·&#34; here indicates logic operator &#34;AND&#34;. 
     The propagation calculating unit CP comprises logic &#34;AND&#34; type ports labeled AND i+1 , AND i+2 , . . . AND i+K  in the drawing. Each of these ports has two inputs. The two inputs of the first port AND i+1  are respectively connected to the propagation outputs p i  and p i+1  of the first pair of cells FA i , FA i+1 . Port AND i+2  comprises two inputs respectively connected to the third propagation output p of cell FA i+2  and to the output of preceding port AND i+1 . 
     In the same fashion, port AND i+K  comprises two inputs respectively connected to the third propagation output of cell FA i+K  and to the output of the preceding port AND i+K-1 . 
     Port AND i+2 , for example, then furnishes a bit p i+2  =P i+1  ·p i+2  and port AND i+K  furnishes a bit p i+K  =P i+K-1  ·p i+j . Generally, it is P i+j  =P i+j-1  ·p i+j . Adder ADP K   1  also comprises a logic unit CS for sum calculation, which furnishes at its outputs operands S i , S i+1 , . . . , S i+j , . . . , S i+K  of addition of the binary data received at the first inputs of the adder. This unit comprises inputs respectively connected to the two outputs s i , s i+1 , . . . , s i+j , . . . , s i+K  of elementary cells FA i , FA i+1 , . . . , FA i+j , . . . FA i+K . This unit also comprises inputs respectively connected to propagation outputs P i+1 , P i+2 , . . . , P i+K  of the propagation calculation unit CP. These outputs are those of ports AND of the calculating means CP which furnish propagation bits, in the form P i+j  =P i+j-1  ·p i+j . Propagation output p i  of first cell FA i  is connected to one of the inputs of calculating means CS, because P i  =p i . This addition calculation unit CS also comprises an input CIN for incoming carrys. 
     The addition calculation unit CS furnishes at its outputs the sum operands of data (a i , b i ), (a i+1 , b i+1 ), . . . (a i+K , b i+K ) received at the input. 
     This unit effects the logic operation: 
     
         S.sub.i+j =s.sub.i+j ⊕(P.sub.i+j-1 ·CIN) by P.sub.i-1 =1. 
    
     The sum calculation unit CS comprises logic AND type ports M i , M i+1 , . . . , M i+j , . . . , M i+K  with two inputs and logic &#34;XOR&#34; type ports XOR i , XOR i+1 , . . . , XOR i+j , . . . , XOR i+K  with two inputs. 
     One input of each AND type port M i+j  receives incoming carry bit CIN, while the other input receives propagation bit P i+j  furnished by the corresponding output of calculation unit CP. Only the first port M i  receives, on the other hand, carry input bit CIN at one input; and on the other hand, a bit having the value 1, at its other input. 
     (see above the relation p i-1  =1) 
     The inputs of each port XOR i+j , are respectively connected to the output of port M i+j , thus corresponding to the second output S i+j  of the corresponding elementary cell. Therefore, port XOR i+1 , for example, is connected to the output of port M i+1  and output s i+1  of elementary cell FA i+1 . 
     This propagation unit easily furnishes addition operands such as S i+j  =s i+j  ⊕(P i+j-1  ·CIN). 
     For S i+j  for example, we have: 
     
         S.sub.i+2 =s.sub.i+2 ⊕(P.sub.i+1 ·CIN) 
    
     For ADP K   1  adders which treat segments of data bits from i through i+K (where i belongs to {1, 2, . . . , n}), the number i depends upon the position of adder ADP K   1  in the series comprising adder AD K   NH . Generally, adders ADP K   1  comprise at least k elementary addition cells. 
     FIG. 4 is a schematic representation of adder AD K   1  of order K and level 1. This adder, while utilizing the recursive structure above described, is in fact comprised of an ADP K   1  adder of order K and level 1, whose incoming carry input CIN receives a bit having a value of 0. One of the outputs of this adder furnishes generation bit G, while its carry propagation output P is not connected. Original adder AD K   1  may or may not have a non-null input CIN depending upon whether one desires a global adder with a null or non-null incoming carry.