Abstract:
A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output current and further includes maintaining a voltage across the output transistor. One embodiment includes conducting a reference current through a diode-coupled first field-effect transistor (FET) and biasing a gate of a second FET matched to the diode-coupled first FET by a voltage equal to a gate voltage of the diode-coupled first FET. A current equal to the reference current is conducted through a third FET having a gate coupled to a drain of the second FET, the third FET matched to the second FET.

Description:
TECHNICAL FIELD  
   The present invention relates generally to current sources, and more specifically, to current mirror circuits providing an output current based on a reference current. 
   BACKGROUND OF THE INVENTION 
   Current mirror circuits are widely used in a variety of electronic circuits to copy or scale a reference current.  FIG. 1  illustrates a conventional p-channel metal-oxide-semiconductor (PMOS) current mirror circuit  100 . Although shown in  FIG. 1  and described below with respect to PMOS transistors, the following discussion applies to n-channel metal-oxide-semiconductor (NMOS) current mirror circuits as well. The current mirror circuit  100  includes a first PMOS transistor  110  coupled to a voltage supply providing voltage Vcc. A drain of the PMOS transistor  110  is coupled to a gate and further coupled to a current source  114  that establishes a reference current Iref through the first PMOS transistor. With the gate and drain of the PMOS transistor  110  coupled together, the drain-source voltage Vds and the gate-source voltage Vgs are equal. Additionally, as known, the PMOS transistor  110  is forced into saturation by coupling the gate to the drain. The current mirror circuit  100  further includes a second PMOS transistor  120  coupled to the voltage supply and having a gate coupled to the gate of the first PMOS transistor  110 . The PMOS transistor  120  is matched to the PMOS transistor  110 , that is, the PMOS transistor  120  has the same transistor characteristics as the PMOS transistor  110 . As a result of the gate coupling and matched transistor characteristics, the Vgs of the PMOS transistor  120  is set to the Vgs of the PMOS transistor  110 , and consequently, the PMOS transistor  120  conducts an output current lout that is equal to Iref. This can be shown by the equation for drain current Ids of a PMOS transistor in saturation:
 
 Ids =(½)μ Cox ( W/L )( Vgs−Vth ) 2   (1)
 
   With PMOS transistors  110  and  120  matched and Vgs for the two PMOS transistors  110 ,  120  the same, Iout (i.e., Ids for PMOS transistor  120 ) will be equal to Iref (i.e., Ids for PMOS transistor  110 ). 
   As known, equation (1) is a simplified equation for drain current that does not account for channel length modulation. In MOS transistors having relatively long channel lengths, channel length modulation can be ignored as in equation (1) and provide a good approximation of drain current. However, for transistors having shorter channel lengths, the effect of channel length modulation on drain current Ids becomes more significant, enough so that changes in Vds for a given Vgs can cause variation of the Ids that is unacceptable in applications that rely on a consistent magnitude of current for Iout. In the current mirror circuit  100 , as previously discussed, the Vgs of the PMOS  120  is set by the PMOS transistor  110  and current source  114 . As previously discussed, if the PMOS  120  has a relatively short channel length, variation in Vds of the PMOS  120  will cause the Iout to vary as well due to channel length modulation. Where it is desirable for Iout to be stable, the variation in Iout may be unacceptable. 
   The Vds of the PMOS  120  can vary for several reasons, for example, fluctuation of Vcc provided by the voltage supply, changes in operating temperature, and the like. Utilizing transistors for the PMOS transistors  110 ,  120  having longer channel length can be used to reduce variations in the Ids current due to reduced effect of channel length modulation. The longer channel length transistors, however, occupy greater space on a semiconductor substrate, and can also having decreased response time in comparison to transistors having shorter channel length. Both of these results are generally viewed as undesirable. 
   Therefore, there is a need for a current mirror circuit that can provide a stable output current when utilized with transistors of different transistor dimensions. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a conventional current mirror circuit. 
       FIG. 2  is a schematic diagram of a current mirror circuit according to an embodiment of the present invention. 
       FIG. 3  is a schematic diagram of a current mirror circuit according to another embodiment of the present invention. 
       FIG. 4  is a schematic diagram of a current mirror circuit according to another embodiment of the present invention. 
       FIG. 5  is a schematic diagram of a current mirror circuit according to another embodiment of the present invention. 
       FIG. 6  is a block diagram of a memory system including a current mirror circuit according to an embodiment of the present invention. 
       FIG. 7  is a block diagram of a processor-based system including the memory system of  FIG. 6 . 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Certain details are set forth below to provide a sufficient understanding of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention. 
     FIG. 2  illustrates a current mirror circuit  200  according to an embodiment of the present invention. The current mirror circuit  200  includes the PMOS transistors  110  and  120  and current reference source  114 , previously described with reference to the conventional current mirror circuit  100  shown in  FIG. 1 . Additionally, the current mirror circuit  200  includes a PMOS transistor  210  to isolate the drain of the PMOS transistor  120  from an output  140 , and further includes a clamp circuit  220  coupled to the power supply Vcc, the node  134 , and the PMOS transistor  210 . The reference current Iref is mirrored to an output current Iout provided at the output  140 . The current mirror circuit  200  is less susceptible to Iout variation caused by channel length modulation than conventionally designed current mirror circuits, such as the current mirror circuit  100 . As previously discussed, changes in Vds across the PMOS transistor  120 , which can be caused by changes in Vcc, temperature, output loading, and the like, results in fluctuations of the Iout current. In order to reduce Iout variation, the clamp circuit  220  included in the current mirror circuit  200  is configured to stabilize Vds across the PMOS transistor  120  to the voltage that is set by the Vds (and Vgs) of the PMOS transistor  110 . The clamp circuit  220  further biases the PMOS transistor  210 , which as previously mentioned, isolates the drain of the PMOS transistor  210  so that the voltage of the node  134  can be clamped. 
     FIG. 3  illustrates the current mirror circuit  200  with a clamp circuit  220  according to an embodiment of the invention. The clamp circuit  220  of  FIG. 3  includes a PMOS transistor  310  and a reference current source  320  providing a reference current Irefc that is equal to Iref provided by the current source  114 . The PMOS transistor  310  is preferably matched to the PMOS transistors  110  and  120 . In operation, the Vgs of the PMOS transistor  310  is set by Irefc. The Vds of the PMOS transistor  120  is stabilized by coupling the gate of the PMOS transistor  310  to the drain of the PMOS transistor  120  thereby setting the Vds of the PMOS transistor  120  to the Vgs of the PMOS transistor  310 . With the PMOS transistor  310  matched to the PMOS transistor  110 , and Irefc equal to Iref, the Vgs of the PMOS transistor  310  is matched to the Vgs of the PMOS transistor  110 , and because the gate and drain are coupled together for the PMOS transistor  110  (i.e., Vgs=Vds of PMOS transistor  110 ), the Vds of PMOS transistor  120  is matched to the Vds of the PMOS transistor  110 . As a result, the Vgs of the PMOS transistor  310  stabilizes the Vds across the PMOS transistor  120  to reduce fluctuations in the Iout current. 
     FIG. 4  illustrates a current mirror circuit  200  with the clamp circuit  220  having a reference current source  320  ( FIG. 3 ) according to an embodiment of the invention. The current source  320  is represented in  FIG. 4  by NMOS transistors  410 ,  430 , and PMOS transistor  420 . The PMOS transistor  420  is matched with the PMOS transistor  310 , and the two NMOS transistors  410 ,  430  are matched to saturated NMOS transistor  414 , which represents the current source  114  in the embodiment of  FIG. 4 . 
   In operation, the PMOS transistor  420  is coupled so that its Vgs is equal to the Vgs of the PMOS transistor  110 , thereby setting the Vds of the PMOS transistor  420  equal to the Vds of the PMOS transistor  110 . As a result, the current through the NMOS transistor  430  will be equal to Iref current through the NMOS transistor  414 . 
   With the gates of the two NMOS transistors  410  and  430  tied together, the Irefc current through the NMOS transistor  410  is equal to the Iref current through the NMOS transistor  414  (i.e., Iref=Irefc). Under this condition, the Vgs of the PMOS transistor  310  is equal to the Vds of the PMOS transistor  110 , which is used to stabilize the Vds of the PMOS transistor  120  and reduce Iout variations, as previously described. 
   In the embodiment shown in  FIG. 4 , the Irefc current through the PMOS transistor  310  can vary as voltage, temperature and loading vary. As known, the Vgs of the PMOS transistor  310  will consequently vary as well. Although the varying Vgs of the PMOS transistor  310  will affect the Vds across the PMOS transistor  120 , which as previously explained causes Iout current variation, the degree of variation of Vgs is less than for an unclamped Vds of the PMOS transistor  120  due to the square-law relationship between drain current and Vgs of the PMOS transistor  310 . This can be shown by the following equations:
 
 I   N2     —     1   −I   N2     —     0   =ΔI   N2 =(½)μ n   Cox ( W   N2   /L   N2 )( Vref−Vtn ) 2 (λΔ V )  (2)
 
   where λ is the channel length modulation coefficient and W N2  and L N2  are the width and length of NMOS  410 . With the PMOS transistor  310  in saturation, the ΔVgs caused by the variations in current can be approximated by
 
Δ Vgs =[2 I   N2     —     1 /μ p   /Cox /( W   P4   /L   P4 )] 1/2 −[2 I   N2     —     0 /μ p   /Cox /( W   P4   /L   P4 )] 1/2   (3)
 
Δ Vgs ≈(½)└μ n   Cox ( W   N2   /L   N2 )/μ p   /Cox /( W   P4   /L   P4 )┘( Vref−Vtn )λ·Δ V   (4)
 
   where W P4  and L P4  are the width and length of PMOS  310  and Vref is the gate voltage of NMOS  410  and NMOS  430 . 
   ΔVds of the PMOS  120  will be the same as the ΔVgs of the PMOS  310 . As a result, making the coefficient of ΔV, that is, the coefficient being equal to
 
(½)└μ n   Cox ( W   N2   /L   N2 )/μ p   /Cox /( W   P4   /L   P4 )┘( Vref−Vtn )λ  (5)
 
   much smaller than 1 can reduce the ΔVds of the PMOS  120 . As a result, as previously discussed, variation in Iout caused by channel length modulation can be reduced. 
   The previously described embodiments are PMOS current mirror circuits. However, alternative embodiments of the present invention include NMOS-current mirror circuits having voltage clamp circuitry to stabilize the output current. For example,  FIG. 5  illustrates an NMOS current mirror circuit  500  including NMOS transistor  510  having a drain coupled to a gate, and further coupled to a current source  514  that provides a reference current Iref. An NMOS transistor  520  has a gate coupled to the gate of the NMOS transistor  510  to set the gate voltage. An NMOS transistor  530  is coupled to isolate a drain of the NMOS transistor  520  from an output  560 . A clamp circuit  540  is coupled to a node  534  and is configured to stabilize Vds across the NMOS transistor  520  to the voltage that is set by the Vds (and Vgs) of the NMOS transistor  510 , thereby stabilizing Iout. Although the circuitry of the clamp circuit  540  is not specifically shown in  FIG. 5 , it will be appreciated that those ordinarily skilled in the art will obtain sufficient understanding from the description provided herein to practice the invention with NMOS current mirror circuits. 
     FIG. 6  illustrates a memory system  600  including a current mirror circuit  610  according to an embodiment of the present invention. In one embodiment, the memory system  600  is included in a memory device. In an alternative embodiment, the memory system  600  is an embedded memory system. The memory system  600  includes a memory array  642 , row and column decoders  644 ,  648  and a sense amplifier circuit  646 . The current mirror circuit  610  is coupled to the sense amplifier circuit  646  to provide an output current Iout that is used as a reference current when sensing data from memory cells of the memory array  642 , as will be described in more detail below. The memory array  642  includes a plurality of NOR flash memory cells (not shown) coupled to word lines  680  and digit lines  660  that are arranged into rows and columns, respectively. The digit lines  660  are connected to the sense amplifier circuit  646 , while the word lines  680  are connected to the row decoder  644 . 
   In operation, address and control signals, provided on address/control lines  661  coupled to the column decoder  648 , sense amplifier circuit  646  and row decoder  644 , are used, among other things, to gain read and write access to the memory array  642 . The column decoder  648  is coupled to the sense amplifier circuit  646  via control and column select signals on column select lines  662 . The sense amplifier circuit  646  receives input data to be written to the memory array  642  and outputs data read from the memory array  642  over input/output (I/O) data lines  663 . Data is read from the cells of the memory array  642  by activating a word line  680  (via the row decoder  644 ), which couples all of the memory cells corresponding to that word line to respective digit lines  660 . One or more digit lines  660  are also activated. When a particular word line  680  and digit line  660  are activated, the sense amplifier circuit  646  coupled to respective digit line detects and amplifies the conduction sensed through a given NOR flash memory cell by comparing a digit line current to a reference current. As previously mentioned, the reference current is provided by the current mirror circuit  610 . Based on the comparison, the sense amplifier circuit  646  generates an output indicative of either “1” or “0” data. The previous description is a summary of the operation of the memory system  600 . Operation of NOR flash memory cell-based memory systems, such as the memory system  600 , is well known in the art, and a more detailed description has not been provided in order to avoid unnecessarily obscuring the invention. 
     FIG. 7  is a block diagram of a processor-based system  700  including the NOR flash memory system  600  of  FIG. 6 . The processor-based system  700  may be a computer system, a process control system, an embedded system, or any other system employing a processor and associated memory. The system  700  includes a central processing unit (CPU)  702 , such as a microprocessor, that communicates with the NOR flash memory  600  and an I/O device  708  over a bus  720 . The bus  720  may be a series of buses and bridges commonly used in a processor-based system. A second I/O device  710  is illustrated in  FIG. 7 , but is optional. The processor-based system  700  may also include one or more data storage devices, such as disk drive  704  and CD-ROM drive  706 , to allow the CPU  702  to store data in or retrieve data from internal or external storage media. Additional examples of typical storage devices include flash drives and digital video disk read-only memories (DVD-ROMs). 
   It will be understood that the embodiments shown in  FIGS. 6 and 7  are intended to provide examples of applications for embodiments of the present invention, and are not intended to serve as a complete description of all the elements and features of an electronic system including a current mirror circuit according to an embodiment of the invention. 
   From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.