Abstract:
A voltage generator reduces a stand by current in a stand by or a self-refresh mode and shortens a response time in an active mode by selectively driving a control transistor of a final driver. A core voltage control unit provides a power voltage. Pull-up and pull-down driving signals are generated based on the power voltage. An output driver generates an internal voltage according to the pull-up and pull-down driving signals. An active control unit controls drivability of the core voltage control unit in response to bank active signals.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a semiconductor memory device; and, more particularly, to a bit-line precharge voltage (VBLP) or a cell plate voltage (VCP) generator reducing a stand-by current in a stand-by mode or a self-refresh mode and shortening a response time in an active mode by selectively driving a control transistor of a output driver. 
   DESCRIPTION OF RELATED ARTS 
   A semiconductor memory device often has a low-grade drivability according to varied conditions under a fabrication process. If drivability for an internal voltage is decreased, a level of the internal voltage can fluctuate and, thereby, the unstable internal voltage can cause malfunction of the semiconductor memory device. Because higher integration of the semiconductor memory device increases alternations or limitations on the fabrication process, a level of a core voltage (VCORE) can be decreased and drivability for the VBLP and the VCP in the semiconductor memory device lessens. 
     FIG. 1  is a schematic circuit diagram of a conventional VBLP generator. 
   The conventional voltage generator includes a core voltage control unit  10  and an output driver  20 . The core voltage control unit  10  includes a core voltage generator  11 , a bias voltage generator  12 , a gate voltage generator  13 , and pull-up and pull-down voltage drivers  14  and  15 . 
   The core voltage generator  11  induces a half core voltage used as a reference for generating the VBLP and the VCP. The core voltage generator  11  is provided with PMOS transistors P 1  and P 2  and resistors R 1  and R 2  connected in series between the VCORE and a ground voltage (VSS), generating a reference voltage VREF by embodying a voltage divider having self bias diode resistors and line resistors. When a power voltage is supplied from an external device, the reference voltage VREF is generated by the voltage divider described in  FIG. 1 . Otherwise, if the power voltage is supplied internally, the reference voltage VREF can be generated by a reference voltage generator included in another device. 
   The bias voltage generator  12  generates bias voltages PBIAS and NBIAS based on the reference voltage VREF. The bias voltage generator  12  includes PMOS transistors P 3  to P 5  and NMOS transistors N 1  to N 5 . The third PMOS transistor P 3  and the first and the third NMOS transistors N 1  and N 3 , connected in series between the VCORE and the VSS, provide a predetermined current flow to a terminal supplied with the VSS. A gate of the third PMOS transistor P 3  receives the reference voltage VREF, and a gate and a drain of each of the first and the third NMOS transistors N 1  and N 3  are coupled 
   The fourth PMOS transistor P 4  and the second and the fourth NMOS transistors N 2  and N 4 , connected in series between the VCORE and the VSS, form a current mirror for providing a predetermined current from a terminal supplied with the VCORE. A gate and a drain of the fourth PMOS transistor P 4  are coupled together. Gates of the first and the second NMOS transistors N 1  and N 2 , and gates of the third and the fourth NMOS transistors N 3  and N 4  are coupled respectively. Accordingly, the current through the first and the third NMOS transistors N 1  and N 3  is same as the current through the second and the fourth NMOS transistors N 2  and N 4 . 
   The fifth PMOS transistor P 5  connected between the VCORE and a seventh NMOS transistor N 7  forms a current mirror with the fourth PMOS transistor P 4 , wherein gates of the fourth and the fifth PMOS transistors P 4  and P 5  are coupled. A gate of the fifth NMOS transistor N 5 , connected between the VSS and a seventh PMOS transistor P 7 , is supplied with the bias voltage NBIAS. 
   The gate voltage generator  13  has a current mirror structure provided with NMOS transistors N 7  and N 8 , wherein a gate voltage NGATE is produced, and PMOS transistors P 7  and P 8 , wherein a gate voltage PGATE is produced. The gate voltage generator  13  generates the gate voltages NGATE and PGATE. The gate voltage NGATE is higher than the reference voltage VREF by a threshold voltage of the seventh NMOS transistor N 7 . The gate voltage PGATE is lower than the reference voltage VREF by a threshold voltage of the seventh PMOS transistor P 7 . 
   The pull-up voltage driver  14  includes a sixth PMOS transistor P 6 . A gate of the sixth PMOS transistor P 6 , connected between the VCORE and the eighth NMOS transistor N 8 , receives the bias voltage PBIAS. 
   The pull-down voltage driver  15  includes a sixth NMOS transistor N 6 . A gate of the sixth NMOS transistor N 6 , connected between the VSS and the eighth PMOS transistor P 8 , receives the bias voltage NBIAS. 
   The output driver  20  further includes a ninth PMOS transistor P 9  and a ninth NMOS transistor N 9 . The ninth PMOS transistor P 9  and the ninth NMOS transistor N 9 , whose gates respectively receive pull-up and pull-down driving signals PDRV and NDRV, and drains coupled with each other to output the VBLP, are connected in series between the VCORE and the VSS. 
   The operation process of the conventional voltage generator is described below. 
   The PMOS transistor P 6  is always turned on and serves as a resistor and thereby maintains a constant current. The eighth NMOS transistor N 8  functions as a source follower operating fast according to the level of the VBLP. 
   If the VBLP is decreases, the gate voltage NGATE of the eighth NMOS transistor N 8  is higher than a source voltage of the eighth NMOS transistor N 8 . Accordingly, the current flows fast through the eighth NMOS transistor N 8 , and a level of the pull-up driving signal PDRV decreases. Thus, the ninth PMOS transistor P 9  is turned on and increases the level of the VBLP. 
   The sixth NMOS transistor N 6  is always turned on and serves as a resistor and thereby maintains a constant current. The eighth PMOS transistor P 8  functions as a source follower operating fast according to the level of the VBLP. 
   If the VBLP is increases, the gate voltage PGATE of the eighth PMOS transistor P 8  is lower than a source voltage of the eighth PMOS transistor P 8 . Accordingly, the current flows fast through the eighth PMOS transistor P 8 , and a level of the pull-down driving signal NDRV increases. Thus, the ninth NMOS transistor N 9  is turned on and decreases the level of the VBLP. 
   In the conventional voltage generator, the output driver  20  is provided with the ninth PMOS transistor P 9  and the ninth NMOS transistor N 9  having a slim low threshold voltage in order to prevent decrease or drop of drivability when an internal power voltage has a low level. While the operation is improved in active and read/write modes, a large amount of off leakage currents flow in a precharge mode. 
   When the threshold voltage of the ninth PMOS transistor P 9  or the ninth NMOS transistor N 9  is less than the standard, a precharge, i.e., stand-by, current is generated by a large amount of off leakage currents. Particularly, in low-power and mobile products wherein existence of the stand-by current is critical, a serious malfunction or ineffective performance may result. 
   When drivability of the sixth PMOS transistor P 6  and the sixth NMOS transistor N 6  is increased to reduce the leakage current of the output driver, i.e., the ninth PMOS transistor P 9  or the ninth NMOS transistor N 9 , drivability of the ninth PMON transistor P 9  and the ninth NMOS transistor N 9  is decreased respectively in the active mode. 
   When the VBLP is unstable in the stand-by mode, the output driver  20  turns on fast, because the eighth PMOS transistor P 8  operates as the source follower. However, the output driver  20  turns off late, because a minimum current is supplied for reducing the stand-by current. 
   Accordingly, the on and off timings of the output driver are mismatched. When the ninth PMOS transistor P 9  and the ninth NMOS transistor N 9  turn on at the same time, current flows directly. 
   The direct current in operation mode as well as the stand-by current generates a ringing current in stand-by or operation mode and makes the drivability of the chip poor. 
   SUMMARY OF THE INVENTION 
   It is, therefore, an object of the present invention to provide a method for reducing a stand-by current and shortening a response time in a semiconductor memory device by controlling transistors included in an output driver in a stand-by or a self refresh mode and an active mode. 
   In accordance with an aspect of the present invention, there is provided a voltage generator, including a core voltage control unit for generating pull-up and pull-down driving signals based on a power voltage, a output driver for generating an internal voltage according to the pull-up and pull-down driving signals, and an active control unit for controlling a drivability of the core voltage control unit in response to bank active signals 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a schematic circuit diagram of a conventional voltage generator; 
       FIG. 2  is a schematic circuit diagram of a voltage generator in accordance with the present invention; 
       FIG. 3  is a schematic circuit diagram of an active controller shown in  FIG. 2 ; 
       FIG. 4  is a schematic circuit diagram of the active controller shown in  FIG. 2  in accordance with another embodiment; and 
       FIG. 5  is a waveform explaining an operation of the voltage generator in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Hereinafter, a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings. 
     FIG. 2  is a schematic circuit diagram of a voltage generator in accordance with the present invention. 
   The voltage generator includes a core voltage control unit  50 , an output driver  500  and active control units  100  to  400 . 
   The core voltage control unit  50  includes a core voltage generator, a bias voltage generator, a gate voltage generator, and pull-up and pull-down voltage drivers. 
   The core voltage control unit  50  and the output driver  500  have the same composition as the conventional embodiment of  FIG. 1 . Further detailed explanation of the composition and operation thereof, therefore, is omitted. 
   The present invention additionally includes active control units provided with first and second active controllers  100  and  300  and first and second selecting drivers  200  and  400 . 
   The first active controller  100  activates each bank in response to bank active signals B_atv&lt; 0 :n&gt; by a driving control signal. 
   The first selecting driver  200  includes tenth and eleventh PMOS transistors P 10  and P 11 , first and second inverters IV 1  and IV 2  and a first transmission gate T 1 . The first inverter IV 1  inverts an output of the first active controller  100 . The tenth PMOS transistor P 10 , connected between a VCORE and the first transmission gate T 1 , receives an output of the first inverter IV 1  through a gate. A gate of the eleventh PMOS transistor P 11 , connected between the VCORE and the pull-up driving signal PDRV, is coupled with a drain of the tenth PMOS transistor P 10 . 
   The second inverter IV 2  inverts an output of the first inverter IV 1 . The first transmission gate T 1  selectively connects the drain of the tenth PMOS transistor P 10  with the bias voltage PBIAS in response to outputs of the first and the second inverters IV 1  and IV 2 . 
   Similarly, the active controller  300  activates each bank in response to the bank active signals B_atv&lt; 0 :n&gt; by a driving control signal. 
   The second selecting driver  400  includes tenth and eleventh NMOS transistors N 10  and N 11 , third and fourth inverters IV 3  and IV 4  and a second transmission gate T 2 . The third inverter IV 3  inverts an output of the active controller  300 . The tenth NMOS transistor N 10 , connected between a VSS and the second transmission gate T 2 , receives an output of the fourth inverter IV 4  through a gate. A gate of the eleventh NMOS transistor N 11 , connected between the VSS and the pull-down driving signal NDRV, is coupled with a drain of the tenth NMOS transistor N 10 . 
   The fourth inverter IV 4  inverts an output of the third inverter IV 3 . The second transmission gate T 2  selectively connects the drain of the tenth NMOS transistor N 10  with the bias voltage NBIAS in response to outputs of the third and the fourth inverters IV 3  and IV 4 . 
     FIG. 3  is a schematic circuit diagram of the first active controllers  100  shown in  FIG. 2 . 
   The first and second active controllers  100  and  300  have the same elements. The detailed composition of the active controller  100  is explained as embodiment of the present invention. As a modification, only one of the first and the second active controllers can generate control signals to both the first and the second selecting drivers  200  and  400 . 
   The active controller  100  includes a first NOR gate NOR 1 , inverters IN 5  to IV 8  and a first NAND gate ND 1 . The first NOR gate NOR 1  outputs a signal A_sig after performing a logic NOR operation to bank active signals B_atv&lt; 0 &gt; to B_atv&lt; 3 &gt;. Delaying an output of the first NOR gate NOR 1  in a delay time DEL 1 , the fifth to the eighth inverters IN 5  to IN 8  output a signal B_sig. The first NAND gate ND 1  performs a logic NAND operation to the signal A_sig and the signal B_sig to thereby output a signal C_sig. 
     FIG. 4  is a schematic circuit diagram of the active controller shown in  FIG. 2  in accordance with another embodiment. 
   The active controller  100 A includes a plurality of NOR gates NOR 2  to NORn (n is a positive integer), first and second NAND gates ND 2  and ND 3  and a plurality of inverters IN 9  to IV 13 . 
   The NOR gate NOR 2  performs a logic NOR operation to the first and second bank active signals B_atv&lt; 0 &gt; and B_atv&lt; 1 &gt;. The NOR gate NOR 3  performs a logic NOR operation to the third and fourth bank active signals B_atv&lt; 2 &gt; and B_atv&lt; 3 &gt;. The NOR gate NORn performs a logic NOR operation to bank active signals B_atv&lt;n- 1 &gt; and B_atv&lt;n&gt; 
   The first NAND gate ND 2  performs a logic NAND operation to outputs of the NOR gates NOR 2  to NORn. The fifth inverter IN 9  inverts an output of the first NAND gate ND 2 . The inverters V 10  to IV 13  delay an output of the fifth inverter IV 9 . The second NAND gate ND 3  performs a logic NAND operation to the output of the fifth inverter IV 9  and an output of the inverter IV 13 . 
   Referring to  FIG. 5 , the operation process of the present invention is described below. 
   The bias voltage PBIAS is lower than the VCORE by a threshold voltage VT of the sixth PMOS transistor P 6 . The bias voltage PBIAS is supplied to the sixth PMOS transistor P 6  in order to generate a predetermined current flowing through the sixth PMOS transistor P 6 . The bias voltage NBIAS is higher than the VSS by the threshold voltage VT of the sixth NMOS transistor N 6 . The bias voltage NBIAS is supplied to the sixth NMOS transistor N 6  to generate a predetermined current flowing through the sixth NMOS transistor N 6 . 
   The eighth NMOS transistor N 8  and the eighth PMOS transistor P 8  having sources connected to the VBLP operate fast according to the level of the VBLP. Each of the eighth NMOS transistor N 8  and the eighth PMOS transistor P 8  served as a source follower turns on/off each of the ninth PMOS transistor P 9  and the ninth NMOS transistor N 9  respectively, according to the level of the VBLP. 
   In order to improve drivability of an output terminal in an active mode and reduce a leakage current in a stand-by mode, the present invention changes the number of the conventional transistors controlling the output driver  500  according to stand-by and active modes. 
   In the stand-by mode, by operating the sixth and the eleventh PMOS transistors P 6  and P 11  and the sixth and the eleventh NMOS transistors N 6  and N 11 , the drivability of the output terminal decreases. Accordingly, the consumption of the stand-by current is reduced. 
   The bank active signals B_atv&lt; 0 :n&gt; have a logic low level in the stand-by mode. The driving control signal output by the active controller  100  has a logic low level. 
   Accordingly, the first transmission gate T 1  turns on, and gates of the sixth and eleventh PMOS transistors P 6  and P 11  are coupled. The tenth PMOS transistor P 10  receiving a logic high level signal through a gate persists to turn off. The sixth and eleventh PMOS transistors P 6  and P 11  turn on by the bias voltage PBIAS. 
   Similarly, the driving control signal output by the active controller  300  has a logic low level by all the bank active signals B_atv&lt; 0 :n&gt; having a logic low level. 
   Accordingly, the transmission gate T 2  turns on, and gates of the sixth and eleventh NMOS transistor N 6  and N 11  are coupled. The tenth NMOS transistor N 10  receiving a logic low level signal through a gate persists to turn off. The sixth and eleventh PMOS transistor N 6  and N 11  turn on by the bias voltage NBIAS. 
   In active mode, the eleventh PMOS transistor P 11  and the eleventh NMOS transistor N 11  turn off, and the sixth PMOS transistor P 6  and sixth NMOS transistor N 6  turn on according to the outputs of the active controllers  100  and  300 . A current output to the output driver  500  increases, which continues on for a longer period than an active mode period in the other devices. Increasing drivability of the output driver  500 , the operation process improves in the active mode consequently. 
   The active controllers  100  and  300  receive and perform a logic NOR operation to the bank active signals B_atv&lt; 0 :n&gt; representing an active period of each bank. Referring to  FIG. 5 , in the event that at least one of the bank active signals B_atv&lt; 0 :n&gt; is activated, the output signal A_sig of the first NOR gate NOR 1  has a logic low level. The signal A_sig has a logic low level in the whole active period of the banks, and the signal B_sig delayed by the delay time DEL 1  of the sixth and seventh inverters IV 6  and IV 7  has a logic low level. 
   Consequently, the output signal C_sig of the active controllers  100  and  300  is activated in synchronization with inactivation of the signal A_sig, and is inactivated in synchronization with activation of the signal B_sig. The signal C_sig is activated during the inactivation period of the signal A_sig and the delay time DEL 1 . During the activation period of the signal C_sig in the active mode, the drivability of the transistors in the pull-up and the pull-down voltage drivers decease. 
   The delay time DEL 1  is pre-determined time by the sixth and seventh inverters IV 6  and IV 7 . 
   When at least one of the bank active signals B_atv&lt; 0 :n&gt; is activated, the driving control signal output from the active controller  100  is activated. 
   The first transmission gate T 1  turns off and the tenth PMOS transistor P 10  turns on. The eleventh PMOS transistor P 11  receiving the VCORE through the gate keeps a turn-off state. 
   Similarly, When at least one of the bank active signals B_atv&lt; 0 :n&gt; is activated, the driving control signal output from the active controller  300  is activated. 
   The second transmission gate T 2  turns off and the tenth NMOS transistor N 10  turns on. The eleventh PMOS transistor N 11  receiving the VSS through the gate persists to turn off. 
   The active controller  100  for pull-up driving and the active controller  300  for pull-down driving having the same delay time are described above. However, the delay times of the active controllers  100  and  300  could be set up differently in the present invention. 
   Described above, the present invention has an effect on reducing the leakage current for guaranteeing an output margin in the stand-by mode and improving drivability of the output terminal to stabilize a DRAM operation in active mode by selectively driving a transistor controlling the output driver in both the stand by or the self refresh mode and the active mode. 
   The present application contains subject matter related to Korean patent applications Nos. 10-2005-0091569 and 10-2006-0029654, filed in the Korean Patent Office on Sep. 29, 2005 and Mar. 31, 2006, respectively, the entire contents of which are incorporated herein by reference. 
   While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.