Abstract:
A method for calibrating a resistance value comprises the steps of measuring a value of a reference capacitor, and adjusting a variable resistor based on the measured value of the reference capacitor. The method may more specifically comprise the steps of directing a constant current through the reference capacitor during a reference time interval; after the reference time interval, directing the constant current through the variable resistor; and varying the variable resistor value progressively by varying a control signal until a voltage of the variable resistor reaches a voltage of the reference capacitor.

Description:
BACKGROUND 
     Technical Field 
     The present disclosure relates to the realization of accurate resistors in integrated circuits. 
     Description of the Related Art 
     Certain integrated circuit devices require accurate resistors to perform their functions. In current integrated circuit manufacturing technologies, resistors may be fabricated as polysilicon tracks whose width and length are specified by design to achieve the desired resistance value. The resistance value is however temperature and process dependent, and may be subject to a typical dispersion of approximately ±15% relative to the specified value. When a better accuracy is needed, the resistors are generally adjusted individually during post-fabrication trimming operations, which increases the manufacturing cost. 
     BRIEF SUMMARY 
     A method is provided in the present disclosure for calibrating a resistance value comprising the steps of measuring a value of a reference capacitor, and adjusting a variable resistor based on the measured value of the reference capacitor. 
     The method may comprise more specifically the steps of: 
     directing a constant current through the reference capacitor during a reference time interval; 
     after the reference time interval, directing the constant current through the variable resistor; and 
     varying the variable resistor value progressively by varying a control signal until a voltage of the variable resistor reaches a voltage of the reference capacitor. 
     A circuit is also provided in the present disclosure for calibrating a resistance value, comprising: 
     a reference capacitor; 
     a variable resistor; and 
     control circuitry configured to measure the value of the reference capacitor and accordingly adjust the variable resistor. 
     The circuit may more specifically comprise: 
     a constant current source; 
     a switch configured to direct the constant current through the reference capacitor in a first position and to direct the constant current through the variable resistor in a second position; and 
     a control circuit configured to:
         set the switch in the first position during a reference time interval,   set the switch in the second position, and   control the variable resistor through a progressively varying control signal until a voltage of the variable resistor reaches a voltage of the reference capacitor.       

    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of an embodiment of a resistor calibration circuit according to the invention. 
         FIG. 2  is a time diagram illustrating an exemplary operation of the calibration circuit of  FIG. 1 . 
         FIG. 3  is a circuit diagram of an embodiment of an adjustable resistor usable in the circuit of  FIG. 1 . 
         FIG. 4  is a circuit diagram of another embodiment of an adjustable resistor usable in the circuit of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     In integrated circuits, certain types of capacitors can be manufactured with significantly better accuracy than resistors. This is the case of MOS capacitors, for instance. A MOS capacitor is formed by the conductive elements on either side of the gate oxide of a MOS transistor, i.e. the gate metallization on one side, and the channel, source and drain regions on the opposite side. The value of a MOS capacitor is subject to a typical dispersion as low as ±2% with respect to a value specified by design, mainly thanks to the accuracy of the oxide layer thickness. Indeed, the gate oxide thickness has a significant influence on transistor characteristics, which is why integrated circuit manufacturing processes are designed to offer accurate control over the oxide thickness. 
     It is proposed in the present disclosure to auto-calibrate a variable resistor using the value of a capacitor as a reference, especially a MOS capacitor. As a consequence, an accuracy close to that of a MOS capacitor may be obtained for the variable resistor after the calibration procedure. The auto-calibration procedure may take place each time the integrated circuit is powered on, or on a regular basis for an integrated circuit that may undergo significant temperature variations during operation. 
       FIG. 1  is a schematic diagram of an embodiment of a resistor calibration circuit. It includes a programmable resistor R connected to a ground line Vss. The value of resistor R may be adjusted by a control signal Adj provided by a control circuit  10 . A reference MOS capacitor MC is shown in the form of a P-MOS transistor having its source, drain and bulk terminals connected to a stabilized positive power supply line Vdd. The gate of transistor MC is connected to the ground line Vss through a switch in the form of an N-MOS transistor M 1 . A purpose of transistor M 1  is to charge the capacitor MC to voltage Vdd. The gate of the transistor M 1  is controlled by a reset signal RS issued by circuit  10 . 
     A P-MOS transistor connected to line Vdd, as shown, will operate during the calibration phase with a large gate-source voltage, in a region offering a capacitance that is constant and independent of the gate-source voltage variations. If an N-MOS transistor connected to line Vss is used instead, it may come to operate under low gate-source voltages that can cause a capacitance variation. 
     A constant current source Ir is connected between the line Vdd and a switch S. The switch S, controlled by circuit  10 , is configured to direct the current Ir through capacitor MC in a first position, and to direct the current Ir through resistor R in a second position. 
     A comparator  12  is connected to activate an end-of-calibration signal EOC when the voltage across the resistor R reaches the voltage at the node between the capacitor MC and the transistor M 1 . 
       FIG. 2  is a time diagram illustrating an exemplary operation of the circuit of  FIG. 1 . It shows the reset signal RS controlling the switch M 1 , the signal S controlling the switch S, the end-of-calibration signal EOC, the voltage Vr across the resistor R, the voltage Vmc at the node between the capacitor MC and switch M 1 , and the values of the resistor adjustment signal Adj. 
     Initially, outside a calibration phase, both signals R and S are low, whereby switch M 1  is open and switch S couples the current source Ir to capacitor MC. The voltage Vmc is pulled to a level slightly below Vdd, corresponding to the voltage drop across current source Ir. The current source Ir is in a low consumption mode because it cannot deliver its current. The voltage Vr across the resistor R is zero. 
     At a time t 0 , a calibration phase is initiated. The signal RS goes high during a clock cycle, up to a time t 1 , resetting the capacitor MC by bringing voltage Vmc to 0. 
     From time t 1 , the voltage Vmc increases linearly according to the relation Vmc=Ir·t/Cmc, where Cmc is the value of capacitor MC and t is time. 
     A time t 2  occurs a reference interval Tref after time t 1 . At time t 2 , the signal S goes high, setting switch S in its second position, where the current source Ir biases the resistor R. The capacitor MC is in a floating mode and maintains the voltage Vmc reached at time t 2 . This voltage is equal to: 
     
       
         
           
             
               
                 
                   Vmc 
                   = 
                   
                     
                       Ir 
                       Cmc 
                     
                     ⁢ 
                     Tref 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     The resistor control signal Adj may be at a level selecting the lowest value of resistor R. The signal Adj may be digital, for example a 4-bit signal, as shown. The lowest value of resistor R in its adjustment range may then be selected by Adj=0000. The voltage Vr exhibits a step equal to Ir·R(0000), where R(0000) is the value of resistor R for Adj=0000. 
     From time t 2 , the control circuit  10  progressively increases the value of resistor R, for instance by incrementing the binary value Adj in consecutive clock cycles, as shown, causing a stepwise increase of the voltage Vr. 
     At a time t 3 , the voltage Vr rises above the voltage Vmc. This event is detected by comparator  12 , causing signal EOC to go high. The calibration procedure is ended by the control circuit  10  and the value reached by the control signal Adj ( 0101 ) is stored. 
     At a time t 4 , signal S goes low, placing switch S back in its first position. The current source Ir is connected again to the capacitor MC—the voltage Vmc resumes its linear rise up to a value close to Vdd, eventually crossing the voltage Vr and causing signal EOC to go low again. The resistor R is in a floating mode and may be connected to circuitry that requires it. The stored value of signal Adj is applied to resistor R, which thus maintains the resistance value reached at time t 3  throughout the operation phase of the integrated circuit, or until a next calibration phase. 
     The value of voltage Vr achieved at time t 3  is expressed by
 
 Vr=Ir·R ( Adj )
 
     This value is also substantially equal to the value of voltage Vmc reached at time t 2 , expressed by equation (1), whereby 
     
       
         
           
             
               Ir 
               · 
               
                 R 
                 ⁡ 
                 
                   ( 
                   Adj 
                   ) 
                 
               
             
             = 
             
               
                 Tref 
                 Cmc 
               
               ⁢ 
               Ir 
             
           
         
       
     
     The current Ir disappears from this equation, yielding 
     
       
         
           
             
               R 
               ⁡ 
               
                 ( 
                 Adj 
                 ) 
               
             
             = 
             
               Tref 
               Cmc 
             
           
         
       
     
     The calibration circuit thus produces a resistance value depending only on a time (Tref) and a MOS capacitor value (Cmc). The time Tref may be specified in clock periods of a time base and have an accuracy of a few ppms. The value Cmc, of a MOS capacitor, may be specified by design and achieve a typical accuracy of ±2%. Therefore the desired resistance value R(Adj) may achieve an accuracy close to ±2% provided the adjustment steps are within the ±2% range. 
       FIG. 3  is a schematic diagram of a first embodiment of a pair of matched digitally controlled resistors. The variable resistor R, usable in the circuit of  FIG. 1 , is shown on the left side of the figure. It is configured, as an example, to be adjustable between 0.85R and 1.13125R, where R is the value specified by design, which may differ from the value actually achieved. The value of the resistor may be varied in fifteen steps of 0.01825R, selected by a 4-bit adjustment signal Adj. 
     More specifically, the variable resistor R comprises five fixed-value resistors connected in series. A first one, connected to line Vss, is specified to value 0.85R. The second to fifth resistors are specified to values in geometric progression, respectively 0.15R, 0.075R, 0.0375R, and 0.01875R. Each of the second to fifth resistors has a respective switch connected across it, controlled by a corresponding bit of the adjustment signal Adj, wherein the least significant bits control the switches assigned to the lower value resistors. 
     A variable resistor R as shown on the left side of  FIG. 3  will usually be specified to a value compatible with the calibration device, i.e. with the values chosen for the constant current Ir and the reference interval Tref. Such a value may not be adapted to all situations, for instance, when lower or higher resistance values are desired. Moreover, many applications may require multiple accurate resistors, in which case it may be inconvenient to provide a calibration circuit for each resistor. 
       FIG. 3  shows an approach that may be used for calibrating multiple resistors with a single calibration circuit. The resistors may moreover have any specified value. This approach is based on the fact that resistors fabricated on a same die are usually matched, i.e. although the absolute values of the resistors may be subject to significant dispersion, the ratios of the resistor values remain unchanged. 
     The variable resistor R on the left of  FIG. 3  may be used in the calibration circuit to find and store the correct value of the adjustment signal Adj. The stored adjustment value is then used to control in parallel multiple variable resistors having the same structure, such as a variable resistor R′ shown on the right, specified to a value R′. The variable resistor R′, not used during the calibration phase like resistor R, may be permanently connected between any two nodes N 1 , N 2  of a circuit. 
     In practice, the switches connected across the fixed resistors have a certain on-resistance. When connected in series like in  FIG. 3 , the sum of the on-resistances of the switches may be non-negligible with respect to the specified value R′, especially if the specified value R′ is low and the adjustment step is chosen small by increasing the resolution of signal Adj together with the number of fixed resistors in series. 
       FIG. 4  is a schematic diagram of an embodiment of a digitally controlled resistor R′ that may be used when the on-resistance of the switches becomes non-negligible. The variable resistor comprises five fixed-value resistors connected in parallel, in this example. A first one, connected between nodes N 1 , N 2 , is specified to a value 1.15R′. The second to fifth resistors are specified to values in geometric progression, respectively 48R′, 24R′, 12R′, and 6R′. Each of the second to fifth resistors has a respective switch connected in series, controlled by a corresponding bit of the adjustment signal Adj, wherein the least significant bits control the switches assigned to the higher value resistors. 
     With this configuration, the stepwise increments are not equal, causing a non-linear progression of the resulting resistor value with respect to the control signal Adj. This has no consequence, provided all the variable resistors controlled by the calibration circuit have the same structure, and the largest step is smaller than the desired accuracy. 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. 
     For instance, during the calibration phase, the variable resistor may be controlled so that its value progressively decreases instead of being increased.