Abstract:
A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which reduces ohmic contact between a metal line and a substrate.  
           [0003]    2. Background of the Related Art  
           [0004]    A related art method for manufacturing a semiconductor device will be described with reference to FIGS. 1 a  to  1   e.    
           [0005]    As shown in FIG. 1 a , a chemical vapor deposition (CVD) oxide film  12  is formed on a semiconductor substrate  11 . A photoresist  13  is deposited on the CVD oxide film  12  and then patterned by exposure and developing processes to define a contact region.  
           [0006]    Subsequently, the CVD oxide film  12  is selectively removed to partially expose a surface of the semiconductor substrate  11  using the patterned photoresist  13  as a mask, so that a contact hole  14  is formed.  
           [0007]    As shown in FIG. 1 b , the photoresist  13  is removed and then a titanium (Ti) film  15  and a titanium nitride (TiN) film  16  are sequentially formed on an entire surface of the semiconductor substrate  11  including the contact hole  14 .  
           [0008]    The Ti film  15  is reacted with the semiconductor substrate  11  to form a silicide, which acts as a having low resistance ohmic contact. The TiN film  16  prevents a line layer, formed later in the process, from being diffused into the substrate.  
           [0009]    As shown in FIG. 1 c , an annealing process is performed in the semiconductor substrate  11  to react silicon (Si) of the semiconductor substrate  11  with Ti of the Ti film  15 , so that a silicide film  17  is formed on the interface between the semiconductor substrate  11  and the Ti film  15 .  
           [0010]    To form a film of C-54 silicide, annealing at temperature of 850° C. or more is required. However, annealing is actually performed at about 700° C. thus forming C-49 silicide. The resistance of C-49 silicide film is roughly 4˜5 times higher than C-54 silicide film.  
           [0011]    As shown in FIG. 1 d , a first metal layer (not shown) is formed on the entire surface of the semiconductor substrate  11 . The first metal layer is planarized by etch back process or chemical mechanical polishing (CMP) process to form a plug  18  in the contact hole  14 .  
           [0012]    When forming the plug  18 , the CVD oxide film  12  is used as an etching end point to perform etch back process or CMP process. The Ti film  15  and the TiN film  16  over the CVD oxide film  12  are selectively removed in the etching process.  
           [0013]    As shown in FIG. 1 e , a second metal layer is formed, on the plug  18  and the CVD oxide film  12 , to be electrically connected with the semiconductor substrate  11  through the plug  18 . The second metal layer is then selectively removed to form a metal line  19 .  
           [0014]    However, the related art method for manufacturing a semiconductor device has several problems.  
           [0015]    First, because the annealing process is performed below 850° C., the silicide film of high resistance is formed. Thus, it is difficult to minimize the resistance of the wilicide layer, i.e., to produce a good ohmic contact.  
           [0016]    Second, when compared with the Si, Ti reacts quicker with dopants such as P, As, and B causing dopant loss on the interface between the silicide film and the substrate during the annealing process. This dopant loss results in further increase in resistance, i.e., it degrades the quality of the ohmic contact. Also Ti reacts differently with As, P, and B, resulting in different electrical characteristics in N type and P type substrates.  
           [0017]    Third, the silicide film degrades at a temperature of about 750° C. or more. It is difficult to perform annealing process into the silicide film at high temperature due to low thermal stability of the silicide film.  
           [0018]    Fourth, since the silicide film is formed unevenly, poor contact occurs.  
           [0019]    Finally, the TiN, used as a diffusion prevention film, is a crystal having columnar structure. Thus, it is difficult to effectively prevent the line layer from being diffused into the substrate. Particularly, TiN is not appropriate for prevention or barrier film of a line layer such as Cu, which is quickly diffused.  
         SUMMARY OF THE INVENTION  
         [0020]    Accordingly, the present invention is directed to devices and methods for manufacturing semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.  
           [0021]    An object of the present invention is to provide methods for manufacturing a semiconductor device, which simply form a silicide film for reducing a resistance of an ohmic contact between a metal line and a substrate. The method also forms a ternary phase thin film to act as an amorphous diffusion prevention film between a metal line and the silicide film.  
           [0022]    Another object of the present invention is to provide a structure for a semiconductor diffusion prevention device. The structure includes a silicide film for reducing a resistance an ohmic contact between a metal line and a substrate. The structure also includes a ternary phase film to act as a diffusion prevention film between a metal line and the silicide film.  
           [0023]    Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
           [0024]    To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.  
           [0025]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.  
         [0027]    In the drawings:  
         [0028]    [0028]FIGS. 1 a  to  1   e  are sectional views illustrating a related art method for manufacturing a semiconductor device;  
         [0029]    [0029]FIGS. 2 a  to  2   e  are sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;  
         [0030]    [0030]FIG. 3 shows an X-ray diffraction pattern after rapid annealing for 60 seconds at temperatures of 700° C., 550° C., and 400° C. by respectively depositing Ti of 25 nm and Co of 12 nm on a substrate;  
         [0031]    [0031]FIGS. 4 a  and  4   b  are profiles illustrating depths of thin films by auger electron spectroscopy (AEC) after rapid annealing for 60 seconds at each temperature by fixing Co thin film at 12 nm and depositing Ti thin films of 15 nm and 25 nm, respectively, on a semiconductor substrate; and  
         [0032]    [0032]FIGS. 5 a  and  5   b  show TEM sectional photograph after rapid annealing for 60 seconds at 700□C by depositing Ti thin films of 15 nm and 25 nm, respectively, on a semiconductor substrate. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
         [0034]    A method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.  
         [0035]    [0035]FIGS. 2 a  to  2   e  are sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.  
         [0036]    As shown in FIG. 2 a , a CVD oxide film  32  is formed on a semiconductor substrate  31 . A photoresist  33  is deposited on the CVD oxide film  32  and then patterned by exposure and developing processes to define a contact region. At this time, instead of the CVD oxide film  32 , an inorganic or organic material such as a nitride film may be used.  
         [0037]    Subsequently, the CVD oxide film  32  is selectively removed to partially expose a surface of the semiconductor substrate  31  using the patterned photoresist  33  as a mask, so that a contact hole  34  is formed.  
         [0038]    As shown in FIG. 2 b , the photoresist  33  is removed and then, e.g., a cobalt (Co) film  35  and a Ti film  36  are sequentially formed on an entire surface of the semiconductor substrate  31  including the contact hole  34 . At this time, the Co film  35  and the Ti film  36  are formed by at least one of several processes for forming a thin film, such as CVD process, PVD process, electroplating process, and evaporation process. Instead of the Ti film  36 , any one of Tin, Ta, W, V, Cr, Mn, Zr, Mo and Hf may be used.  
         [0039]    As shown in FIG. 2 c , an annealing process is performed in the semiconductor substrate  31  in which the Co film  35  and the Ti film  36  are formed in a nitrogen (N) atmosphere so as to react Co film  35  with the semiconductor substrate  31  at the contact hole  34 . Thus, a silicide film  37  of representing a low resistance ohmic contact is formed.  
         [0040]    Then an annealing is performed, such as by rapid thermal annealing or furnace annealing.  
         [0041]    A ternary phase thin film  38 , having amorphous structure by Co—Ti—Si reaction, is formed between the silicide film  37  and the Ti film  36  at a portion where the Si is exposed in the semiconductor substrate  31 . The ternary phase thin film  38  acts as a diffusion prevention or barrier film. Also, since the semiconductor substrate  31  is annealed in a nitrogen (N) atmosphere, the Ti film  36  becomes a TiN film.  
         [0042]    As shown in FIG. 2 d , a first metal layer (not shown) is formed on the entire surface of the semiconductor substrate  31 . Any one or a combination of W, Al, Cu, WSix, Mo, Cr, Ni, Pd, Pt and Ta may be used as the first metal layer. The first metal layer is formed by at least one of several processes for forming a thin film, such as CVD process, PVD process, electroplating process, and evaporation process. An etch back process or CMP process is then performed on the entire surface of the first metal layer to form a plug  39  in the contact hole  34 .  
         [0043]    When forming the plug  39 , the CVD oxide film  32  is used as an etching end point to perform etch back process or CMP process. The TiN film  36  and the Co film  35  over the CVD oxide film  32  are selectively removed.  
         [0044]    As shown in FIG. 2 e , a second metal layer is formed, on the plug  39  and the CVD oxide film  32 , to be electrically connected with the semiconductor substrate  31  through the plug  39 . The second metal layer is then selectively removed to form a metal line  40 . The composition and formation of the second metal layer can be like that of the first metal layer described above.  
         [0045]    [0045]FIG. 3 shows an X-ray diffraction pattern after rapid annealing for 60 seconds at temperatures of 700° C., 550° C., and 400° C. by respectively depositing Ti of 25 nm and Co of 12 nm on a substrate.  
         [0046]    As shown in FIG. 3, CoSi 2  thin film and TiN thin film are formed when annealing temperature increases to 700° C., while CoTi film is formed when annealing temperature is below 700° C.  
         [0047]    [0047]FIGS. 4 a  and  4   b  are profiles illustrating depths of thin films by AEC after rapid annealing for 60 seconds at each temperature by fixing Co thin film at, i.e., 12 nm and depositing Ti thin films of, e.g., 15 nm and 25 nm, respectively, on a semiconductor substrate.  
         [0048]    As shown in FIGS. 4 a  and  4   b , TiN layer is formed on a surface of the semiconductor substrate when annealing temperature is below 550° C. and Co—Si reaction occurs on the Si interface. Also, Co—Ti—Si mixing occurs when annealing temperature is 700° C. so that a ternary phase thin film is formed. The ternary phase thin film more clearly appears as the thickness of Ti increases.  
         [0049]    [0049]FIGS. 5 a  and  5   b  show TEM sectional photograph after rapid annealing for 60 seconds at 700° C. by depositing Ti thin films, e.g., of 15 nm and 25 nm, respectively, on a semiconductor substrate.  
         [0050]    As shown in diffraction pattern of FIG. 5 a , a ternary phase thin film (CoTixSiy) of amorphous structure is uniformly formed between cobalt silicide (CoSi) and the TiN thin film.  
         [0051]    As shown in FIG. 5 b , CoSi is epitaxially grown on the substrate and the substrate is uniformly formed.  
         [0052]    According to the results as shown in FIG. 3 to FIG. 5, Ti thin film is capped on Si substrate and Co film is deposited. In this state, if annealing is performed at an appropriate temperature, stable CoSi film and a ternary phase thin film (CoTixSiy) of amorphous structure are formed. The ternary phase thin film prevents diffusion effectively.  
         [0053]    The aforementioned method for manufacturing the semiconductor device has the following advantages.  
         [0054]    First, since a silicide film of low resistance is formed, even at 700° C., it is possible to provide a good ohmic contact having low resistance.  
         [0055]    Second, since Co does not easily react with dopants such as P, As and B, dopant loss is minimized on the interface between the CoSi film and the substrate. This prevents differences in electrical characteristic between N and P type substrates from occurring.  
         [0056]    Third, since the CoSi film is thermally stable even at temperatures of 900° C. or more, the surface of the CoSi film is uniform and it is possible to enhance the thermal properties.  
         [0057]    Fourth, a Co—Ti—Si ternary phase thin film having excellent diffusion prevention characteristics is formed in the contact region between the Co film and the Ti film.  
         [0058]    Fifth, since Ti film is capped on Si substrate to uniformly form the epitaxial CoSi film, it is possible to avoid poor contact, thereby obtaining stable ohmic contact and improving leakage current characteristic.  
         [0059]    Finally, since the ternary phase thin film is self-aligned between Co film and Ti film in a portion where silicon is exposed, the ternary phase thin film is uniform and it can be reliably reproduced.  
         [0060]    It will be apparent to those skilled in the art that various modifications and variations can be made in the method for manufacturing a semiconductor device according to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of the invention provided they come within the scope of the appended claims and their equivalents.