Abstract:
A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATION 
     The present application is the US national stage of PCT/CN2010/070650 filed on Feb. 11, 2010, which claims the priority of the Chinese patent application No. 200910199720.4 filed on Dec. 1, 2009, which application is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to the field of semiconductor manufacturing technologies and more particularly to a hybrid material inversion mode GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor). 
     2. Description of Related Art 
     A CMOS device integrates both NMOS (N-type Metal Oxide Semiconductor) and PMOS (P-type Metal Oxide Semiconductor) transistors in one device. As the device size continues to shrink, a major challenge in scaling down the channel length is to maintain a high current drive capability (I on ) and a stable threshold voltage, and control the device leakage current (I off ) at the same time. Short channel effect (SCE) degrades device performance and is a severe obstacle to scale down the channel length. 
     SOI (Silicon on Insulator) technology uses an ‘engineered’ substrate in place of a conventional bulk silicon substrate. The ‘engineered’ substrate is composed of three layers: a thin monocrystalline silicon top layer with circuits etched thereon; a thin buried oxide (BOX) layer formed of silicon dioxide; and a thick bulk silicon substrate for providing mechanical support to the two layers thereabove. In such a structure, the buried oxide layer separates the monocrystalline silicon top layer from the bulk silicon substrate, so large-area p-n junctions are replaced with a dielectric isolation. Meanwhile, source and drain regions extend downward into the buried oxide layer, which effectively reduce the leakage current and junction capacitance. For nanometer-scale channel length CMOS devices, it is important to control the channel conductance mainly through a gate electric field without being affected by a drain scattering electric field. For SOI devices, the above-described problem is alleviated with the reduced silicon thickness in both partial-depletion and full-depletion structures. Compared with the conventional planar CMOS devices, inversion mode dual-gate or tri-gate fin-type FETs have better gate control and scaling down capabilities. Besides operating in an inversion mode, ultra-thin SOI devices can also operate in an accumulation mode. Comparing to the full-depletion FET, in an accumulation mode, current flows through the whole SOI device, which increases the carrier mobility, reduces low-frequency noises, lowers the short channel effect, and increases the threshold voltage so as to avoid polysilicon gate depletion effect. In an inversion mode FET, the type of impurities doped in the source and drain regions is different from that in channel region, the charge transfer is of minority carriers, and p-n junctions are formed between the source region and the channel region and between the drain region and the channel region respectively. The inversion mode FETs are currently the most widely used devices. 
     Further, in Si(110) substrates, current flows along &lt;110&gt; crystal orientation, hole mobility is more than doubled compared with in conventional Si(100) substrates, and electron mobility is the highest in Si(100) substrates. To fully utilize the advantage of the carrier mobility depending on crystalline orientation, M. Yang et al. at IBM developed a CMOS fabricating technology on hybrid substrates with different crystal orientations Nigh performance CMOS fabricated on hybrid substrate with different crystal orientations&#39;, Digest of Technical Paper of International Electron Devices Meeting, 2003). Through bonding and selective epitaxy growth techniques, an NMOS device is fabricated on a Si (100) surface and a PMOS device is fabricated on a Si (110) surface. The paper reported the drive current of the PMOS device on the Si (110) substrate increases by 45%, when I off =100 nA/μm. The drawback of this technology is that the PMOS device fabricated in the epitaxial layer is not isolated from the substrate with buried oxide and thus the leakage current will be high. 
     Therefore, there is a need to develop new CMOSFET devices to overcome the above-described problems. 
     SUMMARY OF THE INVENTION 
     The present invention provides a hybrid material inversion mode GAA CMOSFET, which includes: a semiconductor substrate, a PMOS region having a first channel, an NMOS region having a second channel, and a gate region, wherein the NMOS region is disposed above the semiconductor substrate and the PMOS region is disposed above the NMOS region. The NMOS region and the PMOS region each includes a source region and a drain region located at the two opposite ends of the channel thereof. The first channel and the second channel each has a substantially circular-shaped cross section, wherein the first channel is formed of n-type Ge and the second channel is formed of p-type Si; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a first buried oxide layer is disposed between the PMOS region and the NMOS region; and a second buried oxide layer is disposed between the NMOS region and the semiconductor substrate. 
     In another embodiment of the present invention, a hybrid material inversion mode GAA CMOSFET includes: a semiconductor substrate, a PMOS region having a first channel and disposed above the semiconductor substrate, an NMOS region having a second channel and disposed above the PMOS region, and a gate region. The PMOS region and the NMOS region each includes a source region and a drain region located at the two opposite ends of the channel thereof. The first channel and the second channel each has a circular-shaped cross section, wherein the first channel is formed of n-type Ge and the second channel is formed of p-type Si; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a first buried oxide layer is disposed between the PMOS region and the NMOS region; and a second buried oxide layer is disposed between the PMOS region and the semiconductor substrate. 
     The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have high carrier mobility, low low-frequency noises. Meanwhile, polysilicon gate depletion and short channel effects are prevented, and the threshold voltages of the devices are increased. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIGS. 1   a - 1   c  show the structure of a GAA CMOSFET device according to a first embodiment of the present invention, wherein  FIG. 1   a  is a top view of the device,  FIG. 1   b  is a cross-sectional view along a line XX′ in  FIG. 1   a , and  FIG. 1C  is a cross-sectional view along a line ZZ′ in  FIG. 1   a;    
         FIG. 2  is a perspective view of the channel of the GAA CMOSFET device according to the first embodiment of the present invention; 
         FIG. 3   a  is a top view of a finished GAA CMOSFET device according to the first embodiment of the present invention; 
         FIG. 3   b  is a cross-sectional view along a line XX′ in  FIG. 3   a;    
         FIGS. 4   a - 4   c  show the structure of a GAA CMOSFET device according to a second embodiment of the present invention, wherein  FIG. 4   a  is a top view of the device,  FIG. 4   b  is a cross-sectional view along a line XX′ in  FIG. 4   a , and  FIG. 4C  is a cross-sectional view along a line ZZ′ in  FIG. 4   a;    
         FIG. 5   a  is a top view of a finished GAA CMOSFET device according to the second embodiment of the present invention; and 
         FIG. 5   b  is a cross-sectional view along a line XX′ in  FIG. 5   a.    
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following illustrative embodiments are provided to illustrate the disclosures of the present invention. It should be noted that figures are schematic representations of devices, and not drawn to scale. 
     First Embodiment 
     Referring to  FIGS. 1   a - 1   c , a hybrid material inversion mode GAA CMOSFET of the first embodiment includes: a semiconductor substrate  100 , a PMOS region  400  having a channel  401 , an NMOS region  300  having a channel  301 , and a gate region  500 . Each of the channels  401 ,  301  has a circular-shaped cross section. The channel  401  is preferably formed of n-type Ge and the second channel  301  is preferably formed of p-type Si. The gate region  500  substantially surrounds the surfaces of the channels  401 ,  301 . 
     In  FIG. 1   b , a first buried oxide (BOX) layer  201  is disposed between the PMOS region  400  and the NMOS region  300 , other than the gate region  500 , to avoid inter-region interference. A second buried oxide layer  202  is disposed between the NMOS region  300  and the underlying semiconductor substrate  100  (i.e. Si substrate), other than the gate region  500 , to isolate the NMOS region  300  from the underlying semiconductor substrate  100 . The BOX layers effectively reduce the leakage current and improve the device performance. 
     The PMOS region  400  comprises a source region  403  and a drain region  402  located at the opposite ends of the channel  401 . The NMOS region  300  comprises a source region  303  and a drain region  302  located at the opposite ends of the channel  301 . The source region  403  and the drain region  402  of the PMOS region  400  are formed of heavily doped p-type Ge, and the source region  303  and the drain region  302  of the NMOS region  300  are formed of heavily doped n-type Si. As shown in  FIG. 1   b , the source region  303  and the drain region  302  of the NMOS region  300  have a length greater than that of the source region  403  and the drain region  402  of the PMOS region  400 , respectively, so that the electrodes from the source region  303  and the drain region  302  can be led out. Referring to  FIG. 1   a , the width of the source and drain regions perpendicular to the channel direction XX′ is greater than the width of the channel, that is, both the PMOS region  400  and the NMOS region  300  are of a fin shape, which is narrow at the center and wide at the ends. Ge in the PMOS region  400  has (111) crystal orientation; and Si in the NMOS region  300  has (100) crystal orientation. 
     Referring to  FIGS. 1   b  and  1   c , the gate region  500  includes: a gate dielectric layer  501  substantially surrounding the surfaces of the channels  401 ,  301 , and a gate electrode material layer  502  substantially surrounding the gate dielectric layer  501 . Therein, the gate electrode material layer  502  is selected from the group consisting of titanium, nickel, tantalum, tungsten, tantalum nitride, tungsten nitride, titanium nitride, titanium silicide, tungsten silicide, nickel silicide, and a combination thereof; the gate dielectric layer  501  is formed of an insulating dielectric material comprising silicon dioxide, silicon oxynitride, silicon oxycarbide or a hafnium-based high-k material. Further, the underlying substrate  100  is formed of a semiconductor material such as Si, Ge, Ga and In. 
     Referring to  FIGS. 1   c , and  2 , the channels  401 ,  301  each has a length L in the range of 10-50 nm, the cross section thereof have a diameter d in the range of 10-80 nm. The first buried oxide layer  201  and the second buried oxide layer  202  each has a thickness in the range of 10-200 nm and is formed of silicon dioxide. Preferably, a Si passivation layer is disposed between the surface of the first channel  401  and the gate dielectric layer  501  and has a thickness in the range of 0.5-1.5 nm (not shown). 
     A FET transistor is fabricated based on the structure of  FIG. 1   b .  FIG. 3   a  is a top view of the transistor and  FIG. 3   b  is a cross-sectional view of the transistor. The fabrication processes include: forming a gate electrode on the gate electrode material layer  502 , forming source electrodes in the source region  403  of the PMOS region and the source region  303  of the NMOS region, respectively, and forming drain electrodes in the drain region  402  of the PMOS region and the drain region  302  of the NMOS region, respectively. To optimize the device performance, dielectric spacers  503  are disposed at the two sides of the gate, and the spacers can be made of silicon dioxide or silicon nitride. 
     Second Embodiment 
       FIGS. 4   a - 4   c  shows another embodiment of the device. The hybrid material inversion mode GAA CMOSFET includes: a semiconductor substrate  100 ′, a PMOS region  400 ′ having a channel  401 ′, an NMOS region  300 ′ having a channel  301 ′, and a gate region  500 ′. The channel  401 ′ and the channel  301 ′ each has a circular-shaped cross section, and the channel  401 ′ is made of a semiconductor material different from the channel  301 ′. In the present embodiment, the channel  401 ′ is preferably formed of n-type Ge and the channel  301 ′ is preferably formed of p-type Si. The gate region  500 ′ surrounds the surfaces of the channels  401 ′,  301 ′. A first buried oxide (BOX) layer  201 ′ is disposed between the PMOS region  400 ′ and the NMOS region  300 ′, other than the gate region  500 ′, to avoid inter-region interference. A second buried oxide (BOX) layer  202 ′ is disposed between the PMOS region  400 ′ and the underlying semiconductor substrate  100 ′, other than the gate region  500 ′, to isolate the PMOS region  400 ′ from the substrate  100 ′. The PMOS region  400 ′ comprises a source region  403 ′ and a drain region  402 ′ located at the opposite ends of the channel  401 ′ respectively. The NMOS region  300 ′ comprises a source region  303 ′ and a drain region  302 ′ located at the opposite ends of the channel  301 ′ respectively. The gate region  500 ′ includes: a gate dielectric layer  501 ′ substantially surrounding the surfaces of the channels  401 ′ and  301 ′, and a gate electrode material layer  502 ′ substantially surrounding the gate dielectric layer  501 ′. 
     Different from the first embodiment, the present embodiment has the NMOS region  300 ′ on top and the PMOS region  400 ′ close to the substrate  100 ′. 
     A transistor is fabricated based on the structure of  FIG. 4   c .  FIG. 4   a  is a top view of the transistor, and  FIG. 4   b  is a cross-sectional view of the transistor. The fabrication processes include: forming a gate electrode on the gate material layer  502 ′, forming source electrodes in the source region  403 ′ of the PMOS region and the source region  303 ′ of the NMOS region, respectively, and forming drain electrodes in the drain region  402 ′ of the PMOS region and the drain region  302 ′ of the NMOS region, respectively. Further, spacers  503 ′ are disposed at the two sides of the gate, the spacers can be made of silicon dioxide or silicon nitride. 
     The advantages of the present invention are explained as follows. 
     On one hand, the PMOS region and the NMOS region utilize different semiconductor materials (Ge and Si). Particularly, the first channel is formed of n-type Ge (111) and the second channel is formed of p-type Si (100). The conductive carriers of the inversion mode CMOS device are minority carriers. The conductive carriers of the first channel are holes in n-type Ge (111), and the conductive carriers of the second channel are electrons in p-type Si (100). Experiments show that the hole mobility in Ge(111) is higher than that in Si(100). Therefore, by replacing Si(100) with Ge(111), the present invention improves the carrier (hole) mobility such that the device has better performance and better scaling down capability. On the other hand, the PMOS region and the NMOS region each have a buried oxide layer to be isolated from the substrate so as to effectively reduce the leakage current. 
     In order to further analyze the device performance of the first and second embodiments, a 3D simulation adopting a precise hydraulic model and a quantum mechanical density gradient model and applying a mobility degradation model related to doping and surface roughness is established. The simulation result shows that the device of the present invention has many advantages that the conventional fin-shaped CMOS does not have. The device in an inversion mode adopts GAA structure having a cylindrical channel, high dielectric constant materials, and metal gate, so as to avoid polysilicon gate depletion and short-channel effect. The GAA CMOSFET having a cylindrical channel shows good output transfer characteristics with different gate oxide thickness and channel doping, but shows best characteristics with no dope (light dope) and thin gate oxide. 
     The above description of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention, Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.