Abstract:
A pixel circuit includes a single photon avalanche diode (SPAD) and a measurement circuit including a capacitance. The SPAD detects an incident photon and the measurement circuit discharges the capacitance at a known rate during a discharge time period. The length of the discharge time period is determined by the time of detection of the photon, such that the final amount of charge on the capacitance corresponds to the time of flight of the photon. The pixel circuit may be included in a time resolved imaging apparatus. A method of measuring the time of flight of a photon includes responding to an incident photon detection by discharging a capacitance at a known rate and correlating final capacitance charge to time of flight.

Description:
PRIORITY CLAIM 
       [0001]    This application claims priority from Great Britain Application for Patent No. 1219782.8 filed Nov. 2, 2012, the disclosure of which is incorporated by reference. 
       TECHNICAL FIELD 
       [0002]    This invention relates to pixel circuits comprising a Single Photon Avalanche Diode (SPAD) and in particular to Single Photon Avalanche Diode based time of flight pixels for time resolved imaging. 
       BACKGROUND 
       [0003]    A SPAD is based on a p-n junction device biased beyond its breakdown region. The high reverse bias voltage generates a sufficient magnitude of electric field such that a single charge carrier introduced into the depletion layer of the device can cause a self-sustaining avalanche via impact ionization. The avalanche is quenched, either actively or passively, to allow the device to be “reset” to detect further photons. The initiating charge carrier can be photo-electrically generated by means of a single incident photon striking the high field region. It is this feature which gives rise to the name ‘Single Photon Avalanche Diode’. This single photon detection mode of operation is often referred to as ‘Geiger Mode’. 
         [0004]    SPAD arrays have been used as solid-state detectors in imaging applications where high sensitivity and timing resolution are required. Current state of the art SPAD imaging arrays typically have large (&gt;20 μm) pixel pitches. A smaller pixel pitch facilitates increased resolution for SPAD based 3D Imagers. 
         [0005]    It is desirable to provide for smaller SPAD time of flight pixel circuits so as to be able to reduce pixel pitches in SPAD imaging arrays. 
       SUMMARY 
       [0006]    In a first aspect there is provided a pixel circuit comprising: a single photon avalanche diode (SPAD); a measurement circuit comprising a capacitance; wherein said SPAD is operable to detect a photon incident on said SPAD; and said measurement circuit is operable to discharge said capacitance at a known rate over a discharge time period, the length of said discharge time period being determined by the time of said detection of said photon incident on said SPAD, such that the final amount of charge on said capacitance corresponds to the time of flight of said photon. 
         [0007]    Correspondence here includes both “forward mode” and “reverse mode” operation. 
         [0008]    Said pixel circuit may comprise either a static or a dynamic memory operable to disable operation of the pixel after detection of a first photon incident on said SPAD. A dynamic memory may comprise only two or three transistor devices, the storage element being provided by the inherent capacitance of at least one of the transistor devices. Said memory may be operable to selectively connect the SPAD output to the measurement circuit depending on its stored content. 
         [0009]    Said pixel circuit may be operable in a reverse mode where it begins discharge of said capacitance on detection of a first SPAD event during a time period and prevents said discharge of said capacitance at the end of said time period. In this embodiment the charge on said capacitance is discharged via a switch controlled by the output of said SPAD. 
         [0010]    Said pixel circuit may be operable in a forward mode where it begins discharge of said capacitance at a first known time period and prevents said discharge of said capacitance on detection of a first SPAD event. In this embodiment a time varying ramp signal may be applied, via a hold switch, to said capacitance, said capacitance sampling said ramp signal, said hold switch disconnecting said ramp signal from said capacitance on detection of said first photon incident on said SPAD. 
         [0011]    Said pixel circuit may comprise a time gating stage operable to begin sensing operation on reception of an enable signal. Said time gate stage may comprise a switch operable to selectively connect the SPAD output to the measurement circuit on reception of said enable signal. Said time gate stage may comprise two further switches operable to disable the pixel circuit on reception of a disable signal. 
         [0012]    In a further aspect there is provided a time resolved imaging apparatus comprising an array of pixels according to the first aspect and an illumination source for providing said radiation incident on said SPAD. Said time resolved imaging apparatus may be operable to begin sensing operation of said array of pixels simultaneously with activation of said illumination source. 
         [0013]    In a further aspect there is provided a method of measuring the time of flight of a photon comprising: activating a radiation source to emit photons; receiving some of said photons using a single photon avalanche diode (SPAD); and discharging a capacitance at a known rate; wherein said discharging is either begun or ended upon detection of a photon received by said SPAD, such that the amount of charge remaining on said capacitance at the end of said time period corresponds to said time of flight of radiation incident on said SPAD. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    Embodiments will now be described, by way of example only, by reference to the accompanying drawings, in which: 
           [0015]      FIG. 1  is a circuit diagram of a time of flight pixel circuit according to a first embodiment; 
           [0016]      FIG. 2  is a timing diagram illustrating operation of the circuit of  FIG. 1  according to an operational embodiment; 
           [0017]      FIG. 3  is a circuit diagram of a time of flight pixel circuit according to a second embodiment; 
           [0018]      FIG. 4  is a timing diagram illustrating operation of the circuit of  FIG. 3  according to an operational embodiment; 
           [0019]      FIG. 5  is a circuit diagram of a first alternative front end for either of the time of flight pixel circuit of  FIG. 1  or  3 ; and 
           [0020]      FIG. 6  is a circuit diagram of a second alternative front end for either of the time of flight pixel circuit of  FIG. 1  or  3 . 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0021]    Disclosed herein are Time of Flight (ToF) analog pixels, which may be used in a large scale array for 3D single photon avalanche diode (SPAD) based imagers. The pixels designs allow for a low transistor count enabling small pixel pitches for large imagers, such as those used for 3D imaging. 
         [0022]    The ToF structures are suitable for direct imaging and address the problem of ‘once and for all’ time capture operation using a dynamic memory to temporarily disable pixel operation. Direct ToF circuits are designed to capture one time measurement until a reset and read out process. Reference is made to this as ‘once and for all’ operation. Therefore a memory (for example SRAM or a 2T or 3T DRAM) is provided to disable the measurement circuit from processing any further incoming SPAD avalanche events. 
         [0023]    The pixels may have a time gate to produce higher signal to noise ratio (SNR) and lower power consumption. Variations of the structures allow for positive or negative going input SPAD pulses. 
         [0024]    The time measurement circuit operates by discharging a known capacitance over a known time. The circuit may be activated by a positive going voltage spike, as produced by the photon-induced avalanche of a positive drive (PD) P-well SPAD. PD deep N-well SPADs or negative drive (ND) P-well SPADs produce a negative going voltage spike on diode avalanche and, if these are used, an inverter should be provided to obtain a positive spike. 
         [0025]      FIG. 1  shows a Time of Flight pixel circuit according to a first embodiment. It works as an analog time to amplitude converter (TAC), and operates in a “reverse mode”, that is the measured time is the time within the time frame which is not the time of flight. As the time frame is of fixed length, the time of flight is easily calculated from this. 
         [0026]    The circuit comprises five main stages. The first stage is the sensing stage  100 , which comprises a SPAD  105  and quenching/reset device  110 . The quenching/reset device receives a SPAD reset signal SR which, when pulsed high or biased above ground potential, causes the avalanche to be quenched. 
         [0027]    The second stage is a time gate stage  115 . This stage comprises three MOS devices  120   a,    120   b,    120   c  arranged in series between the positive rail and ground. The signal Vspad from the output of the sensing stage  100  is received at the node between devices  120   a  and  120   b,  the time gate stage producing an output at the node between devices  120   b  and  120   c.  Devices  120   a  and  120   c  receive on their gate a disable signal DS to selectively disable the pixel. Device  120   b  receives on its gate an enable signal EN to begin pixel operation. The enable signal EN should be received simultaneously with the activation of a light source, thereby time gating the pixel. 
         [0028]    The third stage is a memory stage  130 . This memory stage shares some characteristics with DRAM (dynamic random access memory) cells, and in particular “capacitorless” 1T DRAM cells that store the memory bit within the parasitic capacitance of a transistor. Memory stage  130  comprises MOS devices  135   a,    135   b,    135   c.  Device  135   a  receives memory reset signal MR and device  135   b  receives a NOT enable signal  EN , that is the opposite signal to the enable signal EN. The output of this memory stage  130  is signal Vmem, which is received by the fourth stage. 
         [0029]    The fourth stage is a current sinking stage  140 . Current sinking stage  140  comprises MOS devices  145   a,    145   b,    145   c    145   d,  and capacitor  150 . Device  145   a  receives on its gate, an input TAC reset signal TR, which resets the time to analog converter by recharging capacitor  150 . Device  145   d  receives a bias input B, which adjusts the rate of discharge of capacitor  150  and therefore the sensitivity of the pixel. The output of this stage is the pixel output signal Vc. 
         [0030]    The final stage is a readout stage  160 , comprising source-follower device  165  and read device  170 . Read device  170  receives an input (row) read signal RRead when pixel readout is required and provides the pixel output as column out signal Cout. The operation of such readout stages are well known and will not be described further here. 
         [0031]      FIG. 2  is a timing diagram illustrating operation of the circuit of  FIG. 1  according to an operational embodiment. It shows the signals: sensing stage output Vspad, disable signal DIS, enable signal EN, SPAD reset signal SR, memory stage output Vmem, pixel output signal Vc, memory reset signal MR and TAC reset signal TR. 
         [0032]    With the SPAD having been reset, the signals MR and TR are pulsed. As a result, capacitor  150  is charged, causing signal Vc to increase until the capacitor  150  is fully charged. Also the capacitance on node  180  (which is the inherent capacitance of the devices on this node) is charged, setting signal Vmem high. As signal MR goes low, the charge on this node  180  is isolated, holding Vmem high and keeping device  145   b  switched on. Following this, disable signal DIS goes low, closely followed by enable signal EN going high in synchronization with a pulsed laser or modulated LED. 
         [0033]    On detecting a photon from the laser or LED, the SPAD signal Vspad will go high. The time taken between EN going high and Vspad going high is the time of flight of the photon. Note that the avalanche is not immediately quenched by device  110  (signal SR stays low until the end of the frame). Signal Vspad going high causes device  145   c  to switch on, discharging the capacitor  150  at a rate set by the bias signal on device  145   d.  After a set time period, the length of which determines a time frame, signal EN goes low. This discharges node  180 , causing Vmem to go low and preventing further discharge of the capacitor  150 . As a result the signal Vc is held at a level directly corresponding to the length of the time frame period less the time of flight. As the time frame period length is known, the time of flight is simple to calculate. 
         [0034]    With node  180  discharged and Vmem low, the sensing circuit  100  is effectively isolated from capacitor  150 . This disables the current sinking stage  140  from processing any further incoming SPAD avalanche events, until reset via device  135   a  by pulsing signal MR. 
         [0035]      FIG. 3  shows a Time of Flight pixel circuit according to a second embodiment. It works as a sample and hold, analog time to amplitude converter (S/H TAC), and operates in a “forward mode” where the time of flight is directly measured. 
         [0036]    The sensing stage  300 , time gate stage  315  and readout stage  360  are essentially similar to sensing stage  100 , time gate stage  115  and readout stage  160  of  FIG. 1 . Memory stage  330  comprises MOS devices  335   a  and  335   b,  and also operates in a similar fashion to memory stage  130 , in that node  380  is charged via device  335   a,  this charge then being isolated until discharged. However, in this arrangement it is a SPAD event which directly discharges this node  380 , via device  335   b.  A sample and hold stage  340  is provided between the memory stage  330  and readout stage  360 . The sample and hold stage  340  comprises capacitor  350 , and MOS device  345 . Device  345  selectively passes a ramp signal Vramp to the capacitor  350 , depending on the level of signal Vhold (on node  380 ) on its gate. 
         [0037]      FIG. 4  is a timing diagram illustrating operation of the circuit of  FIG. 3  according to an operational embodiment. It shows the signals: memory reset signal MR, sensing stage output Vspad, disable signal DIS, enable signal EN, SPAD reset signal SR, memory stage output Vhold, ramp signal Vramp and pixel output signal Vc. 
         [0038]    With the SPAD having been reset, the signal MR is pulsed. As a result, the capacitance on node  380  (which is the inherent capacitance of the devices on this node) is charged, setting signal Vhold high. As signal MR goes low, the charge on this node  380  is isolated, holding Vhold high and keeping device  340  switched on. As a result, signal Vramp is sampled onto the capacitor  350 . Disable signal DIS is then switched low. This is closely followed by enable signal EN being switched high, in synchronization with a pulsed laser or modulated LED. Signal Vramp may be a negative going periodic ramp signal synchronized to the laser/LED frequency. 
         [0039]    On detecting a photon from the laser or LED, the SPAD signal Vspad will go high. The time taken between EN going high and Vspad going high is the time of flight of the photon. Signal Vspad going high switches on device  335   b,  thereby discharging node  380 , causing signal Vhold to go low. This turns off device  340 , isolating the capacitor  350  from signal Vramp. The level of signal Vc when device  340  is turned off is held by capacitor  350 , and corresponds directly with the time of flight of the photon. 
         [0040]    In a similar way to that of the circuit of  FIG. 1 , the sample and hold circuit  340  is prevented from processing any further incoming SPAD avalanche events, until node  380  is reset high via device  335   a  using signal MR. 
         [0041]    The embodiments shown above use a positive drive (PD) P-well SPAD. PD deep N-well SPADs (such as described in patent application PCT/GB2011/051686, incorporated by reference) or negative drive (ND) P-well SPADs produce a negative going voltage spike on diode avalanche. Both such SPAD designs (and others) can be used with the concepts disclosed herein. 
         [0042]      FIG. 5  shows a variation on the pixel circuit front end for a deep N-well SPAD. The Deep SPAD Structure uses the substrate as one half of its main p-n junction. Because of this, the anode terminal has to be common to the rest of the chip (usually ground). Therefore, the only method of connecting a bias voltage to the SPAD is to the cathode terminal, which requires a positive polarity in order to reverse bias the diode. The breakdown voltage of such a SPAD constructed from deep n-well (DNW) and the substrate will usually be relatively high because of the low doping concentrations involved. The high positive breakdown voltage of the proposed device is not compatible with standard CMOS transistor gates. Therefore, the only method of creating a high voltage compatible ‘quench’ resistor in CMOS is to use a highly resistive polysilicon to connect the cathode of the SPAD to a positive breakdown voltage supply. Moreover, the SPAD cathode, which is the moving node that falls in response to the avalanche current, cannot be directly connected to the CMOS inverter gates because it is also at a high DC bias level. Therefore, it is required to AC-couple the SPAD moving node to subsequent digital CMOS logic to ensure DC compatibility. To do this, the sensing circuit  700  comprises polysilicon resistor R and coupling capacitor C. 
         [0043]    As a consequence of this, the time gate stage  515  is modified to reset the sensing circuit. The Disable signal DIS is now received by a pair of devices  520   a.  A reset signal DS RST is received by device  520   c.  Furthermore, because the SPAD  505  produces a negative spike, an inverter (in the example shown here, a push-pull inverter  595 ) is provided. 
         [0044]      FIG. 6  shows a variation on the pixel circuit front end for a negative drive (ND) P-well SPAD. The sensing circuit  600  essentially mirrors that of the positive drive (PD) N-well SPAD, but connected with opposite polarity. As with the  FIG. 5  example, time gate stage  615  is essentially similar to those already described, and, a push-pull inverter  695  is provided to invert the SPAD  605  output. Both front end circuits of  FIGS. 5 and 6  can be used in place of sensing circuit  100 ,  300  and time gate circuit  115 ,  315  of the embodiments disclosed above. 
         [0045]    The pixel circuits disclosed herein can be used for various ranging applications, for example. The term “ranging” is intended to cover all ranging devices and methods including by not limited to ranging devices, proximity devices, accelerometers etc. Ranging can occur in a number of applications, including proximity detection which is relative easy to implement and inexpensive; Laser ranging which is more complex and costly than a proximity detector; and three-dimensional imaging which is a high-end application that could be used to recognize gestures and facial expressions. 
         [0046]    A proximity sensor is the most basic of the ranging applications. At its simplest the sensor is capable of indicating the presence or absence of a user or object. Additional computation and illuminator complexity can provide enhanced data such as the range to an object. A typical range is of the order 0.01 m to 0.5 m. In a simple proximity sensor the illumination source could be a modulated LED, at a wavelength of about 850 nm. 
         [0047]    The next application group is that of laser ranging, where the illumination source is a modulated laser diode. Performance can range from &lt;1 cm to 20 m range (and higher for top end systems) with millimetric accuracy. Requirements on optics are enhanced, with hemispherical lenses and narrow bandpass filters being required. A near-field return may result in the introduction of parallax error, i.e. movement of the returned laser spot over the sensor pixel array dependent on distance to object. To overcome these problems the ranger includes calibration functions to enable the subtraction of the electronic and optical delay through the host system. The illumination source wavelength should be visible so that the user can see what is being targeted and is typically around 635 nm. 
         [0048]    The third application group is that of 3D cameras. In this application a pixel array is used in order to avoid mechanical scanning of the array. Systems can be based on a number of different architectures. Both time of flight (TOF) and modulated illuminator based architectures can be used, however, the latter is more robust to ambient light and thus fits best with established photodiode construction. Additional features such as face and gesture recognition are applications of this type of ranging device. 
         [0049]    The pixel pitches of these analogue circuits are may be less than 20 μm, and may even be less than 10 μm. In fact, versions with a pixel pitch of 9.6 μm have been designed. This compares favorably with previous digital designs and existing photodiode based approaches. 
         [0050]    Variations have been designed to allow for differing functionality, physical pixel pitches and SPAD type. Some variations are detailed herein, but further variations (e.g. different types of inverter, etc.) have not been specifically described but fall within the spirit and scope of the invention.