Abstract:
To accomplish low power consumption of a semiconductor memory device, an internal voltage generating apparatus of the present invention applies an internal power voltage having the lower potential level as an operation voltage of a chip. By differentiating the internal power voltage for each of a peripheral circuit and a core circuit within a DRAM to use them as an operational voltage of the cell, i.e., by supplying the lowered internal power voltage to the core circuit unit, the reliability of the cell and noise characteristic is improved.

Description:
BACKGROUND  
         [0001]    1. Field of Invention  
           [0002]    The inventions described and claimed relate in general to powering semiconductor devices. More specifically, they relate to internal voltage generating arrangements.  
           [0003]    2. General Background and Related Art  
           [0004]    Generally, it is desirable to operate portable electronic devices at as low a power consumption level as possible. In fact, power consumption level is probably one of the most competitive issues among manufacturers of portable electronic devices, semiconductor memory devices, etc. To minimize power consumption, it is helpful to operate semiconductor devices as voltages lower than those of externally supplied voltages. Therefore, an internal power voltage, lower than an externally supplied power voltage, is generated and used to operate semiconductor devices.  
           [0005]    Because the power consumption of a CMOS circuit is proportional to square of voltage, power consumption can be reduced significantly, if the internal power voltage can be lowered. It is particularly helpful when the internal voltage source can be set and maintained to a static voltage. When this can be accomplished the operation of the chip is stable because the operational voltage is stable even when the external power voltage has some variation.  
           [0006]    The semiconductor chip should operate normally (e.g., has constant access time) even when the external power voltage varies by 10%. This requirement can lead to circuit complexity. If a stable power source could be provided by an internal voltage generating apparatus, circuit design can be made simpler, which has many design advantages. For this reason, the concept of using an internal voltage generating apparatus was introduced.  
           [0007]    [0007]FIG. 1 (Prior Art) is a circuit diagram of a conventional internal voltage generating apparatus. It includes a reference potential generating unit  100  for generating a reference voltage VREF 1  having a predetermined potential level. A potential amplifying unit  200  amplifies the reference voltage VREF 1 . A reference potential converting unit  300  converts the potential of the reference voltage VREF 1  by comparing a bias voltage VBIAS generated at a power voltage detector  10  with an output voltage VREF 1 _AMF from the potential amplifying unit  200 . A driver unit  400  supplies a second reference voltage VREF 2  converted at the reference potential converting unit  300  to a DRAM internal circuit  500  as an operational voltage in each of a standby mode and an active mode. The reference potential generating unit  100  is typically implemented by a Widlar Current Mirror which is well known in the art and its detailed description is omitted.  
           [0008]    The potential amplifying unit  200  includes a comparator  1  receiving the reference voltage VREF 1  at one of its two inputs. A PMOS transistor MP 1  is coupled between a power voltage input Vcc and an output N 1 . Transistor MP 1  has a gate coupled to the output of comparator  1 . Two resistors R 1  and R 2  are serially coupled between the output N 1  and ground for providing a feedback potential signal VA, resulting from voltage division based on the ratio of resistors R 1  and R 2 , to the other one of the two inputs of the comparator  1 .  
           [0009]    The reference potential converting unit  300  includes a comparator  3  receiving the output potential VREF 1 _AMF from the potential amplifying unit  200  at one of its two inputs and a current sink ground voltage at the other one of its two inputs. A comparator  5  receives the bias voltage from the power voltage detector  10  at one of its two inputs. The other input of comparator  5  is coupled to a current sink ground voltage. Two PMOS transistors MP 2  and MP 3  are coupled in parallel to each other between the power voltage input Vcc and the current sink output N 2 . A gate of PMOS transistor MP 2  is coupled to the output of the comparator  3  and a gate of PMOS transistor MP 3  is coupled to the output of the comparator  5 .  
           [0010]    Driver unit  400  includes a standby driver  20  and an active driver  30 . Drivers  20  and  30  are voltage followers that supply an operational voltage corresponding to the second reference voltage VREF 2  in for standby mode and active mode, respectively. Drivers  20  and  30  include comparators  7  and  9 , respectively, each receiving the second reference voltage VREF 2  at ones of their two inputs and the current sink ground voltage at their other inputs, respectively. Two PMOS transistors MP 4  and MP 5  are coupled respectively between the power voltage input Vcc and the current sink output N 2 . A gate of PMOS transistor MP 4  is coupled to the output of comparator  7  and a gate of PMOS transistor MP 5  is coupled to the output of the comparator  9 . The internal power voltage VINT 1  is applied to the DRAM internal circuit  500  through a common drain of the two PMOS transistors MP 4  and MP 5 .  
           [0011]    The DRAM internal circuit  500  can be divided roughly into the core circuit block, i.e., a memory cell block, and the peripheral circuit block. In order to improve reliability of the memory cell, it is required that the operational voltage of the core circuit block is set to be low by supplying the core circuit block with a power voltage lower than the power voltage of the peripheral circuit block.  
           [0012]    However, as will be appreciated referring to an output waveform of the internal voltage shown in FIG. 2 (Prior Art), the conventional internal voltage generating apparatus generates a single internal voltage VINT  1  by using a single voltage drop circuit, which leads some operational difficulties.  
           [0013]    Firstly, due to the internal power voltage being a single potential level, operational current value To determined by (Cp×VINT 1 +Cc×VINT 1 )×freq and subsequently memory core current increased. Accordingly, over-current flows through a cell capacitor and a swing voltage and a gate voltage of the cell increase. This voltage increase is bad for power consumption as well as in the cell reliability.  
           [0014]    Furthermore, a noise characteristic of a circuit so powered deteriorates due to mutual noise interference of the core circuit block and the peripheral circuit block.  
         SUMMARY  
         [0015]    With this background in mind, the claimed inventions feature, at least in part a dual internal voltage generating arrangement. The voltage generating arrangements presented herein generate internal power voltages used respectively as operational voltages for 1) a peripheral circuit block and 2) a core circuit block of a memory chip. This allows for the operational voltage of the cell used for core to be a lower and stable level.  
           [0016]    One exemplary embodiment of the inventions includes a dual internal voltage generating apparatus. A reference potential generating unit generates a reference voltage VREF 1  of a predetermined potential level. First and second potential amplifying units, parallel to each other, amplify the reference voltage VREF 1 . A first reference potential converting unit converts the reference voltage to a first potential level by comparing a first bias voltage generated at a corresponding power voltage detector with the output voltage from the first potential amplifying unit. A second reference potential converting unit converts the reference voltage to a second potential level by comparing a second bias voltage generated at a corresponding power voltage detector with the output voltage from the second potential amplifying unit. A first driver unit receives the reference voltage generated at the first reference potential converting unit for generating a first internal voltage to be supplied to a peripheral circuit unit within a DRAM. A second driver unit receives the reference voltage generated at the second reference potential converting unit for generating a second internal voltage to be supplied to a core circuit unit within the DRAM. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    Exemplary embodiments of the claimed inventions will be described in detail with reference to the accompanying drawings, in which:  
         [0018]    [0018]FIG. 1 (Prior Art) is a circuit diagram of a conventional internal voltage generating apparatus;  
         [0019]    [0019]FIG. 2 (Prior Art) shows an output waveform of the internal voltage generated in FIG. 1 (Prior Art);  
         [0020]    [0020]FIG. 3 is a circuit diagram of an exemplary embodiment of a dual internal voltage generating apparatus in accordance with the present invention; and  
         [0021]    [0021]FIG. 4 is a graphical representation of voltages generated by the dual voltage generating apparatus shown in FIG. 3.  
     
    
     DETAILED DESCRIPTION  
       [0022]    [0022]FIG. 3 is a circuit diagram of an exemplary embodiment of a dual internal voltage generating apparatus in accordance with the present invention. A reference potential generating unit  120  generates a reference voltage VREF 1  of a predetermined potential level. First and a second potential amplifying units  220  and  240 , parallel to each other, amplify the reference voltage VREF 1 . A first reference potential converting unit  320  converts the reference voltage VREF 1  to a potential level VREF 1 _PERI by comparing a first bias voltage VBIAS  1  generated at a power voltage detector  12  with the output voltage VREF 1 _AMF_PERI from the first potential amplifying unit  220 . A second reference potential converting unit  340  converts the reference voltage VREF 1  to a potential level VREF 2 _CORE by comparing a second bias voltage VBIAS 2  generated at a power voltage detector  14  with the output voltage VREF 1 _AMF_CORE from the second potential amplifying unit  240 . A first driver unit  420  receives the reference voltage VREF 2 _PERI generated at the first reference potential converting unit  320  and generates a first internal voltage VINT 1  to be supplied to a peripheral circuit unit  520 , internal of a DRAM. A second driver unit  440  receives the reference voltage VREF 2 _CORE generated at the second reference potential converting unit  340  and generates a second internal voltage VINT 2  to be supplied to a core circuit unit  540 , internal of a DRAM.  
         [0023]    The reference potential generating unit  120  includes a reference potential generator  2  and a voltage follower  36  adjusting current driving capability of a reference voltage VREF 0  generated at the reference potential generator  2 .  
         [0024]    The reference potential generator  2  can be implemented as a “Widlar current Mirror” which is well known in the art and its detail description is omitted for the sake of simplicity. Of course, other implementations are possible.  
         [0025]    The voltage follower  36  includes a comparator  11  having an input to which the reference voltage VREF 0  is applied from the reference potential generator  2 . A PMOS transistor MP 6  has a gate coupled to the output of comparator  11 , a source coupled to input potential Vcc and a drain coupled to a current source sinked to ground. The drain provides feedback to a second input of comparator  11 . The reference voltage VREF 1  generated as described above is transferred to one input of each of the first and the second potential amplifying units  220  and  240 .  
         [0026]    The potential amplifying units  220 ,  240  can be configured so as to be identical to potential amplifying unit  100  in its general circuit configuration and operation. However, they are constructed and arranged to have serially coupled resistors R 1 , R 2  and R 3 , R 4 , respectively for voltage distribution to differentiate the outputted reference potentials VREF 1 _AMF_PERI, VREF 1 _AMF_CORE.  
         [0027]    Because the reference potential VREF 1 _AMF_CORE from the second potential amplifying unit  240  controls a supply voltage provided to the core circuit unit  540  of the internal of the DRAM, the resistance ratios of the resistors R 1  to R 4  are selected so that the potential VREF 1 _AMF_CORE from unit  240  will be lower than the reference potential VREF 1 _AMF_PERI from potential amplifying unit  220 .  
         [0028]    Potential levels of the reference potential signals VREF 1 _AMF_PERI, VREF 1 _AMF_CORE, from the first and the second potential amplifying units  220 ,  240 , respectively are determined in accordance with the voltage distribution law as follows:  
           VREF 1 —   AMF   —   PERI =( R 1+ R 2)× VREF 1/ R 2  Eq.(1)  
           VREF 1 —   AMF   —   CORE =( R 3+ R 4)× VREF 1/ R 4  Eq.(2)  
         [0029]    Accordingly, by properly selecting the values of resistance of resistors R 1 , R 2 , R 3  and R 4 , the reference potentials VREF 1 _AMF_PERI, VREF 1 _AMF_CORE, from the first and the second potential amplifying units  220 ,  240 , can be controlled.  
         [0030]    For example, assuming that VREF 1 =0.7 V, R 1 =2.57×R 2 , and R 3 =2.14×R 4 , the output potential of the first potential amplifying unit  220  adjusted to have 2.5 V and the output potential of the second potential amplifying unit  240  adjusted to have 2.2 V are applied to the reference potential converting units  320  and  340 , respectively.  
         [0031]    Reference potential converting unit  320  includes a comparator  3  receiving the output potential VREF 1 _AMF_PERI from the first potential amplifying unit  220  at one of its two inputs and a current sink ground voltage at the other one of its two inputs. A comparator  5  receives the first bias voltage from power voltage detector  12  at one of its two inputs and a current sink ground voltage at the other one of its two inputs. Two PMOS transistors MP 2 , MP 3  are coupled in parallel to each other between the power voltage input and a current sink output N 2 . A gate of transistor MP 2  is coupled to the output of comparator  3 . A gate of transistor MP 3  is coupled to the output of the comparator  5 .  
         [0032]    Its operation will be described as follows:  
           VREF 2 —   PERI=VREF 1 —   AMF   —   PERI  (where  VCC&lt;Vy )  Eq.(3)  
         [0033]    [0033] VREF 2 —   PERI=VCC−nVt  (where  VCC&gt;Vy )  Eq.(4)  
         [0034]    The second reference potential converting unit  340  is as similar to the first reference potential converting unit  320  and its detail description will be omitted for the sake of simplicity.  
         [0035]    Its operation will be described as follows:  
         [0036]    [0036] VREF 2 —   CORE=VREF 1 —   AMF   —   CORE  (where  VCC&lt;Vy )  Eq. (5)  
         [0037]    [0037] VREF 2 —   CORE=VCC−nVt  (where  VCC&gt;Vy )  Eq.(6)  
         [0038]    Reference potentials VREF 2 _PERI, VREF 2 _CORE converted as above are applied to the drivers  420  and  440 , respectively, as their reference voltages. The driver unit  420  includes voltage followers  22  and  32 , each supplying the operational voltage corresponding to the reference voltage VREF 2 _PERI in the standby mode and the active mode, respectively, to the peripheral circuit unit  520 . Driver unit  440  includes voltage followers  24  and  34 , each for supplying the operational voltage corresponding to the reference voltage VREF 2 _CORE in the standby mode and the active mode, respectively, to the core circuit unit  540 . For the voltage followers  32  and  34  for the active mode, control clocks ACT_PERI, ACT_CORE for the active mode are applied as control signals of the comparators of the voltage followers  32  and  34 , respectively, to supply the operational voltage only in the active mode.  
         [0039]    Thus, the internal power voltages VINT 2 , VINT 1 , respectively, supplied to the core circuit unit  540  and the peripheral circuit unit  520  included within the DRAM can be differentiated. More particularly, the internal power voltage VINT 2  supplied to the core circuit unit  540  can be made lower than the internal power voltage VINT 1 .  
         [0040]    [0040]FIG. 4 is a graphical representation of voltages generated by the circuit arrangement shown in FIG. 3. Internal power voltages VINT 1  and VINT 2  are differentiated. By applying the internal power voltage having the lower potential level (herein, VINT 2 ) to the core circuit unit  540  within the DRAM, the operational voltage of the cell used in the core can be adjusted to a stable level.  
         [0041]    As described above, the dual internal voltage generating apparatus of the present invention accomplishes low power consumption by lowering the operational voltage of the cell by supplying the lowered internal power voltage to the core circuit unit. Furthermore, the reliability of the cell is improved by the decreased swing voltage and gate voltage of the cell and the noise characteristic is improved by minimizing noise interference between the core circuit unit and the peripheral circuit unit by using the differentiated internal voltages.  
         [0042]    While the present invention has been shown and described with respect to the particular embodiments, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.