Abstract:
An integrated circuit package having at least a product identity information and a product tracking information. The integrated circuit package includes an integrated circuit device and a package body. The package body has a top surface and a bottom surface. The product tracking information is located on the top surface of the package body and indicates a unique orientation of the integrated circuit device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    This Utility Patent Application claims priority to European Patent Application No. EP 03009828.9, filed on May 13, 2004, which is incorporated herein by reference.  
         BACKGROUND  
         [0002]    The invention relates to packaged integrated circuits (ICs). More particularly, the invention relates integrated circuit packages with marked product tracking information.  
           [0003]    ICs are normally “packaged” prior to sale, e.g., mounted in plastic or ceramic carriers that protect the IC. The IC package is then typically mounted on a circuit board, while “package pins” incorporated in the package allow electrical contact (through fragile internal “bond wires”) between the pads of the IC and traces on the board. Commonly used packages include dual in-line (DIP) packages, ball grid arrays (BGA), and many other well-known packages.  
           [0004]    Because many different ICs are generally available in a given package, packaged ICs are normally marked with both product tracking information and product identity information prior to sale.  
           [0005]    The product tracking information typically includes the wafer fabrication lot number and the date on which the wafer was fabricated, as well as the assembly lot number and the date on which the packaged IC was assembled. This information allows the manufacturer to track the manufacturing process and assists in solving manufacturing problems. Basic principles about this information and these methods of marking this information are disclosed e.g. in the U.S. Pat. No. 5,644,102 and U.S. Pat. No. 6,359,248 patents.  
           [0006]    Product identity information typically includes designations for the product type, package type, and performance (speed grade) of the IC.  
           [0007]    In addition, among the various characteristics of integrated circuit devices that can be marked are:  
           [0008]    testing level (e.g., commercial, industrial, mil-spec);  
           [0009]    radiation hardness of the integrated circuit;  
           [0010]    functionality (e.g., microprocessor, peripheral controller, memory device, etc.);  
           [0011]    source or origin of the device (e.g., manufacturer, distributor, etc.);  
           [0012]    temperature and/or humidity range for operation;  
           [0013]    method or process for design or manufacture (e.g., CMOS11, CMOS12 BiCMOS6HFC, etc.);  
           [0014]    device speed;  
           [0015]    testing level (e.g., commercial, industrial, mil-spec);  
           [0016]    availability of added (optional) functionality;  
           [0017]    location and function of groups of functionally related pins of the integrated circuit device; and  
           [0018]    location of reference pin, side, corner.  
           [0019]    [0019]FIG. 1 illustrates a generic, packaged integrated circuit  100 , and is intended to be representative of any conventional package. This figure is included to show some of numerous ways that others have provided features on integrated circuit packages and printed circuit boards, and is not intended in any way to be a limiting representation of the prior art.  
           [0020]    Typically, an IC device is tested briefly while still on the wafer. ICs failing the tests are discarded. ICs passing the tests are packaged, then marked with product tracking information.  
           [0021]    The package is marked on the front with additional information intended for the customer, typically product identity information. Product tracking information may also be included intended for the manufacturer.  
           [0022]    For example, a marked IC may display the company name and logo, an alphanumeric string including the product identity information (PRODUCT IDENTITY), and one or more strings including the product tracking information (PRODUCT TRACKING). FIG. 1 illustrates the marked information in more detail. The IC of FIG. 1 displays the product identity information in the form of a product designator (Prod), package identifier (pkg), and speed grade (spd-grade). Product tracking information includes the wafer lot, processing date, assembly lot, and assembly date.  
           [0023]    Due to the ongoing miniaturization and shrinking of the semiconductor devices it becomes very hard to provide all this information on one the top surface of the package since the available area is becoming smaller and smaller. Especially, providing the product tracking information by alphanumeric strings is becoming almost impossible.  
           [0024]    Therefore, it is known, to mark the product tracking information on the bottom of the package and the more important product identity information is marked on the front. This is illustrated in FIGS. 2A and 2B. However, this method is very complicated and needs additional tools in the marking equipment.  
           [0025]    Furthermore, it is a disadvantage in having this information on the bottom since this information is not visible after mounting the IC on the printed circuit board.  
           [0026]    The package body  102  of the integrated circuit  100  shown in FIG. 1 has four corners, one of which  104  is chamfered to indicate a particular orientation of the package (e.g., the location of pin number  1 ). The package body has a top surface  110 , and a bottom surface opposite the top surface. A plurality of pins  106  extend from the bottom surface of the package body in a rectangularly shaped array, and are electrically connected to a semiconductor (integrated) circuit die (not shown) contained within the package body  102 . The integrated circuit  100  may be mounted to a printed circuit board (PCB)  120  having a plurality of holes  122  for receiving the plurality of pins  106 , and the pins and holes may be arranged in symmetrical arrays or about the periphery of the package.  
           [0027]    Evidently, in such a case, the device  100  could be inserted in any of four orientations into the PCB  120 —only one of which orientation is correct. To ensure that the device  100  is inserted into the PCB  120  in the proper orientation, the chamfered corner  104  indicates a particular orientation, and the printed circuit board may be provided with a mark  124  (“1”), or the like, indicating the location of a particular hole  122   a  corresponding to pin #1 which can be established to be the pin  106   a  nearest to the chamfered edge  104  of the package  102 .  
           [0028]    In the assembly and subsequent inspection of semiconductor devices to circuit boards, it is essential that the proper device be mounted to the proper site on the board, and that the device is properly oriented at its location.  
           [0029]    For example, if the device is rotated 90, 180 or 270 degrees from its proper orientation it most certainly will not function as planned, since the pin-outs would be entirely wrong. To this end, certain semiconductor packages have some sort of locating/orienting feature, such as one of the corners of the package body being chamfered, an advertently missing pin, or the like. These solutions are complex, and require re-tooling to convert a non-orientation-sensitive package design to an orientation-sensitive package design.  
           [0030]    Therefore it is a problem applying indicia to a integrated circuit package that determines its “correct” orientation and simultaneously providing the product identity information and product tracking information on top surfaces if there is only a small area available.  
         SUMMARY  
         [0031]    In one embodiment of the present invention, an integrated circuit package having at least a product identity information and a product tracking information is provided. The integrated circuit package includes an integrated circuit device and a package body. The package body may be ceramic, plastic, epoxy, or the like and has a top surface and a bottom surface. The product tracking information is located on the top surface of the package body and indicates a unique orientation of the integrated circuit device.  
           [0032]    In one embodiment, the product tracking information is encoded having the form of a bar code. In another embodiment the encoded product tracking information has the form of a n×m matrix or a n×n matrix whereby n and m are integers.  
           [0033]    In another embodiment this encoded product tracking information is located on the surface indicating the location of a reference pin or a reference side or a reference corner.  
           [0034]    In another embodiment the encoded product tracking information is provided in a color, other than white or black, that is either applied as a coating or a label to the top surface of the device or incorporated into the material forming the body of the device package. Typically this is done by inking and curing.  
           [0035]    In another embodiment the encoded product information is applied by a laser to the top surface of the device or incorporated into the material forming the body of the device package. A laser is much less likely to damage an IC than other known marking methods. Further, the laser process is much faster than the inking and curing.  
           [0036]    To this end, the encoded product tracking information is applied to (or incorporated into) a particular surface of the packaged semiconductor device, but must not completely cover the package.  
           [0037]    According to another embodiment of the invention, the encoded product tracking information is applied to (or incorporated into) at least one selected area of the top surface of the device. For example, the at least one selected area encompasses less than 75% of a visible surface of the device, including less than 50%, less than 25%, less than 20%, less than 15%, less than 10%, and less than 5%. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0038]    The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.  
         [0039]    [0039]FIG. 1 illustrates the perspective view of a packaged IC and indicates the information that may be marked on the package according to a first known method.  
         [0040]    [0040]FIGS. 2A and 2B illustrate the bottom and top sides, respectively, of a packaged IC after marking with product tracking information according to a second known method.  
         [0041]    [0041]FIGS. 3A and 3B are top views of integrated circuit packages with marked product tracking information, according to the invention. 
     
    
     DETAILED DESCRIPTION  
       [0042]    In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.  
         [0043]    [0043]FIG. 3A is a top view of an integrated circuit package  300   a  having leads (electrical connections) shown as peripheral leads (such as gull wing or J-type leads)  302   a ,  302   b ,  302   c , and  302   d  disposed along respective sides  312   a ,  312   b ,  312   c , and  312   d  of the integrated circuit package  300   a.    
         [0044]    A colored inked 16×16 data code matrix  320   a  appears on a surface  314  of the integrated circuit package  300   a . The inked data code matrix  320   a  occupies an area substantially less than the total area of the surface  314  (e.g., less than 75% of the area of the surface  314 ), and is positioned towards a reference corner  310   a  (between sides  312   a  and  312   b ) of the integrated circuit package  300   a . To an observer, this positioning of the inked data code matrix  320   a  can be used to visually indicate that the corner  310   a  is a reference corner. In the case of a pin grid array (or ball grid array) type package, pin (ball) #1 could be the pin at the corner of the pin (ball) array under the corner  310   a.    
         [0045]    [0045]FIG. 3B is a top view of an integrated circuit package  300   b , similar to  300   a  (FIG. 3A), but with different markings. Like the integrated circuit package  300   a , the integrated circuit package  300   b  has leads  302   a ′,  302   b ′,  302   c ′, and  302   d ′ disposed along respective sides of the package  300   b.    
         [0046]    A lasermarked data code matrix  320   b  bearing the product tracking information appears on a surface  314 ′ of the package  300   b . The lasermarked data code matrix  320   b  has an area less than 25% of the total area of the surface  314 ′, but is significantly larger than characters in a printed text marking  342  on the surface  314 ′, and such lasermarked data code matrix  320   b  is readily discerned from distances well beyond reading distance.  
         [0047]    The lasermarked data code matrix  320   b  is positioned on the surface  314 ′ towards a reference corner  310   b  of the package (in a manner similar to the offset orientation of the inked data code matrix in FIG. 3A). In addition to the lasermarked data code matrix  320   b  and printed text markings  342 , a logo  340  appears on the surface  314 ′. The logo  340  includes the characters “LOGIC” which are not necessarily the color(s) of the “INFINEON” characters. Thus, the “LOGIC” characters could be black or white shades surrounded by the colored square portion—providing a complex internal shaded region to the lasermarked data code matrix  320   b  enhancing the contrast.  
         [0048]    It will be readily appreciated by one of ordinary skill in the art that the data code matrix bearing the product tracking information can be used to convey additional information about one or more characteristics of the integrated circuit.  
         [0049]    Among the various information that can be added additionally to the product tracking information in form of a data code matrix are:  
         [0050]    testing level (e.g., commercial, industrial, mil-spec);  
         [0051]    radiation hardness of the integrated circuit;  
         [0052]    functionality (e.g., microprocessor, peripheral controller, memory device, etc.);  
         [0053]    source or origin of the device (e.g., manufacturer, distributor, subcontractor etc.);  
         [0054]    temperature and/or humidity range for operation;  
         [0055]    method or process for design or manufacture; and  
         [0056]    device speed.  
         [0057]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.