Abstract:
A carrier substrate includes a substrate having a chip side and a PCB side, a plurality of bond pads disposed on the chip side for bonding a chip, a plurality of land grid array (LGA) pads disposed on the PCB side, and a plurality of resilient flanges installed on the PCB side in an array manner. The plurality of resilient flanges electrically connects with the LGA pads correspondingly.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to carrier substrates and, more particularly, to a carrier substrate having an array of contact arms disposed on a PCB side of the carrier substrate and a chip module using the same. The invention is further concerned with a method of fabricating the inventive carrier substrate. 
         [0003]    2. Description of the Prior Art 
         [0004]    As the input/output (I/O) pin count and circuit density of the integrated circuit (IC) chip continue to increase, the process of bonding or mounting a chip module onto a printed circuit board (PCB) becomes a big challenge. Typically, the chip module is directly mounted on the PCB by soldering such as ball grid array (BGA). However, such connections made by soldering are not reversible and the cost is high when replacement of the chip module is required after assembly. 
         [0005]    To cope with the problem, an interposer connector or interposer has been developed, which is interposed between a chip module and a PCB. As shown in  FIG. 1 , an interposer  3  is disposed between a carrier substrate  1  and a PCB  2 . The interposer  3  includes a substrate  30 , a plurality of flexible contact members  32  mounted on a chip mounting side or chip side  3   a  of the substrate  30 , and a plurality of solder balls mounted on a PCB side  3   b  of the substrate  30 . The flexible contact members  32  electrically contact the land grid array (LGA) pads  12  on the bottom side  1   a  of the carrier substrate  1 . The solder balls  34  are electrically connected to the PCB  2 . 
         [0006]    The above-described prior art has several drawbacks. For example, the assembly of the aforementioned interposer is more complex and is thus more expensive. Further, the interposer between the chip and the PCB increase the signal transmission distance, whereby reducing the device performance. Besides, the interposer increases the total thickness of the circuit board assembly and is therefore not feasible for some applications for which the assembly space is limited. 
       SUMMARY OF THE INVENTION 
       [0007]    It is therefore one objective of the invention to provide an improved carrier substrate (or chip carrier) and chip module using such inventive carrier substrate, in order to solve the above-described prior art problems. 
         [0008]    According to one preferred embodiment of the invention, a carrier substrate includes a substrate having a chip side and a PCB side; a plurality of bonding pads on the chip side for bonding a chip; a plurality of land grid array (LGA) pads on the PCB side; and an array of flexible contact arms mounted on the PCB side and electrically connected to the LGA pads respectively. 
         [0009]    According to another preferred embodiment of the invention, a chip module includes a carrier substrate comprising a substrate having a chip side and a PCB side; a plurality of bonding pads on the chip side for bonding a chip; a plurality of land grid array (LGA) pads on the PCB side; and an array of flexible contact arms mounted on the PCB side and electrically connected to the LGA pads respectively. The chip module further includes a chip mounted on the chip side of the carrier substrate. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a schematic diagram showing a prior art interposer connector that is interposed between a carrier substrate of a chip module and a PCB. 
           [0012]      FIG. 2  is schematic, cross-sectional diagram illustrating a carrier substrate in accordance with one preferred embodiment of this invention. 
           [0013]      FIGS. 3-8  demonstrate a method of fabricating the carrier substrate according to this invention, wherein  FIG. 3  shows a cross-section of a substrate,  FIG. 4  shows a cross-section of the substrate after laminating contact arms on the PCB side,  FIG. 5  shows a cross-section of the substrate after electroplating copper and nickel layers,  FIG. 6  shows a cross-section of the substrate after selectively plating gold layer,  FIG. 7  shows a cross-section of the substrate after the circuit trace etching process, and  FIG. 8  shows a cross-section of the substrate after forming a protective coverlay. 
           [0014]      FIG. 9  is a schematic, cross-sectional diagram showing a chip module in accordance with another preferred embodiment of this invention. 
       
    
    
       [0015]    It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. 
       DETAILED DESCRIPTION 
       [0016]    Please refer to  FIG. 2 .  FIG. 2  is schematic, cross-sectional diagram illustrating a carrier substrate in accordance with one preferred embodiment of this invention. As shown in  FIG. 2 , according to the preferred embodiment of the invention, the carrier substrate  100  comprises a substrate  110  such as a multi-layer laminate substrate or a single-layer laminate substrate. The substrate  110  has a chip mounting side or chip side  110   a  and a PCB side  110   b . A plurality of bonding pads  111  are provided on the chip side  110   a  for bonding a chip  101 . A plurality of land grid array (LGA) pads  112  are provided on the PCB side  110   b  that is opposite to the chip side  110   a . An array of flexible contact arms  120  are jointed to the PCB side  110   b  and are electrically connected to the corresponding LGA pads  112 . 
         [0017]    According to the preferred embodiment of the invention, each of the flexible contact arms  120  may be a metal flange such as copper or composite metal. Each of the flexible contact arms  120  may comprise a base  120   a , a slightly curved middle part  120   b , and a distal contact portion  120   c . The base  120   a  of each of the flexible contact arms  120  is jointed to the PCB side  110   b  of the substrate  110  using an adhesive layer  130  such as low-flow prepreg by pressing laminating methods. A selective gold plating layer  140  or other durable conductor materials such as noble metals may be formed on the surface of the flexible contact arms  120 . Each of the flexible contact arms  120  is electrically connected to the corresponding LGA pad  112  through a plated via  150  that is formed in the adhesive layer  130 . Further, a coverlay  160  may be formed on the adhesive layer  130 . 
         [0018]    It is one technical feature of the invention that the carrier substrate  100  is able to be directly mounted on the PCB through the flexible contact arms  120  disposed on the PCB side  110   b . The chip  101  is bonded on the chip side  110   a  of the carrier substrate  100 . By doing this, the prior art interposer connector can be spared. The advantages of the invention at least include: (1) simplified assembly process and reduced cost because the interposer connector is spared; (2) the signal transmission distance between the chip and the PCB is reduced, thereby improving the device performance; and (3) low-profile after assembly and the total thickness of the circuit board assembly is reduced. 
         [0019]    An exemplary method of fabricating the carrier substrate  100  will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. 
         [0020]    Referring to  FIG. 3  to  FIG. 8 , the method of fabricating the carrier substrate  100  starts with a substrate  110  having a chip side  110   a  and a PCB side  110   b . As shown in  FIG. 3 , a plurality of bonding pads  111  are provided on the chip side  110   a  for bonding a chip (not shown). A plurality of LGA pads  112  are provided on the PCB side  110   b  that is opposite to the chip side  110   a . As shown in  FIG. 4 , a metal sheet  200  comprising an array of flexible contact arms  120  is laminated on the PCB side  110   b  using an adhesive layer  130  such as low-flow prepreg. Each of the flexible contact arms  120  may be a metal flange such as copper or composite metal. Each of the flexible contact arms  120  may comprise a base  120   a , a slightly curved middle part  120   b , and a distal contact portion  120   c . The base  120   a  of each of the flexible contact arms  120  is jointed to the PCB side  110   b  of the substrate  110  using the adhesive layer  130  by pressing laminating methods. The array of flexible contact arms  120  on the metal sheet  200  may be formed by punching, etching or other suitable methods. 
         [0021]    As shown in  FIG. 5 , an electroplating process is carried out to plate a copper/nickel composite layer  132  on the PCB side  110   b  of the substrate  110 . A plated via  150  is formed in the adhesive layer  130 . The flexible contact arm  120  is electrically connected to the LGA pad  112  through the plated via  150 . As shown in  FIG. 6 , a selective gold plating process is performed. For example, a photoresist (not shown) is used to mask the non-gold plating area on the substrate  110 . A gold layer  140  is then plated on the gold-plating area not covered by the photoresist. The surface of the flexible contact arm  120  and a portion of the copper/nickel composite layer  132  are covered with the gold layer  140 . As shown in  FIG. 7 , after stripping the photoresist, an etching process is carried out to define the circuit trace. A portion of the metal sheet  200  and a portion of the copper/nickel composite layer  132  are removed to expose the underlying adhesive layer  130 . As shown in  FIG. 8 , a protective coverlay  160  is formed on the adhesive layer  130 . The coverlay  160  may be jointed onto the carrier substrate  100  using an adhesive layer or glue. 
         [0022]      FIG. 9  is a schematic, cross-sectional diagram showing a chip module  100 ′ using the inventive carrier substrate  100  in accordance with another preferred embodiment of this invention. As shown in  FIG. 9 , the chip module  100 ′ comprises a carrier substrate  100  having the same structure as that described in  FIG. 8 . The carrier substrate  100  comprises a substrate  110  having a chip side  110   a  and a PCB side  110   b . An IC chip  101  is mounted on the chip side  110   a  and is connected to the bonding pads  111 . A plurality of LGA pads  112  and an array of flexible contact arms  120  are provided on the PCB side  110   b  opposite to the chip side  110   a . The plurality of flexible contact arms  120  are electrically connected to the LGA pads  112  respectively. Each of the flexible contact arms  120  may be a metal flange such as copper or composite metal. Each of the flexible contact arms  120  may comprise a base  120   a , a slightly curved middle part  120   b , and a distal contact portion  120   c.    
         [0023]    The base  120   a  of each of the flexible contact arms  120  is jointed to the PCB side  110   b  of the substrate  110  using an adhesive layer  130  such as low-flow prepreg by pressing laminating methods. A selective gold plating layer  140  or other durable conductor materials such as noble metals may be formed on the surface of the flexible contact arms  120 . Each of the flexible contact arms  120  is electrically connected to the corresponding LGA pad  112  through a plated via  150  that is formed in the adhesive layer  130 . Further, a coverlay  160  may be formed on the adhesive layer  130 . 
         [0024]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.