Abstract:
A method of cleaning a substrate before and after an LDD implantation comprising the following sequential steps. A substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH 4 OH. An LDD implantation is performed into the substrate to form LDD implants. The substrate is cleaned by a wet clean process excluding NH 4 OH.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor fabrication and more specifically to methods of cleaning a semiconductor wafer before and after low-doped drain (LDD) implantation. 
     BACKGROUND OF THE INVENTION 
     Complimentary metal-oxide semiconductor (CMOS) technology demands channel length scaling beyond 0.1 μm and brings new challenges to channel/source/drain engineering by conventional implant technology. 
     Wet clean processes must be free from silicon (Si) recessing, that is wet clean processes should not also consume the silicon the processes are cleaning. This is particularly important for post implantation to reduce the implantation dose loss or the dose variation induced electrical instability. 
     U.S. Pat. No. 6,150,277 to Torek describes a method of using TMAH to etch an implanted area. 
     U.S. Pat. No. 6,214,682 B1 to Wang describes a process to reduce transient enhanced diffusion (TED) using an anneal. 
     U.S. Pat. No. 4,652,334 to Jain et al., U.S. Pat. No. 5,690,322 to Xiang et al., U.S. Pat. No. 5,486,266 to Tsai et al. and U.S. Pat. No. 5,811,334 to Buller et al. describe related methods. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of LDD implant cleaning. 
     Other objects will appear hereinafter. 
     It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH 4 OH. An LDD implantation is performed into the substrate to form LDD implants. The substrate is cleaned by a wet clean process excluding NH 4 OH. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which: 
     FIGS. 1 to  4  schematically illustrate a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Unless otherwise specified, all structures, layers, steps, methods, etc. may be formed or accomplished by conventional steps or methods known in the prior art. 
     Problem Discovered by the Inventors 
     The following problem has been discovered by the inventors and is not to be considered prior art for the purposes of this invention. 
     The inventors have found in 0.1 μm gate-stack process development practice that using NH 4 OH in conventional wet cleaning processes have a significant deleterious effect on core NMOS device&#39;s short channel effect (SCE) and gate oxide integrity (GOI). However, removal of NH 4 OH from the wet clean process led to significantly worse V T  roll-off and degradation of short channel margin. Further, diminishing reverse short channel effect (RSCE) was noticed as another symptom closely related with worse V T  roll-off and suppression of boron (B) transient enhanced diffusion (TED) is proposed as the possible mechanism. This new finding suggests that boron TED should be critically controlled by the arsenic (As) implant damage and its location. 
     Initial Structure 
     As shown in FIG. 1, structure  10  includes gate structure  12  formed by a gate etch process. Structure  10  is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate. Gate structure is preferably comprised of polysilicon with an underlying gate oxide layer (not shown). 
     The present invention discloses a new finding and mechanism useful to, inter alia, gain channel length scaling margin without resort to lower energy implants or more expensive anneal processes. It has been discovered that the inclusion of NH 4 OH in a pre-LDD implant  18  clean  14  and the exclusion of NH 4 OH in a post-LDD implant  18  clean  22  achieves these desirable qualities as described below. 
     Pre-LDD Wet Clean  14   
     As shown in FIG. 2, a pre-LDD wet clean  14  that includes NH 4 OH is then used to clean silicon wafer  10  and to also intentionally create micro-recesses  16  within the LDD or extension area created by consumption of some of the silicon of silicon wafer  10 . The chemical etching effect causes NH 4 OH to attack the silicon (Si) and form micro-recesses  16  The inclusion of NH 4 OH in the pre-LDD wet clean  14  enhances reverse short channel effect (RSCE) and gain channel length scaling margin. 
     Pre-LDD wet clean  14  is conducted at the following conditions: 
     NH 4 OH: preferably from about 10 to 30% by volume and more preferably from about 15 to 20% by volume; 
     H 2 O 2 : preferably from about 10 to 40% by volume and more preferably from about 20 to 30% by volume; 
     H 2 O: preferably from about 90 to 100% by volume and more preferably from about 95 to 100% by volume; 
     temperature: preferably from about 25 to 80° C. and more preferably from about 40 to 75° C.; and 
     time: preferably from about 30 to 500 seconds and more preferably from about 200 to 450 seconds. 
     LDD Implant  18   
     As shown in FIG. 3, an LDD implant  18  is performed on the structure of FIG. 2 to form LDD implants  20  to a depth of preferably from about 200 to 800 Å and more preferably from about 100 to 300 Å. LDD implant  18  is conducted using As 75 , Sb 221 , BF 2  or B 11  atoms at a dose of preferably from about 1×10 13  to 2×10 15  atoms/cm 2  and more preferably from about 1×10 14  to 1×10 15  atoms cm 2 ; and an energy of preferably from about 0.2 to 70 keV and more preferably from about 0.2 to 50 keV. 
     Shallow junctions formed by the LDD implant  18  are very shallow in the 0.1 μm design rule and sub 0.1 μm design rule for which the method of the present invention is admirably suited. 
     Optional Fine Tuning of LDD Implant  18  Energy 
     Optionally, fine tuning the LDD implant  18  energy for ultra-low NLDD implants (to form N +  extensions  20 ) combined with the NH 4 OH budget described herein may also be used to further optimize RSCE and gain channel length scaling margin. That is, the LDD implant  18  energy is preferably from about 0.2 to 70 keV and more preferably from about 2 to 25 keV. 
     The choice of LDD implant energies depends upon the implant species and the junction depth requirements. For example, for core devices with a junction depth requirement of less than about 500 Å, the implant energy should be less than about 5 keV when using As 75  or BF 2  but may be less than about 1 keV, i.e. from about 0.2 to 0.5 keV when using BF 11 . For input/output (I/O) devices with a junction depth requirement of less than about 1000 Å, the implant energy can be increased to from about 20 to 40 keV when using BF 2  for P-type metal oxide semiconductor (PMOS). 
     Post-LDD Wet Clean  22   
     As shown in FIG. 4, the structure of FIG. 3 is subjected to a post-LDD implant wet clean  22  that excludes NH 4 OH. 
     By excluding NH 4 OH in the post-LDD clean  20 , the post-LDD clean  20  reduces: (1) the dose lose, that is the dose loss of shallow junctions due to further silicon recess; (2) the dose variation induced device degradation; and (3) electrical instability. 
     Post-LDD wet clean  20  is conducted at the following conditions: 
     H 2 O 2 : preferably from about 10 to 40% by volume and more preferably from about 20 to 30% by volume; 
     H 2 O: preferably from about 90 to 100% by volume and more preferably from about 95 to 100% by volume; 
     temperature: preferably from about 25 to 80° C. and more preferably from about 40 to 75° C.; and 
     time: preferably from about 30 to 500 seconds and more preferably from about 200 to 450 seconds. 
     Further processing may then proceed. For example, spacers may be formed on the side walls of gate structure  12 , high dose doped (HDD) may then be performed into silicon substrate  10 , etc. 
     Advantages of the Present Invention 
     The advantages of one or more embodiments of the present invention include: 
     1. gain channel length scaling margin beyond 0.1 μm; 
     2. minimization of silicon recess; 
     3. reduction of source/drain series resistance; 
     4. acceptable gate oxide integrity (GOI); 
     5. shallow junction dose loss is reduced; 
     6. the dose variation induced device degradation is reduced; and 
     7. the electrical instability is reduced. 
     While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.