Abstract:
An oscillator circuit including an integrated circuit amplifier, an integrated circuit active resistance circuit to set the gain of the amplifier, a crystal resonator to set the frequency of the signal generated by the oscillator circuit, and a pair of capacitors respectively situated at the inputs and outputs of the amplifier to assist in the starting of the oscillation signal. The active resistance circuit is responsive to an input signal in order to set the gain of the amplifier slightly above unity gain in order to meet the criterion for oscillation, but not too much above unity gain where the oscillator would unduly consume too much power. Thus, the oscillator has inherent low power characteristics. The active resistance circuit allows the amplifier gain to be set by software or other electronic means.

Description:
FIELD 
     This invention relates generally to electronic oscillators, and in particular, to an oscillator having an active feedback resistance circuit to set the desired operating condition of the oscillator&#39;s amplifier. 
     BACKGROUND 
     Current microprocessor systems use a crystal oscillator as part of a Real Time Clock (RTC) to keep track of the date and time of day. They typically use a relatively accurate and high frequency crystal oscillator, for example 32.768 kHz, which is divided to generate seconds, minutes and hours for the system. Because the Real Time Clock (RTC) needs to be running even when the microprocessor system is off, it is directly connected to a battery. The dependency on battery power raises power consumption issues among other accuracy, stability and manufacturing issues, as will be discussed with regard to the following example. 
     FIG. 1 illustrates a block diagram of a prior art processor system  100 . The processor system  100  consists of a microprocessor  108  coupled to a memory controller  106 , which is sometimes referred to in the relevant art as the “north-bridge.” The memory controller  106  interfaces with the system memory  110 . The processor system  100  further consists of an input/output (I/O) bus  102  coupled to an I/O controller  104 , which is sometimes referred to as the “south-bridge.” The “south bridge” is, in turn, coupled to the “north bridge.” Typically included in the “south-bridge” circuit board is the Real Time Clock (RTC) for the processor system  100 , which keeps track of the time and date for the system. 
     For discussion purposes, FIG. 1 only shows the crystal oscillator  120  portion of the Real Time Clock (RTC) for the processor system  100 . The crystal oscillator  120  consists of an amplifier  122  including a crystal resonator  124 , an external resistor  126 , and a pair of capacitors CL 11  and CL 22 . The crystal resonator  124  and external resistor  126  are connected between the input and output of the amplifier  122 , i.e. in feedback with the amplifier. The capacitor CL 11  is coupled between the input of the amplifier  122  and ground potential. Similarly, the capacitor CL 12  is coupled between the output of the amplifier  122  and ground potential. The crystal resonator  124  resonates precisely at a particular frequency, which causes the oscillator  120  to generate a periodic signal cycling at such frequency. The external resistor  126  biases the amplifier  122  which affects its gain. The capacitors CL 11  and CL 12  serve to optimize the startup and loading conditions of the oscillator  120 . 
     There are several drawbacks with regard to the external resistor  126  of the prior art oscillator  120 . One set of drawbacks arises from the fact that the external resistor  126  sets the gain of the oscillator  120 . In order to satisfy the condition for oscillation, the gain of the amplifier  122  should be at least one (1). However, a gain significantly over one (1) could lead to additional noise in the output signal of the oscillator  120 , could also lead to instability of the oscillator  120 , and could unduly increase the power consumption of the oscillator  120 . Thus, the external resistor  126  should be precisely selected such that the gain of the amplifier  122  is slightly above unity gain. Because there are process variations with regard to the integrated circuit in which the amplifier  122  is formed, there can be substantial trial and error in selecting an external resistor  126  that sets the gain of the amplifier  122  slightly above unity. Such trial and error increases the costs, time and complexity of manufacturing the oscillator  120  in addition to reducing the reliability of the oscillator  120 . In addition, once the external resistor  126  is selected, it becomes impractical to change the resistor later on to account for changes in the oscillator&#39;s performance due to aging or other changes in the environment and/or application. 
     Another set of drawbacks stems from the fact that the external resistor  126  lies external to the integrated circuit in which the amplifier  122  is formed. Since the external resistor  126  lies external to the amplifier integrated circuit, it is typically mounted on the “south bridge” circuit board along with the integrated circuit. This increases the board routing complexity as well as the manufacturing of the “south bridge” board, which leads to increased manufacturing time and costs. Also, because the external resistor  126  is situated external to the shielded integrated circuit, it is exposed to environment noise, thereby introducing additional noise into the oscillator signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a block diagram of a prior art processor system including an input/output controller with a clock circuit; 
     FIG. 2 illustrates a schematic diagram of an exemplary oscillator in accordance with an embodiment of the invention; 
     FIG. 3 illustrates a schematic diagram of an exemplary active resistance circuit in accordance with an embodiment of the invention; 
     FIG. 4 illustrate a graph of exemplary waveforms present in the exemplary active resistance circuit in accordance with an embodiment of the invention; 
     FIG. 5 illustrates a schematic diagram of an exemplary active resistance circuit in accordance with another embodiment of the invention; 
     FIG. 6 illustrates a block diagram of an exemplary oscillator circuit in accordance with another embodiment of the invention; and 
     FIG. 7 illustrates a block diagram of an exemplary processor system in accordance with another embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 illustrates a schematic diagram of an exemplary oscillator  200  in accordance with an embodiment of the invention. The oscillator  200  comprises an amplifier  202 , a crystal resonator  204 , input and output capacitors CL 21  and CL 22 , and an on-chip bias active resistance circuit  206 . The crystal resonator  204  and the on-chip active resistance circuit  206  are coupled in parallel between the input and output of the amplifier  202 . The input and output capacitors CL 21  and CL 22  are coupled respectively between the input and output of the amplifier  202  and ground potential. The crystal resonator  204  resonates precisely at a particular frequency, which causes the oscillator  200  to generate a periodic signal cycling at such frequency. The on-chip external resistance circuit  206  sets the gain of the oscillator  200 . The capacitors CL 21  and CL 22  serve to optimize the startup and loading conditions of the oscillator  200 . 
     The exemplary oscillator  200  has several significant advantageous over the prior art oscillator  100  due to the on-chip active resistance circuit  206 . First, the on-chip active resistance circuit  206  can be tuned electronically including by software means. Thus, the on-chip active resistance circuit  206  can be easily tuned to set the gain of the amplifier  202  at slightly above unity in order to meet the condition for oscillation without unduly consuming too much power. Consequently, less trial and error are required, which translates to less costs, time and complexity in the manufacturing of the oscillator  200  in addition to higher reliability for the oscillator  200 . Furthermore, the active resistance circuit can be tuned “in situ” by software or other electronic means to take into account changes in the oscillator&#39;s performance and/or changes in the environment and/or application. Additional benefits resulting from the active resistance circuit being incorporated into an integrated circuit include less complex circuit routing for the “south bridge” board and potentially less noise in the oscillator signal. 
     FIG. 3 illustrates a schematic diagram of an exemplary active resistance circuit  300  in accordance with an embodiment of the invention. The active resistance circuit  300  is one exemplary embodiment of the active resistance circuit  206  of oscillator  200 , and is coupled across the crystal resonator  302  of an oscillator. The active resistance circuit  300  comprises an active resistor field effect transistor (FET) Q 31 , a current source I BIAS , a bias resistor R BIAS , and an oscillator compensation circuit  304 . The oscillator compensation circuit  304 , in turn, comprises a first compensation leg including a p-channel FET Q 32  and an n-channel FETs Q 33 , and a second compensation leg including a p-channel FET Q 34  and an n-channel FET Q 35 . The current source I BIAS  and bias resistor R BIAS  are connected in series to generate a bias voltage VR BIAS  to bias the gate of the active resistor FET Q 31 . The drain (D) and source (S) of the active resistor FET Q 31  are respectively coupled on either side of the crystal resonator  302 . 
     With regard to the oscillator compensation circuit  304 , the sources (S) of p-channel FETs Q 32  and Q 34  are coupled to the gate of the active resistor FET Q 31 , the drains of the p-channel FETs Q 32  and Q 34  are respectively coupled to the drains (D) of the n-channel FETs Q 33  and Q 35 , and the sources (S) of the n-channel FETs Q 33  and Q 35  are coupled to ground potential. The gates (G) of the p-channel FET Q 32  and the n-channel FET Q 35  are coupled to receive the “in-phase” oscillator signal Osc X 1  on one side of the crystal resonator  302  (and active resistor FET Q 31 ), and the gates (G) of the n-channel FET Q 33  and the p-channel FET Q 34  are coupled to receive the “out-of-phase” oscillator signal Osc X 2  (approximately 180 degrees out-of-phase) on the other side of the crystal resonator  302  (and active resistor FET Q 31 ). 
     The resistance across the channel of the active resistor FET Q 31  is to maintain substantially constant in order to set the gain of the oscillator amplifier substantially constant and slightly above unity gain. In order to keep the channel resistance of the active resistor FET Q 31  substantially constant, the gate-to-source voltage (V GS ) of the active resistor FET Q 31  should also be substantially constant. However, the voltages on the drain (D) and source (S) of the active resistor FET Q 31  fluctuate because they are respectively coupled to either side of the crystal resonator  302 , and thereby respectively receive the “in-phase” and “out-of-phase” oscillator signals Osc X 1  and Osc X 2 . Thus, the oscillator compensation circuit  304  is responsive to the “in-phase” and “out-of-phase” oscillator signals Osc X 1  and Osc X 2  in order to maintain the gate-to-source voltage (V GS ) of the active resistor FET Q 31  substantially constant, as will be explained with reference to FIG.  4 . 
     FIG. 4 illustrate a graph of exemplary waveforms present in the exemplary active resistance circuit  300 . The x-axis of the graph represents the phase of the oscillator signals. The y-axis of the graph represents the amplitude of the oscillator signals and bias voltage. The graph shows the “in-phase” oscillator signal Osc X 1 , the “out-of-phase” oscillator signal Osc X 2 , and the active resistor bias voltage VR BIAS . 
     As the graph illustrates, when the phase of the “in-phase” oscillator signal X 1  is at zero (0) degree and the phase of the “out-of-phase” oscillator signal Osc X 2  is at 180 degrees, the amplitude of the “in-phase” oscillator signal Osc X 1  is greater than the amplitude of the “out-of-phase” oscillator signal X 2 . Accordingly, at this phase the terminal of the active resistor FET Q 31  exposed to the “in-phase” oscillator signal Osc X 1  acts as the drain (D) and the other terminal exposed to the “out-of-phase” oscillator signal Osc X 2  acts as the source (S). Since at this phase the voltage at the source (S) of the active resistor FET Q 31  is at its minimum value, the bias voltage VR BIAS  should also be at its minimum in order to keep the gate-to-source voltage (V GS ) of the active resistor FET Q 31  substantially constant. The second compensation leg minimizes the bias voltage VR BIAS  by drawing maximum current from the current source I BIAS , thereby reducing the current through the bias resistor R BIAS , and thereby lowering the bias voltage VR BIAS . The second compensation leg draws the maximum current by having the minimized “out-of-phase” oscillator signal Osc X 2  minimize the channel resistance of the FET Q 34  and the maximized “in-phase” oscillator signal Osc X 1  minimize the channel resistance of the FET Q 35 . 
     In the phase range from 0 degree to 90 degrees, the amplitude of the “in-phase” oscillator signal Osc X 1  is decreasing and the amplitude of the “out-of-phase” oscillator signal Osc X 2  is increasing. However, in this phase range the amplitude of the “in-phase” oscillator signal Osc X 1  is greater than the amplitude of the “out-of-phase” oscillator signal Osc X 2 . Accordingly, the terminal of the active resistor FET Q 31  exposed to the “in-phase” oscillator signal Osc X 1  still acts as the drain (D) and the other terminal exposed to the “out-of-phase” oscillator signal Osc X 2  still acts as the source (S). Since in this range the voltage at the source of the active resistor FET Q 31  is increasing (because Osc X 2  is increasing), the bias voltage VR BIAS  should similarly increase to maintain the gate-to-source voltage (V GS ) of the active resistor FET Q 31  substantially constant. The second compensation leg increases the bias voltage VR BIAS  by gradually drawing less current from the current source I BIAS , thereby increasing the current through the bias resistor R BIAS , and thereby increasing the bias voltage VR BIAS . The second compensation leg gradually draws less current by having the increasing “out-of-phase” oscillator signal Osc X 2  increase the channel resistance of the FET Q 34  and the decreasing “in-phase” oscillator signal Osc X 1  increase the channel resistance of the FET Q 35 . 
     In the phase range from 90 to 180 degrees, the amplitude of the “in-phase” oscillator signal Osc X 1  is still decreasing and the amplitude of the “out-of-phase” oscillator signal Osc X 2  is still increasing. However, in this phase range the amplitude of the “in-phase” oscillator signal Osc X 1  is less than the amplitude of the “out-of-phase” oscillator signal Osc X 2 . Accordingly, the terminal of the active resistor FET Q 31  exposed to the “in-phase” oscillator signal Osc X 1  now acts as the source (S) and the other terminal exposed to the “out-of-phase” oscillator signal Osc X 2  now acts as the drain (D). Since in this range the voltage at the source of the active resistor FET Q 31  is again decreasing (because Osc X 1  is decreasing), the bias voltage VR BIAS  should similarly decrease to maintain the gate-to-source voltage (V GS ) of the active resistor FET Q 31  substantially constant. In this case, the first compensation leg decreases the bias voltage VR BIAS  by gradually drawing more current from the current source I BIAS , thereby decreasing the current through the bias resistor R BIAS , and thereby decreasing the bias voltage VR BIAS . The first compensation leg gradually draws more current by having the increasing “out-of-phase” oscillator signal Osc X 2  decrease the channel resistance of the FET Q 33  and the decreasing “in-phase” oscillator signal Osc X 1  decrease the channel resistance of the FET Q 32 . 
     In the phase range from 180 to 270 degrees, the amplitude of the “in-phase” oscillator signal Osc X 1  is now increasing and the amplitude of the “out-of-phase” oscillator signal Osc X 2  is now decreasing. However, in this phase range the amplitude of the “in-phase” oscillator signal Osc X 1  is still less than the amplitude of the “out-of-phase” oscillator signal Osc X 2 . Accordingly, the terminal of the active resistor FET Q 31  exposed to the “in-phase” oscillator signal Osc X 1  still acts as the source (S) and the other terminal exposed to the “out-of-phase” oscillator signal Osc X 2  still acts as the drain (D). Since in this range the voltage at the source of the active resistor FET Q 31  is now increasing (because Osc X 1  is increasing), the bias voltage VR BIAS  should similarly increase to maintain the gate-to-source voltage (V GS ) of the active resistor FET Q 31  substantially constant. The first compensation leg increases the bias voltage VR BIAS  by gradually drawing less current from the current source I BIAS , thereby increasing the current through the bias resistor R BIAS , and thereby increasing the bias voltage VR BIAS . The first compensation leg gradually draws less current by having the decreasing “out-of-phase” oscillator signal Osc X 2  increase the channel resistance of the FET Q 33  and the increasing “in-phase” oscillator signal Osc X 1  increase the channel resistance of the FET Q 32 . 
     Finally, in the phase range from 270 to 360 (0) degrees, the amplitude of the “in-phase” oscillator signal Osc X 1  is still increasing and the amplitude of the “out-of-phase” oscillator signal Osc X 2  is still decreasing. However, in this phase range the amplitude of the “in-phase” oscillator signal Osc X 1  is now greater than the amplitude of the “out-of-phase” oscillator signal Osc X 2 . Accordingly, the terminal of the active resistor FET Q 31  exposed to the “in-phase” oscillator signal Osc X 1  now acts as the drain (D) and the other terminal exposed to the “out-of-phase” oscillator signal Osc X 2  now acts as the source (S). Since in this range the voltage at the source of the active resistor FET Q 31  is now decreasing (because Osc X 2  is decreasing), the bias voltage VR BIAS  should similarly decrease to maintain the gate-to-source voltage (V GS ) of the active resistor FET Q 31  substantially constant. The second compensation leg decreases the bias voltage VR BIAS  by gradually drawing more current from the current source I BIAS , thereby decreasing the current through the bias resistor R BIAS , and thereby decreasing the bias voltage VR BIAS . The second compensation leg gradually draws more current by having the decreasing “out-of-phase” oscillator signal Osc X 2  decrease the channel resistance of the FET Q 34  and the increasing “in-phase” oscillator signal Osc X 1  decrease the channel resistance of the FET Q 35 . 
     FIG. 5 illustrates a schematic diagram of an exemplary active resistance circuit  500  in accordance with another embodiment of the invention. The exemplary active resistance circuit  500  is a more detailed embodiment of the active resistance circuit  300  previously discussed. The active resistance circuit  500  comprises an active resistance device  502 , a resistance selection circuit  504 , an active resistor enable device  506  (or an oscillator quality factor (Q) modifying or oscillator amplifier gain modifying device as will be discussed with reference to FIG.  6 ), a bias current source  508 , a bias resistive device  510 , and an oscillation compensation circuit  512 . 
     The active resistance device  502 , in turn, comprises a plurality of series-connected FETs Q 51 - 0  through Q 51 - 4  with gates connected in common. The resistance selection circuit  504 , in turn, comprises a plurality of series-connected FETs Q 52 - 0  through Q 52 - 3  with gates to respectively receive resistance selection signals S 0 - 3 . The active resistor enable device  506  comprises a FET Q 53  with a gate to receive an active resistor enable signal Soff. The current source  508 , in turn, comprises a pair of diode-connected FETs Q 54  and Q 55  connected in series. The bias resistive device  510 , in turn, comprises a pair of diode-connected FETs Q 56  and Q 57  connected in series. And, the oscillator compensation circuit  512  comprises a first compensation leg including series-connected p-channel FET Q 58  and n-channel FET Q 59 , and a second compensation leg including series-connected p-channel FET Q 60  and n-channel FET Q 61 . 
     The plurality of series-connected FETs Q 51 - 0  through Q 51 - 4  of the active resistance device  502  form the total resistance for setting the gain of the oscillator amplifier. The FETs Q 51 - 0  through Q 51 - 4  can be configured (e.g. by sizing the FETs) to provide different resistances. For example, the FETs Q 51 - 0  through Q 51 - 4  can be configured to provide increasing binary-weighted resistance (e.g. 1 K Ohms, 2 K Ohms, 4 K Ohms, 8 K Ohms, 16 K Ohms). The plurality of series-connected FETs Q 52 - 0  through Q 52 - 3  of the resistance selection circuit  504  are respectively coupled across the FETs Q 51 - 0  through Q 51 - 3  to bypass the selected FETs Q 52 - 0  through Q 52 - 3  using the resistance selection signals S 0 -S 3 . Using the resistance selection circuit  504 , the net resistance of the active resistance device  502  can be set or changed by software or other electronic means. 
     The FET Q 53  of the active resistor enable device  506  is connected in series with the active resistance device  502  to enable or disable the active resistance device  502 . Using active resistor enable device  506 , the active resistance device  502  can be disabled if an external resistor for the oscillator is used. The active resistor enable device  506  and the active resistance device  502  connected in series are coupled across the oscillator amplifier and crystal resonator. The current source  508  connected in series with the bias resistive device  510  which, in turn, is connected in parallel with the oscillator compensation circuit  512  generate the appropriate bias voltage VR BIAS  which sets and maintains substantially constant the desired resistance of the active resistance device  502 , as previously discussed with reference to active resistance circuit  300 . 
     FIG. 6 illustrates a block diagram of an exemplary oscillator circuit  600  in accordance with another embodiment of the invention. As previously alluded to, the active resistor enable device  506  can also be used as an oscillator quality factor (Q) modifying device or amplifier gain modifying device. Instead of the enable signal Soff fully turning on or off the FET Q 53  to enable or disable the active resistance device  502 , the signal Soff can be used to bias the FET Q 53  to operate it as a variable resistor to change the quality factor (Q) and/or the gain of the oscillator  600 . The oscillator  600  comprises an oscillator  602 , a buffer  604 , and an oscillating detect circuit  606 . The oscillating detect circuit  606  detects whether the oscillator  602  is oscillating. If it is not because the resistance of the active resistance device is too low, the oscillating detect circuit  606  modifies to the signal Soff to increase the resistance of the FET Q 53  until oscillation is detected. If oscillation is detected, the oscillator detect circuit  606  may cause the signal Soff to increase or decrease the resistance of the FET Q 53  to achieve a desired quality factor (Q) and gain of the oscillator circuit  600 . 
     FIG. 7 illustrates a block diagram of a prior art processor system  700 . The processor system  700  comprises a microprocessor  708  coupled to a memory controller  706 , which is sometimes referred to in the relevant art as the “north-bridge.” The memory controller  706  interfaces with the system memory  710 . The processor system  700  further comprises an input/output (I/O) bus  702  coupled to an I/O controller  704 , which is sometimes referred to as the “south-bridge.” The “south bridge” is, in turn, coupled to the “north bridge.” Typically included in the “south-bridge” circuit board is the Real Time Clock (RTC) for the processor system  700 , which keeps track of the time and date for the system. The Real Time Clock (RTC), in turn, comprises a crystal oscillator  720  including an integrated circuit  722  with an amplifier and an on-chip active resistance circuit in accordance with the invention, a crystal resonator  724 , and a pair of capacitors CL 71  and CL 72 . As previously discussed, the processor system  700  has several significant advantageous over the prior art processor system  100  due to the on-chip active resistance circuit. 
     Although the description of the exemplary embodiments described herein used the exemplary oscillator configuration shown in FIG. 2, it shall be understood that other types of oscillator configurations can benefit from the active resistance circuit described herein. In addition, although field effect transistors were used to describe the various embodiments of the invention, it shall be understood that other types of transistors, such as bipolar transistors, and other types of active devices can be used in place thereof. 
     In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.