Abstract:
A microprocessor system contains a read-only memory (ROM) for storing programs or firmware. Retrieval and execution of program code is controlled by a microprocessor address bus. Erroneous data in the ROM can be corrected by address comparison and translation. Trap, region, and patch tables are provided to store addresses, regions, and translated addresses. An address issued by the microprocessor is stored in the trap and region tables can be translated for selecting another programmable device, such as a SRAM or DRAM, other than the original ROM. Thus, erroneous code in the ROM can be corrected, inserted, or replaced.

Description:
BACKGROUND  
       [0001]     The invention relates to program patching methods, and in particular to program patching methods and systems using bus address translation.  
         [0002]     A microprocessor system generally contains a read-only-memory (ROM) to store programs or firmware. The programs or firmware can be retrieved and executed by a microprocessor through address buses. An electronic product, such as a DVD player, or a computer, may contain a microprocessor system with a ROM for system controlling.  
         [0003]     A ROM in a microprocessor system is generally called an on-chip ROM. While a ROM is a non-writable device, the ROM in a microprocessor system generally stores permanent data. When an electronic product with an on-chip ROM is delivered to a customer, the data stored in the ROM is unchangeable.  
         [0004]     If a program in a ROM contains erroneous code or requires modification, a program patch may be executed for such correction or modification. U.S. Pat. No. 4,542,453 discloses a data processing system, using one bit for each potential ROM address to indicate a program branch for programs in a ROM. U.S. Pat. No. 5,581,776 provides a branch control system for ROM-programmed processors, which modifies a program counter for manifesting program count values and executing a prestored program in accordance with the program count values. Additionally, U.S. Pat. No. 6,237,120 discloses a method of program patching a ROM, which changes the address of a microprocessor by hardware interrupt to execute the program patch.  
         [0005]     The mentioned methods and systems have some drawbacks. For example, using one bit for each potential ROM address may heavily increase system load. Modifying a program counter for a branch lacks flexibility as it can only branch for one source/target pair. Changing microprocessor addresses cannot be applied to certain systems, such as a system with pipelined CPU (central processing unit). Therefore, a more flexible and low cost method and system is desirable.  
       SUMMARY  
       [0006]     An exemplary embodiment of a microprocessor system comprises a microprocessor and a trap controller. The microprocessor issues a first address to a first address bus. The trap controller, coupled to the first address bus and comprising a trap table, a region table, and a patch table, fetches the first address from the first address bus, translates the first address to a second address according to the trap, region, and patch tables, and issues the second address to a second address bus.  
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0007]     The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0008]      FIG. 1  is a diagram of an embodiment of a microprocessor system.  
         [0009]      FIG. 2  is a diagram of an embodiment of a trap controller.  
         [0010]      FIG. 3  is a diagram of an embodiment of bus address translation using the trap, region, and patch tables.  
         [0011]      FIG. 4  is a flowchart of an embodiment of a bus address translation method.  
         [0012]      FIG. 5  is a flowchart of an embodiment of a program patching method using bus address translation.  
         [0013]      FIG. 6  is a diagram of an exemplary embodiment of ROM code replacement using a bus address translation method.  
         [0014]      FIG. 7   a  is a flowchart of an exemplary embodiment of ROM code replacement using a bus address translation method.  
         [0015]      FIG. 7   b  is a flowchart of an exemplary embodiment of ROM code replacement using a bus address translation method.  
         [0016]      FIG. 8  is a diagram of an exemplary embodiment of new code insertion using a bus address translation method.  
         [0017]      FIG. 9   a  is a flowchart of the exemplary embodiment of new code insertion using a bus address translation method.  
         [0018]      FIG. 9   b  is a flowchart of the exemplary embodiment of new code insertion using a bus address translation method.  
         [0019]      FIG. 10  is a diagram of an embodiment of the structure of a patch program. 
     
    
     DESCRIPTION  
       [0020]     Microprocessor systems with program patching are provided.  FIG. 1  is a diagram of an embodiment of a microprocessor system. A microprocessor  10 , such as a CPU, issues a first address to a first address bus  12 . A trap controller  14 , coupled to the first address bus  12 , includes a trap table  140 , a region table  142 , and a patch table  144 . The trap controller  14  fetches the first address from the first address bus, translates the first address to a second address according to the trap, region, and patch tables  140 ,  142 ,  144 , and issues the second address to a second address bus  16 .  
         [0021]     The microprocessor system further includes a first storage device  18  and a second storage device  20 . The first storage device  18 , such as a ROM, is coupled to the second address bus  16  and stores data addressed in the first address. The second storage device  20 , such as a random-access-memory (RAM), is coupled to the second address bus  16  and stores data addressed in the second address.  
         [0022]     The trap controller  14  further includes a comparator  146  and a translator  148 . The comparator  146 , coupled to the trap table  140  and the region table  142 , compares a trap address and a region according to the first address to acquire a comparison result. The trap address is recorded in the trap table  140  and the region is recorded in the region table  142 . The translator  148 , coupled to the region table  142 , the patch table  144 , and the comparator  146 , fetches the second address from the patch table  144  according to the comparison result and issues the second address to the second address bus  16 .  
         [0023]     For example, if the microprocessor is a CPU  10 , the CPU  10  issues an address to the address bus  12  and fetches data from a data bus  22 .  FIG. 2  is a diagram of an embodiment of a trap controller. The comparator  146  compares the address issued by the CPU  10 , hereinafter called CPU address, with records in the trap table  140  and the region table  142 . If the CPU address matches the trap region that is defined by both of the records in the trap table  140  and the region table  142 , the comparator  146  issues a hit signal and indicates the corresponding trap region in the region table  142  and the patch address in the patch table  144  to the translator  148 .  
         [0024]     The translator  148  then translates the CPU address to a translated address according to the comparison result via fetching the corresponding records in the patch table  144  and the region table  142 . The translator  148  then issues the translated address to the translated address bus  16 , thus desired program code can be located.  
         [0025]     The CPU address may not fall into the trap table, so the translated address is the CPU address. The region functions as a mask to determine compared bits of the CPU address. The size of the region can vary, depending on actual requirements.  
         [0026]      FIG. 3  is a diagram of an embodiment of bus address translation using the trap, region, and patch tables. For example, an on-chip ROM  30  is located from address 0x1000 to 0x3000, and a SRAM or a DRAM  36 , storing correct ROM code, is located from address 0x6000 to 0x10000. The address and data bus are all 32 bits. A record, that is a trap pointer (TA)  302 , in the trap table equals 0x2000, and its corresponding region (TR)  342  is 0xF0 (8 bits). The region (TR)  342  is the address bit comparison indicator. If TR=0x00, the corresponding TA  302  is disabled and ignored by the comparator. If TR=0xFF, all the CPU address bits are compared to the TA  302 . If TR=0xF0, the 4 least significant bits (LSB) of the CPU address will be ignored during address comparison and the region extends to 16 bytes. When the CPU issues an address from 0x2000 to 0x200C, the address is translated to a patch address  362  from 0x8000 to 0x800C. The patch code in the SRAM or DRAM  36  will be sent to the CPU through the data bus to replace erroneous code in the ROM  30  addressed from 0x2000 to 0x200C.  
         [0027]     Referring again to  FIG. 1 , the RAM  20  or other storage device, such as a SRAM, storing correct program code, is coupled to the translated address bus  16  rather than the CPU address bus  12 . An external memory controller  24  controls an external memory bus  28  to provide the CPU  10  to access external memory devices  26 , such as a FLASH, a DRAM or other storage devices. This external memory controller  24  can also be coupled to the translated address bus  16 . Therefore, the correct program code can be stored in the external storage devices  26  rather than in the on-chip storage devices.  
         [0028]      FIG. 4  is a flowchart of an embodiment of a bus address translation method. A first address is fetched from a first address bus (step S 400 ). The first address is translated to a second address according to a trap table, a region table, and a patch table.  
         [0029]     The first address is first compared with a trap region to acquire a comparison result (step S 404 ). The reap region address is acquired by a trap address in the trap table and a region in the region table. A second address is then fetched from the patch table according to the comparison result (step S 406 ). The second address is issued to a second address bus (step S 408 ).  
         [0030]     Here, the data or program addressed in the first address is stored in a first storage device, such as a ROM, and the data or program addressed in the second address is stored in a second storage device, such as a RAM.  
         [0031]      FIG. 5  is a flowchart of an embodiment of a program patching method using bus address translation. A trap table, a region table, and a patch table are first initialized (step S 500 ). A first address is compared with a trap region to acquire a comparison result (step S 502 ). The trap region is defined by the records in the trap table and the region table. If the comparison result is matched, a patch record indicating a second address is fetched from the patch table and second code is fetched according to the second address (step S 504 ). If the comparison result is not matched, first code is fetched according to the first address (step S 506 ).  
         [0032]     Here, the trap, region, and patch tables can be established in a microprocessor system. The first address is issued by the microprocessor to a first address bus and the second address is issued by a controller to a second address bus. The first code can be stored in a ROM and the second code can be stored in a RAM.  
         [0033]     As described, the provided systems and methods translate the address indicating to correct data, representing convenience significantly for program patching. The provided systems and methods can also be applied to manufacturing defect recovery for a ROM or data replacement.  
         [0034]      FIG. 6  is a diagram of an exemplary embodiment of ROM code replacement using a bus address translation method. For example, a large segment of ROM code indicated by B 2   602  in a ROM  60  is replaced. B 21   604  is a CPU address that falls into a trap region defined by a trap table  62  and a region table not shown here. A translated address, that is B 21 _  664 , is acquired from a patch table  64 . Code B 21   604  is replaced by code B 21 _  664  in a RAM or DRAM  66  through bus address translation.  
         [0035]     A branch instruction may be used in code B 21 _  664  for jumping to B 22 _  662 , replacing the whole segment B 2   602  in the ROM  60 . For some systems, the branch can be implemented by one direct instruction, such as “JUMP” or “BRANCH”. Alternatively, for some other systems, such as an ARM thumb mode, the branch cannot be implemented by one direct instruction. Therefore, an address attached by a region is effectual for bus address comparison rather than a single address. Additionally, a software interrupt service routine (ISR) can be used for program branch. Code B 22 _  662  can be placed in the ISR to achieve the program branch.  
         [0036]     A return address can be modified in the end of the ISR for returning an entry point of code B 3   606 . Thereafter, the program can return to regular executive procedure in ROM  60 .  
         [0037]      FIG. 7   a  and  FIG. 7   b  are flowcharts of an exemplary embodiment of ROM code replacement using a bus address translation method.  FIG. 7   a  illustrates ROM code replacement using branch instructions. A trap table, a region table, and a patch table are first initialized (step S 700 ). An address is compared with records in the trap table and the region table (step S 702 ). If the comparison is matched, a translated address is fetched from the patch table (step S 704 ). If the comparison is not matched, code or data is fetched from a ROM (step S 712 ). The execution branches to correct code according to the translated address through branch instructions (step S 706 ). The correct code is executed thereafter (step S 708 ). The program execution then returns to ROM code finally (step S 710 ).  
         [0038]      FIG. 7   b  illustrates ROM code replacement using software interrupt service routine (ISR). The difference between  FIG. 7   a  and  FIG. 7   b  is the branch instructions in step S 706 , are replaced by the software interrupt service routine (ISR) (step S 716 ). If the branch instructions are replaced by an ISR, the return can be accomplished by modifying ISR return address in step S 710 .  
         [0039]      FIG. 8  is a diagram of an exemplary embodiment of new code insertion using a bus address translation method. For example, new function code B 4   864  in a RAM  86  is appended after code B 1   802  in a ROM  80 . The address of B 2   804  and a corresponding region is translated to B 2 _  862  in the RAM  86  through a trap table  82 , a region table, and a patch table  84 . The program execution branches to B 4   864  in B 2 _  862  and executes code thereof. Since B 2   804  is replaced by B 2 _  862 , B 2   804  has to be recovered after the execution of B 4   864 . A copy of B 2 , that is B 2 (image)  866 , is appended to B 4 . After execution of B 2 (image)  866 , the program execution returns to B 3   806  in the ROM  80 . A new function code B 4   864  in the RAM  86  is thus inserted between B 1   802  and B 2   804  in the ROM  80 .  
         [0040]      FIG. 9   a  and  FIG. 9   b  are flowcharts of the exemplary embodiment of new code insertion using a bus address translation method.  FIG. 9   a  illustrates new code insertion using branch instructions. A trap table, a region table, and a patch table are first initialized (step S 900 ). An address is compared with records in the trap table and the region table (step S 902 ). If the comparison is matched, a translated address is fetched from the patch table (step S 904 ). If the comparison is not matched, code or data is fetched from a ROM (step S 906 ). The execution branches to new function code according to the translated address through branch instructions (step S 908 ). The new function code is executed thereafter (step S 910 ). The trap region image code is executed thereafter (step S 912 ). Finally, the program execution returns to ROM code (step S 914 ).  
         [0041]      FIG. 9   b  illustrates new code insertion using a software interrupt service routine (ISR). The difference between  FIG. 9   a  and  FIG. 9   b  is the branch instructions in step S 908 , are replaced by the software interrupt service routine (ISR) (step S 918 ). If the branch instructions are replaced by an ISR, the return can be accomplished by modifying the ISR return address in step S 914 .  
         [0042]     A patch program can be written by low-level programming languages, such as assembly language. Low-level programming languages, however, are difficult to maintain and develop.  FIG. 10  is a diagram of an embodiment of the structure of a patch program. The beginning/header  90  and/or end/tail  94  of the patch program can be implemented in low-level languages, while the main function  92  can be accomplished by a high-level programming language, such as the C language to increase flexibility and speed of program development.  
         [0043]     Methods and systems of the present disclosure, or certain aspects or portions of embodiments thereof, may take the form of program code (i.e., instructions) embodied in media, such as floppy diskettes, CD-ROMS, hard drives, firmware, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing and embodiment of the disclosure. The methods and apparatus of the present disclosure may also be embodied in the form of program code transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing and embodiment of the disclosure. When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to specific logic circuits.  
         [0044]     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents