Abstract:
A tracking switch includes an MOS switching transistor with a control terminal coupled to a CMOS inverter. The relative geometries of the transistors that make up the inverter are significantly imbalanced, resulting is substantially different drive strengths (i.e., substantially different on-resistances). The gate of the switching transistor exhibits parasitic capacitances between its current-handling terminals and its control terminal. When the switching transistor is on, these capacitances shunt a portion of the switched signal to a power-supply node, with the problem increasing with the frequency of the propagated signal. The geometry of the transistor used to turn on the switching transistor is selected to produce a high on-resistance, which introduces a high-impedance path from the control terminal of the switching transistor to ground when the switch is closed. The high-impedance path isolates the control terminal of the switching transistor from the supply, thus mitigating the capacitive loading effects of the parasitic capacitors. The transistor used to turn off the switching transistor has a much lower on-resistance than the transistor used to bias the switching transistor on, preventing undesirable signal feed-through from occurring when the switching transistor is off.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.  
       BACKGROUND  
       [0002]     MOS devices are commonly used as tracking switches. Such applications include samplers, multiplexers, track/hold circuits, etc. In the high-speed domain, the non-zero resistance and capacitance of an MOS transistor used to implement such a switch introduce bandwidth limitations that degrade the signal quality. There are techniques for reducing the channel resistance of MOS transistors, and consequently extending the operable bandwidth of tracking switches that utilize them. These techniques include driving the transistor gate by a voltage greater than the supply voltage. Using such so-called “overdrive” gate voltages provides higher channel conductance, and thus lower on-resistance; however, the circuitry required to generate the overdrive voltage above or below the supply voltages (e.g. greater than Vdd or less than ground potential) may be complex and require overdrive protection. There is therefore a need in the art for methods and circuits capable of switching high-speed signals without undue signal attenuation, particularly at relatively high frequencies. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0003]     The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:  
         [0004]      FIG. 1A  depicts a switch  100 , in accordance with one embodiment, that selectively passes a high-speed signal between an input terminal Vin and an output terminal Vout.  
         [0005]      FIG. 1B  is a waveform diagram  105  illustrating the operation of switch  100  of  FIG. 1A .  
         [0006]      FIG. 2  depicts a tracking switch  200  in accordance with another embodiment. Switch  200  is similar in some way to switch  100  of  FIG. 1A , like-numbered elements being the same or similar.  
         [0007]      FIG. 2B  is a waveform diagram illustrating the operation of switch  200  of  FIG. 2A .  
         [0008]      FIG. 3  depicts a tracking switch  300  in accordance with another embodiment. Switch  300  is similar to switch  200  in  FIG. 2A , but includes an NMOS transistor M 1  disposed between an input terminal Vin and an output terminal Vsam.  
         [0009]      FIG. 4  depicts a transmission gate  400  in accordance with yet another embodiment. Pass gate  400  includes NMOS and PMOS transistors  405  and  410 , respectively, coupled in parallel between terminals T 1  and T 2 . 
     
    
     DETAILED DESCRIPTION  
       [0010]      FIG. 1A  depicts a switch  100 , in accordance with one embodiment, that selectively passes a high-speed signal between an input terminal Vin and an output terminal Vout.  FIG. 1B  is a waveform diagram  105  illustrating the operation of switch  100  of  FIG. 1A . Switch  100  includes a PMOS switching transistor M 1  with a first current-handling terminal (e.g., a source S) coupled to input terminal Vin, a second current-handling terminal (e.g., a drain D) coupled to output terminal Vout, and a control terminal (e.g., a gate G) coupled to a control line Ctrl. Control line Ctrl is coupled to switch select terminal Sel via a CMOS inverter comprised of an NMOS transistor M 2  and a PMOS transistor M 3 .  
         [0011]     When select signal Sel is de-asserted (i.e., at a relatively low voltage expressive of a logic zero), transistor M 3  pulls control line Ctrl high, in this case toward supply voltage Vdd, turning off transistor M 1 ; conversely, when select signal Sel is asserted (i.e., at a relatively high voltage expressive of a logic one), transistor M 2  pulls control line Ctrl low, in this case toward ground, turning on transistor M 1 . Though not shown, select signal Sel and transistors M 2  and M 3  can likewise control additional pass transistors.  
         [0012]     At the schematic level, switch  100  is no different from some conventional switches. The improvement lies in the relative geometries of the transistors. In a conventional switch, transistors M 2  and M 3  are of similar strength, providing approximately the same on-resistance. Conventional inverters thus produce an inverted version of select signal Sel that follows changes in select signal Sel. Such a hypothetical inverted select signal is depicted in  FIG. 1B  as control signal Ctrl′, which is shown as a dashed line mirroring select signal Sel. In switch  100 , however, transistor M 2  has a relatively high on-resistance, realized by a relatively narrow, long-channeled NMOS device in this example. Transistor M 3  is relatively wider and shorter, and consequently exhibits a much lower on-resistance. The control signal Ctrl applied to transistor M 1  thus rises rapidly when transistor M 3  is turned on (and transistor M 2  off) and falls relatively slowly when transistor M 2  is turned on (and transistor M 3  off). The impedance between the current-handling terminals of a transistor biased on is primarily resistive, and is therefore referred to herein as an “on-resistance,” whereas the impedances between the current-handling terminals and the gate is primarily capacitance, and is therefore referred to as an impedance.  
         [0013]     With reference to  FIG. 1B , an illustrative signal Ctrl shows that the rise and fall times are substantially different due to the disparate on-resistances of transistors M 3  and M 2 . Switch  100  thus turns off much more quickly than on. The relatively slow turn-on speed is not important for some applications, such as when switch  100  is to be part of a programmable interconnect structure, and results in considerable performance gains when switch  100  is employed to transmit high-frequency signals.  
         [0014]     The gate of transistor M 1  exhibits parasitic capacitances Crs and Crd between respective current-handling terminals and the control terminal. These capacitances result from misalignment and overlap of the gate of transistor M 1  with respect to source and drain diffusions. Transistor M 1  additionally exhibits a channel capacitance Cch, the value of which is primarily a function of the gate area and properties of the gate insulator. For a more detailed discussion of the parasitic and inherent elements of a typical MOS transistor, see pp. 435-445 of “Device Electronics for Integrated Circuits, Second Edition,” by R. S. Muller and T. I. Kamins (1986), which is incorporated herein by reference. Notably, that reference separates channel capacitance Cch into gate-to-source capacitance Cgs and gate-to-drain capacitance Cgd.  
         [0015]     When switch  100  is on, transistor M 2  connects both current-handling terminals of transistor M 1  to ground via the parasitic and channel capacitances. As is well known, the impedance Z through a capacitance reduces with frequency, and is described using the following equation: Z=(C2πf) −1 , where C is capacitance and f is signal frequency. The impedance Z from the current-handling terminals of transistor M 1  to line Ctrl, and thus to ground, consequently reduces with frequency. Transistor  100 , when turned on, therefore acts as a low-pass filter, shunting high-frequency signal components to ground via transistor M 2 .  
         [0016]     The geometry of transistor M 2  is selected to produce a high on-resistance, which introduces a high-impedance path from the control terminal of transistor M 1  to ground. The high-impedance path isolates the control terminal of transistor M 1  from ground, thus mitigating the capacitive loading effects of parasitic capacitors C 1  and C 2 . In other words, as the frequency of the input signal increases, the high series impedance provided by transistor M 2  limits the effective conductance from the current-handling terminals of transistor M 1  to ground. Transistor M 3  has a much lower on-resistance than transistor M 2 , and is thus capable of turning off transistor M 1  quickly and preventing signal feed-through when switch  100  is biased off.  
         [0017]     The length “L” of transistors is most commonly the minimum feature size afforded by the process used to form the transistors. This convention holds true for transistors M 1  and M 3 , but transistor M 2  has a length ten times the minimum feature size. The respective geometries of the transistors of  FIG. 1  are as follows: 
        a. transistor M 1  has a W/L ratio of  60 , which is to say that the gate width of transistor M 1  is  60  times the length;     b. transistor M 2  has a W/L ratio of 1/10, which is to say that the gate length of transistor M 2  is  10  times the width; and     c. transistor M 3  has a W/L ratio of  10 , which is to say that the gate width of transistor M 3  is  10  times the length.        
 
         [0021]     The W/L ratio of transistor M 3  is thus 100 times the W/L ratio of transistor M 2 , in this example. The relationship between the geometries of transistors M 2  and M 3  can vary, however. The W/L ratio of transistor M 3  might be at least ten times the W/L ratio of transistor M 2 , for example.  
         [0022]     Changing transistor length-to-width ratios is only one way to alter transistor behavior. For example, capacitive values for an MOS transistor can change with the type and thickness of the gate dielectric, and resistive values can vary considerable for different types of devices, doping levels, feature geometries, supply voltage levels, etc. As a consequence of such variations, some embodiments characterize the relationship between transistors M 1 , M 2 , and M 3  in terms of impedance.  
         [0023]     The minimum impedance Z min  from the current-handling terminals of transistor M 1  to control line Ctrl may be expressed as Z min =(C 2 πf max ) −1 , where C is the total gate capacitance (Crs+Crd+Cch) of transistor M 1  and f max  is the maximum frequency of input signal Vin. In one embodiment, the on-resistance of transistor M 2  may be greater than impedance Z min , over an order of magnitude greater in some examples. Stated in another way, at frequency f max  the absolute value of the voltage V GS  developed between terminal Vin and line Ctrl is less than or equal to the absolute value of voltage Vin divided by the square root of two. Stated mathematically, when signal Vin is at frequency f max :  
                      V   GS          ≤            V   in            2         ⁢     
             (   1   )             
 
 The relationship of equation (1) ignores some minor variables for simplicity, but is a reasonably accurate approximation. To ensure transistor M 1  turns off quickly and to minimize signal feedthrough when transistor M 1  is off, the on-resistance of transistor M 3  is typically at least an order of magnitude lower than impedance Z min . 
 
         [0024]      FIG. 2  depicts a tracking switch  200  in accordance with another embodiment. Switch  200  may be similar in some ways to switch  100  of  FIG. 1A , like-numbered elements being the same or similar.  FIG. 2B  is a waveform diagram  212  illustrating the operation of switch  200  of  FIG. 2A .  
         [0025]     Switch  200  is a tracking switch adapted for use in e.g. high-speed voltage samplers, however, and so is modified in accordance with another embodiment to turn on more quickly than switch  100  of  FIG. 1 . Switch  200  switches on and off in response to a clock signal Clk on a like-named input terminal to sample an input signal on input terminal Vin. Sampled voltages are stored across a load capacitor  205  as a sampled voltage Vsam. Two additional NMOS transistors M 4  and M 5  and a CMOS inverter  210  assist transistor M 2  in pulling the control terminal of transistor M 1  down to turn transistor M 1  on quickly in response to rising edges of clock signal Clk.  
         [0026]     Switch  200  responds to falling edges on line Clk in much the same way switch  100  of  FIG. 1  responds to falling edges on line Ctrl. Turning to  FIG. 2B , inverter  210  responds with a corresponding rising edge and transistor M 3  pulls control line Ctrl high (toward Vdd). The rising edge on line Clkb turns on transistor M 5 , but this has little or no effect because the falling edge of clock signal Clk turns transistor M 4  off, isolating the control terminal of transistor M 1  from ground.  
         [0027]     Switch  200  responds to rising edges on line Clk in much the same way switch  100  of  FIG. 1  responds to rising edges on line Sel, but transistors M 4  and M 5  create an open a path to ground for an instant, passing a current spike Icomp to help transistor M 2  quickly turn off transistor M 1 . The resulting signals are exaggerated in  FIG. 2A  for ease of illustration.  
         [0028]     Transistor M 5  is on when clock signal Clk is high, and thus offers a path to ground upon the arrival of he first rising clock edge  220  of clock signal Clk. Rising edge  220  turns on transistors M 2 , M 4 , and the NMOS transistor of inverter  210 . Due to the delay inherent in inverter  210 , transistor M 4  begins turning on before transistor M 5  begins turning off. Transistors M 4  and M 5  thus shunt charge away from the control terminal of transistor M 1 , as illustrated by a current spike  230  in  FIG. 2B . The duration of current spike  230  can be adjusted by altering the delay induced by inverters  210 . In some embodiments, inverter  210  is programmable, as by the selective inclusion of parallel transistors or by controlling the level of supply current.  
         [0029]     Transistor M 2 , with the help of current spike  230 , pulls line Ctrl low to turn transistor M 1  on. Transistor M 2  then holds the on state beyond the duration of spike  230 , at which time transistor M 5  is off. As in the example of  FIG. 1A , transistor M 2  is highly resistive in the on state, which reduces the impact of the gate capacitance of transistor M 1  on higher-frequency signals. Switch  200  thus turns on quickly without a low-resistance path between the control terminal of transistor M 1  and ground. (A dashed line  235  indicates the slow fall-time of signal Ctrl that would occur in the absence of the help from current spike  230 .) The strength of transistors M 4  and M 5  may be selected to match that of transistor M 3 . In one embodiment, for example, transistors M 4  and M 5  each have the same W/L ratio of transistor M 3 . PMOS transistors are generally about twice as resistive as NMOS transistors, so the on-resistance of each of NMOS transistors M 4  and M 5  is about half that of transistor M 3 . Resistance adds in series however, so the on-resistance of transistors M 4  and M 5  combined approximately matches the on-resistance of transistor M 3 .  
         [0030]      FIG. 3  depicts a tracking switch  300  in accordance with another embodiment. Switch  300  is similar to switch  200  in  FIG. 2A , but includes an NMOS transistor M 1  in place of the PMOS transistor M 1  in  FIG. 2A . In this example, transistor M 2  exhibits a much lower on-resistance than transistor M 3 , and transistors M 4  and M 5  and an inverter  310  assist transistors M 3  in turning on transistor M 1  quickly. As is well understood in the art, PMOS transistors employ channels of p-type material that is generally less conductive than the n-type material employed in NMOS transistors. The desired relationship between the on-resistances of transistors M 2  and M 3  may therefore be obtained using somewhat different respective W/L ratios as compared with the examples of  FIGS. 1A and 2A .  
         [0031]      FIG. 4  depicts a transmission gate  400  in accordance with yet another embodiment. Pass gate  400  includes NMOS and PMOS transistors  405  and  410 , respectively, coupled in parallel between terminals T 1  and T 2 . Transmission gate  400  can pass signals between terminals T 1  and T 2  in either direction without a threshold drop. An active-low select signal SELb selectively closes gate  400  via a series-coupled pair of CMOS inverters.  
         [0032]     As in the foregoing examples, the control gates of transistors M 1  and M 2  are coupled to ground and Vdd, respectively, via transistors exhibiting relatively high on-resistances, and are coupled to Vdd and ground, respectively, via transistors exhibiting relatively high on-resistances. The W/L ratios of the four transistors M 3 , M 4 , M 5 , and M 6  that control transistors M 1  and M 2  in one embodiment are as follows: M 3 =10W/L, M 4 =W/10L, M 5 =W/4L and M 6 =5W/L. Where switching speed is an issue, configurations of the type described above in connection with  FIGS. 2A and 3  to reduce the turn-on time of pass transistors can be included to momentarily assist transistors M 4  and M 5 .  
         [0033]     In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “de-asserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is de-asserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). Whether a given signal is an active low or an active high will be evident to those of skill in the art.  
         [0034]     An output of the design process for an integrated circuit, or a portion of an integrated circuit, may be a computer-readable medium (e.g., a magnetic tape or an optical or magnetic disk) encoded with data structures or other information defining circuitry that may be physically instantiated as an integrated circuit or portion of an integrated circuit. These data structures are commonly written in Caltech Intermediate Format (CIF) or GDSII, a proprietary binary format. Those of skill in the art of mask preparation can develop such data structures from schematic diagrams of the type detailed above.  
         [0035]     While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example: 
        1. While the foregoing embodiments employ MOS transistors formed using standard CMOS processes, other transistor types or combinations of transistor types might also be used.     2. As noted in the background section above, some conventional devices overdrive the switched transistor to reduce the on-resistance, and consequently increase speed performance. Embodiments of the invention can be adapted to overdrive the gate to achieve still better high frequency performance.     3. Pass gates in accordance with other embodiments can be adapted to including clocking, e.g. in the manner described above in connection with  FIGS. 2A and 3 . 
 
 Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or “coupling,” establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. Section 112.