Abstract:
A first stage of a pipeline A/D converter is configured to output a sub analog signal at a level within a predetermined output voltage range even if a level of an input analog signal exceeds a predetermined input voltage range. Therefore, as compared with an example where a limiter circuit is provided on an input side of each stage, a pipeline A/D converter occupying a small area, consuming low power, and having small errors can be provided.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a pipeline A/D converter, and more particularly to a pipeline A/D converter obtained by cascading a plurality of low-bit A/D conversion stages (hereinafter, simply referred to as “stage”), for obtaining a final digital signal based on a digital signal obtained in each stage. 
         [0003]    2. Description of the Background Art 
         [0004]    Development in system LSI technology in recent years has enabled mounting of a large-scale system on a single LSI. A data converter is indispensable for input/output of an analog signal in such a system LSI. In the system LSI, as various types of information such as a sensor or image signal or a radio signal have more often been input, a plurality of A/D converters are often mounted on a single system LSI. Under such circumstances, pipeline A/D converters have increasingly been used in recent years as circuits excellent in terms of occupied area and power consumption. Meanwhile, further reduction in the area or lower power consumption is required also in pipeline A/D converters excellent in terms of occupied area and power consumption. Here, a shared amplifier configuration has been proposed as measures to meet such demands (see, for example, Japanese Patent Laying-Open No. 2005-252326). 
         [0005]    According to the shared amplifier configuration, with attention being paid to the fact that an amplifier in a general pipeline A/D converter operates during only half of one cycle, (1) the amplifier is shared between two adjacent pipeline stages, or (2) two sets of capacitors are provided to perform an interleaved operation so that the amplifier is shared by the two sets of capacitors. 
         [0006]    In the case of (1), the amplifier requiring largest area in the pipeline stage is shared by two stages so that the area can significantly be reduced, and efficiency in use of the amplifier is doubled so that power consumption can be lowered. Meanwhile, in the case of (2), though disadvantageous in terms of the area because of provision of two sets of capacitors, an operating time of the amplifier can be doubled so that a settling time required in the amplifier is significantly reduced, power required in the amplifier is significantly lowered, and the area of the amplifier can also be made smaller. 
         [0007]    It is likely that the shared amplifier configuration attaining such features will further increasingly be employed in the future, however, no period for resetting the amplifier is available in the pipeline stage adopting the shared amplifier configuration. Accordingly, a large potential difference between differential input terminals of the amplifier, caused by excessive input, is taken over for a plurality of cycles, which results in a great error during the operation over several cycles. Mechanism of this phenomenon is as described below. 
         [0008]    The pipeline stage constituting the pipeline A/D converter includes a switched capacitor circuit. With the effect of negative feedback and artificial ground of the amplifier, a sampled analog signal Vin is multiplied by a specific multiplier α (α is typically set to 2 or 4), and a reference voltage Vr=k·Vref (k=0, ±1, . . . ±(α−1); Vref represents a reference voltage determining an input range) selected in accordance with a level of analog signal Vin is subtracted (Vout=kVin−Vr). 
         [0009]    If signal Vin at such an excessively high level as exceeding Vref is input in performing this calculation, a voltage represented by Vout=kVin−Vr may not be output, because the output range of the amplifier is restricted by a power supply voltage Vdd. Here, the amplifier cannot make transition to a state of artificial ground, and a large potential difference is created between the differential input terminals of the amplifier. 
         [0010]    In order to solve this problem, it is possible to provide a limiter circuit for restricting an input voltage. The limiter circuit is mainly constituted of a comparator and a switch, however, slight deviation in accuracy of the comparator or in a reference potential is doubled or quadrupled per one stage, which results in a value significantly deviating from the input range after several stages. Thus, the possibility of overflow again arises. Accordingly, a large number of limiter circuits are required in order to avoid a great error. Meanwhile, if safety is to be ensured, a limiter circuit is required for each stage and the area therefor is very large. In addition, as a delay path is inserted in a signal path, speed characteristic of a circuit preceding the limiter circuit should be improved and increase in current consumption results. 
       SUMMARY OF THE INVENTION 
       [0011]    Therefore, an object of the present invention is to provide a pipeline A/D converter occupying a small area, consuming low power, and having small errors. 
         [0012]    A pipeline A/D converter according to the present invention is directed to a pipeline A/D converter converting an analog signal to a digital signal, that includes first to Nth (N is an integer not smaller than 2) stages that are cascaded, and an error correction circuit generating the digital signal based on sub digital signals output from the first to Nth stages. The first stage includes a first sub ADC converting the analog signal to the sub digital signal and providing the sub digital signal to the error correction circuit and a first sub DAC outputting to the second stage, a sub analog signal at a level in accordance with the analog signal and the sub digital signal generated in the first sub ADC. Each of the second to N−1th stages includes a second sub ADC converting the sub analog signal provided from a preceding stage to the sub digital signal and providing the sub digital signal to the error correction circuit and a second sub DAC outputting to a subsequent stage, a sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in the second sub ADC. The Nth stage includes a third sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to the error correction circuit. The first sub DAC is configured to output the sub analog signal at a level within a predetermined output voltage range even if the level of the analog signal exceeds a predetermined input voltage range. 
         [0013]    In the pipeline A/D converter according to the present invention, the first sub DAC in the first stage is configured to output the sub analog signal at a level within the predetermined output voltage range even if the level of the analog signal exceeds the predetermined input voltage range. Therefore, as compared with an example where a limiter circuit is provided on the input side of each stage, the pipeline A/D converter occupying a small area, consuming low power, and having small errors can be provided. 
         [0014]    The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a block diagram showing a configuration of a pipeline A/D converter according to a first embodiment of the present invention. 
           [0016]      FIG. 2  is a block diagram showing a configuration of a stage ST 1  shown in  FIG. 1 . 
           [0017]      FIG. 3  is a circuit block diagram showing a configuration of an overflow detection circuit shown in  FIG. 2 . 
           [0018]      FIG. 4  is a circuit block diagram showing a configuration of a comparator shown in  FIG. 3 . 
           [0019]      FIG. 5  is a circuit block diagram showing a configuration of a sub ADC shown in  FIG. 2 . 
           [0020]      FIG. 6  is a circuit block diagram showing a configuration of a comparator shown in  FIG. 5 . 
           [0021]      FIG. 7  is a circuit block diagram showing a configuration of a sub DAC shown in  FIG. 2 . 
           [0022]      FIG. 8  is a time chart illustrating an operation of the sub DAC shown in  FIG. 7 . 
           [0023]      FIG. 9  illustrates a transfer function of stage ST 1  shown in  FIGS. 2 to 8 . 
           [0024]      FIG. 10  illustrates an effect of stage ST 1  shown in  FIGS. 2 to 8 . 
           [0025]      FIG. 11  is a block diagram showing a configuration of a stage ST 2  shown in  FIG. 1 . 
           [0026]      FIG. 12  is a circuit block diagram showing a configuration of a sub ADC shown in  FIG. 11 . 
           [0027]      FIG. 13  is a circuit diagram showing a configuration of a sub DAC shown in  FIG. 11 . 
           [0028]      FIG. 14  is a time chart illustrating an operation of the sub DAC shown in  FIG. 13 . 
           [0029]      FIG. 15  illustrates a transfer function of stage ST 2  shown in  FIGS. 11 to 14 . 
           [0030]      FIG. 16  is a circuit block diagram showing a variation of the first embodiment. 
           [0031]      FIG. 17  is a block diagram showing a configuration of a pipeline A/D converter according to a second embodiment of the present invention. 
           [0032]      FIG. 18  is a block diagram showing a configuration of a stage ST 23  shown in  FIG. 17 . 
           [0033]      FIG. 19  is a circuit diagram showing a configuration of a sub DAC shown in  FIG. 18 . 
           [0034]      FIG. 20  is a time chart illustrating an operation of the sub DAC shown in  FIG. 19 . 
           [0035]      FIG. 21  is a block diagram showing a configuration of a pipeline A/D converter according to a third embodiment of the present invention. 
           [0036]      FIG. 22  is a block diagram showing a configuration of a stage ST 11  shown in  FIG. 21 . 
           [0037]      FIG. 23  is a circuit block diagram showing a configuration of an overflow detection circuit shown in  FIG. 22 . 
           [0038]      FIG. 24  is a circuit block diagram showing a configuration of a sub ADC shown in  FIG. 22 . 
           [0039]      FIG. 25  is a circuit diagram showing a configuration of a sub DAC shown in  FIG. 22 . 
           [0040]      FIG. 26  is a time chart illustrating an operation of the sub DAC shown in  FIG. 25 . 
           [0041]      FIG. 27  illustrates a transfer function of stage ST 11  shown in  FIGS. 22 to 26 . 
           [0042]      FIG. 28  illustrates an effect of stage ST 11  shown in  FIGS. 22 to 26 . 
           [0043]      FIG. 29  is a circuit block diagram showing a variation of the third embodiment. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       [0044]      FIG. 1  is a block diagram showing a configuration of a pipeline A/D converter according to a first embodiment of the present invention. In  FIG. 1 , the pipeline A/D converter includes eight stages ST 1  to ST 8  that are cascaded and an error correction circuit  1 . 
         [0045]    First stage ST 1  receives an analog signal ΔVin to be A/D converted. Stage ST 1  generates a digital signal Dout of 3.25 bits (any of 0000 to 1000) based on input analog signal ΔVin, and provides generated digital signal Dout to error correction circuit  1 . In addition, stage ST 1  generates an analog signal ΔVout at a level in accordance with input analog signal ΔVin and generated digital signal Dout, and provides generated analog signal ΔVout to next stage ST 2 . Moreover, stage ST 1  includes an overflow prevention circuit maintaining analog signal ΔVout within a normal range even if the level of input analog signal ΔVin exceeds a prescribed input voltage range. 
         [0046]    Second stage ST 2  generates a digital signal Dout 1  of 1.5 bit (any of 00 to 10) based on analog signal ΔVout from preceding stage ST 1  and provides generated digital signal Dout 1  to error correction circuit  1 . In addition, stage ST 2  generates an analog signal ΔVout 1  at a level in accordance with input analog signal ΔVout and generated digital signal Dout 1 , and provides generated analog signal ΔVout 1  to next stage ST 3 . Stage ST 2  adopts what is called a lateral shared amplifier configuration. Each of third to seventh stages ST 3  to ST 7  is configured similarly to stage ST 2 . 
         [0047]    Last stage ST 8  includes a comparator, generates a digital signal Dout 7  of 2 bits (any of 00 to 11) based on an analog signal ΔVout 6  from preceding stage ST 7 , and provides generated digital signal Dout 7  to error correction circuit  1 . Error correction circuit  1  outputs a last digital signal DOUT based on digital signals Dout to Dout 7  output from stages ST 1  to ST 8 . 
         [0048]      FIG. 2  is a block diagram showing a configuration of first stage ST 1 . In  FIG. 2 , stage ST 1  includes an overflow detection circuit  2 , a sub ADC (sub A/D converter)  3 , and a sub DAC (sub D/A converters  4 . When the level of input analog signal ΔVin is excessively high, overflow detection circuit  2  sets a signal φ 7  to “H” level representing an activation level. Sub ADC  3  converts input analog signal ΔVin to digital signal Dout of 3.25 bits and provides the digital signal to error correction circuit  1 , as well as provides a switch signal in accordance with the level of analog signal ΔVin to sub DAC  4 . Sub DAC  4  generates analog signal ΔVout based on input analog signal Vin and the switch signal from sub ADC  3 , and provides generated analog signal ΔVout to next stage ST 2 . In addition, when the level of analog signal Vin is excessively high and signal φ 7  is set to “H”, sub DAC  4  sets analog signal ΔVout to 0 level. 
         [0049]      FIG. 3  is a circuit block diagram showing a configuration of overflow detection circuit  2 . In  FIG. 3 , overflow detection circuit  2  includes comparators  5  and  6 , an OR gate  7 , an inverter  7   a , and a reference voltage generation circuit  8 . Reference voltage generation circuit  8  includes sixteen resistance elements  8   a  connected in series. As these resistance elements  8   a  have equal resistance values, a reference voltage VRT−VRB is divided to generate reference voltages VA=(VRT−VRB)×9/16, VB=(VRT−VRB)×7/16, and VCM=(VRT−VRB)/2. 
         [0050]    Comparator  5  compares input analog signal ΔVin=V in+ −V in−  with a reference voltage VRT−VRB+VA−VB=(VRT−VRB)×9/8, which represents the upper limit. If relation of V in+ −V in− &gt;(VRT−VRB)×9/8 is satisfied, a signal φ 5  is set to “H” level, whereas if relation of V in+ −V in− &lt;(VRT−VRB)×9/8 is satisfied, signal φ 5  is set to “L” level. 
         [0051]    Comparator  6  compares input analog signal ΔVin=V in+ −V in−  with a reference voltage VRB−VRT+VB−VA=(VRB−VRT)×9/8, which represents the lower limit. If relation of V in+ −V in− &lt;(VRB−VRT)×9/8 is satisfied, a signal φ 6  is set to “H” level, whereas if relation of V in+ −V in− &gt;(VRB−VRT)×9/8 is satisfied, signal φ 6  is set to “L” level. 
         [0052]    Inverter  7   a  receives output signal φ 6  of comparator  6  and outputs an inverted signal/φ 6  thereof OR gate  7  receives output signal φ 5  of comparator  5 , output signal/φ 6  of inverter  7   a  and a clock signal φ 1   c , and outputs a signal φ 7 . When at least one of signals φ 5 , /φ 6  and φ 1   c  is at “H” level, signal φ 7  is set to “H” level. 
         [0053]      FIG. 4  is a circuit block diagram showing a configuration of comparator  5 . In  FIG. 4 , comparator  5  includes switches  11  to  22 , capacitors  23  to  26 , a differential amplifier  27 , a latch circuit  28 , and an AND gate  29 . One terminals of switches  11  to  18  receive voltage signals VCM, VA, V in+ , VRT, VRB, V in− , VB, and VCM, respectively. The other terminals of switches  11 ,  13 ,  15 , and  17  are connected to one terminals of capacitors  23  to  26 , respectively. The other terminals of switches  12 ,  14 ,  16 , and  18  are connected to one terminals of capacitors  23  to  26 , respectively. 
         [0054]    The other terminals of capacitors  23  and  24  are both connected to a + input terminal of differential amplifier  27 . The other terminals of capacitors  25  and  26  are both connected to a − input terminal of differential amplifier  27 . Switch  19  is connected between the + input terminal and a − output terminal of differential amplifier  27 . Switch  20  is connected between the − input terminal and a + output terminal of differential amplifier  27 . The + output terminal and the − output terminal of differential amplifier  27  are connected to latch circuit  28 , with switches  21  and  22  being interposed, respectively. AND gate  29  outputs an AND signal of clock signal φ 2  and an output signal of latch circuit  28  as output signal φ 5  of comparator  5 . 
         [0055]    During a period in which clock signal φ 2  is at “H” level (clock signal /φ 2  is at “L” level), switches  12 ,  14 ,  15 ,  17 ,  19 , and  20  are conducting, while remaining switches  11 ,  13 ,  16 ,  18 ,  21 , and  22  are non-conducting. A voltage at the + input terminal and a voltage at the − input terminal of differential amplifier  27  are denoted as Vx 1  and Vx 2  respectively. Here, as input and output terminals of differential amplifier  27  are short-circuited through switches  19  and  20 , an operation is such that the input voltage and the output voltage of differential amplifier  27  match with each other, namely, relation of Vx 1 =Vx 2 =VAZ is satisfied. VAZ is referred to as an auto zero potential that is obtained when the input and output terminals of differential amplifier  27  are short-circuited. Therefore, assuming that a capacitance value of each of capacitors  23  to  27  is denoted as C, charges Q 1 =C(VA−VAZ), Q 2 =C(VRT−VAZ), Q 3 =C(VRB−VAZ), and Q 4 =C(VB−VAZ) are charged to capacitors  23  to  26 , respectively. 
         [0056]    During a period in which clock signal φ 2  is at “L” level (clock signal /φ 2  is at “H” level), switches  11 ,  13 ,  16 ,  18 ,  21 , and  22  are conducting, while remaining switches  12 ,  14 ,  15 ,  17 ,  19 , and  20  are non-conducting. Here, the potential at one terminals of capacitors  23  and  24  varies, however, the other terminals of capacitors  23  and  24  enter a high impedance state. Therefore, charges in capacitors  23  and  24  are stored, and relation of Q 1 +Q 2 =C(VCM−Vx 1 )+C(V in+ −Vx 1 )=C(VA−VAZ)+C(VRT−VAZ) is satisfied. Similarly, charges in capacitors  25  and  26  are stored, and relation of Q 3 +Q 4 =C(VCM−Vx 2 )+C(V in− Vx 2 )=C(VRB−VAZ)+C(VB−VAZ) is satisfied. Based on these expressions, relation of Vx 1 ={(V in+ +VCM)−(VRT+VA)}/2+VAZ and Vx 2 ={(V in− +VCM)−(VRB+VB)}/2+VAZ is satisfied. 
         [0057]    Here, assuming that a voltage at the + output terminal and a voltage at the output terminal of differential amplifier  27  are denoted as Vy 1  and Vy 2  respectively and an amplification ratio is denoted as A, relation of Vy 1 −Vy 2 =A(Vx 1 −Vx 2 )=A{(V in+ −V in− )−(VRT−VRB+VA−VB)}/2 is satisfied. Therefore, a difference between (V in+ −V in− ) and (VRT−VRB+VA−VB)=(VRT−VRB)×9/8 is amplified by differential amplifier  27 , whereby Vy 1  attains to “H” level or “L” level while Vy 2  attains to “L” level or “H” level. Latch circuit  28  takes in the level of the signal provided through switch  21  during a period in which clock signal φ 2  is at “L” level, and outputs the taken signal during a period in which clock signal φ 2  is at “H” level. 
         [0058]    Ultimately, when clock signal φ 2  is at “H” level and relation of V in+ −V in− &gt;(VRT−VRB)×9/8 is satisfied, signal φ 5  is set to “H” level. When clock signal φ 2  is at “H” level and relation of V in+ −V in− &lt;(VRT−VRB)×9/8 is satisfied, signal φ 5  is set to “L” level. When clock signal φ 2  is at “L” level, signal φ 5  is constantly at “L” level. 
         [0059]    Comparator  6  is configured similarly to comparator  5 . It is noted that reference voltages VB, VRB, VRT, and VA are input to one terminals of switches  12 ,  14 ,  15 , and  17 , instead of reference voltages VA, VRT, VRB, and VB. 
         [0060]      FIG. 5  is a circuit block diagram showing a configuration of sub ADC  3 . In  FIG. 5 , sub ADC  3  includes a reference voltage generation circuit  30 , comparators  31  to  38 , and an encoder  39 . Reference voltage generation circuit  30  includes sixteen resistance elements  30   a  connected in series. A reference voltage VRT−VRB=ΔVref is divided to generate reference voltages V 1  to V 8 . Sixteen resistance elements  30   a  have equal resistance values. 
         [0061]    Comparators  31  to  38  are activated while clock signal φ 2  is at “H” level. Comparator  31  compares analog signal V in+ −V in−  with reference voltage V 1 −V 8 =ΔVref×7/8. If relation of V in+ −V in− &gt;ΔVref×7/8 is satisfied, signals φ 2   a  and /φ 2   a  are set to “H” level and “L” level respectively, whereas if relation of V in+ −V in− &lt;ΔVref×7/8 is satisfied, signals φ 2   a  and /φ 2   a  are set to “L” level and “H” level respectively. Comparator  32  compares analog signal V in+ −V in−  with reference voltage V 2 −V 7 =ΔVref×5/8. If relation of V in+ −V in− &gt;ΔVref×5/8 is satisfied, signals φ 2   b  and /φ 2   b  are set to “H” level and “L” level respectively, whereas if relation of V in+ −V in− &lt;ΔVref×5/8 is satisfied, signals φ 2   b  and /φ 2   b  are set to “L” level and “H” level respectively. 
         [0062]    Comparator  33  compares analog signal V in+ −V in−  with reference voltage V 3 −V 6 =ΔVref×3/8. If relation of V in+ −V in− &gt;ΔVref×3/8 is satisfied, signals φ 2   c  and /φ 2   c  are set to “H” level and “L” level respectively, whereas if relation of V in+ −V in− &lt;ΔVref×3/8 is satisfied, signals φ 2   c  and /φ 2   c  are set to “L” level and “H” level respectively. Comparator  34  compares analog signal V in+ −V in−  with reference voltage V 4 −V 5 =ΔVref/8. If relation of V in+ −V in− &gt;ΔVref/8 is satisfied, signals φ 2   d  and /φ 2   d  are set to “H” level and “L” level respectively, whereas if relation of V in+ −V in− &lt;ΔVref/8 is satisfied, signals φ 2   d  and /φ 2   d  are set to “L” level and “H” level respectively. 
         [0063]    Comparator  35  compares analog signal V in+ −V in−  with reference voltage V 5 −V 4 =−ΔVref/8. If relation of V in+ −V in− &gt;−ΔVref/8 is satisfied, signals φ 2   e  and /φ 2   e  are set to “H” level and “L” level respectively, whereas if relation of V in+ −V in− &lt;−ΔVref/8 is satisfied, signals φ 2   e  and /φ 2   e  are set to “L” level and “H” level respectively. Comparator  36  compares analog signal V in+ −V in−  with reference voltage V 6 −V 3 =−ΔVref×3/8. If relation of V in+ −V in− &gt;−ΔVref×3/8 is satisfied, signals φ 2   f  and /φ 2   f  are set to “H” level and “L” level respectively, whereas if relation of V in+ −V in− &lt;−ΔVref×3/8 is satisfied, signals φ 2   f  and /φ 2   f  are set to “L” level and “H” level respectively. 
         [0064]    Comparator  37  compares analog signal V in+ −V in−  with reference voltage V 7 −V 2 =−ΔVref×5/8. If relation of V in+ −V in− &gt;−ΔVref×5/8 is satisfied, signals φ 2   g  and /φ 2   g  are set to “H” level and “L” level respectively, whereas if relation of V in+ −V in− &lt;−ΔVref×5/8 is satisfied, signals φ 2   g  and /φ 2   g  are set to “L” level and “H” level respectively. Comparator  38  compares analog signal V in+ −V in−  with reference voltage V 8 −V 1 =−ΔVref×7/8. If relation of V in+ −V in− &gt;−ΔVref×7/8 is satisfied, signals φ 2   h  and /φ 2   h  are set to “H” level and “L” level respectively, whereas if relation of V in+ −V in− &lt;−ΔVref×7/8 is satisfied, signals φ 2   h  and /φ 2   h  are set to “L” level and “H” level respectively. When clock signal φ 2  is at “L” level, output signals φ 2   a  to φ 2   h  and /φ 2   a  to /φ 2   h  of comparators  31  to  38  are fixed to “L” level. Encoder  39  generates digital signal Dout of 3.25 bits based on output signals φ 2   a  to φ 2   h  of comparators  31  to  38 , and outputs generated digital signal Dout to error correction circuit  1 . 
         [0065]      FIG. 6  is a circuit block diagram showing a configuration of comparator  31 . In  FIG. 6 , comparator  31  includes switches  41  to  48 , capacitors  49  and  50 , a differential amplifier  51 , a latch circuit  52 , and AND gates  53  and  54 . One terminals of switches  41  to  44  receive voltage signals V 1 , V in+ , V in− , and V 8 , respectively. The other terminals of switches  41  and  43  are connected to one terminals of capacitors  49  and  50 , respectively. The other terminals of switches  42  and  44  are connected to one terminals of capacitors  49  and  50 , respectively. 
         [0066]    The other terminals of capacitors  49  and  50  are connected to a + input terminal and a − input terminal of differential amplifier  51 , respectively. Switch  45  is connected between the + input terminal and an − output terminal of differential amplifier  51 . Switch  46  is connected between the − input terminal and an + output terminal of differential amplifier  51 . The + output terminal and the − output terminal of differential amplifier  51  are connected to latch circuit  52 , with switches  47  and  48  being interposed, respectively. AND gate  53  outputs an AND signal of clock signal φ 2  and an output signal of latch circuit  52  as output signal φ 2   a  of comparator  31 . AND gate  54  outputs an AND signal of clock signal φ 2  and an inverted output signal of latch circuit  52  as output signal /φ 2   a  of comparator  31 . 
         [0067]    During a period in which clock signal φ 2  is at “H” level (clock signal /φ 2  is at “L” level), switches  41  and  44  to  46  are conducting, while remaining switches  42 ,  43 ,  47 , and  48  are non-conducting. A voltage at the + input terminal and a voltage at the − input terminal of differential amplifier  51  are denoted as Vx 1  and Vx 2  respectively. Here, as input and output terminals of differential amplifier  51  are short-circuited through switches  45  and  46 , an operation is such that the input voltage and the output voltage of differential amplifier  51  match with each other, namely, relation of Vx 1 =Vx 2 =VAZ is satisfied. VAZ is referred to as an auto zero potential that is obtained when the input and output terminals of differential amplifier  51  are short-circuited. Therefore, assuming that a capacitance value of each of capacitors  49  and  50  is denoted as C, charges Q 1 =C(V 1 −VAZ) are charged to capacitor  49  and charges Q 2 =C(V 8 −VAZ) are charged to capacitors  50 . 
         [0068]    During a period in which clock signal φ 2  is at “L” level (clock signal /φ 2  is at “H” level), switches  42 ,  43 ,  47 , and  48  are conducting, while remaining switches  41  and  44  to  46  are non-conducting. Here, the potential at one terminal of capacitor  49  varies from V 1  to V in+ , however, the other terminal of capacitor  49  enters a high impedance state. Then, charges in capacitor  49  are stored, and relation of Q 1 =C(V in+ −Vx 1 )=C(V 1 −VAZ) is satisfied. Similarly, charges in capacitor  50  are stored, and relation of Q 2 =C(V in− −Vx 2 )=C(V 8 −VAZ) is satisfied. Based on these expressions, relation of Vx 1 =(V in+ −V 1 )+VAZ and Vx 2 =(V in− −V 8 )+VAZ is satisfied. 
         [0069]    Here, assuming that a voltage at the + output terminal and a voltage at the − output terminal of differential amplifier  51  are denoted as Vy 1  and Vy 2  respectively and an amplification ratio is denoted as A, relation of Vy 1 −Vy 2 =A(Vx 1 −Vx 2 )=A{(V in+ −V in− )−(V 1 −V 8 )} is satisfied. Therefore, a difference between (V in+ −V in− ) and (V 1 −V 8 ) is amplified by differential amplifier  51 , whereby Vy 1  attains to “H” level or “L” level while Vy 2  attains to “L” level or “H” level. Latch circuit  52  takes in the level of the signal provided through switches  47  and  48  during a period in which clock signal φ 2  is at “L” level, and outputs the taken signal during a period in which clock signal φ 2  is at “H” level. 
         [0070]    Ultimately, when clock signal φ 2  is at “H” level and relation of V in+ −V in− &gt;V 1 −V 8  is satisfied, signals φ 2   a  and /φ 2   a  are set to “H” level and “L” level respectively. When clock signal φ 2  is at “H” level and relation of V in+ −V in− &lt;V 1 −V 8  is satisfied, signals φ 2   a  and /φ 2   a  are set to “L” level and “H” level respectively. When clock signal φ 2  is at “L” level, signals φ 2   a  and /φ 2   a  are always at “L” level. 
         [0071]    Each of comparators  32  to  38  is configured similarly to comparator  31 . It is noted that reference voltages V 2 , V 7 ; V 3 , V 6 ; V 4 , V 5 ; V 5 , V 4 ; V 6 , V 3 ; V 7 , V 2 ; V 8 , V 1  are input to one terminals of switches  41  and  44 , instead of reference voltages V 1 , V 8 . 
         [0072]      FIG. 7  is a circuit diagram showing a configuration of sub DAC  4 . In  FIG. 7 , sub DAC  4  includes switches  61  to  66  and capacitors  67  and  68  provided in correspondence with each of comparators  31  to  38  in  FIG. 5 , switches  69  to  71 , capacitors  72  to  75 , and a differential amplifier  76 . 
         [0073]    One terminals of switches  61  to  63  receive voltage signals V in+ , VRT, and VRB respectively, and switches  61  to  63  have the other terminals connected to one terminal of capacitor  67 . Capacitor  67  has the other terminal connected to a + input terminal of differential amplifier  76 . Switch  61  conducts while a clock signal φ 1  is at “H” level, and switches  62  and  63  conduct when output signals (in this case, φ 2   a  and /φ 2   a ) of each corresponding comparator (such as  31 ) are at “H” level. 
         [0074]    One terminals of switches  64  to  66  receive voltage signals V in− , VRB, and VRT respectively, and switches  64  to  66  have the other terminals connected to one terminal of capacitor  68 . Capacitor  68  has the other terminal connected to a − input terminal of differential amplifier  76 . Switch  64  conducts while clock signal φ 1  is at “H” level, and switches  65  and  66  conduct when output signals (in this case, φ 2   a  and /φ 2   a ) of each corresponding comparator (such as  31 ) are at “H” level. 
         [0075]    One terminals of switches  69  and  70  both receive reference voltage VCM, and switches  69  and  70  have the other terminals connected to the + input terminal and the − input terminal of differential amplifier  76  respectively. Switch  71  is connected between a + output terminal and a − output terminal of differential amplifier  76 . Switches  69  to  71  conduct during a period in which signal φ 7  is at “H” level. 
         [0076]    Capacitors  72  and  73  are connected in parallel between the + input terminal and the − output terminal of differential amplifier  76 . Capacitors  74  and  75  are connected in parallel between the − input terminal and the + output terminal of differential amplifier  76 . Capacitors  67 ,  68  and  72  to  75  have equal capacitance values. Analog signals V out+ , V out−  are output from the − output terminal and the + output terminal of differential amplifier  76  respectively. Here, relation of ΔVout=V out+ −V out−  is satisfied. 
         [0077]      FIG. 8  is a time chart illustrating an operation of sub DAC  4 . In  FIG. 8 , clock signal φ 1  is set to “H” level from time t 1  to t 2 , from t 3  to t 4 , from t 5  to t 6 , from t 7  to t 8 , and so on, and set to “L” level from time t 2  to t 3 , from t 4  to t 5 , from t 6  to t 7 , from t 8  to t 9 , and so on. Clock signal φ 1   c  is a signal of which falling is earlier by a prescribed period than falling of clock signal φ 1 . Signal φ 7  is an output signal of overflow detection circuit  2 . Signals φ 2   a  to φ 2   h  and /φ 2   a  to /φ 2   h  are output signals of comparators  31  to  38 . 
         [0078]    When signal φ 1  is raised to “H” level at time t 1 , signals φ 1   c  and φ 7  are also raised to “H” level. Thus, each switch  61 , each switch  64 , and switches  69  to  71  conduct, each capacitor  67  is charged with a differential voltage between signal V in+  and reference voltage VCM, and each capacitor  68  is charged with a differential voltage between signal V in−  and reference voltage VCM. In addition, when signal φ 1  falls to “L” level at time t 2 , switches  61  and  64  become non-conducting. 
         [0079]    Here, it is assumed that input signal V in+ −V in−  overflows to the positive side. Then, even when signal φ 1   c  attains to “L” level, signal φ 7  is maintained at “H” level, signals φ 2   a  to φ 2   h  attain to “H” level, and signals /φ 2   a  to /φ 2   h  attain to “L” level. Thus, each switch  62 , each switch  65 , and switches  69  to  71  conduct, and output voltage V out+ −V out−  of differential amplifier  76  is set to 0V. 
         [0080]    When signal φ 1  is raised to “H” level at time t 3 , signals φ 1   c  and φ 7  are also raised to “H” level. Thus, each switch  61 , each switch  64 , and switches  69  to  71  conduct, each capacitor  67  is charged with the differential voltage between signal V in+  and reference voltage VCM, and each capacitor  68  is charged with the differential voltage between signal V in−  and reference voltage VCM. In addition, when signal φ 1  falls to “L” level at time t 4 , switches  61  and  64  become non-conducting. 
         [0081]    Here, it is assumed that overflow of input signal V in+ −V in−  does not occur. Then, when signal φ 1   c  attains to “L” level, signal φ 7  falls to “L” level, some of signals φ 2   a  to φ 2   h  and /φ 2   a  to /φ 2   h  attain to “H” level in accordance with the level of input signal V in+ −V in− , and remaining signals attain to “L” level (this state is shown with * 1  and * 2  in  FIG. 8 ). Thus, switches  69  to  71  become non-conducting, and switches  62 ,  63 ,  65 , and  66  corresponding to the signal at “H” level out of signals φ 2   a  to φ 2   h  and /φ 2   a  to /φ 2   h  conduct. Thus, voltage V out+ −V out−  at a level in accordance with the level of input signal V in+ −V in−  is output. 
         [0082]    Here, V in+ −V in−  is denoted as ΔVin, V out+ −V out−  is denoted as ΔVy, and VRT−VRB is denoted as ΔVref. If all of φ 2   a  to φ 2   h  are at “H” level, relation of ΔVy=4ΔVin−4ΔVref is satisfied. Meanwhile, if only φ 2   b  to φ 2   h  among φ 2   a  to φ 2   h  are at “H” level, relation of ΔVy=4ΔVin−3ΔVref is satisfied. In addition, if only φ 2   c  to φ 2   h  among φ 2   a  to φ 2   h  are at “H” level, relation of ΔVy=4ΔVin−2ΔVref is satisfied. Moreover, if only φ 2   d  to φ 2   h  among φ 2   a  to φ 2   h  are at “H” level, relation of ΔVy=4ΔVin−ΔVref is satisfied. Further, if only φ 2   e  to φ 2   h  among φ 2   a  to φ 2   h  are at “H” level, relation of ΔVy=4ΔVin is satisfied. 
         [0083]    In addition, if only φ 2   f  to φ 2   h  among φ 2   a  to φ 2   h  are at “H” level, relation of ΔVy=4ΔVin+ΔVref is satisfied. Moreover, if only φ 2   g  to φ 2   h  among φ 2   a  to φ 2   h  are at “H” level, relation of ΔVy=4ΔVin+2ΔVref is satisfied. Further, if only 42h among φ 2   a  to φ 2   h  is at “H” level, relation of ΔVy=4ΔVin+3ΔVref is satisfied. In addition, all of φ 2   a  to φ 2   h  are at “L” level, relation of ΔVy=4ΔVin+4ΔVref is satisfied. 
         [0084]    When signal φ 1  is raised to “H” level at time t 7 , signals φ 1   c  and φ 7  are also raised to “H” level. Thus, each switch  61 , each switch  64 , and switches  69  to  71  conduct, each capacitor  67  is charged with the differential voltage between signal V in+  and reference voltage VCM, and each capacitor  68  is charged with the differential voltage between signal V in−  and reference voltage VCM. In addition, when signal φ 1  falls to “L” level at time t 8 , switches  61  and  64  become non-conducting. 
         [0085]    Here, it is assumed that input signal V in+ −V in−  overflows to the negative side. Then, even when signal φ 1   c  attains to “L” level, signal φ 7  is maintained at “H” level, signals φ 2   a  to φ 2   h  attain to “L” level, and signals /φ 2   a  to /φ 2   h  attain to “H” level. Thus, each switch  63 , each switch  66 , and switches  69  to  71  conduct, and output voltage V out+ −V out−  of differential amplifier  76  is set to 0V. 
         [0086]      FIG. 9  illustrates a transfer function of stage ST 1 . In  FIG. 9 , the abscissa represents ΔVin=V in+ −V in− , and the ordinate represents ΔVout=V out+ −V out− . In a section 0&lt;ΔVin&lt;ΔVref/8, relation of ΔVout=ΔVin×4 is satisfied. In a section ΔVref/8&lt;ΔVin&lt;ΔVref×3/8, relation of ΔVout=ΔVin×4−ΔVref is satisfied. In a section ΔVref×3/8&lt;ΔVin&lt;ΔVref×5/8, relation of ΔVout=ΔVin×4−ΔVref×2 is satisfied. In a section ΔVref×5/8&lt;ΔVin&lt;ΔVref×7/8, relation of ΔVout=ΔVin ×4−ΔVref×3 is satisfied. In a section ΔVref×7/8&lt;ΔVin&lt;ΔVref×9/8, relation of ΔVout=ΔVin×4−ΔVref×4 is satisfied. In a section ΔVref×9/8&lt;ΔVin, relation of ΔVout=0 is satisfied. 
         [0087]    Thus, a curve representing the transfer function makes a turn from the positive side toward the negative side when ΔVin attains to ΔVref/8, ΔVref×3/8, ΔVref×5/8, ΔVref×7/8, and ΔVref×9/8. ΔVref/8, ΔVref×3/8, ΔVref×5/8, and ΔVref×7/8 correspond to comparators  34 ,  33 ,  32 , and  31  respectively, and ΔVref×9/8 corresponds to comparator  5 . 
         [0088]    In a section 0&gt;ΔVin&gt;−ΔVref/8, relation of ΔVout=ΔVin×4 is satisfied. In a section −ΔVref/8&gt;ΔVin&gt;−ΔVref×3/8, relation of ΔVout=ΔVin×4+ΔVref is satisfied. In a section −ΔVref×3/8&gt;ΔVin&gt;−ΔVref×5/8, relation of ΔVout=ΔVin×4+ΔVref×2 is satisfied. In a section −ΔVref×5/8&gt;ΔVin&gt;−ΔVref×7/8, relation of ΔVout=ΔVin×4+ΔVref×3 is satisfied. In a section −ΔVref×7/8&gt;ΔVin&gt;−ΔVref×9/8, relation of ΔVout=ΔVin×4+ΔVref×4 is satisfied. In a section −ΔVref×9/8&gt;ΔVin, relation of ΔVout=0 is satisfied. 
         [0089]    Thus, when viewed in a direction from 0 to −ΔVref, a curve representing the transfer function makes a turn from the negative side toward the positive side when ΔVin attains to −ΔVref/8, −ΔVref×3/8, −ΔVref×5/8, −ΔVref×7/8, and −ΔVref×9/8. −ΔVref/8, −ΔVref×3/8, −ΔVref×5/8, and −ΔVref×7/8 correspond to comparators  35  to  38  respectively, and −ΔVref×9/8 corresponds to comparator  6 . 
         [0090]    A dotted line in  FIG. 9  represents a transfer function of a first stage in a conventional pipeline A/D converter. In the conventional first stage, a digital signal of 2.75 bits has been generated using −ΔVref×5/8, −ΔVref×3/8, −ΔVref/8, ΔVref/8, ΔVref×3/8, and ΔVref×5/8 as reference voltages. The transfer function of the conventional first stage is the same as the transfer function of stage ST 1  according to the first embodiment in the section 0&lt;ΔVin&lt;ΔVref×7/8, however, if ΔVin is higher than ΔVref×7/8, ΔVout increases in proportion to ΔVin and reaches power supply voltage Vdd. Meanwhile, the transfer function of the conventional first stage is the same as the transfer function of stage ST 1  according to the first embodiment in the section 0&gt;ΔVin&gt;−ΔVref×7/8, however, if ΔVin is lower than −ΔVref×7/8, ΔVout decreases in proportion to ΔVin and reaches power supply voltage −Vdd. In other words, with the conventional first stage, if ΔVin is higher than ΔVref×7/8 or lower than −ΔVref×7/8, ΔVout exceeds the normal output voltage range. 
         [0091]    In contrast, with stage ST 1  according to the first embodiment, two more turning points of the transfer function are provided on each of the positive side and the negative side. In addition, if ΔVin is higher than ΔVref×9/8 or lower than −ΔVref×9/8, output voltage ΔVout is set to 0V. Therefore, ΔVout is always accommodated in the normal output voltage range. 
         [0092]      FIG. 10  shows a transfer function when factors such as variation in manufacturing have led to comparison by comparators  5 ,  6 , and  31  to  38  with error of +ΔVref/8. Even in such a case, ΔVout is accommodated in the normal output voltage range, namely in the range from −ΔVref to ΔVref. Therefore, malfunction originating from overflow does not occur. 
         [0093]      FIG. 11  is a block diagram showing a configuration of stage ST 2 . In  FIG. 11 , stage ST 2  includes sub ADCs  81  and  82 , multiplexers  83  and  84 , and a sub DAC  85 . Alternately activated for a prescribed period, sub ADCs  81  and  82  convert an analog signal ΔVin 1 =ΔVout provided from preceding stage ST 1  to digital signal Dout 1  of 1.5 bit and output a switch signal in accordance with the level of analog signal ΔVin. Multiplexer  83  alternately provides the switch signals generated in sub ADCs  81  and  82  to sub DAC  85 . Multiplexer  84  alternately provides digital signals Dout 1  generated in sub ADCs  81  and  82  to error correction circuit  1 . Sub DAC  85  outputs analog signal ΔVout 1  at a level in accordance with the level of analog signal ΔVin 1  and the switch signals provided from sub ADCs  81  and  82 . 
         [0094]      FIG. 12  is a circuit block diagram showing a configuration of sub ADCs  81  and  82 . In  FIG. 12 , a reference voltage generation circuit  86  is provided in common to sub ADCs  81  and  82 . Reference voltage generation circuit  86  includes eight resistance elements  86   a  connected in series. As resistance elements  86   a  have equal resistance values, reference voltage VRT−VRB is divided to generate reference voltage VC=(VRT−VRB)×5/8 and reference voltage VD=(VRT−VRB)×3/8. 
         [0095]    Sub ADC  81  includes comparators  90  and  91 , a logic gate  92 , an inverter  93 , and an encoder  94 . Comparator  90  is activated during a period in which a clock signal φA is at “H” level. Comparator  90  compares analog signal V inA+ −V inA−  provided from preceding stage ST 1  with reference voltage VC−VD=(VRT−VRB)/4. If relation of V inA+ −V inA− &gt;(VRT−VRB)/4 is satisfied, a signal φAt is set to “H” level, whereas if relation of V inA+ −V inA− &lt;(VRT−VRB)/4 is satisfied, signal φAt is set to “L” level. Here, analog signal V inA+ −V inA−  is the output signal V out+ −V out−  of preceding stage ST 1  during a period in which clock signal φA is at “H” level. 
         [0096]    Comparator  91  is activated during a period in which clock signal φA is at “H” level. Comparator  91  compares analog signal V inA+ −V inA−  provided from preceding stage ST 1  with reference voltage VD−VC=−(VRT−VRB)/4. If relation of V inA+ −V inA− &gt;−(VRT−VRB)/4 is satisfied, a signal φ 91  is set to “H” level, whereas if relation of V inA+ −V inA− &lt;−(VRT−VRB)/4 is satisfied, signal φ 91  is set to “L” level. 
         [0097]    When signals φAt and φ 91  are at “L” level and “H” level respectively, logic gate  92  sets a signal φAm to “H” level, and otherwise sets signal φAm to “L” level. Inverter  93  outputs a signal φAb which is an inverted signal of signal φ 91 . Encoder  94  outputs a digital signal Dout 1 A of 1.5 bit based on output signals φAt and φ 91  of comparators  90  and  91 . 
         [0098]    Sub ADC  82  includes comparators  95  and  96 , a logic gate  97 , an inverter  98 , and an encoder  99 . Comparator  95  is activated during a period in which a clock signal φB is at “H” level. Comparator  95  compares analog signal V inB+ −V inB−  provided from preceding stage ST 1  with reference voltage VC−VD=(VRT−VRB)/4. If relation of V inB+ −V inB− &gt;(VRT−VRB)/4 is satisfied, a signal φBt is set to “H” level, whereas if relation of V inB+ −V inB− &lt;(VRT−VRB)/4 is satisfied, signal φBt is set to “L” level. Here, analog signal V in+ −V inB−  is the output signal V out+ −V out−  of preceding stage ST 1  during a period in which clock signal φB is at “H” level. 
         [0099]    Comparator  96  is activated during a period in which clock signal φB is at “H” level. Comparator  96  compares analog signal V in+ −V inB−  provided from preceding stage ST 1  with reference voltage VD−VC=−(VRT−VRB)/4. If relation of V inB+ −V inB− &gt;−(VRT−VRB)/4 is satisfied, a signal φ 96  is set to “H” level, whereas if relation of V inB+ −V inB− &lt;−(VRT−VRB)/4 is satisfied, signal φ 96  is set to “L” level. 
         [0100]    When signals φBt and φ 96  are at “L” level and “H” level respectively, logic gate  97  sets a signal φBm to “H” level, and otherwise sets signal φBm to “L” level. Inverter  98  outputs a signal φBb which is an inverted signal of signal φ 96 . Encoder  99  outputs a digital signal Dout 1 B of 1.5 bit based on output signals φBt and φ 96  of comparators  95  and  96 . 
         [0101]      FIG. 13  is a circuit diagram showing a configuration of sub DAC  85 , and  FIG. 14  is a time chart illustrating an operation thereof. In  FIG. 13 , sub DAC  85  includes a plurality of switches of which conduction/non-conduction is controlled by signals φA, φAt, φAm, φAb, φAc, φB, φBt, φBm, φBb, and φBc, eight capacitors  101  to  108 , and a differential amplifier  109 . Capacitors  101  to  108  have equal capacitance values. 
         [0102]    In  FIG. 14 , a clock signal CLK alternately attains to “H” level and “L” level in prescribed cycles. Clock signal φA is a signal that has a cycle double the cycle of clock signal CLK and rises in response to rising of clock signal CLK. Clock signal φAc is a signal of which falling is slightly earlier than falling of clock signal φA. Clock signal φB is a signal that has a cycle double the cycle of clock signal CLK and falls in response to rising of clock signal CLK. Clock signal φBc is a signal of which falling is slightly earlier than falling of clock signal φB. 
         [0103]    When signal CLK is raised to “H” level at time t 1 , signals φA and φAc are also raised to “H” level, and switches corresponding to signals φA and φAc conduct. Thus, capacitors  101  and  103  are charged with a differential voltage between analog signal V in1+  provided from preceding stage ST 1  and reference voltage VCM. 
         [0104]    Capacitors  102  and  104  are charged with a differential voltage between analog signal V in1−  provided from preceding stage ST 1  and reference voltage VCM. Meanwhile, one terminals of capacitors  105  and  107  are both connected to an + input terminal of differential amplifier  109 , and the other terminal of capacitor  107  is connected to an − output terminal of differential amplifier  109 . When any one signal out of output signals φAt, φAm and φAb of sub ADC  81  attains to “H” level and the switches corresponding to the signal conduct (this state is shown with * 2  in  FIG. 14 ), the other terminal of capacitor  105  is supplied with voltage VRT, VCM or VRB through the conducting switch. 
         [0105]    One terminals of capacitors  106  and  108  are both connected to an − input terminal of differential amplifier  109 , and the other terminal of capacitor  108  is connected to an + output terminal of differential amplifier  109 . In addition, when any one signal out of output signals φAt, φAm and φAb of sub ADC  81  attains to “H” level and the switches corresponding to the signal conduct (this state is shown with * 2  in  FIG. 14 ), the other terminal of capacitor  106  is supplied with voltage VRB, VCM or VRT through the conducting switch. Thus, in synchronization with the rising edge of clock signal CLK, analog signals V out1+ , V out−  at a level in accordance with the output digital signal of sub ADC  81  are output from the − output terminal and the + output terminal of differential amplifier  109 . Here, analog signals V in1+ , V in1−  are the output signals V out+ , V out−  of preceding stage ST 1 . 
         [0106]    When signal CLK is raised to “H” level at time t 2 , signals φB and φBc are also raised to “H” level, and switches corresponding to signals φB and φBc conduct. Thus, capacitors  105  and  107  are charged with the differential voltage between signal V in1+  provided from preceding stage ST 1  and reference voltage VCM. 
         [0107]    Capacitors  106  and  108  are charged with the differential voltage between analog signal V in1−  provided from preceding stage ST 1  and reference voltage VCM. Meanwhile, one terminals of capacitors  101  and  103  are both connected to the + input terminal of differential amplifier  109 , and the other terminal of capacitor  103  is connected to the − output terminal of differential amplifier  109 . When any one signal out of output signals φBt, φBm and φBb of sub ADC  82  attains to “H” level and the switches corresponding to the signal conduct (this state is shown with * 1  in  FIG. 14 ), the other terminal of capacitor  101  is supplied with voltage VRT, VCM or VRB through the conducting switch. 
         [0108]    One terminals of capacitors  102  and  104  are both connected to the − input terminal of differential amplifier  109 , and the other terminal of capacitor  104  is connected to the + output terminal of differential amplifier  109 . In addition, when any one signal out of output signals φBt, φBm and φBb of sub ADC  82  attains to “H” level and the switches corresponding to the signal conduct (this state is shown with * 1  in  FIG. 14 ), the other terminal of capacitor  102  is supplied with voltage VRB, VCM or VRT through the conducting switch. Thus, in synchronization with the rising edge of clock signal CLK, analog signals V out1+ , V out1−  at a level in accordance with the output digital signal of sub ADC  82  are output from the − output terminal and the + output terminal of differential amplifier  109 . 
         [0109]    Here, V in1+ −V in1−  is denoted as ΔVin 1 , V out1+ −V out1−  is denoted as ΔVy 1 , and VRT−VRB is denoted as ΔVref. If φBt=H and φBm=φBb=L when φA=L and φB=H, relation of ΔVy 1 =2ΔVin 1 −ΔVref is satisfied. In addition, if φBm=H and φBt=φBb=L when φA=L and φB=H, relation of ΔVy 1 =2ΔVin 1  is satisfied. Moreover, if Bb=H and φBt=φBb=L when φA=L and φB=H, relation of ΔVy 1 =2ΔVin 1 +ΔVref is satisfied. 
         [0110]      FIG. 15  illustrates a transfer function of stage ST 2 . In  FIG. 15 , the abscissa represents ΔVin 1 =V in1+ −V in1−  and the ordinate represents ΔVout 1 =V out1+ −V out1− . In a section 0&lt;ΔVin 1 &lt;ΔVref/4, relation of ΔVout 1 =ΔVin×2 is satisfied. In a section ΔVref/4&lt;ΔVin 1 , relation of ΔVout 1 =ΔVin 1 ×2−ΔVref is satisfied. In this section, ΔVout 1  increases in proportion to ΔVin 1  and reaches power supply voltage Vdd. In a section 0&gt;ΔVin 1 &gt;−ΔVref/4, relation of ΔVout 1 =ΔVin×2 is satisfied. In a section −ΔVref/4&gt;ΔVin 1 , relation of ΔVout 1 =ΔVin 1 ×2+ΔVref is satisfied. In this section, ΔVout 1  decreases with decrease in ΔVin 1  and reaches power supply voltage −Vdd. 
         [0111]    Thus, when viewed in a direction from 0 to ΔVref, a curve representing the transfer function makes a turn from the positive side toward the negative side when ΔVin 1  attains to ΔVref/4. Meanwhile, when viewed in a direction from 0 to −ΔVref, the curve representing the transfer function makes a turn from the negative side toward the positive side when ΔVin 1  attains to −ΔVref/4. ΔVref/4 and −ΔVref/4 correspond to comparators  90 ,  91  or  95 ,  96 . As shown in  FIGS. 9 and 10 , as ΔVout, i.e., ΔVin 1 , does not exceed the range from −ΔVref to ΔVref, ΔVout 1  does not exceed the range from −ΔVref to ΔVref 
         [0112]      FIG. 16  is a circuit block diagram showing a variation of the first embodiment, to be compared with  FIG. 4 . In  FIG. 16 , in this variation, comparator  5  further includes switches  111  to  114  and capacitors  115  and  116 . One terminals of switches  111  to  114  receive voltage signals V in+ , VRT, VRB, and V in− , respectively. The other terminals of switches  111  and  112  are both connected to one terminal of capacitor  115 . The other terminals of switches  113  and  114  are both connected to one terminal of capacitor  116 . The other terminals of capacitors  115  and  116  are connected to the + input terminal and the − input terminal of differential amplifier  27 , respectively. Switches  112  and  113  conduct during a period in which clock signal φ 2  is at “H” level (clock signal /φ 2  is at “L” level). Switches  111  and  114  conduct during a period in which clock signal /φ 2  is at “H” level (clock signal φ 2  is at “L” level). 
         [0113]    Here, assuming that the voltage at the + output terminal and the voltage at the − output terminal of differential amplifier  27  are denoted as Vy 1  and Vy 2  respectively and an amplification ratio is denoted as A, relation of Vy 1 −Vy 2 =A[2(V in+ −V in− )−{2(VRT−VRB)+(VA−VB)}]/3 is satisfied. Therefore, a difference between 2(V in+ −V in− )/3 and 2{(VRT−VRB)+(VA−VB)}/3 is amplified by differential amplifier  27 , and attains to “H” level or “L” level. 
         [0114]    The result of comparison the same as in  FIG. 4  can also be obtained with this configuration. Here, comparator  5  in  FIG. 4  compares (V in+ −V in− )/2 with {(VRT−VRB)+(VA−VB)}/2, whereas comparator  5  in  FIG. 16  compares 2(V in+ −V in− )/3 with {2(VRT−VRB)+(VRT−VRB)+(VA−VB)}/3. Namely, comparator  5  in  FIG. 4  performs comparison by multiplying (V in+ −V in− ) by ½, whereas comparator  5  in  FIG. 16  performs comparison by multiplying (V in+ −V in− ) by ⅔. Therefore, results of comparison more accurate can be obtained with comparator  5  in  FIG. 16  than with comparator  5  in  FIG. 4 . 
         [0115]    Comparator  6  may be configured similarly to comparator  5 . Here, one terminals of switches  12 ,  14 ,  112 ,  113 ,  15 , and  17  receive reference voltages VB, VRB, VRB, VRT, VRT, and VA, instead of reference voltages VA, VRT, VRT, VRB, VRB, and VB. 
       Second Embodiment 
       [0116]      FIG. 17  is a block diagram showing a configuration of a pipeline A/D converter according to a second embodiment of the present invention. In  FIG. 17 , the pipeline, A/D converter includes five stages ST 1 , ST 23 , ST 45 , ST 67 , and ST 8  that are cascaded, and error correction circuit  1 . 
         [0117]    First stage ST 1  receives analog signal Vin to be A/D converted. Stage ST 1  generates digital signal Dout of 3.25 bits based on input analog signal Vin, and provides generated digital signal Dout to error correction circuit  1 . In addition, stage ST 1  generates analog signal ΔVout at a level in accordance with input analog signal Vin and generated digital signal Dout, and provides generated analog signal ΔVout to next stage ST 23 . Moreover, stage ST 1  includes an overflow prevention circuit maintaining the level of analog signal ΔVout within a normal output voltage range even if the level of input analog signal Vin exceeds a prescribed input voltage range. Stage ST 1  has the configuration the same as in the first embodiment. 
         [0118]    Second stage ST 23  generates digital signal Dout 1  of 1.5 bit based on analog signal ΔVout from preceding stage ST 1  and provides generated digital signal Dout 1  to error correction circuit  1 . In addition, stage ST 23  generates analog signal ΔVout 1  at a level in accordance with input analog signal ΔVout and generated digital signal Dout 1 , generates a digital signal Dout 2  of 1.5 bit based on generated analog signal ΔVout 1 , and provides generated digital signal Dout 2  to error correction circuit  1 . Moreover, stage ST 23  generates an analog signal ΔVout 2  based on generated analog signal ΔVout 1  and generated digital signal Dout 2 , and provides generated analog signal ΔVout 2  to next stage ST 45 . Stage ST 23  adopts what is called a vertical shared amplifier configuration, and attains a function of stages ST 2  and ST 3  in  FIG. 1 . Each of stages ST 45  and ST 67  is configured similarly to stage ST 23 . 
         [0119]    Last stage ST 8  includes a comparator, generates digital signal Dout 7  of 2 bits based on analog signal ΔVout 6  from preceding stage ST 67 , and provides generated digital signal Dout 7  to error correction circuit  1 . Error correction circuit  1  outputs last digital signal DOUT based on digital signals Dout to Dout 7  output from stages ST 1 , ST 23 , ST 45 , ST 67 , and ST 8 . 
         [0120]      FIG. 18  is a block diagram showing a configuration of stage ST 23 . In  FIG. 18 , stage ST 23  includes sub ADCs  121  and  122 , multiplexers  123  and  124 , and a sub DAC  125 . Sub ADCs  121  and  122  are alternately activated for a prescribed period. Sub ADC  121  converts analog signal ΔVin=ΔVout provided from preceding stage ST 1  to digital signal Dout 1  of 1.5 bit and outputs a switch signal at a level in accordance with analog signal Vin. 
         [0121]    Sub ADC  122  converts analog signal ΔVout 1  provided from sub DAC  125  to digital signal Dout 2  of 1.5 bit and outputs a switch signal at a level in accordance with analog signal ΔVout 1 . Multiplexer  123  alternately provides the switch signals generated in sub ADCs  121  and  122  to sub DAC  125 . Multiplexer  124  alternately provides digital signals Dout 1  and Dout 2  generated in sub ADCs  121  and  122  to error correction circuit  1 . Sub DAC  125  outputs analog signals Vout 1  and Vout 2  at a level in accordance with analog signals ΔVin 1  and ΔVout 1  and the switch signals provided from sub ADCs  121  and  122 . 
         [0122]      FIG. 19  is a circuit diagram showing a configuration of sub DAC  125 , and  FIG. 20  is a time chart illustrating an operation thereof. In  FIG. 19 , sub DAC  125  includes a plurality of switches of which conduction/non-conduction is controlled by signals φA, φAt, φAm, φAb, φAc, φB, φBt, φBm, φBb, and φBc, eight capacitors  101  to  108 , and differential amplifier  109 . Capacitors  101  to  108  have equal capacitance values. 
         [0123]    In  FIG. 20 , clock signal CLK alternately attains to “H” level and “L” level in prescribed cycles. Clock signal φA is a signal that has a cycle the same as that of clock signal CLK and rises in response to rising of clock signal CLK. Clock signal φAc is a signal of which falling is slightly earlier than falling of clock signal φA. Clock signal φB is a signal that has a cycle the same as that of clock signal CLK and falls in response to rising of clock signal CLK. Clock signal φBc is a signal of which falling is slightly earlier than falling of clock signal φB. 
         [0124]    When signal CLK is raised to “H” level at time t 1 , signals φA and φAc are also raised to “H” level, and switches corresponding to signals φA and φAc conduct. Thus, capacitors  101  and  103  are charged with the differential voltage between analog signal V in1+  provided from preceding stage ST 1  and reference voltage VCM. 
         [0125]    Capacitors  102  and  104  are charged with the differential voltage between analog signal V in1−  provided from preceding stage ST 1  and reference voltage VCM. Meanwhile, one terminals of capacitors  105  and  107  are both connected to the + input terminal of differential amplifier  109 , and the other terminal of capacitor  107  is connected to the − output terminal of differential amplifier  109 . When any one signal out of output signals φAt, φAm and φAb of sub ADC  121  attains to “H” level and the switches corresponding to the signal conduct (this state is shown with * 2  in  FIG. 20 ), the other terminal of capacitor  105  is supplied with voltage VRT, VCM or VRB through the conducting switch. 
         [0126]    One terminals of capacitors  106  and  108  are both connected to the − input terminal of differential amplifier  109 , and the other terminal of capacitor  108  is connected to the + output terminal of differential amplifier  109 . In addition, when any one signal out of output signals φAt, φAm and φAb of sub ADC  121  attains to “H” level and the switches corresponding to the signal conduct (this state is shown with * 2  in  FIG. 20 ), the other terminal of capacitor  106  is supplied with voltage VRB, VCM or VRT through the conducting switch. Thus, in synchronization with clock signal CLK, analog signals V out1+ , V out1−  at a level in accordance with the output digital signal of sub ADC  121  are output from the − output terminal and the + output terminal of differential amplifier  109 . Here, analog signals V in1+ , V in1−  are the output signals V out+ , V out−  of preceding stage ST 1 . 
         [0127]    When signal CLK falls to “L” level at time t 2 , signals φB and φBc are raised to “H” level, and switches corresponding to signals φB and φBc conduct. Thus, capacitors  105  and  107  are charged with a voltage which is the difference from reference voltage VCM. 
         [0128]    Capacitors  106  and  108  are charged with a differential voltage between analog signal V out1−  provided from differential amplifier  109  and reference voltage VCM. Meanwhile, one terminals of capacitors  101  and  103  are both connected to the + input terminal of differential amplifier  109 , and the other terminal of capacitor  103  is connected to the − output terminal of differential amplifier  109 . When any one signal out of output signals φBt, φBm and φBb of sub ADC  122  attains to “H” level and the switches corresponding to the signal conduct (this state is shown with * 1  in  FIG. 20 ), the other terminal of capacitor  101  is supplied with voltage VRT, VCM or VRB through the conducting switch. 
         [0129]    One terminals of capacitors  102  and  104  are both connected to the − input terminal of differential amplifier  109 , and the other terminal of capacitor  104  is connected to the + output terminal of differential amplifier  109 . In addition, when any one signal out of output signals φBt, φBm and φBb of sub ADC  122  attains to “H” level and the switches corresponding to the signal conduct (this state is shown with * 1  in  FIG. 20 ), the other terminal of capacitor  102  is supplied with voltage VRB, VCM or VRT through the conducting switch. Thus, in synchronization with clock signal CLK, analog signals V out2+ , V out2−  at a level in accordance with the output digital signal of sub ADC  122  are output from the − output terminal and the + output terminal of differential amplifier  109 . As the configuration and the operation are otherwise the same as in the first embodiment, description thereof will not be repeated. 
         [0130]    The second embodiment can also attain the effect the same as in the first embodiment. 
       Third Embodiment 
       [0131]      FIG. 21  is a block diagram showing a configuration of a pipeline A/D converter according to a third embodiment of the present invention. In  FIG. 21 , the pipeline A/D converter is different from the pipeline A/D converter in  FIG. 1  in that first stage ST 1  adapted to 3.25 bits is replaced with a first stage ST 11  adapted to 2.5 bits. 
         [0132]    First stage ST 11  receives analog signal ΔVin to be A/D converted. Stage ST 11  generates digital signal Dout of 2.5 bits (any one of 000 to 100) based on input analog signal ΔVin, and provides generated digital signal Dout to error correction circuit  1 . In addition, stage ST 11  generates analog signal ΔVout at a level in accordance with input analog signal ΔVin and generated digital signal Dout, and provides generated analog signal ΔVout to next stage ST 2 . Moreover, stage ST 11  includes an overflow prevention circuit maintaining analog signal ΔVout within a normal voltage output range even if the level of input analog signal Vin exceeds a prescribed input voltage range. 
         [0133]    Second stage ST 2  generates digital signal Dout 1  of 1.5 bit based on analog signal ΔVout from preceding stage ST 11  and provides generated digital signal Dout 1  to error correction circuit  1 . In addition, stage ST 2  generates analog signal ΔVout 1  at a level in accordance with input analog signal ΔVout and generated digital signal Dout 1 , and provides generated analog signal ΔVout 1  to next stage ST 3 . Stage ST 2  adopts what is called a lateral shared amplifier configuration. Each of third to seventh stages ST 3  to ST 7  is configured similarly to stage ST 2 . 
         [0134]    Last stage ST 8  includes a comparator, generates digital signal Dout 7  of 2 bits based on analog signal ΔVout 6  from preceding stage ST 7 , and provides generated digital signal Dout 7  to error correction circuit  1 . Error correction circuit  1  outputs last digital signal DOUT based on digital signals Dout to Dout 7  output from stages ST 1  to ST 8 . 
         [0135]      FIG. 22  is a block diagram showing a configuration of first stage ST 11 . In  FIG. 22 , stage ST 11  includes an overflow detection circuit  131 , a sub ADC  132 , and a sub DAC  133 . When the level of input analog signal ΔVin exceeds a prescribed range, overflow detection circuit  131  sets signal φ 7  to “H” level representing an activation level. Sub ADC  132  converts input analog signal ΔVin to digital signal Dout of 2.5 bits and provides the digital signal to error correction circuit  1 , as well as provides a switch signal in accordance with digital signal Dout to sub DAC  133 . Sub DAC  133  generates analog signal ΔVout based on input analog signal ΔVin and the switch signal from sub ADC  132 , and provides generated analog signal ΔVout to next stage ST 2 . In addition, when signal φ 7  is set to “H” level, sub DAC  133  sets analog signal ΔVout to 0 level. 
         [0136]      FIG. 23  is a circuit block diagram showing a configuration of overflow detection circuit  131 . In  FIG. 23 , overflow detection circuit  131  includes comparators  5  and  6 , OR gate  7 , inverter  7   a , and a reference voltage generation circuit  134 . Reference voltage generation circuit  134  includes eight resistance elements  134   a  connected in series. As these resistance elements  134   a  have equal resistance values, reference voltage VRT−VRB is divided to generate reference voltages VA=(VRT−VRB)×5/8, VB=(VRT−VRB)×3/8, and VCM=(VRT−VRB)/2. 
         [0137]    Comparator  5  compares input analog signal V in+ −V in−  with reference voltage VRT−VRB+VA−VB=(VRT−VRB)×5/4, which represents the upper limit. If relation of V in+ −V in− &gt;(VRT−VRB)×5/4 is satisfied, signal φ 5  is set to “H” level, whereas if relation of V in+ −V in− &lt;(VRT−VRB)×5/4 is satisfied, signal φ 5  is set to “L” level. 
         [0138]    Comparator  6  compares input analog signal V in+ −V in−  with reference voltage VRB−VRT+VB−VA=(VRB−VRT)×5/4, which represents the lower limit. If relation of V in+ −V in− &lt;(VRB−VRT)×5/4 is satisfied, signal φ 6  is set to “H” level, whereas if relation of V in+ −V in− &gt;(VRB−VRT)×5/4 is satisfied, signal φ 6  is set to “L” level. 
         [0139]    Inverter  7   a  receives output signal φ 6  from comparator  6 , and outputs inverted signal /φ 6  thereof. OR gate  7  receives output signal φ 5  of comparator  5 , output signal /φ 6  of inverter  7   a  and clock signal φ 1   c , and outputs signal φ 7 . When at least one of signals φ 5 , /φ 6 , and φ 1   c  attains to “H” level, signal φ 7  is set to “H” level. 
         [0140]      FIG. 24  is a circuit block diagram showing a configuration of sub ADC  132 . In  FIG. 24 , sub ADC  132  includes a reference voltage generation circuit  140 , comparators  141  to  144 , a buffer  145 , logic gates  146  to  148 , an inverter  149 , and an encoder  150 . Reference voltage generation circuit  140  includes eight resistance elements  140   a  connected in series. Reference voltage generation circuit  140  divides reference voltage VRT−VRB=ΔVref to generate reference voltages V 1  to V 4 . Eight resistance elements  140   a  have equal resistance values. 
         [0141]    Comparators  141  to  144  are activated while clock signal φ 2  is at “H” level. Comparator  141  compares input analog signal V in+ −V in−  with reference voltage V 1 −V 4 =ΔVref×3/4. If relation of V in+ −V in− &gt;ΔVref×3/4 is satisfied, a signal φ 141  is set to “H” level, whereas if relation of V in+ −V in− &lt;ΔVref×3/4 is satisfied, signal φ 141  is set to “L” level. Comparator  142  compares input analog signal V in+ −V in−  with reference voltage V 2 −V 3 =ΔVref/4. If relation of V in+ −V in− &gt;ΔVref/4 is satisfied, a signal φ 142  is set to “H” level, whereas if relation of V in+ −V in− &lt;ΔVref/4 is satisfied, signal φ 142  is set to “L” level. 
         [0142]    Comparator  143  compares input analog signal V in+ −V in−  with reference voltage V 3 −V 2 =−ΔVref/4. If relation of V in+ −V in− &gt;−ΔVref/4 is satisfied, a signal φ 143  is set to “H” level, whereas if relation of V in+ −V in− &lt;−ΔVref/4 is satisfied, signal φ 143  is set to “L” level. Comparator  144  compares input analog signal V in+ −V in−  with reference voltage V 4 −V 1 =−ΔVref×3/4. If relation of V in+ −V in− &gt;−ΔVref×3/4 is satisfied, a signal φ 144  is set to “H” level, whereas if relation of V in+ −V in− &lt;−ΔVref×3/4 is satisfied, signal φ 144  is set to “L” level. When clock signal φ 2  is at “L” level, output signals φ 141  to φ 144  of comparators  141  to  144  are fixed to “L” level. 
         [0143]    Buffer  145  delays signal φ 141  and outputs the resultant signal as signal φ 2   a . When signal φ 141  attains to “L” level and signal φ 142  attains to “H” level, logic gate  146  sets signal φ 2   b  to “H” level. When signal φ 142  attains to “L” level and signal φ 143  attains to “H” level, logic gate  147  sets signal φ 2   c  to “H” level. When signal φ 143  attains to “L” level and signal φ 144  attains to “H” level, logic gate  148  sets signal φ 2   d  to “H” level. Inverter  149  inverts signal φ 144  and outputs the inverted signal as signal φ 2   e . Encoder  150  generates digital signal Dout of 2.5 bits based on output signals φ 141  to φ 144  of comparators  141  to  144 , and outputs generated digital signal Dout to error correction circuit  1 . 
         [0144]      FIG. 25  is a circuit diagram showing a configuration of sub DAC  133 . In  FIG. 25 , sub DAC  133  includes switches  151  to  159 , four capacitors  160  to  163 , and a differential amplifier  164 . Capacitors  160  to  163  have equal capacitance values. 
         [0145]    Switch  151  has six switch terminals and one common terminal, and it is controlled by signals φ 1  and φ 2   a  to φ 2   e . Six switch terminals of switch  151  receive voltage signals V in+ , VRT 2 , VRT, VCM, VRB, and VRB 2  respectively, the common terminal thereof is connected to one terminal of capacitor  160 , and the other terminal of capacitor  160  is connected to a + input terminal of differential amplifier  164 . Here, relation of VRT 2 =VCM+VRT−VRB and VRB 2 =VCM+VRB−VRT is satisfied. Therefore, relation of VRT 2 −VRB 2 =2(VRT−VRB)=2ΔVref is satisfied. When signals φ 1  and φ 2   a  to φ 2   e  are set to “H” level, voltage signals V in+ , VRT 2 , VRT, VCM, VRB, and VRB 2  are provided to one terminal of capacitor  160  through the common terminal. 
         [0146]    Switch  152  has six switch terminals and one common terminal, and it is controlled by signals φ 1  and φ 2   a  to φ 2   e . Six switch terminals of switch  152  receive voltage signals V in− , VRT 2 , VRT, VCM, VRB, and VRB 2  respectively, the common terminal thereof is connected to one terminal of capacitor  162 , and the other terminal of capacitor  162  is connected to a − input terminal of differential amplifier  164 . When signals φ 1  and φ 2   a  to φ 2   e  are set to “H” level, voltage signals V in− , VRB 2 , VRB, VCM, VRT, and VRT 2  are provided to one terminal of capacitor  162  through the common terminal. 
         [0147]    One terminal of switch  153  receives analog signal V in+ , and switch  153  has the other terminal connected to one terminal of capacitor  161 . Capacitor  161  has the other terminal connected to the + input terminal of differential amplifier  164 . Switch  155  is connected between one terminal of capacitor  161  and an − output terminal of differential amplifier  164 . One terminal of switch  154  receives analog signal V in− , and switch  154  has the other terminal connected to one terminal of capacitor  163 . Capacitor  163  has the other terminal connected to the − input terminal of differential amplifier  164 . Switch  156  is connected between one terminal of capacitor  163  and an + output terminal of differential amplifier  164 . One terminals of switches  157  and  158  both receive reference voltage VCM, and switches  157  and  158  have the other terminals connected to the + input terminal and the − input terminal of differential amplifier  164  respectively. Switch  159  is connected between the + output terminal and the − output terminal of differential amplifier  164 . Switches  153  and  154  conduct during a period in which clock signal φ 1  is at “H” level, switches  155  and  156  conduct during a period in which clock signal φ 2  is at “H” level, and switches  157  to  159  conduct during a period in which clock signal φ 7  is at “H” level. Analog voltage signals V out+ , V out−  are output from the − output terminal and the + output terminal of differential amplifier  164  respectively. 
         [0148]    Here, V in+ −V in−  is denoted as ΔVin, V out+ −V out−  is denoted as ΔVy, and VRT−VRB is denoted as ΔVref. If only φ 2   a  out of φ 2   a  to φ 2   e  is at “H” level, relation of ΔVy=2ΔVin−2ΔVref is satisfied. Meanwhile, if only φ 2   b  out of φ 2   a  to φ 2   e  is at “H” level, relation of ΔVy=2ΔVin−ΔVref is satisfied. In addition, if only φ 2   c  out of φ 2   a  to φ 2   e  is at “H” level, relation of ΔVy=2ΔVin is satisfied. Moreover, if only φ 2   d  out of φ 2   a  to φ 2   e  is at “H” level, relation of ΔVy=2ΔVin+ΔVref is satisfied. Further, if only φ 2   e  out of φ 2   a  to φ 2   e  is at “H” level, relation of ΔVy=2ΔVin+2ΔVref is satisfied. 
         [0149]      FIG. 26  is a time chart illustrating an operation of sub DAC  133 . In  FIG. 26 , clock signal φ 1  is set to “H” level from time t 1  to t 2 , from t 3  to t 4 , from t 5  to t 6 , from t 7  to t 8 , and so on, and set to “L” level from time t 2  to t 3 , from t 4  to t 5 , from t 6  to t 7 , from t 8  to t 9 , and so on. Clock signal φ 1   c  is a signal of which falling is earlier by a prescribed period than falling of clock signal φ 1 . Signal φ 7  is an output signal of overflow detection circuit  131 . Signals φ 2   a  to φ 2   e  are output signals of sub ADC  132 . 
         [0150]    When signal φ 1  is raised to “H” level at time t 1 , signals φ 1   c  and φ 7  are also raised to “H” level. Thus, capacitors  160  and  161  are charged with the differential voltage between signal V in+  and reference voltage VCM, and capacitors  162  and  163  are charged with the differential voltage between signal V in−  and reference voltage VCM. Then, when signal φ 1  falls to “L” level at time t 2 , switches  153  and  154  become non-conducting. In addition, signal φ 2  is raised to “H” level, and switches  155  and  156  conduct. 
         [0151]    Here, it is assumed that input signal V in+ −V in−  overflows to the positive side. Then, even when signal φ 1   c  attains to “L” level, signal φ 7  is maintained at “H” level, signal φ 2   a  attains to “H” level, and signals /φ 2   b  to /φ 2   e  attain to “L” level. Thus, though reference voltages VRT 2  and VRB 2  are applied to one terminals of capacitors  160  and  162 , switches  157  to  159  conduct. Therefore, output voltage V out+ −V out−  of differential amplifier  157  is set to 0V. 
         [0152]    When signal φ 1  is raised to “H” level at time t 3 , signal φ 1   c  is also raised to “H” level. Thus, capacitors  160  and  161  are charged with the differential voltage between signal V in+  and reference voltage VCM, and capacitors  162  and  163  are charged with the differential voltage between signal V in−  and reference voltage VCM. Then, when signal φ 1  falls to “L” level at time t 4 , switches  153  and  154  become non-conducting. In addition, signal φ 2  is raised to “H” level, and switches  155  and  156  conduct. 
         [0153]    Here, it is assumed that overflow of input signal V in+ −V in−  does not occur. Then, when signal φ 1   c  attains to “L” level, signal φ 7  falls to “L” level, any one of signals φ 2   b  to φ 2   e  attains to “H” level in accordance with the level of input signal V in+ −V in− , and remaining signals attain to “L” level (this state is shown with * 1  in  FIG. 26 ). Thus, switches  157  to  159  become non-conducting, and a voltage corresponding to the signal at “H” level out of signals φ 2   b  to φ 2   d  is applied to one terminals of capacitors  160  and  162 . Thus, voltage V out+ −V out−  at a level in accordance with the level of input signal V in+ −V in−  is output. 
         [0154]    When signal φ 1  is raised to “H” level at time t 7 , signals φ 1   c  and φ 7  are also raised to “H” level. Thus, capacitors  160  and  161  are charged with the differential voltage between signal V in+  and reference voltage VCM, and capacitors  162  and  163  are charged with the differential voltage between signal V in−  and reference voltage VCM. Then, when signal φ 1  falls to “L” level at time t 8 , switches  153  and  154  become non-conducting. In addition, signal φ 2  is raised to “H” level, and switches  155  and  156  conduct. 
         [0155]    Here, it is assumed that input signal V in+ −V in−  overflows to the negative side. Then, even when signal φ 1   c  attains to “L” level, signal φ 7  is maintained at “H” level, signal φ 2   e  attains to “H” level, and signals φ 2   a  to φ 2   d  attain to “L” level. Thus, though reference voltages VRB 2  and VRT 2  are applied to one terminals of capacitors  160  and  162 , switches  157  to  159  conduct. Therefore, output voltage V out+ −V out−  of differential amplifier  157  is set to 0V. 
         [0156]      FIG. 27  illustrates a transfer function of stage ST 11 . In  FIG. 27 , the abscissa represents ΔVin=V in+ −V in−  and the ordinate represents ΔVout=V out+ −V out− . In a section 0&lt;ΔVin&lt;ΔVref/4, relation of ΔVout=ΔVin×2 is satisfied. In a section ΔVref/4&lt;ΔVin&lt;ΔVref×3/4, relation of ΔVout=ΔVin×2−ΔVref is satisfied. In a section ΔVref×3/4&lt;ΔVin&lt;ΔVref×5/4, relation of ΔVout=ΔVin×2−ΔVref×2 is satisfied. In a section ΔVref×5/4&lt;ΔVin, relation of ΔVout=0 is satisfied. 
         [0157]    Thus, a curve representing the transfer function makes a turn from the positive side toward the negative side when ΔVin attains to ΔVref/4, ΔVref×3/4, and ΔVref×5/4. ΔVref/4 and ΔVref×3/4 correspond to comparators  142  and  141  respectively, and ΔVref×5/4 corresponds to comparator  5 . 
         [0158]    In a section 0&gt;ΔVin&gt;−ΔVref/4, relation of ΔVout=ΔVin×2 is satisfied. In a section −ΔVref/4&gt;ΔVin&gt;−ΔVref×3/4, relation of ΔVout=ΔVin×2+ΔVref is satisfied. In a section −ΔVref×3/4&gt;ΔVin&gt;−ΔVref×5/4, relation of ΔVout=ΔVin×2+ΔVref×2 is satisfied. In a section −ΔVref×5/4&gt;ΔVin, relation of ΔVout=0 is satisfied. 
         [0159]    Thus, when viewed in a direction from 0 to −ΔVref, a curve representing the transfer function makes a turn from the negative side toward the positive side when ΔVin attains to −ΔVref/4, −ΔVref×3/4, and −ΔVref×5/4−ΔVref/4 and −ΔVref×3/4 correspond to comparators  143  and  144  respectively, and −ΔVref×5/4 corresponds to comparator  6 . 
         [0160]    A dotted line in  FIG. 27  represents the transfer function of the first stage in the conventional pipeline A/D converter. In the conventional first stage, the digital signal of 1.5 bit has been generated using −ΔVref/4 and ΔVref/4 as reference voltages. The transfer function of the conventional first stage is the same as the transfer function of stage ST 11  according to the second embodiment in the section 0&lt;ΔVin&lt;ΔVref×3/4, however, if ΔVin is higher than ΔVref×3/4, ΔVout increases in proportion to ΔVin and reaches power supply voltage Vdd. Meanwhile, the transfer function of the conventional first stage is the same as the transfer function of stage ST 11  according to the second embodiment in the section 0&gt;ΔVin&gt;−ΔVref×3/4, however, if ΔVin is lower than −ΔVref×3/4, ΔVout decreases in proportion to ΔVin and reaches power supply voltage −Vdd. In other words, with the conventional first stage, if ΔVin is higher than ΔVref×3/4 or lower than −ΔVref×3/4, ΔVout exceeds the normal output voltage range. 
         [0161]    In contrast, with stage ST 11  according to the third embodiment, two more turning points of the transfer function are provided on each of the positive side and the negative side. In addition, if ΔVin is higher than ΔVref×5/4 or lower than −ΔVref×5/4, output voltage ΔVout is set to 0V. Therefore, ΔVout is always accommodated in the normal output voltage range. 
         [0162]      FIG. 28  shows a transfer function when factors such as variation in manufacturing have led to comparison by comparators  5 ,  6 , and  141  to  144  with error of +ΔVref/4. Even in such a case, ΔVout is accommodated in the normal output voltage range, namely from −ΔVref to ΔVref. Therefore, malfunction originating from overflow does not occur. 
         [0163]    Here, as shown in  FIG. 29 , stages ST 2  to ST 7  may naturally be replaced with stages ST 23 , ST 45  and ST 67  adopting the lateral shared amplifier configuration. 
         [0164]    Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.