Abstract:
An apparatus includes a first set of circuits adapted to operate in a first mode of operation of the apparatus. The apparatus further includes a second set of circuits adapted to operate in a second mode of operation of the apparatus, where a power consumption of the apparatus is lower in the second mode of operation of the apparatus than in the first mode of operation of the apparatus. The apparatus also includes a charge pump adapted to convert a first supply voltage of the apparatus to a second supply voltage, and the second supply voltage powers the second set of circuits.

Description:
TECHNICAL FIELD 
     The disclosure relates generally to power converter apparatus and related methods. More particularly, the disclosure relates to charge pumps for providing supply voltages to low power apparatus, and associated methods. 
     BACKGROUND 
     Modern ICs have helped to integrate electronic circuitry to decrease size and cost. As a consequence, modern ICs can form complex circuitry and systems. For example, virtually all of the functionality of a system may be realized using one or a handful of ICs. Such circuitry and systems may receive and operate on both analog and digital signals, and may provide analog and digital signals. 
     The result has been a growing trend to produce circuitry and systems with increased numbers of transistors and similar devices. The growth in the number of devices usually leads to an increase in power consumption or power dissipation. Even for a device with a relatively modest number of devices, the power consumption may place a drain on the power source. 
     SUMMARY 
     An apparatus according to one exemplary embodiment includes a first set of circuits adapted to operate in a first mode of operation of the apparatus. The apparatus further includes a second set of circuits adapted to operate in a second mode of operation of the apparatus, where a power consumption of the apparatus is lower in the second mode of operation of the apparatus than in the first mode of operation of the apparatus. The apparatus also includes a charge pump adapted to convert a first supply voltage of the apparatus to a second supply voltage, and the second supply voltage powers the second set of circuits. 
     According to another exemplary embodiment, an apparatus includes a battery, and a microcontroller unit (MCU). The MCU includes a charge pump coupled to the battery. The charge pump is adapted to convert a voltage of the battery to a supply voltage. The supply voltage is lower than the battery voltage. The MCU also includes a first set of circuits adapted to be powered by the battery during a normal operating mode of the MCU. The MCU further includes a second set of circuits coupled to the charge pump. The second set of circuits is adapted to be powered by the supply voltage during a low-power operating mode of the MCU 
     According to yet another exemplary embodiment, a method of operating an apparatus includes converting, by using a charge pump, a first supply voltage of the apparatus to a second supply voltage. The method also includes operating a first set of circuits in a first mode of operation of the apparatus. The method further includes operating a second set of circuits in a second mode of operation of the apparatus, using the second supply voltage to power the second set of circuits, where the power consumption of the apparatus is lower in the second mode of operation of the apparatus than in the first mode of operation of the apparatus. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The appended drawings illustrate only exemplary embodiments and therefore should not be considered as limiting its scope. Persons of ordinary skill in the art appreciate that the disclosed concepts lend themselves to other equally effective embodiments. In the drawings, the same numeral designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks. 
         FIG. 1  illustrates an apparatus that includes a charge pump for supplying power to a set of circuits according to an exemplary embodiment. 
         FIGS. 2A-2B  show more detailed block diagrams of apparatus according to exemplary embodiments. 
         FIG. 3  shows a circuit arrangement for a charge pump for use in exemplary embodiments. 
         FIG. 4  depicts an exemplary set of switch control signals for the charge pump of  FIG. 3 . 
         FIG. 5  illustrates an equivalent circuit diagram for the charge pump of  FIG. 3  during one phase of operation. 
         FIG. 6  depicts an equivalent circuit diagram for the charge pump of  FIG. 3  during another phase of operation. 
         FIG. 7  shows a Thévenin equivalent circuit diagram for the charge pump of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     In various embodiments an apparatus may be provided to provide power to circuitry operating in a relatively low power mode, yet in an efficient manner. More specifically, the disclosure relates to apparatus and methods for using charge pumps to supply power to circuitry that is operational in a low power mode, such as a sleep mode, with relatively high efficiency. 
       FIG. 1  shows an apparatus that includes a charge pump for supplying power to a set of circuits according to an exemplary embodiment. Broadly speaking, a set of circuits in  FIG. 1 , such as the set of circuits labeled as  30 , may correspond to an active or normal mode of operation of apparatus  10 , i.e., they are operational during the active or normal mode of operation. During the low power or sleep mode of operation, however, circuits  30  may be inactivated, put in a sleep mode, etc. 
     Without limitation, circuits  30  may include a variety of circuitry, such as controllers, memory, processor circuitry, clock generation and distribution circuits, power management circuitry, supervisory circuitry, input/output circuitry, and the like. Generally, circuits  30  may include any type or variety of circuit that is desired to be functioning during the active or normal mode of operation, but inactive during a low power or sleep mode of operation. 
     Apparatus  10  includes another set of circuits, such as the set of circuits labeled as  25 . Circuits  25  may correspond to a low power mode (compared to the normal or active mode) or sleep mode of operation of apparatus  10 . In other words, circuits  25  are operational during a low power or sleep mode of operation (as well as during the normal or active mode of operation). Without limitation, circuits  25  may include state-retained memory; universal asynchronous receiver transmitter (UART); registers; real time clock (RTC) circuitry; display circuitry, such as a liquid crystal display (LCD) controller; etc. 
     Note that, in some embodiments, part of a circuit may be desired to be available during the active mode of apparatus  10 , while another part of the circuit may be desired to function in a low power or sleep mode for at least some of the time. For example, RTC circuitry (not shown in  FIG. 1 ) may include analog circuitry that is included in circuits  25  (to keep the clock running), and digital circuitry that may be included in circuits  30 . Other examples of such circuitry exist, as persons of ordinary skill in the art understand, depending on the specifications and desired performance or functionality of a given implementation. 
     In some embodiments, circuits  30  (e.g., controller  45  or other parts of circuits  30 ) may communicate with circuits  25 . In the exemplary embodiment of  FIG. 1 , such communication may take place via link  30 A. Using link  30 A, circuits  25  and  30  may communicate information, such as data, control signals, status signals, clock signals, and the like, as desired. As merely one example, circuits  30  may include a processor or controller that may use link  30 A to provide information to an LCD controller included as part of circuits  25 . As persons of ordinary skill in the art understand, depending on factors like the nature of the communication information and the specification of a particular implementation, link  30 A may include one or more wires, conductors, and the like. 
     Source  15  supplies power to various circuits in apparatus  10 . More specifically, source  15  provides supply voltage V s  to circuits  30 . Apparatus  10  includes charge pump  20 , which via supply line  15 A receives supply voltage V s  from source  15 . Charge pump  20  converts or scales supply voltage V s  to an output voltage V cp , that is lower than supply voltage V s . Thus, charge pump  20  has a voltage conversion factor, K, associated with it, such that K=V cp /V s . In some embodiments, K may have a value of approximately 0.5, i.e., the charge pump output voltage is given by V cp ≈0.5 V s , with such a charge pump sometimes called a “half mode” charge pump. 
     In some embodiments, one or more circuits included in circuits  30  may control the operation of charge pump  20 . In the embodiment shown in  FIG. 1 , link  33  provides a mechanism for providing one or more control signals to charge pump  20 . If desired, link  33  may provide communication from the charge pump to circuits  30 , as persons of ordinary skill in the art understand. 
     According to one aspect of the disclosure, in some embodiments, circuits  25  and  30  and charge pump  20  may be integrated into a single integrated circuit (IC), labeled  12  in  FIG. 1 . Integrating one or more of the circuits described above can improve the overall performance in some applications, for example, flexibility, responsiveness, die area, cost, materials used, power consumption, reliability, robustness, and the like, as desired. 
     According to another aspect of the disclosure, in some embodiments, apparatus  10  may constitute a portable apparatus. In such situations, source  15  may constitute a battery. In other embodiments, even where apparatus  10  is semi-portable or non-portable, or where using other power sources might be inconvenient, source  15  may nevertheless be a battery. Use of the battery overcomes provision of power through other means, such as wires or cables coupled to other sources, such as the mains and associated power conversion circuitry. In some embodiments, whether portable or not, source  15  may constitute a renewable energy or power source, for example, a solar panel (and associated power processing circuitry, as desired). 
       FIGS. 2A-2B  show more detailed block diagrams of apparatus  10  according to exemplary embodiments. Referring to  FIG. 2A , apparatus  10  includes a multiplexer (MUX)  40  or, generally, a controlled switch (e.g., a single pole dual throw (SPDT) switch) to control provision of power to circuits  25 . More specifically, the inputs of MUX  40  receive V s  and V cp , respectively. In response to control signal  47 , MUX  40  provides either V s  or V cp  to circuits  25 . In other words, one may selectively supply either V s  or V cp  to circuits  25 . 
     This capability allows more flexibility in providing a source of power to circuits  25 . Consider the situation where source  15  is a battery, or where the voltage and/or power provided by source  15  fluctuate over time or decrease over time. When source  15  provides a sufficiently high value of V s  that the output voltage of charge pump  20 , V cp , meets the specified supply voltage of circuits  25 , MUX  40  provides V cp  to circuits  25 . If the value of V s  changes such that V cp  is no longer suitable for powering circuits  25  (e.g., V s  falls below a specific value), MUX  40  provides V s  to circuits  25 . 
     Monitor circuit  35 , included as part of circuits  30 , provides control signal  47  (the select signal for MUX  40  in the embodiment shown). Monitor circuit  35  receives as inputs the voltages V s  and V cp . As described above, depending at least one of (or both) of the input voltages (V s  and V cp ), or depending on the relative values of the input voltages (or depending on another desired control scheme), monitor circuit  35  drives control signal  47  to appropriately provide power to circuits  25 . In other embodiments, monitor circuit  35  may receive the output voltage of MUX  40 , labeled V M  in  FIG. 2A , and use this voltage when determining the appropriate state of control signal  47 . 
     In some embodiments, circuits  30  include one or more of controller  45 . Referring to  FIG. 2A , which shows one controller, controller  45  may provide desired information or data processing capabilities, including without limitation, numerical calculation capability. Controller  45  may perform any desired processing or calculation in IC  12 . 
     In exemplary embodiments, controller  45  may constitute a controller, microcontroller, processor, microprocessor, field-programmable gate array (FPGA), programmable controller, or the like, as desired. Without limitation, in exemplary embodiments, controller  45  may include one or more of integrated random access memory (RAM), including program RAM, as desired, read only memory (ROM), non-volatile memory (NVM), such as flash memory, one-time programmable (OTP) circuitry, analog-to-digital converters (ADCs), digital-to-analog-converters (DACs), counters, timers, input/output (I/O) circuitry and controllers, arithmetic circuitry (e.g., adders, subtracters, multipliers, dividers), general and programmable logic circuitry, power regulators, and the like, as desired. 
     In some embodiments, rather than driving MUX  40  (or another switch or type of switch), monitor circuit  35  may interrupt or otherwise cause controller  45  to decide whether to supply V s  or V cp  to circuits  25 . In such embodiments, controller  45  may be programmed, for example, by using associated software or firmware, to control the supply of power to circuits  25  using a variety of criteria or considerations, for example, input from sensors, input from external sources, etc. 
     In addition to controller  45 , in some embodiments, IC  12  may include one or more of other circuitry, such as a power-on reset (POR) circuit, power management unit (PMU), host interface circuitry, brownout detector, watchdog timer, and the like. In some embodiments, one or more of the above circuits may be included in controller  45 , as desired, or may be included in circuits  25 . 
     According to one aspect of the disclosure, in some embodiments, part of a circuit or block may be included in circuits  25 , and another part of the circuit or block may be included in circuits  30 . For example, part of circuitry associated with displaying information on an LCD may be included in circuits  25 , so that the LCD can display information during all times or during desired times. Other LCD circuitry, on the other hand, may be included as part of circuits  30 . Thus, during the low power or sleep mode of operation of apparatus  10 , the LCD may display static information, whereas during the normal or active mode of operation, the other LCD circuitry is powered (as part of circuits  30 ), and provides information to the LCD, for example, as requested by controller  45 . 
     According to another aspect of the disclosure, in some embodiments, part of a circuit or block may be included in circuits  25 A, integrated in IC  12 , and another part of the circuit or block may be included in circuits  25 B, external to IC  12 .  FIG. 2B  shows such an arrangement according to an exemplary embodiment. As an example, and without limitation, in some embodiments, circuitry associated with an LCD may be included in circuits  25 A, whereas the LCD itself may be included in circuits  25 B (external to IC  12 ). A variety of other arrangements may be used according to other embodiments, as persons of ordinary skill in the art understand. 
     Note that, rather than using one link  30 A, as shown in the example in  FIG. 2B , separate links may be used between circuit  30  (controller  45  or other part of circuits  30 ) and circuits  25 A and  25 B, respectively. Using such link(s) circuits  25 A and  25 B may communicate information, such as data, control signals, status signals, clock signals, and the like, as desired. 
       FIG. 3  shows a circuit arrangement for a charge pump  20  for use in exemplary embodiments. Charge pump  20  includes four switches  50 ,  52 ,  54 , and  56 , labeled S 1 -S 4 , respectively. In addition, charge pump  20  includes capacitors  58  and  60 , labeled C 1 -C 2 , respectively. Switches  50 ,  52 ,  54 , and  56  constitute controlled or controllable switches. In other words, in response to control signals (not shown), switches  50 ,  52 ,  54 , and  56  may be opened or closed. 
     In exemplary embodiments, switches  50 ,  52 ,  54 , and  56  may be implemented as transistors, for example, metal oxide semiconductor (MOS) transistors. As persons of ordinary skill in the art understand, however, a variety of other devices may be used, depending on factors such as design and performance specifications, available fabrication technology, etc., for a given implementation. 
     A control signal, say, Φ 1 , controls switches  50  and  56 . A complementary control signal, say, Φ 2 , controls switches  52  and  54 .  FIG. 4  shows an exemplary set of switch control signals for charge pump  20 . Note that control signals Φ 1  and Φ 2  are not exactly complementary in order to avoid a crowbar current through charge pump  20 . More specifically, time periods (e.g., dead-time) labeled as t 1  and t 2 , added between the edges of control signals Φ 1  and Φ 2 , prevent switches  50 ,  52 ,  54 , and  56  from conducting at the same time. (Conduction by switches  50 ,  52 ,  54 , and  56  at the same time would effectively short V s  to ground.) 
     In exemplary embodiments, control signals Φ 1  and Φ 2  may have a desired frequency. In some embodiments, control signals Φ 1  and Φ 2  may have a frequency of 32.768 kHz, a frequency commonly used for RTCs. As persons of ordinary skill in the art understand, however, other frequencies may be used in other embodiments, depending on factors such as design and performance specifications, etc., for a given implementation. 
     Referring to  FIGS. 3 and 4 , when control signal Φ 1  is at a high level, switches  50  and  56  turn on, and couple capacitors  58  and  60  in series between V s  and ground. As a result, capacitors  58  and  60  charge. During this phase of operation, the node between capacitors  58  and  60  constitutes output  20 A of charge pump  20 . While control signal Φ 1  is at a high level, control signal Φ 2  is at a low level, which causes switches  52  and  54  to be off.  FIG. 5  shows the resulting circuit topology for this phase of operation of charge pump  20 . 
     Referring to  FIGS. 3 and 4 , when control signal Φ 2  is at a high level, switches  52  and  54  turn on, and couple capacitors  58  and  60  in parallel between output  20 A of charge pump  20  and ground. Thus, during this phase of operation, the coupled top terminals (the terminals not coupled to ground) of the capacitors constitute output  20 A of charge pump  20 . While control signal Φ 2  is at a high level, control signal Φ 1  is at a low level, which causes switches  50  and  56  to be off.  FIG. 6  shows the resulting circuit topology for this phase of operation of charge pump  20 . 
     Referring back to  FIG. 3 , during steady-state operation, a high level of control signal Φ 2  forces the same voltage (B cp ) across capacitors  58  and  60 . It may be shown that in steady state operation, the output voltage is approximately ½ the input voltage of charge pump  20 . In other words, 
                     V   cp     ≈       1   2     ⁢       V   s     .               (     Eq   .           ⁢   1     )               
Note that, as Equation 1 shows, the steady-state voltage conversion ratio of charge pump  20 , i.e., the ratio of V cp  to V s , does not depend on the capacitances of capacitors  58  and  60 .
 
     In exemplary embodiments, using a charge pump as shown in  FIG. 3  can achieve power conversion or transfer efficiencies of roughly 80%. As such, charge pump  20  exhibits a “transformer effect,” as its efficiency of 80% (0.8) is greater than the ratio of its output to input voltages, i.e., the ratio of the ratio of V cp  to V s , which is about 0.5, as Equation 1 states. Thus, charge pump  20  provides better power efficiency than a conventional linear voltage regulator. 
     Furthermore, charge pump  20  reduces the current drawn from source  15  (see  FIG. 1 ). A Thévenin equivalent circuit of charge pump  20 , illustrated in  FIG. 7 , helps to illustrate this attribute. More specifically, the Thévenin equivalent circuit includes a voltage source  65  with a magnitude V oc  (open-circuit output voltage), and a resistance  68 , with a resistance value R TH . Referring to  FIG. 3 , assuming that charge pump  20  includes a parasitic capacitor, C p , between node  62  and ground, one may show that: 
                       V   oc     =         V   s     ·         C   2     +     C   p         (       2   ⁢           ⁢     C   2       +     C   p       )         ≈       V   s     2         ,     
     ⁢   and           (     Eq   .           ⁢   2     )                   R   TH     =             C   2     +     C   p         (       2   ⁢           ⁢     C   2       +     C   p       )       ·         C   1     +     C   2     +     C   p         2   ⁢   f   ⁢           ⁢       C   1     ⁡     (       C   1     +     C   2       )             ≈     1     4   ⁢   f   ⁢           ⁢     C   1             ,           (     Eq   .           ⁢   3     )               
where f represents the switching or clock frequency of charge pump  20 .
 
     Using P LOSS  to denote power loss in charge pump  20 , Equation 4 expresses the relationship between the input power (P IN ) and output power (P OUT ) of charge pump  20 :
 
 P   IN   =P   OUT   +P   LOSS .  (Eq. 4)
 
Given that:
 
 P   IN   =I   s   ·V   s ,
 
 P   OUT   =I   OUT   ·V   CP ,
 
and
 
 P   LOSS   =I   OUT   2   ·R   TH ,
 
where I S  and I OUT  denote, respectively the input and output currents of charge pump  20 , one may express Equation 4 as:
 
 I   s   ·V   s   =I   OUT ·( V   OC   −I   OUT   ·R   TH )+ I   OUT   2   ·R   TH   =I   OUT   ·V   OC ,
 
and finally as:
 
     
       
         
           
             
               
                 
                   
                     I 
                     S 
                   
                   = 
                   
                     
                       
                         I 
                         OUT 
                       
                       · 
                       
                         
                           V 
                           OC 
                         
                         
                           V 
                           s 
                         
                       
                     
                     = 
                     
                       
                         
                           I 
                           OUT 
                         
                         · 
                         
                           
                             
                               C 
                               2 
                             
                             + 
                             
                               C 
                               p 
                             
                           
                           
                             
                               2 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 C 
                                 2 
                               
                             
                             + 
                             
                               C 
                               p 
                             
                           
                         
                       
                       ≈ 
                       
                         
                           
                             I 
                             OUT 
                           
                           2 
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     5 
                   
                   ) 
                 
               
             
           
         
       
     
     As Equation 5 illustrates, the transformer effect of charge pump  20  reduces the current drawn from source  15  by a factor of about 2, i.e., the inverse of the voltage conversion ratio, which is roughly 0.5. 
     In addition to the transformer effect, charge pump  20  reduces the current drawn from source  15  during the low power or sleep mode of operation in another way. Specifically, supplying a reduced voltage (V CP ) to circuits  25  (see  FIGS. 1-2 ) reduces the supply current that those circuits draw (compared to supplying those circuits with V s ). The reduced supply voltage also reduces the static leakage current of circuits  25 , thus additionally reducing the current draw from source  15 . 
     Referring to  FIGS. 2A and 3 , in some embodiments the function of MUX  40  can be performed by charge pump  20 . For example, the voltage V s  can be coupled to voltage V CP  by closing switches  50  and  52  in  FIG. 3 . In this configuration, an advantage is provided by using capacitor  60  as decoupling for the voltage (V CP ) at output  20 A of charge pump  20 . Furthermore, such an embodiment can provide an additional advantage by configuring switches  54  and  56  such that capacitor  58  is connected in parallel with capacitor  60 , thereby using both capacitors  58  and  60  as decoupling for the voltage (V CP ) at output  20 A of charge pump  20 . 
     Referring to the figures, persons of ordinary skill in the art will note that the various blocks shown might depict mainly the conceptual functions and signal flow. The actual circuit implementation might or might not contain separately identifiable hardware for the various functional blocks and might or might not use the particular circuitry shown. For example, one may combine the functionality of various blocks into one circuit block, as desired. Furthermore, one may realize the functionality of a single block in several circuit blocks, as desired. The choice of circuit implementation depends on various factors, such as particular design and performance specifications for a given implementation. Other modifications and alternative embodiments in addition to those described here will be apparent to persons of ordinary skill in the art. Accordingly, this description teaches those skilled in the art the manner of carrying out the disclosed concepts, and is to be construed as illustrative only. 
     The forms and embodiments shown and described should be taken as illustrative embodiments. Persons skilled in the art may make various changes in the shape, size and arrangement of parts without departing from the scope of the disclosed concepts in this document. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described here. Moreover, persons skilled in the art may use certain features of the disclosed concepts independently of the use of other features, without departing from the scope of the disclosed concepts.