Abstract:
A pixel circuit, and a method for operating a pixel circuit, to provide a multiple knee response characteristic. In one embodiment of the invention, one or more feed-through pulse (FTP) signals are transmitted to an integration node to end a first linear integration time period. The FTP signal allows electrons to drain from the integration node to a reset node through a transfer gate. After the first integration period, a second linear integration period is conducted on the pixel circuit, where the photo conversion gain of the pixel circuit becomes reduced under higher illumination conditions due to the drained node. Such operation creates a pixel with a photo response having multiple “knee” points, where each “knee” in the photo response curve will create separate regions whose photo sensitivities can be independently controlled with minimal thermal interference. By setting different voltage levels for the FTP signal and by controlling the integration time periods, the photo-response of the pixel circuit can be easily controlled.

Description:
[0001]    The present invention relates to a method of operating a pixel circuit to increase intrascene dynamic range while reducing fixed pattern noise.  
         BACKGROUND OF THE INVENTION  
         [0002]    Intrascene dynamic range refers to the range of incident light that can be accommodated by an image sensor in a single frame of pixel data. Examples of scenes that generate high dynamic range incident signals include an indoor room with outdoor window, an outdoor scene with mixed shadows and bright sunshine, night-time scenes combining artificial lighting and shadows and, in an automotive context, an auto entering or about to leave a tunnel or shadowed area on a bright day.  
           [0003]    Dynamic range is measured as the ratio of the maximum signal that can be meaningfully imaged by a pixel of the imager to its noise level in the absence of light. Typical CMOS active pixel sensors (and charge coupled device (CCD)) sensors have a dynamic range from 60 to 75 dB. This corresponds to light intensity ratios of 1000:1 to about 5000:1. Noise in image sensors, including CMOS active pixel image sensors, is typically between 10 and 50 e-rms. The maximum signal accommodated is approximately 30,000 to 60,000 electrons. The maximum signal is often determined by the charge-handling capacity of the pixel or readout signal chain. Smaller pixels typically have smaller charge handling capacity.  
           [0004]    Typical scenes imaged by cameras have lighting levels that generate signals on the order of 10-1,000 electrons under low light (1-100 lux), 1000-10,000 electrons under indoor light conditions (100-1000 lux), and 10,000-&gt;1,000,000 electrons (1000-100,000 lux) under outdoor conditions. To accommodate lighting changes from scene to scene, the so-called interscene dynamic range, an electronic shutter is used to change the integration time of all pixels in the arrays from frame to frame.  
           [0005]    To cover a single scene that might involve indoor lighting (100 lux) and outdoor lighting (50,000 lux), the required intrascene dynamic range is of the order of 5,000:1 (assuming 10 lux of equivalent noise) corresponding to 74 dB. In digital bits, this requires 13-14 bits of resolution. However, most CMOS active pixel sensors have only 10 bits of output and 8 bits of resolution typically delivered to the user in most image formats such as JPEG. Companding of the data is often used to go from 10-12 bits to 8 bits. One type of companding is gamma correction, where roughly the square root of the signal is generated.  
           [0006]    In order to accommodate high intrascene dynamic range, several different approaches have been proposed in the past. A common denominator of most approaches is performing signal companding within the pixel by having either a total conversion to a log scale (so-called logarithmic pixel) or a mixed linear and logarithmic response in the pixel. One example of a mixed linear and logarithmic circuit can be found in co-pending and commonly assigned patent application Ser. No. 10/226,127, filed Aug. 23, 2002, titled “A Wide Dynamic Range Linear-And-Log Active Pixel,” the disclosure of which is incorporated by reference herein.  
           [0007]    These prior approaches have several major drawbacks. First, the knee point in a linear-to-log transition is difficult to control, leading to fixed pattern noise in the output image. Second, under low light, the log portion of the circuit is slow to respond, leading to lag. Third, a logarithmic representation of the signal in the voltage domain (or charge domain) means that small variations in signal due to fixed pattern noise leads to large variations in the represented signal.  
           [0008]    Linear approaches have also been described where the integration time is varied during a frame to generate several different signals. This approach has architectural problems if the pixel is read out at different points in time since data must be stored in an on-board memory before the signals can be fused together. Another approach is to integrate two different signals in the pixel, one with low gain and one with high gain. However, the low gain portion of the pixel often presents color separation processing problems.  
         BRIEF SUMMARY OF THE INVENTION  
         [0009]    The present invention relates to increasing intra-scene dynamic range for image capturing in a pixel circuit. In one aspect, the invention provides a pixel circuit having an integration node; a conversion transistor having a source/drain connected to the integration node and a drain/source connected to a reset line; a feed-through pulse capacitor having one leg connected to a feed-through pulse signal line and the other leg connected to the integration node; a photodiode having one leg connected to the integration node; and an output transistor having a gate connected to the integration node.  
           [0010]    The pixel circuit of the present invention can be operated such that one or more feed-through pulse (FTP) signals are transmitted to an integration node after a first linear integration time period. After the FTP signal is transmitted, a second linear integration period is initiated on the pixel circuit, where the photo conversion gain of the pixel circuit becomes reduced due to leaked electrons from the photodiode. By generating overflow current in a transfer transistor during medium and high illumination conditions in one embodiment of the invention, the pixel circuit can operate with less noise. Such operation creates a pixel with a photo response having multiple “knee” points, where each “knee” in the photo response curve creates separate regions with photo sensitivities that can be independently controlled with minimal thermal interference.  
           [0011]    The disclosed configuration further provides added flexibility to controlling the photo response of a pixel circuit. By adjusting the FTP signal voltage (e.g., high, medium, low) and/or the integration time period, the photo response may be more easily suited to the needs of users.  
           [0012]    In another aspect, the invention provides a method of operating the pixel circuit, where an overflow pulse is transmitted on a feed-through pulse (FTP) line during a blanking period. During the blanking period, scanned data is not transmitted; thus noise from the FTP line is significantly reduced in the resulting video signal.  
           [0013]    In yet another embodiment, a FTP signal is used in conjunction with a readout signal RD in the pixel circuit to further stabilize knee responses during a multiple-knee operation during an overflow condition.  
           [0014]    These and other features and advantages of the invention will be more clearly seen from the following detailed description of the invention which is provided in connection with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    [0015]FIG. 1 is a block diagram of an imaging device of an embodiment of the present invention;  
         [0016]    [0016]FIG. 1A is a schematic diagram of an active pixel circuit of an embodiment of the present invention;  
         [0017]    [0017]FIG. 2 is an exemplary timing diagram illustrating the operation of the FIG. 1A pixel circuit under low illumination;  
         [0018]    [0018]FIG. 3 partially illustrates the pixel circuit of FIG. 1A fabricated on a semiconductor substrate;  
         [0019]    [0019]FIG. 3A is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a signal level readout condition on the reset region and the photodiode region under a low illumination condition;  
         [0020]    [0020]FIG. 3B is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a bias charge injection condition on the reset region and the photodiode region under a low illumination condition;  
         [0021]    [0021]FIG. 3C is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a bias charge overflow condition on the reset region and the photodiode region under a low illumination condition;  
         [0022]    [0022]FIG. 3D is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a reset level readout condition and the beginning of a first integration on the reset region and the photodiode region under a low illumination condition;  
         [0023]    [0023]FIG. 3E is a potential distribution diagram relating to the circuit of FIG. 3, illustrating an overflow condition on the reset region and the photodiode region under a low illumination condition;  
         [0024]    [0024]FIG. 3F is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a signal level readout condition on the reset region and the photodiode region under a low illumination condition;  
         [0025]    [0025]FIG. 3G is a potential distribution diagram relating to the circuit of FIG. 3, illustrating the completion of a second integration on the reset region and the photodiode region under a low illumination condition;  
         [0026]    [0026]FIG. 4 is an exemplary timing diagram illustrating an operating condition of the FIG. 1A pixel circuit under medium illumination;  
         [0027]    [0027]FIG. 5 partially illustrates the pixel circuit of FIG. 1A fabricated on a semiconductor substrate;  
         [0028]    [0028]FIG. 5A is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a signal level readout condition on the reset region and the photodiode region under a medium illumination condition;  
         [0029]    [0029]FIG. 5B is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a bias charge injection condition on the reset region and the photodiode region under a medium illumination condition;  
         [0030]    [0030]FIG. 5C is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a bias charge overflow condition on the reset region and the photodiode region under a medium illumination condition;  
         [0031]    [0031]FIG. 5D is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a reset level readout condition and the beginning of a first integration on the reset region and the photodiode region under a medium illumination condition;  
         [0032]    [0032]FIG. 5E is a potential distribution diagram relating to the circuit of FIG. 3, illustrating an overflow condition on the reset region and the photodiode region under a medium illumination condition;  
         [0033]    [0033]FIG. 5F is a potential distribution diagram relating to the circuit of FIG. 3, illustrating a signal level readout condition on the reset region and the photodiode region under a medium illumination condition;  
         [0034]    [0034]FIG. 5G is a potential distribution diagram relating to the circuit of FIG. 3, illustrating the completion of a second integration on the reset region and the photodiode region under a medium illumination condition;  
         [0035]    [0035]FIG. 6 is an exemplary timing diagram illustrating an operating condition of the FIG. 1A pixel circuit under high illumination;  
         [0036]    [0036]FIG. 7 is a graph illustrating the photo response of the pixel circuit of FIG. 1A under a high illumination condition;  
         [0037]    [0037]FIG. 8 is an exemplary timing diagram illustrating an operating condition of the FIG. 1A circuit using a multiple-knee response under an alternate embodiment of the invention;  
         [0038]    [0038]FIG. 9 is a graph of the photo response of the FIG. 1A pixel circuit utilizing the timing diagram of FIG. 8;  
         [0039]    [0039]FIG. 10 is a block diagram of an exemplary imager utilizing the knee response pixel of FIG. 8 under another embodiment of the invention;  
         [0040]    [0040]FIG. 11 is an exemplary timing diagram of the imager of FIG. 10; and  
         [0041]    [0041]FIG. 12 depicts a block diagram of a processor system employing the FIG. 1A pixel circuit, in accordance with yet another exemplary embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0042]    Embodiments of the present invention are employed in a CMOS imaging device generally illustrated in FIG. 1 by reference numeral  10 . The imaging device includes an array of pixels arranged in rows and columns with each pixel having a pixel circuit  100 , each pixel being associated with a column line to which all pixels of that column are connected, the pixels being selected row-by-row. The pixel circuit  100  provides a reset signal V RST  and a pixel image signal V SIG  as outputs during a reset and integration period, respectively, which are captured by a sample and hold circuit  200  associated with that column in response to sampling signals SHS (for the image signal) and SHR (for the reset signal), respectively. The sample and hold circuit  200  passes the reset signal V RST  and image signal V SIG  of a pixel circuit  100  to an amplifier  40  which in turn provides a signal representing the difference between the reset signal and pixel image signal (V RST −V SIG ) as an output. This difference signal is provided to an analog to digital converter  60  and, from there, to an image processor  80  which receives digitized pixel signals from all pixel circuits  100  of the pixel array and provides an image output.  
         [0043]    An active pixel circuit  100  in accordance with an embodiment of the invention is shown in greater detail in FIG. 1A. Pixel circuit  100  includes a transfer transistor  116 , an output transistor  120 , a row select transistor  124 , a photodiode  108 , and a feed-through capacitor  117 . Also provided are a row select signal line  131  receiving a row select signal RD, a reset signal line  121  receiving a reset signal RST and a feed through pulse line  119  receiving a feed through pulse signal FTP. A voltage supply line  123  is also provided which supplies a voltage VAAPIX to the pixel circuit  100 .  
         [0044]    The transfer transistor  116  has a gate threshold voltage of V t  and is operated either in a shut-off voltage operating mode or a sub-threshold voltage operating mode, as described in greater detail below. The feed through capacitor  117  is located between the horizontal feed through pulse (FTP) signal line  119  and a signal integration node  104 . One source/drain region of the transistor  116  is connected to the row reset (RST) signal line  121 , while the gate of transistor  116  is connected to the power supply line VAAPIX  123 , and the other source/drain region of transistor  116  is connected to integration node VPIX  104 . The photodiode  108  is connected to the integration node  104  and ground. One source/drain region of an output transistor  120  is connected to the supply line VAAPIX  123  while the gate of transistor  120  is connected to the integration node  104 . The gate of row select transistor  124  is connected to the row select signal line which receives the row select signal RD, while the source/drain regions of the transistor  124  are respectively coupled to output transistor  120  and column line  126 .  
         [0045]    When connected to the column line  126  through the row select transistor  124  as described above, the output transistor  120  operates as a source follower transistor and provides a gain to the charge signal received from node  104 .  
         [0046]    As noted, transistor  116  has two operating modes. One operating mode is a shut-off operating mode in which the transistor  116  imparts a linear output to an accumulated pixel image signal V SIG  at node  104  during a charge integration period, while the other operating mode is a sub-threshold operating mode which imparts a logarithmic output to the pixel image signal V SIG  accumulated at node  104 . The SHS and SHR pulses correspond to when the signal and reset voltages, respectively, are sampled. As with the control lines FTP, RD, and RST discussed below, the SHR and SHS pulses are produced by the signal controller  70 .  
         [0047]    The operation of the pixel circuit  100  will now be explained with reference to the timing diagram of FIG. 2, which shows a typical frame cycle during operation of the pixel circuit  100  under a low illumination condition. At time t 1 , the sample and hold signal SHS pulse (not shown) initiates a pixel image sampling signal to be applied to a sample and hold circuit which causes the pixel image signal V SIG  to be sampled and held. The read out signal RD at time t 1  is also high, signifying that charge accumulated at a node  104  is being read out. This charge is accumulated at node  104  prior to the time t 1 . At time t 2 , the RST line and the feed-through pulse line (FTP) go low (shown as V FTP     —     L  for the feed-through pulse). This causes V PIX , the voltage at node  104 , to be set to the RST line  121  low voltage. At time t 3 , the RST line  121  goes high, which begins the process of resetting the pixel. This causes V PIX , the voltage at node  104 , to begin increasing. The voltage V PIX  may be expressed in terms of equation (1), shown below:  
                       V   PIX          (   t   )       =       1   β                     ln        [     kt   +     exp        (     β   ×       V   PIX          (     t   3     )         )         ]                   where             k   =         β                   I   0         C   pix                       exp        [     β        (     VAAPIX   -     VT   0       )       ]                       (   1   )                               
 
         [0048]    where β represents an exponential coefficient of the subthreshold current of transistor  116 , I 0  represents the subthreshold current of transistor  116 , VT 0  represents the subthreshold voltage, and C pix  represents the total capacitance at the node  104 . After the resetting operation is initiated, charge from the reset node is subtracted from any prior signal levels, thus significantly reducing or even eliminating offset variation in the pixel.  
         [0049]    At time t 4 , FTP pulse goes high, causing VPIX to reach the level shown in equation (2) below:  
                 V   PIX          (     t   4     )       =         1   β                     ln        [     kt   RST     ]         +         C   FTP       C   pix            (       V   FTP_H     -     V   FTP_L       )                 (   2   )                               
 
         [0050]    where t RST  represents the overflow reset time (t 4 -t 3 ). The second term of equation (2) represents feed-through charge injected by the FTP pulse, where C FTP  represents the capacitance of capacitor  117 , C pix  represents the total capacitance at the node  104 , and V FTP     —     H  and V FTP     —     L  are the high and low levels of the FTP pulse illustrated in FIG. 2. It should be noted that C pix  consists of C FTP  and also includes the capacitance of the photodiode  108  and the sum of parasitic capacitances of the circuit  100  such as the gate capacitance of the transistor  120 , and the junction capacitance of the source node of the transistor  116 . Prior to a reset operation, a substantial amount of charge is injected into the pixel capacitor C FTP  and its potential is then pinned at the ‘low’ level of the RST line as shown between the time period t 2 -t 3  of FIG. 2. Because of this pinning action, the primary integrated signal is fully discharged from C pix , so that the reset operation completely resets the circuit  100 , and excess charge from previous imaging cycles of the circuit  100  does not ‘lag’ into following imaging cycles.  
         [0051]    At time t 5 , the RD line goes low, ending the first readout process, thus beginning a charge accumulation (integration) period. During the period from t 5  to t 6 , the transfer transistor  116  operates in an shut-off mode and a linear accumulated charge signal is processed at the node  104 .  
         [0052]    At the point t 6 , the FTP signal drops to a medium level (V FTP     —     M ), which interrupts the integration period. A signal charge, represented by I ph ×tac1, is accumulated at the pixel node V PIX    104 , where I ph  represents the photocurrent present at the node, and tac1 represents the first integration period (t 6 -t 5 ). When the FTP pulse drops to V FTP     —     M  at t 6 , V PIX  reaches the level shown in equation (3) below:  
                 V   PIX          (     t   6     )       =         V   PIX          (     t   4     )       -         I     p                 h       ×   tac1       C   pix       -         C   FTP       C   pix            (       V   FTP_H     -     V   FTP_M       )                 (   3   )                               
 
         [0053]    If the accumulated charge at the pixel node  104  is sufficiently small, the bias transistor MCM  116  will not turn on, and the accumulated charge will remain at node  104 . Thus the FTP pulse does not influence the signal charge, and V PIX  returns back to its initial voltage level at t 7 , when the FTP pulse goes back to V FTP     —     H , as shown in FIG. 2. Once the FTP pulse reaches V FTP     —     H  at t 7 , the integration period resumes, where the voltage V PIX  becomes:  
                 V   PIX          (     t   7     )       =         V   PIX          (     t   4     )       -         I     p                 h       ×   tac1       C   pix                 (   4   )                               
 
         [0054]    At the time t 1 ′ the charge accumulation (integration) period ends and the accumulated pixel voltage V PIX  is read out by the transistors  120 ,  124  as the pixel image signal V SIG , and a new frame cycle begins. After the end of the second integration period, a charge of I ph ×tac2 is additionally integrated, where I ph , represents the photocurrent at node  104 , and tac2 represents the second integration time period signified by t 1 ′-t 7 . The voltage V PIX  at time t 1 ′ may be expressed as:  
                 V   PIX          (     t   1   ′     )       =         V   PIX          (     t   4     )       -         I     p                 h       ×   tac1       C   pix       -         I     p                 h       ×   tac2       C   pix                 (   5   )                               
 
         [0055]    The photo response of pixel circuit  100  can thus be expressed as:  
                   Sig   =              G   SF     ×     (           I     p                 h       ×   tac1       C   pix       +         I     p                 h       ×   tac2       C   pix         )                   =              G   SF     ×       I     p                 h         C   pix       ×     (       t   1   ′     -     t   5       )                     (   6   )                               
 
         [0056]    where G SF  represents the source-follower gain.  
         [0057]    Turning to FIG. 3, a portion of the circuit of FIG. 1A is illustrated as an embodiment fabricated on a semiconductor substrate, for example, a silicon substrate. Reset line  121  is shown being connected to reset electrode region  302 , which is adjacent to transfer transistor MCM  116 . Transistor MCM  116  is further coupled to the VAAPIX line  123  as shown in FIG. 3. The FTP  119  line is connected to capacitor C FTP    100 , which connects further to the photodiode region  303 , and to the gate of readout transistor  120 . One source/drain terminal of readout transistor  120  is coupled to the VAAPIX line, while the other source/drain terminal of transistor  120  is connected to a source/drain terminal of transistor  124 . The gate of transistor  131  is connected to the row select line  131 , and the other source/drain terminal is connected to the output PIXOUT, and to an external load  301 , which has been illustrated as a current source in FIG. 3.  
         [0058]    [0058]FIGS. 3A-3G illustrate an exemplary potential distribution diagram for the circuit of FIG. 3 under a low-illumination condition, where the potential charge, or electrons  310  between regions  302  and  303  are illustrated. The barrier between the reset region  302  and the photodiode region  303  electrically isolates the photodiode region from the transfer transistor  116  during the integration period. Thus, any photo-generated charge  311  produced by photodiode  303  is initially stored in the right well region. The left-well region associated with reset node  302  is directly connected to reset line RST  121 , and stores the charge received from the reset RST  121  line.  
         [0059]    Turning to FIG. 3A, the exemplary potential distribution diagram illustrates the potential charge  310  present during the low illumination signal level readout at time t 1 , wherein the photodiode region accumulates photo-generated charge  311  after a previous integration period. Since the sum of the potential charge  310  and photo-generated charge potential  311  does not exceed the barrier potential, the potential is held in the diode region  303 . At time t 2 , both the RST pulse and the FTP pulse go low (see FIG. 2), at which time all regions are filled with electrons  310 , via a bias charge, as shown in FIG. 3B.  
         [0060]    Turning to FIG. 3C, when the RST pulse goes high at time t 3  (see FIG. 2), a bias charge overflow occurs in the reset region  302 , and the excess bias charge is swept away from the reset region  302 . If the reset region  302  potential exceeds the barrier potential, the photodiode region  303  potential is pinned at the potential of the reset region by an electrical channel (not shown) formed at the barrier region. Since transistor  116  is operating in the subthreshold region, the overflow current (I MCM ) can be expressed as:  
           I   MCM   =I   0 exp[β×( VAAPIX−V   PIX   −VT   0 )]  (7)  
         [0061]    where I 0  represents the sub-threshold current of transfer transistor  116 , and VT 0  represents the sub-threshold voltage across transfer transistor  116 .  
         [0062]    At time t 4 , illustrated in FIG. 3D, the feed-through pulse FTP goes high (see FIG. 2), and the reset level is read out and subtracted from the prior readout signal level so that offset variation of the pixel can be eliminated. After the first integration period, when t=t 6  (see FIG. 2), additional photo-generated charge  311  is accumulated at the photodiode region as shown in FIG. 3E. However, since the potential is not great enough under low illumination to overcome the barrier, the charge is held in the photodiode region  303 . In FIG. 3F, the additional charge  311  is integrated after t 7  (See FIG. 2), wherein the integration period ends at t=t 1 ′ (FIG. 3G), and a voltage readout occurs where the voltage from the photodiode region is read by source followed transistor  120  and row select transistor  124  onto the PIXOUT line  126 .  
         [0063]    Turning to FIG. 4, the exemplary timing diagram shows a typical frame cycle during operation of the pixel circuit  100  under a medium illumination condition. For times t 1  to t 5 , the timing operation is substantially identical to the corresponding times illustrated in the low illumination timing diagram of FIG. 2. After time t 5 , pixel circuit undergoes an integration period (tac1) under medium illumination. During the integration period under a medium illumination condition, the voltage V PIX  can be expressed as:  
                 V   PIX          (     t   4     )       -         I     p                 h       ×   tac1       C   pix               (   8   )                               
 
         [0064]    where I ph  is the photodiode current, and C pix  is the total capacitance at the integration node  104 . When the FTP pulse transitions from V FTP     —     H  to V FTP     —     M  at time t 6 , V PIX  drops to a lower level (represented by equation (3) above), causing transfer transistor MCM  116  to turn on. Once transistor  116  turns on, the accumulated photo-charge is drained through transistor  116 , and the VPIX voltage at time t 7  is:  
                 V   PIX          (     t   7     )       =         1   β                     ln        [     k        (       t   7     -     t   6       )       ]         +         C   FTP       C   pix            (       V   FTP_H     -     V   FTP_M       )                 (   9   )                               
 
         [0065]    and if the time period between t 7  and t 6  is set at the same length of the reset time t RST  (t 4 -t 3 ), equation (9) becomes:  
                 V   PIX          (     t   7     )       =         V   PIX          (     t   4     )       -         C   FTP       C   pix            (       V   FTP_M     -     V   FTP_L       )                 (   10   )                               
 
         [0066]    The difference between the circuit  100  operation under low illumination operation versus medium illumination operation can be defined by equation (11) shown below:  
                   I     p                 h       ×   tac1       C   pix       =         C   FTP       C   pix            (       V   FTP_M     -     V   FTP_L       )               (   11   )                               
 
         [0067]    where, if photodiode current I ph  is larger than the photodiode transition point, excess charge overflows through transistor MCM  166  and a medium illumination condition begins. The photodiode transition point can be expressed as:  
               I     p                   h        (   transition   )           =         C   FTP     tac1          (       V   FTP_M     -     V   FTP_L       )               (   12   )                               
 
         [0068]    After t 7 , FTP pulse goes back high, and pixel circuit  100  resumes charge accumulation under a second accumulation period (t 1 ′-t 7 =tac2). If the second accumulation period (tac2) is shorter than the first accumulation period (tac1), signal I ph ×tac2 is added to the integration node  104 . When the reset pulse RD ends the accumulation period at t1′, VPIX may be expressed as:  
                 V   PIX          (     t   1   ′     )       =         V   PIX          (     t   4     )       -         C   FTP       C   pix            (       V               FTP_        M       -     V   FTP_L       )       -         I     p                 h       ×   tac2       C   pix                 (   13   )                               
 
         [0069]    By subtracting the offset from the signal, the photo response of pixel circuit  100  can be expressed as:  
             Sig   =         G   SF       C   pix       ×     [         C   FTP     ×     (       V   FTP_M     -     V   FTP_L       )       +       I     p                 h       ×   tac2       ]               (   14   )                               
 
         [0070]    Turning to FIG. 5, a portion of the circuit of FIG. 1A is illustrated as an embodiment fabricated on a semiconductor substrate. The circuit of FIG. 5 is substantially identical to the circuit of FIG. 3, which was discussed above.  
         [0071]    FIGS.  5 A-G illustrate exemplary potential distribution diagrams for the circuit of FIG. 5 under a medium-illumination condition, where the potential charge, or electrons  310  between regions  302  and  303  are illustrated. Turning to FIG. 5A, the exemplary potential distribution diagram illustrates the potential charge  310  present during the medium illumination signal level readout at time t 1 , wherein the photodiode region accumulates photo-generated charge  311  after a previous integration period. At time t 2 , both the RST pulse and the FTP pulse go low (see FIG. 4), at which time all regions are filled with electrons  310 , via a bias charge as shown in FIG. 5B.  
         [0072]    Turning to FIG. 5C, when the RST pulse goes high at time t 3  (see FIG. 4), a bias charge overflow occurs in the reset region  302 , and the excess bias charge is swept away from the reset region  302 . Transistor  116  is operating in the subthreshold region, thus producing the overflow current (I MCM ) expressed as equation (7), discussed above.  
         [0073]    At time t 4 , illustrated in FIG. 5D, the feed-through pulse FTP goes high (see FIG. 4), and the reset level is read out and subtracted from the prior readout signal level so that offset variation of the pixel can be eliminated. After the first integration period, when t=t 6  (see FIG. 4), bias transistor MCM  116  turns on, allowing excess photo-generated charge  311  accumulated at the photodiode region  303  to drain through transistor MCM  116  to the reset region  302  as shown in FIG. 5E.  
         [0074]    Turning to FIG. 5F, the second integration period is illustrated, where additional photo-generated charge  311  is accumulated at the photodiode region  303 . In FIG. 5F, the additional charge  311  is integrated after t 7  (See FIG. 2), wherein the integration period ends at t=t 1 ′ (FIG. 5G), and a voltage readout occurs where the voltage from the photodiode region is read by source followed transistor  120  and row select transistor  124  onto the PIXOUT line  126 .  
         [0075]    [0075]FIG. 6 shows an exemplary timing diagram of a typical frame cycle during operation of the pixel circuit  100  under a high illumination condition. The timing operation of the FIG. 6 embodiment is substantially identical to the corresponding times illustrated in the medium illumination timing diagram of FIG. 4, except that V PIX  reaches a saturation (overflow) point  601  during the first integration period (tac1), as well as during the second integration period (tac2), illustrated by the dotted line  600  in FIG. 6.  
         [0076]    The photo response of pixel circuit  100  is further illustrated in FIG. 7, wherein the photo conversion characteristic has knee points ( 700 ,  701 ) between Regions I and II, and between Regions II and III. Each of the regions may be expressed by the following equations:  
         [0077]    Region I  
             Iph   &lt;         C   FTP     tac1          (       V   FTP_M     -     V   FTP_L       )               (   15   )               Sig   =       G   SF     ×       I     p                 h         C   pix       ×     (     tac1   +   tac2     )               (   16   )                               
 
         [0078]    Region II  
                   C   FTP     tac1          (       V   FTP_M     -     V   FTP_L       )       &lt;   Iph   &lt;         C   FTP     tac2          (       V   FTP_H     -     V   FTP_M       )               (   17   )               Sig   =         G   SF       C   pix       ×     [         C   FTP     ×     (       V   FTP_M     -     V   FTP_L       )       +       I     p                 h       ×   tac2       ]               (   18   )                               
 
         [0079]    Region III  
                   C   FTP     tac2          (       V   FTP_H     -     V   FTP_M       )       &lt;   Iph           (   19   )               Sig   =           G   SF       C   pix       ×     C   FTP     ×     (       V   FTP_H     -     V   FTP_L       )       =   saturation             (   20   )                               
 
         [0080]    By controlling the integration periods tac1 and tac2, the sensitivity of each region can be controlled. Additionally, the output range in each region is controlled by the levels of FTP pulses. If tac1 should become shorter in relation to tac2, the sensitivity in Region II would become lower than that of Region I. Accordingly, the dynamic range of I ph  would increase, while the overall output dynamic range remained the same. Since the photoconversion of each region is linear, the image processing required for colored images becomes simplified. Also, the controlled photo response is independent of temperature, so that a more stable performance characteristic can be achieved, and that greater uniformity between pixel outputs can be achieved.  
         [0081]    [0081]FIGS. 8 and 9 are an exemplary timing diagram and a photo conversion graph which illustrate how the circuit of FIG. 1A can be operated to achieve multiple knee points ( 900 - 902 ) through a simple modification in the FTP pulse. It should be understood that the number of “knee,” or transition points may be increased further by increasing the number of overflow pulses, and is not limited to the three-transition embodiment discussed herein. The timing diagram in FIG. 8 illustrates three integration periods: tac1 (t 6 -t 5 ), tac2 (t 8 -t 7 ) and tac3 (t 1 ′-t 9 ), where two different medium-level voltages (V FTP     —     M1  and V FTP     —     M2 ) are applied to the FTP pulses during the first (t 7 -t 6 ) and second (t 9 -t 8 ) overflow time periods. Under the exemplary embodiment of FIG. 8, the operation of the circuit is such that tac1&gt;tac2&gt;tac3.  
         [0082]    The transition points of each “knee” are dependent upon the photodiode current I ph  that is produced after an integration period. Thus, each I ph  transition point ( 900 - 902 ) can be expressed as:  
                 I     p                 h            (   transition1   )       =         C   FTP     tac1          (       V   FTP_M1     -     V   FTP_L       )               (   21   )                   I     p                 h            (   transition2   )       =         C   FTP     tac2          (       V   FTP_M2     -     V   FTP_M1       )               (   22   )                   I     p                 h            (   transition3   )       =         C   FTP     tac3          (       V   FTP_H     -     V   FTP_M2       )               (   23   )                               
 
         [0083]    Under a low illumination condition, if I ph  does not reach the level expressed in equation (21), no overflow current will subsequently flow in the 1st and 2nd overflow periods. In such a case, the pixel response may be expressed as:  
                 V   PIX          (     t1   ′     )       =         V   PIX          (     t   4     )       -         I     p                 h       ×     (     tac1   +   tac2   +   tac3     )         C   pix                 (   24   )                               
 
         [0084]    However, when I ph  exceeds the transition expressed in equation (21) after the first integration period, overflow current begins to flow during the first overflow period (t 7 -t 6 ), and the resulting VPIX voltage is pinned by the overflow operation at t 7 :  
                 V   PIX          (     t   7     )       =         V   PIX          (     t   4     )       -         C   FTP       C   pix            (       V   FTP_M1     -     V   FTP_L       )                 (   23   )                               
 
         [0085]    After the first overflow period, the pixel continues accumulation of charge during the second (tac2) and third (tac3) integration periods. The resulting V PIX  signal being read out at time t 1 ′ can be expressed as:  
                       V   PIX          (     t   1   ′     )       =         V   pix          (     t   4     )       -         C   FTP       C   pix            (       V   FTP_M1     -     V   FTP_L       )       -                                I     p                 h       ×       (     tac2   +   tac3     )       C   pix                       (   24   )                               
 
         [0086]    As I ph  increases further and exceeds the second transition point, overflow current will flow in the second overflow period, pinning the V PIX  voltage at time t 9 :  
                 V   PIX          (     t   9     )       =         V   PIX          (     t   4     )       -         C   FTP       C   pix            (       V   FTP_M2     -     V   FTP_M1       )                 (   25   )                               
 
         [0087]    thus:  
                 V   PIX          (     t   1   ′     )       =         V   PIX          (     t   4     )       -         C   FTP       C   pix            (       V   FTP_M2     -     V   FTP_L       )       -       I     p                 h       ×     tac3     C   pix                   (   26   )                               
 
         [0088]    If I ph  becomes sufficiently large and V PIX  reaches an overflow level after the third integration period, the photo conversion operation becomes saturated.  
         [0089]    Turning to FIG. 9, the illustrated graph shows an exemplary photo conversion response of pixel circuit  100  operating under the timing shown in FIG. 8. The graph in FIG. 9 shows three different photo conversion gain responses ( 903 - 905 ), where each transition “knee” ( 900 - 902 ) results in the formation of Regions I-IV. Each of the regions may be expressed by the following equations:  
         [0090]    Region I  
           I   ph   &lt;I   ph (transition 1)  (27)              Sig   =       G   SF     ×       I     p                 h         C   pix       ×     (     tac1   +   tac2   +   tac3     )               (   28   )                                 
         [0091]    Region II  
           I   ph (transition1)&lt; I   ph   &lt;I   ph (transition2)  (29)              Sig   =         G   SF       C   pix       ×       [         C   FTP     ×     (       V   FTP_M1     -     V   FTP_L       )       +       I     p                 h       ×     (     tac2   +   tac3     )         ]     .               (   30   )                                 
         [0092]    Region III  
           I   ph (transition2)&lt; I   ph   &lt;I   ph (transition3)  (31)              Sig   =           G   SF       C   pix       ×     C   FTP     ×     (       V   FTP_M2     -     V   FTP_L       )       +       I     p                 h       ×   tac3               (   32   )                                 
         [0093]    Region IV  
           I   ph   &gt;I   ph (saturation)  (33)              Sig   =           G   SF       C   pix       ×     C   FTP     ×     (       V   FTP_H     -     V   FTP_L       )       =   saturation             (   34   )                                 
         [0094]    Each of the photo response conversion gains  903 - 905  shown in FIG. 9 are determined by the integration periods tac1-tac3, where  
         Gain1   =     1     tac1   +   tac2   +   tac3         ,     Gain2   =     1     tac2   +   tac3         ,       and                 Gain3     =       1   tac3     .                             
 
         [0095]    The ranges of the photo responses ( 906 - 908 ) between transition points ( 900 - 902 ) are a function of the FTP voltage, and may be expressed as Range1=(V FTP     —     M1 −V FTP     —     L ); Range2=(V FTP     —     M2 −V FTP     —     M1 ) and Range3=(V FTP     —     H −V FTP     —     M2 ). Thus it can be seen that the range and gain of each region can be controlled by a predetermined pulse height and overflow timing of the FTP pulse, thus providing flexibility in optimizing photo conversion characteristics through the application of different FTP pulses.  
         [0096]    Turning to FIG. 10, the block diagram illustrates an exemplary embodiment of an imager  1010  using the knee response pixel described above. The imager  1010  consists of a pixel array  1000 , having n×m pixels, having a timing control block  1008 , which provides driving and control pulses, along with sync signals to external circuits. The row address block  1006  generates row address pulses from address signals received from the timing controller  1008 , and transmits the pulses to the level mix block  1007 . Level Mix block  1007  generates row pulses, including RD, RST and FTP, for each of the rows (not shown) in the pixel array  1000 .  
         [0097]    The analog process block  1001  comprises of an amplifier array, a correlated double sampling (CDS) array and an analog memory array (which have been omitted for purposes of simplicity), where pixel outputs from pixel array  1000  are brought up to a required gain level, and where fixed pattern noise caused by variations in the pixel offset are suppressed by the CDS operation and stored in the analog memory array. The column address block  1002  receives column address signals from timing control block  1008 , and generates column address pulses that are transmitted to the analog process block  1001 , so that stored signals in the analog memory array may be read out. The signal readout from the analog memory is transmitted to the analog-to-digital converter (ADC) block  1003 , where the signal is digitally converted and transmitted to the digital process block  1004  for processing (e.g., white balance, color interpolation, gamma correction, etc.). Once processed, the signal is then outputted from the output block  1005 .  
         [0098]    [0098]FIG. 11 illustrates an exemplary timing diagram for one frame cycle having a single “knee” point of the imager of FIG. 10. Signals RD, RST and FTP are output by the level mix block  1007  and are illustrated for each row line (1−m). The SHS and SHR pulses for CDR operation have been omitted for the purpose of clarity. The frame cycle for each row line in the embodiment of FIG. 11 begins when a respective row&#39;s RD pulses goes high, and ending when the RD pulse goes high again after two integration periods (tac1, tac2).  
         [0099]    Turning to row line  1  of FIG. 11, the row address block  1006  outputs a rows select RD(1) pulse at the beginning of the frame cycle, and subsequently outputs a reset pulse RST( 1 ) to reset the pixels in the first row. After the FTP(1) pulse is outputted, the first integration period tac1 is initiated, and continues until level mix block  1007  generates a short RD(1) pulse, ending the first integration period (tac1), and producing an overflow pulse FTP( 1 ) during the horizontal blanking period of row line m−2.  
         [0100]    A row cycle is illustrated in the exemplary embodiment of FIG. 11 between the rising edges of each row select pulses (RD(m−2), RD(m−1)) of adjacent row lines (row line m−2 and row line m−1), where each row cycle is comprised of a horizontal blanking period, followed by a data scanning period. Data stored in the analog memory array in the analog processing circuit  1001  are scanned and read out during the data scanning period, so that, for example, the overflow operation initiated for the first row does not affect data readout for the m−2 row.  
         [0101]    Once a row&#39;s frame cycle is complete (e.g., row line  1 ), the operation moves sequentially to the next row (row line  2 ) to begin a new cycle, until all rows are read, reset and submitted to an overflow operation. Once the last row (row line m) is reached, one frame period will have been completed. In the exemplary embodiment of FIG. 11, signal integration periods tac1 and tac2 are held constant through each row, so that the same photo conversion characteristics and knee responses can be obtained in the entire pixel array region. It should be understood that, while a single “knee” point was described in the embodiment, that multiple knee points can be obtained by providing additional overflow pulses described in the embodiments above.  
         [0102]    [0102]FIG. 12 illustrates an exemplary processing system  2000  which utilizes a pixel circuit such as that described in connection with FIGS. 1-11. The processing system  2000  includes one or more processors  2001  coupled to a local bus  2004 . A memory controller  2002  and a primary bus bridge  2003  are also coupled the local bus  2004 . The processing system  2000  may include multiple memory controllers  2002  and/or multiple primary bus bridges  2003 . The memory controller  2002  and the primary bus bridge  2003  may be integrated as a single device  2006 .  
         [0103]    The memory controller  2002  is also coupled to one or more memory buses  2007 . Each memory bus accepts memory components  2008 . The memory components  2008  may be a memory card or a memory module. The memory components  2008  may include one or more additional devices  2009 . For example, in a SIMM or DIMM, the additional device  2009  might be a configuration memory, such as a serial presence detect (SPD) memory. The memory controller  2002  may also be coupled to a cache memory  2005 . The cache memory  2005  may be the only cache memory in the processing system. Alternatively, other devices, for example, processors  2001  may also include cache memories, which may form a cache hierarchy with cache memory  2005 . If the processing system  2000  include peripherals or controllers which are bus masters or which support direct memory access (DMA), the memory controller  2002  may implement a cache coherency protocol. If the memory controller  2002  is coupled to a plurality of memory buses  2007 , each memory bus  2007  may be operated in parallel, or different address ranges may be mapped to different memory buses  2007 .  
         [0104]    The primary bus bridge  2003  is coupled to at least one peripheral bus  2010 . Various devices, such as peripherals or additional bus bridges may be coupled to the peripheral bus  2010 . These devices may include a storage controller  2011 , a miscellaneous I/O device  2014 , a secondary bus bridge  2015 , a multimedia processor  2018 , and a legacy device interface  2020 . The primary bus bridge  2003  may also be coupled to one or more special purpose high speed ports  2022 . In a personal computer, for example, the special purpose port might be the Accelerated Graphics Port (AGP), used to couple a high performance video card to the processing system  2000 .  
         [0105]    The storage controller  2011  couples one or more storage devices  2013 , via a storage bus  2020 , to the peripheral bus  2010 . For example, the storage controller  2011  may be a SCSI controller and storage devices  2013  may be SCSI discs. The I/O device  2014  may be any sort of peripheral. For example, the I/O device  2014  may be an local area network interface, such as an Ethernet card. The secondary bus bridge may be used to interface additional devices via another bus to the processing system. For example, the secondary bus bridge may be an universal serial port (USB) controller used to couple USB devices  2017  via to the processing system  2000 . The multimedia processor  2018  may be a sound card, a video capture card, or any other type of media interface, which may also be coupled to one additional device such as speakers  2019 . The legacy device interface  2020  is used to couple legacy devices, for example, older styled keyboards and mice, to the processing system  2000 .  
         [0106]    The processing system  2000  illustrated in FIG. 8 is only an exemplary processing system with which the invention may be used. While FIG. 8 illustrates a processing architecture especially suitable for a general purpose computer, such as a personal computer or a workstation, it should be recognized that well known modifications can be made to configure the processing system  2000  to become more suitable for use in a variety of applications. For example, many electronic devices which require processing may be implemented using a simpler architecture which relies on a CPU  2001  coupled to memory components  2008  and/or memory devices  2009 . The modifications may include, for example, elimination of unnecessary components, addition of specialized devices or circuits, and/or integration of a plurality of devices.  
         [0107]    While the invention has been described in detail in connection with preferred embodiments known at the time, it should be readily understood that the invention is not limited to the disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims.