Abstract:
The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.

Description:
BACKGROUND OF INVENTION 
   1. Technical Field 
   The present invention generally relates to transistors for a semiconductor device and methods of fabricating the same. 
   A claim of priority is made to Korean Patent Application No. 10-2004-0005858, filed Jan. 29, 2004, the contents of which are incorporated by reference in their entirety. 
   2. Discussion of the Related Art 
   Conventional semiconductor devices have a transistor. The transistor includes a gate pattern and impurity regions disposed on a semiconductor substrate of the devices. Electrical characteristics of the transistor depend on the gate pattern and the impurity regions. The gate pattern has at least one conductive layer. The conductive layer is formed of a doped polysilicon or a metal silicide stacked on the doped polysilicon. The impurity regions generally refer to source and drain regions of the transistor, and each region is formed by an impurity ion implantation process. 
   However, impurity ions may diffuse into the gate pattern when the transistor is driven. The diffusion causes a depletion capacitance in the gate pattern. Thus, the depletion capacitance causes a voltage applied to the gate pattern to drop, which delays the immediate voltage transfer to the semiconductor substrate. Further, the voltage may drop as much as the capacitance, thereby deteriorating a driving capability of the transistor. Therefore, even though a gate pattern having a conductive layer is advantageous because it simplifies a fabrication process, a method to suppress the depletion capacitance is required. 
   U.S. Pat. No. 6,124,177 discloses, for example, a conventional method of fabricating a deep sub-micron MOSFET structure with improved electrical characteristics. 
   This method discloses forming an arch-shaped gate pattern on a semiconductor substrate. The gate pattern is formed of an undoped polysilicon layer. Ion implantation processes are performed in the semiconductor substrate by using the gate pattern as a mask to form N source and drain areas. The source and drain areas are impurity regions, which overlap the gate pattern. And the source and drain areas produce a gradual concentration gradient in a direction away from the gate pattern. 
   The method further includes forming gate spacers, which do not cover sidewalls of the gate pattern. That is, air spacers are formed between the gate spacers and the sidewalls of the gate pattern. Using the gate spacers and the gate pattern as a mask, an ion implantation process is used to form N+ source and drain areas in the semiconductor substrate. The conductivity type of the gate pattern is determined during the formation of the N+ source and drain contact areas as well as the source and drain N− areas. Then, a silicidation process is performed on the semiconductor substrate to form a silicide layer on the N+ source and drain areas and the gate pattern. 
   However, this method forms a silicide layer on the gate pattern. Thus, this method cannot protect against diffusion of impurity ions through the doped polysilicon portion of the gate pattern, which can cause a depletion capacitance. Therefore, a method to suppress the generation of the depletion capacitance is required. 
   SUMMARY OF THE INVENTION 
   According to an embodiment of the present invention, there is provided a transistor for a semiconductor device having a diffusion barrier region and electrode region disposed in an active region of a semiconductor substrate, wherein the electrode region is located between the diffusion barrier and a surface of the semiconductor substrate, a gate insulating layer disposed on the semiconductor substrate, a silicide gate pattern disposed on the gate insulating layer, and n electrode pattern disposed adjacent the gate pattern, and contacting the electrode region. 
   The present application also discloses a method of manufacturing a transistor for a semiconductor device by forming a gate insulating on a semiconductor gate, forming a sacrificial poly layer pattern on the gate insulating layer, performing a first ion implantation process on the sacrificial poly layer pattern, forming a first metal layer on the sacrificial ploy layer pattern, and performing a first silicide process between the first metal layer and the sacrificial poly layer pattern, thereby forming a gate pattern, wherein the gate pattern is completely a silicide layer. 
   The method is further manufactured by sequentially performing second and third ion implantation processes on the semiconductor substrate mask, to form an impurity electrode definition region and a diffusion barrier region, respectively, forming a gate spacer on sidewalls of the gate pattern, performing a fourth ion implantation process on the electrode definition region, the gate pattern, and the gate spacers, to form an impurity electrode region, wherein the electrode definition region and the impurity electrode definition define an electrode region, forming a second metal layer on the silicide gate pattern and the electrode definition region, and performing a second silicide process on the second metal layer and the electrode definition region, thereby forming an electrode pattern. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows when taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts. 
       FIG. 1  is a layout of a transistor according to the present invention; 
       FIG. 2  is a sectional view taken along line I-I′ of  FIG. 1 ; and 
       FIGS. 3 through 14  are sectional views taken along line I-I′ of  FIG. 1  illustrating a method of fabricating a transistor of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  is a layout of a transistor according to the present invention, and  FIG. 2  is a sectional view taken along line I-I′ of  FIG. 1 . It will be understood that when an element such as a layer, a region or a substrate is referred to as being “on” or “onto” another element, it can be directly on the other element or intervening elements may also be present. 
   Referring to  FIGS. 1 and 2 , an active region  15  is disposed in a semiconductor substrate  10 , and a gate insulating layer  60  is disposed on a predetermined portion of active region  15 . A gate pattern  78  is formed on gate insulating layer  60 , and a gate spacer  120  cover sidewalls of gate pattern  78 . Gate pattern  78  has a square shape or a rectangular shape at its cross-section. Gate pattern  78  is a silicide layer having a conductivity type, and gate spacer  120  is preferably a silicon nitride (Si 3 N 4 ). Further, gate spacer  120  is preferably silicon oxide (SiO 2 ). A material for gate insulating layer  60  is selected from SiO x , SiO x N y , HfO x , ZrO x , and a composite thereof. The silicide layer is formed by a silicidation process between Ti, Co, Ni, Ta, or a mixture thereof with a doped polysilicon layer. 
   An electrode region  140  and a diffusion barrier region  115  are disposed in semiconductor substrate  10 . Electrode region  140  overlaps gate pattern  78  so that gate insulating layer  60  is disposed between two electrode regions  140 . Each of electrode region  140  contains an impurity electrode definition region  105  and an impurity electrode region  135 . Impurity electrode definition region  105  and impurity electrode region  135  have an LDD (lightly doped drain) structure. Diffusion barrier region  115  overlaps a gate spacer  120 , and at the same time, surrounds electrode regions  140 . A channel region  45  is disposed between two electrode regions  140 . The conductivity type of gate pattern  78  is different than the conductivity type of diffusion barrier region  115  and channel region  45 . Electrode region  140  has the same conductivity type as gate pattern  78 . 
   An electrode pattern  160 , which is isolated away from gate pattern  78  by gate spacer  120 , is disposed on and contacts electrode region  140 . 
   As such, gate pattern  78  is preferably disposed on semiconductor substrate  10  to form a C-MOSFET (complementary metal oxide silicon field effect transistor), an N-MOSFET, or a P-MOSFET. If gate pattern  78  has the same Fermi energy level as an N-type conductive polysilicon layer, electrode region  140  and diffusion barrier region  115  have an N-type conductivity and a P-type conductivity, respectively, to form the N-MOSFET. If gate pattern  78  has the same Fermi energy level as a P-type conductive polysilicon layer, electrode regions  140  and diffusion barrier regions  115  have a P-type conductivity and an N-type conductivity, respectively, to form the P-MOSFET. Further, the N- and the P-MOSFETs may be simultaneously disposed in semiconductor substrate  10 , to form the C-MOSFET. 
     FIGS. 3 through 14  are sectional views taken along line I-I′ of  FIG. 1  illustrating a method of fabricating a transistor according to the present invention. 
   Referring to  FIGS. 3 and 4 , in an active region  15 , a pad layer  20  is formed on a semiconductor substrate. A mask layer  30  is formed on pad layer  20 . Using mask layer  30 , a mask pattern  34  is formed on pad layer  20 . Using mask pattern  34  as a mask, an impurity definition region  40  is formed in semiconductor substrate  10 . Further, a mask spacer layer  50  is conformally formed on mask pattern  34 . 
   Mask layer  30  is formed of an insulating material with the same etching ratio as mask spacer layer  50 . Mask layer  30  and mask spacer layer  50  are formed of a material selected from Si x N y /SiO x /Si x N y , Si x N y /SiO x , SiO x /Si x N y , SiO x /Si x N y /SiO x , and Si x N y . In the case of an N-MOSFET, impurity definition region  40  is formed by implanting P-type impurity ions. In the case of a P-MOSFET, impurity definition region  40  is formed by implanting N-type impurity ions. Impurity definition region  40  is implanted near the surface of semiconductor substrate  10  by controlling the implantation energy and dose of the impurity ions. 
   Referring to  FIGS. 5 and 6 , an etching process is performed on mask spacer layer  50  to expose an upper surface of mask patterns  34 , which also forms a mask spacer  55 . Mask spacer  55  is formed on sidewalls of mask patterns  34 . The etching process is sequentially performed on pad layer  20  to expose impurity definition region  40 . 
   A gate insulating layer  60  is formed on the exposed portion of impurity definition region  40 . A sacrificial poly layer  70  is formed on the resulting structure. Gate insulating layer  60  is formed from a material selected from SiO x , SiO x N y , HfO x , and ZrO x , and a composite thereof. Sacrificial poly layer  70  is formed of an undoped polysilicon. 
   Referring to  FIGS. 7 and 8 , an etching process is performed on sacrificial poly layer  70  such that mask pattern  34  and mask spacer  55  are partially etched, and a sacrificial poly layer pattern  74  is formed. 
   Using mask pattern  34  and mask spacer  55  as a mask, a first ion implantation process  80  is performed on sacrificial poly layer pattern  74 . First ion implantation process  80  is performed by controlling energy of the impurity ions such that an Rp (projection range) of the impurity ions is positioned in sacrificial poly layer pattern  74 . Also, the dose of the impurity ions is about 1.0E14 to 5.0E15/cm 2 . 
   In the case of an N-MOSFET, a gate pattern  78  is formed by implanting N-type impurity ions, or in the case of a P-MOSFET, gate pattern  78  is formed by implanting P-type impurity ions. 
   Referring to  FIGS. 9 and 10 , a gate metal layer  90  is formed on the resultant structure. A silicidation process  95  is performed by reacting gate metal layer  90  with sacrificial poly layer pattern  74  to transform sacrificial poly layer pattern  74  into a silicide layer. Then, the non-reacted portions of gate metal layer  90  are removed. 
   Gate metal layer  90  is a metal selected from Ti, Co, Ni, Ta, and a mixture thereof. An annealing process is preferably performed to form a low resistance gate pattern  78 . 
   Subsequently pad layer  20 , mask pattern  34 , and mask spacer  55  are removed from semiconductor substrate  10 . Then using gate pattern  78  as a mask, a second ion implantation process  100  is performed in semiconductor substrate  10  to form an impurity electrode definition region  105 . Second ion implantation process  100  also implants impurity ions into gate pattern  78 . The dose of impurity electrode definition region  105  is higher than that of impurity definition region  40 . Impurity electrode definition region  105  overlaps gate pattern  78 . In this structure, impurity electrode definition region  105  defines a channel region  45  under the gate pattern  78 . 
   In the case of an N-MOSFET, impurity electrode definition region  105  is formed by implanting N-type impurity ions, or in the case of a P-MOSFET, impurity electrode definition regions  105  are formed by implanting P-type impurity ions. 
   Referring to  FIGS. 11 and 12 , using gate pattern  78  as a mask, a third ion implantation process  110  is performed on the resultant structure. Third ion implantation process  110  is performed to form a diffusion barrier region  115  in semiconductor substrate  10 . Third ion implantation process  110  is preferably performed by using impurity ions having a dose lower than those of impurity electrode definition region  105  and channel region  45 . However, third ion implantation process  110  may be performed by using impurity ions having the same dose as that of channel region  45 . Further, third ion implantation process  110  is performed such that an Rp (projection range) of the impurity ions is positioned in semiconductor substrate  10 , and is greater than that of the impurity electrode definition regions  105 . By doing so, diffusion barrier region  115  surrounds impurity electrode definition region  105 . 
   A gate spacer  120  is formed on sidewalls of gate pattern  78 . Using gate spacers  120  and gate pattern  78  as a mask, a fourth ion implantation process  130  is performed on semiconductor substrate  10 . Fourth ion implantation process  130  is performed to form an impurity electrode region  135 , which overlaps gate spacers  120 . By controlling energy of the impurity ions, fourth ion implantation process  130  is performed such that an Rp of the impurity ions is positioned between impurity electrode definition region  105  and diffusion barrier region  115 . Further, fourth ion implantation process  130  is performed such that a dose of the impurity ions is the same as first ion implantation process  90  of  FIG. 9 . Impurity electrode definition region  105  and impurity electrode region  135  form an electrode region  140 . Electrode region  140  is formed to have an LDD (lightly doped drain) structure. 
   In the case of an N-MOSFET, diffusion barrier region  115  and impurity electrode region  135  are formed by implanting P-type and N-type impurity ions, respectively, or in the case of a P-MOSFET, diffusion barrier region  115  and impurity electrode region  135  are formed by implanting N-type and P-type impurity ions, respectively. Each of third and fourth ion implantation processes  110 ,  130  is performed such that impurity ions are also implanted in gate pattern  78 . 
   Referring to  FIGS. 13 and 14 , an electrode metal layer  150  is conformally formed on the resultant structure. Electrode metal layer  150  is a metal selected from Ti, Co, Ni, Ta, and a mixture thereof. A silicidation process is performed on electrode metal layer  150  to form metal silicide layers in electrode regions  140 . Electrode metal layer  150  and gate pattern  78  do not react with each other during this silicidation process, because all the silicon in gate pattern  78  have been completely exhausted. 
   Further, any unreacted electrode metal layer  150  is removed, and an electrode pattern  160 , i.e., a metal silicide layer, is formed. Electrode pattern  160  contacts electrode region  140 . 
   Gate pattern  78  has the same Fermi energy level as a polysilicon layer of a P-type or an N-type conductivity. 
   A degree of freedom of the silicidation process is increased in the formation of a transistor according to the present invention, because electrode metal layer  150  does not react with gate pattern  78  during the formation of electrode patterns  160 . 
   As described above, according to the present invention, the gate pattern is formed of a silicide layer, thereby suppressing depletion by the impurity ions in the pattern when a transistor is driven.