Abstract:
Clock-controlled dual slope voltage to frequency converter has an integrator supplying a charging ramp to a threshold detector. The slope of the ramp depends on the input voltage to the integrator and the threshold detector is triggered by the ramp to enable a pulse from a clock to generate a constant current discharge pulse. The discharge pulse is fed to the integrator to produce a discharge ramp back below the threshold. The frequency output is taken from the output of the threshold detector to be synchronous with triggering of the detector.

Description:
This application is a continuation of my copending U.S. application Ser. No. 06/472,868 filed Mar. 3, 1983 for Clock Controlled Dual Slope Voltage to Frequency Converter. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to clock controlled dual slope voltage to frequency converters. Various types of voltage to frequency converters are known and a useful summary of the various kinds is published in &#34;Designing With Operational Amplifiers--Application Alternatives&#34;, 1977, Burr-Brown Research Corporation, Chapter 8.2 (pages 212-223). The highest precision form of converter as discussed in the above publication is the clock controlled converter which uses a precision clock signal to determine the duration of the constant current discharge pulse applied to the integrator circuit to provide dual slope operation. The problem with such clock controlled converters is that the frequency output signal of the converter is always a subharmonic of the clock frequency, although the average of the output signal frequency is the desired output frequency. As a result, although such converters can have high precision, they have an inherent delay resulting from the need to average the frequency of the output signal. An example of such a converter is shown in U.K. Patent Application Publication No. 2066626. 
     The present invention provides a converter which obtains the benefits of clock controlled operation whilst providing directly an output frequency which is not phase related to the clock frequency so that frequency averaging is not required. 
     SUMMARY OF THE INVENTION 
     According to the present invention there is provided a clock controlled dual slope voltage to frequency converter comprising an input terminal for an input voltage to the converter, an integrator connected to said input terminal to provide an output signal having a charging slope dependent on said input voltage, a clock pulse source, comparator means arranged to provide an output indication in response to each occasion the output signal of the integrator exceeds a predetermined threshold level during charging, discharge pulse generating means arranged to supply, following said output indication, a constant current discharge pulse to the integrator having a constant pulse duration determined by clock pulses from the clock pulse source, whereby the output signal of the integrator has a discharging slope and falls below said predetermined threshold level during each said discharge pulse, frequency signal output means including at least one output terminal of the converter and connected to the output of the comparator means to provide a frequency signal on the output terminal synchronised with the output indications of the comparator means, or a respective said synchronised frequency signal on each output terminal. 
     With this arrangement, an output frequency signal is generated which is not phase related to the clock frequency, but synchronised with the successive occasions on which the integrator charging slope exceeds the threshold level of the comparator. Between each such occasion, a constant current and duration discharge pulse is applied to the integrator to produce the discharge slope providing dual slope operation. It can be seen that, with a constant input voltage signal, the periods between successive such occasions providing an output indication from the comparator, are constant. Thus, the output frequency signal of the converter, has a constant frequency which is not phase related to the clock frequency. Nevertheless, the discharge pulses are accurately defined in duration by the clock pulses. 
     Normally, the comparator means provides a pulse as each said output indication, and thus the frequency signal output means may include simply an electrical connection from the output of the comparator means to the output terminal, or one of the output terminals, so that said frequency signal on said terminal is constituted by the successive output pulses of the comparator means. Normally, the comparator means operates to initiate a pulse as each said output indication, i.e. the output state of the comparator means switches over as the integrator output exceeds the threshold. However, the duration of the pulses from the comparator means are not normally constant depending on the mechanism for switching the comparator means back again. Preferably, therefore, the frequency signal output means includes a flip-flop clocked by said successive output pulses of the comparator means to switch between its output states in response to the initiations of said output pulses, the flip-flop having its output connected to the output terminal or one of the output terminals to provide said frequency signal on said output terminal. Then, the frequency signal comprises a unity mark/space ratio wave form at a frequency equal to half the comparator output pulse rate. 
     Where it is desirable to employ as the output frequency signal, a signal at the same frequency as the comparator output pulses, the frequency signal output means may include pulse stretching means to feed to the output terminal pulses initiated with the initiation of said pulses from the comparator means and having durations between a minimum of one clock period and a maximum of two clock periods. 
     Conveniently, the comparator means comprises a Schmitt trigger circuit having a predetermined hysteresis between switching thresholds, one said threshold providing said predetermined threshold level. With this arrangement, it is important that the discharge slope of the integrator output signal brings the integrator output below the other said threshold of the Schmitt trigger to ensure that the trigger circuit switches back prior to the next charging slope. This can provide a limitation on the dynamic range of the converter. 
     To improve the dynamic range, the converter may include a mode switch arranged to connect the integrator output signal to the Schmitt trigger circuit during each said charging slope and to connect a source of voltage beyond the other of said Schmitt thresholds to the Schmitt trigger circuit during each said discharge pulse to ensure return switching of the Schmitt trigger circuit ready for the next charging slope. 
     The integrator may comprise an operational amplifier having the input voltage fed to its non-inverting input, a capacitor interconnecting the output of the amplifier and its inverting input, a resistor connected to the inverting input and a switch arranged to connect the resistor in series selectively to one of two different reference voltage sources, the discharge pulse generating means controlling the switch to connect the resistor alternately to one reference voltage source to effect the charging slope of the integrator output signal and to the other said source for said constant duration to provide each said discharge pulse. An operational amplifier can also be arranged to provide an inverting integrator by connecting the capacitor and resistor of the non-inverting arrangement described above instead to the inverting input of the amplifier, the non-inverting input then being connected to ground. Then the input voltage to the integrator is also fed via a further series resistor to the inverting input. A drawback of this inverting arrangement of an operational amplifier integrator is that the output signal is dependent on any variation in the values of the two resistors arising, for example, from temperature drift. 
     On the other hand, the non-inverting arrangement of an operational amplifier integrator has the drawback that the output signal includes a term proportional to the input voltage signal. This may not be important for input voltages which are very small compared to the output swing of the integrator. However, said comparator means may be arranged to be responsive directly to the input voltage to the non-inverting input of the amplifier to cancel out the effect of the component of the integrator output signal which is proportional to the input voltage. 
     The present invention also envisages a clock controlled frequency to voltage converter having an input terminal for an input frequency signal to the coverter comprising a train of pulses at said input frequency, a clock pulse source, control pulse generating means arranged to produce a control pulse of constant duration determined by clock pulses from the clock pulse source, following the first pulse of said input train since the preceding control pulse, and integrating means including a capacitor, a resistor and a switch controlled by the control pulses to switch the capacitor via the resistor alternately between a reference voltage and ground, whereby the voltage across the capacitor is the reference voltage proportioned in accordance with the mark/space ratio of said control pulses. With this arrangement, each pulse of the input frequency signal produces a control pulse at a time and having a duration determined by the clock pulses. It can be seen that the maximum input frequency is equal to half the clock pulse frequency. With some arrangements of this frequency to voltage converter, input frequencies in excess of the above maximum frequency may cause the output voltage across the capacitor to fall below the maximum voltage corresponding to an input frequency equal to half of the clock frequency. It can be seen that normally each said control pulse has a duration equal to a single pulse period of the clock pulses and the maximum rate of said control pulses is half the clock pulse rate. In order to ensure that the output voltage of the converter is constant for all input frequencies in excess of the maximum, said control pulse generating means may be arranged to produce a subsequent control pulse in response to one or more pulses of said input train received during the preceding control pulse. 
     Examples of the present invention will now be described with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block schematic diagram of a voltage to frequency converter embodying the present invention; 
     FIG. 2 is a timing diagram illustrating the operation of the circuit of FIG. 1; 
     FIG. 3 is a further timing diagram illustrating how the converter of FIG. 1 can miss output pulses for input voltages in excess of a predetermined maximum; 
     FIG. 4 is a block schematic diagram illustrating a modification of the circuit of FIG. 1 which increases the dynamic range of the circuit; 
     FIG. 5 is a timing diagram illustrating the operation of the modified circuit of FIG. 4; 
     FIG. 6 is a schematic circuit diagram of an inverting summing integrator as an alternative to the non-inverting integrator shown in FIGS. 1 and 4; 
     FIGS. 7a and 7b are block schematic diagrams of alternative modifications to correct for errors in the output signal using a non-inverting integrator; 
     FIG. 8 is a block schematic diagram illustrating a pulse stretching arrangement to increase the minimum length of output pulses from the converter of FIGS. 1 or 4; 
     FIG. 9 is a block schematic diagram illustrating a frequency to voltage converter embodying the present invention; 
     FIG. 10 is a timing diagram illustrating the operation of the frequency to voltage converter of FIG. 9 with two different input frequencies; 
     FIG. 11 is a block schematic diagram illustrating a modified version of the frequency to voltage converter of FIG. 9; and 
     FIG. 12 is a timing diagram illustrating the operation of the converter of FIG. 11. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, an input voltage signal Vin is applied to the non-inverting input of an operational amplifier 10 connected as an integrator. A capacitor C is connected between the output of the amplifier 10 and the inverting input and a resistor R is connected from the inverting input to ground via a switch 11. It will be appreciated that with this circuit arrangement and with the switch 11 connecting the resistor R to ground as shown in FIG. 1, the output signal V 1  from the amplifier 10 comprises a positive going ramp having a slope proportional to Vin. 
     The integrator output signal from the amplifier 10 is fed to a Schmitt trigger 12. The output signal from the Schmitt trigger switches to the &#34;high&#34; state as the integrator output exceeds the upper threshold voltage of the Schmitt. The Schmitt output V 2  is fed to the D input of a D-type flip-flop 13 which is clocked by a precision clock signal on a line 14. The D-type flip-flop 13 operates so that its Q output switches to a logic &#34;1&#34; on the first clock pulse after the signal on its D input goes high. The Q output of the flip-flop 13 is used to control the switch 11 to operate the switch to connect the resistor R to a source of reference voltage Vref so long as the Q output is at a logic &#34;1&#34;. 
     When the resistor R is connected to the reference voltage Vref, the output of the amplifier 10 ramps downwards with a downward slope dependent on the relative values of Vref and Vin. This dual slope operation of the integrator is established in the art. The Q output of the flip-flop 13 remains at a logic &#34;1&#34; until the immediately following clock pulse whereupon it reverts to a logic &#34;0&#34;. Thus, it can be seen that the switch 11 is switched to the reference voltage for a precise period of time corresponding to one clock pulse period. Thus, the discharge pulse applied to the integrator to produce the down ramp has an accurately defined duration determined by the precision of the clock pulses supplied on line 14. 
     Referring to FIG. 2, the sequential operation of the circuit as the output signal of the amplifier 10 repeatedly exceeds an upper threshold V H  of the Schmitt trigger 12 is illustrated. The uppermost wave form in FIG. 2 shows the output V 1  of the amplifier 10. During the positive going slope of the output, the charging slope, V 1  increases at the rate Vin/RC. On the other hand the negative going slope of the amplifier output during the discharge pulses when the switch 11 is connected to Vref (Vr), is ##EQU1## 
     If the clock frequency is f c , the down slope of V 1  has a duration accurately defined as 1/f c . Thus the voltage drop of V 1  during each down slope is equal to ##EQU2## 
     On the other hand, if the total time during which V 1  is increasing between successive transitions of upper threshold V H  is taken to be t, then the total increase in voltage between successive threshold transitions equals ##EQU3## which is equal to ##EQU4## in order to provide a continuous wave form. 
     Thus, ##EQU5## Therefore, the total period between successive transitions of the upper threshold V H  is ##EQU6## 
     It is apparent therefore that the threshold crossings are accurately periodic and are not related in phase to the clock frequency f c . 
     The third wave form shown in FIG. 2 is the output signal V 2  of the Schmitt trigger 12. The output signal switches to a high state as V 1  exceeds the upper threshold V H  of the Schmitt trigger and returns to a low state when V 1  crosses a lower switching threshold V L  of the Schmitt during the downward slope. The hysteresis between V H  and V L  is normal for Schmitt trigger circuits and is useful in eliminating the jitter that can be experienced with an ordinary comparator resulting from noise on the ramp signal V 1 . Such jitter could produce errors by causing erroneous clocking of the flip-flop 13. 
     It can be seen therefore that the leading edges of the pulses produced by the Schmitt trigger 12 (V 2 ) are at a frequency f 0  equal to ##EQU7## f 0  is in no way phase related with the clock frequency f c . The output of the Schmitt trigger 12 is supplied, in the example of FIG. 1, on a line 15 to an output terminal 16 for use as the frequency signal output of the converter. 
     It can be seen however that the duration of the pulses of V 2  are not constant. Desirably, therefore, the voltage V 2  is supplied as the clock input to a toggle flip-flop 17 producing an output signal V 3  on a line 18 to a second output terminal 19. The wave form of V 3  is shown in FIG. 2 and has a frequency f 0  &#39; equal to f 0  /2. However, V 3  has a unity mark/space ratio as illustrated. 
     The advantages of the voltage to frequency converter shown in FIG. 1 include the following: 
     1. The output frequency is independent, rather than a sub-harmonic of the clock. 
     2. The output frequency is dynamically correct, settling within a cycle or so, and thus no averaging need take place. 
     3. The individual period of the output signal is accurate, as is the time between one output transition and the next. 
     4. Accuracy of the converter, neglecting offset voltages and currents in the integrator amplifier 10, is dependent on the accuracy of the reference voltage Vr (which can be derived from a highly stable band gap reference source); the precision of the clock period and frequency, which can be based on a crystal oscillator giving great accuracy and stability. 
     In another arrangement, the output frequency f 0  &#39; can be counted over a period of time also determined by the clock frequency f c , thereby giving a direct digital output in which any clock instability cancels out. 
     It can be seen that the down ramp of V 1  must pass the lower threshold voltage V L  of the Schmitt 12 in the time 1/f c  to avoid errors. This provides a limitation on the dynamic range of the converter: ##EQU8## where VH is the maximum hysteresis voltage of the Schmitt trigger between switching thresholds. 
     FIG. 3 is a timing diagram illustrating what happens if Vin exceeds the above limitation. On some occasions, the down ramp of V 1  does not reach the lower threshold V L  in the time 1/f c  so that the D input to the flip-flop 13 is still high for the next clock pulse on line 14 causing the Q output of the flip-flop to remain at a logic &#34;1&#34;. Thus, the down ramp of V 1  continues for a second clock period with the result that the period between successive transitions of V 1  with the upper threshold V H  do not remain constant. 
     The hysteresis of the Schmitt trigger is desirable in providing some noise immunity as explained previously. However, one method of reducing the dynamic range limitation mentioned above is to minimize this hysteresis. 
     Alternatively, the effect of the hysteresis band can be removed logically by a modification to the circuitry as illustrated in FIG. 4. A mode change switch 21 is included between the output of the integrator 10 and the Schmitt trigger 12. The switch 21 is arranged to connect the output of the amplifier 10 to the Schmitt trigger 12 only when the Q output of the flip-flop 13 is at a logic &#34;0&#34;, and to connect the input of the trigger 12 to ground when the Q output of the flip-flop 13 is at a logic &#34;1&#34;. The effect of this modification is as illustrated in FIG. 5 which shows that the Schmitt trigger 12 is forced to revert to a low output state as soon as the next clock pulse on line 14 toggles the flip-flop 13 causing the Q output to go to logic &#34;1&#34;. This ensures that the Q output remains at a logic &#34;1&#34; only for one clock period even if the down ramp of the integrator output has not reached the lower switching threshold of the Schmitt 12. 
     With this modification, it can be seen that the output frequency f O  of the converter cleanly limits at ##EQU9## Thus, the dynamic range limitation is ##EQU10## 
     A further ranging improvement to the converter may be provided by implementing the integrator as an inverting summing integrator as illustrated in FIG. 6. In this arrangement an amplifier 25 has its non-inverting input connected to ground via a resistor 26. The input voltage to the converter is supplied to the inverting input via a series resistor R s . Capacitor C is connected between the output of the amplifier and the inverting input and the inverting input is also connected via a series resistance R r  to the switch 11 which operates in the same manner as the circuits of FIGS. 1 and 4. The output of the amplifier 25 is supplied to a Schmitt trigger via a mode change switch 21 as before. 
     It can then be shown that the output frequency of the converter ##EQU11## 
     Input voltage flexibility is thereby enhanced, albeit at the expense of two extra components in the circuit. Further the transfer equation of the converter is degraded by inaccuracies and temperature drift resulting from the factor R s  /R r . It should be noted also that the input signal must now be of opposite polarity. 
     The circuit of FIG. 6 can readily be modified to accommodate a bi-polarity input voltage range. Then, a further reference voltage V x  is connected to the inverting input via a further resistor 27 to provide a desired offset bias to the integrator. 
     Although the non-inverting integrator arrangement, as shown in FIGS. 1 and 4, is desirable in avoiding errors arising from temperature drift and inaccuracies in the resistors used for the inverting type integrator, the non-inverting type has the disadvantage that its output signal includes a factor directly proportional to the input voltage. Thus, the output voltage of the non-inverting integrator is equal to ##EQU12## 
     In many cases, since the factor 1/RC is much greater than 1, the influence of the Vin term in the output of the integrator is insignificant. However, when this is not the case, the effect of the term can be compensated for. 
     FIGS. 7a and 7b illustrate two arrangements for compensating non-inverting integrators. In FIG. 7a, the input voltage to the integrator is fed forward to a unity gain amplifier 30 connected as an analogue subtractor. The amplifier 30, subtracts Vin from the output of the integrator to produce a compensated output fed to the Schmitt trigger in the usual way. 
     In FIG. 7b, there is illustrated an arrangement using a Schmitt trigger 31 which has an externally variable upper threshold. In this arrangement, the input voltage to the integrator is fed forward to the Schmitt trigger 31 to control the upper threshold again to compensate for the Vin term in the integrator output. 
     As mentioned above, an output f O  &#39; of the converter can have a unit mark/space ratio. However, in some arrangements, it may be necessary to employ the output f O  in which the pulses are of varying duration. It may then be desirable to ensure that the pulses of the f O  signal have a predetermined minimum duration, i.e. that the pulses are stretched if necessary. FIG. 8 illustrates an appropriate circuit for stretching the pulses in the signal V 2 . The output of the Schmitt trigger V 2  is then supplied on a line 41 to the SET input of a flip-flop 40 so that the Q output of the flip-flop is set to a logic &#34;1&#34; as soon as the Schmitt output goes high. The flip-flop 40 is reset by a signal applied to its clock input on a line 42 from the Q output of the flip-flop 13, so that the Q output of the flip-flop 40 remains at a logic &#34;1&#34; until after the discharge pulse applied to the integrator amplifier 10 as determined by the flip-flop 13. In this way, the output pulses from the flip-flop 40 on line 43 supplied to an output terminal 44 have a minimum duration equal to 1/f c  and a maximum duration equal to 2/f c . 
     FIG. 9 illustrates a frequency to voltage converter which can resynchronise an unsynchronised input frequency signal f in  with a local precision clock signal f c2 . FIG. 10 shows a timing diagram illustrating the operation of this converter of FIG. 9 at two different input frequencies f in . The pulse output signal from output Q 2  of a flip-flop 46 can be seen to have a duration 1/f c2  and t occur once per 1/f in . The limitation is that f in  is not greater than f c  /2. This limit applies because it takes two clock periods to process each f in  pulse. The averaging network including resistor capacitor RC and switch 47 produces an average output V 0  on terminal 48 equal to ##EQU13## 
     In the arrangement illustrated in FIG. 9, when f in  exceeds f c  /2, the system starts to miss input pulses and the response of the converter thus appears to be re-entrant. A solution is illustrated in FIG. 11 which includes a positive edge input monostable 50 connecting the Q 2  output of flip-flop 46 to the reset terminal of flip-flop 45. This permits the flip-flop 45 to be reset promptly after the rising edge of pulses from Q 2  of the flip-flop 46. This is illustrated in the timing diagram shown in FIG. 12. Thus, flip-flop 45 can now respond to f in  pulses even whilst Q 2  is high. 
     A mode change switch 49 interconnects the Q 1  output of flip-flop 45 to the D 2  input of flip-flop 46. The mode change switch 49 is arranged to connect Q 1  to D 2  when Q 2  is at a logic &#34;0&#34;, and to connect D 2  to ground when Q 2  is a logic &#34;1&#34;. Thus, flip-flop 46 is forced to toggle if the pulse rate on f in  is high on each rising edge of the clock pulse f c2 . 
     The result of these modifications is to ensure that the converter cleanly limits ##EQU14## for input conditions of ##EQU15## 
     It can be seen that the voltage to frequency converter illustrated and described above and the above mentioned frequency to voltage converter may be used together, assuming the f 0  output of the voltage to frequency converter, such that where ##EQU16## 
     A further advantage of the frequency to voltage converter of FIG. 9 is that a divider can be included in the clock line to flip-flop 46 effectively to provide digital gain. Thus, ##EQU17## where n is the divisor on f c2 .