Abstract:
A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

Description:
This application is a continuation of application Ser. No. 366,208 filed June 12, 1989; which is a continuation of Ser. No. 220,879 filed June 21, 1988; which is a continuation of Ser. No. 06/794,829, filed Nov. 4, 1985; all now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory, in particular, to an input circuit which receives an external control signal such as a WE (write enable bar) signal. 
     2. Description of the Related Art 
     A semiconductor memory device provides an input circuit which is connected to a reference potential line connectable to an external power source and which provides a MOS transistor receiving an external control signal such as a WE (a write enable bar) signal at a TTL level. The input circuit outputs an inverted MOS level signal in accordance with a high level or a low level of the external control signal. The semiconductor memory device further provides an output stage transistor which is connected to the reference potential line and which generates a low or high level output by turning the output stage to ON. 
     The external control signal of the semiconductor memory device, signals such as RAS (Row address strobe), CAS (Column address strobe), OEand WE having a TTL level, are used for controlling the mode or timing of operation of the internal circuit in the device. Memory cells are accessed by receiving these signals and address signals, and read and write operations are carried out for the memory cells. The present invention is concerned with the input circuit for these external control signals, particularly the WE signal. This input circuit, which receives the TTL level signal supplied to an input terminal, has a high voltage level of 2.4 V or more and a low voltage level of 0.8 V or less and converts the same to a MOS level having a high level power source voltage V CC  (5 V) or a low level power source voltage V SS  (0 V). The input circuit activates a clock generator circuit for carrying out a specific operation mode by signals output after the level is converted. 
     When, for example, the WE signal is at a H (high) level, the memory is in a read-out mode, and data in the memory cell selected by address signals is read out externally. 
     In the circuit as mentioned above, when the output stage transistor is turned ON to make the output level low or high, a comparatively large current flows via the output stage transistor to or from the reference potential line. As the wire for forming the reference potential line has a resistance, then the potential level of the reference potential line rises or falls when the large current flows via the output stage transistor thereto or therefrom. 
     On the other hand, the TTL level input signal, for example the WE signal, has a constant level with respect to the external ground level, that is, lower than 0.8 V for the low level and higher than 2.4 V for the high level with reference to the external ground level. Thus, when the reference potential level inside the device, which should be held at the ground level, rises due to the large current at the output stage, the input stage transistor receiving an input of the TTL high level may not turn ON, so that the input circuit sometimes cannot output a low level output, as explained in detail hereinafter. When the output of the input circuit is not at the L level, a writing mode is operative, and it is possible for the writing circuit inside the device to operate and the memory carry out a write operation. Further, the writing circuit provides a latch function, and thus when the H level output is initially generated, it is latched and a writing error may occur. 
     When the input logic level is defined with respect to the reference potential level supplied by the high level power source voltage, unlike the above case, the falling of the potential at the reference potential line inside the device accompanied by the high level output at the output stage may cause a similar malfunction at the input stage. 
     OBJECT AND SUMMARY OF THE INVENTION 
     An object of the present invention is to remove the above-mentioned drawbacks and to prevent malfunction of the input circuit even when the potential of the reference potential line inside the device rises or falls due to the output current. 
     The above-mentioned object can be achieved by providing a semiconductor memory device connected to a power source including a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. An output circuit has an external output terminal which is connected to the reference potential line. The output current generates an output to the external output terminal. An inhibiting circuit inhibiting a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes. 
     Further features and advantages of the present invention will be apparent from the ensuring description with reference to the accompanying drawings to which, however, the scope of the invention is in no way limited. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the semiconductor memory device to which the present invention is applied; 
     FIGS. 2A and 2B are diagrams of an example of a conventional circuit; 
     FIG. 3 is a diagram showing waveforms for explaining the operation of the conventional circuit shown in FIG. 2; 
     FIG. 4 is a diagram showing one embodiment of the circuit according to the present invention; 
     FIG. 5 is a diagram showing an embodiment of the circuit for generating a signal φ D  used in the circuit shown in FIG. 4; and 
     FIGS. 6 and 7 are diagrams showing waveforms explaining the operation of the circuit shown in FIGS. 4 and 5. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram of the semiconductor memory device to which the present invention is applied. In FIG. 1, RAS denotes a raw address strobe, CAS a column address strobe, A 0  to A N  address input terminals, WE a write enable bar signal, D IN  a data input, and D OUT  a data output. Further, reference numerals 1 and 2 designate clock generators, reference numeral 3 designates address buffers, reference numerals 4 and 5 designate a column decoder and a sense amplifier respectively, reference numeral 6 designates a row decoder, reference numeral 7 designates write clock generators, reference numeral 8 designates a data-in buffer, reference numeral 9 designates a data-out buffer, reference numeral 10 designates a storage cell. The clock generator 1 generates a clock for operating the sense amplifier 5 and the row decoder 6, and the clock generator 2 generates a clock for operating the column decoder 4, the write clock generator 7, and the data-out buffer 9. The semiconductor memory device receives external control signals such as RAS, CAS, and WE, and the storage cell 10 is accessed and a read or write operation is carried out for the cell. 
     The present invention is explained below by way of an example wherein the input circuit of the WE signal is provided with a means for preventing the aforesaid malfunction in accordance with the present invention. This input circuit is included in the write clock generator 7 and receives the WE signal having a TTL level, that is, the high level thereof is 2.4 V or more and the low level thereof is 0.8 V or lower. In the input circuit, this TTL level is converted to a MOS level signal, that is, having a high level that is the same as that of the high power source V CC  (5 V), a low level that is the same as that of the low power source V SS  (0), and the write clock generator 7 is operated by this converted output. 
     When the WE signal is at a H (high) level, the memory is in the read-out mode, and data in the memory cell selected by address signals is read out externally. FIG. 2A shows an output stage of the data output buffer and an input circuit of the WE signal, wherein 21 designates the input circuit and 22 designated the output stage. These circuits are connected to the high potential line l 1  of the power source and the low potential line l 2  of the power source, the latter used as a reference potential line in a TTL logic level system. The input circuit includes a depletion type MOS transistor Q 1 , in which a gate and a source are short-circuited, and an enhancement type MOS transistor Q 2  connected to the transistor Q 1  in series. The input circuit is formed as an inverter having a series-connected point N 1  as an output terminal. The input WE signal enters a gate of the transistor Q 2 , and when the input signal is at a H level and exceeds the threshold value of the transistor Q 2 , the transistor Q 2  turns ON and the output, that is, the level at the node N 1  becomes a L level (V SS ). When the input signal is a low level and below the threshold level of the transistor Q 2 , the transistor Q 2  turns OFF, and the output becomes a H level (V CC ). This threshold level is set at an intermediate level between the TTL low and high levels, for example, at 1.6 V. 
     The output stage 22 includes an output circuit having enhancement type MOS transistors Q 11 , Q 12  connected in series, and a series-connected point used as an output terminal D out  and an output drive circuit 23 thereof. The output drive circuit is formed as shown in FIG. 2B. In FIG. 2B, transistors Q 13  to Q 18  are MOS transistors, and φ S  and φ R  are set and reset clocks for operating the drive circuit 23. Cell data DB and DB are supplied from the sense amplifier 5 (shown in FIG. 1) to the gate of the transistors Q 12  and Q 15  respectively. In FIG. 2B, the transistors Q 17  and Q 18  for forming a latch and reset transistors Q 14  and Q 16  are provided so that the circuit is operated in a stabilized condition, therefore these transistors are not always necessary. 
     When the set clock φ S  rises and the cell data is &#34;1&#34;, that is, DB=high and DB=low, the signal at node N 11  between the transistors Q 13  and Q 14  becomes H (high) level and the signal at node N 12  between the transistors Q 15  and Q 16  becomes L (low) level. These signal levels at nodes N 11  and N 12  are maintained until the latch is reset by the reset transistors Q 14  and Q 16  by reset clock φ R . As a result, the transistor Q 11  turns ON and the transistor Q 12  turns OFF, so that the output D out  (herein the node and its level are shown by the same symbol) is an H level (V CC ). When the data in the cell is &#34;0&#34; and the clock φ S  rises, the output signal N 12  of the driving circuit 22 becomes H, N 11  becomes L, the transistor Q 11  turns OFF, and the transistor Q 12  turns ON, so that the output D out  becomes a L level (V SS ). Thus, the output drive circuit 23 receives the data read out by the clock signal φ S  and holds the data until the reset signal φ R  is received, and continuously drives the output circuit. 
     When the transistor Q 12  turns ON and the output D out  becomes L, the current flows along the path D out , Q 12 , and V SS . The wire of the power source includes a resistance, shown by R in FIG. 2A. When the transistor Q 12  at the output stage turns ON, the current flowing along the path mentioned above is comparatively large, and the phenomenon occurs whereby the level at the wiring l 2  of V SS  rises from V 22 , that is, 0 V, by the resistance mentioned above. V SS1  in FIG. 3 shows this rise in the level of the wiring of V SS . On the other hand, the WE signal may be as high as slightly lower than 0.8 V when it indicates a L level (V IL ) and may be as low as slightly higher than 2.4 V when it indicates a H level (V IH ), in the TTL logic level system. The input transistor Q 2  can be turned on only when the difference between the input level at its gate and the internal V SS  level applied to its source exceeds the threshold value of for example, 1.6 V. Then, if the level at the wiring l 2  of V SS  rises, the transistor Q 2  does not turn ON, even when the WE signal is a the H level, so that the problem occurs wherein the node N 1  does not generate an L output. When the output N 1  of the input circuit is not L level, that is, at an H level, it is in the writing mode, and it is possible for the writing circuit in the device to operate and the memory to carry out the writing operation. Further, the writing circuit (not shown in the drawing) provides a latch function, so that, when the H level output is initially generated, this it is latched and an writing error may occur. 
     The present invention will be explained in reference to FIGS. 4 to 7. As shown in FIG. 4, Q 1  and Q 2  are the MOS transistors in the input circuit as shown in FIG. 2A. The WE signal applied to the terminal pin of the memory chip is input to the gate of the transistor Q 2 . The output of the node N 1  is applied to a clock pulse generator circuit 31 in the writing system so that various clocks are generated and these are input to the writing circuit 32. RST designates a reset signal for stopping the generation of the clock in the circuit 31. In the present invention, a transistor Q 3  is connected in parallel to the transistor Q 2  in the input circuit 21, and a signal is applied to the gate of this enhancement type MOS transistor Q 3 . The signal φ D  is, ○1  the same as the input signal φ S  of the driving circuit 23, or  ○2 , the signal which rises together with φ S  and fails thereafter (at the time when the rise of the wiring l 2  of the power source is finished). Two kinds of memory exist, that is, the first memory exists when the output stage transistor Q 12  or Q 11  is turned ON (the state which the output is held), the WE signal will not be received even if the WE signal is input (or varied), and only when both the output transistors Q 11  and Q 12  are turned OFF, will the WE signal be received; the second memory exists even when the output stage transistor Q 12  or Q 11  is turned ON, the WE signal is received and the write operation becomes possible. The former is applied with ○1 , and the latter with  ○2  mentioned above. FIG. 5 shows the circuit for generating the φ D  of  ○2  mentioned above. 
     In FIG. 5, Q 21  ˜Q 31  are MOS transistor, and these transistors are connected between the power sources V CC  and V SS . φ S  and Q R  are a set signal and a reset signal supplied to the driving circuit 23 as mentioned above, and in the present circuit, they are supplied to the transistors Q 24  and Q 26  and the transistors Q 21 , Q 27 , and Q 28 . 
     The operation will be explained by referring to FIG. 6. When the signal φ S  rises and φ R  falls, the output D out  falls, as already mentioned. Until that time, as the signal φ R  is H and φ S  is L, the transistors Q 21 , Q 27  and Q 28  are turned ON, the transistors Q 26  and Q 29  are turned OFF, the transistor Q 31  is turned ON, the signal φ 3  is L, and the transistors Q 22  and Q 25  are turned OFF. Further, because the transistor Q 23  is turned ON, the transistor Q 24  is turned ON, and because the signal φ S  is L, the signal φ D  is also L. The capacitor C is charged up from the power source V CC  at the interconnection node between transistors Q 28  and Q 29  as the positive side. 
     In this state, when the signal φ S  rises and the signal φ R  falls, the signal φ D  rises together with the signal φ S  via the transistor Q 24 , which is turned ON. Further, the transistors Q 27  and Q 28  turn OFF and the transistor Q 26  turns ON, so that the potential at a node φ 1  rises. Accordingly, the transistor Q 31  is maintained at in an ON state until the transistor Q 29  turns ON and the signal φ 3  is also maintained at the L level. When the transistor Q 29  turns ON, the potential at a node φ 2  falls, the transistor Q 31  then turns OFF, and the potential at a node φ 3  rises. When the signal φ 3  rises, the transistors Q 22  and Q 25  turn ON, the potential at a node φ 4  falls, and the signal φ D  also falls. Thus, the signal φ D  rises together with the rise of the signal φ S , then falls so that a temporarily generated pulse is formed. The generating period of this pulse can be set by the capacity of the capacitor C. 
     FIG. 7 is similar to FIG. 6, and shows the level change of the output D OUT , V SS , etc., and that the width of the signal φ D  is selected to be larger than the period of the level change V SS1 . 
     Since the level change at the V SS  line l 2  is also applied to the other circuit of the memory, it is possible to provide the inhibiting circuit as described above to other input circuits which possibly suffer from such level change and generate malfunctions. 
     As mentioned above, according to the present invention, malfunction of the external control signal input circuit due to the level change at the V SS  wiring can be prevented so as to contribute to an improvement of the reliability of the MOS memory.