Abstract:
A dual-frequency hopping device and method for a frequency synthesizer. An intermediate local oscillating frequency is decreased in the unit of a first frequency by a prescribed number of times as a channel is sequentially increased, to output an intermediate local oscillating frequency signal. A radio local oscillating frequency is increased by one level in the unit of a second frequency when the intermediate local oscillating frequency is decreased by the prescribed number of times, to output a radio local oscillating frequency signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to mobile communication systems, and in particular, to a device and method for providing a fast lock time by hopping an intermediate frequency and a radio frequency. 
     2. Description of the Related Art 
     In general, radio communication systems include a frequency synthesizer having a phase locked loop (PLL). In a GMPCS (Global Mobile Personal Communication by Satellite) system, such as, iridium, global star and ICO (Intermediate Circuit Orbit), for example, the frequency synthesizer uses a dual frequency band frequency synthesizer. The frequency synthesizer used in the GMPCS system has a dual PLL which generates a radio local oscillating frequency and an intermediate local oscillating frequency. These two frequencies are used to convert an input signal frequency into a desired carrier frequency fc. 
     A frequency synthesizer typically comprises a reference oscillator, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and a programmable counter. 
     In the dual PLL, a fractional N counter is used for the radio local oscillating frequency, and an integer N counter is used for the intermediate local oscillating frequency. The integer N counter consists of P (prescaler), B and A (programmable) counters satisfying the following equation N=P×B+A (where P, B and A are all integers). The fractional N counter includes an F (fractional) counter in addition to the P, B and A counters, satisfying the following equation N=P×B+A+F (where P, B and A are all integers, P, A, and F is a fractional number less than 1). 
     A frequency synthesizer having a general dual PLL construction uses a frequency division multiple access (FDMA) technique where each user is assigned a different frequency. To assign a frequency per channel (i.e., user) in the FDMA technique, the integer N counter and fractional N counter operate by 24-bit control data provided from a baseband circuit. The integer N counter provides a uniform frequency without frequency hopping under control of the baseband circuit to output one intermediate local oscillating frequency. The fractional N counter outputs a radio local oscillating frequency hopping in increments of a prescribed frequency according to the channel. 
     For example, in a transmitter of an ICO system, an intermediate local oscillating frequency of 430.0 MHZ is demultiplied by ½ and thus a 215.0 MHZ signal is applied to a mixer as an input representing the uniform frequency without frequency hopping. One of a number of radio local oscillating frequencies of (2200+0.025×n) MHZ are spaced at 25 kHz increments is also applied to the mixer as another input. Therefore, the output of the mixer, that is, an ICO transmitting frequency is the difference of the two inputs, namely, {(2200+0.025×n)−215}MHZ=(1985+0.025×n) MHZ, where n is an integral number, i.e., 1, 2, 3, 4, . . . , its bandwidth being 25 KHz. In a receiver of the ICO, the intermediate local oscillating frequency is preferably fixed at 456.0 MHZ and the radio local oscillating frequency is sequentially incremented (or hopped) in units of 25 KHz. 
     For a GMPCS system, the radio local oscillating frequency should be some multiple of 25 KHz because the frequency bandwidth of the GMPCS system is 25 KHz. If the radio local oscillating frequency is a multiple of 25 KHz, a phase detector of a PLL used for radio local oscillation should also use 25 KHz as a comparison frequency. Since the PLL used for radio local oscillation employs a fractional N counter with modulus−16, the maximum comparison frequency of the phase detector is 400 KHz (=25 KHz×16). The comparison frequency is an important factor in determining a lock time in designing a system, whereby the lock time becomes faster as the comparison frequency is increased. Generally, the GMPCS system has 1199 channels and a demanded lock time of 350 Fs. The more channels the system has, the faster the demanded lock time. A high comparison frequency is desirable to obtain a fast lock time. 
     As described above, it is difficult to flexibly change the comparison frequency to a desired frequency band (i.e., higher frequency), so it is impossible to achieve a faster lock time. Namely, since the intermediate local oscillating frequency is fixed, the comparison frequency range is limited to, for example, 25 KHz (mod. 16/16), 50 KHz (mod. 8/16), 100 KHz (mod. 4/16) and 400 KHz (mod.1/16). Also, the lock time and phase noise are influenced by the comparison frequency. However, since the range of generating the comparison frequency is restricted, it is difficult to provide a fast lock time. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a dual frequency hopping device and method for a frequency synthesizer, in which an intermediate local oscillating frequency hops per channel in increments defined by a first prescribed frequency, and a radio local oscillating frequency hops in increments defined by a second prescribed frequency only after the intermediate local oscillating frequency reaches a target frequency, thereby fully utilizing an RF channel band. 
     In accordance with one embodiment of the present invention, a dual-frequency hopping method for a frequency synthesizer having a dual phase locked loop includes the steps of decreasing an intermediate local oscillating frequency in increments defined by a first prescribed frequency a prescribed number of times as a channel is sequentially increased, to output an intermediate local oscillating frequency signal, and increasing a radio local oscillating frequency by one level in units of a second prescribed frequency after the intermediate local oscillating frequency has been decreased the prescribed number of times, to output a radio local oscillating frequency signal. 
     In accordance with a second embodiment of the present invention, a dual-frequency hopping device for a frequency synthesizer having a baseband processor and a reference frequency generator are provided for generating a reference frequency signal under control of the baseband processor. The dual-frequency hopping device further includes an intermediate frequency local oscillator for demultiplying the reference frequency signal and decreasing an intermediate local oscillating frequency a prescribed number of times in increments of a first prescribed frequency as a channel is sequentially increased, and a radio frequency local oscillator for demultiplying the reference frequency and increasing a radio local oscillating frequency in increments of a second prescribed frequency after the intermediate local oscillating frequency has been decreased the prescribed number of times. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference numerals designate like or corresponding parts throughout several views, and in which: 
     FIG. 1 is a block diagram of an RF circuit to which the present invention is applicable; 
     FIG. 2 is a block diagram of a frequency synthesizer according to a first embodiment of the present invention; 
     FIG. 3 is a diagram showing a frequency plan according to the first embodiment of the present invention; 
     FIG. 4 is a block diagram of a frequency synthesizer according to a second embodiment of the present invention; and 
     FIG. 5 is a diagram showing a frequency plan according to the second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Preferred embodiments of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well known constructions or functions are not described in detail so as not to obscure the present invention. 
     A. First Embodiment 
     A description of a frequency receiving path of an RF circuit will be given with reference to FIG. 1. A common antenna is shown which requires the use of a duplexer  101  to provide isolation means for RF signals transmitted and received through the antenna. A low-noise amplifier  103  low-noise amplifies a received RF signal output from the duplexer  101 . The amplified signal then passes through a first receiving bandpass filter (BPF)  105  and the output of the BPF is mixed by a first mixer  107  with a first local oscillating radio frequency signal (RX RFLO) output from a frequency synthesizer  140  to output a first receiving intermediate frequency (RX 1st IF) signal. A second receiving BPF  109  bandpass filters the RX  1  ST IF signal. The RX 1 st  IF signal output from the second receiving BPF  109  is then amplified by a first receiving amplifier  110  and provided as a first input to a second mixer  111 . The second mixer  111  mixes the amplified RX 1 st  signal with a second local oscillating frequency signal output from a demultiplier  156  to output a baseband signal (i.e., a second receiving IF signal (RX 2nd IF) which is 13 MHZ in the GMPCS system. The baseband signal is supplied to an in-phase/quadrature (IQ) demodulator  117  via a third receiving BPF  113  and a second receiving amplifier  115 . The in-phase/quadrature demodulator  117  demodulates the baseband signal (RX 2 nd  IF) into in-phase data and quadrature data. 
     A baseband circuit  160  receives the in-phase data and quadrature data from the in-phase/quadrature demodulator  117  and provides in-phase data and quadrature data to an in-phase/quadrature modulator  119 . The baseband circuit  160  also supplies a 24-bit control signal (CS) to the frequency synthesizer  140  to determine a radio local oscillating frequency and intermediate local oscillating frequency of the frequency synthesizer  140 . 
     A description of a frequency transmitting path will now be given with reference to FIG.  1 . On a frequency transmitting path, the in-phase/quadrature modulator  119  modulates the prescribed in-phase data and quadrature data into a baseband signal and receives the second local oscillating frequency signal via a ½ demultiplier  157  to output a transmitting IF signal (TX IF). The transmitting IF signal is amplified by a first transmitting amplifier  121  and supplied to a third mixer  123 . The third mixer  123  mixes the amplified IF signal with the first local oscillating frequency signal to output a transmitting RF signal (TX fc) ranging from 1985.0225 MHZ to 2014.975 MHZ with a bandwidth of 25 KHz per channel. The RF signal is supplied to the duplexer  101  via a transmitting BPF  125 , a power amplifier  127  and a lowpass filter (LPF)  129 . The RF signal (TX fc) is isolated from a received RF signal by the duplexer  101  and transmitted via the antenna. 
     The frequency synthesizer  140  generates the first local oscillating frequency signal (RX RFLO) to be supplied to the first mixer  107  and the third mixer  123 , and further generates an intermediate (second) local oscillating frequency signal (RX IFLO) to be supplied to the second mixer  111  via the demultiplier  156  and to the in-phase/quadrature modulator  119  via the ½ demultiplier  157 . 
     The frequency synthesizer  140  includes a reference frequency generator  141 , an IF local oscillator  149  and an RF local oscillator  142 . In the embodiments described herein, the reference frequency generator  141  generating the reference frequency signal is a VCTCXO (Voltage Controlled Temperature Compensated Crystal Oscillator). The IF local oscillator  149  demultiplies the reference frequency signal and generates an intermediate local oscillating frequency signal, which hops at a small predefined frequency increment. The process of hopping the intermediate local oscillating frequency repeats as the channel is sequentially increased. The RF local oscillator  142  demultiplies the reference at a frequency signal and generates radio local oscillating frequency signal which hops at high frequency increments after the intermediate local oscillating frequency signal has hopped a prescribed number of times. This process is also repeated as the channel is sequentially increased. 
     FIG. 2 is a detailed block diagram of the frequency synthesizer  140  shown in FIG.  1 . The frequency values provided are exemplary and given with reference to a GMPCS system. 
     Referring to FIG. 2, a second demultiplier (1/R 1  demultiplier)  143 , a second phase detector  145 , a second loop filter (RF filter)  146 , an RF VCO  147 , and a second programmable counter (fractional N 1  counter)  148  constitute the RF local oscillator  142  shown in FIG.  1 . The second demultiplier  143  demultiplies the reference frequency signal supplied by the reference frequency generator  141  by 1/R 1  (where R 1  is 13 in the GMPCS system). The RF VCO  147  receives a predetermined signal and provides as output an RF signal, ranging from 2200.125 MHZ to 2230.0 MHZ during transmission and from 2385.125 MHZ to 2415.0 MHZ during reception. 
     The fractional N 1  counter  148  fractions or changes the oscillating frequency signal in units of 125 KHz under control of the baseband circuit  160 . The second loop filter  146  lowpass filters the output of the second phase detector  145  and determines a synchronization characteristic or response characteristic which represents the characteristic of the lock time and phase noise. The second phase detector  145  compares the phase of a signal output from the second demultiplier  143  with the phase of a signal output from the second programmable counter  148 . If these two phases are the same, the second phase detector  145  supplies a radio local oscillating frequency signal (TX RFLO) to the RF VCO  147  via the second loop filter  146 . If they are not the same phase, then there is no locking for the phase. 
     Also shown in FIG. 2 is a detailed block diagram of the IF local oscillator  149  shown in FIG.  1 . The IF local oscillator  149  shown in FIG. 1 is comprised of a first demultiplier (1/R 2  demultiplier)  150 , a first phase detector  151 , a first loop filter (IF filter)  152 , an IF VCO  153 , and a first programmable counter  154 . Its operation will be described below. 
     The first demultiplier  150  demultiplies the reference frequency signal by 1/R 2  (where R 2  is 260 in the GMPCS system). The IF VCO  153  receives a predetermined signal and outputs an IF signal. The first programmable counter  154  fractions the IF signal from the IF VCO  153  to a 50 KHz step under control of the baseband circuit  160 . The first loop filter  152  lowpass filters the output of the first phase detector  151  and determines a synchronization characteristic or response characteristic. The first loop filter  152  controls the IF VCO  153  so as to output the intermediate local oscillating frequency signal. The first phase detector  151  compares the phase of a signal output from the first demultiplier  150  with the phase of a signal output from the first programmable counter  154 . If these two phases are the same, the first phase detector  151  provides a corresponding intermediate local oscillating frequency to the IF VCO  153  via the first loop filter  152 . 
     The operation of the frequency synthesizer  140  of FIG. 1 for the first transmitting channel (TX Ch) will now be described with reference to FIGS. 2 and 3 for a GMPCS system. Reference will first be made to the upper half of FIG. 2 which describes the transmitting RF local oscillator portion of the frequency synthesizer  140 , comprising elements  143 - 148 . The reference frequency generator  141  generates a reference frequency signal of 13 MHZ in a GMPCS system which is demultiplied by a second demultiplier (1/R 1 )  143  to 1/13, that is, to a 1 MHZ signal. The 1 MHZ signal is applied as an input to the second phase detector  145 . The second input to the second phase detector  145  is supplied by the second programmable counter (1/N)  148 . That is, the RF VCO  147  outputs a transmitting radio local oscillating frequency signal (TX RFLO) at 2200.125 MHZ which is demultiplied by the second programmable counter  148  by a factor of 1/2200.125, that is, to a 1 MHZ signal. The 1 MHZ signal is applied as a second input to the second phase detector  145 . If there is no phase difference between the two inputs, the phase detector  145  outputs the TX RFLO signal of 2200.125 MHZ as the output of the RF VCO  147  via the second loop filter  146 . 
     The operation of the intermediate frequency (IF) local oscillator portion of the frequency synthesizer  140  comprising elements  150 - 154  for a GMPCS system will be provided. In FIG. 2, the 13 MHZ signal generated from the reference frequency generator  141  is demultiplied by the first demultiplier  150  by a factor of 1/260 to generate a 50 MHZ signal which is applied as a first input to the first phase detector  151 . Meanwhile, a transmitting intermediate local oscillating frequency (TX IFLO) signal of 430.2 MHZ output from the IF VCO  153  is demultiplied by the first programmable counter (1/N)  154  by a factor of 1/8604 to generate a 50 MHZ signal which is applied a second input to the first phase detector  151 . If there is no phase difference between the two inputs, the phase detector  151  outputs the TX IFLO signal as the output of the IF VCO  153  via the first loop filter  152 . 
     The above-described operation is identically applied to a receiving part. Here, a receiving intermediate local oscillating frequency (RX IFLO) signal output from the IF VCO  153  is demultiplied by the demultiplier  156  to ½ and then output as an intermediate local oscillating frequency (RX IFLO 2 ). 
     FIG. 3 illustrates the trequency plan for the radio local oscillating frequency and intermediate local oscillating frequency according to the channel. 
     As shown in the table of FIG. 3, the transmitting intermediate local oscillating frequency (TX IFLO) is different for each channel. That is, channels  1 - 6  transmit at the following TX IFLO frequencies: CH 1 =430.200 MHz; CH 2 =430.150 MHz; CH 3 =430.100 MHz; CH 4 =430.050 MHz; CH 5 =430.000 MHz; and CH 6 =430.200 MHz. As shown in the table, for channels  1 - 6 , the TX IFLO is initialized at 430.200 for channel  1 , and is then decremented four times by a 50 KHz step and then returns to the first channel frequency (i.e., 430.200) at the sixth channel. The corresponding transmitting radio local oscillating frequency (TX RFLO) is maintained at 2200.125 MHZ until the fifth channel and hops by a 125 KHz step to 2200.250 MHZ at the sixth channel. The frequency hopping method described is similarly applied to the receiving part. 
     The values for the radio local oscillating frequency and intermediate local oscillating frequency step sizes, (i.e., 125 KHz and 50 KHz, respectively), described with reference to FIGS. 1 and 2 may be modified and a comparison frequency of the PLL may have a larger value than a value used in the conventional system. Assuming that the RF circuit of a conventional GMPCS system uses a modulus−8 fractional N counter, the comparison frequency of the conventional RF local oscillator is limited to a value of 200 KHz, i.e., 25 KHz×8=200 KHz. By contrast, the comparison frequency of the RF local oscillator according to the present invention is up to 1 MHZ, i.e., 25 KHz×8×5=1 MHz. 
     To briefly summarize the first embodiment, the intermediate local oscillating frequency was decreased in four successive increments of 50 KHz and the radio local oscillating frequency was increased once by 125 KHz after being maintained at the same frequency for the four consecutive iterations. This process is cyclically repeated as shown in FIG. 3 for successive channel assignments (i.e., channels  1 - 6 ,  7 - 12 ,  13 - 18 , etc.). 
     B. Second Embodiment 
     FIG. 4 is a block diagram of the frequency synthesizer according to a second embodiment of the present invention. In the second embodiment of the present invention, the intermediate local oscillating frequency is decreased twice, each time by 50 KHz and the radio local oscillating frequency is increased once by 50 KHz after being maintained at the same frequency for the two iterations in which the intermediate local oscillating frequency is decreased, thereby reducing a lock time of the frequency synthesizer. 
     Referring again to FIG. 1, the frequency synthesizer  140  according to the second embodiment of the present invention generates the transmitting and receiving radio local oscillating frequency signals to be supplied to the first mixer  107  and the third mixer  123 , and generates the transmitting and receiving intermediate local oscillating frequency signals to be supplied to the second mixer  111  via the ¼ demultiplier  156  and to the in-phase/quadrature modulator  119  via the ½ demultiplier  157 . 
     FIG. 4 is a block diagram of a frequency synthesizer according to a second embodiment of the present invention. Note that exemplary values are provided for a GMPCS system to facilitate understanding of the present embodiment. Referring to FIG. 4, the RF local oscillator  142  of FIG. 1 is comprised of elements  443 - 448 ; a 1/R 3  demultiplier  443 , a second phase detector  445 , a second loop filter  446 , an RF VCO  447 , and a fractional N 3  counter  448 . The demultiplier  443  demultiplies the 13 MHZ signal generated from the reference frequency generator  141  by a factor of 1/R 3  (where R 3  is 52 in the GMPCS system), that is, to a 250 KHz signal. The RF VCO  447  receives a predetermined signal and outputs an RF signal ranging from 2259.05 MHZ to 2289.0 MHZ with a 50 KHz step during transmission and from 2320.05 MHZ to 2350.0 MHZ with a 50 KHz step during reception. This radio local oscillating frequency signal is applied to the first and third mixers  107  and  123  (see FIG.  1 ). The fractional N 3  counter  448 , which is a second programmable counter, fractions the radio local oscillating frequency output from the RF VCO  447  to a 250 KHz step under control of the baseband circuit  160 . The second loop filter  446  lowpass filters the output of the second phase detector  445  and determines a synchronization or response characteristic. The second phase detector  445  compares the phase of a signal output from the second demultiplier  443  with the phase of a signal output from the second programmable counter  448 . If they are the same, the second phase detector  145  supplies the radio local oscillating frequency to the RF VCO  447  via the loop filter  446 . 
     The IF local oscillator  149  shown in FIG. 1 is comprised of a first demultiplier  450  (1/R 4  demultiplier), a first phase detector  451 , a first loop filter  452 , an IF VCO  453 , and a first programmable counter  454 . The first demultiplier  450  demultiplies the reference frequency signal to 1/R 4  (where R 4  is 260). The IF VCO  453  receives a predetermined signal and oscillates to an IF signal. The first programmable counter  454  fractions the frequency signal oscillating from the IF VCO  153  to a 50 KHz step by the control of the baseband circuit  160 . The IF filter  452  lowpass filters the output of the first phase detector  451  and determines a synchronization characteristic or response characteristic. The first loop filter  452  controls the IF VCO  453  so as to output the intermediate local oscillating frequency signal. The first phase detector  151  compares the phase of a signal output from the first demultiplier  450  with the phase of a signal output from the first programmable counter  454 . If they are the same, the first phase detector  151  provides a corresponding intermediate local oscillating frequency signal to the IF VCO  453  via the first loop filter  452 . 
     The operation of the frequency synthesizer for the first transmitting channel will now be described with reference to FIGS. 4 and 5 for a GMPCS system. The reference frequency generator  441  generates a 13 MHZ signal which is demultiplied by the second demultiplier  443  by a factor of 1/52, that is, to a 250 KHz signal. The 250 KHz signal is applied as a first input to the second phase detector  445 . A 2259.05 MHZ signal output from the RF VCO  447  is demultiplied by the second programmable counter  448  by a factor of 1/9036.2, that is, to a 250 KHz signal. The 250 KHz signal is applied as a second input to the second phase detector  445 . If there is no phase difference between the two inputs, the phase detector  445  outputs a transmitting radio local oscillating frequency of 2259.05 MHZ as the output of the RF VCO  447  via the second loop filter  446 . 
     The reference frequency signal of 13 MHZ is also input to the first demultiplier  450  and demultiplied by the first demultiplier  450  by a factor of 1/260, that is, to a 50 KHz signal. The 50 KHz signal is applied as a first input to the first phase detector  451 . A 548.05 MHZ signal output from the IF VCO  453  is demultiplied by the first programmable counter  454  by a factor of 1/10961, that is, to a 50 KHz signal. The 50 KHz signal is applied as a second input to the first phase detector  451 . If there is no phase difference between the two inputs, the phase detector  451  outputs a transmitting intermediate local oscillating frequency as the output of the IF VCO  453  via the first loop filter  452 . The above operation is identically applied to the receiving part. 
     Thus for the first transmitting channel, the transmitting radio local oscillating frequency (TX RFLO) signal of 2259.05 MHZ is provided to the third mixer  123  shown in FIG. 1, and the transmitting intermediate local oscillating frequency (TX IFLO) signal of 274.025 MHZ passing through the ½ demultiplier  157  is applied to the in-phase/quadrature modulator  119 . The output of the third mixer  123  is a 1985.025 MHZ signal (=2259.05 MHZ-274.025 MHZ) which is the radio frequency signal (TX fc) for the first transmitting channel. The above operation is applied to the receiving part as well as other channels of the transmitting part. In the receiving part, the receiving intermediate local oscillating frequency (RX IFLO) signal is demultiplied by the demultiplier  156  to ¼ unlike the first embodiment, thereby decreasing a bandwidth of the RF VCO  447 . 
     The transmitting intermediate local oscillating frequency (TX IFLO) is 548.05 MHZ for odd channels and 548.0 MHZ for even channels, as indicated in FIG.  5 . The receiving intermediate local oscillating frequency (RX IFLO) is 548.1 MHZ for odd channels and 548.0 MHZ for even channels. The transmitting radio local oscillating frequency (TX RFLO) is unchanged for even channels and hops by a 50 KHz step for odd channels. 
     At the 1199-th receiving channel for example, the receiving RF (RX fc) signal of 2199.975 MHZ and the receiving radio local oscillating frequency (RX RFLO) signal of 2350.0 MHZ are applied to the first mixer  107 , and the first receiving IF (RX 1st IF) signal of 150.025 KHz which is the difference there between is applied to the second mixer  111  as an input. The receiving intermediate local oscillating frequency (RX IFLO) signal of 548.1 MHZ is demultiplied by the demultiplier  156  to ¼, that is, to a 137.025 MHZ signal and output as a receiving intermediate local oscillating frequency (RX IFLO 4 ) signal. The RX IFLO 4  signal of 137.025 MHZ is applied to the second mixer  111  as another input. The second mixer  111  outputs a second IF (RX 2nd IF) signal of 13 MHZ. 
     It has been shown that a fast lock time is provided by hopping both the intermediate local oscillating frequency and radio local oscillating frequencies in the RF circuit. Further, the comparison frequency of the phase detector of the RF local oscillator is selectable and thus the frequency plan can be effectively designed. 
     While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.