Abstract:
Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

Description:
BACKGROUND OF THE INVENTION  
     RELATED APPLICATIONS  
       [0001]     This application claims the benefit of priority to Korean Patent Application 2004-30213, filed Apr. 29, 2004, the disclosure of which is incorporated herein by reference.  
         [0002]     1. Field of the Invention  
         [0003]     The present invention relates to dynamic random access memory (DRAM) semiconductor devices and systems, and more particularly to methods and apparatus for per-bank auto-refresh operations to a specified memory bank of a multi-bank.  
         [0004]     2. Description of the Related Art  
         [0005]     DRAM devices are well known and commonly found in digital systems having a need for read/write digital memory. DRAM devices are so-named because the data in each memory cell must be refreshed periodically by reading the data, or else the stored data will be corrupted. Modern synchronous DRAM devices typically employ an “auto-refresh” mode, which refreshes one row of the DRAM memory cell array each time an auto-refresh operation is initiated by an external memory controller. An internal refresh row counter increments through the rows for successive auto-refresh operations, and wraps back to the top of the array upon reaching the bottom. The DRAM memory controller thus has some flexibility as to when it issues the auto-refresh commands to a DRAM device, as long as all rows are refreshed within the maximum time specified for the array to maintain stable data.  
         [0006]     Many SDRAM devices contain multiple banks of memory, with the high-order row address bits supplied to the SDRAM along with an operation determining which bank is to receive the operation. U.S. Pat. No. 5,627,791, issued to Wright et al., describes such a device. Wright&#39;s device allows auto-refresh operations to be addressed to individual banks, using the high-order row address bits. Wright maintains a separate refresh row counter for each bank, and selects the appropriate refresh row counter for the bank that is the target of each refresh operation. Wright&#39;s memory controller is responsible for addressing each bank at the minimum rate required to maintain data stability.  
       SUMMARY OF THE INVENTION  
       [0007]     The described embodiments add flexibility and increased capability as compared to prior art Per-Bank Refresh (PBR) SDRAM devices. A refresh address generator is shared by a plurality of memory banks. Bank address circuitry receives an externally supplied bank address for a refresh operation, and applies the refresh operation to the current refresh row of the memory cell array bank corresponding to the bank address. A refresh bank address counter determines when the refresh address generator should increment to a new refresh row by one of several techniques that are described below. This allows a memory controller to efficiently schedule auto-refresh operations on some banks while read/write operations are ongoing on a separate memory bank, and to change the auto-refresh sequence for different refresh rows. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  illustrates, in block diagram form, a synchronous dynamic random access memory (SDRAM) device according to a first embodiment of the present invention;  
         [0009]      FIG. 2  illustrates a refresh bank address counter useful, e.g., in the SDRAM device of  FIG. 1 ;  
         [0010]      FIG. 3  contains a block diagram for a bank address decoder useful, e.g., in the SDRAM device of  FIG. 1 ;  
         [0011]      FIG. 4  depicts a timing diagram for operation of the SDRAM device of  FIG. 1 ;  
         [0012]      FIG. 5  contains a block diagram for an SDRAM device according to a second embodiment of the present invention;  
         [0013]      FIG. 6  illustrates a refresh bank address counter useful, e.g., in the SDRAM device of  FIG. 5 ;  
         [0014]      FIG. 7  shows one circuit for a bank address latch as used in  FIG. 6 ;  
         [0015]      FIG. 8  depicts another refresh bank address counter useful with embodiments of the present invention;  
         [0016]      FIG. 9A  illustrates the internal organization for the refresh start detection/latch circuit shown in  FIG. 8 ;  
         [0017]      FIGS. 9B and 9C  show two possible refresh start detection circuits useful in the refresh start detection/latch circuit of  FIG. 9A ;  
         [0018]      FIG. 10  contains a timing diagram for auto-refresh operation according to an embodiment of the present invention with the start bank address fixed;  
         [0019]      FIG. 11  illustrates yet another SDRAM device according to an embodiment of the present invention;  
         [0020]      FIGS. 12 and 13  shows circuit alternatives that allow a programmed bank address to be used as a final bank address in embodiments of the present invention;  
         [0021]      FIG. 14   a  illustrates a bonding option circuit useful for programming a final bank address;  
         [0022]      FIG. 14   b  illustrates a mode register set circuit useful for programming a final bank address;  
         [0023]      FIG. 14   c  illustrates an electronically settable fuse circuit useful for programming a final bank address;  
         [0024]      FIG. 14   d  illustrates a fuse circuit useful for programming a final bank address;  
         [0025]      FIG. 15  contains a timing diagram for auto-refresh operation according to an embodiment of the present invention with the final bank address fixed;  
         [0026]      FIG. 16  depicts a memory system according to an embodiment of the present invention; and  
         [0027]      FIG. 17  shows examples of different command sequences that can be accomplished with a memory system according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0028]      FIG. 1  shows a SDRAM device  100  in block diagram form. A memory cell array  10  comprises a plurality of memory cell array banks  10 - 1  to  10 -n, where n can be any number larger than 1, and is typically a power of 2. Each bank comprises a plurality of memory cells MC, each connected to a unique combination of one of a plurality of bit lines BL and one of a plurality of word lines WL, as is known in the art.  
         [0029]     A row address decoder circuit  12  selects one of the word lines for each memory operation based on a supplied row address radda. Row address decoder circuit  12  comprises a plurality of row address decoders  12 - 1  to  12 -n, each activating word lines in a respective one of the memory cell array banks  10 - 1  to  10 -n. A plurality of bank select signals ba 1  to ban determines which of the row address decoders responds to row address radda.  
         [0030]     A column address decoder circuit  14  selects the bit line(s) that will be read/written during memory read/write operations, based on a column address cadd. Column address decoder circuit  14  comprises a plurality of column address decoders  14 - 1  to  14 -n, each reading bit lines in a respective one of the memory cell array banks  10 - 1  to  10 -n.  
         [0031]     A refresh bank address counter  16  receives an externally supplied auto-refresh command signal REF, and activates an Address Count Update (ACU) signal to a refresh address counter  18  when a new refresh row address should be generated. Refresh address counter supplies a current refresh row address RADD to a selector  26 . That is, when the memory  100  is composed of eight banks, the refresh bank address counter  16  activates the address count update (ACU) signal after the refresh bank address counter  16  receives the external auto-refresh command signal (REF) eight times, once for each memory banks. After the ACU signal is enabled, the current refresh row address RADD is updated to a next refresh row address RADD corresponding to a memory cell refresh row to be refreshed during the next refresh cycle time. This process is continuously repeated during refresh operations.  
         [0032]     An address latch  20  receives a plurality of external address signals ADD and a plurality of external bank address signals BA. The external auto-refresh command signal REF, an Active command (ACT) signal, Write command (WR) signal, and Read command (RD) signal determine how ADD and BA are interpreted. During an active command, the ADD signals are latched and supplied as a row address radd to selector  26  for activating a word line corresponding to the row address radd of a selected memory bank, and the BA signals are latched and supplied to a bank address decoder  22  as a bank address ba of the selected memory bank. During a read or write command, the ADD signals (and possibly the BA signals as well) are latched and supplied as column address cadd to the column address decoder circuit  14 . During an auto-refresh command, the bank address signals BA are latched and supplied as bank address ba to the bank address decoder  22 .  
         [0033]     The bank address decoder  22  decodes bank address ba to generate the appropriate bank select signal from the group ba 1 -ban.  
         [0034]     A command decoder  24  receives external command signals COM and generates various control signals, including ACT, WR, and RD.  
         [0035]     Selector  26  determines whether the current refresh row address RADD or the address latch output address radd is passed to row address decoder circuit  12  as row address radda. The auto-refresh command signal REF is supplied to selector  26  as the selection signal—when REF is asserted, RADD is selected, and otherwise radd is selected.  
         [0036]     A data input circuit  28  reads write data signals Din from an external data bus when Write command signal WR is active, and supplies the write data signals din to a selected memory cell array bank responsive to the bank address BA. A data output circuit  30  receives read data signals dout from the selected memory cell array bank in response to the bank address BA when Read command signal RD is active, and supplies the read data signals Dout to the external data bus. The following figures will further illustrate operation of SDRAM device  100 .  
         [0037]      FIG. 2  shows an embodiment of refresh bank address counter  16 , specifically for a case where n=8. A count circuit  200  contains three T (toggle) flip flops  200 - 1 ,  200 - 2 , and  200 - 3 , each with an input T tied to logic high, an output QB, and a clock input CK. For flip flop  200 - 1 , clock input CK is tied to REF, such that flip flop  200 - 1  toggles QB on successive auto-refresh commands. Flip flop  200 - 1  output QB is tied to flip flop  200 - 2  clock input CK, such that flip flop  200 - 2  toggles every other time an auto-refresh command is received. Flip flop  200 - 2  output QB is tied to flip flop  200 - 3  clock input CK, such that flip flop  200 - 3  toggles every fourth time that an auto-refresh command is received.  
         [0038]     The outputs of flip flops  200 - 1 ,  200 - 2 , and  200 - 3  are supplied as inputs Q 1 , Q 2 , and Q 3  to a three-input NAND gate NA 1 . NAND gate NA 1  supplies its output to an inverter I 1 , which supplies its output in turn as the refresh bank address counter ACU signal.  
         [0039]     In operation, count circuit  200  produces, on eight consecutive auto-refresh cycles, an output Q 1 Q 2 Q 3  of 000, 001, 010, 011, 100, 101, 110, 111, and then repeats. For example, assuming that counter circuit  200  output data Q 1 Q 2 Q 3  is 000 after the refresh command signal REF is enabled, then when output data Q 1 Q 2 Q 3  equals 111, ACU is activated, signaling refresh address counter  18  to advance the current refresh row. In another example, assuming that the output data Q 1 Q 2 Q 3  of the counter circuit  200  is ‘101’ after REF is enabled, ACU is activated when output data Q 1 Q 2 Q 3  becomes ‘100’.  
         [0040]      FIG. 3  shows the bank address decoder  22  for the eight-bank case of  FIG. 2 . Three bank address signals BA 0  to BA 2  are decoded to select one of eight bank select signals ba 0 -ba 7 .  
         [0041]      FIG. 4  shows a timing diagram for the circuit of  FIGS. 1, 2 , and  3 . In a first auto-refresh cycle  1  of  FIG. 4 , an external controller asserts REF and supplies a bank address BA=000. Count circuit  200  has an output Q 1 Q 2 Q 3 =000, and the refresh row address RADD has least significant bits 00. On the next seven auto-refresh cycles, the memory controller supplies different bank addresses (other than 000) to refresh row address 00..00 in each of the eight banks. On refresh cycle  8 , Q 1 Q 2 Q 3  has counted up to 111, causing ACU to transition to logic high on the next clock edge. ACU transitioning high causes refresh address counter  18  ( FIG. 1 ) to increment RADD, such that the least significant bits are now 01.  
         [0042]     On refresh cycle  9 , a bank address of 000 is supplied for the new refresh row 00..01. For cycles  9 - 16 , however, the bank refresh order varies from that of cycles  1 - 8 . This does not change the operation of refresh bank address counter  16 , which signals refresh address counter  18  to advance the refresh row after eight refresh operations have been addressed to the current refresh row.  
         [0043]      FIG. 5  illustrates a second embodiment of the present invention, wherein a refresh bank address counter  516  is substituted for refresh bank address counter  16 . Refresh bank address counter  516  receives, in addition to auto-refresh command signal REF, the external bank address BA. This allows refresh bank address counter  516  to ensure that all banks have been addressed in an auto-refresh operation—even if one is duplicated and more than eight refresh operations are required—before the refresh address counter is advanced.  
         [0044]      FIG. 6  shows further detail for one embodiment of refresh bank address counter  516 . A plurality of bank addresses latches, BAL 0 -BAL 7 , are configured to register when respective decoded bank addresses ba 0 -ba 7  are addressed in an auto-refresh operation. A first NOR gate  610  NORs the outputs of bank address latches BAL 0 , BAL 1 , and BAL 2 . A second NOR gate  612  NORs the outputs of bank address latches BAL 3 , BAL 4 , and BAL 5 . A third NOR gate  614  NORs the outputs of bank address latches BAL 6  and BAL 7 . The outputs of NOR gates  610 ,  612 , and  614  are supplied as inputs to a NAND gate  620 . The output of NAND gate  620  is supplied through an inverter  622  as the address count update signal ACU to refresh address counter  18 .  
         [0045]     In operation, each bank address latch BAL 0 -BAL 7  outputs a logic high value until a refresh operation is directed to the corresponding memory bank. Each of NOR gates  610 ,  612 , and  614  will generate a logic low output until each bank address latch BALn feeding that NOR gate registers a refresh operation directed to its corresponding memory bank. NAND gate  620 /inverter  622  will therefore hold ACU low until each NOR gate has received an indication that all bank address latches generating inputs to that NOR gate have registered an auto-refresh operation with a corresponding bank address. In other words, the ACU signal is activated after all banks are enabled for a refresh operation with regard to the identical refresh row address.  
         [0046]      FIG. 7  shows additional details for one bank address latch  516  embodiment, and specifically for BAL 0  and BAL 7 . With respect to BAL 0 , a transmission gate  710  receives ba 0  as an input and supplies an output to a latch comprising two inverters  720  and  725 . The output of inverter  720  supplies a latch output A 0  and an input to inverter  725 . Inverter  725  connects back to the input of inverter  720  to hold a latch value.  
         [0047]     Latch output  730  is supplies as one input to a NAND gate  730 . The other input of NAND gate  730  receives the auto-refresh command signal REF. The output of NAND gate  730  directly drives a low-enabled transmission input of transmission gate  710 , and drives a high-enabled transmission input of transmission gate  710  through an inverter  735 . Finally, the ACU signal drives a transistor  740  connected between the latch input and ground.  
         [0048]     In operation, when ACU is asserted, transistor  740  is turned on and pulls the input of latch  720  low, which drives latch output A 0  high. With latch output A 0  high, NAND gate  730  can respond to a high input at auto-refresh signal REF. When both A 0  and REF are high, NAND gate  730  generates a low output, which energizes transmission gate  710 . When transmission gate  710  is energized, it passes ba 0  through to the input of latch transistor  720 . In such a circumstance, the latch will switch state and output A 0  low when ba 0  is high, indicating that an auto-refresh operation was requested for bank  0 . Once this event is latched and A 0  is low, NAND gate  730  will not respond to additional auto-refresh cycles until ACU resets the latch after all banks have been addressed.  
         [0049]      FIG. 8  illustrates a refresh bank address counter embodiment  816  that can be substituted for refresh bank address counter  516  in some embodiments. Whereas refresh bank address counter  516  counts each refreshed bank in the order latched, refresh bank address counter  816  operates differently. Refresh bank address counter  816  does not begin counting refresh cycles until a predetermined start bank address is received along with an auto-refresh command, after which it counts eight refresh cycles, resets, and then waits for another auto-refresh command issued with the start bank address. For instance, in one embodiment bank  0  is designated as the start bank. Once a memory controller asserts bank  0  during an auto-refresh, it may then address the remaining seven banks in any order, and then the auto-refresh row advances and the device waits for another auto-refresh directed at bank  0  to begin counting again. One advantage of this embodiment is the memory controller can control when refresh operations begin on each row by when it asserts REF along with bank address  0 .  
         [0050]     In  FIG. 8 , refresh bank address counter  816  comprises a count circuit  800 , a reset circuit  810 , a refresh start detection/latch circuit  820 , two NAND gates NA 1  and NA 2 , and two inverters I 1  and I 2 . Refresh start detection/latch circuit  820  receives the external bank address BA and external auto-refresh command signal REF. When the predetermined start bank address is received on BA along with an auto-refresh command on REF, circuit  820  asserts its output BAL.  
         [0051]     BAL and REF are input to NA 2 , such that once BAL is asserted, the output of NA 2  responds to REF. Inverter  12  inverts the output of NA 2  and supplies the inverted signal to count circuit  800 .  
         [0052]     Count circuit  800  contains three T (toggle) flip flops  800 - 1 ,  800 - 2 , and  800 - 3 , each with an input T tied to logic high, an output QB, and a clock input CK. For flip flop  800 - 1 , clock input CK is tied to the output of I 2 , such that flip flop  800 - 1  toggles QB on successive auto-refresh commands once an auto-refresh command with the start bank address is received. Flip flop  800 - 1  output QB is tied to flip flop  800 - 2  clock input CK, such that flip flop  800 - 2  toggles every other time an auto-refresh command is received after BAL is asserted. Flip flop  800 - 2  output QB is tied to flip flop  800 - 3  clock input CK, such that flip flop  800 - 3  toggles every fourth time that an auto-refresh command is received after BAL is asserted.  
         [0053]     The outputs of flip flops  800 - 1 ,  800 - 2 , and  800 - 3  are supplied as inputs Q 1 , Q 2 , and Q 3  to three-input NAND gate NA 1 . NAND gate NA 1  supplies its output to inverter I 1 , which supplies its output in turn as the refresh bank address counter ACU signal.  
         [0054]     ACU is supplied to reset circuit  810 , which resets refresh start detection/latch circuit  820  when ACU is asserted. Once reset, start detection/latch circuit  820  waits for an auto-refresh command for the start bank address to start the count for the next refresh row.  
         [0055]      FIG. 9A  shows internal circuit details for refresh start detection/latch circuit  820 , including a refresh start detection circuit  900 , a switch  910 , a latch  920 , and a transistor  930 . Refresh start detection circuit  900  receives REF and BA, and asserts a START signal when BA matches the start bank address. Switch  910  receives the START signal and passes it to the input of latch  920  when switch  910  is activated. When START is passed to latch  920 , latch  920  is latched high, asserting output BAL from circuit  820 . BAL is also fed back to switch  910 , deactivating switch  910 .  
         [0056]     When RESET is asserted from reset circuit  810  ( FIG. 8 ), transistor  930  is activated, pulling latch  920  low. When latch  920  is pulled low, BAL is deasserted and switch  910  is reactivated to prepare the circuit for the next auto-refresh command to the start address.  
         [0057]      FIGS. 9B and 9C  show two possible refresh start detection circuits  900 . In  FIG. 9B , circuit  900  comprises a NAND gate  940  paired with an inverter  950  to implement an AND function. REF and one decoded bank address (in this case ba 0 , but any other bank address could also be chosen) are supplied as inputs to the NAND gate. When REF and ba 0  are high, the output of inverter  950  is also driven high, and is supplied as the START signal.  
         [0058]      FIG. 10  shows a timing diagram for the memory device of  FIGS. 5, 8 ,  9 A, and  9 B. Three different refresh bank address sequences are commanded for consecutive refresh rows, one sequence for auto-refresh cycles  1 - 8 , a second sequence for auto-refresh cycles  9 - 16 , and a third sequence for auto-refresh cycles  17 - 24 . Each sequence begins, however, with an auto-refresh to bank address  0  (BA 000), causing BAL to be asserted from a refresh start detection/latch circuit  820 . BAL remains asserted until eight auto-refresh operations have been completed (at auto-refresh cycles  8 ,  16 , and  24 ), at which time ACU is asserted, triggering reset circuit  810  to reset refresh start detection/latch circuit  820  and BAL.  
         [0059]     In  FIG. 9C , refresh start detection circuit  900  can accept any bank address as the start bank address. All eight decoded bank addresses ba 0 -ba 7  are ORed together by three NOR gates  960 ,  962 , and  964  with outputs combined by a NAND gate  970 . The ORed bank addresses are combined with REF using a NAND gate  980  and inverter  990  to produce a start signal, in a manner similar to that employed in  FIG. 9B  for a single bank address.  
         [0060]      FIG. 11  illustrates a third embodiment of the present invention, an SDRAM circuit  1100  wherein a refresh bank address detector  1116  is substituted for refresh bank address counter  516  of  FIG. 5 . Refresh bank address detector  1116  functions by asserting ACU whenever a refresh operation is received for a predetermined final bank address.  
         [0061]      FIG. 12  illustrates one embodiment of refresh bank address detector  1116 . Detector  1116  comprises an inverter  1210 , an m-input/m-output transmission gate  1220 , a comparator  1300 , and a bank address register  1320 . The m lines of external bank address BA are supplied to transmission gate  1220 . Transmission gate  1220  is controlled by external auto-refresh command signal REF, which directly drives the n-gate of the transmission gate, and drives the p-gate of the transmission gate through inverter  1210 .  
         [0062]     Bank address register  1320  contains a predetermined final bank address, stored using m bits in the same order as the m BA inputs. When REF activates transmission gate  1220 , comparator  1300  compares the m BA inputs to the M bank address register  1320  inputs. Comparator  1300  asserts ACU when the comparison evaluates true.  
         [0063]     Bank address register  1320  can be programmed in many different ways. One simple, but inflexible, approach involves designing the chip mask to permanently assert a given final bank address. Several other more flexible approaches will now be described.  
         [0064]      FIG. 13  shows one approach that allows any bank address to be programmed as the final bank address. Bank address register  1320  actually comprises hard-coded binary bank addresses &lt;BA 0 ,BA 1 ,BA 2 &gt; corresponding to each bank Bank 0  to Bank 7 . A switch crossbar  1340  allows any of the register  1320  bank addresses to be loaded to a bank address latch  1330  in response to one select signal (SEL) among a plurality of select signals (SELs) generated from a programmable bank selector  1400 . A programmable bank selector  1400  energizes one of the switches in crossbar  1340  according to a corresponding select signal SEL, which indicates a programmed bank indication.  
         [0065]     Comparator  1300  comprises three bank address comparators, one each for BA 0 , BA 1 , and BA 2 . Each comparator performs a binary comparison between one of the bank address lines and a corresponding bit from bank address latch  1330 , All three bank address comparators produce a binary match output to an AND circuit, which asserts ACU when all bits match.  
         [0066]      FIGS. 14   a ,  14   b ,  14   c , and  14   d  illustrate four possible methods for setting programmable bank selector  1400 . In  FIG. 14   a , bank selector  1400  comprises one or more circuits comprising a bond pad  1420   a  and an inverter  1440   a . Bond pad  1420   a  provides a bonding option—when pad  1420   a  is bonded to a lead frame V cc  contact  1410   a , inverter  1440   a  does not assert a selection output SEL for that line. When pad  1420   a  is bonded to a lead frame ground contact  1430   a , inverter  1440   a  does assert a selection output SEL for that line. Thus a final bank address can be selected during packaging by bonding one selector  1400  bond pad to ground and the rest to V cc .  
         [0067]     In  FIG. 14   b , a Mode Register Set (MRS)  1450  provides n select lines SEL 1  to SELn. When a particular combination of inputs RASB, CASB, and WEB trigger MRS  1450 , it reads the external address lines Ai and decodes the address as a particular mode register instruction. Different mode register instructions can thus be used to activate different ones of select lines SEL 1  to SELn.  
         [0068]     A Mode Register Set can also be used to permanently program a final bank address, after the SDRAM device has been assembled. In  FIG. 14   c , MRS  1450  supplies a plurality of MRS fuse-burning outputs MRS 1 -MRSn. By asserting a particular combination on the fuse-burning outputs, an electric fuse circuit permanently severs one of two electric fuses F 1  and F 2  for each select line SEL. Depending on which fuse is severed, each SEL line will be set permanently high or permanently low, even when the device is powered off and on again.  
         [0069]     In  FIG. 14   d , another programmable bank selector circuit  1400  is illustrated. The  FIG. 14   d  embodiment uses a laser-cut fuse F 3  that can be cut after the device is fabricated but prior to packaging. Circuit  1400  delays power-on until supply voltages stabilize, by relying on a delayed control voltage VCCH that is not triggered high until the supply voltage rises above a threshold (illustrated in the time vs. voltage plot included with  FIG. 14   d . Depending on whether fuse F 3  is severed or not, SEL will always be asserted or deasserted once the device powers on.  
         [0070]      FIG. 15  contains a timing diagram example for the embodiments of  FIGS. 11-14   d . By the chosen means, a final bank address 111 is selected for comparison to the external bank address. The SDRAM  1100  continues to refresh banks in the same row until an auto-refresh command accompanied by the final bank address 111 is received (auto-refresh cycles  8 ,  16 , and  24 ). When final bank address 111 is received, the refresh command is executed and the refresh row is advanced. It does not matter what order the other bank addresses are presented—in fact, refresh row could be advanced in this circuit without every bank being addressed for a given refresh row.  
         [0071]     Each of the above-described SDRAM devices is assumed to be paired with a memory controller capable of supplying allowable refresh bank address sequences. In  FIG. 16 , one common configuration for coupling the SDRAM and memory controller is illustrated as a memory system  1600 . Memory system  1600  comprises a memory controller  1610  and a memory module  1620 . Memory module  1610  comprises one or more SDRAM devices according to an embodiment of the present invention, coupled in a single rank or multiple ranks of memory devices. Memory controller  1610  supplies command (COM), auto-refresh (REF), address (ADD), and bank address (BA) signals to the SDRAM devices on memory module  1620 . Data is supplied to memory module  1620  on data lines Din, and data is received from memory module  1620  on data lines Dout (lines Din and Dout may be the same lines, with only one of controller  1610  and module  1620  allowed to drive the lines at any given time).  
         [0072]      FIG. 17  illustrates how the memory system of  FIG. 16  can be operated according to an embodiment of the present invention, for three different exemplary activity sequences Case 1, Case 2, and Case 3. In each case, a different auto-refresh sequence is used. Memory controller  1610  knows which banks have memory accesses in progress, and which banks will soon have memory accesses requested. When an auto-refresh command must be issued, the memory controller selects a bank that is not currently being accessed, and will not need to be accessed before the auto-refresh command completes for that bank. This allows auto-refresh operations to be accomplished, if desired, in the least obtrusive manner.  
         [0073]     Those skilled in the art will recognize that many other device configuration permutations can be envisioned and many design parameters have not been discussed. For instance, although a separate external auto-refresh signal line REF has been assumed, auto-refresh commands could be decoded from a specific combination asserted on a command bus. Various features of the described embodiments can be combined with other embodiments. The specific circuits described and shown in the drawings are merely exemplary—in most cases, other circuits can accomplish the same or similar functions. Such minor modifications and implementation details are encompassed within the embodiments of the invention, and are intended to fall within the scope of the claims.  
         [0074]     The preceding embodiments are exemplary. Although the specification may refer to “an”, “one”, “another”, or “some” embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.