Abstract:
In one aspect, a method includes forming a pit in a top surface of a substrate by removing a portion of the substrate and growing a semiconductor material with a bottom surface on the pit, the semiconductor material different than the material of the substrate. The pit has a base recessed in the top surface of the substrate. In another aspect, a structure includes a substrate having a top surface, the substrate including at least one pit having a base lower than the top surface of the substrate, and a semiconductor material having a bottom surface formed on the base of the pit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. provisional application No. 60/999,304, filed Oct. 17, 2007, and entitled “Method of Fabrication of Ge or SiGe photo detector by selective growth on bulk Si or SOI wafer;” and to U.S. provisional application No. 60/999,317, filed Oct. 17, 2007, and entitled “Method of selectively growing Ge or SiGe materials on bulk Si or SOI wafer,” both of which are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to semiconductor photodetectors. 
     BACKGROUND 
     High density photonic lightwave circuits have been the subject of significant investigation recently. High index contrast waveguide-based devices (e.g., modulators or attenuators) and devices such as photodetectors and modulators formed from silicon-compatible materials (e.g., germanium or SiGe) are fabricated using complementary metal-oxide-semiconductor (CMOS) processing technology onto silicon or silicon-on-insulator (SOI) substrates. For instance, photodetectors formed of one or more layers of Ge or SiGe on a Si substrate that detects light incident from the top or bottom of the substrate have been studied. Such photodetectors, when monolithically integrated with CMOS integrated circuits on the same substrate, are often fabricated from thin films of Ge and SiGe that are inefficient at absorbing incident light from the top or bottom of the substrate. 
     SUMMARY 
     In a general aspect, a method includes forming a pit in a top surface of a substrate by removing a portion of the substrate and growing a semiconductor material with a bottom surface on the pit, the semiconductor material different than the material of the substrate. The pit has a base recessed in the top surface of the substrate. 
     Embodiments of the method may include one or more of the following features. Growing the semiconductor includes forming a photodetector. The method includes forming active electronic components on the top surface of the substrate, the active electronic components electrically coupled to the photodetector. The method includes doping at least a portion of the base of the pit prior to growing the semiconductor material. The at least a portion of the base of the pit is configured to be an electrode of the semiconductor material. The method further includes annealing the substrate after growing the semiconductor material. The anneal is performed between 700° C. and 900° C. 
     The method includes forming a dielectric layer on top of at least a portion of the substrate prior to growing the semiconductor material, the portion of the substrate including the pit; and generating a hole in the dielectric layer in the region of the pit. The semiconductor material is grown in the hole in the dielectric layer. The method further includes performing a chemical mechanical polish process after growing the semiconductor material. The dielectric layer includes at least one of silicon dioxide (SiO 2 ), silicon oxide (SiO x ), silicon nitride (Si x N y ), or silicon oxynitride (SiO x N y ). The dielectric layer includes a plurality of sublayers, each sublayer including at least one of silicon dioxide (SiO 2 ), silicon oxide (SiO x ), silicon nitride (Si x N y ), or silicon oxynitride (SiO x N y ). 
     The pit is formed by at least one of dry chemical etching, wet chemical etching, dry thermal oxidation, or wet thermal oxidation. Forming the pit includes depositing a mask on the top surface of the substrate, oxidizing the portion of the substrate to be removed by wet or dry oxidation, and removing at least a part of an oxide formed by the oxidation of the portion of the substrate. The mask defines the portion of the substrate to be removed. The oxide is removed by chemical mechanical polishing or at least one of wet chemical etching or dry chemical etching. The mask includes at least one of silicon nitride (Si x N y ), silicon oxynitride (SiO x N y ), silicon dioxide (SiO 2 ), or silicon oxide (SiO x ). 
     The method further includes fabricating an integrated circuit on the top surface of the substrate. The integrated circuit is fabricated using CMOS processing or CMOS compatible processing. The step of growing the semiconductor material occurs after front-end processing of the integrated circuit and prior to back-end processing of the integrated circuit. Front-end processing includes fabricating at least one metal-oxide-semiconductor (MOS) transistor. The bottom surface of the semiconductor material is lower than a bottom surface of a gate oxide of the at least one MOS transistor, such as at least 50 nm lower or at least 200 nm lower than the bottom surface of the gate oxide of the at least one MOS transistor. A top surface of the semiconductor material is higher than the top surface of the substrate and lower than a top surface of the at least one MOS transistor. Back-end processing includes fabricating at least one layer of metal interconnects. A top surface is lower than or at substantially the same level as a bottom surface of a lowest layer of metal interconnects. 
     The method includes growing polysilicon or amorphous silicon on top of or on at least one side of the semiconductor material. The method further includes doping at least a portion of the polysilicon or amorphous silicon. The at least a portion of the polysilicon or amorphous silicon is configured to be an electrode of the semiconductor material. The semiconductor material includes a photodetector. 
     The semiconductor material has a lateral size of between 50 μm and 75 μm, or of less than 50 μm. The semiconductor material includes Ge or SiGe. The semiconductor material is grown to a thickness of at least 0.5 μm. The semiconductor material is grown through a chemical vapor deposition (CVD) process, such as a low pressure CVD process or a high vacuum CVD process. The substrate includes silicon or silicon-on-insulator. 
     In another general aspect, a structure includes a substrate having a top surface, the substrate including at least one pit having a base lower than the top surface of the substrate, and a semiconductor material having a bottom surface formed on the base of the pit. 
     Embodiments of the structure may include one or more of the following features. The semiconductor material is a photodetector. An efficiency of the photodetector is at least 95%. The structure further includes active electronic components formed on the top surface of the substrate, the active electronic components electrically coupled to the photodetector. At least a portion of the base of the pit is doped. The at least a portion of the base of the pit is configured to be an electrode of the semiconductor material. The semiconductor material includes Ge or SiGe. The semiconductor material is at least 0.5 μm thick. The semiconductor material has a lateral size of between 50 μm and 75 μm, or of less than 50 μm. The structure includes a layer of an insulator substantially covering the substrate. The substrate includes silicon or silicon-on-insulator. 
     The structure includes an integrated circuit fabricated on the top surface of the substrate. The integrated circuit includes at least one MOS transistor. A top surface of the semiconductor material is higher than the top surface of the substrate and lower than a top surface of the at least one MOS transistor. The integrated circuit includes at least one layer of metal interconnects. A top surface of the semiconductor material is lower than or at substantially the same level as a bottom surface of a lowest layer of metal interconnects. 
     The structure further includes a layer of polysilicon or amorphous silicon on top of or on at least one side of the semiconductor material. At least a portion of the polysilicon or amorphous silicon is doped. The at least a portion of the polysilicon or amorphous silicon is configured to be an electrode of the semiconductor material. The semiconductor material includes a photodetector. 
     In a further general aspect, an electro-optical system includes at least one integrated device including a photodetector body and active electronic components electrically coupled to the photodetector body. The photodetector body has a thickness selected to enable fabrication of the active electronic components. 
     Embodiments of the electro-optical system may include one or more of the following features. The electro-optical system includes an optical fiber coupled to the photodetector body. The electro-optical system includes a plurality of integrated devices. The active electronic components are configured to amplify and to reshape a signal detected by the photodetector body. The active electronic components include a digital microprocessor. 
     Embodiments may include one or more of the following advantages. 
     In some examples, a Ge or SiGe photodetector fabricated on a wafer and configured to detect light coming from the top or bottom of the wafer is between approximately 900 nm and several micrometers in thickness in order for the photodetector to absorb 95% of incoming light having a wavelength between approximately 0.85 μm and 1.5 μm. The height of a first metallization layer (M1) in a CMOS integrated circuit is often less than an optimal thickness of the photodetector. For example, the height of the M1 layer is typically about 500 nm above the top surface of the substrate for a typical 0.13 μm CMOS foundry processing line. More advanced CMOS processing lines may have even lower heights. Growing a photodetector in a pit in the substrate (e.g., a pit having a depth of at least 400 nm) can recess the photodetector so that its height above the top surface of the substrate is lower than the height of the M1 layer. This compatibility in height of the photodetector and the M1 layer enables standard CMOS processing techniques. 
     High-temperature front-end processing of MOS transistors (e.g., fabrication of the poly gate structures), which often exceeds 950° C., can be completed before the fabrication of the photodetector, which cannot endure such high temperatures. The growth and optional anneal of the photodetector then requires processing at temperatures in the range of 600° C. to 900° C., which is too high for the back-end processing of metal interconnects. Thus, the back-end processing can be performed after the growth and anneal of the photodetector. This process sequence, in which the growth and anneal of the photodetector is performed after front-end processing but before back-end processing, is enabled by the structure and height of the photodetector. Since the top surface of the photodetector is at a level lower than the M1 layer, standard CMOS processing techniques, such as chemical mechanical polish (CMP) steps, are possible for the fabrication of back-end structures. Furthermore, existing models and designs for integrated circuit components can be preserved while integrating an efficient photodetector onto the same substrate as the integrated circuit components. For instance, the height compatibility allows a standard integrated circuit design including the digital integrated circuit design for the M1 layer to be used. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIGS. 1A-1B  are top view and cross-sectional view schematic diagrams of a photodetector and an integrated circuit fabricated on a single wafer. 
         FIG. 2  is a flow diagram of a general fabrication process. 
         FIG. 3  is a cross-sectional view of a wafer with a pit. 
         FIGS. 4A-4D  are flow diagrams of fabrication processes for a pit in a wafer. 
         FIGS. 5A-5C  are cross-sectional views of a method for generating a pit in a wafer. 
         FIGS. 6A-6B  are cross-sectional views of a method for generating a pit in a wafer. 
         FIG. 7  is a cross-sectional view of the wafer of  FIG. 2  with a deposited insulating layer. 
         FIG. 8  is a cross-sectional view of the wafer of  FIG. 5  with a photodetector body grown in the pit. 
         FIG. 9  is a cross-sectional view of the wafer of  FIG. 6  with a top contact formed on the photodetector body. 
         FIG. 10  is a cross-sectional view of the wafer of  FIG. 7  with initial back-end structures fabricated. 
         FIG. 11  is a flow diagram of one example of a fabrication process. 
         FIG. 12  is a cross-sectional view of one embodiment of a method for generating a pit in a wafer. 
         FIGS. 13A-13B  are cross-sectional views of an implantation into the wafer of  FIG. 9 . 
         FIG. 14  is a cross-sectional view of a second implantation step into the wafer of  FIG. 10 . 
         FIG. 15  is a cross-sectional view of a shallow trench isolation (STI) etch step in the wafer of  FIG. 11 . 
         FIG. 16  is a cross-sectional view of the wafer of  FIG. 12  with a deposited thick oxide layer. 
         FIG. 17  is a cross-sectional view of an implantation into the wafer of  FIG. 13 . 
         FIG. 18  is a cross-sectional view of a processing step for the wafer of  FIG. 14 . 
         FIG. 19  is a cross-sectional view of the wafer of  FIG. 15  with a photodetector body grown in the pit. 
         FIG. 20  is a cross-sectional view of a processing step for the wafer of  FIG. 16 . 
         FIG. 21  is a cross-sectional view of an implantation into the wafer of  FIG. 17 . 
         FIG. 22  is a cross-sectional view of the wafer of  FIG. 18  with salicide regions. 
         FIG. 23  is a cross-sectional view of the wafer of  FIG. 19  with initial back-end structures fabricated. 
         FIGS. 24A-24B  are cross-sectional views of an alternative embodiment with a silicon-on-insulator (SOI) wafer. 
         FIGS. 25A-25D  are cross-sectional views of a further embodiment with a photodetector configured for horizontal carrier collection. 
         FIG. 26  is a schematic diagram of a CMOS integrated circuit. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS. 1A and 1B , an integrated circuit  100  includes a photodetector body  102  and complementary metal-oxide-semiconductor (CMOS) integrated circuit components  106  fabricated on a single substrate  101 . Integrated circuit components  106  may include transistors, such as a representative metal-oxide-semiconductor (MOS) transistor  108 ; conductive interconnects, such as metal plugs  110  and  112 , metal plugs (not shown) to a gate of MOS transistor  108 , and metal lines  114  in metallization layer M1, and other standard components of integrated circuits. Photodetector body  102  is formed of germanium (Ge) or silicon germanium (SiGe) and preferably has a thickness of 0.5 μm to 2.5 μm. To accommodate this thickness, a pit  104  is formed in substrate  101  such that the base of photodetector body  102  is lower than a top surface of substrate  101 . The top of photodetector body  102  is lower than a bottom surface of metal lines  114  in metallization layer M1, and preferably at a similar level as integrated circuit components  106 . For instance, the top of photodetector body is preferably at a level between a top surface of substrate  101  and a top surface of a gate of MOS transistor  108 . This height configuration enables standard designs for integrated circuit components  106  and standard complementary metal-oxide-silicon (CMOS) processing techniques to be used for integrated circuit fabrication processes. That is, for instance, metallization layer M1 is fabricated based on standard or existing integrated circuit designs. In general, the fabrication steps described below use standard CMOS processing procedures and parameters. 
     Photodetector body  102  can be configured to detect light incoming from the top or bottom of the substrate, incident vertically or at an angle. In the example shown in  FIG. 1B , light  116  is incident on photodetector body  102  from the bottom of substrate  101  via an optical fiber  118 . In the configuration of integrated circuit  100 , the cross-sectional size of photodetector body  102  can be made with a dimension selected for a desired application. For instance, photodetector body  102  can have a cross-sectional size as low as 10 μm to 75 μm to match the size of a single mode optical fiber or a multimode optical fiber, or in the range of several hundred micrometers to match the size of a polymer optical fiber, or even as large as several millimeters for use as an optical-to-electrical power converter. In one example, the cross-sectional size of photodetector body may be in the range of 50-75 μm, which matches the core size of a standard multimode optical fiber (typically 50 μm or 62.5 μm). 
     Referring to  FIGS. 2 and 3 , examples of fabrication processes for devices structured as shown in  FIGS. 1A-1B  on a wafer  200  begin with laser marking and cleaning ( 10 ) a silicon substrate  202 . A pit  204  is formed ( 12 ) in a region of silicon substrate  202 ; the depth of pit  204  is generally between 0.2 μm and 2.0 μm. Pit  204  may be formed at any point during front-end processing of standard metal-oxide-semiconductor (MOS) transistors. In the example shown in  FIG. 3 , a representative transistor  206  was fabricated prior to the formation of pit  204 . In other embodiments, pit  204  is formed prior to the fabrication of front-end integrated circuit components, such as MOS transistors. In general, pit  204  is formed before the fabrication of any back-end integrated circuit components. 
     Pit  204  can be formed using a variety of methods. Referring to  FIG. 4A , in some examples, silicon substrate  202  is masked and a lithography process is performed ( 50 ) to define a location for the formation of pit  204 . Pit  204  is formed by a dry chemical etch ( 52 ) of silicon substrate  202  followed by a wet chemical etch ( 54 ) to smooth the etched surface of the silicon substrate. Alternatively, as shown in  FIG. 4B , a lithography process defines ( 56 ) a location for the formation of pit  204 . A first wet chemical etch ( 58 ) of silicon substrate  202  is followed by a second wet chemical etch ( 60 ) to smooth the surface of the substrate to form pit  204 . In general, the location of pit  204  is defined by a mask. 
     Referring to  FIGS. 4C and 5A , another method to fabricate pit  204  involves a lithography process ( 62 ) to pattern a mask  210  defining a position for a preliminary pit  208 . Mask  210  is typically a hard mask such as silicon nitride (Si x N y ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), or another material having suitable properties. Preliminary pit  208  is etched ( 64 ) into silicon substrate  202  via a wet etch or a dry etch. After etching preliminary pit  208 , the surface of silicon substrate  202  is oxidized ( 66 ) using either dry oxidation or wet oxidation to smooth the etched surface of preliminary pit  208  and/or to deepen preliminary pit  208 . Oxidation can be performed with mask  210  still present, as shown in  FIG. 5B , or after the removal of mask  210 , as shown in  FIG. 5C . The oxidation process generates an oxide layer  212 . Pit  204  is then formed by a wet etch or dry etch ( 68 ) of oxide layer  212  within preliminary pit  208 . 
     Referring to  FIGS. 4D and 6A , a further alternative to forming pit  204  involves a lithography process ( 70 ) to pattern mask  210 , defining a position for pit  204 . The top surface of silicon substrate  202  is thermally oxidized ( 72 ) to form an oxide  214  in the regions of the surface not protected by mask  210 . Mask  210  is then removed ( 74 ) and pit  204  is revealed by removal of oxide  214  via wet etching or dry etching ( 76 ), as shown in  FIG. 6B . To obtain the desired pit depth, multiple patterning, oxidation, and removal steps may be performed. 
     Referring again to  FIGS. 2 and 3 , after pit  204  is formed, an implantation process ( 14 ) is performed to adjust the doping concentration in a region  205  at the base and/or in the sidewalls of pit  204 . Ultimately, a photodetector body will be grown in pit  204 . Adjusting the doping concentration in region  205  reduces the contact and/or series resistance between the photodetector body and silicon substrate  202 . 
     Continuing to refer to  FIGS. 2 and 7 , after the formation of pit  204  and the implantation of the pit region, an insulating layer  216  is grown or deposited ( 16 ) over the surface of silicon substrate  202 . Insulating layer  216  is typically silicon dioxide (SiO 2 ), but may be composed of silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiO x N y ), or another material having similar properties. Multiple layers of these materials may be formed. The top surface of insulating layer  216  is higher than the top surface of transistor  206 . A chemical mechanical polish (CMP) step is optionally performed ( 20 ) to flatten the surface of insulating layer  216 . Alternatively, in the embodiment shown in  FIG. 6A , oxide layer  212  is not removed ( 18 ) after the thermal oxidation step, and a CMP step is performed ( 20 ) after mask removal to planarize oxide layer  212 . 
     Referring again to  FIGS. 2 and 7 , a hole  218  is generated ( 22 ) in insulating layer  216  by a wet etch or dry etch process, or a combination of both wet etch and dry etch processes. Hole  218  is aligned with pit  204  and is deep enough such that a portion of silicon substrate  202  is exposed at the base of hole  218 . In some embodiments, an implantation process is performed ( 24 ) to adjust the doping concentration in a region  220  at the base of hole  218 . As with the doping of region  205 , adjusting the doping concentration in region  220  reduces the contact and/or series resistance between the photodetector body and silicon substrate  202 . 
     Referring to  FIGS. 2 and 8 , selective growth of germanium (Ge) or silicon germanium (SiGe) within hole  218  to form a photodetector body  222  is performed ( 26 ) by a chemical vapor deposition (CVD) process, such as ultra-high vacuum CVD (UHCVD) or low pressure CVD (LPCVD). Photodetector body  222  may be grown by epitaxial growth of Ge or SiGe on substrate  202 . Since Ge and SiGe does not grow on insulating layer  216 , growth is limited to the exposed region of substrate  202  at the base of hole  218 . In some embodiments, after the growth of photodetector body  222 , wafer  200  is thermally annealed ( 28 ) at a defined temperature range between 700° C. and 900° C. During the CVD growth process, photodetector body  222  may have grown higher than a top surface  224  of insulating layer  216 . In this case, a CMP process is optionally performed ( 30 ) to remove the overgrown portion of photodetector body  222 , resulting in a planar top surface of wafer  200 . 
     Referring to  FIGS. 2 and 9 , in some embodiments, a contact layer of polysilicon or amorphous silicon is grown or deposited ( 32 ) and then patterned ( 34 ) to form a top contact  226  to photodetector body  222 . 
     Referring to  FIGS. 2 and 10 , a dielectric layer  230  is deposited ( 36 ) on top of existing insulating layer  216  and top contact  226  to raise the top surface of wafer  200  to a level sufficient for further processing, such as for the formation of interconnects and a first metallization layer M1. Metal plugs, such as tungsten plugs, are formed ( 40 ) using standard CMOS processing techniques. Photodetector contact plugs  234   a  and  234   b  are used to make contact with top contact  226  and region  205  (i.e., the doped bottom contact) of photodetector body  222 , respectively. Prior to the formation of photodetector contact plugs  234 , an implantation in a region  227  at the base of pit  204  may be performed ( 38 ) to adjust the doping level in region  227 , thus reducing the contact resistance between photodetector contact plug  234   b  and silicon substrate  202 . In this configuration, photon induced carriers generated in photodetector body  222  are collected vertically through top contact  226  and bottom contact region  205 . Transistor contact plugs  236  are formed to connect a source, drain, and gate (not shown) of transistor  206  to first metallization layer M1. The materials and processing steps for the formation of photodetector contact plugs  234  are not necessarily the same as the materials and processing steps for the formation of transistor contact plugs  236 . After the formation of metal plugs  234  and  236 , standard back-end processing for the wiring of metal interconnects of MOS transistors, other integrated circuit components, and photodetectors is then performed ( 42 ). 
     Since Ge and SiGe does not, in general, endure the high temperature thermal processing (&gt;950° C.) used for front-end CMOS processing (i.e., transistor fabrication), the growth of photodetector body  222  and the optional thermal anneal step are preferably performed after the finish of high temperature front-end processing of transistor  206 . For example, photodetector body  222  is grown after the formation of the polysilicon gate of transistor  206 . The growth and anneal of Ge or SiGe photodetector body  222  involves processing at relatively high temperatures (between approximately 600° C. and 900° C.). All low-temperature back-end processing (i.e., fabrication of metal interconnects) is preferably performed after photodetector body  222  is grown and annealed. 
     Referring to  FIGS. 11 and 12 , in a specific embodiment, a wafer  300  on which a photodetector is fabricated includes a silicon substrate  302 . A pad oxide layer  306  is grown ( 600 ) on the top surface of silicon substrate  302  and a hard mask  308  of silicon nitride is deposited ( 602 ). A photoresist layer  310  is deposited on top of hard mask  308  and a lithography process is performed ( 606 ) to define a region for the formation of a pit  304 . To generate pit  304 , hard mask  308  and pad oxide  306  are removed by an etch process ( 608 ), and pit  304  is etched ( 610 ) into silicon substrate  302  to a depth of between 0.2 μm and 2.0 μm. Photoresist layer  310  is stripped and wafer  300  is cleaned ( 612 ). 
     Referring to  FIGS. 11 and 13A , a thermal oxide  312  is grown ( 614 ) within pit  304  to repair the base of pit  304 . Implantation processes are then performed to dope the base and sidewalls of pit  304 . A photoresist layer  314  is deposited on top of hard mask  308  and a lithography process is performed ( 616 ) to define a region for the implantation. For a p-side-down photodetector, a first high energy implantation ( 618 ) of Boron generates a p-well  316  within pit  304 . A subsequent medium dose implantation ( 620 ) of Arsenic or Phosphorus generates an n-sub  318  within p-well  316 , as shown in  FIG. 13B . Alternatively, if an n-side-down photodetector is desired, high energy implantation of Arsenic or Phosphorus forms an n-well, and medium dose implantation of Boron is used to generate a p-sub. Following implantation, photoresist layer  314  is stripped and wafer  300  is cleaned ( 622 ). 
     Referring to  FIGS. 11 and 14 , a further implantation process is performed to dope the sidewalls of pit  304 . A photoresist layer  320  is deposited and a lithography process ( 624 ) defines a region for the implantation. A high dose implantation ( 626 ) of Phosphorus or Arsenic generates an n+ conductive region  322  (for a p-side-down photodetector). Alternatively, for an n-side-down photodetector, an implantation of Boron generates a p+ conductive region. Photoresist layer  320  and thermal oxide  312  on the bottom and sides of pit  304  are stripped and wafer  300  is cleaned ( 628 ). 
     In this embodiment, front-end fabrication of transistors is started after the formation and doping of pit  302 . Referring to  FIGS. 11 and 15 , a photoresist layer  324  is deposited and lithography is performed to define regions  326  for a shallow trench isolation (STI) etch. Hard mask  308 , pad oxide  306 , and silicon substrate  302  are etched ( 632 ) in regions  326 . Photoresist layer  324  is stripped and wafer  300  is cleaned ( 634 ). Referring to  FIG. 16 , a liner oxide layer  328  and a silicon nitride etch stop layer (not shown) are grown ( 636 ) over the top surface of wafer  300 . A thick oxide layer  330  is deposited ( 638 ) using a high density plasma (HDP) deposition process or other deposition process. The thickness of thick oxide layer  330  is greater than the depth of pit  304 . Another layer of photoresist (not shown) is deposited and lithography is performed ( 640 ) to enable a reverse dry etch ( 642 ) of thick oxide layer  330 . The reverse etch process leaves thick oxide layer  330  only above pit  304  and in regions  326  to facilitate a subsequent CMP process. The photoresist layer is stripped and wafer  300  is cleaned ( 644 ). A CMP process and a clean are then performed ( 646 ) to flatten the surface of wafer  300 . Hard mask  308  and pad oxide  306  are stripped ( 648 ). At this point, CMOS transistors may be fabricated ( 650 ) following standard CMOS procedures until reaching the n-MOS (or p-MOS) source/drain (S/D) implant steps. 
     Referring to  FIGS. 11 and 17 , once the CMOS transistors (not shown) have been fabricated, a photoresist layer  332  is deposited onto wafer  300 . A lithography step is performed ( 652 ) to open regions  334  in locations suitable for generating a bottom contact for the photodetector. A high dose n+ (or p+, depending on the electrode orientation of the photodetector) S/D implant is performed ( 654 ) under conditions identical to those for a standard CMOS S/D implant process, forming n+ (or p+) regions  336 . Photoresist layer  332  is stripped, wafer  300  is cleaned ( 656 ), and n+ (or p+) regions  336  are activated ( 658 ). 
     Referring to  FIGS. 11 and 18 , a layer of tetraethylorthosilicate (TEOS) oxide  338  is then deposited ( 660 ) to isolate transistors when integrating the photodetector with a CMOS integrated circuit. To form the photodetector, another photoresist layer  340  is deposited and lithography is performed ( 662 ) to open the photoresist in a region above pit  304 . TEOS layer  338  and the portion of thick oxide layer  330  inside pit  304  are dry etched ( 664 ). Silicon nitride etch stop layer and liner oxide layer  328  at the base of pit  304  are wet etched ( 666 ). Photoresist layer  340  is stripped and wafer  300  is cleaned ( 668 ). Referring to  FIG. 19 , a germanium photodetector body  342  is selectively grown ( 670 ) within the etched opening in pit  304  to a thickness of between 0.5 μm to 2.5 μm. A layer  344  of polysilicon or amorphous silicon is deposited ( 672 ) on the surface of wafer  300 . 
     Referring to  FIGS. 11 and 20 , a photoresist layer  346  is deposited and lithography is performed ( 674 ) such that photoresist layer  346  remains only in the region above pit  304 . The layer  344  of polysilicon or amorphous silicon is etched ( 676 ) except in the region protected by photoresist layer  346 . The etch process is stopped at thick oxide layer  330 . Photoresist layer  346  is stripped and wafer  300  is cleaned ( 678 ). 
     Referring to  FIGS. 11 and 21 , the process to form metal plugs begins by depositing a photoresist layer  348  and performing a lithography process ( 680 ) to open desired regions  350  and  352  above photodetector body  342  and a p-well region (or n-well region), respectively. A high dose p+ implantation ( 682 ) of Boron (or an n+ implantation of Phosphorus or Arsenic) generates two p+ (or n+) regions  354  and  356 , shown in FIG.  22 . Photoresist layer  348  is stripped, wafer  300  is cleaned ( 684 ), and the implants in regions  354  and  356  are activated ( 686 ). A salicide blocking (SAB) layer  358  is deposited ( 688 ) over the entire top surface of wafer  300 . A photoresist layer (not shown) is deposited over SAB layer  358  and a lithography process is performed ( 690 ) to define areas for etching of SAB layer  358 . SAB layer  358  is etched ( 692 ) in the regions defined by the patterned photoresist, with the etch stopping at silicon substrate  302 . The etch process leaves SAB layer  358  in all but regions  360 . The photoresist layer is stripped and wafer  300  is cleaned ( 694 ), and regions  360  are converted to salicide ( 696 ). 
     Referring to  FIGS. 11 and 23 , a silicon nitride stop layer  364  and a thick interlayer dielectric (ILD) oxide  366  are deposited ( 698 ). ILD oxide  366  is planarized by a CMP process and wafer  300  is cleaned ( 700 ). A photoresist layer (not shown) is deposited and a lithography process ( 702 ) defines regions for metal contact plugs  368 . ILD oxide  366  is etched ( 704 ) in these regions, stopping at stop layer  364 ; stop layer  364  is then etched ( 706 ). The photoresist layer is stripped and wafer  300  is cleaned ( 708 ). A barrier layer (not shown) is deposited ( 710 ) within the etched regions and metal contact plugs  368  are formed ( 712 ) by depositing Tungsten into the etched regions. A CMP step ( 714 ) removes any Tungsten above the level of ILD oxide  366 . Wafer  300  is then cleaned and M1 structures and other back end structures are formed ( 716 ) following standard CMOS processing techniques. 
     Referring to  FIG. 24A , in an alternative embodiment, the photodetector and other integrated circuit components are fabricated on a silicon-on-insulator (SOI) wafer  400 . An SOI substrate  402  is composed of a handling silicon wafer  406 , an insulating SiO 2  layer  408 , and a top silicon layer  410 . The procedure for forming a pit  404  is substantially the same as the procedures described above. However, to form pit  404 , the top silicon layer  410 , the insulating SiO 2  layer  408 , and the handling silicon wafer  406  must all be etched. The base of pit  404  lies within handling silicon wafer  406 . A transistor  411  is fabricated either before or during the formation of pit  404 . After the formation of pit  404 , the implantation steps, the processing of detector body  412  (including the doping of bottom contact regions  414 ,  416 , and  418  and the deposition of a top contact  419  and an insulating layer  420 ) and the fabrication of metal plugs  422 , M1 structures, and other integrated circuit components proceeds as described above, resulting in a structure such as that shown in  FIG. 24B . 
     In a further embodiment, photon induced carriers in the photodetector body are collected horizontally rather than vertically. Referring to  FIG. 25A , two pits  504   a  and  504   b  are formed in a silicon substrate  502  covered with an oxide layer  506  using methods described above. A transistor  507  may also be fabricated. Two photodetector bodies  508   a  and  508   b , composed of either Si or SiGe, are grown in pits  504   a  and  504   b , respectively, as shown in  FIG. 25B . Portions of oxide layer  506  adjacent to photodetector bodies  504   a  and  504   b  are removed using wet etching or dry etching techniques to form trenches. Referring to  FIG. 25C , polysilicon or amorphous silicon is deposited into the trenches to form side contacts  510 . Further processing of metal plugs  512  and other integrated circuit components, as shown in  FIG. 25D , proceeds according to methods described above. In this configuration, photon induced carriers in photodetector bodies  508   a  and  508   b  are collected laterally by side contacts  510 . Such a configuration is useful for fabricating interdigitated lateral photodetectors. 
     Referring to  FIG. 26 , in some embodiments, a CMOS integrated circuit  800  incorporates a Ge or SiGe photodetector  802  with a companion amplification circuit  804 , which may include a transimpedance amplifier (TIA) and a limiting amplifier (LA), and a reshaping circuit  806 , such as a clock and data recovery circuit (CDR). Light  808  carrying a digital signal is transmitted through an optical fiber  810 , which couples the light  812  through the top of the CMOS integrated circuit  800  into on-chip photodetector  802 . Photodetector  802  converts the light signal to an electrical photocurrent  814 , which is amplified by amplification circuit  804  to be a voltage signal  816 . The clock and digital information carried by the original light signal is then recovered through CDR circuit  806  to produce an output signal  818 . CMOS integrated circuit may also include arrays  820  of photodetectors  802 , each photodetector having a companion amplification circuit  804  and reshaping circuit  806 , each photodetector receiving light from one of an array  822  of optical fibers  810 . This monolithically integrated optoelectronic circuit may be used as an optical receiver in an optical communication system. 
     Other embodiments are also within the scope of the invention. It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the following claims.