Abstract:
A semiconductor device includes a semiconductor chip, electrodes pads, insulating layer, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The insulating layer is formed on a second area of the semiconductor chip so as to expose the electrode pads. The first conductive patterns provides a ground potential and is formed on the insulating layer. The second conductive pattern transfers a signal. The second conductive pattern and is formed on the insulating layer and located between the first conductive patterns. The external terminals are formed on the first and second patterns at the second area.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to a semiconductor device having a package structure, and more particularly, relates to a semiconductor device having a WCSP type structure.  
         [0002]     The high integration of a semiconductor device mounted in an electronic device and the high frequency of a transmission signal have been expected increasingly in recent years. A CSP (Chip Size Package) serving as a semiconductor, which is packaged in an outline size substantially same as that of a semiconductor chip, has been proposed to cope with this expectation.  
         [0003]     In recent years, with a view of decreasing a manufacturing cost or the like, a technical development of a WCSP (Waferlevel Chip Size Package) has been promoted. The WCSP comprises a CSP, in which its external terminal formation process is completed in a waferlevel and is individualized by dicing.  
         [0004]     In this WCSP, there is known, as one example thereof, one having a structure such that an electrode pad and an external terminal, which are mounted on a semiconductor chip, are electrically connected via a wiring layer (a rewiring layer) for rearranging this external terminal in a desired position.  
         [0005]     In the WCSP having the above described rewiring layer, a degree of freedom in a wire design may be improved due to the rewiring layer.  
         [0006]     In the case of transmitting a high frequency signal by the use of the above described WCSP having the rewiring layer, it is desirable that, between a circuit element, which is provided to a semiconductor chip, and a signal line, namely, a rewiring layer to be electrically connected to the foregoing circuit element via an electrode pad, impedance of the both is matched.  
         [0007]     To get rid of a mismatch between the both enables attenuation of the transmission signal arising from the reflection or the like of the transmission signal generated in the vicinity of a joint between the electrode pad and the signal line to be restrained.  
         [0008]     However, regardless of that a characteristic impedance of the signal line in the WCSP is sufficiently larger than the impedance of the circuit element, an effective method has not been proposed to match the impedance between the both by decreasing the characteristic impedance of the signal line.  
       SUMMARY OF THE INVENTION  
       [0009]     A semiconductor device of the present invention includes a semiconductor chip, electrodes pads, insulating layer, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The insulating layer is formed on a second area of the semiconductor chip so as to expose the electrode pads. The first conductive patterns provides a ground potential and is formed on the insulating layer. The second conductive pattern transfers a signal. The second conductive pattern and is formed on the insulating layer and located between the first conductive patterns. The external terminals are formed on the first and second patterns at the second area. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  is a schematic plane view for showing a semiconductor device of a first embodiment according to the present invention;  
         [0011]      FIGS. 2A  to  2 C are a schematic plane view and a schematic cross sectional view for showing partially the semiconductor device of the first embodiment according to the present invention;  
         [0012]      FIGS. 3A  to  3 C are a schematic plane view and a schematic cross sectional view for showing partially the semiconductor device of a second embodiment according to the present invention;  
         [0013]      FIGS. 4A  to  4 C are a schematic plane view and a schematic cross sectional view for showing partially the semiconductor device of a third embodiment according to the present invention;  
         [0014]      FIGS. 5A  to  5 C are a schematic plane view and a schematic cross sectional view for showing partially the semiconductor device of a fourth embodiment according to the present invention;  
         [0015]      FIGS. 6A  to  6 C are a schematic plane view and a schematic cross sectional view for showing partially the semiconductor device of a fifth embodiment according to the present invention;  
         [0016]      FIGS. 7A  to  7 C are a schematic plane view and a schematic cross sectional view for showing partially the semiconductor device of a sixth embodiment according to the present invention;  
         [0017]      FIGS. 8A  to  8 D are a schematic plane view and a schematic cross sectional view for showing partially the semiconductor device of a seventh embodiment according to the present invention; and  
         [0018]      FIGS. 9A  to  9 D are a schematic plane view and a schematic cross sectional view for showing partially the semiconductor device of an eighth embodiment according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]     With reference to FIGS.  1  to  9 , the embodiments according to the present invention will be described below. Further, each drawing schematically illustrates a constitutional example of the semiconductor device according to the present invention. In addition, in each drawing, a shape, a size and an arrangement of each constitutional component are only schematically illustrated so as to allow the present invention to be understood, but the present invention is not limited to the examples shown in the drawings. In addition, in order to make the drawings understandable, hatching (i.e., a diagonal line) is omitted except for a part thereof. Further, in the following descriptions, a particular material and a particular condition or the like are used, however, these material and condition are merely preferable examples. Accordingly, the present invention is not limited to these. In addition, in each drawing, with respect to the identical parts, the identical reference numerals are given and the explanations thereof may be omitted.  
         [0020]     In addition, according to each embodiment to be described below, an individual CSP obtained by cutting the CSP in a waferlevel by means of dicing is referred to as a WCSP, and the present invention will be described with taking this WCSP as an example of the semiconductor device.  
         [0000]     [First Embodiment] 
         [0021]     With reference to  FIG. 1  and  FIGS. 2A  to C, a semiconductor device of the first embodiment according to the present invention will be described below.  FIG. 1  is a plane view for showing schematically a WCSP  10 , which is the semiconductor device of the present embodiment. In addition,  FIG. 2A  illustrates each constitutional element in detail as enlarging an A region, which is encircled by a broken line in the plane view shown in  FIG. 1  (hereinafter, in each embodiment, the drawings corresponding to  FIG. 1  are omitted and the description will be provided with reference to the drawings corresponding to this enlarged schematic view). In addition, in  FIG. 2B , a cut area (a cross section) to be acquired by cutting  FIG. 2A  along a broken line I-I′ is seen from an arrow I direction in  FIG. 2A . Further, in  FIG. 2C , a cut area (a cross section) to be acquired by cutting  FIG. 2A  along a broken line P-P′ is seen from an arrow P direction in  FIG. 2A  (the same is applied to the following respective embodiments). Further, in  FIG. 1  and  FIG. 2A , for convenience, the illustration of a sealing membrane  50  such as an organic resin membrane or the like, which is provided to the WCSP  10 , is omitted, and in  FIG. 1 , the illustration of a wiring layer  35  and a post portion  40  are also partially omitted.  
         [0022]     On a semiconductor chip  15 , which is provided to the WCSP  10  serving as the semiconductor device, electrode pads  20  made of aluminum (A1) are arranged at a regular interval along an outer circumference of the semiconductor chip  15 . According to the example shown in  FIG. 1 , a shape in plain view of the WCSP  10  is square, so that the electrode pads  20  are linearly arranged along the respective side of the square. In addition, the number and the position of the electrode pads  20  are not limited to this, and for example, only one set of the electrode pads  20  is arranged on the semiconductor chip  15 , where each thereof is opposed with each other.  
         [0023]     In addition, as shown in  FIGS. 2A and 2B , on the semiconductor chip  15  provided with the circuit element, insulating layers (this insulating layer is also referred to as a first insulating layer)  32  such as a passivation membrane  25  and a protection membrane  30 , are sequentially disposed so as to expose the surfaces of these electrode pads  20 . Further, for example, the passivation membrane  25  is formed by a silicon oxide film (SiO 2 ), and the protection membrane  30  is formed by a membrane material with a low degree of hardness such as a polyimide resin, so that it is possible to restrain the shock against the semiconductor chip  15  during manufacturing and the abruption of the insulating layers due to the stress between a sealing membrane  50  and the semiconductor chip  15 .  
         [0024]     Further, as shown in  FIG. 2A , respective electrode pads  20  ( 20   a ,  20   b ) are electrically connected to corresponding respective post portions  40  ( 40   a ,  40   b ) individually via respective dedicated wiring layers  35  ( 35   a ,  35   b ). This wiring layer  35  is elongated on the protection layer  30  in a center direction of the semiconductor chip  15  and is formed by a copper (Cu).  
         [0025]     More in detail, each of wiring layers  35  according to the present embodiment is connected to the electrode pad  20  corresponding to this wiring layers  35 , and further, the post portion  40  is formed on a surface elongated on a first insulating layer  32  among respective wiring layers  35 .  
         [0026]     Thus, by this wiring layer  35 , a solder ball (bump) (not illustrated), which is formed on this post portion  40  serving as an external terminal for connection to a mounting substrate, is capable of being disposed on a desirable position on a substantially horizontal plane, namely, a position at the upper side of the semiconductor chip  15  shifted from a right above position of the electrode pad  20  without depending on the position of the electrode pad  20 . Accordingly, this wiring layer  35  functions as a rewiring layer, which enables rearrangement of the external terminal (hereinafter, the wiring layer  35  may be refereed to as the rewiring layer).  
         [0027]     In addition, as shown in  FIGS. 2B and 2C , on the upper face side of the semiconductor chip  15 , the sealing membrane  50  such as an epoxy resin is formed so as to cover the passivation membrane  25  and the protection membrane  30  or the like and to expose the surface of the post portion ( 40   a ,  40   b ). Then, this post portion ( 40   a ,  40   b ) is connected to a solder ball  45  serving as the external terminal as a bump for connection to a print substrate (not illustrated).  
         [0028]     According to a connection structure of the wiring layer  35  shown in  FIG. 2A , by each of two first wiring layers  35   a , the connection between the first electrode pads  20   a  and the first post portions  40   a  is formed, respectively. Further, by the second wiring layer  35   b , the connection between the second electrode pad  20   b  and the second post portion  40   b  is formed. The first wiring layers  35   a  are also referred to as a GND wire or a GND layer since the grounding (GND) voltage is supplied thereto. In addition, the second wiring layer is also referred to as a signal line or a signal layer since an electric signal having a voltage based on the grounding (GND) voltage, namely, a high frequency signal (a variable potential signal) is supplied thereto. Further, the high frequency in this constitutional example means a frequency of a signal transmitted through the signal line having a length that is not so short with respect to an effective wave length of the operational frequency of the semiconductor chip.  
         [0029]     In this case, between a pair of first wiring layers  35   a , the second wiring layer  35   b  is placed on the upper surface of the protection membrane  30  so that the second wiring layer  35   b  does not contact each of the first wiring layers  35   a  with each other.  
         [0030]     In this way, the connection structure of these wiring layers shown in  FIG. 2A  comprises a coplanar line structure, in which the second wiring layer is placed with being sandwiched by two first wiring layers from the opposite sides thereof, when the first and second wiring layers are viewed two-dimensionally.  
         [0031]     In this coplanar line structure, the signal line  35   b  is sandwiched by the GND wire  35   a , so that the electromagnetic bond between the GND wire  35   a  and the signal line  35   b  is enhanced. As a result, a capacity between the GND wire  35   a  and the signal line  35   b  is increased and the impedance of the signal line is decreased, so that it is possible to decrease the characteristic impedance of the signal line  35   b  as compared to a conventional case.  
         [0032]     Therefore, the inventor of the present invention has a knowledge that the characteristic impedance to be decreased of this signal line  35   b  and the impedance of the circuit element may be matched particularly by considering the arranging position of the GND wire  35   a  as the rewiring layer.  
         [0033]     It is possible to match the characteristic impedance of this signal line  35   b  with the impedance of the circuit element mainly by adjusting a width of the GND wire  35   a  (represented by A in  FIG. 2C ), a width of the signal line  35   b  (represented by B in  FIG. 2C ), a thickness of the GND wire  35   a  (represented by d 1  in  FIG. 2C ), a thickness of the signal line  35   b  (represented by d 2  in  FIG. 2C ), a horizontal spacing between the GND wire  35   a  and the signal line  35   b  (represented by C in  FIG. 2C ), an electric resistivity ρ of the wiring layer  35  (here, a copper (Cu) is used as a formation material of the wiring layer  35 ), a dielectric constant ε (here, the dielectric constant ε of an epoxy resin  50  between the signal line  35   b  and the GND wire  35   a , which has a considerable impact on the characteristic impedance of the signal line  35   b ) of a dielectric layer around a conductive part (the wiring layer  35 , the electrode pad  20 , the post portion  40 ) on the semiconductor chip  15 , and a thickness (represented by d 3  in  FIG. 2C ) of a dielectric layer around the conductive part (here, the epoxy resin  50 ). Further, it is preferable that transmission efficiency is also considered when the formation material of the wiring layer  35  is a magnetic body.  
         [0034]     According to the constitutional example shown in  FIGS. 2A  to  2 C, the first and second electrode pads  20   a ,  20   b , and  20   a  are linearly placed in parallel and respective wiring layers  35   a ,  35   b , and  35   a  are linearly elongated from right above the electrode pad to respective post portions  40   a ,  40   b , and  40   a  in a direction orthogonal to the arranging direction of these electrode pads. Accordingly, in this case, the width of the signal line  35   b  (represented by B in  FIG. 2C ) indicates the width of a signal line portion (a portion represented by L in  FIG. 2B ) in the signal line  35   b  between a contact portion  351  with the second electrode pad  20   b  (refer to  FIG. 2B ) and a contact portion  352  with the external terminal  40   b  (refer to  FIG. 2B ) in the arranging direction of the electrode pads, when this constitutional example is seen two-dimensionally in  FIG. 2 A . In the same way, the width of the GND wire  35   a  (represented by A in  FIG. 2C ) indicates the width of the GND wire portion corresponding to L in  FIG. 2B  in the arranging direction of the electrode pads.  
         [0035]     Therefore, for example, in the case of making the characteristic impedance of the signal line  35   b  about 50 [Ω], which is nearly equal to the impedance of the circuit element provided to the semiconductor chip  15 , the characteristic impedance of the signal line  35   b  may be set so that, for example, A=200 [μm], B=40 [μm], d 1 =5 [μm], d 2 =5 [μm], C=23 [μm], ρ=1.67×10 −6  [Ωcm (20° C.)], and ε≅4 [F/m] and d 3 =90 [μm] are established.  
         [0036]     In this way, the width of each of the GND wire and the signal line and the spacing between the GND wire and the signal line depend on the electric resistivity of the formation materials of the GND wire and the signal line and the dielectric constant of the dielectric layer filled in the gap between the GND wire and the signal line.  
         [0037]     According to the above described setting conditions, the characteristic impedance of the signal line  35   b  can be made about 50 [Ω]. Accordingly, it is possible to get rid of a mismatch of the impedance between the signal line  35   b  and the circuit element provided to the semiconductor chip  15 .  
         [0038]     In other words, according to the present embodiment, a function to decrease the characteristic impedance of the signal line is further added to the wiring layer, which has been provided for rearranging the external terminal so far.  
         [0039]     As being apparent from the above descriptions, according to the present embodiment, matching of the characteristic impedance of the signal line  35   b  and the impedance of the circuit element provided to the semiconductor chip  15  is realized.  
         [0040]     Therefore, the transmission of the high frequency signal can be effectively realized, so that it is possible to obtain a semiconductor device having the high frequency property, which is superior to the conventional one.  
         [0000]     [Second Embodiment] 
         [0041]     With reference to  FIG. 3 , a semiconductor device of the second embodiment according to the present invention will be described below.  
         [0042]     The present embodiment is different from the first embodiment mainly in that the width of the GND wire  35   a  (=A) and the spacing (=C) between the GND wire  35   a  and the signal line  35   b  are set to be narrower as compared to the first embodiment. In addition, with respect to the constitutional elements, which are identical to those described in the first embodiment, the identical reference numerals are given and the specific explanations thereof may be omitted (the same is applied to the following respective embodiments).  
         [0043]     On the upper part of the semiconductor chip  15 , to which the high frequency signal is transmitted, for example, passive elements such as a coil and a capacitor are formed (not illustrated). Such passive elements come under the influence of an electromagnetic field to be radiated when the current is applied to the post portion  40  and the wiring layer  35 , so that the operation of an integrated circuit provided to the semiconductor chip  15  may get unstable.  
         [0044]     Therefore, as shown in  FIGS. 3A  to  3 C, according to the present embodiment, in the rewiring layer according to the first embodiment, the width of the signal line  35   b  (=B) and the spacing (=C) between the GND wire  35   a  and the signal line  35   b  are the same or nearly same as the case of the first embodiment, however, the width of the GND wire  35   a  (=A), which was considerably wider than that of the signal line  35   b  (=B), is set to be narrower.  
         [0045]     However, when the width of the GND wire  35   a  (=A) is narrower, the electromagnetic bond between the GND wire  35   a  and the signal line  35   b  is weaken. Accordingly, an electric charge capacity between the GND wire  35   a  and the signal line  35   b  is decreased, so that the inductance is increased.  
         [0046]     As a result, since the characteristic impedance of the signal line is a square root of a value obtained by dividing the inductance by the capacity, the characteristic impedance of the signal line  35   b  is increased by making the width of the GND wire  35   a  (=A) narrower.  
         [0047]     Therefore, according to the present embodiment, by setting the spacing (=C) between the GND wire  35   a  and the signal line  35   b  to be narrower as compared to the first embodiment, increase in the characteristic impedance of the signal line  35   b  is restrained.  
         [0048]     Therefore, in the case of making the characteristic impedance of the signal line  35   b  about 50 [Ω], which is nearly equal to the impedance of the circuit element provided to the semiconductor chip  15 , the characteristic impedance of the signal line  35   b  may be set so that, for example, A=100 μm, B=40 [μm], d 1 =5 [μm], d 2 =5 [μm], C=22 [μm], ρ=1.67×10 −6  [Ωcm (20° C.)], and ε≅4 [F/m] and d 3 =90 [μm] are established.  
         [0049]     According to the above described setting conditions, it is possible to get rid of a mismatch of the impedance between the signal line  35   b  and the circuit element provided to the semiconductor chip  15 .  
         [0050]     As being apparent from the above description, it is possible to obtain the same advantage as the first embodiment.  
         [0051]     Further, according to the present embodiment, the undesirable mutual interaction between the GND wire  35   a  serving as the rewiring layer and the integrated circuit provided to the semiconductor chip  15  is restrained, so that the semiconductor device having a higher reliability can be obtained.  
         [0000]     [Third Embodiment] 
         [0052]     With reference to  FIGS. 4A  to  4 C, a semiconductor device according to the third embodiment of the present invention will be described below.  
         [0053]     The present embodiment is different from the first embodiment in that two GND wires  35   a  are placed so as to encircle the signal line  35   b.    
         [0054]     In order to further decrease the transmission loss of the high frequency signal, to say nothing of the characteristic impedance of the signal line  35   b , it is preferable that the characteristic impedance of each constitutional element of a conductive part formed on the semiconductor chip  15  (for example, the electrode pad  20 , the post portion  40  and the solder ball (external terminal)  45  or the like) is matched with the impedance of the circuit element.  
         [0055]     Therefore, according to the present embodiment, as shown in  FIG. 4A , in a planar arrangement, the sides, which are not connected to the first electrode pad  20   a  of two GND wires  35   a  sandwiching the signal line  35   b  from the opposite sides thereof, namely, the terminals at the sides to be connected to the first post portions  40   a  are coupled so as to encircle the signal line  35   b  and the second post portion  40   b  to be connected to the signal line  35   b , so that a bond wiring layer is formed.  
         [0056]     Therefore, for example, in the case of making the characteristic impedance of the signal line  35   b  about 50 [Ω], which is nearly equal to the impedance of the circuit element provided to the semiconductor chip  15 , for example, as in the first embodiment, a setting condition of each portion is determined (refer to  FIG. 4C ) and further, the GND wire  35   a  is integrally formed in a U character extending from one electrode pad  20   a  to other electrode pad  20   a . Then, this GND wire  35   a  encircles the signal line  35   b  and the second post portion  40   b  to be connected to this signal line  35   b  in a U character. In addition, each first post portion  40   a  is capable of being connected to the U-shaped GND wire  35   a  in the midstream thereof.  
         [0057]     As a result, as shown in  FIGS. 4A and 4B , as compared to the first embodiment, the GND wire  35   a  is widely arranged in the vicinity of the second post portion  40   b  to be connected to the signal wire  35   b.    
         [0058]     In this way, by conforming the width of each of the GND wire  35   a  and the signal line  35   b  and the spacing between the GND wire  35   a  and the signal line  35   b  to the above described setting conditions, it is possible to get rid of a mismatch of the impedance between the signal line  35   b  and the circuit element provided to the semiconductor chip  15 .  
         [0059]     As being apparent from the above description, according to the present embodiment, it is possible to obtain the same advantage as that of the first embodiment.  
         [0060]     Further, according to the present embodiment, as compared to the first embodiment, the characteristic impedance of the post portion  40  is decreased, so that the semiconductor device having a higher reliability can be obtained, which enables the transmission loss of the high frequency signal to be further restrained.  
         [0000]     [Fourth Embodiment] 
         [0061]     With reference to  FIGS. 5A  to  5 C, a semiconductor device according to the forth embodiment of the present invention will be described below.  
         [0062]     The present embodiment is different from the second embodiment mainly in that the GND wire  35   a  is provided so as to encircle the signal line  35   b  as same as the third embodiment.  
         [0063]     Therefore, for example, in the case of making the characteristic impedance of the signal line  35   b  about 50 [Ω], which is nearly equal to the impedance of the circuit element provided to the semiconductor chip  15 , for example, as the second embodiment, a setting condition of each portion is determined (refer to  FIG. 5C ) and further, the GND wire  35   a  is integrally formed in a U character extending from one electrode pad  20   a  to other electrode pad  20   a . Then, this GND wire  35   a  encircles the signal line  35  band the second post portion  40   b  to be connected to this signal line  35   b  in a U character. In addition, each first post portion  40   a  is capable of being connected to the U-shaped GND wire  35   a  in the midstream thereof.  
         [0064]     As a result, as shown in  FIGS. 5A and 5B , as compared to the second embodiment, the GND wire  35   a  is widely arranged in the vicinity of the second post portion  40   b  to be connected to the signal wire  35   b.    
         [0065]     In this way, by conforming the width of each of the GND wire  35   a  and the signal line  35   b  and the spacing between the GND wire  35   a  and the signal line  35   b  to the above described setting conditions, it is possible to get rid of a mismatch of the impedance between the signal line  35   b  and the circuit element provided to the semiconductor chip  15 .  
         [0066]     As being apparent from the above description, according to the present embodiment, it is possible to obtain the same advantage as that of the second embodiment.  
         [0067]     Further, according to the present embodiment, as compared to the second embodiment, the characteristic impedance of the post portion  40  is decreased, so that the semiconductor device having a higher reliability can be obtained, which enables the transmission loss of the high frequency signal to be further restrained.  
         [0000]     [Fifth Embodiment] 
         [0068]     With reference to  FIGS. 6A  to  6 C, a semiconductor device according to the fifth embodiment of the present invention will be described below.  
         [0069]     The present embodiment is different from the fourth embodiment mainly in that, while the width of the GND wire  35   a  (=A) is set narrower, the spacing between the GND wire  35   a  and the signal line  35   b  (=C) is not narrowed and the GND wire  35   a  and the signal line  35   b  are embedded in a dielectric layer having a larger dielectric constant than that of the sealing membrane  50  (here, the epoxy resin with the dielectric constant ε≅4 [F/m]).  
         [0070]     Therefore, according to the present embodiment, the GND wire  35   a  and the signal line  35   b  are embedded in a dielectric layer  55  made of a phenol resin (here, the dielectric constant ε≅4.5 to 5 [F/m]) (refer to  FIGS. 6A  to  6 C).  
         [0071]     By embedding the dielectric layer  55  between the GND wire  35   a  and the signal line  35   b , the electromagnetic bond between the both is more enhanced as compared to the case that the epoxy resin  50  is embedded therebetween.  
         [0072]     Accordingly, it is possible to decrease the characteristic impedance of the signal line  35   b  to be increased by narrowing the width of the GND wire  35   a  (=A) by means of this dielectric layer  55 .  
         [0073]     Further, according to the present embodiment, the dielectric layer  55  is provided so as to cover the full upper surface of the semiconductor chip  15  except for the post portion  40 , and at least, the dielectric layer  55  may be provided so as to fill the gap between the GND wire  35   a  and the signal line  35   b  from one GND wire  35   a  sandwiching the signal line  35   b  across the other GND wire  35   a , because the capacity between the GND wire  35   a  and the signal line  35   b  can be increased considerably at least by enhancing the electromagnetic bond between the both. As a result, it is possible to effectively decrease the characteristic impedance of the signal line  35   b.    
         [0074]     Therefore, for example, in the case of making the characteristic impedance of the signal line  35   b  about 50 [Ω], which is nearly equal to the impedance of the circuit element provided to the semiconductor chip  15 , the characteristic impedance of the signal line  35   b  may be set so that, for example, A=100 μm, B=40 μm, d 1 =5 [μm], d 2 =5 [μm], C=23 μm, ρ=1.67×10 −6  [Ωcm (20° C.)], and ε≅4.5 to 5 [F/m] and d 3 =90 [μm] are established.  
         [0075]     According to the above described setting conditions, it is possible to get rid of a mismatch between the signal line  35   b  and the circuit element provided to the semiconductor chip  15 .  
         [0076]     As being apparent from the above description, according to the present embodiment, it is possible to obtain the same advantage as that of the fourth embodiment.  
         [0000]     [Sixth Embodiment] 
         [0077]     With reference to  FIGS. 7A  to  7 C, a semiconductor device according to the sixth embodiment of the present invention will be described below.  
         [0078]     The present embodiment is different from the third embodiment mainly in that the GND wire  35   a  is provided in a mesh.  
         [0079]     As shown in  FIG. 7A , when the GND wire  35   a  is formed in a mesh, an occupied area of the GND wire  35   a  itself is capable of being reduced, so that, as described above, the undesirable mutual interaction between the GND wire  35   a  serving as the rewiring layer and the integrated circuit provided to the semiconductor chip  15  is restrained.  
         [0080]     Therefore, for example, in the case of making the characteristic impedance of the signal line  35   b  about 50 [Ω], which is nearly equal to the impedance of the circuit element provided to the semiconductor chip  15 , the characteristic impedance of the signal line  35   b  may be set so that, for example, A=20 μm (this is a width of mesh), B=40 μm, d 1 =5 [μm], d 2 =5 [μm], C=22 [μm], ρ=1.67×10 −6  [Ωcm (20° C.)], and ε≅4 [F/m] and d 3 =90 [μm] are established.  
         [0081]     According to the above described setting conditions, it is possible to get rid of a mismatch between the signal line  35   b  and the circuit element provided to the semiconductor chip  15 .  
         [0082]     As being apparent from the above description, according to the present embodiment, it is possible to obtain the same advantage as that of the third embodiment.  
         [0083]     Further, according to the present embodiment, when the GND wire  35   a  is formed in a mesh, the undesirable mutual interaction between the GND wire  35   a  serving as the rewiring layer and the integrated circuit provided to the semiconductor chip  15  is restrained. As a result, the semiconductor device having a higher reliability can be obtained.  
         [0000]     [Seventh Embodiment] 
         [0084]     With reference to  FIGS. 8A  to  8 D, a semiconductor device according to the seventh embodiment of the present invention will be described below. In  FIG. 8D , a cut area (across section) to be acquired by cutting  FIG. 8A  along a broken line Q-Q′ is seen from an arrow P direction in  FIG. 8A .  
         [0085]     Therefore, as shown in  FIG. 8A , the wiring layer of the present embodiment has a micro strip line structure, in which the GND wire  35   a  is provided so as to cover the signal line  35 , for example, via a dielectric layer (here, this dielectric layer is also referred to as a second insulating layer)  60 , which is formed by the polyimide membrane.  
         [0086]     More in detail, as shown in  FIGS. 8A  to  8 D, on the semiconductor chip  15 , a first insulating layer  32  and a second insulating layer  60  are mounted. Further, the second insulating layer  60  is mounted on this first insulating layer  32 . An upper surface of a first electrode pad  20   a  is exposed from the first and second insulating layers ( 32 ,  60 ), and the second electrode pad  20   b  is exposed from the first insulating layer  32 . Further, solder balls  45  formed on first and second post portions ( 40   a ,  40   b ) serving as an exterior terminal for connection to a mounting substrate are arranged with being shifted to the upper side of the semiconductor chip  15  from directly above the first and second electrode pads ( 20   a ,  20   b ), respectively. In addition, in this case, the second post portion  40   b  is mounted on a signal line  35   b , which is placed on the first insulating layer  32 . The side surface of this second post portion  40   b  is covered by the second insulating layer  60  and the resin seal  50 . In addition, the first post portion  40   a  is mounted on the GND wire  35   a  placed on the second insulating layer  60 . The side surface of this first post portion  40   a  is covered by the resin seal  50 . Then, the first and second post portions ( 40   a ,  40   b ), as described above according to the first to sixth embodiments, is derived to the surface of the sealing membrane  50  to be connected to the solder ball  45  serving as the exterior terminal.  
         [0087]     According to the present embodiment, the signal line  35   b  to be connected to the second electrode pad  20   b  is elongated on the protection membrane  30 , namely, the first insulating layer  32  in a center direction of the semiconductor chip  15  to be electrically connected to the second post portion  40   b.    
         [0088]     On the other hand, the GND wire  35   a  to be connected to the first electrode pad  20   a  is elongated from the first electrode pad  20   a  to this first electrode pad  20   a  in a vertical direction, and then, the GND wire  35   a  is continuously provided across the surface of a dielectric layer  60  covering the semiconductor chip  15  so as to expose the surface of the second post portion  40   b  and is electrically connected to the first post portion  40   a.    
         [0089]     In this way, in the micro strip line structure, which is provided so that the signal line  35   b  and the GND wire  35   a  are superposed with each other, as same as the coplanar line structure, the signal line  35   b  is provided with being sandwiched by the GND wires  35   a , so that the electromagnetic bond between the GND wires  35   a  and the signal line  35   b  is enhanced. As a result, the capacity between the GND wires  35   a  and the signal line  35   b  is increased and the inductance of the signal line is decreased, so that it is possible to more decrease the characteristic impedance of the signal line  35   b  as compared to the conventional case.  
         [0090]     Further, in the micro strip line structure, the GND wires  35   a  is placed with being more separated from the semiconductor chip  15  as compared to the coplanar line structure.  
         [0091]     Therefore, it is possible to restrain the undesirable mutual interaction between the GND wire  35   a  and the integrated circuit provided to the semiconductor chip  15  more effectively.  
         [0092]     Further, according to the present embodiment, the second insulating layer, namely, the dielectric layer  60  is provided so as to cover the full upper surface of the semiconductor chip  15  except for the second post portion  40   b , and at least, the second insulating layer may be provided so as to cover the signal line  35   b , because the capacity between the GND wire  35   a  and the signal line  35   b  can be increased considerably at least by enhancing the electromagnetic bond between the both. As a result, it is possible to effectively decrease the characteristic impedance of the signal line  35   b . In addition, as described according to the first embodiment, two GND wires  35   a  may be elongated along the signal line  35   b  at the opposite sides thereof and may be continuously provided so as to reach the surface of the dielectric layer  60 .  
         [0093]     More in detail, it is possible to match the characteristic impedance of this signal line  35   b  with the impedance of the circuit element provided to the semiconductor chip  15  mainly by adjusting a width of the GND wire  35   a  (represented by A in  FIGS. 8C and 8D ), a width of the signal line  35   b  (represented by B in  FIG. 8C ), a thickness of the GND wire  35   a  (represented by d 1  in  FIG. 8C ), a thickness of the signal line  35   b  (represented by d 2  in  FIG. 8C ), a vertical spacing between the GND wire  35   a  and the signal line  35   b  (represented by C′ in  FIGS. 8C and 8D ), an electric resistivity ρ of the wiring layer  35  (the wiring layers  35   a ,  35   b ) (here, a copper (Cu) is used as a formation material of the wiring layer  35 ), a dielectric constant ε (here, the dielectric constant ε of a polyimide membrane  60  between the signal line  35   b  and the GND wire  35   a , which has a considerable impact on the characteristic impedance of the signal line  35   b ) of a dielectric layer around a conductive part (the electrode pad  20 , the post portion  40 ) on the semiconductor chip  15 , and a thickness (represented by d 4  in  FIG. 8C ) of a dielectric layer around the conductive part (here, the polyimide membrane  60 ). Further, it is preferable that transmission efficiency is also considered when the formation material of the wiring layer  35  is a magnetic body.  
         [0094]     Therefore, for example, in the case of making the characteristic impedance of the signal line  35   b  about 50 [Ω], which is nearly equal to the impedance of the circuit element provided to the semiconductor chip  15 , the characteristic impedance of the signal line  35   b  may be set so that, for example, A=400 μm, B=40 μm, d 1 =5 [μm], d 2 =5 [μm], C′=33 μm, ρ=1.67×10 −6  [Ωcm (20° C.)], and ε≅3.3 [F/m] and d 4 =38 [μm] are established.  
         [0095]     According to the above described setting conditions, the characteristic impedance of the signal line  35   b  can be made about 50 [Ω]. Accordingly, it is possible to get rid of a mismatch of the impedance between the signal line  35   b  and the circuit element provided to the semiconductor chip  15 .  
         [0096]     As being apparent from the above description, according to the present embodiment, matching of the characteristic impedance of the signal line  35   b  and the impedance of the circuit element provided to the semiconductor chip  15  is realized. Therefore, the transmission of the high frequency signal can be effectively realized, so that it is possible to obtain a semiconductor device having the high frequency property, which is superior to the conventional one.  
         [0000]     [Eighth Embodiment] 
         [0097]     With reference to  FIGS. 9A  to  9 D, a semiconductor device according to the eighth embodiment of the present invention will be described below.  
         [0098]     The present embodiment is mainly different from the seventh embodiment in that, in place of the insulating layer  60  according to the seventh embodiment, a dielectric layer  65  having a higher dielectric constant than that of this insulating layer  60  is used as the second insulating layer.  
         [0099]     According to the present embodiment, as the dielectric layer  65  in place of the dielectric layer  60  (the polyimide membrane (a dielectric constant ε≅3.3 [F/m]) according to the seventh embodiment, a phenol resin (a dielectric constant ε≅4.5 to 5 [F/m]) is provided.  
         [0100]     Therefore, for example, in the case of making the characteristic impedance of the signal line  35   b  about 50 [Ω], which is nearly equal to the impedance of the circuit element provided to the semiconductor chip  15 , the characteristic impedance of the signal line  35   b  may be set so that, for example, A=400 μm, B=40 μm, d 1 =5 [μm], d 2 =5 [μm], C′=35 μm, ρ=1.67×10 −6  [Ωcm (20° C.)], and ε≅4.5 to 5 [F/m] and d 4 =38 [μm] are established.  
         [0101]     According to the above described setting conditions, it is possible to obtain the same advantage as that of the seventh embodiment.  
         [0102]     Further, according to the present embodiment, the dielectric layer having the higher dielectric constant as compared to the seventh embodiment, namely, the second insulating layer  65  is disposed between the signal line  35   b  and the GND wire  35   a.    
         [0103]     As a result, it is possible to further enlarge the vertical spacing between the signal line  35   b  and the GND wire  35   a  (represented by C′ in the drawing) as compared to the seventh embodiment.  
         [0104]     Therefore, the undesirable mutual interaction between the GND wire  35   a  serving as the rewiring layer and the integrated circuit provided to the semiconductor chip  15  is restrained, so that the semiconductor device having a higher reliability can be obtained.  
         [0105]     As described above, the present invention is not limited to the combination of the above described embodiments. Therefore, at the arbitrary preferable stage, it is possible to combine the preferable conditions and apply the present invention.  
         [0106]     Further, by providing this signal line  35   b  so that the signal line length of the signal line  35   b  is not more than quarter of the effective wave length of the operational frequency of the semiconductor chip, the attenuation of the transmission signal arising from the reflection or the like is capable of being effectively restrained.  
         [0107]     As being apparent from the above description, according to the semiconductor device of the present embodiment, matching of the characteristic impedance of the signal line and the impedance of the circuit element is realized more effectively as compared to the conventional case.  
         [0108]     Therefore, it is possible to realize the transmission of the high frequency signal effectively and the semiconductor device having the high frequency property, which is superior to the conventional one, may be acquired.