Abstract:
Charge pump circuitry ( 30 ) compares bottom plate voltages of first (C 1 ) and second (C 2 ) flying capacitors in a current mode charge pump ( 1 B) to a reference value (V DD −V 28 ) by means of a comparator ( 20 ) which drives a flip-flop ( 22 ) that generates first (F 1 ) and second (F 2 ) complementary phase signals. The first and second phase signals control switching of the flying capacitors to determine a flying capacitor swapping frequency just low enough to prevent saturation of a discharge current source (I 0 ) that discharges the flying capacitors into an output conductor ( 3 ).

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates generally to integrated charge pump circuits, and more particularly to improvements therein which reduce power consumption and which reduce the amount of integrated circuit chip area required. 
         [0002]    Use of an on-chip charge pump in an integrated circuit operational amplifier to bootstrap an input stage tail current source thereof provides an increased rail-to-rail common mode input voltage range of the operational amplifier. The boosted output voltage produced by the charge pump needs to have a low ripple voltage because the ripple voltage causes noise in the tail current which then propagates to the output of the operational amplifier. It is desirable that the on-chip charge pump consume as little current and power as possible. 
         [0003]      FIG. 1  shows a low-ripple, on-chip current mode charge pump that has been used in the assignee&#39;s OPA365 operational amplifier, which is believed to be the closest prior art. In  FIG. 1 , an integrated circuit  1 A includes a current mode charge pump circuit  1 B which produces a boosted output voltage Vout. Vout is applied to bias a current source that functions as the tail current source of the input stage of an operational amplifier (not shown). Current mode charge pump  1 B includes an operational amplifier  4  that functions as a feedback amplifier. The (+) input of feedback amplifier  4  is connected by a conductor  6  to the (+) terminal of a voltage source  5 , the (−) terminal of which is connected to the positive rail voltage source V DD , whereby a reference voltage Vref is produced on conductor  6 . Voltage source  5  may produce a constant voltage of about 1 volt, and can be implemented in various ways, for example by means of the gate-to-source voltage V GS  of a P-channel MOS transistor and a circuit including a resistor and a current source (not shown). (Since the voltage source  5  must operate at voltages higher than V DD , the source of the P-channel transistor would be coupled through the resistor and the current source to Vout, with the gate and drain of the P-channel transistor being connected to V DD .) The (−) input of feedback amplifier  4  is connected to conductor  3 , on which the charge pump output voltage Vout is produced. The output of feedback amplifier  4  is connected by conductor  8  to the control terminals of two essentially identical controlled current sources  7  and  9  which produce a “discharge current” I 0  and a “recharge current” I 1 , respectively. The upper terminal of each of controlled current sources  7  and  9  is connected to V DD . 
         [0004]    The lower terminal of discharge current source  7  is connected by conductor  12  to one terminal of each of switches S 1  and S 5 . The other terminal of switch S 1  is connected by conductor  13  to the “bottom” plate of a flying capacitor C 1  and to one terminal of a switch S 2 , the other terminal of which is connected to a conductor  2 , on which a supply voltage such as V SS  is applied. The “upper” plate of flying capacitor C 1  is connected by conductor  14  to one terminal of each of switches S 3  and S 4 . The other terminal of switch S 3  is connected by conductor  15  to the lower terminal of recharge current source  9 . The other terminal of switch S 4  is connected to charge pump output conductor  3 . The lower terminal of recharge current source  9  is connected by conductor  15  to one terminal of switch S 7 . The other terminal of switch S 7  is connected by conductor  18  to the top plate of a second flying capacitor C 2  and to one terminal of a switch S 8 , the other terminal of which is connected to Vout conductor  3 . The bottom plate of flying capacitor C 2  is connected by conductor  17  to one terminal of each of switches S 5  and S 6 . The other terminal of switch S 6  is connected to V SS  conductor  2 . The other terminal of switch S 5  is connected to conductor  12 . A voltage V DISCHARGE  on conductor  12  is equal to either the bottom plate voltage Vc 1  of flying capacitor C 1  or the bottom plate voltage Vc 2  of flying capacitor C 2 . 
         [0005]    An internal bypass capacitor C 0  is connected between Vout conductor  3  and V DD . A load  19  which draws a load current I L  is connected between Vout conductor  3  and V SS , and can be either internal or external to integrated circuit chip  1 A. Typically, an external oscillator  10 A generates a phase signal F 1  and its logical complement F 2 . Phase signal F 1  controls switches S 1 , S 4 , S 6 , and S 7  and phase signal F 2  controls switches S 2 , S 3 , S 5 , and S 8 . 
         [0006]    Flying capacitors C 1  and C 2  are alternately recharged and alternately discharged into Vout conductor  3  so as to produce an essentially constant value of output voltage Vout. In the example of  FIG. 1 , Vout is used to control the tail current of an operational amplifier (not shown) wherein the gate-to-source voltage V GS  of a MOS transistor (not shown) which functions as a tail current source needs to be equal to a reference voltage Vref that is roughly 1 volt above the positive rail voltage V DD  and is generated by means of voltage source  5 . The various switches of charge pump  1 B typically are implemented by means of MOS transistors and are controlled such that one of the flying capacitors C 1  and C 2  is always connected by a switch to the output Vout except during short switching transitions. The value of the discharge current I 0  and the recharge current I 1  is determined by the feedback loop including amplifier  4 , with Vout as its inverting input and the voltage Vref on conductor  6  as its non-inverting input. 
         [0007]    If various components, including controlled current sources I 0 , I 1  and operational amplifier  14  are ideal, then the discharging current I 0  and the recharging current I 1  are equal to the load current I L , and Vout is essentially constant (except for a relatively small ripple voltage component) during the flying capacitor discharge process. This is because the feedback loop including feedback amplifier  4  and controlled current sources  7  and  9  adjusts I 0  and I 1  so as to cause Vout to be precisely equal to Vref as a result of each of flying capacitors C 1  and C 2  being alternately connected to charge pump output conductor  3  and being discharged to load  19  by discharge current I 0  from controlled current source  7 , while the other flying capacitor is being recharged by the same amount of current I 1  from controlled current source  9 . 
         [0008]    Typically, external oscillator  10 A is used to cause the “swapping” of flying capacitors C 1  and C 2  to occur at a frequency just above the bandwidth of the above mentioned operational amplifier (not shown) that includes input tail current source  26 . The “swapping” of flying capacitors C 1  and C 2  refers to alternately switching their functions from being recharged by I 1  to being discharged by I 0 . 
         [0009]    However, the foregoing technique is not optimal from a power efficiency standpoint because the flying capacitor swapping frequency needs to be based on worst-case values of flying capacitors C 1  and C 2 , V DD , and load current I L . During the switching transitions between phases F 1  and F 2 , charge pump  1  consumes energy being used to recharge the switch gate capacitances of MOS transistors (not shown) which are typically used to implement switches S 1 , S 2 , . . . S 8  and to recharge parasitic capacitances Cp 1  and Cp 2  associated with flying capacitors C 1  and C 2 . 
         [0010]    Consequently, the power consumption of charge pump circuitry  1 B is directly proportional to the frequency of phase signals F 1  and F 2  and is inversely proportional to the capacitance of flying capacitors C 1  and C 2 . 
         [0011]    In existing products including prior art charge pump  1 B of  FIG. 1 , switching between pulses of phase signals F 1  and F 2  is typically controlled by external oscillator  10 A. The frequency of external oscillator  10 A typically has to be chosen for the worst-case combination of power supply values, charge pump load current value, and high resistances and capacitances of on-chip frequency-setting resistors and capacitors which typically have at least a 15% variation in value due to process parameter variation. 
         [0012]    The bottom plate voltage Vc 1  or Vc 2  of the flying capacitor presently being discharged by discharge current I 0  increases as the parasitic capacitance Cp 1  or Cp 2  associated with that flying capacitor is charged up, but the bottom plate voltage Vc 1  or Vc 2  cannot exceed V DD . The worst case capacitance value of flying capacitors C 1  and C 2  is selected in accordance with the worst case values of load current I L , the charge pump supply voltage, and Vout. 
         [0013]    As a practical matter, the flying capacitor values must be at least twice the values required for charge pump operation with nominal values of the various circuit parameters. Every time the flying capacitor functions are effectively swapped, some energy is lost or wasted because it is necessary to recharge one of the parasitic capacitors Cp 1  or Cp 2 . The current necessary to recharge parasitic capacitors Cp 1  or Cp 2  is in effect lost. Therefore, it is desirable that the capacitor swapping frequency be as small as possible, and it also is desirable to reduce integrated circuit chip area and cost by making the flying capacitors as small as possible, and it also is desirable to decrease the parasitic components Cp 1  and Cp 2  of the flying capacitors by making their capacitances as small as possible. 
         [0014]    Thus, there is an unmet need for an improved integrated circuit charge pump circuit which operates more efficiently than the closest prior art charge pump circuits having comparable low noise performance. 
         [0015]    There also is an unmet need for an improved integrated circuit charge pump circuit which requires less integrated circuit chip area than the closest prior art charge pump circuits having comparable low noise performance. 
       SUMMARY OF THE INVENTION 
       [0016]    It is an object of the invention to provide an improved integrated circuit charge pump circuit which operates more efficiently than the closest prior art charge pump circuits having comparable low noise performance. 
         [0017]    It is another object of the invention to provide an improved integrated circuit charge pump circuit which requires less integrated circuit chip area than the closest prior art charge pump circuits having comparable low noise performance. 
         [0018]    Briefly described, and in accordance with one embodiment, the present invention provides charge pump circuitry ( 30 ) that compares bottom plate voltages of first (C 1 ) and second (C 2 ) flying capacitors in a current mode charge pump ( 1 B) to a reference value (V DD −V 28 ) by means of a comparator ( 20 ) which drives a flip-flop ( 22 ) that generates first (F 1 ) and second (F 2 ) complementary phase signals. The first and second phase signals control switching of the flying capacitors to determine a flying capacitor swapping frequency just low enough to prevent saturation of a discharge current source (I 0 ) that discharges the flying capacitors into an output conductor ( 3 ). 
         [0019]    In one embodiment, the invention provides charge pump circuitry ( 30 ) including a current mode charge pump circuit ( 1 B) having first (C 1 ) and second flying (C 2 ) capacitors and various associated switches operative in response to first (F 1 ) and second (F 2 ) phase signals which are of opposite phase, first ( 7 ) and second ( 9 ) controlled current sources, and a feedback amplifier ( 4 ) all coupled so as to generate a boosted output voltage (Vout). Self-oscillating circuitry ( 10 B) includes a comparison circuit ( 20 ) having first and second inputs and an output (V 21 ), a flip-flop circuit ( 22 ) having a clock input ( 21 ) coupled to the output (V 21 ) of the comparison circuit ( 20 ) and first and second outputs producing the first (F 1 ) and second (F 2 ) phase signals, respectively. The current mode charge pump circuit ( 1 B) produces a discharge signal (V DISCHARGE ) representative of first (Vc 1 ) and second (Vc 2 ) bottom plate voltages alternately produced on the first (C 1 ) and second (C 2 ) flying capacitors. The comparison circuit output (V 21 ) indicates times at which the first (Vc 1 ) and second (Vc 2 ) bottom plate voltages approach to within a predetermined voltage (V 28 ) of a first supply voltage (V DD ) of the charge pump circuitry ( 30 ). The first input (+) of the comparison circuit ( 20 ) receives the discharge signal (V DISCHARGE ). 
         [0020]    In a described embodiment, the comparison circuit includes a comparator ( 20 ) and a voltage source ( 28 ) coupled between the second (−) input of the comparison circuit ( 20 ) and the first supply voltage (V DD ). The flip-flop circuit ( 22 ) is configured to perform a divide-by-two function. 
         [0021]    In the described embodiment, the voltage source ( 28 ) generates a voltage of sufficient magnitude to prevent saturation of the first controlled current source ( 7 ). The self-oscillating circuitry ( 10 B) is powered by the first supply voltage (V DD ) and a LDO (low drop out) regulator ( 11 ). 
         [0022]    In one embodiment, the invention provides a method for operating charge pump circuitry ( 30 ) to generate a boosted output signal (Vout), including comparing a discharge signal (V DISCHARGE ) produced in a current mode charge pump ( 1 B) to a reference value (V DD −V 28 ) by means of a comparison circuit ( 20 ) producing an output signal (V 21 ) having edges indicative, respectively, of times at which the discharge signal (V DISCHARGE ) rises above the reference value (V DD −V 28 ) and times at which the discharge signal (V DISCHARGE ) falls below the reference value (V DD −V 28 ), the discharge signal (V DISCHARGE ) being representative of first (Vc 1 ) and second (Vc 2 ) bottom plate voltages alternately produced on first (C 1 ) and second (C 2 ) flying capacitors of the current mode charge pump ( 1 B); applying the output signal (V 21 ) of the comparison circuit ( 20 ) to an input of a flip-flop ( 22 ); generating first (F 1 ) and second (F 2 ) complementary phase signals by means of the flip-flop ( 22 ); and applying the first (F 1 ) and second (F 2 ) phase signals to control electrodes of various switches that control operation of the first (C 1 ) and second (C 2 ) flying capacitors to generate the discharge signal (V DISCHARGE ). The reference value (V DD −V 28 ) approximately minimizes the frequency of the first (F 1 ) phase signal and also avoid saturation of a controlled current source (I 0 ) of the current mode charge pump ( 1 B). 
         [0023]    In one embodiment, the invention provides current mode charge pump circuitry ( 30 ), including means ( 20 ) for comparing a discharge signal (V DISCHARGE ) produced in a current mode charge pump ( 1 B) to a reference value (V DD −V 28 ) by means of a comparison circuit ( 20 ) producing an output signal (V 21 ) indicative of times at which the discharge signal (V DISCHARGE ) rises above the reference value (V DD −V 28 ) and times at which the discharge signal (V DISCHARGE ) falls below the reference value (V DD −V 28 ), the discharge signal (V DISCHARGE ) being representative of first (Vc 1 ) and second (Vc 2 ) bottom plate voltages alternately produced on first (C 1 ) and second (C 2 ) flying capacitors of the current mode charge pump ( 1 B); means ( 22 ) for generating first (F 1 ) and second (F 2 ) complementary phase signals in response to the output signal (V 21 ) of the comparison circuit ( 20 ); and means for applying the first (F 1 ) and second (F 2 ) phase signals to control electrodes of various switches (S 1 ,  2  . . .  8 ) which control circuit connections of the first (C 1 ) and second (C 2 ) flying capacitors to generate the discharge signal (V DISCHARGE ) to thereby determine a flying capacitor swapping frequency of the current mode charge pump ( 1 B). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIG. 1  is a schematic diagram of a prior art charge pump circuit. 
           [0025]      FIG. 2  is a schematic diagram of a self-oscillating charge pump circuit according to the present invention. 
           [0026]      FIG. 3  is a timing diagram that indicates details of the operation of the optimally self-oscillating charge pump circuit of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0027]    The present invention provides an energy-efficient way of creating an accurate on-chip, low-noise voltage source by providing differential current-mode charge pump circuitry wherein swapping of the flying capacitors is based on the bottom plate voltage (i.e., V DISCHARGE  in Prior Art  FIG. 1 ) of the flying capacitor presently being discharged. The resulting “self-oscillation” ensures the lowest possible flying capacitor swapping frequency for any particular load on the charge pump circuit and any particular supply voltage. 
         [0028]      FIG. 2  shows an integrated circuit including a self-oscillating charge pump  30 , the output voltage Vout of which can be applied via conductor  3  to an on-chip utilization circuit  26 , such as the previously mentioned tail current source of an operational amplifier. Self-oscillating charge pump  30  includes the current mode charge pump  1 B of Prior Art  FIG. 1  along with a phase signal generating circuit  10 B which includes a comparison circuit. The comparison circuit may be a comparator including built-in offset circuitry. Alternatively, the comparison circuit may include a comparator  20  coupled between V DD  and V SS  with its (−) input coupled to the (−) terminal of a voltage source  28  having its (+) terminal connected to V DD . 
         [0029]    A power supply voltage V SS  may be applied to conductor  2  of current mode charge pump  1 B of  FIG. 1 , or alternatively, a regulated reference voltage V LDO  may be applied to conductor  2 . V LDO  may be generated by a conventional LDO (low drop out) voltage regulator  11  connected between V DD  and V SS . LDO voltage regulator  11  may be external to integrated circuit chip  1 A or it may be included in the same integrated circuit chip with self-oscillating charge pump  30 . Use of LDO voltage regulator  11  decreases the amount of clock signal leakage noise that propagates to the output Vout. (Every time switching of the flying capacitors occurs in charge pump  1 B, a large pulse of current flows through the source of the power supply voltage V DD  and causes a power supply ripple voltage due to parasitic resistances and integrated circuit wire bond inductance. That power supply ripple voltage propagates through the charge pump circuitry and causes an undesirable noise component on the charge pump output signal Vout.) 
         [0030]    The (+) input of comparator  20  is connected to receive the discharge voltage V DISCHARGE  produced on conductor  12  ( FIG. 1 ) by current mode charge pump  1 B. Comparator  20  produces an output signal V 21  on conductor  21 , wherein V 21  is a “0” if V DISCHARGE  is less than V DD  minus the voltage V 28  of voltage source  28  and is a “1” if V DISCHARGE  is greater than V DD  minus the voltage V 28  of voltage source  28 . V 21  is applied to the clock input of a D-type flip-flop  22 . The Q output of flip-flop  22  produces the phase signal F 1 , which is applied to the control electrodes of various switches of current mode charge pump  1 B as shown in  FIG. 1 . The  Q  output of flip-flop  22  produces the phase signal F 2 , which is connected to various switches of current mode charge pump  1 B as shown in  FIG. 1 , and also is connected to the D input of flip-flop  22 , thereby causing it to function as a positive-edge-triggered divide-by-two circuit. 
         [0031]    The power consumption of charge pump  30  of  FIG. 2  is reduced by forcing it to self-oscillate at the lowest possible operational frequency for any particular circuit parameters, such as V DD , load current I L , and the bandwidth of the above mentioned operational amplifier that includes the above mentioned tail current source. The instants at which each swapping of the flying capacitor discharge and recharge functions occurs are defined by the voltage Vc 1  or Vc 2  at the bottom plate of the flying capacitor presently coupled by switch S 4  or S 8  to Vout conductor  3 . That is, the instant at which each swapping occurs is defined by the voltage V DISCHARGE  on conductor  12 , which is coupled by either switch S 1  or S 5  to the bottom plate of the flying capacitor presently coupled to Vout. 
         [0032]    V 28  has a value at which current source I 0  becomes close to saturation and cannot deliver current any longer. Therefore, as V DISCHARGE  approaches V DD −V 28 , current source I 0  tends to saturate and therefore no longer is capable of accurately delivering the load current and accurately maintaining Vout equal to Vref. Accordingly, the present invention provides a way of swapping the functions of flying capacitors C 1  and C 2  at a minimum swapping frequency in a way that preserves the accuracy of self-oscillating charge pump  30 . 
         [0033]    Specifically, in self-oscillating charge pump  30  the functions of flying capacitors C 1  and C 2  are swapped only when their respective bottom plate voltages Vc 1  and Vc 2  are increased to V 28 , for example to 150 millivolts below positive rail voltage V DD , because controlled current source  7  can not accurately provide discharge current I 0  when V DISCHARGE  is closer than approximately 150 millivolts to V DD . The bottom plates of flying capacitors C 1  and C 2  are switched to produce discharge voltage V DISCHARGE  on conductor  12  when either switch S 1  or S 5  is closed so as to cause the discharge and recharge functions of flying capacitors C 1  and C 2  to be swapped before discharge current source  7  begins to saturate. Comparator  20  compares discharge voltage V DISCHARGE  of the bottom plate of the flying capacitor C 1  or C 2  presently being discharged by I 0  such that V 21  goes from a “0” level to a “1” level when V DISCHARGE  exceeds V DD −150 millivolts. That causes flip-flop  22  to change state and thereby reverse the complementary logic levels of phase signals F 1  and F 2 . That in turn switches the connections of flying capacitors C 1  and C 2  so as to swap their functions of being discharged and recharged. 
         [0034]    For example, when flying capacitor C 2  is almost completely discharged at the end of the present F 2  pulse, then its top plate  18  is disconnected from Vout conductor  3  and is connected by switch S 7  so as to receive recharge current I 1  via conductor  15  from recharge current source  9 . At the same time, bottom plate  17  of capacitor C 2  is connected by switch S 6  to V LDO . Essentially simultaneously with that, the top plate  14  of flying capacitor C 1  is connected by switch S 4  to Vout and its bottom plate  13  is connected by switch S 1  so as to receive discharge current I 0  via conductor  12  from discharge current source  7 . Then discharge current I 0  begins to charge parasitic capacitor Cp 1  and thereby discharge capacitor C 1  into Vout conductor  3  until capacitor C 1  is nearly completely discharged and V DISCHARGE  has increased to V DD −150 millivolts, as indicated by the Vc 1  section of the V DISCHARGE  waveform of  FIG. 3 . That in turn causes the output V 21  of comparator  20  to go from a “0” level to a “1” level. That causes flip-flop  22  to reverse the logic levels of phase signals F 1  and F 2  and thereby reverse the discharge and recharge functions of flying capacitors C 1  and C 2 . 
         [0035]    Thus, discharge current I 0  is always simultaneously discharging one of the two flying capacitors and recharge current I 1  is always recharging the other flying capacitor except during the short switching transitions of pulses of complementary phase signals F 1  and F 2 , and feedback amplifier  4  continuously determines and controls the value of the equal currents I 0  and I 1  needed in order to maintain Vout equal to Vref. 
         [0036]    Thus, at every instant at which V DISCHARGE  becomes equal to V DD −150 millivolts, output V 21  of comparator  20  goes from a “0” to a “1” level, thereby forcing flip-flop  22  to change its state. This causes the bottom plate of the previously recharged flying capacitor to be connected between Vout and causes discharge current source I 0  to discharge that flying capacitor into Vout on conductor  3 , and also causes the bottom plate of the other flying capacitor to be connected between recharge current source I 1  and V LDO  to recharge the latter capacitor. 
         [0037]    For example, assume flying capacitor C 1  is being discharged by I 0  flowing through switch S 1  into parasitic capacitance Cp 1  and into bottom plate  13  of capacitor C 1 , boosting Vc 1  toward V DD  by forcing charge stored in capacitor C 1  through switch S 4  into Vout conductor  3 , and therefore also boosting V DISCHARGE  toward V DD  as indicated by reference  40  in  FIG. 3  because switch S 1  is closed. Then bottom plate  17  of flying capacitor C 2  is connected to V LDO  through switch S 6  and I 1  simultaneously is recharging C 2  through switch S 7 . When V DISCHARGE  reaches V DD −150 millivolts as indicated by point  41  in  FIG. 3 , the output V 21  of comparator  20  rapidly goes from a “0” to a “1” level as indicated by rising pulse edge  42  in  FIG. 3 , causing flip-flop  22  to change state and reverse the logic levels of phase signals F 1  and F 2  as indicated at points  45  and  46  in  FIG. 3 . These new levels of phase signals F 1  and F 2  open switches S 1 , S 4 , S 6 , and S 7  and close switches S 2 , S 3 , S 5 , and S 8 , thereby connecting bottom plate  13  of flying capacitor C 1  to V LDO  through switch S 2  and connecting top plate  14  of capacitor C 1  to I 1  through switch S 3 , and thereby causing C 1  to be recharged. Bottom plate  17  of C 2  is connected to I 0  through switch S 5  and top plate  18  is connected to Vout conductor  3  through switch S 8 . That it is, the discharge function and recharge functions of flying capacitors C 1  and C 2  have been swapped. 
         [0038]    Consequently, V DISCHARGE  falls rapidly toward V LDO , as indicated by reference numeral  50  in  FIG. 3 . At the same time, flying capacitor C 2  is discharged by I 0  into Vout as parasitic capacitance Cp 2  is charged and C 1  is recharged by I 1 . This causes Vc 2  to rise toward V DD , which causes V DISCHARGE  to also rise toward V DD  as indicated by reference numeral  51  in  FIG. 3  until V DISCHARGE  reaches V DD −150 millivolts as indicated by point  52 . This causes V 21  to again go from a “0” to a “1” level as indicated by reference numeral  55 , causing flip-flop  22  to change state again and thereby again reverse the logic levels of phase signals F 1  and F 2 , thereby again swapping the discharge and recharge functions of C 1  and C 2 . 
         [0039]    The same process continues to be repeated as long as self-oscillating charge pump  30  continues to be powered up. The timing of the low amplitude noise glitches of Vout also are shown in  FIG. 3 . 
         [0040]    Thus, flying capacitors C 1  and C 2  of charge pump  30  are swapped only when it is necessary to maintain accurate charge pump operation by ensuring that current source  7  does not saturate, thereby essentially minimizing the flying capacitor swapping frequency and thereby decreasing the overall power consumption of charge pump  30  of  FIG. 2 . 
         [0041]    If initially the voltage V LDO  on conductor  2  is close to the positive rail, then the circuit of A 2  will not start. To avoid this problem, the clock input of flip-flop  22  may be coupled to suitable circuitry which forces it to change state after the elapsing of a certain amount of time which is significantly larger than the worst-case normal operating period of self-oscillating charge pump  30 . For example, if self-oscillating circuit  10 B of  FIG. 2  gets “stuck” due to the voltage on conductor  2  being too close to V DD , then flip-flop  22  can be forced to change state in various ways, whereupon it will continue to self-oscillate. For example, a low frequency oscillator (not shown) could be used to ensure that flip-flop  22  changes state after elapsing of a predetermined time interval, and an AND/OR gate or the like could be coupled between the output V 21  of comparator  20  and the clock input of flip-flop  22  so that if V 21  does not switch from a “0” level to a “1” level within the predetermined time interval, then the foregoing low-frequency oscillator causes flip-flop  22  to change state to thereby initiate self-sustaining self-oscillation of charge pump circuit  30 . 
         [0042]    The present invention provides increased circuit operating efficiency and reduced amounts of required chip area for integrated charge pump circuits. 
         [0043]    While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. Of course, the boosted output voltage Vout produced by the integrated circuit  10 B of  FIG. 2  could be utilized for purposes other than controlling a tail current source. Constant voltage sources  5  and  28  can have suitable values other than those disclosed herein.