Abstract:
A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value. That portion of main memory containing the slot positions is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a nonvolatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the table to the card option registers if the status of all the slots has not not changed since the last power-down, system reset, or channel reset.

Description:
This application is a continuation of 07/296,387 filed Jan. 6, 1989, now U.S. Pat. No. 5,038,320, which is a continuation of 07/021,391 filed Mar. 13, 1987 which is now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     Users of smaller computer systems typically do not have sophisticated programming skills, and user-transparent programmable parameter switches have been suggested to simplify configuration of the systems to the user&#39;s needs. However, the routines that are required to so configure such systems are complex, error prone, and time consuming. It is an objective of the present improvement to substantially reduce the time delay experienced by a user before he can do productive work on the system upon re-powering or resetting of the system after a power-down, so long as no cards are changed in, added to, or removed from the slots. 
     SUMMARY OF THE INVENTION 
     In the improved system, each card type is provided a unique ID, which value is hardwired on each card. A register is also provided on the card to store parameter data such as an address factor (to programmably change the I/O address space of the card where required), priority, status, and other system information providing for the efficient transfer of data between the system processor and the card, and between cards. 
     When two or more of the same card type are used in the system, parameter data may be used to permit use of the cards at different priority levels or to render redundant cards inactive. 
     One portion of main memory is provided with battery backup to power that portion when system power fails or is turned off. Positions in this nonvolatile portion of memory are provided (one for each I/O slot) to store the ID values of the cards inserted in the respective slots together with the respective card parameter data. 
     When the system is first configured and initialized, a complex routine is executed to create and/or fetch all of the parameter data required for the cards attached to the system, to resolve system resource conflicts and to store the data into the appropriate card registers and the memory slot positions. 
     However, if after a power-down, no change is made in the cards attached to the slots or in the slot positions of the cards, a simplified setup routine determines that no change has been made by comparing each card ID with the ID value stored in the respective slot position. Then the routine transfers the parameter data from the memory slot positions to the respective card registers; and the system is ready for normal operation. 
     After the system is configured and initialized, a feedback line is provided to signal the use of the select mechanism during normal operation. Routines are invoked to check the response of each card to given select resources to detect duplicate use of a select resource. 
    
    
     These and other features of the present improvement will be apparent from the following detailed description and accompanying drawings, in which: 
     FIG. 1 is a fragmentary block diagram of the improved system; 
     FIG. 2 illustrates the bus structure; 
     FIG. 3 show certain of the logic utilized by the setup routines; 
     FIG. 4 shows timings for certain of the logic of FIG. 3; 
     FIG. 5 shows logic utilized by test routines to check the proper selection of an I/O card; and 
     FIGS. 6 and 7 are flowcharts which illustrate briefly the setup routines used in the present system. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 illustrates a preferred embodiment of the present improvement in the form of an integrated circuit desktop type computer system featuring user-transparent establishment of addressing and other variable system resource parameters for attached peripheral options. Thus the user is not burdened with having to set dip switches, follow complex setup procedures, etc. System resource conflicts are reduced or eliminated by reassigning of parameters. Other parameters include priority levels and a state bit which allows for coexistence of two identical option attachments. 
     System board 1 contains plural sockets or slots 2-0 to 2-7 into which I/O option cards 5-0 to 5-7 may be interchangeably plugged. These cards control various types of peripheral devices (disk drives, printers, etc.) and add-on memory which are either integrally contained on respective cards or attached thereto via external connectors, not shown. Board 1 also contains elements of the central processing system, including a central processor unit (CPU) 8, random access memory (RAM) main memory modules 9, 10, 11, direct memory access (DMA) controls 12, timing controls 13, slot address decoder 14, whose function is described below, other logical elements not relevant to the present discussion indicated collectively at 15, power supply 16, and bus 17 which links the central processing elements with each other and with attached peripherals. Darkened portions of the bus represent plural address lines 17b, data lines 17c, and control lines 17a (FIG. 2). 
     A feature hereof is that slots 2-0 to 2-7 can be addressed by &#34;slot address&#34; signals on the address lines of bus 17 during setup routines, and cards residing in the slots can be separately addressed by &#34;I/O address&#34; signals on the address lines during normal program execution; where the slot addresses and I/O addresses are distinctly different values associated respectively with physical locations of the sockets and with the types of devices currently attached. Many different types of devices are each potentially attachable to any one of the few sockets of the system. 
     One of the memory modules, module 10 in the illustration, is nonvolatile, and stores information relative to each of the slots 2-0 to 2-7 and its associated card when the system is powered down. This module for example, may consist of an array of capacitive storage circuits, i.e., known complimentary metal-oxide silicon (CMOS) type semiconductor circuits, configured to operate under system power while the system is powered up and under battery power 18 in the absence of system power. Within this module, a separately addressable space is allocated to each slot, for storing certain information relative to the slot. As shown, this information includes an identity value ID, an addressing factor AD, a priority value PR, a state bit S, and other information O. 
     A feature to be described is the use of this information in the nonvolatile memory to speed up initialization (FIG. 7) of the system when the slot configuration has not changed since the last power-down, and thereby reduce the time the user has to wait to begin useful applications after operating the system power-on switch, not shown, or after system or channel reset. This difference in complexity and number of steps required is illustrated by FIGS. 6 (initialization) and 7 (POST). 
     Details of card 5-7 are indicated as representative of the relevant logical organizations of all cards to the extent required for describing the present improvement. Driver circuits 20 are pre-wired at manufacture, and under conditions described below transmit a set of identity signals ID which uniquely identify that card type and its respective peripheral device. 
     Register 21 stores parameter information for controlling communications between the card and the system, including the address factor AD, the priority value PR, the state bit S, and other information O described with respect to module 10. This information is set by the central system during power-up initialization (FIG. 6). A feature of the system is that, if slot conditions have not changed since the last power-down of the system, the information is simply transferred to register 21 from the nonvolatile memory 10 in a relatively fast operation (FIG. 7), whereas if slot conditions have changed the system is required to perform a lengthy program process (FIG. 6) to retrieve and/or develop some or all of the information and then transfer it to both memory 10 and the card register 21. 
     Control logic 22 and decode logic 23 control response of the card 5-7 to I/O addresses appearing on bus 17. When power is applied to the system, the cards are addressable initially only through their sockets, and a portion of the address bus. But after the power-up process, the value AD in register 21 controls decoder 23 to detect a default or alternate I/O address associated uniquely to the card type and unrelated to the socket location. Upon such detection, the priority value PR and state bit S in conjunction with control logic 22 determine when data may be exchanged between the card and the bus 17. One manner in which an AD value, the decoder 23 and logic 22 detect an I/O address is shown and described in Interfacing to the IBM Personal Computer by L. Eggebrecht published 1983 at pages 130, 131. 
     In operation, during its power-up sequence the central system individually addresses the option sockets, by sending respective &#34;slot address&#34; signals on the bus which are uniquely detected by decoder 14 and result in separate activation of setup (or enable card) lines EC0-EC7 extending to respective sockets 2-0 to 2-7 and through the sockets to attached cards 5-0 to 5-7. Upon activation of one such line, if the respective socket is vacant the hexadecimal value of FFFF is returned to the system which terminates further operation relative to that socket. However, if the socket contains a card, the activated line in conjunction with additional address signals on the bus 17 condition logic 22 on the respective card to cause drivers 20 to transmit the ID signals mentioned above which identify the respective card and device type. The system CPU compares the returned ID signals with the ID value stored in the location in memory 10 allocated to the respective slot, and sets an indication denoting whether the compared values are the same or different. This indication serves effectively as a branch condition for subsequent program processes which determine the action to be taken relative to the respective slot. 
     If the indication just mentioned represents a matching comparison, and conditions of all other slots have not changed, a subsequent program process will simply transfer the value of AD, PR, S, and O, which are currently stored in the associated location of memory 10 to the respective card for storage in its register 21. If the indication represents a non-matching comparison, and if the transmitted ID indicates that the respective slot contains a card, the processor 8 uses the transmitted ID and information gleaned from the other slots to retrieve and/or develop new AD, PR, S, and O values for the respective card using files describing card resource requirements and alternatives. After all card values are established, the values for each card are transferred in sequence first to the respective slot location in memory 10 and subsequently to the respective card register 21. 
     Mismatching comparisons occur when the state of the interrogated socket has been altered. The ID value stored in memory 10 relative to a socket which was vacant at last power-down is FFFF, and the ID value stored relative to a previously occupied socket is that of the card last occupying that slot. Thus, if a card is installed into a previously vacant slot or substituted for a card having a different ID, a mismatching comparison will occur causing the system to retrieve and/or develop new AD, PR, S, and O values for the responding card. 
     As noted above, the system cannot deal with mismatching indications until the states of all sockets have been ascertained. This is because the priority level, and in certain instances the address and state values, assigned to any card are relative to the cards in other slots. The address and state values are relative when two cards with the same identity ID are currently installed, either to provide redundant backup for device failure or to provide additional device capacity. In the latter instances, the state value can be used to place a backup device in an inactive state during normal system operation or the priority values can be used to allow both devices to operate fully but at different priority levels. 
     In the preferred embodiment, system information is stored in the eight slot positions (only three--30, 31, 32--are shown) of module 10 to accommodate up to eight feature cards 5-0 to 5-7. Each slot position is four bytes wide, twenty-eight bytes for seven feature cards. The card ID resides in the first two bytes and the switch (parameter) settings in the last two bytes. The corresponding ID and parameter data on each card resides in drivers 20 and register 21, respectively. 
     FIG. 3 shows schematically certain of the logic on the board 1 and feature card 5-7 used during setup routines to read out a card ID and store parameters in the register 21. With respect to FIG. 3, the hexadecimal I/O address values assigned to certain of the components on each of the feature cards is as follows: 
     096--socket select value (one byte) 
     100, 101--ID drivers 20 (two bytes) 
     102, 103--parameter register 21 (two bytes) 
     These are &#34;dummy&#34; addresses since they are used by the processor 8 to access I/O cards and components via the slots during setup operations. The address 096 selects the logic (gates 38, 39) of slot address decoder 14 for storing the card select value into slot register 40 and also for reading out the value, i.e., during diagnosis. Address lines A0 and A1 of FIG. 3 form the lower address values 00, 01, 02, and 03 for selecting the components 20 and 21, while a logical 1 signal on address line A2 provides the most significant digit value of 1. A0, A1, and A2 are coupled to appropriate bit lines of address bus 17b, FIG. 2. 
     FIG. 3 shows in more detail certain of the logic of the slot address decoder 14 and of the control logic 22 of card 7 which are used in the setup routines of FIGS. 6 and 7. It will be assumed for simplicity of discussion, that addressing of two bytes at a time, i.e., one cycle, is available and that two byte data transfers occurs on busses. Hence, decoding address 101 gates both bytes for addresses 101 and 100. 
     Slot register 40 is program controlled to store a three bit value (000-111) corresponding to a slot (2-0 to 2-7) to be accessed. A decode circuit 41 changes this three bit binary value to a one in eight line output but only when it is gated by a signal on input line 42. Each output line, such as EC7, is connected via the respective socket to the card held in the socket. When a decode circuit 43 decodes an address in the range 0100-0103 during a setup routine, it produces an output on line 42 to gate the value in 40 to cause an output (see FIG. 4) on a card setup line such EC7, one of the control lines 17a of bus 17. 
     This output on EC7 is applied to AND gates 44 and 45. The address line A2 is coupled to gates 44 and 45. An I/O read line IOR and an I/O write line IOW (decoded from control lines 17a) are coupled respectively to gates 44 and 45. An output 46 from gate 44 is coupled to a pair of decoder circuits 47 and 48. An output 49 from gate 45 is coupled to a decode circuit 50. An output 51 from decode 48 is coupled to the ID driver circuit 20 and the output 52 from decode 50 is coupled to the parameter register 21. 
     During the post setup routine of FIG. 7, when an ID is being fetched from card 7, the processor 8 forces A2 negative (logical 1) and A1, A0 to logic 01 (address 101). EC7 is negative (FIG. 4). When IOR goes negative, the gate 44 produces an output at 46 to produce an output at 51 which gates the card ID value in 20 to data bus 17c. Processor 8 compares this ID with the ID in the respective slot position in memory module 10. If the IDs compare, processor 8 transfers the parameter values in the slot position 32 (FIG. 1) to data bus 17c and forces A2, A1, A0 to logic 111 (address 103). Shortly thereafter, processor 8 issues an IOW to cause gate 45 to produce an output on 49. This gates an output from 50 to register 21 via line 52 to gate the parameter values on bus 17c into register 21. The output 53 of decode 47 is used during diagnostic routines to gate the output of parameter register 21 to bus 17c via gate 54. 
     As discussed above with respect to a setup routine, an ID of hexadecimal value FFFF is returned during an ID fetch operation when the addressed socket is empty. One method of achieving this result is shown in FIG. 3. A pre-wired circuit 60 is gated to force bus 17 to all &#34;1&#39;s&#34; during the IOR cycle by a negative going signal on any one of the enable card lines EC1 to EC7 via OR circuit 61 and the negative going signal on IOR. If a card is in the socket which has been addressed, its ID is gated to bus 17c at the same time and all logical 0s in the ID override the logical 1s from 60 to correctly reproduce the ID on bus 17c. 
     The logic of FIG. 3 is used in a similar manner during the initialization setup and the POST setup routines of FIGS. 6 and 7. 
     When two identical cards (same ID) are connected to two of the I/O slots and it is desired to render both active, the first card is assigned the standard I/O default address at one priority level and the other card is assigned an alternate I/O address at a different priority level. 
     The logic of FIG. 5 is then utilized during a diagnostic routine to ascertain whether each card properly responds to its respective I/O address. The address decode logic 23 decodes the address on bus 17b if it corresponds to the alternate address when the appropriate alternate address factor AD is stored in parameter register 21 and the least significant bit is on (the card is active). Similarly, a priority decode circuit 55 produces an output if the priority value on bus 17a is equal to PR in register 21 and the card active bit is on. If outputs are produced by logic 23 and 55, an AND gate 56 produces a feedback signal on line 57 to set one bit in a register 58 on the board 1. The CPU8 under program control will read register 58 to determine that one and only one card properly responded to the I/O alternate address and reset register 58. Similar circuits on the other identical card will respond to the default I/O address and the appropriate priority level to set another bit in register 58 for diagnostic purposes. 
     While there have been described what are at present considered to be a preferred embodiment of this invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention, and it is, therefore, intended to cover all such changes and modifications as fall within the true spirit and scope of the invention.