Abstract:
An apparatus for aligning semiconductor wafers includes equipment for positioning a first surface of a first semiconductor wafer directly opposite to a first surface of a second semiconductor wafer and equipment for aligning a first structure on the first semiconductor wafer with a second structure on the first surface of the second semiconductor wafer. The aligning equipment comprises at least one movable alignment device configured to be moved during alignment and to be inserted between the first surface of the first semiconductor wafer and the first surface of the second semiconductor wafer. The positioning equipment are vibrationally and mechanically isolated from the alignment device motion.

Description:
CROSS REFERENCE TO RELATED CO-PENDING APPLICATIONS  
       [0001]    This application claims the benefit of U.S. provisional application Ser. No. 61/041,629 filed Apr. 2, 2008 and entitled “APPARATUS AND METHOD FOR SEMICONDUCTOR WAFER ALIGNMENT”, the contents of which are expressly incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]    The present invention relates to an apparatus and a method for semiconductor alignment, and more particularly to an interwafer wafer-to-wafer alignment that provides nanometer range alignment accuracy. 
       BACKGROUND OF THE INVENTION  
       [0003]    Alignment of semiconductor wafers is usually achieved by utilizing mechanical or optical fiducial marks, such as notches at the edges of wafers, pins, e-beam etchings, or holographic images, among others. Mechanical alignment marks provide millimeter range alignment accuracy, while optical marks provide micron to submicron alignment accuracy. 
         [0004]    In several semiconductor processes, such as 3-D integration, bonding and mask alignment, among others, submicron to nanometer alignment accuracy is desirable. 
       SUMMARY OF THE INVENTION  
       [0005]    A wafer-to-wafer alignment apparatus and method according to this invention utilize microscopes that are inserted between two wafers to be aligned parallel to each other. This “interwafer” alignment method can be used for any type of wafer material, transparent or not transparent, uses visible light and does not require fiducial marks at the back of the wafers. The alignment accuracy is of the order of a few hundred nanometers. In general, in one aspect, the invention features an apparatus for aligning semiconductor wafers including equipment for positioning a first surface of a first semiconductor wafer directly opposite to a first surface of a second semiconductor wafer and equipment for aligning a first structure on the first semiconductor wafer with a second structure on the first surface of the second semiconductor wafer. The aligning equipment comprises at least one movable alignment device configured to be moved during alignment and to be inserted between the first surface of the first semiconductor wafer and the first surface of the second semiconductor wafer. 
         [0006]    Implementations of this aspect of the invention may include one or more of the following features. The positioning equipment are vibrationally and mechanically isolated from the alignment equipment. The apparatus may further include an inverted U-shaped frame and a vibration isolated base. The inverted U-shaped frame is supported on a top surface of the base. The inverted U-shaped frame includes left and right vertical columns and a horizontal beam comprising left and right ends. Each of the column tops comprises two parallel vertical slots extending from the column top surface toward the column center and the two vertical slots are separated by a center block. The center block extends from the bottom of the slots toward the column top and has a height less than the height of the vertical slots thereby forming a gap between the two vertical slots near the column top surface. The left and right ends of the horizontal beam are supported upon the center blocks of the left and right vertical columns, respectively. The apparatus may further include an XYZ stage supporting the movable alignment device and the XYZ stage is configured to slide along the horizontal beam and be supported by the horizontal beam. The movable alignment device includes an optical microscope assembly including an elongated tube and first and second optical microscopes arranged coaxially within the elongated tube along a first axis. The first and second optical microscopes are configured to obtain first and second images of the first and second structures, respectively. The first and second images of the first and second structures are used to determine coordinates of the first and second structures relative to fixed top and bottom reference marks and to guide the positioning equipment for aligning the first surfaces of the first and second semiconductor wafers parallel to each other. The apparatus further includes a microscope calibration reference unit including fixed top and bottom reference marks. The calibration reference unit may be attached to one of the vertical columns. The optical microscope assembly may further include a mirror plane arranged so that the first axis is parallel to the mirror plane. The apparatus may further include pattern recognition software used to analyze the first and second images of the first and second structures, respectively, and to determine their coordinates relative to the fixed top and bottom reference marks. The positioning equipment includes a lower support block and an upper supporting block. The lower supporting block includes a lower wafer plate supporting the first semiconductor wafer and the upper supporting block includes an upper wafer plate supporting the second semiconductor wafer and a plate leveling system for leveling the upper wafer plate. The plate leveling system includes a spherical wedge error compensation mechanism that rotates and/or tilts the upper wafer plate around a center point corresponding to the center of the second semiconductor wafer without translation. The lower support block includes a coarse X-Y-T stage, an air bearing Z-stage carried by the coarse X-Y-T stage and a fine X-Y-T stage carried on top of the Z-stage, and wherein the X-Y-T fine stage carries the lower wafer plate. The X-Y-T coarse stage further includes one or more position sensors for measuring the X-Y-T distance between the coarse X-Y-T stage and the fine X-Y-T stage. The position sensors may be capacitance gauges. The upper and lower wafer plates comprise materials having a CTE matching the semiconductor wafer CTE. The apparatus may further include a fixture for transporting the first and second semiconductor wafers. The fixture includes an outer ring supporting a lower wafer carrier chuck and three or more clamp/spacer assemblies arranged at the periphery of the outer ring. Each of the clamp/spacer assemblies includes a clamp and a spacer. The clamp and the spacer are configured to be moved independent from each other and from the motion of clamps or spacers of the other assemblies and the motion is precise and repeatable both at room and high temperatures. The fixture further may further include a center pin for pinning together the centers of the first and second semiconductor wafers. The first semiconductor wafer is placed upon the lower wafer carrier chuck, the spacers are inserted on top of the edge of the first semiconductor wafer surface and then the second semiconductor wafer is placed on top of the spacers and then the first and second semiconductor wafers are clamped together via the clamps. 
         [0007]    In general, in another aspect, the invention features an apparatus for aligning semiconductor wafers including equipment for positioning a first surface of a first semiconductor wafer directly opposite to a first surface of a second semiconductor wafer and equipment for aligning a first structure on the first semiconductor wafer with a second structure on the first surface of the second semiconductor wafer. The aligning equipment includes at least one movable alignment device configured to be moved during alignment. The positioning equipment are vibrationally and mechanically isolated from the alignment device motion. 
         [0008]    In general, in another aspect, the invention features a method for aligning semiconductor wafers including positioning a first surface of a first semiconductor wafer directly opposite to a first surface of a second semiconductor wafer, providing alignment equipment comprising at least one movable alignment device and then aligning a first structure on the first semiconductor wafer with a second structure on the first surface of the second semiconductor wafer by inserting the movable alignment device between the first surface of the first semiconductor wafer and the first surface of the second semiconductor wafer. 
         [0009]    Implementations of this aspect of the invention may include one or more of the following features. The positioning step is vibrationally and mechanically isolated from the inserting of the movable alignment device between the first surface of the first semiconductor wafer and the first surface of the second semiconductor wafer. The movable alignment device includes an optical microscope assembly including an elongated tube and first and second optical microscopes arranged coaxially within the elongated tube along a first axis. The first and second optical microscopes are configured to obtain first and second images of the first and second structures, respectively. The first and second images of the first and second structures are used to determine coordinates of the first and second structures relative to fixed top and bottom reference marks and to guide the positioning equipment for aligning the first surfaces of the first and second semiconductor wafers parallel to each other. The apparatus further includes a microscope calibration reference unit including fixed top and bottom reference marks. The calibration reference unit may be attached to one of the vertical columns. The optical microscope assembly may further include a mirror plane arranged so that the first axis is parallel to the mirror plane. The method may further include providing pattern recognition software for analyzing the first and second images of the first and second structures, respectively, and determining their coordinates relative to the fixed top and bottom reference marks. The positioning step may include providing a lower support block comprising a lower wafer plate and placing the first semiconductor wafer upon the lower wafer plate and then providing an upper supporting block comprising an upper wafer plate for supporting the second semiconductor wafer and a plate leveling system for leveling the upper wafer plate. The plate leveling system may include a spherical wedge error compensation mechanism that rotates and/or tilts the upper wafer plate around a center point corresponding to the center of the second semiconductor wafer without translation. The lower support block includes a coarse X-Y-T stage, an air bearing Z-stage carried by the coarse X-Y-T stage and a fine X-Y-T stage carried on top of the Z-stage, and wherein the X-Y-T fine stage carries the lower wafer plate. The X-Y-T coarse stage further includes one or more position sensors for measuring the X-Y-T distance between the coarse X-Y-T stage and the fine X-Y-T stage. The apparatus may further include a fixture for transporting the first and second semiconductor wafers. The fixture includes an outer ring supporting a lower wafer carrier chuck and three or more clamp/spacer assemblies arranged at the periphery of the outer ring. Each of the clamp/spacer assemblies includes a clamp and a spacer. The clamp and the spacer are configured to be moved independent from each other and from the motion of clamps or spacers of the other assemblies and the motion is precise and repeatable both at room and high temperatures. The fixture further may further include a center pin for pinning together the centers of the first and second semiconductor wafers. The aligning of the first structure with the second structure includes the following steps. First, placing the first semiconductor wafer upon the lower support block with its first surface facing up. Next, supporting the second semiconductor wafer by the upper wafer plate with its first surface facing down. Next, inserting the optical microscope assembly into the fixed reference unit and focusing the first and second optical microscopes onto the fixed bottom and top reference marks, respectively. Next, using the pattern recognition software to determine position and distance of the fixed top and bottom reference marks and the mirror plane angular position. Next, inserting the optical microscope assembly between the first surfaces of the first and second semiconductor wafers, and focusing the second optical microscope onto the second structure of the second semiconductor wafer and then locking the optical microscope assembly position. Next, moving the coarse X-Y-T stage and Z-stage to focus the first microscope onto the first structure of the first semiconductor wafer and locking coarse X-Y-T and Z stages. Next, using the pattern recognition software to determine position coordinates of the first and second structures and determine their offsets. Finally, moving fine X-Y-T stage by the amount of the determined offsets and an amount determined by a global calibration method, thereby bringing the first and second structures in alignment with each other. The alignment of the first and second structures may further include the following. Moving the optical microscope assembly out from in between the first surfaces of the first and second semiconductor wafers and then moving the Z-stage up while maintaining the fine X-Y-T stage alignment with feedback from the position sensors. Next, bringing the first surface of the first semiconductor wafer in contact with the first surface of the second semiconductor wafer, then clamping the first and second semiconductor wafers together and then unloading the aligned first and second semiconductor wafers. After supporting the second semiconductor wafer by the upper wafer plate the method may further include moving the Z-stage up to bring the spacers on top of the first semiconductor wafer first surface in contact with the second semiconductor first surface. Next, performing wedge error compensation of the second semiconductor wafer under force feedback control and locking the wedge position and then moving the first semiconductor wafer down and removing the spacers. 
         [0010]    The details of one or more embodiments of the invention are set forth in the accompanying drawings and description below. Other features, objects and advantages of the invention will be apparent from the following description of the preferred embodiments, the drawings and from the claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0011]    Referring to the figures, wherein like numerals represent like parts throughout the several views: 
           [0012]      FIG. 1  is a schematic diagram of an aligner system according to this invention; 
           [0013]      FIG. 2  is a detailed side view of area P of  FIG.1 ; 
           [0014]      FIG. 3  is a schematic side view of the aligner system of  FIG. 1 ; 
           [0015]      FIG. 4  is a schematic diagram of the microscope system of  FIG. 1 ; 
           [0016]      FIG. 5  is a perspective view of the aligner apparatus according tot his invention; 
           [0017]      FIG. 6  is a perspective side view of the aligner apparatus of  FIG. 3 ; 
           [0018]      FIG. 7  is a front cross-sectional view of the aligner apparatus of  FIG. 3 ; 
           [0019]      FIG. 8  is a perspective top view of the microscope system of  FIG. 3 ; 
           [0020]      FIG. 9  is a perspective side view of the microscope system of  FIG. 8 ; 
           [0021]      FIG. 10  is a cross-sectional side view of the microscope system of  FIG. 8 ; 
           [0022]      FIG. 11  is detailed view of the two microscope systems within the aligner of  FIG. 8 ; 
           [0023]      FIG. 12  is a top view of the wafer fixture tool; 
           [0024]      FIG. 13  is a top view of the wafer fixture tool loaded with the top and lower plates; 
           [0025]      FIG. 14  is a schematic cross-sectional view of the wafer fixture tool loaded with the top and lower plates and wafers in the clamped position; 
           [0026]      FIG. 15  is a top view of the lower plate of the global calibration device; 
           [0027]      FIG. 16  is a side view of the top and lower plates of the global calibration device; 
           [0028]      FIG. 17  is a side view of the top and lower plates and transparent wafer of the global calibration device 
           [0029]      FIG. 18A-FIG .  18 B is a flow diagram of the alignment process; 
           [0030]      FIG. 19A  is a schematic diagram of step  610  of the alignment process of  FIG. 18B ; 
           [0031]      FIG. 19B  is a schematic diagram of step  611  of the alignment process of  FIG. 18B ; 
           [0032]      FIG. 19C  is a schematic diagram of step  613  of the alignment process of  FIG. 18B ; 
           [0033]      FIG. 20A  is a schematic diagram of steps,  608  and  611  of the alignment process of  FIG. 18A-FIG .  18 B; 
           [0034]      FIG. 20B  is a schematic diagram of steps,  608  and  612  of the alignment process of  FIG. 18A-FIG .  18 B; and 
           [0035]      FIG. 20C  is a schematic diagram of steps,  608  and  613  of the alignment process of  FIG. 18A-FIG .  18 B. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0036]    Referring to  FIG. 1-FIG .  5  a wafer alignment apparatus  100 , includes a base  102  supporting an inverted U-shaped frame  104 , first and second microscope sets  210   a,    210   b,  a lower wafer support block  150  supporting a lower wafer  80  and an upper wafer support block  180  holding an upper wafer  90 . Base  102  is made of a solid material and is supported on a table  106  via four vibration isolating legs  108   a,    108   b,    108   c,    108   d.  In one example, base  102  is a rectangular shaped block made of granite material. In other examples, base  102  may be made of metal or ceramic material and may have a honeycomb structure. The inverted U-shaped frame  104  includes left and right vertical legs  101 ,  103  respectively, and a beam  105  supported on the tops  113 ,  114  of the left and right legs  101 ,  103 , respectively. Each of the leg tops  113 ,  114  includes two vertical slots  111 ,  112  extending from the top surface  119  of the leg toward the center of the leg, as shown in  FIG. 2 . Vertical slots  111 ,  112  divide the top of each leg  101 ,  103 , respectively, into three separate block extensions  121 ,  122 ,  123 , also shown in  FIG. 2 . The ends  105   a,    105   b  of beam  105  are fixedly attached to the outer two block extensions  121 ,  123  of each leg  101 ,  103 , respectively. Vertical slots  111 ,  112  are spaced apart by a distance  115   a  and a gap  115  is formed between them, as shown in  FIG. 2 . Gap  115  extends from the top surface  119  of the leg, has a height  116  less than the height  117  of the slots  111  and  112  and the same width as the distance  115   a  between the slots  111  and  112 . Gap  115  is dimensioned to receive a support bar  120  extending from the top  113  of left leg  101  to the top  114  of right leg  103 , as shown in  FIG. 7 . Left and right ends  120   a,    120   b  of support bar  120  are placed within the gaps  115  of the left and right legs  101 ,  103 , respectively, and are fixedly attached to the inner blocks  122 , as shown in  FIG. 6  and  FIG. 2 . In this type of arrangement there is no contact between the ends  105   a,    105   b  of the frame beam  105  and the ends  120   a,    120   b,  of support bar  120 . Frame beam  105  supports two separate sets of microscope X-Y-Z stages  201   a,    201   b  controlling the motion of the two microscope sets  210   a,    210   b,  respectively. The upper wafer support block  180  is fixedly attached to support bar  120 . The lack of contact between the ends  105   a,    105   b  of the frame beam  105  and the ends  120   a,    120   b,  of support bar  120  isolates the frame beam  105  from the support bar  120  and prevents the transfer of vibrations due to the microscope stage motion to the upper wafer support block  180  and therefore to the upper wafer  90 . 
         [0037]    Referring to  FIGS. 3 and 4 , each microscope set  210   a,    210   b,  includes two coaxially arranged microscopes  224   a,    224   b  and  225   a,    225   b,  placed within elongated tubes  202   a,    202   b,  respectively. Each microscope  224   a,    224   b  includes a light source  211   a,    211   b,  a high performance objective lens  212   a,    212   b  and a CCD camera  213   a,    213   b.  A double-sided mirror  215  arranged at  45  degrees angle relative to the optical axis  217  is also included. Light  214   a  emitted from light source  211   a  is focused via the objective lens  212   a  and directed via the mirror  215  toward the lower wafer surface  81 . Light  216   a  reflected by the lower wafer surface  81  is then directed by the mirror  215  and focused onto the CCD camera  213   a.  Similarly, light  214   b  emitted from light source  211   b  is focused via the objective lens  212   b  and directed via the mirror  215  toward the upper wafer surface  91 . Light  216   b  reflected by the upper wafer surface  91  is then directed by the mirror  215  and focused onto the CCD camera  213   b.  The surface images of the lower and upper wafer surfaces  81 ,  91  collected by the CCD cameras  213   a,    213   b  are then used to align the wafer surfaces  81 ,  91  parallel to each other. In one example, light sources  211   a,    211   b  are yellow Light Emitting Diodes (LED). In other examples, other visible or infrared light sources are used. 
         [0038]    Elongated tubes  202   a,    202   b  are connected to inverted U-shape structures  204   a,    204   b  that are carried by the microscope XYZ stages  201   a,    201   b,  respectively, around the frame beam  105 . Microscope stages  201   a,    201   b  move the axes  217   a,    217   b  of the microscopes in X, Y, Z directions. In some embodiments stages  201   a,    201   b  are X-Y-Z-T stages and may also rotate the microscope axes around an axis perpendicular to them by an angle theta (T). The legs of the U-shape structures  204   a,    204   b  are fixedly connected to plates  232   a,    232   b,    234   a,    234   b  and plates  232   a,    232   b,    234   a,    234   b  are connected to the ends of the elongated tubes  202   a,    202   b,  via three kinematic couplings  233   a,    233   b,    233   c,  as shown in  FIG. 8 . Mirrors  235   a,    235   b,  are also connected to plates  232   a,    232   b,  respectively, separately from the elongated tubes, and are arranged below the elongated tubes  202   a,    202   b,  so that the microscope axes  217   a,    217   b  are parallel to the mirror planes  236   a,    236   b,  respectively, shown in  FIG. 11 . Furthermore, the apparatus includes left and right microscope calibration reference units  140   a,    140   b  attached on the left and right frame legs  101 ,  103 , respectively, shown in  FIG. 1  and  FIG. 7 . Each reference unit  140   a,    140   b,  includes fixed top and bottom reference marks K, K′, L, L′ located on fixed top and bottom plates  141   a,    141   b,    142   a,    142   b,  respectively. The X-Y-Z and T coordinates of the two microscope optical axes  217   a,    217   b,  and the angular position of the mirror planes  236   a,    236   b,  shown in  FIG. 11 , are determined in reference to these fixed marks and are used as references for the wafer alignment process, as will be described below. 
         [0039]    Referring to  FIG. 7 , upper wafer  90  is held via vacuum suction onto upper wafer block  180 , so that surface  91  to be aligned parallel to the lower wafer surface  81  is facing down. Upper wafer block  180  includes an upper wafer plate  182  supporting the wafer  90  and a plate leveling system  184  for leveling upper wafer plate  182 . The plate leveling system includes a spherical Wedge Error Compensating (WEC) mechanism that rotates and/or tilts the upper wafer plate  182  around a center point corresponding to the center of the wafer  90  without translation. Lower wafer  80  is held via vacuum suction onto lower wafer block  150 , so that its surface  81  to be aligned parallel to the upper wafer surface  91  is facing up. Lower wafer block  150  includes a coarse X-Y-T air-bearing table  152  carrying an air bearing Z-stage  154 , and a fine X-Y-T stage  155  is carried on top of the Z-stage. Fine X-Y-T stage  155  carries the lower wafer plate  156  upon which a fixture  300  carrying wafer  80  is positioned. In one example, coarse X-Y-T table  152  has a position range of ±3 millimeters and ±3 degrees, while fine X-Y-T stage has a position range of ±100 micrometers and ±1 millidegree and the Z-axis range is 60 millimeters. Connected to the coarse X-Y-T stage  152  are three position sensors  157  that measure the X-Y-T-distance between the coarse stage  152  and fine stage  155  and provide feedback for the fine X-Y-T manipulation of the lower wafer surface plane  81 . In one example, the position sensors  157  are capacitance gauges and are used for making high precision non-contact measurements of linear displacements. Upper and lower wafer plates  182 ,  156 , are made of materials with CTE matching the CTE of the wafers. In one example, wafers  80 ,  90  are made of silicon and plates  182 ,  156  are made of silicon carbide. In other embodiments, separate sets of position sensors are placed on both the lower wafer plate and the upper wafer plate. 
         [0040]    Referring to  FIG. 12 , a fixture  300  is used to transport the upper and lower wafers  90 ,  80  in and out of the alignment apparatus and to maintain the alignment of the two wafers for further processing, such as bonding of the wafers or further deposition steps. Fixture  300  includes an outer ring  310  supporting a lower wafer carrier chuck  315  and three clamp/spacer assemblies  320   a,    320   b,    320   c,  arranged at the periphery of ring  310 . Each clamp/spacer assembly  320   a  includes a spacer  321   a  and a clamp  322   a.  The motion of clamp/spacer assemblies is very precise and repeatable both at room temperatures and at the high temperatures where the further wafer processing takes place. Wafer  80  is placed on top of lower wafer carrier chuck  315 , the spacers  321   a,    321   b,    321   c  are inserted on top of the edges of the wafer surface  81 , then the upper wafer  90  is placed on top of the spacers  321   a,    321   b,    321   c,  and then the upper wafer carrier chuck  316  is placed on top of the upper wafer  90  and the clamps  322   a,    322   b,    322   c  engage the upper wafer carrier chuck to clamp the two wafers together onto the fixture. The spacers  321   a,    321   b,    321   c,  may be moved independent from each other from the clamping motion to bring the wafer surfaces  91 ,  81  in contact or to set a gap between them. The two clamped wafers may also be pinned together via a center pin  325 , as shown in  FIG. 14 . In one example ring  310  is made of titanium and wafer carrier chucks  315 ,  316  are made of silicon carbide. 
         [0041]    Referring to  FIG. 18A-FIG .  20 C, the alignment process includes the following steps. First, microscope sets  210   a,    210   b  are positioned in the reference units  140   a,    140   b  and microscopes  224   a,    224   b  and  225   a,    225   b  are focused onto the fixed top and bottom reference marks K, K′, L, L′ located on the top and bottom plates  141   a,    141   b,    142   a,    142   b,  respectively. Next, a pattern recognition software is used to determine the X-Y coordinates of the fixed reference marks K, K′, L, L′ and their separation distance, as well as the angular positions theta (T) of the mirror planes  236   a,    236   b  (reflecting the positions of microscope axes  217   a,    217   b ) relative to the reference marks. Reference marks K, L and axis  217   a  define a reference plane  290   a  (shown in  FIG. 20A ) for microscopes  224   a,    224   b  and marks K′, L′ and axis  217   b  define a reference plane  290   b  (not shown) for microscopes  225   a,    225   b.  Next, the microscope sets  210   a,    210   b  are inserted between the lower wafer  80  and upper wafer  90  and the X-Y-Z microscope stages  201   a,    201   b,  are moved so that the images A′, B′ of the fiducial marks A, B, on the upper wafer surface  91  are brought into the field of view (FOV)  280  of the microscopes  224   b,    225   b  looking up and the microscopes  224   b,    225   b  are focused onto them, respectively, as shown in  FIG. 19A . The microscope stages  201   a,    201   b  are locked and then the lower wafer  80  is moved in the X-Y-T- and Z directions to bring the images C′, D′ of the lower wafer fiducial marks C, D, into the field of view  282  of the microscopes  224   a,    224   b  looking down and to focus the microscopes  224   a,    225   a  onto them, respectively, as shown in  FIG. 19B . Next, the positions of the fiducial marks A, B, C, D are determined by analyzing their images A′, B′, C′, D′ within the corresponding fields of view  280 ,  282  of microscopes  224   b,    225   b,    224   a,    225   a  with the pattern recognition software Patmax® program available from Cognex Co, Natick Mass., and by taking into consideration the positions of the microscopes  224   b,    225   b,    224   a,    225   a  relative to the reference planes  290   a,    290   b.  In addition to the microscope positions any change in the mirror angles ( and the upon them reflected optical axes  217   a,    217   b ) is taken into consideration and the X-Y-T offsets Δx, Δy, Δθ, shown in  FIG. 20B , between the upper fiducial marks A, B and lower fiducial marks C, D are determined. Next, the lower wafer  80  (and carrier) is moved in the X-Y-T directions by the determined amount of the X-Y-T offsets Δx, Δy, Δθ, to position the fiducial marks C, D of the lower wafer  80  in alignment with the fiducial marks A, B of the upper wafer  90 , shown in  FIG. 19C  and  FIG. 20C . This results with the lower wafer  80  being in alignment with the upper wafer  90  while they are separated by a distance  294 . Next, the lower wafer  80  is moved up in the Z-direction while the X-Y-T position of wafer stage  155  is maintained by measuring its distance from the coarse stage  152  with the three co-planar position sensor  157  that are fixed on it and adjusting the position of wafer stage  155  so that the aligned lower wafer  80  position is maintained. The lower wafer  80  is moved up in the Z-direction until surface  81  contacts the surface  91  of the upper wafer  90 . The aligned stack of wafers  80 ,  90  is clamped with clamps  322   a,    322   b,    322   c  onto the fixture  300  and is removed from the aligner for further processing, such as bonding of the two wafers. In other embodiments, wafer  80  is moved up in the Z-direction until surface  81  contacts spacers  321   a,    321   b,    321   c  inserted between the two wafers. In this configuration wafers  80  and  90  are clamped together while separated by a distance corresponding to the spacer thickness. The complete alignment sequence  600  is depicted in  FIG. 18A-FIG .  18 B and includes the following steps. Starting out, the microscopes are out of the space between the upper and lower blocks  180 ,  150  and the Z-axis of the X-Y-T-Z wafer stage  152  is down ( 601 ). Next, the fixture  300  with the upper and lower wafer chucks is loaded in the aligner and placed on the X-Y-T-Z wafer stage  152  ( 602 ). X-Y-T-Z wafer stage  152  is then moved up in the Z-direction and the upper chuck is handed over to the upper block  180 . X-Y-T-Z wafer stage  152  with the lower wafer chuck is then moved down ( 603 ). Next, the upper wafer  90  is loaded in the aligner and transferred to the upper wafer chuck ( 604 ). The lower wafer is then loaded into the aligner and transferred onto the lower wafer chuck and the spacers are placed on top of the lower wafer surface ( 605 ). The z-axis of the lower wafer stage  152  is then moved up to bring the spacers in contact with the upper wafer  90  and to perform the Wedge Error Correction (WEC) on the upper wafer plate under force feedback control ( 606 ). The upper wafer plate position is locked and the z-axis is moved down and the spacers are removed ( 607 ). Next the microscopes are inserted in the fixed reference units and the upper microscopes are focused onto the fixed top marks and the lower microscopes are focused onto the fixed bottom marks ( 608 ). The fixed mark images are analyzed with an image pattern recognition software and their position, the distance from each other and the mirror angular positions (i.e., axes of the microscopes) are determined ( 609 ). These measurements define the reference point (i.e., center of coordinate system) for the further measurements. Next, the microscopes are inserted between the upper and lower wafer and the upper directed microscopes are focused onto the upper wafer marks. The microscope positions are then locked ( 610 ). The lower X-Y-T-Z wafer stage  152  is then moved to focus the lower directed microscopes onto the lower wafer marks and the stage position is locked ( 611 ). The images of the upper and lower marks are analyzed with the image pattern recognition software and their position relative to the fixed mark positions and the X-Y-T offsets between them are determined and the mirror angular positions (i.e., axes of the microscopes) are also measured ( 612 ). The lower wafer fine stage is then moved by the X-Y-T offset amount and by the amount determined by the global calibration, as is described below ( 613 ). Next, the microscopes are moved out of the space between the upper and lower wafer ( 614 ) and the lower wafer stage is moved up in the z-direction while the X-Y-T alignment of the fine wafer stage is maintained with the help of the position sensors ( 615 ). The lower wafer  80  is brought into contact with the upper wafer  90  and the stack is clamped together ( 616 ) in the fixture  300 . Finally, the aligned wafer set and fixture are removed from the aligner and placed into another process chamber ( 617 ) for further processing such as bonding or deposition. 
         [0042]    The aligner system  100  is calibrated with a global calibration device  400  shown in  FIG. 14-FIG .  17 . Global calibration device  400  includes a lower plate  415 , an upper plate  425  and a clear transparent wafer  430  (shown in  FIG. 17 ) arranged between them. Lower plate  415  includes concentric vacuum grooves  418  and fiducial marks  416   a,    416   b.  Upper plate  425  includes vacuum grooves  419  and transparent wafer  430  includes fiducial marks  432   a,    432   b.  Lower plate  415 , transparent wafer  430  and upper plate  425  are placed in fixture  300  and are placed in the aligner apparatus  100 . The above described alignment process  600  is performed to bring the fiducial marks  432   a,    432   b  of the transparent wafer  430  in alignment with the fiducial marks  416   a,    416   b  of the lower plate  415 . Next, the transparent wafer  430  is placed in contact with the lower plate and the overlap of the transparent wafer marks  432   a,    432   b  with the lower plate marks  416   a,    416   b  is observed with the down focusing microscopes  225   a,    224   a.  Any X-Y-T offsets between these marks are measured, as well as the mirror angular positions and are used for the global calibration correction. 
         [0043]    In some embodiments, the entire aligner  100  may be enclosed in a controlled atmosphere, temperature and pressure chamber  70 , as shown in  FIG. 1 . The microscope stages  201   a,    201   b  may be X-Y-Z-T stages. 
         [0044]    Several embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications is made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.