Abstract:
A synchronous rectifier is disclosed, which makes use of gate charge retention technique. In a forward converter after the main transformer is reset its secondary voltage diminishes to zero. For self-driven synchronous rectifiers the driving voltage is lost and current is forced to go through body diode with high conduction loss. Active clamp is a method to get around the problem but it requires an active switch on the primary side. The present invention introduces gate charge retention method by, which no additional active switch is required on the primary side. Synchronous rectifiers are kept on even after the main transformer is reset and secondary voltage diminished to zero. This synchronous rectifier avoids effect of leakage inductance in converter transformer windings and operates at high efficiency. This synchronous rectifier can operate in a number of circuit topologies.

Description:
This application claims benefit to domestic priority of Ser. No. 60/144,127 filed Jul. 16, 1999. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to the field of switch mode power converters and, in particular, to the field of synchronous rectification for high efficiency converters. 
     BACKGROUND OF THE INVENTION 
     With the ever-increasing demand in the power electronics market for low voltage, high current power converters, power supply designers are faced with the challenge of designing high efficiency converters in smaller physical sizes. For converters with output voltages as low as 2.2V or lower, the state of the art schottky diodes have limited utility because their forward voltage drop of 0.3V is still unacceptably high. To achieve an overall efficiency as high as 90%, the rectification stage voltage drop would have to be lower than 0.1V. Only with synchronous rectification MOSFETs can one possibly approach achieving this goal. The performance of synchronous rectification, however, is not always superior to traditional schottky diode rectification. This is especially true when the driving signal timing and the driving voltage level of synchronous rectifiers are not well designed. 
     There are two primary methods for controlling synchronous rectifiers: the self-driven method and the controller driven method. In isolated power conversion, the controller driven method is usually more complex and costly than its self-driven counterpart, so it is not preferred. 
     There are two types of self-driven methods: the voltage driven method and the current driven method. A current driven synchronous rectifier uses current sensing to control the switching times. The current driven rectifier requires additional current sensing components such as current transformer or current sensing MOSFET thereby increasing circuit complexity. A voltage driven synchronous rectification is attractive for its simplicity. The driving signals for the voltage driven synchronous rectifier can be derived from the main transformer windings or output inductor coupled windings. 
     Among various isolated topologies, the forward topology is one of the most suitable topologies for low voltage power conversion because it is the simplest derivation of isolated step-down topology, however it has shortcomings. A prior art synchronous rectifier, as shown in FIG. 1A, uses the secondary winding of the main transformer to drive the synchronous rectifier. The gates of the synchronous MOSFETs S 1  and S 2  are connected to two terminals of the main transformer secondary winding. Alternating voltage at the secondary winding drives the MOSFETs S 1  and S 2  in synchronism with the converter main switch S. 
     The main drawback of this topology is conduction through the body diode of the synchronous MOSFETs when magnetizing current resets to zero. When this happens, the voltage at the transformer secondary becomes zero as shown in FIG.  1 B. The time period when this occurs is normally called the dead time. During this dead time period, a freewheeling synchronous rectifier is not driven on but there is output current flowing through it nonetheless. This is because current is flowing through the body diode of the synchronous rectifier. The body diode of a MOSFET has a higher forward voltage drop and poorer reverse recovery characteristic than a normal fast recovery diode. So during this dead time period, the loss is much higher with the synchronous rectifier than with a traditional diode rectifier. The advantages of synchronous rectifiers is greatly compromised because of diode body conduction during dead time periods. 
     Efforts to address the body diode conduction problem include the active clamp method as shown if FIG.  2 A. With the help of an auxiliary switch SA, which is coupled to a precharged capacitor, magnetizing energy is recovered and transformer dead time can be reduced to a very short time period. The active clamp method is effective and provides complementary signals to drive two synchronous MOSFETs. But, it requires an additional floating switch SA on the primary side, which is costly together with its associated circuitry. 
     In U.S. Pat. No. 5,886,881, Xia put the active clamp switch on the secondary side. But, to do this a p-channel MOSFET was needed, which has much inferior parameter values than an n-channel MOSFET. 
     In U.S. Pat. No. 5,343,383, Shinada attempted to increase the response speed of synchronous rectifiers by driving the gates through capacitors. This reference, however, does not attempt to solve the dead time problem and does not prevent MOSFET body diode conduction when in the presence of transformer leakage inductance. 
     Other systems have proposed methods for keeping synchronous rectifiers turned on during dead time. But, they attempt this by reducing the input voltage range of the converter. 
     Therefore, there remains a need in this art for a system for overcoming the body diode conduction problem in synchronous rectifiers without adding costly components, inferior components and without reducing the input voltage range of the converter. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the problems noted above and satisfies the needs in this field for a system for overcoming the body diode conduction problem in synchronous rectifiers during dead time. 
     The present invention provides a simple system for eliminating the problem of body diode conduction without using the active clamp method. The present invention utilizes a retention of gate charge technique wherein the gate charge is retained during dead time until it is released at the end of a switching period. As a result, the synchronous rectifier remains turned on during dead time without a primary clamp circuit and without body diode conduction. 
     Because transformer leakage inductance may delay the switching of the synchronous MOSFETs, the present invention provides a system that employs an auxiliary winding to drive the synchronous MOSFETs. 
     The present invention is very versatile since it can be used in many topologies. Disclosed are several embodiments for use with current doubler topologies, topologies with center-tapped secondary windings, and forward converter topologies. 
     Accordingly, it is an object of the present invention to provide high efficiency self-driven synchronous rectifier circuits for low voltage power supply apparatus. 
     It is another object of the present invention to use the voltage sensing method for its simplicity. 
     It is another object of the present invention to enable synchronous rectifiers to remain conducting during dead time without using active clamp circuit on the primary side. 
     It is another object of the present invention to avoid the effect of leakage inductance in the main transformer of a converter. 
     It is another object of the present invention to provide synchronous rectification to a wide range of power converter topologies. 
     In accordance with the present invention a synchronous rectifier system for a power converter is provided. The system comprises a transformer having a first secondary winding; a first synchronous switch coupled to the transformer secondary, and a second synchronous switch coupled to the transformer secondary. The system further comprises a state retention device coupled to the second synchronous switch, the state retention device being operative to allow the second synchronous switch to remain in a conduction state when the voltage across the transformer secondary approaches zero volts; and a state release switch coupled to the second synchronous switch, the state release switch being operative to direct the second synchronous switch to switch to a non-conducting state when the first synchronous switch is directed to switch to a conducting state. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become apparent from the following description when read in conjunction with the accompanying drawings wherein: 
     FIG. 1A is a prior art forward converter with self driven synchronous rectifier; 
     FIG. 1B shows waveforms for the prior art forward converter of FIG. 1A; 
     FIG. 2A is a prior art forward converter with a synchronous rectifier and active clamp circuit; 
     FIG. 2B shows waveforms for the prior art forward converter in FIG. 2A; 
     FIG. 3 shows the principle of charge retention; 
     FIG. 4A is a schematic diagram of synchronous rectification on the secondary side of a power transformer; 
     FIG. 4B shows waveforms for the schematic diagram in FIG. 4A; 
     FIG. 5A is a schematic diagram of the first embodiment of the present invention; 
     FIG. 5B shows waveforms for the first embodiment of the present invention; 
     FIG. 6A is a schematic diagram of the second embodiment of the present invention; 
     FIG. 6B shows waveforms for the second embodiment of the present invention; 
     FIG. 7A is a schematic diagram of the third embodiment of the present invention; 
     FIG. 7B shows waveforms for the third embodiment of the present invention; 
     FIG. 8A is a schematic diagram of the forth embodiment of the present invention; 
     FIG. 8B shows waveforms for the forth embodiment of the present invention; 
     FIG. 9A is a schematic diagram of the fifth embodiment of the present invention; 
     FIG. 9B shows waveforms for the fifth embodiment of the present invention; 
     FIG. 10A is a schematic diagram of the sixth embodiment of the present invention; 
     FIG. 10B shows waveforms for the sixth embodiment of the present invention; 
     FIG. 11A is a schematic diagram of the seventh embodiment of the present invention; and 
     FIG. 11B shows waveforms for the seventh embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the drawings, the principle of gate charge retention is illustrated in FIG.  3 . Switch S is off and the initial voltage of capacitor C is zero before t 0 . At time t 0 , driving signal V 1  becomes positive. Assuming that the capacitance value of capacitor C is small, capacitor voltage V 2  also becomes positive because of the charging current through the diode D. When the driving signal V 1  drops to zero at t 1 , diode D is reverse biased and charge remains on capacitor C provided switch S is off. So voltage V 2  remains positive until switch S is turned on at time t 2 , and capacitor C is discharged through switch S. 
     The present invention applies this principle to power converters having synchronous rectifiers. FIG. 4A shows a schematic diagram of synchronous rectification on the secondary side of a power transformer. Voltage output from the transformer secondary side is rectified by synchronous recifiers and then filtered to produce a DC voltage. Different arrangements of the filters can produce a forward converter, a center tapped converter or a current doubler converter. Regardless of the converter type, the synchronous rectifiers need similar driving signals. When secondary voltage Vs is positive, synchronous rectifier SR 1  has to be turned on while synchronous rectifier SR 2  has to be turned off, and vice versa for negative secondary voltage Vs. Such driving signals can be derived from secondary voltage Vs. When the secondary voltage Vs is zero during dead time, one of the synchronous rectifiers should be turned on in order to avoid body diode conduction. The principle of gate charge retention is applied to synchronous rectifier SR 2  so it remains turned on in the dead time period. This avoids body diode conduction and excessive dissipation. 
     A first embodiment of the present invention is shown in FIG.  5 A. It comprises input terminals for a DC source. It further comprises a switching apparatus with a transformer having at least a secondary winding WS 1 . In FIG. 5A a single switch forward converter is shown, however, it is emphasized that any forward or flyback topology, which can produce an appropriate alternating voltage waveform at its secondary output winding, can be applied to the present invention. A first terminal of the transformer secondary winding is attached to the drain terminal of a MOSFET switch S 8 . The gate terminal of MOSFET switch S 8  is coupled to the cathode of a diode D 1 . The anode of diode D 1  is connected to a second terminal of the transformer secondary winding. A second MOSFET switch S 9  has its drain terminal attached to the gate terminal of MOSFET switch S 8 , its source terminal connected to that of MOSFET switch S 8 , and its gate terminal attached to the gate terminal of a third MOSFET switch S 10 . This node joining the gate terminals of MOSFETs S 9  and S 10  is attached to the first terminal of the transformer secondary winding. MOSFET switch S 10  has its drain terminal attached to the second terminal of the transformer secondary winding. A low pass filter with inductor L 3  and capacitor C 3  is coupled to the first terminal of the transformer secondary winding and the node joining the source terminals of MOSFETs S 8 , S 9  and S 10 . Two output terminals are attached to capacitor C 3  for attachment to a load Ro. 
     The operation of this synchronous rectifier can be explained in terms of the waveforms shown in FIG.  5 B. 
     In the time period t 0  to t 1 , primary switch S 11  is turned on. Input voltage Vin is applied to the transformer primary winding. A corresponding voltage is induced on the secondary winding WS 1 , MOSFET switches S 9  and S 10  are turned on. Load current goes through MOSFET S 10  while MOSFET S 8  is turned off by MOSFET S 9 . 
     In the time period t 1  to t 2 , primary switch S 11  is turned off. Magnetizing current goes through a reset winding of the transformer and a reset diode D 2 . On the secondary side, voltage induced changes sign and turns off MOSFETs S 9  and S 10 . At the same time MOSFET S 8  is turned on. Now S 8  is on and output current freewheels through it. The time duration of this mode depends on the fall of transformer magnetizing current. 
     In the time period t 2  to t 0 ′ when transformer has reset, zero voltage appear across the transformer secondary. However, MOSFET S 8  remains on because gate charged acquired in the previous period is retained. Load current is able to continue to freewheel through the low loss MOSFET S 8  rather than its body diode. This solves the problem of conduction through body diode during dead time. Charge storage in MOSFET S 8  is discharged only when MOSFET S 9  is turned on at the beginning of next cycle. In this embodiment, switch S 10  is a first synchronous switch, switch S 9  is a state release switch, switch S 8  is a second synchronous switch, and diode D 1  is a state retention device. 
     There is an overall saving in component cost compared to active clamp method. Compared to prior art self-driven synchronous rectifier, the present invention needs two more devices S 9  and D 1  on the secondary side. Despite this, only low power components are required since they do not carry load current. By this arrangement the present invention eliminates active clamp circuit on the primary side. This brings about saving of at least one power switch and its associated circuitry. 
     In general, gate charge of MOSFET devices can be retained sufficiently long for dead time period. One can estimate the time that the gate voltage can be kept above threshold voltage in the present invention. There are three discharging paths for gate charge. Namely, through diode D 1 , MOSFET S 9 , and the gate to source resistance of synchronous MOSFET S 8 . A typical Synchronous MOSFET has total gate charge of around 60 nc. Typical gate to source leakage current is about 100 nA. Drain to source leakage current is about 100 mA. Diode reverse leakage current is 1 mA for schottky diode in the worst case, although diode with much less leakage than schottky diode is used for diode D 1 . Assume that typical gate threshold voltage is 2V and initial gate voltage is 5V. Gate voltage remains above threshold voltage for around 33 ms. Compared this period with the dead time period at switching frequencies higher than 100 kHz in most applications, which is less than 10 ms, one can say that this time period is long enough to sustain conduction of the synchronous rectifier during dead time. 
     In practical design, transformer always has leakage inductance. This leakage inductance and other parasitic inductance such as device lead inductance and PCB layout inductance create a transition period for secondary current winding to build up from zero to load current or to decrease from load current to zero. During this transition period, secondary voltage falls on the leakage inductance instead of gate source terminals of synchronous MOSFETs because of current commutation. Thus output current goes through body diode of synchronous MOSFETs. Body diode turn on address high conduction loss and serious reverse recovery problems, which greatly degrade synchronous rectification performance. It should be noted that leakage inductance may cause body diode conduction in almost all topologies if the synchronous rectifiers are not properly driven. The two synchronous rectifiers may also conduct simultaneously and cause overcurrent in the secondary side if there is delay in turning off of these devices. 
     In order to solve the problem of leakage inductance and delay, a second embodiment of the present invention, which comprises of auxiliary windings is presented. A schematic diagram of this embodiment is shown in FIG.  6 A. It comprises of input terminals for a DC source. It further comprises of switching apparatus with a transformer having at least a secondary winding and two auxiliary windings. In FIG. 6A a single switch forward converter is shown, however, it is emphasized that any forward topology, which can produce an appropriate alternating voltage waveform at its secondary output winding can be applied to the present invention. A first terminal of the transformer secondary winding with embedded leakage inductance is attached to the drain terminal of a MOSFET switch S 12 . A second MOSFET switch S 13  has its drain terminal attached to the gate terminal of MOSFET switch S 12 , its source terminal connected to that of MOSFET switch S 12 , and its gate terminal attached to the gate terminal of a third MOSFET switch S 14 . This MOSFET S 14  has its source tied to a node joining the source terminals of MOSFETs S 12  and S 13 . This MOSFET S 14  has its drain terminal connected to a second terminal of the transformer secondary winding. The transformer has two auxiliary windings. A first auxiliary winding WA 1  with embedded leakage inductance has one of its two terminals attached to a node joining the gate terminals of MOSFETs S 13  and S 14 . Another terminal of winding WA 1  is tied to a node joining the source terminals of MOSFETs S 12 , S 13  and S 14 . This node is also tied to a terminal of a second auxiliary winding WA 2 . A diode D 3  has its anode coupled to a second terminal of winding WA 2 , and its cathode attached to a node joining the gate terminal of MOSFET S 12  and the drain terminal of MOSFET S 13 . A low pass filter with inductor L 4  and capacitor C 4  is coupled to the drain of MOSFET S 12  and a node joining the source terminals of MOSFETs S 12 , S 13  and S 14 . Two output terminals are attached to output capacitor C 4  for attachment to a load. 
     Waveforms associated with the second embodiment are shown in FIG.  6 B. The operation of this embodiment is very similar to that of the aforementioned first embodiment. When primary switch S 15  is on, input DC voltage is applied to primary winding of the transformer. Auxiliary winding WA 1  reflected voltage turns on switch S 14  and S 13 . So S 12  is turned off. Because of the existence of secondary leakage inductance L 5 , voltage of secondary winding first falls on the leakage inductance. Current flowing through S 14  builds up linearly until it picks up output current. When MOSFET S 15  is off, magnetic reset period begins. Auxiliary winding WA 1  reflected voltage turns off MOSFETs S 14  and S 13  while WA 2  voltage charges the gate capacitance of MOSFET S 12  through diode D 3 . Again there is a current transition period during, which output current commutes from MOSFET S 14  to S 12 . Because MOSFET S 13  remains off until the next switching cycle, even if magnetic reset period is over and transformer winding voltage is zero, the gate voltage of MOSFET S 12  is still high because of gate charge retention. This provides output current a low impedance path, which keeps the merit of synchronous rectifier. Synchronous MOSFETs S 12  and S 14  are driven by auxiliary windings WA 1  and WA 2 . Even if the auxiliary windings have similar amount of leakage inductance they carry much lower current than the load current. Hence the transition time is much shorter. Also time delay so caused is reduced and turn on and turn off signals depend solely on reflected signal from the primary side and thus eliminate the problem of simultaneous conduction and overcurrent. 
     The number of auxiliary winding is not restricted to two, a third embodiment of the present invention is shown in FIG. 7A, which has only one auxiliary winding to drive two synchronous rectifiers. This embodiment comprises of input terminals for a DC source. It further comprises of switching apparatus with a transformer having at least a secondary winding and one auxiliary winding. In FIG. 7A a single switch forward converter is shown, however, it is emphasized that any forward topology, which can produce an appropriate alternating voltage waveform at its secondary output winding can be applied to the present invention. A first terminal of the transformer secondary winding with embedded leakage inductance is attached to the drain terminal of a MOSFET switch S 16 . A second MOSFET switch S 17  has its drain terminal attached to the gate terminal of MOSFET switch S 16 , its source terminal connected to that of MOSFET switch S 16 , and its gate terminal attached to that of a third MOSFET switch S 18 . This MOSFET S 18  has its source tied to a node joining the source terminals of MOSFETs S 16  and S 17 . This MOSFET S 18  also has its drain terminal connected to a second terminal of the transformer secondary winding WS 3 . The transformer has an auxiliary winding WA 3 . Its embedded leakage inductance L 9  is also shown in FIG.  7 A. Auxiliary winding WA 3  has one of its two terminals attached to a node joining the gate terminals of MOSFETs S 17  and S 18 . Another terminal of winding WA 3  is tied to a node joining the cathode of a diode D 4  and the anode of another diode D 5 . Diode D 4  has its anode connected to a node joining the source terminals of MOSFETs S 16 , S 17  and S 18 . Diode D 5  has its cathode connected to the gate terminal of MOSFET S 16 . Another diode D 6  has its anode connected to the anode of diode D 4 , and its cathode connected the gate terminal of MOSFET S 18 . A low pass filter with inductor L 10  and capacitor C 5  is coupled to the drain of MOSFET SI 6  and a node joining the source terminals of MOSFETs S 16 , S 17  and S 18 . Two output terminals are attached to output capacitor C 5  for attachment to a load. 
     Waveforms associated with the third embodiment are shown in FIG.  7 B. The number of auxiliary windings is reduced to one at the expenses of two extra diodes. When primary switch S 19  is on, input DC voltage is applied to primary winding of the transformer. Reflected voltage of auxiliary winding WA 3  turns on MOSFETs S 18  and S 17  with charging path through diode D 4 . So MOSFET S 16  is turned off. Because of the existence of secondary leakage inductance L 8 , voltage of secondary winding first falls on the leakage inductance. Current flowing though MOSFET S 18  increases linearly until it picks up output current. When MOSFET S 19  is off, magnetic reset period begins. Reflected voltage of auxiliary winding WA 3  changes it polarity. Diode D 5  and MOSFET S 17  provide a discharging path for gate charge in S 18  and S 17 . It should be noted that MOSFET S 17  is part of the discharging path for its own gate charge. Ideally all gate charge should be removed before the switches are completely turned off. However in case when MOSFET S 17  turns off before the gate charge is completely removed, voltage induced in auxiliary winding WA 3  continues to discharge the gate source capacitance and charge up the capacitances across MOSFET S 17 . This effect is enhanced in the presence of a leakage inductance L 9  and diode D 6 . Leakage inductance L 9  forms a resonance circuit with capacitances in the conducting path and improves charge exchange between the gate source capacitance and those across MOSFET S 17 . Diode D 6  clamps the gate source of MOSFET S 18  to ensure that the voltage does not go excessively negative. Again there is a current transition period during, which output current commutes from MOSFET S 18  to MOSFET S 16 . Because MOSFET S 17  remains off until the next switch cycle, even if magnetic reset period is over and transformer winding voltage is zero, the gate voltage of MOSFET S 16  is still high because of gate charge retention. This provides output current a low impedance path, which keeps the merit of synchronous rectifier. 
     It is to be appreciated that the number of auxiliary winding used for driving in alternative arrangement can be one or two, and this is applicable to all following embodiments with auxiliary winding. It is preferable to adopt single auxiliary winding embodiments because in these embodiments the driving loss of MOSFET S 16  and S 18  is lower than that in the embodiment with two auxiliary windings as no negative gate drive voltage is allowed. The gate voltage of MOSFETs S 17  and S 18  is clamped by diode D 6 , while the gate voltage of MOSFET S 16  is clamped by diodes D 4  and D 5 . 
     It is also to be appreciated that diode D 6  may be removed without impairing the gate charge retention function. However negative gate voltage exists in S 18  and driving loss is higher. 
     A forth embodiment of the present invention is shown in FIG.  8 A. It is a single ended current doubler converter with synchronous rectifiers driven by transformer secondary winding. This embodiment comprises of input terminals for a DC source. It further comprises of switching apparatus with a transformer having at least a secondary winding WS 4 . In FIG. 8A a single switch forward converter is shown, however, it is emphasized that any forward topology, which can produce an appropriate alternating voltage waveform at its secondary output winding can be applied to the present invention. A first terminal of the transformer secondary winding is attached to the drain terminal of a MOSFET switch S 20 . A second MOSFET switch S 21  has its drain terminal attached to the gate terminal of MOSFET switch S 20 , its source terminal connected to that of MOSFET switch S 20 , and its gate terminal attached to the gate terminal of a third MOSFET switch S 22 . This MOSFET S 22  has its source tied to a node joining the source terminals of MOSFETs S 20  and S 21 . MOSFET S 22  also has its drain terminal connected to a second terminal of the transformer secondary winding. A diode D 7  has its anode connected to the second terminal of the transformer secondary winding and its cathode connect to the gate terminal of MOSFET S 20 . An inductor L 11  is connected between the drain terminal of MOSFET S 20  and a node joining another inductor L 12 , which is in turn connected to the drain terminal of MOSFET S 22 . An output capacitor C 6  is connected between the node joining inductors L 11  and L 12  and the node joining the source terminals of MOSFETs S 20 , S 21  and S 22 . Two output terminals are attached to output capacitor C 6  for attachment to a load. 
     Waveforms associated with the forth embodiment are shown in FIG.  8 B. This embodiment is a single ended current doubler converter. In a first time period when voltage across secondary winding WS 4  is positive, energy is transferred to output by forward mode. In the time period that follows, when primary switch S 23  is turned off, energy is transferred to the output by flyback mode. Current on secondary side is handled by MOSFETs S 22  and S 20  in the two time periods respectively. Towards the end of a switching cycle voltage across secondary winding has diminishes to zero. MOSFET S 20  is kept conducting by the charge retention principle. Low conduction lost is maintained throughout the cycle. When primary switch S 23  is on, input DC voltage is applied to primary winding of the transformer. On the secondary side, MOSFETs S 21  and S 22  are turned on by the secondary winding WS 4  reflected voltage. MOSFET S 20  is turned off. Output current commutes from MOSFET S 20  to MOSFET S 22 . When MOSFET S 23  is off, magnetic reset period begins. Secondary reflected voltage turns off MOSFETs S 21  and S 22  while charges the gate capacitance of MOSFET S 20  through diode D 7 . Because S 21  remains off until the next switch cycle, even if magnetic reset period is over and transformer winding voltage is zero, the gate voltage of MOSFET S 20  is still high because of gate charge retention. This provides output current a low impedance path, which keeps the merit of synchronous rectifier. 
     A fifth embodiment of the present invention is shown in FIG.  9 A. It is another current doubler converter with synchronous rectifiers driven by an auxiliary winding. This embodiment comprises of input terminals for a DC source. It further comprises of switching apparatus with a transformer having at least a secondary winding WS 5  and an auxiliary winding WA 4 . In FIG.  9 A a single switch forward converter is shown, however, it is emphasized that any forward topology, which can produce an appropriate alternating voltage waveform at its secondary output winding can be applied to the present invention. A first terminal of the transformer secondary winding with embedded leakage inductance is attached to the drain terminal of a MOSFET switch S 24 . A second MOSFET switch S 25  has its drain terminal attached to the gate terminal of MOSFET switch S 24 , its source terminal connected to that of MOSFET switch S 24 , and its gate terminal attached to that of a third MOSFET switch S 26 . This MOSFET S 26  has its source tied to a node joining the source terminals of MOSFETs S 24  and S 25 . MOSFET S 26  also has its drain terminal connected to a second terminal of the transformer secondary winding. An auxiliary winding WA 4  has one of its terminals with embedded leakage inductance attached to a node joining the gates of MOSFETs S 25  and S 26 , and another terminal attached to the anode of a diode D 8  and the cathode of diode D 10 . Diode D 8  has its cathode attached to the gate terminal of MOSFET S 24  and diode D 10  has its anode connected to node joining the source terminals of MOSFETs S 24 , S 25  and S 26 . Another diode D 9  is connected between the gate and source terminals of MOSFET S 25 . An inductor L 13  is connected between the drain terminal of MOSFET S 24  and a node joining another inductor L 14 , which is in turn connected to the drain terminal of MOSFET S 26 . An output capacitor C 7  is connected between the node joining inductors L 13  and L 14  and the node joining the source terminals of MOSFETs S 24 , S 25  and S 26 . Two output terminals are attached to output capacitor C 7  for attachment to a load. 
     Waveforms associated with the fifth embodiment are shown in FIG.  9 B. This embodiment is also a single ended current doubler converter similar to the forth embodiment. Synchronous MOSFETs in this embodiment are driven by a separate auxiliary winding instead of transformer secondary winding. This method avoids the aforementioned effect of leakage inductance and reduce time delay. When primary switch S 27  is on, input DC voltage is applied to primary winding of the transformer. The reflected voltage of auxiliary winding WA 4  turns on MOSFETs S 25  and S 26  with charging path through diode D 10 . So MOSFET S 24  is turned off. Because of the existence of secondary leakage inductance L 20 , reflected voltage of secondary winding falls first on the leakage inductance. Current flowing though MOSFET S 26  increases linearly until it picks up output current. When MOSFET S 27  is off, magnetic reset period begins. Reflected voltage of auxiliary winding WA 4  changes it polarity. Diode D 8  and MOSFET S 25  provide a discharging path for gate charge in S 25  and S 26 . It should be noted that MOSFET S 25  is part of the discharging path for its own gate charge. Ideally all gate charge should be removed before the switches are completely turned off. However in case when MOSFET S 25  turns off before the gate charge is completely removed, voltage induced in auxiliary winding WA 4  continues to discharge the gate source capacitance and charge up the capacitances across MOSFET S 25 . This effect is enhanced in the presence of leakage inductance L 21  and diode D 9 . Leakage inductance L 21  forms a resonance circuit with capacitances in the conducting path and improves charge exchange between the gate source capacitance and those across MOSFET S 25 . Diode D 9  clamps the gate source of MOSFET S 25  to ensure that the voltage does not go excessively negative. Again there is a current transition period during, which output current commutes from MOSFET S 26  to MOSFET S 24 . Because MOSFET S 25  remains off until the next switch cycle, even if magnetic reset period is over and transformer winding voltage is zero, the gate voltage of MOSFET S 24  is still high because of gate charge retention. This provides output current a low impedance path, which keeps the merit of synchronous rectifier. 
     It is to be appreciated that diode D 9  may be removed without impairing the gate charge retention function. However negative gate voltage exists in S 25  and driving loss is higher. 
     A sixth embodiment of the present invention is shown in FIG.  10 A. It is a center tapped converter with synchronous rectifiers operated on the principle of the present invention. This embodiment comprises of input terminals for a DC source. It further comprises of switching apparatus with a transformer having at least two secondary windings WS 6  and WS 7 . In FIG. 10A a single switch forward converter is shown, however, it is emphasized that any forward topology, which can produce an appropriate alternating voltage waveform at its secondary output winding can be applied to the present invention. A first terminal of transformer secondary winding WS 6  is attached to the drain terminal of a MOSFET switch S 28 . The gate terminal of MOSFET S 28  is attached to a second terminal of secondary winding WS 6 . The source terminal of MOSFET S 28  is attached to the source terminal of a second MOSFET S 29 . MOSFET S 29  has its gate terminal attached to that of MOSFET S 28 , and its drain terminal attached to the gate terminal of a third MOSFET S 30 . MOSFET S 30  has its drain terminal attached to a first terminal of secondary winding WS 7  and its source terminal attached to those of MOSFETs S 28  and S 29 . A diode D 11  is coupled between a second terminal of secondary winding WS 7  and a node joining the drain terminal of MOSFET S 29  and the gate terminal of MOSFET S 30 . A connection connects up the second terminal of winding WS 7  the second terminal of winding WS 6 . A low pass filter with inductor L 15  and capacitor C 8  is coupled to the second terminal of winding WS 6  and a node joining the source terminals of MOSFETs S 28 , S 29  and S 30 . Two output terminals are attached to output capacitor C 8  for attachment to a load. 
     Waveforms associated with the sixth embodiment are shown in FIG.  10 B. This embodiment is a converter with a tapped secondary, or two secondary windings. In a first time period when voltage across secondary winding WS 6  is positive, energy is transferred to output by forward mode. Current is established in inductor L 15 . In the time period that follows, energy is transferred by flyback mode. At the same time current through inductor L 15  contributes to reset of the main transformer. Current on secondary side is handled by MOSFETs S 28  and S 30 . Towards the end of a switching cycle voltage across the secondary windings diminish to zero. MOSFET S 30  is kept conducting by the charge retention principle. Low conduction loss is maintained throughout the cycle. When primary switch S 31  is on, input DC voltage is applied to primary winding of the transformer. In the secondary side, MOSFETs S 28  and S 29  are turned on by the reflected voltage of secondary winding WS 6 . MOSFET S 30  is turned off. Output current commutes from MOSFET S 30  to S 28 . When MOSFET S 31  is off, magnetic reset period begins. Secondary reflected voltage turns off MOSFETs S 28  and S 29  while charges the gate capacitance of MOSFET S 30  through diode D 11 . Because MOSFET S 29  remains off until the next switch cycle, even if magnetic reset period is over and transformer winding voltage is zero, the gate voltage of MOSFET S 30  is still high because of gate charge retention. This provides output current a low impedance path, which keeps the merit of synchronous rectifier. 
     A seventh embodiment of the present invention is shown in FIG.  11 A. It is another center tapped converter with synchronous rectifiers operated on the principle of the present invention with an auxiliary winding. This embodiment comprises of input terminals for a DC source. It further comprises of switching apparatus with a transformer having at least two secondary windings WS 8  and WS 9 , and an auxiliary winding WA 5 . Each of these windings has its embedded leakage inductance. In FIG. 11A a single switch forward converter is shown, however, it is emphasized that any forward topology, which can produce an appropriate alternating voltage waveform at its secondary output winding can be applied to the present invention. A first terminal of transformer secondary winding WS 8  is attached to the drain terminal of a MOSFET switch S 32 . The gate terminal of MOSFET S 32  is attached to that of MOSFET S 33 . The drain terminal of MOSFET S 33  is attached the gate terminal of a third MOSFET S 34 . MOSFETs S 32 , S 33  and S 34  have their source terminals tied together at a node. The drain terminal of MOSFET S 34  is attached to a first terminal of a secondary winding WS 9 . A second terminal of winding WS 9  with embedded leakage inductance is connected to a second terminal of winding WS 8  with embedded leakage inductance. The transformer has an auxiliary winding WA 5 . It has one of its terminals attached to the cathode of a first diode D 13  and another terminal with embedded leakage inductance attached to the cathode of a second diode D 14 . The anodes of diodes D 13  and D 14  are connected to the node joining the source terminals of MOSFETs S 32 , S 33  and S 34 . A third diode D 12  has its anode attached to the cathode of diode D 13  and its cathode connected to the gate terminal of MOSFET S 34 . A low pass filter with inductor L 16  and capacitor C 9  is coupled to the second terminal of winding WS 8  and a node joining the source terminals of MOSFETs S 32 , S 33  and S 34 . Two output terminals are attached to output capacitor C 9  for attachment to a load. 
     Waveforms associated with the seventh embodiment are shown in FIG.  11 B. This embodiment operates similar to the sixth embodiment. Synchronous MOSFETs in this embodiment are driven by a separate auxiliary winding instead of transformer secondary winding. This method avoids the aforementioned effect of leakage inductance and reduce time delay. When primary switch MOSFET S 35  is on, input DC voltage is applied to primary winding of the transformer. The reflected voltage of auxiliary winding WA 5  turns on MOSFETs S 32  and S 33  with charging path through diode D 13 . So MOSFET S 34  is turned off. Because of the existence of secondary leakage inductance L 22  and L 23 , reflected voltages of secondary windings fall first on the leakage inductance. Current flowing though MOSFET S 32  linearly increases until it picks up output current. When MOSFET S 35  is off, magnetic reset period begins. Reflected voltage of auxiliary winding WA 5  changes it polarity. Diode D 12  and MOSFET S 33  provide a discharging path for gate charge of S 32  and S 33 . It should be noted that MOSFET S 33  is part of the discharging path for its own gate charge. Ideally all gate charge should be removed before the switches are completely turned off. However in case when MOSFET S 33  turns off before the gate charge is completely removed, voltage induced in auxiliary winding WA 5  continues to discharge the gate source capacitance and charge up the capacitances across MOSFET S 25 . This effect is enhanced in the presence of leakage inductance L 24  and diode D 14 . Leakage inductance L 9  forms a resonance circuit with capacitances in the conducting path and improves charge exchange between the gate source capacitance and those across MOSFET S 33 . Diode D 14  clamps the gate voltage of MOSFET S 33  to ensure that the voltage does not go excessively negative. Again there is a current transition period during, which output current commutes from MOSFET S 32  to MOSFET S 34 . Because MOSFET S 33  remains off until the next switch cycle, even if magnetic reset period is over and transformer winding voltage is zero, the gate voltage of S 34  is still high because of gate charge retention. This provides output current a low impedance path, which keeps the merit of the synchronous rectifier. 
     It is to be appreciated that diode D 14  may be removed without impairing the gate charge retention function. However negative gate voltage exists in S 32  and driving loss is higher. 
     The invention has been described with reference to preferred embodiments. Those skilled in the art will perceive improvements, changes, and modifications. Such improvements, changes, and modification are intended to be covered by the appended claims. 
     Having described in detail the preferred and alternate embodiments of the present invention, including the preferred modes of operation, it is to be understood that the invention is capable of other and different embodiments, its several details are capable of modifications in various respects, and its operation could be carried out with different elements and steps, all without departing from the spirit of the invention. The drawings and description of the preferred and alternate embodiments are presently only by way of example and are be regarded as illustrative in nature and are not meant to limit the scope of the present invention which is defined by the following claims.