Abstract:
An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional of U.S. patent application Ser. No. 11/820,659, filed Jun. 20, 2007, which is a continuation of U.S. patent application Ser. No. 11/147,508, filed Jun. 8, 2005 (now U.S. Pat. No. 7,271,111), both of which are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an electronic circuit element and, more particularly, to an electronic circuit element formed from layers of different segments deposited on a substrate by way of a shadow mask deposition process. 
         [0004]    2. Description of Related Art 
         [0005]    Electronic circuits with repetitive patterns, such as memories and imaging or display devices are, widely used in LED industry. Presently, such circuits are formed by photolithographic processes. 
         [0006]    A shadow mask deposition process is well-known and has been used for years in micro-electronics manufacturing. The shadow mask process is a significantly less costly and less complex manufacturing process compared to the photolithography process. Accordingly, it would be desirable to utilize the shadow mask deposition process to form electronic circuits. 
         [0007]    One problem with the current shadow mask deposition process is the need to engineer, manufacture and inventory a large number of shadow masks, each of which typically has one or more apertures of a unique size and/or location in the shadow mask. Thus, for example, if a plurality of shadow mask deposition events is required to produce the electronic elements of an electronic circuit having a repetitive pattern, a plurality of different shadow masks is typically required, since each deposition event will typically entail the deposition of material of a unique size and/or a unique location on the substrate. 
         [0008]    It would, therefore, be desirable, to overcome the above problem and others by providing shadow masks that have configurable opening sizes whereupon the need to engineer, manufacture and inventory a unique shadow mask for each deposition event is avoided. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention is an electronic circuit with repetitive patterns formed by shadow mask vapor deposition. The electronic circuit includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes a substrate; a first semiconductor segment deposited on a portion of the substrate; a second semiconductor segment deposited on a different portion of the substrate; a first metal segment deposited on the substrate over a portion of the first semiconductor segment; a second metal segment deposited on the substrate over a different portion of the first semiconductor segment spaced from the first metal segment; a third metal segment deposited on the substrate over a portion of the second semiconductor segment; a fourth metal segment deposited on the substrate over a different portion of the second semiconductor segment spaced from the third metal segment; a fifth metal segment deposited on the substrate over at least a portion of the fourth metal segment; a sixth metal segment deposited on the substrate over at least a portion of the first metal segment; a first insulator segment deposited on the substrate over the first semiconductor segment, at least a portion of the first metal segment and at least a portion of the second metal segment; a second insulator segment deposited on the substrate over at least a portion of the fifth metal segment; a third insulator segment deposited on the substrate over the second semiconductor segment and at least portions of the third metal segment, the fourth metal segment and the fifth metal segment; a seventh metal segment deposited on the substrate over at least a portion of the first insulator segment; an eighth metal segment deposited on the substrate over at least portions of the first insulator segment, the second insulator segment and the seventh metal segment; a ninth metal segment deposited on the substrate over at least portions the second metal segment and the third insulator segment; and a tenth metal segment deposited on the substrate over at least portions the third insulator segment and the ninth metal segment. 
         [0010]    All of the above segments may be deposited via a shadow mask deposition process. One or more of the first and second semiconductor segments, the first, second, third, fifth, sixth, seventh and eighth metal segments and the first insulator segment may have an elongated shape, and one or more of the fourth, ninth and tenth metal segments and the second and third insulator segments may have a rectangular shape. One or more of the first and second semiconductor segments may be formed from a semiconductor material that is suitable for forming a thin-film transistor by vacuum evaporation such as, but not limited to, cadmium selenide (CdSe), cadmium sulfide (CdS) or tellurium (Te). One or more of the metal segments may be formed of any suitable electrically conductive material, such as, but not limited to, molybdenum (Mo), copper (Cu), nickel (Ni), chromium (Cr), aluminum (Al), gold (Au) or indium-tin oxide (ITO). One or more of the insulator segments may be formed of any suitable electrically nonconductive material, such as, but not limited to, aluminum oxide (Al 2 O 3 ) or silicon dioxide (SiO 2 ). The substrate may be formed of an electrically insulative material. 
         [0011]    The combination of the second semiconductor segment, the third, fourth and tenth metal segments and the third insulator segment may form a first transistor. The combination of the first semiconductor segment, the first, second, seventh, and eighth metal segments and the first insulator segment may also form a second transistor. The electronic circuit element may be an element of an array of like electronic circuit elements. 
         [0012]    The present invention is also an electronic circuit element of an electronic circuit comprising a first stack of materials, a second stack of materials operatively connected to the first stack and a third stack of materials operatively connected to the first stack and the second stack. The first stack of materials includes a first semiconductor material layer, a first conductive material layer overlaying a first part of the semiconductor material layer, a second conductive material layer overlaying a second part of the semiconductor material layer spaced from the first part thereof, an insulator material layer overlaying the first semiconductor material layer and the first and second conductive material layers, and a third conductive material layer overlaying at least a portion of the insulator material layer. The second stack of materials includes a first conductive material layer, an insulator material layer overlaying at least a portion of the first conductive material layer, and a second conductive material layer overlaying at least a portion of the insulator material layer and in contact with the third conductive material layer of the first stack of materials. The third stack of materials includes a second semiconductor material layer, a first conductive material layer overlaying a first part of the second semiconductor material layer, a second conductive material layer overlaying a second part of the second semiconductor material layer spaced from the first part thereof, an insulator material layer overlaying the second semiconductor material layer and the first and second conductive material layers in alignment with the second semiconductor material layer, a third conductive material layer overlaying the insulator material layer, and a fourth conductive material layer overlaying a portion of the third conductive material layer and a portion of the second conductive material of the first stack of materials. 
         [0013]    Lastly, the present invention is a method of manufacturing an electronic circuit element, comprising providing a substrate; depositing a first semiconductor segment on a portion of the substrate; depositing a second semiconductor segment on a different portion of the substrate; depositing a first metal segment on the substrate in contact with a portion of the first semiconductor segment; depositing a second metal segment on the substrate in contact with another portion of the first semiconductor segment spaced from the first metal segment; depositing a third metal segment on the substrate in contact with a portion of the second semiconductor segment; depositing a fourth metal segment on the substrate in contact with another portion of the second semiconductor segment spaced from the third metal segment; depositing a fifth metal segment on the substrate in contact with a portion of the fourth metal segment; depositing a sixth metal segment on the substrate in contact with a portion of the first metal segment; depositing a first insulator segment on the substrate over the first semiconductor segment, and portions of the first metal segment and the second metal segment in contact with the first semiconductor segment; depositing a second insulator on the substrate over a portion of the fifth metal segment spaced from the fourth metal segment; depositing a third insulator segment on the substrate over the second semiconductor segment and at least portions of the third metal segment, the fourth metal segment and the fifth metal segment; depositing a seventh metal segment on the substrate over at least a portion of at least one of the first insulator segment and the second insulator segment; depositing an eighth metal segment on the substrate over at least a portion of at least one of the first insulator segment and the second insulator segment and in contact with at least a portion of the seventh metal segment; depositing a ninth metal segment on the substrate over at least portions of the second metal segment and the third insulator segment; and depositing a tenth metal segment on the substrate over the third insulator segment and in contact with at least a portion of the ninth metal segment. 
         [0014]    An insulating material may be deposited over the substrate such that only a portion of the third metal segment is exposed through an opening in said insulating material. An eleventh metal segment may be deposited over the insulating material and in contact with the third metal segment. A light emitting material may be deposited in contact with the eleventh metal segment. 
         [0015]    Each segment may be deposited via a shadow mask deposition process. One or more of the semiconductor segments may be formed from cadmium selenide (CdSe), cadmium sulfide (CdS) or tellurium (Te). One or more of the metal segments may be formed from molybdenum (Mo), copper (Cu), nickel (Ni), chromium (Cr), aluminum (Al), gold (Au) or indium-tin oxide (ITO). One or more of the third insulator segments may be formed of one of aluminum oxide (Al 2 O 3 ) and silicon dioxide (SiO 2 ). The combination of the second semiconductor segment, the third, fourth and tenth metal segments and the third insulator segment may form a transistor. The combination of the first semiconductor segment, the first, second, seventh, and eighth metal segments and the first insulator segment may form another transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1A  is a diagrammatic illustration of a shadow mask deposition system for forming pixel structures of a high resolution active matrix backplane; 
           [0017]      FIG. 1B  is an enlarged view of a single deposition vacuum vessel of the shadow mask deposition system of  FIG. 1A ; 
           [0018]      FIG. 2  is a circuit schematic of a 3×3 array of sub-pixels of an active matrix backplane wherein a 2×2 array of said 3×3 array define a pixel of said active matrix backplane; 
           [0019]      FIG. 3  is an enlarged view of an exemplary physical layout of one of the sub-pixels of  FIG. 2 ; 
           [0020]      FIG. 4  is a view of an exemplary physical layout of the sub-pixel structures that form the sub-pixels of  FIG. 2 ; 
           [0021]      FIG. 5A  is a view of a portion of a compound shadow mask utilized in the shadow mask deposition system of  FIG. 1A  atop a substrate upon which is deposited a plurality of segments of the sub-pixel structures shown in  FIG. 4  through openings in the compound shadow mask; 
           [0022]      FIG. 5B  is an exploded sectional view taken along lines VB-VB in  FIG. 5A ; 
           [0023]      FIG. 5C  is an exploded sectional view taken along lines VC-VC in  FIG. 5A ; and 
           [0024]      FIGS. 6-19  are views of a sequence of openings in compound shadow masks of the shadow mask deposition system of  FIG. 1A  through which a plurality of materials is deposited to form the sub-pixel element shown adjacent each opening. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0025]    The present invention will be described with reference to the accompanying figures where like reference numbers correspond to like elements. 
         [0026]    With reference to  FIGS. 1A and 1B , a shadow mask deposition system  2  for forming an electronic device, such as, without limitation, a high resolution active matrix light emitting diode (LED) display, includes a plurality of serially arranged deposition vacuum vessels  4  (e.g., deposition vacuum vessels  4   a - 4   x ). The number and arrangement of deposition vacuum vessels  4  is dependent on the number of deposition events required for any given product to be formed therewith. 
         [0027]    In use of shadow mask deposition system  2 , a flexible substrate  6  translates through the serially arranged deposition vacuum vessels  4  by means of a reel-to-reel mechanism that includes a dispensing reel  8  and a take-up reel  10 . 
         [0028]    Each deposition vacuum vessel includes a deposition source  12 , a substrate support  14 , a mask alignment system  15  and a compound shadow mask  16 . For example, deposition vacuum vessel  4   a  includes deposition source  12   a , substrate support  14   a , mask alignment system  15   a  and compound shadow mask  16   a ; deposition vacuum vessel  4   b  includes deposition source  12   b , substrate support  14   b , mask alignment system  15   b  and compound shadow mask  16   b ; and so forth for any number of deposition vacuum vessels  4 . 
         [0029]    Each deposition source  12  is charged with a desired material to be deposited onto substrate  6  through one or more openings in the corresponding compound shadow mask  16  which is held in intimate contact with the portion of substrate  6  in the corresponding deposition vacuum vessel  4  during a deposition event. 
         [0030]    Each compound shadow mask  16  of shadow mask deposition system  2  includes one or more openings. The opening(s) in each compound shadow mask  16  corresponds to a desired pattern of material to be deposited on substrate  6  from a corresponding deposition source  12  in a corresponding deposition vacuum vessel  4  as substrate  6  translates through shadow mask deposition system  2 . 
         [0031]    Each compound shadow mask  16  is formed of, for example, nickel, chromium, steel, copper, Kovar® or Invar®, and has a thickness desirably between 20 and 200 microns, and more desirably between 20 and 50 microns. Kovar® and Invar® can be obtained from, for example, ESPICorp Inc. of Ashland, Oreg. In the United States, Kovar® is a registered trademark, Registration No. 337,962, currently owned by CRS Holdings, Inc. of Wilmington, Del., and Invar® is a registered trademark, Registration No. 63,970, currently owned by Imphy S.A. Corporation of France. 
         [0032]    Those skilled in the art will appreciate that shadow mask deposition system  2  may include additional stages (not shown), such as an anneal stage, a test stage, one or more cleaning stages, a cut and mount stage, and the like, as are well-known. In addition, the number, purpose and arrangement of deposition vacuum vessels  4  can be modified by one of ordinary skill in the art as needed for depositing one or more materials required for a particular application. An exemplary shadow mask deposition system and method of use thereof is disclosed in U.S. patent application Ser. No. 10/255,972, filed Sep. 26, 2002, and entitled “Active Matrix Backplane For Controlling Controlled Elements And Method Of Manufacture Thereof”, which is incorporated herein by reference. 
         [0033]    Deposition vacuum vessels  4  can be utilized for depositing materials on substrate  6  to form one or more electronic elements of the electronic device on substrate  6 . Each electronic element may be, for example, a thin film transistor (TFT), a memory element, a capacitor etc., or, a combination of one or more of said elements to form a higher level electronic element, such as, without limitation, a sub-pixel or a pixel of the electronic device. In accordance with the present invention, a multi-layer circuit can be formed solely by successive depositions of materials on substrate  6  via successive deposition events in deposition vacuum vessels  4 . 
         [0034]    Each deposition vacuum vessel  4  is connected to a source of vacuum (not shown) which is operative for establishing a suitable vacuum therein in order to enable a charge of the material disposed in the corresponding deposition source  12  to be deposited on substrate  6  in a manner known in the art, e.g., sputtering or vapor phase deposition, through the one or more openings in the corresponding compound shadow mask  16 . 
         [0035]    Herein, substrate  6  is described as a continuous flexible sheet which is dispensed from dispensing reel  8 , which is disposed in a pre-load vacuum vessel, into the deposition vacuum vessels  4 . However, this is not to be construed as limiting the invention since shadow mask deposition system  2  can be configured to continuously process a plurality of standalone or individual substrates. Each deposition vacuum vessel  4  can include supports or guides that avoid the sagging of substrate  6  as it advances therethrough. 
         [0036]    In operation of shadow mask deposition system  2 , the material disposed in each deposition source  12  is deposited on the portion of substrate  6  in the corresponding deposition vacuum vessel  4  through one or more openings in the corresponding compound shadow mask  16  in the presence of a suitable vacuum as said portion of substrate  6  is advanced through the deposition vacuum vessel  4 , whereupon plural, progressive patterns is formed on substrate  6 . More specifically, substrate  6  has plural portions, each of which is positioned for a predetermined time interval in each deposition vacuum vessel  4 . During this predetermined time interval, material is deposited from the corresponding deposition source  12  onto the portion of substrate  6  that is positioned in the corresponding deposition vacuum vessel  4 . After this predetermined time interval, substrate  6  is step advanced so that the portion of substrate  6  is advanced to the next vacuum vessel in series for additional processing, as applicable. This step advancement continues until each portion of substrate  6  has passed through all deposition vacuum vessels  4 . Thereafter, each portion of substrate  6  exiting the final deposition vacuum vessel  4  in the series is received on take-up reel  10 , which is positioned in a storage vacuum vessel (not shown). Alternatively, each portion of substrate  6  exiting shadow mask deposition system  2  is separated from the remainder of substrate  6  by a cutter (not shown). 
         [0037]    With reference to  FIG. 2 , an exemplary LED pixel  20   a  that can be formed via shadow mask deposition system  2  comprises a 2×2 arrangement of sub-pixels  22 , e.g., sub-pixels  22   a - 22   d . Sub-pixels  22   a ,  22   b ,  22   c  and  22   d  can be a red sub-pixel, a first green sub-pixel, a second green sub-pixel and a blue sub-pixel, respectively. Alternatively, sub-pixels  22   a ,  22   b ,  22   c  and  22   d  can be a red sub-pixel, a first blue sub-pixel, a second blue sub-pixel and a green sub-pixel, respectively. Since LED pixel  20   a  is representative of one of several of identical pixels arranged in any user defined array configuration for forming a complete active matrix LED device, the description of LED pixel  20   a , including the color of each sub-pixel  22 , is not to be construed as limiting the invention. In  FIG. 2 , the sub-pixels of adjacent pixels  20   b ,  20   c  and  20   d  are shown for illustration purposes. 
         [0038]    Sub-pixels  22   a  and  22   b  are addressed via a pulse signal applied on a Row A bus and via voltage levels applied on a Column A bus and a Column B bus, respectively. Sub-pixels  22   c  and  22   d  are addressed via a pulse signal applied on a Row B bus and via voltage levels applied on the Column A and the Column B bus, respectively. In the illustrated embodiment, each sub-pixel  22  includes cascade connected transistors  24  and  26 , such as, without limitation, thin film transistors (TFTs); an LED element  28  formed of light emitting material  30  sandwiched between two electrodes; and a capacitor  32  which serves as a voltage storage element. In an exemplary, non-limiting embodiment, transistors  24  and  26 , LED element  28  and capacitor  32  of each sub-pixel  22  are interconnected to each other in a manner illustrated in  FIG. 2 . In addition, for each sub-pixel  22 , a control or gate terminal of transistor  24  is electrically connected to a suitable row bus, a node  34  formed by the connection of the drain terminal of transistor  26  to one terminal of capacitor  32  is connected to a power bus (Vcc), and the source terminal of transistor  24  is connected to a suitable column bus. 
         [0039]    To activate each LED element  28  when a suitable voltage is applied to the corresponding power bus Vcc, the voltage applied to the corresponding column bus connected to the source terminal of transistor  24  is changed from a first voltage  40  to a second voltage  42 . During application of second voltage  42 , a pulse signal  44  is applied to the row bus connected to the gate terminal of transistor  24 . Pulse signal  44  causes transistors  24  and  26  to conduct, whereupon, subject to the voltage drop across transistor  26 , the voltage of power bus Vcc is applied to one terminal of LED element  28 . Since the other terminal of LED element  28  is connected to a different potential, e.g., ground potential, the application of the voltage applied to power bus Vcc to LED element  28  causes LED element  28  to illuminate. During application of pulse signal  44 , capacitor  32  charges to the difference between second voltage  42  and the voltage on power bus Vcc, minus any voltage drop across transistor  24 . 
         [0040]    Upon termination of pulse signal  44 , capacitor  32  retains the voltage stored thereon and impresses this voltage on the gate terminal of transistor  26 , whereupon LED element  28  is held in an active, illuminating state in the absence of pulse signal  44 . 
         [0041]    LED element  28  is turned off when pulse signal  44  is applied in the presence of first voltage  40  on the corresponding column bus. More specifically, applying pulse signal  44  to the gate terminal of transistor  24  when first voltage  40  is applied to the source terminal of transistor  24  causes transistor  24  to turn on, whereupon capacitor  32  discharges through transistor  24  thereby turning off transistor  26  and deactivating LED element  28 . Upon termination of pulse signal  44 , capacitor  34  is charged to approximately voltage  40 , whereupon transistor  26  is held in its off state and LED element  28  is held in its inactive state even after pulse signal  44  is terminated. 
         [0042]    In a like manner, each LED element  28  of each sub-pixel  22  of each pixel  20  can be turned on and off in response to the application of a pulse signal  44  on an appropriate row bus when second voltage  42  and first voltage  40 , respectively, are applied to the appropriate column bus in the presence of a suitable voltage applied via the appropriate power bus Vcc. 
         [0043]    With reference to  FIG. 3  and with continuing reference to  FIG. 2 , a sub-pixel structure  50  representative of the physical structure that forms each sub-pixel  22  of each pixel  20  includes, in desired order of deposition, elongated semiconductor segment  52 , elongated semiconductor segment  54 , elongated metal segment(s)  56 , elongated metal segment  58 , elongated metal segment  60 , rectangular metal segment  62 , elongated metal segment(s)  64 , elongated metal segment  66 , elongated insulator segment  68 , rectangular insulator segment  70 , rectangular insulator segment  72 , elongated metal segment(s)  74 , elongated metal segment  76 , rectangular metal segment  78  and rectangular metal segment  80 . 
         [0044]    Each metal segment  56 - 66  and  74 - 80  can be formed of any suitable electrically conductive material that is depositable via a shadow mask deposition process, such as, without limitation, molybdenum (Mo), copper (Cu), nickel (Ni), chromium (Cr), aluminum (Al), gold (Au) or indium-tin oxide (ITO). Insulator segments  68 - 72  can be formed of any suitable electrically nonconductive material that is depositable via a shadow mask deposition process, such as, without limitation, aluminum oxide (Al 2 O 3 ) or silicon dioxide (SiO 2 ). Each semiconductor segment  52  and  54  can be formed of a semiconductor material that is depositable via a shadow mask deposition process and which is suitable for forming a thin-film transistor (TFT) by vacuum evaporation, such as, without limitation, cadmium selenide (CdSe), cadmium sulfide (CdS) or tellurium (Te). 
         [0045]    In sub-pixel structure  50 , the stack comprised of metal segment  62 , insulator  72  and metal segment  80  forms capacitor  32 ; the combination of the segments forming capacitor  32  along with semiconductor segment  54  and metal segment  60  form transistor  26  (with metal segments  80 ,  60  and  62  being the respective gate, source and drain of transistor  26 ); and the combination of semiconductor segment  52 , metal segments  56  and  58 , insulator segment  68  and metal segments  74  and  76  forming transistor  24  (with metal segments  56  and  58  being the source and drain of transistor  24 , and with metal segments  74  and  76  forming the gate of transistor  24 ). 
         [0046]    Desirably, each sub-pixel  22  in  FIG. 2  is realized by the same sub-pixel structure, such as sub-pixel structure  50 . However, this is not to be construed as limiting the invention since each sub-pixel  22  can be realized by any suitable sub-pixel structure. For purpose of describing the present invention, however, it will be assumed hereinafter that each sub-pixel  22  is realized by sub-pixel structure  50 . 
         [0047]    In one exemplary, non-limiting, embodiment, substrate  6  is formed of an electrically insulative material, such as an insulative coated metal sheet; metal segments  60 ,  62  and  80  are formed from Mo, Cu, Ni, Cr, Au or Al; insulator segments  68 - 72  are formed from Al 2   0   3  or SiO 2 ; metal segments  56 ,  58 ,  64 ,  66  and  74 - 78  are formed from Mo, Cu, Ni, Cr, Au or Al and semiconductor segments  52  and  54  are formed from CdSe, CdS, Te or any other suitable semiconducting material that can be deposited via a shadow mask deposition process. 
         [0048]    To complete formation of each functioning sub-pixel  22 , a suitable insulating material (not shown) is deposited atop of the sub-pixel structure  50  shown in  FIG. 3  with an opening exposing all or a portion of metal segment  60 . Another metal segment  36  can then be deposited atop the thus deposited insulating material in contact with metal segment  60  via the opening in the insulating material. Thereafter, light emitting material  30  can be deposited atop the sub-pixel structure  50  in contact with metal segment  36  and a transparent metal segment  38  can be deposited atop light emitting material  30 , whereupon light emitting material  30  is sandwiched between metal segment  36  and transparent metal segment  38 . Desirably, each deposit of metal segment  36 , light emitting material  30  and transparent metal segment  38  is deposited atop of their corresponding sub-pixel  22  in isolation from adjacent deposits of metal segment  36 , light emitting material  30  and transparent metal segment  38  atop their corresponding sub-pixels  22 . Lastly, a layer or sheet of transparent metal (not shown) can be deposited atop of all of the metal layers  38  and the insulating material therebetween as a common electrode for all of the sub-pixels. 
         [0049]    With reference to  FIG. 4  and with continuing reference to  FIGS. 1-3 , a physical implementation of an LED pixel structure corresponding to the circuit schematic of  FIG. 2  is shown upon substrate  6 . In one exemplary embodiment, the overall dimensions of each pixel  20  are 126×126 microns and the overall dimensions of each sub-pixel  22  are 63×63 microns. The foregoing dimensions of each pixel  20  and each sub-pixel  22   a , however, are exemplary only and are not to be construed as limiting the invention. 
         [0050]    An exemplary, non-limiting sequence of depositions through openings in compound shadow masks  16  of shadow mask deposition system  2  to form the sub-pixel structure  50  comprising each sub-pixel  22  will now be described. 
         [0051]    With reference to  FIGS. 5A-5C  and with continuing reference to all previous figures, each compound shadow mask  16  includes a first shadow mask  90  having a plurality of first apertures  92  therethrough and a second shadow mask  94  having a plurality of second apertures  96  therethrough. The description of first and second shadow masks  90  and  94  having a plurality of first apertures  92  and a plurality of second apertures  96  therethrough, respectively, is not to be construed as limiting the invention since first shadow mask  90  may only include a single first aperture  92  and second shadow mask  94  may only include a single second aperture  96  therethrough if desired. For purpose of describing the present invention, it will be assumed that first shadow mask  90  has a plurality of first apertures  92  therethrough and second shadow mask  94  has a plurality of second apertures  96  therethrough. 
         [0052]    Each deposition vacuum vessel  4  desirably includes an instance of the same compound shadow mask  16 . Thus, the compound shadow mask  16   b  in deposition vacuum vessel  4   b  is desirably the same as the compound shadow mask  16   a  in deposition vacuum vessel  4   a ; the compound shadow mask  16   c  in deposition vacuum vessel  4   c  is desirably the same as the compound shadow mask  16  in deposition vacuum vessel  4   b ; and so forth. More specifically, the first shadow masks  90  forming compound shadow masks  16  are desirably identical, the second shadow masks  94  forming compound shadow masks  16  are desirably identical, and each shadow mask  90  is desirably identical to each shadow mask  94 . Thus, identical shadow masks  90   a  and  94   a  are desirably utilized to form compound shadow mask  16   a ; identical shadow masks  90   b  and  94   b  are desirably utilized to form compound shadow mask  16   b , and so forth. 
         [0053]    In order to accomplish the desired deposition of materials to form the various segments of each sub-pixel structure  50 , the positions of first and second shadow masks  90  and  94  forming each compound shadow mask  16  are adjusted with respect to each other such that the respective first and second apertures  92  and  96  are positioned at least partially in alignment to define openings  98  of suitable dimensions or sizes and locations in compound shadow mask  16  for the deposition of material therethrough. Each compound shadow mask  16  can also be positioned within the corresponding deposition vacuum vessel  4  in a manner to position openings  98  to facilitate the deposition of the corresponding material at desired locations upon substrate  6 . 
         [0054]    It has been observed that in order to deposit each segment  52 - 80  of each sub-pixel structure  50  utilizing identical compound shadow masks  16  formed from identical shadow masks  90  and  94 , that the height and width of each aperture  92  and  96  need be only slightly greater than one-half of the height and width of sub-pixel structure  50 . Thus, for example, if the overall dimensions of sub-pixel structure  50  are 63×63 microns, it is only necessary that the overall dimensions of each aperture  92  and  96  be slightly greater than one-half of the dimensions of sub-pixel structure  50 , e.g., 34×34 microns as shown in  FIG. 5A . 
         [0055]    Limiting the length and width of each aperture  92  and  96  to slightly more than one-half of the respective length and width of each sub-pixel structure  50  enables the shadow masks  90  and  94  comprising the compound shadow masks  16  of shadow mask deposition system  2  to deposit each segment  52 - 80  of each sub-pixel structure  50  while avoiding undesirable alignment of one or more instances of a single first apertures  92  with two or more second apertures  96 , or vice versa. More specifically, the actual length and width of each aperture  92  and  96  is selected as a compromise between avoiding undesirable overlap of one or more instances of a single first apertures  92  with two or more second apertures  96 , or vice versa, while, as shown best in  FIG. 3 , enabling desirable overlapping of deposited segments, e.g., segment  66  overlapping segment(s)  56 ; segment  76  overlapping segment(s)  74 ; segment(s)  64  overlapping segment  66 , and so forth. In other words, limiting the length and width of each aperture  92  and  96  to slightly more than one-half of the length and width of the corresponding sub-pixel structure  50  enables the formation of a densely packed array of sub-pixel structures  50  by way of identical compound shadow masks  16 , each of which is formed from identical shadow masks  90  and  94 . An obvious benefit of utilizing identical shadow masks  90  and  94  to form each compound shadow mask  16  of shadow mask deposition system  2  is the avoidance of the time and cost associated with designing, fabricating and inventorying a unique shadow mask for each deposition vacuum vessel  4 . Another benefit is the interchangeability of shadow masks  90  and  94  to form each compound shadow mask  16 . This is especially beneficial when a new or clean shadow mask  90  or  94  is utilized to replace a worn-out or dirty (material encrusted) shadow mask. 
         [0056]      FIGS. 5A-5C  illustrate deposits of semiconductor segments  52  on a portion of substrate  6  via openings  98   a  formed by the partial alignments of first apertures  92   a  and second apertures  96   a  of shadow masks  90   a  and  94   a , respectively, forming compound shadow mask  16   a  which is disposed in deposition vacuum vessel  4   a  having deposition source  12   a  for depositing the material forming semiconductor segments  52  on substrate  6 . In  FIGS. 5B and 5C , substrate  6 , second shadow mask  94   a  and first shadow mask  90   a  are shown spaced from each other for illustration purposes. However, in practice, shadow mask  90   a  is positioned in intimate contact with shadow mask  94   a  which is positioned in intimate contact with substrate  6  during deposition of semiconductor segments  52 . Moreover, in  FIGS. 5B and 5C , the height of deposition of semiconductor segments  52  is exaggerated for illustration purposes. 
         [0057]    The positioning of the first and second shadow masks  90  and  94  of each compound shadow mask  16  of shadow mask deposition system  2  for depositing material segments  54 - 80  will now be further described with reference to the alignment of a single first aperture  92  and a single second aperture  96  of first and second shadow masks  90  and  94 , respectively, forming the corresponding compound shadow mask  16 . In  FIGS. 6-19 , the alignment of the single first aperture  92  and the single second aperture  96  to form the opening  98  in the corresponding compound shadow mask  16  is shown adjacent an exemplary sub-pixel structure  50  for illustration purposes. 
         [0058]    With reference to  FIG. 6  and with continuing reference to all previous figures, following the deposition of each semiconductor segment  52  on the portion of substrate  6  in deposition vacuum vessel  4   a , said portion of substrate  6  is advanced into deposition vacuum vessel  4   b  which includes compound shadow mask  16   b . The first and second shadow masks  90   b  and  94   b  of compound shadow mask  16   b  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   b  and a single second aperture  96   b  are aligned to form an opening  98   b  of compound shadow mask  16   b  for the deposition of semiconductor segment  54  with material from deposition source  12   b.    
         [0059]    With reference to  FIG. 7  and with continuing reference to all previous figures, following the deposition of each semiconductor segment  54  on the portion of substrate  6  in deposition vacuum vessel  4   b , said portion of substrate  6  is advanced into deposition vacuum vessel  4   c  which includes compound shadow mask  16   c . The first and second shadow masks  90   c  and  94   c  of compound shadow mask  16   c  are arranged such that, for each sub-pixel structure  50 , a single first aperture  92   c  and a single second aperture  96   c  are aligned to form an opening  98   c  of compound shadow mask  16   c  for the deposition of metal segment  56  with material from deposition source  12   c.    
         [0060]    With reference to  FIG. 8  and with reference to all previous figures, following the deposition of each metal segment  56  on the portion of substrate  6  in deposition vacuum vessel  4   c , said portion of substrate  6  is advanced into deposition vacuum vessel  4   d  which includes compound shadow mask  16   d . The first and second shadow masks  90   d  and  94   d  of compound shadow mask  16   d  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   d  and a single second aperture  96   d  are aligned to form an opening  98   d  of compound shadow mask  16   d  for the deposition of metal segment  58  with material from deposition source  12   d.    
         [0061]    With reference to  FIG. 9  and with continuing reference to all previous figures, following the deposition of each metal segment  58  on the portion of substrate  6  in deposition vacuum vessel  4   d , said portion of substrate  6  is advanced into deposition vacuum vessel  4   e  which includes compound shadow mask  16   e . The first and second shadow masks  90   e  and  94   e  of compound shadow mask  16   e  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   e  and a single second aperture  96   e  are aligned to form an opening  98   e  of compound shadow mask  16   c  for the deposition of metal segment  60  with material from deposition source  12   e.    
         [0062]    With reference to  FIG. 10  and with continuing reference to all previous figures, following the deposition of each metal segment  60  on the portion of substrate  6  in deposition vacuum vessel  4   e , said portion of substrate  6  is advanced into deposition vacuum vessel  4   f  which includes compound shadow mask  16   f . The first and second shadow masks  90   f  and  94   f  of compound shadow mask  16   f  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   f  and a single second aperture  96   f  are aligned to form an opening  98   f  of compound shadow mask  16   f  for the deposition of metal segment  62  with material from deposition source  12   f.    
         [0063]    With reference to  FIG. 11  and continuing reference to all previous figures, following the deposition of each metal segment  62  on the portion of substrate  6  in deposition vacuum vessel  4   f , said portion of substrate  6  is advanced into deposition vacuum vessel  4   g  which includes compound shadow mask  16   g . The first and second shadow masks  90   g  and  94   g  of compound shadow mask  16   g  are positioned such that a single first aperture  92   g  and a single second aperture  96   g  are aligned to form an opening  98   g  of compound shadow mask  16   g  for the deposition of each metal segment  64  with material from deposition source  12   g.    
         [0064]    With reference to  FIG. 12  and with continuing reference to all previous figures, following the deposition of each metal segment  64  on the portion of substrate  6  in deposition vacuum vessel  4   g , said portion of substrate  6  is advanced into deposition vacuum vessel  4   h  which includes compound shadow mask  16   h . The first and second shadow masks  90   h  and  94   h  of compound shadow mask  16   h  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   h  and a single second aperture  96   h  are aligned to form an opening  98   h  of compound shadow mask  16   h  for the deposition of metal segment  66  with material from deposition source  12   h.    
         [0065]    With reference to  FIG. 13  and with continuing reference to all previous figures, following the deposition of each metal segment  66  on the portion of substrate  6  in deposition vacuum vessel  4   h , said portion of substrate  6  is advanced into deposition vacuum vessel  4   i  which includes compound shadow mask  16   i . The first and second shadow masks  90   i  and  94   i  of compound shadow mask  16   i  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   i  and a single second aperture  96   i  are aligned to form an opening  98   i  of compound shadow mask  16   i  for the deposition of insulator segment  68  with material from deposition source  12   i.    
         [0066]    With reference to  FIG. 14  and with continuing reference to all previous figures, following the deposition of each insulator segment  68  on the portion of substrate  6  in deposition vacuum vessel  4   i , said portion of substrate  6  is advanced into deposition vacuum vessel  4   j  which includes compound shadow mask  16   j . The first and second shadow masks  90   j  and  94   j  of compound shadow mask  16   j  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   j  and a single second aperture  96   j  are aligned to form an opening  98   j  of compound shadow mask  16   j  for the deposition of insulator segment  70  with material from deposition source  12   j.    
         [0067]    With reference to  FIG. 15  and with continuing reference to all previous figures, following the deposition of each insulator segment  70  on the portion of substrate  6  in deposition vacuum vessel  4   j , said portion of substrate  6  is advanced into deposition vacuum vessel  4   k  which includes compound shadow mask  16   k . The first and second shadow masks  90   k  and  94   k  of compound shadow mask  16   k  are positioned such that, for each sub-pixel  50 , a single first aperture  92   k  and a single second aperture  96   k  are aligned to form an opening  98   k  of compound shadow mask  16   k  for the deposition of insulator segment  72  with material from deposition source  12   k.    
         [0068]    With reference to  FIG. 16  and with continuing reference to all previous figures, following the deposition of each insulator segment  72  on the portion of substrate  6  in deposition vacuum vessel  4   k , said portion of substrate  6  is advanced into deposition vacuum vessel  41  which includes compound shadow mask  161 . The first and second shadow masks  901  and  941  of compound shadow mask  161  are positioned such that a single first aperture  921  and a single second aperture  961  are aligned to form an opening  981  of compound shadow mask  161  for the deposition of each metal segment  74  with material from deposition source  121 . 
         [0069]    With reference to  FIG. 17  and with continuing reference to all previous figures, following the deposition of each metal segment  74  on the portion of substrate  6  in deposition vacuum vessel  41 , said portion of substrate  6  is advanced into deposition vacuum vessel  4   m  which includes compound shadow mask  16   m . The first and second shadow masks  90   m  and  94   m  of compound shadow masks  16   m  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   m  and a single second aperture  96   m  are aligned to form an opening  98   m  of compound shadow mask  16   m  for the deposition of metal segment  76  with material from deposition source  12   m.    
         [0070]    With reference to  FIG. 18  and with continuing reference to all previous figures, following the deposition of each metal segment  76  on the portion of substrate  6  in deposition vacuum vessel  4   m , said portion of substrate  6  is advanced into deposition vacuum vessel  4   n  which includes compound shadow mask  16   n . The first and second shadow masks  90   n  and  94   n  of compound shadow mask  16   n  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   n  and a single second aperture  96   n  are aligned to form an opening  98   n  of compound shadow mask  16   n  for the deposition of metal segment  78  with material from deposition source  12   n.    
         [0071]    Lastly, with reference to  FIG. 19  and with continuing reference to all previous figures, following the deposition of each metal segment  78  on the portion of substrate  6  in deposition vacuum vessel  4   n , said portion of substrate  6  is advanced into deposition vacuum vessel  4   o  which includes compound shadow mask  16   o . The first and second shadow masks  90   o  and  94   o  of compound shadow mask  16   o  are positioned such that, for each sub-pixel structure  50 , a single first aperture  92   o  and a single second aperture  96   o  are aligned to form an opening  98   o  of compound shadow mask  16   o  for the deposition of metal segment  80  with material from deposition source  12   o.    
         [0072]    The deposition of metal segment  80  on substrate  6  completes the formation of the electronic element defined by sub-pixel structure  50 . Desirably, all of the sub-pixel structures  50  are formed at the same time in the manner discussed above. Thereafter, if desired, additional segments or layers, described above, can be applied to substrate  6  in furtherance of the fabrication of an electronic device, such as an active matrix LED. 
         [0073]    In the foregoing description, all of the shadow masks  90  are the same and all of the shadow masks  94  are the same. In addition, each shadow mask  90  is the same as each shadow mask  94 . Limiting the size of each aperture  92  and  96  to a length and width slightly greater than about one-half of the length and width, respectively, of the sub-pixel structure to be formed thereby enables alignment combinations of apertures  92  and  96  to be utilized to form tightly packed structures, such as an array of sub-pixel structures  50 , on substrate  6  while avoiding overlap of a single first aperture  92  with two or more second apertures  96 , or vice versa, during a deposition event. The use of a plurality of identical shadow masks  90  and  94  to form the compound shadow masks  16  of shadow mask deposition system  2  avoids the need to engineer, manufacture and inventory a large number of different shadow masks having openings of different dimensions (or sizes) and/or locations for use in shadow mask deposition system  2 . 
         [0074]    Desirably, the mask alignment system  15  of each deposition vacuum vessel  4  is configured to enable the selective x and/or y alignment of one or both of each individual shadow mask  90  and  94  forming the corresponding compound shadow mask  16  from an exterior of the deposition vacuum vessel  4  whereupon the x and/or y dimension(s) of each opening  98  of the compound shadow mask  16  can be adjusted without breaking the vacuum of the deposition vacuum vessel  4 . Thus, if it is determined that one or more dimensions of material deposited through each opening  98  of a compound shadow mask  16  is out of tolerance, mask alignment system  15  can be utilized to adjust said one or more dimensions without breaking the vacuum of the deposition vacuum vessel  4  to bring subsequent depositions of material into tolerance. The capacity provided by each mask alignment system  15  to adjust one or more dimensions of each opening  98  of a compound shadow mask  16  is particularly useful in a continuous in-line shadow mask deposition system to compensate for the buildup of deposited material on or around each opening  98  during a continuous production process thereby avoiding the need to break the vacuum of the deposition vacuum vessel  4  to adjust the dimensions of each opening  98  in response to such buildup. Each mask alignment system  15  is also useful for establishing the dimensions of each opening  98  and the position thereof in the corresponding deposition vacuum vessel  4  prior to the production deposition of material as well as for correcting for any changes in the dimensions of each opening  98  bought about by means other than the buildup of deposited material, e.g., vibration. 
         [0075]    In one non-limiting embodiment, mask alignment system  15  comprises micrometers for adjustment of the x and/or y position of each individual shadow mask  90  and  94  forming the corresponding compound shadow mask  16 . However, this is not to be construed as limiting the invention. 
         [0076]    The invention has been described with reference to the preferred embodiment. Obvious modifications and alterations will occur to others upon reading and understanding the preceding detailed description. It is intended that the invention be construed as including all such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.