Abstract:
A secret-key block-cipher utilizing the principles of factorization and composition with respect to general logarithmic signatures in permutation groups of arbitrary size 2 l , and methods of use thereof are disclosed. The preferred embodiment uses two encryption/decryption stages from composition and factorization means including novel and efficient circuits for multiplication and inversion of permutations, operating in their compact form representation. The system is scalable to any input/output block size l and performs encryption/decryption at very high data rates.

Description:
This application claims the benefit of U.S. Provisional No. 60/068,811 filed Dec. 24, 1997. 
    
    
     TECHNICAL FIELD 
     The present invention relates to secret key cryptosystems and more particularly is a secret key block cipher utilizing logarithmic signatures of permutation groups of arbitrary order 2 l , and method of use thereof. The system is scalable to an arbitrary input/ouput block size l, and operates at very high speeds. The present invention is also a new and efficient method of representing and/or multiplying and/or factoring elements of said permutation groups with respect to said logarithmic signatures. Preferred embodiment uses two logarithmic signatures and two encryption stages selected from composition and factorization means. Said two logarithmic signatures, are obtained by a randomization process seeded by a user key. The encryption transformation is performed using a multiplier means operating on input vectors in compact form. 
     BACKGROUND OF THE INVENTION 
     Related Work 
     Our new cryptosystem will be referred to as TST from the initials of the first names of the inventors. TST is theoretically related to, yet dramatically different from cryptosystem PGM which is, to our knowledge, the only cryptosystem based on factorizations of arbitrary non-abelian permutation groups. 
     Private key cryptosystem PGM was invented by S. Magliveras in the late 1970&#39;s. The system was described in his paper titled &#34;A cryptosystem from logarithmic signatures of finite groups&#34;, Proceedings of the 29th Midwest Symposium on Circuits and Systems, Elsevier Publishing Company (1986), pp 972-975. An earlier paper by S. S. Magliveras, B. A. Oberg and A. J. Surkan, titled &#34;A New Random Number Generator from Permutation Groups&#34;, Rend. del Sem. Matemat. e Fis. di Milano, LIV (1984), pp 203-223 also discusses PGM. The statistical and algebraic properties of PGM were studied by S. S. Magliveras and N. D. Memon in their papers &#34;Algebraic Properties of Cryptosystem PGM&#34;, Journal of Cryptology, 5 (1992), pp 167-183, and &#34;The Linear Complexity Profile of Cryptosystem PGM&#34;, Congressus Numerantium, Utilitas Mathematica, 72 (1989), pp 51-60. Additional related work appeared in the papers: &#34;Complexity tests for cryptosystem PGM, Congressus Numerantium, Utilitas Mathematica, 79 (1990). pp 61-68, by S. S. Magliveras, N. D. Memon and K. C. Tam, and in &#34;Factorizations of elementary Abelian p-groups and their cryptographic significance&#34;, J. of Cryptology, 7 (1994), pp 201-212 by M. Qu and S. A. Vanstone. Here we include only a brief description of PGM. 
     PGM is based on certain fundamental data structures for permutation groups, which are called logarithmic signatures. Let G be a permutation group of degree n. A logarithmic signature for G is an ordered collection α=(A 0 , A 1  , . . . , A w-1 ) of ordered subsets A i  =(a i ,0 , . . . , a i ,r.sbsb.i -1 ) of G, such that each element g ε G has a unique representation as a product of the form 
     
         g=a.sub.0,x.sbsb.0 ·a.sub.1,x.sbsb.1 . . . a.sub.w-1,x.sbsb.w-1 a.sub.i,x.sbsb.i ε A.sub.i                        (1) 
    
     Thus, g corresponds to a unique vector x=(x 0 , . . . , x w-1 ), where 0≦x i  ≦r i  =|A i  |. The property that (A 0  , . . . , A w-1 ) is a logarithmic signature can best be described by means of the equation: 
     
         G=A.sub.0 . . . A.sub.w-2 ·A.sub.w-1              (2) 
    
     holding in the group ring G. It is a necessary condition for cryptographic security that the order of G be exponential in n, while for computational efficiency it is necessary that ##EQU1## be bounded by a polynomial in n. 
     The A i  are called the blocks of α, the vector of block lengths r=(r 0 , . . . , r w-1 ) is called the type of α, and ##EQU2## is called the length of α. There are tame logarithmic signatures i.e. those for which the factorization for each g can be obtained in time polynomial in n, supertame signatures (the factorization can be obtained in time O(n 2 )) and there are wild signatures for which the factorization requires time O(|G|). The question of existence of tame logarithmic signatures has been settled. It has been shown that each member of an extremely large class of signatures is tame. This is the class of so called transversal logarithmic signatures. There exist an even larger number of non-transversal logarithmic signatures (see &#34;On Logarithmic Signatures and Applications&#34;, M. Sc. Thesis, University of Nebraska--Lincoln, (1989), pp 1-59), but the question of whether the class of non-transversal logarithmic signatures is identical with the class of wild signatures is open and appears to be equivalent to the complexity-theory question P≠NP. Surprisingly, the smallest group which has non-transversal logarithmic signatures is the cyclic group  8 . Let Λ=Λ(G) denote the family of all logarithmic signatures of a given group G. 
     Each signature α ε Λ of type (r 0 , . . . , r w-1 ) induces a bijection α:.sub.|G| (≈ r .sbsb.0 ⊕ . . . ⊕ r .sbsb.w-1)→G, which is efficiently invertible if and only if α is tame. 
     To understand some of the significant differences between TST and PGM it is important to describe the mapping α mentioned above. If α=(A 0 , . . . , A w-1 ) is a logarithmic signature for G, we denote by α ij  the j th  element of block A i  of α. Let r=(r 0 , . . . , r w-1 ) be the type of α. We now define a bijection Θ.sub.α :  r .sbsb.0 ⊕ . . . ⊕  r .sbsb.w-1 →G by: 
     
         Θ.sub.α (x.sub.0, . . . , x.sub.w-1)=α.sub.0,x.sbsb.0 ·α.sub.1,x.sbsb.1 . . . α.sub.w-1,x.sbsb.w-1(3) 
    
     Next, define the integers m i , i=0, 1, . . ., w-1 by ##EQU3## and let λ be the bijection from  r .sbsb.0 ⊕ . . . ⊕  r .sbsb.w-1 onto .sub.|G|, defined by ##EQU4## For any x ε .sub.|G|, λ -1  (x) is efficiently computable by successive subtractions. This corresponds to obtaining the mixed base representation of x with respect to (r 0 , . . . , r w-1 ). Next, for any α ε Λ, define a map α: .sub.|G| →G by composing λ -1  with Θ.sub.α, thus α=λ -1  Θ.sub.α. FIG. 5. illustrates the definition of α. 
     The λ -1  or λ portions in computing α=λ -1  Θ.sub.α, or α -1  =Θ.sub.α -1  λ are referred to as knapsack segments. 
     The function α is always efficiently computable, but α -1  is not unless α is tame. We denote by Λ the collection {α:α ε Λ}. 
     Basic PGM uses a pair of tame logarithmic signatures (α,β) and defines the encryption transformation as the mapping E.sub.α,β =α β -1  :.sub.|G| →.sub.|G|  and the corresponding decryption transformation as D.sub.α,β =E.sub.β,α =β α -1 . 
     We illustrate basic PGM by means of a small example. The group used is the alternating group on five points, A 5 , of order 60. This implies that the message space is the set  60  ={0, 1, . . . , 59}. Consider below a table consisting of two log signatures α and β for A 5 . For simplicity we have selected both α and β to be of type (5,4,3). For compatibility reasons with the new TST system we list the blocks of a logarithmic signature α=(A 0 , . . . , A w-1 ) so that the A i  are stacked sequentially one on top of the other with A 0  at the bottom and A w-1  at the top. The central column of the table displays the common knapsack vector v to be used in the knapsack segments of the encrypting and decrypting functions. The integers m i  are 1, 5 and 20 respectively. Let us now demonstrate the operation of enciphering. If for example, the plaintext message is 56, it can be uniquely decomposed with respect to v as, 56=(1+15+40)=1·m 0  +3·m 1  +2·m 2 . This determines uniquely the vector of row-indices λ -1  (56)=(1,3,2). We next compute 
     
         π=Θ.sub.α (1,3,2)=(1 5 4 3 2)·(1)(2 4)(3 5)·(1)(2)(3 5 4)=(1 5 2)(3)(4). 
    
     We then compute Θ.sub.β -1  (π), that is the representation of π with respect to β. Because β is supertame the factorization can be obtained very efficiently but we will not go into this process here. After the factorization has been achieved we have 
     
         π=(1 5 2)(3)(4)=(1 3 5 4 2)·(1)(2 3 4)(5)·(1)(2)(3 4 5) 
    
     This determines the indices for β as (3,1,0), i.e. 
     
         Θ.sub.β.sup.-1 (π)=(3,1,0) 
    
     Finally, λ(3, 1, 0)=3+5+0=8. Hence, E.sub.α,β (56)=8. It can be easily verified now that D.sub.α,β (8)=E.sub.β,α (8)=56. 
     
         ______________________________________α     v             β______________________________________(1)(2)(3)(4)(5)       0             (1)(2)(3 4 5)(1)(2)(3 4 5)       20            (1)(2)(3 5 4)(1)(2)(3 5 4)       40            (1)(2)(3)(4)(5)(1)(2)(3)(4)(5)       0             (1)(2 5)(3 4)(1)(2 3)(4 5)       5             (1)(2 3 4)(5)(1)(2 5)(3 4)       10            (1)(2 4 3)(5)(1)(2 4)(3 5)       15            (1)(2)(3 4 5)(1)(2)(3)(4)(5)       0             (1 4 2 3 5)(1 5 4 3 2) 1             (1)(2)(3 5 4)(1 3 5 2 4) 2             (1 2 5 4 3)(1 2 3 4 5) 3             (1 3 5 4 2)(1 4 2 5 3) 4             (1 5 4)(2)(3)______________________________________ 
    
     Some of the aforementioned references describe methods for obtaining pseudorandom logarithmic signatures from a very large class of transversal signatures and we will not go into this description either. 
     A hardware implementation for PGM was proposed by T. Horvath, S. Magliveras and Tran van Trung in &#34;A Parallel Permutation Multiplier for a PGM Cryptochip&#34;, Advances in Cryptology--CRYPTO&#39;94, Springer-Verlag 1994, pp 108-113. The proposed implementation adheres heavily to the ideas involved in the initial PGM including the knapsack portions at the front and back end of the encryption and decryption transformations. 
     Salient Features of the New System 
     Main drawbacks of PGM regarding implementation aspect can be described as follows: 
     1. In order for PGM to be secure a large carrier group is needed. To accomplish this in a space-efficient way, using cartesian representation of permutations in the given logarithmic signature, we need to use as large a group as possible for the given degree. Hence, use of the symmetric group of a given degree n is indicated. Then, the size of the message space is n! which for n&gt;2 is not a power of 2. As a consequence, the high-order bit is unusable for a block of input plaintext. The corresponding ciphertext however may have the high-order bit on. It follows that the plaintext and ciphertext spaces are not identical, an undesirable property, which, among other, makes superencryption cumbersome. 
     2. The second problem with PGM when using a group of order not a power of 2, is that the signatures contain blocks of length not a power of 2. Therefore, there is no way to avoid the computationally intensive knapsack transformations λ and λ -1 , that is, the conversion of binary words to a mixed radix format, and conversely, prior to and after the essential PGM transformations. 
     The new system TST differs radically from PGM in a number of significant ways, amongst others the new system overcomes the disvantages of PGM listed above. Several features of TST are briefly described below. 
     1. TST works with permutation 2-groups, i.e., permutation groups in which the number of elements is a power of 2. The new system is born with the invention of new permutation networks working with elements of G represented in what we call the compact form. As a consequence, the invention makes feasible the utilization of permutation groups of much larger degrees in VLSI realizations. 
     2. The ability to use permutation 2-groups allows the new system to completely avoid the computationally intensive front- and back-end knapsack portions of PGM. This results in a significant reduction of the hardware complexity. 
     3. The problem of incompatible cleartext and ciphertext space of PGM is automatically eliminated in the new system. 
     4. The new permutation multiplier designs have evolved by fusing and simplifying an indirect binary cube interconnection network with the new compact representation for elements of the carrier group. Consequently the multipliers work directly with the compact representation, rather than via the cartesian representations of the input and output permutations. This results in a very significant data-path width reduction by an approximate factor s for the data path, the i/o registers and related buses when using a group of degree 2 s . 
     A search of patents was conducted and revealed very little of relevance. However the following patents are disclosed because they discuss systems and methods of encryption. 
     References Cited 
     
         ______________________________________3,962,539 Jun., 1976  Ehrsam et al.                              380/294,087,152 Mar., 1978  Tuckerman    178/224,200,770 Apr., 1980  Hellman et al.                              380/304,405,829 Sept., 1983 Rivest et al.                              380/304,850,019 Jul., 1989  Shimizu et al.                              380/295,003,597 Mar., 1991  Merkle       380/375,214,703 May, 1993   Massey et al.                              380/375,276,737 Jan., 1994  Micali       380/305,351,299 Sept., 1994 Matsuzaki et al.                              380/295,511,123 Apr., 1996  Adams        380/295,515,307 May, 1996   Aiello et al.                              364/7175,577,123 Nov., 1996  Shimada      380/30______________________________________ 
    
     OTHER PUBLICATIONS 
     &#34;A New Random Number Generator from Permutation Groups&#34;, S. S. Magliveras, B. A. Oberg and A. J. Surkan, Rend. del Sem. Matemat. e Fis. di Milano, LIV (1984), pp 203-223. 
     &#34;A cryptosystem from logarithmic signatures of finite groups&#34;, S. S. Magliveras. Proceedings of the 29&#39;th Midwest Symposium on Circuits and Systems, Elsevier Publishing Company (1986), pp 972-975. 
     &#34;The Linear Complexity Profile of Cryptosystem PGM&#34;, S. S. Magliveras and N. D. Memon, Congressus Numerantium, Utilitas Mathematica, 72 (1989), pp 51-60. 
     &#34;On Logarithmic Signatures and Applications&#34;, N. D. Memon, M. Sc. Thesis University of Nebraska--Lincoln, (1989), pp 1-59. 
     &#34;Complexity tests for cryptosystem PGM&#34;, S. S. Iagliveras, N. D. Memon and K. C. Tam, Congressus Numerantium, Utilitas Mathematica, 79 (1990), pp 61-68. 
     &#34;Algebraic Properties of Cryptosystem PGM&#34;, S. S. Magliveras and N. D. Memon, Journal of Cryptology, 5 (1992), pp 167-183. 
     &#34;Factorizations of elementary Abelian p-groups and their cryptographic significance&#34;, M. Qu and S. A. Vanstone, J. of Cryptology, 7 (1994), pp 201-212. 
     &#34;A Parallel Permutation Multiplier for a PGM Crypto-chip&#34;, T. Horvath, S. Magliveras, Tran van Trung, Advances in Cryptology--CRYPTO&#39;94, Springer-Verlag 1994, pp 108-113. 
     Disclosure of the Invention 
     The present invention is a vector encryption system which utilizes a user supplied secret data key and a data key expanding pseudo-random number generator, to provide a sequence of pseudo-random numbers which provide direction for its operation. Said vector encryption system includes a fixed, accessible, first logarithmic signature which is developed and stored in a first logarithmic signature containing means, and from which first logarithmic signature are formed additional logarithmic signatures by operation of a mathematical operations means, which additional logarithmic signatures are then utilized, via factorization or composition procedures, to encrypt an input vector. 
     To aide with understanding, it is disclosed that logarithmic signatures consist of a plurality of mathematical construct blocks, each of which mathematical construct blocks contains at least two permutations of a sequential plurality of numbers. A property of logarithmic signatures requires that they be a collection of ordered mathematical construct blocks in which each input vector encrypted by utilization thereof can be uniquely represented as one, and only one composition of permutations which are present in said logarithmic signature, one such composed permutation being selected from each of said ordered mathematical construct blocks. Said property is associated with groups of permutations in Symmetric groups of all permutations of a sequence of a plurality of numbers which constitute a &#34;Sylow&#34; 2-subgroup of said symmetric group. The &#34;Sylow&#34; criteria are discussed in the Detailed Description Section of this Disclosure. It is also disclosed that a composition means accepts a sequential plurality of input permutations and provides an output which is the product thereof. For insight, it is disclosed that the term &#34;product&#34; as utilized herein is actually a mapping as exemplified by the following: ##EQU5## 
     To follow the &#34;multiplication&#34; process which provides a &#34;product&#34; in C, begin in the first row of A and note that, for instance, 4 therein maps to 3 in the second row of A; then said resulting 3 is applied to the first row of B and is seen to map to 8 in the second row of B, such that the &#34;product&#34; of A×B which is shown in C under 4 of the first row in C, is 8. Other entries in A are handled in the same fashion to provide the entire A×B result as shown in C. 
     It is also disclosed that a factorization means finds the positions of permutations in a logarithmic signature such that when said permutations are composed the result is a vector input to said factorization means. Said permutation positions in said logarithmic signature are each assigned location identifying &#34;pointer&#34; binary digits, which when concatenated provide an output vector. The operational aspects of a factorization means are better illuminated in the Detailed Description Section of this Disclosure, but it is noted that the output in C (ie. 1 2 7 8 5 6 3 4) in the foregoing example would be given at the outset of a factorization process, and the factorization process then yields the permutations in B (ie. 1 2 8 7 6 5 4 3) and A (ie. 1 2 4 3 6 5 8 7) which when multiplied together, provide said output in C is provided. 
     While a present invention system can provide a single stage of vector encryption based in utilization of either factorization or composition, a preferred embodiment of the present invention vector encryption system is comprised of two stages, each of which stages applies one of the factorization or composition processes, to the end that a doubly encrypted version of an input vector is provided as an output vector. As a result there are four configurations of a preferred present invention two stage vector encryption system: 
     1. Factorization followed by composition; 
     2. Factorization followed by factorization; 
     3. Composition followed by composition; and 
     4. Composition followed by factorization. 
     While systems which apply more than two such stages are within the scope of the present invention, only the four identified present invention configurations are described in more detail in the following. It should be clear that adding a third, fourth etc. stage of encryption would simply involve repeated application of described stages which apply factorization or composition as are described in the following. 
     It is noted that in what follows, functional blocks are identified and labeled as: 
     primary and secondary mathematical operations means; 
     primary and secondary factorization means; 
     primary and secondary composition means; 
     factorization and composition means; 
     first, second and third logarithmic signature containing means; 
     multiplier means and decomposition means; 
     vector accepting means for receiving input binary digit vectors; and 
     data key expanding pseudo-random number generator and fourth and fifth logarithmic signature containing means. 
     It is to be understood that each functional block group can be a physically separate circuit means, or selections from said functional blocks group can be constructed as a circuit means while other selections are combined into separate circuitry, or all identified functional blocks can be physically one circuit means. The listed functional blocks are identified as convenient means to present and distinguish functions performed by the present invention. Any combinations of physical circuit elements into functional blocks which perform multiple functions equivalent to those described herein are also possible and are within the scope of the present invention as Claimed. For instance, physically combined circuitry factorization and decomposition means and combined composition means and multiplier means are possible. 
     First Stage Factorization 
     A present invention system for encrypting input vectors of length (l), which input vectors each consist of a sequential plurality of binary digits, can then comprise a first stage which applies factorization and said first stage can be described as functionally comprised of: 
     a. a vector accepting means for receiving input binary digit vectors; and 
     b. a data key expanding pseudo-random number generator means for accepting a user provided input data key, and for generating and outputting a data key dependent sequence of pseudo-random numbers; and 
     c. a first logarithmic signature containing means which comprises means for containing a first logarithmic signature which consists of plurality of mathematical construct blocks, each of said mathematical construct blocks containing at least two permutations of a sequential plurality of numbers; and 
     d. a second logarithmic signature containing means which comprises means for containing a second logarithmic signature which consists of plurality of mathematical construct blocks, each of said mathematical construct blocks containing at least two permutations of a sequential plurality of numbers; and 
     e. a primary mathematical operations means which comprises means for accepting a sequence of pseudo-random numbers and means for accessing said first logarithmic signature containing means, and means for accessing said second logarithmic signature containing means, and means for applying direction found in a sequence of pseudo-random numbers, to a first logarithmic signature caused to be contained in said first logarithmic signature containing means, to the end that at least a second logarithmic signature is produced by said primary mathematical operations means and caused to be contained in said second logarithmic signature containing means; and 
     f. a primary factorization means for determining, accessing and concatenating into a primary factorization means output vector, binary pointers which identify locations of permutations in a second logarithmic signature caused to be present in said secondary logarithmic signature containing means, which permutations, when sequentially composed, duplicate a vector caused to be input into said primary factorization means. 
     In use a user defined data key is input to said data key expanding pseudo-random number generator means and said data key expanding pseudo-random number generator means outputs a sequence of pseudo-random numbers in response; and said sequence of pseudo-random numbers is received by said primary mathematical operations means and caused to direct alteration of a first logarithmic signature caused to be contained in said first logarithmic signature containing means, to the end that a second logarithmic signature is produced and caused to be contained in said second logarithmic signature containing means. This is accomplished while preserving a property of logarithmic signatures requiring that they be a collection of ordered mathematical construct blocks in which each input vector encrypted by utilization thereof can be uniquely represented as one, and only one composition of permutations which are present in said logarithmic signature, one such permutation subjected to composition being selected from each of said ordered mathematical construct blocks. 
     Also in use, at least one input vector consisting of a sequence of binary digits, is input to said primary factorization means from said vector accepting means for receiving input binary digit vectors and is utilized by said primary factorization means to determine selection of permutations present in said mathematical construct blocks of said second logarithmic signature which when sequentially composed result in said at least one input vector. Said primary factorization means then assigns identified permutations in each of said mathematical construct blocks of said second logarithmic signature present in said second logarithmic signature containing means, a binary digit pointer which identifies the permutation location within said second logarithmic signature. Said primary factorization means then sequentially concatenates said determined binary digit location pointers into a once encrypted vector version of said at least one input vector input to said vector accepting means for receiving input binary digit vectors and makes said once encrypted vector version of said at least one input vector available as output therefrom. 
     Second Stage Composition 
     Said present invention system for encrypting input vectors which applies first stage factorization based encryption as just described, can also further comprise a second stage of encryption which applies composition and said second stage can be described as functionally comprised of: 
     a. a third logarithmic signature containing means which comprises means for containing a third logarithmic signature which consists of plurality of mathematical construct blocks, each of said mathematical construct blocks containing at least two permutations of a sequential plurality of numbers; and 
     b. a composition means which comprises means for identifying, accessing and sequentially multiplying a plurality of permutations in a third logarithmic signature caused to be present in said third logarithmic signature containing means into a composition means output vector, which permutations are each a sequential plurality of binary digits. 
     In use said sequence of pseudo-random numbers produced by said pseudo-random number generator means is accepted by a selection from said group consisting of: (said primary mathematical operations means and a mathematical operations means other than said primary mathematical operations means which is functionally similar to said primary mathematical operations means). Said selection comprises means for accepting a sequence of pseudo-random numbers and means for accessing said first logarithmic signature containing means, and means for accessing said third logarithmic signature containing means, and means for applying direction found in a sequence of pseudo-random numbers to a first logarithmic signature caused to be contained in said first logarithmic signature containing means, to the end that a third logarithmic signature is produced by said primary mathematical operations means and caused to be contained in said third logarithmic signature containing means. This is accomplished while preserving a property of logarithmic signatures requiring that they be a collection of ordered mathematical construct blocks in which each input vector encrypted by utilization thereof can be uniquely represented as one, and only one composition of permutations which are present in said logarithmic signature, one such permutation subjected to composition being selected from each of said ordered mathematical construct blocks, said third logarithmic signature being non-identical to said second logarithmic signature. 
     Also in use, said once encrypted vector version of at least one input vector made available by said primary factorization means is caused to be entered to said composition means which accesses said third logarithmic signature caused to be present in said third logarithmic signature containing means, such that a permutation in each of said mathematical construct blocks of said third logarithmic signature is identified. Said identified permutations in each of said mathematical construct blocks of said third logarithmic signature are then caused to be sequentially multiplied in said composition means, to the end that a twice encrypted version of said at least one input vector entered to said vector accepting means for receiving input binary digit vectors is made available by said composition means as output therefrom. 
     It is noted that FIG. 1 shows functionally, in block diagram form, a two stage present invention system for encrypting input vectors which comprises a first stage primary factorization means and a second stage composition means as described. The dashed lines encompass groupings of circuit elements which can each be considered as a single unit. For instance, in the Claims a primary factorization means and a second logarithmic signature and a composition means and a third logarithmic signature are identified as functionally separate only to enable description of the present invention vector encryption system operation. It is to be understood, in interpreting the Functionally Focused Claims, that in actual circuitry the functionally identified circuit element blocks might not be quite as independent as shown. 
     Second Stage Factorization 
     Said present invention system for encrypting input vectors which applies first stage factorization based encryption as described, can alternatively further comprise a second stage of encryption which also applies factorization, and said second stage can be described as functionally comprised of: 
     a. a third logarithmic signature containing means which comprises means for containing a third logarithmic signature consisting of plurality of mathematical construct blocks, each of said mathematical construct blocks containing at least two permutations of a sequential plurality of numbers; and 
     b. a secondary factorization means for determining, and concatenating into a secondary factorization means output vector, binary pointers which identify locations of permutations in a third logarithmic signature caused to be present in said third logarithmic signature containing means, which permutations, when sequentially composed, duplicate a vector caused to be input into said secondary factorization means. 
     In use said sequence of pseudo-random numbers produced by said pseudo-random number generator means is accepted by a selection from the group consisting of: (said primary mathematical operations means and a mathematical operations means other than said primary mathematical operations means which is functionally similar to said primary mathematical operations means). Said selection comprises means for accepting a sequence of pseudo-random numbers and means for accessing said first logarithmic signature containing means, and means for accessing said third logarithmic signature containing means, and means for applying direction found in a sequence of pseudo-random numbers to a first logarithmic signature caused to be contained in said first logarithmic signature containing means, to the end that a third logarithmic signature is produced by said primary mathematical operations means and caused to be contained in said third logarithmic signature containing means. This is accomplished while preserving a property of logarithmic signatures requiring that they be a collection of ordered mathematical construct blocks in which each input vector encrypted by utilization thereof can be uniquely represented as one, and only one composition of permutations which are present in said logarithmic signature, one such permutation subjected to composition being selected from each of said ordered mathematical construct blocks, said third logarithmic signature being non-identical to said second logarithmic signature. 
     Also in use said once encrypted vector version of said at least one input vector made available by said primary factorization means is caused to be entered to said secondary factorization means and is utilized thereby to determine selection of permutations present in said mathematical construct blocks of said third logarithmic signature which when sequentially composed result in said at least one once encrypted vector version input thereto. Said secondary factorization means then assigns identified permutations in each of said mathematical construct blocks of said third logarithmic signature present in said third logarithmic signature containing means, a binary digit pointer which identifies the permutation location within said third logarithmic signature. This is followed by said secondary factorization means sequentially concatenating said determined binary digit location pointers into a twice encrypted vector version of said at least one input vector input to said vector accepting means for receiving input binary digit vectors, to the end that said twice encrypted version of said at least one input vector entered to said vector accepting means for receiving input binary digit vectors is made available by said secondary factorization means as output therefrom. 
     It is noted that FIG. 2 shows functionally, in block diagram form, a two stage present invention system for encrypting input vectors which comprises a first stage primary factorization means and a second stage composition means as described. The dashed lines encompass groupings of circuit elements which can each be considered as a single unit. For instance, in the Claims a primary factorization means and a second logarithmic signature and a secondary factorization means and a third logarithmic signature are identified as functionally separate only to enable description of the present invention vector encryption system operation. It is to be understood, in interpreting the Functionally Focused Claims, that in actual circuitry the functionally identified circuit element blocks might not be quite as independent as shown. 
     First Stage Composition 
     A present invention system for encrypting input vectors of length (l), which input vectors each consist of a sequential plurality of binary digits, can alternatively comprise a first stage which applies composition based encryption, which first stage can be described as functionally comprised of: 
     a. a vector accepting means for receiving input binary digit vectors; and 
     b. a data key expanding pseudo-random number generator means for accepting a user provided input data key, and for generating and outputting a data key dependent sequence of pseudo-random numbers; and 
     c. a first logarithmic signature containing means which comprises means for containing a first logarithmic signature which consists of plurality of mathematical construct blocks, each of said mathematical construct blocks containing at least two permutations of a sequential plurality of numbers; and 
     d. a second logarithmic signature containing means which comprises means for containing a second logarithmic signature which consists of plurality of mathematical construct blocks, each of said mathematical construct blocks containing at least two permutations of a sequential plurality of numbers; and 
     e. a primary mathematical operations means which comprises means for accepting a sequence of pseudo-random numbers and means for accessing said first logarithmic signature containing means, and means for accessing said second logarithmic signature containing means, and means for applying direction found in a sequence of pseudo-random numbers to a first logarithmic signature caused to be contained in said first logarithmic signature containing means, to the end that at least a second logarithmic signature is produced by said primary mathematical operations means and caused to be contained in said second logarithmic signature containing means; and 
     f. a primary composition means which comprises means for identifying, accessing and sequentially multiplying a plurality of permutations in a second logarithmic signature caused to be present in said second logarithmic signature containing means into a primary composition means output vector, which permutations are each a sequential plurality of binary digits. 
     In use a user defined data key is input to said data key expanding pseudo-random number generator means and said data key expanding pseudo-random number generator means provides a sequence of pseudo-random numbers in response and said sequence of pseudo-random numbers is applied by said primary mathematical operations means to a first logarithmic signature caused to be contained in said first logarithmic signature containing means, to the end that a second logarithmic signature is produced and caused to be contained in said second logarithmic signature containing means. This is accomplished while preserving a property of logarithmic signatures requiring that they be a collection of ordered mathematical construct blocks in which each input vector encrypted by utilization thereof can be uniquely represented as one, and only one composition of permutations which are present in said logarithmic signature, one such permutation subjected to composition being selected from each of said ordered mathematical construct blocks. 
     Also in use, at least one input vector is input to said vector accepting means for receiving input binary digit vectors and is caused to be entered to said primary composition means which accesses said second logarithmic signature caused to be present in said second logarithmic signature containing means such that a permutation in each of said mathematical construct blocks of said second logarithmic signature is identified. Said identified permutations in each of said mathematical construct blocks of said second logarithmic signature are then caused to be sequentially multiplied in said primary composition means, to the end that a once encrypted version of said at least one input vector entered to said vector accepting means for receiving input binary digit vectors is made available by said primary composition means as output therefrom. 
     Second Stage Composition 
     Said present invention system for encrypting input vectors which applies first stage composition based encryption as just described, can also further comprise a second stage which applies composition based encryption, and said second stage can be described as functionally comprised of: 
     a. a third logarithmic signature containing means which comprises means for containing a third logarithmic signature which consists of plurality of mathematical construct blocks, each of said mathematical construct blocks containing at least two permutations of a sequential plurality of numbers; and 
     b. a secondary composition means which comprises means for identifying, accessing and sequentially multiplying a plurality of permutations in a third logarithmic signature caused to be present in said third logarithmic signature containing means into a secondary composition means output vector, which permutations are each a sequential plurality of binary digits. 
     In use said sequence of pseudo-random numbers produced by said pseudo-random number generator means is accepted by a selection from said group consisting of: (said primary mathematical operations means and a mathematical operations means other than said primary mathematical operations means which is functionally similar to said primary mathematical operations means). Said selection comprises means for accepting a sequence of pseudo-random numbers and means for accessing said first logarithmic signature containing means, and means for accessing said third logarithmic signature containing means, and means for applying direction found in a sequence of pseudo-random numbers to a first logarithmic signature caused to be contained in said first logarithmic signature containing means, to the end that a third logarithmic signature is produced by said primary mathematical operations means and caused to be contained in said third logarithmic signature containing means. This is accomplished while preserving a property of logarithmic signatures requiring that they be a collection of ordered mathematical construct blocks in which each input vector encrypted by utilization thereof can be uniquely represented as one, and only one composition of permutations which are present in said logarithmic signature, one such permutation subjected to composition being selected from each of said ordered mathematical construct blocks, said third logarithmic signature being non-identical to said second logarithmic signature. 
     Also in use, said once encrypted vector version of at least one input vector made available by said primary composition means is caused to be entered to said secondary composition means which accesses said third logarithmic signature caused to be present in said third logarithmic signature containing means such that a permutation in each of said mathematical construct blocks of said third logarithmic signature is identified. Said identified permutations in each of said mathematical construct blocks of said third logarithmic signature are then caused to be sequentially multiplied in said secondary composition means, to the end that a twice encrypted version of said at least one input vector entered to said vector accepting means for receiving input binary digit vectors is made available by said secondary composition means as output therefrom. 
     It is noted that FIG. 3 shows functionally, in block diagram form, a two stage present invention system for encrypting input vectors which comprises a first stage primary factorization means and a second stage composition means as described. The dashed lines encompass groupings of circuit elements which can each be considered as a single unit. For instance, in the Claims a primary composition means and a second logarithmic signature and a secondary composition means and a third logarithmic signature are identified as functionally separate only to enable description of the present invention vector encryption system operation. It is to be understood, in interpreting the Functionally Focused Claims, that in actual circuitry the functionally identified circuit element blocks might not be quite as independent as shown. 
     Second Stage Factorization 
     Said present invention system for encrypting input vectors which applies first stage composition based encryption as just described, can also further comprise a second stage which applies factorization based encryption, and said second stage can be described as functionally comprised of: 
     a. a third logarithmic signature containing means which comprises means for containing a third logarithmic signature consisting of plurality of mathematical construct blocks, each of said mathematical construct blocks containing at least two permutations of a sequential plurality of numbers; and 
     b. a factorization means for determining, accessing and concatenating into a factorization means output vector, binary pointers which identify locations of permutations in a third logarithmic signature caused to be present in said third logarithmic signature containing means, which permutations, when sequentially multiplied together, duplicate a vector caused to be input thereinto. 
     In use said sequence of pseudo-random numbers produced by said pseudo-random number generator means is accepted by a selection from the group consisting of: (said primary mathematical operations means and a mathematical operations means other than said primary mathematical operations means which is functionally similar to said primary mathematical operations means). Said selection comprises means for accepting a sequence of pseudo-random numbers and means for accessing said first logarithmic signature containing means, and means for accessing said third logarithmic signature containing means, and means for applying direction found in a sequence of pseudo-random numbers to a first logarithmic signature caused to be contained in said first logarithmic signature containing means, to the end that a third logarithmic signature is produced by said primary mathematical operations means and caused to be contained in said third logarithmic signature containing means. This is accomplished while preserving a property of logarithmic signatures requiring that they be a collection of ordered mathematical construct blocks in which each input vector encrypted by utilization thereof can be uniquely represented as one, and only one composition of permutations which are present in said logarithmic signature, one such permutation subjected to composition being selected from each of said ordered mathematical construct blocks, said third logarithmic signature being non-identical to said second logarithmic signature. 
     Also in use said once encrypted vector version of said at least one input vector which is output by said primary composition means is input to said factorization means and utilized thereby to determine selection of permutations present in said mathematical construct blocks of said third logarithmic signature which when sequentially composed result in said at least once encrypted vector version input thereto. Said factorization means then assigns identified permutations in each of said mathematical construct blocks of said third logarithmic signature present in said third logarithmic signature containing means, a binary digit pointer which identifies the permutation location within said third logarithmic signature. Said factorization means then sequentially concatenates said determined binary digit location pointers into a twice encrypted vector version of said at least one input vector input to said vector accepting means for receiving input binary digit vectors, to the end that said twice encrypted version of said at least one input vector entered to said vector accepting means for receiving input binary digit vectors is made available by said factorization means as output therefrom. 
     It is noted that FIG. 4 shows functionally, in block diagram form, a two stage present invention system for encrypting input vectors which comprises a first stage primary factorization means and a second stage composition means as described. The dashed lines encompass groupings of circuit elements which can each be considered as a single unit. For instance, in the Claims a primary composition means and a second logarithmic signature and a factorization means and a third logarithmic signature are identified as functionally separate only to enable description of the present invention vector encryption system operation. It is to be understood, in interpreting the Functionally Focused Claims, that in actual circuitry the functionally identified circuit element blocks might not be quite as independent as shown. 
     Additional Functional Element Description 
     With the basic present invention system configurations which provide for two stage combinations of factorization and/or composition to be applied to encrypt input vectors now disclosed, attention is turned to more detailed description of the functional elements identified, namely: 
     1. The form of the first logarithmic signature; and 
     2. The data key expanding pseudo-random number generator means; and 
     3. The mathematical operations means; and 
     4. The factorization means; and 
     5. The composition means. 
     First Logarithmic Signature 
     The preferred present invention first logarithmic signature which is contained in the logarithmic signature containing means comprises a plurality of mathematical construct blocks, each of which mathematical construct blocks contains two permutations of a sequential plurality of numbers, said first logarithmic signature being developed by a process of: 
     a. defining a vector I s  =(1, 2, 3, . . . , 2 s ); 
     b. defining a vector I s  =(2 s  +I s ); 
     c. defining an array ##EQU6## 
     d. defining an array ##EQU7## 
     e. defining logarithmic signatures ##EQU8## each of strength 1; 
     f. utilizing the above defined I s , I s , J 1 , J 1 , α 1  and α 1  in a recursive manner to construct additional first logarithmic signatures of increasing strengths: ##EQU9## 
     where the recursively progressing alpha&#39;s (α&#39;s) of increasing strengths (s) are the first logarithmic signature. 
     A system for encrypting input vectors as just described comprises a first logarithmic signature of strength (s), where (s) is an integer, in which, in use, an input vector input to said vector accepting means for receiving input binary digit vectors consists of a plurality sequence of binary digits of length (l=2 s  -1). 
     Scalable Present Invention System Where Vector Length Is Not Equal To (2 s  -1) Where (s) Is The Strength Of The First Logarithmic Signature 
     A system for encrypting input vectors can also be comprised of (n) systems for encrypting vectors as just described, each of said (n) systems for encrypting vectors having a first logarithmic signature of some strength (s i ), where (s i ) is an integer, in which, in use, an input vector input to an effective vector accepting means for receiving input binary digit vectors consists of a sequential plurality of binary digits of length (l), where (l≠2 s  -1 ) for any integer (s); 
     said system for encrypting input vectors providing a total of (n) first logarithmic signatures, the strengths of which sum to (s&#39;), and 
     in which a first, initial, sequence of binary digits of length (2 s .sbsp.1 -1) of said input vector is input to one of said (n) systems for encrypting input vectors having a first logarithmic signature of strength (s 1 ), and in which a second, following, sequence of binary digits of length (2 s .sbsp.2 -1) of said input vector is input to a second of said systems for encrypting input vectors having a first logarithmic signature of strength (s 2 ), and 
     in which, as necessary, (n) additional, following sequences of binary digits of length (2 s .sbsp.i -1) of said input vector which consists of a plurality sequence of binary digits are input to (n) additional systems for encrypting input vectors each having first logarithmic signatures of strength (s i ); 
     such that an effective system for encrypting input vectors with an effective first logarithmic signature of strength (s&#39;=s 1  +s 2  + . . . +s n ) is achieved and into which effective system for encrypting input vectors is input said input vector which consists of a plurality sequence of binary digits of length (l), where (l=2 s&#39; ). 
     Data Key Expanding Pseudo-Random Number Generator 
     A data key expanding, pseudo-random number generator means comprises a forth logarithmic signature and a fifth logarithmic signature, in a forth logarithmic signature and a fifth logarithmic signature containing means respectively; such that in use a user provided data key is input to said pseudo-random number generator means and applied to said forth logarithmic signature to the end that, by a procedure involving a selection from the group consisting of: (factorization and composition), a first encrypted version of said data key is produced, and such that said first encrypted version of said data key is applied to said fifth logarithmic signature to the end that, by a procedure involving a selection independently selected from the group consisting of: (factorization and composition), a second encrypted version of said data key is produced, said second encrypted version of said data key being an expanded data key dependent sequence of pseudo-random numbers. It is noted that FIGS. 1-4 basically, functionally show said pseudo-random number generator means where the shown pseudo-random number generator means and the primary/secondary mathematical operations means and the first logarithmic signature containing means are considered as deleted so that logarithmic signature in the second interpreted as fourth and third interpreted as fifth, logarithmic signature means are fixed rather than set by action of the primary/secondary mathematical operations means and a first logarithmic signature, and a user provided input data key is considered entered at the vector accepting means for receiving input binary digit vectors. 
     Mathematical Operations Means 
     A present mathematical operations means selected from the group consisting of: (said primary mathematical operations means and said secondary mathematical operations means), accesses said first logarithmic signature and produces a logarithmic signature selected from the group consisting of: (said second logarithmic signature and said third logarithmic signature), therefrom; said present mathematical operations means comprising means for performing at least one mathematical operation selection from the group consisting of: 
     1. commutative shuffle; 
     2. fusion procedure; 
     3. randomization procedure; and 
     4. permutation shuffle; 
     Commutative Shuffle 
     Said commutative shuffle, as directed by said expanded data key dependent, expanded sequence of pseudo-random numbers, functionally comprises the steps of: 
     a. identifying at least one pair of adjacent mathematical construct blocks in said first logarithmic signature, in which permutations in one said mathematical construct block commute with permutations in the adjacent mathematical construct block in that the same product result is achieved when said permutations are multiplied together regardless of an order in which said pair of permutations are multiplied together; and further based upon said data key dependent expanded sequence of pseudo-random numbers proceed to: (interchange the positions of said identified adjacent mathematical construct blocks in said first logarithmic signature or leave the positions of said identified adjacent mathematical construct blocks unchanged in said first logarithmic signature); and 
     b. repeating step a. as directed by said expanded data key dependent, expanded sequence of pseudo-random numbers. 
     Fusion Procedure 
     Said fusion procedure functionally comprises the steps of, as directed by said expanded random data key dependent sequence of pseudo-random numbers: 
     identifying at least one sequential grouping of mathematical construct blocks in said first logarithmic signature, each of which mathematical construct blocks contains two permutations of a sequential plurality of numbers; 
     from each of said at least one sequential grouping of mathematical construct blocks in said first logarithmic signature forming a separate mathematical construct block which contains more than two permutations of a sequential plurality of numbers. 
     The resulting logarithmic signature does not then consist entirely of a plurality of mathematical construct blocks each of which contain only two permutations of a sequential plurality of numbers, but rather consists of a number of mathematical construct blocks, some of which have more than two permutations therein. 
     As an example, consider three mathematical construct blocks, each of which contain two permutations: ##EQU10## are grouped together. Then application of the Fusion Procedure will provide a single mathematical construct block therefrom comprising 2 3  or eight (8) permutations as follows: ##EQU11## 
     Randomization Procedure 
     Said randomization procedure functionally comprises, as directed by said expanded data key dependent sequence of pseudo-random numbers, the steps of: 
     a. selecting a mathematical construct block in a logarithmic signature which consists of a plurality of mathematical construct blocks, said selected mathematical construct block consisting of at least two permutations of a sequential plurality of numbers, 
     then selecting a permutation therein; 
     then for said selected permutation selecting permutation(s), one each, from at least one alternative, other, mathematical construct block in said logarithmic signature; 
     then multiplying said selected permutations in said selected mathematical construct block and in said alternative, other, mathematical construct blocks together and replacing said selected permutation in said selected mathematical construct block with the result of said multiplication, to form a replacement mathematical construct block for said selected mathematical construct block, and 
     b. as directed by said expanded data key dependent sequence of pseudo-random numbers, repeating step a. for other permutations in said selected mathematical construct block in said logarithmic signature; and 
     then replacing said selected mathematical construct block in said logarithmic signature with said replacement mathematical construct block; and 
     c. as directed by said expanded data key dependent sequence of pseudo-random numbers, repeating step a. but selecting an alternative, other, mathematical construct block in said logarithmic signature to be the selected mathematical construct block than was selected in the first application of step a.; and 
     then replacing said selected alternative, other, mathematical construct block in said logarithmic signature with said replacement mathematical construct block. 
     It is noted that practical application of the Randomization Process requires that only mathematical construct blocks &#34;below&#34; a mathematical construct block in a logarithmic signature being Randomized be accessed as alternative, other, mathematical construct blocks. For instance if mathematical construct blocks A, B, C and D are present in a logarithmic signature as: ##EQU12## and it is mathematical construct block A which is being subjected to Randomization, then one permutation from each of mathematical construct blocks B, C and D are composed with a selected permutation in mathematical construct block A, and said selected permutation in mathematical construct block A replaced with the result. This procedure can of course be, but is not necessarily, repeated for each permutation in mathematical construct block A to the end that a new mathematical construct block A finally replaces the original mathematical construct block A being Randomized. However, if it is mathematical construct block B which is being subjected to Randomization, then at least one selected permutation therein will be composed with selected permutations, one each, from only mathematical construct blocks C and D. As well, if it is mathematical construct block C which is being Randomized, only a permutation in mathematical construct block D will be selected and composed with a selected permutation in mathematical construct block C. It is possible to perform Randomization involving composition of a selected permutation in a mathematical construct block being Randomized with a permutation selected from a mathematical construct block located &#34;above&#34; the mathematical construct block in said logarithmic signature which is being Randomized, but additional considerations then come into play and the preferred present invention embodiment does not typically tend to such additional considerations as the benefits achieved do not justify the effort required. 
     Permutation Shuffle 
     Said permutation shuffle, as directed by said expanded data key dependent sequence of pseudo-random numbers, functionally comprises the step(s) of: 
     a. identifying at least one pair of permutations in a selected mathematical construct block in said logarithmic signature, and based upon said expanded data key dependent sequence of pseudo-random numbers proceed to reverse the positions of said identified permutations in said selected mathematical construct block; and 
     b. as directed by said expanded data key dependent sequence of pseudo-random numbers, repeating step a. for other permutation pairs in said selected mathematical construct block in said logarithmic signature; and 
     c. as directed by said expanded data key dependent sequence of pseudo-random numbers, repeating step a. but modified by the selection of an alternative, other, mathematical construct block in said logarithmic signature. 
     Any of said mathematical operations performed is performed only if, and only in a sequence which provides that, the property of logarithmic signatures requiring that they be a collection of ordered mathematical construct blocks in which each input vector encrypted by utilization thereof can be uniquely represented as one, and only one composition of permutations which are present in said logarithmic signature, one such composed permutation being selected from each of said ordered mathematical construct blocks, is preserved. 
     Factorization Means 
     A present invention factorization means selected from the group consisting of: (said primary factorization means and said secondary factorization means), functionally comprises a decomposition means with the operational property that an output vector produced thereby and made present at an output means thereof is a product of a first vector input thereto at a first input means thereof and an inverse second vector input thereto at a second input means thereof; an input to said factorization means being capable of accessing, via a feedback means, said output means. In use, repeated application is made thereof in which, at each application after the first, the output of said factorization means produced at said output means thereof by a previous application, is input to said first input means thereof simultaneous with input of an inverted vector to said second input means. As the Factorization procedure is complex, an example of the practice thereof is deferred to the Detailed Description Section of this Disclosure. 
     Composition Means 
     A present invention composition means selected from the group consisting of: (said primary composition means and said secondary composition means), functionally comprises a multiplier means with the operational property that an output vector produced thereby and made present at an output means thereof is a product of a first vector input thereto and of a second vector input thereto; an input to said composition means being capable of accessing, via a feedback means, said output means. In use, repeated application is made thereof in which, at each application after the first, the output of said multiplier means produced at said output means thereof by a previous application, is input to said first input means thereof simultaneous with input of a vector to said second input means which is to be multiplied by said vector input to said first input means. 
     It is important to understand that the preferred embodiment of the present invention operates on compact form binary vectors of length (l)=(2 n  -1) which are input to a vector accepting means for receiving input binary digit vectors, which compact form binary vectors represent elements of a carrier group of permutations which is a Sylow 2-subgroup of a full symmetric group of degree 2 n , said carrier group being of size 2.sup.(2.spsp. -1 ). In this light it is noted that a preferred present invention system for encrypting vectors which comprises composition means, utilizes an &#34;N&#34; bit multiplier system for each composition means present, which &#34;N&#34; bit multiplier systems serves to multiply two compact form binary vectors A and B input thereto, each of said two compact form binary vectors A and B being of length (l)=(2 n  -1). Again, said compact form binary vectors A and B represent elements of a carrier group of permutations which is a Sylow 2-subgroup of a full symmetric group of degree 2 n , said carrier group being of size 2.sup.(2.spsp.n -1 ). Further, as better discussed in the Detailed Description Section of this Disclosure, a utilized N bit multiplier system comprises a means for accepting input of two compact form binary vectors A and B each of length (N)=(l)=(2 n  -1); and a swapping means for accepting two binary input vectors each consisting of (N-1)/2 binary bits and essentially comprising the upper and lower halves of B; the output of said swapping means consisting of two binary vectors each of length (N-1)/2 in an order selected from the group consisting of: (unchanged order and swapped order). And said multiplier system further comprising two (N-1)/2 bit &#34;self-similar&#34; sub-multiplier systems therein; where each of said two &#34;self-similar&#34; sub-multiplier systems comprises a sub-input accepting means, sub-swapping means and two sub-sub-multiplier systems. The lower input vectors of length (N-1)/2 of each sub-multiplier consisting of the two output vectors of the swapping means; and the upper input vectors of length (N-1)/2 of each sub-multiplier consisting essentially of the upper and lower halves of input vector A. Said swapping means in said multiplier system is located with respect to said two sub-multipliers in said multiplier system at a location selected from the group consisting of: (before and after) said two submultipliers, such that compact binary form vectors input thereto are input sequentially first to a selection from the group consisting of: (said swapping means and said two sub-multipliers) and then into a selection from the group consisting of: (said two sub-multipliers and said swapping means respectively). As much better described in the Detailed Description Section of this Disclosure, the sequential order of said swapping means and two sub-multipliers in an N bit multiplier system, (ie. which thereof a binary vector input thereto encounters first), is determinative of the result of multiplication and/or inversion, said result being a member of the group consisting of: (AB, A -1  B, AB -1 , and A -1 ). 
     It is again noted that the term &#34;multiplication&#34; as used herein refers to a composition mapping process as demonstrated infra herein. 
     Method of Use 
     Briefly, the method of use of the present invention can be described as a method of encrypting input vectors and/or providing a sequence of pseudo-random numbers comprising the steps of: 
     a. providing a system for encrypting input vectors which can also be used as a pseudo-random number generator means, comprising a logarithmic signature in a logarithmic signature containing means; such that in use a user provided input vector/data key is input to said system for encrypting input vectors which can also be used as a pseudo-random number generator means, and applied to said logarithmic signature to the end that, by a procedure involving a selection from the group consisting of: (factorization and composition) a once encrypted version of said input vector/data key is produced; 
     b. causing at least one input vector/data key to be input thereto; 
     c. monitoring said once encrypted version of said input &#34;vector/data key which is produced. 
     An expanded method can be described as a method of encrypting input vectors and/or providing a sequence of pseudo-random numbers comprising the steps of 
     a. providing a system for encrypting input vectors which can also be used as a pseudo-random number generator means, comprising a fourth logarithmic signature and a fifth logarithmic signature, in forth logarithmic signature and a fifth logarithmic signature containing means respectively, wherein said fourth logarithmic signature is non-identical to said fifth logarithmic signature; such that in use a user provided input vector/data key is input to said system for encrypting input vectors which can also be used as a pseudo-random number generator means, and applied to said forth logarithmic signature to the end that, by a procedure involving a selection from the group consisting of: (factorization and composition), a once encrypted version of said input vector/data key is produced; and such that said first encrypted version of said input vector/data key is applied to said fifth logarithmic signature to the end that, by a procedure involving a selection independently selected from the group consisting of: (factorization and composition), a twice encrypted version of said input vector/data key is produced; 
     b. causing at least one input vector/data key to be input thereto; 
     c. monitoring a selection from the group consisting of a once and a twice encrypted version of said input vector/data key which is produced. 
     General Discussion 
     It is generally noted that a present invention system for encrypting input vectors can provide that present said first, second and third logarithmic signature containing means each comprise computer memory, and that present said primary and secondary mathematical operations means and present said primary and secondary factorization means and present said primary and secondary composition means, and said data key expanding pseudo-random number generator means all comprise computer, software driven computer system hardware. It is further noted that a present invention system for encrypting input vectors has been described herein on a functional basis, emphasis added, and that physical circuit realization can, where functionally appropriate, provide that: 
     a. said primary and secondary mathematical operations means are physically one circuit means and distinguishable only by function performed at a point in time; 
     b. said primary and secondary factorization means are physically one circuit means and distinguishable only by function performed at a point in time; 
     c. said primary and secondary composition means are physically one circuit means and distinguishable only by function performed at a point in time; 
     d. said primary factorization means, decomposition means and said second logarithmic signature containing means are physically one circuit means and distinguishable only by function performed; 
     e. said primary composition means, multiplier means and said second logarithmic signature containing means are physically one circuit means and distinguishable only by function performed; 
     f. said secondary composition means, multiplier means and said third logarithmic signature containing means are physically one circuit means and distinguishable only by function performed; 
     g. said secondary factorization means, decomposition means and said third logarithmic signature containing means are physically one circuit means and distinguishable only by function performed; 
     h. said composition means, multiplier means and said third logarithmic signature containing means are physically one circuit means and distinguishable only by function performed; 
     i. said factorization means, decomposition means and said third logarithmic signature containing means are physically one circuit means and distinguishable only by function performed; 
     j. selections from the group consisting of: (said primary and secondary mathematical operations means, said primary and secondary factorization means, said primary and secondary composition means, said factorization and composition means, said first and second and third logarithmic signature containing means, said multiplier means and decomposition means, said vector accepting means for receiving input binary digit vectors, and said data key expanding pseudo-random number generator and forth and fifth logarithmic signature containing means), are all physically one circuit means and distinguishable only by function performed; Any combinations of physical circuit elements into functional blocks which perform multiple functions equivalent to those described herein are also possible and are within the scope of the present invention as Claimed. 
     The most preferred embodiment of the present invention, which comprises a first stage factorization encryption means and a second stage composition encryption means for providing a doubly encrypted version of an input vector, along with insight to mathematical operations basis of Sylow 2-subgroups, logarithmic signatures, commutative shuffle, fusion procedure, randomization procedure, and permutation shuffle, is provided in the Detailed Description Section of this Disclosure. For continuity purposes it is further noted that the generic terminology &#34;mathematical operations means&#34; as used in this Disclosure of the Invention Section, is specifically referred to as a &#34;Signature Generator Algorithm&#34; in the Detailed Description Section. Similarly the first, second and third logarithmic signatures are referred to as (α), (β 1 ), (β 2 ), logarithmic signatures, respectively, in the Detailed Description Section, and the data key expanding pseudo-random number generator is referred to as a &#34;cyclic encryption generator&#34; in said Detailed Description Section. Also, input vectors are termed &#34;plaintext&#34; in the Detailed Description and the terminology &#34;compact representation&#34; indicates that any permutation in a carrier group is present in binary digit form of the shortest functional length. It is further noted, and emphasised, that &#34;compact representation&#34; allows the most efficient representation of permutations in selected carrier groups G of order (2 l ). This is a very significant point. Further, the present invention allows that any given element of a carrier group G can be factorized with respect to any logarithmic signature within a large well defined family of logarithmic signatures, all in compact representation. 
     The mathematical basis of the present invention will be better understood, by reference to the Detailed Description Section of this Disclosure, in conjunction with appropriate reference to the accompanying Drawings. 
     SUMMARY OF THE INVENTION 
     It is therefore a purpose of the present invention to teach single and multiple stage secret key cryptosystems and more particularly a secret key block cipher utilizing a novel idea of efficient factorizations of permutation groups of arbitrary order 2 l . 
     It is another purpose of the present invention to identify four functional configurations of a preferred present invention two stage vector encryption system which apply factorization and composition procedures in the various orders: 
     1. factorization followed by composition; 
     2. factorization followed by factorization; 
     3. composition followed by composition; and 
     4. composition followed by factorization. 
     It is yet another purpose of the present invention to identify the present invention functional configuration consisting of factorization followed by composition as the most preferred embodiment. 
     It is still yet another purpose of the present invention to describe functional elements utilized therein, namely: 
     1. the form of the first logarithmic signature; and 
     2. the data key expanding pseudo-random number generator means; and 
     3. the mathematical operations means; and 
     4. the factorization means; and 
     5. the composition means; and 
     6. the multiplier means for accepting two input vectors, A and B, in compact representation and providing as output a selection from the group consisting of: (AB, A -1  B, AB -1 ), as well as the inverting means for accepting an input vector A, in compact representation and providing as output (A -1 ). It is yet still another purpose of the present invention to describe that it is scalable to use with vectors of any length (l), where (l)=(2 s&#39; ) by combining encryption systems which have logarithmic signatures of strength (s i ) such that (s&#39;=s 1  +s 2  + . . . +s n ). 
     It is another purpose of the present invention to describe the functions performed by a mathematical operations means as being selection from the group consisting of: 
     1. commutative shuffle; 
     2. fusion procedure; 
     3. randomization procedure; and 
     4. permutation shuffle; 
     It is yet another purpose of the present invention to describe realization utilizing computer hardware to embody present said first, second, third logarithmic signature containing means, and said primary/secondary mathematical operations means and present said primary/secondary factorization means and present said primary/secondary composition means, and factorization and composition means, and permutation multiplier means and said data key expanding pseudo-random number generator means and fourth and fifth logarithmic signature containing means etc., and to make clear that functionally identifiable separate elements in said present invention need not be physically separately identifiable in realization circuitry. 
     It is still yet another purpose of the present invention to disclose an encryption system which accepts data key as input and expands it as a sequence of pseudo-random numbers; which sequence of pseudo-random numbers is applied to a first logarithmic signature in a first logarithmic signature containing storage means to develop a second logarithmic signature, which second logarithmic signature is then stored in a second logarithmic signature containing storage means under the control of a primary mathematical operations means which comprises means for accepting a sequence of pseudo-random numbers; means for accessing said first logarithmic signature containing storage means; means for accessing said second logarithmic signature containing storage means; and means for applying a sequence of pseudo-random numbers to a first logarithmic signature, producing at least a second logarithmic signature and storing it in said second logarithmic signature containing storage means, said second logarithmic signature then being used in encrypting input vectors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1: 
     FIG. 1. shows a two stage encryption systems sequentially composing factorization and composition means. 
     FIG. 2: 
     FIG. 2. shows a two stage encryption systems sequentially composing factorization and factorization means. 
     FIG. 3: 
     FIG. 3. shows a two stage encryption systems sequentially composing composition and composition means. 
     FIG. 4: 
     FIG. 4. shows a two stage encryption systems sequentially composing composition and factorization means. 
     FIG. 5: 
     FIG. 5. explains the definition of mapping α as used in PGM from the background section. 
     FIG. 6: Multiplier MULAB(N) 
     This multiplier architecture computes the product q=a·b of two permutations a and b, entered to the circuitry at the input buses A and B in their compact representation. The result q is produced on output bus Q. The width of the input and output buses is defined by the scaling parameter N. The circuitry is purely combinational. It consists of a swapping module SW with input/output buses of width (N-1)/2 and controlled by the high order input bit A[N-1]; furthermore of a higher and a lower multiplier (UMUL and resp. LMUL) of type MULAB, but of input/output length (N-1)/2; and finally of an XOR-gate. The recursive structure is reflected in the fact, that a multiplier scaled to N embeds multipliers scaled to (N-1)/2. Whenever the scaling parameter reduces to N=1, all the embedded components, but the XOR-gate of course, become scaled to 0, and thus the recursion stops. 
     FIG. 7: Multiplier MULAB(15) 
     This is a concrete example of MULAB for scaling parameter N=15, i.e. for strength s=4. The structure is displayed here on one single hierarchical layer instead of a recursive form. This view is obtained through the expansion of the embedded recursive components. All input/output buses have width 15. The bits of input bus B are fed through a cascade of swapping modules, and finally combined in 15 XOR-gates with bits of bus A. The swapping modules are controlled by bits of A too. 
     FIG. 8: Multiplier MULAIB(N) 
     This multiplier architecture computes the product q=a -1  ·b for two permutations a and b, entered to the circuitry at the input buses A and B in their compact representation. The result q is produced on output bus Q. The width of the input and output buses is given by the scaling parameter N. The circuitry is purely combinational, and is similar to MULAB(N), except that the order of swapping module SW and multipliers UMUL and LMUL is reversed. 
     FIG. 9: Multiplier MULABI(N) 
     This multiplier architecture computes the product q=a·b -1  for two permutations a and b, entered to the circuitry at the input buses A and B in their compact representation. The result q is produced on output bus Q. The width of the input and output buses is defined by the scaling parameter N. The circuitry is purely combinational, and is similar to MULAB(N), except that swapping module SW is controlled by the high order output bit Q[N-1] instead of input bit A[N-1]. 
     FIG. 10: Inverter INV1(N) 
     This inverter architecture computes the inverse q=a -1  of a permutation a, entered to the circuitry at the input bus A in its compact representation. The result q is produced on output bus Q. The width of input and output buses is defined by the scaling parameter N. The circuitry is purely combinational. It consists of an upper and a lower inverter (UINV and resp. LINV) with input/output buses of width (N-1)/2; and of a swapping module SW with input/output buses of width (N-1)/2, and controlled by the high order input bit A[N-1]. The recursive structure is reflected in the fact, that an inverter scaled to N has embedded inverters scaled to (N-1)/2. Whenever the scaling parameter reduces to N=1, all the embedded components become scaled to 0, and thus the recursion stops. 
     FIG. 11: Another inverter: INV2(N) 
     This inverter architecture computes the inverse q=a -1  of a permutation a, entered to the circuitry at the input buses A in its compact representation. The result q is produced on output bus Q. The width of the input and output buses is defined by the scaling parameter N. The circuitry is purely combinational, and is similar to INV1(N), except that the order of swapping module SW and inverters UINV and LINV is reversed. The two schemes are equivalent with respect to function, speed and complexity. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Canonical Logarithmic Signatures of H s   
     It is well known that all Sylow p-subgroups of a finite group G are conjugate in G and hence isomorphic to each other. Hence, we talk about &#34;the&#34; Sylow p-subgroup of G when we refer to any one of these groups up to isomorphism. It can be seen that the Sylow 2-subgroup H s  of the symmetric group S 2 .spsb.s on 2 s  symbols (or points) is a group of order 2 2 .spsp.s -1 . H s  can be defined recursively as follows: 
     For s=1, H s  = 2 , the cyclic group of order 2, and 
     for s&gt;1, H s  =H s-1  ι 2  =(H s-1  ×H s-1 )· 2 , namely, the wreath product of H s-1  with  2 . 
     Our cryptosystem relies on a particular instance of H s , which acts on symbol set X s  ={1, 2, 3, . . . , 2 s  }, and is further described as follows: The two instances of H s-1  in the wreath product H s  =(H s-1  ×H s-1 )· 2  act on symbol sets X s-1  ={1, 2, 3, . . . , 2 s-  } and X s-1  =2 s-1  +X s-1  ={2 s-1  +1,2 s-1  +2,2 s-1  +3, . . . , 2 s  } respectively. In what follows we denote the first instance by H s-1  and the second instance by H s-1 . The permutation representation T s  of  2  contains exactly two permutations, the identity τ and an involution ι s , which exchanges the elements of X s-1  with the elements of X s-1 . It is easy to see that H s-1  =τ s   -1  H s-1  τ s  =H s-1 .sup.τ.sbsp.s, and H s-1  =(H s-1 ).sup.τ.sbsp.s.spsp.-1 =(H s-1 ).sup.τ.sbsp.s, i.e. H s-1  and H s-1  are conjugates of each other by means of the element τ s . 
     The canonical logarithmic signature (LS) α s  of H s  can be defined recursively in terms of the canonical LS&#39;s for H s-1 , H s-1  and T s  respectively, as follows: 
     the first 2 s-1  -1 blocks (A 0 , . . . A 2  s-1 -2 ) contain the canonical α s-1 , and fix all the elements of X s . 
     the next 2 s-1  -1 blocks (A 2  s-1 -1 , . . . , A 2  s -3 ) contain the canonical α s-1  of H s-1 , obtained by conjugating each element of α s-1  by the involution τ s . Thus, α s-1  =α s-1 .sup.τ.sbsp.s ={x.sup.τ.sbsp.s |x ε α s-1  }. Each element in α s-1  fixes X s  elementwise. 
     the last block A 2 .spsb.s -2  consists of the identity permutation ι and the involution τ s , forming the canonical LS for group T s . 
     We list the blocks A 0 , . . . , A 2 .spsb.s -2  in reverse order with A 0  occupying the bottom of the table representing the LS, A 1  just above A 0 , A 2  just above A 1 , etc. 
     We clarify the above description by means of the following constructive definitions: Let X s  ={1, 2, 3, . . . , 2 s  } and X s  =2 s  +X s  be as above. Let I s  be the vector (1, 2, 3, . . . , 2 s ), and I s  =2 s  +I s . More generally, if A is any n×m array with entries in X s , we define A to be 2 s  +A, i.e. the result of adding 2 s  to each element of A. Let J s  denote the (2 s+1  -2)×2 s  array of which each row is equal to I s . Thus, J 1  and J 1  are given by: ##EQU13## 
     We now define recursively the canonical logarithmic signature α s , of H s  by: ##EQU14## 
     (ii) Suppose next that α 1 , α 2 , . . . , α s-1  have been constructed, then: ##EQU15## 
     We note here that the above recursive definition for α s  could have been started with s=0, and α 0  =[1]. 
     We display, for example, the canonical logarithmic signatures for H 1 , H 2 , and H 3  : ##EQU16## 
     This process continues inductively to define the canonical logarithmic signature α s , for H s  in terms of that of H s-1 . We note that the rows of each α s  are permutations of the symbols of X s  (in cartesian form.) Moreover, there are 2 s  -1 consecutive blocks of such permutations, each block containing exactly two permutations, i.e. the canonical logarithmic signature has type (2, 2, . . . , 2). It is clear that each block is a subgroup of H s . 
     Representation Of Elements In H s  With Respect To Any Logarithmic Signature 
     If β=(B 0 , B 1 , . . . , B w-1 ) is a general logarithmic signature of H s , then, |B i  |=τ i  =2 m .sbsp.i, and |H s  |=II i=0   w-1  τ i  =2 2 .spsp.s -1 . If h ε H s , then h has a unique representation as a product of the form 
     
         h=x.sub.0,j.sbsb.0 ·x.sub.1,j.sbsb.1 . . . x.sub.w-1,j.sbsb.w-1 
    
     where, x i ,j.sbsb.i is the j i   th  element of block B i , 0≦j i  &lt;τ i . Let u i  be the binary vector of length m i  representing the integer j i  in its binary representation. Then by the representation of h with respect to β we mean the binary vector of length l=2 s  -1 obtained by catenating the u i , that is: 
     
         β(h)=u.sub.0 ||u.sub.1 || . . . ||u.sub.w-1 
    
     Conversely, given any binary vector υ=(υ 0 , . . . , υ l-1 ), separate υ into successive segments υ i  of length m i , 0&lt;i&lt;w-1. Let j i  be the integer whose binary representation is υ i , 0&lt;j i  &lt;r i , 0&lt;i&lt;w-1. Now, form the permutation 
     
         h=x.sub.0j.sbsb.0 ·x.sub.1,j.sbsb.1 . . . x.sub.w-1,j.sbsb.w-1 
    
     where x i ,j.sbsb.i is as before. Then, h=β -1  (υ). 
     In the case where the logarithmic signature β is in fact the canonical logarithmic signature α as described earlier, we obtain the compact representation of the elements of H s  by binary vectors. In this case, we have α=(A 0 , . . . , A l-1 ), where |A i  |=2, and l=2 s  -1. The binary vector α(h)=(j 0 ,j 1 , . . . ,j l-1 ) is called the compact representation of h with respect to the canonical logarithmic signature α. 
     On the other hand, for any given binary vector υ=(j 0 ,j 1 , . . . , j l-1 ) there is a unique permutation h which has υ as its compact representation, namely h=x 0 ,j.sbsb.0 ·x 1 ,j.sbsb.1 . . . x l-1 ,j.sbsb.l-1. Thus the mappings α and α -1  are used to identify a permutation in the carrier group H s  with a binary vector of length l. 
     The compact representation is therefore optimal, because l is the minimum number of bits needed to represent a set with 2 l  elements. On the other hand, direct hardware implementation of permutations in their cartesian form requires (l+1) log 2  (l+1) bits per permutation. Thus, our compact representation results in a significant storage reduction by a factor of log 2  (l+1). For example, in the case of message-block length l=127, the RAM needed for storing permutations in compact form is 7 times smaller than what is required by the cartesian form. Finally, the reduction in circuit complexity when using the compact representation, together with the fact that the knapsack circuit segments of the PGM algorithm can now be deleted, results in very significant speedups over circuits using cartesian hardware representation. 
     The Signature Generation Algorithm 
     We present an algorithm for generating a very large class L of random logarithmic signatures of G=H s , starting from the canonical signature α which is the basis for the compact representation. For short, we refer to this signature generation algorithm as SGA. The four main steps of SGA perform different types of operations and result in a sequence β 0 , β 1 , . . . , β t  of LS&#39;s for G, where β 0  =α, and β=β t  is the desired randomized LS of G. Each step consists of a sequence of elementary operations. Each elementary operation transforms a logarithmic signature β i  in the sequence to a logarithmic signature β i+1  for G. Each LS β in the class L produced by SGA has the property that factorization of any group element g ε G with respect to β can be carried out efficiently. 
     Step 1. Commutative shuffle 
     If β=(B 0 , B 1 , . . . , B w-1 ) is an LS for G, then two contiguous blocks B i  and B i+1  are said to commute if xy=yx for any x ε B i  and y ε B i+1 , i.e. if they commute elementwise. An elementary operation in Step 1 consists of transforming an LS β by exhanging two neighboring commuting blocks. Step 1 generates a sequence of LS&#39;s β 0 , β 1 , . . . , β m  where β 0  =α, the canonical LS, and each β i  is obtained from β i-1 , by the exchange of two contiguous commuting blocks. Such exchanges of commuting blocks are not applied beyond Step 1. 
     Step 2. Block fusion 
     After carrying out a random number of commutative shuffle operations in Step 1, a sequence of elementary operations, called block fusions, are performed in Step 2. Each operation replaces a randomly chosen collection of contiguous blocks, say B i , B i+1 , . . . , B i+d-1 , by a new block C of size 2 d , comprised of all elements of the form x=x i  ·x 1+1  . . . x i+d-1 , where x i+j  ε B i+j , j=0, . . . , d-1. It can be shown that any LS β=(C 0 , C 1 , . . . , C w-1 ), obtained from α by means of Steps 1. and 2., has the property that (C 0 , C 1 , . . . , C i  ) is an LS for the group G i  generated by C 0 , C 1 , . . . , C i  so that G i  =C 0  ·C 1  . . . C i , and |G i  |=|C 0  |·|C 1  | . . . |C i  |. These facts are crucial in making the following randomization step possible. 
     Step 3. Randomization 
     Let β=(C 0 , . . . , C w-1 ) be the LS obtained by means of Steps 1. and 2. Then, C i  is a complete set of coset representatives of the subgroup G i-1  =C 0  ·C 1  . . . C i-1  in the subgroup G i  =C 0  ·C 1  . . . C i-1  ·C i . Step 3. proceeds as follows: For each block C i  and each element x i ,j ε C i , x i ,j is replaced by z i ,j ·x i ,j where z i ,j is a random element of the subgroup G i-1  =C 0  . . . C i-1 . The operations of Step 3. in effect accomplish a change of the coset representatives C i  by a different transversal C&#39; i . 
     Step 4. Permutation shuffle of blocks 
     Suppose that logarithmic signature β=(C 0 , . . . , C w-1 ) has resulted from Steps 1., 2., and 3. In this final step 4., each block C i  is reordered by applying a random permutation on the positions of the elements of C i . The effect of this action is to simply rearrange the elements within each block. 
     We display an example of this algorithm for the canonical signature α for H 3 . 
     We display an example of this algorithm for the canonical group basis α for H 3 . The seven blocks of canonical group basis α for H 3  : 
     
         ______________________________________α     Cartesian repr.              Compact repr.______________________________________A.sub.8     5 6 7 6 1 2 3 4                  0 0 0 0 0 0 1       1 2 3 4 5 6 7 8                  0 0 0 0 0 0 0A.sub.5     1 2 3 4 6 7 4 5                  0 0 0 0 0 1 0       1 2 3 4 5 6 7 8                  0 0 0 0 0 0 0A.sub.4     1 2 3 4 5 6 8 7                  0 0 0 0 1 0 0       1 2 3 4 5 6 7 8                  0 0 0 0 0 0 0A.sub.3     1 2 3 4 6 5 7 8                  0 0 0 1 0 0 0       1 2 3 4 5 6 7 8                  0 0 0 0 0 0 0A.sub.2     3 4 1 2 5 6 7 8                  0 0 1 0 0 0 0       1 2 3 4 5 6 7 8                  0 0 0 0 0 0 0A.sub.1     1 2 4 3 5 6 7 8                  0 1 0 0 0 0 0       1 2 3 4 5 6 7 8                  0 0 0 0 0 0 0A.sub.0     2 1 3 4 5 6 7 8                  1 0 0 0 0 0 0       1 2 3 4 5 6 7 8                  0 0 0 0 0 0 0______________________________________ 
    
     Step 1. Commutative shuffle yields: 
     
         ______________________________________β      Cartesian repr.               Compact repr.______________________________________B.sub.6 = A.sub.6        5 6 7 8 1 2 3 4                   0 0 0 0 0 0 1        1 2 3 4 5 6 7 8                   0 0 0 0 0 0 0B.sub.5 = A.sub.5        1 2 3 4 7 8 5 6                   0 0 0 0 0 1 0        1 2 3 4 5 6 7 8                   0 0 0 0 0 0 0B.sub.4 = A.sub.3        1 2 3 4 6 5 7 8                   0 0 0 1 0 0 0        1 2 3 4 5 6 7 8                   0 0 0 0 0 0 0B.sub.3 = A.sub.2        3 4 1 2 5 6 7 8                   0 0 1 0 0 0 0        1 2 3 4 5 6 7 8                   0 0 0 0 0 0 0B.sub.2 = A.sub.0        2 1 3 4 5 6 7 8                   1 0 0 0 0 0 0        1 2 3 4 5 6 7 8                   0 0 0 0 0 0 0B.sub.1 = A.sub.1        1 2 4 3 5 6 7 8                   0 1 0 0 0 0 0        1 2 3 4 5 6 7 8                   0 0 0 0 0 0 0B.sub.0 = A.sub.4        1 2 3 4 5 6 8 7                   0 0 0 0 1 0 0        1 2 3 4 5 6 7 8                   0 0 0 0 0 0 0______________________________________ 
    
     Step 2. Fusion of the blocks between double lines above yields: 
     
         ______________________________________γCartesian repr.         Compact repr. Product wrt. β______________________________________C.sub.2  5 6 7 8 4 3 0 2             0 0 0 1 0 1 1 b.sub.4,1 · b.sub.5,1 ·                           b.sub.6,1  5 6 7 8 3 4 0 2             0 0 0 0 0 1 1 b.sub.4,0 · b.sub.5,1 ·                           b.sub.6,1  5 6 7 8 2 0 3 4             0 0 0 1 0 0 1 b.sub.4,1 · b.sub.5,0 ·                           b.sub.6,1  5 6 7 8 0 2 3 4             0 0 0 0 0 0 1 b.sub.4,0 · b.sub.5,0 ·                           b.sub.6,1  1 2 3 4 8 7 5 6             0 0 0 1 0 1 0 b.sub.4,1 · b.sub.5,1 ·                           b.sub.6,0  1 2 3 4 7 8 5 6             0 0 0 0 0 1 0 b.sub.4,0 · b.sub.5,1 ·                           b.sub.6,0  1 2 3 4 6 5 7 8             0 0 0 1 0 0 0 b.sub.4,1 · b.sub.5,0 ·                           b.sub.6,0  1 2 3 4 5 6 7 8             0 0 0 0 0 0 0 b.sub.4,0 · b.sub.5,0 ·                           b.sub.6,0C.sub.1  4 3 1 2 5 6 7 8             1 0 1 0 0 0 0 b.sub.2,1 · b.sub.3,1  3 4 1 2 5 6 7 8             0 0 1 0 0 0 0 b.sub.2,0 · b.sub.3,1  2 1 3 4 5 6 7 8             1 0 0 0 0 0 0 b.sub.2,1 · b.sub.3,0  1 2 3 4 5 6 7 8             0 0 0 0 0 0 0 b.sub.2,0 · b.sub.3,0C.sub.0  1 2 4 3 5 6 8 7             0 1 0 0 1 0 0 b.sub.0,1 · b.sub.1,1  1 2 4 3 5 6 7 8             0 1 0 0 0 0 0 b.sub.0,0 · b.sub.1,1  1 2 3 4 5 6 8 7             0 0 0 0 1 0 0 b.sub.0,1 · b.sub.1,0  1 2 3 4 5 6 7 8             0 0 0 0 0 0 0 b.sub.0,0 · b.sub.1,0______________________________________ 
    
     Step 3. Randomization yields: 
     
         ______________________________________δCartesian repr.         Compact repr. Product wrt. γ______________________________________D.sub.2  8 7 5 6 4 3 1 2             1 0 1 1 0 1 1 c.sub.0,0 · c.sub.1,3 ·                           c.sub.2,7  7 8 5 6 3 4 2 1             0 0 1 0 1 1 1 c.sub.0,1 · c.sub.1,2 ·                           c.sub.2,6  6 5 8 7 2 1 3 4             1 1 0 1 0 0 1 c.sub.0,2 · c.sub.1,1 ·                           c.sub.2,5  5 6 8 7 1 2 4 3             0 1 0 0 1 0 1 c.sub.0,3 · c.sub.1,0 ·                           c.sub.2,4  1 2 3 4 8 7 5 6             0 0 0 1 0 1 0 c.sub.0,0 · c.sub.1,0 ·                           c.sub.2,3  2 1 3 4 7 8 6 5             1 0 0 0 1 1 0 c.sub.0,1 · c.sub.1,1 ·                           c.sub.2,2  3 4 2 1 6 5 7 8             0 1 1 1 0 0 0 c.sub.0,2 · c.sub.1,2 ·                           c.sub.2,1D.sub.1  4 3 2 1 5 6 7 8             1 1 1 0 0 0 0 c.sub.0,3 · c.sub.1,3 ·                           c.sub.2,0  4 3 1 2 5 6 8 7             1 0 1 0 1 0 0 c.sub.0,1 · c.sub.1,3  3 4 2 1 5 6 7 8             0 1 1 0 0 0 0 c.sub.0,2 · c.sub.1,2  2 1 3 4 5 6 8 7             1 0 0 0 1 0 0 c.sub.0,1 · c.sub.1,1D.sub.0  1 2 4 3 5 6 8 7             0 1 0 0 1 0 0 c.sub.0,3 · c.sub.1,0  1 2 4 3 5 6 8 7             0 1 0 0 1 0 0 c.sub.0,3  1 2 4 3 5 6 7 8             0 1 0 0 0 0 0 c.sub.0,2  1 2 3 4 5 6 8 7             0 0 0 0 1 0 0 c.sub.0,1  1 2 3 4 5 6 7 8             0 0 0 0 0 0 0 c.sub.0,0______________________________________ 
    
     Step 4. Permutation shuffle yields: 
     
         ______________________________________εCartesian repr.         Compact repr. Element wrt. δ______________________________________E.sub.2  1 2 3 4 8 7 5 6             0 0 0 1 0 1 0 d.sub.2,3  4 3 2 1 5 6 7 8             1 1 1 0 0 0 0 d.sub.2,0  6 5 8 7 2 1 3 4             1 1 0 1 0 0 1 d.sub.2,5  5 6 8 7 1 2 4 3             0 1 0 0 1 0 1 d.sub.2,4  2 1 3 4 7 8 6 5             1 0 0 0 1 1 0 d.sub.2,2  8 7 5 6 4 3 1 2             1 0 1 1 0 1 1 d.sub.2,7  7 8 5 6 3 4 2 1             0 0 1 0 1 1 1 d.sub.2,6  3 4 2 1 6 5 7 8             0 1 1 1 0 0 0 d.sub.2,1E.sub.1  2 1 3 4 5 6 8 7             1 0 0 0 1 0 0 d.sub.1,1  4 3 1 2 5 6 8 7             1 0 1 0 1 0 0 d.sub.1,3  1 2 4 3 5 6 8 7             0 1 0 0 1 0 0 d.sub.1,0  3 4 2 1 5 6 7 8             0 1 1 0 0 0 0 d.sub.1,2E.sub.0  1 2 3 4 5 6 8 7             0 0 0 0 1 0 0 d.sub.0,1  1 2 3 4 5 6 7 8             0 0 0 0 0 0 0 d.sub.0,0  1 2 4 3 5 6 7 8             0 1 0 0 0 0 0 d.sub.0,2  1 2 4 3 5 6 8 7             0 1 0 0 1 0 0 d.sub.0,3______________________________________ 
    
     Factorization With Respect To Signatures Generated By SGA 
     We describe a methodology for factoring any element in the carrier group G=H s  with respect to a given logarithmic signature generated by algorithm SGA. Let β=(B 0 , B 1 , . . . , B w-1 ) be a logarithmic signature of H s  obtained from SGA, where |B i  |=r i  =2 m .sbsp.i, and |H s  |=2 2 .spsp.s-1 =Π i=0   w-1  r i . Again, let α=(A 0 , A 1 , . . . , A.sub.ν-1) be the canonical signature used for the compact representation of the elements of H s , where υ=2 s  -1 and |B i  |=2 for all 0≦i≦w-1. Let 
     
         h=x.sub.0,j.sbsb.0 ·x.sub.1,j.sbsb.1 . . . x.sub.υ-1,j.sbsb.υ-1 
    
     be the unique representation of an element h ε H s  with respect to α of an element h ε H s , where x i ,j.sbsb.i, is the j i   th  element of block A i , 0≦j i  ≦1. Then the compact representation of h is the binary vector α(h)=(j 0 , j 1 , . . . , j.sub.υ-1). In this form, factoring an element h, given its compact representation α(h), becomes trivial: each bit j i  of the vector α(h) refers to the unique factor x i ,j.sbsb.i in block A i , i.e. if j i  =0 then x i ,0 is the identity permutation, whereas if j i  =1 then x i ,1 is the non-identity element of A i . When talking about the bits of a permutation h ε G we always mean the bits of α(h). 
     In general, factoring an element h ε H s  with respect to a logarithmic signature β=(B 0 , B 1 , . . . , B w-1 ) is the process of finding the factors y i ,j.sbsb.i ε B i , i=0, . . . , w-1, and 0≦j i  ≦r i  -1 in the unique representation of h as a product of the form 
     
         h=y.sub.0,j.sbsb.0 ·y.sub.1,j.sbsb.1 . . . y.sub.w-1,j.sbsb.w-1 
    
     Actually, the factoring procedure will find the factors in reverse order, i.e. first the factor y w-1 ,j.sbsb.w-1, then y w-2 ,j.sbsb.w-2, and so forth, with y 0 ,j.sbsb.0 last to be determined. 
     To simplify our description of the factorization process we adopt the notation: 
     
         h.sub.w-t =y.sub.0,j.sbsb.0 ·y.sub.1,j.sbsb.1 . . . y.sub.w-t,j.sbsb.w-t, 0&lt;t≦w 
    
     Thus, we have h=h w-1 , and 
     
         h.sub.w-t =h.sub.w-t-1 ·y.sub.w-t,j.sbsb.w-t 
    
     Given h ε H s , the factoring algorithm first finds y w-1 ,j.sbsb.w-1 ε B w-1  and computes h w-2  =h·(y w-1 ,j.sbsb.w-1) -1 . The permutation h w-2  is an element of the group G w-2  =B 0  . . . B w-2  having (B 0 , . . . , B w-2 ) as a logarithmic signature. The factoring algorithm then finds the factor y w-2 ,j.sbsb.w-2 ε B w-2  and computes h w-3  =h w-2  ·(y w-2 ,j.sbsb.w-2) -1 . Again h w-3  is an element of the group G w-3  =B 0  . . . B w-3  having (B 0 , . . . , B w-3 ) as a logarithmic signature. The factoring algorithm is then repeated to find factor y w-3 ,j.sbsb.w-3 ε B w-3  and so forth until factor y 0 ,j.sbsb.0 ε B 0  is finally found. Thus, the factoring process is iterative and completes after w-1 iterations. 
     For the sake of clarity in describing the iteration step of the factoring algorithm, some terminology needs to be introduced. 
     Suppose that γ=(C 0 , . . . C w-1 ) is an LS obtained by means of SGA. Then, there are several bit positions at which all elements of C i  have value 0. For short, we say that C i  fixes those bits at 0. Note also that blocks C 0 , C 1 , . . . , C i-1  fix the same bits at 0 as C i , plus exactly m i  more bits, where r i  =2 m .sbsp.i is the length of block C i . These m i  bits, i.e. bits fixed by C 0 , C 1 , . . . , C i-1 , but not by C i , are called the key bits of C i . It follows from the construction of γ that the 2 m .sbsp.i elements of C i  exhibit all 2 m .sbsp.i different binary patterns at the key bits. 
     Now, at each iteration step i, finding factor y i ,j.sbsb.i ε C i  proceeds as follows: 
     Let h i  be an element of the group G i  having (C 0 , . . . , C i ) as a logarithmic signature. The factoring algorithm searches for the unique element y i ,j.sbsb.i ε C i  having exactly the same bit pattern as h i  on the key bits of C i . 
     To prove the correctness of the factoring algorithm, we follow the 4 steps of SGA while generating the signature γ. 
     Commutative shuffle 
     Each operation in this step is an exchange of two neighboring commutative blocks, say A i  and A i+1 , of the canonical signature α, and thus produces a logarithmic signature α 1  =(A 0 , . . . , A i-1 , A i+1 , A i , A i+2 , . . . , A.sub.υ-1). Factoring an element h ε H s  with respect to α 1  is just the same as with respect to α, because the two factors x i ,j.sbsb.i and x i+1 ,j.sbsb.i+1 are commutative, i.e. x i ,j.sbsb.i x i+1 ,j.sbsb.i+1 =x i+1 ,j.sbsb.i+1 x i ,j.sbsb.i. 
     Any further exchange of neighboring commutative blocks of α a  gives a further logarithmic signature α 2 , for which the factorization remains the same as for α 1 . This shows that any sequence of commutative block exchanges produces a logarithmic signature, for which the factorization remains in essence the same as for α. 
     Fusion 
     The fusion of m i  neighboring blocks B M .sbsb.i, . . . , B M .sbsb.i +m .sbsb.i -1 , where M 0  =0 and M j  32 m 0  + . . . +m j-1  for j&gt;0, forms block C i . Block C i  has 2 m .sbsp.i binary vectors having all 2 m .sbsp.i possible bit patterns at bits M i , M i  +1, . . . , M i  +m i  -1, the so called key bits of C i , and all other bits are 0. 
     In order to find a factor in C i  for a permutation h with respect to a logarithmic signature containing the fused block C i , the factoring algorithm will select the unique element in C i  having the same bit pattern as h at the key bits. 
     Randomization 
     Suppose a fused signature with w blocks (C 0 , . . . , C w-1 ) is obtained after the fusion step, where C i  is the fusion of B M .sbsb.i, . . . , B M .sbsb.m +m .sbsb.i -1 , where M 0  -0, and for j&gt;0, M j  =m 0  + . . . +m j-1 . Then the type of the signature is r=(r 0 , . . . , r w- ), where r i  =2 m .sbsp.i. Each step of the randomization process effects a replacement of an element c i ,j ε C i  by an element z i ,j c i ,j, where z i ,j ε G i-1  =C 0  ·C 1  . . . C i-1  =&lt;B 0 , . . . , B m .sbsb.0 -1 , B M .sbsb.1, . . . , B M .sbsb.1 +m .sbsb.1 -1 , . . . , B M .sbsb.1-1, . . . , B M .sbsb.i-1 +m .sbsb.i-1 -1  &gt;. It follows that z i ,j contains random bits at positions {0, . . . , m 0  -1, M 1 , . . . , M 1  +m 1  -1, . . . , M i-1 , . . . , M i-1  +m i-1  -1}={0, . . . , M i-1  +m i-1  -1}={0, . . . , M i  -1}, and 0 elsewhere. On the other hand, the non-zero bits of c i ,j can occur only at key positions {M i , . . . , M i  +m i  -1}. In other words, z i ,j and c i ,j factor with respect to α as z i ,j =x 0  . . . x M .sbsb.i -1  and c i ,j =x M .sbsb.i . . . x M .sbsb.i +m .sbsb.i -1 , where x.sub.ι ε B.sub.ι. It follows that their product z i ,j ·c i ,j =x 0  . . . x M .sbsb.i -1  x M .sbsb.i . . . x M .sbsb.i +m .sbsb.i -1  can be formed by simply taking the bitwise OR of the compact representations of z i ,j and c i ,j. 
     Consequently, the compact representation of z i ,j ·c i ,j contains the same bit pattern at key bits M i , . . . , M i  +m i  -1 as c i ,j does. In other words, the key bits of C i  remain unchanged during the randomization. 
     With the same argumentation it can be seen that the compact representation of a permutation h i  =(h i-1  z i ,j)c i ,j ε G i , since (h i-1  z i ,j) ε G i-1  contains the same bit pattern at the key bits as c i   
     To recapitulate, factorization of a permutation h with respect to the randomized signature proceeds in w steps: in step i the algorithm selects the unique element y i ,j =z i ,j c i ,j ε C i  having the same bit pattern as h i  at the key bits of C i . The procedure is then repeated for h i-1  =h i  ·(z i ,j c i ,j) -1  and so on. 
     Permutation shuffle 
     Shuffling coset representatives within a block does not change the actual factors of a permutation h with respect to the signature, it only changes the assignment of indices to factors. It has therefore no impact on the selection process for finding factors within each block, except for possibly finding the appropriate elements y i ,j in a different position inside the i th  block. 
     An example of factorization 
     In this section we provide an example which demonstrates the factorization procedure for some random element of the carrier group H 3  with respect to LS ε as produced by the Signature Generation Algorithm of this Detailed Description of the invention. For easy reference logarithmic signature ε is displayed again below: 
     
         ______________________________________ε     Cartesian repr.              Compact repr.______________________________________E.sub.2     1 2 3 4 8 7 5 6                  0 0 0 1 0 1 0       4 3 2 1 5 6 7 8                  1 1 1 0 0 0 0       6 5 8 7 2 1 3 4                  1 1 0 1 0 0 1       5 6 8 7 1 2 4 3                  0 1 0 0 1 0 1       2 1 3 4 7 8 6 5                  1 0 0 0 1 1 0       8 7 5 6 4 3 1 2                  1 0 1 1 0 1 1       7 8 5 6 3 4 2 1                  0 0 1 0 1 1 1       3 4 2 1 6 5 7 8                  0 1 1 1 0 0 0E.sub.1     2 1 3 4 5 6 8 7                  1 0 0 0 1 0 0       4 3 1 2 5 6 8 7                  1 0 1 0 1 0 0       1 2 4 3 5 6 8 7                  0 1 0 0 1 0 0       3 4 2 1 5 6 7 8                  0 1 1 0 0 0 0E.sub.0     1 2 3 4 5 6 8 7                  0 0 0 0 1 0 0       1 2 3 4 5 6 7 8                  0 0 0 0 0 0 0       1 2 4 3 5 6 7 8                  0 1 0 0 0 0 0       1 2 4 3 5 6 8 7                  0 1 0 0 1 0 0______________________________________ 
    
     Consider the element x=1 1 0 0 1 0 1 which is the compact representation of permutation X=6 5 8 7 1 2 3 4 in cartesian form. The key bits for block E 2  are {4, 6, 7}, the key bits for E 1  are {1, 3} and the key bits for E 0  are {2, 5}. 
     1. The bits of x on {4, 6, 7} are 0 0 1 matching the element c=0 1 0 0 1 0 1 of block E 2 , corresponding to cartesian form C=5 6 8 7 1 2 4 3. 
     2. We now compute y=x·c -1  =1 0 0 0 0 0 0 with cartesian form Y=2 1 3 4 5 6 7 8. The bits of y on {1,3} match those of element b=1 0 0 0 1 0 0 of block E 1 , corresponding to cartesian form B=2 1 3 4 5 6 8 7. 
     3. We next compute z=x·c -1  ·b -1  =y·b -1  =0 0 0 1 1 0 1, with cartesian form Z=5 6 7 8 2 1 4 3. 
     4. The bits of z on {2,5} match those of element a=0 0 0 0 1 0 0 with cartesian form A=1 2 3 4 5 6 8 7. 
     5. This completes the factoring process for x. 
     We can now check that x=a·b·c, as well the counterpart equality of permutations in cartesian form X=A·B·C. 
     Multiplication In Compact Representation 
     In what follows we describe a series of algorithms and corresponding circuitry, the hardware implementations of those algorithms, for performing multiplication and inversion of elements of our carrier group G=H s . In particular, we introduce 3 algorithms and corresponding designs for the computation of products q=a·b, q=a -1  ·b and q=a·b -1 , as well as 2 algorithms and designs for computing the inverse q=a -1 . The algorithms and circuitry operate directly with the compact representations of the elements of H s . We presently consider only the fundamental case. The extension of the schemes to 2-groups of order other than 2 2 .spsp.s -1  will be handled at a later stage. 
     Multiplication a·b 
     As described in the previous subsections, group H s  has a recursive structure: H s  =(H s-1  ×H s- )·T s . The canonical LS α s  reflects the structure of H s  : α s  consists of a canonical LS α s-1 , of H s-1 , of another canonical LS α s-1  of H s-1  and of the last block, which is a canonical LS of T s . The compact representation with respect to α s  inherits the same kind of recursive structure. If binary vector (j 0 , . . . , j l-1 ) is the compact representation of a permutation h=(m·n)·t, where h ε H s , m ε H s-1 , n=n T .sbsp.s ε H s-1  (i.e., n ε H s-1 ) and t ε T s , then bits (j 0 , . . . , jl-1/2 -1 ) form the compact representation of m with respect to α s-1 , bits (jl-1/2, . . . , j l-2 ) form the compact representation of n with respect to α s-1  (i.e. of n wrt. α s-1 ), and finally bit j l-1  indicates factor t. 
     Now, the multiplication method takes operands α=r a  ·t a  =(m a  ·n a )·t a  and b=r b  ·t b  =(m b  ·n b )·t b  in their compact representations a=(a 0 , . . . , a l-1 ) and resp. b=(b 0 , . . . , b l-1 ). The product q=r q  ·t q  =(m q  ·n q )·t q  can be formed as follows: a·b=r a  ·t a  ·r b  ·t b  =r a  ·(t a  ·r b  ·t a   -1 )·t a  ·t b  =r a  ·r b   t .sbsp.a ·t a  ·t b . Since r b  ε (H s-1  ×H s-1 )∇ H s , the conjugate r b   t .sbsp.a lies also in (H s-1  ×H s-1 ). Therefore it is readily shown that t q  =t a  ·t b  and r q  =r a  ·r b   t .sbsp.a. 
     In the following we first consider how to compute t q , and then we show how to compute r q . Since t a , t b  ε T s  ≅ 2 , and t a  and t b  are indicated solely by bits a l-1  and b l-1  respectively, the multiplication in T s  can be effected by an elementary binary exclusive-OR (⊕) operation: q l-1  =a l-1  ⊕ b l-1 . 
     The &#34;normal&#34; part r q  =r a  ·r b   t .sbsp.a will be computed in two steps: 
     Step 1. the conjugate r&#39; b  =r b   t .sbsp.a is formed, and then 
     Step 2. the multiplication r a  r&#39; b  is performed. 
     Step 1. Conjugation of r b  =m b  ·n b  ε (H s-1  ×H s-1 ) by t a  ε T s  involves two cases: 
     --if t a  =ι then trivially m&#39; b  =m b  and n&#39; b  =n b  (i.e. n&#39; b  =n b ); 
     --if, on the other hand, t a  =τ s  then, since τ s  transforms elements of H s-1  to corresponding elements of H s-1 , and vice versa, m&#39; b  =n b .sup.τ.sbsp.s =n b  and n&#39; b  =m b .sup.τ.sbsp.s (i.e. n b  =m&#39; b ). 
     When representing operands in compact form, conjugating r b  by ι (induced by a l-1  =0) does not change r b , whereas conjugating by τ s  (induced by a l-1  =1) can be implemented as a swap of the subsequences (b 0 , . . . , bl-1/2 -1 ) and (bl-1/2, . . . , b l-2 ), corresponding to m b  and respectively to n b , within the compact representation of b. 
     Step 2. Next, r a  =m a  ·n a  is multiplied by the the conjugate r&#39; b  =m&#39; b  ·n&#39; b . Multiplication can be effected &#34;component-wise&#34; in the direct product group (H s-1  ×H s-1 ), i.e. r a  ·r&#39; b  =m a  ·n a  ·m&#39; b  ·n&#39; b  =(m a  ·m&#39; b )·(n a  ·n&#39; b ). Components of the product r q  =m q  ·n q  are therefore computed separately and independently: m q  =m a  ·m&#39; b  and n q  =n a  ·n&#39; b . From n q  =n a  ·n&#39; b  follows that n q  =n a  ·n b , showing that the latter multiplication can also be performed in H s-1 . 
     So far, it has been shown that the product q is obtained from the compact representation of input operand a and b applying a single XOR-operation, a conditional swapping operation and, recursively two independent calls of the algorithm forming products in H s-1 , and thus of reduced complexity s-1. In what follows we describe a hardware multiplier that implements this method at very high speeds. 
     Swapping Module 
     We first describe a swapping module SW(M) with scaling parameter M which has two input vectors (X[0], . . . , X[M-1]), (Y[0], . . . , Y[M-1]), and two output vectors (V[0], . . . , V[M-1]), (W[0], . . . , W[M-1]), as well as a control input bit Z. If control signal Z is set to 0, each X[i] is directly connected to V[i], and each Y[i] is connected to W[i], whereas if Z=1, then each X[i] is connected to W[i], and each Y[i] is connected to V[i], for 0≦i≦M-1. This circuit is used throughout, in the hardware implementation of the various permutation multipliers and inverters. 
     Multiplier circuit for a·b 
     We present a recursive description of the multiplier which computes Q=A·B. Let MULAB(N) denote such a multiplier of strength s with two input vectors A, B, and one output vector Q, each of length N=l=2 s  -1. The architecture of the multiplier is depicted in FIG. 6. 
     The inputs to MULAB(N) are binary vectors (A[0], A[1], . . . , A[N-1]) and (B[0], B[1], . . . , B[N-1]). Bits B[0], . . . , B[(N-3)/2] are connected to the X-bus, while bits B[(N-1)/2], . . . , B[N-2] to the Y-bus of a swapping module SW of type SW((N-1)/2). Bit A[N-1] is connected to the control input bit Z of SW. Moreover, bits A[N-1] and B[N-1] are XOR&#39;ed and the result is output as bit Q[N-1]. 
     The V-bus of SW is connected to the B-bus of a lower multiplier LMUL, and the W-bus of SW is connected to the B-bus of an upper multiplier UMUL. Moreover, bits A[0], . . . , A[(N-3)/2] are connected to the A-bus of LMUL, while bits A[(N-1)/2], . . . , A[N-2] are connected to the A-bus of UMUL. Both LMUL and UMUL are of type MULAB((N-1)/2) and perform multiplication of the form Q=A·B. 
     The Q-bus of LMUL forms output bits Q[0], . . . , Q[(N-3)/2], and the Q-bus of UMUL forms output bits Q[(N-1)/2], . . . , Q[N-2]. 
     Due to the recursive structure apparent in the design, the multiplier can be scaled easily for any length N=l=2 s  -1. The depth of the circuitry is proportional to log 2  (N+1)=s, promising a very high speed at reasonably low costs. For illustration, a concrete realization for strength s=4 and input/output length N=l=15 is displayed with a flattened hierarchy in FIG. 7. 
     Multiplication a -1  ·b 
     A simple derivation yields: q=a -1  ·b=(r a  ·t a ) -1  ·(r b  ·t b )=t a   -1  ·r a   -1  ·r b  ·t b  =(r a   -1  ·r b ) t .sbsp.a ·t a  ·t b . Since (r a   -1  ·r b ) t .sbsp.a ε (H s-1  ×H s-1 ), it is readily seen that t q  =t a  ·t b  and r q  =(r a   -1  ·r b ) t .sbsp.a. 
     Computing t q  requires a single binary XOR-operation in  2 . The &#34;normal&#34; part r q  is computed in two steps. At first, the product r&#39; q  =r a   -1  r b  is computed, and then the conjugation (r&#39; q ) t .sbsp.a is performed. Since multiplication and inversion can be performed component-wise in the direct product group (H s-1  ×H s-1 ), the product r&#39; q  has components m&#39; q  =m a   -1  ·m b  and n&#39; q  =n a   -1  ·n b . From n&#39; q  =n a   -1  ·n b  follows n&#39; q  =n a   -1  ·n b , showing that the latter multiplication can be performed in H s-1 . Conjugation of r&#39; q  falls into two cases: 
     if t a  =ι then trivially m q  =m&#39; q  an n q  =n&#39; q  ; 
     if t a  τ s  then m q  =n&#39; q  and n q  =m&#39; q . 
     When the operands are represented in compact form, the multiplication requires a single binary XOR-operation, two multiplications of type a -1  ·b of reduced complexity (strength), as a recursive step, and finally a conditional swapping operation. The corresponding hardware multiplier MULAIB(N) of strength s, with two input vectors A, B, and one output vector Q, each of length N=l=2 s  -1, is shown in FIG. 8. 
     Multiplier circuit for a -1  ·b 
     The inputs to MULAIB(N) are binary vectors (A[0], A[1], . . . , A[N-1]) and (B[0], B[1], . . . , B[N-1]). Bits A[0], . . . , A[(N-3)/2] are connected to the A-bus of a lower multiplier LMUL, while bits A[(N-1)/2], . . . , A[N-2] are connected to the A-bus of an upper multiplier UMUL. Moreover, bits B[0], . . . , B[(N-3)/2] are connected to the B-bus of LMUL, while bits B[(N-1)/2], . . . , B[N-2] are connected to the B-bus of UMUL. Both LMUL and UMUL are of type MULAIB((N-1)/2). 
     Bits A[N-1] and B[N-1] are XOR&#39;ed and the result is output as bit Q[N-1]. The Q-bus of LMUL is connected to the X-bus, while the Q-bus of UMUL is connected to the Y-bus of a swapping module SW of type SW((N-1)/2). Bit A[N-1] is connected to the control input bit Z of SW. 
     The V-bus of SW forms output bits Q[0], . . . , Q[(N-3)/2], and the W-bus of SW forms output bits Q[(N-1)/2], . . . , Q[N-2]. 
     Multiplication a·b -1   
     A simple derivation yields : q=a·b -1  =(r a  ·t a )·(r b  ·t b ) -1  =r a  ·t a  ·t b   -1  ·r b   -1  =r a  ·(t a  ·t b )·r b   -1  =r a  ·(r b   -1 ).sup.(t.sbsp.a.sup.·t.sbsp.b.sup.) ·(t a  ·t b )=r a  ·(r b .sup.(t.sbsp.a.sup.·t.sbsp.b.sup.)) -1  ·(t a  ·t b ). Since r a  ·(r b .sup.(t.sbsp.a.sup.·t.sbsp.b.sup.)) -1  ε (H s-1  ×H s-1 ) it is readily seen that t q  =t a  ·t b  and r q  =r a  ·(r b .sup.(t.sbsp.a.sup.·t.sbsp.b.sup.)) -1 . 
     Computing t q  requires a single binary XOR-operation in  2 . The &#34;normal&#34; part r q  is computed in two steps. As a first step, the conjugation r&#39; b  =r b .sup.(t.sbsp.a.sup.·t.sbsp.b.sup.) is carried out, and then the product r q  =r a  ·(r&#39; b ) -1  is computed. Conjugating r b  by t a  ·t b  falls into two cases: 
     if t a  ·t b  =ι then trivially m&#39; b  =m b  and n&#39; b  =n b  ; 
     if t a  ·t b  =τ s  then m&#39; b  =n b  and n&#39; b  =m b . 
     Since multiplication and inversion can be performed component-wise in the direct product group (H s-1  ×H s-1 ), the product r q  has components m q  =m a  ·(m&#39; b ) -1  and n q  =n a  ·(n&#39; b ) -1 . From n q  =n a  ·(n&#39; b ) -1  follows that n q  =n a  ·(n&#39; b ) -1 , showing that the latter multiplication can be performed in H s-1 . 
     When operands are represented in compact form, the multiplication requires a single binary XOR-operation, a conditional swapping operation and finally two multiplications of type a·b -1  and of reduced complexity (strength), as a recursive step. The corresponding hardware multiplier MULABI(N) of strength s, with two input vectors A, B, and one output vector Q, each of length N=l=2 s  -1, is shown in FIG. 9. 
     Multiplier circuit for a·b -1   
     The inputs to MULABI(N) are binary vectors (A[0], A[1], . . . , A[N-1]) and (B[0], B[1], . . . , B[N-1]). Bits B[0], . . . , B[(N-3)/2] are connected to the X-bus, while bits B[(N-1)/2], . . . , B[N-2] to the Y-bus of a swapping module SW of type SW((N-1)/2). 
     Moreover, bits A[N-1] and B[N-1] are XOR&#39;ed and the result is, on one hand, output as bit Q[N-1], and is further connected to the control input bit Z of SW. The V-bus of SW is connected to the B-bus of a lower multiplier LMUL, and the W-bus of SW is connected to the B-bus of an upper multiplier UMUL. Moreover, bits A[0], A[(N-3)/2] are connected to the A-bus of LMUL, while bits A[(N-1)/2], . . . , A[N-2] are connected to the A-bus of UMUL. Both LMUL and UMUL are of type MULABI((N-1)/2). The Q-bus of LMUL forms output bits Q[0], . . . , Q[(N-3)/2], and the Q-bus of UMUL forms output bits Q[(N-1)/2], . . . , Q[N-2]. 
     Inversion 
     In this subsection we present two algorithms and corresponding designs that compute q=a -1 . In the derivations, we continue to use the previously used notation. 
     A simple derivation yields : q=a -1  =(r a  ·t a ) -1  =t a   -1  ·r a   -1  =(t a   -1  ·r a   -1  ·t a )·t a   -1  =(r a   -1 ) t .sbsp.a ·t a . Since (r a   -1 ) t .sbsp.a ε (H s-1  ×H s-1 ), it is readily seen that t q  =t a  and r q  =(r a   -1 ) t .sbsp.a. 
     The &#34;normal&#34; part r q  is computed in two steps. Initially, the inverse r&#39; a  =r a   -1  is computed, and then the conjugation (r&#39; a ) t .sbsp.a is performed. The inverse r&#39; a  =r a   -1  =(m a  ·n a ) -1  can be obtained component-wise in the direct product group (H s-1  ×H s-1 ), therefore m&#39; a  =m a   -1  and n&#39; a  =n a   -1 . From nn&#39;hd a=n a   -1  follows that n&#39; a  =n a   -1  showing that the latter inversion can be performed in H s-1 . Conjugation of r&#39; a  falls into two cases: 
     if t a  =κ then trivially m q  =m&#39; a  and n q  =n&#39; a  ; 
     if t a  =r s  then m q  =n&#39; a  and n q  =m&#39; a . 
     When a is represented in compact form, inversion requires a conditional swapping operation and, as a recursive step, two inversions of reduced complexity (strength). The corresponding hardware inverter INV(N) of strength s, with an input vector A and an output vector Q, each of length N=l=2 s  -1, is shown in FIG. 10. 
     Inversion Circuit 
     Input to INV(N) is the binary vector (A[0], A[1], . . . , A[N-1]). Bits A[0], . . . , A[(N-3)/2] are connected to the A-bus of a lower inverter LINV, while bits A[(N-1)/2], . . . , A[N-2] to the A-bus of an upper inverter UINV. Both LINV and UINV are of type INV((N-1)/2). Moreover, bit A[N-1] is, on one hand, output as bit Q[N-1], and is also connected to the control input bit Z of a swapping module SW of type SW((N-1)/2). 
     The Q-bus of LINV is connected the X-bus, and the Q-bus of UINV is connected to the Y-bus of SW. 
     The V-bus lines of SW form output bits Q[0], . . . , Q[(N-3)/2], and the W-bus lines of SW form output bits Q[(N-1)/2], . . . , Q[N-2]. 
     Note that since r q  =(r a   -1 ) t .sbsp.a =(m a   -1  ·n a   -1 ) t .sbsp.a =(m a   -1 ) t .sbsp.a ·(n a   -1 ) t .sbsp.a =(m a   t .sbsp.a) -1  ·(n a   t .sbsp.a) -1  =(m a   t .sbsp.a ·n a   t .sbsp.a) -1  =(r a   t .sbsp.a) -1 , it is possible to reverse the order of inversion and conjugation, that yields another variant of inversion algorithms. The corresponding hardware inverter INV(N) is shown in FIG. 11. 
     The input to INV(N) is binary vector (A[0], A[1], . . . , A[N-1]). Bits A[0], . . . , A[(N-3)/2] are connected to the X-bus, while bits A[(N-1)/2], . . . , A[N-2] to the Y-bus of a swapping module SW of type SW((N-1)/2). Moreover, bit A[N-1] is, on one hand, output as bit Q[N-1], and second, is connected to the control input bit Z of SW. 
     The V-bus of SW is connected to the A-bus of a lower inverter LINV, and the W-bus of SW is connected to the A-bus of an upper inverter UINV. Both LINV and UINV are of type INV((N-1)/2). 
     The Q-bus of LINV forms output bits Q[0], . . . , Q[(N-3)/2], and the Q-bus of UINV forms output bits Q[(N-1)/2], . . . , Q[N-2]. 
     Description Of The New Secret Key Cryptosystem 
     Our new cryptosystem has a distinguishing feature, scalability, which differentiates it from presently known, secret-key encryption systems, such as DES, FEAL, IDEA etc. For these widely used systems, input and output blocks have a predetermined fixed length, which cannot be modified. Our system&#39;s scalability allows it to be adopted to any i/o length l, while using the same algorithms for the various operations. Consequently, the new system covers a whole class of cryptosystems of arbitrary block lengths. This particular feature makes the new cryptosystem suitable for applications in standard as well as non conventional IT systems. 
     In summary, the components we described earlier are: 
     the compact representation of permutations 
     the signature generation algorithm SGA 
     the method of factorization of permutations with respect to any signature generated by SGA 
     the permutation multiplier and inverter circuits 
     The new cryptosystem can be efficiently implemented on a chip with a simple and homogeneous structure using these components. So far we have only described methods and circuits for the fundamental case, i.e. for the case where the carrier group is isomorphic to the Sylow 2-subgroup of a symmetric group of degree 2 s . Accordingly, we will describe the new encryption system for the fundamental case. A generalization of the methods to 2-groups of arbitrary order will be described in a separated section. 
     The setup for the encryption system is as follows: 
     The cleartext space M and the ciphertext space C are the set of all binary vectors of length l, i.e. M=C={0,1} l . 
     The secret key K is a pair of logarithmic signatures β 1  and β 2  generated by SGA using a sequence of pseudorandom numbers x 0 , x 1 , . . . , x k , . . . , where x i  ε M. The sequence is generated by an internal random number generator seeded by means of the user password. The internal random number generator is itself based on a particular instance of the cryptosystem. 
     Let R: {0,1} l  →{0,1} l  denote the bit order reversing mapping defined by 
     
         R(y.sub.0, y.sub.1, . . . , y.sub.l-1)=(y.sub.l-1, y.sub.l-2, . . . , y.sub.0), 
    
     i.e. R reverses the order of the input sequence bits. 
     The encryption/decryption functions of the system are described as follows. 
     ENCRYPTION: 
     Encrypting a cleartext m ε M, using a key K=(β 1 ,β 2 ), is defined by 
     
         c=E.sub.K (m)=[α.sup.-1 β.sub.1 Rβ.sub.2.sup.-1 α](m). 
    
     DECRYPTION: 
     Decrypting ciphertext c ε C is carried out by the inverse mapping D K  of E K  : 
     
         m=D.sub.K (c)=[α.sup.-1 β.sub. Rβ.sub.1.sup.-1 α](c). 
    
     Note that the decryption works algorithmically in the same way as the encryption, with reversed roles for β 1  and β 2 . 
     Because of the compact representation and the special form of the multiplier circuits, which work directly with permutations in compact form, the expressions of the form α(.) and α -1  (.) are always implicit, automatic, and never need to be separately computed. To clarify the functionality of the mappings used in the encryption/decryption algorithm we explain in words the encryption process: 
     The binary input vector m is viewed as the compact representation of a permutation h=α -1  (m). The permutation h is then factorized with respect to signature β 1 . 
     
         h=x.sub.0,υ.sbsb.0 ·x.sub.1,υ.sbsb.1 . . . x.sub.w.sbsb.1 -1,υ.sub.w.sbsb.1.sub.-1, 
    
     where x i ,υi is the unique factor of h in the i th  block of β 1 . The result of this step is a binary vector y=β 1  (h)=υ 0  ||υ 1  || . . . ||υ w .sbsb.1 -1 , obtained by catenating the binary bits of the w 1  numbers υ i , The bits of y are then reversed by the mapping R to produce an intermediate binary vector R(y). Next, the bits of R(y) are separated into successive segments u i  of length m i , 0≦i≦w 2  -1 where r=(r 0 , r 1 , . . . , r w .sbsb.2 -1 ) is the type of signature β 2 , and r i  =2 m .sbsp.i. The integer u i  is then used as a pointer index in the composition process with respect to β 2 . The result is a permutation 
     
         h&#39;=y.sub.0,u.sbsb.0 ·y.sub.1,u.sbsb.1 . . . y.sub.w.sbsb.2 -1,u.sub.w.sbsb.2.sub.-1, 
    
     whose compact representation is the output of the encryption process. 
     It is worth mentioning that our system differs from other known secret key systems such DES, FEAL, or IDEA, in the following way. In the known systems, a key is a certain binary sequence of small length, for example 56, 64, or 128 bits, used as a parameter for an independent encryption function, whereas in our system, the key is a pair of logarithmic signatures which embody the encryption function itself. Thus, the memory required for storing logarithmic signatures in essence corresponds to the memory for implementing encryption functions in the known cryptosystems. 
     Generalization Of The System To Arbitrary Input Length l 
     So far we have described the new system for the fundamental case, where the carrier group G is the Sylow 2-subgroup H s  of the symmetric group of degree 2 s . In this case the order of G is 2 2 .spsp.s -1  and therefore the i/o length l=2 s  -1 of the system is always a power of 2 minus 1. As an illustration the following table shows the i/o lengths l for different strengths s in the case G=H s . 
     
         ______________________________________s:   1     2       3   4      5   6     7    8     . . .l:   1     3       7   15    31  63    127  255    . . .______________________________________ 
    
     To overcome the above limitation on l, we present a method for generalizing the system to groups of order 2 l , where l is an arbitrary natural number. This results in a system that is freely scalable to arbitrary i/o lengths l. In particular, most communication and computer systems require a block length that is a power of two. For the generalized case, just as for the fundamental case, we discuss the following aspects: 
     Choice of group G, 
     Compact representation of elements of G, 
     Signature generation algorithm, 
     Factorization algorithm, 
     Permutation multipliers/inverters, 
     System description. 
     Choice of group G 
     Given an arbitrary i/o length l, the generalized system will rely on a group G l  of order 2 l . For each l there is at least one possible choice for a group G l  and as l grows, so does the number of non-isomorphic choices for G l . The 2-group G l  is always a subgroup of some larger (fundamental case) H s , i.e. G l  ≦H s . Clearly, if G l  ≦H s , then G l  &lt;H t  for all t&gt;s, and thus there are many possible embeddings of G l  in an H s . In what follows, we describe a method for constructing possible groups G l . In parallel to the construction of G l , the method constructs a particular, small, but not necessarily the theoretically smallest possible H s  in which G l  is embeddable. We will call this H s  obtainable from our algorithm, the supergroup of G l . 
     As already described, the Sylow 2-subgroup H s  used in the fundamental system has a recursive structure: 
     H 1  =T 1  and 
     H s  =(H s-1  ×H s-1 )·T s  for s&gt;1. 
     The recursive composition rules of a G l  ≦H s  are similar. The algorithm below offers alternatives at different steps of the construction, where different choices lead to different carrier groups: 
     G 1  =T 1  and 
     G k  for k&gt;1 is choosably 
     1. Either the wreath product G k  =G 2e+1  =(G e  ×G e )·T e&#39;+1 , in which case: 
     G e  is a 2-group generated by this algorithm, and 
     H e&#39;   is the supergroup of G e . 
     Then G e  =G e   T .sbsp.e&#39;+1, and the supergroup of G k  is H e&#39;+1 . 
     2. or the direct product G k  =G e  ×G f , in which case: 
     G e  and G f  are two, possibly different 2-groups, generated by this algorithm, having the same degree and satisfying k=e+f, and 
     H e&#39;  =H f&#39;   is the supergroup of both G e  and G f . 
     Then G f  =G f   T .sbsp.e&#39;+1, and the supergroup of G k  H e&#39;+1 . 
     3. or the extension G k  =G* 2  of G e , in which case: 
     G e  is a 2-group generated by this algorithm, and of degree 2 e&#39; , and 
     H e&#39;   is the supergroup of G e . 
     The extension is defined as follows: if G e  acts on symbol set X e  ={1, . . . , 2 e&#39;  } then the extension G* e  of G e  acts on X* e  ={1, . . . , 2 e&#39;+1  }, |G* e  |=|G e  |, and each permutation p=(p(1), . . . , p(2 e&#39; )) ε G e  corresponds to a permutation p*=(p(1), . . . , p(e&#39;),e&#39;+1, . . . , 2e&#39;) ε G* e . 
     Then the supergroup of G k  =G* e  is H e&#39;+1 . 
     Note that any of the alternative steps constructs a subgroup G k  of H e&#39;+1 . As a result, carrier group G l  is a subgroup of some H s , independent of the options taken at particular steps. In particular, if alternative 1. is always taken, then the algorithm generates H s  itself, otherwise it generates some proper subgroup of H s . In general, G l  may also be seen as a subgroup of H s  obtained by removing some atomic subgroups T a  from H s . In particular: 
     when choosing alternative 2. in the composition of G k , then the atomic subgroup T e&#39;+1  is omitted from the supergroup H e&#39;+1 . 
     when choosing alternative 3. in the composition of G k , then the atomic subgroup T e&#39;+1  and all atomic subgroups of H e&#39;   are omitted from H e&#39;+1   
     Compact Representation 
     Since G l  ≦H s , elements of G l  can be represented in compact form with respect to the canonical LS α Hs  of H s . However, since G l  misses some atomic subgroups T a  of H s , the corresponding factors x a ,j.sbsb.0 ε T a  will all be the identity ι in the factorization h=x 0 ,j.sbsb.0 . . . x 2  s -2 ,j.sbsb.2 s .sbsb.-2 for the elements h ε G l  with respect to α H .sbsb.s. Accordingly, all bits j a  will be zeros in the representation with respect to α H .sbsb.s. This observation leads to two different, but equivalent definitions of the compact representation in G l  : 
     On one hand, there is clearly no need to store bits b a  =0 in the representation of h with respect to α H .sbsb.s. By omitting the superfluous bits, a non-redundant representation, the compact representation of elements h ε G l  is obtained. 
     On the other hand, blocks B a , contributing only with ι in the factorization of any element h ε G l , may themselves be removed from α H .sbsb.s without failing to generate the entire carrier group G l . The signature α G .sbsb.l, obtained by removing blocks B a  from α H .sbsb.s is called the canonical logarithmic signature of G l , and the representation of elements h ε G l  wrt. α G .sbsb.l is called the compact representation in G l . 
     An illustrative example for a group G 8  =G 5  ×G* 3  =(((T 0  ×T 1 )×(T 2  ×T 3 ))·T 4 )×((T 5  ×T 6 )·T 7 )* is listed below: 
     
         ______________________________________B.sub.7     1 2 3 4 5 6 7 8 11 12  9 10 13 14 15 16       1 2 3 4 5 6 7 8  9 10 11 12 13 14 15 16B.sub.6     1 2 3 4 5 6 7 8  9 10 12 11 13 14 15 16       1 2 3 4 5 6 7 8  9 10 11 12 13 14 15 16B.sub.5     1 2 3 4 5 6 7 8 10  9 11 12 13 14 15 16       1 2 3 4 5 6 7 8  9 10 11 12 13 14 15 16B.sub.4     5 6 7 8 1 2 3 4  9 10 11 12 13 14 15 16       1 2 3 4 5 6 7 8  9 10 11 12 13 14 15 16B.sub.3     1 2 3 4 5 6 8 7  9 10 11 12 13 14 15 16       1 2 3 4 5 6 7 8  9 10 11 12 13 14 15 16B.sub.2     1 2 3 4 6 5 7 8  9 10 11 12 13 14 15 16       1 2 3 4 5 6 7 8  9 10 11 12 13 14 15 16B.sub.1     1 2 4 3 5 6 7 8  9 10 11 12 13 14 15 16       1 2 3 4 5 6 7 8  9 10 11 12 13 14 15 16B.sub.0     2 1 3 4 5 6 7 8  9 10 11 12 13 14 15 16       1 2 3 4 5 6 7 8  9 10 11 12 13 14 15 16______________________________________ 
    
     Note that B 0 , . . . , B 4  form a canonical LS for G 5  and blocks B 5 , . . . , B 7  for G* 3 . Note also that G 3  acts on {9, . . . , 12}, whereas its extension G* 3  on {9, . . . , 16}. Furthermore, H 3  is the supergroups of G 5 , H 3  is that of G* 3 , and H 4  is that of G 8 . 
     Signature Generation Algorithm 
     In the fundamental version of the system, the signature generation algorithm starts out from the canonical LS α H .sbsb.s, and relies only on such properties of α H .sbsb.s that are inherited by canonical LS α G .sbsb.l too. Therefore the signature generation algorithm in the generalized version is just the same as in the fundamental case. 
     Factorization Algorithm 
     In the fundamental version of the system, the factorization algorithm utilizes only such properties of the compact representation and of the employed LSs that are present in the generalized representation and LS too. Therefore the factorization algorithm remains the same in the generalized version too. 
     Permutation Multipliers/Inverters 
     Since G l  ≦H s , the multipliers and inverters used to compute in H s  can also be employed to compute in G l . The multipliers and inverters need to be provided with operands in the representation with respect to αH.sub..sbsb.s, that can be obtained from the representation with respect to α G .sbsb.l by inserting zero bits for all blocks B a  removed from α H .sbsb.s. In a practical implementation, however, the multiplier and inverter designs should be optimized by removing inputs that hold the inserted zeros and by simplifying the logic driven by those inputs. Such an optimization results in multipliers and inverters that work directly with the compact representation of the carrier group G l . The optimization is straightforward and can be performed automatically by most CAE tools, therefore is not further discussed here. 
     System Description 
     Finally, since all components (representation, signature generation, factorization, multipliers) remain essentially the same, the generalized cryptosystem employs the same algorithm as used in the fundamental version. 
     Pseudorandom Number Generators from the New System 
     For cryptographic applications, the new system may be used as a means for producing pseudorandom numbers. Among several techniques of using block ciphers to build pseudorandom number generators we intend to use TST in the following two methods: Cyclic Encryption Generator and ANSI X9.17 Pseudorandom Number Generator. 
     Cyclic Encryption Generator (CEG) 
     The CEG is based on said cryptosystem with i/o length l. From an initial binary vector IV=(υ 1 , . . . , υ l ) used as seed, CEG produces a sequence of 2 l  distinct binary vectors z 1 , z 2 , . . . , z 2 .spsb.l each of length l. Thus, the pseudorandom number generator has a full period. The CEG is described as follows: Let E K  be the encryption function of the new system, i.e. encryption using a key K. Let x 0  =IV=(υ 1 , . . . , υ l ) be a random initial vector, for each i=1, 2, . . . , 2 l , output z i  is computed by 
     
         z.sub.i =E.sub.K (x.sub.i), 
    
     where x i  =x i-1  +1, 1=(0, . . . , 0, 1) and + is ordinary addition of integers when x i  is viewed as an integer in its binary representation. 
     ANSI X9.17 Pseudorandom Number Generator (ANSI X9.17) 
     The ANSI X9.17 is known to be one of the strongest pseudorandom number generators, which is proposed for use with block ciphers. Again, let E K  be the TST encryption function using key K. Two inputs of length l drive ANSI X9.17: One is an l-bit representation of the current date and time and is updated each time the generator is used. The other is an f-bit seed value, which is initialized to some random value and is updated during the generation process. The output of ANSI X9.17 consists of an f-bit pseudorandom number and an l-bit seed value. 
     ANSI X.9.17 works as follows: 
     Let: 
     DT i  be the date and time value at the beginning of the i th  generation stage, 
     S i  the seed value at the beginning of the i th  generation stage, 
     R i  the pseudorandom number output of the i th  generation stage, 
     Then, 
     
         R.sub.i =E.sub.K (E.sub.K (DT.sub.i) ⊕ S.sub.i) 
    
     
         S.sub.i+1 =E.sub.K (E.sub.K (DT.sub.i) ⊕ R.sub.i) 
    
     Having hereby disclosed the subject matter of this invention, it should be obvious that many modifications, substitutions, and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that the invention may be practised other than as specifically described, and should be limited in breadth and scope only by the appended claims.