Abstract:
The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     The present application claims the benefit of priority from pending U.S. Provisional Patent Application No. 60/605,458, entitled “Enhancing Timing Margin Memory Interface”, filed on Aug. 17, 2004, which is herein incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to the field of digital memory modules and more specifically it relates to means for transmitting data and control signals onto individual lines in the memory interface buss.  
         [0004]     2. Background Art  
         [0005]     Digital memory modules such as used in computers, printers, and telecommunications equipment are clocked devices that must communicate data, control, and status signals onto a memory buss. The signals are digital signals that are typically switched synchronously with the memory clock. Following a clocked transition, signals require a period of time to stabilize and allow switching transients to die off before their signal state can be considered “valid”. The time difference between the time of signal stabilization and the start of the subsequent clocked transitioning minus the time required by the system to receive the valid information comprises the timing margin of the memory.  
         [0006]     Historically, timing margin (as well as power consumption) has not represented a major problem with memory modules. When more than one signal was to be coupled onto a single line in the memory buss, memory buss driver outputs were connected together as the simplest and lowest cost method for driving the memory buss, because timing margin was not a concern. An example prior art configuration is illustrated in  FIG. 1 . Signals A and B are coupled to node  100  through buffers U 100  and U 101  respectively. The output of node  100  is strobed for A or B as desired.  
         [0007]     With the increasing need for higher speed memory, timing margin can no longer be ignored. The combined transition and stabilization time now represents a significant portion of, if not the entire, clock period. Since transition times and time delays are subject to manufacturing variability, timing margin has become both small and widely variable. This makes for low yield production and very costly memory modules.  
         [0008]     In addition to the timing margin problem, the trend has been toward larger and larger capacity memory modules. The transition period with associated high current draw has resulted in a major power consumption/distribution problem for state of the art memory modules. One of the major sources for high power consumption is the use of simple wired-OR connections of multiple line driver outputs driving the memory buss. During transitions, both upper and lower type switching devices within the line drivers attached to an individual line in the buss can be “on” or partially “on”. This results in high transient current flow and resulting high power dissipation. At high memory clock rates, this represents a high “duty cycle” that will only become worse with increasing memory clock rates in the future. For large memory modules, there are such a large number of the transitions occurring at a typical clocked transition that the total power consumption is large and difficult to deal with given conventional memory module to motherboard interfacing.  
         [0009]     As a result, it would be extremely desirable to have digital memory to memory buss interface circuitry that would provide adequate timing margin for memory modules at higher clock frequencies while reducing the total power consumption associated with the present buss interface.  
       SUMMARY OF THE INVENTION  
       [0010]     The present invention is an active, electronic circuit that is used within a digital memory circuit and comprises a number of features. One feature is the use of a single line driver per memory bus line instead of the wired-OR line drivers used in the present art. Another feature is the use of one or more logic gates to perform signal combining or signal selection functions and thereby avoid the need for the multiple, wired-OR line drivers used in the present art. Another feature comprises the use of timing margin enhancement circuits that independently adjust the rise and fall time of the digital signal transitions for each signal that would be applied to and drive the memory bus line through its separate line driver in the present art. The timing margin enhancement circuits are applied to both memory data and control/status signals.  
         [0011]     In one or more embodiments, the present invention includes an OR gate for signal selection. In one or more embodiments, the timing margin enhancement circuits are implemented using multiple transistors in a totem-pole configuration. In one or more embodiments, the timing margin enhancement circuits are implemented using single transistors. In one or more embodiments, the timing margin enhancement circuits are implemented using Field Effect Transistors (FETs). In one or more embodiments, the timing margin enhancement circuits are implemented using bipolar transistors.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a circuit diagram illustrating wired-OR line driver output interconnection typically used to drive memory data and control bus lines on digital memory modules.  
         [0013]      FIG. 2  is a block diagram illustrating means for driving data and control bus lines on digital memory modules utilizing the enhanced timing margin and reduced power dissipating configuration of the present invention.  
         [0014]      FIG. 3  is a circuit diagram of the preferred embodiment of the asymmetric rise and fall time generating circuit of the present invention.  
         [0015]      FIG. 4  is a circuit diagram of an alternate embodiment of the asymmetric rise and fall time generating circuit of the present invention.  
         [0016]      FIG. 5  is a circuit diagram of another alternate embodiment of the asymmetric rise and fall time generating circuit of the present invention.  
         [0017]      FIG. 6  is a circuit diagram of an alternate embodiment of the asymmetric rise and fall time generating circuit of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     The present invention is directed to circuitry for use in a memory module. In the following description, numerous specific details are set forth to provide a more thorough description of embodiments of the invention. It is apparent, however, to one skilled in the art, that the invention may be practiced without these specific details. In other instances, well known features have not been described in detail so as not to obscure the invention. Except as noted herein, common components and connections, identified by common reference designators function in like manner in each circuit.  
         [0019]     The present invention is illustrated in  FIG. 2  and comprises a single line driver for the memory buss line being driven, one or more combinational logic gates for selecting or combining logic signals to be communicated over the memory buss line, and a transition time adjustment circuit for each signal that would other be wired-OR through its line driver buss interface in the present art. Strobe A is a transition time adjust circuit coupled to memory logic for input A. Strobe B is a transition time adjust circuit for input B. The outputs of these circuits are coupled as inputs t OR gate  200 . The output of OR gate  200  is coupled through buffer  201 .  
         [0000]     Line Driver  
         [0020]     The present invention implements a single line driver for each line in the memory buss thereby eliminating the noise and distortion produced at the clock transitions. Where multiple memory modules are connected in parallel to the memory buss, the invention can be applied by putting comparable signals from each memory module through an OR-gate whose output is coupled to the single line driver which drivers the appropriate line in the memory buss. The OR-gate could be located off the memory module thus affecting system architecture. The present invention would nevertheless reduce the number of wired-OR line drivers by half.  
         [0000]     Logic Gates  
         [0021]     The combinational logic used in the present invention typically comprises a single, 2-input OR-gate. Additional inputs can be added for custom memory configurations where more than two signals and line driver outputs would be connected in the wired-OR configuration of the present art.  
         [0000]     Transition Time Adjustment Circuit  
         [0022]     This circuit provides the capability to adjust circuit timing by providing independent rise and fall time adjustment capability. This can be used to set up conditions in anticipation of a transition, adjust the timing margin by allowing one signal to transition quickly while the other is slowed, and by avoiding the situation where both transitioning signals are simultaneously in regions of high noise susceptibility.  
         [0000]     Example Embodiment of Transition Time Adjustment Circuit  
         [0023]     An example embodiment is shown in  FIG. 3 . Resistors R 300  and R 301  represent the series resistance of the FET and package. Resistors R 302  and R 303  are selectable to set the RC time constant in conjunction with C 300  that produce the desired (asymmetric rise and fall time). The input from memory logic is coupled to node N 300 . Node N 300  is coupled to transistors Q 300  (coupled to Voltage V 300 ) and Q 301  (coupled to ground). The output of transistor Q 300  is coupled through resistor R 300  to node N 301 . The output of transistor Q 301  is coupled to node N 302  through resistor R 301 . Nodes N 301  and N 302  are coupled to Node N 303  through resistors R 302  and R 303  respectively. Node N 303  is coupled through capacitor C 300  to ground and to logic U 200 .  
         [0024]      FIG. 4  shows an alternate embodiment where the resistance values are determined in the manufacturing process by varying the size and doping characteristics of the FETs to produce the desired resistance ratio. As in  FIG. 3 , the input signal is coupled through node N 300  through a pair of transistors Q 300  and Q 301  through resistors R 300  and R 301 . In this embodiment the outputs of resistors R 300  and R 301  are coupled to node N 400 . Node N 400  is coupled through resistor R 400  to Node N 303 . Node N 303  is pulled to ground via capacitor C 300 .  
         [0000]     Single Transistor Embodiments  
         [0025]      FIGS. 5 and 6  illustrate embodiments of the transition time adjustment circuit using a single switching transistor. The circuit of  FIG. 5  uses a single FET Q 301  coupled to the input node N 300 . Instead of the transistor Q 300 , the supply voltage V 300  is coupled through resistor R 500  to Node N 500 . The remainder of the circuit matches that of  FIG. 4 .  
         [0026]     The circuit of  FIG. 6  uses a single bipolar transistor Q 600  with “ON” state base current provided from node N 300  through resistor R 600 . Resistor R 500  effectively replaces the upper switching device Q 300  in the totem pole structure of the prior embodiments. The remainder of the circuit matches that of  FIGS. 4 and 5 .  
         [0027]     The benefits of single switching transistor embodiments is a potential savings in cost.  
         [0028]     Thus, an Enhanced Timing Margin Memory Interface electronic circuit has been described.