Abstract:
Provided is a digital duty cycle corrector capable of generating a clock signal with the rate of duty 50:50, by means of three or more duty cycle correction circuits assigning different weight values to first and second clock signals that are different in duty cycle each other in order to reduce a phase difference between the first and second clock signals, and one or more duty cycle correction circuits assigning the same weight value to the first and second clock signals in order to eliminate a phase difference between the first and second clock signals.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a digital duty cycle corrector of a delay locked loop and specifically, to a digital duty cycle corrector revising duty of an input clock signal in the rate of 50:50. 
   DISCUSSION OF RELATED ART 
   There are general ways of correcting duty of a clock signal. For example, one is the method of correcting duty of a clock signal by using an analogue duty cycle correction circuit, and the other is the method of correcting duty by using a digital duty correction circuit with a synchronous delay loop. 
     FIG. 1  is a circuit diagram illustrating a conventional duty cycle corrector, and  FIG. 2  is a timing diagram showing waveforms of signals shown in  FIG. 1 . 
   Referring to  FIG. 1 , the digital duty correction circuit includes input buffers  110  and  120 , a duty cycle corrector  130 , and an output circuit  140 . 
   The input buffer  110  temporarily stores and transfers a clock signal CLK, while the input buffer  120  temporarily stores and transfers a clock signal CLKZ. 
   The duty cycle corrector  130  includes inverters  131  and  132  outputting a clock signal OUTX from mixing output signals of the input buffers  110  and  120 , and inverters  133  and  134  outputting a clock signal OUTY from mixing output signals of the input buffers  110  and  120 . 
   The output circuit  140  includes an inverter  141  converting the clock signal OUTX to output a clock signal OUT, and an inverter  142  converting the clock signal OUTY to output a clock signal OUTZ. 
   Such a digital duty cycle correction circuit is configured with an extended fan-out (here, larger than 6), which makes the clock signals CLK and CLKZ be mixed without distortion by lengthening the rising times of the clock signals CLK and CLKZ (refer to  FIG. 2 ). In other words, the rising or falling times of the clock signals CLK and CLKZ become longer so as to prevent distortion of the clock signals generated from mixing the clock signals CLK and CLKZ. 
   However, if the rising or falling times of the clock signals CLK and CLKZ are lengthened, it becomes weakened against power supply noises. And, if an operating frequency increases, the rising or falling times of the clock signals CLK and CLKZ becomes longer than a half period of the clock signal. Then, it is impossible to correct the duty because the clock signals CLK and CLKZ are disable to fully swing up and down. As a result, there is a problem that the conventional duty cycle corrector becomes useless when the frequency of the clock signals CLK and CLKZ increase. 
   SUMMARY OF THE INVENTION 
   The present invention is directed to solve the problem, providing a digital duty cycle corrector capable of a clock signal having duty of 50:50 by assigning different weight values to first and second clock signals that are different in duty cycle and last assigning the same weight value to the first and second clock signals. 
   In order to achieve the direction, a duty cycle corrector of a delay locked loop, according to a preferred embodiment of the present invention, is comprised of: more than three duty cycle correction circuits assigning different weight values to first and second clock signals that are different in duty cycle, reducing a phase difference between the first and second clock signals; and at least one duty cycle correction circuits assigning the same weight value to the first and second clock signals, eliminating a phase difference between the first and second clock signals. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings: 
       FIG. 1  is a circuit diagram illustrating a conventional duty cycle corrector; 
       FIG. 2  is a timing diagram showing waveforms of signals shown in  FIG. 1 ; 
       FIG. 3  is a circuit diagram illustrating a duty cycle corrector according to a preferred embodiment of the present invention; and 
       FIG. 4  is a timing diagram showing waveforms of signals shown in  FIG. 3 . 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numerals refer to like elements throughout the specification. 
     FIG. 3  is a circuit diagram illustrating a duty cycle corrector according to a preferred embodiment of the present invention, and  FIG. 4  is a timing diagram showing waveforms of signals shown in  FIG. 3 , to which clock signals TCLK and FCLK with the same rising phase difference and a large falling phase difference are applied. 
   Referring to  FIG. 3 , the digital duty cycle corrector shortens rising or falling times of the clock signals RCLK and FCLK with a small fan-out for example 2 or 3. 
   This digital duty cycle corrector is comprised of input buffers  210  and  220 , first through third duty cycle correction circuits  230 ,  240 , and  250  gradually reducing a phase difference between the clock signals RCLK and FCLK by assigning different weight values to the clock signals RCLK and FCLK, and a fourth duty cycle correction circuit  260  finally eliminating a phase difference between the clock signals RCLK and FCLK by assigning the same weight value to the clock signals RCLK and FCLK. 
   First, the input buffer  210  is composed of two inverters serially connected to each other, temporarily storing and outputting the clock signal RCLK. The input buffer FCLK is composed of two inverters serially connected to each other, temporarily storing and outputting the clock signal FCLK. 
   The first duty cycle correction circuit  230  is comprised of an inverter  231  with an enlarged MOS structure to make a weight value of the clock signal RCLK larger, an inverter  232  with a shrunken MOS structure to make the clock signal FCLK smaller, an inverter  233  with an enlarged MOS structure to make a weight value of the clock signal FCLK larger, and an inverter  234  with a shrunken MOS structure to make the clock signal RCLK smaller. 
   If the inverters  231  and  233  to increase the weight values of the clock signals RCLK and FCLK are constructed with a PMOS and an NMOS sized in the ratio 8:4, the inverters  232  and  234  to decrease the weight values of the clock signals FCLK and RCLK are constructed with a PMOS and an NMOS sized in the ratio 4:2. 
   The inverters  231  and  232  generate a mixed clock signal OUT 1  by mixing the clock signals RCLK and FCLK after increasing the weight value of the clock signal RCLK while decreasing the weight value of the clock signal FCLK. The inverters  233  and  234  generate a mixed clock signal OUT 2  by mixing the clock signals RCLK and FCLK after increasing the weight value of the clock signal FCLK while decreasing the weight value of the clock signal RCLK. From these operations, the mixed clock signal OUT 1  becomes similar to the clock signal RCLK, while the mixed clock signal OUT 2  becomes similar to the clock signal FCLK. But, a phase difference between the mixed clock signals OUT 1  and OUT 2  is smaller than that between the clock signals RCLK and FCLK (refer to the second waveform graph of  FIG. 4 ). 
   The second duty cycle correction circuit  240  is comprised of an inverter  241  with an enlarged MOS structure to make a weight value of the mixed clock signal OUT 1  larger, an inverter  242  with a shrunken MOS structure to make the mixed clock signal OUT 2  smaller, an inverter  243  with an enlarged MOS structure to make a weight value of the mixed clock signal OUT 2  larger, and an inverter  244  with a shrunken MOS structure to make the mixed clock signal OUT 1  smaller. 
   If the inverters  241  and  243  to increase the weight values of the mixed clock signals OUT 1  and OUT 2  are constructed with a PMOS and an NMOS sized in the ratio 8:4, the inverters  242  and  244  to decrease the weight values of the mixed clock signals OUT 2  and OUT 1  are constructed with a PMOS and an NMOS sized in the ratio 4:2. 
   The inverters  241  and  242  generate a mixed clock signal OUT 3  by mixing the mixed clock signals OUT 1  and OUT 2  after increasing the weight value of the mixed clock signal OUT 1  while decreasing the weight value of the mixed clock signal OUT 2 . The inverters  243  and  244  generate a mixed clock signal OUT 4  by mixing the mixed clock signals OUT 1  and OUT 2  after increasing the weight value of the mixed clock signal OUT 2  while decreasing the weight value of the mixed clock signal OUT 1 . From these operations, the mixed clock signal OUT 3  becomes similar to the mixed clock signal OUT 1 , while the mixed clock signal OUT 4  becomes similar to the mixed clock signal OUT 2 . But, a phase difference between the mixed clock signals OUT 3  and OUT 4  is smaller than that between the mixed clock signals OUT 1  and OUT 2  (refer to the third waveform graph of  FIG. 4 ). 
   The third duty cycle correction circuit  250  is comprised of an inverter  251  with an enlarged MOS structure to make a weight value of the mixed clock signal OUT 3  larger, an inverter  252  with a shrunken MOS structure to make the mixed clock signal OUT 4  smaller, an inverter  253  with an enlarged MOS structure to make a weight value of the mixed clock signal OUT 4  larger, and an inverter  254  with a shrunken MOS structure to make the mixed clock signal OUT 3  smaller. 
   If the inverters  251  and  253  to increase the weight values of the mixed clock signals OUT 3  and OUT 4  are constructed with a PMOS and an NMOS sized in the ratio 8:4, the inverters  242  and  244  to decrease the weight values of the mixed clock signals OUT 4  and OUT 3  are constructed with a PMOS and an NMOS sized in the ratio 4:2. 
   The inverters  251  and  252  generate a mixed clock signal OUT 5  by mixing the mixed clock signals OUT 3  and OUT 4  after increasing the weight value of the mixed clock signal OUT 3  while decreasing the weight value of the mixed clock signal OUT 4 . The inverters  253  and  254  generate a mixed clock signal OUT 6  by mixing the mixed clock signals OUT 3  and OUT 4  after increasing the weight value of the mixed clock signal OUT 4  while decreasing the weight value of the mixed clock signal OUT 3 . From these operations, the mixed clock signal OUT 5  becomes similar to the mixed clock signal OUT 3 , while the mixed clock signal OUT 6  becomes similar to the mixed clock signal OUT 4 . But, a phase difference between the mixed clock signals OUT 5  and OUT 6  is smaller than that between the mixed clock signals OUT 3  and OUT 4  (refer to the fourth waveform graph of  FIG. 4 ). 
   The fourth duty cycle correction circuit  260  is comprised of inverters  261 ,  262 ,  263 , and  264  each constructed in the size ratio 5:5, in order to make weight values of the mixed clock signals OUT 5  and OUT 6  be equal. 
   That is, the ratio of PMOS and NMOS of each of the inverters  261 ˜ 264  in size is designed to be 5:5. 
   The inverters  261  and  262  generate a mixed clock signal OUT 7  by mixing the mixed clock signals OUT 5  and OUT 6  after making the weight values of the mixed clock signals OUT 5  and OUT 6  identical. The inverters  263  and  264  generate a mixed clock signal OUT 8  by mixing the mixed clock signals OUT 5  and OUT 6  after making the weight values of the mixed clock signals OUT 5  and OUT 6  identical. The mixed clock signals OUT 7  and OUT 8  are conditioned without a phase difference (refer to the fifth waveform graph of  FIG. 4 ), having the duty 50:50 of logical high and low. 
   As aforementioned, the present invention is advantageous to set the duty ratio of input clock signals with different duty cycles even in a wide frequency range, for example by differentiating weight values of the first and second clock signals different in duty cycles and finally assigning the same weight value to the first and second clock signals. 
   Moreover, it is possible to overcome the problem weak in power noises by reducing a rising or falling time of a clock signal. 
   Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitution, modifications and changes may be thereto without departing from the scope and spirit of the invention.