Abstract:
A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the V nbias  between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to biasing circuitry for differential buffer stages. 
       BACKGROUND OF THE INVENTION 
       [0002]    A block diagram of a conventional DLL (delay-locked loop) is shown in  FIG. 1 . A voltage controlled delay line consisting of differential delay elements  12 ,  14 , . . .  16  takes an input clock signal refclk  10  and delays it by a precise amount based on its bias voltages  26 ,  28 . When the DLL is locked to the reference clock, the delay of each delay element is T clk /n, where T clk  is the clock period, and there are n differential delay elements  12 ,  14 , . . . ,  16 . The delay line produces a delayed clock dclk  18 . A feedback portion of the circuit compares the delayed clock dclk  18  to the reference clock refclk  10  and produces and adjusts the bias voltages V nbias    26  and V pbias    28  such that the delay is one clock period of the input clock. To do this, the feedback portion of the circuit has a phase detector  20  that compares the phase of refclk  10  to the phase of dclk  18 . If the two are the same, the bias voltages should remain as they are. If the two are out of phase, the bias voltages should increase or decrease to speed up or slow down the delay line accordingly. The phase detector  20  produces digital up or down pulses whose duration is proportional to the phase difference detected. The up and down pulses are used by the charge pump  22  to adjust a control voltage V ctrl    23 , typically stored on a loop filter capacitor. V ctrl  is used by the biasing circuit  24  to set the bias voltages  26 ,  28 . 
         [0003]    A specific example of a differential delay element is shown in  FIG. 2 . The amount of delay introduced into a digital waveform passing through the delay element can be controlled with the analog bias voltages. The analog bias voltages change the trip points at which the delay element changes logical state. The delay elements use a differential structure in order to increase noise rejection. Input devices M 2   42 , M 3   44  are a differential pair which steer output current through two branches. The analog voltage V nbias  on transistor M 1   40  helps determine the delay through the delay element by controlling the total current through each branch. Devices M 4   48 , M 5   50 , M 6   52 , M 7   54 , make up two symmetric load elements  49 ,  51  that are used to provide a linear resistance load. Only load element  49  will be described in detail. The symmetric load  49  is made up of two PMOS devices  48 ,  50  connected in parallel. One device M 5   50  has its gate tied to V pbias  while the other device M 4   48  is diode connected. V pbias  also helps control the delay by determining the signal swing. 
         [0004]    In order for the differential delay stage to operate properly, the bias voltages V nbias , V pbias  must be set. These voltages are derived from another voltage, V ctrl    23  of  FIG. 1 .  FIG. 3  shows an example of a conventional feedback circuit for generating the bias voltages V pbias  and V nbias  from V ctrl . V ctrl    23  is connected to an inverting input of an operational amplifier  102 . The output of operational amplifier  102  is connected to the gate of transistor  104  and to the gate of transistor  114 . A symmetric load  108  is connected to transistor  104  through additional transistor  106 . The symmetric load  108  includes a first transistor  110  having its gate connected to a non-inverting input of the operational amplifier  102 , and a second transistor  112  that is similarly connected. Transistors  114 ,  116 ,  111 ,  113  are connected in the same manner as transistors  104 ,  106 ,  110 ,  112 , and operate as a buffer for the output. The bias voltages are indicated at V pbias    28  and V nbias    26 . 
         [0005]    The feedback circuit of  FIG. 3  generates bias voltages that have the DC behaviour illustrated in  FIG. 4 .  FIG. 4  shows a first curve  120  for V ctrl , a second curve  122  for V pbias , and a third curve  124  for V nbias . 
         [0006]    Disadvantageously, the circuit of  FIG. 3  includes significant complexity, in particular including operational amplifier  102  which in itself includes many transistors not shown in detail. 
       SUMMARY OF THE INVENTION 
       [0007]    According to one broad aspect, the invention provides a biasing circuit comprising: an input for receiving a control voltage  23 , and a V nbias  output  26  for outputting a V nbias  voltage comprising: a feedback-free circuit  200 ,  202 ,  204  that produces the V nbias  voltage from the control voltage such that the V nbias  voltage is near one V DD  over a first control voltage range, sharply declines over a second control voltage range that follows the first control voltage range, and less sharply declines in a substantially linear manner over a third control voltage range that follows the second control voltage range. 
         [0008]    In some embodiments, the feedback-free circuit comprises: a pull-up network  200  for pulling up the V nbias  voltage when the control voltage is low; a pull-down network  204  for pulling down the V nbias  voltage when the control voltage is high; and a variable resistive element  202  for impeding the pull-down network from pulling down the V nbias . 
         [0009]    In some embodiments, the first voltage range is from about 0.0V to about 0.2V, the second voltage range is from about 0.2V to about 0.4V, and the third voltage range is a range above about 0.4V. 
         [0010]    In some embodiments, each of the voltage ranges is a respective range between 0 and V DD . 
         [0011]    In some embodiments, the feedback-free circuit comprises: a CMOS output stage having a P-type transistor  150  and an N-type transistor  152 , with a diode connected transistor  154  between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the V nbias  between the P-type transistor and the diode connected transistor. 
         [0012]    In some embodiments, the biasing circuit further comprises: V pbias  output  28  for outputting a V pbias  voltage; a direct connection between the input and the V pbias  output. 
         [0013]    In some embodiments, a delay locked loop comprises: a delay line comprising a plurality of differential delay elements  12 ,  14 ,  16 ; the biasing circuit is connected to provide the V pbias  voltage and the V nbias  voltage as biasing inputs to the differential delay elements. 
         [0014]    According to another broad aspect, the invention provides a method of biasing comprising: receiving a control voltage and outputting a V nbias  voltage; producing the V nbias  voltage in a feedback-free manner from the control voltage such that the V nbias  voltage is near one V DD  over a first control voltage range, sharply declines over a second control voltage range that follows the first control voltage range, and less sharply declines in a substantially linear manner over a third control voltage range that follows the second control voltage range. 
         [0015]    In some embodiments, the first voltage range is from about 0.0V to about 0.2V, the second voltage range is from about 0.2V to about 0.4V, and the third voltage range is a range above about 0.4V. 
         [0016]    In some embodiments, each of the voltage ranges is a respective range between 0 and V DD . 
         [0017]    In some embodiments, the method further comprises outputting a V pbias  voltage that tracks the control voltage. 
         [0018]    Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein: 
           [0020]      FIG. 1  is a block diagram of a delay locked loop; 
           [0021]      FIG. 2  is a schematic diagram of an example of a delay element; 
           [0022]      FIG. 3  is a schematic diagram of an example of a biasing circuit; 
           [0023]      FIG. 4  is a graph showing various voltages produced by the biasing circuit of  FIG. 3 ; 
           [0024]      FIG. 5  is a schematic diagram of a biasing circuit provided by an embodiment of the invention; 
           [0025]      FIG. 6  is a graph showing various voltages produced by the biasing circuit of  FIG. 5 ; and 
           [0026]      FIG. 7  is a schematic diagram of another example of a biasing circuit provided by an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]      FIG. 5  is a schematic diagram of a biasing circuit provided by an embodiment of the invention. The biasing circuit of  FIG. 5  will be described in the context of its application in providing biasing voltages to the delay element of  FIG. 2 . However, it is to be understood that the biasing circuit may find application to providing biasing voltages to other delay element designs. This circuit also takes the input V ctrl    23  and produces biasing voltages V pbias    28  and V nbias    26 . The circuit directly connects the input voltage V ctrl    23  to V pbias    28 . V ctrl    23  is also connected to the gate of transistor P 1   150  and the gate of transistor S 1   152 . Transistor P 1   150  is connected to transistor S 1   152  through diode connected transistor M 1   154 . The bias voltage V nbias    26  is taken at the drain of transistor M 1   154 . Transistor S 1  may be implemented with a size larger than that of M 1  to accommodate the current generated by M 1 . 
         [0028]    The purpose of this circuit is to mimic the DC behaviour of the biasing circuit of  FIG. 3 . With reference to  FIG. 4 , when V ctrl  is between 0.3V and 0.9V if can be seen that V ctrl  and V pbias  are approximately equal. With reference back to  FIG. 5 , this behaviour is reproduced by a direct connection between V ctrl    23  and V pbias    28 . Operation of the circuit for other values of V ctrl  will result in different behaviour than that shown in  FIG. 4 . The remaining circuitry of  FIG. 5  is for producing a V nbias  that mimics the behaviour of V nbias  shown in  FIG. 4  for the circuit of  FIG. 3 . The behaviour of the circuit of  FIG. 5  is shown in  FIG. 6 . Shown are curves  160  for V ctrl =V pbias , and  162  for V nbias . 
         [0029]    It is noted that a biasing circuit that produces only V pbias    28  is also contemplated. The control voltage V ctrl    23  might for example be directly connected to the V pbias  inputs of the differential delay elements, or the V pbias  inputs might be generated in some other manner. 
         [0030]    In operation, as V ctrl  rises, transistor S 1 , which is selected for its switching characteristics, starts to turn on, and transistor P 1   150  starts to turn off. This starts to pull down the voltage V nbias . When transistor S 1   152  is completely on, transistor P 1   150  will be completely off and V nbias  will then be very close to zero volts (or V SS ). Between approximately 0.2 volts and 0.4 volts the transistor S 1  is transitioning from being completely off to being partially on. During this period, the transistor P 1   150  and the switch S 1   152  are both trying to pull V nbias  in one way or the other, but outside of that range, S 1  overtakes P 1 . The result is that, again referring to  FIG. 6 , V nbias  drops sharply between 0.2 and 0.4 volts, and then levels off to a more moderate rate of decline between 0.4 volts and 1.0 volts. 
         [0031]    It can be seen that the curve  162  for V nbias  in  FIG. 6  is very similar to the curve for V nbias    124  in  FIG. 4 . Furthermore, the curve for V pbias  in  FIG. 6  is the same as curve  122  for V pbias  in  FIG. 4  over the range of 0.3 through 0.9 volts. 
         [0032]    The bias voltages V pbias , V nbias  together define the voltage swing at the output of the differential delay element. The effect of the inaccuracy in V pbias  between 0.2 volts and 0.3 volts is that the voltage will swing a little bit lower, and the swing will be non-symmetric. The assumption is that the circuits operation is non-critical below 0.3 volts. Setting V pbias  sets the swing. 
         [0033]    In more general terms, the biasing circuit includes a complementary MOS output stage (P 1   150 , S 1   152 ) with a diode-connected transistor  154  in series between the two complementary transistors. However, the transistor  154  clearly makes the operation very different from that of a standard CMOS output stage, which would have a steep transition between high and low states of the output voltage as the control or input voltage is changed. 
         [0034]    More generally still, a feedback-free circuit is provided that produces the V nbias  voltage from the control voltage such that the V nbias  voltage is near V DD  over a first control voltage range, sharply declines over a second control voltage range that follows the first control voltage range, and less sharply declines in a substantially linear manner over a third control voltage range that follows the second control voltage range. In some implementations, V DD  is about 1V, and the first voltage range is from about 0V to about 0.2V, the second voltage range is from about 0.2V to about 0.4V, and the third voltage range is a range above about 0.4V. These ranges are process and design dependant. In some implementations, the ranges are a function of V DD , for example 0 to 0.2V DD , 0.2 V DD  to 0.4V DD  and above 0.4V DD . Another specific example is 0 to 0.3V DD , 0.3V DD  to 0.5V DD , and above 0.5V DD . 
         [0035]    Referring now to  FIG. 7 , shown is a schematic diagram of another biasing network provided by an embodiment of the invention. This circuit again receives the V ctrl    23  input and produces a V nbias  output  26 . The input  23  is connected to a pull-up network  200  and a pull-down network  204 . There is a variable resistor element  202  for impeding the pull-down network from pulling down V nbias    26 . It can be seen that the circuit of  FIG. 5  is a specific example of the  FIG. 7  embodiment. Specifically, for the  FIG. 5  embodiment, the pull-up network  200  is P transistor  150 , the pull-down network  204  is the transistor S 1   152 , and the variable resistor  202  is the diode connected transistor M 1   154 . However, it is to be understood that other elements can be used. 
         [0036]    In the embodiments described above, the device elements and circuits are connected to each other as shown in the figures, for the sake of simplicity. In practical applications of the present invention to semiconductor ICs and DRAM devices, elements, circuits, etc. may be connected directly to each other. As well, elements, circuits etc. may be connected indirectly to each other through other elements, circuits, etc., necessary for operation of the semiconductor ICs and DRAM devices. Thus, in actual configuration of semiconductor ICs and DRAM devices, the circuit elements and devices are coupled with (directly or indirectly connected to) each other. 
         [0037]    The above-described embodiments of the present invention are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.