Abstract:
An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a surface area of the first die. A method including arranging a plurality of second dice on a first die such that collectively the plurality of second dice include a surface area approximating the surface area of the first die; and electrically coupling a plurality of second device to a plurality of the first die. A system including an electronic appliance including a printed circuit board and a module, the module including a first die including a plurality of TSVs; and the plurality of second dice arranged to collectively include a surface area approximating the surface area of the first die.

Description:
FIELD 
     Integrated circuit packaging 
     BACKGROUND 
     Efforts are being made to stack chips or dice to increase performance without taking more space (e.g., more surface area) on a printed circuit board. This is particularly driven by requirements for sophisticated cell phones, smart phones, and other mobile devices. Chip makers have combined dynamic and static random access memory (DRAM and SRAM), flash and other memory in a connected integrated circuit structure or stack, but have historically been restrained by the added space requirements of wiring (e.g., wire bonding) that connects the chips. Chip or die stacking technology bonds two or more dies together to form a connected integrated circuit structure. The chips or dies may be connected together with interconnect wiring along the sides of the stack or metal vias at the die-die interfaces. 
     One common approach for chip or die stacking is referred to as face-to-face bonding. In this configuration, the device sides of, for example, two respective dies are stacked so that their device sides are facing one another and metal vias electrically connect the dies at the die-die interface. In one representation of a face-to-face bonded connected integrated circuit structure, a central processing unit (CPU) or logic die and a memory die (e.g., SRAM or DRAM die) are stacked together in a face-to-face bonding configuration. A heat sink may be attached to the bulk of the CPU or logic die and the power and input/output (I/O) connections to the package or circuit board are made with bump technology attached to the bulk of the memory die. Through-silicon vias (TSVs) may be used to pass through the memory die and connect to the metal die-to-die interface. 
     In the above example, since the through-silicon vias pass through the active silicon area of the memory of the second die (e.g., a memory die), sufficient area must be allocated in the circuitry to permit the through-silicon vias. These vias can typically be large (greater than 10 times) the minimum design rules for a given process due to power delivery requirements. Power for both dies is supplied by the through-silicon vias. Power requirements will dictate an approximately one through-silicon via per bump contact. In flip chip packaging, the bumps are usually arranged in a widely spaced uniform pattern across an entire two-dimensional die allowing for a high number of uniform power and ground connections at the top metal layer. This requires that the circuitry in the second die (e.g., memory die) be designed to accommodate these vias with proper spacing to adjacent geometries. This implies that the second die would need to be custom designed to exactly match the via requirements of the first die. 
     Another bonding configuration is a face-to-back bonding configuration. Using the example of a CPU die and a memory die, in a face-to-back bonding configuration, the position of the two die might be swapped. For example, the first die (CPU die) signal and power connections would be attached to the package in a typical way using standard bump technology. Power and signal connections for the second die (e.g., memory die) would pass through the first die using through-silicon vias. The power requirements of a memory die are usually much lower than a CPU or logic die and therefore the number of through silicon vias required to pass through the first die (e.g., CPU die) is considerably less and need not be uniformly spaced across the die. This makes the design and layout of a CPU die much less impacted by the three-dimensional bonding of a second die. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features, aspects, and advantages of embodiments will become more thoroughly apparent from the following detailed description, appended claims, and accompanying drawings in which: 
         FIG. 1  shows a top exploded view of a connected integrated circuit structure including a first die and multiple singulated or unsingulated dice arranged to occupy a surface area of the first die. 
         FIG. 2  shows a top side view of the structure of  FIG. 1  and shows bond pads associated with each of the second dies. 
         FIG. 3  shows a side view taken through line  3 - 3 ′. 
         FIG. 4  shows the structure of  FIG. 2  taken through line  3 - 3 ′ and illustrating a redistribution layer to electrically connect the contacts on the second dies with through-silicon vias on the first die. 
         FIG. 5  shows an embodiment of a surface of the first die. 
         FIG. 6  shows another embodiment of a connected integrated circuit structure including a first die and a plurality of second dies. 
         FIG. 7  shows a flow chart of an embodiment of a method of forming a connected integrated circuit structure. 
         FIG. 8  shows a schematic side view of an electronic assembly as part of a desktop computer. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1-3  show different views of an embodiment of a connected integrated circuit structure including first die  110  and a number of singulated or unsingulated second dice  210  electrically connected on die  110 . Die  110  is for example a CPU or logic die. In one embodiment, dice  210  (collectively individual die  210 A, die  210 B, die  210 C and die  210 D) are memory dice (e.g., SRAM, DRAM) or other dice or a combination of different dice (e.g., logic and memory). The multiple dice represented by dice  210  collectively have a die size (surface area) approximating or matching a size (surface area) of first die  110 . Representatively, die  110  that is a CPU or logic die may have, for example, a surface area of 400 square millimeters (mm 2 ). Each of dice  210  (die  210 A, die  210 B, die  210 C, die  210 D), in this example, have a surface area of 100 mm 2  such that the total surface area occupied by dice  210  is also 400 mm 2 . Where dice  210  are memory structures such as DRAM, the dice may be selected such that collectively the dies constitute an acceptable match for DRAM density and die size. With respect to density, a DRAM die size may be one gigabyte (Gb) according to current technologies where the number of dice is four as shown. Alternatively, for less capacity DRAM (e.g., 512 kilobytes (Kb) or 256 Kb, the number of dies  210  may be greater (e.g., eight dies for 512 Kb at 60 mm 2  each (480 mm 2 )). 
       FIG. 1  shows two examples of dice  210 . In one example, each of dice  210  (die  210 A, die  210 B, die  210 C and die  210 D) are singulated and assembled as a distinct unit on die  110 . Alternatively, the multiple dies may be scribed as a single unit and attached to die  110 . 
     Memory dice (e.g., SRAM, DRAM) are readily available in either die or wafer form. These dice are commonly used in wire-bonded applications. Representatively, these dice may have 4-32 I/O plus power bond pads per die. These bond pads are usually arranged in a narrow one to two bond pad wide column through the center of the die.  FIG. 2  shows dice  210  (e.g., die  210 A, die  210 B, die  210 C and die  210 D) having a two bond pad wide column through the center of each die of bond pads  220  (shown in ghost lines to illustrate the bond pads are on an opposite surface of the dice as viewed). 
     In one embodiment die  110  may be a multi-core processor. A multi-core processor generally has multiple complete execution cores in one physical processor, each running at the same frequency. Each core typically shares the same packaging. Referring to  FIG. 1 , die  110  may be, for example, a dual core processor, a quad-core processor (illustrated) or more. 
     In one embodiment, die  110  and dice  210  are connected in a face-to-back bonding configuration. Referring to  FIG. 3 , die  110  has a number of through-silicon vias (TSVs)  130  formed therein. Through-silicon vias  130  include a conductive material therethrough such as copper that is used to connect die  110  and/or contacts  320  on package  310  to contacts (e.g., bond pads) on dice  210  (die  210 C and die  210 D as shown).  FIG. 3  shows die  110  with device side  120  adjacent and coupled to package  310  with through-silicon vias  130  extending through die  110  (from a device side to a back side (surface  125 ). Through-silicon vias of a conductive material such as copper may be formed as part of the processing steps that are utilized to make up die  110 . In such manner, through-silicon vias  130  may be patterned to align with contact pads  220  (see  FIG. 2 ) of the second dice.  FIG. 3  shows through-silicon vias  130  extending from electrical contacts  320  (e.g., solder bumps on bond pads) to bond pads  220  of second dice  210 C and  210 D. Dice  210  may be arranged such that a device side (bond pad side) of each die is arranged on the back side of die  110 .  FIG. 3  also shows heat sink  410  connected to a back side of dice  210 . 
     In some embodiments, through-silicon vias associated with die  110  will not be aligned with contacts (e.g., bond pads) of dice  210 . In such situations, an electrically conductive redistribution layer, such as a metal (e.g., copper) layer, may be patterned on either the back side of die  110  or the device side of dice  210 . Such a redistribution layer can serve as an interconnect between the contact points (e.g., bond pads) of dice  210  and through-silicon vias  130 .  FIG. 4  shows the connected integrated circuit structure of  FIG. 2  through lines  3 - 3 ′ layer according to another embodiment. In this example, contact points  220  of die  210 C and die  210 D are not aligned to through-silicon vias  130  extending between package  310  and through die  110 .  FIG. 4  shows redistribution layer  150  of, for example, a conductive material such as copper patterned, in one embodiment, on a back side of die  110 .  FIG. 5  shows a back side surface of die  110  having through-silicon vias  130 A and  130 B extending through die  110  to the back side surface.  FIG. 5  also shows patterned redistribution layer  150  extending laterally from each through-silicon via  130 A. In this example, through-silicon vias  130 B would be aligned with contact points of second dice  210 . Representatively, redistribution layer  150  may be a conductive material such as copper patterned using photolithographic techniques wherein, for example, a copper material is deposited on a back side surface of die  110  followed by a mask to define redistribution layer  150  and etching to pattern the redistribution layer as fingers extending laterally from through-silicon vias  130 A to a desired position for electrical contact with contact points of second dice  210 C and  210 D. Redistribution layer  150  may be connected to contact points of dies  210  through, for example, solder connections as can through-silicon vias  130 B. 
     Where necessary, a spacer material may be formed of, for example, a dielectric material in conjunction with the redistribution layer on a surface of die  110  or dies  210  to account for any gaps between the dies.  FIG. 4  shows spacer material  160  formed with redistribution layer  150  on a surface of die  110 . 
     In the description with reference to  FIGS. 1-5 , four dice  210  such as memory die (e.g., DRAM or SRAM) are shown each of the dice having a similar die size. It is appreciated that, in other embodiments, dice having different functions and different sizes may be stacked on top of one another.  FIG. 6  shows a top view of a connected integrated circuit structure of die  510  of, for example, a CPU or logic die. Arranged on a surface (e.g., a back side surface) of die  510  are dice  610 A and  610 B of, for example, DRAM memory. Also on a back side of die  510  is die  620  having a die size (cross-sectional area) greater than die  610 A or die  610 B. Die  620  is, for example, SRAM memory. In this example, die  610 A, die  610 B and die  620  are described as memory dice, but it is appreciated that other forms of die may be used as well, such as CPU or logic dice. 
       FIG. 7  shows a flow chart of a method of forming a connected integrated circuit structure. In this embodiment, memory dice will be assembled on a surface, such as a back side surface of a CPU or logic die. As noted above, it is appreciated that the selection of the type of die may vary. 
     Referring to  FIG. 7 , in this embodiment, initially the memory requirements for a connected integrated circuit structure are determined (block  710 ). For example, the desired memory requirements may be one gigabyte (Gb) of DRAM memory for a connected integrated circuit structure. 
     Having determined the memory requirements, a number of memory dice are then selected such that a sum of the surface area of multiple dice approximate the surface area (e.g., a back side surface area) of a CPU logic die (block  720 ). For example, where a surface area of a CPU or logic die is 400 mm 2 , and one Gb DRAM memory chips are available having a surface area of 100 mm 2 , four DRAM memory chips (4×100 mm 2 ) approximates a surface area of the CPU or logic die. 
     Following the selection of the memory dice, the contact points (power and I/O contact points) of the memory dice are examined and a pattern compared to a pattern of through-silicon vias desired for the CPU logic die. At that point, a determination is made whether a redistribution layer is necessary (block  730 ). If no redistribution layer is necessary, the contacts may be patterned on the back side of CPU or logic die (block  740 ). If a redistribution layer is necessary, a redistribution layer is patterned on a back side surface of a CPU or logic die and contacts established to the redistribution layer (block  750 ). 
     Once contacts are established on a surface (e.g., back side surface) of a CPU die, the multiple memory dies are connected to the CPU or logic die by, for example, solder connections (block  760 ). Following the connection of the memory dies to the CPU or logic die, the connected die stack may be connected to a substrate package including the through-silicon vias that extend to the memory dies (block  770 ). A heat sink and any other processing techniques typically utilized in assembling package substrates may then follow. 
       FIG. 8  shows a side view of an electronic assembly including a connected integrated circuit structure that can be physically and electrically connected to a printed wiring board or printed circuit board (PCB). The electronic assembly can be part of an electronic system such as a computer (e.g., desktop, laptop, handheld, server, etc.), wireless communication device (e.g., cellular phone, cordless phone, pager, etc.), computer-related peripheral (e.g., printer, scanner, monitor, etc.), entertainment device (e.g., television, radio, stereo, tape and compact disc player, video cassette recorder, MP3 (motion picture experts group, audio layer 3 player, etc.), and the like.  FIG. 8  illustrates the package is part of a desktop computer.  FIG. 8  shows electronic assembly  800  including connected integrated circuit structure  805  physically and electrically connected to package substrate  810 . Package substrate  810  may be used to connect die  100  to printed circuit board  820 , such as a motherboard or other circuit board. 
     In the preceding detailed description, reference is made to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.