Abstract:
A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.

Description:
FIELD OF INVENTION 
     The present invention relates to semiconductor nanowire field effect transistors. 
     DESCRIPTION OF RELATED ART 
     A nanowire field effect transistor (FET) includes the nanowire channel region surrounded by a gate material. The nanowire channel region is contacted by doped portions of said nanowire that serve as source and drain regions of the device. Previous fabrication methods used silicon on insulator (SOI) pads to keep the nanowires suspended above a buried oxide (BOX) layer to allow the gate to be formed on all sides of the nanowire, resulting in gate-all-around transistors. The pads may consume valuable space on a silicon wafer. 
     BRIEF SUMMARY 
     In one aspect of the present invention, a method for forming a nanowire field effect transistor (FET) device includes forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a semiconductor substrate, patterning a first hardmask layer over the second SOI portion, forming, from the first SOI portion, a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming, from the second SOI portion, a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer. 
     In another aspect of the present invention, a method for forming a nanowire field effect transistor (FET) device includes forming a raised silicon on insulator (SOI) region on a semiconductor substrate, patterning a first hardmask layer over a first portion of the SOI region and a second portion of the SOI region, forming from an exposed portion of the SOI region, a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer to expose the first and second portions of the SOI region, forming, from the exposed first SOI portion, a second suspended nanowire over the semiconductor substrate and from the exposed second SOI portion, a third suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire and a third gate structure around a portion of the third suspended nanowire, and removing the second hardmask layer. 
     In yet another aspect of the present invention, a nanowire field effect transistor (FET) device includes a silicon nanowire having a first channel region surrounded by a first gate structure disposed circumferentially around the silicon nanowire and a second channel region surrounded by a second gate structure disposed circumferentially around the silicon nanowire, wherein the silicon nanowire is suspended above a semiconductor substrate by a first capping portion disposed on the first gate structure and a second capping portion disposed on the second gate structure. 
     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIGS. 1A-8  illustrate an exemplary method for forming nanowire FET devices. In this regard: 
         FIG. 1A  illustrates a cross-sectional view of an example of a relationship between the width of SOI pad regions and the width of undercut regions from an exemplary etching process. 
         FIG. 1B  illustrates the formation of a SOI layer; 
         FIG. 1C  illustrates a top view of the SOI layer of  FIG. 1B ; 
         FIG. 2  illustrates the formation of nanowires; 
         FIG. 3A  illustrates the formation of gates; 
         FIG. 3B  illustrates a cross-sectional view of a gate along the line  3 B of  FIG. 3A ; 
         FIG. 4  illustrates the formation of a nanowire; 
         FIG. 5  illustrates the formation of gates; 
         FIG. 6  illustrates the removal of a hardmask layer; 
         FIG. 7  illustrates the formation of spacers; and 
         FIG. 8  illustrates ion implantation. 
         FIGS. 9A-16  illustrate cross-sectional views of an alternate exemplary method for forming nanowire FET devices. In this regard: 
         FIG. 9A  illustrates the formation of a SOI layer; 
         FIG. 9B  illustrates a top view of the formation of the SOI layer; 
         FIG. 10  illustrates the formation of a hardmask layer; 
         FIG. 11  illustrates the formation of a nanowire; 
         FIG. 12  illustrates the formation of gates; 
         FIG. 13  illustrates the formation of nanowire; 
         FIG. 14  illustrates the formation of gates; 
         FIG. 15  illustrates the formation of spacers; and 
         FIG. 16  illustrates ion implantation. 
     
    
    
     DETAILED DESCRIPTION 
     Previous fabrication methods limit the number of gate-all-around FET devices that may be formed over suspended nanowire sections. This is due to the finite length of suspended nanowires, as a long section of suspended nanowire may sag and contact an buried oxide layer of the device, preventing formation of gate-all-around structures. 
     Silicon on insulator (SOI) pads with sufficient width may be used to keep sections of the nanowires suspended above the BOX layer ( FIG. 1A ). However, as device pitch continue to decrease, the pad width (W) could become so narrow that the undercut width in the BOX layer (U), used to fully suspend the nanowire, could cause the pad to loose physical support and thus, no longer suspend the nanowires. While the pads are used, if a hydrogen annealing process is to be used to smooth the nanowires, the pads may consume valuable space on a silicon wafer. 
       FIG. 1A  illustrates an example of a relationship between the width of SOI pad regions  1701 ,  1702  and  1703  having different widths (W). In this regard, the etching and removal of the BOX layer  104  material is operative to result in an undercut regions having a length (U). The resultant structure results in SOI pad region  1701  having a width greater than 2 U remaining supported by the BOX layer  1704 . The SOI pad region  1702  having a width equal to 2 U is partially supported by the BOX layer  1704 . The SOI pad region  1703  having a width less than 2 U is detached from the BOX layer  1704 . 
       FIGS. 1B-8  illustrate cross-sectional views of an exemplary method for forming nanowire FET devices. 
     With reference now to  FIG. 1B , a cross-sectional view is shown of a silicon on insulator (SOI) portion  102  is defined on a buried oxide (BOX) layer  104  that is disposed on a silicon substrate  100 . The SOI portion  102  includes SOI pad regions  106 , SOI pad regions  108 , and nanowire portions  109   a - c . The SOI portion  102  may be patterned by the use of lithography followed by an etching process such as, for example, reactive ion etching (RIE). 
       FIG. 1C  illustrates a top-down view of the SOI portion  102  that illustrates an example of the arrangement of the nanowire portions  109   a - n . As illustrated, the SOI portion  102  may include any number (n) of nanowire portions  109 . 
       FIG. 2  illustrates the resultant structure following the deposition and patterning by lithography and etching of a hardmask layer  203   b  over the nanowire portion  109   b . The hardmask layer  203   b  may be formed from, for example, a nitride and/or oxide material. Once the hardmask layer  203   b  is formed, portions of the BOX layer  104  that are not protected by the hardmask layer  203   b  are removed with an isotropic etching process. The BOX layer  104  is recessed in regions not covered by SOI portion  102 . The isotropic etching results in the lateral etching of portions of the BOX layer  104  that are under the SOI portion  102 . The lateral etch suspends the nanowires  109   a  and  109   c  above the BOX layer  104 . The length of the suspended nanowire  109   a  and  109   c  may be chosen to limit the nanowire  109   a  and  109   c  from sagging and touching the BOX layer  104 . The lateral etch may form undercuts  201  in the BOX layer  104  and overhang portions at the edges of SOI regions  106  and  108 . The isotropic etching of the BOX layer  104  may be, for example, performed using a diluted hydrofluoric acid (DHF). A 100:1 DHF etches about 2 to 3 nm of BOX layer  104  per minute at room temperature. Following the isotropic etching the nanowires portions  109   a  and  109   c  may be smoothed to reduce the line edge roughness. This process may result in elliptical shaped (and in some cases, cylindrical shaped) nanowires  110   a  and  110   c  that are suspended above the BOX layer  104  by the SOI pad regions  106  and the SOI pad regions  108 . The smoothing of the nanowires may be performed by, for example, annealing of the nanowires  109   a  and  109   c  in hydrogen. Example annealing temperatures may be in the range of 600° C.-900° C., and a hydrogen pressure of approximately 7 torr to 600 torr. 
     A thinning process may be performed on the nanowires  110   a  and  110   c  to reduce the diameter of the nanowires  110   a  and  110   c . The reduction of the diameter of the nanowires  110   a  and  110   c  may be performed by, for example, an oxidation of the nanowires  110   a  and  110   c  followed by the etching of the grown oxide. The oxidation and etching process may be repeated to achieve a desired nanowire  110   a  and  110   c  diameter. Once the diameters of the nanowires  110   a  and  110   c  have been reduced, gates are formed over the channel regions of the nanowires  110   a  and  110   c  (described below). 
       FIG. 3A  illustrates gates  302  that are formed around portions of the nanowires  110   a  and  110   c , as described in further detail below, and capped with a polysilicon layer (capping layer)  304 . A hardmask layer  306 , such as, for example silicon nitride (Si 3 N 4 ) is deposited over the polysilicon layer  304 . The polysilicon layer  304  and the hardmask layer  306  may be formed by depositing polysilicon material over the BOX layer  104  and the SOI portion  102 , depositing the hardmask material over the polysilicon material, patterning by lithography and etching by RIE to form the polysilicon layer  304  and the hardmask layer  306  illustrated in  FIG. 3A . Portions of the polysilicon layer  304  are formed under the SOI pad regions  106  and  108  in the undercut regions  201  (of  FIG. 2 ). The polysilicon layer  304  partially supports portions of the SOI pad regions  106  and  108 . 
     The etching of the gates  302  may be performed by directional etching that results in straight sidewalls of the gate  302 . Following the directional etching, polysilicon  304  remains under portions of the nanowires  110   a  and  110   c  that are outside the region encapsulated by the gates  302 . Isotropic etching may be performed to remove polysilicon  304  from under the nanowires  110   a  and  110   c.    
       FIG. 3B  illustrates a cross sectional view of a gate  302  along the line  3 B (of  FIG. 3A ). The gate  302  is created by forming a first gate dielectric layer  402 , such as silicon dioxide (SiO 2 ) fully surrounding a channel portion of the nanowire  110   a . A second gate dielectric layer  404  such as, for example, hafnium oxide (HfO 2 ) is formed around the first gate dielectric layer  402 . A metal layer  406  such as, for example, tantalum nitride (TaN) or titanium nitride (TiN) is formed around the second gate dielectric layer  404 . The metal layer  406  is surrounded by polysilicon layer  304  (of  FIG. 3A ). Doping the polysilicon layer  304 , which may occur before or after gate patterning, with impurities such as boron (p-type), or phosphorus (n-type) makes the polysilicon layer  304  conductive. Following the polysilicon  304  patterning described above, portions of the metal layer around the nanowire  110   a  outside the encapsulated gate region(s)  302  are removed by an isotropic etching process. This process may be carried out by, for example, an isotropic chemical etch or a RIE process that has a significant lateral etch component. 
     Alternatively, full metal gates may be formed on the nanowires  110   a  and  110   c . A metal gate may include a combination of metal layers such as tantalum, titanium aluminum nitride, aluminum, and titanium nitride. These metal layers are deposited around the nanowire  110   a  after the dielectric formation, and are patterned by lithography and etching in a similar fashion as described above. The metal layers result in a similar structure as described above, however, the regions filled with the polysilicon  304  material are filled with a metallic gate material. 
     Alternatively, the gate stack  302  and  304  may form a dummy gate, composed of replaceable materials such as polysilicon or oxide, which can be later replaced with an alternative gate stack. 
       FIG. 4  illustrates the resultant structure where hardmask layers  203   a  and  203   c  are formed over the polysilicon layers  304 , the hardmasks  306 , the nanowires  110   a  and  110   c , and the SOI pad regions  106  and  108  using a similar method as described above to form the hardmask layer  203   b  (of  FIG. 2 ). Alternatively, spacers with sufficient thickness may be formed on the sidewalls of polysilicon  304  and hardmask  302  to cover the pads  106  and  108 . This spacer can be formed by a blanket deposition of dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by RIE. This method affords a self-aligned process in masking the region. 
     The hardmask layer  203   b  is selectively removed, and the nanowire  110   b  is formed from the nanowire portion  109   b  using a similar process as described above to form the nanowires  110   a  and  110   c.    
     Referring to  FIG. 5 , gates  302 , capping layer  304 , and hardmask  306  are formed on the nanowire  110   b  using similar methods as described above, though composition of the individual gate stack layers may vary. The formation of the capping layer  304  results in undercut regions below the SOI pad regions  106  and  108  being filled with the capping layer  304  material resulting in the SOI pad regions  106  and  108  being partially supported by the capping layer material  304 . 
       FIG. 6  illustrates the resultant structure following the removal of the hardmask layers  203   a  and  203   c.    
       FIG. 7  illustrates spacer portions  704  that may be formed along opposing sides of the polysilicon layer  304 . The spacers are formed by depositing a blanket dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by RIE. The spacer walls  704  are formed around portions of the nanowire  110   a - c  that extend from the polysilicon layer  304  and surround portions of the nanowires  110   a - c . Spacer portions (not shown) may be formed under the nanowires  110   a - c , and in the undercut regions (not shown) of the SOI pad regions  106  and  108 . 
     At this point, source (S) and drain (D) regions may be defined on the device by a variety of process. For example, the exposed nanowires  110   a - c  and the SOI pad regions  106  and  108  may be increased in size using an epitaxial silicon growth process, with or without in-situ doping. The source and drain regions may be doped by, for example, exposure to n-type or p-type ions. 
       FIG. 8  illustrates the resultant structure following the removal of the hardmasks  306 , which exposes the polysilicon layers  304 . Following the removal of the hardmasks  306 , the gate (G) regions may be defined on the device by a variety of process, for example, doping by exposure to n-type or p-type ions. 
     Alternatively, following the removal of the hardmasks  306 , the source (S) drain (D), and gate (G) regions may be defined on the device simultaneously by a variety of process, for example, doping by exposure to n-type or p-type ions. 
     A silicide may be formed in the source, gate, and drain regions, and conductive contacts may be formed to contact the regions by any suitable process. 
       FIGS. 9A-16  illustrate cross-sectional views of an alternate exemplary method for forming a nanowire FET. The alternate exemplary method is similar to the method described above in  FIGS. 1-8 . 
     Referring to  FIG. 9A , a silicon on insulator (SOI) portion  102  is defined on a buried oxide (BOX) layer  104  that is disposed on a silicon substrate  100 . The SOI portion  102  includes a nanowire portion  109 . The SOI portion  102  may be patterned by the use of lithography followed by an etching process such as, for example, reactive ion etching (RIE). 
       FIG. 9B  illustrates a top-down view of the SOI portion  102  that illustrates an example of the arrangement of the nanowire portion  109 . 
       FIG. 10  illustrates the resultant structure following the patterning and deposition of hardmask layers  203   a  and  203   c  over the nanowire portion  109 . The hardmask layers  203   a  and  203   c  are formed in a similar manner to the hardmask layers  203  described above. 
       FIG. 11  illustrates the resultant structure following an isotropic etching process similar to the process described above to remove portions of the nanowire portion  109  to form a nanowire  110   b  and to define the nanowire portions  109   a  and  109   c  that are protected from the etching process by the hardmask layers  203   a  and  203   c . The nanowire  110   b  is suspended above the BOX layer  104  by the nanowire portions  109   a ,  109   c  and hardmasks  203   a  and  203   c . An oxidation process similar to the process described above may be performed to reduce the size of the nanowire  110   b  if desired. 
       FIG. 12  illustrates the resultant structure following the formation of gates  302  that are around portions of the nanowires  110   b , capped with a polysilicon layer (capping layer)  304 , and topped with a hardmask layer  306 . The gate is patterned using a similar method as described above. 
     Referring to  FIG. 13 , hardmasks  203   b  have been deposited over the nanowire  110   b , the polysilicon layer  304  and the hardmask layer  306 . The hardmask layers  203   a  and  203   c  have been removed, and the nanowires  110   a  and  110   c  are suspended by the hardmasks  203   b . An oxidation process similar to the process described above may be performed to reduce the size of the nanowire  110   a  and  110   c  if desired. 
       FIG. 14  illustrates the formed gates  302 , polysilicon layers  304 , and hardmask layers  306  that are formed on the nanowires  110   a  and  110   c  using a similar method as described above. 
       FIG. 15  illustrates spacer portions  704  that may be formed along opposing sides of the polysilicon layer  304  using similar methods as described above. 
       FIG. 16  illustrates the resultant structure following the removal of the hardmasks  306 , which exposes the polysilicon layers  304 . Following the removal of the hardmasks  306 , source (S), drain (D), and gate (G) regions may be defined on the device by a variety of process. For example, the exposed nanowires  110   a - c  may be increased in size using an epitaxial silicon growth process. The source and drain regions may be doped by, for example, exposure to n-type or p-type ions, and a silicide may be formed in the source, gate, and drain regions, and conductive contacts may be formed to contact the regions by any suitable process. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 
     The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
     While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.