Abstract:
The disclosure provides a motherboard including a north bridge chipset, a basic input output system (BIOS), a first video graphics array (VGA) connector, and a controlling module. The north bridge chipset outputs a sleep signal to the controlling module, the controlling module obtains a switch signal from the first VGA connector, the controlling module outputs a first mode signal to the north bridge chipset according to the sleep signal and the switch signal, the north bridge chipset controls the computer host to be asleep according to the sleep mode. The disclosure also provides a computer control system including the motherboard. The motherboard and the computer control system control the computer to be asleep via a display.

Description:
FIELD 
     The subject matter herein generally relates to a motherboard, and particularly to a computer control system including the motherboard. 
     BACKGROUND 
     Typically, a user must remember to manually turn off a workstation before leaving the desk in order to save energy. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
         FIG. 1  is a block diagram of an embodiment of a computer control system. 
         FIG. 2  is a circuit diagram of the controlling module coupled to a video graphics array (VGA) connector and a north bridge chipset of  FIG. 1 . 
         FIG. 3  is a diagrammatic view of a VGA connector of a motherboard coupled to a VGA connector of a display of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrates details and features. The description is not to be considered as limiting the scope of the embodiments described herein. 
     A definition that applies throughout this disclosure will now be presented. 
     The term “comprising” means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in a so-described combination, group, series and the like. 
       FIG. 1  illustrates an embodiment of a computer control system. The computer control system can comprise a motherboard  10  and a display  20 . The motherboard  10  can comprise a north bridge chipset  104 , a basic input output system (BIOS)  108 , a VGA connector  102 , and a controlling module  106 . The controlling module  106  is electrically coupled to a VGA connector  202  of the display  20  through the VGA connector  102 . 
     In at least one the embodiment, the VGA connector  102  obtains a switch signal from the VGA connector  202 , and transmits the switch signal to the controlling module  106 . 
     In at least one the embodiment, the BIOS  108  can set three work modes of the computer, such as sleep mode, dormant mode, and shutdown mode. When the computer is placed in the sleep mode, the BIOS  108  sets the north bridge chipset  104  to output a sleep signal to the controlling module  106 . When the computer is placed in the dormant mode, the BIOS  108  sets the north bridge chipset  104  to output a dormant signal to the controlling module  106 . When the computer is placed in the shutdown mode, the BIOS  108  sets the north bridge chipset  104  to output a shutdown signal to the controlling module  106 . In at least one the embodiment, the controlling module  106  can comprise a sleep control circuit  1062 , a dormant control circuit  1064 , and a shutdown control circuit  1066 . 
     The sleep control circuit  1062  can obtain the switch signal from the VGA connector  102  and the sleep control signal from the north bridge chipset  104 . The sleep control circuit  1062  outputs a first mode signal to the north bridge chipset  104  according to the switch signal and the sleep control signal, the BIOS sets the north bridge chipset  104  to control the computer to be in a state of sleep when the north bridge chipset  104  obtains the first mode signal. 
     The dormant control circuit  1064  can obtain the switch signal from the VGA connector  102  and the dormant control signal from the north bridge chipset  104 . The dormant control circuit  1064  outputs a second mode signal to the north bridge chipset  104  according to the switch signal and the dormant control signal, the BIOS sets the north bridge chipset  104  to control the computer to be dormant when the north bridge chipset  104  obtains the second mode signal. 
     The shutdown control circuit  1066  can obtain the switch signal from the VGA connector  102  and the shutdown control signal from the north bridge chipset  104 . The sleep control circuit  1066  outputs a third mode signal to the north bridge chipset  104  according to the switch signal and the shutdown control signal, the BIOS sets the north bridge chipset  104  to control the computer to be shutdown when the north bridge chipset  104  obtains the third mode signal. 
     When the computer is sleeping, dormant, or shutdown, significant electrical consumption is saved compared to leaving the computer fully on. 
       FIG. 2  illustrates that the north bridge chipset  104  can comprise a sleep terminal S_SLP_S 3 #, a dormant terminal S_SLP_S 4 #, a shutdown terminal S_SLP_S 5 #, a boot terminal PWRBTN#IN, a general purpose input output (GPIO) terminal GPIO 1 -GPIO 3 . The VGA connector  102  can comprise an idle pin P 9 . 
     The sleep control circuit  1062  can comprise three field effect transistors (FETs) Q 1 -Q 3 . The gate G of the FET Q 1  is coupled to the sleep terminal S_SLP_S 3 # to obtain the sleep control signal from the north bridge chipset  104 , and the drain D of the FET Q 1  is coupled to the GPIO 1  terminal. The gate G of the FET Q 2  is coupled to the sleep terminal S_SLP_S 3 # to obtain the sleep control signal from the north bridge chipset  104 , the source S of the FET Q 2  is coupled to a dual power source+3VDUAL, and the drain D of the FET Q 2  is coupled to the gate G of the FET Q 3 . The source S of the FET Q 3  is coupled to the boot terminal PWRBTN#IN, and both the source S of the FET Q 1  and the drain D of the FET Q 3  are coupled to the idle pin P 9  of the VGA connector  102 . 
     The dormant control circuit  1064  can comprise three field effect transistors (FETs) Q 4 -Q 6 . The gate G of the FET Q 4  is coupled to the dormant terminal S_SLP_S 4 # to obtain the dormant control signal from the north bridge chipset  104 , and the drain D of the FET Q 4  is coupled to the GPIO 2  terminal. The gate G of the FET Q 5  is coupled to the dormant terminal S_SLP_S 4 # to obtain the dormant control signal from the north bridge chipset  104 , the source S of the FET Q 5  is coupled to the dual power source+3VDUAL, and the drain D of the FET Q 5  is coupled to the gate G of the FET Q 6 . The source S of the FET Q 6  is coupled to the boot terminal PWRBTN#IN, and both the source S of the FET Q 4  and the drain D of the FET Q 6  are coupled to the idle pin P 9  of the VGA connector  102 . 
     The shutdown control circuit  1066  can comprise three field effect transistors (FETs) Q 7 -Q 9 . The gate G of the FET Q 7  is coupled to the shutdown terminal S_SLP_S 5 # to obtain the shutdown control signal from the north bridge chipset  104 , and the drain D of the FET Q 7  is coupled to the GPIO 3  terminal. The gate G of the FET Q 8  is coupled to the shutdown terminal S_SLP_S 5 # to obtain the shutdown control signal from the north bridge chipset  104 , the source S of the FET Q 8  is coupled to the dual power source+3VDUAL, and the drain D of the FET Q 8  is coupled to the gate G of the FET Q 9 . The source S of the FET Q 9  is coupled to the boot terminal PWRBTN#IN, and both the source S of the FET Q 7  and the drain D of the FET Q 9  are coupled to the idle pin P 9  of the VGA connector  102 . 
       FIG. 3  illustrates that the VGA connector  202  can comprise an idle pin P 9 . The VGA connector  102  is electrically coupled to the VGA connector  202 . The idle pin P 9  of the VGA connector  102  is electrically coupled to the idle pin P 9  of the VGA connector  202 . 
     When the button of the display  20  is pressed, the VGA connector  102  obtains the switch signal with low level from the idle pin P 9  of the VGA connector  202 , and the VGA connector  102  transmits the switch signal to the controlling module  106 . 
     When the BIOS  108  sets the computer in the sleep mode, the sleep terminal S_SLP_S 3 # of the north bridge chipset outputs the sleep control signal to the sleep control circuit  1062 , the sleep control circuit  1062  starts working. When the computer is fully running, the sleep control signal output by the north bridge chipset  104  is at a high level state, and the FET Q 1  is turned on, both the FET Q 2  and the FET Q 3  are turned off. When the user leaves the computer, and the button of the display  20  is pressed, the VGA connector  102  obtains a switch signal with low level from the idle pin P 9  of the VGA connector  202 , and the source S of the FET Q 1  obtains the switch signal with the low level, as the FET Q 1  is turned on, the GPIO 1  terminal of the north bridge chipset  104  obtains the first mode signal with low level from the sleep control circuit  1062 , and the north bridge chipset  104  controls the computer to sleep. When the computer is sleeping, both the gate G of the FET Q 1  and the gate G of the FET Q 2  obtain a low level sleep control signal, the FET Q 1  is turned off, the FET Q 2  is turned on, and the FET Q 3  is turned on. When the user comes back to the computer, and the button of the display  20  is pressed, the idle pin P 9  of the VGA connector  102  transmits the switch signal with low level to the drain D of the FET Q 3 , and the FET Q 3  is turned on, the boot terminal PWRBTN#IN of the north bridge chipset  104  obtains the switch signal with low level, at the same time, the computer is woken up. 
     When the BIOS  108  sets the computer in the dormant mode, the dormant terminal S_SLP_S 4 # of the north bridge chipset outputs the dormant control signal to the dormant control circuit  1064 , the dormant control circuit  1064  starts working. When the computer is fully running, the dormant control signal output by the north bridge chipset  104  is at a high level, and the FET Q 4  is turned on, both the FET Q 5  and the FET Q 6  are turned off. When the user leaves the computer, and the button of the display  20  is pressed, the VGA connector  102  obtains a switch signal with low level from the idle pin P 9  of the VGA connector  202 , and the source S of the FET Q 5  obtains the switch signal with the low level, as the FET Q 4  is turned on, the GPIO 2  terminal of the north bridge chipset  104  obtains the second mode signal with low level from the dormant control circuit  1064 , and the north bridge chipset  104  controls the computer to be dormant. When the computer is dormant, both the gate G of the FET Q 4  and the gate G of the FET Q 5  obtain a low level dormant control signal, the FET Q 4  is turned off, the FET Q 5  is turned on, and the FET Q 6  is turned on. When the user comes back to the computer, and the button of the display  20  is pressed, the idle pin P 9  of the VGA connector  102  transmits the switch signal with low level to the drain D of the FET Q 6 , and the FET Q 6  is turned on, the boot terminal PWRBTN#IN of the north bridge chipset  104  obtains the switch signal with low level, at the same time, the computer is woken up. 
     When the BIOS  108  sets the computer in the shutdown mode, the shutdown terminal S_SLP_S 5 # of the north bridge chipset outputs the shutdown control signal to the shutdown control circuit  1066 , the shutdown control circuit  1066  starts working. When the computer is fully running, the shutdown control signal output by the north bridge chipset  104  is at a high level, and the FET Q 7  is turned on, both the FET Q 8  and the FET Q 9  are turned off. When the user leaves the computer host, and the button of the display  20  is pressed, the VGA connector  102  obtains a switch signal with low level from the idle pin P 9  of the VGA connector  202 , and the source S of the FET Q 8  obtains the switch signal with the low level, as the FET Q 7  is turned on, the GPIO 3  terminal of the north bridge chipset  104  obtains the third mode signal with low level from the shutdown control circuit  1066 , and the north bridge chipset  104  controls the computer to be turned off. When the computer is turned off, both the gate G of the FET Q 7  and the gate G of the FET Q 8  obtain a shutdown control signal with low level, the FET Q 7  is turned off, and the FET Q 8  is turned on, the FET Q 9  is turned on. When the user comes back to the computer, and the button of the display  20  is pressed, the idle pin P 9  of the VGA connector  102  transmits the switch signal with low level to the drain D of the FET Q 9 , and the FET Q 9  is turned on, the boot terminal PWRBTN#IN of the north bridge chipset  104  obtains the switch signal with low level, at the same time, the computer is woken up. 
     While the disclosure has been described by way of example and in terms of a preferred embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.