Abstract:
A control circuit and method for a ripple regulator system generate a ripple signal in-phase and synchronous with an inductor current of the ripple regulator system, and extract a ripple information proportional to the amplitude of the ripple signal. The ripple signal is used for triggering control in PWM signal generation to make the ripple regulator system have small ripples and better loop stability simultaneously. The ripple information is used to improve the output offset of the ripple regulator system that is caused by the ripple signal.

Description:
FIELD OF THE INVENTION 
     The present invention is related generally to a ripple regulator system and, more particularly, to a control circuit and method for a ripple regulator system. 
     BACKGROUND OF THE INVENTION 
     In a constant on time (COT) or hysteretic mode self-clocking DC-to-DC power converter system, generation of the pulse width modulation (PWM) signal relies on ripples of the output voltage to carry out triggering control. Large ripples are beneficial to loop stability; however, they may result in over specification conditions. On the contrary, small ripples could remain the system under specifications, while they are adverse to loop stability. Thus, it is a challenge to maintain loop stability with small output voltage ripples for design of the power converter system. 
     As shown in  FIG. 1 , a traditional COT ripple regulator system includes a high-side device Q 1  and a low-side device Q 2  connected to each other by a phase node Phs in series between a voltage input terminal Vin and a ground GND, a control circuit  10  to provide PWM signals UG and LG for controlling the high-side device Q 1  and the low-side device Q 2 , respectively, to regulate an inductor current IL to charge an output capacitor Co to generate an output voltage Vout, and voltage divider resistors R 1  and R 2  divide the output voltage Vout to generate a feedback voltage Vfb 1  for the control circuit  10 . In  FIG. 1 , the resistor R 3  represents the effective series resistance (ESR) of the output capacitor Co. In the control circuit  10 , an error comparator  14  compares the feedback voltage Vfb 1  with a reference voltage Vref to generate a comparison signal Sc, a PWM controller  12  triggers the PWM signal UG responsive to the comparison signal Sc, to control the high-side device Q 1 , and an inverter  16  inverts the PWM signal UG to generate the PWM signal LG for controlling the low-side device Q 2 . In the PWM controller  12 , a constant time generator  18  determines the constant time Ton of the PWM signal UG, and a logic controller  22  generates a triggering signal St responsive to the comparison signal Sc for a one shot circuit  20  to trigger the PWM signal UG. 
       FIG. 2  is a waveform diagram of the circuit shown in  FIG. 1  to illustrate operation of the COT ripple regulator system. Referring to  FIGS. 1 and 2 , at time t 1 , the feedback voltage Vfb 1  becomes lower than the reference voltage Vref, so the comparison signal Sc turns to low from high and as a result, the logic controller  22  asserts the triggering signal St to trigger the PWM signal UG, to turn on the high-side device Q 1  for a time period, i.e. the constant time Ton. During the high-side device Q 1  is on, the feedback voltage Vfb 1  increases, and then upon expiration of the constant time Ton, the high-side device Q 1  is turned off and the low-side device Q 2  is turned on, by which the feedback voltage Vfb 1  decreases. When the feedback voltage Vfb 1  again becomes lower than the reference voltage Vref, the high-side device Q 1  is turned on again for the constant time Ton. By working with such a cycle, the COT ripple regulator system regulates the output voltage Vout at a default value. 
     However, in the case that a ceramic capacitor is used as the output capacitor Co, due to the very small effective series resistance R 3  of the ceramic capacitor, the output voltage Vout and thereby the feedback voltage Vfb 1  will have very small ripples, even could be regarded as DC signals, causing the COT ripple regulator system almost impossible to operate stably. 
     SUMMARY OF THE INVENTION 
     An objective of the present invention is to provide a control circuit and method for a ripple regulator system to have small ripples and high loop stability simultaneously. 
     Another objective of the present invention is to provide a control circuit and method for improving the output offset of a ripple regulator system. 
     According to the present invention, a control circuit for a ripple regulator system includes an error comparator to compare a reference voltage with a feedback voltage related to the output voltage of the ripple regulator system to generate a comparison signal, a PWM controller to trigger a PWM signal responsive to the comparison signal to control an inductor current, a ripple generation circuit to provide a ripple signal in-phase and synchronous with the inductor current to be superposed to the reference voltage or the feedback voltage for improving the loop stability, and an offset cancellation circuit to extract a ripple information proportional to the amplitude of the ripple signal from the ripple generation circuit, to generate an offset cancellation signal for the error comparator to improve the offset of the output voltage caused by the ripple signal. 
     According to the present invention, a control method for a ripple regulator system includes comparing a reference voltage with a feedback voltage related to the output voltage of the ripple regulator system to generate a comparison signal for triggering a PWM signal to control an inductor current, generating a ripple signal in-phase and synchronous with the inductor current to be superposed to the feedback voltage or the reference voltage, and extracting a ripple information proportional to the amplitude of the ripple signal to generate an offset cancellation signal for improving the offset of the output voltage caused by the ripple signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objectives, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a circuit diagram of a traditional COT ripple regulator system; 
         FIG. 2  is a waveform diagram of the circuit shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram of an embodiment according to the present invention; 
         FIG. 4  is a waveform diagram of the circuit shown in  FIG. 3 ; 
         FIG. 5  is a circuit diagram of an embodiment for the ripple generation circuit shown in  FIG. 3 ; and 
         FIG. 6  is a circuit diagram of an embodiment for the offset cancellation circuit shown in  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 3  is a circuit diagram of an embodiment according to the present invention based on the circuit shown in  FIG. 1 , in which the output capacitor Co has a very small effective series resistance R 3  and thus makes the feedback voltage Vfb 1  have small ripples that can be regarded as a DC signal, as shown by the waveform  36  in  FIG. 4 . In addition to the PWM controller  12 , error comparator  14  and inverter  16  as those shown in  FIG. 1 , the control circuit  10  shown in  FIG. 3  further includes a ripple generation circuit  30  and an offset cancellation circuit  32 . According to the voltage at the phase node Phs, the ripple generation circuit  30  generates a ripple signal Vripple in-phase and synchronous with the inductor current IL for a positive input terminal of the error comparator  14 . In particular, the ripple signal Vripple is superposed to the feedback voltage Vfb 1  to generate a feedback voltage Vfb 2  having large ripples, as shown by the waveform  34  in  FIG. 4 , thereby preventing the loop instability that might otherwise be caused by the small effective series resistance R 3 . In other embodiments, the ripple signal Vripple may be superposed to the reference voltage Vref at the negative input terminal of the error comparator  14  instead. The COT ripple regulator system shown in  FIG. 3  uses the feedback voltage Vfb 2  to trigger the PWM signal UG, so when the loop is steady, as shown by the waveform  36  in  FIG. 4 , the feedback voltage Vfb 1  is not equal to the reference voltage Vref, but has a difference ΔV from Vref, where ΔV is equal to the amplitude of the ripple signal Vripple. This will cause an offset of the output voltage Vout departing from the default value, and this offset may be over specifications for systems requiring higher preciseness. In the circuit shown in  FIG. 3 , the offset cancellation circuit  32  generates an offset cancellation signal Soc according to a ripple information Sam of the ripple signal Vripple extracted from the ripple generation circuit  30 , for the error comparator  14  to improve the offset of the output voltage Vout caused by the ripple signal Vripple. The ripple information Sam is proportional to the amplitude ΔV of the ripple signal Vripple. The offset cancellation signal Soc may be provided to the positive or negative input terminal of the error comparator  14  to shift the feedback voltage Vfb 2  or the reference voltage Vref, or to adjust an internal offset parameter of the error comparator  14 . 
       FIG. 5  is a circuit diagram of an embodiment for the ripple generation circuit  30 , in which a resistor RA and a capacitor CA establish a low-pass filter  38  to filter off the high-frequency component of the voltage at the phase node Phs to generate a signal VA, a resistor RB and a capacitor CB establish a low-pass filter  40  to filter off an AC component of the signal VA to generate a signal VB, and a transconductance amplifier  42  amplifies the difference between the signals VA and VB to generate a transconductance current I 1 =gm×(VA−VB), where gm is the transconductance of the transconductance amplifier  42 . When the high-side device Q 1  is on and the low-side device Q 2  is off, the voltage at the phase node Phs is equal to the input voltage Vin and the capacitor CA is charged by the voltage source Vin through the high-side device Q 1  and the resistor RA. When the high-side device Q 1  is off and the low-side device Q 2  is on, the capacitor CA discharges to ground GND through the resistor RA and the low-side device Q 2 . Therefore, the signal VA has a triangular-like waveform and is in-phase and synchronous with the inductor current IL, the signal VB is the average of the signal VA, and the transconductance current I 1  is in-phase and synchronous with the inductor current IL. A resistor R 4  is connected between the error comparator  14  and the node Vfb 1 , by which the ripple signal Vripple is generated because of the transconductance current I 1 , and is superposed to the feedback voltage Vfb 1  to generate the feedback voltage Vfb 2 . 
     As shown in  FIG. 5 , the ripples of the ripple signal Vripple is generated by multiplying the difference between the signals VA and VB by gm×R 4 . Since R 4  is constant, the offset caused by the ripple signal Vripple can be reduced by sending the information about the maximum of |gm×(VA−VB)| to the offset cancellation circuit  32 .  FIG. 6  is a circuit diagram of an embodiment for the offset cancellation circuit  32 , in which a current source  44  provides an offset current I 2 =gm×VF according to the ripple information Sam, where VF is proportional to the maximum of |VA−VB|, and a resistor RF is connected between the negative input terminal of the error comparator  14  and the reference voltage terminal Vref, to generate the offset cancellation signal Soc responsive to the offset current I 2  to shift the reference voltage Vref, thereby reducing the offset of the output voltage Vout. Referring to  FIGS. 4-6 , the ripples of the ripple signal Vripple has the magnitude equal to gm×R 4 ×(VA−VB), so the offset ΔV between the feedback voltage Vfb 1  and the reference voltage Vref is equal to the maximum of |0.5×gm×R 4 ×(VA−VB). If the offset cancellation signal Soc=I 2 ×RF=ΔV, the offset of the output voltage Vout can be fully eliminated. 
     While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.