Abstract:
A level-shifting signal buffer contains a totem pole arrangement of MOS transistors connected to an output thereof and a control circuit that drives the totem pole arrangement of MOS transistors in a preferred manner so that none of the signals across the MOS transistors exceed predetermined limits that may damage the MOS transistors. A preferred signal buffer may include a PMOS pull-up transistor and an NMOS pull-down transistor arranged within a transistor totem pole. This transistor totem pole extends between a first power supply signal line that receives a first power supply signal (e.g., Vdd ext ) and a reference signal line that receives a reference signal (e.g., GND). The PMOS pull-up transistor may be configured to support a maximum gate-to-drain voltage which is less than a difference in voltage between the first power supply signal and the reference signal. The control circuit, which is responsive to a data input signal, drives gate electrodes of the PMOS pull-up transistor and the NMOS pull-down transistor with signals that cause an output of the transistor totem pole to swing from a voltage of the first power supply signal line to a voltage of the reference signal line during a pull-down time interval, while simultaneously maintaining a gate-to-drain voltage of the PMOS pull-down transistor within the maximum gate-to-drain voltage throughout the pull-down time interval.

Description:
REFERENCE TO PRIORITY APPLICATION 
     This application claims priority to U.S. Provisional Application Serial No. 60/263,009, filed Jan. 19, 2001, the disclosure of which is hereby incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to integrated circuit devices and methods of operating same, and more particularly to integrated circuit signal buffers and methods of operating integrated circuit signal buffers. 
     BACKGROUND OF THE INVENTION 
     Conventional signal buffers frequently include CMOS inverter stages that drive an output signal line rail-to-rail, from a lower reference potential (e.g., GND) to a power supply voltage (e.g., Vdd). Attempts to use such signal buffers at higher power supply voltages frequently require the development and use of MOS transistors that can support correspondingly higher gate-to-drain, gate-to-source and drain-to-source voltages without failure. Accordingly, signal buffers are frequently designed to include MOS transistors that can support the maximum anticipated power supply voltage for a designated application. Unfortunately, the characteristics of MOS transistors capable of supporting higher voltages may not be acceptable for other applications which do not require operation under relatively high voltages, including applications in other portions of an integrated circuit chip that operate at lower internal power supply voltages. To address these issues, level shifting circuits have been developed to “insulate” MOS transistors from higher external power supply voltages by reducing on-chip voltages. However, such circuits may not allow for changes in an external power supply voltage to occur to meet a particular application and/or may not adequately shield all MOS transistors from high voltages. 
     Thus, notwithstanding the use of such level shifting circuits, there continues to be need to develop signal buffers that have excellent performance characteristics and can be operated at a plurality of different power supply voltages without failure. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention includes a level-shifting signal buffer that contains a totem pole arrangement of MOS transistors connected to an output thereof and a control circuit that drives the totem pole arrangement of MOS transistors in a preferred manner so that signals across the MOS transistors will not exceed limits that may seriously damage the MOS transistors. A preferred signal buffer may include a PMOS pull-up transistor and an NMOS pull-down transistor arranged within a transistor totem pole. This transistor totem pole extends between a first power supply signal line that receives a first power supply signal (e.g., Vdd ext ) and a reference signal line that receives a reference signal (e.g., GND). The PMOS pull-up transistor may be configured to support a maximum gate-to-drain voltage which is less than a difference in voltage between the first power supply signal and the reference signal. The control circuit, which is responsive to a data input signal, drives gate electrodes of the PMOS pull-up transistor and the NMOS pull-down transistor with signals that cause an output of the transistor totem pole to swing rail-to-rail from a voltage of the first power supply signal line to a voltage of the reference signal line during a pull-down time interval, while simultaneously maintaining a gate-to-drain voltage of the PMOS pull-down transistor within the maximum gate-to-drain voltage throughout the pull-down time interval. 
     An additional embodiment includes a level-shifting signal buffer comprising a CMOS inverter configured as a first totem pole arrangement of at least two PMOS transistors connected in series between a first power supply signal line and an output of the CMOS inverter and at least two NMOS transistors connected in series between the output and a reference signal line. A control circuit is also provided that drives the gate electrodes of the at least two PMOS transistors and the at least two NMOS transistors, in response to a data input signal (IN), a first bias signal (PG) having a magnitude that sets a minimum voltage to which a gate electrode of one of the at least two PMOS transistor is driven, a first power supply signal (Vdd ext ) on the first power supply signal line and a second power supply signal (Vdd int ) having a magnitude less than a magnitude of the first power supply signal. The magnitude of the first bias signal (PG) may vary as a function of the magnitude of the first power supply signal. 
     According to this embodiment, the first bias signal (PG) has a magnitude that sets a first minimum voltage to which a gate electrode of an uppermost PMOS transistor in the CMOS inverter is driven and also sets a second minimum voltage to which a gate electrode of a lowermost PMOS transistor in said CMOS inverter is driven. The control circuit may comprise a first PMOS bias transistor and the first minimum voltage may equal a sum of the magnitude of the first bias signal (PG), a magnitude of a threshold voltage (V TP ) of the first PMOS transistor and a magnitude of a reference signal on the reference signal line. The control circuit may also comprise a second PMOS bias transistor and the second minimum voltage may equal a sum of the magnitude of the first bias signal, a magnitude of a threshold voltage of the second PMOS transistor and a magnitude of a reference signal on the reference signal line. The uppermost PMOS transistor and the lowermost NMOS transistor in the CMOS inverter may also be driven by respective inverters. In particular, a first inverter may be provided that is powered by the first power supply signal and has an output electrically coupled to a gate electrode of the uppermost PMOS transistor. The first inverter may be driven by a level shift circuit that is responsive to the data input signal and first and second bias signals (PG and NG). A second inverter may also be provided that is powered by the second power supply signal and has an output electrically coupled to a gate electrode of a lowermost NMOS transistor. 
     A preferred level shift circuit comprises a second totem pole arrangement of two PMOS and two NMOS transistors arranged in an alternating sequence with a lowermost NMOS transistor and an uppermost PMOS transistor. The level shift circuit also comprises a pair of cross-coupled PMOS transistors, with a gate electrode of one of the PMOS transistors in the cross-coupled pair being electrically connected to a gate electrode of the uppermost PMOS transistor in the second totem pole. One of the PMOS transistors in the second totem pole is responsive to the first bias signal (PG) and is positioned within a pull-down path therein and one of the NMOS transistors in the second totem pole is responsive to the second bias signal (NG). The level shift circuit may also include a third totem pole arrangement of two PMOS and two NMOS transistors arranged in an alternating sequence and a fourth totem pole arrangement of two PMOS and two NMOS transistors arranged in an alternating sequence, with both the third and fourth totem poles having a lowermost NMOS transistor and an uppermost PMOS transistor. Based on this configuration, the lowermost NMOS transistor in the third totem pole may be responsive to a complementary data input signal ({overscore (IN)}) and the lowermost NMOS transistor in the fourth totem pole may be responsive to the data input signal (IN). 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an electrical schematic of a signal buffer according to a preferred embodiment of the present invention. 
     FIG. 2 is an electrical schematic of a preferred level shift circuit that may be used in the signal buffer of FIG.  1 . 
     FIG. 3 is a graph that illustrates the voltages of a plurality of signals (Vdd int , NG, PG, PG+|V TP |), which vary in relation to a magnitude of an “external” power supply signal Vdd ext . 
     FIG. 4 is an electrical schematic of a signal buffer according to another preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Signal lines and signals thereon may be referred to by the same reference characters. Like numbers refer to like elements throughout. 
     Referring now to FIG. 1, a level-shifting signal buffer  10  according to a preferred embodiment of the present invention will be described. As illustrated, the signal buffer  10  is powered at two levels: Vdd int  and Vdd ext , where Vdd int ≦Vdd ext . In particular, the level Vdd ext , which may be treated as an “external” power supply voltage that is generated external to an integrated circuit chip, is typically higher than the level Vdd int , which may be treated as an “internal” power supply voltage that is generated by an integrated circuit chip containing the signal buffer  10 . Alternatively, both Vdd ext  and Vdd int  may be generated external to the integrated circuit chip or internal to the integrated circuit chip. According to a preferred aspect of the illustrated signal buffer  10 , the following relationship can be satisfied: Vdd int ≦Vdd ext ≦ 2 Vdd int . For example, circuits and devices typically designed to operate within a 3 volt part may be used within a 5 volt design. The signal buffer  10  preferably includes a CMOS inverter stage and a control circuit  20  that drives the CMOS inverter stage and is responsive to a data input signal IN. The control circuit  20  may comprise first and second inverters INV 1  and INV 2  and PMOS biasing transistors P 3  and P 4  which may be commonly connected at node A to a current source(s) (shown as a 1 microamp current source). The control circuit  20  also preferably comprises a level shift circuit  30  that is responsive to the data input signal and a pair of bias signals PG and NG. As illustrated by FIG. 3, these bias signals PG and NG may have voltage characteristics that vary as the magnitude of Vdd ext  varies. For example, the magnitude of bias signal NG may increase with increasing Vdd ext  up to a first limit and the magnitude of bias signal PG may increase from a lower level (e.g., 0 volts) after Vdd ext  exceeds a threshold level. 
     As illustrated, the CMOS inverter stage of FIG. 1 is configured as a first totem pole arrangement of two PMOS transistors P 1  and P 2 , connected in series between a first power supply signal line Vdd ext  and an output (OUT) (i.e., the “pull-up” path), and two NMOS transistors N 1  and N 2  connected in series between the output and the reference signal line (i.e., the “pull-down” path). As described herein with respect to the preferred embodiments, the reference signal line is treated as a ground signal line (GND) having a voltage of 0 volts, however, as will be understood by those skilled in the art, the reference signal line may be held at a non-zero reference voltage. The CMOS inverter stage may also comprise more than two PMOS transistors in the pull-up path and more than two NMOS transistors in the pull-down path. These MOS transistors in the pull-up path and pull-down path may be designed and manufactured to operate in a circuit environment which does not typically sustain voltages as high as Vdd ext . For example, the MOS transistors may be designed using a process technology and ground rules that result in devices capable of supporting a maximum gate-to-drain, gate-to-source and/or source-to-drain voltage which may be no greater than Vdd int , where Vdd int  may be substantially lower than Vdd ext . 
     As described more fully hereinbelow, the CMOS inverter stage operates to provide an output signal OUT that swings from a logic 0 level of 0 volts (i.e., GND) to a logic 1 level equal to Vdd ext  and vice versa without exposing any of the MOS transistors in the first totem pole arrangement to an excessive voltage. In particular, assuming ideal device characteristics, when the output signal line OUT is pulled to a logic 0 level by operation of the control circuit  20 , the gate-to-source and gate-to-drain voltages across NMOS transistors N 1  and N 2  become equal to Vdd int . This state of the output signal line OUT also establishes the drain voltage of PMOS transistor P 1  (and the source voltage of PMOS transistor P 2 ) at a level equal to (PG+|V TP |+|V TP |), where V TP  designates the threshold voltage of PMOS transistor P 4  and PMOS transistor P 2 . The gate electrode of PMOS transistor P 2  will also be set at a minimum voltage of (PG+|V TP |) and the source of PMOS transistor P 1  will be set at Vdd ext . For simplicity of explanation, the threshold voltages of all the illustrated PMOS transistors are equal to V TP  and the threshold voltages of all the illustrated NMOS transistors are equal to V TN . 
     In contrast, when the output signal line OUT is pulled to a logic 1 level equal to Vdd ext ,the drain-to-gate voltage across NMOS transistor N 1  will equal (Vdd ext −Vdd int ) and the drain of NMOS transistor N 2  will be pulled up to a maximum voltage of (Vdd int −V TN ), where V TN  is the threshold voltage of NMOS transistor N 1 . Accordingly, neither the establishment of a logic 0 voltage nor a logic 1 voltage of Vdd ext  at the output OUT of the signal buffer  10  results in an excessive voltage across any of the transistors in the CMOS inverter stage, even though these transistors may be nominally rated for a part operating at a maximum power supply voltage of Vdd int . 
     Referring still to FIG. 1, the receipt of a logic 1 input signal IN at a voltage Vdd int  will operate to turn off NMOS transistor N 2  by causing the output of the second inverter INV 2  to pull low, and will also operate to turn on PMOS transistor P 1 . As described more fully hereinbelow with respect to FIG. 2, a logic 1 input signal IN will result in the generation of a logic 1 signal at the output LSOUT of the level shift circuit  30 . This logic 1 signal at the output LSOUT will have a voltage equal to Vdd ext  and will drive the input of the first inverter INV 1  to a logic 1 level. The receipt of a logic 1 input signal by the first inverter INV 1  will cause the output of the first inverter INV 1  to be pulled down to a logic 0 level. Because the reference terminal of the first inverter INV 1  is connected to node A, the logic 0 level at the output of the first inverter will have a minimum voltage equal to PG+|V TP |. This logic 0 level will operate to turn on PMOS pull-up transistor P 1 . Although not shown, the “substrate” or “well” terminal of PMOS transistor P 1  (and all other PMOS transistors) may be tied to Vdd ext .Based on this configuration of the control circuit  20 , the signal buffer  10  of FIG. 1 operates as a non-inverting signal buffer. 
     Referring now to FIGS. 2-3, the operation of a preferred level shift circuit  30  will now be described. As illustrated, the level shift circuit  30  includes a second totem pole arrangement of alternating PMOS and NMOS transistors at an output stage thereof. The second totem pole includes PMOS transistors P 10  and P 5  and NMOS transistors N 8  and N 3 , with PMOS transistor P 10  in the pull-up path and NMOS transistors N 8  and N 3  and PMOS transistor P 5  in the pull-down path. The level shift circuit  30  also includes a third totem pole arrangement of alternating PMOS and NMOS transistors and a fourth totem pole arrangement of alternating PMOS and NMOS transistors. The third totem pole includes PMOS transistors P 7  and P 9  and NMOS transistors N 5  and N 7 . The fourth totem pole includes PMOS transistors P 6  and P 8  and NMOS transistors N 4  and N 6 . The level shift circuit  30  also includes a third inverter INV 3  which receives the data input signal IN and drives the gate electrodes of NMOS transistors N 7  and N 3  with a complementary data input signal ({overscore (IN)}). 
     As illustrated by the preferred circuit of FIG.  2  and the voltage graph of FIG. 3, the first bias signal PG (“P” gate signal), which may be generated by a bias generating circuit (not shown), and the PMOS transistors P 8 , P 9  and P 5  operate to protect the upper NMOS and PMOS transistors in the second, third and fourth totem poles (i.e., NMOS transistors N 4 , N 5  and N 8  and PMOS transistors P 6 , P 7  and P 10 ) from excessive voltages and also set up the minimum logic 0 voltage to which the output LSOUT can be pulled down to. Likewise, the second bias signal NG (“N” gate signal), which may be generated by the bias generating circuit, and the NMOS transistors N 4 , N 5  and N 8  operate to protect the lower NMOS and PMOS transistors in the second, third and fourth totem poles (i.e., PMOS transistors P 8 , P 9  and P 5  and NMOS transistors N 6 , N 7  and N 3 ). The level shift circuit  30  performs a level shift function by converting an input signal IN having a voltage swing between 0 and Vdd int  into an output signal LSOUT having a voltage swing between PG+|V TP | and Vdd ext . 
     Based on the configuration of the illustrated level shift circuit  30  of FIG. 2, the receipt of a logic 1 data input signal IN will cause NMOS transistor N 6  to turn on. The biasing of NMOS transistor N 4  and PMOS transistor P 8  at levels illustrated by FIG. 3 will also cause PMOS transistor P 7  and PMOS pull-up transistor P 10  to turn on as their gate electrodes are pulled low by the turn on of NMOS transistor N 6 . In particular, the gate electrode of PMOS pull-up transistor P 10  will be pulled down to a minimum voltage equal to PG+|V TP | (based on the protective clamping provided by the protective PMOS transistor P 8 ). Alternatively, the receipt of a logic 0 data input signal IN will cause NMOS transistors N 7  and N 3  to turn on. When NMOS transistor N 7  turns on, the gate electrode of PMOS transistor P 6  is pulled low and the gate electrode of PMOS pull-up transistor P 10  is pulled high to Vdd ext . This action will enable the output LSOUT to be pulled low to a minimum voltage of PG+|V TP |. Here, the minimum voltage at the output LSOUT is set by PMOS transistor P 5 , which is provided within the pull-down path of the second totem pole. Accordingly, the preferred level shift circuit  30  of FIG. 3 not only performs a level shift function on the data input signal IN, it also includes protection circuitry that enables the use of MOS transistors having lower nominal ratings. 
     Referring now to FIG. 4, a signal buffer  40  according to another embodiment of the present invention includes a CMOS inverter stage having a pull-up path defined by at least an uppermost PMOS transistor (shown as P 1 ) and a lowermost PMOS transistor (shown as P 2 ) and a pull-down path defined by an uppermost NMOS transistor (shown as N 1 ) and a lowermost NMOS transistor (shown as N 2 ). The signal buffer  40  includes a control circuit  50  that drives the gate electrodes of the transistors in the CMOS inverter. As illustrated, the control circuit  50  may include a plurality of inverters (INV 1  and INV 2 ) and additional circuitry that operates as a plurality of voltage sources (shown as V 1 , V 2  and V 3 ) when viewed from the standpoint of a Thevenin equivalent circuit. A first voltage source V 1  may be tied to a reference terminal of the first inverter (thereby setting the minimum voltage to which the output of the first inverter may be pulled down to), a second voltage source V 2  may be tied to a gate electrode of a lowermost PMOS transistor P 2  in the pull-up path, and a third voltage source V 3  may be tied to a gate electrode of an uppermost NMOS transistor N 1  in the pull-down path. A gate electrode of the uppermost PMOS transistor P 1  is driven by a first inverter (INV 1 ) and a gate electrode of the lowermost NMOS transistor N 2  is driven by a second inverter (INV 2 ). The second inverter INV 2  receives a data input signal (IN) and the first inverter INV 1  receives a modified data input signal (IN*). This modified data input signal IN* may constitute an upwards level shifted version of the data input signal IN. For example, in the event the data input signal IN swings between a logic 0 level equal to a ground reference potential (GND) and a logic 1 level equal to a lower power supply voltage (e.g., Vdd int ), the modified data input signal IN* may swing between a logic 0 level equal to V 1  volts and a logic 1 level equal to a higher power supply voltage (e.g., Vdd ext ). The maximum voltage swing associated with the data input signal IN need not equal the maximum voltage swing associated with the modified data input signal IN*. 
     Based on the illustrated configuration of the control circuit  50  of FIG. 4, the minimum voltage to which the source of PMOS transistor P 2  (and the drain of PMOS transistor P 1 ) will be pulled down to during a pull-down time interval when the output OUT is at the reference voltage (e.g., GND), is (V 2 +|V TP-P2 |), where V TP-P2  is the threshold voltage of PMOS transistor P 2 . Moreover, the maximum voltage to which the drain of NMOS transistor N 2  (and the source of NMOS transistor N 1 ) will be pulled up to during a pull-up time interval when the output OUT is at the higher power supply voltage of Vdd ext , is V 3 −V TN-N1 , where V TN-N1  is the threshold voltage of NMOS transistor N 1 . According to a preferred aspect of the embodiments of the present invention, the voltage levels of V 1 , V 2  and V 3  are preferably held at values which preclude an excessive gate-to-drain (or gate-to-source) voltage from appearing across any of the NMOS or PMOS transistors in the inverter, even where the maximum gate-to-drain (or maximum gate-to-source) voltage that can be supported by the MOS transistors are substantially less than Vdd ext  (e.g., ½VDD ext ). 
     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.