Abstract:
A pipelined analog-to-digital converter in which signal value samples are represented differentially by pairs of charges and which uses charge-coupled-devices (CCDs) for delay and arithmetic operations on the charges is presented. In the pipeline, each successive stage resolves an equal or smaller charge difference. After a certain number of pipeline stages, the common-mode component of the signal-charge pair is reduced. The pipeline stages following this common-mode-charge reduction stage have a reduced charge capacity and size, allowing more sensitive charge comparison. The result is improved A/D converter resolution and reduced power consumption.

Description:
STATEMENTS REGARDING FEDERALLY SPONSORED RESEARCH 
   This invention was made with government support under Contract No. F19628-00-C-0002 awarded by the Air Force. The government has certain rights in the invention. 

   CROSS REFERENCE TO RELATED APPLICATIONS 
   Not Applicable. 
   FIELD OF THE INVENTION 
   The present invention relates generally to analog-to-digital converters and more specifically to pipelined analog-to-digital converters employing charge-coupled devices (CCDs). 
   BACKGROUND OF THE INVENTION 
   Pipelined charge-domain analog-to-digital converters (ADCs) are known. In these ADCs, a sampled analog signal is represented as a sequence of charges or of charge-pair differences. The signal charges are stored, transported and processed in one or more CCD shift registers. In addition to charge storage and shifting, these charge-domain ADCs employ the operations of charge splitting, charge comparison and charge merging (addition) to perform analog-to-digital conversion. 
   As is known in the art, analog-to-digital converters (ADCs) convert a signal in analog format to a signal in digital format. Conventional ADC circuits can have a variety of circuit architectures each of which has certain concomitant benefits and disadvantages. Known ADC architectures include pipeline, sigma-delta, cyclic, flash, successive approximation, and dual-slope. Each architecture is generally applicable to a limited operating range. That is, each of these architectures has strengths and weaknesses that make them more amenable to working in certain frequency and resolution ranges. 
   Flash ADCs, for example, provide the highest available sampling rates, but at relatively limited resolution and at relatively high power consumption. At the other extreme, sigma-delta ADCs provide very high resolution, but relatively low output sampling rate. The general class of pipeline ADCs is particularly suitable for simultaneous operation at moderate-to-high resolution and moderate-to-high sampling rate. Most pipeline ADCs are implemented using switched-capacitor circuit techniques which employ op-amps. The op-amps limit circuit speed and consume considerable power. Charge-domain (CCD-based) pipeline ADCs eliminate the need for op-amps, and thus provide reduced power consumption and potentially smaller circuit area. 
   Prior-art charge-domain (CCD-based) pipelined analog-to-digital converters (ADCs) have been limited in precision to approximately 10 bits. A principal reason for this limit is the difficulty of precisely and non-destructively comparing charges in CCD shift registers. Such comparison is performed using floating gates, in which the charges to be compared induce voltage changes on overlying, temporarily floating gates of the CCDs; these voltage changes are then sensed by a voltage comparator circuit. This floating-gate charge-comparison method is subject to errors due to parasitic capacitances, capacitance mismatches, capacitance-precharge or “kTC” noise, and comparator circuit noise and voltage offset. These error causes are all related to the fact that various capacitances, both intrinsic and parasitic to the CCD, limit the available magnitude and accuracy of the differential voltage signal induced by a given differential charge on the floating gates. 
   Various circuit methods such as comparator auto-zeroing can alleviate these problems, but they generally reduce operating speed, and may increase power dissipation. Similarly, serial comparison, in which the charge packets to be compared are presented in sequence to the same floating gate, can improve charge comparison accuracy, but this method reduces the sample rate of the CCD to half the clock rate, again imposing a reduction of operating speed. 
   SUMMARY OF THE INVENTION 
   A pipelined analog-to-digital converter in which signal value samples are represented differentially by pairs of charges and which uses charge-coupled-devices (CCDs) for storage, transport, and arithmetic operations on the charges is presented. In the pipeline, each successive stage resolves an equal or smaller charge difference. After a certain number of pipeline stages, the common-mode component of the signal-charge pair is reduced. The pipeline stages following this common-mode-charge reduction stage have a reduced charge capacity and size, allowing more sensitive charge comparison. The result is improved A/D converter resolution and reduced power consumption. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram of a prior art device; 
       FIG. 2  is a graph of two charge streams of a prior art device; 
       FIG. 3  is a block diagram of the present invention; 
       FIG. 4  is a graph of two charge streams of the present invention; 
       FIG. 5  is a block diagram of a multiplexed embodiment of the present invention; and 
       FIG. 6  is a block diagram of a further embodiment of a multiplexed device. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In order to make clear the advantages of the present invention, a brief description of the operation of a prior-art charge-domain pipelined ADC is first described. A typical pipeline stage in such an ADC is shown in  FIG. 1 . In this schematic representation, charge-transfer paths are shown as heavy lines with arrowheads, and normal (wired) connections are shown as single lines. 
   The details of the CCD structures are not important to this discussion and are not shown. Likewise the number of storage gates per pipeline stage can be varied from the number shown. The pipeline shown in this example has parallel CCD registers for the two components of the signal-charge pair. ADCs based on similar pipelines in which the signal-charge pair is interleaved in a single CCD register are also within the scope of the present invention. 
   Referring now to  FIG. 1  a pipeline stage  1  operates as follows. A differential signal-charge pair Q Pin    2  and Q Min    4  enter the stage as inputs either from another pipeline stage or from a signal source. Elements  6 ,  8 ,  12 ,  14 ,  16 , and  18  represent storage gates within CCD shift registers, under which charges can be stored. Storage gates  6  and  8  are floating gates. A characteristic of floating gates is that after being pre-charged to a voltage attractive to signal charges, they are disconnected from the voltage source and left electrically floating. When the two signal charges are shifted under floating gates  6  and  8 , they induce proportional voltage changes on gates  6  and  8 . The resulting voltages  6   a  and  8   a  are compared by voltage comparator  10 . The decision of the comparator constitutes the digital output b out  from this stage (not shown) and indicates which of the two signal charges Q Pin    2  and Q Min    4  is larger. Two nominally equal reference charges are stored under gates  12  and  14 . As the input charge pair is shifted to gates  16  and  18  respectively, the comparator decision directs the addition of one of the reference charges to the smaller member of the pair. In this instance the signal charge  8   b  at gate  8  is smaller than the signal charge  6   b  at gate  6 , thus the reference charge from gate  14  is added to the signal charge  8   b  from gate  8  at gate  18 . The unused reference charge from gate  12  is discarded. If the signal charge  6   b  at gate  6  were smaller than the signal charge  8   b  at gate  8 , then the reference charge from gate  12  would have been added to the signal charge  6   b  from gate  6  at gate  16 . The unused reference charge from gate  14  would have been discarded. The charge pair resulting from these comparison and addition operations exits gates  16  and  18  as outputs Q Pout    20  and Q Mout    22  respectively. 
   This process is repeated in successive pipeline stages. The reference charge is ordinarily smaller at each successive stage of the pipeline. The reference charge reduction is typically by a factor of two per stage, yielding binary coding of the digital output from the comparators. 
   Referring now to  FIG. 2 , the sequence of values taken on by a signal-charge pair Sig 1  and Sig 2  as it progresses through four pipeline stages of the type described in  FIG. 1  is shown. As shown in  FIG. 2 , charges Sig 1  and Sig 2  are provided as inputs to a first stage. As described above, the charges are compared and a reference charge is added to the smaller of the two charges. At stage  1 , Sig 2  has a reference charge added to its value  24  to become the value  26 , and Sig 1  retains its value  28  unchanged. At each stage the reference signal is approximately half the value of the reference signal of the prior stage. At stage  2  the two signals are again compared and a reference charge is added to the smaller of the two signals. In this case, Sig 2  again has a reference charge added thereto to produce the charge level  30 ; again, Sig 1  is unchanged. At stage  3 , Sig 1  is now the smaller of the two signals, so it has a reference charge added thereto to produce a signal having a level  32 . This time it is Sig 2  which retains its value unchanged at level  30 . At stage  4 , the two signals are compared and Sig 1 , again being smaller, has a reference charge added thereto in order to produce the output charge level  34 , while Sig 2  again is unchanged. As is readily apparent, the two signals converge over a number of stages. 
   The charge output from a stage is changed in two ways from the charged provided at the input to the stage. First, the smaller of the charges entering the stage is increased by the amount of added reference charge. Over a number of stages, this effect causes the two charges to converge. Second, the common-mode charge, that is, the average of the two signal charges, is increased by half the added reference charge. When Q Pin &gt;Q Min , then (as illustrated in  FIG. 1 ):
 
Q Pout =Q Pin   (Equation 1)
 
 Q   Mout   =Q   Min   +Q   REF   (Equation 2)
 
and the output common-mode charge is given by
 
 Q   CMout =( Q   Pout   +Q   Mout )/2=( Q   Pin   +Q   Min   +Q   REF )/2 =Q   CMin   +Q   REF /2  (Equation 3)
 
Both effects are visible in the graph of  FIG. 2 . The result of these effects is that over several stages, the difference between charges to be compared becomes smaller, while the common-mode charge becomes larger. Both effects degrade charge comparison precision. The increasing common-mode charge exacerbates the effect of floating-gate capacitance mismatch, while requiring relatively large CCD capacitance for its storage. The shrinking charge difference results in smaller induced voltage difference, exacerbating the effects of comparator offset and noise, as well as kTC noise. Because of the necessity of accommodating the common-mode charge, the floating gate capacitance cannot be reduced; otherwise, such reduction could be used to increase the sensitivity of charge comparison.
 
   In the invention herein disclosed, the operation of common-mode charge reduction is applied to alleviate these performance limits, resulting in an increase in ADC resolution. 
   Referring now to  FIG. 3 , a four-stage pipelined charge-domain ADC employing the method of this invention is shown. Each ADC stage  36 ,  38 ,  40  and  42  may be similar to the general type shown in  FIG. 1 . A common-mode (CM) reduction stage  44  is inserted between ADC stages  38  and  40 . Additional embodiments of this invention could involve more stages both before and after the CM reduction stage  44 . The resulting architecture can be described as a first block  46  of ADC pipeline stages, followed by the CM reduction stage  44 , which is in turn followed by a second block  48  of pipelined stages. 
   Because the differential charge at the output of stage  38  has been reduced relative to the differential input charge to stage  36  (as described above), the differential charge can be supported by a smaller common-mode charge than is needed at the input of stage  36 . The CM reduction stage  44  removes a nominally identical charge from each of the charge packets passing through it (i.e., an equal amount from each member of the signal-charge pair, and the same amount from each sequential pair.) Thus the outgoing signal-charge pair, as supplied to the input of stage  40 , has a reduced common-mode charge relative to the output of stage  38 , while maintaining the same differential charge. Because of this reduced common-mode charge, downstream CCD stages  40  and  42  can be reduced proportionately in size and capacitance. The reductions in floating-gate capacitance C FG  and in the common-mode charge alleviate the resolution-limiting effects listed above. Specifically because of smaller C FG , the sensitivity of differential floating-gate voltage to differential charge is increased. Additionally, since the common-mode charge is reduced, any C FG  mismatch produces a reduced apparent voltage offset. Further, because C FG  is reduced, the kTC pre-charge noise is correspondingly reduced. Due to the increased charge-to-voltage conversion sensitivity mentioned above, the effect of voltage noise and offset in the comparator translates to smaller charge errors. 
   Referring now to  FIG. 4 , the sequence of values taken on by a signal-charge pair Sig 1  and Sig 2  as it progresses through the first three stages,  36 ,  38  and  44 , of the circuit of  FIG. 3  is shown. As shown in  FIG. 4 , charges Sig 1  and Sig 2  are provided to a first stage  36 . As described above, the charges are compared and a reference charge is added to the smaller of the two charges. At stage  36 , Sig 2  has a reference charge added to its value at  50  to become the value at  52 , while Sig 1  is left unchanged with its value at  54 . At each stage the reference charge is approximately half the value of the reference signal of the prior stage. At stage  38  the two charges are compared and a reference charge is added to the smaller. In this case, Sig 2  again has a reference charge added thereto to produce the charge level  56 ; again, Sig 1  is unchanged. At the next stage,  44 , a common mode reduction operation is performed, resulting in the Sig 1  signal being reduced to the value shown at  58 . Similarly, Sig 2  has been reduced by a same amount resulting in the value at  60 . As shown, the difference between the signal levels  58  and  60  at the output of the common mode reduction stage  44  is the same as the difference between the signal levels  56  and  54  at the output of stage  38 . At the same time, the common-mode value of the signal pair, equal to the average of levels  58  and  60 , is reduced. 
   The description above shows how the disclosed invention makes more-sensitive charge comparison possible, thus improving ADC resolution. However, in a charge-domain pipeline ADC with two times reference scaling between stages (as is required in order to directly generate a binary output code), a further disadvantage remains. In order for the overall A/D conversion to be accurate to one least-significant bit (LSB), each comparison must be accurate to one LSB. If an early comparison in the pipeline is in error, then the downstream stages cannot correct for the error, even if their comparison resolution is better than that of earlier stages. The disclosed method and apparatus as described so far, however, improves the resolution of stages in the second block  48 , but not the resolution of stages in the first block  46 . 
   The resolution of the overall ADC can be improved to the level of the second block  48  by using a technique common in sub-ranging ADCs. The stage-to-stage reference-charge scaling is interrupted at the CM reduction stage, and the following stage ( 40  in  FIG. 3 ) has a larger reference charge than it would with pure-binary scaling. Typically, the reference charge for stage  40  would be twice its value in a pure binary sequence (i.e., equal to the reference charge in stage  38 ). This technique enables stages  40  and  42  to correct for errors in previous stages of up to the reference value of stage  38 . Thus the first block  46  of the ADC need only have comparisons accurate to the LSB of that block, not the LSB of the whole ADC. The improved resolution of block  48  thus applies to the entire A/D converter. This technique requires, in effect, the addition of one extra stage after the CM reduction stage—that is, stage  40 &#39;s output bit represents the same magnitude as stage  38 &#39;s. It also requires added logic to merge the two sub-range results from blocks  46  and  48 . 
   The resulting architecture comprises a combination of the sub-ranging technique with the CM reduction stage. This architecture constitutes a sub-ranging ADC in which each block is itself a pipelined sub-ADC. It is herein described as a “subranging pipelined charge-domain ADC.” 
   In addition to increasing the resolution of the charge-domain ADC, the present invention has the further advantage of reducing its power consumption for a given resolution. This reduction happens in two ways. First, because of relaxed voltage-resolution requirements on the comparators in each block of the multi-stage architecture, their power can be reduced for a given speed. Second, the power required to clock the CCDs comprising the ADC is reduced, for the following reason. For all ADCs in which the signal is represented as charge, signal-to-noise ratio is ultimately limited by the size of the charge packets representing the signal. For any given ADC resolution, a minimum charge-packet size is thus fixed. Clock-power dissipation is proportional to CCD capacitance, which is in turn proportional to the signal charge magnitude. In the sub-ranging architecture described, only the first block has to accommodate the full signal charge. The downstream blocks, having reduced size, thus dissipate less clock power. 
   A further application of the present invention is to extend the sub-ranging structure by adding a second CM-reduction stage and a third block of pipeline stages, with yet-smaller gate sizes. The result of this extension is a three-stage pipeline of blocks, each block consisting of a multi-stage pipelined (sub-)ADC. This concept could obviously be extended to further stages if such extension were beneficial. 
   In an alternative pipelined charge-domain ADC implementation, the two charge packets constituting a differential pair are carried sequentially in a single CCD register. In this implementation, charge comparison is done time-sequentially at the same floating gate, thus eliminating the effects of floating-gate capacitance mismatch and comparator DC offset. These characteristics are listed above as limitations of the prior art. A negative consequence of the single-register implementation is that the sample rate is only half that of the parallel-register implementation for a given CCD clock rate. The present invention is equally applicable to this single-register, interleaved-charge ADC implementation. It is useful in this application since by reducing post-CM-reduction channel capacity, it increases floating-gate charge-to-voltage scaling, thus reducing demands on the voltage comparators. 
   In a further embodiment it is possible to use floating-gate charge replication or other means to amplify the charges entering the common-mode reduction block. The common-mode reduction step is then applied to this amplified signal, or combined with the amplification process, resulting in an amplified differential signal with relatively reduced common-mode charge. 
   Referring now to  FIG. 5 , a further embodiment is shown. In a CM-reduction stage  64  the signal charges are temporarily transported on metallic connections rather than by CCD transfer. During such a metallic transfer, the charges can be topologically re-arranged and/or switched to alternate paths. Thus it is feasible for the CM-reduction-stage output charges to be demultiplexed into two or more outgoing CCD registers. 
   Elements  66  and  68  in  FIG. 5  represent the final storage gates of  62 , the pipeline stage immediately preceding the common-mode reduction stage  64 .  70  and  72  represent the first storage gates of  74 , a first pipeline stage following the common-mode reduction stage  64 . Elements  76  and  78  represent the first storage gates of  80 , a second pipeline stage following the common-mode reduction stage  64 . Storage gates  71  and  73  store the outputs from gates  70  and  72  respectively. Storage gates  77  and  79  store the outputs from gates  76  and  78  respectively. Each of the pipeline stages  74  and  80  is equivalent to stage  40  in  FIG. 3 . The added feature in this embodiment is that the common-mode reduction stage  64  directs the outgoing charge-packet pairs alternately between the two sets of output  82 ,  84  and  86 ,  88  of the stage  64 . These outputs are provided respectively to the two following pipelines, of which the input stages are respectively  74  and  80 . Stage  64  combines the de-multiplexing function indicated explicitly in  FIG. 5  with the common-mode reduction functionality previously discussed. This figure shows two outgoing pipelines for simplicity; however the number can be greater than two. 
   If this method is used with N output pipelines, then each of these N pipelines can be operated at 1/N the clock rate of the pipeline stages preceding common-mode reduction stage  64 . This lower clock rate can be exploited directly to make the charge comparison more sensitive. For example, the speed and thus the noise bandwidth of the comparators can be reduced, and more precise auto-zeroing of the comparators can be employed. 
   Alternatively, output signal-charge pairs from stage  64  can be injected sequentially into the same CCD channel, rather than simultaneously into a pair of channels, allowing sequential charge comparison as discussed above. This concept is shown in  FIG. 6  (which again illustrates the case of only two outgoing pipelines, although more are possible). Since this alternative has multiple single-register pipelines following the CM-reduction stage, the sample rate of the overall ADC is not reduced as it would be in the case of an entire ADC based on a single register. 
   Elements  90  and  92  in  FIG. 6  represent the final storage gates of  94 , the pipeline stage immediately preceding the common-mode reduction stage  96 . Gates  98  and  100  represent the first storage gates of  102 , a first pipeline stage following the common-mode reduction stage  96 . A delay gate  104  is disposed between the output  106  of the common-mode reduction stage  96 , and storage gate  98 . Elements  108  and  110  represent the first storage gates of  112 , a second pipeline stage following the common-mode reduction stage  96 . A delay gate  114  is disposed between the output  116  of the common-mode reduction stage  96 , and storage gate  108 . Each of the pipeline stages  102  and  112  is equivalent to stage  40  in  FIG. 3 . The common-mode reduction stage  96  directs its outgoing charge-packet pairs alternately between the two sets of outputs  106 ,  118  and  116 ,  120 . The outputs of storage gates  98  and  100  are merged by element  122  then stored in storage gate  124 . The resulting signal in  124  comprises sequential charge pairs, allowing sequential charge comparison, as described above. Similarly, the outputs of storage gates  108  and  110  are merged by element  126  then stored in storage gate  128 . The resulting signal in 218 comprises sequential charge pairs, allowing sequential charge comparison, as described above. This figure shows two outgoing pipelines for simplicity; however the number can be greater than two. 
   In the present invention the reduction of common-mode charge of the signal-charge pairs relative to the differential charge signal as they propagate between blocks of the ADC pipeline is disclosed. This common-mode charge reduction can be accomplished passively, by removing a fixed charge from each charge packet. Other methods could be employed to implement the present invention, including the following. Active circuitry could be used to improve the linearity and/or speed of the common-mode-reduction operation. A dynamic-double-sampling wire-transfer technique is one example; and the use of op-amp integrators is another. Differential charge-packet-splitting could be used to generate the downstream charge pairs. Such a splitter could be driven by floating-gate or floating-diffusion sensors of the signal-charge packets, with or without active gain or buffering circuitry. The common-mode-to-differential-mode ratio of the outgoing charge pair can be chosen to be reduced relative to that of the incoming charge pair in each of these methods. 
   Having described preferred embodiments of the invention it will now become apparent to those of ordinary skill in the art that other embodiments incorporating these concepts may be used. Accordingly, it is submitted that that the invention should not be limited to the described embodiments but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.