Abstract:
An electronic device disclosed herein includes a photodiode, and a plurality of storage components each configured to independently sample and hold charges from the photodiode during each of a plurality of integration periods without discharging the held charge between successive integration periods of the plurality thereof. Each storage component accumulates the charges from the photodiode for a given time window during each integration period, with the given time window for each storage component being different than the given time window for each other storage component. Readout circuitry is configured to transfer the charges from each storage component to a readout node in a respective read period for that storage component. The photodiodes and storage components are not configured to be reset between successive time windows during each integration period.

Description:
TECHNICAL FIELD 
       [0001]    This application is directed to the field of light sensing pixels, and, more particularly, to a light sensing pixel having sampling circuitry that samples a photodiode signal multiple times before resetting the photodiode as to provide for enhanced performance over conventional light sensing pixels. 
       BACKGROUND 
       [0002]    Arrays of light sensing pixels are widely used in digital camera sensors, which are incorporated into devices such as automobiles and smartphones. In some applications, such a digital camera sensor may be instructed to acquire images, and the field of view represented by those images may include lighting delivered by light emitting diodes (LEDs). 
         [0003]    LEDs typically operate by emitting discrete pulses of light in accordance with a duty cycle. This may create an issue with properly representing the shape and color of the light emitted by the LEDs, if the acquisition time of the digital camera sensor is not synchronized with the duty cycle of the LEDs. That is, a LED may be in an “off” portion of its duty cycle while the digital camera sensor is acquiring an image, or may be transitioning between “off” and “on”, or between “on” and “off”, while the digital camera sensor is acquiring the image. 
         [0004]    This can be particularly problematic in cases where another electronic device relies upon images captured by a digital camera sensor in taking other actions. For example, in certain automotive applications, a vehicle may autonomously take an action based upon an illuminated color of a traffic light captured by a digital image sensor, or may present information to a driver based upon the illuminated color of the traffic light. Since an issue with the image captured by the digital camera sensor may thus result in an incorrect autonomous action or in incorrect information being presented to the user, there is a strong commercial desire for improved light sensing pixels capable of properly representing light from emitted LEDs. 
       SUMMARY 
       [0005]    This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter. 
         [0006]    An electronic device disclosed herein includes a photodiode, and a plurality of storage components each configured to independently sample and hold charges from the photodiode during each of a plurality of integration periods without discharging the held charge between successive integration periods of the plurality thereof. Each storage component accumulates the charges from the photodiode for a given time window during each integration period, with the given time window for each storage component being different than the given time window for each other storage component. Readout circuitry is configured to transfer the charges from each storage component to a readout node in a respective read period for that storage component. The photodiodes and storage components are not configured to be reset between successive time windows during each integration period. 
         [0007]    Another aspect is directed to an electronic device including a photodiode, and a first storage component configured to sample and hold voltage from the photodiode during a first sample window of each of a plurality of integration periods. A second storage component is configured to sample and hold voltage from the photodiode during a second sample window of each of the plurality of integration periods. A third storage component is configured to sample and hold voltage from the photodiode during a third sample window of each of the plurality of integration periods. The third sample window is greater in duration than the second sample window which is greater in duration than the first sample window. The first, second, and third sample windows are non-overlapping. 
         [0008]    Readout circuitry is configured to transfer voltage from the first storage component to a storage node during a first read period, transfer voltage from the second storage component to the storage node during a second read period, and transfer voltage from the third storage component to the storage node during a third read period. The photodiode is not configured to be reset between the first, second, and third sample windows. The storage node is configured to be reset between each read period. 
         [0009]    A further aspect is directed to electronic device including a photodiode having an anode coupled to a reference node and a cathode coupled to a first node. A photodiode reset transistor has a drain coupled to a power supply node, a source coupled to the first node, and a gate coupled to receive a photodiode reset signal. A first sample transistor has a source coupled to the first node, a drain coupled to a first intermediate node, and a gate coupled to receive a first sample/hold signal. A second sample transistor has a source coupled to the first node, a drain coupled to a second intermediate node, and a gate coupled to receive a second sample/hold signal. A third sample transistor has a source coupled to the first node, a drain coupled to a third intermediate node, and a gate coupled to receive a third sample/hold signal. First, second, and third storage capacitors are respectively coupled between the first, second, and third intermediate nodes and the reference node. A first transfer gate transistor has a source coupled to the first intermediate node, a drain coupled to a sensing node, and a gate coupled to receive a first read control signal. A first reset transistor has a drain coupled to the power supply node, a source coupled to the sensing node, and a gate coupled to receive a reset signal. A first source follower transistor has a drain coupled to the power supply node, a source coupled to a first follower node, and a gate coupled to the sensing node. A first read transistor has a drain coupled to the first follower node, a source coupled to a first column, and a gate coupled to receive a read signal. 
         [0010]    A method aspect is directed to a method including allowing light to impinge upon a photodiode for an exposure period, and integrating a signal from the photodiode over multiple integration periods during the exposure period, with each integration period having a plurality of sub-periods, wherein successive sub-periods during each integration period are longer than preceding sub-periods during that integration period. The method also includes sampling and holding the signal during each sub-period of each integration period over the exposure period, using a respective storage device for each sub-period, and for each storage device, reading a voltage associated with that storage device during a respective read period associated with that storage device, after passage of the multiple integration periods. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a schematic diagram of a light sensing pixel in accordance with this disclosure. 
           [0012]      FIG. 2  is a timing diagram of the light sensing pixel of  FIG. 1  in operation. 
           [0013]      FIG. 3  is a more detailed timing diagram of the light sensing pixel of  FIG. 1  in operation. 
           [0014]      FIG. 4  is a schematic diagram of a different embodiment of a light sensing pixel in accordance with this disclosure. 
           [0015]      FIG. 5  is a timing diagram of the light sensing pixel of  FIG. 4  in operation. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    In the following description, numerous details are set forth to provide an understanding of the present disclosure. It will be understood by those skilled in the art, however, that the embodiments of the present disclosure may be practiced without these details and that numerous variations or modifications from the described embodiments may be possible. 
         [0017]    With initial reference to  FIG. 1 , a light sensing pixel  100  is now described. The light sensing pixel  100  includes a photodiode PD coupled between a reference node and node N 1 . A photodiode reset transistor Qpd has its drain coupled to a power source node VRT, its source coupled to node N 1 , and its gate coupled to a photodiode reset signal AB. 
         [0018]    Sample transistor Qm 1  has its source coupled to node N 1 , its drain coupled to node N 2 , and its gate coupled to sample/hold signal TGMem 1 . Transfer gate transistor Qr 1  has its drain coupled to node N 2 , its source coupled to node N 3 , and its gate coupled to read control signal TGRead 1 . Memory capacitor MEM 1  is coupled between node N 2  and the reference node. 
         [0019]    Sample transistor Qm 2  has its source coupled to node N 1 , its drain coupled to node N 5 , and its gate coupled to sample/hold signal TGMem 2 . Transfer gate transistor Qt 2  has its drain coupled to node N 5 , its source coupled to node N 3 , and its gate coupled to read control signal TGRead 2 . Memory capacitor MEM 2  is coupled between node N 5  and the reference node. 
         [0020]    As should be appreciated, there may be any number of sample transistors QmN and transfer gate transistors QrN. 
         [0021]    A floating diffusion capacitor FD is shown coupled between node N 3  and the reference node, and represents the sum of parasitic capacitances in the circuit. Reset transistor Qres 1  has its drain coupled to the power supply node VRT, its source coupled to node N 3 , and its gate coupled to receive the reset signal RESET. 
         [0022]    A source follower transistor Qsf 1  has its drain coupled to the power supply node VRT, its source coupled to node N 4 , and its gate coupled to node N 3 . 
         [0023]    A readout transistor Qrd 1  has its drain coupled to node N 4 , its source coupled to node N 7 , and its gate coupled to the read signal READ. 
         [0024]    Operation of the light sensing pixel  100  will now be described with additional reference to  FIGS. 2-3 . After the photodiode reset signal AB is pulsed, the photodiode PD begins to detect light during an exposure period that is between successive assertions of the photodiode reset signal AB. The photodiode PD is integrated over X integration periods (as shown in  FIG. 2 , here there are two integration periods), and each integration period is split into Y integration sub-periods periods (as shown in  FIG. 2 , here each integration period is split into three integration sub-periods). 
         [0025]    It should be noticed, viewing  FIGS. 2 and 3 , that within each integration period, each successive integration sub-period is greater than its predecessor in duration. Thus, integration sub-period I 3  is greater in width than integration sub-period I 2 , which is in turn greater in width than integration sub-period I 1 . The purpose of the successively increasing integration sub-periods is to provide for a range of different exposure times from short to low so as to account for the high light and low light portions of the image captured. 
         [0026]    Each of the sample/hold signals TGMem 1 -TGmemN is pulsed once per integration period, and each during a separate integration sub-period. As an example, in the operation shown in  FIG. 3 , during the I 1  integration sub-period of each integration period, TGMem 1  is pulsed. Similarly, during the I 2  integration sub-period of each integration period, TGMem 2  is pulsed, and during the I 3  (or IN) integration sub-period of each integration period, TGMem 3  (or TGMemN) is pulsed. This sequence will be repeated multiple times within the total Photodiode exposure period. 
         [0027]    Each time TGMem 1  is pulsed, charge fully transferred, between the pinned diode PPD and memory capacitor MEM 1 . Thus, memory capacitor MEM 1  acquires more charge during each integration period after reset of the phododiode AB and before a subsequent reset of the phododiode AB. Likewise, each time TGMem 2  is pulsed, charge is transferred, between the diode PPD and memory capacitor MEM 2 , and each time TGMem 3  (or TGMemN) is pulsed, charge is transferred, between the diode PPD and memory capacitor MEMN. 
         [0028]    Thus, by the end of the exposure period, memory capacitors MEM 1 -MEMN are charged with values representing image data. Subsequently, during a number of readout periods matching the number of storage nodes (here, RD 1 -RD 3 ), each memory capacitor MEM 1 -MEMN is subsequently read out. 
         [0029]    The readout is accomplished by asserting the read signal READ without interruption during all read periods. At the beginning of each read period, the reset signal RESET is pulsed, which causes reset transistor Qres 1  to charge up the floating diffusion capacitor FD. Since at this point transistor Qres 1  is off and transistor Qrd 1  is on, a first read of the FD can be performed after reset and before pulsing TGRead 1  to avoid noise. Once the reset signal RESET pulse is complete, the first read control signal TGRead 1  is pulsed, turning on transistor Qr 1 . Charge is shared between memory capacitor MEM 1  and the floating diffusion capacitor FD in order to perform a correlated double sampling. Transistor Qsf 1 , which is a source follower, transfers the voltage on the diffusion capacitor FD to node N 4 , and transistor Qrd 1  then transfers the voltage to the column at node N 7 . At this point, additional circuitry reads the voltage from node N 7  and performs post processing or analysis on the voltage. 
         [0030]    This proceeds for each readout transistor. Thus, next, the reset signal RESET is pulsed again, and the next read control signal TGRead 2  is pulsed, turning on transistor Qr 2 , resulting in charge being shared between memory capacitor MEM 2  and the floating diffusion capacitor FD, the voltage of which is ultimately transferred to node N 7 . Thereafter, the reset signal RESET is pulsed again, and the next read control signal TGRead 2  (TGReadN) is pulsed, turning on transistor QrN, resulting in charge being shared between memory capacitor MEMN and the floating diffusion capacitor FD, the voltage of which is ultimately transferred to node N 7 . 
         [0031]    Shown in  FIG. 2  are the dead zone times during which the photodiode PD is still detecting incoming photons, but integration is not being performed. Instead, the charge collected during the dead zone is purged through pulsing the AB control. 
         [0032]    A different embodiment of the light sensing pixel  100 ′ is now described with reference to  FIG. 4 . Here, it should be noted that there is but one transfer gate transistor Qr 1 , and that sample transistors Qr 2  and Qr 3  to not have transfer gate counterparts Qm 2  or Qm 3 . Instead, here there is a floating diffusion reset transistor counterpart to each sample transistor. Thus, floating diffusion reset transistor Qres 2  has its drain coupled to the power supply node VRT, its source coupled to node N 5 , and its gate coupled to the reset signal RESET. Similarly, floating diffusion reset transistor Qres 3  has its drain coupled to the power supply node VRT, its source coupled to node N 6 , and its gate coupled to the reset signal RESET. 
         [0033]    Additionally, here there is also a source follower transistor and readout transistor counterpart to each sample transistor. Thus, source follower transistor Qsf 2  has its drain coupled to power supply node VRT, its source coupled to node N 10 , and its gate coupled to node N 5 . Source follower transistor Qsf 3  has its drain coupled to power supply node VRT, its source coupled to node N 11 , and its gate coupled to node N 6 . 
         [0034]    Readout transistor Qrd 2  has its drain coupled to node N 10  its source coupled to a second column at node N 12  and its gate coupled the read signal READ. Redout transistor Qrd 3  has its drain coupled to node N 11 , its source coupled to a third column at node N 13 , and its gate coupled to the reads signal READ. 
         [0035]    Operation of this embodiment will now be described with further reference to  FIG. 5 . Here, the photodiode PD is reset via the photodiode reset signal AB between each integration period. Thus, in operation, first reset signal AB is asserted, turning on transistor Qpd, pulling photodiode PD high, and allowing it to begin detection of incoming photons. Then the reset signal RESET is asserted, turning on reset transistors Qres 1 -Qres 2 , charging diffusion capacitor FD, as well as charging memory capacitors MEM 2  and MEM 3 . The voltage at the photodiode PD, as shown in  FIG. 5 , decreases until TGMem 1  is asserted during I 1 , at which point charge is transferred between the photodiode PD and memory capacitor MEM 1 , pulling the voltage at the photodiode PD high. When TGMem 2  is asserted during I 2 , charge is shared between the photodiode PD and memory capacitor MEM 2 , pulling the voltage at photodiode PD high once again. When TGMem 3  is asserted during I 3 , charge is shared between the photodiode PD and memory capacitor MEM 3 , pulling the voltage at photodiode PD high yet again. As can be seen from the voltages at the memory capacitors MEM 1 -MEM 3  in  FIG. 5 , each successive share of charge results in a voltage decrease. Next, the photodiode PD is reset by photodiode reset signal AB, and the next integration period begins. After the given number of integration periods has passed (which in this case is four integration periods), the read signal READ is held asserted, and the read signal TG is pulsed. At the pulse of read signal TG, the voltage across memory capacitor MEM 1  is transferred to node N 3 , and is in turn passed to node N 7  at the first column by transistors Qsf 1  and Qrd 1 . The voltage across memory capacitors MEM 1 -MEM 2  has already been transferred via their source follower transistors Qsf 2 , Qsf 3  and readout transistors Qrd 2 , Qrd 3  to node N 10  and N 11 , respectively at the second and third columns. 
         [0036]    The circuits presented above provide for accurate detection of LED lighting via the different integration periods and sub-periods. Although the preceding description has been described herein with reference to particular means, materials and embodiments, it is not intended to be limited to the particulars disclosed herein; rather, it extends to all functionally equivalent structures, methods, and uses, such as are within the scope of the appended claims.