Abstract:
There is provided a voltage comparison circuit including: a voltage adjustment section connected between a first potential supply line and a first node; a first constant current source connected between the first node and a fixed potential supply line; a switch element connected between a second potential supply line and a second node, and including a control terminal connected to the first node, the switch element operating in accordance with a voltage of the first node; and a second constant current source connected between the second node and the fixed potential supply line.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2011-290414 filed on Dec. 29, 2011, the disclosure of which is incorporated by reference herein. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a voltage comparison circuit, and for example relates to a voltage comparison circuit capable of directly comparing various power source voltages. 
         [0004]    2. Related Art 
         [0005]    A voltage comparison circuit  60  as illustrated in  FIG. 6  is commonly known as a voltage comparison circuit (a comparator). The voltage comparison circuit  60  combines a differential stage  62  with a grounded-source amplification stage  64 . The differential stage  62  includes NMOS transistors  72  and  74 , the sources of which are connected together. Voltages that are objects of comparison are inputted to the respective gates of the NMOS transistors  72  and  74 . 
         [0006]    However, in the voltage comparison circuit  60  as illustrated in  FIG. 6 , the respective gates of the NMOS transistors  72  and  74  serve as input terminals. Therefore, if a voltage exceeding the threshold voltage of the NMOS transistor  72  or the threshold voltage of the NMOS transistor  74  is inputted, a linear region is formed in the NMOS transistor  72  or  74 , and the voltages may not be compared. Thus, a range of voltages that can be inputted to the voltage comparison circuit  60  is limited, and power source voltages such as VDD and the like may not be directly compared. 
         [0007]    To compare power source voltages using the voltage comparison circuit  60 , the power source voltages must be voltage-divided by resistors or the like, or a range of voltages that can be inputted to the voltage comparison circuit must be extended, or the like. 
         [0008]    When a voltage is voltage-divided by resistors, the overall circuit area increases, and power consumption is greater because of the provision of the resistors. Moreover, variations in accuracy of the resistance components are likely to have an effect on comparison results. 
         [0009]    To extend the range of voltages that can be inputted to a voltage comparison circuit, providing a level shifter stage or forming the differential stage of the voltage comparison circuit as a folded cascode amplification circuit have been considered. 
         [0010]    However, providing a level shifter stage or forming the differential stage as a folded cascode amplification circuit increases the size of the circuit. Hence, power consumption increases, the effects of variations in components become greater, and the level of difficulty of circuit design rises. 
         [0011]    Japanese Patent Application Laid-Open (JP-A) No. 2010-230508 discloses a battery voltage detection circuit that measures the voltage of a battery of approximately 3 V, and makes a determination as to whether the voltage of the battery is at least a predetermined threshold. 
         [0012]    However, the battery voltage detection circuit recited in JP-A No. 2010-230508 is only applicable to voltages in a narrow range of about 1.5 V to 3 V, which are supplied from batteries used in watches. The problem of voltages that can be inputted to a voltage comparison circuit being limited has not been solved. 
       SUMMARY 
       [0013]    The present invention is proposed to solve the problem described above, and an object of the present invention is to provide a voltage comparison circuit, particularly a voltage comparison circuit capable of directly comparing various power source voltages. 
         [0014]    An aspect of the present invention provides a voltage comparison circuit including: 
         [0015]    a voltage adjustment section connected between a first potential supply line and a first node; 
         [0016]    a first constant current source connected between the first node and a fixed potential supply line; 
         [0017]    a switch element connected between a second potential supply line and a second node, and including a control terminal connected to the first node, the switch element operating in accordance with a voltage of the first node; and 
         [0018]    a second constant current source connected between the second node and the fixed potential supply line. 
         [0019]    According to the present invention, currents measuring voltages are inputted to the sources of MOS transistors. Thus, a useful effect is provided in that a voltage comparison circuit capable of directly comparing various power source voltages may be provided. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    Exemplary embodiments of the present invention will be described in detail based on the following figures, wherein: 
           [0021]      FIG. 1  is a circuit diagram showing an example of schematic structure of a voltage comparison circuit in accordance with a first exemplary embodiment of the present invention; 
           [0022]      FIG. 2  is a graph showing output results of the first exemplary embodiment of the present invention; 
           [0023]      FIG. 3  is a circuit diagram showing a variant example of the voltage comparison circuit in accordance with the first exemplary embodiment of the present invention; 
           [0024]      FIG. 4  is a circuit diagram showing an example of schematic structure of a voltage comparison circuit in accordance with a second exemplary embodiment of the present invention; 
           [0025]      FIG. 5  is a circuit diagram showing a variant example of the voltage comparison circuit in accordance with the second exemplary embodiment of the present invention; and 
           [0026]      FIG. 6  is a circuit diagram showing an example of schematic structure of a commonly known voltage comparison circuit. 
       
    
    
     DETAILED DESCRIPTION 
     First Exemplary Embodiment  
       [0027]    Herebelow, a voltage comparison circuit according to the present exemplary embodiment is described with reference to the attached drawings. 
         [0028]      FIG. 1  shows an example of schematic structure of the voltage comparison circuit according to the present exemplary embodiment. A voltage comparison circuit  100  of the present exemplary embodiment that is illustrated in  FIG. 1  is provided with a first PMOS transistor  12  in a front stage. A source  51  of the first PMOS transistor  12  is connected to a first power source, a power source voltage of which is VDD 1 , and a drain D 1  and gate G 1  are short-circuited together. Thus, the first PMOS transistor  12  is “diode-connected” and constituted to operate in the saturation region. 
         [0029]    A first NMOS transistor  14  is also provided in the front stage of the voltage comparison circuit  100  of the present exemplary embodiment. A drain D 2  of the first NMOS transistor  14  is connected with the drain D 1  of the first PMOS transistor  12  at a node  1 , a source S 2  is connected to a ground potential VSS, and a gate G 2  is provided with a bias voltage VBN 1 . 
         [0030]    In a next stage, a second PMOS transistor  16  is provided. A source S 3  of the second PMOS transistor  16  is connected to a second power source, a power source voltage of which is VDD 2 , and a gate G 3  is connected with the drain D 1  of the first PMOS transistor  12  at the node  1 . The second PMOS transistor  16  has the same threshold voltage and current capacity as the first PMOS transistor  12 . 
         [0031]    A second NMOS transistor  22  is also provided in the next stage. A drain D 4  of the second NMOS transistor  22  is connected with the drain D 3  of the second PMOS transistor  16  at a node  2 , a source S 4  is connected to the ground potential VSS, and a gate G 4  is provided with a bias voltage VBN 1 . The second NMOS transistor  22  has the same threshold voltage and current performance as the first NMOS transistor  14 . The first NMOS transistor  14  and the second NMOS transistor  22  function as constant current sources. 
         [0032]    A subsequent stage is a CMOS inverter  26  including an inverter PMOS transistor  28  and an inverter NMOS transistor  30 . A gate G 5  of the inverter PMOS transistor  28  is connected to the drain D 3  of the second PMOS transistor  16 , and a gate G 6  of the inverter NMOS transistor  30  is also connected to the drain D 3  of the second PMOS transistor  16 . 
         [0033]    In the CMOS inverter  26 , the voltage VDD 2  is provided to a source S 5  of the inverter PMOS transistor  28 , and a source S 6  of the inverter NMOS transistor  30  is connected to the ground potential VSS. A drain D 5  of the inverter PMOS transistor  28  and a drain D 6  of the inverter NMOS transistor  30  are connected together, and a junction point of this connection serves as an output terminal  32 . 
         [0034]    Because the first PMOS transistor  12  provided in the front stage of the voltage comparison circuit  100  of the present exemplary embodiment is diode-connected and constituted to operate in the saturation region by the drain D 1  and gate G 1  being short-circuited, the gate-source voltage of the first PMOS transistor  12 , VGS 12 , is equal to the drain-source voltage, VDS 12 . 
         [0035]    The diode-connected first PMOS transistor  12  operates as a resistance element with a predetermined on-resistance, and functions as a voltage adjustment section that adjusts the voltage of node  1 . 
         [0036]    In the front stage of the voltage comparison circuit  100  of the present exemplary embodiment, the first PMOS transistor  12  and the first NMOS transistor  14  are connected in a complementary arrangement. Therefore, when saturation regions are formed in the first PMOS transistor  12  and the first NMOS transistor  14 , the same current flows in the first PMOS transistor  12  and the first NMOS transistor  14 . 
         [0037]    In the next stage of the voltage comparison circuit  100  of the present exemplary embodiment, the second PMOS transistor  16  and the second NMOS transistor  22  are connected in a complementary arrangement. Therefore, when saturation regions are formed in the second PMOS transistor  16  and the second NMOS transistor  22 , the same current flows in the second PMOS transistor  16  and the second NMOS transistor  22 . 
         [0038]    In the present exemplary embodiment, as mentioned above, because the drain D 1  and gate G 1  of the first PMOS transistor  12  are short-circuited, VGS 12 =VDS 12 . 
         [0039]    Therefore, if the voltage of the drain D 1  of the first PMOS transistor  12  is represented by VD 1 , the gate-source voltage VGS 12  of the first PMOS transistor  12  can be expressed by the following expression (1). 
         [0000]        VGS   12   =VD   1   −VDD 1   (1)
 
         [0040]    Because the gate of the second PMOS transistor  16  is connected to the drain D 1  of the first PMOS transistor  12 , a gate-source voltage VGS 16  of the second PMOS transistor  16  can be expressed by the following expression (2). 
         [0000]        VGS   16   =VD   1   −VDD 2   (2)
 
         [0041]    If the threshold voltage of the first PMOS transistor  12  is represented by VT, a current Id 12  flowing in the first PMOS transistor  12 , which is in the saturation region, can be found from the following expression (3) and expression (4). 
         [0000]        Id   12   =K   p   W/L ( VGS   12 - VT ) 2    (3)
 
         [0000]        K   p =½*μ*Cos   (4)
 
         [0042]    In expression (3), W represents the width of an inversion layer and L represents the length of the inversion layer. In expression (4), μ represents the mobility of electrons and Cos represents a capacitance per unit area of the gate oxide layer. 
         [0043]    If the aforementioned expression (1) is substituted into expression (3), the following expression (5) is obtained. 
         [0000]        Id   12   =K   p   W/L ( VDD 1- VD   1   +VT ) 2    (5)
 
         [0044]    A current Id 16  flowing in the second PMOS transistor  16 , which has the same threshold voltage as the first PMOS transistor  12  and is in the saturation region, can be found from the following expression (6). 
         [0000]        Id   16   =K   p   W/L ( VGS   16 - VT ) 2    (6)
 
         [0045]    If the aforementioned expression (2) is substituted into expression (6), the following expression (7) is obtained. 
         [0000]        Id   16   =K   p   W/L ( VDD 2- VD   1   +VT ) 2    (7)
 
         [0046]    Thus, if VDD 1 &gt;VDD 2 , the current Id 12  provided by expression (5) is greater than the current Id 16  provided by expression (7). 
         [0047]    Therefore, a sufficient current does not flow in the second PMOS transistor  16 , and a voltage VD 20  of the drain D 3  of the second PMOS transistor  16  is lowered. 
         [0048]    Alternatively, if VDD 1 &lt;VDD 2 , the current Id 16  provided by expression (7) is greater than the current Id 12  provided by expression (5). 
         [0049]    Sufficient current flows in the second PMOS transistor  16 , and the voltage VD 20  of the drain D 3  of the second PMOS transistor  16  is raised. 
         [0050]    VD 20  is inputted to the CMOS inverter  26 . Thus, output results as illustrated in  FIG. 2  are obtained. 
         [0051]    When VD 20 is lowered, the inverter PMOS transistor  28  turns on, and VDD 2  is outputted at the output terminal  32 . 
         [0052]    When VD 20  is raised, the inverter NMOS transistor  30  turns on, and the ground potential VSS of approximately 0 V is outputted at the output terminal  32 . 
         [0053]    Thus, the voltages of VDD 1  and VDD 2  may be compared by making a determination as to whether the voltage of the output terminal  32  is VDD 2  or the ground potential VSS. 
         [0054]    In the voltage comparison circuit  100  according to the present exemplary embodiment, because the number of components is smaller than in the common voltage comparison circuit illustrated in  FIG. 6 , the overall area of the circuit may be made smaller, and hence power consumption may be reduced and operation at a low voltage is possible. Moreover, because the number of components is small, the elements may be mounted close together. Thus, the effects of temperature changes on the components and the effects of variations in the performance of components may be reduced compared to the voltage comparison circuit  60  illustrated in  FIG. 6 . 
         [0055]    The voltage comparison circuit  100  according to the present exemplary embodiment compares the voltages VDD 1  and VDD 2  on the basis of the current Id 12  flowing in the first PMOS transistor  12 , as calculated by the aforementioned expression (5), and the current Id 16  flowing in the second PMOS transistor  16 , as calculated by the aforementioned expression (7). 
         [0056]    Provided the threshold voltages and current capacities of the first PMOS transistor  12  and the second PMOS transistor  16  are the same and the threshold voltages and current capacities of the first NMOS transistor  14  and the second NMOS transistor  22  are the same, voltages may be compared on the basis of the current Id 12  and the current Id 16 . Therefore, even if there is a temperature change or a voltage fluctuation, the voltages of VDD 1  and VDD 2  may be compared with high accuracy. 
         [0057]    While the present exemplary embodiment has the configuration illustrated in  FIG. 1 , in order to compare the voltages of VDD  1  and VDD 2  with high accuracy, it is desirable to dispose the first PMOS transistor  12  and the second PMOS transistor  16  as close together as possible, and to dispose the first NMOS transistor  14  and the second NMOS transistor  22  as close together as possible. 
         [0058]    If the voltage comparison circuit according to the present exemplary embodiment is implemented in an integrated circuit, variations in the components of the voltage comparison circuit according to the present exemplary embodiment may be restrained by suitable provision of dummy MOSs. 
         [0059]    If feasible, variations in the components may be made to cancel out by the components being arranged in a common centroid layout. 
         [0060]    The voltage comparison circuit  100  according to the present exemplary embodiment may also compare voltages other than power source voltages such as VDD 1  and VDD 2  or the like. 
         [0061]      FIG. 3  is a diagram showing a variant example of the voltage comparison circuit according to the present exemplary embodiment. 
         [0062]    In a voltage comparison circuit  102  illustrated in  FIG. 3 , a voltage V 1  must be at least the sum of the voltage VD 1  of the drain D 1  of the first PMOS transistor  12  and an overdrive voltage VOV 14  of the first NMOS transistor  14 . 
         [0063]    If the threshold voltage of the first PMOS transistor  12  is represented by VT, the voltage VD 1  of the first PMOS transistor  12  in which the saturation region is formed should be a voltage that is lower than V 1  by VT±α. Here, a represents a change in measured VT associated with a change in a current flowing in the first NMOS transistor  14 . 
         [0064]    Therefore, the voltage V 1  must satisfy the following expression (A). 
         [0000]        V 1&gt;( VT ±α)− VOV   14    (A)
 
         [0065]    Furthermore, for driving of the CMOS inverter  26  of the back stage to be possible, V 2  must be at least a voltage capable of driving the CMOS inverter  26 . 
         [0066]    The meaning of the term “a voltage capable of driving the CMOS inverter  26 ” as used here includes a voltage that exceeds the larger threshold voltage of the respective threshold voltages of the inverter PMOS transistor  28  and inverter NMOS transistor  30  constituting the CMOS inverter  26 . 
         [0067]    According to the present exemplary embodiment and variant example as described hereabove, a voltage comparison circuit capable of directly comparing various power source voltages may be provided. 
       Second Exemplary Embodiment  
       [0068]    Herebelow, a voltage comparison circuit according to the present exemplary embodiment is described with reference to the attached drawings. 
         [0069]      FIG. 4  shows an example of schematic structure of the voltage comparison circuit according to the present exemplary embodiment. A voltage comparison circuit  104  of the present exemplary embodiment that is illustrated in  FIG. 4  has a structure in which the structure of the voltage comparison circuit  100  of the first exemplary embodiment is inverted. 
         [0070]    In the voltage comparison circuit  104  of the present exemplary embodiment, the third NMOS transistor  42  is provided in the front stage. A source S 8  of the third NMOS transistor  42  is connected to a ground potential VSS 1  and a drain D 8  and gate G 8  are short-circuited together. Thus, the third NMOS transistor  42  is “diode-connected” and constituted to operate in the saturation region. 
         [0071]    A third PMOS transistor  44  is also provided in the front stage of the voltage comparison circuit  104  of the present exemplary embodiment. A drain D 7  of the third PMOS transistor  44  is connected with the drain D 8  of the third NMOS transistor  42  at a node  1 , a source S 7  is connected to a power source, of which a power source voltage is VDD 1 , and a gate G 7  is provided with a bias voltage VBP 1 . 
         [0072]    A fourth NMOS transistor  46  is provided in the next stage. A source S 10  of the fourth NMOS transistor  46  is connected to a ground potential VSS 2  and a gate G 10  is connected with the drain D 8  of the third NMOS transistor  42  at node  1 . The fourth NMOS transistor  46  has the same threshold voltage and current capacity as the third NMOS transistor  42 . 
         [0073]    A fourth PMOS transistor  52  is provided in the above-mentioned next stage. A drain D 9  of the fourth PMOS transistor  52  is connected with the drain D 10  of the fourth NMOS transistor  46  at a node  2 , a source S 9  is connected to the power source whose power source voltage is VDD 1 , and a gate G 9  is provided with the bias voltage VBP 1 . The fourth PMOS transistor  52  has the same threshold voltage and current capacity as the third PMOS transistor  44 . 
         [0074]    The subsequent stage is a CMOS inverter  56  including the inverter PMOS transistor  28  and the inverter NMOS transistor  30 . A gate G 11  of the inverter PMOS transistor  28  is connected to the drain D 10  of the fourth NMOS transistor  46 , and a gate G 12  of the inverter NMOS transistor  30  is also connected to the drain D 10  of the fourth NMOS transistor  46 . 
         [0075]    The CMOS inverter  56  is the same as the CMOS inverter  26  of the voltage comparison circuit  100  of the first exemplary embodiment except that a source S 11  of the inverter PMOS transistor  28  is connected to the power source whose power source voltage is VDD 1  and a source S 12  of the inverter NMOS transistor  30  is connected to the ground potential VSS 2 . Accordingly, detailed descriptions of the CMOS inverter  56  are not given. 
         [0076]    In the front stage of the voltage comparison circuit  104  of the present exemplary embodiment, the third PMOS transistor  44  and the third NMOS transistor  42  are connected in a complementary arrangement. Therefore, when saturation regions are formed in the third PMOS transistor  44  and the third NMOS transistor  42 , the same current flows in the third PMOS transistor  44  and the third NMOS transistor  42 . 
         [0077]    In the next stage of the voltage comparison circuit  104  of the present exemplary embodiment, the fourth PMOS transistor  52  and the fourth NMOS transistor  46  are connected in a complementary arrangement. Therefore, when saturation regions are formed in the fourth PMOS transistor  52  and the fourth NMOS transistor  46 , the same current flows in the fourth PMOS transistor  52  and the fourth NMOS transistor  46 . 
         [0078]    In the present exemplary embodiment, because the drain D 8  and gate G 8  of the third NMOS transistor  42  are short-circuited, if the gate-source voltage of the third NMOS transistor  42  is represented by VGS 42  and the drain-source voltage of the third NMOS transistor  42  is represented by VDS 42 , then VGS 42 =VDS 42 . 
         [0079]    Therefore, if the voltage of the drain D 8  of the third NMOS transistor  42  is represented by VD 8 , the gate-source voltage VGS 42  of the third NMOS transistor  42  can be expressed by the following expression (8). 
         [0000]        VGS   42   =VD   8   −VSS 1   (8)
 
         [0080]    Because the gate G 10  of the fourth NMOS transistor  46  is connected to the drain D 8  of the third NMOS transistor  42  and the source S 10  of the fourth NMOS transistor  46  is connected to the ground potential VS 52 , a gate-source voltage VGS 46  of the fourth NMOS transistor  46  can be expressed by the following expression (9). 
         [0000]        VGS   46   =VD   8   −VSS 2   (9)
 
         [0081]    If the threshold voltages of the third NMOS transistor  42  and the fourth NMOS transistor  46  are represented by Vt, a current Id 42  flowing in the third NMOS transistor  42 , which is in the saturation region, can be found from the following expression (10). 
         [0000]        Id   42   =K   p   W/L ( VSS 1 −VD   8   +Vt ) 2    (10)
 
         [0082]    Similarly, a current Id 46  flowing in the fourth NMOS transistor  46 , which is in the saturation region, can be found from the following expression (11). 
         [0000]        Id   46   =K   p   W/L ( VSS 2 −VD   8   +Vt ) 2    (11)
 
         [0083]    Thus, if VSS 1 &lt;VSS 2 , the current Id 46  provided by expression (11) is greater than the current Id 42  provided by expression (10). 
         [0084]    Sufficient current flows in the fourth NMOS transistor  46 , and electrons, having negative charges, move from the source S 10  of the fourth NMOS transistor  46  toward the drain D 10 . As a result, a voltage VD 10  of the drain D 10  of the fourth NMOS transistor  46  is lowered. 
         [0085]    Alternatively, if VSS 1 &gt;VSS 2 , the current Id 42  provided by expression (10) is greater than the current Id 46  provided by expression (11). 
         [0086]    A sufficient current does not flow in the fourth NMOS transistor  46 , and sufficient electrons cannot move from the source S 10  of the fourth NMOS transistor  46  toward the drain D 10 . As a result, the voltage VD 10  of the drain D 10  of the fourth NMOS transistor  46  is higher than in the above-described case in which VSS 1 &lt;VSS 2 . 
         [0087]    The current outputted at the drain D 10  is inputted to the CMOS inverter  56 . If the voltage VD 10  of the drain D 10  is raised, that is, if VSS 1 &gt;VSS 2 , VSS 2  is outputted from the output terminal  32 . If the voltage VD 10  of the drain D 10  is lowered, that is, if VSS 1 &lt;VSS 2 , VDD 1  is outputted from the output terminal  32 . 
         [0088]    According to the present exemplary embodiment as described above, a determination may be made as to which of the different VSS potentials is higher and which is lower. 
         [0089]    The voltage comparison circuit  104  according to the present exemplary embodiment may compare voltages other than VSS 1  and VSS 2 . 
         [0090]      FIG. 5  is a diagram showing a variant example of the voltage comparison circuit according to the present exemplary embodiment. 
         [0091]    In a voltage comparison circuit  106  illustrated in  FIG. 5 , if the voltage of the drain D 8  of the third NMOS transistor  42  is represented by VD 8  and the overdrive voltage of the third PMOS transistor  44  is represented by VOV 44 , the voltage VDD 1 -V 1  must be at least VD 8 +VOV 44 . 
         [0092]    If the threshold voltage of the third NMOS transistor  42  is represented by Vt, the voltage VD 8  of the third NMOS transistor  42  in which the saturation region is formed should be a voltage that is lower than VDD 1  by Vt±α. Here, a represents a change in measured Vt associated with a change in the current flowing in the third NMOS transistor  42 . 
         [0093]    Therefore, the voltage V 1  must satisfy the following expression (B). 
         [0000]        V 1&gt; VDD 1−( Vt ±α)− VOV   44    (B)
 
         [0094]    Furthermore, for driving of the CMOS inverter  56  of the subsequent stage to be possible, the potential difference between VDD  1  and V 2  must be at least a voltage capable of driving the CMOS inverter  56  provided at the subsequent stage. 
         [0095]    The meaning of the term “a voltage capable of driving the CMOS inverter  56 ” as used here includes a voltage that exceeds the larger threshold voltage of the respective threshold voltages of the inverter PMOS transistor  28  and inverter NMOS transistor  30  constituting the CMOS inverter  56 . 
         [0096]    Therefore, if the larger value of the threshold voltages of the MOS transistors constituting the CMOS inverter  56  is represented by Vti, V 2  must satisfy the following expression (C). 
         [0000]        V 2&gt; VDD 1 −Vti    (C)
 
         [0097]    As described hereabove, according to the present exemplary embodiment, the potential difference between the two voltages VSS may be determined, and hence the voltages of two power sources that serve as ground potentials may be determined. 
         [0098]    It will be obvious to practitioners that the structures, operations and the like of the voltage comparison circuit  100 , the voltage comparison circuit  102 , the voltage comparison circuit  104 , the voltage comparison circuit  106  and the like described in the present exemplary embodiments are merely examples, and that modifications may be applied in accordance with circumstances, within a scope not departing from the spirit of the present invention. 
         [0099]    For example, although ordinary MOS transistors are used in the first exemplary embodiment and the second exemplary embodiment, a further improvement in accuracy may be expected if the components are connected in a cascode arrangement.