Abstract:
Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path are described. In an example shared signal path, a command circuit is configured to receive a command and an indicator signal. A lockout circuit is coupled to the command circuit and configured to give precedence to a chosen command type by masking the indicator signal. In another example, a counter circuit is coupled to the lockout circuit and configured to force the lockout circuit to sample the indicator signal at regular intervals.

Description:
BACKGROUND 
       [0001]    In many memory systems, such as in synchronous dynamic random access memory (SDRAM), it may be advantageous to have a cloned delay line to shift commands in the system clock time domain to a delay locked loop (DLL) time domain. The DLL time domain represents the time domain for various clock and control signals internal to a memory. To save layout area, this cloned delay line may be a combined command line, that is, it may carry both read and write commands. The read and write commands may be extended over multiple clock cycles in order to reduce the power requirements of the memory system. The extended read and write commands may be separated at the output of the DLL for subsequent use by components of the memory system. The layout and power conservation advantages of the above configuration may be negatively impacted by the inability to separate read and write commands properly when a read command is followed closely by a write command in memory systems with tight timing specifications. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0002]      FIG. 1  is a block diagram of a memory command circuit that includes a lockout circuit according to an illustrative embodiment of the disclosure. 
           [0003]      FIG. 2  is a circuit diagram of a memory command circuit including a lockout circuit according to a particular illustrative embodiment of the disclosure. 
           [0004]      FIG. 3  is a timing diagram illustrating operation of the lockout circuit shown in  FIG. 2  according to an illustrative embodiment of the disclosure. 
           [0005]      FIG. 4  is a circuit diagram of a memory command circuit including a lockout circuit with a counter circuit according to an illustrative embodiment of the disclosure. 
           [0006]      FIG. 5  is a timing diagram illustrating the operation of the memory command circuit shown in  FIG. 4  according to an illustrative embodiment of the disclosure. 
           [0007]      FIG. 6  is a portion of a memory according to an illustrative embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    Certain details are set forth below to provide a sufficient understanding of embodiments of the disclosure. However, it will be clear to one having skill in the art that embodiments of the disclosure may be practiced without these particular details. Moreover, the particular embodiments of the present disclosure described herein are provided by way of example and should not be used to limit the scope of the disclosure to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the disclosure. 
         [0009]      FIG. 1  illustrates an apparatus with a memory command circuit  100  that may be included in a memory, according to an embodiment of the invention. As used herein, apparatus may refer to, for example, an integrated circuit, a memory device, a memory system, an electronic device or system, a smart phone, a tablet, a computer, a server, etc. CmdDLL  105  is a command path, which may be a combined command cloned DLL line that may carry both read and write command signals and shift them from the system clock time domain to the DLL time domain. Rd/Wr  110  is a signal path that may carry an indicator signal which may be used by the memory command circuit  100  to indicate whether a command on CmdDLL  105  is a read or a write command. The Rd/Wr  110  signal path is in the system clock time domain. The Rd/Wr  110  may not be converted to the DLL time domain to save the layout space of a second DLL line clone. CmdDLL  105  and Rd/Wr  110  may be coupled to a lockout circuit  115 . The lockout circuit  115  may be used to prevent truncation of read commands in the RdDLL/WrDLL command circuit  120  when followed closely by a write command, as will be explained in more detail below. The RdDLL/WrDLL command circuit  120  is configured to differentiate and separate the read and write commands at the output of the command circuit  100  into two internal command signals RdDLL  130  and WrDLL  135 . RdDLL  130  and WrDLL  135  may be provided to detection circuits (not shown) or other components of the memory. In other embodiments, CmdDLL  105  may be configured to carry more than two different command types, and the RdDLL/WrDLL circuit  120  may then be configured to differentiate and separate the command types onto a respective number of signal lines. 
         [0010]    In the current embodiment, when a command is sent on CmdDLL  105 , Rd/Wr  110  may be set to a high logic level for a read command or set to a low logic level for a write command. As mentioned previously, Rd/Wr  110  is in the system clock time domain, but CmdDLL is in the DLL time domain. Command types are identified at the exit point of the command circuit  100 . Tight read to write timing specifications may result in a failure to identify the type of command at the correct point in time resulting in truncated signals glitches, or other problems. This may be due to the problem of placing a signal on Rd/Wr  110  accurately in relation to the DLL time domain. The timing difficulties described above for read and write commands may also occur for other command sequences. 
         [0011]    The lockout circuit  115  may be used as a masking circuit to prevent the command identification problems mentioned above. For example, the lockout circuit  115  may give one command priority over the other. In an embodiment of the disclosure, the lockout circuit  115  may give the read command priority over the write command, and may block the change to a write command until the read command has finished. The lockout circuit  115  may grant precedence to the RdDLL  130  once it transitions to a high logic level. The state of the RdDLL  130  may be fed back into the lockout circuit to mask a subsequent incoming signal on Rd/Wr  100 , for example, indicating a write command so that the write command cannot truncate the RdDLL  130  command prematurely. In other embodiments, a different command type may be given priority over other commands. 
         [0012]      FIG. 2  is circuit diagram of a memory command circuit  200  according to an embodiment of the invention. CmdDLL  105  is coupled to the inputs of NAND gate  235  and NAND gate  225 . NAND gates  235 ,  225  are coupled to inverters  245 ,  240 , respectively. Inverter  240  outputs WrDLL  135 . Inverter  245  outputs RdDLL  130 , and its output is also coupled to inverter  250 , which is coupled to the input of NAND gate  230 . The output of NAND gate  230  is coupled to the second input of NAND gate  235 , creating a feedback loop. Rd/Wr  110  is coupled to inverter  215  to NAND gate  230 . Rd/Wr  110  is further coupled to NOR gate  220 . RdDLL  130  is also provided to NOR gate  220 . The output of NOR gate  220  is coupled to the other input of NAND gate  225 . 
         [0013]    The foregoing description is an example implementation of the lockout circuit  115 . Embodiments of the invention may be implemented with alternative logic gates and command types without departing from the scope of the present disclosure. Certain examples of circuit operation will now be described. The examples described below are provided to enhance understanding of the present disclosure. The examples should not be considered to be limiting in scope of the present disclosure. 
         [0014]    In a first example, a read command is provided to the cloned delay line, CmdDLL  105 , with the command represented by a high logic level. To indicate a read command on the cloned delay line, Rd/Wr  110  is also a high logic level. Regardless of the current state of RdDLL  130 , the output of NOR gate  220  is at a low logic level. The NAND gate  225  receives a high and a low logic level input, resulting in an output having a high logic level, which is inverted to provide WrDLL  135  having a low logic level. NAND gate  230  receives a low logic level signal from inverter  215 . Regardless of the current state of RdDLL  130 , the output of NAND gate  230  is a high logic level. Both inputs into NAND gate  235  are at a high logic level, and the output of NAND gate  235  is at a low logic level, resulting in RdDLL  130  having a high logic level. 
         [0015]    Now consider a second example where Rd/Wr  110 , in the system clock time domain, has switched to a low logic level to indicate a write command has been sent. However, the previous read command has not yet completely transited through the cloned delay line. RdDLL  130  and CmdDLL  105  are still at high logic levels, but Rd/Wr  110  is a low logic level. The output of NOR gate  220  is kept at a low logic level due to the high logic level RdDLL  130  feedback. WrDLL  135  is kept at a low logic level. NAND gate  230  receives a high logic level signal from inverter  215  and a low logic level signal from inverter  250 , and the output of NAND gate  230  is kept at a high logic level. Therefore, the read command on CmdDLL  105  is allowed to transit without being truncated by the incoming write command. The write command will then transit CmdDLL  105  through the lockout circuit  115 , and the RdDLL/WrDLL circuit  120  to WrDLL  135 . 
         [0016]    The advantages of the lockout circuit disclosed above may be understood in view of the timing diagram  300  in  FIG. 3 . External clock  305  corresponds to the system domain clock. External cmd  310  illustrates the read and write commands received by the memory. A read command is received at time T 0  and a write command is received at time T 6 . Read cmd decode signal  315  and Write cmd decode signal  320  illustrate the decoded commands internal to the memory resulting from the external commands. For example, shortly after the read command is received, an internal command extending between shortly after time T 0  and time T 2  represents an internal command corresponding to the read command received at time T 0 . Similarly, shortly after the write command is received, an internal command extending between shortly after time T 6  and time T 8  represents an internal command corresponding to the write command received at time T 6 . Stretched read command  325  and stretched write command  330  illustrate the internal read and write commands that have been extended. In the example operation illustrated in the timing diagram  300 , the stretched read command  325  and stretched write command  330  extend over four clock cycles, for example, between shortly after time T 0  and T 3  for the stretched internal read command  325 . The read/not write signal  340  corresponds to the state of Rd/Wr  110 . For example, the read/not write signal  340  is at a high logic level to indicate a read command, and changes to a low logic level at time T 4  to indicate a write command. 
         [0017]    The combined command in clock domain  335  is the combination of the stretched read command  325  and the stretched write command  330 . The combined command in DLL domain  345 , which is based on the combined command in clock domain  335  (e.g., delayed therefrom), corresponds to the state of CmdDLL  105 . The combined command in DLL domain  345  is at a high logic level when a command is transiting (e.g., between times T 1  and T 5  for the command corresponding to the read command, and following time  1 T 7  for the command corresponding to the write command) and at a low logic level when no command is transiting (e.g., between times T 5  and T 7  between the commands corresponding to the read and write commands). The timing margin to identify read versus write  350  between the falling edge of the read/not write  340  at time T 4  and the rising edge of the combined command in DLL domain at time T 7 , is widened such that the read/not write signal  340  carried by Rd/Wr  110  can be switched before the previous read command has finished transiting CmdDLL  105 . For example, as illustrated in  FIG. 3 , the read/not write signal  340  transitions to a low logic level at time T 4  before the command corresponding to the read command transitions to a low logic level at time T 5 . The widened timing margin  350  may allow for greater flexibility when synchronizing DLL domain and system clock domain signals. 
         [0018]    The precedence given to read commands on RdDLL  130  by the lockout circuit  115  as illustrated in  FIG. 2  may not cause problems for write commands followed by read commands. This is due to the column address write strobe latency (CWL) and data-collection specifications set in the memory system prevent read commands from prematurely truncating write signals. A read may only be issued after CWL, collected write data, and the column to column command delay (tCCD) from internal write have elapsed. Accordingly, a lockout circuit may not be necessary to give precedence to incoming write commands followed by read commands on CmdDLL  105 . 
         [0019]    The lockout circuit  115  implementation in  FIG. 2  may allow the RdDLL/WrDLL circuit  120  to differentiate between commands without truncating commands as long as there is at least one clock cycle between successive stretched read and write commands on CmdDLL  105 . The specified column address strobe latency (CL) and column address write strobe latency (CWL) of current DDR 3 /DDR 4  may allow for the implementation of the lockout circuit  115  described above. However, some memory systems have, or may have in the future, latency settings that could cause a read command followed by a write command to appear as a single pulse on CmdDLL  105 . 
         [0020]      FIG. 4  illustrates a memory command circuit  400  according to an embodiment of the invention. In this example implementation, a counter circuit  410  may be included to provide a count value. As shown for the embodiment of  FIG. 4 , the counter circuit  410  is a 2-bit counter that provides a 2-bit count value that includes first and second bits represented by count signals C 0  and C 1 . The counter circuit  410  is provided a system clock signal and its complement, CLK and CLKF, and is configured to change the count according to the CLK and CLKF signals. CLK and CLKF are in the DLL time domain and may allow for accurately placing time edges in the DLL time domain. The counter circuit  410  may be any suitable counter known in the art. The counter circuit  410  may be further configured to provide a phase shifted C 1  signal C 1 P 5 . The C 1 P 5  signal is shifted later relative to the C 1  signal by one-half a clock period of a system clock signal CLK. 
         [0021]    The C 0 , C 1 , and C 1 P 5  signals are provided to a lockout circuit  415 , that is coupled to a RdDLL/WrDLL circuit  420 . The lockout circuit  415  includes similar circuits as the lockout circuit  115 , and the RdDLL/WrDLL circuit  420  includes similar circuits as the RdDLL/WrDLL circuit  120  included in the memory command circuit  200  of  FIG. 2 . The same reference number is used for these circuits. The lockout circuit  415  further includes NAND gate  435  and a clocked inverter  430 . The clocked inverter  430  is clocked by the CLK and CLKF signals to provide an output to an OR gate  425 . The output of the clocked inverter  430  (and the input of the OR gate  425 ) is provided the C 1 P 5  signal from the counter circuit  410 . The lockout circuit  415  further includes a NOR gate  417  that is provided the C 0  and C 1  signals from the counter circuit  410 , and the NOR gate  417  provides an output to the NAND gate  419 . NAND gate  419  also receives an input from inverter  215  and provides an output to the OR gate  425 . An output of the OR gate  425  and the NOR gate  220  are provided to the RdDLL/WrDLL circuit  420 , which in turn provides the RdDLL  130  and WrDLL  135  signals. 
         [0022]    The lockout circuit  415  may be configured such that a write signal on Rd/Wr  110  is masked by the lockout circuit  415  for some number of clock cycles from the rising edge of the RdDLL  130  signal. The number of clock cycles may be determined by the command extension scheme used. In the current example, read and write commands are stretched to 4 clock cycles, and the counter circuit  410  is a 2-bit counter that counts four values. However, commands may be stretched more or less, depending on the command extension scheme used. After some number of clock cycles (e.g., four clock cycles for the present example), the Rd/Wr  110  is sampled again to determine if the next command on CmdDLL  105  is a read or a write command. The counter circuit  410  may allow the lockout circuit  415  to prevent the truncation of read commands, and prevent the lockout circuit  415  to cause the RdDLL/WrDLL circuit  420  to miss a subsequent write command when the read command and write command are merged on CmdDLL  105 . 
         [0023]    The foregoing description is a possible implementation of the lockout circuit  415  and a counter counter  410 . The disclosure may be implemented with alternative logic gates and command types without departing from the scope of the present disclosure. 
         [0024]      FIG. 5  is a timing diagram  500  illustrating various signals during the operation of the memory command circuit  400  according to an embodiment of the invention. External clock  505  corresponds to the system domain clock. External cmd  510  illustrates the read and write commands received by the memory. A read command is received at time T 0  and a write command is received at time T 5 . Read cmd decode signal  515  and Write cmd decode signal  520  illustrate the decoded commands internal to the memory resulting from the external commands. For example, shortly after the read command is received, an internal command extending between shortly after time T 0  and time T 2  represents an internal command corresponding to the read command received at time T 0 . Similarly, shortly after the write command is received, an internal command extending between shortly after time T 5  and time T 7  represents an internal command corresponding to the write command received at time T 7 . Stretched read command  525  and stretched write command  530  illustrate the internal read and write commands that have been extended. In the example operation illustrated in the timing diagram  500 , the stretched read command  525  and stretched write command  530  extend over to four clock cycles, for example, between shortly after time T 0  and T 5  for the stretched internal read command  525 . The read/not write signal  545  corresponds to the state of Rd/Wr  110 . For example, the read/not write signal  545  is at a high logic level to indicate a read command, and changes to a low logic level just before time  14  to indicate a write command. 
         [0025]    The combined command in clock domain  535  is the combination of the stretched read command  525  and the stretched write command  530 . The state of CmdDLL  105  is illustrated by the combined command in DLL domain  550 . The combined command in DLL domain  550  is based on the combined command in clock domain  535  (e.g., delayed therefrom). Note that in this example the combined command in DLL domain  550  does not switch between high and low logic states between the stretched read command  525  and subsequent stretched write command  530  commands transiting on CmdDLL  105 . The hold signal in DLL domain  540  is the output of the lockout circuit  415  with the counter circuit  410 . In this example, the hold signal in DLL domain  540  changes to a logic high at time T 3  half a clock cycle after the combined command in DLL domain  550  transitions to logic high at time T 1  for the received read command. The hold signal in DLL domain  540  transitions to a low logic level at time T 6 , corresponding to when the read command has finished transiting CmdDLL  105 , and the write command begins, also at time T 6 . In the example counter circuit  410  described in  FIG. 4 , the counter is a two-bit counter, accordingly, the hold signal in DLL domain  540  remains at a high logic level for three and a half clock cycles. Other time durations of the hold signal in DLL domain  540  are possible with different counter circuit configurations. The hold signal in the DLL domain  540  allows for the read/not write signal  545  to switch logic states within the margin  555  between time T 3  and time T 6 , to indicate the subsequent write command without truncating the current read command. For example, as illustrated in  FIG. 5 , the read/not write signal  545  transitions to a low logic level at T 4  before the command corresponding to the read command transits at time T 6 . The lockout circuit  415  triggers resampling of the read/not write signal  545  on Rd/Wr  110  to allow the RdDLL/WrDLL circuit  120  to capture the incoming write command without the CmdDLL  105  changing from a high logic level to a low logic level between successive commands. 
         [0026]    The above embodiments may increase the time margin within which the Rd/Wr  110  signal may be placed without adversely affecting closely spaced commands. This may be advantageous as timing specifications for memory systems continue to tighten. 
         [0027]      FIG. 6  illustrates a portion of a memory  600  according to an embodiment of the present invention. The memory  600  includes an memory array  602 , which may be, for example, volatile memory cells (e.g., DRAM memory cells, SRAM memory cells, etc.), non-volatile memory cells (e.g., flash memory cells, PCM cells, etc.), or some other types of memory cells. The memory  600  includes a command decoder  606  that receives memory commands through a command bus  608  and provides (e.g. generates) corresponding control signals within the memory  600  to carry out various memory operations. Row and column address signals are provided (e.g. applied) to the memory  600  through an address bus  620  and provided to an address latch  610 . The address latch then outputs a separate column address and a separate row address. 
         [0028]    The row and column addresses are provided by the address latch  610  to a row address decoder  622  and a column address decoder  628 , respectively. The column address decoder  628  selects bit lines extending through the memory array  602  corresponding to respective column addresses. The row address decoder  622  is connected to word line driver  624  that activates respective rows of memory cells in the memory array  602  corresponding to the received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to the read/write circuitry  630  to provide read data to an input/output data block  934  via an input-output data bus  640 . Write data are provided to the memory array  602  through the I/O data block  634  and the memory array read/write circuitry  630 . 
         [0029]    The memory  600  further includes a memory command circuit  614 . The memory command circuit  614  may be implemented using a memory command circuit according to an embodiment of the invention, for example, the memory command circuits illustrated in  FIGS. 1 ,  2 , and  4 . The memory command circuit  614 , which is shown in  FIG. 6  as being included in the command decoder  606 , but is not limited to such a configuration, provides internal command signals for executing memory operations. The command decoder  606  responds to memory commands provided to the command bus  608  to perform various operations on the memory array  602 . In particular, the command decoder  606  is used to provide internal command signals, which may correspond to signals RdDLL  130  and WrDLL.  135  in the example embodiment illustrated in  FIG. 2 , to read data from and write data to the memory array  602 . 
         [0030]    Those of ordinary skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or processor executable instructions depends on the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. 
         [0031]    The previous description of the disclosed embodiments is provided to enable a person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.