Abstract:
A current bias circuit and a current bias start-up circuit thereof are disclosed. The bias start-up circuit supplies a compensation current to the bias circuit to compensate the leakage current of the current bias circuit during activation and turns off the compensation current after start-up. Accordingly, the bias start-up circuit could compensate the leakage current of the current bias circuit and the bias start-up circuit could reduce the power consumption.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims the priority benefit of Taiwan application serial no. 94134930, filed on Oct. 6, 2005. All disclosure of the Taiwan application is incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of Invention 
   The present invention relates to an analog circuit, and, more particularly, to a current bias circuit and a current bias start-up circuit thereof. 
   2. Description of Related Art 
   Generally speaking, a current mirror serves as a bias circuit in an analog circuit. A start-up circuit is needed by this kind of bias circuit to ensure the proper operation of the circuit. 
     FIG. 1  is a diagram of a conventional bias circuit. Referring to  FIG. 1 , the conventional bias circuit includes a current bias circuit  10  and a bias start-up circuit  11  wherein the current bias circuit  10  includes P-type transistors MP  101  and MP 102 , N-type transistors MN 101 , MN 102 , MN 103 , and MN 104 , diodes D 101 , D 102 , and D 103 . The bias start-up circuit  11  includes diodes D 111 , D 112 , and a resistor R 111 . 
   During activation, the bias start-up circuit  11  supplies the current I PU  passing through the diodes D 111  and D 112  to the current mirror formed of the N-type transistors MN 103  and MN 104  in the current bias circuit  10  to turn on the bias circuit. The resistor R 111  is used for limiting the current I PU . 
   Generally speaking, there is a working range, e.g. from 7V to 15V, for the power supply voltage of an integrated circuit. Referring to the bias start-up circuit  11  in  FIG. 1 , the start-up circuit works with lower current when the power supply voltage is working at 7V. When the power supply voltage is working at 15V, the working current of the start-up circuit may increase 2 times, which results in power consumption in the integrated circuit. 
     FIG. 2  is a diagram of another conventional bias circuit. Referring to  FIG. 2 , the bias circuit includes a current bias circuit  20  and a bias start-up circuit  21  wherein the current bias circuit  20  includes P-type transistors MP 201  and MP 202 , N-type transistors MN 201 , MN 202 , MN 203 , and MN 204 , diodes D 201 , D 202 , and D 203 . The bias start-up circuit  21  includes an inverter INV 21  and an N-type transistor MN 211 . The inverter INV 21  comprises a P-type transistor MP 212  and an N-type transistor MN 213 . 
   During activation, the input voltage level of the input terminal of the inverter INV  21 , the gates of the P-type transistor MP 212  and the N-type transistor MN 213 , is at low voltage level, so that the output terminal of the inverter INV 21 , which is the nodes where the sources/drains of the P-type transistor MP 212  and the N-type transistor MN 213  are coupled to each other, outputs high voltage level to the gate of the N-type transistor MN 211  to turn on the N-type transistor MN 211 . Since the N-type transistor is turned on, the voltage level at the node where the gates of the P-type transistors MP 201  and MP 202  are coupled is pulled down. The P-type transistors MP 201  and MP 202  are turned on forcedly to activate the bias circuit. 
   Upon completion of activation, the input terminal of the inverter INV 21  receives high voltage level so that the node where the sources/drains of the P-type transistor MP 212  and the N-type transistor MN 213  are coupled, outputs low voltage level to the gate of the N-type transistor MN 211 . Additionally, the gate of the N-type transistor MN 211  is turned off. The advantage of the bias start-up circuit is that no additional power consumption upon completion of activation. 
   However, the circuit discussed above does not provide much solution for leakage current. Generally speaking, an integrated circuit produces leakage current when it is illuminated. The circuit in  FIG. 2  cannot be turned off when the PN Junction formed of the N-type transistors MN 201  and MN 203  produces leakage current. 
   SUMMARY OF THE INVENTION 
   Accordingly, the present invention is directed to provide a current bias start-up circuit for turning on a current bias circuit. 
   According to another aspect of the present invention, a current bias circuit, which can be turned on even when there is leakage current in the circuit, is provided. 
   The present invention provides a current bias start-up circuit for turning on a current source including N current mirrors, each current mirror includes a first transistor and a second transistor, the drain of the first transistor is coupled to the gate of the first transistor, the gate of the second transistor is coupled to the gate of the first transistor, the sources of the first transistor and the second transistor of the first current mirror are coupled to a first voltage. The current bias start-up circuit includes a third transistor, a resistor, and a fourth transistor. The gate of the third transistor is coupled to the gate of the second transistor of the first current mirror, and the first source/drain of the third transistor is coupled to the first voltage. The first terminal of the resistor is coupled to the second source/drain of the third transistor, and the second terminal of the resistor is coupled to a second voltage. The gate of the fourth transistor is coupled to the first terminal of the resistor, the first source/drain of the fourth transistor is coupled to the first voltage, the second source/drain of the fourth transistor is coupled to the gate of the first transistor of the K th  current mirror, wherein N and K are natural numbers and 2&lt;K&lt;N. 
   According to the current bias start-up circuit in an exemplary embodiment of the present invention, the resistor includes a fifth transistor. The gate of the fifth transistor is coupled to the first voltage, the first source/drain of the fifth transistor is the first terminal of the resistor, and the second source/drain of the fifth transistor is another terminal of the resistor. 
   The present invention provides a current bias circuit including a current source, a third transistor, a resistor, and a fourth transistor. The current source includes N current mirrors, and each current mirror includes a first transistor and a second transistor. The drain of the first transistor is coupled to the gate of the first transistor. The gate of the second transistor is coupled to the gate of the first transistor. The sources of the first transistor and the second transistor of the first current mirror are coupled to the first voltage. The gate of the third transistor is coupled to the gate of the second transistor of the first current mirror, and the first source/drain of the third transistor is coupled to the first voltage. The first terminal of the resistor is coupled to the second source/drain of the third transistor, and the second terminal of the resistor is coupled to the second voltage. The gate of the fourth transistor is coupled to the first terminal of the resistor, the first source/drain of the fourth transistor is coupled to the first voltage, the second source/drain of the fourth transistor is coupled to the gate of the first transistor of the K th  current mirror, wherein N and K are natural numbers and 2&lt;K&lt;N. 
   According to the current bias circuit in an exemplary embodiment of the present invention, the aforementioned resistor includes a fifth transistor, the gate of the fifth transistor is coupled to the first voltage, the first source/drain of the fifth transistor is the first terminal of the resistor, and the second source/drain of the fifth transistor is another terminal of the resistor. 
   Since the present invention adopts the structure of supplying a current to the bias circuit to compensate the leakage current during activation and to turn off the current upon completion of activation, the circuit can not only compensate the leakage current, but also reduce power consumption. 
   In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below. 
   It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
       FIG. 1  is a diagram of a conventional bias circuit. 
       FIG. 2  is a diagram of another conventional bias circuit. 
       FIG. 3  is a diagram of a current bias circuit according to an embodiment of the present invention. 
       FIG. 4  is a diagram of a current bias circuit according to another embodiment of the present invention. 
   

   DESCRIPTION OF EMBODIMENTS 
     FIG. 3  is a diagram of a current bias circuit according to an embodiment of the present invention. Referring to  FIG. 3 , the current bias circuit includes a bias current source  31  and a bias start-up circuit  30  according to the embodiment of the present invention. The bias current source  31  includes 3 current mirrors MR 31  (an embodiment, not intended to limit the present application), MR 32 , and MR 33 , and diodes D 31 , D 32 , and D 33  and each current mirror includes a first transistor M 311  and a second transistor M 312 . The drain of the first transistor M 311  is coupled to the gate of the first transistor M 311 . The gate of the second transistor M 312  is coupled to the gate of the first transistor M 311 . The sources of the first transistor M 311  and the second transistor M 312  of the first current mirror are coupled to a first voltage, such as VDD. 
   The bias start-up circuit  30  includes a third transistor MP 303 , an impedance device in which a resistor R 301  is used as an example in the present embodiment, and a fourth transistor MP 304 . The gate of the third transistor MP 303  is coupled to the gate of the second transistor M 312  of the first current mirror MR 31 , and the first source/drain of the third transistor MP 303  is coupled to the first voltage VDD. The first terminal A 30  of the resistor R 301  is coupled to the second source/drain of the third transistor MP 303 , and the second terminal B 30  of the resistor R 301  is coupled to the second voltage, such as the ground voltage GND. The gate of the fourth transistor MP 304  is coupled to the first terminal A 30  of the resistor R 301 , the first source/drain of the fourth transistor MP 304  is coupled to the first voltage VDD, and the second source/drain of the fourth transistor MP 304  is coupled to the gate of the first transistor M 311  of the second current mirror. 
   In the present embodiment, the second source/drain of the fourth transistor MP 304  is coupled to the gate of the first transistor M 311  of the second current mirror. However, it should be understood by those skilled in the art that the second source/drain of the fourth transistor MP 304  can be coupled to the gate of the first transistor M 311  of the third current mirror. Accordingly, the present invention is not limited to the coupling structure discussed above. In addition, the third transistor MP 303  and the fourth transistor MP 304  of the present embodiment are embodied with P-type metal-oxide-semiconductor field-effect transistors, and the first transistor M 311  and the second transistor M 312  of the first current mirror MR 31  are embodied with P-type metal-oxide-semiconductor field-effect transistors. 
   Upon activating the circuit, the gate voltage of the first transistor M 311  of the first current mirror MR 31  approaches to VDD to turn off the third transistor MP 303 . Because the second terminal B 30  of the resistor R 301  is coupled to the ground voltage GND, the fourth transistor MP 304  is turned on and the current I 1  is supplied from the power supply VDD to the current mirror MR 32  of the bias current source  31  through the fourth transistor MP 304 . In addition, the current I 1  can be used for compensating the leakage current of the bias current source  31 , such as the leakage current of the second current mirror and the third current mirror caused by diodes D 31 , D 32 , and D 33 . 
   Upon completion of activation, the voltage received by the gate of the third transistor MP 303  drops slightly to turn on the third transistor MP 303 . Since the third transistor MP 303  is turned on, the current I 2  passes through the resistor R 301 , which results in a voltage drop V AB . The voltage drop V AB  will turn off the fourth transistor; therefore, no additional power consumption upon completion of activation. 
     FIG. 4  is a diagram of a current bias circuit according to another embodiment of the present invention. The difference between  FIG. 4  and  FIG. 3  is that the resistor R 301  in  FIG. 3  is disposed as the impedance device while the impedance device according to embodiment of  FIG. 4  is a fifth transistor M 415 . Additionally, in  FIG. 3 , the fourth transistor MP 304  is coupled to the second current mirror MR 32  while the fourth transistor MP 404  in  FIG. 4  is be coupled to the third current mirror MR 43 . The gate of the fifth transistor M 415  is coupled to the first voltage VDD, the first source/drain of the fifth transistor M 415  is the first terminal A 30  of the resistor R 301  in  FIG. 3 , and the second source/drain of the fifth transistor is the second terminal B 30  of the resistor R 301  in  FIG. 3 . 
   The way the current bias activating the circuit according to the embodiment in  FIG. 4  is similar to that of  FIG. 3 . Upon activating the circuit, the leakage current of the bias current source  41 , such as the leakage current of the third current mirror produced by diodes D 41 , D 42 , and D 43 , is compensated by the current I passing through the fourth transistor MP 404 . Upon completion of activation, the third transistor MP 403  is turned on to produce a voltage drop V AB  on the fifth transistor M 415  to turn off the fourth transistor MP 404 , which is similar to that in  FIG. 3 . 
   In view of the foregoing, according to the embodiments of the present invention, during activation a current is supplied to the bias circuit to compensate for the leakage current and the current is turned off upon completion of activation. Accordingly, the circuit can not only compensate for the leakage current, but also reduce power consumption. 
   It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.