Abstract:
The invention comprises a in line memory module which includes connections on its surface so that either a standard Electrically Erasable Programmable Read Only Memory (EEPROM), or a &#34;daisy chain&#34; EEPROM can be utilized with the memory module.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a wiring configuration for memory module, for example, a Single (SIMM) or Dual In-Line Memory Module (DIMM). 
     2. Description of the Related Art 
     Memory Modules (e.g. Single In Line Memory Modules (SIMMs), Dual In Line Memory Modules (DIMMs), etc.) are an essential part of almost every computer. In fact, the random access memory (RAM) of most computers is comprised mainly of memory modules. Computer mother boards often include expansion ports for the placement of additional memory modules to increase the memory capacity of the computer. The memory module is essentially a circuit board with memory devices affixed to one or both sides thereof. These memory devices are typically DRAMs, but may also comprise other similar memories (e.g., SDRAMs, SRAMS, etc.) The circuit board also include terminals, or &#34;pins&#34; which facilitate communications between the memory devices and the rest of the computer (e.g., CPU, etc.). In Line Memory Modules (IMMs) are the most popular memory modules for use in computer systems. They include SIMMs and DIMMs. For convenience the ensuing discussion describes IMMs as representative of memory modules with which the invention may be used. 
     Most IMMs on the market today include an Electrically Erasable Programmable Read Only Memory (EEPROM) containng configuration information relating to the IMM. One of the main functions the EEPROM performs is serial presence detect (SPD) commonly used in computer systems. SPD is a method by which a IMM identifies itself to a (CPU of a computer through information stored in the EEPROM. The SPD is performed by a SPD processor in conjunction with the EEPROMs of the IMMs. When the computer first boots up, the SPD controller reads out the EEPROM of each memory module in order to identity to the CPU how much and what type of memory is installed. 
     FIG. 1 shows an exemplary IMM with an associated EEPROM attached thereto. The EEPROM typically includes 256 bytes of storage capacity. The first 128 bytes are used to store industry standard information relating to the IMM. The contents of each of these 128 bytes is specified by the Joint Electron Device Engineering Council (JEDEC). The other 128 bytes are usually reserved for use by either the manufacturer or purchaser of the IMM. Using a conventional JEDEC protocol, the EEPROMs of only eight IMMs can be addressed by the SPD controller because of the limited number of address pins (3) on the EEPROM and the computer bus structure. This causes a problem because it limits the amount of memory that can be utilized by the computer. 
     Recently, a new type of memory module architecture has been developed which allows more than eight memory modules and their associated EEPROMs to be addressed by a CPU. This new module is referred to as a &#34;daisy chain&#34; module because it has the capability to link together with other memory modules to increase memory capacity of a computer. The &#34;daisy chain&#34; memory module contains an EEPROM which is different from the EEPROM of the JEDEC specification and includes pins not present on traditional EEPROMs, which provide ports for the clock signals of several EEPROMs to be serially interconnected. By linking together the multiple EEPROMs of the multiple memory modules, the number of memory modules which can be addressed becomes unlimited. This new memory architecture is beginning to gain popularity and is being deployed in IMMs. 
     Since most IMMs were developed with configurations for the JEDEC standard only at present a memory module manufacturer must stock different circuit boards for JEDEC type of memory module and associated EEPROM as well as for a &#34;daisy chain&#34; type of memory module and its associated EEPROM. There is accordingly a current need for an IMM mounting board which can support either the JEDEC standard EEPROM or the newer &#34;daisy chain&#34; EEPROM, yet be universally accepted by computer systems designed for use with either architecture. There is also currently a need for a method for transforming exisitng circuit boards so that they can be used with either the JEDEC standard or the &#34;daisy chain&#34; EEPROM. 
     SUMMARY OF THE INVENTION 
     The present invention relates to wiring placed on the surface of a memory module, such as an IMM mounting board, for accommodating either standard EEPROM or a &#34;daisy chain&#34; EEPROM, while providing the proper pin-out terminals for a computer system no matter which of the two types of memory modules the system is designed for. Accordingly, the same mounting board can be used for providing the standard JEDEC memory module or a &#34;daisy chain&#34; type of memory module. 
     The above and other advantages and features of the present invention will be better understood from the following, detailed description of the preferred embodiments of the invention which is provided in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a representative prior art memory module; 
     FIG. 2 illustrates a representative memory module employing the present invention; and, 
     FIG. 3 illustrates the relevant wiring of a portion of the circuit board of the memory module employing the present invention in detail. 
     FIG. 4 illustrates a computer system utilizing the memory module constructed in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 shows a memory module 100 of the present invention. The memory module is shown as an IMM for purposes of further explanation. The IMM includes multiple memory chips (e.g. DRAMs) 110, and multiple edge connection pins 120 for mating with a memory socket of a computer system. The memory chip interconnect wiring pattern is omitted from FIG. 2 for sake of clarity. The IMM 100 also includes two land patterns 130, 140 for mounting of EEPROM chips. One land pattern 130 is for the placement of a JEDEC standard EEPROM chip, and the other land pattern 140 is for the placement of the &#34;daisy chain&#34; EEPROM chip. Therefore, by utilizing the present IMM 100, either a JEDEC standard EEPROM or a &#34;daisy chain&#34; EEPROM can be attached to the IMM circuit board, as will be explained in detail below. 
     Five connection pins on the right end of the FIG. 2 IMM enable the SPD processor to access the EEPROM, whether it be of the JEDEC standard or the &#34;daisy chain&#34; variety. FIG. 3 shows the IMM circuit board of FIG. 2 enlarged to show the circuit board electrical connections which connect the EEPROM terminals to the electrical contacts of the five edge connection pins of the IMM 100. The first pin (from left to right), SCL, is an input pin which provides a clock signal to the SCL terminals of both types of EEPROMs. The second pin, SDA, is an input/output pin which provides for data transfer to and from both types of EEPROMs. The last three pins, SA0-SA2, are used for addressing of the EEPROMs of the JEDEC standard IMM. These pins are input address pins which specify which IMM EEPROM is being addressed by the SPD processor. The SA0-SA2 pins are only used with the JEDEC standard EEPROM. Because of the limited number of address pins, the maximum number of IMM EEPROMs that can be addressed is eight (8). 
     For &#34;daisy chain&#34; memory modules the EEPROMs of the IMMs are addressed in sequence using an output clock from an upstream EEPROM to provide an input clock for the next in sequence EEPROM. A first clock signal from the SPD processor is sent to the SCL terminal of the EEPROM of a first memory module in a daisy chain. After that EEPROM data is read out over a data line SDA common to all memory modules and then the first addressed EEPROM sends a clock signal on line SCLO to the SCL input terminal of the EEPROM of the next memory module in the chain causing it to read out data to the SPD processor on line SDA. This sequence is repeated until all EEPROMs of all memory modules are read. 
     Thus, for a JEDEC type memory module terminals SCL, SDA, SAO, SA1 and SA2 are required to address the memory module EEPROM, while for a &#34;daisy chain&#34; type memory module terminals SCL, SDA and SCLO are required. FIG. 3 illustrates how both sets of terminals are integrated on a single circuit board using one wiring pattern for the JEDEC standard EEPROM and one wiring pattern for the &#34;daisy chain&#34; EEPROM. 
     The SA0/SCLO, SCL and SDA pins of the circuit board are the only pills shared between the JEDEC standard and the &#34;daisy chain&#34; EEPROMs. As explained above, the &#34;daisy chain&#34; EEPROM does not require address pins SA0-SA2, it does, however, require a SCLO pin. The SCL0 pin is used to supply a clock signal to the SCL input of the next &#34;daisy chain&#34; EEPROM in the chain. Therefore, when the JEDEC EEPROM is placed on land pattern 130, the circuit board pin SA0 is used for address control, but when the &#34;daisy chain&#34; EEPROM is placed on land pattern 140, the SA0 pin is used for the SCLO output clock signal. 
     The &#34;daisy chain&#34; EEPROM land pattern 140, includes terminals SCLO, Vss, Vcc, SCL and SDA. As explained above, the terminals SCL and SDA are for receiving a clock signal and for transferring data, respectively. The Vss terminal provides a ground connection for the EEPROM, and Vcc provides c power supply voltage for the EEPROM. The SCL0 terminal is the key element of the &#34;daisy chain&#34; EEPROM. The SCL0 terminal provides a clock output signal which is applied to the SCL input of the next in sequence &#34;daisy chain&#34; EEPROM. 
     The conventional JEDEC standard EEPROM includes terminals SCL, SDA, SA0, SA1, SA2, Vss, Vcc, and WP. The JEDEC, standard EEPROM shares common terminals SCL, SDA, Vss, and Vcc with the &#34;daisy chain&#34; EEPROM and therefore further discussion of these terminals will be omitted. The JEDEC standard EEPROM further includes address input terminals SA0-SA2. These terminals receive signals from the SPD processor (not shown) which specifies which one of the eight IMMs is being addressed at that time. The JEDEC standard EEPROM also includes a write protect terminal (WP), which is used to prevent overwriting of the information stored in the EEPROM. 
     The normal and the &#34;daisy chain&#34; EEPROM share terminals SDA and SCL in common, and therefore the SDA and SCL pins of the IMM are connected to the respective SCL and SDA terminals of both EEPROM land patterns 130, 140 (See FIG. 3). The SA1-SA2 pins of the IMM are only connected to the SA1-SA2 terminals of the normal EEPROM land pattern 130. The SA0/SCL0 shared pin of the IMM is connected to the SCL0 terminal of the &#34;daisy chain&#34; EEPROM land pattern 140, and the SA0 terminal of the normal EEPROM land pattern 130. Thus, if a JEDEC standard EEPROM is placed on land pattern 130, the wiring configuration allows the EEPROM to work properly with the memory module 100. Similarly, if a &#34;daisy chain&#34; EEPROM is placed on land pattern 140, the present wiring configuration allows the EEPROM to work properly with the memory module 100. 
     FIG. 4 illustrates a processor-based system 200 including memory modules, here IMMs 208 constructed in accordance with the present invention. The processor-based system 200 may be a computer system, a process control system or any other system employing a processor and associated memory. The processor-based system includes a central processing unit (CPU) 202, e.g., a microprocessor, that communicates with the IMM and I/O devices 204, 206 over a bus 220. The processor-based system 200 also includes read only memory (ROM) 210, and may include peripheral devices such as a floppy disk drive 212 and a compact disk (CD) drive 214 that also communicate with the CPU 202 over the bus 220 as is well known in the art. An SPD processor (not shown) is connected between the IMMs 208 and the bus 220 to facilitate information transfer. In other words, when the processor-based system is first activated (i.e. switched on), the SPD processor works in conjunction with the EEPROMs of the IMMs to determine what type and kind of memory is attached to the system and to relay that information to the CPU 202 via bus 220. 
     It should be noted that although the invention has been described in terms of fabricating an entirely new circuit board which can connect to either JEDEC standard or &#34;daisy chain&#34; EEPROMs, the present invention also encompasses a method by which existing circuit boards, with JEDEC standard terminals, can be altered to accommodate both types of EEPROMs, by forming an additional wiring pattern on the existing circuit board for the &#34;daisy chain&#34; EEPROM. The additional wiring pattern would be fabricated to connect to the JEDEC standard EEPROM in the same way as described above with reference to FIG. 3. 
     While the invention has been described in detail in connection with the preferred embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.