Abstract:
A voltage controlled oscillator outputting a differential signal includes: an inductor connected to a first power supply supplying first voltage; first and second transistors for differential switching; first and second variable capacitors connected to the inductor in parallel; a third transistor of which a gate electrode is connected to a first node; and a fourth transistor of which a gate electrode is connected to a second node. When bias voltage is applied to the gate electrode of the first transistor to be turned on, negative resistance is generated by voltage applied to the first capacitor and the second capacitor through the first transistor. When voltage outputted through the first node is applied to the gate electrode of the third transistor to be turned on, the voltage is additionally applied to the first capacitor and the second capacitor by the third transistor to increase the negative resistance.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of Korean Patent Application No. 10-2009-0042587 filed in the Korean Intellectual Property Office on May 15, 2009, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    (a) Field of the Invention 
         [0003]    The present invention relates to a differential Colpitts voltage controlled oscillator for improving negative resistance, and more particularly, to a voltage controlled oscillator for improving negative resistance of a Colpitts oscillator. 
         [0004]    (b) Description of the Related Art 
         [0005]    In recent years, a complementary metal-oxide semiconductor (CMOS) process technology has been rapidly being developed according to a request for integration by technological convergence. However, low voltage and an increase of flicker noise by the CMOS process technology are being magnified as a problem to be solved in order to design an analog circuit. In particular, a decrease of output voltage and the increase of the flicker noise may cause deterioration of phase noise performance at the time of designing a voltage controlled oscillator by the CMOS process technology. 
         [0006]    As such, a Colpitts voltage controlled oscillator is being attracting attention as a structure for solving the problem caused at the time of designing the voltage controlled oscillator by the CMOS process technology, but start-up current and power consumptions may be large and the phase noise performance may deteriorate due to small oscillation amplitude. 
         [0007]    Accordingly, a design technology of a voltage controlled oscillator is required, which is capable of reducing the start-up current and power consumptions and improving the phase noise performance of the oscillator at the operating point of the maximum saturation region. 
         [0008]    The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention has been made in an effort to a Colpitts voltage controlled oscillator having an advantage of improving negative resistance. 
         [0010]    An exemplary embodiment of the present invention provides a voltage controlled oscillator outputting a differential signal that includes: 
         [0011]    an inductor connected to a first power supply supplying first voltage; first and second transistors of which drain electrodes are connected to one terminal and the other terminal of the inductor, respectively and for differential switching; first and second variable capacitors that are connected between the first transistor and the second transistor in serial and connected to the inductor in parallel; a third transistor of which a drain electrode is connected to a source electrode of the first transistor and a gate electrode is connected to a first node connected to the inductor, the second variable capacitor, and the second transistor; and a fourth transistor of which a drain electrode is connected to a source electrode of the second transistor and a gate electrode is connected to a second node connected to the inductor, the first variable capacitor, and the first transistor. 
         [0012]    Another embodiment of the present invention provides a voltage controlled oscillator outputting a differential signal that includes: 
         [0013]    an inductor connected to a first power supply supplying first voltage; first and second transistors that are differentially turned on and turned off by being connected to the inductor, respectively; a third transistor of which a drain electrode is connected to a source electrode of the first transistor and a gate electrode is connected to a first node connected to the inductor and the second transistor; a fourth transistor of which a drain electrode is connected to a source electrode of the second transistor and a gate electrode is connected to a second node connected to the inductor and the first transistor; a first capacitor that is connected to the first transistor in parallel and of which one terminal is connected to the second node; a first variable capacitor and a second capacitor of which terminals are connected to the first capacitor and a third node connected with the source electrode of the first transistor and the drain electrode of the third transistor; a third capacitor that is connected to the second transistor in parallel and of which one terminal is connected to the first node; and a second variable capacitor and a fourth capacitor of which terminals are connected to the third capacitor and a fourth node connected with the source electrode of the second transistor and the drain electrode of the fourth transistor, wherein the first variable capacitor is connected with the second capacitor in parallel and the second variable capacitor is connected with the fourth capacitor in parallel. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a diagram showing one example of a known Colpitts oscillator; 
           [0015]      FIG. 2  is a diagram showing another example of a known Colpitts oscillator; 
           [0016]      FIG. 3  is a diagram schematically showing one example of a differential Colpitts oscillator according to an embodiment of the present invention; 
           [0017]      FIG. 4  is a diagram schematically showing another example of a differential Colpitts oscillator according to an embodiment of the present invention; 
           [0018]      FIG. 5  is a diagram showing one example of output voltage of a differential Colpitts oscillator according to an embodiment of the present invention; 
           [0019]      FIG. 6  is a diagram showing one example of a measurement value of phase noise of a differential Colpitts oscillator according to an embodiment of the present invention; and 
           [0020]      FIGS. 7A and 7B  are diagrams showing one example of phase noise performance of a differential Colpitts oscillator according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0021]    In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. 
         [0022]    In this specification and the claims that follow, when it is described that an element is “coupled” to another element, the element may be “directly coupled” to the other element or “electrically coupled” to the other element through a third element. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. 
         [0023]      FIG. 1  is a diagram showing one example of a known Colpitts oscillator and  FIG. 2  is a diagram showing another example of a known Colpitts oscillator. 
         [0024]    The known Colpitts oscillator  100  shown in  FIG. 1  has a single output structure and includes a transistor M 11 , an inductor L 11 , capacitors C 11  and C 12 , and a current source I 11 . 
         [0025]    The Colpitts oscillator  100  has excellent phase noise performance, but is not widely used due to a problem in that start-up current and power consumptions are large due to small negative resistance. 
         [0026]    Meanwhile, the known Colpitts oscillator  200  shown in  FIG. 2  has a differential output structure and includes transistors M 21 , M 22 , M 23 , and M 24 , an inductor L 21 , capacitors C 21 , C 22 , C 23 , and C 24 , variable capacitors C var11  and C var12 , and a current source I 21 . 
         [0027]    The Colpitts oscillator  200  consumes low power by improving the negative resistance according to the differential output structure unlike the Colpitts oscillator  100  shown in  FIG. 1 . That is, the Colpitts oscillator  200  is designed to connect gate electrodes of the transistor M 23  and the transistor M 24  to an output terminal OUT I+  and connect gate electrodes of the transistor M 21  and the transistor M 22  to an output terminal OUT I−  to increase the negative resistance and reduce the start-up current and power consumptions by the increase of the negative resistance. However, the Colpitts oscillator  200  has a problem in that phase noise performance deteriorates at an operating point of a maximum saturation region. 
         [0028]    Hereinafter, referring to  FIGS. 3 to 7B , a differential Colpitts oscillator  300  according to an embodiment of the present invention will be described in detail, which is capable of reducing the start-up current and power consumptions and improving the phase noise performance of an oscillator at the operating point of the maximum saturation region by improving the negative resistance and oscillation amplitude while having the differential output structure. 
         [0029]      FIG. 3  is a diagram schematically showing one example of a gm-boosted differential drain-to-source feedback Colpitts voltage controlled oscillator, that is, a differential Colpitts oscillator according to an embodiment of the present invention. 
         [0030]    In  FIG. 3 , transistors M sw1 , M sw2 , M gm1 , and M gm2  of the differential Colpitts oscillator  300  are shown as an n-channel metal oxide semiconductor (NMOS) transistor, but the present invention is not limited thereto and other transistors having a similar function to the NMOS transistor may be used as the transistors M sw1 , M sw2 , M gm1 , and M gm2  instead of the NMOS transistor. 
         [0031]    As shown in  FIG. 3 , the differential Colpitts oscillator  300  according to the embodiment of the present invention includes a pair of transistors M sw1  and M sw2  for generating the negative resistance and a pair of transistors M gm1  and M gm2  for increasing the negative resistance that are connected to each other in the differential output structure, an inductor L 1 , variable capacitors C var1  and C var2 , capacitors C 1 , C 2 , C 3 , and C 4 , and a current source I 1 . 
         [0032]    The inductor L 1  is connected to a power supply VDD and one terminal of the inductor L 1  is connected to a drain electrode of the transistor M sw1  and the other terminal of the inductor L 1  is connected to a drain of the transistor M sw2 . One terminal of the variable capacitor C var1  is connected to a node NA which is a contact point between the drain electrode of the transistor M sw1  and one terminal of the inductor L 1  and the other terminal is connected to one terminal of the variable capacitor C var2 . The other terminal of the variable capacitor C var2  is connected to a node NC which is a contact point between the drain electrode of the transistor M sw2  and the other terminal of the inductor L 1 . At this time, voltage V tune  is supplied to the variable capacitors C var1  and C var2  to change values of the capacitors and the frequency of an output signal is changed depending on the changed capacitor value. Herein, the inductor L 1  and the variable capacitors C var1  and C var2  are connected to each other in parallel. 
         [0033]    The drain electrode of the transistor M sw1  is connected to one terminal of the inductor L 1  and a source electrode of the transistor M sw1  is connected to a drain electrode of the transistor M gm1 . At this time, direct current DC as bias voltage V bias  is applied to a gate electrode of the transistor M sw1  and an output terminal OUT I+  is connected to the node NA. One terminal of the capacitor C 1  is connected to the node NA and the output terminal OUT I+  and the other terminal of the capacitor C 1  is connected to a node NB which is a contact point between the source of the transistor M sw1  and the drain of the transistor M gm1 . One terminal of the capacitor C 2  is connected to the node NB and the other terminal of the capacitor C 1  and the other terminal of the capacitor C 2  is connected to a power supply GND. 
         [0034]    The drain electrode of the transistor M sw2  is connected to the other terminal of the inductor L 1  and a source electrode of the transistor M sw2  is connected to a drain electrode of the transistor M gm2 . At this time, the direct current DC as the bias voltage V bias  is applied to a gate electrode of the transistor M sw2  and an output terminal OUT I−  is connected to the node NC. One terminal of the capacitor C 3  is connected to the node NC and the output terminal OUT I−  and the other terminal of the capacitor C 3  is connected to a node ND which is a contact point between the source of the transistor M sw2  and the drain of the transistor M gm2 . One terminal of the capacitor C 4  is connected to the node ND and the other terminal of the capacitor C 3  and the other terminal of the capacitor C 4  is connected to the power supply GND. 
         [0035]    Herein, a gate electrode of the transistor M gm1  is connected to the node NC and a gate electrode of the transistor M gm2  is connected to the node NA. In addition, a node NE which is a contact point between a source electrode of the transistor M gm1  and a source electrode of the transistor M gm2  is connected to one terminal of the current source I 1 . At this time, the current source I 1  generates constant bias current and provides high impedance to a high-frequency component to achieve a complete differential operation. 
         [0036]      FIG. 4  is a diagram schematically showing another example of a differential Colpitts oscillator according to an embodiment of the present invention 
         [0037]    Although the variable capacitors C var1  and C var2  are connected to the inductor L 1  in parallel like in the differential Colpitts oscillator  300 , in the differential Colpitts oscillator  300 ′ according to another embodiment of the present invention, the variable capacitor C var1  is connected to the capacitor C 2  in parallel and the variable capacitor C var2  is connected to the capacitor C 4  in parallel as shown in  FIG. 4 . Then, the differential Colpitts oscillator  300 ′ has a broadband characteristic of the variable capacitors C var1  and C var2  caused due to the decrease of the output voltage. Herein, the differential Colpitts oscillator  300 ′ has the same configuration as the differential Colpitts oscillator  300  except that the variable capacitors C var1  and C var2  are connected to the capacitors C 2  and C 4  in parallel, respectively. Therefore, a detailed description thereof will be omitted. 
         [0038]    In the differential Colpitts oscillators  300  and  300 ′, the output terminal OUT I+  is connected to the node NA which is the contact point between the drain electrode of the transistor M sw1  and one terminal of the inductor L 1  and the output terminal OUT I−  is connected to the node NC which is the contact point between the drain electrode of the transistor M sw2  and the other terminal of the inductor L 1 , but the present invention is not limited thereto and an output terminal OUT I+ ′ may be connected to the node NB which is the contact point between the source of the transistor M sw1  and the drain of the transistor M gm1  and an output terminal OUT I− ′ may be connected to the node ND which is the contact point between the source of the transistor M sw2  and the drain of the transistor M gm2 . At this time, since the output terminal OUT I+ ′ uses a drain output of the transistor M gm1  and the output terminal OUT I− ′ uses a drain output of the transistor M gm2 , it is possible to improve a frequency error by reducing a process deviation caused due to a parasite component. 
         [0039]      FIG. 5  is a diagram showing one example of output voltage of a differential Colpitts oscillator according to an embodiment of the present invention.  FIG. 6  is a diagram showing one example of a measurement value of phase noise of a differential Colpitts oscillator according to an embodiment of the present invention.  FIGS. 7A and 7B  are diagrams showing one example of phase noise performance of a differential Colpitts oscillator according to an embodiment of the present invention. 
         [0040]    Referring to  FIGS. 3 and 5 , in the differential Colpitts oscillator according to the embodiment of the present invention, when the bias voltage V bias  is applied to the gate electrode of the transistor M sw1 , which is turned on, the capacitor C 1  and the capacitor C 2  generate negative resistance R Y  by voltage applied through the turned on transistor M sw1 . At this time, voltage outputted by the inductor L 1  and the variable capacitors C var1  and C var2  is applied to the gate electrode of the transistor M gm1 , such that the transistor M gm1  is turned on and the negative resistance R Y  is increased by additional voltage which is fed back to the capacitors C 1  and C 2  by the turned on transistor M gm1  and is shown in Equation 1. 
         [0000]    
       
         
           
             
               
                 
                   
                     R 
                     Y 
                   
                   = 
                   
                     
                       - 
                       
                         
                           G 
                           
                             gm 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         2 
                       
                     
                     - 
                     
                       
                         
                           
                             G 
                             
                               sw 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                            
                           
                             ω 
                             2 
                           
                            
                           
                             C 
                             1 
                           
                            
                           
                             C 
                             2 
                           
                         
                         - 
                         
                           0.5 
                            
                           
                             G 
                             
                               gm 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                            
                           
                             ω 
                             2 
                           
                            
                           
                             
                               C 
                               2 
                             
                              
                             
                               ( 
                               
                                 
                                   C 
                                   1 
                                 
                                 + 
                                 
                                   C 
                                   2 
                                 
                               
                               ) 
                             
                           
                         
                       
                       
                         
                           G 
                           
                             sw 
                              
                             
                                 
                             
                              
                             1 
                           
                           2 
                         
                         + 
                         
                           
                             ω 
                             2 
                           
                            
                           
                             ( 
                             
                               
                                 C 
                                 1 
                               
                               + 
                               
                                 C 
                                 2 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                      
                     
                         
                     
                      
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
         [0041]    Herein, G gm1  is a trans-conductance of the transistor M gm1  and G sw1  is a trans-conductance of the transistor M sw1 . 
         [0042]    Likewise, when the bias voltage V bias  is applied to the gate electrode of the transistor M sw2 , which is turned on, the capacitor C 3  and the capacitor C 4  generate the negative resistance R Y  by voltage applied through the turned on transistor M sw2 . At this time, the voltage outputted by the inductor L 1  and the variable capacitors C var1  and C var2  is applied to the gate electrode of the transistor M gm2 , such that the transistor M gm2  is turned on and the negative resistance R Y  is increased by additional voltage which is fed back to the capacitors C 3  and C 4  by the turned on transistor M gm2  and is shown in Equation 2. 
         [0000]    
       
         
           
             
               
                 
                   
                     R 
                     Y 
                   
                   = 
                   
                     
                       - 
                       
                         
                           G 
                           
                             gm 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                         2 
                       
                     
                     - 
                     
                       
                         
                           
                             G 
                             
                               sw 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                            
                           
                             ω 
                             2 
                           
                            
                           
                             C 
                             1 
                           
                            
                           
                             C 
                             2 
                           
                         
                         - 
                         
                           0.5 
                            
                           
                             G 
                             
                               gm 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                            
                           
                             ω 
                             2 
                           
                            
                           
                             
                               C 
                               2 
                             
                              
                             
                               ( 
                               
                                 
                                   C 
                                   1 
                                 
                                 + 
                                 
                                   C 
                                   2 
                                 
                               
                               ) 
                             
                           
                         
                       
                       
                         
                           G 
                           
                             sw 
                              
                             
                                 
                             
                              
                             2 
                           
                           2 
                         
                         + 
                         
                           
                             ω 
                             2 
                           
                            
                           
                             ( 
                             
                               
                                 C 
                                 1 
                               
                               + 
                               
                                 C 
                                 2 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                      
                     
                         
                     
                      
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
         [0043]    Herein, G gm2  is a trans-conductance of the transistor M gm2  and G sw2  is a trans-conductance of the transistor M sw2 . 
         [0044]    As such, in the differential Colpitts oscillators  300  and  300 ′ according to the embodiment of the present invention, as shown in  FIG. 5 , as the negative resistance R Y  increases, the start-up current and power consumptions may decrease in comparison with the known Colpitts oscillator  100 . In addition, the differential Colpitts oscillators  300  and  300 ′ are designed to increase the negative resistance in addition to low power consumption which is the merit of the known Colpitts oscillator  200 . The differential Colpitts oscillators  300  and  300 ′ can improve the phase noise performance at a low-frequency offset as shown in  FIG. 6  in comparison with the known Colpitts oscillator  200 . 
         [0045]    Further, the differential Colpitts oscillators  300  and  300 ′ are designed to generate larger output voltage at an operating point of the maximum saturation region to improve the phase noise performance in the saturation region unlike the known Colpitts oscillator  200 . 
         [0046]    For example, as shown in  FIG. 7A , at an offset frequency of 100 KHz in an operation of the saturation region, the differential Colpitts oscillators  300  and  300 ′ have phase noise of −102 dBc and the known Colpitts oscillators  200  have phase noise of −105 dBc. Accordingly, the differential Colpitts oscillators  300  and  300 ′ can improve the phase noise performance by 3 dBc in comparison with the known Colpitts oscillator  200 . As another example, as shown in  FIG. 7B , at an offset frequency of 1 MHz in an operation of a general saturation region, the differential Colpitts oscillators  300  and  300 ′ have phase noise of −126.5 dBc and the known Colpitts oscillator  200  has phase noise of −122.5 dBc. Accordingly, the differential Colpitts oscillators  300  and  300 ′ can improve the phase noise performance by 4 dBc in comparison with the known Colpitts oscillator  200 . 
         [0047]    As described above, according to an embodiment of the present invention, it is possible to reduce start-up current and power consumptions and improve phase noise performance at an operating point of a maximum saturation region by improving negative resistance and oscillation amplitude. 
         [0048]    In addition, according to the embodiment of the present invention, it is possible to improve an oscillation frequency error by means of using a drain output of a boosting transistor for increasing the negative resistance which reduces a process variation by a parasitic component. 
         [0049]    While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.