Abstract:
The present invention is a serial to parallel data conversion method and device where new serial data are stored within a first n-bit register prior to presentation at an n-bit parallel output. Subsequently, additional data are stored within a second n-bit register while the data stored within the first register are presented at the parallel output. Data storage and data presentation are thereafter alternated, thereby eliminating the problem of setup time seen in prior art.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The invention generally relates to a method used in semiconductor manufacturing and, more particularly, to a serial to parallel data converter used in the fabrication of integrated circuits (ICs). 
     (2) Description of Prior Art 
     Serial to parallel data converters have numerous applications in electronics including circuitry where serial data from a disk or CDROM are converted to parallel format to be processed within a computer. As processing speeds increase and memory sizes grow, there is a need to reduce the time necessary to convert data from serial to parallel format. 
     Refer now to FIG. 1 showing a typical serial to parallel data converter. A plurality (n) of first D flip-flops (DFF A )  10 - 13  are provided. A serial data stream (DATA_IN) is applied to the input of each DFF A    10 - 13 . A plurality (n) of phase clocks are applied to the corresponding clock input of each latch  10 - 13  such that CLK 0  is applied to DFF A0 , CLK 1  is applied to DFF A1 , etc. The output of each DFF A    10 - 13  is connected to the input of a corresponding second D flip-flop (DFF B )  15 - 18 . CLK n−1  is connect through a delay  19  to each clock inputs of DFF B    15 - 18 . The outputs of each DFF B    15 - 18  correspond to parallel data PD 0  through PD n−1 . The operation of the circuit of FIG. 1 is as follows. DATA_IN are applied to the plurality of DFF A  ( 10 - 13 ). On the rising edge (for example) of each phase clock (CLK 0 -CLK n−1 ) the corresponding serial data bit is stored on the output of its respective DFF A . Once all n data bits are stored, the clock inputs of each DFF B    15 - 18  are simultaneously triggered and the data are then transferred to the corresponding parallel data output PD 0  through PD n−1 . The parallel data are then ready for use. The process is repeated and when the next n data bits are received, new parallel data appear at the output. 
     The problem with this circuit is that as speeds increase, the DFFs  15 - 18  may not be able to load properly before the next data bit is latched into DFF A0    10 . Additionally, as serial data speeds increase, the processor using the parallel data may not be able to keep up with the presentation of parallel data. Thus, the serial data transfer must be stopped until the processor is ready to accept more parallel data. It is therefore necessary to find a better method to transfer serial to parallel data. 
     Other approaches related to improving serial to parallel data conversion circuits exist. U.S. Pat. No. 6,259,387 B1 to Fukazawa describes a serial-parallel converter, which uses a plurality of data extraction units, a delay unit and parallel registers for storing data for parallel distribution. U.S. Pat. No. 6,052,073 to Carr et al. discloses a serial-parallel converter using a shift register, a parallel latch and a controller for enabling and synchronizing the data stream. U.S. Pat. No. 5,777,567 to Murata et al. shows a serial-parallel converter using a delay line and phase locked loop (PLL) to synchronize the data. U.S. Pat. No. 5,561,423 to Morisaki describes a serial-parallel converter operating at high-speed and low power dissipation and utilizing differential flip-flops. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide a serial to parallel data conversion method utilizing a high-speed clock and high data rate application. 
     Another object of the present invention is to provide a serial to parallel data conversion circuit utilizing a high-speed clock and high data rate application. 
     A further object of the present invention is to provide a serial to parallel data conversion method that avoids the problem of setup between parallel loading of data and latching of the next serial data bit. 
     A still further object of the present invention is to provide a serial to parallel data conversion circuit that avoids the problem of setup between parallel loading of data and latching of the next serial data bit. 
     These objects are achieved using a serial to parallel data conversion method and circuit where the first serial data word is stored within a first n-bit register prior to presentation at the n-bit parallel output. The second serial data word is stored within a second n-bit register while the first serial data word stored within the first register is presented in parallel format at the output. The third serial data word is then stored within the first n-bit register while the second serial data word stored within the second register is presented at the output. Thus odd serial data words are stored within the first n-bit register while the contents of the second n-bit register are output and even serial data words are stored within the second n-bit register while the contents of the first n-bit register are output. By alternating data storage and data presentation the problem with setup time observed in prior art is eliminated. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings forming a material part of this description, there is shown: 
     FIG. 1 schematically illustrating a block diagram representation of a typical serial to parallel data conversion system; 
     FIG. 2 schematically illustrating a block diagram of the serial to parallel data conversion system of the present invention; 
     FIG. 3 illustrating a schematic representation of controller block of the serial to parallel data conversion system used in FIG. 2; 
     FIG. 4 illustrating a timing diagram for the controller clock of FIG. 3; 
     FIG. 5 illustrating a block diagram of the sampler block of the serial to parallel data conversion system used in FIG. 2; 
     FIG. 6 illustrating a schematic representation of the latcher block used in the sampler block of FIG. 5; and 
     FIG. 7 illustrating a schematic representation of the data selector block used in FIG. 2 of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Refer now to FIG. 2, depicting in block diagram the serial to parallel data converter of the present invention. An n-bit converter is depicted. A controller circuit  20  is provided having inputs CLK 0 , CLK n/2  and LOCK. The phase locked loop (not shown) that maintains all the clocks (CLK 0  through CLK n−1 ) generates the LOCK signal indicating that frequency lock has been achieved. The controller  20  outputs (LOCK_A and LOCK_B) are applied to the sampler circuit  22  along with the DATA_IN and clock signals (CLK 0  through CLK n−1 ). The sampler  22  has a pair of outputs (DATA X     —     A ) and DATA X     —     B ) for each of the n bits of the parallel data. Additionally a TOGGLE signal is output from the sampler  22 . Each of the n pairs of outputs from the sampler  22  are applied to paired inputs of the n-bit, 2 to 1, data selector  24 . The TOGGLE signal is applied to the (A/!B) select input (A/!B) of the data selector  24 . 
     An overview of the operation of the present invention of FIG. 2 will now be discussed with additional details to follow. In the example, a rising clock edge is assumed to be the trigger, however those skilled in the art will realize that a falling edge could be used without changing the intent of the invention. 
     The sampler  22  has two n-bit registers A and B having outputs DATA 0     —     A  through DATA n−1     —     A  and DATA 0     —     B  through DATA n−1     —     B , respectively. If the phase locked loop is not properly synchronized with the data stream, the LOCK signal will be low and the two registers will be cleared. Once a LOCK signal is indicated from the phase locked loop, LOCK_A will go high on the CLK 0  edge. As each CLK X  edge is presented the corresponding bit of the first n/2 bits of the first serial data word (DATA_IN) is stored in the first sampler register. On the edge of CLK n/2 , LOCK_B will go high and as each CLK X  edge is presented the corresponding bit of the next n/2 bits of the first serial data word (DATA_IN) will be stored internally to the lower half of the first sampler register. Once all n bits have been stored in the first sampler register, the subsequent CLK X  edges will store the second n-bits of the serial data word (DATA_IN) in the second sampler register. Additionally, on the next CLK 0  edge, TOGGLE will become high so that DATA 0     —     A  through DATA n−1     —     A  are selected by the data selector  24  and will then appear at the corresponding PD X  output of the data selector  24 . Once the second register is filled, the third serial data word will be stored to the first register, TOGGLE will go low so that DATA 0     —     B  through DATA n−1     —     B  are selected by the data selector  24  and will then appear at the corresponding PD X  output of the data selector  24 . The process is repeated with odd and even serial data words alternately being stored to the first or second sampler register, respectively. By doing this, the data has time to setup prior to parallel reading. 
     Refer to FIG. 3 showing the circuit for the controller block  20 . A first DFF  26  has the LOCK signal applied to the D input and the CLK 0  signal applied to the clock (CLK) input. The output of the first DFF  26  (LOCK_A) is applied to the D input of the second DFF  28 . CLK n/2  provides the clock (CLK) input of the second DFF  28 . The output of the second DFF  28  is LOCK_B. Referring now to the timing diagram of FIG.  4  and the circuit of FIG. 3, the operation of the controller will now be provided. Prior to the LOCK signal going high, LOCK_A will be low on each edge of CLK 0 . Since LOCK_A provides the D input to the second DFF  28 , whenever LOCK_A is low, LOCK_B will be low on each edge of CLK n/2 . Once a phase locked loop lock condition is achieved, LOCK will go high and LOCK_A will become high on the next edge of CLK 0 . Thereafter LOCK_B will become high on the next edge of CLK n/2 . 
     Refer now to FIG. 5, showing a block diagram of the sampler  22  of the present invention. A plurality of n LATCHER blocks  30 - 33  are provided. Each LATCHER block  30 - 33  has an input tied to the DATA_IN signal line. Each LATCHER X    30 - 33  has a corresponding CLK X  applied to a CLK input. The first n/2 LATCHERs  30 - 31  have a control input (CTRL) with LOCK_A applied, while the remaining n/2 LATCHERs  32 - 33  have the control input (CTRL) connected to LOCK_B. Each LATCHER X    30 - 33  has a pair of outputs (DATA X     —     A  and DATA X     —     B ) and a TOG output, with TOG 0  (from LATCHER 0 ) providing the TOGGLE signal used by the data selector  24 . The LOCK_A and LOCK_B signals assure that all the TOG bits in each LATCHER block  30 - 33  are properly set, thus avoiding any possible mistake in latching during the initial data capture. Thereafter, the TOG bits will toggle between logic states. 
     Referring now to FIG. 6, the detailed circuitry of the LATCHER block  30 - 33  is now discussed. A JK flip-flop (JKFF)  40  is provided. The JKFF  40  has the J input connected to the CTRL signal (either LOCK_A or LOCK_B) while the K input is tied high. The CLK input of the JKFF and a first and second DFF ( 46  and  48 , respectively) are connected to the CLK X  signal. The output of the JKFF  40  is the signal TOG that is in turn applied to the select inputs (SEL A/!B) of a first and second 2:1 multiplexer or MUX ( 42  and  44 , respectively). The first MUX  42  is connected such that the DATA_IN (serial data) signal is applied to the B input and the output (Q) of the first DFF  46  is applied to the A input. The second MUX  44  is connected such that the DATA_IN (serial data) signal is applied to the A input and the output (Q) of the second DFF  48  is applied to the B input. The output (Q) of the first DFF  46  is DATA X     —     A  of the LATCHER X , and the output (Q) of the second DFF  48  is DATA X     —     B  of the LATCHER X . 
     Still referring to FIG. 6, the operation of the LATCHER block  30 - 33  is now described. Initially the CTRL input (from either LOCK_A or LOCK_B) is low. Therefore on each edge of CLK X  the output of the JKFF  40  (TOG) is reset (logic 0). This selects the B inputs from the first and second MUX  42  and  44 . This applies DATA_IN to the D input of the first DFF  46  and DATA X     —     B  to the D input of the second DFF  48 . Thus on each CLK X  edge DATA_IN and DATA X     —     B  are refreshed upon the Q outputs of DFFs  46  and  48 , respectively. Once PLL lock is achieved the CTRL signal will go high (1). On the first subsequent rising edge of CLK X  valid DATA_IN will be stored on the Q output (DATA X     —     A ) of the first DFF  46  and DATA X     —     B  is refreshed on the Q output of second DFF  48 . Simultaneously, TOG will become high (logic 1). On the second subsequent rising edge of CLK X  valid DATA_IN will be stored on the Q output (DATA X     —     B ) of the second DFF  48 , DATA X     —     A  is refreshed on the Q output of the first DFF  46  and TOG will become low (logic 0). Thus on each CLK X  edge whenever CTRL is high, TOG will toggle between 0 and 1, and the valid DATA_IN will be stored on one of the two DFF Q outputs while the other DFF Q output is refreshed. 
     Refer now to FIG. 7, showing the circuitry of the data selector  24 . There are a plurality, n, of 2 to 1 multiplexers (MUX)  50 - 53 . Each MUX  50 - 53  has a pair of data inputs DATA X     —     A  and DATA X     —     B . The input that appears at the output (PD X ) is selected by a common select input (SEL A/!B) such that when SEL is low the DATA X     —     B  input will appear at PD X  and when SEL is high the DATA X     —     A  input will appear at PD X . 
     With all of the blocks of the serial to parallel data system described, the overall operation will now be described in further detail. If the phase locked loop is not properly synchronized with the data stream, the LOCK signal and the LOCK_A and LOCK_B will be low. The individual TOG signals for each LATCHER  30 - 33  will be low and invalid DATA_IN and DATA X     —     B  are refreshed upon the Q outputs of DFFs  46  and  48 , respectively. Since TOG 0  is low and applied to the SEL input of the data selector  24 , the output of the data selector  24  will be DATA X     —     B . Once the phase locked loop LOCK is achieved (1), LOCK_A and LOCK_B will become high on CLK 0  and CLK n/2  respectively. With the first CLK X  after LOCK_A, valid serial data will be stored in the first DFF  46  within the LATCHER blocks  30 - 33 . During this time SEL is low so that parallel output data (PD X ) will continue to be from the second DFFs  48 . On the second CLK 0  edge, the SEL signal will become high and the parallel output data (PD X ) will be from the first DFFs  46 . On the second CLK X  after LOCK_A, valid serial data will be stored in the second DFF  48  within the LATCHER block  30 - 33 . On subsequent CLK 0  the SEL signal will TOGGLE so that while one serial data word is being stored, the prior set is presented in parallel format at the output. By using a pair of n-bit registers to store serial data prior to being presented, the present invention solves the problem where new data is being presented to the parallel output before the previous data has stabilized. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.