Abstract:
A circuit for controlling the operation of synchronous rectifiers. The circuit delays the turn-off of the synchronous rectifiers in accordance with the load current. The magnitude of the load current is examined to determine which of a plurality of delay elements is selected to delay turn-off of the synchronous rectifiers. Delay is accomplished by holding up for a predetermined time period one of a plurality of control signals utilized to determine when the synchronous rectifier should be turned-off.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 11/002,426 filed on Dec. 2, 2004. The disclosure of the above application is incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates generally to switching power supplies, and, more particularly, to a control circuit for synchronous rectifiers. 
   BACKGROUND OF THE INVENTION 
   Manufacturers of electronic components increasingly demand switching power converters that have a very low voltage loss and a high output current. One type of a switching power converter uses a synchronous rectification technique. Synchronous rectifiers typically are implemented as metal-oxide semiconductor field-effect transistors (MOSFETs), although other switches such as bipolar junction transistors (BJTs), insulated-gate field-effect transistors (IGBTs), or other switches may be used. Synchronous rectification improves the efficiency of a power converter by substituting a transistor for a rectifier diode. This type of switching power converter is generally formed by a switching circuit, a transformer, a rectifying circuit, and at least one control circuit. 
   The switching circuit typically includes a bridge circuit arranged in a push-pull configuration with a transformer. For example, four switching devices (switches) may define the bridge circuit. The first and second switches are connected in series. The third and a fourth switches are also connected in series, and the series pairs are connected in parallel across a direct current (DC) voltage source. The transformer, which has a primary winding and a secondary winding, connects to the first and the second switches at one end of the primary winding. The other end of the primary winding connects to the third and the fourth switches. A rectifying circuit including two synchronous rectifiers connects to the secondary side of the transformer. A primary control circuit connects to the switching circuit. The primary control circuit generates a drive signal for each of the switches. 
   A secondary control circuit drives the synchronous rectifiers in accordance with drive signals output by the primary control circuit. In one configuration, the secondary control circuit includes two logical OR gates. The drive signals used to control the first and fourth switches define inputs to the first logical OR gate. The first logical OR gate outputs a drive signal to one of the two synchronous rectifiers. The drive signals used to control the second and third switches define inputs to the second logical OR gate. The second logical OR gate outputs a drive signal to the other of the two synchronous rectifiers. An example of such a configuration may be seen with respect to U.S. Pat. No. 6,504,739 issued Jan. 7, 2003, and assigned to the assignee of the present invention, the disclosure of which is incorporated by reference in its entirety herein. 
   While the switching power converter described above has a low voltage loss and a high current output, it may not address all of the parasitic components that potentially exist in a synchronous rectifier circuit. For example, a zero phase shifted full bridge, zero voltage switching (ZVS) converter includes transformer leakage inductance. Transformer leakage inductance causes a delay in the actual voltage of the secondary winding relative to the voltage across the primary winding. It may also increase the time necessary for the drain current passing through the synchronous rectifier to deplete to zero with respect to the primary winding voltage. This voltage and current delay increases as the load current increases. When the synchronous rectifiers turn off, the drain current through the MOSFET transfers to the body diode of the MOSFET, thereby increasing the voltage drop across the MOSFET. These conduction losses are higher than if the drain current was able to pass through a drain-to-source on-resistance. 
   SUMMARY OF THE INVENTION 
   The present invention is directed to circuit including a secondary controller and a delay circuit coupled to the secondary controller. The delay circuit receives a first synchronous rectifier control signal from the secondary controller and a load current signal. The delay circuit applies a predetermined delay to the first synchronous rectifier control signal. A synchronous rectifier control circuit is coupled to the secondary controller and to the delay circuit. The synchronous rectifier control circuit receives the delayed first synchronous rectifier control signal and controls a synchronous rectifier in accordance with the first synchronous rectifier control signal. The delay applied to the first synchronous rectifier control signal varies in accordance with the load current signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1  is a schematic diagram of a synchronous rectifier control circuit for synchronous rectification in accordance with the present invention; 
       FIG. 2  is a schematic diagram of a switching power converter in accordance with one embodiment of the present invention; 
       FIGS. 3A-3D  are schematic diagrams of a secondary control circuit for the power converter of  FIG. 2 ; 
       FIG. 4  depicts waveforms describing operation of a portion of a circuit of  FIG. 2  for a light load region of load current; 
       FIG. 5  depicts waveforms describing operation of a portion of a circuit of  FIG. 2  for a mid-load region of load current; 
       FIG. 6  depicts waveforms describing operation of a portion of a circuit of  FIG. 2  for a heavy load region of load current; 
       FIG. 7  is a graph illustrating an exemplary turn-off delay for a synchronous rectifier versus load current; 
       FIG. 8  is a graph illustrating power efficiency versus load for a power converter arranged in accordance with the principles of the present invention; 
       FIG. 9  is a graph illustrating power loss versus load on a power converter; 
       FIG. 10  is a graph illustrating an exemplary turn-off delay for a synchronous rectifier versus load current; 
       FIG. 11  is a schematic diagram of a delay circuit for synchronous rectification; and 
       FIG. 12  is a block diagram of a current sensing circuit for providing the current sense signal of  FIGS. 3A-3D . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, similar reference numbers are used in the drawings to identify similar elements. 
   The present invention increases the efficiency of power converters by reducing the body diode conduction due to transformer leakage inductance. This is accomplished by optimizing control of the synchronous rectifier relative to the output load current. For example, turning a synchronous rectifier to an off state is delayed until the drain current is nearly zero in the synchronous rectifier. This reduces body diode conduction through the synchronous rectifier. Moreover, the cost to manufacture a switching power converter is reduced since lower performing components may replace more expensive components while still attaining power efficiency requirements. 
   Although the following description generally relates to a full bridge converter, it is readily understood that the broader aspects of the present invention are applicable to other types of converter topologies (e.g. push-pull topologies, half bridge topologies, etc.) that use synchronous rectification. In particular, the present invention may be applied to soft switched full bridge, full bridge, forward half bridge, and flyback converters that use synchronous rectification. 
     FIG. 1  depicts a block diagram of a synchronous rectifier control circuit  10  for delaying a signal to turn off a synchronous rectifier. Synchronous rectifier control circuit  10  includes synchronous rectifier controller  12 , delay selector circuit  16 , and synchronous rectifier delay control circuit  18 . 
   Primary side drive signals enter synchronous rectifier controller  12  from a primary control circuit (not shown). Synchronous rectifier controller  12  controls the application of the primary side drive signals to synchronous rectifier delay control circuit  18  and to delay selector circuit  16 . A load current signal (I SEN ), which depends upon the magnitude of a load current I LOAD , is input to delay selector circuit  16 . Based upon I LOAD , delay selector circuit  16  determines the desired delay. A delay signal is then output from delay selector circuit  16  to synchronous rectifier delay control circuit  18 . Synchronous rectifier delay control circuit  18  then generates a control signal to turn off a selected synchronous rectifier. 
     FIG. 2  is a detailed embodiment of a zero phase shifted full bridge, zero voltage switching (ZVS) power converter  100 . Power converter  100  comprises input voltage source  132  (V IN ), switching circuit  134 , transformer  136 , rectifying circuit  138 , primary control circuit  140 , secondary control circuit  142 . 
   Switching circuit  134  includes a first switching device (switch) Q A  connected in series to a second switch Q B  to form a first switching leg. Switching circuit  134  also includes a third switch Q C  connected in series to a fourth switch Q D  to form a second switching leg. The switching legs are connected in parallel across input voltage source  132 . In one embodiment, one or more of the primary switches are metal-oxide semiconductor field-effect transistors (MOSFETs) switches, although one skilled in the art will recognize that bipolar junction transistor (BJTs), insulated-gate field-effect transistors (IGBTs) or other suitable switches may also be used. Switching circuit  134  connects to transformer  136 , which includes a primary side having primary winding  112  and a secondary side including secondary winding  114 . One end of primary winding  112  connects to first node  116 , and the other end of the primary winding  112  connects to second node  118 . 
   Primary control circuit  140  generates drive signals for each of the switches Q A , Q B , Q C , and Q D  of switching circuit  134 . In one configuration, primary control circuit  140  generates drive signals of various phases to the Q A /Q D  pair of switches and drive signals of various phases to the Q C /Q B  pair of switches. The control signals to switch pair Q A /Q D  are generally complementary to control signals to switch pair Q C /Q B . This allows diagonal switches (i.e., Q A /Q D and Q C /Q B ) to conduct alternately to effect a push-pull configuration across primary winding  112 . Thus, primary control circuit  140  provides ZVS, phase shifted control over switching circuit  134 . 
   Rectifying circuit  138  includes two synchronous rectifiers connected to a center-tapped secondary winding  114  of transformer  136 . A first rectifying switch FETQ 1  (also referred to as first synchronous rectifier) connects to a first end of secondary winding  114 , and a second rectifying switch FETQ 2  (also referred to as second synchronous rectifier) connects to the other end of secondary winding  114 . An inductor L connects between a center tap of secondary winding  114  and an output terminal providing an output voltage V 0  to a load  126  in parallel with capacitor  156 . 
   Secondary control circuit  142  connects to switches FETQ 1  and FETQ 2  of the rectifying circuit  138 . Control signals Q A , Q B , QC, Q D  from primary control circuit  140  provide input signals to secondary control circuit  142  to activate and to deactivate synchronous rectifiers FETQ 1 , FETQ 2 . In a conventional drive configuration, when a first pair of diagonal switches on the primary side of transformer  136  are both conducting, one of the two synchronous rectifiers FETQ 1 , FETQ 2  is typically in an on state. After both of the first pair of diagonal switches is driven to an off state by primary control circuit  140 , secondary control circuit  142  drives the one of the two synchronous rectifiers FETQ 1 , FETQ 2  to an off state. In an embodiment of the present invention, secondary control circuit  142  delays turn off of the control signal for the second switch of a diagonal pair to correspondingly delay turn off of the associated synchronous rectifier. More specifically, the synchronous rectifier control signal that controls the later switch to be turned off of the switch pairs Q A /Q D  and Q C /Q B is delayed by secondary control circuit  142 . As described herein, active refers to active high. 
     FIGS. 3A-3D  depict secondary control circuit  142  of  FIG. 2  which includes a delay selection section  162  and delay element section  164 . Except where noted, delay element section  164  includes substantially identical halves a and b, and like elements are referred to using like reference numerals having suffixes a and b. Generally, the amount of delay to turn off a synchronous rectifier depends on the delay elements operating in delay element section  164 . Delay selection section  162  determines the delay elements operating in the delay element section  164 . 
   Delay selection section  162  selects the delay element to operate in the delay element section  164  based on the magnitude of the load current flowing through the load  126  of  FIG. 2 . Referring to  FIG. 3A , I SEN  is determined based upon I LOAD  using a conventional current sensing circuit  200  as shown in  FIG. 12 , as will be described in greater detail herein. I SEN  passes through resistor R 101 , and a capacitor C 101  provides low pass filtering. The voltage at the anode of capacitor C 101  is referred to as V ISEN . 
   The V ISEN  voltage is applied to comparators U 2  and U 1  via respective resistors R 103  and R 107 . Resistors R 104  and R 105  form a voltage divider for a reference voltage V REF  to provide a reference voltage applied to the inverting input of comparator U 2 . The output signal CON 2  is determined by comparing the voltage at the inverting input to the voltage at the non-inverting input of comparator U 2 . When the voltage at the non-inverting input exceeds the voltage at the inverting input, CON 2  is high. If the voltage at the non-inverting input is less than the voltage at the inverting input, CON 2  is low. A feedback resistor R 102  provides hysteresis at the non-inverting input. 
   The output signal CON 1  from comparator U 1  is similarly determined. Resistors R 108  and R 109  form a voltage divider for a reference voltage V REF  to provide a reference voltage applied to the inverting input of comparator U 1 . The output signal CON 1  is determined by comparing the voltage at the inverting input to the voltage at the non-inverting input of comparator U 2 . If the voltage at the non-inverting input is less than the voltage at the inverting input, CON 1  is low. If the voltage at the non-inverting input exceeds the voltage at the inverting input, CON 1  is high. A feedback resistor R 106  provides hysteresis at the non-inverting input of comparator U 1 . CON 1  and CON 2  are applied to the delay element section  164 . 
   Delay element section  164  includes first and second delay circuits  170   a ,  170   b . First delay circuit  170   a  will be described herein. One skilled in the art will recognize that second delay circuit  170   b  operates similarly. First delay circuit  170   a  connects to an input of a first OR gate  160   a . Drive signal Q A connects to the input of first OR gate  160   a  through a parallel connection of resistor R 1   a  and D 1   a  of first delay circuit  170   a . Drive signal Q D  connects to the other input of the first OR gate  160   a . First OR gate  160   a  outputs a drive signal to the synchronous rectifier FETQ 1 . As will be described in greater detail herein, activating CON 1  and/or CON 2  correspondingly activates respective switches S 1   a  and S 2   a  to selectively introduce varying capacitances between the Q A  input of OR gate  160   a  and ground. 
   The CON 1  output of comparator U 1  connects to a voltage divider that includes resistors R 4   a , R 3   a , and R 2   a . One terminal of resistor R 4   a connects to an 8 volt source and the other terminal of resistor R 4   a  connects to resistor R 3   a . One node of the voltage divider connects to the gate of switch S 1   a . Switch S 1   a  includes a capacitance Coss across its drain and source, which connects to ground. The capacitance Coss may be the small output capacitance of switch S 1   a , or it may be an external capacitance. 
   Similarly, CON 2  connects to a voltage divider that includes resistors R 7   a , R 6   a , and R 5   a . One terminal of resistor R 7   a  connects to an 8 volt source, and the other terminal of resistor R 7   a  connects to resistor R 6   a.  The drain of switch S 2   a  connects to a node interconnecting capacitors C 2   a  and C 3   a  to provide a path from the interconnecting terminal of C 3   a,  through switch S 2   a,  to ground. 
   Delay element section  164  generates a delay that depends upon which, if any, of switches S 1   a , S 2   a  are activated by respective signals CON 1  and CON  2 .  FIGS. 3B-3D  depict circuits describing the operation of secondary control circuit  142  based upon the load current signal I SEN , which varies in accordance with the load current I LOAD  By way of example, I LOAD  may fall into one of three regions, a low load region, a mid-load region, or a high load region. The low load region ( FIG. 3B ) is generally between 0 ampere (A) and 30 A. The mid-load region ( FIG. 3C ) is generally between 30 A and 65 A. The high load region ( FIG. 3D ) is generally greater than 65A. These regions of the load current I LOAD  determine the amount of delay introduced prior to switching the synchronous rectifiers FETQ 1 , FETQ 2  to an off state. One skilled in the art will recognize that load currents defining these regions and the number of regions may vary. 
   The arrow in  FIG. 3B  illustrates the circuit path through selected capacitive elements of the delay element circuit  164  when the I LOAD  is in the low load region. V ISEN  is below the threshold voltage level to turn on comparators U 2  and U 1 . Specifically, the inverting input voltages exceed the non-inverting input voltages, thereby causing the CON 1  and CON 2  outputs of comparators U 1  and U 2  to be low. With the output signal CON 1  and CON 2  low, switches S 1   a  and S 2   a  are off. With switches S 1   a  and S 2   a  off, capacitors C 1   a , C 2   a , and C 3   a  form a series connection between the input of first OR gate  160   a and ground. This configuration minimizes equivalent capacitance between the input to OR gate  160   a  and ground, and the corresponding delay. For the circuit of  FIG. 3B , the signal to turn FETQ 1  to an off state has a delay of about 20 ns when I LOAD  is in the low level region.  FIG. 4  depicts exemplary waveforms representing such a delay. As stated above, skilled artisans will understand that the capacitance between the drain and source off switch S 1   a  may be implemented using the Coss of FET S 1   a  if the timing requirements meet the design criteria. 
     FIG. 3C  illustrates the circuit path through selected capacitive elements of delay element circuit  164  when I LOAD  is in the mid-load region. When I LOAD  is in the mid-load region, V ISEN  is above the threshold level for comparator U 1  to turn on, driving CON 1  high. CON 1  then turns on the switch S 1   a , effectively, shorting capacitor C 1   a  and placing capacitors C 2   a  and C 3   a  in series between the input to OR gate  160   a  and ground. The equivalent series capacitance of C 2   a and C 3   a  exceeds the equivalent series capacitance of capacitors C 1   a , C 2   a  and C 3   a . For the circuit of  FIG. 3C , the signal to turn FETQ 1  off has a delay of about 100 ns.  FIG. 5  depicts exemplary waveforms representing such a delay. 
     FIG. 3D  illustrates the circuit path through selected capacitive elements of delay element circuit  164  when I LOAD  is in the heavy load region. In this scenario, V ISEN  is above the threshold level for comparators U 1  and U 2  to turn on, thereby driving CON 1  and CON 2  is high. This activates switches S 1   a and S 2   a . Activating switch S 1   a  causes the circuit to operate similarly as described above. Activating switch S 2   a  provides a current path from capacitor C 3   a , through switch S 2   a , to ground. This leaves only capacitor C 3   a  between the input to OR gate  160   a  and ground. The equivalent capacitance of capacitor C 3   a exceeds the equivalent capacitance of the series connection of capacitors C 2   a and/or C 3   a , thereby increasing the delay. For the circuit of  FIG. 3D , the signal to turn FETQ 1  has a delay of approximately 150 ns.  FIG. 6  depicts exemplary waveforms representing such a delay. 
   From the description of  FIGS. 3A-3D , skilled artisans will appreciate that various components of the circuits described herein may have various values. Exemplary values for selected components are provided in the attached figures. One skilled in the art will further appreciate that the values shown in the figures may vary in accordance with various design criteria for implementing the present invention. 
   From the embodiments described herein, it will be apparent that the turn-off delay of the synchronous rectifier control increases as the I LOAD increases. Similarly, the turn-off delay of the synchronous rectifier decreases when I LOAD  decreases.  FIG. 7  shows a graphical example of the linear relationship between the turn-off delay and the I LOAD . 
   This process of delaying the signal to turn-off a synchronous rectifier reduces or eliminates the body diode conduction through the synchronous rectifier FETQ 1 , FETQ 2 , thereby increasing the efficiency of power converter  100 . Referring to  FIGS. 8 and 9 , the power converter  100  of the present invention increases the efficiency and reduces power loss. The power converter used to generate  FIGS. 8 and 9  used a 12V/110 A phase shifted ZVS full bridge power supply operating at 300 kHz.  FIGS. 8 and 9  depict curves corresponding to a power converter operating without and with the delay circuit of the present invention. 
   One skilled in the art will recognize that numerous relationships between the load current and turn-off delay exist.  FIG. 10  shows a stepped relationship between the turn-off delay and the load current. For example, one skilled in the art will recognize that N discrete steps relating load current regions and turn-off delay may be utilized. In the embodiment of  FIGS. 3A-3D , three discrete steps were utilized. One skilled in the art will also recognize that both linear and non-linear relationships between turn-off delay and load current may be implemented. 
     FIG. 11  shows an alternate embodiment for generating a delay to turn off a synchronous rectifier.  FIG. 11  is a schematic diagram of a control circuit  400  which may be substituted for delay circuits  170   a ,  170   b  of delay element section  164  of  FIGS. 3A-3D .  FIG. 11  utilizes BJTs in place of FETs for switches S 1   a  and S 2   a . BJTs provide a relatively low output capacitance compared to the FETs. BJTs thus provide a delay that more closely attains zero current in the body diode of the synchronous rectifiers FETQ 1  and FETQ 2 . In the configuration of  FIG. 11 , freewheeling diodes DS 1   a  and DS 2   a  provide a discharge path for the capacitors C 2   a  and C 3   a.    
     FIG. 12  depicts a diagram of a current sensing circuit  200  used to sense I LOAD  and generate I SEN . Current sensing circuit  200  is implemented as a half-wave capacitive-filter rectifier having an output connected to a buffer amplifier. A current transformer  190  is arranged to sense the load current I PRI  at the primary side. The secondary winding of transformer  190  connects to a diode  194  and load resistor  196 . A filter capacitor  198  in parallel with resistor  196  provides filtering of the rectified signal. Buffer amplifier  192  outputs the sense signal I SEN  to the input of delay selection section  162  of  FIGS. 3A-3D . Resistor R 101  and capacitor C 101  cooperate to provide a low pass filter function for I SEN . 
   While the invention has been described in its presently preferred form, it will be understood that the invention is capable of modification without departing from the spirit of the invention as set forth in the appended claims.