Abstract:
Embodiments relate to semiconductor devices and methods for fabricating semiconductor devices. According to embodiments, a semiconductor device may include a bit line and a bit line bar. The device may also include a precharge controller that may generate a precharge control signal, and NMOS transistors and PMOS transistors to precharge the bit line and the bit line bar in response to the precharge control signal. According to embodiments, a precharge speed of a bit line in a semiconductor device may be improved and an operating cycle time of a memory device may also be improved.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2007-0135988 (filed on Dec. 24, 2007), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    A memory operation may include amplifying data stored in respective memory cells through a sense amplifier according to a read command or write command in a state that a bit line and a data line are precharged to a given voltage and to output the data to the outside, or to transfer data input from the outside to data line by using a data write driver and then store the data in a memory cell selected through bit line. 
         [0003]    When a read or write operation of the memory is completed, a bit line and a data line should be charged again to a given voltage to be capable of performing a subsequent memory operation. 
         [0004]    Hence, to obtain a high speed operation of a memory device, a speed in a read operation and write operation should be optimized. In addition, a speed in a precharge of bit line before and/or after the read and write operation should also be optimized. 
       SUMMARY 
       [0005]    Embodiments relate to a semiconductor circuit that may include a precharge circuit to improve a precharge speed of bit line. 
         [0006]    According to embodiments, a semiconductor circuit may include a bit line and a bit line bar. It may also include a precharge controller to generate a precharge control signal, and NMOS transistors and PMOS transistors to precharge the bit line and the bit line bar in response to the precharge control signal. 
         [0007]    According to embodiments, a precharge speed of a bit line in a semiconductor circuit may be optimized and an operating cycle time of a memory device may also be optimized. 
     
    
     
       DRAWINGS 
         [0008]    Example  FIG. 1  is a circuit diagram of bit line precharge voltage generating device according to embodiments. 
           [0009]    Example  FIG. 2  is a graph illustrating a precharge drive of the bit line precharge voltage generating device shown in Example  FIG. 1 . 
           [0010]    Example  FIG. 3  is a circuit diagram of precharge circuit in a semiconductor device according to embodiments. 
           [0011]    Example  FIG. 4  is a graph illustrating operation of precharge circuit according to embodiments. 
       
    
    
     DESCRIPTION 
       [0012]    Hereinafter, a semiconductor device is described referring to the accompanying drawings. 
         [0013]    Example  FIG. 1  illustrates a bit line precharge voltage generating device according to embodiments. Example  FIG. 2  is a graph illustrating a precharge drive of the bit line precharge voltage generating device shown in Example  FIG. 1 . 
         [0014]    Referring to example  FIG. 1 , a bit line precharge voltage generating device according to embodiments may include a bit line to which power source voltage VDD may be applied. The device may also include a bit line bar to which ground power VSS may be applied. The device may also include a precharge circuit. According to embodiments, precharge circuit may include NMOS transistors  31 ,  32  and  33  to output through a ½ VDD precharge voltage Vblp when the bit line and the bit line bar are in a standby state. Precharge circuit may also include precharge generator  10 , which may output a precharge voltage in the precharge circuit, and precharge controller  20 , which may operate and control the precharge circuit. 
         [0015]    Referring to example  FIGS. 1 and 2 , according to embodiments, a Vblp potential may be applied to bit line and bit line bar using three NMOS transistors  31 ,  32  and  33  before and/or after an operation of core cell. According to embodiments, after a read operation of data in a cell is completed, a precharge operation for a subsequent read or write may be performed using Vblp. By using the NMOS transistor, current may flow from a logic high level to a logic low level to precharge bit line and bit line bar. 
         [0016]    Example  FIG. 3  is a circuit diagram of precharge circuit in a semiconductor device according to embodiments. Example  FIG. 4  is a graph illustrating an operation of precharge circuit according to embodiments. 
         [0017]    Referring to  FIG. 3 , bit line may be provided to which power source voltage VDD may be applied. Bit line bar may also be provided, to which ground power VSS may be applied. There may further be provided a precharge circuit. According to embodiments, precharge circuit may include PMOS transistors  141 ,  142  and  143  and NMOS transistors  131 ,  132  and  133  for an output through a ½ VDD precharge voltage Vblp when the bit line and the bit line bar are in a standby state. Precharge circuit may further include precharge generator  110 , which may be configured to output a precharge voltage in precharge circuit, and precharge controller  120 , which may be configured to operate and control precharge circuit. 
         [0018]    According to embodiments, a current flow from a logic low level to a logic high level may be produced by using PMOS transistors  141 ,  142  and  143  configured between bit line and bit line bar. A current flow from a logic high level to a logic low level may be produced by using the NMOS transistors  131 ,  132  and  133  configured between bit line and bit line bar. This may reduce a precharge time to achieve a precharge of ½ VDD and may improve a cycle time for a high speed operation. According to embodiments, bit line may be a longest line within a memory cell array. Hence, parasitic capacitance of bit line may be large. This may cause a delay in precharging. For example, when not precharged to a desired precharge voltage level, an error may occur when reading data. According to embodiments, however, precision in reading data may increase by rapidly precharging a bit line. According to embodiments, time to arrange a subsequent memory operation may be reduced. Operation of a semiconductor device at a high speed may be optimized. 
         [0019]    According to embodiments, precharge generator  110  may be a constant voltage generator, or any voltage generator, to provide bit line and bit line bar with a precharge voltage of approximately ½ VDD. According to embodiments, precharge controller  120  may be a circuit group and may prevent an error operation for bit line and bit line bar in operation of a memory cell, in a word line on/off, sense amplifier operation, bit line/bit line bar precharge and floating time, and other operations known in the art. According to embodiments of a precharge circuit, first and second NMOS transistors  131  and  132  may be provided and may couple to bit line to bit line bar. According to embodiments, first and second PMOS transistors  141  and  142  may also be provided and may couple to bit line to bit line bar. First and second NMOS transistors  131  and  132  may be disposed in series, and first and second PMOS transistors  141  and  142  may be disposed in series. 
         [0020]    According to embodiments, third NMOS transistor  133  may also be provided and may be configured such that a gate of first NMOS transistor  131  and a gate of second NMOS transistor  132  are coupled. According to embodiments, third PMOS transistor  143  may also be provided, and may be configured such that a gate of first PMOS transistor  141  and a gate of second PMOS transistor  142  may be coupled. Sources and drains may be mutually coupled in third NMOS transistor  133  and third PMOS transistor  143 . A drain of third NMOS transistor  133  and a source of third PMOS transistor  143  may be coupled to VDD. A source of third NMOS transistor  133  and a drain of third PMOS transistor  143  may be coupled to VSS. According to embodiments, precharge controller  120  may apply a control signal to the gate of first, second, and third NMOS transistors  131 ,  132 , and  133  and first, second, and third PMOS transistors  141 ,  142 , and  143 . A layout of first, second, and third PMOS transistors  141 ,  142 , and  143  may be configured as a mirror type of the layout of first, second, and third NMOS transistors  131 ,  132  and  133 . 
         [0021]    With reference to example  FIG. 4 , a precharge circuit may include NMOS transistors  131 ,  132 , and  133  and PMOS transistors  141 ,  142 , and  143 . In such a configuration, current flow may be induced in both directions for voltage of bit line and bit line bar. This may precharge two lines to a voltage of the same level (approximately ½ VDD) within time t2. Time t2 may be more rapid than time t1, which represents a precharge time by a precharge circuit including only NMOS transistors. Hence, a precharge time may be reduced for a subsequent cell operation, which may improve an operation cycle time. 
         [0022]    Although embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.