Abstract:
This invention is an amplification circuit which limits increased power consumption and circuit surface area use and an imaging device including this amplification circuit. After initially discharging a capacitor, a signal charge corresponding to the difference between pixel signals is transferred repeatedly to the capacitor during an integration phase storing a signal charge proportional to the number of repetitions. The output of amplification is the signal charge accumulated in the capacitor. The gain is independent of the capacitor capacitance ratio. Thus the capacitor size can be smaller than conventional amplification circuits.

Description:
CLAIM OF PRIORITY 
       [0001]    This application claims priority under 35 U.S.C. 119(a) to Japanese Patent Application No. 2009-025714 filed Feb. 6, 2009. 
       TECHNICAL FIELD OF THE INVENTION 
       [0002]    The technical field of this invention is an amplifying circuit that amplifies the difference between two signals in particular is an amplifying circuit that provides noise cancellation and amplification for signals output from an image sensor. 
       BACKGROUND OF THE INVENTION 
       [0003]    Ordinary CMOS (complementary metal-oxide semiconductor) image sensors include a pixel array and a reading unit. A photodiode and an amplifier circuit are included for each pixel of the pixel array. The voltage generated by the photodiode is amplified by the amplifier circuit and output on a column signal line. The reading unit reads each one pixel twice for noise cancellation processing. This is called correlated double sampling (CDS). The image signals at the dark level (N) and signal level (NS) are each read. The new pixel signal (S) is obtained from the difference of these signals (N−NS). Analog-digital conversion (ADC) is performed for pixel signal (S) following CDS for further image processing. 
         [0004]    Each pixel is read using a technique combining a parallel system and a sequential system. Each row of the pixel array is selected in succession. Pixel signals are read in parallel from multiple columns in the selected row. The degree of parallelism changes according to the extent of read processing performed in each column. Table 1 shows the details of read processing performed in each column and the degree of parallelism. 
         [0000]    
       
         
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                 N/NS 
                   
                 Signal 
                 AD 
               
               
                   
                 Parallelism 
                 memory 
                 CDS 
                 amplification 
                 conversion 
               
               
                   
                   
               
             
             
               
                   
                 Low 
                 ◯ 
                 — 
                 — 
                 — 
               
               
                   
                 Moderate 
                 ◯ 
                 ◯ 
                 ◯ 
                 — 
               
               
                   
                 High 
                 ◯ 
                 ◯ 
                 ◯ 
                 ◯ 
               
               
                   
                   
               
             
          
         
       
     
         [0005]    Improved parallelism improves performance while keeping power consumption low. This is because integration of pixels at the column level is strongly promoted when image sensor resolution is increased. In recent years, CMOS image sensors include an amplifying circuit for each column. 
         [0006]      FIG. 26  shows an example of an ordinary switched capacitor amplifier that performs amplification and CDS of pixel signals in an image sensor of the prior art. 
         [0007]    The amplifier shown in  FIG. 26  has capacitors Ca and Cb, an operational amplifier  101  and a switch circuit  102 . One terminal of capacitor Ca is connected to a column signal line of the image sensor and the other terminal is connected to the negative input terminal of operational amplifier  101 . Capacitor Cb and switch circuit  102  are connected in parallel between the negative input terminal and the output terminal of operational amplifier  101 . Reference voltage GND is input to the positive input terminal of operational amplifier  101 . 
         [0008]    When dark level voltage Vn is output from the image sensor, switch circuit  102  is ON. The negative input terminal of operational amplifier  101  is held approximately at reference voltage GND so voltage Vn is supplied to capacitor Ca. The charge in capacitor Cb is cleared by switch circuit  102  being ON. 
         [0009]    When signal level voltage Vns is output from the image sensor, switch circuit  102  goes OFF. The negative input terminal of operational amplifier  101  is held approximately at reference voltage GND, so voltage Vns is applied to capacitor Ca. When the voltage at capacitor Ca changes from Vn to Vns, a charge corresponding to the amount of voltage change is accumulated in capacitor Cb. The output voltage Vout of operational amplifier  101  is roughly represented by the following formula. 
         [0000]        V out=( Ca/Cb )×( Vns−Vn )   (1) 
         [0010]    As shown in formula (1), the amplifier shown in  FIG. 26  amplifies the difference between dark level and signal level (Vns−Vn) at a gain according to the capacitance ratio between capacitors Ca and Cb. 
         [0011]    When an amplifier is provided for each column of the image sensor, variation in gain due to mismatching of electrostatic capacitance will be a problem. 
         [0012]    Precision in matching of electrostatic capacitance is limited by masking processing. Even when relatively large capacitors are formed with the processes of recent years, the precision remains at around 0.1%. This precision is equal to a resolution of 10 bits. When a dark scene is photographed and additional signal amplification is performed outside the camera system, an error of 0.1% instantly produces visible noise. The noise accompanying variation in amplifier gain appears as a line running from the top to the bottom on the screen. When using a wide dynamic range technique to adaptively change the gain in each column, the problem of this noise becomes even more serious. 
         [0013]    The minimum size of capacitor Cb is limited by both electrostatic capacitance matching precision and thermal noise. When high gain is required with the amplifier shown in  FIG. 26 , the size of capacitor Ca must be large. This creates a problem of the integrated circuit surface area becoming large. Capacitor C 1  is divided into multiple unit capacitors to make gain programmable and a switch circuit to switch connections between them must be provided. This causes the surface area to become even larger. Therefore, the amplifier shown in  FIG. 26  is unsuitable for a system with a high degree of parallelism where amplification is performed in each column of the image sensor. 
         [0014]    Increasing the gain in the amplifier shown in  FIG. 26  decreases the amount of feedback in operational amplifier  101 . This causes further deterioration in the dynamic characteristics. The drive capability drops when the amount of feedback decreases, so the problem that operational amplifier  101  becomes unable to drive later-stage circuitry occurs. When the direct current gain of operational amplifier  101  is increased to broaden the gain bandwidth to avoid such problems, the problem that power consumption and circuit surface area increase is produced. Therefore, gain that can be achieved with the amplifier shown in  FIG. 26  is actually limited to 8 times to 16 times. When higher gain is required, a separate amplifying stage will be provided, so increased power consumption and circuit surface area are unavoidable. 
         [0015]    The present invention was devised in consideration of this situation, with the objective of providing an amplifying circuit with which increased power consumption and circuit surface area can be limited, and an imaging device provided with such an amplifying circuit. 
       SUMMARY OF THE INVENTION 
       [0016]    The amplifying circuit pertaining to a first viewpoint of the present invention is an amplifying circuit that amplifies the difference between a first signal and second signal and has a first capacitor provided between a first node and a second node, a second capacitor provided between a third node and a fourth node, an input circuit that inputs the first signal or the second signal to the first node, a first switch circuit that connects the second node to a reference voltage, a second switch circuit that connects the second node to the third node, a current supply circuit that supplies current to the fourth node so that the voltage at the third node will approach the reference voltage, and a second capacitor discharge circuit that discharges the charge in the second capacitor. With the amplifying circuit in an initial phase, the second capacitor discharge circuit discharges the charge in the second capacitor. With the amplifying circuit in an integration phase, a first signal accumulation operation in which the first switch circuit is ON, the second switch circuit is OFF and the input circuit inputs the first signal to the first node. Following the first signal accumulation operation, a second signal accumulation operation in which the first switch circuit is OFF occurs, the second switch circuit being ON and the input circuit inputs the second signal to the first node are repeated a number of times corresponding to the amplification factor. 
         [0017]    With the amplifying circuit in the initial phase, the charge in the second capacitor is discharged by the second capacitor discharge circuit. 
         [0018]    With the first signal accumulation operation in the integration phase, the second node is connected to the reference voltage through the first switch circuit, and the first signal is input to the first node by the input circuit, so a charge corresponding to the first signal is accumulated in the first capacitor. 
         [0019]    With the second signal accumulation operation following the first signal accumulation operation, the first switch circuit is OFF and the second switch circuit is ON, so the charge can move from the first capacitor to the second capacitor. In this instance, the second signal is input to the first node by the input circuit also being supplied to the fourth node so that the voltage at the third node will approach the reference voltage, so a charge corresponding to the second signal is accumulated in the first capacitor. In addition, a charge corresponding to the difference between the first signal and the second signal is transferred to the second capacitor from the first capacitor. 
         [0020]    A charge corresponding to the difference between the first signal and the second signal is accumulated in the second capacitor by the first signal accumulation operation and the second signal accumulation operation being repeated. The amount of the accumulated charge increases by the number of the repetitions being increased. 
         [0021]    Ideally, the amplifying circuit could also have a third switch circuit that connects the fourth node to the current output terminal of the current supply circuit, a fourth switch circuit that connects the fourth node to the reference voltage, a fifth switch circuit that connects the first node to the current output terminal of the current supply circuit, and a first capacitor discharge circuit that discharges the charge in the first capacitor. Then, with the circuit, in the integration phase, the fourth switch circuit and the fifth switch circuit could be OFF. In at least the second signal accumulation operation in the integration phase, the third switch circuit could be ON. In a discharge phase after the integration phase, the first capacitor discharge circuit could discharge the charge in the first capacitor. In a charge transfer phase after the discharge phase, the first switch circuit and the third switch circuit could be OFF, the second switch circuit, the fourth switch circuit and the fifth switch circuit could be ON, and the current supply circuit could supply current to the first node so that the voltage at the third node will approach the reference voltage. 
         [0022]    With the amplifying circuit, in the discharge phase after the integration phase, the charge in the capacitor is discharged by the first capacitor discharge circuit. Then, in the charge transfer phase after the discharge phase, the first switch circuit is OFF and the second switch circuit is ON, so the charge can move from the second capacitor to the first capacitor. In this instance, when the third switch circuit is OFF, the fifth switch circuit is ON, and current is supplied to the first node so that voltage at the third node will approach the reference voltage, the charge is transferred from the second capacitor to the first capacitor so that the voltage at the third node will approach the reference voltage. Said fourth switch circuit is ON, so approximately all the charge accumulated in the second capacitor is transferred to the first capacitor. 
         [0023]    Ideally, the amplifying circuit could also have a third capacitor provided between a fifth node and the second node, and a sixth switch circuit that connects the fifth node to the current output terminal. Said current supply circuit could also output current corresponding to the voltage difference between the voltage at the fifth node and the reference voltage. In this case, in the initial phase, the second switch circuit and the fifth switch circuit could be OFF and the first switch circuit and the sixth switch circuit could be ON, and in the second signal accumulation operation in the integration phase and the charge transfer phase, the sixth switch circuit could be OFF. 
         [0024]    Ideally, the amplifying circuit could also have a seventh switch circuit that connects the fifth node to the third node. In this case, in the first signal accumulation operation in the integration phase, the third switch circuit and the seventh switch circuit could be ON, and the sixth switch element could be OFF. In the second signal accumulation operation in the integration phase, the third switch circuit could be ON, and the sixth switch circuit and the seventh switch circuit could be OFF. In the discharge phase, the third switch circuit and the seventh switch circuit could be ON, and the sixth switch circuit could be OFF. In the charge transfer phase, the third switch circuit, the sixth switch circuit, and the seventh switch circuit could be OFF. 
         [0025]    Ideally, with the amplifying circuit, in the initial phase, the third switch circuit could be OFF, and the fourth switch circuit and the seventh switch circuit could be ON. In this case, the fourth switch circuit, the seventh switch circuit and the sixth switch circuit, which form a conduction path in the initial phase, and the current supply circuit, which supplies discharge current to the conduction path, could also operate as the second capacitor discharge circuit. 
         [0026]    Ideally, the amplifying circuit could also have an eighth switch circuit that connects a sixth node shared by the first switch circuit and the third capacitor to the second node, and a ninth switch circuit that connects the fifth node to the second node. In this case, in the initial phase, the integration phase, the discharge phase and the charge transfer phase, the eighth switch circuit could be ON, and the ninth switch circuit could be OFF. In a correction phase after the charge transfer phase, the first switch circuit, the fifth switch circuit and the ninth switch circuit could be ON, and the second switch circuit, the third switch circuit, the sixth switch circuit, the seventh switch circuit, and the eighth switch circuit could be OFF. 
         [0027]    Ideally, the first capacitor could also comprise multiple unit capacitors connected in parallel. In this case, the amplifying circuit could also have a selection circuit that selects at least some of the multiple unit capacitors according to a gain setting signal, and that connects the selected unit capacitors between the first node and the second node, in the charge transfer phase. 
         [0028]    Ideally, the input circuit could also input the first signal, the second signal, a first reference signal or a second reference signal to the first node. In this case, with the amplifying circuit, in the integration phase, a first reference signal accumulation operation in which the first switch circuit is ON, the second switch circuit is OFF, and the input circuit inputs the first reference signal to the first node, and following the first reference signal accumulation operation, a second reference signal accumulation operation in which the first switch circuit is OFF, the second switch circuit is ON, and the input circuit inputs the second reference signal to the first node, could be repeated a number of times corresponding to the amplification factor. 
         [0029]    Ideally, the amplifying circuit could also have a tenth switch circuit that connects the first node to the reference voltage, and in the discharge phase, the first switch circuit and the tenth switch circuit could be ON. In this case, the first switch circuit and the tenth switch circuit, which form a conduction path in the discharge phase, could operate as the first capacitor discharge circuit. 
         [0030]    Ideally, the amplifying circuit could also have a hold circuit that holds the first signal and the second signal, each of which is generated at a prescribed timing. 
         [0031]    The imaging device pertaining to a second viewpoint of the present invention is provided with a pixel array comprising multiple pixel circuits arranged in a matrix form, a pixel scan circuit that successively selects each row of the pixel array and outputs a first signal corresponding to noise level and a second signal corresponding to imaging level from each of the N pixel circuits belonging to the selected row, and N of the aforementioned amplifying circuits, each of which amplifies the difference between the first signal and the second signal output from the N pixel circuits. 
         [0032]    With the present invention, amplification is performed by repetitive accumulation in capacitors of a charge corresponding to the difference between two signals which are input, so increased power consumption and circuit surface area can be limited. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0033]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0034]      FIG. 1  shows an example of the configuration of an imaging device pertaining to a first embodiment; 
           [0035]      FIG. 2  shows an example of the configuration of a pixel circuit; 
           [0036]      FIG. 3  shows an example of the configuration of a vertical scan circuit; 
           [0037]      FIG. 4  shows an example of the configuration of a signal hold circuit; 
           [0038]      FIG. 5  shows an example of the configuration of a read circuit; 
           [0039]      FIG. 6  shows an example of the configuration of a serial conversion circuit; 
           [0040]      FIG. 7  shows an example of the read circuit of  FIG. 5  connected in the initial phase; 
           [0041]      FIG. 8  shows an example of the read circuit of  FIG. 5  connected in the second signal accumulation operation; 
           [0042]      FIG. 9  shows an example of the read circuit of  FIG. 5  connected in the first signal accumulation operation; 
           [0043]      FIG. 10  shows an example of the read circuit of  FIG. 5  connected in the discharge phase; 
           [0044]      FIG. 11  shows an example of the read circuit of  FIG. 5  connected in the charge transfer phase; 
           [0045]      FIG. 12  shows an example of the read circuit of  FIG. 5  connected in the correction phase. 
           [0046]      FIG. 13  shows an example of the configuration of a read circuit in a second embodiment; 
           [0047]      FIG. 14  shows an example of the read circuit of  FIG. 13  connected in the charge transfer phase; 
           [0048]      FIG. 15  shows an example of the configuration of a read circuit in a third embodiment; 
           [0049]      FIG. 16  shows an example of the read circuit of  FIG. 15  connected in the first reference signal accumulation operation; 
           [0050]      FIG. 17  shows an example of the read circuit of  FIG. 15  connected in the second reference signal accumulation operation; 
           [0051]      FIG. 18  shows an example of the configuration of a read circuit in a fourth embodiment; 
           [0052]      FIG. 19  shows an example of the read circuit of  FIG. 18  in the initial phase; 
           [0053]      FIG. 20  shows an example of the read circuit of  FIG. 18  connected in the second signal accumulation operation; 
           [0054]      FIG. 21  shows an example of the read circuit of  FIG. 18  connected in the first signal accumulation operation; 
           [0055]      FIG. 22  shows an example of the read circuit of  FIG. 18  connected in the discharge phase; 
           [0056]      FIG. 23  shows an example of the read circuit of  FIG. 18  connected in the charge transfer phase; 
           [0057]      FIG. 24  shows an example of the configuration of a read circuit in a fifth embodiment; 
           [0058]      FIG. 25  shows an example of the configuration of a serial conversion circuit in a sixth embodiment; and 
           [0059]      FIG. 26  shows an example of an ordinary switched capacitor amplifier that performs amplification and CDS of pixel signals in an image sensor of the prior art. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0060]    In the Figures:  1  is a pixel array;  10  is a pixel circuit;  2  is a vertical scan circuit;  3  is a read processing circuit;  4  is a control circuit;  21  is a pulse shift circuit;  31 - 1  to  31 - j  are signal hold circuits;  32 ,  32 A,  32 B,  32 C,  32 D and  32 - 1  to  32 - j  are read circuits;  33  is a serial conversion circuit;  34  is an analog-digital conversion circuit;  301  and  302  are buffer circuits;  303  is a switch circuit;  304  is a current source;  305  and  306  are operational amplifiers; C 1  to C 3 , CM 1  to CMj and CMA 1  to CMAj are capacitors; SW 1  to SW 13  are switch circuits; PD is a photodiode; Q 1  to Q 4  are MOS transistors; LR 1  to LRi are row signal lines; and LC 1  to LCj are column signal lines. 
         [0061]      FIG. 1  shows an example of the configuration of an imaging device pertaining to a first embodiment of the present invention. The imaging device pertaining to this embodiment has a pixel array  1 , a vertical scan circuit  2 , a read processing circuit  3 , and a control circuit  4 . 
         [0062]    Pixel array  1  is an embodiment of the pixel array in the present invention. 
         [0063]    Vertical scan circuit  2  is an embodiment of the pixel scan circuit in the present invention. 
         [0064]    Pixel array  1  has multiple pixel circuits  10  that convert light from photographed subjects to electrical signals. Pixel circuits  10  are arranged in a matrix form, and are connected to common row signal lines LR 1 , LR 2 , . . . in each row, and are connected to common column signal lines LC 1 , LC 2 , . . . in each column. 
         [0065]      FIG. 2  shows an example of the configuration of pixel circuit  10 . A pixel circuit  10  has a photodiode PD that receives light from a photographed subject to generate a light charge, and n-type MOS transistors Q 1  to Q 4 . 
         [0066]    The anode of photodiode PD is connected to reference voltage GND, and the cathode is connected to a floating region FD through MOS transistor (transfer transistor) Q 1 . MOS transistor (reset transistor) Q 2  is connected between power line VDD and floating region FD. The gate of MOS transistor (amplifying transistor) Q 3  is connected to floating region FD, the drain is connected to power line VDD, and the source is connected to output Pout through MOS transistor (selection transistor) Q 4 . Control signals φt, φr and φx are input through the row signal lines (LR 1 , LR 2 , . . . ) to the gates of MOS transistors Q 1 , Q 2  and Q 4 . The pixel signals generated in pixel circuits  10  are output to the column signal lines (LC 1 , LC 2 , . . . ) from output Pout. 
         [0067]    Pixel circuits  10  shown in  FIG. 2  operate as below. 
         [0068]    When a new field is entered, transfer transistor Q 1  and reset transistor Q 2  are set to OFF, and an accumulation period is started. In the accumulation period, a light charge generated according to light from a photographed subject is accumulated in photodiodes PD. 
         [0069]    When the accumulation period ends, transfer transistor Q 1  is set to OFF, and reset transistor Q 2  is ON. The charge in floating region FD is reset by this. In the reset mode, the output signal from amplifying transistor Q 3  is read as reset level signal N. 
         [0070]    After the charge in floating region FD is reset, transfer transistor Q 1  is ON, and reset transistor Q 2  to OFF. The light charge accumulated in photodiode PD is transferred to floating region FD, which is in reset mode, by this. After light charge transfer, transfer transistor Q 1  is again set to OFF. With the light charge transferred to floating region FD, the output signal from amplifying transistor Q 3  is read as pixel signal NS. Pixel signal NS includes a component for the light charge accumulated in the capacitance of photodiode PD, and a component for reset level signal N. A pixel signal S in which the noise portion of the reset level has been canceled is obtained by subtracting reset level signal N from pixel signal NS. 
         [0071]    When one field ends in this way, the same operation is repeated in the next field. When signals (N, NS) are read in read processing circuit  3 , control signal φx is set to high level, and selection transistor Q 4  is ON. 
         [0072]    Vertical scan circuit  2  successively selects pixel rows and columns in pixel array  1  one row at a time, and outputs the pixel signals in pixel circuits  10  that belong to a selected row to the respective column signal lines LC 1 , LC 2 , . . . 
         [0073]      FIG. 3  shows an example of the configuration of vertical scan circuit  2 . Vertical scan circuit  2  shown in  FIG. 3  has a pulse shift circuit  21  and a switch circuit  22 . 
         [0074]    Pulse shift circuit  21  generates pulse signals that are successively shifted according to control signals (start signal, vertical scan lock signal, etc.) generated by control circuit  4 . Pulse shift circuit  21  is configured with a shift register, for example. 
         [0075]    Switch circuit  22  connects the control signal lines (φr, φt, φx) of pixel circuits  10  to any one of row signal lines LR 1  to LRi corresponding to the pulse signal of pulse shift circuit  21 . Switch circuit  22  is configured with a transistor that turns ON and OFF according to the pulse signal from pulse shift circuit  21 , as shown in  FIG. 3 , for example. 
         [0076]    Read processing circuit  3  reads pixel signals from one row of pixel circuits  10  in pixel array  1  selected successively by vertical scan circuit  2 , and applies processing, such as CDS, amplification, and AD conversion, to the pixel signals that are read to generate pixel data Pdat. 
         [0077]    Read processing circuit  3  has signal hold circuits  31 - 1  to  31 - j , read circuits  32 - 1  to  32 - j , a serial conversion circuit  33 , and an analog-digital conversion circuit  34 , as shown in  FIG. 1 , for example. 
         [0078]    Signal hold circuit  31 - k  (k represents any integer from 1 to j) holds reset level signal N and pixel signal NS read from pixel circuit  10  through a column hold line LCk. 
         [0079]      FIG. 4  shows an example of the configuration of signal hold circuit  31 - k . Signal hold circuit  31 - k  shown in  FIG. 4  has capacitors Cn and Cns, buffer circuits  301  and  302 , a switch circuit  303 , and a current source  304 . 
         [0080]    Current source  304  is connected to the output of pixel circuit  10  through column hold line LCk, and sends a constant current to the source of amplifying transistor Q 3  ( FIG. 2 ). 
         [0081]    One terminal of capacitors Cn and Cns is connected to reference voltage GND, and the other terminal is connected to column signal line LCk through switch circuit  303 . Switch circuit  305  selectively connects capacitors Cn and Cns and column signal line LCk in response to control by control circuit  4 . 
         [0082]    During the period when reset level signal N is output from pixel circuits  10 , capacitor Cn and column signal line LCk are connected. During the period when pixel signal NS is output, capacitor Cns and column line signal LCk are connected. Reset level signal N is held in capacitor Cn by this, and voltage Vn corresponding to it is output from buffer circuit  301 . Pixel signal NS is held in capacitor Cns. A voltage Vns corresponding to pixel signal NS is output from buffer circuit  302 . 
         [0083]    Read circuit  32 - k  accepts input of reset level signal N and pixel signal NS held in signal hold circuit  31 - k , and amplifies and outputs the difference. 
         [0084]      FIG. 5  shows an example of the configuration of read circuit  32 - k . Note that read circuit  32 - k  may be represented with the symbol ‘ 32 ’. 
         [0085]    In the example in  FIG. 5 , read circuit  32  has switch circuits SW 1  to SW 12 , capacitors C 1 -C 3 , and an operational amplifier  305 . 
         [0086]    Capacitor C 1  is an embodiment of the first capacitor in the present invention. 
         [0087]    Capacitor C 2  is an embodiment of the second capacitor in the present invention. 
         [0088]    The circuit that includes switch circuits  11  and  12  is an embodiment of an input circuit in the present invention. 
         [0089]    Switch circuits SW 1 -SW 10  are examples of the first through tenth switch circuits in the present invention. 
         [0090]    Operational amplifier  305  is an embodiment of the current supply circuit in the present invention. 
         [0091]    Switch circuit SW 11  inputs reset level signal N (voltage Vn) held in signal hold circuit  31 - k  to node N 1 . 
         [0092]    Switch circuit SW 12  inputs pixel signal NS (voltage Vns) held in signal hold circuit  31 - k  to node N 1 . 
         [0093]    Switch circuit SW 10  connects node N 1  to reference voltage GND. 
         [0094]    Capacitor C 1  is provided between node N 1  (first node) and node N 2  (second node). 
         [0095]    Capacitor C 2  is provided between node N 3  (third node) and node N 4  (fourth node). 
         [0096]    Switch circuit SW 8  connects node  6  (sixth node) to node N 2 . 
         [0097]    Switch circuit SW 1  connects node N 6  to reference voltage GND. When switch circuit SW 8  is ON, switch circuit SW 1  connects node N 2  to reference voltage GND. 
         [0098]    Switch circuit SW 2  connects node N 6  to node N 3 . When switch circuit SW 8  is ON, switch circuit SW 2  connects node N 2  to node N 3 . 
         [0099]    Operational amplifier  305  generates current according to the voltage difference between a positive input terminal input to reference voltage GND and a negative input terminal connected to node N 5  (fifth node), and outputs it to node N 4 . Operational amplifier  305  is an OTA (operational transconductance amplifier), for example, the gain (transconductance) of which is very large. For this reason, voltage at node N 5  will be approximately equal to reference voltage GND by the action of negative feedback of current supplied to node N 4  from operational amplifier  305 . 
         [0100]    Capacitor C 3  is provided between node N 5  and node N 6 . 
         [0101]    Switch circuit SW 6  connects node N 5  to the current output terminal of operational amplifier  305 . 
         [0102]    Switch circuit SW 7  connects node N 5  to node N 3 . 
         [0103]    Switch SW 9  connects node N 5  to node N 2 . 
         [0104]    Switch circuit SW 4  connects node N 4  to reference voltage GND. 
         [0105]    Switch circuit SW 3  connects node N 4  to the current output terminal of operational amplifier  305 . 
         [0106]    Switch circuit SW 5  connects the current output terminal of operational amplifier  305  to node N 1 . 
         [0107]    With read circuit  32  shown in  FIG. 5 , by charge corresponding to the difference (Vn−Vns) between reset level signal N (voltage Vn) and pixel signal NS (voltage Vns) being transferred repeatedly from capacitor C 1  to capacitor C 2 , a signal charge which has been integrated according to the number of repetitions is accumulated in capacitor C 2 . Accurate gain that is not dependent on the capacitance of capacitors C 1  and C 2  is obtained by returning the signal charge accumulated in capacitor C 2  to capacitor C 1 . 
         [0108]    Detailed operation by read circuit  32  is explained later by referring to  FIGS. 7-12 . 
         [0109]    Serial conversion circuit  33  converts pixel signals output in parallel from the read circuits ( 32 - 1  to  32 - j ) to a serial signal string. 
         [0110]      FIG. 6  shows an example of the configuration of serial conversion circuit  33 . 
         [0111]    Serial conversion circuit  33  shown in  FIG. 6  has capacitors CM 1 -CMj provided at the outputs of read circuits  32 - 1  to  32 - j , switch circuits SA 1  to SAj, SB 1  to SBj, SC 1  to SCj and SD 1  to SDj, and an OTA or other operational amplifier  306 . 
         [0112]    Capacitor CMk (k=1-j) holds pixel signal Ps output from read circuit  32 - k  . One terminal of capacitor CMk is connected to the output of read circuit  32 - k  through switch circuit SAk, and is also connected to the output of operational amplifier  306  through switch circuit SCk. The other terminal of capacitor CMk is connected to reference voltage GND through switch circuit SBk and is also connected to the negative input terminal of operational amplifier  306  through switch circuit SDk. The positive input terminal of operational amplifier  306  is connected to reference voltage GND. 
         [0113]    In the period when amplified pixel signals Ps are output from read circuits  32 - 1  to  32 - j , switch circuits SA 1  to SAj and SB 1  to SBj are all ON, and switch circuits SC 1  to SCj and SD 1  to SDj are all OFF. Pixel signals Ps output from read circuits  32 - 1  to  32 - j  are held by capacitors CM 1  to CMj, respectively, by this. 
         [0114]    When the output period for pixel signals Ps ends, switch circuits SA 1  to SAj and SB 1  to SBj all go OFF, and switch circuits SC 1  to SCj and SD 1  to SDj successively come ON. Switch pairs successively turn ON in the situation of switch circuits SC 1  and SD 1 , SC 2  and SD 2 , SC 3  and SD 3 , . . . When one pair turns ON, another pair turns OFF. When a pair of switch circuits comes ON in succession, capacitors CM 1  to CMj are connected one at a time in succession between the negative input terminal and the output terminal of operational amplifier  306 . Due to the action of negative feedback, the negative input terminal of operational amplifier  306  will be approximately equal to reference voltage GND, so at the output of operational amplifier  306 , voltage approximately equal to the voltage in the capacitor (CM 1  to CMj) connected at that time is generated. In this way, pixel signals Ps held in capacitors CM 1  to CMj are output serially from operational amplifier  306 . 
         [0115]    Analog-digital conversion circuit  34  converts pixel signal Sout output serially from serial conversion circuit  33  to a digital signal with a prescribed bit length, and outputs it as pixel data Pdat. 
         [0116]    Control circuit  4  generates control signals for controlling the individual components of the imaging device. 
         [0117]    For example, control circuit  4  generates control signals φt, φr, φx) for generated pixel signals in pixel circuits  10 , control signals for successively selecting each row in pixel array by vertical scan circuit  2 , control signals for holding the signals (N, NS) from pixel circuits  10  by signal hold circuits  31 - 1  to  31 - j , control signals to supply [the previous signals] to the switch circuits (SW 1 -SW 12 ) with read circuits  32 - 1  to  32 - j , controls signals for obtaining a serial signal string with serial conversion circuit  33 , etc. 
         [0118]    Here, the operation of an imaging device that has the configuration described above will be explained in detail concentrating on read circuit  32 . 
         [0119]    The row signal lines (LR 1 , . . . LRj) are successively activated as a result of scanning by vertical scan circuit  2 . When a row signal line is activated, the pixel signals (N, NS) from the pixel circuits  10  in the one line (one line) connected to it are output. The pixel signals are input to read processing circuit  3  through the column signal lines (LC 1  to LCj) and are held in signal hold circuits  31 - 1  to  31 - j . When one line of pixel signals N and NS are held in signal hold circuits  31 - 1  to  31 - j , operation to amplify the difference (NS−N) between the pixel signals is started in read circuits  32 - 1  to  32 - j.    
         [0120]    With read circuit  32 , the amplification operation proceeds in steps with multiple phases (initial phase, integration phase, discharge phase, charge transfer phase, correction phase). 
       1. Initial Phase (FIG. 7) 
       [0121]    In the initial phase, the charge in capacitor C 2  is initialized. 
         [0122]      FIG. 7  shows an example of read circuit  32  connected in the initial phase. 
         [0123]    The ON or OFF state of each switch in the initial phase is as follows. 
         [0124]    ON: SW 1 , SW 4 , SW 6 , SW 7 , SW 8 , SW 11   
         [0125]    OFF: SW 2 , SW 3 , SW 5 , SW 9 , SW 10 , SW 12   
         [0126]    In the initial phase, the output terminal of operational amplifier  305  is connected to the negative input terminal through switch circuit SW 6 , and capacitors C 2  and C 3  are connected between the negative input terminal and the positive input terminal. The voltages at the negative input terminal and the positive input terminal will be approximately equal due to the action of negative feedback, but because operational amplifier  305  has a finite direct current gain, a minute offset voltage Vofs is held in capacitors C 2  and C 3 . 
         [0127]    In addition, in the connection mode illustrated in  FIG. 7 , reset level signal N (voltage Vn) is input to node N 1 , and reference voltage GND is input to node N 2 , so reset level signal N (voltage Vn) is held in capacitor C 1 . 
       2. Integration Phase (FIG. 7, FIG. 8, FIG. 9) 
       [0128]    In the integration phase, by charge (hereafter called ‘signal charge’) corresponding to the difference (Vn−Vns) between reset level signal N and pixel signal NS being transferred repeatedly from capacitor C 1  to capacitor C 2 , a signal charge that is integrated according to the number of repetitions is accumulated in capacitor C 2 . 
         [0129]    In concrete terms, the set of first signal accumulation operation and second signal accumulation operation described next is repeated according to the amplification factor (gain). 
         [0130]    That is, with the first signal accumulation operation, charge corresponding to reset level signal N (voltage Vn) is accumulated in capacitor C 1 . 
         [0131]    With the second signal accumulation operation following the first signal accumulation operation, charge corresponding to pixel signal NS (voltage Vns) is accumulated in capacitor C 1 , and a signal charge corresponding to the difference (Vn−Vns) is also transferred from capacitor C 1  to capacitor C 2 . 
         [0132]    First, the initial first signal accumulation operation in the integration phase is performed simultaneously with the initial phase in the connection mode shown in  FIG. 7  described above. In this instance, voltage ‘C 1 ×Vn’ corresponding to reset level signal N is accumulated in capacitor C 1 . (‘C 1 ’ also represents the electrostatic capacitance of capacitor C 1 . The same holds for capacitors C 2  and C 3 .) 
         [0133]    Following the first signal accumulation operation performed simultaneously with the initial phase, the second signal accumulation operation is performed. 
         [0134]      FIG. 8  shows an example of read circuit  32  connected in the second signal accumulation operation. 
         [0135]    The ON or OFF state of each switch in the second signal accumulation operation is as follows. 
         [0136]    ON: SW 2 , SW 3 , SW 8 , SW 12   
         [0137]    OFF: SW 1 , SW 4 , SW 5 , SW 6 , SW 7 , SW 9 , SW 10 , SW 11   
         [0138]    With the second signal accumulation operation, pixel signal (voltage Vns) is input to node N 1 , the output terminal of operational amplifier  305  is connected to node N 2  through capacitor C 2 , and node N 5  is connected to node N 2  through capacitor C 3 . 
         [0139]    In this instance, offset voltage Vofs occurring at the negative input terminal (node N 5 ) of operational amplifier  305  and the voltage held in capacitor C 3  in the first signal accumulation operation are approximately equal, so the two voltages cancel out, and the voltage at node N 2  will be approximately equal to reference voltage GND. 
         [0140]    Because the voltage at node N 2  is approximately equal to reference voltage GND, a charge ‘C 1 ×Vns’ is accumulated in capacitor C 1 . Charge ‘C 1 ×Vn’ was accumulated in capacitor C 1  in the immediately preceding first signal accumulation operation, so a differential signal charge ‘C 1 (Vn−VnS)’ is transferred from capacitor C 1  to capacitor C 2 . 
         [0141]    Offset voltage Vofs at operational amplifier  305  is canceled by the voltage held in capacitor C 3 , so error produced by offset voltage Vofs when charge is transferred from capacitor C 1  to capacitor C 2  is approximately canceled. 
         [0142]    Relating to the effect of the finite direct current gain of operational amplifier  305 , error is present due to the fact that the output voltage of operational amplifier  305  changes accompanying integration of the signal charge. However, because the direct current gain of operational amplifier  305  is approximately constant in the signal range, the error is proportional to the integration result, so it becomes a constant gain error. For this reason, there is not much of a problem in the image sensor. 
         [0143]    Following the second signal accumulation operation described above, the second and subsequent first signal accumulation operations are performed using the connection status shown in  FIG. 9 . 
         [0144]    The ON or OFF state of each switch in the second and subsequent first signal accumulation operations is as follows. 
         [0145]    ON: SW 1 , SW 3 , SW 7 , SW 8 , SW 11   
         [0146]    OFF: SW 2 , SW 4 , SW 5 , SW 6 , SW 9 , SW 10 , SW 12   
         [0147]    In the first signal accumulation operation shown in  FIG. 9 , reset level signal N (voltage Vn) is input to node N 1 , and node N 2  is connected to reference voltage GND, so reset level signal N (voltage Vn) is held in capacitor C 1 . 
         [0148]    With the first signal accumulation operation shown in  FIG. 9 , the output terminal of operational amplifier  305  is connected to node N 5  through capacitor C 2 , and node N 5  is connected to reference voltage GND through capacitor C 3 . In this instance, the voltage held in capacitor C 3  and offset voltage Vofs occurring at node N 5  are approximately equal, so the amount of charge in capacitor C 3  does not change from the value in the immediately preceding second signal accumulation operation. Therefore, the amount of charge in capacitor C 3  connected in series with capacitor C 2  is also kept approximately the same. 
         [0149]    In the second signal accumulation operation, the connection point of node N 3  changes from reference voltage GND to node N 5 , so the output voltage (Ps) of operational amplifier  305  shifts by the amount of offset voltage Vofs. 
       3. Discharge Phase (FIG. 10) 
       [0150]    In the discharge phase, the charge accumulated in capacitor C 1  in the last second signal accumulation operation of the integration phase is discharged. 
         [0151]      FIG. 10  shows an example of read circuit  32  connected in the discharge phase. 
         [0152]    The ON or OFF state of each switch circuit in the discharge phase is as follows. 
         [0153]    ON: SW 1 , SW 3 , SW 7 , SW 8 , SW 10   
         [0154]    OFF: SW 2 , SW 4 , SW 5 , SW 6 , SW 9 , SW 11 , SW 12   
         [0155]    In the discharge phase, node N 1  and node N 2  are connected to reference voltage GND, so the charge accumulated in capacitor C 1  in the integration phase is discharged. 
         [0156]    In addition, in the discharge phase, the output terminal of operational amplifier  305  is connected to node N 5  through capacitor C 2 , and node N 5  is connected to reference voltage GND through capacitor C 3 , the same as the first signal accumulation operation shown in  FIG. 9 , so the charge in capacitor C 2  is kept constant. 
         4 . Charge Transfer Phase (FIG. 11) 
       [0157]    In the charge transfer phase, the integrated charge in capacitor C 2  is transferred to capacitor C 1 . 
         [0158]      FIG. 11  shows an example of read circuit  32  connected in the charge transfer phase. 
         [0159]    The ON or OFF state of each switch circuit in the charge transfer phase is as follows. 
         [0160]    ON: SW 2 , SW 4 , SW 5 , SW 8   
         [0161]    OFF: SW 1 , SW 3 , SW 6 , SW 7 , SW 9 , SW 10 , SW 11 , SW 12   
         [0162]    In the charge transfer phase, the output terminal of operational amplifier  305  is connected to node N 2  through capacitor C 1 , node N 5  is connected to node N 2  through capacitor C 3 , and node N 2  is connected to reference voltage GND through capacitor C 2 . In this case, negative feedback works so that the voltage at node N 2  is approximately equal to reference voltage GND, so the voltage at capacitor C 2  will be zero, and the charge accumulated in capacitor C 2  is all transferred to capacitor C 1 . 
         [0163]    When one set of the first signal accumulation operation and the second signal accumulation operation have been performed, voltage ‘C 1 ×(Vn−Vns)’ is accumulated in capacitor C 2 . Therefore, when the operations are repeated for K sets, charge Qs represented by the following formula is accumulated in capacitor C 2 . 
         [0000]        Qs=KC 1×( Vn−Vns )   (2) 
         [0164]    When charge Qs is returned to capacitor C 1  again, voltage Vc 1  generated at capacitor C 1  is represented with the following formula 
         [0000]        Vc 1 =Qs/C 1 =Kx ( Vn−Vns )   (3) 
         [0165]    As shown in formula (3), voltage Vc 1  of capacitor C 1  is proportional to the number of operations K of the accumulation operations and does not depend on the electrostatic capacitance of capacitors C 1  and C 2 . 
       5. Correction Phase (FIG. 12) 
       [0166]    In the correction phase, the offset voltage Vofs component included in voltage Vc 1  of capacitor C 1  is corrected. 
         [0167]      FIG. 12  shows an example of read circuit  32  connected in the correction phase. 
         [0168]    The ON or OFF state of each switch in the correction phase is as follows. 
         [0169]    ON: SW 1 , SW 5 , SW 9   
         [0170]    OFF: SW 2 , SW 3 , SW 4 , S 6 , SW 7 , SW 8 , SW 10 , SW 11 , SW 12   
         [0171]    In the correction phase, the output terminal of operational amplifier  305  is connected to node N 5  through capacitor C 1 , and node N 5  is connected to reference voltage GND through capacitor C 3 . 
         [0172]    In this case, the voltage held at capacitor C 3  and offset voltage Vofs produced at node N 5  are approximately equal, so the amount of charge in capacitor C 3  does not change from the value in the immediately preceding charge transfer phase. Therefore, the amount of charge in capacitor C 1 , which is connected in series with capacitor C 3 , is kept approximately the same. 
         [0173]    On the other hand, the voltage at node N 2  is approximately equal to reference voltage GND in the charge transfer phase, but shifts by the amount of offset voltage Vofs from reference potential GND in the correction phase. That is, while the amount of charge in capacitor C 1  is held, the voltage at node N 2  shifts by the amount of offset voltage Vofs. For this reason, the output voltage (voltage at node N 1 ) of operational amplifier  305  shifts by the amount of offset voltage Vofs, compared to the charge transfer phase. 
         [0174]    This voltage shift cancels the error component produced by offset voltage Vofs applied to capacitor C 2  in the initial phase. That is, the error component produced by offset voltage Vofs remaining in voltage Vol of capacitor C 1  is corrected in the correction phase. 
         [0175]    Pixel signals Ps amplified as described above are output at one time from read circuits  32 - 1  to  32 - j . Pixel signals Ps output from read circuits  32 - 1  to  32 - j  are held in capacitors CM 1  to CMj of the respective serial conversion circuit  33  ( FIG. 6 ). Pixel signals Ps held in capacitors CM 1  to CMj are serially output in succession through operational amplifier  306 . The pixel signals that are output serially from serial conversion circuit  33  are converted to digital pixel data Pdat in analog-digital conversion circuit  34 . 
         [0176]    As explained above, with this embodiment, after the charge in capacitor C 2  is discharged in the initial phase ( FIG. 7 ), a signal charge corresponding to the difference between pixel signals (N−NS) is repeatedly transferred to capacitor C 2  in the integration phase. That is, in the integration phase, in the first signal accumulation operation ( FIG. 7 ,  FIG. 9 ), a charge corresponding to reset signal N is accumulated in capacitor C 1 , and in the second signal accumulation operation following the first signal accumulation operation ( FIG. 8 ), a charge corresponding to pixel signal NS is accumulated in capacitor C 1 , and a signal charge corresponding to the difference (N−NS) is also transferred from capacitor C 1  to capacitor C 2 . The first signal accumulation operation and the second signal accumulation operation are repeated a number of times corresponding to the gain setting value. 
         [0177]    In this way, with this embodiment, a signal charge proportional to the number of repetitions (K) of the signal accumulation operations is accumulated in capacitor C 2 , and an amplification effect based on the signal charge is obtained, so gain can be set independent of the capacitor capacitance ratio. Thus, it is not necessary to provide a large-capacitance capacitor with high gain, as in the amplifying circuit shown in  FIG. 26 , for example, so the circuit surface area can be limited. 
         [0178]    In addition, because it is not necessary to provide a large-capacitance capacitor to obtain the desired gain, a reduction in the amount of feedback produced by driving a large-capacitance capacitor is augmented, as in the amplifying circuit shown in  FIG. 26 , for example, so it is not necessary to widen the gain bandwidth of the operational amplifier or increase the direct current gain. Therefore, increased power consumption and circuit surface area in the operational amplifier can be limited. 
         [0179]    In addition, with this embodiment, because gain can be changed without switching of the capacitors, increased circuit surface area produced by providing circuitry for switching can be avoided. 
         [0180]    In addition, with this embodiment, the amplification effect is obtained by integrating signal charges in capacitor C 2 , so the integration works as a low-pass filter, and the effects of high-frequency noise can be significantly reduced. Low-frequency noise can be reduced by CDS processing by taking the difference of two input signals. 
         [0181]    In addition, with this embodiment, gain magnitude is set by transferring a repeated signal charge from capacitor C 1  to capacitor C 2 , so gain monotonicity can be assured structurally. 
         [0182]    With the amplifying circuit shown in  FIG. 26 , the ideal gain that is proportional to the capacitance ratio as shown in formula (1) is obtained by the effect of change in the amount of feedback to operational amplifier  101 , etc. Even when electrostatic capacitance value is programmable with a method of switching between multiple capacitors that have binary weighting, the gain magnitude cannot be changed monotonically relative to the value of the digital signal. On the other hand, with this embodiment, gain changes monotonically relative to the number of repetitions K of the signal accumulation operations in the integration phase, and monotonicity is not subject to effects such as the characteristics of operational amplifier  305 . For this reason, gain can be set more accurately than with the amplifying circuit shown in  FIG. 26 . 
         [0183]    In addition, with this embodiment, power consumption and circuit surface area of read circuit  32  can be limited, so overall power consumption can be kept lower while using a system with high parallelism where a read circuit  32  is provided for each column of pixel array  1 . Furthermore, because the integration phase time for each read circuit  32  can be sufficiently assured in the scan period for one line, even when amplification processing time becomes somewhat longer, overall processing speed can be maintained. 
         [0184]    In addition, with this embodiment, after the repeated signal charge is transferred from capacitor C 1  to capacitor C 2  in the integration phase, the charge in capacitor C 1  is eliminated in the discharge phase ( FIG. 10 ), and the signal charge is transferred from capacitor C 2  to capacitor C 1  in the charge transfer phase ( FIG. 11 ). 
         [0185]    In this way, with this embodiment, an amplification effect that is not dependent on the electrostatic capacitances of capacitors C 1  and C 2 , as shown in formula (3), can be obtained by returning the signal charge integrated in capacitor C 2  to capacitor C 1 . Therefore, gain can be set accurately unaffected by variation in capacitor capacitance. 
         [0186]    In addition, with this embodiment, offset voltage Vofs of operational amplifier  305  is held in capacitor C 3  by a feedback path being formed from the output of operational amplifier  305  to node N 5  (negative input terminal) and by node N 5  being connected to reference voltage GND through capacitor C 3  in the initial phase ( FIG. 7 ). Offset voltage Vofs of operational amplifier  305  occurring at node N 5  is canceled by the voltage in capacitor C 3  by the output terminal of operational amplifier  305  being connected to node N 2  through capacitor C 1  and by node N 5  being connected to node N 2  through capacitor C 3  in the second signal accumulation operation ( FIG. 8 ). That is, the voltage at node N 2  will be approximately equal to reference voltage GND. Because pixel signal NS is input to capacitor C 1  from node N 1  in this state, an accurate pixel signal NS is input to capacitor C 1 , and an accurate signal charge for the difference (N−NS) is transferred from capacitor C 1  to capacitor C 2 . 
         [0187]    Therefore, with this embodiment, the integration error produced by offset voltage Vofs of operational amplifier  305  will be very small, and the error that is integrated is small, even when the signal accumulation operation is repeated many times, so high gain can be accurately set. 
         [0188]    In addition, with this embodiment, offset voltage Vofs of node N 5  is canceled by the voltage in capacitor C 3  the same way as described above in the charge transfer operation ( FIG. 11 ), as well, and the voltage at node N 2  will be approximately equal to reference voltage GND. Because signal charge is accurately transferred from capacitor C 2  to capacitor C 1 , error in offset voltage Vofs in the output signal can be reduced. 
         [0189]    In addition, with this embodiment, the output terminal of operational amplifier  305  is connected to node N 5  through capacitor C 1 , and node N 5  is connected to reference voltage GND through capacitor C 3  in the correction phase ( FIG. 12 ). Because of this, the component caused by offset voltage Vofs, which is applied to capacitor C 2  in the initial phase ( FIG. 7 ), is corrected using offset voltage Vofs held in capacitor C 3 , so error in offset voltage Vofs in the output signal can be reduced. 
         [0190]    Next, a second embodiment of the present invention will be explained. 
         [0191]    With the imaging device pertaining to the second embodiment, read circuit  32  in the imaging device pertaining to the first embodiment ( FIG. 5 ) is replaced with a read circuit  32 A in which the capacitance of capacitor C 1  is variable ( FIG. 13 ). 
         [0192]    With read circuit  32  shown in  FIG. 5 , gain is set according to the number of repetitions of the signal accumulation operations in the integration phase, but with read circuit  32 A in this embodiment, gain can additionally be adjusted according to the capacitance ratio of capacitors C 1  and C 2 . 
         [0193]      FIG. 13  shows an example of the configuration of read circuit  32 A. 
         [0194]    Read circuit  32 A shown in  FIG. 13  has capacitor C 1 , which includes two unit capacitors connected in parallel between nodes N 1  and N 2 , and switch circuits SW 14  and SW 15  provided in the conduction path between the unit capacitors and node N 2 . The other components in read circuit  32 A are the same as read circuit  32  shown in  FIG. 5 . Switch circuits SW 14  and SW 15  are an embodiment of the selection circuit in the present information. 
         [0195]    With read circuit  32 A shown in  FIG. 13 , the capacitance of capacitor C 1  is changed by switch circuits SW 14  and SW 15 . For example, assuming that the two unit capacitors have approximately the same electrostatic capacitance ‘Ct,’ the electrostatic capacitance of capacitor C 1  will be ‘Ct’ when only one switch circuit SW 14  or SW 15  is ON, and will be ‘2 Ct’ when both switch circuits SW 14  and SW 15  are ON. 
         [0196]    Switch circuits SW 14  and SW 15  are both ON in the initial phase, the integration phase and the discharge phase, and only one is ON in the charge transfer phase and the correction phase.  FIG. 14  shows read circuit  32  connected in the charge transfer phase. 
         [0197]    The electrostatic capacitance of capacitor C 1  will be one half when shifting from the integration phase to the charge transfer phase according to the operation of switch circuits SW 14  and SW 15 . When the electrostatic capacitance of capacitor C 1  changes to one half, the voltage at capacitor C 1  doubles. Thus when electrostatic capacitance does not change, the gain will double. 
         [0198]    With the example in  FIG. 13 , capacitor C 1  is configured with two unit capacitors, and the capacitance ratio of capacitors C 1  and C 2  can be changed in the desired range by appropriately setting the number of unit capacitors and the electrostatic capacitance value of each unit capacitor. 
         [0199]    In this way, with this embodiment, gain can be adjusted by changing the electrostatic capacitance ratio of capacitors C 1  and C 2  when shifting from the integration phase to the charge transfer phase. For example, gain can be X times by changing the capacitance of capacitor C 1  to 1/X when shifting from the integration phase to the charge transfer phase. The number of repetitions of the signal accumulation operations required to obtain the same gain can be reduced by achieving gain according to the change in electrostatic capacitance of capacitors C 1  and C 2 , so the time required for amplification processing can be shortened. 
         [0200]    Next, a third embodiment of the present invention will be explained. 
         [0201]    With the imaging device pertaining to the third embodiment, read circuit  32  in the imaging device pertaining to the first embodiment ( FIG. 5 ) is replaced with read circuit  32 B to which a dark level voltage VB can be input ( FIG. 15 ). 
         [0202]    With read circuit  32  shown in  FIG. 5 , the signal charge is integrated in the integration phase, but with read circuit  32 B in this embodiment, a reference charge for setting the desired dark level is integrated, in addition to the signal charge. 
         [0203]      FIG. 15  shows an example of read circuit  32 B. 
         [0204]    Read circuit  32 B shown in  FIG. 15  has a switch circuit SW 13  to input dark level voltage VB to node N 1 . The other components of read circuit  32 B are the same as read circuit  32  shown in  FIG. 5 . 
         [0205]    With read circuit  32 B shown in  FIG. 15 , in the integration phase, the signal charge is accumulated by repeating the first signal accumulation operation ( FIG. 7 ,  FIG. 9 ) and the second signal accumulation operation ( FIG. 8 ) already explained, while in addition to this, a reference charge is also integrated by repeating a first reference signal accumulation operation ( FIG. 16 ) and a second reference signal accumulation operation ( FIG. 17 ) described next. 
         [0206]      FIG. 16  shows an example of read circuit  32 B connected in the first reference signal accumulation operation. 
         [0207]    The first reference signal accumulation operation shown in  FIG. 16  is basically the same as the first signal accumulation operation shown in  FIG. 9 , and the difference is that reference voltage GND is input to node N 1 . That is, with the first reference signal accumulation operation shown in  FIG. 16 , switch circuits SW 11 , SW 12  and SW 13  are OFF, and switch circuit SW 10  is ON. 
         [0208]    The voltage in capacitor C 1  will be zero due to the first reference signal accumulation operation. 
         [0209]      FIG. 17  shows an example of read circuit  32 B connected in the second reference signal accumulation operation. 
         [0210]    The second reference signal accumulation operation shown in  FIG. 17  is basically the same as the second signal accumulation operation shown in  FIG. 8 , and the difference is that dark level voltage VB is input to node N 1 . That is, with the second reference signal accumulation operation shown in  FIG. 17 , switch circuits SW 10 , SW 11  and SW 12  are OFF, and switch circuit SW 13  is ON. 
         [0211]    With the second reference signal accumulation operation, the voltage at node N 2  is approximately equal to reference voltage GND, so a charge ‘C 1 ×VB’ is accumulated in capacitor C 1 . Because the charge in capacitor C 1  in the first reference signal accumulation operation immediately preceding is zero, a reference voltage of ‘C 1 ×(-VB)’ for the difference is transferred from capacitor C 1  to capacitor C 2 . 
         [0212]    With read circuit  32 B, first, a signal charge is accumulated in capacitor C 2  with the initial phase ( FIG. 7 ) and the second signal accumulation operation ( FIG. 8 ), and then a reference charge is accumulated in capacitor C 2  by the first reference signal accumulation operation ( FIG. 16 ) and the second reference signal accumulation operation ( FIG. 17 ). Thereafter, read circuit  32 B repeats signal charge accumulation ( FIG. 9 ,  FIG. 8 ) and reference charge accumulation ( FIG. 16 ,  FIG. 17 ) a number of times corresponding to the gain setting value. The charge accumulation sequence is arbitrary, and for example, signal charge accumulation ( FIG. 9 ,  FIG. 8 ) and reference charge accumulation ( FIG. 16 ,  FIG. 17 ) could be performed alternately, or one charge accumulation could be performed continuously, and then the other charge accumulation could be performed continuously. 
         [0213]    After a signal charge and a reference charge are accumulated in capacitor C 2  in the integration phase, read circuit  32 B transfers the charge in capacitor C 2  to capacitor C 1  with the discharge phase ( FIG. 10 ) and the charge transfer phase ( FIG. 11 ), and error in offset voltage Vofs is corrected by the correction phase ( FIG. 12 ). 
         [0214]    Signal Ps output from read circuit  32 B in this way is the equivalent of amplifying the result (Vns−Vn+VB) of dark level voltage VB added to the voltage difference between pixel signals (Vns−Vn). Therefore, with this embodiment, the dark level of pixel signals can be adjusted freely by adjusting dark level voltage VB. 
         [0215]    Note that with the example described above, dark level voltage VB is added to differential voltage (Vns−Vn), but dark level voltage VB can also be subtracted from differential voltage (Vns−Vn) by reversing the operation of switch circuits SW 10  and SW 13 . In concrete terms, dark level voltage VB could be input to node N 1  in the first reference signal accumulation operation ( FIG. 16 ) (switch circuit SW 13  is ON, switch circuit SW 10  is OFF), and reference voltage GND may be input to node N 1  in the second reference signal accumulation operation ( FIG. 17 ) (switch circuit SW 13  is OFF, switch circuit SW 10  is ON). Therefore, with this embodiment, positive or negative adjustment of the dark level can easily be accomplished. 
         [0216]    Next, a fourth embodiment of the present invention will be explained. 
         [0217]    With the imaging device pertaining to the fourth embodiment, read circuit  32  in the imaging device pertaining to the first embodiment ( FIG. 5 ) is replaced with read circuit  32 C with a simpler configuration ( FIG. 18 ). 
         [0218]      FIG. 18  shows an example of the configuration of read circuit  32 C. 
         [0219]    With read circuit  32 C shown in  FIG. 18 , switch circuits SW 7 , SW 8  and SW 9  and capacitor C 3  in read circuit  32  shown in  FIG. 5  are omitted. The locations of switch circuits SW 7  and SW 8  are shorted, and the locations of switch circuit SW 9  and capacitor C 3  are open. Otherwise the configuration of read circuit  32 C is the same as read circuit  32 . 
         [0220]    Read circuit  32 C shown in  FIG. 18  performs amplification processing in the order initial phase, integration phase, discharge phase, and charge transfer phase, and no correction phase is performed. The state of the switch circuits in each phase in read circuit  32 C is roughly the same as read circuit  32 . 
       1. Initial Phase (FIG. 19) 
       [0221]      FIG. 19  shows read circuit  32 C connected in the initial phase. 
         [0222]    The ON or OFF state of each switch circuit in the initial phase is as follows. 
         [0223]    ON: SW 1 , SW 4 , SW 6 , SW 11   
         [0224]    OFF: SW 2 , SW 3 , SW 5 , SW 10 , SW 12   
         [0225]    In the initial phase, the output terminal of operational amplifier  305  is connected to the negative input terminal, and capacitor C 2  is connected between the negative input terminal and the positive imputer terminal. Very small offset voltage Vofs from operational amplifier  305  is applied to capacitor C 2  because of this. 
         [0226]    In the meantime, reset level signal N (voltage Vn) is input to node N 1 , and node N 2  is connected to reference voltage GND. Therefore, reset level signal N (voltage Vn) is held in capacitor C 1 . 
       2. Integration Phase (FIG. 19, FIG. 20, FIG. 21) 
       [0227]    In the integration phase, the first signal accumulation operator to accumulate a charge corresponding to voltage Vn in capacitor C 1 , and a second signal accumulation operation to transfer a signal charge corresponding to difference (Vn−Vns) from capacitor C 1  to capacitor C 2  are repeated, and a signal charge is accumulated in capacitor C 2 . 
         [0228]    The first iteration of the first signal accumulation operation is performed simultaneously with the initial phase in the connection state shown in  FIG. 19 , the same as read circuit  32  shown in  FIG. 5 . After the initial phase, the second signal accumulation operation shown in  FIG. 20  is performed. Thereafter, the first signal accumulation operation shown in  FIG. 21  and the second signal accumulation operation shown in  FIG. 20  are repeated a number of times corresponding to the gain setting value. 
         [0229]      FIG. 20  shows read circuit  32 C connected in the second signal accumulation operation. 
         [0230]    The ON or OFF state of each switch circuit in the second signal accumulation operation is as follows. 
         [0231]    ON: SW 2 , SW 3 , SW 12   
         [0232]    OFF: SW 1 , SW 4 , SW 5 , SW 6 , SW 10 , SW 11   
         [0233]    With the second signal accumulation operation, voltage Vns is input to node N 1 , and the output terminal of operational amplifier  305  is connected to node N 2  through capacitor C 2 . 
         [0234]    In this instance, the negative feedback works so that the voltage at node N 2  is approximately equal to reference voltage GND, so charge ‘C 1 ×Vns’ is accumulated in capacitor C 1 , and a signal charge ‘C 1 ×(Vn−Vns)’ for the difference is transferred from capacitor C 1  to C 2 . 
         [0235]      FIG. 21  shows an example of read circuit  32 C connected in the first signal accumulation operation from the second iteration on. 
         [0236]    The ON or OFF state of each switch circuit in the first signal accumulation operation from the second iteration on is as follows. 
         [0237]    ON: SW 1 , SW 11   
         [0238]    OFF: SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 10 , SW 12   
         [0239]    In the signal accumulation operation shown in  FIG. 21 , voltage Vn is input to node N 1 , and node N 2  is connected to reference voltage GND, so voltage Vn is held at capacitor C 1 . In this instance, switch circuit SW 3  is OFF, so the charge accumulated in capacitor C 2  is kept constant. 
       3. Discharge Phase (FIG. 22) 
       [0240]    In the discharge phase, the charge accumulated in capacitor C 1  in the last second signal accumulation operation in the integration phase is discharged. 
         [0241]      FIG. 22  shows an example of read circuit  32 C connected in the discharge phase. 
         [0242]    The ON or OFF state of each switch circuit in the discharge phase is as follows. 
         [0243]    ON: SW 1 , SW 10   
         [0244]    OFF: SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 11 , SW 12   
         [0245]    In the discharge phase, node N 1  and node N 2  are connected to reference voltage GND, so the charge accumulated in capacitor C 1  in the integration phase is discharged. In addition, in this instance, because switch circuit SW 3  is OFF, the charge accumulated in capacitor C 2  is kept constant. 
       4. Charge Transfer Phase (FIG. 23) 
       [0246]      FIG. 23  shows an example of read circuit  32 C connected in the charge transfer phase. 
         [0247]    The ON or OFF state of each switch in the charge transfer phase is as follows. 
         [0248]    ON: SW 2 , SW 4 , SW 5   
         [0249]    OFF: SW 1 , SW 3 , SW 6 , SW 10 , SW 11 , SW 12   
         [0250]    In the charge transfer phase, the output terminal of operational amplifier  305  is connected to node N 2  through capacitor C 1 , and node N 2  is connected to reference voltage GND through capacitor C 2 . In this case, negative feedback works so that the voltage at node N 2  will be approximately equal to reference voltage GND, so the voltage at capacitor C 2  will be approximately zero, and all the charge accumulated in capacitor C 2  is transferred to capacitor C 1 . 
         [0251]    In this embodiment, too, the same as the embodiments already explained, a charge signal that is proportional to the number of repetitions of the signal accumulation operations is integrated in capacitor C 2 , and amplified results are obtained based on the signal charge, so the same effects as with the embodiments already described, such as being able to limit an increase in power consumption and circuit surface area, can be accomplished. 
         [0252]    In addition, by returning the signal charge accumulated in capacitor C 2  to capacitor C 1 , amplification effects that are not dependent on the electrostatic capacitance of capacitors C 1  and C 2  can be obtained, so gain setting precision can be improved the same way as in the embodiments described above. 
         [0253]    Next, a fifth embodiment of the present invention will be explained. 
         [0254]    With the imaging device pertaining to the fifth embodiment, read circuit  32 C in the imaging device pertaining to the fourth embodiment ( FIG. 18 ) is replaced with read circuit  32 D with an even simpler configuration ( FIG. 24 ). 
         [0255]    With read circuit  32 D shown in  FIG. 24 , switch circuits SW 5  and SW 10  in read circuit  32 C shown in  FIG. 18  are omitted. The locations of switch circuits SW 5  and SW 10  are open. Otherwise, the configuration of read circuit  32 D is the same as read circuit  32 C. 
         [0256]    With read circuit  32 C shown in  FIG. 24 , amplification processing is performed in the order initial phase and integration phase. The discharge phase and the charge transfer phase are omitted. Switch circuit state in each phase in read circuit  32 D is the same as read circuit  32 C shown in  FIG. 18 . 
         [0257]    In this embodiment, too, the same as in the embodiments already explained, a signal charge that is proportional to the number of repetitions of the signal accumulation operations is integrated in capacitor C 2 , and amplification results are obtained based on the signal charge, so the same effects as the embodiments already described, such as being able to limit an increase in power consumption and circuit surface area, can be accomplished. 
         [0258]    Next, a sixth embodiment will be explained. 
         [0259]    With the imaging device pertaining to the sixth embodiment, serial conversion circuit  33  in the imaging device pertaining to the first embodiment ( FIG. 6 ) is replaced with a serial conversion circuit  33 A provided with two lines worth of memory ( FIG. 25 ). 
         [0260]    Serial conversion circuit  33 A shown in  FIG. 25 , in addition to the same configuration as serial conversion circuit  33  shown in  FIG. 6 , additionally has capacitors CMA 1  to CMAj, and switch circuits SE 1  to SEj, SF 1  to SFj, SG 1  to SGj and SH 1  to SHj. 
         [0261]    Capacitor CMAk (k=1-j) holds pixel signal Ps output from read circuit  32 - k . One terminal of capacitor CMAk is connected to the output of read circuit  32 - k  through switch circuit SEk, and is also connected to the output of operational amplifier  306  through switch circuit SGk. The other terminal of capacitor CMAk is connected to reference voltage GND through switch circuit SFk, and is also connected to the negative input terminal of operational amplifier  306  through switch circuit SHk. 
         [0262]    Capacitors CM 1  to CMj and capacitors CMA 1  to CMAj each constitute a memory that holds one line worth of pixel signals Ps. When pixel signals Ps for on line are input in parallel to one memory, pixel signals for the perceiving line are output serially from the other memory. 
         [0263]    For example, in the period in which pixel signals Ps for a certain line are output from read circuits  32 - 1  to  32 - j , switch circuits SA 1  to SAj and SB 1  to SBj are all ON, and switch circuits SC 1  to SCj and SD 1  to SDj are all OFF, so that pixel signals Ps are input from read circuits  32 - 1  to  32 - j  to capacitors CM 1  to CMj. On the other hand, in this period, switch circuits SE 1  to SEj and SF 1  to SFj are all OFF, and switch circuits SG 1  to SGj and SH 1  to SHj come ON successively, so that pixel signals Ps for the previous line held in capacitors CMA 1  to CMAj are output serially from operational amplifier  306 . 
         [0264]    The period for the one line ends, and in the period in which the next line of pixel signals Ps is output from read circuits  32 - 1  to  32 - j , by switch circuits SE 1  to SEj and SF 1  to SFj all being ON, and switch circuits SG 1  to SGj and SH 1  to SHj all being OFF, the opposite of the, pixel signals Ps are input to capacitors CMA 1  to CMAj from read circuits  32 - 1  to  32 - j . In this period, by switch circuits SA 1  to SAj and SB 1  to SBj all being OFF, and by switch circuits SC 1  to SCj and SD 1  to SDj successively coming ON, the previous line of pixel signals Ps held in capacitors CM 1  to CMj are output serially from operational amplifier  306 . 
         [0265]    With this embodiment, while one line of pixel signals Ps in read circuits  32 - 1  to  32 - j  is being input to one memory, the pixel signals Ps can be output serially from the other memory. An entire one line period can be assigned to amplification processing by read circuits  32 - 1  to  32 - j  by this, so amplification processing can be accomplished with a margin, even when the number of repetitions in the integration phase becomes large, and high gain can be achieved. 
         [0266]    In addition, because margin occurs in the amplification processing period, it is possible to make the electrostatic capacitance of capacitors C 1  and C 2  relatively large. By so doing, even when capacitor charge changes due to phenomena such as clock feed-through accompanying individual switch circuits being turned ON and OFF, voltage error produced by the change will be relatively small, so pixel signals can be amplified more precisely. 
         [0267]    Several embodiments of the present invention were explained above, but the present invention is not limited to only the abovementioned embodiments and includes many variations. 
         [0268]    With the abovementioned embodiments, the first signal accumulation operation is performed simultaneously in the initial phase ( FIG. 7 ), but the first signal accumulation operation could also be performed following the initial phase. 
         [0269]    With the abovementioned second embodiment, the capacitance of capacitor C 1  is variable, and capacitor C 2  is fixed ( FIG. 13 ), but the present invention is not limited to this. For example, the capacitance of capacitor C 2  could be variable, and the capacitance of capacitor C 1  could be fixed. Alternatively, the capacitance of both capacitors could also be variable. 
         [0270]    With the abovementioned embodiments, discharge by capacitor C 2  in the initial phase ( FIG. 7 ) and discharge by capacitor C 1  in the discharge phase ( FIG. 10 ) are performed with switch circuits used in separate phases, but the present invention is not limited to this. For example, discharge could also be performed with specialized switch circuits connected in parallel with the capacitors. It is also not necessary to bring the charge to zero with the discharge, and the capacitors could be discharged to a fixed charge that is not zero. 
         [0271]    In the first charge accumulation operation ( FIG. 9 ) and the discharge phase ( FIG. 10 ), the charge of capacitor C 2  is held in a feedback loop, but the present invention is not limited to this. For example, the charge could also be held with at least one terminal of capacitor C 2  opened. 
         [0272]    In the abovementioned embodiments, analog-digital conversion is performed in a stage after serial conversion circuit  33 , but the present invention is not limited to this. 
         [0273]    For example, an analog-digital conversion circuit could also be provided in a stage after each read circuit. 
         [0274]    The imaging device of the present invention could also be configured with one semiconductor chip, or it could be configured with multiple semiconductor chips. 
         [0275]    With the abovementioned embodiments, examples in which the amplifying circuit of the present invention is applied to an imaging device were shown, but the amplifying circuit of the present invention is not limited to this. That is, the amplifying circuit of the present invention can be applied broadly to any device that amplifies the difference between two signals.