Abstract:
The present invention provides a compilation system for compiling and linking an integrated executable adapted to execute on a heterogeneous parallel processor architecture. The compiler and linker compile different segments of the source code for a first and second processor architecture, and generate appropriate stub functions directed at loading code and data to remote nodes so as to cause them to perform operations described by the transmitted code on the data. The compiler and linker generate stub objects to represent remote execution capability, and stub objects encapsulate the transfers necessary to execute code in such environment.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application relates to co-pending U.S. patent applications entitled “METHOD AND APPARATUS FOR SETTING BREAKPOINTS WHEN DEBUGGING INTEGRATED EXECUTABLES IN A HETEROGENEOUS ARCHITECTURE” (Docket No. AUS920020454US1), “METHOD AND APPARATUS FOR OVERLAY MANAGEMENT WITHIN AN INTEGRATED EXECUTABLE FOR A HETEROGENEOUS ARCHITECTURE” (Docket No. AUS920020455US1), “METHOD AND APPARATUS FOR ENABLING ACCESS TO GLOBAL DATA BY A PLURALITY OF CODES IN AN INTEGRATED EXECUTABLE FOR A HETEROGENEOUS ARCHITECTURE” (Docket No. AUS920020456US1); and “METHOD AND APPARATUS FOR MAPPING DEBUGGING INFORMATION WHEN DEBUGGING INTEGRATED EXECUTABLES IN A HETEROGENEOUS ARCHITECTURE” (Docket No. AUS920020457US1), filed concurrently herewith and having the same inventors, Michael Karl Gschwind, Kathryn O&#39;Brien, John Kevin O&#39;Brien, and Valentina Salapura 
     
    
     
       TECHNICAL FIELD  
         [0002]    The invention relates generally to multiprocessing and, more particularly, to the standardization of the passing of information between a plurality of processors.  
         BACKGROUND  
         [0003]    Parallel processing, which generally comprises employing a plurality of microprocessors coupled to the same computer system to concurrently process a batch of data, is of great importance in the computer industry. Generally, there are three major types of parallel processing. These are parallel processing systems employing shared memory or distributed memory or a combination of the two. Typically, shared memory is memory that can be accessed in a single operation, such as a “load” or “read” command, by a plurality of processors. Distributed memory is memory that is localized to an individual processor. In other words, in a distributed system, each processor can access its own associated memory in single access operation, but typically cannot access memory associated with the other processors in a single operation. Finally, there is a hybrid, or “heterogeneous,” parallel processing, in which there is some system memory accessible by one or more processors, and some memory which is distributed and local to at least one processor.  
           [0004]    One such example of a hybrid parallel processor system comprises at least one reduced instruction set (RISC) main processor unit (MPU), such as a PowerPC™ processor, and at least one specialized or “attached” processor unit (APU), such as a Synergistic™ APU (SPU). Typically, the MPU is employed to execute general purpose code, wherein the general purpose code comprises complex control flows and orchestrating the overall hybrid parallel processing function. The MPU has access to the full range of system memory. The APU is generally directed to executing dataflow operations. In other words, the APU calculates highly repetitive multimedia, graphics, signal. or network processing workloads which are identified by high compute to control decision ratios. In conventional hybrid systems, APUs do not have access to the system memory, and their own memory, the local store, is typically smaller than the shared memory.  
           [0005]    Generally, while employment of the hybrid system provides high computational performance, it poses significant challenges to the programming model. One such problem relates to the APU. The APU cannot directly address system memory. Therefore, any code to be run on the APU has to be transferred to an associated local storage of the APU before this code can be executed on the APU. Furthermore, the APU and the MPU can have different instruction sets.  
           [0006]    However, in the program design process, conventional compilers generally do not assign information sequences, such as specific code sequences or data, to be run on a PU or an APU in a hybrid system. Instead, programmers determine how to allot code functionality to the APU or the MPU. This allotment of code to a processor typically entails inefficiencies in the programming process. Furthermore, there is no standard programming “tool box” for passing information, be it text (that is, code) or data, between the attached processor and the main processor. Therefore, programmers typically have no standard format for passing this information sequences, thereby also creating inefficiencies in the programming process.  
           [0007]    Therefore, what is required is a programming environment that allows for systematized programming of an MPU and an APU, and the transference of code and data between the MPU and the APU, that overcomes the deficiencies of conventional systems.  
         SUMMARY  
         [0008]    The present invention provides for compiling and using code for employment in a distributed computing system. The code is partitioned into a plurality of modules, wherein the modules comprise at least one main processor code module and at least one attached processor code module. Code is selected to be encapsulated within at least one main processor code module, wherein the selected code is targeted for employment by at least one attached processor. At least one main processor code module and at least one selected attached processor code module are compiled. A stub function is generated from the selected at least one attached processor module. The compiled processor code targeted for the main processing module is linked to the at least one stub function. A linked object integrated executable program is created. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following Detailed Description taken in conjunction with the accompanying drawings, in which:  
         [0010]    [0010]FIG. 1 schematically depicts a distributed processing system environment for executing integrated executables comprising stub functions;  
         [0011]    [0011]FIG. 2 illustrates a method for compiling and using code destined for a plurality of execution environments in the distributed computing system;  
         [0012]    [0012]FIG. 3A depicts “C” programming language pseudo-code for a stub function that is employable to transfer data from the MPU to the APU; and  
         [0013]    [0013]FIG. 3B depicts “C++” programming language pseudo-code for a stub function that is employable to transfer data from the MPU to the APU. 
     
    
     DETAILED DESCRIPTION  
       [0014]    In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning network communications, electro-magnetic signaling techniques, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the understanding of persons of ordinary skill in the relevant art.  
         [0015]    It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor, such as a computer or an electronic data processor, in accordance with code, such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.  
         [0016]    Referring to FIG. 1, the reference numeral  100  generally designates heterogeneous parallel processing architecture that provides an environment for the passing of information by employment of a stub function. The architecture  100  comprises distributed computing environment  110  and a shared system memory  160 , both of which are electrically coupled by an interface  150 . The environment  110  comprises a plurality of APUs  120 , each with its respective local store  125 . The environment  110  further comprises an MPU  130 , such as a RISC processor, and its level one cache  135 . In one embodiment, the MPU  130  is coupled to the system memory  160  through a signal path  145 . In one embodiment, the APU comprises an SPU. In one embodiment, a single MPU  130  is employed. In a further embodiment, a plurality of MPUs  130  are employed.  
         [0017]    The environment  110  further comprises a memory flow controller (MFC)  140 . Generally, the MFC  140  enables the movement of data and synchronization capability between the MPU  130  and the APU  120  processors, and provides for data transfer between the main system memory  160  and local storage  125 . In FIG. 1, the MFC  140  is coupled to the system memory  160  through the interface  150 .  
         [0018]    Generally, the MFC  140  enables the movement of information, both text (that is, code) and data, between the system memory  160  and the local store  125  of the APU  120 , at the request of the main processor  130  or the APU  120 . Because the APU  120  does not have direct access to the system memory  160 , the MFC  140  transfers information between the system memory  160  and the local store  125  of the APU  120 , at the request of a transfer function, such as stub function, running on either the APU  120  or the MPU  130 . In one embodiment, the MFC  140  comprises a direct memory access (DMA) device.  
         [0019]    The architecture  100  is an environment in which an executable program runs, wherein the executable program has a stub function or stub functions embedded within it. In the stub function, code and data to be employed by the APU  120  is encapsulated as a software “object.” Generally, the stub function commands the MFC  140  to transfer information between two separate execution environments, such as the system memory  160  and the local store  125 . The stub function enables the MPU  130  to stream code and data to the local store  125  of the APU  120  for processing, for the APU  120  to perform the processing, and for the APU  120  to then stream the processed data back to the MPU  130 . This processing of the data and code performed by the APU  120  is invisible to the MPU  130 , and allows the MPU  130  to concurrently perform other data processing or program flow control tasks concurrently.  
         [0020]    Typically, the stub function commands the MFC  140  to stream both code and data to a designated address within the local store  125  of a selected APU  120  from the designated addresses in the system memory  160 . The stub function also commands the MFC  140  to command the APU  120  to process the data. The command issued from the stub function to the APU  120  are remote commands. Generally, remote commands are commands that are sent from a first execution environment to a second execution environment. Typically, the stub function is the single entry point to the APU  120 . In other words, the APU  120 , or its associated local store  125 , is typically only accessible through the stub function.  
         [0021]    In a further embodiment, the streamed code also contains within it yet another stub function. This streamed stub function enables the APU  120  to command the MFC  140  to send processed data back to the shared memory  160  when the APU  120  has finished data processing. In this embodiment, a stub function in the MPU  130  polls the APU  125  to determine whether the APU  120  is finished processing. If the APU  120  is finished processing, then the stub function executed by the MPU  130  commands the MFC  140  to send the processed data back to the system memory  160 . In yet another embodiment, all stub functions are executed by the MPU  130 , as all stub functions reside in the system memory  160 . However, not all MFC commands need necessarily be associated with stub functions.  
         [0022]    Turning now to FIG. 2, illustrated is a method  200  for compiling and using code, thereby creating an integrated executable with embedded stub functions. In step  210 , source code is partitioned into modules to be run on both the APU  120  or APUs  120  and the MPU  130 , thereby creating an APU  120  code module and an MPU  130  code module. The partitioning can be performed either by a compiler or through the intervention of a human programmer, or a combination of both approaches. The partitioning can be based upon such considerations as type of data manipulations required, repetitiveness of the data manipulation, and so on. Examples of modules to be run on the selected APU  120  are trigonometric functions, matrix manipulations, square root calculations, and so on.  
         [0023]    In step  220 , the compiler (or programmer) selects at least one separate APU  120  code module that is to be encapsulated within the MPU  130  code module or code modules. In step  230 , the partitioned modules, written in a programming language are compiled by a compiler. Some examples are programming languages are “C,” “C++” or “Assembler,” although other programming languages are within the scope of the present invention. This compilation produces a plurality of object code modules tailored for execution in one or more of the separate processing architectures, such as the local store  125  of the APU  120  and the system memory  160  coupled to the MPU  140  ,or a plurality of MPUs  140 .  
         [0024]    A compiled object code module destined for one or more APUs  120  or one or more MPUs  130  can be the result of the combination of code or data originating from several different source files. Also, more than one object code section can include the same code or data. Generally, step  230  combines into one contiguous area all the code or data can be loaded in one operation into the corresponding local store  125  of the selected APU  120 . Furthermore, step  230  combines any files to be compiled into an object module for the MPU  130 .  
         [0025]    In step  240 , the linker generates a stub function by encapsulating the at least one compiled module selected in step  220  as a stub function, wherein the stub function further comprises the means to transfer the code and data between the APU  120  and the MPU  130 . The stub function comprises an “object,” wherein both the code, the data, and the means for accessing the code and data are contained within the stub function. The means for streaming the data between the MPU  130  and the targeted APU  120  typically comprises commands to the MFC  140 .  
         [0026]    In step  250 , the linker binds the at least one module destined for the APU  120 , which has been encapsulated as a stub function within the module to be executed on the MPU  130  to any other compiled modules destined for the APU  120  or APUs  120 . The linker binds the linked APU  120  compiled modules to the compiled module destined for the MPU  130 . In one embodiment, the linker first links all the modules targeted to attached processors  120 , then further links these linked modules to the module targeted for the MPU  130 .  
         [0027]    Turning now to FIG. 3A, disclosed is pseudo-code in the “C” programming language for stub routine for transmitting information from the system memory  160  to the local store  125 . The stub routine includes header file “apu_xfer.h” which represent the interface specifications of system-level operations necessary to effect MFC operations, such as moving a block of data, initiating execution, and so forth.  
         [0028]    Generally, the stub function comprises a software “object” which further comprises embedded code and data to be streamed into the APU  120 , along with the software means to transfer the code and data to the APU  120  from the system memory  160 . In FIG. 3A, this code and data are the apu_text[] and the apu_data[] arrays, respectively. Furthermore, in FIG. 3A, the stub function comprises two subfunctions. These are the “apu_transfer_block( ) subfunction and the apu_start_exec( ) subfunction invocations referring to system-level operations defined by the header file “apu_xfer.h” in this exemplary embodiment.  
         [0029]    Generally, the “apu_transfer_block( ) subfunction commands the MFC  140  to send information, such as code and data, to a selected APU  120 . The apu_transfer_block( ) subfunction comprises four fields of information within its header. In FIG. 3A, the first field of information, “apuno,” is the indicia of the APU  120  to which the text and data is to be streamed. The second field of information comprises the memory address within the local store  125  of the APU  120  in which the information is to be stored. In FIG. 3A, this exemplary value is “116” for the first apu_transfer_block( ) subfunction, “32768” for the second apu_transfer_block( ) subfunction. The third field comprises indicia, to the text or data that is to be sent. In FIG. 3A this is apu_text[] and apu_data[], respectively. Finally, the length of the information is sent in the fourth field. These exemplary values are “172” for the apu_text and “16” for the apu_data fields respectively.  
         [0030]    The stub function of FIG. 3A further comprises a subfunction to start the selected APU  120  processing data. This subfunction, “apu_start_exec( ),” comprises two fields. The first field is indicia of the selected APU  120  upon which the processing is to initiate. The second field is the address of the text or executable code in the local store  125  of the selected processor  120 . The address of the text of the executable code conveys to the selected APU  120  where to look in memory to start executing the streamed code.  
         [0031]    Turning briefly to FIG. 4B, illustrated is a “C++” code class which can be used as a base class to derive stubs for different modules providing common member functions to load, transfer parameters, initiate execution, and retrieve results. In one exemplary embodiment, there is defined a public class function, that has a virtual int spu_load( ) subfunction, a virtual int spu_load_data( ) subfunction, and a virtual int spu_load_text( ) subfunction. In one embodiment, the spu_load( ) performs the functions of the spu_load_data( ) subfunction and the spu_load_text( ) subfunction. There is also virtual spu_xfer_parm ( ).  
         [0032]    In this exemplary embodiment, parameters are represented by a user-defined type parm_descriptor which has been adequately defined to accommodate different sets of parameters which might be passed to a stub. In other embodiments, parameters can be passed using different conventions such as by the use of the C/C++ “stdarg” facility. As is understood by those of skill in the art, “stdarg” is a part of the C language standard which deal with passing a variable invocation-defined parameters {both variable in number and data type(s)} to a function. In yet another embodiment, each derived subclass from the base class apu_root_function may have its own invocation member function which also provide the parameters. Such function may then either directly effect the transfer of the parameters to the selected APU, or invoke a member function such as spu_xfer_parm( ), or other functions to copy one or more data items to a local APU memory. There is also a sub function, virtual int spu_start( ), to start the APU  120  processing the data, and another subfunction, virtual int spu_retrieve( ) subfunction, to fetch the processed data from the APU  120 .  
         [0033]    It is understood that the present invention can take many forms and embodiments. Accordingly, several variations may be made in the foregoing without departing from the spirit or the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying mechanisms on which these programming models can be built.  
         [0034]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered obvious and desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.