Abstract:
A charge pump type booster circuit generates a positive or negative boosted output voltage by switching booster paths one by one. This charge pump type booster circuit includes a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor, wherein a number of the booster capacitor at each of the plurality of booster paths is different between one booster path and the other booster path. This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a booster circuit. More particularly, this invention relates to a charge pump type booster circuit. 
     2. Description of Related Art 
     Generally, a booster circuit is required to keep an output voltage constant. However, in a charge pump type booster circuit, the output voltage drops in a relatively short period of time when a value of a current flowing to a load becomes larger. Note that the load is connected to the booster circuit in general. 
     A related technique disclosed in a Japanese Unexamined Patent Application Publication No. 8-149802 is shown in  FIG. 9 . As shown in  FIG. 9 , a booster circuit  100  has two booster units  110 ,  120 . Control signals A and B are input to the booster unit  110 . The control signals A and B are input to the booster unit  120  after inverted by buffers, which are connected to input terminals of the booster unit  120 . A capacitor C 100  is charged by the booster unit  120  when the control signal A is high (H) and the control signal B is low (L). The capacitor C 100  is charged by the booster unit  110  when the control signal A is low (L) and the control signal B is high (H). That is, the capacitor C 100  is charged by the booster unit  110  and the booster unit  120  alternately along with the time axis. 
     It is common in the charge pump type booster circuit to use external capacitor parts, which are provided separately from an IC (Integrated Circuit) chip including the charge pump type booster circuit. Because the charge pump type booster circuit requires a large capacitance value, it is often not enough for an integrated capacitor to satisfy the required capacitance value. 
     In this case, an increase in a number of the capacitors results in an increase of manufacturing cost of the circuit. When a plurality of booster units as shown in  FIG. 9  are used so as to suppress ripples of the output voltage, manufacturing cost of the circuit raises accordingly and it becomes difficult to suppress the cost up of the circuit. 
     As explained above, it was difficult to suppress a total number of external capacitors so as to keep the output voltage constant. 
     SUMMARY 
     In one embodiment, a charge pump type booster circuit generates a positive or negative boosted output voltage by switching booster paths one by one. This charge pump type booster circuit includes a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor, in which a number of the booster capacitor at each of the plurality of booster paths is different between one booster path and the other booster path. 
     This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant. 
     In still another embodiment, a booster circuit includes a first output path boosting an input voltage N (N is a positive or negative integer having an absolute value two or more) times; and a second output path boosting the input voltage N times; in which the booster circuit outputs a first boosted voltage output from the first output path and a second boosted voltage output from the second output path alternately based on a control signal transmitted from a control circuit, and in which the second boosted voltage is set based on a boosted voltage gained by boosting the input voltage M (M is a positive or negative integer having an absolute value smaller than that of N) times when the first output voltage is output from the booster circuit. 
     The output voltage is set based on the boosted voltage. This boosted voltage is gained by boosting the input voltage M times. This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant. 
     In still another embodiment, a charge pump type booster circuit generates a positive or negative boosted output voltage. The charge pump type booster circuit includes a first booster path connected between an input terminal and an output terminal to output the positive or negative boosted output voltage gained by boosting an input voltage through N (N is a positive integer of two or more) capacitors; and a second booster path connected between the input terminal and the output terminal to output the positive or negative boosted output voltage gained by boosting the input voltage through M (M is a positive integer of less than N) capacitor. This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a schematic circuit diagram of a booster circuit according to a first embodiment of the present invention; 
         FIG. 2  is a schematic view for explaining a configuration of a control circuit; 
         FIG. 3  is a schematic circuit diagram of the booster circuit in a first condition; 
         FIG. 4  is a schematic circuit diagram of the booster circuit in a second condition; 
         FIG. 5  is a timing chart for explaining a function of the booster circuit; 
         FIG. 6  is a reference view for explaining a configuration of the booster circuit in the first condition; 
         FIG. 7  is a reference view for explaining a configuration of the booster circuit in the second condition; 
         FIG. 8  is a schematic circuit diagram of a booster circuit according to a second embodiment of the present invention; 
         FIG. 9  is a schematic view of a related booster circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
     First Embodiment 
       FIG. 1  shows a schematic circuit diagram of a booster circuit  1  according to the first embodiment of the present invention. A control circuit  2  is also shown in  FIG. 1  which controls switches SW 1 -SW 11  ON or OFF. The switches SW 1 -SW 11  are included in the booster circuit  1 . 
     First, connection relations of circuit elements included in the booster circuit  1  is explained. 
     As shown in  FIG. 1 , the booster circuit  1  includes an input terminal Pin, an output terminal Pout, switches SW 1 -SW 11 , and capacitors C 1 -C 3 . 
     The input terminal Pin is connected to a power supply E 1 . The output terminal Pout is connected to a smoothing capacitor Col. An input voltage is supplied from the power supply E 1  to the booster circuit  1  via the input terminal Pin. The smoothing capacitor Col is charged by an output voltage output from the booster circuit  1  via the output terminal Pout. The output voltage is a voltage gained by boosting the input voltage by the booster circuit  1 . 
     A first end of the capacitor C 1  is connected to the power supply E 1  via the switch SW 1  and the input terminal Pin. The first end of the capacitor C 1  may be set to a power supply potential VDD (a first power supply potential). Note that the first end of the capacitor C 1  is connected to a second end of the capacitor C 3  via the switch SW 8  (a second switch unit) and the switch SW 10  (a sixth switch unit). 
     A second end of the capacitor C 1  is connected to ground via the switch SW 2 . And the second end of the capacitor C 1  may be set to a ground potential GND (a second power supply potential). Note that the second end of the capacitor C 1  is connected to the power supply E 1  via the switch SW 7  (a first switch unit) and the input terminal Pin. The second end of the capacitor C 1  may be set to a power supply potential VDD. 
     A first end of the capacitor C 3  is connected to the power supply E 1  via the switch SW 3  and the input terminal Pin. The first end of the capacitor C 3  may be set to a power supply potential VDD. The first end of the capacitor C 3  is also connected to an end of the smoothing capacitor Col via the switch SW 11  and the output terminal Pout. A second end of the capacitor C 3  is connected to the first end of the capacitor C 1  via the switches SW 10  and SW 8 . 
     A first end of the capacitor C 2  (a second boosting capacitor) is connected to the first end of the capacitor C 1  via the switch SW 8 . The first end of the capacitor C 2  is connected to the end of the smoothing capacitor Col via the switch SW 6  (a fifth switch unit) and the output terminal Pout. Note that the first end of the capacitor C 2  is connected to a node N 1  between the switch SW 8  and the switch SW 10 . 
     A second end of the capacitor C 2  is connected to ground via the switch SW 9  (switch unit). The second end of the capacitor C 2  may be set to a ground potential GND. The second end of the capacitor C 2  is connected to the power supply E 1  via the switch SW 5  (a forth switch unit) and the input terminal Pin. The second end of the capacitor C 2  may be set to a power supply potential VDD. 
     The switches SW 1 -SW 11  included in the booster circuit  1  becomes ON (conductive) or OFF (non-conductive) based on control signals from the control circuit  2 . 
     Now, a configuration of the control circuit  2  is shown in  FIG. 2 . As shown in  FIG. 2 , the control circuit  2  includes an oscillator  10 , a level shift unit  11 , and an inverting buffer  12 . The level shift unit  11  includes a first buffer  13  and a second buffer  14 . 
     The oscillator  10  outputs a clock signal (CLK) having a predetermined cycle. This clock signal is input to the first buffer  13  included in the level shift unit  11 . This clock signal is also input to the second buffer  14  after inverted by the inverting buffer  12 . 
     With such a configuration, the control circuit  2  outputs a first control signal output from the first buffer  13  and a second control signal output from the second buffer  14 . When the first control signal is HIGH, the second control signal is LOW. When the first control signal is LOW, the second control signal is HIGH. The first control signal is input to the switches SW 1 -SW 6 . The second control signal is input to the switches SW 7 -SW 11 . 
     With a reference to  FIG. 3 , the booster circuit  1  in a first condition is explained. The booster circuit  1  is to be in the first condition based on the first and second control signals transmitted from the control circuit  2 . Note that all the switches SW 1 -SW 6  are in an OFF-state and all the switches SW 7 -SW 11  are in an ON-state when the booster circuit  1  is in the first condition. 
     As shown in  FIG. 3 , a first switch group including switches SW 7 -SW 11  is in an ON-state when the booster circuit  1  is in the first condition. Note that the first switch group includes all the switches SW 7 -SW 11  included in a latter mentioned first booster path. 
     When the first switch group is in an ON-state, the first booster path is generated between the input terminal Pin and the output terminal Pout. This first booster path includes the first switch group on its path. The first booster path boosts the input voltage (VDD) input from the power supply E 1  via the input terminal Pin three times, and outputs the tripled voltage (3VDD) as an output voltage (a first output voltage). 
     This output voltage is input to the smoothing capacitor Col via the output terminal Pout. Note that the second end of the capacitor C 1  included in the first booster path is connected to the input terminal Pin. The first end of the capacitor C 1  is connected to the capacitor C 3 . The second end of the capacitor C 3  included in the first booster path is connected to the first end of the capacitor C 1 . The first end of the capacitor C 3  is connected to the smoothing capacitor Col via the output terminal Pout. The capacitor C 1  and the capacitor C 3  are connected in series between the input terminal Pin and the output terminal Pout. 
     In this embodiment, when the booster circuit  1  is in the first condition, the first end of the second capacitor C 2  is connected to the first end of the capacitor C 1  and the second end of the capacitor C 2  is connected to the ground. Note that the switch SW 8  and the switch SW 9  are both in an ON-state. 
     The capacitor C 2  is charged based on the boosted voltage (2VDD), which is generated by the capacitor C 1 , when the booster circuit  1  is in the first condition. In other words, the capacitor C 2  is charged by the boosted voltage (2VDD) that is generated by the capacitor C 1 . 
     The boosted voltage is a voltage gained by boosting the input voltage (VDD) two times and is smaller than the output voltage that is boosted by boosting the input voltage (VDD) three times. The multiple for the boosted voltage is smaller than the multiple for the output voltage. 
     Note that the capacitor C 2  is in a state of being charged. This makes it possible to set the output voltage 3VDD when the booster circuit  1  changes from the first condition to a second condition. 
     When the booster circuit  1  is in the first condition, the switches SW 1  (switch unit) and SW 2  (switch unit) for charging, the capacitor C 1  are both in an OFF-state. And the switches SW 3  and SW 4  for charging the capacitor C 3  are both in an OFF-state. And both of the switches SW 6  between the first end of the capacitor C 2  and the output terminal Pout and SW 5  between the second end of the capacitor C 2  and the input terminal Pin are in an OFF-state. 
     Next, with a reference to  FIG. 4 , the booster circuit  1  in the second condition is explained. The booster circuit  1  is to be in the second condition based on the first and second control signals output from the control circuit  2 . Note that all the switches SW 1 -SW 6  are in an ON-state and all the switches SW 7 -SW 11  are in an OFF-state when the booster circuit  1  is in the second condition. 
     The booster circuit  1  changes to the first condition or the second condition alternately at a predetermined time interval so as to set the output voltage within a predetermined voltage range. 
     As shown in  FIG. 4 , a second switch group including switches SW 5  and SW 6  is in an ON-state when the booster circuit  1  is in the second condition. Note that the second switch group includes the switches SW 5  and SW 6  included in the second booster path. 
     When the second switch group is in an ON-state, the second booster path is generated between the input terminal Pin and the output terminal Pout. This second booster path includes the second switch group on its path. The second booster path boosts the input voltage (VDD) input from the power supply E 1  via the input terminal Pin three times, and outputs the tripled voltage (3VDD) as the output voltage (a second output voltage). 
     This output voltage is input to the smoothing capacitor Col via the output terminal Pout. Note that the first end of the capacitor C 2  included in the second booster path is connected to the output terminal Pout and the second end of the capacitor C 2  is connected to the input terminal Pin. 
     In this embodiment, when the booster circuit  1  is in the first condition, the first end of the second capacitor C 2  is set at a potential level 2VDD (a level of the boosted voltage). Therefore, it is possible to set the first end of the capacitor C 2  at a potential level 3VDD by changing the condition of the booster circuit  1  from the first condition to the second condition. In other words, it is possible to set the first end of the capacitor C 2  at a potential level 3VDD by connecting the second end of the capacitor C 2  with the power supply E 1  via the switch SW 5  and the input terminal Pin, and setting the second terminal of the capacitor C 2  at a potential level VDD. 
     In this way, the input voltage VDD is boosted by three times. And the second booster path outputs the tripled voltage 3VDD as the output voltage. Note that the input voltage input to the second terminal of the capacitor C 2  is a voltage to be boosted. 
     When the booster circuit  1  is in the second condition, both of the switches SW 1  and SW 2  are in an ON-state and the capacitor C 1  is in a state of being charged. Both of the switches SW 3  and SW 4  are in an ON-state and the capacitor C 3  is in a state of being charged. The capacitors C 1  and C 3  are connected to the input terminal Pin in parallel and charged by the input voltage VDD supplied from the power supply E 1 . 
     Using now a timing chart of  FIG. 5 , an operation of the booster circuit  1  is further explained with reference to  FIGS. 6 and 7 . 
     As shown in  FIG. 5 , during a period t 1  to t 2 , the clock signal CLK output from the oscillator  10  is HIGH and the booster circuit  1  is in the second condition. At this time, the capacitor C 1  is in a state of being charged. Therefore, the first end of the capacitor C 1  is set to a power supply potential VDD. The first end of the capacitor C 3  is also set to a power supply potential VDD. 
     As shown in  FIG. 5 , during a period t 2  to t 3 , the clock signal CLK output from the oscillator  10  is LOW, and the booster circuit  1  is in the first condition. At this time, as shown in  FIG. 6 , the power supply E 1 , the input terminal Pin, the capacitor C 1 , the capacitor C 3 , and the output terminal Pout are connected in series in this order. 
     When the booster circuit  1  changes from the second condition to the first condition, the second end of the capacitor C 1  is set to a potential level VDD. More specifically, a potential level of the second end of the capacitor C 1  rises from a potential level GND to a potential level VDD. And a potential level of the first end of the capacitor C 1  rises from a potential level VDD to a potential level 2VDD. 
     A potential level of the second end of the capacitor C 3  rises from a potential level GND to a potential level 2VDD in accordance with a rise in potential level of the first end of the capacitor C 1 . And the output voltage output from the booster circuit  1  is set to 3VDD that is three times higher than the input voltage VDD. 
     As shown in  FIG. 6 , a potential level of the first end of the capacitor C 1  and a potential level of the first end of the capacitor C 2  are set to be the same when the booster circuit  1  is in the first condition. Therefore, a potential level of the first end of the capacitor C 2  is set to a potential level 2VDD at the same time when a potential level of the first end of the capacitor C 1  is set to a potential level 2VDD. A potential level of the first end of the capacitor C 2  is set in this way, and the output voltage is to be set 3VDD when the booster circuit  1  changes from the first condition to the second condition. 
     As shown in  FIG. 5 , during a period t 3  to t 4 , the clock signal CLK output from the oscillator  10  is HIGH, and the booster circuit  1  changes from the first condition to the second condition. At this time, as shown in  FIG. 7 , the power supply E 1 , the input terminal Pin, the capacitor C 2 , and the output terminal Pout are connected in series in this order. 
     When the booster circuit  1  changes from the first condition to the second condition, a potential level of the second end of the capacitor C 2  rises from a ground potential GND to the power supply potential VDD. At this time, a potential of the first end of the capacitor C 2  raises from a potential level 2VDD to a potential level 3VDD. And the output voltage is set to 3VDD which is three times higher than the magnitude of the input voltage. 
     In the first condition, a potential level of the first end of the capacitor C 2  is set to a potential level 2VDD. Then, in the second condition, a potential level of the second end of the capacitor C 2  is set to a potential level VDD. In this way, it is possible to gain output voltage three times higher than the input voltage without increasing a number of capacitor. As described above, a number of capacitors included in the second booster path is less than a number of capacitors included in the first booster path. 
     An operation of the booster circuit  1  during a period t 4  to t 5  is the same with that of t 2  to t 3 . Therefore, overlapping explanation is omitted. 
     The booster circuit  1  can be used in a various applications. Especially when it is used in a driver circuit for a liquid crystal display, a property of high withstand voltage is required for the booster circuit  1 , because a drive voltage applied to a liquid crystal cell is high. Therefore, it is required to configure at least switch SW 6  and SW 1  which are included in the booster circuit  1  using elements having a high withstand voltage. Note that the elements having a high withstand voltage has a higher withstand voltage compared with the elements having a low withstand voltage. 
     Generally, an element having high withstand voltage requires a larger circuit space than that required for an element having low withstand voltage. In addition to this, on-resistance of the element having a high withstand voltage is higher than that of the element having a low withstand voltage. Therefore, it is required to increase amplitude of a voltage of a control signal, thereby causing an increase in power consumption. Note that the control signal is to be transmitted from the control circuit  2  to the switch element of the booster circuit  1 . 
     If a booster circuit is configured with such a simple circuit configuration of this embodiment, it is possible to suppress an increase in the number of element having a high withstand voltage. Moreover, it makes it possible to lower amplitude of the voltage of the control signal. 
     Note that in this embodiment, the switch SW 11  at a side of the output terminal included in the first booster path is configured with an element having a higher withstand voltage compared with the switch SW 7  at a side of the input terminal included in the second booster path. And the switch SW 6  at a side of the output terminal included in the second booster path is configured with an element having a higher withstand voltage compared with the switch SW 5  at a side of the input terminal included in the second booster path. 
     The capacitors C 1  to C 3  are external capacitor parts. Especially when the booster circuit  1  is integrated in an IC, an increase in a number, of the external capacitor parts results in a cost up of a circuit product. According to this embodiment, it is possible to reduce a number of the capacitor for boosting the input voltage and suppress the cost up of the booster circuit  1  effectively. And also, this makes it possible to suppress an increase in a circuit area and set the output voltage of the booster circuit  1  constant. 
     Second Embodiment 
     A booster circuit  20  according to a second embodiment is shown in  FIG. 8 . The booster circuit  20  is an example of applying this invention to a booster circuit for a negative power supply. The booster circuit  20  outputs an output voltage −2VDD by doubling an input voltage VDD to a negative side. Charging the capacitors C 1  and C 3  are conducted at a ground potential GND with the power supply E 1  as a standard. Charging the capacitor C 2  is conducted with a bias between GND-VC 1  (VC 1  is a potential at one terminal of the capacitor C 1 ). Configuration and operation of the booster circuit  20  are the same with the booster circuit  1  of the first embodiment. Note that in this second embodiment, the ground potential GND is the first power supply potential and the power supply potential VDD is the second power supply potential. 
     This invention is not limited to the above mentioned embodiments. That is, it is not limited to a circuit configuration for the three times boosting. It is possible to booster more than three times by increasing a number of the capacitor. It is noted that other circuit configuration can be adopted. 
     The switch unit can be configured with a one field effect transistor or a transfer switch. 
     It is apparent that the present invention is not limited to the above embodiment but may be modified and changed without departing from the scope and spirit of the invention.