Abstract:
A magnetic storage system includes a preamplifier writer that selectively drives a write current through a write head to write data to a magnetic storage medium. The write current generated by the preamplifier writer has a boost stage and a settling stage. An impedance changing circuit communicates with the preamplifier writer and the write head and provides a lower resistance value during the boost stage and a higher resistance value during the settling stage.

Description:
FIELD OF THE INVENTION 
   The present invention relates to magnetic data storage systems, and more particularly to a preamplifier writer for a write head in a magnetic data storage system operating at high data transfer rates. 
   BACKGROUND OF THE INVENTION 
   Conventional data storage systems typically write information onto a recording surface of a magnetic storage medium. These systems typically include a write head and a write driver circuit. The magnetic storage medium may be a disk drive of a computer. The write head may be an inductive coil, although other types of write heads may be used. 
   Information is written to the magnetic storage medium by switching a direction of current flowing through the write head. A magnetic field that is produced by the write head is stored by the magnetic storage medium. One polarity represents one digital value and the opposite polarity represents the other digital value. Data storage rates of these systems are proportional to a rate that the write driver circuit can change the direction of the write current through the write head. 
   SUMMARY OF THE INVENTION 
   A magnetic storage system includes a preamplifier writer that selectively drives a write current through a write head to write data to a magnetic storage medium. The write current generated by the preamplifier writer has a boost stage and a settling stage. An impedance changing circuit communicates with the preamplifier writer and the write head and provides a lower resistance value during the boost stage and a higher resistance value during the settling stage. 
   In other features, the write current transitions from one of a steady state positive write current to a peak negative write current and a steady state negative write current to a peak positive write current during the boost stage. The write current transitions from one of the peak negative write current to the peak steady state negative write current and the peak positive write current to the steady state positive write current during the settling stage. 
   In still other features, the lower resistance value during the boost stage increases a maximum rate change period t MRC  of the write current and the higher resistance value during the settling stage reduces a settling period t s  of the write current. 
   In yet other features, the impedance changing circuit includes a settling resistance having one end that communicates with the preamplifier writer and an opposite end that communicates with the write head. A boost resistance is in series with a switching device. The boost resistance and the switching device are in parallel with the settling resistance. The switching device is closed during the boost stage and open during the settling stage. 
   In still other features, the impedance changing circuit includes a settling resistance having one end that communicates with the preamplifier writer. A switching device is in parallel with the settling resistance. A boost resistance has one end that communicates with the settling resistance and an opposite end that communicates with the write head. The switching device is closed during the boost stage and open during the settling stage. 
   In yet other features, the preamplifier writer has a transition period T p  that is equal to a time period that is required to write data to the magnetic storage medium. The preamplifier writer and the write head are positioned on a read/write arm. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1A  is a functional block diagram of a preamplifier writer chip, transmission lines and a write head; 
       FIG. 1B  illustrates an equivalent circuit for the write head; 
       FIG. 1C  is a graph illustrating write current as a function of time; 
       FIG. 2  illustrates a boost stage, a settling stage and a steady state stage of the write current; 
       FIG. 3A  illustrates an equivalent write circuit during the boost stage; 
       FIG. 3B  illustrates write current as a function of time for a step voltage input; 
       FIG. 4A  illustrates the write circuit with the transmission line; 
       FIG. 4B  illustrates the write circuit for time less or equal to twice a transmission line delay period; 
       FIG. 4C  illustrates the circuit seen by the write head for time less or equal to twice the transmission line delay period; 
       FIG. 5  illustrates overshoot time and overshoot settling time for the write current; 
       FIG. 6  illustrates a maximum rate of change time for the write current; 
       FIG. 7  illustrates the preamplifier writer chip located at a distance d from the write head to substantially reduce transmission line effects; 
       FIG. 8  illustrates the preamplifier writer chip located on a read/write arm of the magnetic storage device; 
       FIG. 9  illustrates a first exemplary switched resistance circuit that provides a lower resistance during the boost stage and a higher resistance during the settling stage; 
       FIG. 10  illustrates a second exemplary switched resistance circuit that provides a lower resistance during the boost stage and a higher resistance during the settling stage; 
       FIG. 11  illustrates the switched resistance as a function of the boost and settling stages; and 
       FIG. 12  illustrates a third exemplary switched resistance. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify the same elements. 
   Referring now to  FIG. 1A , a write circuit  10  includes a preamplifier writer integrated circuit or chip  12  that is connected by transmission lines  14  and  16  to a write head  18 . In  FIG. 1B , an equivalent circuit for the write head  18  is shown and includes a series resistance R, an inductance L w , a capacitance C in parallel with the inductance L w , and a parallel resistance R p . 
   The transmission lines  14  and  16  introduce delays into the system. For example, a 5″ connection introduces a delay of 200 ps for 2 GHz systems. The transmission line also has an impedance Z 0  of approximately 500 Ω. Other delays and impedances can be used depending upon the particular design criteria and operating speeds. Typical values for the resistance R p  is approximately 300 Ω. Likewise, typical values for the capacitance is approximately 300 ff and for the inductance L w , is approximately 10 nH. 
   During operation, the write circuit  10  drives the write current I w  through the write head L w . For high speed operation, the write circuit  10  should be able to switch the direction of the current very fast. Referring now to  FIG. 1C , the write current I w  is shown as a function of time. The write current swings between steady state values of −I w  and +I w . A rise time t r  is typically defined as the amount of time that is required to transition from 10% to 90% of the steady state values of −I w  and +I w , although the rise time can be defined in other ways. The setting time t s  is typically defined as the amount of time required for the write current to transition from the end of the rise time to a steady state value, although the settling time can be different in other ways. In other words, the settling time t s  is from the end of the rise time t r  to the time that the write current asymptotically reaches the steady state write current value. The width of the transition period T p  depends upon the desired write speed. For example, a magnetic storage system operating at 2 GHz system has a transition period of 500 ps, although other periods may be used. The write current overshoots the steady state I w (ss) value to overcome hysteresis in the magnetization process. In other words, the write current reaches a peak write current I w (pk) before setting to the steady state value I w (ss). Preferably, I w (pk)&gt;I w (ss), t r  is short in duration and tS is very fast for magnetic storage systems. 
   Referring now to  FIG. 2 , in write circuits  10 , there are two stages of operation: boost and settling stages. The boost stage occurs when the write current transitions from a steady state positive write current to a peak negative write current and from a steady state negative write current to a peak positive write current. The settling stage occurs when the write current transitions from the peak negative write current to the peak steady state negative write current and from the peak positive write current to the steady state positive write current. The write circuit preferably operates the same for the settling period and the steady state period. 
   In  FIGS. 3A and 3B , an equivalent circuit is shown in the boost stage. For a step voltage change from 0 to V at time  0 , the write current I w  increases from 0 to 
       V   R       
 
as shown in  FIG. 3B . More particularly, 
         I   w     =       V   R     ⁢     (     1   -     ⅇ     -     (     t   τ     )           )           
 
where 
       τ   =       L   R     .         
 
for t&lt;&lt;τ, 
         I   w     ≈       V   R     ⁡     [     1   -     (     1   +     t   τ       )       ]           
 
and 
         Δ   ⁢           ⁢     I   w       =         V   R     ⁢     (     t   τ     )       =         V   R     ⁢     (     t   τ     )     ⁢   R     =     V   ⁢           ⁢       t   τ     .               
 
   Therefore, there is a certain amount of time when t&lt;&lt;τ to change I w  at the highest rate. Beyond that time, the write circuit boost is far less effective. 
   Referring now to  FIG. 4A , a simplified preamplifier writer circuit  50  is shown and includes a voltage source  52 , a source resistance R, a transmission line  54  and a write head inductor L w . Assuming that the time delay is equal to T D  and that the transmission line is matched to the source at all times (R=Z 0 ), an equivalent circuit shown in  FIG. 4B  is applicable for t≦2T D . Typical values for a 2 GHz circuit would be Tp=500 ps, T D =200 ps and 2T D =400 ps. For t≦2T D 
         V   1     =     V   2         
 
if Z 0 =R. In other words, half of the voltage V is sent to the write head. However, due to the transmission line effect, V 0  sees 2V 1 =V.
 
   For t&lt;2T D , the write head sees the circuit shown on the left in  FIG. 4C , which is similar to the circuit shown on the right in  FIG. 4C . Using typical values for T D , 2T D , Z 0 , L w  and R, the values for τ beyond which the boost is not efficient can be identified. For example, using T D =200 ps, 2T D =400 ps, Z 0 
=1000 Ω, L w =10 nH and R=150 Ω
       τ   ≤       10   ⁢           ⁢   nH       150   ⁢           ⁢   Ω       &lt;     100   ⁢           ⁢     ps   .           
 
In other words, the boost will be most effective for τ≦100 ps for these circuit values. Additional requirements may include I w (pk)=P[I w (ss)], where P is greater than 1. In some circuits, P can be set equal 2 or larger values. Therefore, t s  must be very fast before next write cycle such that t r +t s &lt;T p .
 
   As discussed above, the available time for effectively changing I w  at the highest rate is for τ≦100 ps. For example, 
           Δ   ⁢           ⁢     I   w       =       V   ⁢           ⁢   τ     L       ;       
 
In this example, τ≦100 ps, V=10V−2V be  8V for bipolar transistors, L=10nH;
 
   Therefore, 
         Δ   ⁢           ⁢     I   w       =         V   ⁢           ⁢   τ     L     =           (   8   )     ⁢     (     100   ⁢           ⁢   ps     )         10   ⁢     n   ⁢   H         =     80   ⁢           ⁢     mA   .               
 
   Referring now to  FIG. 5 , the overshoot time t osh  is defined as the time from the prior steady state I w (ss) (of one polarity) to the peak I w (pk) (of the opposite polarity). The overshoot setting time t s     —     osh  is defined as the time from the peak I w (pk) to a time when the write current asymptotically reaches the I w (ss) value. 
   Referring now to  FIG. 6 , the time period for the maximum rate of change t MRC  of I w  is equal to 
       L   R       
 
and is preferably greater than or equal to t osh . Otherwise, the write current will not quickly reach I w (pk) and the overshoot time t osh  will increase. Therefore to enlarge t MRC  to allow the peak write current to be reached more quickly (reducing t osh ), the boost requires a small value for Z 0 =R. Since the write head needs to be matched to the transmission line for operation beyond 2 GHz, the write resistance R must also be low. Having a low write resistance R, however, increases the steady state time t s .
 
   According to the present invention, an impedance changing circuit decreases the resistance R during the boost stage to increase t MRC . During the steady state stage, the impedance changing circuit increases R to minimize t s . Referring now to  FIG. 7 , the preamplifier writer is positioned at a distance d from the write head to significantly reduce the effect of transmission lines. In convention systems, the preamplifier writer is positioned approximately 5″ from the write head for 2 GHz operation, which creates transmission lines having delay effects that are described above. In a preferred embodiment, the preamplifier writer chip is positioned such that the transmission line delays have minimal effect. For example, a delay of approximately 10% of the transmission period T p  or less typically has a minimal effect. However, skilled artisans will appreciate that delays of 15%, 20% and 25% will also work with somewhat reduced performance. 
   By reducing the transmission line to approximately 10% of T p , the transmission line effects are significantly reduced. In addition to positioning the preamplifier writer close to the write head, the resistance R is changed during the boost and settling stages to increase t MRC  and to reduce t s . More particularly, the resistance R is set low during the boost stage to maximize t MRC . The resistance R is set high during the settling stage to minimize t s . 
   For example, if T p  is equal to 500 ps for 2 GHz operation, conventional preamplifier writers would be positioned approximately d=5″ and have a delay of 200 ps. According to the present invention, the preamplifier writer chip would be positioned at a distance d such that the delay is equal to T p/ 10 from the write head. Thus, using the same example set forth above for 2 GHz operation, the preamplifier writer chip is positioned at approximately (5″)(50 ps/200 ps)=5″/4=1.25″ or less from the write head. Referring now to  FIG. 8 , the preamplifier writer  12  and the write head  18  are positioned on a read/write arm  60  when the distance d is less than ½ of the diameter of a magnetic storage medium  62 . 
   Referring now to  FIG. 9 , the impedance changing circuit can be implemented in a variety of ways. For example, the impedance changing circuit can include a boost resistor R boost  and a switch. When the switch is open, the resistance is equal to R s . When the switch is closed, the resistance is equal to 
             R   boost     ⁢     R   s           R   boost     +     R   s         .       
 
If R boost &lt;&lt;R s , the resistance during the boost stage is much less than the resistance during the settling stage.
 
   Referring now to  FIG. 10 , the impedance changing circuit can include a boost resistor R boost  and a switch that is in series with the settling resistor. When the switch is closed during the boost stage, the settling resistor is shorted and the resistance is equal to R boost . When the switch is opened during the settling stage, the resistance is equal to R boost +R s . If R boost &lt;&lt;R s , then the resistance during the boost stage is much less than the resistance during the settling stage. As can be appreciated, the switches can be implemented using transistors or in any other suitable manner. Likewise the resistances can be implemented using resistors, poly resistors, inherent resistance of traces, or in any other manner. 
   During the boost stage, the resistance is reduced. During the settling stage, the resistance is increased. In  FIG. 11 , the resistance is shown as a function of the boost and settling stages. The resistance increases from the boost stage to the settling stage. 
   Referring now to  FIG. 12 , an alternate impedance changing circuit is shown. First and second transistors T 1  and T 2  have emitters that are connected to one end of the write head L w . A base of the first transistor T 1  is connected to a bias voltage A. A base of the second transistor T 2  is connected to a bias voltage B. A resistor R is connected between the emitter of the first transistor T 1  and the emitter of the second transistor T 2 . When A&gt;B, the resistor R is in circuit and the resistance is increased during the settling stage. When B&gt;A, an emitter resistance R e  shorts R, which reduces the resistance during the boost stage. Still other impedance changing circuits are contemplated. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.