Abstract:
A deep trench super switch device has a plurality of trenches, each of the trenches containing a gate electrode polysilicon layer on top of a plurality of stacked conductive floating polysilicon layers, the remainder of each of the trenches being filled with a nonconductive material.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims the benefit of U.S. Provisional Application No. 60/577,017, filed on Jun. 4, 2004, the entirety of the contents of which is hereby incorporated by reference herein. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to semiconductor devices and processes for their manufacture, and more specifically relates to a trench type MOSFET with reduced R DSON  and improved reverse recovery characteristics. 
   2. Description of the Related Art 
   High voltage superjunction MOSFET devices are well known. Such devices are usually made by a process in which multiple epitaxially grown layers with respective aligned P diffusions (for an N channel device) are formed to define spaced, elongated P type pylons or columns in an N type epitaxially grown substrate (N epi). These P type pylons are in charge balance with the surrounding N epi and, as a result, the concentration of the N epi can be increased, as compared to that of a conventional MOSFET, to reduce on resistance (R DSON ). 
   This process is complex and requires a large inventory of epitaxial reactors and a large number of process steps. Further, the breakdown voltage of the superjunction device is very sensitive to the charge balance. Thus, a 10% deviation from an optimum design can defeat production of acceptable devices. 
   It would be very desirable to provide a device which can be made by a simpler process which has the benefits of the superjunction device but without the need for multiple epitaxial depositions and charge balance control. 
   SUMMARY OF THE INVENTION 
   In accordance with the invention, the P type pylons of the superjunction device are replaced by respective stacks of conductive polysilicon bodies separated by thin oxide, thereby to define capacitor stacks within the full depth of the trench. This will define an at least constant electric field along the trench depth from the top to the bottom of the epi layer (N type for an N channel device or P type for a P channel device). The doping concentration of the epi layer can be chosen to be as low as that of a corresponding superjunction device to achieve a low R DSON , high voltage MOSFET. Further, since the P column or pylon is not used, the JFET effect of the superjunctions is eliminated along with the charge balance problems. 
   Further, the body diode is similar to that of the conventional trench device so the reverse recovery property of the new device will be better than that of the superjunction device, particularly beneficial to a zero voltage switch (ZVS) topology application. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
       FIG. 1  is a cross-section through a small segment of a wafer (or die) of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  shows a small portion of the active area of a 600 volt N channel MOSFET made in accordance with the present invention. Other voltage ratings can be chosen, and the invention can be carried out as a P channel device. 
   In  FIG. 1 , an N epi drift layer  10 , about 50 μm thick, is grown on an N +  body  11 . A drain electrode  12  is formed on the bottom of body  11 . Plural parallel trenches are etched into the N epi  10 , two of which are shown as trenches  13  and  14 . Trenches  13  and  14  may be about 36 μm deep. 
   The interior and bottom of trenches  13  and  14  are covered with a SiO 2  or other insulator material  15  and  16  respectively and are filled by stacks of conductive polysilicon layers  20 ,  21 ,  22 ,  23  and  24  in trench  13  and polysilicon layers  30 ,  31 ,  32 ,  33  and  34  in trench  14 . Layers  20  to  24  and  30  to  34  may have any desired thickness, and any number can be used. The spacing between trenches and the width of the trenches can be selected as desired. Each of the polysilicon layers are separated and insulated from one another by thin oxide layers  40 ,  41 ,  42  and  43  in trench  13  and  50 ,  51 ,  52  and  53  in trench  14 . Oxide layers  40 - 43  and  50 - 53  (preferably SiO 2 ) are each about 2 μm thick. 
   A standard trench MOSFET is then formed at the top of the die, including a P channel region  70 , an N +  source region  71  and a source metal  72  which contacts the source and channel regions  71  and  70  respectively. Source, gate and drain terminals are formed as shown. It should be noted that the gate terminals are formed in polysilicon layers  20  and  30 , and, thus these layers are biased to the gate voltage. 
   In  FIG. 1 , the polysilicon stacks  21  to  24  and  31  to  34  are floating and act as a series of capacitors which divide the drain voltage uniformly along the depth of the epi  10 . Hence the electric field is relatively constant from top to bottom of the epi layer  10 . The trenches may extend for the full depth of epi layer  10 . A bottom epi layer can be left as shown as an option for a higher voltage device. 
   The doping concentration of epi layer  10  can be made as low as in a superjunction device to achieve a low R DSON , high voltage MOSFET. 
   Since the novel structure of the invention does not have the P column (for an N channel device) the “super” JFET effect is eliminated. Further, the body diode is similar to that of a conventional trench device so its reverse recovery property will be significantly improved from classical superjunction devices to make it perform better, especially in ZVS (zero voltage switch) technology. 
   Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art such as fill the trench with P/N diode instead of polysilicon. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.