Abstract:
A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    The present application claims benefit under 35 USC 119(e) of U.S. provisional Application No. 60/908,922, filed Mar. 29, 2007, entitled “Method For Clamping A Semiconductor Region At Or Near Ground”, the content of which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to semiconductor integrated circuits, and more particularly to a circuit for clamping the voltage received by an n-type region formed in a semiconductor substrate. 
         [0003]    One conventional technique for ensuring that the voltage applied to an n-type semiconductor region does not fall significantly below the ground potential, is to place a Schottky diode between the n-type region and the ground, and further, to place a current limiting resistor between the n-type region and the node that may pull the n-type region below the ground potential, as shown in  FIG. 1 . As node  16  is pulled below the ground potential, Schottky diode  12  is forward biased thus maintaining n-type region  10  clamped at a forward Schottky diode voltage below the ground potential. 
         [0004]    One disadvantage of the clamping circuit shown in  FIG. 1  is that Schottky diode  12 , which is a metal-semiconductor junction may not be available for use. Second, if the Schottky diode has a relatively high series resistance and/or a high forward voltage, n-type region  10  may be clamped at a voltage sufficiently below the ground potential as to cause an associated parasitic lateral NPN transistor to turn on. 
       SUMMARY OF THE INVENTION 
       [0005]    In accordance with the present invention, a clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. In accordance with one embodiment, the clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base (gate) terminals of the transistors disposed in the current mirror. 
         [0006]    In accordance with another embodiment, a clamping circuit includes a current mirror, as well as first, second, third and fourth bipolar transistors. The third and fourth bipolar transistors form a cross-coupled transistor pair. The current mirror receives a first current and supplies a second current in response. The first current is received by the first and third bipolar transistors. The second current is received by the second and fourth bipolar transistors. The emitter-base junction voltages of the first and second bipolar transistors together with the base-emitter junction voltages of the third and fourth transistors define the voltage at which the n-type region is clamped. A current source supplying a current to the first bipolar transistor ensures that the clamping circuit starts up properly. 
         [0007]    In accordance with another embodiment, a clamping circuit includes a current mirror, as well as first, second, third and fourth bipolar transistors. The third and fourth bipolar transistors form a cross-coupled transistor pair. The current mirror receives a first current and supplies a second current in response. The first current is received by the first and third bipolar transistors. The second current is received by a fifth transistor coupled to the first and third transistor and adapted to develop a base-emitter voltage substantially similar to the base-emitter voltage of the first and third transistors. The emitter-base junction voltages of the first and second bipolar transistors together with the base-emitter junction voltages of the third and fourth transistors define the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base (gate) terminals of the transistors disposed in the current mirror. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, as known in the prior art. 
           [0009]      FIG. 2  is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, in accordance with one exemplary embodiment of the present invention. 
           [0010]      FIG. 3A  is a cross-section of a substrate showing a number of different regions associated with the circuit of  FIG. 2 , in accordance with one exemplary embodiment of the present invention. 
           [0011]      FIG. 3B  is a cross-section of a substrate showing a number of different regions associated with the circuit of  FIG. 2 , in accordance with another exemplary embodiment of the present invention. 
           [0012]      FIG. 4  is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, in accordance with one exemplary embodiment of the present invention. 
           [0013]      FIG. 5  is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, in accordance with one exemplary embodiment of the present invention. 
           [0014]      FIG. 6  is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, in accordance with one exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    In accordance with the present invention, an n-type semiconductor region is clamped at or near the ground potential without the use of a Schottky transistor. Although the following description is provided with reference to bipolar transistors, it is understood that MOS transistors may also be used to clamp an n-type semiconductor region in accordance with the present invention. 
         [0016]      FIG. 2  is a transistor schematic diagram of a clamping circuit  50  adapted to clamp n-type semiconductor region  20  to a known voltage, in accordance with one exemplary embodiment of the present invention. Clamping circuit  50  is shown as including bipolar PNP transistors  22 ,  24 , as well as bipolar NPN transistors  26 ,  28 . PNP transistors  22  and  24  have the same base-emitter voltage and form a current mirror. Accordingly, current I 28  supplied by the current mirror is proportional or substantially equal to current I 26  received by the current mirror. Current limiting resistor  30  is disposed between the emitter terminal of transistor  26  and node  55  to which voltage V Test  is applied. 
         [0017]    As voltage V Test  is pulled below the ground potential, transistor  32  begins to draw a relatively small amount of current from the base terminals of transistors  22  and  24 , thereby causing clamping circuit  50  to start up properly. Because transistors  22  and  24  form a current mirror, the ratio of the collector current I 26  of transistor  26  to the collector current I 28  of transistor  28  is determined by the relative base-emitter areas of transistors  22  and  24 . 
         [0018]    Assume that the ratio of the base-emitter area of transistor  22  to transistor  24  is X. The voltage received by n-type region  20  with respect to the ground potential is defined by the difference between the base-emitter regions of transistors  26  and  28 , namely VBE 28 -VBE 26 , where VBE 28  is the voltage across the base-emitter terminals of transistor  28  and VBE 26  is the voltage across the base-emitter terminals of transistor  26 . Voltages VBE 26  and VBE 28  are related to currents I 26  and I 28  according to the following: 
         [0000]        VBE   28 =(kT/q)*ln( I   28   /I   28 )  (1) 
         [0000]        VBE   26 =(kT/q)*ln( I   26   /I   26 )  (2) 
         [0000]        VBE   28   −VBE   26 =(kT/q)*ln( I   28   /I   s28 )−(kT/q)*ln( I   26   /I   s26 )  (3) 
         [0000]    where k is Boltzmann&#39;s constant (1.38×10 −23 ), T is the temperature in Kelvin, q is the electron&#39;s charge, I s26  and I s28  are constant values, respectively defined by the transfer characteristics of transistors  26  and  28  in the forward-active region. 
         [0019]    Equation (3) may be simplified as: 
         [0000]        VBE   28   −VBE   26 =(kT/q)*ln( X *( I   s26   /I   s28 ))  (4) 
         [0000]    where I s26 /I s28  is the ratio of the base-emitter areas of transistors  26  and  28 . 
         [0020]    Assume the area of transistor  28  is Y times the area of transistor  26 . Since I 28 =X*I 26 , the voltage of region  20  is defined by the following: 
         [0000]        VBE   28   −VBE   26 =(kT/q)*ln( X/Y )  (5) 
         [0021]    Since (kT/q) is constant for any given temperature, from equation (5) it is seen that the voltage of region  20  may be controlled by selecting the ratio of X and Y. For example, if X and Y are both selected to be equal to 1, the voltage of n-type region  20  with respect to ground may be set to zero. If Y is selected to be twice as large as X, the voltage of n-type region  20  with respect to ground may be set to (−18 mV) at room temperature. It is often desirable to set the clamp point slightly below ground to prevent the circuit from conducting current during a shutdown state. 
         [0022]    Current limiting resistor  30  limits the amount of current I 26  flowing through transistors  26  and  24 , according to the following: 
         [0000]        I   26 =((voltage of clamped region 20)− V   test )/( R   30 ) 
         [0000]    where R 30  is the resistance of resistor  30 ; this resistance is typically selected to be sufficiently large to keep the currents flowing through transistors  22 ,  24 ,  26 , and  28  relatively small in order to ensure proper operation. 
         [0023]    PNP transistors  22  and  24  may be either lateral or vertical PNP transistors. Transistors  26 ,  28  and  32  may be either lateral or vertical NPN transistors. Transistor  32  may be a parasitic NPN transistor that when selected to be a lateral NPN transistor may be formed by placing n-type region  20  in close proximity of transistors  22 ,  24 , or alternatively by placing an n-type moat around n-type region  20  and connecting the moat to the bases of transistors  22  and  24 . 
         [0024]    Concurrent references are made below to  FIGS. 2 and 3A .  FIG. 3A  is a cross-sectional view of a semiconductor substrate  40  having formed therein a number of different regions associated with clamp circuit  50  of  FIG. 2 , in accordance with one exemplary embodiment of the present invention. N-type region  20  is assumed to be an epitaxial region that is clamped in accordance with one embodiment of the present invention. In the embodiment shown in  FIG. 3A , it is assumed that transistors  22  and  24  (see  FIG. 2 ) are not in the vicinity of n-type region  20 . N-type region  56  and n+ region  46  is connected to the base terminals of transistors  22 ,  24  via a metal layer (not shown) and form the collector region of transistor  32  of  FIG. 2 . P-type substrate region  40  and n-type region  20  respectively form the base and emitter regions of transistor  32  of  FIG. 2 . 
         [0025]    Concurrent references are made below to  FIGS. 2 and 3B .  FIG. 3B  is a cross-sectional view of a semiconductor substrate  70  having formed therein a number of different regions associated with clamp circuit  50  of  FIG. 2 , in accordance with another exemplary embodiment of the present invention. In this embodiment, n-type region  56  and n+ region  54  together are assumed to form the base region of transistor  24  (or  22 ), as well as the collector terminal of transistor  32 . P-type substrate region  40  and n-type region  20  respectively form the base and emitter regions of transistor  32  of  FIG. 2 . 
         [0026]      FIG. 4  is a transistor schematic diagram of a clamping circuit  150  adapted to clamp n-type semiconductor region  20  to a known voltage, in accordance with another exemplary embodiment of the present invention. Clamping circuit  150  is similar to clamping circuit  50  except that in clamping circuit  150 , transistors  122  and  124  are PMOS transistors. The ratio of the channel-width to channel length of transistors  122 ,  124 , in addition to the ratio of the emitter-base areas of transistors  26  and  28  collectively define the voltage at which n-type region  20  is clamped. 
         [0027]      FIG. 5  is a transistor schematic diagram of a clamping circuit  100  adapted to clamp n-region  40  to a known voltage, in accordance with another exemplary embodiment of the present invention. Clamping circuit  100  is shown as including bipolar PNP transistors  142 ,  144 , as well as bipolar NPN transistors  146 ,  148 ,  150  and  152 . PNP transistors  142  and  144  have the same base-emitter voltages and form a current mirror, accordingly, current I 1  supplied by this current mirror is proportional or substantially equal to current I 2  received by this current mirror. Current I 1  is shown as also flowing through transistors  146  and  148 . Likewise, current I 2  is shown as also flowing through transistors  150  and  152 . Current limiting resistor  156  is disposed between the emitter terminal of transistor  150  and node  55  to which voltage V Test  is applied. 
         [0028]    Current I trickle  supplied by current source  54  is used to properly start up clamping circuit  150 . As described above, transistors  142  and  144  form a current mirror, thus setting the currents that flow through transistors  146 ,  148 , on the one hand, and transistors  150  and  152 , on the other, at a predetermined ratio. The voltage of the clamped n-type region  40  relative to the ground is defined by the following: 
         [0000]      VBE 150 +VBE 146 −VBE 152 −VBE 148   (6) 
         [0000]    where VBE 150 , VBE 146 , VBE 152 , and VBE 148  represent the base-emitter voltages of transistors  150 ,  146 ,  152  and  148  respectively. 
         [0029]    By selecting the ratio of the base-emitter areas of the various transistors shown in  FIG. 5 , the voltage at which n-type region  40  is clamped, is set to a desired value. N-type region  40  is clamped in accordance with the following expression: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    where I s152 , I s148 , I s146 , and I s150  are values respectively defined by the transfer characteristics of transistors  152 ,  148 ,  146  and  150  in the forward-active region. Cross-coupled transistors  148  and  150  reduce the output impedance and improve the power supply rejection ratio. In some embodiments, PMOS transistors may be used in place of PNP transistors  142   144 . The cross-coupled transistors  148  and  150  cancel collector current mismatches between transistors  142 ,  152  and  150  disposed in current leg  155 , and transistors  144 ,  146  and  148  disposed in current leg  145 . If the supply voltage V CC  rises, early voltage effects cause a shift in the current ratio of transistors  142  and  144 . The cross-coupling of transistors  148  and  150  cancels out such a current shift, thereby improving the power supply rejection ratio. As n-type region  40  is pulled further below the ground potential, the level of currents flowing through the base terminals of transistors  142  and  144  increases. The cross-coupling of transistors  148  and  150  cancels out any shift that would otherwise occur in the collector currents of transistors  142  and  144  as a result of increases in the base currents of these two transistors. 
         [0030]      FIG. 6  is a transistor schematic diagram of a clamping circuit  200  adapted to clamp n-region  80  to a known voltage, in accordance with another exemplary embodiment of the present invention. Clamping circuit  200  is shown as including, in part, bipolar PNP transistors  270 ,  272 , as well as bipolar NPN transistors  268 ,  266 ,  264 ,  260  and  262 . Transistor  272 , also disposed in clamping circuit  200 , may be a parasitic NPN transistor used to start up circuit  200 . The following description is provided with reference to setting the clamp voltage of n-region  80  to nearly 0 volts, i.e., the ground potential. It is understood, however, that the clamp voltage of n-region  80  may be selectively set to any other desired value by varying the ratio of the emitter-base areas of the various transistors shown in circuit  200  in a manner generally similar to that described above with respect to  FIG. 2 . 
         [0031]    Current limiting resistor  276  is disposed between the emitter terminal of transistor  262  and node  55  to which voltage V Test  is applied. As voltage V Test  is pulled below the ground potential, transistor  272  is turned on, thereby pulling a relatively small amount of current out from the base terminals of transistors  270  and  274 , in turn, ensuring that circuit  200  starts up properly. 
         [0032]    Transistors  270  and  274  form a current mirror, therefore assuming transistors  270  and  274  have similar base-emitter areas, current I 1  is substantially equal to current I 2 . Therefore, assuming that the base currents are negligible, the collector currents of transistors  266  and  268  are substantially equal. Consequently, the base-emitter voltage of transistor  268 , namely VBE 268 , is substantially equal to the base-emitter voltage of transistor  266 , namely VBE 266 . Since the emitter terminals of both transistors  268  and  266  receive the ground potential, the voltage at node N 1  is substantially equal to the voltage at node N 2 . 
         [0033]    Because the emitter voltages of transistors  260  and  264  are substantially the same and the base terminals of these two transistors are coupled to one another, current I 2  flowing through transistor  264  is substantially equal to current I 3  flowing through transistor  260 . Hence, neglecting base currents, because current I 2  is equal to current I 3 , the base-emitter voltage of transistor  266 , i.e., VBE 266  is substantially equal to the base-emitter voltage of transistor  262 , i.e., VBE 262 . Likewise, the base-emitter voltage of transistor  264 , i.e., VBE 264  is substantially equal to the base-emitter voltage of transistor  266 . Accordingly: 
         [0000]      VBE 268 =VBE 266 =VBE 264 =VBE 260 =VBE 262   (8) 
         [0034]    As seen from  FIG. 5 , the voltage at n-type region  80  is defined by the following expression: 
         [0000]      VBE 266 +VBE 260 −VBE 264 −VBE 262   (9) 
         [0035]    Since the base-emitter voltages of transistors  266 ,  260 ,  264  and  262  are substantially the same, as shown in expression (8), the voltage at n-type region  80  is nearly equal to zero. As described above, by varying the ratio of the emitter-base areas of the transistors shown in circuit  100 , the voltage at which n-type region  80  is clamped, may be selectively set to any other desired value. N-type region  80  is clamped in accordance with the following expression: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    where I s265 , I s262 , I s266 , and I s260  are values respectively defined by the transfer characteristics of transistors  264 ,  262 ,  266  and  260  in the forward-active region 
         [0036]    The above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible. The invention is not limited by the type of transistors or integrated circuits in which the present invention may be disposed. Nor is the disclosure limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present disclosure. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.