Abstract:
A switch system has a master sub-switch and a slave sub-switch, the master sub-switch having a first bridge for transmitting the received packet via the first bus, a second bridge for transmitting the packet when the address information of the second bridge matches with the address information included in the packet, and a third bridge for receiving the packet from the first bridge and transmitting the packet to the slave sub-switch, the slave sub-switch having a fourth bridge for receiving the packet from the third bridge and transmitting the packet, and a fifth bridge for receiving the packet from the fourth bridge, and transmitting the packet when the address information of the fifth bridge matches with the address information included in the packet, wherein the master sub-switch has a table including address information of the fifth bridge, and transmits the packet to the fifth bridge in reference to the table.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-074287, filed on Mar. 25, 2009, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The present art relates to a switch system, a sub-switch and a method of controlling the switch system. 
     BACKGROUND 
     One example of an input/output (I/O) bus that connects an information processing device and an I/O device is a PCI Express (peripheral component interconnect express) bus. The PCI Express has a tree structure with a host bridge located at the root and an I/O device located at an endpoint. When multiple I/O devices are connected, a PCI express switch is required at an intermediate point in the tree structure. The PCI Express switch has a two-level tree structure in which ports serve as PCI-to-PCI (P2P) bridges. Unique numbers are assigned from an OS (operating system)/BIOS (basic input/output system) to devices included in the PCI Express. 
     A switch that supports a large number of ports is required in order to connect a large number of I/O devices in a single system. However, when the number of ports is merely increased in a single switch LSI (large scale integration), cost for LSI design and manufacture and printed-circuit-board implementation increases. Accordingly, multiple PCI Express switches are simply connected to increase the number of ports in order to connect a large number of I/O devices. When the switches are connected, the PCI Express hierarchical structure is determined depending on which switch is closer to a host bridge. That is, during start of an information processing device, the bus hierarchical levels of the switches are seen differently from the OS/BIOS. However, since the bus hierarchical levels are finite, the depth of the bus hierarchical levels that can be supported by the OS/BIOS is also limited. 
     SUMMARY 
     According to an aspect of an embodiment, a switch system connectable to a first I/O device, a second I/O device, and a third I/O device, has a master sub-switch and a slave sub-switch, the master sub-switch having a first bus, a first bridge connected to the first bus for receiving a packet from the first I/O device and transmitting the received packet to the first bus, the first bridge being capable of transmitting a request to the first bus so as to inquire whether there is any bridge addressed by the packet via the first bus, the first bridge being capable of receiving an acknowledge from any bridge addressed by the packet via the first bus before transmitting the packet to the first bus, a second bridge connected to the first bus for receiving the packet from the first bridge via the first bus, comparing address information of the second bridge with address information included in the packet, and transmitting the packet to the second I/O device when the address information of the second bridge matches with the address information included in the packet, and a third bridge connected to the first bus for receiving the packet from the first bridge via the first bus and transmitting the packet to the slave sub-switch, the slave sub-switch having a second bus, a fourth bridge for receiving the packet from the third bridge and transmitting the packet via the second bus, and a fifth bridge for receiving the packet from the fourth bridge to the second bus, comparing address information of the fifth bridge with address information included in the packet, and transmitting the packet to the third I/O device when the address information of the fifth bridge matches with the address information included in the packet, wherein the master sub-switch has a table including address information of the fifth bridge, and the first bridge determines whether the address information included in the packet matches with the address information of the fifth bridge or not in reference to the table, and transmits the packet to the fifth bridge when the address information included in the packet matches with the address information of the fifth bridge. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a diagram of a system according to a first embodiment of the present art; 
         FIG. 2  is a diagram of a PCIe system in the first embodiment; 
         FIG. 3  illustrates a system tree in the first embodiment; 
         FIG. 4  illustrates how bus numbers are assigned; 
         FIG. 5  is a diagram illustrating one example of a packet format in the first embodiment; 
         FIG. 6  is a diagram of a switch system in the first embodiment; 
         FIG. 7  is a diagram of switches before connection in the first embodiment; 
         FIG. 8  is a diagram of a switch system in the first embodiment; 
         FIG. 9  is a diagram of switches before connection in the first embodiment; 
         FIG. 10  is a diagram of switch system in the first embodiment; 
         FIG. 11  illustrates a configuration information table; 
         FIG. 12  is a flowchart illustrating processing for updating the configuration information table in the first embodiment; 
         FIG. 13  is a diagram illustrating routing of a packet received by a master switch; 
         FIG. 14  is a diagram illustrating routing of a packet received by a slave switch; 
         FIG. 15  is a flowchart illustrating packet transfer processing performed by the master switch; 
         FIG. 16  is a flowchart illustrating packet transfer processing performed by the slave switch; 
         FIG. 17  is a flowchart illustrating packet destination search processing; 
         FIG. 18  is a diagram illustrating an advantage of the first embodiment; 
         FIG. 19  is a diagram illustrating a system according to a second embodiment; 
         FIG. 20  is a diagram illustrating a PCIe system in the second embodiment; 
         FIG. 21  is a diagram illustrating one example of a packet format in the second embodiment; 
         FIG. 22  is a diagram illustrating a switch system in the second embodiment; 
         FIG. 23  is a diagram illustrating switches before connection in the second embodiment; 
         FIG. 24  is a diagram illustrating a switch system in the second embodiment; 
         FIG. 25  illustrates a partition table in the second embodiment; 
         FIG. 26  is a flowchart illustrating processing for updating a configuration information table in the second embodiment; 
         FIG. 27  is a diagram illustrating routing of a packet received by a master switch; 
         FIG. 28  is a diagram illustrating routing of a packet received by a slave switch; 
         FIG. 29  is a flowchart illustrating packet transfer processing in the second embodiment; 
         FIG. 30  is a flowchart illustrating the packet transfer processing in the second embodiment; and 
         FIG. 31  illustrates an advantage of the second embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Embodiments of the present art will be described below with reference to the accompanying drawings. 
       FIG. 1  is a block diagram of a system  100  according to a first embodiment of the present art. The system  100  includes a host  102 , a PCI Express (PCIe) switch  104 , an I/O (Input/Output) device  106 , a network interface card (NIC)  108 , a network  110 , a host bus adapter (HBA)  112 , and a disk  111 . 
     The system  100  has a tree structure having its root at a host bridge  1021 . Leaf elements are called endpoints (EPs). The host  102  has a central processing unit (CPU)  1022  and the host bridge  1021 . 
     The host  102  performs data processing. The CPU  1022  is connected to the host bridge  1021 . The host bridge  1021  interconnects the CPU  1022  and a PCI bus to perform data control. The host bridge  1021  is connected to the PCIe switch  104 . The PCIe switch  104  connects the host  102  with the I/O device  106 , the NIC  108 , and the HBA  112 , which are endpoints. 
     The NIC  108  is an extension card for connecting the PCIe switch  104  with the network  110 , which may be a local area network (LAN). The NIC  108  is connected to the network  110 . The HBA  112  is an adapter for connecting the PCIe switch  104  with the disk  111 . The HBA  112  is connected to the disk  111 . Information is stored on the disk  111 . 
       FIG. 2  is a block diagram of the PCIe switch  104  in the present embodiment. The PCIe switch  104  has an upstream port  1041 , an upstream P2P (PCI-to-PCI) bridge  1040 , downstream P2P bridges  1042 , and downstream ports  1043 . The upstream port  1041  is connected to the upstream P2P bridges  1040 . The upstream P2P bridge  1040  and the downstream P2P bridges  1042  are interconnected through an internal PCI bus  1044 . The downstream P2P bridges  1042  are connected to the corresponding downstream ports  1043 . The PCIe switch  104 , which serves as a master switch, has a configuration information table  500 . The configuration information table  500  is described below. 
     The upstream port  1041  and the downstream ports  1043 , which are physical ports, control PCIe links to perform data transfer. The PCIe links are communication channels with other devices. 
     The upstream P2P bridge  1040  and the downstream P2P bridges  1042  perform packet transfer and ordering. Each of the upstream P2P bridge  1040  and the downstream P2P bridges  1042  is broadly classified into an upstream portion and a downstream portion. The PCIe switch  104  has one upstream P2P bridge  1040 . Bus numbers  508 , device numbers  506 , and function numbers  509  are assigned to the upstream portions of the upstream P2P bridge  1040  and the downstream P2P bridges  1042 . The bus numbers  508  are assigned from an OS/BIOS. The device numbers  506  indicate relative port numbers after connection with the PCIe switch  104 . The function numbers  509  are assigned to respective functions of devices. The downstream portions of the upstream P2P bridge  1040  and the downstream P2P bridges  1042  have range information of the bus numbers  508  to be assigned. The downstream portions of the upstream P2P bridge  1040  and the downstream P2P bridges  1042  also have information of a first address and a size of address space to be assigned. The upstream P2P bridge  1040  is capable of transmitting a request to a first bus so as to inquire whether there is any bridge addressed by the packet to the first bus, the upstream P2P bridge  1040  being capable of receiving an acknowledge from any bridge address by the packet to the first bus before transmitting the packet to the first bus. 
     Each of the upstream P2P bridge  1040  and the downstream P2P bridges  1042  has a state machine  1037  and a register  1039 . The register  1039  stores a bus number and so on of a device connected downstream. For example, by referring to a bus number in a packet transmitted from the host  102  and a bus number stored by the register  1039 , the state machine  1037  determines the destination of the packet. 
       FIG. 3  illustrates one example of a system tree  200  in the present embodiment. Bus numbers, device numbers, and function numbers are assigned to devices included in the system tree  200 . Unique bus numbers are assigned to PCIe links and an internal bus. The term “internal bus” herein refers to a bus that interconnects P2P bridges in devices. The bus numbers are finite resources and the total number of bus segments is 256. The P2P bridge divides the bus segments. The bus segments are divided into an upstream side and a downstream side across the P2P bridge. The bus segments that are closer to the host  102  are at the upstream side and the bus segments that are farther from the host  102  are at the downstream side. The distance of the downstream P2P bridge  1042  from the host  102  is defined as depth of the hierarchy. 
     How the OS assigns bus numbers to bridges will now be described with reference to  FIG. 4 . A system  210  includes a CPU  1022 , a bridge  1   10 , a bridge  2   20 , a bridge  3   30 , and devices  21 ,  22 ,  23 , and  24 . The CPU  1022 , the bridge  1   10 , and the device  21  and  22  are interconnected through a bus  0   9 . The bridge  1   10 , the devices  23  and  24 , the bridge  2   20 , and the bridge  3   30  are interconnected through a bus  1   11 . A bus  2   12  is further connected to the bridge  2   20  and a bus  3   13  is connected to the bridge  3   30 . Ports are not illustrated in the system  210 . 
     The OS performs scanning to find the bridge  1   10  as a first bridge. For example, a depthwise algorithm is used as a method for the scanning. The OS assigns a bus number of 1 to the bus  1   11  located downstream of the bridge  1   10 . The bridge  1   10  is assigned a primary bus number of 0, which is a bus number immediately upstream of the bridge  1   10 . The bridge  1   10  is assigned a secondary bus number of 1, which is a bus number immediately downstream of the bridge  1   10 . In addition, the bridge  1   10  is temporarily assigned a subordinate bus number of 0xFF, which is the largest one of the numbers of reachable buses located downstream of the bridge  1   10 . This means that a type 1 PCI configuration address specifying a bus number of 1 or larger is passed to the bus  1   11  across the bridge  1   10 . When a packet has a bus number of 1, type 1 is converted into type 0. However, when a packet has a number other than a bus number of 1, type 1 is not converted into type 0. 
     The OS proceeds the scanning to the bus  1   11 . In this case, the OS finds the bridge  2   20 . The OS assigns a primary bus number of 1 to the bridge  2   20  and a secondary bus number of 2 to the bridge  2   20 . Since no new bridge exists downstream of the bridge  2   20 , the OS assigns a subordinate bus number of 2 to the bridge  2   20 . 
     The OS returns to scanning of the bus  1   11  and finds the bridge  3   30 . The OS assigns a primary bus number of 1 and a secondary bus number of 3 to the bridge  3   30 . Since no bridge exists downstream of the bridge  3   30 , the OS assigns a subordinate bus number of 3 to the bridge  3   30 . Lastly, the OS assigns a subordinate bus number of 3 to the bridge  1   10 . 
       FIG. 5  illustrates one example of the format of a packet. A packet  300  has a header  302 , a transaction layer packet (TLP)  304 , and a cyclic redundancy check (CRC- 32 )  306 . The header  302  is used for identifying the start of the packet. The TLP  304  is a packet for transmission and reception of a command and data and includes a destination address or a bus number. The CRC- 32   306  is an error detection code. In the present embodiment, for example, the header  302  has 2 bytes, the TLP  304  has 12 to 4116 bytes, and the CRC- 32   306  has 4 bytes. 
     There are an address routing scheme and an ID (identifier) routing scheme as a packet routing scheme. The address routing scheme is a scheme in which the destination port of a packet is specified by a destination address. The packet is transferred to a downstream P2P bridge having the destination address in its downstream address space. When no corresponding P2P bridge exists, a packet is transferred to an upstream bridge. The ID routing scheme is a scheme in which the destination port of a packet is specified by a set of a bus number, a device number, and a function number. The packet is transferred to a downstream P2P bridge having a corresponding bus number at the downstream thereof. 
     The packet is broadly classified into three types: a configuration read/write (R/W) packet, a memory read/write (R/W) packet, and a message packet. The configuration read/write packet represents reading or writing of device information and is used for configuration access. The memory read/write packet represents data reading or writing. The message packet represents an interruption. The term “configuration access” herein refers to a configuration transaction issued from the OS/BIOS. The configuration access is a transaction for allowing the OS/BIOS to set bus numbers for the P2P bridges and the I/O devices and to obtain vender information and for setting enabling/disabling of direct access memory on the P2P bridges and the I/O devices. Configuration information of PCIe devices including a PCIe switch is set by the configuration access. 
     In addition, the configuration access is classified into type 0 and type 1. The type 0 configuration access does not contain a bus number. The type 0 configuration access is interpreted by all devices as a configuration address on the PCI device. The type 1 configuration access contains a bus number. The type 1 configuration access is ignored by all PCIe devices except P2P bridges. Each P2P bridge that refers to the type 1 configuration address transfers a packet downstream. 
       FIG. 6  illustrates a switch system  400  in the present embodiment. The switch system  400  illustrated in  FIG. 6  has a configuration in which two switches illustrated in  FIG. 7  are connected. Of switches to be connected, a switch that is the closest to the host bridge  1021  is referred to as a master switch  402 . Another switch is referred to as a slave switch  404 . A dedicated link that is called a virtual link provides a connection between the master switch  402  and the slave switch  404 . Ports to which the virtual link is connected are referred to as virtual ports  1045 . When N switches are connected in the system, the master switch  402  has N−1 virtual ports  1045  and the slave switch  404  has one virtual port. 
     A P2P bridge  1046  is connected to each virtual port  1045 . The P2P bridge  1046  first determines whether or not a command transmitted from the OS/BIOS is a configuration access command. When the command is a configuration access command, the corresponding virtual port  1045  transmits the command to the connected switch. In this manner, the P2P bridge  1046  connected to the virtual port  1045  directly transfers a configuration access command to the opposing switch through the virtual link without terminating the configuration access transmitted from the OS/BIOS. Conversion from type 1 to type 0 is not also performed. This operation prevents the OS/BIOS from recognizing the virtual link hierarchy. The P2P bridge  1046  directly transfers all transactions to the virtual link that connects the PCI Express switches, without making changes to the transactions. The same applies to the configuration access. The virtual ports and the virtual link do not depend on a PCI Express protocol. As an illustrative example of the virtual ports, a closed PCI Express bus can be used for the virtual ports and the virtual link. That is, the provision of address space that is independent from the OS/BIOS achieves the above-described function. 
     The state machine  1037  illustrated in  FIG. 2  determines whether or not a packet is requesting access to the register  1039  to thereby determine whether or not a command transmitted from the OS/BIOS is a configuration access command. When a command transmitted from the OS/BIOS is a configuration access command, the state machine  1037  transmits the packet without allowing packet to access the register  1039 . The processing in which the P2P bridge  1046  connected to the virtual port  1045  determines whether or not a command transmitted from the OS/BIOS is a configuration access command may be realized by, for example, firmware. 
       FIG. 8  illustrates a switch system  401  in the present embodiment. The switch system  401  illustrated in  FIG. 8  has a configuration in which three switches illustrated in  FIG. 9  are connected. 
       FIG. 10  illustrates a switch system  410 . A master switch  402  has configuration information of the master switch  402  and a slave switch  404  as a configuration information table  500 . The configuration information table  500  is updated based on a configuration access issued by the OS/BIOS. The master switch  402  snoops a configuration access packet and uses information of the configuration access packet to create the configuration information table  500 . 
       FIG. 11  illustrates the configuration information table  500 . The configuration information table  500  has switch numbers  502 , port numbers  504 , device numbers  506 , bus numbers  508 , address range information  510 , and bus range information  512 . The switch numbers  502  are unique numbers in the system. Each port number  504  indicates a port position of each switch. Each device number  506  indicates a relative port number after connection. Each bus number  508  is assigned from the OS/BIOS. The address range information  510  is assigned from the OS/BIOS and indicates the range of address space located below a corresponding P2P bridge. The bus range information  512  is assigned from the OS/BIOS and indicates the range of PCI buses located below a corresponding P2P bridge. 
     Processing for updating the configuration information table will now be described with reference to  FIG. 12 . In step S 101 , the upstream P2P bridge  1040  of the master switch  402  receives a packet. The process then proceeds to step S 102 . 
     In step S 102 , the upstream P2P bridge  1040  checks the header of the received packet. The process then proceeds to step S 103 . 
     In step S 103 , the upstream P2P bridge  1040  refers to the header of the received packet to determine whether or not the received packet is a type 0 configuration write request. When the received packet is a type 0 configuration write request, the process proceeds to step S 104 . On the other hand, when the received packet is not a type 0 configuration write request, the process proceeds to step S 106 . 
     In step S 104 , the upstream P2P bridge  1040  refers to the header of the received packet to determine whether or not the configuration address of the received packet is a secondary bus number. The term “secondary bus number” refers to the number of a bus immediately downstream of the PCI bridge. When the configuration address of the received packet is a secondary bus number, the process proceeds to step S 105 . On the other hand, when the configuration address of the received packet is not a secondary bus number, the process proceeds to step S 109 . 
     In step S 105 , the upstream P2P bridge  1040  updates an internal bus number. The processing then ends. 
     When it is determined in step S 103  described above that the received packet is not a type 0 configuration write request, the process proceeds to step S 106 . 
     In step S 106 , the upstream P2P bridge  1040  refers to the header of the received packet to determine whether or not the received packet is a type 1 configuration write request. When the received packet is a type 1 configuration write request, the process proceeds to step S 107 . On the other hand, when the received packet is not a type 1 configuration write request, the processing ends. 
     In step S 107 , the upstream P2P bridge  1040  refers to the header of the received packet to determine whether or not the bus number in the packet is an internal bus number. When the bus number in the packet is an internal bus number, the process proceeds to step S 108 . On the other hand, when the bus number in the packet is not an internal bus number, the processing ends. 
     In step S 108 , the upstream P2P bridge  1040  refers to the device number in the packet, sets an entry to be processed in the configuration information, and updates the bus number in the entry. The process then proceeds to step S 109 . 
     In step S 109 , the upstream P2P bridge  1040  determines whether or not the configuration address is bridge information by referring to the device number in the packet. When the configuration address is bridge information, the process proceeds to step S 110 . On the other hand, when the configuration address is not bridge information, the proceeding ends. 
     In step S 110 , the upstream P2P bridge  1040  updates the bridge information of the entry to be updated, the entry being set in step S 108 . The processing then ends. 
     A packet routing scheme will now be described with reference to  FIGS. 13 and 14 .  FIG. 13  illustrates routing of a packet received at a port of the master switch  402 . First, the header of a packet is analyzed at the reception port and a request is issued to the configuration information table  500  to resolve the destination. Depending on the type of packet, the configuration information table  500  determines the destination port of the packet on the basis of a number association table and bus range cache (ID routing) or address range cache (address routing). When the destination port of the packet is in the slave switch  404 , the packet is transferred to the virtual port  1045  corresponding to the virtual link. The slave switch  404  performs processing that is analogous to that of a typical PCIe switch. On the other hand,  FIG. 14  illustrates routing of a packet received at a port of the slave switch  404 . The reception port transfers the packet to the master switch  402  through the virtual link. The master switch  402  routes the packet in accordance with the above-described procedure. 
     Packet transfer processing performed by the master switch  402  will now be described with reference to  FIG. 15 . 
     In step S 201 , the upstream P2P bridge  1040  of the master switch  402  receives a packet. The process then proceeds to step S 202 . 
     In step S 202 , the upstream P2P bridge  1040  checks the header of the received packet. The process then proceeds to step S 203 . 
     In step S 203 , the upstream P2P bridge  1040  refers to the configuration information table  500  to search for the destination of the packet. Destination search processing is described below with reference to  FIG. 17 . After step S 203 , the process proceeds to step S 204 . 
     In step S 204 , the upstream P2P bridge  1040  determines whether or not the destination of the packet is in the master switch  402 . When the destination of the packet is in the master switch  402 , the process proceeds to step S 205 . On the other hand, when the destination of the packet is not in the master switch  402 , the process proceeds to step S 206 . 
     In step S 205 , the upstream P2P bridge  1040  transfers the packet to a corresponding port in the master switch  402 . The processing then ends. 
     In step S 206 , the upstream P2P bridge  1040  transfers the packet to a virtual port of the corresponding slave switch  404 . The processing then ends. 
     Packet transfer processing performed by the slave switch  404  will now be described with reference to  FIG. 16 . 
     In step S 211 , the downstream P2P bridge  1042  of the slave switch  404  receives a packet. The process then proceeds to step S 212 . 
     In step S 212 , the downstream P2P bridge  1042  determines whether or not the reception port is a virtual link. When the reception port is a virtual link, the process proceeds to step S 213 . On the other hand, when the reception port is not a virtual link, the process proceeds to step S 214 . 
     In step S 213 , the downstream P2P bridge  1042  transfers the packet in accordance with a PCI Express rule. The processing then ends. 
     In step S 214 , the downstream P2P bridge  1042  transfers the packet to the virtual port connected to the master switch  402 . The processing then ends. 
     Packet destination search processing will now be described with reference to  FIG. 17 . 
     In step S 301 , the upstream P2P bridge  1040  determines whether or not the routing type of the packet is an address or ID. When the packet routing type is an address, the process proceeds to step S 302 . On the other hand, when the packet routing type is an ID, the process proceeds to step S 303 . 
     In step S 302 , the upstream P2P bridge  1040  determines whether or not the address in the packet is in the range of addresses registered in the configuration information table  500 . When the address in the packet is in the range of addresses registered in the configuration information table  500 , the process proceeds to step S 304 . On the other hand, when the address in the packet is not in the range of addresses registered in the configuration information table  500 , the process proceeds to step S 306 . 
     In step S 304 , the upstream P2P bridge  1040  sets a corresponding port as the destination portion. The processing then ends. 
     In step S 303 , the upstream P2P bridge  1040  determines whether or not the ID of the packet is in the range of IDs registered in the configuration information table  500 . When the ID of the packet is in the range of IDs registered in the configuration information table  500 , the process proceeds to step S 304  in which the upstream P2P bridge  1040  sets a corresponding port as the destination port. On the other hand, when the ID of the packet is not in the range of IDs registered in the configuration information table  500 , the process proceeds to step S 305 . 
     In step S 305 , the upstream P2P bridge  1040  determines whether or not the bus of the packet is in the range of buses registered in the configuration information table  500 . When the bus of the packet is in the range of buses registered in the configuration information table  500 , the process proceeds to step S 304  in which the upstream P2P bridge  1040  sets a corresponding port as the destination port. On the other hand, when the bus of the packet is not in the range of buses registered in the configuration information table  500 , the process proceeds to step S 306 . 
     In step S 306 , the upstream P2P bridge  1040  determines whether or not the packet is transmitted from a downstream port. When the packet is transmitted from a downstream port, the process proceeds to step S 307 . On the other hand, when the packet is not transmitted from a downstream port, the process proceeds to step S 308 . 
     In step S 307 , the upstream P2P bridge  1040  sets an upstream port as the destination port. The processing then ends. 
     In step S 308 , the upstream P2P bridge  1040  outputs an error indicating that no packet transfer destination exists. 
     An advantage of the first embodiment will now be described with reference to  FIG. 18 . For example, when two PCIe switches are connected in a manner in which an upstream port and a downstream port are combined as in a switch system  421  illustrated in  FIG. 18 , a bus number used in the system and the number of hierarchical levels up to the endpoints each increase by two compared to the case of a single switch. In contrast, according to the first embodiment, since two PCIe switches are connected through a virtual link, a bus number used in the system and the number of hierarchical levels up to the endpoints do not increase. Therefore, even when multiple switches are connected, the bus hierarchical levels used and the depth in the hierarchy can be maintained constant. 
       FIG. 19  is a block diagram of a system  101  according to a second embodiment. In  FIG. 19 , elements that are similar to those in the first embodiment are denoted by the same reference numerals. There is a demand to use logically divided (partitioned) ones of a system having multiple hosts, such as for servers or PCs. The system  101  meets the demand. The system  101  has a first host bridge  1021  and a second host bridge  1021 . Since the multiple host bridges  1021  are provided, the PCIe switch also requires partitioning. As a technology for logically dividing a PCIe switch having multiple switch chips, Multi-Root I/O Virtualization (MR-IOV) has been standardized by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). 
       FIG. 20  illustrates logical division of a PCIe switch  114  in the present embodiment. The PCIe switch  114  has a partition  1  and a partition  2 . The partition  1  has an upstream port  1141 , an upstream P2P bridge  1140 , downstream P2P bridges  1142 , and downstream ports  1143 . The upstream P2P bridge  1140  and the downstream P2P bridges  1142  are interconnected through an internal PCI bus  11441 . The partition  2  has an upstream port  1141 , an upstream P2P bridge  1140 , a downstream P2P bridge  1142 , and a downstream port  1143 . The upstream P2P bridge  1140  and the downstream P2P bridge  1142  are interconnected through an internal PCI bus  11442 . 
       FIG. 21  illustrates one example of the format of a packet. A packet  310  has a header  302 , a tag  301 , a PTN# 303 , a TLP  304 , and a CRC- 32   306 . Elements described in  FIG. 5  are denoted by the same reference numbers, and descriptions thereof are not given hereinbelow. The tag  301  is a header for identifying the start of the PTN# 303 . The PTN# 303  indicates a partition number. In the present embodiment, for example, the header  302  has 2 bytes, the tag  301  has 2 bytes, the PTN# 303  has 2 bytes, the TLP  304  has 12 to 4116 bytes, and the CRC- 32   306  has 4 bytes. 
       FIG. 22  illustrates a switch system  411  in the present embodiment. The switch system  411  illustrated in  FIG. 22  has a configuration in which two switches illustrated in  FIG. 23  are connected. Of switches to be connected, a switch that is the closest to the host bridge  1021  is referred to as a master switch  412  and another switch is referred to as a slave switch  414 . A dedicated link that is called a virtual link provides a connection between the master switch  412  and the slave switch  414 . Ports to which the virtual link is connected are called virtual ports  1145 . When N switches are connected in the system, the master switch  412  has N−1 virtual ports  1145  and the slave switch  414  has one virtual port. 
     A P2P bridge  1146  is connected to each virtual port  1145 . The P2P bridge  1146  first determines whether or not a command transmitted from the OS/BIOS is a configuration access command. When the command is a configuration access command, the virtual port  1145  transmits the command to the connected switch. 
       FIG. 24  illustrates a switch system  420 . A master switch  412  has configuration information of the master switch  412  and a slave switch  414  as a configuration information table  500 . 
       FIG. 25  illustrates a partition table  600 . The partition table  600  has partition numbers  602 , switch numbers  604 , port numbers  606 , transfer port numbers  608 , and downstream port numbers  610 . The partition numbers  602  indicates indices. The switch numbers  604  and the port numbers  606  are upstream port information. The transfer port numbers  608  and the downstream port numbers  610  are local-switch information. The partition table  600  is set by, for example, software during determination of partition configuration. 
     Processing for updating the configuration information table will now be described with reference to  FIG. 26 . 
     In step S 401 , the upstream P2P bridge  1140  of the master switch  412  receives a packet. The process then proceeds to step S 402 . 
     In step S 402 , the upstream P2P bridge  1140  obtains a partition number from the reception port number of the packet. The process then proceeds to step S 403 . 
     In step S 403 , the upstream P2P bridge  1140  obtains a configuration information table corresponding to the partition number obtained in step S 402 . The process then proceeds to step S 404 . 
     In step S 404 , the upstream P2P bridge  1140  checks the header of the received packet. The process then proceeds to step S 405 . 
     In step S 405 , the upstream P2P bridge  1140  determines whether or not the received packet is a type 0 configuration write request by referring to the header of the received packet. When the received packet is a type 0 configuration write request, the process proceeds to step S 406 . On the other hand, when the received packet is not a type 0 configuration write request, the process proceeds to step S 408 . 
     In step S 406 , the upstream P2P bridge  1140  determines whether or not the configuration address of the received packet is a secondary bus number by referring to the header of the received packet. When the configuration address of the received packet is a secondary bus number, the process proceeds to step S 407 . On the other hand, when the configuration address of the received packet is not a secondary bus number, the process proceeds to step S 411 . 
     In step S 407 , the upstream P2P bridge  1140  updates an internal bus number. The processing then ends. 
     In step S 408 , the upstream P2P bridge  1140  determines whether or not the received packet is a type 1 configuration write request by referring to the header of the received packet. When the received packet is a type 1 configuration write request, the process proceeds to step S 409 . On the other hand, when the received packet is not a type 1 configuration write request, the processing ends. 
     In step S 409 , the upstream P2P bridge  1140  determines whether or not the bus number of the packet is an internal bus number by referring to the header of the received packet. When the bus number of the packet is an internal bus number, the process proceeds to step S 410 . On the other hand, when the bus number of the packet is not an internal bus number, the processing ends. 
     In step S 410 , the upstream P2P bridge  1140  refers to the device number in the packet, sets an entry to be processed in the configuration information, and updates the bus number in the entry. The process then proceeds to step S 411 . 
     In step S 411 , the upstream P2P bridge  1140  determines whether or not the configuration address is bridge information by referring to the device number in the packet. When the configuration address is bridge information, the process proceeds to step S 412 . On the other hand, when the configuration address is not bridge information, the proceeding ends. 
     In step S 412 , the master switch  412  updates the bridge information of the entry to be updated, the entry being set in step S 410 . The processing then ends. 
     A packet routing scheme will now be described with reference to  FIGS. 27 and 28 .  FIG. 27  illustrates routing of a packet received at a port of the master switch  412 . First, the header of a packet is analyzed at the reception port and a request is issued to the configuration information table  500  to resolve the destination. Depending on the type of packet, the configuration information table  500  determines the destination port of the packet on the basis of a number association table and bus range cache (ID routing) or address range cache (address routing). When the destination port of the packet is in the slave switch  414 , the packet is transferred to the virtual port  1145  corresponding to the virtual link. A packet through which the packet is to be transferred is obtained from the partition table  600  in accordance with the partition number of the reception port of the packet. The slave switch  414  performs processing that is analogous to that of a typical PCIe switch. On the other hand,  FIG. 28  illustrates routing of a packet received at the port of the slave switch  414 . The reception port transfers the packet to the master switch  412  through the virtual link. The master switch  412  routes the packet in accordance with the above-described procedure. A port through which the packet is to be transferred is obtained from the partition table  600  in accordance with the partition number of the reception port of the packet. 
     Packet transfer processing will now be described with reference to  FIGS. 29 and 30 . 
     In step S 501 , the upstream P2P bridge  1140  of the master switch  412  that has received a packet determines whether or not the reception port thereof is a virtual link. When the reception port is a virtual link, the process proceeds to step S 502 . On the other hand, when the reception port is not a virtual link, the process proceeds to step S 503 . 
     In step S 502 , the upstream P2P bridge  1140  obtains a partition number from the packet obtained in step S 501 . The process then proceeds to step S 504 . 
     In step S 503 , the upstream P2P bridge  1140  obtains a partition number from the number of the reception port. The process then proceeds to step S 504 . 
     In step S 504 , the upstream P2P bridge  1140  determines whether or not a virtual switch corresponding to the partition number is a master switch. When the virtual switch corresponding to the partition number is a master switch, the process proceeds to step S 509 . On the other hand, when the virtual switch corresponding to the partition number is not a master switch, the process proceeds to step S 505 . 
     In step S 505 , the upstream P2P bridge  1140  determines whether or not the reception port is a virtual link. When the reception port is a virtual link, the process proceeds to step S 506 . On the other hand, when the reception port is not a virtual link, the process proceeds to step S 508 . 
     In step S 506 , the downstream P2P bridge  1142  selects a downstream port corresponding to the partition number. The process then proceeds to step S 507 . 
     In step S 507 , the downstream P2P bridge  1142  transfers the packet in accordance with a PCI Express rule. The processing then ends. 
     In step S 508 , the downstream P2P bridge  1142  transfers the packet to the virtual port  1145  connected to the master switch  412 . The processing then ends. 
     In step S 509 , the downstream P2P bridge  1142  obtains a configuration information table corresponding to the partition number. The process then proceeds to step S 510  in  FIG. 30 . 
     In step S 510 , the upstream P2P bridge  1140  checks the header of the received packet. The process then proceeds to step S 511 . 
     In step S 511 , the upstream P2P bridge  1140  searches for the destination of the received packet. Since the destination search processing is analogous to that described with reference to  FIG. 17 , a description thereof is not given hereinbelow. After step S 511 , the process proceeds to step S 512 . 
     In step S 512 , the upstream P2P bridge  1140  determines whether or not the destination of the received packet is in the master switch  412 . When the destination of the packet is in the master switch  412 , the process proceeds to step S 513 . On the other hand, when the destination of the packet is not in the master switch  412 , the process proceeds to step S 514 . 
     In step S 513 , the upstream P2P bridge  1140  transfers the packet to a corresponding port in the master switch  412 . The processing then ends. 
     In step S 514 , the upstream P2P bridge  1140  transfers the packet to the virtual port  1145  of the corresponding slave switch  414 . The processing then ends. 
     An advantage of the second embodiment will now be described with reference to  FIG. 31 . For example, when two PCIe switches are connected in a manner in which an upstream port and a downstream port are combined as in a switch system  431  illustrated in  FIG. 31 , a bus number used in the system and the number of hierarchical levels up to the endpoints each increase by two compared to the case of a single switch. In contrast, according to the second embodiment, since two PCIe switches are connected through a virtual link, a bus number used in the system and the number of hierarchical levels up to the endpoints do not increase. Therefore, even when multiple switches are connected, the bus hierarchical levels used and the depth in the hierarchy can be maintained constant. 
     According to one aspect of an embodiment, since a first switch refers to a table included in the switch to transfer a packet to a second switch or an I/O device corresponding to an address in the packet, the first switch and the second switch can be integrated into a single unit. Accordingly, it is possible to increase the system scale without increasing the number of bus hierarchical levels. 
     As mentioned above, the present art has been specifically described for better understanding of the embodiments thereof and the above description does not limit other aspects of the invention. Therefore, the present invention can be altered and modified in a variety of ways without departing from the gist and scope thereof. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.