Abstract:
A system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the majority of the collected data to external system memory, which is typically comprised of commodity memory chips. Since this external system memory is already in use by other system functions, utilizing such unused regions of this external memory increases overall hardware efficiency, while achieving lower ASIC manufacturing cost.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S)  
       [0001]     This application is a continuation of U.S. patent application Ser. No. 09/785,794, filed Feb. 16, 2001, which claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/183,615, filed Feb. 18, 2000. The entire content in each of the above-cited applications is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention generally relates to the field of data storage. More particularly, the invention relates to an efficient system and method for storing and transferring data within a data-collecting system, such as statistical information collected from monitored functions in communications transceivers.  
       BACKGROUND OF THE INVENTION  
       [0003]     Orthogonal Frequency Domain Multiplexing (OFDM) transceiver application-specific integrated circuits (ASIC), such as those used in wireless modems, often include a data collection function that monitors various components of the circuit and collects corresponding data for subsequent processing, often by an external processor. Typically, the collected data is statistical data relating to the performance of the respective components.  
         [0004]     The ASIC&#39;s data collection function gathers information from internal processing units of the ASIC and forwards this information to a host processor for postprocessing. For example, system requirements may require monitoring relevant parameters of internal blocks, such as power, antenna gain, and the like, with the collected data being processed to determine whether fine tuning of the system is needed.  
         [0005]     In order to achieve this data collection function, the prior art systems employ large amounts of on-chip memory (e.g., 12K (12,000) bytes) to store the collected statistical information within the ASIC prior to forwarding that data to the host processor for processing. This approach of using large on-chip memory to store collected statistics is undesirable because it increases the cost of the ASIC, and does not exploit unused regions of existing system memory.  
         [0006]     Thus, what is needed is a system and method for efficiently collecting and transferring data from an ASIC or other like circuit to external system memory. The present invention addresses one or more of these desirable features.  
       SUMMARY OF THE INVENTION  
       [0007]     Briefly, the present invention is directed to a system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the majority of the collected data to external system memory, which is typically comprised of commodity memory chips. Since this external system memory already exists for use by other system functions, utilizing unused regions of this external memory increases overall hardware efficiency, while achieving lower ASIC manufacturing cost.  
         [0008]     In one embodiment, the invention is directed to a system for managing data generated by one or more sources, and includes a host processor and memory unit, and a circuit including one or more sources, a controller connected to the one or more sources, and a buffer memory, where the controller is operative to periodically receive data from the one or more sources, transfer the data to the buffer, and at a predetermined point the buffer is controlled to transfer the data to the memory unit.  
         [0009]     In another embodiment, the invention is directed to a method for managing data in an integrated circuit, including receiving data from one or more sources within the integrated circuit, storing the data in a buffer memory, transferring the data from the buffer to an external memory location upon reaching a predetermined condition, and then repeating the process. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     Other features and advantages of the invention will become apparent from a description of the figures, in which:  
         [0011]      FIG. 1  shows in block diagram form an overview of one illustrative embodiment of a system according to the present invention; and  
         [0012]      FIG. 2  shows in block diagram form in more detail an overview of an illustrative embodiment of a system according to the present invention which includes-, in combination, both a statistics collection function and diagnostic function. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]     Referring now to the figures, and in particular to  FIG. 1 , there is shown one illustrative embodiment of a circuit  10  for collecting and transferring data according to the present invention. Circuit  10  receives data from one or more data collecting and/or generating modules  12 , and forwards such data to a buffer memory device  14 . Buffer memory device  14  periodically transfers the data to an external system memory  16 , which is accessed by a host processor  18  for processing of the collected data, as is described in more detail below.  
         [0014]     In one embodiment, circuit  10  is in the form of an application-specific integrated circuit (ASIC) that is designed to collect data from the module or modules  12 . For example, circuit  10  may interact with a plurality of modules  12 , where each module monitors a particular system function and generates corresponding data. Such data can correspond to various parameters, such as voltage levels, antenna gain, and the like. Thus, it will be understood by those skilled in the art that the data can take many different forms. For ease of description, such data will be collectively referred to herein as “statistics data”. Moreover, while only two modules are shown in  FIG. 1 , it will be apparent that the number of modules can be one, two, or any other number of modules.  
         [0015]     Circuit  10  includes a controller  20 , which in one embodiment is in the form of a statistics output selector (hereinafter referred to as “controller”). As described above, controller  20  may interact with one or more modules  12 . In one embodiment, data capture control signals are transmitted between the controller  20  and the module(s)  12  over a signal line  22  upon reaching respective time slots. Each module may be assigned to selected time slots, and when those pre-selected time slots are detected, the controller receives data from that module and writes the received data to the buffer  14 . Alternatively, the module(s)  12  may be designed to perform periodically monitoring and to automatically collect corresponding data, which is then transmitted to controller  20  over a data bus  24  or any other suitable signal line or lines for writing to buffer  14 . In yet another embodiment, handshaking may be implemented between controller  20  and buffer  14  for monitoring the status of the buffer  14  to determine the progress of the write operation.  
         [0016]     In the situation where controller  20  is connected to plural modules  12  over data bus  24 , controller  20  is preferably designed to perform a multiplexing function to transfer the collected data from plural modules over one or more data lines  26  to buffer memory device  14 . Such multiplexing may be conducted in any suitable manner, such as time division multiplexing or the like.  
         [0017]     Buffer memory device  14  is connected to controller  20  via a pair of signal lines  28  and  30 . Signal line  28  provides for transmission of the collected data from controller  20  to buffer memory device  14  for temporary storage, while signal line  30  provides for the two-way transmission of write control signals between buffer  14  and controller  20 , as described above.  
         [0018]     Buffer memory device  14  is also connected to an external memory interface  32  via signal lines  34  and  36 . Signal line  34  provides for transmission of stored data from buffer memory device  14  to the interface  32 , while signal line  36  provides for the two-way transmission of read control signals between buffer memory device  14  and interface  32 .  
         [0019]     In one embodiment, when a minimum quantity of new data is present in the buffer  14 , and the external device which will use the data is available for processing the data, read controls are asserted to the buffer  14  to retrieve the data from buffer  14  and transfer the data to the external memory xx. Thus, when the buffer  14  achieves a predetermined level of fullness (based on the size of buffer  14  and the particular statistics mode), read request signals are transmitted from buffer  14  to interface  32 . The status of the external device (e.g., processor  18 ) is then determined and, when it is available, the read controls are asserted to buffer  14 , such that the data is transferred to external memory  16  for accessing by the external device.  
         [0020]     Interface  32  connects to external system memory  16  via signal line  38 , and transfers the stored data to memory  16  at a predetermined, unused location of that memory  16 . Host processor  18 , via a processor interface  19 , may then access memory  16  over signal line  40  and retrieve the data for processing.  
         [0021]     Buffer memory device  14  is a relatively small memory device. In one embodiment, buffer memory device  14  is capable of storing 128 bytes of data. However, it will be understood that the size of buffer memory device will vary, depending on the number of modules  12 , the capabilities of host processor  18 , and the like. Thus, in one embodiment the size of the buffer memory can be between about 100 and about a few kilobytes.  
         [0022]     Buffer memory device  14  may also have other attributes, such as an input pointer (where new data will be written into the buffer), and an output pointer (where the next item will be read from) and/or a count of the space used or free. Such attributes may be used during the control signal stages of the circuit  10 , as is described below.  
         [0023]     The operation of circuit  10 , in one illustrative embodiment, is now described in greater detail. Operation begins with controller  20  transmitting data capture control signals to the respective modules  12  over signal line  22  to coordinate the receipt of data from the respective modules  12 . It will be understood that, in the case of multiple modules  12 , controller  20  may either assign discrete time slots for each module  12  to transmit its data, or controller  20  may simultaneously receive data from multiple modules  12  and perform a multiplexing function to transmit the data to buffer memory device  14 . Alternatively, the modules may be programmed to automatically perform their respective data collection and/or generation functions, and to forward such data on to controller  20 .  
         [0024]     In any event, prior to transmitting data to buffer memory device  14 , controller  20  transmits write control signals to buffer memory device  14  over signal line  30 . Those control signals may include a request from controller  20  to buffer memory device  14 , requesting to transmit data to buffer memory device  14 . Included in the request may be the amount of data to be transmitted. Buffer memory device  14  may then determine the amount of available memory and transmit a reply signal to controller over signal line  30  indicating that it is ready to receive the data. Controller  20  then transmits the data over data line  28 , and the data is stored in buffer memory  14 .  
         [0025]     At a predetermined point in the process, buffer read control signals are transmitted between buffer memory device  14  and interface  32  over control signal line  36 . In one embodiment, interface  32  transmits a request to read data from buffer memory device  14 , and device  14  transmits a reply indicating the amount of new data to be read. Alternatively, buffer memory device  14  can transmit a signal to interface  32  at a predetermined point in the process, for example in the situation where the buffer memory  14  contains some minimum amount of new data, or when buffer  14  is full of new data and controller  20  is requesting to transmit additional data to the buffer  14 .  
         [0026]     At the appropriate point, for example when the external device (e.g., host processor  18 ) is available to access data from external memory  16 , buffer memory device  14  then transmits the stored data over data line  34  to interface  32 , which writes the data to a preselected location in external system memory  16 , based upon memory control signals transmitted between interface  32  and memory  16 . Host processor  18  may then access the data in memory  16  to process the data.  
         [0027]     Referring now to  FIG. 2 , there is shown an ASIC  40  in which the present invention can be implemented. The ASIC includes a plurality of modules, each of which generates data relating to a particular parameter. In addition, designated modules may be stimulated during a diagnostics mode of operation with data from input test pins, with such module generating output data that either drives output test pins, or drives another module, which then generates output that drives the test pins. The ASIC includes a Statistics/Diagnostics Bus (SDB)  42  that provides the means through which the normal run-time statistics as well as testing related system diagnostic information are collected.  
         [0028]     Under normal mode of operation, parameters accessible within the ASIC, in groups of up to 128 bytes per burst, may be captured by an SDB Controller  44  and stored in buffer memory  46  before being relayed to the external system, including system memory  47  and a Central Processing Unit (CPU) (or Host Processor)  48 , for analysis, as described above in connection with  FIG. 1 . It will be understood by those skilled in the art that some modules have less than 128 bytes of data per burst to be collected, and that some modules may generate more than 128 bytes per burst.  
         [0029]     Within the ASIC  40 , datapath modules can generate statistics data characterizing system performance and operating conditions on a periodic basis when the statistics collection function is enabled.  
         [0030]     In one embodiment, the respective modules generate data representative of the respective characteristics being monitored on a per burst of data basis. For example, within one burst, a first one of the modules will generate a measurement of the data that it is processing, such as keeping the statistics of the input that it is receiving. Under the control of controller  44 , that data is provided to data output selector  50  for storage in the buffer memory device  46 . Data output selector  50 , under appropriate write controls, multiplexes the data from the respective modules onto buffer memory  46 . Under buffer read controls, an external memory interface  52 , such as a Direct Memory Access (DMA) device, provides an interface to external system memory  47 , such as a Synchronous Dynamic Random Access Memory (SDRAM). The information stored in external system memory  47  can then be accessed by CPU/Host Processor  48 , via interface  74  and appropriate software, for use by various aspects of the system as desired.  
         [0031]     In detail, the embodiment of  FIG. 2  includes the following data collecting modules: a Receiver Finite Impulse Response Filter RXFIR  54 , Receiver Synchronization block RXSYNC  56 , Receiver Front End RXFE  58 , Receiver Back End RXBE  60 , and Receiver Forward Error Correction block RXFEC  62 , under the control of Receiver Media Access Control layer/Physical layer RX MAC/PHY  64 . Similarly, data (e.g., diagnostic data) can be collected from Transmit Forward Error Correction block TXFEC  66 , Transmit Digital Signal Processor TXDSP  68 , and Transmit Finite Impulse Response filter TXFIR  70 . Controller  44  is fed by Clock Generator CLKGEN  71  which is responsive to clock signals XTAL and MCK. Host processor  48  and external memory  47  communicate with each other and with controller  44  over an Internal System Bus (ISB) 72 , via respective CPU interface  74 , external system memory interface  76 , and external memory interface  52 . Controller  44  can also be involved with handling diagnostics under the control of register  78 , and provide input/output clocking and output data and valid signals on output lines  80 ,  82 , and  84  for diagnostics purposes.  
         [0032]     Thus, it will be understood by those skilled in the art that the present invention has utility in various ASICs as well as in other circuits. The specific example shown in  FIG. 2  is meant for illustrative purposes to illustrate one such implementation.  
         [0033]     From the foregoing, it will be apparent that the present invention efficiently manages the storage of collected data, such as statistics data and the like. By shifting the burden of storing the bulk of the collected data to previously unutilized regions of the external system memory, the invention achieves a relatively low-cost ASIC due to the relatively small on-chip memory size, as well as increased hardware efficiency due to utilization of previously unused region of system memory.  
         [0034]     While the above description contains many specific features of the invention, these should not be construed as limitations on the scope of the invention, but rather as exemplary embodiments thereof. Many other variations are possible. Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their legal equivalents.