Abstract:
Disclosed herein is an apparatus and a method for determining characteristics of a bit stream of binary pulses having measuring apparatus for sampling pulse voltage levels in excess of voltage threshold levels during each of delayed clock pulses for a series of pulses of the binary coded pulse bit stream. Control apparatus coupled to the measuring apparatus generates a series of the threshold voltage levels and the delayed clock pulses during each period of a bit stream pulse. Multiple counts of the sampled pulse voltage levels are recorded during each delayed clock pulse and accumulated for a series of pulses of the binary coded pulse bit stream. The control apparatus analyzes and processes the accumulated counts to generate an eye diagram therefrom defining the characteristics of the binary pulse bit stream.

Description:
FIELD OF THE INVENTION 
     This invention relates to apparatus and a method for analyzing a waveform and in particular to apparatus and method for the statistical eye diagram measurement of a high speed binary pulse coded bit stream. 
     BACKGROUND OF THE INVENTION 
     High-speed communication systems typically communicate with each other by sending serial bit streams of data between transmitters and receivers. These bit streams are usually binary coded pulse signals represented by zeros and ones which may be electrical voltages or optical signals derived from the electrical voltages created by the transmitters and which pulse coded signals are applied to a transmission facility connecting the transmitters with the receivers. The receivers decode the received pulse code signal data to obtain the information therein. 
     If a receiver receives pulse code signals that have been deformed by errors occurring in the transmission facility problems or if the receiver improperly decodes the received pulse coded signals, the effect is that bit errors may occur in the communications there resulting in wrong information being received by the receiver. Thus, designers, engineers, installers and maintenance personal need to evaluate the stream of pulse coded signals, oftentimes called bit streams, to monitor system performance and to help in diagnosing system problems. It is typical to monitor the quality of such bit streams by using a sampling oscilloscope. 
     In the monitoring operation, the bit stream and a trigger input in the form of a clock signal having a repetition rate identical to the repetition rate of the bit stream and synchronous therewith are applied to the inputs of the sampling oscilloscope. Samples of the voltage levels of the binary pulses of the bit stream are taken at various time offsets from the repetitive trigger input and are plotted as sample points on the display of the oscilloscope. Voltage samples are continuously taken of the bit stream and added to the sample oscilloscope in combination with the older sample points, which continue to exist on the sample oscilloscope display. Over a relatively short period of time, hundreds or thousands of the sample points on the sample oscilloscope display plot the possible voltage distributions at each time offset from the trigger input. By sweeping all time offsets in the range of interest, a diagram appears on the sampling oscilloscope display, which reveals the quality of the measured high-speed bit stream. This type of diagram, oftentimes called an “eye” diagram, is often used to view high-speed binary pulse bit streams during the various development, installation and maintenance phases of high-speed communications systems. 
     A problem exists in using sampling oscilloscopes in this manner to measure the quality of high-speed communication systems. As the bit stream data rate increases, the bandwidth of the sampling oscilloscopes needed to create the eye diagrams increases proportionally thereto resulting in a higher cost. Another problem arises in that as the cost of the sampling oscilloscopes increases and due to the design issues of super high-speed systems, the present sampling methods takes samples at a relatively few of all the possible edges of the bit stream pulses thereby limiting the current effective sampling rate in the range of ten thousand samples per second by typical known systems. Accordingly, a need exists in the art for an apparatus and a method for actively determining the quality of high-speed binary pulse bit streams used to transfer information and data between communications systems. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide binary pulse coded waveform measuring apparatus for determining the characteristics of a high speed bit stream of binary pulses used to transfer information between communications systems and in particular to generate an eye diagram defining the quality of the binary pulse bit stream. 
     It is also an object of the invention to provide to provide logic apparatus for sampling pulse voltage levels in excess of a series of voltage threshold levels during each of a series of delayed clock pulses for a series of pulses of the binary pulse bit stream. 
     It is also an object of the invention to provide a control apparatus coupled to the logic apparatus and controlled by a programmed processor to generate the series of threshold voltage levels and the delayed clock pulses during each period of a bit stream pulse. The control apparatus accumulates multiple counts of the sampled pulse voltage levels during each delayed clock pulse for a series of pulses of the binary coded pulse bit stream and processes the accumulated counts to generate an eye diagram therefrom defining the characteristics of the binary pulse bit stream. 
     It is a further object of the invention to provide a method for determining characteristics of a bit stream of binary pulses by sampling pulse voltage levels in excess of voltage threshold levels during each of delayed clock pulses for a series of pulses of the binary coded pulse bit stream. The method generates a series of the voltage threshold levels and the delayed clock pulses during each period of a bit stream pulse and accumulating multiple counts of the sampled pulse voltage levels during each delayed clock pulse for a series of pulses of the binary pulse bit stream. The accumulated counts are processed to generate an eye diagram defining the characteristics of the binary pulse bit stream. 
     In a preferred embodiment of the invention, apparatus for determining characteristics of a bit stream of binary pulses has measuring apparatus for sampling pulse voltage levels in excess of voltage threshold levels during each of delayed clock pulses for a series of pulses of the binary coded pulse bit stream. Control means coupled to the measuring apparatus generates a series of the threshold voltage levels and the delayed clock pulses during each period of a bit stream pulse and accumulates multiple counts of the sampled pulse voltage levels during each delayed clock pulse for a series of pulses of the binary coded pulse bit stream. The accumulated counts are processed to generate an eye diagram therefrom defining the characteristics of the binary pulse bit stream. 
     Also in accordance with the preferred embodiment of the invention, a method for determining characteristics of a bit stream of binary pulses generates a series of threshold voltage levels and delayed clock pulses during each period of a bit stream pulse. The method measures and accumulates multiple counts of pulse voltage levels in excess of the generated voltage threshold levels during each delayed clock pulse for a series of pulses of the binary coded pulse bit stream. The method then analyzes the accumulated voltage counts and generates an eye diagram therefrom defining the characteristics of the binary pulse bit stream. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a further understanding of the objects and advantages of the present invention, reference should be had to the following detailed description, taken in conjunction with the accompanying drawing figures, in which like parts are given like reference numerals and wherein: 
     FIG. 1 is a block diagram of binary pulse coded waveform measuring apparatus in accordance with the principles of the invention connected to a communication system for generating a statistical eye diagram measurement of a binary pulse coded waveform transmitted from a system transmitter to a system receiver, 
     FIG. 2 is a block diagram of the binary pulse coded waveform measuring apparatus set forth in FIG. 1, 
     FIG. 3 is a flow chart of the operation of the measuring apparatus set forth in FIGS. 1 and 2 for generating an array of data counts of the measurement of the voltage levels versus time of each pulse of the high speed binary bit stream set transmitted between the transmitter and receiver of the communication system set forth in FIG. 1, 
     FIG. 4 is a flow chart of the operation of the measuring apparatus set forth in FIGS. 1 and 2 for processing the measurement data generated by executing the flow chart operating steps of FIG. 3 into a statistical array of eye diagram data, 
     FIG. 5 is an example representation of the raw sample count data processed by operation of the measurement algorithm flow chart of flow chart of FIG. 3, and 
     FIG. 6 is an example representation of the statistical data processed by the operation of the processing algorithm flow chart of flow chart of FIG. 5 to form an eye diagram representing the characteristics and quality of the high speed binary bit stream transmitted between the transmitter and receiver of the communication system set forth in FIG.  1 . 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1 of the drawing, high-speed communication system  1  consists of a transmitter  10  interconnected by a transmission facility  12  with a receiver  11 . Information is transmitted to receiver  11  in a binary coded pulse format as a binary bit stream  13  applied to the input of transmission facility  12 . Transmission facility  12  may be any one of a large number of high-speed transmission facilities such as coaxial cables, optical fibers, radio and satellite links or the like. In a typical application, the binary pulses of input binary bit stream  13  may be reconfigured by the characteristics of the transmission facility  12  and appear as the rounded binary coded pulse format shown as the binary bit stream  14  received by receiver  11 . The binary pulse coded waveform measuring apparatus  2  as set forth in FIG. 1, may be connected to transmission facility  12  at either the output of transmitter  10 , the input of receiver  11 , at various locations along transmission facility  12  or at various locations within transmitter  10  and receiver  11  wherein it is desired to measure the quality of the transmitted and received binary pulse coded bit streams. In operation, control  21  controls the operation of count logic  20  to generate a statistical eye diagram  30  representing the quality of the measured the binary pulse coded bit stream  14  on display apparatus  3  which may be any one of a number of well known display such as a computer or stand alone monitors, plotters, various storage devices, or the like. 
     In order to create an eye diagram from the measured high speed pulse coded bit stream, samples must be collected from the waveform such that the samples correspond to the number of times that the waveform of the measured pulse crosses over a time offset and voltage coordinate for all the time offsets and voltage levels of interest. In general, a pulse coded bit stream consists of a series of succeeding “0” and “1” pulses wherein each “0” pulse is transmitted at one voltage level and each “1” pulse is transmitted at another voltage level. The specific sequence of the of the “0” and “1” pulses define the information or data transmitted by transmitter  10  to receiver  11 . The pulses have a repetition rate wherein each pulse has a period of time, hereinafter referred to as the pulse period, and follows a preceding pulse at the repetition rate determined by the communication system clock. 
     Measuring apparatus, or count logic  20 , controlled by control  21 , samples the pulse voltage levels in excess of voltage threshold levels during each of delayed clock pulses for a series of pulses of the binary coded pulse bit stream. Count logic  20  collects counts of the voltage of each pulse during the pulse period at variable voltage thresholds V VT  occurring at voltage steps ΔV between a minimum voltage V MIN  and a maximum voltage V MAX  at a variable time delayed clock pulse T VD  occurring in time steps ΔT between a range of zero and a selected maximum time T MAX . 
     Control  21  coupled to the count logic  20  generates a series of the threshold voltage levels V VT  and the delayed clock pulses T VD  during each period of a bit stream pulse and accumulates multiple counts of the sampled pulse voltage levels in excess of the threshold voltage levels V VT  during each delayed clock pulse T VD  for a series of pulses of the binary coded pulse bit stream. The counts are recorded by control  21  as an Eye Data Array A 1   2111  in memory  211  (FIG. 2) wherein the count data is stored at positions T VD , V VT  in the array defined by the voltage threshold levels V VT  separated by the voltage step ΔV and at ones of the delayed clock pulses T VD  separated by the time step ΔT during pulse periods of the series of pulses succeeding the first measured binary pulse. Thus, the count starts in each pulse at time zero of the pulse period wherein counts of the pulse voltage level are taken and recorded in the Eye Data Array as the variable voltage threshold V VT  is moved from the minimum voltage V MIN  to the maximum voltage V MAX . The time delay clock pulse T VD  is advanced in time a time step ΔT and the counting process is repeated. The count measurement continues in ΔT steps until time T MAX  is reached. The measurement of the counts may be continued over a large number of the bit stream pulses, for example, over several thousand serial pulses, with the total count being recorded in the eye data array. 
     The binary pulse coded waveform measuring apparatus  2 , FIG. 2, comprises count logic  20  controlled by a control  21 . Control  21  may be any one of a number of different types of computers and need not be described in great detail. Sufficient for an understanding of the invention, control  21  has a processor  210  connected by a bus  212  to a memory  211  and a display unit  3 . Processor  210  is also connected by bus  212  to address registers  213  and  215 , the operation of the registers are well known. In the general operation, processor  210  addresses address register  213  and requests that the count data received from the above threshold counter  202  of count logic stored in address register  213  be recorded in the eye data array A 1 ,  2111  of memory  211 . Processor  210  also addresses address registers  215  and transfers information thereto that is stored in the address registers and used to control various components in the count logic  20 . The high-speed binary bit stream  13  is applied to interface  216  so that processor  210  can generate clock pulses that are synchronous the repetition rate of the bit stream. The programs stored in memory  211  control processor  210  in the operation of the count logic  20  and control logic  21  in accordance with the principles of the invention. 
     Count logic  20  has a one-bit comparator  200  with one input connected to the transmission facility  12  or other point in the transmitter  10  or receiver  11  to measure the high speed binary coded bit stream  13 . The logic elements  200  and  201  are the main sampling components and are comprised of a D-type flip-flop  201  preceded by a one-bit comparator  200 . The one-bit comparator  200  will output a high when the signal voltage on the positive pin is higher than the signal voltage on the negative pin. The D-flip flop  201  will copy the value on the “D” input to the “Q” output connected to the enable input of the above threshold counter  202 . In operation, processor  210  determining a pulse repetition rate of the high speed binary pulse bit stream by interface  216  and generates a series of time delay clock pulses T VD  each separated by a predefined time step ΔT during a period of each binary pulse and applies the time delay clock pulses T VD  to the above threshold counter  202  and measurement window counter  203  via address register  215 . The above threshold counter  202  is a synchronous enableable and resetable counter and is of a type well known in the art. The counter will increment when not reset only when the enable line is “1” (high) at the rising edge of a clocking signal applied to the counter. Above threshold counter  202  holds the number of counts that succeeded in being higher than the voltage threshold V VT  as the voltage threshold V VT  is moved from the minimum voltage V MIN  to the maximum voltage V MAX . threshold at the time of the rising edge of the time delay clock pulse T VD . 
     The measurement window counter  203  is also a synchronous enableable and resetable counter and sets the measurement window size which sets the number of bits that are looked at to compute the “Above Threshold” count for each time delay clock pulse T VD  and voltage threshold V VT  position in the eye diagram. The variable voltage threshold V VT  is a static control voltage applied to the negative pin of comparator  200  and is set by processor  210  by addressing address register  215  to control the digital to V VT  converter  214  to step this voltage in precise increments and apply the appropriate voltage step ΔV increment to the negative pin of comparator  200 . 
     Control  21  initiates the start sample sequence by applying a start sample pulse to reset the above threshold counter  202  and measurement window counter  203  which starts accumulating data. Once the measurement window counter  203  reaches it&#39;s terminal count, its corresponding output signal will cause the flip-flop  201  to shift the delayed sample value to the output and the apparatus  2  will automatically hold the current “Above Threshold” count ready to be stored away. To start the next measurement, control  21  generates a new variable voltage threshold V VT  and/or variable time delay clock pulse T VD  and another start sample pulse. 
     The measurement algorithm, FIG. 3, is stored in memory  211  and starts controlling control  21  to apply the start sample pulse to control logic  20 . The initial value of the variable time delay pulse T VD  is set to zero, step  21110 , and values selected by the user are assigned to time T MAX , voltage V MAX , time step ΔT, voltage step ΔV and minimum voltage V MIN , step  21111 . 
     If the value of time delay pulse T VD  is greater than the value of time T MAX , step  21112 , the algorithm is completed. If not, the variable voltage threshold V VT  is set to the value of minimum voltage V MIN , step  21113 . 
     Count logic  20  takes the count, step  21114 , and records the count in eye diagram array (EDA) AI  2111  at the position EDA (time delay pulse T VD , variable voltage threshold V VT ), step  21115 . 
     The variable voltage threshold V VT  is increased by the value of the voltage step ΔV. step  21116 . If the new value of the variable voltage threshold V VT , step  21117 , is less than the value of voltage V MAX , the algorithm repeats steps  21114  through  21116  to record counts in the eye data array  2111  at the appropriate time delay pulse T VD  and variable voltage threshold V VT  array positions. 
     When the value of the variable voltage threshold V VT  becomes greater than the value of the voltage V MAX , step  21117 , the time delay pulse T VD  is increased by the time step ΔT, step  21118 . Steps  21112  through  21117  are repeated to record additional counts in the eye data array  2111  at the appropriate time delay pulse T VD  and variable voltage threshold V VT  array positions. When the value of the time delay pulse T VD  is greater than the value of time T MAX , step  21112 , the measurement algorithm is at an end, step  21119 . 
     Typically, the measurement may be repeated many times to determine the quality of a high speed binary pulse bit stream. Thus, when finished, the operation of the measurement algorithm has enabled processor  210 , FIG. 2, to generate a first eye data array  2111  in memory  211  wherein the sampled pulse voltage level counts are recorded at array positions defined by ones of the variable voltage threshold levels V VT  separated by the voltage step ΔV and at ones of the time delayed clock pulses T VD  separated by the time step ΔT during the pulse periods. An example of an eye data array showing typical count data collected by the measuring algorithm of FIG. 3 is set forth in FIG. 5 of the drawing wherein the count data is recorded at the array positions T VD , V VT  wherein the time delay pulses T VD  are separated by the time step ΔT and the variable voltage thresholds V VT  are separated by the voltage step ΔV. 
     It is obvious from the foregoing that the facility, economy and efficiency of binary pulse coded waveform measuring apparatus has been improved by apparatus arrange to measure a high speed binary pulse bit stream and generate an eye diagram showing the characteristics and quality of the measured high speed binary pulse bit stream. 
     While the foregoing detailed description has described an embodiment of specific binary pulse coded waveform measuring apparatus, it is to be understood that the above description is illustrative only and is not limiting of the disclosed invention. Particularly other configurations are within the scope and spirit of this invention. Thus, the invention is to be limited only by the claims set forth below.