Abstract:
Methods and apparatus for forming word line stacks are comprised of a silicon diffusion barrier region, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

Description:
This application is a divisional of application Ser. No. 08/741,870 filed Oct. 29, 1996 now U.S. Pat. No. 6,080,645. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the manufacture of semiconductor devices, and in particular, to the manufacture of gate structures utilized in advanced semiconductor products, having a doped silicon diffusion barrier region. 
     Background 
     Semiconductor memory devices are comprised of an array of memory cells. Each memory cell is comprised of a capacitor, on which the charge stored represents the logical state of the memory cell. A charged capacitor corresponds to a logical state of “1” and an uncharged capacitor corresponds to a logical state of “0.” Word lines activate access transistors, so that the logical state of a memory cell can be read. Gates of multiple transistors are formed as one word line. 
     An example of a word line&#39;s application is in a dynamic random access memory (DRAM). In a DRAM, a common word line, used to access memory cells, is fabricated on a p-type silicon substrate coated with a thin film of silicon dioxide (SiO 2 ), known as gate oxide. Then, a word line is formed on the gate oxide layer as a two-layer stack, comprising silicon (or polysilicon), coated with a conductor material. The most common two-layer stack used in the industry is a layer of polysilicon, coated with a tungsten silicide layer. Tungsten silicide is used because of its good integration properties, such as providing good thermal stability, stability during source/drain oxidation, and stability during dry etching, as well as having a low resistivity. Although titanium silicide is approximately 75% less resisitive than tungsten silicide, it has not been used extensively in two-layer stacks because it is not as thermally stable. Titanium silicide tends to agglomerate during subsequent high temperature processing steps. Alternatively, a metal is used instead of a silicide for the conductor layer. 
     Of primary concern is minimizing resistivity throughout the word line, due to the need to reduce RC time constants and access multiple memory cells in as short a period of time as possible. The problem is especially critical due to the extended length of word lines. Diffusion of silicon from the bottom polysilicon layer to the top conductor layer increases the resistivity of the two-layer stack. When silicon diffuses through the stack, it reacts with the conductor layer elements, increasing the resistivity of the conductor layer. When the conductor layer is formed of a metal, suicides are formed, which have a higher resistivity than pure metal. 
     One previous unsuccessful attempt to solve this diffusion problem introduces a third layer, which acts as a diffusion barrier, between the silicon and conductor layers. For example, a silicon nitride layer is used as the third layer in a two-layer stack. However, the silicon nitride diffusion barrier layer of Ito et al. (IEEE Transactions on Electron Devices, ED-33 (1986), 464 and U.S. Pat. No. 4,935,804) is difficult to employ because it must be ultrathin (less than 3 nanometers thick) to allow tunneling of charges through the layer, yet thick enough to act as a reaction barrier between the polysilicon and conductor layer elements. 
     Another diffusion barrier used in the past is comprised of a titanium nitride layer interposed between a two-layer stack. The conductive titanium nitride barrier layer of Pan et al. (IBM General Technology Division, “Highly Conductive Electrodes for CMOS”) attempts to solve the problems of Ito et al., but it requires a special source/drain (S/D) oxidation process when forming oxide spacers to maintain gate oxide layer integrity. A special process is required due to the tendency for tungsten and titanium nitride to oxidize, resulting in degradation of these layers. This adds time and cost to the fabrication process. 
     In ultra large scale integrated (ULSI) circuits, a highly conductive word line is necessary to improve circuit density and performance. In order to maintain a highly conductive word line, it is necessary to provide an effective method for decreasing diffusion within the two-layer stack. As devices are scaled down in size, word line widths are also decreased. While smaller line widths result in a decreased amount of resistance, this decrease is more than offset by an increase resistance due to the longer length of word lines. To date, word line resistance is one of the primary limitations of achieving faster ULSI circuits. A method for decreasing the resistivity of word lines is needed for use in ULSI applications. 
     In addition to creating a diffusion barrier layer in a two-layer word line stack, another way of decreasing resistance in a word line is by forming a high conductivity film on the word line. Such films are commonly formed of a refractory metal silicide, such as titanium suicide (TiSi 2 ). Titanium is preferably used as the refractory metal component because it has the ability to reduce oxygen, which remains on surfaces in the form of native oxides. Native oxides are reduced to titanium oxide by titanium. Native oxides degrade interface stability, and often cause device failure if not removed. 
     Due to the increased sensitivity of ULSI circuits, it is important to maintain low resistivity in ULSI devices. There is a need for a method of preventing diffusion between the two layers in a semiconductor word line stack, in order to prevent a reduction in the conductivity in the word line stack. The method for decreasing such diffusion preferably should be compatible with other ways of decreasing resistivity in a word line stack. 
     SUMMARY OF THE INVENTION 
     A method for forming a word line, which is used in ultra-large scale integrated (ULSI) circuits, produces a lower resistivity word line than that formed using prior art techniques. A doped silicon diffusion barrier formed in the word line stack prevents diffusion from a bottom silicon layer to a conductor layer in a word line stack, which results in degradation of the word line stack, increasing its resistivity. Oxygen or nitrogen is used for the dopant. Compared to dielectric diffusion barriers, oxygen or nitrogen doped silicon has a significantly lower resistance. Furthermore, such dopants improve the thermal stability of the conductor layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A to  1 G are cross-sectional representations of a word line stack formed in accordance with the method of the invention. 
    
    
     DETAILED DESCRIPTION 
     A word line is formed for use in ultra-large scale integrated (ULSI) circuits. While the invention is described with reference to it being a word line, other conductors may also be formed for various purposes, especially where reduced resistance is needed. The forming of diffusion barriers using oxygen or nitrogen in a word line stack is used to prevent diffusion from a bottom silicon layer to a conductor layer. 
     Doped Silicon Diffusion Barrier 
     According to one aspect of the invention, a doped silicon diffusion barrier region is formed prior to formation of a conductor layer, and subsequent to formation of a bottom silicon layer, to form a word line stack. In a first embodiment of the invention, a conventional p-type silicon substrate  210  is provided and a conventional (i.e., a thin layer of SiO 2 ) gate oxide layer  212  is grown by standard techniques, as shown in FIG.  1 A. After gate oxide  212  growth, a polysilicon (or amorphous silicon) “bottom silicon” layer  214  of thickness from approximately 50 to 300 nanometers is deposited on the gate oxide layer  212 , as shown in FIG.  1 B. This bottom silicon layer  214  is doped with conventional dopants (such as, but not limited to, arsenic, phosphorous, and boron), or it can be a layer of undoped, intrinsic material. Regardless of composition, the bottom silicon layer  214  is manufactured according to known techniques in order to guarantee good electrical properties at the interface between the gate oxide layer  212  and the bottom silicon layer  214 . 
     Next, a thin layer  216  of oxygen, or nitrogen, doped polysilicon (or amorphous silicon) material is formed on the bottom layer  214 , as shown in FIG.  1 C. This “doped silicon” film  216  is formed in one of two ways. The first way is by deposition (either in-situ or non-in-situ), using chemical vapor deposition (CVD). CVD takes on many different forms, including low pressure chemical vapor deposition (LPCVD), ambient pressure chemical vapor deposition (APCVD), and plasma enhanced chemical vapor deposition (PECVD). However, any form of CVD or sputtering can be used. The second way to form the “doped silicon film”  216  is by implantation of oxygen or nitrogen into the exposed surface of the bottom silicon layer  214  to form oxygen-doped or nitrogen-doped polysilicon or oxygen-doped or nitrogen-doped amorphous silicon. 
     The interface between the bottom silicon layer  214  and the doped silicon layer  216  can be abrupt, or gradual, with respect to the oxygen, or nitrogen, distribution, as shown in FIG.  1 C. The thickness of the doped silicon layer  216  ranges from approximately 5 to 100 nanometers, and the concentration of oxygen, or nitrogen, ranges from between approximately 1×10 17 atoms/cm 3  to 5×10 21  atoms/cm 3 . However, the required doped silicon layer  216  thickness and dopant concentration depend on the if total thermal budget of subsequent processes, and are selected according to known principles. 
     Then, as shown in FIG. 1D, a conductor layer  218  (preferably, but not necessarily, composed of tungsten, titanium silicide (TiSi x ), or other conventional materials) of between approximately 50 to 200 nanometers thick is deposited on the doped silicon layer  216  by conventional techniques, such as sputtering, or CVD. If an intrinsic bottom silicon layer  214  of polysilicon is used, ion implantation of arsenic, phosphorous, or boron is performed after creation of the bottom silicon layer  214 , after creation of the doped silicon layer  216 , or after creation of the conductive layer  218 . 
     The presence of oxygen, or nitrogen, doped polysilicon inhibits silicon diffusion from the bottom polysilicon layer  214  to the conductor layer  218 . Furthermore, it improves the thermal stability of the conductor film  218 . Compared to a polysilicon film that is not doped with oxygen or nitrogen, the oxygen or nitrogen-doped polysilicon film  216  has a higher resistance value. However, compared to a dielectric film, the oxygen or nitrogen doped polysilicon film  216  has a significantly lower resistance, and thus provides good electrical conduction between the conductive layer  218  and the bottom polysilicon layer  214 . 
     Finally, a cap  220  of one or more dielectric materials, such as silicon oxide or silicon nitride, is formed, if needed, according to conventional techniques, as shown in FIG.  1 E. Conventional photo mask and dry etch processes then define a word line stack. After wafer cleaning, spacers  222  are formed alongside the word line stack  236 , as shown in FIG.  1 F. Then, source/drain (S/D) implantation forms doped S/D regions  260  aligned with the spacers  222 , as shown in FIG.  1 G. 
     The resultant word line structure is comprised of: a conductor layer  218 ; an oxygen or nitrogen, doped polysilicon (or amorphous silicon) region  216 ; and a polysilicon (or amorphous silicon) layer  214 , as shown in FIGS. 1A to  1 G. The conductor layer  218  provides low resistivity. The oxygen, or nitrogen, doped region  216  eliminates (or reduces) agglomeration of the C54-TiSi 2  high temperature phase at interfaces between the low temperature C49-TiSi 2    218  and polysilicon (or amorphous silicon)  214  during subsequent process heat cycles. The bottom polysilicon (or amorphous silicon) layer  214  provides stable gate oxide interface electrical properties. 
     Conclusion 
     Numerous further embodiments will be apparent to one skilled in the art. Different embodiments of the invention can be applied simultaneously to further decrease the resistivity of a word line. The above described embodiments are examples only, and are not meant to be read in a limiting sense. While the invention has been described for use in the formation of low resistivity word line structures, other conductive structures, such as column lines or other conductors between components on a chip may be formed using the invention.