Abstract:
An apparatus with load dump protection incorporates first and second half-bridge circuits, first and second comparators, and first and second clamping circuits. The first comparator compares a supply voltage with a first set voltage and generates a first comparison signal while the supply voltage exceeds the first set voltage. The second comparator compares the supply voltage with a second set voltage and generates a second comparison signal while the supply voltage exceeds the second set voltage. The first clamping circuit divides the supply voltage and provides a divided voltage to the first half-bridge circuit in response to the second comparison signal. The second clamping circuit divides the supply voltage and provides a divided voltage to the second half-bridge circuit in response to the second comparison signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
       [0001]    The present invention relates generally to an electronic apparatus, and more particularly to an electronic apparatus having a load dump protection circuit. 
       2. Description of the Related Art 
       [0002]    In an automotive application, abnormal conditions, such as load dump situations, surge pulses or voltage transients, may occur on power supplies. 
         [0003]    When a load dump occurs, a surge voltage higher than 100V is applied to an electronic apparatus. In order to protect against high voltage, a protection circuit is required to protect devices of the system from permanent damage during a load dump. 
       SUMMARY OF THE INVENTION 
       [0004]    One aspect of the present invention is to provide an apparatus for driving a load between first and second output nodes. The apparatus comprises a first half-bridge circuit, a second half-bridge circuit, a first comparator, a second comparator, a first clamping circuit, and a second clamping circuit. The first half-bridge circuit comprises first and second transistors connected in series between a supply voltage and a reference voltage, with the first output node between the first and second transistors. The second half-bridge circuit comprises third and fourth transistors connected in series between the supply voltage and the reference voltage, with the second output node between the third and fourth transistors. The first comparator is configured to compare the supply voltage with a first set voltage and generate a first comparison signal while the supply voltage exceeds the first set voltage. The second comparator is configured to compare the supply voltage with a second set voltage and generate a second comparison signal while the supply voltage exceeds the second set voltage. The first clamping circuit is configured to divide the supply voltage and provide a first divided voltage at the first output node in response to the second comparison signal. The second clamping circuit is configured to divide the supply voltage and provide a second divided voltage at the second output node in response to the second comparison signal. The second set voltage is larger than the first set voltage. The first, second, third, and fourth transistors are turned off in response to the first comparison signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The invention will be described according to the appended drawings in which: 
           [0006]      FIG. 1  shows a block diagram of an electronic apparatus according to one embodiment of the present invention; 
           [0007]      FIG. 2  illustrates a detailed circuit diagram of the clamping circuits shown in  FIG. 1  according to one embodiment of the present invention; 
           [0008]      FIG. 3  illustrates a detailed circuit diagram of the clamping circuits shown in  FIG. 1  according to another embodiment of the present invention; 
           [0009]      FIG. 4  shows a block diagram of the electronic apparatus according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0010]      FIG. 1  shows a block diagram of an electronic apparatus  100  according to one embodiment of the present invention. In this embodiment, the electronic apparatus  100  includes a class-D amplifier for driving a load  12 . Class-D amplifiers are commonly used as speaker drivers in consumer, automotive and mobile applications. Referring to  FIG. 1 , the apparatus  100  comprises the class D amplifier with an H-bridge output stage. The H-bridge output stage consists of two complementary half-bridge output stages  14  and  15 . One half-bridge output stage  14  has a high-side transistor M 1  and a low-side transistor M 2  connected in series between a supply potential VDD and a supply potential GND, and the other half-bridge output stage  15  has a high-side transistor M 3  and a low-side transistor M 4  connected in series between the power supply potential VDD and the supply potential GND. The half-bridge output stage  14  has a non-inverting output OUTP and the half-bridge output stage  15  has an inverting output OUTN. 
         [0011]    The apparatus  100  further comprises two clamping circuits  16  and  18 , wherein the clamping circuits  16  and  18  are connected between the power supply potential VDD and the supply potential GND. The clamping circuit  16  is used to divide the power supply potential VDD and provide a divided voltage at the output OUTP of the half-bridge output stage  14 . The clamping circuit  18  is used to divide the power supply potential VDD and provide a divided voltage at the output OUTN of the half-bridge output stage  15 . 
         [0012]    The apparatus  100  further comprises two comparators  20  and  22 . The comparator  20  is used to compare the power supply potential VDD with a set voltage VC 1  to generate a comparison signal CP 1 . The comparator  22  is used to compare the power supply potential VDD with a set voltage VC 2  to generate a comparison signal CP 2 . The comparison signal CP 1  determines whether the transistors M 1 , M 2 , M 3  and M 4  of the H-bridge output stage are in OFF states, and the comparison signal CP 2  determines whether the clamping circuits  16  and  18  are enabled. 
         [0013]    Under normal conditions, that is, when the power supply potential VDD is not higher than a first predetermined voltage (e.g. 22V), current flows through the load  12  from left to right if the transistor M 1  of the half-bridge output stages  14  and the transistor M 4  of the half-bridge output stages  15  are turned on and the transistor M 2  of the half-bridge output stages  14  and the transistor M 3  of the half-bridge output stages  15  are turned off. Current flows through the load  12  from right to left if the transistor M 2  of the half-bridge output stages  14  and the transistor M 3  of the half-bridge output stages  15  are turned on and the transistor M 1  of the half-bridge output stages  14  and the transistor M 4  of the half-bridge output stages  15  are turned off. 
         [0014]    When a load dump occurs, the power supply potential VDD rises above the first predetermined voltage for a short time. If the power supply potential VDD exceeds the first predetermined voltage, the comparator  20  generates the comparison signal CP 1 . The comparison signal CP 1  transmits to a driver  11  to turn off the transistors M 1 , M 2 , M 3  and M 4  of the H-bridge output stage so as to protect the devices of the apparatus  100 . Thereafter, if the power supply potential VDD rises above a second predetermined voltage higher than the first the predetermined voltage (e.g. VDD&gt;28V), a protection mechanism for the transistors M 1 , M 2 , M 3  and M 4  in the OFF states is activated by enabling the clamping circuits  16  and  18 . 
         [0015]    When the power supply potential VDD rises above the second predetermined voltage, the comparator  22  generates the comparison signal CP 2 . The comparison signal CP 2  transmits to the clamping circuit  16  to clamp the voltage at the output OUTP of the half-bridge output stage  14  and transmits to the clamping circuit  18  to clamp the voltage at the output OUTN of the half-bridge output stage  15 .  FIG. 2  illustrates a detailed circuit diagram of the clamping circuits  16  and  18  shown in  FIG. 1  according to one embodiment of the present invention. Referring to  FIG. 2 , the clamping circuit  16  comprises a plurality of resistors R 1  and R 2  serially connected to the power supply potential VDD through a transistor M 5 , the clamping circuit  18  comprises a plurality of resistors R 3  and R 4  serially connected to the power supply potential VDD through a transistor M 6 . 
         [0016]    The detailed operations of the clamping circuits  16  and  18  are described below with respect to  FIG. 1  and  FIG. 2 . When the power supply potential VDD rises above the second predetermined voltage, the transistors M 5  and M 6  turn on. Since the ON-resistance value of the transistor M 5  is significantly smaller than the total resistance values of the resistors R 1  and R 2 , the clamping circuit  16  generates a divided voltage according to a resistance ratio of the resistors R 1  and R 2 ; and since the ON-resistance value of the transistor M 6  is significantly smaller than the total resistance values of the resistors R 3  and R 4 , the clamping circuit  18  generates a divided voltage according to a resistance ratio of the resistors R 3  and R 4 . 
         [0017]    Referring to  FIG. 1  and  FIG. 2 , when the power supply potential VDD rises above the first predetermined voltage, the transistors M 1 , M 2 , M 3  and M 4  of the H-bridge output stage are turned off. However, if the power supply potential VDD continues to raise, such high voltage may cause the transistors M 1 , M 2 , M 3  and M 4  to experience drain-source voltages in excess of their rated drain-source breakdown voltage (BVdss). Therefore, the clamping circuits  16  and  18  are enabled to clamp the drain-source voltages of the transistors M 1 , M 2 , M 3  and M 4 . Referring to  FIG. 2 , in one embodiment, the resistance ratio of the resistors R 1  and R 2  is set to be 1:1, and the resistance ratio of the resistors R 3  and R 4  is set to be 1:1. Therefore, the clamping circuit  16  generates a divided voltage by dividing the supply potential VDD at a ratio of 2, and the clamping circuit  18  generates a divided voltage by dividing the supply potential VDD at a ratio of 2. 
         [0018]    The clamping circuits  16  and  18  shown in  FIG. 2  are resistor dividers. However, it should be obvious that the present invention is not limited to this configuration. Referring to  FIG. 3 , the clamping circuits  16 ′ and  18 ′ can be capacitive dividers. When the transistors M 7  to M 10  turn on, the clamping circuit  16 ′ generates a divided voltage at the output OUTP according to a capacitance ratio of the capacitors C 1  and C 2 , and the clamping circuit  18 ′ generates a divided voltage at the output OUTN according to a capacitance ratio of the capacitors C 3  and C 4 . Therefore, the drain-source voltages of the transistors M 1 , M 2 , M 3  and M 4  are limited by the clamping circuits  16 ′ and  18 ′. Furthermore, the drain-source voltages of the transistors M 1  and M 2  in the OFF states can be varied by adjusting the capacitance ratio of the capacitors C 1  and C 2 , and the drain-source voltages of the transistors M 3  and M 4  in the OFF states can be varied by adjusting the capacitance ratio of the capacitors C 3  and C 4 . 
         [0019]    Referring to  FIG. 1 , the transistors M 1  and M 3  of the H-bridge output stage are P-channel MOSFETs, and the transistors M 2  and M 4  of the H-bridge output stage are N-channel MOSFETs. However, it should be obvious that the present invention is not limited to this configuration. Referring to  FIG. 4 , the transistors M 1 ′, M 2 ′, M 3 ′, and M 4 ′ of the H-bridge output stage are all N-channel MOSFETs. In this embodiment, bootstrap capacitors (not show) are used to boost the voltage at the gate of the high-side transistor M 1 ′ of the half-bridge output stage  14 ′ and boost the voltage at the gate of the high-side transistor M 3 ′ of the half-bridge output stage  15 ′. When a load dump occurs, if the power supply potential VDD rises above the first predetermined voltage, the transistors M 1 ′, M 2 ′, M 3 ′, and M 4 ′ of the H-bridge output stage are turned off first. If the power supply potential VDD continues to rise, the clamping circuits  16 ′ and  18 ′ are enabled to clamp the drain-source voltages of the transistors M 1 ′, M 2 ′, M 3 ′, and M 4 ′, so that the devices can be protected from damage. 
         [0020]    The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the invention as recited in the following claims.