Abstract:
A current mode DC-DC controller operates with high efficiency even when the input and output voltages are close. Switches selectively connecting an input, ground and an output to inductor terminals are controlled in a buck/boost region to alternate between operation as a buck converter and operation as a boost converter. The number of switches repeatedly changing state is thus reduced, lowering switching losses and improving conversion efficiency. Current through the inductor during operation is sensed and compared to an error value to control switching from buck mode operation to boost mode operation and back.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) AND CLAIM OF PRIORITY 
     The present application claims the benefit under 35 U.S.C. §119 to an application filed in the Chinese Intellectual Property Office on Dec. 31, 2009 and assigned Application No. 200910265997.2, the contents of which are herein incorporated by reference. 
     TECHNICAL FIELD 
     The present disclosure is directed, in general, to DC-DC controllers, and more specifically, to a current mode DC-DC controller having high efficiency even when generating a desired output voltage that is close to the input voltage. 
     BACKGROUND 
     Conversion of a direct current (DC) power supply voltage to a different voltage is employed for various purposes, including for example charging batteries or providing power to selected components within a computer, mobile telephone, or other electronic device. A versatile DC-DC controller should operate as either a “buck” (step-down) controller or a “boost” (step-up) controller, depending on the specific needs of the application, and should preferably operate across a complete range of input-output conversions without discontinuities. However, when changing a power supply voltage to a voltage that is close to that of the power supply, conversion efficiency (the power retained after conversion—that is, the input power less conversion losses) can be unacceptably low. 
     There is, therefore, a need in the art for an improved DC-DC controller with high efficiency even when generating a desired output voltage that is close to the input voltage. 
     SUMMARY 
     A current mode DC-DC controller operates with high efficiency even when the input and output voltages are close. Switches selectively connecting an input, ground and an output to inductor terminals are controlled in a buck/boost region to alternate between operation as a buck converter and operation as a boost converter. The number of switches repeatedly changing state is thus reduced, lowering switching losses and improving conversion efficiency. Current through the inductor during operation is sensed and compared to an error value to control switching from buck mode operation to boost mode operation and back. 
     Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
         FIG. 1A  is a simplified circuit diagram of a high efficiency current mode DC-DC controller in accordance with one embodiment of the present disclosure; 
         FIG. 1B  illustrates ranges of operation for the current mode DC-DC controller of  FIG. 1A ; 
         FIG. 2A  is a more detailed circuit diagram of the current mode DC-DC controller of  FIG. 1A ; 
         FIG. 2B  illustrates selected signals during operation of the current mode DC-DC controller of  FIG. 1A  in the buck/boost region of  FIG. 1B ; 
         FIG. 3  illustrates an application of a high efficiency current mode DC-DC controller in accordance with one embodiment of the present disclosure; and 
         FIGS. 4A through 4C  are plots illustrating simulation results for operation of the controller application depicted in  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1A through 4C , discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system. 
       FIG. 1A  is a simplified circuit diagram of a high efficiency current mode DC-DC controller in accordance with one embodiment of the present disclosure. Controller  100  includes switches A and C connected in series between an input voltage V IN  and ground, and switches B and D connected in series between an output voltage V OUT  and ground. An inductor L 0 , shown as an external inductor connected between integrated circuit package input/output (I/O) connections SW 1  and SW 2 , is connected from the common node between switches A and C and the common node between switches B and D. (Inductor L 0  is shown in phantom since it is preferably external to the integrated circuit package containing controller  100 , as illustrated below in  FIG. 3 ). Within the exemplary embodiment illustrated, switches A and B may be implemented as p-channel metal oxide semiconductor (pMOS) field effect transistors (FETs) and switches C and D may be implemented as n-channel metal oxide semiconductor (nMOS) FETs. 
       FIG. 1B  illustrates ranges of operation for the current mode DC-DC controller of  FIG. 1A . When the input voltage V IN  is much higher than the desired output voltage V OUT , between minimum and maximum differentials Δ min, buck  and Δ max, buck , the controller  100  works in the buck (step-down) region. In the buck region, switch B may be kept on (closed), switch D may be kept off (open) and switches A and C may be controlled by a PWM signal to achieve the required voltage conversion. When the input voltage V IN  is much lower than the desired output voltage V OUT , between minimum and maximum differentials Δ min, boost  and Δ max, boost , the controller  100  works in the boost (step-up) region. In the boost region, switch A may be kept on, switch C may be kept off, and switches B and D are controlled by a PWM signal. In both cases, only two switches are repeatedly changing state and switching losses are therefore sufficiently low to allow conversion with acceptably high efficiency (greater than 90%). 
     However, when the input voltage V IN  is close to the desired output voltage V OUT  (the “buck/boost region” in  FIG. 1B ), in a voltage mode implementation all four switches A, B, C and D are typically controlled by a PWM signal, substantially increasing switching losses and resulting in unacceptable conversion efficiency. To avoid such switching losses, the current mode DC-DC controller  100  alternates between operation as a buck controller and operation as a boost controller when the input voltage V IN  is close to the desired output voltage V OUT . Thus, within the buck/boost region, the current mode controller  100  alternates between operating with switches A and C controlled by a PWM signal and operating with switches B and D controlled by a PWM signal. In that manner, only two switches are regularly changing state (except during transitions between buck and boost operation) and the conversion efficiency will be higher than a voltage mode implementation. 
       FIG. 2A  is a more detailed circuit diagram of the current mode DC-DC controller of  FIG. 1A . Controller  100  receives the input voltage at the input V IN , which is connected to the drain of a pMOS FET M 0  (corresponding to switch A in  FIG. 1A ). The drain of transistor M 0  is connected to a terminal SW 1 . A current sensing resistor R S  and a transistor M 1  are serially connected in parallel with transistor M 0 , with one terminal of the resistor R S  connected to the input V IN , the other terminal of the resistor R S  connected to the drain of transistor M 1 , and the source of transistor M 1  connected to terminal SW 1 . The gates of transistors M 0  and M 1  are connected together and controlled in tandem by control logic  201 . 
     A terminal SW 2  is connected to the drain of a pMOS FET M 2  (corresponding to switch B in  FIG. 1A ), and the source of transistor M 2  is connected to output V OUT . The drain of nMOS FET M 3  (corresponding to switch C in  FIG. 1A ) is connected to terminal SW 1 , and the drain of nMOS FET M 4  (corresponding to switch D in  FIG. 1A ) is connected to terminal SW 2 . The sources of transistors M 3  and M 4  are both connected to ground. The gates of transistors M 2 , M 3  and M 4  are separately controlled, and controlled separately from the gates of transistor M 0  and M 1 , by control logic  201 . An inductor L 0  is connected between terminals SW 1  and SW 2 . Control logic  201  controls transistors M 0 , M 1 , M 2 , M 3  and M 4  to operate, together with inductor L 0 , in different modes as a boost converter, as a buck converter, or as an alternating buck/boost converter as described in further detail below. 
     An operational amplifier (op-amp) I SEN  has the inverting input connected to one terminal of resistor R S  and the non-inverting input connected to the other terminal of resistor R S , generating a generally sawtooth output voltage V SUM  corresponding to pulses applied to the gates of transistors M 0  (and M 1 ) and M 3  by control logic  201  (or pulses applied to the gates of transistors M 2  and M 4 , with transistor M 0  kept on). The output of op-amp I SEN  is supplied to the inverting inputs of comparators COMP 1  and COMP 2 , with control voltages VC 1  and VC 2  supplied to the non-inverting inputs of comparators COMP 1  and COMP 2 , respectively. The outputs of comparators COMP 1  and COMP 2  are control voltages V RST1  and V RST2 , respectively, and are supplied to control logic  201 . The output V SUM  of op-amp I SEN  is also applied to a voltage-controlled oscillator  202 , the output of which is supplied to control logic  201 . 
     Control voltages VC 1  and VC 2  are produced based on a reference voltage V REF  and a feedback voltage V FB  applied to the non-inverting and inverting inputs, respectively, of an error amplifier EA. Before being supplied to the non-inverting input, reference voltage V REF  is first filtered by a resistive-capacitive soft-start circuit  203  that inhibits excessive power dissipation when the controller  100  is powered up from a non-powered state. The feedback voltage V FB  is produced by driving an external resistor using the output V OUT . The output of error amplifier EA is control voltage VC 1 , and is passed through a DC level shifter  204  to produce control voltage VC 2 . 
     A discontinuous mode detection amplifier DMD is connected at the non-inverting input to the drain of transistor M 2  and at the inverting input to the source of transistor M 2 . The output of amplifier DMD is supplied to control logic  201 . 
     Those skilled in the relevant art will recognize that the full structure and operation of the high-efficiency current mode DC-DC controller is not depicted in the drawings or described herein. Instead, for simplicity and clarity, only so much of the structure and operation as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. For example, the particular circuits enabling the DC-DC controller to operate simply as a buck converter in one mode or as a boost converter in another mode are not depicted or described in greater detail than is found in  FIGS. 1A and 1B  and the accompanying description. Nonetheless, those skilled in the relevant art will be able to readily implement such modes of operation. 
       FIG. 2B  illustrates selected signals during operation of the current mode DC-DC controller of  FIG. 1A  in the buck/boost region of  FIG. 1B . Based on the sawtooth voltage V SUM  output by current sensing op-amp I SEN , error-based feedback control voltage VC 1  increases during a buck phase of the alternative buck-boost operation from a minimum level to a level equaling or exceeding the maximum value of current sensing output V SUM . The controller  100  then switches to boost operation, with error-based (and level shifted) feedback control voltage VC 2  increasing during the boost phase of buck-boost operation from a minimum level to a level equaling or exceeding the maximum value of current sensing output V SUM . The controller  100  then switches back to buck operation, and the cycle repeats. The pulse widths for the result V RST1  of comparing V SUM  with VC 1  increase with consecutive cycles of V SUM  as VC 1  increases, and the pulse widths for the result V RST2  of comparing V SUM  with VC 2  increase with consecutive cycles of V SUM  as VC 2  increases. While not expressly depicted, it should be apparent to those skilled in the art that control logic  201  may include latches that are set and reset by signals V SET  from oscillator  202 , V RST1  from comparator COMP 1  and V RST2  from comparator COMP 2 , with the latches controlling switching between buck and boost phases of operation. 
       FIG. 3  illustrates an application of a high efficiency current mode DC-DC controller in accordance with one embodiment of the present disclosure. Application  300  includes controller  100  of  FIGS. 1A and 2A  implemented within a single integrated circuit package, with inductor L 0  connected between input/output connections SW 1  and SW 2 . An input/output connection VIN for receiving the input voltage V IN  is coupled by a capacitor CIN to ground, and an input/output connection V OUT  for outputting the output voltage V OUT  is coupled by a capacitor COUT to ground. The input/output connection VOUT is also coupled to ground by a voltage divider formed by resistors R 1  and R 2 , with an input/output connection VFB for receiving the feedback voltage V FB  connected to the junction between resistors R 1  and R 2 . 
       FIGS. 4A through 4C  are plots illustrating simulation results for operation of the controller application depicted in  FIG. 3 . An inductance of 2.2 micro-Henries (μH) was selected for inductor L 0  and a capacitance of 10 micro-Farads (μF) was selected for the output capacitor COUT. Within each set of plots: the top trace  501  depicts the input signal V IN ; the second trace  502  illustrates current I through the inductor L 0  between terminals SW 1  and SW 2 ; the third trace  503  illustrates the output voltage V OUT ; and the fourth and fifth traces  504  and  505  illustrate the voltages at terminals SW 1  and SW 2 , respectively. 
       FIG. 4A  illustrates simulation results for an input voltage V IN  of 2.4 volts (V) and an output voltage V OUT  of 3.3 V, and thus corresponds to operation in the boost region of  FIG. 1B . A conversion efficiency of 94.1% is achieved.  FIG. 4B  illustrates simulation results for an input voltage V IN  of 3.6 V and an output voltage V OUT  of 3.3 V, corresponding to operation in the buck/boost region of  FIG. 1B  with a conversion efficiency of 93.1%.  FIG. 4C  illustrates simulation results for an input voltage V IN  of 4.2 V and an output voltage V OUT  of 3.3 V, corresponding to operation in the buck region of  FIG. 1B  with a conversion efficiency of 95%. 
     The current-mode DC-DC controller described above achieves high conversion efficiency regardless of how close the desired output voltage is to the input voltage. The design also eliminates the need for external compensation, and required very few external components, such that reduced printed circuit board (PCB) area is required. 
     Although the above description is made in connection with specific exemplary embodiments, various changes and modifications will be apparent to and/or suggested by the present disclosure to those skilled in the art. It is intended that the present disclosure encompass all such changes and modifications as fall within the scope of the appended claims.