Abstract:
An electronic chip including a semiconductor substrate ( 1 ) covered with an insulating layer ( 4 ) including metal interconnection levels ( 3 ) and interconnection pillars ( 10 ) connected to said metal interconnection levels ( 3 ), said pillars ( 110 ) forming regions ( 111 ) protruding from the upper surface of said insulating layer ( 4 ) and capable of forming an electric contact, wherein said pillars ( 110 ) have a built-in portion ( 115 ) in a housing formed across the thickness of at least said insulating layer ( 4 ).

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to microelectronics. It more specifically relates to specific layouts involving interconnection pillars which are formed on the chip surfaces to enable their connection with adjacent chips or with packages. 
       BACKGROUND 
       [0002]    Generally, electronic components may comprise several integrated circuits formed within separate chips, which are associated inside of a same package. It is necessary to form electric connections between the different tracks of the chips which need to be interconnected, as well as between the chips and the different electric tracks which come out of the package. 
         [0003]    A solution used is to create, inside of the chip substrate layer, through interconnection vias which are formed of a conductive material, such as copper or the like. 
         [0004]    On one side, the vias are connected to the tracks of the internal functional areas of the integrated circuit. At their other end, the vias emerge on one of the chip surfaces. These vias may be present on the upper surface side of the chip, or “front” side, that is, on the side where the substrate comprises active areas where transistors or the like are implanted. Frequently, however, these vias emerge on the opposite surface, or “back side” of the chip. 
         [0005]    It is also possible to form connection areas on the front surface side of the chip, by forming connection areas connected to one of the metallization levels, generally the upper metallization level, formed in the insulating layer (or “back-end” layer) which covers the substrate. This insulating layer comprising metallization levels should not be mistaken for the passivation layer separating the metallization levels and the metal areas forming contact pads from the conducting layers forming a redistribution line (RDL), which are sometimes placed on top of the “back-end” layer. 
         [0006]    Protruding areas are created on one and/or the other of the chip surfaces. They are arranged to be, on the one hand, connected to the interconnection vias or to the metallization level and, on the other hand, to be able to be soldered to the adjacent chips or to the package. 
         [0007]    A known embodiment comprises using, as protruding areas, metal balls or spheres, generally called bumps, which are deposited on the front and/or back sides of the chip, at the level of the appropriate areas, and which will come into contact with the connections of the adjacent chip. 
         [0008]    The bump technique has been progressively replaced with a so-called interconnection pillar technique, to increase the density of connection points. Indeed, bumps have a spherical geometry, whereby their bulk compared with the effective contact area crossed by the current is not optimal. 
         [0009]    Conversely, interconnection pillars have a cylindrical geometry, which makes it possible to implant a larger number thereof per surface area unit. 
         [0010]    Such interconnection pillars are generally made of copper. They are formed by electrodeposition from seed layers deposited in appropriate areas of the surface of the involved chip. 
       SUMMARY 
       [0011]    Now, the Applicant has observed that certain operations, in the context of the chip manufacturing or of the association of different chips, may risk damaging interconnection pillars. 
         [0012]    Indeed, at certain chip manufacturing stages, it is necessary to work on the back side of the chip. To reach this back side, the chip must be manipulated by being associated by its front side to a mechanical support element having a much greater size than the chip. To achieve this, the front side of the chip is positively connected to a support element, also called “handle”, by means of an adhesive material. 
         [0013]    Once the operations on the back side have been carried out, the chip must be separated from the support element. 
         [0014]    This separation is performed by heating the adhesive and applying a transverse load, which causes the shearing of the adhesive layer and separates the chip from the support. In the case where the front surface comprises interconnection pillars, the Applicant has observed that the transverse load applied by this element in contact with the front surface can cause the tearing off of the interconnection pillars, or delaminations in the stack of metal interconnection layers of the chip, which may cause a failure of said chip. 
         [0015]    Further, in the case where the chip is transferred by its front side in a package (of BGA, or Ball Grid Array type) or directly on an electronic card, the Applicant has observed that the difference in thermal expansion coefficient between the chip silicon and the materials forming the package or the card, may stress the interconnection pillars, with the same risks as discussed hereabove. 
         [0016]    To decrease or suppress such risks, the Applicant has devised a new layout in terms of placing of the interconnection pillars. 
         [0017]    Thus, an embodiment of the present invention provides an electronic chip comprising a semiconductor substrate covered with an insulating layer comprising metal interconnection levels and interconnection pillars connected to said metal interconnection levels, said pillars forming regions protruding from the upper surface of said insulating layer, and capable of forming an electric contact, wherein said pillars have a built-in portion in a housing formed across the thickness of at least said insulating layer. 
         [0018]    According to different alternative embodiments, the housing may be formed across a fraction of the thickness of said insulating layer, or cross said insulating layer and a portion of the substrate thickness. 
         [0019]    In practice, the insulating layer may comprise a metal layer crossed by said housing. 
         [0020]    According to various embodiments, the cross-section of the built-in fraction of the interconnection pillar may be smaller than or identical to the cross-section of the protruding portion of said pillar. 
         [0021]    According to some embodiments, the housing may have an insulating layer interposed between, on the one hand, the material of the pillar and, on the other hand, the insulating layer and the substrate. 
         [0022]    Further, the pillar may have a shoulder coming into contact with said metal layer. 
         [0023]    In practice, the depth of the housing may range between approximately 20 and 50% of the height of the protruding portion of the pillar. 
         [0024]    As a complement, the present invention provides a method for manufacturing an electronic chip comprising a semiconductor substrate, covered with an insulating layer comprising metal interconnection levels, wherein at least one housing is formed across the thickness of at least said insulating layer, the forming of said housing exposing a fraction of said metal interconnection levels, and wherein an interconnection pillar is formed inside of each housing, said pillar coming into contact with said fraction of said metal interconnection levels, said pillar forming a region protruding from the upper surface of said insulating layer. 
         [0025]    According to various alternative embodiments, the housing is formed by crossing the entire thickness of said insulating layer, or a fraction only of the thickness of said insulating layer. 
         [0026]    In certain cases, it is advantageous to deposit a layer of insulating material in said housing before forming the interconnection pillar. 
         [0027]    The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]      FIG. 1  is a partial cross-section view of a chip comprising an interconnection pillar according to a first embodiment. 
           [0029]      FIGS. 2 to 13  are cross-section views similar to  FIG. 1  illustrating the different steps enabling to form the connection pillar illustrated in  FIG. 1 . 
           [0030]      FIG. 14  is a partial cross-section view of a chip comprising an interconnection pillar according to a second embodiment. 
           [0031]      FIGS. 15 to 19  are cross-section views similar to  FIG. 14 , illustrating the different steps enabling to form the connection pillar illustrated in  FIG. 14 . 
       
    
    
     DETAILED DESCRIPTION 
       [0032]    On manufacturing of an electronic chip, a functional area  2  is generally formed on one of the surfaces of a semiconductor wafer. This functional area comprises different transistors or the like necessary to implement the dedicated chip functions. Functional area  2 , formed in semiconductor substrate layer  1 , is connected to different metal interconnection levels  3  formed inside of an insulating layer, typically made of oxide or the like, and also called back-end layer. 
         [0033]    Functional area  2  has been shown in a simplified manner since it is not indispensable to the understanding of the present invention. 
         [0034]    The different metal interconnection levels  3  enable to form the connection between functional area  2  and the upper surface of back-end layer  4 . In its uppermost portion, back-end layer  4  supports metallized areas  5 , sometimes referred to as “pads”, typically formed of copper, aluminum, or the like, on which are formed the areas of connection with the adjacent elements, which may be other chips or packages, for example. 
         [0035]    Conventionally, the upper surface of back-end layer  4  is covered with a passivation layer  7 , which may be of various natures, for example, formed of a silicon nitride layer deposited on an oxide layer, itself doped, for example, with phosphorus. This passivation layer  7  should not be mistaken for the back-end layer  4 , comprising the metallization levels. Sometimes, conducting layers, known to a person skilled in the art as redistribution lines (RDL), not shown in any of the drawings enclosed, are formed on top of this passivation layer. These conducting layers ensure a better electric contact between the pads  5  and the pillars or bumps that can be found in the prior art. 
         [0036]    In the embodiment illustrated in  FIG. 1 , the chip comprises an interconnection pillar  10 , which has an apparent portion  11  above passivation layer  7 . This apparent portion is topped with a dome  12  intended to ease the soldering to the adjacent elements, and typically based on a tin-silver alloy. 
         [0037]    Interconnection pillars  10  comprise a built-in fraction  15  inside of the chip and which crosses back-end layer  4  and a portion of substrate layer  1 . 
         [0038]    It should be noted that the width of built-in portion  15  shown in cross-section view is smaller than the width of apparent portion  11  of the pillar. This width difference defines a shoulder  16  which enables the pillar to rest on metal layer  5 , thus creating an electric contact between pillar  10  and interconnection levels  3 . 
         [0039]    In practice, the anchoring depth of pillar  10 , that is, the height of built-in portion  15 , ranges between approximately 20 and 50% of the height of apparent portion  11 , that is, the portion located above passivation layer  7 . 
         [0040]    Such a deep anchoring may be preferred for large interconnection pillars, that is, is typically, pillars having a diameter greater than 25 micrometers and having a height greater than 30 micrometers. 
         [0041]    Such an interconnection pillar may be formed according to a method illustrated in  FIGS. 2 to 13 . 
         [0042]    Thus, at a given stage of the chip manufacturing and as illustrated in  FIG. 2 , passivation layer  7  is etched above metallization layer  5  to define an opening  18  exposing a fraction of metallization layer  5 . 
         [0043]    In a second step illustrated in  FIG. 3 , a photolithography mask  19  is deposited, to be subsequently removed from an area  20  located above opening  18 , thus exposing metallization layers  5 . It should be noted that opening  20  is smaller than opening  18 , so that a portion of the resin mask covers peripheral portion  21  of opening  18 , to form the future area of electric contact with the pillar, corresponding to shoulder  16  illustrated in  FIG. 1 . 
         [0044]    In a subsequent step illustrated in  FIG. 4 , different etch steps enabling to remove the layers accessible through opening  20  are carried out. A first etching thus enables to remove metallization layer  5 . A second etching enables to remove the silicon oxide layer forming the back-end layer. A third step then enables to etch a fraction of the thickness of substrate layer  1  to thus form well  22 , which will form the housing of the built-in portion of pillar  10 . Resin layer  19  is then removed. 
         [0045]    In a subsequent step illustrated in  FIG. 5 , the assembly receives the deposition of an insulating layer, typically based on silicon oxide, which may advantageously be deposited by an SACVD (Sub Atmospheric Chemical Vapor Deposition) technique. 
         [0046]    It should be noted that this deposition is conformal, that is, it lines the sides of well  22 , thus enabling to create an insulation between, on the one hand, the materials which will then be deposited inside of the well and, on the other hand, the rest of the component and especially substrate layer  1 . 
         [0047]    In a subsequent step illustrated in  FIG. 6 , a resin mask  30  which partially closes well  22  is deposited. Resin layer  30  is then removed to be only kept in fraction  31  above well  22 . Resin fraction  31  enables to protect the sides of well  22 , and especially oxide layer  23 . In a subsequent step illustrated in  FIG. 8 , the oxide layer which had been deposited full wafer is then removed from the apparent portions. According to the type of oxide used, the etching may be dry or wet. As already mentioned, it remains within well  22 . 
         [0048]    In a subsequent step illustrated in  FIG. 9 , resin layer  31  is then removed to fully expose well  22  where the built-in portion of the pillar will be deposited later on. 
         [0049]    In a subsequent step illustrated in  FIG. 10 , a layer forming a barrier against the diffusion of copper  33 , which may typically be formed of tantalum and/or tantalum nitride, or even of titanium nitride, is deposited full-wafer. 
         [0050]    This layer is deposited by a physical vapor deposition method (PVD), for a thickness on the order of hundreds of nanometers. After, a copper seed layer  34  is deposited, also by PVD. 
         [0051]    It should be noted that due to the removal of insulator  23  from shoulder areas  21 , as previously illustrated in  FIG. 8 , conductive layers  33  and  34  are electrically connected to metallization layer  5 . 
         [0052]    Then, and as illustrated in  FIG. 11 , a resist mask  36  is deposited and then opened at the level of well  22  to form opening  37 . It should be noted that opening  37  exposes portions  21  of metallization layer  5  covered by conductive layers  33  and  34 , thus enabling to form the electric connection between the pillar and metallization level  5 , given that the vertical sides of well  22  are covered with an oxide layer  23  which partially covers the lateral sides of the opening formed in metallization layer  5 . 
         [0053]    After, and as illustrated in  FIG. 12 , a copper electrodeposition is carried out, by electric contacting at the wafer edges, at the level of seed layer  34 . 
         [0054]    The deposition of copper  40  is interrupted when the desired pillar height has been reached. The copper deposition is continued by the deposition of a conductive material of low melting point, typically a tin/silver alloy. Then, as illustrated in  FIG. 13 , resin mask  36  is removed to expose visible portion  11  of the pillar and tin/silver deposit  40 . 
         [0055]    Seed layer  34  and copper diffusion barrier layer  33  are then removed to expose initial passivation layer  7 . 
         [0056]    A subsequent anneal step enables to give tin/silver deposit 40 a dome shape such as illustrated in  FIG. 1 . 
         [0057]    According to another embodiment illustrated in  FIG. 14 , copper pillar  110  has a buried portion  115  with a cross-section similar to the cross-section of apparent portion  111 . Built-in portion  115  penetrates inside of back-end oxide layer  4 , without coming into contact with substrate layer  1 . 
         [0058]    Thereby, since back-end layer  4  is insulating by nature, it is not necessary to deposit an insulating layer inside of the housing receiving the pillar, as in the first embodiment. This has the advantage of simplifying the manufacturing process, in the case where the mechanical anchoring does not have to be extremely resistant. 
         [0059]    A manufacturing method for obtaining the structure of  FIG. 14  comprises, as illustrated in  FIG. 15 , a first step similar to that illustrated in  FIG. 2 , which comprises etching the passivation layer to expose a portion  118  of metallization layer  5 . 
         [0060]    In a second step illustrated in  FIG. 16 , apparent portion  118  of metallization layer  5  is exposed, after which back-end layer  4 , located underneath, is etched to define well  122 . It should be noted that well  122  has a width substantially identical to that of opening  18  formed on the passivation layer and does not penetrate into substrate  1 . 
         [0061]    In a subsequent step, a layer forming a barrier against the diffusion of copper is deposited by PVD, for example, after which a copper seed layer is deposited, both depositions being performed over the entire wafer surface. 
         [0062]    In a subsequent step illustrated in  FIG. 17 , a resin mask  136  is deposited, said resin mask having a recess  137  formed therein above well  122 . 
         [0063]    Then, in a subsequent step, an electrolytic deposition is performed to form copper pillar  110 , and for the subsequent deposition of materials of tin/silver type enabling to solder the pillar to other components or to the package. 
         [0064]    Then, in a step illustrated in  FIG. 19 , resin mask  136 , seed layers  134 , and diffusion barrier layer  133  are removed to disengage pillar  110 . 
         [0065]    A subsequent anneal step enables to give the silver/tin deposit a dome shape such as illustrated in  FIG. 14 . 
         [0066]    As appears from the foregoing, the described embodiments enable to provide an anchoring of the interconnection pillars, which very strongly decreases risks of tearing off under a transversal load and risks of delamination within the metal interconnection layers. According to the estimated stress level, it is thus possible to perform a particularly deep anchoring all the way to the inside of the semiconductor substrate layer. When the estimated stress level is lower, an anchoring in the back-end layer only may be sufficient, which enables to take advantage of a simplified pillar forming method. 
         [0067]    Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.