Abstract:
While a drain power source of a reset transistor and a drain power source of an amplifying transistor are separated, the load of drain power source can be reduced by sharing a drain diffusion layer of the reset transistor and a drain diffusion layer of the amplifying transistor by adjacent cells in sharing pixel units. Further, an efficient pixel layout is provided by reducing the number of routing wires.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-046478, filed on Mar. 3, 2011; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a solid state imaging apparatus. 
     BACKGROUND 
     In a CMOS image sensor seeking pixel miniaturization by adopting a multi-pixel shared structure, a method of reducing a drive load of pixels by installing a power source of each drain of a reset transistor and an amplifying transistor of the CMOS image sensor as a separate power source is known. 
     According to this method, compared with a case when the drain power source of the reset transistor and the drain power source of the amplifying transistor are driven by the same source, a capacity load of a vertical signal line becomes smaller so that a high-speed operation can be performed. In this method, however, a pulse enters the reset transistor of all pixels at the same time to drive the reset transistor and thus, the load of the drain power source of the reset transistor may become large. 
     The present patent is a patent that solves the above problem and further relates to an efficient pixel layout by sharing a drain diffusion layer of the reset transistor and a drain diffusion layer of the amplifying transistor by adjacent cells in different pixel sharing units to reduce the number of routing wires. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating an outline configuration of a solid state imaging apparatus according to a first embodiment; 
         FIG. 2  is a timing chart illustrating a read operation of the solid state imaging apparatus in  FIG. 1 ; 
         FIG. 3  is a plan view illustrating a layout configuration of a pixel array unit of the solid state imaging apparatus in  FIG. 1 ; 
         FIG. 4  is a block diagram illustrating the outline configuration of a solid state imaging apparatus according to a second embodiment; 
         FIG. 5  is a timing chart illustrating the read operation of the solid state imaging apparatus in  FIG. 4 ; 
         FIG. 6  is a plan view illustrating the layout configuration of a pixel array unit of the solid state imaging apparatus in  FIG. 4 ; 
         FIG. 7  is a block diagram illustrating the outline configuration of a solid state imaging apparatus according to a third embodiment; 
         FIG. 8  is a timing chart illustrating the read operation of the solid state imaging apparatus in  FIG. 7 ; 
         FIG. 9  is a plan view illustrating the layout configuration of a pixel array unit of the solid state imaging apparatus in  FIG. 7 ; 
         FIG. 10  is a block diagram illustrating the outline configuration of a solid state imaging apparatus according to a fourth embodiment; 
         FIG. 11  is a timing chart illustrating the read operation of the solid state imaging apparatus in  FIG. 10 ; and 
         FIG. 12  is a plan view illustrating the layout configuration of a pixel array unit of the solid state imaging apparatus in  FIG. 10 . 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to a solid state imaging apparatus in an embodiment, a cell, an amplifying transistor, a reset transistor, and a row scanning circuit are provided. The cell is provided with K (K is an integer equal to 2 or greater) pixels. The amplifying transistor is shared by the K pixels in the cell and amplifies a signal read from the pixels. The reset transistor is shared by the K pixels in the cell and resets a signal read from the pixels. The row scanning circuit drives the drains of the reset transistors in different rows separately. 
     Solid state imaging apparatuses according to the embodiments will be described below with reference to drawings. However, the present invention is not limited by these embodiments. 
     (First Embodiment) 
       FIG. 1  is a block diagram illustrating an outline configuration of a solid state imaging apparatus according to a first embodiment. 
     In  FIG. 1 , the solid state imaging apparatus has a cell UC 1  arranged in a matrix form in a row direction and a column direction. The cell UC 1  is provided with two photodiodes PD 1 , PD 2 , two read transistors Td 1 , Td 2 , one reset transistor Tc, one floating diffusion FD, and one amplifying transistor Tb. 
     Each of the photodiodes PD 1 , PD 2  can convert light from an object to be imaged into an electric signal in units of pixel. The read transistors Td 1 , Td 2  can read a signal photoelectrically converted by the photodiodes PD 1 , PD 2  respectively. The reset transistor Tc is shared by the photodiodes PD 1 , PD 2  and can reset a signal read from the photodiodes PD 1 , PD 2 . The floating diffusion FD is shared by the photodiodes PD 1 , PD 2  and can cause detection of a signal read from the photodiodes PD 1 , PD 2 . The amplifying transistor Tb is shared by the photodiodes PD 1 , PD 2  and can amplify a signal read from the photodiodes PD 1 , PD 2 . 
     The photodiodes PD 1 , PD 2  are vertically arranged side by side and the photodiode PD 1  can be arranged in an M (M is a positive integer)-th row and the photodiode PD 2  can be arranged in an (M+1)-th row. The floating diffusion FD is shared by the drains of the read transistors Td 1 , Td 2 . Sources of the read transistors Td 1 , Td 2  are connected to the photodiodes PD 1 , PD 2  respectively. The source of the reset transistor Tc is connected to the floating diffusion FD. 
     The cell UC 1  is arranged in such a way that a mirror image is formed with respect to cells adjacent to each other in the vertical direction. The drain of the reset transistor Tc and the drain of the amplifying transistor Tb of the cell UC 1  are shared by different cells adjacent to each other in the vertical direction. For example, the drain of the reset transistor Tc can be made to be shared with the adjacent cell above the cell UC 1  and the drain of the amplifying transistor Tb can be made to be shared with the adjacent cell below the cell UC 1 . 
     The solid state imaging apparatus is provided with a row scanning circuit  1  that scans pixels in units of row and also a vertical signal line VL that transmits a signal read from each pixel in units of column. A drain power source line HD, a reset control line HS, and read control lines HR 1 , HR 2  are connected to the row scanning circuit  1 . The read control lines HR 1 , HR 2  are provided for each row and connected to the read transistors Td 1 , Td 2  respectively. The reset control line HS is provided for every two rows and connected to the gate of the reset transistor Tc. The two reset control lines HS can be arranged adjacent to each other for every four pixels in the vertical direction. The drain power source line HD is provided for every four rows and connected to the gate of the reset transistor Tc. The drain power source line HD can be arranged between the two reset control lines HS arranged adjacent to each other. The row scanning circuit  1  can drive the drains of the reset transistors Tc in different rows separately. The row scanning circuit  1  can also drive the drain of the reset transistor Tc and the drain of the amplifying transistor Tb separately. For example, the row scanning circuit  1  can drive the drain of the reset transistor Tc from row to row. However, if the drain of the reset transistor Tc is shared by two pixels adjacent to each other in the vertical direction, the drain of the reset transistor Tc can be driven for every two rows. If the drain of the reset transistor Tc is shared by four pixels adjacent to each other in the vertical direction, the drain of the reset transistor Tc can be driven for every four rows. 
     The gate of the amplifying transistor Tb is connected to the floating diffusion FD, the source of the amplifying transistor Tb is connected to the vertical signal line VL, and the drain of the amplifying transistor Tb is connected to a drain power source AVDD. 
     The drain power source AVDD can commonly be connected to the drains of the amplifying transistors Tb of all the cells UC 1  in the solid state imaging apparatus. The voltage of the drain power source AVDD can be set to a fixed value. 
       FIG. 2  is a timing chart illustrating a read operation of the solid state imaging apparatus in  FIG. 1 . 
     In  FIG. 2 , if, for example, signals are to be read from pixels in the M-th row, the reset transistor Tc is turned on and a charge of the floating diffusion FD is reset by a reset signal RESET 2  being provided to the reset control line HS. Then, with the voltage in accordance with a reset level of the floating diffusion FD being applied to the gate of the amplifying transistor Tb and the voltage applied to the gate of the amplifying transistor Tb being followed by the voltage of the vertical signal line VL in an N (N is a positive integer)-th column, a pixel signal VSig 1  of the reset level is output to the vertical signal line VL in the N-th column. Incidentally, the amplifying transistor Tb can configure a source follower together with a load transistor connected to the vertical signal line VL. 
     Next, the read transistor Td 1  is turned on by a read signal READ 3  being provided to the read control line HR 1  and a charge detected by the photodiode PD 1  is transferred to the floating diffusion FD. Then, with the voltage in accordance with a signal level of the floating diffusion FD being applied to the gate of the amplifying transistor Tb and the voltage applied to the gate of the amplifying transistor Tb being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the signal level is output to the vertical signal line VL in the N-th column. 
     Next, the reset transistor Tc is turned on by the reset signal RESET 2  being provided to the reset control line HS. At this point, the potential of the floating diffusion FD is set to an L level by a drain pulse DRAIN 1  being provided to the drain power source line HD in the M-th row. 
     If the potential of the floating diffusion FD is set to the L level, the amplifying transistor Tb is turned off and each pixel is cut off from the vertical signal line VL. Thus, after the signal from each pixel being read, the vertical signal line VL can be prevented from being driven based on a signal from a pixel other than the pixels to be read by setting the potential of the floating diffusion FD of the cell UC 1  to the potential of the power source. 
     By driving the drain power source line HD separately in different rows, the load of the drain power source of the reset transistor Tc can be reduced. 
     Also, the capacity load of the vertical signal line VL can be reduced by separating the drain power source line HD from the drain power source AVDD so that a high-speed operation can be realized and also the drain potential of the amplifying transistor Tb can be fixed, leading to reduced noise by minimizing fluctuations in potential of the vertical signal line VL. 
     By making different cells adjacent to each other in the vertical direction share the drain of the reset transistor Tc and the drain of the amplifying transistor Tb of the cell UC 1 , the layout area can be reduced while pixels in the horizontal direction and the vertical direction enabling to be equally spaced. 
     Also by making cells adjacent to each other in the vertical direction share the drain of the reset transistor Tc of the cell UC 1 , cells adjacent to each other in the vertical direction can be made to share the drain power source line HD so that the number of the drain power source lines HD can be reduced by half. 
       FIG. 3  is a plan view illustrating a layout configuration of a pixel array unit of the solid state imaging apparatus in  FIG. 1 . 
     In  FIG. 3 , the two photodiodes PD 1 , PD 2  are vertically arranged side by side in units of the cell UC 1  on a semiconductor substrate. Then, the floating diffusion FD is arranged adjacent to the photodiodes PD 1 , PD 2 . 
     A gate electrode G 1  is arranged between the photodiode PD 1  and the floating diffusion FD and a gate electrode G 2  is arranged between the photodiode PD 2  and the floating diffusion FD. The gate electrodes G 1 , G 2  can configure the read transistors Td 1 , Td 2  respectively. 
     An impurity diffusion layer F 1  is arranged in a boundary region with the adjacent cell on the upper side and a gate electrode G 0  is arranged between the floating diffusion FD and the impurity diffusion layer F 1 . The gate electrode G 0  can configure the reset transistor Tc. 
     An impurity diffusion layer F 2  is arranged adjacent to the floating diffusion FD in the vertical direction and an impurity diffusion layer F 3  is arranged adjacent to the impurity diffusion layer F 2  in the vertical direction. A gate electrode G 3  is arranged between the impurity diffusion layers F 2 , F 3 . The gate electrode G 3  can configure the amplifying transistor Tb. 
     The reset transistor Tc and the amplifying transistor Tb of the cell UC 1  are arranged between the photodiodes PD 1 , PD 2  in the N-th column and the photodiodes PD 1 , PD 2  in the (N+1)-th column. 
     The floating diffusion FD is connected to the gate electrode G 3  via a wire H 1 . The impurity diffusion layer F 2  is connected to the vertical signal line VL via a wire H 2 . The drain power source line HD is connected to the impurity diffusion layer F 1 . 
     The reset control line HS is connected to the gate electrode G 0 . The read control lines HR 1 , HR 2  are connected to the gate electrodes G 1 , G 2  respectively. A power source line VD is connected to the impurity diffusion layer F 3 . The power source line VD can supply the drain power source AVDD. 
     Incidentally, the read transistors Td 1 , Td 2 , the reset transistor Tc, the floating diffusion FD, and the amplifying transistor Tb are arranged on the front side of the semiconductor substrate and the photodiodes PD 1 , PD 2  are arranged on the back side of the semiconductor substrate. For such a back-side illumination type, wires such as the reset control line HS, the read control lines HR 1 , HR 2 , and the power source line VD can be arranged overlapping with the photodiodes PD 1 , PD 2  so that flexibility of the wire layout can be increased. 
     Incidentally, the photodiodes PD 1 , PD 2  may also be arranged on the front side of the semiconductor substrate together with the read transistors Td 1 , Td 2 , the reset transistor Tc, the floating diffusion FD, and the amplifying transistor Tb. For such a front-side illumination type, wires of the reset control line HS, the read control lines HR 1 , HR 2 , and the power source line VD can be arranged while avoiding the photodiodes PD 1 , PD 2  so that the incidence of light into the photodiodes PD 1 , PD 2  is not prevented. 
     By making the drain diffusion layer of the reset transistor Tc of the cell UC 1  and the drain diffusion layer of the reset transistor Tc of the adjacent cell on the upper side shared and the drain diffusion layer of the amplifying transistor Tb of the cell UC 1  and the drain diffusion layer of the amplifying transistor Tb of the adjacent cell on the lower side shared, the layout area can be reduced while pixels in the horizontal direction and the vertical direction enabling to be equally spaced. 
     (Second Embodiment) 
       FIG. 4  is a block diagram illustrating the outline configuration of a solid state imaging apparatus according to a second embodiment. 
     In  FIG. 4 , the solid state imaging apparatus has a cell UC 1  arranged in a matrix form in the row direction and the column direction. The configuration of the cell UC 1  in  FIG. 4  is similar to the configuration of the cell UC 1  in  FIG. 1 . However, a cell UC 1 ′ in the (N+1)-th column in  FIG. 4  is arranged by being shifted upward in the vertical direction by one pixel with respect to the cell UC 1  in the N-th column and a cell UC 1 ″ in the (N+1)-th column in  FIG. 4  is arranged by being shifted downward in the vertical direction by one pixel with respect to the cell UC 1  in the N-th column. 
     A drain power source line HD′ and a reset control line HS′ are provided in the cell UC 1 ′ in the (N+1)-th column separately from the drain power source line HD and the reset control line HS of the cell UC 1  in the N-th column. In addition, the drain power source line HD′ and a reset control line HS″ are provided in the cell UC 1 ″ in the (N+1)-th column separately from the drain power source line HD 1  and the reset control line HS 1  of the cell UC 1  in the N-th column. The drain power source line HD′ is shared by the cells UC 1 ′, UC 1 ″. 
     The reset control line HS′ is connected to the gate of the reset transistor Tc of the cell UC 1 ′ in the (N+1)-th column. The reset control line HS″ is connected to the gate of the reset transistor Tc of the cell UC 1 ″ in the (N+1)-th column. The drain power source line HD′ is connected to the drains of the reset transistors Tc of the cells UC 1 ′, UC 1 ″ in the (N+1)-th column. 
     In the cell UC 1 ′ in the (N+1)-th column, the read control line HR 1  is connected to the gate of the read transistor Td 2  and the read control line HR 2  is connected to the gate of the read transistor Td 1 . 
     In this solid state imaging apparatus, instead of the row scanning circuit  1  in  FIG. 1 , a row scanning circuit  2  is provided. The drain power source lines HD, HD′, the reset control lines HS, HS′, HS″, and the read control lines HR 1 , HR 2  are connected to the row scanning circuit  2 . The row scanning circuit  2  can drive the drains of the reset transistors Tc from row to row separately from the drain of the amplifying transistor Tb. When a signal is read from a pixel in the M-th row, the drain power source lines HD, HD′ can be driven as a set. 
       FIG. 5  is a timing chart illustrating the read operation of the solid state imaging apparatus in  FIG. 4 . 
     In  FIG. 5 , if, for example, a signal is to be read from a pixel in the N-th column and the M-th row, the reset transistor Tc of the cell UC 1  is turned on and a charge of the floating diffusion FD of the cell UC 1  is reset by a reset signal RESET 2  being provided to the reset control line HS. Then, with the voltage in accordance with the reset level of the floating diffusion FD of the cell UC 1  being applied to the gate of the amplifying transistor Tb of the cell UC 1  and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 1  being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the reset level is output to the vertical signal line VL in the N-th column. 
     At this point, the reset transistor Tc of the cell UC 1 ′ is turned on and a charge of the floating diffusion FD of the cell UC 1 ′ is reset by a reset signal RESET 3  being provided to the reset control line HS′. Then, with the voltage in accordance with the reset level of the floating diffusion FD of the cell UC 1 ′ being applied to the gate of the amplifying transistor Tb of the cell UC 1 ′ and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 1 ′ being followed by the voltage of the vertical signal line VL in the (N+1)-th column, a pixel signal VSig 2  of the reset level is output to the vertical signal line VL in the (N+1)-th column. 
     Next, the read transistor Td 1  of the cell UC 1  is turned on by the read signal READ 3  being provided to the read control line HR 1  and a charge detected by the photodiode PD 1  of the cell UC 1  is transferred to the floating diffusion FD of the cell UC 1 . Then, with the voltage in accordance with the signal level of the floating diffusion FD of the cell UC 1  being applied to the gate of the amplifying transistor Tb of the cell UC 1  and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 1  being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the signal level is output to the vertical signal line VL in the N-th column. 
     Also, the read transistor Td 2  of the cell UC 1 ′ is turned on by the read signal READ 3  being provided to the read control line HR 1  and a charge detected by the photodiode PD 2  of the cell UC 1 ′ is transferred to the floating diffusion FD of the cell UC 1 ′. Then, with the voltage in accordance with the signal level of the floating diffusion FD of the cell UC 1 ′ being applied to the gate of the amplifying transistor Tb of the cell UC 1 ′ and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 1 ′ being followed by the voltage of the vertical signal line VL in the (N+1)-th column, the pixel signal VSig 2  of the signal level is output to the vertical signal line VL in the (N+1)-th column. 
     Next, the reset transistor Tc of the cell UC 1  is turned on by the reset signal RESET 2  being provided to the reset control line HS. At this point, the potential of the floating diffusion FD of the cell UC 1  is set to the L level by the drain pulse DRAIN 1  being provided to the drain power source line HD. 
     Also, the reset transistor Tc of the cell UC 1 ′ is turned on by the reset signal RESET 3  being provided to the reset control line HS′. At this point, the potential of the floating diffusion FD of the cell UC 1 ′ is set to the L level by a drain pulse DRAIN 2  being provided to the drain power source line HD′. 
     Next, if a signal is to be read from a pixel in the N-th column and the M-th row, the reset transistor Tc of the cell UC 1  is turned on and a charge of the floating diffusion FD of the cell UC 1  is reset by the reset signal RESET 2  being provided to the reset control line HS. Then, with the voltage in accordance with the reset level of the floating diffusion FD of the cell UC 1  being applied to the gate of the amplifying transistor Tb and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 1  being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the reset level is output to the vertical signal line VL in the N-th column. 
     At this point, the reset transistor Tc of the cell UC 1 ″ is turned on and a charge of the floating diffusion FD of the cell UC 1 ″ is reset by a reset signal RESET 4  being provided to the reset control line HS″. Then, with the voltage in accordance with the reset level of the floating diffusion FD of the cell UC 1 ″ being applied to the gate of the amplifying transistor Tb of the cell UC 1 ″ and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 1 ″ being followed by the voltage of the vertical signal line VL in the (N+1)-th column, the pixel signal VSig 2  of the reset level is output to the vertical signal line VL in the (N+1)-th column. 
     Next, the read transistor Td 2  of the cell UC 1  is turned on by a read signal READ 4  being provided to the read control line HR 2  and a charge detected by the photodiode PD 2  of the cell UC 1  is transferred to the floating diffusion FD of the cell UC 1 . Then, with the voltage in accordance with the signal level of the floating diffusion FD of the cell UC 1  being applied to the gate of the amplifying transistor Tb of the cell UC 1  and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 1  being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the signal level is output to the vertical signal line VL in the N-th column. 
     Also, the read transistor Td 1  of the cell UC 1 ″ is turned on by the read signal READ 4  being provided to the read control line HR 2  and a charge detected by the photodiode PD 1  of the cell UC 1 ″ is transferred to the floating diffusion FD of the cell UC 1 ″. Then, with the voltage in accordance with the signal level of the floating diffusion FD of the cell UC 1 ″ being applied to the gate of the amplifying transistor Tb of the cell UC 1 ″ and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 1 ″ being followed by the voltage of the vertical signal line VL in the (N+1)-th column, the pixel signal VSig 2  of the signal level is output to the vertical signal line VL in the (N+1)-th column. 
     Next, the reset transistor Tc of the cell UC 1  is turned on by the reset signal RESET 2  being provided to the reset control line HS. At this point, the potential of the floating diffusion FD of the cell UC 1  is set to the L level by the drain pulse DRAIN 1  being provided to the drain power source line HD. 
     Also, the reset transistor Tc of the cell UC 1 ″ is turned on by the reset signal RESET 4  being provided to the reset control line HS″. At this point, the potential of the floating diffusion FD of the cell UC 1 ″ is set to the L level by the drain pulse DRAIN 2  being provided to the drain power source line HD′. 
     Hereafter, a similar operation is caused when signals are read from the next row. 
     The layout of greens can be made symmetrical by arranging cells being shifted in the vertical direction between the N-th column and the (N+1)-th column so that variations in color can be reduced. 
       FIG. 6  is a plan view illustrating the layout configuration of a pixel array unit of the solid state imaging apparatus in  FIG. 4 . 
     In  FIG. 6 , the layout configuration of the cell UC 1  of the solid state imaging apparatus is similar to the layout configuration in  FIG. 3 . However, the reset transistor Tc, the floating diffusion FD, and the amplifying transistor Tb of the cell UC 1  in the (N+1)-th column are arranged by being shifted in the vertical direction by two pixels with respect to the reset transistor Tc, the floating diffusion FD, and the amplifying transistor Tb of the cell UC 1  in the N-th column. 
     Accordingly, even if the cell UC 1  is arranged in a staggered configuration, by making the drain diffusion layer of the reset transistor Tc of the cell UC 1  and the drain diffusion layer of the reset transistor Tc of the adjacent cell on the upper side shared and the drain diffusion layer of the amplifying transistor Tb of the cell UC 1  and the drain diffusion layer of the amplifying transistor Tb of the adjacent cell on the lower side shared, the layout area can be reduced while pixels in the horizontal direction and the vertical direction enabling to be equally spaced. 
     In the example of  FIG. 6 , the wire layout of a back-side illumination type CMOS sensor is taken as an example, but the present embodiment may also be applied to a front-side illumination type CMOS sensor. 
     (Third Embodiment) 
       FIG. 7  is a block diagram illustrating the outline configuration of a solid state imaging apparatus according to a third embodiment. 
     In  FIG. 7 , the solid state imaging apparatus has a cell UC 2  arranged in a matrix form in the row direction and the column direction. Each of the cells UC 2  is provided with four photodiodes PD 1  to PD 4 , four read transistors Td 1  to Td 4 , one reset transistor Tc, one floating diffusion FD, and one amplifying transistor Tb. 
     Each of the photodiodes PD 1  to PD 4  can convert light from an object to be imaged into an electric signal in units of pixel. The read transistors Td 1  to Td 4  can read a signal photoelectrically converted by the photodiodes PD 1  to PD 4  respectively. The reset transistor Tc is shared by the photodiodes PD 1  to PD 4  and can reset a signal read from the photodiodes PD 1  to PD 4 . The floating diffusion FD is shared by the photodiodes PD 1  to PD 4  and can cause detection of a signal read from the photodiodes PD 1  to PD 4 . The amplifying transistor Tb is shared by the photodiodes PD 1  to PD 4  and can amplify a signal read from the photodiodes PD 1  to PD 4 . 
     The photodiodes PD 1  to PD 4  are vertically arranged side by side and the photodiode PD 1  can be arranged in the M-th row, the photodiode PD 2  can be arranged in an (M+1)-th row, the photodiode PD 3  can be arranged in an (M+2)-th row, and the photodiode PD 4  can be arranged in an (M+3)-th row. The floating diffusion FD is shared by the drains of the read transistors Td 1 , Td 2 . The sources of the read transistors Td 1  to Td 4  are connected to the photodiodes PD 1  to PD 4  respectively. The source of the reset transistor Tc is connected to the floating diffusion FD. 
     The cell UC 2  in the N-th column is arranged point-symmetrically with respect to a cell UC 2 ′ in the (N+1)-th column. The drain of the reset transistor Tc of the cell UC 2  in the N-th column and the drain of the reset transistor Tc of the cell UC 2 ′ in the (N+1)-th column are shared. Also, the drain of the amplifying transistor Tb of the cell UC 2  in the N-th column and the drain of the amplifying transistor Tb of the cell UC 2 ′ in the (N+1)-th column are shared. 
     The solid state imaging apparatus is provided with a row scanning circuit  3  that scans pixels in units of row and also a vertical signal line VL that transmits a signal read from each pixel in units of column. A drain power source line HD, reset control lines HS 1 , HS 2 , and read control lines HR 1  to HR 4  are connected to the row scanning circuit  3 . The read control lines HR 1  to HR 4  are provided for each row and connected to the gates of the read transistors Td 1  to Td 4  respectively. The reset control lines HS 1 , HS 2  are provided for every four rows, the reset control line HS 1  is connected to the gate of the reset transistor Tc of the cell UC 2  in the N-th column, and the reset control line HS 2  is connected to the gate of the reset transistor Tc of the cell UC 2 ′ in the (N+1)-th column. The drain power source line HD is provided for every four rows and connected to the gate of the reset transistor Tc. The row scanning circuit  3  can drive the drains of the reset transistors Tc in different rows separately. The row scanning circuit  3  can also drive the drain of the reset transistor Tc and the drain of the amplifying transistor Tb separately. If, for example, the drain of the reset transistor Tc is shared by four pixels adjacent to each other in the vertical direction, the drain of the reset transistor Tc can be driven for every four rows. The row scanning circuit  3  can drive the reset control line HS 1  of the cell UC 2  in the N-th column and the reset control line HS 2  of the cell UC 2 ′ in the (N+1)-th column as a set. 
     The gate of the amplifying transistor Tb is connected to the floating diffusion FD, the source of the amplifying transistor Tb is connected to the vertical signal line VL, and the drain of the amplifying transistor Tb is connected to a drain power source AVDD. 
     The drain power source AVDD can commonly be connected to the drains of the amplifying transistors Tb of all the cells UC 2  in the solid state imaging apparatus. The voltage of the drain power source AVDD can be set to a fixed value. 
       FIG. 8  is a timing chart illustrating the read operation of the solid state imaging apparatus in  FIG. 7 . 
     In  FIG. 8 , if, for example, signals are to be read from pixels in the (M+2)-th row, each of the reset transistors Tc of the cells UC 2 , UC 2 ′ is turned on and a charge of each of the floating diffusions FD of the cells UC 2 , UC 2 ′ is reset by reset signals RESET 1 , RESET 2  being provided to the reset control lines HS 1 , HS 2  respectively. Then, with the voltage in accordance with the reset level of the floating diffusion FD of the cell UC 2  being applied to the gate of the amplifying transistor Tb of the cell UC 2  and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 2  being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the reset level is output to the vertical signal line VL in the N-th column. 
     Next, the read transistor Td 3  is turned on by the read signal READ 3  being provided to the read control line HR 3  and a charge detected by the photodiode PD 3  is transferred to the floating diffusion FD. Then, with the voltage in accordance with a signal level of the floating diffusion FD being applied to the gate of the amplifying transistor Tb and the voltage applied to the gate of the amplifying transistor Tb being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the signal level is output to the vertical signal line VL in the N-th column. 
     Next, each of the reset transistors Tc of the cells UC 2 , UC 2 ′ is turned on by the reset signals RESET 1 , RESET 2  being provided to the reset control lines HS 1 , HS 2  respectively. At this point, the potential of the floating diffusion FD is set to the L level by the drain pulse DRAIN 1  being provided to the drain power source line HD. 
     Hereafter, a similar operation is caused when signals are read from the next row. 
     By driving the drain power source line HD separately in different rows, the load of the drain power source of the reset transistor Tc can be reduced also in the 4-pixel shared structure. 
     By arranging the cell UC 2  in the N-th column point-symmetrically with respect to the cell UC 2 ′ in the (N+1)-th column, the drain of the reset transistor Tc and the drain of the amplifying transistor Tb of the cell UC 1  can be made to be shared with different adjacent cells while ensuring symmetry of the arrangement of the floating diffusion FD in the vertical direction and the horizontal direction. Therefore, the layout can be set so that parasitic capacitances between the floating diffusions FD are mutually equal to prevent an occurrence of stepwise noise between the cells UC 2 . 
       FIG. 9  is a plan view illustrating the layout configuration of a pixel array unit of the solid state imaging apparatus in  FIG. 7 . 
     In  FIG. 9 , the four photodiodes PD 1  to PD 4  are vertically arranged side by side in units of the cell UC 2  on a semiconductor substrate. Then, the impurity diffusion layer F 3  is arranged adjacent to the photodiodes PD 1 , PD 2  and the floating diffusion FD is arranged adjacent to the photodiodes PD 3 , PD 4 . 
     A gate electrode G 11  is arranged between the photodiode PD 1  and the impurity diffusion layer F 3 , a gate electrode G 12  is arranged between the photodiode PD 2  and the impurity diffusion layer F 3 , a gate electrode G 13  is arranged between the photodiode PD 3  and the floating diffusion FD, and a gate electrode G 14  is arranged between the photodiode PD 4  and the floating diffusion FD. The gate electrodes G 11  to G 14  can configure the read transistors Td 1  to Td 4  respectively. 
     The impurity diffusion layer F 1  is arranged in a boundary region with the adjacent cell UC 2 ′ in the horizontal direction and a gate electrode G 10  is arranged between the floating diffusion FD and the impurity diffusion layer F 1 . The gate electrode G 10  can configure the reset transistor Tc. 
     The impurity diffusion layer F 2  is arranged adjacent to the floating diffusion FD in the vertical direction and an impurity diffusion layer F 4  is arranged in a boundary region with the cell UC 2 ″ adjacent to the cell UC 2 ′ in the vertical direction. A gate electrode G 15  is arranged between the impurity diffusion layers F 2 , F 4 . The gate electrode G 15  can configure the amplifying transistor Tb. The floating diffusion FD of the cell UC 2  and the floating diffusion FD of the cell UC 2 ′ are arranged point-symmetrically with respect to the impurity diffusion layer F 1 . The floating diffusion FD of the cell UC 2  and the floating diffusion FD of the cell UC 2 ″ are arranged point-symmetrically with respect to the impurity diffusion layer F 4 . 
     The reset transistors Tc and the amplifying transistors Tb of the cells UC 2 , UC 2 ′, UC 2 ″ are arranged between the photodiodes PD 1  to PD 4  in the N-th column and the photodiodes PD 1  to PD 4  in the (N+1)-th column. 
     The floating diffusion FD is connected to the impurity diffusion layer F 3  via a wire H 11 . The floating diffusion FD is connected to the gate electrode G 15  via a wire H 12 . The impurity diffusion layer F 2  is connected to the vertical signal line VL via a wire H 13 . The drain power source line HD is connected to the impurity diffusion layer F 1 . 
     The reset control line HS 1  is connected to the gate electrode G 10  of the cell UC 2  and the reset control line HS 2  is connected to the gate electrode G 10  of the cell UC 2 ′. The read control lines HR 1  to HR 4  are connected to the gate electrodes G 11  to G 14  respectively. A power source line VD is connected to the impurity diffusion layer F 4 . The power source line VD can supply the drain power source AVDD. 
     Incidentally, the read transistors Td 1  to Td 4 , the reset transistor Tc, the floating diffusion FD, and the amplifying transistor Tb are arranged on the front side of the semiconductor substrate and the photodiodes PD 1  to PD 4  are arranged on the back side of the semiconductor substrate. For such a back-side illumination type, wires such as the reset control lines HS 1 , HS 2 , the read control lines HR 1  to HR 4 , and the power source line VD can be arranged overlapping with the photodiodes PD 1  to PD 4  so that flexibility of the wire layout can be increased. 
     Incidentally, the photodiodes PD 1  to PD 4  may also be arranged on the front side of the semiconductor substrate together with the read transistors Td 1  to Td 4 , the reset transistor Tc, the floating diffusion FD, and the amplifying transistor Tb. For such a front-side illumination type, wires such as the reset control lines HS 1 , HS 2 , the read control lines HR 1  to HR 4 , and the power source line VD can be arranged while avoiding the photodiodes PD 1  to PD 4  so that the incidence of light into the photodiodes PD 1  to PD 4  is not prevented. 
     By separating the reset control lines HS 1 , HS 2  between the cells UC 2 , UC 2 ′ adjacent to each other in the horizontal direction, the layout can be set so that parasitic capacitances between the floating diffusions FD are mutually equal even if the drain diffusion layer of the reset transistor Tc and the drain diffusion layer of the amplifying transistor Tb of the cell UC 1  are made to be shared with adjacent cells. 
     (Fourth Embodiment) 
       FIG. 10  is a block diagram illustrating the outline configuration of a solid state imaging apparatus according to a fourth embodiment. 
     In  FIG. 10 , the solid state imaging apparatus has the cell UC 2  arranged in a matrix form in the row direction and the column direction. The configuration of the cell UC 2  in  FIG. 10  is similar to the configuration of the cell UC 2  in  FIG. 7 . However, the cell UC 2 ′ in the (N+1)-th column in  FIG. 10  is arranged by being shifted upward in the vertical direction by two pixels with respect to the cell UC 2  in the N-th column and the cell UC 2 ″ in the (N+1)-th column in  FIG. 10  is arranged by being shifted downward in the vertical direction by two pixels with respect to the cell UC 2  in the N-th column. 
     While the arrangement relationship between the reset transistor Tc and the amplifying transistor Tb in the vertical direction is mutually reversed in the cell UC 2  in the N-th column and the cell UC 2 ′ in the (N+1)-th column in the solid state imaging apparatus in  FIG. 7 , the arrangement relationship between the reset transistor Tc and the amplifying transistor Tb in the vertical direction is mutually equal in the cell UC 2  in the N-th column and the cell UC 2 ′ in the (N+1)-th column in the solid state imaging apparatus in  FIG. 10 . 
     In this solid state imaging apparatus, instead of the row scanning circuit  3  in  FIG. 7 , a row scanning circuit  4  is provided. The drain power source lines HD 1 , HD 2 , the reset control lines HS 1 , HS 2 , and the read control lines HR 1  to HR 4  are connected to the row scanning circuit  4 . The row scanning circuit  4  can drive the drains of the reset transistors Tc in different rows separately. The row scanning circuit  4  can also drive the drain of the reset transistor Tc and the drain of the amplifying transistor Tb separately. If, for example, the drain of the reset transistor Tc is shared by four pixels adjacent to each other in the vertical direction, the drain of the reset transistor Tc can be driven for every four rows. The row scanning circuit  4  can drive the reset control line HS 1  of the cell UC 2  in the N-th column and the reset control line HS 2  of the cell UC 2 ″ in the (N+1)-th column as a set. 
       FIG. 11  is a timing chart illustrating the read operation of the solid state imaging apparatus in  FIG. 10 . 
     In  FIG. 11 , if, for example, a signal is to be read from a pixel in the N-th column and the (M+2)-th row, the reset transistor Tc of the cell UC 2  is turned on and a charge of the floating diffusion FD of the cell UC 2  is reset by the reset signal RESET 2  being provided to the reset control line HS 1 . Then, with the voltage in accordance with the reset level of the floating diffusion FD of the cell UC 2  being applied to the gate of the amplifying transistor Tb of the cell UC 2  and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 2  being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the reset level is output to the vertical signal line VL in the N-th column. 
     At this point, the reset transistor Tc of the cell UC 2 ″ is turned on and a charge of the floating diffusion FD of the cell UC 2 ″ is reset by the reset signal RESET 3  being provided to the reset control line HS 2 . Then, with the voltage in accordance with the reset level of the floating diffusion FD of the cell UC 2 ″ being applied to the gate of the amplifying transistor Tb of the cell UC 2 ″ and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 2 ″ being followed by the voltage of the vertical signal line VL in the (N+1)-th column, the pixel signal VSig 2  of the reset level is output to the vertical signal line VL in the (N+1)-th column. 
     Next, the read transistor Td 3  of the cell UC 2  is turned on by the read signal READ 3  being provided to the read control line HR 3  and a charge detected by the photodiode PD 3  of the cell UC 2  is transferred to the floating diffusion FD of the cell UC 2 . Then, with the voltage in accordance with the signal level of the floating diffusion FD of the cell UC 2  being applied to the gate of the amplifying transistor Tb of the cell UC 2  and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 2  being followed by the voltage of the vertical signal line VL in the N-th column, the pixel signal VSig 1  of the signal level is output to the vertical signal line VL in the N-th column. 
     Also, if the read signal READ 3  is provided to the read control line HR 3 , the read transistor Td 1  of the cell UC 2 ″ is turned on and a charge detected by the photodiode PD 1  of the cell UC 2 ″ is transferred to the floating diffusion FD of the cell UC 2 ″. Then, with the voltage in accordance with the signal level of the floating diffusion FD of the cell UC 2 ″ being applied to the gate of the amplifying transistor Tb of the cell UC 2 ″ and the voltage applied to the gate of the amplifying transistor Tb of the cell UC 2 ″ being followed by the voltage of the vertical signal line VL in the (N+1)-th column, the pixel signal VSig 2  of the signal level is output to the vertical signal line VL in the (N+1)-th column. 
     Next, the reset transistor Tc of the cells UC 2  is turned on by the reset signal RESET 2  being provided to the reset control line HS 1 . At this point, the potential of the floating diffusion FD of the cell UC 2  is set to the L level by the drain pulse DRAIN 1  being provided to the drain power source line HD 1 . 
     Also, the reset transistor Tc of the cell UC 2 ″ is turned on by the reset signal RESET 3  being provided to the reset control line HS 2 . At this point, the potential of the floating diffusion FD of the cell UC 2 ″ is set to the L level by the drain pulse DRAIN 2  being provided to the drain power source line HD 2 . 
     Hereafter, a similar operation is caused when signals are read from the next row. 
       FIG. 12  is a plan view illustrating the layout configuration of a pixel array unit of the solid state imaging apparatus in  FIG. 10 . 
     In  FIG. 12 , the layout configuration of the cell UC 2  of the solid state imaging apparatus is similar to the layout configuration in  FIG. 9 . However, the cells UC 2 , UC 2 ′, UC 2 ″ are arranged in a staggered configuration by the wire H 11  connecting the impurity diffusion layer F 3  and the floating diffusion FD of the cell UC 2  in the N-th column being shifted in the vertical direction by two rows in the (N+1)-th column. 
     Accordingly, the drain diffusion layer of the reset transistor Tc and the drain diffusion layer of the amplifying transistor Tb of the cell UC 2  can be made to be shared with different adjacent cells while ensuring symmetry of the arrangement of the floating diffusion FD in the vertical direction and the horizontal direction also when the cells UC 2 , UC 2 ′, UC 2 ″ are arranged in a staggered configuration. 
     In the example of  FIG. 12 , the wire layout of a back-side illumination type CMOS sensor is taken as an example, but the present embodiment may also be applied to a front-side illumination type CMOS sensor. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.