Abstract:
A network device for determining an optimal sampling phase for source synchronous data received on a data communications channel. The network device includes a transmitter clock domain for providing a data pattern along with a synchronous free-running clock. The network device also includes a plurality of phases of a core clock. The network devices further includes means, in a core clock domain, for sampling a data pattern generated by the received clock with the plurality of phases to determine the optimal phase for sampling the data received from the external device:

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a network device in a data communications network and more particularly to a method of obtaining an optimal sampling of data obtained from an external source synchronous communication channel.  
         [0003]     2. Description of the Related Art  
         [0004]     A data network may include one or more network devices, such as a Ethernet switching chip, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, as data enters the device from multiple ports, it is forwarded to an ingress module where switching and other processing are performed on the data. Thereafter, data is transmitted to one or more destination ports through one or more units including a Memory Management Unit (MMU). The MMU provides access to one or more off-chip source synchronous memory devices, for example, an external Double Data Rate (DDR) memory. The network device typically generates a source synchronous clock that is provided with data during a write operation on the source synchronous memory device. The memory device then uses the clock to capture the data and perform the write operation. However, when the network device is performing a read operation from the memory device, the delay for data and clock from the memory device is indeterministic based on at least the trace lengths and process corner associated with the memory device. For example, if there is a fast process or slow process corner device, the delay from the memory device will vary. As such, the round trip delays for a read operation can vary greatly from chip-to-chip or board-to-board.  
         [0005]     When a read operation is performed by the source synchronous memory device, the memory device returns data and clock. However, the clock phase from the source synchronous memory device can vary relative to the clock within the network device because the phases may shift. As is known, when the phases of the clock and data line up with each other, bit errors may occur and the network device cannot adequately sample data returned from the memory device.  
         [0006]     Therefore, to obtain the least amount of error, a mechanism must be provided to sample the received data at a time when the data is most stable. Some source synchronous interfaces and some memory devices provide free running clocks. Current network devices typically sample the data multiple times to find out where the edges exist in relation to the internal clock in the network device. However, when there are no memory operations being performed by the source synchronous memory device, the received data is not changing. Hence, there are no edges/transitions for determining the optimal phase of the clock. Furthermore, even if memory operations are occurring, if the same data value is being continuously read, there will still be no transitions for determining the optimal phase of the clock.  
         [0007]     To overcome the problems presented by source synchronous memory devices with free running clocks, some network devices use a first-in-first-out (FIFO) buffer to absorb difference between the memory controller clock in the network device and the clock generated by the source synchronous memory device. However, the use of the FIFO to absorb the differences between the clocks increases gate count which in turn increases circuit area. Use of a FIFO to realign clock phases also increases latency for received data.  
       SUMMARY OF THE INVENTION  
       [0008]     According to one aspect of the invention, there is provided a network device for determining an optimal sampling phase for source synchronous data received from an external device. The network device includes receiving means for receiving from a transmitting device a clock and data with a fixed phase relationship. The network device also includes a plurality of phases of a core clock, in a core clock domain, for sampling received data. The network device further includes selecting means for selecting an optimal phase for sampling a data pattern based on results of sampling the data using the plurality of phases.  
         [0009]     According to another aspect of the invention, there is provided a method for determining an optimal sampling phase for source synchronous data received from an external device. The method includes the step of receiving from a transmitting device a clock and data with a fixed phase relationship. The method also includes the steps of sampling a locally generated data pattern with a plurality of phases of a core clock and selecting an optimal phase for sampling a data pattern based on results of sampling the data using the plurality of phases.  
         [0010]     According to another aspect of the invention, there is provided an apparatus for determining an optimal sampling phase for source synchronous data received from an external device. The apparatus includes receiving means for receiving from a transmitting device a clock and data with a fixed phase relationship. The apparatus also includes sampling means for sampling a locally generated data pattern with a plurality of phases of a core clock. The apparatus further includes selecting means for selecting an optimal phase for sampling a data pattern based on results of sampling the data using the plurality of phases. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention that together with the description serve to explain the principles of the invention, wherein:  
         [0012]      FIG. 1  illustrates a network device in which an embodiment of the present invention may be implemented;  
         [0013]      FIG. 2   a  illustrates how memory read data is sampled by the network device;  
         [0014]      FIG. 2   b  aligned memory clock and read data;  
         [0015]      FIG. 3  illustrates sampling phases generated by the network device using multiple quadrature phases;  
         [0016]      FIG. 4  illustrates the steps in providing data for sampling from a memory clock domain to a network device clock domain; and  
         [0017]      FIG. 5  illustrates the steps implemented in selecting an optimal sampling phase. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0018]     Reference will now be made to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
         [0019]      FIG. 1  illustrates a network device, such as a switching chip, in which an embodiment the present invention may be implemented. Device  100  includes an ingress module  102 , a MMU  104 , and an egress module  106 . Ingress module  102  is used for performing switching functionality on an incoming packet. The primary function of MMU  104  is to efficiently manage cell buffering and packet pointer resources in a predictable manner even under severe congestion scenarios. Egress module  106  is used for performing packet modification and transmitting the packet to an appropriate destination port.  
         [0020]     Device  100  may also include one internal fabric high speed port, for example a HiGig port,  108 , one or more external Ethernet ports  109   a - 109   x , and a CPU port  110 . High speed port  108  is used to interconnect various network devices in a system and thus form an internal switching fabric for transporting packets between external source ports and one or more external destination ports. As such, high speed port  108  is not externally visible outside of a system that includes multiple interconnected network devices. CPU port  110  is used to send and receive packets to and from external switching/routing control entities or CPUs. According to an embodiment of the invention, CPU port  110  may be considered as one of external Ethernet ports  109   a - 109   x . Device  100  interfaces with external/off-chip CPUs through a CPU processing module  111 , such as a CMIC, which interfaces with a PCI bus that connects device  100  to an external CPU.  
         [0021]     Network traffic enters and exits device  100  through external Ethernet ports  109   a - 109   x . Specifically, traffic in device  100  is routed from an external Ethernet source port to one or more unique destination Ethernet ports. In one embodiment of the invention, device  100  supports twelve physical Ethernet ports  109 , each of which can operate in 10/100/1000 Mbps speed and one high speed port  108  which operates in either 10 Gbps or 12 Gbps speed.  
         [0022]     In an embodiment of the invention, device  100  is built around a shared memory architecture, wherein MMU  104  provides access to one or more off-chip source synchronous memory devices, for example, an external Double Data Rate (DDR) memory device  201 . In an embodiment of the invention, MMU  104  includes 4 DDR interfaces. During a write operation to device  201 , network device  100  typically generates a source synchronous clock that is provided with data to the source synchronous memory device. Memory device  201  then uses the clock to capture the data and perform the write operation. However, when network device  100  is performing a read operation from memory device  201 , the phase of the received clock and data is indeterministic and thus an optimal sampling phase must be derived.  
         [0023]      FIG. 2   a  illustrates how memory read data is sampled by device  100  and timing is transferred from a clock domain  203  of the external memory to an internal clock domain  205  of device  100 . As shown in  FIG. 2 , during a read operation in memory clock domain  203 , memory device  201  generates a clock  202  and data  204  which is aligned as shown in  FIG. 2   b . This figure shows double data rate (DDR) data but the data could also be single data rate (SDR). However, the aligned clock  202  and data  204  do not provide an optimal sampling phase because clock edges do not occur when the data is most stable. Therefore, clock  202  is transmitted to a 90 degree phase shift generator  206 , with offset control, which generates a 90 degree phase offset clock  207 . Shift generator  206  may be a standard DLL or PLL generator. Clock  207  is then used to sample data  204 , wherein clock  207  samples data  204  at the rising edge of clock  207  at flop  210  and samples data  204  at the falling edge of clock  207  at flop  212 . Thereafter flops  214  and  216  are used to line up the data sampled at the rising and falling edges of the clock  207 . Clock  207  is also transmitted to a divide-by-two circuit  208  which creates an alternating 1/0 data pattern that alternates every clock cycle. According to an embodiment of the invention, by using the same flip-flop cell in the divide-by-two operation as is used for the initial read data sample, the inventive system allows for better matching of delays and better determination of the optimal sampling phase. In an embodiment of the inventive system, memory  201  is not required to perform an operation in order for device  100  to obtain the transitions that are needed to determine an optimal phase for sampling data. The sampled results are then synchronized back into main clock domain  205  and are then fed into the state machine to decide which quadrature phase should be used to sample data from memory clock domain  203 .  
         [0024]     In an embodiment of the invention, along with the rise and fall data transmitted from memory device  201 , device  100  also obtains the alternating I/O data pattern generated by circuit  208 , wherein the alternating data pattern is in line with the aligned rise and fall data from flops  214  and  216 . Device  100  then uses phases  222   a - 222   d  to multiply sample the alternating 1/0 data pattern multiple times to determine the optimal sampling phase. Thereafter, in core clock domain  205 , device  100  provides multiple quadrature phases  222   a - 222   d  of a core clock. Phase  222   a  has a 0 degree offset from the core clock, phase  222   b  has a 270 degree offset from the core clock, phase  222   c  has a 180 degree offset from the core clock and phase  222   d  has a 90 degree offset from the core clock. According to one embodiment of the invention, device  100  generates four phases  222   a - 222   d  of the core clock. However, as is known to those of ordinary skill in the art, device  100  may generate more than four phases for better resolution.  
         [0025]     In an embodiment of the inventive system, during sampling, device  100  ignores data  204  returned from memory device  201 . Device  100  only samples the alternate 1/0 data pattern from clock  202 , wherein the 1/0 data pattern provides a transition in every cycle. Since device  100  samples the alternating 1/0 data pattern, memory  201  is not required to perform an operation in order for device  100  to obtain the needed transitions that are sampled to determine an optimal phase for sampling data. As such, the inventive system eliminates the drifts that occur between phases when a transition does not occur every cycle, thereby causing the phase to be off. By producing a transition every cycle, the inventive system enables device  100  to constantly re-correct in order to determine the location of the optimal sampling phase.  
         [0026]     Sampling of the alternating data pattern provides an advantage over directly sampling of the received clock or data in that it enables better phase match with the delays data from flops  214  and  216  to provide the most optimal sampling phase. The process corner delay variations of the alternating data pattern match the process corner delay variation of the data from flops  214  and  216 . As is known to those skilled in the art, the clock returned from memory  201  typically includes jitter that blurs the edges. As such when a sample is obtained from near the edge, the data pattern may sometimes be a zero or a one, which is a non-optimal point for sampling data. Therefore, according to an embodiment of the invention, device  100  selects the optimal sampling phase that will produce the fewest sampling errors, that is, a sampling phase that is farthest away from the edges.  
         [0027]     As mentioned above, device  100  operates without the need for any memory operations. As such, when device  100  is started, as long as a free running clock in memory  201  is executing, device  100  can determine the optimal sampling phase. Device  100  therefore relies only on the free running read strobe clock from external memory  210  and may run without a training sequence and remains locked even in the absence of memory operations. Since there is a transition every cycle, device  100  can realign every cycle, is insensitive to data patterns, and can tolerate infinite sequences of ones and zeros. Device  100  can also respond quickly to changes in phase of memory read strobe clocks since the sampled data has a guaranteed transition on every rising clock edge.  
         [0028]      FIG. 3  illustrates sampling phases generated by device  100  using phases  222   a - 222   d . According to the inventive system, as illustrated in  FIG. 3 , the 90 degree shifted clock  207  was used to create an alternating 1/0 data pattern  302  which is then double-flop sampled with multiple 90 degree shifted quadrature phases  222   a - 222   d  in domain  205 . The sample clock which lands in the middle of the eye of the alternate 1/0 pattern is then used to sample all of the read data from the memory. Therefore, based on the illustrations of  FIG. 3 , clock phase  222   a  will be selected as the optimal sampling phase because that phase provides points that are farthest away from the edges of the clock. Since an embodiment of the inventive system uses the same flip-flop cell that is used for generating the alternate 1/0 pattern for sampling the read data from the memory, the phase of the alternate 1/0 pattern is virtually identical to the phase of the sampled rise and fall data  304  and  306 . Therefore, the optimal clock phase  222   a , as shown as  308 , needed to sample the alternate 1/0 pattern will be the same as that needed to sample rise and fall data  314  and  316  at the output of flops  214  and  216 .  
         [0029]      FIG. 4  illustrates the steps implemented in transferring timing from a memory clock domain to a core clock domain in order to determine an optimal sampling phase. In Step  4010 , during a read operation in memory clock domain  203 , memory device  201  generates clock  202  and data  204 . In Step  4020 , clock  202  is then transmitted to 90 degree phase shift generator  206  which generates 90 degree phase offset clock  207 . It should be noted that while the phase shift generator  206  in one embodiment of the invention is a 90 degree phase shift generator, a 90 degree phase shift generator is optional and other phase shift generators may be implemented in the present invention. In Step  4030 , clock  207  is used to sample data at the rising and falling edges of clock  207 . In Step  4040 , the data sampled at the rising and falling edges of the clock  207  are lined up. In Step  4050 , clock  207  is also transmitted to divide-by-two circuit  208  which creates an alternating 1/0 data pattern that alternates every clock cycle. In Step  4060 , in core clock domain  205 , device  100  provides multiple quadrature phases  222   a - 222   d  for sampling the alternating 1/0 pattern. In Step  4070 , device  100  samples the alternating 1/0 data pattern multiple times with clocks  222   a - 222   d  to determine which of the quadrature phases is optimal for resampling the received data.  
         [0030]     According to an embodiment, device  100  includes an algorithm for determine which quadrature clock  222   a - 222   d  to use in sampling data. The algorithm relies on comparing samples (voting) from clocks  222   a - 222   d  of the sampled values from the alternating 1/0 pattern to determine where the edges of the pattern are located. The results of these comparisons create “votes” for selecting one particular phase of sampling clock. According to an embodiment of the invention, the algorithm counts these votes from quadrature clock  222   a - 222   d  and only makes changes when the counts pass predetermined thresholds. Specifically, a free running counter is programmable to thresholds of 16, 32 and 64. While the counter is running, a count is taken on how many times a vote is asserted for selecting any particular one of the quadrature clocks  222   a - 222   d . If any count is asserted to a maximum count value, then the device  100  switches to that sampling phase, otherwise it says at the current phase selection. When the data edge occurs coincident with a sampling clock and there are sufficient counts for two different quadrature clocks, then an optimal phase selection point is determined to be 180 degrees from the sampling clock which is aligned with the data bit. The counting of votes for a particular number of clock cycles essentially forms a filtering function which prevents a noise event from causing an erroneous change in the sampling point. Note that the use of an alternating I/O patterns for multiphase sampling is preferable to sampling received data because data transition is assured in every clock cycle and votes can be compared with a max count of 16, 32 or 64. According to another embodiment of the invention, the algorithm makes changes immediately upon detecting a more optimal sampling point without accumulating a count of votes.  
         [0031]      FIG. 5  illustrates the steps implemented in determining which quadrature clock  222   a - 222   d  to use in sampling data. In Step  5010 , a free running counter is programmable to thresholds of 16, 32 and 64. In Step  5020 , while the counter is running, counts are taken on how many times votes are asserted for each of the quadrature clocks  222   a - 222   d . In Step  5030 , if any count is asserted to a maximum count value, then device  100  switches to that sampling phase, otherwise it says at the current phase selection. In Step  5040 , when the data edge occurs coincident with a sampling clock and there are sufficient counts for two different quadrature clocks, device  100  determines that an optimal phase selection point is 180 degrees from the sampling clock which is aligned with the data bit.  
         [0032]     The foregoing description has been directed to specific embodiments of this invention. It will be apparent, however, that other variations and modifications may be made to the described embodiments, with the attainment of some or all of their advantages. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.