Abstract:
A charge transfer device according to the present invention comprises 4n (where n is a positive integer) initial-stage charge transfer registers to which a plurality of photoelectric converters is connected and a charge detection unit detecting a charge transferred from the initial-stage charge transfer registers in sequence via a secondary-stage charge transfer register. The merging of two charge transfer registers adjacent to each other among the initial-stage charge transfer registers into one charge transfer register disposed in the secondary stage is repeated at least once, and the final two charge transfer registers after merging are connected to one charge detection unit.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a charge transfer device and to a drive method for the same.  
         [0003]     2. Description of the Related Art  
         [0004]     Progress in reduction of pixel size and increased resolution has been made in image sensors or charge transfer devices in recent years, and miniaturization in design rules is desired. However, the miniaturization of design rules requires resources and time, and instant adaptation to the demand for reduced pixel size is difficult. Because of this situation, various charge transfer systems have been developed for obtaining a high-resolution CCD without changing design rules.  
         [0005]      FIG. 12  is a plan view-showing the structure of a single CCD-type charge transfer device.  
         [0006]     The charge transfer device shown in  FIG. 12  is provided with a photodiode row  2  in which photodiodes are arranged in a row at a prescribed pitch; a single Charge Coupled Device (CCD) 1 ; and a read gate  10  provided between the CCD  1  and the photodiode row  2 .  
         [0007]     In  FIG. 12 , the arrows pointing towards the CCD  1  from the photodiodes contained in the photodiode row  2  indicate the read direction from each of the photodiodes to the CCD  1 . In other words, the charges from the photodiodes are read to the CCD  1  via the read gate  10 .  
         [0008]     The CCD  1  is connected to the charge detection unit  4  via the output gate  3   a . The CCD  1  is provided with a reset gate  5  that is adjacent to the charge detection unit  4 . Furthermore, a drain  6  is provided adjacent to the reset gate  5 , and the drain  6  is connected to the power supply line  8  from which a power supply potential is provided.  
         [0009]     The charge detection unit  4  is connected to a source follower amplifier  7 . This source follower amplifier  7  is provided with interconnected MOS transistors  12   a  and  12   b . Among these components, the source of the MOS transistor  12   a  is connected to the power supply line  8 , the gate thereof is connected to the charge detection unit  4 , and the drain thereof is connected to the source of the MOS transistor  12   b . The gate of the MOS transistor  12   b  is connected to the power supply line  8 , and the drain thereof is connected to the (GND) line  9  from which a ground (GND) potential is supplied. Furthermore, the point at which the MOS transistors  12   a  and  12   b  are interconnected is connected to a signal output line  11 .  
         [0010]     Thus, the single CCD-type charge transfer device is provided with one CCD  1  for one photodiode row  2 .  
         [0011]      FIG. 13  is a plan view showing the structure of a dual-CCD charge transfer device.  
         [0012]     In the charge transfer device shown in  FIG. 13 , the same symbols are used for structural elements that are the same as those in the charge transfer device shown in  FIG. 12 , and description thereof is omitted.  
         [0013]     As shown in  FIG. 13 , CCD  1   a  and  1   b  are provided on both sides corresponding to a single photodiode row  2  in the dual-CCD charge transfer device.  
         [0014]     Specifically, the photodiodes contained in the photodiode row  2  are in a staggered arrangement that alternates in sequence on the side of the CCD  1   a  or on the side of the CCD  1   b , whereby each photodiode is connected to one of either the CCD  1   a  or the CCD  1   b  and sends a charge to the CCD it is connected to.  
         [0015]     The CCD  1   a  and  1   b  merge at the output gate  3   a , and are both connected to the charge detection unit  4 .  
         [0016]     Other aspects of the structure of the dual-CCD charge transfer device shown in  FIG. 13  are the same as in the single CCD-type charge transfer device shown in  FIG. 12 .  
         [0017]     In the dual-CCD system shown in  FIG. 13 , increased resolution is obtained by miniaturizing (reducing the dimensions in the arrangement direction) only the photodiodes contained in the photodiode row  2 , while the design rules of the CCD  1   a  and  1   b  are kept unchanged.  
         [0018]     A configuration has conventionally been adopted whereby a charge detection unit  4  is separately provided for each CCD  1   a  and  1   b , and signal output lines  11  are independently provided in alternating fashion on the side of the CCD  1   a  and on the side of the CCD  1   b , however in the case of this type of configuration, it is necessary for the output signals from the signal output lines  11  to be synthesized by an external circuit.  
         [0019]     It is for this reason that a system was developed for receiving the charge delivered from the two CCD  1   a  and  1   b  using a single charge detection unit  4 , as shown in  FIG. 13 , in order to eliminate the synthesis of output signals by an external circuit.  
         [0020]      FIG. 14  is a plan view showing the structure of a charge transfer device having a staggered photodiode arrangement with a two-pixel structure.  
         [0021]     In the charge transfer device shown in  FIG. 14 , the same symbols are used for structural elements that are the same as those in the charge transfer device shown in  FIG. 13 , and description thereof is omitted.  
         [0022]     As shown in  FIG. 14 , the charge transfer device having a staggered photodiode arrangement with a two-pixel structure has two photodiode rows  2   a  and  2   b  arranged parallel to each other in alternating fashion, and CCD  1   a  and  1   b  corresponding to the photodiode rows  2   a  and  2   b , respectively.  
         [0023]     In this arrangement, the photodiodes contained in the photodiode row  2   a  and the photodiodes contained in the photodiode row  2   b  are arranged so as to be offset by a half pitch with respect to each other in their arrangement direction.  
         [0024]     Other aspects of the structure of the charge transfer device having a staggered photodiode arrangement shown in  FIG. 14  are the same as in the dual-CCD charge transfer device shown in  FIG. 13 .  
         [0025]     In other words, the system shown in  FIG. 14  is a method for obtaining a single output by aligning the two photodiode rows  2 , CCD  1 , and read gates  10  in the single-CCD system in mutually staggered fashion, and synthesizing the charges delivered from the two photodiode rows  2 , CCD  1 , and read gates  10  in the charge detection unit  4 .  
         [0026]     An example of design rules whereby a single-CCD system can be obtained having a photodiode pitch of 8 μm will be described to show what resolution is obtained by the systems shown in  FIGS. 12 through 14 . The aspect that causes resolution to be limited by the design rules is usually the design that is related to the electrode positioning of the CCD.  
         [0027]     First, in a dual-CCD system ( FIG. 13 ), by setting the photodiode dimensions to 4 μm, and, using each CCD  1   a  and  1   b  to transfer every other charge of the photodiodes to the two CCD  1   a  and  1   b , twice the number of pixels can be included in the same pitch length with respect to an 8-μm single CCD system. In this dual CCD system, the electrode pitch of each CCD  1   a  and  1   b  can be designed to the same pitch as the 8-μm single system.  
         [0028]     In the staggered photodiode arrangement with a two-pixel structure ( FIG. 14 ), the dimension of the photodiodes is 8 μm, and the same number of pixels can be included in the same pitch length as in the dual CCD system ( FIG. 13 ) in which the photodiode dimension is 4 μm. The merit of having a large photodiode dimension is that the dynamic range can be increased, specifically, that the S/N ratio can be increased.  
         [0029]      FIG. 15  is a plan view showing the first example of the structure of a charge transfer device having a four pixel-structured staggered photodiode arrangement, and  FIG. 16  is a plan view showing the second example of the structure thereof.  
         [0030]     In the charge transfer devices shown in  FIGS. 15 and 16 , the same symbols are used for structural elements that are the same as those in the charge transfer devices shown in  FIGS. 12 through 14 , and description thereof is omitted.  
         [0031]     The charge transfer device shown in  FIG. 15  is provided with four photodiode rows  2   a ,  2   b ,  2   c , and  2   d  arranged parallel to each other, and two CCD  1   a  and  1   b.    
         [0032]     Specifically, the photodiode rows  2   a  and  2   b  are arranged on both sides of the CCD  1   a , and the photodiode rows  2   c  and  2   d  are arranged on both sides of the CCD  1   b.    
         [0033]     The photodiodes in the photodiode rows  2   a  through  2   d  are connected to the corresponding CCD (one of either the CCD  1   a  or the CCD  1   b ) via the read gates  10 . Furthermore, among the photodiodes in the photodiode rows  2   a  through  2   d , the terminals thereof that are on the opposite side from the terminal connected to the read gate  10  are connected to the corresponding charge evacuation means among the charge evacuation means  20   a ,  20   b , and  20   c . The photodiodes in the photodiode rows  2   a  and  2   c  that are positioned between the CCD  1   a  and the CCD  1   b  share a common connection to the charge evacuation means  20   b.    
         [0034]     In this arrangement, the photodiode rows  2   a  through  2   d  are arranged so as to be offset by a quarter pitch with respect to each other in their arrangement direction. Therefore, in the charge transfer device shown in  FIG. 15 , it becomes possible to obtain twice the resolution of the dual system ( FIG. 13 ). However, signals must be read for each of the photodiode rows  2   a  through  2   d  separately in the case of the charge transfer device of  FIG. 15 .  
         [0035]     Other aspects of the configuration of the charge transfer device having a four pixel-structured staggered photodiode arrangement shown in  FIG. 15  are the same as those of the charge transfer device having a staggered photodiode arrangement with a two-pixel structure shown in  FIG. 14 .  
         [0036]     The charge transfer device shown in  FIG. 16  is provided with four photodiode rows  2   a ,  2   b ,  2   c , and  2   d  arranged parallel to each other, and four CCD  1   a ,  1   b ,  1   c , and  1   d,  each corresponding to one of the photodiode rows  2   a  through  2   d , respectively.  
         [0037]     The photodiodes in the photodiode rows  2   a  through  2   d  are connected to the corresponding CCD (one of the CCD  1   a  through  1   d ) via the read gates  10 . Furthermore, among the photodiodes in the photodiode rows  2   a  through  2   d , the terminals that are on the opposite side from the terminal connected to the read gate  10  are connected to the corresponding charge evacuation means among the charge evacuation means  20   a ,  20   b . The photodiode rows  2   a  and  2   b  are positioned between the CCD  1   a  and the CCD  1   b , and these photodiode rows  2   a  and  2   b  share a common connection to the charge evacuation means  20   a . In the same manner, the photodiode rows  2   c  and  2   d  are positioned between the CCD  1   c  and the CCD  1   d , and these photodiode rows  2   c  and  2   d  share a common connection to the charge evacuation means  20   b.    
         [0038]     In the case of the charge transfer device shown in  FIG. 16 , the CCD  1   a  and  1   b  are connected to the charge detection units  4  via the output gates  3   a . Furthermore, a reset gate  5 , a drain  6 , a power supply line  8 , a source follower amplifier  7 , a ground line  9 , and a signal output line  11  are provided on the side of the CCD  1   a  and on the side of the CCD  1   b , in the same manner as in the charge transfer devices ( FIGS. 12 through 15 ) described above.  
         [0039]     The CCD  1   c  and  1   d  are also connected to a charge detection unit  4  via an output gate  3   a . A reset gate  5 , a drain  6 , a power supply line  8 , a source follower amplifier  7 , a ground line  9 , and a signal output line  11  are provided on the side of the CCD  1   c  and on the side of the CCD  1   d , in the same manner as in the charge transfer devices ( FIGS. 12 through 15 ) described above.  
         [0040]     The signal output line  11  on the side of the CCD  1   a  and  1   b , and the signal output line  11  on the side of the CCD  1   c  and  1   d  are connected to a signal switch  101 , and the signal switch  101  is connected to a signal output line  102 .  
         [0041]     Also in the case of the charge transfer device shown in  FIG. 16 , the photodiode rows  2   a  through  2   d  are arranged so as to be offset by a quarter pitch with respect to each other in their arrangement direction, the same as in the case of  FIG. 15 . Therefore, in the charge transfer device shown in  FIG. 16 , it becomes possible to obtain twice the resolution of the dual system ( FIG. 13 ), the same as in the case of  FIG. 15 . However, in the case of the charge transfer device of  FIG. 16 , there must be two outputs (signal output lines  11 ), and the outputs must be synthesized into a single output by the signal switch  101 .  
         [0042]      FIG. 17  is a plan view showing the structure of a 4-CCD, 1-output charge transfer device.  
         [0043]     In the charge transfer device shown in  FIG. 17 , the same symbols are used for structural elements that are the same as those in the charge transfer devices shown in  FIGS. 12 through 16 , and description thereof is omitted.  
         [0044]     The 4-CCD, 1-output charge transfer device shown in  FIG. 17  was developed for obtaining the advantage of the good S/N ratio of a staggered-type device, the advantage of being able to obtain further increased resolution while maintaining the same design rules, and the advantage of being able to reduce the clock (pulse φ1, φ2) frequency for transfer by one-half or less.  
         [0045]     As shown in  FIG. 17 , the 4-CCD, 1-output charge transfer device is provided with two photodiode rows  2   a  and  2   b , and four CCD  1   a ,  1   b ,  1   c , and  1   d.    
         [0046]     Specifically, in the case of the charge transfer device shown in  FIG. 17 , two of the CCD  1   a  through  1   d  are provided for each of the photodiode rows  2   a  and  2   b . The four CCD  1   a  through  1   d  are also connected to one charge detection unit  4 .  
         [0047]     The photodiodes contained in the photodiode row  2   a  are in a staggered arrangement that alternates in sequence on the side of the CCD  1   a  or on the side of the CCD  1   b , whereby each photodiode is connected to one of either the CCD  1   a  or the CCD  1   b  and sends a charge to the CCD it is connected to.  
         [0048]     In the same manner, the photodiodes contained in the photodiode row  2   b  are in a staggered arrangement that alternates in sequence on the side of the CCD  1   c  or on the side of the CCD  1   d,  whereby each photodiode is connected to one of either the CCD  1   c  or the CCD  1   d  and sends a charge to the CCD it is connected to.  
         [0049]     In this arrangement, the two photodiode rows  2   a  and  2   b  are arranged so as to be offset by half the photodiode pitch with respect to each other in their arrangement direction. By offsetting the photodiode rows by a half pitch in this manner, it becomes possible to obtain twice the resolution in a single photodiode row.  
         [0050]     The charges (signal charges) transferred from the two photodiode rows  2   a  and  2   b  to each of the four CCD  1   a  through  1   d  are transferred to the charge detection unit  4  via the output gate  3   c , the output gate  3   d , and the output gate  3   e  in sequence, converted to signal voltages, and detected via the output circuit subsequent to the source follower amplifier  7 .  
         [0051]     Other examples of the conventional art are found in Japanese Unexamined Patent Publication Nos. 11-205532, 4-14842, and 64-14966, for example.  
         [0052]      FIG. 18  is a partial magnified view showing the bottom portion the polysilicon electrode in the 4-CCD, 1-output charge transfer device ( FIG. 17 ), and  FIG. 19  is a partial magnified view showing the positioning of the polysilicon electrode in the 4-CCD, 1-output charge transfer device.  
         [0053]     As shown in  FIGS. 18 and 19 , an N-well  22  ( FIG. 18 ) is formed on one principal surface of the P-substrate not shown in the diagram, and a first polysilicon layer electrode  24  and a second polysilicon layer electrode  25  (both in  FIG. 19 ) are formed via an insulating film (not shown) on the N-well  22  so as to be arranged in alternating fashion.  
         [0054]     Boron is implanted in the gap of the first polysilicon layer electrode  24 , and an N-negative well  26  is formed in the top layer portion of the N-well  22 . The first polysilicon layer electrode  24  thereby becomes a storage electrode for accumulating a charge, and the second polysilicon layer electrode  25  becomes a barrier electrode.  
         [0055]     The drain  6  adjacent to the reset gate  5  is also composed of an N+positive diffusion layer  27  ( FIG. 18 ).  
         [0056]     In general, decreased charge detection capacity is desired in order to enhance sensitivity in charge transfer devices, and the charge detection unit  4  is therefore made so as to have the smallest surface area possible. Since the charges from four CCD  1   a  through  1   d  are transferred to a single charge detection unit  4  having a small surface area, the channel width is inevitably narrowed (for example, the width in the CCD  1   b  and  1   c  is narrowed from width W 1  to width W 2 ), and differences in the length (the length in the orthogonal direction with respect to the width W 1 ) of the transfer channel inevitably occur due to a lack of symmetry. The length of the transfer channel is an important parameter relating to the transfer speed, and as a result of differences occurring in the transfer channel length, drawbacks occur whereby the transfer efficiency fluctuates between the CCD  1   a  through  1   d.    
         [0057]     In  FIG. 18 , channel separation areas  15   a  through  15   c  (notch-shaped portions formed in the electrode) for preventing charge mixing in the CCD  1   a  through  1   d  extend up to the output gate  3   d  (see  FIG. 19 ). If the channel separation areas  15   a  through  15   c  did not extend up to the output gate  3   d , it would be possible for a portion of the charge at the bottom of the CCD  1   b  to spill over into the CCD  1   a ,  1   c , and  1   d  through the output gate  3   c , and for charge mixing to occur in cases in which, for example, a low-level pulse has been applied to the last electrode of the CCD  1   b , and high-level pulses have been applied to the last electrodes of the CCD  1   a ,  1   c , and  1   d.    
         [0058]     Since the channel separation area extends up to the output gate  3   d , the channel width of the CCD  1   b  and the CCD  1   c  gradually narrows from width W 1  to width W 2  in the direction of transfer. Drawbacks therefore occur whereby the transfer efficiency of the two inside CCD  1   b  and  1   c  among the four CCD  1   a  through  1   d  declines in comparison with that of the two outside CCD  1   a  and  1   d.    
       SUMMARY OF THE INVENTION  
       [0059]     According to one aspect of the present invention, there is provided a charge transfer device comprising 4n (where n is a positive integer) initial-stage charge transfer registers to which a plurality of photoelectric converters is connected, and a charge detection unit detecting a charge transferred from the initial-stage charge transfer registers in sequence via a secondary-stage charge transfer register. The merging of two charge transfer registers adjacent to each other among the initial-stage charge transfer registers into one charge transfer register disposed in the secondary stage is repeated at least once, and the final two charge transfer registers after merging are connected to one charge detection unit.  
         [0060]     According to another aspect of the present invention, there is provided a charge transfer device comprising a plurality of initial-stage charge transfer registers, each being connected to a plurality of photoelectric converters, a secondary-stage charge transfer register coupled to at least two initial-stage charge transfer registers and a charge detection unit coupled to the secondary-stage charge transfer register.  
         [0061]     According to another aspect of the present invention, there is provided a method for driving the charge transfer device, comprising transferring a charge by applying first and second two-phase pulses in an inverse relationship to each other to the charge transfer registers.  
         [0062]     According to the present invention, narrowing can be performed gradually and with good symmetry during merging of the charge transfer registers, allowing fluctuations in transfer efficiency between charge transfer registers to be minimized, and a charge transfer device having good transfer efficiency to be obtained. It is possible to obtain a charge transfer device that is designed for preventing mixing of charges between charge transfer registers and occurrence of devoid of transfer degradation due to the pattern structure thereof. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0063]     The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:  
         [0064]      FIG. 1  is a plan view showing the structure of the charge transfer device according to a first embodiment;  
         [0065]      FIG. 2  is a magnified view of portion A of  FIG. 1 ;  
         [0066]      FIG. 3  is a magnified view of portion B of  FIG. 1 ;  
         [0067]      FIG. 4  is a magnified view of portion C of  FIG. 1 ;  
         [0068]      FIG. 5  is a cross-sectional view along line V-V of  FIG. 2 ;  
         [0069]      FIG. 6  is a cross-sectional view along line VI-VI of  FIG. 4 ;  
         [0070]      FIG. 7  is a time chart showing the operational timing in the case of the first embodiment;  
         [0071]      FIG. 8  is a circuit diagram showing an example of the φ5 and φ6 timing generation circuits;  
         [0072]      FIG. 9  is a partial magnified view showing the bottom portion of the polysilicon electrode in the charge transfer device of  FIG. 1 ;  
         [0073]      FIG. 10  is a partial magnified view showing the positioning of the polysilicon electrode in the charge transfer device of  FIG. 1 ;  
         [0074]      FIG. 11  is a cross-sectional view along-line V-V of  FIG. 2  in the case of the charge transfer device according to a second embodiment;  
         [0075]      FIG. 12  is a plan view showing the structure of a conventional single-CCD charge transfer device;  
         [0076]      FIG. 13  is a plan view showing the structure of a conventional dual-CCD charge transfer device;  
         [0077]      FIG. 14  is a plan view showing the structure of a staggered charge transfer device with a two-pixel structure;  
         [0078]      FIG. 15  is a plan view showing the structure of a first example of a conventional staggered charge transfer device with a four-pixel structure;  
         [0079]      FIG. 16  is a plan view showing the structure of a second example of a conventional staggered charge transfer device with a four-pixel structure;  
         [0080]      FIG. 17  is a plan view showing the structure of a conventional 4-CCD, 1-output charge transfer device;  
         [0081]      FIG. 18  is a partial magnified view showing the bottom portion of the polysilicon electrode in the charge transfer device of  FIG. 17 ; and  
         [0082]      FIG. 19  is a partial magnified view showing the positioning of the polysilicon electrode in the charge transfer device of  FIG. 17 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0083]     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.  
       First Embodiment  
       [0084]      FIG. 1  is a plan view showing the structure of the charge transfer device according to the first embodiment.  
         [0085]     As shown in  FIG. 1 , the charge transfer device according to the present invention embodiment has two photodiode rows  2   a  and  2   b ; four initial-stage CCD  1   a ,  1   b ,  1   c , and  1   d ; and two secondary-stage CCD  1   e  and  1   f.    
         [0086]     The two CCD  1   a  and  1   b  are provided to the photodiode row  2   a , and the two CCD  1   c  and id are provided to the photodiode row  2   b.    
         [0087]     The photodiode rows  2   a  and  2   b  are also each provided with a plurality of photodiodes (photoelectric converters) arranged at a prescribed pitch.  
         [0088]     A read gate  10  is provided between the photodiodes contained in the photodiode rows  2   a  and  2   b  and the CCD  1   a  through  1   d.    
         [0089]     The photodiodes contained in the photodiode row  2   a  are in a staggered arrangement that alternates in sequence on the side of the CCD  1   a  or on the side of the CCD  1   b , whereby each photodiode is connected via a read gate  10  to one of either the CCD  1   a  or the CCD  1   b  and sends a charge to the CCD it is connected to.  
         [0090]     In the same manner, the photodiodes contained in the photodiode row  2   b  are in a staggered arrangement that alternates in sequence on the side of the CCD  1   c  or on the side of the CCD  1   d , whereby each photodiode is connected via a read gate  10  to one of either the CCD  1   c  or the CCD  1   d  and sends a charge to the CCD it is connected to.  
         [0091]     In this arrangement, the two photodiode rows  2   a  and  2   b  are arranged so as to be offset by half the photodiode pitch with respect to each other in their arrangement direction. By offsetting the photodiode rows by a half pitch in this manner, it becomes possible to obtain twice the resolution with respect to a single photodiode row.  
         [0092]     The CCD  1   a  and  1   b  merge into the secondary CCD  1   e  (are connected to the CCE  1   e ) via the transfer gates  13   a  and  13   b  in portion A of  FIG. 1 .  
         [0093]     In the same manner, the CCD  1   c  and  1   d  merge into the secondary CCD  1   f  via the transfer gates  13   a  and  13   b  in portion B of  FIG. 1 .  
         [0094]     The CCD  1   e  and  1   f  are also connected to the charge detection unit  4  via the output gates  3   a  and  3   b  in portion C of  FIG. 1 .  
         [0095]     This charge detection unit  4  is provided with a reset gate  5  adjacent thereto, a drain  6  is provided adjacent to the reset gate  5 , and the drain  6  is connected to the power supply line  8  from which a power supply potential is supplied.  
         [0096]     The charge detection unit  4  is also connected to the source follower amplifier  7 .  
         [0097]     This source follower amplifier  7  is provided with interconnected MOS transistors  12   a  and  12   b . Among these components, the source of the MOS transistor  12   a  is connected to the power supply line  8 , the gate thereof is connected to the charge detection unit  4 , and the drain thereof is connected to the source of the MOS transistor  12   b . The gate of the MOS transistor  12   b  is connected to the power supply line  8 , and the drain thereof is connected to the (GND) line  9  from which a ground (GND) potential is supplied. Furthermore, the point at which the MOS transistors  12   a  and  12   b  are interconnected is connected to a signal output line  11 .  
         [0098]      FIG. 2  is a magnified view of portion A of  FIG. 1 ;  FIG. 3  is a magnified view of portion B of  FIG. 1 ; and  FIG. 4  is a magnified view of portion C of  FIG. 1 .  
         [0099]     As shown in  FIGS. 2 through 4 , the CCD  1   a  through  1   f  are each composed of a plurality of first polysilicon layer electrodes (first electrodes)  24  and second polysilicon layer electrodes (second electrodes)  25  arranged in alternating stages in the charge transfer direction.  
         [0100]     In the present embodiment, a charge transfer device provided with two-phase-drive CCD  1   a  through  1   f  is described, and the CCD  1   a  through  1   f  are configured such that a charge is transferred by the application of first and second two-phase pulses that are in an inverse relationship to each other.  
         [0101]     In this arrangement, CCD  1   a  and  1   b  constitute a two-phase-drive based on pulses φ1 and φ2 (see  FIG. 7 ); CCD  1   c  and  1   d  constitute a two-phase-drive based on pulses φ3 and φ4 (see  FIG. 7 ); and CCD  1   e  and  1   f  constitute a two-phase-drive based on pulses φ5 and φ6 (see  FIG. 7 ).  
         [0102]     As shown in  FIG. 7 , the pulses φ1, φ2, φ3, and φ4 have the same period. Pulse φ1 and pulse φ2 are inverted with respect to each other into high-level and low-level pulses; pulse φ3 and pulse φ4 are inverted with respect to each other into high-level and low-level pulses; and pulse φ5 and pulse φ6 are inverted with respect to each other into high-level and low-level pulses.  
         [0103]     Pulse φ1 and pulse φ3 are out of phase with each other by a quarter period, and pulse φ2 and pulse φ4 are out of phase with each other by a quarter period.  
         [0104]     Furthermore, the periods of pulse φ5 and pulse φ6 are half the periods of pulses φ1 through φ4.  
         [0105]     More specifically, in the CCD  1   a , the electrode pairs  33  and  34  composed of pairs of first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  adjacent to each other in the charge transfer direction are provided so as to be positioned in alternating fashion in the charge transfer direction. A configuration is adopted whereby pulse  41  is applied as the first pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  34 . At the same time, pulse φ2 is applied as the second pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  33 .  
         [0106]     In the same manner, in the CCD  1   b , the electrode pairs  35  and  36  composed of pairs of first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  adjacent to each other in the charge transfer direction are provided so as to be positioned in alternating fashion in the charge transfer direction. A configuration is adopted whereby pulse φ2 is applied as the second pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  36 . At the same time, pulse φ1 is applied as the first pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  35 .  
         [0107]     In other words, pulse φ1, for example, is applied as the first pulse to the electrode pair  34  positioned furthest downstream of CCD  1   a , which is one of the two mutually merged devices CCD  1   a  and CCD  1   b , and pulse φ2 is applied as the second pulse to the electrode pair  36  positioned furthest downstream of the other CCD  1   b.    
         [0108]     In the same manner, in the CCD  1   c , the electrode pairs  51  and  52  composed of pairs of first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  adjacent to each other in the charge transfer direction are provided so as to be positioned in alternating fashion in the charge transfer direction. A configuration is adopted whereby pulse φ3 is applied as the first pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  52 . At the same time, pulse φ4 is applied as the second pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  51 .  
         [0109]     In the same manner, in the CCD  1   d , the electrode pairs  53  and  54  composed of pairs of first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  adjacent to each other in the charge transfer direction are provided so as to be positioned in alternating fashion in the charge transfer direction. A configuration is adopted whereby pulse φ4 is applied as the second pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  54 . At the same time, pulse φ3 is applied as the first pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  53 .  
         [0110]     In other words, pulse φ3 is applied as the first pulse to the electrode pair  52  positioned furthest downstream of CCD  1   c , which is one of the two mutually merged devices CCD  1   c  and CCD  1   d,  and pulse φ4 is applied as the second pulse to the electrode pair  54  positioned furthest downstream of the other CCD  1   d.    
         [0111]     The phases of the first and second pulses are offset by a quarter period from each other in the pulses applied to CCD  1   a  (first charge transfer register) and CCD  1   b  (second charge transfer register), and in the pulses applied to CCD  1   c  (third charge transfer register) and CCD  1   d  (fourth charge transfer register). In other words, as described above, pulse φ1 and pulse φ3 are out of phase with each other by a quarter period, and pulse φ2 and pulse φ4 are out of phase with each other by a quarter period.  
         [0112]     Pulses φ1 through φ4 are generated by a pulse generation means not shown in the diagram, and are applied to the electrodes  24  and  25 .  
         [0113]     As shown in  FIG. 2  and  FIG. 4 , in the CCD  1   e , the electrode pairs  37  and  38  composed of pairs of first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  adjacent to each other in the charge transfer direction are provided so as to be positioned in alternating fashion in the charge transfer direction. A configuration is adopted whereby pulse φ5 is applied as the first pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  37 . At the same time, pulse φ6 is applied as the second pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  38 .  
         [0114]     In the same manner, in the CCD  1   f,  as shown in  FIG. 3  and  FIG. 4 , the electrode pairs  55  and  56  composed of pairs of first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  adjacent to each other in the charge transfer direction are provided so as to be positioned in alternating fashion in the charge transfer direction. A configuration is adopted whereby pulse φ5 is applied as the first pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  56 . At the same time, pulse φ6 is applied as the second pulse to the first polysilicon layer electrode  24  and second polysilicon layer electrode  25  contained in the electrode pair  55 .  
         [0115]     As shown in  FIG. 4 , in the last two CCD  1   e  and CCD  1   f,  the second polysilicon layer electrodes  25  adjacent to the output gate  3   a  are not part of an electrode pair, and these electrodes are particularly referred to as the final transfer electrodes  14   a  and  14   b.    
         [0116]     Among the final two CCD  1   e  and CCD  1   f,  pulse φ6 is applied as the second pulse to the final transfer electrode  14   a  of the single CCD  1   e,  and pulse φ5 is applied as the first pulse to the final transfer electrode  14   b  of the other CCD  1   f.    
         [0117]     The pulses φ5 and φ6 applied to the final two CCD  1   e  and CCD  1   f  are set to half the period of the pulses applied to the CCD  1   a  through  1   d  of the previous stage.  
         [0118]     In the case of the present embodiment, a configuration is adopted, for example, whereby the pulses φ5 and φ6 applied to the CCD  1   e  and  1   f  of the next stage are generated based on the pulses φ1 through φ4 applied to the CCD  1   a  through  1   d  of the previous stage.  
         [0119]      FIG. 8  is a circuit diagram showing an example of the logic circuit for generating pulses φ5 and φ6 using pulses φ1 through φ4.  
         [0120]     The logic circuit shown in  FIG. 8  is provided with a first AND circuit  41  to which pulse φ2 and pulse φ3 are inputted; a second AND circuit  42  to which pulse φ1 and pulse φ4 are inputted; a third AND circuit  43  to which the outputs from the first AND circuit  41  and second AND circuit  42  are inputted together; a fourth AND circuit  44  to which pulse φ2 and pulse φ4 are inputted; a fifth AND circuit  45  to which pulse φ1 and pulse φ3 are inputted; and a sixth AND circuit  46  to which the outputs from the fourth AND circuit  44  and fifth AND circuit  45  are inputted together. Therefore, the third AND circuit  43  outputs pulse φ5, and the sixth AND circuit  46  outputs pulse φ6.  
         [0121]     By using this type of logic circuit, pulse φ5 is the pulse generated when the pulse φ2 applied to the CCD  1   a  and the CCD  1   b , and the pulse φ3 applied to the CCD  1   c  and the CCD  1   d  are both high level, and when the pulse φ1 applied to the CCD  1   a  and the CCD  1   b , and the pulse φ4 applied to the CCD  1   c  and the CCD  1   d  are both high level. Specifically, pulse φ5 can be used as the first pulse applied to CCD  1   e , which is one of the final two CCD, and as the second pulse applied to CCD  1   f , which is the other of the final two CCD. Also, pulse φ6 is the pulse generated when the pulse  2  applied to the CCD  1   a  and the CCD  1   b , and the pulse φ4 applied to the CCD  1   c  and the CCD  1   d  are both high level, and when the pulse φ1 applied to the CCD  1   a  and the CCD  1   b , and the pulse φ3 applied to the CCD  1   c  and the CCD  1   d  are both high level. Specifically, pulse φ6, can be used as the second pulse applied to CCD  1   e,  which is one of the final two CCD, and as the first pulse applied to CCD  1   f,  which is the other of the final two CCD.  
         [0122]     A more specific description of the shape of the electrodes will next be given.  
         [0123]     As shown in  FIG. 2 , in the portion that extends from the point downstream in the charge transfer direction of the two mutually merged CCD  1   a  and  1   b  to the point upstream of the single CCD  1   e  after the CCD  1   a  and  1   b  are merged, the first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  in each stage in the charge transfer direction are symmetric about the centerline between the two merged CCD  1   a  and  1   b.    
         [0124]     Specifically, the two mutually merged CCD  1   a  and  1   b  and the single merged CCD  1   e  form a substantial Y-shape, for example.  
         [0125]     The second polysilicon layer electrodes  25  in each stage are formed so that the width thereof in the charge transfer direction is substantially constant along the direction that intersects the transfer direction.  
         [0126]     Furthermore, in the portion that extends from the point downstream in the charge transfer direction of the two mutually merged CCD  1   a  and  1   b  to the point upstream of the single merged CCD  1   e,  the first polysilicon layer electrodes  24  in each stage are formed so as to gradually widen towards the centerline between the two merged charge transfer registers, and also so as to gradually narrow away from the centerline. In addition, the wide portions on the side of the aforementioned centerline of the first polysilicon layer electrodes  24  in each stage are formed so as to gradually narrow towards the downstream side in the charge transfer direction.  
         [0127]     In the same manner, as shown in  FIG. 3 , in the portion that extends from the point downstream in the charge transfer direction of the two mutually merged CCD  1   a  and  1   b  to the point upstream of the single CCD  1   e  after the CCD  1   a  and  1   b  are merged, the first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  arranged in each stage in the charge transfer direction are symmetric about the centerline between the two merged CCD  1   a  and  1   b.    
         [0128]     Specifically, the two mutually merged CCD  1   a  and  1   b  and the single merged CCD  1   e  form a substantial Y-shape, for example.  
         [0129]     Furthermore, in the portion extending from the point downstream in the charge transfer direction of the two mutually merged CCD  1   a  and  1   b  to the point upstream of the merged single CCD  1   e,  the first polysilicon layer electrodes  24  in each stage are formed so as to gradually widen towards the centerline between the two merged charge transfer registers, and also so as to gradually narrow away from the centerline. In addition, the wide portion on the side of the aforementioned centerline in the first polysilicon layer electrodes  24  in each stage are designed so as to gradually narrow towards the downstream side of the charge transfer direction.  
         [0130]     Since the electrodes have the type of shape described above, the width in the charge transfer direction of the second polysilicon layer electrodes  25  in each stage can easily be narrowed while a substantially constant width is maintained along the direction that intersects the transfer direction when the two CCD  1   a  and  1   b  are narrowed into one CCD  1   e , and also when the two CCD  1   c  and  1   d  are narrowed into the single CCD  1   f.    
         [0131]      FIG. 5  is a diagram showing the cross-sectional structure along line X-X′ of  FIG. 2 ; and  FIG. 6  is a diagram showing the cross-sectional structure along line Y-Y′ of  FIG. 4 .  
         [0132]     As shown in  FIG. 5 , an N-well  22  is formed on one principal surface of the P-substrate  21 , and the first polysilicon layer electrodes  24  and second polysilicon layer electrodes  25  are formed on the N-well  22  so as to be arranged in alternating fashion.  
         [0133]     Boron is implanted in the gap of the first polysilicon layer electrode  24 , and an N-negative well  26  is formed in the top layer portion of the N-well  22 . The first polysilicon layer electrode  24  thereby becomes a storage electrode for accumulating a charge, and the second polysilicon layer electrode  25  becomes a barrier electrode.  
         [0134]     As shown in  FIG. 6 , an N-negative well  26  is formed by localized barrier boron implantation in a portion of the top layer of the N-well  22  positioned below the final transfer electrode  14   a , and a storage area and a barrier area exist below one electrode (one final transfer electrode  14   a ).  
         [0135]     The gate electrode of the MOS transistor  12   a  of the source follower amplifier  7  formed by the second polysilicon layer electrode  25  is connected to the charge detection unit  4 . The drain  6  adjacent to the reset gate  5  is composed of the N-positive diffusion layer  27 .  
         [0136]     Operation will next be described.  
         [0137]     In  FIG. 1 , the arrows pointing towards the CCD  1   a  through  1   d  from the photodiodes contained in the photodiode rows  2   a  and  2   b  indicate the read direction of charges from each of the photodiodes to the CCD  1   a  through  1   d , and the charges are transferred to different CCD in alternating fashion. In other words, a charge is transferred to the CCD  1   b  from the photodiode on one end in the photodiode row  2   a , a charge is transferred to the CCD  1   a  from the adjacent photodiode, a charge is transferred to the CCD  1   b  from the next adjacent photodiode, and so forth, with charges being transferred from the photodiodes to the corresponding (in other words, to the connected) CCD.  
         [0138]     Charges transferred via the CCD  1   a  and the CCD  1   b  are transferred to the CCD  1   e  in alternating fashion via the transfer gates  13   a  and  13   b . Specifically, when pulse φ1 is low level, and pulse φ5 is high level, a charge is transferred from the CCD  1   a  to the CCD  1   e.  When pulse φ2 is low level, and pulse φ5 is high level, a charge is transferred from the CCD  1   b  to the CCD  1   e.    
         [0139]     In the same manner, charges transferred via the CCD  1   c  and the CCD  1   d  are transferred to the CCD  1   f  in alternating fashion via the transfer gates  13   a  and  13   b.    
         [0140]     Specifically, when pulse φ3 is low level, and pulse φ6 is high level, a charge is transferred from the CCD  1   c  to the CCD  1   f.  When pulse φ4 is low level, and pulse φ6 is high level, a charge is transferred from the CCD  1   d  to the CCD  1   f.    
         [0141]     The transfer gates  13   a  and  13   b  are presented with a DC voltage at which the channel potential at the bottom of the transfer gate  13   b  is higher than at the bottom of the transfer gate  13   a  among the channel potentials at the bottoms of the transfer gates  13   a  and  13   b.    
         [0142]     Charges transferred via the CCD  1   e  and the CCD  1   f  are transferred to the charge detection unit  4  in alternating fashion via the output gates  3   a  and  3   b.    
         [0143]     Specifically, when pulse φ6 is low level, a charge is transferred from the CCD  1   e  to the charge detection unit  4 , and when pulse φ5 is low level, a charge is transferred from the CCD if to the charge detection unit  4 .  
         [0144]     The output gates  3   a  and  3   b  are presented with a DC voltage at which the channel potential at the bottom of the output gate  3   b  is higher than at the bottom of the output gate  3   a  among the channel potentials at the bottoms of the output gates  3   a  and  3   b.    
         [0145]     As a result, a signal charge is outputted in the following sequence: CCD  1   b →CCD  1   d →CCD  1   a →CCD  1   c . The signal charge transferred to the charge detection unit  4  is converted to a voltage, and is outputted via the source follower amplifier  7 . After charge detection, the charge detection unit  4  is reset to the potential of the drain  6  by a reset pulse being applied to the reset gate  5 .  
         [0146]      FIG. 9  is a partial magnified view showing the bottom portion of the electrode near the charge detection unit in the charge transfer device according to the present embodiment; and  FIG. 10  is a partial magnified view showing the positioning of the electrode near the charge detection unit in the charge transfer device according to the present embodiment.  
         [0147]     As shown in  FIG. 9  and  FIG. 10 , in the present embodiment, the four CCD  1   a  through  1   d  are merged into the two CCD  1   e  and  1   f , and the final two CCD  1   e  and  1   f  are merged and connected to the charge detection unit  4 . Therefore, the symmetry is good in comparison with the conventional example, and it becomes possible to make the shapes of the CCD transfer channels substantially identical. Specifically, to merge the various CCD, it is possible to use substantially the same shapes for the transfer channels of CCD  1   a  and CCD  1   b , the transfer channels of CCD  1   c  and CCD  1   d , the transfer channels of CCD  1   a /CCD  1   b  and CCD  1   c /CCD  1   d , and the transfer channels of CCD  1   e  and CCD  1   f . Narrowing can be performed easily and with good symmetry. Therefore, fluctuation in the efficiency of transfer between CCD can be minimized, and a charge transfer device having good transfer efficiency can be obtained.  
         [0148]     Since a charge transfer device can be obtained using half the number of channels compared to the conventional example, extra space appears in the layout area, and even if a channel separation area for preventing charge mixing is formed between CCD, sudden narrowing in the CCD channel width such as that shown in  FIG. 18  can be avoided. There is therefore no occurrence of transfer degradation due to the pattern structure.  
       Second Embodiment  
       [0149]     An example will be described as a second embodiment wherein pulses φ1 through φ4 are set to 5 V, and pulses φ5 and φ6 are set to voltage pulses that are higher than pulses φ1 through φ4 in the charge transfer device described in the first embodiment above.  
         [0150]      FIG. 11  is a cross-sectional view along line X-X′ of  FIG. 2  in the case of the charge transfer device according to the second embodiment.  
         [0151]     The pulses φ5 and φ6 (the voltage pulses that are higher than pulses φ1 through φ4) are increased in voltage and generated as described below using the circuit in  FIG. 8 .  
         [0152]     Specifically, the lower part of the electrodes for generating pulses φ1 through φ4 is designated as the first N-negative well (corresponding to the N-negative well  26  shown in  FIG. 5  and  FIG. 6 ), while the lower part of the electrodes for generating pulses φ5 and φ6 is designated as the second N-negative well  29 . It is thereby possible to vary the potential difference under the first and second polysilicon layer electrodes  24  and  25  for the pulses φ5 and φ6 independently from the pulses φ1 through φ4.  
         [0153]     A potential diagram is shown at the bottom of  FIG. 11 .  FIG. 11  shows a case in which pulse φ5 is low level, and pulse φ6 is high level. The difference between the first potential (potential  1 )  30   a  and the second potential (potential  2 )  30   b , and the difference between the third potential (potential  3 )  30   c  and the fourth potential (potential  4 )  30   d  are adjusted by the concentration of the second N-negative well  29 , and the difference between the first potential  30   a  and the third potential  30   c , or the difference between the second potential  30   b  and the fourth potential  30   d , is adjusted by the voltage value of pulse φ6.  
         [0154]     By the combination of making the voltage of pulse φ6 higher than 5 V and increasing the injection concentration of the second N-negative well  29 , the amount of charge accumulated by the charge accumulating portion  31  in  FIG. 11  is increased in comparison with the side on which pulses φ1 through φ4 are generated.  
         [0155]     When the same amount of charge is transferred as in the case of the above-mentioned first embodiment, the charge transfer channel width of pulses φ5 and φ6 can thereby be narrowed and less space can be used by the second embodiment in comparison with the first embodiment.  
         [0156]     As described above, by the second embodiment, the same effects are obtained as in the abovementioned first embodiment, the charge transfer channel width of pulses φ5 and φ6 can additionally be narrowed, and less space can be used by the second embodiment in comparison with the first embodiment.  
         [0157]     It is apparent that the present invention is not limited to the above embodiment and it may be modified and changed without departing from the scope and spirit of the invention.