Abstract:
An apparatus allowing stable and reliable voice communication between a computer and a network without generating noise due to slips of voice data is disclosed. A FIFO memory section temporarily stores voice data. A clock converter performs a clock conversion between the computer and the network according to a controlled clock signal and a network-extracted clock signal. The amount of data stored in the FIFO memory section is monitored. A frequency of the controlled clock signal is changed depending on the amount of data stored in the FIFO memory section so that the voice data is continuously transferred.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a technique allowing communications between a computer and a network such as a switched telephone network.  
           [0003]    2. Description of the Related Art  
           [0004]    With the widespread use of personal computers (PCs), the demands for voice communication between personal computers through a telephone network are growing. Conventionally, voice data communication is performed using telephone terminal equipment connecting a personal computer to the telephone network. More specifically, the telephone terminal equipment is provided with a phase-locked loop circuit that is used to synchronize to a clock signal extracted from the telephone network.  
           [0005]    It is necessary to synchronize all devices connected to the same communication line and therefore the USB (universal serial bus) interface is used to synchronize the clock of a PC to the clock signal extracted from the telephone network. However, the clock of a PC cannot be controlled from outside. Accordingly, it is difficult or almost impossible to establish synchronization of a PC.  
           [0006]    When clock synchronization is not perfectly established, the clock of a PC that is used to digitize a voice signal and the transmission clock of the telephone network are independently running. In the case where the PC clock frequency is higher than the transmission clock frequency of the telephone network, the digital signal generated by the PC cannot be transmitted to the telephone network. Contrarily, when the PC clock frequency is lower than the transmission clock frequency of the telephone network, data to be transmitted to the telephone network is partly lost, which causes noise due to slips of voice data.  
         SUMMARY OF THE INVENTION  
         [0007]    An object of the present invention is to provide a clock adjustment method and apparatus allowing stable and reliable voice communication between a computer and a network without generating noise due to slips of voice data.  
           [0008]    According to an aspect of the present invention, an apparatus connecting a first network and a second network to transfer data between them, wherein the first and second networks operate at different clock frequencies, respectively, includes: a first interface to the first network; a second interface to the second network; a buffer memory connected to the first interface, for storing data to be transferred to one of the first and second networks; a clock converter connected between the buffer memory and the second interface, performing a clock conversion according to a controlled clock signal corresponding to the first network and an extracted clock signal that is extracted from the second network; a buffer monitor for monitoring an amount of data stored in the buffer memory to produce a buffer status signal; and a clock adjuster for adjusting the controlled clock signal depending on the buffer status signal.  
           [0009]    The clock adjuster may change a frequency of the controlled clock signal so that the amount of data stored in the buffer memory is kept at a predetermined level. The clock adjuster may change a frequency of the controlled clock signal by an amount within a permissible frame clock error which may occur in the first interface.  
           [0010]    According to another aspect of the present invention, an apparatus includes: a USB (universal serial bus) interface to a USB bus connected to the personal computer; a network interface to the switched telephone network; a transmission buffer memory for storing transmission digital voice data that the personal computer transmits; a reception buffer memory for storing reception digital voice data received from the switched telephone network via the network interface; a PCM modulator for modulating the transmission digital voice data to produce a transmission PCM signal; a PCM demodulator for demodulating a reception PCM signal to produce the reception digital voice data; a transmission clock converter connecting the PCM modulator to the network interface, performing a clock conversion according to a controlled clock signal corresponding to the USB interface and an extracted clock signal that is extracted from the second network; a reception clock converter connecting the network interface to the PCM demodulator, performing a clock conversion according to the controlled clock signal and the extracted clock signal; a buffer monitor for monitoring an amount of data stored in each of the transmission and reception buffer memories to produce a buffer status signal; and a clock switching controller for switching a frequency of the controlled clock signal to one selected from a plurality of predetermined frequencies depending on the buffer status signal.  
           [0011]    The clock switching controller may switch a frequency of the controlled clock signal so that the amount of data stored in the buffer memory is kept at a predetermined level. The plurality of predetermined frequencies may be a normal frequency, a lower frequency, and a higher frequency, wherein a difference between each of the lower and higher frequencies and the normal frequency falls into a range within a permissible frame clock error which may occur in the USB interface. The permissible frame clock error may be 5% of a normal frame clock of the USB bus.  
           [0012]    The transmission clock converter may include: a first coder for coding the transmission PCM signal to produce a transmission analog voice signal according to the controlled clock signal; and a first decoder for decoding the transmission analog voice signal to produce network-side transmission PCM signal according to the extracted clock signal. The reception clock converter may include: a second coder for coding network-side reception PCM signal to produce a network-side reception analog voice signal according to the extracted clock signal; and a second decoder for decoding the network-side reception analog voice signal to produce the reception PCM signal according to the controlled clock signal.  
           [0013]    The digital voice data may be transferred through the USB bus in an isochronous mode.  
           [0014]    The transmission buffer memory and the reception buffer memory may be FIFO (first-in-first-out) memories, respectively.  
           [0015]    The transmission buffer memory may include a plurality of FIFO memories and the reception buffer memory comprises a plurality of FIFO memories.  
           [0016]    A control method for a telephone terminal connecting a personal computer and a switched telephone network to transfer voice data between them, includes the steps of: storing digital voice data to be transferred to one of the personal computer and the switched telephone network in a buffer memory; monitoring an amount of data stored in the buffer memory to produce a buffer status signal; adjusting a frequency of a controlled clock signal corresponding to the personal computer depending on the buffer status signal; extracting an extracted clock signal from the switched telephone network; and converting an operation clock between the personal computer and the switched telephone network according to the controlled clock signal and the extracted clock signal.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 is a block diagram showing the configuration of a clock adjustment apparatus according to an embodiment of the present invention;  
         [0018]    [0018]FIG. 2 is a diagram showing a clock adjustment operation of the embodiment when transferring data from a PC to a telephone network; and  
         [0019]    [0019]FIG. 3 is a diagram showing a clock adjustment operation of the embodiment when transferring data from the telephone network to the PC.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0020]    Referring to FIG. 1, a personal computer (PC)  1  and a telephone terminal  3  are connected via a USB bus  2 . The telephone terminal  3  includes a clock adjustment apparatus according to an embodiment of the present invention and is connected to a switched telephone network  4 .  
         [0021]    The telephone terminal  3  is provided with a USB interface  11  allowing isochronous communication with the PC  1  through the USB bus  2 . Here, it is assumed that the USB bus  2  allows 16-byte voice data to be transferred for each frame of 1 msec in the isochronous mode. The output terminal of the USB interface  11  is connected to a PCM (pulse code modulation) modulator  12  through a FIFO (first-in first-out) memory section  101 - 104 . The input terminal of the USE interface  11  is connected to a PCM demodulator  13  through a FIFO memory section  201 - 204 .  
         [0022]    Each FIFO memory section may be composed of a single FIFO memory or a plurality of FIFO memories connected in series. Here, the FIFO memory section between the USE interface  11  and the PCM modulator  12  is composed of 16-byte FIFO memories  101 - 104  and the FIFO memory section between the USB interface  11  and the PCM demodulator  13  is composed of 16-byte FIFO memories  201 - 204 .  
         [0023]    As described later, when 16-byte transmission voice data enters the FIFO memory section  101 - 104  for the first time,, the transmission voice data is sequentially transferred through the FIFO memories  101 - 103  and stored in the FIFO memory  104 , In this manner, transmission voice data is sequentially stored in the FIFO memory section starting from the FIFO memory  104 .  
         [0024]    Contrarily, when 16-byte reception voice data enters the FIFO memory section  201 - 204  for the first time, the reception voice data is sequentially transferred through the FIFO memories  204 - 202  and stored in the FIFO memory  201 . In this manner, reception voice data is sequentially stored in the FIFO memory section starting from the FIFO memory  201 .  
         [0025]    The PCM modulator  12  and PCM demodulator  13  are connected to a USB-side coder/decoder (CODEC)  14 , which is connected to a line-side CODEC  15 . The line-side CODEC  15  is connected to the switched telephone network  4  via a line interface  16 . Here, it is assumed that the line interface  16  transmits and receives an 8-bit PCM signal for each frame of 125 μsec to and from the switched telephone network  4 .  
         [0026]    The USB-side CODEC  14  receives a transmission PCM signal from the PCM modulator  12  and converts it into a transmission analog signal. The line-side CODEC  15  receives the transmission analog signal from the USB-side CODEC  14  and converts it into a line-transmission PCM signal to be transmitted to the switched telephone network  4 . When receiving a reception PCM signal from the line interface  16 , the line-side CODEC  15  converts it into a reception analog signal. The USE-side CODEC  14  receives the reception analog signal from the line-side CODEC  15  to convert it into a USB-reception PCM signal and outputs it to the PCM demodulator  13 .  
         [0027]    The USB-side CODEC  14  converts a transmission PCM signal into analog according to a controlled clock signal supplied from a clock generation switch  17 . The line-side CODEC  15  converts the transmission analog signal into digital according to an operation clock signal supplied from a clock supplier  18  connected to a clock extractor  19 . The clock extractor  19  is connected to the line interface  16  to extract a line clock signal from the switched telephone network  4 . The clock supplier  18  produces the operation clock signal from the line clock signal to operate the line-side CODEC  15 . In this manner, clock conversion is performed such that a PCM signal is converted into an analog signal according to one clock signal and the resultant analog signal is converted into a PCM signal according to the other clock signal.  
         [0028]    The telephone terminal  3  is further provided with a FIFO status monitor  20  that monitors the statuses of respective ones of the FIFO memory sections  101 - 104  and  201 - 204 . More specifically, the FIFO status monitor  20  monitors the amount of transmission data storing in the FIFO memory section  101 - 104  and monitors the amount of reception data storing in the FIFO memory section  201 - 204 . For example, each of the FIFO memories  101 - 104  and  201 - 204  outputs a full-status signal to the FIFO status monitor  20  when the FIFO memory becomes full and outputs an available/empty-status signal until the FIFO memory is full. The details will be described later (see FIGS. 2 and 3).  
         [0029]    The FIFO status monitor  20  outputs a FIFO status signal to a clock controller  21 , which controls the clock generation switch  17  depending on the FIFO status so that an appropriate clock frequency is supplied to the USB-side CODEC  14 . Hereafter, a clock adjustment operation according to the present embodiment will be described in detail.  
       CLOCK ADJUSTMENT  
       [0030]    Referring to FIG. 2, each of the 16-byte FIFO memories  101 - 104  outputs a full-status signal to the FIFO status monitor  20  when the FIFO memory has stored 16-byte transmission voice data for each frame and outputs an empty-status signal when the FIFO memory stores no data. Here, the FIFO status monitor  20  outputs one of four FIFO status signals to the clock controller  21  depending on the amount of transmission voice data stored in the FIFO memories  101 - 104 .  
         [0031]    As shown in FIG. 2, when the FIFO memories  103  and  104  are full and the remaining FIFO memories  102  and  101  are empty, the clock controller  21  controls the clock generation switch  17  so that a normal-frequency (normal-speed) clock signal is supplied to the USB-side CODEC  14 . Here, the period of the normal-frequency clock is 125 μsec. In other words, the clock generation switch  17  supplies the USB-side CODEC  14  with a frame pulse signal having a period of 125 μsec.  
         [0032]    When only the FIFO memory  104  is full and the remaining FIFO memories  101 - 103  are empty, it means that the frequency of the PC-side clock is lower than that of the controlled clock generated by the clock generation switch  17 . Accordingly, the clock controller  21  controls the clock generation switch  17  so that a lower-frequency (lower-speed) clock signal with respect to the normal-frequency clock signal is supplied to the USB-side CODEC  14  to increase the amount of data stored in the FIFO memory section. When the amount of data stored in the FIFO memory section becomes normal, the clock controller  21  controls the clock generation switch  17  so that a normal-frequency (normal-speed) clock signal is supplied to the USB-side CODEC  14 .  
         [0033]    The lower frequency is lower than the normal frequency by an amount within a permissible frame clock error of ±5% which may occur in the USB interface  11  and the PC clock can accommodate. For example, the lower-frequency clock signal has a period of 132 μsec. In other words, the clock generation switch  17  switches the period of a frame pulse signal supplied to the USB-side CODEC  14  from 125 μsec to 132 μsec.  
         [0034]    When the FIFO memories  102 - 104  are full and only the FIFO memory  101  is empty, which is caused by frame pulse jitter on the USB bus  2  and/or by the frequency of the PC-side clock higher than that of the controlled clock generated by the clock generation switch  17 . Accordingly, the clock controller  21  controls the clock generation switch  17  so that a higher-frequency (higher-speed) clock signal with respect to the normal-frequency clock signal is supplied to the USB-side CODEC  14  to decrease the amount of data stored in the FIFO memory section. When the amount of data stored in the FIFO memory section becomes normal, the clock controller  21  controls the clock generation switch  17  so that a normal-frequency (normal-speed) clock signal is supplied to the USB-side CODEC  14 .  
         [0035]    The higher frequency is higher than the normal frequency by an amount within a permissible frame clock error of ±5% which may occur in the USB interface  11  and the PC clock can accommodate. For example, the higher-frequency clock signal has a period of 117 μsec. In other words, the clock generation switch  17  switches the period of a frame pulse signal supplied to the USB-side CODEC  14  from 125 μsec to 117 μsec.  
         [0036]    When the PC  1  starts data transmission in the isochronous mode, transmission voice data sequentially store into the FIFO memories  101 - 104  as described before. When the FIFO memories  104  and  103  become full, the clock generation switch  17  starts supplying the normal-frequency clock signal to the USB-side CODEC  14  under control of the clock controller  21  as described before. If the transmission voice data are stored in the FIFO memories  104  to  102 , the clock controller  21  switches the normal-frequency clock signal to the higher-frequency clock signal. Contrarily, when the FIFO memories  101 - 103  become empty, the clock controller  21  switches the normal-frequency clock signal to the lower-frequency clock signal.  
         [0037]    Referring to FIG. 3, each of the 16-byte FIFO memories  201 - 204  outputs a full-status signal to the FIFO status monitor  20  when the FIFO memory has stored 16-byte reception voice data for each frame and outputs an empty-status signal when the FIFO memory stores no data. Here, the FIFO status monitor  20  outputs one of four FIFO status signals to the clock controller  21  depending on the amount of reception voice data stored in the FIFO memories  201 - 204 .  
         [0038]    As shown in FIG. 3, when the FIFO memories  201  and  202  are full and the remaining FIFO memories  203  and  204  are empty, the clock controller  21  controls the clock generation switch  17  so that a normal-frequency (normal-speed) clock signal is supplied to the USB-side CODEC  14 . Here, the period of the normal-frequency clock is 125 μsec. In other words, the clock generation switch  17  supplies the USB-side CODEC  14  with a frame pulse signal having a period of 125 μsec.  
         [0039]    When only the FIFO memory  201  is full and the remaining FIFO memories  202 - 204  are empty, it means that the frequency of the PC-side clock is higher than that of the controlled clock generated by the clock generation switch  17 . Accordingly, the clock controller  21  controls the clock generation switch  17  so that a higher-frequency (higher-speed) clock signal with respect to the normal-frequency clock signal is supplied to the USB-side CODEC  14  to increase the amount of data stored in the FIFO memory section. When the amount of data stored in the FIFO memory section becomes normal, the clock controller  21  controls the clock generation switch  17  so that a normal-frequency (normal-speed) clock signal is supplied to the USB-side CODEC  14 .  
         [0040]    As described before, the higher frequency is higher than the normal frequency by an amount within a permissible frame clock error of ±5% which may occur in the USB interface  11  and the PC clock can accommodate. Here, the higher-frequency clock signal has a period of 117 μsec.  
         [0041]    When the FIFO memories  201 - 203  are full and only the FIFO memory  204  is empty, it means that the frequency of the PC-side clock is lower than that of the controlled clock generated by the clock generation switch  17 . Accordingly, the clock controller  21  controls the clock generation switch  17  so that a lower-frequency (lower-speed) clock signal with respect to the normal-frequency clock signal is supplied to the USB-side CODEC  14  to decrease the amount of data stored in the FIFO memory section. When the amount of data stored in the FIFO memory section becomes normal, the clock controller  21  controls the clock generation switch  17  so that a normal-frequency (normal-speed) clock signal is supplied to the USB-side CODEC  14 .  
         [0042]    The lower frequency is lower than the normal frequency by an amount within a permissible frame clock error of ±5% which may occur in the USE interface  11  and the PC clock can accommodate. Here, the lower-frequency clock signal has a period of 132 μsec.  
         [0043]    When the line-side CODEC  15  starts operating in response to reception of data from the switched telephone network  4 , the clock generation switch  17  starts supplying the USB-side CODEC  14  with the normal-frequency clock signal. Accordingly, reception voice data sequentially store into the FIFO memories  201 - 204  as described before. When the FIFO memories  201  and  202  become full, the USB interface  11  starts sequentially transferring the stored voice data to the PC  1  through the USB bus  2  in the isochronous mode. When the reception voice data are stored in the FIFO memories  201  to  203 , the clock controller  21  switches the normal-frequency clock signal to the lower-frequency clock signal. Contrarily, when the FIFO memories  202 - 204  become empty, the clock controller  21  switches the normal-frequency clock signal to the higher-frequency clock signal.  
         [0044]    As described above, data transmission and reception can be performed by the telephone terminal  3  according to the clock adjustment operations as shown in FIGS. 2 and 3, respectively. Accordingly, even in the case where the PC clock is not synchronized to the line clock of the switched telephone network  4 , the clock adjustment allows continuous voice data transmission without data slip or noise, resulting in improved stability and reliability on voice data communication.  
         [0045]    In the above embodiment, the FIFO memory section is composed of a plurality of FIFO memories connected in series. It is also possible to use a single FIFO memory having a necessary capacity.