Abstract:
A high-voltage sensing circuit is provided that inhibits or prevents a low-voltage from being inadvertently sensed as a high-voltage during power-up and power-down and triggering a high-voltage operation such as a chip erase. The high-voltage sensing circuit comprises a low-power supply sensing circuit for generating a control signal in response to the detection of a power supply level and a switch, controlled by the control signal, that receives the input voltage and passes an output voltage if the input voltage is greater than a reference voltage. Until the power supply exceeds a certain amount, a switching transistor will be OFF and VIN (the output of the charge pump) will not be high enough. Thus, a low-voltage is prevented from being inadvertently sensed by the high-voltage sensing circuit as a high-voltage and triggering a high-voltage operation such as a chip erase.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field of the Invention 
     The present invention relates to voltage sensing in an integrated circuit, and more specifically, to a high-voltage sensor that prevents a low-voltage from being inadvertently sensed as a high-voltage during power-up and power-down and triggering an unintentional operation. 
     2. Background of the Related Art 
     Many integrated circuits require high-voltage sensor circuitry to detect higher than power supply (V CC ) voltage levels in order to carry out operations such as read/write and erase. For example, on a flash memory EEPROM device, a low-voltage supplied to the device may indicate a read operation is to be performed, whereas a high-voltage (12V) supplied to the device (or internally generated via an on-board charge pump) may indicate a program operation or an erase operation is to be performed. 
     Therefore, in operation, high-voltage sensor circuitry detects the high-voltage, and in response, provides an output signal to other circuitry in the device to cause the device to enter a special operational mode (e.g., program, erase or test mode), other than a normal mode (e.g., read mode). If the high-voltage sensor does not operate properly, or inadvertently senses a low-voltage as a high-voltage, especially at power-up and power-down, a device such as a non-volatile memory may be erroneously programmed, erased, or stressed. 
     Normally, the output of a high-voltage sensor circuit provides a low voltage (V SS  or GROUND). However, if the input to the circuit is greater than a predetermined voltage level, the output switches to a high-voltage (V CC , the power supply voltage). The switch to the high-voltage output occurs if the input voltage is greater than a specified reference voltage level higher than the power supply voltage V CC . 
     During the sequence of coupling the power supply voltage V CC  to the integrated circuit (power-up), or of de-coupling the power supply voltage from the integrated circuit (power-down), many conventional high-voltage sensor circuits may furnish an output signal erroneously indicating that a high-voltage level has been applied to the device. Typically, these conventional high-voltage sensor circuits are designed to detect high-voltage input levels only during normal operation. Therefore, the conventional high-voltage sensor circuits require that the power-up sequence be followed exactly to ensure that the high-voltage sensor circuit does not erroneously furnish an output signal indicating detection of a high-voltage level. 
     One such conventional high-voltage sensing circuit is shown in FIG.  1 . As shown, the conventional high-voltage sensor  1  comprises a plurality of telescopically interconnected transistors  2   a-c , which receive a voltage input, and in accordance therewith, provide a resultant output voltage. Additionally, the sensor  1  comprises a current source  3  and another transistor  4 . 
     Transistor  2   a  is connected at its source/drain terminal with the input signal VIN and its gate terminal is connected with the other source/drain terminal. Transistor  2   b  is connected at its source/drain terminal with the respective source/drain terminal of transistor  2   a , while its gate terminal is connected with the other source/drain terminal. Therefore, a voltage threshold drop occurs across each of diode-connected transistors  2   a  and  2   b.    
     Transistor  2   c  has its source/drain terminal connected with the respective source/drain terminal of transistor  2   b . The gate terminal of transistor  2   c  receives an input voltage source V CC . The other source/drain terminal of transistor  2   c  is connected with a current source  3 . The output VOUT of the circuit  1  is provided at node B. Finally, transistor  4  serves as a keeper transistor to keep the node A at a specific voltage range, such that node A does not float. 
     This conventional circuit suffers from the problems identified above with respect to inadvertent sensing of a low-voltage as a high-voltage during power-up or power-down because the threshold voltage of the gate terminal of FET  2   c  (which is connected with V CC ) is still quite low. Thus, there is a need to provide an improved high-voltage sensing circuit that inhibits or prevents a low-voltage from being inadvertently sensed as a high-voltage, primarily during power-up or power-down, and triggering a high-voltage operation such as a chip erase. 
     SUMMARY OF THE INVENTION 
     A high-voltage sensing circuit is provided that inhibits or prevents a low-voltage from being inadvertently sensed as a high-voltage and triggering a high-voltage operation such as a chip erase primarily during power-up or power-down. 
     The high-voltage sensing circuit comprises a high-voltage sensing circuit, a low-power sensing circuit, and a switch. The switch is controlled by the output signal of the low-power sensing circuit. Therefore, when the low-power sensor is activated, operation of the high-voltage sensing circuit is cut-off. When the low-power sensor is deactivated, i.e. the circuit has risen to a high-voltage status, then the high-voltage sensor is activated. 
     Thus, a low-voltage is prevented from being inadvertently sensed by the high-voltage sensing circuit as a high-voltage and triggering a high-voltage operation such as a chip erase. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional high-voltage sensing circuit. 
     FIG. 2 is a circuit diagram of a high-voltage sensing circuit according to an embodiment of the present invention. 
     FIG. 3 is a circuit diagram of a low-power sensing circuit that generates signal POR_L. 
     FIG. 4 is a graph of signal POR_L vs. time during the power supply V CC  power-up sequence. 
     FIG. 5 is a circuit diagram of a high-voltage sensing circuit according to another embodiment of the present invention. 
     FIG. 6A is a circuit diagram of another conventional high-voltage sensing circuit. 
     FIG. 6B is a signal graph of the voltage signals of the circuit of FIG. 6A illustrating the high-voltage signal problem inherent to the conventional high-voltage sensing circuit of FIG.  6 A. 
     FIG. 7A is a circuit diagram of a high-voltage sensing circuit of another embodiment of the present invention. 
     FIG. 7B is a signal graph of the voltage signals of the circuit of FIG. 7A illustrating the controlled high-voltage signal. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An improved high-voltage sensing circuit  10  is provided that inhibits or prevents a low-voltage from being inadvertently sensed as a high-voltage and triggering a high-voltage operation such as a chip erase, primarily during power-up or power-down. 
     FIG. 2 is a circuit diagram of the high-voltage sensing circuit  10  according to an embodiment of the present invention. As shown in FIG. 2, the high-voltage sensing circuit  10  comprises a plurality of telescopically-connected transistors  20   a-e , a switching transistor  30  interposed between transistors  20   d  and  20   e  and an additional transistor  40 . 
     Transistor  20   a  has its source/drain terminal connected with an input voltage source VIN. The gate terminal of transistor  20   a  is connected with the source/drain terminal, such that transistor  20   a  is diode-connected. 
     Transistor  20   b  has its source/drain terminal connected with the opposing respective source/drain terminal of transistor  20   a . The gate terminal is also connected with the source/drain terminal, such that transistor  20   b  is also diode-connected. 
     Additionally, transistor  20   c  has its source/drain terminal connected with the opposing respective source/drain terminal of transistor  20   b . The gate terminal of transistor  20   c  is also connected with the source/drain terminal, such that transistor  20   c  is additionally diode-connected. Thus, each transistor  20   a-c  provides a threshold voltage drop V t , with transistors  20   a-c  providing a total of 3V t . 
     Transistor  20   d  is a PMOS field effect transistor, while transistor  20   e  is an NMOS field effect transistor. Each of the respective gate terminals of transistors  20   d  and  20   e  is connected to a voltage source V CC . 
     However, transistors  20   d  and  20   e  are separated by a switching transistor  30  that receives, at its gate terminal, signal POR_L, which is the output signal of the low-power sensing circuit  60  to be described herein with reference to FIG.  3 . As will be described, depending upon signal POR_L, operation of the voltage sensing circuit  10  can be shutoff. 
     Still referring to FIG. 2, the switching transistor  30  has a source/drain terminal connected with a source/drain terminal of transistor  20   d  and another source drain terminal connected with a source/drain terminal of transistor  20   e , the opposing source/drain terminal of which is grounded. 
     Transistor  20   d  is further coupled by the respective source/drain terminal connection with transistor  20   c  at node C. Node C serves as a “keeper” node. That is, transistor  40  is diode-connected with its source/drain terminal and gate terminal connected with voltage source V CC . The opposing source/drain terminal and the substrate are coupled to node C, such that node C serves as a “keeper” node so as not to float the node. 
     The output VH of the voltage sensing circuit  10  is provided at node D and propagated through inverter buffers  50 . Therefore, in operation, if signal VIN&gt;V CC +V tpl +3V t , where V CC  is provided from a voltage source, V tpl  is the threshold voltage of the PMOS transistor  20   d , and V t  is the threshold voltage of each of the NMOS transistors  20   a ,  20   b  and  20   c , then output VH is HIGH (VH=1). Therefore, typically, with VCC=3V, VIN=8V, and the current I(IN)=30 μA, then, the high-voltage circuit  10  will be active. 
     FIG. 3 is a circuit diagram of a low-power sensing circuit  90  that generates signal POR_L. The low-power sensing circuit  90  shown in FIG. 3 is described in Assignee&#39;s U.S. Pat. No. 5,181,187 and is herein incorporated by reference in its entirety. In addition, the output of the low-power sensing circuit  90  is coupled to a plurality of logic gates  100  from which signal POR_L is determined. 
     FIG. 4 shows a graph of the output voltage signal POR_L with respect to time. As described with reference to FIG. 2, the high-voltage circuit  10  will be operated only if POR_L is a HIGH logic level. Therefore, a low-voltage can be inhibited or prevented from being inadvertently sensed as a high-voltage and triggering a high-voltage operation such as a chip erase, since switching transistor  30  can selectively cut-off the high-voltage sensing circuit  10  if signal POR_L is less than a specific reference voltage. 
     FIG. 5 shows an alternative embodiment of the high-voltage sensing circuit  150 . Much of the high-voltage sensing circuit  150  is the same as that shown in FIG.  2 . However, instead of comprising a switching transistor, as that of the embodiment of FIG. 2, the voltage sensing circuit  150  shown in FIG. 5 operates on the output signal VH by including a NAND gate  160 , the output of which eliminates inadvertent sensing of a low-voltage as a high voltage. 
     Specifically, the high-voltage sensing circuit  150  shown in FIG. 5 comprises a plurality of telescopically connected transistors  170   a-d , a keeper transistor  180  and a NAND gate  160 . 
     Transistor  170   a  has its source/drain terminal connected with an input voltage source VIN. The gate terminal of transistor  170   a  is connected with the source/drain terminal, such that transistor  170   a  is diode-connected. 
     Additionally, transistor  170   b  has its source/drain terminal connected with the opposing respective source/drain terminal of transistor  170   a . The gate terminal is also connected with the source/drain terminal, such that transistor  170   b  is also diode-connected. Thus, transistors  170   a  and  170   b  each provide a threshold voltage drop V t . 
     Transistor  170   c  is a PMOS field effect transistor, while transistor  170   d  is an NMOS field effect transistor. Each of the respective gate terminals of transistors  170   c  and  170   d  is connected to a voltage source V CC . 
     Transistor  170   c  is coupled by the respective source/drain terminal connection with transistor  170   b  at node I. Node I serves as a “keeper” node. That is, transistor  180  is diode-connected with its source/drain terminal and gate terminal connected with voltage source V CC . The opposing source/drain terminal is coupled to node I, such that node I serves as a “keeper” node so as not to float the node. 
     The output VH of the voltage sensing circuit  150  is provided at node J and propagated through a two-input NAND gate  160 . The other input to NAND gate  160  is the complement of signal POR_L, that is provided by a low-power sensing circuit  90 , such as that shown in FIG.  3 . 
     The NAND gate  160  operates on these inputs and provides an output signal that is propagated through inverter buffers  190 . Therefore, the NAND gate  160  eliminates the possibility of inadvertent sensing of a low-voltage as a high-voltage, performing a similar function as that of the switching transistor  30  of FIG.  2 . 
     In order to illustrate the improvement over the prior art, reference will now be made to FIGS. 6A-7B. FIGS. 6A and 6B show a conventional high-voltage sensing circuit  200  and its respective voltage signals (V IN , V CC  and V H ) at different potentials. 
     In FIG. 6A, transistor  210   a  is diode connected, in that a source/drain terminal is coupled with the gate terminal. The opposite source/drain terminal of transistor  210   a  is coupled with a respective source/drain terminal of transistor  210   b , while the gate terminal of transistor  210   b  is connected to V CC . 
     Node A, the like connection between respective source/drain terminals of transistors  210   a ,  210   b  is further coupled with a respective source/drain terminal of transistor  210   c . Transistor  210   c  is also diode connected, in that its source/drain terminal is connected with its gate terminal, each connected to voltage source V CC . 
     The opposite source/drain terminal of transistor  210   b  is connected with a respective source/drain terminal of transistor  210   d  to form an inverter. Transistor  210   d  has its gate terminal connected with V CC  while its opposite source/drain terminal is grounded. Output voltage VH is provided as the output of the inverter pair  210   b ,  210   d.    
     Thus, in operation, when V IN =6V, and V CC  is charged-up from LOW to HIGH, such as occurs at start-up, output VH is not completely LOW. VH is only LOW from a time T. Prior to time T, output VH may be interpreted as HIGH, which could cause problems in interpretation of voltages for memory purposes. 
     In comparison, a low-voltage sensing circuit  300  according to an embodiment of the invention is shown in FIG. 7A, with respective voltage potential levels (V IN , V CC  and VH) indicated in FIG.  7 B. While a majority of circuit  300  resembles the prior art circuit  200 , in addition, transistor  310  is sandwiched between transistors  210   b  and  210   d . Transistor  310  receives, at its gate terminal, signal POR_L. Therefore, transistor  310  is controlled by the low-power sensing circuit  90 , described in FIG.  3 . 
     In operation, when V IN =6V and V CC  is charged-up from LOW to HIGH, such as occurs during start-up, voltage VH remains constantly LOW. No voltage spike occurs, such as what occurred in the prior art circuit  200  in FIG.  6 A. Therefore, an improved high-voltage sensing circuit can be is provided that inhibits or prevents a low-voltage from being inadvertently sensed as a high-voltage during power-up and power-down and triggering a high-voltage operation such as a chip erase. 
     It should be noted that the above description is not intended to limit the invention to what is described herein. Additional embodiments of the invention can be performed. For example, while the above-described embodiment provided an internal high-voltage input, an external high-voltage input VIN can be supplied without diverging from the invention. In addition, while the above-described embodiment provided a NAND gate as the logic gate of the voltage sensor circuit, a NOR gate could be provided without diverging from the invention.