Abstract:
A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered reference DC bias voltage lowers amplifier gain and output power, thus protecting the amplifier.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is a continuation of U.S. patent application Ser. No. 10/215,802, which was filed on Aug. 9, 2002, now U.S. Pat. No. 6,762,647 and is incorporated herein by reference in its entirety. 

   BACKGROUND 
   1. Field of Invention 
   The invention is related to radio frequency (RF) power amplifier protection circuits. 
   2. Description of the Related Art 
   RF power amplifiers are intended to operate into a particular load impedance. This load impedance is typically set by an impedance matching circuit coupled to an antenna (load) used to radiate the amplified RF signal. In mobile transmitters (e.g., a cellular telephone handset), the proximity of the antenna to nearby objects (e.g., metal shopping carts) changes the load impedance. 
   In load mismatch situations, excess amplifier output power fails to reach the load and must be dissipated by one or more power amplifier transistors in the amplifier. In severe load mismatch conditions, this dissipated power damages or destroys the transistors. To preserve the transistors, the RF power amplifier must withstand load impedances that are mismatched to the load impedance for which the amplifier was designed. However, not all integrated circuit power transistors are capable of withstanding highly mismatched load impedances. Therefore, what is required is a device and a method to effectively protect the power transistors. 
   SUMMARY 
   A radio frequency (RF) amplifier driving a highly mismatched load impedance outputs an RF voltage that is over a predetermined level (overpeak voltage). A peak detector is used to detect the overpeak voltage. If an output overpeak voltage is detected, an emitter follower buffer is used to activate a clamping transistor. The clamping transistor is coupled to the output of a bias circuit, and the activated clamping transistor is used to limit a reference DC bias voltage output from the bias circuit. The reference DC voltage is applied to an RF amplifier—either the amplifier producing the RF output voltage being detected, or a previous amplifier in an amplifier chain that ends with the amplifier producing the RF output voltage being detected. The limited reference DC bias voltage limits the gain of the amplifier. Consequently, the output power of the amplifier producing the overpeak voltage being detected is reduced. Thus, the amplifier is protected when driving a highly mismatched load impedance. 
   In one embodiment a set of diodes is coupled in series between the output of the amplifier being protected and ground. The anode of a peak detector diode is coupled to a node between two diodes in the diode set. The number of semiconductor junctions between the amplifier output and the peak detector diode anode determines the detected voltage. The cathode of the peak detector diode is coupled to the base of an emitter follower buffer and to a capacitor shunting AC to ground. The emitter of the emitter follower is coupled to the base of a clamping transistor. The collector of the clamping transistor is coupled to the collector of a bias transistor. The activated clamping transistor limits the bias transistor collector voltage, which is used as the reference voltage output to the amplifier. In some embodiments the emitter of the emitter follower buffer is coupled to the base of two or more clamping transistors, each clamping transistor being associated with a unique bias circuit. Each unique bias circuit provides a clamped reference voltage to an amplifier in a chain of amplifiers. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a combined diagrammatic and schematic view of an electronic circuit that includes an amplifier and a protection circuit for the amplifier. 
       FIG. 2  is a combined diagrammatic and schematic view of an electronic amplifier. 
   

   DETAILED DESCRIPTION 
   Skilled individuals will understand that certain known circuit elements are omitted from the accompanying drawing so as to more clearly illustrate the embodiment. Skilled individuals will also understand that electrical components such as resistors, capacitors, and diodes are selected due to the electrical properties they possess, and that various actual devices may provide the desired electrical properties. For example, in some embodiments the diodes are diode-connected bipolar transistors. The V+ symbol in the drawings illustrates a supply voltage and is not necessarily the same value at each indicated point. 
     FIG. 1  is a combined diagrammatic and schematic view showing an embodiment of the invention. One embodiment is formed in a gallium arsenide (GaAs) integrated circuit. Other embodiments are formed in other semiconductor materials. As shown in  FIG. 1 , radio frequency (RF) input signal RFIN to be transmitted is received at input terminal  10  and is passed to RF driver amplifier  12  via input impedance matching circuit  14 . Driver amplifier  12  subsequently outputs the RF signal to RF final power amplifier  16  via interstage impedance matching circuit  18 . Power amplifier  16  then outputs signal RFOUT to load  20  (e.g., an antenna) via output impedance matching circuit  22 . In one embodiment, all electrical circuit elements other than load  20  and impedance matching circuit  22  are formed as a single integrated circuit chip. In other embodiments, impedance matching circuit  22  may also be formed on the integrated circuit chip. 
   Impedance matching circuits  14 ,  18 , and  22  are of conventional design and each include a network of at least one inductor and at least one capacitor. Transformers may be used in some embodiments of circuits  14 ,  18 , and  22 . Amplifier circuits  12  and  16  are depicted as including a transistor, which illustrates various known amplifier configurations. In the depicted embodiment, for example, the input signal to the amplifier is received at the base terminal of one or more transistors and the amplified signal is output at the collector terminal(s). In one instance, power amplifier  16  includes several gallium arsenide npn heterojunction bipolar transistors (HBTs) connected in parallel and outputting signal RFOUT from a node common to all collector terminals. 
   Two sets (a set may include one element) of series-connected diodes are connected between the output node  24  of amplifier  16  and ground (e.g., chassis ground). Diode set  26 , which includes subsets  26   a  and  26   b , is forward biased, and diode set  28  is normally reverse biased. These diode sets  26 , 28  provide electrostatic discharge protection and both positive and negative overvoltage protection. 
   Collector voltage of the power amplifier transistor(s) at output node  24  is sampled at node  30  between diode sets  26   a  and  26   b , which act as a voltage divider. In one embodiment, the band gap voltage is approximately 1.3 volts. The number of diodes used in sets  26   a  and  26   b  depends on the amplifier  16  collector voltage at which clamping is desired. In one embodiment, diode set  26   b  includes three diodes (three junctions). The number of diodes in diode set  26   a  is then set by the desired limiting peak voltage, which in one instance is selected to be twice the magnitude of the DC supply voltage. That is, the total number of diodes in sets  26   a  and  26   b , multiplied by 1.3 volts perjunction, is made equal to twice the magnitude of VCC applied to amplifier  16 . Other numbers of diodes may be used. 
   The anode of peak-detector diode  32  is connected to node  30  and the cathode of diode  32  is connected to the base of emitter-follower buffer transistor  34 . The cathode of diode  32  is also connected to ground via capacitor  36 . Capacitor  36  is quickly charged to the peak detected level. The discharge time constant for capacitor  36  is designed to be long (relative to the modulation symbol rate in a digital modulated application) compared to normal envelope modulated periods to provide stable overvoltage protection loop operation. 
   The emitter output of transistor  34  is connected to the base of clamping transistor  38  via resistor  40  and to the base of clamping transistor  42  via resistor  44 . The base and the collector of clamping transistor  38  are connected via capacitor  46 . Similarly, the base and the collector of clamping transistor  42  are connected via capacitor  48 . Capacitors  46  and  48  provide additional filtering in the protection loop response. The emitters of transistors  38  and  42  are connected to ground. The collector of transistor  38  is connected to the collector of bias transistor  50  in bias circuit  52 . In the same way, the collector of transistor  42  is coupled to the collector of bias transistor  54  in bias circuit  56 . DC bias reference voltage VREF 1  is output from the collector terminals of transistors  38 , 50  to power amplifier  16  and is used therein as base bias voltage. Likewise, DC bias reference voltage VREF 2  is output from the collector terminals of transistors  42 , 54  to amplifier  12  and is used therein as base bias voltage. The embodiment shown in  FIG. 1  includes two amplifier stages. Hence, two bias circuit and clamping transistor combinations are used. In embodiments using other than two amplifier stages, a bias circuit and clamping transistor combination may be used for each one or more amplifier stage. 
   Referring to the circuits associated with amplifier  16  as an example, during normal operation in which amplifier  16  drives a reasonably matched load impedance, the voltage in signal RFOUT is insufficient to trigger the clamping operation of transistor  38 . Without clamping transistor  38 , voltage VREF 1  is established by the current in resistor  58 , which is the combined collector current in transistor  50  and current being drawn by a device in amplifier  16 . As amplifier  16  begins to drive a load with a mismatched impedance, the voltage of signal RFOUT increases. At a predetermined voltage set by the number of diodes (i.e., semiconductor junctions) in diode sets  26   a  and  26   b , the effect of this increased signal RFOUT voltage causes current to flow through diode set  26 , peak detector  32 , and emitter follower buffer transistor  34  to the base of clamping transistor  38 . When clamping transistor  38  conducts, the resistor  58  current increases. The increased resistor  58  current causes an increased voltage across resistor  58 , and consequently the value of voltage VREF 1  is lowered. The lowered voltage VREF 1  lowers the current in amplifier  16 , which in turn lowers the voltage of signal RFOUT. The lowered amplifier  16  current corresponds to lowered amplifier  16  power output. Therefore, power dissipated by amplifier  16  due to the mismatched load is reduced and amplifier  16  remains undamaged. A similar action occurs in clamping transistor  42  and bias circuit  56  associated with amplifier  12 , further reducing the power output by amplifier  16 . 
     FIG. 2  is a schematic view that shows electrical connections of an illustrative power amplifier transistor  60  in amplifier  16  which may include other similarly connected power amplifier transistors. In one embodiment, for example, transistor  60  is illustrative of one transistor cell of several GaAs HBT transistor cells having a common collector terminal. As shown in  FIG. 2 , the base of transistor  60  receives voltage VREF 1  from bias circuit  52  via resistor  62  (e.g., a base ballast resistor). The base of transistor  60  also receives an RF signal for amplification from impedance match circuit  18 . The emitter of transistor  60  is coupled to ground through a resistor. The collector of transistor  60  receives a DC supply voltage (e.g., VCC) via inductor  64  and outputs the amplified signal RFOUT. As voltage VREF 1  is lowered, the base-emitter voltage of transistor  60  is lowered, and consequently the power output from transistor  60  is reduced. The circuit topology shown in  FIG. 2  is also illustrative of amplifier  12  circuit topology. 
   TABLE I shows values of components in one embodiment. These values are illustrative and are not limiting. 
   
     
       
             
             
             
             
             
           
         
             
                 
               TABLE I 
             
             
                 
                 
             
             
                 
               Component 
               Value 
               Component 
               Value 
             
             
                 
                 
             
           
           
             
                 
               Resistor 40 
               500 Ohms 
               Capacitor 36 
               30 pF 
             
             
                 
               Resistor 44 
               500 Ohms 
               Capacitor 46 
                5 pF 
             
             
                 
               Transistor 34 
               45 μm 2   
               Capacitor 48 
                5 pF 
             
             
                 
               Transistor 38 
               45 μm 2   
             
             
                 
               Transistor 42 
               45 μm 2   
             
             
                 
                 
             
           
        
       
     
   
   The use of an integrated electrostatic discharge diode array to sense peak voltage in a protection loop to protect against over voltage conditions provides a structure and method that is simpler than more complicated circuits such as ones using directional couplers. Specific embodiments have been used to illustrate the invention, but skilled individuals will understand that various modifications and substitutions may be made. Therefore the invention is limited only by the following claims.