Abstract:
An electrical-optical modulator may function at high data rates and may be realized in comparably low cost silicon base technology, typically in BJT, BiCMOS or CMOS technologies. The output signal path may include a high transition frequency BJT and by using an active load constituted by a MOS driven by an inverted version of the modulating signal that drives the BJT, the falling edge of the output signal is sped up.

Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates to electrical-optical (E-O) modulator interfaces for high speed communication systems, and in particular, to integrated E-O interfaces. 
       BACKGROUND 
       [0002]    E-O interfaces are used in high speed communication systems to convert an electrical signal into a light signal. Typically, an E-O interface includes a driver stage controlled by voltage signals produced in preceding electronic stages and capable to drive E-O coupling elements of the modulator with sufficiently large voltages and currents to modulate a continuous light wave propagating in an optical wave guide. 
         [0003]    In high data rate (DR) applications, the driver stage of an E-O modulator may be of interest since it must provide large output voltage levels with steep rising and falling edges in order to ensure proper operation without degrading the Inter-Symbol Interference (ISI) of a transmitted bit stream. At the same time, the final power stage may have reduced power dissipation, since it contributes significantly to the overall power budget of a typical optical link. 
         [0004]    In order to meet these guidelines, high speed final driver stage implementations for data rates equal to or greater than 25 Gbps rely on the use of comparably expensive materials, such as Gallium Arsenide, Indium Phosphide, Indium Gallium Arsenide, or on expensive technological platforms, such as Silicon-On-Insulator (SOI) (See A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS, Joohwa Kim; Buckwalter, J. F., IEEE Journal of Solid-State Circuits, Vol. 47, 2012 , Page(s): 615-626; Design of an opto-electronic modulator driver amplifier for 40-Gb/s data rate systems, Long, A.; Buck, J.; Powell, R., Journal of Lightwave Technology, Volume: 20, 2002 Page(s): 2015-2021; Ultra-low voltage substrate-removed mach-zehnder intensity modulators with integrated electrical drivers, Dogru, S.; JaeHyuk Shin; Dagli, N., LEOS Annual Meeting Conference Proceedings, 2009. LEOS &#39;09. IEEE, Page(s): 656-657; A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 13-CMOS SOI Technology, Analui, B.; Guckenberger, D.; Kucharski, D.; Narasimha, A., IEEE Journal of Solid-State Circuits, Volume: 41, 2006, Page(s): 2945 - 2955; Power Efficiency Comparisons of Interchip Optical Interconnect Architectures, Palaniappan, A.; Palermo, S., IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 57, Publication Year: 2010, Page(s): 343-347) and use comparably large voltage supplies, up to 5V. Only recently, silicon complementary metal-oxide-semiconductor (CMOS) or BiCMOS implementations have been developed and proposed as viable low cost alternatives (See U.S. Pat. Nos. 7,899,276, 7,515,775, 7,450,787, and 7,039,258.) 
       SUMMARY 
       [0005]    A high speed driver provides an approach to the above discussed guidelines for an electrical-optical modulator to function at high data rates and being realized even in comparably low cost silicon base technology, typically in bipolar junction transistor (BLIT), BiCMOS or CMOS technologies, and requiring relatively low supply voltages (e.g. 2.5V-3.3V). 
         [0006]    The circuit may provide excellent performance in terms of rise times and fall times of the voltage signals applied by the final power stage to the elements of electro-optical coupling of the E-O interface of the modulator and can be used for both digital modulation schemes (e.g. on-off keying (OOK)) and analog modulation schemes (e.g. quadrature phase-shift keying (QPSK)). In some embodiments, the high speed driver may be realized in fully integrated E-O interfaces, e.g. on a silicon photonics platform (either with monolithic integration of electronics with photonics, or with two die, one dedicated to electronics and one to photonics, assembled in the same package), but it is useful also for technological platforms other than based on silicon wafers (e.g. GaAs, InP, InGaAs, SOI). 
         [0007]    The driver may be suitable for any kind of light wave modulator (e.g. Mach Zendher, Ring Resonator, Electro Absorption Modulator). Instead of realizing a single driver, the driver can even be split in several stages for implementing a distributed E-O modulator structure. Use of integrated transmission lines for connecting the driver to distributed replicas of final power stages of corresponding distributed E-O interfaces may allow a precise equalization to the optical delay of the light propagating within the waveguide modulator of the delay of the electrical signal propagating toward the final power stages of the driver. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a schematic block diagram of the driver, according to the present disclosure. 
           [0009]      FIG. 2  shows an exemplary single-ended BiCMOS embodiment. 
           [0010]      FIG. 3  shows an exemplary bias network for the two transistors of the final power stage of the driver, according to the present disclosure. 
           [0011]      FIG. 4  shows an exemplary embodiment of a BiCMOS pre-driver stage, according to the present disclosure. 
           [0012]      FIGS. 5A-5C  shows exemplary embodiments of an intermediate buffer stage for the embodiment of  FIG. 4 . 
           [0013]      FIG. 6  shows an exemplary embodiment of the differential application of the driver, according to the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0014]    For the sake of simplicity, several exemplary embodiments of the driver illustrated in the attached drawings and described in detail contemplate a single ended driven load. As will be appreciated by the skilled person, the typical circuit topology in high speed communication systems is a differential (or pseudo-differential) configuration using a differential (or pseudo-differential) version of the driver. 
         [0015]    A high level block diagram of the driver of this disclosure according to an embodiment is shown in  FIG. 1 . For a BiCMOS implementation, the driver core (i.e. basically the final power stage connected to the driven load) may basically be realized as shown in  FIG. 2 . The A-OUT path is the main signal path through a high transition frequency BJT, Q 1 , intrinsically capable of switching at the high speed contemplated by the application. However, the load of the final power stage Q 1  if typically implemented with a static load element or with a current generator would result in a fast switching at the rising edge but in a relatively slow switching at the falling edge. This is effectively avoided by introducing the MOS M 1 , driven by an inverted version B of the modulating A signal that drives Q 1 , that speeds up the falling edge of the output signal OUT. 
         [0016]    The load Z 1  on the M 1  source may be properly sized for optimal performance: in a basic topology, it may be just a short circuit, but it may be, for example, a resistance with a capacitance in parallel, for simultaneously ensuring proper biasing conditions and enhanced high frequency operation. A current generator Il may be used to ensure proper Q 1  biasing. 
         [0017]      FIG. 3  depicts exemplary alternative input bias networks for properly biasing both Q 1  and M 1 . Since the M 1  contribution to the driver operation is mainly to speed up switching at the falling edge of the output signal OUT, in the example implementation, a capacitance C 1  can be used in parallel with R 2  to provide a proper high frequency signal feeding at the M 1  input. 
         [0018]    Since the AC gain of the driver core is ˜1, a dedicated input gain stage can optionally be added to achieve the desired overall gain and at the same time to ensure a proper level shifting if needed. Such a pre-driver stage is much less critical than the driver core because of the much lower capacitive load that it must drive and thus can be realized, for example, as shown in  FIG. 4 , i.e. sharing R 1  as its output load. 
         [0019]    The load Z 2  on the Q 2  emitter may be properly sized for optimizing performance: in its basic and simplest topology it can be just a short circuit, but it can be, for example, a resistance or a current generator in order to control better the biasing conditions of Q 2 . It should be remarked that the use of a MOS transistor M 1  for speeding up the switching at falling edges is particularly suitable for low supply voltage implementations, but its function may be implemented as well with a BJT. 
         [0020]    Optionally, in order to further optimize high frequency operation of the driver circuit, an intermediate buffer stage can be introduced, as depicted in the alternative exemplary topologies of  FIGS. 5A-5C . Peaking techniques (e.g. series peaking/shunt peaking) can be implemented on any intermediate node to further increase the slope of the rising and falling edges. 
         [0021]    As already noted, the differential embodiment for high speed communication systems, implementing the same functional circuit topologies described above, is a differential (or pseudo-differential) configuration. 
         [0000]    An exemplary differential embodiment of the driver circuit is shown in  FIG. 6 . In the depicted differential embodiment, the signal inverting operation at the gate of M 1  is intrinsically accomplished by the differential version, as shown in  FIG. 6 . This avoids possible delays, intrinsic in the single-ended inverting operation, between the switching edges of A and B signals. In addition, both the load on the Q 2  emitter and the load on the M 1  source can be shared. Moreover, the differential driver circuit, similarly to the single ended version, may include intermediate buffer stages for incrementing the overall gain. 
         [0022]    The load Zload can be split in two series contributions, e.g. in case coupling elements of the E-O modulator interface must be driven with opposite polarities. A pseudo-differential version of the circuit can be obtained by connecting the intermediate node at a fixed voltage level (e.g. gnd). In some embodiments, a pure MOS implementation of the driver circuit is possible by replacing the BJT transistors with MOS ones. Nevertheless, the unique circuit features of the driver of this disclosure also remain valid and advantageous for a pure BJT implementation or for implementation in technological platforms other than silicon based ones (e.g. GaAs, InP, InGaAs) and SOI. 
         [0023]    The embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.