Abstract:
The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a passivation layer is temporarily formed on semiconductor substrate and a process of implanting impurities is conducted by the passivation layer as a protection mask, thereby inducing damages of substrate due to ion implantation processes to be minimized.  
     According to the present invention, implantation of impurities depends on thickness of the passivation layer, so that it is made possible to freely control impurity implantation by controlling thickness of passivation layer. Therefore, it is made possible to control a diffusion range of the lightly doped source/drain electrode.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method of manufacturing a semiconductor device, which may minimize damages of semiconductor substrate due to ion implantation process by using a passivation layer as a protection mask.  
           [0003]    2. Description of the Prior Art  
           [0004]    Recently, as the size of semiconductor devices and the channel length of transistors are rapidly reduced, various kinds of defects including a punch-through are also greatly increased in its incidence, in proportion to such reduction of the channel length.  
           [0005]    In previous consideration of the defects such as punch-through, the prior art has proposed a method, wherein an LDD structure is formed to secure a shallow junction between a source electrode and a drain electrode of transistor, and by such LDD structure, an electric field strength between the source and drain electrodes are naturally reduced.  
           [0006]    The shallow junction of the prior art is disclosed in U.S. Pat. No. 5,319,232 entitled “Transistor having a lightly doped drain”, U.S. Pat. No. 6,521,502 entitled “Solid phase epitaxy activation process for source/drain junction extensions and halo regions”, EP984,487 entitled “Method of making shallow well MOSFET structure”, and so forth.  
           [0007]    First, as shown in FIG. 1, in the prior art, a substrate  10  is provided whose active region is defined by an isolating layer  10   a . A gate electrode  13  having a gate oxide layer pattern  11  and a gate poly layer pattern  12  on the active region of the substrate  10  is formed.  
           [0008]    Then, as shown in FIG. 2, by performing an ion implantation process using the gate electrode  13  as an ion-implantation mask, impurities are lightly doped onto the substrate  10 , forming a source/drain electrode  15  with low concentration for LDD structure on the substrate  10  adjacent to the gate electrode  13 .  
           [0009]    Then, as shown in FIG. 3, spacers  16  are formed on both sidewalls of the gate electrode  13 .  
           [0010]    Then, as shown in FIG. 4, by performing an ion implantation using the spacers  16  as an ion implantation mask, impurities with high concentration are implanted into the substrate  10 , forming a source/drain electrode  17  with high concentration on both sides of the gate electrode  13 .  
           [0011]    Finally, certain subsequent process, such as annealing process, is performed, thus forming a semiconductor device with LDD structure, for example, a transistor.  
           [0012]    In such prior system as described above, in order to form the LDD structure source/drain electrode  15  with low concentration, a process of implanting impurities into the substrate  10  should be preceded, so that certain impact shocks due to implantation of impurities might be applied to the surface of substrate  10 , with the result that a lattice structure of partial silicon atoms constituting the surface of substrate  10  being considerably destroyed.  
           [0013]    In this case, when certain subsequent process, for example, an annealing process, is forcedly performed without conducting separate measures, partial silicon atoms with their lattice structure destroyed due to impact shocks of impurities become separated from the surface of substrate  10  and then being scattered outside by heat applied during the annealing process, thus generating unnecessary defects such as voids on the surface of substrate  10 .  
           [0014]    Such voids continuously have a bad influence on a certain construction formed on the substrate  10 , so that product quality of finally finished semiconductor devices may be degraded below a certain level unless separate measures are conducted so as to remove the voids.  
         SUMMARY OF THE INVENTION  
         [0015]    Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to minimize damages of semiconductor substrate due to an ion implantation of impurities for LDD structure by additionally and temporary forming passivation layers on a part of a semiconductor substrate and performing the ion implantation using the passivation layers as a protection mask.  
           [0016]    In order to accomplish at least these objects, in whole or in parts, there is provided a method of manufacturing a semiconductor device, including: forming a gate electrode on a semiconductor substrate; forming a sidewall layer on both sides of the gate electrode; forming a passivation layer on a portion of the semiconductor substrate excluding the gate electrode and the sidewall layer; forming a first impurity region by implanting the impurities; forming a spacer on both sides of the sidewall layer; and forming a second impurity region by implanting the impurities using the spacer as an ion implantation mask. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0018]    FIGS.  1  to  4  illustrate a procedure of a method of manufacturing a semiconductor device according to the prior art; and  
         [0019]    FIGS.  5  to  12  illustrate a procedure of a method of manufacturing a semiconductor device according to the embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]    Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description of the same or similar components will be omitted.  
         [0021]    As show in FIG. 5, a trench is formed in a device isolating region of a substrate  20  by utilizing sacrificial layer patterns, for example, a nitride layer pattern, a sacrificial oxide layer pattern and so forth, and a gap-filling process of an insulating layer, a patterning process and so forth are further performed, thus forming a device isolating layer  20   a  defining an active region while being filled in the trench.  
         [0022]    Then, a gate insulating layer and a poly silicon layer are successively deposited on the substrate  20  by a chemical vapor deposition (CVD) process, and the gate insulating layer and the poly silicon layer are collectively patterned using a photolithography, so that a gate electrode  23  having a gate insulating layer pattern, for example, a gate oxide layer pattern  21  and a gate poly layer pattern  22  is formed on a part of the active region of the substrate  20  defined by the device isolating layer  20   a.    
         [0023]    When the gate electrode  23  has been formed through the foregoing processes, using CVD process as shown in FIG. 6, a first insulating layer  24   a , for example, an oxide layer, is formed on the substrate  20  to cover the gate electrode  23 , and a second insulating layer  25   a , for example, a nitride layer, is formed on the first insulating layer  24   a.    
         [0024]    Then, as shown in FIG. 7, using a dry etching process having an anisotropic etching feature, for example, a reactive ion etching process, the first and second insulating layers  24   a  and  25   a  are selectively etched in such a way that the first and second insulating layers  24   a  and  25   a  are left only on both sides of the gate electrode  23 , thus forming a sidewall layer  26  consisting of, for example, an oxide layer pattern  24  and a nitride layer pattern  25 , on both sides of the gate electrode  23 .  
         [0025]    When the sidewall layer  26  has been formed through the foregoing processes, performing a selective epitaxial growth process as shown in FIG. 8, a silicon of substrate  20  is grown along a crystal axis thus to form a passivation layer  27  for substrate on the surface of the substrate  20  excluding the gate electrode  23  and the sidewall layer  26 .  
         [0026]    Preferably, the passivation layer  27  has a thickness of 100 to 200 Å.  
         [0027]    Herein, as described above, since the sidewall layer  26  is previously formed on both sides of the gate electrode  23 , the gate electrode  23  is stably maintained at normal state without being damaged even though a series of processes for forming the passivation layer  27  are severely conducted.  
         [0028]    In this case, as described above, the sidewall layer  26  has a dual structure that the oxide layer pattern  24  and the nitride layer pattern  25  are overlapped, so that the sidewall layer can effectively perform a given function of protecting the gate electrode  23 .  
         [0029]    Meanwhile, when the passivation layer  27  has been formed on the surface of the substrate excluding the gate electrode  23  and the sidewall layer  26  through foregoing processes, as shown in FIG. 9, by performing an ion implantation process using the sidewall layer  26  and the passivation layer  27  as an ion implantation mask, impurities are implanted as to be lightly doped into the substrate  20 , thus forming a lightly doped source/drain electrode  28  for LDD structure on both sides of the gate electrode  23 .  
         [0030]    Herein, since the passivation layer  27  has been previously formed on the surface of the substrate  20 , damages applied to the substrate due to the ion implantation of impurities can be considerably reduced comparing with the prior art.  
         [0031]    In the prior art, an implantation with low concentration of impurities into the substrate as a target should be severely preceded without separate protection means, so that certain impact shocks due to implantation of impurities might be applied to the surface of substrate, with the result that a lattice structure of partial silicon atoms constituting the surface of substrate being considerably destroyed.  
         [0032]    However, in the present system, since the passivation layer  27  has been previously formed on the surface of the substrate  20 , damages to be applied to the substrate due to the ion implantation of impurities can be considerably reduced and thus restricted to the minimum.  
         [0033]    Herein, as described above, since the thickness of the passivation layer  27  is maintained at a certain level, preferably, 100 to 200 Å, to the extent that shocks applied to the substrate  20  may be properly mitigated, the lightly doped source/drain electrode  28  formed after the implantation process of impurities can maintain its quality corresponding to that of the conventional lightly doped source/drain electrode formed by the conventional impurity implanting process.  
         [0034]    According to the present invention, since a state of impurity implantation might be sensitively influenced on the thickness of the passivation layer  27 , the impurity implantation can be freely controlled by controlling the thickness of the passivation layer  27 , thus possibly controlling a diffusion range of the lightly doped source/drain electrode  28 .  
         [0035]    As described above, in the present invention, since the sidewall layer  26  for preventing damages of the gate electrode  23  has been previously and additionally formed on both sides of the gate electrode  23 , if impurities are implanted linearly without separate measures, the lightly doped source/drain electrode  28  may not be normally positioned under the sidewall layer  26  due to an interference of the sidewall layer.  
         [0036]    Considering this problem, in the present invention, as shown in the drawings, the impurities for forming the lightly doped source/drain electrode  28  are implanted inclined toward, preferably, the gate electrode  23  at a certain angle.  
         [0037]    Therefore, the impurities implanted into the substrate  20  as a target can be concentratedly implanted under the gate electrode  23  despite the interference of the sidewall layer  26 , with the result that the finished source/drain electrode  28  can be normally positioned under the sidewall layer  26  even a severe condition that the sidewall layer has been formed.  
         [0038]    Meanwhile, when the lightly doped source/drain electrode  28  for LDD structure has been formed through processes described above, as shown in FIG. 10, the passivation layer that has been formed on both sides of the sidewall layer  26  is removed using the etching process.  
         [0039]    In this case, since the sidewall layer  26  is previously formed on both sides of the gate electrode  23 , the gate electrode  23  is stably maintained at normal state without being damaged even though a series of processes for removing the passivation layer  27  are severely conducted.  
         [0040]    Of course, as described above, the sidewall layer  26  has a dual structure that the oxide layer pattern  24  and the nitride layer pattern  25  are overlapped, so that the sidewall layer  26  can effectively perform a given function of protecting the gate electrode  23 .  
         [0041]    When the passivation layer  27  has been removed through the foregoing process, an insulating layer, for example, an oxide layer  30   a , is formed on the substrate  20  using CVD process to cover the sidewall layer  26  and the gate electrode  23 , and as shown in FIG. 12, using a dry etching process having an anisotropic etching feature, for example, a reactive ion etching process, the oxide layer  30   a  is selectively etched in such a way that the oxide layer is left only on both sides of the sidewall layer  26 , thus forming a spacer  30  on both sides of the sidewall layer  26 .  
         [0042]    Then, by performing an ion implantation process using the spacer  30  as an ion implantation mask, impurities with high concentration are implanted into the substrate  20 , thus forming a heavily doped source/drain electrode  29  on both sides of the gate electrode  23 .  
         [0043]    After foregoing processes, a certain subsequent process, for example, an annealing process, is performed so that LDD structure semiconductor devices, for example, transistors, are completely formed.  
         [0044]    According to the aforementioned embodiments of the present invention, passivation layers are additionally and temporarily formed on a part of a semiconductor substrate and an ion implantation of impurities for a lightly doped drain (LDD) structure is performed using the passivation layers as a protection mask, thereby minimizing damages of semiconductor substrate due to the ion implantation process.  
         [0045]    In such system of the present invention, since a state of impurity implantation might be sensitively influenced on the thickness of the passivation layer, the impurity implantation can be freely controlled by controlling the thickness of the passivation layer, thus possibly controlling a diffusion range of the lightly doped source/drain electrode.  
         [0046]    Although preferred embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.  
         [0047]    The entire disclosure of Korean Patent Application No. 10-2002-0087287 filed on Dec. 30, 2002 including specification, claims, drawings and summary are incorporated herein by reference in its entirety.