Abstract:
A storage pixel sensor comprises a photosensor selectively connectable to a reset potential; a switched buffer amplifier having a control terminal coupled to said photosensor, a first terminal connected to a source of a transfer signal, and a second terminal; a storage capacitor coupled to said second terminal of said switched buffer amplifier; and an amplifier coupled to said storage capacitor.

Description:
RELATED APPLICATIONS 
     This application is a Continuation of U.S. patent application Ser. No. 09/108,110 filed Jun. 30, 1998, U.S. Pat. No. 6,054,704. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to image sensor arrays. More particularly, the present invention relates to CMOS storage pixel sensors and arrays for applications such as still cameras and to methods for operating those sensors and arrays. 
     2. The Prior Art 
     Integrated image sensors are known in the art. Such sensors have been fabricated from charge-coupled devices (CCDs) and as bipolar and MOS image sensors. 
     Storage pixel sensors formed from MOS devices are known in the art. MOS storage pixel-sensors employ capacitive storage elements. One such storage pixel sensor and array is disclosed in co-pending application Ser. No. 08/969,383, filed Nov. 13, 1997, entitled INTRA-PIXEL FRAME STORAGE ELEMENT, ARRAY, AND ELECTRONIC SHUTTER METHOD SUITABLE FOR ELECTRONIC STILL CAMERA APPLICATIONS, assigned to the same assignee as the present invention. 
     It is a delicate task to select a satisfactory capacitor value for MOS storage pixel sensors. For good photocharge to voltage gain in the storage pixel sensor, it is desirable to employ a small capacitance. If the capacitor value is too small, however, the storage time of the pixel sensor suffers because the voltage on the small storage capacitance is easily subject to change by mechanisms such as dark current. For good storage integrity, it is desirable to employ a larger capacitor. If the capacitor value is too large, however, the photocharge generated by the photosensor element in the pixel sensor does not cause much of a voltage change on the capacitor during integration of photocharge. 
     It is therefore an object of the present invention to provide a storage pixel sensor and an array of pixel sensors that overcome some of the shortcomings of the prior art. 
     A further object of the present invention is to provide a storage-pixel sensor and an imaging array of storage-pixel sensors that provides good photocharge-to-voltage gain. 
     Another object of the present invention is to provide a storage-pixel sensor and an imaging array of storage-pixel sensors that provides good voltage stability during a storage period. 
     Yet other object of the present invention is to provide a storage-pixel sensor and an imaging array of storage-pixel sensors that provides good photocharge-to-voltage gain and that provides good voltage stability during a storage period. 
     BRIEF DESCRIPTION OF THE INVENTION 
     According to one aspect of the present invention, a storage-pixel sensor with driven capacitor storage and an array of storage-pixel sensors with driven capacitor storage suitable for use in an active-pixel area-array image sensor employing an electronic shutter method are disclosed. 
     According to a presently preferred embodiment, the storage pixel sensor of the present invention comprises a photodiode coupled to a reset potential via a reset switch. A source follower transistor has its gate coupled to the photodiode, its source connected to a storage capacitor-and its drain connected to a control line. The control line has a first voltage during an integration state and a second voltage during a storage state. An amplifier has an input connected to the common connection of the storage capacitor and the source of the source follower transistor and an output that may be connected to a column output line of an array of storage pixel sensors via a select device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES 
     FIG. 1 is a simplified schematic diagram of a storage-pixel sensor according to the present invention. 
     FIG. 2 is a timing diagram showing a first method for the operation of the storage-pixel sensor of FIG.  1 . 
     FIGS. 3 a  and  3   b  are timing diagrams showing two ways to implement a first method for the operation of the storage-pixel sensor of FIG. 1 including the step of terminating the transfer period. 
     FIG. 4 is a timing diagram showing a second method for the operation of the storage-pixel sensor of FIG. 1 including the step of terminating the transfer period. 
     FIGS. 5 a  and  5   b  are timing diagrams showing two ways to implement a method for the operation of a storage-pixel sensor like that of FIG. 1 having a reduced number of metal interconnect lines including the step of terminating the transfer period. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons. 
     Referring first to FIG. 1, a schematic diagram shows storage pixel sensor according to a presently preferred embodiment of the invention. It is contemplated that storage pixel sensor  10  will be disposed in an array of storage pixels, and FIG. 1 illustrates how storage pixel sensor  10  will be connected in an array environment. 
     A photodiode  12 , serving as the photosensor of pixel sensor  10 , has its anode connected to a fixed potential, shown as ground in FIG. 1, and its cathode connected to the source of N-Channel MOS reset transistor  14  serving as a reset switch. The gate of N-Channel MOS reset transistor  14  is connected to RESET control line  16  and its drain is connected to Vref line  18 . The voltage Vref will typically be between about 1 and about 3 volts. 
     An N-Channel MOS switched buffer amplifier transistor  20 , serving as a transfer switch, has its gate connected to the cathode of photodiode  12 , its source connected to a first plate of a storage capacitor  22  and its drain connected to a XFR control line  24 . The other plate of storage capacitor  22  is connected to a fixed potential shown as ground in FIG.  1 . 
     An amplifier comprising N-Channel MOS amplifier transistor  26 , connected as a source follower, has its gate connected to the common connection of the first plate of storage capacitor  22  and the source of N-Channel MOS transfer transistor  20 , and its drain connected to Vcc line  28 . An N-Channel MOS select transistor is connected between the source of N-Channel MOS amplifier transistor  26  and column output line  32  of the array containing the storage pixel sensor  10 . The gate of N-Channel MOS select transistor  30  is connected to row SELECT line  34 . 
     Referring now to FIG. 2, a timing diagram shows the control voltages asserted to and the resulting signal voltages present in the storage pixel sensor  10  of FIG. 1 during the Reset period, Photo Integration period, Frame Store period, and Row-Readout period. The top three traces of FIG. 2 (reference numerals  40 ,  42 , and  44 , respectively) represent the RESET, XFR, and SELECT control signals applied to storage pixel  10  during its operation. The next three traces (reference numerals  46 ,  48 ,  50 , respectively) represent the pixel data signals present at the cathode of the photodiode, the storage capacitor, and the column output line and show how these signals relate to the control signals asserted to the storage pixel sensor  10 . The Reset period is indicated at reference numeral  52 , the Photo Integration period is indicated at reference numeral  54 , the Frame Store period is indicated at reference numeral  56 , and the Row-Readout period is indicated at reference numeral  58 . Persons of ordinary skill in the art will appreciate that the timing of the signals in FIG. 2 is intended to be relative and that accuracy of pulse duration is not intended in the figure. 
     The Reset period  52  begins when the RESET control signal goes high, turning on N-Channel MOS reset transistor  14 , and ends when the RESET control signal again goes low, turning that device off. The RESET control signal is preferably common to all storage pixel sensors in an array. At the beginning of the Reset period  52 , the voltage at the cathode of photodiode  12  (trace  46 ) is forced to Vref. In addition, because the drain of the switched buffer amplifier transistor  20  is low and its gate Is at Vref, storage capacitor  22  is discharged to approximately the voltage at the drain of switched buffer amplifier transistor  20 . Persons of ordinary skill in the art will appreciate that, during the reset operation, the terminal of switched buffer amplifier transistor  20  referred to herein as the “drain” actually acts as the source of the switched buffer amplifier transistor  20 . For consistency in the specification and claims herein, this terminal will be referred to as the drain of the switched buffer amplifier transistor  20 . 
     The Photo Integration period  54  begins when the RESET signal goes low, allowing the voltage at the cathode of the photodiode (trace  46 ) to drop as a result of accumulation of negative photocharge. Because the photocharge is accumulating on the relatively small capacitance of the photodiode  12  and the gate of the N-Channel MOS transfer transistor  14 , the voltage can drop an appreciable amount. 
     As is known in the art of pixel sensors using photodiodes and MOS reset transistors, the low level of the RESET signal  16  (trace  40 ) can be chosen to be a voltage near or above the threshold voltage of reset transistor  14 , thereby establishing an overflow barrier that will divert excess photocharge to the Vref line and prevent the cathode of photodiode  12  from falling below a limiting potential known as an overflow level near or above ground, and thereby preventing blooming of excess photocharge into other nearby pixel sensors. Therefore, a preferable voltage for the low level of the RESET signal  16  is typically in the range of about 0.7 to about 1.5 Volts. 
     The Photo Integration period  54  ends and the Frame Store period  56  begins when the XFR signal (trace  42 ) goes high and pulls the drain of the source follower N-Channel MOS switched buffer amplifier transistor  20  up to a voltage level around that of Vref, preferably about equal to Vcc. This turns on the transfer transistor which charges storage capacitor  22  to approximately a threshold drop below the voltage on the cathode of photodiode  12  and the gate of the transfer transistor resulting from the accumulated photocharge. The XFR control signal is preferably common to all storage pixel sensors in an array. 
     The rising edge of the XFR control signal will cause some capacitive coupling back to the gate of switched buffer amplifier transistor  20  and the cathode of photodiode  12 . Depending on the relative capacitances of the photodiode and the transfer transistor gate, the step up in the potential at the photodiode cathode may be significant, and due to a boostrapping effect there may be a corresponding improvement in the charge-to-voltage gain at the photodiode cathode, similar to that discussed in co-pending application Ser. No. 09/099,116. 
     As will be appreciated by persons of ordinary skill in the art, the voltage on the cathode of photodiode  12  continues to drop from additional photocharge accumulated after the XFR signal has gone high until the pixel sensor saturates sometime into the Frame Store period  56 . As shown in trace  48  of FIG. 2, the voltage on the plate of the capacitor  22  at the source of switched buffer amplifier transistor  20  cannot follow the continuing drop of the photodiode cathode voltage and thus stays constant. The only other connection to the storage capacitor  22  is the gate of the N-Channel MOS amplifier transistor  26  which is ideally an infinite impedance. There is thus no current path to allow the charge on storage capacitor  22  to leak off and lower the stored voltage. The relatively large size of storage capacitor  22  will sustain the voltage stored thereon for a long Frame Store period despite any negligible leakages encountered in this node of the circuit. 
     As will be appreciated by persons of ordinary skill in the art, the photodiode of the storage pixel sensor of FIG. 1 cannot be returned to a reset state during the Frame Store period. In such a case, the raising of the photodiode cathode voltage to Vref would cause the voltage stored on storage capacitor  22  to follow upward and erase the data stored thereon. 
     The voltage on capacitor  22  will follow a log-time curve such that it will rise about 60 mV per decade of time that it is allowed to settle upward, if the voltage on the photodiode  12  remains constant, since the switched buffer amplifier transistor  20  is operating as a source follower with no bias current load. To cause the voltage on capacitor  22  to settle at a precise offset from the voltage on photodiode  12 , it is preferable to make sure the source follower action charging the capacitor  22  stops at a definite time. Two additional operating methods to accomplish this termination of the transfer process in the pixel sensor of the present invention are disclosed herein. 
     A first method for terminating the transfer process according to the present invention is illustrated in the timing diagrams of FIGS. 3 a  and  3   b.  As may be seen in FIGS. 3 a  and  3   b,  a discrete Transfer period  60  is identified in addition to Reset period  52 , Photo-integrate period  54 , Frame Store period  56 , and Row-Readout period  58 . 
     According to this method of operating the pixel sensor of the present invention, the gate of source follower switched buffer amplifier transistor  20  is pulled downward via the reset transistor to turn off switched buffer amplifier transistor  20 . The Transfer period  60  begins at the low-to-high assertion of the XFR control signal, at which time storage capacitor  22  begins to charge through switched buffer amplifier transistor  20 . A predetermined time after the end of the Photo Integration period  54  after the XFR control signal has been asserted, the Vref voltage line  18  is switched to a low potential such as ground (as shown in trace  62 ) and then the reset transistor  14  is turned on to pull the cathode of photodiode  12  and the gate of switched buffer amplifier transistor  20  to ground through reset transistor  14  and Vref line  18 . Reset transistor  14  may be turned on in one of two ways. Either the Reset signal  16  is held at a potential above the threshold of the reset transistor  14  as is shown by the symbol “&gt;Vth” in FIG. 3 a,  or it is switched to such a potential as is shown in FIG. 3 b.  This action terminates the charging of capacitor  22  and ends Transfer period  60 . In either case, placing the low level of the RESET signal (trace  40 ) at a Vth above ground allows for an overflow drain for excess charge in bright pixels to accomplish antiblooming. 
     Referring now to FIG. 4, a timing diagram illustrates a second method for terminating the transfer process according to the present invention. According to this method, the source of switched buffer amplifier transistor  20  is pulled upward via capacitive coupling from a switched potential on the supply voltage Vcc line (trace  64 ) driving the drain of amplifier transistor  26 . During the Reset period  52  and Photo Integration period  54 , the Vcc line  28  is held at a low potential such as ground. A predetermined time after the end of the Photo Integration period  54 , the Vcc line  28  is switched to a higher potential to allow the amplifier transistor  26  to function as a source follower. The rising voltage transition at Vcc  28  couples capacitively to the gate of transistor  26  and the storage-node plate of capacitor  22 , thereby turning off switched buffer amplifier transistor  20 . As described in copending application Ser. No. 09/099,116, this method of switching the Vcc potential leads to improved readout gain and other advantages, and allows the gate capacitance of transistor  26  to serve as the storage capacitor, thereby removing the need for an explicit capacitor  22 . 
     The Frame Store period  56  lasts until the Row Readout period  58  defined by the assertion of the SELECT signal (trace  44 ) to turn on N-Channel MOS select transistor  30  to place the output signal from the amplifier transistor  26  onto the column output line  32 . As shown in trace  50  of FIGS. 2,  3   a,    3   b,  and  4  the voltage on column output line  32  is only related to the signal in the pixel sensor under consideration during assertion of SELECT control signal  44 . The SELECT signal asserted in trace  44  of FIG. 2 is common to all storage pixel sensors in the row of an array containing the storage pixel sensor  10 . Persons of ordinary skill in the art will appreciate that the Frame Store period  56  will be different for pixel sensors in different rows in an array of storage pixel sensors according to the present invention, since the SELECT control signals for storage pixel sensors in different rows will occur at different times. 
     According to another embodiment of the present invention, the number of metal interconnect lines may be reduced by sharing the XFR and Vcc lines in the embodiment of FIG. 1 as indicated by the dashed connection at reference numeral  66 . In this embodiment, a first method for operating the pixel sensor illustrated in FIG. 5 a  and includes the steps of 1) maintaining the combined Vcc/XFR line at a low voltage until the beginning of the Transfer period  60 , and 2) pulling Vref low to cause the pixel sensor to enter the Frame Store period  56  (as in the method illustrated in FIGS. 3 a  and  3   b ). This action pulls the gate of the switched buffer amplifier transistor  20  low, thereby terminating any log-time rise of the voltage on storage capacitor  22  to remove that source of signal level uncertainty. 
     The method illustrated in FIG. 5 b  is the same as that shown in FIG. 5 a  except that the RESET control line  16  is pulled high during the Frame Store period after the Vref line has gone to a low level. This action pulls the cathode of the photodiode  12  to zero volts through reset transistor  14  to stop any change in the voltage at storage capacitor  22 . 
     The storage pixel sensor  10  of FIG. 1 has the advantageous feature of utilizing a lower capacitance comprising the photodiode capacitance and the gate capacitance of the N-Channel MOS switched buffer amplifier transistor switch  20  during integration, and the larger capacitance of storage capacitor  22  during the storage period prior to readout. The smaller photodiode and transistor gate capacitance used during photocharge integration provides a relatively large voltage change in response to accumulated photocharge, but the circuit also provides a larger storage capacitance less susceptible to voltage droop as a result of leakage during the storage period prior to pixel data readout. 
     Illustrative embodiments of the present invention have been disclosed herein. More specifically, embodiments of the present invention employing N-channel MOS transistors have been disclosed. Persons of ordinary skill in the art will recognize that the present invention is not limited to these embodiments and that other equivalent embodiments of the invention are contemplated herein. For example, embodiments of the present invention employing P-channel MOS transistors will readily suggest themselves to persons of ordinary skill in the art from this disclosure. Such persons will readily contemplate the reversal of p-type and n-type materials, the reversal of anode and cathode connections of the photodiode, and the accompanying voltage polarity changes for such embodiments. 
     While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.