Abstract:
A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

Description:
BACKGROUND 
     The invention relates to power semiconductor modules. 
     Conventional power semiconductor modules include one or more power semiconductor chips which are arranged on a plane ceramic substrate which includes a metallization on at least one side. At least one of such ceramic substrates is soldered to a metallic base plate of the module. To improve cooling, the base plate may be pressed against a heat sink. 
     The metallized ceramic substrates are pressed against the heat sink without a metallic base plate in between. To reduce the heat transmission resistance between the substrate and the heat sink, a layer of heat conductive paste is required. As the thermal conductivity of such a heat conductive paste is limited, the thickness of the layer of heat conductive paste needs to be very thin. However, apart from the locations to which downforce is applied to the substrates, the substrates tend to bend upwards, i.e. away from the heat sink. The result is a non-uniform thickness of the heat conductive paste. 
     To avoid this, the downforce is sought to be uniformly distributed over the substrate. For this, mechanical structures are provided to apply pressure onto the substrate all over the substrate area. However, due to the presence of semiconductor chips, bonding wires etc., the options to apply pressure all over the substrate area are limited. 
     For these and other reasons, there is a need for the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
         FIG. 1  illustrates a vertical cross sectional view of an arrangement with a power semiconductor module including a single multilayer substrate as base plate with three metal layers and two ceramic layers which is pressed with the multilayer substrate against a heat sink. 
         FIG. 2  illustrates an enlarged view of an edge area of the power semiconductor module of  FIG. 1 . 
         FIG. 3  illustrates a vertical cross sectional view of a modified edge area of the power semiconductor module of  FIG. 1 , wherein a ceramic layer of the multilayer substrate includes a via which electrically connects the metal layers which are arranged on opposite sides of the ceramic layer. 
         FIG. 4  illustrates a vertical cross sectional view of another modified edge area of the power semiconductor module of  FIG. 1 , wherein the side wall of the housing cover of the module is formed to perform a contact pressure against one of the ceramic layers of the module. 
         FIG. 5  illustrates a vertical cross sectional view of still another edge area of the power semiconductor module of  FIG. 1 , wherein the base plate includes more than three metal layers and more than two ceramic layers, and wherein some of the ceramic layers include vias which are arranged below a semiconductor chip. 
         FIG. 6  illustrates a vertical cross sectional view of an embodiment of a multilayer substrate where the top layer is a structured metal layer, and which is equipped with power semiconductor chips and power supply terminals, wherein an output terminal is located opposite the power supply terminals. 
         FIG. 7  illustrates a vertical cross sectional view of another embodiment of an equipped multilayer substrate where one of the ceramic layers includes a number of vias arranged below a power semiconductor chip, and where two power supply terminals and an output terminal are arranged in the same edge area of the multilayer substrate. 
         FIG. 8  illustrates a vertical cross sectional view of an equipped multilayer substrate, in which one of the power supply terminals is directly soldered or welded to a metal layer which is different from the top metal layer. 
         FIG. 9  illustrates a vertical cross sectional view of an equipped multilayer substrate in which the output terminal is directly soldered or welded to a metal layer different from the top metal layer. 
         FIG. 10  illustrates a vertical cross sectional view of an equipped multilayer substrate including four metal layers and three ceramic layers, where one of the metal layers being different from the top metal layer includes sections which are spaced apart from one another. 
         FIG. 11  illustrates a vertical cross sectional view of an equipped multilayer substrate of a power semiconductor module to be pressed against a heat sink, where the multilayer substrate is formed convex relative to the center of the power semiconductor module. 
         FIG. 12  illustrates a vertical cross sectional view of an equipped multilayer substrate being pressed against a heat sink and formed concave relative to the center of the power semiconductor module. 
         FIG. 13   a  illustrates a circuit diagram of power semiconductor module including a single switch. 
         FIG. 13   b  illustrates a circuit diagram of power semiconductor module including a single switch, where a number of semiconductor chips are switched parallel to one another. 
         FIG. 14  illustrates a circuit diagram of power semiconductor module including a half bridge (“phase leg”). 
         FIG. 15  illustrates a circuit diagram of power semiconductor module including a three phase legs as illustrated in  FIG. 14  connected parallel to one another. 
         FIG. 16  illustrates a circuit diagram of power semiconductor module including a three phase legs as illustrated in  FIG. 14  with separate phase output terminals (“six pack”). 
         FIG. 17  illustrates a circuit diagram of power semiconductor module including a H-Bridge. 
         FIG. 18  illustrates different processes of a procedure for manufacturing a sub-substrate of a multilayer substrate. 
         FIG. 19  illustrates different processes of a procedure for manufacturing a multilayer substrate. 
         FIG. 20  illustrates different processes of another procedure for manufacturing a multilayer substrate. 
         FIG. 21  illustrates different processes of a procedure for manufacturing a pre-curved multilayer substrate. 
     
    
    
     DETAILED DESCRIPTION 
     In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
     It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise. 
     One or more embodiments provide a power semiconductor module with a multilayer substrate. In one embodiment, the multilayer substrate includes a group of metal layers with at least a first metal layer, a second metal layer and a third metal layer, and a group of ceramic layers with at least a first ceramic layer and a second ceramic layer. The layers of the group of metal layers and the layers of the group of ceramic layers are arranged successively in a vertical direction such that the first ceramic layer is arranged between the first metal layer and the second metal layer and that the second ceramic layer is arranged between the second metal layer and the third metal layer. The third metal layer forms the bottom layer of the multilayer substrate. The second ceramic layer includes a top surface facing away from the third metal layer. An electric power circuit of the module includes at least one power semiconductor chip. A housing cover of the module includes a side wall including a bottom surface facing towards the multilayer substrate. Between the bottom surface of the side wall and the top surface of the second ceramic layer an elastic filler is arranged at least partly. 
     Another embodiment provides a power semiconductor arrangement including such power semiconductor module and a heat sink. The power semiconductor module is pressed against the heat sink with the multilayer substrate ahead. 
     Another embodiment provides a multilayer substrate for a power semiconductor module. The multilayer substrate includes a group of metal layers with at least a first metal layer, a second metal layer and a third metal layer, and a group of ceramic layers with at least a first ceramic layer and a second ceramic layer. The layers of the group of metal layers and the layers of the group of ceramic layers are arranged successively in a vertical direction such that the first ceramic layer is arranged between the first metal layer and the second metal layer and that the second ceramic layer is arranged between the second metal layer and the third metal layer. The thickness of the first metal layer and the thickness of the third metal layer is less than or equal to 2 mm. The third metal layer forms an outer surface layer of multilayer substrate. 
       FIG. 1  is a vertical cross sectional view of an arrangement with power semiconductor module  1  which includes a single base plate which is formed as multilayer substrate  3 . The power semiconductor module  1  configured is to be pressed against a heat sink  9  using screws  5 . After inserting the screws  5  into mounting holes  6  the screws  5  are screwed in internal threads  9   a  of the heat sink  9  and the power semiconductor module  1  is detachable connected with the heat sink  9 . The downforce generated by the screws  5  affects mounting areas  4   a  of a housing cover  4  of the semiconductor module  1 . Thus, the multilayer substrate  3  is pressed against the heat sink  9  by the lower parts of the side walls  4   d  of the housing cover  4 . Whereas conventional power semiconductor modules require a base plate to which the module is mounted before the module is pressed against a heat sink, in the power semiconductor module  1  according to the present invention such an additional base plate is dispensable, i.e. the power semiconductor module  1  may be pressed directly against a heat sink  9  with the multilayer substrate  3  ahead. Optionally, a heat conductive paste may be arranged between the multilayer substrate  3  and the heat sink  9 . Instead of or in addition to screws  5  any other mechanism may be applied to directly or indirectly press the multilayer substrate  3  against the heat sink  9 . 
     The multilayer substrate  3  includes three metal layers  11 ,  12 ,  13  and two ceramic layers  21 ,  22  which are arranged in succession and alternately in a vertical direction v. Between any two of the metal layers II,  12 ,  13  at least one of the ceramic layers  21 ,  22  is arranged. 
     Metal layer  11  is the top layer of the multilayer substrate  3 , i.e. the layer facing to the inner area of the module  1 , and structured into sections  11   a ,  11   b ,  11   c ,  11   d ,  11   e ,  11   f . The sections  11   a - 11   f  may form conductive lines and/or conductive areas. To the sections  11   a ,  11   c ,  11   d ,  11   f  power semiconductor chips  40  are directly joint and/or electrically connected by use of a bonding layer  41 , e.g., a soft solder, a conductive adhesive, or a silver including layer which is the result of a low temperature joining technique (LTJT). The power semiconductor chips may be, for example, a controllable power semiconductor such as, e.g., MOSFETs, IGBTs, Thyristors, or power diodes. The upper sides of the power semiconductor chips  40  are connected to one another or to sections  11   b ,  11   e  of the top metallization  11  by bonding wires  42 . The bonding wires  42  may be, e.g., wires made of aluminum or of an aluminum alloy, e.g., an aluminum-magnesium alloy, or wires made of copper or a copper alloy. The bonding may be done, e.g., by ultrasonic bonding. Instead of bonding wires  42  metal clips may be provided which are joined by a low temperature joining technique (LTJT). 
     Power semiconductor chips are semiconductor chips with high and/or high voltage ratings. For example, the current ratings may be greater than 50 A or greater than 75 A, the voltage ratings more than, e.g., 500 V. Moreover, the power semiconductor chips may include chip sizes of more than 5.5 mm×5.5 mm, or of more than 7 mm×7 mm. 
     To externally connect the power semiconductor module  1  to, e.g., a power supply, a load, a control unit, etc., terminals  31 ,  32  and  34  are provided. The terminals  31 ,  32  may, e.g., be formed as power supply terminals and be electrically connected and/or mechanically joint to the sections  11   a ,  11   b ,  11   c ,  11   d ,  11   e ,  11   f . The terminals  34  may be, e.g., control terminals for controllable ones of the power semiconductor chips  40 , or output terminals to provide information regarding the status of the module  1 . 
     Above the power semiconductor chips  40  an optional printed circuit board (PCB)  8  for interconnecting internal driving terminals is provided. The printed circuit board  8  may also be equipped with control electronics for controlling the controllable ones of the power semiconductor chips  40 . Power semiconductor modules including control electronics are also referred to as intelligent power modules (IPM). 
     The lower part of the power semiconductor module  1  is potted with an optional soft potting  51 , e.g., silicone gel. The soft potting  51  may extend in the vertical direction v from the multilayer substrate  3  at least beyond the bonding wires  42 , e.g., to the printed circuit board  8 . Above the soft potting  51  an optional hart potting  52 , e.g., of epoxy, is arranged to electrically insulate and mechanically stabilize the terminals  31 ,  32  and  34  and the printed circuit board  8 . Alternatively, instead of hard potting  52  a soft potting, e.g., silicone, may be provided. Furthermore, the whole power semiconductor module  1  may be free of any hard potting, e.g., epoxy. 
     Terminals mounted directly on the multilayer substrate  3  the module may include terminals which are incorporated in a plastic frame, e.g., in the housing cover or in a housing cover, and be bonded by wires or ribbons etc. to the multilayer substrate  3  or a device, e.g., a semiconductor chip  40  mounted thereon, and/or to the printed circuit board  8  or a device, e.g., a control circuit, mounted thereon. 
     Along the outer edges of the multilayer substrate  3 , an optional filler  7  is provided for cushioning the down force effecting the multilayer substrate  3 . Instead of a filler  7  different from soft potting  51  the filler  7  may be a part of the soft potting  51 . Such cushioning is important as modern power semiconductor modules  1  may include a large number of power semiconductor chips  40  which requires a multilayer substrate  3  including a large area, e.g., of greater than 6 cm×8 cm. For example, the power semiconductor chips  40  may be arranged in more than 2 rows and more than 2 columns, i.e. the number of power semiconductor chips  40  mounted to the multilayer substrate  3  may be more than or equal to 9, or, e.g., more than or equal to 24, or more than or equal to 36. 
     In one embodiment, filler  7  may be used to electrically insulate at least some of the metal layers  11 ,  12 ,  13  from one another. Aside from that, the filler  7  distributes the down pressure from the side wall  4   d  of the housing cover  4  affecting the multilayer substrate  3  when the semiconductor module  1  is pressed against the heat sink  9  with the multilayer substrate  3  ahead. The filler  7  may include a hardness shore A of less than 85, or less than 65. To ensure a required rigidity, hardness shore A of filler  7  may be greater than, e.g., 20, or greater than 40. 
     If the housing cover  4  of the power semiconductor module  1  is pressed against a heat sink with the multilayer substrate  3  ahead, filler  7  will be compressed, i.e. filler  7  causes a cushioning effect. The effective length d 7  of filler  7  being relevant for that cushioning effect is the smallest dimension of the filler  7  that appears between a bottom face  4   f  of the side wall  4   d  and the multilayer substrate  7  in the vertical direction. When the filler  7  is not compressed, i.e. when the power semiconductor module is not pressed against a heat sink, the effective length d 7  may be from 0.1 mm to 1 mm, or from 0.3 mm to 2 mm. It is pointed out that the surface  4   f  is designated as bottom surface because it is facing away from the upper side  4   h  of the housing cover and towards the multilayer substrate  3 . A “bottom surface” of the side wall  4   d  is not necessarily that  4   g  of some surfaces  4   f ,  4   g  of the side wall  4   d  facing away from the upper side of the housing cover, which is furthermost distant from the upper side. 
     As the multilayer substrate  7  protrudes the mounting area  4   a  in the vertical direction towards the exterior of the power semiconductor module  1  by a distance d 1 , filler  7  will be compressed if the power semiconductor module  1  is pressed by use of the mounting area  4   a  against a heat sink with the multilayer substrate  3  ahead. The distance d 1  may be, e.g., from 0.1 mm to 1 mm, or from 0.1 mm to 0.5 mm, or from 0.3 mm to 2.0 mm. 
     The power semiconductor module  1  includes an electrical circuit with the at least one power semiconductor chip  40 . This electrical circuit is electrically connected to at least one of the metal layers  11 ,  12 ,  13  of the multilayer substrate  3 . 
     Hence, the border area, of the metal layers being electrically connected to the electrical circuit may be completely electrically insulated. In this spirit, the border area of a metal layer is the area which is accessible between the ceramic layers  21   22  adjacent to the respective metal layer. 
     In general, all metal layers of the multilayer substrate  3  which are electrically connected to the electrical circuit may be completely insulated against any contact with air or gas inside and surrounding the module  1 . The insulation may be realized by use of the soft potting  51  and/or the filler/glue  7 . In  FIG. 1 , the bottom metal layer  13  is floating, i.e. not connected to the electrical circuit and therefore not completely insulated against contact with air or gas. 
     Optionally, the bottom layer of all metal layers  11 ,  12 ,  13  of the multilayer substrate which are electrically connected to the electrical circuit and all above metal layers may be insulated, e.g., at least in their boarder areas or completely, against contact with air or gas. 
     For assembling the power semiconductor module  1  the prepared multilayer substrate  3  may be equipped with the power semiconductor chips  40 , the bonding wires  42 , the printed circuit board  8 , the bus bars  35  and  36 , and the terminals  31 ,  32  and  34 . Then, the equipped multilayer substrate  3  may be inserted with the terminals  31 ,  32 , and  34  ahead in the housing cover  4  and glued to the side wall  4   d  of the housing cover  4 . The glue may be applied additionally to the filler  7 . Alternatively, the filler act both as filler and glue. Materials suitable as filler and/or glue are, e.g., silicone rubber or any other elastic glue. 
       FIG. 2  illustrates a magnified section of the power semiconductor module  1  of  FIG. 1 . The section includes a mounting area  4   a , the lower part of the side wall  4   d  and an outer edge of the multilayer substrate  3 . The lower part of the side wall  4   d  includes a recess in which the multilayer substrate  3  and the top metal layer  11  extend in the lateral direction r. The gap between the side wall  4   d  and the multilayer substrate  3  is filled with filler  7 . Each of the layers  11 ,  21 ,  12 ,  22 ,  13  of multilayer substrate  3  includes a main face facing towards the upper side of the housing cover  4 , and a further main face facing away from the upper side of the housing cover  4 . Each of the main faces of the layers  11 ,  12 ,  13 ,  21 ,  22  of the multilayer substrate  3  includes an outer edge  11   k ,  12   k ,  13   k ,  21   k  and  22   k , respectively. In the context of the present invention the expression “outer edge” of a layer indicates an outer edge of the complete respective layer, which means, e.g., that an edge of a layer including sections distant from one another is not referred to as “outer edge” if it faces towards another section of that layer. 
     Filler  7  insulates the outer edges  11   k ,  12   k  of metal layers  11  and  12 , respectively, the outer edges  21   k  of ceramic layer  21 , and the outer edge  22   k  of ceramic layer  22  facing towards the center of the module  1 . Such an insulation may be required if a high voltage, e.g., more than 1500 V, shall be applied to metal layers  11  and/or  12 , as a contact between air and the metal layer may result in a partial discharge of the metal layer. In the embodiment of  FIGS. 1 and 2 , the bottom metal layer  13  of substrate  3  is electrically insulated against the metal layer  12  next to it and against the electric power circuit of the module by the bottom ceramic layer  22 . Therefore, filler  7  covers only the outer edges of the upper metal layers  11  and  12  but not of the bottom metal layer  13 . 
     The multilayer substrate  3  includes three metallization layers  11 ,  12 ,  13  and two ceramic layers  21 ,  22 , which are arranged in the vertical direction v. Optionally, the multilayer substrate  3  may include additional metal layers and/or additional ceramic layers. One, some or all of the metal layers  11 ,  12 ,  13  may include thicknesses d 11 , d 12 , and d 13 , respectively, ranging from 0.05 mm to 2 mm, or from 0.25 mm to 2.5 mm. The ceramic layers  21 ,  22  may include thicknesses d 21  and d 22 , respectively, ranging from e.g., 0.1 mm to 2 mm, or from 0.25 mm to 1 mm. The bottom metal layer  13  of the multilayer substrate  3  may include a thickness d 13  of, e.g., less than 2 mm or less than 1 mm. 
     In the embodiment of  FIG. 2 , the metal layers  11 ,  12 ,  13  include identical thicknesses d 11 , d 12  and d 13 , respectively, e.g., 0.5 mm. The upper ceramic layer  21  includes a thickness d 21  of 0.25 mm, the lower ceramic layer  22  a thickness d 22  of 0.38 mm or of 0.63 mm. The thickness d 22  of the bottom ceramic layer  22  of the ceramic layers  21 ,  22  of the multilayer substrate  3  may be greater than or equal to the thickness d 21  of any other ceramic layer  21  of the multilayer substrate  3 . Further, the thickness d 13  of the bottom ceramic layer  22  of the multilayer substrate  3  may be, e.g., less than 2 mm or less than 1 mm. In the lateral direction r, the ceramic layers  21 ,  22  extend beyond the metal layers  11 / 12  and  12 / 13 , respectively, which are arranged next to the respective ceramic layer  21 ,  22 . In particular, if the bottom layer  13  of the multilayer substrate  3  is a metal layer, the bottom ceramic layer  22  may extend beyond that bottom metal layer  13  in each lateral direction r being perpendicular to the vertical direction v. 
     The down pressure with which the multilayer substrate  3  is pressed against the heat sink  9  may be generated by use of a fastener in a mounting area  4   a  which may be a part of the housing cover  4 . In the embodiment of  FIGS. 1 and 2 , the mounting area  4   a  includes mounting holes  6 . The mounting area  4   a  which is provided at the exterior of the housing cover  4 , may include plastic and/or metal parts and may be elastically attached to the housing cover  4  by use of an elastic connection  4   b . The elastic connection  4   b  serves as pressure transfer element and as shock absorber. Such elastic connection  4   b  is designed with respect to the required down pressure and elongation and may be formed as elastic element, e.g., made of or including metal and/or plastics, for example an elastic metal or a plastic bend or a plastic sheet. An elastic connection  4   b  may be an integral part of the housing cover  4 , e.g., a bar of a housing cover made of plastics. Alternatively, an elastic connection  4   b  may be joined to the housing cover  4 , e.g., moulded to it. 
     A modification of  FIG. 2  illustrates  FIG. 3  where at least one ceramic layer  22  of the ceramic layers  21 ,  22  of the multilayer substrate  3  includes one or more vias  10 . The vias  10  may serve to electrically connect the metal layers  12  and  13  adjoining to opposite sides of the ceramic layer  22  in which the via  10  is formed. For example, the vias  10  may be formed cylindrical or as cylinder ring and include a diameter D of, e.g., less than 5 mm, or from 1 mm to 2.5 mm. In  FIG. 3 , the bottom layer  13  of substrate  3 , i.e. the layer facing away from the center of the module  1 , is a metal layer which is electrically insulated against the electric power circuit of module  1 . However, an electric field generated by the electric power circuit may couple into bottom metal layer  13  and cause an electrical discharge in particular in the area of the outer edges  13   k  of bottom metal layer  13 , as the highest strength of electric field occurs at locations where the surface of the metal layer includes its smallest radius of curvature. To reduce or avoid such electrical discharge, bottom metal layer  13  and the metal layer  12  next to it are electrically connected by at least one via  10 , but electrically insulated against the electrical power circuit of the module  1  and, optionally, against all other metal layers  11  of the substrate  3 . As metal layer  12  is electrically connected to the electric potential of bottom metal layer  13 , the strength of the electric field that occurs at the outer edges  13   k  is reduced compared with the electric field that occurs at the outer edges  13   k  when the bottom layer  13  is electrically insulated against metal layer  12  next to it, because two metal layer with four outer edges  13   k ,  12   k  instead of only one metal layer with two outer edges  13   k  are connected to the same electric potential. 
     The ceramic layer  22  is arranged between the bottom metal layer  13  and the metal layer  12  next to the bottom metal layer  13 . The upper of the outer edges  22   k  of the ceramic layer  22  faces away from the bottom metal layer  13 . Filler  7  covers, e.g., completely, at least that upper of the outer edges  22   k . Optionally, filler  7  may also cover the outer edges  12   k ,  21   k  and  11   k  of one, some or all layers  12 ,  21 ,  11  of substrate  3  which are arranged on the side of ceramic layer  22  facing away from the bottom metal layer  13 . 
     As also illustrated in  FIG. 3 , an optional mechanical support may be applied to the multilayer substrate  3  by one or more posts  4   c  which are spaced apart from the outer edges of the multilayer substrate  3 . The posts  4   c  may be a part of the housing cover  4  or be separate therefrom. 
     In the embodiments of  FIGS. 1 ,  2  and  3 , the down pressure from the side wall  4   d  of the housing cover  4  affects the top layer  11  of the multilayer substrate  3 . Alternatively, as illustrated in  FIG. 4 , it is not required that the down pressure affects the top metal layer  11  of the multilayer substrate  3 . In the embodiment of  FIG. 4 , the down pressure caused by the side wall  4   d  of the housing cover  4  affects the ceramic layer  22 . To allow for this, the ceramic layer  22  extends beyond the above layers  11 ,  21  and  12  of the multilayer substrate  3 . 
     As can be seen from  FIG. 5 , the multilayer substrate  3  may also include more than three metal layers  11 ,  12 ,  13 ,  14  and more than three ceramic layers  21 ,  22 ,  23 . To improve heat dissipation from a power semiconductor chip  14  being disposed on the multilayer substrate  3 , one, some or all of the ceramic layers  21 ,  22 ,  23  of the multilayer substrate  3  may include a number of vias  10  in their respective areas below the power semiconductor chip  40 . Additionally, the vias  10  may serve to electrically connect adjacent metal layers. In the recess of the lower part of the side wall  4   d  of the housing cover  4  an optional trench  4   e  is provided. This trench  4   e  serves as reservoir for filler  7  when gluing the multilayer substrate  3  to the housing cover  4 . 
     From  FIGS. 2 to 5  it can be seen that if the power semiconductor module  1  is attached to but not yet pressed against a heat sink with the multilayer substrate  3  ahead, the housing cover  4  is distant from the heat sink. When down pressure increases, filler  7  will be compressed. However, the down pressure affecting the multilayer substrate  3  may be limited to a predefined value by dimensioning the distance d 7  and/or the distance d 3  between the lower end of the side wall  4   d  and the bottom of the multilayer substrate  3  in the vertical direction v. This limitation results from the lower end of the side wall  4   d  which will contact the heat sink when the down pressure increases. As soon as the side wall  4  is in contact with the heat sink, a further increasing down force affecting the housing cover  4  will not result in a further increasing down force affecting the multilayer substrate  3 . The distance d 3  may range, e.g., from 0 μm to 50 μm, or from 50 μm to 300 μm. 
     A further limitation of the down force affecting the multilayer substrate  3  may be achieved by determining the distance d 2  between the side wall  4   d  of the housing cover  4  and the center of the mounting holes  6 . The distance d 2  may be, e.g., greater than or equal to 10 mm. 
       FIG. 6  is a vertical cross sectional view of a multilayer substrate  3  equipped with power semiconductor chips  40  and with terminals  31 ,  32  and  33 . The power semiconductor chips  40  are electrically connected to form a half bridge. The electrical connections of the equipped multilayer substrate  3  are realized by bonding wires  42  and by sections  11   a ,  11   b ,  11   c ,  11   d  of the top metal layer  11 , vias  10  and the metal layer  12 . The terminals  31 ,  32  may be soldered or welded to the sections  11   d ,  11   c , respectively, and serve as power supply terminals. Accordingly, the terminal  33  may be soldered or welded to the section  11   a  of the top metal layer  11  and serve as phase output layer. The electrical connection between the bottom of one of the power semiconductor chips  40  (the left one in  FIG. 3 ) and the power supply terminal  31  is realized by use of the bonding layer  41 , vias  10  and metal layer  12 . For example, the power supply terminals  31 ,  32  on the one hand and the phase output terminal  33  on the other hand may be arranged in opposite boarder areas of the multilayer substrate  3 . 
     As can be seen from  FIG. 7 , the power supply terminals  31 ,  32  and the phase output terminal  33  may be arranged within the same boarder area of the multilayer substrate  3 . 
     According to another embodiment which is illustrated in  FIG. 8 , the power supply terminals  31 ,  32  are arranged in the same boarder area of the multilayer substrate  3 , whereas the phase output terminal  33  is arranged in the inner area of the multilayer substrate  3 . Likewise, the phase output terminal  33  may be arranged in a boarder area of the multilayer substrate  3 , whereas the power supply terminals  31 ,  32  are arranged in an inner area of the multilayer substrate  3 , which can be seen from  FIG. 9 . In  FIG. 8  the power supply terminal  31  and in  FIG. 9  the phase output terminal  33  are not soldered or welded to the top metal layer  11  but to another  12  of the remaining metal layers  12 ,  13 . In  FIG. 9 , metal layer  12  includes sections  12   a  and  12   b  which are arranged distant and electrically insulated from one another by a dielectric  15 . 
     In the embodiments of  FIGS. 6 to 9 , the bottom metal layer  13  of the multilayer substrate  3  is electrically insulated against metal layer  12  next to it. Alternatively, the bottom layer of the multilayer substrate  3  may also be electrically connected with the power semiconductor chips  40 . 
     In the embodiment of  FIG. 10 , which illustrates an equipped multilayer substrate  3  with four metal layers  11 ,  12 ,  13 ,  14  and three ceramic layers  21 ,  22 ,  23 , the bottom metal layer  14  is electrically connected to the power supply terminal  31  for the negative power supply voltage. Alternatively, the bottom metal layer  14  may be electrically connected with the power supply terminal  32  for the positive power supply voltage, or with the phase output terminal  33 . As also illustrated in  FIG. 10 , for electrically connecting the power semiconductor chips  40  also one or more of the lower metal layers  12 ,  13 ,  14  may be used. In  FIG. 10 , metal layer  13  includes sections  13   a ,  13   b  and  13   c  which are arranged distant from one another and electrically insulated by a dielectric  15 . The dielectric  15 , e.g., the unsintered “green” ceramics, may be filled, e.g., pressed, in grooves during the manufacturing process of the multilayer substrate, followed by a sintering step. The grooves may be filled with material identical with the material of one of the ceramic layers  22  or  23  adjacent to metal layer  13  in which the dielectric is arranged. Alternatively or additionally, the grooves may be filled with dielectric potting, e.g., made of plastics, for example polyimide, epoxy, or silicone, via openings which are provided in the metal layers and in the ceramic layers above the groove to be filled. Afterwards, the potting may be hardened, e.g., during a tempering step. 
     The embodiments of  FIGS. 6 to 10  illustrate multilayer substrates  3  being equipped with power semiconductor chips  40  and with terminals  31 ,  32 ,  33  only. However, these equipped multilayer substrates  3  may be completed to power semiconductor modules including the options as described with reference to  FIGS. 1 to 5  and to below  FIGS. 11 to 17 . 
     If a plane multilayer substrate  3  is pressed against the heat sink by a down pressure as explained with reference to  FIG. 1  and the down pressure affects the multilayer substrate  3  for instance in its boarder area, the multilayer substrate  3  will lift off from the heat sink in the inner area of the multilayer substrate  3 . Likewise, if the down force which presses the multilayer substrate  3  against a heat sink in the inner area of a plane multilayer substrate  3 , the multilayer substrate  3  will lift off from the heat sink  9  in the boarder area of the multilayer substrate  3 . In both cases, the heat transmission resistance between the multilayer substrate  3  and the heat sink  9  will increase because of the reduced heat conductivity in the lift-off areas. 
     As illustrated in  FIGS. 11 and 12 , this may be avoided by using a pre-curved multilayer substrate  3 . In  FIG. 11 , the multilayer substrate  3  is pre-curved convex relative to the center of the power semiconductor module  1  which can be seen from areas  2  in which the multilayer substrate  3  is spaced apart from the heat sink  9 . If a down force affects the multilayer substrate  3  in the boarder area of the multilayer substrate  3  to press the substrate  3  against the plane surface of the heat sink  9 , the multilayer substrate  3  will deform from its pre-curved shape to an almost plane multilayer substrate  3 . 
     In  FIG. 12 , the multilayer substrate  3  is pre-curved concave relative to the center of the power semiconductor module  1  which can be seen from an area  2  in which the multilayer substrate  3  is spaced apart from the heat sink  9 . If a down pressure which is created by a center screw  5  and transmitted by a post  4   c  of the housing cover  4  affects the multilayer substrate  3  in the center area of the multilayer substrate  3 , the substrate  3  is pressed against the plane surface of the heat sink  9  and the multilayer substrate  3  will deform from its pre-curved shape to an almost plane multilayer substrate  3 . At the lower end of the post  4   c  a filler  7  may be provided. This filler may include the same properties as the filler  7  between the lower ends of the side walls  4   d.    
     In the embodiments described above the power semiconductor modules may include at least one power semiconductor chip. The following  FIGS. 13 to 17  illustrate circuit diagrams of embodiments of power semiconductor modules  1  including a multilayer substrate as described above. 
       FIG. 13   a  is a circuit diagram of a single switch power semiconductor module  1 . The single switch includes an IGBT  40   a  and an optional free wheeling diode  40   b  switched antiparallel to IGBT  40   a . For its external connections the module  1  includes terminals  31 ,  32  for power supply, and a control terminal  34 . The IGBT  40   a  may consist of a single semiconductor chip, or alternatively, as illustrated in  FIG. 13   b , include a number of semiconductor chips  40   a  switched parallel to one another. 
       FIG. 14  is a circuit diagram of a half bridge power semiconductor module  1 . The half bridge (“phase leg”) includes an upper leg I and a lower leg II. The upper leg I includes an IGBT  40   a  and an antiparallel free wheeling diode  40   b , the lower leg an IGBT  40   c  and an antiparallel free wheeling diode  40   d . The IGBTs  40   a ,  40   c  are connected in series. During normal operation, none or one of but not both IGBTs  40   a ,  40   c  are switched on at the same time. Such a half bridge allows for connecting one of the electric potentials applied to the power supply terminals  31  and  32  with the phase output terminal  33  and to a load  60  connected therewith. 
     To improve ampacity, instead of just one IGBT and one freewheeling diode per leg I, II each of the legs I, II may include more than one IGBT and/or more than one freewheeling diode.  FIG. 15  is a circuit diagram of such a power semiconductor module  1 . The upper leg I includes a number of IGBTs  40   a ′ connected parallel to one another, and a number of freewheeling diodes  40   b ′ connected parallel to one another. The IGBTs are connected antiparallel to the freewheeling diodes. In the same way, the lower leg II includes a number of IGBTs  40   c ′ and freewheeling diodes  40   d ′ that are connected to one another. 
       FIG. 16  is a circuit diagram of a power semiconductor module  1  including three phase legs L 1 , L 2 , L 3  as illustrated in  FIG. 14 . The phase outputs of the phase legs L 1 , L 2 , L 3  are connected to independent phase output terminals  33 ′,  33 ″,  33 ′″, respectively, independent from one another. The control inputs of the IGBTs  40   a ,  40   c  are also independent from one another and connected to independent control input terminals  34 . As illustrated in  FIG. 16 , the phase legs L 1 , L 2 , L 3  may include common power supply terminals  31 ,  32 . Alternatively, one, some or all of the phase legs L 1 , L 2 , L 3  may include individual power supply terminals. 
       FIG. 17  illustrates an embodiment of a power semiconductor module  1  including a H-Bridge. The module includes two half bridges  1   a  and  1   b  each of which is designed similar to the half bridge described with reference to  FIG. 14 . The output of the half bridge  1   a  is electrically connected to a first phase output terminal  33   a , the output of the half bridge  1   b  to a second phase output terminal  33   b . An external load  61 , e.g., a motor, is connected to the phase output terminals  33   a ,  33   b . Dependent on input signals applied to control terminals  34  of the module  1  the direction of rotation as well as the rotational speed of the motor  61  can be varied. For example, if the IGBTs in the upper leg la of half bridge  1   a  and in the lower leg IIb of half bridge  1   b  are switched on and the IGBTs in the upper leg Ib of half bridge  1   b  and in the lower leg IIa of half bridge  1   a  are switched off, the direction of rotation of the motor is opposite to the direction of rotation when the IGBTs in the upper leg Ia of half bridge  1   a  and in the lower leg IIb of half bridge  1   b  are switched off and the IGBTs in the upper leg Ib of half bridge  1   b  and in the lower leg IIa of half bridge  1   a  are switched on. 
     With reference to  FIGS. 13 to 17 , a single switch, a half bridge, “six pack” and a H-bridge have been described. However, other embodiments may relate to power semiconductor modules including other configurations including one or more power semiconductor chips, e.g., power semiconductor modules which are designed as full inverter (“six pack”), or subunits thereof. 
     The power semiconductor modules described in  FIGS. 1 to 12  include multilayer substrates  3 . Each of the multilayer substrates  3  includes at least three metal layers and at least two ceramic layers. Such a metal layer may, e.g., consist of copper, aluminum, or silver, or include at least one of these metals, e.g., an alloy. In case of an alloy, also other materials may be comprised. Optionally, a metal layer may include sublayers. Each of the ceramic layers of such a multilayer substrate  3  may, e.g., consist of or include Al 2 O 3  (aluminum oxide), AlN (aluminum nitride), or Si 3 N 4  (silicon nitride). The multilayer substrates  3  may be manufactured using an AMB process (AMB=active metal brazing), a DAB process (DAB=direct aluminum bonding), or a DCB process (DCB=direct copper bonding). 
     One way for producing a multilayer substrate is to stack metal layers and ceramic layers alternately and successively and afterwards bonding the stacked layers to one another by applying pressure and high temperature to the stack. The required temperature depends on the selected bonding process. The metal layers and/or the ceramic layers may be structured prior to stacking. Optionally, the ceramic layers may be provided prior to bonding with openings in which electrically conductive material, e.g., copper balls or a silver paste, is inserted. In case of stacking and bonding structured metal layers and/or ceramic layers the metal layers and/or ceramic layers may be aligned prior to the bonding step. 
     In a further way, some of the metal layers and some of the ceramic layers may be bonded separately to form a sub-substrate. Afterwards, such a sub-substrate may be joined with further metal layers and/or further ceramic layers and/or further sub-substrates. As far as it is accessible, the area of a metal layer of a sub-substrate may be structured prior to joining the sub-substrate with the further metal layers and/or further ceramic layers and/or further sub-substrates. A sub-substrate may comprise, e.g., one ceramic layer which is joined with one metal layer, or with two metal layers which are arranged on opposite sides of the ceramic layer and joined therewith. For both ways, AMB, DAB, DCB may apply as joining technique. Other techniques are vacuum soldering, LTJT, TLP soldering (TLP=transient liquid phase), or gluing with a conductive glue. 
       FIG. 18  illustrates different processes of a procedure for manufacturing a sub-substrate of a multilayer substrate. According to  FIG. 18   a  two metal layers  11 ′,  12 ′ and a ceramic layer  21 ′ are provided. In an optional step, an opening  18  may be created in the ceramic layer  21  ( FIG. 18   b ). In the opening  18   a  conductive material  10 , e.g., a silver paste or a copper ball, may be inserted ( FIG. 18   c ). Afterwards, the metal layers  11 ′,  12 ′ and the ceramic layer  21 ′ may be stacked such that ceramic layer  21 ′ is arranged between the metal layers  11 ′,  12 ′ ( FIGS. 18   d  and  18   e ). Between adjacent layers  11 ′,  12 ′,  21 ′ additional material, e.g., silver paste or glue, may be arranged to improve the joining properties. Then this stacked arrangement is clamped between clamping jaws  20  ( FIG. 18   f ) such that the layers  11 ′,  12 ′,  21 ′ are pressed to one another. During clamping the temperature of the stack may be increased.  FIG. 18   g  illustrates the sub-substrate  3 ′ after releasing the pressure. The sub-substrate  12 ′ including two metal layers  11 ′,  12 ′ and a via  10  results ( FIG. 18   g ). 
     Optionally, grooves  19 ′ may be produced in at least one of the metal layers  11 ′,  12 ′. Due to the grooves  19 ′ the respective metal layer  12 ′ is divided into sections  12   a ′,  12   b ′,  12   c ′ distant and electrically insulated from one another ( FIG. 18   h ). The grooves  19 ′ may be produced by conventional masking and etching technique. Alternatively, grooves  19 ′ may be produced by milling. 
     Instead of producing a sub-substrate including one ceramic layer  12 ′ and two metal layers  11 ′,  12 ′, sub-substrates including one ceramic layer and just one metal layer may be manufactured in a corresponding way. A further modification may be a sub-substrate including a metal layer which is arranged between two ceramic layers. 
     With reference to  FIG. 19   a  two sub-substrates  3 ′,  3 ″ are provided. Each of the sub-substrates  3 ′,  3 ″ may be produced as described above. Each of the bottom metal layer  12 ′ of sub-substrate  3 ′ and the top metal layer  12 ″ of sub-substrate  3 ″ includes a number of grooves  19 ′. The sub-substrates  3 ′,  3 ″ are stacked and aligned such that the grooves  19 ′ of metal layer  12 ′ and the grooves of metal layer  12 ″ match. Between adjacent sub-substrates  3 ′,  3 ″ additional material, e.g., silver paste or conductive glue, may be arranged to improve the joining properties. Then this stacked arrangement is clamped between clamping jaws  20  ( FIG. 19   b ) such that the sub-substrates  3 ′,  3 ″ are pressed to one another. During clamping the temperature of the stack may be increased.  FIG. 19   c  illustrates the multilayer substrate  3  after releasing the pressure. Adjacent grooves  19 ′ of adjacent metal layers  12 ′,  12 ″ form grooves  19  due to which metal layer  12  which is formed from metal layers  12 ′,  12 ″ is divided into sections  12   a ,  12   b ,  12   c  distant and electrically insulated from one another. Optionally, another grooves  19  may be produced in at least one of the top metal layer  11  and the bottom metal layer  13  ( FIG. 19   d ). 
     Another embodiment for a method of producing a multilayer substrate  3  is explained with reference to  FIG. 20 .  FIG. 20   a  illustrates metal layers  11 ′,  12 ′,  13 ′ and ceramic layers  21 ′,  22 ′. Ceramic layer  21 ′ is provided with an opening  18  which may be filled with conductive material, e.g., silver paste or copper balls. Metal layer  12 ′ includes sections  12 ′ a ,  12 ′ b ,  12 ′ c  which are distant from one another. After adjusting and stacking the metal layers  11 ′,  12 ′,  13 ′ and the ceramic layers  21 ′,  22 ′ the stack is clamped between clamping jaws  20  ( FIG. 20   b ) such that the layers  11 ′,  21 ′,  12 ′,  22 ′,  13 ′ are pressed to one another. During clamping the temperature of the stack may be increased. After releasing the pressure, a multilayer substrate exists which differs from the multilayer substrate  3  of  FIG. 19   c  in that the middle metal layer  12  is made in one piece. Instead of grooves  19  the sections  12   a ,  12   b ,  12   c  of metal layer  12  are spaced apart by spaces  16 . 
     If, e.g., the metal layers  11 ′,  12 ′,  12 ″,  13 ′ include identical thicknesses, the thickness d 11  of the top metal layer  11  and the thickness d 13  of the bottom metal layer  13  ( FIGS. 19   d ,  20   b ) of the multilayer substrate  3  is about half the thicknesses d 12  of all other metal layers  12  of the multilayer substrate  3 . 
       FIG. 21  illustrates different processes of a procedure for manufacturing a pre-curved multilayer substrate. The processes may be identical to the procedures described with reference to  FIGS. 19 and 20 . However, the pre-curvature may be achieved by using curved clamping jaws  20  ( FIG. 21   a ) instead of plane clamping jaws  20  described with reference to  FIG. 18   f .  FIG. 21   b  illustrates the pre-curved sub-substrate  3 ′ after releasing the pressure applied by the curved clamping jaws  20 . In the same way, pre-curved multilayer substrates may be produced by using curved clamping jaws  20  instead of plane clamping jaws  20  described with reference to  FIGS. 19   b  and  20   b.    
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.