Abstract:
A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     In traditional metal insulator semiconductor (MIS) dynamic random access memory (DRAM) devices, high temperature nitridation before the high dielectric constant (k) deposition is needed to prevent bottom electrode oxidation during the high-k deposition. It is noted that a high dielectric constant (k) is above about 3.9.  
         [0002]     The major concern is to eliminate native oxide and to increase capacitance. However, a high temperature anneal is not acceptable for embedded DRAM because logic performance will be degraded.  
         [0003]     U.S. Pat. No. 6,580,115 B2 to Agarwal describes a capacitor electrode for integrating high-k materials (wherein high-k materials have a dielectric of greater than about 20).  
         [0004]     U.S. Pat. No. 5,663,098 to Creighton et al. describes a method for deposition of a conductor in integrated circuits.  
         [0005]     U.S. Pat. No. 4,751,101 to Joshi describes low stress tungsten films by silicon reduction of WF 6 .  
       SUMMARY OF THE INVENTION  
       [0006]     Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of eliminating native oxide formation in the formation of metal insulator semiconductor (MIS) capacitors.  
         [0007]     Other objects will appear hereinafter.  
         [0008]     It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate including a capacitor area isolated by shallow trench isolation structures formed within shallow trench isolation structure trenches is provided. An inchoate capacitor is formed on the substrate within the capacitor area whereby portions of the substrate separate the inchoate capacitor from the shallow trench isolation structures. A first dielectric layer is formed over the substrate, the shallow trench isolation structures and the inchoate capacitor. The first dielectric layer is patterned to: form a patterned first dielectric layer portion masking the inchoate capacitor; and expose at least portions of the shallow trench isolation structures and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the shallow trench isolation structures whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The capacitor is then completed. The invention also includes the structures formed thereby.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:  
         [0010]      FIG. 1  schematically illustrate an initial structure common to both the first and second preferred embodiments of the present invention.  
         [0011]      FIGS. 1 and 2  to  6  schematically illustrate a first preferred embodiment of the present invention.  
         [0012]      FIGS. 1 and 7  to  11  schematically illustrate a second preferred embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0000]     Initial Structure Common to Both the First and Second Embodiments— FIG. 1   
         [0013]      FIG. 1  illustrates the initial structure common to both the first and second embodiments of the present invention which illustrates a standard logic process up past the interlevel dielectric (ILD) layer  20  planarization, preferably by chemical mechanical polishing (CMP).  
         [0014]     Substrate  10  is divided by a first shallow trench isolation (STI)  12  and a second shallow trench isolation (STI)  14 , for example, with an N/P well region  16  and a cell region  18 . Within the cell region  18 , an inchoate capacitor  24  is formed within a capacitor area  22 . Inchoate capacitor  24  includes dual gate electrodes  30 ,  32  with: respective overlying silicide portions  34 ,  36 ; respective underlying gate oxide portions  38 ,  40 ; and respective sidewall spacers  42 ;  44 . Pairs of LDD implants  46 ,  48  are formed within the substrate  10  are outboard of the respective gate electrodes  30 ,  32  and a central source/drain (S/D) implant  52  is formed within the substrate  10  is between the gate electrodes  30 ,  32  and includes a silicide portion  54  thereover formed on the substrate  10 .  
         [0015]     First device  26  may be formed on substrate  10  over N/P well region  16 . First device  26  may include a gate electrode  41  with an overlying silicide portion  43  and an underlying gate oxide portion  45 , sidewall spacers  47 , LDD implants  49 , source and drain implants  51 ,  53  with respective overlying silicide portions  55 ,  57 .  
         [0016]     Second device  28  may be formed on STI  14  and includes gate electrode  60  with an overlying silicide portion  62  and sidewall spacers  64 .  
         [0017]     Substrate  10  is preferably comprised of silicon or germanium and is more preferably silicon. Silicide portions  34 ,  36 ,  54 ;  43 ,  55 ,  57 ;  62  are preferably comprised of cobalt silicide (CoSi x ) titanium silicide (TiSi x ) or nickel silicide (NiSi x ) and are more preferably cobalt silicide (CoSi x ).  
         [0018]     Respective resist protect oxide (RPO) portions  66 ,  67  are formed outboard from silicide portions  34 ,  36  over dual gate electrodes  30 ,  32  over: (1) the outboard sidewall spacers  42 ,  44 ; (2) the adjacent portions of substrate  10 ; and (3) over at least a portion of the adjacent STIs  12 ,  14 . RPO portions  66 ,  67  are preferably comprised of oxide or silicon oxide and more preferably oxide and have a thickness of preferably from about 30 to 700 Å and more preferably from about 150 to 400 Å.  
         [0019]     An etch stop layer  70  is then formed over the RPO portions  66 ,  67 , inchoate capacitor  24 , first device  26 , second device  28  and silicide portions  54 ,  55 ,  57  to a thickness of preferably from about 50 to 700 Å and more preferably from about 300 to 500 Å. Etch stop layer  70  is preferably comprised of a composite film oxide/silicon oxynitride (SiON).  
         [0020]     A planarized interlevel dielectric layer (ILD)  20  is then formed over the etch stop layer  70  to a thickness of preferably from about 5000 to 12,000 Å and more preferably from about 8000 to 10,000 Å. ILD layer  20  is preferably planarized by chemical mechanically polishing (CMP). ILD layer  20  is preferably comprised of oxide.  
         [0021]     The structure of  FIG. 1  is then used in respective first (FIGS.  2  to  6 ) and second (FIGS.  7  to  11 ) embodiments as described below.  
         [0022]     In the first embodiment of the present invention, the crown patterning step to open the capacitor area  22  also patterns portions of the respective STI&#39;s  12 ,  14  while in the second embodiment of the present invention, the crown patterning step to open the capacitor area  22  does not pattern the respective STI&#39;s  12 ,  14 .  
       First Embodiment  
     FIGS.  2  to  6   
       [0000]     Crown Patterning Step and Patterning of STI&#39;s  12 ,  14 — FIG. 2   
         [0023]     As shown in  FIG. 2 , a patterned masking layer  80  (that is preferably comprised of photoresist) is formed over the ILD layer  20  to mask the inchoate capacitor  24  and the respective first and second device regions  82 ,  84  within which the first and second devices  26 ,  28  are formed and the ILD layer  20  is patterned to form patterned ILD portions  20 ′,  20 ″,  20 ′″ and expose portions  85 ,  87  of the underlying substrate  10  and, in this first embodiment, portions of the respective STI&#39;s  12 ,  14  within the capacitor area  22  are also patterned to form patterned STI&#39;s  12 ′,  14 ′ exposing portions  86 ,  88  of the respective STI trenches  11 ,  15  within which the STI&#39;s  12 ,  14  were formed.  
         [0024]     STI&#39;s  12 ,  14  are also patterned during this crown patterning step by: etching the ILD layer  20  and stopping on the etch stop layer  70 ; removing the exposed etch stop layer  70  in situ; etching substrate  10  to form STI trenches  11 ,  15 ; and then filling STI trenches  11 ,  15  to form STI&#39;s  12 ,  14 .  
         [0000]     Formation of Respective Tungsten (W) Portions  90 ,  92  Over the Exposed Portions  85 ,  87  of Substrate  10  and Exposed Portions  86 ,  88  of the STI Trenches  11 ,  15 — FIG. 3   
         [0025]     As shown in  FIG. 3 , the patterned masking layer  80  is removed and the structure is cleaned as necessary.  
         [0026]     Then, metal portions  90 ,  92  are formed over the exposed portions  85 ,  87  of substrate  10  and the exposed portions  86 ,  88  of the STI trenches  11 ,  15  to a thickness of preferably from about 10 to 300 Å and more preferably from about 100 to 200 Å. Metal portions  90 ,  92  are preferably formed using a selective metal deposition process so that metal is formed only on the expose Si surfaces and preferably comprise tungsten (W) formed using WF 6 , provided that metal portions  90 ,  92  are formed at sufficiently low temperatures to prevent logic device degradation.  
         [0027]     The reaction to form the tungsten (W) portions  90 ,  92  is based upon a CVD process and is believed to be: 
 
2WF 6 +3Si→2W+3SiF 4  
 
         [0028]     These tungsten (W) portions  90 ,  92  will prevent oxidation of the otherwise exposed underlying portions  85 ,  86 ,  87 ,  88  of substrate  10  during the subsequent high-k dielectric layer  94  formation.  
         [0000]     Formation of High-K Dielectric Layer  94 , Barrier Layer  96  and Metal Layer  98 — FIG. 4   
         [0029]     As shown in  FIG. 4 , a high-k dielectric layer  94  (that is a dielectric layer having a dielectric constant (k) of greater than about 3.9 is formed over the structure of  FIG. 3  to a thickness of preferably from about 10 to 200 Å and more preferably from about 50 to 100 Å. High-k dielectric layer  94  is preferably comprised of a composite film such as Ta 2 O 5 /Al 2 O 3 , HfO 2 /Al 2 O 3  or Al 2 O 3 /HfO 2 /Al 2 O 3 ; Ta 2 O 5 ; HfO 2 ; Al 2 O 3 ; TiO 2 ; SrTiO 3  or ZrO 2 ; and is more preferably a composite film such as Ta 2 O 5 /Al 2 O 3  or HfO 2 /Al 2 O 3 . or Al 2 O 3 /HfO 2 /Al 2 O 3 .  
         [0030]     It is noted that the tungsten (W) portions  90 ,  92  prevent oxidation of the underlying portions  85 ,  86 ,  87 ,  88  of substrate  10  during the formation of the high-k dielectric layer  94 .  
         [0031]     Preferably, a barrier layer  96  is then formed over high-k dielectric layer  94  to a thickness of preferably from about 15 to 300 Å and more preferably from about 100 to 200 Å. Barrier layer  96  is preferably comprised of TiN, TaN, WN, etc. and is more preferably TiN.  
         [0032]     As shown in  FIG. 4 , a barrier layer lined plate opening  100  is positioned between inchoate capacitor  24  and first device  26  and a barrier layer lined plate opening  102  is positioned between inchoate capacitor  24  and second device  28 .  
         [0033]     Then, a metal plate layer  98  is formed over the barrier layer  96 /high-k dielectric layer  94  to at least fill barrier layer lined plate openings  100 ,  102 .  
         [0034]     Metal plate layer  98  is preferably comprised of tungsten (W).  
         [0000]     Planarization of Metal Plate Layer  98 , Optional Barrier Layer  96  and High-K Dielectric Layer  94 — FIG. 5   
         [0035]     As shown in  FIG. 5 , metal plate layer  98 , optional barrier layer  96  and high-k dielectric layer  94  are planarized, preferably by chemical mechanical polishing (CMP), to remove them from over the patterned ILD layer portions  20 ′,  20 ″,  20 ′″ and to form metal plates  104 ,  106  within barrier layer lined plate openings  100 ,  102 .  
         [0000]     Formation of Contacts  110 ,  112 ,  114 ,  116  and Back End of Line (BEOL) Processing— FIG. 6   
         [0036]     As shown in  FIG. 6 , various contacts  110 ,  112 ,  114 ,  116  may be formed through various patterned ILD portions  20 ′,  20 ″,  20 ′″ to contact select source drains and/or gate electrodes such as shown.  
         [0037]     Further back end of line (BEOL) processing may then proceed. For example, as shown in  FIG. 6 , an upper dielectric layer  108  may be formed over contacts  110 ,  112 ,  114 ,  116  and patterned ILD portions  20 ′,  20 ″,  20 ′″ and: (1) plate pickups  200 ,  202  may be formed there through to contact respective metal plates  104 ,  106 ; and (2) pickups  204 ,  206 ,  208  may be formed there through to contact respective contacts  110 ,  112 ,  114 ,  116 . As shown, plate pickups  200 ,  202  and pickups  204 ,  206 ,  208  may be barrier layer lined.  
         [0038]     This completes formation of the capacitor  24 ′.  
       Second Embodiment  
     FIGS.  7  to  11   
       [0000]     Crown Patterning Step— FIG. 7   
         [0039]     As noted above, the second embodiment of the present invention is substantially the same as the first embodiment except that the crown patterning step in the second embodiment does not pattern the STI&#39;s  12 ,  14 . As such like reference numbers will be used for like structures in the first embodiment.  
         [0040]     As shown in  FIG. 7 , a patterned masking layer  80  (that is preferably comprised of photoresist) is formed over the ILD layer  20  to mask the inchoate capacitor  24  and the respective first and second device regions  82 ,  84  within which the first and second devices  26 ,  28  are formed and the ILD layer  20  is patterned to form patterned ILD portions  20 ′,  20 ″,  20 ′″ and expose portions  85 ′,  87 ′ of the underlying substrate  10 .  
         [0000]     Formation of Respective Tungsten (W) Portions  300 ,  302  Over the Exposed Portions  85 ′,  87 ′ of Substrate  10 — FIG. 8   
         [0041]     As shown in  FIG. 8 , the patterned masking layer  80  is removed and the structure is cleaned as necessary.  
         [0042]     Then, metal portions  300 ,  302  are formed over the exposed portions  85 ′,  87 ′ of substrate  10  to a thickness of preferably from about 10 to 300 Å and more preferably from about 100 to 200 Å. Metal portions  300 ,  302  are preferably formed using a selective metal deposition process so that metal is formed only on the expose Si surfaces and preferably comprise tungsten (W) formed using WF 6 , provided that metal portions  300 ,  302  are formed at sufficiently low temperatures to prevent logic device degradation.  
         [0043]     The reaction to form the tungsten (W) portions  300 ,  302  is based upon a CVD process and is believed to be: 
 
2WF 6 +3Si→2W+3SiF 4  
 
         [0044]     These tungsten (W) portions  300 ,  302  will prevent oxidation of the otherwise exposed underlying portions  85 ′,  87 ′ of substrate  10  during the subsequent high-k dielectric layer  94 ′ formation.  
         [0000]     Formation of High-K Dielectric Layer  94 ′, Barrier Layer  96 ′ and Metal Layer  98 ′— FIG. 9   
         [0045]     As shown in  FIG. 9 , a high-k dielectric layer  94 ′ (that is a dielectric layer having a dielectric constant (k) of greater than about 3.9 is formed over the structure of  FIG. 8  to a thickness of preferably from about 10 to 200 Å and more preferably from about 50 to 100 Å. High-k dielectric layer  94 ′ is preferably comprised of a composite film such as Ta 2 O 5 /Al 2 O 3 , HfO 2 /Al 2 O 3  or Al 2 O 3 /HfO 2 /Al 2 O 3 , etc.; Ta 2 O 5 ; HfO 2 ; Al 2 O 3 ; TiO 2 ; SrTiO 3 ; ZrO 2 ; etc. and is more preferably a composite film such as Ta 2 O 5 /Al 2 O 3  or HfO 2 /Al 2 O 3 . or Al 2 O 3 /HfO 2 /Al 2 O 3 , etc.  
         [0046]     It is noted that the tungsten (W) portions  300 ,  302  prevent oxidation of the underlying portions  85 ′,  87 ′ of substrate  10  during the formation of the high-k dielectric layer  94 ′.  
         [0047]     Preferably, a barrier layer  96 ′ is then formed over high-k dielectric layer  94 ′ to a thickness of preferably from about 15 to 300 Å and more preferably from about 100 to 200 Å. Barrier layer  96 ′ is preferably comprised of TiN, TaN, WN, etc. and is more preferably TiN.  
         [0048]     As shown in  FIG. 9 , a barrier layer lined plate opening  100 ′ is positioned between inchoate capacitor  24  and first device  26  and a barrier layer lined plate opening  102 ′ is positioned between inchoate capacitor  24  and second device  28 .  
         [0049]     Then, a metal plate layer  98 ′ is formed over the barrier layer  96 ′/high-k dielectric layer  94 ′ to at least fill barrier layer lined plate openings  100 ′,  102 ′.  
         [0050]     Metal plate layer  98 ′ is preferably comprised of tungsten (W).  
         [0000]     Planarization of Metal Plate Layer  98 ′, Optional Barrier Layer  96 ′ and High-K Dielectric Layer  94 ′— FIG. 10   
         [0051]     As shown in  FIG. 10 , metal plate layer  98 ′, optional barrier layer  96 ′ and high-k dielectric layer  94 ′ are planarized, preferably by chemical mechanical polishing (CMP), to remove them from over the patterned ILD layer portions  20 ′,  20 ″,  20 ′″ and to form metal plates  304 ,  306  within barrier layer lined plate openings  100 ′,  102 ′.  
         [0000]     Formation of Contacts  110 ,  112 ,  114 ,  116  and Back End of Line (BEOL) Processing— FIG. 11   
         [0052]     As shown in  FIG. 11 , various contacts  110 ,  112 ,  114 ,  116  may be formed through various patterned ILD portions  20 ′,  20 ″,  20 ′″ to contact select source drains and/or gate electrodes such as shown.  
         [0053]     Further back end of line (BEOL) processing may then proceed. For example, as shown in  FIG. 11 , an upper dielectric layer  108  may be formed over contacts  110 ,  112 ,  114 ,  116  and patterned ILD portions  20 ′,  20 ″,  20 ′″ and: (1) plate pickups  200 ,  202  may be formed there through to contact respective metal plates  304 ,  306 ; and (2) pickups  204 ,  206 ,  208  may be formed there through to contact respective contacts  110 ,  112 ,  114 ,  116 . As shown, plate pickups  200 ,  202  and pickups  204 ,  206 ,  208  may be barrier layer lined.  
         [0054]     This completes formation of the capacitor  24 ′.  
         [0055]     It is noted that the second embodiment is an extension of the first embodiment.  
         [0000]     Advantages of the Present Invention  
         [0056]     The advantages of one or more embodiments of the present invention include: 
        1. increase in capacitance due to the elimination of native oxide;     2. the cell size is shrinkable;     3. the same logic performance is maintained when using the embodiments of the present invention; and     4. an extra mask is not needed to define top electrode because a selective metal (W) formation is used as the bottom electrode with the metal (W) is only being formed on the exposed Si surface. (If a normal process were used to deposit the metal as the bottom electrode, an extra mask would be needed to define hi-k and the top electrode to avoid electrical short between the top and bottom electrodes.)        
 
         [0061]     While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.