Abstract:
A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.

Description:
BACKGROUND 
     The present invention relates to semiconductor package structures and methods of making, and in particular to Quad Flat No-lead (QFN) packages and methods of making. 
     DESCRIPTION OF RELATED ART 
     Semiconductor packages include various package types. One type is the Quad Flat No-lead (QFN) package, which is characterized by short signal transmission path and rapid signal transmission speed. These packages are suitable for high frequency (e.g. radio frequency bandwidth) chip packages, and for low pin count packages. 
     In one method of making a conventional QFN package, a plurality of chips, or dies, are secured to die pads of a lead frame wafer. The dies are electrically connected to leads of the lead frame via bonding wires. The leads, the bonding wires, and the chips are encapsulated and protected by a molding compound, or encapsulant. The bottom surfaces of the leads are exposed from the encapsulant for electrical connection to an external device. The wafer is then singulated to divide the structure into individual QFN packages. 
     When the size of a QFN package is enlarged, the distance between the chip and the leads increases, thus slowing down the performance of the package due to the need for electrical signals to traverse longer distances. One solution to this problem is to add extension portions to the leads to save the lengths of the bonding wires. However, since the extension portions of the leads are exposed from the encapsulant and not connected to any external device, the extension portions of the leads may oxidize when exposed to air. 
     SUMMARY 
     One of the present embodiments comprises a semiconductor package. The package comprises a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface. 
     Another of the present embodiment comprises a semiconductor package. The package comprises a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead has a concave side surface facing toward a lower surface of the package. A second lead having a concave side surface is disposed between the die pad and the first lead. The second lead has a concave surface facing toward an upper surface of the package. 
     Another of the present embodiment comprises a method of making a plurality of semiconductor packages. The method comprises disposing a plurality of dies on a plurality of leadframes. Each leadframe includes an upper surface, a lower surface opposite the upper surface, a cavity, a plurality of first recesses, and a plurality of second recesses, and wherein (1) the first recesses are formed in the lower surface and define a plurality of first leads, a plurality of extension portions, and a plurality of support ribs connecting the extension portions to the first leads, (2) the second recesses are formed in the upper surface and define a plurality of second leads and a plurality of die pads, (3) depths of the cavities are less than depths of the second recesses, and (4) at least one of the first recesses connects with at least one of the second recesses. The method further comprises electrically connecting the dies with the extension portions and the second leads with a plurality of bonding wires. The method further comprises forming a package panel covering the dies and the bonding wires and filling the first recesses and the second recesses. The method further comprises removing a portion of each leadframe and a portion of the package panel from the lower surfaces to electrically isolate the die pads, the first leads and the second leads. The method further comprises singulating each of the dies by cutting the package panel and removing the support ribs to form the plurality of semiconductor packages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1F  are cross-sectional side views showing steps in a method of making a leadframe according one of the present embodiments; 
         FIGS. 1G-1N  are cross-sectional side views showing steps in a method of making a semiconductor package structure according to one of the present embodiments; 
         FIG. 2  is a top view of a part of an upper surface of the leadframe of  FIG. 1F ; and 
         FIG. 3  is a cross-sectional side view of a semiconductor package structure according to one of the present embodiments. 
     
    
    
     Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements. The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. 
     DETAILED DESCRIPTION 
     Referring to  FIG. 1A , a conductive substrate  110   a  having an upper surface  111  and a lower surface  112  is illustrated. The conductive substrate  110   a  may be, for example, copper or iron, or any other conductive material. A mask layer  10  is formed to completely cover the upper surface  111  of the conductive substrate  110   a , and a patterned mask layer  20  is formed to cover a portion of the lower surface  112 . In the illustrate embodiment, the mask layer  10  and the patterned mask layer  20  can be, for example, a dry film photoresist or a wet photoresist. 
     Referring to  FIG. 1B , using the patterned mask layer  20  as an etching mask, a half etching process is performed on the lower surface  112  of the conductive substrate  110   a  to form first recesses  114  in regions of the conductive substrate  110   a  not covered by the mask layer  20 . The first recesses  114  define first leads  116 , which may also be referred to as outer leads. When the half etching process is performed, the mask layer  10  covers and protects the upper surface  111  of the conductive substrate  110   a . After the half etching process is performed, the mask layer  10  and the patterned mask layer  20  are removed. 
     Referring to  FIG. 1C , a mask layer  30  is applied to completely cover the lower surface  112  and fill the first recesses  114 . A metal layer  110   b  is selectively plated on the upper surface  111 , and a patterned mask layer  12  is formed to cover the metal layer  110   b . The metal layer  110   b  is an anti-oxidation layer, e.g. a surface finishing layer, and may be, for example, gold (Au), Palladium (Pd), nickel (Ni), a combination of the foregoing, or any other material. With reference to  FIG. 2 , the patterned mask layer  12  defines the patterns of a plurality of die pads  113 , first leads  116 , extension portions  117  of the first leads  116 , second leads  118 , which may also be referred to as inner leads  118 , and support ribs  119 . The extension portions  117  are integral with the first leads  116  and extend inward, toward the corresponding die pads  113 . 
       FIG. 1C  illustrates an alternative embodiment that is similar to the embodiment of  FIG. 1C , except that the pattern of the metal layer  110   b  formed in the embodiment of FIG.  1 C′ is different from that formed in the embodiment of  FIG. 1C . Since the patterned mask layer  12  is used as an etching mask, the metal layer  110   b  is formed only in the regions that are used as the contacts. 
     Referring to  FIG. 1D , using the patterned mask layer  12  as an etching mask, a half etching process is performed on the upper surface  111  of the conductive substrate  110   a  to fowl second recesses  115  and cavities  113   a  of the die pads  113  in regions of the conductive substrate  110   a  not covered by the patterned mask layer  12 . Side surfaces of the second recesses  115  and the cavities  113   a  have concave profiles. 
     Referring to  FIG. 1E , a second patterned mask layer  14  is formed to cover the cavities  113   a . Using the patterned mask layers  12 ,  14  as etching masks, a further half etching process is performed on the conductive substrate  110   a  to increase the depth of the second recesses  115 . After the further half etching process, some of the second recesses  115  connect with the first recesses  114 , so that the first leads  116  and the second leads  118  can be electrically and physically isolated from each other. Note that in  FIG. 1E  the first and second recesses  114 ,  115  appear to be separated, but after the mask layer  30  is removed they are connected ( FIG. 1F ). 
     Referring to  FIG. 1F  after the patterned mask layers  12 ,  14  and the mask layer  30  are removed, a leadframe strip  110  including a plurality of leadframes  110   c  is completed. Each of the leadframes  110   c  has the die pad  113 , the cavity  113   a  of the die pad, the first recesses  114 , the second recesses  115 , the first leads  116 , the extension portions  117  of the first leads  116 , the second leads  118  and the metal layer  110   b . With reference to  FIG. 2 , the first leads  116  are connected to the support ribs  119 , which are connected to the tie bars  119   a , which are connected to the die pads  113  for holding them together. The first leads  116  and the second leads  118  have concave profiles. The cavities cavity  113   a  of the die pad  113  have the depth d 1  that is smaller than the depth d 2  of the second recesses  115 . This configuration can remain a certain thickness of die pad  113  after the process of isolating the die pad  113  from the second leads  118 . Details will be described in the step of  FIG. 1L . The cavities  113   a  also have a flat region for placing a die. Furthermore, the support rib  119  is disposed between two adjacent first leads  116 . In this embodiment, the support rib  119  is used to connect a plurality of leadframes  110   c , so as to fabricate a plurality of semiconductor packages at the same time. This embodiment illustrates two leadframes connected by the support rib  119  as an example, to show that the leadframes are fabricated in an array. 
       FIGS. 1G-1N  are cross-sectional side views showing a method for making a semiconductor package structure according to one of the present embodiments. Referring to  FIG. 1G , dies  120  are disposed in the cavities  113   a  of the die pads  113 . The dies  120  may be secured within the cavities  113   a , such as with an adhesive, such as colloidal silver or another suitable material, for example. The cavities  113   a  include a curved inner surface  113   c  facing toward the die  120 . 
     Referring to  FIG. 1H , the dies  120  are electrically connected to the extension portions  117  of the first leads  116 , the second leads  118 , and the die pads  113  with a plurality of bonding wires  130 . A heating block  40  can be used to support and heat the first leads  116  and the second leads  118  of the leadframe strip  110 . The heating block  40  is positioned on the lower surface  112  and extends into the first recesses  114  to support the extension portions  117  of the first leads  116 . The heating block  40  can heat the interface between the bonding wires  130  and the extension portions to enhance the eutectic bonding. Advantageously, since the die  120  electrically connects to the first leads  116  through the bonding wires  130 , which are connected between the die  120  and the extension portions  117  of the first leads  116 , lengths of the wires  130  can be reduced in comparison to a configuration in which the extension portions  117  are absent. 
     Referring to  FIG. 1I , a protective film  50  is adhered to the lower surface  112  of the leadframe strip  110 . The protective film  50  can be, for example, a pre-mold tape. The protective film  50  does not extend into the first recesses  114 . 
     Referring to  FIG. 1J , a molding compound  160  is formed to cover the dies  120 , the die pads  113 , the second recesses  115 , the first leads  116 , the second leads  118 , the support ribs  119  and the bonding wires  130 . As discussed above, some of the first recesses  114  connect with the second recesses  115  at reentrant portions  114   a . Thus, the molding compound  160  can flow from the second recesses  115  into the first recesses  114  to encapsulate the extension portions  117  of the first leads  116 . The protective film  50  adhered to the lower surface  112  of the leadframe strip  110  prevents the molding compound  160  from overflowing to the lower surface  112 . 
     Referring to  FIG. 1K , the protective film  50  is removed. Although not shown in the drawing, the lower surface of the molding compound  160  may be slightly depressed from the lower surface  112  of the leadframe  110 . Referring to  FIG. 1L , a process is performed on the lower surface  112  of the leadframe strip  110  to remove a portion of the conductive substrate  110   a  and a portion of the molding compound  160  to expose the second recesses  115  and so that the die pads  113  and the second leads  118  are electrically and physically isolated from each other. The process performed may be, for example, grinding, polishing, etching or any other suitable process. Accordingly external surfaces  116   a  of the first leads  116  and external surfaces  118   a  of the second leads  118  are also exposed, thus providing contact elements. In this embodiment, since the first depth d 1  of the cavities  113   a  is smaller than the second depth d 2  of the second recesses  115 , the cavities  113   a  are not exposed during this process. Therefore, the die pads  113  still have a certain thickness and only external surfaces  113   b  of the die pads  113  are exposed after the process is complete. The external surfaces  113   b ,  116   a ,  118   a  are coplanar with a lower surface  160   a  of the molding compound  160 . Furthermore, since the second recesses  115  and cavities  113   a  of the die pads  113  are formed by half etching process, the side surfaces of the die pads  113  and the second leads  118  have concave profiles. More specifically, in the semiconductor packages  100  of this embodiment, the first leads  116  have curved or concave side surfaces  116   b  that open in a first direction, generally downward, and the second leads  118  have curved or concave side surfaces  118   b  that open in a second direction opposite the first direction, generally upward. This geometry provides mechanical interlock with the molding compound  160 , which resists separation of the leads from the molding compound  160 . This geometry also results in lower surfaces  116   a  of the first leads  116  having smaller surface areas than lower surfaces  118   a  of the second leads  118 . 
     Referring to  FIG. 1M , a plurality of solder balls  170  are disposed on external surfaces  113   b ,  116   a ,  118   a  of the die pads  113 , the first leads  116 , and the second leads  118 , respectively, that are exposed outside the molding compound  160 . The solder balls  170  advantageously resist oxidation of the external surfaces  113   b ,  116   a ,  118   a . The solder balls  170  are also used to electrically connect an external circuit (not shown), such as a printed circuit board. The solder balls  170  can be formed by a dip soldering process, a solder printing process, or an electroless plating process, for example, or any other process. 
     Referring to  FIG. 1N , a singulation process is performed to remove the support ribs  119  and a portion of the molding compound  160 , to form a plurality of semiconductor packages  100 . The singulation may comprise laser cutting, mechanical cutting, etc. 
     Advantageously, side surfaces  116   b ,  118   b  of the first leads  116  and the second leads  118 , as well as lower surfaces  117   b  of the extension portions  117  of the first leads  116 , are encapsulated by the molding compound  160 . Only the external surface  113   b  of the die pad  113 , the external surfaces  116   a  of the first leads  116 , and the external surfaces  118   a  of the second leads  118  are exposed. Hence, oxidation of the encapsulated portions of the first leads  116 , the extension portions  117  of the first leads  116 , and the second leads  118  can advantageously be prevented. Furthermore, the concave side surfaces  113   c ,  116   b  and  118   b  of the die pad  113 , the first leads  116  and the second leads  118  are also locking mechanisms to prevent the die pad  113 , the first leads  116  and the second leads  118  from delaminating from the molding compound  160 . 
       FIG. 2  illustrates a top plan view of part of an upper surface of the leadframe strip  100  of  FIG. 1F . For ease of understanding the connecting relationship between the first leads  116  and the support rib  119 ,  FIG. 2  merely illustrates the upper surface  111 , and the metal layer  110   b  is not shown. The hatching in  FIG. 2  indicates that the leadframe strip  100  has been half etched from underneath. The support rib  119  connects the first leads  116  positioned on facing edges of the two adjacent leadframes  110   c . The support rib  119  thus connects adjacent leadframes  110   c  to form one leadframe strip  110 , so that multiple semiconductor packages  100  can be fabricated at the same time. 
     With further reference to  FIG. 2 , the extension portions  117  of the first leads  116  extend away from the first leads  116  at a non-zero angle. In alternative embodiments, the extension portions  117  may extend away from the first leads  116  in any direction, including along a same straight line traced by the first leads  116 . The extension portions  117  may, for example, be routed so as to reduce a distance between the extension portions  117  and the second leads  118 . Reducing this distance advantageously reduces the length of bond wire  130  needed to connect the die  120  with the extension portions  117 . 
     Referring to  FIG. 3 , a cross-sectional view of another semiconductor package structure according to an embodiment of the invention is illustrated. A difference between a semiconductor package  200  and the semiconductor package  100  is that a second metal layer  210   b  is disposed on the external surface  113   b  of a die pad  113 , the external surface  116   a  of the first leads  116 , and the external surface  118   a  of the second leads  118 . The second metal layer  210   b  can prevent the oxidation of the external surface  113   b  of the die pad  113 , the external surface  116   a  of the first leads  116 , and the external surface  118   a  of the second leads  118 . In addition, the semiconductor package  200  is electrically connected with an external circuit (not shown), such as a printed circuit board, through the second metal layer  210   b . A material of the second metal layer  210   b  can be selected from a group consisting of Au, Pd, Ni, or a combination of the foregoing, but is not limited to the foregoing. The material of the second metal layer  210   b  can be different from the material of the metal layer  110   b.    
     While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present invention which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.