Abstract:
The invention relates to signal transmission. The use of the invention for transmitting and receiving quadrature amplitude modulation signals on unlicensed frequency bands makes it possible to lower a demodulation threshold owing to a low synchronization threshold. The inventive method consists in extending a burst of M m-level quadrature amplitude modulation signals with the aid of two pseudo-random sequences, one of which is periodically inverted in some bursts, thereby making it possible to extract, on a receiving side, the quadrature amplitude modulation signal components corresponding to a meander signal of the pseudo-random sequence inversion (the frequency of which is known). The inventive method is carried out by means of a corresponding system in a hardware and software mode. Moreover, said method can be used for synchronizing the reception of quadrature amplitude modulation signals.

Description:
RELATED APPLICATIONS 
     This application is a Continuation of International Application No. PCT/RU2008/000404, filed Jun. 30, 2008, which claims priority to Russian Patent Application No. RU 2007125231 filed Jul. 4, 2007, both of which are incorporated herein by reference in their entirety. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to the signal transmission technique. Specifically, this invention relates to the method and system for transmitting and receiving quadrature-amplitude modulation signals meant for preferred use in the non-licensed frequency ranges. 
     BACKGROUND OF THE INVENTION 
     In transmitting and receiving the signals modulated in one or another manner, a very important characteristic is the demodulation threshold, i.e., the ratio of the signal power to the noise power (signal-to-noise ratio, SNR), at which the carrier wave of the signal being received ceases to be derived, which results in loss of the reception. The demodulation threshold depends essentially on the demodulation type employed at the transmission side, and the noiseless coding type. 
     One of possible techniques for lowering the demodulation threshold consists in enlarging a spectrum of the signal being transmitted using the so called pseudo-random sequences (PRS). Particularly, the use of the signals like the PRS is directly specified in radio communication systems operating in those frequency ranges which do not require for licensing the right of exclusive use of one or another part thereof (i.e., in the ranges of 2.400 to 2.483 MHz and of 5.725 to 5.850 MHz). Beside this, requirements for using a frequency separation, for limiting a radiation power (maximum 100 mW in any direction), and for employing normalized frequency band of the radiated signal depending on the PRS base. The PRS base is a repetition cycle thereof expressed in the length intervals of one element of the PRS. For the above ranges, the PRS base should be not less than 10. 
     In the modems produced at the present time and intended for operating in the above frequency ranges, the modulation of the type QPSK is used, which PRS base is equal to 15. 
     In these modems which sensitivity ranges from −90 to −98 dBm, the carrier and clock synchronization takes place at the signal-to-noise ratio from 0 to +3 dB, which is caused by a non-linear synchronization circuit. Should the synchronization circuit in these modems is linear, the sensitivity thereof could be improved by 7-10 dB. 
     Known are various proposals for increasing the demodulation threshold. 
     Thus, the Japan Laid-open Application No. 2001-237908 (2001 Aug. 31) discloses a system for extracting a synchronization signal from the QAM signal, which system ensures a quasi-synchronous detection. The U.S. Pat. Nos. 6,717,462 (2004 Apr. 6) and 6,727,772 (2004 Apr. 27) disclose methods and systems for transmitting and receiving the QAM signals with a carrier frequency adjustment. However, both these patents provide only a simple processing of the common QAM signal, which does not permit to lower the demodulation threshold. 
     The US Patent Applications Nos. 2004/0022328 (2004 Feb. 5) and 2005/0111601 (2005 May 26) disclose systems and methods for transmitting quadrature-amplitude modulation (QAM) signals, where the receiver synchronization is based on determining a rotation angle of the received signal vector in the phase space of the complex coordinates. However, these systems employ non-linear techniques of synchronization. 
     The Japan Laid-open Applications Nos. 2005-117366 (2005 Apr. 28), 2005-217636 (2005 Aug. 11) and 2006-262494 (2006 Sep. 28) disclose QAM methods and systems, where additional specific symbols are introduced for the synchronization at the transmitting side, and the synchronization adjustment is performed at the receiving side using these symbols. Similar principle is used in the International Application WO 2006/135275 (2006 Dec. 21). However, the use of the additional symbols complicates the processing of the received signal. 
     SUMMARY OF THE INVENTION 
     The object of the present invention consists in providing such method and system for transmitting and receiving QAM signals, which permit to lower the demodulation threshold by means of providing a low synchronization threshold. 
     In order to accomplish such a result, provided are a method and system for implementing thereof, both intended for transmitting and receiving QAM signals according to the present invention. The main principle of this invention consists in enlarging the burst of M m-level QAM symbols with two pseudorandom sequences (PRSs), one of which being periodically inverted in some bursts. Owing to this, at the receiving side, the QAM signal components corresponding to the meander signal of the PRS inversion (which frequency is known) are derived. This ensures the ambiguity deletion in adjusting the synchronization frequency at the receiving side. 
     Detailed aspects and features of the present invention are set forth in the appended claims. The detailed specification serves for better understanding the claimed group of the inventions. 
     The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale; emphasis has instead been placed upon illustrating the principles of the invention. Of the drawings: 
         FIG. 1  shows a possible signal used in the system according to the present invention. 
         FIG. 2  is the block diagram of the transmitting side of the system for transmitting and receiving QAM signals according to the present invention. 
         FIG. 3  is the block diagram of the receiving side of the system for transmitting and receiving QAM signals according to the present invention. 
         FIG. 4  illustrates an embodiment of the digital quadrature demodulator in the quadrature transform unit at the receiving side of the system according to the present invention. 
         FIG. 5  is the block diagram of the first frequency adjustment extractor at the receiving side of the system according to the present invention. 
         FIG. 6  is the block diagram of the second frequency adjustment extractor at the receiving side of the system according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The form of the signal used in the system for transmitting and receiving the QAM signals according to the present invention is shown in  FIG. 1 . The spectrum of this signal in the I (In-phase) channel is a set of frequency components spaced apart at a predetermined frequency value and interleaved with pilot signals ( FIG. 1   a ). Taking into account the signal in the Q (Quadrature) channel, possible signal constellations for various modulation types are shown in  FIG. 1   b.    
     The system for transmitting and receiving QAM signals according to the present invention consists generally of a transmitting side and a receiving side connected with a communication channel. 
       FIG. 2  represents a block diagram of the transmitting side of the system for transmitting and receiving QAM signals according to the present invention. 
     The transmitting side comprises a m-level symbol former  3  configured for converting the initial information sequence  1  of bit symbols coming at a clock frequency kf 1    2  into a sequence of m-level symbols, where m=2 k , k=2, 3, . . . , which m-level symbols coming out at the first clock frequency f 1 . This first clock frequency is generated in a clock frequency former  4  at the transmitting side, at the first output of this clock frequency former  4 , from the clock frequency kf 1  signal  2  coming at the input thereof, which signal  2  accompanies the bit symbol sequence  1 . 
     A channel divider  5  is configured for dividing the information sequence of the m-level symbols from the m-level symbol former  3  into the I channel of the transmitting side and Q channel of the transmitting side. The repetition frequency of the m-level symbols in each of the I and Q channels of the transmitting side being equal to f 1 /2 is generated at the second output of the clock frequency former  4 . 
     Each of first and second multipliers  6  and  7  is configured for multiplying the values of the m-level symbols in the I and Q channels of the transmitting side, respectively, by a signal of pseudo-random sequence (PRS). This signal of the first PRS is generated in a first PRS former  8 , so that every even member of that first PRS has one of the values +1 or −1, and all odd members thereof are equal to 0. Herewith, the base of the first PRS is equal to C 1 ≧10, and the repetition frequency of the first PRS is equal to C 1 ·f 1 /2. 
     Due to multiplying the values of the m-level symbols by the signal of the first PRS in the multipliers  6  and  7 , a spectrum of each of the m-level symbols is enlarged (or widened) by a factor of C 1 . 
     Each of first and second adders  9  and  10  is configured for summing signals of the first and second multipliers, respectively, with a signal at an output of manipulator  11  configured for keying (multiplying by the meander, inverting) a signal from a second PRS former  12 . 
     The second PRS former  12  is configured for generating the second PRS having a time base C 2 &gt;&gt;C 1 , but the same frequency C 1 ·f 1 /2 as the first PRS from the former  8 . In so doing, every even member of the second PRS has one of the values +A or −A, and all odd members thereof are equal to 0. 
     A meander signal former  13  generates the meander signal having a period twice as much as the period of the second PRS, i.e., the frequency of this meander signal is equal to the value C 1 ·f 1 /2C 2 . This meander signal comes to the manipulator  11 . As a result, the signs of all even members in the second PRS alter periodically. 
     Such second PRS inverted periodically is summed in the adders  9  and  10  with the signals from the corresponding multipliers  6  and  7  in the I and Q channels, respectively. 
     The first PRS former  8 , the second PRS former  12 , and the meander signal former  13  are clocked with the frequency C 1 ·f 1 /2 coming from a third output of the clock frequency former  4 . 
     Each of first and second digital filters  14  and  15  are configured for filtering the signals from the corresponding adders  9  and  10 . This filtering step is performed with the clock frequency C 1 ·f 1  from a fourth output of the clock frequency former  4 . It should be noted that the amplitude-frequency characteristic of both those digital filters  14  and  15  has the cutoff frequency equal to the Nyquist frequency. 
     First and second digital-to-analog converters (DACs)  16  and  17  are configured for converting the signals from the first and second digital filters  14  and  15 , respectively, into analog signals. The operation of the first and second DACs  16  and  17  is clocked with the same frequency C 1 ·f 1  as the operation of the digital filters  14 ,  15 . 
     A transmission signal former  19  is configured for forming the transmission signal from the signals of the first and second DACs  16 ,  17 . Within the former  19 , a third and fourth multipliers  20 ,  21  perform multiplication of the signals from the first and second DACs  16 ,  17 , respectively, by a cosine and sine signals (quadrature components) of the carrier frequency and summation of the results of this multiplication in an summing unit  22 . A signal from the output of the summing unit  22  in the former  19  is the transmission signal  24  which is supplied into the communication channel (not shown). 
       FIG. 3  represents a block diagram of the receiving side in the system for transmitting and receiving QAM signals according to the present invention. 
     The receiving side, which input is connected to the communication channel, comprises conventional—for any receiver—amplifying, filtering and down-converting means, which are shown in  FIG. 3  as a unit  25  for transferring to the intermediate frequency (IF). Further, the receiving side comprises a digital quadrature-amplitude demodulation unit  26  configured for dividing the received signal into a I channel signal of the receiving side and a Q channel signal of the receiving side and for performing the quadrature-amplitude demodulation of these signals. The receiving side includes also a clock frequency extractor  38  configured for extracting the clock frequencies using the signals in the I and Q channels of the receiving side. The embodiment of the clock frequency extractor  38  will be shown below. 
     The digital quadrature-amplitude demodulation unit  26  comprises a fifth and sixth multipliers  40  and  41 , each configured for multiplying the input signal transferred onto the intermediate frequency by the respective quadrature (i.e., cosine and sine) component having a frequency 
                   ω   IF     -     Δ   ⁢           ⁢   ω         2   ⁢   π       ,           ⁢     
     ⁢   where                 Δ   ⁢           ⁢   ω       2   ⁢   π           
is the frequency of the approximate detuning from the intermediate frequency
 
                 ω   IF       2   ⁢   π       .         
Signals from the fifth and sixth multipliers  40 ,  41  comes, respectively, through first and second filters  42 ,  43  to first and second analog-to-digital converters (ADCs)  44 ,  45 , respectively. Each of the ADCs  44 ,  45  is configured for converting the cosine and sine components of the received signal into corresponding digital samples with the frequency C 1 ·f 1 ′ obtained from the clock frequency f 1 ′ of the receiving side, which clock frequency is extracted in the clock frequency extractor  38 . Finally, signals from the ADCs  44 ,  45  come to a digital quadrature demodulator  46  performing the demodulation of the signals of the in-phase (I) and quadrature (Q) channels of the receiving side. The embodiment of the digital quadrature demodulator  46  will be shown below.
 
     First and second optimal digital filters  27  and  28  are configured for optimal digital filtering the signals from corresponding outputs of the digital quadrature demodulator  46  in the digital quadrature demodulation unit  26 . This filtering step is performed with the clock frequency C 1 ·f 1 ′. It should be noted that the amplitude-frequency characteristic of those optimal digital filters  27  and  28  has the cutoff frequency equal to the Nyquist frequency, as in the digital filters  14  and  15  of the transmitting side. 
     First and second units  29  and  30  of the convolution with the first PRS are configured for convolving the signals from the first and second optimal digital filters  27  and  28 , respectively, with the first PRS used at the transmitting side and known at the receiving side. First and second units  31  and  32  for convolution with the second PRS are configured for convolving the signals from the first and second optimal digital filters  27  and  28 , respectively, with the second PRS, also used at the transmitting side and known at the receiving side. 
     Each of first and second converters  33  and  34  into m-level sequence is configured for forming a sequence of m-level samples from signals of the first and second units  29  and  30  of the convolution with the first PRS, respectively. 
     A sequence combining unit  35  is configured for combining the signals from the first and second converters  33 ,  34  into m-level sequence into one sequence of the m-level samples, which is an output signal  39  of the receiving side. 
     A first frequency adjustment extractor  36  is configured for forming a frequency adjustment signal for the clock frequency extractor  38  from the signals of the first and second units  29 ,  30  of the convolution with the first PRS. 
     A second frequency adjustment extractor  37  is configured for forming a frequency adjustment signal for the digital quadrature demodulator  46  in the digital quadrature demodulation unit  26  from the signal of the first and second units  31 ,  32  for convolution with the second PRS. 
     The digital quadrature demodulator  46  in the digital quadrature demodulation unit  26  is built in accordance with the diagram shown in  FIG. 4 . The digital quadrature demodulator  46  comprises a seventh and eighth multipliers  47  and  48 , each configured for multiplying the sine component of the input signal by the corresponding quadrature component of the frequency 
                 Δ   ⁢           ⁢   ω       2   ⁢   π       ,         
and a ninth and tenth multipliers  49  and  50  each configured for multiplying the cosine component of the input signal by the corresponding quadrature component of the frequency
 
                 Δ   ⁢           ⁢   ω       2   ⁢   π       .         
The components of the frequency
 
               Δ   ⁢           ⁢   ω       2   ⁢   π           
are generated under the control of a controllable frequency synthesizer  51 . The digital quadrature demodulator  46  includes also a first subtractor  52  configured for subtracting the signals from the eighth and ninth multipliers  48 ,  49 , and a third adder  53  configured for summing the signals from the seventh and tenth multipliers  47 ,  50 . Signals from the outputs of the first subtractor  52  and third adder  53  are the signals of the in-phase (I) and quadrature (Q) channels of the receiving side.
 
     The first frequency adjustment extractor  36  ( FIG. 5 ) comprises: first and second absolute magnitude calculators  54 ,  55  configured for calculating the absolute magnitude of the signals from the first and second units  29 ,  30  of the convolution with the first PRS, respectively; a fourth adder  56  configured for summing the signals from the first and second absolute magnitude calculators  54 ,  55 ; a first phase detector  57  configured for comparing in phase the signal of the fourth adder  56  with a reference signal cos(πf 1 ′t) having the frequency f 1 ′ and being supplied from the first output of the clock frequency extractor  38 ; a first loop filter  58  connected in a clock frequency adjustment loop and configured for filtering a result of the comparison from the first phase detector  57  and for forming the frequency adjustment signal for the clock frequency extractor  38 . 
     The second frequency adjustment extractor  37  ( FIG. 6 ) comprises: first and second convolutional signal converters  59 ,  60  configured for converting the convolutional signal, respectively, from the first and second units  31 ,  32  for convolution with the second PRS into the meander signal; a third subtractor  61  configured for subtracting the signals of the first and second convolutional signal converters  59 ,  60 ; a second phase detector  62  configured for comparing in phase the signal of the third subtractor  61  with the reference signal 
             cos   ⁡     (     π   ⁢         C   1     ·     f   1   ′         2   ⁢     C   2         ⁢   t     )           
having a frequency
 
                 C   1     ·     f   1   ′         2   ⁢     C   2             
and being supplied from the second output of the clock frequency extractor  38 ; a second loop filter connected in the clock frequency adjustment loop and configured for filtering a result of the comparison from the second phase detector  62  and for forming the frequency adjustment signal for the digital quadrature demodulator  46  in the digital quadrature demodulation unit  26 .
 
     The clock frequency extractor  38  comprises a phase-locked-loop (PLL) unit configured for receiving the signal from the first frequency adjustment extractor  36  and for supplying signals cos(πf 1 ′t) and 
               cos   ⁡     (     π   ⁢         C   1     ·     f   1   ′         2   ⁢     C   2         ⁢   t     )       .         
Moreover, the clock frequency extractor  38  comprises respective frequency dividers for forming the signals having the following clock frequencies: C 1 ·f 1 ′ at the third output for clocking the ADCs  44  and  45  in the digital quadrature demodulation unit  26 , optimal digital filters  27  and  28 , units  29  and  30  of the convolution with the first PRS, and units  31  and  32  for convolution with the second PRS; f 1 ′/2 at the fourth output for clocking the converters  33  and  34  into the m-level sequence; kf 1 ′/2 at the fifth output and kf 1 ′ at the sixth output for clocking the sequence combining unit  35 .
 
     The PLL unit in the clock frequency extractor  38  could be made in accordance with any known circuit. 
     The method for transmitting and receiving QAM signals according to the present invention in implemented in the shown system as follows. 
     An initial bit sequence  1  ( FIG. 2 ) having the frequency kf 1   
             cos   ⁡     (     π   ⁢         C   1     ·     f   1   ′         2   ⁢     C   2         ⁢   t     )           
comes to the information input of the m-level symbol former  3 , which converts this bit (i.e., binary) sequence into the m-level symbol sequence, where m=2 k , k=2, 3, . . . , which m-level symbols coming out at the first clock frequency f 1 . In principle, the former  3  is not required is the initial sequence is just the m-level symbols sequence. The first clock frequency is generated in the clock frequency former  4  of the transmitting side at the first output thereof from the signal  2  having the clock frequency kf 1  coming to the input of the former  4 . In the case where the initial sequence is the m-level symbol sequence, the first clock frequency f 1  comes directly from the input. Then the additional frequency multiplication should be provided for in the clock frequency former  4 .
 
     The obtained m-level symbol sequence from the former  3  comes to the channel divider  5 , where this sequence is divided into the I channel of the transmitting side having the even m-level symbols and the Q channel of the transmitting side having the odd m-level symbols. The repetition frequency of the m-level symbols in each of the I and Q channels of the transmitting side being equal to f 1 /2. The corresponding clock signal is formed at the second output of the clock frequency former  4 . 
     In the first and second multipliers  6  and  7 , the step of enlarging the spectrum of the coming m-level sequences by means of multiplying thereof by the first PRS supplied from the first PRS former  8 . Then, the obtained signals are summed in the first and second adders  9  and  10 , respectively, with the second PRS formed in the second PRS former  12  and manipulated in the manipulator  11  with the meander signal from the meander signal former  13 . Since, as noted above, the first PRS has the zero even members and the second PRS has the zero odd members, no undesired interaction occurs between the components of the first and second PRS when summing in the adders  9  and  10 . 
     The signals from the outputs of the first and second adders  9  and  10  comes to the digital filters  14  and  15 , respectively, where the step of filtering these signals by the Nyquist criterion, or the matched filtering is carried out whereafter these signals are translated into the analog form in the first and second DACs  16  and  17 , respectively, and supplied to the transmission signal former  19 . In the transmission signal former  19 , the analog signals from the outputs of the first and second DACs  16  and  17  comes&lt;respectively, to the third and fourth multipliers  20  and  21 , where each of those analog signals is multiplied by the corresponding quadrature component of the carrier frequency signal (i.e., by the cos ω 0 t and sin ω 0 t). The results of these multiplications are fed to the summing unit  22 , from which output the transmission signal  23  is supplied into the communication channel (not shown). 
     At the receiving side ( FIG. 3 ), the signal  24  from the communication channel comes to input of the unit  25  for transferring to the IF, where this signal is amplified, filtered and transferred to the intermediate frequency 
                 ω   IF       2   ⁢   π       .         
From the unit  25  for transferring to the IF the signal comes to the digital quadrature demodulation unit  26 .
 
     In this unit  26 , the incoming signal is supplied to one of the inputs of each of fifth and sixth multipliers  40 ,  41 , and another input of each of these multipliers  40 ,  41  is supplied with the cosine or sine components of the signal having the frequency 
                   ω   IF     -     Δ   ⁢           ⁢   ω         2   ⁢   π       ,           ⁢     
     ⁢   where                 Δ   ⁢           ⁢   ω       2   ⁢   π           
is the frequency of the approximate detuning from the intermediate frequency
 
                 ω   IF       2   ⁢   π       .         
Signals from the fifth and sixth multipliers  40 ,  41  comes, respectively, through the first and second filters  42 ,  43  to the first and second analog-to-digital converters (ADCs)  44 ,  45 , respectively, where the cosine and sine components of the received signal are converted into the corresponding digital samples. The signals from the ADCs  44 ,  45  come to the digital quadrature demodulator  46  performing the demodulation of the signals of the in-phase (I) and quadrature (Q) channels of the receiving side.
 
     In the digital quadrature demodulator  46 , the signal from the first ADC  44  comes to the first inputs of the seventh and ninth multipliers  47 ,  49 , and the signal from the second ADC  45  comes to the first inputs of the eighth and tenth multipliers  48 ,  50 . The controllable frequency synthesizer  51  produces the signal 
             sin   ⁢       Δ   ⁢           ⁢   ω       2   ⁢   π             
to the second inputs of the seventh and eighth multipliers  47 ,  48  and the signal
 
             cos   ⁢       Δ   ⁢           ⁢   ω       2   ⁢   π             
to the second inputs of the ninth and tenth multipliers  49 ,  50 . The signals from the outputs of the eighth and ninth multipliers  48 ,  49  are supplied to the first subtractor  52 , from which output the signal of the in-phase (I) channel of the receiving side is output. The signals from the outputs of the seventh and tenth multipliers  47 ,  50  are supplied to the inputs of the third adder  53 , from which output the signal of the quadrature (Q) channel of the receiving side is output.
 
     The I and Q channel signals come ( FIG. 2 ), respectively, to the first and second optimal digital filters  27  and  28 , where these signals are subjected to the optimal filtration, as described for the transmitting side. The signal from the output of the first optimal digital filter  27  is supplied to the first unit  29  of the convolution with the first PRS and to the first unit  31  of the convolution with the second PRS, and the signal from the second optimal digital filter  28  is supplied to the second unit  30  of the convolution with the first PRS and to the second unit  32  of the convolution with the second PRS. These convolution operations are carried out by means of the matched filtering with the first PRS. As a result, the signals are extracted at the output of the units  29 ,  30  of the convolution with the first PRS, the spectrum of which signals being compressed in comparison with the spectrum enlarged at the transmitting side using the first PRS. In other words, the m-level symbol sequences transmitted from the transmitting side are extracted at the outputs of the units  29  and  30  of the convolution with the first PRS. Similarly, the signals having the compressed spectrum are extracted at the outputs of the units  31 ,  32  of the convolution with the second PRS. 
     The m-level symbol sequences from the units  29 ,  30  of the convolution with the first PRS come to the units  33 ,  34 , where they are converted into the k-bit code combinations, which are supplied after the step of combining in the combining sequence unit  35  in the form of the single sequence  39  to the output of the receiving side. 
     At the same time, the m-level symbol sequences from the units  29 ,  30  of the convolution with the first PRS come to the first frequency adjustment extractor  36 . 
     In this unit  36  ( FIG. 5 ), the incoming signals come, respectively, to the first and second absolute magnitude calculators  54 ,  55 , where the absolute magnitude of each m-level symbol is determined. These signals are summed in the fourth adder  56 , which signal is supplied to the first input of the first phase detector  57 , which another input is fed with the signal having the frequency f 1 ′ from the clock frequency extractor  38 . After the step of filtering in the first loop filter  58 , the extracted frequency adjustment signal is supplied to the clock frequency extractor  38  for tracking by the PLL system. 
     The m-level symbol sequences from the units  31 ,  32  of the convolution with the second PRS come to the second frequency adjustment extractor  37 . 
     In this unit  37  ( FIG. 6 ), the incoming signals come to the first inputs of the first and second convolutional signal converters  59 ,  60 , respectively, where the signal from the output of the corresponding unit  31 ,  32  of the convolution with the second PRS is converted into the meander signal. The obtained signal are subtracted in the third subtractor  61 , and the resulting signal is supplied to the first input of the second phase detector  62 , which second input is fed with the signal having the frequency C 1 ·f 1 /2C 2 . The resulting signal, after the step of filtering in the second loop filter  63 , comes to the digital quadrature demodulator  46  of the digital quadrature demodulation unit  26  for adjusting the controllable frequency synthesizer  51 . 
     Thus, the meander signal is obtained at the output of the second frequency extractor  37 , and the values of the second PRS are inverted with cycle of that meander signal. 
     Those skilled in the art will appreciate that all steps of the method for transmitting and receiving QAM signals according to the present invention could be entirely implemented not in a hardware embodiment, but also in a software embodiment, since the signal being processed is already sampled, digitized and translated into the form of bit samples. These samples will be processed by the computer processor in accordance with a program, which algorithm is practically described above. In this case, the program corresponding to the implementation of the foregoing operation algorithm, by which execution in the computer the method of the present invention could be realized, can be recorded to the machine-readable medium intended for the direct operation as a part of the computer. 
     Moreover, the method of the present invention could be purposefully used not for transmitting the information using QAM signals, but only for synchronizing the reception of quadrature-amplitude modulation signals at the time interval 
     
       
         
           
             T 
             = 
             
               
                 
                   2 
                   ⁢ 
                   kM 
                 
                 
                   f 
                   1 
                 
               
               . 
             
           
         
       
     
     Therefore, all indicated possibilities are included in the form of separate aspects into the appended claims fully defining the scope of the present invention taking into account any equivalent features used in those claims. The specification serves only the purposes for illustrating and explaining the principles rather than for limiting the scope of the present invention. 
     While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.