Abstract:
Disclosed is a method for the growing of heteroepitaxial layers of monocrystalline semiconductor materials. To this end, on a substrate made of a material of a first type, there is made a seed of a second type of material. This seed is between a face of the substrate and a confinement layer which defines a confinement space with the face of the substrate. A vapor phase epitaxy of a material of the second type is then effected in the confinement space. This material of the second type grows from the seed in the confinement space. The method can be applied to the manufacture of heterogeneous semiconductor structures and to the three-dimensional integration of semiconductor components.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a method for the making of heteroepitaxial layers, more precisely, a method for the making of at least one thin layer of a semiconductor material on a semiconductor substrate of another type. 
     The invention relates to the field of &#34;thin layers&#34; and, particularly, to the field of monocrystalline thin layers epitaxially grown on a substrate of a different nature. 
     The invention will be preferably applied to the growing of GaAs layers on Si, and it enables the removal, by blocking, of the dislocations generated at the crystal/substrate interface. 
     During the heteroepitaxial growth of GaAs on Si, dislocations are generated at the crystal/substrate interface and spread in the thin layer during the deposition. Very broadly speaking, the presence of these dislocations is due both to the difference between the lattice parameters of Si (0.54 nm) and GaAs (0.56 nm) and to the difference between their coefficients of thermal expansion (2.3 10 -6  ° C. for Si against 5.6 10 -6  ° C. -1  for GaAs). 
     These dislocations once nucleated are practically impossible to eliminate during a normal growth of the MBE (Molecular Beam Epitaxy) or MOCVD (Metal Organic Chemical Vapor Deposition) type, thus considerably limiting the application of the heteroepitaxy of GaAs on Si. 
     For, since the dislocations act as recombination centers, they drastically reduce the lifetime of the minority carriers The result of this is that it is practically impossible to make bipolar components, such as lasers and photodiodes for example, in the heteroepitaxially grown layers of GaAs. 
     A method of blocking dislocations has been developed (see the French patent application No. 88 044 38 filed on Apr. 5, 1988). This method can be used to obtain practically fault-free dislocations. The principle of this method (known as the forced growth method) is shown in FIG. 1. One of the drawbacks of this method is that it calls for the use of two dielectric levels and two masking levels to make the seeding bands, on the one hand, and the bands enabling the access of the gas of the forced epitaxy phase, on the other hand (see FIG. 1). 
     The present invention enables the above method to be considerably simplified by limiting it to a single dielectric layer and to a single masking level. 
     SUMMARY OF THE INVENTION 
     The invention therefore relates to a method for the manufacturing, by vapor phase growth, on a substrate made of a semiconductor material of a first type, of a monocrystalline thin layer of a semiconductor material of a second type, wherein the growth is initiated on at least one seed with a chemical composition identical to that of the semiconductor material of the second type, and is confined to a space defined by a face of the substrate itself and a confinement layer made of a material different from the semiconductor material of the second type, in such a way that there can be neither nucleation nor deposition of semiconductor material whether on this confinement layer or on said face of the substrate, the confinement space defining the thickness of the monocrystalline thin layer of semiconductor to be obtained. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The different objects and features of the invention shall appear more clearly from the following description and from the appended drawings, of which: 
     FIG. 1 illustrates the state of the art, already described here above; 
     FIG. 2 shows a basic drawing of the manufacturing method according to the invention. 
     FIGS. 3a to 3f show different steps of the manufacturing method according to the invention; 
     FIGS. 4a to 4f show different steps of an improvement of the method according to the invention; 
     FIG. 5 shows an intermediate structure of the method of the invention; 
     FIG. 6 shows an additional stage of a variant of the manufacturing method according to the invention; 
     FIGS. 7 and 8 show stages of manufacture, resulting from the stage of FIG. 6; 
     FIGS. 9 to 11 show stages for the manufacture of another variant of the method of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The principle of the method is shown in FIG. 2. 
     The feasibility of this method comes from the fact that it has been observed that GaAs deposited by a VPE method of the AsCl 3  +Ga type (the so-called trichlorides method) does not nucleate on the free surfaces of silicon. 
     The invention shall be described with reference to the example of GaAs heteroepitaxially grown on Si, but its framework of application is much broader. For, to make it possible to apply the present method to the heteroepitaxy of a material A on a material B, it is enough to use a deposition method enabling the elimination (at least temporarily) of the nucleation of A on B or to provide for a material B on which there can be neither nucleation nor deposition of the material A. 
     The invention shall be understood more clearly from the following description. 
     On an initial substrate 1 made of silicon (100), a thin layer 2 of GaAs (typically with a thickness of 0.5 to 1 μm) is made (see FIG. 3a). 
     A wafer that is slightly disoriented towards the direction &lt;100&gt; does not necessarily have to be used, for the faults of the antiphase domain boundary type will also be blocked as shall be seen further below. This preliminary operation of heteroepitaxy can be done by MBE (Molecular Beam Epitaxy), MOCVD (Metal Organic Chemical Vapor Deposition), MOMBE (Metal Organic Molecular Beam Epitaxy), CBE (Chemical Beam Epitaxy) etc. 
     It is known (see for example the article by H. Kroemer in the book, &#34;Heteroepitaxy on Silicon&#34;, edited by Fan and Poate, MRS Symposia Proceedings, No. 67, Pittsburgh Pa., 1986) that the layers of GaAs made by methods such as those referred to above contain, in the optimum cases, about 10 6  dislocations per cm 2 . They may also contain microtwins and antiphase domain boundaries depending on the conditions of growth. It is naturally impossible to manufacture lasers and photodiodes in the layers having a density of faults such as this. 
     On the GaAs layer 2, a uniform layer 3 of Si 3  N 4  is made. This layer 3 has a typical thickness of the order of 0.3 to 0.9 μm (FIG. 3b). Si 3  N 4  has been chosen in this exemplary embodiment, but it could also be any other material on which there could be neither nucleation nor deposition of the material (GaAs according to the example taken) which will be epitaxially grown in the following stages. 
     In this layer 3 of Si 3  N 4 , there is etched a series of apertures 4 taking the form of equidistant parallel bands. 
     The size of the apertures of these bands is of the order of one to several microns, and the repetition pitch is typically equal to some tens of microns, and may go up to several hundreds of μm (see FIG. 3c). 
     These bands are oriented in such a way that, during the lateral growth which shall be carried out subsequently, there appears no single growth facet of the (111) type, which would have the effect of limiting the speed of lateral growth. Orientations of the &lt;110&gt; and &lt;110&gt; type will therefore be avoided for these bands. It has been observed that one group of orientations giving satisfactory results ranges from 15 to 30 degrees, for example 22.5°, on either side of the directions &lt;110&gt; and &lt;110&gt; mentioned above. This does not, however, restrict the scope of the invention and it may be necessary to use exact &lt;110&gt; type orientations if (110) or (111) type facets are to be introduced. 
     The structure of FIG. 3c is submerged in a reagent for the chemical attacking of the layer 2. For example, a mixture of H 2  O 2  and H 2  SO 4  is appropriate to the selective elimination of a part of the thin layer 2 of the heteroepitaxially grown GaAs. However, the attacking of the layer 2 is stopped so as to preserve a central part 20 that is used to support the layer 3 of Si 3  N 4  and will act as a seed during the operation of growth that follows. Thus, the structure of FIG. 3d is obtained. 
     The structure of FIG. 3d is introduced into a reactor, for example of the VPE (vapor phase epitaxy) type, using AsCl 3  and Ga as its sources. Under normal deposition conditions, i.e. when the Ga source is kept towards 850° C., the mole fraction of AsCl 3  is 10 -3  and the substrate is kept in the region of 750° C., it is seen that there is nucleation and growth of GaAs on the central seed 20 but, on the contrary, neither nucleation nor growth is observed, whether on the exposed surfaces of the layer 3 of Si 3  N 4  or on the Si substrate 1 (100). 
     A similar effect of selective growth may be obtained by using an MOCVD type reactor, with precursors that are no longer of the triethyl or trimethyl gallium type but incorporate chlorides, namely precursors such as diethylgallium chloride (C 2  H 5 ) 2  GaCl (see, for example, the document by Kuech et al, Proceedings of the 5th International Conference on MOVPE, Aachen, Germany Jun. 18-22, 1990). 
     Growth from the central seed 20 of GaAs is therefore done in the manner shown in FIG. 3e, between the surface of the substrate Si (100) and the lower surface of the layer 3 of Si 3  N 4 , without there being nucleation on Si and Si 3  N 4 . 
     A phenomenon of the blocking of all the faults that are not strictly parallel to the GaAs/Si 3  N 4  interfaces (dislocations, microtwins and antiphase domain boundaries) is seen here. This blocking is done either on the lower face 30 of the layer 3 or on the surface of the Si (100) substrate 1, as is shown in FIG. 3f. Once the defects have been blocked, the growth continues normally on either side of the central seed 20, the crystal obtained being then one of excellent quality 
     During a following step, the layer 3 is removed and GaAs semiconductor elements in thin layers are obtained on a silicon substrate. 
     In one variant of the technique, the structure shown in FIG. 3c is introduced directly into the epitaxy reactor. The attacking of the GaAs layer 2 through the apertures 4 made in the layer 3 of Si 3  N 4  is then done in situ by hydrochloric acid HCl, either generated by the breakdown of AsCl 3  in the case of a trichloride reactor (it is then necessary to have an additional line of AsCl 3  that does not go through the Ga charge) or directly injected from a bottle in the case of an MOCVD reactor. The structure obtained after this in situ attack is identical to that of FIG. 3d. The subsequent steps remain unchanged. 
     It is observed, however, that the central region of the thin layer obtained remains defective which, depending on the applications envisaged, may raise problems. A description is given below of a way to overcome this drawback. 
     The initial situation is shown schematically in FIG. 4a. It results from the previous method, and the epitaxial growth has been deliberately stopped in the confinement space 5 before the aperture 4 is reached, in order to avoid overflows. 
     The method is continued by the opening, in the layer 3, of a window 6 parallel to the edges of the layer. This is done above the region of the seed 20 (FIG. 4b). The region of the seed and of defective GaAs is eliminated by chemical attack, for example by means of H 2  O 2 , H 2  SO 4  (see FIG. 4c). This defective region can also be eliminated by an attack in situ in the epitaxy reactor, as described here above. 
     The selective epitaxial operation is repeated so as to fill a part of the gap left by the attack on the defective crystal (FIG. 4d). This operation of selective epitaxy is stopped when the two growth fronts F 1  and F 2  at the position where the defective crystal was located earlier are at a distance, from each other, of about Δ1=1 μm (typical but non-restrictive value). 
     The layer 2 of Si 3  N 4  is then eliminated (by HF attack for example) so as to obtain the structure of FIG. 4e. 
     If the different bands have been oriented by 22.5° from the direction &lt;110&gt; as indicated here above, there is observed, for GaAs, a ratio of the order of 4 between the speed of growth of the lateral front and the speed of growth of the vertical front (here the plane (100) of the surface). Under these conditions, if the distance Δ1 between the fronts F 1  and F 2  (FIG. 4e) has been kept at a small value (typically 1 μm as indicated here above), it is possible to make these two fronts meet by carrying out a low vertical growth (typically of the order of Δ1/8=0.125 μm, for an original spacing of the order of 1=1 μm between F 1  and F 2 ). 
     Thus, if it is desired to obtain a thin layer with a final thickness e 2 , the starting thickness e 1  (see FIG. 4a) will be chosen so that 
     
         e.sub.1 =e.sub.2 -Δ1/8, 
    
     which dictates the additional condition Δ1&lt;8e 2  during the lithography step of FIG. 4b leading to the etching of the layer 3 of Si 2  N 4  above the defective region. Thus we obtain a layer 7 of a fault-free monocrystalline semiconductor material of a certain type (GaAs according to the example chosen) on a semiconductor material of another type (silicon according to the example chosen). 
     The dimension of the bands in the direction parallel to the apertures such as 4 has been considered to be limited solely by the size of the substrate. The situation is summarized in FIG. 5 where, in the direction of the axis yy&#39;, the dimension of the bands resulting from the etching in the nitride layer 3 is not restricted (or is restricted only by the dimension of the substrate). In fact, it may be worthwhile to limit the GaAs seeding zones along the axis yy&#39; in order to reduce the cooling stresses (due to the differences between the thermal expansion coefficients of GaAs and Si) in the seeding band 20, where the GaAs crystal has been nucleated on the substrate Si during the prior MBE or MOCVD operation. These stresses could lead, for example, to an undulation of the end of the GaAs films after forced growth. 
     A variant of the method of the invention therefore starts with the etching of insulation bands 8 in the layer 2 (GaAs) heteroepitaxially grown on the substrate. 
     The repetition pitch of these insulation bands 8 is typically 50 to 100 μm and the width of these bands is typically one to several microns (see FIG. 6). These bands are oriented as above, preferably at about 22.5° with respect to a direction &lt;110&gt; or (along xx&#39; in FIG. 6). 
     The layer 3 of Si 3  N 4  is then deposited on the previously etched surface. FIG. 7 shows a section along yy&#39; after the deposition of this layer 3 of Si 3  N 4 . 
     The typical thickness of the layer 3 of Si 3  N 4  is 0.5 to 1 μm. 
     Just as in FIG. 3c, a second system of bands 9 is etched in the layer 3 of Si 3  N 4 . This second system of bands 9 may be preferably perpendicular to the first bands, i.e. perpendicular to the etchings 8 as shown in FIG. 8. 
     These bands typically have a width of 1 to 10 μm, and their repetition pitch ranges from some tens to some hundreds of microns. 
     The operations described with reference to FIGS. 3d and 3e are then repeated These FIGS. 3d and 3e may now be considered to be sections of FIG. 8 along the axis xx&#39;. 
     Thus, after forced growth and removal of the layer 3, we obtain GaAs blocks which are fault-free apart from the central seeding zone 20 (FIG. 9). The seed 20 and the band of faults can be eliminated according to the same type of operation as described in relation to FIG. 4. 
     To this end, as shown in FIG. 10 before the removal of the layer 3, an etching is done of bands 6 in the layer 3, along a direction yy&#39; so as to make an aperture above each seed 20. This operation corresponds to that of FIG. 4b. Then, as described in relation with FIG. 4c, a chemical attack is carried out on the seeds 20 and the defective semiconductor parts. Then an epitaxy of the same material as the bands 7 (GaAs) is made, the Si 3  N 4  layer is removed and blocks of semiconductor material are obtained such as those shown in FIG. 11, made of fault-free semiconductor material. 
     It is then possible, if necessary, to effect a growth of semiconductor material (GaAs) on the blocks such as 17 and 27 (in a manner similar to that done with reference to FIG. 4f) so as to join two blocks 17 and 27. 
     According to the invention, it is also possible to modulate the composition of the epitaxially grown layer 15 or provide for a doping of the layer (doping of a same type, modulated or unmodulated, or else dopings of different types) as described in the French patent application No. 89 04257 filed on Mar. 31, 1989). 
     It is also possible to use the layer 15 obtained as a starting substrate for a following epitaxy and to continue the process in this manner to obtain a superimposition of epitaxially grown layers, or even a superimposition of components located in different planes. 
     The method of the invention may be applied to the making of monocrystalline thin layers of semiconductor materials on amorphous or polycrystalline insulators. It may enable the making of special structures (double-gate field-effect transistors, permeable base transistors, heterostructures and lateral superlattices etc.). 
     The method of the invention can thus be used to achieve growth with semiconductors of different natures and to obtain heteroepitaxial structures in which the different layers are nonetheless monocrystalline and have neither dislocations nor fault planes. 
     It is clear that the above description has been given purely as a non-restrictive example. Other variants may be envisaged without going beyond the scope of the invention. The numerical values have been given soley in order to illustrate the description. Besides, as already mentioned, the application of the invention to a semiconductor-based structure as indicated in the description has been provided solely by way of an example, and other materials could be used.