Abstract:
Embodiments of the invention provide processes for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a copper-containing surface and a dielectric surface, exposing the substrate to a ruthenium precursor to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface, and depositing a copper bulk layer over the ruthenium-containing film.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims benefit of U.S. Ser. No. 60/976,113 (APPM/011881 L), filed Sep. 28, 2007, which is herein incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    Embodiments of the invention generally relate to a metallization process for manufacturing semiconductor devices, and more particularly, to depositing ruthenium and copper materials on a substrate. 
         [0004]    2. Description of the Related Art 
         [0005]    Copper is the current metal of choice for use in multilevel metallization processes that are crucial to semiconductor and electronic device manufacturing. The multilevel interconnects that drive the manufacturing processes require planarization of high aspect ratio apertures including contacts, vias, lines, and other features. Filling the features without creating voids or deforming the feature geometry is more difficult when the features have higher aspect ratios. Reliable formation of interconnects is also more difficult as manufacturers strive to increase circuit density and quality. 
         [0006]    As the use of copper has permeated the marketplace because of its relative low cost and processing properties, semiconductor manufacturers continue to look for ways to improve the boundary regions between copper and dielectric material by reducing copper diffusion and dewetting. Several processing methods have been developed to manufacture copper interconnects as feature sizes have decreased. Each processing method may increase the likelihood of errors such as copper diffusion across boundary regions, copper crystalline structure deformation, and dewetting. Physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemical plating (ECP), and electroless deposition, are processes for depositing copper while chemical mechanical polishing (CMP) and electrochemical mechanical polishing (ECMP) are processes for removing copper. These processes utilize mechanical, electrical, and/or chemical techniques to manipulate the copper materials that form interconnects. Barrier and capping layers may be deposited to contain the copper material. 
         [0007]    In the past, a layer of tantalum, tantalum nitride, or copper alloy with tin, aluminum, or magnesium was used to provide a barrier layer or an adhesion promoter between copper and other materials. These options are costly or only partially effective or both. As the copper atoms along the boundary regions experience changes in temperature, pressure, atmospheric conditions, or other process variables common during multiple step semiconductor processing, the copper may migrate along the boundary regions and become agglomerated copper. The copper may also be less uniformly dispersed along the boundary regions and become dewetted copper. These changes in the boundary region include stress migration and electromigration of the copper atoms. The stress migration and electromigration of copper across the dielectric layers or other structures increases the resistivity of the resulting structures and reduces the reliability of the resulting devices. 
         [0008]    Barrier layers containing ruthenium have been deposited by PVD, CVD, and ALD processes. PVD processes for depositing ruthenium are often hard to control the precise thicknesses of the deposited material. CVD processes usually suffer from poor conformality and contaminants in the deposited ruthenium-containing film. During a typical ALD process, a ruthenium precursor and a reducing agent are sequentially exposed to a substrate to form the desired ruthenium-containing film. ALD processes have several advantages over other vapor deposition processes, such as very conformal films and the ability to deposit into high aspect ratio vias. However, the deposition rates of an ALD process are often too slow, so that ALD processes are not often used in commercial applications. Also, ruthenium is usually deposited across the overall substrate surface by ALD, regardless that the exposed substrate surface may have various types of materials. 
         [0009]    Therefore, a need exists to enhance the stability and adhesion of copper-containing layers, especially for copper seed layers. Also, a need exists to improve the electromigration (EM) reliability of copper-containing layer, especially for copper line formations, while preventing the diffusion of copper into neighboring materials, such as dielectric materials. A further need exist for an improved vapor deposition process to deposit ruthenium materials. 
       SUMMARY OF THE INVENTION 
       [0010]    Embodiments of the invention provide methods for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning the substrate within a processing chamber, wherein the substrate contains a copper-containing surface and a dielectric surface, exposing the substrate to a ruthenium precursor to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface, and depositing a copper bulk layer over the ruthenium-containing film. In one example, a copper seed layer may be deposited by a physical vapor deposition (PVD) process and the copper bulk layer may be deposited by an electrochemical plating (ECP) process. 
         [0011]    In another embodiment, a method for forming layers on a substrate is provided which includes positioning exposing the substrate to a ruthenium precursor containing an organic ligand to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface. The ruthenium precursor reacts with the copper-containing surface to form copper-containing compounds containing the organic ligand. The method further provides removing the copper-containing compounds as a gas from the processing chamber and depositing a copper bulk layer over the ruthenium-containing film. 
         [0012]    In various examples, the ruthenium-containing film may be deposited by a vapor deposition process while the substrate is heated to a temperature within a range from about 100° C. to about 400° C. In some examples, the ruthenium-containing film may have a thickness within a range from about 2 Å to about 20 Å. In other examples, the ruthenium-containing film may have a thickness of about 100 Å or less, preferably, about 20 Å or less, such as about 10 Å or less. 
         [0013]    The ruthenium precursor used during the deposition process may contain at least one ligand that includes cyclopentadienyl, alkylcyclopentadienyl, pentadienyl, alkylpentadienyl, amindinate, carbonyl, pyrrolyl, oxide, derivatives thereof, or combinations thereof. Some exemplary ruthenium precursors include bis(cyclopentadienyl)ruthenium, bis(2,4-dimethylcyclopentadienyl)ruthenium, bis(2,4-diethylcyclopentadienyl)ruthenium, bis(methylethylcyclopentadienyl)ruthenium, (methylcyclopentadienyl)(ethylcyclopentadienyl)ruthenium, bis(2,4-dimethylpentadienyl)ruthenium, bis(2,4-diethylpentadienyl)ruthenium, (2,4-dimethylpentadienyl)(cyclopentadienyl)ruthenium, (2,4-dimethylpentadienyl)(methylcyclopentadienyl)ruthenium, (2,4-dimethylpentadienyl)(ethylcyclopentadienyl)ruthenium, derivatives thereof, or combinations thereof. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    So that the manner in which the above recited features of the invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
           [0015]      FIGS. 1A-1E  depict schematic views of a substrate at different process steps according to an embodiment described herein; and 
           [0016]      FIGS. 2A-2B  depict schematic views of a substrate at different process steps according to another embodiment described herein. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Embodiments of the invention provide a method that utilizes a ruthenium-containing film to prevent copper diffusion and dewetting in interconnect boundary regions. The transition metal, for example, ruthenium, improves copper boundary region properties to promote adhesion, decrease diffusion and agglomeration, and encourage uniform roughness and wetting of the substrate surface during processing. Embodiments provide that a ruthenium-containing film may be deposited on a copper seed layer prior to bulk copper deposition in order to improve the dewetting of the copper seed layer. 
         [0018]      FIGS. 1A-1E  illustrate a ruthenium-containing film between a copper seed layer and a copper bulk layer. It is believed that the presence of a ruthenium-containing film has a minimal effect on resistivity and decreases the likelihood of copper dewetting.  FIG. 1A  illustrates substrate  100  with dielectric layer  101  having via  102  formed therein with base  103  that reveals metal feature  104  such as a copper-containing feature deposited below dielectric layer  101 . In one example, metal feature  104  contains copper or a copper alloy and has a copper-containing surface. Dielectric surface  110  of dielectric layer  101  extends across the field of substrate  100 . 
         [0019]      FIG. 1B  shows optional barrier layer  105  conformally deposited within via  102  over dielectric layer  101 . Barrier layer  105  may be deposited by a PVD process or a selective ALD or CVD process. Barrier layer  105  may have a thickness within a range from about 5 Å to about 50 Å, preferably, from about 10 Å to about 30 Å. Barrier layer  105  may contain titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, silicides thereof, borides thereof, derivatives thereof, or combinations thereof. 
         [0020]    In some embodiments, barrier layer  105  may contain multiple layers, such as a bilayer of metallic tantalum and tantalum nitride, a bilayer of metallic titanium and titanium nitride, or a bilayer of metallic tungsten and tungsten nitride. In one example, barrier layer  105  may contain a tantalum/tantalum nitride bilayer or a titanium/titanium nitride bilayer. During a PVD process, barrier layer  105  may contain tantalum nitride and metallic tantalum layers deposited followed by an etching step, or a tantalum nitride layer may be deposited followed by an etching step followed by an additional tantalum deposition step. The subsequent etching step opens the bottom of the feature down to metal feature  104 . 
         [0021]      FIG. 1C  illustrates copper seed layer  106  deposited on barrier layer  105 . Copper seed layer  106  may be deposited by a vapor deposition process, such as ALD, PVD, or CVD or by a liquid process, such as ECP or electroless deposition. In one embodiment, copper seed layer  106  may have a thickness within a range from about 2 Å to about 100 Å. In another embodiment, copper seed layer  106  may have a thickness within a range from about 50 Å to about 1,500 Å. In one example, copper seed layer  106  is deposited by a PVD process. In one example, copper seed layer  106  contains copper or a copper alloy and has a copper-containing surface. Alternatively, copper seed layer  106  may be deposited by alternating a copper containing precursor and a reducing agent during an ALD process. 
         [0022]      FIG. 1D  illustrates ruthenium film  107  selectively deposited on copper seed layer  106 . Ruthenium film  107  is intended to lock the grain boundaries of copper seed layer  106  to minimize agglomeration. Accordingly, ruthenium film  107  may be a continuous layer or a discontinuous layer across copper seed layer  106 . However, since ruthenium film  107  is selectively deposited on copper seed layer  106 , dielectric surface  110  is free or at least substantially free of ruthenium film  107 . Ruthenium film  107  may have a thickness of about 100 Å or less, preferably, about 40 Å or less, more preferably, about 20 Å or less, such as about 10 Å or less. In one example, ruthenium film  107  may have a thickness within a range from about 2 Å to about 20 Å. 
         [0023]    Ruthenium film  107  may be deposited on copper seed layer  106  by thermal decomposition of a ruthenium precursor contained within a carrier gas. The carrier gas may be argon, nitrogen, hydrogen, or combinations thereof. In one embodiment, the carrier gas may be inert or substantially inert and contain nitrogen gas or argon. In another embodiment, the carrier gas may be a reducing agent, such as hydrogen gas. 
         [0024]    The substrate may be heated to a temperature within a range from about 100° C. to about 400° C. during a thermal decomposition process. The ruthenium precursor used during the deposition process may contain at least one ligand that includes cyclopentadienyl, alkylcyclopentadienyl, pentadienyl, alkylpentadienyl, amindinate, carbonyl, pyrrolyl, oxide, derivatives thereof, or combinations thereof. Some exemplary ruthenium precursors include bis(cyclopentadienyl)ruthenium, bis(methylcyclopentadienyl)ruthenium, bis(ethylcyclopentadienyl)ruthenium, bis(dimethylcyclopentadienyl)ruthenium, bis(diethylcyclopentadienyl)ruthenium, bis(methylethylcyclopentadienyl)ruthenium, (methylcyclopentadienyl)(ethylcyclopentadienyl)ruthenium, (methylcyclopentadienyl)(ethylcyclopentadienyl)ruthenium, bis(2,4-dimethylpentadienyl)ruthenium, bis(2,4-diethylpentadienyl)ruthenium, (2,4-dimethylpentadienyl)(cyclopentadienyl)ruthenium, (2,4-dimethylpentadienyl)(methylcyclopentadienyl)ruthenium, (2,4-dimethylpentadienyl)(ethylcyclopentadienyl)ruthenium, or derivatives thereof. In one example, the ruthenium precursor is methylcyclopentadienyl ethylcyclopentadienyl ruthenium. 
         [0025]    In an alternative embodiment, ruthenium film  107  may be deposited by exposing the substrate to the ruthenium precursor gas and a reducing gas or other reagent during an ALD process or a CVD process. Ruthenium materials may be deposited by ALD processes further described in commonly assigned U.S. Pat. No. 7,264,846 and U.S. Ser. No. 10/811,230, filed Mar. 26, 2004, and published as US 2004-0241321, which are herein incorporated by reference. 
         [0026]      FIG. 1E  shows copper bulk layer  108  deposited over ruthenium film  107 . In one example, copper bulk layer  108  may be deposited by an ECP process. It is believed that the transition metal layers facilitate the ECP process when the seed layer is thin and/or discontinuous. Ruthenium film  107  may provide a conductive bridge across the surface of substrate  100  to facilitate current distribution across the substrate and across areas where seed layer  106  may be discontinuous. Copper bulk layer  108  may also be deposited by PVD, CVD, electroless deposition, or other deposition methods. 
         [0027]    In another embodiment,  FIGS. 2A-2B  illustrate an additional embodiment utilizing a ruthenium film or layer in a capping layer application deposited on a metal feature such as copper.  FIG. 2A  illustrates dielectric layer  201  with ruthenium film  202 , barrier layer  203  (e.g., tantalum nitride), and copper bulk layer  204  deposited in a feature formed therein on substrate  200 . Ruthenium film  202  is optional deposited on substrate  200 . The upper surface of substrate  200  has been chemically mechanically polished following copper deposition leaving exposed upper surface  212  of copper bulk layer  204  and dielectric surface  210  of dielectric layer  201 . Ruthenium film  205  is selectively deposited on upper surface  212  of copper bulk layer  204  while leaving dielectric surface  210  free or at least substantially free of ruthenium film  205 . The ruthenium is preferably deposited on the exposed copper surface or copper bulk layer  204  by thermal decomposition of a ruthenium precursor that may be combined with a carrier gas. The same deposition process for depositing ruthenium film  107  may be used to deposit ruthenium films  202  or  205 , including using the same temperatures, ruthenium precursors, carrier gases, and other process variables. 
         [0028]    Alternatively, ALD or CVD may be used to deposit the ruthenium. Ruthenium film  205  improves copper adhesion to subsequent capping layers formed thereon. Ruthenium film  205  may act as a capping layer. Alternatively, a separate capping layer or another copper layer may be deposited on ruthenium film  205  as layer  206 , depicted in  FIG. 2B . 
         [0029]    Optionally, a chemical treatment may be used to treat ruthenium film  205  before depositing layer  206 . Chemical treatments include exposing the substrate surface to cleaning agents, complexing agents, or other chemicals and rinsing the substrate. As one example, a material such as cobalt tungsten or cobalt tungsten phosphorous may be deposited as layer  206  on ruthenium film  205 . In another example, a bulk copper material may be deposited as layer  206  on ruthenium film  205 . Layer  206  containing copper may also be deposited by PVD, ECP, electroless deposition, or other deposition methods. 
         [0030]      FIG. 2B  illustrates layer  206  deposited on top of ruthenium film  205 . Layer  206  containing a capping material may be deposited by an electroless process. In an electroless process, the substrate is exposed to a liquid containing the precursors for the capping layer. A capping process that may be used herein which utilizes a ruthenium-containing film in combination with an additional materials is disclosed in commonly assigned, now abandoned U.S. Ser. No. 10/967,099, filed on Oct. 15, 2004, and published as US 2005-0085031, which is incorporated herein by reference. 
         [0031]    A low dielectric constant barrier layer such as a silicon carbide based layer and/or a silicon nitride layer may be deposited conformally on ruthenium film  205  or layer  206 . An example of a suitable film is a silicon carbide based film formed using CVD or plasma enhanced CVD (PE-CVD) processes such as the processes described in commonly assigned U.S. Pat. Nos. 6,537,733, 6,790,788, and 6,890,850, which are herein incorporated by reference. It is believed that the ruthenium-containing film improves adhesion between subsequently deposited low dielectric constant film, such as a silicon and carbon containing low dielectric constant film, and capping layers. An additional dielectric deposition step may follow the silicon carbide and/or silicon nitride deposition. 
         [0032]    While the foregoing is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.