Abstract:
A process and an apparatus to calculate the FCS (Frame Check Sequence) error checking code of packets payload sent over a fixed size packet networks in a network equipment sending said packets and to check said FCS in the network equipment receiving said packet; this invention applies to calculations of FCS based on CRC (Cyclic Redundancy Checking) codes generated by the polynomial generator of degree 10, G(X)=X 10  +X 9  +X 5  +X 4  +X+1. Particularly, this invention is for use in the ATM layer of ATM nodes processing OA&amp;M and AAL3/4 ATM cells. The solution consists in using the calculation of the FCS based on the CRC code generated by the polynomial generator of degree 9, X 9  +X 4  +1 and simple operations. The calculation and the checking of the FCS is simple and thus the performance are improved authorizing the support of higher speed network lines.

Description:
FIELD OF THE INVENTION 
     This invention relates to Frame Check Sequence (FCS) error code calculation for data integrity checking of packets in high speed packet networks. The invention can be applied to Asynchronous Transfer Mode (ATM) networks in which high speeds require a fast process for data integrity checking. 
     BACKGROUND OF THE INVENTION 
     When digital messages are transmitted over telecommunication networks some errors can be expected and to insure data integrity, the serialized data is protected with Error Detection Codes. In modern high speed networks the lines have a low error rate and the security of data only requires a end to end process. The data integrity process is carried out at both the sending and the receiving station; the sending station calculates a code corresponding to the data and the transmitting station checks the integrity of the data and code. ATM uses Frame Check Sequence (FCS) field derived from Cyclic Redundancy Check (CRC) Error Detection codes for error checking. The CRC codes are often used for checking integrity of data because they are easy to implement and they detect a wide range of errors. The access nodes of an ATM network having the responsibility of data integrity, the originating node calculates the redundancy bits constituting the Frame Check Sequence, (FCS) which is appended by the originating system to the bit stream to be checked before sending it over the network. At the end node, a new FCS is computed on the bit stream plus its initial FCS. There is no error in transmission if the computed FCS at the end node yields a constant value depending on the type of CRC used. 
     CRC codes are generated by a generator polynomial characterizing the type of CRC; the CRC code corresponding to the polynomial representation of a bit stream to be encoded is the remainder of the polynomial division of the polynomial representation of the bit stream by the polynomial generator; CRC calculations are described, for instance, in `Teleinformatique I` of Henri Nussbaumer, 1987, Presses informatiques romandes CH-1015 Lausanne. The FCS code has been standardized for data integrity checking as described in the ANSI X3.139-1987 document pages 28 and 29 and in the Appendix B. All the CRC codes constitute a finite mathematical multiplying group. If the polynomial generator is of degree d and if it is irreducible, the finite group constitutes a Galois Field having 2 d  -1 elements. The facility of implementing codes based on CRC is due to the simple characteristics of calculations in the finite Galois Fields. 
     In ATM networks different types of connections between two end points may be established depending on the quality of service required. The ATM Forum organization followed by the ATM network industry and some ATM standards organizations (ITU-T The International Telecommunication Union-Telecommunication and ETSI The European Telecommunication Standardization Institute) have standardized different ATM Adaptation Layers (AALS) to provide generalized interworking across the ATM network. This AAL function is implemented in the ATM end point which connects to the ATM network over the User Network Interface (UNI). As ATM switches usually contain endpoint functions as well as switch functions, AAL function is also implemented in ATM switches. In the case of data, this AAL function takes frames (blocks) of data delivered to the ATM network, breaks them up into cells and adds necessary header information to allow rebuilding of the original block at the receiver. Different AALs correspond to different traffic types. For instance, if AAL1 is used for the service class A, circuit emulation, AAL3/4 provides an end-to-end transport for both connection oriented (class C) and connectionless data (class D). 
     The ATM cell headers have their own error checking based on FCS calculation. The payload of 384 bits (48 bytes) of some ATM cells uses FCS redundancy bits for error checking; The AAL3/4 cell payload error checking is based on the CRC-10 codes generated by the generator polynomial of degree 10: 
     
         G(X)=X.sup.10 +X.sup.9 +X.sup.5 +X.sup.4 +X+1 
    
     The ATM Operations Administration and Maintenance (OA&amp;M) cell payload also uses FCS redundancy bits for error checking based on CRC-10 codes. The OA&amp;M cells are used for supporting protocols specified as part of the ATM layer designed to dynamically test ATM connections, links, virtual Channels, Virtual Paths and links. These protocols perform the functions of performance monitoring, defect and failure detection, system protection, failure or performance information and fault isolation. These functions must be performed by the management system in an ATM network according to the ATM forum recommendations. 
     The polynomial representation of a CRC-10 code of a bit stream represented by the polynomial P(X) is the remainder of the polynomial division of P(X) by the generator polynomial G(X) Assuming the CRC-10 code of a data bits stream represented by the polynomial Ps(X) is Rem G  (PA(X) the corresponding FCS code based on CRC-10 is: 
     
         FCS (P(X))=Rem.sub.G (X.sup.10 P(X)+X.sup.k L(X)) 
    
     k=degree of p(x) 
     L (X)=X 10  +X 9  + . . . +X 2  +X+1 
     The standard circuitry for computing the FCS of a message is a Linear Feedback Shift Register (LFSR) which carries out a bit by bit multiplication in the Galois Field. Each bit of the message is pushed in the LFSR, Most Significant Bit (MSB) first. The division is performed by the feedbacks. At the end of the process, the FCS (remainder of the division) is within the shift register. This method and type of circuitry is described, for instance in `Error Checking Codes` by Peterson and Weldon, the MIT Press, 2nd edition, 1972. Although simple the method suffers drawbacks since only one bit is processed at each shift as many shifts as the number of bits is the message is needed in the LFSR. As the 10 bits CRC is used, a 10-bit register is needed. Therefore computing the CRC takes as many clock pulses as there are bits in the message. 
     A faster CRC calculation is provided in the patent application published under the reference EP 0614 294 entitled `Method for generating a frame check sequence` disclosing a one (or more) byte(s) based FCS calculation, this method being more efficient than a bit based FCS calculation as with the LFSRs. This patent application takes advantage of the properties of the operations in the Galois Fields. One property of the Galois Field is to have a root α, an irreducible polynomial element of the Galois Field, characterized in that each element of the Galois Field is represented by α d , d being one integer greater or equal to zero and smaller than the number of elements of the Galois Field. According to the preferred embodiment of the cited patent application, the calculation of FCS of a byte stream can be performed byte by byte, each new byte read being XORed with the result of the multiplication of the previous FCS value by the α 8  element of the Galois Field. The multiplier is the implementation of the α 8  multiplication in the Galois Field, this means modulo the polynomial generator G(X). The mathematical formula illustrating the method is expressed in the Galois Field as follows: 
     
         FCS(N+1)=FCS(N)α.sup.8 +B(N+1)                       (expression 1) 
    
     Where FCS(N) is the FCS of the message consisting of the N previous bytes, B(N+1) the polynomial representation of the next byte (new byte) of the message. 
      is the sign of the polynomial multiplication in the Galois Field. It is a two step operation comprising a first step to multiply the two polynomials and a second step to take the remainder of the result in the division by G. 
     α at is an irreducible polynomial, root of the Galois Field generated by G. 
     α 8  is the 9th element of the Galois Field (simple element having only one coefficient equal to 1 in its polynomial representation). 
     This per byte calculation of the FCS is implemented using a Multiplier adder implemented in adapter cards of the ATM access nodes. The same method can be used also for this calculation while handling any number of bits at a time consequently improving the processing time. However, with the method of the prior art and the current technologies, it is very difficult to perform the FCS calculations for data integrity checking of cell payload while sustaining media speed particularly over OC3 links (155 Mbps which allows 2.8 μs to process the cell). 
     It is the object of the invention to simplify and reduce process time of cell payload FCS calculations such as those performed in an ATM access node sending OA&amp;M or AAL3/4 types of cells on the ATM network. The same performance improvement should apply to the process of checking the OA&amp;M or AAL3/4 cell payload FCS in the access node at cell reception. 
     SUMMARY OF THE INVENTION 
     The invention discloses a method for calculating the FCS (Frame Check Sequence) based on CRC (Cyclic Redundancy Check) code generated by the polynomial generator of degree 10, G10(X)=X 10  +X 9  +X 5  +X 4  +X+1, of a packet payload in a packet network, said method comprising the steps of: 
     calculating (520) CRC code generated by the polynomial generator of degree 9, G9(X)=X 9  +X 4  +1, of the packet payload and storing the resulting 9-bit stream FCS in 9-bit storage means; 
     calculating (510) the parity of said payload; setting (580) the most significant bot of the 10-bit storage means to zero; 
     if the payload parity is odd (590), adding (597) the 9-bit stream FCS to a bit stream representation of the generator polynomial of degree 9, G9(X); and 
     storing the 10-bit stream resulting from the addition of the previous step in the 10-bit storage means, this stored 10-bit stream representing the payload FCS that was to be calculated; 
     if the payload parity is even, storing (595) the 9-bit stream FCS in the least significant bits of the 10-bit storage means, the 10-bit stream of the 10-bit storage means representing the payload FCS that was to be calculated. 
     The method of the invention turns a CRC calculation based on the polynomial generator of degree 10, G10(X)=X 10  +X 9  +X 5  +X 4  +X+1 into a much simpler CRC calculation based on the simpler polynomial generator of degree 9, G9(X)=X9+X 4  +1. 
     The step of the method implementing the calculation of the CRC code generated by the polynomial generator of degree 9, G9(X)=X 9  +X 4  +1 of the packet payload can be performed by any known method of CRC calculation; more particularly, this CRC calculation can use the calculation in the Galois Field disclosed in the prior art which adds in the simplification and as reducing processing brings more performance. Combining the method of the present invention with this known CRC calculation brings a simplification leading to higher performance; consequently, when implemented in ATM nodes adapters, the method of the invention allows support of higher speed lines. 
     The invention discloses also an apparatus comprising means for implementing the steps of the method disclosed in the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts the OA&amp;M cells flow in an ATM network 
     FIG. 2 depicts the logical diagram of a Byte wise calculation of FCS. 
     FIG. 3 illustrates the Galois Field multiplier/Adder of FIG. 2. 
     FIG. 4 illustrates the component of FIG. 2 allowing calculation of FCS from the current Remainder Register. 
     FIG. 5 is the chart flow of the generation of FCS and the checking of FCS. 
     FIG. 6 illustrates the calculation of bit 5 of FIG. 3 which is set in the current Remainder Register. 
     FIG. 7 illustrates all the operations caracterizing the Galois Field multiplier Adder of FIG. 2 based on the Galois Field generated by the generator polynomial of degree 9. 
     FIG. 8 is the representation of the first and the last elements of the Galois Field generated by the generator polynomial of degree 9, X 9  +X 4  +1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the preferred embodiment, the calculation and checking of FCS is done on the OA&amp;M or AAL3/4 ATM cells. 
     FIG. 1 illustrates the ATM loopback tests based on the OA&amp;M cell protocols at Virtual Path level or Virtual Channel level on an OA&amp;M segment (single link) flow L1 or on a OAM end-to-end flow L2. The L1 flow is established between an ATM end point providing the ATM interface and the access point of the public network, noted as `public` in FIG. 1. This segment to be tested may cross an ATM private network comprising one or more ATM private switches. The L2 flow establish a test loop between two ATM end points located from one side to the other side of the ATM public network. 
     The generator polynomial provided by the standards organizations for CRC-10 calculation is non irreducible. It can be factorized as follows: 
     
         G(X)=X.sup.10 +X.sup.9 +X.sup.5 +X.sup.4 +X+1 
    
     
         G(X)=(X.sup.9 +X.sup.4 +1)(X+1) 
    
     The two polynomial factors are quite simple. In terms of implementation of Galois Field calculations, the complexity of the hardware or software is a direct function of the number of terms in the polynomial generator of the Galois Field; with the hardware implementation of the fast CRC calculation of the cited prior art, the number of terms is directly related to the number of n-way XOR gates. As a matter of fact, the degree nine polynomial factor has three terms as the degree 10 polynomial generator has 6 terms: their binary representation have respectively 3 and 6 bits set to 1. A significant simplification may be anticipated if one may use the degree 9 instead of the original degree 10 polynomial in the CRC-10 codes computation. It is noted that no simpler polynomial could possibly exist since all the irreducible polynomials have an odd number of ones equal or larger than 3. 
     Calculations performed in algebra of polynomials are similar those done with ordinary numbers in that if a number is divisible by 6 it is also divisible by 2 and 3. Similarly, with binary polynomials, if one polynomial is divisible by X 10  +X 9  +X 5  +X 4  +X+1, it is also divisible by X 9  +X 4  +1 and X+1. This means that elements of the Galois Field generated by the irreducible polynomial generator of degree 9 can be used to calculate the elements of the Galois Field generated by the polynomial generator of degree 10, i.e., the CRC-10. The solution will consist first in performing calculations made in the Galois Field generated by the irreducible polynomial generator of degree 9 than to use this first calculation to calculate FCS based on CRC-10. FIG. 8 illustrates the first and the last elements of the Galois field generated by the irreducible polynomial generator of degree 9 (of 2 9  -1=511 elements. 
     The ATM cells have a payload of 48 bytes, 384 bits. The first 374 first bits constitue the information field and the remaining 10 bits are used for storing the FCS of the payload based on CRC-10 codes. The method for checking the payload (48 bytes or 384 bits including the 10 bits of FCS) of a received OA&amp;M cell consists in dividing the polynomial representation of the payload 384 bit stream by the irreducible polynomial of degree 9, X 9  +X 4  +l, and dividing also the same payload 384 bit stream by the polynomial X+1. If both remainders in the divisions just described are zero then, the CRC-10 checking is correct. If not, the cell payload is in error and the cell is discarded; a `higher level protocol` than the adaptation layer handles the error recovery. However, dividing the polynomial representation of the cell payload bit stream by the polynomial X+1 is checking the parity of the cell payload. This is a known calculation already implemented, for the computation of the BIP-16 (Bit Interleave Parity) of the `performance monitoring` function of OA&amp;M cells. 
     The checking of cell is illustrated in FIG. 5. The cell payload 384 bit stream to be checked is read (500); it is noted that this payload includes the 10 bits FCS which has been calculated when the cell was sent. The parity of the payload is then calculated and stored (510). In parallel, when the cell is received, the polynomial division of the polynomial representation of the payload bit stream by the polynomial of degree 9, X 9  +X 4  +1, is performed and the remainder, R(X 9 ), is stored (520). The polynomial remainder, R(X 9 ), is of degree lesser than 9. When the cell is received the checking is started (530) at reception of the cell. The polynomial remainder of the division of the payload bit stream by the polynomial generator of degree 9, X 9  +X 4  +1 is tested (540), if it is not zero (all coefficients of the remainder polynomial are zero or all the bits are zero), the checking has failed (560). If not, the parity of the payload bit stream is tested (550). If the parity is odd, checking has failed. If the parity is even, checking passes. 
     The calculation of the cell FCS is illustrated also in FIG. 5. For starting FCS generation (530) before one cell is sent over the network, the parity of the 374 bits cell payload is calculated and stored (510). In parallel, the polynomial division of the polynomial representation of the payload bit stream by the polynomial of degree 9, X 9  +X 4  +1, is performed and the remainder, R(X 9 ), is stored (520). The 10 bits cell FCS field is filled with zeros (580). The parity of the payload is then tested (590); If odd, the polynomial representation of the FCS field in the cell payload is calculated (597) as the result of the addition of the remainder, R(X 9 ), of the division of the payload bit stream polynomial by the polynomial generator of degree 9, X 9  +X 4  +1 with X 9  : 
     
         FCS=R(X.sup.9)+X.sup.9 
    
     If the parity of the payload tested (590) is even, the FCS field in the cell payload is then (595) the remainder, R(X 9 ), of the division of the payload bit stream polynomial by the polynomial generator of degree 9, X 9  +X 4  +1: 
     
         FCS=R(X.sup.9) 
    
     The polynomial representation of the FCS code of the payload is of degree 9 and the corresponding FCS field in the cell payload comprising 10 bits. 
     FIG. 2 illustrates the logical blocks of the apparatus implementing the method of the invention to calculate the FCS of the payload. In this preferred embodiment, it is a byte wise process. The payload is read byte by byte in a register (200). Each new byte Bn+1 of the cell payload is entered in the Galois Field Multiplier/Adder (210). This Multiplier/Adder computes byte by byte the FCS of the byte stream based on the Galois-Field elements generated by the polynomial generator of degree 9, X 9  +X 4  +1 according to the process of the cited prior art. The Multiplier/Adder first multiplies the 9 bits FCS (Rn) calculated on the previous payload bytes, up to byte n, by α 8 , the 9nth element of the Galois field, and secondly, takes the remainder of the division of the resulting bit stream by the polynomial generator of degree 9. The resulting bit stream is then added to the Bn+1 8 bit stream corresponding to the new payload byte read, the result of the addition being stored in the current remainder register (220). The result stored is the FCS of the payload calculated up to byte n+1, Rn+1. This first blocks (200, 210, 220) are implementing the first step of the method (520). 
     As disclosed in the European application EP0614294 of the prior art, a hardware implementation of the Multiplier/Adder (210) of FIG. 2 is shown in FIG. 3. There are 9 XOR gates as the polynomial generator is of degree 9. Because the polynomial has three non zero terms the widest XOR gate is a 4-way XOR. The first entries of XOR gates are the R0, R1, . . . R8 binary values corresponding to the 9 bits of the Rn bit stream representing the FCS of the payload calculated up to byte n (Rn). The other entries to the XOR gates are the B0, B1, . . . B7 binary values corresponding to the 8 bits of the new byte Bn+1 of the payload. The XOR gate entries are combined in accordance with the calculation in the Galois Field generated by the polynomial generator of degree 9. FIG. 6 is an example of an actual hardware implementation of the 4-way XOR corresponding to the calculation of bit R5 in Rn+1 bit stream using 2-way XOR gates. The XOR gate entry combinations perform the multiplication and addition in the Galois Field generated by the polynomial generator of degree 9. The table of FIG. 7 provides the list of operations of the GF Multiplier/Adder 210 for each bit of the 9 bit FCS stream. 
     Coming back to FIG. 2, in the second hardware block (230) of the implementation is a 10 bits adder (240) having as inputs: the 9 bits FCS stream just computed (220), the parity of the payload (247), the bit stream corresponding to the generator polynomial of degree 9 and the 0 value for the most left bit added. The resulting 10 bits stream of the addition is stored in the FCS register (250). The hardware block (230) is for implementing the steps of the method (580, 590, 597, 595) described in FIG. 5. 
     FIG. 4 shows an implementaion of the polynomial of degree 9 addition of FIG. 2. To the content of the current rem register (220) are applied three 2 way XOR gates (240) at positions corresponding to the ones of the polynomial generator of degree 9. The first entry of the most left 2 way XOR gate (245) is always zero, the output thus reflecting the second input value: the parity (247) of the cell payload. The parity applied to all the XOR gates of the addition changes the corresponding bit value only if the parity is ODD. The resulting bits stream is stored in the 10 bit FCS register (250).