Abstract:
Provided is a pipelined folding analog-digital converter, the pipelined folding analog-digital converter comprising: a first sample-and-hold unit that samples and outputs a number of analog input voltages; a reference voltage generator that generates a number of reference voltages; a pre-amplifier that amplifies and outputs a number of values subtracting each reference voltage from the outputs of the first sample-and-hold unit, wherein an offset effect due to asymmetry of the amplifier is eliminated; a first folder that folds and outputs a number of outputs of the pre-amplifier; a second sample-and-hold unit that samples and outputs a number of outputs of the first folder; a second folder that folds and outputs a number of outputs of the second sample-and-hold unit; and a comparator that performs a comparison operation between the outputs of the pre-amplifier and the output values of the second folder to find a digital output value, whereby the offset caused by the device mismatch is removed, so that it is possible to realize a high-resolution analog-digital converter.

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention relates to an analog-digital converter. More specifically, the present invention relates to a pipelined folding analog-digital converter. 
   2. Discussion of Related Art 
   The conventional analog-digital converter is composed of a first quantizer that quantizes an analog voltage, a residue circuit that outputs a value subtracting an output of the first quantizer from the analog voltage, and a second quantizer that quantizes an output of the residue circuit. The first quantizer can be called a coarse quantizer, and the second quantizer can be called a fine quantizer. A folding analog-digital converter replaces the residue circuit of the conventional analog-digital converter with a folder, thereby improving performance, especially speed, of the analog-digital converter. A pipelined folding analog-digital converter introduces a pipeline scheme into the analog-digital converter having a number of folders, thereby improving the performance of the folding analog-digital converter. A pipeline folding scheme was disclosed on February, 2002 by Myung-Jun Choe in ‘IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 2’ entitled to ‘An 8-b 100-MSample/s CMOS Pipelined Folding ADC’ 
     FIG. 1  is a pipelined folding analog-digital converter according to the prior art. The pipelined folding analog-digital converter according to the prior art comprises a sample-and-hold unit  1 , a reference voltage generator  2 , a first folder  3 , a first track-and-hold unit  4 , a second folder  5 , a second track-and-hold unit  6 , first and second quantizers  7  and  8 , a third folder  9  and a digital decoder  10 . 
   The pipelined folding analog-digital converter according to the prior art processes a difference between an analog input voltage Vin and a reference voltage by amplifying it through the first and second folders  3  and  5 , so that there exists a problem that resolution that can be implemented is limited due to mismatch of devices within the first and second folders  3  and  5 . Further, to apply the pipeline scheme, it has the first and second track-and-holder units  4  and  6  between each stage. That is, it is a structure connecting a switch and a capacitor, which exist between each stage, in a parallel. Therefore, it should be designed such that the previous stage and the next stage have the same signal level, and when the signal level is not identical, signal linearity can be degraded. Further, there is a problem that it is difficult to decode lower bits when configuring multiple stages with a folder that has an odd number of folding factors. 
   SUMMARY OF THE INVENTION 
   The present invention is contrived to address the problems described above, and is directed to provide a high-speed and high-resolution pipelined folding analog-digital converter. 
   To overcome the foregoing problems, one aspect of the present invention provides an analog-digital converter comprising a first sample-and-hold unit that samples and outputs a number of analog input voltages; a reference voltage generator that generates a number of reference voltages; a pre-amplifier that amplifies and outputs a number of values subtracting each reference voltage from the outputs of the first sample-and-hold unit, and that eliminates an offset effect due to the asymmetry of the amplifier; a first folder that folds and outputs a number of outputs of the pre-amplifier; a second sample-and-hold unit that samples and outputs a number of outputs of the first folder; a second holder that folds and outputs a number of outputs of the second sample-and-hold unit; and a comparator that performs a comparison operation between the outputs of the pre-amplifier and the output values of the second folder to find a digital output value. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a pipelined folding analog-digital converter according to the prior art. 
       FIG. 2  is a pipelined folding analog-digital converter according to an embodiment of the present invention. 
       FIG. 3  is a circuit diagram of a pre-amplification circuit included in the pre-amplifier employed in the analog-digital converter of  FIG. 2 . 
       FIG. 4  is a diagram showing waveforms of φ 1, φ 2 and φ 3 signals of  FIG. 3 . 
       FIG. 5  is a circuit diagram of a folding circuit included in the first folder employed in the analog-digital converter of  FIG. 2 . 
       FIG. 6  is a diagram showing a waveform of φ 1D signal of  FIG. 5  together with a waveform of φ 1 signal. 
       FIG. 7  is a circuit diagram of a sample-and-hold circuit included in the second sample-and-hold unit employed in the analog-digital converter of  FIG. 2 . 
       FIG. 8  is a circuit diagram of a folding circuit included in the second folder employed in the analog-digital converter of  FIG. 2 . 
       FIG. 9  is a diagram showing a waveform of φ 2D signal of  FIG. 8  together with a waveform of φ 2 signal. 
       FIG. 10  is a circuit diagram of a sample-and-hold circuit included in the third sample-and-hold unit employed in the analog-digital converter of  FIG. 2 . 
       FIG. 11  is a circuit diagram of a subranging amplifier employed in the analog-digital converter of  FIG. 2 . 
       FIG. 12  is a circuit diagram showing an interpolator. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. 
     FIG. 2  is a block diagram of a pipelined folding analog-digital converter according to an embodiment of the present invention. In  FIG. 2 , the analog-digital converter comprises a first sample-and-hold unit  11 , a reference voltage generator  12 , a pre-amplifier  13 , a first folder  14 , a second sample-and-hold unit  15 , a second folder  16 , a third sample-and-hold unit  17 , a subranging amplifier  18 , a comparator  19  and a digital error corrector  20 . 
   The first sample-and-hold unit  11  samples and outputs differential analog input voltages Vin+, Vin−. The reference voltage generator  12  performs interpolation for input reference voltages Vref+ and Vref− to generate differential reference voltages Vr 1 +, Vr 1 −, Vr 2 +, Vr 2 −, . . . Vrn+ and Vrn−. The pre-amplifier  13  amplifies and outputs values that subtract each differential reference voltages Vrk+ and Vrk−, where k is natural number equal to or less than n, from the sampled differential analog input voltages V 1 s+ and V 1 s−. The first folder  14  and the second folder  16  fold and output a number of outputs of the pre-amplifier  13  and a number of outputs of the second sample-and-hold unit  15 , respectively. The second sample-and-hold unit  15  and the third sample-and-hold unit  17  sample and output a number of outputs of the first folder  14  and the second folder  16 , respectively. The subranging amplifier  18  amplifies and outputs a number of outputs of the third sample-and-hold unit  17 . The comparator  19  receives positive outputs Va 1 +, Va 2 +, . . . , and Van+ of the pre-amplifier  13  to perform a comparison operation for each input, and outputs a value MSB that sums the number of ‘1’. Further, after receiving positive outputs of the second folder  16  to perform a comparison operation for each input, it outputs a value MLSB that sums the number of ‘1’. Further, after receiving positive outputs of the subranging amplifier  18  to perform a comparison operation for each input, it outputs a value LSB that sums the number of ‘1’. Here, what is meant by “comparison operation” is that when the input value is larger than the threshold value, one of ‘1’ and ‘0’ is outputted, and when the input value is smaller than the threshold value, the remaining one of ‘1’ and ‘0’ is outputted. The digital error corrector  20  receives an output signal of the comparator to check whether or not there exists an error in the digital value, and if there is an error, performs correction of the error. 
   The analog-digital converter according to an embodiment of the present invention amplifies values subtracting each reference voltage from the sampled differential analog input voltages V 1 s+ and V 1 s−, and then passes the values through the comparator  19  to form the upper bits MSB. Twice folded outputs of the pre-amplifier  13  are passed through the comparator  19  to form the intermediate bits MLSB. The outputs of the second folder  16  are amplified and then passed through the comparator  19  to form the lower bits LSB. The digital error corrector  20  receiving the MSB, the MLSB and the LSB corrects an error and outputs the resultant N bit digital signal. 
   Each stage samples the signals of the previous stage through capacitors connected in series, thereby allowing a pipeline scheme to be applied for a high-speed operation while making each stage isolated with each other in view of a direct current. Therefore, the levels between the output voltages of each stage and the input voltages of the next stage can be designed differently so that flexibility in designing a circuit is enhanced and a lager linear area can be obtained. 
   The pre-amplifier employed in the analog-digital converter of  FIG. 2  will now be described with reference to  FIGS. 3 and 4 . 
     FIG. 3  is a circuit diagram of a pre-amplification circuit included in the pre-amplifier employed in the analog-digital converter of  FIG. 2 . The pre-amplifier  13  includes a number of pre-amplification circuits. In  FIG. 3 , the pre-amplification circuit comprises an amplifier  21 , an input unit  22 , an output unit  23  and a reset unit  24 . 
   The amplifier  21  amplifies voltages of differential input stages to output the amplified voltages to differential output stages. The input unit  22  applies a common voltage to the differential input stages of the amplifier  21  during a period when φ 1 signal is ‘1’, and applies a voltage subtraction-operation performed between a sampled positive analog input voltage V 1 s+ and a positive reference voltage Vrk+, where k is natural number equal to or less than n, and a voltage subtraction-operation performed between a sampled negative analog input voltage V 1 s− and a negative reference voltage Vrk− to the differential input stages of the amplifier  21  during a period when φ 2 signal is ‘1’. The output unit  23  stores the offset voltage, caused by the asymmetry of the amplifier  21 , during the period when the φ 1 signal is ‘1’, and outputs a value subtracting the offset voltage, stored during the period when φ 1 the signal is ‘1’, from the differential output of the amplifier  21  during the period when the φ 2 signal is ‘1’. The reset unit  24  interconnects the differential output stages of the amplifier  21  during a period when φ 3 signal is ‘1’. 
   From another point of view, the pre-amplification circuit includes an amplifier  21  and four capacitors CIN 1 , CIN 2 , CO 1  and CO 2 , and seven switches SW 1  to SW 7  for eliminating the offset. 
   The first switch SW 1  turns on, when the φ 1 signal is ‘1’, and connects the sampled positive analog input voltage V 1 s+ to a first terminal of the first capacitor CIN 1 . The second switch SW 2  turns on, when φ 2 signal is ‘1’, and connects the positive reference voltage Vrk+ to a first terminal of the first capacitor CIN 1 . The third switch SW 3  turns on, when the φ 2 signal is ‘1’, and connects the negative reference voltage Vrk−to a first terminal of the second capacitor CIN 2 . The fourth switch SW 4  turns on, when the φ 1 signal is ‘1’, and connects the sampled negative analog input voltage V 1 s− to a first terminal of the second capacitor CIN 2 . The second terminals of the first and second capacitors CIN 1  and CIN 2  are each connected to the differential input stages of the amplifier  21 . The fifth switch SW 5  turns on, when the φ 1 signal is ‘1’, and connects a common voltage CM to the second terminal of the first capacitor CIN 1  and the second terminal of the second capacitor CIN 2 . The amplifier  21  amplifies and outputs the differential input. The amplifier  21  includes a current source Is, two NMOS transistors MN 1  and MN 2  and two loads RL 1  and RL 2 . For the first and second transistors MN 1  and MN 2 , gates are each connected to the differential input stages of the amplifier  21 , sources are each connected to a first terminal of the current source Is, and drains are each connected to the differential output stages of the amplifier  21 . A second terminal of the current source Is is connected to the ground, first terminals of the first and second loads RL 1  and RL 2  are connected to the power supply voltage VDD, and their second terminals are connected to the differential output stages of the amplifier  21 . The sixth switch SW 6  turns on, when the φ 3 signal is ‘1’, and interconnects the differential output stages of the amplifier  21 . First terminals of the third and fourth capacitors C 01  and C 02  are each connected to the differential output stages, and their second terminals are connected to the output stages of the pre-amplification circuit. The seventh switch SW 7  turns on, when the φ 1 signal is ‘1’, and connects the common voltage CM to the second terminal of the third capacitor CO 1  and the second terminal of the fourth capacitor C 02 . 
     FIG. 4  shows waveforms of the φ 1, φ 2 and φ 3 signals of  FIG. 3 . In  FIG. 3 , the φ 1 and φ 2 signals become ‘1’ alternatively, and there is no period that both signals are ‘1’ at the same time. The φ 3 signal is a signal that temporarily becomes ‘1’ in a front part of a period when the φ 1 is ‘1’, and the remaining period is ‘0’. 
   During the period when the φ 1 signal is ‘1’, in the first capacitor CIN 1 , the first terminal is connected to the sampled positive analog input voltage V 1 s+, and the second terminal is connected to the common voltage CM. Therefore, the voltage of CM−V 1 s+ is applied between the second terminal and the first terminal of the first capacitor CIN 1 . In the same manner, the voltage of CM−V 1 s− is applied between the second terminal and the first terminal of the second capacitor CIN 2 . Since all of the differential input stages of the amplifier  21  are connected to the common voltage CM, theoretically, all of the differential output stages of the amplifier  21  should have the same voltage. However, due to the asymmetry between the first and second NMOS transistors NM 1  and NM 2  and the first and second loads RL 1  and RL 2 , an offset voltage Δ V is generated. For this reason, the voltage of the first terminal of the fourth capacitor CO 2  is higher than that of the third capacitor C 01  by the offset voltage Δ V, thus the voltage applied between the second terminal and the first terminal of the fourth capacitor C 02  has a lower voltage by the offset voltage Δ V as compared with a voltage applied between the second terminal and the first terminal of the third capacitor CO 1 . 
   During the period when the φ 2 signal is ‘1’, the first terminal of the first capacitor CIN 1  is connected to the positive reference voltage Vrk+, and the first terminal of the second capacitor CIN 2  is connected to the negative reference voltage Vrk−. For this reason, Vrk+−V 1 s++CM and Vrk−−V 1 s−+CM are each applied to the differential input stages of the amplifier  21 . Ideally, the amplifier  21  amplifies and outputs a value subtracting one input from the other input of the differential input stages. However, due to the asymmetry as described above, in the first terminal of the fourth capacitor C 02 , a voltage is applied higher than the ideal output of the amplifier by the offset voltage Δ V. However, as described above, during the period when the φ 1 is ‘1’, the voltage applied between the first terminal and the second terminal of the fourth capacitor C 02  has a lower voltage by the offset voltage Δ V, so that during the period when the φ 2 signal is ‘1’, a value for which the offset voltage Δ V is cancelled is outputted to the second terminal of the fourth capacitor. Therefore, differential output voltages Vak+ and Vak− of the pre-amplification circuit outputted during the period when the φ 2 signal is ‘1’ are not affected by the offset voltage Δ V. 
   During a period when the φ 3 signal is ‘1’, the sixth switch SW 6  becomes ‘1’, serving to reset the output stages of the amplifier  21  rapidly. 
   The pre-amplification circuit effectively cancels the offset generated at the pre-amplification circuit itself, so that the amplification ratio of the pre-amplification circuit is increased, thereby optimizing the effect of the offset generated at the subsequent folder. 
   A first folder employed in the analog-digital converter of  FIG. 2  will now be described with reference to  FIGS. 5 and 6 . 
     FIG. 5  is a circuit diagram of a folding circuit included in the first folder used for the analog-digital converter of  FIG. 2 . The first folder  14  includes a number of folding circuits. 
   In  FIG. 5 , the folding circuit has three differential inputs, that is, the folding factor is 3. Generally, the folding circuit has an odd number of differential inputs. The folding circuit has three current switches  25 ,  26  and  27 , two loads RL and one switch SW. Each current switch  25 ,  26  or  27  has two NMOS transistors MN and one current source Iss, for converting and outputting the differential input voltage into the differential current. The output stages of the current switches  25 ,  26  and  27  are connected to the differential output stages of the folding circuit, alternatively. That is, for the first current switch  25 , a positive output is connected to a positive output stage of the folding circuit and a negative output is connected to a negative output stage of the folding circuit, while for the second current switch  26 , a positive output is connected to a negative output stage of the folding circuit and a negative output is connected to a positive output stage of the folding circuit, and for the third current switch  27 , a positive output is connected to a positive output stage of the folding circuit and a negative output is connected to a negative output stage of the folding circuit. 
     FIG. 6  is a diagram showing a waveform of the φ 1D signal of  FIG. 5  together with a waveform of the φ 1 signal.  FIG. 6  shows that the φ 1D signal has a period of ‘1’ longer than that of φ 1 signal. 
   While resetting an output signal of the folding circuit during a period when the φ 1D signal is ‘1’, an output signal of the pre-amplifier is folded and outputted during a period when the φ 2 is ‘1’. The reset time of the folder is set to be slightly longer than the period when the φ 1 signal is ‘1’, thereby avoiding backward flows due to the previous signal stored in the next stage during the period when the φ 2 signal is ‘1’, and facilitating the output signal to be fixed more rapidly. 
   The second sample-and-hold unit employed in the analog-digital converter of  FIG. 2  will now be described with reference to  FIG. 7 . 
     FIG. 7  is a circuit diagram of a sample-and-hold circuit included in the second sample-and-hold unit employed in the analog-digital converter of  FIG. 2 . The second sample-and-hold unit  15  includes a number of sample-and-hold circuits. For each sample-and-hold circuit, a voltage subtracting the input voltage Vin from a common voltage CM 2 , that is, CM 2 −Vin is applied between the second terminal and the first terminal of the capacitor CIN during the period when the φ 2 signal is ‘1’, and then a first common voltage CM 1  is applied to a first terminal of the capacitor CIN during the period when the φ 1 signal is ‘1’, thereby making CM 1 +CM 2 −Vin applied to the output stages during the period when the φ 1 signal is ‘I’. With this operation, the sample-and-hold circuit samples and outputs the output signals of the first folder  14 . 
   The second folder employed in the analog-digital converter of  FIG. 2  will now be described with reference to  FIGS. 8 and 9 . 
     FIG. 8  is a circuit diagram of a second folding circuit included in the second folder employed in the analog-digital converter of  FIG. 2 . The second folder  16  includes a number of folding circuits.  FIG. 9  is a diagram showing a waveform of the φ 2D signal of  FIG. 8  together with a waveform of the φ 2 signal. The folding circuit of the second folder  16  has no difference in the configuration compared with the folding circuit of the first folder  14 , except for the timing difference. That is, for the folding circuit of the second folder  16 , while the output signals of the folding circuit are reset during a period when the φ 2D signal is ‘1’, the output signals of the second sample-and-hold unit  15  are folded and outputted during the period when the φ 1 signal is ‘1’. 
   The third sample-and-hold unit employed in the analog-digital converter of  FIG. 2  will now be described with reference to  FIG. 10 . 
     FIG. 10  is a circuit diagram of a sample-and-hold circuit included in the third sample-and-hold unit employed in the analog-digital converter of  FIG. 2 . The third sample-and-hold unit  17  includes a number of sample-and-hold circuits. For each sample-and-hold circuit, a voltage subtracting the input voltage Vin from the common voltage CM 2 , that is, CM 2 −Vin is applied between the second terminal and the first terminal of the capacitor CIN during the period when the φ 1 signal is ‘1, and then the first common voltage CM 1  is applied to the first terminal of the capacitor CIN during the period when the φ 2 signal is ‘1’, thereby making CM 1 +CM 2 −Vin applied to the output stages during the period when the φ 2 signal is ‘1’. With this operation, the sample-and-hold circuit samples and outputs the output signals of the second folder  16 . 
   The subranging amplifier employed in the analog-digital converter of  FIG. 2  will now be described with reference to  FIG. 11 . 
     FIG. 11  is a circuit diagram of the subranging amplifier employed in the analog-digital converter of  FIG. 2 . In  FIG. 11 , the subranging amplifier  18  includes first to fifth amplifiers  28  to  32  and an interpolator  33 . 
   The third amplifier  30  receives an output of the third sample-and-hold unit  17  determined by the output value of the second folder  16 . The second and fourth amplifiers  29  and  31  receive the upper level and the lower level of the input of the third amplifier  30 , respectively. The first and fifth amplifiers  28  and  32  receive the upper level of the second amplifier  29  and the lower level of the input of the fourth amplifier  31 , respectively. The interpolator  33  interpolates and outputs the output voltages of the first to fifth amplifiers  28  to  32  with resistors. 
   At this time, for the first and fifth amplifies  28  and  32 , that is, both ends of the subranging amplifier  18 , the resolution can be improved by inverting the output signals of the first and fifth amplifiers  28  and  32  to connect with resistors to have the same output condition with the other second, third, and fourth amplifiers  29 ,  30  and  31 . For the differential configuration, the same effect can be achieved by crossing the differential outputs of two amplifiers. 
   The interpolator, which can be used for the output stages of the pre-amplifier  13 , the first folder  14  and the second folder  16  employed in the analog-digital converter of  FIG. 2 , will now be described with reference to  FIG. 12 .  FIG. 12  is a circuit diagram showing the interpolator. The interpolator, having a number of resistors connect in series, interpolates and outputs the input signals. The interpolator can be used in connection with the output stages of the pre-amplifier  13 , the first folder  14  and the second folder  16 . 
   Although the preferred embodiments of the present invention have been described, it should be noted that these embodiments are just illustrative, and not restrictive. Further, those skilled in the art will appreciate that various modifications can be made without departing from the scope of the present invention. 
   The pipelined folding analog-digital converter according to the present invention eliminates the offset caused by the asymmetry of the amplifier, thereby having a merit that a high-resolution analog-digital converter can be implemented. 
   Further, for the pipelined folding analog-digital converter according to the present invention, each folder is connected to the sample-and-hold unit, thereby having a merit that it can be applied even when the signal level of each folder is not equal. 
   Further, the pipelined folding analog-digital converter according to the present invention comprises the subranging amplifier, resulting in a high-resolution.