Abstract:
An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

Description:
RELATED APPLICATION(S) 
       [0001]    This application is a continuation in part of and claims priority to International Application No. PCT/US2005/024137 under 35 U.S.C. §120, which designated the United States and was filed on Jul. 6, 2005, published in English, which claims the benefit of U.S. Provisional Application No. 60/585,610, filed on Jul. 6, 2004. The entire teachings of the above applications are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    Several different types of circuits require the generation of multiple analog output voltages in accordance with digital input signals. In such circuits it has been customary to implement this function using a separate digital to analog converter for each required output voltage. 
         [0003]    This approach is adequate when only a few analog voltages must be generated. However, certain types of circuits, such as charge to digital converters, may require generation of many such analog voltages. Even if integrated circuits are used to implement such circuits, the voltage generating function can occupy much space in a design. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention is an integrated circuit memory cell and voltage ladder design to implement a compact array of digital to analog converters. The invention, in effect, provides an analog Voltage Random Access Memory (VRAM). 
         [0005]    The VRAM allows storing a digital value in a memory location. A resistor ladder network and a compact array of switchable memory cells provide the set of output reference voltages. The compact array of switchable memory cells are arranged to store digital bits, which are individually addressable by row and column address decoders, in much the same way as a Static Random Access Memory (SRAM) memory circuit. However, each stored bit in a memory cell is also connected to control the state of a corresponding switch. In a preferred embodiment, each switch is coupled to a pre-selected point in the resistor ladder network. 
         [0006]    By writing the bits in the memory cells accordingly, the switches are thereby controlled to determine which of many possible resistances in the ladder network will be selected to produce one or more output voltages. 
         [0007]    The ladder can include a set of resistors connected in simple series to provide a set of selectable, coarse resistances. 
         [0008]    However, in a preferred embodiment, one or more fine resistance steps can also be provided by one or more resistors arranged in parallel with one or more of the coarse resistors. 
         [0009]    The VRAM thus provides a large number of adjustable analog voltages under control of digital inputs. This function is provided in a compact form factor that is a form factor that can be as almost as compact as standard random access memory circuitry. The equivalent functionality to a large number of latched digital analog converters is provided by requiring much less physical area and power consumption as a result. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. 
           [0011]      FIG. 1  is a block diagram of a circuit function, such as a charge to digital converter, that may use a Voltage Random Access Memory (VRAM) according to the present invention. 
           [0012]      FIG. 2A  and  FIG. 2B  show a prior art arrangement for a Static Random Access Memory (SRAM). 
           [0013]      FIG. 3  shows an array of VRAM cells and a resistor ladder arranged according to the present invention. 
           [0014]      FIG. 4  is a more detailed view of a VRAM cell, showing the memory bit storage circuit and the associated switch. 
           [0015]      FIG. 5  shows one specific possible arrangement for the resistor ladder of  FIG. 3  with both coarse and fine step resistors. 
           [0016]      FIG. 6  is a chart listing the output voltages that can be selected with the resistor ladder of  FIG. 5 . 
           [0017]      FIG. 7  illustrates another implementation of a VRAM cell providing a coarse and fine output voltage, to increase output resolution and improve noise immunity. 
           [0018]      FIG. 8  is a VRAM receiver, that may be scattered throughout an IC design, that uses a difference amplifier to produce and output voltage that is proportional to a difference between a coarse voltage and a fine voltage. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    A description of preferred embodiments of the invention follows. 
         [0020]      FIG. 1  is a block diagram of a device  10  that may use a Voltage Random Access Memory (VRAM)  20  according to the present invention. The illustrated device  10  is arranged as a Charge to Digital Converter (QDC). It should be understood, however, that the VRAM  20  can be used in any other application circuit where multiple analog voltages must be produced in parallel from digital inputs. 
         [0021]    This particular QDC  10  is a so-called successive approximation type converter that uses a number of charge storage stages arranged as a serial pipeline register. In the illustrated circuit there are actually two pipelines  24 - p ,  24 - m  (a “plus” pipeline and a “minus” pipeline”) that carry charges as complimentary charge pairs. A reference charge generator  22 - p ,  22 - m , input sampler  23 - p ,  23 - m , and digital to analog converter (DAC)  27 - p ,  27 - m  are associated with each serial pipeline register  24 - p ,  24 - m . A reference charge generator and a charge splitter at each stage generate reference signals which are then optionally added to the charge as it travels down the pipeline. An array of comparators  25  produce the conversion result as a series of digital bits. The QDC  10  is implemented similar to the one described in U.S. Pat. No. 5,559,007 issued to Paul. 
         [0022]    Of particular interest to the present invention is the VRAM  20  that can be used to generate a number of offset and adjustment voltage levels used by various components of QDC  10 . The VRAM  20  can be arranged to provide coarse output  28  or fine outputs  29 , or a combination thereof, in a manner that will be described in more detail below. The resulting reference voltages produced by VRAM  20 , for example, are used to calibrate the DACs  27 , to provide biasing points for splitter circuits, to provide reference charges to the comparators  25 , or for other purposes. 
         [0023]    The approach for implementing the digital bit storage portion of the VRAM  20  is similar to a Static Random Access Memory (SRAM) type circuits. As shown in  FIG. 2A , as is well known in the art, an SRAM consist of a row address decoder  30 , a column address decoder  32 , and associated drivers  31 ,  33 , to address an array  35  of memory cells  36 . The row  30  and column  32  decoders provide access to a particular cell  36  to allow a read/write circuit  38  to either read data to the cell  36  through a “data in” connection or read data from the cell  36  through a “data out” connection. 
         [0024]    A detailed view of a typical Complementary Metal Oxide Semiconductor (CMOS) SRAM cell  36  is shown in  FIG. 2B . The row address enable line (from the left hand side of the figure) and column address enable lines (from the bottom of the figure) are input to the cell  36 . The cell  36  consists of an input gate  41  and output gate  42 , together with a circuit capable of storing a single bit of information, such as the illustrated pair of cross-coupled inverters  43   a ,  43   b . The cell is enabled for reading or writing by strobing its associated row and column select lines. 
         [0025]      FIG. 3  shows a more detailed view of a VRAM  20  according to the present invention. The VRAM includes a resistor array  50  and a compacy storage array  46  of memory cells  46 . The compact storage array in the VRAM  20  is generally similar to that in an SRAM, to the extent that it includes a array  45  of memory cells  46 . However, each memory cell  46  in the VRAM contains not only a storage bit portion  47  but also a voltage switch  48 . 
         [0026]    Each voltage or “cross point” switch  48  has an input terminal that is coupled to a respective portion of the resister ladder  50 . The resistor ladder  50  itself consists of a number of resistances  51 - 1 ,  51 - 2 , . . .  51 - n  connected between a high voltage reference V h  and a low voltage reference V l . Although resistances  51 - 1 ,  51 - 2 , . . .  51 - n  are shown in a series configuration in  FIG. 3 , it should be understood that is only one possible configuration, and that other configurations of resistors in parallel and series are possible. 
         [0027]    The data bits stored in the memory cells  46  control the state of the switches  48 . This permits any connection of resistances in the ladder  50  to be used in providing the output on a respective column line  60 . In other words, a selected voltage level between Vh and Vl can be provided at any output  60  by activating the corresponding switch  48 , as determined by the data stored in the corresponding cell  46 . 
         [0028]    The memory cells are preferably arranged in groups; there typically will be multiple memory cells  46  associated with each particular node  52  in the resistor ladder. 
         [0029]    Furthermore, the output side of the n switches  48  at each step of the ladder are connected together to provide a respective one of the outputs  60 - 1 ,  60 - 2 , . . .  60 - m  on a respective VRAM output column line  62 - 1 ,  62 - 2 , . . .  62 - m  (OUT 1 , OUT 2 , . . . , OUT m ). For example, a representative column line  62 - 2  connects the output of switches  48 - 2 - 1 ,  48 - 2 - 2 , . . . ,  48 - 2 - n  to produce output OUT 2 . The voltage provided at a given output column line  62 - k  thus depends upon which one of the corresponding switches  48 - k - 1 ,  48 - k - 2 , . . . ,  48 - k - n  are closed to connect to a point in ladder  50 . Thus, only a single voltage is picked from ladder  50  for each output line  62 . 
         [0030]    The available accuracy of this technique is limited only by the number of resistors  51  in the ladder  50 . In one preferred embodiment there are thirty-two (32) such resistors  51 , as will be discussed in connection with  FIG. 5 . 
         [0031]      FIG. 4  shows a more detailed view of one of the cells  46  of the VRAM  20 . The latch or storage bit  47  portion of the VRAM is used to store a data bit in much the same way as a memory cell in the SRAM. Not shown in  FIG. 4 , although present, are the row and address decoder circuits that allow access to each cell for addressing and storing information in each latch  47 . These circuits are the same as for the SRAM. 
         [0032]    In addition each cell  46  also has a switch  48 , which corresponds to the switches  48  shown in  FIG. 3  that are coupled to steps of the ladder  50 . Thus by adding the a switch  48  to each of the basic memory cells  46 , there is provided a compact storage array which can be used to store information needed to produce a large number of selectable analog output voltages. 
         [0033]      FIG. 5  illustrates that the ladder  50  may not consist of coarse resistances but may also have one or more fine resistor steps. The fine resistor steps allow for more precise control of the output voltages, by providing additional voltage steps between selected coarse steps. For example, a number of fine steps may be provided in the center portion of the ladder. As will be explained below, a different between a coarse and fine voltage can then be taken to give a fine voltage result. 
         [0034]    More particularly, resistor ladder  50  consists of a coarse ladder portion  110  and a fine ladder portion  120 . The coarse ladder portion  110  is provided by sixteen resistors  51  connected in series. Fourteen of the resistances are equal and have a resistance value, R, of 100 ohms. Two of the resistances in the coarse ladder are equal to 2 R ohms; the purpose of this is to accommodate the fine ladder portion, as will be understood shortly. 
         [0035]    The high reference voltage V h  represents the largest possible selectable output voltage; V l  represents the smallest possible selected output voltage. The coarse ladder of  FIG. 5  thus provides 16 possible output voltages VC 0 , VC 1 , . . . VC 15  spaced between V h  and V l . 
         [0036]    The fine ladder portion  120  consists of 16 additional resistances, also arranged in series. The value of each of these fine resistances is R/4, or 25 ohms. These resistances provide 16 additional fine gradations. In the illustrated example, fine voltages VF 0 , VF 1 , . . . VF 15  are provided ranging from VC 7  to VC 9 . 
         [0037]    A node just below VC 7  in the coarse ladder is connected to node VC 7  in the fine ladder; the node just below VC 8  is connected to a node below VF 8  in the middle of the fine ladder, and the node just below VC 9  is connected to the node above VF 15 . Recall that the resistances in the coarse ladder  110  between VC 7  and VC 8  and between VC 8  and VC 9  were 2 R (200 ohms). Thus, the arrangement of  FIG. 5  provides 16 equally spaced fine gradation steps between VC 7  and VC 9 . 
         [0038]    The resistors values 2 R and R/4 can be provided by two resistance devices, such as FETs in series, and four resistances R in parallel, respectively. This allows the very same device, having the same geometry, to be used to implement all components of each of the coarse and fine arrays. That same device thus exhibits the same behavior over a wide range of operating conditions, resulting in greater output voltage accuracy. 
         [0039]    In the particular embodiment illustrated in  FIG. 5 , sixteen (16) resistance steps in the coarse ladder portion  110  provide 4 bits of output resolution. The fine ladder portion  120 , also consisting of 16 resistance steps, spans two of the coarse steps in the middle of the range. This provides a total of 7 bits of effective resolution in the middle portion. It should be understood that in other embodiments, the arrangement of resistors could be different. For example, if the 16 fine steps were to span only one of the coarse steps, the fine output resolution would be 8 bits. A embodiment where t least 2 coarse steps are spanned assures that there are no gaps in the digital code ranges. 
         [0040]      FIG. 6  is a table listing one possible range of the thirty-two (32) output voltages V 0 , V 1 , . . . , V 31  available with the resistor ladder shown in  FIG. 5 . Here V h , or the top of the ladder reference is set to 1.675 volts, and V l  or the bottom of the ladder is set to 1.3 volts. The coarse portion  110  of the ladder  50  produces voltages V 0  through V 7  and V 24  through V 31 , with coarse steps of 0.025 volts. The fine ladder  120  produces voltages from V 8  through V 23 , with fine steps of 0.003125 volts. The ladder thus provides fine level adjustments in the middle of the V h  to V l  range centered around 1.5 volts (i.e., at V 16 ). 
         [0041]      FIG. 7  shows an optional embodiment of the invention where cell outputs are combined. This permits generation of a voltage that is a difference between a two of the output voltages OUT 1 , OUT 2 , . . . , OUT m . One of these output voltages, V coarse, is the output OUT c  taken from a selected one of the VRAM cells  47 - c  that is connected to one of the nodes in the coarse portion  110  of the ladder  50 . Another one of the output voltages, V fine, is the output OUT f , provided by a VRAM cell  47 - f  which is connected to select one of the nodes in the fine portion  120  of the ladder  50 . 
         [0042]    The V coarse and V fine output voltages are then fed to an output circuit  150  as shown in  FIG. 8 . The output circuit  150  is a pair of transistors  151 ,  152  and current source  153  to ground  155  arranged as a difference amplifier. The loads  154  convert the current difference to a voltage difference at the output  68 . 
         [0043]    The resulting output  68  is thus proportional to V coarse minus V fine. This permits generation of a very small but still very accurate output voltage  68 , such as 0.003125 volts, by selecting V coarse input from one of the cells to be V 16  and the V fine input from another cell at V 17 . The availability of such small voltages under program control can greatly improve the performance of circuits such as QDC shown in  FIG. 1 . 
         [0044]    While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.