Abstract:
In one embodiment, an optoelectronic device is provided having a pin photo diode including a semi-insulating substrate or layer, with a patterned implant region of a first dopant type. The pin photo diode includes an upper layer having semiconductor material with a second dopant type. An intermediate layer is provided having a substantially intrinsic semiconductor material. An upper layer contact is provided having a portion with a generally circular interior facing edge. The implant region has a first portion having an outer periphery substantially nonoverlapping with the interior facing edge of the upper layer contact. The implant region includes a contact portion located beyond the upper layer contact. A connecting portion couples the first portion and the contact portion of the implant region. In one embodiment, the device includes a heterojunction bipolar transistor coupled to the pin photo diode. The transistor may have a patterned implant region in the semi-insulating substrate or layer comprising the first dopant type.

Description:
ORIGIN OF INVENTION 
   The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for the terms of contract number TFAST AFRL F33615-02-C-11268 awarded by DARPA. 

   BACKGROUND 
     FIG. 1  shows a cross sectional view of a simplified illustration of one example of a conventional pin photo diode  100 . The pin photo diode  100  is capable of use in a optoelectric integrated circuit or OEIC (not shown). The OEIC may further include other devices such as a heterojunction bipolar transistor or HBT (not shown), for example. 
   The pin photo diode  100  is formed on a substrate  110 , which may be for example InP. On the substrate  110  is an isolation mesa  120  may be doped with n+ dopant to form a subcollector. Formations of the isolation mesa  120  functions to electrically isolate the photo diode from adjacent devices (not shown) on the OEIC (not shown). To provide electrical connection, collector metal  130  is located on the isolation mesa  120 . An intrinsic or lightly doped n− layer  140  is located between the isolation mesa  120  and a base layer  150 , which may be doped with p+ dopant. A ring, or partial ring, of base metal  160  provides an opening for light to pass through to the intrinsic layer  140 , and provides electrical connection with the base layer  150 . 
   The isolation mesa  120  typically includes n+ type dopant in a semiconductor material, while the base includes a p+ type dopant in semiconductor material. The p type-intrinsic-n type or p-i-n configuration may be fabricated using masking and etching techniques known in the art. 
   With pin photo diodes  100 , as with HBT transistors, base-to-collector capacitance limits the bandwidth of a device. A trade-off exists between series resistance and capacitance of the device. For low series resistance you need a large collector contact  130  and a large base contact  160 . A large subcollector (isolation mesa  120 )-to-base  150  overlap, however, increases the capacitance of the device. Ideally a low RC time constant is desired. This is particularly desirable in high performance devices operating at high frequency. Thus, what is needed is a device with low capacitance and low resistance. 
   SUMMARY 
   In one embodiment, an optoelectronic device is provided which has a pin photo diode including a semi-insulating substrate or layer having a patterned implant region of a first dopant type. For example, the semi-insulating substrate or layer may be indium phosphide and the first dopant type may be n+. The pin photo diode includes an upper layer having semiconductor material with a second dopant type. For example, the second dopant type may be p+. An intermediate layer having a substantially intrinsic semiconductor material is located between the implant region and the upper layer. 
   An upper layer contact having a portion with a generally circular interior facing edge. The patterned implant region has a first portion having an outer periphery substantially nonoverlapping with the interior facing edge of the upper layer contact. The patterned implant region includes a contact portion located beyond the upper layer contact. A connecting portion couples the first portion and the contact portion of the patterned implant region. 
   In one embodiment, the optoelectronic device includes a transistor coupled to the pin photo diode, such as a heterojunction bipolar transistor. The transistor has a patterned implant region of the first dopant type in the semi-insulating substrate or layer. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will be better understood with regard to the following description, appended claims, and accompanying drawings where: 
       FIG. 1  shows a cross sectional view of a simplified illustration of a conventional pin photo diode. 
       FIG. 2  is a simplified illustration of a cross sectional view, along the  2 - 2  line of  FIG. 4 , of a pin photo diode in accordance with one embodiment of the present invention. 
       FIG. 3  shows a cross sectional view, along the  3 - 3  line of  FIG. 4 , of a pin photo diode in accordance with one embodiment of the present invention. 
       FIG. 4  shows a top view of a pin photo diode in accordance with one embodiment of the present invention. 
       FIG. 4A  shows a top view of the implant region of the pin photo diode of  FIG. 4 . 
       FIG. 4B  shows a top view of the base layer of the pin photo diode  FIG. 4 . 
       FIG. 4C  shows a top view of the base metal of the pin photo diode  FIG. 4 . 
       FIG. 5  is a simplified diagram of an optoelectric integrated circuit shown in cross sectional side view in accordance with one embodiment of the present invention. 
       FIG. 6  is a top view of a possible optoelectric integrated circuit in accordance with one embodiment of the present invention. 
   

   DESCRIPTION 
     FIG. 2  is a cross sectional view, along the  2 - 2  line of  FIG. 4  of a simplified illustration (without collector contact  230 , vias  336  and interconnect metal  338  shown in  FIG. 4 ) of a pin photo diode  200  in accordance with one embodiment of the present invention. An n+ doped implant region  220  is formed in semi-insulating substrate  210  or in a semi-insulating layer over a substrate, for example in a semi-insulating InP substrate or semi-insulating InP layer above a substrate. 
   The implant region  220  may be formed with a patterned ion implant, followed by an activation process, such as a rapid thermal anneal activation, CVD chamber annealing, or other known activation techniques for forming a patterned doped region. Various ion implant species may be utilized such as, for example, Si, Si/Se, or Si/P can be used for n-type implant. Dopant concentrations after activation/annealing may be on the order of about 10 18 /cm 3  to about 10 19 /cm 3 , for example. Other known ion implant and co-implant species, and concentrations, are possible. 
   An intrinsic layer  240  is positioned over the implant region  220 . The intrinsic layer  240  may include or be a lightly doped n− layer in some embodiments. In this embodiment, in addition to a portion of the intrinsic layer  240  being located on the implant region  220 , a portion of the intrinsic layer  240  is located directly on the semi-insulating layer or substrate  210 . A p+ base layer  250  with an overlying base metal  260  is located over the intrinsic layer  240 . 
   Referring to  FIGS. 2 and 4A , to limit extrinsic base-to-collector capacitance, the implant region  220 , shown in top view in  FIG. 4A , has a circular portion  220   r  which is sized and positioned so that the periphery of the circular portion  220   a , does not extend beyond the base metal layer  260 . In some embodiments, as illustrated in  FIG. 2 , the periphery  220   a  does not extend beyond the interior facing sidewall  260   b  of the base metal  260 . 
   Because light does not penetrate the base metal  260 , the active region  245  (shown within phantom lines) of the pin photo diode  200  is located primarily under the area inside of the base metal  260 , i.e. below a central LIGHT opening defined by the interior facing sidewall  260   b . Unlike the isolated mesa  120  of  FIG. 1 , which extends substantially beyond the periphery of the base layer  150 , the periphery  220   a  of the circular portion  220   r  of the implant region  220  does not extend beyond the inner periphery of the base metal  260  in the embodiment of  FIG. 2 . This size limitation provides reduced capacitance between the implant region  220  (subcollector) and the base layer  250 . 
     FIG. 3  shows a cross sectional view along the  3 - 3  line of  FIG. 4  of a pin photo diode  300  in accordance with one embodiment of the present invention. As shown in  FIGS. 3 and 4A , a contact portion  220   c  of the implant region  220  is located beyond the base metal  260 . An elongated strip portion  220   e  extends in a radial direction between the circular portion  220   r  and the contact portion  220   c  of the region  220 . A collector contact  230  is on the contact portion  220   c  of the implant region  220 . 
   Referring to  FIGS. 4 ,  4 B, and  4 C, the base metal layer  260  has an annular portion  260   w . Contact regions  260   c , which are distanced from the annular portion  260   w , allow vias  336  to contact the interconnect metal  338 . The base metal layer  260  is overlying the base layer  250 .  FIG. 4B  shows a top view of the base layer  250 . 
   In the embodiment of  FIG. 4 , only the elongated portion  220   e  of the subcollector implant region  220  passes under the base metal  260 . This provides a significantly reduced subcollector area extending under the base layer as compared to pin photo diodes having an isolated mesa subcollector area. This reduction of subcollector area is achieved by reducing the area under the base metal  260  near an optically inactive region of the photo diode. The inactive region occurs due to shading of the light by the base metal  260 . The n+ implant region is substantially confined to directly below the active region  245 , so there is no longer a significant amount of carriers in non-active region. As a result, the electric field is able to penetrate all the way through the substrate reducing the capacitance in the non-active region. The reduction in capacitance becomes more significant as a percentage of the total base-to-collector parasitic capacitance C bc  as photo diode size is reduced. 
   As a result of the reduced parasitic capacitance, the active device area of the photo diode can be designed larger to facilitate fiber alignment tasks. This is because the diameter of the active device area has to be greater than the beam-width to avert signal loss. Thus, some embodiments will allow more available light which can enhance responsivity. 
   Furthermore, referring to  FIGS. 3 and 4 , because the contact portion  260   c  is not opposing the base layer  250  it may be constructed large enough to accommodate a low resistance interconnection with the vias  336 . As such, with some embodiments it is possible able to reduce the base-to-collector capacitance C bc  without a significant increase in base resistance. 
   With conventional photo diodes, shown in  FIG. 1 , base-to-collector capacitance C bc  is tied to base resistance R s . Base-to-collector capacitance C bc  typically is reduced by reducing the size of the base metal ring, by either reducing the annular width of the base metal ring, or reducing the circular length of the base metal ring. As base-to-collector capacitance C bc  decreases, base resistance R s  increases, proportionally. Some embodiments of the present invention, however, allow the base-to-collector capacitance C bc  to be decreased without a concomitant increase in base resistance R s . Also, in certain embodiments of the present invention, the width of the annular portion  260   w  of the base metal ring may be increased without proportionately increasing C bc . Thus, it allows base resistance R s  to be decreased without a concomitant increase in base-to-collector capacitance C bc . 
     FIG. 5  is a simplified diagram optoelectric integrated circuit or OEIC  500  shown in cross sectional side view in accordance with one embodiment of the present invention. This embodiment, a pin photo diode  700  and a heterojunction bipolar transistor or HBT  600  are located on the same substrate  510 . The pin photo diode  700 , similar to those discussed above, includes an activated n+ implant region  720  within a semi-insulating substrate  510 , a lightly doped or intrinsic layer  740  located over the implant region  720 , and a p+ base layer  750  with an overlying base metal  760 . 
   This embodiment shows an n− passivation layer  770  shorted to the adjacent underlying p+ base layer by a conductor ring portion  780 , which connects the n− passivation layer  770  to the base metal conductor ring portion  760 . A similar passivation layer  770  may be included in the above discussed embodiments. The passivation layer  770  inhibits surface current. An optically non-active material may be utilized, such as for example InAlAs, InP, ect. 
   The HBT  600  may be located adjacent the pin photo diode  700 . As with the pin photo diode  700 , a patterned n+ implant region  620  is formed in the substrate  510 . An intrinsic layer  640  and a base layer  650  are located between the n+ subcollector implant region  620  and an emitter layer  670 . A collector metal  630  is located on the n+ implant region  620 , a base metal  660  is located on the extrinsic base layer  650 , and emitter metal  680  is located on the emitter layer  670 . Additionally, a portion of the extrinsic base layer  650  extends over the semi-insulating substrate  510 . With the OEIC embodiment, many of the corresponding layers/structures of the pin photo diode  700  and the HBT  600  may be fabricated during the same process steps. Thus, the intrinsic layer  740  (absorption layer of the pin diode  700 ) and the intrinsic layer  640  (collector of the HBT  600 ) may be formed from the same deposition layer(s), with the same thickness, for example about 300 nm to about 400 nm in thickness of intrinsic or lightly doped n− material. It is important to note that intrinsic layers may be formed of intrinsic material or of lightly doped material, or may be formed of several layers of intrinsic material and/or lightly doped material. 
   In certain embodiments with the semi-insulating substrate  510 , such as InP, or other semi-insulating, or insulating, substrates capable of patterned implantation, electrical isolation is present in the region  515  between the patterned implant region structures  620  and  720 . 
   In OEIC receivers, small sized photo detectors are often required due to their lower capacitance. The patterned implant may be performed prior to building the rest of the structures of the pin photo diode. As such, surface topology will not constrain buried n+ region tolerances as it sometimes does with traditional structures, which are sometimes fabricated with top down fabrication approaches. Thus, the patterned implant regions may be fabricated to extremely precise/small tolerances and sizes in order to limit capacitance and improve performance. Furthermore, the above described structures are more robust because they are formed on a buried n+ layer and adjacent substrate material. This reduces stack height and can reduce structural overhang of a collector, or a sub-collector. This improves processing yields and uniformity. Moreover, it can improve the thermal properties of the device. 
   Although the layers  640 ,  650 ,  670 ,  740 ,  750 , and  770  are illustrated as single layers, they may each include multiple sub-layers as is well known in the art. An example of a device having multiple sub-layers is illustrated by D. Huber et al., in “InP-InGaAs Single HBT Technology for Photorecever OEIC&#39;s at 40 Gb/s and Beyond”, Journal of Lightwave Technology, Vol. 18, No. 7, pp. 992-1000, July 2000, herein incorporated by reference. 
     FIG. 6  is a top view of a possible optoelectric integrated circuit in accordance with one embodiment of the present invention. A pin photo diode  400 , as discussed above, is coupled to an HBT  800 . The interconnect metal  334  is coupled between the subcollector  720  of the pin photo diode  400  and the base  850  of the HBT  800  through via  835  and base metal  860 . The base  850  and base metal  860  is located between emitter  870  and n+ implant region  820 . The collector interconnect metal is provided at  834 . 
   Furthermore, the HBT devices discussed above may be single-heterojunction bipolar transistor or SHBT, or double-heterojunction bipolar transistor or DHBT as known in the art. One example of a DHBT is discussed by Matsuoka, et al., in “Novel InP/InGaAs Double-Heterojunction Bipolar Transistors Suitable for High-Speed IC&#39;s and OEIC&#39;s, Conference Proceedings of the 6th International Conference on Indium Phosphide and Related Material (1994), pp. 555-558, herein incorporated by reference. Thus, in some embodiments, the pin photo diode  700  may be fabricated simultaneously with a DHBT  600 , as discussed by Matsuoka, et al. 
   Although the above example is illustrated with respect to an HBT transistor, other variations are possible. Various embodiments of the optoelectric integrated circuit may include field effect transistors, such as heterojunction field effect transistor or HFET, junction field effect transistor or JFET, or the like, or other transistor types. One example of a photodetector-JFET device is shown in “Advanced Integrated Planar In/InGaAs/InP:Fe Photoreceiver with Selectively Ion Implanted p and n Regions,” by C. Lauterbach et al., Inst. Phys. Conf., Ser. No. 112, Chapter 8, pp. 585-590, presented at Int. Symp. GaAs and Related Compounds (1980), herein incorporated by reference. In addition, other devices may be integrated and/or combined with the patterned implant pin photo diode discussed above. 
   Various embodiments of the present invention may include InP, InP:Fe, GaAs, InGaAs, as well as other Group III-V compounds, or the like, in the device layers and/or in the semi-insulating substrate/layer. Other semi-insulating substrates/layers are possible. 
   Having described this invention in connection with a number of embodiments, modification will now certainly suggest itself to those skilled in the art. As such, the invention is not to be limited to the disclosed embodiments except as required by the appended claims.