Abstract:
A first mixer circuit mixes a first center frequency signal with a first local oscillation signal to generate a second mixed signal, and mixes the first center frequency signal with a second local oscillation signal to generate a first mixed signal, and a second mixer circuit mixes a second center frequency signal with the first local oscillation signal to generate a fourth mixed signal, and mixes the second center frequency signal with the second local oscillation signal to generate a third mixed signal. An adder and subtracter circuit subtracts the third mixed signal from the second mixed signal to output a signal of subtraction result as a first upper side band signal, and adds the first mixed signal to the fourth mixed signal to output a signal of addition result as a second upper side band signal different in phase from the first upper side band signal by 90 degrees.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a reference signal generator circuit for use in, e.g., a wireless communication system, and in particular, a reference signal generator provided with two 90-degree phase shifters and two mixer circuits. 
     2. Description of the Related Art 
     In MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) which is a scheme for a UWB (Ultra Wide Band) system, as shown in  FIG. 8 , a frequency band (a band) in a range from 3.1 GHz to 10.6 GHz is divided into five groups G 1  to G 5 . Each of the groups G 1  to G 5  has three sub-frequency bands (subbands) and requires high-rate frequency switching of 9.2 nanoseconds. Conventionally, oscillators for handling the seven subbands (B 1  to B 7  and B 8  to B 14 ) have been proposed in such a manner that wide-band PLL circuits are switched or a plurality of SSB mixers are used. 
       FIG. 9  is a circuit diagram showing a configuration of a conventional reference signal generator circuit for use in a wireless communication system.  FIG. 10  is a spectrum diagram showing a reference signal generated by the reference signal generator circuit shown in  FIG. 9 . Referring to  FIG. 9 , the reference signal generator circuit is configured to include a center frequency oscillator  90  for generating a reference signal having a center frequency fc, mixers  91  and  92 , a shift frequency oscillator  93  for generating a local oscillation signal having a shift frequency Δf, a 90-degree phase shifter  94 , low pass filters (LPFs)  95  and  97 , high pass filters (HPFs)  96  and  98 , and multiplexers  99  and  100  for selectively switching between two input signals in accordance with a selection signal Ss to output reference signals S 1  and S 2 . 
     In the reference signal generator circuit configured as described above, the mixers  91  and  92  output mixed signals M 1  and M 2 , respectively, and the mixed signals M 1  and M 2  are expressed by the following equations: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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     where, H 1  and H 2  denote upper side band signals outputted from the HPFs  96  and  98 , respectively, and L 1  and L 2  denote lower side band signals outputted from the LPFs  95  and  97 , respectively. The multiplexers  99  and  100  selectively switch between the two input signals to output reference signals S 1  and S 2  called an I signal and a Q signal which are different in phase from each other by 90 degrees. 
     Documents related to the present invention are as follows:
     (a) Patent Document 1: Japanese Patent Laid-open Publication No. 2004-523142;   (b) Patent Document 2: Japanese Patent Laid-open Publication No. 2007-295068;   (c) Patent Document 3: U.S. Pat. No. 7,321,268; and   (d) Non-patent Document 1: Geum-Young Tak et al., “A 6.3-9-GHz CMOS Fast Setting PLL for MB-OFDM UWB Applications”, IEEE Journal of Solid-state Circuits, Vol. 40, No. 8, August 2005.   

     However, the use of the wide-band PLL circuit requires control of wide-band frequencies for the plurality of groups and control of fine frequencies corresponding to the subbands. Consequently, this case makes it considerably difficult to cover all the groups in the MB-OFDM (e.g., See Non-patent Document 1). In addition, when a normal mixer is used, a filter is required (e.g., See  FIG. 9 ). Alternatively, this case requires four or more SSB mixers (e.g., See Patent Document 2). Hence, there is a problem of increase in circuit scale. 
     In addition, the case where the filters  95  to  98  are used in accordance with the conventional example shown in  FIG. 9  causes the following problem. For example, if the shift frequency Δf is relatively small, a signal from one filter can not be completely separated from a signal from another filter with ease, as shown in  FIG. 10 . 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to solve the problems described above and to provide a reference signal generator circuit capable of generating a plurality of reference signals, which are different from each other by a predetermined shift frequency and are completely separated from each other, with a simple circuit configuration using no filters, unlike a conventional reference signal generator circuit. 
     In order to achieve the aforementioned objective, according to one aspect of the present invention, there is provided a reference signal generator circuit including first and second signal generators, first and second phase shifters, first and second mixer circuits, and an adder and subtractor circuit. 
     The first signal generator circuit generates a first center frequency signal having a center frequency, and the first phase shifter shifts a phase of the first center frequency signal by 90 degrees to generate a second center frequency signal. The second signal generator circuit generates a first local oscillation signal having a shift frequency, and the second phase shifter shifts a phase of the first local oscillation signal by 90 degrees to generate a second local oscillation signal. The first mixer circuit mixes the first center frequency signal with the first local oscillation signal to generate a second mixed signal, and mixes the first center frequency signal with the second local oscillation signal to generate a first mixed signal. The second mixer circuit mixes the second center frequency signal with the first local oscillation signal to generate a fourth mixed signal, and mixes the second center frequency signal with the second local oscillation signal to generate a third mixed signal. 
     The adder and subtracter circuit in a first case, (a) subtracts the third mixed signal from the second mixed signal to output a signal of subtraction result as a first upper side band signal, and (b) adds the first mixed signal to the fourth mixed signal to output a signal of addition result as a second upper side band signal which is different in phase from the first upper side band signal by 90 degrees. The adder and subtractor circuit in a second case, (c) adds the second mixed signal to the third mixed signal to output a signal of addition result as a first lower side band signal, and (d) subtracts the fourth mixed signal from the first mixed signal to output a signal of subtraction result as a second lower side band signal which is different in phase from the first lower side band signal by 90 degrees. 
     The above-mentioned reference signal generator circuit preferably further includes a switch circuit in a third case, for outputting the first and second center frequency signals in place of the first and second upper side band signals and the first and second lower side band signals, which are outputted from the adder and subtracter circuit. 
     In the above-mentioned reference signal generator circuit, the first mixer circuit and the second mixer circuit are preferably combined as a quadrature mixer with shared trans-conductance stage. 
     In addition, in the above-mentioned reference signal generator circuit, the reference signal generator circuit is preferably configured with one of a differential circuit and a CMOS differential circuit. 
     Accordingly, the reference signal generator circuit according to the present invention can generate a plurality of reference signals, which are different from each other by a predetermined shift frequency, are different in phase from each other by 90 degrees, and are completely separated from each other, with a simple circuit configuration using no filters, unlike a conventional reference signal generator circuit. In addition, the switch circuit is configured with, e.g., a transistor, so that the plurality of reference signals can be selectively switched at a high rate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings throughout which like parts are designated by like reference numerals, and in which: 
         FIG. 1  is a circuit diagram showing a first portion of a configuration of a reference signal generator circuit for use in a wireless communication system, according to one preferred embodiment of the present invention; 
         FIG. 2  is a circuit diagram showing a second portion of the reference signal generator circuit shown in  FIG. 1 ; 
         FIG. 3  is a table showing signals outputted from output terminals T 1 , T 2 , T 3  and T 4  selected in accordance with control voltages Vc 1  and Vc 2  in the reference signal generator circuit shown in  FIG. 1 ; 
         FIG. 4  is a spectrum diagram showing a reference signal generated by the reference signal generator circuit shown in  FIG. 1 ; 
         FIG. 5  is a circuit diagram showing a configuration of an implemental example in which the reference signal generator circuit shown in  FIG. 1  employs a CMOS circuit configuration; 
         FIG. 6A  is a circuit diagram showing a detailed circuit configuration of switch devices  51  to  54  shown in  FIG. 5 ; 
         FIG. 6B  is a diagram showing each symbol of the switch devices  51  to  54 ; 
         FIG. 7A  is a circuit diagram showing a detailed circuit of switch devices  55  to  58  shown in  FIG. 5 ; 
         FIG. 7B  is a diagram showing each symbol of the switch devices  55  to  58 ; 
         FIG. 8  is a spectrum diagram showing a frequency band in conventional UWB-OFDM; 
         FIG. 9  is a circuit diagram showing a configuration of a conventional reference signal generator circuit for use in a wireless communication system; and 
         FIG. 10  is a spectrum diagram showing a reference signal generated by the reference signal generator circuit shown in  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     With reference to the drawings, hereinafter, description will be given of preferred embodiments of the present invention. It is to be noted that like constituent elements are described with an identical reference mark in the respective preferred embodiments to be described below. 
       FIG. 1  is a circuit diagram showing a first portion of a configuration of a reference signal generator circuit for use in a wireless communication system, according to the preferred embodiment of the present invention.  FIG. 2  is a circuit diagram showing a second portion of the reference signal generator circuit shown in  FIG. 1 . The reference signal generator circuit shown in  FIGS. 1 and 2  is configured to include a center frequency oscillator  10 , a shift frequency oscillator  20 , two 90-degree phase shifters  11  and  21 , four differential buffer amplifiers  12 ,  13 ,  22  and  23 , a differential quadrature mixer circuit  30  configured with mixers  31  and  32 , a differential quadrature mixer circuit  40  configured with mixers  41  and  42 , switch devices  51  to  58  and  61  to  64  each configured with a CMOS circuit, and a controller  70  for controlling the switch devices  51  to  58  and  61  to  64 . 
     Referring to  FIG. 2 , the center frequency oscillator  10  generates a reference signal having a predetermined center frequency fc to output the reference signal to the differential buffer amplifier  12 , and also, to output the reference signal to the differential buffer amplifier  13  via the 90-degree phase shifter  11 . The differential buffer amplifier  12  buffers and amplifies the input signal to generate two center frequency signals Ic and −Ic having a mutually differential relation, and outputs the center frequency signals Ic and −Ic to the mixers  31  and  32  of the differential quadrature mixer circuit  30  shown in  FIG. 1 . In addition, the differential buffer amplifier  13  buffers and amplifies the input signal to generate two center frequency signals Qc and −Qc having a mutually differential relation, and outputs the center frequency signals Qc and −Qc to the mixers  41  and  42  of the differential quadrature mixer circuit  40  shown in  FIG. 1 . The shift frequency oscillator  20  generates a local oscillation signal having a predetermined shift frequency Δf to output the local oscillation signal to the differential, buffer amplifier  22 , and also, to output the local oscillation signal to the differential buffer amplifier  23  via the 90-degree phase shifter  21 . The differential buffer amplifier  22  buffers and amplifies the input signal to generate two local oscillation signals Id and −Id having a mutually differential relation, and outputs the local oscillation signals Id and −Id to the mixer  31  of the differential quadrature mixer circuit  30  shown in  FIG. 1  and the mixer  41  of the differential quadrature mixer circuit  40  shown in  FIG. 1 . In addition, the differential buffer amplifier  23  buffers and amplifies the input signal to generate two center frequency signals Qd and −Qd having a mutually differential relation, and outputs the center frequency signals Qd and −Qd to the mixer  32  of the differential quadrature mixer circuit  30  shown in  FIG. 1  and the mixer  42  of the differential quadrature mixer circuit  40  shown in  FIG. 1 . 
     Referring to  FIG. 1 , the mixer  31  of the differential quadrature mixer circuit  30  has at least second-order non-linear input and output characteristic. The mixer  31  performs a multiplying operation by mixing the center frequency signals Ic and −Ic with the local oscillation signals Id and −Id, and generates and outputs mixed signals E 2  and −E 2  having a mutually differential relation. In this case, the mixed signal E 2  is outputted to a terminal T 11  and to an output terminal T 1  via a contact “b” of the switch device  61 . On the other hand, the mixed signal −E 2  is outputted to a terminal T 12  and to an output terminal T 2  via a contact “b” of the switch device  62 . 
     In addition, the mixer  32  of the differential quadrature mixer circuit  30  has at least second-order non-linear input and output characteristic. The mixer  32  performs a multiplying operation by mixing the center frequency signals Ic and −Ic with the local oscillation signals Qd and −Qd, and generates and outputs mixed signals E 1  and −E 1  having a mutually differential relation. In this case, the mixed signal E 1  is outputted to a terminal T 13  and to an output terminal T 3  via a contact “b” of the switch device  63 . On the other hand, the mixed signal −E 1  is outputted to a terminal T 14  and to an output terminal T 4  via a contact “b” of the switch device  64 . 
     Further, the mixer  41  of the differential quadrature mixer circuit  40  has at least second-order non-linear input and output characteristic. The mixer  41  performs a multiplying operation by mixing the center frequency signals Qc and −Qc with the local oscillation signals Id and −Id, and generates and outputs mixed signals E 4  and −E 4  having a mutually differential relation. In this case, the mixed signal E 4  is outputted to the switch device  51 , to the terminal T 13 , and to the output terminal T 3  via the contact “b” of the switch device  63 . The mixed signal E 4  is also outputted to the switch device  55 , to the terminal T 14 , and to the output terminal T 4  via the contact “b” of the switch device  64 . In addition, the mixed signal −E 4  is outputted to the switch device  52 , to the terminal T 14 , and to the output terminal T 4  via the contact “b” of the switch device  64 . The mixed signal −E 4  is also outputted to the switch device  56 , to the terminal T 13 , and to the output terminal T 3  via the contact “b” of the switch device  63 . 
     Furthermore, the mixer  42  of the differential quadrature mixer circuit  40  has at least second-order non-linear input and output characteristic. The mixer  42  performs a multiplying operation by mixing the center frequency signals Qc and −Qc with the local oscillation signals Qd and −Qd, and generates and outputs mixed signals E 3  and −E 3  having a mutually differential relation. In this case, the mixed signal E 3  is outputted to the switch device  53 , to the terminal T 12 , and to the output terminal  72  via the contact “b” of the switch device  62 . The mixed signal E 3  is also outputted to the switch device  57 , to the terminal T 11 , and to the output terminal T 1  via the contact “b” of the switch device  61 . In addition, the mixed signal −E 3  is outputted to the switch device  54 , to the terminal T 11 , and to the output terminal T 1  via the contact “b” of the switch device  61 . The mixed signal −E 3  is also outputted to the switch device  58 , to the terminal T 12 , and to the output terminal T 2  via the contact “b” of the switch device  62 . 
     The controller  70  generates a control voltage Vc 1 , and outputs the control voltage Vc 1  to the switch devices  51  to  58  to perform ON/OFF control. The controller  70  also generates a control voltage Vc 2 , and outputs the control voltage Vc 2  to the switch devices  61  to  64  to perform ON/OFF control. For example, when the controller  70  generates a control voltage Vc 2  having an H level such as a direct-current voltage V DD , a contact “a” is selected in the switch devices  61  to  64 . On the other hand, when the controller  70  generates a control voltage Vc 2  having an L level such as a ground voltage, the contact “b” is selected in the switch devices  61  to  64 . In addition, when the controller  70  generates a control voltage Vc 1  having the H level such as a direct-current voltage V DD , the switch devices  51  to  54  are turned on whereas the switch devices  55  to  58  are turned off. Further, when the controller  70  generates a control voltage Vc 1  having the L level such as a ground voltage, the switch devices  51  to  54  are turned off whereas the switch devices  55  to  58  are turned on. Each of the terminals T 11 , T 12 , T 13  and T 14  performs an adding operation or a subtracting operation on electric currents from the respective mixers  31 ,  32 ,  41  and  42  in accordance with the ON state or the OFF state of the switch devices  51  to  58  to generate a signal having a voltage level corresponding to each electric current. 
       FIG. 3  is a table showing signals outputted from the output terminals T 1 , T 2 , T 3  and T 4  selected in accordance with the control voltages Vc 1  and Vc 2  in the reference signal generator circuit shown in  FIG. 1 . It is apparent from  FIG. 3  that when the control voltage Vc 2  has the H level, the contact “a” is selected in the switch devices  61  to  64 , so that the center frequency signals Ic, −Ic, Qc and −Qc are outputted from the terminals T 1 , T 2 , T 3  and T 4 , respectively. On the other hand, when the control voltage Vc 2  has the L level, the contact “b” is selected in the switch devices  61  to  64 , so that upper side band signals (Iu, −Iu, Qu, −Qu) or lower side band signals (π, −π, Q 1 , −Q 1 ) corresponding to reference signals according to the ON state or the OFF state of the switch devices  51  to  58  are outputted from the output terminals T 1  to T 4 , respectively. In  FIG. 3 , the signals E 1  to E 4  as well as these addition and subtraction signals are expressed by the following equations: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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                         , 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
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                         = 
                         
                           
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                         , 
                       
                     
                   
                 
               
               
                 
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                     = 
                     
                       
                         
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                   ( 
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                     = 
                     
                       
                         
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                         ⁡ 
                         
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                   ( 
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                   , 
                 
               
               
                 
                   ( 
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                 and 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     Q 
                     ⁢ 
                     
                         
                     
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                   = 
                   
                     
                       
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                     = 
                     
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                       ⁢ 
                       
                         
                           ( 
                           
                             
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                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     According to the reference signal generator circuit configured as described above, the center frequency signal having the center frequency fc, the signal whose phase is shifted by 90 degrees, and the two local oscillation signals which are different in phase from each other by 90 degrees and have the shift frequency Δf are inputted to the differential quadrature mixer circuits  30  and  40  to be mixed with each other, and the resultant mixed signals are subjected to the adding operation or the subtracting operation. Thus, the reference signal having the center frequency fc and the reference signals having the side band frequencies fc±Δf, which are selected at a high rate and are completely separated from each other without use of filters, can be generated at the output terminals T 1  to T 4 , as shown in  FIG. 4 . Accordingly, the present invention proposes a novel scheme suitable for a UWB synthesizer that requires high-rate frequency hopping. 
     In the reference signal generator circuit, the use of the differential quadrature mixer circuits  30  and  40  simultaneously allows some advantageous effects such as control of fine frequencies corresponding to subbands based on signal calculation by simple interconnections, elimination of filters, and correction of orthogonality of signals. Moreover, in MB-OFDM application, the reference signal generator circuit can handle seven or more bands with an oscillator configuration (including a PLL configuration) in about or less than 10 GHz while the configuration thereof is made compact. That is, the reference signal generator circuit according to the present preferred embodiment can generate a plurality of reference signals, which are different from each other by a predetermined shift frequency and are completely separated from each other, with a simple circuit configuration using no filters, wake a conventional reference signal generator circuit. 
     IMPLEMENTAL EXAMPLE 
       FIG. 5  is a circuit diagram showing a configuration of an implemental example in which the reference signal generator circuit shown in  FIG. 1  employs a CMOS circuit configuration. In  FIG. 5 , constituent elements similar to those shown in  FIGS. 1 and 2  are shown with the identical numeral reference, and therefore description thereof will not be given. 
     Referring to  FIG. 5 , a differential quadrature mixer circuit  30  is configured to include a mixer  31  configured with four n-channel MOS field effect transistors (hereinafter, referred to as nMOSFETs) Q 1  to Q 4 , resistors R 1  and R 2 , two nMOSFETs Q 9  and Q 10 , and a current source CS 1 ; and a mixer  32  configured with four nMOSFETs Q 5  to Q 8 , resistors R 3  and R 4 , the two nMOSFETs Q 9  and Q 10 , and the current source CS 1 . In this case, the mixers  31  and  32  share use of the two nMOSFETs Q 9  and Q 10 , and the current source CS 1 . In addition, a differential quadrature mixer circuit  40  is configured to include a mixer  41  configured with four nMOSFETs Q 11  to Q 14 , resistors R 5  and R 6 , two nMOSFETs Q 19  and Q 20 , and a current source CS 2 ; and a mixer  42  configured with four nMOSFETs Q 15  to Q 18 ; resistors R 7  and R 8 , the two nMOSFETs Q 19  and Q 20 , and the current source CS 2 . In this case, the mixers  41  and  42  share use of the two nMOSFETs Q 19  and Q 20 , and the current source CS 2 . 
     It is to be noted that a voltage source of a direct-current voltage V DD  is connected to drains of the nMOSFETs Q 1  and Q 3  via the resistor R 1 , and also, is connected to drains of the nMOSFETs Q 2  and Q 4  via the resistor R 2 . The voltage source of the direct-current voltage V DD  is connected to drains of the nMOSFETs Q 5  and Q 7  via the resistor R 3 , and also, is connected to drains of the nMOSFETs Q 6  and Q 8  via the resistor R 4 . In addition, the voltage source of the direct-current voltage V DD  is connected to drains of the nMOSFETs Q 11  and Q 13  via the resistor R 5 , and also, is connected to drains of the nMOSFETs Q 12  and Q 14  via the resistor R 6 . The voltage source of the direct-current voltage V DD  is connected to drains of the nMOSFETs Q 15  and Q 17  via the resistor R 7 , and also, is connected to drains of the nMOSFETs Q 16  and Q 18  via the resistor R 8 . In this case, a node between the nMOSFET Q 1  and the nMOSFET Q 3  is connected to a terminal T 11 , and a node between the drain of the nMOSFET Q 2  and the drain of the nMOSFET Q 4  is connected to a terminal T 12 . A node between the drain of the nMOSFET Q 5  and the drain of the nMOSFET Q 7  is connected to a terminal T 14 , and a node between the drain of the nMOSFET Q 6  and the drain of the nMOSFET Q 8  is connected to a terminal T 13 . A node between the drain of the nMOSFET Q 11  and the drain of the nMOSFET Q 13  is connected to the terminal T 13  via a switch device  51 , and also, is connected to the terminal T 14  via a switch device  55 . A node between the drain of the nMOSFET Q 12  and the drain of the nMOSFET Q 14  is connected to the terminal T 14  via a switch device  52 , and also, is connected to the terminal T 13  via a switch device  56 . A node between the drain of the nMOSFET Q 15  and the drain of the nMOSFET Q 17  is connected to the terminal T 11  via a switch device  54 , and also, is connected to the terminal T 12  via a switch device  58 . A node between the drain of the nMOSFET Q 16  and the drain of the nMOSFET Q 18  is connected to the terminal T 12  via a switch device  53 , and also, is connected to the terminal T 11  via a switch device  57 . It is to be noted that the remaining configuration is similar to the circuit configuration shown in  FIGS. 1 and 2 . 
       FIG. 6A  is a circuit diagram showing a detailed circuit configuration of the switch devices  51  to  54  shown in  FIG. 5 , and  FIG. 6B  is a diagram showing each symbol of the switch devices  51  to  54 . Referring to  FIG. 6A , each of the switch devices  51  to  54  is configured to include an nMOSFET Q 21 , a p-channel MOS field effect transistor (hereinafter, referred to as a pMOSFET) Q 22  and an inverter  81 . When a control voltage Vc 1  has an H level, the switch devices  51  to  54  are turned on. On the other hand, when the control voltage Vc 1  has an L level, the switch devices  51  to  54  are turned off. 
       FIG. 7A  is a circuit diagram showing a detailed circuit configuration of the switch devices  55  to  58  shown in  FIG. 5 , and  FIG. 73  is a diagram showing each symbol of the switch devices  55  to  58 . Referring to  FIG. 7A , each of the switch devices  55  to  58  is configured to include a pMOSFET Q 23 , an nMOSFET Q 24  and an inverter  82 . When the control voltage Vc 1  has the H level, the switch devices  55  to  58  are turned off. On the other hand, when the control voltage Vc 1  has the L level, the switch devices  55  to  58  are turned on. 
     In the reference signal generator circuit shown in  FIG. 5 , each of the differential quadrature mixer circuits  30  and  40  has such a circuit configuration that two Gilbert cell circuits are combined. The two mixer circuits  30  and  40  may be combined as a quadrature mixer with shared trans-conductance (gm) stage. Each of the differential quadrature mixer circuits  30  and  40  outputs a mixed signal of an I signal and a Q signal (a cosine wave and a sine wave) which are signals orthogonal to each other, and simultaneously, corrects orthogonality thereof by itself. The reference signal generator circuit shown in  FIG. 5  operates in a manner similar to that of the reference signal generator circuit shown in  FIG. 1 , and has functions and advantageous effects similar to those of the reference signal generator circuit shown in  FIG. 1 . 
     In the foregoing preferred embodiment and implemental example, the reference signal generator circuit has the differential circuit configuration, however, the present invention is not limited thereto. The reference signal generator circuit may have a circuit configuration for a single signal. 
     AVAILABILITY OF INDUSTRIAL UTILIZATION 
     As described above in detail, the reference signal generator circuit according to the present invention can generate a plurality of reference signals, which are different from each other by a predetermined shift frequency, are different in phase from each other by 90 degrees, and are completely separated from each other, with a simple circuit configuration using no filters, unlike a conventional reference signal generator circuit. In addition, the switch circuit is configured with, e.g., a transistor, so that the plurality of reference signals can be selectively switched at a high rate. In particular, in a UWB wireless communication system, the reference signal generator circuit according to the present invention is suitably used as a circuit for generating a plurality of reference frequency signals in an MB-OFDM scheme or a wireless communication circuit for performing frequency hopping. 
     Although the present invention has been fully described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications are apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims unless they depart therefrom.