Abstract:
A memory core includes a bit line and a word line. The memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line. Methods for accessing a memory core cell also are described.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is related to the following applications: (1) U.S. patent application Ser. No. ______ (Attorney Docket No. MXICP020), filed on the same day as the instant application, and entitled “Method for Adjusting the Threshold Voltage of a Memory Cell”; and (2) U.S. patent application Ser. No. ______ (Attorney Docket No. MXICP022), filed on the same day as the instant application, and entitled “Multi-Level Memory Device and Methods for Programming and Reading the Same.” The disclosures of these related applications are incorporated herein by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    The present invention relates generally to memory devices and, more particularly, to a memory cell structure not requiring access transistors.  
           [0003]    Typical memory cells include a steering element, e.g., one or more transistors, to access each cell. The access transistors, which may also be diodes, provide access for the word lines to the bit lines of the memory cell. That is, the access transistors act as a pass gate to provide access for the word line to the bit line in order to read and write data to a memory cell. With respect to chalcogenide memory cells, the current/voltage required to program the chalcogenide memory cells is relatively high as compared to the operating current/voltage. However, the access transistors may not be able to handle the programming voltages, thereby limiting the current that can be used for programming because a high current may damage the transistors or diodes acting as access transistors for the memory cells.  
           [0004]    In light of the foregoing, there is a need for a memory cell structure that enables selective access to the core cells without the need of an access transistor.  
         SUMMARY OF THE INVENTION  
         [0005]    Broadly speaking, the present invention enables the access transistor, which is also referred to as a steering element, for accessing a memory core cell to be eliminated through the use of a threshold changing material that can be programmed to function as a steering element.  
           [0006]    In accordance with one aspect of the present invention, a memory core is provided. The memory core includes a bit line and a word line. A core cell in electrical communication with the word line and the bit line is included. The core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line.  
           [0007]    In one embodiment, the threshold changing material is associated with transistor like properties enabling the memory core to function as both a steering device and a memory device. In one embodiment, the threshold material is programmed by either a floating technique or a bias technique.  
           [0008]    In accordance with another aspect of the present invention, a method for providing access to a memory core cell is provided. The method initiates with determining a threshold voltage for access to a memory core cell. Then, a threshold changing material of the memory core cell is programmed to enable access to the memory core cell at the threshold voltage. Next, a voltage is applied to a word line in communication with the memory core cell. If the voltage is at least as large as the threshold voltage, then the method includes accessing the memory core cell.  
           [0009]    In accordance with yet another aspect of the present invention, a method for reading a chalcogenide memory device is provided. The method initiates with applying a read voltage to a word line. The read voltage is configured to directly access the chalcogenide memory device. Then, a zero bias is applied on the bit line corresponding to the word line. Next, a value stored in the chalcogenide memory device is read.  
           [0010]    It will be apparent to those skilled in the art that the method of adjusting the V th  of the present invention can be applied in numerous memory/solid state device applications. One of the significant advantages of the memory core is the elimination of access transistors that function as steering elements for signals to the memory core cells.  
           [0011]    It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention.  
         [0013]    [0013]FIG. 1 is an I-V curve of chalcogenide memory cells associated with different V th .  
         [0014]    [0014]FIG. 2 is a graph representing the symmetric nature of the current (I)-voltage (V) characteristic of a chalcogenide memory device.  
         [0015]    [0015]FIG. 3 is a simplified schematic diagram of a memory array having dual function memory cells.  
         [0016]    [0016]FIGS. 4A through 4D illustrate exemplary plots associated with programming techniques that may be applied to a chalcogenide memory device.  
         [0017]    [0017]FIGS. 5A through 5C illustrate three exemplary methods for reading a device.  
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0018]    Several exemplary embodiments of the invention will now be described in detail with reference to the accompanying drawings.  
         [0019]    In accordance with the present invention, a threshold changing material is incorporated into a memory cell in order to eliminate the need for access transistors. In one embodiment, the threshold changing material is a chalcogenide material. Further information on adjusting the threshold voltage, V th , of a material capable of changing V th  is discussed in related U.S. patent application Ser. No. ______ ( Attorney Docket No MXICP020), filed on even date herewith, and entitled “Method for Adjusting the Threshold Voltage for a Memory Cell.” The disclosure of this related application is incorporated herein by reference for all purposes. In one embodiment, the transistor-like properties of the threshold changing material are exploited to simplify the memory cell structure by enabling the elimination of the steering element, e.g., the access transistor or P—N diode. It will be apparent to one skilled in the art that the chalcogenide memory cell may be embedded with logic circuits to form a system on a chip (SoC). Furthermore, with respect to chalcogenide, the nonvolatile nature once programmed, enables for relatively fast reading and writing operations. It should be appreciated that the programming voltage associated with a threshold changing material, e.g., a chalcogenide material, is much lower than that of a flash read only memory (ROM). For example, the programming voltage associated with a chalcogenide memory cell is about 5 volts (V) as compared to a programming voltage of about 10 V for a flash ROM.  
         [0020]    The chalcogenide memory cell is capable of functioning as both a steering device and memory device. Accordingly, the fabrication of just a chalcogenide memory cell is much easier than combining both a transistor and a chalcogenide memory cell. Additionally, where the memory cell also acts as a steering device, enables a reduction in the chip size for the same amount of memory as compared to a memory having separate steering devices and memory cells. Alternatively, a dual functioning chalcogenide memory may be able to provide more memory capacity as compared to memories having separate steering devices and memory cells. As discussed herein, a minimum-sized chalcogenide memory device is capable of passing a higher current as compared to an access transistor. It should be appreciated that while a chalcogenide material is used as an example of a threshold changing material, the embodiments described herein are not limited to a chalcogenide material. That is, any suitable material having the desirable characteristics of a chalcogenide material, i.e., having stable and tunable voltage threshold (V th ) properties, may serve as a nonvolatile dual function memory cell.  
         [0021]    [0021]FIG. 1 is an I-V curve of chalcogenide memory cells associated with different V th .As discussed in the above-mentioned related application (Attorney Docket No MXICP020), the V th  of chalcogenide may be adjusted by applying energy into the film. Therefore, there can be chalcogenide memory cells having different V th  within a memory core. Because the device can pass high current when voltage is below V th  and can block current when voltage is below V th , the device is capable of serving as an active steering device. It should be appreciated that because the V th  is capable of being tuned and the V th  is stable after programming, the cell can serve as a nonvolatile memory device. FIG. 1 illustrates a first threshold voltage (V th1 ) associated with a memory cell captured by line  102  and a second threshold voltage (V th2 ) associated with a memory cell captured by line  104 .  
         [0022]    [0022]FIG. 2 is a graph representing the symmetric nature of the current (I)-voltage (V) characteristic of a chalcogenide memory device. As shown therein, line  106  illustrates the symmetrical nature between the relationship of I and V for the chalcogenide memory device.  
         [0023]    [0023]FIG. 3 is a simplified schematic diagram of a memory array having dual function memory cells. Memory cells  108   a  through  108   n  are illustrated in the matrix defined by word lines (WLn) WLn−1 to WLn+1 and bit lines BLn−1 to BLn+1. Since the chalcogenide memory cells function as both a memory cell and steering device, there is no need for access transistors.  
         [0024]    [0024]FIGS. 4A through 4D illustrate exemplary plots associated with programming techniques that may be applied to a chalcogenide device. FIG. 4A illustrates a floating programming technique. Here, it is assumed that the chalcogenide memory device includes two voltage thresholds, i.e., a low voltage threshold (V th1 ) as state 1 and a high voltage threshold (V thh ) state 0. The plot of FIG. 4A illustrates the bias applied and the resulting bias on the cells. The unselected cells are associated with a bias of −V p  to +V p . The selected cell is associated with a forward bias of +V p . Cell  108   s  represents the selected cell, while the remainder of cells  108   a - 108   n  represent the unselected cells. Table 1 below summarizes the programming method for program 1 and program 0.  
                                             TABLE 1                                   Program 1   Program 0                                        Selected Bit line   0   0           Other Bit line   Floating   Floating           Selected Word line   V pl     V ph             Other Word line   Floating   Floating                      
 
         [0025]    As summarized in Table 1, the selected bit line is zero, while the selected word line is dependent upon the program or state selected, i.e., V p1  or V ph .  
         [0026]    [0026]FIG. 4B illustrates a biased programming technique. The plot of FIG. 4B illustrates the bias applied. Here, a voltage (bias) may be applied on the unselected word lines and bit lines. The selected cell  108   s  is associated with a forward bias of +V p . It may be assumed that the chalcogenide memory device includes two voltage thresholds, i.e., a low voltage threshold (V th1 ) as state 1 and a high voltage threshold (V thh ) state 0. The programming method for states 1 and 0 is listed in Table 2 below.  
                                             TABLE 2                                   Program 1   Program 0                                        Selected Bit line   0   0           Other Bit line   0 ≦ V ≦ V pl     0 ≦ V ≦ V ph             Selected Word line   V pl     V ph             Other Word line   0 ≦ V ≦ V pl     0 ≦ V ≦ V ph                        
 
         [0027]    As summarized in Table 2, the selected bit line is zero, while the selected word line is dependent upon the program or state selected, i.e., V p1  or V ph . It should be appreciated that two exemplary types of bias programming methods may be used, i.e., the V/2 method and the V/3 method, illustrated in FIGS. 4C and 4D, respectively. Of course, other bias programming methods may be used as the methods illustrated herein are exemplary and not meant to be limiting.  
         [0028]    [0028]FIG. 4C illustrates a plot of the V/2 method. The plot of FIG. 4C illustrates the bias applied and the resulting bias on the cell. The selected cell  108   s  is associated with a forward bias of +V p  while the remaining unselected cells are associated with a forward bias of +V p /2. It may be assumed that the chalcogenide memory device includes two voltage thresholds, i.e., a low voltage threshold (V th1 ) as state 1 and a high voltage threshold (V thh ) state 0. The programming method for states 1 and 0 is listed in Table 3 below.  
                                             TABLE 3                                   Program 1   Program 0                                        Selected Bit line   0   0           Other Bit line   V pl /2   V ph /2           Selected Word line   V pl     V ph             Other Word line   V pl /2   V ph /2                      
 
         [0029]    As summarized in Table 3, the selected bit line is zero, while the selected word line is dependent upon the program or state selected, i.e., V p1  or V ph .  
         [0030]    [0030]FIG. 4D illustrates a plot of the V/3 method. The plot of FIG. 4D illustrates the bias applied and the resulting bias on the cell. The selected cell  108   s  is associated with a forward bias of +V p  while the remaining unselected cells fall into one of two characterizations, i.e., those associated with a forward bias and those associated with a reverse bias. Cells  108   f  are associated with a forward bias of +V p /3, while cells  108   r  are associated with a reverse bias of −V p /3. It may be assumed that the chalcogenide memory device includes two voltage thresholds, i.e., a low voltage threshold (V th1 ) as state 1 and a high voltage threshold (V thh ) state 0. The programming method for states 1 and 0 is listed in Table 4 below.  
                                             TABLE 4                                   Program 1   Program 0                                        Selected Bit line   0   0           Other Bit line   2V pl /3   2V ph /3           Selected Word line   V pl     V ph             Other Word line   V pl /3   V ph /3                      
 
         [0031]    As summarized in Table 4, the selected bit line is zero, while the selected word line is dependent upon the program or state selected, i.e., V p1  or V ph . It should be appreciated that the limit of the programming voltage may be represented as: V th  high&lt;Vp&lt;3Vth low.  
         [0032]    The reading methods include a floating method and a bias method. The floating method refers to a bias V r  that is applied between V th1  and V thh  on the selected word line (or bit line) and zero bias on the selected word line (or bit line). Other word lines and bit lines are floating. The bias method refers to a bias V r  that is applied between V th1  and V thh  on the selected word line (or bit line) and zero bias on the selected word line (or bit line). Other word lines and bit lines apply a certain bias of 0&lt;V&lt;V th1 . Two illustrative bias methods, V/2 method and V/3 method were presented.  
         [0033]    [0033]FIGS. 5A through 5C illustrate three exemplary methods for reading a device. Each of FIGS. 5A-5C represents the bias applied and the resulting bias on the cells. FIG. 5A represents a floating method where the bias is −V r −&gt;+V r  and selected cell  108   s  is associated with a forward bias of +V r . FIG. 5B represents a V/2 reading method. Selected cell  108   s  is associated with a forward bias of +V r . The remaining unselected cells of FIG. 5B are associated with a forward bias of +V r /2. FIG. 5C represents a V/3 reading method. Selected cell  108   s  is associated with a forward bias of +V r . The remaining unselected cells of FIG. 5C are associated with either a forward bias of +V r /3 or a reverse bias of −V r /3. It should be appreciated that the unselected cells form a similar pattern as discussed above with reference to FIG. 4D.  
         [0034]    In summary, the present invention provides a memory core that eliminates the need for access transistors providing access to the core cells. That is, the access to the core cells may be accomplished through the programming of the core cells when the core cells incorporate a threshold changing material, e.g., a chalcogenide material. In essence, the steering element is now accomplished through the programming of the threshold changing material. One skilled in the art will appreciate that the elimination of the access transistors also provides for simplified decode logic as signals for the access transistors are no longer necessary for the embodiments described herein.  
         [0035]    The invention has been described herein in terms of several exemplary embodiments. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention. The embodiments and preferred features described above should be considered exemplary, with the scope of the invention being defined by the appended claims and their equivalents.