Abstract:
A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

Description:
FIELD OF THE INVENTION 
   The present invention relates to the field of high power devices; more specifically, it relates to high power devices, isolation of high power devices and methods of manufacturing high power devices and integration of high power devices with conventional logic and memory devices. 
   BACKGROUND OF THE INVENTION 
   High power devices utilize internal dielectric isolation to electrically isolate internal elements of the devices from each other as well as dielectric isolation to electrically isolate the high power devices from other, lower power, devices. Conventional isolation methods result in a compromise between the effectiveness of the inter-device isolation and the performance of the high power devices. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove. 
   SUMMARY OF THE INVENTION 
   A first aspect of the present invention is a method of fabricating an electronic device, comprising: forming a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; forming a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and forming a first device in the first region and forming a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device. 
   A second aspect of the present invention is a structure, comprising: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
       FIG. 1A  is a cross-section illustrating a first inter-device isolation scheme with a first intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 1B  is a cross-section illustrating the first inter-device isolation scheme with a second intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 1C  is a cross-section illustrating the first inter-device isolation scheme with a third intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 1D  is a cross-section illustrating the first inter-device isolation scheme with a fourth intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 2A  is a cross-section illustrating a second inter-device isolation scheme with the first intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 2B  is a cross-section illustrating the second inter-device isolation scheme with the second intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 2C  is a cross-section illustrating the second inter-device isolation scheme with the third intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 2D  is a cross-section illustrating the second inter-device isolation scheme with the fourth intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 3A  is a cross-section illustrating a third inter-device isolation scheme with the first intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 3B  is a cross-section illustrating the third inter-device isolation scheme with the second intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 3C  is a cross-section illustrating the third inter-device isolation scheme with the third intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 3D  is a cross-section illustrating the third inter-device isolation scheme with the fourth intra-device isolation scheme according to embodiments of the present invention; 
       FIG. 4A  is a cross-section of an exemplary first high power device that may be integrated with conventional devices according to embodiments of the present invention; 
       FIG. 4B  is a cross-section of an exemplary second high power device that may be integrated with conventional devices according to embodiments of the present invention; 
       FIG. 5  is a cross-section illustrating application of the present invention to a silicon-on-insulator substrate; 
       FIG. 6  is a cross-section of an exemplary first conventional power device that may be integrated with the high power devices according to embodiments of the present invention; 
       FIG. 7  is a cross-section of an exemplary second conventional power device that may be integrated with the high power devices according to embodiments of the present invention; and 
       FIG. 8  is a cross-section of an exemplary third conventional power device that may be integrated with the high power devices according to embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1A  is a cross-section illustrating a first inter-device isolation scheme with a first intra-device isolation scheme according to embodiments of the present invention. In  FIG. 1A , a semiconductor substrate  100  has a top surface  105  and includes a first region  110  and a second region  115 . First region  110  is exemplary of multiple first regions  110  and second region  115  is exemplary of multiple second regions  115 . First region(s)  110  are electrically isolated from each other and from second regions  115  by shallow trench isolation (STI)  120 . Second region(s)  115  are also electrically isolated from each other and from first regions  110  by STI  120 . STI  120  extends a perpendicular distance D 1  from top surface  105  of substrate  100  into the substrate. Within second region(s)  115  is a very shallow trench isolation(s) (VSTI)  125 . VSTI  125  extends a perpendicular distance D 2  from top surface  105  of substrate  100  into the substrate. D 1  is greater than D 2 . Conventional power devices such as p-channel and n-channel field effect transistors (NFETs and PFETs), bipolar transistors and diodes may be fabricated in first regions  110  of substrate  100 . High power devices such as lateral double diffused metal-oxide-silicon (LDMOS) devices may be fabricated in second regions  115 . In the case of LDMOS devices, VSTI is formed under the gate in the drain side of the LDMOS device (see  FIGS. 4A and 4B  and description infra). 
   In one example, substrate  100  is a single crystal silicon substrate. In one example, STI and VSTI independently comprise tetraethoxysilane (TEOS) oxide or high-density plasma (HDP) oxide. In one example, STI  120  and VSTI  125  may be formed by etching two sets of trenches of different depths into substrate  100 , overfilling the trenches with a dielectric material and then performing a chemical-mechanical polish (CMP) to remove excess dielectric material so top surfaces of STI  120  and VSTI  125  are coplanar with top surface  105  of the substrate. Either STI  120  or VSTI  125  may be formed fully formed first or the STI  120  and VSTI  125  trenches may be formed separately and filled simultaneously. In one example, a high voltage device is a device capable of sustaining about 25 volts or more of gate to drain voltage. The value of D 1  is chosen to optimize inter-device leakage and the value of D 2  chosen to optimize the speed of the high voltage device. 
     FIG. 1B  is a cross-section illustrating the first inter-device isolation scheme with a second intra-device isolation scheme according to embodiments of the present invention.  FIG. 1B  is similar to  FIG. 1A  except VSTI  125  of  FIG. 1A  is replaced with dual-depth STI (DDSTI)  130 . DDSTI  130  includes a thin region  132  and a thick region  134 . Thin region  132  of DDSTI  130  extends a perpendicular distance D 3  from top surface  105  of substrate  100  into the substrate. Thick region  134  of DDSTI  130  extends a perpendicular distance D 4  from top surface  105  of substrate  100  into the substrate. D 1  is greater than D 4 . In one example, DDSTI comprises tetraethoxysilane (TEOS) oxide or high-density plasma (HDP) oxide. In one example, STI  120  and DDSTI  130  may be formed by etching three sets trenches of different depths. Two sets of the three sets of trenches form the DDSTI into substrate  100 , overfilling the trenches with a dielectric material and then performing a chemical-mechanical polish (CMP) to remove excess dielectric material so top surfaces of STI  120  and DDSTI  130  are coplanar with top surface  105  of the substrate. Either STI  120  or DDSTI  130  may be formed fully formed first or the STI  120  and DDSTI  125  trenches may be formed separately and filled simultaneously. In the case of LDMOS devices, DDSTI is formed under the gate in the drain side of the LDMOS device. The values of D 3  and D 4  are chosen to optimize the speed of the high voltage device. 
     FIG. 1C  is a cross-section illustrating a first inter-device isolation scheme with a third intra-device isolation scheme according to embodiments of the present invention.  FIG. 1C  is similar to  FIG. 1A  except VSTI  125  of  FIG. 1A  is replaced with local oxidation of silicon (LOCOS)  135 . LOCOS  135  includes an upper region  137  extending above top surface  105  of substrate  100  and a lower region  139  extending a perpendicular distance D 5  from the top surface of the substrate into the substrate. D 1  is greater than D 5 . LOCOS is formed by masking regions of top surface  105  with a material such as silicon nitride and exposing the unmasked regions at many hundreds of degrees centigrade to oxygen or water steam. STI  120  is formed by etching a set of trenches, filling the trenches and performing a CMP as described supra. In one example, STI  120  is formed before LOCO  135 . In the case of LDMOS devices, LOCOS is formed under the gate in the drain side of the LDMOS device. The value of D 5  is chosen to optimize the speed of the high voltage device. 
     FIG. 1D  is a cross-section illustrating a first inter-device isolation scheme with a fourth intra-device isolation scheme according to embodiments of the present invention.  FIG. 1D  is similar to  FIG. 1A , except a CMP has been performed to remove upper portion  137  (see  FIG. 1D ) of LOCOS  140  making a top surface  142  of remaining of LOCOS  140  coplanar with top surface  105  of substrate  140 . In the case of LDMOS devices, the remaining LOCOS is formed under the gate in the drain side of the LDMOS device. Distance D 5  is now D 6  (D 6  less than or equal to D 5 ), as the possibility exists that some of the substrate may be removed by the CMP operation. 
     FIG. 2A  is a cross-section illustrating a second inter-device isolation scheme with the first intra-device isolation scheme according to embodiments of the present invention.  FIG. 2A  is similar to  FIG. 1A , except a deep trench isolation (DTI)  145  is formed through STI  120 . DTI  145  includes a polysilicon core surrounded by a dielectric layer  149 . In one example dielectric liner  149  is silicon oxide. In one example DTI  145  is formed by etching a trench through STI  120  into substrate  100 , forming a conformal dielectric layer on the bottom and sidewalls of the trench, filling the trench with polysilicon (e.g. using a chemical-vapor-deposition (CVD) process) and then performing a CMP process. DTI  145  extends a perpendicular distance D 7  from top surface  105  of substrate  100  into the substrate. D 7  is greater than D 2 . 
     FIG. 2B  is a cross-section illustrating the second inter-device isolation scheme with the second intra-device isolation scheme according to embodiments of the present invention.  FIG. 2B  is similar to  FIG. 1B , except DTI  145  is formed through STI  120 . DTI  145  extends a perpendicular distance D 7  from top surface  105  of substrate  100  into the substrate. D 7  is greater than D 3 . 
     FIG. 2C  is a cross-section illustrating the second inter-device isolation scheme with the third intra-device isolation scheme according to embodiments of the present invention.  FIG. 2C  is similar to  FIG. 1C , except DTI  145  is formed through STI  120 . DTI  145  extends a perpendicular distance D 7  from top surface  105  of substrate  100  into the substrate. D 7  is greater than D 5 . 
     FIG. 2D  is a cross-section illustrating the second inter-device isolation scheme with the fourth intra-device isolation scheme according to embodiments of the present invention.  FIG. 2D  is similar to  FIG. 1D , except DTI  145  is formed through STI  120 . DTI  145  extends a perpendicular distance D 7  from top surface  105  of substrate  100  into the substrate. D 7  is greater than D 6 . 
     FIG. 3A  is a cross-section illustrating a third inter-device isolation scheme with the first intra-device isolation scheme according to embodiments of the present invention.  FIG. 3A  is similar to  FIG. 1A , except a trench isolation (TI)  150  is formed through STI  120 . In one example TI  150  comprises TEOS oxide or HDP oxide. In one example, TI  150  is formed by etching a trench through STI  120  into substrate  100 , filling the trench with dielectric and then performing a CMP process. TI  150  extends a perpendicular distance D 8  from top surface  105  of substrate  100  into the substrate. D 8  is greater than D 2 . 
     FIG. 3B  is a cross-section illustrating the third inter-device isolation scheme with the second intra-device isolation scheme according to embodiments of the present invention.  FIG. 3B  is similar to  FIG. 1B , except TI  150  is formed through STI  120 . TI  150  extends a perpendicular distance D 8  from top surface  105  of substrate  100  into the substrate. D 8  is greater than D 3 . 
     FIG. 3C  is a cross-section illustrating the third inter-device isolation scheme with the third intra-device isolation scheme according to embodiments of the present invention.  FIG. 3C  is similar to  FIG. 1C , except TI  150  is formed through STI  120 . TI  150  extends a perpendicular distance D 8  from top surface  105  of substrate  100  into the substrate. D 8  is greater than D 5 . 
     FIG. 3D  is a cross-section illustrating the third inter-device isolation scheme with the fourth intra-device isolation scheme according to embodiments of the present invention.  FIG. 3D  is similar to  FIG. 1D , except TI  150  is formed through STI  120 . TI  150  extends a perpendicular distance D 8  from top surface  105  of substrate  100  into the substrate. D 8  is greater than D 6 . 
     FIGS. 4A ,  4 B and  5  illustrate types of devices that may be fabricated in second region  115 . While illustrated using the isolation structure illustrated in  FIG. 1A , it should be understood that the isolation structures illustrated in  FIGS. 1B ,  1 C,  1 D,  2 A,  2 B,  2 C,  2 D,  3 A,  3 B,  3 C and  3 D may be substituted. 
     FIG. 4A  is a cross-section of an exemplary first high power device that may be integrated with conventional devices according to embodiments of the present invention. In  FIG. 4A , a laterally double N-diffused MOS (NDMOS) device  155 A which is a type of LDMOS device includes a P-body  155 A and a N-well  160 A are formed on either side of a channel region  165 . Formed in P-body  155 A is a P type body contact  170  and an abutting N-type source. Formed in N-well  160 A is an N-type drain  180 A. P-body  155 A, N-well  160 A and channel region  165  are formed in an n-type doped N-tub  185  when substrate  100  is P-type. An electrically conductive gate  190  is formed over and electrically isolated from top surface  105  of substrate  100  by a gate dielectric  195 . Dielectric spacers  200  are formed on either sidewall of gate  190 . P-body  155 A extends under gate  190 . Source  175 A is separated from channel region  165  by P-body  155 A. N-well  160 A and VSTI  120  both extend under gate  190  with N-well  160 A separating VSTI  120  from channel region  165 . NDMOS device  155 A is electrically isolated by surrounding STI  120 . Body contact  170 A, P-body  155 A, drain  180 A and N-well  160 A all abut STI  120 . 
   In a reduced surface variant of NDMOS device  155 A, N-tub  185  is eliminated, the width of a now p-type channel region is reduced so P-body  155 A and N-well  160 A are brought much closer to each other and N-well  160 A abuts but does not extend under drain  180 A. In a reduced surface NDMOS (Resurf NDMOS) the N-well is called a drift region. 
     FIG. 4B  is a cross-section of an exemplary second high power device that may be integrated with conventional devices according to embodiments of the present invention. In  FIG. 4B , a laterally double P-diffused MOS (PDMOS) device  155 B is similar to NDMOS device  155 A of  FIG. 4A  except, an N-body  155 B replaces P-body  155 A, a P-well  160 B replaces N-well  160 A, an N-type body contact  170 B replaces P-type body contact  170 A, P-type source  175 B replaces N-type source  175 A and a P-type drain  180 B replaces B-type drain  180 A. 
   In a reduced surface variant of PDMOS device  155 B, N-tub  185  is eliminated, the width of a now p-type channel region is reduced so N-body  155 B and P-well  160 B are brought much closer to each other and P-well abuts but does not extend under drain  180 B. In a reduced surface PDMOS (Resurf PDMOS) the P-well is called a drift region. 
     FIG. 5  is a cross-section illustrating application of the present invention to a silicon-on-insulator substrate. In  FIG. 5 , a PDMOS device  155 C is similar to NDMOS device  155 A of  FIG. 4A  except, substrate  100  includes a buried oxide layer (BOX)  205  and NDMOS device  155 C is formed in a single-crystal silicon layer  210  formed on top BOX  205 . STI  120  abut BOX  205 . Substrate  100  is accordingly a silicon-on-insulator (SOI) substrate. A variant of transistor  255  includes a subcollector under collector  260 . 
     FIGS. 6 ,  7  and  8  illustrate types of devices that may be fabricated in first region  110 . While illustrated using the isolation structure illustrated in  FIG. 1A , it should be understood that the isolation structures illustrated in  FIGS. 1B ,  1 C,  1 D,  2 A,  2 B,  2 C,  2 D,  3 A,  3 B,  3 C and  3 D may be substituted. 
     FIG. 6  is a cross-section of an exemplary first conventional power device that may be integrated with the high power devices according to embodiments of the present invention. In  FIG. 6 , a field effect transistor (FET)  215  includes a source  220 , and a drain  225  separated by a channel region  230 , all formed in substrate  100 . An electrically conductive gate  235  is formed over and electrically isolated from top surface  105  of substrate  100  by a gate dielectric  240 . Dielectric spacers  245  are formed on either sidewall of gate  240 . Both source  220  and drain  225  extends under gate  245 . Both source  220  and drain  225  abut STI  120 . When source  220  and drain  225  are doped n-type and channel region  230  is doped p-type, FET  215  is a N-channel FET (NFET). When source  220  and drain  225  are doped p-type and channel region  230  is doped n-type, FET  215  is a PN-channel FET (PFET). 
     FIG. 7  is a cross-section of an exemplary second conventional power device that may be integrated with the high power devices according to embodiments of the present invention. In  FIG. 7 , a FET  250  is similar to FET  215  of  FIG. 6  except substrate  100  is an SOI substrate and includes a BOX layer  205 . STI  120  abut BOX  205 . Since source  220  and drain  225  abut BOX  205 , FET  250  is a fully depleted FET. In a variant, source  220  and drain  225  do not abut BOX  205 . 
     FIG. 8  is a cross-section of an exemplary third conventional power device that may be integrated with the high power devices according to embodiments of the present invention. In  FIG. 8 , a bipolar transistor  255  includes a collector  260 , a base  265  formed in the collector and an emitter  275  formed in the base. Collector  260  abuts STI  120 . And optional sub-collector  270  is formed under collector  260 . 
   Another type of bipolar transistor that may be formed in first region  110  is called a heterojunction bipolar transistor (HBT). HBTs utilize different semiconductors for the elements of the transistor. Usually the emitter is composed of a larger bandgap material than the base. This helps reduce minority carrier injection from the base when the emitter-base junction is under forward bias and increases emitter injection efficiency. The improved injection of carriers into the base allows the base to have a higher doping level, resulting in lower resistance to access the base electrode. A commonly used HBT is silicon-germanium (SiGe) with the SiGe used in the base. 
   It should be clear that conventional devices such a MOSFETs and bipolar transistors utilize one of STI, STI/DTI, or STI/TI only the LDMOS devices utilize one of STI, STI/DTI, or STI/TI in combination with VSTI, DDSTI or LOCOS. 
   Finally, it should be appreciated that any one or more of the devices illustrated in  FIGS. 4A ,  4 B, and  5  may be used with any one or more of the devices illustrated in  FIGS. 6 ,  7  and  8  with any of the isolation schemes illustrated in  FIGS. 1A ,  1 B,  1 C,  1 D,  2 A,  2 B,  2 C,  2 D,  3 A,  3 B,  3 C and  3 D. Thus, the present invention overcomes the deficiencies and limitations described supra by the use of different depths of isolation for inter and intra device isolation. 
   The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.