Abstract:
A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation. Rather, it uses the same voltage supply that is used to power the rest of the circuit. Accordingly, such an approach uses less area, consumes less power and has greater noise immunity.

Description:
RELATED APPLICATION(S) 
     This application is a divisional of U.S. application Ser. No. 09/241,496, filed Feb. 1, 1999, now U.S. Pat. No. 6,414,520. The entire teachings of the above application(s) are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     Generally speaking, computer systems typically include one or more central processor units (CPUs). In order to reduce power consumption and increase the performance of those CPUs, selected signals are operated in a “low voltage swing” manner. Low voltage swing signals typically represent digital data with a representative voltage that is less than the supply voltage (Vdd) level. Low swing voltage signals are typically generated in true/complement pairs, referred to as “differential” pairs. The prior art sense amplifiers operate by sensing the voltage differential between the true/complement pair to determine the logic level of the signal. 
     For example, the circuitry of a CPU may be powered by a Vdd supply voltage of 2.0 Volts. An associated pair of low voltage swing signals may develop a voltage differential of only +0.2 Volts to represent logic high data and −0.2 Volts to represent logic low data. Such low voltage swing signals can increase performance because the amount of time to generate a voltage differential of 0.8 Volts is significantly shorter than to transition that signal from 2.0 to 0 Volts. A signal that transitions from 2.0 to 0 Volts (i.e., from Vdd to Vss) is referred to as a “rail-to-rail” signal. 
     While low voltage swing signals present benefits to a CPU, they also add additional design requirements. For example, CPUs that employ low voltage swing signals, such as to represent data read from hardware registers, typically include amplifiers referred to as “sense amplifiers” for detecting the logic levels of those low voltage swing signals. When such a register is accessed, data that is stored therein is presented to the sense amplifier. That sense amplifier is designed to detect the logic levels of the low swing voltage signals and convert them to rail-to-rail voltage signals. Those rail-to-rail voltage signals can be input to other circuits that operate on the data, for example the CPU&#39;s floating point data store unit. 
     Such sense amplifiers are replicated many times in a typical CPU. Accordingly, the size of each device is critical to the total area used by such a CPU. Further, the chip real estate that each sense amplifier consumes reduces the total area available for other devices. 
     In the past, sense amplifiers have included at least two input stages connected to a corresponding number of data lines. Those input stages are connected to each signal of a true/complement or differential pair. The differential pairs are conveyed by wires across relatively large distances from the sourcing location to the destination location, e.g. the sense amplifier. Accordingly, those wires must be physically wide enough to present as little resistance as possible to the low swing voltage signals, such that the voltage levels are not degraded. Because those wires are connected to the inputs of each sense amplifier, they significantly increase the amount of real estate that is used by the floating point unit. 
     Prior art approaches to reducing the area of such sense amplifiers have used a reference voltage supply circuit. The reference voltage supply circuit is used as a reference to determine the logic level of an associated low voltage swing signal. Such an approach poses area, power consumption, process tracking and electrical noise concerns. 
     SUMMARY OF THE INVENTION 
     Generally, the sense amplifier of the present invention senses the logic level of data that is conveyed using a low voltage swing signal. The data is input to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation. Rather, it uses the same voltage supply that is used to power the rest of the circuit. Accordingly, the area used by the sense amplifier is significantly reduced. 
     More specifically, a method is provided for sensing an input voltage level of a data signal. Such a method involves pre-charging, and subsequently discharging, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a chip voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance (i.e., conductance capacity), it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharges is the fastest and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. 
     With such a structure, the data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized power supply for proper operation. Rather it uses the same power supply that is used to power the rest of the circuit. Accordingly, the area used by the sense amplifier is significantly reduced. 
     In a further aspect of the present invention, the discharge operation associated with one of the nodes, that is discharging at a faster rate, is allowed to continue while the discharge operation associated with the other node is terminated. Accordingly, the method allows the sensing operation to operate using a single data signal. Therefore, the semiconductor area that is used to practice the sensing operation is significantly reduced. 
     The input data signal may be a single low voltage swing signal. The sense amplifier may also include a pull-up unit coupled to the internal signal nodes for pulling the node that is discharged at a slower rate to a high logic level. 
     Further, the sense amplifier may include an evaluate unit, such as a transistor, connected to an electrical ground and to the pair of discharge paths for conveying the charge to electrical ground, and for initiating that conveyance when the input data signal achieves a voltage level that is capable of being resolved by the sense amplifier. 
     Further still, one of the discharge paths may include a pair of transistors connected in series by one of the internal signal nodes. That structure is connected in parallel with another, similar series connection of transistors. The input data signal is connected thereto. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. 
     FIG. 1 is a schematic drawing of a computer system including a central processing module, in which the present invention can be used; 
     FIG. 2 is a schematic diagram of the central processing module of FIG. 1; 
     FIG. 3A is a block diagram of the floating point register unit of the FBOX unit of the central processing unit of FIG. 2; 
     FIG. 3B is a more detailed block diagram of one portion of the floating point unit of FIG. 3A; 
     FIG. 4 is a functional block diagram of a sense amplifier according to the present invention; 
     FIG. 5 is a schematic diagram of a sense amplifier according to the present invention; 
     FIG. 6 is a flow diagram of the pre-charge operation of the sense amplifier of FIG. 5; 
     FIG. 7 is a flow diagram of the operation of the sense amplifier of FIG. 5, in response to data having a logic low level; 
     FIG. 8 is a flow diagram of a further operation of the sense amplifier of FIG. 5 in response to data having a logic high level; 
     FIG. 9 is a timing diagram of the operation of the sense amplifier of FIG. 5; 
     FIG. 10 is a block diagram of a physical layout of the sense amplifier of FIG. 5; and 
     FIG. 11 is a detailed diagram of the physical layout depicted in FIG.  10 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Generally, the sense amplifier of the present invention senses the logic value of digital data that is conveyed using a low voltage swing differential pair of signals. The digital data is input to the sense amplifier by a single low voltage swing wire. Accordingly, the area used by the sense amplifier is significantly reduced. 
     I. A Computer System 
     FIG. 1 is a schematic diagram of a computer system  10  that includes a central processing unit (CPU) module  12 , a memory system  14  and a PCI chip set  16  connected by a processor bus  18 . The PCI chip set  16  is further connected to an I/O system  20  and a co-processor module  22  by a system bus  24 . Central processing module  12  can include a number of sense amplifiers for use with low voltage swing signals according to the present invention. 
     Referring now to FIG. 2, central processing module  12  is shown to include a CPU  26 . A private address bus  27  and a private data bus  28  within CPU  26  connects a primary cache  29  and a system bus interface  31 . The private data bus  28  connects the CPU  26  to a backup cache (Bcache)  32  that, along with the primary cache  29 , is controlled by the Cache Control and Bus Interface unit  33 . 
     CPU  26  further includes several logic circuits that enable it to perform the major operations that the computer system  10  requires. The Ibox  34 , or Instruction Fetch and Decode Unit, controls instruction prefetching, instruction decoding, branch prediction, instruction issuance, and interrupt handling. The Ebox  35 , or Integer Execution Unit, handles the functions of addition, shifting, byte manipulation, logic operations, and multiplication for integer values stored in the system. These same operations, for floating point values, are controlled by the Fbox  36 , or Floating Point Execution Unit. The Mbox  37 , or Memory Address Translation Unit, translates virtual addresses, generated by programs running on the system, into physical addresses which are used to access locations in the computer system. Lastly, the Cbox  33 , or Cache Control and Bus Interface Unit, controls the primary cache  29  and backup cache  32 . It also controls the private data bus, private address bus, memory related external interface functions, and all accesses initiated by the Mbox  37 . 
     Each of the circuits mentioned above can include sense amplifiers to detect and latch logic levels of received data signals. Accordingly, sense amplifiers are widely used in many different areas of CPU module  12 . 
     II. Floating Point Register 
     FIG. 3A is a block diagram of the floating point register  40  of the Fbox unit  36 . The floating point register unit  40  includes sixty-six columns of memory locations  42   a  - 42   n . Referring now to FIG. 3B, one of those columns  42   a  is shown connected to a sense amplifier  44  by data — 1 signal line  46 . 
     Generally, when a read operation is initiated, the word line signal  62  that is associated with the desired memory locations is asserted. When a memory location, such as location  41   a , detects the assertion of the word line signal  62   a , transistor  200   a  IS responsively turned-on. The logic level of the data stored by the circularly connected inverters  200   c  and  200   d  causes transistor  200   b  to either turn-on or turn-off. Accordingly, a corresponding logic level is imposed on the data — 1 signal  46 . The data is conveyed to sense amplifier  44 . When the sense amplifier  44  senses that the data has been imposed on data — 1  46 , it responsively generates a rail-to-rail voltage on signals out_h  51  and out — 1  53 . Signals out_h  51  and out — 1  53  subsequently convey those rail-to-rail voltages to the floating point store data unit  48 . 
     III. An Inventive Sense Amplifier 
     Referring now to FIG. 4, a functional block diagram of sense amplifier  44  is shown to include pre-charge units  76  and  80  that are used for initializing or “pre-charging” the internal nodes ( 89 ,  90 , L 3 , L 3 X, L 6  and L 6 X, see FIG. 5) of sense amplifier  44  to predetermined logic values. Also, sense amplifier  44  includes a pair of discharge paths, the data low discharge path  72  and the data high discharge path  74 , connected to an evaluate unit  78  and to a pull-up unit  70 . 
     The pre-charge units are connected to a clock signal  86  and pre-charge the internal nodes ( 89 ,  90 , L 3 , L 3 X, L 6  and L 6 X) when that clock signal  86  transitions to a logic low level. Alternatively, when the clock signal  86  transitions to a logic high level, the pre-charge units are turned-off and the evaluate unit  78  is turned-on. Evaluate unit  78  allows current to flow from the data low discharge path  72  and from the data high discharge path  74 , to Vss or ground. 
     In prior art systems, the data low discharge path  72  and the data high discharge path  74  were capable of discharging equivalent amounts of current, and hence charge, in response to similar input voltage levels. Therefore, in order for one of those discharge paths to discharge an internal signal at a faster rate, its associated input voltage level would have to be greater than the input voltage level associated with the other discharge path. Accordingly, prior art sense amplifiers made use of a reference voltage that provided a selected input voltage level to the data low discharge path  72  which was intermediate to the logic high and low levels of the input data signal applied to the data high discharge path  74 . 
     If the input data signal developed a logic high level, the associated voltage level would be greater than the chosen reference voltage. Accordingly, the data high discharge path  74  would discharge at a faster rate than the data low discharge path  72 . Alternatively, if the input data signal developed a logic low level, the associated voltage level would be less than the chosen reference circuit voltage. Accordingly, the data high discharge path  74  would discharge at a slower rate than the data low discharge path  72 . In either case, the sense amplifier would thereafter generate a pair of rail-to-rail output signals in relation to the discharge path that discharged at the faster rate. 
     While such a sense amplifier is functionally adequate, the reference voltage circuits that are disposed therein are relatively large, consume substantial power and are susceptable to electrical noise. 
     In comparison to the prior art, the inventive sense amplifier  44  of FIG. 4 provides a significant reduction in the required amount of semiconductor area by using a simple connection to the Vdd power supply. That involves significantly less semiconductor area, consumes less power and has greater electrical noise immunity than the reference voltage circuit approach of the prior art. 
     The Vdd supply voltage can be utilized because the discharge paths  72  and  74  of sense amplifier  44  are capable of discharging different amounts of charge in response to similar input voltage levels. In one embodiment, the data high discharge path  74  is capable of discharging twice as much current as the data low discharge path  72 . Therefore, in order for the data high discharge path  74  to discharge an internal signal at a faster rate, its associated input voltage level does not have to be greater than the input voltage level associated with the data low discharge path  72 . Hence, the Vdd supply voltage that supplies the sense amplifier and the associated circuitry can be coupled to the data low discharge path  72  while providing the required level of functionality. 
     Accordingly, depending upon the logic level of data line  46 , one of the discharge paths  72  or  74  will allow current to flow at a faster rate. Responsively, one of the associated output signals,  89  or  90 , will be discharged at a faster rate. The signal  89  or  90  that discharges at the fastest rate will be detected and allowed to continue to discharge. The remaining signal  89  or  90  will be returned to Vdd by pull-up unit  70 . Signals  89  and  90  are inverted by inverters  82  and  84  to generate signals out_h  51  and out — 1  53 . Accordingly, the out — 1 signal  53  will contain a rail-to-rail voltage that has the same polarity as signal data — 1  46 , and out_h  51  will contain a rail-to-rail voltage that is the opposite polarity as signal data — 1  46 . For example, if data — 1  46  is at a logic low level, signal out — 1  53  will develop essentially the same voltage as Vss or ground. Also, signal out_h  51  will develop the same voltage as Vdd. 
     IV. Pre-Charge Operation 
     Referring now to the schematic diagram of FIG.  5  and the flow diagram of FIG. 6, the pre-charge operation of sense amplifier  44  will be described. Sense amplifier  44  returns to a reset or “pre-charge” state between each sensing operation (Step  100 ). For example, in the instant embodiment, sense amplifier  44  returns to such a pre-charge state between data read cycles. During such a pre-charge state, the input clock signal  86  remains at a logic low level (Step  102 ) and the data line  46  can be at any logic level. The clock signal  86  conveys the logic low level to the gates of PMOS transistors P 3  and P 4 , turning them “on” or, in other words, allowing current to flow from their source terminals (s) to their drain terminals (d) (Step  104 ). Also, NMOS transistor N 1  receives the clock signal  86  and is turned “off”(Step  106 ). When transistors P 3  and P 4  are turned on, output signal lines  89  and  90  are charged to approximately the same voltage as Vdd (Step  108 ). Output signal lines  89  and  90  are thereby pre-charged to logic high levels. 
     The logic level of output signal  90  is conveyed to the gate terminal of PMOS transistor P 1 , turning it off, and NMOS transistor N 8 , turning it on (Step  110 ). Also, the logic level on signal lines  89  is conveyed to the gate terminal of PMOS transistor P 2 , turning it off, and NMOS transistors N 7  and N 9 , turning them on (Step  112 ). The NMOS transistors that are turned-on allow nodes L 3 , L 6  and L 6 X to be pre-charged to logic high levels by PMOS transistors P 3  and P 4  (Step  114 ). The NMOS transistors remain on until the gate to source voltage (Vgs) of each transistor N 8 , N 9  and N 7  is less than the threshold voltage (Vt), or approximately 0.35 Volts (Step  116 ). 
     Further, because NMOS transistors N 2  and N 4  are turned-on, node L 7  is pre-charged to a logic high level, i.e. to a level of Vdd minus the threshold voltage V t  (Step  118 ). If data line  46  contains a logic high level, NMOS transistors N 3  and N 5  will also be turned-on and contribute to pre-charging node L 7 . Sense amplifier  44  is now referred to as being in a pre-charge state (Step  120 ). 
     Node L 3 X, and its associated transistors N 4  and N 6 , are included in sense amplifier  44  for balancing the amount of parasitic capacitance that is coupled onto output signal line  89  with the amount of parasitic capacitance that is coupled onto output signal line  90 . Without the inclusion of transistors N 4  and N 6 , the parasitic capacitance on output signal line  90  would differ from the amount of parasitic capacitance of output signal line  89  due to the number of transistors coupled thereto. Such an imbalance can cause differences in the charging and discharging rates of those signal lines. However, the present invention is not so limited and can operate without the addition of node L 3 X and its associated transistors. 
     V. Sense Amplifier Operation: Data — 1 Transition 
     Referring now to the schematic diagram of FIG.  5  and the flow diagram of FIG. 7, the operation of sense amplifier  44  will be shown in response to signal data — 1  46  transitioning from a logic high level to a logic low level. Assuming that signal data — 1  46  is initially pre-charged to a logic high level, data will be read from a memory location  42   a  that will cause data — 1  46  to transition to a logic low level (Step  122 ). After data line  46  has reached a logic low level that can be sensed by sense amplifier  44 , clock signal  86  will transition to a logic high level (Step  124 ). That logic high level is conveyed to PMOS transistors P 3  and P 4 , turning them off, and to NMOS evaluate transistor N 1 , turning it on (Step  126 ). Because evaluate transistor N 1  has its source terminal connected to Vss (ground), node L 7  begins to discharge to a logic low level (Step  128 ). 
     At this point in the read cycle, NMOS transistors N 3  and N 5  are “weakly” turned-on since signal data — 1  46  does not have as high of a voltage level as Vdd (Step  130 ). However, NMOS transistors N 4  and N 2  are strongly turned-on and can conduct more current than transistors N 3  and N 5  (Step  132 ). Transistors N 4  and N 2  are referred to as being “strongly” turned-on because the Vdd supply voltage is applied to their gate terminals and the voltage on node L 7  is discharging. Responsively, node L 3  begins to discharge at a faster rate than nodes L 6  and L 6 X (Step  134 ). Also, output signal  89  discharges through NMOS transistors N 8 , N 2  and N 1  faster than signal  90  can be discharged (Step  136 ). The difference in those discharge rates allows output signal  89  to reach a logic low level before output signal  90  can reach a logic low level. Responsively, NMOS transistors N 7  and N 9  are turned-off by output signal  89  before NMOS transistor N 8  can be turned-off by output signal  90  (Step  138 ). Therefore, the discharging of output signal  90  will be halted when transistors N 7  and N 9  are turned-off (Step  140 ). 
     In addition, the logic low level on output signal  89  turns-on PMOS transistor P 2  which pulls-up signal  90  to a logic high level (Step  142 ). Because transistor P 1  remains off, output signal  89  will continue falling to a logic low level, such as to the Vss level (Step  144 ). Thereafter, output signals  89  and  90  will be inverted by inverters  82  and  84  to generate a logic high level on signal out_h  51  and a logic low level on signal out — 1  53  (Step  146 ). It should be noted that those resulting output signals are rail-to-rail voltage signals. 
     VI. Sense Amplifier Operation: Data_h Transition 
     Referring now to the flow diagram of FIG. 8, the operation of sense amplifier  44  will be described in response to signal data — 1  46  remaining at a logic high level. For illustration purposes, consider that the sense amplifier  44  has again been returned to the reset or pre-charge state in the manner previously described (see FIG. 6) (Step  120 ). When sense amplifier  44  is in such a pre-charge state, the input clock signal  86  is at a logic low level. 
     While data signal  46  is at a logic high level, the clock signal  86  transitions from a logic low level to a logic high level (Step  152 ). The clock signal  86  conveys the logic high level to the gate of PMOS transistors P 3  and P 4 , turning them off (Step  154 ). Also, clock signal  86  turns-on NMOS evaluate transistor N 1  (Step  156 ). Because evaluate transistor N 1  has a source terminal connected to Vss, node L 7  discharges to a logic low level (Step  158 ). 
     At this point in the cycle, NMOS transistors N 3  and N 5  are turned on “strongly” since data line  46  has approximately the same voltage level as Vdd (Step  160 ). Also, NMOS transistors N 4  and N 2  are also strongly turned-on (Step  162 ). Therefore, nodes L 3 , L 3 X, L 6  and L 6 X can discharge through NMOS transistors N 2 , N 3  and N 5  at approximately the same rate. However, because NMOS transistor N 6  is turned-off, output signal  89  can only discharge through NMOS transistors N 8 , N 2  and N 1 . Alternatively, output signal  90  can discharge through NMOS transistors N 9 , N 3 , N 7 , N 5 , and N 1 . Since transistors N 2 -N 9  in sense amplifier  44  have the same width, twice as much current can flow through transistors N 9 , N 3 , N 7 , N 5  and N 1 , i.e., that construct the data high discharge path  74  and the evaluate unit  78  (Step  164 ). 
     Accordingly, output signal  90  discharges at a faster rate than output signal  89 . The differences in the discharge rates allow NMOS transistor N 8  to be turned-off by the logic level of output signal  90  before NMOS transistors N 9  and N 7  can be turned-off by output signal  89  (Step  166 ). Therefore, the discharging of output signal  89  through transistors N 8 , N 2  and N 1  will be halted (Step  168 ). In addition, when output signal  90  is discharged to a logic low level, PMOS transistor P 1  is turned-on and pulls output signal  89  to a logic high level (Step  170 ). Output signal  90  continues falling to the Vss voltage level (Step  172 ). Thereafter, output signals  89  and  90  are inverted by inverters  82  and  84  to generate a logic high level on signal out — 1  53  and a logic low level on signal out_h  51  (Step  174 ). 
     It should be noted that in the present embodiment, each transistor includes equivalent widths. Since the rate at which a particular discharge path,  72  or  74 , discharges is also related to the size of the associated transistors, equivalent circuits could be implemented that include transistors that include different widths. Further, the order of the transistors within each discharge path  72  and  74  can be exchanged without affecting the operation of the sense amplifier  44 . 
     Referring briefly to the timing diagram of FIG. 9, the timing waveforms of signals clock  86 , data — 1  46 , output signal  90  and output signal  89  are related to the corresponding operational steps of FIGS. 7 and 8. 
     VII. Sense Amplifier Layout 
     Referring now to FIG. 10, a high level physical layout of the NMOS portion of sense amplifier  44  is shown to include several areas  176 - 180 . The first area  176  is referred to as the “N-diffusion” area and includes only N-type semiconductor material for forming the NMOS transistors N 1 -N 9 . The areas associated with signal lines CLK  86 , output signal  90 , output signal  89  and VSS represent diffused polysilicon material. Those diffusions of polysilicon material construct the gate terminals of NMOS transistors N 1 -N 9 . Further, areas  178  and  180  are referred to as “moveable window” areas. The locations of moveable window areas  178  and  180  can be tailored to change the sizes of NMOS transistors N 2 -N 9  in relation to each other. Adjusting the sizes of transistors N 2 -N 9 , will set the sense amplifier&#39;s “trip point”, i.e. the voltage above which inputs are considered to be a logic high and below which inputs are considered to be a logic low. 
     Referring now to FIG. 11, the N-diffusion area  176  is shown in greater detail. Each NMOS transistor N 2 -N 9 , and the polysilicon diffusion areas corresponding to signal lines CLK  86 , output signal  90 , output signal  89  and VSS are identified in relation to the moveable window areas  178  and  180 . For example, transistors N 3  and N 9  are disposed along one edge of moveable window area  178 , and transistors N 5  and N 7  are disposed along the opposing edge of moveable window area  178 . Further, transistors N 2  and N 8  are disposed along one edge of moveable window area  180 , and transistors N 4  and N 6  are disposed along the opposing edge of moveable window area  180 . Adjustments that are made to the location of moveable window areas  178  and  180  will affect the relative size of transistors N 2 -N 9  and are used to adjust the trip point of sense amplifier  44 . 
     The location of moveable window areas  178  and  180  can be shifted up or down in the y-axis direction. Accordingly, when moveable window areas  178  and  180  are shifted in the positive y-axis direction, the size of transistors N 2 , N 8 , N 3  and N 9  are reduced and the size of transistors N 4 , N 6 , N 5  and N 7  are correspondingly increased. Likewise, when moveable window areas  178  and  180  are shifted in the negative y-axis direction, the size of transistors N 2 , N 8 , N 3  and N 9  are increased and the size of transistors N 4 , N 6 , N 5  and N 7  are correspondingly decreased. 
     The trip point of sense amplifier  44  can be defined in terms of the relative sizes of transistors N 7 , N 8  and N 9 . The following empirical relation equates the size of transistor N 8  to the voltage on the data signal  46  that must be attained before a logic low level can be sensed. It should be noted that this equation should be scaled according to the process used to make the transistors. 
     Voltage (% of Vdd) Size Relationship 
     A percentage of Vdd (N 8 /(N 7 +N 9 ))=((desired logic low level/Vdd*1.1111)+0.2 Accordingly, for sense amplifier  44  to be able to sense that a certain voltage on data signal  46  represents a logic low level, the sizes of transistors N 7 , N 8  and N 9  should conform to the specified relationship. For example, assume that Vdd is 2.0 Volts and that it is desired that a voltage of 1.0 Volts (50% of Vdd) should be sensed as a logic low level. Therefore, in order for sense amplifier  44  to detect that voltage as a logic low level, the ratio of transistor sizes, N 8 /(N 7 +N 9 ), should equate to ((1.0V/2.0V)*1.1111) +0.2 or 0.711. Accordingly, it will be recognized that selecting the trip point of sense amplifier  44  by adjusting the locations of moveable window areas  178 - 180  is less complex than individually re-sizing each transistor. 
     VIII. Alternative Embodiments 
     It will be recognized by one of ordinary skill in the art that the functionality of the inventive sense amplifier will be preserved if the NMOS and PMOS transistor types are exchanged, along with the polarity of the associated logic signals. Further, the sense amplifier of the present invention is not limited to the present embodiment. To the contrary, the instant sense amplifier can be used in any circuit or application that utilizes a sense amplifier such that similar performance can be retained while significantly reducing the required amount of CPU or chip real estate. Such circuits can include edge-triggered latches and flip flops. 
     While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.