Abstract:
A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) latch capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state ( 0  or  1 ) of the comparator, hysteresis is generated by adding or subtracting a first charge stored in the latch intrinsic capacitance to or from a second charge stored in the sampling capacitor. The ratio of latch intrinsic capacitance and the capacitance of the sampling capacitor can be adjusted to trim hysteresis value. The hysteresis function does not require additional capacitors or additional logic.

Description:
TECHNICAL FIELD 
       [0001]    This application is related generally to electronic devices, and more particularly to comparators with programmable hysteresis. 
       BACKGROUND 
       [0002]    In many applications, comparators only function over a portion of a time period. Such circuits are driven by a clock and have a first (sampling) phase when the comparator output is not available and a second (amplifying) phase when the comparator output is available. Some of these comparators can include one or more preamplifier stages followed by a latch stage. When a low offset is required, the preamplifier stage(s) can build up an input voltage difference to a sufficiently large value and then apply the input voltage to the latch stage to decrease the effect of latch offset. When low power is required, a dynamic latch can be used. 
         [0003]    The conventional comparator described above works well for some applications. However, when a very low operational current (e.g., 100 nA) and hysteresis are required, the linear preamplifier stage(s) cannot be used. 
       SUMMARY 
       [0004]    A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state ( 0  or  1 ) of the comparator, hysteresis is generated by adding or subtracting a first charge stored in the latch intrinsic capacitance to or from a second charge stored in the sampling capacitor. The ratio of latch intrinsic capacitance and the capacitance of the sampling capacitor can be adjusted to trim hysteresis value. The hysteresis function does not require additional capacitors or additional logic. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a schematic diagram of a comparator in a sampling state. 
           [0006]      FIG. 2  is a schematic diagram of the comparator of  FIG. 1  in an amplifying state. 
           [0007]      FIG. 3  is a schematic diagram of an example low current comparator with programmable hysteresis in a sampling and amplification state. 
           [0008]      FIG. 4  is a schematic diagram of the low current comparator of  FIG. 3  in a level shift and latch discharge state with no hysteresis. 
           [0009]      FIG. 5  is a schematic diagram of the low current comparator of  FIG. 3  in a level shift and latch pre-charge state with hysteresis. 
           [0010]      FIG. 6  illustrates example waveforms for controlling the state of the low current comparator of  FIGS. 3-5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]      FIG. 1  is a schematic diagram of a comparator  100  operating in a sampling phase. The comparator  100  includes a linear preamplifier  102  coupled to a dynamic latch  104  through switches S 1  and S 2 . Capacitors cp 1  and cp 2  are gate_to_drain capacitors of MOS transistors M 1 , M 3  and M 2 , M 4 , respectively. During a sampling phase (phs 1 =1, phs 2 =0), the input signal between inp and inn is continuously amplified. The differential outputs inn 1 , inp 1  of the preamplifier  102  are applied to the inputs of the dynamic latch  104  through switches S 1  and S 2 . Power switches S 3 , S 4  are open. As M 1 , M 3  and M 2 , M 4  inverters are cross connected and S 3 , S 4  power switches are open, the outputs of preamplifier  102  are applied to an equivalent capacitor equal to cp 1 +cp 2  during the sampling phase, creating a voltage difference between outp and outn. 
         [0012]      FIG. 2  is a schematic diagram of the comparator  100  operating in an amplifying phase. During the amplifying phase (phs 1 =0, phs 2 =1), the inputs of dynamic latch  104  are disconnected from the outputs of preamplifier  102  by opening switches S 1  and S 2 . The charge stored in cp 1 , cp 2  and the voltage difference between outp and outn remains. Then, power switches S 3  and S 4  are closed, and the dynamic latch  104  formed by transistors M 1 , M 3  and M 2 , M 4  cross coupled inverters enters an unstable state and the outputs outp, outn of comparator  100  flip to 0,1 or 1,0, depending on a voltage difference polarity at the end of the previous sampling period. 
         [0013]      FIG. 3  is a schematic diagram of an example low current comparator  300  with programmable hysteresis in a sampling and amplification state. In comparator  300 , the preamplifier has been removed. In place of the preamplifier, the comparator  300  includes a sampling input stage  302  and a dynamic latch output stage  304 . The input and output stages  302 ,  304  are operatively coupled by switches S 1  and S 2 . In some implementations, the sampling input stage  302  is a switched capacitor structure that includes sampling capacitors C 1  and C 2  and switches sa, sb, sc, S 1  and S 2 . The dynamic latch output stage  304  includes transistors M 1 , M 2 , M 3 , M 4 , and switches S 3 , S 4 , S 5 . The transistors M 1  through M 4  are shown in a cross-coupled inverter arrangement. The dynamic latch output stage  304  has intrinsic gate to drain capacitance cp 1  and cp 2 . 
         [0014]    The operating state of comparator  300  is controlled by three-phase, non-overlapped clocks: Phs 1 , Phs 2  and Phs 3 . The waveforms for these clocks are shown in  FIG. 6 . During a first phase (e.g., phs 1 =1), inp and inn input signals are sampled in C 1 ,C 2  serial capacitors and through sa and sb switches. Since switch sc is open, the capacitors C 1 , C 2  are coupled to inn 1  and inp 1  and to a common node (“com”). The common node Com is floating and biased to [v(inp)+v(inn)]/2. The voltage difference across inp 1  and inn 1  is δvin. During the same phase, S 3  and S 4  power switches are closed, switch S 5  is opened, and the dynamic latch  304  formed by M 1 , M 3  and M 2 , M 4  cross-coupled inverters transitions to an unstable state. The outputs outp and outn of comparator  300  flip to 0,1 or 1,0 depending on a voltage difference polarity at the end of a previous sampling period. 
         [0015]      FIG. 4  is a schematic diagram of the low current comparator of  FIG. 3  in a level shift and latch discharge state with no hysteresis. During a second phase (e.g., phs 2 =1), sampling capacitors C 1 ,C 2  are disconnected from inp and inn by opening switches sa, sb, switch sc is closed, and the common node is biased to vref voltage (e.g., vref=Vcc/2). If no hysteresis is needed, power switches S 3  and S 4  are opened, switch S 5  is closed, and the charge stored in the latch intrinsic capacitance cp 1 +cp 2  is discharged to 0, resulting in v(outp)=v(outn). If hysteresis is needed, switch S 5  remains open and a Qh=+−Vcc*(cp 1 +cp 2 ) charge is maintained inside cp 1 +cp 2 , then v(outp)−v(outn) remains to +−Vcc, depending on the output value of comparator  300 . 
         [0016]      FIG. 5  is a schematic diagram of the low current comparator  300  of  FIG. 3  in a level shift and latch pre-charge state with hysteresis. During a third phase (e.g., phs 3 =1), switch S 5  is opened, switches S 1 ,S 2  are closed and the latch intrinsic capacitor (cp 1 +cp 2 ) is charged by sampling capacitors C 1 , C 2  (hereinafter referred to as “C 12 ”). Depending on hysteresis selection, the voltage v(outp)−v(outn) across cp 1 +cp 2  is given by 
         [0000]      δvout1=δvin* C 12/( C 12+ cp 1+ cp 2),   (1)
 
         [0017]    where C 12 =C 1 *C 2 /(C 1 +C 2 ), if the no-hysteresis mode is selected, and 
         [0000]      δvout2=(δvin* C 12− Qh )* C 12/( C 12+ cp 1+ cp 2)   (2)
 
         [0018]    with Qh=+−Vcc*(cp 1 +cp 2 ), if the hysteresis mode is selected. In the latter case, δvout 2  depends on the comparator&#39;s previous state, which generates a comparator hysteresis given by 
         [0000]        Hys= 2* Vcc *( cp 1+ cp 2)* C 12/( C 12+ cp 1+ cp 2)=2* Qh*C 12/( C 12+ cp 1+ cp 2).   (3)
 
         [0019]    As shown in Equation [2], the ratio of the latch intrinsic capacitance (cp 1 +cp 2 ) and the sampling capacitance (C 12 ) can be used to adjust hysteresis. During a third phase (Phs 3 =1), the ratio can be used to add or subtract a charge stored in the latch intrinsic capacitance cp 1 +cp 2 , during an amplifying phase (Phs 1 =1). This charge will be added to the charge stored in the C 12  capacitor during the first phase, if v(inp)−v(inn) has the same polarity compared to the polarity present in the previous amplifying phase. The charge will be subtracted from the charge stored in the C 12  capacitor during the first phase if v(inp)−v(inn) has an opposite polarity compared to the polarity present in the previous amplifying phase. 
         [0020]      FIG. 6  illustrates example waveforms for controlling the state of the low current comparator  300  of  FIGS. 3-5 . At the top of  FIG. 6 , the three phased clocks (Phs 1 , Phs 2 , Phs 3 ) are shown over seven time periods T 1 -T 7 . As previously described, these three clocks can be used to open or close the various switches in the comparator  300 . Waveforms are also shown for inputs inp, inn, Inp 1 , Inn 1 , common node com, outputs outp, outn, and clock Phsh for opening and closing switch S 5 . In the no-hysteresis mode, v(outp-outn) polarity changes when vinp=vinn. In the hysteresis mode, v(outp−outn) polarity changes when v(vip−vin)&gt;Hys/2 or v(vip−vin)&lt;−Hys/2.