Abstract:
An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.

Description:
BACKGROUND 
       [0001]    1. Field of Invention 
         [0002]    The invention generally relates to an integrated circuit. Furthermore, the invention also relates to a corresponding manufacturing method for an integrated circuit. 
         [0003]    2. Related Art 
         [0004]    Floating gate transistors are commonly used for non-volatile storage such as NAND flash devices and NOR flash devices to store the charge of one or more bits per floating gate transistor in the associated floating gate. The floating gate is mounted above an active area of substrate silicon which forms the transistor channel and is separated from the substrate by a tunnel dielectric. 
         [0005]    There is a need to provide flash memories with a high density of floating gate transistors at relative low costs and with a reasonable good functionality of the floating gate transistors. 
       SUMMARY 
       [0006]    An integrated circuit is described. The integrated circuit may include a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. 
         [0007]    Furthermore, a manufacturing method for an integrated circuit is described. The manufacturing method may include: depositing an insulation layer on a semiconductor substrate; depositing at least one layer of floating-gate electrode material on the insulation layer, the at least one layer of floating-gate electrode material comprising a transition metal; forming a multitude of floating-gate electrodes of the at least one layer of floating-gate electrode material, wherein at least one the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width. 
         [0008]    Other systems, methods, features and advantages of the invention will be or will become apparent to one with skills in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0009]    The invention can be better understood by referring to the following figures. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views. 
           [0000]    In the figures: 
           [0010]      FIGS. 1A-1E  show cross sections of a semiconductor structure for illustrating a manufacturing method for an integrated circuit; 
           [0011]      FIGS. 2A-2D  show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method; 
           [0012]      FIGS. 3A ,  3 Ba,  3 Bb and  3 C show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method; 
           [0013]      FIGS. 4A  and B show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method; 
           [0014]      FIGS. 5A-5C  show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method; 
           [0015]      FIGS. 6A ,  6 Ba and  6 Bb show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method; 
           [0016]      FIGS. 7A-7F  show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method; 
           [0017]      FIGS. 8A-8F  show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    In the following description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration one or more specific implementations in which the technology may be practiced. It is to be understood that other implementations may be utilized and structural changes may be made without departing form the scope of this technology. 
         [0019]      FIGS. 1A-1E  show cross sections of a semiconductor structure for illustrating a manufacturing method for an integrated circuit. 
         [0020]    First, a method of producing a multilayer semiconductor structure (PMSS-method) is carried out. In a first process step of the PMSS-method, an insulation layer  12 , for example a silicon oxide layer is formed on a surface of a semiconductor substrate  10 . In case that the semiconductor substrate  10  includes silicon, the silicon oxide layer may be formed for instance during a thermal oxidation step. However, the pre-sent technology is not restricted to silicon oxide to provide the insulation layer  12 . Various other insulating materials may also be deposited on the semiconductor substrate  10  to provide the insulation layer  12 . The layer thickness of the insulation layer  12  may be about 10 nm. 
         [0021]    A layer of a conductive material  14  is deposited on the insulation layer  12 . The layer thickness of the layer of a conductive material  14  may be in a range between 10 nm to 30 nm. The layer of a conductive material  14  may comprise polysilicon, a metal, a transition metal or a transition metal compound. In the present example, the layer of a conductive material  14  includes polysilicon. In a subsequent process step, a transition metal layer  16  is deposited on the layer of a conductive material  14 . The transition metal layer  16  may include iridium, ruthenium, a transition metal oxide, a transition metal silicide, a transition metal boride, a transition metal aluminide, a transition metal carbide and/or a transition metal nitride. For instance, the transition metal layer  16  may include iridium oxide, ruthenium oxide, tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, cobalt silicide, zirconium silicide, hafnium silicide, niobium silicide, tungsten nitride, titanium nitride, tantalum nitride, hafnium nitride and/or zirconium nitride. Of course, the transition metal layer  16  may include at least two of the materials listed above. The transition metal layer  16  may have a layer thickness between 20 nm to 100 nm. The transition metal of transition metal layer  16  may have a different etch rate than the material of the layer of a conductive material  14 . 
         [0022]    The layer of a conductive material  14  and/or transition metal layer  16  are formed for instance by a chemical vapour deposition (CVD) or by a physical vapour deposition (PVD). The materials of the layers  14  and  16  may react with each other. Thus, the interface between the layers  14  and  16  may not be flat. Instead, the interface between the layers  14  and  16  may have peaks and/or trenches. However, the present technology in not restricted to a non-flat interface between the layers  14  and  16 . 
         [0023]    An oxide layer  18  and a nitride layer  20  are formed on the transition metal layer  16 . The semiconductor structure produced by the PMSS-method is shown in  FIG. 1A . 
         [0024]      FIG. 1B  shows the result of a method of etching trenches (ET-method) into the semiconductor structure of  FIG. 1A . The ET-method starts with the process step of depositing a (not shown) first mask on the surface of the semiconductor structure. The first mask is for instance a carbon hard mask. The mask is structured to expose those areas of nitride layer  20  that cover the sites of (later etched) trenches  22   a . This may be done for example by a lithographic step. Then, a reactive ion etch (RIE) step is carried out to etch trenches  22   a  into the semiconductor structure. The RIE step is stopped when the bottoms of the trenches  22   a  are within a distance s 1  from the interface of the layers  14  and  16 . The distance s 1  may be in a range between 5 nm to 20 nm. Then the ET-method ends. 
         [0025]    An isotropic etch step is carried out to increase the width of the trenches  22   a . This isotropic etch step is performed with an etching material that etches the exposed material of the transition metal layer  16  and the oxide layer  18 . However, the nitride of layer  20  is not sensitive against the etching material. To protect the nitride layer  20  further, the first mask is kept on the nitride layer  20  during the isotropic etch step. After the isotropic etch step, the first mask may be removed. The newly formed trenches  22   b  are shown in  FIG. 1C . 
         [0026]    A method of forming nitride spacers (FNS-method) to cover the sidewalls of the trenches  22   b  is carried out. First, the trenches  22   b  are filled with nitride. Then, a second (not shown) mask is deposited on the nitride layer  20  and structured. In a subsequent process step, an anisotropic etch step is performed to remove the nitride partially from the trenches  22   b . This anisotropic etch step is continued till the bottoms of the trenches  22   b  are exposed. However, due to the anisotropy of this etch step, the nitride covering the sidewalls of the trenches  22   b  is not attacked more than tolerable. Thus, the nitride spacers  24  shown in  FIG. 1C  are formed. 
         [0027]    A second RIE step is carried out to increase the depth of the trenches  22   b . The nitride spacers  24  covering the sidewalls of the trenches  22   b  are not sensitive against this second RIE step. Therefore, the sidewalls of the trenches  22   b , which are protected by the nitride spacers  24 , are not damaged by this second RIE step. The second mask is removed after the second RIE step. 
         [0028]    The result of this second RIE step are trenches  22   c , which extend from the surface of the semiconductor structure into the semiconductor substrate  10 , as can be seen from  FIG. 1D . The depths of the trenches  22   c  is in a range between 100 nm to 300 nm. The trenches  22   c  have a lower width d 2  which is significantly smaller than the upper width d 1 . For instance, the lower width d 2  is in a range between 50 nm to 100 nm while the upper width d 1  is in a range between 100 nm to 200 nm. 
         [0029]    In the interspaces of the trenches  22   c  newly formed floating-gate electrodes FG are arranged. Each of these floating-gate electrodes FG includes a lower part  26  formed of the layer of a conductive material  14  and an upper part  28  formed of the transition metal layer  16 . The lower part  26  has a column-like shape. The upper part  28  has an inverse T-shape, because its width decreases in the direction to the oxide layer  18 . Upper width d 3  of the upper part  28  may be in a range between 10 m to 30 nm. Lower width d 4  of the upper part  28 , which is also the width of the lower part  26 , may be in a range between 50 nm to 100 nm. 
         [0030]    A floating-gate electrode FG with an inverse-T shape or a triangular shape may provide a reduced interaction, i.e. electrical coupling, between the floating-gate electrode FG and an adjacent floating-gate electrode FG associated with another wordline WL. The interaction between the floating-gate electrode FG and its associated control-gate electrode CG may not be limited due to the inverse-T shape of the floating-gate electrode FG. 
         [0031]    Due to the small value of the upper width d 3 , the upper part  28  of each of the floating-gate electrodes FG includes a transition metal. The low resistivity of the transition metal decreases the risk of depletion. However, to provide a conventional dielectric interface structure, the lower part  26  of each of the floating-gate electrodes FG includes polysilicon. 
         [0032]    The trenches  22   c  are filled with a STI-fill  30  according to the following STI-method. First, the STI-fill-material is deposited on the semiconductor structure. Then, a chemical mechanical polishing (CMP) step is carried out to remove those parts of the STI-fill-material that protrude above the nitride spacers  24 . Further, the STI-fill  30  is etched back to a level that is within the distance s 1  from the interface of the lower part  26  and the upper part  28 . 
         [0033]    In a wet chemical etch step, for instance with hot phosphoric acid, the nitride layer  20  and the nitride spacers  24  are completely removed. However, the oxide layer  18  is not sensitive against hot phosphoric acid. Thus, oxide spacers  32  are left on the floating-gate electrodes FG, as can be seen from  FIG. 1D . 
         [0034]    A method of forming control-gate CG electrodes and wordlines WL (FCW-method) on the semiconductor structure of  FIG. 1D  is performed. 
         [0035]    A layer of coupling dielectric material  34 , for instance an oxide, is deposited on the surface of the semiconductor structure. Then, a layer of control-gate material  36 , for example polysilicon, is deposited on the layer of coupling dielectric material  34  to form control-gate electrodes CG. In an additional step of the FCW-method, the material of the wordlines WL is deposited on the layer of control gate material  36 . In the example of  FIG. 1E , the wordlines WL include a tungsten nitride layer  38  and a tungsten layer  40 . 
         [0036]    To provide an additional insulation between the floating-gate electrodes FG and the layer of control-gate material  36 , the oxide spacers  32  are arranged on the top of the floating-gate electrodes FG. Due to the small upper width d 3  of the floating-gate electrodes FG, a relative strong electrical field may occur at the peak-like upper end of each of the floating-gate electrodes FG. To provide an additional insulation on the peak-like upper end of each of the floating-gate electrodes FG is a good way with regard to the strong electrical field. 
         [0037]    As an alternative to the floating-gate electrodes FG formed of polysilicon and a metallic material, the floating-gate electrodes FG may be formed only of the transition metal layer  16 . In this case, no layer of a conductive material  14  is deposited on the insulation layer  12  and the transition metal layer  16  may have a layer thickness which is in a range between 50 nm to 100 nm. Furthermore, the layer of a conductive material  14  may include TaN and the transition metal layer  16  may include tungsten. Thus, floating-gate electrodes FG are provided that have a lower subunit of TaN and an upper subunit of tungsten. 
         [0038]      FIGS. 2A-2D  show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method. 
         [0039]    The PMSS-method is carried out to produce the semiconductor structure shown in  FIG. 2A . The semiconductor structure has a semiconductor substrate  10 , an insulation layer  12 , a transition metal layer  50  and a nitride layer  20 . The transition metal layer  50  may include at least one of the materials iridium and/or ruthenium. Of course, the transition metal layer  50  may also include a transition metal oxide, a transition metal silicide, a transition metal boride, a transition metal aluminide, a transition metal carbide and/or a transition metal nitride. For example, the transition metal layer  50  may include at least one of the materials: iridium oxide, ruthenium oxide, tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, cobalt silicide, zirconium silicide, hafnium silicide, niobium silicide, tungsten nitride, titanium nitride, tantalum nitride, hafnium nitride and/or zirconium nitride. The transition metal layer  50  may have a layer thickness between 50 nm to 100 nm. The variety of the materials suited for the insulation layer  12  is mentioned above. 
         [0040]    The ET-method is performed to etch trenches  52  into the semiconductor structure of  FIG. 2A . The ET-method is stopped when the newly etched trenches  52  extend from the surface of the semiconductor structure into the semiconductor substrate  10 . The total height h 1  of the trenches  52  is in a range between 250 to 350 nm. 
         [0041]    The trenches  52  are filled with an STI-fill  30  according to the STI-method. The surface of the STI-fill  30  is within a distance s 2  from the interface between the insulation layer  12  and the transition metal layer  50 , as can be seen from  FIG. 2B . The distance s 2  may be in a range between 10 nm to 30 nm. 
         [0042]    Nitride layer  20  is removed by an etching step with hot phosphoric acid. In a following process step, an isotropic etch step is carried out to form floating-gate electrodes FG of the transition metal layer  50 . However, this isotropic etch step is performed with an etching material which does not attack the STI-fill  30 . The result of the isotropic etch step is shown in  FIG. 2C . The newly formed floating-gate electrodes FG have an inverse-T shape with an upper width d 3  between 10 nm to 50 nm and a lower width d 4  between 30 nm to 100 nm. 
         [0043]    The STI-fill  30  protruding above the interspaces between the floating-gate electrodes FG is etched away. Then, the FCW-method is repeated to form control-gate electrodes CG and wordlines WL. Thus, the semiconductor structure shown in  FIG. 2D  is produced. 
         [0044]    Of course, it is also possible to form floating-gate electrodes FG according to the method mentioned above from two layers of different materials. In this case, the lower layer may be a polysilicon layer and the upper layer may be a transition metal layer. 
         [0045]      FIGS. 3A ,  3 Ba,  3 Bb and  3 C show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method. 
         [0046]    The PMSS-method is carried out to form a semiconductor structure comprising a semiconductor substrate  10 , an insulation layer  12 , a layer of floating-gate electrode material  60 , an oxide layer  18  and a nitride layer  20 . The layer of floating-gate electrode material  60  may include polysilicon and/or at least one transition metal. For example, the layer of floating-gate electrode material  60  may include iridium, ruthenium, a transition metal oxide, a transition metal silicide and/or a transition metal nitride. Furthermore, the layer of floating-gate electrode material  60  may include a first layer of polysilicon and at least one second layer of a transition metal. 
         [0047]    The ET-method is performed to etch trenches  52 . The total height h 1  of these trenches  52  may be in a range between 250 nm to 350 nm. The trenches  52  are filled with a STI-fill  30  according to the STI-method. The STI-fills  30  have a surface within a distance s 2  from the interface of the insulation layer  12  and the layer of floating-gate electrode material  60 . The result is shown in  FIG. 3A . 
         [0048]    In the interspaces of the trenches  52 , strings  62  of the material of former layer of floating-gate electrode material  60  are formed. The lower parts of the sidewalls of these strings  62  are covered by the STI-fill  30 . However, the upper parts of the sidewalls of the strings  62  are exposed. 
         [0049]    In a further process step, the semiconductor structure of  FIG. 3A  is heated in an oxygen atmosphere to perform a thermal oxidation of the exposed surfaces of the strings  62 . Thus, silicon oxide layers  64  are formed that cover the exposed areas of the strings  62  completely. These silicon oxide layers  64  may have a layer thickness up to 30 nm. 
         [0050]    However, the lower parts of the sidewalls of the strings  62  are protected by the STI-fill  30  against the oxygen atmosphere. Therefore, the lower parts of the sidewalls are not oxidised (i.e. the oxidation rate is negligibly small) during the thermal oxidation, as can be seen from FIG.  3 Ba. 
         [0051]    In a subsequent process step, the silicon oxide layers  64  are etched away. Thus, floating-gate electrodes FG are formed that have an upper width d 3  that is significantly smaller than the lower width d 4 . Of course, to decrease the upper width d 3  further, it is possible to repeat the thermal oxidation step several times. 
         [0052]    As an alternative to the thermal oxidation step of FIG.  3 Ba, it is also possible to form floating-gate electrodes FG by a wet etch of the exposed areas of the strings  62 . The result is shown in FIG.  3 Bb. This wet etch step may be performed in case that the material of the layer of floating-gate electrode material  60  is not suited for the thermal oxidation step. 
         [0053]    After the thermal oxidation step or after the wet etch step, oxide layer  18  and nitride layer  20  are etched away, for instance with hot phosphoric acid and hydrofluoric acid. Then, the FCW-method is performed to form control-gate electrodes CG and wordlines WL. The result is shown in  FIG. 3C . 
         [0054]      FIGS. 4A  and B show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method. 
         [0055]    According to the PMSS-method explained above, a semiconductor structure comprising a semiconductor substrate  10 , an insulation layer  12 , a layer of floating-gate electrode material  60 , an oxide layer  18  and a nitride layer  20  is produced. The layer of floating-gate electrode material  60  may include polysilicon and/or at least one transition metal. For example, the layer of floating-gate electrode material  60  may include iridium, ruthenium, a transition metal oxide, a transition metal silicide, a transition metal boride, a transition metal aluminide, a transition metal carbide and/or a transition metal nitride. In another approach, the layer of floating-gate electrode material  60  may include at least two layers of different materials. 
         [0056]    To etch the trenches  52  shown in  FIG. 4A , the ET-method is repeated. The newly etched trenches  52  extend from the surface of the semiconductor structure into the semiconductor substrate  10 . Their height h 1  may be in a range between 250 nm to 350 nm. The trenches  52  are completely filled with an STI-fill  30 . Then, a CMP step is carried out to remove the STI-fill  30  protruding above the nitride layer  20 . In a subsequent process step, a RIE etch is performed to partially reset the STI-fill  30  of the trenches  52 . The surface of the STI-fill  30  is now below the oxide layer  18 . Then, the first mask (not shown) of the ET-method is removed. 
         [0057]    After the removal of the first mask, a nitride pullback etch (NPE) step is carried out. Before the NPE step is carried out, the nitride spacers  70   a  cover the oxide layer  18  completely. 
         [0058]    The NPE step is performed to get a nitride mask for a following etch step to form oxide spacers  32  of the oxide of layer  18  and floating-gate electrodes FG of the material of layer  60 . The NPE step is a wet chemical etch step, for instance with hot phosphoric acid. The oxide layer  18  is not sensitive against this wet chemical etch step. Therefore, only the size of the nitride spacers  70   a  is decreased by the wet chemical etch step. The newly formed nitride spacers  70   b  are shown in  FIG. 4A . 
         [0059]    After the NPE step, a RIE step is performed. The nitride spacers  70   b  are not sensitive to this RIE step. Therefore, the size of the nitride spacers  70   b  is not decreased by the RIE step. 
         [0060]    However, the RIE step attacks the unprotected material of the layers  18  and  60 . Therefore, only the part of the oxide layer  18  which is protected by the nitride spacers is not etched away. Thus, oxide spacers  32  are formed. The nitride spacers  70   b  and the oxide spacers  32  serve as a mask to form floating-gate electrodes FG with an inverse-T shape. 
         [0061]    The RIE step is performed till the surface of the STI-fill  30  is within the distance s 2  from the insulation layer  12 . The result of the RIE step is shown in  FIG. 4B . 
         [0062]    A thermal oxidation step may be performed to oxidise the exposed surfaces of the floating-gate electrodes FG. The (not shown) oxide layers formed by this thermal oxidation step may be etched away. The thermal oxidation step and the following etching step may be carried out to remove the damaged zones of the floating-gate electrodes FG and to reduce the widths of the floating-gate electrodes FG further. The oxide spacers  32  are not attacked during this etching step, because they are protected by the nitride spacers  70   b.    
         [0063]    In a following etch step, carried out for example with hot phosphoric acid, the nitride spacers  70   b  are removed from the semiconductor structure. The oxide spacers  32  are not sensitive against this etch step. Therefore, the oxide spacers  32  are not removed from the floating-gate electrodes FG during this etch step. 
         [0064]    In the following process steps, control-gate electrodes CG and wordlines WL are formed according the FCW-method explained above. 
         [0065]      FIGS. 5A-5C  show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method. 
         [0066]    A semiconductor structure is produced according to the PMSS-method. The semiconductor structure includes a semiconductor structure  10 , an insulation layer  12 , a layer of floating-gate electrode material  60 , an oxide layer  18  and a nitride layer  20 . Several examples for the material of the layer of floating-gate electrode material  60  are given above. 
         [0067]    A method of forming a mask of nitride spacers (FMNS-method) is performed: First, a (not shown) first mask is deposited on the surface of the nitride layer  20 . Some areas of the mask which cover the interspaces of the (later etched) nitride spacers are exposed in a following lithographic step. In a subsequent etching step, nitride spacers  70   a  are formed of nitride layer  20  (see broken lines in  FIG. 5A ). In a further process step of the FMNS-method, the first mask is removed. 
         [0068]    In a following process step, the width of the nitride spacers  70   a  is decreased by an isotropic etch step. The newly formed nitride spacers  70   b  are shown in  FIG. 5A . 
         [0069]    The nitride spacers  70   b  serve as a mask during the following RIE step which does not attack the nitride spacers  70   b  but etches the material of the layers  18  and  60 . During the RIE step, trenches  72   a  are etched which extend into the layer of floating-gate electrode material  60 . Thus, the upper parts of floating-gate electrodes FG with an inverse-T shape are formed of the layer of floating-gate electrode material  60 . The RIE step is continued till the bottom of the trenches  72   a  is within the distance s 2  from the interface of the layers  12  and  60 . The result of the RIE step is shown in  FIG. 5B . 
         [0070]    Then, nitride spacers  24  which cover the sidewalls of the trenches  72   a  are formed according to FNS-method. Only the bottom of the trenches  72   a  is not protected by the nitride spacers  24 . 
         [0071]    A second RIE etch is performed to increase the depth of the trenches  72   a . During this second RIE etch, the exposed material at the bottoms of the trenches  72   a  is attacked. The second RIE step is stopped when the total height h 1  of the trenches  72   b  is within a range between 250 nm to 350 nm. 
         [0072]    Thus, the lower parts of the floating-gate electrodes FG with inverse-T shape are formed. The result of the second RIE step is shown in  FIG. 5C . 
         [0073]    The newly formed trenches  72   b  are partially filled with a STI-fill  30 . The nitride spacers  24  are removed by an etching step carried out with hot phosphoric acid. The oxide spacers  32  formed on the floating gate electrodes are not removed. 
         [0074]    In and additional process step, control-gate electrodes CG and wordlines WL may be formed according to the FCW-method. 
         [0075]      FIGS. 6A ,  6 Ba and  6 Bb show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method. 
         [0076]    According to the PMSS-method, a semiconductor structure comprising a semiconductor substrate  10 , an insulation layer  12 , a layer of floating-gate electrode material  60 , an oxide layer  18  and a nitride layer  20  is produced. The layer of floating-gate electrode material  60  may include polysilicon and/or at least one transition metal. For example, the layer of floating-gate electrode material  60  may include iridium, ruthenium, a transition metal oxide, a transition metal silicide, a transition metal boride, a transition metal aluminide, a transition metal carbide and/or a transition metal nitride. It is also possible to deposit at least two layers of these materials to form floating-gate electrodes FG from their materials according to the method explained below. 
         [0077]    Then, a mask of nitride spacers  70   a  is formed of the nitride layer  20  according to the FMNS-method explained above. 
         [0078]    A RIE step is performed to etch the exposed parts of the oxide layer  18 . The RIE step is carried out with an etching material that does not attack the nitride spacers  70   a  or the material of layer  60 . The RIE step is continued till the surface of the layer of floating-gate electrode material  60  is exposed in the interspaces of the nitride spacers  70   a . Thus, the upper part of trenches  80   a  is etched. The upper parts of the trenches  80   a  have a first width d 5 . 
         [0079]    An isotropic etch step is carried out to etch the lower parts of the trenches  80   a  into the layer  60 . The lower parts of the trenches  80   a  have a second width d 6  that is significantly larger than the first width d 5 . The etching material of the isotropic etch step does not attack nitride or oxide. Therefore, the width d 5  of the upper part of the trenches  80   a  is not increased significantly during the isotropic etch step. The isotropic etch step is continued till the bottom of the trenches  80   a  is within the distance s 2  of the insulation layer  12 . The result of the isotropic etch step is shown in  FIG. 6A . 
         [0080]    In a next process step, nitride spacers  24  which cover the sidewalls of the trenches  80   a  are formed according to the FNS-method. These nitride spacers  24  only protect the sidewalls of the trenches  80   a . The bottoms of the trenches  80   a  are exposed. 
         [0081]    In a following RIE step, the unprotected material at the bottoms of the trenches  80   a  is etched to increase the depth of the trenches  80   a . The RIE step is continued till the etched trenches  80   b  extend into the semiconductor substrate  10  and have a total height h 1  in a range between 250 nm to 350 nm. The result of the RIE step is shown in FIG.  6 Ba. 
         [0082]    The nitride spacers  24 , the nitride layer  20  and the oxide layer  18  are removed according to the methods explained above and the trenches  80   b  are filled with a STI-fill  30 . Then, the FCW-method is performed to form control-gate electrodes CG and wordlines WL on the semiconductor structure. 
         [0083]    As an alternative to the RIE step of this method, the oxide layer  18  may also be etched by the isotropic etch step. Thus, it is possible to form oxide spacers  32  on the floating-gate electrodes FG. The oxide spacers  32  are also protected during the following RIE step by the nitride spacers  24 , as can be seen from FIG.  6 Bb. 
         [0084]      FIGS. 7A-7F  show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method. 
         [0085]    A semiconductor structure is fabricated according to the PMSS-method. The semiconductor structure includes a semiconductor substrate  10 , an insulation layer  12 , a layer of floating-gate electrode material  60 , an oxide layer  18  and a nitride layer  20 . The layer of floating-gate electrode material  60  may include polysilicon and/or at least one transition metal, for instance a transition metal oxide, a transition metal nitride, a transition metal boride, a transition metal aluminide, a transition metal carbide and/or a transition metal silicide. 
         [0086]    In a second process step, the already mentioned ET-method is carried out to etch trenches  52  into the semiconductor structure. These trenches  52  extend from the surface of the semiconductor structure into the semiconductor substrate  10 . Their total height h 1  of the trenches  52  may be in a range between 250 nm to 350 nm. The semiconductor structure with the trenches  52  is shown in  FIG. 7A . 
         [0087]    In a following process step, the trenches  52  are filled with a STI-fill  30 . A CMP step may be performed to remove the STI-fill  30  protruding above the nitride layer  20 . Then, the STI-fill  30  is partially removed from the trenches  52  till the surface of the STI-fill  30  is near to the surface of layer  60 . Thus, the sidewalls of the nitride spacers  70   a  formed of nitride layers  20  are exposed. The mask build of the nitride spacers  70   a  is shown (in broken lines) in  FIG. 7B . 
         [0088]    This mask of nitride spacers  70   a  is used to etch floating-gate electrodes FG. In a first step of the method of etching floating-gate electrodes FG (EFE-method) an isotropic etch step is performed to decrease the width of the nitride spacers  70   a . This isotropic etch step has a rather short duration to make sure that the decrease of the width of the nitride spacers  70   b  is rather small, as can be seen from  FIG. 7B . 
         [0089]    Then, a RIE step is performed to etch the exposed oxide of the oxide layer  18  and the exposed material of layer  60 . This RIE step is continued for a rather short time to make sure that the surface of the STI-fill  30  is moved for a little distance in the direction to the insulation layer  12 . The result is shown in  FIG. 7B . 
         [0090]    The nitride spacers  70   b  are not sensitive against the RIE step. Therefore, the decrease of the nitride spacers  70   b  during the RIE step is not significant. 
         [0091]    In a following process step, the width of the nitride spacers  70   b  is decreased again by an isotropic etch step. The newly formed nitride spacers  70   c  are shown in  FIG. 7C . (The broken lines mark the former size of the nitride spacers  70   b .) 
         [0092]    The RIE step is repeated, as can be seen from  FIG. 7C . 
         [0093]    Thus, a RIE step is followed by an isotropic etch step and vice versa. Both etching steps are performed several times to make sure that the etched floating-gate electrodes FG get a staged shape.  FIG. 7D  shows another intermediate stage of the EFE-method. 
         [0094]    The EFE-method is continued till the surface of the STI-fill  30  is within the distance s 2  of the insulation layer  12 . The distance s 2  may be in a range between 10 nm to 30 nm. The final shape of the newly etched floating-gate electrodes FG is shown in  FIG. 7E . The cross sections of the floating-gate electrodes FG are now almost triangular. 
         [0095]    In case that the materials of the layers  18  and  20  are not completely removed by the EFE-method, etching steps which specifically attack oxide and/or nitride may be carried out. 
         [0096]    A thermal oxidation may be performed to form silicon oxide layers  82  on the exposed areas of the floating-gate electrodes FG (see  FIG. 7E ). The silicon oxide layers  82  are then etched away. The thermal oxidation and the following etching step may be done to remove damaged material of the floating-gate electrodes FG and to decrease the widths of the floating-gate electrodes FG further. 
         [0097]    Even though the floating-gate electrodes FG shown in  FIG. 7E  have a rather triangular shape compared to the inverse-T shape of the floating-gate electrodes FG mentioned above, it is possible to form control-gate electrodes CG and wordlines WL on the triangle-shaped floating gate electrodes according to the FCW-method. The result of the FCW-method is shown in  FIG. 7F . 
         [0098]      FIGS. 8A-8F  show cross sections of another semiconductor structure for illustrating another approach of the manufacturing method. 
         [0099]      FIG. 8A  shows a semiconductor structure comprising a semiconductor substrate  10 , an insulation layer  12 , a layer of floating-gate electrode material  60 , an oxide layer  18  and a nitride layer  20 . The semiconductor structure may be produced according to the PMSS-method. 
         [0100]    Then, a mask of nitride spacers  70   a  is formed of the nitride layer  20  according to the FMNS-method. Those parts of the oxide layer  18 , which are not protected by the nitride spacers  70   a , are etched away. This is done till some areas of the surface of layer  60  are exposed, as can be seen from  FIG. 8A . 
         [0101]    The EFE-method is started and continued till trenches  84  are etched that extend to the surface of the insulation layer  12 . Thus, floating-gate electrodes FG that have an almost triangular shape are etched.  FIGS. 8B and 8C  show an intermediate stage and a further stage of the EFE-method. 
         [0102]    After the EFE-method, a thermal oxidation step is carried out to grow a (not shown) thin oxide layer with a layer thickness about 2 nm on the exposed areas of the floating gate electrodes FG. Then, a nitride layer  86  is deposited on the surface of the semiconductor structure. A mask is formed on the nitride layer  20 . The areas of the mask which cover the bottoms of the trenches  84  are exposed in a lithographic step. In the following RIE step, the nitride layer  86  is removed from the bottoms of the trenches  84 . Only the nitride covering the sidewalls of the floating-gate electrodes FC is protected by the mask during the RIE step. Thus, the nitride spacers  86  shown in  FIG. 8D  are formed. 
         [0103]    Another RIE step is carried out to etch the exposed material at the bottoms of the trenches  84  and to increase the depth of the trenches  84 . This RIE step is continued till the trenches  84  extend into the semiconductor substrate  10  (see  FIG. 8E ). The total height hi of the trenches  84  is in a range between 250 nm to 350 nm. 
         [0104]    In case that it is necessary to remove the damaged material of the semiconductor structure, another thermal oxidation step may be carried out. Then, at least one etching step is performed to remove the oxide and the nitride from the semiconductor substrate. The result of this at least one etching step is shown in  FIG. 8F . 
         [0105]    The method of producing an integrated circuit is then continued as explained above with the FCW-method.