Abstract:
A method for accessing a Flash memory and an associated Flash memory system are provided, where the Flash memory includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages includes a plurality of sectors. The method includes: receiving a page of data from a host; encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data; encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, wherein the first seed is different from the second seed; and storing the first encoded data and the second encoded data to the Flash memory. An associated method and an associated Flash memory system are also provided.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application of U.S. patent application Ser. No. 12/907,990 filed on Oct. 20, 2010. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to access to a Flash memory, and more particularly, to a method for accessing a Flash memory, and to an associated Flash memory system. 
         [0004]    2. Description of the Prior Art 
         [0005]    As technologies of Flash memories progress in recent years, many kinds of portable memory devices (e.g. memory cards respectively complying with SD/MMC, CF, MS, and XD standards) or solid state drives (SSDs) equipped with Flash memories are widely implemented in various applications. Therefore, the control of access to Flash memories in these memory devices has become an important issue. 
         [0006]    Taking NAND Flash memories as an example, they can mainly be divided into two types, i.e. Single Level Cell (SLC) Flash memories and Multiple Level Cell (MLC) Flash memories. Each transistor that is considered a memory cell in SLC Flash memories only has two charge levels that respectively represent a logical value 0 and a logical value 1. In addition, the storage capability of each transistor that is considered a memory cell in MLC Flash memories can be fully utilized. More specifically, the voltage for driving memory cells in the MLC Flash memories is typically higher than that in the SLC Flash memories, and different voltage levels can be applied to the memory cells in the MLC Flash memories in order to record information of at least two bits (e.g. binary values 00, 01, 11, or 10) in a transistor that is considered a memory cell. Theoretically, the storage density of the MLC Flash memories may reach twice the storage density of the SLC Flash memories, which is considered good news for NAND Flash memory manufacturers who encountered a bottleneck of NAND Flash technologies. 
         [0007]    As MLC Flash memories are cheaper than SLC Flash memories, and are capable of providing higher capacity than SLC Flash memories while the space is limited, MLC Flash memories have been a main stream for implementation of most portable memory devices on the market. However, various problems of the MLC Flash memories have arisen due to their unstable characteristics. In order to ensure that the access control of a memory device over the Flash memory therein can comply with related standards, the controller of the Flash memory should have some handling mechanisms in order to properly handle its data access operations. 
         [0008]    According to the related art, the memory device having the aforementioned handling mechanisms may still suffer from some deficiencies. For example, due to usage behaviors of the user, data of some specific data patterns would probably be constantly written into the Flash memory, where these specific data patterns may easily cause errors such as write/program errors, read errors, etc. Although the memory device may be equipped with a randomizer for adjusting data in order to solve such a problem, the data after adjustment is typically not random enough due to the conventional low cost design. According to the typical implementation of the related art, with regard to each sector, the value of an input seed of the randomizer remains unvaried (i.e. for each sector, the input seed always has the same value), so the problem mentioned above are not really resolved. Therefore, a novel method is required for performing data pattern management regarding data accessed by the controller in order to reduce the probability of error occurrence. 
       SUMMARY OF THE INVENTION 
       [0009]    It is therefore an objective of the claimed invention to provide a method for accessing a Flash memory, and to provide an associated Flash memory system, in order to solve the above-mentioned problems. 
         [0010]    According to at least one preferred embodiment of the claimed invention, a method for accessing a Flash memory is provided, where the Flash memory comprises a plurality of blocks, each of the blocks comprises a plurality of pages, and each of the pages comprises a plurality of sectors. The method comprises: receiving a page of data from a host; encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data; encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, wherein the first seed is different from the second seed; and storing the first encoded data and the second encoded data to the Flash memory. 
         [0011]    According to at least one preferred embodiment of the claimed invention, a method for accessing a Flash memory is provided, where the Flash memory comprises a plurality of blocks, each of the blocks comprises a plurality of pages, and each of the pages comprises a plurality of sectors. The method comprises: reading a page of data from the Flash memory; decoding a first portion of the page of data by a derandomizer that operated under a first seed to generate a first decoded data; and decoding a second portion of the page of data by the derandomizer that operated under a second seed to generate a second decoded data, wherein the first seed is different from the second seed. 
         [0012]    According to at least one preferred embodiment of the claimed invention, a Flash memory system comprises a Flash memory, and further comprises a controller coupled to the Flash memory. The Flash memory comprises a plurality of blocks, each of the blocks comprises a plurality of pages, and each of the pages comprises a plurality of sectors. In addition, the controller is utilized for receiving a page of data from a host, encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data, encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, and storing the first encoded data and the second encoded data to the Flash memory, wherein the first seed is different from the second seed. 
         [0013]    According to at least one preferred embodiment of the claimed invention, a Flash memory system comprises a Flash memory, and further comprises a controller coupled to the Flash memory. The Flash memory comprises a plurality of blocks, each of the blocks comprises a plurality of pages, and each of the pages comprises a plurality of sectors. In addition, the controller is utilized for reading a page of data from the Flash memory, decoding a first portion of the page of data by a derandomizer that operated under a first seed to generate a first decoded data, and decoding a second portion of the page of data by the derandomizer that operated under a second seed to generate a second decoded data, wherein the first seed is different from the second seed. 
         [0014]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a diagram of a memory device according to a first embodiment of the present invention. 
           [0016]      FIG. 2  is a flowchart of a method for suppressing errors according to one embodiment of the present invention. 
           [0017]    FIGS.  3 A-3B respectively illustrate a conversion matrix and a corresponding conversion circuit involved with the method shown in  FIG. 2  according to an embodiment of the present invention. 
           [0018]      FIG. 4A  illustrates some implementation details of the seed generator shown in  FIG. 1  that are involved with the method shown in  FIG. 2  according to an embodiment of the present invention. 
           [0019]      FIG. 4B  illustrates some implementation details of the seed generator shown in  FIG. 1  that are involved with the method shown in  FIG. 2  according to another embodiment of the present invention. 
           [0020]      FIG. 5  illustrates a series of values involved with the embodiment shown in  FIG. 4B , while the series of values can be generated in a situation where the number of cycles of operations of the randomizer/derandomizer shown in  FIG. 1  is not limited. 
           [0021]      FIG. 6  is a diagram of a seed generator of a memory device according to a second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Please refer to  FIG. 1 , which illustrates a diagram of a memory device  100  according to a first embodiment of the present invention. In particular, the memory device  100  of this embodiment is a portable memory device, examples of which may include, but not limited to, memory cards complying with SD/MMC, CF, MS, or XD standards, and Universal Serial Bus (USB) Flash drives (which can be referred to as USB Flash disks). The memory device  100  comprises a Flash memory  120 , and further comprises a controller arranged to access the Flash memory  120 , where the aforementioned controller of this embodiment is a memory controller  110 . According to this embodiment, the memory controller  110  comprises a microprocessor  112 , a read only memory (ROM)  112 M, a control logic  114 , a buffer memory  116 , and an interface logic  118 . In addition, the control logic  114  comprises an adjustment unit  114 A, a seed generator  114 G, a multiplexer  114 M (labeled “MUX” in  FIG. 1 ), and a randomizer/derandomizer  114 R. In practice, the adjustment unit  114 A can be an exclusive OR (XOR) gate or an adder. Please note that the portable memory device is taken as an example of the memory device  100  in this embodiment. This is for illustrative purposes only, and is not meant to be a limitation of the present invention. According to a variation of this embodiment, the memory device  100  can be a solid state drive (SSD). 
         [0023]    In this embodiment, the ROM  112 M is arranged to store a program code  112 C, and the microprocessor  112  is arranged to execute the program code  112 C to control the access to the Flash memory  120 . Typically, the Flash memory  120  comprises a plurality of blocks, and the controller (e.g. the memory controller  110  that executes the program code  112 C by utilizing the microprocessor  112 ) performs data erasure operations on the Flash memory  120  by erasing in units of blocks. In addition, a block can be utilized for recording a specific amount of pages, where the controller mentioned above performs data writing operations on the Flash memory  120  by writing/programming in units of pages. 
         [0024]    In practice, the memory controller  110  that executes the program code  112 C by utilizing the microprocessor  112  is capable of performing various control operations by utilizing the internal components within the memory controller  110 . For example, the memory controller  110  utilizes the control logic  114  to control access to the Flash memory  120  (e.g. operations of accessing at least one block or at least one page), utilizes the buffer memory  116  to perform buffering operations for the memory controller  110 , and utilizes the interface logic  118  to communicate with a host device. According to this embodiment, in addition to accessing the Flash memory  120 , the memory controller  110  is capable of properly managing the plurality of blocks. 
         [0025]    In addition, the memory controller  110  can further suppress errors regarding data accessed by the memory controller  110  itself (e.g. the data D B  shown in  FIG. 1 ), and more particularly, suppress errors by utilizing operations of the randomizer/derandomizer  114 R. More specifically, the randomizer/derandomizer  114 R is arranged to generate a random function according to an input seed  114 S, with the random function being utilized for adjusting a plurality of bits of the data (e.g. the data D B ) bit by bit when the controller receives a write/read command, where the write/read command is utilized for instructing the controller to write the data into/read the data from the Flash memory  120 . As a result, the adjustment unit  114 A shown in  FIG. 1  adjusts the data D B  according to the random sequence  114 RS (i.e. the sequence of the random function mentioned above) to generate the adjusted data D A . For example, in a situation where the write/read command mentioned above represents a write command, when the data path passing through the adjustment unit  114 A represents a write path, the data D B  may represent the data to be written into the Flash memory  120  by the controller, and the data D A  may represent the adjusted data for being written. In anther example, in a situation where the write/read command mentioned above represents a read command, when the data path passing through the adjustment unit  114 A represents a read path, the data D B  may represent the data read from the Flash memory  120  by the controller, and the data D A  may represent the adjusted data for being further processed to be sent back to the host device. In practice, the memory controller  110  that executes the program code  112 C by utilizing the microprocessor  112  can generate control signals C 0 , C 1 , and C 2 , in order to control the seed generator  114 G, the multiplexer  114 M, and the randomizer/derandomizer  114 R. 
         [0026]    In this embodiment, the control signal C 0  may carry at least one index for indicating the sector, the word, and/or the byte that the data D B  corresponds to, and more particularly, for indicating the portion currently being processed within the data D B . In addition to the control signal C 0 , the seed generator  114 G of this embodiment further receives the original seed  114 B. As a result, according to the control of the control signal C 0 , the seed generator  114 G can adjust the original seed  114 B correspondingly to generate the new seed  114 N, where the new seed  114 N corresponds to the index, and the new seed  114 N is typically different from the original seed  114 B since the seed generator  114 G (whose implementation details will be described later) is properly designed. Thus, even in a situation where the original seed  114 B is generated by utilizing the architecture of the conventional low cost design, causing repeated occurrence of the same value of the original seed  114 B, there is no repeated occurrence of the same value of the new seed  114 N. In addition, the control of the control signal C 1  is utilized for controlling multiplexing operations of the multiplexer  114 M, in order to make the multiplexer  114 M correspondingly multiplex the original seed  114 B or the new seed  114 N as the input seed  114 S of the randomizer/derandomizer  114 R. Additionally, the control of the control signal C 2  is utilized for controlling loading operations of the randomizer/derandomizer  114 R, in order to make the randomizer/derandomizer  114 R be able to correctly load the input seed  114 S. 
         [0027]    Based upon the architecture shown in  FIG. 1 , as there is no repeated occurrence of the same value of the new seed  114 N, as long as the operations of selecting the original seed  114 B or the new seed  114 N as the input seed  114 S can be properly controlled, the related art problem that the adjusted data is not random enough is no longer an issue. As a result, the original seed  114 B can still be generated by utilizing the architecture of the conventional low cost design. In this embodiment, with regard to at least each block of the blocks, the value of the original seed  114 B remains unvaried, where for each block of the blocks, the same original seed  114 B is utilized. For example, with regard to each page of each block, the value of the original seed  114 B remains unvaried. More particularly, with regard to each sector of each block, the value of the original seed  114 B remains unvaried. Please refer to  FIG. 2  for related details of error suppression performed by the memory controller  110 . 
         [0028]      FIG. 2  is a flowchart of a method  910  for suppressing errors according to one embodiment of the present invention. The method can be applied to the memory device  100  shown in  FIG. 1 , and more particularly, to the controller mentioned above (e.g. the memory controller  110  that executes the program code  112 C by utilizing the microprocessor  112 ). In addition, the method can be implemented by utilizing the memory device  100  shown in  FIG. 1 , and more particularly, by utilizing the controller mentioned above. The method  910  is described as follows. 
         [0029]    In Step  912 , the controller determines whether to utilize the original seed  114 B as the input seed  114 S of the randomizer/derandomizer  114 R according to an address of the data to be written into or read from the Flash memory  120  (e.g. the data D B ). When it is determined that the original seed  114 B should be utilized as the input seed  114 S, Step  914 - 1  is entered; otherwise (i.e. when it is determined that the original seed  114 B should not be utilized as the input seed  114 S), Step  914 - 2  is entered. 
         [0030]    In Step  914 - 1 , the controller inputs the original seed  114 B into the randomizer/derandomizer  114 R, in order to generate the random function according to the original seed  114 B to adjust the data. 
         [0031]    In Step  914 - 2 , the controller inputs the new seed  114 N into the randomizer/derandomizer  114 R, in order to generate the random function according to the new seed  114 N to adjust the data. 
         [0032]    In this embodiment, when the address mentioned in Step  912  falls within a predetermined range, the controller determines that the original seed  114 B should be utilized as the input seed  114 S. In addition, when the address does not fall within the predetermined range, the controller determines that the original seed  114 B should not be utilized as the input seed  114 S. For example, with regard to each block, the value of the original seed  114 B remains unvaried, and in this situation, the predetermined range may correspond to a block, a page, a sector, or a storage unit that is smaller than the sector. In another example, with regard to each page of each block, the value of the original seed  114 B remains unvaried, and in this situation, the predetermined range may correspond to a page, a sector, or a storage unit that is smaller than the sector, where the page mentioned in this situation may comprise multiple sectors. In another example, with regard to each sector of each block, the value of the original seed  114 B remains unvaried, and in this situation, the predetermined range may correspond to a sector or a storage unit that is smaller than the sector. 
         [0033]    According to this embodiment, the seed generator  114 G is arranged to adjust the original seed  114 B to generate the new seed  114 N, where the original seed  114 B comprises a plurality of bits, and the new seed  114 N comprises a plurality of bits. In addition, the seed generator  114 G stores one or more predetermined matrixes, and more particularly, a plurality of predetermined matrixes A Z(1) , A Z(2) , . . . , and A Z(X) , where the notation A represents a conversion matrix of the randomizer/derandomizer  114 R regarding the random sequence  114 RS, and in this embodiment, the seed generator  114 G can be regarded as a circuit for implementing the aforementioned one or more predetermined matrixes. As a result, the seed generator  114 G utilizes the original seed  114 B and a specific predetermined matrix of the one or more predetermined matrixes to perform operations, in order to generate the new seed  114 N. For example, in a situation where the original seed  114 B and the new seed  114 N respectively comprise W bits, the conversion matrix A is a W by W matrix, and the predetermined matrixes A Z(1)j , A Z(2) , . . . , and A Z(X)  mentioned above are also W by W matrixes, respectively. Please note that the conversion matrix A is not limited to be a square matrix. In another example, the conversion matrix A can be a W by M matrix or an M by W matrix as long as the conversion matrix A can be utilized for performing multiplication operations on the original seed  114 B, where M is not equal to W. 
         [0034]    Here, the random sequence  114 RS can be expressed as the sequence {RS(t)|t is an integer} (with t being an index corresponding to time), and the relationship between any value RS(t) of this sequence and the next value RS(t+1) thereof can be expressed according to the following equation: 
         [0000]        RS ( t+ 1)= A*RS ( t ); 
         [0035]    Thus, when the value of the input seed  114 S is equal to RS(t 0 ), by utilizing the conversion expressed by the above equation, the randomizer/derandomizer  114 R can generate at least one portion (e.g. a portion or all) of the sequence {RS(t)}, and more particularly, the portion starting from RS(t 0 +1), i.e. the sequence {RS(t)|t≧(t 0 +1)}. 
         [0036]      FIGS. 3A-3B  respectively illustrate the conversion matrix A and the corresponding conversion circuit  300  involved with the method  910  shown in  FIG. 2  according to an embodiment of the present invention, where the conversion circuit  300  is positioned within the randomizer/derandomizer  114 R, and the conversion circuit  300  comprises W registers  310 - 0 ,  310 - 1 , . . . , and  310 -(W−1) and an XOR gate  320  (labeled “XOR” in  FIG. 3B ). In a situation where W=5, the registers  310 - 0 ,  310 - 1 ,  310 - 2 ,  310 - 3 , and  310 - 4  (respectively labeled “RS(t; 0)”, “RS(t; 1)”, “RS(t; 2)”, “RS(t; 3)”, and “RS(t; 4)” in  FIG. 3B ) store respective bits RS(t; 0), RS(t; 1), RS(t; 2), RS(t; 3), and RS(t; 4) of the binary form of the value RS(t), respectively. According to the architecture shown in  FIG. 3B , the randomizer/derandomizer  114 R can generate at least one portion of the sequence {RS(t)}, such as a portion or all of the sequence {RS(t)}. 
         [0037]      FIG. 4A  illustrates some implementation details of the seed generator shown in  FIG. 1  that are involved with the method  910  shown in  FIG. 2  according to an embodiment of the present invention. According to this embodiment, the seed generator  114 G comprises an adjustment circuit  410  and a storage unit. The storage unit  420  stores X predetermined matrixes A Z(1) , A Z(2) , . . . , and A Z(X) , where Z(1), Z(2), . . . , and Z(X) are all positive integers, and more particularly, positive integers that are different from each other. In addition, according to the aforementioned at least one index, the seed generator  114 G (and more particularly, the adjustment circuit  410 ) selects a corresponding predetermined matrix A Z(x)  from the X predetermined matrixes A Z(1) , A Z(2) , . . . , and A Z(X) , where x=1, 2, . . . , or X, and the control signal C 0  carries the aforementioned at least one index. As a result, the seed generator  114 G utilizes the predetermined matrix A Z(x)  to adjust the original seed  114 B, in order to generate the new seed  114 N. According to a special case of this embodiment, Z(1), Z(2), . . . , and Z(X) can be an arithmetic sequence. According to another special case of this embodiment, Z(1), Z(2), . . . , and Z(X) can be an arithmetic sequence, and the common difference of successive members of this arithmetic sequence Z(1), Z(2), . . . , and Z(X) is equal to Z(1). 
         [0038]      FIG. 4B  illustrates some implementation details of the seed generator  114 G shown in  FIG. 1  that are involved with the method  910  shown in  FIG. 2  according to another embodiment of the present invention, where this embodiment is a special case of the embodiment shown in  FIG. 4A . In this embodiment, Z(x)=(1024*x) and X=3, and each page comprises 4 kilobytes and each sector comprises 1 kilobyte (i.e. each page comprises 4 sectors), given that 1 kilobyte is 1024 bytes. As shown in  FIG. 4B , the storage unit  420  stores 3 predetermined matrixes A 1024 , A 2048 , and A 3072 . Please refer to  FIG. 5  for better comprehension.  FIG. 5  illustrates a series of values involved with the embodiment shown in  FIG. 4B , while the series of values can be generated in a situation where the number of cycles of operations of the randomizer/derandomizer  114 R shown in  FIG. 1  is not limited. As shown in  FIG. 5 , the series of values comprise {RS(1), RS(2), RS(3), . . . , RS(1024)}, {RS(1025), . . . , RS(2048)}, {RS(2049), . . . , RS(3072)}, {RS(3073), . . . , RS(4096)}, and {RS(4097), . . . , RS(32K)}, where RS(32K) represents RS(32768). In a situation where W=8, each value of the series of values falls within the range of the interval [0, 255]. Here, the numbers in the respective circles shown in  FIG. 5  are taken as examples of the series of values. This is for illustrative purposes only, and is not meant to be a limitation of the present invention. According to a variation of this embodiment, these numbers in the respective circles shown in  FIG. 5  can be varied. 
         [0039]    According to this embodiment, after the value RS(32K) is generated, the next value to be generated (i.e. the value to be subsequently generated after generating the value RS(32K)) is the first value RS(1) of this series of values, where this series of values can be generated repeatedly. In general, this series of values can be divided into (Y+1) portions as follows: 
         [0000]    
       
         
           
             
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         [0000]    where Y=31 in this embodiment. 
         [0040]    Suppose that after the controller inputs the original seed  114 B into the randomizer/derandomizer  114 R and a cycle goes by, the first value that appears within the random sequence  114 RS is RS(1), and the predetermined range utilized by the controller corresponds to a sector (which comprises 1 kilobyte), and more particularly, the first sector of any page. As a result, when the address mentioned in Step  912  falls within the predetermined range, which means the address represents the first sector of a certain page, the controller determines that the original seed  114 B should be utilized as the input seed  114 S. In addition, when the address does not fall within the predetermined range, and more particularly, when the address represents the (v+1) th  sector of a certain page, under control of the controller, the seed generator  114 G can utilize the original seed  114 B and the predetermined matrix A Z(v)  to perform operations, in order to generate the new seed  114 N, where v=1, 2, or 3. Similar descriptions for this embodiment are not repeated in detail here. 
         [0041]    According to a variation of this embodiment, the predetermined range utilized by the controller corresponds to a sector (which comprises 1 kilobyte), and more particularly, the first sector of each set of sectors. In this embodiment, each set of sectors may comprise 32 sectors. In addition, the storage unit  420  stores 31 predetermined matrixes A 1024 , A 2048 , A 3072 , . . . , and A 31K , where A 31K  represents A 31744 . As a result, when the address mentioned in Step  912  falls within the predetermined range, which means the address represents the first sector of a certain set of sectors, the controller determines that the original seed  114 B should be utilized as the input seed  114 S. Additionally, when the address does not fall within the predetermined range, and more particularly, when the address represents the (v+1) th  sector of a certain set of sectors, under control of the controller, the seed generator  114 G can utilize the original seed  114 B and the predetermined matrix A Z(v)  to perform operations, in order to generate the new seed  114 N, where v=1, 2, . . . , or 31. Similar descriptions for this variation are not repeated in detail here. 
         [0042]      FIG. 6  is a diagram of a seed generator  114 G′ of a memory device  200  according to a second embodiment of the present invention, where this embodiment is a variation of the first embodiment. The multiplexer  114 M of this embodiment is integrated into the seed generator  114 G mentioned above, and in response to the change of the architecture, the seed generator of this embodiment is labeled using a similar notation such as  114 G′, where the seed generator  114 G′ inputs the aforementioned input seed  114 S into the randomizer/derandomizer  114 R mentioned above. Thus, the memory device  200  of this embodiment (or the memory controller  210  thereof) can be distinguished from the memory device  100  shown in  FIG. 1  (or the memory controller  110  thereof) according to whether the multiplexer  114 M is positioned within the seed generator. Similar descriptions for this embodiment are not repeated in detail here. 
         [0043]    It is an advantage of the present invention that, by properly designing the seed generator  114 G accompanied with associated control (e.g. the control signals C 0 , C 1 , and C 2 ), the present invention can properly perform data pattern management regarding data accessed by the controller, in order to reduce the probability of error occurrence. In addition, implementing according to any of the respective embodiments/variations disclosed above will not cause unreasonable additional costs, while the original seed  114 B can still be generated by utilizing the architecture of the conventional low cost design. Therefore, by implementing based upon one or more of the embodiments/variations disclosed above, the related art problems can be resolved without greatly increasing the overall costs. 
         [0044]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.