Abstract:
An apparatus is capable of improving the power factor of a power supply powered by a high power line and a ground power line. The apparatus comprises a line voltage detector and an ON time controller. The line voltage detector provides a scaled voltage to represent a line voltage of the high power line. The ON time controller has a valley voltage detector, which provides, in response to the scaled voltage, a valley representative representing a valley voltage of the line voltage. The ON time controller controls an ON time of a power switch in the power supply in response to the valley representative.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to and the benefit of Taiwan Application Series Number 102132129 filed on Sep. 6, 2013, which is incorporated by reference in its entirety. 
     BACKGROUND 
     The present disclosure relates generally to apparatuses and control methods for power factor correction, more particularly to apparatuses and control methods for improving the power factor when a power supply drives a light load. 
     The power factor of an AC electrical power system is defined as the ratio of the real power flowing to a load, to the apparent power into the power circuit, and is a dimensionless number between −1 and 1. If a power supply has a power factor less than 1, an electric power company must reserve power delivery capacity more than the output power rating of the power supply, to make the power supply operate properly in all allowed circumstances. In order to relieve the burden of reserving over-high power delivery capacity, developed and developing countries have enforced regulations requiring power supplies for lighting or with more than 100 Watt output rating to have a power factor more than 0.9. 
     Active power factor correction (PFC) refers to use of active devices including a control circuit and at least one power switch for achieving a good power factor. Normally, one power switch is well controlled to intentionally drain an input current, making its average substantially in proportion to an input voltage, such that a power factor of 1 could be approximately achieved. Active PFC is commonly embodied by switching-mode power supplies (SMPSs). A booster operating in a constant ON-time scheme, for example, could results in a very high power factor. 
     A SMPS normally has an anti-EMI (electromagnetic inference) circuit, which usually includes a low-pass filter comprising an inductor and a capacitor at least, and is positioned between a main converter and an outlet plug connected to AC main power lines. When driving a light load or no load, the SMPS drains very little current from the outlet plug, and the main converter might receive a filtered input voltage very different from the input voltage in the outlet plug. As a result, even if the main converter makes its average input current substantially in proportion to the filtered input voltage, the power factor of the SMPS is not optimized because the waveform of the average input current still differs to that of the filtered input voltage in shape. 
     Therefore, it is an issue to optimize the power factor of a SMPS when driving a light load. 
     SUMMARY 
     Embodiments of the invention include an apparatus capable of improving power factor of a power supply powered by a high power line and a ground power line. The power supply comprises a power switch connected to an inductive device. The apparatus comprises a line voltage detector and an ON time controller. The line voltage detector provides a scaled voltage to represent a line voltage of the high power line. The ON time controller has a valley voltage detector, which provides, in response to the scaled voltage, a valley representative representing a valley voltage of the line voltage. The ON time controller controls an ON time of the power switch in response to the valley representative. 
     Embodiments of the invention further include a control method for improving a power factor of a power supply, which is powered by a high power line and a ground power line. The power supply comprises a power switch. A scaled voltage is provided to represent a line voltage of the high power line. A valley representative is provided, in response to the scaled voltage, to represent a valley voltage of the line voltage. An ON time of the power switch is controlled in response to the scaled voltage and the valley representative. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted. 
       The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  demonstrates a SMPS with PFC according to embodiments of the invention; 
         FIG. 2  illustrates the controller in  FIG. 1 ; 
         FIG. 3  shows the ramp generator in  FIG. 2 ; 
         FIG. 4  demonstrates some waveforms of signals according to an embodiment of the invention; 
         FIGS. 5A and 5B  demonstrate two valley voltage detectors; 
         FIG. 6  demonstrates another ramp generator; 
         FIG. 7  demonstrates another SMPS according to embodiments of the invention; 
         FIG. 8  shows waveforms of the secondary current I SEC  through the secondary winding, the auxiliary voltage V AUX , and the PWM signal S PWM  in  FIG. 7 ; 
         FIG. 9  demonstrates the controller  210  in  FIG. 7 ; and 
         FIG. 10  illustrates the line voltage detector  216  in  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  demonstrates a SMPS with PFC according to embodiments of the invention, including an anti-EMI circuit  102 , a bridge rectifier  104 , a booster  106 , and a controller  110 . 
     The anti-EMI circuit  102  has inductors and a capacitor, to block any high-frequency signal from propagating from the booster  106  to an AC input port  114 , an outlet plug for example, where the high-frequency signal could occur due to the high-frequency switching of the power switch  112 . The AC input port  114  receives an AC input voltage V AC . The bridge rectifier  104  rectifies its AC inputs and generates a direct-current voltage across between a high power line LINE and a ground line GND. The voltage at the high power line LINE is denoted as line voltage V LINE , and the voltage at the ground line is about zero by definition. The line voltage V LINE  is a filtered voltage result as the anti-EMI circuit  102  low-passes the AC input voltage V AC . The current flowing from the bridge rectifier  104  into the primary winding  118  is denoted as line current V LINE . The booster  106  includes the primary winding  118  and the power switch  112 , and they are connected in series and between the high power line LINE and the ground power line GND. The auxiliary winding  119  (of the transformer  116 ) is coupled to a terminal ZCD (named from zero current detection) of the controller  110 . The terminal ZCD might be a pin if the controller  110  is a packaged integrated circuit. A voltage-divider  108  provides a feedback voltage V FB  representing an output voltage V OUT  of the booster  106 . The controller  110 , in response to the feedback voltage V FB , the line voltage V LINE , and signals delivered from the auxiliary winding  119 , generates a pulse-width-modulation (PWM) signal S PWM  to a gate terminal GATE to periodically turn ON and OFF the power switch  112 . 
     The purpose of the controller  110  is to stabilize the feedback voltage V FB  at a target voltage V TAR , such that the output voltage is stable. As to PFC, the controller  110 , at the same time, is designed to make an average of the line current I LINE  proportional to the AC input voltage V AC , thereby optimizing the power factor. 
       FIG. 2  illustrates the controller  110  in  FIG. 1 , including a voltage-divider  121 , an ON time controller  120 , an OFF time controller  122 , an SR flip-flop  124 , and driver  126 . The voltage-divider  121  scales down the line voltage V LINE , which could be as high as 240V, to generate a scaled voltage V LINE-IN , whose voltage is below 40V and is acceptable by the ON time controller  120 . The ON time controller  120  can reset the SR flip-flop  124 , to turn OFF the power switch  112  via the driver  126 , therefore giving an end to an ON time T ON  of the power switch  112 . The OFF time controller  122  can set the SR flip-flop  124 , to turn ON the power switch  113 , therefore giving an end to an OFF time T OFF  and a beginning to an ON time T ON . 
     The ON time controller  120  has a ramp generator  128 , a comparator  130 , and an operational amplifier  132 . The ramp generator  128  generates a ramp voltage V RAMP  in response to the scaled voltage V LINE-IN  and the PWM signal SO PWM  output from the SR flip-flop  124 . Based on the difference between the target voltage V TAR  and the feedback voltage V FB , the operational amplifier  132  provides in its output a compensation voltage V COM . Starting from the beginning of the ON time T ON , the ramp voltage V RAMP  ramps up with a slope from a default value. Once the ramp voltage V RAMP  exceeds the compensation voltage V COM , the comparator  130  resets the SR flip-flop  124 , so both the PWM signals SO PWM  and S PWM  become “0” in logic to turn off the power switch  112  and end an ON time T ON . The dependence of the ramp voltage V RAMP  to both the scaled voltage V LINE-IN  itself and a local minimum of the scaled voltage V LINE-IN  will be detail later. The scaled voltage V LINE-IN  represents the line voltage V LINE , and accordingly a local minimum of the scaled voltage V LINE-IN  represents a valley voltage V VALLEY  of the line voltage V LINE . In one embodiment of the invention, the higher scaled voltage V LINE-IN  the higher slope of the ramp voltage V RAMP ; and the higher local minimum of the scaled voltage V LINE-IN  the lower slope of the ramp voltage V RAMP . 
     The OFF time controller  122  acts like a de-energization detector. When the electromagnetic energy stored in the transformer  116  (of  FIG. 1 ) is depleted or the line current I LINE  drops to zero, the auxiliary voltage V AUX  at the terminal ZCD starts oscillating. After an ON time T ON  ends, the first time when the voltage V AUX  drops across a reference voltage (which shown in  FIG. 2  is 0.1V) indicates that the transformer  116  has depleted its stored energy, so in response the comparator  134  sets the SR flip-flop  124  to make the PWM signals SO PWM  and the S PWM  both “1” in logic, and the power switch  112  is turned ON, claiming the beginning of the next ON time T ON . 
       FIG. 3  shows the ramp generator  128  in  FIG. 2 . The switch  144  is under the control of the PWM signal SO PWM . During an ON time T ON , the switch  144  performs an open circuit, the main constant current source  142  provides a constant current I DEFAULT  to charge the capacitor  146 , so the ramp voltage V RAMP  increases over time and its waveform has a slope. During an OFF time T OFF , the switch  144  performs a short circuit, and the ramp voltage V RAMP  is clamped to be as 0V, a ground voltage. A supplemental current source  140  provides a supplemental current I SUPP , and includes two voltage-controlled current sources  148  and  150 , and a valley voltage detector  152 . The valley voltage detector  152  provides a scaled valley voltage V VALLEY-IN , which is a scaled version of the valley voltage V VALLEY  of the line voltage V LINE . The voltage-controlled current source  148  generates charge current I SUPP-LINE  in response to the scaled voltage V LINE-IN , while the voltage-controlled current source  148  generates discharge offset current I SUPP-OFFSET  in response to the scaled valley voltage V VALLEY-IN . Accordingly, the slope of the ramp voltage V RAMP  increases if the scaled voltage V LINE-IN  becomes higher, but decreases if the scaled valley voltage V VALLEY-IN  increases. 
     Preferably, the constant current I DEFAULT  is considerably much more than the supplemental current I SUPP , the ON time T ON  is roughly a constant, and the booster  106  in  FIG. 1  substantially operates at a constant ON-time mode, whose excellency in power factor correction has been approved in the art. Derivable from  FIG. 2 , the length of an ON time T ON  is determined by the compensation voltage V COM  and the slope of the ramp voltage V RAMP . Since the supplemental current I SUPP  slightly adjusts the slope of the ramp voltage V RAMP , it also changes the ON time T ON , mildly. If the line voltage V LINE  increases, both the scaled voltage V LINE-IN  and the charge current I SUPP-LINE  raise, and the slope increases, so the ON time T ON  shortens. If the valley voltage V VALLEY  of the line voltage V LINE  increases, the scaled valley voltage V VALLEY-IN  becomes higher, the discharge offset current I SUPP-OFFSET  increases, the slope decreases, so the ON time T ON  lengthens. 
       FIG. 4  demonstrates some waveforms of signals according to an embodiment of the invention, including, from top to bottom, the absolute of the AC input voltage V AC , the line voltage V LINE  and the valley voltage V VALLEY  when an output load is light, the scaled voltage V LINE-IN  and the scaled valley voltage V VALLEY-IN , the line current I LINE  if there is no supplemental current I SUPP  provided, and the line current I LINE  if the supplemental current I SUPP  is provided. 
     As demonstrated in  FIG. 4 , the absolute of the AC input voltage V AC  is always positive and its valleys all are 0V. When the load of the booster  106  is light or absent, the local minimum of the line voltage V LINE  might not go down to 0V because the booster  106  could not deplete the charge in the capacitor of the anti-EMI circuit  102  every half cycle of the AC input voltage V AC . So the valley voltage V VALLEY , the local minimum of the line voltage V LINE , stays somewhere above zero. The scaled voltage V LINE-IN  is a scaled version of the line voltage V LINE , such that it has the waveform similar to the line voltage V LINE , as demonstrated in  FIG. 4 . Supposed that the discharge offset current I SUPP-OFFSET  in  FIG. 3  is absent, the line current I LINE  still goes up and down in response to the ON and OFF of the power switch  112 , and the average of the line current I LINE  mainly follows the waveform of the line voltage V LINE , which, as shown in the second diagraph of  FIG. 4 , is nevertheless very different to that of the absolute of the AC input voltage V AC . If the discharge offset current I SUPP-OFFSET  in  FIG. 3  is provided as some embodiments of the invention do, it will take away the charge current I SUPP-LINE  when the line voltage V LINE  is at its valleys, and the average of the line current I LINE  will follow the line voltage V LINE  minus the valley voltage V VALLEY , as shown by the last diagraph in  FIG. 4 . It also can be derived from  FIG. 4  that the waveform  162 , the average of the line current I LLNE  under the help of discharge offset current I SUPP-OFFSET , fits the waveform of the absolute of the AC input voltage V AC , better than the waveform  160 , the average of the line current I LINE  without the help of discharge offset current I SUPP-OFFSET , does. In other words, the existence of the discharge offset current I SUPP-OFFSET  improves the power factor when the booster  106  powers a light load or no load. 
     If the load of the booster  106  is heavy, the charge stored in the capacitor of the anti-EMI circuit  102  can be easily depleted by strong line current I LINE , and the valley voltage V VALLEY  will be very close to 0V, so the discharge offset current I SUPP-OFFSET  is almost zero. In other words, since the discharge offset current I SUPP-OFFSET  almost disappears when a heavy load is driven, the embodiment shown  FIGS. 1 to 3  will have the same power factor as it was without the introduction of the discharge offset current I SUPP-OFFSET . 
       FIG. 5A  demonstrates a valley voltage detector  152 A, suitable for use in  FIG. 3 . The valley voltage detector  152 A has a diode and a capacitor, and the voltage on the capacitor could be used as the scaled valley voltage V VALLEY-IN . The capacitor in the valley voltage detector  152 A should excel in resisting leakage, to hold the scaled valley voltage V VALLEY-IN  constantly, and might be costly in view of implementation.  FIG. 5B  shows another valley voltage detector  152 B, where a digital counter  172  outputs a count DO, which is converted by a digital-to-analog converter  174  into the scaled valley voltage V VALLEY-IN , an analog signal. The count DO seems to be a digitalized valley voltage, memorized and held by the counter  172 . The clock generator  178  provides a pulse every period of time to reset the D flip-flop  176  and make the counter  172  count up or down, depending on the output from the D flip-flop  176 . The period of time to issue the pulse should be not less than a cycle time of the waveform  164  shown in  FIG. 2 . Preferably, the period of time is not less than 8 ms. The output of the comparator  170  connects to the clock terminal of the D flip-flop  176 . Simply put, in one period of time defined by the clock generator  178 , if the scaled voltage V LINE-IN  never drops below the scaled valley voltage V VALLEY-IN , then the non-inverted output terminal Q is always held to output “0”, otherwise it outputs “1” before the beginning of a next period of time. In case that the scaled voltage V LINE-IN  is always above the scaled valley voltage V VALLEY-IN , it means the real valleys of the scaled voltage V LINE-IN  are all above the scaled voltage V LINE-IN , so at the beginning of the next period of time the “1” at the inverted output terminal Q-bar of the D flip-flop  176  makes the counter  172  count up, and the scaled voltage V LINE-IN  increases by a little bit to trace the real valleys of the scaled voltage V LINE-IN . In the opposite, if the scaled voltage V LINE-IN  has dropped across the scaled valley voltage V VALLEY-IN , it means the valleys of the scaled voltage V LINE-IN  have values somewhere below the scaled valley voltage V VALLEY-IN , the counter counts down at the beginning of the next period of time, so as to decrease the scaled valley voltage V VALLEY-IN  and to trace the valleys. As the time goes by, the scaled valley voltage V VALLEY-IN  will have about the value representing the valleys. 
       FIG. 6  demonstrates another ramp generator  128 A, similar with the ramp generator  128  in  FIG. 3  and suitable for use in  FIG. 2 . Similarly, the valley voltage detector  152  in  FIG. 6  provides a scaled valley voltage V VALLEY-IN  to the adder  180  as a deduction from the scaled voltage V LINE-IN . After deduction, the adder  180  provides the remainder to the voltage-controlled current source  148 , which accordingly outputs the supplemental current I SUPP  to charge the capacitor  146 . 
     This invention is not limited to use for a booster. It could be employed in a flyback converter, for example, as demonstrated by the power supply  200  in  FIG. 7 . The power supply  200  includes an anti-EMI circuit  102 , a bridge rectifier  104 , a flyback converter  202 , a voltage divider  208 , and a controller  210 . 
     The voltage divider  208  consists of two resistors connected in series between two ends of the auxiliary winding  119 , and is capable of providing a scaled version of the auxiliary voltage V AUX  to the terminal ZCD of the controller  210 . The controller  210  generates the PWM signal S PWM  to turn ON or turn OFF the power switch  212 . During an ON time T ON  when the power switch  212  is ON, the primary winding  118  of the transformer energizes; and during an OFF time T OFF  when the power switch  212  is OFF, the transformer de-energizes and releases, via the auxiliary winding  119  and the secondary winding  201 , the electromagnetic energy stored therein. 
       FIG. 8  shows waveforms of the secondary current I SEC  through the secondary winding  201 , the auxiliary voltage V AUX , and the PWM signal S PWM  in  FIG. 7 . During an ON time T ON , the auxiliary voltage V AUX  is a negative reflective voltage in proportion to the line voltage V LINE ; and during an OFF time T OFF , it is a positive reflective voltage substantially in proportion to the output voltage V OUT . 
       FIG. 9  demonstrates the controller  210  in  FIG. 7 . An OFF time controller  213  acts like a de-energization detector, and deems the secondary winding  213  as having depleted its own electromagnetic energy when the voltage V Aux  drops across a reference voltage (which is 0.1 for example). The OFF time controller  213  accordingly sets the SR flip-flop  224  to make the PWM signals SO PWM  and the S PWM  both “1” in logic, and the power switch  212  is turned ON, claiming the beginning of an ON time T ON , as what happens at time point t 0  of  FIG. 8 . 
     During the discharge time T DIS , which is the period of time when the secondary current I SEC  is not 0, the sampling circuit  214  in  FIG. 9  samples the scaled version of the auxiliary voltage V AUX  and holds the sampled result as a feedback voltage V FB . The operational amplifier  220  compares the feedback voltage V FB  and a target voltage V TAR , and generates a compensation voltage V COM  based on the difference between them. The ramp generator  218  generates a ramp voltage V RAMP  in response to the scaled voltage V LINE-IN  and the PWM signal SO PWM  output from the SR flip-flop  224 . At the beginning of an ON time T ON , the ramp voltage V RAM  increases with a slope from a default value. At time point t 1  of  FIG. 8 , the ramp voltage V RAMP  exceeds the compensation voltage V COM , such that the comparator  222  resets the SR flip-flop  224  and makes both the PWM signals SO PWM  and S PWM  “0”, turning OFF the power switch  212  and giving an end to an ON time T ON . Examples of the ramp generator  218  has been illustrated in  FIGS. 3 and 6 , teaching of which has detailed how the slope of the ramp voltage V RAMP  is in response to the scaled voltage V LINE-IN  and the scaled valley voltage V VALLEY-IN . 
     During an ON time T ON  in  FIG. 8 , the line voltage detector  216  of  FIG. 9  clamps the voltage at the terminal ZCD at about 0V, and senses the current drained out from the terminal ZCD to generate the scaled voltage V LINE-IN , which is representative to the line voltage V LINE .  FIG. 10  illustrates the line voltage detector  216  in  FIG. 9 , and includes a bipolar junction transistor (BJT)  230  with its base electrode clamped at 0.7V. Accordingly, the BJT  230  could provide abundant current to clamp its emitter electrode at 0V, and this abundant current will be in proportion to the line voltage V LINE . A current mirror provides a mirror current to flow through the resistor  232  and to generate the scaled voltage V LINE-IN  across the resistor  232 , such that the mirror current and the scaled voltage V LINE-IN  as well are in proportion to the line voltage V LINE . In other words, the scaled voltage V LINE-IN  is capable of representing the line voltage V LINE . A capacitor  234  and a switch  236  are for holding the line voltage information during an OFF time T OFF . Even though the current drained out from the BJT  230  will become zero during an OFF time T OFF  when the switch  236  is turned OFF, the capacitor  234 , as being isolated from the BJT  230 , holds the gate voltages of the PMOS transistors in the current mirror, such that the current mirror is able to continue providing the mirror current and to build up the scaled voltage V LINE-IN . Therefore, the scaled voltage V LINE-IN  shows no matter it is during an ON time T ON  or an OFF time T OFF . 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.