Abstract:
A video processing apparatus includes: a line-based data encoder for performing line-based data encoding on an input signal to generate a line-based data encoded signal; and a video signal controller coupled to the line-based data encoder for receiving a first video signal and the line-based data encoded signal, decoding the line-based data encoded signal to generate a second video signal, and choosing one of the first and second video signals to generate an output signal.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to digital televisions (TVs), and more particularly, to a video processing apparatus and a method thereof.  
         [0003]     2. Description of the Prior Art  
         [0004]     Within a digital television (TV), a controller chip typically utilizes a blending module to blend video data from different sources, e.g., video frames transmitted from content/service providers, logo information, scrolling banner information, caption information, and/or on-screen display (OSD) information generated by the digital TV. The blended data is then transmitted to a display panel for further display. Real time calculation and display for the video data from these different sources mentioned above require a portion of bus bandwidth of the digital TV.  
         [0005]     An example of typically encoded information transmitted from the content/service provider is subtitle data, including logo information, scrolling banner information, and/or caption information. The subtitle data is decoded by a subtitle decoder and converted into corresponding image data. After certain processing operations such as scaling and/or filtering, the image data is then blended with the other video data mentioned above, e.g. the video frames and the OSD information. The amount of the image data generated in the scaling and filtering processing is considerably large. As a result, the bus bandwidth of the digital TV is heavily occupied, and therefore the overall display performance of the digital TV becomes significantly hindered.  
       SUMMARY OF THE INVENTION  
       [0006]     It is therefore an objective of the claimed invention to provide a video processing apparatus and method, which can alleviate burden imposed upon the bandwidth of an internal bus.  
         [0007]     According to embodiments of the invention, a video processing apparatus is disclosed. The video processing apparatus comprises: an encoder for encoding an input signal to generate an encoded signal; and a blending circuit coupled to the encoder for blending a first video signal and a second video signal corresponding to the encoded signal to generate an output signal.  
         [0008]     According to embodiments of the invention, a video processing method is further disclosed. The video processing method comprises: encoding an input signal to generate an encoded signal; and blending a first video signal and a second video signal corresponding to the encoded signal to generate an output signal.  
         [0009]     According to embodiments of the invention, a video processing apparatus is further disclosed. The video processing apparatus comprises a shared data bus; a data encoder coupled to the shared data bus, for encoding a first video signal and transmitting the encoded first video signal through the shared data bus; a data decoder coupled to the shared data bus, for receiving the encoded first video signal from the shared data bus and decoding the encoded first video signal; and a blending module coupled to the data decoder, for blending the first video signal decoded by the data decoder and a second video signal, to generate a blended video signal.  
         [0010]     These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is a diagram of a video processing apparatus according to one embodiment of the present invention.  
         [0012]      FIG. 2  is a diagram illustrating caption data processed by the line-based data encoder shown in  FIG. 1 .  
         [0013]      FIG. 3  is a diagram illustrating pixel data processed by the line-based data encoder shown in  FIG. 1 . 
     
    
     DETAILED DESCRIPTION  
       [0014]     Please refer to  FIG. 1 .  FIG. 1  is a diagram of a video processing apparatus  100  according to one embodiment of the present invention, wherein the video processing apparatus  100  comprises a subtitle controller  110  and a video signal controller  120 . The subtitle controller  110  comprises a subtitle decoder  112 , a subtitle processing module  114 , and a line-based data encoder  116 , and the video signal controller  120  comprises a line-based data decoder  122  and a blending circuit  124 . In this embodiment, the video processing apparatus  100  is installed in a digital television (TV), wherein the video signal controller  120  is coupled to the subtitle controller  110  through a data bus in the digital TV.  
         [0015]     It should be noted that although the video processing apparatus  100  of this embodiment is installed in the digital TV as mentioned above, those skilled in the art will appreciate that the video processing apparatus  100  can be applied to other products requiring similar video processing, according to other embodiments of the present invention.  
         [0016]     The subtitle decoder  112  shown in  FIG. 1  is utilized for decoding subtitle data  111 , such as caption information, logo information, and/or scrolling banner information, to generate a subtitle decoded signal  113 . In this embodiment, the subtitle processing module  114  is capable of performing processing operations such as scaling and image enhancement calculations, or various other calculation operations for subtitle processing, which are well known to those skilled in the art. After processing such as subtitle decoding and scaling calculation is carried out, a large amount of data will be generated, and then sent to the line-based data encoder  116  for further encoding. According to this embodiment, the line-based data encoder  116  performs line-based data encoding on these data carried on the input signal  115  to generate a line-based data encoded signal  117 , which has less amount of data in contrast to the input signal  115 . The line-based data encoded signal  117  is then sent to the video signal controller  120 , whereby the loading on the bus bandwidth of the digital TV can be saved.  
         [0017]     In this embodiment, the line-based data encoder  116  compresses and encodes one row, or one line, of data (hence line-based), based on each row of pixel data of the image represented by the input signal  115 , for example, the dashed-line-enclosed portion of an embodiment closed caption as shown in  FIG. 2 , and then appends a header to the encoded data, to generate the line-based data encoded signal  117 . As each set of line-based data comprises a header and a set of encoded data, the header can be utilized to distinguish between two sets of encoded data in the line-based data encoded signal  117 . According to this embodiment, the line-based data encoder  116  encodes the input signal  115  according to Huffman encoding algorithm to generate the line-based data encoded signal  117 , and the line-based data decoder  122  is capable of decoding the line-based data encoded signal  117  correspondingly.  
         [0018]     Utilizing each row of pixels as a unit of encoding to perform data compression/encoding is advantageous to the design of the later stage blending circuit  124 . The blending circuit  124  typically blends video data of different sources on a pixel-row, or line, basis, and a display panel of the digital TV typically displays the blended data on a pixel-row basis; that is, data are blended and displayed each row of pixels a time. Therefore, the system architecture and control can be most simplified while utilizing pixel row as unit for data compression/encoding and the corresponding decoding.  
         [0019]     However, such an implementation mentioned above is not meant to serve as a limitation for the present invention. This is merely one of the various implementation choices of the present invention. In another embodiment of the present invention, other kinds of line-based data encoding algorithms such as Run-Length encoding algorithm, JBIG encoding algorithm, and JPEG encoding algorithm, can also be applied to the line-based data encoder, where the line-based data decoder may decode the line-based data encoded signal correspondingly. In other embodiments, the encoding calculations of the encoder in the subtitle controller may adopt some other encoding units, e.g. block-based encoding or others, instead of pixel-row, or line-based encoding, to encode the input signal.  
         [0020]     As shown in  FIG. 1 , the video signal controller  120  receives, through the line-based data decoder  122 , the aforementioned line-based data encoded signal  117 , which is transmitted through the data bus. Additionally, the video signal controller  120  further receives, through the blending circuit  124 , the on-screen display (OSD) signal OSD_sig and the video signal V_sig, which is transmitted through the data bus and corresponds to the video frames. In addition, a video signal  123 , which is generated by the line-based data decoder  122  after the line-based data decoder  122  performs line-based data decoding on the line-based data encoded signal  117 , is also transmitted to the blending circuit  124 . The blending circuit  124  then blends the OSD signal OSD_sig, the video signal V_sig, and the video signal  123  corresponding to the line-based data encoded signal  117 , to generate an output signal  125 , which carries calculation results of the blending calculations performed by the blending circuit  124 . The blending calculations are well known to those skilled in the art, and therefore are not described in detail herein.  
         [0021]     Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating pixel data processed by the line-based data encoder  116  shown in  FIG. 1 . In this embodiment, the input signal  115  comprises a plurality of pixels complying with ARGB specifications, and each pixel comprises pixel values of α, R, G, and B, where the pixel value of α represents transparency. In order to raise the data compression rate, when the α value  221  of a pixel  220  in the input signal  115  appears to be zero, which means that the pixel  220  eventually is not to be shown in the resulting output image and that the R, G, and B values bear no consequence, the pixel values of R, G, and B  222  can then be set so as to increase the compression rate, and hence minimize the data flow through the data bus.  
         [0022]     In one embodiment, when an α value of a pixel is zero, the line-based data encoder  116  sets the R, G, and B values of this pixel according to those of a previous pixel before encoding. For example, when the blending values, e.g. the α values  221  and  231  respectively corresponding to the pixels  220  and  230  in the input signal  115 , are both zero, the line-based data encoder  116  sets the pixel data  222  and  232  (i.e. the R, G, and B values of the pixels  220  and  230 , respectively) to be the same as the pixel data  212  (i.e. the R, G, and B values of the pixels  210 ) before performing the line-based data encoding. In another embodiment, when α values of a plurality of pixels are zero, the line-based data encoder  116  sets the R, G, and B values of these pixels to certain predetermined value before encoding. For example, when the blending values, e.g. the α values  221  and  231 , are zero, the line-based data encoder  116  sets all the values of the pixel data  222  and  232  to be zero before performing the line-based data encoding.  
         [0023]     Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.