Abstract:
A semiconductor device which is capable of shutting off the influence of noise introduced into a reference voltage while preventing an increase in die size. The semiconductor device including a reference potential generator, first and second filter, and first and second input circuit. The reference potential generator generates a reference potential in accordance with a first power supply. The first filter is connected to the first power supply and filters the reference potential to generate a first filtered reference potential. The second filter is connected to a second power supply and filters the reference potential to generate a second filtered reference potential. The first input circuit is connected to the first power supply and receives the first filtered reference potential to generate a first predetermined voltage. The second input circuit is connected to the second power supply and receives the second filtered reference potential to generate a second predetermined voltage.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor device comprising an input circuit which operates in accordance with a reference potential, and more particularly, to countermeasures to noise introduced into a reference potential supplied to a plurality of input circuits.  
           [0002]    Latest semiconductor memory devices receive power from various external power supplies due to the tendency toward an increased number of bits and larger scale of die size. For example, a driver circuit for I/O pads is supplied with power from external dedicated power supplies VccQ, VssQ, while general peripheral function circuits within a device are supplied with power from external general power supplies Vcc, Vss. Among the peripheral function circuits, a circuit for converting the level of a small voltage supplied from an external input pin, and a sense amplifier for discriminating a small potential difference are vulnerable to external noise, so that they are separated from circuits which consume a large amount of power, such as a delay locked loop (DLL) circuit. In this event, wires associated with the power supplies Vcc, Vss for the sense amplifier are separated from pads for the DLL circuit.  
           [0003]    [0003]FIG. 1 is a schematic circuit diagram illustrating a sense amplifier  100  of a semiconductor integrated circuit which is described in Japanese Unexamined Patent Publication No. 2000-11649. The sense amplifier  100  is supplied with an internal supply voltage Vint to a node N 1  via a low pass filter  1 . The node N 1  is connected to an inverter circuit  2 , so that a voltage changing rate at the node N 1  is adjusted in response to a changing rate of a reference voltage Vref supplied to the inverter circuit  2 .  
           [0004]    When the internal supply voltage Vint rises, potentials at nodes N 2 , N 3  once rise, and a potential difference is generated between the nodes N 2  and N 3  based on the internal supply voltage Vint. A latch circuit  3  performs a latch operation in accordance with the potential difference. This configuration prevents the latch operation from starting with unstable voltage levels at the nodes N 2 , N 3 , so that a normal latch signal is output from the latch circuit  3 .  
           [0005]    After the internal supply voltage Vint has risen, the internal supply voltage Vint may be supplied to other circuits. In this event, a consumed current temporarily increases to cause sudden fluctuations in the level of the internal supply voltage Vint. However, high frequency noise caused by the fluctuations in the internal supply voltage Vint is removed by the low pass filter  1 . Therefore, the latch circuit  3  is prevented from erroneous operations due to fluctuations in the internal supply voltage Vint.  
           [0006]    In the sense amplifier  100 , the internal supply voltage Vint is supplied to the inverter circuit  2  via the low pass filter  1 , while the reference voltage Vref is supplied to the inverter circuit  2  without intervention of a low pass filter. In this event, for avoiding the influence of noise in the reference voltage Vref, it is necessary to commonly provide a power supply Vss of a voltage generator circuit for generating the internal supply voltage Vint, a power supply Vss of a reference voltage generator circuit for generating the reference voltage Vref, and a power supply Vss of the sense amplifier. This requirement imposes a large constraint on designing of layouts of the respective generator circuits, sense amplifier and power supply wiring, and results in a larger die size of the device.  
           [0007]    [0007]FIGS. 2 through 5 are schematic circuit diagrams illustrating an internal power supply circuit  200  for a semiconductor integrated circuit described in Japanese Unexamined Patent Publication No. 2000-124797.  
           [0008]    The internal power supply circuit  200  includes a boost power generator circuit  4 , two control voltage generator circuits  5   a ,  5   b , and four power supply circuits  6   a  to  6   d.    
           [0009]    The boost power generator circuit  4  receives power from a power supply Vcc 2  and a power supply Vss 2 , and performs a pumping operation in accordance with an oscillating signal supplied from an oscillator  7  and having a predetermined frequency to generate a boosted voltage Vpp 1 . The boosted voltage Vpp 1  is supplied to the first and second control voltage generator circuits  5   a ,  5   b  which have the same configuration.  
           [0010]    The first control voltage generator circuit  5   a  generates a first control voltage Vg 1  which is higher than the reference voltage Vref by a predetermined voltage based on the boosted voltage Vpp 1  and the power supply Vss 1 . The second control voltage generator circuit  5   b  generates a second control voltage Vg 2  which is higher than the reference voltage Vref by a predetermined voltage based on the boosted voltage Vpp 1  and the power supply Vss 2 .  
           [0011]    The first control voltage Vg 1  is supplied to the power supply circuit  6   b  for a DLL circuit (see FIG. 3). The power supply circuit  6   b  for a DLL circuit receives power from a power supply Vcc 1  and the power supply Vss 1 , and generates a predetermined first internal supply voltage ViiD in accordance with the first control voltage Vg 1 .  
           [0012]    The second control voltage Vg 2  is supplied to the power supply circuit  6   a  or to the power supply circuit  6   d  illustrated in FIG. 5. Each of the power supply circuits  6   a ,  6   d  receives power from the power supply Vcc 2  and the power supply Vss 2 , and generates a second predetermined internal supply voltage ViiS in accordance with the second control voltage Vg 2 .  
           [0013]    The power supply circuit  6   c  illustrated in FIG. 4 generates a supply voltage Viin for other circuits in the DLL circuit. The power supply circuit  6   c  receives power from the power supplies Vcc 1 , Vss 1  or from the power supplies Vcc 2 , Vss 2 , and generates the supply voltage Viin in accordance with the first or second control voltage Vg 1 , Vg 2 .  
           [0014]    Each of the power supply circuits  6   b  to  6   d  has a low pass filter  8  which absorbs noise introduced into each of the control voltages Vg 1 , Vg 2 .  
           [0015]    The internal power supply circuit  200  requires a plurality of control voltage generator circuits  5   a ,  5   b  for supplying corresponding control voltages to the plurality of power supply circuits  6   a ,  6   b ,  6   c ,  6   d  connected to different power supplies. Therefore, a device which requires multiple power supplies for its operations must have multiple control voltage generator circuits laid out therein, thereby causing an increase in the die size of the device.  
         SUMMARY OF THE INVENTION  
         [0016]    It is an object of the present invention to provide a semiconductor device which is capable of shutting off the influence of noise introduced into a reference voltage while preventing an increase in die size.  
           [0017]    In one aspect of the present invention, there is provided a semiconductor device including a reference potential generator circuit for generating a reference potential in accordance with a first power supply, a first filter connected to the reference potential generator circuit and the first power supply for filtering the reference potential to generate a first filtered reference potential, a second filter connected to the reference potential generator circuit and a second power supply for filtering the reference potential to generate a second filtered reference potential, a first input circuit connected to the first filter and the first power supply for receiving the first filtered reference potential to generate a first predetermined voltage, and a second input circuit connected to the second filter and the second power supply for receiving the second filtered reference potential to generate a second predetermined voltage.  
           [0018]    Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]    The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:  
         [0020]    [0020]FIG. 1 is a schematic circuit diagram illustrating a sense amplifier according to a first prior art example;  
         [0021]    [0021]FIG. 2 is a schematic circuit diagram illustrating an internal power supply circuit according to a second prior art example;  
         [0022]    [0022]FIG. 3 is a schematic circuit diagram illustrating a power supply circuit of the internal power supply circuit of FIG. 2;  
         [0023]    [0023]FIG. 4 is a schematic circuit diagram illustrating a power supply circuit of the internal power supply circuit of FIG. 2;  
         [0024]    [0024]FIG. 5 is a schematic circuit diagram illustrating a power supply circuit of the internal power supply circuit of FIG. 2;  
         [0025]    [0025]FIG. 6 is a schematic block diagram illustrating a semiconductor device according to one embodiment of the present invention;  
         [0026]    [0026]FIG. 7 is a schematic circuit diagram illustrating a reference potential generator circuit of the semiconductor device of FIG. 6;  
         [0027]    [0027]FIG. 8 is a schematic circuit diagram illustrating a first input circuit of the semiconductor device of FIG. 6;  
         [0028]    [0028]FIG. 9 is a schematic circuit diagram illustrating a second input circuit of the semiconductor device of FIG. 6;  
         [0029]    [0029]FIG. 10 is an explanatory diagram illustrating a layout of the semiconductor device of FIG. 6;  
         [0030]    [0030]FIG. 11 is an explanatory diagram illustrating another layout of the semiconductor device of FIG. 6; and  
         [0031]    [0031]FIG. 12 is a schematic block diagram illustrating an exemplary modification to the semiconductor device of FIG. 6. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]    In the drawings, like numerals are used for like elements throughout.  
         [0033]    [0033]FIG. 6 is a block diagram generally illustrating a semiconductor device  300  according to one embodiment of the present invention. The semiconductor device  300  includes a reference potential generator circuit  11 , first and second low pass filters  12 ,  14 , and first and second input circuits  13 ,  15 . Each of the circuits  11  to  15  is formed on the same semiconductor substrate, and functions as an input circuit unit of the semiconductor device  300 . The first input circuit  13  is included in a first functional circuit of the semiconductor device  300 , while the second input circuit  15  is included in a second functional circuit.  
         [0034]    The reference potential generator circuit  11  receives power from a high potential power supply Vcc 1  and a low potential power supply Vss 1 , and generates a reference potential Vref. The reference potential Vref is supplied to the first input circuit  13  via the first low pass filter  12  as well as to the second input circuit  15  via the second low pass filter  14 .  
         [0035]    The first low pass filter  12  includes a resistor R 1  and a capacitor C 1 . The capacitor C 1  has a first terminal connected to a node n 1  which is an input terminal of the first input circuit  13 , and a second terminal connected to the power supply Vss 1 . The first input circuit  13  receives power from the high potential power supply Vcc 1  and low potential power supply Vss 1 .  
         [0036]    The second low pass filter  14  includes a resistor R 2  and a capacitor C 2 . The capacitor C 2  has a first terminal connected to a node n 2  which is an input terminal of the second input circuit  15 , and a second terminal connected to a low potential power supply Vss 2 . The second input circuit  15  receives power from a high potential power supply Vcc 2  and the low potential power supply Vss 2 . The low potential power supply Vss 2  is laid out such that it is completely separated from the low potential power supply Vss 1  within the chip of the semiconductor device. However, the low potential power supply Vss 1  and low potential power supply Vss 2  are at the same ground level. In this way, this embodiment employs a different system of low potential power supply for each input circuit.  
         [0037]    As illustrated in FIG. 7, the reference potential generator circuit  11  is a known circuit which includes a differential circuit  16 , an output P-channel MOS transistor Tr 1 , and resistors R 1  to R 3 .  
         [0038]    When the differential circuit  16  is supplied with a constant voltage Vf at a gate of an N-channel MOS transistor Tr 2 , the differential circuit  16  operates such that a potential at a gate of an N-channel MOS transistor Tr 3  matches the constant voltage Vf. With this operation, the predetermined reference potential Vref is generated.  
         [0039]    As illustrated in FIG. 8, the first input circuit  13  generates a first predetermined internal supply voltage Vdd in accordance with the reference potential Vref. The first input circuit  13  includes a differential circuit  17  which receives power from the high potential power supply Vcc 1  and low potential power supply Vss 1 , an inverter circuit  18  connected to the differential circuit  17 , and an output P-channel MOS transistor Tr 4  connected to the differential circuit  17 . The inverter circuit  18  has an input terminal connected to the low potential power supply Vss 1 , and receives power from the low potential power supply Vss 1  and the internal power supply Vdd generated by the first input circuit  13 .  
         [0040]    The filtered reference potential Vref output from the first low pass filter  12  is supplied to a gate of an N-channel MOS transistor Tr 5  in the differential circuit  17 , while an inverted output signal of the inverter circuit  18  is supplied to a gate of an N-channel MOS transistor Tr 6 .  
         [0041]    As illustrated in FIG. 9, the second input circuit  15  generates a second predetermined internal supply voltage Vddi in accordance with the reference potential Vref. The second input circuit  15  includes a differential circuit  19  which receives power from the high potential power supply Vcc 2  and the low potential power supply Vss 2 , an inverter circuit  20  connected to the differential circuit  19 , and an output P-channel MOS transistor Tr 7  connected to the differential circuit  19 . The inverter circuit  20  has an input terminal connected to the low potential power supply Vss 2 , and receives power from the low potential power supply Vss 2  and the internal power supply Vddi generated by the second input circuit  15 .  
         [0042]    The filtered reference voltage Vref output from the second low pass filter  14  is supplied to a gate of an N-channel MOS transistor Tr 8  of the differential circuit  19 , while an inverted output signal from the inverter circuit  20  is supplied to a gate of an N-channel MOS transistor Tr 9 .  
         [0043]    Next, the operation of the semiconductor device  200  will be described.  
         [0044]    The reference potential generator circuit  11 , first low pass filter  12  and first input circuit  13  are supplied with power from the common high potential and low potential power supplies Vcc 1 , Vss 1 . Therefore, when noise occurring in the low potential power supply Vss 1  introduces into the reference potential Vref, the low potential power supply Vss 1  of the first input circuit  13  also includes noise in phase with the reference potential Vref. However, since a threshold of the first input circuit  13  does not vary in relation to fluctuations in the reference potential Vref due to the noise, the first input circuit  13  generates the stable internal supply voltage Vdd.  
         [0045]    When the reference potential Vref fluctuates due to noise in the low potential power supply Vss 1 , the fluctuations are absorbed by the second low pass filter  14 . Therefore, the second input circuit  15  is supplied with the stable reference potential Vref.  
         [0046]    When noise occurs in the low potential power supply Vss 2 , the first input circuit  13  is not at all affected by the noise since the input circuit  13  is not associated with the low potential power supply Vss 2 . Also, when the low potential power supply Vss 2  fluctuates, a potential at the node n 2  varies in phase with the fluctuations in the low potential power supply Vss 2  due to capacitive coupling of the capacitor C 2  of the second low pass filter  14 . Thus, a threshold of the second input circuit  15  does not vary in relation to fluctuations of the output signal of the second low pass filter  14 , allowing the second input circuit  13  to generate the stable internal supply voltage Vddi.  
         [0047]    Next, the layout of the semiconductor device  300  will be described with reference to FIG. 10. The reference potential generator circuit  11 , first low pass filter  12  and first input circuit  13  are supplied with the voltage of the low potential power supply Vss 1  from a pad  21  through a wire L 1 . The first and second low pass filters  12 ,  14  in turn are supplied with the reference potential Vref through a wire L 3 .  
         [0048]    The second low pass filter  14  and second input circuit  15  are supplied with the voltage of the low potential power supply Vss 2  from a pad  22  through a wire L 2 .  
         [0049]    With the layout as described, the first and second input circuits  13 ,  15  are supplied with the reference potential Vref from the common reference potential generator circuit  11  respectively through the first and second low pass filters  12 ,  14 .  
         [0050]    The semiconductor device  300  according to the present invention provides the following advantages.  
         [0051]    (1) Even if noise occurring in the low potential power supply Vss 1  introduces into the reference potential ref, the first input circuit  13  stably generates the internal supply voltage Vdd.  
         [0052]    (2) Even if noise occurs in the reference potential Vref, the noise is absorbed by the second low pass filter  14 , so that the second input circuit  15  is supplied with the stable reference potential Vref. Consequently, the second input circuit  13  stably generates the internal supply voltage Vddi.  
         [0053]    (3) Even if noise occurs in the low potential power supply Vss 2 , the potential at the node n 2  varies in phase with fluctuations in the low potential power supply Vss 2  due to the capacitive coupling of the capacitor C 2  of the second low pass filter  14 . Since the threshold of the second input circuit  15  does not vary in relation to the fluctuations of the voltage of the output signal from the second low pass filter  14  (the potential at the node n 2 ), the second input circuit  13  stably generates the internal power supply Vddi.  
         [0054]    (4) The common reference potential Vref is supplied to each of the input circuits  13 ,  15  from the reference potential generator circuit  11 . This eliminates the need for a plurality of circuits for generating reference voltages, and the need for laying out a plurality of wires for supplying a plurality of reference potentials to a plurality of input circuits, resulting in a reduction in the die size of the device.  
         [0055]    (5) The reference potential Vref is supplied to each of the input circuits  13 ,  15  from the reference potential generator circuit  11 . This eliminates the need for providing a plurality of reference potential generator circuits corresponding to multiple power supplies, resulting in a reduction in the die size of the device.  
         [0056]    It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the invention may be embodied in the following forms.  
         [0057]    (a) As illustrated in FIG. 11, the low potential power supply Vss 1  and low potential power supply Vss 2  may be supplied to the reference potential generator circuit  11 , first and second low pass filters  12 ,  14 , and first and second input circuits  13 ,  15  through a common pad  23  and a plurality of power supply wires L 1 , L 2  independent of each other.  
         [0058]    (b) In the first input circuit  13 , the transistor Tr 6  of the differential circuit  17  may be directly supplied with the internal supply voltage Vdd. Alternatively, the transistor Tr 6  may be supplied with a divided potential which may be generated by resistively dividing the potential difference between the internal supply voltage Vdd and the voltage of the low potential power supply Vss 1 .  
         [0059]    (c) In the second input circuit  15 , the transistor Tr 9  of the differential circuit  19  may be directly supplied with the internal supply voltage Vddi. Alternatively, the transistor Tr 9  may be supplied with a divided potential which may be generated by resistively dividing the potential difference between the internal supply voltage Vddi and the voltage of the low potential power supply Vss 2 .  
         [0060]    (d) As illustrated in FIG. 12, a third low pass filters  31  and a third input circuit  32  may be added. The third low pass filters  31  is connected to the reference potential generator circuit  11  and a low potential power supply Vss 3  the system of which is different from that of the low potential power supplies Vss 1 , Vss 2 . The third input circuit  32  is connected to the third low pass filter  31  and receives power from a high potential power supply Vcc 3  and the low power supply Vss 3 . In this case, the low potential power supplies Vss 1 , Vss 2  and Vss 3  are the same ground power supply.  
         [0061]    (e) The first and second input circuits  13 ,  15  may include circuits other than the differential circuits.  
         [0062]    (f) The resistors of the first and second low pass filters  12 ,  14  may be selected from diffusion resistors, polysilicon resistors and so on.  
         [0063]    (g) The capacitors of the first and second low pass filters  12 ,  14  may be selected from MOS capacitors, metal capacitors and so on.  
         [0064]    Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.