Abstract:
In a memory device, a shift-register comprises a plurality of stages for transferring sequentially a pair of signals which have mutually opposite phases. Each stage has a comparator circuit which compares the pair of signals and generates a pair of fixed voltage signals. By this construction, high-speed operation of the memory device, low power consumptions, and high-capacity load driving are achieved.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a novel electric circuit, and more particularly to a novel shift-register and memory device. 
     Semiconductor memory devices in which shift-registers are included have recently been studied for obtaining a high-speed operation of the device. Some structures have been proposed. There are, however, serious problems in the conventional shift-register when applying it to a device for a high-speed operation. That is, the two characteristics of lower power consumptions and higher load driving capabilities (so called trans-conductance; gm), which are mutually incompatible, are demanded, and the conventional shift-register cannot meet these demands. Further, the output in a high level condition cannot be maintained for a long period using the conventional shift-registers. 
     SUMMARY OF THE INVENTION 
     The present invention solves the problems of conventional shift-registers described above, and makes possible semiconductor memory devices having a high-speed of operation. 
     The first object of this invention is to provide shift-registers capable of a high-speed of operation. 
     The second object of this invention is to provide shift-registers in which both a low power consumption and high-capacity load drive capability are achieved. 
     The third object of this invention is to provide shift-registers which are capable of holding the level of the output signal for a long period of time. 
     The fourth object of this invention is to provide a memory device which operates at a higher speed. 
     These and other objects are accomplished using the following construction. A shift register comprises a plurality of stages for transferring a pair of signals having mutually opposite phases. Each stage has an electric circuit, that is, a comparator circuit to which a pair of input signals having mutually opposite phases are applied for comparing said input signals and for generating a pair of fixed voltage signals according to the result of said comparison. A buffer circuit is providing for receiving said pair of fixed voltage signals and for changing the impedance exchange from higher impedance condition to a lower impedance condition. A latch circuit is provided for holding said pair of fixed voltage signals by means of an electrical latch function. 
     The above construction results in a shift-register having a low power consumptions and a high-capacity load drive capability. The shift-register is capable of holding the level of the output signal for a long period of time, and is a high-speed shift-register applicable to a high-speed semiconductor memory device. 
     While the novel features of the invention are set forth with particularity in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an embodiment of this invention in which the shift-register is applied to a semiconductor memory device. 
     FIG. 2 is a circuit diagram showing the composition of one stage of the shift-register of this invention. 
     FIG. 3 shows a block diagram of a clock generator which generates clock signals φ 1 , φ 2  and φ 3  applied to the shift-register of this invention. 
     FIG. 4 is the timing diagram of clock signals φ 1 , φ 2  and φ 3 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows the basic construction of an embodiment of this invention. Reference number 100 designates a memory array which has a number of memory cells arranged in a matrix. Reference number 102 designates the shift-register which sequentially transmits signals from the input-output circuit 104, and which receives signals transferred from the memory array 100 through the switching circuit 106 and sequentially transmits them to the input-output circuit 104. They are controlled by the clock signals φ 1 , φ 2  and φ 3  generated by clock generator 108. The switching circuit 106 is also controlled by the clock signal φ&#39; also generated from clock generator 108. In this embodiment, in a write mode, an 8-bit signal is supplied to the shift-register 102 from the input-output circuit 104. The signal is transmitted in series by means of the clock signals φ 1 , φ 2  and φ 3 , and each bit-signal is stored in each stage of the shift-register. Next, at the input of clock signal φ&#39; to the switching circuit 106, the signals stored in the stages are transmitted in parallel to the memory array 100 and stored. In a read mode, the signal stored in the memory array 100 is read-out and stored temporarily in each stage of the shift-register 102 when the clock signal φ&#39; is applied to the switching circuit 106. The stored signal is then sequentially transmitted to the input-output circuit 104 at the clock signals φ 1 , φ 2  and φ 3  to shift-register 102. 
     FIG. 2 shows one stage of a shift-register in an embodiment of this invention. Plural numbers of these stages constitute a shift-register. As shown in FIG. 2, each stage is composed of a comparator section C, a buffer section B and a latch section L. 
     FIG. 3 illustrates where the clock signals φ 1 , φ 2  and φ 3  are generated in the clock generator 108 in FIG. 1. The clock signals φ 1 , φ 2  and φ 3  shown in FIG. 4 are generated by means of the outer clock supplied through the input circuit, the buffers 1, 2 and 3, and the inverter. Clock signals φ 1  and φ 2   have opposite phases. Clock signal φ 3  is slightly delayed from signal φ 2 . 
     Operation of the shift-register composed as shown in FIG. 2 is explained in detail in the following: 
     In FIG. 2, the input signals I and I, from the input-output circuit 104, having mutually opposite phases, are applied to the gates of MOS transistors Q 3  and Q 4  which are the input points of the dynamic comparator C, via the transfer gates of the MOS transistors Q 1  and Q 2  which consist of MOS transistors. 
     When the first clock signal φ 1  is in an &#34;H&#34; level, the input signals I and I are transmitted to the gates of the MOS transistor Q 3  and Q 4  respectively. Since the first clock signal φ 1  is in an &#34;H&#34; level (=Vcc), and the second clock φ 2  is in an &#34;L&#34; level in the comparator C at this time, and nodes N 3 , N 4 , and N 5  are charged up at a potential lower by the threshold voltage of MOS transistors than the power source voltage. Thus, since the nodes N 3  and N 4  are in an &#34;H&#34; level, and the second clock signal φ 2  is in an &#34;L&#34; level, both nodes N 1  and N 2  are in an &#34;L&#34; level notwithstanding the input signals. 
     Under this condition, if the input signals I and I are &#34;H&#34; and &#34;L&#34; levels respectively, MOS transistor Q 3  is ON and MOS transistor Q 4  is in an OFF state. If the first clock signal φ 1  becomes &#34;L&#34; next, the MOS transistors Q 1  and Q 2  become OFF, and at the gates of the MOS transistors Q 3  and Q 4 , the information of the input signals I and I are sustained, and these conditions of the MOS transistors Q 3  and Q 4  would not be affected during the period when the first clock signal φ 1  is kept at an &#34;L&#34; level regardless of the conditions of input signals I and I. Furthermore, the electric charges are held at the nodes N 3 , N 4 , and N 5  because the MOS transistors Q 11 , Q 12  and Q 13  are in an OFF state. 
     The second clock signal φ 2  is then shifted from an &#34;L&#34; to &#34;H&#34; level, and the potentials of nodes N 1  and N 2  to rise since the MOS transistors Q 9  and Q 10  are in an ON state. In this situation, since MOS transistor Q 3  is ON, and MOS transistor Q 4  is in OFF, the electrical potential of node N 2  rises faster than that of the node N 1 . Therefore, MOS transistors Q 5  and Q 7  reach an ON state earlier than Q 6  and Q 8 , and the potential rising of node N 1  is suppressed, and at the same time, the charges stored at node N 3  are discharged through MOS transistor Q 5 . As a result the potential of node N 3  decreases, and therefore, MOS transistor Q 9  is turned OFF, and the potential of node N 1  reduces also. 
     On the other hand, no discharge takes place at node N 4 , since the potential of N 1  would not rise high enough to turn MOS transistor Q 6  ON, and since node N 4  is in a high impedance condition. Furthermore, due to the gate capacitance coupling effect at transistor Q 10 , the node N 4  potential rises from the initial potential which is lower, by the threshold voltage of the MOS transistor, than the source voltage when the second clock becomes &#34;H&#34; level. 
     Therefore, when the input signal I is at an &#34;H&#34; level, node N 4  is at an &#34;H&#34; level, and node N 3  is at an &#34;L&#34; level. When the input I is at an &#34;H&#34; level, the results should be reversed. In the above described circuit operations, there exist no current paths which consume electric current constantly, that is, there are no current paths between Vcc and ground. 
     Since the comparison of input signal is performed by setting either one of the nodes N 3  or N 4  at an &#34;L&#34; level, and the feedback at the &#34;H&#34; level side is applied to the node on the &#34;L&#34; level side, and the comparison can be performed at high speed. 
     When the third clock signal φ 3  is then changed from an &#34;L&#34; to an &#34;H&#34; level, the MOS transistors Q 14  -Q 17  of the buffer B come into operation. At the initial condition, since both nodes N 3  and N 4  are at an &#34;H&#34; levels, MOS transistors Q 16  and Q 17  are in an ON state, and nodes N 6  and N 7  are, the same as the third clock signal φ 3 , at an &#34;L&#34; level. When the input I is at an &#34;H&#34; level, since the node N 3  is at an &#34;L&#34;, and node N 4  is at an &#34;H&#34; level after the comparison is made, MOS transistor Q 16  is turned OFF, and the other MOS transistor Q 17  is in turned ON conditions. 
     Therefore, when the third clock signal φ 3  rises to an &#34;H&#34; level, the potential of the node N 7  rises. At this time, due to the gate capacitance coupling effect of the MOS transistor Q 17 , the potential of node N 4  rises to a higher potential than the potential which is reduced by the threshold voltage of the MOS transistor from the source voltage, and the node N 7  potential rises to the source voltage. 
     On the other hand, the MOS transistors Q 18  and Q 19  are turned ON through MOS transistors Q 20  and Q 21  because the second clock signal φ 2  is at an &#34;H&#34; level. As a result, the potentials of nodes N 6  and N 7  are, as the output signal O and O, transmitted to the succeeding next stage. As the case above, because of the gate capacitance coupling effects of MOS transistor Q 19 , the output signal O maintains the source voltage potential. By utilizing the buffers which can change the impedance condition from a higher to a lower state, driven by the third clock signal φ 3 , the output O and O can drive a high capacitance load at high speed. 
     When the first clock signal φ 1 , by means of the outer clock, is returned from an &#34;L&#34; to an &#34;H&#34; level, the MOS transistors Q 1  and Q 2  which constitute the transfer gate are turned ON, and the input signals are again transmitted to the input of the comparator C. This dynamic comparator then starts, preparing for the coming comparator operation by the precharging of N 3 , N 4 , and N 5 . 
     Then, as shown in FIG. 4, by means of the first clock signal φ 1 , the second clock signal φ 2  goes to an &#34;L&#34; from an &#34;H&#34; level, and slightly later, the third clock signal φ 3  goes to an &#34;L&#34; level from an &#34;H&#34; level, and the buffer B returns to its standby condition (i.e., reset to initial condition) ready for the coming amplification. The reason the timing of clock signal φ 3  is delayed after that of φ 2  is that if clock signal φ 3  goes to an &#34;L&#34; level before clock signal φ 2  goes to an &#34;L&#34; level, the charges indicating the &#34;H&#34; level of the output will discharge to ground through Q 14  and Q 15 . In this case, in order to maintain the output signal O and O, the latch circuit L comprising MOS transistors Q 22  -Q 25  operates to hold the output signal O at an &#34;H&#34; level and the other output signal O at an &#34;L&#34; level at low impedance conditions. 
     In order to transfer the output signal to another circuit, for example, the next stage of the shift-register or the memory array, it is required to maintain for a long period the &#34;H&#34; level of the output signal O and O at the source voltage. In order to do this, a voltage higher than the source voltage, by the amount of the threshold voltage of MOS transistor, must be applied to the gates of MOS transistor Q 24  and Q 25 . In order to accomplish such a function, in this embodiment, a pumping circuit comprised of a oscillator circuit OSC, MOS transistors Q 26  -Q 28 , and a capacitor C 1  is added to the latch circuit L. By means of this pumping circuit, the decrease in the holding period of the output voltage at an &#34;H&#34; level due to minute leakage can also be overcomed. It should be noted that if it is not required to maintain the &#34;H&#34; level, the pumping circuit is not needed. 
     With the present invention, when the input signal is taken in by means of the first clock signal φ 1 , and by means of the second clock signal φ 2 , the output of the dynamic type comparator can be confirmed. However, because of the dynamic type, no penetration current is drained as set forth above. The buffer is then driven, by means of the third clock signal φ 3 , to change from a higher impedance to a lower impedance condition and to amplify the output of the dynamic comparator. 
     As explained above, the operations of the comparator and the amplifier are performed independently, and therefore, even with a high capacitance load, a high speed operation is possible. Moreover, since a latch circuit is provided at the output, even when the third clock signal φ 3  goes to an &#34;L&#34; level, the output is connected to the power source or the ground potential at a low impedance, and there is no limitation for the output holding period. Furthermore, because of the dynamic type, the occupation area in a semiconductor chip can be minimized. 
     Therefore, according to this invention, a shift register which operates on low power consumption, is capable of driving a high capacitance load at a high speed, and has no limitation on the output holding time. 
     While specific embodiments of the invention have been illustrated and described herein, it is realized that modifications and changes will occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all modifications and changes as fall within the true spirit and scope of the invention.