Abstract:
A semiconductor circuit for testing a logic circuit, the semiconductor circuit including: an exclusive OR circuit receiving an input testing signal to a circuit under testing and a output testing signal from the circuit under testing; a multiplexer receiving a result signal output from the exclusive OR circuit and a clock signal; and a flip-flop storing a logical value represented by a captured signal in synchronization with a multiplexed signal output from the multiplexer, the captured signal being selected from a entered signal(I) and a data signal that is output from another semiconductor circuit for testing.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application NO. 2010-132342 filed on Jun. 9, 2010, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a semiconductor integrated circuit. 
       BACKGROUND 
       [0003]    Miniaturization of integrated circuits is increasing the probability of frequent resistive open defects, which cause delay faults (malfunctions of circuits caused by signal delay), in circuits. Since a resistive open defect, unlike a full open defect, does not prevent a signal from flowing through the circuit, the impact of a resistive open defect on the behavior of the circuit that is seemingly properly operating at the factory may become noticeable in use after the shipment of the circuit. Therefore resistive open defects need to be adequately eliminated prior to shipment of circuits. 
         [0004]    Logic testing using an automatic test pattern generation tool such as an automatic test pattern generator (ATPG) is being commonly used for testing integrated circuits. Techniques relating to circuit testing are disclosed in Japanese Laid-Open Patent Publication Nos. 2007-139603 and 2007-263790, for example. 
         [0005]    However, while the logic testing using ATPG is effective for detection of stuck-at faults in which a logical value input into or output from a particular element is stuck at 0 or 1, the logic testing is not useful for detecting delay faults. This is because the ATPG generates test patterns from function-level circuit information and therefore does not assume delay faults at all. 
       SUMMARY 
       [0006]    According to one aspect of the embodiments, there is provided a semiconductor circuit for testing a logic circuit, the semiconductor circuit including: an exclusive OR circuit receiving an input testing signal to a circuit under testing and a output testing signal from the circuit under testing; a multiplexer receiving a result signal output from the exclusive OR circuit and a clock signal; and a flip-flop storing a logical value represented by a captured signal in synchronization with a multiplexed signal output from the multiplexer, the captured signal being selected from a entered signal(I) and a data signal that is output from another semiconductor circuit for testing. 
         [0007]    The object and advantages of the embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0008]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the embodiments, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0009]      FIG. 1  is a diagram schematically illustrating an exemplary configuration of a semiconductor integrated circuit according to an embodiment of the present invention; 
           [0010]      FIG. 2  is a diagram illustrating an exemplary configuration of a testing circuit according to an embodiment of the present invention; 
           [0011]      FIG. 3  is a diagram illustrating an initialization procedure; 
           [0012]      FIG. 4  is a diagram illustrating a test pattern input procedure; and 
           [0013]      FIG. 5  is a diagram illustrating a detection result output procedure. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0014]    Embodiments of the present invention will be described with reference to drawings.  FIG. 1  schematically illustrates an exemplary configuration of a semiconductor integrated circuit according to an embodiment of the present invention. The semiconductor integrated circuit  1  in  FIG. 1  has (includes) one or more built-in testing circuits  10 . The testing circuit(s)  10  is (are) redundant circuit(s) that does (do) not affect or contribute to the functionality of the semiconductor integrated circuit  1 . That is, the testing circuit(s)  10  is (are) circuit(s) for detecting primarily delay faults caused by resistive open defects in parts (parts to be tested, or parts under test) of the semiconductor integrated circuit  1  other than the testing circuit(s)  10 . 
         [0015]      FIG. 2  illustrates an exemplary configuration of testing circuits according to an embodiment of the present invention. Illustrated in  FIG. 2  are a multiple testing circuits  10   a ,  10   b , . . . ,  10   x . The testing circuits  10  are associated with different parts to be tested. For example, the testing circuit  10   a  is associated with a wiring line L 1  that is to be tested by the testing circuit  10   a . The other testing circuits  10  are associated with other wiring lines to be tested, not shown. A part in which a resistive open defect may occur is chosen as a part to be tested. 
         [0016]    Each testing circuit  10  includes an exclusive OR (XOR) circuit  11 , a multiplexer (MUX)  12 , a flip-flop (FF)  13 , and other components. When the components are to be distinguished among the testing circuits  10  herein, letters (a, b, . . . , x) appended to the reference numerals of the testing circuits  10  will be added to the reference numerals of the components. 
         [0017]    The exclusive OR circuit  11  receives a signal at the input of a part under test (input signal Va) and a signal at the output of the part under test (output signal Vb) and outputs a signal Vc representing the exclusive OR of values represented by the two signals. The multiplexer  12  receives the signal Vc output from the exclusive OR circuit  11  and a clock signal CLK and selectively outputs one of the input signals according to a control input SEL. The flip-flop  13  is a D flip-flop including a data input terminal D, a clock terminal C and a data output terminal Q. A signal output from the multiplexer  12  is input to the clock terminal C. Accordingly, the flip-flop  13  takes in a value represented by a data input signal I at the data input terminal D, stores the value, and outputs a signal representing a value that has been stored in the flip-flop  13  from the data output terminal Q in synchronization with a rising edge of the signal output from the multiplexer  12 . 
         [0018]    The multiple flip-flops  13  of the multiple testing circuits  10  in  FIG. 2  form a shift register. That is, the flip-flops  13  are cascaded so that data stored in each flip-flop  13  is shifted. In the shift register, a multiplexer  14  is provided between the data output terminal Q of the preceding flip-flop  13  (on the input side) and the input terminal D of the next flip-flop  13  (on the output side). For example, a multiplexer  14   b  is provided between a flip-flop  13   a  and a flip-flop  13   b . Each multiplexer  14  receives a signal output from the preceding flip-flop  13  and a data input signal I and selectively outputs one of the input signals according to a control input SEL. The signal output from the multiplexer  14  is input to the input terminal Q of the next flip-flop  13 . 
         [0019]    While multiple testing circuits  10  are illustrated in  FIG. 2 , only a single testing circuit  10  may be included in the semiconductor integrated circuit  1  if the semiconductor integrated circuit  1  has only one part to be tested. 
         [0020]    A procedure for detecting a resistive open defect in the semiconductor integrated circuit  1  using the testing circuit  10  will be described below. The detection procedure includes an initialization procedure, a test pattern input procedure and a detection result output procedure. 
         [0021]      FIG. 3  illustrates the initialization procedure. In the initialization procedure, the value of the data input signal I is set to “0”. And the value of the control signal “SEL” is set to “1”, Mux  12  output input clock signal “CLK”. Accordingly, the data input signal I representing 0 is applied (input) to the first flip-flop  13   a . A control input SEL for causing each multiplexer  12  to output a clock signal CLK illustrated at the top right of  FIG. 3  is input into the multiplexer  12 . Further, a control input SEL for causing each multiplexer  14  to output a signal output from the preceding flip-flop  13  is input into the multiplexer  14 . 
         [0022]    As a result, the value (“0”) of the data input signal I is shifted from one flip-flop  13  to the next on a rising edge of the clock signal CLK and is output from the data output terminal Q of the last flip-flop  13   x  (at the last stage). Consequently, a 0 is stored in each flip-flop  13 . The pattern of the signal output from the data output terminal Q of the flip-flop  13   x  may be observed to determine whether there is any abnormality in each testing circuit  10 . That is, if consecutive 0s are detected, it may be determined that there is no abnormality in the testing circuits  10 . 
         [0023]    In the initialization procedure, the data input signal I is always set to “0” or always set to “1”. In either case, it may be determined whether or not there is an abnormality in the testing circuits  10  on the basis of whether or not a pattern output from the output terminal Q of the flip-flop  10   x  is the same as the input pattern of the data input signal I. However, the same values, 0s or 1s, are stored in all of the flip-flops  13  at the end of the initialization procedure. In the present embodiment, 0s are stored in the flip-flops  13  at the end of the initialization procedure. 
         [0024]      FIG. 4  illustrates the test pattern input procedure. In the test pattern input procedure, a test pattern is applied to the semiconductor integrated circuit  1 . The test pattern is a signal for testing (test signal). For example, a test pattern generated by an automatic test pattern generator (ATPG) may be used. However, the test pattern is not limited to a predetermined one; any signal pattern with varying signal values may be used. 
         [0025]    A data input signal I representing “1” is applied to the testing circuits  10 . The value (“1”) of the data input signal I is constant throughout the test pattern input procedure. A control signal SEL, is set to “0”, for causing each multiplexer  12  to output a signal output from the exclusive OR circuit  11  is input in the multiplexer  12 . Furthermore, a control input SEL for causing each multiplexer  14  to output the data input signal I is input in the multiplexer  14 . 
         [0026]    If a resistive open defect has occurred in the wiring line L 1 , displacements occurs between the input single Va and the output signal Vb as illustrated at top right of  FIG. 4 . The exclusive OR circuit  11   a  outputs an output signal Vc representing “1” during the periods of the displacements. 
         [0027]    As a result, the flip-flop  13   a  stores a 1, which is the value of the data input signal I, on a rising edge of the output signal Vc. If a resistive open defect has occurred in another part under test, the same operation is performed in the testing circuit  10  associated with the part under test. 
         [0028]    Upon completion of the application of the test pattern, the test pattern input procedure ends. The flip-flop  13  of the testing circuit  10  associated with a part under test where a resistive open defect has been detected contains a “1” at the end of the test pattern input procedure. 
         [0029]      FIG. 5  illustrates the detection result output procedure. In the detection result output procedure, the value of the data input signal I is set to “0”. And the value of the control signal “SEL” is set to “1”, Mux  12  output input clock signal “CLK” same as the initialization procedure. Accordingly, the data input signal representing “0” is applied (input) to the first flip-flop  13   a  (at the first stage). A control input SEL for causing each multiplexer  12  to output a clock signal CLK illustrated at top right of  FIG. 5  is input into the multiplexer  12 . Furthermore, a control input SEL for causing each multiplexer  14  to output a signal output from the preceding flip-flop  13  is input in the multiplexer  14 . 
         [0030]    As a result, the values in the flip-flops  13 s are shifted from one flip-flop  13  to the next on a rising edge of the clock signal CLK and are output from the data output terminal Q of the last flip-flop  13   x  (at the last stage) in sequence. A signal O output from the data output terminal Q may be observed to detect whether or not there is a resistive open defect and if there is a resistive open defect, the resistive open defect may be located. Specifically, if an output signal O that represents “1” is detected, it indicates that a resistive open defect has occurred. Furthermore, the testing circuit  10  that has detected the resistive open defect, and therefore the part under test where the resistive open defect has been detected, may be identified on the basis of the timing of output of a 1 (that is, what number in order a 1 has been output). 
         [0031]    If the value of each flip-flop  13  is initialized to “1” at the end of the initialization procedure, the value of the data input signal I in the test pattern input procedure may be set to “0” and the value of the data input signal I in the detection result output procedure may be set to “1”. That is, the value of the data input signal I in the test pattern input procedure may be set to a value different from the initial value in the flip-flops  13 . The value of the data input signal I in the detection result output procedure may be set to the same value as the initial value in the flip-flops  13 . 
         [0032]    As has been described above, according to the present embodiments, delay faults in a semiconductor integrated circuit may be properly detected. Test patterns are not limited to predetermined ones. Therefore, test patterns generated by an ATPG may be used to conduct testing relating to delay faults while performing logic testing (for detecting primarily stuck-at faults) conventionally widely used. 
         [0033]    Any part of the semiconductor integrated circuit  1  may be tested. 
         [0034]    Having described embodiments of the present invention, the present invention is not limited to the specific embodiment and various changes and modifications may be made without departing from the spirit of the present invention as defined in the claims. 
         [0035]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a depicting of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.