Abstract:
A semiconductor device having a plurality of interconnection layers includes signal lines formed of copper according to a single damascene process, vias formed of tungsten beneath the signal lines according to a single damascene process, and power and ground lines and vias therebeneath formed of copper according to a dual damascene process. Since copper has a better heat radiating capability than tungsten, the vias in all the layers have a better heat radiating capability than those formed of tungsten.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and a method of manufacturing interconnections thereof, and more particularly to a semiconductor device having a damascene structure and a method of manufacturing interconnections thereof. 
     2. Description of the Related Art 
     The damascene technology used in processes of fabricating semiconductor devices is capable of easily planarizing interlayer insulation films and forming interconnections, and is applicable to the formation of interconnections made of conductive materials such as copper (Cu), etc. which are difficult to etch according to reactive ion etching (RIE). 
     Damascene structures include a single damascene structure and a dual damascene structure. The single damascene structure is produced by embedding a conductive layer in a via hole and an interconnection groove by film deposition, and then polishing off an excessive deposit of the conductive layer to produce a via hole filling and an interconnection separately. The dual damascene structure is produced by forming a groove in a region where a via hole and an interconnection will be produced, embedding a conductive layer in the groove by film deposition, and then polishing off an excessive deposit of the conductive layer to produce a via hole filling and an interconnection simultaneously. 
     A process of fabricating a semiconductor device according to the single damascene technology will be described below with reference to FIGS. 1 a  through  1   j  of the accompanying drawings. 
     First, as shown in FIG. 1 a , oxide film  102  is deposited on silicon substrate  101  with circuit components formed therein. INTERCONNECTIONS THEREOF 
     Then, as shown in FIG. 1 b,  groove  103  is formed by etching in a portion of oxide film  102  where a contact will be produced. 
     As shown in FIG. 1 c,  barrier layer  104  is deposited on the entire surface of oxide film  102  including groove  103 . 
     As shown in FIG. 1 d,  conductive layer  105  of tungsten is deposited on barrier layer  104 , thereby embedding tungsten in groove  103 . 
     Thereafter, the entire assembly is polished by CMP (Chemical Mechanical Polishing) to remove conductive layer  105  and barrier layer  104  except groove  103 , thus  25  producing contact  106  in groove  103 , as shown in FIG. 1 e.    
     Then, as shown in FIG. 1 f,  oxide film  107  is deposited on oxide film  102  with contact  106  provided therein. 
     As shown in FIG. 1 g,  groove  108  is formed by etching in oxide film  107  over contact  106 . 
     As shown in FIG. 1 h,  barrier layer  109  is deposited on the entire; surface of oxide film  107  including groove  108 . 
     Then, as shown in FIG. 1 i,  conductive layer  110  of copper is deposited on barrier layer  109 , thereby embedding copper in groove  108 . 
     Thereafter, the entire assembly is polished by CMP to remove conductive layer  110  and barrier layer  109  except groove  108 , thus producing interconnection  111  in groove  108 , as shown in FIG. 1 j.    
     The above successive steps of the process produce a semiconductor device having a single damascene structure. If a semiconductor device comprising a plurality of layers is to be fabricated according to the single damascene technology, then the above process is repeated to produce a semiconductor device of single damascene structure which comprises a plurality of layers. 
     A process of fabricating a semiconductor device according to the dual damascene technology will be described below with reference to FIGS. 2 a  through  2   f  of the accompanying drawings. 
     First, as shown in FIG. 2 a,  contact  106  and interconnection  111  are formed according to the single damascene technology as shown in FIGS. 1 a  through  1   j.    
     Then, as shown in FIG. 2 b,  oxide film  112  is deposited on oxide film  107  with interconnection  111  formed therein. 
     Then, as shown in FIG. 2 c,  groove  113  is formed by etching in a portion of oxide film  112  where a via and an interconnection will be produced. 
     As shown in FIG. 2 d,  barrier layer  114  is deposited on the entire surface of oxide film  112  including groove  113 . 
     As shown in FIG. 2 e,  conductive layer  115  of copper is deposited on barrier layer  114 , thereby embedding copper in groove  113 . 
     Thereafter, the entire assembly is polished by CMP to remove conductive layer  115  and barrier layer  114  except groove  113 , thus producing via  116  and interconnection  117 , as shown in FIG. 2 f.    
     The above successive steps of the process produce a semiconductor device having a dual damascene structure. If a semiconductor device comprising a plurality of layers is to be fabricated according to the dual damascene technology, then the above process as shown in FIGS. 2 b  through  2   f  is repeated to produce a semiconductor device of dual damascene structure which comprises a plurality of layers. 
     A semiconductor device which comprises a plurality of layers includes a portion where interconnections and vias are formed linearly across several layers for heat radiation. 
     A semiconductor device which comprises a plurality of layers that has been fabricated according to the single damascene technology only will be described below with reference to FIG. 3 of the accompanying drawings. 
     As shown in FIG. 3, the semiconductor device comprises silicon substrate  101 , contact  121   a  of tungsten and vias  121   b - 121   e  of tungsten, and interconnections  122   a - 122   e  of copper. Contact  121   a , vias  121   b - 121   e,  and interconnections  122   a - 122   e  are deposited linearly on silicon substrate  101 . 
     Tungsten has a relatively low heat conduction capability. 
     Therefore, the interconnection structure shown in FIG. 3 is liable to suffer thermal breakdown, thermal runaway, and latch-up, and has low ESD (Electrostatic Discharge) resistance. 
     A semiconductor device which comprises a plurality of layers that has been fabricated according to the dual damascene technology only will be described below with reference to FIG. 4 of the accompanying drawings. 
     As shown in FIG. 4, the semiconductor device comprises silicon substrate  101 , contact  121   a  of tungsten and vias  131   a - 131   d  of copper, and interconnections  122   a - 122   e  of copper. Contact  121   a , vias  131   a - 131   d , and interconnections  122   a - 122   e  are deposited linearly on silicon substrate  101 . 
     Copper is of weak tensile strength and weak mechanical strength. 
     Therefore, when the semiconductor device with linearly arranged vias  131   a - 131   d  undergoes a bonding process, the region where vias  131   a - 131   d  are formed is apt to be broken under the bonding pressure. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a semiconductor device which has large mechanical strength and excellent heat radiation capability, and a method of fabricating such a semiconductor device. 
     According to the present invention, a semiconductor device having a plurality of interconnection layers includes signal lines formed of copper according to a single damascene process, vias formed of tungsten beneath the signal lines according to a single damascene process, and power and ground lines and vias therebeneath formed of copper according to a dual damascene process. Since copper has a better heat conduction capability than tungsten, the semiconductor device has a better heat radiating capability than if the vias in all the layers were formed of tungsten. 
     The vias formed of copper beneath the power and ground lines have inside diameters greater than the inside diameters of the vias formed of tungsten beneath the signal lines by a predetermined proportion. The proportion is such that the mechanical strength of the vias formed beneath the power and ground lines is equal to or greater than the mechanical strength of the vias formed beneath the signal lines (specifically, greater by 12.9 times). Therefore, a reduction in the mechanical strength due to the vias being formed of copper is suppressed. 
     According to the present invention, furthermore, a semiconductor device having a plurality of at least six interconnection layers formed on a semiconductor substrate includes vias formed of tungsten in the first through third interconnection layers according to a single damascene process, interconnections formed of copper in the first through third interconnection layers according to a single damascene process, and vias and interconnections formed of copper in the interconnection layers higher than the third interconnection layer according to a dual damascene process. Since copper has a better heat conduction capability than tungsten, the semiconductor device has a better heat radiating capability than if the vias in all the layers were formed of tungsten. 
     The vias formed of copper in the interconnection layers higher than the third interconnection layer have inside diameters greater than the inside diameters of the vias formed of tungsten in the first through third interconnection layers by a predetermined proportion. The proportion is such that the mechanical strength of the vias in the interconnection layers higher than the third interconnection layer is equal to or greater than the mechanical strength of the vias in the first through third interconnection layers (specifically, greater by 12.9 times). Therefore, a reduction in the mechanical strength due to the vias being formed of copper is suppressed. 
     The above proportion determines not only the inside diameters of the vias formed of copper, but the number of vias in a location for interconnecting interconnection layers if the inside diameters of all the vias are equal to each other. 
     The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 a  to  1   j  are fragmentary cross-sectional views illustrative of a process of fabricating a semiconductor device according to the single damascene technology; 
     FIGS. 2 a  to  2   f  are fragmentary cross-sectional views illustrative of a process of fabricating a semiconductor device according to the dual damascene technology; 
     FIG. 3 is a fragmentary cross-sectional view of a semiconductor device which comprises a plurality of layers that has been fabricated according to the single damascene technology only; 
     FIG. 4 is a fragmentary cross-sectional view of a semiconductor device which comprises a plurality of layers that has been fabricated according to the dual damascene technology only; 
     FIG. 5 a  is a plan view of a semiconductor device according to the present invention; 
     FIG. 5 b  is a fragmentary cross-sectional view of a portion of the semiconductor device shown in FIG. 5 a  which as an input/output buffer; 
     FIG. 6 is a graph showing the mechanical strengths of various materials depending on the temperature; 
     FIG. 7 is a graph showing the thermal conductivities of the materials; 
     FIG. 8 is a graph showing the ESD resistance of the semiconductor device shown in FIGS. 5 a  and  5   b  depending on the number of vias of tungsten; 
     FIG. 9 is a graph showing the dynamic strength of the semiconductor device shown in FIGS. 5 a  and  5   b  depending on the number of vias of tungsten; 
     FIGS. 10 a  to  10   k  are fragmentary cross-sectional views illustrative of steps of forming a first layer in a process of fabricating the semiconductor device shown in FIGS. 5 a  and  5   b;    
     FIGS. 11 a  to  11   l  are fragmentary cross-sectional views illustrative of steps of forming second and third layers in the process of fabricating the semiconductor device shown in FIGS. 5 a  and  5   b;    
     FIGS. 12 a  to  12   i  are fragmentary cross-sectional views illustrative of steps of forming fourth through sixth layers in the process of fabricating the semiconductor device shown in FIGS. 5 a  and  5   b;    
     FIG. 13 is a schematic illustration of an embodiment in which copper vias outnumber tungsten vias by at least a factor of  13 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 5 a  shows in plan a semiconductor device according to the present invention. As shown in FIG. 5 a,  the semiconductor device has substrate  1  supporting thereon memory cells  2 , clock driver  3 , and input/output buffers  4  disposed in peripheral portions of substrate  1 . As shown in FIG. 5 b,  each of the portions of substrate  1  which has one of input/output buffers  4  includes a plurality of vias arranged linearly across a plurality of layers. 
     Substrate  1  comprises silicon substrate  10 , contact  11  of tungsten, interconnection  13   a  as a signal line of copper connected by contact  11  to transistors  12   a,    12   b  formed on silicon substrate  10 , via  14   a  of tungsten formed on interconnection,  13   a,  interconnection  13   b  as a signal line of copper connected to interconnection  13   a  by via  14   a,  via  14   b  of tungsten formed on interconnection  13   b,  interconnection  13   c  as a signal line of copper connected to the interconnection  13   b  by via  14   b,  via  15   a  of copper formed on interconnection  13   c,  interconnection  13   d  as a power line or ground line of copper connected to interconnection  13   c  by via  15   a,  via  15   b  of copper formed on interconnection  13   d,  interconnection  13   e  as a power line or ground line of copper connected to interconnection  13   d  by via  15   b,  via  15   c  of copper formed on interconnection  13   e,  and interconnection  13   f  as a power line or ground line of copper connected to interconnection  13   e  by via  15   c.  Contact  11  and interconnection  13   a  jointly make up a first layer. Via  14   a  and interconnection  13   b  jointly make up a second layer. Via  14   b  and interconnection  13   c  jointly make up a third layer. Via  15   a  and interconnection  13   d  jointly make up a fourth layer. Via  15   b  and interconnection  13   e  jointly make up a fifth layer. Via  15   c  and interconnection  13   f  jointly make up a sixth layer. Insulating films  16  are formed in the first layer to the sixth layer each. The first through third layers are of a single damascene structure, and the fourth through sixth layers of a dual damascene structure. 
     The relationship between the diameters and numbers of contact  11 , vias  14   a,    14   b,  and vias  15   a  through  15   c  will be described below. 
     Copper has a greater coefficient of thermal expansion than tungsten, and tungsten has a greater Young&#39;s modulus than copper. Based on these two characteristics, the mechanical strengths of tungsten and copper depending on the temperature are determined. 
     As shown in FIG. 6, tungsten has a thermal stress of 1.607 N/cm2 while copper has a thermal stress of 20.64 N/cm2. Therefore, in order to achieve a strength equal to or greater than the strength of tungsten with copper, it is necessary that the size of copper be at least 12.9 times greater than the size of tungsten. 
     As shown in FIG. 7, tungsten has a thermal conductivity of 1.60 J/K·g·cm·sec. while copper has a thermal conductivity of 3.86 J/K·g·cm·sec. Therefore, if the size of copper is at least 0.42 times greater than the size of tungsten, then it is possible to provide a sufficient heat radiating capability. 
     Based on the thermal stresses shown in FIG.  6  and the thermal conductivities shown in FIG. 7, if the area of vias  15   a - 15   c  of copper shown in FIG. 5 b  is 12.9 times greater than the area of contact  11  and vias  14   a ,  14   b  of tungsten, then the mechanical strength of vias  15   a - 15   c  can be made equivalent to the mechanical strength of vias  14   a,    14   b,  and a sufficient heat radiating capability can be provided. 
     FIG. 8 shows the ESD resistance of the semiconductor device shown in FIGS. 5 a  and  5   b  depending on the number of vias of tungsten. 
     Generally, the ESD resistance of semiconductor devices is sufficient if it is 10 V, which is twice the power supply voltage of 5 V, or higher. 
     As shown in FIG. 8, the ESD resistance is sufficient if the number of vias of tungsten is  3  or less. 
     FIG. 9 shows the dynamic strength of the semiconductor device shown in FIGS. 5 a  and  5   b  depending on the number of vias of tungsten. 
     If the number of vias of tungsten is 3 or less based on the ESD resistance shown in FIG. 8, then the dynamic strength of the semiconductor device is about 7 PSI as shown in FIG. 9, which is of a sufficient level. 
     A process of fabricating the semiconductor device shown in FIGS. 5 a  and  5   b  will be described below with reference to FIGS. 10 a  through  10   k,  FIGS. 11 a  through  11   l , and FIGS. 12 a  through  12   i.    
     As shown in FIG. 10 a,  oxide film  21  is formed on silicon substrate  10 . 
     Then, as shown in FIG. 10 b,  groove  22  is formed by etching in a portion of oxide film  21  where a contact will be produced. 
     As shown in FIG. 10 c  barrier layer  23  of SiON is deposited on the entire surface of oxide film  21  including groove  22 . 
     As shown in FIG. 1 d,  conductive layer  24  of tungsten is deposited on barrier layer  23 , thereby embedding tungsten in groove  22 . 
     Thereafter, the entire assembly is polished by CMP (Chemical Mechanical Polishing) to remove conductive layer  24  and barrier layer  23  except groove  22 , thus producing contact  11  in groove  22 , as shown in FIG. 10 e.    
     As shown in FIG. 10 f,  interlayer film  25  of SiON and oxide film  26  are successively formed on oxide film  21  with contact  11  formed therein. 
     Then, as shown in FIG. 10 g,  resist  27  is coated on the surface of oxide film  26  except for a region where an interconnection will be formed. 
     As shown in FIG. 10 h,  interlayer film  25  and oxide film  26  in the region where no resist  27  is coated are etched away, forming groove  28 . Thereafter, resist  27  is removed. 
     As shown in FIG. 10 i,  barrier layer  29  is deposited on the entire surface of oxide film  26  including groove  28 . 
     Then, as shown in FIG. 10 j,  conductive layer  30  of copper is deposited on barrier layer  29 , thereby embedding copper in groove  28 . 
     Thereafter, the entire assembly is polished by CMP to remove conductive layer  30  and barrier layer  29  except groove  28 , thus producing interconnection  13   a  in groove  28 , as shown in FIG. 10 k.    
     A first layer is thus formed by the above steps. 
     Then, as shown in FIG. 11 a,  an interlayer film  31  and an oxide film  32  are successively formed on the assembly thus formed by the steps shown in FIGS. 10 a  through  10   k.    
     As shown in FIG. 11 b,  resist  33  is coated on the surface of oxide film  32  except for a region where a via will be formed. 
     As shown in FIG. 11 c,  interlayer film  32  in the region where no resist  33  is coated is etched away, forming groove  34 . Thereafter, resist  33  is removed. 
     As shown in FIG. 11 d,  barrier layer  35  is deposited on the entire surface of oxide film  32  including groove  34 . 
     Then, as shown in FIG. 11 e,  conductive layer  36  of tungsten is deposited on barrier layer  35 , thereby embedding tungsten in groove  34 . 
     Thereafter, the entire assembly is polished by CMP to remove conductive layer  36  and barrier layer  35  except groove  34 , thus producing via  14   a  in groove  34 , as shown in FIG. 11 f.    
     As shown in FIG. 11 g,  interlayer film  37  and oxide film  38  are successively formed on oxide film  32  with via  14   a  formed therein. 
     Then, as shown in FIG. 11 h,  resist  39  is coated on the surface of oxide film  37  except for a region where an interconnection will be formed. 
     As shown in FIG. 11 i,  interlayer film  37  and oxide film  38  in the region where no resist  39  is coated are etched away, forming groove  40 . Thereafter, resist  39  is removed. 
     As shown in FIG. 11 j,  barrier layer  41  is deposited on the entire surface of oxide film  39  including groove  40 . 
     Then, as shown in FIG. 11 k,  conductive layer  42  of copper is deposited on barrier layer  41 , thereby embedding copper in groove  40 . 
     Thereafter, the entire assembly is polished by CMP to remove conductive layer  42  and barrier layer  41  except groove  40 , thus producing interconnection  13   b  in groove  40 , as shown in FIG. 11 l.    
     A second layer is thus formed by the above steps. 
     The steps shown in FIGS. 11 a  through  11   l  are carried out again to form a third layer. 
     Then, as shown in FIG. 12 a,  interlayer film  43 , oxide film  44 , interlayer film  45 , and oxide-film  46  are successively formed on the third layer which has been formed by the steps shown in FIGS. 11 a  through  11   l.    
     Then, as shown in FIG. 12 b,  resist  47  is coated on the surface of oxide film  46  except for a region where a via will be formed. 
     As shown in FIG. 12 c,  oxide films  44 ,  46  and interlayer film  45  in the region where no resist  47  is coated are etched away, forming groove  48 . Thereafter, resist  47  is removed. 
     Then, as shown in FIG. 12 d,  antireflection film  49  is deposited on the entire surface of oxide film  46  including groove  48 , thus embedding antireflection film  49  in groove  48 . 
     As shown in FIG. 12 e,  a resist  50  is coated on the surface of antireflection film  49  except for a region where an interconnection will be formed. 
     As shown in FIG. 12 f,  oxide film  46  and antireflection film  49  in the region where no resist  50  is coated are etched away. Thereafter, resist  50  is removed. 
     As shown in FIG. 12 g,  barrier layer  51  is deposited on the entire surface of assembly. 
     Then, as shown in FIG. 12 h,  conductive layer  52  of copper is deposited on barrier layer  51 , thereby embedding copper in groove  48 . 
     Thereafter, the entire assembly is polished by CMP to remove conductive layer  52  and barrier layer  51  except groove  48 , thus producing via  15   a  and interconnection  13   d  in groove  48 , as shown in FIG. 12 i.    
     A fourth layer is thus formed by the above steps. 
     The steps shown in FIGS. 12 a  through  12   i  are repeated form fourth and fifth layers. 
     In the above embodiment, the area of vias  15   a - 15   c  of copper shown is 12.9 times greater than the area of contact  11  and vias  14   a,    14   b  of tungsten. According to another embodiment, the areas of respective vias are equal to each other, and the number of vias of copper is 13 times greater than the number of vias of tungsten, as illustrated schematically in FIG.  13 . 
     While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.