Abstract:
A differential amplifier includes a differential input pair ( 2 A) coupled to a folded cascode stage ( 2 B) and a common mode feedback circuit ( 34 ) including a tracking circuit ( 30 A) coupled to first (Vout − ) and second (Vout + ) outputs of the folded cascode stage ( 2 B). The first and second outputs are coupled to first terminals of first ( 31 A) and second ( 31 B) tracking capacitors which have second terminals on which a first common mode output signal (V CM1 ) is produced and also are coupled to first terminals of third ( 32 A) and fourth ( 32 B) tracking capacitors, respectively, which have second terminals on which a second common mode output signal (V CM2 ) is produced. The first and third tracking capacitors are discharged by first ( 27 A) and second ( 27 B) switches that directly couple the first and second outputs to first and second inputs of a common mode feedback amplifier ( 4 ). A desired common mode output voltage (V CM-IN ) is applied to a third input of the common mode feedback amplifier. The switches are opened to cause the first and second common mode output voltages to be generated, causing a common mode feedback control signal (V CMFB ) to be generated for biasing the folded cascode stage.

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates generally to common mode feedback circuits for fully differential amplifiers, and more particularly to common mode feedback circuits which avoid introducing errors into the differential output signal. 
   All fully differential amplifiers (i.e., differential amplifiers having both differential inputs and a differential outputs) have a common mode feedback circuit. For example, differential amplifier  1 A of  FIG. 1 , which includes a typical differential input transistor pair  2 A and a typical folded cascode stage  2 B, also includes a common mode feedback circuit  3 . The inputs of common mode feedback circuit  3  are coupled to the outputs Vout +  and Vout −  of folded-cascode stage  2 B, and the output of common mode feedback circuit  3  is fed back via common mode feedback conductor  22  to P-channel current source transistors  15  and  16  of folded cascode stage  2 B. 
   The main requirements of a common mode feedback circuit are to (1) keep the outputs Vout +  and Vout −  of the amplifier within a suitable range, (2) to have as little effect as possible on the differential output voltage (Vout + −Vout − ), and (3) to keep the output common mode voltage (V CMO ) constant. It is important that the output common mode voltage V CMO  be kept constant since it affects the differential voltage Vout + −Vout −  because of the output characteristics of the differential amplifier itself. (A non-constant V CMO  affects the differential output voltage in two ways. First, it affects the linearity of the amplifier, and second, it “moves” and thereby limits the output voltage swing.) Also, V CMO  should be constant because if it is not constant and if the CMRR (common mode rejection ratio) of circuitry following the differential amplifier is low, this results in signal errors. Furthermore, the common mode feedback frequently has to operate with large output voltage swings of the differential amplifier. Also, the common mode feedback may need to operate with differential amplifiers having an auto-zero phase and an active amplification phase. 
   The common mode feedback circuit  3  shown in Prior Art  FIG. 1  keeps the outputs in an operational range, but provides very poor control of the output common mode voltage V CMO . Furthermore, common mode feedback circuit  3  of Prior Art  FIG. 1  operates effectively only for relatively small swings of the differential output voltage Vout + −Vout − . If the differential output voltage Vout + −Vout −  increases, common mode feedback circuit  3  keeps one of the output voltages Vout +  or Vout −  approximately constant, and therefore the output common mode voltage V CMO  (which is the average of Vout +  and Vout − ) varies over a wide range. The output voltage swings are small because if the differential output voltage is large, then one of transistors  23  and  24  is off and therefore has no effect on the common mode feedback control voltage on conductor  22 , and therefore only one of the output voltages Vout +  or Vout −  controls the common mode feedback control voltage. The common mode feedback control voltage on conductor  22  just follows the lower of Vout +  and Vout − , and therefore does not track to the actual output common mode voltage, i.e., does not track the average of Vout +  and Vout − . Also, variation of the output common mode voltage V CMO  of common mode feedback circuit  3  varies significantly with semiconductor processing variables and with circuit temperature. 
   Another prior art common mode feedback circuit  3 A is shown in the differential amplifier  1 B of  FIG. 2 . In this common mode feedback circuit, a tracking circuit  30  includes equal tracking capacitors  31  and  32  and a CMOS transmission gate switch  27  that is controlled by a “phase one” signal PH 1  which occurs before normal amplifying, referred to as “phase  2 ”. PH 1  can be an auto-zero signal in a typical case in which an auto-zeroing circuit is connected to output conductors  19  and  20  of folded cascode circuit  2 B. The auto-zeroing circuit cross-connects Vin +  to Vout −  and Vin −  to Vout +  during the auto-zeroing phase, during which time the differential input voltage is very small. Then the resulting differential output voltage is equal to the magnitude of the differential amplifier input offset voltage. Next, switch  27  is closed, which discharges tracking capacitor  32 , so the offset voltage appears across tracking capacitor  31 . This provides V CM1  as a DC bias point on the gate of a P-channel input transistor  35  of transistor pair  21 A which also includes P-channel input transistors  36 . Switch  27  when closed also prevents V CM1  from electrically “floating”, i.e., from changing as a result of leakage currents associated with conductor  33 . During the amplification phase of operation of differential amplifier  1 B, switch  27  is open, and V CM1  therefore is equal to the common mode output voltage of differential amplifier  1 B (i.e. to the average value of Vout +  and Vout − ). 
   The gate of input transistor  36  receives the voltage V CM-IN , which is the constant desired common mode output voltage of differential amplifier  1 B. V CM-IN  may be provided by a reference voltage circuit, for example a voltage divider. The drains of input transistors  35  and  36  are connected to the summing nodes  39  and  40 , respectively, of a folded cascode circuit  21 B of common mode feedback circuit  3 A. Common mode feedback circuit  3 A can zero itself during auto-zeroing (i.e., during PH 1 ) and can also track the output differential voltage Vout + −Vout −  during the amplifying phase by means of equal tracking capacitors  31  and  32 . 
   Common mode feedback circuit  3 A of Prior Art  FIG. 2  allows both large Vout +  and Vout −  voltage swings of differential amplifier stage  2  and precise control of the output common mode voltage. The main problem of common mode feedback circuit  3 A of Prior Art  FIG. 2  is that charge is injected on only one of the output voltages (i.e., only on Vout + ) by parasitic capacitance of CMOS transmission gate switch  27  when it opens at the end of PH 1 . The injected charge generates a spike voltage on Vout + . This introduces an error in the output differential voltage Vout + −Vout − . (It should be appreciated that providing an additional switch similar to switch  27  across tracking capacitor  31  to balance the above mentioned charge injection would short-circuit Vout +  and Vout −  together, which would be unacceptable because it does not allow input offset correction during this phase. 
   Thus, there is an unmet need for a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier. 
   There also is an unmet need for a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and has very little effect on the differential output voltage of the differential amplifier. 
   There also is an unmet need for a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and keeps the common mode output voltage constant. 
   There also is an unmet need for a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and keeps the common mode output voltage constant and also keeps the amplifier output voltages within a suitable range. 
   There also is an unmet need for a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and does not short circuit the differential amplifier outputs during auto-zeroing of the differential amplifier. 
   There also is an unmet need for a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and accurately tracks the common mode voltage during both an auto-zeroing phase and an amplification phase. 
   There also is an unmet need for a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and precisely controls the output common mode voltage. 
   SUMMARY OF THE INVENTION 
   Thus, there is an unmet need for a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier. 
   It is another object of the invention to provide a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and has very little effect on the differential output voltage of the differential amplifier. 
   It is another object of the invention to provide a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and keeps the common mode output voltage constant. 
   It is another object of the invention to provide a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and keeps the common mode output voltage constant and also keeps the amplifier output voltages within a suitable range. 
   It is another object of the invention to provide a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and does not short circuit the differential amplifier outputs during auto-zeroing of the differential amplifier. 
   It is another object of the invention to provide a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and accurately tracks the common mode voltage during both an auto-zeroing phase and an amplification phase. 
   It is another object of the invention to provide a common mode feedback circuit which operates effectively with any two-phase fully differential amplifier and precisely controls the output common mode voltage. 
   Briefly described, and in accordance with one embodiment, the present invention provides a differential amplifier which includes a differential input pair ( 2 A) coupled to a folded cascode stage ( 2 B) and a common mode feedback circuit ( 34 ) including a tracking circuit ( 30 A) coupled to first (Vout − ) and second (Vout + ) outputs of the folded cascode stage ( 2 B). The first and second outputs are coupled to first terminals of first ( 31 A) and second ( 31 B) tracking capacitors which have second terminals on which a first common mode output signal (V CM1 ) is produced and also are coupled to first terminals of third ( 32 A) and fourth ( 32 B) tracking capacitors, respectively. The third ( 32 A) and fourth ( 32 B) tracking capacitors have second terminals on which a second common mode output signal (V CM2 ) is produced. The first and third tracking capacitors are discharged by first ( 27 A) and second ( 27 B) switches that directly couple the first and second outputs to first and second inputs of a common mode feedback amplifier ( 4 ). A desired common mode output voltage (V CM-IN ) is applied to a third input of the common mode feedback amplifier. The switches are opened to cause the first and second common mode output voltages to be generated, causing a common mode feedback control signal (V CMFB ) to be generated for biasing the folded cascode stage. 
   In one embodiment, the invention provides a differential amplifier ( 10 ) including a differential input transistor pair ( 2 A) having first ( 5 ) and second ( 6 ) input transistors, a first folded cascode stage ( 2 B) including first ( 9 ) and second ( 8 ) summing junctions coupled to drains of the first ( 5 ) and second ( 6 ) input transistors, respectively, and first ( 20 ) and second ( 19 ) outputs conducting first (Vout − ) and second (Vout + ) output signals, respectively. First ( 12 ) and second ( 11 ) current source transistors have drains coupled by the first ( 9 ) and second ( 8 ) summing junctions, respectively, to sources of first ( 14 ) and second ( 13 ) cascode transistors. The first ( 14 ) and second ( 13 ) cascode transistors have drains coupled to the first ( 20  and second ( 19 ) outputs, respectively, and third ( 16 ) and fourth ( 15 ) current source transistors have drains coupled to the first ( 20 ) and second ( 19 ) outputs, respectively. A common mode feedback circuit ( 34 ) includes a tracking circuit ( 30 A) coupled to the first ( 20 ) and second ( 19 ) outputs for producing first (V CM1 ) and second (V CM2 ) common mode output signals in response to the first (Vout − ) and second (Vout + ) output signals. An auxiliary amplifier stage ( 4 ) includes a differential input stage ( 26 A) including third ( 35 A), fourth ( 35 B) and fifth ( 36 ) input transistors. Gates of the third ( 35 A) and fourth ( 35 B) input transistors are coupled to receive the first (V CM1 ) and second (V CM2 ) common mode output signals, respectively. A gate of the fifth ( 36 ) input transistor is coupled to receive a desired common mode voltage (V CM-IN ). Drains of the third ( 35 A) and fourth ( 35 B) input transistors are coupled to a third summing junction ( 39 ) in a second folded cascode circuit ( 26 B) having an output ( 22 ). A drain of the fifth input transistor ( 36 ) is coupled to a fourth summing junction ( 40 ) in the second folded cascode circuit ( 26 B). The output ( 22 ) of the second folded cascode circuit ( 26 B) couples a common mode feedback control signal (V CMFB ) to bias gates of the third ( 16 ) and fourth ( 15 ) current source transistors. 
   In the described embodiment, the tracking circuit ( 30 A) includes a first section ( 30 A- 1 ) coupled to receive both the first (Vout − ) and second (Vout + ) output signals for producing the first common mode output signal (V CM1 ) and a second section ( 30 A- 2 ) coupled to receive both the first (Vout − ) and second (Vout + ) output signals for producing the second common mode output signal (V CM2 ). The first section ( 30 A- 1 ) includes first ( 31 A) and second ( 31 B) tracking capacitors having first terminals connected to produce the first common mode output signal (V CM1 ) and a first switch ( 27 A) coupled across the first tracking capacitor ( 31 A). A second terminal of the first tracking capacitor ( 31 A) is coupled to receive the first output signal (Vout − ), and a second terminal of the second tracking capacitor ( 31 B) is coupled to receive the second output signal (Vout + ). The second section ( 30 A- 2 ) includes third ( 32 A) and fourth ( 32 B) tracking capacitors having first terminals connected to produce the second common mode output signal (V CM2 ) and a second switch ( 27 B) coupled across the third tracking capacitor ( 32 A). A second terminal of the third tracking capacitor ( 32 A) is coupled to receive the second output signal (Vout + ), and a second terminal of the fourth tracking capacitor ( 32 B) is coupled to receive the first output signal (Vout − ). In the described embodiment, the capacitances of the first ( 31 A), second ( 31 B), third ( 32 A) and fourth ( 32 B) tracking capacitors) are equal and the sizes of the first ( 27 A) and second ( 27 B) switches are equal, which results in symmetric charge injection into the first ( 20 ) and second ( 19 ) outputs of the first folded-cascode stage ( 2 B) so as to eliminate errors due to asymmetric charge injection. 
   In a described embodiment, the first ( 5 ) and second ( 6 ) input transistors are P-channel transistors and the first ( 12 ) and second ( 11 ) current source transistors and the first ( 14 ) and second ( 13 ) cascode transistors are N-channel transistors. The third ( 16 ) and fourth ( 15 ) current source transistors are P-channel transistors. The first folded-cascode stage ( 2 B) includes a P-channel third cascode transistor ( 18 ) coupled between a drain of the third current source transistor ( 16 ) and the first output ( 20 ) and a P-channel fourth cascode transistor ( 17 ) coupled between the drain of the fourth current source transistor ( 15 ) and the second output ( 19 ). The third ( 35 A), fourth ( 35 B), and fifth ( 36 ) input transistors are P-channel transistors. The second folded cascode circuit ( 26 B) includes a N-channel fifth cascode transistor ( 43 ) having a source coupled to the third summing junction ( 39 ) and a drain coupled to a drain and gate of a P-channel seventh current source transistor ( 49 ) and a N-channel sixth cascode transistor ( 44 ) having a source coupled to the fourth summing junction ( 40 ) and a drain coupled to a drain and gate of a P-channel eighth current source transistor ( 50 ) and to the output ( 22 ) conducting the common mode feedback control signal (V CMFB ). In operation, the first ( 27 A) and second ( 27 B) switches are closed in response a phase signal (PH 1 ) during an initial phase and then are opened during an amplifying phase of the differential amplifier ( 10 ). 
   In a described embodiment, an auto-zeroing circuit ( 56 ) is coupled to the first ( 20 ) and second ( 19 ) outputs of the first folded cascode stage ( 2 B). 
   In one embodiment, the invention provides a method of reducing error in a differential amplifier ( 10 ) including a differential input transistor pair ( 2 A) coupled to a folded cascode stage ( 2 B), and a common mode feedback circuit ( 34 ) including a tracking circuit ( 30 A) coupled to first (Vout − ) and second (Vout + ) outputs of the folded cascode stage ( 2 B). The method includes coupling the first (Vout − ) and second (Vout + ) outputs to first terminals of first ( 31 A) and second ( 31 B) tracking capacitors, respectively, in a first section ( 30 A- 1 ) of the tracking circuit ( 30 A), the first ( 31 A) and second ( 31 B) tracking capacitors having second terminals on which a first common mode output signal (V CM1 ) is produced, coupling the second (Vout + ) and first (Vout − ) outputs of the folded-cascode stage ( 2 B) to first terminals of third ( 32 A) and fourth ( 32 B) tracking capacitors, respectively, in a second section ( 30 A- 2 ) of the tracking circuit ( 30 A), the third ( 32 A) and fourth ( 32 B) tracking capacitors having second terminals on which a second common mode output signal (V CM2 ) is produced, discharging the first tracking capacitor ( 31 A) and producing a direct coupling of the first output (Vout − ) to a first input of an auxiliary common mode feedback amplifier ( 4 ), discharging the third tracking capacitor ( 32 A) and producing a direct coupling of the second output (Vout + ) to a second input of the auxiliary common mode feedback amplifier ( 4 ), applying a desired common mode output voltage (V CM-IN ) to a third input of the auxiliary common mode feedback amplifier ( 4 ), terminating the direct couplings to cause the first (V CM1 ) and second (V CM2 ) common mode output voltages to be produced, generating a common mode feedback control signal (V CMFB ) by means of the auxiliary common mode feedback amplifier ( 4 ), and applying the common mode feedback control signal (V CMFB ) to bias the folded cascode stage ( 2 B). In a described embodiment, the method includes closing a first switch ( 27 A) coupled across the first tracking capacitor ( 31 A) to discharge the first tracking capacitor ( 31 A) and produce the direct coupling of the first output (Vout − ) and closing a second switch ( 27 B) coupled across the third tracking capacitor ( 32 A) to discharge the third tracking capacitor ( 32 A) and produce the direct coupling of the second output (Vout + ), and opening the first ( 27 A) and second ( 27 B) switches to terminate the direct couplings. 
   In one embodiment, the invention provides differential amplifier ( 10 ) including a differential input transistor pair ( 2 A) coupled to a folded cascode stage ( 2 B) and a common mode feedback circuit ( 34 ) including a tracking circuit ( 30 A) coupled to first (Vout − ) and second (Vout + ) outputs of the folded cascode stage ( 2 B), means ( 20 , 19 ) for coupling the first (Vout − ) and second (Vout + ) outputs to first terminals of first ( 31 A) and second ( 31 B) tracking capacitors, respectively, in a first section ( 30 A- 1 ) of the tracking circuit ( 30 A), the first ( 31 A) and second ( 31 B) tracking capacitors having second terminals on which a first common mode output signal (V CM1 ) is produced, and means ( 20 , 19 ) for coupling the second (Vout + ) and first (Vout − ) outputs of the folded-cascode stage ( 2 B) to first terminals of third ( 32 A) and fourth ( 32 B) tracking capacitors, respectively, in a second section ( 30 A- 2 ) of the tracking circuit ( 30 A), the third ( 32 A) and fourth ( 32 B) tracking capacitors having second terminals on which a second common mode output signal (V CM2 ) is produced, means ( 27 A) for discharging the first tracking capacitor ( 31 A) and producing a direct coupling of the first output (Vout − ) to a first input of an auxiliary common mode feedback amplifier ( 4 ), and means ( 27 B) for discharging the third tracking capacitor ( 32 A) and producing a direct coupling of the second output (Vout + ) to a second input of the auxiliary common mode feedback amplifier ( 4 ), and applying a desired common mode output voltage (V CM-IN ) to a third input of the auxiliary common mode feedback amplifier ( 4 ), means ( 27 A,B) for terminating the direct couplings to cause the first (V CM1 ) and second (V CM2 ) common mode output voltages to be produced, and means ( 4 , 22 ) for generating a common mode feedback control signal (V CMFB ) by means of the auxiliary common mode feedback amplifier ( 4 ) and applying the common mode feedback control signal (V CMFB ) to bias the folded cascode stage ( 2 B). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is schematic diagram of a differential amplifier having a prior art common mode feedback circuit. 
       FIG. 2  is a schematic diagram of a differential amplifier having another prior art common mode feedback circuit. 
       FIG. 3  is a schematic diagram of a differential amplifier having a common mode feedback circuit in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention provides a common mode feedback circuit with fully differential behavior for fully differential amplifiers. This common mode feedback circuit avoids short-circuiting of the amplifier outputs during auto-zeroing of the amplifier, tracks the desired common mode voltage V CM-IN  during both phases, and precisely controls the output common mode voltage. A simplified schematic diagram of a fully differential amplifier  10  including a common mode feedback circuit  34  in accordance with the present invention is shown in  FIG. 3 . 
   Referring to  FIG. 3 , differential amplifier  10  includes an input stage  2  having a differential input transistor pair  2 A and a folded cascode stage  2 B. Differential input transistor pair  2 A includes P-channel input transistors  5  and  6 , the gates of which receive input signals Vin +  and Vin − , respectively. The sources of input transistors  5  and  6  are connected to a tail current source  7 . The drains of input transistors  5  and  6  are connected to summing junctions  9  and  8 , respectively, of folded cascode stage  2 B. Summing junction  9  is connected to the drain of N-channel current source transistor  12  and the source of N-channel cascode transistor  14  of folded cascode stage  2 B, and summing junction  8  is connected to the drain of N-channel current source transistor  11  and the source of N-channel cascode transistor  13 . The sources of transistors  11  and  12  are connected to ground or V SS . The gates of cascode transistors  13  and  14  are connected to a suitable bias voltage V B1 , and the gates of current source transistors  11  and  12  are connected to a suitable bias voltage V B2 . The collectors of cascode transistor  13  and P-channel cascode transistor  17  are connected to an output conductor  19  on which an output voltage Vout +  is produced, and similarly, the collector of cascode transistor  14  is connected to the collector of a P-channel cascode transistor  18  by means of a conductor  20  on which the output voltage Vout −  is produced. The gates of cascode transistors  17  and  18  are connected to a suitable bias voltage V B3 . The sources of cascode transistors  17  and  18  are connected to the drains of P-channel current source transistors  15  and  16 , respectively, the sources of which are connected to V DD . The gates of current source transistors  15  and  16  are connected by common mode feedback conductor  22  to the output of folded cascode stage  26 B of common mode output circuit  34 . A conventional auto-zero circuit  56  may be coupled to Vout +  and Vout − . 
   Common mode output circuit  34  includes a tracking circuit  30 A and also an auxiliary amplifier  4  which includes a differential input stage  26 A and folded cascode stage  26 B. Tracking circuit  30 A includes a first CMOS transmission gate switch  27 A and a tracking capacitor  31 A connected in parallel between conductors  20  and  54 A, and also includes another tracking capacitor  31 B connected between output conductor  19  and conductor  54 A. Tracking capacitors  31 A and  31 B can be thought of as a “split” version of tracking capacitor  31  in Prior Art  FIG. 2 , and the circuitry including switch  27 A and “split” tracking capacitors  31 A and  31 B can be thought of as a first section  30 A- 1  of tracking circuit  30 A. Similarly, a second CMOS transmission gate switch  27 B is coupled in parallel with a tracking capacitor  32 A between conductor  19  and conductor  54 B, and another tracking capacitor  32 B is connected between conductor  20  and conductor  54 B. Tracking capacitors  32 A and  32 B can be thought of as a “split” version of tracking capacitor  32  in Prior Art  FIG. 2 , and the circuitry including switch  27 B and “split” tracking capacitors  32 A and  32 B can be thought of as a second section  30 A- 2  of tracking circuit  30 A. 
   During the above-mentioned “phase one”, the signal PH 1  causes switches  27 A and  27 B to be turned on prior to the amplification phase of differential amplifier  10  in order to discharge tracking capacitors  31 A and  32 A and provide directly coupled DC paths from Vout +  and Vout −  to the gates of input transistors  35 A and  35 B, respectively, in order to provide DC bias points for the gates of transistors  35 A and  35 B. During the amplification phase when switches  27 A and  27 B are open, the actual common mode output voltages V CM1  and V CM2  are produced on conductors  54 A and  55 B. 
   Input stage  26 A of common mode output circuit  34  includes P-channel input transistors  35 A,  35 B and  36 , the sources of which are connected to tail current source  37 . The gate of input transistor  35 A receives V CM1  on conductor  54 A, and the gate of input transistor  35 B receives V CM2  on conductor  54 B. The drains of input transistors  35 A and  35 B are connected to summing junction  39  of folded cascode stage  26 B. The gate of input transistor  36  is connected to conductor  38 , on which the desired common mode input voltage V CM-IN  for differential amplifier  10  is produced. The drain of input transistor  36  is coupled to summing junction  40  of folded cascode stage  26 B. 
   Folded cascode circuit  26 B includes N-channel current source transistors  41  and  42  having their sources connected to ground (or V SS ) and their gates connected to bias voltage V B2 . The drain of transistor  41  is connected by summing junction  39  to the source of N-channel cascode transistor  43 , and the drain of transistor  42  is connected by summing junction  40  to the source of N-channel cascode transistor  44 . The gates of transistors  43  and  44  are coupled to bias voltage V B1 . The drains of cascode transistors  43  and  44  are connected to the drains of P-channel cascode transistors  47  and  48 , respectively, the gates of which are coupled to bias voltage V B3 . The sources of cascode transistors  47  and  48  are connected to the drains of P-channel current source transistors  49  and  50 , respectively, the sources of which are connected to V DD . The gate of transistor  49  is connected by conductor  45  to the drains of cascode transistors  47  and  43 , and the gate of transistor  50  is connected by common mode feedback conductor  22  to the drains of cascode transistors  44  and  48 . It should be appreciated that if desired, cascode transistors  47  and  48  can be omitted and the drains of transistors  49  and  50  can be connected directly to the drains of transistors  43  and  44 , respectively. Alternatively, transistors  49  and  50  can be connected in a conventional current mirror configuration, with their gates both connected to conductor  45 . Also, cascode transistors  17  and  18  in folded cascode stage  2 B also can be omitted in the same way if desired. It also should be appreciated that stage  26 B of a auxiliary amplifier  4  can be implemented by almost any kind of secondary amplifying circuit to produce the common mode feedback control signal on conductor  22 . 
   Common mode feedback circuit  34  in  FIG. 3  differs from other common mode feedback circuits, such as the one shown in Prior Art  FIG. 2 , by providing complete symmetry with respect to both outputs Vout +  and Vout − , and avoids the problem of short-circuiting Vout +  to Vout −  during the initial or auto-zeroing phase. This symmetry minimizes errors introduced into the differential output voltage Vout + −Vout −  introduced by the above-mentioned asymmetrical charge injection into the conductors of output voltages Vout +  and Vout − . Furthermore, common mode feedback circuit  34  in  FIG. 3  does not adversely affect the differential output voltage in any other ways, and precisely controls the output common mode voltage. Common mode feedback circuit  34  also allows large output voltage swings of the main amplifier input stage  2  without adversely affecting the output common mode voltage. 
   It should be appreciated that input transistor  35  in the differential input transistor pair  21 A of Prior Art  FIG. 2  can be thought of as being “split” in half to provide the two input transistors  35 A and  35 B in differential input stage  26 A of  FIG. 3 . This is also necessary to prevent short-circuiting of Vout +  to Vout −  while switches  27 A and  27 B are closed. It should also be appreciated that since the sizes of “split” tracking capacitors  31 A,  31 B,  32 A and  32 B are only half the sizes of tracking capacitors  31  and  32  in Prior Art  FIG. 2 , and since input transistors  35 A and  35 B in  FIG. 3  are half the size of input transistor  35  in Prior Art  FIG. 2 , the only additional integrated circuit chip area required for the present invention is the area required for the extra CMOS switch. 
   To understand the operation of capacitors  31 B and  32 B, which are cross-connected between conductors  54 A and  54 B and the “opposite” Vout +  or Vout −  conductors  19  and  20 , it is helpful to note that if, in Prior Art  FIG. 2 , an additional switch identical to  27  is connected across tracking capacitor  31 , it will short-circuit Vout +  to Vout − . What is needed is for the values of Vout +  and Vout −  to be separated by the amplifier input offset voltage during the zero-ing phase, i.e., during PH 1 . That is why in  FIG. 3  each of the tracking capacitors of  FIG. 2  has been split into a pair of tracking capacitors, and also is why input transistor  35  of  FIG. 2  is split into a pair of input transistors. During PH 1 , Vout −  is short-circuited by switch  27 A to the gate of transistor  35 A and Vout +  is short-circuited by switch  27 B to the gate of transistor  35 B. The result is that at the end of PH 1 , the same amount of parasitic charge is injected into both conductors  54 A and  54 B when switches  27 A and  27 B are opened. Also, short-circuiting Vout +  to Vout −  is avoided, and the input offset voltage can be stored across capacitors  31 A and  31 B. 
   The basic structure shown in  FIG. 3  is workable using either P-channel or N-channel transistors in the differential input pair  2 A and using either P-channel or N-channel transistors in input stage  26 A of auxiliary amplifier  4 . Furthermore, control of the current through folded cascode stage  2 B can be achieved by using a common mode feedback control signal coupled to the gates of either N-channel current source transistors  11  and  12  or P-channel current source transistors  15  and  16 . Also, it would be practical in some cases to provide both P-channel and N-channel differential input transistor pairs so as to provide a rail-to-rail differential input stage. 
   It should be appreciated that common mode feedback circuit  34  is useful in a differential amplifier either with or without auto-zeroing, as long as there is a “phase” during which Vout +  and Vout −  are at nearly the same in mid-range voltage when switches  27 A and  27 B are closed to provide DC paths to the gates of transistors  35 A and  35 B. 
   While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. For example, the main amplifier  2  could be implemented using bipolar NPN and/or PNP transistors in place of any of the various N-channel and/or P-N-channel transistors. Also, bipolar transistors could be used to implement whatever kind of secondary amplifying circuitry is selected to perform the function of folded cascode stage  26 B.