Abstract:
An apparatus which provides a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical re-wiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices. The computational logic self-reconfiguration process in the circuit takes place as training input signals, which are input causing the impedance state of the memristor device to change. Once the training process is completed, the circuit is probed to determine whether the desired logic operation has been programmed.

Description:
PRIORITY CLAIM UNDER 35 U.S.C. §119(e) 
       [0001]    This patent application claims the priority benefit of the filing date of a provisional application Ser. No. 61/463,952, filed in the United States Patent and Trademark Office on Feb. 25, 2011. 
     
    
     STATEMENT OF GOVERNMENT INTEREST 
       [0002]    The invention described herein may be manufactured and used by or for the Government for governmental purposes without the payment of any royalty thereon. 
     
    
     BACKGROUND OF THE INVENTION 
       [0003]    This invention relates generally to the field of electronic circuit design. More specifically, this invention relates to electronic circuits which have a reprogrammable function. More specifically still, the present invention relates to reprogrammable electronic circuits which can function as reconfigurable computing circuits. 
         [0004]    The basic electronic theory and operation of passive electronic circuit elements (inductor, resistor, and capacitor) are well understood in theory and practice [1]. Also, the memristor device electronic operation, model, and theory have been described in detail elsewhere [2][3]. From a functional point of view an electronic circuit composed of an inductor, capacitor, resistor, and memristor (LCRM) can be categorized as resonant circuit whose oscillating frequency can be determined theoretically in both time and frequency domains [1]. Given that the memristor device is essentially an electronic variable solid state resistor; the specific oscillating frequency of the resonant LCRM circuit can be made dependent on the impedance state variable M of the memristor device. [2][3] 
         [0005]    What is lacking in the prior art, however, is an LCRM circuit into which an electronic signal can be input so as to change the oscillating frequency and magnitude of oscillation of the circuit based on the time-domain dynamic of the memristor device. 
       OBJECTS AND SUMMARY OF THE INVENTION 
       [0006]    It is an object of the present invention to provide an apparatus that performs computing functions that are reprogrammable. 
         [0007]    It is another object of the present invention, then, to provide an apparatus that performs computing functions that does not require power consumption to retain a programmed logic state or computing configuration. 
         [0008]    It is yet another object of the present invention to provide an apparatus that serves as a fundamental building block for computing machine design that can be logically reconfigured repeatedly through the application of input signals while not requiring power consumption to retain any configured logical state. 
         [0009]    Briefly stated, the present invention provides an apparatus which provides a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical re-wiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices. The computational logic self-reconfiguration process in the circuit takes place as training input signals, which are input causing the impedance state of the memristor device to change. Once the training process is completed, the circuit is probed to determine whether the desired logic operation has been programmed. 
         [0010]    The above, and other objects, features and advantages of the present invention will become apparent from the following description read in conjunction with the accompanying drawings, in which like reference numerals designate the same elements. 
       REFERENCES 
       [0000]    
       
         A. Robbins and W. C. Miller, “Circuit Analysis: Theory &amp; Practice,” 2 nd  Ed,  Delmar Cengage Learning , New York, 2003. 
         R. Pino, J. Bohl, N. McDonald, B. Wysocki, P. Rozwood, K. Campbell, A. Oblea, and A. Timilsina, “Memristor Devices Compact Model Development for Neuromorphic Computing Applications”,  IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH  2010, Anaheim, Calif., Jun. 17-18, 2010. 
         L. Chua, “Memristor—The Missing Circuit Element,” IEEE Transactions on Circuits Theory (IEEE), vol. 18, no. 5, 1971, pp. 507-519. 
       
     
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1   a  depicts the electronic circuit schematic and configuration of the basic analog logic gate of the present invention. 
           [0015]      FIG. 1   b  depicts the simplified logic block diagram of the basic analog logic gate of the present invention. 
           [0016]      FIG. 2  depicts the circuit and memristor device models parameter values used to validate the performance of the reconfigurable logic gate operations. 
           [0017]      FIG. 3  depicts the time domain output response when the basic analog logic gate of the present invention is programmed to function as a Boolean AND logic gate. 
           [0018]      FIG. 4  depicts the time domain output response when the basic analog logic gate of the present invention is programmed to function as a Boolean OR logic gate. 
           [0019]      FIG. 5  depicts the time domain output response when the basic analog logic gate of the present invention is programmed to function as a Boolean XOR logic gate. 
           [0020]      FIG. 6  depicts the time domain output response when the basic analog logic gate of the present invention is programmed to function as a Boolean NOR logic gate. 
           [0021]      FIG. 7  depicts specific memristor device impedance state changes that allowed the logic gate to achieve self-reconfiguration. 
           [0022]      FIG. 8  depicts the basic analog logic gate of the present invention self-reconfiguration process from Boolean logic AND to NOR. 
           [0023]      FIG. 9  depicts the basic analog logic gate of the present invention self-reconfiguration process from Boolean logic NOR to XOR. 
           [0024]      FIG. 10  depicts the basic analog logic gate of the present invention self-reconfiguration process from Boolean logic XOR to OR. 
           [0025]      FIG. 11  depicts the basic analog logic gate of the present invention self-reconfiguration process from Boolean logic OR to AND. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0026]    The present invention provides an apparatus and method for implementing a two port inductor, capacitor, resistor, memristor (LCRM) network that can be trained or conditioned to exhibit logic computing operations. An electronic input to the LCRM circuit will have the ability to change the oscillating frequency and magnitude of oscillation of the circuit based on the time-domain dynamic of the memristor device. The logic operations displayed by the LCRM circuit of the present invention are characterized by the peak oscillating voltage output. In particular, when the LCRM peak oscillating voltage output exceeds in magnitude a predetermined range, the output is characterized as a logic one output. On the other hand, when the output is lower than the predetermined threshold value, the output of the apparatus is considered a logic zero output. 
       Analog Logic Gate 
       [0027]    Referring to  FIG. 1   a  and  FIG. 1   b , the present invention&#39;s basic components for a digital computing architecture are its logic building blocks.  FIG. 1   a  depicts the electronic circuit schematic and configuration of the basic analog logic gate to enable the present invention&#39;s analog self-reconfigurable computer functionality.  FIG. 1   b  depicts a simplified logic block diagram of the electronic circuit schematic depicted in  FIG. 1   a . Still referring to  FIG. 1   a  and  FIG. 1   b , respectively, the schematic placement of all LCRM electronic components and the corresponding block diagram of the reconfigurable logic gate are apparent. The inputs to the logic gate are labeled Vin 1  and Vin 2 , and the bias form of the inputs can be a discrete time variant input voltage pulses. The mathematical relationships governing the time domain dynamic behavior of the present invention&#39;s LRCM circuit schematic shown in  FIG. 1   a  are given by Kirchhoff&#39;s current law and described in detail in equations (1) to (6) below. 
         [0000]    
       
         
           
             
               
                 
                   0 
                   = 
                   
                     
                       
                         
                           V 
                           3 
                         
                         - 
                         
                           V 
                           
                             i 
                              
                             
                                 
                             
                              
                             n 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                       
                       
                         R 
                         1 
                       
                     
                     + 
                     
                       
                         1 
                         
                           L 
                           1 
                         
                       
                        
                       
                         ( 
                         
                           
                             ∫ 
                             
                               
                                 V 
                                 3 
                               
                                
                               
                                  
                                 t 
                               
                             
                           
                           - 
                           
                             ∫ 
                             
                               
                                 V 
                                 1 
                               
                                
                               
                                  
                                 t 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   0 
                   = 
                   
                     
                       
                         1 
                         
                           L 
                           1 
                         
                       
                        
                       
                         ( 
                         
                           
                             ∫ 
                             
                               
                                 V 
                                 1 
                               
                                
                               
                                  
                                 t 
                               
                             
                           
                           - 
                           
                             ∫ 
                             
                               
                                 V 
                                 3 
                               
                                
                               
                                  
                                 t 
                               
                             
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         
                           V 
                           1 
                         
                         - 
                         
                           V 
                           out 
                         
                       
                       
                         R 
                         3 
                       
                     
                     + 
                     
                       
                         C 
                         1 
                       
                        
                       
                         ( 
                         
                           
                             
                                
                               
                                 V 
                                 1 
                               
                             
                             
                                
                               t 
                             
                           
                           - 
                           
                             
                                
                               
                                 V 
                                 5 
                               
                             
                             
                                
                               t 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   0 
                   = 
                   
                     
                       
                         V 
                         5 
                       
                       
                         M 
                         1 
                       
                     
                     + 
                     
                       
                         C 
                         1 
                       
                        
                       
                         ( 
                         
                           
                             
                                
                               
                                 V 
                                 5 
                               
                             
                             
                                
                               t 
                             
                           
                           - 
                           
                             
                                
                               
                                 V 
                                 1 
                               
                             
                             
                                
                               t 
                             
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         C 
                         3 
                       
                        
                       
                         
                            
                           
                             V 
                             5 
                           
                         
                         
                            
                           t 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
             
               
                 
                   0 
                   = 
                   
                     
                       
                         
                           V 
                           out 
                         
                         - 
                         
                           V 
                           1 
                         
                       
                       
                         R 
                         3 
                       
                     
                     + 
                     
                       
                         
                           V 
                           out 
                         
                         - 
                         
                           V 
                           2 
                         
                       
                       
                         R 
                         4 
                       
                     
                     + 
                     
                       
                         V 
                         out 
                       
                       
                         M 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
             
               
                 
                   0 
                   = 
                   
                     
                       
                         
                           V 
                           2 
                         
                         - 
                         
                           V 
                           out 
                         
                       
                       
                         R 
                         4 
                       
                     
                     + 
                     
                       
                         1 
                         
                           L 
                           2 
                         
                       
                        
                       
                         ∫ 
                         
                           
                             V 
                             2 
                           
                            
                           
                              
                             t 
                           
                         
                       
                     
                     + 
                     
                       
                         C 
                         2 
                       
                        
                       
                         ( 
                         
                           
                             
                                
                               
                                 V 
                                 2 
                               
                             
                             
                               
                                  
                                 t 
                               
                                
                               
                                   
                               
                             
                           
                           - 
                           
                             
                                
                               
                                 V 
                                 4 
                               
                             
                             
                                
                               t 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   0 
                   = 
                   
                     
                       
                         
                           V 
                           4 
                         
                         - 
                         
                           V 
                           
                             i 
                              
                             
                                 
                             
                              
                             n 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                       
                         R 
                         2 
                       
                     
                     + 
                     
                       
                         C 
                         2 
                       
                        
                       
                         ( 
                         
                           
                             
                                
                               
                                 V 
                                 4 
                               
                             
                             
                                
                               t 
                             
                           
                           - 
                           
                             
                                
                               
                                 V 
                                 2 
                               
                             
                             
                                
                               t 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0028]    The circuit and memristor device models parameter values used to validate the performance of the reconfigurable logic gate operations are shown in  FIG. 2 . The memristor device model operation and formalism is described elsewhere in the published literature [2]. 
         [0029]    Still referring to  FIG. 1   a  and  FIG. 1   b , the circuit shown can be reconfigured to function as either an XOR gate, OR gate, AND gate, NOR gate, or the output can be turned off so it always outputs a zero. The circuit contains two memristor devices that can be switched to either a high or low resistance state to make the circuit perform the desired logic operation as shown. During normal operation, the input voltage to the gate representing the logic 1 bit is a 2 Volt amplitude positive half wave sinusoidal pulse at 1 KHz frequency. The output of the resonant logic gate is deemed high if it goes above the specified threshold voltage of 0.55 volts. During programming, pulses of a higher amplitude voltage of either positive or negative polarity are applied to the input nodes of the circuit, Vin 1  and/or Vin 2 , to switch the memristors to the desired state. 
         [0030]    Referring to  FIG. 3  shows the time domain output response when the logic gate in  FIG. 1   a  and  FIG. 1   b  is programmed to function as a Boolean AND logic gate.  FIG. 3  shows the input pulses Vin 1  and Vin 2  and the output response Vout. Still, from  FIG. 3 , it is apparent that the output, Vout, of the logic gate is higher than the specified threshold value of 0.55 Volts only when both inputs at input at the same time between the 12 and 14 ms of operation. The memristor state values that allow the circuit to exhibit the Boolean AND logic functionality are M 1 =1,539Ω and M 2 =25,001Ω respectively. 
         [0031]    Referring to  FIG. 4  depicts the performance of the present invention when the logic circuit gate of  FIG. 1   a  and  FIG. 1   b  is programmed to behave as a Boolean OR logic gate, and, accordingly, the memristor values are programmed to M 1 =1,539Ω and M 2 =50,000Ω respectively. It is apparent in  FIG. 4  that for any input to the resonant logic gate, the output is always above the specified 0.55 Volt threshold voltage. 
         [0032]    Referring to  FIG. 5 , when the memristor values are set to M 1 =1,500Ω and M 2 =50,000Ω respectively, the Boolean XOR logic operation can be performed. The Boolean XOR logic function states that the output is 1 whenever the inputs are different which is the case in  FIG. 5  in which the output is below the threshold voltage only when both inputs, Vin 1  and Vin 2 , are high, 2 Volts, between the 12 and 14 ms operation time. 
         [0033]    Referring to  FIG. 6  shows the operations of the Boolean NOR logic function of the present invention when the memristor values are set to M 1 =1,500Ω and M 2 =25,001Ω respectively. 
         [0034]    In the foregoing figures it was demonstrated how the present invention can reconfigure the logic gate to operate as various Boolean logic gates by setting the memristor devices M 1  and M 2  to specific impedance values. Additionally, however, the present invention can provide logic gate self-reconfiguration capability from a particular Boolean functionality to another and vice versa. To reprogram or reconfigure the logic gate, positive or negative programming pulses are applied to the inputs of the logic gate in a certain sequence to switch the state of one and/or both memristor devices, M 1  and M 2 . The voltage of the programming pulses can range from −7.5 to 7.5 Volts approximately. These pulses are applied so that the voltage across the memristor to be switched exceeds the threshold voltage of the memristor and is of the correct polarity to make the memristor switch to the desired resistance state [2]. 
         [0035]    Referring to  FIGS. 8 ,  9 ,  10 , and  11  illustrates the logic gate self-reconfiguration process from Boolean logic AND to NOR (see  FIG. 8 ), from NOR to XOR (see  FIG. 9 ), from XOR to OR (see  FIG. 10 ), and from OR to AND (see  FIG. 11 ), respectively. The specific memristor device impedance state changes that allowed the logic gate to achieve self-reconfiguration are given in  FIG. 7 . 
         [0036]    Referring to  FIG. 8  illustrates that a single 7.5 Volt electrical pulse applied to node Vin 1  is required to change the Boolean logic function from a AND to a NOR logic gate, and  FIG. 7  illustrates that the memristor impedance values change, M 1  change from 1,539 to 14,411Ω while M 2  remained fixed at 25,001Ω. Similarly, the transitions to and from any other Boolean logic gate functionality can be described from the results in  FIG. 9 ,  FIG. 10 , and  FIG. 11  and the memristor initial/final impedance state values again given in  FIG. 7 . It is important to state that the experimental results described here represent only a small subset of the possible memristor impedance state combinations that would result in a particular Boolean logic gate functionality. 
         [0037]    Thus to summarize, the present invention provides an apparatus and method for the design and operation characteristics of an analog self-reconfigurable Boolean logic computing architecture. The present invention&#39;s computing architecture leverages in a unique and novel way the non-linear dynamic properties of memristor devices with passive electronic components (inductor, capacitor, and resistor) to deliver threshold-based Boolean logic computational capabilities. 
         [0038]    Having described preferred embodiments of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.