Abstract:
A process for fabricating an integrated Micro-Electro-Mechanical Systems (MEMS) filter includes bonding an insulating substrate having a first end and a second end to a base substrate, the second end of the insulating substrate cantilevered over and separated from the base substrate by a gap, forming a resonator element on the second end of the insulating substrate, forming an inductive element comprising a coil, wherein the coil is formed on the insulating substrate, and forming a capacitive element on the first side of the insulating substrate, the capacitive element comprised of two conductive plates, wherein one of the two conductive plates is formed on the insulating substrate.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This is a divisional application of U.S. patent application Ser. No. 12/268,309, filed on Nov. 10, 2008, and issued as U.S. Pat. No. 7,994,877, which is incorporated herein as though set forth in full. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention addresses the integration of passive components such as inductors and capacitors onto a quartz film, for example, which may be suspended over a substrate by wafer bonding techniques. The U.S. patent application entitled “Quartz-Based Nanoresonators and Method of Fabricating Same” (U.S. Ser. No. 10/426,931) covers the fabrication process and resonator design for integrating VHF-UHF quartz mechanical resonators with active circuitry using handle wafer technology, wafer bonding, and final resonator release. This disclosure extends that disclosure by describing a method and device design whereby RF passive components are integrated directly on the quartz film, thereby providing wide-band filters, such as hybrid quartz filters or LC filters with low loss and low parasitics, and a method of producing same. This technology gives a filter designer numerous options for optimizing ladder filters using various combinations of high Q resonators, low loss inductors, and small capacitors with minimal parasitics. 
     Many filter designs require various combinations of active resonators, inductors, and capacitors connected in so-called ladder networks. These ladder network designs provide a large flexibility in producing filters with matched impedances, wide bandwidth range, and high out-of-band rejection. Previously, for monolithic integration, the inductors and capacitors were usually added to existing silicon integrated circuits (ICs) using conventional lithography techniques. If quartz resonators were added for high Q applications, the quartz device was added as a hybrid and attached to the circuitry of the IC using wire bond attachments. This prior art technique produces stray capacitance which can affect the filter performance, especially at VHF and UHF frequencies and higher frequencies. In addition, the RF loss in the substrate reduces the circuit&#39;s Q and can thereby increase the insertion loss. By adding some of all of the passive components directly on the quartz film using the presently disclosed quartz Micro-Electro-Mechanical Systems (MEMS) process, the RF losses and stray capacitances can be minimized. This allows one to produce filters with higher Q, lower insertion loss, and wider bandwidth in very compact designs. Lowering the parasitic capacitances improves the filter performance and also simplifies the design and fabrication of the filters since these parasitic capacitances do not have to be compensated for comparison to an ideal design without parasitic capacitance thereby reducing the manufacturing cost and improving the performance of the filter. 
     There exist many applications for narrow-to-wide band filters having small form factors. These applications includes advanced radio and communication systems as well as radar systems, all of which need filters having low insertion loss and small size for multi-spectral systems. 
     Traditional compact filters are typically manufactured either as hybrids (when mechanical resonators are used) or as integrated circuit elements (for passive components) on a silicon or group III-V semiconductor wafer. Although many filters designs have been investigated using a combination of mechanical resonators and passive Ls (inductors) and Cs (capacitors), integrating these elements on an active substrate while maintaining high Q and low loss has not been easy. Integrating a mechanical resonator directly on a silicon substrate leads to mechanical energy loss while placing Ls and Cs on silicon wafers leads to RF losses in the substrate. In some previous work, the Si substrate has been removed to reduce these losses, but this increases the complexity of the process, reduces packaging density, hinders the ultimate miniaturization, and makes CMOS processing more expensive. See “A Robust High-Q Micromachined RF Inductor for RFIC application,” Ji-Wei Lin, et al.,  IEEE Transactions on Electron Devices , Vol. 52, No. 7, pp. 1489-1496, July, 2005. Thus, by placing all the elements on a thin quartz film suspended over the substrate, as is disclosed herein, one can isolate the mechanical modes using conventional energy trapping techniques used by the quartz industry while minimizing RF losses and parasitics for the passive components. This is especially important at higher frequencies where parasitics begin to play a dominant role in the performance characteristics. In addition, ultra-small LC ladder filters can be fabricated at much higher frequencies than previously thought possible for wide bandwidth and tunable applications. 
     SUMMARY OF THE INVENTION 
     In a first embodiment disclosed herein, an integrated Micro-Electro-Mechanical Systems (MEMS) filter includes an insulating substrate bonded to a base substrate such that at least a portion of the insulating substrate is separated from the base substrate by a gap, the insulating substrate having a first side and a second side, an inductive element having a coil, wherein the coil of the inductive element is on the insulating substrate, and a capacitive element having two conductive plates, wherein one of the two conductive plates is on the insulating substrate. 
     In one aspect the insulating substrate is quartz. 
     In another aspect the inductive element includes a conductive spiral having a center contact point on the insulating substrate, a further contact point exterior to the spiral on the insulating substrate, and a conductive bridge connecting the center contact point of the conductive spiral to the further contact point. 
     In yet another aspect the capacitive element includes a first conductive plate on the insulating substrate, a dielectric layer on the first conductive plate, and a second conductive plate on the dielectric layer. 
     In another aspect integrated MEMS filter further includes a piezoelectric resonator element that includes a first electrode plate on the first side of the insulating substrate, and a second electrode plate on the second side of the insulating substrate, positioned opposite to the first electrode plate such that the insulating substrate positioned between the first electrode plate and the second electrode plate is able to act as the resonator plate substrate for the resonator element. 
     In yet another aspect the insulating substrate is crystalline quartz. 
     In another embodiment disclosed herein, a process for fabricating an integrated Micro-Electro-Mechanical Systems (MEMS) filter includes integrating an inductive element and a capacitive element onto an insulating substrate; and bonding the insulating substrate to a base substrate such that at least a portion of the insulating substrate is separated from the base substrate by a gap. 
     In one aspect the step of integrating includes metallizing a first side of the insulating substrate, attaching a handle wafer to the first side of the insulating substrate, thinning and etching vias in the insulating substrate, metallizing the second side of the insulating substrate, and releasing the handle wafer from the insulating substrate. 
     In another aspect the step of attaching a handle wafer includes depositing a release layer on a first side of the insulating substrate, and deposing a handle wafer on the release layer, wherein the step of releasing the handle wafer includes etching away the release layer. 
     In another aspect the handle wafer has perforations for assisting in etching away the release layer. 
     In yet another aspect the bonding step includes low-temperature pressure bonding. 
     In another aspect the process further includes metallizing a resonator element on the insulating substrate. The step of metallizing a resonator element may include metallizing a first electrode on a first side of the insulating substrate, and metallizing a second electrode on a second side of the insulating substrate opposite the first side. 
     These and other features and advantages will become further apparent from the detailed description and accompanying figures that follow. In the figures and description, numerals indicate the various features, like numerals referring to like features throughout both the drawings and the description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1F  depict an example of the steps that can be used to provide the layers for a MEMS quartz filter in accordance with the present disclosure. 
         FIG. 2A  depicts an example of a MEMS quartz filter resonator.  FIG. 2A-PT  shows the top-side plan view of  FIG. 2A  in accordance with the present disclosure.  FIG. 2A-PU  shows the under-side plan view of  FIG. 2A  in accordance with the present disclosure. 
         FIGS. 3A-3E  depict an example of how to fabricate a MEMS quartz filter inductor in accordance with the present disclosure.  FIG. 3A-P  shows the plan view of  FIG. 3A .  FIG. 3E-P  shows the plan view of  FIG. 3E  in accordance with the present disclosure. 
         FIGS. 4A-4C  depicts an example of how to fabricate a MEMS quartz filter capacitor in accordance with the present disclosure.  FIGS. 4A-P  to  4 C-P show the plan views of  FIGS. 4A-4C  respectfully in accordance with the present disclosure. 
         FIG. 5  depicts an example circuit diagram in accordance with the prior art that can be implemented using a MEMS quartz filter in accordance with the present disclosure. 
         FIGS. 6A-6D  depict the structure of an example MEMS quartz filter to implement the circuit diagram of  FIG. 5  in accordance with the present disclosure. 
         FIG. 6E  depicts the structure of another example MEMS quartz filter to implement the circuit diagram of  FIG. 5  in accordance with the present disclosure. 
         FIGS. 7A and 7B  are flow diagrams of a process for fabricating an integrated Micro-Electro-Mechanical Systems (MEMS) filter in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth to clearly describe various specific embodiments disclosed herein. One skilled in the art, however, will understand that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well known features have not been described so as not to obscure the invention. 
     The descriptions below describe the use of quartz as a substrate, however other equivalent insulating materials can be used, such as diamond. 
       FIGS. 1A-1F  show an example of how, in general, to create a MEMS quartz filter.  FIG. 1A  shows a quartz substrate  100 , which may be crystalline quartz, with top-side metallization  102  for the various filter components and interconnects deposited.  FIG. 1B  shows the deposition of a release layer  104 , which may be made of a material such as silicon that can be etched away without damaging the quartz substrate  100  or the top-side metallization  102 , and a handle wafer  106  which may be made of quartz or silicon.  FIG. 1C  shows  FIG. 1B  flipped over with a thinned down quartz substrate  100   x . The quartz substrate  100   x  may be thinned for example by milling or grinding and polishing.  FIG. 1D  shows under-side metallization  112  deposited on the thinned-down quartz substrate  100   x .  FIG. 1E  shows  FIG. 1D  flipped over and the under-side metallization  112  bonded, for example with a low-temperature pressure bond, to a bond pad  120  on a base substrate  130 .  FIG. 1F  shows the wafer with the handle wafer removed by etching away the release layer  104 , which also removes handle wafer  106 . 
       FIG. 2A  shows an example resonator design for a MEMS quartz resonator. The resonator consists of a top-side electrode  200  opposite an under-side electrode  210  on the thinned-down quartz substrate  100   x . The resonator can be physically isolated from the other filter components by means of a relatively long top-side conductive conduit  212  from the top-side electrode  200  and an under-side conductive conduit  202  from the under-side electrode  210 .  FIG. 2A-PT  shows the top-side plan view of  FIG. 2A  and  FIG. 2A-PU  shows the under-side plan view of  2 A. As shown in  FIGS. 2A-PT  and  2 A-PU, the top-side conductive conduit  202  and the under-side conductive conduit  212  can be positioned so they are not aligned directly opposite each other. 
       FIGS. 3A-3E  (along with plan views  3 A-P and  3 E-P) show an example of the creation of a inductor for a MEMS quartz filter. FIGS.  3 A and  3 A-P (plan view of  3 A) show the deposition of a metal spiral  302  on the thinned-down quartz substrate  100   x . The spiral  302  is connected on the outside ring to a conductive conduit  300  connecting the inductor to the rest of the filter circuit (not shown in  FIG. 3A ). Another conductive conduit  301  is laid down near, but not yet connected to, the spiral  302 .  FIG. 3B  shows the deposition of a releasable material  304 , such as silicon or photoresist, over the spiral  302  and surrounding area.  FIG. 3C  shows a masked etching of the releasable material  304  to create the space  305  for a bridge between the non-connected conductive conduit  301  and the center  303  of the spiral  302 .  FIG. 3D  shows the deposition of metal to create the bridge  306  and a connection  310  from the bridge  306  to the center  303  of the spiral  302 . FIGS.  3 E and  3 E-P (plan view of  3 E) shows the completed inductor with the releasable material  304  removed. 
       FIGS. 4A-4C  (along with the corresponding plan views  4 A-P to  4 C-P) show an example of the creation of a capacitor for a MEMS quartz filter.  FIG. 4A  and plan view  4 A-P shows a first electrode plate  402  and a first circuit conduit  400  deposited on the thinned-down quartz wafer  100   x .  FIG. 4B  and plan view  4 B-P shows a layer of dielectric  404  deposited over the first electrode  402 .  FIG. 4C  and plan view  4 C-P shows a second electrode plate  406  deposited over the dielectric  404  and connected to a second circuit conduit  408 . 
       FIG. 5  depicts an example circuit diagram of a filter using capacitors, inductors, and resonators. Other designs utilizing those elements are possible and well known in the art, including designs not requiring a resonator such as LC filters. The signal is input at the input terminals  502 , 504  and the filtered signal is output at the output terminals  512 ,  514 . This design utilizes two capacitors  520 , 521  and one inductor  530  in parallel with the input terminals  502 ,  504 , and one resonator  540  in series between the inductor  530  and one of the capacitors  521 . If a resonator is not used, then the quartz substrate does not need to be made of piezoelectric quartz, but can be fabricated from fused quartz. 
       FIGS. 6A-6D  depict an example of the circuit design shown in  FIG. 5  implemented as a MEMS quartz filter.  FIG. 6A  shows a thinned-down quartz substrate  100   x  with four vias  600  to allow connection between the two sides of the thinned down quartz substrate  100   x . The vias  600  can be etched before or after the thinning down process. The number of vias  600  may vary depending on the circuit being implemented. 
       FIG. 6B  shows one side of the thinned down quartz substrate  100   x  (in this example, the top-side). The vias  600  may be connected to the input terminals  502 ,  504  and output terminals  512 ,  514  so that each input terminal  502 ,  504  and each output terminal  512 ,  514  is available on both surfaces of the thinned down quartz substrate  100   x . The capacitors  520 ,  521  and inductor  530 , which may be fabricated on the thinned-down quartz substrate  100   x  in accordance with the process described relative to FIGS.  4 A to  4 C-P and FIGS.  3 A to  3 E-P, respectively, are connected to input terminals  502 ,  504  and output terminals  512 ,  514  by conductive conduits  501 ,  503 ,  513 ,  515 ,  517 , and  519 , as shown in  FIGS. 6B and 6C  to implement the circuit of  FIG. 5 . 
     The top-side electrode  200  of the resonator is deposited on the thinned-down quartz substrate  100   x  in a location that allows it to resonate without interference from the rest of the circuit and connected by conductive circuit  610  to output terminal  512 . 
       FIG. 6C  shows the under-side elements of the filter (the figure is flipped around its horizontal axis from  FIG. 6B ). The input terminals  502 ,  504  and output terminals  512 ,  514  are connected to the base substrate (not shown in  FIG. 6C ). The under-side conductive conduit  620 , which connects input terminal  502  to the underside electrode  210  may be positioned relative to conductive circuit  610  to avoid unwanted capacitive or resonating effects. 
       FIG. 6D  shows a side-view of the MEMS quartz filter after bonding input terminals  502 ,  504  and output terminals  512 ,  514  to the base substrate  130  and subsequent release of the handle wafer  106  as described relative to  FIGS. 1E and 1F .  FIG. 6D  also shows how the quartz substrate  100   x  is separated from the base substrate  130  by a gap  650  to allow the resonator ( 200  with  210 ) to resonate freely. 
       FIG. 6D  shows only inductor  530  and capacitor  520  however it should be understood that capacitor  521  and other parts of the MEMS quartz filter are hidden from view in  FIG. 6D . As described above with respect to  FIG. 1A , top-side metallization  102  may include metallization for the various filter components, such as inductor  530  and capacitors  520 , as shown in  FIG. 6D , on the quartz substrate  100   x , which results in the inductor  530  and capacitors  520  and  521  being located on the same side as top-side electrode  200  on quartz substrate  100   x.    
     In another embodiment the various filter components, such as inductor  530  and capacitors  520  and  521  and the conductive circuits can be fabricated at the same time that the under-side metallization  112  is deposited in  FIG. 1D  on the thinned-down quartz substrate  100   x  and thereby be located on the same side as under-side electrode  210  on quartz substrate  100   x . This embodiment is illustrated in  FIG. 6E . 
     Therefore the inductors and capacitors may be located on either one side or located on both sides of the thinned-down quartz substrate  100   x . Also the may be near the top-side and under-side electrodes  200 ,  210  or spaced further away, and also may be located in  FIG. 6E  between input terminals  502  and  504 . 
       FIGS. 7A and 7B  are flow diagrams of a process for fabricating an integrated Micro-Electro-Mechanical Systems (MEMS) filter in accordance with the present invention. In one embodiment in step  700  an inductive element  530  and a capacitive element  520  are integrated onto an insulating substrate  100   x . In step  720  the insulating substrate  100   x  is bonded to a base substrate  130  such that at least a portion of the insulating substrate  100   x  is separated from the base substrate  130  by a gap  650 . Then in step  722  a resonator element  200 ,  210  may be metallized on the insulating substrate  100   x.    
     The integration step  700  may include step  702  of metallizing a first side of the insulating substrate  100   x , step  704  of attaching a handle wafer  106  to the first side of the insulating substrate  100   x , step  712  of thinning and etching vias  600  in the insulating substrate  100   x , step  714  of metallizing the second side of the insulating substrate  100   x , and step  716  of releasing the handle wafer  106  from the insulating substrate  100   x . The step  716  of releasing the handle wafer  106  may include the step  718  of etching away the release layer  104 . 
     Step  704  may include step  706  of depositing a release layer  104  on a first side of the insulating substrate  100   x , and step  708  of deposing a handle wafer  106  on the release layer  104 . 
     Step  722  may include step  724  of metallizing a first electrode  200  on a first side of the insulating substrate and step  726  of metallizing a second electrode  210  on a second side of the insulating substrate  100   x  opposite the first side. 
     Having now described the invention in accordance with the requirements of the patent statutes, those skilled in this art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as disclosed herein. 
     The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . .”