Abstract:
The present invention relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The invention also relates to the wafer that is produced by the new method.

Description:
FIELD OF INVENTION  
       [0001]    The present invention relates to fully depleted CMOS devices, in particular, wafers for the manufacture of embedded DRAM devices and co-integrated on the same piece of substrate, fully depleted SOI transistors with back biasing capability, wherein the wafers comprise intrinsic semiconductor layers. 
       BACKGROUND OF THE INVENTION 
       [0002]    Semiconductor-On-Insulator (SeOI) and, in particular, Silicon-On-Insulator (SOI) semiconductor devices are of increasing interest in present and future semiconductor manufacturing, for example, in the context of the Complementary Metal Oxide Semiconductor (CMOS) technology. 
         [0003]    Embedded DRAM devices become increasingly important for high-performance CMOS electronics, since compared to conventional SRAMs the package density can be significantly increased. Besides the high integration lower noise and power consumption as well as higher bandwidth can be achieved as compared to external SRAM/DRAM architectures. In addition, planar fully depleted SOI transistors represent a cost effective approach with respect to the scaling of transistor devices. Planar fully depleted SOI transistors advantageously allow for back biasing in order to adjust the threshold voltage to reduce leakage power and/or boost performances. With Back Bias VI can be changed dynamically. Relatively thin buried oxide (BOX) layers, for example, with a thickness in the range of 5 to 50 nm, are necessary to provide optimal back biasing benefit. 
         [0004]    It is known to manufacture embedded DRAMs based on wafers with a pre-doped n-layer formed in the handle substrates, directly underneath the BOX and rather thick to contain the entire DRAM capacitor trench, typically several microns. For example, a phosphorous n +  layer with a concentration of 10 19  cm −3  may serve as a capacitor bottom plate. The n +  layer is crucial in terms of scaling of the eDRAMs. However, there arises a problem when a logic part comprising back-biased planar fully or partially depleted SOL transistors shall be integrated together with embedded DRAMs, since the pre-doped n +  layer heavily hampers the manufacture of the back-biasing features. Back bias regions must be electrically insulated one from another in order for them to be biased at different voltages without high leakage current. To achieve that insulation, we will need reverse-biased junctions on the current path from one back bias region to another. We will typically have N and P layers on top of the handle substrate creating the need junctions, and cut then vertically by STI structures to insulate one region from the others. 
         [0005]    Such multilayer structure can potentially be manufactured starting with the thick N+ layer required for the eDRAM, but would require high implantation doses to be implanted through the SOI and BOX layers. This is not desirable because it might create defects and also dope the SOI layer, 
         [0006]    In view of this, it is a problem underlying the present invention to provide a method for the integrated manufacture of both embedded DRAMS and back-biased transistors. 
       SUMMARY OF THE INVENTION 
       [0007]    In order to address the above-mentioned problem, it is provided a method for the manufacture of a wafer, comprising the steps of providing (e.g., by forming) a doped layer on a semiconductor substrate; providing (e.g., by forming) a first semiconductor layer on the doped layer; providing (e.g., by forming) an oxide layer on the first semiconductor layer; and providing (e.g., by forming) a second semiconductor layer on the oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. 
         [0008]    The process results in a wafer comprising a semiconductor substrate; a doped layer upon the semiconductor substrate; a first semiconductor layer upon the semiconductor substrate; an oxide layer formed upon the first semiconductor layer; and a second semiconductor layer formed upon the buried oxide layer, thus providing a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. 
         [0009]    The thus provided wafer facilitates the manufacture of an embedded DRAM integrated together with a logic part comprising SOI transistors that are back-biased for control of the threshold voltage. Contrary to the art there is no need for any complicated processing of a conventional wafer for preparation for the formation of back-biasing regions required by the provision of the heavily doped embedded doped layer, Rather, the provision of the first (intrinsic) semiconductor layer allows for easy conversion into n or p doped back-biasing regions for the SOL transistors of the logic part enabling a first level of Vt tuning by changing the back bias region doping between N or P. 
         [0010]    According to particular examples, the substrate is made of or comprises (poly- or mono) silicon. Both the first and the second semiconductor layer may comprise or consist of silicon, The buried oxide. layer may comprise an SiO 2  compound. The doped layer may, for example, be n +  doped silicon, for example, silicon comprising phosphorus dopants. The concentration of such phosphorus dopants may be in the range of some 10 18  to 10 20  cm −3 , in particular, about 10 19  cm −3 . 
         [0011]    As far as the thicknesses of the individual layers of the provided wafer concerns the following choices are, for example, suitable: The thickness of the first semiconductor layer may be in the range of 10 to 300 nm, in particular, 50 to 150 nm. The thickness of the second semiconductor layer may be in the range of 5 to 100 nm, in particular, 5 to 20 nm, An extra thin second semiconductor layer (5 to 15 nm) may be provided, if a fully depleted SOI transistor shall be formed in a logic part of the wafer. A somewhat thicker second semiconductor layer (up to some 100 nm) may be provided, if a partially depleted SOI transistor shall be formed in a logic part of the wafer. The thickness of the buried oxide layer may be in the range of 5 to 200 nm, in particular, 5 to 25 nm and the thickness of the doped layer may be in the range of 1 to 10 μm. 
         [0012]    According to an embodiment the wafer may be manufactured on the basis of some wafer transfer process, for instance, a wafer transfer process comprising the Smart Cut© process. The doped layer and the first semiconductor layer may be grown on the semiconductor substrate and the second semiconductor layer may be grown on a donor substrate and the wafer may be obtained by bonding the first and the second semiconductor layers by the buried oxide layer and detaching the donor substrate. 
         [0013]    In some detail, the manufacture of the wafer according to an example comprises the steps of growing the epitaxial doped layer on the semiconductor substrate and growing the first semiconductor epitaxial layer on the doped layer. The above-mentioned step of forming the second semiconductor layer on the buried oxide layer may comprise growing the second semiconductor layer on a donor substrate to obtain a donor wafer; forming a first oxide layer on the second semiconductor layer grown on the donor substrate; and/or forming a second oxide layer on the epitaxial first semiconductor layer grown on the doped layer; and bonding the donor wafer to the epitaxial first semiconductor layer grown on the doped layer by the first and/or second intermediate buried layer, wherein the first and/or second oxide layer form the buried oxide layer, and removing the donor substrate. Thus, the oxide layer can be provided on either or both of the semiconductor layers to facilitate bonding of the layers together. Thereafter, a portion of the donor substrate can be removed by any one of a number of processes, including grinding, polishing, etching or detaching. Detaching may be achieved by heating the donor substrate after providing a weakened zone therein, or by the application of a mechanical force or by a laser lift-off technique. The generally known Smart Cut® process or a variation thereof is the preferred way of removing the remainder of the donor substrate to transfer the second semiconductor layer and, when present, an exposed oxide layer upon it to the first semiconductor layer or when present the exposed oxide layer upon that layer. In such a manner, the desired wafer can reliably be formed avoiding significant defects of the semiconductor layers. 
         [0014]    The method for the manufacture of a wafer may further comprise doping at least a region of the first semiconductor layer by n or p dopants. For example, some predoping of the first semiconductor layer during the growth of the same on the substrate can he performed. Predoping in a concentration of about 10 18  cm −3  might he performed. Further doping might be performed in later processing steps when an embedded DRAM together with a logic part comprising back-biased transistors is manufactured based on the provided wafer. 
         [0015]    The above-described examples of the inventive wafer can be used for the manufacture of a semiconductor device comprising an embedded DRAM device in a first region of the wafer and a back-biased transistor in a second region of the wafer. In particular, it is provided a method for the manufacture of a semiconductor device, comprising the steps of providing a wafer obtained by a method according to one of the herein -described examples; forming an embedded DRAM device in a first region (DRAM part) of the wafer comprising forming a capacitor trench extending from the second semiconductor layer at least partly into the doped layer; and forming a back-biased transistor in a second region (logic part) of the wafer that is separated from the first region by a shallow trench isolation and comprising forming a back-biasing region in the first semiconductor layer. The formation of the back-biasing region may particularly comprise doping of the first semiconductor layer of the wafer after it has been provided in accordance to one of the above-described examples. 
         [0016]    By this method an embedded DRAM device can readily be manufactured that comprises both a capacitor bottom plate for the DRAM in form of the relatively heavily doped layer below the first (intrinsic) semiconductor layer and a back-biasing region for an SOI transistor formed in the first (intrinsic) semiconductor layer. 
         [0017]    Furthermore, herein it is provided semiconductor device, comprising a wafer provided in accordance with one of the herein-described examples; and integrated on that wafer, .an embedded DRAM device comprising a capacitor trench extending from the second semiconductor layer at least partly into the doped layer and a control FET having a channel region in the second semiconductor layer; and a back-biased SOI transistor comprising a channel region in the second semiconductor layer and a doped back-biasing region in the first semiconductor layer and a contact for biasing the doped back-biasing region. 
         [0018]    According to an example, in the provided semiconductor device the first semiconductor layer is doped in an upper region adjacent to the buried oxide layer and undoped in a lower region adjacent to the doped layer. By doping an upper surface region of the first semiconductor layer only a sufficiently high resistivity in the lower region between two respective contacts that may be provided for back-biasing two different transistors in the logic part of the semiconductor device is guaranteed. 
         [0019]    The semiconductor device may comprise a number of back-biased SOI transistors separated from each other and from the embedded DRAM device by shallow trench isolations extending from the second semiconductor layer at least pa into the doped layer or into the semiconductor substrate. Both the control FET and the back-biased transistors may be provided as fully depleted or partially depleted transistor devices. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    Additional features and advantages of the present invention will be described with reference to the drawings. In the description, reference is made to the accompanying figures that are meant to illustrate preferred embodiments of the invention. It is understood that such embodiments do not represent the full scope of the invention. 
           [0021]      FIG. 1  illustrates an example for the method for manufacturing a wafer comprising an intrinsic semiconductor layer according to the present invention, 
           [0022]      FIG. 2  illustrates an embedded DRAM device integrated with back-biased SOI transistors of a logic part manufactured on the basis on the wafer illustrated in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0023]    A particular example for manufacturing a wafer in accordance with the present invention will now be described with reference to  FIG. 1 . In a donor substrate  1  a nucleation layer  2  is formed by the implantation of ions. The implantation of ions results in a weakened zone at the main concentration of the implanted ions. The implantation energy may be in a range of some 5 key to 20 keV and the implantation dose may be chosen to be in the range of 5×10 16  to 10 17  ions/cm  2 , for example. A silicon layer  3  is formed on the donor substrate  1 . Subsequently, an oxide layer  4  is formed atop of the silicon layer  3 . Another substrate  5 , for example, a silicon substrate  5  is provided. A doped layer  6 , for example, a silicon layer doped with phosphorus dopants of a concentration of 10 19  cm −3  , is formed on the silicon substrate  5 . A silicon layer  7  is formed on the doped layer  6 . For example, silicon layer  7  can be grown by epitaxy and some dopant can be added during the epitaxial growth. Then, another oxide layer  8  is formed atop the silicon layer  7 . 
         [0024]    The structure comprising the donor substrate  1  and the silicon substrate  5  are then bonded to each other at the free surfaces of the oxide layers  4  and  8  as it is indicated by the arrow in  FIG. 1 . Next, stresses, for example, thermal and/or mechanical stresses are applied to the bonded structure in order to detach the donor substrate  1  and the nucleation layer  2 . For this, the Smart Cut© process may be employed, i.e., a heat treatment is carried out at a temperature of about 500° C. to 600° C., for a time period of about 30 minutes up to about 3 hours, for example. Alternatively, a laser lift-off technique that is also known in the art may be applied in order to detach the donor substrate  1 . 
         [0025]    After detachment and a surface treatment like grinding and/or chemical-mechanical polishing the wafer results that is illustrated in the lower sketch of  FIG. 1 . On the silicon substrate  5  it is arranged the doped layer  6 . On the doped layer  6  it is arranged the first (intrinsic) silicon layer  7 . On the silicon layer  7  it is arranged a buried oxide layer  9  resulting from the bonded oxide layers  4  and  8 . On the buried oxide layer  9  it is arranged the second silicon layer  3 . Exemplary thicknesses of the individual layers of the wafer are as follows. The doped layer  6  may have a thickness of some μm, for example, 2 to 5 μm. The (intrinsic) silicon layer  7  may have a thickness of some 50 nm. The buried oxide layer  9  may have a thickness of 5 to 25 nm and the top silicon layer  3  may have a thickness of 5 to 20 nm. 
         [0026]    In  FIG. 2  an embedded DRAM device in a DRAM part A integrated with SOI transistors of a logic part B for addressing the DRAMs manufactured by means of the wafer shown in  FIG. 1  is illustrated. On the left-hand-side the DRAM part A is illustrated and on the right-hand side of  FIG. 2  the logic part B is illustrated. In the DRAM part A a capacitor deep trench  10  extending to the doped layer  6  that functions as a capacitor back plate is illustrated. A control FET  11  is formed in the DRAM part A with a channel region formed in the upper silicon layer  3 . The control FET  11  may be realized as a fully depleted or partially depleted device. The thickness of the upper silicon layer  3  is chosen accordingly. 
         [0027]    The DRAM part A and the logic part B are separated from each other by a shallow trench isolation  12 . Transistors  13  formed in the logic part B are also separated from each other by shallow trench isolation  12 . Regions of the silicon layer  7  can be easily converted into doped regions in order to form back-biasing regions for the transistors  13 . For example, a region of the silicon layer  7  below the left transistor  13  in the logic part B may be n doped with a concentration of some 10 18  cm −3  whereas a region of the silicon layer  7  below the right transistor  13  in the logic part B may be p doped with a concentration of some 10 18  cm −3  depending on the Vt shift we want to induce in the transistor channels formed in the upper silicon layer  3 .  FIG. 2 , moreover, shows contacts  14  for back-biasing. N back-biasing regions in the logic part B are connected with each other through the n +  doped doped layer  6 . In order to ensure sufficient electrical resistivity between two back-biasing contacts it might be considered necessary to keep some part of the intrinsic silicon layer  7  undoped or p doped. Thus, the intrinsic silicon layer  7  might be provided with a thickness of some 100 to 300 nm. 
         [0028]    It should be noted that the shallow trench isolators  12  might be provided extending partly into the doped layer  6 . They might also be provided extending through the doped layer  6  and into the substrate  5  thereby cutting the n +  doped layer  6 , Different embedded DRAM blocks can be separated by such shallow trench isolators  12  reaching into the substrate  5 . 
         [0029]    All previously discussed embodiments are not intended as limitations but serve as examples illustrating features and advantages of the invention. It is to be understood that some or ail of the above described features can also be combined in different ways.