Abstract:
A multiprocessor system comprises a series of processors arranged to process data in an assembly-line fashion. Each processor includes an executor (execution unit, instruction decoder, and program counter) and a set of registers. Each set of registers is divided into two banks. At any given time, one bank is the “active” bank that is accessible by the local processor, and the other is the “shadow” bank, inaccessible to the local processor. Each processor but the last writes in parallel to its active bank and to the shadow bank of the immediate downstream processor. When all processors have completed working the data in their respective possession, a context-switch is performed switching register banks so that former active banks become shadow banks and former shadow banks become active banks. This makes data that was being processed by an upstream processor virtually immediately available to a local processor. This saves the latency that would be involved in transferring register data after the data is processed. Accordingly, system throughput is improved.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to data processing and, more particularly, to multiprocessor data processing. A major objective of the invention is to provide for improved performance in a pipelined series of processors. 
     Much of modern progress is associated with advances in computer technology. A classical computer system includes a processor and memory. The memory includes memory storage locations, each with a unique memory address. The contents of the memory include data and instructions. The instructions constitute one or more computer programs according to which data is to be worked (manipulated). The processor reads the instructions from memory and executes them. According to the instructions executed, the processor reads data from memory, manipulates the data, and writes data to memory. 
     The processor itself can include an instruction decoder, an execution unit, a set of registers, and a program counter. The instruction decoder decodes instructions for execution by the execution unit. The execution unit uses the registers as a very small and very fast local memory, for example, to store coefficients, operands, partial results and final results for various operations called for by the instructions. The program counter is, in effect, a self-incrementing register so that, by default, instructions are fetched from memory in the order of the addresses of the memory locations at which they are stored. This default order can be changed as called for by various conditional and unconditional “jump” instructions. 
     The earliest processors had to complete execution of an instruction before the next instruction was fetched. Since an instruction fetch from memory is relatively time consuming, processors are usually designed with instruction buffers to hold instructions, e.g., at successive memory locations, likely to be used next. Still a delay would be involved where processing of one instruction had to wait until execution of the previous instruction was complete. 
     Pipelining, analogous to assembly lines in manufacturing, was introduced to minimize the latency between instruction executions. For example, in a two-stage pipeline, one instruction can be decoded while the previous instruction is being executed. Multi-stage pipelines break instruction execution into stages, with each stage processing a different instruction. The latency between instructions is reduced roughly in proportion to the number of stages in the pipelined. 
     Architectural advances such as pipelining, along with increasing circuit densities and clock speeds, have provided dramatic improvements in processor performance over the years. At any given level of processor development, further advances in performance could be achieve by using multiple processors. While parallel arrangements of processors are more widely known, serial arrangements of processors can be used to great advantage in many situations. 
     In a serial multiprocessor system, a first data set can be worked by a first processor. The data, as worked by the first processor, can then be worked by a second processor; in the meantime, a second data set can be worked by the first data processor. Then, the first data set can be worked by a third processor, the second data set worked by the second processor, and a third data set worked by the first processor. For example, the first processor performs error detection and correction, the second processor analyzes the data to determine what further processing should be performed, and the third processor performs the further processing. The data is thus pipelined through the series of processors to reduce the latency between data sets. In this case, the pipeline stages are not execution stages within a processor, but separate processors within the series. 
     The performance of a pipelined series of processors is adversely affected to the extent of any latency involved in transferring data from one processor to the next. If the transfer involves reading and writing to a common main memory, this latency can be quite large. The latency can be much reduced if some or all of the data can be transferred directly from the registers of the upstream processor to those of the downstream processor. 
     One limitation of this approach is that the memory capacity of a processor&#39;s register set is typically very small (so that access speeds can be high). For example, a typical processor might only be able to access sixteen 32-bit registers. (A processor might have a greater number of registers, but only be able access a limited number of these without switching operating modes.) Nonetheless, there are applications that involve sufficiently small data sets that all or most data that needs to be transferred can be transferred directly between processors. For example, once an upstream processor completes its processing of a data set, it can transfer the data from its registers to a downstream processor using “store” (or “store multiple”) commands, while the downstream processor uses “load” (or “load multiple”) commands to transfer the data into its registers. 
     Of course, there is still a latency involved in the inter-processor transfer of data. Even with such efficient instructions as “load multiple” and “store multiple”, the latency measured in clock cycles will exceed the number of registers involved in the data transfer. What is needed is a pipelined serial processor system that minimizes this latency to provide for greater system throughput. 
     SUMMARY OF THE INVENTION 
     The present invention provides a multiprocessor system in which a processor performs writes concurrently to its active register bank and to a shadow register bank of a downstream processor. After processing of a first data set is completed, a context switch causes the former shadow register bank to become the active register bank for the downstream processor. Thus, the second processor can begin data manipulation of the first data set without an additional data transfer between register banks. In the meantime, the first processor can manipulate a second data set in accordance with a pipelining strategy. Thus, the latency associated with inter-processor data transfer is reduced since all or most of the transfer takes place during processing rather than after completion of processing. 
     The invention provides for two or more processors. Many applications would require that processors switch context in a coordinated fashion. To this end, the system can include global control logic. Each processor informs the global control logic when it has completed its processing of a current data set. This informing, for example, can involve processing a instruction to signal that the program is done. The global control logic determines when all processors are done and, when they are, can issue a context-switch command. In response to this command, all active and shadow register banks can switch roles. 
     The switch can be conceptualized as effected by 2×2 multiplexers. Write inputs to the multiplexer come from the local and upstream processors. The two write outputs are respectively directed to two register banks, one of which is the “active” register bank and the other of which is the “shadow” register bank at any given time. This multiplexer can be built into the register set (e.g., in the cases of registers with dual write ports) or be external. The multiplexer can be controlled directly by the global control logic or indirectly via the local processor. The active register bank is readable by the local processor without a context switch, while the shadow register is not readable by the local processor without a context switch. 
     In some cases, the data manipulation by an upstream processor may determine how the data is to be processed by a downstream processor. To this end, the processors are coupled so that a downstream processor can set its program counter in response to data received from an upstream processor. The program count represents the memory location of the next instruction to be fetched; setting the program count selects the program to be executed. Thus, the program to be executed can be selected based on the outcome of a data analysis by an upstream processor. 
     A major advantage of the invention is the reduction of the data transfer latency between pipeline stages. Instead of transferring data register by register after data processing is complete, the data is transferred during processing. After data processing, all that is required is a context switch. Such a switch can be effected in one clock cycle, as opposed to a number of clock cycles exceeding the number of registers involved in the data transfer. Another advantage of the invention is that the context switches can be coordinated among processors. In addition, program selection for a downstream processor can be conveniently selected by an upstream processor. These and other features and advantages of the invention are apparent from the description below with reference to the following drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a multiprocessor system in accordance with the present invention. 
     FIG. 2 is a flow chart of a method of the invention practiced in the context of the system of FIG.  1 . 
     FIG. 3 is a block diagram of a second multiprocessor system in accordance with the present invention. 
     FIG. 4 is a block diagram of a processor of the multiprocessor system of FIG.  3 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A multiprocessor system AP 1  comprises a series of processors P 1 , P 2 , and P 3 , respective memories ME 1 , ME 2 , ME 3 , and global control logic GCL. Each processor P 1 , P 2 , P 3  includes a respective executor E 1 , E 2 , E 3 , a respective multiplexer MX 1 , MX 2 , MX 3 , and a respective register set RS 1 , RS 2 , RS 3 . Each register set RS 1 , RS 2 , RS 3 , includes a first register bank R 1 A, R 2 A, R 3 A, and a second register bank R 1 B, R 2 B, R 3 B. Each executor E 1 , E 2 , E 3 , includes a respective instruction decoder ID 1 , ID 2 , ID 3 , a respective execution unit EU 1 , EU 2 , EU 3 , and a respective program counter PC 1 , PC 2 , PC 3 . 
     Each memory ME 1 , ME 2 , ME 3  contains data to be worked and programs of instructions for working the data. System AP 1  is general purpose, so the data and instructions can be varied in many ways. By way of example, memory ME 1  can include a program directed to error detection and correction; memory ME 2  can include a program to perform a preliminary data analysis, as well as a program to handle cases in which errors detected in the previous stage cannot be corrected; and memory ME 3  can include various programs that are selected as a function of the result of the analysis performed by the analysis program stored in memory ME 2 . 
     Processors P 1 , P 2 , and P 3  are structurally identical. Accordingly, the following detailed description of processor P 1  serves also as a description of processors P 1  and P 3 . Differences between the processors due to their different series positions as first (P 1 ), intermediate (P 2 ), and last (P 3 ) are also indicated below. 
     Executor E 2  of processor P 2  is coupled to memory ME 2  for reading instructions and data therefrom and for writing data thereto. More specifically, executor E 2  reads the instruction stored at the memory location indicated in program counter PC 2 . By default, program counter PC 2  increments, but can jump to a non-sequential memory address using various conditional and unconditional jump instructions. 
     Executor E 2  is also coupled to register set RS 2  through multiplexer MX 2 . Executor E 2  is coupled to only one of register banks R 2 A and R 2 B at any given time according to the setting of multiplexer MX 2 . Herein, the bank of a local register set to which a processor is coupled is referred to as the “active” bank, and the other local bank is referred to as the “shadow” bank. Selection of either bank R 21  or R 22  as the active bank is made by global control logic GCL, which controls all three multiplexers MX 1 -MX 3  concurrently. 
     Multiplexer MX 2  is a 2×2 multiplexer. In the case of a register write operation, multiplexer MX 2  has two write inputs and two write outputs. The write outputs are coupled to respective register banks R 2 A and R 2 B. One write input is coupled to local executor E 2 , while the other write input is coupled to upstream executor E 1 . Thus, upstream executor E 1  is coupled to the current shadow register bank of register set RS 2 . Accordingly, the contents of the local shadow register bank mirrors the contents of the upstream active register bank. Local executor E 2  can read from the respective local active bank (via first and second operand paths). 
     Executor E 2  is coupled to global control logic GCL for indicating when the program being executed by executor E 2  is “done”. This indication is provided in response to a “signal program done” instruction to that effect. Global control logic GCL is also coupled to processors P 1  and P 3  to the same end. When “done” indications are received from all three processors P 1 , P 2 , and P 3 , global control logic GCL issues a context-switch command to multiplexers MX 1 -MX 3 . Thus, all three multiplexers MX 1 , MX 2 , and MX 3  are switched concurrently. 
     As indicated above, processors P 1  and P 3  are essentially identical to processor P 2 . However, since processor P 1  is the first in the series, multiplexer MX 1  is not coupled to an upstream executor. Likewise, since processor P 3  is the last in the series, executor E 3  is not coupled to a downstream multiplexer. 
     A method M 1  practiced in the context of system AP 1  in accordance with the present invention is flow charted in FIG.  2 . This flow chart focuses on the perspective of intermediate processor P 2 , since it is both downstream (relative to processor P 1 ) and upstream (relative to processor P 3 ). Accordingly, method M 1  is shown with a first step S 11  of working data. This involves reading data from the active bank (e.g., R 2 A) of register set RS 2 , writing to the active bank (e.g., bank R 1 A) of local register set RS 2 , and copying (writing forward) to the shadow bank (e.g., R 3 B) of downstream register set RS 3 . Concurrently, processor P 1  forwards a copy of data it is writing to its active bank (e.g., R 1 A) to the shadow bank (e.g., R 2 B) of processor P 2 . From the perspective of processors P 1  and P 3 , step S 11  also encompasses the inputting data to processor P 1 , e.g., as data processing begins, and outputting data from processor P 3 , e.g., as data processing ends. 
     Once it completes its processing of the current data set, processor P 2  indicates to global control logic GCL that it is “done” at step S 12 . Processors P 1  and P 3  also provide “program done” indications in the same time frame, although not, in general, at the same time. Once global control logic GCL receives “done” indications from all three processors, it issues a context-switch command, which is received by all three processors at step S 13 . 
     All three processors (or, more specifically, their multiplexers) execute the context switch command at step S 14 . This execution involves switching the bank (e.g., R 2 A) that was active during previous step S 11  so that it becomes the shadow bank, and switching the bank (e.g., R 2 B) that was “in the shadow” in step S 11  so that it becomes the active bank. If the upstream processor has provided a program counter value, it is adopted by the local processor at step S 14 . 
     Once the context switch is complete, method M 1  returns to step S 11 . In this next iteration of step S 11 , the data set worked by the local processor moves to the downstream processor, and the local processor processes the next data set in the series. 
     System AP 1  is an example of a system designed from the ground up to take advantage of the present invention. For many reasons, including compatibility with established processor architectures, it can be necessary to “retrofit” an existing processor design with the present invention. System AP 2 , as shown in FIG. 3, is an example of a system based on the Arm 7TDMI processor, available from VLSI Technology, San Jose, Calif. 
     System AP 2  comprises processors  2 P 1 ,  2 P 2 ,  2 P 3  arranged in a linear array. Associated with each processor is a respective local memory  2 M 1 ,  2 M 2 ,  2 M 3 , and a coprocessor CP 1 , CP 2 , CP 3 . Global control logic  2 CL coordinates the actions of the respective pairs of processors and coprocessors. 
     System AP 2  differs from system AP 1  primarily in the presence of coprocessors CP 1 , CP 2 , and CP 3 . The core ARM processors do not provide directly for some of the instructions called for by the present invention. For example, the native ARM instruction set does not provide a “done” signal in response to an instruction to do so. The ARM does recognize a set of coprocessor instructions that it leaves for a coprocessor to execute. In this case, the coprocessors provide the “program done” signals in response to a coprocessor instruction, e.g., at the end of a program, to do so. 
     The coprocessors are also used to manage transfer of a program counter selected by an upstream processor. The upstream processor transfers the desired count to the local coprocessor. The local coprocessor holds the count until it can be transferred to the program counter of the local processor during the next context switch. 
     The memory connections are depicted in simplified form in FIG.  3 . Each memory is coupled both to the respective processor and the respective coprocessor. Thus, memory  2 M 2  is coupled to both processor  2 P 2  and coprocessor CP 2 . In this way, both the processor and the coprocessor receive all instructions to enable speculative execution. 
     The processors are coupled as shown in FIG.  3 . Each upstream processor (e.g.,  2 P 1 ) provides to the local processor (e.g.,  2 P 2 ) a write enable signal, a four-bit address (for sixteen total registers), and a 32-bit data word. Each upstream coprocessor (e.g., CP 1 ) provides to the local coprocessor (e.g., CP 2 ) a 15-bit program count and a write enable signal to indicate when the asserted program count is valid. Each coprocessor (e.g., CP 2 ) is coupled to its respective processor (e.g.,  2 P 2 ) for receiving a “done” or “CP control” signal therefrom and for providing the count data and a count write signal thereto. 
     The standard ARM7TDMI has several operating modes including User 32 , Fast IRQ (FIQ), Supervisor, IRQ, Abort, and Undefined Instruction. In each mode, the processor can access sixteen registers. In system AP 2 , context-switches are between supervisor mode and FIQ mode. These modes share registers R 0 -R 7 , so these registers are not switched. Register R 15  is the program counter and is also not switched. Registers fiq 8 -fiql 4  are switched with registers R 8 -R 12 , svcR 13 , and svcR 14 ). This illustrates an optional feature of the invention: switching some registers while leaving some unswitched. 
     This situation is depicted in FIG. 4 with respect to processor  2 P 2  and its main processor  2 P 2  and its register set  2 R 2 . In FIG. 4, the write ports are shown on the left of the register banks, while the read ports are shown to the right. As indicated by the Xs on input lines, only one write port is enabled for each of the switched register banks. For one of the switched register banks, the local write port is enabled, while for the other, the upstream write port is enabled. Functionally, the dual write ports correspond to built-in multiplexers corresponding to MX 1 -MX 3  of system AP 1 . The dual read ports are used to present first and second operands to processor  2 P 2  for two-operand operations. 
     The present invention provides for many alternatives to the embodiments detailed above. Processors can have dedicated local memory, memory common to all processors, or both. Preferably, data originally input to an upstream register set is copied to a downstream register set. However, in cases where only modified data is copied, provisions must be made for unmodified data to be copied at some point. For example, register flags can be used to indicate (with “dirty bits”) modified data. Once all data modifications have been completed, unmodified data can be transferred using, for example, load-store commands. Alternatively, unmodified data can be transferred during unused write cycles of the upstream processor. 
     The invention provides for pipelines as short as two processors, and imposes no maximum number of processors. Multiple pipelines can be used in parallel to increase throughput. The invention is not limited to two register banks per processor. Other variations upon and modifications to the described embodiments are provided for by the present invention, the scope of which is limited only by the following claims.