Abstract:
An automatic transistor checking method is provided, whereby an unknown, bipolar transistor may be typed, pinned and checked for forward DC gain, H fe . The method is suitable for portable instruments, because the method uses little battery current to perform the H fe  measurement. The method automatically determines transistor type (NPN or PNP) and pinout, making it suitable for quick checking of batches of unknown devices.

Description:
This application is a continuation of Ser. No. 08/858,860, now U.S. Pat. No. 5,355,082. 
    
    
     FIELD OF THE INVENTION 
     This invention relates generally to the field of measurement instruments and, more particularly, to automatic transistor testers for determining transistor pinout, type and DC gain (H fe ) of bipolar junction transistors. 
     DISCUSSION OF THE PRIOR ART 
     Transistor testers are known which can readily measure the forward DC gain, H fe , of a bipolar junction transistor (BJT). The general topology of such a tester is shown in FIGS. 1A and 1B. In FIG. 1A, the tester is configured for measurement of an NPN type of transistor. In FIG. 1B, the tester is configured for the measurement of a PNP type of transistor. As seen in both FIGS. 1A and 1B, H fe  is generally measured by injecting a small current I B  into the base terminal B of the transistor under test (TUT), and measuring the resulting current I meas  flowing in the collector terminal C of the transistor under test TUT. In order to obtain valid results from this test, the measurement instruments must be configured appropriately for the type and pinout of the transistor under test. Furthermore, if H fe  of the transistor under test TUT is large, then injecting a small base current I B  may produce a large collector current I meas . However, in portable instruments which rely on battery power, it is undesirable to produce large currents, because they may substantially reduce battery life. 
     Therefore, it is a general aim of the present invention to provide an improved transistor tester. 
     SUMMARY OF THE INVENTION 
     In accordance with the foregoing aim, and other aims which will be readily apparent to those skilled in the art, a method of finding the forward H fe  of a transistor under test having a first terminal, a second terminal and a third terminal is provided. According to the method of the present invention, a diode check is performed between the first terminal and the second terminal of the transistor. A diode check is a simple test, known to those skilled in the art, for determining the existence and polarity of a single P-N junction in a semiconductor device. In BJTs, such P-N junctions exist between the base and collector, and between the base and emitter. These junctions may be identified by use of a diode check. A diode check is also performed between the second terminal and the third terminal of the transistor. The transistor type and the base terminal of the transistor are identified in accordance with the results of the diode checks. Once the transistor type and base terminal are known, the H fe  of the transistor may be measured. 
     According to the present invention H fe  may be measured by injecting a current into one unidentified terminal of the transistor, i.e. a terminal other than the base terminal. A current flows in-the base terminal of the transistor, responsive to the current injected. This base current is measured. Furthermore, by alternatively injecting a current into the other unidentified terminal, and measuring the current flowing in the base terminal of the transistor, the forward H fe  and the identities of the collector and emitter terminals may be determined. 
     The present invention may be better understood with reference to the accompanying drawings, wherein like reference designations represent like elements. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1a and FIG. 1b are schematic representations of a transistor checker according to the prior art. 
     FIG. 2 is a block diagram of a transistor checker which may be used to practice the method of the present invention. 
     FIG. 3 is a flow chart of a transistor checking method according to the present invention. 
     FIG. 4 is a truth table relating transistor type and base terminal connection to diode check results. 
     FIG. 5 is a flow chart of one embodiment of FIG. 3, step 307. 
     FIG. 6 is a flow chart of an alternate embodiment of FIG. 3, step 307. 
     FIG. 7a and FIG. 7b are schematic representations of a circuit for practicing a method of measuring H fe  according to the present invention. 
     FIG. 8a and FIG. 8b are schematic representations of a circuit for performing a diode check with respect to two terminals of a transistor under test. 
     FIG. 9a and FIG. 9b are schematic representations of another circuit for performing a diode check with respect to two terminals of a transistor under test. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention, and specific embodiments thereof are now described with reference to the figures. 
     An apparatus suitable for practicing the method of the present invention is shown in a representative block diagram in FIG. 2. First, second and third-terminals 201, 203 and 205 of a transistor under test TUT are connected respectively to tester terminals X, Y and Z. Test signals may be applied to the transistor under test TUT through tester terminals X, Y and Z. Responses of the transistor under test TUT to test signals applied thereto are monitored through tester terminals X, Y and Z. 
     Application of test signals and measurement of responses is achieved through the intermediary of switch matrix 207. A plurality of test circuit signals 209 and 211 may be selectively connected with tester terminals X, Y and Z by switch matrix 207. Thus, diode check circuit 213 and H fe  measurement circuit 215 may be connected to transistor under test TUT in a variety of configurations. 
     A method of finding the H fe  of a transistor under test TUT using the apparatus of FIG. 2, is now described in connection with FIGS. 3 and 4. The steps of the method are set forth in the flow chart of FIG. 3. 
     First, switch matrix 207 is configured to make connections between diode check circuit 213 and tester terminals X and Y, for performance of a first diode check (Step 301). Possible embodiments of this diode check are discussed below in connection with FIGS. 8a, 8b, 9a and 9b. These diode checks are performed in two parts, with switch matrix 207 configured to make the connections shown in each part in turn. 
     A second diode check (step 303) is performed between tester terminals Y and Z, by appropriate configurations of switch matrix 207. The possible results of the first and second diode checks may be represented as shown in the first two columns of FIG. 4. 
     Depending on the transistor type and which tester terminal has been connected to the base terminal of the transistor under test TUT, three results are possible for each diode check. The diode check may indicate an open circuit (&#34;OPEN&#34; in FIG. 4) between the terminals, the diode check may indicate a diode connected with the anode at one terminal, or the diode check may indicate a diode connected with the anode at the other terminal. FIG. 4 is a truth table which relates the six combinations of diode check results to the transistor type and base terminal connection indicated by those results. For example, if diode check 1 indicates that a diode is connected between terminals X and Y, having the anode at terminal X, and diode check 2 indicates an open circuit; then the transistor under test TUT is an NPN transistor having the base terminal connected to tester terminal X. Thus, by use-of this truth table or by use of logic implementing the function of this truth table, transistor type and the base terminal connection may-be derived from the results of the first and second diode checks (step 305). 
     Once the transistor type and base terminal connections are known, H fe  may be measured (step 307). Two alternatives with respect to performing the H fe  test are now discussed in connection with FIGS. 5 and 6. 
     A test for H fe  may serve a variety of purposes. One possible purpose includes identifying the three terminals 201, 203 and 205 of the transistor under test TUT, together with determining the actual H fe  of the transistor under test TUT, as accomplished in the additional method steps of FIG. 5. Another possible purpose is to only complete identification of the three terminals 201, 203, and 205 of the transistor under test TUT as accomplished by the additional method steps of FIG. 6. FIGS. 5 and 6 are now discussed in turn. 
     In FIG. 5, an assumption is made with respect to the collector/emitter (C/E) orientation of the transistor under test TUT (step 501). That is, the tester terminal to which the base of the transistor is connected is known. Of the remaining two tester terminals, one is assumed to be connected to the collector of the transistor, while the other is assumed to be connected to the emitter of the transistor. A test for H fe  is performed on the basis of that assumption (step 501). Next, the other possible C/E orientation is assumed, and the H fe  test is repeated (step 503). One of steps 501 and 503 will produce a larger value for H fe  than the other. This larger value for H fe  is the desired, forward characteristic of the transistor under test TUT. Therefore, the larger value of H fe  and the C/E orientation which produced that larger value of H fe  is reported as the result (step 505). 
     If only the correct orientation of the transistor under test is desired, the simpler and quicker test of FIG. 6 may be performed. Since the desired, forward H fe  is typically large with respect to a fixed threshold, the H fe  test may be performed once using one assumed C/E orientation (step 601). The result may be compared to the threshold (step 603) and either the assumed orientation is reported (step 605) or the other orientation is reported (step 607) as the result. 
     An H fe  test according to the present invention is now described in connection with FIGS. 7A and 7B. These figures illustrate the same test, as applied to an NPN type transistor under test TUT (FIG. 7A) and a PNP type transistor under test TUT (FIG. 7B). The tests are identical and therefore, described together. A collector current I c  is injected in the collector C of transistor under test TUT by current source 701. The injected collector current I c  causes a base current I meas  to flow in the base of transistor under test TUT. The base current I meas  is measured by metering circuits 703, which are known in the art. H fe  may then be calculated conventionally, in accordance with the relationship: ##EQU1## The collector and emitter terminals shown in FIGS. 7A and 7B are those assumed in each of the H fe  tests described above. 
     By injecting collector current I c  and measuring base current I meas , far less current may be drawn by the transistor tester according to the present invention, because I c  may be chosen to be small, and I meas  will be smaller than I c  for a typical transistor under test TUT. This is in contrast to the prior art tests of FIGS. 1A and 1B, wherein a small injected I b  could result in a large I meas , because of the H fe  of the transistor under test TUT. 
     Furthermore, the measurement of H fe  according to the present invention produces a more accurate result than that of the prior art, because H fe  is a function of collector current I c . In a tester according to the present invention, I c  is a controlled parameter which may be selected to be substantially equal to a value used in a specific application of a transistor, for example. Thus, the measured H fe  is that experienced when using the transistor in the specific application. 
     Diode tests are discussed above in connection with FIGS. 2 and 3, are now described in connection with FIGS. 8A, 8B 9A and 9B. These figures simply illustrate known methods for determining the existence and plurality of a diode between a pair of terminals. In each pair of figures, the first figure illustrates the first half of a test, wherein one polarity is tested, while the second figure illustrates the second half of a test, wherein the second polarity is tested. 
     In FIGS. 8A and 8B, the existence and polarity of a diode is tested for by connecting a source of current I test  across a pair of terminals 801 and 803 of the transistor under test TUT. In FIG. 8A, the source injects current I test  into terminal 803 and extracts current I test  from terminal 801. In FIG. 8B, the current source has been reversed, so that it injects current I test  into terminal 801 and extracts current I test  from terminal 803. In each case, the voltage between terminals 803 and 801, V meas  is measured. If the two parts of this test produce different values for V meas , then the test indicates a diode connected between terminals 801 and 803. The anode of the diode is connected to the one of terminals 801 and 803 into which current I test  was injected when the smaller V meas  was produced. If substantially similar values for V meas  are produced by the two parts of this test, then the reported result is &#34;OPEN&#34;, as noted in the first two columns of FIG. 4. 
     FIGS. 9A and 9B illustrate a similar test, performed using the Thevenin equivalents of the circuits illustrated in FIGS. 8A and 8B. In this two-part test, a voltage V BB  is applied across terminals 901 and 903 of the transistor under test TUT. If a diode is connected across terminals 901 and 903, then the magnitude of the current flowing in the terminals I meas  will be large when the positive terminal of the source of voltage V BB   is connected to the anode of the diode. If I meas  is small under both parts of this test, then the test reports &#34;OPEN&#34; as seen in the first and second columns of FIG. 4. 
     Although the present invention has been described in connection with a number of specific embodiments, numerous extensions, modifications and other applications should now be evident to those skilled in the art. The embodiment presented herein are illustrative, and not to be considered limiting, having been presented by way of example only. The scope of the present invention is limited only by the appended claims and equivalents thereto.