Abstract:
Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.

Description:
FIELD OF THE INVENTION 
     This invention relates to a HOUT position control circuit used to control position where image is displayed in a display. 
     BACKGROUND OF THE INVENTION 
     Multisync monitors use a HOUT position control circuit to control the delay amount from input horizontal synchronous signal (hereinafter referred to as ‘Hsync signal’) to output horizontal drive signal (hereinafter referred to as ‘Hout signal’) so as to conduct the control of image display position (hereinafter referred to as ‘position control’). 
     Conventionally, in the HOUT position control circuit of multisync monitors, an adjustable delay circuit is provided in PLL loop, and the position control is conducted by controlling the delay value of the adjustable delay circuit. 
     FIG. 1 is a block diagram showing the composition of a conventional HOUT position control circuit. 
     As shown in FIG. 1, the conventional HOUT position control circuit is provided with adjustable delay circuits  24 ,  25  at the input stage of a phase comparator  3 . Two input signals to the phase comparator  3  are separately delayed by the adjustable delay circuits  24 ,  25 . The position control is conducted by controlling the delay value. 
     FIG. 2 is a block diagram showing the composition of the adjustable delay circuits  24 ,  25  in FIG.  1 . 
     Multisync monitors need the delay amount to be a same proportion to input Hsync signal. Therefore, sawtooth wave  31  synchronized with input signal  29  of the adjustable delay circuits  24 ,  25  is generated by a sawtooth generator circuit  28 , and then delayed output signal  27  is made by using a comparator  32 . 
     The control of delay value is conducted by using delay control voltage  30 , which is DC voltage. 
     FIG. 3 is a timing chart showing the process of generating a delay value from sawtooth wave. 
     However, since the conventional HOUT position control circuit has the adjustable delay circuit in PLL loop, a dispersion in the adjustable delay circuit may cause a deviation in position. 
     Further, since the adjustable delay circuit is operated in analogue manner, the delay value may vary depending on a noise thereby causing a jitter. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the invention to provide a HOUT position control circuit that can suppress a deviation in position or a jitter. 
     It is a further object of the invention to provide a position control circuit used to control the vertical position of display image in a multisync monitor that can suppress a deviation in position or a jitter. 
     According to the invention, a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor, comprises: 
     a first PLL circuit that is phase-locked with input horizontal synchronous signal; 
     a second PLL circuit that is phase-locked with output of the first PLL circuit; and 
     means for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal. 
     According to another aspect of the invention, a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor, comprises: 
     the position control of display image is conducted in digital manner. 
     According to another aspect of the invention, a position control circuit used to control the vertical position of display image in a multisync monitor, comprises: 
     a first PLL circuit that is phase-locked with input vertical synchronous signal; 
     a second PLL circuit that is phase-locked with output of the first PLL circuit; and 
     means for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input vertical synchronous signal to output vertical drive signal. 
     According to another aspect of the invention, a position control circuit used to control the vertical position of display image in a multisync monitor, comprises: 
     the position control of display image is conducted in digital manner 
     Also, the invention offers a multisync monitor using the above-composed HOUT position control circuit or a position control circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be explained in more detail in conjunction with the appended drawings, wherein: 
     FIG. 1 is a block diagram showing the conventional HOUT position control circuit, 
     FIG. 2 is a block diagram showing an adjustable delay circuit in FIG. 1, 
     FIG. 3 is a timing chart showing the process of generating a delay value from sawtooth wave, 
     FIG. 4 is a block diagram showing a HOUT position control circuit in a preferred embodiment according to the invention, 
     FIG. 5 is a timing chart showing the operation of the HOUT position control circuit in FIG. 4, and 
     FIG. 6 is a block diagram showing a position control circuit for Vsync signal in another preferred embodiment according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiments of the invention will be explained below referring to the drawings. 
     FIG. 4 is a block diagram showing a HOUT position control circuit in the preferred embodiment according to the invention. 
     In FIG. 4, a PLL circuit  1  is used to match the phase to Hsync signal  18  to be input and a PLL circuit  2  is used to match the phase to the output of a M value programmable decoder  7  of the PLL circuit  1 . 
     The components of the PLL circuits  1  and  2  are explained below. 
     Hsync signal  18  is input to a phase comparator  3  of the PLL circuit  1 , where it is phase-compared with the output of a 1/N programmable frequency divider  6 . Then, error output, I.e. output of the phase comparator  3 , is smoothed by LPF  4 . By the output voltage of the LPF  4 , the oscillation frequency of VCO  5  is controlled. 
     The 1/N programmable frequency divider  6  is used to change a frequency-division value N by the frequency of Hsync signal  18  to be input. A frequency-division value N is a positive integer and is set by a division value decoding value control circuit  8 . 
     For Hsync signal  18  to be input, system clock  14  phase-locked can be produced. The system clock  14  is used as a system clock to control the division value decoding value control circuit  8 , Hsync signal, vertical synchronous signal (hereinafter referred to as ‘Vsync signal’) etc. 
     An M value programmable decoder  7 , described later in FIG. 5, is used to decode the M th  clock of the 1/N programmable frequency divider  6 . The decode value M, where M is an integer, is set by the division value decoding value control circuit  8  when conducting the position control. 
     Also in the PLL circuit  2 , output of the M value programmable decoder  7  is phase-compared with FBP signal  17  generated in a Braun tube  13  by a phase comparator  9 , and then error output, i.e. output of the phase comparator  9 , is smoothed by LPF  10 . By the output voltage of the LPF  10 , the oscillation frequency of VCO  11  is controlled. 
     The frequency-division value N of a 1/N programmable frequency divider  12  is set to have the same value as the 1/N programmable frequency divider  6  in the PLL circuit  1 . Output of the 1/N programmable frequency divider  12  is used as Hout signal  16  in the Braun tube  13 . 
     The Hout position control operation in this embodiment is explained below. 
     At first, the operation of PLL circuits  1  and  2  is explained in FIG.  5 . The PLL circuit conducts the phase-locked oscillation to Hsync signal  18  to be input, by using the phase comparator  3 , LPF  4 , VOC  5  and 1/N programmable frequency divider  6 . 
     Hereupon, the frequency-division ratio of the 1/N programmable frequency divider  6  is set by the division value decoding value control circuit  8  based on the frequency of Hsync signal  18 . In general, the division value decoding value control circuit  8  is composed of microcomputer, DSP etc. 
     In FIG. 5, B) indicates Hsync signal  18  to be input, C) indicates output of the 1/N programmable frequency divider  6 , and A) indicates the timing of system clock  14  as the output of the VCO  5 . 
     Since Hsync signal  18  is phase-locked with the output of the 1/N programmable frequency divider  6 , they have the same timing. System clock  14  as the output of the VCO  5  corresponds to a frequency N times Hsync signal  18 . 
     Also in the PLL circuit  2 , the output of the M value programmable decoder  7  as input signal is phase-locked with FBP signal  17 . 
     The position control operation is explained below. 
     The M value programmable decoder  7 , which is synchronized with the 1/N programmable frequency divider  6 , outputs a pulse at an arbitrary count value M of the 1/N programmable frequency divider  6 . 
     In FIG. 5, C) and D) indicate the output of the 1/N programmable frequency divider  6  and the M value programmable decoder  7 , respectively. 
     The output D) of the M value programmable decoder  7  has a delay corresponding to M value set by the division value decoding value control circuit  8 , and outputs periodically the same signal as the output of the 1/N programmable frequency divider  6 . 
     The output D) of the M value programmable decoder  7  is phase-locked with FBP signal  17  by the PLL circuit  2 . Delay from Hout signal  16  to FBP signal  17  is a constant value determined by the Braun tube  13 . 
     The delay amount H from Hsync signal  18  to Hout signal  16  can be set by changing the M value of the M value programmable decoder  7 . 
     Accordingly, the control of delay amount H from Hsync signal  18  to Hout signal  16 , i.e. position control, can be performed by controlling the M value of the M value programmable decoder  7 . 
     Thus, in this embodiment, the position control can be performed if only setting the M value of the M value programmable decoder  7  in digital manner. Therefore, a conventional adjustable delay circuit for position control that is provided at the input of the phase comparator is not necessary any more. 
     The position control circuit in the embodiment can solve the problem that a fluctuation in delay value occurred in the adjustable delay circuit due to a noise etc. causes a jitter to affect the quality of image. Also, it can solve the problem that a dispersion in the adjustable delay circuit causes a deviation in position. 
     Also, in this embodiment, since the position control can be conducted in digital manner, pin valance correction, key balance correction etc. needed for the multisync monitor can be performed by controlling the M value set by the division value decoding value control circuit  8 . 
     Another preferred embodiment of the invention is explained below referring to the drawings. 
     FIG. 6 is a block diagram showing a position control circuit for Vsync signal according the invention. 
     In FIG. 6, except that Vsync signal  21  is input signal, V drive pulse  22  is a drive pulse output to the Braun tube  13  and VFBP  23  is FBP from the Braun tube  13 , the circuit composition is the same as that in the embodiment in FIG.  4 . The explanation of common components is omitted herein. 
     In this embodiment, like the embodiment in FIG. 4, for Vsync signal  21 , the position control can be performed using the value of the M value programmable decoder  7 . 
     Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modification and alternative constructions that may be occurred to one skilled in the art which fairly fall within the basic teaching here is set forth.