Abstract:
A semiconductor device is provided which has a plurality of output drivers whose slew rates are differentially controlled. The slew rates of the output drivers are controlled by a control means such that the slew rate of at least one of the output drivers is different than the slew rate of another output driver. Preferably, the slew rates are differentially controlled such that an output driver that drives a signal that reaches an output pin of a semiconductor package later slews at a faster rate than an output driver that drives a signal that reaches an output pin of a semiconductor package earlier. In this way all of the output pins of a semiconductor package can be driven to change states at approximately the same time. The slew rates of the output drivers can be differentially controlled through the utilization of programmable resistors.

Description:
This is a continuation of application Ser. No. 07/938,401, filed Aug. 31, 1992 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to semiconductor integrated circuit devices, and more specifically to output driver devices. 
     2. Description of the Prior Art 
     As is well known, a phenomenon known as power supply line noise inductance effects can significantly decrease the potential output performance of an integrated circuit device. This phenomena, which results from the inductance on various signal lines both on chip and from chip to package, is proportional to both the inductance and to the rate of change of the current with respect to time (di/dt), and causes the output signal and the power supply lines to oscillate or bounce. 
     Since the output of the chip is not output until the power supply lines have settled down, the power supply line noise inductance has the effect of slowing down the potential output performance of an integrated circuit device. Many different design techniques have been developed in an attempt to limit di/dt and simultaneously increase the output performance of the chip. 
     A common approach to this problem is to limit the di/dt for all output drivers. Limiting di/dt both allows the power supply line to stabilize faster and increases the amount of time taken by an output driver to change states. However, with appropriate di/dt limiting, this tradeoff can still result in a decrease in the access time at the output pins of the integrated circuit package, which is an increase in device performance. 
     Limiting di/dt has been accomplished by several methods. One method is to add resistors to the power supply lines of the output transistors or the stage driving the output transistors. The resistors uniformly reduce the rate of switching of the output drivers. Another method to limit di/dt is to use an output driver designed to drive the load with a constant di/dt. Another approach is to provide power buses for the output drivers which are separate from the rest of the circuit. 
     It is known that the outputs at the output pins of the integrated circuit package do not all change state at the same time. Since the chip cannot be validly accessed until the slowest output pin is ready, a wait time exists between the time at which the fastest output pin changes state and the time at which the slowest output pin changes state. 
     Currently available methods for di/dt limiting increase device operating speed by minimizing power supply oscillations, but the methods do not attempt to reduce the wait time. Thus, overall device operating speed is less than the theoretical maximum speed. 
     It would be desirable to increase device operating speed beyond that currently achievable through the reduction of the power supply oscillation settling time without suffering wait time delays to the extent of the prior art. 
     SUMMARY OF THE INVENTION 
     Therefore, according to the present invention a semiconductor device is provided which has a plurality of output drivers whose slew rates are differentially controlled. The slew rates of the output drivers are controlled by a control means such that the slew rate of at least one of the output drivers is different than the slew rate of another output driver. Preferably, the slew rates are differentially controlled such that an output driver that drives a signal that reaches an output pin of a semiconductor package later slews at a faster rate than an output driver that drives a signal that reaches an output pin of a semiconductor package earlier. In this way all of the output pins of a semiconductor package can be driven to change states at approximately the same time. The slew rates of the output drivers can be differentially controlled through the utilization of programmable resistors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a plan view of an integrated circuit package according to the present invention; 
     FIG. 2 is an illustration of a single output driver connected to an output pad; 
     FIG. 3 is a logic diagram of an output driver showing the preferred location of the differential di/dt control circuitry; 
     FIG. 4 is a schematic diagram of a NAND gate showing a preferred type of differential di/dt control circuitry; 
     FIG. 5 is a plan view of a selectable resistance load; and 
     FIGS. 6-9 are timing diagrams illustrating operation of various output driver circuits. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Generally, the purpose of this invention is to increase the operating speed of an integrated circuit device. It is known that operating speed can be increased by implementing circuitry in the output drivers to limit the rate of change of current (di/dt) drawn by the output drivers during state transition. This present invention in its preferred embodiment employs the novel idea of differential di/dt limiting for each output driver. 
     Differential di/dt limiting is defined as providing di/dt limiting circuitry to the output drivers so that at least one of the output drivers has a different di/dt limit than at least one of the other output drivers. The preferred embodiment of the differential di/dt limiting circuitry is described below. 
     FIG. 1 is an illustration of an integrated circuit  10  having 8 output pins, but it will be appreciated by those skilled in the art that other sized integrated circuits may take advantage of the invention described below. The integrated circuit package is accessed by outside means through the output leads  12 - 26 . A low voltage reference is provided through the lead  28  (Vss), and a high voltage reference is provided through the lead  30  (Vcc). An integrated circuit chip  32  is located within the integrated circuit package  34 . 
     The preferred location of the bond pads  36 - 50  are shown at the outside edge of the integrated circuit chip  32 . The output leads  12 - 26  are connected to the bond pads through bond wires  54 - 68 . The preferred location of the output drivers  70 - 84  are shown to be adjacent to the bond pads  36 - 50 . The output drivers  70 - 84  drive the data signals D 0 -D 7  received from the data source  86  so that an acceptable signal is provided to those devices accessing the integrated circuit  10 . The data signal is transmitted from the data source  86  to the output drivers  70 - 84  via the data lines  88 - 102 . Data source  86  represents any circuitry, such as sense amps, which generates data signals for communication off chip. 
     FIG. 2 is a symbolic representation of an individual output driver  104 , a bond pad  106  and a bond wire  108  of the integrated circuit  10 . The output driver consists of drive circuitry  110  and the differential di/dt control circuitry  112 . It will be appreciated by those skilled in the art that the differential di/dt control circuitry may be positioned between the high voltage reference  114  (Vcc) and the drive circuitry  110 , between the low voltage reference  116  (Vss) and the drive circuitry  110 , between both as shown, or in any other location such that di/dt will be limited to the output driver  110 . 
     FIG. 3 is a symbolic representation of the preferred embodiment of an output driver  104  and a bond pad  106 . The output driver consists of drive circuitry  110  and differential di/dt control circuitry  112 . The drive circuitry  110  consists of a NAND gate  118 , an inverter  120 , a NOR gate  122 , a p-channel transistor  124 , and a n-channel transistor  126 . The drive circuitry  110  is connected to a high voltage reference source  114  (Vcc), and a low voltage reference source  116  (Vss). As known in the art, transistor  124  can be an n-channel transistor to improve resistance to latch up effects. 
     Two signals are received by the output driver  104 , the output disable signal  128  and the data signal  130 . When the output disable signal  128  is low and the data signal  130  changes from low to high, the p-channel transistor  124  will go from an “off” state to an “on” state. The n-channel transistor  126  will go from an “on” state to an “off” state. The NAND gate  118  and the NOR gate  122  provide the voltage to drive the p-channel transistor  124  and n-channel transistor  126 , respectively. Therefore, limiting the slew rate of the NAND gate  118  and the NOR gate  122  limits the rate of change of current through the p-channel transistor  124  and the n-channel transistor  126 . 
     As the p-channel transistor  124  and n-channel transistor  126  change states they begin to draw current along with the rest of the drive circuitry  110 . The rate of change of this current is represented by di/dt. To control the rate of change of current, differential di/dt control circuitry is introduced between the power supply and NAND gate  118  and NOR gate  122 . The nomenclature of “differential di/dt control circuitry” is used because the di/dt limit will be different for some of the output drivers. 
     FIG. 4 represents the preferred embodiment of the NAND gate  118  portion of the drive circuitry  110  and the preferred embodiment of the differential di/dt control circuitry  112 . The NAND gate  118  consists of two p-channel transistors  132  connected in parallel and two n-channel transistors  134  connected in series. Each of the input signal lines  136  and  138  is connected to one of the p-channel transistors  132  and one of the n-channel transistors  134 . The differential di/dt control circuitry  112  consists of programmable resistors  140 . A lower value of resistance is used to provide less current limiting. 
     Resistor  140  connected to the p-channel devices  132  provides slew rate limiting during a positive-going transition of the NAND gate output, and resistor  140  connected to the n-channel devices  134  provides slew rate limiting during a negative-going transition of the output. The two resistors  140  need not have the same value, and one may in fact not be included depending on the particular design. NOR gate  122  is constructed in a similar manner, and operates analogously. 
     FIG. 5 is a preferred embodiment of the current limiting resistor  140 . The resistor  140  is a programmable poly resistor, but could be any other type of resistor as known in the art. Different values of resistance can be obtained by connecting the metal interconnect lead portion  142  to the poly resistor  144  at different contact locations  146 - 154 . Making contact at location  146  provides a higher value resistor, while making contact at location  154  provides a lower value resistor. Use of such programmable resistors allows a modular output driver design to be utilized to provide differential di/dt limiting to the various output drivers. 
     FIGS. 6-9 are timing diagrams of data signals D 0 -D 7  at various points on the integrated circuit  10 . The data signals D 0 -D 7  represent data from an 8 bit integrated circuit  10 , but it will be appreciated by those skilled in the art that other size integrated circuits will have similar timing diagrams and may take advantage of the invention described below. 
     FIG. 6 is a timing diagram representing data signals D 0 -D 7  at the data source  86  output. As described above, data source  86  represents any circuitry, such as sense amps or a register, that generates output signals. The data signals D 0 -D 7  are shown at the data source  86  changing from a low state at t a =0 to a high state at t a =1. It will be appreciated by those skilled in the art that the data signals D 0 -D 7  may not actually change states simultaneously. It will be further appreciated by those skilled in the art that state changes can also be from high to low or any combination thereof. 
     FIG. 7 is a timing diagram representing data signals D 0 -D 7  at the inputs to the output drivers  70 - 84 , respectively. The data signals D 0 -D 7  arrive at the input to the output drivers at various times ranging from t b =0 to t b =6. The time delays are due to differential propagation delay for the data signals D 0 -D 7 . The differential propagation delay is caused by various factors including different inductive and capacitive loading and longer data lines  88 - 102  for some of the data signals D 0 -D 7 . Output drivers located further from the data source will generally receive their data later. Also, output drivers further from supply pins may tend to switch slower due to resistance and inductance in the supply lines. 
     FIG. 7 shows D 0  and D 7  arriving at the output drivers  70  and  84  at the same time, D 1  and D 6  arriving at the output drivers  72  and  82  at the same time, D 2  and D 5  arriving at the output drivers  74  and  80  at the same time, and D 3  and D 4  arriving at the output drivers  76  and  78  at the same time. Because some of the data signals D 0 -D 7  arrive at an output driver sooner than others, those output drivers will begin to change states sooner than the others. It will be appreciated by those skilled in the art that the data signals D 0 -D 7  may arrive at the inputs of the output drivers at different times than those shown. 
     An integrated circuit  10  cannot be validly accessed by another device until all of its outputs at the output leads  12 - 26  have finished changing to their appropriate states. As a result the operating speed of the integrated circuit  10  is measured using the time at which the slowest output changes state. If there is less di/dt limiting for those output leads that change state slower than others, the slew rate of the slower outputs will increase. The time difference between when the fastest output lead changes state and when the slowest output lead changes state is therefore decreased or eliminated. 
     Less di/dt limiting also tends to cause greater power supply oscillation or bounce. The power supply oscillations cause the signals D 0 -D 7  at the output leads  12 - 26 , respectively, to oscillate. However, with differential di/dt limiting, the time saved by forcing the slower output leads to change states more quickly is greater than the increase in the time necessary for the output leads to stabilize. The result is a net increase in the integrated circuit  10  operating speed. 
     FIG. 8 is a timing diagram representing data signals D 0 -D 7  at the output leads  12 - 26 , respectively, of the integrated circuit  10  with the implementation of differential di/dt limiting circuitry  112 . The state at the output leads of the integrated circuit  10  receiving those data signals D 0 -D 7  that arrived at the input of an output driver sooner than others as illustrated in FIG. 7 will begin to change state sooner than the others. As shown in FIG. 8, output leads  18  and  20  receiving data signals D 3  and D 4  begin to change state at t c =0, output leads  16  and  22  receiving data signals D 2  and D 5  begin to change state at t c =1 output leads  14  and  24  receiving data signals D 1  and D 6  begin to change state at t c =2, and output leads  12  and  26  receiving data signals D 0  and D 7  begin to change state at t c =3. 
     As described above, the preferred differential di/dt control circuitry consists of a programmable poly resistor  140 . To provide less di/dt limiting, the programmable poly resistor  140  should be programmed for a smaller resistance. In the illustrated embodiment, the differential di/dt limiting circuitry  112  is applied so that di/dt is greater for output drivers  70  and  84  than for output drivers  72  and  82 , di/dt is greater for output drivers  72  and  82  than for output drivers  74  and  80 , and di/dt is greater for output drivers  74  and  80  than for output drivers  76  and  78 . 
     The larger di/dt is allowed to be, the faster an output lead will change state. As a result, the output leads  12  and  26  receiving signals D 0  and D 7 , respectively, change states in delta t c =1, the output leads  14  and  24  receiving signals D 1  and D 6  change states in delta t c =2, the output leads  16  and  22  receiving signals D 2  and D 5  change states in delta t c =3, and the output leads  18  and  20  receiving signals D 3  and D 4  change states in delta t c =4. The result is that all output leads  12 - 26  reach their final state simultaneously. 
     It will be appreciated by those skilled in the art that the above example is for illustrative purposes, and implementations will vary widely depending upon the particular characteristics of any particular device. For example, only one or two output drivers may need a faster di/dt limit in order to improve overall device operation. The particular levels of slew rate limiting programmed into the various output drivers will be a tradeoff between improving the output speed of the slower drivers, while keeping di/dt limiting low enough to minimize power supply bounce. 
     FIG. 9 is a timing diagram representing data signals D 0 -D 7  at the output leads  12 - 26 , respectively, of the integrated circuit  10  without the implementation of differential di/dt limiting. For this illustration, consistent with prior art practices, the slew rate of all output drivers is the same. The state at the output leads of the integrated circuit  10  receiving those data signals D 0 -D 7  that arrived at the input an output driver  70 - 84  sooner than others, as illustrated in FIG. 7, will begin to change sooner than the others. As shown in FIG. 9, output leads  18  and  20  receiving data signals D 3  and D 4  begin to change state at t d =0, output leads  16  and  22  receiving data signals D 2  and D 5  begin to change state at t d =1, output leads  14  and  24  receiving data signals D 1  and D 6  begin to change state at t d =2, and output leads  12  and  26  receiving data signals D 0  and D 7  begin to change state at t d =3. 
     Without differential di/dt limiting, the output leads that begin changing state before other output leads will also finish changing state before those other output leads. Because di/dt is not differentially controlled, the output leads  12 - 26  all change states at delta t d =4 resulting in the different output leads changing state at different times. The time difference between when the fastest output leads  18  and  20  receiving data signals D 3  and D 4  change state and when the slowest output leads  12  and  26  receiving data signals D 0  and D 7  is delta t d =3. 
     Thus, providing differential di/dt limiting for the output drivers of a device can improve its overall performance. Providing less limiting on otherwise slow output drivers can reduce the delay before all outputs are valid, without unduly increasing the adverse effects of power supply bounce. This is especially true when only a small number of output drivers need reduced di/dt limiting. The slew rates of the various output drivers can be adjusted to optimize output speed with supply bounce minimization. 
     While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.