Abstract:
In a demodulator circuit including a multi-level comparator, the demodulator circuit obtaining output data through comparison, made in a four-level comparator and a NRZ comparator, of a signal obtained by subjecting a received signal to a process of detection and predetermined threshold levels, comprises a level detector circuit for detecting the level of the received signal transmitted through the process of detection and a control circuit for controlling relative magnitudes of the level detected in the level detector circuit of the signal transmitted through the process of detection and the predetermined threshold levels for the four-level comparator and the NRZ comparator, whereby stabilized output data conforming to changes in the level of the detected output are made obtainable.

Description:
BACKGROUND OF THE INVENTION 
     The invention, in a demodulator circuit such as a pager, relates to a control circuit of threshold levels for a multi-level comparator in the demodulator circuit for detecting a multi-level signal with the use of the comparator. 
     In a demodulator circuit such as a pager, a multi-level comparator is used for receiving and demodulating a multi-level signal and it is practiced therein to compare the signal transmitted through the process of detection and predetermined threshold levels to obtain the desired signal. 
     FIG.  1  and FIG. 2 are circuit diagrams explanatory of related art examples. In the circuit shown in FIG. 1, a current output of a detector is input to two comparators  1  and  2  through a low-pass filter (LPF) to be compared therein with their respective different threshold levels and, thereby, output data corresponding to the multivalued data is obtained. Further, in the above described circuit, it is adapted such that the average voltage of the detected output is detected in an average voltage detector circuit  4  and the same is fed back to a comparator  5  as its threshold level and, thereby, the operating point of the detected output is shifted. 
     In the circuit shown in FIG. 2, it is adapted such that a detector output is input to two comparators  11  and  12  through a low-pass filter (LPF) to be compared with their respective different threshold levels and, thereby, output data corresponding to the multivalued data is obtained. In this circuit, the average voltage of the detected output is detected in an average voltage detector circuit  13  and, with the use of it, the threshold levels for the comparators  11  and  12  are shifted. 
     However, there have been problems with such circuits that the signal level is shifted by a deviation in the intermediate frequency and thereby lowering of the sensitivity is incurred, or that the threshold levels for the multi-level comparator become unable to follow changes in the level of the detected output and therefore lowering of the sensitivity is incurred when there arise fluctuations in the devices, changes in the temperature, or changes in the input level. 
     Further, when identical data or biased data are continuously included in the received data, the average value of the level of the detected output changes and an offset is produced between the threshold levels for the comparators and the operating point of the level of the detected output, and hence problems of lowering in the sensitivity or inability of signal reception arise. Still further, in the case of intermittent signal reception, to decrease the time constant in obtaining the average voltage at a rise of the received signal (quick charging), then, by the setting to shorten the rise period, an error voltage is left according to the timing of the quick charging. A problem then arises that the duty cycle of the output data changes at each instant intermittent signal reception is made. 
     OBJECT AND SUMMARY OF THE INVENTION 
     An object of the invention is to allow a multi-level comparator to stably operate in conformity with changes in the level of the input signal. Accordingly, in a demodulator circuit for obtaining output data through comparison, made in a comparator, of a signal obtained by subjecting a received signal to a process of detection in a detector circuit and predetermined threshold levels, there is provided a control circuit of threshold levels for a multi-level comparator in the demodulator circuit which comprises a level detector circuit for detecting the level of the received signal transmitted through the process of detection and a control circuit for controlling relative magnitudes of the level detected in the level detector circuit of the signal transmitted through the process of detection and the predetermined threshold levels for the multi-level comparator. 
     Since, in the invention, the level of a signal transmitted through a process of detection is detected in the level detector circuit and the detected level of the signal transmitted through the process of detection and the predetermined threshold levels for the multi-level comparator are controlled for their relative magnitudes in the control circuit, it is made possible, even if the signal level is changed, to set the predetermined threshold levels at fixed ratios to the changed signal level. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram explanatory of a comparator of a related art (first example); 
     FIG. 2 is a circuit diagram explanatory of a comparator of a related art (second example); 
     FIG. 3 is a block diagram explanatory of a first embodiment of the demodulator circuit of the invention; 
     FIG. 4 is a block diagram explanatory of a threshold level setting circuit as a second embodiment of the invention; 
     FIG. 5A and 5B is a circuit diagram showing an example of a detector circuit; 
     FIG. 6 is a drawing explanatory of functions of a threshold level setting circuit; 
     FIG. 7 is a drawing explanatory of variations in the NRZ threshold voltage; 
     FIG. 8 is a drawing explanatory of error voltage occurring in quick charging; 
     FIG. 9 is a drawing explanatory of deviations in the duty cycle; 
     FIG. 10 is a graph showing detected output voltages against IF input frequencies; and 
     FIG. 11 is a block diagram explanatory of a third embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of a control circuit of threshold levels for a multi-level comparator in a demodulator circuit according to the invention will be described with reference to the accompanying drawings. FIG. 3 is a block diagram explanatory of a first embodiment. The first embodiment is that establishes predetermined threshold levels for a four-level comparator  28  and an NRZ (non-return-to-zero) comparator  29 , for example, used in a demodulator circuit  21  such as a pager. 
     The demodulator circuit  21  is formed of an antenna  22 , an RF amplifier  23 , a BPF (band-pass filter)  24 , an LIM (limiter)  25 , a DET (detector circuit)  26 , an LPF (low-pass filter)  27 , a four-level comparator  28 , an NRZ comparator  29 , a local oscillator  30 , a threshold level setting circuit  31 , and a timing circuit  32 . 
     The threshold level setting circuit  31  characteristic of the present embodiment is operated by the timing circuit  32  formed with a microcomputer (not shown) and establishes threshold levels for the four-level comparator  28  and the NRZ comparator  29  and also supplies the threshold level for the NRZ comparator  29  to the local oscillator  30 , namely, delivers a signal for feedback control of the intermediate frequency, or for AFC (Auto Frequency Control). 
     The threshold level setting circuit  31  is formed, as shown in FIG. 4, of a MAX level detector circuit  31   a,  a MIN level detector circuit  31   b,  and resistors R 1 -R 4 . The MAX level detector circuit  31   a  detects the maximum value of the LPF output and the MIN level detector circuit  31   b  detects the minimum value of the LPF output. According to the output voltages of the MAX level detector circuit  31   a  and the MIN level detector circuit  31   b  and by means of voltage division by the resistors R 1 -R 4 , a threshold level {circle around (1)} for the four-level comparator is output from the terminal T 1 , the threshold level for the NRZ comparator and the voltage for the AFC are output from the terminal T 2 , and another threshold level {circle around ( 2 )} for the four-level comparator is output from the terminal T 3 . 
     By using such threshold level setting circuit  31 , it becomes possible to establish each of the threshold levels at fixed ratios to the signal level of the LPF output even if the signal level is changed. 
     Circuit diagrams showing an example of the detector circuits are given in FIG. 5, in which (a) shows an example of the MAX level detector circuit and (b) shows an example of the MIN level detector circuit. The MAX level detector circuit  31   a  shown in FIG.  5 ( a ) is an example designed after considering operations in a receiver for a pager or the like (power voltage is 1.5 V, for example), in which the input of the detected output is DC-shifted by the transistor Q 1  and the maximum voltage is held by the capacitor C 1  through switching operations of the diode D 1 . At this time, while the charging time constant of the capacitor C 1  is determined by the impedance of the diode D 1 , the impedance is set high (for example, a resistor is connected in series) to improve the antinoise characteristic. 
     The voltage charged on the capacitor C 1  is output through the buffer amplifier A 1 . The resistor R and the switch S are inserted for resetting the circuit, i.e., for discharging the charges on the capacitor C 1 , at a discharging time constant of CR. The discharging occurs in response to a signal from the timing circuit  32  shown in FIG.  3 . 
     In the MIN level detector circuit  31   b  shown in FIG.  5 ( b ), the minimum value of the input of the detected output is charged on the capacitor C 2  and an input higher than that, if any, is prevented from being charged by the diode D 2 . In this circuit, the voltage charged on the capacitor C 2  amounts to MIN voltage +1 VF. Therefore, 1 VF is deducted from it by the transistor Q 2 . Resetting of the circuit by means of the resistor R and the switch S is carried out in response to a signal from the timing circuit  32  shown in FIG.  3 . 
     Detection of the maximum value can be achieved, as shown in FIG. 6, by inputting the detected output to the MAX level detector circuit  31   a  and the MIN level detector circuit  31   b  (refer to FIG. 5) and, by means of the resistors R 1 -R 4  shown in FIG. 4, the threshold levels A-C at fixed ratios to the maximum value can be obtained. Accordingly, even if the level of the detected signal is changed, the threshold levels change proportionally to the changed level, and hence output data corresponding to the changed level can be obtained from the comparators. 
     In such a case as shown in FIG. 7 where the detected output is biased to one side of the signal level (to “1” in the case shown), when the NRZ threshold level was set through detection of average voltage (in the related art example), there were variations produced in the NRZ threshold level as shown in (a) affected by the biased detected output. However, according to the NRZ threshold level setting in the present embodiment, a constant NRZ threshold level can be obtained as shown in (b) unaffected by the bias of the detected output. 
     Further, a fluctuation d of the average voltage as shown in FIG. 8 does not occur in the present embodiment at the time of quick charging (operation at a short time constant in order to start the demodulator circuit quickly), and a constant threshold level α can be maintained with respect to the detected output as shown in FIG. 9, and accordingly, any deviation in the duty cycle (refer to the upper graph of the comparator output) due to occurrence of an error as indicated by the threshold level β is not produced. Hence, it becomes possible to obtain a constant duty cycle (refer to the lower graph of the comparator output). 
     Further, in the present embodiment, as shown in FIG. 3, the threshold level for the NRZ comparator  29  obtained in the threshold level setting circuit  31  is supplied to the local oscillator  30  to perform AFC. The AFC is carried out by making use of the fact that a deviation of the IF input frequency causes a deviation of the operating point of the detected output according to the relationship between the input frequency (IF) and the detected output voltage as shown in FIG. 10, i.e., the S-curve characteristic. Thus, feedback controlling to cope with deviations of the input frequency (IF) has become possible and, hence, it has been made possible to suppress shifts of the signal level and obtain the comparator output in accordance with the stabilized detected signal and threshold levels. 
     Although, in the above described first embodiment, an example was shown in FIG. 3 in which each of the threshold levels for the four-level comparator  28  and the NRZ comparator  29  were calculated from the detected output by the threshold level setting circuit  31 , each of the threshold levels may be fixed and the relative magnitudes of the threshold levels and the level of the detected output may be adjusted by applying feedback control to the detected output. 
     An example in which feedback control is applied to the detected output is shown as a third embodiment in the block diagram of FIG.  11 . The third embodiment is similar to the first embodiment in that it comprises an antenna  22 , an RF amplifier  23 , a BPF (band-pass filter)  24 , an LIM (limiter)  25 , a DET (detector circuit)  26 , an LPF (low-pass filter)  27 , a four-level comparator  28 , an NRZ comparator  29 , and a local oscillator  30 , but differs from the first embodiment in that there is provided a level detector circuit  31 ′ for applying feedback control to the DET  26 . 
     The level detector circuit  31 ′ is similar to the threshold level setting circuit  31  comprising the MAX level detector circuit  31   a  and the MIN level detector circuit  31   b  shown in FIG.  4 . The level detector circuit  31 ′ gives a DC offset and the gain of the detected output to the DET  26  to thereby apply feedback control to the detected output. The DC offset corresponds to the AFC in the first embodiment and the gain of the detected output corresponds to the threshold levels for the four-level comparator  28  in the first embodiment (refer to FIG.  3 ). 
     In the circuit configuration of the third embodiment, the detected output is controlled so that each of the threshold levels are kept constant with respect to the level of the detected output and thereby it is made possible to obtain stabilized output data from the four-level comparator  28  and the NRZ comparator  29  as with the first embodiment. 
     While the four-level comparator  28  was used in each of the above described embodiments, the present invention is not limited to it but equally applicable to cases where another multi-level comparator is used. 
     According to the control circuit of the threshold levels for a multi-level comparator in the demodulator circuit of the invention, as described above, such effects can be obtained as mentioned below. That is, since the relative magnitudes of the level of the signal transmitted through a process of detection and the predetermined threshold levels for the multi-level comparator can be controlled, output data with stabilized sensitivity can be obtained even if there occur fluctuations in the circuit and parts, changes in temperature, or changes in the input signal level. 
     Further, stabilized demodulation can be achieved even if identical data are sent over continuously. Besides, fluctuations in the duty cycle of the output data can be suppressed and therefore a stabilized output can be obtained even right after quick charging. Thus, it has been made possible to provide a highly reliable demodulator circuit.