Abstract:
The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims under 35 U.S.C. §119(a) the benefit of Taiwanese Application No. 103145895, filed Dec. 27, 2014 the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to package structures and fabricating methods thereof, and more particularly, to a package structure having embedded electronic components and a method of fabricating the same. 
     2. Description of Related Art 
     With the advancement in semiconductor packaging technology, various types of packages of the semiconductor device have been developed. A chip scale package (CSP) having the package size as small as or slightly larger than the chip size, is developed in order for meeting the demand of miniaturization. 
     Referring to  FIGS. 1A-1F , a method of fabricating a conventional semiconductor package  1  is shown. 
     As shown in  FIG. 1A , a first carrier  10   a  having a first adhesive layer  100   a  is provided, and at least one semiconductor element  11  is disposed on the first adhesive layer  100   a , then an encapsulating layer  12  is formed to encapsulate the semiconductor element  11 . The semiconductor element  11  has an active surface  11   a  bonded with the first adhesive layer  100   a  and an opposing none-active surface  11   b  having a plurality of electrode pads  110  thereon. 
     As shown in  FIG. 1B , a polishing method is employed to remove a portion of the encapsulating layer  12 , allowing the none-active surface  11   b  of the semiconductor element  11  to be exposed from the second surface  12   b  of the encapsulating layer  12 . Subsequently, the first carrier  10   a  and the first adhesive layer  100   a  are removed, and a second carrier  10   b  having a second adhesive layer  100   b  is attached on the second surface  12   b  of the encapsulating layer  12 . 
     As shown in  FIG. 1C , a first redistribution layer (RDL)  13  is formed on the first surface  12   a  of the encapsulating layer  12  and the active surface  11   a  of the semiconductor element  11 , and the first redistribution layer  13  is electrically connected with the electrode pads  110  of the semiconductor element  11 . 
     As shown in  FIG. 1D , a third carrier  10   c  having a third adhesive layer  100   c  is disposed on the first redistribution layer  13 , followed by removing the second carrier  10   b  and the second adhesive layer  100   b . After that, a plurality of vias  121  penetrating the encapsulating layer  12  are formed by laser to expose the first redistribution layer  13 . 
     As shown in  FIG. 1E , a second redistribution layer  14  is formed on the second surface  12   b  of the encapsulating layer  12  and in the vias  121 , and is electrically connected with the first redistribution layer  13 . 
     As shown in  FIG. 1F , the third adhesive layer  100   c  and the third carrier  10   c  are removed, followed by performing a singulation process to form a plurality of conductive elements  15  such as solder balls on the first redistribution layer  13 , such that the conductive elements  15  electrically connect the first redistribution layer  13  with the second redistribution layer  14 . 
     However, according to the method of fabricating the semiconductor package  1 , the vias  121  formed by laser is not only slow (especially when the number of vias is large) but also time consuming, and the residuals (such as the remaining materials of the encapsulating layer  12 ) left during the process of forming the vias  121  may easily accumulate at the bottom of the vias  121 . Therefore, a cleaning process must be performed to clean the interior of the vias  121  before the conductive materials could be filled in the vias  121  to form the second redistribution layer  14 , thereby overcomplicating the steps involved in fabrication. 
     Second, laser drilling to form openings may cause unevenness of the walls of the vias  121 , leading to poor attachment of the conductive materials to the walls of the vias  121 , causing peeling, and ultimately resulting in poor reliability for the semiconductor package  1 . 
     Further, the laser drilling process is performed from the second surface  12   b  of the encapsulating layer  12 , but since the encapsulating layer  12  is opaque, the laser equipment could not detect the first redistribution layer  13  under the encapsulating layer  12 , and thus requires a specialized process and equipment for alignment, thereby further increasing the complexity and cost in fabrication. 
     Besides, the laser beam utilized in the laser drilling process would result in a problem of heat affect zone; that is, when the vias  121  are at proximity of the semiconductor element  11 , the high temperature heat would damage the semiconductor element  11 , and thus the vias  121  must be kept with a certain distance from the semiconductor element  11 . As such, the semiconductor package  1  could not be further miniaturized, and is difficult to meet the low-profile requirement. 
     Meanwhile, the number of steps (at least 3) increases for bonding and removing the carrier (i.e. from the first to the third carrier  10   a - 10   c ) during the fabricating process of the semiconductor package  1 , thereby overcomplicating the fabricating process, which is time consuming and the fabricating cost is also increased due to more materials required for both the carriers and the adhesive layers. 
     Thus, there is an urgent need for solving the problems of the prior art. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing drawbacks, the present invention provides a method of fabricating a package structure, comprising: providing a first carrier having a metal layer; forming a patterned dielectric layer on the metal layer of the first carrier, and forming a plurality of openings for exposing the metal layer in the patterned dielectric layer; forming a plurality of conductive pillars having opposing first and second ends, wherein each of the conductive pillars is electrically connected with the metal layer via the first end thereof, and the second end of each of the conductive pillars protrudes from a surface of the dielectric layer; disposing at least one first electronic component on the dielectric layer; forming an encapsulating layer on the dielectric layer, for encapsulating the conductive pillars, the first electronic component and the dielectric layer; removing a portion of the encapsulating layer, for exposing the second end of each of the conductive pillars; and removing the first carrier. 
     The present invention further provides a package structure, comprising: a dielectric layer; an encapsulating layer formed on the dielectric layer, allowing the dielectric layer and the encapsulating layer to form an encapsulant body having opposing first and second surfaces, wherein the first surface is an outer surface of the dielectric layer, while the second surface is an outer surface of the encapsulating layer; at least one first electronic component disposed on the dielectric layer and embedded in the encapsulating layer; and a plurality of conductive pillars which are vertically embedded in the encapsulating layer and the dielectric layer, each of the conductive pillars having a first end being exposed from the first surface and an opposing second end being exposed from the second surface. 
     In summary, the package structure according to the present invention and the method of fabricating the same involve forming conductive pillars in the dielectric layer in advance of forming an encapsulating layer As the package structure and the fabrication method of the present invention are without the need of forming openings, not only the number of steps involved in the fabricating process is reduced but also the fabricating process is time-saving and cost-effective, with increased reliability of the package structure and reduced package size as desired. Besides, without the need to form openings, the number of steps for bonding/removing carrier is reduced, and additional laser process is also not required, thereby preventing the occurrence of heat affect area. Furthermore, it is not required to have laser alignment equipment, and in addition, the present invention provides a solution to prevent the problem of peeling of the conductive pillars from occurrence, such that the fabricating process is made simplified with reduced cost. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1F  are cross-sectional views showing a method of fabricating a conventional semiconductor package; 
         FIGS. 2A-2I  are cross-sectional views showing a method of fabricating a package structure according to the present invention; wherein  FIG. 2D ′ is another aspect of  FIG. 2D . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention is described in the following with specific embodiments, so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention. 
     It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms, such as “first”, “second”, “surface”, and etc., are merely for illustrative purpose and should not be construed to limit the scope of the present invention. 
       FIGS. 2A-2G  are cross-sectional views showing a method of fabricating a package structure  2  according to the present invention. 
     As shown in  FIG. 2A , a first carrier  20   a  is provided. The first carrier  20   a  includes a first board  200   a , a first releasing layer  201   a  and a first adhesive layer  202   a . The first board  200   a  is made of, but not limited to, a semiconductor material, dielectric material, ceramic material, glass or metal material. 
     The first releasing layer  201   a  can be a releasing film. The first adhesive layer  202   a  can be made of an adhesive material. The first releasing layer  201   a  and the first adhesive layer  202   a  can be respectively formed on the first board  200   a  in a sequential order via a coating or an attachment method. 
     A metal layer  21  is formed on the first adhesive layer  202   a  of the first carrier  20   a . The metal layer  21  may be made of copper and formed by a lamination method, which will serve as a conductive pathway for the latter electroplating process. 
     After that, a patterned dielectric layer  22  is formed on the metal layer  21 . The dielectric layer  22  has a plurality of openings  221  for exposing the metal layer  21 . The patterned dielectric layer  22  is formed by an exposure and development method, and the dielectric layer  22  is made of photosensitive material such as polybenzoxazole (PBO). 
     As shown in  FIG. 2B , a plurality of conductive pillars  23  are formed in the plurality of openings  221  of the metal layer  21 , and each of the conductive pillars  23  has a first end  231  and an opposing second end  232 . Each of the conductive pillars  23  can be formed on the patterned dielectric layer  22  by an electroplating plating method through forming a patterned resist layer (not shown) and a seed layer (not shown). 
     In an embodiment, the first end  231  of each of the conductive pillars  23  is electrically connected with the metal layer  21 , and the second end  232  of each of the conductive pillars  23  protrudes from a surface of dielectric layer  22 ; that is, each of the conductive pillars  23  is vertically mounted on the metal layer  21 . 
     As shown in  FIG. 2C , at least one electronic component  24  is disposed on the dielectric layer  22 . The electronic component  24  has an active surface  24   a  and an opposing non-active surface  24   b . The active surface  24   a  is coupled with the dielectric layer  22  and has a plurality of electrode pads  240  thereon. 
     Subsequently, an encapsulating layer  25  is formed on the dielectric layer  22 , that covers each of the conductive pillars  23 , the electronic component  24  and the dielectric layer  22 . The encapsulating layer  25  is made of an encapsulating material, and is formed selectively by using liquid compound, injection, lamination or compression molding. 
     Further, the encapsulating layer  25  covers the non-active surface  24   b  of the electronic component  24 , and covers the second end  232  of each of the conductive pillars  23 . 
     As shown in  FIG. 2D , a chemical mechanical polishing (CMP) method for instance is employed to remove a portion of the encapsulating layer  25 , until the second end  232  of each of the conductive pillars  23  is exposed therefrom. In an embodiment, the non-active surface  24   b  of the electronic component  24  is still covered by the encapsulating layer  25  thereon. 
     In an embodiment, referring to  FIG. 2D ′, a portion of the encapsulating layer  25  can be removed by a polishing method, until both the second end  232  of each of the conductive pillars  23  and the non-active surface  24   b  of the electronic component  24  are exposed at the same time. 
     Proceeding with  FIG. 2D , a second carrier  20   b  is formed on the encapsulating layer  25  and bonded with the second end  232  of each of the conductive pillars  23 , then the first carrier  20   a  is removed, as shown in  FIG. 2E . 
     In an embodiment, the second carrier  20   b  comprises a second board  200   b , a second releasing layer  201   b  and a second adhesive layer  202   b . The second board  200   b , second releasing layer  201   b  and second adhesive layer  202   b  are the same as the previously described first board  200   a , first releasing layer  201   a  and first adhesive layer  202   a , therefore will not be described herein. 
     As shown in  FIG. 2F , a redistribution layer  26  is formed on the dielectric layer  22 . In an embodiment, the metal layer  21  is firstly formed, after that, a plurality of conductive vias  222  are formed in the dielectric layer  22  via an exposure and development process. Subsequently, a redistribution layer  26  is formed on the plurality of conductive vias  222  and the dielectric layer  22  by an electroplating process, as well as a solder mask layer  27  on the dielectric layer  22 . 
     In an embodiment, the method to form the redistribution layer  26  by which the metal layer  21  could be left on without being removed is achieved by forming a partnered resist layer (not shown) on the metal layer  21 , followed by etching the metal layer  21 . Then, a solder mask layer  27  is formed on the dielectric layer  2 . 
     The solder mask layer  27  is formed with a plurality of openings  271  for exposing the redistribution layer  26 , allowing a plurality of conductive elements  28  such as solder balls to be mounted therein. The redistribution layer  26  is electrically connected with the first end  231  of each of the conductive pillars  23  and the electrode pads  240  of the electronic component  24 . 
     As shown in  FIG. 2G , the second carrier  20   b  is removed, followed by performing a singulation process so as to obtain the package structure  2  of the present invention. 
     According to the fabricating method of the present invention, the conductive pillars  23  are formed in the openings  221  of the dielectric layer  22 , followed by forming the encapsulating layer  25 , such that the conductive pillars  23  penetrate both the top and bottom surfaces of the dielectric layer  22  and the encapsulating layer  25 . Therefore, the present invention requires no need of using a laser method to form vias. Processes such as alignment for laser drilling, cleaning vias and forming electroplating material in the vias in the prior art can be all omitted. Accordingly, the method of the present invention not only reduces the number of steps and cost involved in the fabrication, the problem of peeling of conductive pillars as a result of uneven surface of the vias wall is prevented, thereby desirably increasing the reliability of the package structure  2 . 
     Further, since no laser drilling process is performed, there will be no Heat Affect Zone, thereby preventing the electronic component  24  from being damaged by the heat generated during laser drilling. Besides, the positions of the conductive pillars  23  can be designed according to practical uses, allowing the distance between the conductive pillars  23  and the electronic component  24  be further reduced, such that the package structure  2  can be made smaller, thereby meeting the low-profile requirement for the products. 
     Further, as the process of forming openings is omitted, the process of bonding/removing carrier (i.e. the first and second carriers  20   a ,  20   b ) only requires to be repeated twice. As compared to the prior art, the present invention is capable of effectively reducing the number of steps for bonding/removing the carrier, and thereby simplifying the fabricating process and reducing the fabricating cost. 
     A package structure  2  according to the present invention has a dielectric layer  22 , an encapsulating layer  25 , a plurality of conductive pillars  23 , at least one electronic component  24  and a redistribution layer  26 . 
     The encapsulating layer  25  is formed on the dielectric layer  22 , and the dielectric layer  22  and the encapsulating layer  25  forms an encapsulant body  30  having a first surface  301  and an opposing second surface  302 , wherein the first surface  301  is the outer surface of the dielectric layer  22 , while the second surface  302  is the outer surface of the encapsulating layer  25 . 
     The conductive pillars  23  are vertically embedded in the encapsulating layer  25  and the dielectric layer  22 . Each of the conductive pillars  23  has a first end  231  being exposed from the first surface  301  and an opposing second end  232  being exposed from the second surface  302 . In other words, the first end  231  and the second end  232  penetrate the outer side surfaces of the dielectric layer  22  and the encapsulating layer  25 , respectively. 
     The electronic component  24  is disposed on the dielectric layer  22  and embedded in the encapsulating layer  25 . The electronic component  24  has an active surface  24   a  and an opposing non-active surface  24   b . The active surface  24   a  is coupled with the dielectric layer  22 , and has a plurality of electrode pads  240  thereon. 
     In an embodiment, the first end  231  of each of the conductive pillars  23  is flush with the first surface  301  and the second end  232  of each of the conductive pillars  23  is flush with the second surface  302 . 
     The dielectric layer  22  has conductive vias  222 . The redistribution layer  26  is formed on the first surface  301  of the encapsulant body  30  and in the conductive vias  222 , for electrically connecting with the first end  231  of each of the conductive pillars  23  and the electrode pads  240  on the active surface  24   a  of the electronic component  24 . 
     In an embodiment, the package structure  2  further has a solder mask layer  27  formed on the first surface  301  of the encapsulant body  30  and having a plurality of openings  271  exposing the redistribution layer  26 , for enabling a plurality of conductive elements  28  such as solder balls to be mounted thereon. The conductive elements  28  are electrically connected with the corresponding conductive pillars  23  and the electronic component  24  via the redistribution layer  26 . 
     In an embodiment, the non-active surface  24   b  of the electronic component  24  is still covered by the encapsulating layer  25  without exposing the second surface  302 . 
     In another embodiment, the non-active surface  24   b  of the electronic component  24  is exposed from the second surface  302 , so as to form a package structure of another aspect. 
     In an embodiment, following  FIG. 2G , as shown in  FIG. 2H , after the package structure  2  of the present invention is obtained, a redistribution layer (RDL)  31  is formed on the second surface  302  of the encapsulant body  30 , and the redistribution layer  31  is electrically connected with the second end  232  of each of the conductive pillars  23 . After that, an electronic component  32  is stacked on the second surface  302  of the encapsulant body  30  and electrically connected with the redistribution layer  31  via conductive elements  33  such as solder bumps, copper bumps and so on. The electronic component  32  can be an encapsulant body, a chip or a substrate, but is not limited thereto. 
     In another embodiment, following  FIG. 2G , as shown in  FIG. 2I , after the package structure  2  of the present invention is obtained, an electronic component  32  can be directly stacked on the second surface  302  of the encapsulant body  30  and electrically connected with the second end  232  of each of the conductive pillars  23  via conductive elements  33  such as solder bumps, copper bumps and so on. 
     In summary, the package structure according to the present invention and the method of fabricating the same, involves forming conductive pillars in the dielectric layer in advance of forming an encapsulating layer. Therefore, it eliminates the need of forming openings such that not only the number of steps involved in the fabricating process is reduced but also the fabricating process is time-saving and cost-effective, with increased reliability of the package structure and reduced package size as desired. 
     Besides, without employing procedures to form openings, the number of steps for bonding/removing carrier is reduced, and additional laser process is also not required, thereby preventing the occurrence of heat affect area, such that it is not required to have laser alignment equipment. Furthermore, the present invention provides a solution to prevent the problem of peeling of the conductive pillars from occurrence, such that the fabricating process is made simplified with reduced cost. 
     The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.