Abstract:
An assembly for mitigating at least one of an electrostatic discharge and electromagnetic interference is provided. The assembly includes (a) first and second spaced apart electrical conductors  108  and  116  and (b) a mitigation module  300  electrically coupled to the first and second spaced apart electrical conductors to control a magnitude of an electrostatic discharge and/or electromagnetic interference in the first and second electrical conductors  108  and  116 . One or more of the following statements is true: (i) the mitigation module  300  comprises a ferrite material  304 ; (ii) the mitigation module  300  comprises a lossy dielectric material  308 ; and (iii) an equivalent electrical circuit for at least part of the mitigation module  300  comprises at least a first circuit segment  512  comprising a first inductor and a first capacitor electrically connected in parallel and a second capacitor  504  electrically connected in series with the first circuit segment  512 . The first and second electrical conductors can be, for example, a ground plane of a printed circuit board  108  and a wall of the enclosure or chassis  116.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to modules for protecting electronic devices from electromagnetic energy and specifically to a module for protecting printed circuit boards (PCBs) from electrostatic discharge (ESD) and electromagnetic incompatibility.  
         BACKGROUND OF THE INVENTION  
         [0002]    Printed circuit boards (PCBs) housed within metal enclosures must comply with electrostatic discharge (ESD) and electromagnetic compatibility (EMC) requirements. To comply with these requirements, the PCBs must not malfunction in the presence of electrical discharges that are coupled onto the metal enclosures, and the PCBs must not emit excessive radiation outside of the metal enclosures.  
           [0003]    In an EMC compliance approach, the PCBs ground plane(s) are electrically connected to the enclosure&#39;s chassis, thereby reducing electric-field radiation. The interconnection of the ground plane with the chassis equalizes potential differences that may exist between the PCB and the enclosure&#39;s chassis. The interconnection is typically implemented as a series of tapped (conductive) metal standoffs spaced periodically throughout the chassis. The PCB is placed on top of the array of metal standoffs, and the alignment holes within the PCB are aligned with and receive the standoffs. The holes are copper plated and connected to the PCB&#39;s ground plane. Metal screws attach the ground plane to the standoffs.  
           [0004]    Although this approach reduces certain types of electric-field radiation, it compromises compliance with certain ESD/EMC requirements. The PCB&#39;s robustness against ESD discharges is compromised because the metal standoffs provide a low-impedance path. As shown in FIG. 1, the low-impedance path  100  passes through the low impedance standoffs  104 , the ground plane  108  of the PCB  112 , and the chassis  116 . Current from an electrostatic discharge to the chassis  116  can freely travel along the path  100 . The path enables excellent coupling of electrostatic discharge from the chassis  116  to the PCB  112 . This coupling allows ESD currents to flow from the chassis onto the PCB, possibly causing PCB malfunction. Also, this coupling allows PCB noise currents to be coupled onto the chassis, allowing radiation of magnetic fields into the surrounding environment. As shown in FIG. 2, the low impedance path  100  conducts the noise current generated by the EMI noise current source  200  to the chassis  116 , thereby causing EMI radiation  204  to be emitted from the chassis  116  into the surrounding environment. In practice, designers typically rely on trial and error approaches to determine where the periodically spaced metal standoffs can be electrically connected to the PCB&#39;s ground plane(s) without compromising protection against ESD discharges and mitigation against electromagnetic interference (EMI).  
           [0005]    In an ESD compliance approach, electrically insulating standoffs, characterized by extremely large impedances, are used to electrically isolate the PCB from the chassis. In this manner, any electrical discharges directly onto the chassis are unable to couple onto the PCB, and any noise currents generated by the PCB are unable to couple to the chassis. The use of such insulative standoffs can compromise EMC compliance. The standoffs will maximize potential differences between the PCB and the chassis and cause excessive radiation of electric fields as a result of the large potential differences.  
           [0006]    There is thus a need for a mitigation module that will provide concurrent compliance with both ESD and EMC requirements rather than compromising compliance with one set of requirements in lieu of ensuring compliance with another.  
         SUMMARY OF THE INVENTION  
         [0007]    These and other needs are addressed by the various embodiments and configurations of the present invention. The present invention provides a mitigation module that provides a medium amount of impedance between the ground plane and the chassis to mitigate EMI and ESD currents while also mitigating potential differences between the PCB and the chassis.  
           [0008]    In one embodiment, an assembly for mitigating the magnitude of an electrostatic discharge and/or electromagnetic interference signal is provided. The assembly includes:  
           [0009]    (a) first and second spaced apart electrical conductors and  
           [0010]    (b) a mitigation module electrically coupled to the first and second spaced apart electrical conductors to control the magnitude of any electrostatic discharge and/or electromagnetic interference in the first and second electrical conductors. One or more of the following statements is true: (i) the mitigation module comprises a ferrite material; (ii) the mitigation module comprises a lossy dielectric material; and (iii) an equivalent electrical circuit for at least part of the mitigation module comprises at least a first circuit segment comprising a first inductor and a first capacitor electrically connected in parallel and a second capacitor electrically connected in series with the first circuit segment. The first and second electrical conductors can be, for example, a ground plane of a printed circuit board and a wall of the enclosure or chassis. The module can provide engineers with the capability of connecting every metal standoff to the PCB&#39;s ground plane(s) while simultaneously achieving robust protection against ESD and realizing electromagnetic compatibility.  
           [0011]    The module can be configured in many different ways. By way of illustration, the module can be configured as a through-hole device, a PCB surface mountable device, and/or as all or part of the standoff itself. The surface mountable design is generally preferred because it can more readily be miniaturized (thereby conserving invaluable space on the PCB) and, compared to a through-hole device, require less labor and fewer steps (and therefore is cheaper) to mount on the PCB. The surface mountable design more readily lends itself to automated placement of the module on the PCB, which is often crowded with other electrical circuitry.  
           [0012]    By selecting appropriate materials for the ferrite and dielectric, the module can be tuned to satisfy a broad variety of design criteria. The module can be configured to provide neither a very high nor a very low impedance to the three types of ESD and EMI signals. The module effectively provides a medium impedance barrier to all three types of signals.  
           [0013]    The module is tunable or configurable to behave differently, depending on the application. For instance, in applications where EMI is of greater concern, the module can be designed to allow better EMC performance and less ESD performance. In applications where ESD is of greater concern, the module can be designed to allow better ESD performance and less EMC performance. The module can thus be designed to satisfy concurrently both EMC and ESD requirements.  
           [0014]    These and other advantages will be apparent from the disclosure of the invention(s) contained herein.  
           [0015]    The above-described embodiments and configurations are neither complete nor exhaustive. As will be appreciated, other embodiments of the invention are possible utilizing, alone or in combination, one or more of the features set forth above or described in detail below. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 shows a PCB mounting design according to the prior art;  
         [0017]    [0017]FIG. 2 is another view of the PCB mounting scheme of FIG. 1;  
         [0018]    [0018]FIG. 3 is a perspective view of a mitigation module according to a first embodiment of the present invention;  
         [0019]    [0019]FIG. 4 is a cross-section along line  4 - 4  of FIG. 3;  
         [0020]    [0020]FIG. 5 is an equivalent electrical circuit for the mitigation module of FIG. 3;  
         [0021]    [0021]FIG. 6 is a PCB mounting design according to the first embodiment;  
         [0022]    [0022]FIG. 7 is another view of the PCB mounting design of FIG. 6;  
         [0023]    [0023]FIG. 8 is a plot of impedance (vertical axis) versus frequency (horizontal axis) for the mitigation module of FIG. 3;  
         [0024]    [0024]FIG. 9 is a plot of absorption loss (vertical axis) versus frequency for a 2 mm thick dielectric useful in the mitigation module of the present invention;  
         [0025]    [0025]FIG. 10 is a cross-sectional view of a second embodiment of a mitigation module according to the present invention;  
         [0026]    [0026]FIG. 11 is a side view of a PCB mounting design according to a third embodiment of the present invention;  
         [0027]    [0027]FIG. 12 is a cross-sectional view of a PCB mounting design according to a fourth embodiment of the present invention; and  
         [0028]    [0028]FIG. 13 is a cross-sectional view of a PCB mounting design according to a fifth embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0029]    [0029]FIGS. 3 and 4 depict a cylindrical through-hole mitigation module according to a first embodiment of the present invention. The mitigation module  300  comprises first and second (co-axially aligned) ferrite cores  304   a  and  b , first and second (co-axially aligned) dielectric materials  308   a  and  b  surrounding the peripheries of the first and second ferrite cores  304   a  and  b , respectively, first and second (co-axially aligned) outer conductive (e.g., metal) shells  312   a  and  b  surrounding the peripheries of the first and second dielectric materials  308   a  and  b , respectively, and a conductive (e.g., metal) annular spacer disk  316  positioned between the first and second sections  320   a  and  b  of the module. The first and second ferrite cores  304   a  and  b , first and second dielectric materials  308   a  and  b , first and second outer conductive shells  312   a  and  b , and conductive spacer disk  316  are, in one configuration, co-axially aligned along line  324 .  
         [0030]    The electrical behavior of the module  300  is depicted in FIG. 5. The first capacitor C 1    504  is defined by the first ferrite core  304   a , the first dielectric material  308   a  and the first outer conductive shell  312   a , and the second capacitor  508  by the second ferrite core  304   b , the second dielectric material  308   b , and the second outer conductive shell  312   b . The first parallel R-C 2 -L circuit  512  is the equivalent electrical circuit for the first ferrite core  304   a , and the second parallel R-C 2 -L circuit  516  is the equivalent electrical circuit for the second ferrite core  304   b . The connection  520  between the left and right hand circuits represents the conductive spacer disk  316 . The spacer disk  316  electrically connects only the first outer shell  312   a  to the second outer shell  312   b  to allow current to flow from the first section  320   a  to the second section  320   b  and vice versa and can be bonded to the first and second outer shells metallurgically or the spacer  316 , and the first and second outer shells can be fabricated as one (an integral) unit using existing capacitor manufacturing processes.  
         [0031]    While not wishing to be bound by any theory, the module  300  provides a medium impedance barrier for both ESD signals and EMI signals while mitigating potential differences between the PCB  112  and the chassis  116 . As will be appreciated, ESD signal frequencies typically fall between about 200 Hz and 30 MHZ while EMI frequencies fall between about 30 MHZ and 1,000 MHZ. To produce this behavior, the first and second capacitors  504  and  508  are each tuned to provide at least about 10,000 ohms of impedance at signal frequencies up to about 30 MHZ to attenuate ESD signals, and the first and second parallel R-C 2 -L circuits  512  and  516  are each tuned to provide between about 1,500 ohms and 10,000 ohms of impedance at signal frequencies between about 30 MHZ and 1,000 MHZ to attenuate EMI signals.  
         [0032]    The performance of the module  300  will now be described with reference to FIGS. 6 and 7. As can be seen from the Figures, the module  300  is placed on the PCB. The through-hole leads  324   a  and  b  (FIG. 3) are metallurgically attached to each end  328   a  and  b  of the inner cylindrical holes  332   a  and  b  of the first and second ferrite cores  332   a  and  b , respectively. The modules  300 , PCB ground plane  108 , integrated circuit  600 , standoffs  104 , and chassis  116  form a medium-impedance path  604 . For EMI noise currents, the current flow is depicted in FIG. 6. For ESD discharge currents, the current flow (which is in a direction opposite to the direction of flow of EMI noise currents) is depicted in FIG. 7. FIG. 4 depicts the segment  400  of the path  604  passing through the module  300 .  
         [0033]    To cause the path  604  to have the configuration shown in FIG. 4, the capacitance C E  is selected to be less than the capacitance C 1 . This prevents the current flowing along the path segment  400  from flowing directly from one of the ferrite cores to the other ferrite core and not passing through the dielectric materials and spacer ring. This can be done by selecting a suitable width of the gap  404  between the ferrite cores and/or dielectric material (not shown) in the gap  404 .  
         [0034]    The various module components are carefully selected to produce these design parameters.  
         [0035]    The material(s) used in first and second outer conductive shells  312   a  and  b  and the spacer ring  316  is/are selected to have relatively high conductivities (preferably of at least about  10  million siemens/meter) and therefore high conductivity. Preferably, the material is a conductive metal such as aluminum or copper.  
         [0036]    The ferrite core  304  can be formed from any suitable ferrite material. Preferably, the ferrite in the ferrite core  304  has a resistivity of no more than about 10,000 ohm-meters. Preferred ferrite materials are manganese-zinc-based ferrites, such as 3S1 and 3S4 manufactured by Phillips. Such conductive ferrites can perform two important functions. First, the first and second ferrite cores  304   a  and  b  serve as the inner conductor for the capacitors  504  and  508  (FIG. 5), respectively. Second, the first and second ferrite cores  304   a  and  b  provide a medium impedance barrier to the high-frequency EMI currents attempting to flow from the PCB  112  to the chassis  116 .  
         [0037]    The first and second dielectric materials  308   a  and  b  can be any dielectric material, however, lossy dielectric materials would be preferred, such as lossy ceramic (e.g., glass) dielectrics. Lossy dielectrics absorb a given percentage of the currents flowing through them by converting the absorbed energy into heat throughout the dielectric, thereby attenuating ESD and EMI signals. As will be appreciated, lossy dielectrics are dielectric materials characterized by a nonzero loss tangent. Particularly preferred lossy glass dielectrics comprise Corning&#39;s 0081™ and Owens-Illinois R-6™ glasses.  
         [0038]    [0038]FIG. 9 shows the absorption loss as a function of frequency using a 2 mm thick lossy dielectric. The lossy dielectric used to generate the test results is Corning&#39;s 0081 glass. For high frequencies up to 1 GHz, the lossy dielectric provides roughly an additional 7 to 8 db of suppression and the attenuation or absorption increases with lower frequencies. Thus, lossy dielectrics provide significant attenuation levels over a relatively wide frequency range.  
         [0039]    [0039]FIG. 8 shows the impedance performance of the module  300  of FIG. 4 as a function of frequency for four different geometries of the module. The first module geometry denoted by curve  800  was comprised of capacitor geometries yielding 0.5 pF for both capacitors and a ferrite geometry yielding a peak resonant impedance of 2450 ohms at 247MHz for the combination of both ferrite cylinders. These values reflect the expected geometries for the module. Maintaining the ferrite geometry, curves  804 ,  812  and  816  reflect the expected module impedances for capacitor geometries yielding 0.7 pF, 0.8 pF, and 0.9 pF, respectively, for both capacitors. FIG. 8 shows that impedance values of between about 1,000 ohms and 1,000,000 ohms over a wide frequency range (from 0 Hz or DC to 1,000 MHZ) can be realized using the various modules. Thus, for ESD signals (which typically have a frequency up to about 30 MHZ) the module provides a high impedance while for EMI signals (which typically comprise frequencies above about 30 MHZ the module provides a lower, but still significant, impedance.  
         [0040]    [0040]FIG. 10 shows a second embodiment of a module according to the present invention that is particularly useful as a surface mountable module design that can be used in a tape-and-reel installation technique. The module  1000  comprises co-axially aligned (continuous) ferrite core  1004 , dielectric material  1008 , first and second outer conductive shells  1012   a  and b, and insulative (annular) spacer ring  1016 . A washer-shaped air gap  1010  (or insulative material) exists that is coplanar with the insulative annular ring. This air gap physically separates the two dielectric materials of the two capacitors and provides a much smaller capacitance than that capacitance provided by the conductive shell-dielectric-ferrite structure. As will be appreciated, the air gap  1010  and ring  1016  can be placed by a washer-shaped insulative annular ring extending from the outer surface of the shells  1012   a  and  b  to the outer surface of the core  1004 . This design can be more manufacturable than an air gap and provide a high degree of mechanical stability to the overall structure. The path of the ESD/EMI currents through the module  1000  is shown by line  1020 . To provide this path, the upper and lower ends  1024  and  1028  ferrite core  1004  are each spaced from the corresponding upper and lower ends  1032  and  1036  of the conductive outer shell  1040 . Each of the capacitances C E  between the upper end of the conductive shell  1032  and the upper end  1024  of the ferrite core and between the lower end of the conductive shell  1028  and the lower end  1028  of the ferrite core are selected to be less than the capacitance C 1  between the outer conductive shell  1012   a,b  and ferrite core  1004  to cause the ESD/EMI currents to follow the path shown. The insulative ring  1016  preferably is an insulator having a resistivity that is at least about 100,000 billion ohm-meters.  
         [0041]    The module  1000  can be fabricated in separate parts joined together along joint line  1044  as shown in FIG. 10. Alternatively, the module  1000  can be fabricated as an integral unit in which case the ferrite core would be a single-piece design.  
         [0042]    The module  1000  can be placed onto the PCB in the desired location using tape-and-reel techniques. In this technique, the module  1000  is located on a tape that is spooled on a reel. A robotic unit using suction removes the module from the tape and places it on solder prelocated on the PCB. The board is then passed through an oven to metallurgically set the solder.  
         [0043]    In other configurations, the module is mounted on one or more of standoffs or is incorporated into the design of the standoff itself. Such configurations are depicted in FIGS.  11 - 13 .  
         [0044]    [0044]FIG. 11 depicts a PCB mounting design according to a third embodiment of the present invention. In the design, the PCB ground plane  108  is in contact with standoff  1100 , which in turn is in contact with the chassis  116 . The first and second sections  1104   a  and  1104   b  of the standoff are electrically conductive while the central section  1110  of the standoff is electrically insulating. The mitigation module  300  or  1100  is positioned adjacent to the central section  1108  and is in electrical contact with the first and second sections  1104   a  and  1104   b . This configuration of components produces the electromagnetic current path  1108  shown.  
         [0045]    [0045]FIG. 12 depicts a PCB mounting design according to a fourth embodiment of the present invention. In the design, the PCB ground plane  108  is in contact with standoff  1200 , which in turn is in contact with the chassis  116 . The first and second annular end sections  1204  and  1208  of the standoff are electrically insulative. The standoff  1200  further includes a cylindrical ferrite core  1212  (which has a resistivity not exceeding 10,000 ohm-meters), an annular-shaped dielectric material  1216  positioned around the periphery of the upper and lower sections of the ferrite core  1212 , and a cylindrical conductive outer shell  1220  and upper and lower sections of the dielectric materials  1206  positioned around the periphery of the upper and lower sections of the ferrite core  1212  and between the first and second annular sections  1204  and  1208 . An air gap  1210  separates the upper and lower sections of the dielectric and ferrite materials. Instead of an air gap, an insulative spacer can be used to fill the intervening space. The spacer preferably has a resistivity of at least about 100,000 billion ohms. The capacitances C E  between the ground plane  108  and the outer shell  1220  and between the chassis  116  and the outer shell  1220  are each less than the capacitance C 1 . The electromagnetic current path  1224  resulting from the component arrangement is depicted in the figure.  
         [0046]    [0046]FIG. 13 depicts a PCB mounting design according to a fifth embodiment of the present invention. In the design, the PCB ground plane  108  is in contact with standoff  1300 , which in turn is in contact with the chassis  116 . The standoff  1300  includes a continuous cylindrical ferrite core  1304 , a spaced-apart annular-shaped upper and lower sections of dielectric material  1308  positioned around the periphery of the ferrite core  1304 , first and second cylindrical conductive outer shells  1312  and  1316  positioned around the periphery of the ferrite core, and an annular electrically insulative spacer ring  1320  (which has a volume resistivity higher than the ferrite core  1304 ) positioned between the first and second outer shells  1312  and  1316  and washer-shaped air gap (or washer-shaped insulative material having a resistivity similar to the insulative spacer discussed in the previous paragraph)  1310  positioned between the upper and lower sections of the dielectric material to produce the electromagnetic current path  1324  shown. The capacitance C E  between the first and second outer shells  1312  and  1316  and the capacitances between the ground plane  108  and the first end  1324  of the ferrite core  1308  and between the chassis  116  and the second end  1328  of the ferrite core  1308  are each less than the capacitance C 1 . This design can provide a high degree of mechanical stability to the overall structure.  
         [0047]    A number of other variations and modifications of the invention can be used. It would be possible to provide for some features of the invention without providing others.  
         [0048]    For example in one alternative embodiment, the module  300 ,  1000 ,  1100 ,  1200  and  1300  has a geometry other than cylindrical. In one configuration, for example, the module has a polygonal (e.g., rectangular or cubic) geometry.  
         [0049]    In another embodiment, the composition(s) of the ferrite and/or dielectric materials in the first portion  320   a  of the module is different from the composition(s) of the corresponding ferrite and/or dielectric material in the second portion  320   b  (FIG. 4) of the module. In this configuration for example, the capacitances for the two capacitors  504  and  508  (FIG. 5) are different and/or the corresponding values for R, C 2 , and/or L in the circuit segments  512  and  516  are different.  
         [0050]    The present invention, in various embodiments, includes components, methods, processes, systems and/or apparatus substantially as depicted and described herein, including various embodiments, subcombinations, and subsets thereof. Those of skill in the art will understand how to make and use the present invention after understanding the present disclosure. The present invention, in various embodiments, includes providing devices and processes in the absence of items not depicted and/or described herein or in various embodiments hereof, including in the absence of such items as may have been used in previous devices or processes, e.g., for improving performance, achieving ease and/or reducing cost of implementation.  
         [0051]    The foregoing discussion of the invention has been presented for purposes of illustration and description. The foregoing is not intended to limit the invention to the form or forms disclosed herein. Although the description of the invention has included description of one or more embodiments and certain variations and modifications, other variations and modifications are within the scope of the invention, e.g., as may be within the skill and knowledge of those in the art, after understanding the present disclosure. It is intended to obtain rights which include alternative embodiments to the extent permitted, including alternate, interchangeable and/or equivalent structures, functions, ranges or steps to those claimed, whether or not such alternate, interchangeable and/or equivalent structures, functions, ranges or steps are disclosed herein, and without intending to publicly dedicate any patentable subject matter.