Abstract:
A high speed ratioless FET sense amplifier for sensing stored information in a semiconductor memory system. The amplifier is capable of sensing very small voltage signals provided by charges stored in a plurality of single FET/capacitor memory cells. The amplifier comprises a pair of cross-coupled FET devices coupled to a pair of bit/sense lines by clock signal responsive switching devices. The source electrodes of the cross-coupled FETs are each independently capacitively coupled to another clock signal and also to a source of low potential through a pair of clock driven source pull-down FETs. The amplifier uses minimal size devices and is process parameter independent.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to semiconductor memory systems and particularly to information sense amplifiers for single FET/capacitor memory cells. 
     2. Description of the Prior Art 
     U.S. Pat. No. 3,387,286 entitled &#34;Field Effect Transistor Memory&#34;, issued June 4, 1968, to R. H. Dennard and assigned to the present assignee, describes an array of semiconductor memory cells, each comprising only a single FET coupled to a storage capacitor. Because of the relatively lower cost of FET processing over bipolar processing and the inherent optimum density achievable using a single active device in a memory cell, the approach to designing high density semiconductor memory systems has, in recent years, emphasized the development of single FET/capacitor memory cell technology. 
     A typical sense amplifier and memory system configuration for such memory cells appears in U.S. Pat. No. 3,678,473 entitled &#34;Read-Write Circuit for Capacitive Memory Arrays&#34;, issued July 18, 1972, to S. E. Wahlstrom, which includes a ratioless cross-coupled sense latch coupled between common bit lines of a pair of single FET/capacitor memory arrays. A charged or uncharged memory capacitor is coupled to one bit line and a reference potential is coupled to the other bit line, the differential potential between the bit lines is sensed. In large memory systems where the parasitic capacitance of the bit/sense line is large compared with the storage capacitance, the sense signal is severely attenuated due to the charge redistribution between the small storage capacitance and the large bit/sense line capacitance. In practical FET devices any imbalances, such as differences in the threshold voltages of the cross-coupled devices, or differences in bit line capacitance, requires that a sense signal larger than the minimum achievable through cell design be provided to offset any mismatch. In addition, the speed at which the latch can be set is limited by the size of the bit/sense line capacitance which must be driven to high and low signal levels. The article, &#34;Sense Latch Circuit for Memory Cells&#34;, by A. Furman et al. IBM Technical Disclosure Bulletin, February 1974, pp. 2792-3, provides clock driven isolation devices between the latch sense nodes and the bit/sense lines to isolate the bit/sense line capacitance from the latch circuit at the time the latch is being set. 
     Additional improvements in sense amplifier design are taught in U.S. Pat. No. 3,764,906 entitled &#34;Stored Charge Detection by Charge Transfer&#34;, issued Oct. 9, 1973,  to L. G. Heller and assigned to the instant assignee, which teaches a charge transfer, or bucket brigade, sensing technique which is insensitive to device parameters and can effectively transfer the storage capacitor voltage directly to the sense node. This technique, although more sensitive to input voltages, is slower than the dynamic latch due to the time required to fully charge the large bit/sense line capacitance through an FET approaching cutoff while operating in the saturation region. Improvements in charge transfer sense amplifiers are found in U.S. Pat. No. 3,760,381, entitled &#34;Stored Charge Memory Detection Circuit&#34;, issued Sept. 18, 1973, to Y. L. Yao and assigned to the instant assignee, and in the article &#34;Differential Sense Amplifier&#34; by D. P. Spampinato, IBM Technical Disclosure Bulletin, November 1974, pp. 1797-8. 
     In summary, two different types of sense amplifiers have been previously proposed for use with single FET/capacitor memory cells. The dynamic cross-coupled latch, although faster, remains device parameter sensitive and therefore requires a larger input signal, while the charge transfer sense amplifier is more sensitive but slower. 
     Three additional prior art references are pertinent to certain aspects of the subject invention and, although they relate to diverse areas of the semiconductor art, are described below: 
     U.S. Pat. No. 3,549,912, entitled &#34;JK Flip-Flop&#34;, issued Dec. 22, 1970 to R. G. Lewis, describes a bipolar flip-flop circuit which uses a capacitively coupled clock signal combined with pulse steering diodes to disable the conductive one of a pair of cross-coupled transistors in order to allow the static state of the flip-flop to be more quickly changed. 
     The article, &#34;Sense Amplifier for IGFET Memory&#34;, by D. L. Critchlow, IBM Technical Disclosure Bulletin, November 1970, pp. 1720-2, shows a cross-coupled FET sense/latch circuit in which the source electrodes of the cross-coupled FETs are coupled to separate voltage nodes from which an output signal is derived. The nodes are initially unconditionally prebiased to the same DC potential. 
     U.S. Pat. No. 3,854,059, entitled &#34;Flip-Flop Circuit&#34;, issued Dec. 10, 1974, to K. Nomiya et al., shows an FET flip-flop in which cross-coupled devices, having isolated source electrodes, are initially precharged. The circuit also includes separate source pull-down devices for each of the cross-coupled FET devices. In operation the circuit is responsive to logical input signals selectively applied to the precharged source nodes prior to activation of the source pull-down devices. Regenerative operation is prevented by a feedback interrupting device conditioned to be conductive only during a precharge period. 
     SUMMARY OF THE INVENTION 
     The circuit of this invention provides a further improvement in sense amplifiers which overcomes the above problems through the use of a cross-coupled FET latch coupled to a pair of bit/sense lines by isolation gates. The source electrodes of the cross-coupled FETs are isolated from each other and are independently prebiased to a potential determined by the threshold of each FET. After the signal to be sensed is placed on the latch nodes and isolated, a high DC impedance means drives the precharged source nodes negatively at a constant rate. The initial differential input signal is increased by charge transfer amplification between a relatively small drain capacitance and a relatively large source capacitance to enable an extremely small input signal to be effectively amplified to the point that the cross-coupled FET devices may be used as a latch. The latch is set by connecting both source nodes to a reference potential. Once the latch is set the isolation gates are opened allowing one bit/sense line to discharge to the reference potential. 
     The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic circuit diagram of a portion of a memory system and includes a sense amplifier according to the principles of the present invention. 
     FIG. 2 is a timing diagram illustrating a typical pulse program sequence for operating the circuit of FIG. 1. 
     FIG. 3 is a schematic drawing illustrating the generation of clock pulse CP1 from clock pulses CP3 and CP4 and voltage sources VI and VN. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1 there is shown a schematic circuit diagram of a portion of an integrated circuit memory system which includes a preferred embodiment of the sense amplifier of the subject invention. Although only a single addressable memory cell and sense amplifier are shown, it will be understood by those skilled in the art that, in an actual system, there are normally provided two separate arrays of memory cells organized in rows and columns. In the example shown, columns of memory cells are associated with word accessing lines and rows of memory cells are associated with bit accessing lines, each row having a single sense amplifier. Although differential sensing between two arrays is preferred, the use of a single array having sense amplifiers placed along one edge may also be used, provided certain modifications are made. 
     Each memory array includes a plurality of charge storage cells comprising a gating FET T7 for selectively coupling a storage capacitor CS to a bit/sense line 10 in response to an address signal VW provided by a word decoder, not shown. VW also drives an additional number of memory cells, as indicated by reference numeral 12, associated with other bit positions. Each bit/sense line also has coupled to it an additional number of memory cells, designated 14, and 14&#39;, which are associated with different addressable word lines. Bit/sense line 10 has an inherent capacitance CB/S which is rather large when compared with storage capacitor CS. On the other side of the sense amplifier there is a second bit/sense line 16 which normally has the same number of memory cells associated with it as bit/sense line 10, as known in the art. Each bit/sense line also has associated with it one reference level providing means, or dummy memory cell, comprising, for example, device T12, responsive to dummy cell select signal DWL, and a capacitor CD. DWL also drives additional dummy cells, as indicated by reference numeral 13. During each sensing cycle the dummy cell associated with the bit/sense line on which a memory cell is not to be addressed is selected. Since only the memory cell on the left bit/sense line is illustrated, only the right dummy cell is shown. 
     Also associated with each bit/sense line are precharge devices T9 and T10 which are responsive to clock pulse CP2 and serve to charge each bit/sense line to an intermediate potential level VI when CP2 is true, positive in the illustrated case of n-channel MOSFET devices. Since it is preferable to store data charge levels at the highest available power supply level, restore devices T8 and T11 are provided to apply a high potential VH to the bit lines at clock pulse CP4 time. 
     The sense amplifier comprises a pair of bit line isolation devices T1 and T2 which are normally conditioned to be conductive in the linear region in response to clock pulse CP3. T1 and T2 serve to couple input signals to the sense amplifier and also to isolate the amplifier from the rather large bit/sense line capacitance CB/S as will be explained in more detail below. Within the sense amplifier and connected to isolation gates T1 and T2 are cross-coupled devices T3 and T4. The drain and gate electrodes of T3 and T4 are cross-coupled to provide a regenerative feedback circuit. 
     Associated with the drain electrodes of T3 and T4 are parasitic capacitances C5 and C6. The source electrodes of T3 and T4 are each independently coupled to a pair of pull-down devices T5 and T6, which are responsive to clock pulse CP1D. T5 and T6 serve to couple the source nodes of T3 and T4 to a low, or negative, potential VN when the latch is to be set. Capacitors C1 and C3 are also coupled to the source electrodes of T3 and T4 and are responsive to clock pulse CP1 which initiates the sense/amplification portion of the memory cycle. 
     Data may be read into and out of any of the memory cells by any of several techniques. As shown in FIG. 1 it is preferable to provide input/output signals I/O through bit/sense line 16. However both bit/sense lines could be used as well as coupling the I/O signal directly to the sense nodes C and D. 
     Referring now to FIGS. 1 and 2 the operation of the sense amplifier will be described. Three power supply potential levels are used: VH refers to the highest power supply potential available, normally VDD, VN refers to the lowest power supply potential, normally VSS, and VI to a potential intermediate VH and VN. VI may be selected to provide a bit/sense line potential equal or greater than the potential intended to be stored as a charge on a storage capacitor. For purposes of illustration it will be assumed that the state of the amplifier has been previously set such that bit/sense line 10 (voltage node A) is at VH-Vt, where Vt is the threshold voltage of T8, being previously charged through T8 by CP4, and that bit/sense line 16 (voltage node B) is at VN, having been discharged through devices T2, T4, and T6. Just prior to to, CP3 is at VH, CP1 at VI, CP2, CP4 and VW are at VN and CP1D is at VH. At to CP2 goes to VH, bit/sense line 10 starts discharging towards VI and bit/sense line 16 starts charging towards VI. CP1D remains at VH long enough to guarantee that voltage nodes E and F start charging from a potential below VI-Vt. At t1 time, CPID falls to VN turning off T5 and T6 allowing nodes E and F to charge up to within one threshold of the final voltage at nodes C and D, respectively. Nodes E and F will restore to different potential levels due to differences in their individual threshold voltages. Bit/sense lines 10 and 16 and nodes C and D will restore to VI, as CP2 and CP3 are at VH. At equilibrium, node E will restore to the potential at node D (VI) less the threshold voltage Vt3 of T3 and node F will restore to the voltage at node C(VI) less the threshold voltage Vt4 of T4. T3 and T4 will become non-conductive, as parasitic source capacitances will have been charged. At t2 CP2 returns to VN turning off T9 and T10 and word line potential VW (and also dummy word line potential DWL) rises from VN to VH to turn on T7 coupling the signal stored on storage capacitor CS onto bit/sense line 10. At the same time a reference potential equal to one-half the differential normally provided by a fully charged stored capacitor and a fully discharged storage capacitor is applied to bit/sense line 16 by dummy storage capacitor CD. 
     The amplifier is responsive to an input signal on node C(D) equal or greater than 0 and a change in potential on node D(C) equal to a negative sensitivity threshold, dependent upon various device mismatches, of -ΔV1, or a change in potential on node C(D) equal or greater than -2ΔV1 and a change in potential on node D(C) equal to -ΔV1. At t3, after data has been introduced to node C, or D, CP3 turns off T1 and T2, decoupling the large bit/sense line capacitance CB/S from the amplifier. At t4, CP4 turns on to restore both bit/sense lines toward VH through T8 and T11. Since VW is still at VH, a logical &#34;one&#34; or charged condition is unconditionally applied to the storage capacitor being read. The dummy cell is also restored. As CP4 rises (see FIG. 3) it causes CP1 to begin to fall toward VN. CP1 causes a known charge Q to be coupled at a constant rate through each of capacitors C1 and C3 to cause the potential on nodes E and F to drop as a function of the ratio of C1 to C2 and C3 to C4. Although the source potentials of T3 and T4 may be at different potential levels, due to differences in their threshold voltages, it is important that the change in gate drive, i.e. (VG-Vt-VS), where VG is the gate potential and VS is the source potential, is increased at a constant rate in order to provide proper operation of the circuit. Since T3 and T4 were previously non-conductive, a voltage drop (-ΔV) on nodes E and F will cause one of them to just turn on in the saturation region. T3 or T4 will act as a constant current limited device allowing the charge Q removed from nodes E and F to be accurately coupled from node C or D. One of the cross-coupled devices T3 or T4, with the highest gate drive will turn on, allowing either node C or D to be discharged by an amount which is a function of the ratios of the capacitances of the drain and source electrodes of T3 or T4 and the -ΔV coupled out of the source node. If the parasitic capacitance C5 and C6 at the isolated drain electrodes (nodes C and D) of T3 and T4 is minimized, the amplified voltage across nodes C and D will be large enough to completely mask any threshold mismatch between devices T3 and T4. As the potential on the source electrode of the conductive cross-coupled device falls, charge transfer amplification will occur on the drain node. As -ΔV further increases the conductive device will begin to operate in the linear region causing node C or D to fall rapidly to the applied source potential. The other cross-coupled device will remain non-conductive as the gate drive remains substantially constant due to the regenerative feedback which insures that the gate potential will fall at least as fast as the source potential. At t5, CPID turns T5 and T6 on shorting nodes E and F to VN causing the differential signal between nodes C and D to be further amplified. At t6 CP4 drops to VN, isolating the bit/sense lines from VH. At t7, CP3 rises to VH allowing the bit/sense lines to be coupled to nodes C and D. Because of the latched state of T3 and T4, one of the bit lines will be discharged to VN. If a logical one, corresponding to a charge of VH-VE in storage capacitor CS, has been sensed, bit/sense line 16 will discharge. At t8 VW returns to VN trapping the proper potential on storage capacitor CS, thus ending the cycle. 
     FIG. 3 shows a typical circuit which can be used to generate clock pulse CP1 from clock pulses CP3 and CP4 from potential supplies VI and VN. During the time that CP3 is positive device T13 applies VI to the output. When CP4 is positive T14 will apply VN to the output. 
     While the subject invention relies on charge transfer amplification to provide additional amplification of the input signal, certain processing technologies may make it undesirable to provide the proper ratio of drain to source capacitances. In such a case regenerative feedback alone may be relied upon to provide the differential voltage necessary to set the latch. In addition other sensing means or latching configurations may be used which are responsive to the amplified differential voltage at nodes C and D. 
     Data is written in a similar manner as sensing except that the level on the appropriate bit/sense line is forced to a potential level higher than that provided when sensing a charged storage capacitor, or lower than that provided when sensing an uncharged storage capacitor. 
     While conventional latch type sense amplifiers have an input sensitivity of about 250-500 millivolts, the subject sense amplifier has an input sensitivity in the range of about 2- 20 millivolts, depending upon performance required. This improvement in response is due to the initial precharging of the source nodes of the cross-coupled devices and to the decrease in source potentials at a constant rate. It will be recognized that variations in pulse amplitude and timing will permit operation without a dummy cell and/or allow the use of T1 and T2 as charge transfer amplifiers. 
     Although the invention has been described in terms of a single embodiment, those skilled in the art will recognize that various modifications previously described by others and obvious extentions of the subject invention may be made. For example, other types of devices may be used to perform various functions of the invention. Since the cross-coupled FETs are operated in the saturation region during the amplification stage of the sensing cycle, other current-limited conduction devices exhibiting a controllable threshold may be substituted therefor, and, although the invention has been described in a single FET/capacitor memory cell environment, other charge storage means may be utilized.