Abstract:
A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running placement and routing with the new books, and timing the resulting logic. If there are timing violations, existing, non-filler books which are in close proximity are considered for swapping with the eco books. The book swaps are all done with wire connections only (i.e. the book placements are not affected). This way, critical paths and non-critical paths can be traded-off to achieve a faster design, even though books are not allowed to be moved. Some simple algorithms are discussed; however, there are many heuristic and analytic algorithms that can be applied in choosing swaps, based on the needs of the particular design.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     Trademarks  
         [0002]     IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. and other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.  
       BACKGROUND OF THE INVENTION  
       [0003]     1. Field of the Invention  
         [0004]     This invention relates to swapping circuits in a metal-only, engineering change only (ECO) process using wire swaps to allow for better slews and timing.  
         [0005]     2. Description of Background  
         [0006]     This invention relates to an engineering change only (ECO) process where timing and slews can be improved by effectively swapping similar circuits using wiring changes. Typically, in IBM&#39;s engineering processes wire-only changes are used to make minor tweaks to a chip design by keeping all the silicon masking while changing the wire masks in the chip fabrication process.  
         [0007]     In fact, even logic circuits can be created with metal, provided special ‘filler cells’ are used. These filler cells contain un-customized transistors. By connecting up these transistors in the right way, different logical functions can be created (i.e. NAND3, OR2, Inverter, etc.).  
         [0008]     This way, wafers can be created in large quantities up through the wire customization steps. Then, if new problems are detected in the design, the design fixes can be made simply using wire changes that get applied to make new masks to apply to the existing sub-stock. The effect is a quicker chip fabrication from the last detected problem/fix until chip availability.  
         [0009]     One problem with metal-only engineering changes is that the metal-customized filler cell gates are generally not as fast as original silicon gates due to the limitation of making the filler cells growable. Also, it is difficult to provide all the flavors of filler-cell books (due to high cost of design and modeling efforts) and there is a likelihood that some of these books would never get used. There may also not be enough contiguous space for some of the larger books required in an engineering change since much of the space may have already been used up.  
         [0010]     It would be desirable to have a way to design using filler cells that were just as good as original silicon books due to the cost of modeling efforts. Also, if a new path becomes the most critical path in an area, it would be nice to have the flexibility of re-choosing which circuits get used for which applications to achieve the same function with better performance.  
       SUMMARY OF THE INVENTION  
       [0011]     This invention provides a way for making wire-only design changes while maintaining or improving system path performance. In accordance with the preferred embodiment, the engineering changes are made using any current engineering change method. The changes can be fully placed and wired, or simply placed with wire estimates. Then, the design is exercised to determine if there are any design violations. If so, the invention can be invoked. In the preferred embodiment using a design exercised by timing, a determination is made if there are any slew and/or slack timing violations. A replacement candidate is selected and the violation replaced by the processed described in detail below.  
         [0012]     Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:  
         [0014]      FIG. 1  illustrates the prior art for an original circuit design.  
         [0015]      FIG. 2  illustrates the prior art for a wire-only change to an original circuit design.  
         [0016]      FIG. 3  illustrates the first timing problem and the first swap.  
         [0017]      FIG. 4  illustrates the results after the first swap.  
         [0018]      FIG. 5  illustrates the second timing problem.  
         [0019]      FIG. 6  illustrates the results after the second swap.  
         [0020]      FIG. 7  illustrates the high-level process of the invention.  
         [0021]      FIG. 8  illustrates incumbent/candidate table with distances. 
     
    
       [0022]     The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0023]     The first step of the invention is to use the timing model to classify all books in the design. First, they are classified by pin-compatible function (e.g. NAND3, NOR2, AOI22, etc.) and put on the appropriate list as potential ‘candidates’ for swapping. Next, they are analyzed for original slack (i.e. slack of the worst path each book is involved in), gain, beta ratio (or any other parameter that will be used for book swap selection). These properties are associated with the books (i.e. through an associated list or look-up table).  
         [0024]     Then, the timing model is analyzed to determine which books (circuits) are contributing to the timing problems. These could be books that are slow, have poor gains, cause bad slews, have poor locations, etc. These books to be replaced are referred to as ‘incumbent’ books.  
         [0025]     The invention then calls for the ‘BEST replacement’ candidate to be chosen for each incumbent. Distance can be factored in as well as slack, gain, and slew. Swaps are made between incumbents and candidates. Then, the model is re-timed.  
         [0026]     Results of the preferred embodiment did not require any reiteration of the invention, although that could certainly be done.  
         [0027]     In order to understand the invention in more detail, it is important to review the engineering change metal-only (ECO) process. Turning to  FIG. 1 , notice that there is an original logic circuit design. In this design, there are NANDs, NORs, and Buffers (made up of double-invertors). However, there can be any number or type of logic gates. In this example, NAND2 gate,  101 , and NAND2 gate,  108 , have outputs connected to inputs of NAND2 gate,  102 , whose output is connected to input of NOR2 gate,  103 . Another input is connected directly to input of said NOR2 gate,  103 . Said NOR2 gate,  103 , has output connected to NAND2 gate,  104 , whose output is connected to input of BUFFER gate,  105 . NAND2 gate,  106 , has output connected to input of buffer gate,  107 , and input of said NAND2 gate,  104 . This figure represents an example of an original circuit, prior to any metal-only EC design.  
         [0028]     There are times when a logical change is needed to enhance a function or fix a design.  FIG. 2  represents a metal-only engineering change to the design in  FIG. 1 . Notice in  FIG. 2  there is an additional input connected to input of new NAND2 gate,  201  instead of to original input of said NOR2 gate,  103 . The output of NAND2 gate,  102 , is now connected to input of said new NAND2 gate,  201 . Output of said new NAND2 gate,  201 , is connected to same original input of said NOR2 gate,  103 . The output of said new NAND2 gate,  201 , is also connected to input of new BUFFER gate,  202 , whose output is used for some new function.  
         [0029]     Turning to  FIG. 3 , notice there is a new critical timing path,  301 , (for the logic described with  FIG. 2 ) that did not exist in  FIG. 1 . This path, propagates through NAND2,  101 , NAND2,  102 , NAND2,  201 , NOR2,  103 , NAND2,  104 , and BUFFER,  105 . Suppose this path is critical because of a bad slew introduced at the output of new NAND2 gate,  201 , observed at the poor slew net,  302 . In the prior art, the only way to fix this problem with a metal-only fix is to change the power levels of new NAND2,  201 , or new BUFFER,  202 , or to find a different set of filler cells to accomplish better timing results. Often, there is a limitation to the types of metal-only filler cell books that can be customized to solve this problem.  
         [0030]     The current invention allows for a solution that can improve timing tremendously. In this simple example in  FIG. 3 , it would be beneficial to swap NAND2,  106 , and NAND2,  201 , because NAND2,  106 , is a stronger book (i.e. has more gain), and could likely solve the bad slew problem on bad slew net,  302 . The only major restriction is that after the swap, it is important that the new NAND2 gate,  201 , does not break the timing of the path involving NAND2 gate,  106 . This means that the original slack, slew, gain, and location of these gates may be needed to ensure paths do not get worse.  
         [0031]     Please note that there are many algorithms that could be chosen to select which books to swap. These swaps could all be determined for the entire design and then all applied at once. The swaps could also be done incrementally (i.e. one at a time) and the design re-timed after each swap. The algorithm could also involve substituting every possible equivalent book in a greedy algorithm and saving the best swap for each case.  
         [0032]     The preferred embodiment was implemented with a program (a perl script). The following parameters were used by the program:  
                                                         Parameter   Default   Description                                RADIUS   200   um   Any book that is greater than this distance                   from the incumbent will not be considered as                   a candidate. This ‘distance’ is the                   equivalent wire distance of the two books.                   Book 1: (x1, y1), Book 2: (x2, y2).                   Distance = abs(x2 − x1) + abs(y2 − y1) &lt;=                   RADIUS to be considered.       PSLACK   200   ps   Candidates must have more than this positive                   slack to be considered for a swap. This is                   to protect the previous circuit from getting                   harmed by the metal-only book after a swap.       NSLACK   50   ps   Incumbents with a slack that is less than                   this number are considered for swap to                   improve their slack. Using a slightly                   positive number can help to improve the                   slack past zero (the target).       NSLEW   150   ps   Incumbents with a slew greater than this                   value will be considered for a swap. The                   slack and slew targets can be tweaked to                   get the best filter. There can also be a                   manual list generated for which books to                   choose as incumbents, if necessary.       NDLY   50   ps   Sometimes, the book delay can be used to                   see that there are problems with an ECO                   book.       MINPOWER   6       Do not even consider candidates whose                   power is not great than this number.                   This is very much dependent on the                   technology. For the preferred embodiment,                   this number represented a large power                   level that could handle large fanout and                   slews.                  
 
         [0033]     In the preferred embodiment, new NAND2 gate,  201  would be the incumbent gate. Suppose its slack is −120 ps and its physical location is x, y (microns from origin). Its slew is 300 ps and its delay is 210 ps. With a technology whose slews should be less than 100 generally, the 300 is extreme. This is a good indication that the book does not have enough gain for the surrounding circuits. Therefore, it would be selected as an incumbent. Suppose NAND2 gate,  106 , has a slack of +520, a power level of 8, and is at physical location x+80, y−40. This equates to a distance of 80+40=120 um from the incumbent, new NAND2 gate,  201 . Since the distance, 120 um, is less than RADIUS=200 um, the power 8 is greater than MINPOWER=6 and the original slack +520 is greater than PSLACK=200, this is a candidate. Assuming the 120 um is the closest book, this candidate would be the best choice.  
         [0034]     In  FIG. 4 , NAND2 gate,  106 , and NAND2 gate,  201 , have been swapped from the new design shown in  FIG. 3 .  
         [0035]     Turning to  FIG. 5 , notice that there may be another critical timing path,  501 , that is better than the new critical timing path,  301 , but still needs further fixes. In this case, the new BUFFER gate,  202 , is not strong enough to feed whatever logic it connected to before. However, BUFFER gate,  107 , seems to have a stronger gain and is located nearby. The invention would once again comparing slews, gains, slacks, and locations of these books. Assume a swap is determined to improve the design.  
         [0036]      FIG. 6  shows the resulting circuit after BUFFER gate,  107 , is swapped with new BUFFER gate,  202 .  
         [0037]     Turning to  FIG. 7 , notice that the invention makes use of the prior art. For the prior art, the first step is to change the design and perform the ECO place and wire,  701 . This ensures there are only wire changes made to the design. The next step is to run timing on the design,  702 . The timing is checked,  703 . If the timing is acceptable, the ECO task is done,  704 . However, if the design does not meet timing, there was no adequate alternative. The design would need to be re-worked manually and the process repeated from steps  701  through  704 .  
         [0038]     This invention allows for further automatic changes to the design. After the slack is determined to be unacceptable,  703 , the invention allows the step of creating an incumbent list,  705 . This consists of filtering all books out of the design that have poor slews, slack, etc. These are typically the new filler cell gate array books, but could also be any other books in the original design that have timing problems.  
         [0039]     The next step is to create a candidate list,  706 . This can be accomplished in many ways. The preferred embodiment uses a perl program to create a linked list for all books of each type. Pre-filtering of this list is done for speed (i.e., only books with a power level greater than MINPOWER=6, slack&gt;PSLACK, etc. are added to the table). Each book also has an associate list with properties of placement, slack, slew, gain, book type, etc. For each incumbent, the book type is extracted. The linked list for that type book is traversed. For each book, the distance is calculated and any additional filtering could be done as well (i.e. slack, slew). All books that qualify are added to a table of possible substitutions, but the closest book is also added to a FINAL list of swaps. The program can output JUST the FINAL swaps or the list of all possible swaps.  
         [0040]     The next step is the make the best swap for each book,  707 . The preferred embodiment is a perl script which runs outside the timing environment. It is fast and will determine all the swaps in less than a minute. However, it is also possible to have the program run in an incremental timing environment and determine just the first swap. The swap can then be made, the results analyzed, and the program come up with the next swap. Care has to be taken to keep the program from looping on the same group of swaps.  
         [0041]     Once the swaps are made,  707 , timing is run again,  702 , and the slacks reanalyzed,  703 . If the slacks are acceptable, the design is done,  704 . If not, the process can be iterated again with different parameters.  
         [0042]     While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. This invention could also be applied to fixing other types of problems (i.e. non-timing) in a metal-only EC. For instance, if testability or fault tolerance need improvements, violations detected for these criteria could corrected by replacements applied as additional features and advantages are realized through the techniques of the present invention.  
         [0043]     These claims should be construed to maintain the proper protection for the invention first described.