Abstract:
The invention concerns a method of detecting a fault attack including providing a plurality of blinding values; generating a first set of data elements including a first group of data elements and at least one additional data element generated by performing the exclusive OR between at least one data element in the first group and at least one of the blinding values; generating a second set of data elements corresponding to the exclusive OR between each data element of the first set and a selected one of the plurality of blinding values; generating a first signature by performing a commutative operation between each of the data elements of the first set; generating a second signature by performing the commutative operation between each of the data elements of the second set; and comparing the first and second signatures to detect a fault attack.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the priority benefit of French patent application Ser. No. 09/58141, filed on Nov. 18, 2009, entitled “Method and Apparatus for Detection of a Fault Attack,” which is hereby incorporated by reference to the maximum extent allowable by law. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method and apparatus for detecting fault attacks, and in particular to a method and apparatus for providing detection based on signatures. 
     2. Discussion of the Related Art 
     Integrated circuits may comprise circuitry that is considered sensitive in view of the security of the data it manipulates, such as authentication keys, signatures, etc., or in view of the algorithms it uses, such as encryption or decryption algorithms. Such information is desired to be kept secret, meaning that it should not be communicated to or otherwise be detectable by third parties or unauthorized circuits. 
     A common process for pirating information manipulated by an integrated circuit consists in detecting the zones of the circuit that are used during the processing of that information. For this, the circuit is activated or placed in a functional environment and data packets to be encoded are introduced at an input. While the data is being processed, the surface of the integrated circuit is swept by a laser to inject faults in the functioning of the circuit. By analyzing in parallel the outputs of the circuit, this enables the zones of the circuit that process the data to be determined. Having localized these zones, the pirate can concentrate attacks on these zones in order to determine the secret data being processed. 
     Signatures provide a way of protecting a circuit against fault attacks. A signature is generated based on one or more data values that will be used by an algorithm. A signature is then generated on the same data values after they have been used by the algorithm. A difference in the two signatures will indicate the occurrence of an attack. Once the detection circuit has detected such an attack, it can trigger a counter measure, such as resetting the circuit, and/or incrementing a counter, which renders the integrated circuit permanently inactive once a certain number of faults have been detected. 
     Side channel attacks are a different type of attack involving, for example, measuring the power consumption of a circuit. Blinding provides a way of protecting a circuit against side channel attacks. Blinding involves altering, in a non-destructive fashion, the inputs of an algorithm using a pseudo-random variable. 
     It would be desirable to provide circuits in which a same group of data values can be used to generate signatures to detect fault attacks and be blinded to make side channel attacks harder. However, there are difficulties in implementing effective circuits that combine these functions. 
     SUMMARY OF THE INVENTION 
     It is an aim of the present invention to at least partially address one or more problems in the prior art. 
     According to one embodiment of the present invention, there is provided a method of detecting a fault attack comprising: providing a plurality of blinding values; generating a first set of data elements comprising a first group of data elements and at least one additional data element generated by performing the exclusive OR between at least one data element in the first group and at least one of said blinding values; generating a second set of data elements corresponding to the exclusive OR between each data element of the first set and a selected one of said plurality of blinding values; generating a first signature by performing a commutative operation between each of the data elements of the first set; generating a second signature by performing said commutative operation between each of the data elements of the second set; and comparing the first and second signatures to detect a fault attack. 
     According to one embodiment, generating said at least one additional data element comprises generating a plurality of additional groups of data elements by performing the exclusive OR between each data element of the first group of data elements and each of said plurality of blinding values, and selecting at least one data value of at least one additional group to form the at least one additional data element. 
     According to another embodiment, generating the at least one additional groups of data elements further comprises performing the exclusive OR between each data element of the first group of data elements and each combination of two of said blinding values. 
     According to another embodiment, the second set of data elements is generated by blinding each data element of said first set by performing the exclusive OR between each data element of the first set and the selected one of the plurality of blinding values. 
     According to another embodiment, the second set of data elements is generated by blinding said first group of data values to generate a blinded group of data elements by performing the exclusive OR between each data element of the first group and the selected one of the plurality of blinding values, and performing the exclusive OR between at least one data element and said at least one of said blinding values. 
     According to another embodiment, selecting the at least one additional data element comprises, for each data value in each blinded group: determining whether said data value is already present in the second set; and if said data value is not already present in the second set, adding said data value to the second set. 
     According to another embodiment, selecting the at least one additional data element further comprises: tagging each data value added to the second set as unavailable; and if said data value is already present in the second set, determining whether said data value is tagged as unavailable, and if not, tagging said data value as unavailable, and if so, adding said data value to the second set. 
     According to another embodiment, generating said first and second signatures comprises performing an exclusive OR between each data element of the corresponding set of data elements. 
     According to another embodiment, generating said first and second signatures comprises adding together each data element of the corresponding set of data elements. 
     According to another embodiment, generating said first and second signatures comprises multiplying together each data element of the corresponding set of data elements. 
     According to another embodiment of the present invention, there is provided circuitry for detecting a fault attack comprising: a memory storing a plurality of blinding values; a computation block arranged to: generate a first set of data elements comprising a first group of data elements and at least one additional data element generated by performing the exclusive OR between at least one data element in the first group and at least one of said blinding values; generate a second set of data elements corresponding to the exclusive OR between each data element of the first set and a selected one of said plurality of blinding values; a signature block arranged to generate a first signature by performing a commutative operation between each of the data elements of the first set, and a second signature by performing said commutative operation between each of the data elements of the second set; and a comparator arranged to compare the first and second signatures to detect a fault attack. 
     According to another embodiment, the circuitry further comprises a function unit arranged to perform an operation based on at least one data value of the first set, wherein said function block is arranged to perform an encryption or decryption operation based on a secret key. 
     According to another embodiment of the present invention, there is provided an integrated circuit, an integrated circuit (IC) card or an integrated circuit (IC) card reader comprising the above circuitry. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other purposes, features, aspects and advantages of the invention will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which: 
         FIG. 1  illustrates a circuit for detecting fault attacks and protecting against side channel attacks according to one embodiment; 
         FIG. 2  illustrates data values used by the circuitry of  FIG. 1 ; 
         FIG. 3  illustrates circuitry for detecting fault attacks and protecting against side channel attacks according to an embodiment of the present invention; 
         FIG. 4  illustrates an example of data used by the circuitry of  FIG. 3 ; 
         FIG. 5  illustrates circuitry for detecting a fault attack and protecting against side channel attacks according to a further embodiment of the present invention; 
         FIG. 6  illustrates an example of data used by the circuitry of  FIG. 5 ; 
         FIG. 7  illustrates steps in a method for generating a data set according to an embodiment of the present invention; and 
         FIG. 8  illustrates an electronic device comprising circuitry for detecting fault attacks according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     For clarity, only those steps and elements useful in an understanding of the invention have been represented in the figures and will be described in detail. In particular, the circuitry for resetting an integrated circuit or rendering it inactive upon detection of one or more fault injections has not been detailed, the invention being applicable to any such circuits. Furthermore, the primary functions of the integrated circuit being protected have not been described in detail, the invention being compatible with integrated circuits implementing any sensitive functions, such as encryption or decryption, or other functions involving sensitive data. 
       FIG. 1  illustrates a circuit  100  comprising a function unit (FUNCTION)  102 , which for example implements an algorithm involving sensitive data, such as an encryption key or the like. In the present example, unit  102  receives a key K on an input line  104 . 
     A group of data values D 1  to D N  are provided on a line  106  to a blinding block (BLINDING)  108 , which applies a blinding algorithm on these data values based on a blinding value R provided on an input line  110  to the blinding block  108 . The blinding value R is for example a pseudo-random value. The blinded data values D 1 ′ to D N ′ are then provided on a line  112  to the function unit  102 . Function unit  102  implements an algorithm that uses the blinded data values D 1 ′ to D N ′, and outputs a result C, which could be an encrypted or decrypted data block, or other value. 
     While being used by function unit  102 , the blinded data values D 1 ′ to D N ′ are, for example, stored in a register (not shown in  FIG. 1 ). At various stages during execution of the algorithm by the function block  102 , and/or at the end of this execution, the blinded values D 1 ′ to D N ′ are output on a line  114  to a signature block (SIG)  116 . The original data values D 1  to D N  are also provided to the signature block  116  on a line  118 . 
     Signature block  116  generates a signature S 1  based on the original data values D 1  to D N , and a signature S 2  based on the blinded data values D 1 ′ to D N ′. The signatures S 1  and S 2  are then compared by a comparator (COMP)  120 , which provide an output on an output line  122  indicating whether or not the signatures match. 
     The blinding algorithm applied by block  108  is, for example, the XOR function, applied between the blinding value R and each of the data values D 1  to D N . However, there is a problem in choosing a signature function to be applied to the both groups of data values to achieve the same result when no fault attack is present. For example,  FIG. 2  illustrates an example of this problem. 
       FIG. 2  illustrates, in a first row  200 , an example of the data values D 1  to D N  for the case that N is equal to 9, and the values D 1  to D 9  are equal to 12, 1, 0, 128, 245, 0, 1, 2 and 8 respectively. Assuming that the function for determining the signature is an addition of all the data values, the signature of D 1  to D 9  will equal 397. A second row  202  in  FIG. 2  illustrates the blinded data values D 1 ′ to D 9 ′, which in this example are obtained by applying an XOR operation between each of the data values D 1  to D 9  and the value 01. Thus the values D 1 ′ to D 9 ′ are equal to 13, 2, 1, 129, 244, 1, 0, 3 and 9 respectively. However, the sum of the data values D 1 ′ to D 9 ′, and thus the signature S 2 , is equal to 402, assuming no faults. Thus, the signature scheme is ineffective as a mismatch of the signatures S 1  and S 2  occurs despite there being no fault. 
       FIG. 3  illustrates circuitry  300  for detecting a fault attack and for protecting against side channel attacks. Circuitry  300  comprises many of the same elements as the circuitry of  FIG. 1 , and these elements will not be described again in detail. In particular, this circuit comprises the function unit  102 , blinding block  108 , signature block  116 , and comparator  120 . 
     The circuitry  300  additionally comprises a pre-blinding block (PRE-BLINDING)  302 , which receives on input lines  304  the data values D 1  to D N  and on input lines  306  a plurality of blinding values R 1  to R L . The pre-blinding block  302  generates a data set of data values D 1  to D M . The set D 1  to D M  comprises the data values D 1  to D N , and one additional data value D M , or a plurality of additional data values D N+1  to D M . The data values D 1  to D M  are provided to the blinding block  108  on lines  308 , and to the signature block  116  on lines  310 . 
     The set D 1  to D M  is generated such that when an XOR blinding function is applied by block  108 , the result is a permutation of the data values D 1  to D M , without introducing new values, and thus the signature block  116  is able to generate a valid signature using any commutative function. This is, for example, achieved as will now be described in more detail with reference to  FIG. 4 . 
       FIG. 4  illustrates a table containing an example of the data values of the data set D 1  to D M . The top row of the table shows the data values D 1  to D N , in this case comprising nine values D 1  to D 9  equal to the binary equivalent of the decimal values 12, 1, 0, 128, 245, 0, 1, 2 and 8 respectively. These data values will be called group A. In this example, it is assumed that the blinding values R 1  to R L  comprise two values R 1  and R 2 , equal to the binary equivalent of the decimal values 01 and 02 respectively. 
     The pre-blinding block  302  generates a new group of data values “A+1” equal to the XOR of each of the values of the data group A with the first blinding value 01 (the symbol “+” designates herein the function XOR). This is shown in the second row of the table in  FIG. 4 , and the values are equal to 13, 0, 1, 129, 244, 1, 0, 3 and 9. The pre-blinding block also generates a new group of data values “A+2” equal to the XOR of each of the values of the data group A with the second blinding value 02. This is shown in the third row of the table in  FIG. 4 , and the values are 14, 3, 2, 130, 247, 2, 3, 0 and 10. 
     In the example of  FIG. 4 , an additional group of data values “(A+1)+2” is also generated. This is equivalent to “A+3”, and is equal to the XOR of each of the values of the data group A with the value 03. The values, shown in the fourth row of  FIG. 4 , are 15, 2, 3, 131, 246, 3, 2, 1 and 11. This group is not always generated, as in some embodiments only a set of data values, corresponding to each of the blinding values R 1  to R L , is generated. 
     For example, rows corresponding to each possible combination of two of the blinded values R 1  to R L  are also generated, unless this combination is equivalent to a blinding value of a row already present. In the example of  FIG. 4 , (A+1)+2=A+3 is not equivalent to any of the rows previously generated. However, if an additional blinding value R 2 =03 were also used, only the rows A+1, A+2 and A+3 would be generated, as (A+1)+3 is equivalent to A+2, (A+1)+2 is equivalent to A+3, and (A+2)+3 is equivalent to A+1. 
     The table of  FIG. 4  thus represents the values D 1  to D M , which are provided on lines  308  and  310  to the blinding block  108  and the signature block  116  respectively. When blinding is applied to this table, the result is merely a permutation of the rows, without adding any new values. In particular, if the blinding value R, for example selected pseudo-randomly from the values R 1  and R 2 , is equal to 01, the first row would become A+1, while second row becomes (A+1)+1, which is equal to A. Similarly, the third row becomes (A+2)+1, which is equal to A+3, and the fourth row becomes equal to (A+3)+1, which is equal to A+2. 
     The blinded versions of the data values D 1  to D N  are used by the function unit  102 . In the example of  FIG. 4 , depending on whether the blinding value is 01 or 02, these blinded values will be those of the second or third row. 
       FIG. 5  illustrates circuitry  500  for detecting a fault attack and for protecting against side channel attacks. 
     Circuitry  500  comprises many of the same elements as the circuitry of  FIG. 1 , and these elements will not be described again in detail. With respect to the embodiment of  FIG. 1 , the embodiment of  FIG. 5  additionally comprises a line  502  for providing the data values D 1  to D N  to an additional pre-signature block  504 , and an additional pre-signature block  506  positioned between the function unit  102  and the signature block  116 , for processing the blinded data values prior to signature generation. Operation of the circuitry of  FIG. 5  will now be described with reference to  FIG. 6 . 
       FIG. 6  illustrates the same numerical example as  FIG. 4  when applied to the circuitry of  FIG. 5 . The pre-signature block  504  generates the same table of values D 1  to D M  as generated in  FIG. 4  (not illustrated again), which will not be described again in detail. The pre-signature block  506  on the other hand generates a new table based on the blinded values D 1 ′ to D N ′. The rows of the table are generated in the same way as the table of  FIG. 4 , in other words by applying each of the blinding values systematically. It is assumed in the example of  FIG. 6  that the blinding value received on line  110  is 02, and thus the values D 1 ′ to D N ′ correspond to the XOR of each of the values D 1  to D N  with the value 02. Thus, the first row of the table in  FIG. 6 , which is labelled A′, is equal to A+2, which is the same as the third row of the table in  FIG. 4 . The second row of the table in  FIG. 6  is equal to K+1, which is equivalent to A+3, in other words the fourth row of the table of  FIG. 4 . The third row of the table of  FIG. 6  is equal to A′+2, which is equivalent to A, in other words the first row of the table of  FIG. 4 . Finally, the fourth row of the table of  FIG. 6  is equal to (A′+1)+2, which is equivalent to A+1, in other words the second row of the table in  FIG. 4 . 
     Thus, it has been shown that the values of the table of  FIG. 6  are a permutation of the values of table of  FIG. 4 , and thus the signature block  116  can validly detect faults by applying a commutative signature algorithm to both sets of data values. 
     An advantage of the embodiment of  FIG. 5  when compared to the embodiment of  FIG. 3  is that it makes the use of multi-fault attacks harder. In particular, whereas a multi-fault attack targeting  FIG. 3  could attack the pre-blinding block  302  and function block  102 , in  FIG. 4  such an attack would have to target both the pre-signature blocks  504  and  506  in addition to the function block  102 . 
     The signature applied by block  116  of  FIG. 3  or  5  is a commutative function such that the order of the data values does not affect the result. Examples of such functions are the XOR function applied between each of the values D 1 ′ to D M ′, or the sum of all the values D I ′ to D M ′, or the multiplication of all the values D 1 ′ to D M ′. Alternatively a combination or variation of one or more of these functions could be used. 
     The number of additional values D N+1  to D M  present in the set D 1  to D M  can be reduced by removing values which are repeated. For example, in the example of  FIG. 4 , the values “0” and “1” in the second row could be removed entirely without reducing the effectiveness of the signature comparison. An example of technique for determining which data values can be added to the initial values D 1  to D N  in the set D 1  to D M  will now be described with reference to the flow diagram of  FIG. 7 . 
       FIG. 7  shows a method for generating the data values D N+1  to D M . In this example, D n  designates the n th  value in the group D 1  to D N , while R P  designates the p th  value of the set of values R 1  to R P , of which a first L values R 1  to R L  are the set of blinding values from which R is selected, and the values R L+1  to R P  are the additional combinations, equal to the result of the following XOR calculations: R 1 +R (L+1) , R 1 +R (L+2) , . . . R 1 +R P , R 2 +R (L+1) , R 2 +R (L+2) , . . . R 2 +R P , . . . R (L−1) +R L . Any repeated values in the set R 1  to R P  can be removed so that each value appears only once, thereby allowing processing time to be reduced. The letter S is used to designate the set of values D 1  to D M , which initially comprises just the values D 1  to D N . 
     In a first step S 1  of the method, the variables n and p are both set equal to one. 
     Next, in a step S 2 , a variable Q is set equal to D n  XOR R p . Initially this will be equal to the XOR of D 1  and the first blinding value R 1 . 
     In a next step S 3 , it is determined whether Q is an element of set S, in other words whether this value is present among the values of D 1  to D N . If not, the next step is S 4 , in which Q is added to the set S, and a tag is associated with value Q indicating that this value is unavailable. The tag could be, for example, a flag associated with this value in a memory, or any other means of indicating that this value is unavailable. 
     If in step S 3  it is determined that Q is an element of S, it is checked in a step S 5  whether this data value in S is available. In other words, it is checked whether this value has already been tagged as unavailable. If it is not available, the next step is the step S 4 , as described above, in which Q is added to the set S, and tagged as unavailable. If, however, in step S 5  it is determined that the data value in S has not been tagged as unavailable, the next step is S 6 , in which the data value Q is not added to set S, but instead this value in S is tagged as unavailable. 
     After steps S 4  and S 6 , the next step is S 7 , in which it is determined whether p is equal to P. If not, p is incremented in step S 8 , and the method returns to step S 2 . If however in step S 7  it is determined that p is equal to P, the next step is S 9 . 
     In step S 9  it is determined whether n is equal to N. If not, then n is incremented in step S 10 , and the method returns to step S 2 . If, however, n is equal to N, the process finishes. 
       FIG. 8  illustrates an electronic device  800  comprising a microprocessor  802 , a memory block  804 , and an input line  806 , which provides input values to microprocessor  802 . The microprocessor  802  provides output values on an output line  808 . Furthermore, fault detection circuitry  810 , for example comprising the pre-blinding block  302  or pre-signature blocks  504  and  506 , a signature block  116  and a comparator  120  as described herein, is provided coupled to an output of the microprocessor. This circuitry  810  provides an alert signal on an output line  812  provided back to the microprocessor  802  if a fault attack is detected due to a mismatch between the signatures. The alert signal for example triggers a reset of microprocessor  802  and/or increments a counter (not shown in  FIG. 8 ) which will permanently deactivate the microprocessor once a certain count value has been reached. 
     The electronic device  800  is for example, an integrated circuit ( 1 C) card, such as a smart card, an IC card reader, such as a credit card payment terminal, or a set top box, a hard disk drive for a PC or laptop, a PC or laptop, a vending machine or other device handling sensitive information. 
     An advantage of the embodiments described herein is that, by generating a set of data values D 1  to D M  as described herein for generation of signatures, the result of blinding these values using an XOR operation will result in a permutation of these values. This leads to a broad choice of signature algorithms that can be used to produce comparable signatures for detecting fault attacks. 
     While a number of particular embodiments of the present invention have been described, it will be apparent to those skilled in the art that numerous variations and alterations may be applied. 
     For example, it will be apparent to those skilled in the art that the embodiments described herein could be applied to a broad range of circuits in which signature variation is used to detect faults. 
     Furthermore, it will be apparent to those skilled in the art that while embodiments have been described in which the enlarged set D 1 ′ . . . D M ′ comprises many additional values D N+1′  to D M′ , in some cases only one or just a few additional values are provided. 
     Furthermore, the embodiments described herein could be implemented in software, hardware or a combination thereof. Additionally, the features described in relation to the various embodiments could be combined in any combination in alternative embodiments. 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.