Abstract:
A power supply circuit is disclosed in which the influence due to variation in the characteristics of transistors is reduced by variation alleviating devices, each connected to transistors that constitute a current mirror. The power supply circuit comprises a configuration having a current mirror to produce a reference voltage. A multiple number of transistors constitute a current mirror. Multiple variation alleviating devices are connected in series with individual transistors.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a power supply circuit having a current mirror.  
         [0003]     2. Description of the Related Art  
         [0004]     As a circuit for producing a reference power supply voltage, a bandgap power supply circuit having a current mirror circuit has been used (see Japanese Patent Application Laid-open 2001-202147, for example).  
         [0005]      FIG. 1  is a schematic circuit diagram showing a configuration of a conventional bandgap power supply circuit. Referring to  FIG. 1 , a conventional bandgap power supply circuit includes transistors MP 1  to MP 3 , transistors MN 1  and MN 2  and transistors B 1  to B 3  and resistances R 1  and R 2 .  
         [0006]     For calculation simplicity, it is assumed that transistors MP 1  to MP 3  are PMOS transistors of an identical size; transistors MN 1  and MN 2  are NMOS transistors of an identical size; transistors B 1  to B 3  are PNP bipolar transistors; transistor B 1  and transistor B 3  have an identical emitter size; and transistor B 2  has an emitter size greater than transistor B 1 .  
         [0007]     Transistor MP 1 , transistor MN 1  and transistor B 1  are connected in series in this order to power supply Vcc. Similarly, transistor MP 2 , transistor MN 2 , resistance R 1  and transistor B 2  are connected in series in this order to power supply Vcc. Further, transistor MP 3 , resistance R 2  and transistor B 3  are connected in series in this order from power supply Vcc. Transistors MP 1  to MP 3  constitute a current mirror portion. Output voltage BGREF is output from the node between transistor MP 3  and resistance R 2 .  
         [0008]     Here, currents flowing through transistors MP 1 , MP 2  and MP 3  will be denoted as I 1 , I 2  and I 3 , respectively. The potential difference between both ends of resistance R 1  will be denoted as          VBE.  
         [0009]     Resistances R 1  and R 2  are set up with appropriate values so that the temperature dependence of BGREF is minimized.  
         [0010]     Further, the base-emitter voltages of transistors B 1 , B 2  and B 3  are referred to as VBE 1 , VBE 2  and VBE, respectively.  
         [0011]     The conventional bandgap power supply circuit having the above configuration produces a reference power supply voltage as an output voltage when power supply Vcc is given. This output voltage BGREF is represented as Eq.(1) 
 
 BGREF=VBE+R 2 ·I 3   (1) 
 
         [0012]     On the other hand, potential difference          VBE between both ends of resistance R 1  is represented by Eq.(2) and current I 3  flowing through transistor MP 3  is represented by Eq. (3). 
 
Δ VBE=R 1 ·I 2   (2) 
 
I3=I2   (3) 
 
         [0013]     Eq. (4) is obtained from Eq.(2) and Eq. (3). 
 
 I 3 =ΔVBE/R 1   (4) 
 
         [0014]     Substituting Eq. (1) into this Eq. (4) gives Eq.(5). 
 
 BGREF=VBE +( R 2/ R 1)·Δ VBE    (5) 
 
         [0015]     Here, if it is assumed that there is no variation in PMOS transistor characteristics and threshold voltage Vth of transistor MP 2  has no offset relative to that of transistor MP 1 , currents I 2  and I 1  flowing through transistor MP 1  and transistor MP 2  are equal to each other, as shown in Eq. (6). 
 
I2=I1   (6) 
 
         [0016]     Further, if Eq. (7) is true and when the emitter area of transistor B 1  and the emitter area of transistor B 2  are denoted by A 1  and A 2 , respectively, then Eq. (8) holds, where q is the elementary charge, k is the Boltzmann constant, T is the absolute temperature of the PN junction.  
               Δ   ⁢           ⁢   VBE     =       VBE   ⁢           ⁢   1     -     VBE   ⁢           ⁢   2               (   7   )                 I   ⁢           ⁢     1   /   I     ⁢           ⁢   2     =       A   ⁢           ⁢   1   ⁢   exp   ⁢           ⁢     (       q   ·   VBE     ⁢           ⁢     1   /   kT       )         A   ⁢           ⁢   2   ⁢   exp   ⁢           ⁢     (       q   ·   VBE     ⁢           ⁢     2   /   kT       )                 (   8   )             
 
         [0017]     Eq. (8) can be transformed into Eq. (9). 
 
 VBE 1 −VBE 2 =kT/q ·ln(( I 1 /I 2)·( A 2/ A 1))   (9) 
 
 Substituting Eq. (6) and Eq. (7) in Eq. (9) produces Eq. (10). 
 
Δ VBE=kT/q ·ln( A 2/ A 1)   (10) 
 
         [0018]     From Eq. (5) and Eq. (10), output voltage BGREF can be represented as 
 
 BGREF=VBE +( R 2/ R 1)·( kT/q )·ln( A 2/ A 1)   (11) 
 
         [0019]     It is understood that VBE has a negative temperature dependence, but the temperature dependence can be cancelled out by adjusting R 2 /R 1 .  
         [0020]     However, the prior art technology described above entails the problem as follows.  
         [0021]     The above description was made referring to a case where threshold voltage Vth of transistor MP 2  has no offset, but there are cases where some offset occurs due to variation in PMOS transistor characteristics. As a result, a shift of the output voltage from the bandgap power supply circuit takes place.  
         [0022]     To begin with, threshold voltage Vth of transistor MP 2  is presumed to have an offset of          Vp relative to that of transistor MP 1 . When the threshold voltage Vth of transistor MP 1  is denoted by Vp, threshold voltage Vth of transistor MP 2  is given as Vp+         Vp.  
         [0023]     Here, when the S-parameter involving transistors MP 1  and MP 2  is read as S, aforementioned Eq. (6) does not hold, and the relationship between currents I 2 ′ and I 1 ′ flowing through transistors MP 1  and MP 2  can be given by Eq. (6′) instead. 
 
 I 2 ′=I 1′·10 (−ΔVp/S)    (6′) 
 
         [0024]     Accordingly, the aforementioned Eq. (10) is rewritten as Eq. (10′). 
 
Δ VBE′ =( kT/q )·{(Δ Vp/S )·ln10+ln( A 2/ A 1)}  (10′) 
 
         [0025]     According to Eq. (5), a shift          BGREF(=BGREF′−BGREF) arising in output voltage BGREF is given by Eq. (12). 
 
Δ BGREF =( R 2/ R 1)·(Δ VBE′−ΔVBE )   (12) 
 
         [0026]     By inserting Eq. (10) and Eq. (10′) into Eq. (12), Eq. (13) is obtained. 
 
Δ BGREF =( R 2/ R 1)·( kT/q )·ln10·(Δ Vp/S )   (13) 
 
         [0027]     Here, as a specific example where it is assumed that R2/R1=8, T=27 deg. C., S=90 mV/K are assumed, output voltage shift          BGREF is given as 
 
Δ BGREF= 5.32 ·ΔVp    (13′) 
 
 which is understood to be the shift that will occur. 
 
         [0028]     Next, threshold voltage Vth of transistor MP 3  is presumed to have an offset of          Vp relative to that of transistor MP 2 . When the threshold voltage Vth of transistor MP 2  is denoted by Vp, threshold voltage Vth of transistor MP 3  is given as Vp+         Vp.  
         [0029]     Here, when the S-parameter involving transistors MP 2  and MP 3  is read as S, aforementioned Eq. (3) does not hold, and the relationship between currents I 3 ′ and I 2 ′ flowing through transistors MP 2  and MP 3  can be given by Eq. (3′) instead. 
 
 I 3 ′=I 2′·10 (−ΔVp/S)    (3′) 
 
         [0030]     Accordingly, the aforementioned Eq. (4) is rewritten as Eq. (4′). 
 
 I 3′=(1 /R 1)·10 (−ΔVp/S)   ·ΔVBE    (4′) 
 
         [0031]     By inserting this Eq. (4′) into Eq. (1), 
 
 BGREF′=VBE +( R 2/ R 1)·10 (−ΔVp/S)   ·ΔVBE    (5′) 
 
 From Eq. (5′) and Eq. (5) the output voltage shift          BGREF is  
                     Δ   ⁢           ⁢   BGREF     =       BGREF   ′     -   BGREF                 =         {       10     (       -   Δ     ⁢           ⁢       V   p     /   S       )       -   1     }     ·     (     R   ⁢           ⁢     2   /   R     ⁢           ⁢   1     )     ·   Δ     ⁢           ⁢   VBE                   (   14   )             
 
 By inserting this Eq. (14) into Eq. (10), 
 
Δ BGREF ={10 (−ΔVp/S) −1}·( R 2/ R 1)·( kT/q )·ln( A 2/ A 1)   (15) 
 
         [0032]     Here, as a specific example where it is assumed that R 2 /R 1 =8, A 2 /A 1 =8, T=27 deg. C., S=90 mV/K, output voltage shift          BGREF is given as  
                     Δ   ⁢           ⁢   BGREF     =         {       10     (       -   Δ     ⁢           ⁢       V   p     /   S       )       -   1     }     ·   8   ·     (     kT   /   q     )     ·   ln     ⁢           ⁢   8                 =       {       10     (       -   Δ     ⁢           ⁢       V   p     /   0.09       )       -   1     }     ·   0.43                   (     15   ′     )             
 
 which is understood to be the shift that will occur. 
 
         [0033]     Next, threshold voltage Vth of transistor MN 2  is presumed to have an offset of          Vn relative to that of transistor MN 1 . When the threshold voltage Vth of transistor MN 1  is denoted by Vn, threshold voltage Vth of transistor MN 2  is given as Vn+         Vn.  
         [0034]     In this case, −         Vn is added to          VBE in the above Eq. (5). Accordingly, the output voltage shift          BGREF is given as 
 
Δ BGREF =−( R 2/ R 1)·Δ Vn    (16) 
 
         [0035]     Here, as a specific example where it is assumed that R 2 /R 1 =8, output voltage shift          BGREF is given as 
 
Δ BGREF=− 8 ·ΔVn    (16′) 
 
 which is understood to be the shift that will occur. 
 
         [0036]      FIG. 2  is a graph showing the relationship between the offset of threshold voltage Vth and output voltage shift          BGREF in the three specific examples. In  FIG. 2 , the output voltage shifts          BGREF, given by Eq. (13′), Eq. (15′) and Eq. (16′), are plotted by  91 ,  92  and  93 , respectively. It is understood that, as an offset of about 20 mV occurs in threshold voltage Vth, output voltage BGREF will have a shift of about 300 mV max. That is, there is a possibility that an output voltage shift that is equal to ten times of, or greater than, the offset occurring in threshold voltage Vth may take place.  
         [0037]     Further, here for calculation simplicity it was assumed that transistors MP 1  to MP 2 , MN 1  and MN 2  are of an identical size and transistors B 1  and B 3  are of an identical size. However, in other than the above case a serious shift will similarly take place in output voltage BGREF, due to the influence of threshold voltage Vth.  
         [0038]     As described above, in the conventional bandgap power supply circuit, there has been the problem that the output voltage is seriously affected by minute variation in device characteristics.  
         [0039]     In the actual LSIs, variation in characteristics will take place due to anisotropy and layout pattern dependence, however, such variation to some extent is regarded to be within tolerance. However, as for the bandgap power supply circuits, it has become difficult to operate the current mirror portion in saturated range as LSIs developed into low-voltage configurations. As a result, some level of minute variation which can be permitted in usual circuits may cause a serious output voltage shift in a bandgap power supply circuit, which cannot be permitted.  
       SUMMARY OF THE INVENTION  
       [0040]     The object of the present invention is to provide a power supply circuit in which influence on the output voltage due to variation in device characteristics can be reduced.  
         [0041]     In order to attain the above object, the power supply circuit of the present invention is a power supply circuit for producing a reference voltage, and includes a plurality of MOS transistors and a plurality of variation alleviating devices. The multiple MOS transistors constitute a current mirror to produce a reference voltage. The multiple variation alleviating devices are connected in series with the individual transistors.  
         [0042]     According to the present invention, since a plurality of transistors that constitute a current mirror are connected in series with variation alleviating devices for reducing the influence of variation in the characteristics of the transistors, it is possible to reduce the influence on the output voltage due to variation in device characteristics.  
         [0043]     The above and other objects, features, and advantages of the present invention will become apparent from the following description with references to the accompanying drawings which illustrate examples of the present invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0044]      FIG. 1  is a schematic circuit diagram showing a configuration of a conventional bandgap power supply circuit;  
         [0045]      FIG. 2  is a graph showing the relationship between the offset of the threshold voltage Vth and the output voltage shift          BGREF in three specific examples; and  
         [0046]      FIG. 3  is a schematic circuit diagram showing a bandgap power supply circuit of the present embodiment. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0047]      FIG. 3  is a schematic circuit diagram showing a bandgap power supply circuit of the present embodiment. Referring to  FIG. 3 , a bandgap power supply circuit of the present embodiment includes transistors MP 1  to MP 3 , transistors MN 1  and MN 2 , diodes D 1  to D 3 , resistances R 1  and R 2 , and resistances r 1  to r 3 .  
         [0048]     For calculation simplicity, it is assumed that transistors MP 1  to MP 3  are PMOS transistors of an identical size, and transistors MN 1  and MN 2  are NMOS transistors of an identical size. Diodes D 1  to D 3  are used as an example, but any other devices can be used as long as they have similar I-V characteristics and have the temperature dependence that is characteristic of diodes. For example, bipolar transistors or MOS transistors may be used as diodes D 1  to D 3 . It is assumed that the PN junction area of diode D 1  and that of D 3  are the same. It is also assumed that diode D 2  has a greater PN junction area than diode D 1 .  
         [0049]     Resistance r 1 , transistor MP 1 , transistor MN 1  and diode D 1  are connected in series in this order to power supply Vcc. Similarly, resistance r 2 , transistor MP 2 , transistor MN 2  resistance R 1  and diode D 2  are connected in series in this order from power supply Vcc. Further, resistance r 3 , transistor MP 3 , resistance R 2 , diode D 3  are connected in series in this order to power supply Vcc. Transistors MP 1  to MP 3  constitute a current mirror portion. Output voltage BGREF is output from the node between transistor MP 3  and resistance R 2 .  
         [0050]     Here, currents flowing through transistors MP 1 , MP 2  and MP 3  will be denoted as I 1 , I 2  and I 3 , respectively. The potential difference between both ends of resistance R 1  is referred to as          VBE.  
         [0051]     Resistances R 1  and R 2  are set up with appropriate values so that the temperature dependence of BGREF is minimized.  
         [0052]     It is also assumed that there is a minute difference (offset)          Vtp in threshold voltage Vth between transistor MP 1  and transistor MP 2 . It is assumed that this difference produces current error          I between current I 1  flowing through transistor MP 1  and current I 2  flowing through transistor MP 2 . It is also assumed that the S-coefficients of transistors MP 1  to MP 3  and transistors MN 1  and MN 2  as MOS transistors are S.  
         [0053]     One of the features of the bandgap power supply circuit of the present embodiment is that resistance r 1  is interposed between the source of transistor MP 1  and power supply Vcc, resistance r 2  is interposed between the source of transistor MP 2  and power supply Vcc, and resistance r 3  is interposed between the source of transistor MP 3  and power supply Vcc.  
         [0054]     Since there is a minute difference          Vtp in threshold voltage Vth between transistor MP 1  and transistor MP 2 , the relationship represented by Eq. (17) holds between gate-source voltage Vgs 1  of transistor MP 1  and gate-source voltage Vgs 2  of transistor MP 2 . 
 
 Vgs 1 =Vgs 2 −ΔVtp    (17) 
 
         [0055]     Further, current I 1  flowing through transistor MP 1  and current I 2  flowing through transistor MP 2  are represented by Eq. (18) and Eq. (19), respectively. 
 
 I 1 =I 0·10 ((Vgs1−Vtp)/S)    (18) 
 
 I 2 =I 0·10 ((Vgs2−Vtp−ΔVtp)/S)    (19) 
 
         [0056]     Accordingly, from Eqs. (17) to (19), Eq. (20) is obtained. 
 
 I 2/ I 1=10 ((Vgs2−Vgs1−ΔVtp)/S)    (20) 
 
         [0057]     Eq. (20) is transformed into Eq. (21):  
                           ⁢         Vgs   ⁢           ⁢   2     -     Vgs   ⁢           ⁢   1       =       Δ   ⁢           ⁢   Vtp     +       S   ·   log     ⁢           ⁢     (     I   ⁢           ⁢     2   /   I     ⁢           ⁢   1     )                       =       Δ   ⁢           ⁢   Vtp     +       S   ·   log     ⁢           ⁢     (     1   +     (     Δ   ⁢           ⁢     I   /   I     ⁢           ⁢   1     )       )                     =       Δ   ⁢           ⁢   Vtp     +         (       S   /   ln     ⁢           ⁢   10     )     ·   ln     ⁢           ⁢     (     1   +     (     Δ   ⁢           ⁢     I   /   I     ⁢           ⁢   1     )       )                       (   21   )             
 
 Using linear approximation (ln(1+x)≅x), 
 
Vgs2−Vgs1≈ΔVtp+(S/ln10)·(ΔI/I1)   (22) 
 
         [0058]     On the other hand, in the present embodiment, resistance r 1  and resistance r 2  are equal in resistance value. When this resistance value is denoted by R, the following relationship holds: 
 
 I 1 ·R+Vgs 1 =I 2 ·R+Vgs 2   (23) 
 
         [0059]     Because this relationship is transformed by rewriting the difference in current between current I 1  and current I 2  as          I, 
 
 Vgs 2 −Vgs 1 =R ·( I 1 −I 2)=− R·ΔI    (24) 
 
 From Eq. (22) and Eq. (24), the relationship between          I and R is given as 
 
   −R·ΔI≈ΔVtp+(S/ln10)·(ΔI/I1)   (25) 
 
 From this, current difference          I is approximated by Eq. (26). 
 
ΔI≈−ΔVtp/(R+(S/(ln10·I1)))   (26) 
 
         [0060]     As a specific example, assuming that S=90 mV, current difference □I is obtained from Eq. (26) as 
 
ΔI≈−ΔVtp/(R+(39 mV/I1))   (27) 
 
         [0061]     Accordingly, as has been described heretofore, according to the power supply circuit of the present embodiment, since a plurality of transistors MP 1  to MP 3  constituting a current mirror are connected in series with respective resistances r 1  to r 3  having resistance value R for reducing characteristics variations of the transistors, it is possible to reduce current difference          I compared to the case where resistance value R is zero, hence it is possible to reduce the influence on the output voltage due to variation in device characteristics.  
         [0062]     Further, since resistances r 1  to r 3  are individually connected between respective transistors MP 1  to MP 3  and power supply Vcc, it is possible to reduce the influence on the output voltage due to variation in threshold voltages Vth of the transistors.  
         [0063]     As understood from Eq. (26), selection of resistance value R makes it possible to suppress to a low level current difference          I corresponding to difference          Vtp in threshold voltage Vth, hence it is possible to improve the effect of correcting variation in characteristics. Though the output voltage shift due to variation in characteristics is preferably as small as possible, the permissible range of the output voltage or current difference is determined by the conditions required by the circuit configuration to which the power supply circuit is applied. It is possible to efficiently reduce the output voltage shift by selecting a proper resistance value R in order to suppress the influence of the variation in characteristics, which is indexed by current difference          I, to and within a predetermined range that is determined in accordance with the required conditions.  
         [0064]     It is also said from Eq. (26) that the greater the resistance value R, the more efficiently variation is corrected. However, as resistance value R becomes greater, the voltage drop proportionally becomes greater. As a result, the power supply operating margin of the circuit to which the power supply circuit is applied will be reduced. Since the permissible power supply operating margin differs depending on the individual circuits to which the power supply circuit is applied, resistance value R may and should be set at maximum within the range of the power supply operating margin. With this scheme, it is possible for the power supply circuit of the present embodiment to reduce the influence of variation in characteristics upon the output voltage while producing an output voltage within the power supply operating margin.  
         [0065]     As a specific example, assuming that I 1 =1 μA,          Vtp=10 mV and R=100 kΩ, current difference          I≅0.07 μA (error 7%) is obtained from Eq. (27). Since          I≅0.26 μA (error 26%) when no resistances r 1  to r 3  are used, or when resistance value R=0Ω it can be said that the current error is reduced from 26% to 7%.  
         [0066]     Further, for calculation simplicity here it was assumed that transistors MP 1  to MP 3 , MN 1  and MN 2  are of an identical size and diodes D 1  and D 3  are of an identical size. However, in other than the above case it is also possible to similarly reduce the shift of output voltage BGREF by the effect of resistance value R.  
         [0000]     (The Difference from Circuits that Use Bipolar Transistors)  
         [0067]     Configurations in which resistances are inserted, as described above, have been disclosed as examples of circuits using PNP bipolar transistors, in which, for example, the source node is replaced by the emitter, the drain node is replaced by the collector, and the gate node is replaced by the base (for example, see Japanese Patent Application Laid-open 06-062531 and Japanese Patent Application Laid-open 02-165212).  
         [0068]     In the circuit using bipolar transistors, the above configuration is needed in order to improve the current mirror characteristics attributed to the base current that is unique to a bipolar transistor and to improve the circuit characteristics attributed to the voltage dependence that is caused by the Early voltage unique to bipolar transistors. Accordingly, in a circuit using bipolar transistors it is necessary to insert resistance devices without regard to device-to-device variation.  
         [0069]     In contrast to this, in a circuit using MOS transistors, no substantial base current that is found in bipolar transistors exists, and the voltage dependence attributed to the Early voltage that is found with bipolar transistors is very small so that usually it does not cause any problem. That is, conventionally, no circuit that uses MOS transistors has had a resistance inserted in order to prevent the voltage operating margin from being lowered.  
         [0070]     In the present embodiment, the purpose of the configuration that has resistances inserted into a circuit using MOS transistors, is to address the technical requirement for reducing the change in current through the current mirror as a countermeasures against variation. That is, the basic concept is quite different from that of the configuration with bipolar transistors.  
         [0071]     While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.