Abstract:
A semiconductor integrated circuit apparatus includes a periodic signal generation circuit connected with N logical circuits, wherein the N is a natural number, outputting a periodic signal. The periodic signal generation circuit includes a reset circuit outputting a reset signal initializing according to outputs from a first stage logic circuit to N−1th logic circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor integrated circuit apparatus, and particularly to a semiconductor integrated circuit apparatus automatically restoring data stored to a plurality of logic circuits connected in series in an event of data loss due to noise or soft error. 
     2. Description of Related Art 
     In recent years, a manufacturing process of a semiconductor integrated circuit apparatus becomes more and more miniaturized. A semiconductor integrated circuit apparatus formed in such a miniaturized manufacturing process consumes low operating power supply voltage having small parasitic capacity in devices. Accordingly in such semiconductor integrated circuit, data stored in a logic circuit mounted therein may be lost due to noise or soft error. 
     The noise here indicates a noise generated due to an interference of adjacent lines in a semiconductor integrated circuit apparatus, an external noise supplied externally, or a noise generated at a junction of a synchronous circuit and an asynchronous circuit. These noises cause an amplitude of a signal waveform to be smaller, or rising edge of a signal may be delayed for example. 
     The soft error here indicates an error that in case radiation (for example neutron radiation and a radiation) is inserted to a semiconductor integrated circuit apparatus, a semiconductor substrate reacts with the radiation, generating a charge, and a logic is inverted by a plurality of the generated charges in output devices of a logic circuit being collected. 
     Such noise or soft error could disable a circuit to recognize a synchronizing clock that activates the circuit because the noise and soft error reduce an amplitude of a signal. Further, even with a reduction in the amplitude small enough for the circuit to still recognize the signal, the signal could delay while the signal transmits through lines due to parasitic resistance or capacity in the lines or devices. In this case also, the circuit is disabled to recognize the signal. In case an amplitude of a signal waveform is reduced due to the noise and soft error, a circuit may induce a malfunction, thereby losing data stored in a logic circuit, for example. 
     A loss of data is described hereinafter in detail. A circuit having a plurality of logic circuits connected in series is explained as an example. A circuit of shift register as an example of such circuit is shown in  FIG. 6 . A shift register  2  shown in  FIG. 6  includes registers REG 0  to REG 7  connected in series. An output from the REG 7  is connected to an input of the register REG 0 . A clock CLK is input to each of the registers REG 0  to REG 7 . The shift register synchronizes with the clock CLK to operate. Outputs from the REG 3  to REG 5  are connected to blocks not shown, with control signals A to C to the blocks. The control signals A to C are signals used to control the blocks. 
     A timing chart of the shift register  2  of  FIG. 6  is shown in  FIG. 7 . As shown in  FIG. 7 , at time t 0  where power is turned on for the shift register, data  1  is set to the register REG 0  by a power-on reset operation. At this time, data  0  is set to other registers. After the time t 0 , data  1  transits to a register connected subsequently in response to a rising edge of the clock CLK. At time t 7 , data  1  is stored to the register REG 7  by this operation. Then data  1  is returned to the register REG 0  at a rising edge of the clock at time t 8 . That is, the shift register  2  shown in  FIG. 6  is a circuit that data  1  transits in a loop of the registers REG 0  to REG 7  in response to rising edges of clocks. 
     A timing chart in case data is lost in the shift register  2  operating as above is shown in  FIG. 8 . As shown in  FIG. 8 , in case an amplitude of a clock to be input at time t 3  is reduced due to noise or soft error, the REG 3  is not activated even with the REG 2  being activated. Further, data  1  stored to the REG 2  does not transit to the REG 3  and is lost. The lost data is not restored until turning on the power again. 
     A specific example of the shift register is disclosed in Japanese Unexamined Patent Application Publication No. 2004-294224. The shift register disclosed in Japanese Unexamined Patent Application Publication No. 2004-294224 includes 5 registers connected in series, having an exclusive or of outputs from first, third, and fifth stages as an input of the first stage. This shift register generates patterns of random numbers. In case data  1  stored to a register is lost due to noise or soft error, this circuit also generates a pattern different from a correct pattern of random numbers. Further, all data stored to a register may become data  0  depending on a status of the pattern of random numbers. In such case, data  1  cannot be transited after that as with the shift register shown in  FIG. 6 . 
     SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, there is provided a semiconductor integrated circuit apparatus that includes a periodic signal generation circuit connected with N logical circuits, wherein the N is a natural number, outputting a periodic signal, and a reset circuit outputting a reset signal initializing according to outputs from a first stage logic circuit to N−1th logic circuit among the N logic circuits. 
     According to the semiconductor integrated circuit apparatus of the present invention, the reset circuit generates a reset signal initializing the first stage logic circuit according to the output signals from the first stage logic circuit to the N−1th logic circuit. For example in case outputs from the first logic circuit to the N−1th logic circuit become the same logic, the reset circuit generates a reset signal to input the reset signal to the first stage logic circuit. Accordingly in case an amplitude of a synchronizing clock is reduced and data transition is failed to lose the data, the periodic signal generation circuit can be initialized by detecting the data loss and inputting data  1  to the first stage logic circuit. The semiconductor integrated circuit apparatus of the present invention therefore is capable of transiting data  1  without restarting such as turning the power on again. 
     Further, in case the reset circuit generates a reset signal according to all the output signals from the N logic circuits, all the logic circuits have data  0  for a period of one clock after output signals from all the logic circuit. However by the reset circuit generating the reset signal according to output signals from the first stage logic circuit to N−1th stage, data  1  can be input to the first stage logic circuit while Nth stage logic circuit is outputting data  1 . This enables to use all synchronizing clocks for transitions of data  1 . 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a circuit view showing a shift register according to a first embodiment of the present invention; 
         FIG. 2  is a timing chart showing a shift register according to a first embodiment of the present invention; 
         FIG. 3  is a timing chart in case data  1  is lost in the shift register of the first embodiment; 
         FIG. 4  is a circuit diagram showing the shift register of the first embodiment in case outputs from all registers are input to a reset circuit; 
         FIG. 5  is a timing chart showing a shift register of  FIG. 4 ; 
         FIG. 6  is a circuit view showing a shift register according to a conventional technique; 
         FIG. 7  is a timing chart showing a shift register according to a conventional technique; and 
         FIG. 8  is a timing chart in case data  1  is lost in a shift register of a conventional technique. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
     First Embodiment 
     An embodiment of the present invention is described hereinafter in detail. A semiconductor integrated circuit apparatus of a first embodiment is a periodic signal generation circuit whereby a plurality of logic circuits is connected in series outputting a periodic signal. In this embodiment, a shift register comprised of an N registers connected in series is described hereinafter in detail as an example. A shift register  1  of this embodiment is shown in  FIG. 1 . 
     As shown in  FIG. 1 , the shift register  1  of this embodiment assumes N=8, having registers REG 0  to REG 7 , and a reset circuit  10 . A first stage of the shift register  1  is REG 0 . The registers REG 1  to REG 7  are connected in series to the register REG 0 . A synchronizing clock CLK is input to the registers REG 0  to REG 7 . Outputs signals of the registers REG 3 , REG 4 , and REG 7  are control signals A to C respectively that are used in other circuit blocks. 
     An input of the reset circuit  10  is connected with outputs from the registers REG 0  to REG 6 , and an output (DETOUT) of the reset circuit  10  is connected to an input of the register REG 0 . An output from the register REG 7  is not input to the reset circuit  10 . A connection of the reset circuit  10  is described hereinafter in detail. 
     The reset circuit  10  includes NOR gates  11  to  13 , and an AND gate  14 . Outputs from the register REG 0  and REG 1  are connected to an input of the NOR gate  11 . Outputs from the register REG 2  and REG 3  are connected to an input of the NOR gate  12 . Outputs from the registers REG 4  to REG 6  are connected to an input of the NOR gate  13 . The outputs from the NOR gates  11  to  13  are connected to an input of the AND gate  14 . An output from the AND gate  14  is connected to the input of the register REG 0 . 
     The registers REG 0  to REG 7  of this embodiment obtains input signals in response to a rising edge of the synchronizing clock CLK to output. The NOR gates  11  to  13  each include a plurality of input terminals. In case all signals input to each of the terminal is low level (for example a ground potential, data  0 ), high level (for example a power supply potential, data  1 ) is output. In case at least one signal input to each of the terminal is high level, low level is output. The AND gate  14  includes a plurality of input terminals. In case all signals input to each of the terminal is high level, high level is output. In case at least one signal input to each of the terminal is low level, low level is output. 
     An operation of the shift register  1  of the first embodiment is described hereinafter in detail.  FIG. 2  shows a timing chart of the shift register  1  of the first embodiment. As shown in  FIG. 2 , in the shift register  1 , data  1  is set to the register REG 0  at timing t 0  on a power on. Then from timings t 1  to t 2 , data  1  is sequentially transmitted at an every rising edge of the synchronizing clock CLK from the register REG 1  to REG 6  that are connected as subsequent stages. At timing t 7 , data  1  is set to the register REG 7 . Then the outputs of the registers REG 0  to REG 6  become data  0 . At this time the reset circuit  10  outputs data  1 , and data  1  is set to the input of the register REG 0 . The register REG 0  obtains data  1  that is set at the timing t 7 , at a rising edge of the synchronizing clock, which is timing t 8 . The operation from timings t 1  to t 8  is repeated afterward. 
     Accordingly the shift register  1  of the first embodiment is a circuit sequentially transiting data  1  through registers connected in series in response to rising edges of a clock that is specified at a power on. 
     An operation of the reset circuit  10  is described hereinafter in detail. After the power is turned on at the timing t 0 , the register REG 0  outputs data  1 , and the registers REG 1  to REG 7  output data  0 . At this time the NOR gate  11  is input with data  0  and data  1 . Thus the NOR gate  11  outputs data  0 . Further, data  0  is input to the inputs of the NOR gates  12  and  13 . Thus the NOR gates  12  and  13  each outputs data  1 . Accordingly the outputs from the NOR gates  11  to  13  at the timing t 0  are respectively data  0 , data  1 , and data  1 . Thus at the timing t 1 , the output from the AND gate  14  that inputs those signals is data  0 . After that from the timing t 1  to t 6 , the AND gate  14  outputs data  0  as long as one of the registers REG 0  to REG 6  outputs data  1 . 
     At the timing t 7  when the registers REG 0  to REG 6  outputs data  0 , the NOR gates  11  to  13  each outputs data  1 . This makes all signals input to the AND gate  14  to be data  1 , thus the AND gate  14  outputs a reset signal (for example data  1 ) . After that as long as one of the registers REG 0  to REGG outputs data  1 , the AND gate  14  outputs data  0 . Accordingly the reset signal is a pulse signal that becomes an inversed logic (for example data  1 ) to output signals while the output signals from the first stage logic circuit to N−1th logic circuit are the same logic (for example data  0 ) 
     A case of losing data  1  in the shift register  1  is explained hereinafter in detail. As an example of data loss, a case where an amplitude of a synchronizing clock is reduced to disable the register REG 3  to respond with the synchronizing clock, thereby losing data  1  is explained hereinafter. A timing chart of the shift register  1  in such case is shown in  FIG. 3 . 
     As shown in  FIG. 3 , the power is turned on at timing to and data  1  is set to the register REG 0 . Data  1  transits to the register REG 2  in an operation from timings t 0  to t 2 . At timing t 3 , an amplitude of a synchronizing clock is reduced due to noise or soft error. Thus even the register REG 2  is operating in response to the synchronizing clock, the register REG 3  is not able to respond and operate. In such case, the register REG 2  takes data  0 , which is being input at that time, in response to a rising edge of the synchronizing clock at timing t 3 . On the other hand the register REG 3  is not able to take in data  1 , that is output from the register REG 2  at a rising edge of the synchronizing clock which is the timing t 3 . Thus the register REG 3  keep storing data  0  that is stored at the timing t 2 . Data  1  that is supposed to transit to the register REG 3  is lost. 
     In case data  1  is lost in this way, outputs from the registers REG 0  to REG 6  of the shift register  1  all become data  0 . The reset circuit  10  generates a reset signal (for example data  1 ) in case all the outputs from the registers REG 1  to REG 6  become data  0  and sets data  1  to the input of the register REG 0 . Accordingly, in the reset circuit  10 , in case all the outputs from the registers REG 0  to REG 6  become data  0 , the AND gate  14  outputs data  1  because the NOR gates  11  to  13  output data  1 . By this operation, the reset circuit  10  generates the reset signal (for example data  1 ) in case data  1  is lost in any of the register REG 0  to REG 6  due to noise or soft error. On the other hand in case any one of the registers REG 0  to REG 6  outputs data  1 , in the reset circuit  10 , the AND gate  14  outputs data  0  because an NOR gate connected with the register outputting data  1  outputs data  0 . 
     Then at the timing t 4 , the register REG 0  takes data  1  in response to a rising edge of the synchronizing clock. After that, the shift register  1  repeats the operation from the timings t 1  to t 8 , which is shown in  FIG. 2 . 
     As described in the foregoing, in the shift register  1  of the first embodiment, in case data  1  is not stored to any register due to noise or soft error while the registers are performing an operation to transit one data  1 , the reset circuit  10  generates a reset signal (for example data  1 ) in response to all the outputs from N−1 registers (in this embodiment, registers REG 0  to REG 6 ) becoming data  0 . Then the shift register  1  sets the reset signal to an input of the register REG 0 , which is the first stage. This enables the register REG 0  to take in data  1  in response to a rising edge of the synchronizing clock that is input after data  1  is lost. By data  1  transiting through the registers, the shift register  1  is able to initialize without performing a reset operation such as restarting the power. Further, after the initialization, data  1  can be transited. Accordingly, in case the outputs from the first stage logic circuit to N−1th stage logic circuit matches with a signal of a first level (for example data  0 ), the reset circuit  10  outputs a second level (for example data  1 ) regardless of the output from Nth stage logic circuit. Even in case data  1  is not stored to any register due to noise or soft error, it is possible to initialize without a reset operation such as restarting the power. 
     A shift register  1 ′ inputting outputs from N registers (in this embodiment, REG 0  to REG 7 ) into the reset circuit is explained hereinafter in detail.  FIG. 4  shows a circuit diagram of the shift register  1 ′ .  FIG. 5  shows a timing chart of the shift register  1 ′ of  FIG. 4 . As shown in  FIG. 5 , in the shift register  1 ′, in case all the outputs from the registers REG 0  to REG 7  become data  0 , a reset circuit  10 ′ outputs a reset signal (for example data  1 ) . Accordingly, after data  1  is taken into the register REG 7 , the last stage, and then data  0  is taken in again, all the outputs from the registers REG 0  to REG 7  become data  0 . The reset circuit  10 ′ generates a reset signal (for example data  1 ) in response to this. In such case, the synchronizing clock that makes the register REG 7  to transit from data  1  to data  0  is not used for an operation for the shift register  1 ′ to transit data  1 . That is, a period from timings t 8  to t 9  is a dead cycle when data  1  does not transit between registers. 
     On the other hand the shift register  1  of the first embodiement (as shown in  FIGS. 1 and 2 ) inputs outputs from the N−1 registers (in this embodiment the registers REG 0  to REG 6 ), which is excluding the last stage, into the reset circuit  10 . By such connection, when data  1  transits from the register REG 6 , which is N−1 stage, to the register REG 7 , which is Nth stage, all the outputs from the registers REG 0  to REG 6  that are input to the reset circuit  10  become data  0 . This makes the reset circuit  10  to generate the reset signal (for example data  1 ). Further, data  1  is stored to the first stage register REG 0  at a rising edge of a synchronizing clock when data stored to the register REG 7  transits from data  1  to data  0 . Accordingly while the registers REG 0  to REG 6  output a signal of a first logical level (For example data  0 ) and the last stage register REG 7  outputs a signal of a second logical level (for example data  1 ), the reset circuit  10  of this embodiment outputs data  1  and the first stage register REG 0  inputs data  1 . Thus it is possible to eliminate a period that the shift register  1  stores data  1 . The shift register  1  of this embodiment is able to use all the rising edges of the synchronizing clocks for transition of data  1 . 
     The present invention is not limited to the above embodiment but may be modified as appropriate. For example the reset circuit  10  is not limited to the circuit configuration of the above embodiment but may be changed as long as it has a logic of generating data  1  in case all signals being input become data  0 . 
     It is apparent that the present invention is not limited to the above embodiment and it may be modified and changed without departing from the scope and spirit of the invention.