Abstract:
Briefly, a stage amplifier comprises a differential amplifier having stages and a switch to connect a first differential output of a stage with a second differential output of the stage at a beginning of a conversion cycle.

Description:
BACKGROUND OF THE INVENTION 
     A pipeline analog to digital converter (ADC) architecture may include stage amplifiers. The number of stage amplifiers may be substantially equal to the number of output bits. The output bits may indicate the instantaneous amplitude level of an analog signal. The stage amplifier may receive an analog signal and according to a clock signal may compare the analog signal to a reference voltage level. The comparison result of the stage amplifier may be outputted in the form of an output voltage level that may be translated to values of logic bits. Furthermore, the stage amplifier may output one or two bits to provide a digital value to the sample of the analog signal. However, the output voltage of the stage amplifier may need to be adapted to a required output voltage level within a given range, e.g., a given error window. One solution of enabling the stage amplifier to adapt to the required output voltage level range within the given error window nay be to provide a large current to the stage amplifier. The large current may increase a slew rate and a bandwidth of the stage amplifier. A large charge current may increase a power consumption of the stage amplifier. 
     Thus, there is a need to provide a pipeline ADC which mitigates the above-described disadvantage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanied drawings in which: 
     FIG. 1 is a block diagram of a receiver that includes an analog to digital converter (ADC), according to an embodiment of the present invention; 
     FIG. 2 is a block diagram of an ADC, according to an embodiment of the present invention; 
     FIG. 3 is a block diagram of a stage amplifier, according to an embodiment of the present invention; and 
     FIG. 4 is a schematic illustration of clock signal and output voltage diagrams helpful in understanding the operation of the stage amplifier of FIG.  3 . 
    
    
     It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. 
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. 
     It should be understood that the present invention may be used in a variety of applications. Although the present invention is not limited in this respect, the circuits and techniques disclosed herein may be used in many apparatuses such as pipeline analog to digital converters (ADC). Although the present invention is not limited in this respect, pipeline ADC&#39;s may be used with receivers of a radio system. Receivers intended to be included within the scope of the present invention include, by a way of example only, wireless local area network (LAN) receivers, two-way radio receivers, digital system receivers, analog system receivers, cellular radiotelephone receivers and a like. 
     Types of wireless LAN receivers intended to be within the scope of the present invention include, but are not limited to, receivers for receiving spread spectrum signals such as, for example, Frequency Hopping Spread Spectrum (FHSS), Direct Sequence Spread Spectrum (DSSS) and the like. 
     For simplicity, although the scope of the invention is in no way limited in this respect, embodiments of the present invention that will be described below may be related to a pipeline ADC. The term “plurality” may be used throughout the specification to describe two or more components, devices, elements, parameters and the like. For example, “plurality of stage amplifiers” describes two or more stage amplifiers. 
     Referring firstly to FIG. 1, a block diagram of an apparatus that may be used with an exemplary embodiment of the present invention is shown. In this example, the apparatus is a receiver  100  and, more particularly, a receiver that may be used with a wireless LAN system and may comply with IEEE standard “IEEE Std 802.11-1997”, if desired, although the scope of the present invention is in no way limited in this respect. 
     Although the scope of the present invention is not limited in this respect, the receiver  100  may include an antenna  110 , a demodulator  120 , a pipeline ADC  130 , a digital signal processor (DSP)  140 , and a LAN interface  150 . 
     In operation, antenna  110 , for example, a dipole antenna, a shot antenna, or the like, may receive modulated radio frequency (RF) signal that may include data Demodulator  120  may demodulate the RF signal and may provide an analog signal. Pipeline ADC  130  may receive the analog signal and may convert the analog signal into a digital signal. A detailed description of the operation of a pipeline ADC will be given with the description of FIG. 2 below. DSP  140  may receive the digital signal from pipeline ADC  130  and process the signal to provide LAN data to LAN interface  150 . In this example, LAN interface  150  may be used to transmit the LAN data to a Personal Computer (PC), if desired. 
     Referring to FIG. 2 a pipeline ADC  200  according to an exemplary embodiment of the present invention is shown. Although the scope of the present invention is not limited in this respect, pipeline ADC  200  may include a sample and hold (S/H) unit  210 , conversion stages  220 ,  230 ,  240 , a clock system  250  and a digital correction unit  260 . 
     In operation, pipeline ADC may convert an analog signal  201  to a digital signal  270 . Clock system  250  may provide clock signals to S/H unit  210 , conversion stages  220 ,  230  and  240 , and digital correction unit  260 . Although the scope of the present invention is not limited in this respect, clock system  250  may generate conversion cycles by providing clock signals during the conversion of analog signal  201  into digital signal  270 . A conversion cycle may be controlled by a clock signal  252 , a clock signal  254 , and a clock signal  256 . Although the scope of the present invention is not limited in this respect, a conversation cycle may include a sampling period controlled by clock signal  252  and a process-and-hold period controlled by clock signal  254 . Furthermore, in an embodiment of the invention, for example, at the beginning of the sampling period, a reset period may be provided. The reset period may be controlled by clock signal  256 . For example, during the sampling period, analog signal  201  may be sampled. During the process-and-hold period, the sample of the analog signal  201  may be held and processed by conversion stages  220 ,  230  and  240 , and digital correction unit  260 . 
     Conversion stages  220 ,  230  and  240  may provide at least one bit to digital correction unit  260 . However, in this embodiment of the present invention, conversion stages  220 ,  230  and  240  may provide 1.5 bits to digital correction unit  260 . Furthermore, in alternative embodiments of the present invention, conversion stages  220 ,  230  and  240  may provide two or more bits to digital correction unit  260 , if desired, although the scope of the present invention is in no way limited in this respect. In addition, in this example of the present invention, conversion stages  220 ,  230  and  240  may have generally the same architecture. However, in alternative embodiments of the present invention, the architecture of some of the conversion stages may be different from the architecture of other stages. For example, in one embodiment of the present invention, one of the conversion stages, e.g. conversion stage  220 , may include a differential stage amplifier and at least two comparators, and may provide 1.5-2 bits to digital correction unit  260 . 
     Digital correction unit  260  may receive 2 bits from conversion stages  220 ,  230  and  240 , may correct the value of the bits according to algorithms that may be known to one skilled in the art, and may provide a stream of bits that may represent an instantaneous amplitude level of analog signal  201 . Although the scope of the present invention is not limited in this respect, the number of bits of digital signal  270  may be substantially equal to the number of conversion stages, if desired. Furthermore, in some embodiments of the present invention the number of bits may be less then the number of conversion stages, if desired. For example, a pipeline ADC that comprises ten conversion stages may output a 9 bits digital signal, if desired. 
     Turning to FIGS. 3 and 4, a detailed description will now be provided of the operation of a stage amplifier  300  that may perform the functionality of at least part of a conversion stage in accordance with exemplary embodiments of the invention. FIG. 3 is a schematic illustration of stage amplifier  300  according to an embodiment of the present invention, and FIG. 4 is a schematic illustration of timing and output voltage diagrams showing clock signals that may control conversion cycles of an input signal useful for the operation of stage amplifier  300 . 
     Although the scope of the present invention is not limited in this respect, stage amplifier  300  may include a set of switches  310 , a set of switches  320 , a set of switches  330 , capacitors  340 ,  341 ,  345  and  346 , and a differential amplifier  370  that may include a first amplification stage  350  and a second amplification stage  360 . 
     In operation, a conversion cycle may begin with a reset period  432 . Although the scope of the present invention is not limited in this respect, during reset period  432  switches  330  may be closed. Thus, during reset period  432 , differential outputs  354  and  356  of first amplification stage  350  of differential amplifier  370  may be connected to each other, and differential outputs  364  and  366  of second amplification stage  360  of differential amplifier  370  may also be connected to each other. Although the scope of the present invention is not limited in this respect, switches  330  may be controlled by a clock signal  430  (shown in FIG.  4 ). Switches  330  may be opened at the end of the reset period  432 . 
     Concurrently, in an embodiment of the invention, switches  310  may be closed for a sampling period  415 . Thus, capacitors  340  and  341  may be charged to a positive voltage level, which may be provided by input  302 , and capacitors  345  and  346  may be charged to a negative voltage level, which may be provided by input  304 . Furthermore, an output voltage level at outputs  364  and  366  may be substantial zero during sampling period  415 , as indicated by level  444  of an output voltage diagram  440  shown with the timing and output voltage diagrams of FIG.  4 . Although the scope of the present invention is not limited in this respect, the activation of switches  310  may be controlled based on a clock signal  410 . However, it should be understood to one skilled in the art that clock signal  410  may include two clock cycles and/or a shorter clock cycle and/or a longer clock cycle, in comparison to the exemplary clock signal  410  described above with reference to in FIG. 4, or the like. 
     Although the scope of the present invention is not limited in this respect, at a process and hold period  445 , switches  320  may be closed, and switches  310  may be opened. Furthermore, the operation of switches  320  may be controlled based on clock signal  420 . However, it should be understood to one skilled in the art that clock signal  420  may include two clock cycles and/or shorter clock cycle and/or longer clock cycle, in comparison to the exemplary clock cycle  420  described with reference to FIG. 4, or the like. In addition, the output voltage level at outputs  364  and  366 , during the process and hold period, may be relatively high, as indicated by level  446  of the output voltage diagram in FIG.  4 . In addition, a positive reference voltage may be provided to capacitors  341  from an input  306 , and a negative reference voltage may be provided from an input  308 ; however, it should be understood to one skilled in the art that a negative input voltage may be provided from input  306  and a positive voltage level may be provided from input  308 . Furthermore, in some embodiments of the present invention, inputs  306  and  308  may be shorted by comparators (not shown). Although the scope of the present invention is not limited in this respect, the processing of the input signal may be performed by differential amplifier  370 . For example, in the case of one to two conversion bits per stage, an output voltage of differential amplifier  370  may be calculated as follow Vout=2* Vin±Vref, wherein Vin may include differential input voltages  302  and  304 , respectively, and Vref may include differential reference voltages  306  and  308 , respectively. 
     Although the scope of the present invention is not limited in this respect, the next sampling period may begin with a reset period to reset the voltage at the outputs of first stage  350  and second stage  360  of differential amplifier  370 . However, in alternative embodiments of the present invention, the reset period, during which the operation of connecting between the first differential output and the second differential output of the differential amplifier may be performed, may be at an end of the process and hold period of the conversion cycle. Furthermore, in other alternative embodiments of the present invention, the reset period may be performed at a time period between the beginning of the sampling period and the end of the process and hold period of the conversion cycle (not shown). 
     While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true