Abstract:
An acceptable voltage margin between a voltage level for triggering electrostatic current discharge and a voltage level for programming operation of an OTP device is determined. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor.

Description:
TECHNICAL FIELD 
       [0001]    This present disclosure relates to electrostatic discharge (ESD) protection, more particularly in relation to one-time programmable (OTP) integrated circuit devices. The present disclosure is particularly applicable to 0.18 micrometer (μm) multi-project wafers (MPW). 
       BACKGROUND 
       [0002]    Recent development of some OTP products, such as flash drives, LCD-drivers and the like, has incurred an increase in programming voltage from the 3.3 volt level to 8.5 volts. The purpose of the ESD protection device is to protect victims and bypass ESD current during an electrostatic discharge event. The typical ESD protection device, such as an NMOSFET circuit provided for 3.3 volt applications, presents reliability issues if applied to the higher voltage devices. Gate-drain oxide breakdown in FET circuitry is a likely possibility. 
         [0003]    Moreover, the protection circuit should not turn on under normal and programming operation modes. Normally, the junction breakdown of 3.3V devices is around 9.7V. For an 8.5V programming voltage OTP application, the Vt 1  “trigger voltage” of an ESD device can&#39;t be lower than the programming voltage; otherwise the ESD device will cause a false trigger, thus interfering with normal and programming operation modes. 
         [0004]    A critical need thus exists for an ESD protection device for one-time programmable products that is highly reliable and immune to false-triggering under a high damping noise environment or under a latch-up testing environment. Such a protection device should operate at a voltage margin that can accommodate, for example, programming timing of about 50 μs pulse width with 10 μs rise time. The trigger voltage should be set at a level that adequately protects the circuit during electrostatic discharge to divert discharge current between supply terminals, but at a level that prevents diversion of current during the relatively high voltage programming operation for one-time programmable (OTP) devices. 
       SUMMARY 
       [0005]    The needs described above are fulfilled, at least in part, by determining an acceptable voltage margin between a voltage level for triggering diversion of electrostatic current discharge from supply terminals and a voltage level for programming operation of an OTP device. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor. 
         [0006]    The bipolar transistor of the ESD protection circuit is coupled between supply terminals. A control circuit for the transistor is coupled to an output of the false trigger prevention circuit. The false trigger prevention circuit is connected in series with a downsize capacitive circuit across the supply terminals. The control circuit comprises an FET transistor connected in series with a resistor across the bipolar transistor, a junction between the control FET transistor and the resistor connected to the base of the bipolar transistor. An output node of the false trigger prevention circuit is connected to the gate of the control FET transistor. A resistor in the control circuit is set to a resistive value to configure the resistive-capacitive time constant of the circuit commensurate with the determined voltage margin. 
         [0007]    The false trigger prevention circuit includes a first FET, connected between a first supply terminal and the false trigger prevention circuit output node, and a second FET, connected between the gate of the first FET and a second supply terminal. The gate of the second FET is connected to the false trigger prevention circuit output node. 
         [0008]    The downsize capacitive circuit includes a capacitor and current mirror connected in series between the false trigger prevention circuit output node and the second supply terminal. The current mirror comprises first and second capacitive circuit FETs connected in parallel, the gates of the capacitive circuit FETs connected to each other. 
         [0009]    Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which: 
           [0011]      FIG. 1  is a schematic diagram of a traditional stack NMOS power clamp of the prior art; 
           [0012]      FIGS. 2   a  and  2   b  are a schematic diagram and a TLP characteristic representation of a traditional lateral NPN, respectively; 
           [0013]      FIG. 3  is a block diagram of an ESD protection device in accordance with the present disclosure; and 
           [0014]      FIGS. 4   a    4   b  are a detailed schematic diagram in accordance with the device exemplified in  FIG. 3 , and a corresponding TLP characteristic representation thereof, respectively. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.” 
         [0016]    The present disclosure addresses and solves the current problems of gate oxide unreliability, large trigger voltage margin, and large chip area requirements attendant upon forming OTP ESD protection for high voltage devices. In accordance with embodiments of the present disclosure, a poly gate stack is eliminated and a lateral NPN is utilized to avoid gate oxide unreliability issues. Further ESD requirements are met, and device size is reduced. 
         [0017]    Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
         [0018]      FIG. 1  illustrates a traditional stack MOS OTP ESD protection device of the prior art, applied to protect an OTP device having a high 9.0 programming voltage. Reliability of this device is in jeopardy because of the likelihood of gate oxide breakdown with respect to the programming pad and the first gate. Moreover, the ESD device trigger voltage (Vt 1 ) is likely to be too high to protect internal devices. Although a stack PMOS ESD protection device may be substituted, both alternatives require a large integrated circuit size to attain ESD performance 
         [0019]    Normally, the junction breakdown of 3.3V devices is around 9.7V. For 8.5V programming voltage OTP application, the Vt 1  “trigger voltage” of the ESD device can&#39;t be lower than the 8.5V programming voltage, otherwise the ESD device will be false trigger and interfere with normal and programming operation modes. Thus the Vt 1  trigger voltage of the ESD device should be designed to be between 8.6V to 9.6. 
         [0020]    To address the reliability concern with respect to the high programming voltage, a lateral NPN transistor can be used in place of the MOS implementation. Elimination of a poly gate avoids the possibility of gate oxide breakdown. A single stage lateral NPN also occupies a significantly smaller size. The schematic diagram and TLP characteristic representation of traditional lateral NPN is shown in  FIG. 2   a  and  FIG. 2   b , respectively. As indicated in the TLP characteristic, ESD performance (It 2 ) is around 2.7 A, which is good enough to pass 2 KV HBM specification. The Vh holding voltage is around 6.0V, which is greater than the 3.6V maximum operation voltage so there is no latch-up risk. However, the Vt 1  trigger voltage is around 13V, which may not meet requirements and is still too high to adequately protect internal circuits. 
         [0021]      FIG. 3  is a block diagram illustrative of the ESD protection device of the present disclosure. ESD pipolar transistor  12  is connected to supply terminals VPP and VSS. During an ESD event, control circuit  14  applies an activation signal at the base of transistor  12  to turn it on and thus divert ESD discharge current away from the circuit to be protected. False trigger prevention circuit  16  is connected in series with capacitive downsize circuit  18  across the supply terminals. The output of false trigger prevention circuit  16  is applied to control circuit  14 , providing a positive feedback thereto to prevent false triggering of transistor  12  during rapid noise in the programming mode of the OTP device. Capacitive downsize circuit  18  provides equivalent capacitance under normal and ESD modes, while reducing the area of the integrated circuit. 
         [0022]      FIG. 4   a  is a schematic diagram of the protection device represented in  FIG. 3 . Control circuit  14  comprises FET Q 5  connected in series with resistor R 2  across the supply terminals. Junction node N 2  is connected to the base of transistor  12 . Resistor R 1  is connected between supply VPP and the gate of FET Q 5 . 
         [0023]    False trigger prevention circuit  16  comprises FET Q 4  and FET Q 3 . FET Q 4  is connected in parallel with resistor R 1 , between VPP and node N 1 . Node N 1  is also connected to the gate of FET Q 3 . FET Q 3  is connected between the gate of FET Q 4  at node N 3  and VSS. 
         [0024]    Capacitive downsize circuit  18  comprises the series connection of capacitor C′ and a current mirror between node N 1  and VSS. The current mirror comprises FET Q 1  and FET Q 2  connected in parallel, their gates connected together. The equivalent capacitance of circuit  18  is represented in  FIG. 4   a  as “C.” The downsize circuit  18  provides a capacitive multiplication factor M, wherein M=W 2 /W 1 , and C=C′*(1+M). 
         [0025]    Under normal operation mode, in the absence of an ESD event, Q 5  is off. Node N 1  is at a high state, as it is at the potential of VPP by virtue of its connection to R 1 . FET Q 3  is on by virtue of the high state of N 1 . N 3  is thus at the low state of VSS and turns FET Q 4  on to maintain node N 1  at the high VPP value. Node N 2  is at the low state of VSS by virtue of its connection through resistor R 2 . 
         [0026]    NON Under ESD operation mode, node N 1  is at VSS level, and both FET Q 3  and FET Q 4  will be off. FET Q 5  is on, so that node N 2  will be high through FET Q 5 . Transistor Qesd is rendered on to bypass ESD current through VPP pad. 
         [0027]    The advantages of the false trigger prevention circuit can be understood in relation to operation during normal programming. Ideally, the potential of nodes N 1  and N 2  should be same as in the normal operation described above, i.e., high and VSS, respectively. In the absence of FET Q 3  and FET Q 4 , programming noise can change the voltage level of node N 1  to VSS, and the voltage level of N 2  will change to high, causing transistor Qesd to turn on. False triggering then occurs. In the presence of the FET Q 3  and FET Q 4  in circuit  16 , the following operation takes place during programming. Initially, node N 1  is at a high potential. In the presence of noise, FET Q 3  and FET Q 4  provide positive feedback to node N 1  to maintain it at a high potential state. Node N 2  will remain at the VSS potential and transistor Qesd will not turn on. False triggering is thus prevented. 
         [0028]    The RC time constant of this exemplified embodiment is designed to be around 2 us. Thus, the ESD device will not be triggered under a programming operation mode with 50 us pulse width and 10 us rising time. 
         [0029]    As indicated in the TLP characteristic of  FIG. 4   b , ESD performance (It 2 ) is approximately 2.8 A, which is within specification. The holding voltage (Vh) is around 6.0V, which is greater than the maximum operating voltage. The trigger voltage Vt 1  is reduced, in comparison with that of  FIG. 2   b , and meets the requirement of around 9.V with well-controlled mis-triggering RC elements. 
         [0030]    The embodiments of the present disclosure can achieve several technical effects, including OTP ESD protection with robust ESD performance for high voltage applications, with no gate oxide reliability concerns, and more efficient use of I/O area. The present disclosure enjoys industrial applicability as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or any other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use ESD protection devices to pass ESD/Latch-up standards specifications (e.g., liquid crystal display (LCD) drivers, synchronous random access memories (SRAM), One Time Programming (OTP), and power management products). 
         [0031]    In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.