Abstract:
A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This claims the benefit of commonly-assigned U.S. Provisional Patent Application No. 60/790,404, filed Apr. 7, 2006, which is hereby incorporated by reference herein in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to programmable logic devices (PLDs), and, more particularly, to specialized processing blocks which may be included in such devices. 
     As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof. 
     One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations. 
     For example, a PLD sold by Altera Corporation, of San Jose, Calif., under the name STRATIX® II includes DSP blocks, each of which includes four 18-by-18 multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed. In order to support four 18-by-18 multiplication operations, the block has 4×(18+18)=144 inputs. Similarly, the output of an 18-by-18 multiplication is 36 bits wide, so to support the output of four such multiplication operations, the block also has 36×4=144 outputs. 
     However, those inputs and outputs may not be used in every mode in which the DSP block can operate. For example, if the DSP block is configured as a finite impulse response (FIR) filter, with 18-bit data and coefficients, each block may be used to perform the summation of four 18-by-18 multiplications to form a 4-tap sub-block of a longer FIR filter. In this case, the number of inputs is 4×(18+18)=144 lines, but the output is only 38 bits wide even though the DSP block is able to support 144 output lines. Similarly, in a 36-by-36 bit multiplication, all four internal multipliers are used but only (36+36)=72 input lines and 72 output lines are used (even though there are 144 input lines and 144 output lines). Hence, in that configuration the input lines are not used fully even though the core of the DSP block is fully used. 
     Input/output (I/O) drivers and lines can consume significant device area. Indeed, in a DSP block of the aforementioned STRATIX® II PLD, I/O resources consume approximately 50% of the DSP block area. And yet, as discussed above, they are not always used. At the same time, they cannot be eliminated because all of the potential configurations of the block have to be supported. 
     It would be desirable to be able to reduce the area of a PLD consumed by a specialized processing block such as a DSP block without losing functionality of the block. 
     SUMMARY OF THE INVENTION 
     The present invention relates to specialized processing blocks for PLDs wherein the specialized processing blocks have reduced area without losing functionality. According to one aspect of the invention, the specialized processing block preferably includes a plurality of fundamental processing units instead of discrete multipliers. Each fundamental processing unit preferably includes the equivalent of at least two multipliers and logic to sum the partial products of all of the at least two multipliers. As a result, the sums of the all of the multiplications are computed in a single step, rather than summing the partial products of each multiplier to form individual products and then summing those products. Such a fundamental processing unit can be constructed with an area smaller than that of the individual multipliers and adders. If a single multiplication is required to be performed, one of the multipliers in the fundamental processing unit is used, while the inputs to the other(s) are zeroed out. Nevertheless, because the provision of the fundamental processing unit reduces the area of the specialized processing block, efficiency is improved. 
     In a preferred embodiment, the fundamental processing unit includes the equivalent of two 18-by-18 multipliers and one adder so that it can output the sum of the two multiplication operations. While each of the 18-by-18 multipliers can be configured for a smaller multiplication operation (e.g., 9-by-9 or 12-by-12), the integrated nature of the fundamental processing unit means that the individual multiplier outputs are not accessible. Only the sum is available for use by the remainder of the specialized processing block. Therefore, to obtain the result of a single non-complex multiplication that is 18 bits-by-18 bits or smaller, an entire fundamental processing unit must be used. The second multiplier, which cannot be disengaged, simply has its inputs zeroed. 
     Preferably, each block includes four such fundamental processing units, preferably arranged in half-blocks having two fundamental processing units each, capable of computing a sum of four multiplications. Additional facility preferably is provided to connect the two half-blocks to allow more complex computations when necessary. 
     The specialized processing block according to the invention preferably also has an input multiplexing stage that increases the effective number of inputs for certain more complex operations without increasing the number of I/O lines. Similarly, an output cascade stage allows the outputs of several blocks to be chained for certain more complex operations. Therefore the specialized processing block preferably can be configured for various forms of filtering and other digital signal processing operations. In addition, the specialized processing block preferably also has the capability to feed back at least one of its outputs as an input, which is useful for accumulation and also in adaptive filtering operations. 
     Therefore, in accordance with the present invention, there is provided a specialized processing block for a programmable logic device. The specialized processing block preferably includes a plurality of fundamental processing units, Each of the fundamental processing units includes a plurality of multipliers, circuitry for adding, in one operation, partial products produced by all of the plurality of multipliers, and circuitry interconnecting the fundamental processing units whereby the circuitry for adding adds, in that one operation, the partial products produced by all of the plurality of multipliers in all of the fundamental processing units. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
         FIG. 1  is a functional diagram of one preferred embodiment of a specialized processing block in accordance with the present invention; 
         FIG. 2  is a functional diagram of one half of the specialized processing block of  FIG. 1 ; 
         FIG. 3  is a block diagram of a preferred embodiment of the input multiplexing stage of the specialized processing block of  FIGS. 1 and 2 ; 
         FIG. 4  is a block diagram of a preferred embodiment of an output stage of a specialized processing block in accordance with the present invention; 
         FIG. 5  is a diagram of the output stage of  FIG. 4  configured in a first mode in accordance with the present invention; 
         FIG. 6  is a diagram of the output stage of  FIG. 4  configured in a second mode in accordance with the present invention; 
         FIG. 7  is a functional diagram of a specialized processing block in accordance with the present invention configured for arithmetic shifting; 
         FIG. 8  is a preferred embodiment of an output stage of a specialized processing block in accordance with the present invention configured for logical shifting; 
         FIG. 9  is a functional diagram of a specialized processing block in accordance with the present invention configured for rotation; 
         FIG. 10  is a functional diagram of a specialized processing block in accordance with the preferred invention configured as a barrel shifter; 
         FIG. 11  is a representation of a conventional finite impulse response filter; 
         FIG. 12  is a functional diagram of a specialized processing block in accordance with the present invention configured as a finite impulse response filter; and 
         FIG. 13  is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention will now be described with reference to  FIGS. 1-12 . 
       FIG. 1  shows a functional diagram of one preferred embodiment  10  of a specialized processing block according to the invention. As seen in  FIG. 1 , specialized processing block  10  includes input multiplexing stage  11 , multiplication stage  12 , and output cascade stage  13 . 
     Input multiplexing stage  11  can format and rearrange the inputs to block  10  as required for particular operations. As described in more detail below, input multiplexing stage  10  can be used to allow the performance, in certain conditions, of operations that require more inputs than there are to block  10 , if some of those inputs are duplicates of others. 
     As one example of the type of formatting performed by input multiplexing stage  11 , consider an 18-by-18 complex multiplication in which:
 
Real Result= Re [( a+jb )×( c+jd )]=( ac−bd )
 
Imag Result= Im [( a+jb )×( c+jd )]=( ad+bc )
 
This complex operation requires four 18-by-18 multiplications and hence eight 18-bit inputs, for a total of 144 inputs. Although each half-block  20  can have 144 inputs, in a preferred embodiment, specialized processing block  10  as a whole accepts only 144 inputs. If all of those inputs were routed to only one of the half-blocks  20 , there would be no inputs available for the other half-block  20 . However, because the complex multiplication referred to above has only four unique 18-bit shared inputs, input multiplexing stage  11  can take the 72 inputs a, b, c and d and perform the necessary duplication so those four inputs are properly routed to the correct multiplier inputs for each of the real and imaginary calculations. This leaves another 72 inputs available for the other half-block  20 .
 
     Multiplication stage  12  preferably includes a plurality of fundamental processing units as described above. In a preferred embodiment, each specialized processing block  10  (see  FIGS. 1 and 2 ) includes four fundamental processing units  100 , meaning that it can perform up to eight multiplications in groups of two multiplications that are summed together. In that embodiment, the fundamental processing units  100  in specialized processing block  10  preferably are grouped into identical half-blocks  20 , so that each half-block  20  in its own right can be considered a specialized processing block within the invention. 
     Each fundamental processing unit  100  preferably includes the functionality for a sum of two 18-by-18 multiplications. It is possible to negate one of the inputs in input multiplexing stage  11  in order to provide a difference of multiplications. 
     Each fundamental processing unit  100  preferably supports a sum of two 18-by-18 multiplications and preferably includes two partial product generators  21 , two ten-vector-to-two-vector compressors  22 , a 4:2 compressor  23 , a carry-propagate adder  24  and an output register  25 . Adder  24  preferably also includes rounding capability (e.g., round-to-nearest-integer) and saturation capability (e.g., asymmetric saturation—i.e., from −(2 n ) to +2 n −1). 
     Each partial product generator  21  preferably creates nine 20-bit Booth-encoded vectors (Booth-encoding is a known technique that can reduce the number of partial products), as well as a 17-bit unsigned carry vector (negative partial products are in ones-complement format, with the associated carry-in bit in the carry vector). An additional 19-bit signed partial product may be generated in the case of unsigned multipliers (which preferably will always be zero for signed multipliers). Although preferably up to 11 vectors may be generated, the carry bits preferably can be combined with the partial product vectors, requiring only 10 vectors to be compressed. 
     In each fundamental processing unit  100 , preferably the output of one of the two 10:2 compressors  22  passes through 3:1 multiplexer  26 . In a case where fundamental processing unit  100  is being used for only one multiplication of a size up to 18-by-18, zero input  27  of multiplexer  26  is selected, zeroing out one of the two 18-by-18 multiplications. In a case where fundamental processing unit  100  is being used for two 18-by-18 multiplications (including a case where half-block  20  is being used for a sum-of-four 18-by-18 multiplications such as one of the complex multiplications described above), input  28  of multiplexer  26  is selected to pass the compressor vectors unchanged. In a case where both fundamental processing units  100  are being used together to perform a 36-by-36 multiplication, input  29  of multiplexer  26  is selected, passing the output of that one of compressors  22  through an 18-bit left-shifter  200 . 
     As shown in  FIGS. 1 and 2 , each fundamental processing unit  100  outputs a respective separate output vector P(n) or Q(n). However, an additional 4:2 compressor  201 , along with multiplexer  202  and shifter  203 , are provided to allow the two fundamental processing units  100  to be used together. In the embodiment shown, 4:2 compressor  201  is included in the right-hand one of fundamental processing units  100 , accepting as inputs the output of 4:2 compressor  23  from that fundamental processing unit  100  as well as the output of 4:2 compressor  23  from the left-hand one of fundamental processing units  100 , as modified by multiplexer  202 . 
     Thus, zero input  204  of multiplexer  202  zeroes the left-hand input to compressor  201 , and is selected when the two fundamental processing units  100  are to be used separately. In a case where the two fundamental processing units  100  are being used together, such as a case where half-block  20  is being used for a sum-of-four 18-by-18 multiplications such as one of the complex multiplications described above, input  205  of multiplexer  202  is selected to pass the compressor vectors unchanged. In a case where both fundamental processing units  100  are being used together to perform a 36-by-36 multiplication, input  206  of multiplexer  22  is selected, passing the output of that one of left-hand compressor  23  through an 18-bit left-shifter  207 . 
     When both fundamental processing units  100  are being used together, the two carry-propagate adders  24  preferably are used as a single adder, as indicated by the dashed lines  240 . Similarly, the two output registers  25  preferably are used as a single output register as indicated by dashed lines  250 . 
     Preferably, the Q(n) output (which could include the P(n) output in cases where both fundamental processing units  100  are being used together) can be fed back either to 3:2 compressor  220 , which preferably is interposed between 3:1 multiplexer  26  and 4:2 compressor  23  of right-hand fundamental processing unit  100 , where it is combined with the output of multiplexer  26  to enable an accumulation function, or to input multiplexing stage  11  as a loopback to enable various adaptive filtering functions. This feedback or loopback preferably is accomplished using optional multiplexers  208 - 210  and optional connections  211 - 216 . 
     For example, using optional multiplexer  208  and connections  211 - 213 , one can implement the aforementioned accumulation feedback. In such an embodiment, multiplexer  208  can select either output Q(n) or zero as an input to be fed back. 
     If optional connection  214  is added between connection  212  and input multiplexing stage  11 , and optional multiplexer  209  is added between connections  212  and  213 , then the output of multiplexer  208  can be used either as accumulation feedback or as the aforementioned loopback. In loopback mode, multiplexer  209  would select a zero input to prevent the loopback data from reaching compressor  220 . In feedback mode, multiplexer  209  would select the feedback data. It is not necessary in feedback mode to provide an additional multiplexer (or other selector device) to prevent the feedback data from reaching input multiplexing stage  11 , because internal multiplexers (not shown) in stage  11  can be used for that purpose. 
     Alternatively, multiplexer  209  and connection  214  can be omitted, and a completely independent loopback path can be established using optional multiplexer  210  and optional connections  215 ,  216 . The two separate paths would not normally be used simultaneously because output Q(n) would not normally be used for both feedback and loopback. However, the two embodiments are essentially interchangeable because each requires two multiplexers. 
     As indicated in  FIG. 1 , when outputs P(n), Q(n) are used separately, each can represent, for example, one 18-by-18 multiplication or one sum of two 18-by-18 multiplications. Because an 18-by-18 complex multiplication, as described above, is specialized sum of four 18-by-18 multiplications, the sum of two 18-by-18 multiplications represented by an output P(n) or Q(n) can represent half of an 18-by-18 complex multiplication. 
     Similarly, as shown, when outputs P(n), Q(n) are used together, the output is represented by Q(n), which can represent, for example, any of one 36-by-36 multiplication, one 52-bit to 72-bit multiply-accumulate function, or one sum of four 18-by-18 multiplications. 
     As discussed above, each half-block  20  preferably has 72 inputs. Four 18-by-18 multiplications requires 36×4=144 inputs. As also discussed above, in the case of an 18-by-18 complex multiplication, although there are four 18-by-18 multiplications involved, there are really only four 18-bit inputs (72 inputs), which are rearranged as necessary by input multiplexing stage  11 . In the case of a sum of four independent 18-by-18 multiplications, input multiplexing stage  11  preferably is used as a shift register as shown in  FIG. 3 . 
     As shown in  FIG. 3 , input multiplexing stage  11  preferably includes, in addition to multiplexers and other circuitry (not shown), a first set of 18-bit registers  30 , each of which is associated with one of partial product generators  21 , and a second set of 18-bit registers  31 , each one of which also is associated with one of partial product generators  21  and all of which are chained together (as at  32 ). In this way, for each 18-by-18 multiplication, one independent multiplicand may be input via the block inputs  33  and registers  30 , while the second input for each 18-by-18 multiplication is shifted in via registers  31 . Thus in the case of a sum of four 18-by-18 multiplications, one multiplicand is the same in each of the four multiplications. That one common multiplicand may be input via additional input  34 , or the first one of inputs  33  in the first block  10  (assuming cascaded blocks  10  as discussed below), can be connected via multiplexer  35  to chained registers  31 . 
     Outputs P(n), Q(n) can be used individually, or a plurality of blocks  10  (or half-blocks  20 ) can be chained together using the cascade stage  40  shown in  FIG. 4 . Using cascade stage  40 , output P(n) can be output at  41  via multiplexer  42 . Alternatively, output P(n) can be added at  43  to the output of three-input multiplexer  44 , then registered at  45  and output at  41  via multiplexer  42  and/or chained to three-input multiplexer  440  or, via line  441 , to the third input of three-input multiplexer  44  of the next half-block  20 . Similarly, output Q(n) can be output at  410  via multiplexer  420 . Alternatively, output Q(n) can be added at  430  to the output of three-input multiplexer  440 , then registered at  450  and output at  410  via multiplexer  420  and/or chained to three-input multiplexer  44  of the next half-block  20  or, via line  442 , to the third input of three-input multiplexer  440  of the next half-block  20 . 
       FIG. 5  shows an embodiment  50  where the P(n) and Q(n) outputs are cascaded together. In this embodiment, each three-input multiplexer  44 ,  440  selects its second input and lines  441 ,  442  are unused. This mode can be used for vector multiplications whose outputs are real, including, but not limited to, systolic form FIR filter  1200 , described below in connection with  FIG. 12 .  FIG. 6  shows an interlaced cascade embodiment  60  where the P(n) and Q(n) outputs are cascaded separately. In this embodiment, each three-input multiplexer  44 ,  440  selects its third input, using lines  441 ,  442 . This mode can be used for vector multiplications whose outputs are complex. 
     Specialized processing block  10  of the present invention may be programmably configured as a barrel shifter. Specifically, by using the 36-by-36 multiplier mode, a 32-bit vector can be arithmetically or logically shifted to the left or to the right. Such a shift by N bits may be accomplished by multiplying the vector to be shifted by a second vector of equal length, all of whose bits are 0 except for the Nth least significant bit, which is 1. 
     If the vector to be shifted is sign-extended to 36 bits and the second vector is padded with zeroes to 36 bits, the result is an arithmetic shift, and whether the shift is to the left or to the right depends on whether the result is taken, respectively, from the 32 most significant bits of the 64-bit result, or the 32 least significant bits.  FIG. 7  shows such a shifting operation. 
     Similarly, if both vectors are padded with zeroes to 36 bits, the result is a logical shift, and whether the shift is to the left or to the right depends on whether the result is taken, respectively, from the 32 most significant bits of the 64-bit result, or the 32 least significant bits.  FIG. 8  shows such a shifting operation. 
     In addition, if both vectors are padded with zeroes to 36 bits, and the 32 most significant bits of the 64-bit result are ORed with the 32 least significant bits, the result is a rotation of the N most significant bits of the first vector to the N least significant bits of the result, as shown in  FIG. 9 . 
       FIG. 10  shows how the arithmetic and logical shifting, and rotation, can be performed using the 36-by-36 multiplier mode  190  to perform the 32-by-32 multiplication as described above, an OR gate  191  whose inputs are the two 32-bit halves of the 64-bit result, and a three-input multiplexer  192 , operating according to the following table: 
                                                     A   B   MUX   Result                           Signed   Unsigned   00   Arithmetic shift left           Signed   Unsigned   01   Arithmetic shift right           Unsigned   Unsigned   00   Logical shift left           Unsigned   Unsigned   01   Logical shift right           Unsigned   Unsigned   10   Rotation                        
It should be noted that the arithmetic shift left and the logical shift left produce the same result and thus those cases are redundant. Put another way, a signed input is really needed only for the arithmetic shift right.
 
     Specialized processing block  10  of the present invention may be programmably configured as a finite impulse response (FIR) filter.  FIG. 11  shows a conventional FIR filter  1100  of the systolic form, while  FIG. 12  shows a systolic form FIR filter  1200  configured from specialized processing block  10 . As seen in comparing  FIGS. 11 and 12 , the use of compressors in fundamental processing units  100  as opposed to additional adders reduces the latency in FIR filter  1200  as compared to FIR filter  1100 . 
     Thus it is seen that a specialized processing block for a programmable logic device, based on a plurality of fundamental processing units, has been provided. 
     A PLD  90  incorporating such circuitry according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system  900  shown in  FIG. 13 . Data processing system  900  may include one or more of the following components: a processor  901 ; memory  902 ; I/O circuitry  903 ; and peripheral devices  904 . These components are coupled together by a system bus  905  and are populated on a circuit board  906  which is contained in an end-user system  907 . 
     System  900  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD  90  can be used to perform a variety of different logic functions. For example, PLD  90  can be configured as a processor or controller that works in cooperation with processor  901 . PLD  90  may also be used as an arbiter for arbitrating access to a shared resources in system  900 . In yet another example, PLD  90  can be configured as an interface between processor  901  and one of the other components in system  900 . It should be noted that system  900  is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. 
     Various technologies can be used to implement PLDs  90  as described above and incorporating this invention. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.