Abstract:
A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to perform external accesses during one portion of a clock cycle, and required refresh operations during another portion of the same clock cycle.

Description:
RELATED APPLICATIONS 
     The present application is a continuation in-part of U.S. patent application Ser. No. 09/405,607, by Wingyu Leung, entitled “Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same” filed Sep. 24, 1999, now U.S. Pat. No. 6,415,353 which is a continuation-in-part of U.S. patent application Ser. No. 09/165,228 filed Oct. 1, 1998, now U.S. Pat. No. 5,999,474, by Wingyu Leung and Fu-Chieh Hsu, entitled “Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory” issued Dec. 7, 1999. 
     The present application is further related to U.S. Pat. No. 6,028,804, by Wingyu Leung, entitled “Method and Apparatus for 1-T SRAM Compatible Memory” and issued Feb. 22, 2000; U.S. Pat. No. 6,222,705, by Wingyu Leung, entitled “Method and Apparatus For Refreshing A Semiconductor Memory using Idle Memory Cycles” issued Apr. 24, 2001; and U.S. Pat. No. 6,075,740, by Wingyu Leung, entitled “Method and Apparatus for Increasing The Time Available for Refresh For 1-T SRAM Compatible Devices”, issued Jun. 13, 2000. These patents are hereby incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention is related to semiconductor memories, especially dynamic random access memory (DRAM). In particular, the present invention relates to a method and apparatus of handling refresh operations in a semiconductor memory such that the refresh operations do not interfere with external access operations. 
     DISCUSSION OF RELATED ART 
     A conventional DRAM memory cell, which consists of one transistor and one capacitor, is significantly smaller than a conventional SRAM cell, which consists of 4 to 6 transistors. However, data stored in a DRAM cell must be periodically refreshed, while the data stored in an SRAM cell has no such requirement. Each refresh operation of a DRAM cell consumes memory bandwidth. It is possible for an external access to be initiated at the same time that a refresh access is required. In this case, the external access must be delayed until after the refresh access has been performed. In general, this prevents DRAM cells from being operated as SRAM cells, because SRAM cells do not require refresh operations. 
     Previous attempts to use DRAM cells in SRAM applications have been of limited success for various reasons. For example, one such DRAM device has required an external signal to control refresh operations. (See, 131,072-Word by 8-Bit CMOS Pseudo Static RAM, Toshiba Integrated Circuit Technical Data (1996).) Moreover, external accesses to this DRAM device are delayed during the memory refresh operations. As a result, the refresh operations are not transparent and the resulting DRAM device cannot be fully compatible with an SRAM device. 
     In another prior art scheme, a high-speed SRAM cache is used with a relatively slow DRAM array to speed up the average access time of the memory device. (See, U.S. Pat. No. 5,559,750 by Katsumi Dosaka et al, and “Data Sheet of 16 Mbit Enhanced SDRAM Family 4M×4, 2M×8, 1M×16” by Enhanced Memory Systems Inc., 1997.) The actual access time of the device varies depending on the cache hit rate. Circuitry is provided to refresh the DRAM cells. However, the refresh operation is not transparent to external accesses. That is, the refresh operations affect the memory access time. Consequently, the device cannot meet the requirement of total deterministic random access time. 
     Other prior art schemes use multi-banking to reduce the average access time of a DRAM device. Examples of multi-banking schemes are described in “Data sheet, MD904 To MD920, Multi-bank DRAM (MDRAM) 128K×32 to 656K×32” by MoSys Inc., 1996, and in “An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM&#39;s” by Kazushige Ayukawa et al, IEEE JSSC, vol. 33, No. 5, May 1998, pp. 800-806. These multi-banking schemes do not allow an individual memory bank to delay a refresh cycle. Another prior art scheme uses a read buffer and a write buffer to take advantage of the sequential or burst nature of an external access. An example of such a prior art scheme is described in U.S. Pat. No. 5,659,515, entitled “Semiconductor Memory Device Capable of Refresh Operation in Burst Mode” by R. Matsuo and T. Wada. In this scheme, a burst access allows a register to handle the sequential accesses of a transaction while the memory array is being refreshed. However, this scheme does not allow consecutive random accesses. For example, the memory cannot handle a random access per clock cycle. 
     Another prior art scheme that attempts to completely hide refresh operations in a DRAM cell includes the scheme described in U.S. Pat. No. 5,642,320, entitled “Self-Refreshable Dual Port Dynamic CAM Cell and Dynamic CAM Cell Array Refreshing Circuit”, by H. S. Jang. In this scheme, a second port is added to each of the dynamic memory cells so that refresh can be performed at one port while a normal access is carried out at the other port. The added port essentially doubles the access bandwidth of the memory cell, but at the expense of additional silicon area. 
     Another prior art scheme that attempts to completely hide the refresh operations in an asynchronous DRAM is described in U.S. Pat. No. 4,549,284, entitled “Dynamic MOS Random Access Memory”, by Kunihiko Ikuzaki. In this scheme, an automatic refresh circuit is incorporated in an asynchronous DRAM to generate a refresh cycle after an external access cycle is performed. In the absence of an external access, an internal oscillator continues to generate refresh cycles. Thus, the memory device is constantly performing refresh operations, thereby wasting power. 
     Moreover, the oscillation period of the oscillator is set by the transconductance of an MOS transistor and a capacitor, which varies with process and temperature. Within a typical process and commercial temperature range, the oscillation period varies by up to a factor of two. As a result, it becomes difficult to synchronize the external accesses and the refresh operations. For this reason, the memory device is not suitable for high-speed operations in the auto-refresh mode. 
     Accordingly, it would be desirable to have a DRAM device that handles refresh operations in a manner that is completely transparent to an external accessing memory client for both low-speed and high-speed operations. It would further be desirable if such a DRAM device only performed refresh operations at the times when the memory cells need to be refreshed (i.e., at a rate determined mainly by the charge leakage mechanism of the memory cells, and not by the circuit operation of the automatic refresh circuit). 
     SUMMARY 
     Accordingly, the present embodiment provides a memory device (or an embedded memory block) that includes a plurality of memory cells, which must be periodically refreshed in order to retain data values. In one embodiment, the memory cells are DRAM cells arranged in an array having a plurality rows and columns. In a particular embodiment, the array is divided into a plurality of banks. 
     The memory device includes a plurality of terminals for receiving signals from an external accessing client. These signals can include a clock signal, an address signal, a write/read indicator signal, and address strobe signal and a reset signal. However, these signals do not include a signal that indicates that a refresh operation must be performed. 
     To implement refresh operations, the memory device includes a refresh controller that periodically asserts a refresh request signal, which is used to indicate that a refresh operation is pending. The refresh controller also provides a refresh address identifying one of the rows of the array. The refresh controller increments the refresh address each time that the refresh request signal is asserted. 
     The memory device also includes a memory array sequencer for controlling the timing of external accesses and refresh accesses within the memory device. In general, the memory array sequencer ensures that the required refresh accesses are performed without interfering with any external accesses. 
     More specifically, the memory array sequencer synchronizes external accesses and refresh accesses with different edges of an external clock signal. In one embodiment, external accesses are synchronized (initiated) in response to rising edges of the external clock signal. The external accesses are then completed during the first half cycle of the clock period (e.g., while the clock signal has a high state). In this embodiment, pending refresh accesses are synchronized (initiated) in response to falling edges of the external clock signal. The refresh accesses are then completed during the second half cycle of the clock period (e.g., while the clock signal has a low state). 
     In another embodiment, external accesses are synchronized (initiated) in response to rising edges of the external clock signal. The external accesses are performed as quickly as possible. Pending refresh accesses are then synchronized (initiated) in response to the end of the external accesses. The refresh accesses are completed prior to the next rising edge of the external clock signal. This embodiment allows the external accesses and refresh accesses to be performed as quickly as possible, without being dependent on the duty cycle of the external clock signal. 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a memory system in accordance with one embodiment of the present invention. 
     FIG. 2 is a block diagram of a refresh controller used in the memory system of FIG. 1 in accordance with one embodiment of the present invention. 
     FIG. 3 is a circuit diagram of a memory array sequencer used in the memory system of FIG. 1 in accordance with one embodiment of the present invention. 
     FIG. 4 is a waveform diagram illustrating the timing of various signals in the memory system of FIG. 1 in accordance with one embodiment of the present invention. 
     FIG. 5 is a circuit diagram of another memory array sequencer, which can be used to replace the memory array sequencer of FIG. 3 in another embodiment of the present invention. 
     FIG. 6 is a waveform diagram illustrating the timing of various signals in the memory system of FIG. 1, when the memory array sequencer of FIG. 5 is used in place of the memory array sequencer of FIG.  3 . 
    
    
     DETAILED DESCRIPTION 
     In accordance with the present invention, an SRAM compatible device is designed using DRAM cells. This SRAM compatible device is hereinafter referred to as a one transistor SRAM (1-T SRAM). 
     FIG. 1 is a block diagram of a 1-T SRAM system  100  in accordance with one embodiment of the present invention. 1-T SRAM system  100  includes DRAM array  101 , 2-to-1 multiplexer  102 , AND gate  103 , input signal registers  120 , refresh controller  121  and memory array sequencer  122 . DRAM array  101  includes 64 DRAM memory banks  0 - 63 , read data amplifier  70  and write data buffer  80 . Each of DRAM banks  0 - 63  includes 32 rows and 512 columns of DRAM memory cells, as well as the associated address decoders, word line drivers, sense-amplifiers and column multiplexers, which are not shown, but are understood by those of ordinary skill in the art. The column multiplexers of DRAM memory banks  0 - 63  are connected in parallel to read data amplifiers  70  and write data buffer  80 . Each of DRAM banks  0 - 63  is capable of storing 512 32-bit words. The total capacity of DRAM memory banks  0 - 63  is therefore 32K 32-bit words. 
     The external interface of 1-T SRAM system includes a 32-bit input data bus for providing an input data word DIN[31:0] to write data buffer  80 , a 32-bit output data bus for providing an output data word DOUT[31:0] from read data amplifier  70 , a write/read indicator line for receiving write/read indicator signal WR#, a clock input terminal for receiving an external clock signal CLK, a 14-bit address bus for receiving external address bits EA[14:0], an address strobe line for receiving an address strobe signal ADS#, and a reset line for receiving a reset signal RST#. As used herein, the # symbol indicates that a signal is active low. Note that the signals listed above do not include any signals specifically relating to refresh accesses of DRAM banks  0 - 63 . 
     All of the external signals are referenced to the rising edge of the CLK signal. The external address signal EA[14:0] is divided into 3 fields: a 4-bit word (column) address EA[14:11] (which identifies one of the sixteen 32-bit words in a row), a 6-bit bank address EA[10:5] (which identifies one of the 64 memory banks  0 - 63 ), and a 5-bit row address A[4:0] (which identifies one of the 32 rows in a memory bank). 
     An external device initiates an access to 1-T SRAM system  100  by asserting a logic low address strobe signal ADS#, driving the write/read indicator signal WR# to the desired state (high for write and low for read), and providing an external address EA[14:0]. The ADS#, WR# and EA[14:0] signals are all registered (i.e., latched) into input signal registers  120  at the rising edge of CLK signal. Input signal registers  120  provide the latched ADS#, WR# and EA[14:0] signals as latched output signals LADS#, LWR# and LEA[14:0], respectively. The latched external address LEA[14:0] is divided into two groups of address signals. Address signal LEA[14:11] contains the column address of the memory cells selected for the external access, and address signal LEA[10:0] contains the row and bank address of the memory cells selected for the external access. Address signal LEA[14:11] is provided to the column decoder circuitry in each of DRAM banks  0 - 63 . Address signal LEA[10:0] is provided to an input bus of 2-to-1 multiplexer  102 . 
     The latched address strobe signal LADS# is provided to memory array sequencer  122  and to an inverting input terminal of AND gate  103 . The latched write/read indicator signal LWR# is provided to read data amplifier  70  and write data buffer  80 . 
     Refresh accesses to DRAM array  101  are managed by refresh controller  121 . Refresh controller  121  initiates a refresh access by activating a refresh request signal RREQ high in response to the external clock signal CLK. As described in more detail below, refresh controller  121  activates the refresh request signal RREQ high once every 64 clock periods. Refresh controller  121  also provides an 11-bit refresh address RFA[10:0], which identifies the bank and row to be refreshed in DRAM array  101 . The refresh address RFA[10:0] is incremented each time the refresh request signal is activated. 
     FIG. 2 is a block diagram of refresh controller  121  in accordance with one embodiment of the present invention. Refresh controller  121  includes a modulo-64 counter  201  for generating the refresh request signal RREQ, and an 11-bit binary counter  202  for generating the bank and row address RFA[10:0] for the current refresh operation. Counters  201  and  202  are reset to zero counts when the reset signal RST# is activated low during the initialization of memory system  100 . After the RST# signal is de-activated high, modulo-64 counter  201  begins counting from 0 to 63, with counter  201  being incremented by one in response to each rising edge of the external clock signal CLK. When modulo-64 counter  201  reaches a full count of 63, this counter  201  drives the refresh request signal RREQ high for one period of the CLK signal. Modulo-64 counter  201  then wraps around to a zero count in response to the next rising edge of the CLK signal. 
     The falling edge of the refresh request signal RREQ increments the count of 11-bit binary counter  202  by one. The output of 11-bit binary counter  202 , provides the refresh address RFA[10:0], which identifies the bank and row to be refreshed in DRAM array  101 . After 11-bit binary counter  202  reaches a full count of “111 1111 1111”, the count will automatically wrap around to a zero count in response to the next rising edge of the refresh request signal RREQ. In this manner, refresh controller  121  provides a refresh address RFA[10:0] that traverses the entire row and bank address space of DRAM array  101 . 
     Memory array sequencer  122  generates the conventional DRAM control signals RAS# (row access), SEN# (sense amplifier enable), CAS# (column access), and PRC# (precharge) for controlling the operations of memory array  101 . The functionality of the RAS#, SEN#, CAS# and PRC# control signals in accessing a DRAM array is understood by those of ordinary skill in the art. For example, the functionality of these control signals is described in detail in U.S. Pat. No. 6,078,547, “Method and Structure for Controlling Operation of a DRAM Array”, by Wingyu Leung, which is hereby incorporated by reference. 
     FIG. 3 is a circuit diagram of memory array sequencer  122  in accordance with one embodiment of the present invention. Memory array sequencer  122  includes delay lines  301 - 304 , OR gates  311 - 318 , one-shot circuits  331 - 332 , AND gate  341 , and flip-flops  351 - 352 . Flip-flop  351  includes cross-coupled NAND gates  321 - 322 , and flip-flop  352  includes cross-coupled NAND gates,  323 - 324 . Delay lines  301 ,  302 ,  303  and  304  introduce signal delays d 1 , d 2 , d 3 , and d 4 , respectively. In general, memory array sequencer  122  activates the RAS#, SEN#, CAS# and PRC# signals at predetermined times during half of a CLK period. As a result, an external access (read or write) may be performed during one half of a CLK period, and a refresh access may be performed during the other half of the same CLK period. In the described embodiment, external accesses are performed during the half clock period that the CLK signal has a logic high state, and refresh accesses are performed during the half clock period that the CLK signal has a logic low state. 
     When 1-T SRAM system  100  is started, the RST# signal is activated low, thereby setting flip-flops  351  and  352 , such that these flip-flops provide logic high output signals to AND gate  341 . The RST# signal is then de-activated high, thereby allowing flip-flops  351  and  352  to operate in response to the other applied signals. When there is no external access to system  100 , the latched address strobe signal LADS# is deactivated high. When there is not refresh access pending in system  100 , the refresh request signal RREQ is de-activated low. Under these conditions, OR gates  311  and  312  provide logic high signals to one-shot circuits  331  and  332 , respectively. In response, one-shot circuits  331 - 332  provide logic high signals to flip-flops  351 - 352 , respectively, thereby causing flip-flops  351 - 352  to continue to provide logic high output signals to AND gate  341 . The logic high output of AND gate  341  de-activates the RAS#, SEN#, CAS# and PRC# control signals high. At this time, memory array  101  is idle. 
     As described in more detail below, the latched address strobe signal LADS# is activated low during an external access. The low state of the LADS# signal, along with the high state of the CLK signal causes the output of OR gate  311  to go low. The falling edge at the output of OR gate  311  causes one-shot circuit  331  to generate a negative going pulse having a width substantially shorter than half of the CLK period. This negative pulse resets the output of flip-flop  351  to a logic low value. The logic low value provided by flip-flop  351  causes AND gate  341  to activate the RAS# signal low. The low state of the RAS# signal propagates through delay lines  301 ,  302 ,  303  and  304  (as well as OR gates  315 - 317 ) to drive signals SEN#, CAS# and PRC# low in sequence. More specifically, the low RAS# signal propagates through delay line  301  and OR gate  315  to activate the SEN# signal low after a delay of d 1 . The low SEN# signal then propagates through delay line  302  and OR gates  316 - 317  to activate the CAS# signal low after an additional delay of d 2 . Note that the logic high CLK signal applied to the inverting input terminal of OR gate  317  allows the logic low signal from OR gate  316  to be passed as the low CAS# signal. The low CAS# signal then propagates through delay line  303  to activate the PRC# signal low after an additional delay of d 3 . 
     The logic low signal provided by delay line  303  propagates through delay line  304  after an additional delay of d 4 . The logic low output of delay line  304  is provided to the inverting input terminal of OR gate  318 . As a result, the PRC# signal is de-activated high a delay d 4  after being activated low. 
     The low state of the output of delay line  303  and the high state of the CLK signal cause OR gate  313  to provide a logic low value to flip-flop  351 , thereby setting the output of flip-flop  351  to a logic high state. In response, AND gate  341  deactivates the RAS# signal to a logic high state. The logic high RAS# signal is applied to OR gates  315  and  316 , thereby causing the SEN# and CAS# signals, respectively, to be immediately de-activated high. The logic high value provided by OR gate  316  propagates through delay line  303  after a delay of d 3 , thereby causing OR gate  318  to continue to de-activate the PRC# signal high. The logic high value provided by delay line  303  propagates through delay line  304  after a delay of d 4 , and is applied to the inverting input terminal of OR gate  318 . In this manner, the output signals provided by delay lines  301 - 304  are reset to their original logic high states, such that these delay lines are ready for the next access. 
     The total delay introduced by delay lines  301 ,  302 ,  303 , and  304  is designed to be less than or equal to a half period of the CLK signal. Notice that the RAS# signal is recovered to a logic high state before the CLK signal transitions from the high state to a low state. As a result, another memory cycle can be started at the falling edge of the CLK signal. To ensure that the SEN# and CAS# signals are generated properly during back-to-back memory cycles, the outputs of delay lines  301  and  302  are required to be de-activated high before the RAS# signal is activated low again. 
     In the present embodiment, the delay d 4  introduced by delay line  304  is longer than the delay d 1  introduced by delay line  301  or the delay d 2  introduced by delay line  302 . As a result, when the PRC# signal is de-activated high, delay lines  301  and  302  are already providing logic high output signals. In other embodiments, delay line  301  or delay line  302  can have a longer delay than delay line  304 . However, in such embodiments, a fast reset must be provided on delay lines  301  and  302 , thereby ensuring that the output signals provided by delay lines  301  and  302  recover to logic high states before the activation period of the PRC# signal expires. 
     A memory refresh operation is performed when the refresh request signal RREQ is activated to a logic high value and the CLK signal has a logic low value. That is, refresh operations are only performed during the half period that the CLK signal has a logic low state. The high state of the RREQ signal and the low state of CLK signal causes OR gate  312  to provide a logic low output signal to one-shot circuit  332 . In response, one-shot circuit  332  provides a negative going pulse having a pulse width substantially shorter than a half period of the CLK signal. The negative pulse resets the output of flip-flop  352  to a logic low state. This logic low output signal provided by flip-flop  352  is applied to an input terminal of AND gate  341 . In response, AND gate  341  activates the RAS# signal low. The low state of RAS# signal propagates through delay line  301 , thereby causing the SEN# signal to be activated low after delay dl. The low state of the SEN# signal propagates through delay line  302  after delay d 2 , thereby causing OR gate  316  to provide a logic low output signal to OR gate  317 . Because the inverting input terminal of OR gate  317  receives a logic low CLK signal at this time, the CAS# signal remains de-activated high. The CAS# signal is thereby suppressed during the refresh access (because the refresh access does not involve a column access). [ 0043 ] The logic low signal provided by OR gate  316  propagates through delay line  303 , thereby providing a low signal to the non-inverting input terminal of OR gate, and causing the PRC# signal to be activated low after delay d 3 . The logic low state of the output signal provided by delay line d 3  propagates through delay line  304 , thus providing a logic low signal to the inverting input terminal of OR gate  318  after delay d 4 . OR gate  318  de-activates the PRC# signal high in response to the logic low signal provided to the inverting input terminal of OR gate. The low state of the output signal provided by delay line  303  and the low state of the CLK signal cause OR gate  314  to provide a logic low output signal to flip-flop  352 . In response, flip-flop  352  provides a logic high signal to AND gate  341 , thereby causing AND gate  341  to deactivate the RAS# signal high. The high state of the RAS# signal causes OR gate  315  to provide a logic high output signal, thereby causing the SEN# signal to be deactivated high. The high state of the RAS# signal also causes OR gate  316  to provide a logic high output signal. After a delay of d 3 , the logic high output signal provided by OR gate  316  propagates through delay line  303 , to the non-inverting input terminal of OR gate  318 , thereby causing OR gate  318  to continue to de-activate the PRC# signal high. The logic high value provided by delay line  303  propagates through delay line  304  after a delay of d 4 , and is applied to the inverting input terminal of OR gate  318 . In this manner, the output signals provided by delay lines  301 - 304  are reset to their original logic high states, such that these delay lines are ready for the next access. 
     Returning now to FIG. 1, multiplexer  102  routes either the latched external address LEA[10:0] or the refresh address RFA[10:0] to memory array  101  as the row/bank address RBA[10:0]. Multiplexer  102  is controlled by the output signal provided by AND gate  103 . During an external access, the LADS# signal is activated low and the CLK signal is high, thereby causing AND gate  103  to provide a logic high signal to the control terminal of multiplexer  102 . In response, multiplexer  102  routes the latched external address LEA[10:0] to array  101 . If an external access is not being performed, AND gate  103  provides a logic low signal to the control terminal of multiplexer  102 , thereby causing the refresh address RFA[10:0] to be routed to array  101 . 
     FIG. 4 is a waveform diagram that illustrates the timing of various signals in 1-T SRAM system  100  in accordance with one embodiment of the present invention. In the described example, a read access is performed during the first half of clock cycle T 1 . A refresh operation is performed during the second half of clock cycle T 1 . A write access is performed during the first half of clock cycle T 2 . Memory system  100  is idle during the second half of clock cycle T 2 , as there is no pending refresh at this time. To simplify the timing in the description below, all of the logic gates are assumed to have a negligible delay compared to the period the CLK signal and the delays d 1 -d 4  introduced by delay lines  301 - 304 . 
     Read Access 
     The external accessing client provides a low ADS# signal, a low WR# signal and an external address signal EA[14:0] before the rising edge of clock cycle T 1 . The low WR# signal specifies a read operation, and the external address signal EA[14:0] specifies the read address within DRAM array  101 . At the rising clock-edge of cycle T 1 , the ADS#, WR# and EA[14:0] signals are latched into input signal registers  120 , and provided as the LADS#, LWR# and LEA[14:0] signals, respectively. 
     Within refresh controller  121 , the rising clock-edge of cycle T 1  increments modulo-64 counter  201  to a full count thereby causing the refresh request signal RREQ to be activated high. The high state of the RREQ signal increments 11-bit binary counter by one count, such that the refresh address RFA[10:0] has a value represented by “FA”. The refresh address FA identifies the bank and row address for the pending refresh operation. The refresh address FA is provided to multiplexer  102 , as the refresh address signal RFA[10:0]. 
     The logic low LADS# signal and the logic high CLK signal cause AND gate  103  (FIG. 1) to provide a logic high control signal to multiplexer  102 . In response, multiplexer  102  routes the bank/row information of the latched address LEA[10:0] to memory array  101  as the RBA[10:0] signal. The column information of the latched address LEA[14:11] is also provided to memory array  101 . In response, decoders (not shown) identify an addressed bank, an addressed row and an addressed set of columns of the present read access. 
     The logic low LADS# signal and the logic high RREQ are provided to memory array sequencer  122  (FIG.  3 ). The low state of the LADS# signal and the high state of the CLK signal causes the RAS# signal to be activated low in the manner described above. The low state of the RAS# signal propagates through delay line  301 , thereby causing the SEN# signal to be activated low after a delay of d 1 . The low state of the SEN# signal propagates through delay line  302 , thereby causing the CAS# signal to be activated low after a delay of d 2 . Finally, the low state of the CAS# signal propagates through delay line  303 , thereby causing the PRC# signal to be activated low after a delay of d 3 . In this manner, the RAS#, SEN#, CAS# and PRC# signals are sequentially activated low. 
     The logic low RAS# signal causes the data in the addressed row of the addressed bank (as specified by LEA[10:0]) to be driven to the sense amplifiers of the addressed bank. The logic low SEN# signal causes this row of data to be latched in the sense amplifiers of the addressed bank. The logic low CAS# signal causes the sense amplifiers corresponding with the addressed set of columns (as specified by LEA[14:11]) to be coupled to read data amplifier  70 . The logic low PRC# signal causes the data word (RDA) read from DRAM array  101  to be latched into read data amplifier  70  and provided as the data output signal DOUT[31:0]. 
     Within memory array sequencer  122 , the low state of the PRC# signal also causes the RAS#, SEN# and CAS# signals to be deactivated high in the manner described above. Within memory array  101 , the low state of the PRC# signal turns off the word line of the addressed row in the addressed bank, turns off the sense amplifiers in the addressed bank, and precharges the bit lines of the addressed bank, thereby preparing memory array  101  for the next operation. After a delay of d 4 , the logic low output signal provided by delay line  303  propagates through delay line  304 , thereby de-activating the PRC# signal high in the manner described above, and completing the read access. 
     Refresh Access 
     In the second half of clock cycle T 1 , the low state of the CLK signal causes AND gate  103  to provide a logic low signal to the control terminal of multiplexer  102 . In response, multiplexer  102  routes the refresh address RFA[10:0] to memory array  101  as the RBA[10:0] signal. In response, decoders (not shown) identify an addressed bank and an addressed row of the present refresh access. 
     Within memory array sequencer  122 , the low state of the CLK signal and the high state of the RREQ signal cause the RAS# signal to be activated low in the manner described above. 
     The low state of the RAS# signal propagates through delay line  301 , thereby causing the SEN# signal to be activated low after a delay of d 1 . The low state of the SEN# signal propagates through delay line  302 , with a delay of d 2 , and then through delay line  303 , with a delay of d 3 , thereby causing the PRC# signal to be activated low after a delay of d 2  plus d 3 . Note that the logic low CLK signal prevents OR gate  317  from activating a logic low CAS# signal, as column access is not required during a refresh operation. In this manner, the RAS#, SEN# and PRC# signals are sequentially activated low. 
     The logic low RAS# signal causes the data in the addressed row of the addressed bank (as specified by RFA[10:0] to be driven to the sense amplifiers of the addressed bank. The logic low SEN# signal causes this row of data to be latched in the sense amplifiers of the addressed bank. The sense amplifiers resolve the data values to a full signal swing, thereby refreshing the data from the addressed row. 
     Within memory array sequencer  122 , the low state of the PRC# signal causes the RAS# and SEN# signals to be deactivated high in the manner described above. Within memory array  101 , the low state of the PRC# signal turns off the word line of the addressed row in the addressed bank, turns off the sense amplifiers in the addressed bank, and precharges the bit lines of the addressed bank, thereby preparing DRAM array  101  for the next operation. After a delay of d 4 , the PRC# signal is deactivated high, thereby completing the refresh access. 
     Write Access 
     The external accessing client provides a low ADS# signal, a high WR# signal, a write data value DIN[31:0] and an external address signal EA[14:0] before the rising edge of clock cycle T 2 . The high WR# signal specifies a write operation, and the external address signal EA[14:0] specifies the write address within DRAM array  101 . At the rising clock-edge of cycle T 2 , the ADS#, WR# and EA[14:0] signals are latched into input signal registers  120 , and provided as the LADS#, LWR# and LEA[14:0] signals, respectively. In addition, the write data value DIN[31:0] is latched into write data buffer  80 . 
     The logic low LADS# signal and the logic high CLK signal cause AND gate  103  (FIG. 1) to provide a logic high control signal to multiplexer  102 . In response, multiplexer  102  routes the bank/row information of the latched address LEA[10:0] to DRAM array  101  as the RBA[10:0] signal. The column information of the latched address LEA[14:11] is also provided to memory array  101 . In response, decoders (not shown) identify an addressed bank, an addressed row and an addressed set of columns of the present write access. 
     Within refresh controller  121 , the modulo-64 counter  201  is incremented to a zero count in response to the rising edge of the CLK signal, thereby causing the refresh request signal RREQ to be deactivated low. 
     The logic low LADS# signal and the logic low RREQ signal are provided to memory array sequencer  122  (FIG.  3 ). The low state of the LADS# signal and the high state of the CLK signal cause the RAS#, SEN#, CAS# and PRC# signals to be sequentially activated low in the manner described above. 
     The logic low RAS# signal causes the data in the addressed row of the addressed bank (as specified by LEA[10:0]) to be driven to the sense amplifiers of the addressed bank. The logic low SEN# signal causes this row of data to be latched in the sense amplifiers of the addressed bank. The logic low CAS# signal causes the sense amplifiers corresponding with the addressed set of columns (as specified by LEA[14:11]) to be coupled to write data buffer  80 , thereby overwriting the data in the sense amplifiers corresponding with the addressed set of columns with the write data value DIN[31:0]. These sense amplifiers, in turn, couple the write data value to the corresponding memory cells in the addressed row. 
     Within memory array sequencer  122 , the low state of the PRC# signal causes the RAS#, SEN# and CAS# signals to be deactivated high in the manner described above. Within DRAM array  101 , the low state of the PRC# signal turns off the word line of the addressed row in the addressed bank, turns off the sense amplifiers in the addressed bank, and precharges the bit lines of the addressed bank, thereby preparing memory array  101  for the next operation. After a delay of d 4 , the PRC# signal is deactivated high, thereby completing the write access. 
     In the foregoing manner, 1-T SRAM system  100  implements refresh accesses without interfering with external accesses, and without requiring an external refresh indicator signal. In the embodiment described above, the RAS#, SEN#, CAS# and PRC# signals are only activated when an external access or refresh operation is being performed. This results in power savings in 1-T SRAM system  100 . 
     Alternate Embodiment 
     In the embodiment described above, the external accesses are performed during one half of the clock period (i.e., when the CLK signal is high), and the refresh operations are performed during the other half of the clock period (i.e., when the CLK signal is low). Operation of 1T SRAM system  100  therefore depends on both the high period and the low period of the CLK signal. Consequently, the operation and performance of 1-T SRAM system  100  is affected by the duty-cycle of the external clock signal CLK. Because a refresh access does not involve a column access operation, the memory cycle time for a refresh access is shorter than the memory cycle time for an external access. Consequently, 1-T SRAM system  100  would be capable of operating at higher clock frequencies if the memory cycle time of refresh accesses is optimized. In general, the shortest possible clock period (i.e., the highest possible clock frequency) exists when the clock period is equal to memory cycle time of an external access plus the memory cycle time of a refresh access. It is therefore desirable to have a memory system that operates independent of the clock duty-cycle, such that the memory system can operate in response to the shortest possible clock period. 
     FIG. 5 is a circuit diagram of memory array sequencer  500 , which is used in another embodiment of the present invention. In this embodiment, memory array sequencer  500  replaces memory array sequencer  122  (FIGS. 1,  3 ). The construct of the other functional blocks of memory system  100  remains the same. As described in more detail below, memory array sequencer  500  enables memory system  100  to operate independent of the duty-cycle of the CLK signal. 
     Memory array sequencer  500  includes delay lines  501 - 505 , OR gates  511 - 520 , AND gates  521 - 523 , one-shot circuits  531 - 533 , and flip-flops  551 - 554 , which include cross-coupled NAND gate pairs  541 - 542 ,  543 - 544 ,  545 - 546  and  547 - 548 , respectively. In general, delay lines  501 - 503  introduce the same signal delays (d 1 , d 2 , d 3 ) as delay lines  301 - 303 , respectively. Delay lines  504  and  505  introduce the same delays (d 1 , d 3 ) as delay lines  501  and  503 , respectively. Delay lines  501 - 503  serve two functions. First, during an external (read/write) access, delay lines  501 - 503  generate the timing control for the memory access operations. That is, delay lines  501 - 503  control the timing of the SEN#, CAS# and PRC# signals during an external access cycle. Second, delay lines  501 - 503  control the timing of the beginning of a refresh period. Delay lines  504  and  505  generate the timing control for the refresh access operations. That is, delay lines  504 - 505  control the timing of the SEN# and PRC# signals during a memory refresh cycle. External access timing control signals aRAS#, aSEN#, aPRC# and their counterpart refresh timing control signals rRAS#, rSEN# and rPRC# are logically AND&#39;ed to form the array control timing signals RAS#, SEN#. and PRC#, respectively. The CAS# signal, which controls the column operation of the array, is activated only during external access cycles. 
     Initial Generation of aRAS#, aSEN#, CAS#, aPRC# 
     FIG. 6 is a waveform diagram illustrating the operation of 1-T SRAM system  100  when using memory array sequencer  500 . During the first clock cycle T 1 , there are no external accesses or refresh accesses pending in the memory system. During the second clock cycle T 2 , both a read access and a refresh access are pending. Although a write access is not specifically described in FIG. 6, it is understood that memory array sequencer  500  generates the same signals during read and write accesses. 
     The first clock cycle T 1  is representative of the state of memory array sequencer  500  after memory system  100  has been initialized (although it is understood that a refresh request would not be generated the cycle after initialization). When 1-T SRAM system  100  is started, the RST# signal is activated low, thereby setting flip-flops  551 - 554 , such that these flip-flops provide logic high output signals. During clock cycle T 1 , there is no external access or refresh access to system  100 , so the latched address strobe signal LADS# is de-activated high and the refresh request signal RREQ is de-activated low. As a result, OR gates  511  and  512  provide logic high signals to one-shot circuits  532  and  533 , respectively. In response, one-shot circuits  532 - 533  provide logic high signals to flip-flops  552 - 553 , respectively, thereby causing flip-flops  552 - 553  to continue to provide logic high output signals. The output signal of flip-flop  552  is referred to as the aRAS# signal. As described below, the aRAS# signal is used to activate the RAS# signal during an external access. The logic high aRAS# signal is provided to AND gate  521 . 
     The logic high LADS# signal causes OR gates  518 - 520  to provide logic high output signals aSEN#, CAS# and aPRC#, respectively. The aSEN# and aPRC# signals are used to activate the SEN# and PRC# signals during an external access. The CAS# signal always corresponds with an external access (because the CAS# signal is not required during a refresh access). The logic high aSEN# and aPRC# signals are provided to AND gates  522  and  523 , respectively. 
     Initial Generation of rRAS#, rSEN#, rPRC# 
     The logic high output signal of flip-flops  553  and  554  cause OR gate  513  to provide a logic high signal to OR gate  516 . In response, OR gate  516  provides a logic high output signal. The output signal of OR gate  516  is referred to as the rRAS# signal. As described below, the rRAS# signal is used to activate the RAS# signal during a refresh access. The logic high rRAS# signal is provided to AND gate  521 . Because both the aRAS# and rRAS# signals initially have logic high values, AND gate  521  initially provides a logic high (deactivated) RAS# signal. 
     The logic high rRAS# signal is routed through delay line  504  to OR gate  517 , thereby causing OR gate  517  to provide a logic high rSEN# signal. The rSEN# signal is used to activate the SEN# signal during a refresh access. The logic high rSEN# signal is provided to AND gate  522 . Because both the aSEN# and rSEN# signals initially have logic high values, AND gate  522  initially provides a logic high (deactivated) SEN# signal. 
     The logic high rSEN# signal is routed through delay line  505  to provide a logic high rPRC# signal. The rPRC# signal is used to activate the PRC# signal during a refresh access. The logic high rPRC# signal is provided to AND gate  523 . Because both the aPRC# and rPRC# signals initially have logic high values, AND gate  523  initially provides a logic high (de-activated) PRC# signal. 
     Generation of aS#, C# and aP# 
     Initially, flip-flop  551  provides a logic high output signal to delay line  501 . This logic high output signal propagates through delay line  501  to OR gate  514 . In response, OR gate  514  provides a logic high aS# signal. As described below, the aS# signal is used to activate the aSEN# signal. 
     The logic high aS# signal propagates through delay line  501  to OR gate  515 . In response, OR gate  515  provides a logic high C# signal. As described below, the C# signal is used to activate the CAS# signal. 
     The logic high C# signal propagates through delay line  503 , thereby providing a logic high aP# signal. As described below, the aP# signal is used to activate the aPRC# signal, and to signal the start of a refresh access. 
     At the rising edge of each clock cycle, including clock cycle T 1 , one-shot circuit  531  is activated, such that one-shot circuit  531  generates a negative going pulse having a duration substantially shorter than one half the CLK period. This negative pulse resets the output of flip-flop  551  to a logic low value. The logic low value provided by flip-flop  551  propagates through delay line  501 , with delay d 1 , to OR gate  514 . In response, OR gate  514  provides a logic low aS# signal. 
     The logic low aS# signal propagates through delay line  502 , with delay d 2 , to OR gate  515 . In response, OR gate  515  provides a logic low C# signal. 
     The logic low C# signal propagates through delay line  503 , with delay d 3 , thereby providing a logic low aP# signal. The logic low aP# signal causes the aS# and C# signals to transition to logic high states (through OR gates  514  and  515 , respectively). The logic low aP# signal also returns (sets) the output of flip-flop  551  to a logic high state. The logic high C# signal propagates through delay line  503 , with delay d 3 , thereby causing the aP# signal to transition back to a logic high state. Note that the aS#, C# and aP# signals are generated in this sequence during every cycle of the CLK signal, regardless of the states of the LADS# or RREQ signals. That is, the aS#, C# and aP# signals are generated in this sequence whether or not there is an external access and/or refresh access pending in memory system  100 . 
     External Access 
     The external accessing client provides a low ADS# signal, a low WR# signal and an external address signal EA[14:0] before the rising edge of clock cycle T 2 . The low WR# signal specifies a read operation, and the external address signal EA[14:0] specifies the read address within array  101 . At the rising clock-edge of cycle T 2 , the ADS#, WR# and EA[14:0] signals are latched into input signal registers  120 , and provided as the LADS#, LWR# and LEA[14:0] signals, respectively. The functionality of the WR#, LWR#, EA[14:0] and LEA[14:0] signals has been described above in connection with FIGS. 1-4. Because these signals are not relevant to the operation of memory array sequencer  500 , these signals are not discussed further in the present example. 
     Within refresh controller  121 , the rising clock-edge of cycle T 2  increments modulo-64 counter  201  to a full count thereby causing the refresh request signal RREQ to be activated high. The high state of the RREQ signal increments 11-bit binary counter by one count, such that the refresh address RFA[10:0] has a value represented by “FA”. Because the functionality of the refresh address RFA[10:0] has been described above, this description is not repeated in the present example. 
     As described above, the LADS# signal is activated low at the rising edge of clock cycle T 2 . The low state of the LADS# signal, along with the high state of the CLK signal causes the output of OR gate  511  to go low. The falling edge at the output of OR gate  511  causes one-shot circuit  532  to generate a negative going pulse having a width substantially shorter than half of the CLK period. This negative pulse resets the output of flip-flop  552  (i.e., the aRAS# signal) to a logic low value. This logic low aRAS# signal causes AND gate  521  to activate the RAS# signal low. 
     The rising edge of clock cycle T 2  also causes one-shot circuit  551  to generate a negative going pulse having a width substantially shorter than half of the CLK period. This negative pulse resets the output of flip-flop  551  to a logic low value. This logic low value propagates through delay lines  501 ,  502  and  503 , thereby sequentially activating and deactivating the aS#, C# and aP# signals in the manner described above for clock cycle T 1 . Because the LADS# signal has a logic low value at this time, OR gates  518 ,  519  and  520  effectively pass the aS#, C# and aP# signals as the aSEN#, CAS# and aPRC# signals, respectively. In addition, AND gates  522  and  523  effectively pass the aSEN# and aPRC# signals as the SEN# and PRC# signals, respectively. When the aP# signal is activated low, flip-flop  552  is set, thereby de-activating the aRAS# signal high. In response, to the high aRAS# signal, AND gate  522  deactivates the RAS# signal high. The read access is performed in response to the sequentially activated and deactivated RAS#, SEN#, CAS# and PRC# signals. As described in more detail below, the aP# signal is used to coordinate the timing of the refresh access. 
     Refresh Access 
     Turning now to the refresh access, the rising edge of clock cycle T 2  (along with the logic high RREQ signal) causes OR gate  512  to provide a logic low signal to one-shot circuit  533 . In response, one-shot circuit  553  generates a negative going pulse having a width substantially shorter than half of the CLK period. This negative pulse resets the output of flip-flop  553  to a logic low value, which is provided to OR gate  513 . However, because flip-flop  554  provides a logic high signal to OR gate  513 , this OR gate continues to provide a logic high output signal. As a result, the rRAS# signal remains deactivated high. 
     The aP# signal is applied to an input terminal of flip-flop  554 . When the aP# signal is activated low, flip-flop  554  is reset, thereby causing this flip-flop  554  to provide a logic low output signal to OR gate  513 . However, because an inverting input terminal of OR gate  513  is coupled to receive the aP# signal, OR gate  513  continues to provide a logic high output signal at this time. As a result, the rRAS# signal remains deactivated high. 
     As described above, the aP# signal is deactivated high after a delay of d 3 . However, this transition of the aP# signal does not change the output signal of flip-flop  554 . As a result, OR gate  513  provides a logic low output signal in response to the rising edge of the aP# signal. The logic low output signal of OR gate  513  is provided to OR gate  516 . In response, OR gate  516  activates the rRAS# signal low. This logic low rRAS# signal is effectively routed through AND gate  521 , thereby providing a logic low RAS# signal for the refresh access. In this manner, the RAS# signal of the refresh access is activated in response to the deactivated aP# signal. Stated another way, the refresh access is automatically initiated at the conclusion of the external (read) access. This advantageously allows the external access and the refresh access to be implemented in the shortest possible time. 
     The logic low rRAS# signal propagates through delay line  504  (with delay d 2 ) to OR gate  517 . In response, OR gate  517  activates the rSEN# signal low. This logic low rSEN# signal is effectively routed through AND gate  522 , thereby providing a logic low SEN# signal for the refresh access. 
     The logic low rSEN# signal propagates through delay line  505  (with delay d 3 ), thereby activating the rPRC# signal low. This logic low rPRC# signal is effectively routed through AND gate  523 , thereby providing a logic low PRC# signal for the refresh access. 
     The logic low rPRC# signal causes the rRAS# and rSEN# signals to be deactivated high (through OR gates  516  and  517 , respectively). The logic low rPRC# signal is also applied to input terminals of flip-flops  553  and  554 , thereby setting the output signals of these flip-flops to logic high values, and preparing these flip-flops for the next refresh access. The logic high deactivated rSEN# propagates through delay line  505 , thereby deactivating the rPRC# signal high after delay d 2 . At this time, memory array sequencer  500  has been returned to its initial state, and is ready for the next clock cycle. 
     Notice that if a refresh access were not pending in clock cycle T 2 , the RREQ signal would not be activated high. As a result, one-shot  533  would not be activated, and flip-flop  533  would continue to provide a logic high output signal to OR gate  513 . Under these conditions, the rRAS#, rSEN# and rPRC# signals would not be activated low during this cycle, and the RAS#, SEN# and PRC# would not be activated for a second time during this cycle. That is, a refresh access will not be performed if a refresh access is not pending. 
     Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. For example, although the read/write accesses have been described as occurring during the first half of a clock cycle, and the refresh operations have been described as occurring during the second half of a clock cycle, it is understood that this order may be reversed in other embodiments. The manner of performing this reversal would be apparent to one of ordinary skill in the art. Furthermore, although the refresh operations have been described as no activating the CAS# signal, it is understood that the CAS# signal may be activated during refresh operations in other embodiments. Moreover, although the above-described memory array sequencers are initially reset by the RST# signal, it is understood that these memory array sequencers are capable of resetting themselves in the absence of the RST# signal. For example, the DRAM memory banks can have different sizes in different embodiments. Similarly, different numbers of DRAM banks can be used. Moreover, buses having different widths than those described can be used in other embodiments. In addition, different logic can be used to provide the same results. Thus, the invention is limited only by the following claims.