Abstract:
Method and apparatus for use with internal array voltage generators in semiconductor memory devices are disclosed. In one described embodiment, an overdriving level control circuit is used to generate an overdriving control signal for an internal array voltage generator driver, just prior to a sensing operation. The overdriving level control circuit uses a cell modeling circuit to estimate, just prior to the sensing operation, a current requirement for the sensing operation, and an amplifier to generate the overdriving control signal in response to the estimated current requirement. Such a design allows the amount of overdrive signal to track process, voltage, and temperature changes, for example, to provide an accurate overdrive that allows the internal array voltage to remain stable. Other embodiments are described and claimed.

Description:
RELATED APPLICATIONS 
     This application claims the benefit of priority to Korean Patent Application P2004-46774, filed Jun. 22, 2004, the disclosure of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to dynamic random access memory (DRAM) semiconductor devices and systems, and more particularly to methods and apparatus for generating an internal array voltage. 
     2. Description of the Related Art 
     Semiconductor memory devices, such as DRAM devices, require several different voltages for proper operation. One of these voltages is an internal array voltage, different than the voltage of externally supplied power, which is used by the memory cell array sensing circuitry during memory operations. 
       FIG. 1  shows a portion of a typical prior art semiconductor memory device  100 , including a memory cell array  10 , a control circuit  20 , a standby internal voltage generator  30 , and an active internal voltage generator  40 . The two voltage generators work together to supply an internal array voltage VINTA to memory cell array  10 , from an external power supply maintained at an external voltage VEXT. 
     Standby internal voltage generator  30  operates in both standby and active modes. A standby driving signal generator  32  within voltage generator  30  generates a first analog control signal scon to a driver  34 , which drives VINTA. Standby driving signal generator  32  receives feedback on the level of VINTA, and adjusts scon as needed to keep VINTA at a reference voltage. 
     Active internal voltage generator  40  only operates in the active mode, in response to a signal act from control circuit  20 . When act is enabled, an active driving signal generator  42 , with function similar to standby driving signal generator  32 , is activated. Once activated, active driving signal generator  42  generates a second analog control signal acon to a second driver  44  within voltage generator  40 , which also drives VINTA. The combined driving capability of drivers  34  and  44  is therefore available to supply current during a sensing operation of the active mode. 
       FIG. 2  contains a timing diagram that illustrates a typical active mode operation of device  100 . When an active command signal ACT is received by control circuit  20 , an active control signal act is asserted. Initially, the internal array voltage VINTA may be slightly overdriven above its steady state voltage level A as active internal voltage generator  40  is activated. 
     Shortly after asserting act, control circuit  20  asserts a sense amplifier enable signal SEN to memory cell array  10 , causing memory cell array  10  to initiate a sensing operation. The sensing operation requires numerous bit lines to be charged rapidly to the internal array voltage VINTA. The current consumed during the initial stages of the sensing operation is significant, causing the internal array voltage VINTA to dip to a voltage level B before recovering to its steady-state value A. If the voltage dip during the sensing operation is not controlled and minimized, the memory device may not work correctly. 
       FIG. 3  shows a portion of a second prior art semiconductor memory device  200 , which attempts to overcome the voltage dip problem of memory device  100  by the addition of an overdriving circuit  50 . A control circuit  20 ′ operates similar to control circuit  20 , but also supplies an overdriving control signal Pact to the overdriving circuit  50 . When overdriving circuit  50  receives Pact, it produces an overdriving signal acon′ to second driver  44 . 
     Referring to the timing diagram shown in  FIG. 4 , Pact is briefly pulsed prior to the activation of sense amplifier enable signal SEN to memory cell array  10 . During this pulse, overdriving circuit  50  forces driver  44  to overdrive VINTA to a voltage C when the external voltage VEXT maintains an appropriate voltage level. Voltage C is designed to be just high enough that during the high-current portion of the sensing operation the internal array voltage VINTA, which is controlled during the sensing operation in conventional fashion by standby and active driving signal generators  32  and  42 , will drop back to A, and not below A as in  FIG. 2 . However, when the external voltage (VEXT) is set to too high of a voltage level, the internal array voltage VINTA may be overdriven to a voltage level D. In this case, the voltage level D will drop back to E after the high-current portion of the sensing operation, causing the memory device to not work correctly. 
     SUMMARY OF THE INVENTION 
     Several problems have now been recognized with the generation of an internal array voltage in accordance with  FIGS. 3 and 4 . First, as shown in  FIG. 4 , when the overdrive voltage is poorly estimated, for instance to level D, the current consumed during the sensing operation may not be sufficient to drop the internal array voltage back to the desired level A. The internal array voltage remains at an elevated voltage E, which can result in unstable device operation. Also, if the overdrive voltage is estimated too low, a situation such as illustrated in  FIG. 2  can still occur. Such problems can occur, for example, if the external voltage VEXT is poorly controlled. Also, the control circuit  20 ′ is affected by process, voltage, and temperature (PVT) conditions, which can vary the pulse width of the Pact pulse, causing variations in the overdrive voltage. 
     The present disclosure describes what is believed to be an internal array voltage generation method, and circuitry, capable of producing a more accurate overdriving signal. In one embodiment, a memory device comprises an overdriving level control circuit having a cell modeling circuit that estimates a charge or current requirement for a sensing operation, and an amplifier to generate a driver control signal in response to the charge or current requirement. Because the cell modeling circuit is generally subjected to the same PVT variations as the actual memory cell array and models the current consumption or charge consumption of the sensing operation, the overdriving level control circuit is believed to provide a more accurate internal array voltage overdrive. 
     In a further embodiment, a memory device is disclosed that comprises a memory cell array, a plurality of sense amplifiers coupled to the memory cell array to sense data stored in the memory cell array, an internal array voltage generator to supply an internal array voltage to at least the sense amplifiers comprising, a first driver to supply power for use by at least the sense amplifiers during a sensing operation. The memory device also comprises a modeling circuit having a reference capacitor and switched circuitry to change the voltage on the reference capacitor from a first voltage level towards a second voltage level prior to the sensing operation. The modeling circuit outputs a sense modeling signal, related to the changing reference capacitor voltage, to an amplifier. The amplifier supplies an analog control signal based on the sense modeling signal to the first driver to increase the internal array voltage before beginning the sensing operation. The reference capacitor may be, for example, a simple capacitor with switching circuitry to charge it from a bit line pre-charge voltage towards an internal array voltage. In other embodiments, the reference capacitor may take the form of a model memory cell, model bit lines, a model sense amplifier, and other circuitry as appears in the sensing path of a memory cell in the memory cell array. 
     In another aspect of the disclosure, a method of operating a memory device is disclosed. The method comprises receiving an active mode command to access the memory cell array on the memory device. In response to the active mode command, a modeling circuit is activated on the memory device to estimate a signal proportional to an amount of charge to be consumed during a sensing operation in response to the active mode command. An internal array voltage is overdriven responsive to the estimated signal. Subsequent to initiation of overdriving the internal array voltage, data stored on the memory device is sensed during a sensing operation that draws current from an internal array voltage generator coupled to the internal array voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates some elements of a prior art memory device, including circuitry used to generate an internal array voltage; 
         FIG. 2  contains a timing diagram illustrating a prior art method of controlling an internal array voltage with the device of  FIG. 1 ; 
         FIG. 3  illustrates some elements of a second prior art memory device, including circuitry used to generate and overdrive an internal array voltage; 
         FIG. 4  contains a timing diagram illustrating a prior art method of controlling an internal array voltage with the device of  FIG. 3 ; 
         FIG. 5  illustrates prior art circuit details for a section of a memory cell array; 
         FIG. 6  illustrates timing for a sensing operation in the memory cell array of claim  5 ; 
         FIG. 7  illustrates some elements of a memory device including circuitry used to generate an internal array voltage and overdrive the level of the internal array voltage; 
         FIG. 8  contains a block diagram for an overdriving level control circuit useful in the  FIG. 7  memory device; 
         FIG. 9  contains a timing diagram illustrating controlling and overdriving the level of an internal array voltage with the device of  FIGS. 7 and 8 ; 
         FIGS. 10 and 11  illustrate modeling circuit embodiments modeling a sense amplifier, bit line pair, and memory cell; 
         FIG. 12  illustrates a modeling circuit embodiment using a capacitor driven from a bit line precharge voltage toward an internal array voltage; 
         FIG. 13  illustrates an amplifier embodiment useful in the overdriving level control circuit of  FIG. 7 ; 
         FIG. 14  illustrates an internal voltage generator useful with some embodiments; 
         FIG. 15  depicts some elements of a memory device including a separate overdriving driver to overdrive the level of the internal array voltage; and 
         FIG. 16  shows one embodiment of the separate overdriving driver. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     As an introduction to the embodiments,  FIGS. 5 and 6  show respectively, the arrangement of a memory cell array and the timing of a sensing operation.  FIG. 5  shows that memory cell array  10  is divided into memory cell array blocks BK 1 , BK 2 , . . . , BKn that are repeated across the array. Each memory cell array block comprises a plurality of memory cells, two of which (MC 1  and MC 2 ) are shown in blocks BK 1  and BK 2 , respectively. Taking MC 1  as exemplary, MC 1  is selected and coupled to a bit line ABL 1  by a word line select signal on word line WL 1 . In a memory device that stores one information bit per memory cell, MC 1  indicates whether the information bit is a logic “0” or “1”, respectively, by the absence or appearance of a charge on a memory cell capacitor. 
     Although not illustrated, it is understood that multiple memory cells are arranged in block BK 1  along the common bit line ABL 1 , each connectable to ABL 1  by application of a word line select signal to a corresponding word line. A reference bit line ABL 1 B runs parallel to bit line ABL 1 , but does not connect to the memory cells. 
     A precharge circuit PREC 1  is coupled between bit line ABL and reference bit line ABL 1 B. The precharge circuit comprises three n-channel MOSFET transistors N 1 , N 2 , and N 3  controlled by a precharge signal PRE. Precharge signal PRE is activated when no word line select signal is active, to precharge bit lines ABL 1  and ABL 1 B to a bit line voltage VBL, which is a voltage halfway between an internal array voltage VINTA and an internal array ground voltage VSSA. Transistor N 1  couples ABL 1  and ABL 1 B together when PRE is activated, equalizing the voltage on each. Transistors N 2  and N 3  couple ABL 1  and ABL 1 B, respectively, to the bit line voltage VBL when PRE is activated. 
     A similar arrangement to the block BK 1  arrangement exists for block BK 2 , including a common bit line ABL 2 , a reference bit line ABL 2 B, and a second precharge circuit PREC 2 . 
     The two blocks BK 1  and BK 2  share a bit line sense amplifier SAC. To provide better sensing capability, BK 1  and BK 2  are coupled to sense amplifier SAC through two isolation circuits ISOG 1  and ISOG 2 , respectively. Each isolation circuit comprises two n-channel MOSFET transistors N 4  and N 5 , coupled respectively between a memory cell array bit line and a corresponding sensing bit line and between a memory cell array reference bit line and a corresponding sensing bit line. When the charge stored in a BK 1  memory cell is to be sensed, isolation circuit ISOG 1  is enabled by a first isolation signal ISO 1 , while a second isolation signal ISO 2  keeps isolation circuit ISOG 2  disabled. 
     Bit line sense amplifier SAC comprises two sensing bit lines SBL and SBLB that are coupled to bit lines ABL 1  and ABL 1 B, respectively, when isolation circuit ISOG 1  is enabled. Sense amplifier SAC contains a serial pair of p-channel MOSFET transistors P 1  and P 2  coupled between SBL and SBLB, with the gate of P 1  connected to SBLB and the gate of P 2  connected to SBL. A sense amplifier enable signal LA, which is connected to the internal array voltage VINTA during a sensing operation, is coupled between P 1  and P 2 . Sense amplifier SAC also contains a serial pair of n-channel MOSFET transistors N 6  and N 7  coupled between SBL and SBLB, with the gate of N 6  connected to SBLB and the gate of N 7  connected to SBL. A complimentary sense amplifier enable signal LAB, which is connected to the internal array ground voltage VSSA during a sensing operation, is coupled between N 6  and N 7 . 
     A data input/output gate IOG, comprising two n-channel MOSFET transistors N 8  and N 9 , selectively couples sensing bit lines SBL and SBLB, respectively, to two input/output lines IO, IOB, in response to a select signal on a column select line CSL. 
     The well-known peripheral circuits necessary to generate the various control signals shown in  FIG. 5  are not illustrated. Such peripheral circuits generally include a row decoder to select a word line and isolation signals, a column decoder to select a column select line, and other timing/switching components to generate appropriate signals on the other illustrated signal lines. An internal array power distribution subsystem distributes VINTA and VSSA to the appropriate sense amplifiers for each sensing operation. 
       FIG. 6  illustrates relative timing for a sensing operation that accesses memory cell MC 1  in  FIG. 5 . Prior to the receipt of an active mode command ACT, PRE is active, such that bit lines ABL 1  and ABL 1 B are precharged to VBL. Sensing bit lines SBL and SBLB are also precharged to VBL by setting sense amplifier enable signals LA and LAB to VBL. 
     Upon receipt of the active mode command ACT, ISO 1  is asserted to couple precharged bit lines ABL 1  and ABL 1 B to precharged sensing bit lines SBL and SBLB, and word line WL 1  is energized to couple MC 1  to bit line ABL 1 . When MC 1  and ABL 1  are coupled, the voltage on ABL 1  is altered according to a charge-sharing operation between the memory cell MC 1  capacitor and the distributed capacitance of the bit line. Thus when the memory cell stores logic “1” as a voltage greater than VBL, the charge sharing operation increases the bit line voltage by an incremental voltage +ΔV. When the memory cell stores logic “0” as a voltage less than VBL, the charge sharing operation decreases the bit line voltage by an incremental voltage −ΔV. 
     Once the charge-sharing operation has stabilized, bit line sense amplifier SAC is activated by a sensing operation control signal SEN. Control signal SEN causes sense amplifier enable signal LA to supply the internal array voltage VINTA to p-channel transistors P 1  and P 2 , and causes complimentary sense amplifier enable signal LAB to supply the internal array ground voltage VSSA to n-channel transistors N 6  and N 7 . Thus when SEN is activated with SBL slightly more positive than SBLB, transistor P 1  presents a lower resistance path to VINTA than transistor P 2 , and transistor N 7  presents a lower resistance path to VSSA than transistor N 6 , causing the sense amplifier to rapidly drive SBL to VINTA and sink SBLB to VSSA. When SEN is activated with SBL slightly more negative than SBLB, a similar analysis causes a reverse effect, with the sense amplifier rapidly sinking SBL to VSSA and driving SBLB to VINTA. 
     Whichever way sense amplifier SAC is driven, significant current is drawn from the VINTA voltage generator to charge one of the bit lines from VBL, or VBL +ΔV, to VINTA. In most memory devices, multiple sense amplifiers are operated together, which multiplies the current needs of the memory cell array during a sensing operation. An understanding of these concepts will aid an understanding of the embodiments that will now be presented. 
       FIG. 7  illustrates a semiconductor memory device  300 , including a memory cell array  10 , a control circuit  20 ′, a standby internal voltage generation circuit  30 , an active internal voltage generation circuit  40 , and an overdriving level control circuit  60 . Standby internal voltage generation circuit  30  operates similar to the same circuit in  FIGS. 1 and 3  to provide an internal array voltage VINTA to the memory cell array in active and standby modes. Active internal voltage generation circuit  40  operates similar to the same circuit in  FIG. 3  to supplement the internal array voltage VINTA generation in an active mode, with the difference that driver  44  receives an analog control signal acon″ from overdriving level control circuit  60 . 
     Referring now to  FIG. 8 , overdriving level control circuit  60  comprises a cell modeling circuit  70  and an amplifier  72 . Cell modeling circuit  70  receives an overdriving control signal Pact, and generates a signal out that estimates an amount of charge or current to be consumed by the memory cell array during a sensing operation at array internal voltage VINTA. For instance, the signal out may estimate a current or voltage proportional to a rate of charge consumption from VINTA during a sensing operation, or estimate a current or voltage that, when integrated, is proportional to the charge consumed from VINTA during a sensing operation. Amplifier  72  receives the signal out, and amplifies it appropriately to provide analog control signal acon″ to a VINTA driver. 
       FIG. 9  shows the intended timing of the overdriving level control circuit output for one embodiment. In response to an active mode command ACT, control circuit  20 ′ generates an overdriving control signal Pact to overdriving level control circuit  60 . Signal Pact activates the cell modeling circuit  70 , which drives amplifier  72 , and consequently driver  44 , to raise internal array voltage according to the model. Active driving signal generator  42  is enabled by an active control signal act prior to the activation of sensing operation control signal SEN. Overdriving control signal Pact is disabled at approximately the same time that control signal SEN is activated (in various embodiments, Pact can be designed to be disabled shortly before, concurrently with, or shortly after the activation of control signal SEN). With an accurate modeling operation, the excess voltage added to VINTA during the modeling circuit activation is consumed as the memory cell array sense amplifiers draw current to charge bit lines to VINTA, returning VINTA at or near its intended voltage A. 
     Embodiments of cell modeling circuit  70  and amplifier  72  will now be described in detail. A first embodiment of cell modeling circuit  70  is illustrated in  FIG. 10 . 
     Modeling circuit  70  comprises, in part, a model memory cell MMC, a model precharge circuit MPREC, two model isolation gates MISOG 1  and MISOG 2 , model array bit lines MABL and MABLB, and a model bit line sense amplifier MSAC. Other circuitry peripheral to these elements is included as well, and will be described as the operation of modeling circuit  70  proceeds. 
     The model memory cell MMC is similar in some respects to a memory cell in the memory cell array: it comprises a capacitor C that can be coupled to a bit line (MABL) when an n-channel MOSFET pass transistor N is enabled. Pass transistor N is enabled by overdriving control signal Pact, causing a charge sharing operation between capacitor C and bit line MABL. 
     The overdriving control signal Pact is also supplied to an inverter I, the output of which is supplied as an enable signal to the gates of three n-channel MOSFET transistors MN 1 , MN 2 , and MN 3  in model precharge circuit MPREC. The three transistors MN 1 , MN 2 , and MN 3  are configured like the transistors N 1 , N 2 , and N 3  in  FIG. 5 , such that except when overdriving control signal Pact is asserted, model precharge circuit MPREC precharges model bit lines MABL and MABLB to bit line precharge voltage VBL. 
     Model isolation gates MISOG 1  and MISOG 2  are functionally similar to isolation gates IS 01  and IS 02  in  FIG. 5 . Instead of being driven by isolation signals, however, the gates of the pass transistors in model isolation gate MISOG 1  are permanently tied to a boosting voltage Vpp which has higher level than that of the external voltage VEXT, such that model isolation gate MISOG 1  is permanently enabled. Similarly, the gates of the pass transistors in model isolation gate MISOG 2  are permanently tied to the internal array ground voltage VSSA, such that model isolation gate MISOG 2  is permanently disabled. Since model isolation gate MISOG 2  is permanently disabled, no bit line precharge circuitry or memory cells are provided to the end of MISOG 2  opposite the model bit line sense amplifier MSAC. Instead, MISOG 2  is simply coupled to the bit line precharge voltage VBL. 
     As model isolation gate MISOG 1  is permanently enabled, model sensing bit lines MSBL and MSBLB in model sense amplifier MSAC are permanently coupled, respectively, to model bit lines MABL and MABLB. Thus the precharging operation on MABL and MABLB also precharges MSBL and MSBLB to the bit line precharge voltage VBL. 
     Like bit line sense amplifier SAC in  FIG. 5 , model bit line sense amplifier comprises two p-channel MOSFET transistors (MP 1  and MP 2 ) and two n-channel MOSFET transistors (MN 6  and MN 7 ) coupled between model sensing bit lines MSBL and MSBLB. When activated, model bit line sense amplifier MSAC thus functions like sense amplifier SAC in  FIG. 5  to amplify a voltage difference between MSBL and MSBLB. 
     Activation of model bit line sense amplifier MSAC occurs in response to overdriving control signal Pact. When Pact is enabled, Pact drives the gate of an n-channel MOSFET transistor MN 8  to couple one side of transistors MN 6  and MN 7  to VSSA. Also when Pact is enabled, the output of inverter I (the logical inverse of overdriving control signal Pact) drives the gate of a p-channel MOSFET transistor MP 3  to couple one side of transistors MP 1  and MP 2  to VINTA. 
     An additional n-channel MOSFET transistor MN 9  can also be included in cell modeling circuit  70 . The gate of MN 9  is driven by a control signal pup that is momentarily driven to a logic high condition during the device startup sequence. When pup is driven high, MN 9  couples capacitor C to internal array ground voltage VSSA, thus draining any charge off of capacitor C. This effectively presets model memory cell MMC to a known logic “0” memory condition. 
     With the preceding component description, the operation of cell modeling circuit  70  in response to an active mode command ACT can now be described. The assertion of Pact turns off model precharge circuit MPREC and initiates a charge-sharing operation that drains part of the charge on model bit lines MABL and MSBL to capacitor C, lowering the voltage on MSBL below VBL, while model bit lines MABLB and MSBLB remain at VBL. The assertion of Pact also connects MN 6  and MN 7  to VSSA, causing charge to be drained from MABL, C, and MSBL through MN 6  until MABL, C, and MSBL reach VSSA. The assertion of Pact also connects MP 1  and MP 2  to VINTA, causing charge to be supplied from VINTA through MP 2  to MABLB and MSBLB until MABLB and MSBLB reach VINTA. 
     It should now be noted that a resistor R 1  is coupled between VINTA and transistor MP 3 , such that all charge supplied from VINTA to MABLB and MSBLB during the modeling circuit activation passes through R 1  as a charging current. The modeling circuit output signal out is taken at the node joining R 1  and MP 3 . Thus prior to the modeling circuit activation, out is set to a voltage VINTA as no current flows through R 1 . When modeling circuit  70  is activated, a bit line charging current Ic flows through R 1 , dropping the voltage at out to VINTA−Ic×R 1 . Current Ic decreases as bit lines MABLB and MSBLB near VINTA, causing out to rise until eventually out approaches voltage VINTA again. 
     The layout and size of the model components in cell modeling circuit  70  can be set to match or approximate those used during a sensing operation in the memory cell array. Thus the charging current used during the modeling circuit activation can be designed to represent an estimate of the charging current that will be required in an actual sensing operating that will begin almost immediately after the time of modeling that sensing operation. As the charging current estimate occurs so near in time to the actual sensing operation, on similar circuitry fabricated at the same time on the same circuit, it can be appreciated that process, voltage, and temperature differences that might affect the current required for a sensing operation will affect the modeling circuit similarly, providing increased accuracy in the overdrive of VINTA. Further, the sensitivity to the width of a Pact pulse can be decreased, as most of the charging current estimated during the modeling circuit activation occurs nearer the beginning of the Pact pulse. 
       FIG. 11  shows an alternate configuration for cell modeling circuit  70 . The MOSFET transistor MP 4 , which set the state of capacitor C during the device startup sequence, is replaced with a p-channel MOSFET transistor MP 4 . The gate of MP 4  is driven by a control signal pupB that is momentarily driven to a logic low condition during the device startup sequence. When pupB is driven low, MP 4  couples capacitor C to internal array voltage VINTA, thus charging capacitor C. This effectively presets model memory cell MMC to a known logic “1” memory condition. 
     Upon activation of the modeling circuit, the charge-sharing operation between C and model bit lines MABL and MSBL charges model bit lines MABL and MSBL from capacitor C, raising the voltage on MSBL above VBL, while model bit lines MABLB and MSBLB remain at VBL. The assertion of Pact also connects transistors MN 6  and MN 7  to VSSA, causing charge to be drained from MABLB and MSBLB through transistor MN 7  until MABLB and MSBLB reach VSSA. The assertion of Pact also connects transistors MP 1  and MP 2  to VINTA, causing charge to be supplied from VINTA through transistor MP 1  to MABL, C, and MSBL until MABL, C, and MSBL reach VINTA. 
     When modeling circuit  70  is activated, a bit line charging current Ic flows through R 1 , dropping the voltage at output node out to VINTA−Ic×R 1 . Current Ic decreases as bit lines MABL and MSBL and capacitor C near VINTA, until eventually out approaches voltage VINTA again. Note that because the sensing operation beginning voltage on MSBL is slightly higher than the beginning voltage on MSBLB in  FIG. 11 , and because the model memory cell MMC is charged as well, the modeling circuit output signal out may be slightly different for  FIG. 11  embodiment than for the  FIG. 10  embodiment. 
     Although the cell modeling circuit embodiments shown in  FIGS. 10 and 11  closely emulate an actual sensing configuration, other modeling circuit embodiments are possible. For instance,  FIG. 12  shows a simpler version of a cell modeling circuit  70 . A model memory cell MMC comprises a capacitor C coupled to an n-channel MOSFET pass transistor N, which connects in turn through a resistor R 2  to internal array voltage VINTA. A cell modeling circuit output signal out is supplied from the node joining resistor R 2  and transistor N. A p-channel MOSFET transistor MP 3  is also coupled to capacitor C and to the bit line precharge voltage VBL. The overdriving control signal Pact drives the gate of pass transistor N, and also drives the gate of transistor MP 3 . 
     Prior to the activation of overdriving control signal Pact, transistor MP 3  is active, allowing capacitor C to charge to bit line precharge voltage VBL. When overdriving control signal Pact is activated, transistor MP 3  is disabled and transistor N is enabled, allowing C to charge from VBL towards VINTA. Output signal out, like in the preceding example, drops below VINTA as charging current is supplied to capacitor C. Capacitor C and resistor R 2  can be selected to achieve a desired output signal profile. Although possibly not as precise a model as that shown in  FIGS. 10 and 11 , The  FIG. 12  modeling circuit will also track PVT variations in similar fashion as the more complex embodiments. 
     Turning now to  FIG. 13 , one embodiment for an amplifier  72  that can be paired with an embodiment of cell modeling circuit  70  is depicted. Amplifier  72  comprises an input section IP, a current mirror CM, and an output section OP. Each will be described in turn. 
     Input section IP comprises an n-channel MOSFET transistor N 10 , a resistor R 3 , and a p-channel MOSFET transistor P 3 . Transistor N 10  and resistor R 3  are connected in a source follower configuration, with the drain of transistor N 10  connected to internal array voltage VINTA, the gate of transistor N 10  driven by the modeling circuit output signal out, and the resistor R 3  coupled between the source of transistor N 10  and internal array ground voltage VSSA. The voltage at node a, where transistor N 10  and resistor R 3  are coupled, follows the voltage appearing on modeling circuit output signal out. The gate of transistor P 3  is coupled to node a, the source of transistor P 3  is coupled to VINTA, and the drain of transistor P 3  is coupled to an input of current mirror CM at node b. 
     Current mirror CM comprises two n-channel MOSFET transistors N 11  and N 12  with a transistor width ratio A:B. Transistor N 11  has a drain coupled to current mirror input node b, a source coupled to VSSA, and a gate coupled to current mirror input node b. Transistor N 12  has a drain coupled to a current mirror output node c, a source coupled to VSSA, and a gate coupled to current mirror input node b. The width ratio A:B forces the current i 2  passing through transistor N 12  to relate to the current i 1  passing through transistor N 11  by a scaling factor B/A. 
     Output section OP comprises a p-channel MOSFET transistor P 4  with a source coupled to an external power voltage VEXT, and a drain and gate coupled to current mirror output node c. The overdriving level control circuit output signal acon″ is also taken at node c. 
     Operation of amplifier  72  is as follows. Prior to the activation of overdriving control signal Pact, out is approximately equal to VINTA, causing the voltage at node a to approach VINTA approximately also. This high voltage at node a turns off transistor P 3 , cutting off currents i 1  and i 2  and providing no drive signal at output acon″. When overdriving control signal Pact enables the cell modeling circuit, the voltage out at the gate of transistor N 10  drops, which drops the voltage of node a in turn. As the voltage of node a drops, P 3  turns on and a current i 1  begins to flow. Current i 1  is mirrored as i 2 , scaled by a scaling factor B/A. This results in a corresponding voltage drop at node c and a reduced voltage for output acon″. 
       FIG. 14  shows one configuration for the active driving signal generator  42  and driver  44  shown in  FIG. 7 . Active driving signal generator  42  comprises a differential amplifier COM and an n-channel MOSFET transistor N 13  having a gate driven by activation signal act. When signal act is generated by control circuit  20 ′, transistor N 13  is turned on, turning on amplifier COM in turn. A negative input terminal of amplifier COM is coupled to a reference voltage VREF, and a positive input terminal of amplifier COM is coupled to VINTA. The output of the differential amplifier, acon, drives the gate of a p-channel MOSFET transistor P 5  in driver  44 . Transistor P 5  has a source connected to the external array voltage VEXT and a drain connected to internal array voltage VINTA. This connection completes a feedback loop that causes amplifier COM to attempt to drive acon such that VINTA is equal to VREF. 
     The control signal acon″, from overdriving level control circuit  60 , also drives the gate of transistor P 5  in driver  44 . When Pact is active and act is not active, the feedback loop including amplifier COM is disabled, allowing acon″ to drive VINTA above VREF. For instance, as acon″ drops in response to the charging current of the modeling circuit, transistor P 5  is turned on to a greater degree, allowing additional charging of VINTA above the VREF level. Subsequently, when act is enabled, amplifier COM cannot control the internal array voltage VINTA back to VREF until sufficient charge is consumed in the internal array power distribution subsystem and sense amplifiers to allow the voltage to drop. 
       FIG. 15  shows a second semiconductor memory device embodiment  400 . Although similar in many respects to embodiment  300  of  FIG. 7 , several differences are notable. A separate driver  62  is provided for overdriving VINTA. The control signal acon″ is no longer provided by the overdriving level control circuit  60  to active mode driver  44 , but is supplied instead to the new driver  62 . All three drivers  34 ,  44 , and  62  can provide drive current for internal array voltage VINTA, with driver  34  always active, driver  44  active for the duration of an act pulse, and driver  62  active for the duration of a Pact pulse. 
       FIG. 16  shows one configuration for driver  62 . The output of overdriving level control circuit  60 , acon″, drives the gate of a p-channel MOSFET transistor P 6  in driver  62 . Transistor P 6  has a source connected to the external array voltage VEXT and a drain connected to internal array voltage VINTA. When Pact is active, acon″ can drive VINTA above VREF. For instance, as acon″ drops in response to the charging current of the modeling circuit, transistor P 6  is turned on to a greater degree, allowing additional charging of VINTA above the VREF level. 
     Those skilled in the art will recognize that many other device configuration permutations can be envisioned and many design parameters have not been discussed. For instance, in the embodiments of  FIGS. 10 and 11 , a cell modeling circuit output signal could be constructed using circuitry that measures the current drained to VSSA during a sensing operation. The particular current-mode and voltage-mode signals as shown in the embodiments are but one possibility for generating modeling signals. Furthermore, other memory cell array and sensing configurations exist, and may require or be better suited for a different modeling circuit configuration that more accurately models such other configurations. The specific circuits described and shown in the drawings are merely exemplary—in most cases, other circuits can accomplish the same or similar functions. Such minor modifications and implementation details are encompassed within the embodiments of the invention, and are intended to fall within the scope of the claims. 
     The preceding embodiments are exemplary. Although the specification may refer to “an”, “one”, “another”, or “some” embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.