Abstract:
A switched operation amplifier including a biased circuit, an amplifier circuit, and a buffer circuit is provided. The biased circuit is to provide a first, a second, and a third biased signals by means of an input signal and a reference current source. The amplifier circuit is driven by the biased signals through current mirrors, a sample-and-hold switch, a complementary sample-and-hold switch and a differential pair. The buffer circuit includes a capacitor and two transistors in series. An output signal is generated from a node in between the two transistors, and fed back to a negative terminal of the differential pair of the amplifier circuit. The amplifier circuit charges the capacitor and controls one of the transistors of the buffer circuit until the voltages of a positive and the negative terminal of the differential pair are equal. By means of the operation of the switched op amplifier, the output voltage can be kept being stable.

Description:
FIELD OF INVENTION  
       [0001]     This invention relates to a sample-and-hold circuit, more particularly, to a sample-and-hold circuit having a switched operation amplifier designed.  
       BACKGROUND OF INVENTION  
       [0002]     A sample/hold circuit is mainly utilized in the front stage of ADC (analog to digital converter) to increase data accuracy while sampling data. The sample-and-hold circuit is thus a critical factor on the whole circuit performance. It is widely applied in the electronic device. For instance, as the CD/DVD chip operated at burning mode, it is demanded that a sample-and-hold (S/H) circuit ensures the output voltage stable while sampling or holding data. Generally, the sample-and-hold circuit may have many forms to present. Following switched operation amplifier (SOP) is the common one.  
         [0003]     Referring to  FIG. 1 , a SOP circuit according to prior art is shown. An operation amplifier (OP) having a positive terminal and a negative terminal is connected to a switch S/H. The switch S/H is coupled to a buffer and a capacitor C h  which is connected to ground. The buffer has an output voltage V OUT  feedback to the negative terminal to form a voltage V N . As the switch S/H is on, it is a sampling mode having the voltage V OUT  feedback into the negative terminal of the OP to make the voltage V OUT  equal to an input voltage V P  received from the positive terminal. In the meantime, the capacitor C h  is charged to follow the input voltage V P . As the switch S/H is off, it is the holding mode that the output voltage V OUT  is provided only from the capacitor C h  so that the voltage V OUT  is approximately equivalent to the input voltage V P .  
         [0004]      FIG. 2  shows detailed circuit diagram of the SOP according to  FIG. 1 . The SOP includes an amplifier circuit  10 , a biased circuit  12  and a buffer circuit  14 . The amplifier circuit  10  composed of transistors M 0  to M 12  has a differential pair (M 1 , M 2 ) to receive the input voltage V P  and the voltage V N  which is feedback from the output voltage V OUT  respectively. The biased circuit  12  composed of transistors M 15  to M 24  generates biased voltages bp 0 , bpc, bnc, bn 0  for the amplifier circuit  10  and the buffer circuit  14 , which is composed of transistors M 13 , M 14  and the capacitor C h . The buffer circuit  14  generates the output voltage V OUT  according to the voltage V NZ  at the node NZ. The output voltage V OUT  is feedback to the negative terminal of the differential pair (M 1 , M 2 ) to form the voltage V N .  
         [0005]     In the sampling mode (switch S switched on, switch H switched off), the transistors M 7 , M 8 , M 9 , M 10  are in active region by either biased voltage bpc or bnc, and the capacitor C h  is charged to a predetermined voltage (V P ) via the node NZ so that the output voltage V OUT  equals to the predetermined voltage (V P ). Worthwhile to note, the biased voltages bnc, bn 0  are generated by two current sources i 1 , i 2  through the transistors M 15 , M 17 , which are diode-connected transistor. The biased voltages bnc, bn 0  then derives mirror currents through current mirror (transistors M 18 , M 20 , M 19 , M 21 ), while biased voltages bpc, bp 0  is arisen through PMOS transistors M 22 , M 23 , M 24 . Still, the biased voltage bn 0  is fed into a gate of transistor M 0  of the amplifier circuit  10  to generate a tail current i t . The tail current i t  then branched into two current i t1 , and i t2  on transistors M 1 , M 2  of the differential pair, where i t1 =(½)i t +Δi, and i t2 =(½)i t −Δi.  
         [0006]     Furthermore, the current i t1  generates a mirror current i t3  through current mirror (M 3 , M 5 ). The current i t3  flows through transistors M 7 , M 9 , M 11  and next again generates mirror current i t4  through transistor M 12  by the current mirror relationship. A mirror current i t5  of the current i t2  flows through transistors M 4 , M 6 , M 8 . The mirror current i t5  associated with the mirror current i t4  determines the voltage V NZ  of the node NZ by charging the capacitor C h . The voltage V NZ  turns on the transistor M 13  such that the output voltage V OUT  equals to the voltage V N , and equals to the input voltage V P .  
         [0007]     In the holding mode (switch H switched on, switch S switched off), the transistors M 7 , M 8 , M 9 , M 10  are in cut-off region due to the gates of the transistors M 7  and M 8  are connected to VDD (for PMOS) and the gates of the transistors M 9  and M 10  are connected to ground (for NMOS). The input voltage V P  can not affect the output voltage V OUT . The output voltage V OUT  is kept to a value determined by the capacitor C h .  
         [0008]     However, many problems are found in accordance with aforementioned prior art. For instance, ground voltage drifted due to turning on the transistors M 7 , M 8 , M 9 , M 10  in the sampling mode, will generate about 400 mA, which depends on the size of the transistors, such as channel width/channel length (W/L). In the holding mode, all of the transistors M 7 , M 8 , M 9 , M 10  are turned off, which results in current variation due to effect of stray resistors while upon switching. The current variation will affect the ground potential variation, further, affecting the output voltage, or even causing malfunctions.  
         [0009]     In addition, two sets of current source i 1 , i 2  in the biased circuit  12  are utilized to generate biased voltages bn 0 , bnc, bp 0 , bpc according to prior art. Thus, if it is desired to shift the bandwidth of the SOP, a direct method is to change the current of the current sources i 1  and i 2 . However, owing to cascade structure of the transistors (M 15  to M 21  are coupled among another), any biased current change will shift the biased voltage, which results in the transistors cannot work at optimum working range. Consequently, bandwidth variability is restricted seriously.  
         [0010]     Another disadvantage is the setting limitation. The biased voltages of the transistors M 7 , M 8 , M 9 , M 10  are switched rapidly between the biased voltage bnc to ground or the biased voltage bpc to VDD. Therefore, the voltages on gates of M 7 , M 8 , M 9  and M 10  will be set individually in the sampling mode. If the setting speed of the biased voltage bnc to ground is different from the setting speed of the biased voltage bpc to VDD, it will result in the output voltage temporarily unstable, and the setting time is extended.  
         [0011]     An object of the present invention is to propose a newly structure of SOP to solve above problems.  
       SUMMARY OF THE INVENTION  
       [0012]     An object of the present invention is to provide a SOP having a stable output voltage, a better bandwidth performance.  
         [0013]     According to an embodiment of the present invention, a SOP includes an amplifier circuit, a biased circuit, and a buffer circuit. The biased circuit is to provide a first, a second, and a third biased signal. The amplifier circuit includes a first transistor, a second differential pair, a third, a fourth, a fifth current mirror, a sample-and-hold switch, and a complementary sample-and-hold switch. The first transistor is controlled by the first biased signal so as to provide two reference currents for the third and fourth current mirror, which are, respectively, connected with two transistors of the second differential pair. Further, a mirror current of the third current mirror is controlled by the third biased signal to determine whether the third mirror current of the third current mirror is fed into a reference terminal of the fifth current mirror or not. A mirror current terminal of the fourth current mirror is connected with both of the sample-and-hold switch and the complementary sample-and-hold switch so as to provide a current path either though the sample-and-hold switch to a mirror terminal of the fifth current mirror, or the complementary sample-and-hold switch to ground depending on sampling mode or holding mode being selected. Two gates of the two transistors of the second differential pair are served, respectively, as a positive and a negative terminal. A buffer circuit having a capacitor, a second and a third transistor wherein the capacitor is connected between ground and a node connected both of the sample-and-hold switch and a gate of the second transistor. A source terminal of the second transistor is connected with a drain terminal of the third transistor. Furthermore, the source terminal of the second transistor is served as a signal output terminal and fed back to the negative terminal. Tthe third transistor is controlled by the second biased signal.  
         [0014]     According to an embodiment of the present invention, wherein the biased circuit includes a first current mirror, a biased signal generator, a low output impedance buffer. The first current mirror is to generate the second biased signal according to a reference current. The biased signal generator is connected with a mirror terminal of the first current mirror to generate the first biased signal. The low output impedance buffer is connected with the first current mirror to generate the third biased signal according to a biased input signal.  
         [0015]     According to an embodiment of the present invention, wherein the low output impedance buffer includes a fourth transistor, a first differential pair, and a second current mirror, wherein the fourth transistor is controlled by the second biased signal.  
         [0016]     According to an embodiment of the present invention, wherein the sample-and-hold switch is composed of a fifth transistor in series connected with a sixth transistor and both of them are controlled by the third biased signal while switching to sampling mode.  
         [0017]     According to an embodiment of the present invention, wherein the complementary sample-and-hold switch is a transistor having a source terminal connected with the fourth current mirror and is controlled by the third biased signal while switching to holding mode.  
         [0018]     A method of operating a sample-and-hold circuit, for a switched operation amplifier is also provided. The switched operation amplifier including a biased circuit for generating a third biased signal, an amplifier circuit and a buffer circuit. The amplifier circuit has a second differential pair, a third, a fourth, a fifth current mirror, a sample-and-hold switch, and a complementary sample-and-hold switch. The buffer circuit has a capacitor. The method including the steps of: charging the capacitor through the fourth current mirror and the fifth current mirror by turning on the sample-and-hold switch to do signal sampling, the capacitor providing a rising voltage to a negative terminal of the second differential pair until the negative terminal has the same voltage as an input voltage received by a positive terminal of the second differential pair; and discharging the capacitor by turning off the sample-and-hold switch to do signal holding, while the complementary sample-and-hold switch is turned on to provide a current path for the fourth current mirror.  
         [0019]     According to an embodiment of the present invention, wherein the sample-and-hold switch and the complementary sample-and-hold switch are controlled by the third biased signal, and one is activated while the other one is turned off according to signal holding or sampling.  
         [0020]     According to an embodiment of the present invention, wherein the biased circuit includes only one current source to generate biased signals for the amplifier circuit and the buffer circuit.  
         [0021]     According to an embodiment of the present invention, wherein the current path provided by the complementary sample-and-hold switch is conducted to ground. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with accompanying drawings in which:  
         [0023]      FIG. 1  is a SOP circuit according to prior art;  
         [0024]      FIG. 2  shows detailed circuit of the SOP circuit according to prior art; and  
         [0025]      FIG. 3  shows detailed circuit of the SOP circuit according to an embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0026]     The present invention is to provide a switched operation amplifier (hereinafter called SOP) to avoid current unstable to result in ground voltage variation while doing sample-and-hold switching. Herein a preferred embodiment is depicted. The exemplary is for illustration conveniently only but not intended to limit the claim scope. The detailed of the invention is as follows.  
         [0027]     Referring to  FIG. 3 , a SOP includes an amplifier circuit  20 , a biased circuit  22 , and a buffer circuit  24 . The biased circuit  22  includes a first current mirror consisting of transistors M 15 , M 16  and a low output impedance buffer  220  (transistors M 18  to M 22 ). A reference current i 1  through gates of the transistors M 15  and M 16  of the first current mirror generates a biased voltage bp 0 . Furthermore, a mirror current i 2  of the first current mirror is then through a biased voltage generator which is a transistor M 17  having gate and drain connected together to generate a biased voltage bn 0 . The biased voltage bn 0  is directed to the transistor M 0  of the amplifier circuit  20  so as to generate a tail current i t . The biased voltage bp 0  is to drive a PMOS transistor M 14  of the buffer circuit  24 .  
         [0028]     The output low impedance buffer  220  is composed of transistor M 18 , a first differential pair consisting of transistors M 19  and M 20 , and a second current mirror consisting of transistors M 21  and M 22 . The gate of the transistor M 18  is coupled to gates of transistors M 15  and M 16  and driven by biased voltage bp 0 . Still, a drain of the transistor M 18  coupled to sources of the transistors M 19  and M 20 , and a gate of the transistor M 19  is coupled to a biased input voltage boc_in. A gate and drain of the transistor M 20  are connected together with a drain of the transistor M 22 . A gate and drain of the transistor M 21  are connected together with a gate of the transistor M 22  and a drain of the transistor M 19 .  
         [0029]     The biased voltage bp 0  is for driving the transistor M 18 . The biased input voltage boc_in generated by a voltage divided circuit of resistors (not shown) exerted to the transistor M 19  of the differential pair (transistors M 19 , M 20 ) and the current mirror (transistors M 21 , M 22 ) thereby generating a biased voltage boc. The biased voltage boc, as shown, is to drive transistors M 7 , M 9  of the amplifier circuit  20  and provide biased voltage of the transistors (M 8 , M 10 ) while switch S is switched on in the sampling mode. Worthwhile to note, the low output impedance buffer  220  having low output impedance is to make the biased voltage boc_in equal to the biased voltage boc by the second current mirror (transistors M 21 , M 22 ) to provide the stable biased voltage boc for the amplifier circuit  20  (transistors M 7 , M 8 , M 9 , M 10 , M 8   a ).  
         [0030]     The amplifier circuit  20  includes the transistor M 0 , a second differential pair (transistors M 1 , M 2 ), a third current mirror (transistors M 3 , M 5 , M 7 ), a fourth current mirror (transistors M 4 , M 6 ), a fifth current mirror (transistors M 9 , M 11 , M 12 ), a sample-and-hold switch  26  (transistors M 8 , M 10 ), and a complementary sample-and-hold switch  28  (transistor M 8   a ). The gates of the transistors M 1 , M 2  of the second differential pair are, respectively, coupled to voltages V P , V N  and served as a positive and a negative terminal of the amplifier circuit  20 . The voltage V N  comes from the output voltage V OUT  of the buffer circuit  24 . The voltage V P  is an input voltage which comes from external signal. The sources of the transistors M 1 , M 2  of the second differential pair are connected together then coupled to a drain of the transistor M 0  which is controlled by biased voltage bn 0  to generate a tail current i t . A gate and drain of the transistor M 3  are connected together then coupled to a drain of the transistor M 1  and a gate of the transistor M 5 . Similarly, a gate and drain of the transistor M 4  are connected together then coupled to a drain of the transistor M 2  and a gate of the transistor M 6 . When the transistors M 7  and M 8  (or M 8   a ) are activated by the biased voltage boc, the tail current i t  is induced to generate two reference currents i t1  for the transistor M 1  and i t2  for the transistor M 2 , wherein i t =i t1 +i t2 . The current i t1  and i t2  is determined by the biased voltages V N , V P  of the transistors M 1  and M 2 .  
         [0031]     A mirror current i t3  of the third current mirror is mirrored from the reference current i t1  while the transistors M 7 , M 9  are driven by the biased voltage boc. On the other hand, in the sampling mode when switch S is switched on and the switch H is switched off, the transistor M 8  of the sample-and-hold switch  26  is turned on, a mirror current i t4  of the fourth current mirror is mirrored from the reference current i t2 . According to the fifth current mirror, a mirror current i t5  is mirrored from the reference current i t3 .  
         [0032]     The buffer circuit  24  is composed of two PMOS transistors M 14 , M 13  and a capacitor C h . A drain of the transistor M 14  is connected to the source of the transistor M 13 . The connection node of the transistors M 14 , M 13  is for outputting the voltage V OUT , which is feedback to the negative terminal V N . A gate of the transistor M 13  is connected to the drains of the M 8  and M 10  of the amplifier circuit  20 . Also, the gate of the transistor M 13  is connected with a terminal of the capacitor C h , whose other terminal is grounded. Thus, in the holding mode, as the switch S switched on, switch H switched off in the sample-and-hold switch  26 , the current i t3 =i t5 . The output current of the amplifier circuit  20  will persistently charge the capacitor C h  until the current i t4 =i t5 . At that time V P =V N =V OUT .  
         [0033]     The complementary sample-and-hold switch  28  is a PMOS transistor M 8   a  having its drain grounded. Both transistors M 8   a  and M 8  are circuit having their source connected with a drain of the transistor M 6 . The complementary sample-and-hold switch  28  is to provide a current path for the mirror current i t4  conducted to ground while the sample-and-hold switch  28  is in the holding mode (the transistor M 8  is turned off but the transistor M 8   a  is turned on). Thus, the currents in the amplifier circuit  20  are always stable while mode switching.  
         [0034]     In the sampling mode, the transistors M 7 , M 8 , M 9 , M 10  are controlled by biased voltage boc. The transistors M 7 , M 8 , M 9 , M 10  operate in active region and a branched current i t4  minus i t5  charges the capacitor C h  to a predetermined voltage if the biased voltage boc is over a threshold voltage until the relationship Of V OUT =V N =V P  is established. As forgoing depicted, in the holding mode, the transistors M 8 , M 10  are turned off. Therefore, the voltage V OUT  will not be affected by the input voltage V P . Although the transistor M 8  is turned off, the transistor M 8   a  is, however, turned on to keep the current without obstruction in the amplifier circuit  20 .  
         [0035]     In conclusion, the biased circuit  22  includes only one current source to generate biased voltages for the amplifier circuit  20  and the buffer circuit  24 . Comparing to the prior art, two sets of current source i 1 , i 2  in the biased circuit  12  are utilized to generate biased voltages bn 0 , bnc, bp 0 , bpc shown in  FIG. 2 . Thus, if it is desired to shift the bandwidth of the SOP, a direct method is to change the current of the only one current source according to the present invention. Consequently, bandwidth variability is not restricted seriously. Moreover, the amplifier circuit  20  includes the sample-and-hold switch  26  and the complementary sample-and-hold switch  28  which are both controlled by the same biased voltage (boc), and one is activated while the other one is turned off according to the holding mode or sampling mode. The disadvantage of the setting limitation is avoided by this way according to the present invention. Furthermore, the complementary sample-and-hold switch  28  provides a current path in the holding mode to direct the mirror current to ground, so as to avoid the current variation due to effect of stray resistors while upon switching.  
         [0036]     The benefits of the present invention are as following:  
         [0037]     According to the present invention, the gate voltage of the transistors M 7 , M 9  are biased by the voltage boc. In the meantime, the current path can either flow though transistor M 8  or M 8   a  in the sampling mode or holding mode. The total currents in the amplifier circuit  20  will be nearly constant. Consequently, neither ground voltage in inner nor external of the circuit will be very stable without variation, problem due to switch the sampling or holding mode.  
         [0038]     To generate the biased voltage boc, bn 0 , bp 0  for the amplifier circuit  20  and the buffer circuit  24 , only one set of current source i 1  for the biased circuit  22  is required. Thus the SOP according to the present invention is readily controlled while comparing to the prior art. Thus the frequency bandwidth controlled is more flexible.  
         [0039]     According to the embodiment of the present invention, at switching instant from the holding mode to sampling mode, the gates of the transistors M 8 , M 10  receiving the voltage boc is simultaneously. The voltage boc is nearly an average of the V DD  and GND, thus the charge recombination is very quick during switching. Hence, the operation rate is very fast.  
         [0040]     While there have been described above the principles of the present invention in conjunction with specific devices, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention, Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known and which may be used instead of or in addition to features already described herein.