Abstract:
A spatial light modulation device capable of displaying a large number of gray scales is provided. The inventors of the present invention proposed a spatial light modulation device having: a first structure in which a switching transistor and an erasure transistor, each having its gate electrode connected to a different scanning line, are formed in each pixel, and whose switching is controlled separately; or a second structure in which two switching transistors, each having its gate electrode connected to a different scanning line, are formed in each pixel, and whose switching is controlled separately.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a deformable mirror device (DMD), and more specifically, the present invention relates to a method of driving a DMD.  
           [0003]    2. Description of the Related Art  
           [0004]    The development of high intensity, high definition flat panel displays (FPDs) has been advancing in recent years. Displays such as liquid crystal displays, EL (electroluminescence) displays, and plasma displays can be given as examples of FPDs.  
           [0005]    Furthermore, in addition to the above FPDs, digital micromirror devices (hereafter referred to as DMDs) have been in the spotlight. Techniques related to DMDs have been disclosed by Texas Instruments, Inc., in patent applications such as: Japanese Patent Application Laid-open No. Hei 5-150173, Japanese Patent Application Laid-open No. Hei 5-183851, Japanese Patent Application Laid-open No. Hei 7-240891, Japanese Patent Application Laid-open No. Hei 8-334709, Japanese Patent Application Laid-open No. Hei 8-227044, Japanese Patent Application Laid-open No. Hei 8-051586, and Japanese Patent Application Laid-open No. Hei 8-227044.  
           [0006]    A plurality of micromirrors approximately 16 μm×16 μm in size are formed having a pitch of 17 mμ on a CMOS SRAM formed on a silicon substrate, and each of the micromirrors corresponds to a screen pixel, in the DMD. The number of micromirrors reaches 480,000 for SVGA, 786,000 for XGA, and 1,300,000 for SXGA.  
           [0007]    The angle of the micromirror changes by an angle θ with respect to the substrate if a digital signal having image information (digital video signal) is input to the SRAM of the DMD, in accordance with an electric field effect due to voltage from the SRAM. If the angle of the micromirror with respect to the substrate changes by an amount θ (where 0&lt;θ&lt;90°), then light from a light source is separated into two directions when reflected in the micromirror. One of the lights separated into two directions is absorbed by a light absorber, while the other arrives at a screen and forms an image.  
           [0008]    Note that the term digital signal denotes a signal having two voltage values in this specification. Of the two voltage values, the higher is indicated by the term HI, while the lower is indicated by the term LO.  
           [0009]    Schematic diagrams of a structure of a general DMD pixel are shown in FIGS. 20A and 20B. FIG. 20A is a perspective diagram of a DMD pixel, and FIG. 20B is a cross sectional diagram of the DMD pixel of FIG. 20A. A plurality of pixels are formed on a substrate  901 , and each pixel has a first electrode (first address electrode)  902   a , a second electrode (second address electrode)  902   b , landing sites  903 , a micromirror  904 , a hinge  905 , and hinge support posts  906 .  
           [0010]    The angle of the micromirror  904  with respect to the substrate  901  is changed by an amount θ with the hinge  905  acting as a rotational axis. The hinge  905  is fixed on the substrate  901  by the hinge posts  906 .  
           [0011]    A portion of the micromirror  904  contacts the landing site  903  when the micromirror  904  is inclined to an angle greater than θ with respect to the substrate with the hinge  905  as an axis of rotation. The landing site  903  is maintained at the same electric potential as that of the mirror  904 , or has insulating properties.  
           [0012]    The electric potential of a digital video signal input to the pixel is imparted to the first address electrode  902   a . Further, the digital video signal is inverted with electric potential of ground as a standard point, and the inverted signal is imparted to the second address electrode  902   b  as an inverted digital video signal.  
           [0013]    A fixed electric potential (standard electric potential) is imparted to the micromirror  904 . The micromirror  904  is then inclined by an angle θ to the first address electrode  902   a  side if the electric potential difference between the standard electric potential and that of the digital video signal is greater than the size of the electric potential difference between the standard electric potential and that of the inverted digital video signal. Conversely, if the electric potential difference between the standard electric potential and that of the digital video signal is smaller than the size of the electric potential difference between the standard electric potential and that of the inverted digital video signal, then the micromirror  904  is inclined by an angle θ to the second address electrode  902   b  side.  
           [0014]    Digital light processing (DLP) with a projector using a DMD having the above structure differs from a projector using liquid crystals, and there is no light loss from a polarizing plate, and the aperture ratio is equal to or greater than 90%; the efficiency of utilizing light is therefore high. Further, this is a reflective type device, differing from general transmission type liquid crystal panels, and therefore the spacing between pixels, namely the spacing between the micromirrors, is small at about 0.8 μm, and a high definition image can easily be obtained even a projection is enlarged on the screen. In addition, no thermal problem develops like that of liquid crystal panels using thin film transistors because DMDs have superior cooling efficiency, and it is possible to use a high power light source, and therefore making projectors high definition becomes easy.  
           [0015]    A drive circuit of a pixel in a conventional DMD is shown next in FIG. 21. Reference numeral  911  denotes a data driver, reference numeral  912  denotes a scanning driver, and reference numeral  914  denotes a pixel portion. The pixel portion  914  has a plurality of pixels  913 .  
           [0016]    The digital driver  911  inputs a digital video signal into a plurality of data lines  918 , and the scanning driver  912  inputs a scanning signal into a plurality of scanning lines  917 . Regions having one data line  918  and one scanning line  917  correspond to the pixels  913  for the case of the DMD shown by FIG. 21.  
           [0017]    The pixels  913  each have a switching transistor  915 , and an SRAM  916  having a plurality of transistors. A gate electrode of the switching transistor  915  is connected to the scanning line  917 . Further, one of a source region and a drain region of the switching transistor  915  is connected to the data line  918 , and the other is connected to an input terminal Vin of the SRAM  916  and to the first address electrode  902   a.    
           [0018]    Note that the term SRAM denotes a static RAM having no transfer gates throughout this specification. If HI input is imparted to the SRAM, then LO output is obtained, and if LO input is imparted to the SRAM, then HI output is obtained. Conversely, if a HI output is imparted to the SRAM, then a LO input is obtained, and if a LO output is imparted to the SRAM, then a HI input is obtained.  
           [0019]    Note that, throughout this specification, the term transistor denotes an electric field effect transistor, which functions as a switching element.  
           [0020]    An out put terminal Vout of the SRAM  916  is connected to the second address electrode  902   b . Further, Vddh denotes a high voltage side electric power source, and Vss denotes a low voltage side electric power source.  
           [0021]    The switching transistor  915  is selected in the DMD shown in FIG. 21 by the scanning signal input to the scanning line  917  from the scanning driver  912 . Note that, in this specification, the term selection of a wiring denotes a state in which all transistors whose gate electrode is connected to the wiring are on.  
           [0022]    The digital video signal is then input to the data line  918  from the data driver  911 . The input digital video signal is input to the input terminal Vin of the SRAM  916 , and to the first address electrode  902   a , through the switching transistor  915  in an ON state. The digital video signal input to the input terminal Vin of the SRAM  916  is inverted, with the ground electric potential as a standard, and is then output from the output terminal Vout as an inverted digital video signal, and input to the second address electrode  902   b.    
           [0023]    If the digital video signal and the inverted digital video signal are input to the first address electrode  902   a  and to the second address electrode  902   b , respectively, then the angle of the micromirror  904  of the pixel with respect to the substrate is selected in accordance with the 1″ or 0″ information of the digital video signal. Whether light from a light source is irradiated to a screen, or is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.  
           [0024]    The digital video signal is then input in order to all of the pixels  913  of the pixel portion  914 , and the micromirror angles are selected. Note that, in this specification, the term digital video signal input to the pixels  913  refers to the digital video signal being input to the source region or the drain region of the switching transistors  915  of the pixels  913 .  
           [0025]    If the digital video signal is then once again input to the same pixels, the micromirror angles are selected again.  
           [0026]    Time division gray scale display of a conventional DMD is explained next using FIG. 22. The horizontal axis shows a time scale, and the vertical axis shows the position of a scanning line in FIG. 22.  
           [0027]    A plurality of subframe periods are formed in one frame period with the time division gray scale display used by conventional DMDs.  
           [0028]    An example in which n subframe periods are formed within one frame period is shown in FIG. 22. By then selecting the angle of the micromirror in each of the n subframe periods in accordance with the digital video signal, light from the light source is irradiated to the screen or to the light absorber. Hereafter, light irradiated to the screen is referred to as white display, and light irradiated to the light absorber is referred to as black display.  
           [0029]    White display or black display is selected from the first subframe to the number n subframe in accordance with the first bit to the number n bit of the digital video signal.  
           [0030]    By selecting white display or black display in the n subframe periods, the length of the white display periods and the length of the black display periods within one frame period can be controlled. As a result, the gray scale of an image formed by one frame period can be controlled.  
           [0031]    However, if the number of gray scales of the image displayed is increased with the conventional DMD time division gray scale display shown in FIG. 22, the length of the subframe periods becomes shorter. A problem therefore develops in that the write in speed of the digital video signal to the pixels cannot be managed. This problem is explained in detail below using FIG. 23.  
           [0032]    The horizontal axis of FIG. 23 shows a time scale, and the vertical axis shows the position of a scanning line. Further, reference symbol t 1  denotes the length of a period for writing in the number i bit of the digital video signal to the pixel, and reference symbol t 2  denotes the length of a subframe period SFi.  
           [0033]    For the case of the drive shown in FIG. 23, t 1  t 2 , and the number i bit of the digital video signal is written into all of the pixels before the number i subframe period SFi is complete and the number (i+1) subframe period SF(i+1) begins. Write in of the number i bit of the digital video signal to the pixels and write in of the number (i+1) bit of the digital video signal to the pixels are therefore not performed in parallel within the same pixel portion.  
           [0034]    However, if the number of gray scales becomes larger, and the number i subframe period SFi becomes shorter, then t 1 &gt;t 2 . In this case, there are times when write in of the number i bit of the digital video signal to the pixels is not complete, even though the number i subframe period SFi is finished. In other words, write in of the number (i+1) bit of the digital video signal to the pixels must be performed in parallel with write in of the number i bit of the digital video signal. With the DMD structure shown by FIG. 21, drive in which t 1 &gt;t 2  is impossible.  
         SUMMARY OF THE INVENTION  
         [0035]    In view of the above problem, an object of the present invention is to provide a DMD having a novel structure in which display of an image at a high number of gray scales is possible.  
           [0036]    The inventors of the present invention proposed a first structure in which two switching elements having their gate electrodes connected to differing scanning lines (a switching transistor and an erasure transistor) are formed in each pixel, and in which switching is controlled separately.  
           [0037]    A digital video signal is input to a pixel by placing the switching transistor in an ON state, and a state of black display in the pixel is set by placing the erasure transistor in an ON state. Switching of the switching transistor and the erasure transistor is controlled by using separate scanning driver circuits. Input of the digital video signal in order to the pixels can therefore be performed, in the same pixel portion, in parallel with the setting of a black display state in order in the pixels.  
           [0038]    A method of driving a DMD of the present invention is explained using FIG. 1. The horizontal axis shows a time scale in FIG. 1, while the vertical axis shows the position of a scanning line. Further, reference symbol t 1  denotes the length of a display period Tri in which each line of pixels performs display in accordance with the number i bit of the digital video signal, and reference numeral t 2  denotes the length of a period for performing write in of the number i bit of the digital video signal into all of the pixels.  
           [0039]    With the method of driving of FIG. 1, the display period Tri begins by placing the switching transistors into an ON state and writing the number i bit of the digital video signal into the pixels.  
           [0040]    Next, the pixels become placed in a black display state, in order, after the display period Tri begins and through the time t 1  by turning on the erasure transistors, and the display period Tri is complete. Note that, in this specification, the period during which the pixels are placed in a black display state by turning on the erasure transistors is referred to as a non-display period Td. In particular, the non-display period appearing directly after the display period Tri is referred to as Tdi.  
           [0041]    Reference symbol t 3  denotes the length of the non-display period Tdi in each line of pixels. It is very important that the length t 3  of the non-display period be such that the period for performing write in of the number i bit of the digital video signal to the pixels, and the period for performing write in of the number (i+1) bit of the digital video signal to the pixels, do not overlap. That is, it is very important that t 3 ≧t 2 −t 1 .  
           [0042]    The switching transistors again become placed in an ON state after passing the time t 3  from the start of the non-display period Tdi, and write in of the number (i+1) bit of the digital video signal to the pixels begins. The non-display period Tdi is completed at the same time as the beginning of write in period of the number (i+1) bit of the digital video signal to the pixels, and the display period Tr(i+1) begins.  
           [0043]    In accordance with the above driving method, it becomes possible to make the length of the display period Tri shorter than the length of the period for write in of the digital video signal to all of the pixels, even if write-in to the pixels of the number i bit of the digital signal and write-in to the pixels of the number (i+1) bit of the digital signal are not performed in parallel.  
           [0044]    In other words, compared to the time division gray scale display of a conventional DMD, it becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the first structure of the present invention. Consequently, even if the write in speed to the pixels of the digital video signal is the same as the conventional speed, it becomes possible to make the number of image gray scale very large.  
           [0045]    Further, the inventors of the present invention proposed a second structure in which two switching elements having their gate electrodes connected to differing scanning lines (a first switching transistor and a second switching transistor) are formed in each pixel, and in which switching is controlled separately. In the second structure, the two switching transistors are referred to as the first switching transistor and the second switching transistor in the second structure, and both are referred to using the generic name switching transistors.  
           [0046]    Input of the number i bit of a digital video signal to the pixels can be performed in parallel with input of the number (i+1) bit of the digital video signal to the pixels, in the same pixel portion, by controlling the first switching transistor and the second switching transistor separately.  
           [0047]    A method of driving of the present invention is explained using FIG. 2. The horizontal axis shows a time scale in FIG. 2, while the vertical axis shows the position of a scanning line. Further, reference symbol t 1  denotes the length of a period for performing write in of the number i bit of the digital video signal into all of the pixels, and reference symbol t 2  denotes the length of a display period Tri in which each line of pixels performs display in accordance with the number i bit of the digital video signal. Case in which t 1 &gt;t 2  is shown in FIG. 2.  
           [0048]    With the method of driving of FIG. 2, the display period Tri begins by placing the first switching transistors into an ON state and writing the number i bit of the digital video signal into the pixels.  
           [0049]    Next, the number (i+1) bit of the digital video signal is written into the pixels, in order, after the display period Tri begins and up through the time t 2  by placing the second switching transistors in an ON state. The display period Tri is completed, and the display period Tr(i+1) begins, in order, from the pixels into which the number (i+1) bit of the digital video signal is written.  
           [0050]    It becomes possible to perform write-in to the pixels of the number i bit of the digital video signal, and the number (i+1) bit of the digital video signal, in parallel by using the above driving method. It also becomes possible to make the display period Tri shorter than the length of the period for writing in the digital video signal to all of the pixels.  
           [0051]    Compared to the time division gray scale display of a conventional DMD, it becomes possible to make the length of the display period corresponding to a conventional subframe period be shorter with the DMD time division gray scale display of the second structure of the present invention. Consequently, even if the write in speed to the pixels of the digital video signal is the same as the conventional speed, it becomes possible to make the number of image gray scale very large.  
           [0052]    Now, the structure of the present invention will be described.  
           [0053]    According to a first structure of the present invention, there is provided a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, characterized in that:  
           [0054]    the pixel portion has a plurality of pixels;  
           [0055]    each one of the plurality of pixels has a first address electrode and a second address electrode;  
           [0056]    a digital video signal output from the data driver is input to the first address electrode by the write in scanning driver;  
           [0057]    an electric potential of the power source for the erasing operation is applied to the second address electrode by the erasure scanning driver;  
           [0058]    the electric potential of the first address electrode and the electric potential of the second address electrode are always inverted with ground taken as a reference point.  
           [0059]    The present invention relates to a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, characterized in that:  
           [0060]    the pixel portion has a plurality of pixels;  
           [0061]    each one of the plurality of pixels has a switching transistor, an SRAM, a transistor for the erasing operation, a first address electrode and a second address electrode;  
           [0062]    the write in scanning driver controls a switching of the switching transistor;  
           [0063]    the erasure scanning driver controls a switching of the transistor for the erasing operation;  
           [0064]    the data driver inputs a digital video signal to an input terminal of the SRAM and to the first address electrode through the switching transistor;  
           [0065]    an output terminal of the SRAM is connected to the second address electrode; and  
           [0066]    the power source for the erasing operation is connected to the second address electrode and the output terminal through the transistor for the erasing operation.  
           [0067]    According to the first structure of the present invention, there is provided a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, a plurality of scanning lines for the writing operation, and a plurality of scanning lines for the erasing operation, characterized in that:  
           [0068]    the pixel portion has a plurality of pixels;  
           [0069]    each one of the plurality of pixels has a switching transistor, an SRAM, a transistor for the erasing operation, a first address electrode and a second address electrode;  
           [0070]    a switching of the switching transistor is controlled by a scanning signal for the writing operation which is input to the plurality of the scanning lines for the writing operation from the write in scanning driver;  
           [0071]    a switching of the transistor for the erasing operation is controlled by a scanning signal for the writing operation which is input to the plurality of the scanning lines for the erasing operation from the erasure scanning driver;  
           [0072]    the data driver inputs a digital video signal to an input terminal of the SRAM and to the first address electrode through the switching transistor;  
           [0073]    an output terminal of the SRAM is connected to the second address electrode; and  
           [0074]    the power source for erasing operation is connected to the second address electrode and the output terminal through the transistor for erasing operation.  
           [0075]    According to the first structure of the present invention, there is provided a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, characterized in that:  
           [0076]    the pixel portion has a plurality of pixels;  
           [0077]    each one of the plurality of pixels has a first address electrode and a second address electrode;  
           [0078]    a digital video signal output from the data driver is input to the first address electrode by the write in scanning driver;  
           [0079]    an electric potential of the power source for the erasing operation is applied to the second address electrode by the erasure scanning driver;  
           [0080]    the electric potential of the first address electrode and the electric potential of the second address electrode are always inverted with ground taken as a reference point;  
           [0081]    n display periods Tr 1 , Tr 2  . . . and Trn and j non-display periods Td 1 , Td 2 , and Tdj appear within one frame period of each line of pixels of the plurality of pixels;  
           [0082]    a display period Tri (i is 1, . . . or any one of n) is a period from when the number i bit of a digital video signal is input to each line of the pixels, until the next digital video signal is input to each line of the pixels, or a period until the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively;  
           [0083]    a non-display period Tdk (k is 1, . . . or any one of n) is a period from when the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively, until the digital video signal is input to each line of the pixels;  
           [0084]    after all of the n display periods Tr 1 , Tr 2 , . . . , and Trn appeared, any one of the n display periods Tr 1 , Tr 2 , . . . , and Trn appears again;  
           [0085]    white display or black display is selected, by the digital video signal, in the n display periods Tr 1 , Tr 2 , . . . , and Trn; and  
           [0086]    the ratio of lengths of the n display periods Tr 1 , Tr 2 , . . . , and Trn is represent by 2 0 ::2 1 ::2 2  . . . , 2 (n−1) .  
           [0087]    According to the first structure of the present invention, there is provided a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, a plurality of scanning lines for the writing operation, and a plurality of scanning lines for the erasing operation, characterized in that:  
           [0088]    the pixel portion has a plurality of pixels;  
           [0089]    each one of the plurality of pixels has a switching transistor, an SRAM, a transistor for the erasing operation, a first address electrode and a second address electrode;  
           [0090]    the write in scanning driver controls a switching of the switching transistor;  
           [0091]    the erasure scan driver controls a switching of the transistor for the erasing operation;  
           [0092]    the data driver inputs a digital signal to an input terminal of the SRAM and to the first address electrode through the switching transistor;  
           [0093]    an output terminal of the SRAM is connected to the second address electrode;  
           [0094]    the power source for the erasing operation is connected to the second address electrode and to the output terminal through the transistor for the erasing operation;  
           [0095]    n display periods Tr 1 , Tr 2  . . . and Trn and j non-display periods Td 1 , Td 2 , and Tdj appear within one frame period of each line of pixels of the plurality of pixels;  
           [0096]    a display period Tri (i is 1, . . . or any one of n) is a period from when the number i bit of a digital video signal is input to each line of the pixels, until the next digital video signal is input to each line of the pixels, or a period until the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively;  
           [0097]    a non-display period Tdk (k is 1, . . . or any one of n) is a period from when the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively, until the digital video signal is input to each line of the pixels;  
           [0098]    after all of the n display periods Trl, Tr 2 , . . . and Trn appeared, any one of the n display periods Tr 1 , Tr 2 , . . . , and Trn appears again;  
           [0099]    white display or black display is selected, by the digital video signal, in the n display periods Tr 1 , Tr 2 , . . . , and Trn; and  
           [0100]    the ratio of lengths of the n display periods Tr 1 , Tr 2 , . . . , and Trn is represent by 2 0 ::2 1 ::2 2  . . . , 2 (n−1)    
           [0101]    According to the first structure of the present invention, there is provided a driving method of a micromirror device comprising a pixel portion and a power source for the erasing operation, characterized in that:  
           [0102]    the pixel portion has a plurality of pixels;  
           [0103]    each one of the plurality of pixels has a first address electrode and a second address electrode;  
           [0104]    n display periods Tr 1 , Tr 2  . . . and Trn and j non-display periods Td 1 , Td 2 , and Tdj appear within one frame period of each line of pixels of the plurality of pixels;  
           [0105]    a display period Tri (i is 1, . . . or any one of n) is a period from when the number i bit of a digital video signal is input to each line of the pixels, until the next digital video signal is input to each line of the pixels, or a period until the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively;  
           [0106]    a non-display period Tdk (k is 1, . . . or any one of n) is a period from when the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively, until the digital video signal is input to each line of the pixels;  
           [0107]    after all of the n display periods Tr 1 , Tr 2 , . . . , and Trn appeared, any one of the n display periods Tr 1 , Tr 2 , . . . , and Trn appears again;  
           [0108]    white display or black display is selected, by the digital video signal, in the n display periods Tr 1 , Tr 2 , . . . , and Trn; and  
           [0109]    the ratio of lengths of the n display periods Tr 1 , Tr 2 , . . . , and Trn is represent by 2 0 ::2 1 ::2 2 . . . 2 (n−1) .  
           [0110]    The first structure of the present invention may have a feature that the plurality of pixels each have a micromirror.  
           [0111]    The first structure of the present invention may have a feature that white display or black display is selected, by the digital video signal, in the n display periods Tr 1 , Tr 2 , . . . , and Trn.  
           [0112]    The first structure of the present invention may have a feature that when the electric potential of the power source for the erasing operation is applied to the second address electrode, the micromirror is tilted in a direction so that black display is performed.  
           [0113]    The first structure of the present invention may have a feature that the SRAM has two p-channel transistors and two n-channel transistors.  
           [0114]    The first structure of the present invention may have a feature that the SRAM has two p-channel transistors and two resistors.  
           [0115]    The first structure of the present invention may have a feature that the SRAM has two n-channel transistors and two resistors.  
           [0116]    The first structure of the present invention includes a projector which is characterized by having the micromirror device.  
           [0117]    According to a second structure of the present invention, there is provided a micromirrror device comprising a first data driver, a second data driver, a scanning driver, and a pixel portion, characterized in that:  
           [0118]    the pixel portion has a plurality of pixels;  
           [0119]    each of the plurality of pixels has a first switching transistor, a second switching transistor, an SRAM, a first address electrode, and a second address electrode;  
           [0120]    the scanning driver controls a switching of the first switching transistor and a switching of the second switching transistor;  
           [0121]    the first data driver inputs a digital signal to an input terminal of the SRAM and to the first address electrode through the first switching transistor;  
           [0122]    the second data driver inputs a digital signal to an output terminal of the SRAM and the second address electrode through the second switching transistor;  
           [0123]    the digital signal input to the input terminal is inverted, with an electric potential of a ground being a reference, to be output from the output terminal; and  
           [0124]    the digital signal input to the output terminal is inverted, with the electric potential of the ground being the reference, to be output from the input terminal.  
           [0125]    According to the second structure of the present invention, there is provided a micromirror device comprising a first data driver, a second data driver, a scanning driver, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of a first data lines, and a plurality of a second data lines, characterized in that:  
           [0126]    the pixel portion has a plurality of pixels;  
           [0127]    each of the plurality of pixels has a first switching transistor, a second switching transistor, an SRAM, a first address electrode, and a second address electrode;  
           [0128]    a switching of the first switching transistor and a switching of the second switching transistor are controlled by scanning signals input from the scanning driver to the plurality of the first scanning lines and the plurality of the second scanning lines;  
           [0129]    a digital signal input from the first data driver to the plurality of the first data lines, is input to an input terminal of the SRAM and to the first address electrode through the first switching transistor;  
           [0130]    a digital signal input from the second data driver to the plurality of the second data lines, is input to an output terminal of the SRAM and to the second address electrode through the second switching transistor;  
           [0131]    the digital signal input to the input terminal is inverted, with an electric potential of a ground being a reference, to be output from the output terminal; and  
           [0132]    the digital signal input to the output terminal is inverted, with the electric potential of the ground being the reference, to be output from the input terminal.  
           [0133]    According to the second structure of the present invention, there is provided a micromirror device comprising a first data driver, a second data driver, a scan driver, and a pixel portion, characterized in that:  
           [0134]    the pixel portion has a plurality of pixels;  
           [0135]    each of the plurality of pixels has a first switching transistor, a second switching transistor, an SRAM, a first address electrode, and a second address electrode;  
           [0136]    the scan driver controls a switching of the first switching transistor and a switching of the second switching transistor;  
           [0137]    the first data driver inputs a digital signal to an input terminal of the SRAM and the first address electrode through the first switching transistor;  
           [0138]    the second data driver inputs a digital signal to an output terminal of the SRAM and the second address electrode through the second switching transistor;  
           [0139]    the digital signal input to the input terminal is inverted, with an electric potential of a ground being a reference, to be output from the output terminal; and  
           [0140]    the digital signal input to the output terminal is inverted, with the electric potential of the ground being the reference, to be output from the input terminal;  
           [0141]    (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j) appear in order within one frame period of each line of pixels of the plurality of pixels;  
           [0142]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), j display period is a non-display period;  
           [0143]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), white display or black display is selected by the digital signal within a display period, which is not the non-display period;  
           [0144]    after all of the (n+j) display periods Tr 1 , Tr 2 , . . . , and Tr(n+j) appeared, the (n+j) display periods Tr 1 , Tr 2 , . . . , and Tr(n+j) appears, in order, again; and  
           [0145]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), the ratio of lengths of the display periods, which are not the non-display periods, are arranged in order from the shortest, is represent by 2 0 ::2 1 ::2 2 . . . , 2 (n−n) .  
           [0146]    According to the second structure of the present invention, there is provided a micromirror device comprising a first data driver, a second data driver, a scanning driver, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of a first data lines, and a plurality of a second data lines, characterized in that:  
           [0147]    the pixel portion has a plurality of pixels;  
           [0148]    each of the plurality of pixels has a first switching transistor, a second switching transistor, an SRAM, a first address electrode, and a second address electrode;  
           [0149]    a switching of the first switching transistor and a switching of the second switching transistor are controlled by scanning signals input from the scanning driver to the plurality of the first scanning lines and to the plurality of the second scanning lines;  
           [0150]    a digital signal input from the first data driver to the plurality of the first data lines, is input to an input terminal of the SRAM and to the first address electrode through the first switching transistor;  
           [0151]    a digital signal input from the second data driver to the plurality of the second data lines, is input to an output terminal of the SRAM and to the second address electrode through the second switching transistor;  
           [0152]    the digital signal input to the input terminal is inverted, with an electric potential of a ground being a reference, to be output from the output terminal;  
           [0153]    the digital signal input to the output terminal is inverted, with the electric potential of the ground being the reference, to be output from the input terminal;  
           [0154]    (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j) appear in order within one frame period of each line of pixels of the plurality of pixels;  
           [0155]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), j display period is a non-display period;  
           [0156]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), white display or black display is selected by the digital signal within a display period, which is not the non-display period;  
           [0157]    after all of the (n+j) display periods Tr 1 , Tr 2 , . . . , and Tr(n+j) appeared, the (n+j) display periods Tr 1 , Tr 2 , . . . , and Tr(n+j) appears, in order, again; and  
           [0158]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), the ratio of lengths of the display periods, which are not the non-display periods, are arranged in order from the shortest, is represent by 2 0 ::2 1 ::2 2  . . . , 2 (n−1) .  
           [0159]    According to the second structure of the present invention, there is provided a driving method of a micromirror device having a pixel portion, characterized in that:  
           [0160]    the pixel portion has a plurality of pixels;  
           [0161]    each of the plurality of the pixels has a first address electrode and a second address electrode;  
           [0162]    (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j) appear in order within one frame period of each line of pixels of the plurality of pixels;  
           [0163]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), j display period is a non-display period;  
           [0164]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), white display or black display is selected by the digital signal within a display period, which is not the non-display period;  
           [0165]    after all of the (n+j) display periods Tr 1 , Tr 2 , . . . , and Tr(n+j) appeared, the (n+j) display periods Tr 1 , Tr 2 , . . . , and Tr(n+j) appears, in order, again; and  
           [0166]    among the (n+j) display periods Tr 1 , Tr 2  . . . and Tr(n+j), the ratio of lengths of the display periods, which are not the non-display periods, are arranged in order from the shortest, is represent by 2 0 ::2 1 ::2 2  . . . , 2 (n−1) .  
           [0167]    The second structure of the present invention may have a feature that the (n+j) display periods Tr 1 , Tr 2 , . . . , and Tr(n+j) are periods from when the digital signal is written to the pixels in the (n+j) write in periods Ta 1 , Ta 2 , . . . , and Ta (n+j), until the digital signal is input to the pixels in the write in period which appears next to the (n+j) write in periods Ta 1 , Ta 2 , . . . , and Ta(n+j).  
           [0168]    The second structure of the present invention may have a feature that among the (n+j) write in periods Ta 1 , Ta 2 , . . . , and Ta (n+j), an arbitrary write in period Tai does not overlap with a write in period which appears before two write in periods of the arbitrary write in period Tai and with a write in period which appears after two write in periods of the arbitrary write in period Tai.  
           [0169]    The second structure of the present invention may have a feature that the plurality of pixels each have a micromirror.  
           [0170]    The second structure of the present invention may have a feature that the SRAM has two p-channel transistors and two n-channel transistors.  
           [0171]    The second structure of the present invention may have a feature that the SRAM has two p-channel transistors and two resistors.  
           [0172]    The second structure of the present invention may have a feature that the SRAM has two n-channel transistors and two resistors.  
           [0173]    The second structure of the present invention includes a projector which is characterized by having the micromirror device. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0174]    In the accompanying drawings:  
         [0175]    [0175]FIG. 1 is a diagram which shows simply a method of driving a first structure DMD of the present invention;  
         [0176]    [0176]FIGS. 2A and 2B are diagrams which show simply a method of driving a second structure DMD of the present invention;  
         [0177]    [0177]FIG. 3. is a diagram showing a pixel portion and a driver circuit of a first structure DMD of the present invention;  
         [0178]    [0178]FIG. 4 is a diagram showing a method of driving a first structure DMD of the present invention;  
         [0179]    [0179]FIG. 5. is a diagram showing a pixel portion and a driver circuit of a second structure DMD of the present invention;  
         [0180]    [0180]FIG. 6 is a diagram showing a method of driving a second structure DMD of the present invention;  
         [0181]    [0181]FIGS. 7A and 7B are diagrams showing DMD micromirror driving of the present invention;  
         [0182]    [0182]FIG. 8 is a diagram showing a method of driving a first structure DMD of the present invention;  
         [0183]    [0183]FIG. 9 is a diagram showing the method of driving a first structure DMD of the present invention;  
         [0184]    [0184]FIG. 10 is a diagram showing the method of driving a first structure DMD of the present invention;  
         [0185]    [0185]FIG. 11 is a diagram showing a method of driving a second structure DMD of the present invention;  
         [0186]    [0186]FIG. 12 is a diagram showing the method of driving a second structure DMD of the present invention;  
         [0187]    [0187]FIG. 13 is a diagram showing the method of driving a second structure DMD of the present invention;  
         [0188]    [0188]FIG. 14 is a diagram showing the method of driving a second structure DMD of the present invention;  
         [0189]    [0189]FIG. 15 is a diagram showing a structure of a DMD of the present invention;  
         [0190]    [0190]FIG. 16 is an equivalent circuit diagram of an SRAM;  
         [0191]    [0191]FIGS. 17A and 17B are equivalent circuit diagrams of SRAMs;  
         [0192]    [0192]FIG. 18A to  18 C are diagrams of a DLP and a rotating color foil of a DMD of the present invention;  
         [0193]    [0193]FIGS. 19A and 19B are diagrams of DLPs of a DMD of the present invention;  
         [0194]    [0194]FIGS. 20A and 20B are diagrams showing simply a DMD structure;  
         [0195]    [0195]FIG. 21 is a diagram showing a pixel portion and a driver circuit of a conventional DMD;  
         [0196]    [0196]FIG. 22 is a diagram showing simply a conventional method of driving a DMD; and  
         [0197]    [0197]FIG. 23 is a diagram for explaining problem points of a conventional method of driving a DMD. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0198]    A circuit diagram of a first structure DMD of the present invention is shown in FIG. 3. Reference numeral  111  denotes a data driver, reference numeral  112   a  denotes a write in scanning driver, reference numeral  112   b  denotes an erasure scanning driver, and reference numeral  114  denotes a pixel portion. The pixel portion  114  has a plurality of pixels  113 . Note that the write in scanning driver  112   a  and the erasure scanning driver  112   b  are referred to by the generic name a scanning driver  112 .  
         [0199]    Note also that, although a first structure is shown in this embodiment mode in which there are one each of the data driver  111 , the write in scanning driver  112   a , and the erasure scanning driver  112   b , the first structure DMD of the present invention is not limited thereto. Further, the pixel portion  114 , the data driver  111 , the write in scanning driver  112   a , and the erasure scanning driver  112   b  may be formed on the same substrate, and they may also be formed on different substrates and then be connected to the pixel portion  114  by using a means such as an FPC or TAB.  
         [0200]    The data driver  111  inputs a digital video signal to a plurality of data lines  118 . The write in scanning driver  112   a  then inputs a write in scanning signal to a plurality of write in scanning lines  117   a . Further, the erasure scanning driver  112   b  inputs a write in scanning signal to a plurality of erasure scanning lines  117   b.    
         [0201]    Regions having one data line  118 , one write in scanning line  117   a , and one erasure scanning line  117   b  correspond to one pixel  113  for the case of the DMD shown by FIG. 3.  
         [0202]    The pixel  113  has a switching transistor  115   a , an erasure transistor  115   b , and an SRAM  116  having a plurality of transistors. A gate electrode of the switching transistor  115   a  is connected to the write in scanning line  117   a . Further, a gate electrode of the erasure transistor  115   b  is connected to the erasure scanning line  117   b.    
         [0203]    The switching transistor  115   a  and the erasure transistor  115   b  may have a single gate structure, and may also have a multi-gate structure such as a double gate or triple gate structure. Further, n-channel transistors may be used for the switching transistor  115   a  and the erasure transistor  115   b , and p-channel transistors may also be used.  
         [0204]    One of a source region and a drain region of the switching transistor  115   a  is connected to the data line  118 , while the other is connected to an input terminal Vin of the SRAM  116  and to a first address electrode  102   a.    
         [0205]    An output terminal Vout of the SRAM  116  is connected to a second address electrode  102   b , and is connected to a source region or a drain region of the erasure transistor  117   b.    
         [0206]    The SRAM  116  may have a structure such that the electric potential of the input terminal and the electric potential of the output terminal are inverted, with ground taken as a reference point. It is therefore possible to use any type of SRAM as the SRAM  116  in the present invention, provided that it has a structure which satisfies the above condition. The term Vddh refers to an electric power source on a high voltage side, and the term Vss refers to an electric power source on a low voltage side.  
         [0207]    Further, among the source region and the drain region of the erasure transistor  115   b , the one which is not connected to the output terminal Vout of the SRAM  116  is connected to an erasure electric power source  119 . The erasure electric power source  119  is maintained at an electric potential such that the pixel performs black display when the electric potential of the erasure electric power source  119  is imparted to the output terminal Vout of the SRAM  116 . In practice, the erasure electric power source  119  is maintained at the same electric potential as the high voltage side electric power source Vddh, or the low voltage side electric power source Vss.  
         [0208]    Further, although not shown in FIG. 3, a micromirror is formed on the first address electrode  102   a  and the second address electrode  102   b  of each pixel. The micromirror is formed so as not to contact the first address electrode  102   a  and the second address electrode  102   b.    
         [0209]    Driving of the DMD shown in FIG. 3 is explained next using FIG. 4. The horizontal axis in FIG. 4 shows a time scale, and the vertical axis shows the position of a scanning line.  
         [0210]    A write in period Ta 1  begins in the DMD shown in FIG. 3. When the write in period Ta 1  begins, the switching transistors  115   a  of a first line of pixels are selected in accordance with a write in scanning signal input to the write in scanning line  117   a  from the write in scanning driver  112 . Note that, in this specification, the term selection of a wiring refers to a state in which all transistors whose gate electrode is connected to the wiring are placed in an ON state. Further, the term first line of pixels refers to pixels having the switching transistor  115   a  whose gate electrode is connected to the first line of the write in scanning lines  117   a.    
         [0211]    The first bit of the digital video signal is then input to the data lines  118  from the data driver  111 . The input first bit of the digital video signal is then input to the first address electrode  102   a  and to the input terminal Vin of the SRAM  116 , through the switching transistor  115   a  in the ON state. The first bit of the digital video signal input to the input terminal Vin of the SRAM  116  is inverted with the ground electric potential taken as a reference, output from the output terminal Vout as the first bit of an inverted digital video signal, and input to the second address electrode  102   b.    
         [0212]    If the digital video signal and the inverted digital video signal are input to the first address electrodes  102   a  and to the second address electrodes  102   b , respectively, then the angles of the micromirrors of the pixels, with respect to the substrate, are selected in accordance with the “1” or “0” information in the digital video signal. Whether light from a light source is irradiated to a screen, or whether the light from the light source is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.  
         [0213]    The digital video signal is then input in order to all of the lines of pixels  113 , and the micromirror angles are selected. Note that, in this specification, the term digital video signal is input to the pixel  113  refers to the digital video signal being input to the source region or to the drain region of the switching transistor  115  of the pixel  113 .  
         [0214]    A period up until the digital video signal is input to all of the pixels is the write in period Ta 1 .  
         [0215]    On the other hand, an erasure period Te 1  begins before the write in period Ta 1  is complete. The erasure transistors  115   b  of the first line of pixels are selected in accordance with an erasure scanning signal input to the erasure scanning lines  117   b  from the erasure scanning driver  112   b  when the erasure period Te 1  begins.  
         [0216]    The electric potential of the erasure electric power source (hereafter referred to as an erasure electric potential) is imparted to the output terminals Vout of the SRAMs  116  and to the second address electrodes  102   b , through the erasure transistors  115   b , when the erasure transistors  115   b  are selected.  
         [0217]    An electric potential which is inverted with the ground electric potential as a reference (hereafter referred to as an inverted erasure electric potential) is imparted to the input terminals Vin of the SRAMs  116  when the erasure electric potential is imparted to the output terminals Vout of the SRAMs  116 .  
         [0218]    The micromirrors are inclined in a direction such that light from the light source is irradiated to the light absorber when the erasure electric potential and the inverted erasure electric potential are imparted to the output terminal Vout and to the input terminal Vin of the SRAM  116 , respectively, and the pixels perform black display.  
         [0219]    The erasure transistors  115   b  of all of the lines of pixels are then selected in order, and all perform black display. The erasure period Te 1  is complete when all of the erasure scanning lines  117   b  are selected.  
         [0220]    On the other hand, a write in period Ta 2  again begins either before or after the erasure period Te 1  is complete, and the second bit of the digital video signal is written to the pixels.  
         [0221]    The above operations are repeated until the number m bit of the digital video signal is input to the pixels, and display periods Tr and non-display periods Td repeatedly appear. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Tr 1  to Tr (m−1) are periods from when the switching transistors  115   a  are selected until the erasure transistors  115   b  of the same pixels are next selected. In particular, the display period Tr of the first line of pixels is the same as the period from when the write in period Ta begins until the next erasure period Te to appear begins.  
         [0222]    Non-display periods Td for performing black display also differ with each line of pixels. The non-display periods Td are periods from the selection of the erasure transistors  115   b  until the switching transistors  115   a  are next selected. In particular, the non-display period Td of the first line of pixels is the same as the period from when the erasure period Te begins until the next write in period Ta to appear begins.  
         [0223]    The number m bit of the digital video signal is then input to the pixels when the write in period Tam begins. In order to simplify the explanation, an example of a case in which m=n−2 is shown in FIG. 4, but the present invention is of course not limited to this example. It is possible to arbitrarily select the value of m from 1 to n.  
         [0224]    Then, after the write in period Tam is complete, but not an erasure period, the next write in period Ta(m+1)[n−1] begins. The number (m+1)[n−1] bit of the digital video signal is input to the pixels when the write in period Ta(m+1)[n−1] begins.  
         [0225]    The above operations are repeated until the number n bit of the digital video signal is input to the pixels, and the display periods Tr appear in succession. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Trm to Trn are periods from when the switching transistors  115   a  of the pixels are selected until the switching transistors  115   a  of the same pixels are again selected. In particular, the display period Tr of the first line of pixels is the same as a period from when the write in period Ta begins until the next write in period Ta to appear begins.  
         [0226]    One image can be displayed when all of the display periods Tr 1  to Trn are complete. A period in which one image is displayed is referred to as one frame period F in the present invention. Note that the frame period F differs for each line of pixels in the driving method of the present invention. The frame period of the final line of pixels begins when a time nearly as long as the write in period Ta 1  is passed, after the frame period of the first line of pixels begins.  
         [0227]    Note that the first write in period Ta 1  of the next frame period begins at the same time as the display period Trn is completed, and that the above operations are again repeated.  
         [0228]    It is generally preferable to form 60 or more frame periods in one second in display which displays an image. If the number of images displayed in one second is less than 60, then visual flicker of the image begins to become conspicuous.  
         [0229]    Further, it is very important that the sum of the lengths of all of the write in periods be shorter than the length of one frame period with the present invention. It is necessary that the lengths of the display periods be set such that Tr 1 :Tr 2  Tr 3 : . . . : Tr(n−1):Trn−2 0 :2 1 :2 2 :2 (n−2) :2 (n−1) . The desired gray scale display, from among  2   n  gray scales, can be performed by combining these display periods.  
         [0230]    The gray scale displayed in a pixel during one frame period is set in accordance with finding the total sum of the lengths of the display periods in which light is irradiated to the screen within the one frame period. For example, if light being irradiated to the screen in all display periods when n=8 is taken as the pixels displaying a brightness of 100, then one gray scale can be expressed in the pixel when light is irradiated to the screen only during Tr 1  and Tr 2 . If light is irradiated to the screen only in Tr 3 , Tr 5 , and Tr 8 , then a gray scale of 60 can be expressed in the pixel.  
         [0231]    It is essential that the write in period Tam for writing the number m bit of the digital video signal into the pixels have a length which is shorter than the length of the display period Trm. It is therefore necessary that the value of the bit number m be a value from 1 to n such that the write in period Tam is shorter than the length of the display period Trm.  
         [0232]    Furthermore, the display periods Tr 1  to Trn may appear in any order. For example, it is possible for the display periods to appear in an order in which Tr 3 , Tr 5 , Tr 2 , . . . follow Tr 1  in one frame period. However, it is very important that an order is chosen so that the write in periods Ta 1  to Tan do not mutually overlap. Further, the erasure periods Tel to Ten must also all be chosen in an order such that they do not mutually overlap.  
         [0233]    Next, a circuit diagram of a second structure DMD of the present invention is shown in FIG. 5. Reference numeral  111   a  denotes a first data driver, reference numeral  111   b  denotes a second data driver, reference numeral  112  denotes a scanning driver, and  114  denotes the pixel portion. The pixel portion  114  has a plurality of the pixels  113 . Note that the first data driver  111   a  and the second data driver  111   b  are referred to by the generic name data driver  111 .  
         [0234]    Note also that, although a structure is shown in the embodiment mode in which there is one scanning driver  112  with the second structure, the present invention is not limited to the second structure DMD. A structure having two or more of the scanning drivers  112  may also be used. Further, the pixel portion  114 , the data driver  111 , and the scanning driver  112  may be formed on the same substrate, and they may also be formed on different substrates and then be connected to the pixel portion  114  by using a means such as an FPC or TAB.  
         [0235]    The first data driver  111   a  inputs a digital video signal to a plurality of first data lines  118   a . The second data driver  111   b  inputs the digital video signal to a plurality of second data lines  118   b . The scanning driver  112  then inputs a scanning signal to a plurality of first scanning lines  147   a  and to a plurality of second scanning lines  147   b.    
         [0236]    Regions having one first data line  118   a , one second data line  118   b , and one first scanning line  147   a , and one second scanning line  147   b  correspond to one pixel  113  for the case of the DMD shown by FIG. 5.  
         [0237]    The pixel  113  has a first switching transistor  115   a , a second switching transistor  115   b , and the SRAM  116  having a plurality of transistors. The gate electrode of the first switching transistor  115   a  is connected to the first scanning line  147   a . Further, the gate electrode of the second switching transistor  115   b  is connected to the second scanning line  147   b.    
         [0238]    The first switching transistor  115   a  and the second switching transistor  115   b  may have a single gate structure, and may also have a multi-gate structure such as a double gate or triple gate structure. Further, n-channel transistors may be used for the first switching transistor  115   a  and the second switching transistor  115   b , and p-channel transistors may also be used.  
         [0239]    One of a source region and a drain region of the first switching transistor  115   a  is connected to the first data line  118   a , while the other is connected to the input terminal Vin of the SRAM  116  and to the first address electrode  102   a.    
         [0240]    One of a source region and a drain region of the second switching transistor  115   b  is connected to the second data line  118   b , while the other is connected to the output terminal Vout of the SRAM  116  and to the second address electrode  102   b.    
         [0241]    The SRAM  116  may have a structure such that the electric potential of the input terminal and the electric potential of the output terminal are inverted, with ground taken as a reference point. It is therefore possible to use any type of SRAM as the SRAM  116  in the present invention, provided that it has a structure which satisfies the above condition. The term Vddh refers to an electric power source on the high voltage side, and the term Vss refers to an electric power source on the low voltage side.  
         [0242]    Further, although not shown in FIG. 5, a micromirror is formed on the first address electrode  102   a  and the second address electrode  102   b  of each pixel. The micromirror is formed so as not to contact the first address electrode  102   a  and the second address electrode  102   b.    
         [0243]    Driving of the DMD shown in FIG. 5 is explained next using FIG. 6. The horizontal axis in FIG. 6 shows a time scale, and the vertical axis shows the position of a scanning line.  
         [0244]    A write in period Ta 1  begins in the DMD shown in FIG. 5. When the write in period Ta 1  begins, the first switching transistors  115   a  of a first line of pixels are selected in accordance with a scanning signal input to the first scanning line  147   a  from the scanning driver  112 . Note that, in this specification, the term selection of a wiring refers to a state in which all transistors whose gate electrode is connected to the wiring are placed in an ON state. Further, the term first line of pixels refers to pixels having the gate electrodes of their first switching transistor  115   a  and their second switching transistor  115   b  connected to the first scanning line  147   a  and to the second scanning line  147   b , respectively.  
         [0245]    The first bit of the digital video signal is then input to the first data lines  118   a  from the first data driver  111   a . The input first bit of the digital video signal is then input to the first address electrode  102   a  and to the input terminal Vin of the SRAM  116 , through the first switching transistor  115   a  in an ON state. The first bit of the digital video signal input to the input terminal Vin of the SRAM  116  is inverted with the ground electric potential taken as a reference, output from the output terminal Vout as the first bit of an inverted digital video signal, and input to the second address electrode  102   b.    
         [0246]    If the digital video signal and the inverted digital video signal are respectively input to the first address electrodes  102   a  and to the second address electrodes  102   b , then the angles of the micromirrors of the pixels, with respect to the substrate, are selected in accordance with the 1″ or 0″ information in the digital video signal. Whether light from a light source is irradiated to a screen, or whether the light from the light source is irradiated to a light absorber, is determined when the angle with respect to the substrate is selected.  
         [0247]    The first scanning lines  147   a  are then selected in order, and the first bit of the digital video signal is input to all of the lines of pixels  113 . The angles of the micromirrors of all of the pixels are therefore selected. Note that, in this specification, the term digital video signal input to the pixel  113  refers to the digital video signal being input to the source region or to the drain region of the first switching transistor  115   a  or the second switching transistor  115   b  of the pixel  113 .  
         [0248]    A period up until the first bit of the digital video signal is input to all of the pixels is the write in period Ta 1 .  
         [0249]    On the other hand, a write in period Ta 2  begins before or after the write in period Ta 1  is complete. The second switching transistors  115   b  of the first line of pixels are selected in accordance with the scanning signal input to the second scanning lines  147   b  from the scanning driver  112  when the write in period Ta 2  begins.  
         [0250]    The second bit of the digital video signal is then input to the second data lines  118   b  from the second data driver  111   b . The input second bit of the digital video signal is then input to the second address electrode  102   b  and to the output terminal Vout of the SRAM  116 , through the second switching transistor  115   b  in an ON state. The second bit of the digital video signal input to the input terminal Vin of the SRAM  116  is inverted with the ground electric potential taken as a reference, output from the input terminal Vin as the second bit of the inverted digital video signal, and input to the first address electrode  102   a.    
         [0251]    If the inverted digital video signal and the digital video signal are input to the first address electrodes  102   a  and to the second address electrodes  102   b , respectively, then the angles of the micromirrors of the pixels, with respect to the substrate, are selected in accordance with the 1″ or 0″ information in the digital video signal. Whether light from the light source is irradiated to the screen, or whether the light from the light source is irradiated to the light absorber, is selected when the angle with respect to the substrate is selected.  
         [0252]    The second scanning lines  147   b  are then selected in order, and the second bit of the digital video signal is input to all of the lines of pixels  113 . The angles of the micromirrors of all of the pixels are therefore selected.  
         [0253]    A period up until the second bit of the digital video signal is input to all of the pixels is the write in period Ta 2 .  
         [0254]    The above operations are repeated until the number n bit of the digital video signal is input to the pixels. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Tr 1  to Trn are periods from when the digital video signal is input to each line of pixels, until the next bit of the digital video signal is input to the same pixels. In particular, the arbitrary display period Tr of the first line of pixels is the same as a period from when an arbitrary write in period begins until the next write in period to appear begins.  
         [0255]    One image can be displayed when all of the display periods Tr 1  to Trn are complete. A period in which one image is displayed is referred to as one frame period F in the present invention. Note that the frame period F differs for each line of pixels in the driving method of the present invention. The frame period of the final line of pixels begins when a time nearly as long as the write in period Ta 1  is passed, after the frame period of the first line of pixels begins.  
         [0256]    Note that the first write in period Ta 1  of the next frame period begins at the same time as the display period Trn is completed, and that the above operations are repeated again.  
         [0257]    It is generally preferable to form 60 or more frame periods every one second in display which displays an image. If the number of images displayed in one second is less than 60, then visual flicker of the image begins to become conspicuous.  
         [0258]    Further, it is very important that the ratio of the lengths of all of the display periods Tr be set such that 2 0 :2 1 :2 2 : . . . :2 (n−2) :2 (n−1)  in the present invention if the display periods Tr are lined up in order from the shortest one. The desired gray scale display, from among 2 n  gray scales, can be performed by combining these display periods.  
         [0259]    The gray scale displayed in a pixel during one frame period is set in accordance with finding the total sum of the lengths of the display periods in which light is irradiated to the screen within one frame period. For example, if light being irradiated to the screen in all display periods when n=8 is taken as the pixels displaying a brightness of 100, then one gray scale can be expressed when light is irradiated to the screen only during the display periods whose length ratios correspond to 2 0  and 2 1 . If light is irradiated to the screen only in the display periods whose length ratios correspond to 2 2 , 2 4 , and 2 7 , then the pixel can express a gray scale of 60.  
         [0260]    Further, it is essential that an arbitrary write in period does not mutually overlap with its two neighboring write in periods. For example, it is necessary that a-write in period Tai does not overlap with a write in period Ta(i+2) and does not overlap with a write in period Ta(i−2).  
         [0261]    Further, the first scanning line  147   a  and the second scanning line  147   b  are selected in order in write in periods appearing in succession in this embodiment mode, but it is not necessary to limit the present invention to this structure. For cases in which adjacent write in periods overlap, it is necessary to perform write in of the digital signal by selecting the first scanning line in one of the adjacent write in periods, and selecting the second scanning line in the other write in period. However, there is no such limitation for cases in which neighboring write in periods do not overlap, and the first scanning line may be selected in both of the write in periods, and the second scanning line may also be selected in both of the write in periods.  
         [0262]    The mechanism of a method of driving a micromirror is explained in detail next using FIGS. 7A and 7B. A micromirror  104  is connected to a standard electric power source  140 . The standard electric power source  140  is always maintained at a fixed reference electric potential. The reference electric potential is shown as 5 V in FIGS. 7A and 7B in order to make the explanation easier to understand, but the reference electric potential is not limited to this value in the present invention. It is possible to set the reference electric potential to any value, provided that it is not an average electric potential between the HI electric potential of the digital video signal and the LO electric potential of the digital video signal.  
         [0263]    The digital video signal is input to the first address electrode  102   a  in FIG. 7A, and the inverted digital video signal is input to the second address electrode  102   b.    
         [0264]    Note that, although an explanation is made in which the HI digital video signal is +15 V, and the LO digital video signal is −15 V, with FIGS. 7A and 7B, the present invention is not limited to those values.  
         [0265]    Note also that the digital video signal has “0” or “1” information, and that one of the “0” or the “1” digital video signals is a signal having HI voltage, while the other is a signal having LO voltage.  
         [0266]    The HI digital video signal is input to the first address electrode  102   a , and the LO inverted digital video signal is input to the second address electrode  102   b  in FIG. 7A. In this case, a voltage of 10 V is formed between the micromirror  104  and the first address electrode  102   a . Further, a voltage of 20 V is formed between the micromirror  104  and the second address electrode  102   b . The micromirror  104  is therefore inclined by an angle θ from the reference surface to the second address electrode  102   b  side by the electric field action. Note that the micromirror  104  becomes a reference surface in a state during which the digital video signal is not input to the first and the second address electrodes  102   a  and  102   b . The reference surface is parallel to the substrate.  
         [0267]    The LO digital video signal is input to the first address electrode  102   a , and the HI inverted digital video signal is input to the second address electrode  102   b  in FIG. 7B. In this case, a voltage of 20 V is formed between the micromirror  104  and the first address electrode  102   a . Further, a voltage of 10 V is formed between the micromirror  104  and the second address electrode  102   b . The micromirror  104  is therefore inclined by an angle θ from the substrate surface to the first address electrode  102   a  side.  
         [0268]    It is possible to perform high speed switching at 15 sec with the DMD, and it is suitable for time division gray scale display.  
         [0269]    Note that, although the digital video signal is input to the first address electrode  102   a , and the inverted digital video signal is input to the second address electrode  102   b  in FIGS. 7A and 7B, the operation can be explained similarly for the reverse case.  
         [0270]    It becomes possible to perform write in of an arbitrary digital video signal to the pixels, and write in of the next digital video signal to the pixels, in parallel in accordance with the above stated drive of the present invention. It also becomes possible to make the display period shorter than the length of the period for performing write in of the digital video signal to all of the pixels.  
         [0271]    In other words, compared to conventional DMD time division gray scale display, it becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the present invention. It consequently becomes possible to make the number of image gray scales very high even if the write in speed of the digital video signal to the pixels is the same as the conventional.  
       Embodiments  
       [0272]    Embodiments of the present invention are explained below.  
         [0273]    [Embodiment 1] 
         [0274]    A case of performing 2 6  gray scales of display in the first structure DMD of the present invention, by using a 6 bit digital video signal, is explained in embodiment 1 using FIG. 8. Note that the DMD of embodiment 1 has the structure shown in FIG. 3 and in FIGS. 7A and 7B. The horizontal axis shows a time scale in FIG. 8, while the vertical axis shows the position of a scanning line.  
         [0275]    First, the write in period Ta 1  begins. When the write in period Ta 1  begins, the switching transistors  115   a  of the first line of pixels are selected in accordance with a write in scanning signal input to the write in scanning line  117   a  from the write in scanning driver  112   a.    
         [0276]    The first bit of the digital video signal is then input to the data lines  118  from the data driver  111 . The input first bit of the digital video signal is then input to the first address electrode  102   a  and to the input terminal Vin of the SRAM  116 , through the switching transistor  115   a  in the ON state. The first bit of the digital video signal input to the input terminal Vin of the SRAM  116  is inverted with the ground electric potential taken as a reference, output from the output terminal Vout as the first bit of an inverted digital video signal, and input to the second address electrode  102   b.    
         [0277]    If the digital video signal and the inverted digital video signal are input to the first address electrodes  102   a  and to the second address electrodes  102   b , then the angles of the micromirrors  104  of the pixels, with respect to the substrate, are selected in accordance with the 1″ or 0″ information in the digital video signal. Whether light from a light source is irradiated to a screen, or whether the light from the light source is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.  
         [0278]    The digital video signal is then input in order to all of the lines of pixels  113 , and the micromirror angles are selected. A period up until the first bit of the digital video signal is input to all of the pixels is the write in period Ta 1 .  
         [0279]    On the other hand, the erasure period Te 1  begins before the write in period Ta 1  is complete. The erasure transistors  115   b  of the first line of pixels are selected in accordance with an erasure scanning signal input to the erasure scanning lines  117   b  from the erasure scanning driver  112   b  when the erasure period Te 1  begins.  
         [0280]    The electric potential of the erasure electric power source (hereafter referred to as erasure electric potential) is imparted to the output terminals Vout of the SRAMs  116  and to the second address electrodes  102   b , through the erasure TFTs  115   b , when the erasure transistors  115   b  are selected.  
         [0281]    An electric potential which is inverted with the ground electric potential as a reference (inverted erasure electric potential) is imparted to the input terminals Vin of the SRAMs  116  when the erasure electric potential is imparted to the output terminals Vout of the SRAMs  116 .  
         [0282]    The micromirrors are inclined in a direction such that light from the light source is irradiated to the light absorber when the erasure electric potential and the inverted erasure electric potential are imparted to the output terminal Vout and to the input terminal Vin of the SRAM  116 , respectively, and the pixels perform black display.  
         [0283]    The erasure transistors  115   b  of all of the lines of pixels are then selected in order, and all perform black display. The erasure period Te 1  is complete when all of the erasure scanning lines  117   b  are selected.  
         [0284]    On the other hand, the write in period Ta 2  begins either before or after the erasure period Te 1  is complete, and the second bit of the digital video signal is written to the pixels, and the angles of the micromirrors  104  are selected.  
         [0285]    The above operations are repeated until the number 5 bit of the digital video signal is input to the pixels, and display periods Tr and non-display periods Td repeatedly appear. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Tr 1  to Tr 4  are periods from when the switching transistors  115   a  are selected until the erasure transistors  115   b  of the same pixels are next selected. In particular, the display period Tr of the first line of pixels is the same as the period from when the write in period Ta begins until the next erasure period Te to appear begins.  
         [0286]    The non-display periods Td 1  to Td 4  for performing black display in all the pixels also differ with each line of pixels. The non-display periods Td are periods from the selection of the erasure transistors  115   b  until the switching transistors  115   a  are next selected. In particular, the non-display period Td of the first line of pixels is the same as the period from when the erasure period Te begins until the next write in period Ta to appear begins.  
         [0287]    The number 5 bit of the digital video signal is then input to the pixels when the write in period Ta 5  begins. Then, after the write in period Ta 5  is complete, not an erasure period but the next write in period Ta 6  begins. The number 6 bit of the digital video signal is input to the pixels when the write in period Ta 6  begins.  
         [0288]    The display periods Tr 5  and Tr 6  thus appear in succession, as stated above. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Tr 5  and Tr 6  are periods from when the switching transistors  115   a  are selected until the switching transistors  115   a  of the same pixels are again next selected. In particular, the display period Tr of the first line of pixels is the same as a period from when the write in period Ta begins until the next write in period Ta to appear begins.  
         [0289]    One image can be displayed when all of the display periods Tr 1  to Tr 6  are complete.  
         [0290]    Note that the first write in period Ta 1  of the next frame period begins when one frame period is complete or the same time as the display period Tr 6  is completed, and that the above operations are then repeated.  
         [0291]    It is necessary that the lengths of the display periods be set such that Tr 1 :Tr 2 :Tr 3 : . . . :Tr 6 =2 0 :2 1 :2 2 : . . . :2 6  in 1 embodiment. The desired gray scale display, from among 2 6  gray scales, can be performed by combining these display periods.  
         [0292]    The gray scale displayed in a pixel during one frame period is set in accordance with finding the total sum of the lengths of the display periods in which light is irradiated to the screen within one frame period. For example, if light irradiated to the screen in all of the display periods is taken as the pixels displaying a brightness of 100 for the case of embodiment 1, then a gray scale of 5 can be expressed when light is irradiated to the screen only during Tr 1  and Tr 2 . If light is irradiated to the screen only during Tr 3  and Tr 5 , then a gray scale of 32 can be expressed in the pixel.  
         [0293]    It is essential that the write in period Ta 5  for writing the number 5 bit of the digital video signal into the pixels have a length which is shorter than the length of the display period Tr 5 .  
         [0294]    Furthermore, the display periods Tr 1  to Tr 6  may appear in any order. For example, it is possible for the display periods to appear in an order in which Tr 3 , Tr 5 , Tr 2 , . . . follow Tr 1  in one frame period. However, it is very important that an order is chosen so that the write in periods Ta 1  to Ta 6  do not mutually overlap. Further, the erasure periods Tel to Te 6  must also all be chosen such that they do not mutually overlap.  
         [0295]    It becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the present invention, in comparison with conventional DMD time division gray scale display. Consequently, it becomes possible to make the number of image gray scales very high even if the write in speed of the digital video signal to the pixels is the same as the conventional.  
         [0296]    [Embodiment 2] 
         [0297]    The order of appearance of the display periods Tr 1  to Tr 6  in a method of driving the first structure DMD of the present invention corresponding to a 6 bit digital video signal is explained in embodiment 2.  
         [0298]    [0298]FIG. 9 shows a timing chart of the driving method of embodiment 2. Embodiment 1 may be referred to for the detailed driving mechanism for a pixel, and therefore such explanation is omitted here. The longest non-display period within one frame period (Td 1  in embodiment 2) is formed at the end of one frame period in the driving method of embodiment 2. With the above structure, it becomes visible to a viewer that there is a cutoff of the frame period between the non-display period Td 1  and the first display period of the next frame period (Tr 4  in embodiment 2). Display irregularities, which occur due to adjoining display periods for emitting light in neighboring frame periods when performing an intermediate gray scale display, can thus be made more difficult to recognize in the viewer&#39;s eyes.  
         [0299]    Note that, although a case of a 6 bit digital video signal is explained in embodiment 2, the present invention is not limited by such. It is possible to implement embodiment 2 without placing any limitations on the number of digital video signal bits.  
         [0300]    [Embodiment 3] 
         [0301]    A case of performing 2 4  gray scales of display in the first structure DMD of the present invention, by using a 4 bit digital video signal, is explained in embodiment 3 using FIG. 10. In FIG. 10 the horizontal axis shows a time scale, while the vertical axis shows the position of a scanning line. Note that the DMD of embodiment 3 has the structure shown in FIG. 3 and in FIGS. 7A and 7B.  
         [0302]    First, the write in period Ta 1  begins. When the write in period Ta 1  begins, the switching transistors  115   a  of the first line of pixels are selected in accordance with a write in scanning signal input to the write in scanning line  117   a  from the write in scanning driver  112   a . Note that, in this specification, the term selection of a wiring refers to a state in which all transistors whose gate electrode is connected to the wiring are placed in an ON state. Further, the term first line of pixels refers to pixels having the switching transistor whose gate electrode is connected to the first line of the write in scanning lines.  
         [0303]    The first bit of the digital video signal is then input to the data lines  118  from the data driver  111 . The input first bit of the digital video signal is then input to the first address electrode  102   a  and to the input terminal Vin of the SRAM  116 , through the switching transistor  115   a  in the ON state. The first bit of the digital video signal input to the input terminal Vin of the SRAM  116  is inverted with the ground electric potential taken as a reference, output from the output terminal Vout as the first bit of an inverted digital video signal, and input to the second address electrode  102   b.    
         [0304]    If the digital video signal and the inverted digital video signal are input to the first address electrodes  102   a  and to the second address electrodes  102   b , then the angles of the micromirrors  104  of the pixels, with respect to the substrate, are selected in accordance with the 1″ or 0″ information in the digital video signal. Whether light from a light source is irradiated to a screen, or whether the light from the light source is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.  
         [0305]    The digital video signal is then input in order to all of the lines of pixels  113 , and the micromirror angles are selected. A period up until the first bit of the digital video signal is input to all of the pixels is the write in period Ta 1 .  
         [0306]    On the other hand, the erasure period Tel begins before the write in period Ta 1  is complete. The erasure transistors  115   b  of the first line of pixels are selected in accordance with an erasure scanning signal input to the erasure scanning lines  117   b  from the erasure scanning driver  112   b  when the erasure period Te 1  begins.  
         [0307]    The electric potential of the erasure electric power source (hereafter referred to as erasure electric potential) is imparted to the output terminals Vout of the SRAMs  116  and to the second address electrodes  102   b , through the erasure transistors  115   b , when the erasure transistors  115   b  are selected.  
         [0308]    An electric potential which is inverted with the ground electric potential as a reference (inverted erasure electric potential) is imparted to the input terminals Vin of the SRAMs  116  when the erasure electric potential is imparted to the output terminals Vout of the SRAMs  116 .  
         [0309]    The micromirrors are inclined in a direction such that light from the light source is irradiated to the light absorber when the erasure electric potential and the inverted erasure electric potential are imparted to the output terminal Vout and to the input terminal Vin of the SRAM  116 , respectively, and the pixels perform black display.  
         [0310]    The erasure transistors  115   b  of all of the lines of pixels are then selected in order, and all perform black display. The erasure period Te 1  is complete when all of the erasure scanning lines  117   b  are selected.  
         [0311]    On the other hand, the write in period Ta 2  begins either before or after the erasure period Te 1  is complete, and the second bit of the digital video signal is written to the pixels, and the angles of the micromirrors  104  are selected.  
         [0312]    The display periods Tr 1  and Tr 2  for performing actual display differ for each line of pixels in accordance with the first bit and the second bit of the digital video signal. The display periods Tr 1  and Tr 2  are periods from when the switching transistors  115   a  are selected until the erasure transistors  115   b  of the same pixels are then selected. In particular, the display period Tr of the first line of pixels is the same as the period from when the write in period Ta begins until the erasure period Te to next appear begins.  
         [0313]    The non-display periods Td 1  and Td 2  for performing black display of all pixels also differ with each line of pixels. The non-display periods Td are periods from the selection of the erasure transistors  115   b  until the switching transistors  115   a  are next selected. In particular, the non-display period Td of the first line of pixels is the same as the period from when the erasure period Te begins until the write in period Ta to next appear begins.  
         [0314]    The third bit of the digital video signal is then input to the pixels when the write in period Ta 3  begins. Then, after the write in period Ta 3  is complete, the next write in period Ta 4  and not an erasure period begins. The fourth bit of the digital video signal is input to the pixels when the write in period Ta 4  begins.  
         [0315]    The display periods Tr 3  and Tr 4  thus appear in succession, as stated above. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Tr 3  and Tr 4  are periods from when the switching transistors  115   a  are selected until the same switching transistors  115   a  are again selected. In particular, the display period Tr of the first line of pixels is the same as a period from when the write in period Ta begins until the write in period Ta to next appear begins.  
         [0316]    One image can be displayed when all of the display periods Tr 1  to Tr 4  are complete.  
         [0317]    Note that the first write in period Ta 1  of the next frame period begins when one frame period is complete or the same time as the display period Tr 4  is completed, and that the above operations are then repeated.  
         [0318]    It is necessary that the lengths of the display periods be set such that Tr 1 :Tr 2 :Tr 3 :Tr 4 =2 0 :2 1 :2 2 :2 3 . The desired gray scale display, from among 2 4  gray scales, can be performed by combining these display periods.  
         [0319]    The gray scale displayed in a pixel during one frame period is set in accordance with finding the total sum of the lengths of the display periods in which light is irradiated to the screen within one frame period. For example, if light irradiated to the screen in all of the display periods is taken as the pixels displaying a brightness of 100 for the case of embodiment 3, then a gray scale of 20 can be expressed when light is irradiated to the screen only during Tr 1  and Tr 2 . If light is irradiated to the screen only during Tr 3 , then a gray scale of 27 can be expressed in the pixel.  
         [0320]    It is essential that the write in periods Ta 3  and Ta 4  for writing the third bit and the fourth bit of the digital video signal into the pixels have lengths which are shorter than the length of the display periods Tr 3  and Tr 4 , respectively.  
         [0321]    Furthermore, the display periods Tr 1  to Tr 4  may appear in any order. For example, it is possible for the display periods to appear in an order in which Tr 3 , Tr 4 , and Tr 2  follow Tr 1  in one frame period. Note that it is important that the erasure periods Te 1  to Te 4  must all be chosen such that they do not mutually overlap. Further, it is also very important that an order is chosen such that the display periods Tr 1  to Tr 4  do not mutually overlap.  
         [0322]    It becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the present invention, in comparison with conventional DMD time division gray scale display. Consequently, it becomes possible to make the number of image gray scales very high even if the write in speed of the digital video signal to the pixels is the same as the conventional.  
         [0323]    Note that it is possible to implement embodiment 3 in combination with embodiment 2.  
         [0324]    [Embodiment 4] 
         [0325]    A method of driving in which non-display periods for performing black display in all pixels are formed in the second structure DMD of the present invention is explained in embodiment 4 using FIG. 11. Note that the DMD of embodiment 4 has the structure shown in FIG. 5 and in FIGS. 7A and 7B. The horizontal axis shows a time scale in FIG. 11, while the vertical axis shows the position of a scanning line.  
         [0326]    First, the first bit of a digital video signal is input to each pixel in the write in period Ta 1 . Note that the input to the pixels of the digital video signal in embodiment 4 is performed similarly to that of the embodiment mode, and therefore an explanation of the detailed driving mechanism is omitted here.  
         [0327]    If the digital video signal and the inverted digital video signal are input to the first address electrodes  102   a  and to the second address electrodes  102   b , then the angles of the micromirrors of the pixels, with respect to the substrate, are selected in accordance with the “1” or “0” information in the digital video signal. Whether light from a light source is irradiated to a screen, or whether the light from the light source is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.  
         [0328]    The write in period Ta 2  begins next, before the write in period Ta 1  is complete. A digital signal (non-display signal) having information such that black display is performed in all of the pixels is input to each pixel in the write in period Ta 2  in embodiment 4. Differing from the digital video signal, the non-display signal does not have image information.  
         [0329]    Note that the digital video signal having image information, the inverted digital video signal having image information, and the non-display signal which does not have image information are all included in the term digital signal in this specification.  
         [0330]    All of the pixels are placed in a black display state when the non-display signal is input to each pixel. Display of an image therefore does not occur in the display period Tr 2 . A period in which the pixels are placed in a state of black display in accordance with the non-display signal having no image information is referred to as a non-display period in this specification. The display period Tr 2  is a non-display period in embodiment 4.  
         [0331]    Next, the write in period Ta 3  begins either before or after the write in period Ta 2  is complete. The write in period Ta 3  begins before the write in period Ta 2  is complete in embodiment 4. The second bit of the digital video signal is input to each pixel in the write in period Ta 3 .  
         [0332]    The display period Tr 2 , a non-display period, is completed and the display period Tr 3  begins, when the second bit of the digital video signal is input to each pixel.  
         [0333]    The above operations are repeated until the number n bit of the digital video signal is input to the pixels and all of the display periods (including non-display periods) have appeared.  
         [0334]    One frame period is complete when all of the display periods are completed, and one image can be displayed. If the number of non-display periods having been appeared is taken as j, then (n+j) display periods appear within one frame period.  
         [0335]    The first bit of the digital video signal is again input to the pixels after the first frame period is complete, and the display period Tr 1  begins. The above operations are then repeated.  
         [0336]    The display periods Tr 1 , Tr 2 , . . . , Tr(n+j−1), and Tr(n+j) are periods from when the write in periods Ta 1 , Ta 2 , . . . , Ta(n+j−1), and Ta(n+j) begin, respectively, until the next write in periods to appear Ta 2 , Ta 3 , . . . , Ta(n+j), and Ta 1  begin.  
         [0337]    Further, from among the display periods Tr 1  to Tr(n+j), the ratio of the lengths of the display periods becomes  2   0 :2 1 :2 2 : . . . :2 (n−2) :2 (n−1) , when the display periods which are not non-display periods are lined up in order from the shortest.  
         [0338]    By combining the display periods which are not non-display periods, the desired gray scale display from among the 2 n  gray scales can be performed. The gray scale displayed by a pixel within one frame period is determined by finding the total sum of the lengths of the display periods for performing white display in one frame period. Note that, in embodiment 4, the brightness of a pixel becomes 100 when white display is performed in all of the display periods which are not non-display periods.  
         [0339]    If the display period which is the longest non-display period within one frame period is formed at the end of the frame period in the driving method of embodiment 4, then it becomes visible to a viewer that there is a cutoff of the frame period between the longest non-display period and the display period which appears next. Display irregularities, which occur due to adjoining display periods in neighboring frame periods when performing an intermediate gray scale display, can thus be made more difficult to recognize in the viewer&#39;s eyes.  
         [0340]    Further, it is very important to set the lengths of the non-display periods such that an arbitrary write in period does not mutually overlap with its two adjacent write in periods. For example, it is necessary that a write in period Tai does not overlap with a write in period Ta(i+2) and does not overlap with a write in period Ta(i−2).  
         [0341]    When adjacent write in periods overlap, it is necessary to write in the digital signal by selecting a first scanning line in one of the adjacent write in periods, and selecting a second scanning line in the other of the write in periods. However, there are no such limitations for cases in which adjacent write in periods do not overlap, and the first scanning lines may be selected in both write in periods, and the second scanning lines may be selected in both write in periods.  
         [0342]    It becomes possible with the present invention to perform write in of an arbitrary digital video signal, and the next digital video signal, to the pixels in parallel in accordance with the above stated method of driving. It also becomes possible to make the length of the display period shorter than the period for performing write in of the digital video signal to all of the pixels.  
         [0343]    In other words, it becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the present invention, in comparison with the conventional DMD time division gray scale display. Consequently, it becomes possible to make the number of image gray scales very high even if the write in speed of the digital video signal to the pixels is the same as that of the conventional.  
         [0344]    [Embodiment 5] 
         [0345]    A method of driving in which display is performed in accordance with a 6 bit digital video signal in the second structure DMD of the present invention is explained in embodiment 5 using FIG. 12. Note that the DMD of embodiment 5 has the structure shown in FIG. 5 and in FIGS. 7A and 7B. The horizontal axis shows a time scale in FIG. 12, while the vertical axis shows the position of a scanning line.  
         [0346]    The write in period Ta 1  begins in the DMD shown in FIG. 5, and the first bit of-the digital video signal is input to each pixel. Note that the input to the pixels of the digital video signal in embodiment 5 is performed similarly to that of the embodiment mode, and therefore an explanation of the detailed driving mechanism is omitted here.  
         [0347]    If the digital video signal and the inverted digital video signal are input to the first address electrodes  102   a  and to the second address electrodes  102   b , respectively, then the angles of the micromirrors of the pixels, with respect to the substrate, are selected in accordance with the “1” or “0” information in the digital video signal. Whether light from a light source is irradiated to a screen, or whether the light from the light source is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.  
         [0348]    On the other hand, the write in period Ta 2  begins either before or after the write in period Ta 1  is complete, and the second bit of the digital video signal is input to the pixels. The angles of the micromirrors of all of the pixels are then selected, and display is performed.  
         [0349]    A period until the second bit of the digital video signal is input to all of the pixels is the write in period Ta 2 .  
         [0350]    The above operations are repeated until the sixth bit of the digital video signal is input to the pixels. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Tr 1  to Tr 6  are periods from when the digital video signal is input to each line of pixels, until the next bit of the digital video signal is input to the same pixels. In particular, an arbitrary display period Tr of the first line of pixels is the same as a period from when an arbitrary write in period begins until the write in period to next appear begins.  
         [0351]    One image can be displayed when all of the display periods Tr 1  to Tr 6  are complete. A period in which one image is displayed is referred to as one frame period F in the present invention. Note that the frame period F differs for each line of pixels in the driving method of the present invention. The frame period of the final line of pixels begins when a time nearly as long as the write in period Ta 1  is passed, after the frame period of the first line of pixels begins.  
         [0352]    Note that the first write in period Ta 1  of the next frame period begins at the same time as the display period Tr 6  is completed, and that the above operations are repeated again.  
         [0353]    It is very important that the ratio of the lengths of the display periods be set such that they become 2 0 :2 1 :2 2 : . . . :2 4 :2 5  when the display periods Tr are lined up in order from the shortest. The desired gray scale display, from among 2 6  gray scales, can be performed by combining these display periods.  
         [0354]    The gray scale displayed in a pixel during one frame period is set in accordance with finding the total sum of the lengths of the display periods in which light is irradiated to the screen within one frame period. For example, if light irradiated to the screen in all of the display periods is taken as the pixels displaying a brightness of 100, then a gray scale of 19 can be expressed when light is irradiated to the screen only during the display periods corresponding to length ratios of 2 0  and 2 1 . If light is irradiated to the screen only during the display periods corresponding to length ratios of 2 2 , 2 4 , and 2 5 , then a gray scale of 56 can be expressed in the pixel.  
         [0355]    In addition, it is essential that an arbitrary write in period does not mutually overlap with its two neighboring write in periods. For example, it is necessary that a write in period Tai does not overlap with a write in period Ta(i+2) and does not overlap with a write in period Ta(i−2).  
         [0356]    Furthermore, although the first scanning line  147   a  and the second scanning line  147   b  are selected in order in write in periods appearing in succession in embodiment 5, it is not necessary to limit the present invention to this structure. For cases in which adjacent write in periods overlap, it is necessary to perform write in of the digital signal by selecting the first scanning line in one of the adjacent write in periods, and selecting the second scanning line in the other write in period. However, there is no such limitation for cases in which neighboring write in periods do not overlap, and the first scanning lines may be selected in both of the write in periods, and the second scanning lines may also be selected in both of the write in periods.  
         [0357]    It becomes possible with the present invention to perform write in of an arbitrary digital video signal, and the next digital video signal, to the pixels in parallel in accordance with the above stated method of driving. It also becomes possible to make the length of the display period shorter than the period for performing write in of the digital video signal to all of the pixels.  
         [0358]    In other words, it becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the present invention, in comparison with the conventional DMD time division gray scale display. Consequently, it becomes possible to make the number of image gray scales very high even if the write in speed of the digital video signal to the pixels is the same as that of the conventional.  
         [0359]    [Embodiment 6] 
         [0360]    A method of driving in which display of 2 8  gray scales is performed in accordance with an 8 bit digital video signal, using 10 display periods, in the second structure DMD of the present invention is explained in embodiment 6. Note that the DMD of embodiment 6 has the structure shown in FIG. 5 and in FIGS. 7A and 7B. The horizontal axis shows a time scale in FIG. 13, while the vertical axis shows the position of a scanning line.  
         [0361]    The write in period Ta 1  begins in the DMD shown in FIG. 5, and the first bit of the digital video signal is input to each pixel. Note that the input to the pixels of the digital video signal in embodiment 6 is performed similarly to that of the embodiment mode, and therefore an explanation of the detailed driving mechanism is omitted here.  
         [0362]    If the digital video signal and the inverted digital video signal are input to the first address electrodes  102   a  and to the second address electrodes  102   b , then the angles of the micromirrors of the pixels, with respect to the substrate, are selected in accordance with the “1” or “0” information in the digital video signal. Whether light from a light source is irradiated to a screen, or whether the light from the light source is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.  
         [0363]    On the other hand, the write in period Ta 2  begins either before or after the write in period Ta 1  is complete, and the second bit of the digital video signal is input to the pixels. The angles of the micromirrors of all of the pixels are then selected, and display is performed.  
         [0364]    A period until the second bit of the digital video signal is input to all of the pixels is the write in period Ta 2 .  
         [0365]    The above operations are repeated until the eighth bit of the digital video signal is input to the pixels. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Tr 1  to Tr 10  are periods from when the digital video signal is input to each line of pixels, until the next bit of the digital video signal is input to the same pixels. In particular, an arbitrary display period Tr of the first line of pixels is the same as a period from when an arbitrary write in period begins until the write in period to next appear begins.  
         [0366]    One image can be displayed when all of the display periods Tr 1  to Tr 10  are complete. A period in which one image is displayed is referred to as one frame period F in the present invention. Note that the frame period F differs for each line of pixels in the driving method of the present invention. The frame period of the final line of pixels begins when a time nearly as long as the write in period Ta 1  is passed, after the frame period of the first line of pixels begins.  
         [0367]    Note that the first write in period Ta 1  of the next frame period begins at the same time as the display period Tr 10  is completed, and that the above operations are repeated again.  
         [0368]    Note that, the same bit of the digital video signal are input to the pixels in the write in periods Ta 6 , Ta 8 , and Ta 10  in embodiment 6. The sixth bit of the digital video signal is input to the pixels in the write in periods Ta 6 , Ta 8 , and Ta 10  in embodiment 6.  
         [0369]    Further, the ratio of lengths of the display periods Tr 1  to tr 10  are set in embodiment 6 such that Tr 9 :Tr 7 :Tr 5 :Tr 3 :Tr 1 :Tr 2 :Tr 4 :(Tr 6 +Tr 8 +Tr 10 )=2 0 :2 1 :2 2 :2 3 :2 4 :2 5 :2 6 :2 7 . Note that the length ratios of the display periods are not limited to this order. The length ratios may be set so as to become 2 0 :2 1 : . . . :2 4 :2 7  for a case in which the display periods Tr 1  to Trn are arranged in order from the shortest.  
         [0370]    The three display periods Tr 6 , Tr 8 , and Tr 10  function as one display period in embodiment 6, and 2 8  gray scales of display are therefore performed. It is possible to perform display of a desired gray scale by combining the display periods Tr 1  to Tr 10 , from among 2 8  gray scales.  
         [0371]    The gray scale displayed in a pixel during one frame period is set in accordance with finding the total sum of the lengths of the display periods in which light is irradiated to the screen within one frame period. For example, if light irradiated to the screen in all of the display periods is taken as the pixels displaying a brightness of 100, then a gray scale of 19 can be expressed when light is irradiated to the screen only during the display periods corresponding to length ratios of 2 0  and 2 1 . If light is irradiated to the screen only during the display periods corresponding to length ratios of 2 2 , 2 4 , 2 5 , 2 7 , and 2 9 , then a gray scale of 55 can be expressed in the pixel.  
         [0372]    In addition, it is essential that an arbitrary write in period does not mutually overlap with its two neighboring write in periods. For example, it is necessary that a write in period Tai does not overlap with a write in period Ta(i+2) and does not overlap with a write in period Ta(i−2).  
         [0373]    Furthermore, although the first scanning line  147   a  and the second scanning line  147   b  are selected in order in write in periods appearing in succession in embodiment 6, it is not necessary to limit the present invention to this structure. For cases in which adjacent write in periods overlap, it is necessary to perform write in of the digital signal by selecting the first scanning line in one of the adjacent write in periods, and selecting the second scanning line in the other write in period. However, there is no such limitation for cases in which neighboring write in periods do not overlap, and the first scanning lines may be selected in both of the write in periods, and the second scanning lines may also be selected in both of the write in periods.  
         [0374]    It becomes possible with the present invention to perform write in of an arbitrary digital video signal, and the next digital video signal, to the pixels in parallel in accordance with the above stated method of driving. It also becomes possible to make the length of the display period shorter than the period for performing write in of the digital video signal to all of the pixels.  
         [0375]    [Embodiment 7] 
         [0376]    A method of driving in which display of 2 6  gray scales is performed in accordance with an 6 bit digital video signal, using 7 display periods, in the second structure DMD of the present invention is explained in embodiment 7. Note that the DMD of embodiment 7 has the structure shown in FIG. 5 and in FIGS.  7 A and  7 B. The horizontal axis shows a time scale in FIG. 14, while the vertical axis shows the position of a scanning line.  
         [0377]    First, in the write in period Ta 1  the first bit of the digital video signal is input to each pixel. Note that the input to the pixels of the digital video signal in embodiment 7 is performed similarly to that of the embodiment mode, and therefore an explanation of the detailed driving mechanism is omitted here.  
         [0378]    If the digital video signal and the inverted digital video signal are input to the first address electrodes  102   a  and to the second address electrodes  102   b , then the angles of the micromirrors of the pixels, with respect to the substrate, are selected in accordance with the “1” or “0” information in the digital video signal. Whether light from a light source is irradiated to a screen, or whether the light from the light source is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.  
         [0379]    On the other hand, the write in period Ta 2  either begins before or after the write in period Ta 1  is complete, and the second bit of the digital video signal is input to the pixels. The angles of the micromirrors of all of the pixels are then selected, and display is performed.  
         [0380]    A period until the second bit of the digital video signal is input to all of the pixels is the display period Ta 2 . When the second bit of the digital video signal is input to the pixels, then display is performed in each pixel.  
         [0381]    The above operations are repeated until the sixth bit of the digital video signal is input to the pixels. Note that the display periods Tr for performing actual display differ for each line of pixels in accordance with each bit of the digital video signal. The display periods Tr 1  to Tr 6  are periods from when the digital video signal is input to each line of pixels, until the next bit of the digital video signal is input to the same pixels. In particular, an arbitrary display period Tr of the first line of pixels is the same as a period from when an arbitrary write in period begins until the write in period to next appear begins.  
         [0382]    Next, the write in period Ta 7  begins next, before the write in period Ta 6  is complete. A digital signal (non-display signal) having information such that black display is performed in all of the pixels is input to each pixel in the write in period Ta 7  in embodiment 7. Differing from the digital video signal, the non-display signal does not have image information.  
         [0383]    All of the pixels are placed in a black display state when the non-display signal is input to each pixel. Display of the pixels therefore does not occur in the display period Tr 7 . The display period Tr 7  is a non-display period in embodiment 7.  
         [0384]    Next, the first write in period of the next frame period, the write in period Ta 1 , begins either before or after the write in period Ta 7  is complete. The display period Tr 7  is complete at the same time as Ta 1  of the next frame period begins, and one frame period is completed.  
         [0385]    One frame period is complete when all of the display periods are complete, and one image can be displayed. The number of non-display periods which appear is one, and therefore 7 display periods appear within one frame period.  
         [0386]    After one frame period is complete, the first bit of the digital video signal is again input to the pixels, and the display period Tr 1  begins. The above operations are then repeated.  
         [0387]    The display periods Tr 1 , Tr 2 , . . . , Tr 6 , and Tr 7  are periods from when the digital signal is written to the pixels in the write in periods Ta 1 , Ta 2 , . . . , Ta 6 , and Ta 7 , respectively, until the digital signal is again written to the pixels in the write in periods to next appear Ta 2 , Ta 3 , . . . , Ta(n+j), and Ta 1 .  
         [0388]    Further, from among the display periods Tr 1  to Tr 7 , the ratio of lengths of the display periods becomes 2 0 :2 1 :2 2 : . . . :2 4 :2 5  for a case in which the display periods Tr 1  to Tr 6 , which are not non-display periods, are arranged in order from the shortest.  
         [0389]    By combining the display periods which are not non-display periods, the desired gray scale display from among the 2 6  gray scales can be performed. The gray scale displayed by a pixel within one frame period is determined by finding the total sum of the lengths of the display periods for performing white display in one frame period. Note that, in embodiment 7, the brightness of a pixel becomes 100 when white display is performed in all of the display periods which are not non-display periods.  
         [0390]    For example, if light irradiated to the screen in all of the display periods is taken as the pixels displaying a brightness of 100, then a gray scale of 13 can be expressed in the pixels when light is irradiated to the screen only during the display periods corresponding to length ratios of 2 0 . If light is irradiated to the screen only during the display periods corresponding to length ratios of 2 2 , 2 4 , and 2 5 , then a gray scale of 78 can be expressed in the pixel.  
         [0391]    If the display period which is the longest non-display period within one frame period is formed at the end of the frame period in the driving method of embodiment 7, then it becomes visible to a viewer that there is a cutoff of the frame period between the longest non-display period and the display period which appears next. Display irregularities, which occur due to adjoining display periods in neighboring frame periods when performing an intermediate gray scale display, can thus be made more difficult to recognize in the viewer&#39;s eyes.  
         [0392]    Further, it is very important to set the lengths of the non-display periods such that an arbitrary write in period does not mutually overlap with its two adjacent write in periods. For example, it is necessary that a write in period Tai does not overlap with a write in period Ta(i+2) and does not overlap with a write in period Ta(i−2).  
         [0393]    When adjacent write in periods overlap, it is necessary to write in the digital signal by selecting a first scanning line in one of the adjacent write in periods, and selecting a second scanning line in the other of the write in periods. However, there are no such limitations for cases in which adjacent write in periods do not overlap, and the first scanning lines may be selected in both write in periods, and the second scanning lines may be selected in both write in periods.  
         [0394]    It becomes possible with the present invention to perform write in of an arbitrary digital video signal, and the next digital video signal, to the pixels in parallel in accordance with the above stated method of driving. It also becomes possible to make the length of the display period shorter than the period for performing write in of the digital video signal to all of the pixels.  
         [0395]    In other words, it becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the present invention, in comparison with the conventional DMD time division gray scale display. Consequently, it becomes possible to make the number of image gray scales very high even if the write in speed of the digital video signal to the pixels is the same as that of the conventional.  
         [0396]    [Embodiment 8] 
         [0397]    A detailed structure of a pixel of a DMD of the present invention is explained in embodiment 8.  
         [0398]    An example of a DMD used by the present invention is shown in FIG. 15. Reference numeral  104  denotes the micromirror, and the micromirror  104  is connected to a support post  124  of a yoke  123  by a micromirror support post  122 .  
         [0399]    The yoke  123  maintains a hinge  105 . Further, the hinge  105  is maintained by a post cap  125 . The post cap  125  is connected to a hinge support post connection portion  128  of a bias bus  129  by a hinge support post  106 . The bias bus  129  has a landing site  103 . The landing site  103  has insulating properties, and maintains the same electric potential as that of the micromirror  104 .  
         [0400]    Reference numeral  102   a  denotes the first address electrode, and reference numeral  102   b  denotes the second address electrode. The first address electrode  102   a  is connected to an electrode support post connection portion  131  of a first address electrode pad  126   a  by an electrode support post  130 . Further, the second address electrode  102   b  is also connected to the electrode support post connection portion  131  of a second address electrode pad  126   b  by the electrode support post  130 .  
         [0401]    A digital signal input to the first address electrode pad  126   a  from a first connection portion  127   a  is input to the first address electrode  102   a . A digital signal input to the second address electrode pad  126   b  from a second connection portion  127   b  is input to the second address electrode  102   b.    
         [0402]    The micromirror  104  is inclined in accordance with the digital signal&#39;s input to the first address electrode  102   a  and to the second address electrode  102   b , and white display or black display is selected. A portion of a yoke cantilever  132  may also contact the landing site  103  by the inclination of the micromirror  104 .  
         [0403]    It is possible to implement embodiment 8 by freely combining it with any of embodiments 1 to 7.  
         [0404]    [Embodiment 9] 
         [0405]    A structure of an SRAM used in the present invention is explained in embodiment 9.  
         [0406]    [0406]FIG. 16 shows an example of a circuit diagram of an SRAM. The SRAM has two each of p-channel transistors and n-channel transistors. Source regions of each of the p-channel transistors are connected to the high voltage side electric power source Vddh, while source regions of each of the n-channel transistors are connected to the low voltage side electric power source Vss. One p-channel transistor and one n-channel transistor form a pair, and two sets of the p-channel transistor and n-channel transistor pairs exist within one SRAM.  
         [0407]    The p-channel transistor and n-channel transistor pair are mutually connected by their drain regions. Further, the p-channel transistor and n-channel transistor pair are also mutually connected by their gate electrodes. The drain regions of one pair of the p-channel and the n-channel transistors are then maintained at the same electric potential as the gate electrodes of the other pair of the p-channel and the n-channel transistors. The drain regions of one pair of the p-channel and the n-channel transistors is connected to the input terminal Vin, and the drain region of the other pair of the p-channel and the n-channel transistors is connected to the output terminal Vout.  
         [0408]    The electric potential of Vin and the electric potential of Vout are inverted, with ground as a reference, with the SRAM. In other words, if Vin is HI, then Vout will become a LO signal corresponding to Vss, and if Vin is LO, then Vout will become a HI signal corresponding to Vddh.  
         [0409]    A structure of an SRAM used by the present invention and having a structure which differs from that of FIG. 16 is explained next.  
         [0410]    [0410]FIG. 17A shows an equivalent circuit diagram of an SRAM of embodiment 9. The SRAM has two p-channel transistors and two resistors. One p-channel transistor and one resistor become a pair, and two sets of p-channel transistor and resistor pairs exist within one SRAM. The source region of the p-channel transistor is connected to the high voltage side electric power source Vddh, and the drain region is connected to the low voltage side electric power source Vss through the resistor.  
         [0411]    The drain regions of the p-channel transistors are mutually maintained at the same electric potential as the gate electrodes of the other p-channel transistors. The drain region of one of the p-channel transistors is connected to the input terminal Vin, and the drain region of the other p-channel transistor is connected to the output terminal Vout.  
         [0412]    The electric potential of Vin and the electric potential of Vout are inverted, with ground as a reference, with the SRAM. In other words, if Vin is HI, then Vout will become a LO signal corresponding to Vss, and if Vin is LO, then Vout will become a HI signal corresponding to Vddh.  
         [0413]    It is possible that the SRAM of embodiment 9 form resistors at the same time as the p-channel transistors are formed, and therefore it is not necessary to form any n-channel transistors. The number of process steps can be reduced compared to the SRAM shown by FIG. 16.  
         [0414]    [0414]FIG. 17B shows an equivalent circuit diagram of an SRAM of embodiment 9. The SRAM has two n-channel transistors and two resistors. One n-channel transistor and one resistor become a pair, and two sets of n-channel transistor and resistor pairs exist within one SRAM. The drain region of the n-channel transistor is connected to the high voltage side electric power source Vddh, and the source region is connected to the low voltage side electric power source Vss through the resistor.  
         [0415]    The drain regions of the n-channel transistors are mutually maintained at the same electric potential as the gate electrodes of the other n-channel transistors. The drain region of one of the n-channel transistors is connected to the input terminal Vin, and the drain region of the other n-channel transistor is connected to the output terminal Vout.  
         [0416]    The electric potential of Vin and the electric potential of Vout are inverted, with ground as a reference, with the SRAM. In other words, if Vin is HI, then Vout will become a LO signal corresponding to Vss, and if Vin is LO, then Vout will become a HI signal corresponding to Vddh.  
         [0417]    It is possible that the SRAM of embodiment 9 forms resistors at the same time as the n-channel transistors are formed, and therefore it is not necessary to form any p-channel transistors. The number of process steps can be reduced compared to the SRAM shown by FIG. 16.  
         [0418]    Note that SRAMs capable of being used in the present invention are not limited to those having the above structures. It is possible to use any type of SRAM, provided that it has a structure such that the electric potential of Vin and the electric potential of Vout are inverted, with ground as a reference, It is possible to implement embodiment 9 by freely combining it with any of embodiments 1 to 8.  
         [0419]    [Embodiment 10] 
         [0420]    A projector (DLP) using a DMD of the present invention is explained in embodiment 10.  
         [0421]    Shown in FIG. 18A is a schematic diagram of a one chip projector using one DMD. A light source  801 , condenser lenses  802  and  803 , a rotating color foil  804 , a DMD  805 , a projecting lens  806 , a light absorber  807 , and a screen  808  are formed as shown in FIG. 18A.  
         [0422]    The DMD  805  irradiates light emitted from the light source  801  to the screen  808 , or to the light absorber  807 , in accordance with the information of an input digital video signal.  
         [0423]    [0423]FIG. 18B is a diagram showing a structure of the rotating color foil  804 , which has three color filters, R (red), G (green), and B (blue). One color image is formed by projecting R (red) images, G (green) images, and B (blue) images to the screen  808  in succession.  
         [0424]    [0424]FIG. 18C is a diagram showing a structure of the rotating color foil  804  which differs from that of FIG. 18B. The rotating color foil  804  has color filters in the three colors of R (red), G (green) and B (blue), and also a W (transparent) color filter. One color image is formed by projecting R (red) images, G (green) images, and B (blue) images to the screen  808  in succession. The rotating color foil shown in FIG. 18C differs from the rotating color foil shown in FIG. 18B and it also has the W (transparent) color filter. By forming the transparent color filter, it becomes possible to increase the brightness by approximately 37% over that of the rotating color foil shown in FIG. 18B.  
         [0425]    The one chip projector is completed with one DMD chip, and therefore the cost of the DLP can be reduced.  
         [0426]    A schematic diagram of a two chip projector, using two DMDs, is shown next in FIG. 19A. A light source  811 , a condenser lens  812 , a rotating color foil  813 , a red DMD  814 , a blue/green DMD  815 , a color separating/color combining prism  816 , a projecting lens  817 , and a screen  818  are provided as shown in FIG. 19A.  
         [0427]    Note that, although a light absorber is not shown in FIG. 19A, light absorbers are formed in both the red DMD  814  and in the blue/green DMD  815 . The red DMD  814  and the blue/green DMD  815  irradiate light emitted form the light source  811  to the screen  818 , or to the light absorbers, in accordance with information contained in an input digital video signal.  
         [0428]    The rotating color foil  813  has magenta and yellow color foils.  
         [0429]    Light from the light source  811  normally passes through the rotating color foil  813 . Red color light from the light which has passed through the rotating color foil  813  is separated out by the color separating/color combing prism  816 , and irradiated to the red DMD  814 . Light used to form an image from the light reflected in the red color DMD  814  is made incident to the projecting lens  817 . Time division gray scale display using one frame period is thus performed for a red color image.  
         [0430]    Further, blue color and green color light are each separated by the magenta and yellow color filters, respectively, and are sent to the blue color and green color DMD  815  by the color separating/color combining prism  816 . Time division gray scale display using one-half of one frame period is thus performed for each of the colors.  
         [0431]    Next, a schematic diagram of a three chip projector, using three DMDs, is shown in FIG. 19B. A light source  821 , a condenser lens  822 , a green DMD  823 , a red DMD  824 , a blue DMD  825 , a color separating/color combining prism  826 , a projecting lens  827 , and a screen  828  are formed as shown in FIG. 19B.  
         [0432]    Note that, although a light absorber is not shown in FIG. 19B, light absorbers are formed in the green DMD  823 , in the red DMD  824 , and in the blue DMD  825 , respectively. The green DMD  823 , the red DMD  824 , and the blue DMD  825  irradiate light emitted form the light source  821  to the screen  828 , or to the light absorbers, in accordance with information contained in an input digital video signal.  
         [0433]    The light from the light source  821  is reflected by DMDs specialized for RGB, undergoes an additive color process by the projecting lens, and is then displayed as a color image for the case of the three chip projector. This type of projector has high image quality and high efficiency, and is mainly used in high end projectors.  
         [0434]    Note that it is possible to use the DMD of the present invention in other electronic devices, such as a printer and a photocopier, in addition to a projector.  
         [0435]    It is possible to implement embodiment 10 by freely combining it with any of embodiments 1 to 9.  
         [0436]    It becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the present invention, in comparison with the conventional DMD time division gray scale display. Consequently, it becomes possible to make the number of image gray scales very high even if the write in speed of the digital video signal to the pixels is the same as that of the conventional.