Abstract:
A semiconductor memory device includes an all bank select signal generation block configured to receive level signals including information on at least one bank which has been refreshed, and generate all bank select signals, in response to an all bank refresh command; and a bank block including a plurality of banks which are configured to be refreshed in response to the all bank select signals or are refreshed in response to per bank select signals which are enabled when the level signals are enabled.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C 119(a) to Korean Patent Application No. 10-2012-0053907 filed on May 21, 2012 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety set forth in full. 
       BACKGROUND 
       [0002]    1. Field of Invention 
         [0003]    Various embodiments of the present invention generally relate to a semiconductor memory device having a bank, and more particularly, to refreshing the bank of the semiconductor memory device and method of performing the same. 
         [0004]    2. Description of Related Art 
         [0005]    In general, in a semiconductor memory device, data signals are read as ‘1’ or ‘0’ according to amounts of charges accumulated in a plurality of memory cells in which the data signals are recorded. In this regard, since the charges accumulated in the memory cells are discharged as time goes by, it is difficult to determine a ‘1’ or ‘0’. Thus, an auto refresh operation for amplifying the data signals recorded in the memory cells and re-recording the data signals in the memory cells is performed. 
         [0006]    Auto refresh is divided into per bank refresh in which refresh is performed for respective banks of a semiconductor memory device and all bank refresh in which refresh is performed for all banks of the semiconductor memory device. 
         [0007]      FIG. 1  is a block diagram a conventional semiconductor memory device in which auto refresh is performed. 
         [0008]    Referring to  FIG. 1 , a semiconductor memory device includes a per bank refresh block  10  which receives a per bank refresh command PBR_CMD and generates per bank select signals PER_BS&lt;1:4&gt; enabled, an all bank refresh block  20  which receives an all bank refresh command ABR_CMD and generates an all bank select signal ALL_BS enabled, and a bank block  30  in which first to fourth banks  31  to  34 , respectively, are respectively refreshed in the case where the per bank select signals PER_BS&lt;1:4&gt; are enabled and all of the first to fourth banks  31  to  34 , respectively, are refreshed in the case where the all bank select signal ALL_BS is enabled. 
         [0009]    Operations of the semiconductor memory device configured as mentioned above will be described with reference to  FIG. 1 , assuming that, after the first and second banks  31  and  32 , respectively, are refreshed by receiving the per bank refresh command PBR_CMD, the all bank refresh command ABR_CMD is inputted. 
         [0010]    First, the per bank refresh block  10  receives the per bank refresh command PBR_CMD, and enables the first and second per bank select signals PER_BS&lt;1:2&gt; and disables the third and fourth per bank select signals PER_BS&lt;3:4&gt;. The first and second banks  31  and  32 , respectively, receive the enabled first and second per bank select signals PER_BS&lt;1:2&gt; and are refreshed. The third and fourth banks  33  and  34 , respectively, receive the disabled third and fourth per bank select signals PER_BS&lt;3:4&gt; and are not refreshed. 
         [0011]    Then, the all bank refresh block  20  receives the all bank refresh command ABR_CMD and enables the all bank select signal ALL_BS. The first to fourth banks  31  to  34  receive the enabled all bank select signal ALL_BS and are all refreshed. 
         [0012]    In the semiconductor memory device configured in this way, in the case where the all bank refresh command ABR_CMD is inputted after the per bank refresh command PBR_CMD is inputted and the first and second banks  31  and  32 , respectively, are refreshed, all of the first to fourth banks  31  to  34 , respectively, are refreshed. Thus, since the first and second banks  31  and  32 , respectively, are refreshed again, unnecessary current consumption is caused. 
       SUMMARY 
       [0013]    An embodiment of the present invention generally relates to a semiconductor memory device in which a bank having undergone refresh is prevented from being repeatedly refreshed to reduce unnecessary current consumption. 
         [0014]    In an embodiment, a semiconductor memory device includes: an all bank select signal generation block configured to receive level signals including information on at least one bank which has been refreshed, and generate all bank select signals, in response to an all bank refresh command; and a bank block including a plurality of banks which are configured to be refreshed in response to the all bank select signals or are refreshed in response to per bank select signals which are enabled when the level signals are enabled. 
         [0015]    In an embodiment, a semiconductor memory device includes: a bank selection unit configured to store level signals including information on at least one bank which has been refreshed in response to a first pulse signal enabled when a per bank refresh command is inputted, and generate per bank select signals which are enabled when the level signals are enabled; a signal transfer unit configured to transfer the level signals in response to a second pulse signal enabled when an all bank refresh command is inputted, and generate all bank select signals; and a bank block including a plurality of banks which are configured to be refreshed in response to the per bank select signals or the all bank select signals. 
         [0016]    In an embodiment, a refresh method includes: a first action of storing first and second level signals which are enabled in response to a per bank refresh command, and selecting banks to refresh, according to first and second per bank select signals which are enabled when the first and second level signals are enabled; and a second action of selecting banks to refresh, according to first and second all bank select signals which are generated by transferring the first and second level signals in response to an all bank refresh command. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The above and other aspects, features and other advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0018]      FIG. 1  is a block diagram showing a conventional semiconductor memory device in which auto refresh is performed; 
           [0019]      FIG. 2  is a block diagram showing the configuration of a semiconductor memory device in accordance with an embodiment; 
           [0020]      FIG. 3  is a circuit diagram of the bank selection unit included in the per bank select signal generation block shown in  FIG. 2 ; and 
           [0021]      FIG. 4  is a circuit diagram of the signal transfer unit included in the all bank select signal generation block shown in  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings. However, the embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. 
         [0023]      FIG. 2  is a block diagram showing the configuration of a semiconductor memory device in accordance with an embodiment. 
         [0024]    Referring to  FIG. 2 , a semiconductor memory device in accordance with an embodiment may include a per bank select signal generation block  40 , an all bank select signal generation block  50 , an address generation block  60 , and a bank block  70 . 
         [0025]    The per bank select signal generation block  40  may include a first pulse signal generation unit  41  configured to receive a per bank refresh command PBR_CMD and generate a first pulse signal PER_PUL which is enabled, and a bank selection unit  42  configured to receive the first pulse signal PER_PUL and generate first to fourth level signals LEV&lt;1:4&gt; which are enabled, and generate first to fourth per bank select signals BS 1 &lt;1:4&gt; which are enabled, when the first to fourth level signals LEV&lt;1:4&gt; are enabled. 
         [0026]    Additionally, the configuration of the bank selection unit  42  will be described below with reference to  FIG. 3 . 
         [0027]    Referring to  FIG. 3 , the bank selection unit  42  may include a first bank selecting section  420  configured to receive the first pulse signal PER_PUL, buffer a power supply voltage VDD and generate the first level signal LEV&lt; 1 &gt; and the first per bank select signal BS 1 &lt; 1 &gt;. The bank selection unit  42  may include a second bank selecting section  421  configured to receive the first pulse signal PER_PUL, buffer the first level signal LEV&lt; 1 &gt; and generate the second level signal LEV&lt; 2 &gt; and the second per bank select signal BS 1 &lt; 2 &gt;. The bank selection unit  42  may include a third bank selecting section  422  configured to receive the first pulse signal PER_PUL, buffer the second level signal LEV&lt; 2 &gt; and generate the third level signal LEV&lt; 3 &gt; and the third per bank select signal BS 1 &lt; 3 &gt;. The bank selection unit  42  may include a fourth bank selecting section  423  configured to receive the first pulse signal PER_PUL, buffer the third level signal LEV&lt; 3 &gt; and generate the fourth level signal LEV&lt; 4 &gt; and the fourth per bank select signal BS 1 &lt; 4 &gt;. 
         [0028]    The first bank selecting section  420  may include a first latch part  4200  configured to latch the power supply voltage VDD transferred to a first node nd 40  when the first pulse of the first pulse signal PER_PUL is inputted, buffer the power supply voltage VDD and generate the first level signal LEV&lt; 1 &gt; enabled from a logic low level to a logic high level. The first bank selecting section  420  may include a first logic part  4201  configured to generate the first per bank select signal BS 1 &lt; 1 &gt; which may be enabled when the first level signal LEV&lt; 1 &gt; is enabled from the logic low level to the logic high level. 
         [0029]    The second bank selecting section  421  may include a second latch part  4210  configured to latch the first level signal LEV&lt; 1 &gt; transferred to a second node nd 41  when the second pulse of the first pulse signal PER_PUL is inputted, buffer the first level signal LEV&lt; 1 &gt; and generate the second level signal LEV&lt; 2 &gt; enabled from a logic low level to a logic high level. The second bank selecting section  421  may include a second logic part  4211  configured to generate the second per bank select signal BS 1 &lt; 2 &gt; which may be enabled when the second level signal LEV&lt; 2 &gt; is enabled from the logic low level to the logic high level. 
         [0030]    The third bank selecting section  422  may include a third latch part  4220  configured to latch the second level signal LEV&lt; 2 &gt; transferred to a third node nd 42  when the third pulse of the first pulse signal PER_PUL is inputted, buffer the second level signal LEV&lt; 2 &gt; and generate the third level signal LEV&lt; 3 &gt; enabled from a logic low level to a logic high level. The third bank selecting section  422  may include a third logic part  4221  configured to generate the third per bank select signal BS 1 &lt; 3 &gt; which may be enabled when the third level signal LEV&lt; 3 &gt; is enabled from the logic low level to the logic high level. 
         [0031]    The fourth bank selecting section  423  may include a fourth latch part  4230  configured to latch the third level signal LEV&lt; 3 &gt; transferred to a fourth node nd 43  when the fourth pulse of the first pulse signal PER_PUL is inputted, buffer the third level signal LEV&lt; 3 &gt; and generate the fourth level signal LEV&lt; 4 &gt; enabled from a logic low level to a logic high level. The fourth bank selecting section  423  may include a fourth logic part  4231  configured to generate the fourth per bank select signal BS 1 &lt; 4 &gt; which may be enabled when the fourth level signal LEV&lt; 4 &gt; is enabled from the logic low level to the logic high level. 
         [0032]    The bank selection unit  42  further may include an initializing signal generating section  424  configured to NOR a reset signal RST, the fourth level signal LEV&lt; 4 &gt; and a second pulse signal ALL_PUL and generate an initializing signal RSTB for initializing the first to fourth nodes nd 40  to nd 43  to logic low levels. The reset signal RST is a signal which may be enabled during a power-up period in which the level of an internal voltage of the semiconductor memory device rises according to the level of the power supply voltage VDD. That is to say, the bank selection unit  42  may initialize the first to fourth nodes nd 40  to nd 43  to the logic low levels and disable the first to fourth level signals LEV&lt;1:4&gt;, during the power-up period and in the case where the fourth level signal LEV&lt; 4 &gt; is enabled and the second pulse signal ALL_PUL is enabled. 
         [0033]    Referring to  FIG. 2 , the all bank select signal generation block  50  may include a second pulse signal generation unit  51  configured to receive an all bank refresh command ABR_CMD and generate the second pulse signal ALL_PUL which is enabled, and a signal transfer unit  52  configured to receive the second pulse signal ALL_PUL, inversion-buffer the first to fourth level signals LEV&lt;1:4&gt; and generate first to fourth all bank select signals BS 2 &lt;1:4&gt;. 
         [0034]    Additionally, the configuration of the signal transfer unit  52  will be described below with reference to  FIG. 4 . 
         [0035]    Referring to  FIG. 4 , the signal transfer unit  52  may include a first buffer section  520  configured to receive the second pulse signal ALL_PUL, inversion-buffer the first level signal LEV&lt; 1 &gt; and generate the first all bank select signal BS 2 &lt; 1 &gt;. The signal transfer unit  52  may include a second buffer section  521  configured to receive the second pulse signal ALL_PUL, inversion-buffer the second level signal LEV&lt; 2 &gt; and generate the second all bank select signal BS 2 &lt; 2 &gt;. The signal transfer unit  52  may include a third buffer section  522  configured to receive the second pulse signal ALL_PUL, inversion-buffer the third level signal LEV&lt; 3 &gt; and generate the third all bank select signal BS 2 &lt; 3 &gt;. The signal transfer unit  52  may include a fourth buffer section  523  configured to receive the second pulse signal ALL_PUL, inversion-buffer the fourth level signal LEV&lt; 4 &gt; and generate the fourth all bank select signal BS 2 &lt; 4 &gt;. 
         [0036]    The address generation block  60  may be configured to count and generate internal addresses ADD&lt;1:N&gt; in the case where the first pulse signal PER_PUL or the second pulse signal ALL_PUL is inputted. 
         [0037]    The bank block  70  may include a first bank  71  configured to be refreshed according to a combination of the internal addresses ADD&lt;1:N&gt; when the first per bank select signal BS 1 &lt; 1 &gt; or the first all bank select signal BS 2 &lt; 1 &gt; is enabled. The bank block  70  may include a second bank  72  configured to be refreshed according to a combination of the internal addresses ADD&lt;1:N&gt; when the second per bank select signal BS 1 &lt; 2 &gt; or the second all bank select signal BS 2 &lt; 2 &gt; is enabled. The bank block  70  may include a third bank  73  configured to be refreshed according to a combination of the internal addresses ADD&lt;1:N&gt; when the third per bank select signal BS 1 &lt; 3 &gt; or the third all bank select signal BS 2 &lt; 3 &gt; is enabled. The bank block  70  may include a fourth bank  74  configured to be refreshed according to a combination of the internal addresses ADD&lt;1:N&gt; when the fourth per bank select signal BS 1 &lt; 4 &gt; or the fourth all bank select signal BS 2 &lt; 4 &gt; is enabled. 
         [0038]    The refresh operation of the semiconductor memory device configured as mentioned above will be described with reference to  FIGS. 2 to 4 , this example is where the all bank refresh command ABR_CMD is inputted while the refresh operation is performed by receiving the per bank refresh command PBR_CMD, that is, where the all bank refresh command ABR_CMD is inputted after the first and second banks  71  and  72  are refreshed by the per bank refresh command PBR_CMD. 
         [0039]    First, the first pulse signal generation unit  41  of the per bank select signal generation block  40  receives the per bank refresh command PBR_CMD firstly inputted and generates the first pulse signal PER_PUL to a logic high level. 
         [0040]    The first bank selecting section  420  of the bank selection unit  42  receives the first pulse signal PER_PUL of the logic high level, buffers the power supply voltage VDD and generates the first level signal LEV&lt; 1 &gt; which is enabled from the logic low level to the logic high level, and generates the first per bank select signal BS 1 &lt; 1 &gt; to a logic high level. The second to fourth bank selecting sections  421  to  423  generate the second to fourth level signals LEV&lt;2:4&gt; of the logic low levels and the second to fourth per bank select signals BS 1 &lt;2:4&gt; of logic low levels. 
         [0041]    The address generation block  60  receives the first pulse signal PER_PUL of the logic high level and counts the internal addresses ADD&lt;1:N&gt;. 
         [0042]    The first bank  71  of the bank block  70  receives the first per bank select signal BS 1 &lt; 1 &gt; of the logic high level and is refreshed according to the combination of the internal addresses ADD&lt;1:N&gt;. The second to fourth banks  72  to  74  receive the second to fourth per bank select signals BS 1 &lt;2:4&gt; of the logic low levels and are not refreshed. 
         [0043]    Next, the first pulse signal generation unit  41  of the per bank select signal generation block  40  receives the per bank refresh command PBR_CMD secondly inputted and generates the first pulse signal PER_PUL to the logic high level. 
         [0044]    The first bank selecting section  420  of the bank selection unit  42  receives the first pulse signal PER_PUL of the logic high level, and generates the first level signal LEV&lt; 1 &gt; of the logic high level and the first per bank select signal BS 1 &lt; 1 &gt; of a logic low level. The second bank selecting section  421  of the bank selection unit  42  receives the first pulse signal PER_PUL of the logic high level, buffers the first level signal LEV&lt; 1 &gt; of the logic high level and generates the second level signal LEV&lt; 2 &gt; which transitions from the logic low level to the logic high level, and generates the second per bank select signal BS 1 &lt; 2 &gt; to a logic high level. The third and fourth bank selecting sections  422  and  423  generate the third and fourth level signals LEV&lt; 3 : 4 &gt; of the logic low levels and the third and fourth per bank select signals BS 1 &lt;3:4&gt; of the logic low levels. 
         [0045]    The address generation block  60  receives the first pulse signal PER_PUL of the logic high level and counts the internal addresses ADD&lt;1:N&gt;. 
         [0046]    The first bank  71  of the bank block  70  receives the first per bank select signal BS 1 &lt; 1 &gt; of the logic low level and is not refreshed. The second bank  72  of the bank block  70  receives the second per bank select signal BS 1 &lt; 2 &gt; of the logic high level and is refreshed according to the combination of the internal addresses ADD&lt;1:N&gt;. The third and fourth banks  73  and  74  receive the third and fourth per bank select signals BS 1 &lt;3:4&gt; of the logic low levels and are not refreshed. 
         [0047]    Then, the second pulse signal generation unit  51  of the all bank select signal generation block  50  receives the all bank refresh command ABR_CMD and generates the second pulse signal ALL_PUL to a logic high level. 
         [0048]    The first buffer section  520  of the signal transfer unit  52  receives the second pulse signal ALL_PUL of the logic high level, inversion-buffers the first level signal LEV&lt; 1 &gt; of the logic high level and generates the first all bank select signal BS 2 &lt; 1 &gt; of a logic low level. The second buffer section  521  of the signal transfer unit  52  receives the second pulse signal ALL_PUL of the logic high level, inversion-buffers the second level signal LEV&lt; 2 &gt; of the logic high level and generates the second all bank select signal BS 2 &lt; 2 &gt; of a logic low level. The third buffer section  522  of the signal transfer unit  52  receives the second pulse signal ALL_PUL of the logic high level, inversion-buffers the third level signal LEV&lt; 3 &gt; of the logic low level and generates the third all bank select signal BS 2 &lt; 3 &gt; of a logic high level. The fourth buffer section  523  of the signal transfer unit  52  receives the second pulse signal ALL_PUL of the logic high level, inversion-buffers the fourth level signal LEV&lt; 4 &gt; of the logic low level and generates the fourth all bank select signal BS 2 &lt; 4 &gt; of a logic high level. 
         [0049]    The address generation block  60  receives the second pulse signal ALL_PUL of the logic high level and counts the internal addresses ADD&lt;1:N&gt;. 
         [0050]    The first bank  71  of the bank block  70  receives the first all bank select signal BS 2 &lt; 1 &gt; of the logic low level and is not refreshed. The second bank  72  of the bank block  70  receives the second all bank select signal BS 2 &lt; 2 &gt; of the logic low level and is not refreshed. The third bank  73  of the bank block  70  receives the third all bank select signal BS 2 &lt; 3 &gt; of the logic high level and is refreshed according to the combination of the internal addresses ADD&lt;1:N&gt;. The fourth bank  74  of the bank block  70  receives the fourth all bank select signal BS 2 &lt; 4 &gt; of the logic high level and is refreshed according to the combination of the internal addresses ADD&lt;1:N&gt;. 
         [0051]    As is apparent from the above descriptions, in the semiconductor memory device in accordance with an embodiment, information on banks which have been refreshed in a per bank refresh operation is stored, and the banks which have been refreshed in the per bank refresh operation are not refreshed in an all bank refresh operation, whereby it is possible to reduce unnecessary current consumption. 
         [0052]    The embodiments have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.