Abstract:
A slave circuit of a LIN bus and method for operating a slave circuit is provided. The slave circuit includes a receiver circuit that is connected to the bus in order to output bit sequences as a function of a bus voltage, an interface circuit for controlling a sleep mode and a normal mode, a detector circuit for evaluating the bus voltage which is connected to the bus, a timer device that is connected to an output of the detector circuit and to the interface circuit. Whereby, the detector circuit, the timer device, and the interface circuit are designed to detect an exceedance of a time threshold by a waveform of the bus voltage of the bus, and to continue a sleep mode in the event of an exceedance, wherein the time threshold is greater than the duration of a wake-up command.

Description:
This nonprovisional application claims priority to German Patent Application No. 10 2008 053 534.6, which was filed in Germany on Oct. 28, 2008, and which is herein incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a slave circuit of a LIN bus and a method for operation. 
     2. Description of the Background Art 
     A LIN bus (LIN=Local Interconnect Network) is a type of fieldbus. The LIN bus was developed for the communication of intelligent sensors and actuators in motor vehicles. Typical application examples include networking within a door or a seat. A LIN is composed of a LIN master and one or more LIN slaves. The LIN master has knowledge about the time sequence of all data to be transmitted. This data is transmitted by the appropriate LIN slaves when they are requested to do so by the LIN master. The request takes place through the transmission of a header that is characterized by a specific message address. In this context, the header is transmitted by the master. The slave then places the data bytes on the bus after the header. 
     A LIN transceiver provides the physical bus coupling. A level below 40% of the supply voltage is interpreted by the receiver as a logic zero. Receivers interpret levels greater than 60% of the supply voltage as logic one. In terms of circuitry, a LIN cluster corresponds to an open-collector circuit. A pull-up resistor ensures that the bus level is close to the supply voltage (high level) when the transmitting transistors of all LIN nodes are off. The bus level is pulled close to ground (low level) as soon as a transmitting transistor is on. Accordingly, the low state is called the dominant level, and the high state is called the recessive level. 
     The LIN specification has two network node states: sleep mode and normal mode. The transition between the two modes is initiated either by an explicit command from the LIN master or via a wake-up signal frame from the LIN master or one of the LIN slaves. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to improve a slave circuit of a LIN bus to the greatest extent possible. Accordingly, a slave circuit of a LIN bus is provided. The slave circuit can be designed as a transceiver to receive and transmit information over the LIN bus. 
     The slave circuit can have a receiver circuit that is connectable to the bus, in particular through a filter. The receiver circuit is designed to output bit sequences as a function of a bus voltage on the bus. The slave circuit can have an interface circuit, which is designed to control a sleep mode and a normal mode. The interface circuit can be connected to an output of the receiver circuit. 
     The slave circuit can have a detector circuit for evaluating the bus voltage. The detector circuit can be connected to the bus, for example, through the filter. 
     The slave circuit can have a timer device that is connected to the output of the detector circuit and to the interface circuit. The timer device can have a counter to count time units in order to determine processes in time. 
     The timer device and the interface circuit can be designed to detect when a time threshold by a waveform of a bus voltage of the bus is exceeded. The time behavior of the bus voltage can therefore be evaluated by comparators. The detector circuit, the timer device, and the interface circuit can be designed to continue a sleep mode in the event that the time threshold is exceeded. The time threshold here is greater than the duration of a wake-up command. The duration of the wake-up command is defined as a 5-millisecond dominant level (low level) as a function of the LIN specification. The time threshold is advantageously greater than 6 milliseconds, preferably 10 milliseconds. For example, a dominant level of 10 milliseconds or longer then results in an exceedance of the time threshold. Consequently, no valid wake-up command is detected, and the sleep mode is continued. 
     The invention has the additional object of specifying a method for operating a slave circuit on a LIN bus that is improved to the greatest degree possible. Accordingly, a method for operating a slave circuit on a LIN bus is provided. 
     A bus voltage on the LIN bus is monitored by the slave circuit. The monitoring can take place on a continuous-time basis in that the bus voltage is measured continuously by the slave circuit, for example by comparators. 
     The slave circuit detects when the bus voltage falls below a first threshold value. The bus voltage is advantageously compared with the first threshold value by means of a comparator. A wake-up detection phase for the detection of valid commands to wake up the slave circuit is started as a function of the determination that the value has fallen below the threshold. Such commands can be generated by a master circuit or another slave circuit of the LIN bus, for example. 
     A time duration of the bus voltage falling below at least one second threshold value is evaluated by the slave circuit in the wake-up detection phase. Time units for determining the time duration are advantageously counted by the slave circuit starting when the value falls below the second threshold, with the counter advantageously being stopped when the value exceeds the first and/or second threshold. 
     The slave circuit is awakened from a sleep mode into a normal mode when the time duration of the drop below the second threshold during the wake-up detection phase is associated with a wake-up command. For example, if the time duration of the drop below the threshold is less than ten milliseconds, this time duration is associated with a valid wake-up command and the slave circuit is then preferably initialized. 
     In contrast, the sleep mode of the slave circuit is continued if the time duration of the drop below the second threshold during the wake-up detection phase is not associated with the wake-up command. For example, the time duration of the drop below the threshold is longer than ten milliseconds, so that the drop below the threshold is not equivalent to a valid wake-up command. 
     The improvements described below relate both to the slave circuit and to the method for operating a slave circuit. Features of the method are evident here from functions of the circuit. Functions of the circuit are evident from features of the method. 
     According to an embodiment, the slave circuit can have an additional timer device. The additional timer device is connectable to the output of the receiver circuit and to the interface circuit. 
     According to an embodiment, the second threshold value can be lower than the first threshold value. Accordingly, the bus voltage with a falling voltage first drops below the first threshold value and then drops below the second threshold value as the voltage continues to fall. 
     In an embodiment, provision is made that the detector circuit has a first, for example, analog comparator for comparing the bus voltage with a second threshold value. 
     According to an embodiment, the receiver circuit can have a second comparator. The second comparator can be designed as a window comparator. The second comparator can have at least one second threshold value. For example, the two second threshold values of 40% and 60% constitute the window of the window comparator. 
     The receiver circuit, the interface circuit, and the additional timer device can be designed to determine the wake-up command by comparing the time behavior of the bus voltage of the bus to a minimum time duration. In advantageous fashion, the interface circuit and/or the additional timer device are designed to control the normal mode in the event a wake-up command is determined. 
     According to an embodiment, the slave circuit can be designed to compare the time duration of the drop below the second threshold value to a time threshold for the purpose of evaluation. It is advantageous for the time threshold to be 10 milliseconds. 
     The slave circuit can be awakened from the sleep mode into the normal mode when the time duration of the drop below the second threshold is less than the time threshold. In contrast, the sleep mode of the slave circuit is preferably continued if the time duration of the drop below the second threshold is greater than the time threshold. 
     According to an embodiment, a time duration is measured during the wake-up detection phase, triggered by the drop below the first threshold value. For this purpose, a timer is advantageously started when the value drops below the first threshold value. 
     At the end of the time duration, the slave circuit detects whether the bus voltage has fallen below the second threshold value, or has failed to fall below it. A piece of information associated with the drop below, or the failure to drop below, the second threshold value is preferably stored in the slave circuit in a nonvolatile manner. 
     A mode of the slave circuit is controllable as a function of the stored information. The control takes place when the bus voltage again exceeds the first threshold value and/or the second threshold value after having fallen therebelow. 
     In an embodiment, the sleep mode is continued by the controller when the stored information corresponds to the bus voltage failing to drop below the second threshold value. In contrast, the controller advantageously initiates a safe mode when the stored information corresponds to the bus voltage dropping below the second threshold value. In the safe mode, the interface circuit is active. In contrast, a processing unit—for example a microcontroller—connected to the interface circuit is initially still deactivated. The interface circuit subsequently wakes up the processing unit. The processing unit signals the normal mode (active mode) with an enable signal to the interface circuit. The safe mode is also initiated when the supply voltage is turned on. 
     Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein: 
         FIG. 1  is a block diagram with a slave circuit of a LIN; 
         FIGS. 2   a ,  2   b  and  2   c  illustrate schematic diagrams; and 
         FIGS. 3   a ,  3   b  and  3   c  illustrate schematic diagrams. 
     
    
    
     DETAILED DESCRIPTION 
     Shown in  FIG. 1  is a block diagram with a slave circuit  100  (slave) and a master circuit  200  on a LIN bus LIN. The master circuit  200  (master) is connected to the LIN bus LIN. The LIN bus LIN is connected to the supply voltage VDD, for example through a resistor R (pull-up) connected to an output  201  of the master circuit. The LIN bus LIN has a recessive level (high state) when the transistor MN is off. If the transistor MN is in a conducting state, it connects the LIN bus LIN to ground GND, so that the LIN bus LIN has a dominant level (low state). If the master circuit  200  is disconnected from the supply voltage VDD, a bus voltage on the LIN bus LIN drops. Communication through the LIN bus LIN is no longer possible after disconnection of the master circuit  200  from the supply voltage VDD. If the slave circuit  100  is not simultaneously disconnected from the supply voltage, it advantageously detects from the waveform of the bus voltage that a valid bus signal is not present. 
     The slave circuit  100  is connectable to the LIN bus LIN by the terminal  102 . The slave circuit  100  has a receiver circuit  160 , which is connected to the LIN bus LIN through a filter  110 . The filter  110  is an analog low-pass filter for filtering out high-frequency interference signals. The slave circuit  100  has a detector circuit  180  connected to the LIN bus LIN through the filter  110 , which detector circuit has a comparator with a first threshold value (S 1 ). The receiver circuit  160  has a window comparator with two second threshold values to constitute the comparator window. The first of the two second threshold values is defined as 60% of the supply voltage (VDD), so that an exceedance is interpreted as logic 1. The second (S 2 ) of the two second threshold values is defined as 40% of the supply voltage (VDD), so that a drop below this threshold is interpreted as logic 0. The output of the receiver circuit  160  can be connected to a processing unit  300 , for example a microcontroller, for the purpose of output. 
     The output of the detector circuit  180  is connected to a control input of a first timer device  120 . In addition, the detector circuit  180  is connected to the interface circuit  150 . An additional, second timer device  130  is connected to the output of the receiver circuit  160 . 
     The second timer device  130  determines, together with the receiver circuit  160 , a time duration during which the bus voltage of the LIN bus LIN has a dominant level. If a counter of the second timer device  130  runs out, which device reaches a minimum time duration of a dominant level defined for a wake-up command, a signal associated with expiration of the counter arrives at the interface circuit  150  through a connection. By means of the connection between the interface circuit  150  and the second timer device  130 , it is possible to reset, stop, or start the counter, for example. 
     The detector circuit  180  is designed to determine that the bus voltage has dropped below the first threshold value (S 1 ). If the detector circuit  180  determines by means of a comparator that such a drop has taken place, then a detection signal arrives at the interface circuit  150  to start a safe mode. At the same time, a counter of the first timer device is started by means of the detection signal. As the bus voltage continues to fall, the counter of the second timer device  130  is also started upon reaching 40% of the supply voltage VDD. 
     If the bus voltage remains below the first threshold value (S 1 ), the counter of the first timer device  120  expires. In contrast, if the bus voltage rises above the first threshold value (S 1 ) before expiration of the counter of the first timer device  120 , then safe mode is started. 
     When the counter of the first timer device  120  expires, the interface circuit  150  stores the information as to whether or not the voltage has fallen below the second threshold value (S 2 ) at the point in time when the counter of the first timer device  120  expires. To this end, an output signal of the receiver circuit  160  arrives at the interface circuit  150 . 
     With the aid of the interface circuit  150 , the first timer device  120  identifies when the permissible length of a wake-up command (wake-up signal) has been exceeded on the LIN bus LIN, and reports this exceedance back to the interface circuit  150  as a counter expiration. The interface circuit and power controller  150  stores the current output value of the receiver circuit  160  in a nonvolatile memory and ensures that the internal supply voltages of the slave circuit  100  are switched off to reduce power consumption. Accordingly, the interface circuit  150  controls the power consumption of the slave circuit  100 . 
     A third timer device  140  is connected to the interface circuit  150 . The third timer device  140  is provided for an external signal at the signal input  103 , filtered by an additional filter  170 —for example, an analog bandpass filter. The external signal at the signal input  103  is likewise used for wake-up by means of the interface circuit  150 . 
     A control input  104  of the interface circuit  150  is connected to a processing unit  300 . Using the control input  104 , the processing unit  300  signals the interface circuit  150  by means of an enable signal that a transition from safe mode to normal mode (active mode) is taking place. The slave circuit  100  with the processing unit  300  is now fully awakened. 
       FIGS. 2   a  to  3   c  show several diagrams explaining the invention with exemplary waveforms of the bus voltage U LIN . The example embodiments shown in  FIGS. 2   a  to  3   c  are based on a LIN bus architecture in which a master circuit  200  can be powered off while at the same time at least one slave circuit  100  is still supplied with the supply voltage VDD. As in the example embodiment in  FIG. 1 , however, the powering down of the master circuit  200  also means the loss of the so-called pull-up that holds the line LIN in the recessive state as long as no activity takes place on the LIN bus. 
     The result is that the voltage on the LIN bus slowly drops, wherein the example embodiment in  FIG. 1  has the advantage that this drop is not interpreted as a wake-up command by the slave unit  100 . This achieves the effect that the average current consumption of the slave unit  100  is reduced, since no circuits that monitor the activity on the LIN bus need be put into operation. In this way the further effect is achieved that a motor vehicle battery is discharged less. 
     A wake-up command according to the LIN specification has a defined maximum length of 5 milliseconds. According to the example embodiments in  FIGS. 2   a  to  3   c , this period plus a certain time safety window (for example, a total of 10 milliseconds) is waited, then the slave circuit  100  is placed completely back in the sleep mode SM until the bus state is “recessive” again. 
     To this end, a counter is used, which is started as soon as the slave circuit  100  is in a wake-up detection phase WDP. At the point in time t 1 , the slave circuit  100  detects a drop by the bus voltage U LIN  below a threshold value S 1 , and the wake-up detection phase WDP is started. The wake-up detection phase WDP directly follows a sleep mode SM. The counter defines a time duration starting at t 1  lasting until time t 2 . After expiration of the time duration defined by the counter, a check is made as to whether the LIN bus LIN is already in the dominant state—which is to say below a second threshold value S 2 —or not. The result is stored in a nonvolatile memory. 
     In the embodiment from  FIGS. 2   a ,  2   b , and  2   c , the bus voltage U LIN  quickly drops below another, second threshold value S 2  in the form of a steep falling edge, so that the dominant state has already been achieved by the point in time t 2 . After the time t 2 , the sleep mode SM is continued. 
     Similar also applies for the exemplary embodiment in  FIGS. 3   a ,  3   b , and  3   c . In this exemplary embodiment the bus voltage U LIN  falls slowly, so that the bus voltage U LIN  has not yet fallen below the second threshold value S 2  after the start of the wake-up detection phase WDP at the time t 1 ′, or even after counting to the time t 2 ′. The failure to fall below the second threshold value S 2  is stored accordingly as information about the point in time t 2 ′. During the wake-up detection phase WDP, the current consumption I of the slave circuit  100  rises significantly, as shown schematically in  FIGS. 2   b  and  3   b , while the current consumption I is reduced from the time t 2  or t 2 ′ until the time t 3  or t 3 ′ in the sleep mode SM. The sleep mode SM of the slave circuit  100  is continued if the time duration of the drop below the second threshold value S 2  during the wake-up detection phase is not associated with the wake-up detection phase WDP. This is the case in both exemplary embodiments in  FIGS. 2   a ,  2   b ,  2   c  and  3   a ,  3   b ,  3   c.    
     The result of whether the bus voltage U LIN  has fallen below the additional, second threshold value S 2  at the point in time t 2  or t 2 ′ after the expiration of the time duration (t 1  to t 2 , or t 1 ′ to t 2 ′) is stored in a memory which does not lose its memory contents even in the sleep mode SM. Only after this has been accomplished is the sleep mode SM reestablished in which current consumption is minimal. 
     The sleep mode SM can only be terminated again after a rising edge of the bus voltage U LIN  at the point in time t 3  or t 3 ′, which is to say when the bus voltage U LIN  again rises to the level of the supply voltage VDD. In the concrete application case in a motor vehicle, this takes place when the ignition is turned on again, and hence the pull-up is again present in the LIN network. 
     As a function of the stored result regarding a drop below the second threshold value S 2  or a failure to drop below it at the point in time t 2  or t 2 ′, the slave circuit  100  in the exemplary embodiment in  FIG. 2   c  is now activated and placed in a safe mode, the so-called fail-safe mode FSM, if the dominant threshold S 2  has been achieved at the point in time t 2 . 
     In the exemplary embodiment in  FIGS. 3   a ,  3   b , and  3   c , the awakening is first made possible by means of a repeated voltage drop on the LIN bus LIN, since the dominant threshold S 2  had not (yet) been reached by the bus voltage U LIN  after expiration of the counter of the first timer device  120  at the point in time t 2 ′. 
     For the awakening, the bus voltage drops below the second threshold value S 2  for a specified length of time (not shown) for the wake-up command. When this occurs, the slave circuit  100  is awakened from a sleep mode SM to a normal mode if the time duration of the drop below the second threshold value S 2  is associated with a wake-up command during the wake-up detection phase (not shown). 
     The invention is not restricted to the variant embodiments shown in  FIGS. 1 through 3   c . For example, it is possible to use alternative time thresholds or additional time thresholds. 
     The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.