Abstract:
An offset current independent sense circuit is switchable between a store state and a sense state. In the store state, the sense circuit stores an offset current to a capacitor, and the influence of the offset current is eliminated by a transistor to regenerate the offset current based on a signal provided by the capacitor in the sense state.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention is related generally to a sense circuit and method and more particularly to an offset independent sense circuit and method.  
       BACKGROUND OF THE INVENTION  
       [0002]      FIG. 1  shows a conventional sense circuit  100  configured with a balance circuit for high-side sensing, which comprises two resistors R 1  and R 2  connected to a sensed object  106  at the opposite sides, a transistor  107  having a source  108  connected to the resistor R 1  and a drain  110  and gate  112  connected to a current source  102 , a transistor  113  having a source  114  connected to the resistor R 2 , a gate  118  connected to the gate  112  of the transistor  107 , and a drain  116  connected to a current source  104 , a transistor  119  having a source  120  connected to the source  108  of the transistor  107 , a gate  124  connected to the drain  116  of the transistor  113 , and a drain  122  connected to a resistor R O .  
         [0003]     Based on the voltages at the opposite sides of the sensed object  106 , two currents I 1  and  12  flow through the resistors R 1  and R 2 , respectively, and each of the currents provided by the current sources  102  and  104  is equal to the current  12 . If the current I 1  is larger than the current  12 , the difference I O  between the currents I 1  and I 2  will flow through the transistor  119  and resistor R O  to produce an output voltage V O , by which the voltage drop ΔV across the sensed object  106  is determined.  
         [0004]      FIG. 2  shows a conventional sense circuit  200  configured with a balance circuit for a comparator, in which the balance circuit is the same as that of the sense circuit  100 , and an output voltage V O  is generated on the drain  116  of the transistor  113  in response to the difference between the input voltages VII and VNI connected to the resistors R 1  and R 2 .  
         [0005]     However, the real devices for the transistors  107  and  113  will not match to each other, and there is always an offset current present during the sensing carried out by the sense circuit  100  or  200 . In other words, the sense circuits  100  and  200  never implement precise sensing. Though tuner circuit may be introduced to eliminate the influence caused by the offset current, proper tuning could not be achieved for sense circuits of mass production, since the sense circuits of mass production have not uniform offset currents.  
         [0006]     Therefore, it is desired an offset independent sense circuit and method.  
       SUMMARY OF THE INVENTION  
       [0007]     Accordingly, one object of the present invention is to provide an offset independent sense circuit and method.  
         [0008]     In an offset independent sense circuit, according to the present invention, a balance circuit has a first and second inputs and a first and second outputs, a capacitor is connected to the first output, and a transistor is connected to the second output.  
         [0009]     When a first voltage is switched to the first and second inputs, the sense circuit is switched to a store state, in which an offset current is produced at the first output and stored to the capacitor. When the first voltage and a second voltages are switched to the first and second inputs, respectively, the sense circuit is switched to a sense state, in which the transistor regenerates the offset current at the second output based on the signal provided by the capacitor, thereby eliminating the influence of the offset current.  
         [0010]     Since the sense circuit of the present invention is capable of automatically eliminating the influence of the offset current, there will be not offset issue even for sense circuits of mass production. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0011]     These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:  
         [0012]      FIG. 1  shows a conventional sense circuit configured with a balance circuit for high-side sensing;  
         [0013]      FIG. 2  shows a conventional sense circuit configured with a balance circuit for a comparator;  
         [0014]      FIG. 3A  and  FIG. 3B  show a sense circuit for high-side sensing in store state and sense state, respectively;  
         [0015]      FIG. 4  shows simulated waveforms generated by various sense circuits;  
         [0016]      FIG. 5A  and  FIG. 5B  show another sense circuit for high-side sensing in store state and sense state, respectively;  
         [0017]      FIG. 6A  and  FIG. 6B  show a sense circuit for a high-side comparator in store state and sense state, respectively;  
         [0018]      FIG. 7A  and  FIG. 7B  show a sense circuit for low-side sensing in store state and sense state, respectively; and  
         [0019]      FIG. 8A  and  FIG. 8B  show a sense circuit low-side comparator in store state and sense state, respectively. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0020]     For an embodiment for high-side sensing,  FIG. 3A  and  FIG. 3B  show a sense circuit  300  in store state and sense state, respectively. In the sense circuit  300 , a balance circuit  302  has two inputs  304  and  306  connected to the opposite sides of a sensed object  305 , a transistor  307  has a source  308  connected to the balance circuit  302 , a drain  310  is grounded, and a gate  312  connected to a capacitor C 1 , the capacitor C 1  has the other terminal grounded, and a transistor  313  has a source  314  and gate  318  connected to the balance circuit  302  and capacitor C 1 , and a drain  316  grounded.  
         [0021]     In the balance circuit  302 , a resistor R 1  is connected between the input  304  and a transistor  323 , a resistor R 2  is connected between the input  306  and a transistor  327 , the transistor  323  has its source  324  connected to the resistor R 1 , and its drain  325  and gate  326  connected to a current source  320  and the source  308  of the transistor  307 , the transistor  327  has its source  328  connected to the resistor R 2 , its gate  332  connected to the gate  326  of the transistor  323 , and its drain  330  connected to a current source  322 , a transistor  333  has its source  334  connected to the source  324  of the transistor  323 , its gate  338  connected to the drain  330  of the transistor  327 , and its drain  336  connected to a resistor RO and the source  314  of the transistor  313 .  
         [0022]     In the sense circuit  300 , switches S 1 -S 6  are used to switch the sense circuit  300  between the store state and sense state under the control of a clock. The switch S 1  is between the inputs  304  and  306 , the switch S 2  is between the transistors  333  and  313 , the switch S 3  is between the gate  318  of the transistor  313  and the capacitor C 1 , the switch S 4  is between the input  306  and resistor R 2 , the switch S 5  is between the transistor  333  and resistor R O , and the switch S 6  is between the transistors  323  and  307 . In this embodiment, to determine the direction of the offset current I offset  to be operated, the transistor  327  is smaller than the transistor  323 , or the resistor R 2  is larger than the resistor R 1 .  
         [0023]     Referring to  FIG. 3A , when the switches S 1 -S 3  turn on and the switches S 4 -S 6  turn off, the sense circuit  300  is switched to the store state, and the voltage on the input  304  is applied to the resistors R 1  and R 2 . Due to the transistor  327  smaller than the transistor  323 , or the resistor R 2  larger than the resistor R 1 , the current I 1  flowing through the resistor R 1  is larger than the current I 2  flowing through the resistor R 2 . Moreover, each of the currents provided by the current sources  320  and  322  is equal to the current I 2 , and therefore the output current I O  flowing through the transistor  333  is equal to the difference between the currents I 1  and I 2 . This output current I O  is the offset current I offset . Since the switch S 2  turns on and the switch S 5  turns off, the offset current I offset  is stored to the capacitor C 1  by charging the capacitor C 1 . Referring to  FIG. 3B , when the switches S 1 -S 3  turn off and the switches S 4 -S 6  turn on, the sense circuit  300  is switched to the sense state, and the capacitor C 1  applies a signal V C  based on the offset current I offset  it has stored in the store state to the gate  312  of the transistor  307 , by which the transistor  307  conducts a current as large as the offset current I offset , thereby eliminating the influence of the offset current I offset .  
         [0024]      FIG. 4  shows simulated waveforms generated by various sense circuits, in which the upper panel is an enlargement of the circle in the lower panel. Waveform  40  represents the output voltage of the conventional sense circuit  100 , waveform  42  represents the output voltage of the sense circuit  300 , and waveform  44  represents the output voltage of an ideal sense circuit without offset current.  FIG. 4  shows that the sense circuit  300  is almost not influenced by offset current.  
         [0025]     For another embodiment for high-side sensing,  FIG. 5A  and  FIG. 5B  show a sense circuit  400  in store state and sense state, respectively. The sense circuit  400  is almost the same as the sense circuit  300 , only that the switch S 2  is removed and a transistor  401  replaces the role of the resistor R O  in the sense circuit  300 . The transistor  401  has its gate  406  connected to the gate  318  of the transistor  313  to form a current mirror, the source  402  of the transistor  401  is connected to the output  408  of the sense circuit  400  through the switch S 5 , and the drain of the transistor  401  is grounded. Referring to  FIG. 5A , when the switches S 1  and S 3  turn on and the switches S 4 -S 6  turn off, the sense circuit  400  is switched to the store state, and the output current I O  is the offset current I offset  and is stored to the capacitor C 1  by charging the capacitor C 1 . Referring to  FIG. 5B , when the switches S 1  and S 3  turn off and the switches S 4 -S 6  turn on, the sense circuit  400  is switched to the sense state, and the capacitor C 1  applies a signal V C  based on the offset current I offset  it has stored in the store state to the gate  312  of the transistor  307 , by which the transistor  307  conducts a current as large as the offset current I offset , thereby eliminating the influence of the offset current I offset . On the other hand, the output current I O  is mirrored by the current mirror composed of the transistors  313  and  401  to the output  408  of the sense circuit  400 .  
         [0026]     For an embodiment for a high-side comparator,  FIG. 6A  and  FIG. 6B  show a sense circuit  500  in store state and sense state, respectively. The sense circuit  500  is connected with two voltages VII and VNI and is almost the same as the sense circuit  300 , only that the resistor R O  of the sense circuit  300  is removed, and the switch S 5  and output V O  of the sense circuit  500  are connected to the drain  330  of the transistor  327 . Referring to  FIG. 6A , when the switches S 1 -S 3  turn on and the switches S 4 -S 6  turn off, the sense circuit  500  is switched to the store state, and the output current I O  is the offset current I offset  and is stored to the capacitor C 1 . Referring to  FIG. 6B , when the switches S 1 -S 3  turn off and the switches S 4 -S 6  turn on, the sense circuit  500  is switched to the sense state, and the capacitor C 1  applies a signal V C  based on the offset current I offset  it has stored in the store state to the gate  312  of the transistor  307 , by which the transistor  307  conducts a current as large as the offset current I offset , thereby eliminating the influence of the offset current I offset . On the other hand, the output current I O  is mirrored by the current mirror composed of the transistors  313  and  401  to the output  408  of the sense circuit  400 .  
         [0027]     For an embodiment for low-side sensing,  FIG. 7A  and  FIG. 7B  show a sense circuit  600  in store state and sense state, respectively. In the sense circuit  600 , a balance circuit  302  has two inputs  304  and  306  connected to the opposite sides of a sensed object  305 , a transistor  307  has a source  308  connected to the balance circuit  302 , a drain  310  is grounded, and a gate  312  connected to a capacitor C 1 , the capacitor C 1  has the other terminal grounded, and a transistor  313  has a source  314  and gate  318  connected to the balance circuit  302  and capacitor C 1 , and a drain  316  grounded. In the balance circuit  302 , a resistor R 1  is connected between the input  304  and a transistor  323 ′, a resistor R 2  is connected between the input  306  and a transistor  327 ′, the transistor  323 ′ has its source  324 ′ and gate  326 ′ connected to a current source  320  and the source  308  of the transistor  307 , and its drain  325 ′ connected to the resistor R 1 , the transistor  327 ′ has its source  328 ′ connected to a current source  322 , its gate  332 ′ connected to the gate  326 ′ of the transistor  323 ′, and its drain  330  connected to the resistor R 2 , a transistor  333 ′ has its source  334 ′ connected to a transistor  601 , its gate  338 ′ connected to the drain  328 ′ of the transistor  327 ′, and its drain  336 ′ connected to the drain  325 ′ of the transistor  323 ′, the transistor  601  has its source  602  connected to a supply voltage V CC , and its drain  604  and gate  606  connected to the source  334 ′ of the transistor  333 ′, a transistor  607  is connected to the transistor  606  to form a first current mirror, a transistor  613  is connected to the transistor  607  to form a second current mirror, the transistor  607  has its source  608  connected to the supply voltage V CC , its drain  610  connected to the source  314  of the transistor  313 , and the transistor  613  has its source  614  connected to the supply voltage V CC  and its drain  616  connected to the output of the sense circuit  600 .  
         [0028]     A switch S 1  is between the inputs  304  and  306 , a switch S 3  is between the gate  318  of the transistor  313  and the capacitor C 1 , a switch S 4  is between the input  306  and resistor R 2 , and a switch S 6  is between the transistors  323 ′ and  307 . Those switches S 1 , S 3 , S 4  and S 6  are controlled by a clock to switch the sense circuit  600  between the store state and sense state. In this embodiment, to determine the direction of the offset current I offset  to be operated, the transistor  327 ′ is smaller than the transistor  323 ′, or the resistor R 2  is larger than the resistor R 1 . Referring to  FIG. 7A , when the switches S 1  and S 3  turn on and the switches S 4  and S 6  turn off, the sense circuit  600  is switched to the store state, and the current I O  flowing through the transistor  333 ′ is the offset current I offset  and is mirrored by the first current mirror composed of the transistors  601  and  607  to the transistor  313  to store to the capacitor C 1 . Referring to  FIG. 7B , when the switches S 1  and S 3  turn off and the switches S 4  and S 6  turn on, the sense circuit  600  is switched to the sense state, and the capacitor C 1  applies a signal V C  based on the offset current I offset  it has stored in the store state to the gate  312  of the transistor  307 , by which the transistor  307  conducts a current as large as the offset current I offset , thereby eliminating the influence of the offset current I offset .  
         [0029]     For an embodiment for a low-side comparator,  FIG. 8A  and  FIG. 8B  show a sense circuit  700  in store state and sense state, respectively. The sense circuit  700  is connected with two voltages VII and VNI and is almost the same as the sense circuit  600 , only that the transistor  607  of the sense circuit  600  is removed, and a switch S 5  and output V O  of the sense circuit  700  are connected to the source  328 ′ of the transistor  327 ′. Referring to  FIG. 8A , when the switches S 1  and S 3  turn on and the switches S 4 -S 6  turn off, the sense circuit  700  is switched to the store state, and the output current I O  is the offset current I offset  and is mirrored by the current mirror composed of the transistors  601  and  607  to the transistor  313  to store to the capacitor C 1 . Referring to  FIG. 8B , when the switches S 1  and S 3  turn off and the switches S 4 -S 6  turn on, the sense circuit  700  is switched to the sense state, and the capacitor C 1  applies a signal V C  based on the offset current I offset  it has stored in the store state to the gate  312  of the transistor  307 , by which the transistor  307  conducts a current as large as the offset current I offset , thereby eliminating the influence of the offset current I offset .  
         [0030]     The MOS transistors in the embodiments of  FIGS. 3-8  may be replaced with bipolar transistors.  
         [0031]     While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.