Abstract:
A method of protecting a microelectronic chip contained in a microelectronic assembly, including the steps of depositing a protective coating across the exposed faces of the chip. The coating, having a low modulus of elasticity, is applied across the chip so as to reduce the overall height of the assembly while still protecting the exposed face and corners of the chip from damage.

Description:
BACKGROUND  
       [0001]     The present invention relates to the art of electronic packaging, and more specifically to a method of protecting a surface of a microelectronic element, such as a semiconductor chip.  
         [0002]     Modern electronic devices utilize semiconductor chips, commonly referred to as “integrated circuits” which incorporate numerous electronic elements. Chips are almost universally formed by processing a large semiconductor wafer to form numerous regions, each including the microscopic circuitry of a single chip, and then cutting or “dicing” the wafer to form numerous separate chips. Each chip includes a flat, typically rectangular body having front and back surfaces, with contacts on the front surface connected to the microscopic circuitry within the chip. These chips are then mounted on substrates, known alternatively as interconnect elements or package elements, which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements.  
         [0003]     Once a chip has been mounted to the substrate, the back side and edges of the chip remain exposed to damage that can occur from further handling. Specifically, chipping and cracking along the edges and corners of the unprotected chip can occur. Such damage can in turn prevent proper operation of the chip.  
         [0004]     Conventional means for protecting the chip from such damage typically include surrounding the chip with an overmold. Typically, the overmold is made of a hard material and is attached to the substrate in a way that prevents contact with the chip. In this way, the chip package can withstand the forces prevalent during handling without damaging the chip. The overmold is limiting however, in that it creates extra height to the chip package. This is especially limiting when the chip packages are in a “stacked” configuration.  
         [0005]     In order to decrease the area occupied by chip packages, a number of chips or other microelectronic elements, each mounted to a package element, are vertically stacked one on top of another and interconnected to form a stacked package. This stacked configuration adds to the height of the circuit. However, in many applications low height is essential, as for example, in assemblies intended for use in miniaturized cellular telephones and other devices to be worn or carried by the user. To decrease the height of the stacked packages, it is preferable to reduce the vertical pitch of the packaged chips. In such circumstances, the overmold can act as a lower limit for the spacing between these elements.  
       SUMMARY  
       [0006]     In particular embodiments, the height of the chip above the package element is reduced while still protecting the exposed face and corners of the chip from damage.  
         [0007]     In one embodiment of the present invention, a microelectronic chip has a front face and a back face opposite the front face. The thickness of the microelectronic chip is less than approximately 400 micrometers (μm). A package element is mounted to the front face of the chip, while a thin protective coating including a low modulus material, overlies the back face of the chip.  
         [0008]     In one embodiment of the present invention, the microelectronic chip has a plurality of edges extending between the front and back faces and a plurality of corners between these edges. The protective coating overlies at least one of the edges or corners.  
         [0009]     In another embodiment of the present invention, a plurality of microelectronic assemblies are vertically stacked to form a stacked microelectronic assembly. A thin protective coating overlying at least one chip in the stacked assemblies.  
         [0010]     One method of the present invention includes applying a protective coating to the back face of the microelectronic element, wherein the coating is a flowable material and is applied through a process of stencil printing.  
         [0011]     Another method of the present invention includes a process wherein the coating is in the form of a flexible tape material having a self-adhesive property and is applied to individual chips by a roll lamination process. Alternatively, this process may be applied simultaneously to a plurality of chips attached to each other in the form of a microelectronic wafer or portion thereof. Subsequently, the coated wafer is diced into the microelectronic chips.  
         [0012]     Yet another method of the present invention includes applying the coating material to the back face of the microelectronic element through a process of screen printing. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  is a cross sectional view of a microelectronic assembly having a protective coating in accordance with an embodiment of the invention.  
         [0014]      FIG. 2  is a plan view of the microelectronic assembly of  FIG. 1 , looking towards a front face of a chip.  
         [0015]      FIG. 3  is a perspective view of stacked microelectronic assemblies, in accordance with an embodiment of the invention.  
         [0016]      FIG. 4  is an exploded view of a protective coating being applied by a stencil printing device.  
         [0017]      FIG. 5  is a cross-sectional view of the device of  FIG. 4 .  
         [0018]      FIG. 6  is a cross-sectional view of a protective coating being applied by a screen printing method.  
         [0019]      FIG. 7  is a cross-sectional view of a protective coating being applied by a dispensing method.  
         [0020]      FIG. 8  is a top plan view of a wafer.  
         [0021]      FIG. 9  is a cross-sectional view of a microelectronic wafer having a protective coating in accordance with an embodiment of the invention.  
         [0022]      FIG. 10  is a cross-sectional view of a prior art microelectronic assembly having an overmold. 
     
    
     DETAILED DESCRIPTION  
       [0023]      FIG. 1  and  FIG. 2  show a diagrammatic sectional view of a microelectronic assembly with a protective coating according to one embodiment of the invention. The microelectronic assembly  10  includes a chip  12  having a front face  14  and a back face  16 , with the front face  14  being mounted to a substrate  18 . The substrate includes slots  13  or other openings aligned with bond pads  20  exposed at the front face  14  of the chip. The bond pads  20  are electrically connected by conductive leads  22  to contacts  24  contained on the substrate  14 . The substrate  18  incorporates a dielectric body which desirably is as thin as is practicable. For example, the substrate may include one or more layers of dielectric such as, without limitation, polymide, glass, ceramic or undoped semiconductor.  
         [0024]     A thin protective coating  26  overlies the back face  16  of the chip  12 . The coating  26  is made of a low modulus material having an elastic modulus of less than approximately 10 Gigapascal (GPa). In one embodiment, the low modulus coating is made of polymers or elastomers, such as polymides, bismaleimide matrix adhesives, epoxy matrix adhesives, or silicone elastomers. The thickness of the coating  26 , which is displayed as the vertical dimension in  FIG. 1 , is approximately 25 μm to 150 μm, in order to provide sufficient protection of the chip  12  under most circumstances. In addition, the chip  12  has a thickness between its front face and back face that is less than approximately 400 μm.  
         [0025]     For the embodiment shown in  FIG. 1 , a microelectronic assembly  10  includes a protective coating  26  overlying the plurality of edges  28  extending between the front face  12  and the back face  16  of the chip  12 . The protective coating  26  may also overlie the corners  30  running between the plurality of edges  28  and back face  16 . This coating  26  over the plurality of chip edges  28  and corners  30  further protects against potential crack propagation that could occur during shipping and handling.  
         [0026]     The thickness of the protective coating  26  at the edges  28  and corners  30  need not be uniform and need not be the same as the thickness across the back face  16  of the chip  12 . For example, a protective coating  26  having a thickness of approximately 44 μm across the back face  16  of the chip  12  may have a thickness of approximately 20 μm at a corner  30  and approximately 70 μm at an edge  28 .  
         [0027]     For the embodiment shown in  FIG. 3 , a protective coating  26  is provided on at least one of a plurality of microelectronic assemblies  10  which are mounted together in a stacked configuration. In this embodiment, the substrate  18  of at least one microelectronic assembly  10   a  is mounted to overlie another microelectronic assembly  10   b . The substrates  18  of the two microelectronic assemblies are mounted and conductively connected to each other with a connecting material such as solder balls  37 . In addition, at least one of the microelectronic assemblies  10  has a protective coating  26  overlying the back face  16  of a chip  12 .  
         [0028]     The vertically stacked microelectronic assemblies allow for a greater number of microelectronic elements to be placed in a given area. To further decrease the space these microelectronic assemblies occupy, the vertical height or thickness of each assembly in the stack can be reduced by using a thinner chip  12 . However, as the thickness of the chip  12  is reduced, the risk of damage to the chip, such as by cracking and chipping during handling, increases. This embodiment therefore provides for a coating  26 , which will protect the chip  12  without greatly increasing the thickness of the complete microelectronic assembly.  
         [0029]     The thickness of each microelectronic assembly is determined by the overall height or vertical dimension of the substrate  18 , the chip  12 , and the protective coating  26  of the complete assembly. The use of a protective coating as embodied in the present invention allows a thinner chip  12  to be used without increasing the risk of damage to cracking or chipping.  
         [0030]     In one embodiment, the protective coating  26  is applied through a process of stencil printing, as shown in  FIG. 4  and  FIG. 5 . As shown in  FIG. 4 , a stencil mask  38  having a plurality of apertures  40  each large enough to expose a back face of one chip is aligned with a plurality of chips  12 . In this embodiment, a front face  14  of each chip  12  is mounted to a substrate  18 , as shown in  FIG. 5 . A stencil mask  38 , preferably including a laser-formed, stainless steel material, is used. The distance between the stencil and the back face of the chip is preferably between about 5 and 15 mils. A squeegee blade  42  then passes over the stencil mask  38  at a uniform velocity while distributing the protective coating material in the form of a paste  44 . The stencil mask  38  is then removed leaving a completed microelectronic element including a chip  12 , substrate  18  and protective coating  26  overlying the back face  16 , edges  28  and corners  30  of the chip.  
         [0031]     The thickness of the protective coating  26  in the completed microelectronic assembly is affected by the downward force exerted by the squeegee blade  42  as the squeegee blade  42  passes over the stencil mask  38 . For instance, the coating  26  becomes thinner as the downward force exerted by the squeegee blade  42  is increased.  
         [0032]     In another embodiment, the protective coating  26  is applied through a process of screen printing, as shown in  FIG. 6 . In this process, a printing mesh  46 , typically including strands of stainless steel or a similar material, is placed over the back face  16  of a chip  12 . This process is typically performed simultaneously to a plurality of chips arranged in an array. For ease of reference, only a single chip is illustrated. A squeegee blade  42  then passes over the printing mesh  46  at a uniform velocity while distributing the protective coating material in the form of a paste  44 . The strands of the mesh  46  provide a plurality of small apertures  47 , through which the coating is forced onto the back face  16  by the squeegee to form a protective coating overlying the back face.  
         [0033]     In yet another embodiment ( FIG. 7 ), the protective coating is applied to the microelectronic assembly by a dispensing process. In this process, the coating material  48  is stored in a cartridge  50  and is dispensed onto the back face  16  of the chip  12  through a nozzle  52 . The coating material  48  may be forced through the nozzle by means of a pump or other mechanical device. The flow rate of the coating material  48  through the nozzle must be minimized as to assure an even distribution. Therefore, the opening of the nozzle  52  should be small enough to assure a low flow rate and even distribution.  
         [0034]     In an alternative embodiment, a protective coating  26  is applied to a chip while it remains attached to other chips in form of a wafer  32 , as shown in  FIG. 8  and  FIG. 9 . The wafer  32  includes a plurality of individual chips  34 , attached to each other at dicing lines  60 , each such clip containing internal electronic circuitry (not shown) and bond pads  20  on a front face, as previously described above with reference to  14 . Only a few of the bond pads  20  are depicted for clarity of illustration in  FIG. 9 . A protective coating  26  is applied across the back face  16  of the wafer  32 . The wafer  32  is then severed into individual chips  34  by conventional processes such as sawing, etching or scribing and breaking the material of the wafer along the dicing lanes  60 .  
         [0035]     The protective coating  26  may be applied to the wafer in various methods. For example, the coating  26  may consist of a pre-formed tape material which can be applied by a roll lamination process, or the protective coating  26  may be applied through a spin-coating method.  
         [0036]     The structures and methods discussed above provide a compact microelectronic assembly, while protecting a microelectronic element such as a chip from damage due to stresses common in subsequent manufacturing processes and/or shipping and handling. The current industry practice of applying an overmold  54  is illustrated in  FIG. 10 . However, the cost of applying such an overmold is more expensive than the embodiments described herein. Moreover, the costs associated with the tooling needed to size and form an overmold  54  to the dimensions of a given microelectronic assembly may also be avoided through use of the structures and processes described herein. The application of the overmold can also introduce various stresses onto the chip  12  which can itself increase the risk of damage. A low modulus coating applied to chips or microelectronic assemblies as discussed herein protects against these stresses.  
         [0037]     As these and other variations and combinations of the features discussed above can be utilized without departing from the present invention as defined by the claims, the foregoing description of embodiments should be taken by way of illustration rather than by way of limitation of the invention as defined by the claims.