Abstract:
A driving circuit for an N-channel Metal Oxide Semiconductor (NMOS) transistor can include a charge pump unit and a driver coupled to the charge pump. The charge pump can receive a source voltage and output an output voltage higher than the source voltage, where the source voltage is applied to a source terminal of the NMOS transistor. The driver receives the output voltage of the charge pump unit and converts the output voltage to a driving voltage operable for conducting the NMOS transistor.

Description:
RELATED APPLICATION 
       [0001]    This application claims priority of co-pending provisional application, Ser. No. 61/008,427, filed on Dec. 20, 2007, which is hereby incorporated by reference in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    This invention relates to power management systems, and more particularly, to power management systems with charge pumps. 
       BACKGROUND 
       [0003]    In present power management devices, such as power management controllers and/or chargers, switches can be used to direct power, e.g., direct power from a power source to a system load or to a rechargeable battery pack. In power management controllers or chargers, switches are generally implemented by bipolar transistors or Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs). In electrical circuitries, ideal switches which are defined as having zero ON-state resistances and infinite OFF-state resistances are desired. MOSFETs can have relatively lower ON-state resistances and relatively higher OFF-state resistances than other types of switches. 
         [0004]    Generally, a P-channel MOSFET (PMOS) switch may be driven in an ON state by biasing a gate terminal voltage of the PMOS switch to a low voltage level (e.g., 0 volt) with respect to the voltage on a source terminal of the switch. To turn on an N-channel MOSFET (NMOS) switch, a driving voltage at a gate terminal of the NMOS switch may need to be substantially greater than a source voltage at the source terminal (e.g., 5 volts greater than the source voltage). In conventional circuitries, the source terminal of an NMOS switch may be coupled to a positive terminal (or an output) of a power source (e.g., a battery pack). Therefore, the driving voltage for the gate of the NMOS switch may need to be substantially greater than the output voltage of the power source. This intrinsic characteristic of NMOS switches can limit their applications since such a high driving voltage may not be available. Consequently, PMOS switches are used extensively in current power management devices. 
         [0005]    Although easier to drive, PMOS switches may have substantially larger ON-state resistances than NMOS switches having the same sizes as PMOS switches. For example, the ON-state resistance of a PMOS switch can be two times larger than the ON-state resistance of an NMOS switch having the same size. Accordingly, power dissipation of switches can be doubled if PMOS switches are employed instead of NMOS switches. 
         [0006]    To reduce power dissipation of PMOS switches and obtain targeted power transfer efficiencies, PMOS switches with low ON-state resistance may be employed. However, such PMOS switches are costly as they may need a special fabrication process. Furthermore, such PMOS switches may also need extra chip area to accommodate drivers to drive them. Therefore, costs of such power management devices are increased. 
       SUMMARY 
       [0007]    According to one embodiment of the invention, a driving circuit for an N-channel Metal Oxide Semiconductor (NMOS) transistor includes a charge pump unit and a driver coupled to the charge pump. In such an embodiment, the charge pump receives a source voltage and outputs an output voltage higher than the source voltage, and the driver receives the output voltage of the charge pump unit and converts the output voltage to a driving voltage operable for conducting the NMOS transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The accompanying drawings, which are incorporated in and from a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention. 
           [0009]      FIG. 1  illustrates a block diagram of an example of a power management system in accordance with one embodiment of the present invention. 
           [0010]      FIG. 2  illustrates examples of waveforms of switch control signals and driving signals in accordance with one embodiment of the present invention. 
           [0011]      FIG. 3  illustrates a block diagram of an example of a power management system in accordance with another embodiment of the present invention. 
           [0012]      FIG. 4  illustrates a flowchart of a method of controlling power supply in accordance with another embodiment of the present invention 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Reference will now be made in detail to the embodiments of the present invention. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. Additional advantages and aspects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description. As will be described, the present disclosure is capable of modification in various obvious respects, all without departing from the spirit of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative. 
         [0014]      FIG. 1  illustrates a block diagram of an example of a power management system  100  using NMOS switches and a corresponding driving circuit, in accordance with one embodiment of the present invention. The power management system  100  is operable for controlling power supply from a power source, e.g., an ACDC adapter  102  and/or a battery pack  104  to a system  110  via two NMOS switches  106  and  108 , in one embodiment. As shown in  FIG. 1 , the power source for the system  110  can be an output controllable ACDC adapter  102  and the battery pack  104  which can be a rechargeable battery pack. However, the power source for the system  110  can be any of a variety of power sources, such as an AC/DC adapter with a fixed output, a DC “cigarette” type adapter, a battery pack, a rechargeable battery pack, etc. The battery pack  104  can include any type of rechargeable battery pack, such as lithium-ion, nickel-cadmium, or nickel-metal hydride batteries, or the like. The system  110  can be any variety of electronic devices which include, but are not limited to, a server computer, a desktop computer, a laptop computer, a cell phone, a personal digital assistant, etc. 
         [0015]    In one embodiment, the power management system  100  is also operable for controlling power from the ACDC adapter  102  to charge the battery pack  104  via NMOS switches  106  and  108 . The power management system  100  further includes a control unit  114  which is operable for monitoring the power supply status of the system  110  and the status of the battery pack  104 , in one embodiment. Depending on the status of the system  110  and the battery pack  104 , the control unit  114  selects a working mode for the power management system  100 . Those modes include, but are not limited to: default mode, operation mode, charging operation mode, discharging mode, and heavy load mode. In default mode, both NMOS switches  106  and  108  are in off states, the system  110  and the power management system  100  are powered by either the ACDC adapter  102  or by the battery pack  104  (whichever has the higher output voltage), through one of the body diodes  106 - 1  or  108 - 1  that are intrinsically built into the respective switches,  106  and  108 . In operation mode, the NMOS switch  106  can be switched on and the NMOS switch  108  can be switched off, thus the system  110  can be powered by the ACDC adapter  102  via the switch  106 . In charging mode, both NMOS switches  106  and  108  are in on states, thus the ACDC adapter  102  can power the system  110  as well as charge the battery pack  104 . In discharging mode, NMOS switch  106  is in off state and the NMOS switch  108  is in on state, thus the system  110  can draw power from the battery pack  104 . In heavy load mode, both switches  106  and  108  are in on state, thus the ACDC adapter  102  and battery pack  104  can supply power simultaneously to the system  110  which has a heavy load (e.g., a power requirement of the system  110  is greater than the output power rating of the ACDC adapter  102 ). 
         [0016]    In each working mode, the control unit  114  can generate control signals (e.g., switch control signals  114 - 1  and  114 - 2 ) to control the conductance status of NMOS switches  106  and  108 , and to control an output (e.g., output current, output voltage, and/or output power) of the ACDC adapter  102 . As previously stated herein, NMOS switches may need a driving signal having a voltage level greater than a voltage level at its source terminal. Thus, in one embodiment, a driving circuit  112  is provided to generate adequate driving signals to drive NMOS switches  106  and  108 , such that NMOS switches  106  and  108  can be fully switched on and off. 
         [0017]    In other embodiments, the power management system  100  can also control power supply from multiple power sources and/or multiple battery packs to the system  110  by using multiple NMOS switches and corresponding driving circuits. Furthermore, by using multiple NMOS switches, the power management system  100  can also charge multiple battery packs either simultaneously or individually. 
         [0018]    As illustrated in  FIG. 1 , NMOS switches  106  and  108  are respectively coupled to a common node  116  via two sensing resistors  118  and  120 . Power supply from ACDC adapter  102  and/or battery pack  104  is delivered to the system  110  via the common node  116 , in one embodiment. The conductance status of NMOS switches  106  and  108  are controlled by two switch control signals  114 - 1  and  114 - 2  which are generated by the control unit  114 , in one embodiment. In one embodiment, the driving circuit  112  is used to convert switch control signals  114 - 1  and  114 - 2  to appropriate driving signals  112 - 1  and  112 - 2 , respectively. 
         [0019]    The driving circuit  112  includes two drivers  124 - 1  and  124 - 2 , which are respectively coupled between the control unit  114  and NMOS switches  106  and  108 , in one embodiment. In addition to drivers  124 - 1  and  124 - 2 , a charge pump unit  122  is also included in the driving circuit  112 . The charge pump unit  122  has two input terminals  122 - 1  and  122 - 2  and two output terminals  122 - 3  and  122 - 4 , in one embodiment. Input terminals  122 - 1  and  122 - 2  are respectively coupled to the output terminals of the ACDC adapter  102  and the battery pack  104 . Output terminals  122 - 3  and  122 - 4  are respectively coupled to drivers  124 - 1  and  124 - 2 . The charge pump unit  122  is operable for generating a voltage greater than a source voltage from the input terminals  122 - 1  and  122 - 2  of the charge pump unit  122 . In one embodiment, the source voltages of the charge pump unit  122  can be the output voltage of the ACDC adapter  102  (V ad ) and/or the output voltage of the battery pack  104  (V batt ). Thus, the charge pump unit  122  can provide an output signal having a voltage level greater than that of V ad  at the output terminal  122 - 3  to driver  124 - 1 . Another output signal having a voltage level greater than that of V batt  can also be output at the output terminal  122 - 4  and provided to driver  124 - 2 . Thus, drivers  124 - 1  and  124 - 2  respectively receive the output signals of the charge pump unit  122 , and generate a driving signal  112 - 1  (or  112 - 2 ) having an adequate output voltage level to fully switch on/off NMOS switches  106  and  108 . Once driver  124 - 1  or  124 - 2  receives a switch control signal from the control unit  114 , driver  124 - 1  or  124 - 2  can provide the driving signal  112 - 1  (or  112 - 2 ) having an adequate voltage level to drive NMOS switch  106  or  108 . 
         [0020]      FIG. 2  shows examples of waveforms of switch control signals ( 114 - 1  and  114 - 2 ) and driving signals ( 112 - 1  and  112 - 2 ) in the power management system  100 , in accordance with one embodiment of the present invention. As shown in the example of  FIG. 2 , the switch control signal  114 - 1  (or  114 - 2 ) has two voltage levels V 0  (e.g., 0 volt) and V 1  (e.g., 1.8 volts or 3.3 volts). In one embodiment, the control unit  114  generates a switch control signal  114 - 1  (or  114 - 2 ) having the voltage level V 0  to instruct the driving circuit  112  to switch NMOS switch  106  (or  108 ) off. The control unit  114  can also generate a switch control signal  114 - 1  (or  114 - 2 ) having the voltage level V 1  to instruct the driving circuit  112  to switch NMOS switch  106  (or  108 ) on. By using the driving circuit  112 , the switch control signal  114 - 1  (or  114 - 2 ) can be converted to a driving signal  112 - 1  (or  112 - 2 ). As shown in  FIG. 2 , the driving signal  112 - 1  has two voltage levels V ad  (e.g., 12V) and V on1  (e.g., 18V). The driving signal  112 - 2  has two voltage levels V batt  (e.g., 4.2 volts) and V on2  (e.g., 10 volts). The NMOS switch  106  (or  108 ) is fully switched off if the driving signal  112 - 1  (or  112 - 2 ) having the voltage level V ad  (or V batt ), in one embodiment. If the driving signal  112 - 1  (or  112 - 2 ) has the voltage level V on1  (or V on2 ), the NMOS switch  106  (or  108 ) is fully switched on, in one embodiment. Therefore, a combination of charge pump unit  122  and drivers  124 - 1  and  124 - 2  can provide adequate driving signals  112 - 1  and  112 - 2  to drive NMOS switches  106  and  108 . 
         [0021]    Returning to  FIG. 1 , the charge pump unit  122  can be implemented by two individual charge pumps, in one embodiment. For example, the input terminal  122 - 1  can be an input of a first charge pump which generates a signal having voltage level greater than V ad  at the output terminal. The input terminal  122 - 2  can be an input of a second charge pump which generates a signal having voltage level greater than V batt  at the output terminal  122 - 4 . The charge pump unit  122  can also be a single charge pump which is operable for providing an output signal to the driver  124 - 1  or  124 - 2 , in one embodiment. However, in another embodiment, multiple individual charge pumps can be used in the charge pump unit  122  to provide voltage signals to multiple drivers when multiple NMOS switches are employed in the power management system  100 . In yet another embodiment, a single charge pump can be used in the charge pump unit  122  to alternately provide voltage signals to multiple drivers in a time-sharing way. In the time-sharing way, the multiple drivers can share the voltage signals provided by the single charge pump of the charge pump unit  122  by allocating one driver&#39;s idle time to service other drivers. 
         [0022]    Before the power management system  100  is powered on, the power management system  100  is in the default mode, in which both NMOS switches  106  and  108  are in off states, in one embodiment. Once the power management system  100  is powered on, power can be delivered from the ACDC adapter  102  and/or from the battery pack  104  to the system  110 . Although NMOS switches  106  and  108  are in off states, power can be delivered via body diodes  106 - 1  and  108 - 1  which are intrinsically built into the NMOS switches  106  and  108 . As shown in  FIG. 1 , the body diode  106 - 1  has its anode intrinsically coupled to the source terminal of the NMOS switch  106  and its cathode coupled to the drain terminal of the NMOS switch  106 . The body diode  108 - 1  also has its anode and cathode respectively coupled to the source terminal and drain terminal of the NMOS switch  108 . 
         [0023]    If the ACDC adapter  102  is not available, the system  110  as well as the power management system  100  can be powered on by the battery pack  104 , in one embodiment. Under such circumstances, body diode  108 - 1  is forward biased and current generated by the battery pack  104  can flow through the body diode  108 - 1  to power the system  110 , in one embodiment. 
         [0024]    In one embodiment, the ACDC adapter  102  and the battery pack  104  may present simultaneously. Therefore, system  110  and the power management system  100  can be either powered by the ACDC adapter  102  or by the battery pack  104 , in one embodiment. If V ad  is greater than V batt , the body diode  106 - 1  is forward biased and the body diode  108 - 1  is reverse biased. Consequently, current generated by the ACDC adapter  102  can flow through the body diode  106 - 1 . Thus, system  110  and the power management system  100  can draw power from the ACDC adapter  102 . Otherwise, in the default mode, if V ad  is less than V batt , the body diode  106 - 1  is reverse biased and the body diode  108 - 1  is forward biased, and the system  110  and the power management system  100  are powered by the battery pack  104 . If V ad  is equal to V batt , the system  110  and the power management system  100  can randomly draw power from the ACDC adapter  102  and/or the battery pack  104 . 
         [0025]    Once the system  110  and the power management system  100  are powered on, the control unit  114  starts to manage power supply of the system  110  and the charging process of the battery pack  104 . If the power management system  100  and the system  110  are powered on, under the control of the control unit  114 , NMOS switches  106  and  108  can be fully switched on. Since an ON-state resistance of an NMOS switch can be relatively small, a voltage drop on a conducting NMOS switch may not exceed the conducting threshold of its body diode. Consequently, the body diode may not be conducting a significant current. Thus, after system  110  is powered on, current generated by ACDC adapter  102  and/or battery pack  104  may not flow through body diode  106 - 1  and/or  108 - 1 . 
         [0026]    The control unit  114  can firstly monitor the status of the ACDC adapter  102  and the battery pack  104 , in one embodiment. As illustrated in  FIG. 1 , the control unit  114  has three sensing terminals  114 - 3 ,  114 - 4  and  114 - 5 . In one embodiment, sensing terminal  114 - 3  is coupled to the drain terminal of NMOS switch  106 . Sensing terminal  114 - 4  is coupled to the common node  116 . Sensing terminal  114 - 5  is coupled to the drain terminal of NMOS switch  108 . Via sensing terminals  114 - 3 ,  114 - 4  and  114 - 5 , information such as V ad , V SYS  (input voltage of system  110 ), and V batt  can be monitored. Furthermore, voltage drops on sensing resistors  118  and  120 , and current which flows through sensing resistors  118  and  120 , can also be obtained according to the monitored information from sensing terminals  114 - 3 ,  114 - 4  and  114 - 5 . For example, the current which follows through the NMOS switch  106  can be measured by dividing the voltage drop on the sensing resistor  118  (V ad −V SYS ) by the resistance of the sensing resistor  118 . 
         [0027]    According to the status of the ACDC adapter  102  and battery pack  104 , the control unit  114  enters a specified working mode and generates multiple control signals, in one embodiment. 
         [0028]    If the control unit  114  detects that the battery pack  104  is in an under-voltage condition, the control unit  114  can enter the charging operation mode, in which the ACDC adapter  102  powers the system  110  and charges the battery pack  104 . In the charging operation mode, switch control signals  114 - 1  and  114 - 2  having the voltage level V 1  are generated by the control unit  114 . Upon receiving the switch control signals  114 - 1  and  114 - 2 , driving signals  112 - 1  and  112 - 2  having voltage levels Von 1  and Von 2  are generated, which in turn switch on NMOS switches  106  and  108 . Besides, an ACDC adapter control signal  114 - 6  can also be generated by the control unit  114 . The ACDC adapter control signal  114 - 6  can adjust the output (e.g., output current, output voltage, and/or output power) of the ACDC adapter  102  to satisfy the power requirement of the system  110  and the charging power requirement of the battery pack  104 , in one embodiment. In the charging operation mode, the output current of the ACDC adapter  102  flows through the NMOS switch  106  to the common node  116 . Then, a charging current I CHARGE  flows through the NMOS switch  108  to the battery pack  104  and a system current I SYS  flows to the system  110 . 
         [0029]    The charging operation mode continues until the control unit  114  detects that the battery pack  104  is fully charged, in one embodiment. Then the control unit  114  enters the operation mode, in which the adapter  102  powers the system  110 , in one embodiment. In the operation mode, the control unit  114  switches off NMOS switch  108  and switches on NMOS switch  106 , such that a current equal to I SYS  flows through the NMOS switch  106  to the system  110 . The NMOS switch  108  is switched off, which in turn avoids an over-charge condition of the battery pack  104 . 
         [0030]    If the ACDC adapter  102  is not available, to maintain proper operation of the system  110  and the power management system  100 , the power management device  100  enters a discharging mode, in one embodiment. In the discharging mode, the control unit  114  switches NMOS switch  106  off and NMOS switch  108  on. Thus, the system  110  can be powered by the battery pack  104 . 
         [0031]    In addition, if the power requirement of system  110  exceeds the designed power rating of the ACDC adapter  102 , the power management system  110  enters the heavy load mode. In the heavy load mode, the control unit  114  can generate switch control signals  114 - 1  and  114 - 2  to switch on NMOS switches  106  and  108 . Thus, the system  110  can be powered by the ACDC adapter  102  and the battery pack  104  simultaneously. In addition to the switch control signal  114 - 1  and  114 - 2 , the control unit  114  can also adjust the output of the ACDC adapter  102  so as to provide enough power to maintain a proper operation of the system  110 . 
         [0032]    Advantageously, since an NMOS switch can have an ON-state resistance substantially smaller than a PMOS switch having the same size, the power dissipation caused by NMOS switches  106  and  108  can be reduced, in one embodiment. Power dissipation on each NMOS switch in each operation mode of the power management system  100  can be determined. For example, assume that an ON-state resistance of each NMOS switch is 10 milliohm (mΩ) and the power management system  100  works in the charging operation mode (e.g., I SYS =4A, I CHARGE =3A, and the output voltage of the ACDC adapter  102  is 12V). Then, power dissipation on NMOS switch  106  is approximately 0.49 W (10 mΩ□×(4A+3A) 2 =0.49 W). Power dissipation on NMOS switch  108  is approximately 0.09 W (10 mΩ□×(3A) 2 =0.09 W). Therefore, total power dissipation on NMOS switches  106  and  108  is approximately 0.58 W. Consequently, in the power management system  100 , power dissipation on NMOS switches  106  and  108  only leads to a 0.7% decrease in the power transfer efficiency of the power management system  100 , in one embodiment. Advantageously, NMOS switches can significantly increase the power transfer efficiency of the power management system  100  if multiple NMOS switches are used. Furthermore, the overall performance and stability can be enhanced since less power dissipates on NMOS switches. 
         [0033]      FIG. 3  illustrates a block diagram of an example of a power management system  300  in which NMOS switches, a driving circuit and a DCDC converter are employed, according to another embodiment. The power management system  300  is operable for providing power to a system  326  as well as charging a battery pack  304  which can include various types of battery cells. As shown in  FIG. 3 , the power management system  300  includes two NMOS switches  306  and  308 , a control unit  310 , a driving circuit  312 , and a DCDC converter  314 , in one embodiment. NMOS switches  306  and  308  are operable for controlling power supply from a power source  302 , e.g., an ACDC adapter and/or from a rechargeable battery pack  304 , to a system  326 , in one embodiment. The power management system  300  has similar functionalities as the power management system  100 . 
         [0034]    In one embodiment, the source terminal of the NMOS switch  306  is coupled to an output terminal of the power source  302 . The drain terminal of the NMOS switch  306  is coupled to a common node  324  via a sensing resistor  320 . A source terminal and a drain terminal of the NMOS switch  308  are respectively coupled to an output terminal of the rechargeable battery pack  304  and the common node  324 . As shown in  FIG. 3 , the DCDC converter  314  is coupled between the common node  324  and a sensing resistor  322  having one end coupled to the output of the rechargeable battery pack  304 , in one embodiment. 
         [0035]    In one embodiment, the control unit  310  has four sensing terminals  310 - 1 ,  310 - 2 ,  310 - 3  and  310 - 4 . As illustrated in  FIG. 3 , sensing terminals  310 - 1 - 310 - 4  are respectively coupled to the drain terminal of the NMOS switch  306 , the common node  324 , the output terminal of the DCDC converter  314 , and the output terminal of rechargeable battery pack  304 . By detecting status of the power source  302  and the rechargeable battery pack  304 , the control unit  310  can control conductance status of NMOS switches  306  and  308 , in one embodiment. 
         [0036]    In one embodiment, if the control unit  310  detects that the rechargeable battery pack  304  is in an under-voltage condition, the control unit  310  can switch on NMOS switch  306  and switch off NMOS switch  308 . The DCDC converter  314  receives the output voltage of the power source  302  and converts it to a voltage appropriate for charging the battery pack  304 . The converted voltage can be further used to charge the rechargeable battery pack  304 . The DCDC converter  314  can include, but is not limited to, a buck converter, a boost converter, or a buck-boost converter For example, if the output voltage level of the power source  302  is lower than a charging voltage required by the rechargeable battery pack  304 , a boost converter can be used. A buck converter can also be used if the output voltage level of the power source  302  is greater than a maximum charging voltage of the battery pack  304 . Advantageously, the power management system  300  can not only increase power transfer efficiency, but can also be flexible for being used with various power sources and rechargeable battery packs. 
         [0037]      FIG. 4  illustrates a flowchart of a method for controlling power supply to a system according to one embodiment of the present invention. To control power supply to the system, the status of the system can be monitored, in block  400 . In one embodiment, input current (or voltage) of the system and output voltage of a battery pack in the system can be monitored, in block  402 . According to the monitored status of the system, a power requirement of the system can be determined. In block  404 , if the power requirement of the system is satisfied, the status of the system can be further monitored. If the power requirement of the system is not satisfied, multiple control signals can be generated and/or adjusted, in block  406 . In one embodiment, the aforementioned multiple control signals can be multiple NMOS switch control signals which can be used to control the conductance status of multiple NMOS switches. Each of the aforementioned multiple NMOS switches can be coupled between a power source and the system, in one embodiment. By using multiple NMOS switch control signals, one or more NMOS switches can be turned on so as to provide enough power to the system. The aforementioned multiple control signals can be further converted to driving signals which have adequate driving ability to fully switch on/off NMOS switches, in block  408 . In one embodiment, to fully switch on/off an NMOS switch, an NMOS switch control signal can be converted to a driving voltage which has a voltage level greater than a source voltage of the NMOS switch. By using multiple driving signals, multiple NMOS switches of the system can be fully switched on/off so as to provide sufficient power to the system, in block  410 . In one embodiment, multiple control signals can be converted to multiple driving signals by using a driving circuit which includes a charge pump unit. In addition to controlling the conductance status of multiple NMOS switches, multiple power source output control signals can be generated to control output (e.g., output power, output current or output voltage) of multiple power sources, in block  412 . In one embodiment, a power source output control signal can adjust the output voltage of a power source. By using multiple output controls signals, output powers delivered to the system can be adjusted according to the power requirement of the system, in block  414 . 
         [0038]    While the foregoing description and drawings represent the embodiments of the present invention, it will be understood that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the principles of the present invention as defined in the accompanying claims. One skilled in the art will appreciate that the invention may be used with many modifications of form, structure, arrangement, proportions, materials, elements, and components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and their legal equivalents, and not limited to the foregoing description.