Abstract:
A package for a semiconductor device is formed by a process which includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board. The cap is then sawed along the scribe line with a saw whose kerf is small enough not to sever the contact between the metal layers. The dice are thereby completely detached from each other, forming individual semiconductor device packages.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to application Ser. No. 09/395,095 and application Ser. No. 09/395,097, both of which were filed by the same applicants on the same date as this application and both of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     After the processing of a semiconductor wafer has been completed, the resulting integrated circuit (IC) chips or dice must be separated and packaged in such a way that they can be connected to external circuitry. There are many known packaging techniques. Most involve mounting the die on a leadframe, connecting the die pads to the leadframe by wire-bonding or otherwise, and then encapsulating the die and wire bonds in a plastic capsule, with the leadframe left protruding from the capsule. The encapsulation is often done by injection-molding. The leadframe is then trimmed to remove the tie bars that hold it together, and the leads are bent in such a way that the package can be mounted on a flat surface, typically a printed circuit board (PCB). 
     This is generally an expensive, time-consuming process, and the resulting semiconductor package is considerably larger than the die itself, using up an undue amount of scarce “real estate” on the PCB. In addition, wire bonds are fragile and introduce a considerable resistance between the die pads and the leads of the package. 
     The problems are particularly difficult when the device to be packaged is a “vertical” device, having terminals on opposite faces of the die. For example, a power MOSFET typically has its source and gate terminals on the front side of the die and its drain terminal on the back side of the die. Similarly, a vertical diode has its anode terminal on one face of the die and its cathode terminal on the opposite face of the die. Bipolar transistors, junction field effect transistors (JFETs), and various types of integrated circuits (ICs) can also be fabricated in a “vertical” configuration. 
     Accordingly, there is a need for a process which is simpler and less expensive than existing processes and which produces a package that is essentially the same size as the die. There is a particular need for such a process and package that can be used with semiconductor dice having terminals on both their front and back sides. 
     SUMMARY OF THE INVENTION 
     The process of fabricating a semiconductor device package in accordance with this invention begins with a semiconductor wafer having a front side and a back side and comprising a plurality of dice separated by scribe lines. Each die comprises a semiconductor device. A surface of the front side of each die comprises a passivation layer and at least one connection pad in electrical contact with a terminal of the semiconductor device. The back side of each die may also be in electrical contact with a terminal of the semiconductor device. 
     The process comprises the following steps: forming a first metal layer in electrical contact with the connection pad, a portion of the first metal layer extending laterally beyond an edge of the die; attaching a cap to the front side of the wafer; cutting through the semiconductor wafer from the back side of the wafer in the scribe line area to form a first cut, the first cut having a first kerf W 1  and exposing a part of the first metal layer; forming a nonconductive layer on the back side of the die; forming a second metal layer, the second metal layer having a first section extending over the nonconductive layer and being in electrical contact with the first metal layer; and cutting through the cap in the scribe line area to form a second cut having a second kerf W 2  that is less than the first kerf W 1 , the second cut leaving in place an area of contact between the first and second metal layers. 
     In many embodiments, the process also includes forming a second section of the second metal layer in electrical contact with the backside of the semiconductor wafer, the first and second sections of the second metal layer being electrically insulated from each other. The process may also include grinding, lapping or etching the back side of the semiconductor wafer to reduce the thickness of the wafer after attaching the cap to the front side of the wafer. 
     In one aspect, the invention includes a process for making an electrical connection between a first location on a first side of a semiconductor die and a second location on a second side of the semiconductor die. The process commences while the die is a part of a semiconductor wafer. The process comprises forming a first metal layer extending laterally from the first location on the first side of the die to an area of the wafer beyond an edge of the die; attaching a cap to the first side of the wafer; cutting through the semiconductor wafer from the second side of the wafer to expose a part of the first metal layer; forming a second metal layer extending laterally from the second location on the second side of the die and along an edge of the die to a region of contact with the first metal layer beyond the edge of the die; and cutting through the cap while leaving intact the region of contact between the first and second metal layers. 
     This invention also includes package for a semiconductor device. The package comprises a cap having a width X 1 ; a semiconductor die containing a semiconductor device, the die being attached to the cap with a front side of the die facing the cap and a back side of the die facing away from the cap, the die having a width X 2  that is less than X 1 ; a connection pad in electrical contact with the semiconductor device, the contact being located between the die and the cap and having a width no greater than X 2 ; a first metal layer in electrical contact with the connection pad, a first portion of the first metal layer being located between the connection pad and the cap and a second portion of the first metal layer extending laterally beyond an edge of the connection pad; a second metal layer having first and second sections, the first section of the second metal layer being in contact with the second portion of the first metal layer, the second section being in electrical contact with the backside of the wafer, the first and second sections of the second metal layer being electrically insulated from each other. 
     In yet another aspect, this invention includes a package for a semiconductor device comprising a semiconductor die containing a semiconductor device, a first side of the die comprising a connection pad; a cap attached to the first side of the die, an edge of the cap extending laterally beyond an edge of the die; a first metal layer in electrical contact with the connection pad, the first metal layer extending laterally and terminating in a first flange beyond an edge of the die; and a second metal layer extending from a second side of the die and along an edge of the die and terminating in a second flange beyond the edge of the die, the second flange being in contact with the first flange. 
     Semiconductor packages according to this invention do not require an epoxy capsule or bond wires; the substrate attached to the die serves to protect the die and acts as a heat sink for the die; the packages are very small (e.g., 50% the size of molded packages) and thin; they provide a very low on-resistance for the semiconductor device, particularly if the wafer is ground thinner; they are economical to produce, since they require no molds or lead frames; and they can be used for a wide variety of semiconductor devices such as diodes, MOSFETs, JFETs, bipolar transistors and various types of integrated circuit chips. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This invention will be better understood by reference to the following drawings (not drawn to scale), in which similar components are similarly numbered. 
     FIG. 1 illustrates a top view of a semiconductor wafer. 
     FIGS. 2A-2B through  4 A- 4 B,  5 ,  6 , and  7 A- 7 B through  12 A- 12 B illustrate the steps of a process of fabricating a semiconductor package in accordance with this invention. 
     FIG. 13 illustrates a cross-sectional view of a semiconductor package in accordance with this invention. 
     FIG. 14 illustrates an embodiment of the semiconductor package which includes solder balls. 
    
    
     DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a top view of a semiconductor wafer  100  which contains dice  100 A,  100 B through  100 N. In reality, wafer  100  would contain hundreds or thousands of dice. The individual dice are separated by a perpendicular network of scribe lines, with scribe lines  108  running in the Y direction and scribe lines  110  running in the X direction. Metal pads for connecting to external circuit elements are located on the top surface of each of the dice  100 A- 100 N. For example, since dice  100 A- 100 N contain vertical power MOSFETs, each die has a source connection pad  106 S and a gate connection pad  106 G. 
     Wafer  100  is typically has a thickness in the range of 15-30 mils. Wafer  100  is typically silicon but it could also be another semiconductor material such as silicon carbide or gallium arsenide. 
     As described above, before dice  100 A- 100 N can be used they must be packaged in a form that allows them to be connected to external circuitry. 
     The process of this invention is illustrated in FIGS. 2A-2B through  4 A- 4 B,  5 ,  6 , and  7 A- 7 B through  12 A- 12 B, which show dice  100 A and  100 B that are part of semiconductor wafer  100 . In each drawing where applicable, the figure labeled “A” is taken from a top or bottom view of the wafer; the figure labeled “B” is a cross-sectional view taken at the section labeled “B—B” in the “A” figure. As described below, in the course of the process the wafer is attached to a “cap”, the front side of the wafer normally facing the cap. In the finished package, the wafer is positioned under the cap, although at some points in the process the structure may be inverted, with the cap under the wafer. Unless the context clearly indicates otherwise, as used herein “above”, “below”, “over”, “under” and other similar terms refer to the package in its finished form with the cap above the wafer. 
     This invention will be described with respect to a package for a vertical power MOSFET, which typically has source and gate terminals on its front side and a drain terminal on its back side. It should be understood, however, that the broad principles of this invention can be used to fabricate a package for any type of semiconductor die which has one or more terminals on both its front and back sides or on its front side alone. As used herein, the “front side” of a die or wafer refers to the side of the die or wafer on which the electrical devices and/or a majority of the connection pads are located; “back side” refers to the opposite side of the die or wafer. The directional arrow labeled “Z” points to the front side of the wafer and identifies the drawings in which the wafer is inverted. 
     Referring to FIGS. 2A-2B, since dice  100 A and  100 B contain power MOSFETs (shown symbolically), each die has a gate metal layer  102 G and a source metal layer  102 S overlying the top surface of the silicon or other semiconductor material. Gate metal layers  102 G and source metal layers  102 S are in electrical contact with the gate and source terminals (not shown), respectively, of the power MOSFETs within dice  100 A and  100 B. In FIG. 2A, the separation between layers  102 G and  102 S is shown by the dashed lines. 
     Typically, metal layers  102 G and  102 S include aluminum, although copper layers are also being used. In most embodiments of this invention, metal layers  102 G and  102 S need to be modified so that they will adhere to a solder metal such as tin/lead, for the reasons described below. If there is a native oxide layer on the metal, this native oxide layer must first be removed. Then a solderable metal, such as gold, nickel or silver, is deposited on the exposed metal. The removal of the oxide layer and deposition of a solderable metal can be accomplished by means of a number of known processes. For example, an aluminum layer can be sputter-etched to remove the native aluminum oxide layer and then gold, silver or nickel can be sputtered onto the aluminum. Alternatively, the die can be dipped in a liquid etchant to strip away the oxide layer and the solderable metal can then be deposited by electroless or electrolytic plating. Electroless plating includes the use of a “zincating” process to displace the oxide, followed by the plating of nickel to displace the zincate. 
     In one embodiment metal layers  102 G and  102 S include a 3 μm sublayer of Al overlain by a 1,000 Å TiN sublayer and a 500 Å Ti sublayer. 
     A passivation layer  104  overlies a portion of gate metal layers  102 G and source metal layers  102 S, and openings in passivation layer  104  define gate connection pads  106 G and source connection pads  106 S. Passivation layer  104  can be formed of phosphosilicate glass (PSG) 1 mil thick, for example. 
     Dice  100 A and  100 B are separated by a Y-scribe line  108 , which can be 6 mils wide. X-scribe lines  110  perpendicular to scribe line  108  at the top and bottom of dice  100 A and  100 B can be 4 mils wide. 
     A sublayer  202  of titanium is sputtered onto the front side of wafer  100 , and a sublayer  204  of aluminum is sputtered over the titanium sublayer  202 . For example, titanium sublayer  202  may be 500 Å thick and aluminum sublayer  204  may be 3 μm thick. Sublayers  202  and  204  are then masked and etched, using conventional photolithographic and etching processes, so that the portions of sublayers  202  and  204  shown in FIGS. 3A-3B remain. Portions  202 G,  204 G of sublayers  202 ,  204  cover the gate connection pads  106 G and portions  202 S,  204 S of sublayers  202 ,  204  cover the source connection pads  106 S. Portions  202 G,  204 G are electrically insulated from portions  202 S,  204 S. As shown, the sublayers  202 G,  202 S and  204 G,  204 S extend laterally into the area of Y-scribe line  108 . 
     A 10 μm nickel sublayer  206  is then plated electrolessly onto the top surface of aluminum sublayers  204 G and  204 S and a 0.1 μm gold sublayer  208  is plated on nickel sublayer  206 . The resulting structure is shown in FIGS. 4A-4B, with portions  206 G and  208 G of sublayers  206  and  208 , respectively, overlying gate connection pads  106 G and portions  206 S and  208 S of sublayers  206  and  208 , respectively, overlying source connection pads  106 S. Portions  206 G,  208 G are electrically insulated from portions  206 S,  208 S. 
     Together sublayers  202 ,  204 ,  206  and  208  in each die form a first metal layer  209 . In other embodiments, the first metal layer  209  can include fewer or more than four sublayers, and the sublayers can be deposited by any of the known processes such as sputtering, evaporation, electroless or electrolytic plating, stencil printing or screen-printing. Sublayers  202 ,  204 ,  206  and  208  will sometimes be referred to herein collectively as “first metal layer  209 ”. 
     A cap  212  is attached to the front side of wafer  100  with a nonconductive adhesive layer  210 . Layer  210  can be 25 μm thick and can be an epoxy. Cap  212  can be made of glass, plastic or copper and can be 250-500 μm thick. This structure is shown in FIG. 5, with wafer  100  being inverted from the previous drawings and cap  212  being shown below wafer  100 . 
     As shown in FIG. 6, wafer  100  is then optionally ground from its back side to a thickness of 3-4 mils or as thin as is possible without damaging the internal microstructure of the semiconductor devices within the dice (which can be, for example, trench-gated MOSFETs). For example, a grinding machine available from Strausbaugh can be used. This is possible because of the support provided by cap  212 . Grinding reduces the resistance to current flow from the front side to the back side of wafer  100 . 
     As an alternative to grinding, wafer  100  can be thinned by lapping or etching the back side of the wafer. 
     Preferably using a taper saw, a cut is then made along Y-scribe line  108  from the back side of wafer  100 , leaving a thickness of about 1 mil of silicon at the location of the cut. The kerf of the saw cut is indicated as W 1 . The remaining thickness of silicon is then etched, using a known silicon etchant, to expose the portion of the first metal layer  209  that extends into the area of Y-scribe line  108 . In this case, the titanium sublayer  202  is initially exposed. The cut does not extend all the way through the first metal layer  209  to the adhesive layer  210  and cap  212 . The resulting structure is shown in FIGS. 7A and 7B. 
     An insulating layer  214 , which can be made of polyimide, PSG, nonconductive epoxy, or another nonconductive material, is deposited on the back side of wafer  100 . Insulating layer  214  can be deposited by spin-coating, dispensing or screen-printing and can be 1 mil thick. Insulating layer  214  is masked and etched, using normal photolithographic and etching techniques, so that portions of insulating layer  214  overlying the first metal layer  209  and portions of the backside of the wafer  100  are removed, as shown in FIGS. 8A and 8B. 
     In some embodiments, particularly if the side of the wafer facing away from the cap is already covered by an insulating layer (e.g., a passivation layer), it may be possible to omit the deposition of an insulating layer. 
     A sublayer  216  of titanium is sputtered onto the back side of wafer  100 , and a sublayer  218  of aluminum is sputtered over the titanium sublayer  216 . For example, titanium sublayer  216  may be 500 Å thick and aluminum sublayer  218  may be 3 μm thick. Sublayers  216  and  218  are then masked and etched, using conventional photolithographic and etching processes, so that the portions of sublayers  216  and  218  shown in FIGS. 9A and 9B remain. Sections  216 G,  218 G of sublayers  216 ,  218  contact the first metal layers  209  in the scribe line area  108 , and by means of the first metal layers  209  sections  216 G,  218 G are in electrical contact with the gate connection pads  106 G. Sections  216 S,  218 S of sublayers  216 ,  218  contact the first metal layers  209  in the scribe line area  108  and by means of the first metal layers  209  are in electrical contact with the source connection pads  106 S. Sections  216 D,  218 D of sublayers  216 ,  218  contact the back side of dice  100 A and  100 B which represent the drain terminals of the MOSFETs. Sections  216 G,  218 G and  216 S,  218 S extend over insulating layer  214  on the back side of dice  100 A and  100 B. Sections  216 G,  218 G and  216 S,  218 S and  216 D,  218 D are electrically insulated from each other. 
     A 10 μm nickel sublayer  220  is then plated electrolessly onto the top surface of aluminum sublayers  218 G,  218 S and  218 D, and a 0.1 μm gold sublayer  222  is plated on nickel sublayer  220 . The resulting structure is shown in FIGS. 10A and 10B, with sections  220 G and  222 G of sublayers  220  and  222 , respectively, overlying sections  216 G,  218 G; sections  220 S and  222 S of sublayers  220  and  222 , respectively, overlying sections  216 S,  218 S; and sections  220 D and  222 D of sublayers  220  and  222 , respectively, overlying sections  216 D,  218 D. 
     Together sublayers  216 ,  218 ,  220  and  222  in each of dice  100 A and  100 B form a second metal layer  223 . In other embodiments, the second metal layer  223  can include fewer or more than four sublayers, and the sublayers can be deposited by any of the known processes such as sputtering, evaporation, electroless or electrolytic plating, or screen-printing. Sublayers  216 ,  218 ,  220  and  222  will sometimes be referred to herein collectively as “second metal layer  223 ”. 
     As shown in FIGS. 11A and 11B, solder paste is screen-printed on the second metal layers  224  and then reflowed to form solder posts  224 G,  224 S and  224 D. The solder paste can be 4-5 mils thick. Solder posts  224 G,  224 S and  224 D are electrically insulated from each other. Solder balls, studs, or layers can be used in place of solder posts. 
     Finally, as shown in FIGS. 12A and 12B, dice  100 A and  100 B are separated by saw-cutting cap  212  along Y-scribe line  108 , preferably in the same direction as the first cut, from the back side to the front side of the dice. The kerf of the cut (W 2 ) is less than W 1  so that the portions of the first and second metal layers  209 ,  223  that extend into the scribe line area are left in place. The dice are also separated along the X-scribe lines  110 . As an alternative to saw-cutting, cap  212  can be cut using other known processes such as photolithographic patterning and etching. 
     The resulting semiconductor package  226 , including die  100 A, is shown in the cross-sectional view of FIG.  13 . Package  226  is oriented with a cap  212 A over die  100 A. As shown, cap  212 A has a width X 1 . Die  100 A is attached to cap  212 A, with a front side of die  100 A facing cap  212 A and a back side of  100 A die facing away from cap  212 A. Die  100 A has a width X 2  that is less than X 1 . Connection pad  106 G is in electrical contact with the semiconductor device within die  100 A. The gate metal layer  102 G and gate connection pad  106 G are located between die  100 A and cap  212 A. The first metal layer  209  is in electrical contact with gate connection pad  106 G. A first section  209 A of the first metal layer  209  is located between gate metal layer  102 G and cap  212 A, and a second section  209 B of the first metal layer  209  extends laterally beyond the edge of gate metal layer  102 G. A second metal layer  223  has first and second sections  223 A and  223 B. The first section  223 A of the second metal layer  223  is in contact with the second section  209 B of the first metal layer  209  at a location beyond the edge of the die  100 A and is insulated from the back side of die  100 A by insulating layer  214 . The first section  223 A of the second metal layer  223  also includes a slanted portion  223 X that extends at an oblique angle along the edge of the die  100 A. The second section  223 B of the second metal layer  223  is in electrical contact with the backside of the die  100 A. 
     It will be apparent that the first metal layer  209  terminates in a first “flange”  209 F which extends beyond the edge of the die  100 A, and that the second metal layer extends along the edge of the die  100 A and terminates in a second “flange”  223 F beyond the edge of the die  100 A, and that the first and second flanges  209 F,  223 F are in contact with each other and extend longitudinally outward from die  100 A in a direction parallel to the sides of die  100 A. 
     Package  226  can easily be mounted on, for example, a PCB using solder posts  224 G and  224 D. Solder post  224 S is not shown in FIG. 13 but it too would be connected to the PCB so that the source, gate, and drain terminals of the MOSFET would be connected to the external circuitry. The drain terminal is on the back side of die  100 A and is electrically connected via section  223 B of second metal layer  223 . Package  226  contains no wire bonds and, as has been shown, can be manufactured in a batch process using the entire wafer. 
     FIG. 14 shows an embodiment of semiconductor package  226  which includes solder balls  230  instead of solder posts. The solder balls may be applied in a conventional manner by depositing and reflowing solder paste or by other processes such as screen-printing or solder jetting (using, for example, equipment available from Pac Tech GmbH, Am Schlangenhorst 15-17, 14641 Nauen, Germany), or by using the wafer level solder ball mounter available from Shibuya Kogyo Co., Ltd., Mameda-Honmachi, Kanazawa 920-8681, Japan. Conductive polymer bumps are another alternative, using for example thermosetting polymers, B-state adhesives, or thermoplastic polymers. 
     While a specific embodiment of this invention has been described, the described embodiment is intended to be illustrative and not limiting. It will be apparent to those who are skilled in the art that numerous alternative embodiments are possible within the broad scope of this invention.