Abstract:
A system and same method are provided for producing video signal timing to a display apparatus that has different input/output image/video format. In addition to an image scaler, the system comprises a clock adjuster including a first and a second clock generator. The first clock generator generates a first clock signal by which the input/source pixel data included in the input/source image frame are received. The second clock signal is generated and adjusted to have an average clock period such that the ratio of the input and output frame rates is substantially kept constant. Thus, the skew between the source/input images and the display/output images can be adjusted, and the output frame repeating and/or dropping can be avoided.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to video display systems. More particularly, the present invention is directed to a method and apparatus to convert a source image to a destination image, and is directed to a method and apparatus to produce video signal timing to a display apparatus that has an output/display video format different from an input video format. 
   2. Description of the Prior Art 
   There are numerous kinds of interlaced video signals such as NTSC and PAL, and progressive scan video signals such as VESA VGA, SVGA, XGA, and SXGA. Several methodologies have been adopted in the prior art method in order to accommodate different types of source video signals for viewing on a single display apparatus. And the prior art method involves converting resolution and the frame rate of source video signals which usually include a plurality of image frames/fields to a format which is supported by the display apparatus, such as LCDs, plasma display panels (PDPs), and TV sets. 
   In the display apparatus, there are usually a controller and a display screen, such as a flat panel display and a CRT monitor. The controller is provided for performing necessary video format conversion and related controlling functions. The buffer is provided for receiving and temporarily storing the source video signals. The display apparatus receives the image frames at an input frame rate, and outputs at an output frame rate after performing necessary video format conversion. 
   If the input and output frame or field rates do not match each other, the data transferred for displaying the output images will overflow or underflow in the buffer. Then, the picture displayed will come from two different frames. It is referred as “frame tear” problem. A solution to solve the “frame tear” problem adapted in the prior art is to drop or to repeat the input image frames/fields by the frame buffer. However, such a solution would generate objectionable temporal distortions in the output image frames/fields. This is not acceptable for high-quality display apparatuses. 
   If the display apparatus can lock the output frame/field rate to the input frame/field rate, there are significant advantages because image fields/frames no longer need to be repeated or dropped, and the aforementioned temporal distortion problem in the displaying sequence for the image frames/fields can be eliminated. 
   Furthermore, in case the display apparatus has different input and output frame/field rates, if we can also lock the output frame/field rate to a fractional multiple of input frame/field rate, the “frame tear” problem can be avoid and the frame repeating and dropping will be reduced. The frame repeating and dropping will be periodic and predictable. 
   Therefore, one objective of the present invention is to provide a method and corresponding apparatus for solving the above-mentioned problems. 
   SUMMARY OF THE INVENTION 
   One objective of the present invention is to provide a method and an apparatus for video signal conversion that can adjust the skew between the source/input video signal and the destination/output/display video signal. 
   Another objective of the present invention is to provide a method and an apparatus for video/image converting that can reduce or avoid the frame being repeated and dropped while the destination/output/display image frames/fields are being outputted. 
   Sill an objective of the present invention is to provide a method and an apparatus for video signal converting that can keep the ratio of the input and output frame rates. The ratio could be a constant, either an integer or a fraction. 
   The advantage and spirit of the invention could be better understood by the following recitations together with the appended drawings. 

   
     BRIEF DESCRIPTION OF THE APPENDED DRAWINGS 
       FIG. 1  shows the signal flow chart of the format conversion system according to one embodiment of the present invention. 
       FIG. 2  shows the block diagram of the format conversion system according to the embodiment. 
       FIG. 3  shows the timing diagram of the original destination horizontal synchronization signal (HSYNC_dst), the estimated source horizontal synchronization signal (HSYNC_src′), the original source horizontal synchronization signal (HSYNC_src), and the adjusted destination horizontal synchronization signal (adjusted HSYNC_dst) 
       FIG. 4  shows the block diagram of the clock adjuster according to the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  shows the signal flow chart of the format conversion system according to one embodiment of the present invention. In  FIG. 1 , the format conversion system  100  of the present invention receives a source video signal  102  from a signal line and/or a data bus  200 . The source video signal  102  includes a plurality of source image frames  104  which are received by the format conversion system  100  at an input frame rate  101  and are extracted from the corresponding source video signal  102 . Each source image frame  104  includes a plurality of source scan lines  107  and each source scan line  107  has a plurality of source pixel data  109 . The source pixel data  109  are received with the aid of a first clock signal (CLK_src)  174 . The source image frame  104  includes a plural predetermined source video parameters: a source frame rate (Ftotal_src)  106 , a source vertical length (Vtotal_src)  108  which indicates the number of source scan lines  107  in one source image frame  104 , and a source horizontal length (Htotal_src)  110  which indicates the number of source pixel data  109  in one source scan line  107 . The resolution of the source image frame  104  is determined by the source vertical length (Vtotal_src)  108  and the source horizontal length (Htotal_src)  110 . 
   After the video signal conversion function of the format conversion system  100  is performed, the system  100  outputs a destination video signal  112  to a display screen  300  for suitable and adjusted video/image displaying. The destination video signal  112  includes a plurality of destination image frames  114  which are outputted by the format conversion system  100  at an output frame rate  111 . Each destination image frame  114  includes a plurality of destination scan lines  117  and each destination scan line  117  has a plurality of destination pixel data  119 . The destination pixel data  119  are outputted with the aid of a second clock signal (CLK_dst)  184 . The destination image frame  114  includes a plural predetermined destination video parameters: a destination frame rate (Ftotal_dst)  116 , a destination vertical length (Vtotal_dst)  118  which indicates the number of destination scan lines  117  in one destination image frame  114 , and a destination horizontal length (Htotal_dst)  120  which indicates the number of destination pixel data  119  in one destination scan line  117 . The resolution of the destination image frame  114  is determined by the destination vertical length (Vtotal_dst)  118  and the destination horizontal length (Htotal_dst)  120 . 
   When the desired resolution of the destination image frame  114  is higher than the original resolution of the source image frame  104 , the format conversion system  100  would “upscale” the source image frame  104  in vertical and/or horizontal directions to generate the destination image frame  114 . In contrast, when the desired resolution of the destination image frame  114  is lower than the original resolution of the source image frame  104 , the present format conversion system  100  would “downscale” the source image frame  104  in vertical and/or horizontal directions to generate the destination image frame  114 . The format conversion system  100  provides an efficient method for such video signal format/image resolution conversion and avoids the drawbacks introduced by the prior arts. 
     FIG. 2  shows the block diagram of the format conversion system  100  according to the embodiment. The format conversion system  100  includes a memory (for example: DRAM)  130 , a video standard detector  160 , a line buffer  140 , an image scaler  150 , a clock adjuster  170 , and a timing controller  190 . The memory  130  receives and stores the plural source pixel data  109 , which are contained in the received source video signal  102  and are received by the aid of the first clock signal (CLK_src)  174 . The incoming source video signal  102  could be defined as a specific video signal standard, for example: CCIR-656 NTSC, VGA 1280×1024@75, etc. Different video signal standards define different source frame rate (Ftotal_src), different source vertical length (Vtotal_src) and different source horizontal length (Htotal_src). The video standard detector  160  is employed to detect the source video signal and to identify video signal standard to which the incoming source video signal  102  belongs. The identified result  162  would then be forwarded to the clock adjuster  170 . Based on the result  162 , the clock adjuster  170  can refer to a look-up table  176  to find out the predetermined source video parameters of the source image frame  104 , such as source frame rate (Ftotal_src), source vertical length (Vtotal_src) and source horizontal length (Htotal_src). 
   If the video signal standard of the source video signal is identified as NTSC, PAL, HDTV, VGA, or other types of video format, the source frame rate is their respectively specified (Ftotal_src) frame/second, the source vertical length is their respectively specified (Vtotal_src) lines/frame, and the source horizontal length can then be computed as CLK_src/(Ftotal_src*Vtotal_src) pixels/line. There are two examples as following: 
                                                         NTSC   PAL                                    Input CLK_src(MHz)   13.5   13.5       Ftotal_src(frame/sec)   29.97   25       Vtotal_src(lines/frame)   525   625       Computed   13500000/   13500000/           (29.97*525) = 858   (25*625) = 864       Htotal_src(pixels/line)                    
By referring to these parameters, the clock adjuster  170  can generate an adjusted and updated new clock signal (New CLK_dst)  188 . The detailed function and operation of the clock adjuster  170  will be explained later in  FIG. 4 , and is skipped here to avoid redundancy. Based on the rendered and updated clock signal (New CLK_dst)  188 , the timing controller  190  can output the adjusted horizontal synchronization signal (HSYNC_dst)  194  and the adjusted vertical synchronization signal (VSYNC_dst)  192  by counting based on the updated clock signal (New CLK_dst)  188 . A counter  196  in the timing controller  190  would perform counting according to the destination video parameters: the destination horizontal length (Htotal_dst)  120  which indicates the number of destination pixel data  119  in one destination scan line  117 , and the destination vertical length (Vtotal_dst)  118  which indicates the number of destination scan lines  117  in one destination image frame  114 . The adjusted horizontal synchronization signal (HSYNC_dst)  194  and the adjusted vertical synchronization signal (VSYNC_dst)  192  are outputted for assisting the line buffer  140 , the image scaler  150  and the display screen  300 .
 
   The line buffer  140  would then temporarily store the source pixel data  109  of the current source scan line/lines  107  from the memory  130  based on the adjusted HSYNC_dst signal  194  and the adjusted VSYNC_dst signal  192 . The image scaler  150  includes a vertical interpolator  152  and a horizontal interpolator  154 . The vertical interpolator  152  scales, either upscales or downscales, the source pixel data  109  of the source image frame  104  in the vertical direction based on the adjusted HSYNC_dst signal  194  and the adjusted VSYNC_dst signal  192 . The horizontal interpolator  154  scales, either upscales or downscales, the source pixel data  109  of the source image frame  104  in the horizontal direction based on the adjusted HSYNC_dst signal  194 . That is, the image scaler  150  scales the source pixel data  109  of the source image frame  104  in vertical and/or horizontal directions to generate the plural destination pixel data  119  representative of the destination image frame  114 . Those destination pixel data  119  of the destination image frame  114  are displayed on the display screen  300  based on the adjusted second clock signal (New CLK_dst)  188 . The vertical interpolation procedure employed in the vertical interpolator  152  and the horizontal interpolation procedure employed in the horizontal interpolator  154  are well-known for those skilled in the video/image processing art. No further detail is here provided for the interpolation operation in the vertical interpolator  152  and the horizontal interpolator  154 . 
   The frequency relationship between the first clock signal (CLK_src)  174  and the second clock signal (CLK_dst)  184  can be expressed in the following equation (Equ.1): 
                   CLK_dst   CLK_src     =       Ftotal_dst   *   Vtotal_dst   *   Htotal_dst       Ftotal_src   *   Vtotal_src   *   Htotal_src               (     Equ   .           ⁢   1     )               
The period of the source horizontal synchronization signal (HSYNC_src)  175  is defined as (T_Hsrc), which is equal to the value of (Htotal_src)  110  divided by the frequency of the first clock signal (CLK_src)  174 . The relationship is shown in the following equation (Equ.2):
   T   —   Hsrc=CLK   —   src   −1   *H total —   src   (Equ.2) 
Similarly, the period of the destination horizontal synchronization signal (HSYNC_dst) is defined as (T_Hdst), which is equal to the value of (Htotal_dst)  120  divided by the frequency of the second clock signal (CLK_dst)  184 . The relationship is shown in the following equation (Equ.3):
   T   —   Hdst=CLK   —   dst   −1   *H total —   dst   (Equ.3) 
Combining the equations of (Equ.1), (Equ.2) and (Equ.3), the relationship between the periods of (T_Hsrc) and (T_Hdst) can be expressed in the following equation (Equ.4):
 
                 T_Hsrc   =         Ftotal_dst   *   Vtotal_dst       Ftotal_src   *   Vtotal_src       *   T_Hdst             (     Equ   .           ⁢   4     )               
The ratio for (T_Hsrc) and (T_Hdst) can be defined as (Ftotal_dst*Vtotal_dst)/(Ftotal_src*Vtotal_src). That means, if we know the period of the source horizontal synchronization signal (HSYNC_src), all the required parameters (Ftotal_dst), (Vtotal_dst), (Ftotal_src) and (Vtotal_src) can be easily obtained and the period of the destination horizontal synchronization signal (HSYNC_dst) can be calculated by using the above equation (Equ.4).
 
   However, because the incoming source video signal  102  might be instable and thus unpredictable, the source pixel data  109  of the source image frame  104  might not be stably received. This would also lead to variation of the first clock signal (CLK_src)  174 . That means the first clock signal (CLK_src)  174  may be variant over time, and the input frame rate (or the input pixel rate) won&#39;t be always fixed. Therefore, we have to modify the second clock signal (CLK_dst)  184  according to the varied first clock signal (CLK_src)  174 , so as to let the fixed ratio (Ftotal_dst*Vtotal_dst)/(Ftotal_src*Vtotal_src) be maintained. According to the above equation (Equ.4), once the input frame rate (or the input pixel rate) is changed, T_Hsrc must also be changed. If we can also modify T_Hdst, the fixed ratio can be maintained. 
     FIG. 3  shows the timing diagram of the original destination horizontal synchronization signal (HSYNC_dst), the estimated source horizontal synchronization signal (HSYNC_src′), the original source horizontal synchronization signal (HSYNC_src), and the adjusted destination horizontal synchronization signal (adjusted HSYNC_dst). The original destination horizontal synchronization signal (HSYNC_dst) can be generated if (Htotal_dst) is divined by (CLK_dst)  184 . Equally, the original (HSYNC_src) can be computed by (Htotal_src) being divided by (CLK_src). According to (Equ.4), the estimated source horizontal synchronization signal (HSYNC_src′) can be obtained by (Ftotal_dst*Vtotal_dst)/(Ftotal_src*Vtotal_src) times (T_Hdst). Here, (T_Hdst) varies with the changing of (CLK_dst)(or (New CLK_dst)). The changing of (CLK_dst)(or (New CLK_dst)) is generated by comparing (HSYNC_src′) with (HSYNC_src). (HSYNC_src′) and (HSYNC_src) are compared to obtain a phase difference (Δt_src) which represents the difference between them. With this phase difference (Δt_src), some signal feed-back mechanism can be designed and employed to minimize the phase difference (Δt_src), so as to generate the adjusted destination horizontal synchronization signal (adjusted HSYNC_dst), and accordingly the second clock signal (New CLK_dst). The signal (New CLK_dst) is generated by adjusting the original second clock signal (CLK_dst), so that the output frame/field rate can be locked to the input frame/field rate. The ratio of the input and output frame/field rates needs merely to be kept or locked around a constant over a period of time. That is, exactness at any given temporal moment is not necessary. Minor variation over this constant along the temporal axis, more or less, is acceptable. Such circuit design will be explained in the following paragraph associated with the clock adjuster  170  together with the present invention. 
     FIG. 4  shows the block diagram of the clock adjuster  170  in the embodiment. In  FIG. 4 , the detailed components associated with the clock adjuster  170  are depicted. The clock adjuster  170  is to generate an adjusted second clock signal (New CLK_dst)  188 , such that by adjusting its second clock period (CLK_dst) the ratio of the input and output frame rates is substantially kept constant. 
   In an exemplary embodiment, the clock adjuster  170  includes a first timing generator  171 , a second timing generator  181 , a phase frequency detector (PFD)  186 , and a phase locked loop (PLL)  187 . By using this first clock signal (CLK_src)  174 , the plural source pixel data  109  included in the source image frame  104  are received by the format conversion system  100 . Because of the unpredictability and instability of the incoming source video signal  102 , the source pixel data  109  of the source image frame  104  may not be well received. This would also lead to the variation of the first clock signal (CLK_src)  174 . That means the period of the first clock signal (CLK_src)  174  might be variant over time. In the first timing generator  171 , a first divider  172  is employed for dividing a first factor  173  by the first clock signal (CLK_src) to generate a source horizontal synchronization signal (HSYNC_src)  175 . The first factor  173  is the source horizontal length (Htotal_src) which can be pre-stored in first divider  172 . Furthermore, if there is a horizontal synchronization input accompanied with the video input, which is sampled by CLK_src, the first timing generator  171  uses this horizontal synchronization input instead of the output of first divider  172 . In the second clock generator  181 , a second divider  182  is employed for dividing a second factor  183  by the second clock signal (CLK_dst)  184  to generate an estimated source horizontal synchronization signal (HSYNC_src′)  185 . Here, the second clock signal can be generated by, for example, another local oscillator and is independent from the first clock signal (CLK_src). The second factor  185  is the value (Htotal_dst*Vtotal_dst*Ftotal_dst) Because the second factor  185  may be a fractional value, a fractional divider is preferred for the implementation of the second divider  182 . 
   The source horizontal synchronization signal (HSYNC_src)  175  and the estimated source horizontal synchronization signal (HSYNC_src′)  185  are forwarded to the phase frequency detector (PFD)  186 . The phase frequency detector  186  includes a comparator  189  for comparing the estimated source horizontal synchronization signal (HSYNC_src′) with the source horizontal synchronization signal (HSYNC_src) to obtain a phase difference (Δt_src)  176 . Ideally, the phase difference (Δt_src)  176  is zero if the period of the first clock signal (CLK_src)  174  is not varied due to some reasons, for example: instability of the incoming source video signal  102 . When the period of the first clock signal (CLK_src)  174  is not fixed in its due duration, the phase difference (Δt_src)  176  would be rendered. The phase difference (Δt_src)  176  is in proportion to the phase difference between the rising or falling edges of two signals (HSYNC_src)  175  and (HSYNC_src′)  185 . 
   The phase locked loop  187  is configured to receive the phase difference (Δt_src)  176  from the phase frequency detector  186 . Using the obtained phase difference (Δt_src)  176 , the phase locked loop  187  is able to adjust the clock period of the original second clock signal (CLK_dst)  184 , so as to generate the adjusted second clock signal (New CLK_dst)  188 . This can be achieved by feeding back the adjusted second clock signal (New CLK_dst)  188  to the second divider  183 . Then, the adjusted second clock signal (New CLK_dst)  188  divide the second divider  183 . Such signal feed-back mechanism is known and widely-employed in the art of signal processing field. With the signal feed-back mechanism, the obtained phase difference (Δt_src)  176  would be gradually minimized and even reduced to zero over a short period of time. When the updated clock signal (New CLK_dst)  188  is generated, it can be provided to the timing controller  190  for outputting the adjusted horizontal synchronization signal (HSYNC_dst)  194  and the adjusted vertical synchronization signal (VSYNC_dst)  192  by counting based on the updated clock signal (New CLK_dst)  188 . The destination pixel data  119  of the destination image frame  114  are therefore displayed on the display screen  300  based on the updated clock signal (New CLK_dst)  188 . 
   It should be noted that the function of the first clock signal (CLK_src) in the embodiment could be external or internal. That means the embodiment can use the externally generated first clock signal (CLK_src), which is external to the source video signal  102 , to receive the source pixel data  109 . In addition, the embodiment could also use the internally contained or accompanied data valid signal (DATA_valid), which is internal to the source video signal  102 , to receive the source pixel data  109 . Both signals would work well pursuant to the spirit of the present invention. 
   With the example and explanations above, the features and spirits of the invention will be hopefully well described. Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teaching of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.