Abstract:
An AC-to-DC power converter controller reconstructs the output voltage of the power converter without a sample-and-hold circuit or an opto-coupler. The controller includes an accumulation module for accumulating a difference value obtained by subtracting a first representation of an output voltage of the power converter corresponding to a first sampling timing from the output voltage value sampled at a second sampling timing subsequent to the first sampling timing to obtain a second representation of the output voltage of the power converter corresponding to the second sampling timing. The accumulation module may set the second representation of the output voltage to a predetermined maximum value if the output voltage value sampled at the second sampling timing exceeds the predetermined maximum value, or to a predetermined minimum value if the output voltage value sampled at the second sampling timing is less than the predetermined minimum value.

Description:
TECHNICAL FIELD 
     The present invention relates generally to a power converter, and more specifically, to reconstructing the output voltage of a power converter. 
     BACKGROUND OF THE INVENTION 
     Power converters need to detect or reconstruct their output voltage in order to regulate the output voltage to a desired voltage. Power converters need to reconstruct the output voltage and keep it stable for during the switching cycle in order to regulate the output voltage to the desired voltage. Conventional power converters typically reconstruct the output voltage by way of an analog feedback loop using an opto-coupler or a sample-and-hold circuit. 
       FIG. 1  is a diagram illustrating a conventional power converter that measures the output voltage using an opto-coupler  102 . The power converter senses the output voltage Vout via a diode  114  from the secondary winding of the transformer  112 . The sensed output voltage Vout is detected on the primary side of the transformer  112  through an opto-coupler  102  which optically couples the output voltage Vout to the primary side but maintains electrical isolation between the secondary side and the primary side of the transformer  112 . The coupled signal  103  is passed through a signal-conditioning module  104 . The signal-conditioning module  104  is a combination of a filter with a gain stage to generate a usable scaled voltage signal that represents the value of the sensed output voltage Vout, which is the control voltage Vc. The control voltage Vc is compared to a set voltage in an error amplifier  106 , and the amplified error signal  107  is input to the gate drive logic  108 . The gate drive logic  108  controls when the switch  110  is turned on or off, by generating turn−on timings (t ON ) and turn−off timings (t OFF ) for the switch  110  to regulate the output voltage Vout to the desired voltage. 
       FIG. 2  is a diagram illustrating a conventional power converter that measures the output voltage using a sample and hold circuit  204 . The power converter senses the feedback voltage FB, which is a scaled down version of the output voltage Vout at the secondary winding side of the transformer  214 , using an auxiliary winding  220 . The feedback voltage FB is sampled from the auxiliary winding  220  at a certain sampling timing. However, because the feedback voltage FB does not remain constant after it is sampled, there is a need for a mechanism to retain the value of the feedback voltage FB until the next sampling timing in order to use the feedback voltage FB to regulate the power converter to a desired voltage. Thus, the feedback voltage FB is input to an amplifier  202  and then through a signal conditioning and sample-and-hold circuit  204  to generate a control voltage Vc. The sample-and-hold circuit  204  holds the value of the feedback voltage FB sampled at the sampling timing at the detected value until the next sampling timing. The held signal  205  is amplified by another amplifier  206  to generate the control voltage Vc. The control voltage Vc is compared to a set voltage in an error amplifier  208 , and the amplified error signal output from the error amplifier  208  is input to the gate drive logic  210 . The gate drive logic  210  controls when the switch  212  is turned on or off, by generating turn−on timings (t ON ) and turn−off timings (t OFF ) for the switch  212  to regulate the output voltage Vout to the desired voltage. 
     However, as shown in  FIGS. 1 and 2 , conventional power converters use additional components such as opto-couplers or sample-and-hold circuits to measure the output voltage of the power converter while isolating the secondary side of the transformer from the primary side of the transformer in the power converter. Using opto-couplers or sample-and-hold circuits have disadvantages. For example, opto-couplers have an inaccurate transfer ratio resulting in error in the measurement, and they are bandwidth-limited. Sample-and-hold circuits have a disadvantage of capacitive leakage, which means that the error in the sample-and-hold circuit becomes greater as the sampling period becomes longer. 
     Therefore, there is a need for a power converter that can reconstruct its output voltage without using additional components such as opto-couplers or sample-and-hold circuits. 
     SUMMARY OF INVENTION 
     The present invention provides an AC-to-DC power converter, its controller, and a method that can reconstruct the output voltage of the AC-to-DC power converter without a sample-and-hold circuit or an opto-coupler. The AC-to-DC power converter generally includes a switch that electrically couples or decouples a load to or from a power source, and a switch controller coupled to the switch for controlling the on-times and off-times of the switch. 
     The switch controller includes an accumulation module for accumulating a difference value obtained by subtracting a first representation of an output voltage of the power converter corresponding to a first sampling timing from an output voltage value sampled at a second sampling timing subsequent to the first sampling timing to obtain a second representation of the output voltage of the power converter corresponding to the second sampling timing. A differencer may be provided in the switch controller to obtain the difference value. 
     In one embodiment, the accumulation module sets the second representation of the output voltage to a predetermined maximum value if the output voltage value sampled at the second sampling timing exceeds the predetermined maximum value. In another embodiment, the accumulation module sets the second representation of the output voltage to a predetermined minimum value if the output voltage value sampled at the second sampling timing is less than the predetermined minimum value. 
     In another embodiment of the present invention, the controller comprises a comparator and an accumulation module. The comparator includes a negative terminal coupled to a first representation of an output voltage of the power converter corresponding to a first sampling timing and a positive terminal coupled to an output voltage value sampled at a second sampling timing subsequent to the first sampling timing. The comparator compares the values on the positive and negative terminals, and outputs a positive value (typically, +1 or some other positive value) if the output voltage value sampled at the second sampling timing is greater than the first representation of the output voltage of the power converter corresponding to the first sampling timing or a negative value (typically, −1 or some other negative value) if the output voltage value sampled at the second sampling timing is less than the first representation of the output voltage of the power converter corresponding to the first sampling timing. The accumulation module accumulates the positive value or the negative value output from the comparator to obtain a second representation of the output voltage of the power converter corresponding to a second sampling timing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. 
         FIG. 1  is a diagram illustrating a conventional power converter that measures the output voltage using an opto-coupler. 
         FIG. 2  is a diagram illustrating a conventional power converter that measures the output voltage using a sample-and-hold circuit. 
         FIG. 3  is a diagram illustrating an AC-DC power converter according to one embodiment of the present invention. 
         FIG. 4  is a diagram illustrating the cycles in which the switch in the power converter is controlled by the switch controller and the waveforms of the signal VSENSE during such switching cycles, according to one embodiment of the present invention. 
         FIG. 5  is a block diagram illustrating the switch controller according to one embodiment of the present invention. 
         FIG. 6  is a flowchart illustrating a method of reconstructing the output voltage of the power converter, according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The embodiments of the present invention will be described below with reference to the accompanying drawings. Like reference numerals are used for like elements in the accompanying drawings. 
       FIG. 3  is a diagram illustrating an AC-DC power converter according to one embodiment of the present invention. The power converter of  FIG. 1  is a flyback converter with primary side sensing of the feedback signals. However, it should be noted that the present invention is not limited to a flyback converter and that it can be applied to a power converter of any topology. The power converter includes, among other components, a bridge rectifier BR, a transformer T 1 , a switch Q 1 , an output rectifier diode D 5 , output filter capacitor C 5 , and a controller  300 . 
     Referring to  FIG. 3 , the rectifier BR receives an input AC voltage and converts it into a fill-wave rectified voltage for transfer to the output V-OUT. The controller  300  controls the opening and closing of the switch Q 1  using its output control signal OUTPUT. When the switch Q 1  is turned on, energy is stored in the primary side windings of the transformer T 1  because the diode D 5  is reverse biased. When the switch Q 1  is turned off, the energy stored in the primary windings of the transformer T 1  is released to the secondary side of the transformer T 1  because the diode D 5  becomes forward biased. By controlling the period of time during which the switch Q 1  is on or off, the power converter can control the amount of power delivered to the output. 
     The controller  300  receives various input parameters for use in controlling the switch Q 1 . The controller  300  receives a Vcc (supply voltage) via the startup resistor R 8 , a divided-down version (V SENSE ) of the reflected secondary voltage on the auxiliary windings of the transformer T 1 , a reference voltage V REG  of the controller  300 , a zero voltage switching voltage Vzvs, an input voltage V IN  which is a scaled version of V BULK , the primary current sense voltage I SENSE  sensing the current flowing through switch Q 1  in terms of a voltage across the network of resistors R 4 , R 5 , and R 6 , and Power Ground (PGND), and generates a control signal OUTPUT coupled to the switch Q 1  for controlling the on-times and off-times of the switch Q 1 . The diode D 5  rectifies the output voltage on the secondary windings of the transformer T 1  and the capacitor C 5  filters the output voltage signal on the secondary windings of the transformer T 1  for outputting as V-OUT. 
       FIG. 4  is a diagram illustrating the cycles in which the switch Q 1  in the power converter is controlled by the controller  300  and the waveforms of the signal V SENSE  during such switching cycles, according to one embodiment of the present invention. Referring to  FIG. 4 , the switch Q 1  is sometimes turned on primarily for the purpose of delivering energy to the load (power cycle), although primary side sensing is still carried out during the power cycle. During the power cycle, the power converter is typically operated in critical discontinuous conduction mode to deliver as much power to the load as possible. At other times, the switch Q 1  is turned on primarily for the purpose of primary-side sensing of the output voltage (sense cycle), although some power is still delivered to the load during the sense cycle. During the sense cycle, the power converter is typically operated in discontinuous conduction mode to deliver less power to the load. In one embodiment, the controller  300  generates control signals OUT to control the switch Q 1  according to the power cycles and sense cycles depicted in  FIG. 4 . 
     As shown in  FIG. 4 , V SENSE  is sampled at points (t n , t n+1 , t n+2 , t n+3 ) near the end of the OFF period of each power cycle or sense cycle and is compared to the threshold voltage V SENSE-THRESHOLD . If the sampled value of V SENSE  is larger than V SENSE-THRESHOLD , the next cycle is controlled by the controller  300  to be a sense cycle. If the sampled value of V SENSE  is smaller than V SENSE-THRESHOLD , the next cycle is controlled by the controller  300  to be a power cycle. 
     As can be seen from  FIG. 4 , the value of V SENSE , which is a scaled down value of the output voltage V-OUT, changes over timing during each cycle (n, n+1, n+2, and n+3). Thus, the power converter samples the values of V SENSE  at the sampling timings (t n , t n+1 , t n+2 , t n+3 ) to obtain a representation of the output voltage V-OUT of the power converter at such sampling timings. However, the power converter needs to have a stable value of V SENSE  during the entire cycle (n, n+1, n+2, and n+3) in order to regulate the output voltage V-OUT. Therefore, the controller  300  of the present invention uses an accumulator to obtain a stable value of the V SENSE  during the each of the switching cycles, as will be explained in more detail with reference to  FIG. 5 . 
       FIG. 5  is a block diagram illustrating the switch controller  300  according to one embodiment of the present invention. The controller  300  includes, among other components, an accumulator  502 , comparators  510 ,  514 ,  516 , and a digital-to-analog (D/A) converter  506 . As will be clear to one of ordinary skill in the art, there are other components in the switch controller  300 , for example, to generate the on-timings (t ON ) and the off-timings (t OFF ) for the switch Q 1 , however they are not directly related to the subject matter of the present invention and are omitted from  FIG. 5 . In addition, other input/output signals to or from the switch controller  300  are also omitted from  FIG. 5  to the extent that they are not directly related to the subject matter of the present invention. 
     The accumulator  502  accumulates the differences between V SENSE  sampled at the current sampling timing and the representation of V SENSE  corresponding to the previous sampling timings to obtain the current representation of V SENSE  at the current sampling timing. Thus, the accumulator  502  executes the following accumulation function:
 
 S ( n )= S ( n− 1)+Δ S ( n ),
 
where S(n) is the sum corresponding to the current sampling timing (cycle) representative of the value of V SENSE  at the current sampling timing (t n ), S(n−1) is the sum corresponding to the preceding sampling timing (cycle) representative of the value of V SENSE  at the preceding sampling timing (t n−1 ), and ΔS(n) is the difference between V SENSE  and S(n−1), i.e., ΔS(n)=V SENSE −S(n−1). Thus, S(n)=S(n−1)+ΔS(n)=S(n−1)+V SENSE −S(n−1)=V SENSE . Thus, the accumulator  502  provides S(n), i.e., a digital representation of V SENSE  at the current sampling timing (t n ) without any sample-and-hold circuitry. Since S(n) is obtained as a digital value, it is also compatible with the remaining components (not shown) of the switch controller  300  that digitally generate the on-timings (t ON ) and off-timings (t OFF ) for the switch Q 1  to regulate the output voltage V-OUT of the power converter. The accumulator  502  is clocked by the sampling timing signals (t n ). The preceding sampling timing (t n−1 ) may immediately precede the current sampling timing (t n ) or precede the current sampling timing (t n ) by two or more cycles.
 
     The D/A converter  506  receives S(n−1) corresponding to the preceding sampling timing (t n−1 ) as a digital value  504  and converts it to an analog value  507  corresponding to S(n−1). The analog value  507  of S(n−1) is compared to V SENSE  in the comparator  510 . 
     In one embodiment, the comparator  510  is a digital differencer that compares the magnitudes of the values of V SENSE  to S(n−1) and outputs a digital value  512  representative of the difference between the two values, i.e., ΔS(n)=V SENSE −S(n−1). In another embodiment, the comparator  510  is a binary comparator that merely generates +1 (or some other positive value) if V SENSE  is larger than S(n−1) or −1 (or some other negative value) if V SENSE  is less than S(n−1) as its output  512 . 
     The sampling period Δt is the difference in time between two successive sampling timings, i.e., Δt=t n −t n−1 . In one embodiment, the sampling timings are regularly spaced such that the sampling period Δt is uniform for every switching cycle (n, n+1, n+2 . . . ). However, in other embodiments, the sampling timings need not be regularly spaced and Δt does not have to be uniform for every switching cycle. 
     In one embodiment, the sampling period Δt is set such that the sampling frequency (1/Δt) exceeds at least twice the frequency of V SENSE  (to satisfy the Nyquist sampling theorem and generally avoid aliasing), regardless of whether the sampling period Δt is the uniform for every switching cycle. However, even with such sampling frequency (1/Δt) exceeding twice the frequency of V SENSE , it is still possible for aliasing to occur for periodic signals whose frequency is approximately the same as the sampling frequency (1/Δt). 
     Therefore, in another embodiment, the sampling frequency (1/Δt) is set such that the sampling frequency (1/Δt) is much higher than the frequency of V SENSE  in order to avoid under-sampling. For example, the sampling frequency (1/Δt) is set at least 10 times higher than the frequency of V SENSE . If the sampling period Δt is not uniform, then the sampling frequency (1/Δt) is set such that the minimum of the sampling frequencies (1/Δt) is much higher than the frequency of V SENSE  in order to avoid under-sampling. For example, the minimum of the sampling frequency (1/Δt) is set at least 10 times higher than the frequency of V SENSE . 
     In another embodiment, the switch controller  300  is also capable of detecting excessively high or low values of V SENSE  that are out of range of the switch controller  300 . Thus, the comparator  516  compares the value of V SENSE  at the sampling timing (t n ) to a predetermined maximum value for V SENSE  (V SENSE,max ) and generates a FlagMax signal  520  of “  1 ” when the value of V SENSE  at the sampling timing (t n ) exceeds the predetermined maximum value for V SENSE  (V SENSE,max ). Otherwise, the comparator  516  generates a FlagMax signal  520  of “0.” The comparator  514  compares the value of V SENSE  at the sampling timing (t n ) to a predetermined minimum value for V SENSE  (V SENSE,min ) and generates a FlagMin signal  518  of “1” when the value of V SENSE  at the sampling timing (t n ) is less than the predetermined minimum value for V SENSE  (V SENSE,min ). Otherwise, the comparator  514  generates a FlagMin signal  518  of “0.” The accumulator  502  includes logic (not shown) that sets S(n) for the sampling timing (t n ) to V SENSE,max  when FlagMax  520  is “1” or to V SENSE,min  when FlagMin  518  is “1.” 
       FIG. 6  is a flowchart illustrating a method of reconstructing the output voltage of the power converter, according to one embodiment of the present invention. In one embodiment, the process described in  FIG. 6  occurs in the switch controller  300 . In another embodiment, the process described in  FIG. 6  may occur in a state machine forming at least part of the switch controller  300 . 
     As the process starts  602 , the switch controller  300  receives  604  the V SENSE  sample sampled at the current sampling timing (t n ). Then, the switch controller  300  determines  606  whether the sampled V SENSE  value exceeds a predetermined maximum value, V SENSE , max. If the sampled V SENSE  value exceeds the predetermined maximum value, V SENSE , max, the switch controller sets  608  S(n) to be equal to V SENSE , max. Then, the switch controller  300  determines  610  whether the sampled V SENSE  value is less than a predetermined minimum value, V SENSE, min . If the sampled V SENSE  value is less than the predetermined minimum value, V SENSE, min , then the switch controller sets  612  S(n) to be equal to V SENSE,min . 
     Finally, the switch controller accumulates  614  the differences between the V SENSE  value sampled at the current sampling timing and the value representative of V SENSE  corresponding to the preceding sampling timing, by performing S(n)=S(n−1)+ΔS(n), where S(n) is the sum corresponding to the current sampling timing (cycle) representative of the value of V SENSE  at the current sampling timing (t n ), S(n−1) is the sum corresponding to the preceding sampling timing (cycle) representative of the value of V SENSE  at the preceding sampling timing (t n−1 ), and ΔS(n) is the difference between the sampled V SENSE  value and S(n−1), i.e., ΔS(n)=V SENSE −S(n−1). Then, the process returns  604  to receive the sampled V SENSE  value corresponding to the next sampling timing. 
     Although the present invention has been described above with respect to several embodiments, various modifications can be made within the scope of the present invention. For example, the present invention is not limited to any topology of AC-to-DC power converter, and can be used with flyback type AC-to-DC power converters, boost type AC-to-DC power converters, and the like. The accumulator  502  described herein may be implemented by digital logic circuits, state machines, or other types of circuitry to the extent that it can perform the accumulation functions as described herein. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.