Abstract:
An embodiment of a crystal oscillator circuit includes leakage-current compensation, transconductance enhancement, or both leakage-current compensation and transconductance enhancement. Such an oscillator circuit may draw a reduced operating current relative to a conventional oscillator circuit, and thus may be suitable for battery or other low-power applications.

Description:
PRIORITY CLAIM 
     The instant application claims priority to Indian Patent Application No. 3122/DEL/2010, filed Dec. 28, 2010, which application is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     An embodiment relates broadly to a crystal oscillator circuit, to a method of operating a crystal oscillator core, a digital integrated circuit, and a communication device. 
     BACKGROUND 
     Crystal oscillators are one of the most important and widely used circuits for precise clock-generation in integrated circuits. Single-transistor-based Pierce and Collpitt oscillators are typically used in the industry for the oscillator core. There is a need to design ultra-low-power crystal oscillators, e.g., for applications in battery-powered biomedical devices and real-time-clock (RTC) chip sets. Such devices typically should be capable of being used for a relatively long period of time without a need of changing the battery. Therefore, such applications favor the design of crystal oscillator circuits which consume less power and help increase the battery life. 
     With shrinking CMOS technologies, leakage currents are becoming increasingly more important for robust analog designs in CMOS technologies. In the case of crystal oscillators, leakage current at the crystal input nodes, which may arise due to the Electrostatic Discharge (ESD) protection devices at these nodes, may directly alter the drain current of the transistor and, therefore, the operating transconductance and the achieved negative resistance may be affected. Therefore, even if low-power crystal oscillators are made such that the leakage current at the crystal input nodes is comparable in magnitude and opposite in direction to the bias current, the circuit still might fail to produce oscillations due to insufficient negative resistance. This is because the operating transconductance typically cannot be greater than the critical transconductance that is due to the reduced device current. Thus, a circuit designer typically takes into account both transconductance enhancement, so that the operating transconductance (typically at least three times greater than critical transconductance) is achieved with reduced bias current, and leakage-current (at the crystal nodes) compensation for robust circuit operation. 
     The design of conventional single-transistor three-point oscillator core  100 , see  FIG. 1 , involves generation of negative resistance sufficient to overcome the crystal losses, i.e., the series resistance of the crystal. This typically involves setting the operating transconductance gm op  to be sufficiently greater than the critical transconductance (typically, as a rule of thumb, at least three times the value of the critical transconductance, i.e., gm op 3gm crit ). This typically ensures a good start-up margin and is a robustness feature to make the design work across process “corners,” i.e., process variations that may affect the operating transconductance. The critical transconductance is the minimum transconductance required for the oscillator to start and its value is given by the following equation: 
     
       
         
           
             
               
                 
                   
                     gm 
                     crit 
                   
                   = 
                   
                     
                       ω 
                       2 
                     
                     ⁢ 
                     
                       C 
                       1 
                     
                     ⁢ 
                     
                       C 
                       2 
                     
                     ⁢ 
                     
                       
                         
                           R 
                           m 
                         
                         ⁡ 
                         
                           ( 
                           
                             1 
                             + 
                             
                               
                                 
                                   C 
                                   0 
                                 
                                 ⁡ 
                                 
                                   ( 
                                   
                                     
                                       C 
                                       1 
                                     
                                     + 
                                     
                                       C 
                                       2 
                                     
                                   
                                   ) 
                                 
                               
                               
                                 
                                   C 
                                   1 
                                 
                                 ⁢ 
                                 
                                   C 
                                   2 
                                 
                               
                             
                           
                           ) 
                         
                       
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     where, ω is the angular frequency at which it is desired that the oscillator operate, R m  is the motional resistance of the crystal (not shown in  FIG. 1 ), Co is the shunt capacitance (not shown in  FIG. 1 ) of the crystal, and C 1  and C 2  (neither shown in  FIG. 1 ) are the load capacitances coupled between the node XTALIN and ground and the node XTALOUT and ground, respectively. For example, a typical 32 kHz crystal has Rm≈50 kΩ, Co≈4 pF (this value already includes the approximately 2 pF parasitic capacitance between the crystal nodes), and C 1 ≈C 2 ≈30 pF such that the transconductance values are gm crit ≈3 μA/V and gm op  is approximately equal to or greater than 9 μA/V to achieve a magnitude of negative resistance of more than 150 kΩ. 
     An inverter-type oscillator core  200 , see  FIG. 2 , has been proposed which uses two stacked transconductance devices (one NMOS and one PMOS device). Under the condition that the transconductance of the NMOS and PMOS device are approximately the same (i.e., gm p ≈gm N ), for a given bias current I B  the proposed inverter-type oscillator core provides approximately twice the transconductance as compared to a conventional Pierce Oscillator core such as shown in  FIG. 1 . This means that to achieve the same operating transconductance, the proposed inverter-type oscillator requires about half the bias current I B  as that of a Pierce oscillator. However, the aforementioned improvement in the current consumption typically requires a node X between V DD  and the stacked transistors of the inverter-type oscillator to be virtually grounded (e.g., AC grounded). For example, such a virtual ground may be achieved by using an extra capacitor C c  such that the pole frequency f p  is given by the following equation: 
     
       
         
           
             
               
                 
                   
                     f 
                     p 
                   
                   = 
                   
                     
                       
                         
                           gm 
                           p 
                         
                         
                           2 
                           ⁢ 
                           π 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             C 
                             c 
                           
                         
                       
                       ⪡ 
                       
                         f 
                         op 
                       
                     
                     = 
                     
                       32 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       kHz 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Assuming that gm P ≈gm N ≈0.5·gm op ≈1.5·gm crit ≈4.5 μA/V, and considering that f p ≈f op /100 (i.e., the magnitude of a small signal voltage at the gate of the PMOS device is attenuated by a factor of 100), the design calls for C o ≈2.2 nF. As will be appreciated, such a capacitor is generally too big to be integrated on a die on which the other components of the oscillator, and the components of other circuits, are integrated. Thus, the use of such an inverter-type oscillator for a 32 kHz crystal oscillator may require a prohibitively large virtual-grounding capacitance value for applications in which it is desired to integrate the virtual-grounding capacitor on the same die as the other oscillator components. 
     SUMMARY 
     An embodiment includes an oscillator having a circuit architecture that may provide a higher transconductance value than a conventional oscillator for a given current while avoiding the use of a capacitor for virtual grounding a non-supply node of the oscillator. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments will be better understood from the following written description, which is given by way of example only, and in conjunction with the following drawings, in which: 
         FIG. 1  is a schematic diagram of a conventional single-transistor 3-point oscillator core. 
         FIG. 2  is a schematic diagram of a conventional inverter-type oscillator core. 
         FIG. 3  is a schematic diagram of an oscillator circuit topology according to an embodiment. 
         FIG. 4  is a schematic diagram of a corresponding CMOS implementation of the circuit topology of  FIG. 3 , according to an embodiment. 
         FIGS. 5  ( a ) and ( b ) are different-resolution plots of Re(Z) versus the transconductance of the transistor device for a conventional pierce oscillator and for an embodiment of an oscillator such as described in conjunction with  FIGS. 3 and 4 . 
         FIG. 6  is a block diagram of a system that incorporates an embodiment of a crystal oscillator circuit such as described in conjunction with  FIGS. 3-5(   b ). 
     
    
    
     DETAILED DESCRIPTION 
     In accordance with an embodiment, there is provided a crystal oscillator circuit comprising a three-point oscillator core having crystal nodes; and a current feedback circuit coupled between the crystal nodes of the three-point oscillator core, the current feedback circuit having a gain factor that is configured such that in operation at least one of a leakage current at the crystal nodes is compensated, and a transconductance of the crystal oscillator circuit is enhanced. 
     The three-point oscillator core may include a first transistor device; and the current feedback circuit may include a second transistor device; and wherein the first transistor device and the second transistor device may define a current mirror. 
     The current mirror may have a mirror ratio of 1:α, with a α≈1. 
     The current feedback circuit may further comprise an inverting current amplifier circuit providing the gain factor. 
     The inverting current amplifier may be designed to sink/source a current of N/(N+1) times the leakage current, where N is the gain factor. 
     The crystal oscillator circuit may further comprise a bias-current-generator circuit coupled to the three-point oscillator core and the current-feedback circuit. 
     The leakage current may be compensated 1/(N+1) times, where N is the gain factor. 
     The current-feedback circuit may enhance a transconductance of the crystal oscillator circuit based on the gain factor. 
     A desired negative resistance may be achievable with the transconductance of the first transistor device of the three-point oscillator core (1+N)−times less compared to a conventional Pierce oscillator, where N is the gain factor. 
     A desired negative resistance may be achievable with the device bias current of the first transistor device of the three-point oscillator core (1+N)−times less compared to a conventional Pierce oscillator, where N is the gain factor. 
     The transconductance may be enhanced (N+1) times, where N is the gain factor. 
     A total power consumption of the crystal oscillator circuit may be reduced compared to a conventional Pierce oscillator for the same crystal parameters and leakage values. 
     The gain factor N may be approximately 9. 
     In accordance with an embodiment, there is provided a method of operating a crystal oscillator circuit, the method comprising of providing a current-feedback circuit coupled between crystal nodes of a three-point oscillator core of the crystal oscillator circuit, and configuring a gain factor of the current-feedback circuit such that at least one of a leakage current at the crystal nodes is compensated, and a transconductance of the crystal oscillator circuit is enhanced. 
     An embodiment, which is described below, provides a transconductance-enhanced (gm-boosted) and leakagecurrent compensated oscillator core enabling an ultra-low power crystal-oscillator design. By means of the gm-boosting technique, lower bias-current values may be used to provide the same operating transconductance and negative resistance as compared to a conventional single-transistor Collpitts or Pierce oscillator. Such an ultra-low-power crystal oscillator may be used in, e.g., battery-powered devices where long battery life may be a key requirement. 
     The circuit topology  300  of an embodiment is shown in  FIG. 3 , and a corresponding CMOS implementation  400  of the topology  300  is shown in  FIG. 4 . 
     Referring to  FIG. 3 , the crystal (not shown in  FIG. 3 ) is coupled between the XTALIN and XTALOUT nodes, and load capacitances C 1  and C 2  (also not shown in  FIG. 3 ) are coupled between XTALIN and ground and XTALOUT and ground, respectively. A Pierce Oscillator core  302  is indicated within dotted lines, with transistor pair M1−M2 acting as a current mirror (in this embodiment with the mirror ratio α=1). It is noted that in other embodiments, M1 and M2 may each be in the form of multiple-transistor devices. A current-mode active building block, here a current-flipper  304 , is provided. A characterizing equation for an ideal inverting current-amplifier (herein referred to as the current flipper  304 ) is:
 
 I   out   =−NI   in   (3)
 
where N is the current-gain factor from input to output of the and the directions of the currents are in accordance with the network convention that all currents are flowing into the nodes. In an embodiment, the current flipper  304  and the current mirror form part of a current feedback circuit  305  of the circuit topology  300 . Note that the current transfer function in equation (3) indicates the DC gain, but the gain for the actual circuit will be bandwidth limited (due to parasitic capacitances of the MOS device). But the 3 dB pole-frequency of the current-flipper  304  may be made significantly greater than (e.g., ten or more times greater than) the operating frequency f op  (i.e., in this case significantly greater than 32 kHz).
 
     Due to the current-feedback action in an embodiment, leakage currents arising at the XTALIN (A) and/or XTALOUT (ZO) nodes (due to the presence of, e.g., ESD-protection structures, not shown, present at both nodes) may be reduced by a factor of (1+N). For a conventional Pierce oscillator, a leakage current of I L  arising at the A or ZO nodes changes the device current (through the transistor M1) to I B ±I L  (note that both increase and decrease of the bias current is possible). Reduction of the device current due to leakage mandates the addition of a pessimistic leakage floor onto the device current during design, so that even in the worst case the device current is sufficient to provide the required operating transconductance. In an embodiment, the modified device current (drain current of M1) due to the leakage current at either the A or ZO nodes is sensed by means of the current mirror M1−M2, and the difference current (the difference between I B  and the leakage current I L ) acts as the input to the current flipper  304 . The current-feedback action thus makes the device current through M1 approximately equal to I B ±I L /(1+N), which is closer to I B  than I B ±I L  for the circuit without feedback. This can be derived from the following equation for I M1  DC:
 
 I   M1   =±I   L   +I   B   −N·α· ( I   M1   −I   B )  (4)
 
where α=1 and the bias current for M1 is approximately the same as the bias current for M2.
 
     The small-signal analysis of an embodiment of the circuit  400  of  FIG. 4  may be performed similarly to any other three-point oscillator analysis. This involves finding the small-signal impedance of the active circuit that the crystal “sees.” Considering the small-signal model of the circuit  400  as shown in  FIG. 4 , routine circuit analysis yields the following equation for the small-signal impedance: 
                       Z   in     ⁡     (   ω   )       =           -     (     1   +   N     )       ⁢   gm         ω   2     ⁢     C   1     ⁢     C   2         +       -     j   ⁡     (       C   1     +     C   2       )           ω   ⁢           ⁢     C   1     ⁢     C   2                   (   5   )               
which represents a series combination of a frequency-dependent negative resistance (FDNR) and an effective load capacitance. The numerator of the FDNR indicates that the device transconductance (gm of M1) is multiplied by the factor (1+N) and the effective transconductance of this modified oscillator core is (1+N)gm M1 . Thus, the operating transconductance gm op  (to make the negative resistance e.g., three times that of the crystal series resistance) may be achieved by making the device transconductance of M1 (1+N)−times less compared to a conventional Pierce oscillator (since (1+N)gm M1 =gm op ).
 
     For the same over-drive voltage of device M1 as that of a conventional Pierce oscillator, this translates to a reduction in bias current of M1 by a factor of (1+N). Considering the shunt capacitance of the crystal (Co) in parallel with Z in , the impedance that the crystal R-L-C series arm sees is a parallel combination of Z in  and Co, i.e., Z=Z in ∥(1/sCo). The plot  500  of Re(Z) of a conventional Pierce oscillator (i.e., N=0) and the plot  502  of an embodiment of the circuits  300  and  400  of  FIGS. 3 and 4  using N=9 versus the transconductance of device M1 (gm M1 ) is shown in  FIG. 5(   a ) and ( b ). It is evident from  FIG. 5(   a ) that to achieve a desired negative resistance of 150 kΩ (magnitude), the transconductance of M1 required for an embodiment of the circuit  300 / 400  is 0.9 μA/V as compared to 9 μA/V (which is (1+N) times higher) for a conventional Pierce oscillator. 
     Furthermore, for a minimum negative resistance of 175 kΩ (magnitude), the transconductance of M1 an embodiment with N=9 is about 1.05 μA/V as compared to 10.5 μA/V for a conventional Pierce oscillator. The increase in the magnitude of the negative resistance with increase in transconductance occurs up to a particular value of gm, termed as the “optimum transconductance” (gm optm ). Beyond this value, negative resistance falls with increase in transconductance, as shown in  FIG. 5(   b ). As with a conventional Pierce oscillator, the effective operating transconductance of the oscillator core in an embodiment, i.e., (1+N)gm M1 , is chosen to be greater than approximately 3·gm crit  but less than approximately gm optm . It is also noted from  FIGS. 5(   a ) and ( b ) that the maximum negative resistance (approximately −490 kΩ) occurs in an embodiment with N=9 at a transconductance of M1, gm M1 , of about 5.7 μA/V, as compared to the 57 μA/V for a conventional Pierce oscillator without current feedback. 
     In order to illustrate the current saving that may accrue from an embodiment, a comparison is made to some typical numbers from an existing 32 kHZ crystal oscillator in HCMOS9A technology, taking the standard 32 kHz crystal (most widely used) model parameters, namely, R m =50 kΩ, C o =4 pF. With a load capacitance of C 1 =C 2 =30 pF, to achieve a magnitude of negative resistance of more than 175 kΩ requires about 600 nA (minimum) of biasing current I B  (for the device to be working in the saturation region with over-drive voltage of about 30 mV)—this corresponds to an effective operating transconductance requirement of about 10.5 μA/V. If a leakage floor estimate of ±50 nA is assumed at both the crystal nodes A and ZO, an additional 100 nA is added to the device current, making it 700 nA. This is the minimum current required (at slowest process corner and temperature of −40° C.) to still achieve the required transconductance in the worst case. Since the bias-current generator  402  of  FIG. 4  (for example a sub-threshold proportional-to-absolute-emperature (PTAT) current generator) has a process temperature spread of approximately 1:2, the bias current of 700 nA becomes 1.4 μA (for the fastest corner and temperature of 125° C.). This increase in current improves the operating transconductance and thereby also the negative resistance and oscillator start-up margin. 
     Considering the same aforementioned crystal parameters and leakage values of ±50 nA for a current-flipper gain of nine (i.e., N=9), in an embodiment the bias current I B  for the M1 device may be reduced to approximately 70 nA. The current-flipper  404  is biased with a current I CF  of approximately 180 nA, a value sufficient to compensate for compensating ±50 nA, at both the crystal nodes A and ZO. It is noted that the current-flipper  304 , 404  may be designed to appropriately sink/source a current of I L ·N/(1+N), where I L  is the leakage current arising at either of the crystal nodes A and ZO. Thus, the minimum current consumption for an embodiment becomes 70·2 nA (bias currents for M1 and M2)+180 nA≈320 nA, as opposed to an approximately 700 nA current requirement for a conventional Pierce oscillator. This corresponds to a 55% current reduction. 
     It is noted that an embodiment is not limited to processes having higher leakage, but may also be suited for negligibly lower-leakage processes. In such a case, the functionality of the circuit in an embodiment relates to gm-boosting only. Without any leakage considerations, an embodiment of the oscillator  300 ,  400  requires a bias current of 60·2 nA (bias current for M1 and M2)+180 nA (same bias current for the current-flipper as discussed above). This corresponds to a current consumption of about 300 nA, as opposed to 600 nA minimum current requirement for a conventional Pierce oscillator. 
     Still referring to  FIG. 3 , for the feedback circuit  305  to compensate for only leakage current I L  into the drain node of the transistor M1, the coupling between the amplifier  302  and the feedback circuit  305  (e.g., the coupling between M1 and M2) may be designed to pass only lower-frequencies. 
     Conversely, for the feedback circuit  305  to compensate for only the gm of the amplifier  302 , the coupling between the amplifier  302  and the feedback circuit  305  (e.g., the coupling between M1 and M2) may be designed to pass only higher-frequencies. 
     Furthermore, although described as being the same, the bias current I B  to M1 and the bias current to M2 may be different. 
     Referring to  FIG. 4 , an embodiment of the oscillator circuit  400  may also include a start-up circuit to force the oscillator circuit to a stable operating point at which it oscillates at a desired non-zero frequency; this prevents the circuit from operating at a stable operating point at which the circuit effectively oscillates at a zero frequency or at another undesirable frequency. 
     Moreover, although described as being coupled to a crystal, the circuits  300  and  400  may be coupled to a microelectromechanical (MEMS) oscillating element. 
       FIG. 6  is a block diagram illustrating a system  600 , which incorporates a crystal oscillator circuit  610  according to an embodiment, for example an embodiment of the circuit  300  or the circuit  400  of  FIGS. 3 and 4 . Such a system  600  may be, for example, a wristwatch, clock, radio, computer, cell phone, smart phone, test and measurement equipment such as a counter, signal generator, oscilloscope, a control board for a battery-powered biomedical device, or a real-time-clock (RTC) chip set. Here, the crystal oscillator circuit  610  may be part of a first integrated circuit  612 , which may be coupled to a second integrated circuit  614 , where the first and second integrated circuits may be disposed on a same die or on different dies. Examples of the first and second integrated circuits  612  and  614  include a controller such as a processor, a power source, memory devices, etc. (not shown). In an embodiment, the crystal oscillator circuit  610  may be used to provide a stable clock signal for one or both of the circuits  612  and  614 , or may be used to generate stable frequencies for a communication system  600  such as a smart phone. 
     It will be appreciated that an embodiment is not limited to the inverting current amplifier being a current flipper as described above, but other current-feedback circuit implementations may be used. Furthermore, a current mirror in an embodiment may employ other values for the mirror parameter α. Also, an embodiment is not limited to N=9 as described above. In addition, an embodiment of a crystal oscillator circuit may be employed with a multi-transistor crystal-oscillator cores. 
     From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.