Abstract:
A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants&#39; diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement. Mixed epitaxial layer growth materials inducing tensile or compressive gate stresses can be advantageously used with the invention to further improve device characteristics.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 62/200,533 filed Aug. 3, 2015. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention generally relates to the structure and manufacturing of metal-oxide semiconductor field effect transistors (MOSFETs), and more particularly to MOSFETs manufactured for reproducibility of threshold voltages among otherwise identical transistors and for improvement of transistor performance. Further, this invention addresses random doping induced channel length modulation concerns in transistors manufactured with dimensions finer than 40 nm. 
         [0004]    2. Prior Art 
         [0005]    Integrated circuits (ICs) have found applications in all areas of human life, like home, health and communications to transportation. The device densities have been doubling every 18 to 24 months and device sizes have been scaling downward to achieve these densities. Currently the most prevalent device critical dimensions for typical silicon designs are 35 nm going down to 28 nm and the most advanced device critical dimensions are at 14 nm and 10 nm. At the finest scales, FinFET and SOI devices are displacing the more economical planar bulk CMOS devices. 
         [0006]    As dimensions of metal-oxide semiconductor (MOS) field effect transistors (FETs) become smaller, the depletion regions of the transistors occupy a much smaller volume. Smaller volume implies a smaller absolute quantity of doping atoms, and the smaller quantity of dopant atoms is subject to increased random, statistical variations. Ultimately, key device properties subject to variations arising from the randomness of the exact positions of discrete dopants in and near the channel. Such variations, particularly random variations in threshold voltage (aVT), are impacting the functionality of all low-power circuits, especially static random access memories (SRAM). Random variations in threshold voltage increase both the minimum voltage required for reliable SRAM operation and the leakage current. Both effects have an adverse impact on the power consumption at a given level of performance. 
         [0007]    Random threshold variations aVT in conventional planar MOS transistors are caused by several factors. The dominant factors are: (i) random dopant fluctuations (RDF) in the well and in the pocket implant regions underneath the gate, which, among other things, cause variations in depletion layer thickness; (ii) line edge roughness (LER) which causes random variations in the length of the gate electrode resulting from random variations in profile of the etched gate; (iii) metal gate granularity (MGG) in high-k metal gate technologies which causes random variations in the local work function due to the grain structure of the gate material; (iv) poly-silicon granularity in poly-silicon gate technology, which causes potential pinning at grain boundaries and corresponding local threshold voltage variation; and (v) the randomness in the effective channel length, arising from statistical variations in the position of the junction that separates the channel from either the source or the drain extensions. This last effect has significant roots in the ion implantation processes used to form transistor sources and drains. Both the scattering of discrete dopants associated with implantation and the heat treatments required for activation contribute to uncertainties in the final positions of channel-length defining junctions. 
         [0008]      FIGS. 1A and 1B  show a typical approach to creating source and drain structures in a planar MOS transistor.  FIG. 1A  shows a cross-section of a substrate with well implants  110 , and that has a gate oxide  120  grown on it. Over the gate oxide there is a silicon gate  130 , either polycrystalline or amorphous, and that gate has been oxidized to form an oxidation layer  140  subsequent to patterning.  FIG. 1A  shows an ion implantation or a sequence of implantations  151  that are used to create source and drain extensions  150 . In contemporary processes, the implant sequences for NMOS transistors include arsenic and/or phosphorous for drain extensions and boron and/or indium for pocket implants. Similarly, the implant sequences for PMOS transistors include boron, indium and/or BF 2  for drain extensions and phosphorous and/or arsenic for pocket implants. 
         [0009]      FIG. 1B  further shows a spacer  160  that has been formed by chemical vapor deposition (CVD), with or without plasma assistance, typically of silicon nitride or silicon oxide. Through the use of anisotropic plasma etching, the deposited material is removed from all surfaces parallel to the silicon wafer surface, but due to the anisotropic nature of the etch, the spacers  160  remain on the sidewalls. The spacers protect the source and drain extensions  150  during the ion implantations  171  that create the very heavily doped source and drain regions  170 . Again, single or multiple implants may be used to fabricate the transistor sources and drains. During ion implantation steps  151  and  171  the implanted region of the semiconductor, typically silicon, is made amorphous and an annealing step is needed to repair crystal damage, re-crystallize the amorphous semiconductor regions and to activate the dopants. While at least one annealing step is required, some process flows require multiple annealing steps. Rapid thermal annealing is the current norm for implants  151  and  171 , where peak temperatures can exceed 1000° C. Depending upon the process, annealing times range from microseconds to tens of seconds. The sheet resistance of the source and drain regions  170  is further reduced by reaction with deposited metallic Ti, Co or Ni to form a highly conductive layer of metal silicide  180 . These steps are followed by the formation of interlayer dielectrics (ILD), contacts, and multiple layers of interconnect in the usual process flows. 
         [0010]    At high drain bias, the implanted drain regions that extend into the semiconductor substrate, act as side gates, influencing the channel region and controlling the carriers in the channel; this is responsible for drain induced barrier lowering (DIBL) and strong short channel effects. Very high channel doping is needed to control the short channel effects in contemporary, prior art bulk CMOS technologies. The high channel doping results in very large random dopant induced threshold voltage variations which dominate the statistical threshold voltage variability in bulk MOSFETs. High channel doping also reduces the transistor conductance because impurity scattering leads to very low mobility in the channel. 
         [0011]    Even though the gate  130  and its oxide  140  act as a hard mask, the final locations of the channel defining edges of the source and drain extensions  150  are subject to localized, random variations. Some of these variations are associated with scattering of the implanted ions as they recoil from collisions with semiconductor nuclei prior to coming to rest in the silicon, and some of the variations are associated with enhanced local diffusion of the dopant ions assisted by crystalline defects created during the annealing processes. The overall effect of these uncertainties is to impose a random variation on the length of the channel. For transistors having channel lengths of less than  65  nm, the channel length affects both the threshold voltage and the current carrying capability of the transistors. Some of these effects are further increased by pocket implants used in the drain extension formation sequence  151 . The ultimate locations of the source-to-channel and drain-to channel junctions are subject to variations that are exaggerated by the local differences between two large, statistically uncertain doping densities. 
         [0012]    Statistical uncertainties are unavoidable in minute devices that depend upon substrate doping to fix their threshold voltages. These uncertainties are only exaggerated by implanted source and drain doping ions that are randomly scattered into the substrate regions near the transistor channels. 
         [0013]    A further effect of the heavy doping in traditional source and drain regions is the penetration of ions from these heavily doped sources and drains into the substrate, forming deep junctions, frequently to depths that are comparable to the designed channel lengths. The electrostatic effect of these deep junctions is to pass partial control of the threshold voltage to the drain voltage, resulting in a net reduction of the threshold voltage, increased subthreshold slope and drain induced barrier lowering (DIBL) and increased random variability. These effects work together to increase circuit leakage. 
         [0014]    The electrostatic effect is illustrated in  FIG. 1C , which shows the electric fields perpendicular to the silicon surface at the intersection of the substrate and the gate dielectric in prior art transistors. This instance is a transistor with zero volts on the gate and source and  1  volt on the drain. Note that the drain voltage induces a vertical electric field ranging up to nearly  10   6  volts/cm over a large portion of the channel region. These fields are particularly important in the channel region close to the source. 
         [0015]    Random threshold variations associated with random doping density variations have been known in the past, but their effects were not critical until the gate lengths of the devices were scaled below 65 nm. and the supply voltages were scaled to 1 volt and below. Some approaches to mitigate these effects involve the use of a very lightly doped epitaxial semiconductor layer beneath the gate. The use of very lightly doped channel regions with implanted source and drain and extensions in transistors with gate lengths below 45 nm have been found to be more prone to threshold perturbations by the uncertain locations of the tails of source/drain extension implants, some of which are related to dopant scattering. 
         [0016]    Solutions have also been proposed to mitigate the effect of channel length variation of small devices by the use of raised epitaxial source and drain regions with implantation doping in the raised epitaxial regions. These allow superior source and drain conductivity, particularly in semiconductor-on-insulator (S 01 ) devices, but these structures do not provide a solution for the variations in threshold voltage (cNT) of the devices due to doping variations. Use of selective epitaxial growth in selectively etched down extension regions have also been proposed to have shallow extensions, improving the device characteristics, but none of these directly address the threshold variation issues of the small devices. 
         [0017]    In view of the deficiencies of the prior art it would be advantageous to provide a transistor structure and a manufacturing process that reduce variations between otherwise identical transistors by improved control of the channel length, the location of the channel edge and variations in location of dopant atoms under the gate. It is further desirable to have devices with planar junctions that provide improved electrostatic control with low and uniform doping concentrations in the channel. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1A  is a schematic cross-section of a MOSFET gate with the source/drain extension implant (prior art). 
           [0019]      FIG. 1B  is a schematic cross-section of a MOSFET gate with a spacer in place and the heavy source/drain (N+ or P+) implant (prior art). 
           [0020]      FIG. 1C  is an illustration of the electric fields perpendicular to the silicon surface in a transistor realized using the prior art. 
           [0021]      FIG. 2A  is a schematic cross-section of a transistor realized in accordance with an embodiment. 
           [0022]      FIG. 2B  is an illustration of the electric fields perpendicular to the silicon surface in the transistor illustrated in  FIG. 2A . 
           [0023]      FIG. 3A  are schematic cross sections representative of substrate configurations that are consistent with embodiments. 
           [0024]      FIG. 3B  is a schematic cross section of a transistor realized in accordance with an embodiment and using a substrate with an extremely low-doped epi layer. 
           [0025]      FIG. 4A  is a schematic cross section of a conventional substrate with gate oxide and shallow trench isolation as it may be used with an embodiment. 
           [0026]      FIG. 4B  is a schematic cross section of a patterned gate and sidewall oxidation in accordance with an embodiment. 
           [0027]      FIG. 4C  is a schematic cross section of epitaxial source and drain extensions in accordance with an embodiment. 
           [0028]      FIG. 4D  is a schematic cross section of sidewall spacers adjacent the gate in accordance with an embodiment. 
           [0029]      FIG. 4E  is a schematic cross section of high-conductivity epitaxial source and drain regions in accordance with an embodiment. 
           [0030]      FIG. 4F  is a schematic cross section of a completed transistor, including salicide contact layers, interlayer dielectric and metallic contact plugs in accordance with an embodiment. 
           [0031]      FIG. 5A  is a schematic cross section of a conventional substrate with gate oxide and shallow trench isolation as it may be used with an alternative embodiment. 
           [0032]      FIG. 5B  is a schematic cross section of a conventional substrate with an oxidized sacrificial gate as it may be used with an alternative embodiment. 
           [0033]      FIG. 5C  is a schematic cross section of a conventional substrate with the addition of an epitaxial source/drain extension layer as it may be used with an alternative embodiment. 
           [0034]      FIG. 5D  is a schematic cross section of a conventional substrate with addition of spacers adjacent to the sacrificial gate as it may be used with an alternative embodiment. 
           [0035]      FIG. 5E  is a schematic cross section of a conventional substrate with the source and drain structures completed with a second epitaxial layer and salicide layers as it may be used with an alternative embodiment. 
           [0036]      FIG. 5F  is a schematic cross section of a conventional substrate with the application of a first interlayer dielectric as it may be used with an alternative embodiment. 
           [0037]      FIG. 5G  is a schematic cross section of a conventional substrate after CMP to planarize the first interlayer dielectric and expose the top of the sacrificial gate as it may be used with an alternative embodiment. 
           [0038]      FIG. 5H  is a schematic cross section of a conventional substrate showing the recess left after removing the sacrificial gate as it may be used with an alternative embodiment. 
           [0039]      FIG. 5I  is a schematic cross section of a conventional substrate with depositions of a high-K dielectric, gate metal and gate handle as it may be used with an alternative embodiment. 
           [0040]      FIG. 5J  is a schematic cross section of a nearly completed transistor in the alternative embodiment on a conventional substrate subsequent to CMP that clears excess gate-related depositions from the first interlayer dielectric. 
           [0041]      FIG. 5K  is a schematic cross section of a completed transistor in the alternative embodiment, with a second interlayer dielectric and metallic contact structures for the source, drain and gate. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0042]    Several factors impact the variations in the threshold voltage of nominally identical transistors. Among them are inevitable randomness of ionized dopants beneath the gate, variations in the effective channel length that are associated with the randomness of the scattering of source/drain extension implants (RXF), uncertainty in the activation of those ions, and the counting statistics of their intersection with pocket and well implants. These variations, important because of tiny device dimensions, are exacerbated by short channel effects. The solutions are to avoid ion implantation with its associated uncertainties in final dopant ion positions and to avoid temperatures that are high enough to further exacerbate the random final locations of active dopant ions. The described and disclosed transistor structure and process are based on using low temperature epitaxy to form source/drain structures, where low temperature typically means 650° C. or less. Further, these structures are raised with respect to the substrate, and their substrate interface is essentially coplanar with the gate oxide interface with the substrate. The region beneath the channel may be lightly doped compared with the prior art, or it may include a substantially undoped epitaxial layer. This is illustrated by  FIG. 2A , a schematic cross section of the basic transistor utilizing this construction principle. In this figure,  210  is a substrate, doped appropriately to obtain, with the gate structure, a desired threshold voltage for the transistor. The transistor is typically formed in an area isolated from devices on the die with shallow trench isolation  215 . The gate structure of the transistor consists of a gate dielectric  220 , a conducting gate electrode  230 , frequently doped polycrystalline silicon, and the gate contact  275 . The differentiating structures are epitaxial source and drain extensions  250 , and the epitaxial source and drain conductors  270 . The extensions  250  are formed of thin epitaxy, and they are separated from the gate conductor  230  by a layer of dielectric  240 , typically silicon dioxide or silicon oxy-nitride. A typical lower limit on the thickness of dielectric  240  is the thickness of the gate dielectric  220 ; an upper limit would be three times the gate dielectric  220  thickness. The more heavily doped source and drain conductors  270  are also formed by low-temperature epitaxy. They are separated from the gate conductor  230  by a dielectric spacer  260  in addition to the thin dielectric  240  on the gate sidewall. In order to minimize parasitic capacitance, the spacer  260  will be much thicker than the gate dielectric  220 , 10 to 300 times thicker. 
         [0043]    The formation of the source and drain extensions  250  and subsequent processing is done in a way to substantially prevent diffusion of dopant atoms from the extensions  250  into the substrate  210 , thereby creating substantially abrupt source and drain junctions that are aligned along the planar surface of the substrate at the interface between the substrate and the epitaxial extensions. For example, this can be accomplished by forming the drain extensions  250  at a low temperature, typically 650° C. or lower, forming the more heavily doped epitaxial layers  270  at a similar temperature, and restricting subsequent processing to that temperature or less. In a more general case, the growth of the epitaxial layers  250  and  270  and further processes at elevated temperatures can be optimized so the time and temperature combinations substantially prevent diffusion of dopant ions from the source and drain extensions  250  into the substrate  210 . 
         [0044]    In the currently described invention, the source and drain extensions  250  do not extend into the substrate  210 . Their bases are coplanar with the interface between the substrate  210  and the gate oxide  220 . This configuration gives results in the electric fields shown in  FIG. 2B . This figure shows the electric fields perpendicular to the surface of the substrate of a turned-off transistor with  1  volt on the drain. The electric fields near the source are modest, less than 5×10 5  volts/cm, over most of the channel region. As a result the drain control of the charge in the channel is greatly reduced, improving the electrostatic integrity and allowing much lower channel doping without adversely affecting the subthreshold slope, DIBL and the corresponding leakage. This reduces the tendency of the drain voltage to alter the threshold voltage (short channel effect). The new geometry also reduces the tendency of the transistor to break down by punch-through. 
         [0045]    The source and drain structures  250  and  270  may be used with a variety of transistor substrate configurations.  FIG. 3A  shows some examples. With  FIG. 3A , example (a) is a conventional substrate, where the substrate  310  beneath the transistor is doped with one or more well implants, p-type for NMOS transistors or n-type for PMOS transistors. These may be regular implanted wells or retrograde wells providing a low doped surface at the channel, The gate oxide is indicated as  320 , and shallow trench isolation is  315 . Example (b) shows an approach to reduce the effect of the random doping variations beneath the gate oxide  320 . Layer  312  is an un-doped epitaxial layer, immediately beneath the gate oxide  320 . In this substrate, layer  311  is optional, but when used it is typically heavily doped to combine threshold voltage control and minimal RDF variations in epitaxial transistors. Example (c) is representative of a silicon-on-insulator transistor, with a thin single crystal active layer  313  lying over a thin buried oxide  316 . The thin buried oxide allows a degree of threshold modulation by changing the voltage on the substrate under the isolation and buried oxide. Example (d) is similar to (c), except the oxide beneath the active layer  313  is much thicker, decreasing parasitic capacitance but eliminating convenient threshold modulation. The transistor structure disclosed is usable with any of these classes of substrates. 
         [0046]      FIG. 3B  shows a schematic representation of the transistor of  FIG. 2A  realized using a substrate with an undoped or very lightly doped epitaxial layer  312  supporting the transistor&#39;s channel. The thickness of this layer  312  is designed to minimize the threshold variations arising from statistical variations in the layers  310  and  311  below. Typical thicknesses for layer  312  lie in the range of 3 nm to  30  nm. As noted above, the well region is denoted  310 , and layer  311  is an optional layer of high doping, acceptors for an NMOS transistor or donors for a PMOS transistor. In the extreme, layer  311  is a monolayer of extremely high doping, frequently called a delta layer, with reference to the Dirac delta function. The transistor structure above the undoped layer  312  includes the gate oxide or gate oxide stack  320 , a first, source/drain extension layer  350  formed by low-temperature epitaxial growth. The elimination of diffusion from the source/drain extensions is particularly important when the channel has zero or very light doping. The tails of conventional doping profiles would create irregular variations in the channel length. The second epitaxial layer  370  provides superior conduction and connectivity to the transistor, and it is also grown at low temperature after the formation of dielectric spacers  360 . 
         [0047]    As discussed above, the transistor described here can be realized on a variety of substrates, including SOI, and with a variety of gate architectures, including FinFETs, but the descriptions below will address conventional substrates. Two representative embodiments will be described. The first is a simple adaptation of the most common polysilicon gate transistor structure. The second illustrative embodiment is based on the Gate Last method of fabricating transistors with Hi-K gate dielectrics and work-function-controlled metal gates. 
       Gate First Embodiment 
       [0048]      FIG. 4A  shows a gate oxide  420  grown over a well  410  in a semiconductor substrate on which an integrated circuit is to be formed. The region to be occupied by the subject transistor is isolated from other devices by shallow trench isolation regions  415 . In general, the well  410  will be doped with acceptors, boron (B) or indium (In) ions, if the subject transistor is to be n-type, or it will be doped with donors, phosphorus (P), arsenic (As) or antimony (Sb), if the subject transistor is to be p-type. In the vicinity of the transistor, doping densities in the range of 1×10 17  to 5×10 18  ions per cm 3  are representative, and there is no requirement for extreme doping gradients. In common practice, the gate oxide  420  may be nitrided and a substrate may include one or more oxide thicknesses, as appropriate for the intended operating voltages. 
         [0049]      FIG. 4B  shows the result of depositing amorphous or polycrystalline silicon and patterning that material to for a gate  430 . Since the use of a silicon nitride hard mask is common in patterning gates  430 , some process flows may retain that hard mask on the top surface of the gate  430 . With or without a retained hard mask, the next step is to create a sidewall oxide  440  on the patterned gate  430 . This oxide will preferably have a thickness approximating the thickness of the gate oxide  420 . 
         [0050]    While  FIG. 4B  shows a polysilicon gate and a conventional SiO 2 -based gate dielectric, the gate structure could alternatively be composed of a metallic gate  430  with controlled work function overlying a high-K gate dielectric  420 , possibly comprising an oxide or nitride of hafnium. References below to gate oxide would apply equally to any other selected gate dielectric. 
         [0051]      FIG. 4C  illustrates the results of two critical steps. The first is using an anisotropic etch to clear the gate oxide  420  from the well regions  410  not protected by either the gate  430  or its sidewall oxide  440 . The next step is low-temperature, selective epitaxial growth of the source/drain extensions  450 . These regions  450  are grown to a typical thickness of 3 to 20 nm, thick compared to the gate oxide  420 , but thin compared to the height of the gate  430 . The epitaxial drain extensions  450  are grown at relatively low temperatures, 500° C. to 700° C., and they are doped during the growth process to a typical doping density of  1  x  10   20  to  5  x  10   20  ions per cm 3 . For n-type transistors, the source/drain extensions  450  would normally be doped with phosphorus or arsenic, and the epitaxial material would be silicon. For p-type transistors, the epitaxial material would preferably be silicon-germanium, to facilitate achieving the target doping levels of boron or possibly indium, and to allow the application of a compressive strain in the channel, enhancing mobility and performance. Note that the residual sidewall oxide  440  will be subjected to the extremes of gate to source voltages and drain to gate voltages, so its thickness has to be comparable to or greater than the gate oxide thickness, but still thin enough to avoid a potential barrier between the gate region and the epitaxial source/drain regions. Dimensional control and electrostatic coupling control depend upon having an abrupt junction between the drain extension  450 , doped with dopant ions of a first type and the substrate  410 , undoped or doped with dopant ions of a second type, The ideal would be a step junction between the well region  410  and the epitaxial extension  450 , with one monolayer reflecting the doping density of the well  410  and the adjacent monolayer reflecting the doping density of the extension  450 . Substantially abrupt junctions can be realized by minimizing the diffusion from the drain extension  450  and the substrate  210 . This is typically achieved by using low temperatures for the epitaxial growth of this and the succeeding epitaxial layers and for subsequent process steps in order to establish the most abrupt transition between the higher doping of the drain extension  450  and the adjacent, low doping of the underlying substrate  410 . This abrupt transition helps minimize the variation in transistor thresholds and provide for other improved transistor characteristics, and it can only be realized if all processing temperatures are kept low. Further, the times and temperatures of the epitaxial depositions and subsequent processing of the disclosed process are optimized to provide a substantially abrupt junction between the source and drain extensions  450  and the substrate  410 . 
         [0052]    Because the oxide  440  is thin, the capacitance between the source/drain extensions  450  and the gate  430  has the potential to degrade transistor performance. The drain-to-gate capacitance is particularly critical because it is enhanced by the Miller effect. To utilize a thick, high conductivity source/drain, more dielectric isolation is required.  FIG. 4D  illustrates the formation of a dielectric spacer  460  on the exposed sides of the gate  430 . While the exact nature of the spacers  460  are not critical to the transistor, they are typically formed by depositing a dielectric like silicon nitride, and then using an anisotropic etch to clear the nitride from the surfaces paralleling the substrate while leaving a sidewall of dielectric on the surfaces perpendicular to the substrate. In advanced technology nodes the silicon nitride spacer may be replaced by a spacer formed from a material having lower dielectric constant. Small fillets of the spacer  460  may remain adjacent to the source/drain extensions  450 , but they have no significant effect. 
         [0053]    In order to provide robust, high-conductivity sources and drains, a second epitaxial step produces the source and drain regions  470 , as shown in  FIG. 4E . These epitaxial layers  470  are also doped during growth to typical levels of 5×10 20  to 1×10 21  ions per cm 3 . For n-type transistors, the source/drain regions  470  would normally be doped with phosphorus or arsenic, and the epitaxial material would be silicon. For p-type transistors, the epitaxial material would preferably be silicon-germanium, to facilitate achieving the target doping levels of boron, most frequently, or possibly indium and to increase the compressive strain in the channel. Again, low temperature epitaxy, 500° C. to 700° C. is preferred in order to minimize the diffusion of dopants among the various regions of the transistor. The thickness of the source/drain regions  470  is greater than the thickness of the source/drain extensions  450 , and it may be comparable to the height of the gate  430 . 
         [0054]    The source/drain structure  470  may comprise more than a single epitaxial layer. Other layers may be used to provide either tensile or compressive stress in the transistor channel or to provide other specific device characteristics. Further, while the descriptions above have indicated that silicon would be a logical choice for the epitaxial material in layers  450  and  470  for NMOS transistors, and silicon-germanium would be a logical choice for layers  450  and  470  for PMOS transistors, other choices may be elected, including III-V compound semiconductors, silicon-carbon and silicon-carbon-germanium. The requirement for low-temperature processing remains. 
         [0055]    The finished transistor is shown in  FIG. 4F , where industry standard steps have been used to cap the gate  430  and the epitaxial source/drain regions  470  with a metal silicide  475 . Common silicides include NiSi, CoSi 2  and TiSi 2 . In some instances, the advantages of this transistor structure may be retained and the processing simplified by growing the epitaxial source and drain extensions  450  to a greater thickness, at the expense of increased parasitic capacitance, then forming the suicide  475  directly on the epitaxial layers  450  after forming the spacer  460 . In order to improve the contact metallization it is possible to use a graded epitaxial layer, or multiple epitaxial layer depositions to achieve a high doped surface for silicidation and contact formation. An interlayer dielectric  480  is formed by depositing a silicon dioxide based material after the silicidation  475  and using CMP to create a planar surface. Finally, contact holes are etched and filled with tungsten plugs  490  using industry standard steps and materials sequences that are not detailed here. 
         [0056]    At this point, the transistor is ready for interconnection using patterned metal layers that contact the tungsten contact plugs  490 . 
       Gate Last Embodiment 
       [0057]    Certain aggressive CMOS processes utilize a process sequence called “Gate Last.” This sequence enables the use of exotic high-dielectric-constant gate dielectrics and metal gates having well specified work functions. By processing the gate-related materials after the high-temperature steps have all been completed, a wide spectrum of compounds can be employed without concern for their thermal degradation. Further, metallic gate materials will not be subject to re-crystallization, another source of threshold variability. The double epitaxial structures can be used advantageously with Gate Last technologies, as discussed in the paragraphs below. 
         [0058]      FIG. 5A  shows a schematic cross-section of the commencement of transistor processing. The region  510  is a portion of the substrate having well implants for either an NMOS or a PMOS transistor. That transistor region is separated from other components on the chip by shallow trench isolation  515 . The oxide layer  521  may be a screen oxide for early implant steps or it may be a gate oxide for conventional, gate-first transistors, input and output transistors for example, to be fabricated on the same chip. Several of the subsequent steps are identical to the equivalent steps for a Gate First embodiment. 
         [0059]      FIG. 5B  shows the result of depositing amorphous or polycrystalline silicon and patterning that material to form a sacrificial gate  531 . Since the use of a silicon nitride hard mask is common in patterning gates  530 , some process flows may retain that hard mask on the top surface of the sacrificial gate  531 . With or without a retained hard mask, the next step is to create a sidewall oxide  541  on the patterned sacrificial gate  531 . The target thickness of the sidewall oxide will be determined by the other steps to follow. 
         [0060]      FIG. 5C  illustrates the results of two critical steps. The first is using an anisotropic etch to clear the gate or screen oxide  521  from the well regions  510  not protected by either the sacrificial gate  531  or its sidewall oxide  541 . The next step is low-temperature, selective epitaxial growth of the source/drain extensions  550 . These regions  550  are grown to a thickness of 3 to 20 nm, thick compared to the ultimate gate oxide  520 , but thin compared to the height of the sacrificial gate  531 . The epitaxial drain extensions  550  are grown at relatively low temperatures, 500° C. to 700° C., and they are doped during the growth process, to typical doping densities of 1×10 20  to 5×10 20  ions per cm 3 . For n-type transistors, the source/drain extensions  450  would normally be doped with phosphorus or arsenic, and the epitaxial material would be silicon. For p-type transistors, the epitaxial material would preferably be silicon-germanium, to facilitate achieving the target doping levels of boron, or possibly indium. 
         [0061]    The interfaces between the epitaxial source/drain extensions  550  and the well region  510  should be as close as possible to ideal step junctions, a quality which requires a minimum of thermal exposure during the epitaxial growth and all subsequent processing. 
         [0062]    To avoid transistor performance degradation, relatively low specific capacitance is needed between the greater source and drain structures and the ultimate transistor gate.  FIG. 5D  illustrates the formation of spacer  560  on the exposed sides of the sacrificial gate  531 . While the exact nature of the spacer  560  is not critical to the transistor, it is typically formed by depositing a dielectric like silicon nitride, and then using an anisotropic etch to clear the nitride from the surfaces paralleling the substrate while leaving a sidewall of dielectric on the surfaces perpendicular to the substrate. Small fillets of the spacer  560  may remain adjacent to the source/drain extensions  550 , but they have no significant effect. 
         [0063]    In order to provide robust, high-conductivity sources and drains, a second epitaxial step produces the source and drain regions  570 , as shown in  FIG. 5E . These epitaxial layers  570  are also doped during growth to typical levels of 5×10 20  to 1×10 21  ions per cm 3 . For n-type transistors, the source/drain regions  570  would normally be doped with phosphorus or arsenic, and the epitaxial material would be silicon. For p-type transistors, the epitaxial material would preferably be silicon-germanium, to facilitate achieving the target doping levels of boron, most frequently, or possibly indium. Again, low temperature epitaxy, 500° C. to 700° C. is preferred in order to minimize the diffusion of dopants among the various regions of the transistor. The thickness of the source/drain regions  570  is greater than the thickness of the source/drain extensions  550 , but its upper surface must be less than the height of the sacrificial gate  531 . In order to facilitate further processing, the top surfaces of the source/drain epitaxial layer  570  may be limited to approximately half the height of the sacrificial gate  531 . This epitaxial step and the subsequent thermal processes are kept to low temperatures in order to minimize diffusion that would make the junction between the relatively high doped source/drain extensions and the oppositely, lightly doped substrate less abrupt. This is important to minimizing statistical variations. 
         [0064]    Epitaxial layers  570  may be replaced by multiple layers of epitaxial growth in order to realize alternative device characteristics. Further, the epitaxial layers  550  and  570  are not limited to silicon and silicon-germanium. Other semiconductor materials may be used in order to realize either tensile or compressive stress in the channel or other specific device characteristics. However, the requirement for low-temperature processing remains. 
         [0065]    Subsequent to the selective epitaxial deposition of regions  570 , the contact characteristics of those regions will normally be enhanced by forming a metallic silicide  575  on their upper surfaces. This silicide is normally formed by a controlled reaction with metallic titanium, chromium or nickel with the underlying silicon to form TiSi 2 , CrSi 2  or NiSi. If, after patterning the sacrificial gate  531 , the hard mask is retained, no silicide will form on the upper surface of  531 . If the hard mask has not been retained, a silicide  576  will be grown on the sacrificial gate  531 . 
         [0066]      FIG. 5F  shows that, after forming the silicides  575  on the source/drain regions  570 , a thick interlayer dielectric  581  is deposited on the wafer. The highest structures on the wafer at this point are the spacers  560  and the sacrificial gate  531  with or without its metal silicide  576 . The total thickness of the layer  581  must exceed the elevation of those highest structures. A thickness of two to four times their height is not uncommon. 
         [0067]    As shown if  FIG. 5G , the next step is the employment of chemical mechanical polishing (CMP) first to make the surface of the interlayer dielectric  580  planar, and second to remove the silicide  576  on top of the sacrificial gate  531 , exposing the silicon material  531  lying beneath. The source/drain silicide layers  575  must remain protected by the interlayer dielectric  580 . 
         [0068]    The Gate Last sequence commences, as shown in  FIG. 5H , with selectively etching the sacrificial silicon gate  531 , leaving the surrounding dielectrics  541 ,  560  and  580  intact and creating an opening  532 . Through the opening  532 , the screen oxide  521  is then etched to expose the underlying silicon in the channel region. Depending upon the details of the etch, some part of the screen oxide  521  may be left adjacent to the opening  532 , and similarly, some of the sidewall oxide  541  may remain after the etch that clears the screen oxide  521  from the substrate  510 . 
         [0069]      FIG. 5I  shows the next elements in the Gate Last sequence. The gate oxide stack  520  is deposited. This stack may be a single uniform oxide, or it could be multiple components, possibly including a SiO 2  transition layer adjacent the substrate  510 . In most cases, the gate dielectric  520  will be dominated by a high-K material, frequently an oxide or nitride of hafnium. Depending upon the deposition process, the gate dielectric  520  may be formed on the vertical walls of the cavity  532 . After the gate dielectric  520  is completed, a work-function-controlled, metallic material  530  is deposited, and on top of that a protective conductor  535 , sometimes polycrystalline silicon, is deposited. The combination of dielectrics adjacent to the metallic gate  530 , including the screen oxide  521 , the initial sidewall oxide  541  and the gate oxide  520 , need to be sufficiently thick to isolate the metallic gate  530  from the epitaxial source/drain extensions  550  for all operating voltages. 
         [0070]    Because the deposition of metallic gate  530  and the protective conductor  535  cover the interlayer dielectric  580  with conductive materials, chemical mechanical polishing must be used to clear the added layers  520 ,  530  and  535  back to the interlayer dielectric  580 . This is shown in Figure Si. 
         [0071]      FIG. 5K  shows the finished transistor, including a possible silicide layer  575  over the protective conductor  535 . The interlayer dielectric  580  is covered by a second interlayer dielectric  585 , and the transistor is then contacted by etching apertures in the interlayer dielectrics  580  and  585 . Those apertures are then filled with conducting plugs  590 , typically tungsten to facilitate interconnection among all transistors occupying a specific integrated circuit. 
         [0072]    In each of the descriptions above, the epitaxial layers for the NMOS have been described as silicon, and the epitaxial layers for PMOS have been described as silicon/germanium. The essentials of the double epitaxial source and drain transistors can be realized using any epitaxial materials capable of being doped during their growth and deposited selectively. This includes silicon, of course, but it also includes silicon-germanium and silicon/carbon. Certain III-V compounds may also prove to be advantageous components of these transistors. 
       CMOS Processing 
       [0073]    The principles described in the two embodiments described above may be combined in order to create integrated circuits having different classes of transistors. For instance, a high-performance processing chip may use the Gate Last sequence to create high-K, metal gate transistors that operate at a low voltage, 1 volt or below, but the input and output transistors, operating at 1.5 volts or higher, would employ the simpler polycrystalline silicon gated transistors. The principles of the double epitaxy sources and drains would normally be employed in a complementary manner to form CMOS integrated circuits. Further, the described transistor structure is agnostic with respect to the particular class of substrate employed. While bulk substrates have been used in the illustrative descriptions, the transistor is consistent with all forms of silicon-on-insulator substrates. It is also consistent with transistors using lightly doped or zero doped epitaxial channel layers, independent of the doping profiles beneath that layer. 
         [0074]    The embodiments of the invention as described above are exemplary and should not be considered as limiting. A practitioner of the art will be able to understand and modify the invention to include other steps and process details that can influence the characteristics of the devices and tailor them to specific purposes while retaining the concepts and teachings of the invention. Accordingly, the invention should only be limited by the Claims included herewith.