Abstract:
A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a divisional of U.S. patent application Ser. No. 11/619,671 filed Jan. 4, 2007, the entirety of which is hereby incorporated by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates in general to semiconductor devices and more particularly to high voltage REduced SURface Field (RESURF) transistor devices and methods of making such devices. 
       BACKGROUND OF THE INVENTION 
       [0003]    Both vertical and lateral high voltage transistors are widely used in power applications. In the on state, it is desirable that the transistor have low on resistance to minimize conduction losses. In the off state, it is desirable that the transistor have a high breakdown or blocking voltage. Lateral RESURF transistors are lateral devices having a source and a drain laterally spaced from each other and having a drift region between the source and drain regions. In the on state, current flows between the source and drain through the drift region, while, in the off state, the drift region is depleted preventing current flow. In order to increase the performance characteristics of power transistors, U.S. Pat. No. 6,097,063, issued Aug. 1, 2000, inventor Fujihiro, and U.S. Pat. No. 6,207,994 B1, issued Mar. 27, 2001, inventors Rumennik et al., disclose the use in a lateral device of a drift region having alternating layers of semiconductive material of a first and second conductivity types (p/n). U.S. Pat. No. 5,216,275, issued Jan. 1, 1993, inventor Chen, and U.S. Pat. No. 5,438,215, issued Aug. 1, 1995, inventor Tihanyi, apply this concept to vertical devices. The following article is of interest in disclosing the use in a VDMOS device of metal-thick-oxide at the sidewalls of the drift region to either increase the blocking voltage or increase the background doping—“Oxide-Bypassed VDMOS (OBVDMOS0: An Alternative to Superjunction High Voltage MOS Power Devices”, by Liang et al., IEEE Electron Devices Letters, Vol. 22. NO. 8, Pages 407-409, August 2001. An advantage of the current invention relative to these technologies is the use of four sided rather than two sided depletion regions when in the voltage blocking state. 
         [0004]    There is a constant need for transistors with both high blocking voltage and ever lower on state resistance. The present invention addresses this need. 
       SUMMARY OF THE INVENTION 
       [0005]    According to the present invention there is provided a solution to the needs discussed above. 
         [0006]    According to a feature of the present invention, there is provided 
         [0007]    a semiconductor device comprising: 
         [0008]    a semiconductor substrate; 
         [0009]    a source region and a drain region provided in said substrate; wherein said source region and said drain region are laterally spaced from each other; 
         [0010]    a drift region in said substrate between said source region and said drain region; 
         [0011]    wherein said drift region includes a structure having at least first and second trench capacitors extending between said source region and said drain region, said trench capacitor having an inner plate and a dielectric material adjacent to said inner plate; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of said first conductivity type, wherein said stack lies between said at least first and second trench capacitors and in contact with said dielectric of said first and second trench capacitors; 
         [0012]    wherein, when said device is in an on state, current flows between said source and drain regions through said second region of said second conductivity type; and, when said device is in an off/blocking state, said second conductivity region is depleted four ways into said first and third regions of said stack and into said first and second trench capacitors. 
         [0013]    According to another feature of the present invention, there is provided 
         [0014]    a method of making a semiconductor device comprising: 
         [0015]    providing a semiconductor substrate having a source and a drain laterally spaced from each other with a drift region between said source and drain region; 
         [0016]    forming an area in said drift region including at least a first region of a first conductivity type, a second region of a second conductivity type on top of said first region, and a third region of said first conductivity type on top of said second region; and 
         [0017]    producing in said area at least two spaced trench capacitors extending between said source and said drain, wherein a stack of said first, second, and third regions is formed between said trench capacitors in electrical connection with said trench capacitors. 
         [0018]    The present invention has the following advantages: 
         [0019]    1. A RESURF high voltage transistor is provided that uses MOS capacitor depletion in addition to PN junction depletion in the blocking mode. This allows significantly higher doping in the drift region and thus greatly reduces the on state resistance of the transistor. 
         [0020]    2. By using depletion from four sides in the blocking mode, there is an improvement over known two-side depletion, thus improving the properties of the transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    The aforementioned and other features, characteristics, advantages, and the invention in general will be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which: 
           [0022]      FIG. 1  is a plan, diagrammatic view of an embodiment of the present invention; 
           [0023]      FIG. 2  is an elevational, cross-sectional, diagrammatic view taken along line  2 - 2  in  FIG. 1 ; 
           [0024]      FIG. 3  is an elevational, cross-sectional, diagrammatic view taken along line  3 - 3  in  FIG. 1 ; 
           [0025]      FIGS. 4A-4C  are cross-sectional diagrammatic views taken along line  4 A, B, C- 4 A, B, C in  FIG. 1 ; 
           [0026]      FIG. 4D  is a cross-sectional, diagrammatic view taken along line  4 D- 4 D in  FIG. 1 ; 
           [0027]      FIGS. 5A-5E  are cross-sectional diagrammatic views illustrating select details in fabricating the invention of  FIG. 1 ; 
           [0028]      FIGS. 6A-6D  are cross-sectional diagrammatic views illustrating further select details in fabricating the invention of  FIG. 1 ; 
           [0029]      FIG. 7  is a plan, diagrammatic view of two of the embodiments shown in  FIG. 1  together with an additional device on a single substrate with an isolation region that surrounds each of the three devices; 
           [0030]      FIG. 8  is an elevational, cross-sectional, diagrammatic view taken along line  8 - 8  in  FIG. 7 ; and 
           [0031]      FIG. 9  is an elevational, cross-sectional, diagrammatic view of the embodiment shown in  FIG. 1  together with a complementary embodiment in a CMOS integrated circuit arrangement. 
       
    
    
       [0032]    It will be appreciated that for purposes of clarity and where deemed appropriate, reference numeral have been repeated in the figures to indicate corresponding features. Also, the relative size of various objects in the drawings has in some cases been distorted to more clearly show the invention. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0033]    Example embodiments of the invention are now provided. While these illustrate application of concepts to silicon-based power devices, it is intended that the principles disclosed herein will apply to a wide variety of semiconductor devices, including those formed with compound semiconductor materials, e. g., silicon carbide, as well as integrated circuits. Although examples of devices reference specific conductivity types, and incorporation of specific materials, e. g., dielectrics and conductors, these are only exemplary and it is not intended that the invention be limited to embodiments that incorporate such conventional components or methodologies. For example the embodiments shown herein are NMOS transistors, but the present invention is also applicable to a PMOS transistor by reversing the doping polarities. 
         [0034]    Referring now to  FIG. 1 , there is shown an embodiment of the present invention. As shown, RESURF transistor  10  includes a semiconductor N −  substrate  12  with a source  14  having a p− well  16 , gate  20 , drain  22  having a drain contact  24 , and a drift region  26  between source  14  and drain  22 . Drift region  26  incorporates the trench MOS capacitor/P + /N +  junction hybrid structure. More particularly, the hybrid structure  26  includes spaced trench MOS capacitors  28  separated by P + /N +  stacks  30 . Each of the P + /N +  stacks  30  have a vertical P +  region  32 , which are also shown in  FIG. 4D , and which make contact with each P +  and N +  layer in their respective stack so that all the P+ regions are connected to each other in parallel, and likewise all the N+ regions are connected to each other in parallel. The P +  doped regions  32  are also electrically tied to the poly filling in the trench capacitors  28  by a metal layer represented schematically by the connections  34  in  FIG. 4D . The regions  32  connect the P +  layers in the P + /N +  stack  26  with the P +  polysilicon in the trench capacitors  28  in order to create four sided depletion regions in the N +  layers in the P + /N +  stack  26  as shown in  FIG. 4C . 
         [0035]      FIGS. 2 and 3  are respective elevational, cross-sectional, diagrammatic views taken along line  2 - 2  and  3 - 3  in  FIG. 1 .  FIG. 2  shows the profile of one of the trench capacitors  28  showing the silicon dioxide dielectric layer  40  and the polysilicon  42 .  FIGS. 2 and 3  indicate with arrows  44  the current flowing between source  14  and drain  22  through the P + /N +  stacks  30  when the RESURF transistor  10  is on. The P + /N +  stacks  30  includes regions  46  of a first conductivity type of P +  interleaved with regions  48  of a second conductivity type of N + . As shown in  FIGS. 2 and 3 , the current flows principally through the N +  regions  48 . 
         [0036]      FIGS. 4A-4D , are cross-sectional diagrammatic views taken along line  4 A, B, C- 4 A, B, C in  FIG. 1 . As shown, trench capacitors  28  include trenches  50  having silicon dioxide sidewalls  40  filled with doped polysilicon  42 . N +  regions  48  are conduction/blocking regions depending on whether the RESURF transistor  10  is on or off. 
         [0037]      FIG. 4B  shows the semiconductor device in the on state in which the junctions of the P + /N +  layers of P + /N +  stacks  30  and the trench capacitors  28  are biased so as not to deplete the N +  doped conduction regions  48 . Current is shown as flowing into the plane of the figure as depicted by the crossed circles  56 . 
         [0038]      FIG. 4C  shows the semiconductor device in the off state in which the junctions between the P + /N +  layers of the P + /N +  stacks  30  and the trench capacitors  28  are biased so as to deplete the N +  doped conduction regions  48  from four sides. Current flow is thus blocked as shown by the dashed line rectangles  60 . Because of the four-sided depletion, the doping of the N +  layer  48  layers can be significantly higher (up to a factor of 2) or the size of the N +  layers  48  can be significantly increased, or a combination of increasing the doping and the size of the N +  layers  48 , than with two sided depletion regions while still depleting the N +  layers  48  when the RESURF transistor  10  is off. The higher doping and/or increased surface area of the N +  region significantly reduces the on state resistance of the device. 
         [0039]      FIG. 4D  is a cross-sectional, diagrammatic view taken along line  4 D- 4 D in  FIG. 1 . The P +  regions  32  form a connection of the P +  layers  32  to the top of the RESURF transistor  10 , which are joined together with the P +  polysilicon  42  in the trench capacitors  22  by metallization (not shown) in one embodiment of the invention. The common connection  34  of the P +  layers  32  and the P +  polysilicon  42  in the trench capacitors  28  provide uniformity in the depletion regions  46  when the RESURF transistor  10  is off. 
         [0040]      FIGS. 5A-5C  are cross-sectional diagrammatic views illustrating select details in fabricating the invention of  FIG. 1 . to show select details in fabricating the P + /N +  layers of the P + /N +  stacks  30 .  FIGS. 5A-5C  show successive P +  and N +  implants  70 ,  72 ,  74 ,  76 , and  78  to form the multiregion area for the P + /N +  stacks  30 . Those skilled in the art will appreciate that the P + /N +  layers can also be formed by diffusion or with epitaxial layers. 
         [0041]      FIGS. 6A-6D  are cross-sectional diagrammatic views illustrating further select details in fabricating the invention of  FIG. 1  to show select details in forming the trench capacitors  28 .  FIG. 6A  shows a mask  80  on the upper surface of semiconductor substrate  12 . One or more trenches  82  are etched in the P + /N +  stacks  30  for forming trench capacitors  28 .  FIG. 6B  shows silicon dioxide  40  deposited or grown on the side walls and bottom of trenches  82 .  FIG. 6C  shows P + /N +  polysilicon  84  deposited in the trenches  82  to form trench the capacitors  28 . The mask  80  and the portion of the P + /N +  polysilicon above the substrate  12  are then removed. 
         [0042]      FIG. 6D  shows another mask  88  formed on the top of the substrate  12  and the P +  regions  46  formed by ion implantation in one embodiment. After the regions  32  are formed, the mask  88  is removed. 
         [0043]    The trench capacitors  28  are fabricated in the same manner as a trench gate, and therefore do not require any additional masks. Using p+ pillars in place of the trench capacitors  28  would require additional processing not needed with the trench capacitors  28 . 
         [0044]      FIG. 7A  is a plan, diagrammatic view of two of the RESURF transistors  10  shown in  FIG. 1  together with an additional device  100  on a single P −  substrate  102  (shown in  FIG. 7B ) with an N −  epi layer  104  and an isolation region  106  that surrounds each of the three devices. 
         [0045]      FIG. 7B  is an elevational, cross-sectional, diagrammatic view taken along line  7 B- 7 B in  FIG. 7A . As can be seen in  FIG. 7A  the trench capacitors  28  extend down into the P −  substrate  102  as does the isolation region  106  to thereby isolate the three devices shown in  FIG. 7A . 
         [0046]    The additional device  100  may be an controller for a synchronous buck converter, for example, that controls the two RESURF transistors  10  with the three devices interconnected by wire bonds. 
         [0047]      FIG. 8  is an elevational, cross-sectional, diagrammatic view of the RESURF transistor  10  shown in  FIG. 1  together with a complementary RESURF transistor  110  in a P −  well  112  used in CMOS integrated circuits. The majority doping types in the complementary RESURF transistor  110  are opposite to the doping types in the RESURF transistor  10 . Thus, the corresponding capacitors  112  are filled with N+ polysilicon  114 , and each of the P+/N+ stacks  116  have N+ top middle and bottom layers  118 , and P+ layers  120  between the N+ layers  118 . 
         [0048]    Although specific embodiments of the invention have been shown and described, it will be understood that variations and modifications can be effected within the spirit and scope of the invention. Thus, other materials well known to those skilled in the art can be used to form the trench capacitors and other processes can be used to form the p/n stacks and trench capacitors. In addition, the device can have more or less than the number of trench capacitors shown, and more or less than the number of alternating regions of said first and second conductivity types in said stacks.