Abstract:
An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.

Description:
This application claims the benefit of U.S. Provisional Application Ser. No. 61/692,335, filed Aug. 23, 2012, which is hereby incorporated by reference. 
     FIELD OF THE INVENTION 
     The present invention relates to designing circuits for test generally and, more particularly, to a method and/or apparatus for core wrapping in the presence of an embedded wrapped core. 
     BACKGROUND OF THE INVENTION 
     Core wrapping is a design-for-test solution that handles testing of large system-on-a-chip (i.e., SoC) designs by implementing and executing tests in a same hierarchical manner as the rest of the design steps (i.e., timing and physical design). The core wrapping enables the tests to be inserted and verified by concurrent teams. 
     Currently available techniques for hierarchical testing using wrapped cores do not address certain situations. Some situations include designs in which multiple wrapped cores are embedded within another wrapped core. Other situations include designs having multiple levels of nested wrapped cores. Conventional testing of hierarchical implementations treat the designs as a single level hierarchical implementation where different hierarchical cores are sitting adjacent to each other. 
     Referring to  FIG. 1 , a diagram of a conventional die  20  having a wrapped embedded core  22  is shown. The die  20  has a wrapper  24 , an internal scan chain  26 , interface logic  28   a - 28   n  and an internal test (i.e., INTEST) test compression logic (i.e., TCL) block  30 . The wrapped embedded core  22  includes a wrapper  34 . 
     During an internal test mode, the wrapper  24  and the internal scan chain  26  are driven by the internal test TCL block  30 . During an external test mode, the wrapper  24  is driven by an external test (i.e., EXTEST) test compression logic block  36  outside the die  20 . Instantiating the wrapped core  22  into the die  20  results in a loss of coverage loss of the interface logic  28   a - 28   n . In the internal test mode, the wrapper  34  is in a non-observation mode, so fault effects through the interface logic  28   a - 28   n  cannot be observed. In the external test mode, the internal scan chain  26  is not scanned so the interface logic  28   a - 28   n  cannot be controlled. 
     It would be desirable to implement core wrapping in the presence of an embedded wrapped core. 
     SUMMARY OF THE INVENTION 
     The present invention generally concerns an apparatus having a core and one or more logic blocks. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core. 
     The objects, features and advantages of the present invention include core wrapping in the presence of an embedded wrapped core that may (i) support design-for-test techniques, (ii) enable hierarchical testing, (iii) enable tests to be inserted and verified by concurrent teams working in different geographical locations and different cores, (iv) reduce test generation time, (v) reduce test verification turnaround time, (vi) enable test scheduling of the cores to efficiently deal with issues of test power and defect isolation during debug, (vii) provide nested scan testing of hierarchical cores, (viii) enable sub-design blocks to be plugged into the design independent of the testing configuration and/or (ix) be implemented in an integrated circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a diagram of a conventional die having a wrapped embedded core; 
         FIG. 2  is a block diagram of an apparatus in accordance with a preferred embodiment of the present invention; 
         FIG. 3  is a block diagram of an example implementation of a multi-embedded core circuit; 
         FIG. 4  is a block diagram of an example implementation of nested embedded wrapped cores; 
         FIG. 5  is a block diagram of an example implementation of a circuit having wrapper chain connections; 
         FIG. 6  is a block diagram of an example implementation of another circuit having wrapper chain connections; 
         FIG. 7  is a block diagram of an example implementation of a circuit with embedded unwrapped cores; 
         FIG. 8  is a block diagram of an example implementation of a circuit with embedded wrapped cores; 
         FIG. 9  is a block diagram of an example apparatus implementing a method for circuit design in the presence of an embedded wrapped core; 
         FIG. 10  is a block diagram of an example internal test configuration of an embedded wrapped core; 
         FIG. 11  is a block diagram of an example external test configuration of an embedded wrapped core; 
         FIG. 12  is a block diagram of an example modular test configuration of an embedded wrapped core; and 
         FIG. 13  is a block diagram of a hierarchical test configuration of an embedded wrapped core. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Some embodiments of the present invention generally concern design-for-test (e.g., DFT) logic and techniques that may enable a creation of one or more core isolation wrappers (or scan chains) for cores (or blocks, or cells, or circuits, or macros) that include one or more internally embedded wrapped cores. Furthermore, one or more of the embedded wrapped cores may also contain one or more levels of nested embedded wrapped cores. The logic and/or techniques generally allow all wrapped cores, regardless if such wrapped cores are embedded within another wrapped core or not, to be scheduled independently in an arbitrary manner for core internal testing. A single external test mode is generally sufficient to be established for an entire system-on-a-chip (e.g., SoC) design having the embedded cores. Furthermore, the DFT logic and techniques generally allow configurable testing of nested embedded hierarchical architectures while retaining a plug-and-play nature of the embedded cores. 
     Referring to  FIG. 2 , a block diagram of an apparatus  100  is shown in accordance with a preferred embodiment of the present invention. The apparatus (or die, or chip, or circuit, or block, or macro, or integrated circuit or wrapped core)  100  may include one or more embedded cores (or circuits)  102  (a single core shown for clarity). The circuit  100  generally comprises a wrapper (or circuit)  104 , one or more scan chains (circuits)  106 , one or more blocks (or circuits)  108   a - 108   n , a block (or circuit)  110  and a wrapper (or circuit)  112 . The core  102  generally includes a wrapper (or circuit)  114 . Multiple interface blocks (or circuits)  116   a - 116   n  may be provided in the circuit  100  to interface to the external test TLC block  36 . The circuits  100  to  116   n  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. 
     The wrapper  104  generally comprises multiple blocks (or circuits)  120   a - 120   n  and multiple blocks (or circuits)  122   a - 122   n . The scan chain  106  may include multiple blocks (or circuits)  126   a - 126   n . The wrapper  112  generally comprises multiple blocks (or circuits)  128   a - 128   n  and multiple blocks (or circuits)  130   a - 130   n . The wrapper  114  may include multiple blocks (or circuits)  132   a - 132   n  and multiple blocks (or circuits)  134   a - 134   n . The circuits  120   a  to  134   n  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. 
     One or more of the circuits  128   a - 128   n  and  130   a - 130   n  may be directly connected to the circuits  108   a - 108   n . One or more of the circuits  128   a - 128   n  and  130   a - 130   n  may be directly connected to the circuits  132   a - 132   n  and  134   a - 134   n . One or more of the circuits  132   a - 132   n  may be directly connected to the circuits  108   a - 108   n . The wrapper  104  may be coupled to the interfaces  116   a - 116   n  (e.g., coupled to the interface  116   n ) and the circuit  110 . The wrapper  112  may be coupled to the interfaces  116   a - 116   n  (e.g., coupled to the interface  116   b ) and the circuit  110 . The wrapper  114  may be coupled to the interfaces  116   a - 116   n  (e.g., coupled to the interface  116   a ) and the circuit  110 . The scan chain  106  may be coupled to the circuit  110 . 
     When the wrapped core  102  is instantiated into the circuit  100 , which is also wrapped (e.g., the wrapper  104 ), an isolation wrapper (e.g., the wrapper  112 ) may be created around the interface with the embedded wrapped core  102  and the circuits  108   a - 108   n  in a manner similar to the wrapper  104  around a periphery of the circuit  100 . Input signals driving the embedded wrapped core  102  may be treated as “pseudo” output signals from the circuit  100  and analyzed in the same way as the actual output signals generated by the circuit  100  for the purpose of inclusion in the wrapper. Output signals generated by the embedded wrapped core  102  may be treated as “pseudo” input signals into the circuit  100  and analyzed in the same way as the actual input signals received by the circuit  100  for the purpose of inclusion in the wrapper. 
     The circuit  100  may implement an electronic circuit having one or more embedded wrapped cores. The circuit  100  is generally operational to perform multiple logic functions. The functions generally accept input data into the circuit  100  through the circuits  120   a - 120   n . Output data generated by the functions may be presented off the circuit  100  through the circuits  122   a - 122   n . The circuit  100  may also be operational to perform internal testing and/or external testing. 
     The circuit  102  may implement a core circuit. The circuit  102  is generally operational to perform one or more logic functions. The functions generally accept input data into the circuit  102  through the circuits  132   a - 132   n . Output data generated by the functions may be presented off the circuit  102  through the circuits  134   a - 134   n . The circuit  102  may also be operational to perform internal testing and/or external testing. 
     The wrapper  104  may implement a scan chain (or peripheral wrapper). The wrapper  104  is generally operational to control data flows into and out of the circuit  100 . In a normal operational mode, the wrapper  104  may pass data unaltered from input interfaces to output interfaces of the various scan cells. In one or more test modes, the wrapper  104  may be operational to scan data into the circuits  120   a - 120   n  and/or  122   a - 122   n  serially, present and/or capture data in parallel, and read out the captured data sequentially. The wrapper  104  may be controlled by the circuit  110  and the circuit  36  (when connected to the circuits  116   a - 116   n ). 
     The circuit  106  may implement a scan chain. The scan chain  106  is generally operational to control data flows internal to the circuit  100 . In the normal operational mode, the scan chain  106  may pass data through unaltered. In one or more test modes, the scan chain  106  may be operational to scan data into the circuits  126   a - 126   n  serially, present and/or capture data in parallel, and read out the captured data sequentially. The scan chain  106  may be controlled by the circuit  110 . 
     The circuit  108   a - 108   n  may implement logic circuits. The circuits  108   a - 108   n  are generally operational to provide glue logic to interface the circuit  102  with the rest of the circuit  100 . Each circuit  108   a - 108   n  may be coupled between the circuit  102  and the wrapper  112 . 
     The circuit  110  may implement an internal test (e.g., INTEST) test compression logic (e.g., TLC) circuit for test compression. The circuit  110  may coupled to the wrappers  104 ,  106  and  112 . The circuit  110  is generally operational to conduct the internal tests of the circuit  100 . The circuit  110  may also be operational to conduct interface testing of the interfaces between (i) the circuit  100  and the external world and (ii) the circuit  100  and the circuit  102 . The circuit  110  may also conduct testing of the circuit  102  via the wrapper  112 . 
     The wrapper  112  may implement a scan chain (or isolation wrapper). The wrapper  112  is generally operational to control data flows between the circuit  100  and the combination of the circuits  102  and  108   a - 108   n . In the normal operational mode, the wrapper  112  may pass data unaltered from input interfaces to output interfaces of the various scan cells. In one or more test modes, the wrapper  112  may be operational to scan data into the circuits  128   a - 128   n  and/or  130   a - 130   n  serially, present and/or capture data in parallel, and read out the captured data sequentially. The wrapper  112  may be controlled by the circuit  110  and the circuit  36 , when connected. 
     The wrapper  114  may implement a scan chain (or peripheral wrapper). The wrapper  104  is generally operational to control data flows into and out from the circuit  102 . In the normal operational mode, the wrapper  114  may pass data unaltered from input interfaces to output interfaces of the various scan cells. In one or more test modes, the wrapper  114  may be operational to scan data into the circuits  132   a - 132   n  and/or  134   a - 134   n  serially, present and/or capture data in parallel, and read out the captured data sequentially. The wrapper  114  may be controlled by the circuit  36 . 
     Each circuit  116   a - 116   n  may implement an interface (or port) circuit. The circuits  116   a - 116   n  are generally operational to provide communication of data and commands between the wrappers (e.g., the wrappers  104 ,  112  and  114 ) and the circuit  36 . 
     Each circuit  120   a - 120   n ,  122   a - 122   n ,  126   a - 126   n ,  130   a - 130   n ,  132   a - 132   n  and  134   a - 134   n  may implement a scan cell circuit. The circuits  120   a - 120   n ,  130   a - 130   n  and  132   a - 132   n  may implement input-types of scan cells. The circuit  122   a - 122   n ,  128   a - 128   n  and  134   a - 134   n  may implement output-types of scan cells. In some embodiments, one or more of the scan cell circuits may implement bidirectional-types of scan cells. In the normal operational mode, the scan cell circuits may be operational to pass data through from input interfaces to output interfaces. In the one or more test modes, some scan cell circuits may be loaded with test data serially from the circuit  110  and/or the circuit  36 , present the test data in parallel, capture new data, and serially present the captured data to the circuit  110  and/or the circuit  36 . Some scan cells may implement a shift-only state (e.g., SS). In the shift-only state, the scan cells generally act as launch points for data serially scanned into the cells. Shifted data may be loaded into such scan cells by a shift operation via a scan path but data is typically not captured via a functional path. Other scan cells may implement a transparent state (e.g., TS). In the transparent state, the scan cells generally act as any other scan, flip-flop in which data may be shifted via the shift path and data may be captured via the functional path. 
     The circuits  120   a - 120   n  and  122   a - 122   n  generally form the wrapper  104  at an external boundary of the circuit  100 . The circuits  126   a - 126   n  may form the scan chain  106  internal to the circuit  100 . The circuits  128   a - 128   n  and  130   a - 130   n  may form the wrapper  112  at the interface between (i) the circuit  102  and the circuits  108   a - 108   n  and (ii) the rest of the circuit  100 . The circuits  132   a - 132   n  and  134   a - 134   n  may form the wrapper  114  at an outer boundary of the circuit  102 . 
     For internal testing of the wrapped cores (e.g., the circuits  100  and  102 ), no dependencies generally exist between the circuit  100  and the circuit  102 . The circuit  102  may be tested independently of the operation of the rest of the circuit  100 . The circuit  100  may be tested independently of the operation of the circuit  102 . Therefore, all the embedded wrapped cores (e.g., the circuit  102 ) and the rest of the circuit  100  may be scheduled for testing either in the same internal test session or in different internal test sessions. 
     For interface testing (e.g., EXTEST) (i) at the external interfaces of the circuit  100  and (ii) between the circuit  102  and the rest of the circuit  100 , a single interface (or external) test session may be supported for testing (i) the circuits  100 / 102  and (ii) an entire SoC in which the circuits  100 / 102  are a part. The interface connections (e.g., the circuits  120   a - 120   n ,  122   a - 122   n ,  128   a - 128   n ,  130   a - 130 ,  132   a - 132   n  and  134   a - 134   n ) between the embedded wrapped cores and the external wrapped core may be tested in the external test mode. 
     A single external test mode may be defined for the entire SoC. In the single external test mode, only the circuits  108   a - 108   n  may be tested. Therefore, the remaining logic within the circuits  100  and  102  may be removed from a netlist representation used for an external test mode pattern generation and simulation of the SoC. The operation of the circuit  100 / 102  may be emulated by controlling the wrappers  104 ,  112  and  114  with the circuit  36 . 
     Referring to  FIG. 3 , a block diagram of an example implementation of a multi-embedded core circuit  100   a  is shown. The circuit  100   a  may be a variation of the circuit  100 . The circuit  100   a  generally comprises multiple cores (or circuits)  102   a - 102   b , the wrapper  104  and multiple wrappers (or circuits)  112   a - 112   b . The circuits  102   a - 102   b  may be embedded wrapped cores within the circuit  100   a . Each circuit  102   a - 102   b  generally comprises a respective wrapper (or circuit)  114   a - 114   b . The circuits  100   a - 114   b  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. The circuits  102   a - 102   b  may be the same as or variations of the circuit  102 . In some embodiments, the circuits  102   a  and  102   b  may be instantiations of the same core. In other embodiments, the circuit  102   a  may have a different design than the circuit  102   b.    
     The multiple embedded wrapped cores  102   a - 102   b  and the remainder of the circuit  100   a  may all be scheduled independently during internal testing either in the same internal test session or across multiple internal test sessions in any arbitrary grouping of the wrapped cores. 
     Referring to  FIG. 4 , a block diagram of an example implementation of a nested embedded wrapped circuit  100   b  is shown. The circuit  100   b  may be a variation of the circuits  100  and/or  100   a . The circuit  100   b  generally comprises multiple cores (or circuits)  102   c - 102   d , the wrapper  104  and a wrapper (or circuit)  112   c . The circuit  102   d  may be an embedded wrapped core within the circuit  102   c . The circuit  102   c  may be an embedded wrapped core within the circuit  100   b . The circuit  102   c  generally comprises a wrapper (or circuit)  112   d  and a wrapper (or circuit)  114   c . The circuit  102   d  generally comprises a wrapper (or circuit)  114   d . The circuits  100   b - 114   d  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. The circuits  102   c - 102   d  may be the same as or variations of the circuits  102 ,  102   a  and/or  102   b.    
     Embedding of wrapped cores may be performed at any level by providing a corresponding isolation wrapper (e.g., wrappers  112   c - 112   d ). The multiple embedded wrapped cores may all be scheduled independently during internal testing either in the same internal test session or across multiple internal test sessions in any arbitrary grouping of the wrapped cores. 
     Referring to  FIG. 5 , a block diagram of an example implementation of a circuit  100   c  having wrapper chain connections is shown. The circuit  100   c  may be a variation of the circuits  100 ,  100   a  and/or  100   b . The circuit  100   c  generally comprises a core (or circuit)  102   e , the wrapper  104 , the scan chain  106 , the circuit  110  and the wrapper  112 . The circuit  102   e  may be an embedded wrapped core within the circuit  100   c . The circuit  102   e  generally comprises the wrapper  114 . The circuits  100   c - 114  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. The circuit  102   e  may be the same as or a variation of the circuits  102 ,  102   a ,  102   b ,  102   c  and/or  102   d.    
     The circuit  102   e  may include an INTEST TCL circuit. The INTEST TCL circuit may be operational to perform testing of the circuit  102   e . The wrapper  114  and any other internal scan chains within the circuit  102   e  may be connected to the INTEST TCL circuit designed into the circuit  102   e.    
     When multiple embedded wrapped cores are present, the circuit  36  and/or any other compression logic may drive all of the wrappers (e.g., wrapper  114 ) of the embedded wrapped cores (e.g., circuit  102   e ) and the wrappers (e.g., wrappers  104  and  112 ) of the outside core (e.g.,  100   c ). 
     Referring to  FIG. 6 , a block diagram of an example implementation of another circuit  100   d  having wrapper chain connections is shown. The circuit  100   d  may be a variation of the circuits  100 ,  100   a ,  100   b  and/or  100   c . The circuit  100   d  generally comprises the circuit  102   e , a core (or circuit)  102   f  and a block (or circuit)  36   a . The circuit  102   f  may be an embedded wrapped core within the circuit  100   d . The circuits  36   a ,  100   d - 102   f  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. The circuit  102   f  may be the same as or a variation of the circuits  102 ,  102   a ,  102   b ,  102   c ,  102   d  and/or  102   e . In some embodiments, the circuits  102   e  and  102   f  may be instantiations of the same core. In other embodiments, the circuit  102   e  may have a different design than the circuit  102   f.    
     The circuit  36   a  may be the same as or a variation of the circuit  36 . The circuit  36   a  may be operational to test the circuits  100   d ,  102   e  and/or  102   f . When multiple embedded wrapped cores are present, the circuit  36   a  may be operational to drive all of the wrapper chains of the embedded wrapped cores (e.g., circuits  102   e  and  102   f ) and the outside core (e.g., circuit  100   d ). The circuit  110  may be operational to test the circuit  110   d  and control the interfaces between (i) the circuit  102   e  and the rest of the circuit  100   d  and (ii) the circuit  102   f  and the rest of the circuit  100   d.    
     Referring to  FIG. 7 , a block diagram of an example implementation of a circuit  100   e  with embedded unwrapped cores is shown. The circuit  100   e  may be a variation of the circuits  100 ,  100   a ,  100   b ,  100   c  and/or  100   d . The circuit  100   e  generally comprises a block (or circuit)  102   g , a block (or circuit)  102   h , a block (or circuit)  102   i , multiple blocks (or circuits)  136   a - 136   d  and multiple blocks (or circuits)  138   a - 138   n . The circuits  102   g - 102   i  may be embedded unwrapped cores within the circuit  100   e . The circuits  100   e ,  102   g - 102   i  and  136   a - 138   n  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. In some embodiments, the circuits  102   g - 102   i  may be instantiations of the same core. In other embodiments, the circuits  102   g - 102   i  may have different designs. 
     Since none of the circuits  102   g - 102   i  are wrapped, the circuits  102   g - 102   i  may be treated as part of the circuit  100   e  for self-test purposes. No extra wrappers may be applied around the circuits  102   g - 102   i  to control the interfaces. The circuits  136   a - 136   d  and  138   a - 138   n  may be treated as input, output and/or bidirectional wrapper (or scan) cells. For example, each circuit  136   a  and  136   b  may be implemented as input scan cell circuit. The circuit  136   c  may be implemented as a bidirectional scan cell circuit. The circuit  136   d  may be implemented as an output scan cell circuit. Each circuit  138   a - 138   c  may be implemented as part of the core scan chains of the circuit  100   e . The circuit  138   n  may implement another output scan cell circuit. 
     Referring to  FIG. 8 , a block diagram of an example implementation of a circuit  100   f  with embedded wrapped cores is shown. The circuit  100   f  may be a variation of the circuits  100 ,  100   a ,  100   b ,  100   c ,  100   d  and/or  100   e . The circuit  100   f  generally comprises a block (or circuit)  102   j , a block (or circuit)  102   k , a block (or circuit)  102   m , the circuits  136   a - 136   d  and the circuits  138   a - 138   n . The circuits  102   j - 102   m  may be embedded wrapped cores within the circuit  100   f . The circuits  100   f ,  102   j - 102   m ,  136   a - 136   d  and  138   a - 138   n  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. In some embodiments, the circuits  102   j - 102   m  may be instantiations of the same core. In other embodiments, the circuits  102   j - 102   m  may have different designs. 
     In the presence of embedded wrapped cores, the wrapper chain analysis for the outer core is generally changed relative to the circuit  100   f . The circuits  136   a - 136   d  may form part of the outer wrapper (e.g., wrapper  104 ). One or more of the circuits  136   a - 136   d  (e.g., the circuits  136   a ,  136   b  and  136   d ) may be adjusted relative to the circuit  100   e  ( FIG. 7 ) to operate as bidirectional scan cell circuits in the circuit  100   f . The circuit  138   a - 138   n  may by adjusted from being part of one or more internal scan chains within the circuit  100   e  to operate as part of an isolation wrapper (e.g., wrapper  112 ) at the interfaces between (i) the circuit  100   f  and the circuits  102   j - 102   m  and (ii) between the circuits  102   j - 102   m  and each other. Some of the circuits  138   a - 138   n  (e.g.,  138   a  and  138   c ) may be operational as output scan cells of the isolations wrappers. Some of the circuits  138   a - 138   n  (e.g.,  138   b ) may be operational as input scan cells of the isolation wrappers. Some of the circuits  138   a - 138   n  (e.g.,  138   n ) may be operational as input scan cells, output scan cells or bidirectional scan cells of the isolation wrappers. 
     Referring to  FIG. 9 , a block diagram of an example apparatus  140  implementing a method for circuit design in the presence of an embedded wrapped core is shown. The apparatus (or system or circuit)  140  may be implemented as a computer (or processor)  142  and one or more storage media (or memory devices)  144   a - 144   b . The storage media  144   a - 144   b  may be implemented as non-transitory media. 
     A storage medium  144   b  may store a software program (or program instructions)  146  and a library  148 . The software program  146  may define multiple steps of a circuit design in the presence of one or more embedded wrapped cores. The library  148  may define one or more files of wrapped and/or unwrapped cores. The storage medium  144   a  may hold a design file  150  containing one or more designs of one or more circuits (e.g., circuits  100 - 100   g ). 
     The software program  146  may be read and executed by the computer  142  to implement the process of designing circuits with the embedded wrapped cores. During the circuit design, one or more wrapped and/or unwrapped cores may be read from the library  148  and embedded (added) to the circuit design being created. The circuit design process may include adding logic blocks (e.g., circuits  108   a - 108   n ) to interface the embedded cores to the rest of the circuit. Isolation wrappers (e.g., wrapper  112 ) may also be added around each embedded wrapped core to support design-for-test. The internal/isolation wrappers (or scan chains) may be coupled to one or more internal test circuits (e.g., circuit  110  and circuit  36   a ) and/or one or more ports (e.g., ports  116   a - 116   n ) connectable to one or more external test circuits (e.g., circuits  36 ). The completed design may be stored in the file  150 . 
     Referring to  FIG. 10 , a block diagram of an example internal test configuration of an embedded wrapped core  102   p  is shown. The circuit  102   p  may be an embedded wrapped core within any one or more of the circuits  100 - 100   g . The circuit  102   p  generally comprises one or more blocks (or circuits)  160   a - 160   n , one or more blocks (or circuits)  162   a - 162   n , one or more blocks (or circuits)  164   a - 164   n  and a block (or circuit)  166 . The circuits  160   a - 166  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. The circuit  102   p  may be the same as or a variation of the circuits  102 - 102   l  and/or  102   m.    
     Each circuit  160   a - 160   n ,  162   a - 162   n  and  164   a - 164   n  may implement a scan cell circuit. The circuits  160   a - 160   n  may implement input-types of scan cells (e.g., an input isolation scan chain). The circuit  162   a - 162   n  may implement internal-types of scan cells (e.g., an internal scan chain). The circuit  164   a - 164   n  may implement output-types of scan cells (e.g., an output isolation scan chain). In some embodiments, one or more of the scan cell circuits may implement bidirectional-types of scan cells. In the normal operational mode, the scan cell circuits may be operational to pass data through from input interfaces to output interfaces. In the one or more test modes, some scan cell circuits may be loaded with test data serially, present the test data in parallel, capture new data, and serially present the captured data. Some scan cell circuits may implement the shift-only state. Other scan cell circuits may implement the transparent state. 
     The circuit  166  may implement a state controller circuit. The circuit  166  is generally operational to configure states of the circuits  160   a - 160   n ,  162   a - 162   n  and  164   a - 164   n  into different modes (or states) for both testing and normal operation. The modes generally include the internal test mode, the external test mode and a modular mode. The modes may be local to the circuit  102   p . Control of the modes may be provided via a JTAG (e.g., Joint Test Action Group) IEEE 1149.1 standard interface. Other test interfaces may be implemented to meet the criteria of a particular application. 
     In the internal test mode, the circuits  160   a - 160   n  may be commanded into the shift-only state to receive test data from an INTEST TCL. The circuits  162   a - 162   n  may be commanded into the transparent state to allow the circuit  102   p  to function as normal. The circuits  164   a - 164   n  may also be commanded into the transparent state to (i) allow the circuit  102   p  to function as normal and (ii) capture results data generated in response to the test data. Clock paths within the circuit  102   p  may be clock gated effectively to control test power. 
     Referring to  FIG. 11 , a block diagram of an example external test configuration of an embedded wrapped core  102   q  is shown. The circuit  102   q  may be an embedded wrapped core within any one or more of the circuits  100 - 100   g . The circuit  102   q  generally comprises the circuits  160   a - 160   n , the circuits  162   a - 162   n , the circuits  164   a - 164   n  and the circuit  166 . The circuit  102   q  may be the same as or a variation of the circuits  102 - 102   m  and/or  102   p.    
     In the external test mode, (i) the circuits  160   a - 160   n  may be commanded into the transparent state to receive results data at the input ports. The circuits  162   a - 162   n  may be commanded into a not active (e.g., NA) state because the circuitry internal to the circuit  102   q  may not be operational. The circuit  164   a - 164   n  may be commanded into the shift-only state to allow the circuit  102   q  to present test data at the output ports. Clock paths within the circuit  102   q  may be clock gated effectively to control test power. 
     Referring to  FIG. 12 , a block diagram of an example modular test configuration of an embedded wrapped core  102   r  is shown. The circuit  102   r  may be an embedded wrapped core within any one or more of the circuits  100 - 100   g . The circuit  102   r  generally comprises the circuits  160   a - 160   n , the circuits  162   a - 162   n , the circuits  164   a - 164   n  and the circuit  166 . The circuit  102   r  may be the same as or a variation of the circuits  102 - 102   p  and/or  102   q.    
     In the modular test mode, all of the circuits  160   a - 160   n ,  162   a - 162   n  and  164   a - 164   n  may be commanded into the transparent state such that the circuit  102   r  operates as normal. Therefore, any data received at the input ports by the circuits  160   a - 160   n  may be processed by the internal circuitry and the results presented at the output ports by the circuits  164   a - 164   n.    
     Referring to  FIG. 13 , a block diagram of a hierarchical test configuration of the embedded wrapped core  102   q  is shown. The circuit  102   q  may be embedded within a block (or circuit)  100   g . Several blocks (or circuits)  170   a - 170   n  may provide test data into the circuit  100   a . Several blocks (or circuits)  172   a - 172   n  may receive results data from the circuit  100   g . The circuit  100   g  may include a block (or circuit)  176 . The circuit  100   g  may be a variation of, or the same as the circuits  100 - 100   e  and/or  100   f . The circuits  170   a - 176  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. 
     The circuits  170   a - 170   n  and  172   a - 172   n  may implement scan cells in one or more scan chains. The circuits  170   a - 170   n  may be operational to transfer test data directly into the (outer wrapped core) circuit  100   g  and the (inner wrapped core) circuit  102   q . In the example, the circuit  170   a  may be connected directly to the circuit  160   a . The circuits  172   a - 172   n  may be operational to receive results data directly from the circuit  100   g  and the circuit  102   q . In the example, the circuit  172   a  may connected directly to the circuit  164   a.    
     The circuit  176  may implement a state controller circuit. The circuit  176  is generally operational to control the state of the scan chains and scan cells within the circuit  100   g , not including the scan chains and scan cells within the circuit  102   q . The circuit  176  may command the scan chains and scan cells into the transparent state, the shift-only state and/or the not active state. 
     The circuit  176  generally merges the isolation scan chains (e.g., circuits  160   a - 160   n  and  164   a - 164   n ) with the internal scan chains of the circuit  100   g  while the circuit  100   g  is in a respective internal test mode. The circuit  176  may merge the isolation scan chains of the circuit  102   q  with isolation scan chains of the circuit  100   g  while the circuit  100   g  is in a respective external test mode. Nested embedded hierarchical scenarios for the circuit  100   g  are generally described in Table I as follows: 
     
       
         
               
               
               
             
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                 TABLE I 
               
             
             
               
                   
               
               
                   
                 Circuit 100 g 
                 Circuit 102 q 
               
             
          
           
               
                   
                   
                 Input 
                 Output 
                   
                 Input 
                 Output 
               
               
                 Mode 
                 Intern. 
                 Isolate 
                 Isolate 
                 Intern. 
                 Isolate 
                 Isolate 
               
             
          
           
               
                 Circuit 
                 Circuit 
                 Chain 
                 Chain 
                 Chain 
                 Chain 
                 Chain 
                 Chain 
               
               
                 100 g 
                 102 q 
                 State 
                 State 
                 State 
                 State 
                 State 
                 State 
               
               
                   
               
               
                 Intern. 
                 Extern.  
                 TS 
                 SS 
                 TS 
                 NA 
                 TS 
                 SS 
               
               
                   
                 Intern. 
                 NA 
                 NA 
                 NA 
                 TS 
                 SS 
                 TS 
               
               
                 Extern. 
                 Extern. 
                 NA 
                 TS 
                 SS 
                 NA 
                 TS 
                 SS 
               
               
                 Intern. 
                 Modular 
                 TS 
                 SS 
                 TS 
                 TS 
                 TS 
                 TS 
               
               
                   
               
             
          
         
       
     
     The core wrapping generally supports design-for-test solutions to handle testing of SoCs by implementing and executing tests in the same hierarchical manner as the rest of the design steps (e.g., timing, physical design etc.). The core and the isolation wrappers may enable tests to be inserted and verified by concurrent teams working in different geographic locations on different cores in the SoC. The core and the isolation wrappers may also reduce test generation and test verification turnaround time. Test scheduling of the cores may be enabled to deal with issues of test power and defect isolation during debug effectively. Furthermore, hierarchical tests based on core wrapping may be enabled with the core and isolation wrappers. 
     The ability to embed (or integrate) wrapped cores into larger circuits generally has a variety of applications. For example, serialization/deserialization (e.g., SERDES) cores are commonly used across multiple designs under various usage scenarios. A SERDES core (or intellectual property) may be instantiated in a SoC at a top-level and/or inside other design blocks. For maximum reuse, the SERDES core may be designed once and used multiple times (e.g., 64 times) in a design and/or used in multiple designs. The SERDES core may be developed and delivered as a wrapped core to manage tester time and resources effectively using test scheduling. Use of the same core in a new core design where the new core is instantiated in another big design block generally results in a situation where both the SERDES core and the design block together may be wrapped cores. 
     In another example, a random access memory (e.g., RAM) core may be used as a stand-alone wrapped core or instantiated inside another design block. To maintain flow consistency, a single design flow may be performed where all RAM blocks are created as wrapped cores. The situation of a RAM block instantiated inside another design block that is also wrapped may be addressed by the logic and/or techniques. 
     In still another example, adoption of three-dimensional and two-and-a-half-dimensional packaging technologies generally results in logic partitioning approaches. The logic partitioning may result in a SoC divided into multiple dies (or chips or integrated circuits) that are later assembled into a single multi-dimensional package. The individual dies should be electronically isolated so that the dies may be tested stand-alone. To support the stand-alone testing, the dies may contain embedded design blocks that are wrapped resulting in situations having multiple embedded wrapped cores inside other wrapped cores or even multiple levels of nested wrapped cores. 
     The state controller circuits generally support design-for-test solutions to handle testing of the SoCs by implementing nested scan testing of hierarchical blocks. Sub-design blocks (e.g., wrapped cores) may be plugged into larger designs independent of the testing configurations of the larger designs. The nested scan testing may subsequently reduce test power consumption and improve verification times. The nested scan testing is generally suitable for where the design logic block (e.g., circuit  100   g ) is large and/or where the embedded logic block (e.g., circuit  102   q ) may be large. The nesting may provide isolated testing of the embedded logic blocks. Furthermore, the technique generally enables the same embedded logic blocks to be plugged into one or more designs with two or more testing configurations. 
     The functions performed by the diagrams of  FIGS. 2-13  may be implemented using one or more of a conventional general purpose processor, digital computer, microprocessor, microcontroller, RISC (reduced instruction set computer) processor, CISC (complex instruction set computer) processor, SIMD (single instruction multiple data) processor, signal processor, central processing unit (CPU), arithmetic logic unit (ALU), video digital signal processor (VDSP) and/or similar computational machines, programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software, firmware, coding, routines, instructions, opcodes, microcode, and/or program modules may readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). The software is generally executed from a medium or several media by one or more of the processors of the machine implementation. 
     The present invention may also be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic devices), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products), one or more monolithic integrated circuits, one or more chips or die arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
     The present invention thus may also include a computer product which may be a storage medium or media and/or a transmission medium or media including instructions which may be used to program a machine to perform one or more processes or methods in accordance with the present invention. Execution of instructions contained in the computer product by the machine, along with operations of surrounding circuitry, may transform input data into one or more files on the storage medium and/or one or more output signals representative of a physical object or substance, such as an audio and/or visual depiction. The storage medium may include, but is not limited to, any type of disk including floppy disk, hard drive, magnetic disk, optical disk, CD-ROM, DVD and magneto-optical disks and circuits such as ROMs (read-only memories), RAMS (random access memories), EPROMs (erasable programmable ROMs), EEPROMs (electrically erasable programmable ROMs), UVPROM (ultra-violet erasable programmable ROMs), Flash memory, magnetic cards, optical cards, and/or any type of media suitable for storing electronic instructions. 
     The elements of the invention may form part or all of one or more devices, units, components, systems, machines and/or apparatuses. The devices may include, but are not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptop computers, notebook computers, palm computers, personal digital assistants, portable electronic devices, battery powered devices, set-top boxes, encoders, decoders, transcoders, compressors, decompressors, pre-processors, post-processors, transmitters, receivers, transceivers, cipher circuits, cellular telephones, digital cameras, positioning and/or navigation systems, medical equipment, heads-up displays, wireless devices, audio recording, audio storage and/or audio playback devices, video recording, video storage and/or video playback devices, game platforms, peripherals and/or multi-chip modules. Those skilled in the relevant art(s) would understand that the elements of the invention may be implemented in other types of devices to meet the criteria of a particular application. 
     The terms “may” and “generally” when used herein in conjunction with “is(are)” and verbs are meant to communicate the intention that the description is exemplary and believed to be broad enough to encompass both the specific examples presented in the disclosure as well as alternative examples that could be derived based on the disclosure. The terms “may” and “generally” as used herein should not be construed to necessarily imply the desirability or possibility of omitting a corresponding element. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.