Abstract:
A method and apparatus for detecting and correcting single bit errors, detecting double bit errors, and detecting multiple bit errors within a nibble of a data field comprising 135 data bits and 9 check bits. 9 check bits are generated based on 135 data bits. The 9 check bits are appended to the data bits and the cumulative data field is checked for errors. An error detection syndrome is generated that indicates whether an error has occurred and whether the error is correctable. Check bit generation and error detection syndrome generation is accomplished based on the ordering in an ECC code matrix.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to error detection and correction, and more specifically to a 9 bit error correcting code (ECC) for correcting single bit errors, detecting double bit errors, and detecting nibble errors in a 144 bit field (135 data bits). 
     A number of schemes exist for correcting errors and detecting corruption of data during transport, for example, data transmitted between agents over a network or between an external memory and a processor&#39;s internal memory cache. One example of a scheme for detecting errors in a data field is parity. When data is transmitted, a parity generator appends an additional parity bit to the data, for example a 9th bit (parity) to a 8-bit byte, such that the overall parity of the 9-bit field is odd or even. The receiving entity checks the parity of the 9-bit field and an error is detected if the parity does not match the predetermined parity (odd or even). This only works well for detecting single bit errors in a word. 
     Another example of an error detection scheme is a CRC (cyclic redundancy check) checksum. When receiving a data field for the first time, a CRC generator divides the data bits by a generator polynomial G(x). The remainder of the division is the CRC checksum, which is written in two bytes and appended to the data. When the bit field is retrieved another time, the complete sequence of bits, including the CRC bits, will be read by a CRC checker. The complete sequence should be exactly divisible by the generator polynomial G(x). If they are not, an error has been detected. One example of a standard generator polynomial is G(x)=x 16  +x 12  +x 5  +1 which has the binary value 10001000000100001. This value has been defined by the CCITT and is often called CRC-CCITT. Implemented in hardware, the CRC check is an exclusive OR (XOR) of each bit position. 
     Closely related to the CRC are ECC codes (error correcting or error checking and correcting). ECC codes are sometimes referred to as EDC codes for error detecting and correcting. ECC codes are in principle CRC codes whose redundancy is so extensive that they can restore the original data if an error occurs that is not too disastrous. ECC codes are used, for example, for magnetic data recording with floppy or hard disk drives as well as for fail-safe RAM memory systems. A memory controller with embedded ECC logic, for example, is able to repair soft errors in DRAM chips caused by natural radioactivity in the air or tiny amounts of radioactive substances in the chip substrate. The ionizing effect of alpha-particles causes additional charges in the storage area of a DRAM memory cell which may distort the held value. 
     FIG. 1 depicts an example of a memory system 10 using embedded ECC logic (or CRC logic) for error detection and correction. Memory system 10 incudes bus interface 20, memory 25 and memory controller 30. Memory 25 is any memory device such as a floppy or a hard drive, for example. Memory system 10 is useful for transferring data between memory 25 and main memory or RAM (not shown), which is usually one or more banks of DRAM chips, for example. Data is transferred through controller 30 to and from bus interface 20 and controller chip 35. Bus interface 20 provides the connection to the main memory. Controller chip 35 determines the ECC (or CRC) bytes and provides any necessary formatting such as converting parallel submitted data into serial data and vice versa. ECC logic 40 (or CRC) generates and/or checks ECC bytes (or CRC bytes) being transmitted between bus interface 20 and memory 25. If an error is detected ECC (CRC) logic 40 generates an error detect signal to controller 35, and if the error is correctable, ECC logic 40 handles correction. Microprocessor 50 provides overall control, including synchronization, of controller chip 35 ECC (CRC) logic 40 and memory interface 60 of memory controller 30. Microcode ROM 55 provides the necessary instructions for microprocessor 50, and memory interface 60 provides the necessary interface to memory 25, depending on the memory type. 
     Conventional and modified Hamming SEC-DED codes (single error correction, double error detection codes) have been widely used to increase computer memory reliability. These codes generally require a large number of check bits and often require extensive circuitry to handle a complicated and lengthy decoding process. An improvement to the conventional Hamming SEC-DED codes that provides faster and better error-detection algorithm is given in Hsiao, M. Y., &#34;A Class of Optimal Minimum Odd-weight-column SEC-DED Codes&#34;, IBM Journal of Research and Development, Vol.14, No. 4, July 1980, which is hereby incorporated by reference. The Hsiao algorithm demonstrates a new way of constructing a class of SEC-DED codes that use the same number of check bits as the Hamming SEC-DED code but which is superior in cost, performance and reliability. 
     What is needed in the art is an algorithm for detecting and correcting single bit errors, detecting double bit errors, and detecting multiple bit errors within a nibble for 135 data bits and 9 check bits. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method and apparatus for detecting and correcting single bit errors, detecting double bit errors, and detecting multiple bit errors within a nibble of a data field comprising 135 data bits and 9 check bits. 
     According to an aspect of the invention a method of detecting errors in data is provided, comprising the steps of: a) generating a 9-bit check field for a 135-bit data field; b) appending the check field to said data field so as to create a 144-bit cumulative data field; c) transporting the cumulative data field to an agent; d) generating a 9-bit syndrome (S[8:0]) for detecting errors using the cumulative data field; and e) determining, based on the syndrome, whether the cumulative data field includes an error. 
     According to another aspect of the invention, a system for detecting errors in data is provided, the system comprising: a check field generator for generating a 9-bit check field for a 135-bit data field, wherein the check field is appended to the data field so as to create a 144-bit cumulative data field; a transport mechanism for transporting the cumulative data field to an agent; and an error detection circuit, coupled to the agent, for detecting errors in the cumulative data field, wherein the circuit generates a 9-bit error detection syndrome (S[8:0]) using the cumulative data field and wherein the circuit determines, based on the syndrome, whether the cumulative data field includes an error. 
     The invention will be further understood upon review of the following detailed description in conjunction with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts an example of a memory system using embedded ECC logic (or CRC logic); 
     FIG. 2 is a simplified block diagram of an ECC system according to an embodiment of the present invention; 
     FIGS. 3a-d shows an ECC code matrix according to an embodiment of the present invention; and 
     FIG. 4 depicts a table representing the error indication for a given generated syndrome according to an embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2 is a simplified block diagram of an ECC system according to an embodiment of the present invention. ECC generation circuit 100 includes ECC generator 110. ECC generation circuit 100 is coupled to ECC detection and correction circuit 120 by bus 150. ECC detection and correction circuit 120 includes ECC correction logic 130 and ECC checking logic (syndrome generator 140 and signal generator 160). ECC generation circuit 100 and ECC detection and correction circuit 120 can be included on the same chip, such as on a CPU chip, or they can exist as separate components. 
     ECC generation circuit 100 receives a data field and inputs the data field to ECC generator 110. ECC generator processes the data field and generates check bits according to the methodology as will be described below. The check bits are concatenated with, or appended to, the original data field on bus 150. 
     According to an embodiment of the present invention, the incoming data field comprises 135 data bits. ECC generator 110, in this embodiment, generates 9 check bits, which are concatenated with the 135-bit data field to make up a 144-bit cumulative data field. 
     ECC detection and correction circuit 120 receives the cumulative data field over bus 150. The cumulative data field is provided to syndrome generator 140 and the 135-bit data field is provided to ECC correction logic 130. As shown, ECC correction logic 130 and syndrome generator 140 and signal generator 160 are separate circuit components, but they may be implemented as one functional circuit element. 
     Syndrome generator 140 processes the received cumulative data and generates an error detection syndrome according to the methodology of the present invention as will be described below. The 9-bit syndrome is received by ECC correction logic circuit 130 and signal generator 160. Signal generator 160 reads the syndrome and generates an error signal if the syndrome indicates an error in the cumulative data field (135-bit data field+9-bit ECC check field). If the error is correctable, signal generator 160 generates a signal indicating that an error was detected and that it is correctable. As shown, syndrome generator 140 and signal generator 160 are separate circuit components, but they may be implemented as one functional circuit element. 
     ECC correction logic circuit 130 corrects any correctable errors in the data field. In one embodiment, ECC correction circuit 130 is provided with a connection to signal generator 160 so as to receive error detection signals. If no error is present, the data field passes through correction circuit 130 as output over bus 180. If an error exists and is correctable, correction circuit 130 corrects the error and outputs the corrected data field on bus 180. 
     ECC detection and correction circuit 120 is also coupled to control circuit 190. In one embodiment, control circuit 190 is a CPU trap generator for generating and executing a software trap. For example, if an error is detected, the error is logged to control circuit 190. If the error is correctable, the error is logged as a correctable error. If the error is not correctable, the error is logged as uncorrectable. In this case, a software trap is generated to kill any processing of the errored data and to control reloading or restoring a clean copy of the data from a main memory, for example. Copending application Ser. No. 08/880,369 (our file 16747-7200), filed Jun. 23, 1997, which is hereby incorporated by reference, shows one example of a CPU that includes a data transport/cache system with a software trap for which the present invention is useful. 
     In operation, the data field (135-bit) is received by ECC generator 110. The 9 check bits are generated by exclusive or&#39;ing (XOR) all the bits marked with a `1` in each row, excluding the check bit columns (i.e., just the 135 data bits). According to an embodiment of the present invention, the check bits are generated according to the ECC code matrix 200 shown in FIGS. 3a-d. That is, the XORing of the data bits is done according to the order of bits listed in ECC code matrix 300. In matrix 300, D[127:0] designate the 128 data bits, M[6:0] designate the 7 MTag bits (which are set to zero when generating ECC bits and when checking for errors), C[8:0] designate the 9 ECC check bits, and S[8:0] designate the syndrome bits generated from the data, MTag and ECC check bits (cumulative data field). Alternatively, the MTag bits are 35 replaced with data bits such that matrix 300 represents 135 data bits D[134:0], 9 ECC check bits C[8:0], and 9 syndrome bits S[8:0]. 
     ECC code matrix 300 is implemented in circuitry using RTL and is designed according to the following properties: 
     1) all columns have odd weight (an Odd weight column); 
     2) all possible one-weight columns (9) are used for check bits; 
     3) all possible three-weight columns (84) are used; 
     4) 51 of the possible 126 five-weight columns are used; and 
     5) the matrix is mirrored except for the two nibbles in the middle (i.e., bit positions [143:76] are a rotation of bit positions [0:67]). In other words, column 143 is the flipped image of column 0, column 142 is the flipped image of column 1, etc. . . . Column 143 corresponds to data bit 127 (D127) and column 0 corresponds to data bit 0 (D0). 
     Once the check bits have been generated by ECC generator 110, they are then stored with, or concatenated with, the data field resulting in the 144-bit cumulative data field on bus 150. Syndrome generator 140 of ECC detection and correction circuit 120 receives the cumulative data and generates a 9-bit error detection syndrome. Like the ECC bits, the syndrome bits are generated according to the ECC code matrix 200 shown in FIGS. 3a-d. That is, the cumulative data field is XORed according to the order of bits listed in ECC code matrix 300 to produce the 9-bit syndrome. If the weight of the syndrome is zero (i.e., all syndrome bits are zero), then no error has occurred in the cumulative data field. If the weight of the syndrome is greater than zero (i.e., one through nine) then an error has occurred. &#34;Weight&#34; is defined as the number of &#34;1&#34;s in a column. Whether the error is correctable or not depends on the weight and/or patterns as follows: 
     1) A zero weight syndrome means there is no error; 
     2) A correctable single bit error is indicated by the following: 
     Any 1- or 3-weight syndromes. 
     Any 5-weight syndromes following one of these patterns 
     i) S[2:0]=3&#39;b111 OR 
     ii) S[5:3]=3&#39;b111 OR 
     iii) S[8:6]=3&#39;b111 OR 
     iv) S[5:3]=3&#39;b011 AND S[2:0]=3&#39;b011 OR 
     v) S[8:6]=3&#39;b110 AND S[5:3]=3&#39;b110 
     3) Detection of 3-bit errors within a nibble: 
     Modulo 2 addition of any combination of 3 syndromes within a nibble (0-1-2, 0-1-3, 0-2-3, 1-2-3) yield either a 7-weight syndrome or a 5-weight syndrome which does not match any correctable 5-weight syndromes in the matrix. 
     4) Detection of 4-bit errors within a nibble: Modulo 2 addition of all 4 syndromes within the nibble result in a 6-weight syndrome. 
     A nibble, is defined to be a grouping of four consecutive data bits from left to right for each matrix. In other words, D[127:124] correspond to columns 0 to 3 of the first nibble, D[123:120] corresponds to columns 0 to 3 of the second nibble and so on. There are a total of 38 nibbles and D[3:0] is the last nibble. 
     5) Multiple bit error is detected by any even weight syndrome or a 7- or 9-weight syndrome or a 5-weight syndrome that doesn&#39;t satisfy the above correctable patterns. 
     For example, if the syndrome listed in column D66 of matrix 300 (FIG. 3b) is generated, a five-weight error with S[2:0]=3&#39;b111 has occurred. This represents that a single bit correctable error has occurred in data bit 66. Similarly, if the syndrome listed in column D57 is generated, then a five-weight correctable single bit error of the type S[5:3]=3&#39;b011 AND S[2:0]=3&#39;b011 has occurred. 
     FIG. 4 depicts a table 400 representing the error indication for a given generated syndrome according to an embodiment of the present invention. M indicates a multi-bit uncorrectable error, an integer indicates the data bit number (correctable), and CO through C8 indicates a check bit number (correctable). For example, suppose a single bit error in data bit D81 has occurred. Syndrome generator 160 will generate a syndrome according column D81 of FIG. 3. S[3:0] of column D81 represents the value 8, and S[8:4] represents the value 18. Thus, checking column 8 and row 18 of table 400 indicates that a single bit error has occurred at D81. Supposing a different syndrome is generated with the values S[3:0]=5 and S[8:4]=1d, referencing table 400 at column 5, row 1d indicates that a multi-bit error has occurred. 
     The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art upon reference to the present description. It is therefore not intended that this invention be limited, except as indicated by the appended claims.