Abstract:
A method for transmitting logical information from a transmitter to a receiver via a single line, the receiver being connected to the transmitter by the line, the receiver placing a first signal on the line and the first signal being made up of alternating recessive and dominant levels, the transmitter placing a second signal on the line and the second signal being superposed on the line by the transmitter at least in the segments in which the first signal has a recessive level, the second signal being made up of a sequence of recessive and dominant levels, and the receiver determining from the second signal the logical information that is to be received.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a circuit and method for communicating via a single line. 
       BACKGROUND INFORMATION 
       [0002]    From the literature, various methods and protocols are believed to be understood for communication between integrated circuits, for example for the purpose of configuration. 
         [0003]    Serial interfaces such as SBI transmit data serially but regularly use a plurality of lines, in particular using a further line for synchronization in addition to the data line. Thus, in the case of the SPI interface, each participant is connected to the following three common lines: SDO (Serial Data Out) or MISO (Master In Slave Out), SDI (Serial Data In) or MOSI (Master Out Slave In), and SCK (Serial Clock). In addition, the participants are connected to a common ground. 
         [0004]    The interface of the I2C bus, discussed for example in WO 03/005211 A2, is made up of two line terminals and a ground connection, with the possibility of selectively addressing individual participants on the bus. 
         [0005]    Patent document US 2008/0282005 A1 discusses a method for communication between integrated circuits that is placed on an existing physical layer of the OSI model, and additionally provides for example configuration information in the associated communication layer. In this way, additional connections are saved. 
         [0006]    Patent document DE 0588274 A1 discusses a further method for communication on a line. The transmitter releases the communication line, and the receiver sends pulses that the transmitter counts. At the same time, the receiver checks whether the pulse was correctly outputted on the line. When the number that is to be transmitted is reached, the transmitter again blocks the transmission line. The receiver knows the number of pulses and has thus received the number. 
         [0007]    Patent document U.S. Pat. No. 5,668,716 A discusses a design for single-wire communication using an adapter that converts the signals onto a serial two-wire interface. 
         [0008]    Patent document GB 2295039 A discusses a serial interface having a line that presupposes that the clock lines of both circuits are coupled and, if warranted, terminated in matching fashion. 
         [0009]    In U.S. Pat. No. 5,864,872 A, a serial communication via a line is discussed in which the line is held high by the receiver and the transmitter then, in a defined time interval, either pulls it to ground or leaves it in its high state. The receiver checks the status of the line and recognizes whether 0 or 1 was sent. 
       SUMMARY OF THE INVENTION 
       [0010]    The exemplary embodiments and/or exemplary methods of the present invention describe an interface for communication between two integrated circuits on a single line, e.g. for the transmission of configuration information during the initialization of a control device. 
         [0011]    A method as described here can be used for the transmission of configuration data, e.g. for the configuration of CAN transceivers or other integrated circuits that do not have their own non-volatile memory and therefore must receive configuration data when they are switched on. 
       ADVANTAGES OF THE INVENTION 
       [0012]    Advantageously, in the method according to the present invention a transmitter transmits logical information to a receiver via a single line by which the receiver is connected to the transmitter. 
         [0013]    The receiver places on the line a first signal made up of alternating recessive and dominant levels, and the transmitter places a second signal on the line, the second signal being superposed on the line by the transmitter at least in the segments in which the first signal has a recessive level, and the second signal being made up of a sequence of recessive and dominant levels. This has the advantage that both the transmitter and the receiver can access the bus and the receiver can determine from the second signal the logical information that is to be received. 
         [0014]    In an advantageous realization, as logical information configuration information is transmitted for the initialization of a control device or component or of a bus connection unit. 
         [0015]    In a particular realization that is easy to represent, the first signal is made up of a sequence having a prespecified or prespecifiable number of rectangular pulses, the duration of the recessive line level and/or the duration of the dominant line level being approximately constant within the sequence. 
         [0016]    It is advantageous if the transmitter begins with the superposition of the second signal after receiving a prespecified or prespecifiable number of recessive and/or dominant levels of the first signal. 
         [0017]    An advantage of the represented invention, differing from I2C and SPI, is that only a single line is required, and no use is made of already-existing protocols or communication layers. 
         [0018]    In addition, it is advantageous that it requires no additional clock or synchronization lines for the realization of the method, thereby saving costs. 
         [0019]    The clock of both circuits does not require any synchronization, which is a further advantage with regard to usability, robustness, and expense of use of the method. Rather, the transmission rate, which according to the exemplary embodiments and/or exemplary methods of the present invention is specified by the receiver, may fluctuate during the transmission. This is advantageous because no requirements are made on a clock pulse generator used for the communication. 
         [0020]    The transmission rate of the receiver also need not be known to the transmitter, thus advantageously reducing the configuration outlay for the creation or setting up of the communication. 
         [0021]    The exemplary embodiments and/or exemplary methods of the present invention thus allow a simple, low-cost, and robust realization of a single-wire interface, e.g. for the configuration of a component or control device, without the requirement of a synchronization, configuration, or setting of the transmission clock pulse. In the sense explained, the interface is self-synchronizing, including to temporally variable transmission rates. 
         [0022]    In the following, the exemplary embodiments and/or exemplary methods of the present invention are explained in more detail on the basis of the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  shows an example of the transmission data of the two participants of the method according to the present invention. 
           [0024]      FIG. 2  schematically shows an example of a circuit for carrying out the method according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    In the following, exemplary embodiments are described of the method and device according to the present invention. These concrete examples are used to explain the realization of the invention, but do not limit the scope of the basic idea of the invention. 
         [0026]    One aspect of the method according to the present invention is the synchronization of the two circuits on the transmission line, the synchronization taking place via the transmission of a clock signal by the receiver. This is shown as an example in  FIG. 1 . In the upper part of the drawing, the signal sent onto the line by the transmitter is shown, and in the lower part the signal sent by the receiver is displayed opposite. The time axes of the two representations agree with one another. 
         [0027]    As is shown in  FIG. 1 , the receiver module sets an approximately rectangular clock signal on the transmission line. The transmitter module detects this clock signal and sets its signal to be transmitted in each of the recessive phases of the clock signal coming in from the receiver. Analogously to the CAN bus, the transmit signals of the two modules are made up of dominant and recessive signals. This means that, when there is simultaneous transmission by a plurality of modules on the line, and thus in the present case simultaneous transmission by the transmitter and receiver, then due for example to the physical boundary conditions of the signal generation the dominant signal “wins.” The bus remains at the recessive level only if both participants, i.e. transmitter and receiver, send a recessive signal. If at least one participant sends a dominant signal, the bus is at dominant level. If the dominant line level is interpreted as a logical TRUE condition and the recessive line level is interpreted as a logical FALSE condition, then the signal actually present on the line is an OR linkage of the two signals sent by transmitter and receiver. 
         [0028]    In this way, the transmitter sends its data bit-by-bit in the gap between the dominant clock bits of the receiver, these data representing an item of logical information that is to be transmitted to the receiver. As already described, the transmitter observes the transmission line and places its bits to be transmitted in the “recessive gaps” of the clock signal. In the recessive phases of the clock signal that the receiver module sends, the receiver module checks the line for a change of edge from recessive to dominant. If the receiver module detects such a change of edge, this is for example interpreted as a logical one. If the receiver does not measure a change of edge up to the beginning of the next dominant clock bit, this is evaluated as a transmitted logical zero. 
         [0029]    Depending on the physical realization of the bus and the particularities of the transmission protocol, recessive bits may also be represented or interpreted as one and dominant bits as zero (inversion). The bits transmitted from the transmitter to the receiver can be put together according to any arbitrary method to form data words, can be used to describe registers in the receiver, or can be processed and/or stored in some other way in the receiver. 
         [0030]    As shown in  FIG. 1 , the clock signal can be made up of equally long dominant and recessive phases, but a clock signal is also possible in which the dominant phases are shorter or longer than the recessive phases. An irregular signal having alternating dominant and recessive levels is also suitable for the method, because the receiver always knows whether an observed dominant bus level was set by the receiver or by the transmitter. Only this factor is decisive for whether the bit is a bit belonging to the logical item of information or is an element of the clock signal, i.e. a clock bit. 
         [0031]      FIG. 2  shows, as an example, the schematic configuration of the associated circuit, based on an open-drain interface having pull-up resistors: via the represented pull-down transistors  203 ,  206 , transmitter  201  or receiver  204  can pull the transmission line to ground. If this does not happen, at least one pull-up resistor pulls the line to potential VDD 1 . Here the state “potential of the transmission line is ground” is dominant, and the state “potential of the transmission line is VDD 1 ” is recessive. 
         [0032]    Receiver  204  produces the clock signal in that digital logic unit  205  that it contains periodically changes pull-down transistor  206  between blocking and transmission. In the blocking phase (when the transmission line is raised to potential VDD 1 ), transmitter  201  can pull the line to ground by opening its pull-down transistor  203  using digital logic unit  202 . 
         [0033]    This change of the line level, caused by transmitter  201 , is recognized by receiver  204  as a logical one for example at times during which it interprets the absence of the change of line level in the blocking phase of its pull-down transistor  206  as a logical zero. As already mentioned, the representation of one and zero can also be inverted. 
         [0034]    The method or the circuit can be used to transmit logical information, in particular configuration information, for initializing a control device or component or a bus connection unit during a system start, the information being transmitted to this device or component or unit. That is, in this case after activation the receiver can begin to continuously specify the clock signal, and can wait for the scattering in of dominant bits by the transmitter. When the expected or required number of bits has been received, the receiver can terminate the transmission of the clock signal. 
         [0035]    However, the method can of course also be realized in such a way that the receiver continuously transmits a clock signal. Also possible is a transmission as needed, i.e. in such a way that the receiver begins to send the clock signal whenever it requires a particular item of information from the transmitter. 
         [0036]    In the continuous case, the transmitter can begin the transmission of the logical information for example at a time selected by the transmitter itself, or also immediately after having being switched on and having determined the presence of the clock signal from the receiver on the line. If the transmitter does not transmit continuously, but rather for example in packets or in an event-controlled manner, then it makes sense that at the beginning of the transmitted logical information there is transmitted an item of packet start information, for example a leading dominant bit or also a sequence of defined bits, in order to signal to the receiver that a transmission is beginning. It is also conceivable that at the beginning of the logical information there is additionally transmitted an item of length information that indicates how many following logical bits are to be evaluated by the receiver. 
         [0037]    In the case in which the receiver places the clock signal onto the line only as needed, it makes sense for the transmitter to begin its transmission of the logical information when it has received a number of clock signals that is prespecified, or is prespecifiable, or also is not determined in more detail. It can terminate its transmission when the data provided for transmission have been completely transmitted. In this case, the receiver can resume the sending of the clock signal at a prespecified, prespecifiable, or not more precisely determined point in time or number of clock signals after it has received the last expected datum.