Abstract:
The present invention provides a method and device for electrostatic discharge (ESD) protection of a display. A first terminal is coupled to an electrostatic source. A second terminal is coupled to the electronic element. A circuit conductively couples the first terminal to the second terminal, wherein the circuit comprises a plurality of signal lines couple in parallel between the first and the second terminals, and a plurality of ESD units each couple to a signal line.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the invention  
         [0002]     The present invention relates to a method and device for ESD protection, and more particularly to a method and device for raising ESD endurance of a display.  
         [0003]     2. Description of the Related Art  
         [0004]     ESD management is an increased reliability issue in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) due to technology scaling and high frequency requirements. For radio frequency (RF) ICs, on-chip ESD protection design suffers from several limitations, such as low parasitic capacitance, constant input capacitance, and insensitivity to substrate coupling noises. In order to fulfill these requirements, diodes are commonly used for ESD protection in I/O circuits.  
         [0005]     In the above, the power-rail ESD clamp circuit is important for improving the ESD protection in IC products, but must be triggered efficiently during ESD events.  
         [0006]     Thin film transistor (TFT) of low temperature poly-silicon (LTPS) has higher mobility and lower threshold voltage, but displays composed LTPS-TFT accumulate significant charge, posing danger to transistors of internal driving circuits. Therefore, an ESD protection circuit is necessary for an LTPS-TFT display.  
         [0007]      FIG. 1  shows a conventional ESD protection circuit for an LTPS-TFT display, wherein P-type metal-oxide-semiconductor (PMOS) transistors MP i-j  and N-type metal-oxide-semiconductor (NMOS) transistors MN i-j  are utilized to discharge an ESD pulse from an input signal terminal T i  to a power line with a supply voltage of V dd  or V ss , preventing the ESD pulse from entering a signal terminal T o  and damaging the internal driving circuit.  
         [0008]     Generally, the conventional ESD protection circuit is disposed as a “lateral layout” as shown in  FIG. 2 , wherein the ESD protection units, such as the PMOS transistors MP i-j  and the NMOS transistors MN i-j , are disposed laterally to avoid the input signal line T i -T o . In addition to the low area-efficiency of the lateral layout, due to the various distances from each PMOS transistor MP i-j  or each NMOS transistor MN i-j  to the input signal line T i -T o , the MOS transistors are switched on gradually as the current passes, one by one. For example, the MOS transistors (MP i , MN i ) near the input signal lines T i -T o  are switched on earlier than the MOS transistors (MP j , MN j ) farther from the input signal line T i -T o . The asynchronous switching compromises the ESD protection ability of the circuit, whereby damage of a near-end MOS transistor can severely affect the performance of the ESD protection circuit.  
       SUMMARY OF THE INVENTION  
       [0009]     Accordingly, the present invention provides a novel layout of ESD protection circuits for a display with enhanced protection and increased the utility rate of the peripheral area. Generally, the present invention provides a circuit configuration for ESD protection of electronic elements by coupling the input terminal To for static discharge to the input terminal Ti to internal circuits of the electronic elements, in a manner in which ESD protection units are arranged in parallel between To and Ti.  
         [0010]     To achieve the above objects, the invention provides an electrostatic discharge (ESD) protection device for an electronic element, which comprises a first terminal coupled to an electrostatic source, a second terminal coupled to the electronic element, a circuit conductively coupling the first terminal to the second terminal, wherein the circuit comprises a plurality of signal lines coupled in parallel between the first and second terminals, and a plurality of ESD units each coupled to a signal line.  
         [0011]     The invention further provides an electrostatic discharge (ESD) protection method of a display, which comprises dividing a first input signal line into a plurality of second input signal lines, joining the plurality of second input signal lines to form a third input signal line, coupling to an array circuit of the display, and respectively disposing an ESD protection unit corresponding to each of the plurality of second input signal lines, whereby an ESD pulse from the first input signal line is divided among the plurality of second input signal lines and discharged by the ESD protection unit.  
         [0012]     According to the invention, the ESD protection unit may include a diode and/or a metal-oxide-semiconductor transistor, and preferably couples to a power line with a power supply voltage, or a reference voltage.  
         [0013]     The display may be an amorphous-silicon thin-film-transistor (TFT) liquid crystal display ,low-temperature poly-silicon (LTPS) TFT liquid crystal display or organic light emitting display (OLED), and the third input signal line may be electrically connected to a gate line or a date line of the display.  
         [0014]     The ESD pulse divided among the plurality of second input signal lines enables the ESD protection unit and may be discharged to the power line with the power supply voltage, or the power line with the reference voltage.  
         [0015]     The second input signal line preferably has a line width less than that of the first input signal line.  
         [0016]     The ESD protection device of the invention preferably further comprises a dividing part between the first input signal line and the second input signal lines, and a joining part between the second input signal lines and the third input signal line, wherein both the dividing part and the joining part have a line width greater than that of the first input signal line and the sum of the second input signal lines.  
         [0017]     Accordingly, an ESD protection method and device are presented by modifying the layout of the ESD protection circuit. An input signal line is separated into a plurality of sub-signal lines, and an ESD protection unit is correspondingly disposed around each of the sub-signal lines to form an ESD protection circuit, thereby increasing the utility rate of the peripheral area, furthering the switching speed of each ESD protection circuit, and enhancing the ESD protection ability of the display. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0018]     The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0019]      FIG. 1  shows conventional ESD protection circuits for a liquid crystal display;  
         [0020]      FIG. 2  shows the layout of the conventional ESD protection circuits of  FIG. 1 ;  
         [0021]      FIG. 3  shows the inventive layout of the ESD protection circuits in accordance with one embodiment of the present invention;  
         [0022]      FIG. 4  is a schematic diagram of a display incorporating the inventive ESD protection circuit configuration in accordance with one embodiment of the present invention; and  
         [0023]      FIG. 5  is a schematic diagram of an electronic device, incorporating a display having the inventive configuration of ESD protection circuits in accordance with one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]      FIG. 3  shows the inventive layout of the ESD protection circuits in accordance with one embodiment of the present invention.  
         [0025]     The ESD protection units of the invention may be fabricated before or after formation of the input signal lines. In the embodiment, ESD protection units of PMOS transistors MP 1 -MP n  and NMOS transistors MN 1 -MN n , equivalent to diodes, are fabricated after input-signal-line fabrication. In addition, diodes may be applied rather than the MOS transistors (MP 1 -MP n  and MN 1 -MN n ).  
         [0026]     Accordingly, the ESD protection device of the embodiment comprises the first input signal line T 1 , the second input signal lines T 2  separated from the first input signal line T 1 , the third input signal line T 3  joined to the second input signal lines T 2 , and a plurality of ESD protection units (MP i -MP n  and MN 1 -MN n ) corresponding to the second input signal lines T 2 , whereby an ESD pulse from the first input signal line T 1  is divided among the second input signal lines T 2  and discharged by the ESD protection units (MP 1 -MP n  and MN 1 -MN n )  
         [0027]     Furthermore, as shown in  FIG. 3 , the second input signal lines T 2  are disposed in parallel, each having a line width less than that of the first input signal line T 1 . A dividing part B 1 , between the first input signal line T 1  and the second input signal lines T 2 , has line width exceeding that of the first input signal line T 1  and the sum of the second input signal lines T 2 , providing an adequate area for uniformly dividing the ESD pulse among the second input signal lines T 2  and their corresponding ESD protection units (MP 1 -MP n  and MN 1 -MN n ). In addition, a joining part B 2 , between the second input signal lines T 2  and the third input signal line T 3 , has line width exceeding that of the first input signal line T 1  and the sum of the second input signal lines T 2  to provide an adequate area.  
         [0028]     Moreover, the ESD protection units (MP 1 -MP n  and MN 1 -MN n ), respectively disposed around the second input signal lines T 2 , form a compact layout to increase the utility rate of the periphery. The ESD protection units (MP 1 -MP n  and MN 1 -MN n ), coupling to the second input signal lines T 2 , are also coupled to a power line with a power supply voltage (V dd  or V ss ). The ESD protection units (MP 1 -MP n  and MN 1 -MN n ) may also be coupled to a power line with a reference voltage, such as ground (not shown).  
         [0029]     With the inventive ESD protection device disposed prior to an input signal line, a liquid crystal display, particularly an LTPS liquid crystal display, is protected from ESD damage.  
         [0030]     Thus, electrostatic charges are divided from the first input signal line T 1  into the second input signal lines T 2  and the ESD protection units (MP 1 -MP n  and MN 1 -MN n ). The ESD protection units (MP 1 -MP n  and MN 1 -MN n ) are then switched on and the electrostatic charges discharged to the power lines, protecting the internal driving circuit from damage.  
         [0031]     According to the inventive ESD protection method, a first input signal line T 1  is divided among a plurality of second input signal lines T 2  in parallel, each having a line width less than that of the first input signal line T 1 . The second input signal lines T 2  are then joined to form a third input signal line T 3 , coupling to an internal driving circuit of the LCD (not shown). ESD protection units (MP 1 -MP n  and MN 1 -MN n ) are then respectively formed corresponding to each of the second input signal lines T 2 , whereby an ESD pulse from the first input signal line T 1  is divided among the second input signal lines T 2  and discharged by the ESD protection units (MP 1 -MP n  and MN 1 -MN n ).  
         [0032]     The inventive ESD protection method and device are applicable to displays using TFTs as switching elements, such as amorphous-silicon TFT-LCDs, LTPS TFT-LCDs or OLEDs. The third input signal line T 3  is coupled to a gate line or a data line of the liquid crystal display. ESD pulses entering the first input signal line T 1  are divided among the second input signal lines T 2  and the ESD protection units (MP 1 -MP n  and MN 1 -MN n ). The ESD protection units (MP 1 -MP n  and MN 1 -MN n ) are then switched on and the ESD pulse discharged to the power lines, away from the second input signal lines T 2 , and is prevented from entering the third input signal line T 3 , such that gate line or the data line of the LCD is protected from ESD damage.  
         [0033]      FIG. 4  is a schematic diagram of a display incorporating the inventive ESD protection circuit configuration in accordance with one embodiment of the present invention. The ESD protection devices  4  can be couple to a display panel  1 . Each ESD protection device  4  comprises a first terminal coupled to an electrostatic source and a second terminal coupled to each gate line of the display panel  1 . The display panel can be coupled to a controller, forming a display device as shown in  FIG.3 . The controller can comprise a source and a gate driving circuits (not shown) to control the display panel  1  to render image in accordance with an input.  
         [0034]     It should be noted that each gate line or data line of the display panel  1  requires an ESD protection unit separately as in  FIG. 3 .  
         [0035]      FIG. 5  is a schematic diagram of an electronic device  6 , incorporating a display having the inventive configuration of ESD protection circuits in accordance with one embodiment of the present invention. An input device  5  is coupled to the controller  2  of the display device shown in  FIG. 4  can include a processor or the like to input data to the controller  2  to render an image. The electronic device  6  may be a portable device such as a PDA, notebook computer, tablet computer, cellular phone, or a desktop computer.  
         [0036]     The foregoing description has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.