Abstract:
Phase compensation in a dual-channel analog-to-digital converter (ADC) is accomplished by holding conversion results in programmable length registers for controllable time periods. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing, is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay mechanism. A differential delay equal to ΔI-ΔV is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADC&#39;s.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part application of patent application Ser. No. 09/405,370 entitled “ Energy - to - Pulse Converter System, Device and Methods wherein the Output Frequency is greater than the Calculation Frequency, and having Output phasing , having inventors Doug Pastorello and Eric T. King, and having been filed on Sep. 24, 1999, and is related to patent application Ser. No. 09/484,866, entitled “ A Delay Correction System and Method for a Voltage Channel in a Sampled Data Measurement System ” having inventors Eric T. King and Doug Pastorello and having been filed on Jan. 18, 2000 and each incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention generally relates to analog-to-digital converters and more particularly to phase equalization in a dual-channel analog-to-digital converters 
     2. Description of Related Art 
     Energy calculations for electric power loads are made by power meters of all kinds. Until recently, electromechanical power meters were exclusively employed in millions of homes and businesses worldwide to monitor the amount of power consumption by a user at a particular location. Such monitoring allows the electricity/power entities to monitor the power (energy) usage of the user for proper billing, load monitoring, servicing, etc. In electromechanical power meters, a series of electrical components as well as mechanical disks, gears, indicators, and dials are used to convert voltage and current into energy. In addition to low accuracy, these electromechanical power meters also require periodic manual calibration and check-ups by field service technicians to ensure that they are operating properly. Electronic meters have recently begun to replace electromechanical meters in monitoring power consumption for homes and businesses. In general, because they rely on digital rather than electromechanical components, electronic meters are more accurate and reliable than their counterpart electromechanical meters. Additionally, through networking, electronic meters allow calibration and monitoring check-ups to be performed from a remote location such as a central office thereby greatly reducing the on-site visits by field service technicians. Finally, due to the deregulation of the electricity market already underway in the United States and Europe, broader range of information on consumers&#39; power use is needed by competing power suppliers for customizing the billing and servicing plan for each consumer. Due to these advantages, in the near future, electronic meters will likely replace all of the 60 million electromechanical power meters that are in use today in industrial and residential applications. In general, electronic power meters uses sensors such as transformers, etc. to measure the analog current and voltage from the power lines which are then converted into digital words using analog-to-digital converters (ADCs). A power value P is then computed using the converted digital current words and converted digital voltage words according to the equation P=V*I wherein V represents voltage and I represents current. However, the measurement process and conversion process may introduce delays into signals carrying the digital voltage words and digital current words which can cause the signals to be out of phase relative to each other. One technique to equalize the phase change involves making compensation to the sensors. This technique, however, may be expensive because it requires making physical adjustments to passive devices. Another technique to equalize the phase change involves scaling the power output value by a predetermnined scaling factor after it has been computed. This technique is based upon the power equation P=I*V*cosφ that relates voltage V, current I, and the phase angle φ between I and V. According to this technique, the power value P is divided by the factor cosφ to compensate for the phase difference between I and V. This requires prior knowledge of the phase angle φ. However, the phase angle φ is a function of frequency which may drift over time thereby making the scaling factor cosφ a variable. As such, the power value computed using a fixed scaling factor cosφ may be inaccurate under this technique. In addition, an actual phase angle (φ) between the current and voltage may exist as the load becomes less resistive. This also will produce an error in the computed power value. 
     The energy consumed by a particular electric power load can be calculated according to the following formulas:        E   =       ∫   ti   tf            P        (   t   )               t                                
     and        E   =       ∫   ti   tf            I        (   t   )            V        (   t   )               t                                
     The energy calculation can be carried out in a sampled data domain, permitting digital multiplication. The measurement system, including sensors and analog-to-digital converters (ADCs), contributes delays of ΔV and ΔI to the voltage and current channels. These delays produce an error in the energy calculation, as illustrated in the waveforms of FIG.  2 . The error results in a difference in calculated watt-hours between watt-hours calculated with and without delays. In the past, the sample clock for the ADCs has been shifted, making necessary the design of a complex clock generator, not only for the ADCs but for any filters in the signal paths. For example, see U.S. Pat. No. 5,017,860. 
     SUMMARY OF THE INVENTION 
     According to the present invention, phase compensation in a dual-channel analog-to-digital converter (ADC) is accomplished by holding conversion results in programmable length registers for controllable time periods. According to one embodiment of the present invention, a dual-channel ADC includes first and second delta-sigma modulators and digital filters, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. Further according to the present invention, an energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. In particular according to the present invention, the digital data subject to filter processing is delayed by predetermined amounts. According to the present invention, the dual-channel ADC is provided with a programmable channel delay mechanism. With such a controllable delay mechanism, there is no need to provide off-chip compensation in sensors used to receive analog signals of interest. Such an off-chip mechanism is costly and requires burdensome physical adjustment of passive devices. Further, there is no need to scale the energy output after it has been calculated. Calculations according to the present invention moreover are further not limited to just one frequency. According to the present invention there is further no need to shift the sample clock of the ADCs, which would require a complex clock generator not only for the ADC components but for any filters in the signal paths of interest. Further, according to the present invention, a differential delay equal to ΔI-ΔV is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADC&#39;s. Thus according to the present invention, the analog signals are left alone and not adjusted. Instead, the data which comes out of the analog circuitry is treated as normal, and delay circuitry is connected between the filter circuitry in the present embodiment. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a diagram of a continuous time measurement system according to the present invention, including sensors and ADCs, in which the measurement system contributes delays of ΔV and ΔI to the voltage and current channels; 
     FIG. 1B is a diagram of a sampled data measurement system according to the present invention, including sensors and ADCs, in which the measurement system contributes delays of ΔV and ΔI to the voltage and current channels; 
     FIGS. 2A through 2F are diagrams of waveforms showing the errors in calculations resulting from delays of ΔV and ΔI in the voltage and current channels of the ADC system; 
     FIG. 3 is an uncorrected voltage channel in an ADC. converter system, according to the prior art; 
     FIG. 4 is an uncorrected current channel in an ADC converter system, according to the prior art; 
     FIG. 5 is a corrected voltage channel in an ADC converter system having first through third clock speeds (e.g., HICLK, MDCLK, and LOCLK), according to the present invention; 
     FIG. 6A is an uncompensated signal process flow according to the present invention; 
     FIG. 6B is a chart showing the phase delay that can be introduced by various clocks. It is expressing the relationship of selected first through third DCLK values and first and second selected signal frequencies (fsig), to respective phase/HICLK, phase/MDCLK, and phase/LOCLK values; 
     FIG. 7A is a phase compensation system according to the present invention; 
     FIG. 7B is a chart relating values of B3B2B1B0 to Y 2 , Y 1 , total DELAY, and the delay normalized to B=0 (NORM); 
     FIG. 8A shows the delay and decimation of the voltage channel signal path according to the present invention; and 
     FIG. 8B shows the delay and decimation of the current channel signal path according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to FIG. 1A, there is shown a block diagram of a continuous time measurement system  3  with lumped delay to represent delays in sensors and ADCs, shown as ΔV and ΔI in the voltage and current channels. In particular, the continuous time measurement system  3  includes a voltage channel delay  4 , a current channel delay  5 , a multiplication node  6 , and an integrator  7 . The multiplication node  6  is connected to the outputs of the voltage and current blocks  4  and  5 . The integrator  7  is connected to the output of the multiplication node  6 . The integrator  7  produces an output energy (E) signal value. 
     Referring now to FIG. 1B, there is shown a diagram of a sampled data measurement system  13  according to the present invention, with lumped delays V and I to represent delays in the sensors and ADCs of to the voltage and current channels. In particular, the sampled data measurement system includes a voltage channel delay  14 , respectively first and second sampling switches  18  and  19 , a frequency source  20  connected to said first and second sampling switches  18 ,  19 , a current channel delay  15 , a multiplication node  16 , and a summation block  17 . The multiplication node  16  is connected to the outputs of the voltage and current channel delays  14  and  15 . The summation block  17  is connected to the output of the multiplication node  16 . The summation block  17  produces an output energy (E) signal value based upon sampled data. 
     Referring now to FIGS. 2A through 2F are diagrams of waveforms showing the errors in energy calculations resulting from delays of ΔV and ΔI in the voltage and current channels of the ADC. In particular, FIG. 2A is a diagram of an undelayed voltage and current signal according to a sinusoidal format. FIG. 2B are delayed current and voltage signals according to the format of the undelayed sinusoidal indicated in FIG.  2 A. FIGS. 2C and 2D are corresponding undelayed and delayed power curves. Finally, FIGS. 2E and 2F are corresponding undelayed and delayed energy curves. 
     Referring now to FIG. 3, there is shown a phase compensation system  29  according to the present invention, in which programmable delay is added in two places, d 1  and d 2 . In FIG. 3, there is shown a phase compensation system  29  according to the present invention, including sensors and ADCs, in which the delays of ΔV and ΔI to the voltage and current channels are compensated. In particular, the phase compensation system  29  includes a voltage delay  34 , a current delay  35 , first and second delta-sigma analog-to-digital converters respectively  47  and  48 , first and second adjustable delay registers  39  and  42  respectively, first and second decimators  40  and  41 , a current delay  35 , a delay register  43 , a multiplication node  37 , and a summation block  38 . The delta sigma analog to digital converters  47 ,  48  convert analog signals received from the respective voltage and current delays  34 ,  35 , at a first frequency F. After conversion, the frequency is stepped down by a factor of  64  by respective decimators  40 ,  41 . In particular, the frequency is stepped down by the factor of  64  between delay elements  39  and  42 . To compensate for time delay, only one path needs to be subject to compensation. The voltage channel is selected as its resolution is not as great at the current channel, therefore requiring less silicon area for the delay registers. Programmable delay is added in two places, d 1  and d 2 , respectively  39  and  42 . The clock rate for these delay cells  39 ,  42  is f and f/64 respectively. The multiplication node  37  is connected to the outputs of the second delay element  42  and the output of the delay register  43 . The summation block  38  is connected to the output of the multiplication node  37 . The summation block  38  produces an output energy (E) signal value based upon sampled data. The two phases corresponding to the two channels are substantially equal but adjustments are made according to the present invention to at least one selected channel to enable calibrating out errors that are externally derived with respect to the ADC. According to another embodiment of the present invention, first and second ADCs use different filters, each of which is provided with a separate adjustment delay on at least one channel for each filter to ensure phase adjustment according to the present invention. External compensation for the chip (e.g., the sensor) can be provided according to the present invention. Once E is calculated, a predetermined compensation factor can be used to compensate the phases according to one embodiment of the present invention. The following equation relates energy to I and V in view of the delay between current and voltage: E=I*V*Cosφ where φ is the angle between I and V. In these filters, there is a fixed amount of time that one channel is delayed relative to the other channel. Depending on the phase error in the sensor, at one frequency, voltage and current are in phase, while at another frequency, voltage and current are at different phases. The oscillation frequency of V and I (e.g., 50 or 60 Hz) comes out of a wall socket, for example. In the US, the wall frequency is usually 60 Hz and in Europe it is usually 50 Hz. According to the equation above, the compensating factor between voltage and current is cost. According to the present invention, an ADC oversamples at a clock rate in excess of the output rate of the ADC to enable generation of delays for use in downstream filters. According to one embodiment, the ADCs  47 ,  48  run at the Nyquist rate. The total adjustable delay is d 1 +d 2 . The fixed or matching delay in the current channel is 64/f. 
     According to the present invention, the natural delay of the second channel is longer than the delay of the first channel. Since the second channel delay is the current and the first channel delay is the voltage, the natural delay of the current channel is longer than the natural delay of the voltage channel. This additional delay is represented in FIG. 3 by delay block  43 . Without additional, programmable, compensation, the output of the second channel would lag the output of the first channel. By increasing the delay in the first channel, the phase relationship can be moved from lagging (a negative offset) to leading (a positive offset). This fall range of adjustment can be accomplished by adding programmable delay in only one of the channels. 
     Referring now to FIG. 4, there is shown a diagram of first delay cell d 1   39  according to the present invention. The first delay cell d 1  includes delay elements  140 - 142  and a selector element  143  connected to elements  140 - 142 . The selector element S 1  chooses a delayed version of d 1 _in and passes it to d 1 _out. The delay is k 1 z −8 , where k 1  is programmable to the values 0,1,7. z −8 represents an 8 clock delay. At frequency f, this is equivalent to a delay of d 1 =8k 1 /f. For example, with f=512 kHz and k 1 =3, d 1 =46.875 microseconds. Each register is a single bit element, since the data comes directly from the modulator. Implementing the majority of the delay with single bits results in substantial silicon savings. 
     Referring now to FIG. 5, there is shown a diagram of delay cell d 2   42  according to the present invention. The second delay cell d 2   42  includes a delay element  240  and a selector element  241  connected to the delay element  240 . The selector element S 2   241  chooses a delayed version of d 2 _in and passes it out as d 2 _out. The delay will be k 2 *z −1 , where k 2  is programmable to the values 0 or 1. z −1  represents a one clock delay. At the frequency f/64, this is equivalent to a delay of d 2 =64*k 2 /f. For example, with f=512 kHz and k 2 =1, d 2 =125 microseconds. The savings in area by delaying single bits, diminishes for large values of required delay. For this reason some of the delay was implemented at this lower frequency. The implementation is optimal for the given system. The total delay in the voltage channel is d 1 +d 2 =8k 1 /f+64k 2 /f=1/f(8k 1 +64k 2 ). Therefore, dt (relative to current channel) is 64/f−(d 1 +d 2 )=1/f(64−8k 1 −64k 2 ) for k 1 =0,1, . . . ,7 an The range of correction is 64/f to −56/f with a resolution of 8/f. 
     Referring now to FIG. 6A, there is shown a phase compensation system  299  according to the present invention. In particular, the phase compensation system  299  includes a delta sigma analog to digital converter  347 , a sinc filter  348 , a first decimator  349 , a FIR filter block  350 , and a second decimator  351 . In FIG. 6A, the HICLK=DCLK/8. The MDCLK=DCLK/512. The LOCLK=DCLK/1024. f is the frequency of the modulator sampling at 512 kHz for example. The range of correction ensures that 64/f corresponds to an amount of time enabling delay of two channels by a specific amount of time. The maximum and minimum amounts of delay are 64/f (leading) and −56/f (lagging). To implement a phase compensation calculation according to the present invention, a sinc function is used as a filter function to eliminate quantization noise introduced by the delta-sigma converter  347 . Reduction of noise is accomplished by a factor of  64  by downsampling resulting from the earlier oversampling. The FIR  350  in FIG. 6A corrects for the attenuation by the sinc low pass filter  348 . The FIR  350  attenuates noise as well as information signals. When the sinc low pass filter  348  operates at high frequency with attenuation being substantial, both signal and noise components are reduced. No signals are transmitted at that frequency range, however. However, at the low frequencies where the signal is, the attenuation droops slowly, rolling off very gradually from DC levels. With non-DC signals such as a power signal, a slight filter rolloff results in different attenuation at 50 Hz than at 60 Hz (or for example at 100 Hz versus 200 Hz). In a noise reduction filter, it is desirable that any signal, irrespective of frequency, will have the same gain. The FIR  350  does the opposite of the roll off of the sinc, i.e., the FIR  350  corrects for the gain error. The two filters  348 ,  350  combined do not introduce any substantial gain error as frequency shifts between 1 Hz, 10 Hz, or 100 Hz. 
     Referring now to FIG. 6B, there is shown a chart relating selected DCLK and signal frequencies (fsig) to the phase shift that can be introduced by various clocks HICLK, MDCLK, and LOCLK. According to one aspect of the invention, the required range for compensating current transformers is plus or minus one to two degrees. This is accomplished with one MDCLK and 64 HICLKS. 
     FSIG is the input signal. Depending on the signal frequency (e.g., 50 or 60 Hz), a particular time represents a particular amount of phase. For example, for a signal frequency of 50 Hz, a corresponding amount of time may represent 180 degrees of phase. On the other hand, a 100 Hz input may represent 380 degrees of phase. For the indicated values of DCLK, the operating range according to the present invention is ±2.5 degrees, which requires a programmable delay of 0 to 5 degrees. After the operating ranges have been established in the first 2 columns, the calculated phases for hi, mid, and low clocks are shown. From this information, it is clear that the low clock is too slow (5-10 degrees). It moves too much with each clock. With the mid clocks plus a few high clocks, a workable result is achieved. With a high clock, the data is in single bit, because coming out of the delta-sigma, there is just either a one (1) or a zero (0). With Mdclock, the word length is up to 16 bits, and to generate such delays is costly. To generate one unit of delay with a mid clock, 16 registers are used compared to generating one unit of delay at the high clock, where only one extra register is required. The disadvantage of generating a similar delay at high clock compared to at mid clock, more delay blocks (stages) (e.g., z 8 ) are needed. Even with one register, 64 stages are needed to get one which would be obtained at the mid clock. In general, to generate a delay, the 16 bits are copied 10 times like a shift register. This results in a signal delay of 10 units of time. Accordingly, to generate a 1 unit of time delay at a selected mid clock rate, just one extra register bank is needed, wherein the one register used may be 16 bits wide one register is used. At a low clock rate, one of the design rules is not to apply a phase shift of much more than ±2.5 degrees. This ±2.5 degree range is with an added safety factor, because the actual range is only ±1 to ±2 degrees. The delay is inserted at two places because it is known what kind of delay is desired, the resolution is known, the dynamic range is known. In addition, it is desired to optimize the design based on total silicon area. In the initial preferred embodiment the delay is broken into two places. For example if the word width is 32 instead of 16 bits wide, it is anticipated that the delays would be reconfigured. 
     Referring now to FIG. 7A, there is shown a phase compensation delay cell d 1   39  according to the present invention. The first delay cell d 1  includes z elements  140 - 142  and a selector element  143 . The selector element S 1  chooses a delayed version of d 1 ,in and passes it to d 1 ,out. The delay is (k 1 ) * (z −8 ), where k 1  is programmable to the values 0,1,7. Z −8  represents an 8 clock delay. At frequency f, this is equivalent to a delay of d 1 =8k 1 /f For example, with f=512 kHz and k 1 =3, d 1 =46.875 microseconds. Each register is a single bit element, since the data comes directly from the modulator. Implementing the majority of the delay with single bits results in substantial silicon savings. 
     Referring now to FIG. 7B, there is shown a chart relating values of B3B2B1B0 to Y 2 , Y 1 , total DELAY, and delay normalized to B=0. 
     Referring now to FIG. 8A, there is shown a delayed voltage channel  529  according to the present invention. The delayed voltage channel  529  includes a delay element  530 , a decimator  531 , a second delay element  532 , and a second decimator  533 . The Figure shows the total channel delay without phase compensation. 
     Referring now to FIG. 8B, there is shown a delayed current channel according to the present invention. The delayed current channel  629  includes a delay element  630 , a decimator  631 , a second delay element  632 , and a second decimator  633 . The Figure shows the total channel delay without phase compensation.