Abstract:
A circuit stage such as an input stage is provided for a radio frequency tuner having an input which typically receives a broadband signal comprising many channels. The input stage comprises a low noise amplifier in the form of a long tail pair of transistors and a controllable tail current source. A level detector detects the signal level at the input of the amplifier and controls the tail current source so as to increase the tail current as the signal amplitude rises above a threshold level and so as to keep the tail current fixed when the signal amplitude is below the threshold.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates to circuit stage for a radio frequency tuner. The invention also relates to a radio frequency tuner incorporating such circuit stage.  
         BACKGROUND  
         [0002]    Known types of radio frequency tuners are based on superheterodyne techniques. A broadband radio frequency signal containing many channels available for reception is supplied to the tuner input, for example from a terrestrial aerial, a satellite aerial system or a cable distribution system. The tuner is arranged to select any desired one of the channels for reception and converts this to a standard intermediate frequency signal which is then supplied to a demodulator.  
           [0003]    In a typical known type of tuner, for example of the dual conversion type, the broadband input signal is supplied to a low noise amplifier (LNA) input stage, whose output is supplied to a frequency changer or a first frequency changer for converting the frequency of the selected channel to the or the first intermediate frequency. There are no tracking filters between the tuner input and the LNA for attenuating any of the non-selected channels so that a relatively high signal level may be presented to the input of the LNA.  
           [0004]    The LNA typically comprises a long tail pair of transistors whose tail current must be sufficiently large to ensure that the LNA provides adequate intermodulation distortion performance, such as IP3 performance, for acceptable reception. In particular, the tail current must be sufficient to provide the necessary performance when the maximum theoretical total input power is applied to the input of the LNA. This maximum theoretical power would only be achieved if each channel where at its maximum signal level and the signals of all of the channels in the broadband signal were in phase. In practice, such a condition is unlikely to occur so that the total input power supplied to the LNA input is generally much less than the theoretical maximum value. However, in order to provide acceptable performance under all possible conditions, the tail current of the LNA is set to a value which would provide acceptable performance in the worst possible case.  
           [0005]    GB 2 363 523 discloses a transceiver for use as a mobile telephone. The receiver section has an LNA whose bias current is controlled by a baseband signal processor. The main purpose of this is to vary the LNA bias current in accordance with transmitter power of the transmitting section so as to minimise power consumption (for example during standby mode) but to increase the bias current to maintain adequate performance in the presence of strong leakage signals from the transmitter section. The signal level present at the LNA is inferred without making any level measurements at this stage.  
           [0006]    WO 01/73958 is also principally concerned with mobile telephone applications and discloses arrangements which vary the bias current in accordance with the signal level through various stages of a receiver including what amounts to an LNA. In this case, the signal level at the output of the stage is measured and used to determine the appropriate bias current for the stage.  
         SUMMARY  
         [0007]    According to a first aspect of the invention, there is provided circuit stage for a radio frequency tuner, comprising: a signal processing stage having a controllable supply current; and a level detector for detecting the signal level at the signal processing stage and for controlling the controllable supply current to have a first magnitude when the detected level has a first value and a second magnitude greater than the first magnitude when the detected level has a second value greater than the first value, characterised in that the level detector is arranged to increase the magnitude of the controllable supply current with increasing detected level above a threshold level and to maintain the controllable supply current fixed for detected levels below the threshold level.  
           [0008]    The level detector may be arranged to increase the magnitude monotonically with increasing detected level above the threshold level.  
           [0009]    The signal processing stage may comprise a first long tail pair of transistors and the controllable supply current may comprise the tail current of the first long tail pair. The signal processing stage may comprise a controlled current source for supplying the tail current. The controlled current source may comprise a fixed current source and a variable source. The variable current source may comprise an output stage of a first current mirror.  
           [0010]    The level detector may comprise at least one envelope detector. The or each envelope detector may comprise the base-emitter junction of a bipolar transistor and a capacitor connected to the emitter of the transistor. The circuit stage may comprise a second long tail pair of transistors whose inputs are connected to outputs of first and second of the envelope detectors.  
           [0011]    The level detector may comprise a voltage to current output stage. The output stage may comprise a third long tail pair of transistors. The third long tail pair may have outputs connected to a second current mirror. The output of the second current mirror may be connected to an input stage of the first current mirror.  
           [0012]    The signal processing stage may comprise an amplifier, such as a low noise amplifier or an intermediate frequency amplifier.  
           [0013]    The signal processing stage may comprise a baseband stage.  
           [0014]    The signal processing stage may comprise a mixer  
           [0015]    According to a second aspect of the invention, there is provided a radio frequency tuner having circuit stage according to the first aspect of the invention.  
           [0016]    It is thus possible to provide an arrangement in which the supply current, such as the tail current of a long tail pair of transistors, is controlled in accordance with the signal level presented to the circuit stage. Such an arrangement allows the supply current to be set to a value which provides adequate distortion performance for the signal power supplied to the circuit stage while allowing the supply current to be reduced as compared with known arrangements as described hereinbefore. It is thus possible to obtain an improvement in the noise performance of the circuit stage. For example, where the circuit stage is embodied by bipolar transistors, the shot noise can be reduced so that the noise figure is reduced for much of the time. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 is a block schematic diagram of a tuner input stage constituting an embodiment of the invention;  
         [0018]    [0018]FIG. 2 is a circuit diagram of a first example of a level detector of the input stage of FIG. 1;  
         [0019]    [0019]FIG. 3 is a circuit diagram of the output stage of the level detector of FIG. 2 illustrating the operation thereof;  
         [0020]    [0020]FIG. 4 is a circuit diagram illustrating a controllable tail current source of the input stage of FIG. 1;  
         [0021]    [0021]FIG. 5 is a circuit diagram of a second example of the level detector of the input stage of FIG. 1;  
         [0022]    [0022]FIG. 6 is a circuit diagram of a third example of the level detector of the input stage of FIG. 1;  
         [0023]    [0023]FIGS. 7 and 8 are circuit diagrams of alternative arrangements of controlled tail current sources; and  
         [0024]    [0024]FIG. 9 is a block schematic diagram of a tuner including the input stage of FIG. 1. 
     
    
       [0025]    Like reference numerals refer to like parts throughout the drawings.  
       DETAILED DESCRIPTION  
       [0026]    The radio frequency tuner input stage shown in FIG. 1 is intended for use at the input of a tuner with no channel-selective filtering ahead of the input stage. For example, there may be fixed filtering to attenuate signals outside the desired reception range but no filtering to attenuate any of the channels within that range. However, the input stage could also be used in tuners which do have some input filtering to attenuate channels other than the one currently selected for reception.  
         [0027]    The tuner input  1  is connected to the inputs of an LNA  2  and a level detector  3 . The LNA  2  comprises a differential stage of generally known type and illustrated schematically in FIG. 1 as a long tail pair of bipolar transistors  4  and  5  having collector load resistors  6  and  7  and emitter degeneration resistors  8  and  9  connected to a tail current source. The tail current source comprises a fixed current source  10 , and a controlled source  11 , which receives a control current I control  from the level detector  3  and supplies a current N times the current I control  in addition to the fixed current provided by the source  10 .  
         [0028]    A first example of the level detector  3  is shown in FIG. 2 and comprises an input  20  connected to the tuner input  1  and an output  21  connected to the controllable current source  11 . The input  20  is connected via a DC-blocking coupling capacitor  22  to the base of a bipolar transistor  23  which is also connected via an isolating resistor  24  to a bias voltage source at a circuit node  25 . The collector of the transistor  23  is connected to a supply line VCC whereas the emitter thereof is connected to the base of a transistor  26  and to a first terminal of a capacitor  27 , whose second terminal is connected to ground gnd. The collector of the transistor  26  is connected to the supply line VCC and the emitter thereof is connected via a constant current source  28  to ground gnd.  
         [0029]    The base-emitter junction of the transistor  23  and the capacitor  27  form an envelope detector to provide a representation of the level or magnitude of the signal at the tuner input  1 . The base-emitter junction of the transistor  23  acts as a half wave rectifier so that the capacitor  27  is charged by alternate half cycles of the input signal which exceed the voltage across the capacitor  27  plus the base-emitter voltage drop of the transistor  23 . A charge leakage path exists through the base-emitter junction of the transistor  26  so that the voltage across the capacitor  27  follows rising signal levels relatively quickly but falls more slowly when the input signal level is reduced. The transistor  26  and the current source  28  act as an emitter follower for providing the appropriate leakage current and for supplying a signal representative of the input signal level to the following stage.  
         [0030]    The following stage comprises an amplifier in the form of a long tail pair of transistors  29  and  30  whose emitters are connected via emitter degeneration resistors  31  and  32  to another constant current source  33 . The collectors of the transistors  29  and  30  are connected via load resistors  34  and  35  to the supply line VCC and form the outputs of the amplifying stage. The base of the transistor  30  is connected to the emitter of the transistor  26 . The base of the transistor  29  is connected to another emitter follower comprising a transistor  36  and a constant current source  37 . The base of the transistor  36  is connected to another envelope follower comprising a capacitor  38  and a transistor  39  whose base is connected via an isolating resistor  40  to the bias voltage source.  
         [0031]    The transistors  36  and  39  and associated components are substantially identical to the transistors  26  and  23 , respectively, and their associated components so that the inputs of the amplifying stage are balanced at DC.  
         [0032]    The outputs of the amplifying stage are connected to respective level shifting circuits. In particular, the collector of the transistor  29  is connected to the base of a transistor  41 , whose collector is connected to the supply line VCC and whose emitter is connected via a forward-biased diode  42 , a resistor  43  and a constant current source  44  to ground gnd. The connection between the resistor  43  and the constant current source  44  constitutes the output of the level shifting circuit.  
         [0033]    The collector of the transistor  30  is connected to the base of a transistor  45  of the other level shifting circuit. The collector of the transistor  45  is connected to the supply line VCC whereas the emitter of the transistor  45  is connected via a forward-biased diode  46  and a constant current source  47  to ground gnd. The connection between the diode  46  and the constant current source  47  forms the output of the level shifting circuit, which differs from that based on the transistor  41  in that there is no resistor between the diode  46  and the constant current source  47 .  
         [0034]    The outputs of the level shifting circuits are connected to an output stage of the level detector  3  in the form of a voltage-to-current converter. In particular, the output stage comprises a long tail pair of transistors  48  and  49  whose emitters are connected via emitter degeneration resistors  50  and  51  to a constant current source  52 . The collectors of the transistors  48  and  49  are connected to a current mirror formed by MOS field effect transistors  54  and  55 , respectively. The transistor  55  comprises the current mirror input stage and has its gate and drain connected to the collector of the transistor  49  and its source connected to the supply line VCC. The transistor  54  comprises the output stage of the current mirror and has its gate connected to the gate and drain of the transistor  55 , its source connected to the supply line VCC and its drain connected to the collector of the transistor  48  and to the source of another MOS field effect transistor  56 . The transistor  56  is connected in the cascode mode with its gate connected to the base of the transistor  48  and to the output of the level shifting circuit based on the transistor  45 . The drain of the transistor  56  is connected to the input stage of a current mirror comprising a transistor  57  whose emitter is connected to ground gnd via a resistor  58  and whose base is connected to its collector and to the output terminal  21  of the level detector.  
         [0035]    The whole of the current mirror is illustrated in FIG. 4 and comprises the input stage  59  and an output stage in the form of the controlled current source  11  shown in FIG. 1. The current source  11  comprises N transistors such as  60 , all of which are substantially identical to the transistor  57 , and N emitter resistors such as  61 , all of which have the same resistance as the resistor  58 . The collectors of the transistors such as  60  are connected together and form the output of the controllable current source  11 . The controllable current source  11  thus supplies a current which is N times the value of the current I control  through the input stage  59  of the current mirror.  
         [0036]    The current mirror comprising the transistors  57  and  60  is of relatively simple type and is shown by way of example only. More complex current minors of improved performance may be used but are not described herein as they are well known in the art. In the absence of any input signal at the tuner input  1  and hence at the input  20  of the level detector  3 , there is no potential difference between the emitters of the transistors  23  and  39 . The differential output voltage of the amplifier stage comprising the transistors  29  and  30  is therefore also zero. The current provided by the current source  44  in the level shifting stage based on the transistor  41  causes a voltage drop across the resistor  43  so that the base of the transistor  49  is at a lower voltage than the base of the transistor  48 . A larger portion of I 15  is steered to the transistor  48  so that I C10  is larger that I c9 . Because of the action of the current mirror comprising the transistors  54  and  55 , I D1  must be a copy of I c10  I D1  is therefore equal to I c10  and I control  is zero. The current mirror comprising the transistors  57  and  60  therefore supplies zero current and the tail current of the long tail pair of transistors  4  and  5  forming the LNA  2  is at a minimum value and is determined by the output current of the fixed current source  10 .  
         [0037]    When a signal of sufficient amplitude is present at the input  20 , this is half-wave rectified by the base-emitter junction of the transistor  23  and charges up the capacitor  27 . The charge on the capacitor  38  remains constant so that a potential difference exists between the emitters of the transistors  23  and  39  and is supplied via the emitter followers comprising the transistors  26  and  36  to the bases of the transistors  29  and  30  of the amplifying stage. This is amplified by the amplifying stage and supplied to the level shifting circuits, where the voltage drop across the resistor  43  is subtracted from the potential difference supplied to the bases of the transistors  49  and  48 . The resulting potential difference ΔV is illustrated in FIG. 3 together with the current I C9  flowing through the transistors  49  and  55 , the current mirror output current I D1 , the collector current I C10  of the transistor  48 , and the control current I control  which is equal to (I D1 −I C10 ). The tail current supplied by the constant current source  52  is I 15 .  
         [0038]    When the potential difference ΔV is equal to zero, the tail current I 15  is steered equally between the transistors  48  and  49  so that the collector currents I C9  and I C10  are equal to each other. When the potential difference ΔV is greater than zero, a larger portion of the tail current is steered through the transistor  49  so that I C9  is greater than I C10  and, because of the current mirror action, I D1  is equal to I C9  and hence is greater than I C10 . The sum of I C9  and I C10  has to be equal to the tail current I 15  so that I C9  is equal to the difference between I 15  and I C10 . The control current I control  is thus given by:  
           I   control   =I   D1   −I   C10   =I   C9   −I   C10   =I   15 −2 I   C10 .  
         [0039]    If the potential difference ΔV is large enough such that I C10  is zero, the control current I control  is equal to I 15 . Thus, the control current I control  can vary between zero and I 15  and hence the tail current of the LNA can be varied between the current supplied by the fixed current source  10  and the sum of the current supplied by the fixed current source and N times I 15 . In general, the maximum LNA tail current is arranged to be sufficient to provide acceptable distortion performance of the LNA when the theoretical maximum input signal power is supplied to the tuner input  1 .  
         [0040]    The voltage drop across the resistor  43  provides a “delay” such that the amplitude or level of the input signal must be greater than a threshold level (resulting in the potential difference between the collectors of the transistors  29  and  30  exceeding the voltage drop across the resistor  43 ) in order for I control  to have a non-zero value. The emitter degeneration resistors  50  and  51  help to linearise the transconductance of the output stage and likewise the emitter degeneration resistors  31  and  32  help to linearise the transfer function of the amplifying stage. Above the input threshold level, the control current I control  is therefore substantially proportional to the input signal level and is a monotonic function thereof.  
         [0041]    [0041]FIG. 5 shows another example of the level detector  3  which differs from that shown in FIG. 2 in that it has differential inputs  20   a  and  20   b  for receiving a differential input signal. The level detector comprises two envelope detectors based on transistors  23   a  and  23   b  and the common capacitor  27  connected to the emitters thereof. The bases of the transistors  23   a  and  23   b  are connected via respective coupling capacitors  22   a  and  22   b  to the respective inputs  20   a  and  20   b . The bases of the transistors  23   a  and  23   b  are also connected via respective isolating resistors  24   a  and  24   b  to the bias voltage source node  25 . The base of the transistor  39  is connected via isolation resistors  40   a  and  40   b  to the bases of the transistors  23   a  and  23   b , respectively, so as to maintain DC balance at the inputs of the amplifying stage.  
         [0042]    The differential inputs and the two envelope followers provide full-wave rectification of the differential input signal. Thus, the capacitor  27  is charged by each half cycle of the input signal and hence provides a shorter sampling time of the input signal by the level detector than the input arrangement of FIG. 2.  
         [0043]    [0043]FIG. 6 shows an example of the level detector  3  having differential inputs  20   a  and  20   b . However, this level detector may also be used with a single-ended input signal with one of the inputs  20   a  and  20   b  connected to ground gnd. In either case, the level detector provides full-wave rectification in the same way as the level detector shown in FIG. 5.  
         [0044]    The differential inputs  20   a  and  20   b  are connected to the bases of a long tail pair of transistors  65  and  66  whose emitters are connected via respective emitter degeneration resistors  67  and  68  to a constant current source  69 . The collectors of the transistors  65  and  66  are connected via respective load resistors  70  and  71  to the supply line VCC. The collectors of the transistors  65  and  66  are also connected to the bases of the transistors  23   a  and  23   b , respectively, and via respective resistors  40   a  and  40   b  to the base of the transistor  39 . The bias voltage source is not therefore needed and balanced DC conditions are maintained at the inputs of the amplifying stage.  
         [0045]    The long tail pair of transistors  65  and  66  allows connection of a balanced or differential input signal but also converts a single-ended signal to a differential signal for full-wave rectification in the envelope detectors  23   a ,  23   b ,  27 . The long tail pair of transistors  65  and  66  may also provide voltage gain so as to adjust the input signal level before being rectified in the envelope detectors.  
         [0046]    It is thus possible to control the tail current, and hence the supply current, of an LNA in accordance with the signal amplitude present at the LNA input. The average supply current of the LNA is therefore reduced as compared with a known arrangement in which a sufficiently large constant tail current is provided to cope with the worst-case maximum input signal power which may be supplied to the LNA input. When using bipolar transistors in the LNA, such as in the long tail pair configuration, the shot noise generated by the bipolar transistors can be reduced so that the noise figure of the LNA can be reduced during usual operating conditions.  
         [0047]    Although use of the present techniques in an LNA forming the input stage of a radio frequency tuner has been described in detail, such techniques may be applied to other stages of a tuner, such as a mixer, an intermediate frequency amplifier or a baseband stage, or to several stages of a tuner. In particular, where the signal level applied to a stage may vary during use, these techniques may be applied to any such signal processing stage in order to provide a reduction in current consumption and an improvement in noise performance. Also, although the detailed circuit arrangements described hereinbefore provide a level detector which detects the signal level at the input of the signal processing stage, the level at the output of such a stage may instead be detected in order to control the supply current.  
         [0048]    Further, the long tail pair of transistors  4  and  5  is shown in FIG. 1 as having a “T-configuration” current supply with the fixed and controlled current sources  10  and  11  being connected via the emitter degeneration resistors  8  and  9  to the emitters of the transistors  4  and  5 , respectively. However, this current supply may be replaced by a “Π configuration” as illustrated in FIGS. 7 and 8. In FIG. 7, the fixed current source  10  is connected in the same way as shown in FIG. 1. However, the controlled current source  11  is replaced by two controlled current sources  11   a  and  11   b , each of which is arranged to supply N/2× the current I control . The current sources  11   a  and  11   b  are connected directly to the emitters of transistors  4  and  5 , respectively. In FIG. 8, the single fixed current source  10  is replaced by fixed current sources  10   a  and  10   b , which supply half of the fixed current of source  10  and which are connected directly to the emitters of the transistors  4  and  5 , respectively. Such Π-configuration current supplies have the advantage of reducing or avoiding the voltage drop across the emitter degeneration resistors  8  and  9 , which otherwise might cause headroom problems for the various current sources.  
         [0049]    [0049]FIG. 9 illustrates diagrammatically a typical tuner arrangement in which the radio frequency input  1  is connected to the LNA  2  and the level detector  3  shown in FIG. 1. The output of the LNA  2  is supplied to a first frequency changer  100 , which converts the frequency of a selected channel to a first high intermediate frequency (IF). The output of the frequency changer  100  is supplied to an IF filter  101  having a passband characteristic substantially centred on the IF. The filter  101  thus passes the selected channel at the IF and adjacent channels to the input of a second frequency changer  102 .  
         [0050]    The second frequency changer  102  converts the selected channel at the first IF to a second intermediate frequency, which may be zero or near zero or may be of the order of a few tens of MHz. The output of the frequency changer  102  is supplied to a further IF filter  103  having a passband which passes the selected channel and substantially rejects all other channels. The output of the filter  103  is supplied to the input of an IF amplifier  104 , whose output is connected to the output  105  of the tuner.