Abstract:
A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. provisional application No. 62/157,054 filed May 5, 2015. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to a chip package assembly, and more particularly to a semiconductor chip package assembly with improved heat dissipation performance. 
         [0003]    In a conventional method for forming a semiconductor chip package assembly, a chip (or a chip package) is electrically connected to a package substrate and mechanically bonded in a solder joining operation. The chip is aligned with and placed onto a placement site on the package substrate such that the solder balls are aligned with electrical pads or pre-solder on the substrate. The substrate is typically composed of an organic material or laminate. Heat is then applied causing the solder balls to alloy and form electrical connections between the chip and the package substrate. 
         [0004]    For chip packages, electrical performance and dissipation control are two major challenges. In the aspect of electrical performance, chip packages have to maintain signal integrity and operating frequency of semiconductor devices. In the aspect of dissipation control, it is required that chip packages efficiently dissipate heat generated by the semiconductor chip. 
         [0005]    A heat spreader or lid, typically composed of a high thermal conductivity material, and having substantially the same dimensions as the package substrate is typically attached over the substrate and the chip by a thermally conductive adhesive. The purpose of the heat spreader is to disperse the heat generated during operation to reduce stress in the package. 
         [0006]    With the rapid development of semiconductor technology, the number of I/O pads in a chip has dramatically increased, and the power that each chip consumes has also increased. The heat spreader typically mounted on the inactive surface of the flipped chip does not efficiently dissipate the heat from the active surface of the chip (or land side of a chip package). Therefore, there is a need in this industry to provide a chip package assembly with improved heat dissipation performance. 
       SUMMARY 
       [0007]    It is an objective of the claimed invention to provide a semiconductor chip package assembly with improved heat dissipation performance. 
         [0008]    According to one embodiment, a semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package. The discrete device may comprise a land side capacitor, a de-coupling capacitor, a resistor, or an inductor. 
         [0009]    According to another embodiment, a semiconductor chip package assembly includes a substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a multi-chip package mounted on the chip mounting surface and electrically connected to the substrate through a plurality of solder balls on respective solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the substrate; a first solder connecting the first terminal with the first dummy pad and the multi-chip package; and a second solder connecting the second terminal with the second dummy pad and the multi-chip package. 
         [0010]    According to yet another embodiment, a semiconductor chip package assembly includes a substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a package-on-package (PoP) mounted on the chip mounting surface and electrically connected to the substrate through a plurality of solder balls on respective solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the substrate; a first solder connecting the first terminal with the first dummy pad and the PoP; and a second solder connecting the second terminal with the second dummy pad and the PoP. 
         [0011]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: 
           [0013]      FIG. 1  is a schematic, cross-sectional diagram showing a semiconductor chip package assembly in accordance with one exemplary embodiment of the invention; 
           [0014]      FIG. 2  to  FIG. 4  show different configuration of the land side capacitor and the heat dissipating pads on the package substrate according to various embodiments; 
           [0015]      FIG. 5  illustrates a semiconductor chip package assembly according to another embodiment of the invention; and 
           [0016]      FIG. 6  illustrates a semiconductor chip package assembly according to yet another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced. 
         [0018]    These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims. 
         [0019]    Please refer to  FIG. 1 .  FIG. 1  is a schematic, cross-sectional diagram showing an exemplary semiconductor chip package assembly in accordance with one embodiment of the invention. As shown in  FIG. 1 , the semiconductor chip package assembly  1  may comprise a chip package  100  directly mounted on chip mounting surface  200   a  of a package substrate  200  through an array of solder balls  250 . 
         [0020]    According to the exemplary embodiment, the chip package  100  may comprise a semiconductor chip  10  that is encapsulated and surrounded by a molding compound  12 . The active surface  10   a  having a plurality of input/output (I/O) pads  102  distributed thereon is not covered by the molding compound  12  and faces downwardly toward the package substrate  200 . The inactive surface  10   b  of the semiconductor chip  10  may be covered with the molding compound  12 , but is not limited thereto. 
         [0021]    The surrounding molding compound  12  may have a surface that is substantially flush with the active surface  10   a.  A redistribution layer (RDL) structure  20  may be formed on the active surface  10   a  and on the surrounding molding compound  12  to fan out the I/O pads  102 . The RDL structure  20  may comprise at least one dielectric layer  120 , at least one metal layer  110 , and redistributed pads  112  on the land side of the chip package  100 . 
         [0022]    The solder balls  250  placed on the solder pads  212  of the package substrate  200  establish electrical connection between the chip package  100  and the package substrate  200 . Such configuration is also known as a fan-out wafer level package (FOWLP). 
         [0023]    It is to be understood that the structure of the chip package  100  shown in  FIG. 1  is for illustration purposes only. In some embodiments, the chip package  100  maybe replaced with an unpackaged silicon chip or die. In some embodiments, the chip package  100  may be replaced with a multi-die chip package such as Fan-out WLP (FO WLP) or other types of chip package. 
         [0024]    In some embodiments, epoxy or resin underfill (not shown) may be applied between the solder balls  250 . In some embodiments, the solder balls  250  may be replaced with copper pillars or the like. In some embodiments, the package substrate  200  may be replaced with a printed circuit board (PCB). 
         [0025]    According to the exemplary embodiment, semiconductor chip package assembly  1  further comprises at least one discrete device  150  mounted on the land side of the chip package  100 . For example, the discrete device  150  may include, but not limited to, a land side capacitor, a de-coupling capacitor, a resistor, or an inductor. 
         [0026]    According to the exemplary embodiment, the discrete device  150  such as a land side capacitor has two terminals  151  and  152 , which are electrically coupled to V SS  and V DD  voltages, respectively, through the RDL structure  20 . According to the exemplary embodiment, the two terminals  151  and  152  may be connected to the respective pads  111  in the RDL structure  20  by using solder  154 . 
         [0027]    According to the exemplary embodiment, the two terminals  151  and  152  of the discrete device  150  are also connected to the respective pads  211  on the package substrate  200  through solder  154 . The pads  211  are for heat dissipation and may be dummy pads. For example, the dummy pads  211  may be electrically isolated from other metal traces on the package substrate  200 , but is not limited thereto. 
         [0028]    The dummy pads  211  and the solder pads  212  may be partially covered with a solder mask  202 . The solder mask  202  may cover a peripheral region of each of the pads  211  and  212  and may expose a central region of each of the pads  211  and  212 . 
         [0029]    By providing such configuration, the heat generated by the chip package  100  can be efficiently dissipated through the solder  154 , the discrete device  150 , to the package substrate  200 . 
         [0030]      FIG. 2  to  FIG. 4  show different configuration of the land side capacitor and the heat dissipating pads  211  on the package substrate  200 . For the sake of simplicity, only some parts (e.g., RDL structure  20 , the upper portion of the package substrate  200 , and the discrete device  150 ) of the semiconductor chip package assembly are shown. 
         [0031]    As shown in  FIG. 2 , the pads  111  of the RDL structure  20  of the chip package  100  are aligned with the dummy pads  211  on the package substrate  200 . To prevent overflow of the solder  154 , a recess or a slot  202   a  may be provided in the solder mask  202  between the two solder pads  211 . If an underfill (not shown) is applied, the slot  202   a  may be filled with the underfill. 
         [0032]    As shown in  FIG. 3 , the pads  111  of the RDL structure  20  of the chip package  100  are aligned with the dummy pads  211  on the package substrate  200 . To prevent overflow of the solder  154 , a recess or a slot  110   a  may be provided in the dielectric layer  110  between the pads  111 . If an underfill (not shown) is applied, the slot  110   a  may be filled with the underfill. 
         [0033]    As shown in  FIG. 4 , the pads  111  of the RDL structure  20  of the chip package  100  are misaligned with the dummy pads  211  on the package substrate  200 . By increasing the distance between the two dummy pads  211 , the overflow of the solder  154  may be avoided. 
         [0034]      FIG. 5  illustrates another embodiment of the invention, wherein like numeral numbers designate like regions, layers or elements. As shown in  FIG. 5 , according to another embodiment of the invention, a semiconductor chip package assembly la is provided. The semiconductor chip package assembly la may comprise a multi-chip package  100   a  having at least two semiconductor chips  30  and  40  arranged on an RDL structure  20  in a side-by-side manner. The semiconductor chips  30  and  40  comprise a plurality of I/O pads  302  and  402  on their active surfaces, respectively. 
         [0035]    Likewise, the RDL structure  20  may be formed on the active surfaces of the semiconductor chips  30  and  40 , and on the molding compound  12  to fan out the I/O pads  302  and  402 . The RDL structure  20  may comprise at least one dielectric layer  120 , at least one metal layer  110 , and redistributed pads  112  on the land side of the multi-chip package  100   a.    
         [0036]    The semiconductor chip package assembly la further comprises at least one discrete device  150  mounted on the land side of the multi-chip package  100   a.  For example, the discrete device  150  may include, but not limited to, a land side capacitor, a de-coupling capacitor, a resistor, or an inductor. 
         [0037]    According to the exemplary embodiment, the discrete device  150  such as a land side capacitor has two terminals  151  and  152 , which may be electrically coupled to V SS  and V DD  voltages, respectively, through the RDL structure  20 . According to the exemplary embodiment, the two terminals  151  and  152  maybe connected to the respective pads  111  in the RDL structure  20  by using solder  154 . 
         [0038]    According to the exemplary embodiment, the two terminals  151  and  152  of the discrete device  150  are also connected to the respective pads  211  on the package substrate  200  through solder  154 . The pads  211  are for heat dissipation and may be dummy pads. For example, the dummy pads  211  may be electrically isolated from other metal traces on the package substrate  200 , but is not limited thereto. 
         [0039]    The dummy pads  211  and the solder pads  212  may be partially covered with a solder mask  202 . The solder mask  202  may cover a peripheral region of each of the pads  211  and  212  and may expose a central region of each of the pads  211  and  212 . 
         [0040]    By providing such configuration, the heat generated by the multi-chip package  100   a  can be efficiently dissipated through the solder  154 , the discrete device  150 , to the package substrate  200 . 
         [0041]      FIG. 6  illustrates yet another embodiment of the invention, wherein like numeral numbers designate like regions, layers or elements. As shown in  FIG. 6 , according to another embodiment of the invention, a semiconductor chip package assembly lb is provided. The semiconductor chip package assembly lb may comprise a lower chip package  100   b  having at least one semiconductor chip  50  disposed on a lower RDL structure  20   a.  The semiconductor chip  50  comprises a plurality of I/O pads  502  on its active surface. The lower RDL structure  20   a  may be formed on the active surface and on the surrounding molding compound  12  to fan out the I/O pads  502 . The lower RDL structure  20   a  may comprise at least one dielectric layer  120 , at least one metal layer  110 , and redistributed pads  112  on the land side of the chip package  100 . 
         [0042]    An upper chip package  100   c  is stacked on the lower chip package  100   b  to constitute a package-on-package (PoP)  500 . The upper chip package  100   c  may comprise at least one semiconductor chip  60  encapsulated by a molding compound  13 . For example, the semiconductor chip  60  may be a memory chip such as a DRAM chip, but is not limited thereto. The upper chip package  100   c  may be electrically coupled to the lower chip package  100   b  through a plurality of solder balls  350  and a plurality of through mold vias (TMVs)  420 . Optionally, an upper RDL structure  20   b  may be provided between the upper chip package  100   c  and the lower chip package  100   b.    
         [0043]    The semiconductor chip package assembly lb further comprises at least one discrete device  150  mounted on the land side of the PoP  500 . For example, the discrete device  150  may include, but not limited to, a land side capacitor, a de-coupling capacitor, a resistor, or an inductor. 
         [0044]    According to the exemplary embodiment, the discrete device  150  such as a land side capacitor has two terminals  151  and  152 , which may be electrically coupled to V SS  and V DD  voltages, respectively, through the lower RDL structure  20   a.  According to the exemplary embodiment, the two terminals  151  and  152  may be connected to the respective pads  111  in the lower RDL structure  20   a  by using solder  154 . 
         [0045]    According to the exemplary embodiment, the two terminals  151  and  152  of the discrete device  150  are also connected to the respective pads  211  on the package substrate  200  through solder  154 . The pads  211  are for heat dissipation and may be dummy pads. For example, the dummy pads  211  may be electrically isolated from other metal traces on the package substrate  200 , but is not limited thereto. 
         [0046]    The dummy pads  211  and the solder pads  212  may be partially covered with a solder mask  202 . The solder mask  202  may cover a peripheral region of each of the pads  211  and  212  and may expose a central region of each of the pads  211  and  212 . 
         [0047]    By providing such configuration, the heat generated by the PoP  500  can be efficiently dissipated through the solder  154 , the discrete device  150 , to the package substrate  200 . 
         [0048]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.