Abstract:
There is provided a column address buffering circuit for use in memory devices such as a DDR DRAM for receiving column addresses and internally buffering the column addresses. In the buffering process, the column address buffering circuit generates specific internal address signals having different paths according to a burst length before an address strobe signal is inputted thereto. Such an arrangement synchronizes the generation time of the specific internal address signals with those of other internal address signals by positioning a bit transition detecting unit related to generating the specific internal address signals corresponding to an odd cell and an even cell in front of an address latch for generating internal address signals at the same time of the address strobe signal being coupled.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates to a peripheral circuit for use with a synchronous semiconductor memory device and, more particularly, to a column address buffering circuit.  
         BACKGROUND  
         [0002]    A double data rate synchronous dynamic random access memory (DDR SDRAM), which is recently emerging as a very high speed memory device, is an SDRAM in which data or instructions are inputted or outputted in synchronization with falling edges and rising edges of a clock signal. For instance, it is possible to obtain data corresponding to a clock signal of 200 megahertz (MHz) using both the rising and falling edges of a 100 MHz clock signal.  
           [0003]    Like a conventional SDRAM, the DDR SDRAM performs a column access operation by using an internal clock signal aligned to rising edges of an external clock signal. To execute the column access operation synchronized to the rising edges and the falling edges of the external clock signal, the DDR SDRAM should employ a 2-bit prefetch scheme in which an access operation for rising data and falling data is performed in one clock cycle.  
           [0004]    For example, if a column address ‘(A2, A1, A0)=(0, 0, 0)’ is inputted when a burst length is  2  and a burst type is a sequential type, although, on the outside, it looks like data corresponding to addresses of (0, 0, 1), (0, 1, 0) and (0, 1, 1) are sequentially outputted, internally, access operations for the column addresses of (0, 0, 0) and (0, 0, 1) are simultaneously performed in one clock cycle and those for the column addresses of (0, 1, 0) and (0, 1, 1) are simultaneously executed in the next clock cycle.  
           [0005]    Herein, the ‘burst length’ means a length of data continuously outputted from a clock synchronous memory device such as an SDRAM.  
           [0006]    As described above, when the burst length is 2, two column addresses are internally processed as aligned to the external clock signal. Therefore, if a column address A 1  is constant regardless of a least significant column address A 0  having a logic low or a logic high state, the memory is merely required to internally process a most significant column address to the lower column address A 1  regardless of the state of the least significant column address A 0 .  
           [0007]    However, if a logic state of the column address A 1  is differently generated according to the logic state of the least significant column address A 0 , internally, the column address A 1  is processed differently according to the logic state of the least significant column address A 0 . For instance, if column addresses (A 1 , A 0 ) are (0, 0), internal column addresses to be processed in a corresponding clock are (0, 0) and (0, 1). Further, if column addresses (A 1 , A 0 ) are (1, 0), internal column addresses to be processed in the corresponding clock become (1, 0) and (1, 1). Therefore, in case the least significant column address A 0  has a logic low state, its upper column address A 1  is processed regardless of the logic state of the least significant column address A 0 .  
           [0008]    However, if starting column addresses (A 1 , A 0 ) are (0, 1) or (1, 1), column addresses to be simultaneously processed in a corresponding clock become (1, 0) and (0, 0) and the column address A 1  should be internally inverted. That is, in case the least significant bit address A 0  has a logic high state, an inverted column address of A 1 , which is generated through a separate process, should be used.  
           [0009]    In general, for the 2-bit prefetch scheme, it is common to classify cells in a bank in a memory device into odd and even cells and to access the odd cells and the even cells separately. Therefore, the column address A 1  of the odd cell is generated to have a logic state identical to that of an external input address signal while the column address A 1  of the even cell is produced to have a logic state varying depending on a logic state of the least significant column address A 0 .  
           [0010]    Referring to FIG. 1, a block diagram of a conventional column address buffering circuit is shown. The column address buffering circuit comprises a multiplicity of address buffers  10 ,  12 ,  14 , a plurality of address latches  20 ,  22 ,  24  and a bit transition detecting unit  30  for detecting logic states of lower column addresses corresponding to a burst length and outputting address signals at 1 _od and at 1 _ev to access an odd cell and an even cell.  
           [0011]    Referring to FIG. 2, a circuit diagram of the bit transition detecting unit  30  in FIG. 1 when the burst length is 2 is illustrated. The bit transition detecting unit  30  includes a control signal generating block  31  for producing control signals set and setb. The control signal generating block  31  includes a 3-input NAND gate NAND 1  that receives an output signal at_col_ 0  of the address latch  20  (FIG. 1) and inverted signals of an input signal A generated according to the burst length and an input signal B produced according to a burst type (e.g., a sequential or an interleave type) and generates the control signal set and an inverter IN 6  inverting the control signal set to thereby produce the inverted control signal setb.  
           [0012]    The bit transition detecting unit  30  further includes an output block  32  for providing its following predecoder (not shown) with the address signals at 1 _od and at 1 _ev in response to the control signals set and setb. The output block  32  includes an inverter chain IN 1  and IN 2  for buffering the output signal at_col_ 1  of the address latch  20  to thereby output a column address signal at 1 _od for an odd cell. The output block  32  also includes two switching components MT 1  and MT 2  for selectively providing a following predecoder (not shown) with the output signal at_col_ 1  or an inverted signal of the output signal at 13  col_ 1  as a column address signal at 1 _ev for an even cell in response to the control signals set and setb.  
           [0013]    Hereinafter, the operation of the above column address buffering circuit will be described with reference to FIGS. 1 and 2.  
           [0014]    First of all, the address buffers  10 ,  12 ,  14  receive and buffer a plurality of column addresses A 0 , A 1 , An, respectively, in response to an internal clock signal clkp 4  and the address latches  20 ,  22 ,  24  receive signals out_ 0 , out_ 1 , out_n provided from the address buffers  10 ,  12 ,  14 , respectively, and generate output signals at_col_ 0 , at_col_ 1 , at_col_n responsive to an enabled address strobe signal add_stb.  
           [0015]    The bit transition detecting unit  30  is provided with the lower bit address signals, e.g., at_col_ 0  and at_col_ 1  when the burst length BL is 2, applicable to the burst length among the output signals at_col_ 0 , at_col_ 1 , at_col_n of the address latches  20 ,  22 ,  24 , and determines whether or not inverting an upper bit address signal, e.g., A 1  when BL is 2, according to a logic state of the lower bit address signal, e.g., A 0  when BL is 2, thereby transferring output address signals at 1 _ev and at 1 _od to the following predecoder (not shown).  
           [0016]    Referring to FIG. 3, there is provided an operational timing diagram of the address buffering circuit in FIG. 1. In FIG. 3, if column addresses A 0  and A 1  having the waveform of (a) and (b) are inputted, two signals out_ 0  and out_ 1  having the waveform of (d) and (e) are simultaneously generated in synchronization with a rising edge of an internally generated clock signal clkp 4  having the waveform of (c).  
           [0017]    Subsequently, if there is coupled an address strobe signal add_stb having the waveform of (f), which is a kind of internal clock control signals, the internal signals, e.g., at_col_ 2 , at col_n, except the lower bit signals at_col_ 0  and at_col_ 1  corresponding to the burst length are generated in synchronization with the address strobe signal add_stb while the internal signals at 1 _ev and at 1 _od corresponding to the even cell and the odd cell, respectively, are outputted to have the waveform of (h) after being delayed for a certain delay time td by the bit transition detecting unit  30 .  
           [0018]    Meanwhile, an access time of data corresponding to the inputted column address is determined by the latest signal. Therefore, as described above, because the output address signals at 1 _ev and at 1 _od of the bit transition detecting unit  30  are generated in the end, the access time of the column addresses is decided by the generation time of the output address signals at 1 _ev and at_od.  
           [0019]    In short, because the output address signals atl_ev and at 1 _od, which are a part of internal signals to be used in performing a column access operation after being provided to address predecoders, are delayed by the bit transition detecting unit  30  including two or more inverters. The internal address signals at 1 _ev and at 1 _od are generated as being delayed for the certain delay time after the address strobe signal add_stb is inputted. This results in the problem of delaying the column access time and, thus, substantially deteriorating the operational speed of the memory device.  
         SUMMARY  
         [0020]    In accordance with one aspect, the disclosed column address buffering apparatus may include a plurality of address buffers for receiving and buffering column address signals to thereby output buffered column address signals and a bit transition detecting unit for receiving lower bit address signals corresponding to a burst length among the buffered column address signals and for selectively outputting a most significant bit address signal among the lower bit address signals or an inverted signal of the most significant bit address signal according to logic states of the rest of the lower bit address signals. The disclosed apparatus may also include a first address latch for supplying corresponding following predecoders with an output signal of the bit transition detecting unit in response to an address strobe signal and a second address latch for receiving buffered address signals which do not correspond to the burst length among the buffered address signals and providing corresponding following predecoders with the received buffered address signals in response to the address strobe signal.  
           [0021]    In accordance with the disclosed apparatus, there is provided a column address buffering circuit for use in memory devices such as a DDR DRAM for receiving column addresses and internally buffering the column addresses. In the buffering process, the buffering circuit may generate specific internal address signals having different paths according to a burst length before an address strobe signal is inputted thereto so as to synchronize the generation time of the specific internal address signals with those of other internal address signals. As a result, it is possible to steeply shorten the column access time by removing an unnecessary time delay. That is, the inventive column address buffering circuit is configured to position a bit transition detecting unit related to generating the specific internal address signals corresponding to an odd cell and an even cell in front of an address latch for generating internal address signals at the same time of the address strobe signal being coupled, so that the specific internal address signals can be produced when the other internal address signals are generated.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    [0022]FIG. 1 is a block diagram of a conventional column address buffering circuit;  
         [0023]    [0023]FIG. 2 is a circuit diagram of the bit transition detecting unit of FIG. 1;  
         [0024]    [0024]FIG. 3 is an operational timing diagram of the address buffering circuit of FIG. 1;  
         [0025]    [0025]FIG. 4 is a block diagram of a column address buffering circuit;  
         [0026]    [0026]FIG. 5A is a circuit diagram of the bit transition detecting unit of FIG. 4;  
         [0027]    [0027]FIG. 5B is a circuit diagram of the address latch of FIG. 4;  
         [0028]    [0028]FIG. 6 is an operational timing diagram of the column address buffering circuit of FIG. 4;  
         [0029]    [0029]FIGS. 7 and 8 are operational timing diagrams of the bit transition detecting unit of FIG. 4 according to a bit transition detecting state; and  
         [0030]    [0030]FIG. 9 is a circuit diagram of the bit transition detecting unit of FIG. 4. 
     
    
     DETAILED DESCRIPTION  
       [0031]    Referring to FIG. 4, a block diagram of a column address buffering circuit is shown. The column address buffering circuit comprises a plurality of address buffers  110 ,  120 ,  130  for receiving and buffering column address signals A 0 , A 1 , An, a bit transition detecting unit  200  for outputting an internal signal sel_at for an even cell by using lower column address signals corresponding to a burst length and a multiplicity of address latches  310 ,  320  for receiving the internal signal sel_at and output signals of the address buffers  120 - 130  and providing internal address signals to following column predecoders.  
         [0032]    As shown in FIG. 5A, the bit transition detecting unit  200  includes a control signal generating block  210  for producing a pair of control signals set and setb and an output block  220  for selectively providing the address latch  310  with the output signal out_ 1  of the address buffer  110  or an inverted signal of the output signal out_ 1  in response to the control signals set and setb.  
         [0033]    The control signal generating block  210  includes a first NOR gate NOR  1  for logically summing input signals A and B, an inverter IN 1  for inverting an output signal of the first NOR gate NOR 1 . The control signal generating block  210  further includes a first transmission gate MT 1  for transferring the output signal out_ 0  of the address buffer  110 , an NMOS transistor MN 1  for connecting an output node N of the first transmission gate MT 1 , which is turned on when the input signals A and B having a low state are inputted, to a ground voltage node. The block  210  also includes a delay for delaying the output signal out_ 0  transferred through the first transmission gate MT 1  for a preset time, a second NOR gate NOR 2  for producing the control signal set based on a delayed signal outputted from the delay  5  and the output signal out_ 0  and an inverter IN 2  for inverting the control signal set to thereby generate the inverted control signal setb.  
         [0034]    Herein, the input signal A is produced to have a logic low state in case the burst length is 2 and a logic high state for other cases and the input signal B is generated to have a logic low state when a burst type is a sequential type and a logic high state in case the burst type is an interleave type.  
         [0035]    The disclosure in connection with FIG. 5A is an example based on a burst length of 2. Accordingly, the bit transition detecting unit  200  is configured to internally process the address signal A 1  by using the address signal A 0  among the column address signals A 0 , A 1 , An.  
         [0036]    The output unit  220  has second and a third transmission gates MT 2  and MT 3  for selectively providing the address latch  310  with the output signal out_ 1  or the inverted signal of the output signal out_ 1  as the internal signal sel_at according to logic states of the control signals set and setb.  
         [0037]    As shown in FIG. 5B, an exemplary address latch  310  has an even cell address output block  311  for receiving the internal signal sel_at outputted from the bit transition detecting unit  200  in response to an address strobe signal add_stb, latching the internal signal sel_at and providing a following predecoder with an even address signal at 1 _ev. The address latch  310  also includes an odd cell address output block  312  for receiving the output signal out_ 1  in response to the address strobe signal add_stb, latching the signal out_ 1  and supplying a following predecoder with an odd address signal at 1 _od. Fourth and a fifth transmission gates MT 4  and MT 5  transfer the output signal sel_at of the bit transition detecting unit  200  and the output signal out_ 1  of the address buffer  120 , respectively, responsive to the address strobe signal add_stb.  
         [0038]    The followings explains, in detail, the operation of the column address buffering circuit with reference to FIGS.  4  to  6 . At first, the address buffers  110  and  120  receive the column address signals A 0  and A 1  and output the signals out_ 0  and out_ 1 , respectively, in response to the internal clock control signal clkp 4 .  
         [0039]    In the meantime, in the bit transition detecting unit  200 , if at least one of the input signals A and B has a logic high state, the control signal generating block  210  always produces the control signals set and setb having a logic high state and a logic low state, respectively, and, thus, at the output block  220 , the output signal out_ 1  is outputted as it is through the second transmission gate MT 2 .  
         [0040]    Further, if both of the input signals A and B have a logic low state and the output signal out_ 0  of the address buffer  110  has a logic low state, the control signals set and setb are also outputted to have a logic high state and a logic low state, respectively and, thus, at the output block  220 , the output signal out_ 1  is also outputted as it is through the second transmission gate MT 2 .  
         [0041]    Conversely, if both of the input signals A and B have a logic low state and the output signal out_ 0  of the address buffer  110  has a logic high state, the control signals set and setb are outputted to have a logic low state and a logic high state, respectively and, thus, at the output block  220 , the inverted signal of the output signal out_ 1  is outputted as the internal signal sel_at through the third transmission gate MT 3 .  
         [0042]    According to the operational timing diagram of the column address buffering circuit shown in FIG. 6, if the column address signals A 0  and A 1  having the waveform of (a) and (b) are inputted, two output signals out_ 0  and out_ 1  having the waveform of (d) and (e) are simultaneously generated in synchronization with a rising-edge of the internal clock control signal clkp 4  described at (c). At this time, the bit transition detecting unit  200  produces the signal sel_at having the waveform of (f) determined by changing the logic state of the output signal out_ 1  according to the logic state of the output signal out_ 0 .  
         [0043]    Then, the address latch  310  transfers the internal signal sel_at outputted from the bit transition detecting unit  200  to a following predecoder (not shown) in response to the address strobe signal add_stb. Another address latch (e.g.,  320 ) generates an output signal (e.g., at_col_n) to its following predecoder responsive to the address strobe signal add_stb.  
         [0044]    As a result, because the generation of the internal column address signals described at (h) and (i) is performed in synchronization with the generation of the address strobe signal add_stb shown at (g), it is possible to eliminate the delay time unnecessarily spent after the address strobe signal add_stb is inputted in the conventional column address buffering circuit.  
         [0045]    [0045]FIGS. 7 and 8 show operational timing diagrams of the bit transition detecting unit  200  in FIG. 4 according to a bit transition detecting state. In FIG. 7, there is described a timing diagram in case both of the address signals A 0  and A 1  have a logic high state. On the other hand, in FIG. 8, there is illustrated a timing diagram in case the address signals A 0  and A 1  have a logic high state and a logic low state, respectively.  
         [0046]    Referring to FIG. 7, the inverted signal of the output signal out_ 1  is outputted as the internal address signal at 1 _ev by the internal signal sel_at generated prior to the address strobe signal add_stb is actuated. That is, the upper address signal out_ 1  is inverted from the logic high state to the logic low state and outputted.  
         [0047]    Referring to FIG. 8, the inverted signal of the output signal out_ 1  is outputted as the signal at 1 _ev by the internal signal sel_at produced prior to the address strobe signal add_stb is enabled.  
         [0048]    Moreover, the column address buffering circuit disclosed herein is not limited to the burst length of 2. That is, it can be applicable to other burst lengths. For example, in case the burst length is 4, the disclosed circuit detects the logic states of the column address signals A 1  and A 0  to thereby internally process a column address signal A 2 . In this case, because a signal is internally inverted by the column address signals A 0  and A 1  when A 0  has a logic high state and A 1  has a logic high state, the column address buffering circuit is configured to invert an internal signal out_ 2  generated by a column address signal A 2  when both of A 1  and A 0  have a logic high state. FIG. 9 shows a circuit diagram of the bit transition detecting unit  200  in FIG. 4 in case the burst length is 4.  
         [0049]    The disclosed column address buffering circuit reduces the generation time of the internal column address signals and, thus, the column access time of a memory device such as a synchronous semiconductor device can be substantially reduced.  
         [0050]    Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all embodiments of the teachings of the invention fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.