Abstract:
A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the elevated voltage levels and produce communications at an output voltage level equal to the supply voltage indigenous to the device. A high-voltage tolerant driver includes a plurality of output drive devices capable of tolerating an overvoltage, sustaining an electrical connection to an elevated voltage level, and producing an output voltage at an indigenous supply level. An initial pullup drive circuit is coupled to the plurality of output drive devices and produces an initial elevated drive voltage to the plurality of output drive devices. A sustain pullup circuit is coupled to the plurality of output drive devices and produces a sustained output voltage at the indigenous supply level.

Description:
TECHNICAL FIELD 
   The present invention relates to bidirectional port drivers. More specifically, the present invention relates to port drivers tolerant of operating environments requiring an interface with voltages higher than the power supply of the circuit containing the port driver. 
   BACKGROUND ART 
   In electronic systems, subsystem building blocks are frequently implemented in separate integrated circuit devices. To communicate with one another, the building blocks have I/O pads interconnected with one another. In the evolution of integrated circuit fabrication processes, the operating voltages have progressively diminished. In interconnecting subsystem building blocks, integrated circuit devices operating at different supply voltages will be connected by their I/O pads. Across the interconnects of the various integrated circuit devices various combinations of voltages will interact as high logic level signals are communicated. 
   Generally there is no problem for a device with a lower supply voltage driving a device operating from a higher supply voltage. Additionally, there is typically no problem with the higher supply voltage level being applied to a tristated pulldown only device in the lower supply voltage realm. A problem arises in a CMOS integrated circuit technology when a tristated PMOS pullup device in a low supply voltage realm is driven to a high logic level by a device in a high supply voltage realm. 
   With reference to  FIG. 1 , a 3 volt (V) realm  103  connects to a 5 V realm  105  in a schematic diagram of a prior art interconnect network  100  with mixed supply voltages. A 3 V output pullup device  112  connects between a 3 V supply  113 , a 3 V input  111 , and a 3 V I/O pad  133 . A source-substrate diode  116  and a drain-substrate diode  117  connect in parallel from the source and drain respectively of the 3 V output pullup device  112  to a 3 V pullup substrate node  119 . A source-substrate connection  118  connects between the 3 V pullup substrate node  119  and the 3 V supply  113 . A 3 V output pulldown device  114  connects between the 3 V input  111 , the 3 V output pullup device  112 , the 3 V I/O pad  133 , and ground. 
   A 3 V input pullup device  122  connects between a 3 V output  121 , the 3 V supply  113 , and the 3 V I/O pad  133 . A 3 V input pulldown device  124  connects between the 3 volt output  121 , the 3 V input pullup device  122 , the 3 V I/O pad  133 , and ground. 
   A 5 V output pullup device  132  connects between a 5 V supply  115 , a 5 V input  131 , and a 5 V I/O pad  135 . A 5 V output pulldown device  134  connects between the 5 V input  131 , the 5 V output pullup device  132 , the 5 V I/O pad  135 , and ground. 
   A 5 V input pullup device  142  connects between a 5 V output  141 , the 5 V supply  115 , and the 5 V I/O pad  135 . A 5 V input pulldown device  144  connects between the 5 V output  141 , the 5 V input pullup device  142 , the 5 V I/O pad  135 , and ground. 
   The output of the 3 V output pullup device  112 , when tristated, presents a p-n diode connection, in the form of the drain-substrate diode  117 , from an output drain diffusion to substrate. Even though the 3 V output pullup device  112 , is a tristated PMOS FET, the high logic level from the 5 V realm  105  will conduct through the diode and cause high current and possibly latchup conditions that may damage the 3 V realm  103  device. 
   In an effort to solve problems with high input bias levels applied to input diffusions and substrates, previous port drivers have incorporated complex networks for switching substrate biasing to protective voltage levels. What is needed is a port driver operating in a low-voltage realm that is tolerant of high voltages applied from external system devices without a burden of incorporating complex networking for switching the biasing of the substrate. Additionally, such a low-voltage realm port driver ideally drives a high logic level output to the full supply level of the indigenous voltage realm. 
   SUMMARY 
   A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high supply voltage realm. The plurality of output drive devices are capable of sustaining a continuous electrical connection to the elevated voltage levels and produce communications at an output voltage level equal to the supply voltage indigenous to the device. The plurality of output drive devices maintain communications to the high supply voltage realm without sustaining damage and without allowing high currents to damage the device. An initial NMOS pullup drive circuit is connected to the plurality of output drive devices and produces an initial elevated drive voltage that allows the plurality of output drive devices to attain an output drive level at the full supply voltage. The initial NMOS pullup drive circuit contains delay elements operating in sequence that provide a staggering of the initial elevated drive voltage providing slew rate control at the output. A sustaining NMOS pullup circuit connects to the plurality of output drive devices and produces a continuous output drive voltage for maintaining output signaling at the full supply voltage. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a schematic diagram of a prior art interconnect network with mixed supply voltages. 
       FIG. 2   a  is a schematic diagram of an exemplary high voltage tolerant port driver. 
       FIG. 2   b  is a waveform diagram of initial response driving signals corresponding to the exemplary high voltage tolerant port driver of  FIG. 2   a.    
       FIG. 3  is a schematic diagram of an exemplary high voltage tolerant port driver with a further exemplary sustain circuit. 
   

   DETAILED DESCRIPTION 
   With reference to  FIG. 2   a,  a pullup/pulldown circuit  204  connects to an I/O pad  297  in an exemplary high voltage tolerant port driver  200 . The pullup/pulldown circuit  204  is driven by a pullup enable input  205  and a pulldown enable input  245 . The pullup enable input  205  connects to a pullup enable inverter  208 . The pullup enable inverter  208  connects to a first input of a pullup NOR gate  212 . The pullup NOR gate  212  connects to a control input of an NMOS pullup device  216 , a delay block  220 , and a pulldown inverter  232 . The delay block  220  connects to a pullup buffer  224  which connects to an input of a capacitor  228 . An output of the capacitor  228  connects to an output of the NMOS pullup device  216  and to a first pullup slew rate resistor  230   a.  A second input of the NMOS pullup device  216  is connected to a low-voltage supply  213 . An output of the pulldown inverter  232  connects to each control input of a plurality of input pulldown devices  233   a,    233   b,    233   c.    
   A plurality of pull up slew rate resistors  230   a,    230   b,    230   c  connect to the output of the capacitor  228 . Each output of the plurality of pullup slew rate resistors  230   a,    230   b,    230   c  connects to a corresponding control input of one of a plurality of NMOS output drive devices  207  and a corresponding second input of each the plurality of input pulldown devices  233   a,    233   b,    233   c.    
   A pulldown enable inverter  248  connects to the pulldown enable input  245  and to a first input of a pulldown NOR gate  252 . An output of a last pull up slew rate resistor  230   c  connects to a second input of the pulldown NOR gate  252 . A pulldown buffer  256  connects to an output of the pulldown NOR gate  252  and an input of a first pulldown slew rate resistor  270   a.  A plurality of pulldown slew rate resistors  270   a,    270   b,    270   c  connects between the output of the pulldown buffer  256  and a second input of the pullup NOR gate  212 . Each output of the plurality of pulldown slew rate resistors  270   a,    270   b,    270   c  connects to a respective control input of one of a plurality of NMOS output pulldown devices  275   a,    275   b,    275   c.  Each one of the plurality of NMOS output pulldown devices  275   a,    275   b,    275   c  connects in parallel between an output of the pullup/pulldown circuit  204  and ground. 
   A first pullup sustain inverter  266   a  connects between a pullup sustain input  263  of a sustain circuit  260 , an input of a second pullup sustain inverter  266   b,  and a control input of a second NMOS sustain pulldown device  273   b.  A first PMOS sustain pullup device  276   a  and a second PMOS sustain pullup device  276   b  are cross-coupled to one another and each device has a first input connected to a pump voltage input  261 . A first NMOS sustain pulldown device  273   a  is connected at a control input to an output of the pullup sustain inverter  266   b  and at a second input to the first PMOS sustain pullup device  276   a  and a control input of a third NMOS sustain pullup device  278 . The second NMOS sustain pulldown device  273   b  connects between an output of the second PMOS sustain pullup device  276   b  and ground. The third NMOS sustain pullup device  278  connects between the low-voltage supply  213  and a pullup resistor  291 . The pullup resistor  291  connects to an I/O pad  297 . The I/O pad  297  connects to a capacitive load  299 . 
   The plurality of NMOS output drive devices  207  is comprised of, for example, a plurality of NMOS output pullup devices  235   a,    235   b,    235   c.  The plurality of NMOS output pullup devices  235   a,    235   b,    235   c  connect in parallel between the low-voltage supply  213  and the I/O pad  297 . 
   With reference to  FIG. 2   b  and in continuing reference to  FIG. 2   a,  a rising edge of a Drive_up signal  215  is applied to the pullup enable input  205  at t 0  (time zero)  225  in an exemplary initial response driver waveform diagram  250 . To propagate a high logic level to the I/O pad  297 , the positive-going edge of the Drive_up signal  215  is applied to the pullup enable input  205  and propagates through the pullup enable inverter  208 . The positive-going edge becomes a low-level signal input to the pullup NOR gate  212  and causes a high-level signal at the control input of the NMOS pullup device  216 . The output of the NMOS pullup device  216  produces a drive gate signal  229  at the control inputs of the plurality of NMOS output drive devices  207 . The NMOS pullup device  216 , an NMOS FET device, raises the drive gate signal  229  to the threshold limit voltage  292  which is, for example, one NMOS FET device threshold below the voltage on the low-voltage supply  213 . 
   The high voltage level at the output of the NMOS pullup device  216  is applied to the first pullup slew rate resistor  230   a.  The output of the first pullup slew rate resistor  230   a  will pull up the control input to a first NMOS output pullup device  235   a.  The series resistance of the first pullup slew rate resistor  230   a  and the capacitance of the gate of the first NMOS output pullup device  235   a  produce an integrating effect on the drive gate signal  229  immediately after t 0    225  known as slew rate control. The same effect is experienced at each succeeding combination of pullup slew rate resistor  205   b,    205   c  and control input of each NMOS output pullup device  235   b,    235   c  until the threshold limit voltage  292  is attained. 
   The plurality of NMOS output pullup devices  235   a,    235   b,    235   c  is configured as source follower transistors. Due to body effect, the gate-to-source component of the input capacitance of each one of the plurality of NMOS output pullup devices  235   a,    235   b,    235   c  is about one third the magnitude of the gate-to-source capacitance of each one of the plurality of NMOS output pulldown devices  275   a,    275   b,    275   c.  For a balanced slew rate control in both a pull-up and a pull-down transition, the resistance of the plurality of pull up slew rate resistors  230   a,    230   b,    230   c  is selected to be three times the magnitude of the resistance of the plurality of pulldown slew rate resistors  270   a,    270   b,    270   c.    
   Signal transitions (not shown) resulting from the rising edge of the Drive_up signal  215  propagate through the delay block  220  and produce a corresponding rising edge on a Delay_up signal  221  after a boost delay time  294 . The Delay_up signal  221  is produced by the pullup buffer  224  and applied to the input of the capacitor  228 . The Delay_up signal  221  produces a boost voltage  296  at the output of the capacitor  228  elevating the Drive_gate signal  229  to a drive gate voltage  298  which is higher than the low-voltage supply  213 . The drive gate voltage  298  applied to the control inputs of the plurality of NMOS output drive devices  207  is a sufficient voltage to elevate the voltage at an output of the plurality of NMOS output drive devices  207  to the voltage of the low-voltage supply  213 . The boost voltage  296  produced by the Delay_up signal  221  is applied to the capacitor  228  and sustains the drive gate voltage  298  for a finite amount of time as losses discharge the capacitor  228 . 
   A value C of the capacitor  228  is based on an expression derived from an analysis of a network at an interface of the capacitor  228  to the plurality of NMOS output drive devices  207 . The expression 
                 Δ   r     ×     g   m         C   +     C   gs         =     ln   ⁢         Δ   r     ×     g   m         C   gs               
can be solved for the value C of the capacitor  228 , where Δ r  is the boost delay time  294 , C gs  is a gate-to-source component of input capacitance of the plurality of NMOS output drive devices  207 , and g m  is the gain of the plurality of NMOS output drive devices  207 . The value of the capacitor  228  is about, for example, 0.8 pF.
 
   The boost delay time  294 , Δ r , is selected to allow enough time for the capacitor  228  to charge up to an effective voltage to drive the plurality of NMOS output drive devices  207 , yet not so long as to detract from the overall circuit delay. The plurality of NMOS output drive devices  207  is configured as source follower transistors. Due to body effect, the input capacitance is not the sum of each individual gate-to-source capacitance where a source node is connected to ground. A source node of each device varies in voltage with the change in voltage on the I/O pad  297 . An effective input gate capacitance C x  of the plurality of NMOS output drive devices  207  is less than a gate-to-source capacitance C gs  of the NMOS output drive devices  207  if the respective source nodes are connected to ground. 
   Using the effective input gate capacitance C x , the magnitude of the boost voltage  296  is given by 
           Vcc   ×       C     C   +     C   x         .           
The drive gate voltage  298  attained is given by
 
               (       V   CC     -     V   Tn       )     +     Vcc   ×     C     C   +     C   x             ,         
where V Tn  is the NMOS device threshold of the plurality of NMOS output drive devices  207 .
 
   To provide a continuing high-level voltage at the I/O pad  297 , a low-level enable signal (not shown) is applied to the pullup sustain input  263  of the sustain circuit  260 . The low-level enable signal produces a high-level signal from the output of the first pullup sustain inverter  266   a  to the control input of the second NMOS sustain pulldown device  273   b  and a low-level signal from the output of the second pullup sustain inverter  266   b  to the control input of the first NMOS sustain pulldown device  273   a.  The second NMOS sustain pulldown device  273   b  is turned on and the first NMOS sustain pulldown device  273   a  is turned off allowing the cross-coupled combination of the first PMOS sustain pullup device  276   a  and the second PMOS sustain pullup device  276   b  to apply a pump level voltage (not shown) to the control input of the third NMOS sustain pullup device  278 . The pump level voltage is applied to the pump voltage input  261  and is produced by a separate charge pump (not shown). The pump level voltage turns the third NMOS sustain pullup device  278  on, connecting the low-level supply  213  to the pullup resistor  291  and producing a full-level voltage from the low-voltage supply  213 . No device threshold drop is present in the output voltage on the I/O pad  297  due to the pump level voltage on the control input of the third NMOS sustain pullup device  278 . 
   Prior to to  225 , no signal transition is driven to the I/O pad  297  and a condition exists where a low logic level is applied to both the pullup enable input  205  and the pulldown enable input  245 . The application of the low logic level to both inputs causes the pullup/pulldown circuit  204  to be tristated. The low logic level applied to both the pullup enable input  205  and the pulldown enable input  245  produces a high-level signal at the control inputs of the plurality of input pulldown devices  233   a,    233   b,    233   c  and a low-level signal at the control inputs of the plurality of NMOS output pulldown devices  275   a,    275   b,    275   c.  The low-level signal at the control inputs of the plurality of NMOS output pulldown devices  275   a,    275   b,    275   c  turns the devices off and produces a high impedance path from the I/O pad  297  to ground. The high-level signal at the control inputs of the plurality of input pulldown devices  233   a,    233   b,    233   c  turns the devices on, pulling down the control inputs to the plurality of NMOS output drive devices  207  and produces a high impedance path from the I/O pad  297  to the low-voltage supply  213 . Thus, the I/O pad is tristated from the output coming from the pullup/pulldown circuit  204  and the plurality of NMOS output drive devices  207 . 
   With reference to  FIG. 3 , a pullup/pulldown circuit  204  connects to an I/O pad  297  in an exemplary high voltage tolerant port driver  300  with a further exemplary sustain circuit  360 . The pullup/pulldown circuit  204  operates as explained, supra, with reference to  FIG. 2   a.  A first pullup sustain inverter  366  connects between a pullup sustain input  363  of the sustain circuit  360  and a first input of a sustain pass gate  368 . A sustain pass gate input  364  connects to the control input of the sustain pass gate  368 . A first PMOS sustain pullup device  376   a  and a second PMOS sustain pullup device  376   b  are cross-coupled to one another and each device has an input connected to a pump voltage input  361 . 
   A control input of an NMOS sustain pulldown device  373  connects to an output of the sustain pass gate  368  and an output of the first PMOS sustain pullup device  376   a.  A control input of a third NMOS sustain pullup device  378  connects to an output of the second PMOS sustain pullup device  376   b  and a second input of the NMOS sustain pulldown device  373 . The third NMOS sustain pullup device  378  connects between the low-voltage supply  313  and a pullup resistor  391 . The pullup resistor  391  connects to the I/O pad  297 . The I/O pad  297  connects to the capacitive load  299 . 
   With reference to  FIGS. 2 and 3 , a separate high-voltage supply connects to the I/O pad  297  in operation and produces a high voltage on the a low-voltage reverse biased drain-substrate diode (not shown) at the output of the plurality of NMOS output pulldown devices  275   a,    275   b,    275   c  or the source-substrate diode (not shown) at the output of the plurality of NMOS output drive devices  207 . As discussed, supra, with reference to  FIG. 1 , the application of an externally supplied high voltage to a pulldown (NMOS) device is not critical. The plurality of NMOS output drive devices  207  and each one of the plurality of NMOS output pullup devices  235   a,    235   b,    235   c  in a tristate condition, functions as a reversed biased diode between the I/O pad  297  and ground. The pullup/pulldown circuit  204  and the accompanying low-voltage domain are protected from overvoltage of a magnitude typical of mixed interface voltages in a system environment. The overvoltage protection is due to the presence of the reverse bias diodes at both the pullup and the pulldown output. In this way, the low-voltage realm connecting to the high voltage tolerant port driver is protected from latchup and damage due to typical overvoltage experienced in system operation. 
   Although the present invention has been described in terms of specific exemplary embodiments, a skilled artisan will recognize that certain changes and modifications can be made and still be within a scope of the appended claims. For example, the pullup/pulldown transistors described are MOS devices which may readily be replaced by other transistor types or tristatable devices. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.