Abstract:
A programmable number of pulses N, of one or more auxiliary frequencies fa, is inserted between pulses of the frequency f 1  to be processed. The resulting frequency N.f 1 , where N is a positive number (N can be fractional), is at any moment proportional to input frequency f 1  where N, the proportionality factor, varies at will and can assume any positive number value. Pulse insertion results in a frequency shift of positive or negative value and succeeds continuously and without any information loss i.e. the pulse train has not to be interrupted and is processed &#34;on (the) line&#34;. The same method described used for higher frequencies eliminates the known ±1 count problem as it can register fractions of a pulse.

Description:
BACKGROUND OF THE INVENTION 
     A. Field of the invention 
     A frequency counter, being a digital instrument, is limited in its range by the speed of its logic circuitry. Today the state of the art at high-speed logic allows the construction of direct (without any pre-scaling) digital frequency counters in IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT--December 1977--Volume I.M.26--Number 4--p.p. 396-402: DEVELOPING PROGRAMMABLE BROAD-BAND COUNTING CIRCUITS FOR HIGH-SPEED DATA TRANSMISSION AND FREQUENCY DIVISION by A. PAPHITIS. 
     Using down conversion techniques, frequency measurement extension up to 40 GHz is made possible. 
     In conventional counters, however, accuracy drops with input frequency if the gate period, during which the measurement occurs, is held constant. With low frequencies absurdly long measurement times would be needed to keep resolution. 
     To measure a frequency of IHz with 1% precision, for instance, the gate period should be larger than 100 seconds. 
     The method used to shift a given frequency of unknown value to, in the case of low frequency counters, higher frequency values that can be measured, fast and precisely, can be used in other fields too. A typical application would be a digital mixer, or modulator and demodulator, system as the product Nf 1  can be interpreted as the product of two frequencies f 1  and f 2  where N=f 2 . 
     B. Description of the Prior Art 
     Of the various methods to get around the problem of low frequency counters, the most notable are reciprocal counters (R.C.&#39;s) and counters using PHASE-LOCKED LOOPS (PLL&#39;s). R.C.&#39;s measure the period and then arithmetically convert to get the frequency. R.C.&#39;s presently work to 500 MHz, but the advantage of constant resolution disappears when the input frequency exceeds the reciprocal unit clock frequency, usually 10 MHz, and a second counter or a higher unit clock frequency is needed to measure such frequencies accurately, both being extremely uneconomical. R.C.&#39;s are very complex circuits. Several counters of various stages, depending on frequency range and accuracy requirements to be covered, are needed. As described for instance in ELECTRONICS, Mar. 4, 1976, p.p. 100-101: COUNTER INVERTS PERIOD TO MEASURE LOW FREQUENCY by Matthew L. Fichtenbaum, several counter stages are needed to measure the period of the input signal by counting the number of unit clock frequency pulses, N, in one period and inverting the result. While with a conventional counter a 1% accuracy is obtained without need of changing the frequency range, for frequencies above 100 Hz and a gate time of 1 second, this is not the case in R.C.&#39;s. To measure, for instance 100 KHz with the above mentioned unit clock frequency of 10 MHz, 100 pulses of the clock frequency are registered. To measure 100 Hz with the same frequency would require a five stage decimal counter merely to count the period duration. Inversion is now performed by dividing a number K (which is much larger than N if the lowest frequency to be counted is for instance 0.01 Hz, then N=10 9 ) by the count of N where a bit comparator of several stages (if N=10 9 , nine stages) to compare the period count with the count of another auxiliary counter of equal length (in the example, nine stages) and a third counter (of more than nine stages) to count K are necessary and lastly, is necessary too, the readout display counter. Several techniques are known to reduce this effect but the main problem remains the same, which ends always in a big implementational effort. Further another serious disadvantage is the loss of information since, during inversion, the counter input is disabled. As we shall see later it is important to note that this is the case even if the input frequency did not change or presents slight change. 
     Consequently a frequency input signal may not be continuously monitored which is important for instance in ratemeters (heart rate monitoring, motor regulation applications, car velocity and acceleration control, etc.) 
     Of the many known low frequency measurement methods, the R.C.&#39;s have been mentioned because of their popularity among instrument manufacturers. It should be mentioned, however, that the PLL approach, although versatile, has its share of problems. The frequency limit here is 100 MHz and it is obvious that it is easier to build a 100 Mhz pulse counter than to implement a 100 MHz PLL. This, however, is not the main difficulty. PLL&#39;s tend to lock on subharmonics and behave strangely with narrow pulses and modulated FM and AM signals. Because of high frequency limitations of LSI, PLL&#39;s will probably never reach frequencies much higher than 100 MHz. Last but not least, PLL prices are still high. 
     When measuring events between two time marks (or time intervals between two events) several error terms add together, for example, time base error, trigger error, etc. as described in ELECTRONIC DESIGN 24, Nov. 22, 1974, p.p. 162-167: MEASURE TIME INTERVAL PRECISELY by David Martin. One of the error sources described in the above mentioned work is the so-called ±1 count. This refers in the case of frequency (and not period) measurement to the fact that pulse counting always provides this inherent uncertainty, since there can usually be no guarantee of coherence between the input frequency and the gate time (in measuring periods, there is no coherence between input frequency and counted clock). 
     One of the consequences of the ±n count ambiguity (which can be greater than ±1) is that frequency counters are unable to register fractions of a pulse. Precision drops drastically with input frequency. A high frequency counter of a 1 Hz resolution at 100 MHz means a Δf/f=1 Hz/10 8  Hz=10 -8 . For the same counter at 100 Hz we have: 
     ti Δf/f=1/100=10 -2 . 
     Another important factor in counting pulses is the short term stability of the time base oscillator, related with fast phase fluctuations and random frequencies generated along with the desired frequency. The less time the measurement takes, the greater the uncertainty (for times of one second and less). Measuring very short periods, there is this additional limitation, forcing averaging, by measuring more than one event and dividing by the number of measurements to obtain the result, such method meaning loss of resolution. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     It is a primary object of the present invention to provide a direct frequency and pulse counting method to cover the low frequency range, below 100 Hz with frequencies of the order of 0.01 Hz or less, and the higher than 100 Hz frequency range up to 1 GHz or higher using only one frequency counter and measuring directly frequency values i.e. number of input pulses of the unknown pulse frequency f 1  divided by the gate period of the time base during which these pulses are being measured, in lieu of measuring the period of the unknown frequency f 1  and then inverting to obtain the frequency f 1 . 
     Another object of the present invention is to provide a novel arrangement for multiplying an unknown and constantly varying input frequency or number of input pulses of an incident pulse train by a controllable frequency or frequencies of known constant or varying values. 
     In its broadest aspect the present invention comprises a digital frequency process method in which a relatively high auxiliary frequency f b  which is normally known is consecutively diminished by dividing by factors of 2 A  (2 A  is an integer) until a comparison of the results with said first frequency f 1  shows said result to be equal to 10 z  f 1  where Z=1,2,3 . . . Said diminishing of the auxiliary frequency including the final step of dividing by a fraction of 2 A  to satisfy the above condition when f b  /f 1  is not a power of 2 A . 
     The frequency process method of this invention, in another aspect thereof comprises providing a first train of pulses having a first frequency f 1  ; dividing said first train of pulses into a plurality of x second trains of pulses; counting n pulses of a second frequency f b  for each pulses of each second train of pulses; and providing an output related to the total number of pulses of said second frequency which have been counted during a time base, said first and second frequencies obeying the following condition: 
     
         nf.sub.1 ≧f.sub.b ≧(n/x)f.sub.1. 
    
     In the preferred embodiment described herein the first train of pulses is divided into two trains of pulses (X=2) which are inverted with respect to each other and have half the frequency of said first frequency. In this case ten pulses of the second frequency (N=10) are injected between each second train pulse and the condition to be obeyed is 
     
         10f.sub.1 ≧f.sub.b ≧5f.sub.1 
    
     It will be seen from the above and from the following description of the preferred embodiment that the present invention uses &#34;pulse multipliers&#34; to produce auxiliary pulse trains and so on. 
     The invention uses &#34;pulse multipliers&#34; to produce auxiliary pulse trains of frequencies higher than the input frequency and then combines the auxiliary pulse trains to obtain an exact proportionality between f 1  and the combined frequency f s  of higher frequency than f 1 . Low and very low input frequencies are thus &#34;frequency translated&#34; or &#34;frequency shifted&#34; to a higher frequency range of a higher frequency precision, thus overcoming the known difficulty of conventional frequency counters where resolution drops with input frequency, the gate period, during which measurement occurs, being kept constant. 
     The invention will be best understood from the following description when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of version 1 of a digital frequency shifter which is the preferred embodiment of the invention; 
     FIGS. 2A and 2B are pulse charts showing the time of the various pulses of FIG. 1; 
     FIG. 3 is a block diagram of version 2 of a digital frequency shifter which is the preferred embodiment of the invention; 
     FIG. 4 is a pulse chart showing the timing of various pulses of FIG. 3; and 
     FIG. 5 is a multiply-by-two circuit configuration with corresponding pulse chart used in conjunction with FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the drawings, FIG. 1 shows a block diagram of a FREQUENCY SHIFTER digital circuit which is the preferred embodiment of the present invention. All the integrated circuits mentioned in the following description are of the CMOS logic family, manufactured by FAIRCHILD, U.S.A. (or MOTOROLA INC., U.S.A.) among other manufacturers. Clearly other types of logic families like high frequency ECL 1, II or III etc. or cheap TTL circuits are equally adequate. In the discussion of the preferred embodiment two versions will be distinguished depending on whether the auxiliary frequencies f b  and f a  are manually or automatically controlled. 
     Version 1: Manual control of f b  and f a   
     According to this version switch K 1  in FIG. 1 is closed (position 1). The Q output of D flip flop 25, which can be of the type 4013 (14013) of the CMOS logic family, is continuously set to logic one by applying the voltage V dd  through switch K 1  to its set input S. J K flip flop 1, which can be of the type 4027 (14027) has then both its inputs J and K tied on logic one potential, over Q output of IC 25. JK flip flop 1 is set to logic zero (output Q1=logic zero) by applying a logic one at its Reset input R through OR gate 29. 
     There are two ways to reset through OR gate 29. One is by momentarily closing switch 2 (position 1) whereby a logic one (V dd ), which in the case of CMOS corresponds to the positive connection of the power supply, is manually generated to give the RESET after the power supply is turned on. The other manner of resetting D flip flop 25 by means of a RESET PULSE which appears after each gate period of the time base t G . This gate period t G  is usually chosen to be 0.1 sec or 1 second or 10 sec etc. and is exactly the time period during which the input pulses of the (unknown) input frequency are counted. 
     The pulses of the frequency to be measured are applied to the clock input of JK flip flop 1 which acts as a divide-by-two unit. The first input pulse of f 1  turns Q 1  high (logic one) and Q 1  low (logic zero), the second turns Q 1  low and Q 1  high and so on. Odd pulses thus activate Q 1  and even pulses activate Q 1 . The signals at Q 1  and Q 1  are applied, respectively, to the clock inputs C of D flip flops 3 and 4 whose inputs (V dd ) are high. This turns Q 3  or Q 4  high which in turn is applied to a respective one of the two inputs of AND gates 5 or 6 of which the other input is tied to an auxiliary frequency f b . The enabled AND gate 5 or 6 transmits the pulses of f b  to the Enable input E of a respective counter 7 or 8 which, in this case, is a Binary Coded Decimal counter with separated outputs Q 0  through Q 3  to give a count readout in BCD code. These counters can be of the type 4518 (14518) which counts the trailing edges of the pulses applied to its Enable Input E, provided Clock Input C and Reset Input R are at V ss  potential (negative connection of the power supply corresponding to the logic zero of the CMOS). The count of ten (BCD number nine) pulses of the counter 7 is decoded at outputs Q 0  and Q 3 , through AND gate 9, and AND gate 32 (when enabled by Q 1 , to reset D flip flop 3 and counter 7. The enable condition of AND gate 32 will be discussed later. The ten count of counter 8 is decoded at corresponding outputs Q 0  and Q 3 , through AND gate 10 and OR gate 12 to reset D flip flop 4 and counter 8. When one (but not both) counter is still counting, AND gate 13 is disabled because one of its inputs Q 3  or Q 4  is logic zero, this zero then applied to one of the inputs of OR gate 14, of which the output f a  DISABLE is applied to one of the inputs of NOR gate 15 which acts as an inverter. Its output is then f a  (its other input being f a ) and is OR&#39;ed with auxiliary frequency 2 f a  to give again f a  at the output of OR gate 16. When both 7 and 8 are counting the output of AND gate 13 is logic one (its two inputs Q 3  and Q 4  are logic ones) which disables NOR gate 15 through OR gate 14 to give a logic zero at its output, which, in turn, is OR&#39;ed with the auxiliary frequency 2f a  to give 2f a  at the output of OR gate 16. 
     According to the above description, for each pulse counted by counter 7 or 8 there appear ten pulses of frequency f a  or 2f a  at the output of OR gate 16. After the tenth pulse of either counter 7 or 8, the output of AND gate 13 should remain logic one for one more period (except for 10f 1  =f b , in which case AND gate 13 is always disabled). This is done by applying the output of AND gate 13 to the D input of D flip flop 18 whose output Q remains logic one for one more period of f b  after both its input D and the output of AND gate 13 have turned logic 0. The output of D flip flop 18 is applied to the second input of OR gate 14. 
     In order to have the desired proportionality between the input pulse frequency f 1  on the one hand and the pulse frequency at the output of OR gate 16 on the other, the following conditions must be met: 
     
         2nf.sub.1 ≧f.sub.b ≧nf.sub.1                 (1) 
    
     f a  is chosen to be 
     
         f.sub.a =mf.sub.b                                          (2) 
    
     where both m and n are positive numbers. 
     In the special case discussed 
     
         m=2n=10                                                    (3) 
    
     and equations 1 and 2 simplify to: 
     
         10f.sub.1 ≧fb≧5f.sub.1                       (4) 
    
     or with 
     
         fa=10f.sub.b                                               (5) 
    
     
         100f.sub.1 ≧fa≧50f.sub.1                     (6) 
    
     Equation 4 indicates that if auxiliary frequency f b  is fixed, the input frequency can vary up to one octave, from fb/5 to fb/10. 
     The second condition to be met is that the count is only then right if counting of the pulses at the output of OR gate 16 is started after the first logic one level appears at Q 1  which, as already mentioned, turns Q 4  a logic one which makes output Q of D flip flop 31 a logic one applied to one of the inputs of AND gate 19. The other input of AND gate 19 receives a logic one from AND gate 23, provided equations (4) and (5) are satisfied. Equation (4) is controlled as follows: D flip flops 20 and 21 receive the output (Q 1 ) pulses of J K flip flop 1 which are applied to their respective clock inputs C. D input of D flip flop 20 is a logic one (V dd ) so that after the first clock pulse its Q output will turn logic one and be applied to the D input of D flip flop 21 whose output Q will go high after the second clock pulse since its D input was logic zero up to that moment (reset at beginning of the count by the application of a logic one to its R input by OR gate 29 which also resets D flip flop 22). This activates the Light Emitting Diode LED2, provided the D input of flip flop 22 remains at logic one, this being conditioned to the output of D flip flop 20. D flip flop 20 is reset through OR gate 24 either by the reset pulse coming from OR gate 29 at the beginning of each new count or by BCD counter 7 having counted ten pulses which produces a logic 1 at the output of AND gate 9. 
     If counter 7 counts less than 10 pulses of the frequency f b  for the time period of two periods of f 1  (f 1/2  always appears at Q 1 ) or less than 5 pulses for one period of f 1 , then the reset pulse at D flip flop 20 arrives after the second clock pulse has arrived at D flip flop 21 whereby the Q output of the latter turns logic one to make LED2 indicate that 
     
         fb&lt;5f.sub.1 
    
     and that equation 4 is not satisfied. 
     After passing through AND gates 9 and 32 and OR gate 11, the reset pulses of counter 7 are used to disable its input E by resetting D flip flop 3, whose output Q 3  turns logic zero to disable AND gate 5. 
     In order to reset D flip flop 3, however, AND gate 32 must be enabled by a logic one at the Q 1  output of J K flip flop 1. If there is no logic one at the Q 1  output of J K flip flop 1 after 10 counted pulses of f b , then this means that fb&gt;10f 1 , because counter 7 started counting after the first pulse of f 1  had been applied to the J and K inputs of J K flip flop 1 and Q 1  turns logic one after the second pulse so D flip flop 3 is not reset and counter 7 counts 10 more pulses to give a clock pulse which is applied to the C input of D flip flop 22 whose D input is logic one because the output Q of D flip flop 20 has already been reset by the first reset pulse of counter 7. After the application of this clock pulse to D flip flop 22, the Q output of the latter turns logic one and activates LED 1 to indicate that 10f 1  ≧f b  is not satisfied. Should equation 4 be satisfied, then the Q outputs of D flip flops 21 and 22 remain on logic level one and are used to enable AND gate 23 which in turn serves to enable AND gate 19. At the same time the second input pulse of f 1  must have turned the Q 1  of J K flip flop 1 to logic one which in turn is applied to the clock input of D flip flop 4 whose output Q 4  goes logic one and is applied to the clock input of D flip flop 31 of which the D input is on logic one (V dd ). A logic one then appears at the output of AND gate 19 to provide the COUNT ENABLE signal, indicating that the circuit is ready to count and that the pulses at the output of OR gate 16 are in a suitable proportion to the number of pulses at the input of the frequency f 1  to be measured. 
     It is important to note that after the COUNT ENABLE appears, the circuit is capable of counting even fractions of a period of the frequency f 1  since, after the second pulse edge of f 1 , the pulses at the output of OR gate 16 are always proportional to the number of input pulses, fractions included. Thus a fraction of a pulse of f 1  after mentioned first pulse of f 1  counter 30 is able to display the exact value of input frequency f 1  provided f 1  varies according to inequality 4. 
     The &#34;COUNT EMABLE&#34; output of AND gate 19 is applied both to the time base 28 to start the gate time period t G  and to one of the inputs of AND gate 17 to the other input of which is applied the output of OR gate 16 to enable this gate at the pulse frequency of OR gate 16. The output of AND gate 17 is then calibrated by calibrator 27, which in this case is done simply by shifting the decimal point by two positions to the left, and then applied at the input of a high frequency counter 30 which can reach up to 1 GHz or higher. 
     Input signals higher than 100 Hz to couner 30 are not of importance to the invention as presently described and will thus not be further considered. Reference is made, however, to the literature mentioned where such applications are extensively discussed and improved. The basic object of this invention, moreover, is to show that low frequency signals (less than 100 Hz) can be frequency shifted to higher frequency values and these registered by a common counter. 
     The calibrator 27 effects the divide-by-one-hundred shifting the decimal point of counter 30, which counts 100 pulses of frequency f a  or 2f a  per input pulse of frequency f 1  being able of registering even fractions of a pulse, two positions to the left, this being done by applying a logic one (or zero) to the corresponding decimal point of the display. 
     The auxiliary frequencies f a  and f b  are derived by dividing the auxiliary frequency 20f b  (RESULT f b ) by 2 and 10 using suitable integrated circuits 34 and 35. 
     Referring now to FIG. 2A, case 1 is an example where 10f 11  =f b  and counters 7 and 8 alternatively count 10 pulses of auxiliary frequency f b , per input pulse of f 11 . There is no pulse-overlapping (Q outputs of D flip flops 3 and 4 both high) and hence AND gate 13 is always disabled and counter 30 always receives the pulses of f a . The RESET PULSE from the time base, resets the system after 1.75 pulses of f 11  that is between the 18th and 19th pulses of f b  or after 175 pulses of f a . After calibration by 27 (decimal point shifting) the readout at counter 30 is 1.75. In this special case there is always proportionally between f 11  and f S , so t G1  starts with the very first pulse of f 11  (Case 2 and 3 only after Q 1  turns high). All pulses counted by counters 7 and 8 are processed, that is to say, each one of them gives ten output pulses at OR gate 16. 
     Case 2 in FIG. 2B is the opposite or lower limit for f b  where f b  =5f 12 . After the second input pulse edge of f 12  Q 1  of J K flip flop 1 turns high) there is always pulse overlapping. As we see from the FIG. 2, only after the second input pulse edge of f 12  is there proportionality between frequencies f 12  and f S . 
     As already discussed, D flip flop 18 together with OR gate 14 is used to keep the &#34;f a  DISABLE&#34; at logic one which otherwise would not be the case: after each tenth pulse of either counter 7 or 8 (except for 10f 1  =f b ), counter 30 receives pulses of the frequency of f S  =100f 12  whereby, after calibration by 27, it displays f 12 . Counter 7 counts 23 pulses but only 18 of them are processed. 
     Case 3 is the general case of f b  /5&gt;f13&gt;f b  /10. 
     After the second input pulse edge of f 13  Q 1  of J K flip flop 1 turns high and, as before, the time base enables the start of t G3 . Fifteen pulses of f b  or 153 of f a  (and 2f a ) are measured. Once more counter 30 counts pulses of the frequency 100f 13  but displays 1.00f 13 . Note that counter 7 counts 13 pulses but only 5 are processed. 
     It is further important to note that if we consider the frequency 20f b  as input frequency for the circuit of FIG. 1 and frequency f 1  as a frequency shift control signal the frequency f S  at the output of OR gate 17 is f s  =20f b  /K where 
     
         K=20f.sub.b /f.sub.s                                       (7) 
    
     and 2≧K≧1 
     Hence the circuit of FIG. 1 is effectively no more than a divide by K unit for frequency 20f b . 
     Version 2: Digital automatic control of f b  and f a   
     The DIGITAL AUTOMATIC FREQUENCY CONTROL, abbreviated DAFC, shown in FIG. 3, works as follows. In this mode of operation, switch K 1  of FIG. 1 is in position 2 (automatic) whereby set inputs S of D flip flop 25 is logic zero. The first input pulse of the unknown frequency f 1  is applied to the clock input C of D flip flop 25 then makes the output of said flip flop a logic one which serves as the START f b   enable signal indicated at the top of FIG. 3. Thus the output of D flip flop 25 (FIG. 1) is applied to the D input of D flip flop 48 in FIG. 3 which is clocked by 0.1f b1  and the output Q of which is applied to another D flip flop 49, also clocked by 0.1f b1  on the one side and on the other to one of the inputs of AND gate 44 of which the other input is tied to the Q output of D flip flop 49. These two flip flops delay the START f b  signal by at least one period of the frequency 0.1f b1  after which the output of AND gate 44 turns logic one to give START f b  DELAYED which is applied to one of the inputs of AND gate 50 to the other input of which is tied one of the auxiliary frequencies 0.1f b1 . The pulses at the output of AND gate 50 are applied at the Enable input of a two stage binary counter 51,52 which can be of the type 4520 (14520) DUAL BINARY COUNTER. Such mentioned counters have four divide-by-two stages with separated outputs Q 0 , Q 1 , Q 2 , Q 3 , and Enable input E which counts the trailing edges of the applied input pulses at E, provided its clock input C and its reset input R, over which the counter can be zeroed (reset), are both on logic zero potential. Two pulses of the frequency 0.1f b1  after &#34;START f b  &#34; turns logic one, counter 51 receives at its Enable input E a pulse, which turns its ouput Q 0  to logic one. Q 1  turns logic one after four pulses Q 2  after eight etc. Q 0  of counter 52 after 32 pulses, Q 1  of counter 54 after 64 pulses etc. Each of these Q outputs is applied to two D flip flops as clock inputs. Thus Q 0  of counter 51 feeds the clock inputs C of D flip flops 53 and 63, both with D inputs on logic one (V dd ) to disable AND gate 73, as Q of I.C. 53 turns low after a clock pulse at its clock input C. The other input of gate 73 is tied to the common RESET f b  signal. The output of gate 73 is applied to the RESET input of D flip flop 63. Similarly Q 1  of counter 51 works with D flip flops 54 and 64 and AND gate 74, Q 2  with D flip flops 55 and 65 and AND gate 75 and so on. 
     The Q outputs of D flip flops 63 through 70 are applied to one input of AND gates 83 through 90 respectively, the other input of these AND gates being tied to one of the Q outputs of binary counters 61 and 62 which comprise a Dual Binary Counter which is of the same type of the counter 51,52 already described. Thus the output of Q 0  of counter 61 is applied to one input of AND gate 83, Q 1  to AND gate 84 and so on. The output of AND gates 83 through 90 are OR&#39;ed by OR gates 93 through 99 and the result at the output of OR gate 99 (Result f b ) is applied to one of the inputs of NOR gate 26 (FIG. 1) at the other input of which is applied the RANGE CONTROL signal. 
     As all OR&#39;ed frequencies are synchronous and stand in a relation 1:2:4:8 . . . etc. the lowest frequency will predominate at the output of OR gate 99. This fact is similar to the one encountered when discussing the OR&#39;ing of frequencies f a  and 2f a  at the input of OR gate 16 in FIG. 1. Counter 61 receives pulses of the frequency 20f b1  at its enable input E. Its output Q 0  has the frequency 20f b2  =20fb 1  /2 and is applied, as mentioned, to AND gate 83 which is enabled by means of D flip flop 63. This frequency at the output of gate 83 is OR&#39;ed by OR gate 93 with the output of AND gate 84 which is enabled when the output of D flip flop 64 is logic one, which is the case when Q 1  of counter stage 51 turns logic one after four pulses of 0.1f b1  have passed since START f b  turned logic one. The output of OR gate 93 is OR&#39;ed with the output of AND gate 85 and then passes through OR gates 94 through 99 assuming the other inputs of these mentioned OR gates are logic zero. The results of these operations are shown in FIG. 4 where gates 83-85 are enabled. 
     FIG. 5 shows how the RESET f b  pulses are produced. An EXCLUSIVE OR gate 47 receives at one of its inputs the pulses from the Q 1  output of J K flip flop 1 and at the other input the same pulses delayed by two gates 45 and 46 that can be of the OR type. The output of OR gate 47 consists of short pulses in the rhythm of input frequency f 1  or twice the frequencies at the Q 1  output of J K flip flop 1. These pulses are applied, over time delay t 1  (FIG. 3), to the RESET inputs of D flip flops 53 through 60 and, without the delay, to those D flip flops 63 through 70 whose corresponding AND gates 73 through 80 had not been disabled through the D flip flop chain 53 through 60. Time delay t 1  is necessary in order to ensure resetting of D flip flops 63 through 70 t 1  seconds before D flip flops 53 to 60 since otherwise all AND gates 73 through 80 would be enabled by the Q outputs of the corresponding D flip flops 53 through 60 turning logic one on resetting. For the same reason, the reset pulses must be of short duration otherwise AND gates 73 through 80 will be enabled by the Q outputs of D flip flops 53 through 60 all turning logic one after the application of such reset pulses that must be of shorter duration than the propagation delay of the mentioned D flip flops. Alternatively, t 1  must be chosen larger. The example of FIG. 3 can be chosen to work with f b   max . =fb 1  =500 Hz and 2f a   max . =20f b1  =10,000 Hz. The output frequencies at the outputs Q 0  through Q 3  of counters 51 and 52 are as follows: 
     0.1fb 2  =25 Hz, 0.1fb 3  =12.5 Hz, 0.1fb 4  =12.5/2 Hz, 0.1fb 5  =12.5/4 Hz, 0.1fb 6  =12.5/8 Hz, 0.1fb 7  =12.5/16 Hz, 0.1fb 8  =12.5/32 Hz, 0.1fb 9  =12.5/64 Hz. 
     The corresponding frequencies of counters 61 and 62 vary respectively between 200fb 2  =5000 Hz and 200fb 9  =2500/64 Hz. 
     If f 1  is higher than 100 Hz, D flip flops 48 and 49 are reset before the Q output of D flip flop 49 turns logic one and none of D flip flops 53 through 60 is enabled. The result is a logic zero for &#34;RESULT f b  &#34; which is applied in FIG. 1 to one of the inputs of NOR gate 26 whose other input receives the RANGE CONTROL signal which, in this case, is also logic zero, so that the output of NOR gate 26 turns logic one and turns LED 3 on. A LED 4 is used to indicate that the right f b  is being used and that the counter is counting the pulses injected at J K flip flop 1 properly. 100 Hz is then the highest frequency in the described example where pulse multiplication or frequency shifting has been judged reasonable. Higher frequencies are indicated by LED 3 and can be measured by being directly applied at the input of counter 30 which counts frequencies directly up to 1 GHz. 
     The lowest frequency limit in the described example is ##EQU1## It must be noted that the circuits of FIGS. 1 and 3 are no more than an automatic period of estimation method for input frequency f 1 . What is done is to define an auxiliary frequency f a  within the limits of 50% or one octave (FIG. 3), as given by equation (6). Once f 1  is known up to 50%, which is the first approximation, the circuit of FIG. 1 inserts sufficient pulses between consecutive pulses of f 1  to produce the frequency shift. In the case of low frequency counters this resulting frequency shift will compensate the known accuracy and resolution drop at low frequencies as the resulting frequencies are no longer low. The circuit of FIG. 1 is used, among others, to measure the coincidences between the f b  pulses injected in both multiplier channels. Once this overlapping (f a  disable in FIG. 1) is known, f 1  is considered as measured. The output pulses at counter 30 are not equidistant, but this is due to the implementation and is not characteristic of the general method used. 
     Considering further the circuits of FIGS. 1 and 3 as a whole, equation 7 can be rewritten as follows ##EQU2## where n=1, 2, . . . 8 
     From equation 9 it follows that mentioned circuits do no more than divide the auxiliary frequency 20fb 1  by powers of 2 and fractions hereof K to give f s  =100f 1 . 
     Since the principles of the invention have now been made clear, it will be immediately obvious to those skilled in the art that many modifications of structure, arrangement, the elements, materials and components used in the practice of the invention and otherwise, which are particularly adapted for specific environments and operating requirements may be made without departing from the scope of the invention which is to be considered as limited only by the following claims.