Abstract:
A substrate includes a first metal layer containing a first trace, a second metal layer containing a second trace and a dielectric layer arranged between the first and second metal layers. The substrate also includes an electrically conductive signal via electrically coupled to the first and second traces traversing the dielectric layer to form a signal path, wherein physical characteristics of the via are controlled such that signal path characteristics of the via match signal path characteristics of the first and second traces.

Description:
[0001]     This application is a continuation of, and claims priority to, U.S. Provisional Application No. 60/701,138, filed Jul. 20, 2005, and is incorporated herein by reference. 
     
    
     BACKGROUND  
       [0002]     Printed circuit boards (PCBs) or other circuit substrates are often constructed of multiple layers, with connections from the surface of the substrate being connected to inner layer traces of the substrate. For signal integrity, the impedance of the signal path from one point to another should be a constant as possible. With transitions between layers in a substrate, there is a high probability of impedance mismatch between a signal path through a first layer, the transition to a second layer and the signal path through the second layer. This causes overall impedance mismatch in the signal path from end to end, resulting in degraded signal integrity at the receiving end. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0003]     Embodiments of the invention may be best understood by reading the disclosure with reference to the drawings, wherein:  
         [0004]      FIG. 1  shows a three-dimensional view of a circuit substrate.  
         [0005]      FIG. 2  shows an alternative three-dimensional view of a circuit substrate.  
         [0006]      FIG. 3  shows an embodiment of an annular ring at a layer transition.  
         [0007]      FIG. 4  shows an embodiment of annular rings at an inner layer.  
         [0008]      FIG. 5  shows a flowchart of an embodiment of a method of designing a substrate.  
         [0009]      FIG. 6  shows a cross-sectional side view of a circuit substrate with clad vias.  
         [0010]      FIG. 7  shows a top view of a circuit substrate having a signal via and reference vias.  
         [0011]      FIG. 8  shows a top view of a circuit substrate showing alternative placements of reference vias around a signal via.  
         [0012]      FIG. 9  shows a cross-sectional side view of a circuit substrate having an interlayer transition. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0013]      FIG. 1  shows three-dimensional view of a circuit substrate. The board as shown has five layers of conductive material  11 ,  14 ,  13 ,  15  and  19  such as copper clad and four layers of dielectric  16 , which is one layer on the side without the conductive layer  14 , and two layers  16   a  and  16   b  on the side with the conductive layer  14 ,  17  and  18  between them. The conductive layers may take the form of traces. However, it must be noted that this is merely an example and the embodiments disclosed here may apply to any number of layers. The dielectric may be any typical dielectric material used in substrates of this nature. Generally, lower dielectric constant (k) materials are becoming prevalent as circuit substrate dielectrics.  
         [0014]     The circuit substrate  10  has a top surface  11 , which may include traces. An example of a trace is shown at  12 . The circuit substrate has layers  16 ,  17  and  18 , shown here as a dielectric. In this example, layer  16  is a single layer on the left side of the diagram and divided into two sublayers  16   a  and  16   b  on the right side. On the left side, the layer  16  may actually be formed of two different dielectric materials, one on the top of the strip line  14  and the other below, but on the left side, they form one layer of dielectric between conductive layers. The strip line  14  is connected to the trace  12  by a via  20  that has been back drilled or stub drilled to minimize the stub effect of the via, discussed in more detail later.  
         [0015]     It must be noted that the transition shown here is from a microstrip through a plated via to an internal stripline. Application of the invention is not restricted to this occurrence. The transition could be from a microstrip or other surface trace to another microstrip or surface trace coplanar waveguides. Alternatively, the transition could be from a stripline in one layer to a stripline in another layer completely internal to the circuit substrate. For ease of discussion, here, however, the transition will be from a surface microstrip to an internal stripline, with the understanding that the via  20  may traverse a dielectric layer to form a connection between two metal layers.  
         [0016]     The metal stub of the signal via  20  may be formed from a metal-plated via through the substrate  10 . Currently, metal stubs such as  20  are typically formed as a metal-plated via through the substrate which may then be optionally back-drilled to minimize the stub beyond the stripline trace, from the bottom of the substrate in the orientation shown in  FIG. 1 , leaving a significantly reduced metal stub  20 . The depth of the metal stub beyond the strip line is currently not optimized with regard to particular signal characteristics in light of manufacturing process limitations and may form reflections in the path that affects the signal integrity due to the reflected energy trapped in the metal stub.  
         [0017]     The signal path via  20  is electrically connected to the microstrip  12  and the strip line  14 , allowing signals traveling through the microstrip  12  to transition into the layers of the circuit board and into strip line  14 . The signal via  20  may transition through the layers having apertures such as  28 . These transitions, as well as the differences between the microstrip  12 , the signal path via  20  and the strip line  14 , may result in mismatches or irregularities in the signal path characteristics.  
         [0018]     Signal path characteristics as used here means measurable qualities of an electrical signal in the path. These include but are not limited to impedance, including components of impedance of inductance, capacitance, resistance, and conductance; return loss; insertion loss; cross talk; and attenuation.  
         [0019]     In situations where impedance mismatch arises, there is a disturbance in the electromagnetic (EM) field around a signal path. This can affect the signal strength, causing loss in the signal. In more extreme cases, for example, a signal that has a voltage level associated with a logic level ‘ 1 ’ may experience enough loss that when it reaches the other end of the signal path is has a voltage level associated with a logic level ‘ 0 .’ 
         [0020]     Return loss is generally affected by the location of the ground plane relative to the signal path due to reflections associated with the mismatch of impedance between signal vias and references vias. As can be seen in  FIGS. 1 and 2 , reference vias such as  22  surround the signal path via  20  from  FIG. 1 . The placement of these reference vias relative to the signal path via  20  may have a drastic effect on the signal integrity in the signal path.  
         [0021]     In addition to the placement of the reference vias, annular rings used in the manufacturing process may be controlled for the signal characteristics as well. An example of such a ring at a surface of a substrate is shown at  26  in  FIG. 3 .  FIG. 4  shows an annular ring  26  on an interlayer of the substrate. The term ‘annular ring’ is a term used in manufacturing of the substrate. The presence of an annular ring allows more consistent connection to the drilled and plated of the hole forming the via. The annular ring and the other portions of the structure that provide electrical connection may also be referred to as the ‘pad.’ 
         [0022]     In future embodiments, it may be possible and desirable to eliminate the annular ring, in which case the connection would be directly to the metal lining the via, without the annular ring. For example, if via size and drill size were small enough, the via may be drilled such that the circumference of the via is contained within the trace, with no need for an annular ring.  
         [0023]     It is possible to optimize the formation of the annular ring  26 , the placement of the reference vias  22  and the aperture  28  to eliminate or mitigate mismatches and irregularities in the signal path characteristics. As mentioned above, currently substrate manufactures are concentrating on the annular ring and optimizing the formation of that to minimize impedance in the outer layer. The formation of the annular ring in this example, as well as any other apertures in any other layers, may be tuned to a particular electrical characteristic, such as impedance, of the signal path in that layer.  
         [0024]     A method of designing a signal path to manage a selected signal characteristic is shown in  FIG. 5 . For ease of discussion, a cross-section through a substrate, such as along line A-AA in  FIG. 3  is shown in  FIG. 6 . For ease of discussion and better understanding, the process will focus first on a simple substrate having a via from a trace on one side of the substrate to a trace on the other side of the substrate.  
         [0025]     In  FIG. 6 , the signal via  50  has reference vias  52  and  54  on either side of it. The size of the signal via, the number of reference vias, the distance between the signal via and the reference vias, the application of the via, whether for single signals or differential signals, are determined at  30  in  FIG. 5 . The determination may take into account the size of the substrate, the nature of the connectors, the design rules used in designing and laying out the circuitry, etc.  
         [0026]     The number of reference vias may be guided by the size of the area provided for the vias, the application and geometry of the signal vias, the circuit requirements, etc. The placement of the reference vias relative to the signal via and each other may be used to control the desired signal characteristics as will be discussed further.  
         [0027]     In  34 , the via size is selected based upon the determinations made in  30 . If a drill is used to form the via, the drill size is selected based upon the geometry of the via. It must be noted that in current implementations, other means may be used to make the hole such as by laser drilling and are considered to be included in this discussion. Therefore, the drill size selection is considered to be an optional process.  
         [0028]     In  36 , an aperture, sometimes referred to as an anti-pad, is set. Referring back to  FIGS. 3 and 4 , the aperture  28  is the area around the via that is ‘outside’ the annular ring  26 . In one embodiment, using a three-dimensional, electromagnetic (EM) solver tool, a ‘port’ may be defined to be in the area of the aperture with a particular signal characteristic. This process is iterated until the structure being tested meets the desired characteristic.  
         [0029]     In  42 , the aperture on each layer may be dealt with differently depending upon the signal via, reference vias, dielectric thickness and characteristic above and below the trace, the stub, the annular ring, etc.  
         [0030]     For the embodiment under discussion here, once the aperture is set at  36 , the process moves to controlling the trace topology. In one embodiment, the trace is treated as a co-planar waveguide for modeling purposes. A co-planar waveguide is a trace topology that has two reference traces on either side of the signal trace, separated by a gap, typically air on the same plane.  
         [0031]     Using a co-planar waveguide model, it is possible to determine the layout of the surface topology. Referring to  FIG. 7 , it can be seen that the surface can be viewed as a metal pad  62  encompassing the area around the via  20 , the annular ring  26 , if there is one, and the aperture or air gap  28 . This surface is modeled as a co-planar waveguide and adjustments are made to the topology to ensure that the signal characteristics are maintained.  
         [0032]     As can be seen in  FIG. 8 , the position and number of the reference vias such as  22   a - i  may change depending upon the application. Referring to  FIG. 5 , the number of reference vias available for adjustment is generally determined prior to this process within  30 . However, there is no limitations to a particular number of vias being used, so alternative arrangements are presented. During the setting of the aperture  28 , typically also done previous to this process, the aperture may have been adjusted to many different possible positions, including those shown by the dotted circles. The aperture may intersect with the reference vias, be smaller than a circle defined by the reference vias, etc.  
         [0033]     During the process of adjusting the trace topology at  38  of  FIG. 5 , the position of the reference vias may be shifted slightly. In the example of  FIG. 8 , the reference via  22   a  may be shifted slightly to the position of  22   b  to adjust for the presence of the co-planar waveguide. Similarly, the position of the via  22   c  may be adjusted such as shown at  22   d . The arrangement of the other reference vias  22   e - i  may or may not be symmetrical, depending upon the effects of their positions on the desired signal characteristic.  
         [0034]     Once the trace topology is set based upon the co-planar waveguide, there may be further adjustments due to the presence of the annular ring, if one is used, at  40 . Typically, in current manufacturing processes, the presence of an annular ring ensures that the plating of the via is complete with no disconnects. However, in future implementations, it may be possible to drill into the via with a drill small enough that the trace itself will form the connection to the via, without use of an annular ring. Therefore, the process of adjusting for the annular ring may be optional.  
         [0035]     Having discussed application of the embodiments of the invention for a substrate having one layer of dielectric between two metal layers, it is possible to discuss a multi-layer substrate in which there are interlayers. A cross-section of such a substrate is shown in  FIG. 9 .  
         [0036]     In  FIG. 9 , the multi-layer substrate has five layers, which is just an example. It should be noted that the ‘layers’ referred to here are metal or conductive layers. The interposing layers of substrate dielectric are not counted as part of the layers. Layer  1  (L 1 ) is the surface trace. The vias have been plated in this cross-section, resulting in metal cladding such as  70  and  78  on the inner walls of the vias.  
         [0037]     Layer  2  (L 2 ) is a reference layer, connecting to the reference via  52 , but not to the signal via  50 . Layer  3  (L 3 ) is the signal layer connecting to the signal via  50 . For purposes of discussion here, the reference layer  2  will be referred to as being above the signal layer. Similarly, layer  4  (L 4 ), which is another reference layer, will be referred to as being below the signal layer. In this particular embodiment, layer  5  (L 5 ) is the layer on the opposite surface of the substrate from the incoming signal trace.  
         [0038]     In the interlayers, layers  2 - 4 , the apertures of the reference layer relative to the signal via are to be set and controlled similar to the surface aperture referred to previously. The apertures may differ in each layer, however, because the effective dielectric constant is different due to the air dielectric at the surface. The aperture  82 , for example, of the reference layer  2 , is controlled and adjusted to maintain the desired signal characteristic. The apertures  74  and  76  may be of different sizes, due to the dielectric constant of the material used, or the thickness of the dielectric, as examples.  
         [0039]     In the embodiment of  FIG. 9 , where there is a second reference layer, the aperture in the second reference layer, the one below the signal layer, is also manipulated to maintain the desired signal characteristic. The apertures involved may depend upon the relationship between the signal via, reference vias, the signal trace and the annular ring. For example, the signal via may provide connection between a surface microstrip and an interlayer stripline, between two surface microstrips as in the previous example, but through either a ‘simple’ substrate or a multi-layer substrate, or between two interlayers of the substrate. Controlling any apertures through which the signal path passes allows finer control of the properties of the signal path to maintain the desired signal path characteristic. Further, controlling the depth of the back drilling process, the resulting position of which is shown at  80 , contributes to this finer control.  
         [0040]     In this manner, the signal transition portions of the substrate are tuned and controlled so as to make the transitions have a particular target characteristic. For example, if the target characteristic is an impedance for the entire signal path of 50 ohms, the signal transitions from stripline to the various levels of the signal via to the other stripline are tuned and controlled such that the entire signal path has an impedance of 50 ohms. This may sometimes be referred to as an electrically ‘invisible via’ as any testing done shows no impedance variations at the via.  
         [0041]     Thus, although there has been described to this point a particular embodiment for a method and apparatus for manufacture of a circuit substrate, it is not intended that such specific references be considered as limitations upon the scope of this invention except in-so-far as set forth in the following claims.