Abstract:
A current mirror with immunity for the variation of threshold voltage includes raising the voltage difference between the gate and the source of a MOS in the current source, and increasing the channel length of the MOS for limiting the generated reference current.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a current source with immunity for the variation of threshold voltage, and more particularly, to a current source for lowering the impact of the threshold voltage on the magnitude of the current, by increasing the voltage difference between the gate and the source of the current source. 
         [0003]    2. Description of the Prior Art 
         [0004]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional current mirror. As shown in  FIG. 1 , the gate (control end) of the P-type Metal Oxide Semiconductor (PMOS) transistor Q P1  is utilized to receive a control voltage V G , the source (first end) of the PMOS transistor Q P1  is coupled to a voltage source V DD , and the drain (second end) of the PMOS transistor Q P1  is utilized to output a current I 1 . The gate (control end) of the PMOS transistor Q P2  is utilized to receive the control voltage V G , the source (first end) of the PMOS transistor Q P2  is coupled to the voltage source V DD , and the drain (second end) of the PMOS transistor Q P2  is utilized to output a current I 2 . The conventional current mirror utilizes the control voltage V G  to bias the PMOS transistor Q P1  for generating the reference current source I 1 , and then the ratio of the channel aspect ratios (width/length, W/L) of the PMOS transistors Q P1  and Q P2  is utilized to generate the current I 2 , which is proportional to the reference current source I 1 . For instance, if the channel aspect ratio (W 1 /L 1 ) of the PMOS transistor Q P1  is “1” and the channel aspect ratio (W 2 /L 2 ) of the PMOS transistor Q P2  is “2”, then when the reference current source I 1  is 1 amp, the current I 2  is generated to be 2 amps. 
         [0005]    The conventional current mirror operates the PMOS transistor Q P1  in the saturation region. In other words, the relationship between the current  11  and the voltage V G  is described in the formulas as below: 
         [0000]        I   1 =1/2× K ×( W   1   /L   1 )×( V   SG   −V   T ) 2    (1); 
         [0000]      =1/2× K ×( W   1   /L   1 )×( V   DD   −V   G   −V   T ) 2    (2); 
         [0000]    where the voltage V SG  represents the voltage difference, which is equivalent to the voltage of (V DD −V G ), between the source and the gate of the PMOS transistor Q P1 , the voltage V T  represents the threshold voltage of the PMOS transistor Q P1 , and K represents a process variable. Hence, the magnitude of the reference current source I 1  is related to the channel aspect ratio (W 1 /L 1 ) of the PMOS transistor Q P1 , the voltage difference V SG  (equivalent to (V DD −V G )), and the threshold voltage V T . 
         [0006]    Due to the magnitude of the threshold voltage V T  is easily affected by the processing, when under different processing, the magnitude of the current source I 1  is still affected by the threshold voltage V T , even with the same voltage source V DD , the same voltage difference V SG  between the source and the gate, and the same channel aspect ratio (W/L). In this way, the magnitude of the current source differs from the desired. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention provides a current source for driving a first Metal Oxide Semiconductor (MOS) transistor to generate a predetermined current. The current source comprises a feedback circuit. The feedback circuit comprises a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first resistor coupled between the ground end and the control end of the fifth MOS transistor, and a MOS circuit. The second MOS transistor comprises a first end coupled to a voltage source, a control end, and a second end coupled to the control end of the second MOS transistor. The third MOS transistor comprises a first end coupled to the voltage source, a control end coupled to the control end of the second MOS transistor, and a second end. The fourth MOS transistor comprises a first end coupled to the second end of the third MOS transistor, a control end for receiving a control voltage, and a second end coupled to a ground end. The fifth MOS transistor comprises a first end coupled to the second end of the second MOS transistor, a control end for outputting the control voltage, and a second end coupled to the ground end. The MOS circuit comprises a first end coupled to the voltage source, a control end coupled to the first end of the fourth MOS transistor, and a second end coupled to the control end of the fifth MOS transistor. 
         [0008]    The present invention further provides a current source. The current source comprises a first MOS transistor for generating a predetermined current, a feedback circuit, a first resistor coupled to a ground end and the output end of the feedback circuit, and a MOS circuit. The feedback circuit comprises a first end coupled to a voltage source, a control end for receiving a control voltage, an output end for outputting the control voltage, and a feedback end coupled to a control end of the first MOS transistor. The MOS circuit comprises a first end coupled to the voltage source, a control end coupled to the feedback end of the feedback circuit, and a second end coupled to the output end of the feedback circuit. 
         [0009]    The present invention further provides a method for generating current with immunity for variation of threshold voltage. The method comprises providing a first MOS transistor for a first end of the first MOS transistor to be coupled to a voltage source, providing a MOS transistor circuit to be coupled to the first MOS transistor and the voltage source, providing a feedback circuit to be coupled to the voltage source, and inputting a control voltage to the feedback circuit for control a current with a predetermined magnitude passing through the MOS transistor circuit, as well as control a voltage of the feedback end, wherein the feedback end is coupled to a control end of the first MOS transistor. The feedback circuit comprises a feedback end coupled between the MOS transistor circuit and the first MOS transistor. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a diagram illustrating a conventional current mirror. 
           [0012]      FIG. 2  is a diagram illustrating the current source  200  for reducing the affect of the threshold voltage according to the first embodiment of the present invention. 
           [0013]      FIG. 3  is a diagram illustrating the current source  300  for reducing the impact of the threshold voltage according to the second embodiment of the present invention. 
           [0014]      FIG. 4  is a diagram illustrating the current source  400  for reducing the impact of the threshold voltage according to the third embodiment of the present invention. 
           [0015]      FIG. 5  is a flowchart illustrating a method  500  of generating the current with immunity to the variation of the threshold voltage of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    Hence, the present invention raises the voltage difference V SG  between the source and the gate of the MOS transistor for reducing the impact of varying the threshold voltage V T , according to formulas (1) and (2) of the current of the MOS transistor operating in the saturation region. However, to keep the reference current source I 1  generating a fixed current without changing the process variable K, the channel aspect ratio (W/L) of the MOS transistor needs to be reduced in order to keep the current of the reference current source I 1  in the same range. 
         [0017]    Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating the current source  200  for reducing the affect of the threshold voltage according to the first embodiment of the present invention. The current source  200  comprises a feedback circuit  210 , a PMOS transistor Q P1 , and a resistor R 1 . The feedback circuit  210  comprises two PMOS transistors Q PX  and Q PY , two N-channel Metal Oxide Semiconductor (NMOS) transistors Q N1  and Q N2 , and a resistor R 2 . The current source  200  enables the PMOS transistors Q P2 , Q P3  . . . Q PN  to replicate the currents I 2 , I 3  . . . I N , in proportion to the magnitude of the reference current source I 1 . 
         [0018]    In the feedback circuit  210 , the source (first end) of the PMOS transistor Q PX  is coupled to the voltage source V DD , the gate (control end) of the PMOS transistor Q PX  is coupled to the drain (to ensure operation in the saturation region) of the PMOS transistor Q PX , and the drain (second end) of the PMOS transistor Q PX  is coupled to the drain (first end) of the NMOS transistor Q N1 . The source (first end) of the PMOS transistor Q PY  is coupled to the voltage source V DD , the gate (control end) of the PMOS transistor Q PY  is coupled to the gate of the PMOS transistor Q PX , and the drain (second end) of the PMOS transistor Q PY  is coupled to the drain (first end) of the NMOS transistor Q N2 . The source (second end) of the NMOS transistor Q N1  is coupled to the resistor R 2 , the gate (control end) of the NMOS transistor Q N1  is coupled to the resistor R 1 , and the drain (first end) of the NMOS transistor Q N1  is coupled to the drain of the PMOS transistor Q PX . The source (second end) of the NMOS transistor Q N2  is coupled to the resistor R 2 , the gate (control end) of the NMOS transistor Q N2  is utilized to receive a control voltage V 1 , and the drain (first end) of the NMOS transistor Q N2  is coupled to the drain of the PMOS transistor Q PY . The resistor R 2  is coupled between the NMOS transistors Q N1  and Q N2 , and the ground end (V SS ). 
         [0019]    In the current source  200 , the source (first end) of the PMOS transistor Q P1  is coupled to the voltage source V DD , the gate (control end) of the PMOS transistor Q P1  is coupled to the drain (first end) of the NMOS transistor Q N2  of the feedback circuit  210 , and the drain (second end) of the PMOS transistor Q P1  is coupled to the resistor R 1 . The resistor R 1  is coupled between the drain of the PMOS transistor Q P1 , the gate (control end) of the NMOS transistor Q N1 , and the ground end. In this way, the voltage across the resistor R 1  equals the control voltage V 1 . Hence the magnitude of the reference current source I 1  is limited by the control voltage V 1  and the resistance of the resistor R 1  (I 1 =V 1 /R 1 ). Therefore, the feedback circuit  210  controls the magnitude of the voltage difference V SG  according to the magnitude of the control voltage V G  for stabilizing the reference current source I 1  at (V 1 /R 1 ) with the negative feedback manner. 
         [0020]    In the first embodiment of the present invention, the threshold voltage V T1  of the PMOS transistor Q P1  is designed to be significantly higher than the threshold voltage V T2  of the PMOS transistors Q P2 ˜Q PN . Hence, under the condition that the reference current source I 1  is fixed and the channel aspect ratio (W 1 /L 1 ) of the PMOS transistors Q P1 ˜Q PN  is fixed, the voltage V SG  across the PMOS transistor Q P1  is relatively larger than those of the PMOS transistors Q P2 ˜Q PN  such that the replicated currents I 2 ˜I N  can be unaffected by the threshold voltage V T2 . More particularly, when the threshold voltage V T1  equals to the threshold voltage V T2 , the voltage V SG  across the PMOS transistor Q P1  can not be raised (when the magnitude of the reference current source I 1  is fixed to (V 1 /R 1 ), and the channel aspect ratio (W 1 /L 1 ) of the PMOS transistors Q P1 ˜Q PN  is also fixed), according to formula (1): I 1 =1/2×K×(W 1 /L 1 )×(V SG ×V T1 ) 2 . Hence, the first embodiment of the present invention demonstrates that increasing the threshold voltage V T1  increases the voltage difference V SG  accordingly. In  FIG. 2 , as the voltage V G  decreases, the voltage V SG  across the PMOS transistors Q P2 ˜Q PN  increases accordingly. Also, due to the threshold voltage V T2  of the PMOS transistors Q P2 ˜Q PN  is designed to be relatively smaller than the threshold voltage V T1 , the variance of the threshold voltage V T2  has less impact on the raised voltage V SG , consequently causing the replicated currents I 2 ˜I N  to be controlled within a desired range. 
         [0021]    Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating the current source  300  for reducing the impact of the threshold voltage according to the second embodiment of the present invention. The current source  300  comprises a feedback circuit  310 , a PMOS transistor Q P1 , and a resistor R 1 . The feedback circuit  310  comprises two PMOS transistors Q PX  and Q PY , two NMOS transistors Q N1  and Q N2 , and a resistor R 2 . The current source  300  enables the PMOS transistors Q P2 , Q P3  . . . Q PN  to replicate currents I 2 , I 3  . . . I N , in proportion to the magnitude of the reference current source I 1 . 
         [0022]    Differed from the first embodiment, in the second embodiment of the present invention, the threshold voltages of the PMOS transistors Q P1 ˜Q PN  are designed to be as the same as the threshold voltage V T1 , and the channel aspect ratio (W 2 /L 2 ) of the PMOS transistor Q P1  is designed to be significantly lowered than the channel aspect ratios of the PMOS transistor Q P2 ˜Q PN . Hence, under the condition that the magnitude of the reference current source I 1  is fixed and the channel aspect ratio (W 2 /L 2 ) of the PMOS transistor Q P1  is significantly lower than the channel aspect ratio (W 1 /L 1 ) of the PMOS transistors Q P2 ˜Q PN , the voltage V SG  across the PMOS transistor Q P1  can be raised such that the replicated currents I 2 ˜I N  can be unaffected by the threshold voltage V T1 . More particularly, when the channel aspect ratio (W 2 /L 2 ) equals to the channel aspect ratio (W 1 /L 1 ), the voltage V SG  across the PMOS transistor Q P1  cannot be raised (when the magnitude of the reference current source I 1  is fixed to (V 1 /R 1 ) and the channel aspect ratio (W 1 /L 1 ) of the PMOS transistors Q P1 ˜Q PN  is also fixed), according to formula (1): I 1 =1/2×K×(W 1 /L 1 )×(V SG −V T1 ) 2 . When the channel aspect ratio is reduced to (W 2 /L 2 ), the voltage V SG  across the PMOS transistor Q P1  can be raised to keep the reference current source I 1  to be fixed to (V 1 /R 1 ), according to formula (1): I 1 =1/2×K×(W 2 /L 2 )×(V SG −V T1 ) 2 . Hence, the second embodiment of the present invention demonstrates that decreasing the channel aspect ratio of the PMOS transistor Q P1  increases the voltage difference V SG . As shown in  FIG. 3 , as the voltage difference V SG  decreases, the voltage V SG  across the PMOS transistors Q P2 ˜Q PN  increases and the variance of the threshold voltage V T1  of the PMOS transistors Q P2 ˜Q PN  has less impact on the raised voltage V SG , consequently causing the replicated currents I 2 ˜I N  to be controlled within a desired range. 
         [0023]    In addition, there are two ways to lower the channel aspect ratio of the PMOS transistor Q P1 ; one way is to increase the channel length of the PMOS transistor Q P1 , causing the channel aspect ratio of the PMOS transistor Q P1  to decrease accordingly; the other way is to decrease the channel width of the PMOS transistor Q P1 , causing the channel aspect ratio to decrease accordingly. 
         [0024]    Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating the current source  400  for reducing the impact of the threshold voltage according to the third embodiment of the present invention. The current source  400  comprises a feedback circuit  410 , N PMOS transistors Q P11 ˜Q P1N , and a resistor R 1 . The feedback circuit  41   0  comprises two PMOS transistors Q PX  and Q PY , two NMOS transistors Q N1  and Q N2 , and a resistor R 2 . The current source  400  enables the PMOS transistors Q P2 , Q P3  . . . Q PN  to replicate currents I 2 , I 3  . . . I N , in proportion to the magnitude of the reference current source I 1 . 
         [0025]    In the current source  400 , the PMOS transistor Q P1  of the first embodiment of  FIG. 2  is replaced by N PMOS transistors Q P11 ˜Q P1N . In the current source  400 , the source (first end) of the PMOS transistor Q P11  is coupled to the voltage source V DD , the gate (control end) of the PMOS transistor Q P11  is coupled to the drain (first end) of the NMOS transistor Q N2  of the feedback circuit  410 , and the drain (second end) of the PMOS transistor Q P11  is coupled to the source (first end) of the PMOS transistor Q P12 ; the source (first end) of the PMOS transistor Q P12  is coupled to the drain of the of the PMOS transistor Q P11 , the gate (control end) of the PMOS transistor Q P12  is coupled to the drain (first end) of the NMOS transistor Q N2  of the feedback circuit  410 , and the drain (second end) of the PMOS transistor Q P12  is coupled to the source (first end) of the PMOS transistor Q P13  . . . , and so on; the source (first end) of the PMOS transistor Q P1N  is coupled to the drain of the PMOS transistor Q P1(N−1) , the gate (control end) of the PMOS transistor Q P1N  is coupled to the drain (first end) of the NMOS transistor Q N2  of the feedback circuit  410 , and the drain (second end) of the PMOS transistor Q P1N  is coupled to the resistor R 1 . The resistor R 1  is couple between the drain of the PMOS transistor Q P1N , the gate (control end) of the NMOS transistor Q N1 , and the ground end. Hence, the voltage across the resistor R 1  also equals the control voltage V 1 . Hence, the magnitude of the reference current source I 1  is limited to (V 1 /R 1 ). Therefore, the feedback circuit  410  controls the magnitude of the voltage difference V SG  according to the magnitude of the control voltage V G  for stabilizing the reference current source I 1  at (V 1 /R 1 ) with the negative feedback manner. 
         [0026]    In the third embodiment of the present invention, the threshold voltage of the PMOS transistor Q P11 ˜Q P1N  and Q P2 ˜Q PN  are designed to have the same as the threshold voltage V T1  and the same channel aspect ratio (W 1 /L 1 ). Since the PMOS transistors Q P11 ˜Q P1N  are connected in series, the serial-connected PMOS transistors Q P11 ˜Q P1N  can be equivalent to a single PMOS transistor, with an effective channel length of a multiple of N. In other words, in the equivalent MOS transistor, the channel aspect ratio changes to a multiple of 1/N (which implies decreasing to a multiple of 1/N). Hence, effectively speaking, the third embodiment of the present invention is similar to the second embodiment of the present invention in terms of lowering the channel aspect ratio to increase the voltage difference V SG . In other words, under the condition that the reference current source I 1  is kept constant and the channel aspect ratio (W 1 /NL 1 ) of the PMOS transistors Q P11 ˜Q P1N  is significantly lower than the channel aspect ratios (W 1 /L 1 ) of the PMOS transistors Q P2 ˜Q PN , the voltage V SG  across the PMOS transistors Q P11 ˜Q PN  can be raised, consequently avoiding the replicated currents I 2 ˜I N  being affected by the threshold voltage V T1  and being controlled within a desired range. 
         [0027]    Please refer to  FIG. 5 .  FIG. 5  is a flowchart illustrating a method  500  of generating the current with immunity to the variation of the threshold voltage of the present invention. The steps of the method are explained below: 
         [0028]    Step  510 : Start; 
         [0029]    Step  502 : Provide a first MOS transistor to be coupled to a voltage source; 
         [0030]    Step  503 : Provide a MOS circuit to be coupled to the first MOS transistor and the voltage source; 
         [0031]    Step  504 : Provide a feedback circuit to be coupled to the voltage source, wherein the feedback circuit comprises a feedback end coupled between the MOS circuit and the first MOS transistor; 
         [0032]    Step  505 : Input a control voltage to the feedback circuit for control a current with a predetermined magnitude passing through the MOS circuit, as well as control a voltage of the feedback end; 
         [0033]    Step  506 : End. 
         [0034]    In step  503 , the MOS transistor comprises a sixth MOS transistor. The channel aspect ratio of the sixth MOS transistor can be adjusted to be lower than the channel aspect ratio of the first MOS transistor, or, the threshold voltage of the sixth MOS transistor can be adjusted to be higher than the threshold voltage of the first MOS transistor. 
         [0035]    In step  503 , the MOS circuit can also be realized with a plurality of MOS transistors connected in series. The channel aspect ratio of every MOS transistor of the plurality of MOS transistors connected in series can be adjusted to approximately equal to the channel aspect ratio of the first MOS transistor. 
         [0036]    To sum up, the current source and the method for generating the current of the present invention can effectively resist the impact of the variation of the threshold voltage during processing to the current stability, providing great convenience. 
         [0037]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.