Abstract:
A conductive structure in a silicon wafer for preventing plasma damage. The wafer includes a plurality of dies and a plurality of scribe lines between the dies. The semiconductor substrate of this wafer further includes a plurality of patterned conductive layers. The conductive structure comprises of a plurality of ground wires and a plurality of contacts. The ground wires are distributed inside the scribe lines and are positioned at least in the uppermost conductive layer. The contacts are used for connecting the ground wires and the semiconductor substrate electrically. When other conductive layers other than the uppermost conductive layer also contain ground wire connections, the ground wires in different conductive layers are electrically connected by plugs.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 89122536, filed Oct. 26, 2000. 
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a protective structure on a silicon wafer. More particularly, the present invention relates to a conductive structure on a silicon wafer for preventing plasma damage. 
     2. Description of Related Art 
     In integrated circuit (IC) manufacture, the dimensional requirement of each device are getting smaller while the aspect ratio of etching or gap filling is getting higher. Consequently, high-density plasma has to be used in dry etching or chemical vapor deposition (CVD) (for example, plasma-enhanced CVD or high-density plasma CVD). For example, plasma density has increased from a former value of 10 9 ˜10 10 /cm 3  to a current value of about 10 11 ˜10 12 /cm 3 . 
     However, as plasma density rises, any non-uniform charge distribution frequently can lead to arcing. Arcing is an electrical phenomena that results when electric charges jump from a region of high plasma density to a region of low plasma density through a silicon wafer so that electric potential in these regions are equalized. Since the electric potential and current density involved in each arcing process is very high, path inside the wafer through which the current runs may cause serious damages. Therefore, methods of preventing direct arcing through a wafer despite using high-density plasma in various processes are critical to success in semiconductor manufacturing. 
     SUMMARY OF THE INVENTION 
     Accordingly, one object of the present invention is to provide a conductive structure in a silicon wafer for preventing plasma damage. The wafer includes a plurality of dies and a plurality of scribe lines between the dies. The semiconductor substrate of this wafer also includes a plurality of conductive layers. The conductive structure comprises of a plurality of ground wires and a plurality of contacts. The ground wires are distributed inside the scribe lines and are positioned at least in the uppermost conductive layer. The contacts are used for connecting the ground wires and the semiconductor substrate electrically. When other conductive layers other than the uppermost conductive layer also contain ground wire connections, the ground wires in different conductive layers are electrically connected by a plurality of plugs. 
     This invention also provides a method of manufacturing a conductive structure capable of preventing plasma damage in a silicon wafer. First, a plurality of contacts electrically connected with a semiconductor substrate is formed in a plurality of scribe lines. The conductive layers on the scribe lines are patterned when conductive patterns re formed in the die section. Ultimately, ground wires that are electrically connected o the contacts are also formed. Furthermore, if a plurality of ground wire layers is 
     required, the plugs that links with a previous ground wires are formed concurrently with the step of forming necessary plugs in the die section. Moreover, the next layer of ground wires is formed in the scribe lines when the next conductive layer is patterned inside the die section. The ground wires in the upper layer and the ground wires in the lower layer are electrically connected through the plugs. 
     The conductive structure on the wafer has several functions. When a plasma semiconductor process is carried out, the ground wires provide electrical paths for the flow of current so that uneven electrical charge distribution of the plasma can be equalized. In addition, the ground wire, the contact and the plug that links up the ground wires of different layers are electrically connected together with the semiconductor substrate so that the whole structure is effectively grounded. In other words, excess charges above the wafer can be channeled away through the semiconductor substrate. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with he description, serve to explain the principles of the invention. In the drawings, 
     FIG. 1 is a top view of the dies, scribe lines and the ground wires on a silicon wafer according to one preferred embodiment of this invention; and 
     FIGS. 2 through 4 are schematic cross-sectional views showing the progression of steps for producing a conductive structure with a plurality of ground wire layers and corresponding structures in the dies of a silicon wafer according to this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     FIG. 1 is a top view of the dies, scribe lines and the ground wires on a silicon wafer according to one preferred embodiment of this invention. FIG. 3 is a schematic cross-sectional view of a portion of the silicon wafer shown in FIG.  1 . In fact, the right side of FIG. 3 with a labeled  120  is a cross-sectional view along line I-I′ of FIG.  1 . 
     As shown in FIG. 1, the silicon wafer  100  has a plurality of dies  110  and a plurality of scribe lines  120  between the dies  110 . Each scribe line  120  has a plurality of ground wires  210   b  and  220   b  (note that ground wires  210   b  and  220   b  are on a different layer, see the section below). The ground wires  210   b  and  220   b  surround each die  110 . For better clarity, width of the ground wire  210   b  ( 220   b ) and the die  110 /scribe line  120  are drawn with slight exaggeration. 
     As shown in FIG. 3, the ground wire  210   b  is the first layer of ground wire in the upper portion of the semiconductor substrate  200 . The ground wire  210   b  is formed over the dielectric layer  205  above the semiconductor substrate  200 . The dielectric layer  205  has a contact  208   b  that connects the ground wire  210   b  and the semiconductor substrate  200  electrically. The ground wire  220   b  is a second layer ground wire. The ground wire  220   b  is located over a dielectric layer  215  sitting on top of the dielectric layer  205 . The ground wire  220   b  is electrically connected with the ground wire  210   b  by a plug  218   b  that passes through the dielectric layer  215 . In other words, the ground wire  210   b , the contact  208   b  and the semiconductor substrate  200  are electrically connected together via the plug  218   b.    
     FIGS. 2 through 4 are schematic cross-sectional views showing the progression of steps for producing a conductive structure with a plurality of ground wire layers and corresponding structures in the dies of a silicon wafer according to this invention. 
     As shown in FIG. 2, a dielectric layer  205  is formed over a semiconductor substrate  200  inside a die  110  and scribe lines  120 . A gate oxide layer  202  and a gate electrode  204  are sequentially formed over the semiconductor substrate  200  inside the die  110  section. The gate electrode  204  can be a polysilicon layer, for example. A dielectric layer  205  is formed over the semiconductor substrate  200 . A contact  208   a  that electrically connects with the gate electrode  204  is formed in the dielectric layer  205  within the die  110 . In the meantime, a contact  208   b  is also formed in the dielectric layer  205  within the scribe line  120 . The contact  208   b  is electrically connected to the semiconductor substrate  200 . A conductive layer (not shown in the figure) is formed over the semiconductor substrate  200 . The conductive layer is next patterned to form a conductive wire  210   a  that connects electrically with the contact  208   a  within the die  110  section. In the meantime, a ground wire  210   b  that electrically connects with the contact  208   b  inside the scribe line  120  is also formed. Hence, the first ground wire layer is completed. The conductive layer forms a second conductive layer above the semiconductor substrate  200 . In general, the conductive layer is in general a polysilicon or a polysilicon/silicide composite layer. 
     As shown in FIG. 3, a dielectric layer  215  is formed over the semiconductor substrate  200 . A via hole  216   a  that exposes a portion of the conductive wire  210   a  is formed in the dielectric layer  215  inside the die  110 . In the meantime, a via hole  216   b  that exposes a portion of the ground wire  210   b  is also formed in the dielectric layer  215  inside the scribe line  120 . In the process of depositing dielectric material to form the dielectric layer  215  and the etching the dielectric layer  215  to form the via holes  216   a/b , at least one of them involves performing a high-density plasma process. The deposition can be carried out, for example, by performing a plasma-enhanced chemical vapor deposition (PECVD) or a high-density plasma chemical vapor deposition (HDP-CVD). In the presence of the ground wire  210   b  (connects electrically with the substrate  200  through the contact  208   b ) above the dielectric layer  205  within the scribe line  120 , non-uniform charge distribution in the plasma above the wafer can be equalized. The uneven charge distribution can be equalized by passing through various ground wires  210   b  scattered on the wafer  100  or through the ground wire  210   b  and the contact  208   b  and finally exit from the semiconductor substrate  200 . Consequently, even if the high-density plasma has highly non-uniform charge distribution, arcing rarely occurs, thereby preventing serious damages to the devices within the wafer. 
     Similarly, as long as high-density plasma process is involved, a plurality of ground wires may also be patterned in the same manner inside the scribe line  120  when other upper conductive layers are needed within the die  110 . 
     After forming the via holes  216   a  and  216   b , conductive material is deposited into the holes to form plugs  218   a  and  218   b  respectively. The plug  218   a  is electrically connected with the ground wire  210   a  and the plug  218   b  is electrically connected with the ground wire  210   b . A conductive wire  220   a  that connects electrically with the plug  218   a  is formed above the dielectric layer  215  within the die  110 . In the meantime, a ground wire  220   b  that connects electrically with the plug  218   b  is formed above the dielectric layer  215  within the scribe line  120 . 
     As shown in FIG. 4, a dielectric layer  225  is formed over the semiconductor substrate  200 . A via hole  226   a  that exposes a portion of the conductive wire  220   a  is formed in the dielectric layer  225  within the die  10 . At the same time, a via hole  226   b  that exposes a portion of the ground wire  220   b  is formed in the dielectric layer  225  within the scribe line  120 . Here, ground wires  220   b  that connect electrically with the semiconductor substrate  200  are distributed all around the wafer above the dielectric layer  215  inside the scribe line  120 . In the presence of these ground wires  220   b , no arcing due to uneven charge distribution of the high-density plasma will occur. Hence, devices within the wafer will remain intact after conducting a high-density plasma chemical vapor deposition to form the dielectric layer  225  or a high-density plasma etching process to form the via holes  226   a/b.    
     In addition, the invention can form one layer of ground wires or a multiple of ground wires depending on whether subsequent high-density plasma deposition or etching is required. The advantage of this invention is that the ground wires are distributed all across the wafer so that an uneven distribution of electric charges in plasma can be easily equalized. Moreover, various ground wires are electrically connected to the semiconductor substrate via contacts (with ground wires in different layer connected by additional plugs). Hence, excess electrical charges can easily exit from the semiconductor substrate. Ultimately, arcing in the presence of unevenly distributed high-density plasma will rarely occur, thereby preventing any damages to the devices within the wafer. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.