Abstract:
A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation application filed under 35 U.S.C. 111(a) claiming benefit under 35 U.S.C. 120 and 365(c) of PCT International Application No. PCT/JP2007/057152, filed on Mar. 30, 2007, the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     The present disclosure is broadly directed to a semiconductor device, and in particular to a semiconductor integrated circuit device including a p-channel MOS transistor and n-channel MOS transistor having improved operation speeds due to stress application. 
     BACKGROUND 
     Advancements in miniaturization technology have brought about nanoscale and ultrafast semiconductor devices having a gate length of 30 nm or less. 
     In such a nanoscale and ultrafast transistor, areas of channel regions just below gate electrodes are significantly small compared to those in a conventional semiconductor device. Accordingly, the mobility of electrons or holes through the channel regions is largely affected by stress applied to the channel regions. Given this factor, many approaches have been developed that optimize the stress applied to the channel regions, thereby improving the operation speed of semiconductor devices. 
     One of conventionally proposed structures is directed to the improvement of the operation speed of an n-channel MOS transistor, and involves forming a stress film (a typical example of such is an SiN film) having a tensile stress in such a manner as to include the gate electrode in the element region of the n-channel MOS transistor. In this way, the electron mobility in the channel region just below the gate electrode is improved. 
     Another conventionally proposed structure is directed to the improvement of the operation speed of a p-channel MOS transistor, and involves forming a stress film (such as an SiN film) having a compressive stress in such a manner as to include the gate electrode in the element region of the p-channel MOS transistor. In this way, the hole mobility in the channel region just below the gate electrode is improved. 
     Furthermore, a proposed semiconductor integrated circuit device has a structure in which a stress-application n-channel MOS transistor and a stress-application p-channel MOS transistor are integrated. 
     Such a semiconductor integrated circuit device is formed by the following procedures, for example. 
     That is, after an n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate, the entire structure is, first, covered by a tensile stress film. Patterning is then applied to the structure so as to selectively remove the tensile stress film from a region in which the p-channel MOS transistor is formed. 
     Subsequently, a compressive stress film is formed on the resultant structure in such a manner as to directly cover the p-channel MOS transistor in the region where the p-channel MOS transistor is formed, but cover the n-channel MOS transistor with the tensile stress film interposed in between in a region where the n-channel MOS transistor is formed. Next, the compressive stress film is selectively removed from the region where the n-channel MOS transistor is formed. 
     Alternatively, the compressive stress film may be formed first, and the tensile stress film may be subsequently formed. 
     Patterning of the compressive stress film is performed in the region where the n-channel MOS transistor is formed, and on the other hand, patterning of the tensile stress film is performed in the region where the p-channel MOS transistor is formed. It is therefore considered advantageous to use, for the patterning in each element region, an ion implantation mask used at the time of the well formation since this eliminates the necessity of designing a new mask pattern. 
     In view of this, a method of manufacturing a semiconductor integrated circuit device proposed by Japanese Laid-Open Patent Publication No. 2006-173432 involves the following procedures. That is, in the patterning of the tensile stress film, a mask used for the well formation in the element region of the p-channel MOS transistor is employed so as to leave a resist pattern only in the element region of the n-channel MOS transistor and remove the tensile stress film from the remaining region. On the other hand, in the patterning of the compressive stress film, a mask used for the well formation in the element region of the n-channel MOS transistor is employed so as to expose only the element region of the n-channel MOS transistor and, then, remove the tensile stress film only from the element region of the n-channel MOS transistor while covering the remaining region with a resist pattern. 
     In a semiconductor integrated circuit device formed in the above-mentioned manner, the tensile stress film is formed only in the element region of the n-channel MOS transistor and the remaining element region is covered by the compressive stress film. Alternatively, the compressive stress film is formed only in the element region of the p-channel MOS transistor and the remaining element region may be covered by the tensile stress film. 
     On the other hand, the area occupancies of the n-channel MOS transistor and the p-channel MOS transistor on the semiconductor substrate vary from product to product. Therefore, in such semiconductor integrated circuit devices, the area ratio between the tensile stress film and the compressive stress film is generally different from product to product. 
     Etching conditions for patterning are different between the tensile stress film and the compressive stress film. Accordingly, in the case where the area ratio between the tensile stress film and the compressive stress film on the semiconductor substrate is different among products, the etching conditions for patterning the tensile stress film and the compressive stress film need to be adjusted for individual products. However, it is difficult to optimize the etching conditions with respect to each product. 
     Recently, a business has been adopted that leases out different regions out of the same semiconductor wafer to various customers and manufactures semiconductor integrated circuit devices having different specifications according to individual requests for trial production. The above-described conventional manufacturing method cannot deal with cases like this. 
     SUMMARY 
     One aspect of the present disclosure is a semiconductor integrated circuit device including a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate. 
     The object and advantages of the disclosure will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  illustrates a process (part  1 ) for manufacturing a semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 1B  illustrates a process (part  2 ) for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 1C  illustrates a process (part  3 ) for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 1D  illustrates a process (part  4 ) for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 1E  illustrates a process (part  5 ) for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 1F  illustrates a process (part  6 ) for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 1G  illustrates a process (part  7 ) for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 1H  illustrates a process (part  8 ) for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 1I  illustrates a process (part  9 ) for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present disclosure; 
         FIG. 2  illustrates the relationship between area occupancy of a stress film pattern and etching rate; 
         FIG. 3  illustrates a structure of a semiconductor integrated circuit device according to a modification of the first embodiment; 
         FIG. 4  illustrates an example of dummy stress film patterns according to the second embodiment of the present disclosure; 
         FIG. 5  illustrates an example of a dummy stress film pattern according to a modification of the second embodiment; 
         FIG. 6  illustrates an example of a semiconductor integrated circuit device having dummy stress film patterns; 
         FIG. 7  illustrates another example of the semiconductor integrated circuit device having dummy stress film patterns; and 
         FIG. 8  illustrates yet another example of the semiconductor integrated circuit device having dummy stress film patterns. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     First Embodiment 
       FIGS. 1A through 1I  illustrate a method of manufacturing a semiconductor integrated circuit device according to the first embodiment of the present disclosure. On the semiconductor integrated circuit device, a stress-application p-channel MOS transistor and a stress-application n-channel MOS transistor are integrated. 
     With reference to  FIG. 1A , on a silicon substrate  11 , an n-channel MOS transistor element region  11 N and a p-channel MOS transistor element region  11 P are defined by an element isolating region  11 I having a shallow trench isolation (STI) structure. In the element region  11 N, a p-type impurity element is introduced to form a p-type well  11   pw , and in the element region  11 P, an n-type impurity element is introduced to form an n-type well  11   nw.    
     Furthermore, in the state illustrated in  FIG. 1A , an insulating film  12 , such as a thermally-oxidized film or an SiON film, is formed over the element regions  11 N and  11 P. 
     Next in the process illustrated in FIG.  1 B, a gate electrode  13 N and a gate electrode  13 P made of polysilicon, metal or the like are formed in the element regions  11 N and  11 P, respectively, in such a manner that gate insulating films  12 N and  12 P formed of the insulating film  12  are disposed between the gate electrode  13 N and the silicon substrate  11  and between the gate electrode  13 P and the silicon substrate  11 , respectively. In the element region  11 N, an n-type source extension region  11   a N and an n-type drain extension region  11   b N are provided on a first side and a second side, respectively, of the gate electrode  13 N. 
     Furthermore, sidewall insulating films  13   n  are formed on a first and a second sidewall surface which oppose each other across the gate electrode  13 N. In the element region  11 N, an n+ type source region  11   c N and an n+ type drain region  11   d N are disposed outward from the sidewall insulating films  13   n . On the surface of the source region  11   c N and the drain region  11   d N, individual silicide layers  11   s  are formed. 
     In the case where the gate electrode  13 N is formed using a polysilicon pattern, a silicide layer  14 N is disposed also on the gate electrode  13 N. 
     Also in the process illustrated in  FIG. 1B , in the element region  11 P, a p-type source extension region  11   a P and a p-type drain extension region  11   b P are provided on a first side and a second side, respectively, of the gate electrode  13 P. 
     Furthermore, sidewall insulating films  13   p  are formed on a first and a second sidewall surface which oppose each other across the gate electrode  13 P. In the element region  11 P, a p+ type source region  11   c P and a p+ type drain region  11   d P are disposed outward from the sidewall insulating films  13   p . On the surface of the source region  11   c P and the drain region  11   d P, individual silicide layers  11   s  are formed. 
     In the case where the gate electrode  13 P is formed using a polysilicon pattern, a silicide layer  14 P is disposed also on the gate electrode  13 P. 
     Next in the process illustrated in  FIG. 1C , a silicon oxide film  15  is formed as an etching stopper film in a thickness of, for example, 10 nm over the structure of  FIG. 1B  by plasma CVD (chemical vapor deposition) which uses TEOS (tetraethyl orthosilicate) as a basic ingredient. On top of the silicon oxide film  15 , an SiN film  16  having a tensile stress of, for example, 1.4 GPa is formed as a tensile stress film in a thickness of, for example, 80 nm. The formation of the SiN film  16  is achieved by thermal CVD using, for example, silane gas and ammonia gas as basic ingredients under the conditions of a pressure of between 0.1 and 400 Torr and a substrate temperature of between 500° C. and 700° C. 
     Next in the process illustrated in  FIG. 1D , a silicon oxide film  17  is formed as an etching stopper film in a thickness of, for example, 20 nm over the structure of  FIG. 1C  by plasma CVD which uses TEOS as a basic ingredient, as in the case of the silicon oxide film  15 . In the process of  FIG. 1E , the silicon oxide film  17  and the SiN film  16  are selectively removed from the element region  11 P using a resist pattern R 1  covering the element region  11 N as a mask and using the silicon oxide film  15  as an etching stopper. 
     At this point, in the present embodiment, a resist aperture RA is formed in the resist pattern R 1  using exposure data M 1  which are used to form the n-type well  11   nw . With the resist aperture RA, the SiN film  16  is removed from the p-channel MOS transistor element region. 
     At the same time in the process of  FIG. 1E , a dummy resist aperture RB is formed using dummy exposure data M 2  over a part of the element isolating region  11 I outside the element regions  11 N and  11 P. With the resist aperture RB, the silicon oxide film  17  and the underlying SiN film  16  are selectively removed using the silicon oxide film  15  as an etching stopper, at the same time when the procedure using the resist aperture RA is carried out. Herewith, an SiN dummy pattern  16 D, on top of which a silicon oxide film pattern  17 D is laid, is formed over the element isolating region  11 I in a dummy region  11 D. 
     The etching process of  FIG. 1E  is achieved by reactive ion etching (RIE) which uses C 4 F 8  gas, argon gas and oxygen gas, for example. 
     Next, in the process illustrated in  FIG. 1F , the resist pattern R 1  is removed, and then an SiN film  18  having a compressive stress of, for example, 1.4 GPa is formed over the structure of  FIG. 1E  as a compressive stress film in a thickness of, for example, 80 nm. The formation of the SiN film  18  is achieved by plasma CVD using, for example, silane gas and ammonia gas as basic ingredients under the conditions of a pressure of between 0.1 and 400 Torr and a substrate temperature of between 400° C. and 700° C. 
     Next in the process illustrated in  FIG. 1G , the silicon oxide film  18  is selectively removed from the element region  11 N using a resist pattern R 2  covering the element region  11 P as a mask and using the silicon oxide film  17  as an etching stopper. 
     At this point, in the present embodiment, the resist pattern R 2  is formed complementarily to the resist aperture RA using the exposure data M 1  which are used to form the n-type well  11   nw . As a result, the SiN film  18  is removed from an outside RC of the resist pattern R 2 , whereby the silicon oxide film  17  covering the n-channel MOS transistor is exposed. 
     The etching process of  FIG. 1G  is achieved by RIE using CHF 3  gas, Ar gas and oxygen gas. 
     At the same time in the process of  FIG. 1G , a dummy resist pattern R 2 D is formed complementarily to the resist aperture RB using the dummy exposure data M 2  over a part of the element isolating region  11 I outside the element regions  11 N and  11 P. The SiN film  18  is selectively removed using the dummy resist pattern R 2 D as a mask and using the silicon oxide film  17  as an etching stopper, at the same time when the above-described procedure in the region RC is carried out. Herewith, an SiN dummy pattern  18 D is formed in the dummy region  11 D complementarily to the SiN dummy pattern  16 D. 
     Next in the process illustrated in  FIG. 1H , the resist patterns R 2  and R 2 D are removed, and an interlayer insulating film  19  is disposed over the silicon substrate  11  so as to cover the exposed silicon oxide film  17  in the element region  11 N, cover the exposed SiN film  18  in the element region  11 P and cover the oxide film  17 D covering the dummy pattern  16 D as well as the dummy pattern  18 D in the dummy region  11 D. In the process illustrated in  FIG. 1I  after planarization is performed by chemical mechanical polishing (CMP), contact plugs  19 A,  19 B,  19 C and  19 D are formed in the interlayer insulating film  19  in such a manner as to be in contact with the diffusion regions  11   c N,  11   d N,  11   c P and  11   d P via the individual silicide layers  11   s.    
     The present embodiment is able to simplify manufacturing processes of semiconductor integrated circuit devices in the case where different semiconductor integrated circuit devices are manufactured, for example, in the case of manufacturing, after a first device is manufactured, a second device with the element region  11 N having a smaller total area. Specifically, when patterning is performed on the silicon oxide film  17  and the underlying tensile stress film  16  by RIE in the process of  FIG. 1E , as described above, the total etching area of the SiN film  16  over the semiconductor substrate  11  is maintained constant by increasing the total area of the dummy pattern  16 D. This eliminates the necessity of adjusting etching conditions with respect for each device, thus simplifying the manufacturing processes. Similarly, in the case of manufacturing, after a first device is manufactured, a second device with the element region  11 N having a larger total area, the total etching area of the SiN film  16  over the semiconductor substrate  11  is maintained constant by reducing the total area of the dummy pattern  16 D. 
       FIG. 2  illustrates the relationship between the etching rate and the area occupancy of the SiN film pattern formed on a silicon substrate and having compressive stress. 
     Etching is performed by RIE using CHF 3  gas, Ar gas and oxygen gas. With reference to  FIG. 2 , if the pattern occupancy over the silicon substrate is 30% or more, a substantially constant etching rate is achieved regardless of the pattern occupancy; however, if the pattern occupancy is less than 30%, the etching rate of the compressive stress film increases sharply. 
     It is considered that, in the case of a tensile stress film, substantially the same relationship exists between the etching rate and the pattern occupancy. Therefore, in a semiconductor device having a conventional structure in which the n-channel MOS transistor is covered by a tensile stress film and the p-channel MOS transistor is covered by a compressive stress film, if the total area of the n-channel MOS transistor accounts for 30% or less, for example, or if the total area of the p-channel MOS transistor accounts for 30% or less, the need arises to optimize the etching process of  FIG. 1E  or  1 G. 
     On the other hand, in the present embodiment, the dummy patterns  16 D and  18 D are formed on the silicon substrate  11 , whereby the ratio of the total area of the tensile stress film  16  to the total area of the compressive stress film  18  on the silicon substrate  11  is controlled to between 3/7 or more and 7/3 or less, preferably between 2/3 or more and 3/2 or less. Therefore, in either of the above cases (i.e. the case in which the total area of the n-channel MOS transistor accounts for 30% or less, and the case in which the total area of the p-channel MOS transistor accounts for 30% or less), the dry etching process of  FIG. 1E  can be performed under identical conditions, and similarly, the dry etching process of  FIG. 1G  can be performed under identical conditions. 
     In particular, by maintaining the ratio of the total area of the tensile stress film  16  to the total area of the compressive stress film  18  close to 1:1, it is possible to prevent the silicon substrate  11  or the silicon wafer from being distorted. 
     In the semiconductor integrated circuit device of the present embodiment, the tensile stress film  16  and the compressive stress film  18  are formed complementarily to each other. That is, the surface of the silicon substrate  11 , except for the contact holes, is entirely covered by either one of the tensile stress film  16  and the compressive stress film  18  without substantial overlapping between the tensile stress film  16  and the compressive stress film  18 . As a result, an extensive convex surface is absent on the silicon substrate  11 , which facilitates planarization of the surface of the interlayer insulating film  19  by CMP during the formation of the interlayer insulating film  19 . In the case where, due to displacement, the compressive stress film  18  locally overlaps the tensile stress film  16 , or a gap is present at the junction area between the compressive stress film  18  and the tensile stress film  16 , the present invention tolerates the overlapping part or the gap if it is comparable in width with a convex structure formed at where the compressive stress film  18  covers the gate electrode structure. 
     In the above embodiment, the following formation procedures may be adopted instead. That is, the compressive stress film  18  is first formed, and the tensile stress film  16  is formed after the compressive stress film  18  is selectively removed from the element region  11 N. 
       FIG. 3  illustrates the structure of such a semiconductor integrated circuit device in which the compressive stress film  18  is first formed and then the tensile stress film  16  is formed after the compressive stress film  18  is selectively removed from the element region  11 N. In this case, the tensile stress film  16  laid on top of the compressive stress film  18  is selectively removed from the element region  11 P. This structure should be clear from the descriptions given with reference to  FIGS. 1A through 1I , and therefore, further explanation is omitted. 
     Second Embodiment 
       FIG. 4  illustrates an example of dummy patterns  16 D and  18 D formed in the dummy region  11 D over the element isolating region  11 I. Note that, in  FIG. 4 , the silicon oxide film  17 D disposed on the surface of the dummy pattern  16 D is not illustrated. 
     With reference to  FIG. 4 , according to the present embodiment, the dummy patterns  18 D, each of which is formed of a compressive stress film measuring 3 μm per side, are disposed at intervals of 2 μm with a shift of 0.5 μm from the nearest dummy patterns  18 D in orthogonal directions. 
     The area ratio of the compressive stress film and the tensile stress film can be finely adjusted if the size of each dummy pattern  18 D is reduced; however, if the size of the dummy pattern  18 D is too small, drawing data becomes large, which incurs in an increase in manufacturing cost of the semiconductor integrated circuit device. Accordingly, it is preferable to form each dummy pattern  18 D measuring about 1 to 5 μm per side. The interval of the dummy patterns  18 D is adjusted according to the area ratio between the compressive stress film and the tensile stress film. 
     In  FIG. 4 , it appears that the element isolating region  11 I outside the dummy pattern  16 D is exposed; however, the figure is illustrated in this manner only for the intension of indicating that the dummy pattern  16 D is formed over the element isolating region  11 I, and the surface of the element isolating region  11 I is not exposed in fact. 
     According to  FIG. 4 , the isolated dummy patterns  18 D having compressive stress are aligned in the dummy pattern  16 D having tensile stress. However, isolated dummy patterns  16 D having tensile stress may be aligned in a dummy pattern  18 D having compressive stress, as illustrated in  FIG. 5 . 
       FIGS. 6 through 8  illustrate examples of dummy patterns formed in various semiconductor integrated circuit devices. 
     According to the examples of  FIGS. 6 and 7 , the strip-shaped element regions  11 P, each including the n-type well  11   nw , and the strip-shaped element regions  11 N, each including the p-type well  11   pw , are alternately aligned, and the isolated dummy patterns  18 D are formed, over the element isolating region  11 I, complementarily to the dummy pattern  16 D. 
     On the other hand, according to the example of  FIG. 8 , the element region  11 P including the n-type well  11   nw  and the element region  11 N including the p-type well  11   pw  are separately formed on the silicon substrate. In this case also, it can be seen that the dummy patterns  18 D are formed, over the element isolating region  11 I, complementarily to the dummy pattern  16 D. 
     According to the examples of  FIGS. 6 through 8 , the isolated dummy patterns  18 D are formed complementarily to the continuous dummy pattern  16 D which is formed of a tensile stress film. However, alternatively, the isolated dummy patterns  16 D may be formed complementarily to the continuous dummy pattern  18 D which is formed of a compressive stress film. 
     The following Table 1 concerns various semiconductor integrated circuit devices, Products A through D, and various test element groups TEG 1  through TEG 4 , and illustrates examples of the area occupancy of the compressive stress film before and after insertion of the dummy patterns  18 D. 
     
       
         
               
               
               
             
               
               
               
             
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 AREA OCCUPANCY OF 
                   
               
               
                   
                 COMPRESSIVE STRESS FILM 
               
             
          
           
               
                   
                 BEFORE DUMMY 
                 AFTER DUMMY 
               
               
                   
                 INSERTION 
                 INSERTION 
               
               
                   
                   
               
             
          
           
               
                   
                 PRODUCT A 
                 29.73% 
                 42.27% 
               
               
                   
                 PRODUCT B 
                 26.00% 
                 40.62% 
               
               
                   
                 PRODUCT C 
                 20.53% 
                 39.78% 
               
               
                   
                 PRODUCT D 
                 23.92% 
                 38.55% 
               
               
                   
                 TEG1 
                 10.73% 
                 36.17% 
               
               
                   
                 TEG2 
                 11.61% 
                 37.90% 
               
               
                   
                 TEG3 
                 17.07% 
                 41.06% 
               
               
                   
                 TEG4 
                 15.01% 
                 36.82% 
               
               
                   
                   
               
             
          
         
       
     
     With reference to Table 1, as for Products A through D, the area occupancy of the compressive stress film before the insertion of the dummy patterns  18 D is between 20% and 30%; however, the area occupancy after the insertion of the dummy patterns  18 D increases to between 38% and 42%. 
     Also, as for TEG 1  through TEG 4 , while the area occupancy of the compressive stress film before the insertion of the dummy patterns  18 D is between 10% and 15%, the area occupancy after the insertion of the dummy patterns  18 D increases to between 36% and 41%. 
     In conclusion, the present disclosure relates to a semiconductor integrated circuit device having a structure in which a tensile stress film is provided over the n-channel MOS transistor and a compressive stress film is provided over the p-channel MOS transistor. On a part of the semiconductor substrate at which neither the n-channel MOS transistor nor the p-channel MOS transistor are formed, the dummy pattern of the tensile stress film and the dummy pattern of the compressive stress film are formed complementarily to each other. That is, the surface of the semiconductor substrate is substantially covered by either one of the tensile stress film and the compressive stress film. Accordingly, in the case of manufacturing various semiconductor integrated circuit devices having different specifications of the p-channel MOS transistor and the n-channel MOS transistor, it is not necessary to optimize the etching processes conducted when patterning is performed on the tensile stress film and the compressive stress film, thereby reducing the manufacturing costs of the semiconductor integrated circuit devices. In addition, the ratio between the total area of the tensile stress film and the total area of the compressive stress film is controlled close to 1 by forming the dummy patterns, thereby preventing the semiconductor substrate from being distorted. 
     Thus, the embodiments of the present disclosure have been described in detail; however, it should be understood that the present invention is not limited to the particular embodiments and various changes and modification may be made to the particular embodiments without departing from the scope of the broad scope of the present invention as defined in the appended claims. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority or inferiority of the invention. Although the embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.