Abstract:
An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction

Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to the field of processors; more specifically, the present invention relates to an instruction buffer circuit for buffering multiple instructions for a processor simultaneously and a method of buffering multiple instructions for a processor simultaneously. 
   2. Background of the Invention 
   In a high performance processor application in order to maximize the number of instructions executed concurrently and to provide high bandwidth to the instruction cache, a large register file instruction buffer (IBUF) supporting multiple writes and reads is required. In our application, a 64-entry instruction buffer supporting 8 concurrent writes and 5 concurrent reads is required to allow for high concurrency in the pipeline. The conventional approach is to implement the register file instruction buffer with 8 write ports and 5 read ports. This approach requires a large SRAM cell area to support the required numerous read and write ports. It also requires a complex decoding scheme resulting in a slow access and large array area. The multi-ported array therefore represents a potential integration and timing problem. Therefore, an instruction buffer capable of supporting multiple writes and multiple reads concurrently and requiring a minimum amount of memory area and fast access is needed. 
   SUMMARY OF INVENTION 
   A first aspect of the present invention is an instruction buffer comprising: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction. 
   A second aspect of the present invention is a method of buffering instructions for a processor, comprising: providing a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction; and writing and reading instructions of the set of concurrent instructions to and from the memory array. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
       FIG. 1  is a schematic diagram of a portion of an exemplary single read port, single write port memory array; 
       FIG. 2  is a block schematic diagram of an exemplary instruction buffer utilizing single write port, single read port storage according to the present invention; 
       FIG. 3  is a block schematic diagram of a first exemplary data input rotator multiplexer of  FIG. 2 ; 
       FIG. 4  is a block schematic diagram of a second exemplary data input rotator multiplexer of  FIG. 2 ; 
       FIG. 5  is a block schematic diagram of an exemplary output multiplexer of  FIG. 2 ; 
       FIG. 6  is a block schematic diagram of an exemplary read decoder of  FIG. 2 ; 
       FIG. 7  is a block schematic diagram of an exemplary write decoder of  FIG. 2 ; and 
       FIG. 8  is a block schematic diagram of a general case instruction buffer utilizing a single write port, single read port storage according to the present invention. 
   

   DETAILED DESCRIPTION 
   The present invention uses a memory arrays comprised of single write port, single read port memory cells to make multiple concurrent writes to and reads from an instruction buffer. The present invention supports any number of concurrent writes and reads while still utilizing single read/write port memory cells. Examples of the type of memory arrays that may be used by the present invention include, but are not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), a latch array, or a register file. Since some details of the circuit implementation of the present invention depend on the number of write and read ports to the memory cells in the memory array portion of the invention, it is useful to review a single write port, single read port memory array and a multiple write port, multiple read port memory array. It will also make clearer some of the terminology used in describing the present invention. 
     FIG. 1  is a schematic diagram of a portion of an exemplary single read port, single write port memory array. In  FIG. 1 , a portion of an SRAM array  100  (an SRAM is used as an example) includes a storage latch comprised of inverters I 1  and I 2 , two write pass gates NFETs N 1  and N 2  and a read pass gate NFET N 3 . The gate of NFETs N 1  and N 2  are coupled to a write wordline (WR WL) and the gate of NFET N 3  is coupled to a read wordline (RD WL). The source/drains of NFET N 1  are coupled between a write bitline complement (WR BLC) and a storage node A. The source/drains of NFET N 2  are coupled between a write bitline true (WR BLT) and a storage node B. The source/drains of NFET N 3  are coupled between a read bitline (RD BL) and storage node B. The output of inverter I 1  is coupled to node A and the input of inverter I 2 . The output of inverter  12  is coupled to node B and the input of inverter I 1 . 
   In a write operation, data on WR BLC and WR BLT is written to storage nodes A and B by turning on WR WL. In a read operation, data on storage node B is read out to RD BL by turning on RD WL. While a single ended read is illustrated, a doubled ended read may be used by the present invention as well. 
     FIG. 2  is a block schematic diagram of an exemplary instruction buffer  110  utilizing single write port, single read port storage according to the present invention. In  FIG. 2 , instruction buffer  110  includes a memory array  115  comprised of eight memory sub-arrays  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G and  120 H, an input rotator multiplexer  125 , an output multiplexer  130 , a write address decoder  135  and a read address decoder  140 . Memory sub-arrays  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G and  120 H are also designated SA 0 , SA 1 , SA 2 , SA 3 , SA 4 , SA 5 , SA 6  and SA 7  respectively. This later designation will be used when emphasis of the physical or logical relationship of a memory sub-array to another component of instruction buffer  110  or to an instruction would aid in understanding the present invention. 
   Instruction buffer  110  is a 64 instruction-entry position, write eight instructions and read five instructions instruction buffer. 64 instructions is the maximum number of instructions that instruction buffer  110  is designed to hold. A 64 entry instruction buffer requires 6-bit addresses. Eight instructions is the maximum number of instructions that instruction buffer  110  is designed to receive concurrently. Five instructions is the maximum number of instructions instruction buffer  110  is designed to output concurrently. Concurrent instructions are defined to be a set of instructions having sequential addresses received and outputted in parallel by the processor. 
   Each memory sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G and  120 H is identical and comprises 480 memory cells organized into 8 rows (each row coupled to a different wordline) by 60 columns (each column coupled to a different bitline). The number of bitlines can vary and is a function of the maximum number of bits in an instruction. An instruction is stored in 60 memory cells connected to a single wordline. 
   Since instruction buffer  110  is a write eight instructions instruction buffer, input rotator multiplexer  125  is the logical equivalent of a stack of eight 8:1 multiplexers. There are eight input buses for receiving instruction I 0 , I 1 , I 2 , I 3 , I 4 , I 5 , I 6  and I 7  from an instruction cache (not shown), each bus being as wide as the maximum number of bits in an instruction (in the present example 60 bits wide). There are eight different 60-bit write bitline buses from each 8:1 multiplexer (or equivalent) corresponding to memory sub-arrays  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G and  120 H. The eight input buses may comprise 60-bit BLT buses, 60-bit BLC buses or 60-bit BLT buses and 60-bit BLC bus pairs. When only BLT buses are used, the BLC values are generated from the BLT values prior to writing to memory array  115 . When only BLC buses are used, the BLT values are generated from the BLC values prior to writing to memory array  115 . Which write bitline bus is connected to which sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G or  120 H is a function of the design of input rotator multiplexer  125  and examples are illustrated in detail in  FIGS. 3 and 4  and described infra. 
   Since instruction buffer  110  is a read five instructions instruction buffer, output multiplexer  130  is the logical equivalent of a stack of five 8:1 multiplexers. There are eight 60-bit read bitline buses, each coupled to a different and corresponding read bitline of a single and different memory-sub array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G or  120 H. Multiplexer  130  has five 60-bit output buses designated as R 0 , R 1 , R 2 , R 3  and R 4 . A single instruction appears at each output. Output multiplexer  130  is illustrated in detail in  FIG. 5  and described infra. 
   Since instruction buffer  110  is a 64-entry position, read five instructions instruction buffer, write address decoder  135  is coupled to memory array  115  by eight (64 entries divided by 8 instructions) 8-bit (number of instructions) write wordline buses. Each wordline bus is coupled to a different memory sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G or  120 H. Each bit of a particular write wordline bus is coupled to a different write wordline select of a corresponding particular memory sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G or  120 H. 
   It should be noted that memory array has 64 read wordlines and 64 write wordlines and that there are 8 read and 8 write wordlines in each sub-array. The first write wordline (or physical instruction entry) of the first memory sub-array, memory sub-array  120 A, is physical and logical write wordline  0  of memory array  115 . The next seven physically consecutive write wordlines in memory sub-array  120 A are each eight logical write wordlines (or logical instruction entry positions) higher than the immediately previous write wordline. The first write wordline of the second memory sub-array, memory sub-array  120 B, is physical write wordline  9  but logical write wordline  1  of memory array  115 . The next seven physically consecutive write wordlines in memory sub-array  120 B are each eight logical write wordlines (or instruction entry positions) higher than the immediately previous physical wordline. This pattern is repeated for remaining memory sub-arrays  120 C,  120 D,  120 E,  120 F,  120 G and  120 H. This means that each instruction of a set of eight concurrent instructions is written to a different memory sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G or  120 H. 
   Specifically, the 8-bit write wordline bus from write address decoder  135  to memory sub-array  120 A couples to logical write wordlines (or instruction entry positions)  0 ,  8 ,  16 ,  24 ,  32 ,  40 ,  48  and  56 , the 8-bit write wordline bus from write address decoder  135  to memory sub-array  120 B couples to logical write wordlines (or instruction entry positions)  1 ,  9 ,  17 ,  25 ,  33 ,  41 ,  49  and  59  and so forth until the 8-bit write wordline bus from write address decoder  135  to memory sub-array  120 H couples to logical write wordlines (or instruction entry positions)  7 ,  15 ,  23 ,  31 ,  39 ,  47 ,  55  and  63 . Therefore, eight instructions concurrently received at input rotator multiplexer  125  will be written to eight consecutive logical write wordlines located in physically different memory sub-arrays. Write decoder  135  is illustrated in detail in  FIG. 7  and described infra. 
   Since instruction buffer  110  is a 64-entry positions write eight instructions instruction buffer, read address decoder  140  is coupled to memory array  115  by eight 8-bit read wordline buses. Each read wordline bus is coupled to a different memory sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G and  120 H. Each bit of a particular read wordline bus is coupled to a different wordline of a corresponding particular memory sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G or  120 H. The mapping of physical read wordlines to logical read wordlines is similar to that for mapping physical write wordlines to logical write wordlines described supra. Read decoder  140  is illustrated in detail in  FIG. 6  and described infra. 
   Up to eight logically consecutive instructions are written to memory array  115  at sequential logical entry positions starting with the next available logical instruction entry position. For example, assume the first logical available instruction entry is 5. Then instructions will be written to the physical instruction entry positions as illustrated in TABLE I and there will be wrap between instruction I 2  and I 3 . Wrap means that a concurrent set of instructions is not stored on the same physical wordline position of each memory sub-array, but is shifted over one wordline and occurs when a set of concurrent instructions are written down to the last memory sub array and more sub-arrays are required to hold the rest of the set of concurrent instructions. 
   
     
       
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE I 
             
             
                 
             
           
           
             
               Instruction 
               I0 
               I1 
               I2 
               I3 
               I4 
               I5 
               I6 
               I7 
             
             
               Logical Entry 
               5 
               6 
               7 
               8 
               9 
               10 
               11 
               12 
             
             
               Sub-array 
               SA5 
               SA6 
               SA7 
               SA0 
               SA1 
               SA2 
               SA3 
               SA4 
             
             
               Sub-array 
                0 
                0 
                0 
                1 
                1 
                1 
                1 
                1 
             
             
               Wordline 
             
             
                 
             
           
        
       
     
   
   Up to five consecutive instructions are read from memory array  115  starting at the logical entry of instruction I 0 . For example, assume the first instruction (I 0 ) is stored at logical instruction entry  21 . Then instructions will be read from the physical instruction entry positions as illustrated in TABLE II. Instruction sequence is corrected by select signals applied to output multiplexer  130 . 
   
     
       
             
             
             
             
             
             
           
         
             
               TABLE II 
             
             
                 
             
           
           
             
               Logical Entry 
               21 
               22 
               23 
               24 
               25 
             
             
               Sub-array 
               SA5 
               SA6 
               SA7 
               SA0 
               SA1 
             
             
               Sub-array Wordline 
                2 
                2 
                2 
                3 
                3 
             
             
               (of wordlines 0–7) 
             
             
               Instruction 
               I0 
               I1 
               I2 
               I3 
               I4 
             
             
               Readout Order 
                1 
                2 
                3 
                4 
                5 
             
             
                 
             
           
        
       
     
   
   It should be note that the number of write and the number of read ports is less than the number of concurrent instructions to be written or to be read respectively. A general case instruction buffer according to the present invention is illustrated in  FIG. 8  and described infra. 
     FIG. 3  is a block schematic diagram of a first exemplary data input rotator multiplexer  125 A. In  FIG. 3 , input rotator multiplexer  125 A includes eight 8:1 multiplexers  145 A,  145 B,  145 C,  145 D,  145 E,  145 F,  145 G and  145 H. The eight inputs of each 8:1 multiplexer  145 A,  145 B,  145 C,  145 D,  145 E,  145 F,  145 G and  145 H are coupled to eight 60-bit input buses for receiving instructions I 0 , I 1 , I 2 , I 3 , I 4 , I 5 , I 6  and I 7  respectively. The output bus (60-bits wide) of each 8:1 multiplexer  145  is coupled to corresponding write bitline of different groups of memory sub-arrays  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G and  120 H. The output bus of first 8:1 multiplexer  145 A is coupled to memory sub-array  120 A. The output bus of second 8:1 multiplexer  145 B is coupled to memory sub-array  120 B. The output bus of third 8:1 multiplexer  145 C is coupled to memory sub-array  120 C. The output bus of fourth 8:1 multiplexer  145 D is coupled to memory sub-array  120 D. The output bus of fifth 8:1 multiplexer  145 E is coupled to memory sub-array  120 E. The output bus of sixth 8:1 multiplexer  145 F is coupled to memory sub-array  120 F. The output bus of seventh 8:1 multiplexer  145 G is coupled to memory sub-array  120 G. The output bus of eighth 8:1 multiplexer  145 H is coupled to memory sub-array  120 H. 
   The select input for each 8:1 multiplexer  145 A,  145 B,  145 C,  145 D,  145 E,  145 F,  145 G and  145 H is coupled to a control logic  150 . Control logic  150  keeps track of the next available logical entry in memory array  115  (see  FIG. 3 ) and generates a fully decoded 8-bit select signal SW 8  to “rotate” the incoming instructions I 0 , I 1 , I 2 , I 3 , I 4 , I 5 , I 6  and I 7  into the next eight available instruction entry positions. This address is generated by write decoder  135  (see  FIG. 8 ). While simple to design, a stack of eight 8:1 multiplexers and the connection to a memory array can require a large silicon area and a large numbers of wires. The logical to physical instruction entry mapping described supra allows simpler rotator multiplexer designs. One such example will now be discussed. 
     FIG. 4  is a block schematic diagram of a second exemplary data input rotator multiplexer  125 B. In  FIG. 4 , input rotator multiplexer  125 B includes eight 4:1 multiplexers ( 155 A,  155 B,  155 C,  155 D,  155 E,  155 F,  155 G and  155 H) and eight 2:1 multiplexers ( 160 A,  160 B,  160 C,  160 D,  160 E,  160 F,  160 G and  160 H). 
   The first, second, third and fourth inputs of 4:1 multiplexers  155 A are coupled respectively to the 60-bit bitline buses for receiving in instructions I 0 , I 1 , I 2 , and I 3  and the first, second, third and fourth inputs of 4:1 multiplexer  155 B are coupled respectively to the 60-bit write bitline buses for receiving instruction I 4 , I 5 , I 6 , and I 7 . The first, second, third and fourth inputs of 4:1 multiplexers  155 C are coupled respectively to the 60-bit bitline for receiving in instructions I 1 , I 2 , I 3 , and I 4  and the first, second, third and fourth inputs of 4:1 multiplexer  155 D are coupled respectively to the 60-bit write bitline buses for receiving instruction I 5 , I 6 , I 7 , and I 0 . The first, second, third and fourth inputs of 4:1 multiplexers  155 E are coupled respectively to the 60-bit bitline buses for receiving in instructions I 2 , I 3 , I 4 , and I 5  and the first, second, third and fourth inputs of 4:1 multiplexer  155 F are coupled respectively to the 60-bit write bitline for receiving instruction I 6 , I 7 , I 0 , and I 1 . The first, second, third and fourth inputs of 4:1 multiplexers  155 G are coupled respectively to the 60-bit bitline buses for receiving in instructions I 3 , I 4 , I 5 , and I 6  and the first, second, third and fourth inputs of 4:1 multiplexer  155 H are coupled respectively to the 60-bit write bitline buses for receiving instruction I 7 , I 0 , I 1 , and I 2 . 
   The output of 4:1 multiplexer  155 A is coupled to the first input of 2:1 multiplexers  160 A and second input of  160 B and the output of 4:1 multiplexer  155 B are coupled to the second input of 2:1 multiplexers  160 A and the first input  160 B. The output of 4:1 multiplexer  155 C is coupled to the first input of 2:1 multiplexers  160 C and the second input of  160 D and the output of 4:1 multiplexer  155 D are coupled to the second input of 2:1 multiplexers  160 C and the first input  160 D. The output of 4:1 multiplexer  155 E is coupled to the first input of 2:1 multiplexers  160 E and the second input of  160 F and the output of 4:1 multiplexer  155 F are coupled to the second input of 2:1 multiplexers  160 F and the first input  160 F. The output of 4:1 multiplexer  155 G is coupled to the first input of 2:1 multiplexers  160 G and the second input of  160 H and the output of 4:1 multiplexer  155 H are coupled to the second input of 2:1 multiplexers  160 G and the first input  160 H. 
   The output of 2:1 multiplexer  160 A is coupled to corresponding write bitlines in memory sub-array  120 A. The output of 2:1 multiplexer  160 B is coupled to corresponding write bitline in memory sub-array  120 E. The output of 2:1 multiplexer  160 C is coupled to corresponding write bitlines in memory sub-array  120 B. The output of 2:1 multiplexer  160 D is coupled to corresponding write bitlines in sub-array  120 F. The output of 2:1 multiplexer  160 E is coupled to corresponding write bitlines in memory sub-array  120 C. The output of 2:1 multiplexer  160 F is coupled to corresponding write bitlines in memory sub-array  120 G. The output of 2:1 multiplexer  160 G is coupled to corresponding write bitlines in memory sub-array  120 C. The output of 2:1 multiplexer  160 H is coupled to corresponding write bitlines in memory sub-array  120 H. 
   Thus, a portion of the rotation required is accomplished by the interconnections of rotator multiplexer  125 B and multiplexer select signals may be simplified. All 4:1 multiplexers  155 A,  155 B,  155 C,  155 D,  155 E,  155 F,  155 G and  155 H share the same decoded 4-bit select signal SW 4  and all 2:1 multiplexers  160 A,  160 B,  160 C,  160 D,  160 E,  160 F,  160 G and  160 H share the same 1-bit select signal SW 2  generated by control logic  165  based on the physical location in memory array  115  of the first available instruction entry position. Control logic  165  keeps track of the next available logical entry in memory array  115  (see  FIG. 2 ) and generates the 5 bits of select signals SW 2  and SW 4  based on the address of the physical location in memory array  115  (see  FIG. 2 ) of the first instruction that is to be available to be written to. (There must also be sufficient available sequential logical instruction entry positions to hold the entire set of concurrent instructions.) This address is generated by write decoder  140  (see  FIG. 2 ). For example with SW 4  set to select input  3  of all 4:1 multiplexers  155 A,  155 B,  155 C,  155 D,  155 E,  155 F,  155 G and  155 H and SW 2  set to select input  1  of all 2:1 multiplexers  160 A,  160 B,  160 C,  160 D,  160 E,  160 F,  160 G and  160 H, then SA 0  receives instruction I 2 , SA 1  receives instruction I 3 , SA 2  receives instruction I 4 , SA 3  receives instruction I 5 , SA 4  receives instruction I 6 , SA 5  receives instruction I 7 , SA 6  receives instruction I 0  and SA 7  receives instruction I 1 . The instructions are in sequential order I 2 , I 3 , I 4 , I 5 , I 6 , I 7 , I 0  and I 1  though wrapped. 
     FIG. 5  is a block schematic diagram of an exemplary output multiplexer  130  of  FIG. 2 . In  FIG. 5 , output multiplexer  130  includes five 8:1 multiplexers  170 A,  170 B,  170 C,  170 D and  170 E. Each 8:1 multiplexer  170 A,  170 B,  170 C,  170 D and  170 E is coupled to the same eight 60-bit read bitline buses but in a different order. Input buses to 8:1 multiplexer  170 A are in the order SA 0 , SA 1 , SA 2 , SA 3 , SA 4 , SA 5 , SA 6  and SA 7 . Input buses to 8:1 multiplexer  170 B are in the order SA 1 , SA 2 , SA 3 , SA 4 , SA 5 , SA 6 , SA 7  and SA 0 . Input buses to 8:1 multiplexer  170 C are in the order SA 2 , SA 3 , SA 4 , SA 5 , SA 6 , SA 7 , SA 0  and SA 1 . Input buses to 8:1 multiplexer  170 D are in the order SA 3 , SA 4 , SA 5 , SA 6 , SA 7 , SA 0 , SA 1  and SA 2 . Input buses to 8:1 multiplexer  170 E are in the order SA 4 , SA 5 , SA 6 , SA 7 , SA 0 , SA 1 , SA 2  and SA 3 . Each read bitline bus is coupled to a different and corresponding read bitline of a single and different memory-sub array SA 0 , SA 1 , SA 2 , SA 3 , SA 4 , SA 5 , SA 6  through SA 7 . Each 8:1 multiplexer  170 A,  170 B,  170 C,  170 D and  170 E has a 60-bit output bus corresponding to five result outputs R 0 , R 1 , R 2 , R 3  and R 4 . 
   Control logic  175  decodes the read address bits ADDR&lt;3:5&gt; only from the starting (first) read address into an 8-bit select signal which is applied to the select input of each of the five 8:1 multiplexers  170 A,  170 B,  170 C,  170 D and  170 E respectively in order to ensure that instruction I 0  appears at output R 0 , instruction I 1  at output R 1 , instruction I 2  at output R 2 , instruction I 3  at output R 3  and instruction I 4  at output R 4 . Select signal SR is generated by control logic  175  based on the address of the physical location in memory array  115  (see  FIG. 3 ) of the first instruction (I 0 ) that is to be read out. 
   Note, prior art write 8/read 5 instruction buffers require a full 6-bit wordline address decode for not only the first instruction&#39;s wordline address but also for all subsequent instruction wordline addresses. This entails four additional serial increments of the first address to obtain all five wordline addresses. Thus, the present invention saves decode time (is faster than the prior art) and since there are less circuits required, the present inventions uses less integrated circuit chip area. 
     FIG. 6  is a block schematic diagram of an exemplary read decoder  140  of  FIG. 3 . In  FIG. 6 , read address decoder  140  includes four 2:1 multiplexers  180 A,  180 B,  180 C and  180 D, a read wordline decoder  185  and eight output buses  190 A,  190 B,  190 C,  190 D,  190 E,  190 F,  190 G and  190 H. 
   Addresses of wordlines are coded into a six bit read address (RD ADDR&lt;0:5&gt;) wherein bits&lt;3:5&gt; specify the starting memory sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G or  120 H, and bits &lt;0:2&gt; indicate the wordline in the particular memory sub-array. Six bits support 64 unique wordline addresses. Read wordline decoder  185  operates on the first 3 bits (&lt;0:2&gt;) of 6-bit address (1st RD ADDR &lt;0:5&gt;) of the first instruction entry to be read out. First a 3-bit to 8-bit decode using bits &lt;0:2&gt; of 1st RD ADDR &lt;0:5&gt; is performed to generate an 8-bit read wordline address (RD WL &lt;0:7&gt;). RD WL &lt;0:7&gt; is shifted by one bit to obtain RD WL &lt;1:7,0&gt;. RD WL &lt;0:7&gt; is coupled to the 0 select input of multiplexers  180 A,  180 B,  180 C and  180 D as well as the address select circuits of memory sub-arrays  120 E,  120 F,  120 G and  120 H. RD WL &lt;1:7,0&gt; is coupled to the 1 select input of multiplexers  180 A,  180 B,  180 C and  180 D. The output of multiplexers  180 A,  180 B,  180 C and  180 D is coupled to respective address select circuits of memory sub-arrays  120 A,  120 B,  120 C and  120 D. The select input of multiplexers  180 A,  180 B,  180 C and  180 D is coupled to ADDR &lt;3&gt;. 
   This decode scheme, takes advantage of the fact that there are only eight possible ways five concurrent instructions can be stored in memory sub-arrays  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G and  120 H as illustrated in TABLE III. 
   
     
       
             
             
             
           
         
             
               TABLE III 
             
             
                 
             
             
               FIRST INSTRUCTION 
               FIFTH INSTRUCTION 
               WRAP 
             
             
                 
             
           
           
             
               Memory sub-array 120A (SA0) 
               Memory sub-array 120E 
               No 
             
             
                 
               (SA4) 
             
             
               Memory sub-array 120B (SA1) 
               Memory sub-array 120F 
               No 
             
             
                 
               (SA5) 
             
             
               Memory sub-array 120C (SA2) 
               Memory sub-array 120G 
               No 
             
             
                 
               (SA6) 
             
             
               Memory sub-array 120D (SA3) 
               Memory sub-array 120H 
               No 
             
             
                 
               (SA7) 
             
             
               Memory sub-array 120E (SA4) 
               Memory sub-array 120A 
               Yes 
             
             
                 
               (SA0) 
             
             
               Memory sub-array 120F (SA5) 
               Memory sub-array 120B 
               Yes 
             
             
                 
               (SA1) 
             
             
               Memory sub-array 120G (SA6) 
               Memory sub-array 120C 
               Yes 
             
             
                 
               (SA2) 
             
             
               Memory sub-array 120H (SA7) 
               Memory sub-array 120D 
               Yes 
             
             
                 
               (SA3) 
             
             
                 
             
           
        
       
     
   
   An example of how this “quick” address decode works is illustrated in Table IV where it is assumed five instructions are to be read from logical instruction entry positions 21, 22, 23, 24 and 25. 
   
     
       
             
             
             
             
             
             
             
           
         
             
               TABLE IV 
             
             
                 
             
             
                 
                 
                 
                 
                 
                 
               RD WL 
             
             
                 
                 
                 
                 
                 
               ADDR 
               ADDR &lt;1:7,0&gt; 
             
             
                 
               ADDR 
               ADDR 
               WL 
               Sub 
               &lt;0:2&gt; 
               (Shifted 
             
             
               Entry 
               &lt;0:2&gt; 
               &lt;3:5&gt; 
               Pos 
               Array 
               in 8-bit code 
               Entry 21) 
             
             
                 
             
           
           
             
               21 
               0 1 0 
               1 0 1 
               2 
               SA5 
               0 0 0 0 0 1 0 0 
                 
             
             
               22 
               0 1 0 
               1 1 0 
               2 
               SA6 
               0 0 0 0 0 1 0 0 
             
             
               23 
               0 1 0 
               1 1 1 
               2 
               SA7 
               0 0 0 0 0 1 0 0 
             
             
               24 
               0 1 1 
               0 0 0 
               3 
               SA0 
                 
               0 0 0 0 1 0 0 0 
             
             
               25 
               0 1 1 
               0 0 1 
               3 
               SA1 
                 
               0 0 0 0 1 0 0 0 
             
             
                 
             
           
        
       
     
   
   Note, only address  21  was decoded, addresses  22 – 25  were derived from address  21 . 
   Instructions  21 ,  22  and  23  can use RD WL &lt;0:7&gt; because that is the actual wordline address of entry positions  21 ,  22  and  23 . Instructions  24  and  25  can use RD WL &lt;1:7,0&gt; because that shift results in the actual addresses of entry positions  24  and  25 . 
     FIG. 7  is a block schematic diagram of an exemplary write decoder  135  of  FIG. 3 . In  FIG. 7 , write address decoder  135  includes seven 2:1 multiplexers  195 A,  195 B,  195 C,  195 D,  195 E,  195 F and  195 G, a write wordline decoder  200  and eight output buses  205 A,  205 B,  205 C,  205 D,  205 E,  205 F,  205 G and  205 H. 
   Addresses of wordlines are coded into a six bit write address (WR ADDR&lt;0:5&gt;) wherein bits&lt;3:5&gt; specify the starting memory sub-array  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G or  120 H, and bits &lt;0:2&gt; indicate the wordline in the particular memory sub-array. Write wordline decoder  200  operates only on the first address (1st WR ADDR &lt;0:5&gt;) of the first instruction entry to be written in. First a 3-bit to 8-bit decode using bits &lt;0:2&gt; of 1st WR ADDR &lt;0:5&gt; is performed to generate an 8-bit write wordline address (WR WL &lt;0:7&gt;). WR WL &lt;0:7&gt; is shifted by one bit to obtain WR WL &lt;1:7,0&gt;. WR WL &lt;0:7&gt; is coupled to the 0 select input of multiplexers  195 A,  195 B,  195 C,  195 D,  195 E,  195 F and  195 G as well as the address select circuits of memory sub- 120 H. RD WL &lt;1:7,0&gt; is coupled to the 1 select input of multiplexers  195 A,  195 B,  195 C,  195 D,  195 E,  195 F and  195 G. The output of multiplexers  195 A,  195 B,  195 C,  195 D,  195 E,  195 F and  195 G is coupled to respective address select circuits of memory sub-arrays  120 A,  120 B,  120 C,  120 D,  120 E,  120 F and  120 G. The select inputs of multiplexers  195 A,  195 B,  195 C,  195 D,  195 E,  195 F and  195 G are generated from ADDR &lt;3:5&gt; by logic circuits within write decoder  135 . 
   The generation of write addresses is similar the generation of read addresses discussed supra with the exception that instead of the address of the first instruction entry to be read out, the address of the first available instruction entry in array  115  (see  FIG. 2 ) is used as the seed address. 
   There are only eight possible ways eight concurrent instructions can be stored in memory sub-arrays  120 A,  120 B,  120 C,  120 D,  120 E,  120 F,  120 G and  120 H as illustrated in TABLE V. 
   
     
       
             
             
             
           
         
             
               TABLE V 
             
             
                 
             
             
               FIRST INSTRUCTION 
               EIGHTH INSTRUCTION 
               WRAP 
             
             
                 
             
           
           
             
               Memory sub-array 120A (SA0) 
               Memory sub-array 120H 
               No 
             
             
                 
               (SA7) 
             
             
               Memory sub-array 120B (SA1) 
               Memory sub-array 120A 
               Yes 
             
             
                 
               (SA0) 
             
             
               Memory sub-array 120C (SA2) 
               Memory sub-array 120B 
               Yes 
             
             
                 
               (SA1) 
             
             
               Memory sub-array 120D (SA3) 
               Memory sub-array 120C 
               Yes 
             
             
                 
               (SA2) 
             
             
               Memory sub-array 120E (SA4) 
               Memory sub-array 120D 
               Yes 
             
             
                 
               (SA3) 
             
             
               Memory sub-array 120F (SA5) 
               Memory sub-array 120E 
               Yes 
             
             
                 
               (SA4) 
             
             
               Memory sub-array 120G (SA6) 
               Memory sub-array 120F 
               Yes 
             
             
                 
               (SA5) 
             
             
               Memory sub-array 120H (SA7) 
               Memory sub-array 120G 
               Yes 
             
             
                 
               (SA6) 
             
             
                 
             
           
        
       
     
   
   An example of how this “quick” address decode works is illustrated in Table VI where it is assumed eight instructions are to be written to logical instruction entry positions  23 ,  24 ,  25 ,  26 ,  27  and  28 . 
   
     
       
             
             
             
             
             
             
             
           
         
             
               TABLE VI 
             
             
                 
             
             
                 
                 
                 
                 
                 
                 
               WR WL 
             
             
                 
                 
                 
                 
                 
               ADDR 
               ADDR&lt;1:7,0&gt; 
             
             
                 
               ADDR 
               ADDR 
               WL 
               Sub 
               &lt;0:2&gt; 
               (Shifted 
             
             
               Entry 
               &lt;0:2&gt; 
               &lt;3:5&gt; 
               Pos 
               Array 
               in 8-bit code 
               Entry 21) 
             
             
                 
             
           
           
             
               21 
               0 1 0 
               1 0 1 
               2 
               SA5 
               00000100 
                 
             
             
               22 
               0 1 0 
               1 1 0 
               2 
               SA6 
               0 0 0 0 0 1 0 0 
             
             
               23 
               0 1 0 
               1 1 1 
               2 
               SA7 
               0 0 0 0 0 1 0 0 
             
             
               24 
               0 1 1 
               0 0 0 
               3 
               SA0 
                 
               0 0 0 0 1 0 0 0 
             
             
               25 
               0 1 1 
               0 0 1 
               3 
               SA1 
                 
               0 0 0 0 1 0 0 0 
             
             
               26 
               0 1 1 
               0 1 1 
               3 
               SA2 
                 
               0 0 0 0 1 0 0 0 
             
             
               27 
               0 1 1 
               1 0 0 
               3 
               SA3 
                 
               0 0 0 0 1 0 0 0 
             
             
               28 
               0 1 1 
               1 0 1 
               3 
               SA4 
                 
               0 0 0 0 1 0 0 0 
             
             
                 
             
           
        
       
     
   
   Note, only address  21  was decoded, addresses  22 – 28  were derived from address  21 . 
   Instructions  21 ,  22  and  23  can use WRD WL &lt;0:7&gt; because that is the actual wordline address of entry positions  21 ,  22  and  23 . Instructions  24 ,  25 ,  26 ,  27  and  28  can use WR WL &lt;1:7,0&gt; because that shift results in the actual addresses of entry positions  24 ,  25 ,  26 ,  27  and  28 . 
     FIG. 8  is a block schematic diagram of a general case instruction buffer utilizing single write port, single read port storage according to the present invention. In  FIG. 8 , instruction buffer  210  includes a memory array  215  comprised of N memory sub-arrays  220 , an input rotator multiplexer  225 , an output multiplexer  230 , a write address decoder  235  and a read address decoder  240 . 
   Instruction buffer  210  is an N×Q instruction-entry, write N instructions and read M instructions instruction buffer. N instructions are the maximum number of instructions instruction buffer  210  is designed to write in concurrently. M instructions are the maximum number of instructions instruction buffer  210  is designed to read out concurrently. It should be noted that the number of memory sub arrays is equal to the maximum number, N, of concurrent write instructions. 
   Each memory sub-array  220  is identical and comprises Q×X memory cells organized into Q rows (each row coupled to a different wordline) by X columns (each column coupled to a different bitline). An instruction is stored in the X memory cells connected to a single wordline. The physical wordlines in each memory sub-array  220  are N logical wordlines apart. The same physical wordline positions in adjacent memory sub-arrays  220  are one logical wordline apart. 
   Since instruction buffer  210  is a write N instructions instruction buffer, input rotator multiplexer  225  is the logical equivalent of a stack of N (N:1) multiplexers. There are N input buses for receiving instruction I 0  through I(N−1) from an instruction cache (not shown), each bus is X-bits wide. There are N different X-bit write bitline buses from each N:1 multiplexer (or equivalent) each connected to a different memory sub-array  220 . The N input buses may comprise X-bit BLT buses, X-bit BLC buses or X-bit BLT and X-bit BLC bus pairs. When only BLT buses are used, the BLC values are generated from the BLT values prior to writing to memory array  215 . When only BLC buses are used, the BLT values are generated from the BLC values prior to writing to memory array  215 . 
   Since instruction buffer  210  is a read M instructions instruction buffer, output multiplexer  230  is the logical equivalent of a stack of M (N:1) multiplexers. There are N X-bit read bitline buses, each coupled to a different and corresponding read bitline of a single and different memory-sub array  220 . Multiplexer  230  has M X-bit output buses corresponding to the designated as R 0  through RM. 
   Each wordline bus is coupled to a different memory sub-array  220 . Each bit of a particular write wordline bus is coupled to a different write wordline of a corresponding particular memory sub-array  220 . 
   In the present example, M is less than or equal to N. In the present example, N is a power of 2 in order to keep address decoding relatively simple. 
   Thus, the present invention provides an instruction buffer capable of supporting multiple writes and multiple reads concurrently and requiring a minimum amount of memory area and providing fast access. 
   The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.