Abstract:
A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control signal. A delay circuit may be coupled between the first and second transmission gates so that the delay circuit is configured to receive a test input signal through the first transmission gate and to transmit a delayed test input signal to the second transmission gate, and the delayed test input signal may correspond to the test input signal. A latch may be coupled between the second transmission gate and an output of the semiconductor device, and the latch may be configured to latch a first logic value when a duration of the test clock signal pulse is less than a delay of the delay circuit and to latch a second logic value when a duration of the test clock signal pulse is greater than the delay of the delay circuit, and the first and second logic values be different. Related methods are also discussed.

Description:
RELATED APPLICATION  
       [0001]     This application claims the benefit of Korean Patent Application No. 2005-76986, filed Aug. 22, 2005, the disclosure of which is hereby incorporated herein by reference in its entirety.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to electronics, and more particularly, to semiconductor devices and related methods of testing.  
       BACKGROUND  
       [0003]     In general, a semiconductor device includes a number of integrated electronic circuits, and a plurality of semiconductor devices may be fabricated on a single wafer. However, delay times of elements of the semiconductor device(s) may change over time due to variations of fabrication processes. In other words, delay times of semiconductor device elements may be longer and/or shorter than those intended by design.  
         [0004]     Conventionally, a plurality of semiconductor devices (e.g., semiconductor memory devices) may be provided on a single wafer, and test circuits may be disposed in spaces between the semiconductor devices to measure delay times of various elements.  
         [0005]      FIG. 1  shows construction of a test circuit of a conventional semiconductor device. Referring to  FIG. 1 , the test circuit includes a power supply voltage pad PA 1 , a ground voltage pad PA 2 , output pads PB 1  to PBn, and first to n-th ring oscillators  10 - 1  to  10 -n. The first to n-th ring oscillators  10 - 1  to  10 -n include first to n-th delay circuits DL 1  to DLn, respectively. In  FIG. 1 , each of the first to n-th delay circuits DL 1  to DLn includes different elements.  
         [0006]     A method for measuring delay times of the respective elements of the first to n-th delay circuits DL 1  to DLn will now be described with reference to  FIG. 1 . When a power supply voltage and a ground voltage are applied from a test apparatus (not shown) to the power supply voltage pad PA 1  and the ground voltage pad PA 2 , respectively, the first to n-th ring oscillators  10 - 1  to  10 -n generate clock signals at the respective output pads PB 1  to PBn. The test apparatus receives the clock signals from the output pads PB 1  to PBn and measures cycles of the clock signals so that the test apparatus can calculate delay times of the respective elements of the first to n-th delay circuits DL 1  to DLn.  
         [0007]     A typical ring oscillator includes an odd number of inverters that are cascade-connected. For example, assuming that each of the first to n-th delay circuits DL 1  to DLn includes 7 cascade-connected inverters and a designed delay time of each of the inverters is preset to 1 nsec, the total delay time of the 7 inverters should be 7 nsec and thus, the cycle of each of the clock signals should be 14 nsec. If each of the clock signals output through the output pads PB 1  to PBn has a cycle of 15 nsec, it can be determined that each of the inverters has a cycle of 15/14 nsec that is greater than the designed delay time (i.e., 1 nsec).  
         [0008]     Because the conventional test circuit is disposed in the space between the semiconductor devices on the wafer, however, the test circuit can be measured only in the wafer state and cannot be measured during or after a packaging process.  
       SUMMARY  
       [0009]     According to some embodiments of the present invention, a semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control signal. A delay circuit may be coupled between the first and second transmission gates so that the delay circuit is configured to receive a test input signal through the first transmission gate and to transmit a delayed test input signal to the second transmission gate, and the delayed test input signal may correspond to the test input signal. A latch may be coupled between the second transmission gate and an output of the semiconductor device, and the latch may be configured to latch a first logic value when a duration of the test clock signal pulse is less than a delay of the delay circuit and to latch a second logic value when a duration of the test clock signal pulse is greater than the delay of the delay circuit, and the first and second logic values may be different.  
         [0010]     According to some other embodiments of the present invention, methods of operating a semiconductor device may include generating a test control signal in response to an externally applied test command signal, and opening and closing first and second transmission gates together in response to a test clock signal pulse and the test control signal. A test input signal may be received through the first transmission gate at a delay circuit coupled between the first and second transmission gates, and the test input signal may be transmitted through the delay circuit to generate a delayed test input signal corresponding to the test input signal. When a duration of the test clock signal pulse is less than a delay of the delay circuit, a first logic value may be latched, and when a duration of the test clock signal pulse is greater than a delay of the delay circuit, a second logic value may be latched, and the first and second logic values may be different.  
         [0011]     According to embodiments of the present invention, semiconductor devices may be provided that allow measurement of delay times of elements in a wafer state and also in a package state. According to other embodiments of the present invention, methods for testing semiconductor devices may also be provided.  
         [0012]     According to some embodiments of, the present invention, a semiconductor device may include a control signal generator configured to generate test control signals and a test enable signal in response to an externally applied command signal and an externally applied code signal. At least one delay unit may be configured to generate an internal clock signal in response to an external clock signal and one of the test control signals. The at least one delay unit may be further configured to receive a test input signal in response to a level of the internal clock signal to delay the test input signal, to generate the delayed test input signal, and to transmit the delayed test input signal to a common output node in response to the same level as the level of the internal clock signal.  
         [0013]     The semiconductor device may further include a first switch configured to generate an externally applied input signal as a normal input signal during a normal operation and to generate the externally applied input signal as the test input signal during a test operation, in response to the test enable signal. A second switch may be configured to generate a normal output signal as an output signal during normal operation and to generate a signal output from the common output node as the output signal during the test operation, in response to the test enable signal. The semiconductor device may further include a latch configured to latch the signal output from the common output node and to transmit the latched signal to the second switch. A reset transistor may be configured to reset the signal output from the common output node in response to the test enable signal. The delay unit may include a plurality of cascade-connected elements with the same delay time.  
         [0014]     The at least one delay unit may include a logic gate configured to perform a logic operation on the external clock signal and one of the test control signals and to generate the internal clock signal. A first transmission gate may be configured to transmit the test input signal in response to the level of the internal clock signal. A delay unit may be configured to delay the test input signal and to generate the delayed test input signal. A second transmission gate may be configured to transmit the delayed test input signal to the common output node in response to the same level as the level of the internal clock signal.  
         [0015]     The control signal generator may include a command decoder configured to decode the common signal and to generate a mode setting signal. A mode setting circuit may be configured to receive the code signal in response to the mode setting signal and to generate the test control signals. A logic gate may be configured to perform a logic OR operation on the test control signals and to generate the test enable signal.  
         [0016]     According to some other embodiments of the present invention, a method for testing a semiconductor devices may include decoding an externally applied command signal to generate a mode setting signal, receiving an externally applied code signal in response to the mode setting signal to generate test control signals, and generating a test enable signal in response to the test control signals. An external clock signal may be received in response to one of the test control signals to generate an internal clock signal. A test input signal may be received in response to a first level of the internal clock signal and the test input signal may be delayed using a delay unit to generate a delayed test input signal. The delayed test input signal may be transmitted as an output signal in response to the same level as the first level of the internal clock signal. The external clock signal may be applied while changing the external clock signal in order to change a time point at which the internal clock signal makes a transition from the first level to a second level until an abnormal signal is output as the output signal. The second level may be different from the first level. The same level as the first level of the internal clock signal may be maintained longer than a preset delay time of the delay unit.  
         [0017]     According to still other embodiments of the present invention, a method for testing a semiconductor device may include decoding an externally applied common signal to generate a mode setting signal, receiving an externally applied code signal in response to the mode setting signal to generate test control signals, and generating a test enable signal in response to the test control signals. An external clock signal may be received in response to one of the test control signals to generate an internal clock signal. A test input signal may be received in response to a first level of the internal clock signal, the test input signal may be delayed using a delay unit to generate the delayed test input signal, and the delayed test input signal may be transmitted as an output signal in response to the same level as the first level of the internal clock signal. The external clock signal may be applied while changing the external clock signal to change a time point at which the internal clock signal makes a transition from the first level to a second level until a normal signal is output as the output signal, and the second level may be different from the first level.  
         [0018]     Generating the output signal may include transmitting the test input signal in response to the first level of the internal clock signal. The test input signal may be delayed to generate the delayed test input signal. The delayed test input signal may be transmitted as the ouptut signal in response to the same level of the first level of the internal clock signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The foregoing and other objects, features and advantages of the invention will be apparent from description of embodiments of the invention, as illustrated in the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating principles of the invention.  
         [0020]      FIG. 1  is a block diagram illustrating construction of a test circuit of a conventional semiconductor device.  
         [0021]      FIG. 2  is a block diagram illustrating a semiconductor device according to embodiments of the present invention.  
         [0022]      FIGS. 3A and 3B  are circuit diagrams of delay units of  FIG. 2 .  
         [0023]      FIG. 4  is a timing diagram illustrating operations of testing the semiconductor device of  FIG. 2 . 
     
    
     DETAILED DESCRIPTION  
       [0024]     While the present invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims.  
         [0025]     It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected to” or “directly coupled to” another element, there are no intervening elements. As used herein, the term “and/or ” and“/” includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout the description.  
         [0026]     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.  
         [0027]     It will be understood that although the terms first and second are used herein to describe various components, circuits, regions, layers and/or sections, these components, circuits, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one component, circuit, region, layer or section from another component, circuit, region, layer or section. Thus, a first component, circuit, region, layer or section discussed below could be termed a second component, circuit, region, layer or section, and similarly, a second component, circuit, region, layer or section may be termed a first component, circuit, region, layer or section without departing from the teachings of the present invention.  
         [0028]     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.  
         [0029]      FIG. 2  illustrates construction of a semiconductor device  200  (such as a semiconductor memory device) including test circuitry according to embodiments of the present invention. Referring to  FIG. 2 , the test circuitry includes a command decoder  20 , a mode setting circuit  22 , a reset signal generator  24 , first and second switches  26  and  28 , a latch LA, an inverter I 4 , a PMOS transistor PM, and first to n-th delay circuits  30 - 1  to  30 -n. The command decoder  20 , the mode setting circuit  22 , and the reset signal generator  24  may together define a control signal generator. The semiconductor device  200  may also include functional electronics  202 , such as memory electronics including a memory cell array(s). Accordingly, the semiconductor device  200  may be a semiconductor memory device. The latch LA includes inverters I 2  and I 3 , and each of the first to n-th delay circuits  30 - 1  to  30 -n includes CMOS transmission gates C 1  and C 2  and an inverter I 1 . In addition, each of the first to n-th delay circuits  30 - 1  to  30 -n includes first to n-th NAND gates NA 1  to NAn and first to n-th delay units DL 1  to DLn, respectively. The first to n-th delay units DL 1  to DLn are composed of different delay elements from one another.  
         [0030]     An external power supply voltage EVC is applied as a power supply voltage to the first to n-th delay circuits  30 - 1  to  30 -n shown in  FIG. 2 . Functions of the respective components shown in  FIG. 2  will now be described.  
         [0031]     The command decoder  20  receives an external command signal COM, decodes the command signal COM, and generates a mode setting signal MRS. The mode setting circuit  22  receives an external code signal CODE in response to the mode setting signal MRS, decodes the code signal CODE, and generates test control signals T 1  to Tn. The reset signal generator  24  performs a logic OR operation on the test control signals T 1  to Tn and generates a test enable signal TEN.  
         [0032]     The first switch  26  receives an external input signal IN through an input/output pad and generates a normal input signal NIN when the test enable signal TEN is disabled during a normal operation. More particularly, the first switch may couple a normal input signal NIN from the input pad to functional electronics  202  (such as a memory cell array) during normal operations. The first switch  26  generates the test input signal TIN when the test enable signal TEN is enabled during a test operation responsive to a test input signal applied to the input/output pad. The second switch  28  provides an internally received normal output signal NOUT as an output signal OUT when the test enable signal TEN is disabled during normal operations, and provides a test output signal TOUT as the output signal OUT when the test enable signal TEN is enabled. More particularly, the second switch  28  may couple a normal output signal NOUT from the functional electronics  202  (such as a memory cell array) to the output pad during normal operations. Two pads (or pins) used by the first and second switches  26  and  28  during normal operations can also be used during the test operation. Accordingly, the test circuit need not include additional pads (or pins) to perform test operations.  
         [0033]     The PMOS transistor PM is turned on and transmits the external power supply voltage EVC to a node N 2  when the test enable signal TEN is disabled during normal operations, and is turned off when the test enable signal TEN is enabled during test operations. The latch LA and the inverter I 4  latch a signal of a node N 1  and generate the test output signal TOUT. Since the node N 1  is at a high level during the normal operations, the test output signal TOUT is generated at a low level.  
         [0034]     During test operations, the NAND gate NA 1  of the first delay circuit  30 - 1  inverts an external clock signal ECLK in response to the test control signal T 1  of a high level and generates a clock signal PCLK. Thus, the CMOS transmission gates C 1  and C 2  are turned on in response to the clock signal PCLK of a low level and turned off in response to the clock signal PCLK of a high level. During the normal operations, the NAND gate NA 1  generates the clock signal PCLK of a high level in response to the test control signal T 1  of a low level. Thus both the CMOS transmission gates C 1  and C 2  are turned off.  
         [0035]     The first delay unit DL 1  receives the test input signal TIN, delays the test input signal TIN, and generates a delayed test input signal DTIN when the CMOS transmission gate C 1  is turned on, and transmits the delayed test input signal DTIN to the node N 1  when the CMOS transmission gate C 2  is turned on. If a high-level period of the external clock signal ECLK is shorter than a delay time of the first delay unit DL 1 , however, the CMOS transmission gate C 2  will be turned off before the first delay unit DL 1  generates the delayed test input signal DTIN, and the delayed test input signal DTIN is not transmitted to the node N 1 . In other words, the delayed test input signal DTIN can be transmitted to the node N 1  if the high-level period of the external clock signal ECLK is longer than the delay time of the first delay unit DL 1 , whereas the delayed test input signal DTIN cannot be transmitted to the node N 1  if the high-level period of the external clock signal ECLK is shorter than the delay time of the first delay unit DL 1 . When the test operations are performed while reducing the high-level period of the external clock signal ECLK, a time interval of a high-level period of the external clock signal ECLK when a test output signal TOUT corresponding to the test input signal TIN is generated, and a next time interval of a high-level period of the external clock signal ECLK when the a test output signal TOUT remains unchanged may be used to determine a delay time of the first delay unit DL 1 . In the above-described method, the test control signals T 2  to Tn may be sequentially enabled so that the delay times of the second to n-th delay units DL 2  to DLn of the second to n-th delay circuits  30 - 2  to  30 -N are measured in the same manner as when the delay time of the first delay unit DL 1  of the first delay circuit  30 - 1  is measured as described above.  
         [0036]     In  FIG. 2 , if the test circuit includes additional pads (or pins) for an input signal IN and an output signal OUT, the first and second switches  26  and  28  may be omitted.  
         [0037]      FIG. 3A  is a circuit diagram of one example of a delay unit shown in  FIG. 2 , and  FIG. 3B  is a circuit diagram of another example of a delay unit shown in  FIG. 2 . The delay unit of  FIG. 3A  includes m cascade-connected inverters I 11  to I 1 m, and the delay unit of  FIG. 3B  includes m cascade-connected inverters I 11  to I 1 m, first resistors R 11  to Rm 1 , and second resistors R 12  to Rm 2 .  
         [0038]     Even if two delay units have the same circuit construction as shown in  FIG. 3A , if the delay units have different inventor gate oxide thicknesses, different delays may be provided. In  FIG. 3B , the first resistors R 11  to Rm 1  are connected between an external power supply voltage EVC and first power applying terminals of the inverters I 11  to I 1 m, respectively, and the second resistors R 12  to Rm 2  are connected to second power applying terminals of the inverters I 11  to I 1 m, respectively.  
         [0039]     In  FIG. 3A , when the designed delay time of each of the m inverters I 11  to I 1 m is td 1 , the delay unit should delay the test input signal TIN by m×td 1  to generate the delayed test input signal DTIN. In  FIG. 3B , when the designed delay time of each of the circuits (including the first resistors R 11  to Rm 1 , the second resistors R 12  to Rm 2 , and the inverters I 11  and I 1 m, respectively) is td 2 , the delay unit should delay the test input signal TIN by m×td 2  to generate the delayed test input signal DTIN.  
         [0040]      FIG. 4  is a timing diagram illustrating operations of testing the semiconductor device shown in  FIG. 2 , specifically, when the test control signal T 1  is enabled and the test control signals T 2  to Tn are disabled. Before the test control signal T 1  is enabled, the reset signal generator  24  of  FIG. 2  generates the test enable signal TEN at a low level. Thus, the node N 2  is raised to a high level, and the latch LA latches the high-level signal, and the inverter I 4  inverts the signal to provide the test output signal TOUT at a low level.  
         [0041]     When the test control signal T 1  is enabled, the reset signal generator  24  of  FIG. 2  generates the test enable signal TEN at a high level. Thus, the first switch  26  provides the input signal IN as the test input signal TIN, and the second switch  28  provides the test output signal TOUT as the output signal OUT. Also, the PMOS transistor PM is turned off. The test operation is thus enabled. In this state, the input signal IN and the external clock signal ECLK are sequentially applied at a high level, so that the test input signal TIN of a high level is generated. Then, when the CMOS transmission gate C 1  is turned on in response to the clock signal PCLK of a low level, the test input signal TIN of a high level is transmitted. As a result, the first delay unit DL 1  delays the test input signal TIN by a delay time “d” and generates the delayed test input signal DTIN of a high level. In this case, if the CMOS transmission gate C 2  remains turned on, the high-level delayed test input signal DTIN is transmitted to the node N 1 . Also, the latch LA and the inverter I 4  latch the high-level delayed test input signal DTIN and generate the test output signal TOUT of a high level and the second switch  28  generates the high-level test output signal TOUT as the output signal OUT.  
         [0042]     Thereafter, while moving a high-level period “t” of the external clock signal ECLK from a time point “a” to a time point “c” (namely, while moving up a time point at which the external clock signal ECLK makes a downward transition), the test operation is carried out. If the first delay unit DL 1  generates a test input signal DTIN that is delayed by the delay time “d” from the time point at which a clock signal PCLK makes the downward transition as shown in  FIG. 4 , the high-level test output signal TOUT is generated before the time point at which the external clock signal ECLK making the downward transition reaches the time point “c” and thus, the output signal OUT of a high level is generated through the second switch  28 . On the other hand, if the time point at which the external clock signal ECLK makes the downward transition moves from the time point “c” to a time point “b” to make a high-level period shorter, the test output signal TOUT of a low level is generated as shown with a dotted line and thus, the output signal OUT of a low level is generated through the second switch  28  as shown with a dotted line.  
         [0043]     Therefore, while lessening the high-level period of the external clock signal ECLK, the test apparatus calculates, as a delay time of the first delay unit  30 - 1 , the average of the high-level period of the external clock signal ECLK applied when the low-level output signal OUT is first generated and the high-level period of the external clock signal ECLK applied when the high-level output signal OUT is finally generated. Then, the test apparatus divides the calculated delay time by m so as to obtain the delay times of the respective inverters or elements of the first delay unit.  
         [0044]     In the above-described method, not only the delay times of the second to n-th delay units DL 2  to DLn but also the delay times of the respective inverters or elements can be measured.  
         [0045]     In embodiments discussed above, a high-level period of the external clock signal ECLK is initially longer than the designed delay time of the delay unit and the test operation is performed while lessening the high-level period of the external clock signal ECLK until an abnormal output signal OUT is generated. In an alternative, the high-level period of the external clock signal ECLK may be initially shorter than the designed delay time of the delay unit and the test operation may be performed while increasing the high-level period of the external clock signal ECLK until a normal output signal OUT is generated. In other words, when the test operation is performed while lessening the high-level period of the external clock signal ECLK, a time interval between a high-level period of the external clock signal ECLK in the case where the same test output signal TOUT as the test input signal TIN is finally generated and a high-level period of the external clock signal ECLK in the case where the same test output signal TOUT as the test input signal TIN is not first generated becomes the delay time of the first delay unit DL 1 .  
         [0046]     As discussed above, semiconductor devices and methods for testing the same according to embodiments of the present invention can measure delay times of elements in a wafer state and also in a package state.  
         [0047]     Further, devices and methods according to embodiments of the present invention can measure the delay times of respective elements in a more precise manner using an external clock signal.  
         [0048]     Embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.