Abstract:
A method and an apparatus are provided for loading data to a local store of a processor in a computer system having a direct memory access (DMA) mechanism. A transfer of data is performed from a system memory of the computer system to the local store. The data is fetched from the system memory to a cache of the processor. A DMA load request is issued to request data. It is determined whether the requested data is found in the cache. Upon a determination that the requested data is found in the cache, the requested data is loaded directly from the cache to the local store.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates generally to memory management and, more particularly, to fetching data to a cache in a direct memory access (DMA) mechanism.  
         [0003]     2. Description of the Related Art  
         [0004]     In a multiprocessor design, a DMA mechanism is used to move information from one type of memory to another. The DMA mechanism such as a DMA engine or DMA controller also moves information from a system memory to a local store of a processor. When a DMA command tries to move information from the system memory to the local store of the processor, there is going to be some delay in loading the information from the system memory to the local store of the processor.  
         [0005]     Therefore, a need exists for a system and method for fetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention provides a method and an apparatus for loading data to a local store of a processor in a computer system having a direct memory access (DMA) mechanism. A transfer of data is performed from a system memory of the computer system to the local store. The data is fetched from the system memory to a cache of the processor. A DMA load request is issued to request data. It is determined whether the requested data is found in the cache. Upon a determination that the requested data is found in the cache, the requested data is loaded directly from the cache to the local store. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:  
         [0008]      FIG. 1  shows a block diagram illustrating a single processor computer system adopting a cache along with a direct memory access (DMA) mechanism;  
         [0009]      FIG. 2  shows a block diagram illustrating a multiprocessor computer system adopting a cache along with a DMA mechanism; and  
         [0010]      FIG. 3  shows a flow diagram illustrating a caching mechanism applicable to a DMA mechanism as shown in  FIGS. 1 and 2 . 
     
    
     DETAILED DESCRIPTION  
       [0011]     In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail.  
         [0012]     It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor such as a computer or an electronic data processor in accordance with code such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.  
         [0013]     In the remainder of this description, a processing unit (PU) may be a sole processor of computations in a device. In such a situation, the PU is typically referred to as an MPU (main processing unit). The processing unit may also be one of many processing units that share the computational load according to some methodology or algorithm developed for a given computational device. For the remainder of this description, all references to processors shall use the term MPU whether the MPU is the sole computational element in the device or whether the MPU is sharing the computational element with other MPUs, unless indicated otherwise.  
         [0014]     Referring to  FIG. 1  of the drawings, the reference numeral  100  generally designates a single processor computer system adopting a cache in a direct memory access (DMA) mechanism. The single processor computer system  100  comprises a synergistic processor complex (SPC)  102 , which includes a synergistic processor unit (SPU)  104 , a local store  106 , and a memory flow controller (MFC)  108 . The single processor computer system also includes an SPU&#39;s L1 cache (SL1 cache)  109  and a system memory  110 . The SPC  102  is coupled to the SL1 cache  109  via a connection  112 . The SL1 cache  109  is coupled to the system memory  110  via a connection  114 . The MFC  108  functions as a DMA controller.  
         [0015]     Once the MFC  108  performs data transfers between the system memory  110  and the local store  106 , the transferred data is also fetched to the SL1 cache  109 . When the MFC  108  requests the same data later on, the MFC  108  does not have to go all the way back to the system memory  110  to retrieve the data. Instead, the MFC  108  accesses the SL1 cache  109  to retrieve the data and transfer the data to the local store  106 . Typically, the size of data being transferred should not exceed the size of the SL1 cache  109 .  
         [0016]     Preferably, the MFC  108  checks the SL1 cache  109  first for any data. If there is a hit, the MFC  108  transfers the data from the SL1 cache  109  to the local store  106 . If there is a miss, the MFC  108  transfers the data from the system memory  110  to the local store  106  as the MFC  108  would normally do.  
         [0017]      FIG. 2  is a block diagram illustrating a multiprocessor computer system  200  adopting a cache in a DMA mechanism. The multiprocessor computer system  200  has one or more synergistic processor complexes (SPCs)  202 . The SPC  202  has a synergistic processor unit (SPU)  204 , a local store  206 , and a memory flow controller (MFC)  208 . The multiprocessor computer system  200  further comprises an SPU&#39;s L1 cache (SL1 cache)  210  and a system memory  212 . The SL1 cache  210  is coupled between the SPC  202  and the system memory  212  via connections  216  and  218 . Note here that the single SL1 cache  210  is used to interface with all the SPCs  202 . In different implementations, however, a plurality of caches may be used. Additionally, the multiprocessor computer system  200  comprises a processing unit (PU)  220 , which includes an L1 cache  222 . The multiprocessor computer system  200  further comprises an L2 cache  224  coupled between the PU  220  and the system memory  212  via connections  226  and  228 .  
         [0018]     Once the MFC  208  performs data transfers between the system memory  212  and the local store  206 , the transferred data is also fetched to the SL1 cache  210 . When the MFC  208  requests the same data later on, the MFC  208  does not have to go all the way back to the system memory  212  to retrieve the data. Instead, the MFC  208  accesses the SL1 cache  210  to retrieve the data and transfer the data to the local store  206 . Typically, the size of data being transferred should not exceed the size of the SL1 cache  210 .  
         [0019]     Preferably, the MFC  208  checks the SL1 cache  210  first for any data. If there is a hit, the MFC  208  transfers the data from the SL1 cache  210  to the local store  206 . If there is a miss, the MFC  208  transfers the data from the system memory  212  to the local store  206  as the MFC  208  would normally do.  
         [0020]     Now referring to  FIG. 3 , shown is a flow diagram illustrating a caching mechanism  300  applicable to a DMA mechanism as shown in  FIGS. 1 and 2 .  
         [0021]     In step  302 , the DMA mechanism performs a data transfer from a system memory to a local store of a processor. In  FIG. 1 , for example, the MFC  108  performs a data transfer from the system memory  110  to the local store  106  for the SPC  102 . In  FIG. 2 , for example, the MFC  208  performs a data transfer from the system memory  212  to the local store  206  for the SPC  202 . In step  304 , the data is fetched from the system memory to the cache. In step  306 , a DMA load request is issued to request data from the system memory. In step  308 , it is determined whether the requested data is found in the cache. If the requested data is found in the cache in step  308  (i.e. a cache hit), the process goes to step  310 , where the requested data is loaded directly from the cache to the local store. If the requested data is not found in the cache in step  308  (i.e., a cache miss), the process continues to step  312 , where the requested data is loaded from the memory to the local store.  
         [0022]     Note that there may be many different ways to write data back to the system memory without departing from the true spirit of the present invention. For example, the data may be written back to the system memory (e.g., the system memory  110  of  FIG. 1 ) via the cache (e.g., the SL1 cache  109  of  FIG. 1 ). Alternatively, the data may be directly written back to the system memory without going through the cache. In the latter case, the cache entry for the data being written back to the system memory may be invalidated. These and other details on the process of writing data back to the system memory are not further disclosed herein.  
         [0023]     It will be understood from the foregoing description that various modifications and changes may be made in the preferred embodiment of the present invention without departing from its true spirit. This description is intended for purposes of illustration only and should not be construed in a limiting sense. The scope of this invention should be limited only by the language of the following claims.