Abstract:
A control circuit and method are proposed to generate a control signal to operate a buck-boost power stage of a buck-boost power converter to convert an input voltage to an output voltage. The control circuit and method detect the output voltage to generate an error signal, control the frequency of two ramp signals according to the error signal, generate two pulse width modulation signals according to the error signal and the two ramp signals, and generate the control signal according to the two pulse width modulation signals. When the loading of the buck-boost power converter transits from heavy to light, the frequency of the two ramp signals is decreased to improve the efficiency of the buck-boost power converter. The peaks and valleys of the two ramp signals may be adjusted by signals related to the input voltage and the output voltage.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention is related generally to a buck-boost power converter and, more particularly, to a control circuit and method for a buck-boost power converter. 
       BACKGROUND OF THE INVENTION 
       [0002]    A buck power converter is circuitry to operate a buck power stage  10  as shown in  FIG. 1  to step down an input voltage Vin to an output voltage Vo for a load Rload, and a boost power converter is circuitry to operate a boost power stage  12  as shown in  FIG. 2  to step up an input voltage Vin to an output voltage Vo for a load Rload. Unfortunately, a conventional buck power converter or boost power converter is inadequate to provide a stable voltage for a system, for example a portable device, that uses a battery as its power source Vin because a battery is unable to provide a stable voltage all the time during its lifetime. 
         [0003]    Since the voltage of a battery descends with exhaustion of its power, a system using a battery as its power source requires a power converter switchable between a buck mode and a boost mode. A buck-boost power converter is circuitry to operate a buck-boost power stage  14  as shown in  FIG. 3  to step down or step up an input voltage Vin to an output voltage Vo for a load Rload. However, such a buck-boost power converter produces a negative output voltage Vo and is thus unsuitable for some applications. Therefore, a buck-boost power stage  16  as shown in  FIG. 4  was proposed, by which a positive output voltage Vo is generated from an input voltage Vin. For operating the buck-boost power stage  16  shown in  FIG. 4 , there have been proposed many control circuits and methods, for example, U.S. Pat. Nos. 6,166,527 and 7,518,346. Nevertheless, these arts are still not sufficient for users&#39; demands. 
         [0004]    Therefore, it is desired a novel control circuit and method for a buck-boost power converter. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    An object of the present invention is to provide a control circuit and method for a buck-boost power converter. 
         [0006]    According to the present invention, a control circuit for a buck-boost power converter includes a feedback circuit to detect the output voltage of the buck-boost power converter to generate a feedback signal, an error amplifier to amplify the difference between the feedback signal and a reference voltage to generate an error signal, a waveform generator to provide two ramp signals, a frequency controller to generate an oscillation signal according to the error signal, a clock generator to generate a clock signal according to the oscillation signal for the waveform generator to control the frequencies of the two ramp signals, a PWM comparator to generate two PWM signals according to the error signal and the two ramp signals, a gate driver to generate a control signal according to the two PWM signals to operate a buck-boost power stage to convert an input voltage to the output voltage. 
         [0007]    According to the present invention, a control method for a buck-boost power converter detects the output voltage of the buck-boost power converter to generate a feedback signal, amplifies the difference between the feedback signal and a reference voltage to generate an error signal, generates an oscillation signal according to the error signal, generates two ramp signals according to the oscillation signal, generates two PWM signals according to the error signal and the two ramp signals, and generates a control signal according to the two PWM signals to operate a buck-boost power stage to convert an input voltage to the output voltage. 
         [0008]    The error signal is used to control the frequencies of the two ramp signals in such a way that the frequencies are decreased for light loading to reduce the switching loss of the buck-boost power stage and thereby improve the efficiency of the buck-boost power converter. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
           [0010]      FIG. 1  is a circuit diagram of a conventional buck power stage; 
           [0011]      FIG. 2  is a circuit diagram of a conventional boost power stage; 
           [0012]      FIG. 3  is a circuit diagram of a conventional buck-boost power stage; 
           [0013]      FIG. 4  is a circuit diagram of another conventional buck-boost power stage; 
           [0014]      FIG. 5  is a circuit diagram of an embodiment according to the present invention; 
           [0015]      FIG. 6  is a circuit diagram of a first embodiment for the waveform generator shown in  FIG. 5 ; 
           [0016]      FIG. 7  is a waveform diagram of the waveform generator shown in  FIG. 6  when using a constant frequency clock; 
           [0017]      FIG. 8  is a waveform diagram of the waveform generator shown in  FIG. 6  when using a variable frequency clock; 
           [0018]      FIG. 9  is a waveform diagram of a non-linear ramp signal; 
           [0019]      FIG. 10  is a waveform diagram of a non-linear ramp signal; 
           [0020]      FIG. 11  is a waveform diagram of a non-linear ramp signal; 
           [0021]      FIG. 12  is a circuit diagram of a second embodiment for the waveform generator shown in  FIG. 5 ; 
           [0022]      FIG. 13  is a circuit diagram of a first embodiment for the frequency controller shown in  FIG. 5 ; and 
           [0023]      FIG. 14  is a circuit diagram of a second embodiment for the frequency controller shown in  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]      FIG. 5  is a circuit diagram of an embodiment according to the present invention, in which a buck-boost power converter  18  includes a control circuit  20  to provide control signals S 1 , S 2 , S 3  and S 4  to drive power switches Q 1 , Q 2 , Q 3  and Q 4  of a buck-boost power stage  16 , respectively, to step down or step up an input voltage Vin to an output voltage Vo. In the control circuit  20 , a feedback circuit  22  detects the output voltage Vo to generate a feedback signal VFB related to the output voltage Vo, an error amplifier  24  amplifies the difference between the feedback signal VFB and a reference voltage Vref 1  to generate an error signal Vc, a waveform generator  26  provides ramp signals Vramp 1  and Vramp 2 , a PWM comparator  28  generates PWM signals PWM 1  and PWM 2  according to the error signal Vc and the ramp signals Vramp 1  and Vramp 2 , a gate driver  30  generates the control signals S 1 , S 2 , S 3  and S 4  according to the PWM signals PWM 1  and PWM 2 , a frequency controller  32  generates an oscillation signal Sf according to the error signal Vc, and a clock generator  34  generates a clock CLK according to the oscillation signal Sf for the waveform generator  26  to determine the frequencies of the ramp signals Vramp 1  and Vramp 2 . The frequency of the oscillation signal Sf is determined by the error signal Vc, and the frequency of the clock CLK varies with the frequency of the oscillation signal Sf, so that the frequencies of the ramp signals Vramp 1  and Vramp 2  are determined by the error signal Vc. 
         [0025]    The waveform generator  26  is established by voltage sources, resistors and capacitors, and by use of the input voltage Vin and the output voltage Vo, or other signals related to the input voltage Vin and the output voltage Vo instead, controls the peaks and valleys of the ramp signals Vramp 1  and Vramp 2 .  FIG. 6  is a circuit diagram of a first embodiment for the waveform generator  26 , in which a resistor R 1  and a switch Q 5  are connected in series between a variable voltage source Vref 2  and a capacitor C, a switch Q 6  is connected in parallel with the capacitor C, signals S 5  and S 6  control the switches Q 5  and Q 6 , respectively, to charge and discharge the capacitor C to generate the ramp signal Vramp 1 , a variable voltage source Vref 3  is connected between the capacitor C and a ground GND, a comparator  36  compares the ramp signal Vramp 1  with a voltage Vref 4  to generate a comparison signal Sc, an SR flip-flop  38  generates the signals S 5  and S 6  according to the clock CLK and the comparison signal S 5 , a shift circuit  40  level shifts the voltages Vref 2 , Vref 3  and Vref 4  according to the input voltage Vin and the output voltage Vo to adjust the peak and the valley of the ramp signal Vramp 1 . The SR flip-flop  38  may be substituted by a D-type flip-flop or other logic circuits for the same purpose. When the input voltage Vin is close to the output voltage Vo, the shift circuit  40  pulls high the voltages Vref 2  and Vref 4  or pulls low the voltage Vref 3  to increase the peak of the ramp signal Vramp 1  or to decrease the valley of the ramp signal Vramp 1 , thereby enabling the ramp signal Vramp 1  to determine, together with the error signal Vc, a proper duty for the PWM signal PWM 1  to improve the stability of the buck-boost power converter  18 . Alternatively, the shift circuit  40  may increase or decrease the peak and the valley of the ramp signal Vramp 1  simultaneously to shift the ramp signal Vramp 1  upward or downward, to improve the stability of the buck-boost power converter  18 . 
         [0026]    If the clock CLK has a constant frequency, the ramp signal Vramp 1  has a waveform as shown in  FIG. 7 . At time t 1 , the clock CLK triggers the output S 5  of the SR flip-flop  38  and thereby turns on the switch Q 5 , to charge the capacitor C by the voltage source Vref 2 , and as a result the ramp signal Vramp 1  begins increasing. When the ramp signal Vramp 1  increases to greater than the voltage Vref 4 , as shown at time t 2 , the output Sc of the comparator  36  resets the SR flip-flop  38  and thereby turns off the switch Q 5  and turns on the switch Q 6 , causing the capacitor C to discharge to the level of the voltage Vref 3 . In this embodiment, since the frequency of the clock CLK is fixed, the ramp signal Vramp 1  has a constant frequency. 
         [0027]    If the clock CLK has a variable frequency, the ramp signal Vramp 1  has a waveform as shown in  FIG. 8 . At time t 3 , the clock CLK triggers the SR flip-flop  38  and thereby turns on the switch Q 5 , to charge the capacitor C by the voltage source Vref 2 . When the ramp signal Vramp 1  increases to greater than the voltage Vref 4 , the comparator  36  resets the SR flip-flop  38  and thereby turns off the switch Q 5  and turns on the switch Q 6 , causing the capacitor C to discharge to the level of the voltage Vref 3 . In this embodiment, since the frequency of the clock CLK is variable, the ramp signal Vramp 1  has a variable frequency. 
         [0028]    As shown in  FIGS. 7 and 8 , the waveform generator  26  provides a non-linear ramp signal Vramp 1 , which enables the buck-boost power converter  18  with better voltage regulation and transient response for heavy loading, as compared with a linear ramp signal. In addition to the waveforms shown in  FIGS. 7 and 8 , the waveform generator  26  may provide a non-linear ramp signal Vramp 1  with other waveforms, for example, shown in  FIG. 9 ,  10  or  11 , by using different circuits and methods.  FIG. 12  is a circuit diagram of a second embodiment for the waveform generator  26  to provide the ramp signal Vramp 1  shown in  FIG. 10 , in which a resistor R 2  is additionally connected in series with the switch Q 6  as compared with the waveform generator  26  of  FIG. 6 . Due to the resistor R 2 , the ramp signal Vramp 1  decreases to the level of the voltage Vref 3  mildly when the capacitor C discharges, as shown in  FIG. 10 . 
         [0029]    The circuit for generating the ramp signal Vramp 2  is similar to that for generating the ramp signal Vramp 1  and needs not to be discussed repeatedly. As did the ramp signal Vramp 1 , the ramp signal Vramp 2  may have its frequency fixed or variable, and may have a non-linear waveform. 
         [0030]      FIG. 13  is a circuit diagram of a first embodiment for the frequency controller  32 , which includes a voltage-controlled oscillator (VCO)  42  to generate the oscillation signal Sf according to the error signal Vc, with the frequency thereof increasing or decreasing with raising or failing of the error signal Vc. At heavy load, the error signal Vc is greater and therefore the VCO  42  provides an oscillation signal Sf with a higher frequency. On the contrary, at light load the error signal Vc is smaller and therefore the VCO  42  provides an oscillation signal Sf with a lower frequency. Since the ramp signal Vramp 1  and Vramp 2  have lower frequencies at light load, the frequencies of the PWM signals PWM 1  and PWM 2  are consequently low, thereby reducing the switching loss of the buck-boost power stage  16  and in turn improving the efficiency of the buck-boost power converter  18 . 
         [0031]      FIG. 14  is a circuit diagram of a second embodiment for the frequency controller  32 . In addition to the VCO  42 , this frequency controller  32  further includes a switch SW 1  connected between the VCO  42  and the error amplifier  24 , and a comparator  44  to compare the error signal Vc with the voltage Vref 5  to generate a comparison signal Scomp to switch the switch SW 1  and a switch SW 2  connected between the VCO  42  and a constant voltage source Vref 6  by an inverter  46 . At heavy load, the error signal Vc is higher than the voltage Vref 5 , so the switch SW 1  is off while the switch SW 2  is on. In this case, the VCO  42  generates an oscillation signal Sf with a constant frequency according to the constant voltage Vref 6 . When transiting to light loading, the error signal Vc decreases, and once the error signal Vc becomes smaller than the voltage Vref 5 , the comparator  44  turns on the switch SW 1  and turns off the switch SW 2 , so that the VCO  42  generates an oscillation signal Sf with a variable frequency according to the error signal Vc. 
         [0032]    While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.