Abstract:
The present invention provides a technique for selective cancellation of the 2 nd -order or 3 rd -order nonlinearity of a transistor. Any nonlinearity is a function of the bias voltage of a transistor. In many cases, this function is such that, at a particular bias voltage, nonlinearity is zero. The invention provides a bias circuit that generates the optimum bias voltage for a transistor at which its selected nonlinearity is zero. Mathematically, the nonlinearity can be represented by a sum of multiple components where some components have negative sign. The components are proportional to the DC currents of the transistor at bias voltages differing by a small amount. The bias circuit includes bias transistors that are scaled versions of the main transistor. Each bias transistor generates a DC current representing one of the components. The currents are combined according to the signs of the respective components to form a DC signal proportional to the selected nonlinearity. A feedback circuit senses the DC signal and generates the bias voltages of the bias transistors that force the DC signal to be zero. One of the bias voltages is applied to the main transistor resulting in cancellation of its selected nonlinearity. The system may be readily implemented using the integrated circuit technology such that the transistors of the bias circuit are closely matched to each other and to the main transistor. The distortion cancellation effect provided by the present invention exhibits low sensitivity to variations in the transistor processing and operational temperature.

Description:
RELATED APPLICATIONS 
     This application claims priority from U.S. Provisional Application Ser. No. 60/284,791, filed Apr. 18, 2001, the content of which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention is related generally to transistor circuits and, more particularly, to a bias method and circuit for distortion reduction. 
     BACKGROUND OF THE INVENTION 
     Transistor amplifiers and mixers are commonly used building blocks of analog circuits operating at frequencies ranging from audio to radio frequencies (RF). Generally, these circuits are required to minimally distort the signal they operate on to preserve the information carried by the signal. 
     The signal distortion in active circuits is generated by nonlinearities of the transistor. Consider a simple common-source NMOS amplifier and its equivalent circuit shown in FIGS. 1A and 1B, respectively. In FIG. 1A, M 1  is an NMOS transistor, C is a direct current (DC) blocking capacitor, and R L  is a drain bias resistor. The equivalent circuit of FIG. 1B is an ideal model of the circuit of FIG.  1 A. In FIG. 1B, V GS  is the gate-source voltage and I D  is the drain current of M 1 . The drain current I D  is a function of V GS . For proper operation, the gate of the transistor M 1  should be biased above the threshold voltage to allow a nonzero DC drain current to flow through M 1 . The gate 
     A commonly used prior-art bias circuit is shown in FIG. 2 where a transistor M 2  is a scaled version (replica) of the transistor M 1  with the same gate length but a narrower width. Also shown in FIG. 2 is a reference current source, I REF , and a bias resistor, R B , that isolates the bias circuit from the amplifier input at the operating frequency of the amplifier. The drain of the transistor M 1  is biased in the saturation region for high gain. Ideally, the transistor M 1  operates as a linear voltage-controlled current source having the following characteristics: 
     
       
           I   D   =g   m ( V   GS   −V   TH )  (1) 
       
     
     where V TH  is the threshold voltage of the transistor M 1  and g m  is the bias-independent coefficient called transconductance in units amperes per volt (A/V). 
     For further analysis, it is convenient to separate the DC values of I D  and V GS  from their alternating current (AC) values using the following relations: 
     
       
         
           I 
           D 
           =I 
           D0 
           +i 
           D 
         
       
     
     
       
         
           V 
           GS 
           =V 
           GS0 
           +v 
           GS 
         
       
     
     
       
           I   D0   =g   m ( V   GS0   −V   TH ).  (2) 
       
     
     where I D0  is the DC drain current and V GS0  is the DC gate-source voltage of M 1  generated by the bias circuit. In equation (2) v GS  is the AC gate-source voltage equal to the input signal voltage (v IN ) and i D  is the AC drain current. Equation (1) can be written in terms of the introduced AC values as follows: 
     
       
           i   D   =g   m   v   GS   (3) 
       
     
     Where all terms have been previously defined. 
     When the AC input signal v IN  is applied to the circuit, the transistor M 1  generates an output AC current equal to g m v IN  that creates a voltage drop across the drain-bias resistor R L  equal to −g m v IN R L . This voltage across the drain-bias resistor R L  is the output signal of the amplifier and −g m R L  is its gain. 
     In the ideal amplifier illustrated in FIGS. 1A and 1B, the output signal is a scaled version of the input signal (i.e., there are no spurious responses of the system). The spectrum of the output signal has the same frequency components as the input signal. 
     Unfortunately, the transconductance of a real-life transistor is not a constant but a function of the input bias voltage. This function is often described by a sophisticated equation or a system of equations. To simplify circuit analysis, this function is replaced by its Taylor series expansion near V GS0  as follows: 
     
       
           g   m   =g   1   +g   2   v   GS   +g   3   v   GS   2 +  (4a) 
       
     
     where g 1 , g 2  and g 3  are the expansion coefficients equal to:                        g   1          (     V   GS     )       =            I   D              V   GS                         g   2          (     V   GS     )       =         1   2                 2          I   D              V   GS   2           =         1   2                    V   GS              (            I   D              V   GS         )       =       1   2                   g   1          (     V   GS     )                V   GS                               g   3          (     V   GS     )       =         1   6                 3          I   D              V   GS   3           =       1   3                   g   2          (     V   GS     )                V   GS                           (4b)                                
     Substituting this g m  expansion into equation (3) above, we get the following expression for the output current of a real-life NMOS transistor: 
       i   D   =g   1   v   GS   +g   2   v   GS   2   +g   3   v   GS   3 +  (5) 
     This expansion is often called a power series. The first term in the series is called a linear term and represents the desired function of the transistor (e.g., the transistor M 1 ). The second term is called the 2 nd -order nonlinearity. The third term is called the 3 rd -order nonlinearity, etc. The nonlinearities are not desirable since they generate spurious responses that interfere with the desired signal. 
     There are several well known techniques to reduce the circuit spurious responses relative to its desired fundamental response. These techniques are often referred to as the linearization techniques. The simplest and widely-used technique is based on the fact that the 2 nd  and 3 rd -order expansion coefficients of the FET output current, g 2  and g 3 , decrease relative to the linear transconductance g 1  at gate-to-source voltages much larger than the threshold voltage. So, selecting large-enough V GS0  results in much smaller spurious responses relative to the fundamental response of the circuit. Unfortunately, this technique increases the DC current consumption of the circuit which may not be acceptable for some applications (e.g., battery operated devices). 
     Another technique is based on the fact that, for many field-effect transistors, there are particular input bias voltages at which either the 2 nd  or the 3 rd -order expansion coefficient is zero. These bias voltages are typically close to the threshold voltage and, therefore, don&#39;t result in a large DC drain current. If a transistor is biased at such a voltage, theoretically it generates zero 2 nd  or 3 rd  order distortion. It is possible to calculate a bias voltage at which g 2  or g 3  is zero from the simulated or measured transfer characteristic of the transistor. The calculated bias voltage will only be optimum for either a typical transistor for which the model was extracted or the measured transistor-sample. It will also be optimum only at a specific temperature at which the transfer characteristic was simulated or measured. It possible to design a bias circuit that generates this calculated gate-to-source voltage at which g 2  or g 3  is zero using a resistive divider for example. However, it will not satisfactorily eliminate the corresponding distortion as the operating temperature changes or the parameters of the transistor manufacturing process drift. 
     Accordingly, it can be appreciated that there is a significant need for a bias circuit that eliminates undesirable distortion components independent of temperature fluctuations and manufacturing process drifts. The present invention provides this, and other advantages, as will be apparent from the following detailed description and the accompanying figures. 
     SUMMARY OF THE INVENTION 
     The present invention is embodied in a method and circuit for biasing a transistor. The transistor to be biased has a transfer characteristic that may be characterized by a linear or first-order term that describes a straight line and nonlinear or higher-order terms, such as 2 nd -order and 3 rd -order nonlinearities, that describe the deviations of the transfer characteristic from the straight line. The inventive method generates a direct current signal proportional to a selected nonlinearity of the transistor and uses the DC signal to generate the bias voltage of the transistor at which the selected nonlinearity is zero. 
     In one example, the selected nonlinearity is a 2 nd -order nonlinearity and the DC signal comprises first, second and third portions. The first, second and third portions are combined to form the DC signal. In another example, the selected nonlinearity is a 3 rd -order nonlinearity and the DC signal comprises first, second, third and fourth portions. The first, second, third and fourth portions are combined to form the DC signal. 
     The method may also include providing a mirror to bias circuit elements that generate the DC signal. A feedback circuit may also be provided to sense the DC signal and generate the bias voltage at which the DC signal and the selected nonlinearity are zero. The DC signal may be a current or a voltage, single-ended or differential. 
     The response of the transistor may be characterized by a power series having a linear term and nonlinear terms or nonlinearities. The nonlinearities each consist of multiple components. The bias circuit may comprise individual bias transistors designed to generate DC signal portions corresponding to the individual components of a selected nonlinearity. The DC signal portions are combined to form the DC signal proportional to the selected nonlinearity. A feedback circuit may be provided to sense the DC signal and generate the bias voltages of the bias transistors at which the DC signal and the selected nonlinearity are zero. For example, a 2 nd -order nonlinearity may be characterized by first, second and third components. The bias circuit may comprise first, second and third bias transistors that produce DC signal portions corresponding to the first, second and third components. The DC signal portions are combined to generate the DC signal proportional to the 2 nd -order nonlinearity. A feedback circuit senses the DC signal and generates the bias voltages of the bias transistors at which the DC signal is zero. One of these voltages is applied to the main transistor effectively canceling its 2 nd -order nonlinearity. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a conventional common-source transistor amplifier. 
     FIG. 1B is the equivalent circuit of the common-source amplifier of FIG.  1 A. 
     FIG. 2 is a conventional bias circuit used to bias the common-source transistor amplifier of FIG.  1 A. 
     FIGS. 3A-3D are a series of graphs illustrating the transfer characteristic of a typical transistor and its power series expansion coefficients as functions of the input bias voltage. 
     FIG. 4 is an exemplary embodiment of a bias circuit of the present invention designed to generate the input bias voltage at which the 2 nd -order nonlinearity is zero. 
     FIG. 5 is an alternative embodiment of a bias circuit of the present invention designed to generate the input bias voltage at which the 3 rd -order nonlinearity is zero. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention describes a method and bias circuit to selectively reduce the 2 nd -order or 3 rd -order nonlinearities of a transistor and the corresponding signal distortions. The techniques described herein operates satisfactorily in spite of process variations from one circuit to another and temperature fluctuations. 
     The principles of the present invention are based on the fact that, for many transistors, the 2 nd -order and 3 rd -order expansion coefficients of the output current (i.e., g 2  and g 3 ) depend on the input bias voltage. That is, the AC output current i D  of Equation (5) is a power series comprising 2 nd -order and 3 rd -order nonlinearities characterized by the 2 nd -order and 3 rd -order expansion coefficients, g 2  and g 3 , respectively. In turn, the value of the expansion coefficients g 2  and g 3  depend on the input bias voltage. This dependence is such that, at a particular input bias voltage, either g 2  or g 3  is zero. If the amplifier input is biased at this voltage, its 2 nd  or 3 rd -order nonlinearity will be cancelled and the signal will not exhibit the 2 nd  or 3 rd -order distortion. 
     As an example, consider the transistor circuit of FIG.  1 A and its equivalent circuit, illustrated in FIG.  1 B. As previously noted, the drain current I D  is a function of the gate-to-source voltage V GS . The transfer characteristic of a short-channel NMOS transistor is illustrated in FIG. 3A where the drain current I D  is plotted as a function of the gate-to-source voltage V GS . FIGS. 3B-3D are graphs of the expansion coefficients g 1 -g 3 , derived from Equation (4b). FIG. 3B illustrates the linear transconductance of the transistor M 1 . FIG. 3C illustrates the coefficient of the 2 nd -order nonlinearity. It should be noted that the expansion coefficient g 2  and the corresponding 2 nd -order distortion are zero at V GS =1.63V. FIG. 3D illustrates the coefficient of the 3 rd -order nonlinearity of the transistor M 1 . It should be noted that the expansion coefficient g 3  and the corresponding 3 rd -order distortion are zero at V GS =0.74V. 
     Using techniques known in the prior art, it is possible to use a conventional resistive divider to bias the transistor M 1  with a fixed DC voltage. For example FIG. 3D illustrates that a bias voltage of approximately 0.74 volts results in a value of 0 for the expansion coefficient g 3 . However, it should be appreciated that the characteristic curves of FIGS. 3A-3D represent a single NMOS transistor at a specific temperature. Temperature fluctuations and drifts in the manufacturing process of the transistor cause these characteristics to shift relative to the V GS  axis. The steep slope of the g 3  characteristic in FIG. 3D near the zero-crossing point illustrates that even minor shifts in this point will increase the 3 rd -order distortion significantly if the bias voltage remains fixed at 0.74 volts. Accordingly, fixed DC bias voltage circuits known in the art are inadequate to achieve a stable reduction or elimination of the 2 nd -order or 3 rd -order distortion. It is challenging to design a bias circuit that automatically generates and maintains the optimum bias voltage that cancels a selected nonlinearity under fluctuating temperature and drifting process conditions. The present invention addresses this challenge. 
     To generate and automatically maintain the optimum bias voltage resulting in zero 2 nd  or 3 rd -order distortion, a bias circuit should have a replica of the amplifying transistor such as the bias transistor M 2  in FIG.  2  and the means to produce a measurable electrical quantity such as a DC voltage or current proportional to g 2  or g 3  of the replica-transistor. It should also have a DC feedback that senses this quantity and automatically adjusts the bias voltage of both the amplifying transistor and its replica for g 2 =0 or g 3 =0. 
     The insight into how to generate the DC voltage or current proportional to g 2  or g 3  can be gained if equations (4b) are rewritten in terms of small deviations of the voltages and currents rather than the derivatives.                  g   1          (     V   GS     )       =         I     D        (       V   GS     +     Δ                     V   GS     /   2         )         -     I     D        (       V   GS     -     Δ                     V   GS     /   2         )             Δ                   V   GS                 (6a)                         g   2          (     V   GS     )       =         1   2          g     1        (       V   GS     +     Δ                     V   GS     /   2         )           -       g     1        (       V   GS     -     Δ                     V   GS     /   2         )           Δ                   V   GS                       =       1     2      Δ                   V   GS              [           I     D        (       V   GS     +     Δ                   V   GS         )         -     I     D        (     V   GS     )             Δ                   V   GS         -         I     D        (     V   GS     )         -     I     D        (       V   GS     -     Δ                   V   GS         )             Δ                   V   GS           ]                   =       1     2      Δ                   V   GS   2              {       I     D        (       V   GS     +     Δ                   V   GS         )         +     I     D        (       V   GS     -     Δ                   V   GS         )         -     2        I     D        (     V   GS     )             }                     (6b)                         g   3          (     V   GS     )       =         1   3          g     2        (       V   GS     +     Δ                     V   GS     /   2         )           -       g     2        (       V   GS     -     Δ                     V   GS     /   2         )           Δ                   V   GS                       =       1     3      Δ                   V   GS              [               I     D        (       V   GS     +     3      Δ                     V   GS     /   2         )         -     2        I     D        (       V   GS     +     Δ                     V   GS     /   2         )           +     I     D        (       V   GS     -     Δ                     V   GS     /   2         )             2      Δ                   V   GS   2                   -         I     D        (       V   GS     +     Δ                     V   GS     /   2         )         -     2        I     D        (       V   GS     -     Δ                     V   GS     /   2         )           +     I     D        (       V   GS     -     3      Δ                     V   GS     /   2         )             2      Δ                   V   GS   2                 ]                   =       1     6      Δ                   V   GS   3              {           [       I     D        (       V   GS     +     3      Δ                     V   GS     /   2         )         +     3        I     D        (       V   GS     -     Δ                     V   GS     /   2         )             ]               -     [       3        I     D        (       V   GS     +     Δ                     V   GS     /   2         )           +     I     D        (       V   GS     -     3      Δ                     V   GS     /   2         )           ]             }                     (6c)                                
     It should be noted that terms within the parentheses in equations (6a-6c) indicate operating parameters. For example, the term I D(V     GS     +ΔV     GS     )  in equation (6b) is intended to indicate the current I D  at the voltage V GS +ΔV GS . Similarly, the term I D(V     GS     +3ΔV     GS     /2)  in equation (6c) indicates the current I D  at a voltage V GS +3ΔV GS /2. The term ΔV GS  is a small deviation from V GS . The terms in the braces of equations (6b) and (6c) are measurable quantities that should be set to zero for g 2 =0 or g 3 =0 to cancel the 2 nd -order or 3 rd -order distortion, respectively. FIG. 4 illustrates one example of bias circuit that generates the term in the braces of (6b) and automatically adjusts V GS  to set this term to zero. 
     Transistors M 2   a , M 2   b  and M 2   c  are replicas of the transistor M 1  in FIG. 1 having the same gate length as M 1 , but their width is scaled down. The gates of the three replicas are biased through a resistor chain  2 R, 2 R with a current sink I 0 . The resistor unit value R and the current value I 0  are chosen such that the voltage drop I 0 R is equal to ΔV GS /2 in equations (6a)-(6c). The value of each resistor in FIG. 4 is selected  2 R so that the voltage drops are conveniently measured in terms of ΔV GS . 
     The circuit of FIG. 4 operates satisfactorily so long as the value for ΔV GS  is much smaller than the value for V GS  to make sure that V GS +ΔV GS  and V GS −ΔV GS  are close to V GS . For example, if I 0  were selected to have a value of 0.05 milliamps (mA) and  2 R were selected at 400 Ω, the value of ΔV GS =20 millivolts. The actual value for ΔV GS  is a design choice within the scope of the knowledge of the circuit designer using the principles described herein. Accordingly, the present invention is not limited by the specific current value I 0 , the resistor unit value R or the selected value for ΔV GS . 
     All three bias transistors (M 2   a , M 2   b  and M 2   c ) have the same W/L ratio. The transistors M 2   a  and M 2   c  are single transistor devices, while the transistor M 2   b  consists of two parallel devices, each of which is the same size as the transistors M 2   a  and M 2   c . This is indicated in the circuit of FIG. 4 by the designation m=2 associated with the transistor M 2   b  where m is the multiplicity factor. 
     The transistor M 2   a  generates the current represented by the first summand shown in the braces of equation (6b). That is, the transistor M 2   a  generates a current having the value equal to I D(V     GS     +ΔV     GS     ) . In contrast, the transistor M 2   c  generates the current represented by the second summand shown in the braces of Equation (6b). That is, the transistor M 2   c  generates a current having the value equal to I D(V     GS     −ΔV     GS     ) . Finally, the transistor M 2   b  generates the current represented by the third summand shown in the braces of the Equation (6b). That is, the transistor M 2   b  generates a current equal to 2I D(VGS) . 
     The currents of the transistors M 2   a  and M 2   c  are added by connecting their drains together. The common drain of the transistors M 2   a  and M 2   c  and the drain of M 2   b  are biased through a current mirror comprising a pair of transistors M 3   a  and M 3   b  where M 3   a  and M 3   b  are PMOS transistors of an equal size. The differential DC voltage between the drains of the transistors M 3   a  and M 3   b  is the DC signal proportional to the mathematical term in the braces of the Equation (6b) and, thus, to the 2 nd -order expansion coefficient g 2 . If the differential voltage is zero, the combined current of the transistors M 2   a  and M 2   c  is equal to the current of the transistor M 2   b , and the term in the braces of the Equation (6b) is zero. The transistor M 3   b  is a current mirror that produces the same current as the transistor M 3   a  provided that its drain voltage is the same as that of M 3   a.    
     This balance of the currents is ensured by an operational amplifier OA 1  in FIG. 4 that senses the differential DC voltage between the drains of the transistors M 3   a  and M 3   b  and generates the input voltage for the resistor chain  2 R,  2 R thus creating a feedback loop. The function of the operational amplifier OA 1  is readily understood by a circuit designer following the example circuit of FIG.  4 . Briefly, the operational amplifier OA 1  amplifies the differential input voltage with a high gain and feeds the amplified voltage to the gates of the transistors M 2   a , M 2   b  and M 2   c  with a polarity such that the operating point of these transistors is adjusted until their drain voltages are equal. 
     The gate and drain of the transistor M 3   a  are coupled together. The positive input of the operational amplifier OA 1  is coupled to the junction of the drains of the transistors M 3   b  and M 2   b . If, by way of example, the drain voltage of the transistor M 3   b  increases, the output of the operational amplifier OA 1  provides an increased signal directly to the gate of the transistor M 2   a  and to the gates of the transistors M 2   b  and M 2   c  via the resistor network  2 R,  2 R. The increased gate voltage of the transistor M 2   b  causes a decrease in its drain voltage thus bringing the drain voltage of the transistor M 3   b  into equilibrium with its gate voltage which is also the voltage on the gate and drain of the transistor M 3   a . Therefore, the drain currents of the transistors M 3   a  and M 3   b  are maintained equal. 
     Thus, the voltage V GS  in FIG. 4 is the desired bias voltage that will eliminate the contribution of the 2 nd -order nonlinearity (i.e., g 2 =0). The bias voltage is provided to the gate of the transistor M 1  (see FIG. 1 a ) through a transistor R b , which serves to isolate the bias circuit from the transistor M 1  at the operating frequency. In an exemplary embodiment, the isolation transistor R b  may have a value of approximately 10 kΩ. The feedback loop in FIG. 4 automatically maintains V GS  supplied to the gate of M 1  in FIG. 1 a  at the level that causes its 2 nd -order nonlinearity to be zero even in the presence of process and temperature variations. 
     The circuit of FIG. 4 selectively generates currents proportional to the components of the 2 nd -order nonlinearity that are used to generate the bias voltage to effectively cancel out the 2 nd -order nonlinearity. A similar approach may be used to cancel out the 3 rd -order nonlinearity. FIG. 5 illustrates an exemplary embodiment of a circuit that effectively cancels out the mathematical term in the braces of equation (6c) thus setting the value of the expansion coefficient g 3  equal to zero. 
     Although the circuit of FIG. 5 operates in a similar fashion to that of FIG. 4, some additional explanation may assist in a further understanding of the operation. An analysis of equation (6c) indicates that there are four summands contained within the braces. Each of the transistors M 2   a , M 2   b , M 2   c  and M 2   d  in FIG. 5 generates a DC current represented by a respective summand in the braces of equation (6c). The transistors M 2   a , M 2   b , M 2   c  and M 2   d  are replicas of the transistor M 1  in FIG. 1 having the same gate length as M 1 , but their width is scaled down. The gates of the four replicas are biased through the resistor chain  2 R,R,R, 2 R with the current sink I 0 . 
     The voltage drop produced by passing the current I 0  through the resistance R is equivalent to ΔV GS /2 in equations (6a)-(6c). This voltage drop is chosen relatively small so that V GS +3ΔV GS /2 and V GS −3ΔV GS /2 are close to V GS . As previously discussed, the only requirement is that ΔV GS  be much smaller than V GS . Similarly, the values for the resistors R and  2 R may be selected as a matter of engineering choice to have convenient resistor values. The value of the current sink I 0  is also chosen as a matter of design choice based on the description provided herein. For example, if the circuit of the present invention is intended for use in a battery operated circuit, it is desirable to minimize the current draw in the current sink I 0  and power consumption within the resistors R and  2 R for the selected ΔV GS . In contrast, a circuit having an external power supply has no such limitations. Accordingly, the present invention is not limited by the specific values selected for the resistors R and  2 R or the value of the current through the current sink I 0 . 
     All four transistors have the same W/L ratio. However, the transistors M 2   a  and M 2   d  are single transistor devices while the transistors M 2   b  and M 2   c  each consist of three parallel devices of the same size as the transistors M 2   a  and M 2   d . This is indicated in the circuit of FIG. 5 by the designation m=3 associated with the transistors M 2   b  and M 2   c.    
     The transistor M 2   a  generates the current represented by the first summand shown in the braces of equation (6c). That is, the transistor M 2   a  generates a current equal to I D(V     gs     +3ΔV     gs     /2) . The transistor M 2   b  generates the third current shown in the braces of equation (6c). That is, the transistor M 2   b generates the current equal to 3I D(V     gs     +ΔV     gs     /2) . The transistor M 2   c  generates the second current shown in the braces of equation (6c). That is, the transistor M 2   c  generates a current equal to 3I D(V     gs     −ΔV     gs     /2) . Finally, the transistor M 2   d  generates the fourth current shown in the braces of equation (6c). That is, the transistor M 2   d  generates current equal to I D(V     gs     −3ΔV     gs     /2) . 
     The currents of the transistors M 2   a  and M 2   c  are added by connecting their drains together. The currents of the transistors M 2   b  and M 2   d  are added in the same way. 
     The common drains of the transistors M 2   a ,M 2   c  and the transistors M 2   b ,M 2   d  are biased through a current mirror comprising transistors M 3   a  and M 3   b  where the transistors M 3   a  and M 3   b  are PMOS transistors of an equal size. The differential DC voltage between the drains of M 3   a  and M 3   b  is the DC signal proportional to the mathematical term in the braces of the Equation (6c) and, thus, to the 3 rd -order expansion coefficient g 3 . If the differential voltage is zero, the added currents through the transistors M 2   a ,M 2   c  and M 2   b ,M 2   d  are equal, and the term in the braces of equation (6c) is zero. 
     This balance of the currents is ensured by the operational amplifier OA 1  in FIG. 5, which operates in a manner similar to that of the operational amplifier OA 1  in FIG.  4 . Specifically, the operational amplifier OA 1  in FIG. 5 senses the differential DC voltage between the drains of the transistors M 3   a  and M 3   b  and generates the input voltage for the resistor chain  2 R,R,R, 2 R creating a feedback loop. This feedback loop automatically maintains V GS  supplied to the gate of M 1  in FIG. 1 a  at the level that causes its 3 rd -order nonlinearity to be zero even in the presence of process and temperature variations. 
     Thus, the present invention permits a simple approach that achieves a significant reduction in either the 2 nd -order or 3 rd -order nonlinearity and exhibits low sensitivity to variations in the processes used to manufacture transistors and temperature variations. Although the exemplary bias circuits of FIG.  4  and FIG. 5 do add additional circuitry, the DC current increase required to operate the bias circuits of the present invention is negligible. This is a significant advantage in battery operated applications. Furthermore, the bias circuits of the present invention do not degrade other circuit performance, such as the noise figure of the transistor M 1  (see FIG.  1 A). Furthermore, the DC bias circuits of the present invention may be used for transistors (e.g., the transistor M 1  of FIG. 1A) operating at virtually any frequency. 
     The described bias circuits are possible embodiments of the invention. There are other bias circuit topologies that can generate the optimum bias voltages based on zeroing a DC voltage or current proportional to the 2 nd  or 3 rd -order expansion coefficient. The invention can be used in MOSFET, MESFET, HEMT, BJT and HBT gain stages operating at any frequency. 
     It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the appended claims.