Abstract:
A package device ( 10, 100 ) has one integrated circuit ( 22, 122 ) in a cavity ( 20, 120 ) in a package substrate ( 12, 122 ) and electrically coupled to one side ( 50, 150 ) of the package substrate. A second integrated circuit ( 32, 132 ) is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit ( 38, 138 ) or more may be mounted on the second integrated circuit. Pads ( 16, 116, 116 ) useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.

Description:
FIELD OF THE INVENTION 
     The invention relates generally to a semiconductor package device and more particularly to a method of forming and testing a semiconductor package device. 
     BACKGROUND 
     In packaging integrated circuits, it has become more necessary to provide packages which allow for multiple die within the package. Testing such multiple die packages has become more difficult as the complexity of the die has increased. Also, for some multi-chip packages, it is important to electrically shield one or more of the die in the multi-chip package from one or more remaining die in the multi-chip package. It is also desirable to allow rework to be performed during the manufacturing process of forming a multi-chip package. It is also desirable to have a lower profile multi-chip package due to the limitations of the current circuit board technology. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which: 
         FIGS. 1-12  include illustrations of sequential cross-sectional views of a package device formed in accordance with a one embodiment of the present invention; and 
         FIGS. 13-23  include illustrations of sequential cross-sectional views of a package device formed in accordance with an alternate embodiment of the present invention. 
     
    
    
     Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. 
     DETAILED DESCRIPTION 
     The stacking of a plurality of die using a cavity in a substrate to receive at least one of the plurality of die allows a lower profile package device to be used. In addition, pads used for testing purposes may be located on more than one side of the package device. Also, layers between a plurality of die may be used to provide electrical shielding between selected die. The invention is better understood by turning to the figures. 
       FIG. 1  illustrates a package device  10  having a cavity  20  in accordance with one embodiment of the present invention. Package device  10  includes a package substrate  12  having a surface  50  and a surface  52 . Note that surface  50  constitutes a first plane and that surface  52  constitutes a second plane. At the top, substrate  12  includes one or more bond fingers  14  and one or more pads  16 . In one embodiment of the present invention, pads  16  are conductive and may be used for a variety of purposes. For example, pads  16  may be used to mount discrete devices, may be used to receive test probes for testing purposes, or may be used to receive conductive interconnects (e.g. solder balls).  FIG. 1  illustrates a tape layer  18  which is applied to surface  52  of substrate  12 . In one embodiment of the present invention, substrate  12  contains electrical conductors such as traces and vias which may be used to interconnect one or more die to external contacts (not shown). 
       FIG. 2  illustrates one embodiment of package device  10  wherein a die attach material  24  has been placed overlying tape  18 . A die  22  is then placed on top of die attach material  24 . Alternate embodiments of the present invention may not use die attach material  24 , but may instead directly attach die  22  to tape  18 . Tape  18  is used as a supporting member to support die  22 , and optionally die attach material  24 . Tape  18  may or may not extend over the entire surface  52  of substrate  12 . 
       FIG. 3  illustrates one embodiment of package device  10  in which die  22  has been electrically connected to bond fingers  14  by way of wire bonds  26 . Alternate embodiments of the present invention may use any number of wire bonds  26  and bond fingers  14 . 
       FIG. 4  illustrates one embodiment of package device  10  in which an encapsulating material  28  has been deposited over die  22 , wire bonds  26 , and bond fingers  14 . Note that encapsulating material  28  may be any type of appropriate material for integrated circuits, such as, for example, a molded plastic or a liquid deposited glob material. 
       FIG. 5  illustrates one embodiment of package device  10  in which tape  18  has been removed from the bottom surface  52  of substrate  12 . 
       FIG. 6  illustrates one embodiment of package device  10  in which die attach material  30  is placed to attach die  32  to package device  10 . In one embodiment, die attach material  30  is placed between die attach material  24  and die  32 . In an alternate embodiment, when die attach material  24  is not used, die attach material  30  is placed between die  22  and die  32 . Note that in one embodiment of the present invention, package device  10  may be flipped at this point in processing so that the bottom surface  52  now becomes the top surface  52  and the top surface  50  now becomes the bottom surface  50 . However, alternate embodiments of the present invention may orient package device  10  in any manner during its formation. For simplicity purposes, package device  10  will be shown in the same orientation throughout the remainder of the figures. 
       FIG. 7  illustrates one embodiment of package device  10  in which die  32  has been electrically connected to bond fingers  14  by way of wire bonds  34 . Alternate embodiments of the present invention may use any number of wire bonds  34  and bond fingers  14 . For embodiments of the present invention using flip chip technology, die  32  may have no wire bonds  34 , but may instead be electrically connected by way of surface  52 . 
       FIG. 8  illustrates one embodiment of package device  10  in which die attach material  36  is placed to attach die  38  to die  32 . In one embodiment, die attach material  36  is placed between die  32  and die  38 . In an alternate embodiment which uses flip chip technology, no die attach  36  is used; instead die  38  is directly electrically connected to die  32  using known flip chip techniques. 
       FIG. 9  illustrates one embodiment of package device  10  in which die  38  has been electrically connected to bond fingers  14  by way of wire bonds  42 , and die  38  has been electrically connected to die  32  by way of wire bond  40 . Alternate embodiments of the present invention may use any number of wire bonds  40  and  42 , and any number of bond fingers  14 . For embodiments of the present invention using flip chip technology, die  38  may have no wire bonds  42 , but may instead be directly electrically connected to die  32 . 
       FIG. 10  illustrates one embodiment of package device  10  where test probes  44  are illustrated to show one manner in which one or more of die  22 ,  32 , and  38  may be electrically tested. Note that in alternate embodiments of the present invention, test probes  44  may use one or more pads  16  located on just the top surface  50  of substrate  12 , just the bottom surface  52  of substrate  12 , or alternately on both the top and bottom surfaces  50 ,  52  of substrate  12 . Note that in some embodiments of the present invention, there may be a significant advantage to allowing test probes  44  to access both the top surface  50  and bottom surface  52  of substrate  12 . For example, this may allow more pads  16  to be accessed by test probes  44 , and thus allow more signals to be use during the testing process. Also, allowing test probes  44  access to both the top and bottom surfaces  50 ,  52  of substrate  12  may allow easier access to each individual die  22 ,  32 , and  38 . Note that when multiple die are used within a package, the number of pads  16  required for test may be significantly higher. 
       FIG. 11  illustrates one embodiment of package device  10  wherein an encapsulation material  46  has been deposited overlying die  38 , die  32 , and bond fingers  14 . Note that in alternate embodiments of the present invention, encapsulating material  46  may be deposited over a larger portion of substrate  12 . For example, in some embodiments of the present invention, encapsulating material  46  may be deposited overlying pads  16  as well. Regardless of whether pads  16  are encapsulated by encapsulating material  46 , pads  16  may be used to electrically couple discrete devices to one or more of die  22 ,  32 , and  38 . Note that encapsulating material  46  may be any type of appropriate material for integrated circuits, such as, for example, a molded plastic or a liquid deposited glob material. 
       FIG. 12  illustrates one embodiment of package device  10  in which conductive interconnects  48  have been placed overlying pads  16  at surface  50 . In one embodiment of the present invention conductive interconnects  48  may be solder balls. However, in alternative embodiments of the present invention, conductive interconnect  48  may be any type of electrically conductive material formed in any manner. Note that conductive interconnects  48  are optional. In some embodiments of the present invention, if encapsulating material  28  is flush with the top surface  50  of substrate  12 , then conductive interconnects  48  may not be required and electrical connections can be made directly to pads  16  on surface  50  of substrate  12 . Note again that traces and vias (not shown) within substrate  12  are used to selectively interconnect various portions of substrate  12 . Note also that die attach materials  24 ,  30 , and  36  may be any type of appropriate material, such as, for example, adhesive tape or non-solid adhesive (e.g. glue, epoxy). Die  22 ,  32 , and  38  may be any type of integrated circuit, semiconductor device, or other type of electrically active substrate. Alternate embodiments of the present invention may have any number of die  22 ,  32 , or  38  packaged within package device  10 . For example, alternate embodiments may package only two die in package device  10 . Note that the size and aspect ratios of die  22 ,  32 , and may vary, and that die spacers (not shown) may be used between die. Note that die  22  is located within cavity  20  and that die  32  and die  38  are located outside of cavity  20 . 
       FIG. 13  illustrates a package device  100  having a cavity  120  in accordance with one embodiment of the present invention. Package device  100  includes a package substrate  112  having a surface  150  and a surface  152 . Note that surface  150  constitutes a first plane and that surface  152  constitutes a second plane. At the top, substrate  112  includes one or more bond fingers  114  and one or more pads  116 . In one embodiment of the present invention, pads  116  are conductive and may be used for a variety of purposes. For example, pads  116  may be used to mount discrete devices, may be used to receive test probes for testing purposes, or may be used to receive conductive interconnects (e.g. solder balls).  FIG. 13  illustrates a layer  101  which is part of substrate  112  with its outer surface being surface  152 . In one embodiment of the present invention, layer  101  includes supporting member  119 , one or more bond fingers  114 , and one or more pads  116 . Alternate embodiments of the present invention may not require bond fingers  114  (e.g. when flip chip technology is used) and may not require pads  116  when an electrical connection to surface  152  is not desired. In one embodiment of the present invention, substrate  112  contains electrical conductors such as traces and vias which may be used to interconnect one or more die to external contacts (not shown). 
       FIG. 14  illustrates one embodiment of package device  100  wherein a die attach material  124  has been placed overlying supporting member  119 . A die  122  is then placed on top of die attach material  124 . 
       FIG. 15  illustrates one embodiment of package device  100  in which die  122  has been electrically connected to bond fingers  114  by way of wire bonds  126 . Alternate embodiments of the present invention may use any number of wire bonds  126  and bond fingers  114 . For embodiments of the present invention using flip chip technology, die  122  may have no wire bonds  126 , but may instead be electrically connected by way of layer  101 . 
       FIG. 16  illustrates one embodiment of package device  100  in which an encapsulating material  128  has been deposited over die  122 , wire bonds  126 , and bond fingers  114 . Note that encapsulating material  128  may be any type of appropriate material for integrated circuits, such as, for example, a molded plastic or a liquid deposited glob material. 
       FIG. 17  illustrates one embodiment of package device  100  in which die attach material  130  is placed to attach die  132  to package device  100 . In one embodiment, die attach material  130  is placed between layer  101  and die  132 . Note that in one embodiment of the present invention, package device  100  may be flipped at this point in processing so that the bottom surface  152  now becomes the top surface  152  and the top surface  150  now becomes the bottom surface  150 . However, alternate embodiments of the present invention may orient package device  100  in any manner during its formation. For simplicity purposes, package device  100  will be shown in the same orientation throughout the remainder of the figures. 
       FIG. 18  illustrates one embodiment of package device  100  in which die  132  has been electrically connected to bond fingers  114  by way of wire bonds  134 . Alternate embodiments of the present invention may use any number of wire bonds  134  and bond fingers  114 . For embodiments of the present invention using flip chip technology, die  132  may have no wire bonds  134 , but may instead be electrically connected by way of surface  152 . 
       FIG. 19  illustrates one embodiment of package device  100  in which die attach material  136  is placed to attach die  138  to die  132 . In one embodiment, die attach material  136  is placed between die  132  and die  138 . In an alternate embodiment which uses flip chip technology, no die attach  136  is used; instead die  138  is directly electrically connected to die  132  using known flip chip techniques. 
       FIG. 20  illustrates one embodiment of package device  100  in which die  138  has been electrically connected to bond fingers  114  by way of wire bonds  142 , and die  138  has been electrically connected to die  132  by way of wire bond  140 . Alternate embodiments of the present invention may use any number of wire bonds  140  and  142 , and any number of bond fingers  114 . For embodiments of the present invention using flip chip technology, die  138  may have no wire bonds  142 , but may instead be directly electrically connected to die  132 . 
       FIG. 21  illustrates one embodiment of package device  100  where test probes  144  are illustrated to show one manner in which one or more of die  122 ,  132 , and  138  may be electrically tested. Note that in alternate embodiments of the present invention, test probes  144  may use one or more pads  116  located on just the top surface  150  of substrate  112 , just the bottom surface  152  of substrate  112 , or alternately on both the top and bottom surfaces  150 ,  152  of substrate  112 . Note that in some embodiments of the present invention, there may be a significant advantage to allowing test probes  144  to access both the top surface  150  and bottom surface  152  of substrate  112 . For example, this may allow more pads  116  to be accessed by test probes  144 , and thus allow more signals to be use during the testing process. Also, allowing test probes  144  access to both the top and bottom surfaces  150 ,  152  of substrate  112  may allow easier access to each individual die  122 ,  132 , and  138 . Note that when multiple die are used within a package, the number of pads  116  required for test may be significantly higher. 
       FIG. 22  illustrates one embodiment of package device  100  wherein an encapsulation material  146  has been deposited overlying die  138 , die  132 , and bond fingers  114 . Note that in alternate embodiments of the present invention, encapsulating material  146  may be deposited over a larger portion of substrate  112 . For example, in some embodiments of the present invention, encapsulating material  146  may be deposited overlying pads  116  as well. Regardless of whether pads  116  are encapsulated by encapsulating material  146 , pads  116  may be used to electrically couple discrete devices to one or more of die  122 ,  132 , and  138 . Note that encapsulating material  146  may be any type of appropriate material for integrated circuits, such as, for example, a molded plastic or a liquid deposited glob material. 
       FIG. 23  illustrates one embodiment of package device  100  in which conductive interconnects  148  have been placed overlying pads  116  at surface  150 . In one embodiment of the present invention conductive interconnects  148  may be solder balls. However, in alternative embodiments of the present invention, conductive interconnect  148  may be any type of electrically conductive material formed in any manner. Note that conductive interconnects  148  are optional. In some embodiments of the present invention, if encapsulating material  128  is flush with the top surface  150  of substrate  112 , then conductive interconnects  148  may not be required and electrical connections can be made directly to pads  116  on surface  150  of substrate  112 . Note again that traces and vias (not shown) within substrate  112  are used to selectively interconnect various portions of substrate  112 . Note also that die attach materials  124 ,  130 , and  136  may be any type of appropriate material, such as, for example, adhesive tape or non-solid adhesive (e.g. glue, epoxy). Die  122 ,  132 , and  138  may be any type of integrated circuit, semiconductor device, or other type of electrically active substrate. Alternate embodiments of the present invention may have any number of die  122 ,  132 , or  138  packaged within package device  100 . For example, alternate embodiments may package only two die in package device  100 . Note that the size and aspect ratios of die  122 ,  132 , and  138  may vary, and that die spacers (not shown) may be used between die. Note that die  122  is located within cavity  120  and that die  132  and die  138  are located outside of cavity  120 . 
     In the foregoing specification the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, any appropriate die attach processes, wire bond processes, and tape processes may be used in the formation of package devices  10  and  100 , of which there are many known in the art. Accordingly, the specification and figures are the be regarded in an illustrative rather than restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Benefits, other advantages, and solutions to problems have been described with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any of the claims.