Abstract:
The present invention relates to a structure of a diplexer that prevents outputs of both signals from influencing each other by removing mutual interference between both signals when a signal having a high pulse frequency and a signal having a low pulse frequency are combined and radiated by using the same antenna, and more particularly, to a 2-channel diplexer structure with two channels in which a substrate having a predetermined size is configured, five microstrip lines are arranged on the top of the substrate to be parallel to each other with a predetermined interval.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims under 35 U.S.C. §119 (a) the benefit of Korean Patent Application No. filed the entire contents of which are incorporated herein by reference. 
       BACKGROUND 
       [0002]    (a) Technical Field 
         [0003]    The present invention relates to a structure of a diplexer that prevents outputs of both signals from influencing each other by removing mutual interference between both signals when a signal having a high pulse frequency and a signal having a low pulse frequency are combined and radiated by using the same antenna, and more particularly, to a 2-channel diplexer structure with two channels in which a substrate having a predetermined size is configured, five microstrip lines are arranged on the top of the substrate to be parallel to each other with a predetermined interval wherein a front end of a first microstrip line and a front end of a third microstrip line are connected through a first connection line and a rear end of the third microstrip line and a rear end of a fifth microstrip line are connected through a second connection line to configure one microstrip line of           shape; a second microstrip line as an individual line is configured between the first microstrip line and the third microstrip line by the first connection line opened to a rear side by the first connection line; a fourth microstrip line as an individual line is configured between the third microstrip line and the fifth microstrip line opened to a front side by the second connection line, including a first port connected with the first connection line; a third port connected to a rear end of the second microstrip line; a fourth port connected with the second connection line; and a third port connected to a front end of the fourth microstrip line. 
         [0004]    (b) Background Art 
         [0005]    In general, a diplexer uses an LPF and an HPF instead of a BPF unlike a duplexer. 
         [0006]    For example, as the diplexer used in the related art, four types (band splitters, wide bandpass diplexer &amp; triplexers, a narrow bandpass diplexer, and a quadrature diplexer) are primarily used. 
         [0007]    At present, the diplexer used in a dual-band (tri-mode) communication terminal is almost implemented by a chip. 
         [0008]    In this case, as a frequency band used in the diplexer, a frequency band (hereinafter, referred to as cellular) of 824 to 894 MHz (AMPS) and a frequency band of 1850 to 1990 MHz (PCS) are used. The frequency band used in the diplexer serves to separate the duplexer into a cellular duplexer and a PCS duplexer and separate the duplexer into a duplexer for an intermediate-frequency mixer. 
         [0009]    Herein, the duplexer is a primary component of a mobile communication terminal that serves to pass only a signal required in calling in connection with an antenna and remove a signal and noise which are unnecessary. 
         [0010]    The diplexer in the related art serves to separate the frequencies of 824 to 894 MHz (AMPS) and a frequency band of 1850 to 1990 MHz (PCS) into the cellular duplexer and the PC duplexer in a high-frequency signal received through the antenna (Ant). 
         [0011]    The diplexer is most configured by the chip and in terms of a characteristic thereof, insertion loss of a bandpass frequency is maximum 0.7 dB (0.4 dB typ), and isolation is minimum 15 dB. 
         [0012]    For reference, the insertion loss (IL) as a result caused by inserting a transducer into a transmission system indicates a ratio of power P 2  given to a predetermined place next to a transducer and power P 1  given at the same place when the transducer is removed as a decibel (dB). 
         [0013]    The isolation represents a power transfer amount from one antenna to another antenna and interantenna isolation indicates a ratio of reception power of another antenna to input power into one antenna as the decibel and a reception power ratio at the Rx side from Tx in RF is also one concept of the isolation. 
         [0014]    The insertion loss of the PCS (0.4 dB Typ) and cellular (0.3 dB Typ) band frequencies is designed as approximately 0.7 dB Max (0.4 DB Typ). 
         [0015]    Therefore, the diplexer implemented by one chip has a problem that since performance is implemented in the chip while an inputted frequency is separated into a dual band by an internal selection terminal, a coupling phenomenon and higher isolation which are caused therefrom can not obtained. 
         [0016]    Since there is a high possibility that the chip will be damaged by heat generated from the chip is high, durability is weak. 
         [0017]    In the related art, the diplexer uses a concentrated constant circuit and thus it is impossible to downsize the diplexer. 
       SUMMARY OF THE DISCLOSURE 
       [0018]    The present invention has been made in an effort to solve the above-described problems associated with prior art. 
         [0019]    The present invention has been made in an effort to configure a 2-channel diplexer by acquiring transmission characteristics of five microstrip lines, deducing an optimal width of the microstrip line and an interline interval by inducing a scattering constant for determining the transmission characteristic, and adjusting the lengths of second and fourth microstrip lines after matching an input/output load. 
         [0020]    An exemplary embodiment of the present invention provides a 2-channel diplexer structure with two channels in which a substrate having a predetermined size is configured, five microstrip lines are arranged on the top of the substrate to be parallel to each other with a predetermined interval, in which a front end of a first microstrip line and a front end of a third microstrip line are connected through a first connection line and a rear end of the third microstrip line and a rear end of a fifth microstrip line are connected through a second connection line to configure one microstrip line of           shape, a second microstrip line as an individual line is configured between the first microstrip line and the third microstrip line by the first connection line opened to a rear side by the first connection line, a fourth microstrip line as an individual line is configured between the third microstrip line and the fifth microstrip line opened to a front side by the second connection line, and it includes a first port connected with the first connection line, a third port connected to a rear end of the second microstrip line, a fourth port connected with the second connection line, and a third port connected to a front end of the fourth microstrip line. 
         [0021]    In this case, a 2-channel diplexer is configured by acquiring transmission characteristics of five microstrip lines by using the lengths of the second microstrip line and the fourth microstrip line, deducing an optimal width of the microstrip line and an interline interval by inducing a scattering constant for determining the transmission characteristic, and adjusting the lengths of second and fourth microstrip lines after matching an input/output load. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0022]    The above and other features of the present invention will now be described in detail with reference to certain exemplary embodiments thereof illustrated the accompanying drawings which are given hereinbelow by way of illustration only, and thus are not limitative of the present invention, and wherein: 
           [0023]      FIG. 1  is a diagram illustrating cross-sections and arrays of five microstrip lines that are parallel to each other and 10 resulting ports; 
           [0024]      FIG. 2  is a circuit diagram illustrating a configuration of a 2-channel diplexer of the present invention; 
           [0025]      FIG. 3  is a graph illustrating a response simulation result of a first port according to the present invention; 
           [0026]      FIG. 4  is a graph illustrating a response simulation result of a second port according to the present invention; 
           [0027]      FIG. 5A  is a diagram illustrating a state in which the 2-channel diplexer is implemented of the present invention; 
           [0028]      FIG. 5B  is a diagram illustrating a state in which a second microstrip line according to the present invention is adjusted to be approximately ⅖ shorter; 
           [0029]      FIG. 6  is a graph illustrating a characteristic of S 31  before adjusting the second microstrip line according to the present invention; 
           [0030]      FIG. 7  is a graph illustrating measurement of the characteristic of S 31  after adjusting the second microstrip line according to the present invention; 
           [0031]      FIG. 8  is a graph illustrating a characteristic of S 32  after adjusting the second microstrip line; 
           [0032]      FIG. 9  is a graph illustrating a characteristic of S 42  after adjusting the second microstrip line; 
           [0033]      FIG. 10  is a structure in which the second/fourth microstrip line of the diplexer is adjusted; 
           [0034]      FIG. 11  is a graph illustrating a characteristic of S 31  at the time of adjusting the second/fourth microstrip line; 
           [0035]      FIG. 12  is a graph illustrating a characteristic of S 41  at the time of adjusting the second/fourth microstrip line; 
           [0036]      FIG. 13  is a graph illustrating a characteristic of S 32  after adjusting the second/fourth microstrip line; and 
           [0037]      FIG. 14  is a graph illustrating a characteristic of S 42  at the time of adjusting the second/fourth microstrip line. 
       
    
    
       [0038]    It should be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various preferred features illustrative of the basic principles of the invention. 
         [0039]    In the figures, reference numbers refer to the same or equivalent parts of the present invention throughout the several figures of the drawing. 
       DETAILED DESCRIPTION 
       [0040]    Hereinafter reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings and described below. 
         [0041]    In order to achieve the object, the present invention will be described below in detail with reference to the accompanying drawings. 
         [0042]    In a diplexer, a substrate A having a predetermined size is configured, five microstrip lines are arranged on the top of the substrate A to be parallel to each other with a predetermined interval, in which a front end of a first microstrip line  10  and a front end of a third microstrip line  30  through a first connection line  11  and a rear end of the third microstrip line  30  and a rear end of a fifth microstrip line  50  are connected through a second connection line  12  to configure one microstrip line; a second microstrip line  20  as an individual line is configured between the first microstrip line and the third microstrip line  30  by the first connection line  11  opened to a rear side by the first connection line  11 ; a fourth microstrip line  40  as an individual line is configured between the third microstrip line  30  and the fifth microstrip line  50  opened to a front side by the second connection line  12 , and the diplexer includes: a first port  60  connected with the first connection line  11 ; a third port  80  connected to a rear end of the second microstrip line  20 ; a fourth port  90  connected with the second connection line  12 ; and a third port  70  connected to a front end of the fourth microstrip line  40 . 
         [0043]    Detailed configurations and exemplary embodiments thereof will be described below with reference to the accompanying drawings. 
         [0044]    A 2-channel diplexer is constituted by five microstrip lines and four ports. First, as shown in  FIGS. 2 and 5A , a substrate A having a predetermined size is configured in a housing (not illustrated), five microstrip lines of the first microstrip line  10  to the fifth microstrip line  50  are arranged on the top of the substrate A to be parallel to each other with a predetermined interval, in which the front end of the first microstrip line  10  and the front end of the third microstrip line  30  are connected through the first connection line  11  and the rear end of the third microstrip line  30  and the rear end of the fifth microstrip line  50  are connected through the second connection line  12  to configure one microstrip line of           shape. 
         [0045]    In this case, the lengths of the first microstrip line  10 , the third microstrip line  30 , and the fifth microstrip line  50  are preferably configured with the same length. 
         [0046]    A space between the first microstrip line  10  and the third microstrip line  30  connected to each other through the first connection line  11  is opened rearward and the second microstrip line  20  as the individual line is configured between the first microstrip line  10  and the third microstrip line  30 , which are opened. 
         [0047]    A space between the third microstrip line  30  and the fifth microstrip line  50  connected to each other through the second connection line  12  is opened frontward and the fourth microstrip line  40  as the individual line is configured between the third microstrip line  30  and the fifth microstrip line  50 , which are opened. 
         [0048]    The first port  60  is configured to be connected with the first connection line  11 , the third port  80  is configured to be connected to the rear end of the second microstrip line  20 , the fourth port  90  is configured to be connected with the second connection line  12 , and the second port  70  is configured to be connected to the front end of the fourth microstrip line  40 . 
         [0049]    The exemplary embodiments of the present invention will be described below. 
         [0050]    First, a theoretical fact should be certified in order to implement the present invention.  FIG. 1  illustrates cross-sections and arrays of five microstrip lines that are parallel to each other and 10 ports configured at terminals of five microstrip lines. When five microstrip lines are configured to be arranged in parallel to each other and current and voltage of each terminal at ten ports connected to the terminals of five microstrip lines is set as I, V matrix and corresponding admittance is set as Y matrix as illustrated in  FIG. 1 , the following equation can be induced. 
         [0000]        I=YV   (1)
 
         [0051]    Herein, I, V is an array vector of 10 rows and Y is a 10×10 matrix. 
         [0052]      FIG. 2  is a circuit diagram illustrating a configuration of a 2-channel diplexer. When the 2-channel diplexer is constituted by four ports, voltage and current at each port terminal are given by the following equation. 
         [0000]        I   A   =I   1   +I   3   I   B   =I   4   I   C   =I   7   I   D   =I   8   +I   10 ,,, 
         [0000]        I   2   =I   5   =I   6   =I   9 =0. 
         [0000]        V   A   =V   1   =V   3   V   B   =V   4 ,, 
         [0000]        V   c   =V   7   V   D   =V   8   =V   10 ,  (2)
 
         [0053]    I A : current of first port, I B : current of second port, I C : current of third port 
         [0054]    I D : current of fourth port, V A : voltage of first port, V B : voltage of second port 
         [0055]    V C : voltage of third port, V D : voltage of fourth port 
         [0056]    Four port equivalent admittances Y e  of the first to fourth ports are given by the following equation. 
         [0000]        Y   e   =Y   p   −Y   q   ×Y   r   −1   Y   t   (3)
 
         [0057]    When a set of respective current nodes of the first port, the second port, the third port, and the fourth port is represented by ΣY i,j,k,l , voltage nodes are represented by V i , V j , V k , and V l , terminal voltage other than the first to fourth ports is represented by V p , V q , V r , and V s , an admittance matrix among the port terminals is represented by Y p . 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Y 
                       p 
                     
                      
                     
                       [ 
                       
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ii 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ij 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ik 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   il 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ji 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   jj 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   jk 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   jl 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ki 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   kj 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   kk 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   kl 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   li 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   lj 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   lk 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ll 
                                 
                               
                             
                           
                         
                       
                       ] 
                     
                   
                   = 
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0058]    An admittance among the first port, the second port, the third port, and the fourth port terminals and the terminals other than the ports is represented by Y q . 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Y 
                       q 
                     
                      
                     
                       [ 
                       
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ip 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   iq 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ir 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   is 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   jp 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   jq 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   jr 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   js 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   kp 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   kq` 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   kr 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ks 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   lp 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   lq 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   lr 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ls 
                                 
                               
                             
                           
                         
                       
                       ] 
                     
                   
                   = 
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0059]    An admittance among the terminals other than the first port, the second port, the third port, and the fourth port terminals and the first, second, third, and fourth port terminals is represented by Y r . 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Y 
                       r 
                     
                      
                     
                       [ 
                       
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   π 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   pj 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   
                                     p 
                                      
                                     
                                         
                                     
                                      
                                     k 
                                   
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   pl 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   qi 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   qj 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   qk 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ql 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ri 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   rj 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   rk 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   rl 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   si 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   sj 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   sk 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   sl 
                                 
                               
                             
                           
                         
                       
                       ] 
                     
                   
                   = 
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0060]    In addition, an admittance among the terminals other than the first port, second, third, and fourth port terminals is represented by Y t . 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Y 
                       t 
                     
                      
                     
                       [ 
                       
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   pp 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   pq 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   pr 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   
                                     p 
                                      
                                     
                                         
                                     
                                      
                                     s 
                                   
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   qp 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   qq 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   qr 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   qs 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   rp 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   rq 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   rr 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   rs 
                                 
                               
                             
                           
                         
                         
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   sp 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   sq 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   sr 
                                 
                               
                             
                           
                           
                             
                               ∑ 
                               
                                 ∑ 
                                 
                                   Y 
                                   ss 
                                 
                               
                             
                           
                         
                       
                       ] 
                     
                   
                   = 
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0061]    Therefore, the equivalent admittance of the present invention according to the equation is acquired by applying the conditions of Equations (1) and (2), acquiring Equations (4), (5), (6), and (7), and substituting the equations into Equation (3). 
         [0062]    Y e  is the 4×4 matrix and the first port, the second port, the third port, and the fourth port are determined as 1, 2, 3, and 4 as follows in  FIG. 2 . 
         [0000]    
       
         
           
             
               
                 Y 
                 e 
               
                
               
                 ( 
                 
                   
                     
                       
                         Y 
                         11 
                       
                     
                     
                       
                         Y 
                         12 
                       
                     
                     
                       
                         Y 
                         13 
                       
                     
                     
                       
                         Y 
                         14 
                       
                     
                   
                   
                     
                       
                         Y 
                         21 
                       
                     
                     
                       
                         Y 
                         22 
                       
                     
                     
                       
                         Y 
                         23 
                       
                     
                     
                       
                         Y 
                         24 
                       
                     
                   
                   
                     
                       
                         Y 
                         31 
                       
                     
                     
                       
                         Y 
                         32 
                       
                     
                     
                       
                         Y 
                         33 
                       
                     
                     
                       
                         Y 
                         34 
                       
                     
                   
                   
                     
                       
                         Y 
                         41 
                       
                     
                     
                       
                         Y 
                         42 
                       
                     
                     
                       
                         Y 
                         43 
                       
                     
                     
                       
                         Y 
                         44 
                       
                     
                   
                 
                 ) 
               
             
             = 
           
         
       
     
         [0063]    In addition, scattering matrices of the first port, the second port, the third port, and the fourth port are acquired by the following relational equation. 
         [0000]      [ S]{U−Y   n   }{U−Y   n } −1   ={Z   N   −U}{Z   N   +U}   − = 
         [0064]    Herein, U represents a unit matrix. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         Y 
                         n 
                       
                        
                       
                         [ 
                         
                           Z 
                           0 
                         
                         ] 
                       
                     
                     
                       1 
                       / 
                       2 
                     
                   
                    
                   
                     [ 
                     
                       Y 
                       e 
                     
                     ] 
                   
                 
                  
                 
                   [ 
                   
                     Z 
                     0 
                   
                   ] 
                 
               
               
                 1 
                 / 
                 2 
               
             
             = 
             
               
                 
                   Z 
                   0 
                 
                  
                 
                   ( 
                   
                     
                       
                         
                           Z 
                           1 
                         
                       
                       
                         0 
                       
                       
                         0 
                       
                       
                         0 
                       
                     
                     
                       
                         0 
                       
                       
                         
                           Z 
                           2 
                         
                       
                       
                         0 
                       
                       
                         0 
                       
                     
                     
                       
                         0 
                       
                       
                         0 
                       
                       
                         
                           Z 
                           2 
                         
                       
                       
                         0 
                       
                     
                     
                       
                         0 
                       
                       
                         0 
                       
                       
                         0 
                       
                       
                         
                           Z 
                           1 
                         
                       
                     
                   
                   ) 
                 
               
               = 
             
           
         
       
     
         [0065]    A scattering parameter S′ of an optimal impedance of the input/output port is acquired by an impedance renormalization method depending on loads Z 1  and Z 2 . 
         [0066]    The optimal impedance is fixed to Z 1 , Z 2  is fixed at S′ 22 0, and Z 1  is acquired at S′ 11 0. 
         [0067]    The relational equation is given as follows. 
         [0000]      [ S′]={[Z   d   ]+[Z   S   ][S]}{[Z   S   ]+[Z   d   ][S]}   −1    
         [0068]    Herein, [Z S ] and [Z d ] are diagonal matrices and components thereof are as follows. 
         [0000]    
       
         
           
             
               Z 
               si 
             
             ≈ 
             
               
                 
                   
                     Z 
                     io 
                   
                   
                     Z 
                     i 
                   
                 
               
               + 
               
                 
                   
                     Z 
                     i 
                   
                   
                     Z 
                     io 
                   
                 
               
             
           
         
       
       
         
           
             
               Z 
               di 
             
             ≈ 
             
               
                 
                   
                     Z 
                     io 
                   
                   
                     Z 
                     i 
                   
                 
               
               + 
               
                 
                   
                     Z 
                     i 
                   
                   
                     Z 
                     io 
                   
                 
               
             
           
         
       
     
         [0069]    Herein, Z io  represents an impedance of port i. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         S 
                         22 
                         ′ 
                       
                       = 
                       0 
                     
                      
                     
                       
 
                     
                      
                     
                       Z 
                       1 
                     
                     = 
                     
                       
                         Z 
                         
                           1 
                            
                           o 
                         
                       
                        
                       
                         
                           
                             ( 
                             
                               
                                 k 
                                 2 
                               
                               - 
                               1 
                             
                             ) 
                           
                            
                           
                             ( 
                             
                               
                                 k 
                                 2 
                               
                               + 
                               1 
                             
                             ) 
                           
                         
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     k 
                     = 
                     
                       
                         ( 
                         
                           
                             S 
                             14 
                             2 
                           
                           - 
                           
                             S 
                             11 
                             2 
                           
                           - 
                           1 
                         
                         ) 
                       
                       / 
                       
                         S 
                         11 
                       
                     
                   
                 
               
               
                 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       S 
                       22 
                       ′ 
                     
                     = 
                     0 
                   
                    
                   
                     
 
                   
                    
                   
                     
                       Z 
                       2 
                     
                     = 
                     
                       
                         Z 
                         
                           2 
                            
                           o 
                         
                       
                        
                       
                         
                           
                             ( 
                             
                               
                                 k 
                                 2 
                               
                               - 
                               1 
                             
                             ) 
                           
                            
                           
                             ( 
                             
                               
                                 k 
                                 2 
                               
                               + 
                               1 
                             
                             ) 
                           
                         
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     k 
                     = 
                     
                       
                         ( 
                         
                           
                             S 
                             23 
                             2 
                           
                           - 
                           
                             S 
                             22 
                             2 
                           
                           - 
                           1 
                         
                         ) 
                       
                       / 
                       
                         S 
                         11 
                       
                     
                   
                 
               
               
                 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0070]    The 2-channel diplexer is configured by acquiring transmission characteristics of five microstrip lines, deducing an optimal width of the microstrip line and an interline interval by inducing a scattering constant for determining the transmission characteristic, and adjusting the lengths of the second and fourth microstrip lines  20  and  40  after matching an input/output load. 
         [0071]    A simulation result of the present invention is as follows. 
         [0072]    First, a response simulation is executed by setting a central frequency to 4 GHz, applying a Teflon value in which a relative dielectric constant is 2.22 and a dielectric thickness is 60 [mil] to the substrate, and setting a line width and an interline interval to the following values. 
         [0073]    W i =1200 [mil], i=1, 2, 3, 4, 5. 
         [0074]    S 1 =600 [mil], S 2 =1500 [mil], S 3 =1200 [mil], 
         [0075]    S 4 =600 [mil] 
         [0076]    A result of the response simulation of the first port according to the present invention may be acquired as illustrated in  FIG. 3 . A total effective dielectric constant of a part coupled to the fifth microstrip line  50  from the first microstrip line  10  is calculated as 1.711. 
         [0077]    The input and output loads in simulation are set to 35 ohm and 25 ohm, respectively, and matched to 50 ohm, a characteristic impedance of the input/output line, and a matching line is formed by a ¼ wavelength matching method. 
         [0078]    Effective dielectric constants of respective input and output matching units are 1.914 and 1.893 and a difference therebetween is just 0.02, and as a result, the taper lengths thereof are the same as each other. 
         [0079]    A result of the response simulation of the second port according to the present invention may be acquired as illustrated in  FIG. 4 .  FIG. 5A  is a diagram illustrating a state in which the 2-channel diplexer is implemented according to the present invention. 
         [0080]    The implemented exemplary embodiment of the present invention will be described below. 
         [0081]      FIG. 5B  illustrates a configuration of a diplexer in which the length of the second microstrip line  20  is adjusted. When characteristics of the diplexer in which the length of the second microstrip line  20  is adjusted to be ⅖ shorter are measured, the measured characteristics are illustrated in  FIGS. 6 and 7 . 
         [0082]      FIG. 6  is a diagram illustrating measurement of a characteristic S 31  while the length of the second microstrip line  20  is not adjusted, and  FIG. 7  is a diagram illustrating the measurement of characteristic S 31  while the length of the second microstrip line  20  is adjusted to be ⅖ shorter. 
         [0083]    As illustrated in  FIGS. 6 and 7 , in a bandwidth of 3 dB, 2 GHz is reduced to 1.7 GHz band from 2 GHz by approximately 0.3 GHz, S 11  is enhanced by 8 dB in a band of 4 GHz, and minimum attenuation is improved by 0.2 dB in a passband. 
         [0084]    However, S 32 , the characteristic for the second port  70  is not particularly influenced by a change as attenuation is increased from minimum −25 dB to −26 dB in the 4 GHz band unlike the first port  60 . 
         [0085]    The changed result is illustrated in  FIG. 8  and the characteristic reacts similarly as the characteristic in the original form. 
         [0086]    A characteristic of the fourth port  90  is measured as illustrated in  FIG. 9 . 
         [0087]    S 42  shows a change from 1.9 GHz to 2.0 GHz in the bandwidth and S 22  shows a change from −8 dB to −9 dB, as results before and after the length of the second microstrip line  20  is changed. 
         [0088]      FIG. 10  illustrates a configuration of a diplexer in which the lengths of both the second microstrip line  20  and the fourth microstrip line  40  are adjusted. When a characteristic of the diplexer in which the lengths of both the second microstrip line and the fourth microstrip line  40  are adjusted to be approximately ⅖ shorter, the measured characteristic is illustrated in  FIGS. 11 to 14 . 
         [0089]      FIG. 11  is a diagram illustrating measurement of the characteristic of S 31  when the lengths of the second microstrip line  20  and the fourth microstrip line  40  are adjusted,  FIG. 12  is a diagram illustrating measurement of the characteristic of S 41  when the lengths of the second microstrip line  20  and the fourth microstrip line  40  are adjusted,  FIG. 13  is a diagram illustrating measurement of the characteristic of S 32  when the lengths of the second microstrip line  20  and the fourth microstrip line  40  are adjusted, and  FIG. 14  is a diagram illustrating measurement of the characteristic of S 42  when the lengths of the second microstrip line  20  and the fourth microstrip line  40  are adjusted. 
         [0090]    As illustrated in  FIGS. 11 and 12 , in S 31  and S 41  in the first port  60  and S 32  and S 42  in the second port  70 , the bandwidth is not reduced as compared with the case where only the second microstrip line  20  is adjusted and is restored similarly as a characteristic of an original length in terms of the passband characteristic. 
         [0091]    In an attenuation band, both S 32  and S 41  show maximum attenuation in 3.76 GHz. 
         [0092]    In S 31 , the bandwidth of 3 DB is extended by 0.2 MHz as compared with the case where the second microstrip line  20  is adjusted, and as a result, S 31  is similar as the case where the length is not adjusted. 
         [0093]    S 11  as an input reflection coefficient is improved by 13 dB from −16 dB to −29 dB and S 32  corresponding to the isolation is improved by 6 dB from −26 dB to −32 dB. 
         [0094]    In S 41 , the maximum attenuation frequency is decreased from 3.82 GHz to 3.76 GHz as compared with the second microstrip line  20  and the reflection coefficient S 11  shows the minimum value in a frequency close to the central frequency as compared with the case where the second microstrip line  20  is adjusted to the minimum value in 4 GHz. 
         [0095]    An attenuation amount between the first port  60  and the fourth port  90  increases from −33 dB to −41 dB by −8 dB, and as a result, the isolation is improved. In S 42 , the bandwidth of 3 dB is decreased from 2 MHz to 1.67 MHz by 0.33 MHz. S 11 , the input reflection coefficient in the second port  70  is significantly decreased from −9 dB to −23 dB. 
         [0096]    Accordingly, as described above, interline intervals of five microstrip lines are configured to be different from each other and a change in the bandwidth is tested by changing the lengths of the second microstrip line  20  and the fourth microstrip line  40  to serve as the diplexer. Two ports among four ports constitute one channel to serve as the 2-channel diplexer. 
         [0097]    Since a 2-channel diplexer is configured by acquiring transmission characteristics of five microstrip lines, deducing an optimal width of the microstrip line and an interline interval by inducing a scattering constant for determining the transmission characteristic, and adjusting the lengths of second and fourth microstrip lines after matching an input/output load, the size of the 2-channel diplexer can be adjusted according to selection of a dielectric constant and durability thereof is excellent due to its simple structure. 
         [0098]    Since the diplexer is configured by only the microstrip line, the device can be miniaturized and thinned because there is no part occupying a space as a plane circuit form. 
         [0099]    While the invention will be described in conjunction with exemplary embodiments, it will be understood that present description is not intended to limit the invention to those exemplary embodiments. On the contrary, the invention is intended to cover not only the exemplary embodiments, but also various alternatives, modifications, equivalents and other embodiments, which may be included within the spirit and scope of the invention as defined by the appended claims.