Abstract:
An auto laser power control circuit is provided which improves the response of the optical output level of a laser diode in accordance with variations in the operation mode.  
     In an auto laser power control circuit for comparing a voltage corresponding to the optical output from the laser diode which emits a light in accordance with a supplied driving current with a reference voltage, and controlling the driving current so as to reduce the difference at the time of the steady operation, by controlling a switch connected between the input and output terminals of an operational unit which compares the voltage corresponding to the optical output from the laser diode and the reference voltage, the driving current to the laser diode is controlled with a smaller time constant upon the start such as a transition of from a read operation mode to a write operation mode as compared with the time of the steady operation.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to electronic equipment such as an optical disk device or a rewritable CD-ROM device, which performs writing and reading operation by using a laser diode as a light source. More particularly, it relates to an auto power control circuit for a laser diode or an auto laser power control (ALPC) circuit which is used to control a power to be supplied to the laser diode to keep the optical output from the laser diode constant.  
           [0003]    2. Description of the Related Art  
           [0004]    An optical disk device or a rewritable CD-ROM device uses a laser diode as a light source, and performs data writing and reading operation by irradiation of a laser light onto a disk. However, the optical output from the laser diode varies widely according to ambient the temperature, the operating period of time and so on. As is understood from FIG. 6, for example, even if the laser diode is driven by a certain current IF, the optical output power Po significantly varies according to the temperatures Tc of 50° C., 25° C., 0° C. and −25° C. It may thus occur that the oscillating operation of the laser diode stops or the optical output from the laser diode becomes too large with result of destruction. It is therefore required to control the driving current to be supplied to the laser diode in order to obtaing a substantially constant optical output power.  
           [0005]    To this end, the ALPC circuit is provided to detect the optical output from the laser diode and to then control the driving current flowing through the laser diode such that the optical output from the laser diode is kept constant.  
           [0006]    The description will be made on the fundamental ALPC circuit with reference to FIG. 7. This ALPC circuit  100  has a laser diode (LD)  1 , a photodiode (PD)  2 , a current-to-voltage converter or an I/V converter  3 , an operational amplifier  4  and a current booster  5 . The photodiode  2  is used to detect the optical output  101  from the LD 1  and thus generates a detected current Is that is representative of the power of the optical output  101 . This current Is flows through a resistor RM in the I/V converter  3  so that an optical detection voltage Vd corresponding to the optical output detection current Is is generated across the resistor RM. This voltage Vd is supplied to an inverting input terminal (−) of the operational amplifier  4  having a non-inverting input terminal (+) supplied with a reference voltage Vref. The current booster  5  is constituted by a PNP transistor Q and an resistor RL connected between the emitter thereof and a power voltage line Vcc. The base of the transistor Q is connected to the output of the operational amplifier  4 , and the collector thereof is connected to LD 1  to supply a driving current IF thereto.  
           [0007]    In this manner, the driving current IF of the LD 1  is controlled such that the optical detection voltage Vd becomes equal to the reference voltage Vref. The optical output from the LD 1  is thus controlled to be constant. For example, when the optical output  101  from the LD 1  increases due to the temperature variations, the optical detection current Is from the photodiode PD 2  increases accordingly. The increase in the optical detection current Is makes larger the voltage drop across the resistor RM to lower the optical detection voltage Vd. In response thereto, the operational amplifier  4  increases the base potential of the transistor Q, so that the driving current IF is made small. The optical output power  101  of the LD 1  is thus decreased.  
           [0008]    Based on the above ALPC circuit  1001  an optical disk device according to the prior art is equipped with an ALPC circuit  100  as shown in FIG. 8. It is to be noted that in the optical disk device, the required optical output from a laser diode differs according to the operation modes such as a write operation mode, an erase operation mode and a read operation mode. Therefore, the auto laser power control circuit  1000  is provided with a WRITE block  10 , an ERASE block  20  and a READ block  30 , one of which is brought into an active state in accordance with the operation mode to be currently initiated to control the driving current of the laser diode (LD)  1  during each operation mode. These blocks are substantially identical in configuration with one another. Accordingly, a description will given only to the WRITE block  107 . It is noted that the same constituents as those shown in FIG. 7 are indicated by the same reference numerals to omit further description thereof.  
           [0009]    The current flowing through PD 2  in response to the optical output from the LD 1  driven by the current booster  5  is supplied to the WRITE, ERASE and READ blocks  10 ,  20  and  30 , each of which thus includes the I/V converter  3 . The conversion voltage V 1  is supplied through a resistor R 1  to the operational amplifier  4 , differently from FIG. 7. The resistor R 1  determines the gain of the operational amplifier  4  together with a resistor R 2  connected between the output and the non-inverting terminal of the operational amplifier  4 . Such gain is set to be a considerable value,  100  for example, because a high sensitivity is required for this kind of device. However, such high gain then may sometime cause undesirable overshoot and/or undershoot in the output of the operational amplifier  4 . A capacitor C is therefore connected in parallel to the resistor R 2 , thereby solving such a problem.  
           [0010]    As is further distinct from FIG. 7, the reference voltage V 2  to be supplied to the amplifier  4  is derived from digital data. Specifically, the reference voltage digital data WRCUR is supplied from a system controller (not shown) in the write operation mode and is converted into a reference voltage V 2  by a D/A converter  6 , which the voltage is then supplied to the amplifier  4  as a reference voltage Vref shown in FIG. 7 through a switch SW 0  provided between the D/A converter  6  and the operational amplifier  4 . The switch SW 0  is controlled by a write operation mode signal C 0  that assumes an active level in the write operation mode and an inactive level in the other modes. The active level of the signal C 0  causes the switch SW 0  to select the voltage converted by the D/A converter  6  and supplies it to the operational amplifier  4  as the reference voltage V 2 . When the signal C 0  indicates a mode other than the write operation mode, on the other hand, the switch SW 0  selects and supplies the ground potential to the operation amplifier  4 , so that the LD 1  is maintained uncontrolled from the WRITE block  10  even if the malfunction of the current booster  5  occurs. As is readily understood from the foregoing, each of the other blocks  20  and  30  is activated by the corresponding signal to the control signal C 0  in the same manner with the unique digital data for reference voltage to corresponding mode. Each of the outputs WLD, ELD and RLD of the blocks  10 ,  20  and  30  is then supplied to the current booster  5 . Although not shown, the current booster  5  is constructed to one of the signals WLD, ELD and RLD in response to the operation mode to be currently executed.  
           [0011]    Thus, the LD  101  is controlled to output a laser with a substantially constant power in the respective operation modes.  
           [0012]    It has been, however, recognized by the inventor that the ALPC circuit  100  has the problem that the shift in operation from one mode to another mode to be a relatively long period of time to deteriorate a high speed operation. This problem becomes remarkable upon the operation being moved from the erase or read mode to the write mode. This will be described below in details with reference to FIG. 9 which shows the signal voltage waveforms of respective parts in the WRITE block  10  in case where the operation mode is shifted from write to read, and then back to write.  
           [0013]    In the write operation mode shown on the left-hand side of FIG. 9, the signal C 0  assumes a high level as an active level, so that the reference voltage V 2  based on the data WRCUR is supplied to the operational amplifier  4 . Thus, the output terminal WLD voltage of the block  10  is controlled such that the conversion voltage V 1  becomes equal to this voltage. As a result, the optical output from the LD 1  is kept constant.  
           [0014]    By the selection of the read operation mode, the signal C 0  is changed to a low level as an inactive level. As a result, the ground potential is supplied to the operational amplifier  4  through the switch SW 0 , so that the output from the operational amplifier  4 , i.e., the voltage of the WLD terminal is also changed to the ground potential.  
           [0015]    On the other hand, the current booster  5  selects the output voltage of the READ block  30 . As a result, the LD 1  is held under the control of the READ block  30 . Thus, the current from the PD 2  becomes the optical detection current in the read operation mode. Accordingly, the signal voltage V 1  in the WRITE block  10  becomes the voltage value corresponding to the data RECUR in the READ block  30 . Herein, in the optical disk device, the driving current of the LD 1  required in the write operation mode is considerably larger than that in the other mode. Therefore, the voltage based on the RECUR is considerably smaller as compared with the voltage based on the WRCUR.  
           [0016]    When the read operation has been completed, and the write operation mode is selected again, the signal C 0  is changed to the high level. As a result, the switch SW 0  selects the D/A converter  6 , so that the voltage V 2  rises to the voltage value corresponding to the WRCUR. However, the voltage of the WLD terminal does not follow the voltage V 2 , but rises with a certain time constant as shown in FIG. 9.  
           [0017]    Specifically, as described above, the capacitor C is provided in order to suppress the overshoot and the undershoot of the signal WRCUR which would be otherwise caused by the high gain, about 100, of the operational amplifier  4 . For such a purpose, the capacitance value of the capacitor C is required to be set large (0.01 to 0.1 μF). When the write operation mode is selected, the operational amplifier  4  is first required to recharge the capacitor C which has been discharged in the previous read operation mode. However, the capacitor C has the above large capacitance value, and hence the charging of the capacitor C takes as much as several tens of μsec. The conversion voltage V 1  also changes gradually. During this period, the optical output level from the laser diode LD 1  is of course not stabilized. If information is written on a disk in such unstable state, the writing accuracy is deteriorated. At the worst, erroneous information may be written. For this reason, the actual write operation has to be initiated after elapse of such unstable period. Thus, the shift in operation mode cannot attained at a high speed.  
           [0018]    As described above, a quick shift from the operation mode (ex., read operation mode) requiring a small driving current for the laser diode LD 1  to the operation mode (write operation mode) requiring a large driving current is not executed. Further, there is also a high risk of erroneous writing.  
         SUMMARY OF THE INVENTION  
         [0019]    An object of the present invention is to provide an improved ALPC circuit.  
           [0020]    Another object of the present invention is to provide an ALPC circuit capable of quickly executing a transition from one operation mode to another operation mode.  
           [0021]    A still other object of the present invention is to provide an ALPC circuit whereby the response time of a laser diode to the change in operation mode is improved.  
           [0022]    A still further object of the present invention is to provide an ALPC circuit capable of improving the writing accuracy by a laser diode by providing a higher-speed output response upon the switching of the operation mode, while stabilizing the loop operation in the stationary state.  
           [0023]    An ALPC circuit in accordance with the present invention is constructed such that a voltage responsive to the optical output of a laser diode generated in accordance with a driving current flowing therethrough is compared with a reference voltage to produce a voltage difference, and the driving current is controlled so as to decrease the voltage difference with a first time constant (or first driving ability) during a steady operation and with a second time constant (or second driving ability) that is smaller than the first time constant (the first driving ability) upon initiation.  
           [0024]    More specifically, controlling the driving current during the steady operation is executed with such a first time constant (ability) that suppresses an undesirable overshoot and/or undershoot. On the other hand, upon initiation in which a transition from a first mode such as a read operation to a second operation mode such as a write operation occurs, the control to the driving current is not executed with the first time constant (ability), but is executed is with a second, smaller time constant smaller (that is, a second, larger driving ability) than the first one. In this manner, the operation mode is quickly shifted, and the stabilization in the optical output of the laser diode is also improved.  
           [0025]    The period of time during which the driving current is being controlled with the second time constant (second driving ability) may be determined by observing a signal based on the optical output of the laser diode. However, it is preferable to set such period of time at a certain balue without observing the signal derived from the laser diode. This control may be attained in a timer operation manner. This is because that the second time constant (second driving ability) may be easily obtained by deactivating the feedback loop that functions during the steady operation and such deactivation can be attained by the state of a switch that is controlled by a timer.  
           [0026]    In more detail, the control of the driving current during the steady operation is performed by a operational amplifier that compares the voltage indicative of the optical output of the laser diode with the reference voltage, and the parallel connection of a resistor and a capacitor is provided between the input and output terminals of the operational amplifier to control its gain and to suppress the undesirable overshoot and/or undershoot. In such configuration, therefore, a switch is provided in parallel to the parallel connection in accordance of the present invention. This switch is brought into an OFF state during the steady operation and into an ON state upon initiation. The state of the switch is changed to the OFF state after a predetermined period of time that is controlled by a timer. It is thus possible to obtain the first and second time constants (first and second driving ability).  
           [0027]    An auto laser power control circuit according to another aspect of the present invention includes an operational amplifier producing an output signal in response to a voltage difference between a voltage representative of a laser power of a laser diode and a reference voltage and a driving circuit driving the laser diode in response to the output so as to make the voltage difference small, with the amplifier changing its output signal at a first rate during a predetermined period of time from a time point at which the auto laser power control circuit is initiated and thereafter changing the output signal at a second rate that is lower than the first rate. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0028]    The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:  
         [0029]    [0029]FIG. 1 is a circuit diagram illustrative of an ALPC circuit according to a first embodiment of the present invention;  
         [0030]    [0030]FIG. 2 is a waveform diagram of the respective signals produced in the circuit shown in FIG. 1;  
         [0031]    [0031]FIG. 3 is a circuit diagram illustrative of an ALPC circuit according to a second embodiment of the present invention;  
         [0032]    [0032]FIG. 4 is a waveform diagram of the respective signals produced in the circuit shown in FIG. 3;  
         [0033]    [0033]FIG. 5 is a circuit diagram illustrative of a WRITE block in an ALPC circuit for illustrating a third embodiment of the present invention;  
         [0034]    [0034]FIG. 6 is a graph representative of the characteristic in an optical output power to a driving current of a laser diode;  
         [0035]    [0035]FIG. 7 is a circuit diagram for illustrating a fundamental ALPC operation;  
         [0036]    [0036]FIG. 8 is a circuit diagram illustrative of an ALPC circuit employed in an optical disk drive according to the prior art; and  
         [0037]    [0037]FIG. 9 is a waveform diagram respective signals produced in the ALPC circuit shown in FIG. 8. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0038]    Referring now to FIG. 1, an ALPC circuit  200  according to the first embodiment of the present invention includes a WRITE block  11 , and ERASE block  21  and a READ block  31 . These blocks are substantially identical in configuration with one another. Accordingly, a detailed explanation will be made only on the WRITE block  11 . It is to be noted that the same constituents as those shown FIG. 8 are denoted by the same reference numerals and the further description thereon is omitted.  
         [0039]    In this embodiment, a switch SW 2  is provided in accordance with present invention, which is connected in parallel to a resistor R 2  and a capacitor C between the output terminal and the inverting input terminal of an operational amplifier  4 . The switch SW 2  is controlled by a control signal C 2  supplied from circuit  7 , that responds to Mode signal. The signal C 2  assumes an active level during the predetermined period of time in response to the designation or selection of the write operation mode for initiating the WRITE block  11 . The signal C 2  is changed to an inactive level after such period of time and maintained at the inactive level during the steady operation in the write operation mode. The signal C 2  also takes the inactive level in a mode such as read and erase other than the write operation mode. When the signal C 2  is at the low level as the inactive level, the switch SW 2  is turned OFF state. The gain of operational amplifier  4  is thus determined by the resistors R 1  and R 2 , and further the capacitor C operates to suppress the overshoot and/or undershoot of the signal at the terminal WLD. Thus, the amplifier  4  drives the terminal WLD with a first time constant or a first driving ability. When the signal C 2  takes the high level as the active level, the switch SW 2  is turned ON state. The operational amplifier  4  thus functions as a voltage follower to have the level at the terminal WLD follow the input voltage V 2  in spite of the resistors R 1  and R 2  and the capacitor C. Thus, the amplifier  4  drives the terminal WLD with a second time constant or a second driving ability that is smaller than the first time constant or is larger than the first driving ability. The change in signal at the terminal WLD is thus made at a higher rate.  
         [0040]    In order to made it sure that the terminal WLD is driven by the operational amplifier  4  as a voltage follower during the signal C 2  taking the active level, a switch SW 1  is further provided and connected between the I/V converter  3  and the resistor R 1 . This switch SW 1  is controlled by a control signal C 1  such that it is turned ON only during the steady operation in the write operation mode. During the remaining modes including the initiation of the write operation mode, the switch SW 1  is brought into the OFF state. The I/V converter  3  is thus disconnected from the resistor R 1 .  
         [0041]    It is convenient to generate, upon initiation of the write operation mode, at the terminal WLD such a voltage that is higher than the voltage to be produced during the steady operation in the write operation mode, for the purpose of raising the level of terminal WLD at a much higher rate. To this end, additional digital data WRPOW for such voltage is supplied from a system controller (not shown). As is discussed with reference to FIG. 8, the data WRCUR provides a reference voltage to be produced during the steady operation. These two digital data are supplied to the switch SW 3  which is controlled by a control signal C 3 . The signal C 3  assumes one logic level at lease upon the initiation of the write mode or at least during the predetermined period from the time point at which the write operation mode is started, and assumes the other logic level during the steady operation in the write operation mode. When the signal C 3  takes the high level as one logic level, the switch SW 3  selects and supplies the data WRPOW to the D/A converter  6 . During the whole period of time in the write operation mode, the switch SW 0  forms an electrical path between the D/A converter  6  and the amplifier  4 . Accordingly, the voltage based on the data WRPOW is supplied as the reference voltage V 2  to the operational amplifier  4 . When the signal C 3  is changed to the other logic level, i.e., the low level, the reference voltage is derived from the data WRCUR and supplied to the operational amplifier  4 .  
         [0042]    Although not shown, the control signal generation circuit  7  generating the control signals C 0  to C 3  includes a timer counter. This counter starts it operation to count a clock signal in response to the MODE signal being changed to designate the write mode from another mode and produces an output after the counting values of the clock signal reaches a predetermined value. This period of time is defined as the initiation of the write operation mode. By utilizing the timer counter and the MODE signal, the circuit  7  generates the control signals C 0  to C 3  whose logic levels are controlled as described above. It is apparent that the further detailed description on the circuit  7  is not necessary, because the one having ordinary skill in the art will readily understand the construction and operation of the circuit  7  with reference also to timing chart shown in FIG. 9.  
         [0043]    The description will be now moved on the operation of the ALPC circuit  200  with reference to FIG. 2 in which operation mode makes a transition from writing to reading and again back to writing. Note that the write operation mode shown on the left-hand side of FIG. 2 shows the steady operation in the write operation mode. The signal C 1  thus assumes the high level as the active level, so that the switch SW 1  is brought into the ON state. Accordingly, the conversion voltage V 1  is supplied to the operational amplifier  4 . Further, the signal C 2  assumes the low level as the inactive level, so that the switch SW 2  is in the OFF state. Further, the signal C 3  assumes the low level as the inactive level, so that the switch SW 3  selects the data WRCUR. Accordingly, the reference voltage V 2  based on the data is supplied to the operational amplifier  4 . Therefore, the voltage of the output terminal WLD of the block  11  is controlled such that the conversion voltage V 1  becomes equal to the reference voltage V 2  based on the data WRCUR. As a result, the optical output from the LD 1  becomes substantially constant.  
         [0044]    By the selection of the read operation mode, the signals C 1  and C 2  both assume the low level as the inactive level. During this mode, the signal C 3  is allowed to take any one of the low and high levels. The signal C 0  is changed to the low level, so that the ground potential is supplied to the operational amplifier  4  through the switch SW 0 . Accordingly, the output from the operational amplifier  4 , i.e., the voltage of the terminal WLD is also changed to the ground potential.  
         [0045]    On the other hand, the current booster  5  selects the output voltage of the READ block  31 . As a result, the LD 1  is held under the control of the READ block  31 .  
         [0046]    When the read operation has been completed, and the write operation mode is selected again. The signals C 0  and C 3  are changed to the high level upon the start thereof. As a result, the D/A converter  6  is selected by the switch SW 0 , and the set voltage data WRPOW is selected by the switch SW 3 , so that the reference voltage V 2  rises to the voltage value corresponding to the set voltage data WRPOW. On the other hand, the signal C 1  is kept at the low level, and the signal C 2  is changed to the high level. Accordingly, the operational amplifier  4  starts to operate as a voltage follower without influence of the conversion voltage V 1 . Therefore, the terminal WLD is driven by the operational amplifier  4  to follow the voltage based on the data WRPOW. In other words, the capacitor C is separated from the operation for increase the level at the terminal WLD. Therefore, the rising time constant of the terminal WLD voltage can be set at a very smaller value. The WLD terminal thus reaches the WRPOW voltage level in about 3 μsec.  
         [0047]    In this embodiment, the period of time defined as “initiation” is set to be 5 μsec. After 5 μsec., therefore, the signal C 1  is changed to the high level, so that the conversion voltage V 1  is supplied to the operational amplifier  4  through the switch SW 1 . At the same timing, the signals C 2  and C 3  are both changed to the low level. Accordingly, the switch SW 2  is brought into the OFF state, and the set voltage data WRCUR is selected by the switch SW 3 . As a result, the reference voltage V 2  based on the data WRCUR is supplied to the operational amplifier  4 . The output voltage of the terminal WLD is controlled so that the conversion voltage V 1  becomes equal to this voltage. Consequently, the optical output from the LD 1  becomes constant. The overshoot and the undershoot of the terminal WLD voltage are suppressed by the capacitor C.  
         [0048]    It is preferable that the period of time corresponding to “initiation” is set to be longer the time period required for the WLD terminal voltage to rise up to the voltage V 2  based on the set voltage data WRPOW. In this manner, the voltage of the WLD terminal quickly becomes the voltage equal to the terminal WLD voltage at the steady operation when the operation mode is changed from the read operation to the write operation mode. As a result, the LD 1  quickly obtains an optical output necessary for the write operation mode.  
         [0049]    At the beginning of the steady operation in the write operation mode, the switch SW 1  is brought into the ON state, so that the conversion voltage V 1  is supplied to one of electrodes of the capacitor C. In consequence, the operation WLD terminal voltage decreases as indicated by the portion surrounded by the dotted lines of FIG. 2. Such decrease in the terminal WLD voltage does not provide a substantial affect to the optical output from the LD 1 . This is because the terminal WLD voltage corresponding to such a level that is obtained by multiplying the input voltage by the amplification gain (ex., 100) set by the resistors R 1  and R 2  of the operational amplifier  4  and thus the change of the conversion voltage V 1  is compressed to such a value that is obtained by dividing the change of WLD voltage by the gain. The conversion voltage V 1  decreases slightly lower than the reference voltage V 2  as shown in FIG. 2.  
         [0050]    Referring now to FIG. 3, an ALPC circuit  210  according to the second embodiment of the present invention includes a WRITE block  12 , a ERASE block  22  and a READ block  32 . These blocks are substantially identical in configuration with one another. It is to be noted that the same constituents as those shown in FIG. 1 are indicated by the same reference numerals to omit further description thereof.  
         [0051]    The reference voltage digital data WRCUR and WRPOW are converted by the D/A converter  6  and  8 , respectively, differently from FIG. 1. These two reference voltages are supplied to the switch SW 3  that is controlled by a control signal C 3 .  
         [0052]    As is further distinct from FIG. 1, a switch SW 4  is coupled between one of electrodes of a capacitor C and the inverting input terminal of a operational amplifier  4 . The switch SW 4  is controlled by a control signal C 4  supplied from a circuit  9  that responds to MODE signal. The signal C 4  assumes one logic level during the steady operation in the write operation mode, and assumes the other logic level at least upon the initiation of the write operation mode or at least during the predetermined period from the time point at which the write operation mode is started. When the signal C 4  takes the high level as one logic level, the switch SW 4  forms an electrical path between the inverting input terminal of the operational amplifier  4  and one of electrodes of the capacitor C. When the signal C 4  is changed to the other logic level, i.e., the low level, the switch SW 4  selects and supplies the voltage based on the data WRCUR to one of electrodes of the capacitor C. Thus, the capacitor C is charged with the voltage difference between the voltage of the terminal WLD and the voltage based on the data WRCUR during the initiation of the write operation mode.  
         [0053]    Although not shown, the control signal generation circuit  9  generating the control signals C 0  to C 4  includes a timer counter. The circuit  9  generates the control signal C 0  to C 3  with the counter, as the circuit  7  does, and generates further the control signal C 4  whose logic levels is controlled as described above.  
         [0054]    The description will be now moved on the operation of the ALPC circuit  210  with reference FIG. 4 in which operation mode makes the same transition as shown in FIG. 2.  
         [0055]    During the steady operation in the write operation mode shown on the left-handed side of FIG. 4, the conversion voltage V 1  and the reference voltage V 2  based on the data WRCUR are supplied to the operational amplifier  4  by the switches SW 1 , SW 2  and SW 3 , as described above. The signal C 4  thus assumes the high level as the one level, so that the electrical path between the inverting input terminal of the operational amplifier  4  and one of the capacitor C is formed. Therefore, the voltage output terminal WLD of the block  12  is controlled such that the conversion voltage V 1  becomes equal to the reference voltage V 2  based on the data WRCUR.  
         [0056]    When the read operation mode is selected, the signal C 4  as well as the signal C 3  is allowed to take any one of the low and high levels. The switch SW 0  selects and supplies the ground potential to the operational amplifier  4  in response to the signal C 0 . Accordingly, the voltage of the terminal WLD is also changed to the ground potential. On the other hand, the current booster  5  selects the output voltage of the READ block  32 , so that the LD 1  is held under the control of the READ block  32 .  
         [0057]    When the read operation has been completed, and the write operation mode is selected again. The signal C 4  is changed to the low level upon the start thereof. As a result, the switch SW 4  selects the D/A converter  6 , so that the voltage based on the data WRCUR is supplied to one of electrodes of the capacitor C. On the other hand, the operational amplifier  4  starts to operate as a voltage follower, so that terminal WLD is driven by the operational amplifier  4  to follow the voltage based on the data WRPOW. Therefore, the rising time constant of the terminal WLD voltage can be set at a very small value as the first embodiment. In addition, the capacitor is charged with a voltage difference between the voltages based on the data WRCUR and WRPOW.  
         [0058]    At the beginning of the steady operation in the write operation mode, the switch SW 1  is brought into the ON state, and the switch SW 4  forms the electrical path between one of electrodes of the capacitor C and the inverting input terminal of the operational amplifier  4 . As a result, the conversion voltage V 1  is supplied to one of electrodes of the capacitor C. However, in this embodiment the operation WLD terminal voltage does not decrease as shown in FIG. 2. This is because the capacitor C is charged before the steady operation in the write operation mode. Therefore, the LD 1  quickly obtains an optical output necessary for the write operation mode without such decrease in the terminal WLD as shown in FIG. 2.  
         [0059]    Further, in a third embodiment of the present invention as shown in FIG. 5, a switch SW 5  is coupled between one of electrodes of a capacitor C and the inverting input terminal of a operational amplifier  5  in place of the switch SW 4  as shown in FIG. 3.  
         [0060]    In this embodiment, a switch SW 1  is turned OFF state and the switch SW 5  selects the conversion voltage V 1  when the write operation mode is selected. Thus, the conversion voltage V 1  is supplied not to the inverting input terminal of the operational amplifier  4  but to one of electrodes of the capacitor C. Therefore, the capacitor C is charged with the voltage difference between the conversion voltage V 1  and the voltage of the terminal WLD before the steady operation in the write operation mode. Therefore, the voltage of the WLD terminal does not decreases even if the steady operation in the write operation mode is started.  
         [0061]    As mentioned above, the switching driving current is carried out by the current booster  5  that selects the WLD, ELD and RLD terminal in response to the operation mode to be currently executed in the above embodiments. However, the way of switching is not limited to such switching. Further, the converting the output voltage of the operational amplifier into driving current is not limited to the above embodiments. Therefore, the set voltage data WRPOW is not limited to the voltage that is higher than the set voltage data WRCUR.  
         [0062]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.