Abstract:
A circuit and corresponding method for a precision floating gate voltage reference that uses a feedback loop, conduction of tunnel devices, and a bandgap cell to accurately program a desired charge level on a floating gate and provide a predictable and programmable temperature coefficient parameter for such voltage reference. In one embodiment, a bandgap cell is coupled through a capacitor to the floating gate storage node for providing a voltage source for canceling the temperature coefficient (TC) of the storage capacitor. The circuit and method enables TC to be minimized by either choosing the proper voltage source characteristics or alternatively, by choosing the proper ratio of two capacitors. The bandgap cell can alternatively be designed to have positive TC (PTAT voltage sources) or negative TC (VBE junction).

Description:
FIELD OF INVENTION  
       [0001]     The invention relates generally to the field of circuit design and in particular to improving the accuracy of a floating gate voltage reference circuit.  
       BACKGROUND OF INVENTION  
       [0002]     One of the key performance parameters for precision voltage references and comparators is the temperature coefficient (TC). The TC parameter specifies the amount of voltage change which occurs as a result of a change in temperature. TC for a given component may be positive, negative, or may change direction over various temperature ranges.  
         [0003]     The bandgap and buried zener are two known methods for implementing voltage references. The bandgap and buried zener voltage references utilize special bipolar or BiCMOS process technologies. These types of references require various trimming methods, e.g., laser trimmed thin-film resistors or metal fuses, for achieving close to 1 mV initial accuracy and a TC at or below 5 ppm per degree C.  
         [0004]     More recently, a precision floating gate voltage reference (FGREF) has been implemented on EEPROM CMOS technology. A precision floating gate voltage reference stores a known voltage on a floating capacitor tied to the input of an opamp. Tunnel diodes are typically used as switches to charge the floating capacitor during the programming (set) mode. The TC of the FGREF depends on the TC of the storage capacitor. In order to achieve close to zero TC, known circuits and methods utilize a mix of different types of capacitors for causing the composite TC of the capacitors to be near zero.  
         [0005]      FIG. 1  illustrates a simplified schematic of an ideal prior art floating gate voltage reference circuit  10 . The charge on a capacitor C is set at the factory by using one or more tunnel diodes, as at S 0 , as an ideal switch for coupling an input voltage Vs 0  to capacitor C in a programming (set) mode. Capacitor C holds the programmed voltage, Vs, at a storage node, node  11 , which is coupled to the input of a unity gain buffer  12 . The unity gain buffer  12  is provided to isolate the floating gate storage node  11  from a load at the output terminal  14  of buffer  12 . At the conclusion of the set mode, the output V out  of the voltage reference circuit  10  at node  14  has been set to a voltage that is a function of, and preferably is equal to the input set voltage V so  received at an input terminal  16 .  
         [0006]     The temperature coefficient of voltage reference circuit  10  is a function of the TC of the capacitor C. The TC of capacitor C is typically fairly low (˜+20 ppm/C) for Poly1/Poly2 capacitors in CMOS technology. Since the storage node  11  is floating and fully protected from any outside or inside contact, charge conservation principles can be applied to calculate the TC of Vout due to the change in the value of Capacitor C with temperature. A set of Equations 1 below shows that TC of Vout is the negative of the TC of the capacitor C.  
         [0007]     EQUATIONS 1: Charge at Storage Node  11  is given by Q(t 0 )=constant, determined at programming time and a selected temperature, t 0 .  
         [0008]     Assume: C(t)=C 0 (1+α(t−t 0 )), where t 0 =25° C. (ambient temperature), where t is the die temperature, C 0  is the capacitance of capacitor C, and α is the TC of capacitor C.  
         Q   ⁡     (   t   )       =           C   0     ·       V   S     ⁡     (   25   )         ⁢     
     ∴     Q   ⁡     (   t   )         =         C   ⁡     (   t   )       ·       V   S     ⁡     (   t   )         =       C   0     ·       V   S     ⁡     (   25   )                 
               ⇒       V   S     ⁡     (   t   )         =         C   0     ·       V   S     ⁡     (   25   )           C   ⁡     (   t   )                     =         C   0     ·       V   S     ⁡     (   25   )             C   0     ⁡     (     1   +       α   ·   Δ     ⁢           ⁢   t       )                   
         or   ⁢           ⁢       V   S     ⁡     (   t   )         ≅         V   S     ⁡     (   25   )       ·     (     1   -       α   ·   Δ     ⁢           ⁢   t       )           
         or   ⁢           ⁢       V   R     ⁡     (   t   )         =         V   R     ⁡     (   25   )       ·     (     1   -       α   ·   Δ     ⁢           ⁢   t       )           
         TC     V   R       =         1     V   R       ·       ∂     V   R         ∂   t         =     -   α           
       cos   ⁢     φ   ^     ⁢   cos   ⁢           ⁢     φ   ^         
 
         [0009]     Since the TC of Vout is the negative of the TC of the capacitor C, in order to get zero TC at Vout, capacitors with near-zero TC are required. In one known method, two different types of capacitors are combined for minimizing TC.  FIG. 2   a  illustrates an exemplary prior art circuit  20  utilizing a differential scheme for achieving a minimum TC. The differential scheme with feedback is utilized in order to address drawbacks of the circuit  10 , including common mode noise of the buffer amplifier  12  over a wide range of reference voltage values. The combined composite capacitor comprises a Poly1 to Poly2 capacitor, referred to as CP type capacitor, connected in parallel with a Poly1 to N+ Diffusion capacitor, referred to as CPD type capacitor, as illustrated symbolically in  FIG. 2   b . The CP capacitor typically has a TC of +20 ppm/deg C. and the CPD capacitor typically has a TC of −10 ppm/deg C. TC. This known method includes adjusting the area ratios of CP to CPD in order to cause the TC at Vout to approach zero, in accordance with a set of Equations 2.  
         [0010]     EQUATIONS 2: Where t=die Temperature, t 0 =ambient temperature during the programming of the voltage reference circuit, Δt=t−t 0 , α=TC of a CP type capacitor, and β=TC of a CPD type capacitor:  
       C   =     CP   +   CPD         
       CP   =       CP   0     ⁡     (     1   +       α   ·   Δ     ⁢           ⁢   t       )           
       CPD   =       CPD   0     ⁡     (     1   -       β   ·   Δ     ⁢           ⁢   t       )           
               ∴   C     =       (       CP   0     +     CPD   0       )     +       (       α   ·     CP   0       -     β   ·     CPD   0         )     ⁢   Δ   ⁢           ⁢   t                   =       (       CP   0     +     CPD   0       )     ⁢     (     1   +             α   ·     CP   0       -     β   ·     CPD   0             CP   0     +     CPD   0         ·   Δ     ⁢           ⁢   t       )                 
         TC   eq     =     γ   =         α   ·     CP   0       -     β   ·     CPD   0             CP   0     +     CPD   0               
 
         [0011]     Thus, by choosing CP 0 /CPD 0  appropriately, one can get a Zero TC value.  
         [0012]     In  FIG. 2   a , the switches S 0  and S 1  are coupled between an input terminal  24  and respective inputs of an opamp  22  for setting a set voltage, V S0  on a storage node  21  and on the inverting input of opamp  22 , respectively. Storage capacitors CPD 0  and CP 0  are connected in parallel between node  21  and ground. Feedback capacitors CPD 1  and CP 1  are connected in parallel between the negative input of opamp  22  and, via a switch S 2 , the output of circuit  20 . The switch S 2  is used to set the output end of the feedback capacitor CP 1  to a desired reference voltage value, V R .  
         [0013]     As shown in  FIG. 2   a , when two different types of capacitors are used to achieve close to a zero TC, it is known to use a mix of CP and CPD capacitors. As is also seen, this method is applied to both the storage capacitor in the circuit as well as the feedback capacitor. The TC of the CPD capacitor has been found, however, to be dependent on the applied voltage. Consequently, attempting to use two types of capacitors, e.g., as shown in  FIG. 2   a , to obtain zero TC for different output voltage values, is very challenging and is mostly an empirical exercise.  
         [0014]     What is therefore needed is a method for TC cancellation for a floating gate voltage reference that uses only one type of capacitor so as to provide a predictable and programmable TC for the overall voltage reference generator circuit. What is also needed is an analog floating gate voltage reference circuit for accurately programming a desired charge level on a floating gate and for making TC reduction methods more reliable and repeatable for different output voltage values.  
       SUMMARY OF THE INVENTION  
       [0015]     The present invention overcomes the drawbacks of known circuits and methods by providing a circuit and method for minimizing TC more reliably in a high precision floating gate reference. The circuit and corresponding method of the present invention uses only one type of capacitor so as to provide a predictable as well as a programmable TC for such references.  
         [0016]     In one embodiment according to the present invention, a bandgap cell is coupled through a capacitor to the storage node in order to cancel the TC of the storage capacitor, wherein both capacitors are of the same type. The bandgap cell can be designed to have Positive TC (Proportional to Absolute Temperature (PTAT) source) or Negative TC (Voltage Base-Emitter (VBE) junction source).  
         [0017]     An advantage of the present invention is that the TC of a PTAT or VBE source is very reliable and nearly process/technology independent. As a result, a more predictable and programmable TC of the overall FGREF is provided.  
         [0018]     Standard CMOS technology has only one type of capacitor element. Thus, another advantage of the present invention is that it enables minimizing TC in a high precision floating gate voltage reference circuit utilizing standard CMOS technology.  
         [0019]     Another advantage of the present invention is that it makes minimizing TC more predictable. In an alternative embodiment, a predictable TC value can be dialed in via a programmable control register.  
         [0020]     Broadly stated, the present invention provides, in a floating gate voltage reference circuit for storing a predetermined voltage at a first node coupled to an input of an opamp wherein a voltage reference output is generated at the output of the opamp as a function of the charge of the floating gate, the reference circuit having a first capacitor coupled to the first node; a method for improving the accuracy of the voltage reference output as a function of temperature, comprising coupling a second capacitor to an input of the opamp; wherein the first capacitor and the second capacitor are the same type of capacitor; supplying a voltage source providing an output having a predetermined and substantially constant Temperature Coefficient (TC); and connecting the voltage source in series combination with the second capacitor so as to compensate for the TC of the first capacitor such that, during a read mode of the reference circuit, the temperature coefficient, TC, of the voltage reference output is substantially reduced.  
         [0021]     Broadly stated, the present invention also provides a floating gate reference circuit for improving the accuracy of a voltage reference output as a function of temperature comprising a floating gate for storing charge thereon, the charge appearing at a first node coupled to an input of an opamp, wherein a voltage reference output is generated at the output of the opamp as a function of the charge of the floating gate, a first capacitor coupled to the first node; a second capacitor coupled to an input of the opamp; wherein the first capacitor and the second capacitor are the same type; and a voltage source providing an output voltage having a predetermined and substantially constant TC; the voltage source connected in series combination with the second capacitor so as to compensate for the TC of the first capacitor such that, during a read mode of the reference circuit, the TC of the voltage reference output is substantially reduced.  
         [0022]     These and other embodiments, features, aspects, and advantages of the invention will become better understood with regard to the following description, appended claims and accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     The foregoing aspects and the attendant advantages of the present invention will become more readily appreciated by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:  
         [0024]      FIG. 1  illustrates a simplified schematic of a prior art floating gate voltage reference circuit  10  in a programming (set) mode;  
         [0025]      FIG. 2   a  illustrates an exemplary circuit utilizing a differential scheme for implementing the method using two different type of capacitors method for minimizing TC;  
         [0026]      FIG. 2   b  illustrates a schematic and corresponding symbology for a combined composite capacitor comprising a Poly1 to Poly2, CP type capacitor, and a Poly1 to N+ Diffusion, CPD type capacitor, as shown in the circuit in  FIG. 2   a;    
         [0027]      FIG. 3   a  illustrates a conceptual schematic of a circuit having two capacitors of the same type and TC and a voltage source connected to capacitor C 1 ;  
         [0028]      FIG. 3   b  shows an embodiment further illustrating the concept of the present invention where a voltage source with TC=β is connected to capacitor C 1  to cancel the TC of C 0  in a voltage reference circuit;  
         [0029]      FIG. 3   c  shows an embodiment of the circuit and method according to the present invention;  
         [0030]      FIG. 4  is a schematic of a typical CMOS implementation of a Bandgap reference generation circuit for generating a PTAT current source I ptat  used for generating the positive PTAT voltage source, Vp, in  FIG. 3   c , and a negative TC voltage source, V B , in  FIG. 5   b;    
         [0031]      FIG. 5   a  is a simplified schematic of an alternative embodiment according to the present invention for canceling the TC of the main storage capacitor through use of a negative voltage source; and  
         [0032]      FIG. 5   b  shows a preferred embodiment of the voltage reference circuit in  FIG. 5   a.   
     
    
       [0033]     Reference symbols or names are used in the Figures to indicate certain components, aspects or features shown therein, with reference symbols common to more than one Figure indicating like components, aspects or features shown therein.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0034]     The present invention is a system and method for improving the accuracy of the output reference voltage (V ref ) of a floating gate voltage reference circuit as a function of temperature. An object of the present invention is to minimize Tc in a high precision floating gate voltage reference circuit in a more predictable and programmable way.  
         [0035]      FIG. 3   a  illustrates a conceptual schematic of a circuit  100  having two capacitors of the same type and TC and a voltage source connected to capacitor C 1 . The circuit  100  includes a series combination of a capacitor C 1  and a positive voltage source, V p . The series combination is connected in parallel with a capacitor C 0  between a storage node at a voltage Vs and ground. The voltage source, V p , has a predetermined and constant TC. The voltage source, V p , can be made using bandgap cells, for example, having Proportional to Absolute Temperature (PTAT) voltage outputs which typically have a well defined TC of +3300 ppm/deg C. value. For this example, as the value of capacitor C 1  varies with temperature, V p  also changes, thereby canceling the overall changes in voltage, Vs, as shown in a set of Equations 3.  
         [0036]     EQUATIONS 3: Where t=die Temperature, t 0 =ambient temperature, i.e., 25° C., capacitors C 0  and C 1  are the same type of capacitors with the same TC=α: 
 
At  t   0 =25° C.,
 
 V   S (25)= V   S0 
 
 V   P (25)= V   P0 
 
 Q (25)= C   0   V   S0   +C   1 ( V   S0   −V   P0 )
 
 Assuming V P (t) is provided such that:  
           V   P     ⁡     (   t   )       =       V     P   ⁢           ⁢   0       ⁡     (     1   +       β   ·   Δ     ⁢           ⁢   t       )           
         Δ   ⁢           ⁢   t     =     t   -   25         
       Then   ,          ⁢               V   R     ⁡     (   t   )       =       V   S     ⁡     (   t   )                   =       Q   ⁡     (   25   )                     C   0     ⁡     (     1   +       α   ·   Δ     ⁢           ⁢   t       )       ⁢     V     S   ⁢   0         +         C   1     ⁡     (     1   +       α   ·   Δ     ⁢           ⁢   t       )       ⁢     (       V     S   ⁢   0       -       V     P   ⁢   0       ⁡     (     1   +       β   ·   Δ     ⁢           ⁢   t       )         )                                             =       Q   ⁡     (   25   )                   C   0     ⁢     V     S   ⁢   0         +       C   1     ⁡     (       V     S   ⁢   0       -     V     P   ⁢   0         )       +               Δ   ⁢           ⁢     t   ⁡     (         α   ·     C   0       ⁢     V     S   ⁢   0         +       α   ·     C   1       ⁢     V     S   ⁢   0         -       β   ·     C   1       ⁢     V     P   ⁢   0         -       α   ·     C   1       ⁢     V     P   ⁢   0           )                             
               TC     V   R       =         1     V   R       ·       ∂     V   R         ∂   t         ⁢     ❘     t   =   25                     =       -     1     V   R         ⁢     {         α   ⁡     (       C   0     +     C   1       )       ⁢     V     S   ⁢           ⁢   0         -       (     α   +   β     )     ⁢       C   1     ·     V     P   ⁢           ⁢   0             }                 
 
 Thus, again by choosing a proper ratio of C 1 /C 0  or V P0 , one can minimize TC. 
 
         [0037]      FIG. 3   b  shows an embodiment further illustrating the concept of the present invention where a voltage source with TC=β is connected to capacitor C 1  to cancel the TC of C 0  in a voltage reference circuit. A voltage reference circuit  200  adds an opamp  22  to the circuit  30  in  FIG. 3   a . A feedback capacitor C fo  is coupled from the output, V o , to the negative input of opamp  22 . A voltage source, Vp, which is preferably a PTAT voltage source having V P (t)=V P0 (1+β·Δt)), as shown in Equations 3, is connected in series with a capacitor C 1  for enabling the cancellation of the TC of C 0 .  
         [0038]      FIG. 3   c  is a schematic of an embodiment of a voltage reference circuit  300  and corresponding method according to the present invention. The reference circuit  300  includes a voltage source generation circuit  310 . The voltage source generation circuit  310  includes a 4 bit resistive Digital to Analog Converter (DAC)  302 , schematically represented by distinct switch nodes 1-N for a switch S C  that is controlled by a decoder  304 . Decoder  304  receives 4 bits, C[3:0], in a conventional manner, for providing the desired programmable value of the PTAT voltage source, Vp. The reference circuit  300  also includes a storage capacitor C 1  connected in series between the output of DAC  302  and an end of switch S o  that is connected to a noninverting input of opamp  22  at storage node  309 . The other end of switch S o  is coupled to an input terminal  306 . A storage capacitor C o  is coupled between the storage node  309  and ground. Switch S 1  is coupled between the input terminal  306  and the inverting input of opamp  22 . Switches S 0  and S 1  are operable during the programming mode for setting the voltage on a storage node  309  and on the inverting input of an opamp  22 , respectively, to a set voltage, Vs 0 , which is coupled to the circuit  300  at input terminal  306 . Switch S 2  is operable during the programming mode to set the output side of a feedback capacitor C f0  to a desired reference voltage value VR. From Equations 3, it can be seen that the circuit in  FIG. 3   c  provides a programmable TC of the reference voltage, V R .  
         [0039]      FIG. 4  is a schematic of a typical CMOS implementation of a Bandgap reference generation circuit for generating a PTAT current source I ptat  used for generating the positive PTAT voltage source, Vp, in  FIG. 3   c , and a negative TC voltage source, V B , in  FIG. 5   b . The exemplary circuit embodiment in  FIG. 4  is designed for TC compensation over −10 to +10 ppm/deg C. range with 1.25 ppm resolution to reliably achieve less than 1 ppm/deg C. TC. It would be evident to one skilled in the art to create offset or increase compensation range or resolution by simply changing the PTAT voltage DAC design in circuit  300 .  
         [0040]     Circuit  410  includes MOSFET transistors M 0 , M 1 , M 2 , M 3 , M 4 , and M 5 , PNP transistors Q 1 , Q 2 , and Q 3 , resistor R 0 , variable resistor R 1 , and a 4:16 decoder. Transistors M 0 , M 1 , M 2 , and M 3  are connected so as to provide a current mirror that causes the current in transistors Q1 and Q2 to be either equal or an exact multiple of each other. For simplification of the description, it is assumed that transistor Q 1  and transistor Q 2  conduct the same amount of current. The size of the emitter area for transistor Q 2  is ten times, i.e., 10×, the size for Q1, i.e., 1×. As a result, the base-emitter voltage of transistor Q 2 , V BE2 , will be smaller than the base-emitter voltage of Q 1 , V BE1 . The difference between the base-emitter voltages of transistors Q 1  and Q 2  is in accordance with the equation: ΔV BE =V BE2 −V BE1 =(kT/q)ln(10), where 10 is the ratio of the two emitter areas, k is Boltzmann&#39;s constant, and q is the electron charge. The voltages across transistor M 0  and M 1  are the same since it was assumed that the transistor Q 1  and transistor Q 2  conduct the same amount of current. This causes the voltage across resistor R o  to equal (kT/q)ln(10). The corresponding current for R 0 =V BE /R 0 =(kT/R 0 q)ln(10) which flows through transistor M 3 . The current through M 4  is the same as the current for M 3  and is referred to as PTAT since the current is Proportional To Absolute Temperature in accordance with (kT/R 0 q)ln(10).  
         [0041]     In circuit  410 , the current flowing through variable resistor R 1  creates a voltage V p  as a function of the resistance set for variable resistor, R 1  via the 4 to 16 decoder. Vp is the voltage across R 1  and is given by V P =αR 1 /R 0 *(kT/q)ln(10), where αR 1  is the resistance set for variable resistance R 1  via the 4 to 16 decoder.  
         [0042]     Another sample of the current from transistor M 3 , i.e., I ptat  is forced to conduct from transistor M 5 . A current I ptat  also flows through transistor Q 3  and creates a voltage V B . The voltage V B  is the base-emitter voltage of transistor Q 3  since the base of Q3 is connected to ground. The temperature of a base-emitter junction of PNP transistor Q3 is known to vary by approximately −2 mv/° C. or 3000 ppm/° C. over a very broad temperature range.  
         [0043]      FIG. 5   a  is a simplified schematic of an alternative embodiment according to the present invention for canceling the TC of the main storage capacitor through use of a negative voltage source. In the circuit  500  in  FIG. 5   a , the TC of storage capacitor C 0  is canceled by coupling a negative TC voltage source, V B , to the inverting input of an opamp  522  via a capacitor C f1 . A feedback capacitor C fo  is connected in series between an output terminal  502  at voltage, V 0 , and the series combination of voltage source, V B , and capacitor C f1 . The inverting and noninverting inputs of the opamp  522  are set to a voltage V S . A capacitor C 0  is connected to the noninverting input of the opamp  522 . Capacitors C 0 , C f0 , and C f1  are preferably comprised of a Poly1 to Poly 2 capacitor structure in CMOS technology.  
         [0044]      FIG. 5   b  shows a circuit  600  according to a preferred embodiment of the voltage reference circuit in  FIG. 5   a . The circuit  600  includes a voltage source generator circuit  610  for generating the negative TC voltage source V B . Switch S 0  and S 1  in circuit  600  is operable during a programming mode for setting the voltage on the noninverting input, i.e., storage node  601 , and the inverting input of opamp  522 , respectively, to a set voltage, V so , which is coupled to the circuit  600 . Switches S 1  and S 2  are operable during a programming mode for setting the voltage on the output side of the feedback capacitor C f0  in  FIG. 5   b  to the desired reference voltage value, V R .  
         [0045]     For circuit  600 , in order to adjust TC of reference voltage, V 0 , either the magnitude of V B  or the magnitude of C f1  can be adjusted. Referring to  FIG. 5   b , alternatively, a DAC could be used to produce a variable voltage V B  for coupling to capacitor C f1  for TC cancellation. In the preferred embodiment shown in  FIG. 5   b , V B  is kept fixed and the coupling capacitor Cfl is made variable thru a capacitive DAC arrangement as shown. The circuit  600  includes a capacitive DAC  606 , schematically represented by distinct nodes 1-M for switches S d , S e , . . . S f  that are controlled by a decoder  604 . Decoder  304  receives 4 bits, C[3:0], in a conventional manner, for providing the desired programmable value of the voltage source, V B , for coupling to capacitor C f1  for TC cancellation.  
         [0046]     The present invention according to the embodiment in  FIG. 5  is designed for TC compensation over a range of −10 to +10 ppm/deg C. with 1.25 ppm resolution to reliably achieve less than 1 ppm/deg C. TC. It would be evident to one skilled in the art to create offset or increase compensation range or resolution by changing the VBE capacitive DAC or alternatively using a resistive DAC for the VBE design.  
         [0047]     The exemplary circuit  410  in  FIG. 4  includes an embodiment of the negative voltage source generator circuit  610 . The negative TC voltage source, V B , is generated by the base emitter junction of a PNP transistor in the Bandgap cell in  FIG. 4 . The negative TC voltage source V B  generated by the base emitter junction as in  FIG. 4  is also referred to herein as “VBE junction TC” or “VBE”. For the exemplary circuit  410 , the V B  value is 600 mV and has a well defined TC of −3300 ppm/deg C.  
         [0048]     Equations 4 show that, for a particular V B  value, by choosing a proper ratio of C f1 /C f0  or V B0 , TC can be minimized.  
         [0049]     EQUATIONS #4:  
         [0050]     For V B (t) such that:  
           V   B     ⁡     (   t   )       =       V     B   ⁢           ⁢   0       ⁡     (     1   -       β   ·   Δ     ⁢           ⁢   t       )           
         Δ   ⁢           ⁢   t     =     t   -     t   0           
           V   R     ⁡     (   t   )       =         V   S     ⁡     (   t   )       -       V   FB     ⁡     (   t   )             
           At   ⁢           ⁢   t     =     t   0       ,           ⁢         V   R     ⁡     (     t   0     )       =       V     R   ⁢           ⁢   0       =       V     S   ⁢           ⁢   0       -     V     FB   ⁢           ⁢   0                 
             However   ,       Δ   ⁢           ⁢       V   R     ⁡     (   t   )         =       Δ   ⁢           ⁢       V   S     ⁡     (   t   )         -     Δ   ⁢           ⁢       V   FB     ⁡     (   t   )         -     Δ   ⁢           ⁢         V   B     ⁡     (   t   )       ·       C     f   ⁢           ⁢   1       /     C     f   ⁢           ⁢   0                             =           -   α     ·     V     R   ⁢           ⁢   0       ·   Δ     ⁢           ⁢   t     +       β   ·       C     f   ⁢           ⁢   1         C     f   ⁢           ⁢   0         ·     V     B   ⁢           ⁢   0       ·   Δ     ⁢           ⁢   t                 
         TC     V   R       =           1     V   R       ·       ∂     V   R         ∂   t         ⁢     ❘     t   =     t   ⁢           ⁢   0           =       -   α     +     β   ·       C     f   ⁢           ⁢   1         C     f   ⁢           ⁢   0         ·       V     B   ⁢           ⁢   0         V     R   ⁢           ⁢   0                   
 
 Thus, by choosing a proper ratio of C f1 /C f0  or V B0 , one can minimize TC. 
 
         [0051]     According to an alternative embodiment of the present invention, the voltage source for the voltage reference of the present invention may also be provided by another floating gate reference.  
         [0052]     As described above, the present invention minimizes TC more reliably in a high precision floating gate reference. The circuit and corresponding method of the present invention uses only one type of capacitor so as to provide a predictable as well as programmable TC for such references.  
         [0053]     Although specific embodiments of the invention have been described, various modifications, alterations, alternative constructions, and equivalents are also encompassed within the scope of the invention.  
         [0054]     The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that additions, subtractions, deletions, and other modifications and changes may be made thereunto without departing from the broader spirit and scope of the invention as set forth in the claims.