Abstract:
A semiconductor electronic circuit, which can generate high voltage pulses, includes a current source coupled to form a series circuit with a pair of impedances between first and second voltage source terminals. A driving source is connected with a control terminal of the current source. Output voltage-current characteristics of the driving source are such that its output current is almost 0, when the output voltage is in the proximity of 0 V and that it is not 0 for other voltages. Thus, the voltage at the control terminal of the current source is clamped at a predetermined voltage level determined by the circuit structure of the driving source, when the voltage at the output terminal is lower than the predetermined voltage.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a semiconductor electronic circuit, and, in particular, to a semiconductor electronic circuit which can generate high voltage pulses. 
     Circuit systems are known in which several circuit elements are connected in series in order to obtain a high voltage output. Prior art devices, in which a plurality of transistors are connected in series and their bases are driven simultaneously, are disclosed in JP-A-No. 52-19932, JP-A-No. 56-162543, JP-A-No. 60-51024, JP-A-No. 60-57724, etc. FIG. 2 illustrates a respective circuit construction of such devices. 
     In FIG. 2 transistors 1 and 2 are connected in series and resistors 3 and 4 are resistors short-circuiting the base and the emitter of each of the transistors . A driving signal is inputted through capacitors 5 and 6, respectively. The reference numeral 7 represents a driving signal source. The transistors 1 and 2 work as if they were a single transistor, one end of which is connected through a load resistor 9 with a voltage source terminal 8 and the other end of which is connected with another voltage source terminal 11. The output terminal is designated by 10 and in many cases voltage amplitude signals appearing there are used as the output. 
     By this circuit system it is possible to obtain a high withstand voltage owing to the superposition of many transistors. However, the operation speed of the circuit is slow, because it has no discharge path, in the case where the load is capacitive. 
     FIG. 3 indicates a method for resolving this problem. It is a so-called push-pull circuit construction, by which complementary transistors 12 and 13 are combined. The output terminal 10 is taken-out from the transistor 
     connection point, through which electric power is transferred to the load. By this circuit system it is possible to increase the working speed, but the withstand voltage of the transistor elements 12 and 13 should be raised, in order that the circuit can be used as a high withstand voltage circuit. Further, if each of the transistors 12 and 13 in FIG. 3 actually consists of a plurality of transistors, as is the case for the transistors 1 and 2 in FIG. 2, a high withstand voltage can be obtained. However, in the case where complementary transistors are used as in the circuit indicated in FIG. 3, it is difficult to balance the p and the n conductivity type and particular attention should be paid to how to drive the circuit. In addition, capacitors having a relatively large capacitance are used for coupling the signal source 7 with the base of the transistor, and fairly sophisticated techniques are necessary for fabricating high withstand voltage capacitors. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a voltage pulse generating circuit having a simple circuit construction which permits realizing a high withstand voltage, and, in particular, an electronic circuit suitable for generating positive and negative pulses. 
     In a series connection type high withstand voltage circuit according to prior art techniques, it is fairly difficult to divide a voltage equally to all the constituent elements. This is caused by the fact that capacitors or coils are used as coupling means for signals as indicated in FIG. 3. Also, the potential of the base of the transistors can hardly be determined, when there are no signals. That is, if a definite base-drive is possible and the base potential is fixed certainly, when there are no signals, a high voltage pulse generating circuit working very stably can be realized. This invention utilizes this principle in an ingenious manner. FIG. 1 shows the principle, in which the reference numeral 14 indicates a current source, controlled by electric signals coming from a driving source 17, which is in turn controlled by a signal source 7A. Voltage sources are connected with the terminals 8 and 11, which are connected through impedance elements 15 and 16 with a current source 14. 
     FIG. 4 shows a voltage-current characteristic curve of the driving source 17 in FIG. 1. It has characteristics that, when the voltage of the driving source 17 exceeds a certain value, current begins to flow and when the voltage decreases to 0 V, the current decreases also to 0. On the other hand its reverse direction characteristics are such that at first in the proximity of 0 V almost no current flows and that when the voltage exceeds a certain value, the current increases rapidly. 
     FIG. 5 shows a representative waveform in the circuit indicated in FIG. 1. An output V 0  is produced for an input voltage V I . At this time the amplitude of the output pulse V 0  varies from V ss  to V cc , which are source voltages. At the same time the output voltage V 1  of the driving source 17 varies from V ss  to a predetermined voltage V c  of a certain level (which is determined by the form of the circuit of the driving source and most preferably about 1/2 of |V ss  |+|V cc  | on the basis of the working condition). In a prior art circuit the voltage V 1  varies as indicated by the broken line and the lowest level arrives at the proximity of V cc . For this reason an overvoltage, which is the sum of V ss  and V cc , is applied to the element 15, which gives rise to destruction of the element 15 itself. 
     According to this invention, since the driving source 17 having the characteristics indicated in FIG. 4 is connected with the control terminal of the current source 14, the lowest level of the voltage V 1  is clamped at the predetermined voltage V c  and thus the element 15 cannot be destroyed by overvoltage. 
     Other objects and effects of this invention will be understood from the description of the preferred embodiments stated below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a scheme indicating the principle of this invention. 
     FIGS. 2 and 3 show two different constructions of prior art circuits. 
     FIGS. 4 and 5 are schemes for explaining the principle of this invention. 
     FIGS. 6 to 12 are schemes illustrating various concrete embodiments of this invention. 
     FIGS. 13 to 17 are schemes showing the time sequence for explaining the working mode of the circuits indicated in FIGS. 6 to 12. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 6 indicates a concrete embodiment of this invention, in which the same items as those in the explanation stated above are designated by the same reference numerals. 
     A PNP transistor 14 constitutes the current source and the impedance elements are realized by resistors 15 and 16. An NPN transistor 18 and a resistor 19 form the driving source for the transistor 14. 
     In this circuit, when a certain voltage is applied to input terminals 71 and 72, the transistor 18 becomes conductive. At this time the collector-emitter voltage V 1  and the collector current of the transistor 18 vary as shown by the characteristic curve in FIG. 4 and therefore satisfy the characteristics necessary for the driving source for realizing this invention. At the same time the voltage is applied the transistors 18 and 14 become conductive and a current flows through the resistor 16 and a voltage drop is produced thereacross. Consequently the voltage V 0  at the output terminal 10 rises beyond the source voltage V cc  towards the voltage V ss . This rise stops at the point where the transistor 14 is saturated. At this time almost the entire voltage, which is equal to the sum of V ss  and V cc , is applied to the resistor 16. Then, when the voltage V I  decreases to &#34;0&#34;, the transistor 18 becomes cut-off. Although there is some delay due to the accumulation effect, the transistor 14 becomes cut-off in a short time and the output voltage V 0  falls towards V cc . During this fall period V 0  passes through the ground voltage V c  of the driving circuit. The voltage V 0  is almost equal to V 1  (they differ by about 0.7 V from each other for silicon transistors). When this value reaches V c , the collector-emitter voltage of the transistor 18 is 0 and the working point is in the proximity of the point 0 in FIG. 4. At this time, since the transistors 18 and 14 are in the cut-off state, only a small current flows therebetween. Therefore, while the voltage drop V 1  is kept approximately at 0 and even if V cc  reaches its lowest point, this value is maintained. In this way the output waveforms V 1  and V 0  indicated in FIG. 5 can be obtained. 
     That is, in this case, since the collector voltage of the transistor 18 is clamped to 0 V, when V 0  is at the level of V cc , the sum of the source voltages (V ss  +V cc ) can be shared precisely by the collector junction of the transistor 14 and the resistor 15. For example, for V ss  =100 V, V c  =0 V and for V ss  =-100 V, V 1  =0 and since each of the resistor 15 and the collector junction of the transistor 14 bears 100 V, the circuit may be so designed that the withstand voltage of each element is 100 V. 
     FIG. 13 shows the time sequence of the working mode of the circuit indicated in FIG. 6. When the input voltage V I  is at the level &#34;1&#34; (high level), i.e. when it is at a level obtained by adding 5 V to the voltage V c , the transistor 18 is switched on and subsequently the transistor 14 is also switched on. When the value of the resistor 15 is so chosen that it is lower than that of the resistor 16, the voltage V 1  is approximately equal to the source voltage V ss . Further, when the base current of the transistor 14 is appropriately chosen (from the viewpoint of the operation the base current is set so as to be sufficiently large for the saturation state), the transistor 14 is saturated and the voltage V 0  becomes approximately equal to V 22 . On the other hand, when the voltage V I  reaches approximately the V 0  level, the base-emitter current of the transistor 18 becomes 0 and the transistor 18 enters into the cut-off state. 
     For this reason, since the transistor 14 also enters into the cut-off state, the voltage V 0  reaches the source voltage V cc . When the voltage V 0  reaches V cc , the voltage V 1  also varies towards V cc , following it, but since the characteristics of the transistor 18 are as indicated in FIG. 4, V 1  is fixed at the level of V c . 
     FIG. 14 is a scheme showing the time sequence, in the case where the source voltages are V ss  =400 V, V cc  =0 V and V c  =200 V in the embodiment indicated in FIG. 6. Since the input signal V I  is controlled by referring to the voltage V c , it varies between 200 V and 205 V. When the voltage V I  is 205 V, both of the transistors 18 and 14 are turned on and the voltages V 1  and V 0  become 400 V, which is the source voltage. In the case where V I  is 200 V, both the transistors 18 and 14 are turned off, V 1  being 200 V, which is V ss , V 0  being 0 V, which is V cc . 
     FIG. 15 is a scheme showing the time sequence, in the case where the source voltages V ss  =200 V, V c  =0 V and V cc  =-150 V in the embodiment indicated in FIG. 6. Input signals V I  between 0 and 5 V are applied. In this case the level of the voltage V 1  is 200 V or 0 V and the level of the voltage V 0  is 200 V or -150 V. Generally, in the case where the voltages V ss  and V cc  are not equal in their absolute value, when the value of the voltage V 0  is selected to be (V ss  +V cc )/2, it becomes easy to design the transistors 14, 18 with respect to their withstand voltage. That is, in this way the withstand voltage can be shared equally between the two elements. 
     As has been designed above, according to the prior art techniques the element 15 was easily destroyed, because the base voltage was not clamped to 0 V and varied towards V cc . Such can be prevented according to the present embodiment. In the circuit indicated in FIG. 6, however, the withstand voltage of the resistor 16 should be higher than the sum of the source voltages (V ss  +V cc ), because this sum voltage is applied to the resistor 16, when the output voltage is at the level of V ss  in spite of its simple structure. 
     FIG. 7 illustrates another embodiment of this invention, in which the resistor 15 in FIG. 6 is replaced by an active circuit and an equivalent impedance is formed by a combination of a transistor and a power supply 21. A driving source 17A can be realized by the transistor 18 and the resistor 19. Further, in this embodiment transistors 14C and 20C are complementary to the transistors 14 and 20, respectively, and the function of the resistor 16 is represented by the transistors 14C and 20C. By means of this circuit it is possible to obtain voltage pulses at the output terminal 10 by switching on and off the driving sources 17A and 17C alternately. Since this circuit uses nothing which corresponds to the resistors 15 and 16, almost no electric power loss is produced, particularly when a capacitor C, etc. is connected as a load 10 Therefore, stable operation can be expected. 
     FIG. 8 illustrates still another embodiment of this invention. In this embodiment the transistor 20 and a resistor 21R realizing the equivalent impedance are controlled by another transistor 21. The purpose of this is to make the operation more stable and to reduce electric power consumption . This circuit is a complementary symmetric circuit of p and n conductivity types. 
     The reference numeral 31 means common terminals; 31A and 31B controlling the transistors 20 and 14; 31D and 31E controlling the transistors 14C and 20C. 
     FIG. 16 is a scheme showing the time sequence for the embodiment indicated in FIG. 8. Inputs V IU1  and V IU2  are controlled between V c  and V c  +0.7 V and V IL1  and V IL2  are controlled between V c  and V c  -0.7 V. When the voltages V IU1  and V IU2  are V c  +0.7 V (it is not necessary that these two signals are raised at the same time to the 1 level, as indicated in the figure), transistors 21T, 18, 20, 14 are turned on and V 0  reaches the V ss  level (at this time V 1U  also is at V ss ). On the other hand, since the transistors 14C and 20C are turned off, but V 1L  is at the V c  level, the voltage between V 0  and V cc  is shared on halves by the collector junctions of the transistors 14C and 20C. 
     Next, after having set the voltages V IU1  and V IU2  at V c , when V IL1  and V IL2  become V c  +0.7 V, the transistors 20CT and 18C are turned on and 14C and 20C also are turned on. In this way the output voltage V 0  varies from V ss  towards the V cc  level and finally settles at the V cc  level (at this time V 1L  passes from V c  to the V cc  level). On the other hand, when V 0  becomes V cc , V 1U  arrives at the V c  level is is fixed at this potential. When V 0  is at the V cc  level, the voltage between the source voltages V ss  and V cc  is shared on halves by the collector junctions of the transistors 20 and 14. 
     FIG. 9 illustrates still another embodiment of this invention. In this case all the active elements are constituted by field effect transistors (FET) (preferably MOS.FET) and therefore this embodiment has an advantage that the process can be simplified, when they are integrated in one chip. 
     FIG. 10 illustrates still another embodiment of this invention. 
     In this embodiment the semiconductor element is constituted by bipolar transistors and field effect transistors (FET) (preferably MOS.FET) mixed together. The performance of the circuit is increased owing to the fact that its output stage, for which a particularly high driving power is required, is composed of bipolar transistors 20, 14, 20C and 14C and that the circuit only transmitting signals is composed of FETs 40, 41, 42 and 43. Further, for the FETs, since in some cases their clamp effect due to the characteristics indicated in FIG. 4 is weak, it is preferable to use diodes 44, 45, as indicated by broken lines indicated in the figure, in order to make their clamp action sure. 
     FIG. 17 is a scheme showing the time sequence in the embodiment indicated in FIG. 10. Although the operation time sequence has the same form as that indicated in FIG. 16 showing the sequence for the embodiment illustrated in FIG. 8, since its input stage is constituted by MOS transistors 40, 41, 42 and 43, the amplitude of the input voltages V IU1 , V IU2 , V IL1  and V IL2  is comprised between V c  and V c  +5 V or between V c  and V c  -5 V. One of the voltage amplitudes V 1U  and V 1l  is fixed at V c  in the same way as i the explanation mentioned above. 
     FIG. 11 illustrates still another embodiment of this invention. In this case there are 3 control terminals, among which the terminal 31AB controls the pulse rising portion and the terminal 31DE controls the pulse falling portion. Reference numerals 50, 51, 52 and 53 represent pulse delay circuits. It is possible to ameliorate its characteristics by lowering of electric power consumption and improving waveform generation, operating speed, etc. by choosing appropriately the delay time of each of the pulse delay circuits. 
     FIG. 12 illustrates a modified circuit according to this invention. In this embodiment basic circuits described in the above embodiments are superposed on each other and a plurality of output terminals 10A, 10B, 10C, 10D, 10E, 10F and 10 are taken out from connection points between two adjacent transistors. Control signals are applied to terminals 31M, 31C and 31N. However, since the potential difference between the circuit group 80 having the terminal 10A on the high voltage side and the control terminal 31M is large, the static capacitance of the junction of a diode 60 biased in the reverse direction is used as a signal coupling means. A terminal 62 is connected to a particular voltage level. The same measures as those described above are taken also for a transistor group 81, a diode 61 and a terminal 63 except for the direction of the voltage to be applied. 
     In this embodiment it is possible to obtain a plurality of groups of pulses having different levels. Further it is possible to realize voltage pulses having an amplitude twice as large as that obtained in the embodiments described previously at the terminal 10. 
     The circuits in the embodiments of this invention described above can be used as a drive for capacitive loads such as EL (electroluminescence) structures, plasma displays, piezoelectric motors, ink jet printers, piezo elements, etc. 
     As explained above, according to this invention, since it is possible to generate high voltage pulses, without any coupling means such as capacitors, etc., it is possible to realize a pulse generating element suitable for intergrated circuits. 
     Further it is possible to generate pulses, whose output amplitude extends to 2E (V), by constituting the circuits using elements whose withstand voltage (usually collector-emitter withstand voltage) is E (V).