Abstract:
A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first second, third and fourth conductive plates are electrically connected and constitute at least two capacitors.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C §119 of Korean Patent Application 2006-0051510 filed on Jun. 8, 2006, the entirety of which is hereby incorporated by reference. 
       BACKGROUND 
       [0002]    The present disclosure is related to a semiconductor device, more specifically, a semiconductor device including capacitors having high capacitance and method of fabricating the same. 
         [0003]    A method of realizing a high-capacity capacitor for an analogue circuit and radio frequency (RF) device requiring high-speed operation is being developed. In case the lower electrode and upper electrode of a capacitor are made of doped polysilicon, however, oxidation occurs in the interface between the lower electrode and the dielectric layer, and in the interface between the dielectric layer and the upper electrode, to form a natural oxide layer. This causes a decrease of capacitance. 
         [0004]    In an attempted solution to the above problem, a metal-insulator-metal (MIM) capacitor is introduced. An MIM capacitor has only a small, specific resistance and has no parasitic capacitance resulting from inner depletion. Therefore, the MIM capacitor is typically used in high-performance semiconductor devices. In addition, in an MIM capacitor it is relatively easy to control the capacitance, compared to a poly-insulator-poly (PIP) capacitor, and an MIM capacitor causes less difference in capacitance when varied according to frequency. Therefore, an MIM capacitor is widely used in analog-to-digital converters (ADC), high-frequency devices, switching capacitor filters, and CMOS image sensors, for example. 
         [0005]      FIG. 1A  illustrates a cross-sectional view showing a portion of a conventional MIM capacitor, and  FIG. 1B  illustrates a circuit diagram of the capacitor of  FIG. 1A . 
         [0006]    Referring to  FIG. 1A  and  FIG. 1B , a lower electrode  30  and an upper electrode  40  are disposed on a semiconductor substrate  10  having a bottom interconnection  26 . A dielectric  38  is interposed between the lower electrode  30  and the upper electrode  40 . A first insulation layer  28  is disposed between the lower electrode  30  and the semiconductor substrate  10 , and a second insulation layer  48  is disposed on the first insulation layer  28 . First, second and third top interconnections  52 ,  54  and  56  are disposed in the second insulation layer  48 . The first top interconnection  52  is electrically connected to the upper electrode  40  through a first contact  53 , and the second top interconnection  54  is electrically connected to the lower electrode  30  through a second contact  55 . The third top interconnection  56  is electrically connected to the bottom interconnection  26  through a third contact  57 . As shown in  FIG. 1B , the first top interconnection  52  is also electrically connected to a first external terminal A, and the second top interconnection  54  is electrically connected to a second external terminal B. The upper electrode  40  and the lower electrode  30  constitute a capacitor C 1  shown in  FIG. 1B . 
         [0007]    A capacitance above a predetermined level is required for stable operation of a semiconductor device. However much area the capacitor occupies decreases due to a continuous scaling down of the semiconductor device, thereby to cause a corresponding decrease of capacitance. Accordingly, a capacitor having a high capacitance in a limited area is demanded. 
       SUMMARY OF THE INVENTION 
       [0008]    Exemplary embodiments of the present invention are directed to semiconductor devices and methods of fabricating the same. In an exemplary embodiment of the present invention, a semiconductor device may comprise: a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate stacked sequentially on a semiconductor substrate with an insulation layer interposed between the first and second conductive plates, between the second and third conductive plates, and between tire third and fourth conductive plates, respectively, the first to fourth plates overlapping each other, wherein at least two of the first to fourth plates are electrically connected to each other and constitute at least two capacitors. 
         [0009]    In an exemplary embodiment, a semiconductor device may comprise: a semiconductor substrate having a first conductive plate; a second conductive plate disposed with a first insulation layer interposed on the first conductive plate; a third conductive plate disposed with a second insulation layer interposed on the second conductive plate; and a fourth conductive plate disposed with a third insulation layer interposed on the third conductive plate, wherein the first conductive plate and the third conductive plate are electrically connected to each other, and the second conductive plate and the fourth conductive plate are electrically connected to each other, and the first conductive plate and the second conductive plate constitute a first capacitor, the second conductive plate and the third conductive plate constitute a second capacitor, and the third conductive plate and the fourth conductive plate constitute a third capacitor. 
         [0010]    Also, in an exemplary embodiment, a semiconductor device may comprise: a semiconductor substrate having a first conductive plate; a second conductive plate disposed with a first insulation layer interposed on the first conductive plate; a third conductive plate disposed with a second insulation layer interposed on the second conductive plate; and a fourth conductive plate disposed with a third insulation layer interposed on the third conductive plate, wherein the first conductive plate, the third conductive plate, and the fourth conductive plate are electrically connected, and the first conductive plate and the second conductive plate constitute a first capacitor, and the second conductive plate and the third conductive plate constitute a second capacitor. 
         [0011]    In an exemplary embodiment, a semiconductor device may comprise: a semiconductor substrate having a first conductive plate; a second conductive plate disposed with a first insulation layer interposed on the first conductive plate; a third conductive plate disposed with a second insulation layer interposed on the second conductive plate; and a fourth conductive plate disposed with a third insulation layer interposed on the third conductive plate, wherein the first conductive plate, the second conductive plate, and the fourth conductive plate are electrically connected, and the second conductive plate and the third conductive plate constitute a first capacitor, and the third conductive plate and the fourth conductive plate constitute a second capacitor. 
         [0012]    In an exemplary embodiment, a method of fabricating a semiconductor device may comprise: preparing a semiconductor substrate on which are formed a first conductive plate, a first bottom interconnection electrically connected to the first conductive plate, and a second bottom interconnection insulated from the first conductive plate; forming a second conductive plate with a first insulation layer interposed on the first conductive plate; forming a third conductive plate with a second insulation layer interposed on the second conductive plate; forming a third insulation layer on the semiconductor substrate; performing an etch process to form a first groove and a second groove, the first groove exposing the second bottom interconnection and the second conductive plate, and the second groove exposing the first bottom interconnection and the third conductive plate; and filling the first groove with conductive material to form a fourth conductive plate on the third conductive plate, wherein the first conductive plate and the third conductive plate are electrically connected, and the second conductive plate and the fourth conductive plate are electrically connected. 
         [0013]    According to an exemplary embodiment, a method of fabricating a semiconductor device may comprise: preparing a semiconductor substrate on which are formed a first conductive plate, a first bottom interconnection electrically connected to the first conductive plate, and a second bottom interconnection insulated from, the first conductive plate; forming a second conductive plate with a first insulation layer interposed on the first conductive plate; forming a third conductive plate with a second insulation layer interposed on the second conductive plate; forming a third insulation layer on the semiconductor substrate; performing an etch process to form a first groove and a second groove, the first groove exposing the second bottom interconnection and the second conductive plate, and the second groove exposing die first bottom interconnection and the third conductive plate; and filling the first groove with conductive material to form a fourth conductive plate on the third conductive plate, wherein the first conductive plate, the third conductive plate and the fourth conductive plate are electrically connected. 
         [0014]    In an exemplary embodiment, a method of fabricating a semiconductor device may comprise: preparing a semiconductor substrate on which are formed a first conductive plate, a first bottom interconnection electrically connected to the first conductive plate, and a second bottom interconnection insulated from the first conductive plate; forming a second conductive plate with a first insulation layer interposed on the first conductive plate; forming a third conductive plate with a second insulation layer interposed on the second conductive plate; forming a third insulation layer on the semiconductor substrate; performing an etch process to form a first groove and a second groove, the first groove exposing the second bottom interconnection and the third conductive plate, and the second groove exposing the first bottom interconnection and the second conductive plate; and filling the first groove with conductive material to form a fourth conductive plate on the third conductive plate, wherein the first conductive plate, the second conductive plate and the fourth conductive plate are electrically connected. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    Exemplary embodiments of the present invention will be understood in more detail from the following descriptions taken in conjunction with the accompanying drawings. 
           [0016]      FIG. 1A  is a cross-sectional view of a semiconductor showing a conventional MIM capacitor, and  FIG. 1B  is a circuit diagram, of the capacitor shown in  FIG. 1A . 
           [0017]      FIG. 2  is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present invention. 
           [0018]      FIG. 3A  illustrates a cross-sectional view cut along line I-I′ of  FIG. 2 , and  FIG. 3B  is a circuit diagram of the capacitor shown in  FIG. 3A . 
           [0019]      FIG. 4A  is a cross-sectional view showing a semiconductor device of an exemplary embodiment of the present invention.  FIG. 4B  is a circuit diagram of the device shown in  FIG. 4A . 
           [0020]      FIG. 5  is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present invention. 
           [0021]      FIG. 6A  illustrates a cross-sectional view cut along line II-II′ of  FIG. 5 , and  FIG. 6B  is a circuit diagram of the device shown in  FIG. 6A . 
           [0022]      FIG. 7A  illustrates a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present invention, and  FIG. 7B  is a circuit diagram of the device shown in  FIG. 7A . 
           [0023]      FIG. 8  is a plan view showing a semiconductor device according to an exemplary embodiment of the present invention. 
           [0024]      FIG. 9A  illustrates a cross-sectional view cut along line III-III′ of  FIG. 8 , and  FIG. 9B  is a circuit diagram of the device shown in  FIG. 9A . 
           [0025]      FIG. 10A  illustrates a cross-sectional view of a semiconductor substrate showing a semiconductor device of an exemplary embodiment of the present invention, and  FIG. 10B  is a circuit diagram of the device shown in  FIG. 10A . 
           [0026]      FIG. 11  to  FIG. 14  illustrate cross-sectional views cut along the line I-I′ of  FIG. 2  to describe a method of fabricating a semiconductor device of an exemplary embodiment of the present invention. 
           [0027]      FIG. 15  to  FIG. 18  illustrate cross-sectional views cut along the line II-II′ of  FIG. 5  to describe a method of fabricating a semiconductor device of an exemplary embodiment of the present invention. 
           [0028]      FIG. 19  to  FIG. 22  illustrate cross-sectional views cut along the line III-III′ of  FIG. 8  to describe a method of fabricating a semiconductor device of an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0029]    Exemplary embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those of ordinary skill in the art. Like numbers refer to like elements throughout. 
         [0030]      FIG. 2  illustrates a plan view showing a semiconductor device according to an exemplary embodiment of the present invention.  FIG. 3A  illustrates a cross-sectional view cut along line I-I′ of  FIG. 2  and  FIG. 3B  is a circuit diagram of the device shown in  FIG. 5A . 
         [0031]    Referring to  FIG. 2 .  FIG. 3A , and  FIG. 3B , a second conductive plate  130 , a third conductive plate  150  and a fourth conductive plate  140  are sequentially disposed on a semiconductor substrate  110  having a first conductive plate  120 . The first conductive plate to the fourth conductive plate,  120 ,  130 ,  140  and  150 , overlap with each other. A first insulation layer  128  is interposed between the first conductive plate  120  and the second conductive plate  130 , a second insulation layer  138  is interposed between the second conductive plate  130  and the third conductive plate  140 , and a third insulation layer  148  is interposed between the third conductive plate  140  and the fourth conductive plate  150 . 
         [0032]    The first conductive plate  120  and the fourth conductive plate  150  may be made of metal, such as copper, and the second conductive plate  130  and the third conductive plate  140  may be made of metal, such as Ti, TiN and TaN. 
         [0033]    The first insulation layer  128  may function to prevent a metal from diffusing, and it may be made of a material, such as SiN, SiC or SiCN. The second insulation layer  138  may include a high-K dielectric material to increase its capacitance. The third insulation layer  148  is an interlayer dielectric or an inter-metal dielectric made of a material, such as SiO 2 , SiOF or SiOC. A further insulation, layer (not shown) made of the same material as the first insulation layer  128  may be interposed between the third conductive layer  140  and the third insulation layer  148 . 
         [0034]    The semiconductor substrate  110  may include a first bottom interconnection  122 , a second bottom interconnection  124  and a third bottom interconnection  126 . The first, second and third bottom interconnections  122 ,  124 , and  126  may be electrically connected to a transistor or an interconnection (not shown) placed under them. The first bottom interconnection  122  is electrically connected to the first conductive plate  120 , and the second and the third bottom interconnections  124  and  126  are insulated from the first conductive plate  120 . 
         [0035]    A first top interconnection  152 , a second top interconnection  154  and a third top interconnection  156  may be disposed in the third insulation layer  148  on the semiconductor substrate  110 . The first, second and third top interconnections  152 ,  154 , and  156  may be electrically connected to external terminals A and B, shown in  FIG. 3B , that supply signal power to the semiconductor substrate. The first top interconnection  152  is electrically connected to the fourth conductive plate  150 . And the second and the third top interconnections  154  and  156  are insulated from the fourth conductive plate  150 . 
         [0036]    The second bottom interconnection  124  and the first top interconnection  152 , the first bottom interconnection  122  and the second top interconnection  154 , and the first bottom interconnection  126  and the third top interconnection  156  are respectively electrically connected through a first contact  153 , a second contact  155 , and a third contact  157 . Also, a second conductive plate  130  is electrically connected to the first contact  153 , and a third conductive plate  140  is electrically connected to the second contact  155 . Accordingly, the second conductive plate  130  and the fourth conductive plate  150  are electrically connected to each other, and the first conductive plate  150  and the third conductive plate  140  are electrically connected to each other. Also, the second conductive plate  130  and the fourth conductive plate  150  are electrically connected to the first external terminal A through the first top interconnection  152 , and the first conductive plate  120  and the third conductive plate  140  are electrically connected to the second external terminal B through the second top interconnection  154 . 
         [0037]    The first to a fourth conductive plates  120 ,  130 ,  140  and  150  constitute three capacitors. The second conductive plate  130  and the third conductive plate  140 , the third conductive plate  140  and the fourth conductive plate  150 , and the first conductive plate  120  and the second conductive plate  130  respectively constitute a first capacitor C 1 , a second capacitor C 2 , and a third capacitor C 3 , shown in  FIG. 3B . In other words, the first conductive plate  120  becomes a bottom electrode of the third capacitor C 3 , the second conductive plate  130  becomes a bottom electrode of the second capacitor C 2 , the third conductive plate  140  becomes a bottom electrode of the second capacitor C 2 , and the fourth conductive plate  150  becomes atop electrode of the second capacitor C 2 . 
         [0038]    According to this exemplary embodiment, four conductive plates may constitute three capacitors connected in parallel. As a result, the semiconductor device may have capacitors having high capacitance. In case the second insulation layer is comprised of high-K dielectrics, the capacitance may be increased further. 
         [0039]      FIG. 4A  illustrates a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present invention.  FIG. 4B  is a circuit diagram of the device shown in  FIG. 4A . 
         [0040]    Referring to  FIGS. 4A and 4B , a fifth, a sixth and a seventh conductive plate  130 ′,  140 ′ and  150 ′ may be disposed in the same construction with the construction of the second, third and fourth conductive plates  130 ,  140  and  150  formed on the substrate  110 . Also, a fourth to a sixth insulation layer  128 ′,  138 ′ and  148 ′ interposed between the fifth to the seventh conductive plates  130 ′,  140 ′ and  150 ′ may be further disposed in the same construction with the construction of the first to the third insulation layers  128 ,  138  and  148 . 
         [0041]    The fifth conductive plate  130 ′ and the sixth conductive plate  140 ′ are made of metal, such as Ti, TIN and TaN. The seventh conductive plate  150 ′ may be made of metal such as copper. 
         [0042]    The fourth insulation layer  128 ′ may function to prevent the metal from being diffused, and it may be made of a material, such as SiN, SiC and/or SiCN. The fifth insulation layer  138 ′ may include a high-K dielectric material to increase capacitance. The sixth insulation layer  148 ′ is an interlayer dielectric or inter-metal dielectric, and may be made of a material, such as SiO, SiOF and/or SiOC. An insulation layer made of the same material as the fourth insulation layer  128 ′ may be farther interposed between the sixth conductive plate  140 ′ and the sixth insulation layer  148 ′. 
         [0043]    A fourth top interconnection  152 ′, a fifth top interconnection  154 ′ and a sixth top interconnection  156 ′ may be disposed in the sixth insulation layer  148 ′. The fourth to sixth top interconnections  152 ′,  154 ′ and  156 ′ may be respectively electrically connected to external terminals A and B, shown in  FIG. 4B , that supply signal power to the semiconductor substrate. The fourth top interconnection  152 ′ is electrically connected to the seventh conductive plate  150 ′, and the fifth and the sixth top interconnections  154 ′ and  156 ′ are insulated from the seventh conductive plate  150 ′. 
         [0044]    The first top interconnection  152  and the fourth top interconnection  152 ′, the second top interconnection  154  and the fifth top interconnection  154 ′, and the third top interconnection  156  and the sixth top interconnection  156 ′ are respectively electrically connected through a fourth contact  153 ′, a fifth contact  155 ′ and a sixth contact  157 ′. Also, the fifth conductive plate  130 ′ is electrically connected to the fourth contact  153 ′, and the sixth conductive plate  140 ′ is electrically connected to the fifth conductive plate  130 ′. Accordingly, the second conductive plate  130 , the fourth conductive plate  150 , the fifth conductive plate  130 ′, and the seventh conductive plate  150 ′ are electrically connected. And the first conductive plate  120 , the third conductive plate  150 , and the sixth conductive plate  140 ′ are electrically connected. Also, the second conductive plate  130 , the fourth conductive plate  150 , the fifth conductive plate  130 ′, and the seventh conductive plate  150 ′ are electrically connected to the first external terminal A through the fourth top interconnection  152 ′, and the first conductive plate  120 , the third conductive plate  150 , and the sixth conductive plate  140  are electrically connected to the second external terminal B through the fifth top interconnection  154 ′. 
         [0045]    The first to seventh conductive plates  120 ,  130 ,  140 ,  150 ,  130 ′,  140 ′ and  150 ′ constitute five capacitors. The first to the fourth conductive plates  120 ,  130 ,  140  and  150  constitute three capacitors, as shown in  FIG. 38 . In addition, the fifth conductive plate  130 ′ and the sixth conductive plate  140 ′, and the sixth conductive plate  140 ′ and the seventh conductive plate  140 ′ respectively further constitute a fourth capacitor C 1 ′ and a fifth capacitor C 2 ′. In other words, the fifth conductive plate  130 ′ becomes a bottom electrode of the fourth capacitor C 1 ′. The sixth conductive plate  140 ′ becomes a top electrode of the fourth capacitor C 1 ′ and becomes a bottom electrode of the fifth capacitor C 2 ′. The seventh conductive plate  150 ′ becomes a top electrode of the fifth capacitor C 2 ′. 
         [0046]    According to this exemplary embodiment, seven conductive plates may constitute five capacitors connected in parallel. As a result, the semiconductor device may include capacitors having high capacitance. In case the second insulation layer and the fifth insulation layer are formed of high-K dielectric material, the capacitance may be further increased. Also, the semiconductor device of the exemplary embodiment of the present invention may further include conductive plates disposed repeatedly in the same construction with the construction of the fifth to tire seventh conductive plates. 
         [0047]      FIG. 5  illustrates a plan view showing briefly a semiconductor device according to an exemplary embodiment of the present invention.  FIG. 6A  illustrates a cross-sectional view cut along the line II-II′ of  FIG. 5 . And  FIG. 6B  is a circuit diagram of the device shown in  FIG. 6A . 
         [0048]    Referring to  FIG. 5 ,  FIG. 6A , and  FIG. 6B , a second conductive plate  230 , a third conductive plate  240 , and a fourth conductive plate  250  are respectively disposed on a semiconductor substrate  210  having a first conductive plate  220  formed thereon. The first to fourth conductive plates  220 ,  230 ,  240  and  250  overlap with each other. A first insulation layer  228  is interposed between the first conductive plate  220  and the second conductive plate  230 , a second insulation layer  238  is interposed between the second conductive plate  230  and the third conductive plate  240 , and a third insulation layer  248  is interposed between the third conductive plate  240  and the fourth conductive plate  250 . 
         [0049]    The first conductive plate  220  and the fourth conductive plate  250  may be made of metal, such as copper, and the second conductive plate  230  and the third conductive plate  240  may be made of metal, such as Ti, TiN, and/or TaN. 
         [0050]    The first insulation layer  228  may function to prevent the metal material from diffusing, and it may be made of material such as SiN, SiC, and/or SiCN. The second insulation layer  238  may include high-K dielectric material to increase capacitance. The third insulation layer  248  is an interlayer dielectric or an inter-metal dielectric, and may be made of SiO 1 , SiOF and/or SiOC. A further insulation layer (not shown) made of the same material as the first insulation layer  228  may be interposed between the third conductive plate  240  and the third insulation layer  248 . 
         [0051]    The semiconductor substrate  210  may include a first bottom interconnection  222 , a second bottom interconnection  224 , and a third bottom interconnection  226 . The first to third bottom interconnections  222 ,  224  and  226  may be electrically connected to a transistor or an interconnection placed in the semiconductor substrate under them. The first bottom interconnection  222  is electrically connected to the first conductive plate  220 , and the second and the third bottom interconnections  224  and  226  are insulated from the first conductive plate  120 . 
         [0052]    A first top interconnection  252 , a second top interconnection  254  and a third top interconnection  256  are disposed in the third insulation layer  248 . The first to third top interconnections  252 ,  254  and  256  may be electrically connected to external terminals A and B, shown in  FIG. 6B , that supply signal power to the semiconductor substrate. The first top interconnection  252  is electrically connected to the fourth conductive plate  250 , and the second and the third top interconnections  254  and  256  are insulated from the fourth conductive plate  250 . 
         [0053]    The second bottom interconnection  224  and the second top interconnection  254 , the first bottom interconnection  222  and the first top interconnection  252 , and the third bottom interconnection  226  and the third top interconnection  256  are respectively electrically connected through a first contact  253 , a second contact  155 , and a third contact  257 . Also, a second conductive plate  230  is electrically connected to the first contact  253 , and a third conductive plate  240  is electrically connected to the second contact  155 . Accordingly, the first conductive plate  220 , the third conductive plate  240 , and the third conductive plate  240  are electrically connected to each other. Also, the first conductive plate  220 , the third conductive plate  240  and the fourth conductive plate  250  are electrically connected to a first external terminal A through the first top interconnection  252 , and the second conductive plate  230  is electrically connected to a second external terminal B through the second top interconnection  254 . 
         [0054]    The first to fourth conductive plates  220 ,  230 ,  240  and  250  constitute two capacitors. The second conductive plate  230  and the third conductive plate  240 , and the first conductive plate  220  and the second conductive plate  230  respectively constitute a first capacitor C 1  and a second capacitor C 2 . Namely, the first conductive plate  220  becomes a bottom electrode of the second capacitor C 2 , the second conductive plate  230  becomes a top electrode of the second capacitor C 2  and a bottom electrode of the first capacitor C 1 . The third conductive plate  240  becomes a top electrode of the first capacitor C 1 . 
         [0055]    According to this exemplary embodiment, four conductive plates may constitute two capacitors connected in parallel. As a result, the semiconductor device may have capacitors having high capacitance. In case the second insulation layer is formed of high-K dielectric material, the capacitance may be further increased. 
         [0056]      FIG. 7A  illustrates a cross-sectional view of the semiconductor substrate showing a semiconductor device according to an exemplary embodiment of the present invention, and  FIG. 7B  is a circuit diagram of the device shown in  FIG. 7A . 
         [0057]    Referring to  FIG. 7A  and  FIG. 7B , the fifth to the seventh conductive plates  230 ′,  240 ′ and  250 ′ may be disposed in the same construction as the construction of the second to the fourth conductive plates  230 ,  240 , and  250  formed on the substrate  210  of  FIG. 6A . Also, a fourth to a sixth insulation layer  118 ′,  238 ′, and  248 ′ interposed between the fifth to the seventh conductive plates  230 ′,  240 ′, and  250 ′ may be disposed in the same construction as the first to the third insulation layers  228 ,  238 , and  248 . 
         [0058]    The fifth conductive plate  230 ′ and the sixth conductive plate  240 ′ may be made of metal, such as Ti, TiN and/or TaN. The seventh conductive plate  250 ′ may be made of metal, such as copper. 
         [0059]    The fourth insulation layer  228 ′ may function to prevent the metal material from diffusing and may be made of a material, such as SiN, SiC and/or SiCN. The fifth insulation layer  238 ′ may include a high-K dielectric material to increase capacitance. The sixth insulation layer  248 ′ is an interlayer dielectric or an inter-metal insulation layer and may be made of a material, such as SiO, SiOF and/or SiOC. A further insulation layer (not shown) made of the same material as the fourth insulation layer  228 ′ may he interposed between the sixth conductive plate  240 ′ and the sixth insulation layer  248 ′. 
         [0060]    A fourth top interconnection  252 ′, a fifth top interconnection  254 ′, and a sixth top interconnection  256 ′ may be disposed in the insulation layer  248 ′. The fourth to tire sixth insulation layers  252 ′,  254 ′ and  256 ′ may be respectively electrically connected to external terminals A and B, shown in  FIG. 7B , that supply signal power to the semiconductor substrate. The fourth top interconnection  252 ′ is electrically connected to the seventh conductive plate  250 ′, and the fifth and the sixth top interconnection  254 ′ and  256 ′ are insulated from the seventh conductive plate  250 ′. 
         [0061]    The second top interconnection  254  and the fifth top interconnection  254 ′, the first top interconnection  254  and the fourth top interconnection  252 ′, and the third top interconnection  256  and the sixth top interconnection  256 ′ are respectively electrically connected through a fourth contact  253 ′, a fifth contact  255 ′, and a sixth contact  257 ′, Also, the fifth conductive plate  230 ′ is electrically connected to the fourth contact  253 ′, and tire sixth conductive plate  240 ′ is electrically connected to the fifth contact  255 ′. Accordingly, the first conductive plate  220 , the third conductive plate  240 , the fourth conductive plate  250 , the sixth conductive plate  240 ′ and the seventh conductive plate  250 ′ are electrically connected, and the second conductive plate  230  and the fifth conductive plate  230 ′ are electrically connected. Also, the first conductive plate  220 , the third conductive plate  240 , the fourth conductive plate  250 , the sixth conductive plate  240 ′ and the seventh conductive plate  250 ′ are electrically connected to the first external terminal A through the fourth top interconnection  252 ′. The second conductive plate  230  and the fifth conductive plate  230 ′ are electrically connected to the second external terminal B through the fifth top interconnection  254 ′. 
         [0062]    The first to the seventh conductive plates  220 ,  230 ,  240 ,  250 ,  230 ′,  240 ′ and  250 ′ constitute four capacitors. The first to fourth plates  220 ,  230 ,  240  and  250  constitute two capacitors, as shown in  FIG. 6B . In addition, in this exemplary embodiment, the fifth conductive plate  230 ′ and the sixth conductive plate  240 ′ further constitute a third capacitor C 1 ′, and the fourth conductive plate  250  and the fifth conductive plate  230 ′ constitute a fourth capacitor C 2 ′. More specifically, the fourth conductive plate  250  becomes the bottom electrode of the fourth capacitor C 2 ′, the fifth conductive plate  230 ′ becomes the bottom electrode of the third capacitor C 1 ′, and the sixth conductive plate  240 ′ becomes the top electrode of the third capacitor C 1 ′. 
         [0063]    According to this exemplary embodiment, seven conductive plates constitute four capacitors connected in parallel. Therefore, the semiconductor device may include capacitors having high capacitance. In case the second insulation layer and the fifth insulation layer are formed, of high-K dielectric material, the capacitance may be further increased. Also, a semiconductor device according an exemplary embodiment of the present invention may further include conductive plates disposed repeatedly in the same construction as the construction of the fifth to the seventh conductive plates. 
         [0064]      FIG. 8  is a plan view showing a semiconductor device according to an exemplary embodiment of the present invention.  FIG. 9A  illustrates a cross-sectional view cut along the line III-III′ of  FIG. 8 , and  FIG. 9B  is a circuit diagram of the device shown in  FIG. 9A . 
         [0065]    Referring to  FIG. 8 ,  FIG. 9A  and  FIG. 9B , a second conductive plate  330 , a third conductive plate  340 , and a fourth conductive plate  350  are respectively disposed on the semiconductor substrate  310  having a first conductive plate  320 . The first to the fourth conductive plates  320 ,  330 ,  340 , and  350  overlap with each other. A first insulation layer  328  is interposed between the first conductive plate  320  and the second conductive plate  330 , a second insulation layer  338  is interposed between the first and the third conductive plates  330  and  340 , and a third insulation layer  348  is interposed between the third and the fourth conductive plates  340  and  350 . 
         [0066]    The first and tire fourth conductive plates  320  and  350  may be made of metal such as copper, and the second and the third conductive plates  330  and  340  may be made of metal such as Ti, TiN and TaN. 
         [0067]    The first insulation layer  328  may function to prevent the metal from diffusing, and it may be made of a material such as SiN, SiC or SiCN. The second insulation layer  338  may include a high-K dielectric material to increase capacitance. The third insulation layer  348  is an interlayer dielectric or an inter-metal dielectric, made of a material such as SiO 1 , SiOF or SiOC. A further insulation layer (not shown) made of the same material as the first insulation layer  328  may be interposed between the third conductive layer  340  and the third insulation layer  348 . 
         [0068]    The semiconductor substrate  310  may include a first bottom interconnection  322 , a second bottom interconnection  324 , and a third bottom interconnection  326 . The first to third bottom interconnections  322 ,  324 , and  326  may be electrically connected to a transistor or an interconnection located in the semiconductor substrate  310  under them. The first bottom interconnection  322  is electrically connected to the first conductive plate  320 , and the second and third bottom interconnection  324  and  326  are insulated from the first conductive plate  320 . 
         [0069]    A first top interconnection  352 , a second top interconnection  354 , and a third top interconnection  356  may be disposed in the third insulation layer  348 . The first, second and third top interconnections  352 ,  354 , and  356  may be electrically connected to external terminals A and B, shown in  FIG. 9B , that supply signal power to the semiconductor substrate. The first top interconnection  352  is electrically connected to the fourth conductive plate  350 . And the second and the third top interconnections  354  and  356  are insulated from the fourth conductive plate  350 . 
         [0070]    The second bottom interconnection  324  and the second top interconnection  354 , the first bottom interconnection  322  and the first top interconnection  352 , and the third bottom interconnection  326  and the third top interconnection  356  are respectively electrically connected through a first contact  353 , a second contact  355 , and a third contact  357 . Also, a third conductive plate  340  is electrically connected to the first contact  353 , and a second conductive plate  330  is electrically connected to the second contact  355 . Accordingly, the first conductive plate  320 , the second conductive plate  330 , and the fourth conductive plate  350  are electrically connected. Also, the first, second, and fourth conductive plates  320 ,  330 , and  350  are electrically connected to the first external terminal A through the first top interconnection  352 , and the third conductive plate  340  is electrically connected to the second external terminal B through the second top interconnection  354 . 
         [0071]    The first to fourth conductive plates  320 ,  330 ,  340 , and  350  constitute two capacitors. The second conductive plate  330  and the third conductive player  340 , the third conductive plate  340  and the fourth conductive plate  350 , respectively constitute a first capacitor C 1  and a second capacitor C 2 . In other words, the second conductive plate  330  becomes a bottom electrode of the first capacitor Cl, the third conductive plate  340  becomes a top electrode of the first capacitor C 2 , and it becomes a bottom electrode of the second capacitor C 2 , and the fourth conductive plate  350  becomes a top electrode of the second capacitor C 2 . 
         [0072]    According to this exemplary embodiment, four conductive plates may constitute two capacitors connected in parallel. As a result, the semiconductor device may have capacitors having high capacitance. In case the second insulation layer is formed, of high-K dielectric material, the capacitance may be increased further. 
         [0073]      FIG. 10A  illustrates a cross-sectional view of a semiconductor substrate showing a semiconductor device according to an exemplary embodiment of this invention.  FIG. 10B  is a circuit diagram of the device shown in  FIG. 10A . 
         [0074]    Referring to  FIG. 10A  and  FIG. 10B , the fifth to the seventh conductive plates  330 ′,  340 ′ and  350 ′ may be disposed in the same construction as the construction of the second to the fourth conductive plates  330 ,  340 , and  350  on the substrate  310  shown in  FIG. 6A . Also, a fourth to a sixth insulation layer  318 ′,  338 ′ and  348 ′ interposed between the fifth to the seventh conductive plates  330 ′,  340 ′ and  350 ′ may be disposed in the same construction as the first to third insulation layers  328 ,  338 , and  348 . 
         [0075]    The fifth and the sixth conductive plates  330 ′ and  340 ′ may be made of metal, such as Ti, TiN and/or TaN. The seventh conductive plate  350 ′ may be made of metal, such as copper. 
         [0076]    The fourth insulation layer  328 ′ may function to prevent the metal material from diffusing and may be made of material, such as SiN, SiC and/or SiCN. The fifth insulation layer  338 ′ may include a high-K dielectric material to increase capacitance. The sixth insulation layer  348 ′ is an interlayer dielectric or an inter-metal insulation layer and may be made of material, such as SiO, SiOF and/or SiOC. A further insulation layer (not shown) made of the same material as the fourth insulation layer  328 ′ may be interposed between the sixth conductive plate  340 ′ and the sixth insulation layer  348 ′. 
         [0077]    A fourth top interconnection  352 ′, a fifth top interconnection  354 ′, and a sixth top interconnection  356 ′ may he disposed in the sixth insulation layer  348 ′. The fourth to sixth top interconnections  352 ′,  354 ′ and  356 ′ may be respectively electrically connected to external terminals A and B, shown in  FIG. 10B , that supply signal power to the semiconductor substrate. The fourth top interconnection  352 ′ is electrically connected to the seventh conductive plate  350 ′, and the fifth and sixth top interconnections  354 ′ and  356 ′ are insulated from the seventh conductive plate  350 ′. 
         [0078]    The second top interconnection  354  and the fifth top interconnection  354 ′, the first top interconnection  352  and the fourth top interconnection  352 ′, and the third top interconnection  356  and the sixth top interconnection  356 ′ are respectively electrically connected through a fourth contact  353 ′, a fifth contact  355 ′, and a sixth contact  357 ′. Also, the fifth conductive plate  330 ′ is electrically connected to the fifth contact  355 ′, and the sixth conductive plate  340 ′ is electrically connected to the fourth contact  353 ′. Accordingly, the first conductive plate  320 , the third conductive plate  330 , the fourth conductive plate  350 , the fifth conductive plate  330 ′, and the seventh conductive plate  350 ′ are electrically connected. The third conductive plate  340  and the sixth conductive plate  340 ′ are electrically connected. Also, the first conductive plate  320 , the second conductive plate  330 , the fourth conductive plate  350 , the fifth conductive plate  330 ′ and the seventh conductive plate  350 ′ are electrically connected to the first external terminal A through the fourth top interconnection  352 ′. The third and the fifth conductive plates  340  and  340 ′ are electrically connected to the second external terminal B through the fifth top interconnection  354 ′. 
         [0079]    The first to seventh conductive plates  320 ,  330 ,  340 ,  350 ,  330 ′,  340 ′ and  350 ′ constitute four capacitors. The first, to fourth plates  320 ,  330 ,  340  and  350  constitute two capacitors, as shown in  FIG. 9B . In addition, in this exemplary embodiment, the fifth conductive plate  330 ′ and the sixth conductive plate  340 ′ further constitute a third capacitor C 1 ′, and the sixth conductive plate  340 ′ and the seventh conductive plate  350 ′ constitute a fourth capacitor C 2 ′. More specifically, the fifth conductive plate  330 ′ becomes the bottom electrode of the third capacitor C 1 ′, the sixth conductive plate  340 ′ becomes the top electrode of the third capacitor C 1 ′, and the sixth conductive plate  240 ′ becomes the top electrode of the third capacitor C 1 ′, 
         [0080]    According to this exemplary embodiment, seven conductive plates constitute four capacitors connected in parallel. Therefore, the semiconductor device may include capacitors having high capacitance. In case the second insulation layer and the fifth insulation layer are a high-K dielectric material, the capacitance may be further increased. Also, a semiconductor device according to an exemplary embodiment of the present invention may further include conductive plates disposed repeatedly in the same construction as the construction of the fifth to the seventh conductive plates. 
         [0081]    in the above-described exemplary embodiments, the conductive plates and the interconnections may further include a barrier metal layer capable of preventing the metal from being diffused. 
         [0082]      FIGS. 11 to 14  illustrate cross-sectional view cut along the line I-I′ of  FIG. 2  to describe a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention. 
         [0083]    Referring to  FIGS. 2 and 11 , a first insulation layer  128  is formed on the semiconductor substrate  110  where a first conductive plate  120  and a first to third bottom interconnections  122 ,  124 , and  126  are formed. The semiconductor substrate may include an active device, such as transistor. The first conductive plate  120  and the first to third bottom interconnections  122 ,  124 , and  126  may be made of metal, such as copper. The first insulation layer  128  may be made of a material, such as SiN, SiC, and/or SiCN, which is capable of preventing metal from being diffused. A second conductive plate  130  is formed so that it overlaps with the first conductive plate  120  on the first insulation layer  128  and may be made of metal such as Ti, TiN, and/or TaN, 
         [0084]    Referring to  FIGS. 2 and 12 , a second insulation layer  138  and a third conductive plate  140  are formed on the second conductive plate  130 . The second insulation layer  138  may be made of a silicon insulation layer, such as SiO 2 , SiN, and/or SiON or a metal insulation layer such as Ta 2 O 5 , HfO, Al 2 O 3 . A high-k dielectric material may be used in order to increase capacitance. The third conductive plate  140  is formed so that it overlaps the second conductive plate  130 , and may be made of metal such as Ti, TiN or TaN. 
         [0085]    Referring to  FIGS. 2 and 13 , a third insulation layer  148  is formed on the entire surface of a semiconductor substrate  110 . The third insulation layer  148  may be made of SiO 2 , SiOF or SiOC. The third insulation layer  148  may be referred to as an interlayer dielectric or an inter-metal dielectric. Before forming the third insulation layer  148 , an insulation layer (not shown) that functions to prevent metal from being diffused may further be formed on the conductive plate  140 . 
         [0086]    After that, an etch process is performed to form, a plate-type groove  160 , line-type grooves  162 ,  164 , and  166 , and first to third contact holes  163 ,  165  and  167 . A second bottom interconnection  124  and a second conductive plate  130  are exposed through the first contact hole  163 . A bottom interconnection  122  and a third conductive plate  140  are exposed through the second contact hole  165 , and a third bottom interconnection  126  is exposed through the third contact hole  167 . During the etching process, the first to the third bottom interconnections  122 ,  124  and  126  may function as etch stop layers. Accordingly, over etching may be prevented in the etch process, and short circuits between the bottom interconnections and/or between bottom interconnection and other interconnections placed under them may be prevented. In other words, the capacitors may be formed stably. 
         [0087]    Referring to  FIG. 2  and  FIG. 14 , grooves  160 ,  162 .  164  and  166  and the first to third contact holes  1 . 53 ,  155  and  157  may be filled with metal to form first to third top interconnections  152 ,  154  and  156 , and form first to third contacts  153 ,  155  and  157 . The method to form interconnections by filling metal material in an etched insulation layer may be referred to as the damascene process. Material such as copper may be used for the metal material. 
         [0088]    A second bottom interconnection  124 , a second conductive plate  130 , a first top interconnection  152 , and a fourth conductive plate  150  are electrically connected through the first contact  153 . Also, a first conductive plate  120 , a third conductive plate  140 , and a second top interconnection  154  are electrically connected through the second contact  155 . Even though the first and the second contacts  153  and  155  are made of copper, if the second and the third conductive plates  130  and  140  are made of Ti, TIN, or TaN, it is possible to prevent the copper included in the first and the second contacts  153  and  155  from being diffused into the second and the third conductive plates  130  and  140 . A third bottom interconnection  126  and a third top interconnection  156  may be electrically connected through the third contact  157 . 
         [0089]      FIGS. 15 to 18  illustrate cross-sectional views cut along the line II-II′ of  FIG. 5  to describe a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention. 
         [0090]    Referring to  FIG. 5  and  FIG. 15 , a first insulation layer  228  is formed on a semiconductor substrate  210  where first to third bottom interconnections  222 ,  224 , and  226  are formed. The second conductive plate  230  is formed so that it overlaps with the first conductive plate  220  on the first insulation layer  228 . 
         [0091]    Referring to  FIG. 5  and  FIG. 16 , a second insulation layer  238  and a third conductive plate  240  are formed on the second conductive plate  230 . The second insulation layer  238  may be made of a high-K dielectric material in order to increase capacitance. The third conductive plate  240  is formed so that it overlaps with the second conductive plate  230 . 
         [0092]    Referring to  FIG. 5  and  FIG. 17 , a third insulation layer  248  is formed on the entire surface of the semiconductor substrate  210 . Before forming the third insulation layer  248 , an insulation layer (not shown) that functions to prevent metal from being diffused, such as the first insulation layer  128 , may further be formed on the third conductive plate  240 . 
         [0093]    Subsequently, an etching process is performed to form a plate-type groove  260 , line-type grooves  262 ,  264 , and  266 , and first to third contact holes  263 ,  265 , and  267 . A second bottom interconnection  224  and a second conductive plate  230  are exposed through the first contact hole  263 . A bottom interconnection  222  and a third conductive plate  240  are exposed through the second contact hole  265 , and a third bottom interconnection  226  is exposed through the third contact hole  267 . During the etch process, the first to the third bottom interconnections  222 ,  224  and  226  may function as etch stop layers. 
         [0094]    Referring to  FIG. 5  and  FIG. 18 , grooves  260 ,  262 ,  264 , and  266  and the first to third contact holes  253 ,  255 , and  257  are filled with metal to form a fourth conductive plate  250 , first to third top interconnections  252 ,  254  and  256 , and form first to third contacts  253 ,  255  and  257 . 
         [0095]    A second bottom interconnection  224 , a second conductive plate  230 , and a second top interconnection  254  are electrically connected through the first contact  253 . Also, a first conductive plate  220 , a third conductive plate  240 , a first top interconnection  252  and a fourth conductive plate  250  are electrically connected through the second contact  255 . A third bottom, interconnection  226  and a third top interconnection  256  are electrically connected through the third contact  257 . 
         [0096]      FIG. 19  to  FIG. 22  illustrate cross-sectional views cut along the line III-III′ of  FIG. 8  to describe a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention. 
         [0097]    Referring to  FIG. 8  and  FIG. 19 , a first insulation layer  328  is formed on a semiconductor substrate  310  where a first conductive plate  320  and first to third bottom interconnections  322 ,  324  and  326  are formed. A second conductive plate  330  is formed so that it overlaps with the first conductive plate  320  on the first insulation layer  328 . 
         [0098]    Referring to  FIG. 8  and  FIG. 20 , a second insulation layer  338  and a third conductive plate  340  are formed on the second conductive plate  330 . The second insulation layer  338  may be made of a high-K dielectric material in order to increase capacitance. The third conductive plate  340  is formed, so that it overlaps with the second conductive plate  330 . 
         [0099]    Referring to  FIG. 8  and  FIG. 21 , a third insulation layer  348  is formed on the entire surface of a semiconductor substrate. Before forming the third insulation layer  348 , an insolation layer (not shown) functioning to prevent metal from being diffused, like the first insulation layer  128 , may further be formed on the third conductive plate  140 . 
         [0100]    Next, an etch process is performed to form a plate-type groove  360 , line-type grooves  362 ,  365 , and  367 , and first to third contact holes  363 ,  365  and  367 . A second bottom interconnection  324  and a third conductive plate  340  are exposed through the first contact hole  363 . A bottom interconnection  322  and a second conductive plate  330  are exposed through the second contact hole  365 , and a third bottom interconnection  326  is exposed through the third contact hole  367 . During the etch process, the first to the third bottom interconnections  322 ,  324 , and  326  may function as etch stop layers. 
         [0101]    Referring to  FIG. 8  and  FIG. 22 , grooves  360 ,  362 ,  364 , and  366  and the first to third contact holes  353 ,  355 , and  357  are filled with metal to form a fourth conductive plate  350 , and first to third top interconnections  352 ,  354  and  356  and to form first to third contacts  353 ,  355  and  357 . 
         [0102]    A second bottom interconnection  324 , a third conductive plate  340 , and a second conductive plate  340  are electrically connected through the first contact  353 . Also, a first conductive plate  320 , a second conductive plate  330 , a first top interconnection  352 , and a fourth conductive plate  350  are electrically connected through the second contact  355 . A third bottom interconnection  326  and a third top interconnection  356  may be electrically connected through the third bottom interconnection  326 . 
         [0103]    In the above-described exemplary embodiments, before or after forming the conductive plates and interconnections, a barrier metal layer that prevents metal of the conductive plates and interconnections from being diffused may further be formed. 
         [0104]    Although the present invention has been described in connection with the exemplary embodiments illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those of ordinary skill in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention. 
         [0105]    According to exemplary embodiments of the present invention, the semiconductor device may include capacitors having high capacitance. 
         [0106]    According to exemplary embodiments of the present invention, the capacitors may be formed stably.