Abstract:
A method and apparatus for packaging microprocessors and memory devices on a single silicon substrate is described. Microprocessors and memory devices are placed on both sides of the silicon substrate. Through holes are formed in the substrate to connect the microprocessor and memory devices together. By packaging the microprocessor and memory element this way, the propagation length between the memory and the microprocessors is shortened, and timing skews are minimized, and data transmission speed is increased. In addition, additional active and passive circuits and/or components can also be fabricated in one or both sides of the silicon substrate.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a packaging for holding both microprocessors and memory chips, which increases data access speed and minimizes timing skews by arranging the microprocessors and their associated memories in close proximity to one another. 
     2. Description of the Related Art 
     Microprocessors and memory chips are an essential part of almost every computer today. The speed at which a computer performs operations is partially dependent on the speed at which information is transferred between its microprocessor and the memory. There is an ever-increasing need for faster operating computers. By decreasing the time it takes for a microprocessor to access data contained within the memory units, the operating speed of the computer can be increased. 
     Microprocessors and memories operate in what is called a master-slave relationship. That is, the microprocessor essentially directs the memory operation. This is accomplished through a common bus which connects the microprocessor to the memory. The bus is nothing more than a collection of lines which connect to both the memory and the microprocessor. When a computer seeks to read information from, or write information to, the memory, the address of the particular memory location or locations is placed on the bus and transmitted to the memory. Then, if the microprocessor is reading from the memory, the information stored in the selected locations is transmitted over the bus lines to the microprocessor. If the microprocessor is writing to the memory, information travels from the microprocessor and is stored in the selected memory location(s). 
     Various types of memories are used in today&#39;s computers. Dynamic Random Access Memories (DRAMs) store information dynamically in the form of a stored charge on a capacitor. Since the charge stored on the capacitor has a tendency to leak away over time, the charge must be constantly refreshed. DRAM technology is conventional in the art and is explained in U.S. Pat. No. 4,081,701 to White Jr. et al., which is herein incorporated by reference. DRAMs are beneficial because they provide more input/output (I/O) paths than standard memory devices. Static Random Access Memories (SRAMs) are another type of memory device. SRAMs store information by latching a set of transistors into one of two states, indicative of the associated logic level (i.e., a logic “1” or “0”). Unlike DRAMs, it is not necessary to refresh SRAMs since condition of the memory location is represented by a transistor state, rather than charge stored on a capacitor. SRAM technology is also conventional in the art, and is shown in U.S. Pat. No. 4,653,025 to Minato et al., which is herein incorporated by reference. Both DRAMs and SRAMs provide high data transfer rates, and both are widely used in the art. 
     Data transmission speeds would be greatly increased if both memory and microprocessors could be packaged on a single chip. The proximity of the circuits limits the travel time of the signals, and increases efficiency. Recently, a “System Module” has been developed which consists of a logic and memory chip stacked on top of one another with their contacts facing each other. This technique has been described, for example, by Yamaguchi et al. in “System module: a new Chip-On-Chip module technology”, Proceedings of IEEE 1997 Custom Integrated Circuit Conference, p.439-442, 1997, which is herein incorporated by reference. 
     The “System Module” is formed by pressing two separate chips  10 ,  20  (i.e. logic and memory, respectively) together and bonding them, as shown in FIGS. 1A and 1B. FIG. 1A shows the chips prior to be being pressed together. The chips are attached with their contacts  30 ,  40  facing each other. The connection is formed by placing solder balls  50  on the contact points of the chips, pressing the chips together, and reheating the solder so that it sets. FIG. 1B shows the chips after they have been pressed and heated. This concept is referred to as “micro bump” or “flip chip” bonding. FIGS. 1A and 1B show solder balls on the contacts of both chips, however, it is only required that one chip have solder balls placed on its contacts. In the “System Module”, the ‘bus’ which exchanges information between the logic chip and the memory is actually the solder bump connections. Once the “System Module” has been fabricated, it is placed in a lead frame, or other suitable device, for connection to other devices. The “System Module” provides for high data transfer rates because the logic ( 10 ) and the memory ( 20 ) chips are in direct contact with very little signal propagation distance therebetween. The disadvantage of this device is that only two chips at a time may be connected in this manner. Further, there is no room for placement of auxiliary circuits, such as active and passive devices which can be used to enhance the performance of the logic and memory circuits. 
     Although the “System Module” provides a short connection line between the two connected IC chips, it does not allow for the connection of additional circuits. In addition, in order to connect more than one memory and logic circuit together at a time, or to connect auxiliary circuits to the logic circuit or memory, longer connection lines (buses) are needed. Longer connection lines allow more circuits to be connected, but also increase the overall size of the device. Further, long lines cause signal delays and timing skews as explained below. 
     A major problem which occurs in many microprocessor/memory systems is timing skew. Since vast amounts of data are being transmitted over a bus at any one time, clock signals are used to synchronize various circuits which retrieve or transmit data. Timing skew occurs when respective clock signals, for synchronizing different circuits, do not reach their destination at approximately the same time. Timing skew is usually not a problem in devices which have short data paths and short clock paths, because the respective clock signals often reach their destination at the same time. However, as the length of these lines increases, clock speed must be reduced to compensate for the signal delay caused by the longer data lines. When memory and logic circuits are connected using longer bus lines, timing skew becomes a serious problem, especially at high clock rates. 
     Many prior art schemes have been developed to deal with timing skew problems. One solution is to use a phase locked loop circuit to synchronize the clock signals. Phase locked loop circuits are often utilized to synchronize clock signals on a chip with clock signals off-chip. A main clock generator determines the rate at which data is being transmitted or received by the computer. Since the main clock generator is usually not placed on the chip, it must travel a certain distance to reach the chip. This inherently means that the clock signal is experiencing some type of delay due to the length it travels. Once the main clock signal reaches the chip it must be synchronized with the on-chip clock generator. The phase locked loop circuit locks on to the off-chip clock and synchronizes it with the clock generator on-chip. This synchronization eliminates timing skew problems which occur due to the length of different clock lines. 
     There is currently a need for a microchip-memory interconnection system which allows many chips to be connected at once, and which does not suffer from timing skew problems. By connecting together multiple chips through relatively short bus lines, and by using auxiliary circuits, such as phase locked loop circuits, to minimize timing skews, an increase in data transmission rates can be easily achieved. 
     SUMMARY OF THE INVENTION 
     The present invention provides a superior method of packaging microprocessors and memory chips on a common silicon chip to form a multi-chip module. 
     The invention provides a silicon interposer chip package which is capable of carrying multiple IC chips and which does not suffer timing skew problems. This is accomplished by making the interconnection lines between the IC chips relatively short. The invention also provides active and passive circuits within the interposer substrate. These active and passive circuits increase the overall efficiency of the device. The invention also reduces timing skews which occur outside the interposer by utilizing an active circuit, such as a phase locked loop circuit, placed within the interposer substrate. 
     The above and other advantages and features of the present invention will be better understood from the following detailed description of the preferred embodiment which is provided in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B show a conventional “flip chip” bonded package; and, 
     FIG. 2 shows a preferred embodiment of the present invention. 
     FIGS. 3A-E show a preferred embodiment of the invention at different stages of fabrication. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 shows a preferred embodiment of the present invention. Instead of the having the IC chips bonded to one another, as in the prior art (e.g. FIGS.  1 A and  1 B), they are bonded to a silicon substrate  100  which is interposed between the chips. This silicon interposer substrate  100  is used to carry both memory chips  110  and a microprocessor  120 . The interposer substrate  100  is like a large chip which carries a multitude of smaller chips. The memory chips  110  can be any type of conventional memory device, such as DRAMs, SRAMS, or similar devices. The interposer substrate  100  may have active and passive devices built on one or both sides for further increasing data access speed. The connection between the microprocessor and the memory chips is formed by through holes  130  which extend through the interposer substrate  100  from one side to the other. These through holes form a ‘bus’ for connecting the microprocessor, the memory, and any other elements situated on the interposer substrate  100 . Elements on the same surface of the interposer substrate  100  are connected by one or more layers of metallurgy  140  formed on the surface. As shown in FIG. 2, the open space between the chips and interposer substrate  100  is filled with an epoxy  190 . The epoxy  190  provides for passivation and improves the fatigue characteristics of the solder joints which exist between the leads of the IC chips  110 ,  120  and the leads of the interposer substrate  100 . 
     Silicon is a particularly suitable material for forming the interposer substrate  100  for several reasons. Silicon is inexpensive and readily available. Further, the characteristics of silicon match those of the memory  110  and microprocessor  120  chips. Also, silicon has excellent thermal characteristics. In addition to silicon, Gallium Arsenide (GaAs) may also be used for the interposer material. 
     The construction of the interposer substrate  100  allows both active and passive circuits to be formed within its surface. One example of an active device which can be fabricated on the surface of the chip is a phase locked loop circuit. Such a circuit is shown in FIG. 2 by element  150 . As described above, phase locked loops are conventional in the art, and are often used for clock signal generation and synchronization. The phase locked loop can be used in this invention to minimize timing skews which occur outside the interposer substrate  100 . In other words, the phase locked loop circuit will synchronize an external clock (off-interposer) with the clock signal on the interposer substrate  100 . This allows data to be sent and received by the interposer substrate  100  at more rapid rates. For best results, two phase locked loops may be placed within the interposer substrate  100 , one for synchronizing the interposer clock when transmitting information and one for synchronizing the interposer clock when receiving information. 
     Other active circuits such as phase voltage generators, voltage regulators, line drivers, multiplexers, input/output drivers, power conditioners, and switching circuits may also be formed in the interposer substrate  100 . For example, in FIG. 2, area  160  represents a driver circuit, and area  170  represents a power conditioning circuit. The driver circuit  160  might comprise a differential line driver for reducing the voltage swing on off-chip lines. Power conditioning circuits would include such devices as voltage regulators and filters. Passive circuits  175 , such as resistors and capacitors, can also be formed in the interposer substrate  100 . The active and passive circuits may be placed only on a single side of the interposer substrate  100 , or may be placed on both sides. From a processing standpoint it would be simpler to form only passive circuits on one side of the interposer substrate  100  and only active circuits on the other side. This is because the process required to form active circuits is different than the one required for passive circuits. However, it is possible to process both sides of the interposer substrate  100  simultaneously to form active and passive circuits on both sides. 
     The key problem with operating memories and microprocessors at high data rates is controlling timing skews. Timing skews limit the ability of a computer to process data quickly. This problem is partially solved by decreasing the distance between the sender and receiver of information, in this case the microprocessor and the memory. A normal signal delay would be 1 ns/foot or 30 ps/cm, where the dielectric material is air. When the dielectric is silicon however, these propagation delays become much longer. These delays become troublesome at high clock rates, such as 500 MHz and above. Mounting the memory chips and the microprocessors on an interposer substrate  100  which is less than 50 mils or 0.125 cm thick, serves to keep the signal paths short, and timing skews are minimized or eliminated. The phase locked loop circuitry further reduces timing skews which occur when off-chip signals are used. 
     The process for forming the interposer substrate  100  will next be described with reference to FIGS. 3A-3E. First, as shown in FIG. 3A, a silicon wafer  200 , which will ultimately yield many interposer substrates  100 , has holes  210  drilled in it which will serve as through holes. The holes  210  are then subjected to an oxide deposition. This oxide deposition forms an oxide layer  220  on the inner surface of the holes  210 . The oxide layer serves to create an insulating layer between metal later deposited within the hole and the rest of the interposer substrate  100 . After the oxide deposition the holes  210  are filled with a metal conducting substance  230 , such as Aluminum (Al), Copper (Cu), Gold (Au) or Silver (Ag). These holes  210  provide a high density/high bandwidth connection between the chips  110 ,  120  (FIG. 2) attached to the opposite sides of the interposer substrate  100 . After the holes  210  are formed and treated, active and passive circuits  240  are formed within the silicon wafer  200 , by techniques well known in the art. The silicon wafer  200  with active and passive circuits  240  formed therein is shown in FIG.  3 C. Then, one or more levels of metallurgy (not shown) are formed on the surfaces of the interposer substrate  100 , as are required. Finally, the silicon wafer  200  is divided into a multitude of interposer substrates  100  (FIG. 2) as shown in FIG.  3 D. The dotted lines in FIG. 3D are exemplary dicing lines. 
     After this, the interposer substrate  100  is ready to have the IC chips  110 ,  120  mounted on its surface. The chips are mounted to the interposer substrate  100  by a process often called “flip chip” bonding, described above with reference to FIG.  1 . Essentially, the chips  110 ,  120  are flipped upside down and pressed against the interposer substrate  100 . The chips have contacts formed on their underside, with solder balls affixed thereon. The interposer substrate  100  has similar contacts formed on its surface. The chips are placed on the interposer substrate  100  so that the contacts face each other, with the solder balls placed between them. Once the chips are placed on the interposer, the device is heated so that the solder will melt and create a reliable bond between the chip contacts and the interposer contacts. As an alternative to the process described above, the IC chips may be mounted to the silicon wafer  200  before it is divided, as shown in FIG.  3 E. 
     The fabricator of such an interposer substrate  100  must also be cognizant of the problems caused when attaching chips by micro bump bonding. The IC chips must be attached to each side separately, and therefore the interposer substrate  100  must be heated twice to melt the solder, once for each side. However, a problem may occur if one of the IC chips ( 110 , 120 ) has already been mounted to one side of the interposer  100 . While heating the other side, the solder on the first side will also melt, and may cause the chips on that side to become dislodged. To avoid this problem, the fabricator may use different types of solder with different melting points. For instance, Pb 2.5% solder may be used for the ‘bumps’ on one side, and Pb-11 Wt % Sb for the ‘bumps’ on the other side. Further, another different type of solder, like Pb-62 Wt % Sn, may be used for soldering the interposer into a system circuit board. Another way to solve this problem would be to heat the solder bumps locally so that the heating of one side does not cause heating of the opposite side. 
     Once the complete interposer substrate  100  has been fabricated it can be mounted on a larger circuit board and/or connected to other elements. As shown in FIG. 2, the interposer substrate  100  is attached to external elements on a system circuit board through wire bonds  180 . The mounting of the interposer substrate  100  may be accomplished by mechanical means well-known in the art, such as through the use of a lead frames. FIG. 4 shows a lead frame  300  for carrying the completed interposer substrate  100 . The leads  320  of the lead frame will connect to the wire bonds  180  (FIG. 2) coming from the interposer. In order to protect the interposer substrate  100  and the attached IC chips ( 110 , 120 ), the unit may be encapsulated by methods well-known in the art, such as through an epoxy encapsulation  310 . Additionally, for further protection, the complete interposer unit may be sealed in container which is vacuum-sealed or filled with an inert gas (not shown). 
     It should be readily understood that the invention is not limited to the specific embodiment described and illustrated above. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description, but is only limited by the scope of the appended claims.