Abstract:
The present invention provides a multi-layer flexible circuit board, comprising at least an electric circuit disposed on a vertical interval layer, wherein at least two sides of the electric circuit are covered by neighboring interval layer and another vertical interval composed layer of electric insulating material. The disclosure provides a non-pressing way to stack the multi-layer flexible circuit board, preventing fault crevice derived from a prior-known pressing way.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a multi-layer flexible circuit board and a process for producing the same; in particular, to a multi-layer flexible circuit board which uses an electric insulation layer to enclose at least two sides of the electric circuit and a process for producing the same. 
         [0003]    2. Description of Related Art 
         [0004]    Conventional flexible circuit boards are made by processing precursor substrates. The precursor substrates must be coated with a metal conducting layer to enable subsequent processing. Metals generally do not easily adhere to conventional precursor substrates. Conventional methods of coating metal include metal spraying, sputtering deposition, CVD, vapor deposition, and dry coating. However these methods result in problems of thick precursor substrates, or difficult and overly long coating processes. The excess thickness compromises the miniaturization of products. 
         [0005]    Moreover, large thickness does not facilitate production of multi-layer flexible circuit boards. Difficult and overly long coating processes result in limited production capacity and raised production cost. Additionally, the pressing method used to produce most flexible circuit boards usually result in pressing defects, creating air bubbles due to disjunctions and poor yield rates. 
         [0006]    Also, a multi-layer flexible circuit board has more electric circuits, leading to a more serious problem of crosstalk between electric circuits. This is also a problem waiting to be solved. 
         [0007]    Hence, the present inventor believes the above mentioned disadvantages can be overcome, and through devoted research combined with application of theory, finally proposes the present disclosure which has a reasonable design and effectively improves upon the above mentioned disadvantages. 
       SUMMARY OF THE INVENTION 
       [0008]    The object of the present disclosure is to provide a multi-layer flexible circuit board and a process for producing the same, in order to reduce the product thickness so as to achieve product miniaturization, increase yield rate, and reduce crosstalk between electric circuits. 
         [0009]    In order to achieve the aforementioned objects, the present disclosure provides a process for producing the multi-layer flexible circuit board, including at least the following steps: providing a flexible circuit board whose surface has a first electric circuit protruding therefrom and an empty portion which is empty with respect to the first electric circuit; coating an electric insulation layer on the surface of the flexible circuit board, such that the electric insulation layer fills up the empty portion to define a neighboring interval layer and covers the top portion of the first electric circuit to define a vertical interval layer on top of the first electric circuit; and making the electric insulation layer coat at least two sides of the first electric circuit. 
         [0010]    In order to achieve the aforementioned objects, the present disclosure provides a multi-layer flexible circuit board including at least one electric circuit disposed on a vertical interval layer. The electric circuit is enclosed on at least two sides by a neighboring interval layer and a vertical interval layer formed by an electric insulation layer. 
         [0011]    In summary, the present disclosure coats electric insulation layer on the surface of the flexible circuit board to form the aforementioned neighboring interval layer and vertical interval layer, thereby enclosing at least two sides of the first electric circuit to improve upon the oft-encountered problem of yield rate encountered in conventional pressing techniques and to reduce the thickness of the product. Also, the conventional production method involves large amount of etching, which increases the difficulty the production of multi-layer flexible circuit boards and wastes most of the material due to etching in a non-environmentally friendly manner. The present disclosure however does not require large amount of etching and is therefore, relative to conventional techniques, able to reduce thickness, reduce cost, attain independence of material sourcing, and reduce waste of material to be environmentally friendly. 
         [0012]    Moreover, the electric insulation layer can provide electric shielding, thereby reducing crosstalk between electric circuits on the multi-layer flexible circuit board. In order to further the understanding regarding the present invention, the following embodiments are provided along with illustrations to facilitate the disclosure of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1A  shows a flowchart of steps according to a first embodiment of the present disclosure; 
           [0014]      FIG. 1B  shows a schematic diagram of a chemical mechanism employed during conductivity treatment of a substrate according to a first embodiment of the present disclosure; 
           [0015]      FIG. 1C  shows a flowchart of steps of conductivity treatment according to a first embodiment of the present disclosure; 
           [0016]      FIG. 2A  to  FIG. 2H  are cross-sectional views corresponding to the steps of the first embodiment of the present disclosure; 
           [0017]      FIG. 3  shows a flow chart of steps of the second embodiment of the present disclosure; and 
           [0018]      FIG. 4A  to  FIG. 4K  are cross-sectional views corresponding to the steps of the second embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]    The aforementioned illustrations and following detailed descriptions are exemplary for the purpose of further explaining the scope of the present invention. Other objectives and advantages related to the present invention will be illustrated in the subsequent descriptions and appended drawings. 
       First Embodiment 
       [0020]    Referring to  FIG. 1A  which is a flowchart according to a first embodiment of the present disclosure, the present disclosure provides a process for producing a flexible circuit board, including the following steps. 
         [0021]    As shown in the cross-sectional diagram of  FIG. 2A , provide a substrate  10  having a surface  11 . The surface  11  of the substrate  10  includes an upper surface  11   a  and a lower surface  11   b.  The substrate is a raw material and can be polyimide (PI), polyethylene terephthalate polyester (PET), polyethylene naphthalate (PEN), polytetrafluorethylene (PETE), thermotropic liquid crystal polymer (LCP, epoxy, aramid or other macromolecular polymers. Referring to  FIG. 2B , a via hole  12  can be bored by laser beam processing according to need on the substrate  10  interconnecting the upper surface  11   a  and the lower surface  11   b.  The via hole  12  has a tunnel wall  121  (step S 101 ). Additionally the substrate  10  processed by laser beam can be cleaned by plasma to remove residue left from laser processing. 
         [0022]    Referring to  FIG. 2B  and  FIG. 2C , use an adhesive enhancer to adhesively enhance the surface  11  of the substrate  10 , thereby forming an adhesion enhancing layer  20  on the surface  11  of the substrate  10 . More specifically, the adhesion enhancing layer  20  is positioned on the upper surface  11   a,  the lower surface  11   b  and the tunnel wall  121  of the substrate  10  (step S 103 ). In other words, the adhesion enhancing layer  20  can partially merge or fuse with the upper surface  11   a,  the lower surface  11   b  and the tunnel wall  121 . Preferably, the adhesion enhancer is a palladium adhesion enhancer. Next, form a first electrical conducting layer  30  which chemically bonds with the adhesion enhancing layer  20 . Assisted by the adhesion enhancing layer  20 , the first electrical conducting layer  30  is fixed onto the upper surface  11   a,  the lower surface  11   b  and the tunnel wall  121  of the substrate, thereby completing the production (step S 105 ) of a precursor substrate (label omitted). 
         [0023]    Preferably, the first electric conducting layer  30  has a thickness of 50 to 200 nanometers and is a metal selected from the group consisting of copper, nickel, chromium, cobalt, nickel alloys and cobalt alloys. Since the first electrical conducting layer  30  is fixed onto the substrate  10  by an electroless plating method, it is also an electroless plating layer. 
         [0024]    Referring to  FIG. 2D ,  FIG. 2E , and  FIG. 2F , dispose a layer of photoresist  40  on the first electrical conducting layer  30  on the upper surface  11   a  and the lower surface  11   b  of the substrate  10  (step S 107 ). Preferably the type of photoresist is not limited, and can be a positive photoresist or a negative photoresist. The photoresist can be disposed by laminating or coating. Expose and develop the photoresist  40  according to a circuit configuration diagram to partially remove the photoresist  40  and partially reveal the first electrically conducting layer  30  while leaving behind the remaining photoresist  40   a  (step S 109 ). Coat a metal layer at the revealed portion of the first electrical conducting layer  30  by electroplating (step S 111 ). The metal layer is a second electrical conducting layer  50  or a second electrical conducting layer  50 ′. Hereby only the second electrical conducting layer  50  is further explained. The first electrical conducting layer and the adhesion enhancing layer under the second electrical conducting layer  50  are respectively labeled  30   b  and  20   b.  Under the remaining photoresist  40   a  are the first electrical conducting layer  30   a  and the adhesion enhancing layer  20   a.  Preferably the second electrical conducting layer  50  is copper, but is not limited hereto. 
         [0025]    As shown in  FIG. 2G  and  FIG. 2H , remove the remaining photoresist  40   a  to reveal the first electrical conducting layer  30   a  under the remaining photoresist  40   a  (step S 113 ). Etch the revealed first electrical conducting layer  30   a  and the adhesion enhancing layer  20   a  underneath (step S 115 ). The adhesion enhancing layer  20   b  and the first electrical conducting layer  30   b  under the second electric conducting layer  50  of  FIG. 2G  are renamed as adhesion enhancing layer  20  and first electrical conducting layer  30  in  FIG. 2H . Given that the adhesion enhancing layer  20  and the first electrical conducting layer  30  formed on the substrate  10  are thinner compared to those in conventional techniques, the etching process of the present disclosure wastes less material which is more environmentally friendly. 
         [0026]    In the present embodiment, referring to  FIG. 2C , the substrate  10 , the adhesion enhancing layer  20  and the first electrical conducting layer  30  are respectively made of polyimide, palladium and nickel, but are not limited hereto. Referring to  FIG. 1B  and  FIG. 1C , the aforementioned step “use an adhesion enhancer to adhesively enhance the surface  11  of the substrate  10 , forming an adhesion enhancing layer  20 ” further includes a conductivity treatment. The object is to enhance the adhesion between the surface  11  of the substrate  10  and the palladium adhesion enhancer. The first electrical conducting layer  30  is formed by disposing the nickel on the palladium adhesion enhancer, which serves an important role as a foundation for the nickel to adhere to the substrate  10 . In other words, the nickel of the first electrical conducting layer  30  and the palladium of the adhesion enhancing layer can form a palladium-nickel alloy. 
         [0027]    As shown in  FIG. 1B ,  FIG. 1C  and  FIG. 2C , in order to enhance the adhesion between the surface of the substrate  10  and the palladium adhesion enhancer, the conductivity treatment includes the following steps on the substrate  10  surface: lipid removing process (step S 201 ), denaturation (step S 203 ), roughening process (step S 205 ), adhesion enhancing process (step S 207 ), and reduction process of the adhesion enhancer (step S 209 ). In particular, the roughening process (step S 205 ) includes chemical roughening or physical roughening. The chemical roughening includes using chemical agent on the surface of the substrate  10  to roughen by corrosion or ring-opening reactions. The physical roughening includes roughening the surface of the substrate  10  by mechanical means. Both methods improve adhesion of the surface of the substrate  10  to the palladium adhesion enhancer. The method of ring-opening reaction opens the molecular rings of the material of the substrate  10  to create unevenness in the molecular structure, to enhance adhesion between the palladium adhesion enhancer and the substrate  10 . In other words, if ring opening occurs on the structure of polyimide for example, microscopically the substrate  10  is roughened, thereby creating an adhesion effect between the surface of the substrate  10  and the ions of the palladium adhesion enhancer, such that the ions of the palladium adhesion enhancer is easily fixed onto the substrate  10 , forming the adhesion enhancing layer  20 . 
         [0028]    Furthermore as shown in  FIG. 1B , roughening by chemical ring opening involves using a basic agent to cleave one of the carbon-nitrogen bond of imides (O═C—N—C═O) such that ring opening occurs in the polyimide on the substrate  10 , and then using the palladium adhesion enhancer as a medium to increase adhesion between the polyimide and nickel, completing the process of electroless plating. 
         [0029]    Referring to  FIG. 1C  in conjunction with  FIG. 2A ,  FIG. 2B  and  FIG. 2C , when using ring opening as the roughening method, the following applies in the conductivity process: 
         [0030]    The lipid removing process uses amino alcohol (H 2 NCH 2 CH 2 CH 2 OH, agent number ES-100) agent having pH between 10 and 11 and temperature between 45 and 55 degree Celsius to clean the surface of the substrate  10  for 1 to 3 minutes, in order to remove lipid. 
         [0031]    The surface denaturation process uses a weak base having pH between 7.5 and 8.5 and temperature between 35 and 45 degree Celsius, such as sodium carbonate (agent number ES-FE) to clean the surface of the substrate  10  for 1 to 3 minutes, in order to restore the usual pH value on the surface of the substrate  10  and remove residual ES-100. However depending on the conditions after the previous steps, the present step can be skipped accordingly to achieve better effect. 
         [0032]    The surface roughening process is chemical and uses inorganic base having pH between 11 and 12 and temperature between 45 and 55 degree Celsius, such as potassium hydroxide (KOH, agent number ES-200) but is not limited hereto, in order to perform basic denaturation on the substrate  10  for 1 to 3 minutes, such that one of the carbon-nitrogen bonds in the polyimide O═C—N—C═O is cleaved so ring opening occurs to the polyimide. 
         [0033]    The adhesion enhancing process includes: using an adhesion enhancer to fix onto the surface of the substrate  10  to form an adhesion enhancing layer  20 . More specifically, the present step involves palladium ions forming chemical bonds with the carbonyl group (O═C—O—) of ring-opened polyimide (using agent ES-300, including complex compound having palladium sulfate H 2 SO 4 .Pd 4 , of a pH between 5.5 and 6.5 and between 45 and 55 degree Celsius, for 1 to 4 minutes). 
         [0034]    The reduction process of the adhesion enhancer includes adhering a metal onto the adhesion enhancing layer  20 , thereby merging the first electrical conducting layer  30  with the surface of the substrate  10 . More specifically, the present process uses agent ES-400 whose main ingredient is boron (pH is between 6 and 8, the temperature is between 30 and 40 degree Celsius, the process time is between 1 to 3 minutes), to reduce palladium ions such that the palladium can adhere to metal (nickel). Next use agent ES-500 whose main ingredients are NiSO 4 .6H 2 O and NaH 2 PO 2  (pH is between 8 and 9, temperature is between 35 and 45, processing time is between 3 and 5 minutes). The nickel easily adheres to the surface of the substrate with the palladium adhesion enhancer acting as an intermediary bonding medium. The nickel layer (first electrical conducting layer) has a thickness of 50 to 200 nanometers. After processing of the ES-500, the precipitated electroless plating of nickel has low amount of phosphorus (2-3%), therefore the first electrical conducting layer  30  is more ductile. The precipitation speed is 100 nm/5 minutes, which is faster than the conventional method, thereby saving production time and cost. 
         [0035]    As an aside, in the figures of the present disclosure, the adhesion enhancing layer  20 , the first electrical conducting layer  30 , the top surface  11   a,  the lower surface  11   b,  and the tunnel wall  121  have clear boundaries delineated in the diagrams merely for schematic purposes. In practice, the adhesion between the first electrical conducting layer  30  or the adhesion enhancing layer  20  to the top surface  11   a,  the lower surface  11   b  or the inner wall  121  can include an integrated merging layer (omitted in the figures). This implies that the precursor substrate produced by the production method of the present disclosure has strong adhesion between each of its different layers. 
         [0036]    Therefore, referring to  FIG. 2H , according to the aforementioned production method, the present disclosure provides a flexible circuit board, including: at least one multilayer unit (label omitted) disposed on a substrate  10 , including an adhesion enhancing layer  20 , a first electrical conducting layer  30  and a second electrical conducting layer  50 . The adhesion enhancing layer  20  is positioned on the surface  11  of the substrate  10 . The surface  11  includes the top surface  11   a  or the lower surface  11   b.  The first electrical conducting layer  30  adheres to the adhesion enhancing layer  20 . The second electrical conducting layer  50  is positioned on top of the first electrical conducting layer  30 . 
         [0037]    Preferably, the production method of the material of the substrate  10  is similar to the above. The material of the substrate  10  is at least one material selected from the group consisting of polyimide, polyester, polyethylene terephthalate, polytetrafluoroethylene, liquid crystal polymer, epoxy resin and aramid. The first electrical conducting layer  30  has a thickness of 50 to 200 nanometers and is an electroless plating layer made of a material selected from the group consisting of copper, nickel, chromium, cobalt, nickel alloys and cobalt alloys. The adhesion enhancing layer includes a palladium adhesion enhancer. 
         [0038]    Additionally, referring to  FIG. 2B ,  FIG. 2C  and  FIG. 2H , the substrate  10  has a via hole  12  running in the vertical direction connecting the top surface  11   a  and the lower surface  11   b.  The multilayer unit is respectively disposed on the top surface  11   a  and the lower surface  11   b  and is positioned on the via hole  12 . The adhesion enhancing layer  20  and the first electrical conducting layer  30  of the multilayer unit further extends along the tunnel wall  121  of the via hole  12 . The second electrical conducting layer  50  also extends along the via hole  12 , thereby electrically interconnecting the multilayer unit on the upper surface  11   a  and the multilayer unit on the lower surface  11   b.  The adhesion enhancing layer  20 ′, the first electrical conducting layer  30 ′ and the second electrical conducting layer  50 ′ in  FIG. 2H  do not extend into the via hole  12 . 
         [0039]    More specifically, when the second electrical conducting layer  50  extends into the via hole  12 , the multilayer units of the upper surface  11   a  and the lower surface  11   b  are electrically connected by the first electrically conducting layer  30  or the second electrically conducting layer  50  itself which fills up the via hole  12 . The adhesion enhancing layer  20  is preferably a palladium adhesion enhancer. The multilayer units can overall form a first electrical circuit E 1 . The multilayer units can be electrically connected or not electrically connected. 
       Second Embodiment 
       [0040]    In another embodiment, as shown in the flowchart of  FIG. 3  in conjunction with cross-sectional views of  FIG. 4A ,  FIG. 4B , and  FIG. 4C , the present disclosure provides a method of manufacturing a multi-layer flexible circuit board, including the following steps. Provide a flexible circuit board P whose surface  11  includes an upper surface  11   a  and a lower surface  11   b.  The surface  11  has a first electric circuit E 1  protruding from the surface  11  and an empty portion  11   c  having no first electrical circuit E 1  (step S 301 ). Coat an electric insulation layer on the surface  11  of the flexible circuit board P, such that the electric insulation layer fills up the empty portion  11   c  to form a neighboring interval layer  10   a.  The electric insulation layer coats the top portion of the first electric circuit E 1 , forming a vertical interval layer  11   d  (step S 303 ) such that the electric insulation layer coats at least two sides of the first electric circuit E 1  (step S 305 ). 
         [0041]    Preferably, the electric insulation layer is made of a material selected from the group consisting of polyimide film, polyamic acid (PAA), polyethylene terephthalate, polyethylene, liquid crystal polymer, epoxy resin, polyphenylene sulfide and photosensitive cover film. 
         [0042]    If the electric insulation layer is preferably embodied by polyamic acid, after coating the polyamic acid to form a neighboring interval layer  10   a  and a vertical interval layer  11   d,  the neighboring interval layer  10   a  and the vertical interval layer  11   d  can be cured such that the polyamic acid becomes (develops rings) polyimide. The curing occurs at 300 degree Celsius, in an environment full of nitrogen with infrared light beaming on the polyamic acid. After the polyamic acid becomes polyimide, a via hole  12   a  having a tunnel wall  121   a  can be bore through the vertical interval layer  11   d  such that the via hole  12   a  is connected to the first electric circuit E 1 . 
         [0043]    Referring to cross-sectional views of  FIG. 4D ,  FIG. 4E  and  FIG. 4F , the present production method includes the following steps. 
         [0044]    Use an adhesion enhancer to adhesively enhance the surface of the vertical interval layer  11   d,  thereby forming an adhesion enhancing layer  20   c  on the surface of the vertical interval layer  11   d.  Form a first electrical conducting layer  30   c  for chemically bonding with the adhesion enhancing layer  20   c,  thereby assisting the first electrical conducting layer  30   c  to be fixed onto the surface of the vertical interval layer  11   d.    
         [0045]    Dispose a photoresist  40   c  on the surface of the first electrical conducting layer  30   c.    
         [0046]    Expose and develop the photoresist  40   c  according to a circuit configuration diagram to partially remove the photoresist  40   c  and partially reveal the first electrically conducting layer  30   e  while leaving behind a remaining photoresist  40   d.    
         [0047]    Referring to  FIG. 4G ,  FIG. 4H ,  FIG. 4I  and  FIG. 4J , coat a metal layer on the revealed portion of the first electrical conducing layer (namely the first electrical conducting layer  30   e ) to form a second electric circuit E 2  by electroplating. The second electric circuit can extend into the via hole (label omitted) to electrically connect to the first electric circuit (positioned in the neighboring interval layer  10   a,  label omitted). Remove the remaining photoresist  40   d  to reveal the first electrical conducting layer  30   d  under the remaining photoresist  40   d.  Underneath the first electrical conducting layer  30   d  is the adhesion enhancing layer  20   d.  Etch the revealed first electrical conducting layer  30   d  and the adhesion enhancing layer  20   d  underneath. In this manner a multilayer unit (label omitted) having the adhesion enhancing layer  20   e,  the first electrical conducting layer  30   e  and the second electrical conducting layer  50   e  can be formed on the vertical interval layer  11   d.  Additionally, the same applies to the other multilayer unit formed having the adhesion enhancing layer  20   e ′, the first electrical conducting layer  30   e ′ and the second electrical conducting layer  50   e ′. Given that the two multilayer units are positioned on the same vertical interval layer  11   d,  they are considered as part of the second electric circuit E 2 , even though the two multilayer units can be mutually independent circuits. Even though the second electrical conducting layer  50   e  in the multilayer unit is an independent circuit, the second electrical conducting layer  50   e ′, the first electrical conducting layer  30   e ′ and the adhesion enhancing unit  20   e ′ in the other multilayer unit can be similar to the previous embodiments, passing through the vertical interval layer  11   d  via the via hole (label omitted) to further electrically connect to the second electrical conducting layer  50   b ′ of the first electric circuit E 1 , improving versatility of the electric circuit configuration. 
         [0048]    Additionally, referring to  FIG. 4J , the second electric circuit E 2  can be enclosed by a neighboring interval layer  10   a ′ and a vertical interval layer  11   d ′. The neighboring interval layer  10   a ′ and the vertical interval layer  11   d ′ are likewise formed by curing polyamic acid into polyimide. Therefore comparing  FIG. 4A  and  FIG. 4J , it can be seen that through curing of the polyamic acid, electric circuits can be added on the upper surface  11   a  or the lower surface  11   b  of the flexible circuit board P. 
         [0049]    Of course, when forming the multilayer unit which make up electric circuit on the flexible circuit board P as shown in  FIG. 4A , a conductivity treatment can be included just like the first embodiment, whose detailed process is described in the first embodiment, especially the processes of surface roughening and adhesion enhancing on the surface of the vertical interval layer  11   d,  such that the multilayer unit of the first electric circuit E 1 , the second electric circuit E 2  or any other electric circuit can have an adhesion enhancing layer (label omitted), hereby not further detailed. 
         [0050]    The second embodiment can be interpreted as an extended application of the first embodiment, and adds the multilayer structure of stacked polyamic acid converted to polyimide. Referring to  FIG. 4J  and  FIG. 4K , the present disclosure provides a multi-layer flexible circuit board, whose multi-layer electric-circuit configuration includes at least one electric circuit (label omitted), which can be disposed on the vertical interval layer  11   d  of  FIG. 4J . The electric circuit, for example as shown in  FIG. 4J , can include: a vertical interval layer  11   d,  an adhesion enhancing layer  20   e  (or adhesion enhancing layer  20   e ′), a first electrical conducting layer  30   e  (or a first electrical conducting layer  30   e ′) and a second electrical conducting layer  50   e  (or a second electrical conducting layer  50   e ′). The adhesion enhancing layer  20   e  is formed on the surface of the vertical interval layer  11   d.  The first electrical conducting layer  30   e  is formed on the adhesion enhancing layer  20   e.  The second electrical conducting layer  50   e  is formed on the first electrical conducting layer  30   e.  The first electrical conducting layer  30   e  and the second electrical conducting layer  50   e  both make up the second electric circuit E 2  on the vertical interval layer  11   d.    
         [0051]    In  FIG. 4J , the second electrical conducting layer  50   e ′, the first electrical conducting layer  30   e ′ and the adhesion enhancing layer  20   e ′ all belong to the second electric circuit E 2 . However they do not have to be mutually electrically connected. In order to keep the circuit design versatile, for example the second electrical conducting layer  50   e ′ can cross the vertical interval layer  11   d  to electrically connect to part of the first electric circuit E 1 . Any of the aforementioned electric circuit, for example the first electric circuit E 1  and the second electric circuit E 2  in the figures, is enclosed by neighboring interval layer ( 10   a,    10   a ′) and vertical interval layer ( 11   d,    11   d ′) formed by polyamic acid converted to polyimide. At least the left and right sides of the electric circuit of the flexible circuit board are enclosed and directly in contact with polyimide. Similarly, a third electric circuit E 3  and more can be constructed. 
         [0052]    It can be seen from  FIG. 4K , that the exemplified multi-layer flexible circuit board P with ten layers already includes two layers of circuits having the first electric circuit E 1 . According to the above method, additional layers can be progressively stacked above and below. The present embodiment respectively adds 4 layers on each side of the flexible circuit board P to form 10 layers (2+4+4) of circuits. In view of the concept of vertical interval layers introduced in the present embodiment, as shown in  FIG. 2H  of the first embodiment, the substrate  10  can be broadly viewed as a vertical interval layer. Likewise the substrate of  FIG. 4A  and  FIG. 4B  can also be viewed as a vertical interval layer. 
         [0053]    However, even though the above example includes an adhesion enhancing layer ( 20   e,    20   e ′), they are merely preferred embodiments and not strictly required. Likewise the electric insulation layer does not have to be formed by polyamic acid converting into polyimide. However if the electric insulation layer uses polyamic acid, but the electric circuit (or the multilayer unit) is conventional and does not have an adhesion enhancing layer, then the present embodiment can still form the polyamic acid on a conventional flexible circuit board to coat a conventional electric circuit, and cure the polyamic acid into polyimide to simplify the production of the multi-layer flexible circuit board, facilitating production. Additionally, through the enclosing provided by the polyimide and other electric insulation material, cross-talk is reduced between the many electric circuits on the flexible circuit board, resulting in better transmission quality. 
       Third Embodiment 
       [0054]    Returning to  FIG. 2A ,  FIG. 2B  and  FIG. 2C , the present disclosure further provides a precursor substrate (label omitted) as a partially finished product of a circuit board, to be used in subsequent circuit board processing. The precursor substrate includes at least: a substrate  10  and a first electrical conducting layer  30 . The substrate  10  has a surface  11  which is adhesively enhanced. The adhesively enhanced surface  11  includes an adhesion enhancing layer  20 . The first electrical conducting layer  30  adheres to the adhesion enhancing layer  20  such that the first electrical conducting layer  30  encloses the surface  11  of the substrate  10 . 
         [0055]    Preferably, the material of the substrate is polyimide; the adhesion enhancing layer  20  includes a palladium adhesion enhancer; the thickness of the first electrical conducting layer  30  is between 50 and 200 nanometers; and the first electrical conducting layer  30  is an electroless plating layer made of a material selected from the group consisting of copper, nickel, chromium, cobalt, nickel alloys and cobalt alloys. 
         [0056]    Preferably, the surface includes an upper surface  11   a  and a lower surface  11   b,  the substrate has a via hole  12  connecting the upper surface  11   a  and the lower surface  11   b,  the via hole has a tunnel wall  121 . Broadly speaking, the surface  11  of the substrate  10  includes the upper surface  11   a,  the lower surface  11   b  and the tunnel wall  121 , all of which can be adhesively enhanced and include the adhesive enhancing layer  20 . Thusly, the first electrical conducting layer  30  can be distributed by the adhesion enhancing layer  20  and coat the surface  11  of the substrate  10  including the upper surface  11   a,  the lower surface  11   b  and the tunnel wall  121 . 
         [0057]    The descriptions illustrated supra set forth simply the preferred embodiments of the present invention; however, the characteristics of the present invention are by no means restricted thereto. All changes, alternations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the present invention delineated by the following claims.