Abstract:
A semiconductor structure includes first and second conductive lines which cross each other. The second conductive lines are electrically insulated from the first conductive lines via an insulating material. The second conductive lines include first and second sections. First sections are arranged beneath crossing first conductive lines and include a semiconductor material. The second sections are disposed between adjacent first conductive lines and include a metal-semiconductor compound. A method of manufacturing a semiconductor structure involves forming initial second conductive lines, forming first conductive lines and providing a metal-semiconductor compound on an exposed surface of the initial second conductive lines, thereby obtaining second conductive lines. Forming the metal-semiconductor compound is performed after forming the first conductive lines.

Description:
FIELD THE INVENTION 
       [0001]    The invention relates to a semiconductor structure, a semiconductor memory device and a method of manufacturing the same. 
       BACKGROUND 
       [0002]    Semiconductor structures, for example memory cell arrays, comprise conductive lines. In order to achieve good performance of the semiconductor structure, the resistance of the conductive lines has to be low. One attempt to achieve good performance of the semiconductor structure is to use materials with a small specific resistivity. Not all materials may be used in a semiconductor structure, since some materials cause unwanted phenomena in the semiconductor structure. Therefore metal-semiconductor compounds, like for instance silicides, are used. 
         [0003]    A problem of using a metal-semiconductor compound for conductive lines, which are formed beneath other conductive lines, arises from the fact, that metal-semiconductor compounds do not withstand high thermal budgets. Holes within the metal-semiconductor compound or even destruction of the metal-semiconductor compound may appear resulting in an increase of the resistance of the conductive lines or even in destruction of the conductive lines. High thermal budgets may be caused by process steps, which are subsequently performed after forming first conductive lines comprising the metal-semiconductor compound in order to form second conductive lines above the first conductive lines. 
         [0004]    In nitride read only memory (NROM) technology, buried conductive lines are used as bitlines in the memory cell array.  FIG. 1  shows a top view on a NROM memory cell array. Buried bitlines  8  and wordlines  7  which extend at right angles to bitlines  8  define a lattice structure. Respective memory cells  1  are arranged below wordlines  7  between two respective bitlines  8 . Two memory cells  1  are shown by way of example by dashed lines in  FIG. 1 . Below the wordlines gate regions are provided, whereas the diffusion regions of the bitlines define the source/drain regions of a respective cell. Wordlines  7  and gate regions of single cells are separated from each other by an insulating layer  9 . 
         [0005]      FIG. 2  shows a cross-sectional view of the NROM cell array along line I-I as is shown in  FIG. 1 , for example. Line I-I extends along a wordline  7 . In particular, two NROM cells  1  are completely shown. NROM cell  1  is an n-channel MOSFET device, wherein the gate dielectric is replaced with a storage layer stack  27 . As is shown in  FIG. 2 , storage layer stack  27  is disposed above channel  25  and under gate electrode  26 . Channel  25  is arranged between two adjacent doped regions  2  forming bitlines  8 . Storage layer stack  27  usually comprises a charge trapping layer  272 , which may, for example, be a silicon nitride layer. A lower boundary layer  271  is disposed beneath the charge trapping layer. An upper boundary layer  273  is disposed above the charge trapping layer. The charge trapping layer  272  is disposed between the upper and lower boundary layers. Upper and lower boundary layers  271 ,  273  have a thickness larger than 2 nm to avoid any direct tunnelling. The memory cell is programmed by charge transport from channel  25  into charge trapping layer  272  by tunneling through lower boundary layer  271  and erased by charge transport from charge trapping layer  272  into channel  25  by tunnelling through lower boundary layer  271 . Gate electrode  26  may be formed of a semiconductor material, as for instance polysilicon. Separate gate electrodes  26  are connected by wordline  7 , formed by a polysilicon layer  12 , a metal layer  11  and a cap layer  10 . A charge stored in storage layer stack  27  determines the threshold voltage of the transistor. Accordingly, a charge trapped in storage layer stack  27  can be detected by applying corresponding voltages to doped regions  2  and gate electrode  26 . 
         [0006]    In regions between two memory cells  1 , an insulating layer  9  electrically insulates bitlines  8  from wordline  7 . 
         [0007]    A structure having buried bitlines, like for instance the NROM cell array of  FIG. 1 , shows a limited conductivity of doped regions  2  forming bitlines  8 . 
       SUMMARY 
       [0008]    The invention provides a semiconductor structure comprising a plurality of first conductive lines disposed along a first direction and a plurality of second conductive lines disposed along a second direction. The second direction is different from the first direction and the second conductive lines are formed beneath the first conductive lines. The second conductive lines are electrically insulated from the first conductive lines by an insulating material. At those portions of the second conductive lines, where the first conductive lines do not pass the second conductive lines, the second conductive lines comprise a metal-semiconductor compound. 
         [0009]    The invention provides a semiconductor memory device comprising a semiconductor substrate, a plurality of first conductive lines, a plurality of second conductive lines and a plurality of memory cells. The first conductive lines are disposed along a first direction and the second conductive lines are disposed along a second direction being different from the first direction. The second conductive lines are formed beneath the first conductive lines and are electrically insulated from the first conductive lines by an insulating material. The second conductive lines comprise first and second portions. The first portions comprise a semiconductor material, while the second portions comprise a metal-semiconductor compound. The first conductive lines cover the first portions of the second conductive lines. The memory cells are formed at least partially in the semiconductor substrate and form a memory cell array. Each memory cell of the memory cell array may be addressed by at least one first conductive line and at least one second conductive line. 
         [0010]    Furthermore the invention provides a method of manufacturing a semiconductor structure. First a plurality of second initial conductive lines disposed along a second direction is formed, wherein the initial second conductive lines comprise a semiconductor material. 
         [0011]    Subsequently, a plurality of first conductive lines disposed along a first direction being different from the second direction is formed. The first conductive lines are electrically insulated from the second initial conductive lines by an insulating material. 
         [0012]    A metal-semiconductor compound is provided on an exposed surface of the initial second conductive lines, thereby obtaining second conductive lines. This processing step is carried out after forming the first conductive lines. 
         [0013]    According to another embodiment of the invention, a method of manufacturing a semiconductor memory device comprises providing a semiconductor substrate including a surface, forming a plurality of semiconductor memory cells, forming a plurality of initial second conductive lines, forming a plurality of first conductive lines, and providing a metal-semiconductor compound. 
         [0014]    The memory cells are formed at least partially in the semiconductor substrate and form a memory cell array. 
         [0015]    The initial second conductive lines are disposed along a second direction and comprise a semiconductor material. 
         [0016]    The first conductive lines are disposed along a first direction being different from the second direction. The first conductive lines are electrically insulated from the initial second conductive lines by an insulating material. Each memory cell may be addressed by at least one first conductive line and at least one second conductive line. 
         [0017]    The metal-semiconductor compound is provided on an exposed surface of the initial second conductive lines after forming the first conductive lines. Thereby second conductive lines are obtained. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with a description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
           [0019]    The invention is explained in more detail below with reference to exemplary embodiments, where: 
           [0020]      FIG. 1  illustrates a plan view on an exemplary semiconductor structure; 
           [0021]      FIG. 2  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line I-I; 
           [0022]      FIG. 3  illustrates a plan view on a semiconductor structure according to the invention; 
           [0023]      FIG. 4  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line II-II; 
           [0024]      FIG. 5  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line III-III; 
           [0025]      FIG. 6  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line II-II at a first process; 
           [0026]      FIG. 7  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line III-III at the first process; 
           [0027]      FIG. 8  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line II-II at a second process; 
           [0028]      FIG. 9  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line III-III at the second process; 
           [0029]      FIG. 10  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line II-II at a third process; 
           [0030]      FIG. 11  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line III-III at the third process; 
           [0031]      FIG. 12  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line II-II at a fourth process; 
           [0032]      FIG. 13  illustrates a schematic cross-section of the semiconductor structure of  FIG. 1  along the line III-III at the fourth process. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments by which the invention may be practiced. In this regard directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, etc. is used with reference to the orientation of the figures being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the dependent claims. 
         [0034]      FIG. 3  illustrates a schematic plan view on an embodiment of the semiconductor structure of the invention. It shows by way of example an array of NROM memory cells with a plurality of first conductive lines  7  and a plurality of second conductive lines  8 . Conductive lines  7  may be wordlines of the memory cell array, and conductive lines  8  may be bitlines of the memory cell array. Nevertheless, any other semiconductor structure with at least two pluralities of conductive lines lies in the scope of the invention. 
         [0035]    As shown in  FIG. 3 , second conductive lines  8  lie beneath first conductive lines  7 . Conductive lines  7  run along a first direction  21 , while conductive lines  8  run along a second direction  22  which is different from the first direction. The second direction  22  may be perpendicular to the first direction  21  as shown in  FIG. 3 . 
         [0036]    First and second conductive lines are electrically insulated from each other by an insulating layer (not shown in  FIG. 3 ). In the embodiment shown in  FIG. 3 , self aligned isolation trenches  3  electrically insulate different conductive lines  8  from each other. Layers that may be formed within isolation trenches  3  are not shown in  FIG. 3 . Nevertheless, other insulation structures may be formed. 
         [0037]      FIG. 4  illustrates a schematic cross section of the embodiment of the semiconductor structure of  FIG. 3  along line II-II. Line II-II extends along first direction  21  between two neighboring conductive lines  7  thereby crossing different conductive lines  8 . In a semiconductor substrate  4 , by way of example p-silicon, second conductive lines  8  are formed. Conductive lines  8  comprise first and second portions  81  and  82 . In second portions  82  shown in  FIG. 4 , each conductive line  8  comprises a doped region  2 , by way of example n-doped silicon, formed within semiconductor substrate  4  and a metal-semiconductor compound  6  which is formed on top of doped region  2 . Metal-semiconductor compound  6  may be formed also at the sidewalls of doped region  2  so as to cover the sidewalls partially, as shown in  FIG. 4 . In the case where semiconductor substrate  4  is formed of silicon, the metal-semiconductor compound  6  is a silicide. 
         [0038]    In semiconductor substrate  4  isolation trenches  3  are formed. They electrically insulate adjacent second conductive lines  8  from each other. A covering layer  5  is formed at the surface of isolation trenches  3 . Covering layer  5  may cover the surface of isolation trenches  3  only partially or may completely fill isolation trenches  3 . Covering layer  5  may be an insulating layer or a layer stack comprising an insulating layer. 
         [0039]      FIG. 5  illustrates a schematic cross section of the embodiment of the semiconductor structure of  FIG. 3  along line III-III. Line III-III extends along second direction  22  along a conductive line  8 . First conductive lines  7  are formed above a second conductive line  8  formed in semiconductor substrate  4 . First conductive lines  7  may be formed by a layer stack as shown in  FIG. 3 . By way of example, conductive lines  7  comprise a semiconductor layer  12 , a metal layer  11  and a cap layer  10 . Semiconductor layer  12  may for instance be a poly-silicon layer. Metal layer  11  may for instance be W or WSi x  or any other layer of a material with low resistivity. Cap layer  10  may for instance be a nitride layer. At the sidewalls of each first conductive line  7  an insulating layer  14  is formed. Insulating layer  14  may be a silicon oxide or nitride or of any other conventionally used spacer material. Nevertheless, conductive lines  7  may be formed of any other conductive material. 
         [0040]    Conductive lines  7  are electrically insulated from conductive lines  8  by insulating layer  9  in portions  81 . Portions  81  are that portions where conductive lines  7  pass conductive lines  8 . Insulating layer  9  may be a silicon oxide, for instance formed by a CVD method using TEOS (Tetra-ethyl-ortho-silicate) as a starting material, and may have a thickness of several nanometers. 
         [0041]    In the NROM cell array shown in  FIG. 3 , memory cells are formed beneath conductive lines  7  between two neighboring conductive lines  8 . The schematic cross section of memory cell array along line I-I in  FIG. 3  along a conductive line  7  is identical with the cross section shown in  FIG. 2  and has been explained above. 
         [0042]    Nevertheless, other semiconductor structures are possible, wherein first conductive lines  7  are formed above second conductive lines  8  and wherein other memory cell arrays or no memory cells at all are formed. In any way, first and second conductive lines are electrically insulated from each other by an insulating layer. 
         [0043]    According to the invention, conductive line  8  comprises first and second portions  81  and  82 . In first portions  81 , where first conductive lines  7  pass (cover) second conductive line  8 ; second conductive line  8  comprises a semiconductor material. In second portions  82 , where first conductive lines  7  do not pass second conductive line  8 , second conductive line  8  comprises a semiconductor-metal compound. In the embodiment shown in  FIGS. 3 and 5 , all sections of conductive line  8  comprise a doped region  2  formed within semiconductor substrate  4 . Metal-semiconductor compound  6  is formed on top of doped region  2  only in second sections  82  of conductive line  8  which are not covered by first conductive lines  7  or insulating layer  14 . 
         [0044]    According to the invention, the resistance of second conductive lines  8  is reduced with reference to conventionally used second conductive lines. Since second sections  82  of conductive lines  8  according to the invention comprise metal-semiconductor compound  6 , conductive lines  8  show a lower resistance compared to conductive lines without a metal-semiconductor compound. 
         [0045]    A method of manufacturing a semiconductor structure according to the invention is explained with reference to  FIGS. 6 to 13 .  FIGS. 6 ,  8 ,  10 , and  12  show schematic cross-sectional views of the semiconductor structure of  FIG. 3  at different processing steps along the line II-II.  FIGS. 7 ,  9 ,  11 , and  13  show schematic cross-sectional views of the semiconductor structure of  FIG. 3  at different processing steps along the line III-III. 
         [0046]    First, doped regions  2 , insulating layer  9 , gate regions comprising storage layer stack  27  and gate electrode  26 , and first conductive lines  7  are formed. These processing steps are not shown in any figure, since they are known by any person skilled in the art. The resulting structure is shown in  FIGS. 6 and 7 . Doped regions  2  are formed within semiconductor substrate  4 . Regions  2  are formed as single lines extending from the surface  40  of substrate  4  into a predetermined depth, thereby forming initial second conductive lines  8 ′ which extend above sections  81  and  82 , as shown in  FIG. 7 . Insulating layer  9  is formed on surface  40  of substrate  4  except the gate regions (not shown in  FIGS. 6 and 7 ). First conductive lines  7  are formed above doped regions  2  and insulating layer  9 , and above the gate regions. Insulating layer  14  is formed at the sidewalls of first conductive lines  7 . In the case, that forming first conductive lines  7  comprises an etching step, the thickness of that portions of insulating layer  9  which are not covered by conductive line  7  or insulating layer  14  may be smaller than the thickness of covered portions of insulating layer  9  caused by over etching. This is not shown in  FIGS. 7 and 9 . 
         [0047]      FIGS. 8 and 9  show the semiconductor structure at a first process following above mentioned processing. Insulating layer  9  is patterned such that it is preserved only above doped regions  2 . It serves as a mask for forming isolation trenches  3  within surface  40  of substrate  4 . Isolation trenches  3  extend to a predetermined depth d 3  into substrate  4 , wherein the depth d 3  is larger than the depth d 2  of doped regions  2 . Depth d 3  and depth d 2  are measured from surface  40  of substrate  4 . The resulting structure is shown in  FIGS. 8 and 9  wherein  FIG. 8  shows a cross-sectional view along first direction  21  in the region between two neighboring conductive lines  7  and  FIG. 9  shows a cross-sectional view along a conductive line  8 . As can be seen,  FIG. 9  is identical with  FIG. 7  since insulating layer  9  remains above doped regions  2 . 
         [0048]    Next, insulating layer  9  is removed from top of doped regions  2 . Subsequently, a covering layer  5  is formed on top of the surface of the semiconductor structure. Layer  5  may be an insulating layer as for instance silicon oxide or any other layer which prevents forming a silicide with substrate  4  at following processing steps. The resulting structure is shown in  FIGS. 10 and 11 . As shown in  FIG. 10 , covering layer  5  covers the surface of doped regions  2  and the surface of isolation trenches  3 . It is not necessary to fill isolation trenches  3  completely with layer  5 . Holes in covering layer  5 , as shown in  FIG. 10 , do not affect further processing of semiconductor structure. As shown in  FIG. 11 , covering layer  5  also covers the surface of first conductive lines  7  and insulating layer  14 . 
         [0049]    Subsequently, layer  5  is removed from top of doped regions  2  leaving the surface of isolation trenches  3  at least partially covered. Consequently, layer  5  has to cover at least those portions of the surface of isolations trenches  3  which are not adjacent to doped regions  2 , as shown in  FIG. 12 . In other words, layer  5  extends from a depth d 51  to depth d 3  on the surface of isolation trench  3 . Depth d 51  has to be smaller than depth d 2  which is the depth of doped region  2  extending into substrate  4 . Depth d 3  is the depth of isolation trenches  3 . Depths d 2 , d 3 , and d 51  are measured from surface  40  of substrate  4 . 
         [0050]    Removing of layer  5  from top of doped regions  2  may be carried out by an anisotropic recess etching. The depth d 51  can be selected arbitrarily as long as d 51  is smaller than d 2  and as long as layer  5  is fully removed from top of doped regions  2 . The resulting structure is shown in  FIGS. 12 and 13 . As shown in  FIG. 12 , the top and a part of the sidewalls, of doped regions  2 , is not covered by layer  5 . As shown in  FIG. 13 , insulating layer  5  is removed from first conductive lines  7  and insulating layer  14 . Nevertheless, insulating layer  5  may remain on first conductive lines  7  by using a mask. 
         [0051]    In a next process, a metal-semiconductor compound  6  is formed on those portions of the surface of doped regions  2 , which are not covered by first conductive lines  7  or layers  5  or  14 . Thus, second conductive lines  8  comprising first and second sections  81  and  82  according to the invention are obtained. The resulting structure is shown in  FIGS. 3 to 5 . As shown in  FIG. 4 , metal-semiconductor compound  6  covers the top and partially the sidewalls of doped regions  2  in sections  82 . 
         [0052]    Isolation trenches  3  may be filled with an insulating material in a later process step, wherein layer  5  may remain at the surface of isolation trenches  3 . Nevertheless layer  5  may be removed from surface of isolation trenches  3  before filling isolation trenches  3 . 
         [0053]    Forming of metal-semiconductor compound  6  may be carried out by depositing a metal layer on the surface of the semiconductor structure and carrying out a temperature process. Thus, metal-semiconductor compound  6  is formed only at those regions, where the metal layer contacts a semiconductor material, like for instance doped regions  2 . Therefore, the surface of isolation trenches  3  adjoining substrate  4  have to be covered by covering layer  5 . While forming metal-semiconductor compound that way, material of doped regions  2  is partially transformed. Therefore, metal-semiconductor compound  6  extends partially into doped region  2 , as shown in  FIG. 3 . In other words, the lower interface, between metal-semiconductor compound  6  and doped region  2 , lies beneath surface  40  of substrate  4 . Subsequently, the metal layer not being transformed into metal-semiconductor compound  6  is removed. 
         [0054]    The metal layer may comprise: Co, W, Pt or Ni. The metal-semiconductor compound  6  may comprise: CoSi x , WSi x , PtSi x  or NiSi x  in case of silicon as the semiconductor material of substrate  4 . 
         [0055]    Nevertheless, other possibilities to form metal-semiconductor compound  6  being comprised by the semiconductor structure according to the invention are possible. 
         [0056]    According to the invention, metal-semiconductor compound  6  is formed after forming first conductive line  7 . Thus, problems, like deterioration or destruction of metal-semiconductor compounds, caused by high-temperature processes used to form conductive line  7  may be avoided, while reducing the resistance of second conductive lines  8 . 
         [0057]    The embodiments of the invention described in the foregoing are examples are given by way of illustration and the invention is in no ways limited thereto. Any modification, variation and equivalent arrangement should be considered as being included within the scope of the invention. 
         [0058]    Although specific embodiments has been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variations of the specific embodiments discussed herein. Therefore it is intended that this invention be limited only by the claims and the equivalents thereof. 
       LIST OF REFERENCE SIGNS 
       [0000]    
       
           1  memory cell 
           2  doped region 
           3  isolation trench 
           4  substrate 
           5  covering layer (may be oxide) 
           6  metal-semiconductor compound 
           7  first conductive lines 
           8  second conductive lines 
           8 ′ initial second conductive lines 
           9  insulating layer 
           10  cap layer (nitride) 
           11  metal layer 
           12  semiconductor layer 
           14  insulating layer (spacer) 
           21  first direction 
           22  second direction 
           25  channel 
           26  gate electrode (polysilicon) 
           27  storage layer stack 
           271  lower boundary layer 
           272  charge trapping layer 
           273  upper boundary layer 
           40  surface of the substrate 
           81  first section of second conductive line 
           82  second section of second conductive line 
         d 2  depth of doped region 
         d 3  depth of isolation trench 
         d 51  depth of recessed covering layer