Abstract:
A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Description:
FIELD OF THE INVENTION 
     Embodiments in accordance with the present invention generally pertain to semiconductor devices. 
     BACKGROUND 
     A “flip chip” is a semiconductor device that includes a pattern of solder balls arrayed on one of the chip&#39;s surfaces. During fabrication, the solder balls are formed on the top surface of the chip. The chip can then be readily mounted onto, for example, a circuit board by flipping the chip so that the top surface faces downward and the solder balls are aligned with corresponding pads on the circuit board. 
     In a non-flip chip semiconductor device, the gate and source contacts are on one surface (e.g., the top surface) of the chip while the drain contact is on the opposite surface (e.g., the bottom surface) of the chip. In a flip chip, the gate, source, and drain contacts are on the same surface of the chip. To form a circuit between the source and drain in a conventional flip chip, a “diffusion sinker” or “deep sinker”  110  is formed in the epitaxial layer  150  between the drain  120  and the substrate layer  130  as shown in  FIG. 1 . In operation, current will flow from the source  140  to, and through, the substrate and then to the drain in a known manner. 
     The sinker is formed using an isotropic diffusion process in which a dopant material is diffused through the epitaxial layer until the sinker is in contact with the substrate. However, as the sinker diffuses downward (in the y-direction), it also diffuses both along the surface of the structure (in the x-direction) and into the higher resistivity epitaxial layer. Thus, the surface area of the sinker is relatively large, increasing the size of each cell and thereby decreasing cell density. Also, the resistance of the epitaxial layer increases as the size of the sinker increases, thereby increasing the device&#39;s on-resistance (Rdson). Furthermore, the isotropic diffusion process is relatively slow, which increases the time needed to manufacture the flip chips and decreases throughput, thereby increasing costs. 
     SUMMARY 
     Embodiments according to the present invention provide solutions to the problems associated with sinkers. In one embodiment, relatively deep trenches filled with a conductive material such as tungsten are used to connect the drain contact to the substrate. Compared to a conventional sinker, the trenches—also referred to herein as “feed-throughs”—occupy less surface area and result in lower parasitic resistance in the epitaxial layer. There are also efficiencies associated with the fabrication of the feed-throughs, thus increasing throughput and reducing costs. These and other objects and advantages of the present invention will be recognized by one skilled in the art after having read the following detailed description, which are illustrated in the various drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Like numbers denote like elements throughout the drawings and specification. 
         FIG. 1  is a cross-sectional view showing elements of a conventional semiconductor device. 
         FIG. 2  is a cross-sectional view showing elements of a semiconductor device according to embodiments of the present invention. 
         FIG. 3A  illustrates a top-down view of a portion of a semiconductor device in one embodiment according to the present invention. 
         FIG. 3B  illustrates a portion of a feed-through array in an embodiment according to the present invention. 
         FIG. 4  illustrates an example of an arrangement of feed-throughs in an embodiment according to the present invention. 
         FIG. 5  is a cross-sectional view of feed-throughs showing selected dimensions in one embodiment according to the present invention. 
         FIG. 6  is a flowchart of a process that is used in the fabrication of a semiconductor device according to embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention. 
     Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as “forming,” “performing,” “producing,” “depositing,” “etching” or the like, refer to actions and processes (e.g., flowchart  600  of  FIG. 6 ) of semiconductor device fabrication. 
     The figures are not drawn to scale, and only portions of the structures, as well as the various layers that form those structures, may be shown in the figures. Furthermore, fabrication processes and steps may be performed along with the processes and steps discussed herein; that is, there may be a number of process steps before, in between and/or after the steps shown and described herein. Importantly, embodiments in accordance with the present invention can be implemented in conjunction with these other (perhaps conventional) structures, processes and steps without significantly perturbing them. Generally speaking, embodiments in accordance with the present invention can replace portions of a conventional device or process without significantly affecting peripheral structures, processes and steps. 
     As used herein, the letter “n” refers to an n-type dopant and the letter “p” refers to a p-type dopant. A plus sign “+” or a minus sign “−” is used to represent, respectively, a relatively high or relatively low concentration of the dopant. 
     The term “channel” is used herein in the accepted manner. That is, current moves within a field effect transistor (FET) in a channel, from the source connection to the drain connection. A channel can be made of either n-type or p-type semiconductor material; accordingly, a FET is specified as either an n-channel or a p-channel device. 
       FIGS. 2-6  are discussed in the context of a p-channel device, specifically a p-channel power MOSFET (metal oxide semiconductor FET) embodied as a flip chip; however, embodiments according to the present invention are not so limited. That is, the features described herein can be utilized in an n-channel device. The discussion of  FIGS. 2-6  can be readily mapped to an n-channel device by substituting n-type dopant and materials for corresponding p-type dopant and materials, and vice versa. 
       FIG. 2  is a cross-sectional view showing a portion of a semiconductor device  200  (e.g., a flip chip) according to an embodiment of the present invention. The device  200  includes a conductive (e.g., p+ or p++) substrate layer  202 . In one embodiment, there is a back metal layer  204  adjacent to the substrate layer  202 . The device also includes one or more additional layers exemplified by epitaxial layer  206 , which may also be referred to herein as an intervening layer. The epitaxial layer  206  may include additional structures, layers or regions not shown in  FIG. 2 . For example, the epitaxial layer  206  may include isolation layers and regions; junction and channel (inversion) layers and regions; body regions, etc. These structures, layers and regions are known in the art but are not illustrated here for simplicity. 
     A number of trench or trench-like polysilicon gates  210  are formed in the epitaxial layer  206 ; the gates  210  extend only partially into the epitaxial layer. Isolation caps (e.g., silicon dioxide, SiO 2 )  214  insulate the gates  210  from an overlying source metal  212  (e.g., aluminum) patterned on the epitaxial layer  206 . Between the gates  210  are a number of trench or trench-like source contacts  220 ; the contacts  220  extend only partially into the epitaxial layer  206 . Drain metal  216  (e.g., aluminum) is also patterned on the epitaxial layer  206  as shown in  FIG. 2 , and is isolated from the source metal  212  by an isolation region (e.g., SiO 2 )  218 . In one embodiment, the source metal  212  and the drain metal  216  are connected to respective solder balls (not shown in  FIG. 2 ; refer to  FIG. 3A ). 
     Continuing with reference to  FIG. 2 , a number of trench or trench-like elements  230 , also referred to herein as feed-throughs, are formed in the epitaxial layer  206 . The feed-throughs  230  extend completely through the epitaxial layer  206 , making contact with and perhaps extending into the substrate layer  202 . The feed-throughs  230  provide an electrical connection between the drain metal  216  and the substrate layer  202 . 
     In comparison to a conventional sinker, both the area and the volume consumed by the feed-throughs  230  are substantially reduced. Thus, the size of each cell can be reduced, thereby increasing cell density and/or reducing device size, an important consideration when the flip chip is used in mobile/hand-held devices such as cell phones and smart phones. Also, relative to a sinker, the feed-throughs  230  reduce the resistance of the epitaxial layer  206 , thereby decreasing the on-resistance (Rdson) of the device  200 . Furthermore, the feed-throughs  230  can be fabricated more quickly than a sinker, decreasing the time needed to manufacture the flip chips and increasing throughput, thereby decreasing costs. 
     In one embodiment, the feed-throughs  230  and the source contacts  220  are made of the same filler material. In one such embodiment, the feed-throughs  230  and the source contacts  220  are made of tungsten. Tungsten is chosen because its thermal coefficient is a better match with silicon than that of doped silicon, and because it has intrinsically lower resistance than doped silicon. Using the same material to fill the feed-through trenches and the source contact trenches facilitates fabrication, as will be described further below. 
     In one embodiment, the trenches for the feed-throughs  230  and the trenches for the source contacts  220  are each lined with the same liner material prior to deposition of the filler material, to prevent the filler material from contacting the surrounding silicon. In one such embodiment, the trenches are lined with a conformal coating of titanium (Ti) and Ti-nitride (TiN). In one embodiment, the Ti coating has a thickness of approximately 600 Angstroms, and the TiN coating has a thickness of approximately 200 Angstroms. Using the same material to line the feed-through trenches and the source contact trenches facilitates fabrication, as will be described further below. 
     The device  200  operates in a known manner, except that the feed-throughs  230  provide the functionality previously provided by a conventional sinker. By applying an electrical potential to a gate  210 , a circuit will be completed, with current flowing from the source metal  212  through the source contacts  220  into structures (not shown) in the epitaxial layer  206 , through the substrate layer  202 , and then to the drain metal  216  via the feed-throughs  230 . 
       FIG. 3A  illustrates a top-down (layout) view of a portion of the semiconductor device  200  (e.g., a flip chip) according to one embodiment of the present invention. In the example of  FIG. 3 , two solder balls  302  and  304  are in contact with the source metal  212 , a solder ball  306  is in contact with the gate metal  316 , and a solder ball  308  is in contact with the drain metal  216 . Underlying the drain metal  216  is an array  310  of feed-throughs  230 , shown in cross-section in  FIG. 2 . Thus, the drain metal  216  is formed over and connected with multiple feed-throughs  230 , and the solder ball  308  is formed on the drain metal  216 . 
       FIG. 3B  represents a portion of the feed-through array  310 . There can be many feed-throughs  230  situated within (underneath) the region of drain metal  216  and consequently under (and connected to) the solder ball  308 . Because many feed-throughs  230  are included in the array  310 , a large current can flow through the feed-throughs without causing an electromigration problem. In particular, the dimensions of each feed-through in the array are chosen so that the electromigration threshold is high. 
     Significantly, with reference back to  FIG. 3A , the surface area  320  that encompasses the source metal  212 , gate metal  316 , and drain metal  216  corresponds to the amount of surface area consumed by a conventional diffusion or deep sinker. In other words, the amount of surface area needed to accommodate the array  310  of feed-throughs  230  is substantially less than the area consumed by a sinker. Thus, as alluded to above, the use of the feed-throughs  230  in place of a sinker frees up real estate in the chip that can be used for additional structures such as those shown in  FIG. 3A . By using feed-throughs instead of sinkers, a device of a given size can include more cells; conversely, for a given number of cells, the size of a power MOSFET flip chip can be reduced. 
       FIG. 4  shows an example of an arrangement of feed-throughs  230  in which the feed-throughs are concentrated under only a portion of the region of drain metal  216 . Specifically, in the example of  FIG. 4 , the feed-throughs  230  are concentrated toward the direction from which the current is flowing—that is, toward the source region. Consequently, feed-throughs are not included in the area  410  of the drain region, further reducing the resistance of the epitaxial layer  206  ( FIG. 2 ), and further reducing the amount of surface area utilized for the feed-throughs. Thus, the area  410  can be used for other structures, for example, to increase cell density. 
       FIG. 5  is a cross-sectional view of tungsten feed-throughs  510  and  512  showing selected dimensions. In the example of  FIG. 5 , the feed-throughs  510  and  512  each have a width W of about 0.9 microns (more precisely, 0.95 microns); a depth D 1  of about 8.7 microns (more precisely, 8.73 microns) measured at the shortest (shallowest) point (along the centerline) and a depth D 2  of about 9.3 microns (more precisely, 9.31 microns) measured at the longest (deepest) point; and a distance (pitch P) between adjacent feed-throughs of about 1.7 microns (more precisely, 1.74 microns). With these dimensions, the resistance of an array of tungsten feed-throughs is about one-half of the resistance associated with a conventional sinker. 
       FIG. 6  illustrates a flowchart  600  of one embodiment of a process that is used in the fabrication of semiconductor devices such as the device  200  of  FIG. 2 . Although specific steps are disclosed in  FIG. 6 , such steps are only examples. That is, embodiments according to the present invention are well suited to performing various other steps or variations of the steps recited in  FIG. 6 . As noted above, the epitaxial layer  206  ( FIG. 2 ) may include structures, layers, and regions not shown in the figures—those structures, layers, and regions can be formed before, during (e.g., as part of), and/or after the steps in flowchart  600  are performed. 
     In block  602  of  FIG. 6 , with reference also to  FIG. 2 , a first mask, with openings corresponding to the locations of the source contacts  220 , is applied to the upper surface of the epitaxial layer  206 . The trenches for the source contacts are etched through those openings, and then the first mask is removed. The trenches for the source contacts extend partially into but not completely through the epitaxial layer  206 . 
     In block  604 , a second mask, with openings corresponding to the locations of the feed-throughs  230 , is applied to the upper surface of the epitaxial layer  206 . The trenches for the feed-throughs are etched through those openings, and then the second mask is removed. The trenches for the feed-throughs extend completely through the epitaxial layer  206  and into the substrate layer  202 . 
     In block  606 , a conformal coating is applied to the surfaces of the source contact trenches and to the surfaces of the feed-through trenches. In one embodiment, the conformal coating is applied to the surfaces of the source contact trenches and feed-through trenches in the same process step. In one such embodiment, the same material (e.g., Ti and TiN) is used to coat the surfaces of the source contact trenches and the feed-through trenches. 
     In block  608 , a filler material (e.g., tungsten) is deposited into the source contact trenches and into the feed-through trenches. In one embodiment, the filler material is deposited into the source contact trenches and the feed-through trenches in the same process step. 
     In block  610 , the filler material is etched back so that is flush, or nearly flush, with the upper surface of the epitaxial layer  206 . 
     In block  612 , other structures can be formed. For example, aluminum metal can be deposited and patterned to form source, drain, and gate regions. Subsequently, solder balls are positioned on the source, drain, and gate regions. 
     In comparison to a conventional process, the steps of i) applying the mask associated with the feed-through trenches and ii) forming the feed-through trenches are added, but the conventional steps of i) applying a mask to form a sinker and ii) forming the sinker are eliminated. Because, in one embodiment, the feed-through trenches are coated and filled at the same time that the source contact trenches are coated and filled, those steps do not lengthen the fabrication process by a significant amount, if at all. The feed-throughs  230  take less time to fabricate relative to the time needed to form a conventional sinker. Consequently, in total, the introduction of the feed-throughs shortens the length of the fabrication process, increasing throughput and decreasing cost. 
     Also, as mentioned above, the feed-throughs occupy less surface area and result in lower parasitic resistance in the epitaxial layer in comparison to conventional sinkers. Consequently, the size of each cell can be decreased, thereby increasing cell density. Moreover, the device&#39;s on-resistance is reduced. 
     The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.