Abstract:
A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

Description:
CROSS-REFERENCES TO RELATED-APPLICATION 
       [0001]    The present application claims priority to Korean application number 10-2007-0112034, filed on Nov. 5, 2007, which is incorporated by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to a semiconductor design technology and, more particularly, to a semiconductor device for generating a multi-phase clock signal, which has a plurality of phase information, with a minimum layout area and optimal current consumption. 
         [0003]    Generally, a semiconductor device, such as a DDR SDRAM (Double Data Rate Synchronous DRAM), receives an external clock signal to generate an internal clock signal, and the internal clock signal is inputted to several circuits within the semiconductor device to operate each circuit. 
         [0004]    Meanwhile, the current semiconductor device has been developed with the features of large capacity, high speed and low current consumption. Particularly, in order to achieve high speed operation, the semiconductor device is designed to operate in response to the external clock signal having a higher frequency. 
         [0005]    Recently, since the frequency of the external clock signal has been raised to a few GHz, the frequency of the internal clock signal is also raised within the semiconductor device, thereby causing many problems in the operation timing margin of a circuit and current consumption. 
         [0006]    In order to solve the problems, the semiconductor device employs a method of transferring a multi-phase clock signal. This method is not to transfer a clock signal which has the same high frequency as the external clock signal, but to transfer a plurality of phase clock signals which have a low frequency which corresponds to a half of the high frequency of the external clock signal and have a plurality of phase information, when the internal clock signal is transferred within the semiconductor device. The semiconductor device transfers the internal clock signal by such a method, thereby reducing current consumption caused by internal clock signal transmission and securing a stable timing margin. 
         [0007]    Generally, in order to generate the plurality of the phase clock signals, the semiconductor device can include a phase locked loop (PLL) or a delay locked loop (DLL). 
         [0008]      FIG. 1  is a block diagram illustrating a conventional phase locked loop for generating a plurality of phase clock signals. 
         [0009]    Referring to  FIG. 1 , the phase locked loop includes a clock frequency divider  110 , a control voltage signal generating unit  130  and a voltage control oscillating unit  150 . 
         [0010]    The clock frequency divider  110  divides a frequency of a reference clock signal CLK_REF which corresponds to an external clock signal. The high frequency of the external clock signal is thus reduced by the clock frequency divider  110 . 
         [0011]    The control voltage signal generating unit  130  detects a phase of a clock signal generated from the division of the frequency of the reference clock signal CLK_REF by the clock frequency divider  110  and from a phase of a feedback clock signal CLK_FED, thereby generating a control voltage signal V_CTR which has a voltage level corresponding to that of the feedback clock signal CLK_FED. 
         [0012]    The voltage control oscillating unit  150  generates a plurality of phase clock signals each having a frequency corresponding to the control voltage signal V_CTR, namely, first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 180  and MCLK 270 . Among the first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 180  and MCLK 270 , the third phase clock signal MCLK 180  becomes the feedback clock signal CLK_FED which is fed back to the control voltage signal generating unit  130 . 
         [0013]    The phase locked loop repetitively compares the phase of the clock signal generated from the division of the frequency of the reference clock signal CLK_REF with that of the feedback clock signal CLK_FED in order to generate the first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 180  and MCLK 270  each of which has a desired frequency. The finally generated first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 180  and MCLK 270  have a constant phase difference and a frequency lower than that of the external clock signal. That is, the second phase clock signal MCLK 90  is 90° out of phase with the first phase clock signal MCLK 0 , the third phase clock signal MCLK 180  is 180° out of phase with the first phase clock signal MCLK 0 , and the fourth phase clock signal MCLK 270  is 270° out of phase with the first phase clock signal MCLK 0 . 
         [0014]    Here, since the technical implementation and the operation of the clock frequency divider  110 , the control voltage signal generating unit  130  and the voltage control oscillating unit  150  are obvious to those skilled in the art, a detailed explanation for them will not be described. 
         [0015]    Meanwhile, generally, the voltage control oscillating unit  150  includes a plurality of delay cells (not illustrated), and the first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 180  and MCLK 270  correspond to clock signals outputted from the delay cells. Therefore, in order for the first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 180  and MCLK 270  to have an accurate phase difference, the plurality of the delay cells should be identically included and the loadings between the delay cells should be accurately consistent. Also, in order to reduce external noise, a signal or power line should not pass around the voltage control oscillating unit  150 . However, such a design has a demerit of occupying too much layout area. 
         [0016]    Similar to the phase locked loop, the delay locked loop can also generate the plurality of the phase clock signals. However, there is also a demerit in that the delay locked loop is difficult to design and occupies too much layout area. Also, the phase locked loop and the delay locked loop cause much current consumption during circuit operation. 
         [0017]    As described above, the phase locked loop and the delay locked loop, which can generate the plurality of the phase clock signals, have demerits in that there are lots of things to be considered when designing them, they occupy too much layout area, and they consume too much current during circuit operation. Thus, they are an obstacle to low current consumption and high integration in the semiconductor device. The present invention will suggest a solution for such problems. 
       SUMMARY OF THE INVENTION 
       [0018]    An embodiment of the present invention is directed to providing a semiconductor device for generating a plurality of phase clock signals in response to a plurality of reset signals having different activation timings according to a constant phase difference and an operation method of the semiconductor device. 
         [0019]    Another embodiment of the present invention is directed to providing a semiconductor device for generating a plurality of phase clock signals without a delay locked loop and a phase locked loop and an operation method of the semiconductor device. 
         [0020]    According to the present invention, a semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0022]      FIG. 1  is a block diagram illustrating a conventional phase locked loop for generating a plurality of phase clock signals; 
           [0023]      FIG. 2  is a block diagram illustrating a multi-phase clock signal generating circuit according to the present invention; 
           [0024]      FIG. 3  is a circuit diagram illustrating a reset signal generating unit of  FIG. 2 ; 
           [0025]      FIG. 4  is a waveform diagram illustrating an operation of I/O signals according to the present invention; 
           [0026]      FIG. 5  is a block diagram illustrating a multi-phase clock signal generating unit of  FIG. 2 ; and 
           [0027]      FIG. 6  is a circuit diagram illustrating a first clock frequency divider of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0028]    Hereinafter, the present invention will be described in detail through embodiments. The embodiments are just for exemplifying the present invention, and the scope of right to be protected of the present invention is not limited by them. 
         [0029]      FIG. 2  is a block diagram illustrating a multi-phase clock signal generating circuit according to the present invention. 
         [0030]    Referring to  FIG. 2 , the multi-phase clock signal generating circuit includes a reset signal generating unit  210  and a multi-phase clock signal generating unit  230 . 
         [0031]    The reset signal generating unit  210  receives a source reset signal RST 0  to generate first to fourth reset signals RST 1 , RST 2 , RST 3  and RST 4 , having different activation timings with a constant phase difference, in response to clock signals CLK and CLKB. 
         [0032]    Here, the source reset signal RST 0  is activated first in order to operate the multi-phase clock signal generating circuit. The clock signals CLK and CLKB, which respond to an external clock signal, include a positive clock signal CLK responding to a rising edge of the external clock signal and a negative clock signal CLKB responding to a falling edge of the external clock signal. Particularly, the activation timings of the first to fourth reset signals RST 1 , RST 2 , RST 3  and RST 4  are sequentially decided in response to the positive and negative clock signals CLK and CLKB. 
         [0033]    Meanwhile, the multi-phase clock signal generating unit  230  operates in response to the first to fourth reset signals RST 1 , RST 2 , RST 3  and RST 4  and divides the frequencies of the positive and negative clock signals CLK and CLKB to generate first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 180  and MCLK 270  which have a constant phase difference. 
         [0034]    Here, the first phase signal MCLK 0  corresponds to the rising edge of the positive clock signal CLK, the second phase signal MCLK 90  is 90° out of phase with the first phase clock signal MCLK 0 , the third phase clock signal MCLK 180  is 180° out of phase with the first phase clock signal MCLK 0 , and the fourth phase clock signal MCLK 270  is 270° out of phase with the first phase clock signal MCLK 0 . 
         [0035]    According to the present invention, it is possible to generate a plurality of phase clock signals having a constant phase difference without using a delay locked loop and a phase locked loop. 
         [0036]      FIG. 3  is a circuit diagram illustrating a reset signal generating unit  210  of  FIG. 2 . 
         [0037]    Referring to  FIG. 3 , the reset signal generating unit  210  includes a source reset signal input unit  310  and a shifting unit  330 . 
         [0038]    The source reset signal input unit  310  receives the source reset signal RST 0  to generate a first negative reset signal RST 1 B in response to the positive clock signal CLK. For example, when the source reset signal RST 0  is in a high level, the first negative reset signal RST 1 B is in a low level, and when the source reset signal RST 0  is in a low level, the first negative reset signal RST 1 B is in a high level in response to the positive clock signal CLK. Here, an output signal of the source reset signal input unit  310  can be used as a reference signal of the first to fourth reset signals RST 1 , RST 2 , RST 3  and RST 4 . 
         [0039]    The shifting unit  330  shifts the output signal of the source reset signal input unit  310  in response to the positive and negative clock signals CLK and CLKB to generate the first to fourth reset signals RST 1 , RST 2 , RST 3  and RST 4 . A plurality of first to fourth shifters  332 ,  334 ,  336  and  338  are included in the shifting unit  330 . 
         [0040]    Here, the first reset signal includes a first positive reset signal RST 1 , which corresponds to the first phase clock signal MCLK 0 , and the first negative reset signal RST 1 B, the second reset signal includes a second positive reset signal RST 2 , which corresponds to the second phase clock signal MCLK 90 , and a second negative reset signal RST 2 B, the third reset signal includes a third positive reset signal RST 3 , which corresponds to the third phase clock signal MCLK 180 , and a third negative reset signal RST 3 B, and the fourth reset signal includes a fourth positive reset signal RST 4 , which corresponds to the fourth phase clock signal MCLK 270 , and a fourth negative reset signal RST 4 B. A detailed waveform diagram of such signals will be explained later through  FIG. 4 . 
         [0041]    Meanwhile, since the first to fourth shifters  332 ,  334 ,  336  and  338  have the same configuration, only the first shifter  332  will be described here for convenience in illustration. 
         [0042]    The first shifter  332  includes a reset signal output unit  332 A which receives the first negative reset signal RST 1 B to output the first positive reset signal RST 1  in response to the negative clock signal CLKB and a reset signal latch unit  332 B which latches the first positive reset signal RST 1  to output the second negative reset signal RST 2 B. 
         [0043]    Therefore, in case that the first negative reset signal RST 1 B is in a low level, the first positive reset signal RST 1  is in a high level, and in case that the first-negative reset signal RST 1 B is in a high level, the first positive reset signal RST 1  is in a low level in response to the negative clock signal CLKB. 
         [0044]    The second to fourth shifters  334 ,  336  and  338  operate the same as the first shifter  332 . Thus, each of the first to fourth shifters  332 ,  334 ,  336  and  338  receives an output signal of its previous shifter and outputs a reset signal in response to the positive clock signal CLK or the negative clock signal CLKB. 
         [0045]    In detail, the first shifter  332  receives an output signal of the source reset signal input unit  310  to output the first positive reset signal RST 1  in response to the negative clock signal CLKB and latches the first positive reset signal RST 1  to output the second negative reset signal RST 2 B. The second shifter  334  receives the second negative reset signal RST 2 B to output the second positive reset signal RST 2  in response to the positive clock signal CLK and latches the second positive reset signal RST 2  to output the third negative reset signal RST 3 B. The third shifter  336  receives the third negative reset signal RST 3 B to output the third positive reset signal RST 3  in response to the negative clock signal CLKB and latches the third positive reset signal RST 3  to output the fourth negative reset signal RST 4 B. The fourth shifter  338  receives the fourth negative reset signal RST 4 B to output the fourth positive reset signal RST 4  in response to the positive clock signal CLK and latches the fourth positive reset signal RST 4 . 
         [0046]    That is, the first shifter  332  shifts the output signal of the source reset signal input unit  310  to output the first positive reset signal RST 1  in response to the negative clock signal CLKB, the second shifter  334  shifts the output signal of the first shifter  332  to output the second positive reset signal RST 2  in response to the positive clock signal CLK, the third shifter  336  shifts the output signal of the second shifter  334  to output the third positive reset signal RST 3  in response to the negative clock signal CLKB, and the fourth shifter  338  shifts the output signal of the third shifter  336  to output the fourth positive reset signal RST 4  in response to the positive clock signal CLK. 
         [0047]      FIG. 4  is a waveform diagram illustrating waveforms of I/O signals according to the present invention. It can be seen that the phase difference between adjacent ones of the reset signals is the same, i.e. RST 1  and RST 2  have the same phase difference as RST 2  and RST 3 , which has the same phase difference as between RST 3  and RST 4 . 
         [0048]    Referring to  FIGS. 3 and 4 , when the source reset signal RST 0  is in a high level, the first to fourth positive reset signals RST 1 , RST 2 , RST 3  and RST 4  are in a high level and the first to fourth negative reset signals RST 1 B, RST 2 B, RST 3 B and RST 4 B are in a low level regardless of the positive and negative clock signals CLK and CLKB. 
         [0049]    Then, when the source reset signal RST 0  is in a low level and the positive clock signal CLK is in a high level, the first negative reset signal RST 1 B is in a high level. The reset signal output unit  332 A of the first shifter  332  outputs the first positive reset signal RST 1 , which is in a low level, in response to the negative clock signal CLKB. The reset signal latch unit  332 B of the first shifter  332  latches the first positive reset signal RST 1  and outputs the second negative reset signal RST 2 B which is in a high level. 
         [0050]    Similarly, the second shifter  334  receives second negative reset signal RST 2 B to output the second positive reset signal RST 2 , which is in a low level, in response to the positive clock signal CLK and outputs the third negative reset signal RST 3 B which is in a high level. The third shifter  336  receives the third negative reset signal RST 3 B to output the third positive reset signal RST 3 , which is in a low level, in response to the negative clock signal CLKB and outputs the fourth negative reset signal RST 4 B which is in a high level. The fourth shifter  338  receives the fourth negative reset signal RST 4 B to output the fourth positive reset signal RST 4 , which is in a low level, in response to the positive clock signal CLK. 
         [0051]    For convenience in illustration, the first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 180  and MCLK 270  will be described after  FIGS. 5 and 6  are illustrated. 
         [0052]      FIG. 5  is a block diagram illustrating a multi-phase clock signal generating unit of  FIG. 2 . 
         [0053]    Referring to  FIG. 5 , the multi-phase clock signal generating unit  230  includes first to fourth clock frequency dividers  510 ,  530 ,  550  and  570 . 
         [0054]    The first clock frequency divider  510  operates in response to the first positive and negative reset signals RST 1  and RSTB and divides the frequencies of the positive and negative clock signals CLK and CLKB to generate the first phase clock signal MCLK 0 . The second clock frequency divider  530  operates in response to the first positive and negative reset signals RST 1  and RSTB and divides the frequencies of the positive and negative clock signals CLK and CLKB to generate the second phase clock signal MCLK 90 . The third clock frequency divider  550  operates in response to the first positive and negative reset signals RST 1  and RSTB and divides the frequencies of the positive and negative clock signals CLK and CLKB to generate the third phase clock signal MCLK 180 . The fourth clock frequency divider  570  operates in response to the first positive and negative reset signals RST 1  and RSTB and divides the frequencies of the positive and negative clock signals CLK and CLKB to generate the fourth phase clock signal MCLK 270 . 
         [0055]      FIG. 6  is a circuit diagram illustrating the first clock frequency divider  510  of  FIG. 5 . 
         [0056]    Referring to  FIG. 6 , the first clock frequency divider  510  includes a phase clock signal latch unit  610 , a feedback unit  630 , reset units  650 A and  650 B and a phase clock signal output unit  670 . 
         [0057]    The phase clock signal latch unit  610  latches an input signal IN, which is fed back from the feedback unit  630 , in response to the positive and negative clock signals CLK and CLKB. The feedback unit  630  receives an output signal of the phase clock signal latch unit  610  to output a feedback signal as the input signal IN. The first reset unit  650 A sets or resets node A of the phase clock signal latch unit  610  in response to the first negative reset signal RST 1 B. The second reset unit  650 B sets or resets node B in response to the first positive reset signal RST 1 . The phase clock signal output unit  670  outputs an output signal of the phase clock signal latch unit  610  as the first phase clock signal MCLK 0 . 
         [0058]    Here, the phase clock signal latch unit  610  can include flip-flop circuits. Also, it is possible to use a circuit which is set or reset by the first positive and negative reset signals RST 1  and RST 1 B and divides the frequencies of the positive and negative clock signals CLK and CLKB. 
         [0059]    Meanwhile, the first to fourth clock frequency dividers  510 ,  530 ,  550  and  570  can have the same circuit configurations. Referring to  FIG. 6 , the positive and negative reset signals corresponding to the second to fourth clock frequency dividers  530 ,  550  and  570  can be inputted to the second to fourth clock frequency dividers  530 ,  550  and  570  instead of the first positive and negative reset signals RST 1  and RST 1 B inputted to the first clock frequency divider  510 , and the positive and negative clock signals CLK and CLKB can be inversely inputted to the second clock frequency divider  530  and the fourth clock frequency divider  570 . 
         [0060]    Therefore, the first clock frequency divider  510  outputs the first phase clock signal MCLK 0  of which the frequency is divided in response to the positive clock signal CLK, the second clock frequency divider  530  outputs the second phase clock signal MCLK 90  in response to the negative clock signal CLKB, the third clock frequency divider  550  outputs the third phase clock signal MCLK 180  in response to the positive clock signal CLK, and the fourth clock frequency divider  570  outputs the fourth phase clock signal MCLK 270  in response to the negative clock signal CLKB. 
         [0061]    Referring again to  FIG. 4 , as described above, when the source reset signal RST 0  is in a low level, the activation timings of the first to fourth reset signals RST 1 , RST 2 , RST 3  and RST 4  are sequentially decided in response to the positive and negative clock signals CLK and CLKB. Also, the first to fourth clock frequency dividers  510 ,  530 ,  550  and  570  sequentially prepare to output the first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 280  and MCLK 270  in response to the first to fourth reset signals RST 1 , RST 2 , RST 3  and RST 4  and outputs them in response to the positive and negative clock signals CLK and CLKB. 
         [0062]    The first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 280  and MCLK 270  become low frequency multi-phase clock signals having a phase difference of 90° from each other. 
         [0063]    Since the present invention generates the first to fourth phase clock signals MCLK 0 , MCLK 90 , MCLK 280  and MCLK 270  having a constant phase difference without the phase locked loop and the delay locked loop, a layout area and current consumption can be minimized and its design can be simplified. 
         [0064]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. 
         [0065]    For example, the position and kind of the logic gate and transistor shown in one embodiment of the present invention should be changed according to the polarity of inputted signals. 
         [0066]    Further, in one embodiment of the present invention, the case where the same positive and negative reset signals CLK and CLKB are inputted to the reset signal generating unit  210  and the multi-phase clock signal generating unit  230  is described. However, the present invention can also be applied to the case where other control signals are inputted to the reset signal generating unit  210 . That is, the control signal inputted to the reset signal generating unit  210  only has to make the plurality of the reset signals have sequential activation timings with a constant phase difference.