Abstract:
Disclosed are a control circuit and a noise removing method for a touch screen. The present invention includes technology for performing differential sensing on the outputs of two adjacent sensing lines of a touch screen panel and integrating a differential sensing signal to filter noises. The control circuit and noise filtering according to the present invention may remove the display noise, tri-wave lamp noise having a predetermined frequency, 60 Hz noise and charger noise caused by battery charging that might affect the two adjacent sensing lines.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a touch screen, and more particularly, to a control circuit and noise removal method for a touch screen, which remove a noise introduced into the touch screen. 
         [0003]    2. Related Art 
         [0004]    A Touch Screen Panel (TSP) is configured to detect a user&#39;s touch using a resistive type, a capacitive type, or an infrared type. In recent years, the capacitive type is chiefly used as the touch screen panel. The capacitive type touch screen panel is advantageous in super visibility, durability, and a multi-touch function in middle and small-sized mobile product groups. In particular, a mutual capacitive type touch screen panel is chiefly used. 
         [0005]    A touch screen using a capacitive type panel has a low Signal to Noise Ratio (SNR) due to various noises. Noises that affect the touch screen may be divided into a random noise and a periodic noise. The random noise may include a display noise. The periodic noise may include a 60 Hz noise generated in a fluorescent lamp and a 40 to 50 KHz noise generated in a three-wave inverter lamp. In particular, the periodic noise may include a charger noise generated when the battery is charged, and the charger noise may be classified as the worst type noise. 
         [0006]    If a noise is severe, a lead-out circuit for processing the signal of sensing lines of a touch screen panel does not accurately recognize electric charges included in the sensing line. As a result, an error may occur in the touch recognition of a touch screen due to a noise. 
       SUMMARY 
       [0007]    An object of the present invention is to provide a control circuit for a touch screen, which filters noises including display noises by performing differential sensing on two adjacent sensing lines of a touch screen panel. 
         [0008]    Another object of the present invention is to provide a control circuit for a touch screen, which performs differential sensing on two adjacent sensing lines of a touch screen panel and filters noises including periodic noises using a moving average method. 
         [0009]    Yet another object of the present invention is to provide a control circuit and noise removal method for a touch screen, which filter noises including a charger noise by periodically storing the voltage of a sensing line output by a touch screen panel, integrating and outputting the voltage of a previous cycle in normal cases and blocking the integration of voltages in a previous cycle when a noise is detected. 
         [0010]    Yet another object of the present invention is to provide a control circuit and noise removal method for a touch screen, which remove noises by performing periodic integration on a differential sensing signal for detecting a change of sensing signals output by sensing lines of a touch screen panel and performing the integration using a differential sensing signal included in a cycle before a noise is detected in the sensing signal when the noise is detected. 
         [0011]    Yet another object of the present invention is to provide a control circuit and noise removal method for a touch screen, which simultaneously perform the periodic delay and storage of a differential sensing signal for detecting a change of sensing signals output by sensing lines of a touch screen panel, integrate the delayed differential sensing signals, and perform integration using a differential sensing signal stored in a cycle before a noise is detected when the noise is detected in the sensing signals to be output for the integration. 
         [0012]    Furthermore, Yet another object of the present invention is to provide a control circuit and noise removal method for a touch screen, which simultaneously perform the delay and storage of a differential sensing signal for detecting a change of sensing signals output by sensing lines of a touch screen panel, integrate the delayed differential sensing signals, block the storage of a differential sensing signal corresponding to a sensing signal from which a noise has been detected if the noise is detected in the sensing signal, and perform the integration using a differential sensing signal stored in accordance with the sensing signal of the last cycle in which a noise has not been detected. 
         [0013]    The noise removal method of a control circuit for a touch screen in accordance with the present invention includes a differential sensing signal generation step of periodically generating a differential sensing signal for the sensing signals of two adjacent sensing lines of a touch screen panel; a differential distribution voltage storage step of storing the differential sensing signal as a first differential distribution voltage and a second differential distribution voltage for each cycle; a noise detection step of detecting a noise in the one or more sensing signals for each cycle; and a signal processing step of performing integration for each cycle, selecting a first differential distribution voltage corresponding to a cycle to which a sensing signal in which a noise is determined to be detected corresponds if the noise is not detected, performing integration on the selected first differential distribution voltage, selecting a second differential distribution voltage corresponding to the sensing signal of a cycle prior to the cycle to which the sensing signal in which the noise is determined to be detected corresponds if the noise is detected, and performing the integration on the second differential distribution voltage. 
         [0014]    Furthermore, a control circuit for a touch screen in accordance with the present invention includes a differential sensing unit which periodically generates a differential sensing signal for the sensing signals of two adjacent sensing lines of a touch screen panels; a noise detection unit which cyclically detects a noise in at least one of the sensing signals; a delay unit which comprises first and second delay elements, performs charging of the differential sensing signal and output of the charged differential sensing signal as a first differential distribution voltage on each of the first and the second delay elements, periodically alternately performs the charging and output of the differential sensing signal on the first and the second delay elements, and outputs the first differential distribution voltage when a noise is not detected in the sensing signal by the noise detection unit; a storage unit which comprises a plurality of charging elements, sequentially performs charging of the differential sensing signals periodically provided by the delay unit on the plurality of charging elements, selects a second differential distribution voltage that corresponds to the sensing signal of a cycle prior to a cycle to which a sensing signal in which a noise is determined to be detected corresponds when the noise is detected in the sensing signal by the noise detection unit from the plurality of charging elements, and outputs the selected second differential distribution voltage; and an integration unit which integrates the first differential distribution voltage of the delay unit and the second differential distribution voltage of the storage unit. 
         [0015]    In accordance with the present invention, there are advantages in that a burden of a subsequent digital processor can be reduced and a portion where a touch is generated can be accurately recognized by previously removing several noises that may affect a touch screen at an Analog Front End (AFE) stage. 
         [0016]    Furthermore, in accordance with the present invention, a display noise in common applied to adjacent sensing lines can be filtered by performing differential sensing on two adjacent sensing lines of a touch screen panel, and periodic noises can be filtered in a differentially sensed signal using a moving average method. 
         [0017]    Furthermore, in accordance with the present invention, there are advantages in that a charging circuit for integration can be configured using a feedback capacitor having low capacitance and an additional circuit for compensating for path delay is not required because noise filtering is performed based on a comparison between adjacent sensing lines. 
         [0018]    Furthermore, in accordance with the present invention, there is an advantage in that a charger noise is filtered by performing blocking in response to the detection of a noise in a process of periodically storing sensing signals output by the sensing lines of a touch screen panel and integrating stored voltages. 
         [0019]    In accordance with the present invention, there is an advantage in that a differential sensing signal corresponding to a sensing signal in a cycle including a noise is prevented from being incorporated into integration for recognizing a touch in a process of performing the integration when a noise, in particular, a charger noise generated when a battery is charged is included in a sensing signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIG. 1  is a circuit diagram illustrating an embodiment of a control circuit for a touch screen in accordance with the present invention. 
           [0021]      FIG. 2  is a conceptual diagram of the embodiment of FIG.  1 . 
           [0022]      FIG. 3  is a circuit diagram illustrating another embodiment of the control circuit for a touch screen in accordance with the present invention. 
           [0023]      FIG. 4  illustrating the waveforms of respective nodes in the embodiment of  FIG. 3 . 
           [0024]      FIG. 5  is a circuit diagram illustrating an embodiment in which path switches have been added to the embodiment of  FIG. 3 . 
           [0025]      FIG. 6  is a circuit diagram for simulating response characteristics in accordance with an embodiment of the present invention with respect to a variety of types of noises introduced into a touch screen. 
           [0026]      FIG. 7  is a graph illustrating the results of computer simulations for the circuit of  FIG. 6 . 
           [0027]      FIG. 8  is a graph illustrating the response characteristics of the embodiments of  FIGS. 1 and 3 . 
           [0028]      FIG. 9  is a graph illustrating the response characteristic of a sensing line prior to differential sensing in the embodiments of  FIGS. 1 and 3 . 
           [0029]      FIG. 10  is a graph illustrating the response characteristic of a sensing line after integration in the embodiments of  FIGS. 1 and 3 . 
           [0030]      FIG. 11  is a flowchart illustrating an embodiment of a noise removal method for a touch screen in accordance with the present invention. 
           [0031]      FIG. 12  is a block diagram illustrating yet another embodiment of the control circuit for a touch screen in accordance with the present invention. 
           [0032]      FIG. 13  is a detailed circuit diagram of the control circuit for a touch screen illustrated in  FIG. 12 . 
           [0033]      FIG. 14  is a circuit diagram an embodiment of a comparator illustrated in  FIG. 13 . 
           [0034]      FIG. 15  is a circuit diagram another embodiment of the comparator illustrated in  FIG. 13 . 
           [0035]      FIG. 16  is a circuit diagram an embodiment of a comparison circuit illustrated in  FIG. 15 . 
           [0036]      FIG. 17  is a circuit diagram an embodiment of the comparison circuit illustrated in  FIG. 15 . 
           [0037]      FIG. 18  is a diagram illustrating the relationship between comparison voltages determined based on two sensing signals, the highest voltage, and the lowest voltage. 
           [0038]      FIG. 19  is a graph obtained based on the results of the simulations in the embodiment of  FIG. 12 . 
           [0039]      FIG. 20  is a flowchart illustrating another embodiment of the noise removal method for a touch screen in accordance with the present invention. 
           [0040]      FIG. 21  is a block diagram illustrating yet another embodiment of the control circuit for a touch screen in accordance with the present invention. 
           [0041]      FIG. 22  is a detailed circuit diagram of the control circuit for a touch screen illustrated in  FIG. 21 . 
           [0042]      FIG. 23  illustrating the waveforms of signals used in the embodiment of  FIG. 22 . 
           [0043]      FIGS. 24 to 26  are circuit diagrams illustrating the operation of the control circuit when a noise is not detected. 
           [0044]      FIGS. 27 to 29  are circuit diagrams illustrating the operation of the storage unit of the control circuit of  FIG. 22  when a noise is detected. 
           [0045]      FIG. 30  is a circuit diagram illustrating another embodiment of the storage unit in the embodiment of  FIG. 21 . 
           [0046]      FIG. 31  illustrating the waveforms of signals used in  FIG. 30 . 
           [0047]      FIGS. 32 and 33  are circuit diagrams illustrating the operation of the storage unit of  FIG. 30  when a noise is not detected. 
           [0048]      FIGS. 34 and 35  are circuit diagrams illustrating the operation of the storage unit of  FIG. 30  when a noise is detected. 
           [0049]      FIG. 36  is a diagram illustrating the concept of integration for a differential sensing signal according to the use of the storage unit of  FIG. 22 . 
           [0050]      FIG. 37  is a diagram illustrating the concept of integration for a differential sensing signal according to the use of the storage unit of  FIG. 30 . 
       
    
    
     DETAILED DESCRIPTION 
       [0051]    Preferred embodiments of the present invention are described in more detail below with reference to the accompanying drawings, the same reference numerals proposed in the drawings denote the same elements. 
         [0052]      FIG. 1  is a circuit diagram illustrating an embodiment of a control circuit for a touch screen in accordance with the present invention. 
         [0053]    In  FIG. 1 , a touch screen panel  10  and a control circuit  100  for a touch screen are configured. 
         [0054]    The touch screen panel  10  includes a plurality of driving lines to which driving signals Tx are applied and a plurality of sensing lines D 1 , D 2  coupled with the driving lines with an insulating substance interposed therebetween. The control circuit  100  for a touch screen receives the sensing signals of the two adjacent sensing lines D 1 , D 2 , performs a function for detecting whether there is a touch on the touch screen panel  10 , and includes a differential sensing unit  110  and an integration unit  120 . 
         [0055]    The differential sensing unit  110  generates a delta value, that is, a difference value between charges Q 1 , Q 2  charged in the two adjacent sensing lines D 1 , D 2  of the touch screen panel  10 . The integration unit  120  integrates the outputs (delta values) of the differential sensing unit  110 . Hereinafter, the charges Q 1 , Q 2  charged in the sensing lines D 1 , D 2  mean the sensing signals of the sensing lines D 1 , D 2 . 
         [0056]    The differential sensing unit  110  is configured to include a delta value generator  111  and switches S 1 ˜S 4 . 
         [0057]    The switches S 1 , S 3  form a transfer circuit that transfers the sensing signal of the sensing line D 1  to the delta value generator  111 . The switches S 2 , S 4  form a transfer circuit that transfers the sensing signal of the sensing line D 2  to the delta value generator  111 . 
         [0058]    The switch S 1  is connected between the sensing line D 1  and the positive input terminal + of the delta value generator  111 , and switches the transfer of the charges Q 1  charged in the sensing line D 1  to the positive input terminal + of the delta value generator  111  in response to a second lead signal  2 . The switch S 2  is connected between the sensing line D 2  and the negative input terminal − of the delta value generator  111 , and switches the transfer of the charges Q 2  charged in the sensing line D 2  to the negative input terminal − of the delta value generator  111  in response to the second lead signal  2 . The switch S 3  is connected to a node between the sensing line D 1  and the switch S 1 , and switches the transfer of a ground voltage GND to the positive input terminal + of the delta value generator  111  in response to a first lead signal  1 . The switch S 4  is connected to a node between the sensing line D 2  and the switch S 2 , and switches the transfer of the ground voltage to the negative input terminal − of the delta value generator  111  in response to the first lead signal  1 . In this case, the second lead signal  2  may be defined as a signal having the same amount as the first lead signal  1  and having a phase opposite to that of the first lead signal  1 . Furthermore, the first lead signal  1  and the second lead signal  2  preferably are two non-overlap phase signals having different phases. The driving signal Tx may be used as the first lead signal  1  according to circumstances. 
         [0059]    The delta value generator  111  generates a delta value corresponding to a difference value Q 1 −Q 2  between charges input to the positive input terminal + and the negative input terminal −, and may be formed of a differential sensor. 
         [0060]    The integration unit  120  is configured to include a differential amplifier  121 , a reference voltage source  122 , a feedback capacitor Cf, and switches S 5 ˜S 7 . The switch S 5  is connected between the output terminal of the delta value generator  111  and the negative input terminal − of the differential amplifier  121 , and switches the transfer of a delta value, output by the delta value generator  111 , to the negative input terminal − of the differential amplifier  121  in response to the second lead signal  2 . The switch S 6  is connected to a node between the output terminal of the delta value generator  111  and the switch S 5 , and switches the transfer of the reference voltage Vref of the reference voltage source  122  to the negative input terminal − of the differential amplifier  121  in response to the first lead signal  1 . The reference voltage Vref is applied to the positive input terminal + of the differential amplifier  121 . The feedback capacitor Cf and the switch S 7  are configured to be connected in parallel between the negative input terminal − and output terminal of the differential amplifier  121 . The switch S 7  electrically connects the negative input terminal − of the differential amplifier  121  and the output terminal of the differential amplifier  121  in response to a reset signal  3 . 
         [0061]    The equivalent circuit of the touch screen panel  10  illustrated in  FIG. 1  is commonly known, and a detailed description thereof is omitted. A capacitor in which the plurality of driving lines to which the driving signals Tx are applied and the plurality of sensing lines D 1 , D 201  from which the sensing signals are output are coupled is indicated by Cm. Furthermore, the line resistance of each of the driving lines and the line resistance of each of the sensing lines D 1 , D 2  are indicated by Rd and Rs, respectively. Parasitic capacitors formed in the driving lines and the sensing lines D 1 , D 2  are indicated by Cd and Cs, respectively. 
         [0062]    In the embodiment illustrated in  FIG. 1 , in order to remove a display noise that in common affects the two adjacent sensing lines D 1 , D 2 , a delta value (=Q 1 −Q 2 ), that is, a difference between the charges Q 1 , Q 2  charged in the two sensing lines D 1 , D 2 , is sensed. The sensing of the delta value is performed by the differential sensing unit  110 . 
         [0063]    A display noise that in common affects the two adjacent sensing lines D 1 , D 2  as in the embodiment of  FIG. 1  may be filtered by the differential sensing of the differential sensing unit  110 . 
         [0064]    Furthermore, in the embodiment illustrated in  FIG. 1 , the integration unit  120  may filter a noise having periodicity by performing a moving average method for repeatedly cyclically integrating the delta values (=Q 1 −Q 2 ), that is, differential sensing signals output by the differential sensing unit  110 . 
         [0065]      FIG. 2  is a diagram illustrating the operating concept of the embodiment of  FIG. 1 .  FIG. 2  describes the concept of the embodiment of  FIG. 1  in which a delta value Q is obtained using a difference Q 1 −Q 2  between the two charges Q 1 , Q 2  charges in the two sensing lines of the touch screen panel  10  and such delta values are integrated. 
         [0066]      FIG. 3  illustrates another embodiment of the control circuit for a touch screen in accordance with the present invention. The control circuit  300  for a touch screen of  FIG. 3  includes a differential sensing unit  310  and an integration unit  320 . 
         [0067]    The differential sensing unit  310  includes filter units  311 ,  313 , a differential sensor  315 , and a path switch  316 . 
         [0068]    The filter unit  311  removes a noise introduced from a sensing line D 1 . The filter unit  313  removes a noise introduced form a sensing line D 2 . The differential sensor  315  generates a delta value corresponding to a difference Q 1 −Q 2  between sensing signals output by the filter units  311 ,  313  and corresponds to the delta value generator  111  of  FIG. 1 . The path switch  316  interchangeably applies the outputs of the filter units  311 ,  313  having a negative value to the two input terminals +, − of the differential sensor  315 . 
         [0069]    The filter unit  311  includes an amplifier  312 . The amplifier  312  has a negative input terminal − connected to the sensing line D 1  and has a positive input terminal + supplied with a reference voltage Vref. A feedback resistor Rf 1  and a feedback capacitor Cf 1  that are connected in parallel are connected between the negative input terminal − and output terminal of the amplifier  312 . 
         [0070]    The filter unit  313  includes an amplifier  314 . The amplifier  314  has a negative input terminal − connected to the sensing line D 2  and has a positive input terminal + supplied with the reference voltage Vref. A feedback resistor Rf 2  and a feedback capacitor Cf 2  that are connected in parallel are connected between the negative input terminal − and output terminal of the amplifier  314 . 
         [0071]    The differential sensor  315  has a positive input terminal + connected to the output terminal of the filter unit  311  and has a negative input terminal − connected to the output terminal of the filter unit  313 . The differential sensor  315  may be implemented using an Operational Transconductance Amplifier (OTA) for outputting a delta value to its output terminal. 
         [0072]    The path switch  316  performs an operation for exchanging input signals so that the integrator  320  has unilateral output. Signals output by the sensing lines D 1 , D 2  in response to a touch on the touch screen panel  10  have a pattern in which a positive value and a negative value are repeated. The path switch  316  transfers a signal that belongs to input signals from the filter units  311 ,  313  and that has a positive value without any change, changes the polarity of a signal that belongs to the input signals from the filter units  311 ,  313  and that has a negative value so that the signal has a positive value, and transfers the signal having the changed polarity. Accordingly, the integrator  320  for integrating the outputs of the differential sensor  315  can always have unilateral output due to the above action of the path switch  316 . 
         [0073]    The integration unit  320  for integrating delta values output by the differential sensing unit  310  includes a differential amplifier  321 . The differential amplifier  321  has a positive input terminal + connected to the reference voltage Vref and has a negative input terminal − supplied with a delta value, that is, the output of the differential sensor  315 . A feedback capacitor Cf and a reset switch S 8  that are connected in parallel are connected between the negative input terminal − and output terminal of the differential amplifier  321 . The reset switch S 8  switches an electrical connection between the output terminal and negative input terminal − of the differential amplifier  321  in response to a reset signal. 
         [0074]      FIG. 4  illustrating the waveforms of respective nodes in the embodiment of  FIG. 3 . 
         [0075]      FIG. 4(   a ) is the output signal of the filter unit  311 ,  FIG. 4(   b ) is the output signal of the filter unit  313 ,  FIG. 4(   c ) is the output signal of the differential sensor  315 , and  FIG. 4(   d ) is the output signal of the integration unit  320 . 
         [0076]    In the embodiment of  FIG. 3  in accordance with the present invention, a differential sensing signal, such as that of  FIG. 4(   c ), is output in response to a difference between the signals of  FIGS. 4(   a ) and  4 ( b ) applied by the two sensing lines D 1 , D 2 . The differential sensing signals, that is, the delta values are converted into integration signals having a specific size, such as that of  FIG. 4(   d ), through the integration unit  320 . 
         [0077]      FIG. 3  illustrates that a single path switch  316  has been installed. However, this is for convenience of description and the simplification of the drawings, and various embodiments are possible in terms of the installation of the path switch. 
         [0078]      FIG. 5  illustrates an embodiment in which path switches have been added to the embodiment of  FIG. 3 . 
         [0079]    When comparing  FIG. 5(   a ) with  FIG. 3 , a single path switch  331  may be further added between the differential sensor  315  and the two filter units  311 ,  313 , and another path switch  332  may be added within the differential sensor  315 . Furthermore, a path switch  333  may be added to the two input terminals of the amplifier  321  that forms the integration unit  320 . A path switch  334  may also be added within the amplifier  321 . In this case, the existing path switch  316  and the added path switch  331  included in an ellipse are offset. As a result, as illustrated in  FIG. 5(   b ), the present embodiment may have a configuration in which the two path switches  316 ,  331  are removed by an offset effect and only the three path switches  332 ,  333 ,  334  are installed. 
         [0080]    The control circuit for a touch screen in accordance with the present invention can effectively obtain an integration signal from which a periodic noise has been filtered because odd-numbered path switches are installed as illustrated in  FIGS. 3 and 5 . 
         [0081]    For reference,  FIG. 4  illustrates common touch signals in response characteristics in accordance with an embodiment of the present invention. The response characteristics of noises according to an embodiment are described below. 
         [0082]      FIG. 6  is a circuit diagram for simulating response characteristics in accordance with an embodiment of the present invention with respect to a variety of types of noises introduced into a touch screen. 
         [0083]    In  FIG. 6 , it is assumed that a noise Vn and a display noise Vdn including a 60 Hz noise applied through a finger when a user touches a touch screen and a three-wavelength noise of 40 kHz have been applied to a touch screen panel to which the embodiment has been applied. The circuit of  FIG. 6  is the same as the circuit of  FIG. 3 . The characteristics and introduction paths of a variety of types of noises are well known, and thus a detailed description is omitted. In  FIG. 6 , Vcom means the common electrode of a display panel (not illustrated). The display noise Vdn may be introduced into the touch screen panel when the common electrode is coupled with the touch screen panel. 
         [0084]      FIG. 7  illustrates the results of computer simulations for the circuit illustrated in  FIG. 6 . 
         [0085]    If a variety of types of noises have been introduced as illustrated in  FIG. 6 , a difference V 2 −V 1  between the output signal V 1  of the filter unit  311  and the output signal V 2  of the filter unit  313  illustrated at the bottom of  FIG. 7  may be aware from the output signal of the differential sensor  315  illustrated in the middle of  FIG. 7 . From the output signal Vo of the integration unit  320  having a specific slope as illustrated at the top of  FIG. 7 , it may be seen that although a variety of types of noises have been introduced, output in accordance with an embodiment of the present invention is rarely influenced. Noises are included in the output signal Vo of the integration unit  320 , but may have negligible amount. 
         [0086]      FIG. 8  illustrates the response characteristics of the embodiments of  FIGS. 1 and 3 . 
         [0087]    The lower part of  FIG. 8  illustrates the results of the response characteristics of the control circuit  100  for a touch screen illustrated in  FIG. 1 . The upper part of  FIG. 8  illustrates the results of the response characteristics of the control circuit  300  for a touch screen illustrated in  FIG. 3 . 60 Hz noises of a 4V peak-to-peak voltage and three-wavelength kHz noises of a 10V peak-to-peak voltage have been introduced into the entire section. Display noises have been introduced into only the beginning and last parts. 
         [0088]    It may be seen that the control circuit  300  that is illustrated in  FIG. 3  and in which all of a variety of types of noises have been taken into consideration has better response characteristics than the control circuit  100  illustrated in  FIG. 1  and focused on display noises. 
         [0089]    The control circuit for a touch screen in accordance with the present invention proposes the first embodiment in which delta values for a difference between the charges of two sensing lines are integrated as illustrated in  FIG. 1  and the second embodiment in which each of two sensing lines is filtered and delta values for a difference between the filtered charges are integrated as illustrated in  FIG. 3 . From  FIG. 8 , it may be seen that the second embodiment has better response characteristics than the first embodiment. 
         [0090]    In the second embodiment, an area occupied by the circuits is increased because filter units need to be added. Accordingly, a product according to a required embodiment needs to be applied by taking into consideration the advantages and disadvantages of the first embodiment and the second embodiment. 
         [0091]      FIG. 9  illustrates response characteristics in accordance with an embodiment of the present invention prior to differential sensing, and  FIG. 10  illustrates response characteristics in accordance with an embodiment of the present invention right after integration. 
         [0092]    From  FIG. 9 , it may be seen that the size of a response waveform prior to differential sensing if the distance between the sensing line D 2  and the control circuit is the shortest (V 2 -best) and the size of a response waveform prior to differential sensing if the distance between the sensing line D 2  and the control circuit is the shortest (V 2 -worst) is the longest have a difference. 
         [0093]    In contrast, from  FIG. 10 , it may be seen that a difference between integrated response waveforms is not great although there is a difference between the sizes of the response waveforms prior to differential sensing. 
         [0094]    The control circuit for a touch screen in accordance with the present invention may have an improved SNR characteristic because noises introduced when a user touches a touch screen are removed by the two filter units having bandpass filter characteristics as illustrated in  FIG. 3 , display noises are filtered by the differential sensing unit, and delta values output by the differential sensing unit are integrated. 
         [0095]    Referring to  FIG. 3 , the control circuit for a touch screen in accordance with the present invention is advantageous in that a moving average effect is improved because integration is performed at the falling edge of the driving signal Tx as well as at the rising edge of the driving signal Tx. 
         [0096]      FIG. 11  is a flowchart illustrating a noise removal method for a touch screen in accordance with the present invention.  FIG. 12  is a block diagram illustrating yet another embodiment of the control circuit for a touch screen in accordance with the present invention. The control circuit for a touch screen illustrated in  FIG. 12  may be implemented as illustrated in  FIG. 11 . 
         [0097]    A noise removal method S 100  of  FIG. 11  discloses a method of filtering charger noises applied by a touch screen panel and includes a differential sensing signal generation step S 120 , a differential sensing signal storage step S 130 , a noise detection step S 140 , and signal processing steps S 150 , S 160 . 
         [0098]    In the differential sensing signal generation step S 120 , a differential sensing signal corresponding to a difference between the sensing signals of two adjacent sensing lines D 1 , D 2  of the touch screen panel is generated in a predetermined cycle. In the differential sensing signal storage step S 130 , the differential sensing signal generated for each cycle in the differential sensing signal generation step S 120  is stored. In the noise detection step S 140 , whether a noise is applied to the two sensing lines D 1 , D 2  is determined for each cycle. In the signal processing steps S 150 , S 160 , operations are difference based on a result of the detection of a noise. If a noise is determined to be not applied, a differential sensing signal stored in a previous cycle is transferred for integration (S 150 ). In contrast, if a noise is determined to be applied, the differential sensing signal is not transferred for integration and is blocked (S 160 ). 
         [0099]    In the noise removal method S 100  of  FIG. 11 , sensing signals applied by the two adjacent sensing lines D 1 , D 2  of the touch screen panel are generated into a differential sensing signal, delayed by one cycle, and then transferred. While the transfer of the differential sensing signal is delayed, whether a noise is included in the sensing signals applied by the sensing lines D 1 , D 2  is determined. 
         [0100]    If the noise detection unit  230  determines that a noise is not included in the sensing signals applied by the sensing lines D 1 , D 2 , the delay unit  240  transfers a differential sensing signal that has been input and stored for delay in a previous cycle other than a differential sensing signal that has been currently input and stored to a subsequent signal processing stage (S 150 ). The integration unit  250  integrates signals provided by the delay unit  240 . 
         [0101]    If the noise detection unit  230  determines that a noise is included in the sensing signals applied by the sensing lines D 1 , D 2 , the delay unit  240  blocks the transfer of a differential sensing signal that has been input and stored for delay in a previous cycle to a subsequent signal processing stage. As a result, a noise can be filtered in a step prior to the signal processing of the integration unit  250 . 
         [0102]    In the initial value setting step S 110  of  FIG. 11 , a value assigned to a variable i is reset to 1, and differential sensing signal  0  stored in a cycle prior to a current step (i=1) is reset to 0. Furthermore, in a variable increase step S 170 , the variable i is increased by 1 after a series of the processes S 120  to S 160  are performed. 
         [0103]    The control method of  FIG. 11  may be implemented by the control circuits of  FIGS. 12 and 13 .  FIG. 12  includes the touch screen panel  10  and a control circuit  200 . 
         [0104]    The control circuit  200  may include a differential sensing unit  220 , a noise detection unit  230 , a delay unit  240 , and an integration unit  250 . 
         [0105]    The control circuit  200  may illustratively include a switching block  210 . The switching block  210  may be configured to select the charges of two adjacent sensing lines D 1 , D 2  of the sensing lines of the touch screen panel  10  and output the selected charges. For example, the switching block  210  may select a sensing line at a specific location and a sensing line adjacent to the sensing line on one side in one cycle (called an odd cycle) and select a sensing line at a specific location and a sensing line adjacent to the sensing line on the other side in a next cycle (called an even cycle). Furthermore, the switching block  210  may perform switching for selecting the two adjacent sensing lines D 1 , D 2  while repeating the odd cycle and the even cycle. 
         [0106]    The differential sensing unit  220  senses a difference between the sensing signals of the two sensing lines D 1 , D 2  and generates a differential sensing signal DS_O. The noise detection unit  230  generates a first noise detection signal S_B and a second noise detection signal S_BB that are enabled when a noise is applied to at least one of the two sensing lines D 1 , D 2 . The second noise detection signal S_BB is a signal having the same size as the first noise detection signal S_B and having a phase opposite that of the first noise detection signal S_B. The delay unit  240  stores the differential sensing signal DS_O for each cycle for delay in response to the first noise detection signal S_B and the second noise detection signal S_BB and transfers the differential sensing signal DS_O, stored in a previous cycle, to the integration unit  250  or blocks the differential sensing signal DS_O. The integration unit  250  outputs a value S_RO obtained by integrating a differential sensing signal Del_O transferred by the delay unit  240 . 
         [0107]      FIG. 13  is a detailed circuit diagram of the embodiment of  FIG. 12 . 
         [0108]    In  FIG. 13 , the differential sensing unit  220  generates the differential sensing signal DS_O corresponding to a difference between the sensing signals of the two sensing lines D 1 , D 2 , and may be implemented using various forms of circuits depending on input/output characteristics. In  FIG. 13 , the differential sensing unit  220  may include a differential sensor  221  for generating the differential sensing signal DS_O corresponding to a difference value between charges input to the positive input terminal + and negative input terminal − of the differential sensor  221 . 
         [0109]    The noise detection unit  230  may include a comparator  231 , a NOR gate  232 , a clock generator  233 , a delay unit  234 , a D flip-flop  235 , an SR flip-flop  236 , and a D flip-flop  237 . 
         [0110]    The comparator  231  generates a comparison voltage OH and comparison voltage OL whose values are determined depending on whether the sensing signals of the two sensing lines D 1 , D 2  fall within a predetermined range of the highest voltage VH and the lowest voltage VL. To this end, the comparator  231  may be configured using a multi-input window comparator. 
         [0111]    The NOR gate  232  performs logical OR on the comparison voltage OH and the comparison voltage OL, inverts a result of the logical OR, and outputs the inverted result. 
         [0112]    The clock generator  233  generates a first clock signal CLK and a second clock signal CLKB, that is, a two-phase non-overlapping signal, using a signal output by the NOR gate  232 . 
         [0113]    The delay unit  234  may be configured to delay one of the first clock signal CLK and the second clock signal CLLK for a specific time.  FIG. 13  illustrates that the first clock signal CLK is delayed. 
         [0114]    The D flip-flop  235  is reset by the second clock signal CLKB. The D flip-flop  235  has an input terminal D supplied with an operating voltage VDD and has a clock input terminal supplied to a third clock signal CLK 1 . 
         [0115]    The SR flip-flop  236  has a set input terminal S supplied with a signal output by the delay unit  234  and has a reset input terminal R supplied with a signal output by the output terminal Q of the D flip-flop  235 . 
         [0116]    The D flip-flop  237  has an input terminal D supplied with a signal output by the output terminal Q of the SR flip-flop  236  and has a clock terminal supplied with a fourth clock signal CLK 2 . The first noise detection signal S_B is output by the output terminal Q of the D flip-flop  237 , and the second noise detection signal S_BB is output by the output terminal QB of the D flip-flop  237 . 
         [0117]    In this case, the cycle of the third clock signal CLK 1  and the fourth clock signal CLK 2  may be two times an integration cycle. The phase of the fourth clock signal CLK 2  preferably is a specific time earlier than that of the third clock signal CLK 1 . 
         [0118]    In accordance with the configuration, the noise detection unit  230  outputs the first noise detection signal S_B and the second noise detection signal S_BB in response to the sensing signals of the two sensing lines D 1 , D 2  that are delayed for one cycle. 
         [0119]    The delay unit  240  may include an amplifier  241 , delay capacitors C PD1 , C PD2 , and switches S 11  to S 20 . 
         [0120]    The amplifier  241  has a negative input terminal − supplied with the differential sensing signal DS_O and has a positive input terminal supplied with a reference voltage Vref. The delay capacitors C PD1 , C PD2  are configured in parallel between the negative input terminal − and output terminal of the amplifier  241 . The switch S 11  is connected between the negative input terminal − of the amplifier  241  and the delay capacitor C PD1 , and switches the transfer of the differential sensing signal DS_O to the delay capacitor C PD1  in response to the second lead signal  2 . The switch S 14  is connected between the negative input terminal − of the amplifier  241  and the delay capacitor C PD2 , and switches the transfer of the differential sensing signal DS_O to the delay capacitor C PD2  in response to the first lead signal  1 . The switch S 13  switches the application of a ground voltage to the delay capacitor C PD1  in response to the first lead signal  1 . The switch S 16  switches the application of the ground voltage to the delay capacitor C PD2  in response to the second lead signal  2 . The switch S 12  is connected between the output terminal of the amplifier  241  and the delay capacitor C PD1 , and switches a path for storing the differential sensing signal DS_O in the delay capacitor C PD2  in response to the second lead signal  2 . The switch S 15  is connected between the output terminal of the amplifier  241  and the delay capacitor C PD2 , and switches a path for storing the differential sensing signal DS_O in the delay capacitor C PD2  in response to the first lead signal  1 . The switch S 17  is connected to the delay capacitor C PD1  in parallel to the switch S 12 , and switches a path for transferring the differential sensing signal DS_O of the delay capacitor C PD1  for integration in response to the first lead signal  1 . The switch S 18  is connected to the delay capacitor C PD2  in parallel to the switch S 15 , and switches a path for transferring the differential sensing signal DS_O of the delay capacitor C PD2  for integration in response to the second lead signal  2 . The switch S 19  switches the connection of a node at which the switch S 17  and the switch S 18  are in common connected to the integration unit  250  in response to the first noise detection signal S_B. Furthermore, the switch S 20  switches the transfer of the reference voltage Vref between the node at which the switch S 17  and the switch S 18  are in common connected and the switch S 19  in response to the second noise detection signal S_BB. 
         [0121]    The integration unit  250  includes an amplifier  251  and includes a feedback capacitor C F  and a switch S 21  connected in parallel between the negative input terminal − and output terminal of the amplifier  251 . The amplifier  251  has a negative input terminal − supplied with the differential sensing signal Del_O transferred by the delay unit  240  and has a positive input terminal + supplied with the reference voltage Vref. The switch S 21  discharges the feedback capacitor C F  in response to a reset signal. 
         [0122]      FIG. 14  is an embodiment of the comparator  231  illustrated in  FIG. 13 . 
         [0123]    Referring to  FIG. 14 , the comparator  231  includes comparison circuits  401 ,  402 ,  403 ,  404 , an OR gate  405 , and an NAND gate  406 . 
         [0124]    The comparison circuit  401  compares the sensing signal of the sensing line D 1  of the two sensing lines D 1 , D 2  with the highest voltage VH and generates a middle comparison voltage O 1 . The comparison circuit  402  compares the sensing signal of the sensing line D 2 , that is, the remaining one of the two sensing lines D 1 , D 2 , with the highest voltage VH and generates a middle comparison voltage O 2 . The comparison circuit  403  compares the sensing signal of the sensing line D 1  of the two sensing lines D 1 , D 2  with the lowest voltage VL and generates a middle comparison voltage O 3 . The comparison circuit  404  compares the sensing signal of the sensing line D 2 , that is, the remaining one of the two sensing lines D 1 , D 2 , with the lowest voltage VL and generates a middle comparison voltage O 4 . The OR gate  405  generates a comparison voltage OH by performing logical OR on the outputs Q 1 , Q 2  of the comparison circuit  401  and the comparison circuit  402 . The NAND gate  406  performs logical AND on the outputs O 3 , O 4  of the comparison circuit  403  and the comparison circuit  404  and generates a comparison voltage OL inverted from a result of the logical AND. 
         [0125]      FIG. 15  is another embodiment of the comparator illustrated in  FIG. 13 . 
         [0126]    Referring to  FIG. 15 , the comparator  231  includes comparison circuits  501 ,  502 , an OR gate  505 , and an NAND gate  506 . 
         [0127]    The comparison circuit  501  compares the sensing signals of the two sensing lines D 1 , D 2  with the highest voltage VH and generates a middle comparison voltage O 1  and a middle comparison voltage O 2 . The comparison circuit  502  compares the sensing signals of the two sensing lines D 1 , D 2  with the lowest voltage VL and generates a middle comparison voltage O 3  and a middle comparison voltage O 4 . The OR gate  505  generates a comparison voltage OH by performing logical OR on the middle comparison voltage O 1  and the middle comparison voltage O 2 . The NAND gate  506  performs logical AND on the middle comparison voltage O 3  and the middle comparison voltage and generates a comparison voltage OL inverted from a result of the logical AND. 
         [0128]    The comparator illustrated in  FIG. 15  is different from the comparator illustrated in  FIG. 14  in that it uses the two comparison circuits, but the comparator illustrated in  FIG. 14  uses the four comparison circuits. If there is a burden on using the four comparison circuits in terms of the design, a manufacturer may selectively use two comparison circuits as illustrated in  FIG. 15 . 
         [0129]      FIG. 16  is an embodiment of the comparison circuit  501  illustrated in  FIG. 15 . 
         [0130]    Referring to  FIG. 16 , the comparison circuit  501  illustrated in  FIG. 15  may include a single current source I ds1  and 12 MOS transistors M 1 ˜M 12 . 
         [0131]    The MOS transistor M 1  has one terminal supplied with the operating voltage VDD and has a gate terminal connected to the other terminal of the MOS transistor M 1 . The MOS transistor M 2  has one terminal connected to the other terminal of the MOS transistor M 1  and has a gate terminal supplied with the sensing signal of the sensing line D 1 . The MOS transistor M 3  has one terminal supplied with the operating voltage VDD and has a gate terminal connected to the other terminal of the MOS transistor M 3 . The MOS transistor M 4  has one terminal connected to the other terminal of the MOS transistor M 3  and has a gate terminal supplied with the sensing signal of the sensing line D 2 . The MOS transistor M 5  has one terminal supplied with the operating voltage VDD and has a gate terminal connected to the other terminal of the MOS transistor M 5 . The MOS transistor M 6  has one terminal connected to the other terminal of the MOS transistor M 5  and has a gate terminal supplied with the highest voltage VH. 
         [0132]    The current source I ds1  is connected to the MOS transistor M 2 , the MOS transistor M 4 , and the MOS transistor M 6  in common. 
         [0133]    The MOS transistor M 7  has one terminal supplied with the operating voltage VDD and has a gate terminal connected to the gate terminal of the MOS transistor M 5 . The MOS transistor M 8  has one terminal and a gate terminal connected to the other terminal of the MOS transistor M 7  and has the other terminal connected to the ground voltage GND. The MOS transistor M 9  has one terminal supplied with the operating voltage VDD and has a gate terminal connected to the gate terminal of the MOS transistor M 3 . The MOS transistor M 10  has one terminal connected to the other terminal of the MOS transistor M 9 , has the other terminal connected to the ground voltage GND, and has a gate terminal connected to the gate terminal of the MOS transistor M 8 . The MOS transistor M 11  has one terminal supplied with the operating voltage VDD and has a gate terminal connected to the gate terminal of the MOS transistor M 1 . The MOS transistor M 12  has one terminal connected to the other terminal of the MOS transistor M 11 , has the other terminal connected to the ground voltage GND, and has a gate terminal connected to the gate terminal of the MOS transistor M 8 . 
         [0134]    The middle comparison voltage O 1  is output through a node at which the MOS transistor M 11  and the MOS transistor M 12  are connected. The middle comparison voltage O 2  is output through a node at which the MOS transistor M 9  and the MOS transistor M 10  are connected. 
         [0135]    In the comparison circuit  501  illustrated in  FIG. 16 , the MOS transistor M 1 , the MOS transistor M 3 , the MOS transistor M 5 , the MOS transistor M 7 , the MOS transistor M 9 , and the MOS transistor M 11  are P type MOS transistors, and all the remaining MOS transistors are N type MOS transistors. 
         [0136]      FIG. 17  is an embodiment of the comparison circuit  502  illustrated in  FIG. 15 . 
         [0137]    Referring to  FIG. 17 , the comparison circuit  502  includes a single current source I ds2  and 12 MOS transistors M 21 ˜M 32 . 
         [0138]    The MOS transistor M 21  has one terminal connected to the ground voltage GND and has a gate terminal connected to the other terminal of the MOS transistor M 21 . The MOS transistor M 22  has one terminal connected to the other terminal of the MOS transistor M 21 , has the other terminal connected to the current source I ds2 , and has a gate terminal supplied with the sensing signal of the sensing line D 1 . The MOS transistor M 23  has one terminal connected to the ground voltage GND and has a gate terminal connected to the other terminal of the MOS transistor M 23 . The MOS transistor M 24  has one terminal connected to the other terminal of the MOS transistor M 23 , has the other terminal connected to the current source I ds2 , and has a gate terminal supplied with the sensing signal of the sensing line D 2 . The MOS transistor M 25  has one terminal connected to the ground voltage GND and has a gate terminal connected to the other terminal of the MOS transistor M 25 . The MOS transistor M 26  has one terminal connected to the other terminal of the MOS transistor M 25 , has the other terminal connected to the current source I ds2 , and has a gate terminal supplied with the lowest voltage VL. 
         [0139]    The MOS transistor M 27  has one terminal connected to the ground voltage GND and has a gate terminal connected to the gate terminal of the MOS transistor M 25 . The MOS transistor M 28  has one terminal and a gate terminal connected to the other terminal of the MOS transistor M 27  and has the other terminal supplied with the operating voltage VDD. The MOS transistor M 29  has one terminal connected to the ground voltage GND and has the gate terminal connected to the gate terminal of the MOS transistor M 23 . The MOS transistor M 30  has one terminal connected to the other terminal of the MOS transistor M 29 , has the other terminal supplied with the operating voltage VDD, and has a gate terminal connected to the gate terminal of the MOS transistor M 28 . The MOS transistor M 31  has one terminal connected to the ground voltage GND and has a gate terminal connected to the gate terminal of the MOS transistor M 21 . The MOS transistor M 32  has one terminal connected to the other terminal of the MOS transistor M 31 , has the other terminal supplied with the operating voltage VDD, and has a gate terminal connected to the gate terminal of the MOS transistor M 28 . 
         [0140]    The middle comparison voltage O 3  is output through a node at which the MOS transistor M 31  and the MOS transistor M 32  are connected. The middle comparison voltage O 4  is output through a node at which the MOS transistor M 29  and the MOS transistor M 30  are connected. 
         [0141]    In the comparison circuit  502  illustrated in  FIG. 17 , the MOS transistor M 22 , the MOS transistor M 24 , the MOS transistor M 26 , the MOS transistor M 28 , the MOS transistor M 30 , and the MOS transistor M 32  are P type MOS transistors, and all the remaining transistors are N type MOS transistors. 
         [0142]      FIG. 18  illustrates the relationship between comparison voltages determined based on two sensing signals, the highest voltage, and the lowest voltage. 
         [0143]    Referring to  FIG. 18 , if at least one of the sensing signals of the two sensing lines D 1 , D 2  is higher than the highest voltage VH or lower than the lowest voltage VL, one of the comparison voltage OH and the comparison voltage OL has a level (logical high level) of the operating voltage VDD. This case corresponds to a case where a noise is included. 
         [0144]    The operation of the embodiment of  FIG. 13  is described when a noise is included as described above. 
         [0145]    In response to the output of the comparator  231  of the noise detection unit  230 , the NOR gate  232  provides output of a low level to the clock generator  233 . The clock generator  233  outputs the first clock signal CLK and second clock signal CLK_B corresponding to input of a low level. The delay unit  234  delays the first clock signal CLK and provides the delayed clock signal to the SR flip-flop  236 . The D flip-flop  235  outputs a reset signal, synchronized with the third clock signal CLK 1 , using the second clock signal as the reset signal. The SR flip-flop  236  receives the output of the delay unit  234  as the set signal, receives the output of the D flip-flop  235  as the reset signal, and outputs a pulse. The D flip-flop  237  receives the pulse of the SR flip-flop  236  and outputs the first noise detection signal S_B and the second noise detection signal S_BB in synchronization with the fourth clock signal CLK 2 . That is, the noise detection unit  230  outputs the first noise detection signal S_B and second noise detection signal S_BB corresponding to sensing signals including a noise. 
         [0146]    When the noise detection unit  230  outputs the first noise detection signal S_B and second noise detection signal S_BB corresponding to the sensing signals including a noise as described above, the switch S 19  of the delay unit  240  is turned off, and the switch S 20  is turned on. That is, the transfer of the signal of the delay unit  240  to the integration unit  250  is blocked. In this case, the voltage Vref provided through the switch  20  functions as a bias voltage for charging the delay capacitor C PD1  or the delay capacitor C PD2  with electric charges. 
         [0147]    In accordance with a point of time at which the sensing signal has been input, the first noise detection signal S_B and the second noise detection signal S_BB are provided to the delay unit  240  at a point of time at which they have been delayed by one cycle due to the delay of the delay unit  232  of the noise detection unit  230 . That is, the noise detection unit  230  provides the first noise detection signal S_B and the second noise detection signal S_BB for controlling the output of a differential sensing signal stored in the delay unit  240  in a previous cycle. 
         [0148]    Accordingly, the sensing signals including a noise are stored in the delay capacitor C PD1  or the delay capacitor C PD2  for the delay time of the noise detection unit  230 . Thereafter, although output is selected in response to the first lead signal  1  and the second lead signal  2 , the provision of the output to the integration unit  250  is blocked due to the turn-off of the switch S 19 . 
         [0149]    Accordingly, a noise is not incorporated into the integration value S_RO that is output because the integration unit  250  does not integrate the sensing signals including a noise. 
         [0150]    Meanwhile, referring to  FIG. 18 , if the sensing signals of the two sensing lines D 1 , D 2  are lower than the highest voltage VH and are also higher than the lowest voltage VL, the comparison voltage OH and the comparison voltage OL have a level (logic low level) of the ground voltage GND. This case corresponds to a case where a noise is not included. 
         [0151]    The operation of the embodiment of  FIG. 13  is described when a noise is not included as described above. 
         [0152]    In response to the output of the comparator  231  of the noise detection unit  230 , the NOR gate  232  provides output of a high level to the clock generator  233 . The clock generator  233  outputs the first clock signal CLK and second clock signal CLK_B corresponding to input of a high level. The delay unit  234  delays the first clock signal CLK and provides the delayed clock signal to the SR flip-flop  236 . The D flip-flop  235  outputs a reset signal, synchronized with the third clock signal CLK 1 , using the second clock signal as the reset signal. The SR flip-flop  236  receives the output of the delay unit  234  as the set signal, receives the output of the D flip-flop  235  as the reset signal, and outputs a pulse. The D flip-flop  237  receives the pulse of the SR flip-flop  236  and outputs the first noise detection signal S_B and the second noise detection signal S_BB in synchronization with the fourth clock signal CLK 2 . That is, the noise detection unit  230  outputs the first noise detection signal S_B and second noise detection signal S_BB corresponding to sensing signals not including a noise. 
         [0153]    The first noise detection signal S_B and the second noise detection signal S_BB when a noise is included and when a noise is not included may have opposite phases. Furthermore, the first noise detection signal S_B and the second noise detection signal S_BB may be output at a point of time at which they have been delayed by one cycle due the delay of the delay unit  232  in accordance with a point of time at which the sensing signal has been input. 
         [0154]    The switch S 19  is turned on and the switch S 20  is turned off in response to the first noise detection signal S_B and the second noise detection signal S_BB output by the noise detection unit  230 . Accordingly, electric charges stored in the delay capacitor C PD1  and delay capacitor C PD2  of the delay unit  240  are sequentially transferred to the integration unit  250 . 
         [0155]    More specifically, when the first lead signal  1  shifts to an enable state, a current path including the turned-on switch S 14 , the delay capacitor C PD2 , the turned-on switch S 15 , and the amplifier  241  is formed, and electric charges according to the differential amplification signal DS_O are charged in the delay capacitor C PD2 . At the same time, a current path via the turned-on switch S 13 , the delay capacitor C PD1 , the turned-on switch S 17 , and the turned-on switch S 19  is formed, and the electric charges charged in the delay capacitor C PD1  are provided to the integration unit  250 . 
         [0156]    Thereafter, when the second lead signal  2  shifts to an enable state, a current path including the turned-on switch S 11 , the delay capacitor C PD1 , the turned-on switch S 12 , and the amplifier  241  is formed, and electric charges according to the differential amplification signal DS_O are charged in the delay capacitor C PD1 . At the same time, a current path including the turned-on switch S 16 , the delay capacitor C PD2 , the turned-on switch S 18 , and the turned-on switch S 19  is formed, and the electric charges charged in the delay capacitor C PD2  are provided to the integration unit  250 . 
         [0157]    The first noise detection signal S_B and the second noise detection signal S_BB are provided to the delay unit  240  at a point of time at which they have been delayed by one cycle due to the delay of the delay unit  232  of the noise detection unit  230  in accordance with the point of time at which the sensing signal has been input. 
         [0158]    Accordingly, a sensing signal in which a noise has not been detected is stored in the delay capacitor C PD1  or the delay capacitor C PD2  for the delay time of the noise detection unit  230 . Thereafter, outputs are selected in response to the first lead signal  1  and the second lead signal  1  and sequentially provided to the integration unit  250  via the turned-off switch S 19 . 
         [0159]    Accordingly, the integration unit  250  integrates the sensing signals in which a noise has not been detected and outputs the integrated signal to the integration value S_RO. 
         [0160]      FIG. 19  illustrates the output characteristics of charger noises according to the results of computer simulations in accordance with the embodiments of  FIGS. 11 to 13 . 
         [0161]    A graph at the upper part of  FIG. 19  illustrates a change over the time of the sensing signal of one of the two sensing lines D 1 , D 2 , and a graph at the lower part of  FIG. 19  illustrates a changed over the time of the output voltage of the integration unit  250 . From  FIG. 19 , it may be seen that if a charger noise is applied to the sensing line, the tendency of an increase (indicated by a thick solid line) in accordance with an embodiment of the present invention has relatively better linearity than a conventional increase tendency (indicated by a thin solid line). 
         [0162]    Accordingly, the embodiments of the present invention described with reference to  FIGS. 11 to 19  can have a noise filtering effect because a great noise, such as a charger noise, is blocked from being transferred to the integration unit  250 . 
         [0163]    In the embodiments of  FIGS. 11 to 19 , the sensing signal has been illustrated as being delayed by one cycle in order to help understanding of the present invention, but the delay cycle may be differently set depending on a manufacturer. 
         [0164]    Meanwhile, in the embodiments of  FIGS. 20 to 22  in accordance with the present invention, in order to detect a change of a sensing signal output by a sensing line of the touch screen panel  10  and recognize a touch, noises can be removed by performing periodic integration on a differential sensing signal corresponding to the sensing signal and performing the integration using a differential sensing signal stored in a cycle before a noise is detected when the noise is detected in the sensing signal. 
         [0165]      FIG. 20  is a flowchart illustrating another embodiment of the noise removal method for a touch screen in accordance with the present invention, and  FIG. 21  is a block diagram illustrating yet another embodiment of the control circuit for a touch screen in accordance with the present invention. The control circuit for a touch screen of  FIG. 21  may be performed as in  FIG. 22 . 
         [0166]    Referring to  FIG. 20 , a noise removal method  5200  for a touch screen includes a differential sensing signal generation step S 220 , a differential distribution voltage storage step S 230 , a noise detection step S 240 , and signal processing steps S 250 , S 260 . 
         [0167]    In the differential sensing signal generation step S 220 , a differential sensing signal corresponding to a difference between the sensing signals of two adjacent sensing lines of the touch screen panel  10  is generated in a predetermined cycle. In the differential distribution voltage storage step S 230 , the differential sensing signal i is stored as a first differential distribution voltage i and a second differential distribution voltage i for each cycle. In the noise detection step S 240 , whether a noise is detected in the sensing signals of the two sensing lines for each cycle is determined. If a noise is determined to be not detected in the sensing signals, the signal processing step S 250  is performed. If a noise is detected in the sensing signals, the signal processing step S 260  is performed. If a noise is not detected in the sensing signals, a differential sensing signal stored in response to a sensing signal determined to include a noise at step S 250  is output as the first differential distribution voltage i and integrated. If a noise is detected in the sensing signals, a second differential distribution voltage i−1 stored in a cycle before a differential sensing signal stored in response to a sensing signal determined to include a noise at step S 260  is integrated. 
         [0168]    In this case, the second differential distribution voltage may have the same voltage level as that of the first differential distribution voltage or may have a voltage level averaged at a specific ratio of an average voltage level of a first differential distribution voltage prior to two cycles and a first differential distribution voltage in a previous cycle right before. 
         [0169]    In the initial value setting step S 210  of  FIG. 20 , a value assigned to a variable i is reset to 1, a differential sensing voltage 0 stored prior to a current cycle (i=1) is reset to 0 (zero), and each of a first differential distribution voltage 0 and a second differential distribution voltage 0 is reset to 0. In the variable increase step S 170 , the variable is increased by 1 after a series of the processes S 220 ˜S 260  are performed. 
         [0170]    The noise removal method of  FIG. 20  may be performed by a control circuit  400  for a touch screen illustrated in  FIGS. 21 and 22 . First, referring to  FIG. 21 , the control circuit  400  includes a differential sensing unit  420 , a noise detection unit  430 , a delay unit  440 , a storage unit  450 , and an integration unit  460 . 
         [0171]    The control circuit  400  of  FIG. 21  may illustratively include a switching block  410 . The switching block  410  may be configured to select and output electric charges stored in two adjacent sensing lines D 1 , D 2  of the sensing lines of the touch screen panel  10  like the switching block  210  of  FIG. 12 . 
         [0172]    The differential sensing unit  420  generates a differential sensing signal DS_O, that is, a difference between the sensing signals of the two sensing lines selected by the switching block  410 . 
         [0173]    The noise detection unit  430  generates a first noise detection signal S_B enabled when a noise is detected in at least one of the two sensing lines D 1 , D 2  and a second noise detection signal S_BB that has the same amount as the first noise detection signal S_B and has a phase opposite that of the first noise detection signal S_B. In this case, the noise detection unit  430  may output the first noise detection signal S_B and the second noise detection signal S_BB delayed by one cycle in response to a sensing signal received in order to detect a noise. That is, the first noise detection signal S_B and the second noise detection signal S_BB are signals indicative of whether a noise has been detected in a sensing signal prior to one cycle compared to the sensing signal currently input to the noise detection unit  430 . A detailed configuration of the noise detection unit  430  is the same as the noise detection unit  230  of  FIG. 13 , and thus a redundant description thereof is omitted. 
         [0174]    The delay unit  440  delays the differential sensing signal DS_O for each cycle, stores the delayed differential sensing signal as a first differential distribution voltage Del_O, transfers the first differential distribution voltage Del_O, stored in a cycle prior to the cycle of the differential sensing signal DS_O that is currently stored, to the integration unit  460  in response to the first noise detection signal S_B and the second noise detection signal S_BB, and generates an internal output voltage VO_I of a constant voltage level corresponding to the differential sensing signal DS_O that is currently input. The configuration of the delay unit  440  also corresponds to that of the delay unit  240  of  FIG. 13 . 
         [0175]    The storage unit  450  stores the internal output voltage VO_I, output by the delay unit  440  for each cycle, as a second differential distribution voltage Mem_O and transfers the second differential distribution voltage Mem_O that is one cycle earlier than the first differential distribution voltage Del_O to be output by the delay unit  440  to the integration unit  260  in response to the first noise detection signal S_B and the second noise detection signal S_BB. The integration unit  460  integrates the first differential distribution voltages Del_O transferred by the delay unit  440  or the second differential distribution voltages Mem_O transferred by the storage unit  450 . 
         [0176]    The control circuit  400  of  FIG. 21  may be configured as in  FIG. 22 . In  FIG. 22 , the switching block  410 , the differential sensing unit  420 , the noise detection unit  430 , the delay unit  440 , and the integration unit  460  have been illustrated as having the same configurations as the switching block  210 , differential sensing unit  220 , noise detection unit  230 , delay unit  240 , and integration unit  250  of  FIG. 13 . Accordingly, a description of them is omitted. 
         [0177]    Meanwhile, the storage unit  450  includes AND gates  451 ˜ 453 , charging capacitors C C1 ˜C C3 , and switches S 31 ˜S 36 . 
         [0178]    The AND gate  451  generates a signal C 3 _E by performing logical AND on the first noise detection signal S_B and a third switch control signal C 3 . The AND gate  452  generates a signal C 1 _E by performing logical AND on the first noise detection signal S_B and a first switch control signal C 1 . The AND gate  453  generates a signal C 2 _E by performing logical AND on the first noise detection signal S_B and a second switch control signal C 2 . A reference voltage Vref is applied to one terminal of each of the charging capacitors C C1 ˜C C3 . 
         [0179]    The switch S 31  is switched in response to the first switch control signal C 1 , and switches the application of the internal output voltage VO_I, that is, the output voltage of the amplifier  441 , to the other terminal of a charging capacitor C C1 . The switch S 32  is switched in response to the signal C 3 _E of the AND gate  451 , and switches the provision of a voltage at the other terminal of the charging capacitor C C1  as the second differential distribution voltage Mem_O. The switch S 33  is switched in response to the second switch control signal C 2 , and switches the application of the internal output voltage VO_I, that is, the output voltage of the amplifier  441 , to the other terminal of a charging capacitor C C2 . The switch S 34  is switched in response to the signal C 1 _E of the AND gate  452 , and switches the provision of a voltage at the other terminal of the charging capacitor C C2  as the second differential distribution voltage Mem_O. The switch S 35  is switched in response to the third switch control signal C 3 , and switches the application of the internal output voltage VO_I, that is, the output voltage of the amplifier  441 , to the other terminal of a charging capacitor C C3 . The switch S 36  is switched in response to the signal C 2 _E of the AND gate  453 , and switches the provision of a voltage at the other terminal of the charging capacitor C C3  as the second differential distribution voltage Mem_O. Furthermore, the terminals of the switches S 32 , S 34 , and S 36  that provide the second differential distribution voltage Mem_O are connected in common and connected to the negative input terminal − of the amplifier  461  of the integration unit  460 . 
         [0180]      FIG. 23  illustrating the waveforms of signals used in the control circuit of  FIG. 22 . 
         [0181]    Referring to  FIG. 23 , each of the first switch control signal C 1 , the second switch control signal C 2 , and the third switch control signal C 3  has a cycle that is 1.5 times an integration cycle. Points of time at which the first switch control signal C 1 , the second switch control signal C 2 , and the third switch control signal C 3  are enabled may be synchronized with points of time at which the first lead signal  1  and the second lead signal  2  shift to a high level. 
         [0182]      FIGS. 24 to 26  illustrate the operations of the control circuit  400  according to the state of internal switches corresponding to a case where a noise is not detected in the sensing signals. 
         [0183]    If a noise is not detected in the sensing signals, the switch S 19  is turned on in response to the first noise detection signal S_B, and the storage unit  450  does not provide the second differential distribution voltage Mem_O to the integration unit  460 . In  FIGS. 25 to 27 , a path in which electric charges are stored is indicated by a solid line, and a path in which electric charges are transferred to the integration unit  460  is indicated by a dotted line. 
         [0184]      FIG. 24  illustrates a path in which electric charges are stored in accordance with the state in which the first lead signal  1  has been enabled and the second lead signal  2  has been disabled. 
         [0185]    Referring to  FIG. 24 , electric charges corresponding to the differential sensing signal DS_O output by the differential sensing unit  420  are transferred to a current path, including the switch S 14 , the delay capacitor C PD2 , the switch S 15 , and the output terminal VO_I of the integrator  441 . Electric charges having the same value are stored in the delay capacitor C PD2  of the delay unit  440  and the charging capacitor C C1  of the storage unit  450 . In this case, electric charges stored in the delay capacitor C PD1  in a previous cycle that is one cycle earlier than the cycle of the differential sensing signal DS_O that is input are output as the first differential distribution voltage DEL_O via the switch S 17  and the switch S 19 . The first differential distribution voltage Del_O is transferred to the integration unit  460  and then integrated. 
         [0186]    In this case, the first differential distribution voltage Del_O output to the integrator  460  corresponds to a differential sensing signal that is one cycle earlier than the differential sensing signal currently input to the delay unit  440 . The first noise detection signal S_B and the second noise detection signal S_BB that turn on the switch S 19  and turn off the switch S 20  also correspond to the detection of a noise in a sensing signal that is one cycle earlier than the differential sensing signal currently input to the delay unit  220 . That is, from a viewpoint of the first noise detection signal S_B and the second noise detection signal S_BB, the delay unit  440  outputs the first differential distribution voltage Del_O corresponding to the cycle of a sensing signal that has been determined to not include a noise. Furthermore, from a viewpoint of the differential sensing signal that is currently input, the delay unit  440  outputs the first differential distribution voltage Del_O corresponding to a differential sensing signal that has been input in a cycle that is one cycle earlier. 
         [0187]      FIG. 25  illustrates a path in which electric charges are stored in accordance with the state in which the second lead signal  2  has been enabled and the first lead signal  1  has been disabled. 
         [0188]    Referring to  FIG. 25 , electric charges corresponding to the differential sensing signal DS_O output by the differential sensing unit  420  are transferred to a current path, including the switch S 14 , the delay capacitor C PD1 , the switch S 12 , and the output terminal VO_I of the integrator  441 . Electric charges having the same value are stored in the delay capacitor C PD2  of the delay unit  440  and the charging capacitor C C1  of the storage unit  450 . In this case, electric charges stored in the delay capacitor C PD2  in a previous cycle that is one cycle earlier than the cycle of the differential sensing signal DS_O that is input are output as the first differential distribution voltage DEL_O via the switch S 18  and the switch S 19 . The first differential distribution voltage Del_O is transferred to the integration unit  460  and then integrated. The relationships between a differential sensing signal that is currently input, the first differential distribution voltage Del_O that is currently output, the first noise detection signal S_B, and the second noise detection signal S_BB are the same as those described with reference to  FIG. 24 . 
         [0189]      FIG. 26  illustrates a path in which electric charges are stored in accordance with the state in which the first lead signal  1  has been enabled and the second lead signal  2  has been disabled. The operation of  FIG. 26  is the same as that of  FIG. 24 , and thus a redundant description thereof is omitted. In this case, the operation of  FIG. 26  is different from that of  FIG. 24  in that electric charges corresponding to the differential sensing signal DS_O output by the differential sensing unit  420  are stored in the charging capacitor C C3  of the storage unit  450 . 
         [0190]    The storage unit  450  includes the three charging capacitors C C1 , C C2 , and C C3 . This is for the storage of a differential sensing signal currently input to the delay unit  440 , the storage of a differential sensing signal that is one cycle earlier than a differential sensing signal currently input to the delay unit  440 , that is, the storage of a differential sensing signal corresponding to the first differential distribution voltage Del_O currently output by the delay unit  440 , and the storage of a differential sensing signal corresponding to the second differential distribution voltage Del_O that will be output instead of the first differential distribution voltage Del_O to be currently output by the delay unit  440  in response to the detection of a noise in a sensing signal. The differential sensing signals stored in the respective charging capacitors C C1 , C C2 , and C C3  of the storage unit  450  correspond to three consecutive cycles having a time difference of one cycle. 
         [0191]    If a noise is not detected in the sensing signals, the first noise detection signal S_B applied to one input terminals of the three AND gates  451 ,  452 , and  453  of the storage unit  450  is not enabled. As a result, since the three AND gates  451 ,  452 , and  453  are disabled, the switches S 32 , S 34 , and S 36  maintain a turn-off state. Accordingly, the storage unit  450  does not the second differential distribution voltage Mem_O to the integration unit  460 . 
         [0192]    In contrast, when a noise is detected in the sensing signals and the first noise detection signal S_B is enabled, the output of the second differential distribution voltage Mem_O is determined by the three switch control signals C 1 , C 2 , and C 3  applied to the other input terminals of the three AND gates  451 ,  452 , and  453  of the storage unit  450 . If a noise is detected in the sensing signals, the switch S 19  maintains a turn-off state in response to the first noise detection signal S_B, and the delay unit  440  does not provide the first differential distribution voltage Del_O to the integration unit  460  due to the turn-off of the switch S 19 . Instead, the storage unit  450  provides the second differential distribution voltage Mem_O to the integration unit  460 . 
         [0193]      FIGS. 27 to 29  illustrate the operations of the storage unit  450  according to the state of internal switches when a noise is detected as described above. In  FIGS. 27 to 29 , a path in which electric charges are stored is indicated by a solid line, and a path in which electric charges are provided to the integration unit  460  is indicated by a dotted line. 
         [0194]      FIG. 27  illustrates the state in which the first switch control signal C 1  has been enabled and the second switch control signal C 2  and the third switch control signal C 3  have been disabled in  FIG. 22 . When the first switch control signal C 1  is enabled, the switch S 31  is turned on, and the signal C 1 _E of the AND gate  452  is enabled. In response thereto, the switch S 34  is turned on. Accordingly, electric charges transferred by the output terminal VO_I of the amplifier  441  of the delay unit  440  are stored (indicated by a solid line) in the charging capacitor C C1  through the turned-on switch S 31 . Electric charges stored in the charging capacitor C C2  are provided to the integration unit  460  via the turned-on switch S 34  as the second differential distribution voltage Mem_O as indicated by a dotted line. 
         [0195]      FIG. 27  corresponds to a case where a noise has been generated in a sensing signal stored in the delay capacitor C PD2  of  FIG. 24  in the form of electric charges and illustrates the state in which the switch S 19  is turned off due to the detection of the noise by the noise detection unit  430  and thus the output of electric charges stored in the delay capacitor C PD2  of  FIG. 24  as the first differential distribution voltage Del_O has been blocked. Instead of the electric charges stored in the delay capacitor C PD2  of  FIG. 24 , electric charges stored in the charging capacitor C C2  of  FIG. 27  are output as the second differential distribution voltage Mem_O. The electric charges stored in the charging capacitor C C2  have been stored in a cycle that is one cycle earlier than that of a sensing signal corresponding to the electric charges stored in the delay capacitor C PD1 . Furthermore, positive charges, such as those stored in the delay capacitor C PD2  of  FIG. 24 , are stored in the charging capacitor C C1  of  FIG. 27 . The electric charges stored in the delay capacitor C PD2  of  FIG. 24  and the electric charges stored in the charging capacitor C C1  of  FIG. 27  correspond to a sensing signal that is currently input. 
         [0196]      FIG. 28  illustrates the state in which the second switch control signal C 2  has been enabled and the first switch control signal C 1  and the third switch control signal C 3  have been disabled in  FIG. 22 . When the second switch control signal C 2  is enabled, the switch S 33  is turned on, and the signal C 2 _E of the AND gate  453  is enabled. In response thereto, the switch S 36  is turned on. Accordingly, electric charges transferred by the output terminal VO_I of the amplifier  441  of the delay unit  440  are stored (indicated by a solid line) in the charging capacitor C C2  through the turned-on switch S 33 . Electric charges stored in the charging capacitor C C3  are provided to the integration unit  460  via the turned-on switch S 36  as the second differential distribution voltage Mem_O as indicated by a dotted line. 
         [0197]      FIG. 28  corresponds to a case where a noise has been generated in a sensing signal stored in the delay capacitor C PD2  of  FIG. 25  in the form of electric charges and illustrates the state in which the switch S 19  is turned off due to the detection of the noise by the noise detection unit  430  and thus the output of electric charges stored in the delay capacitor C PD2  of  FIG. 25  as the first differential distribution voltage Del_O has been blocked. Instead of the electric charges stored in the delay capacitor C PD2  of  FIG. 25 , electric charges stored in the charging capacitor C C3  of  FIG. 28  are output as the second differential distribution voltage Mem_O. The electric charges stored in the charging capacitor C C3  have been stored in a cycle that is one cycle earlier than that of a sensing signal corresponding to the electric charges stored in the delay capacitor C PD2 . Furthermore, positive charges, such as those stored in the delay capacitor C PD1  of  FIG. 25 , are stored in the charging capacitor C C2  of  FIG. 28 . The electric charges stored in the delay capacitor C PD1  of  FIG. 25  and the electric charges stored in the charging capacitor C C2  of  FIG. 27  correspond to a sensing signal that is currently input. 
         [0198]      FIG. 29  corresponds to a case where a noise has been generated in a sensing signal stored in the delay capacitor C PD1  of  FIG. 26  in the form of electric charges and illustrates the state in which the switch S 19  is turned off due to the detection of the noise by the noise detection unit  430  and thus the output of electric charges stored in the delay capacitor C PD2  of  FIG. 25  as the first differential distribution voltage Del_O has been blocked. Instead of the electric charges stored in the delay capacitor C PD2  of  FIG. 26 , electric charges stored in the charging capacitor C C1  of  FIG. 29  are output as the second differential distribution voltage Mem_O. The electric charges stored in the charging capacitor C C1  have been stored in a cycle that is one cycle earlier than that of a sensing signal corresponding to the electric charges stored in the delay capacitor C PD1 . Furthermore, positive charges, such as those stored in the delay capacitor C PD2  of  FIG. 26 , are stored in the charging capacitor C C3  of  FIG. 29 . The electric charges stored in the delay capacitor C PD2  of  FIG. 26  and the electric charges stored in the charging capacitor C C3  of  FIG. 29  correspond to a sensing signal that is currently input. 
         [0199]    As illustrated in  FIGS. 27 to 29 , positive charges, such as those stored in the delay capacitor C PD1 , C PD2 , are shifted and stored in the charging capacitor C C1 , C C2 , C C3  of  FIG. 29 . Furthermore, the electric charges of the charging capacitor C C1 , C C2 , C C3  corresponding to a sensing signal that is one cycle earlier and that does not include a noise may be used in the second differential distribution voltage Mem_o instead of the delay capacitor C PD1 , C PD2  whose output has been blocked due to the occurrence of a noise. 
         [0200]    Accordingly, the integration unit  460  may receive the first differential distribution voltage Del_O or the second differential distribution voltage Mem_O depending on the state of a sensing signal and perform integration. As a result, touch recognition can be accurately implemented because an integration value from which noises have been filtered can be obtained. 
         [0201]    Meanwhile,  FIG. 30  illustrates another embodiment of the storage unit  450 . Referring to  FIG. 30 , the storage unit  450  includes two AND gates  456 ,  457 , an amplifier  455 , 4 charging capacitors C C4 ˜C C7 , and 7 switches S 41 ˜S 47 . 
         [0202]    The amplifier  455  has a positive input terminal + connected to the other terminal of the charging capacitor C C5  and has a negative input terminal − connected to the output terminal of the amplifier  455 . The AND gate  456  is configured to output a signal C 5 _E obtained by performing logical AND on the first noise detection signal S_B and a fifth switch control signal C 5 . The AND gate  457  is configured to output a signal C 4 _E obtained by performing logical AND on the first noise detection signal S_B and a fourth switch control signal C 4 . One terminal of each of the 4 charging capacitors C C4 ˜C C7  is configured to be supplied with the reference voltage Vref. 
         [0203]    The switch S 41  switches the charging of electric charges, provided by the output terminal VO_I of the amplifier  441  of the delay unit  440 , in a charging capacitor C C4  in response to the fourth switch control signal C 4 . The switch S 42  switches the output of the electric charges stored in the charging capacitor C C4  in response to the fifth switch control signal C 5 . The switch S 43  switches the transfer of the electric charges, output by the switch S 42 , to the charging capacitor C C5 , in response to the inverted first noise detection signal S_B. The switch S 44  switches the storage of the output of the amplifier  455  in the charging capacitor C C6  in response to the fourth switch control signal C 4 . The switch S 45  switches the output of electric charges, stored in the charging capacitor C C6 , as the second differential distribution voltage Mem_O in response to the signal C 5 _E of the AND gate  456 . The switch S 46  switches the storage of the output of the amplifier  455  in the charging capacitor C C7  in response to the fifth switch control signal C 5 . The switch S 47  switches the output of electric charges, stored in the charging capacitor C C7 , as the second differential distribution voltage Mem_O in response to the signal C 4 _E of the AND gate  457 . The switch S 43  may be configured to perform a switching operation in response to the inverted first noise detection signal S_B received through an inverter (not illustrated) or may be configured to perform an on/off operation opposite that of other switches. That is, if other switches are formed of NMOS transistors, the switch S 43  may be configured using a PMOS transistor. 
         [0204]      FIG. 31  illustrating the waveforms of signals used in the storage unit  450  of  FIG. 30 . Referring to  FIG. 31 , the fourth switch control signal C 4  and the fifth switch control signal C 5  are enabled in accordance with respective points of time at which the first lead signal  1  and the second lead signal  2  are enabled. If a noise is not detected, the disabled first noise detection signal S_B is provided to the AND gate  456  and the AND gate  457 , the AND gate  456  and the AND gate  457  are disabled, and the switch S 45  and the switch S 47  are turned off. Accordingly, electric charges stored in the charging capacitor C C6  and the charging capacitor C C7  are not output as the second differential distribution voltage Mem_O. 
         [0205]    If a noise is detected, the enabled first noise detection signal S_B is provided to the AND gate  456  and the AND gate  457 . In this case, a logic value of the signal C 5 _E output by the AND gate  456  is determined by the fifth switch control signal C 5 , and a logic value of the signal C 4 _E output by the AND gate  457  is determined by the fourth switch control signal C 4 . Electric charges stored in the charging capacitor C C6  and the charging capacitor C C7  are selectively provided to the integration unit  460  depending on the turn-on state of the switch S 45  and the switch S 47 . 
         [0206]      FIGS. 32 and 33  illustrate the operation of the storage unit  450  corresponding to the state in which a noise has not been detected. 
         [0207]      FIG. 32  corresponds to a case where the fourth switch control signal C 4  has been enabled and the first noise detection signal S_B and the fifth switch control signal C 5  have been disabled. Accordingly, the switch S 41 , the switch S 43 , and the switch S 44  are turned on, and all the remaining switches are turned off. Electric charges stored in the charging capacitor C C6  and the charging capacitor C C7  are not output to the integration unit  460 . Electric charges provided by the output terminal VO_I of the amplifier  441  are stored in the charging capacitor C C4  via the switch S 41 . Electric charges stored in the charging capacitor C C5  are buffered in the amplifier  455  and then transferred to the charging capacitor C C6  through the switch S 44 . The charging capacitor C C4  maintains at least a specific amount of charging by the reference voltage Vref. 
         [0208]      FIG. 33  corresponds to a case where the fifth switch control signal C 5  has been enabled and the first noise detection signal S_B and the fourth switch control signal C 4  have been disabled. Accordingly, the switch S 42 , the switch S 43 , and the switch S 46  are turned on, and all the remaining switches are turned off. Electric charges stored in the charging capacitor C C6  and the charging capacitor C C7  are not output to the integration unit  460 . Furthermore, electric charges stored in the charging capacitor C C4  are transferred to the charging capacitor C C5  via the switch S 42  and the switch S 43 . A charge distribution is performed depending on capacitance of the charging capacitor C C4  and the charging capacitor C C5 . The same positive charges as electric charges distributed and stored in the charging capacitor C C5  are buffered in the amplifier  455  and then transferred to the charging capacitor C C7  through the switch S 46 . 
         [0209]    If the charging capacitor C C5  has higher capacitance than the charging capacitor C C4 , the amount of electric charges that have been previously distributed and stored in the charging capacitor C C5  may have a greater influence on a charge distribution than the amount of electric charges currently applied from the charging capacitor C C4  to the charging capacitor C C5 . Accordingly, the charging capacitor C C5  may perform a charge distribution on received electric charges. A ratio of capacitance of the charging capacitor C C4  and capacitance of the charging capacitor C C5  may be determined depending on a method of using the storage unit  450  in accordance with the present invention. 
         [0210]    As in  FIGS. 32 and 33 , the storage unit  450  illustrated in  FIG. 30  stores electric charges, provided by the output terminal VO_I of the amplifier  441 , in the charging capacitor C C4  only in a cycle in which the fourth switch control signal C 4  is enabled and does not charge electric charges provided by the output terminal VO_I of the amplifier  441  in a cycle in which the fifth switch control signal C 5  is enabled. 
         [0211]    As in  FIGS. 32 and 33 , in the embodiment of the storage unit  450  of  FIG. 30 , electric charges provided in any one of an odd cycle and an even cycle are stored, and the second differential distribution voltage Mem_O may be provided using the stored charges in accordance with the detection of a noise as in  FIGS. 34 and 35 . 
         [0212]      FIGS. 34 and 35  illustrate the operations of the storage unit  450  when a noise is detected. 
         [0213]      FIG. 34  corresponds to a case where the fourth switch control signal C 4  and the first noise detection signal S_B have been enabled and the fifth switch control signal C 5  has been disabled. Accordingly, the switch S 41 , the switch S 43 , the switch S 44 , and the switch S 47  are turned on, and all the remaining switches are turned off. Accordingly, the transfer of electric charges, stored in the charging capacitor C C4 , to the charging capacitor C C5  is blocked. That is, the transfer of electric charges, provided by the output terminal VO_I of the amplifier  441  of the delay unit  440  in accordance with sensing signals including a noise, to the charging capacitor C C5  is blocked. Electric charges charged in the charging capacitor C C5  are set to the state before the noise is detected. The fixed positive charges charged in the charging capacitor C C5  are buffered in the amplifier  455  and then charged in the charging capacitor C C6 . In this case, electric charges charged in the charging capacitor C C7  are provided as the second differential distribution voltage Mem_O through the turned-on switch S 47 . 
         [0214]      FIG. 35  corresponds to a case where the fifth switch control signal C 5  and the first noise detection signal S_B have been enabled and the fourth switch control signal C 4  has been disabled. Accordingly, the switch S 42 , the switch S 45 , and the switch S 46  are turned on, and all the remaining switches are turned off. Even in this case, the transfer of electric charges, stored in the charging capacitor C C4 , to the charging capacitor C C5  is blocked. That is, the transfer of electric charges, provided by the output terminal VO_I of the amplifier  441  of the delay unit  440  in accordance with sensing signals including a noise, to the charging capacitor C C5  is blocked. Electric charges charged in the charging capacitor C C5  maintains the state before the noise is detected. The fixed positive charges charged in the charging capacitor C C5  are buffered in the amplifier  455  and then charged in the charging capacitor C C7 . In this case, electric charges charged in the charging capacitor C C6  are provided as the second differential distribution voltage Mem_O through the turned-on switch S 45 . 
         [0215]    Thereafter, the storage unit  450  of  FIG. 30  switches to the state of  FIGS. 32 and 33  when a noise is not detected in the sensing signals. 
         [0216]    The storage unit  450  of  FIG. 30  in accordance with the present invention charges electric charges provided by the output terminal VO_I of the amplifier  441  of the delay unit  440  in the same cycle as an integration cycle, shares the charged electric charges, and stores them in the different charging capacitors C C7 , C C7  in the same cycle as the cycle in which sensing signals are detected. Thereafter, when a noise is detected in sensing signals, a charge distribution using electric charges including a noise is blocked, and the second differential distribution voltage Mem_o is provided using electric charges set in the charging capacitor C C5  before the noise is detected. 
         [0217]      FIG. 36  illustrates the concept of integration according to the use of the storage unit  450  of  FIG. 22 . Referring to  FIG. 36 , when a noise is detected, the storage unit  450  transfers electric charges that do not include a noise and that have been stored in a previous cycle to the integration unit  460 . 
         [0218]      FIG. 37  illustrates the concept of integration according to the use of the storage unit  450  of  FIG. 30 . Referring to  FIG. 37 , when a noise is detected, the storage unit  450  does not perform a charge distribution between the charging capacitor C C4  and the charging capacitor C C4 . Accordingly, the storage unit  450  transfers electric charges, set before the noise is detected, to the integration unit  460 . The storage unit of  FIG. 30  may perform integration using electric charges set before a noise is defected although noises are continuously generated. Accordingly, an embodiment of the present invention can avoid a noise and perform integration on sensing signals using the storage unit  450  of  FIG. 30 . 
         [0219]    Although the technical spirit of the present invention has been described in connection with the accompanying drawings, it illustrates preferred embodiments of the present invention and does not limit the present invention. Furthermore, it is evident that those skilled in the art to which the present invention pertains may modify and imitate the present invention in various ways without departing from the category of the technical spirit of the present invention.