Abstract:
A control circuit for a static VAR generator measures load power during consecutive half cycles of the source voltage. This information, together with load voltage and load current information is used to determine the firing angles of the VAR generator thyristors for providing compensating current for keeping the source current in phase with the source voltage and for balancing the source currents in a three-phase electrical system. The total computation time for determining the firing angles extends into the half cycle in which correction is to be applied beyond a fixed minimum firing angle.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to VAR generators and it relates in particular to high-speed circuits for ascertaining the firing angles in static VAR generators. 
     Static VAR generators compensate for the effects of highly-reactive loads such as arc furnaces on the terminal variables of AC supply systems. The static VAR generator or flicker compensator as it is sometimes called, includes a control circuit which measures the magnitudes of the arc furnace currents in consecutive half cycles of supply voltage. In some cases, arc furnace power may be measured rather than current. Regardless of which parameters are measured, the information is used to compute necessary compensation currents in terms of subsequently required firing angle signals for the thyristors of the static VAR generator. The VAR generator output current can only be adjusted once during each half cycle per phase. Consequently, the response time of the flicker compensator and thus its effectiveness for flicker reduction is largely dependent upon the speed with which the arc furnace current is measured and converted to a firing angle. U.S. Pat. No. 3,597,518, entitled &#34;Electric Arc Furnace Control&#34; by R. W. Roberts, issued Aug. 3, 1971 teaches a control system for an electric arc furnace which is designed to maintain constant arc peaks. The system is designed to respond quickly to large impedance errors, is insensitive to short-term impedance fluctuations, and at the same time is rarely highly sensitive to continuing small errors. U.S. Pat. No. 3,728,516, entitled &#34;Welding Power Source&#34; by A. D. Daspit, issued Apr. 17, 1973, teaches the concept of controlling SCR&#39;s in response to current and voltage applied to an electric welding device in which a capacitor is periodically semidischarged to a switching device. U.S. Pat. No. 3,936,727, issued Feb. 3, 1976 to F. W. Kelley, Jr. and G. R. E. Lezan teaches a compensation control device which determines the firing time of a static switch in accordance with a magnitude of the reactive load current and teaches a regulating means which additionally controls the firing time to maintain the line current and voltage at a selected line location substantially in phase coincidence. U.S. Pat. No. 3,999,117, issued Dec. 21, 1976 to Gyugyi et al. teaches a static VAR generator and compensator where time delayed firing angles are calculated from integrating furnace load currents over prescribed intervals during real time to thus maintain balanced load current at specified phase angles which are usually zero in a three-phase electrical system. The latter utilizes phase-to-phase voltage as a reference. In the latter system, the peak value of the phase-to-phase voltage delineates between operational cycles. Because of this, in the previous patents, it was taught to make the calculations for a control cycle prior to that cycle. The calculations were made over a period of approximately 180° and were ready for utilization in the control circuit at the beginning of the cycle as measured by the reference voltage being at its maximum value. In a later U.S. Pat. No. 4,000,455, issued Dec. 28, 1976 by Gyugyi et al, it was taught that the total computation time for determining the firing angle in each succeeding half cycle would take no longer than the length of time of the last complete half cycle immediately prior to the firing of the thyristor. In U.S. Pat. No. 4,068,159, by Gyugyi et al., it was determined that the computation time for determining the firing angle could actually extend into the half cycle in which the correction was to be applied. This could be done because of the knowledge that the amount of current necessary for compensation is such that the firing angle could not occur before a minimum firing angle of a predetermined amount which may for example be 10°. Consequently, the inventors in the previous case allowed the calculation of the actual firing angle to continue into the half cycle in which compensation was actually required by an amount equal to the previously-described minimum angular amount. It would be advantageous if apparatus and method could be discovered which extended the computation time for determining the firing angle even further into the half cycle than the previously-determined fixed minimum firing angle and thus utilized the extended firing angle time to continue to calculate information about the firing angle. As paradoxical as the latter statement seems to be, apparatus has been invented which performs that function. 
     SUMMARY OF THE INVENTION 
     In accordance with the invention, apparatus and method are taught in which the computation interval, that is the time during which the required compensation is calculated, is not fixed but follows the actual thyristor firing angle. In other words, the computation of the required compensation does not stop at the earliest possible firing point but it continues up to the actual point of firing. In this way, the required compensation is always determined from the most recent condition of the load. This results in improved frequency response for the VAR generator and consequently more effective reduction of voltage flicker caused by a rapidly varying load such as is found in an electric arc furnace. In essence, the actual firing angle is calculated at the time of the minimum firing angle. If the actual firing angle exceeds the minimum firing angle by a predetermined incremental amount, the calculation for the actual firing angle is extended by the incremental time and the actual firing angle is calculated once again at that time. This continues until the actual firing angle is determined to occur before the end of a subsequent fixed interval during which the actual firing of the thyristors is allowed to take place. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the invention, reference may be had to the preferred embodiments thereof exemplified by the accompanying drawings in which: 
     FIG. 1 shows a prior art static VAR generator power circuit; 
     FIG. 2 shows a plot of VAR generator voltage and time-controlled inductor current versus ωt for the apparatus of FIG. 1; 
     FIG. 3 shows a plot of appropriate phase voltages and currents with superimposed delineated calculation intervals and the appropriate firing angle and inductor current for the compensator; 
     FIG. 4 (otherwise identified as FIGS. 4A and 4B) shows a compensator control circuit for an inductive load for a three-phase AC control system. A compensating control system for one phase is shown in great detail while the compensating control system for the other two phases are shown in block diagram form. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings and prior art FIG. 1 in particular, there is shown a basic VAR generator for a single phase AC electrical system. In general, the VAR generator consists of a fixed capacitor C and a thyristor controlled inductor L. At zero leading VAR demand, the thyristor switch TH is closed and the inductive effect of the inductor L cancels the capacitive effect of the capacitor C so that the net current I n  provided for the AC system is zero. That is, the algebraic sum of the capacitor current I c  and the inductor current I.sub.α is equal to zero. The voltage across the parallel combination which includes the capacitive element C, the inductive element L, and the thyristor switch TH is equal to V1. At some non-zero leading VAR demand, the closing of the switch TH is appropriately delayed in each half cycle of the alternating current by a variable angle which shall be called the firing angle α which is measured with respect to the peak of the supply voltage V1 in order to reduce the current I.sub.α flowing in the inductor L. 
     Referring now to FIG. 2, there is shown a plot of voltage V1 and current I.sub.α versus ωt. The curves of FIG. 2 are arbitrarily divided into three zones designated A1, B1, and C1, each of which begins with the maximum positive or negative value of V1 in each half cycle as the case may be. It will be noted that in region A1, the inductor current I.sub.α lags the inductor voltage V1 by 90° and the firing angle α is zero. However, with an increasing firing angle α in the region between zero and 90°, the inductive current I.sub.α decreases and consequently, the leading VAR provided for the AC system increases. At the maximum leading VAR demand, the switch TH of FIG. 1 is fully opened. This occurs at α=90°. When this happens, the current I.sub.α in the inductor L in FIG. 1 is zero and therefore, the maximum rated capacitive current I c  is provided for compensation. FIG. 2 shows in region B1 that for a delay or firing angle α 1 , the inductive current I.sub.α.sbsb.1 flows for a shorter period of time than the current I.sub.α shown in region A1. Likewise, in region C1 where the firing angle or delay is α 2  (where α 2  is greater than α 1  in this case), the inductor current I.sub.α.sbsb.2 flows for an even shorter period of time than those inductive currents I.sub.α and I.sub.α.sbsb.1 shown in regions A1 and B1, respectively. 
     Referring now to FIG. 4, the static VAR generator 10 (or compensator) under consideration is shown schematically. The currents in the three Δ connected inductors L C  of the compensator 10 are controlled by adjusting corresponding firing angles α 12 , α 23 , and α 31  in every half cycle so that the combined currents of the arc furnace and the compensator are balanced and have a fixed (usually zero) reactive component. The maximum range of control of the angles α 12 , α 23 , and α 31  is typically 90°, with α 12  =0°, α 23  =0°, and α 31  =0°, coinciding with the points where the relative line-to-line voltages v 12 , v 23 , and v 31 , respectively, reach their peaks. The operating range of control may be reduced by introducing a fixed delay angle α c  and reducing the inductance of the thyristor-controlled reactor L c  so that at α c , the maximum required inductor current is obtained. As the firing angle is retarded from the fixed delay angle α c , the current in the inductor L c  decreases reaching zero when α c  plus α=90° . 
     The principles of control in the prior art compensator are essentially the same regardless of the value of α c . The three delay angles α 12 , α 23 , and α 31 , are electronically computed in two steps: first, the required currents in the thyristor controlled reactors are calculated from the currents (or power) drawn by the individual phases of the load during the half (or full) cycle interval just prior to α c  (note again, α c  is close to, and may actually be, zero), and second, the delay angles are computed using a mathematical relationship between the delay angle and the fundamental component of current in the thyristor controlled reactor. It is important to note that in the prior art control schemes the computation is usually completed at the earliest possible firing point of α=0°, or in an improved control scheme of α=α c . The firing angle required for the proper compensation is, of course, generally different from α=0° (or α=α c ). Thus, the firing angle represents an inactive interval which separates the measuring interval (information ready) from the conduction interval of the thyristor switch (information used). Load changes taking place during the inactive interval are not included in the computation of the required compensation, which fact is detrimental in achieving the shortest possible response time for the compensator. 
     The computation of the required compensation is based on well known expressions which establish steady state relationships between the load currents and the compensator currents or the per phase load powers and the per phase compensating VARs. The current and power equations have similar meanings and they can be converted readily into each other. The presently proposed control method can be implemented simpler and more conveniently by using basic power relationships than, for example, current relationships, and therefore the description will be restricted to the former case. 
     Assuming steady state sinusoidal voltages and currents, the reactive power in each phase (line-to-line) of the compensator, for balanced real line power, can be expressed in terms of two per phase load power quantities by the following expressions: ##EQU1## where v 12 , v 23 , v 31  are the three line-to-line voltages, i 1 , i 2 , i 3  are the three load currents, t o  is an arbitrary time instant where the integration begins, T is the period time of the ac power supply, and k is any integer (k=1,2,3, . . . ). 
     The reactive powers, Q 12 , Q 23  and Q 31 , required for load compensation may also be given in terms of three per-phase load power quantities as follows: ##EQU2## These equations express the well known relationships: ##EQU3## where Q 1 , Q 2  and Q 3  are the reactive load powers in phases 1, 2 and 3, respectively. 
     The set of Equations (1) and (2) are equivalent, expressing the same quantities in different ways. 
     Neither set of equations describing steady-state conditions is strictly valid under varying load conditions. However, they can still be used by making the integration over a short interval, e.g., over a half period T/2 (k=1). This means that the per phase load powers defined by Equations (1) or (2) are computed from the available supply voltages and currents in each half cycle as if they were steady-state quantities, and from these the reactive power and subsequently the corresponding firing angles required in each phase for compensation are determined. Although the integrations could be carried out over arbitrary half cycle intervals, in prior art approaches the integration intervals are rigidly tied to the ac supply voltages so that the computations are completed just prior to the possible earliest firing points (usually defined by the peaks of the corresponding supply voltages). Theoretically, there is no need for this rigid synchronization. In fact, as explained earlier, there is a considerable advantage in tying the integration interval to the actual firing point (instead of the earliest possible one). 
     The control principle using computation intervals that follow the corresponding firing angles is explained in conjunction with Equations (1) with the understanding that the same principle could be applied to other types of power equations, e.g., such as given in (2). 
     Using ωt (angle measured at ω angular frequency) as a variable, Equations (1) can be re-written for k=1 (integration over half cycle) in the following form: ##EQU4## where a c .sbsb.12, α c .sbsb.23, α c .sbsb.31 are the earliest firing points for the thyristor switches controlling the reactive compensation in phase 12, phase 23 and phase 31, respectively. 
     In order to extend the integration to the actual firing points determined by delay angles α 12 , α 23 , and α 31 , without changing the half period (π) integration interval, Equations (4) are modified in the following way. ##EQU5## 
     Referring now to FIG. 3, the quantities defining the integration intervals for the computation of Q 12  are illustrated. Comparison of Equations (5) with Equations (4) shows that, for example, the integration interval defined by angles α c .sbsb.12 -π and α c .sbsb.12 [Equations (4)] is replaced by that defined by angles a 12  -π and α 12 . The new integration interval just precedes the firing point defined by α 12 . The &#34;shift&#34; of the integration interval is achieved by continuing the integration over the interval, for example, (α c .sbsb.12, α 12 ) [that is, adding integrals (B) to the originally obtained (A)] and, at the same time, negating the integration in the interval (α c .sbsb.12 -π, α 12  -π) [that is, subtracting integrals (C) from (A)]. The interval defined by, for example, angles α c .sbsb.12 and α 12  extending from the earliest possible to the actual firing point, contains the most recent load information, and conversely, the interval defined by α c .sbsb.12 -π and α 12  -π contains the oldest information. Thus, this manipulation makes it possible to replace the oldest with the most recent information about the load. Since the evaluation of the reactive powers (Q 12 , Q 23  and Q 31 ) required for compensation determines the firing angles, it is not possible to decide in advance where the integration should start. The fundamental idea in the technique proposed, as shown by Equations (5), is to start the integration half a period prior to the earliest firing point. If the thyristor switch need not be fired at the earliest firing point (because the compensation requires smaller than the maximum current in the thyristor controlled inductor), the integration is continued until the actual firing point is found. Of course, the continued integration would change the length of the integration interval specified [Equations (1)], resulting in erroneous compensation. To keep the integration interval fixed, it is therefore necessary to negate a portion of the integration at the beginning of the integration interval. To accomplish this, it is necessary to store continuously (or in increments) the results of integration, beginning at the starting point (e.g., α c .sbsb.12 -π) until the maximum possible &#34;shift&#34; of a quarter period (e.g. α c .sbsb.12 -π/2), and to subtract the stored quantity appropriate for the extension of the integration at the other end as specified in Equations (5). 
     In order to describe the above control principles in digital terms, it is useful to rewrite Equations (5) in a form in which the integrations are approximated as sums of finite terms. This means, for example, that the integration interval, π, is divided into n subintervals; during a subinterval, the integration is approximated by multiplying the value of the integrand (taken at a point of the subinterval) with the subinterval; finally, all n products are summed. For example, if the interval (α c .sbsb.12 -π, α c .sbsb.12) is divided into n subintervals by the points 
     
         α.sub.c.sbsb.12 -π ωt.sub.o -π&lt;ωt.sub.1 -π&lt;. . . &lt;ωt.sub.(k-l) -π&lt;ωt.sub.k -π&lt;. . . ωt.sub.n -π=α.sub.c.sbsb.12 
    
     and we find the corresponding value of function v 23  (ξ 12 .sbsb.k)i 2  (ξ 12 .sbsb.k) for any (ωt-π)=ξ 12 .sbsb.k in the interval (ωt k-l  -π, ωt k  -π), then the expression ##EQU6## in Equations (5) may be approximated by ##EQU7## If the n subintervals are of equal length, that is, 
     
         ωt.sub.k -ωt.sub.(k-l) =ωt.sub.(k=l) -ωt.sub.k =. . . =(π/n) 
    
     then, ##EQU8## where q 12a , q 12b , q 23a , q 23b , and q 31a , q 31b  are the instantaneous values of the corresponding voltage and current products appearing in the respective compensating reactive power requirements Q 12 , Q 23  and Q 31 , and K is a constant scale factor: ##EQU9## By combining the terms q a  and q b  into one single term q=q a  +q b  Equation (7) is further simplified as shown below: ##EQU10## 
     On the basis of Equations (6), the mechanism of the control proposed can be described in more specific terms for one of the three phases, for example phase 12, as illustrated in FIG. 3. 
     1. The interval (α c .sbsb.12 -π, α c .sbsb.12), with a length of π, is subdivided into n equal subintervals π/n. 
     2. The computation begins at a time corresponding to angle α c .sbsb.12 -π, i.e., half a period prior to the earliest firing point, α c .sbsb.12. 
     3. The products v 23  i 2  and v 31  i 1  are sampled (measured) in or, for convenience, at the end of the first subinterval and are added to give the value 
     
         q.sub.12.sbsb.1 =v.sub.23 (ξ.sub.12.sbsb.1)i.sub.2 (ξ.sub.12.sbsb.1)=v.sub.31 (ξ.sub.12.sbsb.1)i.sub.1 (ξ.sub.12.sbsb.1). 
    
     The quantity q 12 .sbsb.1 is stored. 
     4. The products v 23  i 2  and v 31  i 1  are sampled at the end of the second subinterval and are added to give the value: 
     
         q.sub.12.sbsb.2 =V.sub.23 (ξ.sub.12.sbsb.2)i.sub.2 (ξ.sub.12.sub.2)=v.sub.31 (ξ.sub.12.sbsb.2)i.sub.1 (ξ.sub.12.sbsb.2). 
    
     q 12 .sbsb.2 is stored. q 12 .sbsb.1 and q 12 .sbsb.2 are summed to give q 12 .sbsb.S2 =q 12 .sbsb.1 +q 12 .sbsb.2. 
     5. The products v 23  i 2  and v 31  i 1  are sampled at the end of the third subinterval and are added to provide q 12 .sbsb.3. 
     
         q.sub.12.sbsb.3 =v.sub.23 (ξ.sub.12.sbsb.3)i.sub.2 (ξ.sub.12.sbsb.3)+v.sub.31 (ξ.sub.12.sbsb.3)i.sub.1 (ξ.sub.12.sbsb.3) 
    
     q 12 .sbsb.3 is stored. q 12 .sbsb.3 is added to q 12 .sbsb.S2 to provide: ##EQU11## 
     6. The above process is repeated for every successive subinterval up to subinterval n/2, at which the previous operations are again performed: 
     
         q.sub.12.sbsb.n/2 =v.sub.23 (ξ.sub.12.sbsb.n/2)i.sub.2 (ξ.sub.12.sbsb.n/2)+V.sub.31 (ξ.sub.12.sbsb.n/2)i.sub.1 (ξ.sub.12.sbsb.n/2). 
    
     q 12 .sbsb.n/2 is stored. q 12 .sbsb.n/2 is then summed to q 12 .sbsb.S(n/2-1) to provide ##EQU12## 
     7. In the subintervals following α 12 .sbsb.n/2, it is no longer necessary to store the instantaneous value of q 12 .sbsb.k (since the possible shift of the integration interval cannot be more than a quarter period, π/2, which corresponds to n/2 subintervals). Thus the operations performed, in, for example the n/2+l&lt;n subinterval are as follows: 
     
         q.sub.12.sbsb.(n/2+l) =v.sub.23 (ξ.sub.12.sbsb.(n/2+l))i.sub.2 (ξ.sub.12.sbsb.(n/2+l))+v.sub.31 
    
     
         (ξ.sub.12.sbsb.(n/2+l))i.sub.1 (ξ.sub.12.sbsb.(n/2+l)).q.sub.12.sbsb.(n/2+l) 
    
     is summed to 
     
         q.sub.12.sbsb.S(n/2+l-1) 
    
     to provide ##EQU13## [Here l is the number of subintervals being evaluated in the interval (α c  -π/2, α c )]. 
     8. At ξ 12 .sbsb.n =α c .sbsb.12 (i.e., at the earliest firing point) the operation, per Equations (6), is performed ##EQU14## [Q 12  (α c .sbsb.12) represents the compensation required in phase 12, calculated in the half period interval just preceding α c .sbsb.12 ]. From Q 12  (α c .sbsb.12), the required inductor current ##EQU15## and, subsequently, the corresponding firing angle α 12  is computed; ##EQU16## where I cc  is the amplitude of the fixed capacitor current and V 12  is the amplitude of the line-to-line voltage v 12 . 
     9. If α 12  computed&gt;α c .sbsb.12 +π/n, that is, firing is not needed at α c .sbsb.12, or in the interval (α c .sbsb.12, α c .sbsb.12 +π/2), the computation is continued in the first π/2 subinterval following ξ 12 .sbsb.n =α c .sbsb.12 point in accordance with Equations (6) i.e., 
     a. The products v 23  i 2  and v 31  i 1  are sampled at the end of the n+1 subinterval (i.e., at ωt=α c .sbsb.12 +π/n) and q 12 .sbsb.(n+1) is computed: 
     
         q.sub.12.sbsb.(n+1) =v.sub.23 (ξ.sub.12.sbsb.(n+1))i.sub.2 (ξ.sub.12.sbsb.(n+1))+v.sub.31 (ξ.sub.12.sbsb.(n+1))i.sub.1 (ξ.sub.12.sbsb.(n+1)). 
    
     b. q 12 .sbsb.(n+1) is added to q 12 .sbsb.Sn to provide ##EQU17## 
     c. q 12 .sbsb.1 (i.e., q 12  obtained and stored at the end of the first subinterval) is subtracted from q 12 .sbsb.S(n+1) and the difference is multiplied by -1/√3n to provide the reactive power compensation required. ##EQU18## 
     d. From the reactive power Q 12  (α c .sbsb.12 +π/n), the corresponding inductor current ##EQU19## and, subsequently, the corresponding firing angle is determined; ##EQU20## 
     10. If α 12  &gt;α c .sbsb.12 +2π/n, that is, firing is not needed at α c .sbsb.12 +π/n, or in the interval (α c .sbsb.12 +π/n, α c .sbsb.12 +2π/n), the above computation is repeated in the next (π/n) subinterval, i.e., in the interval (α c .sbsb.12 +/n,α c .sbsb.12 +2π/n), and so on. Assuming that the condition for firing is satisfied at the mth subinterval after α c , i.e., α 12  &lt;α c .sbsb.12 +(m+1) π/n, the computation in the last subinterval is analogous to those shown under #9. That is: 
     a. The products v 23  i 2  and v 31  i 1  are sampled at the end of the n+m subinterval and q 12 .sbsb.(n+m) is computed: 
     
         q.sub.12.sbsb.(n+m) =v.sub.23 (ξ.sub.12.sbsb.(n+m))i.sub.2 (ξ.sub.12.sbsb.(n+m))+v.sub.31 (ξ.sub.12.sbsb.(n+m))i.sub.1 (ξ.sub.12.sbsb.(n+m)) 
    
     b. q 12 .sbsb.(n+m) is added to q 12 .sbsb.S(n+m-1) to provide ##EQU21## 
     c. The sum ##EQU22## is produced [recall that each q 12 .sbsb.k (k=1,2 . . . m=≦n/2) has been stored] and subtracted from q 12 .sbsb.S(n+m) ; the difference is multiplied by -1/√3n to obtain the reactive power compensation Q 12  (α c .sbsb.12 +mπ/2) required; ##EQU23## 
     d. From Q 12  (α c .sbsb.12 +mπ/n), the corresponding inductor current ##EQU24## and, subsequently, the corresponding firing angle is determined ##EQU25## 
     10. At the firing angle α 12 , which is in the interval (α c .sbsb.12 +π/n, α c .sbsb.12 +(m+1) π/n, the thyristor switch in phase 12 is fired. 
     As is evident from the above description, the procedure described does, in effect shift the original integration interval (α c .sbsb.12 -π,α c .sbsb.12) to coincide with the half period interval (α 12  -π,α 12 ) just prior to the actual firing. It is also clear that by making n appropriately large, and thereby the subinterval π/n short, the approximations indicated in Equations (6) can approach the exact expressions give in (5) as closely as desired. 
     The control principles with the computation procedure described may be implemented by either analog or digital circuits. 
     Referring once again to FIG. 4, an example of a shifting firing angle computer implemented with analogue type circuit elements (for calculating α 12 ) is shown. This block diagram contains four-quadrant Analog Multipliers X1, X2; Adder/Subtractors S1, S2, S3; Amplifiers K, 1/V 12  ; a Resettable Integrator I; a Sample and Hold functional circuit (S/H); an Analog Delay Line (ADL) consisting of n series sample and holds and a common clock, sometimes called a &#34;bucket brigade&#34; in the literature; a Phase Locked Loop device (PLL) which providing real time digital signals in prescribed phase relationship to its input signal (here v 12 ); a Function Generator (FG) which provides a firing angle-inductor current relationship; and a Comparator (COMP) which provides a firing pulse output at α 12 . Two monostable circuits MS1, MS2 are also employed. 
     In the implementation of the analog shifting firing angle computer, it is assumed that the required voltage and current signals are appropriately obtained by the voltage calculators V 12  C, V 23  C and V 31  C for example. In accordance with Equations (5) or its simplified form, Equation (8), the instantaneous values of the voltage and current products q 12a  and q 12b  appear at the outputs of X1 and X2 respectively. The products are summed by summing device S1 resulting in q 12 . The quantity q 12  is scaled by passing it through device K after which the signal K q 12  is obtained. The same K q 12  signal must then be integrated with three different boundaries according to integrals A, B, and C, defined in Equations (5) or (8). Fortunately, these boundaries are such that all three integrals can be derived from the single analog integrator I. The initiation of I is accomplished by resetting the integrator at each α c .sbsb.12 to zero. Since α c .sbsb.12 is constant and locked to the power line frequency, the phase locked loop PLL can trigger MS1 which in turn triggers MS2 thus providing two short pulses. The second pulse starts when the first pulse is terminated. The second pulse is used for resetting I, the first pulse controls the Sample and Hold S/H which samples and stores the final value of I just before it is reset. This is repeated in every half cycle of the line voltage. The resettable Integrator I output is connected to the input of the analog delay line ADL which is also controlled by clock pulses from PLL to provide a half cycle delay for the Integrator I output signal (f v .sbsb.12 =60 Hz in FIG. 4). There is at this point a stored, a delayed, and of course, an instantaneous output of Resettable Integrator I. 
     The stored output represents the complete half cycle integral of K q 12  between α c .sbsb.12 -π and α c .sbsb.12 of consecutive half cycles, therefore, the S/H output is equal to expression (A) in Equations (4) or (8). 
     The delayed output repesents the integral of K q 12  as it occurred 180° earlier. Therefore, according to Equations (5) or (8), this signal is equal to the quantity given in (C). 
     The instantaneous output of I represents (B), because as has been stated stated earlier, I is reset at each α c .sbsb.12 instant, which is the lower limit for the integral given in (B). The two real time signals (B) and (C), and the stored signal (A) are summed by summer S2 according to their signs in the equations. From S2, we obtain the reactive power required for compensation. 
     The reactive power Q 12  (α c .sbsb.12 +mπ/n) is converted to inductor current I L  by the constant scale (gain) factor I/V 12  and then subtracted from I cc  according to Equations (16) by S3. The effect of voltage amplitude variation is taken care of by the Function Generator (FG). The Function Generator (FG) and Comparator (COMP) with firing angle α 12  output are redrawn for completeness of the block diagram and easier comparison with prior art techniques. 
     It will be noted with respect to the embodiment of the invention shown in FIG. 4 that the schematic block diagram of the α 12  calculator is shown in detail. 
     For purposes of simplicity of illustration, the α 23  calculator and the α 31  calculator are shown only as separate functional blocks, it being realized that the internal construction of the various control elements are essentially the same as those shown in the α 12  calculator. 
     It is to be understood with respect to the embodiments of this invention that the load which is schematically shown as an arc furnace in FIG. 4 is not limited thereto. In fact, the regulating circuit and control apparatus shown in FIG. 4 may be utilized for compensating for the reactive load effects of any kind of load which has a wildly-varying reactive component. It is also to be understood that compensation for both negative and positive cycles of current and voltage may be accomplished. It is also to be understood that the techniques for obtaining the load currents i 1 , i 2 , and i 3  may include conventional current monitoring techniques such as those which utilize current transformers and the like. It is to be understood that the utilization of a fixed delay angle α c .sbsb.12 is not necessary for the proper operation of this circuit and the utilization thereof is merely illustrated in FIG. 3, for example, to give a clear indication of the advanced apparatus which is provided by this invention. In a trivial but nevertheless sometimes desirable situation, the fixed delay angle α c .sbsb.12 may be considered to be 0°. 
     The apparatus described with respect to the embodiments of this invention have many advantages. One advantage lies in the fact that the source currents I S1 , I S2 , I S3  as shown in FIG. 4 may appear to be in-phase with the source voltages v t1 , v t2 , and v t3  even though the load currents i 1 , i 2 , and i 3  vary wildly due to the effects of the load. Another advantage lies in the fact that in a three-phase AC system such as is shown in FIG. 4, the source currents I S1 , I S2 , and I S3  may be balanced by the compensator 10 even though the load currents i 1 , i 2 , and i 3  are not balanced. Another advantage lies in the fact that the extension of the computation interval into the half cycle in which compensation is to be made by an amount as large as the angle α 12  allows for the utilization of the most recent data to determine the value of the angle α 12 . This has the tendency to improve the reliability, accuracy, and speed of the control system in terms of determining the proper amount of compensating current for providing balanced and near unity phase relationships for the source currents I S1 , I S2 , and I S3  in relationship to the terminal or source voltages.