Abstract:
An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present invention is related to the following commonly-owned, co-pending United States patent applications filed on even date herewith, the entire contents and disclosure of each of which is expressly incorporated by reference herein as if fully set forth herein. U.S. patent application Serial No. (YOR920070268US1 (21189)), for “A SHARED PERFORMANCE MONITOR IN A MULTIPROCESSOR SYSTEM”; U.S. patent application Serial No. (YOR920070293US1 (21233)), for “OPTIMIZED COLLECTIVES USING A DMA ON A PARALLEL COMPUTER”; U.S. patent application Serial No. (YOR920070295US1 (21232)), for “DMA SHARED BYTE COUNTERS IN A PARALLEL COMPUTER”; U.S. patent application Serial No. (YOR920070297US1 (21208)), for “MULTIPLE NODE REMOTE MESSAGING”; U.S. patent application Serial No. (YOR920070298US1 (21209)), for “A METHOD AND APPARATUS OF PREFETCHING STREAMS OF VARYING PREFETCH DEPTH”; U.S. patent application Serial No. (YOR920070299US1 (21212)), for “PROGRAMMABLE PARTITIONING FOR HIGH-PERFORMANCE COHERENCE DOMAINS IN A MULTIPROCESSOR SYSTEM”; U.S. patent application Serial No. (YOR920070300US1 (21211)), for “METHOD AND APPARATUS FOR SINGLE-STEPPING COHERENCE EVENTS IN A MULTIPROCESSOR SYSTEM UNDER SOFTWARE CONTROL”; U.S. patent application Serial No. (YOR920070301US1 (21210)), for “INSERTION OF COHERENCE EVENTS INTO A MULTIPROCESSOR COHERENCE PROTOCOL”; U.S. patent application Serial No. (YOR920070302US1 (21216), for “METHOD AND APPARATUS TO DEBUG AN INTEGRATED CIRCUIT CHIP VIA SYNCHRONOUS CLOCK STOP AND SCAN”; U.S. patent application Serial No. (YOR920070303US1 (21236)), for “DMA ENGINE FOR REPEATING COMMUNICATION PATTERNS”; U.S. patent application Serial No. (YOR920070304US1 (21239)), for “METHOD AND APPARATUS FOR A CHOOSE-TWO MULTI-QUEUE ARBITER”; U.S. patent application Serial No. (YOR920070307US1(21245)), for “BAD DATA PACKET CAPTURE DEVICE”; U.S. patent application Serial No. (YOR920070321US1 (21256)), for “EXTENDED WRITE COMBINING USING A WRITE CONTINUATION HINT FLAG”; U.S. patent application Serial No. (YOR920070322US1 (21255)), for “A SYSTEM AND METHOD FOR PROGRAMMABLE BANK SELECTION FOR BANKED MEMORY SUBSYSTEMS”; U.S. patent application Serial No. (YOR920070323US1 (21246)), for “AN ULTRASCALABLE PETAFLOP PARALLEL SUPERCOMPUTER”; U.S. patent application Serial No. (YOR920070324US1 (21264)), for “SDRAM DDR DATA EYE MONITOR METHOD AND APPARATUS”; U.S. patent application Serial No. (YOR920070337US1 (21281)), for “A CONFIGURABLE MEMORY SYSTEM AND METHOD FOR PROVIDING ATOMIC COUNTING OPERATIONS IN A MEMORY DEVICE”; U.S. patent application Serial No. (YOR920070338US1 (21293)), for “ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT”; U.S. patent application Serial No. (YOR920070339US1 (21292)), for “STATIC POWER REDUCTION FOR MIDPOINT-TERMINATED BUSSES”; U.S. patent application Serial No. (YOR920070340US1 (21295)), for “COMBINED GROUP ECC PROTECTION AND SUBGROUP PARITY PROTECTION”; U.S. patent application Serial No. (YOR920070355US1 (21299)), for “A MECHANISM TO SUPPORT GENERIC COLLECTIVE COMMUNICATION ACROSS A VARIETY OF PROGRAMMING MODELS”; U.S. patent application Serial No. (YOR920070356US1 (21263)), for “MESSAGE PASSING WITH A LIMITED NUMBER OF DMA BYTE COUNTERS”; U.S. patent application Serial No. (YOR920070357US1 (21312)), for “ASYNCRONOUS BROADCAST FOR ORDERED DELIVERY BETWEEN COMPUTE NODES IN A PARALLEL COMPUTING SYSTEM WHERE PACKET HEADER SPACE IS LIMITED”; U.S. patent application Serial No. (YOR920070361US1 (21215)), for “HARDWARE PACKET PACING USING A DMA IN A PARALLEL COMPUTER”; and U.S. patent application Serial No. (YOR920070371US1 (21335)), for “POWER THROTTLING OF COLLECTIONS OF COMPUTING ELEMENTS”. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OF DEVELOPMENT 
       [0002]    The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract. No. B554331 awarded by the Department of Energy. 
     
    
     BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    The present invention generally relates to computer systems having multiprocessor architectures and, more particularly, to a novel multi-processor computer system for processing memory accesses requests. 
         [0005]    2. Description of the Prior Art 
         [0006]    To achieve high performance computing, multiple individual processors have been interconnected to form multiprocessor computer systems capable of parallel processing. Multiple processors can be placed on a single chip, or several chips—each containing one or several processors—interconnected into a multiprocessor computer system. 
         [0007]    Processors in a multiprocessor computer system use private cache memories because of their short access time (a cache is local to a processor and provides fast access to data) and to reduce the number of memory requests to the main memory. However, managing caches in a multiprocessor system is complex. Multiple private caches introduce the multi-cache coherency problem (or stale data problem) due to multiple copies of main memory data that can concurrently exist in the multiprocessor system. 
         [0008]    Small-scale shared memory multiprocessing systems have processors (or groups thereof) interconnected by a single bus. However, with the increasing speed of processors, the feasible number of processors that can share the bus effectively decreases. 
         [0009]    The protocols that maintain the coherence between multiple processors are called cache coherence protocols. Cache coherence protocols track any sharing of data blocks between the processors. Depending upon how data sharing is tracked, cache coherence protocols can be grouped into two classes: directory based and snooping. 
         [0010]    In a multiprocessor system with coherent cache memory, consistency is maintained by a coherence protocol that generally relies on coherence events sent between caches. A common hardware coherence protocol is based on invalidations. In this protocol, any number of caches can include a read-only line, but these copies must be destroyed when any processor stores to the line. To do this, the cache corresponding to the storing processor sends invalidations to all the other caches before storing the new data into the line. If the caches are write-through, then the store also goes to main memory where all caches can see the new data. Otherwise, a more complicated protocol is required when some other cache reads the line with the new data. 
         [0011]    In a cache-coherent multiprocessor system, there may be bursts of activity that cause coherence actions, such as invalidations, to arrive at a cache faster than the cache can process them. In this case, they are generally stored in first-in, first-out (FIFO) queues, thereby absorbing the burst of activity. As known, FIFO queues are a very common structure used in computer systems. They are used to store information that must wait, commonly because the destination of the information is busy. For example, requests to utilize a shared resource often wait in FIFO queues until the resource becomes available. Another example is packet-switched networks, where packets often wait in FIFO queues until a link they need becomes available. 
         [0012]    A common operation in a multiprocessor is memory synchronization, which insures that all memory accesses and their related coherence protocol events started before some point in time have completed. For example, memory synchronization can be used before initiating a DMA transfer of data prepared in memory. The synchronization insures that the memory is completely consistent before the DMA transfer begins. 
         [0013]    Before a multiprocessor memory synchronization can complete, all coherence protocol events that were initiated prior to the synchronization must be processed. Some of these events could be stored in FIFO queues in the coherence logic of the multiprocessor. One way to make sure all such events have been processed is to drain all of the FIFO queues before completing the memory synchronization. However, this is inefficient because coherence events that arrived after the memory synchronization began are unnecessarily processed, causing a delay in the completion of the synchronization. A second problem with this approach is that processors must be prevented from generating new coherence actions or else the queues will continue to fill, potentially causing a livelock. Stopping all of the processors is necessary for the complete draining approach, but inefficient. 
         [0014]    What is needed is a mechanism for tracking queue entries that existed prior to the memory synchronization, and completing the synchronization when those entries have been processed. Ideally, the memory system should be allowed to continue generating new coherence protocol events while the events prior to the synchronization are draining. 
         [0015]    It would thus be highly desirable to provide a system and method for tracking queue entries that existed prior to the memory synchronization, and completing the synchronization when those entries have been processed. 
         [0016]    Further, it would be desirable to provide a system and method for tracking queue entries wherein the memory system is allowed to continue generating new coherence protocol events while the events prior to the synchronization are draining. 
       SUMMARY OF THE INVENTION 
       [0017]    It is therefore an object of the present invention to provide a novel system and method for tracking coherence event queue entries that existed prior to a memory synchronization operation performed by a processor in a multiprocessor system architecture, and completing the synchronization when those entries have been processed. 
         [0018]    It is a further object of the invention to provide a system and method for tracking queue entries wherein the memory system is allowed to continue generating new coherence protocol events while the events prior to the synchronization are draining (i.e., being dequeued). 
         [0019]    That is, the present invention teaches an apparatus and method for tracking event signals transmitted by processors in a multiprocessor system. According to a first aspect of the invention, the apparatus comprises a queue structure for storing said event signals transmitted in said system; a logic device associated with a queue structure for controlling enqueuing and dequeuing of received event signals at the structure; and, a counting mechanism for tracking a number of event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. The counting mechanism generates an output signal indicating that all of the event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. This output signal indicates that all events present when the timestamp was asserted have completed. 
         [0020]    Further to this embodiment, the logic device generates an enqueue signal for receipt at the queue structure for controlling input of the event signal in the queue structure and a dequeue signal for controlling the dequeuing of coherence event signal from the queue structure. 
         [0021]    Further to this embodiment, the counting mechanism includes a first counter device responsive to assertion of said enqueue signal and dequeue signal for counting a number of enqueued event signals in said queue structure. 
         [0022]    The counting mechanism is further responsive to receipt of the timestamp signal for receiving a count signal representing the number of enqueued signals in the queue structure, the counting mechanism counting down from the number in response to each dequeue signal asserted when each of the enqueued event signals is dequeued from the queue structure, the counting mechanism generating the output signal when it counts down to zero. 
         [0023]    In one additional advantageous embodiment of this invention, flexibility is provided by enabling the counting mechanism to respond to an assertion of a second timestamp signal for tracking a number of events remaining in the queue structure since receipt of a second timestamp signal, issued independently from the assertion of the first timestamp signal. 
         [0024]    In the additional advantageous embodiment of this invention, the counter mechanism in response to assertion of said second timestamp signal, receives the count signal representing the number of enqueued signals in the queue structure, and counts down from the number in response to assertion of each dequeue signals asserted when each of the enqueued coherence event signals is dequeued from the queue structure, and further generating a second output signal when it counts down to zero. 
         [0025]    In the embodiments described, the multiprocessor system performs a memory synchronization operation, such that this output signal is used as part of a completion condition for a memory synchronization operation in the multiprocessor. 
         [0026]    According to a further aspect of the invention, there is provided a method for tracking event signals transmitted in a multiprocessor system, the method comprising: 
         [0027]    intercepting an event signal in the multiprocessor system; 
         [0028]    enqueuing and dequeuing intercepted the event signals at a queue structure of a plurality of queue structures; 
         [0029]    counting a number of event signals enqueued in a respective the queue structure and dequeued from the queue structure since receipt of a timestamp signal, and, 
         [0030]    generating an output signal indicating that all of the event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. 
         [0031]    Further to this aspect of the invention, the method further comprises: 
         [0032]    controlling said enqueuing and dequeuing of intercepted said event signals by generating a respective enqueue signal for receipt at said queue structure for controlling input of said intercepted event signal in said queue structure and a dequeue signal for receipt at said queue structure for controlling said dequeuing of said event signal from said queue structure. 
         [0033]    Further to this aspect of the invention, wherein counting a number of the coherence event signals enqueued and dequeued from each respective queue structure includes: 
         [0034]    implementing a first counter device responsive to assertion of the enqueue signal and dequeue signal for counting a number of enqueued event signals in the queue structure; 
         [0035]    implementing a second counter device responsive to receipt of the timestamp signal for receiving a count signal representing the number of enqueued event signals presently in the queue structure; and, 
         [0036]    counting down from the number in response to assertion of each dequeue signal asserted when removing the enqueued event signal from the queue structure, the second counter device generating the output signal when it counts down to zero. 
         [0037]    Further according to this further aspect of the invention, the method comprises: 
         [0038]    performing a memory synchronization operation by asserting said timestamp inputs for all queue structures in said system, and then waiting until all output signals are asserted before completing a memory synchronization operation. 
         [0039]    Further according to this further aspect of the invention, the method comprises: 
         [0040]    counting a number of coherence event signals enqueued in a respective the queue structure and dequeued from the queue structure since receipt of a second timestamp signal, and, 
         [0041]    responding to assertion of a second timestamp signal for tracking a number of events remaining in the queue structure since receipt of the second timestamp signal. 
         [0042]    In each of the embodiments described, the multiprocessor system may further include an arbitration unit responsive to receipt of said generated output signals associated with a respective queue structure for implementing logic to generate an arbitration signal for input to a processor cache. 
         [0043]    In each of the embodiments described, the event signals may comprise coherence event signals, and the queue unit is a coherence logic unit associated with each processor of the multiprocessor system. The multiprocessor system may further include one or more snoop filter units associated with each the coherence logic unit that process incoming coherence invalidation events and present a reduced number of coherence events to a processor. 
         [0044]    Advantageously, while the invention is described in the context of a microprocessor chip, the invention can be broadly applied to many other digital circuits and systems. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0045]    The objects, features and advantages of the present invention will become apparent to one skilled in the art, in view of the following detailed description taken in combination with the attached drawings, in which: 
           [0046]      FIG. 1  depicts a coherent multiprocessor system  10  consisting of n-processors (e.g., n=4) in which the present invention may be implemented; 
           [0047]      FIG. 2  shows an example structure implementing coherence queuing logic according to the present invention for the system shown in  FIG. 1 . 
           [0048]      FIG. 3  is a diagram of the timestamp queuing structure interface. 
           [0049]      FIG. 4  is a block diagram showing the major components of the timestamp queuing structure. 
           [0050]      FIG. 5  shows a variation of the timestamp queuing structure that provides two independent timestamps. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0051]      FIG. 1  depicts generally an overall base architecture of a multiprocessor system  10  implementing the method and system for tracking queue entries that existed prior to issuance of a timestamp signal, according to the invention. As shown in  FIG. 1 , the multiprocessor system  10  is composed of N processors with N=4 (four) processor devices being illustrated, i.e., processors  100   a , . . . ,  100   d . Although not shown, each processor may be equipped with its own local L1 data and instruction caches, and even associated L2 caches (not shown). Further, although not shown in  FIG. 1 , a main memory may be provided that is shared and can be implemented on-chip or off-chip. In the preferred embodiment, the processor cores  100   a , . . . ,  100   d  are identical but any combination of various processors in a single multiprocessor system can be used without departing from the scope of this invention. 
         [0052]    In one embodiment, when a processor desires to write new data to a cache line, each processor device  100   a , . . . ,  100   d  issues a respective coherence event signal, e.g., invalidate request signal  130   a , . . .  130   d . These invalidation request signals are broadcast from the respective processors, and particularly their associated caches, to every other processor cache in the system. 
         [0053]    Further associated with each processor, as shown in  FIG. 1 , is a corresponding coherence logic unit  125   a , . . .  125   d , that intercepts each invalidate request signal  130   a , . . .  130   d  and generates respective snoop signals  115   a , . . . ,  115   d  which are input to the cache memory processing unit of the processor. According to one embodiment of the present invention, the coherence logic unit generally implements the coherence protocol algorithms and the modifications according to the present invention. The coherence logic units may comprise a directory table or snoop filter structure implementing snoop filter logic provided for each respective processor core  100   a , . . . ,  100   d  such as described in commonly-owned, co-pending U.S. patent application Ser. No. ______ 11/093,131, entitled METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS IN A POINT-TO-POINT INTERCONNECT ARCHITECTURE, the whole contents and disclosure of which is incorporated by reference herein. For transferring coherence event signals, e.g., invalidate request signals  130   a , . . .  130   d , in one embodiment, a point-to-point interconnection scheme  160  is implemented whereby each processor&#39;s associated coherence logic unit is directly connected with each coherence logic unit associated with every other processor in the system. It is understood that other signal coupling architectures may be implemented, e.g., a bus device, to transfer the invalidation request signals between caches associated with the respective processors of the multiprocessor system. Thus, as shown in  FIG. 1 , invalidate requests  130   a , . . .  130   d , in particular, are decoupled from all other memory requests transferred via a system local bus, reducing the congestion of that local bus which is often a system bottleneck. All invalidate requests  130   a , . . .  130   d  to a single processor are forwarded to the coherence logic units  125   a , . . .  125   d . As will be described in greater detail herein, the coherence logic units  125   a , . . .  125   d  processes each invalidate request and implement coherence logic of an n-way multiprocessor in accordance with an invalidation coherence protocol. In the example embodiment depicted in  FIG. 1 , the invalidation coherence protocol governs a four-way multiprocessor. The Coherence Logic at each processor collects invalidations  130   a , . . .  130   d , from the respective remote processors  100   a , . . . ,  100   d , and additionally, an invalidation  130   e  from a direct memory access (DMA) logic unit  150  and forwards them to a processor cache through a respective snoop port, indicated in  FIG. 1  as snoop ports associated with snoop signals  115   a , . . . ,  115   d . In the preferred embodiment, one DMA logic unit participates in the coherence protocol of the multiprocessor system. In another embodiment, multiple DMA units for a multitude of network interfaces participate in the coherence protocol. 
         [0054]    If the inputs and outputs of the Coherence Logic operate at the same speed, then the Coherence Logic units  125   a , . . .  125   d  can receive invalidation requests at four times the rate they can output them to the processor caches. Therefore, according to the invention, the invalidation requests are stored in queues as shown and described herein with respect to  FIG. 2 . 
         [0055]      FIG. 2  particularly illustrates a first-in-first-out (FIFO) queue structure  200  for storing received invalidation requests at a Coherence Logic unit  125   a , . . .  125   d . Four parallel FIFO queues  205  enqueue invalidation requests from the various processors in the system  100  and the outputs of the queues  205  are timed according to an arbitration signal  210  controlling a gated device such as multiplexer  215 . It is to be understood that the invention is not limited to four queues, but can be applied to any number of queues without departing from the scope of the invention. In the preferred embodiment, the queues store coherence events. In another embodiment, the queues store network packets. 
         [0056]    An arbitration unit  220  executes signal processing timed in a manner to control snoop signal requests  225  output from the FIFO queues. Details concerning the operation of the arbitration unit  220  is found in commonly-owned United States patent application Ser. No. ______ [atty docket no. YOR920070304US1 (21239)] the whole contents and disclosure of which is incorporated by reference as if fully set forth herein. In the preferred embodiment, the queues are emptied (drained) as controlled by the arbiter unit. In another embodiment, there is no arbiter or synchronization circuit to synchronize draining of the queues. 
         [0057]      FIG. 3  depicts a diagram of the interface of the timestamp queue  250  of the preferred embodiment, which is preferably implemented in synchronous digital logic circuitry. The timestamp queue receives a timestamp event signal, and allows all entries enqueued prior to a timestamp event to be tagged. The timestamp queue provides a notification when those tagged entries have all been dequeued. New queue entries can be added to the queue during this process of dequeuing of tagged entries. In this manner the system implements efficient memory synchronization. 
         [0058]    A coherence event signal (e.g., invalidation request) is enqueued to the tail of the FIFO queue by placing it on the data_in input  140  of the timestamp queue  250  and pulsing the enqueue input  280  synchronous to the clock input. The coherence event at the head of the queue is always available at the data_out output of the queue. The coherence event at the head of the queue is dequeued, or discarded, by pulsing the dequeue input  290  synchronous to the clock signal. When the timestamp input  275  is pulsed synchronous to the clock signal, all queue entries present at that time are tagged. Once the last of those entries has been dequeued, the timestamp_done output  265  asserts. Therefore, a memory synchronization operation can insure that all coherence protocol events have completed by pulsing the timestamp inputs of all the FIFO queues in the system, and then waiting until all of the timestamp_done outputs assert before completing a memory synchronization. 
         [0059]      FIG. 4  depicts a circuit block diagram  300  of an exemplary embodiment of the timestamp queue of  FIG. 3 . Although not shown, it is assumed that a clock signal is input to the FIFO queue element  305 , and up/down counter  310 , and down counter  315  components. In the exemplary embodiment of the various components of  FIG. 4 , the FIFO component stores the coherence events in the standard first-in, first-out manner as described previously herein. That is, a coherence event on the data_in input is stored when the enqueue input  280  is asserted, and the coherence event on the data_out output is discarded when the dequeue input  290  is asserted. Initially, there are no events stored. 
         [0060]    The up/down counter in  FIG. 4  keeps track of the number of coherence events present in the FIFO  305 . Initially, the up/down counter  310  is set to zero. Whenever the enqueue input  280  is asserted, the counter increments by one. Whenever the dequeue input  290  is asserted, the counter  310  decrements by one. The value of the up/down counter  310  is available on its count output signal  312 . The down counter  315  is initially set to zero. When the timestamp input  275  is asserted, the down counter  315  is loaded with the current value of the up/down counter  310  through the data_in input. Whenever the dequeue input is asserted, the down counter  315  decrements by one. However, it never decrements below zero. The value of the down counter is available on its count output signal  350 . 
         [0061]    The NOR gate  360  shown in  FIG. 4  represents a logical NOR of the bits comprising the count output  350  of the down counter. Those skilled in the art will recognize that the timestamp_done signal  265  is asserted when the value of the down counter is zero, and not asserted otherwise. Therefore, the timestamp_done signal  265  will assert when the down counter  315  has reached zero, indicating that all of the events present in the FIFO at the time of the assertion of the timestamp input  275  have been dequeued. 
         [0062]    In the multiprocessor environment  10  of the preferred embodiment, the timestamp_done outputs of all the timestamp queues can be combined with a logical OR (not shown) to produce a single signal indicating that all coherence events present when timestamp was asserted (i.e. when the memory synchronization began) have completed. This signal can then be used as part of the completion condition for the memory synchronization. 
         [0063]    The timestamp queue of  FIG. 3  could be extended to track two or more timestamps. As shown in  FIG. 5 , in an example two-timestamp implementation, the timestamp queue  400  structure depicted  400  could support multiple, separate timestamps by adding a separate down counter, e.g.,  315   a ,  315   b  for each timestamp signal received  275   a ,  275   b , respectively. Each separate down counter  315   a ,  315   b  loads the value  312  of the up/down counter  310 , but has its own timestamp input, e.g.,  275   a ,  275   b , and its own timestamp_done output  265   a ,  265   b . The timestamp_done_ 1  output  265   a  indicates that all entries present when timestamp_ 1   275   a  was asserted have been dequeued. Similarly, the timestamp_done_ 2  output  265   b  indicates that all entries present when timestamp  2   275   b  was asserted have been dequeued. As in the implementation described herein with respect to  FIG. 3 , the example two or more timestamp signal variation depicted in  FIG. 5  includes two NOR gates  360   a  and  360   b  representing a logical NOR of the bits comprising the count output  350   a,b  of the respective down counter  315   a,b . Those skilled in the art will recognize that the timestamp_done signals  265   a,b  are asserted when the value of their respective down counter is zero, and not asserted otherwise. 
         [0064]    While there has been shown and described what is considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the invention be not limited to the exact forms described and illustrated, but should be constructed to cover all modifications that may fall within the scope of the appended claims.