Abstract:
A circuit for writing, reading, and erasing a programmable device is disclosed. The programmable device includes an ion conductor and a plurality of electrodes. Electrical properties of the device are altered by applying a sufficient bias across the electrode to form a conductive region within the ion conductor. The circuit can be used to program and read multiple bits within a single programmable device.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation of application Ser. No. 11/276,758, entitled READ, WRITE AND ERASE CIRCUIT FOR PROGRAMMABLE MEMORY DEVICES, filed Mar. 13, 2006, which claims the benefit of U.S. Patent Application Ser. No. 60/661,250, entitled READ, WRITE AND ERASE CIRCUITS FOR PROGRAMMABLE METALLIZATION CELLS IN A NON-VOLATILE RANDOM ACCESS MEMORY, filed Mar. 11, 2005. 
     
    
     FIELD OF INVENTION  
       [0002]     The present invention generally circuits for reading, writing, and erasing information, and more particularly, to circuits that are suitable for use with programmable memory devices.  
       BACKGROUND OF THE INVENTION  
       [0003]     Memory devices are often used in electronic systems and computers to store information in the form of binary data. These memory devices may be characterized into various types, each type having associated with it various advantages and disadvantages.  
         [0004]     For example, random access memory (“RAM”), which may be found in personal computers, is typically volatile semiconductor memory; in other words, the stored data is lost if the power source is disconnected or removed. Dynamic RAM (“DRAM”) is particularly volatile in that it must be “refreshed” (i.e., recharged) every few hundred milliseconds in order to maintain the stored data. Static RAM (“SRAM”) will hold the data after one writing so long as the power source is maintained; once the power source is disconnected, however, the data is lost. Thus, in these volatile memory configurations, information is only retained so long as the power to the system is not turned off. In general, these RAM devices can take up significant chip area and therefore may be expensive to manufacture and consume relatively large amounts of energy for data storage.  
         [0005]     One type of programmable semiconductor non-volatile memory device suitable for use in such systems is a programmable read-only memory (“PROM”) device. One type of PROM, a write-once read-many (“WORM”) device, uses an array of fusible links. Once programmed, the WORM device cannot be reprogrammed.  
         [0006]     Other forms of PROM devices include erasable PROM (“EPROM”) and electrically erasable PROM (EEPROM) devices, which are alterable after an initial programming. EPROM devices generally require an erase step involving exposure to ultra violet light prior to programming the device. Thus, such devices are generally not well suited for use in portable electronic devices. EEPROM devices are generally easier to program, but suffer from other deficiencies. In particular, EEPROM devices are relatively complex, are relatively difficult to manufacture, and are relatively large. Furthermore, a circuit including EEPROM devices must withstand the high voltages necessary to program the device. Consequently, EEPROM cost per bit of memory capacity is extremely high compared with other means of data storage. Another disadvantage of EEPROM devices is that, although they can retain data without having the power source connected, they require relatively large amounts of power to program. This power drain can be considerable in a compact portable system powered by a battery.  
         [0007]     Due, at least in part, to a rapidly growing numbers of compact, low-power portable computer systems and hand-held appliances in which stored information changes regularly, low energy read/write semiconductor memories have become increasingly desirable and widespread. Furthermore, because these portable systems often require data storage when the power is turned off, non-volatile storage devices are desired for use in such systems.  
         [0008]     Recently, programmable metallization cell (PMC) devices have been developed for use in such systems to replace DRAM, SRAM, PROM, EPROM, EEPROM, and similar devices. PMC devices offer advantages over traditional memory devices because PMC devices can be formed using amorphous material and can thus be added to existing devices formed on a semiconductor substrate. The PMC devices also typically have lower production cost and can be formed using flexible fabrication techniques, which are easily adaptable to a variety of applications. Further, the PMC devices may be scaled to less than a few square microns in size, the active portion of the device being less than on micron. This provides a significant advantage over traditional semiconductor technologies in which each device and its associated interconnect can take up several tens of square microns.  
         [0009]      FIG. 1  illustrates a typical PMC device  100  formed on a surface of a substrate  110 . Device  100  includes electrodes  120  and  130 , an ion conductor  140 , and an electrode  180 . Generally, device  100  is configured such that when a bias greater than a threshold voltage (V T ) is applied across electrodes  120  and  130 , the electrical properties of structure  100  change. For example, as a voltage V≧V T  is applied across electrodes  120  and  130 , conductive ions within ion conductor  140  begin to migrate and form a conductive region (e.g., electrodeposit  160 ) at or near the more negative of electrodes  120  and  130 . As the electrodeposit forms, the resistance between electrodes  120  and  130  decreases, and other electrical properties may also change. If the same voltage is applied in reverse, the electrodeposit will dissolve back into the ion conductor and the device will return to its high resistance state.  
         [0010]     Because PMC devices have advantages over traditional semiconductor memory devices and can be used in a wide variety of applications, improved circuits for reading, writing, and erasing PMC devices are desired. Accordingly, circuits for programming the programmable PMC devices are desired.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention provides improved circuits for use with programmable devices. More particularly, the invention provides programming circuits suitable for reading, writing, and erasing programmable metallization cell devices. Such circuits, including the corresponding programmable structures, can replace both traditional nonvolatile and volatile forms of memory.  
         [0012]     The ways in which the present invention addresses various drawbacks of now-known circuits are discussed in greater detail below. However, in general, the present invention provides a programming circuit and a programmable device that are relatively easy and inexpensive to manufacture and are relatively easy to program.  
         [0013]     In accordance with various embodiments of the invention, the circuit can be used to read, write, and erase multiple bits from a single PMC device. Thus, increased storage density can be achieved using the circuit of the present invention.  
         [0014]     In accordance with one embodiment of the invention, a circuit for reading, writing, and erasing a programmable device includes an array of programmable metallization cells coupled together by a common anode. In accordance with various aspects of this embodiment, the circuit includes a low voltage supply coupled to the anodes of the PMC devices, a switch coupled to the cathode of the PMC device to select a row of PMC elements, a first current source coupled to the cathode and source voltage via a switch, a second current source coupled to the cathode and the low voltage supply via another switch, an equalizer coupled to the cathode, a current comparator coupled to a third current source, and a decoder coupled to the current comparator.  
         [0015]     In accordance another embodiment of the invention, a circuit for reading, writing, and erasing a programmable device includes an array of programmable metallization cells coupled together by a common cathode. In accordance with various aspects of this embodiment, the circuit includes a low voltage supply coupled to the cathodes of an array of OMC devices, a switch coupled to the anode of the PMC device to select a row of PMC elements, a first current source coupled to the anode and the source voltage via a switch, a second current source coupled to the anode and the low voltage supply via another switch, an equalizer coupled to the anode, a current comparator coupled to a third current source and a decoder coupled to the current comparator.  
         [0016]     In accordance with yet another embodiment of the invention, a circuit for writing a programmable device includes a common bias portion and a current selection portion. The current selection portion is used to generate a write current based on a number of bits to be stored in the PMC device, wherein the write resistance is equal to the threshold voltage of the PMC device divided by the selected programming current.  
         [0017]     In accordance with yet another embodiment of the invention, a circuit for erasing a programmable device includes a common bias portion and a current selection portion to perform a current controlled erase of the PMC device.  
         [0018]     In accordance with yet another embodiment of the invention, a circuit for reading a programmable device includes a common bias portion, a current comparator portion, and a read bias circuit. The read bias circuit is used to force a read bias across the PMC element to produce a current for comparison with the current comparator. The output from the comparator is decoded to output binary digital logic corresponding to the values stored in the PMC element. 
     
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES  
       [0019]      FIG. 1  illustrates a programmable metallization cell as known in the art;  
         [0020]      FIGS. 2-3  illustrate circuits for writing, reading, and erasing an array of programmable devices;  
         [0021]      FIGS. 4-5  illustrate circuits for writing programmable device;  
         [0022]      FIGS. 6-7  illustrate circuits for erasing programmable device; and  
         [0023]      FIGS. 8-9  illustrate circuits for reading programmable device. 
     
    
       [0024]     Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. The dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.  
       DETAILED DESCRIPTION  
       [0025]     The present invention provides a circuit for writing, reading, and erasing programmable devices. More particularly, the invention provides a circuit for writing, reading, and erasing a programmable metallization cell. As explained in greater detail below, exemplary circuits of the present invention can be used to read, write, and erase multiple bits in a single programmable device or to store a single bit of information in the device.  
         [0026]      FIG. 2  illustrates a circuit  200  for programming an array of cells, such as cells set forth in  FIG. 1 , where anodes of each cell are tied to a common low-voltage source. A more detailed description of programmable cells including a common anode and common cathode configurations are set forth in U.S. Pat. No. 6,635,914, issued to Kozicki et al., entitled MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME, the contents of which are hereby incorporated herein by reference.  
         [0027]     An amount of a conductive region (e.g., dendrite  160 ) is proportional to the reduced “on” voltage of the device, which may have virtually infinite states. The circuit described below quantizes these resistance states to obtain digital states of the device. The PMC elements may be used to store a single bit or several bits. The erase resistance can also be quantized to increase the resistance of the PMC device from one state to another, or can be defined simply as the full off resistance of the device.  
         [0028]     Circuit  200  includes a supply voltage Vdd, a low supply voltage Vss, switches S 1 -S 6 , current sources  202 ,  204 ,  206 , PMC device  208 , which is part of an array, a current comparator  210 , a decoder  212 , and an equalization circuit  214 . Although illustrated with switches S 1 -S 6 , those skilled in the art appreciate that any suitable isolation device may be employed with the circuit of the present invention. In the illustrative example, the common anodes are coupled to a low-voltage supply, which is equal to the supply voltage, Vdd, minus the maximum erase voltage, V EMAX , which can be applied across the device without causing a breakdown of the device.  
         [0029]     Vdd is coupled to a cathode of a selected PMC element via switch S 1  and switch S 6 . Current source  202  is coupled to Vdd and the cathode via switch S 1  and switch S 5 . Current source  204  is coupled to the cathode via switch S 1  and switch S 4 . Current comparator  210  is coupled to the selected cathode through switches S 1  and S 3 , and a third current source  206  is coupled to comparator  210  and source voltage  210 . Decoder  212  is coupled to the output of current comparator  210 .  
         [0030]     During operation of circuit  200 , in accordance with the illustrative embodiment, a row is selected by closing S 1 , such that only one PMC element  208  is accessed at a time in a predefined column(s) and rows in the array. Once the element is selected, a write, read, or erase function can be performed.  
         [0031]     To erase a device to a full off resistance, switch S 6  is closed, which pulls a cathode voltage to the supply voltage, forcing a negative voltage, V EMAX  across device  208 , which causes a full erase or an increase in the resistance of device  208  to the off state voltage. The erase can also be performed by selecting current source  202 , coupled to Vdd, through switch S 5 , and forcing current from the cathode to the anode of PMC device  208 . It is noted that if a current less than the original write current of the device is selected (as described in more detail below), an erase step can be used to increase the on resistance of device  208  to a higher on resistance, rather than to perform a full erase of the device.  
         [0032]     To write to device  208 , device  208  is first erased to clear any previous resistance state, and then device  208  is programmed with a selected quantized current from Is to Ik, where k is the number of stages of device  208  and Is is the source bias current, by selecting the program current source through switch S 4 . The erase step can optionally be skipped to perform an incremental write from a high on resistance to a lower on resistance state.  
         [0033]     During the write process, the current is pulled from the anode to the cathode of device  208 , using current source  204  pulling toward Vss. The voltage limiting property of the device limits the voltage across the device to the threshold voltage Vt of the device, which is the potential required to perform the write function.  
         [0034]     For the read operation, switch S 2  is closed to force a read bias, equal to the anode voltage minus the one half of Vt across device  208 . Device  208  is then used as a current source. The current generated by device  208  resistance and the read bias (VR) is then compared, using current comparer  210 , to half of the currents Is to Ik. The comparison generates digital signals, which are decoded, using decoder  212 , into binary digital outputs.  
         [0035]     Equalization circuit  214  ensures that the column and row capacitance of the array are always forced to the anode voltage, when no operation is being performed, to prevent unwanted partial programming or erasing.  
         [0036]      FIG. 3  illustrates a circuit  300  for programming an array of cells, such as cells set forth in  FIG. 1 , where the cathodes of each cell in an array are tied to a common voltage source. Similar to circuit  200 , circuit  300  includes a supply voltage Vdd, a low supply voltage Vss, switches S 1 -S 6 , current sources  302 ,  304 ,  306 , PMC device  308 , which is part of an array, a current comparator  310 , a decoder  312 , and an equalization circuit  314  to ensure that the column and row capacitance of the array are always forced to the cathode voltage, when no operation is being performed, to prevent unwanted partial programming or erasing. The cathodes of each device  308  are tied to a low impedance source, which is equal to V EMAX −Vss.  
         [0037]     The operation of circuit  300  is similar to the operation of circuit  200 . For the write operation, S 5  is closed and current is pushed from the anode to the cathode from Vdd. For the erase step, S 4  is closed and current is pulled from the cathode to the anode from the low supply, Vss. During the erase step, the anode of device  308  connects to Vss, which forces a negative bias of V EMAX  across device  308 , when switch S 6  is closed. The bias forced across the device for the read operation is equal to the cathode voltage plus Vt divided by two.  
         [0038]     Referring now to  FIGS. 4-9  various portions of circuits  200  and  300  will be described in more detail.  
         [0039]      FIGS. 4 and 5  illustrate writes circuits  400  and  500 , respectively. Circuit  400  includes a common bias portion  402 , a current selection portion  404 , voltage source Vdd, low-voltage source Vss, transistors Mr and Mc for row and column selection, transistors Mw 1  and MW 2 , transistor ME. Circuit  500  includes a common bias portion  402 , a current selection portion  404 , transistors Me, Mr, and Mc, and transistors M 1 -M 4  to replicate the desired current from current selection portion  404 . Circuits  400  and  500  are configured to allow writing of multiple bits (n) to a programmable device—e.g., device  208  or  308 .  
         [0040]     Current selection is obtained by ratios of transconductance devices, which can be implemented with transistors, as illustrated. Transistors Mr and Mc are used for row and column selection, as described above. A common bias is used for all of the transistors, which generates Is from transistors Ms, Me, and current source Is. The individual currents I 1 , I 2 , I 3  to Ik are generated by the transistor rations M=a 1 , M=a 2 , M=a 3  to M=ak, where k is an integer. Each transistor defines a current leg, where the current in each leg is related by the ratio ak. The first current leg value I 1  is equal to the source current Is. The transistor ratios are related to the size of the necessary element of the respective transistor. The transistor Me selects the desired current I 1  to Ik to program the device, The appropriate current is then replicated through transistors Mw 1  to Mw 2  (Mw 1 -Mw 4  for the common cathode configuration illustrated in  FIG. 5 ).  
         [0041]     Signal Wen allows the selected mirrored current to be pulled for the for the common anode configuration of  FIG. 4  or pushed for the common cathode configuration of  FIG. 5  out of or into devices  208 ,  308 , respectively, causing the bias to quickly drop to Vt. The programmed resistance is then equal to Vt divided by the selected programming current. The discrete number of current sources creates the a number of resistance states of devices  208 ,  308  for multi-bit storage within each device  208 ,  308 . For single-bit write circuits, only one current leg, M 1 , is required and no current selection is required.  
         [0042]      FIGS. 6 and 7  illustrate erase circuits  600  and  700 , for a common cathode and a common anode array configuration, respectively. Transistors Mr and Mc are used for row and column selection, as described above. The same current selection and common bias devices used in the write operation are used in the erase operation circuit. Since generally only a fraction of the programming current is required to erase the device  208 ,  308 , the selected programming current used for the erase will accomplish a full erase if it is the same current as that used for the programming current. Alternatively, the PMC can be partially erased from one on resistance to a higher one by using a current, which is less than the original programming current. Using the programming currents to erase the PMC device is defined as a current controlled erase.  
         [0043]     To perform a current controlled erase, a desired erase current is selected and replicated through transistors Me 1  to Me 4  for the common anode configuration ( FIG. 6 ) and Me 1  to Me 2  for the common cathode configuration ( FIG. 7 ). The signal E EN  allows the selected current to be pushed for the common anode circuit or pulled for the common cathode circuit into or out of respective PMC devices  208 ,  308 . The voltage across the PMC device quickly rises and is limited by the voltage on the anode for the common cathode configuration or the cathode for the common cathode configuration and Vdd for the common anode circuit or Vss for the cathode circuit.  
         [0044]     To perform a voltage erase, transistor Mev is turned on by the signal Ev and the sourcing or sinking transistors of the common anode or common cathode circuits, respectively, pull the cathode voltage or anode voltage to Vdd and Vss, causing a negative V EMAX  to be forced across the PMC device to perform a full erase of the device.  
         [0045]      FIGS. 8 and 9  illustrate read circuits in accordance with the present invention for common anode and common cathode circuits, respectively. As noted above, transistors Mr and Mc are used for row and column selection to select a particular PMC element  208 ,  308 .  
         [0046]     Transistor M BIAS  and amplifier  802 ,  902  are used to force the read bias of Vt/2 across the PMC device, in accordance with an exemplary embodiment of the invention. The signal READ enables the amplifier. Vt/2 was selected, so that the resistance state of the device is not disturbed by the read operation. Those skilled in the art will appreciate that other values may suitably be selected in accordance with other embodiments of the invention.  
         [0047]     The current is then mirrored to current comparator  404  through transistor MRC. Common bias circuit  402  current is mirrored to current comparator circuit  802 ,  902  directly in the common anode circuit  800  and through MS in the common cathode circuit  900 . The read bias circuits  804 ,  904  illustrated in  FIGS. 8 and 9  are merely exemplary circuits. Other, alternative circuits could be used, as long as the circuit forces a constant bias across the PMC device to generate a current for comparison.  
         [0048]     In exemplary current comparator circuit  802 ,  902 , half of the source current is replicated in the same number of legs as the programming current selector circuit  404 , with the same ratios divided by two. Since the read bias is half of Vt, the current generated is half of the programming current, which is why the ratios in current comparators  802 ,  902  are divided by two.  
         [0049]     Each leg in current comparators  802 ,  902  compares current from the PMC device to one half of the respective source current. The voltage at node Re 1  to Rek will pull high in the common anode circuit  800  if the PMC device current is less than the given programmed current and pull low if the PMC device current is greater than the source current. In the common cathode configuration, circuit  900 , the voltage at Re 1  to Rek pulls in the opposite direction. Transistors Mr 1  to Mrk are scaled by C 1  to Ck to ensure that the voltage Re 1  to Rek do not fall at mid range value, so a comparator is not needed. The bias across the PMC device and the size ratios of the transistors in current comparators  802 ,  902  can also be changed to produce the same effect. The output is then edge enhanced with inverters and decoded to output binary digital logic corresponding to the values stored in memory.  
         [0050]     The number of current legs for n bits is k=2 n−1 , where k and n are both integers. An off resistance may correspond to the low values for a digital word of n bits, the resistance associated with Ik corresponds to the high values for the digital work of n bits, and the resistance associated with I 1  to Ik−1 corresponds to the binary combinations of the digital word of n bits in a multi-bit PMC device. In a single-bit PMC device, an off resistance may correspond to a digital low and an on resistance, programmed with Is, corresponds to a digital  1 , with Re 1  being the single output. The single bit read is performed in the same way, except only one current leg is required.  
         [0051]     Although the present invention is set forth herein in the context of the appended drawing figures, it should be appreciated that the invention is not limited to the specific form shown. Various modifications, variations, and enhancements in the design and arrangement of the method and apparatus set forth herein, may be made without departing from the spirit and scope of the present invention as set forth in the appended claims.