Abstract:
An image sensor is wieldy used in many fields, including medical field and security device. Specifically, the image sensor is most widely used in digital camera and mobile phone. The digital camera and the mobile phone requires capture image of higher resolution and higher quality. However, a preview size of the mobile phone or digital camera requires a small size because of a display limitation. Therefore, a function of reducing an image size or magnifying a specific portion of the picture is essential in the image sensor. Accordingly, there is provided an image sensor with a scaler. The image sensor with the scaler can arbitrarily adjust a size of an image without any additional scaling chip.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 11/319,553, filed on Dec. 29, 2005, entitled “IMAGE SENSOR WITH SCALER AND IMAGE SCALING METHOD THEREOF”, the entirety of which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to a CMOS image sensor; and, more particularly, to a CMOS image sensor with a scaler and an image scaling method thereof. 
       DESCRIPTION OF THE RELATED ART 
       [0003]    An image sensor is an apparatus to capture images using light sensing semiconductor materials. Since brightness and wavelength of light from an object are different in their amount according to the reflection area, electrical signals from pixels are different from one another. These electrical signals are converted into digital signals, which can be processed in a digital circuit. 
         [0004]      FIG. 1  is a block diagram of an image sensor. 
         [0005]    Referring to  FIG. 1 , the image sensor includes a pixel array  10  with M×N unit pixels (M and N are positive integers), a timing controller  11 , an analog signal processor  12 , an image signal processor  14 , and a line memory  13 . 
         [0006]    The analog signal processor  12  is provided with a correlated double sampling (CDS) and analog amplifier  121 , and an analog-to-digital converter (ADC)  122 . 
         [0007]    The timing controller  11  is called a control and external system interface. The timing controller  11  controls an overall operation of the image sensor using a finite state machine (FSM) and serves as an interface for an external system. Also, since the timing controller  11  has a batch register, it can program contents related to several internal operations and controls an overall chip operation according to the program information. 
         [0008]    The pixel array  10  includes M×N unit pixels configured to maximize light-sensitive characteristics. The pixel array  10  is a core of the image sensor and detects information about an image inputted from the outside. 
         [0009]    In the CDS and analog amplifier  121 , the CDS removes a fixed pattern noise of a pixel using a CDS method, and the analog amplifier converts a pixel signal into an electric signal. 
         [0010]    The ADC  122  converts an analog voltage detected by each pixel of the pixel array  10  into a digital voltage that can be processed at a digital system. 
         [0011]    The line memory  13  stores the digital voltage of the pixel, which is converted by the ADC  122 . The line memory  13  includes a plurality of lines for executing various functions of the image signal processor  14 . 
         [0012]    The image signal processor  14  executes several functions for improving the performance of the image sensor, based on the pixel output value stored in the line memory  13 . Examples of the functions are a color interpolation, a color correction, a gamma correction, an auto white balance, an auto exposure, and so on. 
         [0013]    Generally, a camera system using an image sensor includes an image sensor and a back-end chip. The image sensor converts an optical signal into an electric signal, and transfers the corresponding image information. The back-end chip receives the image information from the image sensor, enhance an image picture, compresses the information, and adjusts an image size. In the image sensor, the number of pixels has increased up to million pixels and continuously increases rapidly. However, a preview size of a mobile phone or digital camera requires a small size because of a display limitation. Therefore, the image scaling becomes important in the back-end chip. 
         [0014]    However, after the image information of one picture from the image sensor is all stored, the back-end chip has to adjust the image size. Therefore, a long time is taken for the image scaling. An operation speed of the image sensor is limited due to the speed of the image scaling processed by the back-end chip. Consequently, a frame rate of the image sensor is degraded and a picture is broken in the preview of the mobile phone or digital camera. 
       SUMMARY OF THE INVENTION 
       [0015]    It is, therefore, an object of the present invention to provide an image sensor with an embedded scaling function and an image scaling method thereof, in which the scaling can be executed without any additional scaler chip. 
         [0016]    In accordance with an aspect of the present invention, there is provided an image sensor including: a pixel array having a plurality of pixels formed to maximize light sensing characteristic, the pixel array being configured to detect information on an external image; a timing controller for controlling an overall operation of the image sensor; an analog signal processor for converting an analog signal from the pixel array into a corresponding digital signal under control of the timing controller; a line memory for storing the digital signal in line unit; an image signal processor for processing a plurality of images by using the digital signal stored in the line memory so as to improve performance of the image sensor; and a scaler for receiving a scaling factor of a desired image size from the timing controller and calculating a scaling ratio so as to adjust an image size, and generating a corresponding row/column address and data and scaling the image stored in the line memory, whereby the image with the desired size is outputted. 
         [0017]    In accordance with another aspect of the present invention, there is provided an image scaling method of an image sensor, including: calculating a scaling ratio corresponding to scaling factors (SCALEM, SCALEN) for outputting an image with a desired size, wherein the scaling ratio is SCALEM/SCALEN; determining whether to execute a pre-scaling according to the scaling ratio; when the pre-scaling is necessary to execute, executing the pre-scaling to adjust the size of the image; determining whether to execute a post-scaling; when the post-scaling is necessary to execute, executing the post-scaling to adjust the size of the image; and synchronizing image data scaled through the pre-scaling and the post-scaling with an output clock of the image sensor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
           [0019]      FIG. 1  is a block diagram of an image sensor; 
           [0020]      FIG. 2  is a block diagram of a CMOS image sensor in accordance with an embodiment of the present invention; 
           [0021]      FIG. 3  is a block diagram of a scaler of  FIG. 2 ; 
           [0022]      FIG. 4  is a flowchart diagram illustrating an image scaling algorithm of the scaler in  FIG. 2 ; 
           [0023]      FIG. 5  is a block diagram of a scaling ratio generator of in  FIG. 3 ; 
           [0024]      FIG. 6  is a block diagram of a pre-scaler of  FIG. 3 ; 
           [0025]      FIG. 7  is a block diagram of a post-scaler of  FIG. 3 ; 
           [0026]      FIG. 8A  illustrates an output of the pre-scaler in a full color data level when the pre-scaling ratio is 1/4; 
           [0027]      FIG. 8B  illustrates an output of the pre-scaler in a bayer data level when the pre-scaling ratio is 1/4; 
           [0028]      FIG. 9A  illustrates an output of the post-scaler in a full color data level when the post-scaling ratio is 5/7 with respect to a post 14×14 pixel array; 
           [0029]      FIG. 9B  illustrates an output of the post-scaler in a bayer data level when the post-scaling ratio is 5/7 with respect to a post 14×14 pixel array; and 
           [0030]      FIG. 10  is a flowchart diagram illustrating an algorithm of generating row/column addresses for the image scaling. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0031]    An image sensor with a scaler and an image scaling method thereof in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
         [0032]      FIG. 2  is a block diagram of a CMOS image sensor in accordance with an embodiment of the present invention. 
         [0033]    Referring to  FIG. 2 , the CMOS image sensor includes a pixel array  20  with M×N unit pixels (M and N are positive integers), a timing controller  21 , an analog signal processor  22 , an image signal processor  24 , a line memory  23 , and a scaler  25 . 
         [0034]    The analog signal processor  22  is provided with a CDS and analog amplifier  221 , and a CDS  222 . 
         [0035]    The timing controller  21  is called a control and external system interface. The timing controller  11  controls an overall operation of the image sensor using an FSM and serves as an interface for an external system. Also, since the timing controller  21  has a batch register, it can program contents related to several internal operations and controls an overall chip operation according to the program information. 
         [0036]    The pixel array  20  includes M×N unit pixels configured to maximize light-sensitive characteristics. The pixel array  20  is a core of the image sensor and detects information about an image inputted from the outside. 
         [0037]    In the CDS and analog amplifier  221 , the CDS removes a fixed pattern noise of a pixel using a CDS method, and the analog amplifier converts a pixel signal into an electric signal. 
         [0038]    The ADC  222  converts an analog voltage detected by each pixel of the pixel array  20  into a digital voltage that can be processed at a digital system. 
         [0039]    The line memory  23  stores the digital voltage of the pixel, which is converted by the ADC  222 . The line memory  23  includes a plurality of lines for executing various functions of the image signal processor  24 . 
         [0040]    The image signal processor  24  executes several functions for improving the performance of the image sensor, based on the pixel output value stored in the line memory  23 . Examples of the functions are a color interpolation, a color correction, a gamma correction, an auto white balance, an auto exposure, and so on. 
         [0041]    The scaler  25  receives a scaling factor for adjusting the image size and calculates a scaling ratio. Then, the scaler  25  creates row/column address and data corresponding to the scaling ratio and outputs an image with a desired size. 
         [0042]      FIG. 3  is a block diagram of the scaler  25  illustrated in  FIG. 2 . 
         [0043]    Referring to  FIG. 3 , the scaler  25  includes a scaling ratio generator  250  for determining the scaling ratio according to the scaling factors SCALEM and SCALEN, a pre-scaler  251  for selectively executing the pre-scaling under control of the scaling ratio generator  250  and the timing controller  21 , a post-scaler  252  for selectively executing the post-scaling with respect to the pre-scaled image and the non-pre-scaled image, and an output data synchronizer  253  for synchronizing the scaled image from the post-scaler  252  with the output clock of the image sensor. 
         [0044]    An operation of the scaler  25  will be described in detail below. 
         [0045]    The scaling ratio generator  250  calculates the scaling ratio using the scaling factors SCALEM and SCALEN. The scaling ratio is expressed as 
         [0000]      Scaling ratio=SCALEM/SCALEN  (1) 
         [0046]    Also, the scaling ratio generator  250  determines a pre-scaler valid signal and a pre-scaling ratio according to the scaling ratio. The pre-scaler valid signal determines on/off operation of the pre-scaler  251 . 
         [0047]    Only when the pre-scaler valid signal is generated, the pre-scaler  251  generates pre-scaler row/column addresses according to the pre-scaling ratio calculated by the scaling ratio generator  250 . Also, the pre-scaler  251  generates an image of an appropriate size by sampling only data located at positions matched with the generated addresses. 
         [0048]    The post-scaler  252  adjusts a final image size of the image scaler  25 . When not passing through the pre-scaler  251 , the scaling ratio generated from the scaling ratio generator  250  becomes the post-scaling ratio and thus the size of the final image is adjusted according to the scaling ratio. On the contrary, when passing through the pre-scaler  251 , the post-scaling ratio of the post-scaler  252  is given by 
         [0000]      Post scaling ratio=[(SCALEM/SCALEN)/Scaling ratio]  (2) 
         [0049]    When the pre-scaler  251  is off, the post-scaler  252  receives the row/column addresses from the timing controller  21  to generate new row/column addresses according to the post-scaling ratio. On the contrary, when the pre-scaler  251  is on, the post-scaler  252  receives the row/column addresses from the pre-scaler  251  to generate new row/column addresses according to the post-scaling ratio. 
         [0050]    Since the output timing of the image sensor due to the post-scaler  252  is not constant, the output data synchronizer  253  receives image data of the post scaler  252  and then synchronizes the scaled image data with the output clock of the image sensor. 
         [0051]      FIG. 4  is a flowchart diagram illustrating an image scaling algorithm of the scaler of  FIG. 2 . 
         [0052]    Referring to  FIG. 4 , in the step S 901 , if scaling factors SCALEM and SCALEN for outputting an image with a desired size are transferred through the timing controller  21 , a scaling ratio is generated. Then, in step S 902 , it is determined whether to execute a pre-scaler according to the scaling ratio. 
         [0053]    In step S 903 , if it is determined that the pre-scaler is necessary to execute, a pre-scaling using the pre-scaler is performed to adjust the image size. Then, in step S 904 , it is determined whether the post-scaler is necessary to execute. In step S 905 , if the post-scaler is necessary to execute, a post-scaling is performed through the post-scaler to adjust the image size. If the post-scaler is unnecessary to execute, the image size obtained through the pre-scaling is finally outputted. 
         [0054]    On the contrary, if it is determined in step S 902  that the pre-scaling is not unnecessary to execute, the pre-scaling is bypassed and the image size obtained through the post-scaling in step S 905  is finally outputted. 
         [0055]    In step S 906 , the image data scaled through the pre-scaling and the post-scaling is synchronized with the output clock of the image sensor. That is, data timing synchronization process is performed. 
         [0056]      FIG. 5  is a block diagram of the scaling ratio generator  250  illustrated in  FIG. 3 . 
         [0057]    Referring to  FIG. 5 , the scaling ratio generator  250  includes a divider  250 - 1 , a plurality of comparators  250 - 2 A to  250 - 2 C, a selector  250 - 3 , a post-scaling ratio determiner  250 - 4 . The divider  250 - 1  outputs the scaling ratio given by dividing SCALEM by SCALEN using the scaling factor. The plurality of comparators  250 - 2 A to  250 - 2 C have different reference values ranging from 1/2 to 1/8 for comparing the scaling ratio with a preset scaling ratio. The selector  250 - 3  outputs the corresponding pre-scaling ratio among the outputs of the comparators  250 - 2 A to  250 - 2 C. The post-scaling ratio determiner  250 - 4  determines the post-scaling ratio using the pre-scaling valid signal (the output of the comparator  250 - 2 C having the scaling ratio reference value of 1/2) and the selected pre-scaling ratio. 
         [0058]    Although the post-scaler  250  having the scaling ratio of 1 to 1/8 has been described in the above embodiment, the present invention can also be applied to a greater or smaller scaling ratio. 
         [0059]    An operation of the post-scaler  250  will be described below in detail. 
         [0060]    The divider  250 - 1  calculates the scaling ratio by dividing the scaler factor SCALEM by the scaler factor SCALEN. The scaling ratio outputted from the divider  250 - 1  is inputted to negative (−) terminals of the comparators  250 - 2 A to  250 - 2 C having the reference values 1/2, 1/4, and 1/8, respectively. 
         [0061]    When the scaling ratio is greater than 1/2, the outputs of all the comparators  250 - 2 A to  250 - 2 C are a logic low and the scaler valid signal is also a logic low. Consequently, the pre-scaler  251  is turned off. At this point, the scaling ratio becomes SCALEM/SCALEN. 
         [0062]    When the scaling ratio is less than or equal to 1/2 and greater than 1/4, the output of only the 1/2 comparator  250 - 2 C is a logic high. The pre-scaling ratio becomes 1/2. At this point, the post-scaling ratio becomes (SCALEM/SCALEN)/(1/2). 
         [0063]    When the scaling ratio is less than or equal to 1/4 and greater than 1/8, the outputs of only the 1/2 comparator  250 - 2 C and the 1/4 comparator  250 - 2 B are a logic high. The pre-scaling ratio becomes 1/4. At this point, the post-scaling ratio becomes (SCALEM/SCALEN)/(1/4). 
         [0064]    When the scaling ratio is greater than 1/2, the scaler valid signal is a logic low. When the scaling ratio is less than or equal to 1/2, the post-scaling ratio is a logic high. 
         [0065]      FIG. 6  is a block diagram of the pre-scaler  251  illustrated in  FIG. 3 . 
         [0066]    Referring to  FIG. 6 , the pre-scaler  251  includes a plurality of AND gates  251 - 1 A to  251 - 1 C, an address shift coefficient selector  251 - 2 , a pre-scaler address generator  251 - 3 , and a pre-scaler data sampler  251 - 4 . The AND gate  251 - 1 A has one terminal receiving the reference value of 1/8 and another terminal receiving the pre-scaling ratio, the AND gate  251 - 1 B has one terminal receiving the reference value of 1/4 and another terminal receiving the pre-scaling ratio, and the AND gate  251 - 1 C has one terminal receiving the reference value of 1/2 and another terminal receiving the pre-scaling ratio. The address shift coefficient selector  251 - 2  selects the shift coefficient of the corresponding address using the outputs of the AND gates  251 - 1 A to  251 - 1 C. The pre-scaler address generator  251 - 3  generates the pre-scaler row/column addresses by shifting the addresses from the timing controller  21  as much as the corresponding coefficient selected by the address shift coefficient selector  251 - 2 . The pre-scaler data sampler  251 - 4  samples the original image data and the data stored in the line memory  23  through the pre-scaler row/column addresses and outputs the pre-scaler image data. 
         [0067]    The pre-scaler  251  operates only when the scaler valid signal is a logic high, and shifts the row/column addresses provided from the timing controller  21  in each bit according to the pre-scaling ratio determined by the scaler ratio generator  250 . That is, a 1-bit shift is performed when the scaling ratio is 1/2, a 2-bit shift is performed when the scaling ratio is 1/4, and a 3-bit shift is performed when the scaling ratio is 1/8. Through this shift process, the pre-scaler row/column addresses are generated. 
         [0068]    Meanwhile, even in the same pre-scaling ratio, the pre-scaler row/column addresses are differently generated when the image scaler is performed in the full color data level and in the bayer data level. 
         [0069]    By outputting only data located at positions matched with the pre-scaler address position, which is newly constructed among the original image data through the pre-scaler data sampler  251 - 4 , the output data of the image sensor can be implemented to match with the pre-scaling ratio. 
         [0070]    In various manners, the output data of the pre-scaler  251  can be determined using the data of the previous line and the currently inputted data through the line memory  23  at the position where the address is matched. 
         [0071]    Accordingly, the image quality of the pre-scaler output image is determined by the method of determining the output data. 
         [0072]      FIG. 7  is a block diagram of the post-scaler  252  illustrated in  FIG. 3 . 
         [0073]    Referring to  FIG. 7 , the post-scaler  252  includes a post-scaler address generator  252 - 1 , transmission gates  252 - 3 A and  252 - 3 B, and a post-scaler data sampler  252 - 2 . The post-scaler address generator  252 - 1  receives the row/column addresses from the timing controller  21 , the pre-scaler row/column addresses, the pre-scaler valid signal, and the post-scaling ratio and generates the post-scaler row/column addresses. The transmission gate  252 - 3 A receives the pre-scaler valid signal and its inverted signal through gates of NMOS and PMOS transistors and outputs the pre-scaler image data. The transmission gate  252 - 3 B receives the pre-scaler valid signal and its inverted signal through gates of NMOS and PMOS transistors and outputs the original image data. The post-scaler data sampler  252 - 2  samples the original image data or the pre-scaler image data through the post-scaler row/column addresses and outputs the post-scaler image data. 
         [0074]    The post-scaler address generator  252 - 1  selects one of the pre-scaler row/column post-scaling ratio and the row/column address of the entire size of the image sensor, which is generated by the timing controller  21  by using the post-scaling ratio and the pre-scaling valid signal in Eqs. (1) and (2), and then generates the post-scaler row/column addresses. At this point, like in the pre-scaler  251 , the post-scaler row/column addresses are differently generated when the image scaler is performed in the full color data level and in the bayer data level. 
         [0075]    Also, like the pre-scaler data sampler  251 - 3 , the post-scaler address generator  252 - 2  selects one of the original image data and the pre-scaler image data according to the pre-scaler valid signal and outputs data at the position matched with the new post-scaler address. The image quality of the post-scaler output image is determined by the method of outputting the output data. 
         [0076]      FIG. 8A  illustrates the output of the pre-scaler in the full color data level when the pre-scaling ratio is 1/4, and  FIG. 8B  illustrates the output of the pre-scaler in the bayer data level when the pre-scaling ratio is 1/4. 
         [0077]    Specifically,  FIGS. 8A and 8B  illustrate a case where the pre-scaling ratio is 1/4 with respect to a 16×16 pixel array. Even though the pre-scaling ratios are equal to 1/4, the pre-scaler row/column address is ( 1 , 5 , 9 , 13 ) in the full color data level and ( 1 , 2 , 9 , 10 ) in the bayer level, whereby the pre-scaler addresses are differently implemented. 
         [0078]    Consequently, the data of the positions matched with the row/column addresses are outputted as the output data of the pre-scaler  251 . 
         [0079]      FIG. 9A  illustrates an output of the post-scaler in a full color data level when the post-scaling ratio is 5/7 with respect to a post 14×14 pixel array, and  FIG. 9B  illustrates an output of the post-scaler in a bayer data level when the post-scaling ratio is 5/7 with respect to a post 14×14 pixel array. 
         [0080]    Even though the post-scaling ratios are equal to 5/7, the row/column addresses is ( 1 , 2 , 3 , 5 , 6 , 8 , 9 , 10 , 12 , 13 ) in the full color data level and ( 1 , 2 , 3 , 4 , 5 , 6 , 9 , 10 , 11 , 12 ) in the bayer data level, whereby the post-scaler addresses are differently implemented. 
         [0081]    When the post-scaling ratio is greater than 1/2, it does not pass through the pre-scaler. When the scaling ratio is less than 1/2, it passes through the pre-scaler and is newly constructed like Eqs. (1) and (2). Therefore, the post-scaling ratio is always in a range from 1 to 1/2. 
         [0082]    For example, when the scaling ratio is 3/7, the pre-scaling ratio becomes 1/2 and the post-scaling ratio becomes 6/7 by Eq. (2). When the scaling ratio is 6/7, the post-scaling ratio becomes 6/7 by Eq. (1). 
         [0083]    Therefore, when the scaling ratio is 3/7 and 6/7, the post-scaling ratio becomes 6/7 in both cases. 
         [0084]    Like this, since the scaler method of the present invention can share the same post-scaling ratio, the post-scaler can be implemented in the same configuration, thereby reducing the complexity of hardware. 
         [0085]    The output data synchronizer  253  acts as a first input first out (FIFO) that synchronizes the image scaler output data with a random period, which is outputted from through the post-scaler, with the output clock of the image sensor and then outputs the data at a constant period. The output data synchronizer  253  is configured with a plurality of line memories. Also, the output data synchronizer  253  constantly matches the intervals of the respective lines, as well as the constant period of the output data of the image sensor. 
         [0086]      FIG. 10  is a flowchart diagram illustrating an algorithm of generating row/column addresses for the image scaling. 
         [0087]    Referring to  FIG. 10 , in step S 101 , it is determined whether an image scaler is executed or not. If the image scaling is unnecessary, the row/column addresses are unnecessary to generate. Therefore, the row/column addresses from the timing controller are outputted without change. 
         [0088]    In this case, the size of the output image from the pixel array is identical to that of the output image from the image sensor. 
         [0089]    On the contrary, in step S 102 , if the image scaling is necessary, it is determined whether the scaling is executed in a full color RGB data level or a bayer mosaic pattern data level. The scaling in the full color RGB data level is referred to as a full color scaling (FCS), and the scaling in the bayer mosaic pattern data level is referred to as a bayer mosaic scaling (BMS). 
         [0090]    Unlike the full color data, the bayer data has one color information per pixel in B/Gb or R/Cr line. Therefore, an address of the B/Gb or R/Gr pixel has to be generated at the same time. Thereafter, when the pre-scaling is executed according to the scaling ratio, the row/column addresses for the pre-scaling are generated and used in the pre-scaler. Also, when the post-scaling is executed, the row/column addresses for the post-scaling are generated and used in the post-scaler. 
         [0091]    When the FCS or BMS is selected in step S 102 , the row/column addresses for the pre-scaling and the post-scaling are generated through steps S 103  to S 109 . 
         [0092]    In accordance with the present invention, arbitrary scaling factors (SCALEM, SCALEN) are received and the scaling ratio (=SCALEM/SCALEN) is determined through the scaling ratio generator. Then, the row/column addresses of the entire size of the image generated by the timing controller are reconfigured using the row/column addresses corresponding to the scaling ratio. Consequently, only data located at positions matched with the row/column addresses newly generated are outputted. 
         [0093]    The image size can be arbitrarily adjusted through the pre-scaler and the post-scaler. When the scaling ratio is greater than 1/2, the pre-scaler is off and the image size is adjusted only by the post-scaler. 
         [0094]    Since the size of the output image of the image sensor can be arbitrarily changed according to the scaling ratio, the image size can be adjusted according to the requirement of an image displaying system such as the digital camera or mobile phone. 
         [0095]    Typically, in case that a scaling ratio is small, a whole image size should be converted to a very small size. Thus, damage in an image is generated. However, in case that the scaling ratio is small, a pre-scaler serves a role in controlling an image size to a medium size of the scaling ratio to reduce the damage in the image. 
         [0096]    Therefore, it is possible to satisfy the technical requirements of the high image quality/high resolution of the capture image and the small-sized image display. Thus, it is easy to adjust the image size regardless of the size of the original image in the image sensor. 
         [0097]    Also, the hardware of the scaler can be simplified by separately installing the pre-scaler and the post-scaler depending on the scaling ratio, thereby increasing the degree of integration. 
         [0098]    Although the CMOS image sensor has been taken as an example, the present invention can also be applied to various kinds of image sensors. 
         [0099]    The present application contains subject matter related to the Korean patent application No. KR 2005-0015506, filed in the Korean Patent Office on Feb. 24, 2005, the entire contents of which being incorporated herein by reference. 
         [0100]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.