Abstract:
A 3-dimensional computer graphics rendering system receives object data for a scene to be rendered. This includes vertex data and index data. The scene is subdivided into priority of rectangular areas ( 202 ). Object  8  of each rectangular area in the scene is assembled ( 203 ) and subsequently compressed ( 207 ). This data can subsequently be retrieved and decompressed and used for producing a properly shaded and texted image for display.

Description:
BACKGROUND TO THE INVENTION 
   This invention relates to a 3-dimensional computer graphics rendering system and in particular to a system of the type in which a scene to be rendered is subdivided into a plurality of rectangular areas or tiles, each of which is processed in turn for all the objects which intersect it. 
     FIG. 1  shows a prior art 3-D rendering system. 
   The system takes a three-dimensional description of a scene  100  and generates a two-dimensional representation of the scene  105  that can be displayed on an output device such as a computer monitor. 
   For the purposes of efficient operation, the system subdivides the two dimensional representation of the scene into regions referred to as tiles. 
   The objects in the three-dimensional scene are processed by a Tile Accelerator  101  and data defining then is stored in a display list  102 . The display list contains all the vertex and control data required to render the scene. The vertex data is typically stored as vertex strips. 
   For each tile comprising the scene space, an Image Synthesis Processor (ISP)  103  reads the display list corresponding to that tile and determines which parts of scene are visible. This information is then passed on to a Texturing and Shading processor (TSP)  104  to be rendered. 
   A further refinement is to group regions of tiles together into macrotiles. Instead of generating a display list for the entire scene, the tile accelerator generates a display list for each macrotile. This has the advantage that if all the display list memory has been consumed, then a macrotile can be rendered and the display list memory associated with it reclaimed for use by the system. The disadvantage is that when objects in the scene span multiple macrotiles they may have vertex data replicated in each macrotile display list. 
   The majority of non-tiled 3D graphics systems have an immediate mode rendering architecture. Immediate mode rendering does not need to store a description of the entire scene in the display list, and instead primitives are rendered as they are presented to the system. Immediate mode rendering has the advantage of avoiding the storage requirements of the display list, but it precludes the considerable optimisations that are possible with tiled architectures, such as deferred texturing and translucency sorting. 
   The complexity of scenes to be rendered is increasing as powerful, low-cost rendering systems become more prevalent. This presents a problem for tiled renderers because the display list storage and bandwidth requirements also increase. 
   SUMMARY OF THE INVENTION 
   Embodiments of the present invention provide a method and apparatus for reducing the size and memory bandwidth required for the display list, which will allow tiled rendering systems to be implemented at lower cost. 
   Specific embodiments of the invention collect blocks of screen space vertex data in the Tile Accelerator and reduce the amount of storage and bandwidth required to store the data by exploiting the spatial relationships between them. This is done determining a set of origin values and storing the attributes of the vertices as delta (or difference) values relative to the origin values. 
   Preferred embodiments also use a scheme for compactly describing indexed primitives in the display list that improves the number of times a vertex can be reused in a scene over traditional methods, such as strips, while preserving locality of reference. 
   The invention is defined in its various aspects with more precision in the appended claims to which reference should now be made. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Specific embodiments of the invention will now be described in detail by way of example with reference to the accompanying drawings in which: 
       FIG. 1  is the prior art rendering system described above; 
       FIG. 2  is a block diagram of a tile accelerator embodying the invention; 
       FIG. 3  shows the input data organisation inside the embodiment of  FIG. 3 ; 
       FIG. 4  shows a flow diagram of the processing of indices by tiling in an embodiment of the invention; 
       FIG. 5  shows a structure of vertex buffer organisation within the tile accelerator of  FIG. 2 ; 
       FIG. 6  shows schematically the organisation of the display list in the embodiment of the invention; 
       FIG. 7  is a flow diagram showing how attributes are compressed; 
       FIG. 8  is a more detailed diagram of vertex organisation; and 
       FIG. 9  shows a flow diagram for the retrieval and decompression of vertex data. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 2  illustrates the processing stages and data flow of a tile accelerator with vertex data compression in an embodiment of the invention. 
   Input data  100  contains a description of scene to be rendered. This includes the vertices that define the scene, a description or how vertices should be assembled into primitive objects such as lines and triangles, and state information describing the manner in which they should be rendered. The state information includes information about how to rasterise, texture and shade the primitive objects. In the embodiment, the state information includes the state specified by OpenGL and Direct X both of which are industry standard application programming interfaces 
   The Tile Accelerator  101  reads and processes vertices according to a list of rendering commands in the input data. 
     FIG. 3  shows a possible configuration of the input data. The rendering commands  300  indicate that two triangles are to be drawn and the state information defines how they are to be rendered. In this configuration, the application derives two triplets of indices  301  and  302  each of which describes which of the vertices  303  comprises its respective triangle. 
   Other configurations for describing how primitives should be assembled from a list of vertices, such as lists of indices describing triangle strips or fans are also possible. The description of other types of primitives, such as quads and lines is also possible by using fewer or additional index values. In some configurations, the list of indices may be implied and generated internally by the system. 
   It can be seen that the use of indices permits individual vertices to be referenced by a greater number of primitives in the scene than would otherwise be possible with strips. As will be shown below, the system allows indices to be stored compactly in the display list. In the preferred embodiment, sets of indices are used throughout the system to describe how primitives are formed. 
   As instructed by the rendering commands, in  FIG. 2  the system reads vertices and passes them to a transform processor  200  for conversion into clip space coordinates. This can be implemented as a fixed function transformation and lighting logic or as a programmable logic taking a sequence of operations that are the applied to the vertices. In the embodiment, the transformation process is programmable and includes vertex blending and the tessellation of high order surfaces into primitive objects. In some situations, the input data supplied to the rendering system may already be in screen space and so no transformation needs to be applied to the data. In some implementations, transformation may always be performed prior to the vertex data being supplied to the rendering system and the transform function may not be required at all. 
   Clipping and culling  201  takes transformed vertices and index information and performs clipping against front, rear or arbitrary clip planes and culling of primitives based on whether they are front or rear facing. In the embodiment, the final transformation of vertices to screen space is performed here. 
   Tiling Unit  202  receives indices and vertices from the clipping and culling process. The transformed and clipped vertices are placed into a vertex buffer  203  and the indices placed in an index buffer  204 . The tiling process then uses the indices to fetch the corresponding vertices&#39; screen coordinates from the buffer and determines which tiles the data contained in the buffer effects. 
   In the embodiment, the vertex buffer can store up to 16 vertices and the index buffer up to 96 indices. When these buffers are full, the contents of the vertex buffer are sent to the compression process  207  and the indices sent to the control portion  205  of the display list.  FIG. 4  shows the process used to add vertices and indices into these buffers. 
   The process of  FIG. 4  receives new indices for the next primitive at  500  and at  501  determines whether or not the new indices will fit into the index buffer. If they will not, the contents of the index buffer are flushed to the display list and the contents of the vertex buffer to the compression unit  207  at step  502 . The process then passes to step  503  which can also be reached directly from step  501  if the new indices do fit into the index buffer. At this stage the new indices are compared with the contents of the index buffer and a determination made as to which vertices referred to by the new indices are currently not present in the vertex buffer. After this a determination is made at  504  as to whether the new vertices determined at  503  will fit into the vertex buffer. If they will not the contents of the index buffer are flushed to the display list and the contents of the vertex buffer to the compression unit  207  at step  505 . The process then passes to step  506 , which is also passed to from step  504  if the new vertices do fit into the vertex buffer, and the new indices are then added to the index buffer. The process is completed at step  507  where the new vertices are fetched and added to the vertex buffer. 
   Each vertex in the vertex buffer can have a number of attributes associated with it. In the preferred embodiment, each vertex has 45 IEEE floating point format attribute values consisting of four position attributes (X, Y, Z, W), two groups of colour attributes (R, G, B, A) referred to as base and offset colours, eight groups of texture coordinates (U, V, S, T) and a fog value.  FIG. 5  illustrates the organisation of the vertex buffer. 
   The vertex position  400  indicates the screen space coordinates of the vertex. This data is required to rasterise the scene and determine the visibility of objects. The remaining data, including the base and offset colours  401 , texture coordinates  402  and fog value  403  are used during texturing and shading. 
   Note that the system can be configured so that Z represents the distance from the eye to the point represented by the vertex or so that Z is the distance from the front plane. 
   During the tiling process, it is possible for primitives to be culled because they are entirely off screen or do not cover any of the points where pixels are to be sampled. After culling primitives, the tiling process examines the indices of the remaining primitives and determines which vertices are still referenced. This information is forwarded to the compression process in the form of a mask. Note that if macrotiling is used, this information can be passed to the compression module on a per macrotile basis for each macrotile that the contents of the vertex buffer effects. 
   When the limit of the number of vertices that can be stored in the vertex buffer or the number of indices that can be buffered in tiling is or the last vertex of a primitive, or the end of the scene is reached, the contents of the vertex buffer are flushed and sent to the compression process and the indices describing the primitives are written into the control portion of the display list  205 . 
   The state information is placed in the control portion of the display list by the tiling process. In the preferred embodiment, state information in the input data to the system is tagged with a tag between 1 and 63. The tiling process records the current tag and the tag of the last state written into each tile. When it is determined that a primitive effects a particular tile, the last tag written into that tile is compared against the current tag. If the numbers do not match, the state information is inserted into the control data of that tile and the record of the last tag for that tile is updated. At the beginning of each frame or after 63 tags have been submitted to the system, the record of the last tag written to each tile is cleared to zero. 
     FIG. 6  illustrates the organisation of the display list. Each tile in the display list has its own steam or control data. A region array  706  holds a pointer to the start of the control data for each tile. 
   The part of the display list containing control and vertex data is divided into memory blocks  700  which are typically memory page sized. During the tiling process, the per-tile control data  706  are written into ascending addresses in memory blocks and blocks of vertex data  703  are written into descending memory addresses. When all space in a memory block has been used, a new memory block is allocated. In this manner, locality of reference is improved because vertex data can be stored in the same memory block as the control data that refers to it. 
   During the tiling process, a memory array is used to record the location in the display list of the memory blocks where control data for each tile should be appended. If macrotiling, there is one memory block being filled per macrotile. 
   The control data includes state information  701 , vertex block pointers  702 , indices  704  and stream pointers  705 . 
   In the embodiment, state information that is only required by the ISP is stored directly in the control data. State information that is required by the TSP is written once into the display list and a reference to it is placed in the control data. 
   To reduce the amount of display list storage required for TSP state information it is split into three portions: object state that is shared across a large number of objects, texture state that typically changes frequently, and blending state that is typically large but shared across many objects. In this manner, the texture state can change frequency without it being necessary to replicate the large blending state each time. 
   Vertex block pointers identify the block of vertex data that will be subsequently used to draw primitives. In the preferred embodiment this includes a description of the type of primitives to be drawn from the buffer. This includes lines, points, filled triangles and outline triangles. 
   To reduce the amount of display list storage, indices written into the control data are mapped by means of an associative memory into a range between zero and the number of vertices stored in the vertex buffer. In the, embodiment, the indices written into the control data are 4-bit values. 
   The control data for a tile is written into memory blocks in sequential memory addresses. Each memory block may contain control data for multiple tiles, and the control data for a tile may span multiple memory blocks. At the end of each sequence of control data, the tiling process inserts a stream pointer either to identify the address in the display list where the control data continues or to indicate the end of the control data for a tile. 
   Compression unit  207  in  FIG. 2  examines the attributes of the vertices stored in the vertex buffer and attempts to exploit the spatial relationships between them to reduce their storage and memory bandwidth requirements. In the embodiment, blocks of attributes are compressed by storing them as delta or difference values relative to an origin value. The origin value and the delta values for all vertices in the block are stored in the vertex data in the display list. 
     FIG. 7  illustrates the process of compressing vertex attributes. The process is performed for each attribute for each vertex that is to be compressed. The result is that each set of attributes is either written out in compressed format as a set of delta values and an origin value or in raw “uncompressed” format as a set of 32-bit IEEE floating point values (for all attributes expect R, G, B and A attributes) and 8-bit integers (for R, G, B and A attributes). Note that the tile accelerator can be configured to process only a subset of possible attributes. Also, in the embodiment fog values are not compressed, however they could be processed in a similar manner as for the other attributes. 
   At  600 , a set of attributes is received from the vertex buffer along with a set of mask bits from tiling, indicating which of the attributes should be processed. 
   At  601 , attributes that do not have the corresponding mask bit are discarded from further processing. In some implementations of the system, the mask is not used and all attributes are always processed. 
   At  602  the attribute values are reduced to some amount of fractional accuracy, which is referred to as snapping. The amount of precision retained depends on the attribute type and on how the compression process has been configured. For the embodiment, Table 1 shows the attributes that are truncated and the number of fractional or mantissa bits preserved. 
   
     
       
             
             
             
             
           
         
             
                 
               TABLE 1 
             
             
                 
                 
             
           
           
             
                 
               Position 
               X, Y 
                4 fractional bits 
             
             
                 
                 
               Z 
               24 mantissa bits 
             
             
                 
                 
               W 
               20 mantissa bits 
             
             
                 
               Texture Coordinate 
               U, V, S 
                8-23 fractional bits 
             
             
                 
                 
               T 
               20 mantissa bits 
             
             
                 
                 
             
           
        
       
     
   
   The number of fractional bits preserved for X, Y can be relatively small because the position in screen space is typically sampled at integer coordinates and because of inaccuracies introduces during transformation. Sufficient Z accuracy must be maintained for Z artefacts not to occur. 
   Note that for texture coordinates, the number of fractional bits preserved is configurable. The compressor is typically configured to preserve log2(dim)+8 fractional bits, where dim is the maximum dimension in texels of texture maps associated with that attribute and log2 is the logarithm in base 2. The number of fractional bits preserved can be reduced to improve the compression ratio at the expense of accuracy. 
   In the embodiment, floating point colour values between 0 and 1.0 are converted to unsigned 8-bit integer values multiplying by 255 or by multiplying by 250 and clamping. 
   The compression process can be configured to disable the compression of particular attributes. This forces the attribute to be stored in raw format and no snapping is performed. 
   At  603  the minimum and maximum values of the set of snapped attributes is determined. 
   At  604  the minimum value is selected as an origin value. 
   Texture maps are frequently sampled so that only the fractional part and sometimes the odd/even value of the texture coordinate is significant. For texture coordinates that are used in this manner, the compression process can be configured to discard the most significant bits of the origin values, equivalent to adding or subtracting a multiple of 1 or 2, and thus move it closer to zero. Reducing the magnitude of the texture coordinate origin values in this manner can reduce the amount of storage required for the texture coordinate origins. 
   If macrotiling is being performed, the X and Y attributes can have the macrotile corner closest to the origin of the macrotile subtracted from them. 
   Some attributes may have restrictions on the magnitude of the origin values that can be represented in the compressed format. In the preferred embodiment, texture coordinate origin values are restricted to values between −2 16  and +2 16  and Z, W and T origin values are restricted to being positive. 
   At  605  the compression process determines if the origin value can be represented. If the texture coordinate origin value is outside the range that can be represented, the attributes are not compressed and the “raw” 32-bit IEEE format float value of the attributes are stored in the display list at  611 . 
   To simplify the encoding and decoding of the compressed memory format, the decision to store an attribute in raw format can force related attributes to also be stored in raw format. For example, if the compression process decides to store any of X, Y or Z in raw format, then all attributes in the set could be stored in raw format. Similarly, for each group of texture coordinates, if any of U, V, S or T is stored in raw format, then all texture coordinate attributes for that group could be stored in raw format. 
   Note that if a set of attributes is stored in raw format, the origin value is not used. 
   At  606  the maximum delta or difference value of each attribute is calculated by subtracting the minimum value from the maximum. 
   At  607  the magnitude of the maximum delta value for each attribute is examined and it is determined whether the delta value exceeds the maximum value that can be represented in compressed form. 
   In the preferred embodiment, the compressed format delta values for all X, Y, U, V and S attributes are stored as fixed-point delta values. Table 2 shows the magnitude at which deltas can no longer be represented in the compressed format. 
   
     
       
             
             
             
             
             
           
         
             
                 
               TABLE 2 
             
             
                 
                 
             
           
           
             
                 
               Position 
               X, Y 
               Fixed point 
                2 12   
             
             
                 
                 
               Z 
               Floating point 
               16 mantissa bits 
             
             
                 
                 
               W 
               Floating point 
               16 mantissa bits 
             
             
                 
               Colour 
               R, B 
               Integer 
                2 4  or 2 5   
             
             
                 
                 
               G 
               Integer 
                2 4  or 2 6   
             
             
                 
                 
               A 
               Integer 
                2 4  or 0 
             
             
                 
               Texture 
               U, V, S 
               Fixed point 
                8-23 fractional 
             
             
                 
               Coordinate 
                 
                 
               bits 
             
             
                 
                 
               T 
               Floating point 
               16 mantissa bits 
             
             
                 
                 
             
           
        
       
     
   
   The colour delta values R, G, B and A are integer quantities in the range 0 to 255. In the preferred embodiment, groups of colour delta values are stored in a single 16-bit block. If the A attributes are not all 255, the magnitude at which the R, G, B and A delta values can no longer be represented is 2 4 . If the A attributes are all 255, the values for R and B are 2 6  and 2 6  for B. 
   The Z, W and T attributes are stored as floating point values. The delta values are stored as a mantissa value relative to the exponent of the origin. The number of mantissa bits preserved in the delta values is the same as the number used when snapping. Note that as the origin is the minimum value, storing mantissa values relative to this exponent preserves all possible mantissa accuracy. 
   At  608  the magnitude of the maximum delta value is used to determine the size of the attribute deltas to be stored in the compressed format. In the preferred embodiment, the compressed format for all attributes in each set have the same delta size, which can be. 0, 8 or 16-bits for X, Y, Z, W, U, V, S and T and 16-bits for groups of colours. Note that this means that each vertex in a block has the same size. 
   At  609  the delta values for each attribute is calculated by subtracting the origin value from the value of each attribute. The number of bits preserved is as described previously. 
   At  610  the set of attributes are written into the display list in compressed format as a set of delta values and an origin value. 
   At  611  the set of attributes are written into the display list in raw format as a set of 32-bit IEEE float values. 
     FIG. 8  illustrates how the compression processes organises the vertex data for each vertex data block in display list memory. 
   The first part of the vertex data is the Vertex Format  700 . This describes some of the vertex data format. In the preferred embodiment this contains: a flag indicating whether the X, Y and Z attribute are stored in raw or compressed format; three fields indicating whether the compressed formats Delta X  704 , Delta Y  705  and Delta Z  706  are 8- or 16-bit delta values; three flags indicating whether the W Origin  707 , Base Colour Origin  708 , Offset Colour Origin  709  are present; a field indicating the number of Texture Coordinate Formats  710  present; a field indicating whether W Delta  715  values are 0, 8- or 16-bit delta or 32-bit raw values; two fields indicating whether Base Delta  716  and Offset Delta  717  are 0, 8- or 16-bit delta or 32-bit raw values; and a flag indicating whether Fog  719  values are present. 
   The second part of the vertex data  750  contains the position information for the vertices. 
   If the X, Y and Z attributes are stored in compressed format, the Vertex Format is followed by the X Origin  701 , Y Origin  702  and Z Origin  703  values as determined at  604 . Following the origin values the vertex data then contains the X Delta, Y Delta, and Z Delta values for all of the vertices in the block as determined at  609 . 
   If the X, Y and Z attributes are in raw format the X Origin, Y Origin and Z Origin values are not used and the Vertex Format is followed by the raw format X, Y and Z attribute values for all vertices in the block. In some implementations, X Origin, Y Origin and Z Origin may always be present. 
   The third part of the vertex data  751  contains data required for texturing and shading of the vertices. In some implementations this may not be present if the vertices do not require texturing or shading. 
   The W Origin  707 , Base Colour Origin  708 , Offset Colour Origin  709  contain the origin values for W and the R, G, B and A origin values for Base Colour and Offset Colour as determined at  604 . These origin values are only present if the corresponding flags in the Vertex Format are set. 
   Zero or more Texture Coordinate Formats may be present. Each describes the format for a group of U, V, S and T attributes. In the preferred embodiment this contains: a flag indicating whether the U, V and S attributes for this group are stored in raw or compressed format; three fields indicating whether U Delta, V Delta and S Delta values for this group are 8- or 16-bit; two flags indicating whether the S and T attributes are present; two fields indicating whether S Delta and T Delta values are 8- or 16-bit. 
   Each Texture Coordinate Format is followed by U Origin  711 , V Origin  712 , S Origin  713  and T Origin  614  values as determines in  604 . In the preferred embodiment, The U Origin, V Origin and S Origin values are stored as 16-bit floating point numbers with one sign bit, four exponent bits and 11 mantissa bits, and the T Origin is stored as a 32-bit IEEE format floating point number. 
   Following the Texture Coordinate Formats and U Origin, V Origin, S Origin and T Origin data, is the per-vertex data for the remaining attributes. This includes: W Delta  715 , Base Colour Delta  716 , Offset Colour Delta  717 , Fog  718 , and for each group of texture coordinate attributes present U Delta  719 , V Delta  720 , S Delta  721  and T Delta  722 . In some implementations, these values are only present if the corresponding bits in the Vertex Format or Layer Format are set. 
   Vertex position data is decompressed as the ISP fetches the per-tile control data from the display list.  FIG. 9  illustrates the process performed for each tile in the scene. To commence fetching the control stream, a control stream data pointer is initialised to the start of the control stream data from an address stored in a Region Array. At  900  the item pointed to by the control stream pointer is read and the pointer incremented to point to the next item. At  901  the item read is examined to determine if the end of the control stream has been reached. If it has, the ISP data fetch for this tile is complete and either the next tile in the scene should be processed or the scene render is complete. If the end of the stream has not been reached, then at  902  the item is examined to determine whether it is a stream pointer. If it is, then at  903  the control stream data pointer is updated to the address indicated and control is returned to step  901 . If the item is not a stream pointer it is examined at  904  to determine whether it is sate. If it is state, the state data is recorded at  905  and control is returned to step  901 . If the item is not state, it is examined at  906  to determine if it is a Vertex Block Pointer. If it is then the origin data is read from the vertex block at  907  and control is returned to step  901 . If the item is not a Vertex Block Pointer then the item must be indices. In this case, the delta values corresponding to the indices are fetched from the vertex block. The attributes of the vertex are reconstructed by adding the delta values to the origin values. 
   Note that the data required to decompress a vertex consists of the origin values and the delta values for that vertex. In this way, a single vertex can be fetched without having to fetch the data form all the other vertices in the block. 
   In the embodiment, Z, W, and T origin values are restricted to being positive. In an alternative implementation of the compression process, the sign of the sets of Z, W and T attributes is recorded and the compression process is performed on the absolute values of the attributes as described about. For each of these attributes, if the compressed format is selected an additional bit containing the original attribute&#39;s sign is recorded along with each attribute delta value in the vertex data. Note that this allows compressed floating point values to maintain their sign. If the raw format is selected, the value written into the vertex data includes the original sign.