Abstract:
A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of, and claims priority from, U.S. application Ser. No. 13/365,505 filed on Feb. 3, 2012; which application is itself a division of Ser. No. 12/062,055, filed on Apr. 3, 2008; which is incorporated by reference in its entirety herein. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED-RESEARCH OR DEVELOPMENT 
     None. 
     INCORPORATION BY REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC 
     None. 
     FIELD OF THE INVENTION 
     The invention disclosed broadly relates to the field of integrated circuit packaging and more particularly relates to the field of cooling devices for integrated circuits 
     BACKGROUND OF THE INVENTION 
     Current module cooling solutions remove heat primarily from the back of a chip or chip stack, limiting the amount of heat which can be removed. Furthermore, it is difficult with conventional test fixturing to provide adequate cooling and interconnection to chips and chip stacks with fine pitch interconnects during electrical testing. 
     Therefore, there is a need for a cooling device and process for cooling chips and chip stacks that overcomes the shortcomings of the prior art. 
     SUMMARY OF THE INVENTION 
     Briefly, according to an embodiment of the invention a method includes using a prefabricated shape with a silicon carrier to form both liquid cooling and electrical interconnection for integrated circuits. 
     According to another embodiment of the present invention, a chip package with an integrated cooling structure includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; a first set of liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling. The cooling lid includes: a temporary seal attaching the cooling lid to the silicon carrier; and a second set of liquid microchannels aligned with the first set. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       To describe the foregoing and other exemplary purposes, aspects, and advantages, we use the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which: 
         FIG. 1  shows a cross-section of a silicon carrier with multiple chips and with integrated electrical interconnection and microchannel liquid cooling, according to an embodiment of the present invention; 
         FIG. 2  shows a silicon carrier with a chip and a chip stack and with integrated electrical interconnection and microchannel liquid cooling, according to an embodiment of the present invention; 
         FIG. 3  shows one example of a silicon-based test head for chip stack testing at chip level assembly, according to an embodiment of the present invention; 
         FIG. 4  shows an example of a silicon-based test head probe for chip stack testing at wafer level, according to an embodiment of the present invention; 
         FIG. 5  shows a silicon-based carrier providing cooling to both the top and bottom of a chip, according to an embodiment of the present invention; 
         FIG. 6  shows an example of a silicon-based carrier on a segmented platform, according to an embodiment of the present invention; 
         FIG. 7  shows another example of a silicon-based test head for chip stack testing at chip level assembly, according to an embodiment of the present invention; and 
         FIG. 8  shows a flow chart of a method for producing a silicon-based chip package, according to an embodiment of the present invention. 
     
    
    
     While the invention as claimed can be modified into alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the present invention. 
     DETAILED DESCRIPTION 
     We describe an integrated silicon (Si) carrier that provides both microchannel cooling and electrical interconnections for integrated circuits. The silicon carrier includes electrical through vias, electrical wiring and an interconnection to chips made by means of metallic conductors such as solder and/or copper. The interconnections provide both electrical and thermal transport. 
     Additional thermal transport may be added, if required, by means of alternate or additional thermal paths off the chip or chip stack. The carrier can function as a permanent package to support chips and/or chip stacks as well as provide means for testing for known good chips where the silicon base acts to provide power and cooling. 
     A method according to an embodiment of the invention provides a way to remove heat effectively from a silicon carrier, which when used with small, high-conductivity balls or interconnects in the range of size from about 2.0 to 20 microns in diameter (for very high density interconnections) to about 50 to 100 microns in diameter (for lower density interconnections) as described herein provides an effective way to remove heat from the front as well as from the back of a chip or chip stack. This is useful both for chip testing and for chip operation in a final application. 
     The interconnections between the silicon carrier and the chips or chip stacks may have one or more size pads, or interconnections, such that small size interconnections may provide a means for electrical interconnections of signals, power and grounds (as well as enhance thermal conduction) and there may be other pads or large area interconnections which serve as an alternate means for heat transfer and may also be used for electrical interconnection. This method for fabricating the integrated carrier simplifies the methodology for assembly, test, and also reduces the hardware required in module assembly, as well as rework. 
     We describe a silicon package with electrical through silicon vias (TSV) and liquid cooling for one or more chips mounted on the surface and also for many layers of chips stacked with cooling only on periodic layers. The reason for this is that the use of liquid generally increases the thickness of the silicon layer and thus increases the electrical link path in that layer and this is not desirable for a high density stack of chip with high bandwidth interconnections. 
     Referring now in specific detail to the drawings, and particularly  FIG. 1 , there is illustrated an integrated circuit package according to an embodiment of the present invention.  FIG. 1  is a simplified schematic of the structure of a silicon-based package. Shown is a cross-section of a package  100  that provides electrical interconnection for power (voltage and ground to the silicon chip) and for signals to the chips  1  and  2 , between chips  1  and  2  on the silicon carrier  120 , and off the silicon carrier  120  and provides for liquid cooling of one or more chips  1  and  2  on the silicon carrier  120 . Note that for purposes of this disclosure, we use the term “chip” to encompass a single chip, chip stack, wafer, or stack of wafers. 
     The liquid cooling channels  108  (shown as a wave pattern) can be fabricated to permit liquid cooling across the silicon package  105 . In addition, through-silicon-vias (TSV)  110  are introduced which provide vertical electrical interconnections. Note the through-silicon-vias  110  may take advantage of electrical isolation from the silicon carrier  120  by means of a dielectric layer between the silicon and a conductor, such as Tungsten (W) or Copper (Cu). 
     The silicon carrier  120  may also provide electrical wiring for a high bandwidth interconnection between chips  1  and  2 , may provide integrated decoupling capacitors to support low inductance and close proximity capacitors to chips  1  and  2 , and may provide active and/or passive circuits for voltage regulation, power inversion and/or other functions. 
     The silicon package  105  uses small, heat conductive interconnects  112  such as balls preferably made from copper or solder between the chips and the carrier  120 . The balls  112  provide thermal as well as electrical transport. Additionally, balls  122  placed between the carrier  120  and the substrate  102  serve to further provide thermal and electrical transport. 
     The silicon carrier  120  may be mounted on another substrate  102  for improved mechanical integrity as well as providing a means for integration into a module, onto a board or socket by use of a ball grid array (BGA)  140 , column grid array (CGA) or land grid array (LGA) interconnection. Cooling of the chips  1  and  2  may be done by means of heat removal from the back of the chips  1  and  2 , by means of liquid cooling for heat removal from the silicon carrier, or by a combination of both. 
     Interconnections for liquid to remove heat from the silicon carrier  120  may be achieved by means of a connector, cap or lid (shown in  FIG. 3 ) disposed over the chips  1  and  2  which connects by means of an adhesive (such as epoxy-based or silicon-based adhesive) or other means to channels, holes and or other liquid conduits created in the silicon carrier  120 . A thermal enhancement material such as a thermal interface material (TIM), thermally conductive gel, solder or alternate thermal enhancement structure and method may be used to transfer heat from the chips  1  and  2  to the lid, cap or module, and/or between chips and the silicon package. 
     The TSV  110  and liquid channels  108  in the silicon carrier  120  may be formed by means of deep reactive ion etching or other means known in the art. In addition, the silicon package  100  may provide a means for not only electrical and thermal cooling but may also provide a means for optical interconnections (not shown) on or off module by use of vertical and/or horizontal channels or holes or other optical conduits. 
       FIG. 2  shows a schematic cross-section of a silicon-based package  200  featuring integrated electrical and microchannel liquid cooling of stacked chips. The package of  FIG. 2  provides electrical interconnection for power (voltage and ground to the silicon chips) and for signals to the chips and/or chip stacks, between chips and/or chip stacks, and off the silicon substrate and provides for liquid cooling of one or more chips and/or chip stacks on the silicon substrate  102 . 
     Referring to  FIG. 3  there is shown a silicon-based test platform substrate with an integrated cooling structure. This provides socket testing for chip stacks or chip stacks on a module. Liquid cooling provides cooling during test by means of liquid flow through the lid  322  and silicon carrier  120 . Note the temporary seal between the lid  322  and the silicon package may be a rubber or polymer “O” ring to seal a liquid connection between the lid  322  and the silicon carrier  120 . An adhesive may be used from the silicon carrier  120  to the substrate  102  for improved mechanical integrity of the silicon package  105 . Power, ground, and signals for testing can be provided with active circuits in the silicon package  105  and/or by means of electrical interconnections through the supporting substrate and/or board interconnections. 
     Referring to  FIG. 4  there is shown a silicon test head probe that provides means for electrical test and cooling of wafers or wafer stacks with integrated liquid cooling in a silicon based package. 
     Referring to  FIG. 5  there is shown a silicon-based package  505  which can provide electrical and liquid cooling to one or more chips  1  and  2  (shown) from both sides of the chips  1  and  2 . The structure  505  can also provide electrical and liquid cooling to chips and/or chip stacks where liquid cooling may be critical in cooling chip stacks from the top and bottom of the chip stacks as well as power delivery and signal transmission may be critical from one or both top and bottom of the chip stacks. 
     Referring to  FIG. 6  there is shown a structure wherein a silicon-based package  605  provides a segmented platform to provide electrical power, voltage and signal transmission to one or more chip stacks  601  as well as liquid cooling for the chip stacks  601 . These units  605  may be stacked for power delivery, signal transmission and cooling within the stacked chips and package structures, as shown. In addition, but not shown, optical interconnections may also be provided by means of the silicon package  605 . 
     Referring to  FIG. 7  there is shown an example of a test head, probe or socket which can be utilized to test stacked chips  1  and  2 , along with silicon packages  705  which provide electrical power, signal transmission and cooling for the assemblies in stacked configurations. 
     Referring to  FIG. 8  there is shown a high-level flow chart  800  of a method for producing a coolant device according to an embodiment of the present invention. In step  810  the silicon carrier  120  is fabricated with through-silicon-vias  110  and microchannels  108  for liquid coolant. The through-silicon-vias  110  can accommodate electrical conduits or optical interconnects. The vias  110  run through the carrier to make contact with the chip  1 . 
     Next, in step  820  the substrate  102  is fabricated. Note the order of steps  810  and  820  can be switched. In step  840  we affix the substrate  102  to the silicon carrier  120  and affix chips to the silicon carrier. 
     In step  850 , once the chips are positioned, we place an additional coolant device above them. This coolant device may be a cap  322  or another carrier  520 . Note that the additional carrier  520  should also be pre-fabricated with through-silicon-vias  110  and microchannels  108  in order to further enhance cooling. Step  850  may be repeated with additional layers of carrier  520 , chip  1 , and additional carrier  520 . 
     In step  860  we place a ball array  140  between the substrate  102  and a printed circuit board or other surface. 
     While typically only about 5% of the heat from the chip travels from the chip through the C4&#39;s (controlled collapse chip connections) into the first level package, it is possible to greatly increase the amount of heat removed from the front of the chip by using smaller metal balls  112  with better thermal conductivity and by providing a way to remove heat from the first level package. For example, if there were a 25% coverage of copper balls 25 microns high between the chip and the first level package, the area normalized thermal resistance (Rth) would be
 
 Rth= 25×10−6  m /(0.25×390  W/m−K )=0.25  K−mm 2 /W  
 
     Even after adding the thermal resistance of the chip wiring/insulation layers, the thermal resistance could be less than or comparable to that for removing heat from the back of the chip. This invention describes a way to remove heat effectively from a silicon carrier, which when used with small, high-conductivity balls as described here, can provide a way to effectively remove heat from the front of the chip as well as from the back. This can be useful both for chip testing and for chip operation in a final application. 
     Therefore, while there has been described what is presently considered to be the preferred embodiment, it will understood by those skilled in the art that other modifications can be made within the spirit of the invention.