Abstract:
A driver circuit disclosed herein comprises a first inverter which comprises: a first transistor which is connected between a first power supply with a first voltage and a first output node; a second transistor which is connected between the first output node and a second power supply with a second voltage; and a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims benefit of priority under 35 U.S.C.§119 to Japanese Patent Application No. 2004-107086, filed on Mar. 31, 2004, the entire contents of which are incorporated by reference herein.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a driver circuit and a system including a driver circuit, and particularly relates to a driver circuit having a predriver in a stage previous to an output driver and a system including such a driver circuit.  
         [0004]     2. Background Art  
         [0005]      FIG. 1  is a diagram showing the configuration of a related driver circuit. As shown in  FIG. 1 , the driver circuit includes a predriver  10  and an output driver  12 .  
         [0006]     The predriver  10  is configured by connecting plural CMOS inverters  20  in series. The output driver  12  is a CML (Current Mode Logic) type output driver and includes N-type MOS transistors N 1 , N 2 , and N 3  and resistances R 1  and R 2 .  
         [0007]     A bias voltage BIAS is applied to the transistor N 3 , and hence the transistor N 3  functions as a constant current source.  
         [0008]      FIG. 2  is a diagram showing operation waveforms of the driver circuit shown in  FIG. 1 . As shown in  FIG. 2 , a node MAIN_P and a node MAIN_N which are output nodes of the predriver  10  oscillate, for example, between 0 V and a voltage VTERM.  
         [0009]     If threshold voltages of the transistors N 1  and N 2  are VTHN, the transistor N 1  remains off while the voltage of the node MAIN_N is between 0 V and the voltage VTHN when the node MAIN_N rises from low (0 V) to high (voltage VTERM). Accordingly, the voltage of an output terminal TX_P does not drop. Then, the voltage of the output terminal TX_P starts to drop only after the voltage of the node MAIN_N has reached VTHN.  
         [0010]     On the other hand, the node MAIN_P drops from high (voltage VTERM) to low (0 V), and when the voltage of the node MAIN_P drops from the voltage VTERM to the voltage VTHN, the transistor N 2  is turned off. Therefore, at this point, the voltage of an output terminal TX_N rises to high (voltage VTERM).  
         [0011]     As described above, on/off timings of the transistor N 1  and the transistor N 2  do not coincide, whereby a voltage waveform of the output terminal TX_P and a voltage waveform of the output terminal TX_N are not perfect differential waveforms. Therefore, as shown in  FIG. 2 , an intersection point (VCOMMON) of the voltage waveform of the output terminal TX_P and the voltage waveform of the output terminal TX_N when the output switches between high and low has a higher potential than an intermediate potential. Namely, {(voltage of output terminal TX_P)+(voltage of output terminal TX_N)}/2=VCOMMON is not a constant value.  
         [0012]     However, specifications needed for the driver circuit sometimes require that VCOMMON is constant (fluctuations are within a predetermined range), for example, as in the case of PCI-EXPRESS. In such specifications, it is necessary to avoid fluctuations in VCOMMON in the driver circuit as much as possible.  
       SUMMARY OF THE INVENTION  
       [0013]     In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a driver circuit, comprises a first inverter which comprises:  
         [0014]     a first transistor which is connected between a first power supply with a first voltage and a first output node;  
         [0015]     a second transistor which is connected between the first output node and a second power supply with a second voltage; and  
         [0016]     a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on.  
         [0017]     According to another aspect of the present invention, a system including a driver circuit comprises a first inverter which comprises:  
         [0018]     a first transistor which is connected between a first power supply with a first voltage and a first output node;  
         [0019]     a second transistor which is connected between the first output node and a second power supply with a second voltage; and  
         [0020]     a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]      FIG. 1  is a circuit diagram showing the configuration of a related driver circuit;  
         [0022]      FIG. 2  is a diagram showing operation waveforms of the driver circuit in  FIG. 1 ;  
         [0023]      FIG. 3  is a circuit diagram showing the configuration of one block in a predriver according to a first embodiment;  
         [0024]      FIG. 4  is a diagram showing operation waveforms of the predriver circuit in  FIG. 3 ;  
         [0025]      FIG. 5  is a diagram showing operation waveforms of a driver circuit which uses the predriver circuit in  FIG. 3 ;  
         [0026]      FIG. 6  is a circuit diagram showing the configuration of the driver circuit which uses the predriver according to the first embodiment;  
         [0027]      FIG. 7  is a diagram showing a modification of the driver circuit according to the first embodiment;  
         [0028]      FIG. 8  is a circuit diagram showing the configuration of a driver circuit according to a second embodiment;  
         [0029]      FIG. 9  is a diagram showing operation waveforms of the driver circuit in  FIG. 8 ;  
         [0030]      FIG. 10  is a diagram showing a modification of the driver circuit according to the second embodiment;  
         [0031]      FIG. 11  is a block diagram showing the configuration of a serial interface which uses the driver circuit of each of the embodiments;  
         [0032]      FIG. 12  is a block diagram showing the configuration of a motherboard which uses the serial interface in  FIG. 11 ;  
         [0033]      FIG. 13  is a block diagram showing the configuration of a graphic card which is inserted into an expansion slot of the motherboard in  FIG. 12 ;  
         [0034]      FIG. 14  is a diagram showing a modification of the graphic card in  FIG. 13 ; and  
         [0035]      FIG. 15  is a block diagram showing the configuration of a PC card which uses the driver circuit of each of the embodiments. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0036]     [First Embodiment] 
         [0037]      FIG. 3  is a diagram showing the configuration of a predriver  10  according to the first embodiment.  FIG. 3  shows the configuration of only either a MAIN_P side or a MAIN_N side. Namely, a circuit corresponding to two stage inverters is shown.  
         [0038]     As shown in  FIG. 3 , the predriver circuit  10  according to this embodiment includes P-type MOS transistors P 10  and P 11 , N-type MOS transistors N 12  to N 15 , a capacitor C 10 , and a resistance R 10 .  
         [0039]     More specifically, the transistor P 10  and the transistor N 12  which are connected in series between a power supply with a voltage VTERM and a ground GND constitute a CMOS inverter. A voltage signal inputted from a terminal SER_MAIN is inputted to a gate of the transistor P 10  and a gate of the transistor N 12 . An output of the CMOS inverter is outputted from a node SER_MAIN_B between the transistor P 10  and the transistor N 12 .  
         [0040]     Similarly, the transistor P 11  and the transistor N 13  which are connected in series between the power supply with the voltage VTERM and the ground GND constitute a CMOS inverter, and the node SER_MAIN_B is connected to a gate of the transistor P 11  and a gate of the transistor N 13 . An output of this CMOS inverter is outputted from a node MAIN between the transistor P 11  and the transistor N 13 . This node MAIN is connected to a gate of a transistor N 1  or a gate of a transistor N 2  in an output driver  12  in  FIG. 1 .  
         [0041]     A gate of the transistor N 14  connected between the transistor N 13  and the ground GND is connected to the node MAIN. Namely, the transistor  14  is diode-connected. Hence, when the node MAIN is low, the transistor N 14  is off, and when the node MAIN is high, the transistor N 14  is on.  
         [0042]     The capacitor C 10  and the transistor N 15  are connected in parallel between a node, which is between the transistor N 13  and the transistor N 14 , and the ground GND. A PRECHCAP signal is inputted to a gate of the transistor N 15 . This PRECHCAP signal is inputted from SER_MAIN_B of the other inverter which constitutes a complementary block.  
         [0043]     When the PRECHCAP signal is high, the transistor N 15  is on, and electric charge accumulated in the capacitor C 10  is discharged. On the other hand, when the PRECHCAP signal is low, the transistor N 15  is off, and electric charge is accumulated in the capacitor C 10 .  
         [0044]     One end of the resistance R 10  is connected to the power supply with the voltage VTERM, and the other end of the resistance R 10  is connected to the capacitor C 10 . Therefore, even when both the transistors N 14  and N 15  are off, an electric current flows into the capacitor C 10  from the power supply with the voltage VTERM through the resistance R 10 .  
         [0045]     As shown in  FIG. 4 , it is assumed that the voltage of the node SER_MAIN_B switches from low to high. In this case, the transistor P 11  is turned off, and the transistor N 13  is turned on. Consequently, the node MAIN goes low, and the transistor  14  is turned off. The timing in which the transistor N 14  is turned off is a point in time when the voltage of the node MAIN has dropped to a threshold voltage VTHN of the N-type transistor. Accordingly, the voltage of the node MAIN becomes constant at the voltage VTHN without dropping to 0 V. In other words, the voltage of the node MAIN is maintained in the vicinity of the threshold voltage of the transistor N 1  to which the node MAIN is connected.  
         [0046]     Hence, the timings of switching between “on” and “off” of the transistors N 1  and N 2  in the output driver  12  come to coincide, and as shown in  FIG. 5 , VCOMMON becomes constant. Namely, a voltage waveform of an output terminal TX_P and a voltage waveform of an output terminal TX_N can maintain differential waveforms, which can reduce fluctuations in the intermediate voltage VCOMMON to a minimum.  
         [0047]     Incidentally, in the diode-connected transistor N 14  in  FIG. 3 , the voltage change of the node MAIN is not as shown by a solid line but as shown by a broken line in  FIG. 4  due to transistor characteristics. Namely, as the voltage of the node MAIN drops, the speed at which the voltage drops decreases.  
         [0048]     Hence, in this embodiment, the capacitor C 10  is provided. Namely, while the voltage of the node MAIN is high, the transistor N 15  is on and electric charge in the capacitor C 10  is discharged. At a point in time when the node SER_MAIN_B is high, the transistor N 15  is turned off, and the capacitor C 10  is brought into a state capable of accumulating electric charge.  
         [0049]     Since electric charge is not accumulated in the capacitor C 10 , the voltage of the node MAIN is strongly pulled to ground and comes close to an ideal waveform such as shown by the solid line in  FIG. 4 . On this occasion, a voltage V of the node MAIN is determined in the following manner. Namely, the voltage V is fixed at a voltage calculated by V=(C×VTERM+C′×0)/(C+C′) where C is a capacitance of the capacitor C 10  and C′ is a stray capacitance of the node MAIN. In other words, the voltage is fixed at a value obtained through capacitively dividing the voltage of the voltage VTERM and the ground GND by the capacitance of the capacitor C 10  and the stray capacitance of the node MAIN. In this embodiment, the capacitively divided voltage V is set to be the threshold voltage VTHN of the N-type MOS transistor. Incidentally, the stray capacitance of the node MAIN is determined by the gate capacitance of the transistor N 1  or the transistor N 2  of the output driver  12 , wire capacitance, and so on.  
         [0050]     Moreover, even if the voltage of the node MAIN is constant at the threshold voltage VTHN, in reality, a subthreshold leakage current exists in the transistor N 14 . If this leakage current continues flowing, the voltage of the node MAIN gradually drops from the voltage VTHN. Hence, in this embodiment, an electric current is supplied from the power supply with the voltage VTERM via the resistance R 10 . Consequently, the voltage of the node MAIN is maintained at the voltage VTHN.  
         [0051]     As can be seen from the above, these transistor N 14 , transistor N 15 , capacitor C 10 , and resistance R 10  constitute a voltage maintaining circuit in this embodiment.  
         [0052]      FIG. 6  is a diagram showing the entire configuration of a driver circuit according to this embodiment. As shown in  FIG. 6 , the predriver  10  includes four inverters  12   a  to  12   d . The inverter  12   a  and the inverter  12   b  constitute one block, and the inverter  12   c  and the inverter  12   d  constitute the other block.  
         [0053]     As described above, an input signal of the node SER_MAIN_B of one block is inputted to the gate of the transistor N 15  of the other block. More specifically, an input signal of the inverter  12   b  is inputted to the gate of the transistor N 15  of the inverter  12   d , and an input signal of the inverter  12   d  is inputted to the gate of the transistor N 15  of the inverter  12   b . The input signal of the inverter  12   b  and the input signal of the inverter  12   d  are complementary signals, and one signal is obtained by inverting the other, and vice versa. Thereby, while the input signal of the node SER_MAIN_B is low, the transistor N 15  can be on, and electric charge can be discharged from the capacitor C 10 .  
         [0054]     As described above, according to the driver circuit of this embodiment, fluctuations in the intermediate voltage VCOMMON of the voltage waveform of the output terminal TX_P and the voltage waveform of the output terminal TX_N can be minimized. Consequently, the precision of the differential output of the driver circuit can be improved.  
         [0055]     Incidentally, as shown in  FIG. 7 , the diode-connected transistor N 14  can be replaced with a PN diode D 10 .  
         [0056]     [Second Embodiment] 
         [0057]     In the second embodiment, the aforementioned first embodiment is modified so that the output driver  12  is composed of P-type MOS transistors.  FIG. 8  is a diagram showing the configuration of a driver circuit according to this embodiment and corresponds to  FIG. 6  described above.  
         [0058]     As shown in  FIG. 8 , the predriver  10  in the driver circuit according to this embodiment includes P-type MOS transistors P 20  to P 23 , N-type MOS transistors N 24  and N 25 , a capacitor C 20 , and a resistance R 20 . The output driver  12  includes P-type MOS transistors P 30  to P 32  and resistances R 33  and R 34 .  
         [0059]     The basic role of each element is the same as that in the aforementioned first embodiment. Namely, the transistor P 21  is diode-connected and turned off at a point in time when the voltage of the node MAIN (MAIN_N, MAIN_P) becomes higher than a threshold voltage VTHP of the P-type MOS transistor. Therefore, the voltage of the node MAIN does not rise to the voltage VTERM when the node MAIN is high. In other words, the voltage of the node MAIN is maintained in the vicinity of the threshold voltage of the transistors P 30  and P 31  to which the node MAIN is connected. The capacitor C 20  operates such that the voltage of the node MAIN rises rapidly when the node MAIN switches from low to high. These transistor P 21 , transistor P 23 , capacitor C 20 , and resistance R 20  constitute a voltage maintaining circuit in this embodiment.  
         [0060]     When the node MAIN is low, the transistor P 23  is on and electric charge in the capacitor C 20  is discharged, and when the node MAIN goes high, the transistor N 23  is turned off, and the capacitor C 10  is brought into a state capable of accumulating electric charge. The resistance R 20  feeds an electric current which compensates for a leakage current flowing through the transistor P 21  from the power supply with the voltage VTERM to the ground.  
         [0061]      FIG. 9  is a diagram showing operation waveforms of the driver circuit in  FIG. 8 . As can be seen from  FIG. 9 , a voltage waveform of the node MAIN_P and a voltage waveform of the node MAIN_N do not rise to the voltage VTERM even at their high level. Therefore, the timings of switching between “on” and “off” of the transistor P 30  and the transistor P 31  come to coincide. Accordingly, even in timing of switching, the voltage waveform of the output terminal TX_P and the voltage waveform of the output terminal TX_N can keep complementary, whereby fluctuations in VCOMMON can be minimized.  
         [0062]     Incidentally, as shown in  FIG. 10 , the diode-connected transistor P 21  can be replaced with a PN diode D 20 .  
         [0063]     [Third Embodiment] 
         [0064]      FIG. 11  is a diagram showing the configuration of a serial interface to which the driver circuit of the aforementioned first embodiment or second embodiment is applied. As shown in  FIG. 11 , a 8-bit parallel signal is inputted to a parallel/serial converter  40 .  
         [0065]     In this parallel/serial converter  40 , conversion from a parallel signal to serial signal is performed, and a complementary serial signal is inputted to the predriver  10 . This serial signal is amplified to approximately between 10 mA and 15 mA in the predriver  10  and inputted to the output driver  12 . In the output driver  12 , the complementary signal is amplified to approximately 20 mA and outputted from this chip. The serial signal outputted from the output driver  12  is inputted to a printed board and transmitted via a transmission line  42 .  
         [0066]     S-ATA, USB, PCI-EXPRESS are examples of the above serial interface.  
         [0067]     [Fourth Embodiment] 
         [0068]      FIG. 12  is a block diagram partially showing the configuration of a motherboard  50  of a personal computer. This motherboard  50  is provided with a CPU  52 , an ASIC  54 , and an expansion slot  56 . In the ASIC  54 , the aforementioned driver circuit and parallel/serial converter are formed.  
         [0069]     Hence, data on a card inserted into the expansion slot  56  is transmitted to the ASIC  54  with a parallel signal, and the parallel signal is converted into a serial signal in the ASIC  54 , amplified, and inputted to the CPU  52 .  
         [0070]      FIG. 13  is a block diagram partially showing the configuration of a graphic card  60  inserted into the expansion slot  56 . This graphic card  60  is provided with an interface  62  and a graphic chip  64 . In the interface  62 , the aforementioned driver circuit is formed. Incidentally, the interface  62  may be built in a graphic chip  66  as shown in  FIG. 14 .  
         [0071]      FIG. 15  is a block diagram partially showing the configuration of a PC card  70  inserted into a PC card slot of a notebook personal computer. This PC card  70  is provided with an ASIC  72 , and the aforementioned driver circuit and parallel/serial converter are formed in this ASIC  72 . Accordingly, the PC card  70  inserted into the PC card slot exchanges data with the notebook personal computer via the ASIC  72 .  
         [0072]     It should be mentioned that the present invention is not limited to the aforementioned embodiments, and various changes may be made therein. For example, the driver circuit according to the present invention can be used by being incorporated not only into the motherboard  50 , the graphic card  60 , and the PC card  70  but also into various other systems.  
         [0073]     Respective elements and circuits are not limited to the aforementioned ones but can be realized by other elements and circuits which perform equal operations.