Abstract:
An on-chip thermal sensing circuit is disclosed. The thermal sensing circuit including a detection circuit located on an integrated circuit (IC) for detecting a local temperature of the IC. The output of the thermal sensor has a frequency that is directly related to the local temperature. The detection circuit has an associated time constant that is used to produce the frequency.

Description:
BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention relates generally to the field of integrated circuits, and, more specifically to an on-chip thermal sensing circuit for measuring the temperature of integrated circuit chips and particularly microprocessor chips. 
   2. Description of Related Art 
   It is important to be able to monitor the temperature of an integrated circuit (IC), particularly those implemented using CMOS designs. At higher temperatures, the IC&#39;s characteristics change. Circuits get slower, and reliability decreases. Thus, it is important to monitor the temperature of integrated circuits, and in particular microprocessor chips. 
   It is known in the art for a microprocessor to attempt to manage its temperature by regulating the speed at which it processes. In order to manage its temperature, both external sensors and on-chip sensors have been used. 
   External sensors are those sensors that are not located on the integrated circuit itself. These sensors are not preferable, however, because they do not provide real-time results and are unable to measure the circuit temperature at the location on the chip of the highest power dissipating circuits. 
   There have been a number of prior art proposals for on-chip temperature sensing. These proposals include the use of a pair of on-chip thermally response diodes coupled to an off-chip current source. The diode pair generates a differential voltage output that is proportional to temperature. This technique for sensing on-chip temperatures requires numerous connections between the chip and external circuitry for each temperature sensing circuit. Each connection to the chip increases the cost of the product. Small, self contained on-chip temperature sensors have a much lower cost than sensors requiring connections to circuitry external to the chip. 
   Another prior art design utilizes an on-chip thermal sensor as part of a thermal assist unit. The thermal assist unit consists of three registers, a multiplexer, a latch, a decoder, an interrupt generator, and a thermal logic control block. The thermal sensor circuit utilizes the differential voltage change across two diodes biased at the same operating current, where one diode is larger than the other. For example, the voltage across the larger diode will decrease more quickly than the voltage across the smaller diode when the temperature increases. 
   It would be desirable to be able to measure localized heating of the chip. Therefore, a need exists for an on-chip thermal sensing circuit that may be replicated throughout the chip. 
   SUMMARY OF THE INVENTION 
   An on-chip thermal sensing circuit is disclosed. The thermal sensing circuit including a detection circuit located on an integrated circuit (IC) for detecting a local temperature of the IC. The output of the thermal sensor has a frequency that is directly related to the local temperature. The detection circuit has an associated time constant that is used to produce the frequency. 
   The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
       FIG. 1  is a block diagram of a microprocessor chip that includes multiple thermal sensors on the chip in accordance with a preferred embodiment of the present invention; and 
       FIG. 2  is a schematic diagram of a circuit that is used as one of the thermal sensors of  FIG. 1  in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   A preferred embodiment of the present invention and its advantages are better understood by referring to the figures, like numerals being used for like and corresponding parts of the accompanying figures. 
     FIG. 1  is a block diagram of a microprocessor chip that includes multiple thermal sensors on the chip itself in accordance with a preferred embodiment of the present invention. Multiple thermal sensor circuits may be included on an integrated circuit, such as microprocessor chip  100 . For example, thermal sensing circuits  102 ,  104 , and  106  may be included in various locations on chip  100 . Each thermal sensor will detect and monitor a local temperature of the chip. The thermal sensors are small and require little power and therefore may be included throughout the chip. 
     FIG. 2  is a schematic diagram of a circuit  200  that is used as one of the thermal sensors  102 ,  104 , or  106  of  FIG. 1  in accordance with the present invention. Thermal sensing circuit  200  is based on the temperature coefficient of an on-chip resistor R sense  which can be composed of metal wire resistance, poly-silicon resistance, silicon diffusion resistance, or a combination of all three resistances. The resistance change of R sense  is converted to a frequency change through an RC time constant as described below. 
   Circuit  200  is an astable multivibrator circuit which produces a logical output signal at a frequency determined by the RC time constant of (R sense )(C) and the voltages V 1  and V 2  established by the voltage divider circuit that includes R 1 , R 2 , and R 3 . Circuits A 1  and A 2  are analog comparator circuits that produce a logic high level when the voltage at the first input, labeled “+”, is greater than the voltage at the second input, labeled “−”, and provides a logic low level signal when the voltage at the first input is less than the voltage at the second input. Logic gates G 1  and G 2  are two input logical NAND gates wired together to form a simple set/reset latch L 1 . Logic gate G 3  is a buffer circuit which buffers logic high and logic low levels to an RC circuit R sense  and C which are connected in series. 
   Once circuit  200  has achieved its operating state, initially, the voltage across capacitor C will be a little higher than voltage V 2  with analog comparator circuits A 1  and A 2  providing a logic high level output signal. The output of logic gate G 2  is a logic high level, and the output of logic gate G 1  is a logic low level. The output of logic gate G 3  is thus a logic high level causing the voltage across capacitor C to increase at a rate determined by the (R sense )(C) time constant. 
   When the voltage across capacitor C reaches or exceeds voltage V 1 , analog comparator circuit A 1  output changes from a logic high level to a logic low level causing logic gate G 1  output to change from a logic low level to a logic high level. This in turn causes the output of logic gate G 2  to change from a logic high level to a logic low level which in turn causes the output of logic gate G 3  to change from a logic high level to a logic low level. The logic low level on the output of G 3  causes the voltage to decrease on capacitor C at a rate determined by the (R sense )(C) time constant. As the voltage across capacitor C decreases to, or slightly below, voltage V 1 , analog comparator circuit A 1  changes output voltage from a logic low level to a logic high level. The outputs of logic gates G 1 , G 2 , and G 3  remain unchanged. 
   When the voltage across capacitor C reaches or is slightly below voltage V 2 , analog comparator circuit A 2  changes from a logic high level to a logic low level which in turn changes the output of logic gate G 2  from a logic low level to a logic high level. The logic high level on the output of logic gate G 2  causes the output of logic gate G 1  to change from a logic high level to a logic low level and also causes the output of logic gate G 3  to change from a logic low level to a logic high level. The logic high level of the output of logic gate G 3  causes the voltage to increase on capacitor C at a rate determined by the (R sense )(C) time constant. When the voltage across capacitor C is equivalent to or exceeds voltage V 2 , the output of analog comparator circuit A 2  changes from a logical low level to a logical high level. The outputs of logic gates G 1 , G 2 , and G 3  remain unchanged. 
   As the temperature on the chip changes, so will the resistance of resistor R sense  which in turn causes the (R sense )(C) time constant of the circuit to change. The frequency output will change as the chip temperature changes. The frequency change will be directly proportional to the resistor change which is directly proportional to the local chip temperature change. 
   The frequency output signal of logic gate G 1  may be used to regulate the chip temperature. This output signal may be provided as an input into a power management circuit, such as power management circuit 34 described in U.S. Pat. No. 5,485,127 which is hereby incorporated by reference in its entirety. The present invention could be used as the temperature sensor 32 of U.S. Pat. No. 5,485,127. 
   Circuit  200  is inherently self-starting. There are three possible initial conditions of circuit  200  prior to the circuit achieving its operating state. For example, if the initial condition is such that the voltage across capacitor C is less than V 2 , then comparator circuit A 2  will provide a logic low level to logic gate G 2 , while comparator circuit A 1  will provide a logic high level to logic gate G 1 . The logic low level at the input of logic gate G 2  results in a logic high level at the output of logic gate G 2  which in turn causes the output of logic gate G 3  to be a logic high level. The logic high level at the output of logic gate G 3  causes the voltage across capacitor C to increase at a rate determined by the (R sense ) (C) time constant. When the voltage across capacitor C reaches or exceeds voltage V 2 , analog comparator circuit A 2  output changes from a logic low level to a logic high level. The output of logic gate G 2  and G 3  does not change. When the voltage across capacitor C reaches or exceeds voltage V 1 , analog comparator circuit A 1  output changes from a logic high level to a logic low level causing logic gate G 1  output to change from a logic low level to a logic high level. The circuit has now achieved its operating state. It should be noted that the clock period for the initial clock cycle will not be equivalent to succeeding clock periods due to this initial voltage requiring addition time for capacitor C to charge to voltage V 1 . 
   A second initialization case is when the initial voltage across capacitor C is greater than V 1 . For this start up case, comparator A 1  will provide a logic low level to logic gate G 1 , while comparator circuit A 2  will provide a logic high level to logic gate G 2 . The logic low level at the input of logic gate G 1  results in a logic high level at the output of logic gate G 1 , providing a logic high level at the input of logic gate G 2 . The two logic high level signals at the inputs of logic gate G 2  cause the output of logic gate G 2  to be a logic low level, which in turn causes the output of logic gate G 3  to be a logic low level. The logic low level on the output of G 3  causes the voltage to decrease across capacitor C at a rate determined by the (R sense )(C) time constant. The voltage across capacitor C will decrease. When the voltage across capacitor C is less than V 1 , the output voltage of comparator A 1  will change to a logic high level. The output of logic gates G 1 , G 2  and G 3  does not change. The voltage across capacitor C continues to decrease until the voltage becomes equal or slightly lower than V 2 , which causes the output of comparator A 2  to change to a logic low level. The circuit has now achieved its operating state. It should be noted that the clock period for the initial clock cycle will not be equivalent to succeeding clock periods due to this initial voltage requiring additional time for capacitor C to discharge to voltage V 2 . 
   A third case to consider is when the voltage across capacitor C is between voltage V 1  and V 2 . For this case, the output logic level of G 2  determines whether the voltage across capacitor C will initially increase or decrease. The output voltage of both comparators A 1  and A 2  is a logic high level. If the output logic level of logic gate G 2  is a logic low level, the voltage across capacitor C will initially decrease until the voltage drops slightly below V 2 . This causes the output voltage of comparator A 2  to become a logic low level which in turn causes the output of logic gate G 2  to become a logic high level. This causes the output of logic gate G 3  to become a logic high level switch causes the voltage across capacitor C to increase. The circuit then operates as described above. If the initial condition is logic high level at the output of logic gate G 2 , the voltage across capacitor C initially increases until the voltage rises slightly above V 1 . This causes the output voltage of comparator A 1  to become a logic low level which in turn causes a logic high level at the output of logic gate G 2 . The logic high level of gate G 1  output and logic high level of comparator A 2  output causes the output of logic gate G 2  to switch to a logic low level which in turn causes the output of logic gate G 3  to switch to a logic low level. The logic low level output of G 3  causes the voltage across capacitor C to decrease at a rate determined by the (R sense )(C) time constant. The circuit then operates as described above. 
   Those skilled in the art will recognize that this circuit can be modified by removing analog comparator circuit A 2  and logic gates G 1  and G 2 , and by replacing the connection between the first input of A 1  and V 1  with two orthogonally switched circuits, such that a first switch is connected between the first input of A 1  and V 1  and a second switch is connected between the first input of A 1  and V 2 . When the output of analog comparator A 1  is a logic high level, the first switch is closed and the second switch is open. When the output of analog comparator A 1  is a logic low level, the first switch is opened and the second switch is closed. The output of analog comparator A 1  is connected to the input of logic gate G 3 . The circuit of this embodiment will operate similarly as described above with the voltage across capacitor C alternately increasing and decreasing between voltages V 1  and V 2 . 
   The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.