Abstract:
Semiconductor alloy fin structures can be formed by recessing a semiconductor material layer including a first semiconductor material to form a trench, and epitaxially depositing a semiconductor alloy material of the first semiconductor material and a second semiconductor material within the trench. The semiconductor alloy material is epitaxially aligned to the first semiconductor material in the semiconductor material layer. First semiconductor fins including the first semiconductor material and second semiconductor fins including the semiconductor alloy material can be simultaneously formed. In one embodiment, the first and second semiconductor fins can be formed on an insulator layer, which prevents diffusion of the second semiconductor material to the first semiconductor fins. In another embodiment, shallow trench isolation structures and reverse biased wells can be employed to provide electrical insulation among neighboring semiconductor fins.

Description:
BACKGROUND 
     The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure including semiconductor fins containing an alloy of two semiconductor materials, and a method of manufacturing the same. 
     A semiconductor alloy material including at least two semiconductor materials can provide a performance advantage for a field effect transistor. For example, a silicon germanium alloy channel can provide enhanced on-current over a silicon channel for p-type field effect transistors. However, forming a semiconductor alloy material on a semiconductor substrate is prone to generating an undesirable lateral diffusion of semiconductor materials into neighboring semiconductor material regions requiring a single semiconductor material. 
     BRIEF SUMMARY 
     Semiconductor alloy fin structures can be formed by recessing a semiconductor material layer including a first semiconductor material to form a trench, and epitaxially depositing a semiconductor alloy material of the first semiconductor material and a second semiconductor material within the trench. The semiconductor alloy material is epitaxially aligned to the first semiconductor material in the semiconductor material layer. First semiconductor fins including the first semiconductor material and second semiconductor fins including the semiconductor alloy material can be simultaneously formed. In one embodiment, the first and second semiconductor fins can be formed on an insulator layer, which prevents diffusion of the second semiconductor material to the first semiconductor fins. In another embodiment, shallow trench isolation structures and reverse biased wells can be employed to provide electrical insulation among neighboring semiconductor fins. 
     According to an aspect of the present disclosure, a method of forming a semiconductor structure is provided. A trench is formed in a single crystalline semiconductor material layer including a first semiconductor material and located in a semiconductor substrate. A single crystalline semiconductor alloy of the first semiconductor material and a second semiconductor material different from the first semiconductor material is epitaxially deposited within the trench. The single crystalline semiconductor material layer and the single crystalline semiconductor alloy are patterned to form a first semiconductor fin including the first semiconductor material and a second semiconductor fin including the single crystalline semiconductor alloy, respectively. 
     According to another aspect of the present disclosure, a semiconductor structure is provided, which includes a semiconductor substrate embedding a first single crystalline embedded doped well and a second single crystalline embedded doped well in an upper portion of the semiconductor substrate. A first semiconductor fin is epitaxially aligned to the first single crystalline embedded doped well and includes a first single crystalline semiconductor material. A second semiconductor fin is epitaxially aligned to the second single crystalline embedded doped well, and includes a single crystalline semiconductor alloy of the first semiconductor material and a second semiconductor material different from the first semiconductor material, and is located on the top surface of the insulator layer. 
     According to yet another aspect of the present disclosure, another semiconductor structure is provided which includes a substrate that contains a stack, from bottom to top, of a handle substrate and an insulator layer. A first semiconductor fin includes a first single crystalline semiconductor material and is located on a top surface of the insulator layer. A second semiconductor fin includes a single crystalline semiconductor alloy of the first semiconductor material and a second semiconductor material different from the first semiconductor material, and is located over the top surface of the insulator layer. The first single crystalline semiconductor material and the single crystalline semiconductor alloy material have an identically oriented set of crystallographic orientations. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1A  is a top-down view of a first exemplary semiconductor structure after formation of a hard mask layer and application and patterning of a photoresist layer according to a first embodiment of the present disclosure. 
         FIG. 1B  is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 1A . 
         FIG. 2A  is a top-down view of the first exemplary semiconductor structure after formation of a trench according to the first embodiment of the present disclosure. 
         FIG. 2B  is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 2A . 
         FIG. 3A  is a top-down view of the first exemplary semiconductor structure after epitaxially depositing a single crystalline semiconductor alloy region to the first embodiment of the present disclosure. 
         FIG. 3B  is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 3A . 
         FIG. 4A  is a top-down view of the first exemplary semiconductor structure after removal of the hard mask layer according to the first embodiment of the present disclosure. 
         FIG. 4B  is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 4A . 
         FIG. 5A  is a top-down view of the first exemplary semiconductor structure after formation of fin cap dielectric portions according to the first embodiment of the present disclosure. 
         FIG. 5B  is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 5A . 
         FIG. 6A  is a top-down view of the first exemplary semiconductor structure after patterning of first semiconductor fins and second semiconductor fins according to the first embodiment of the present disclosure. 
         FIG. 6B  is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 6A . 
         FIG. 7A  is a top-down view of the first exemplary semiconductor structure after optional homogenization of second semiconductor fins according to the first embodiment of the present disclosure. 
         FIG. 7B  is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 7A . 
         FIG. 8A  is a top-down view of the first exemplary semiconductor structure after formation of gate electrodes and source and drain regions according to the first embodiment of the present disclosure. 
         FIG. 8B  is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 8A . 
         FIG. 9A  is a top-down view of a second exemplary semiconductor structure after formation of single crystalline embedded doped wells according to a second embodiment of the present disclosure. 
         FIG. 9B  is a vertical cross-sectional view of the second exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 9A . 
         FIG. 10A  is a top-down view of the second exemplary semiconductor structure after formation of a hard mask layer and application and patterning of a photoresist layer according to the second embodiment of the present disclosure. 
         FIG. 10B  is a vertical cross-sectional view of the second exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 10A . 
         FIG. 11A  is a top-down view of the second exemplary semiconductor structure after epitaxially depositing a single crystalline semiconductor alloy region according to the second embodiment of the present disclosure. 
         FIG. 11B  is a vertical cross-sectional view of the second exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 11A . 
         FIG. 12A  is a top-down view of the second exemplary semiconductor structure after patterning of first semiconductor fins and second semiconductor fins according to the second embodiment of the present disclosure. 
         FIG. 12B  is a vertical cross-sectional view of the second exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 12A . 
         FIG. 13A  is a top-down view of the second exemplary semiconductor structure after formation of shallow trench isolation structures according to the second embodiment of the present disclosure. 
         FIG. 13B  is a vertical cross-sectional view of the second exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 13A . 
         FIG. 14A  is a top-down view of the exemplary semiconductor structure after optional diffusion of materials within second semiconductor fins according to the second embodiment of the present disclosure. 
         FIG. 14B  is a vertical cross-sectional view of the second exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 14A . 
         FIG. 15A  is a top-down view of the second exemplary semiconductor structure after formation of gate electrodes and source and drain regions according to the second embodiment of the present disclosure. 
         FIG. 15B  is a vertical cross-sectional view of the second exemplary semiconductor structure along the vertical plane B-B′ of  FIG. 15A . 
     
    
    
     DETAILED DESCRIPTION 
     As stated above, the present disclosure relates to a semiconductor structure including semiconductor fins containing an alloy of two semiconductor materials, and a method of manufacturing the same. Aspects of the present disclosure are now described in detail with accompanying figures. It is noted that like reference numerals refer to like elements across different embodiments. The drawings are not necessarily drawn to scale. 
     Referring to  FIGS. 1A and 1B , a first exemplary semiconductor structure according to a first embodiment of the present disclosure can be formed by providing a semiconductor-on-insulator (SOI) substrate. The SOI substrate can include a vertical stack, from bottom to top, of a handle substrate  10 , a buried insulator layer  20 , and a top semiconductor layer  30 L. 
     The handle substrate  10  can include a semiconductor material, a conductive material, and/or a dielectric material. The handle substrate  10  provides mechanical support to the buried insulator layer  20  and the top semiconductor layer  30 L. The thickness of the handle substrate  10  can be from 30 microns to 2 mm, although lesser and greater thicknesses can also be employed. 
     The buried insulator layer  20  includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The thickness of the buried insulator layer  20  can be from 50 nm to 5 microns, although lesser and greater thicknesses can also be employed. 
     The top semiconductor layer  30 L is a single crystalline semiconductor material layer including a first semiconductor material. The first semiconductor material can be an elemental semiconductor material or a compound semiconductor material. For example, the first semiconductor material can be silicon, germanium, a silicon-germanium alloy, or a silicon-carbon alloy. The first semiconductor material may, or may not, be doped with p-type dopants and/or n-type dopants. The entirety of the top semiconductor layer  30 L can be single crystalline. In one embodiment, the first semiconductor material can be an elemental single crystalline semiconductor material. In one embodiment, the first semiconductor material can be single crystalline silicon. The thickness of the top semiconductor layer  30 L can be from 10 nm to 500 nm, although lesser and greater thicknesses can also be employed. 
     A hard mask layer  40  can be formed over the top semiconductor layer  32 L. The hard mask layer  40  includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The hard mask layer  40  can be deposited, for example, by chemical vapor deposition (CVD). The hard mask layer  40  can be deposited as a blanket (unpatterned) layer having a uniform thickness over the top surface of the top semiconductor layer  30 L. The thickness of the hard mask layer  40  can be from 3 nm to 100 nm, although lesser and greater thicknesses can also be employed. 
     A photoresist layer  47  is applied over the top semiconductor layer  30 L, and is subsequently patterned by lithographic methods. Specifically, an opening is formed in the photoresist layer  47  above a region of the top semiconductor layer  30 L by lithographic exposure and development. 
     Referring to  FIGS. 2A and 2B , the pattern in the photoresist layer  47  is transferred into an upper portion of the top semiconductor layer  30 L by an etch that employs the photoresist layer  47  as an etch mask. The etch can be an anisotropic etch such as a reactive ion etch, or an isotropic etch such as a wet etch. 
     The portion of the top semiconductor layer  30 L underneath the opening in the photoresist layer  47  is recessed during the etch. A trench  31  is formed in an upper portion of the top semiconductor layer  30 L. The depth of the trench  31 , defined as the vertical distance between the topmost surface of the top semiconductor layer  30 L and the bottom surface of the trench  32 , is less than the thickness of the top semiconductor layer  30 L in regions outside the trench  31 . Thus, the bottom surface of the trench  31  is located within a horizontal plane that is located above, and vertically spaced from, the interface between the top semiconductor layer  30 L and the buried insulator layer  20 . The ratio of the depth of the trench  31  to the thickness of the top semiconductor layer  30 L in regions outside the trench  31  can be from 0.01 to 0.99, and is typically from 0.1 to 0.9. The photoresist layer  47  is subsequently removed selective to the top semiconductor layer  30 L, for example, by ashing. 
     Referring to  FIGS. 3A and 3B , an alloy of the first semiconductor material and a second semiconductor material is deposited within the trench  31  by selective epitaxy. The second semiconductor material is a different semiconductor material than the first semiconductor material. As used herein, a second semiconductor material is different from a first semiconductor material if the second semiconductor material includes a different elemental semiconductor material or a different compound semiconductor than the first semiconductor material. In one embodiment, the first semiconductor material can be silicon, and the second semiconductor material can be germanium or carbon. 
     The alloy of the first semiconductor material and the second semiconductor material can be deposited by selective epitaxy, in which the second epitaxial material nucleates upon, and grows from, physically exposed semiconductor surfaces of the first semiconductor material within the trench  31 , while not nucleating on any dielectric surface such as the surfaces of the hard mask layer  40 . The selective epitaxy can be performed, for example, by concurrently or alternately flowing reactant gases with an etchant gas. The reactant gases can be selected, for example, from a combination of at least two of SiH 4 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , Si 2 H 6 , GeH 4 , Ge 2 H 6 , CH 4 , C 2 H 2 , C 2 H 4 , C 2 H 6 , or any other source gas for silicon, germanium, carbon, or compound semiconductor materials as known in the art. The etchant gas can be, for example, HCl. A carrier gas such as H 2 , He, Ar, N 2 , or combinations thereof, can be optionally employed. 
     The alloy of the first semiconductor material and the second semiconductor material is deposited with epitaxial alignment to the single crystalline semiconductor structure of the top semiconductor layer  30 L, and forms a single crystalline semiconductor alloy region  50 R. In one embodiment, the alloy of the first semiconductor material and the second semiconductor material can be deposited to completely fill the trench  31  and to protrude above the horizontal plane of the top surface of the hard mask layer  40 . Subsequently, the portion of the alloy of the first semiconductor material and the second semiconductor material above the horizontal plane of the top surface of the hard mask layer  40  can be removed, for example, by chemical mechanical planarization. Optionally, the alloy of the first semiconductor material and the second semiconductor material can be recessed below the horizontal plane of the top surface of the hard mask layer  40  by a wet etch or a dry etch such that the recessed top surface of the single crystalline semiconductor alloy region  50 R is located below the horizontal plane of the top surface of the hard mask layer  40 . 
     In one embodiment, the top surface of the single crystalline semiconductor alloy region  50 R can be substantially coplanar with, raised above, or recessed below the topmost surface of the top semiconductor layer  30 L. A horizontal interface between the first semiconductor material of the top semiconductor layer  30 L and the single crystalline semiconductor alloy region  50 R is formed above the interface between the buried insulator layer  20  and the top semiconductor layer  30 L. The single crystalline semiconductor alloy region  50 R can include a single crystalline semiconductor alloy of at least two semiconductor materials. 
     In one embodiment, the first semiconductor material and the single crystalline semiconductor alloy material in the single crystalline semiconductor alloy region  50 R can be single crystalline semiconductor materials having a same crystallographic structure. In this case, the first single crystalline semiconductor material of the top semiconductor layer  30 L and the single crystalline semiconductor alloy material of the single crystalline semiconductor alloy region  50 R can have an identically oriented set of crystallographic orientations. In other words, each corresponding crystallographic orientation having a same set of Miller indices can be spatially along the same orientation across the top semiconductor layer  30 L and the single crystalline semiconductor alloy region  50 R. 
     Referring to  FIGS. 4A and 4B , the hard mask layer  40  is removed, for example, by a wet etch. In one embodiment, the removal of the hard mask layer  40  can be performed employing an etch chemistry that is selective to the semiconductor materials of the top semiconductor layer  30 L and the single crystalline semiconductor alloy region  50 R. Optionally, a planarization process, such as chemical mechanical planarization, can be performed so that the topmost surface of the top semiconductor layer  30 L and the top surface of the single crystalline semiconductor alloy region  50 R are coplanar with each other. 
     Referring to  FIGS. 5A and 5B , a plurality of fin cap dielectric portions  60  are formed over the top semiconductor layer  30 L and the single crystalline semiconductor alloy region  50 R. The plurality of fin cap dielectric portions  60  can be formed, for example, by forming a dielectric material layer on top of the top semiconductor layer  30 L and the single crystalline semiconductor alloy region  50 R, and subsequently patterning the dielectric material layer with a pattern by a lithographic method. For example, a photoresist layer (not shown) can be applied over the dielectric material layer and lithographically patterned, and the pattern in the photoresist layer can be transferred into the dielectric material layer by a pattern transfer etch to form the plurality of fin cap dielectric portions  60 . The photoresist layer can be removed, for example, by ashing. 
     The dielectric material layer includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric metal oxide, or a dielectric metal oxynitride. The dielectric material layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), or by spin-coating. The thickness of the dielectric material layer can be, for example, from 10 nm to 200 nm, although lesser and greater thicknesses can also be employed. 
     In one embodiment, the pattern in the plurality of fin cap dielectric portions  60  can include a plurality of line structures having a uniform width and laterally extending along a direction, which is herein referred to as a lengthwise direction of the plurality of fin cap dielectric portions  60 . In one embodiment, the uniform width can be a minimum lithographic dimension that can be printed as parallel lines. For example, the uniform width can be 80 nm or less. In one embodiment, portions of the plurality of fin cap dielectric portions  60  can be in a one-dimensional array having a periodicity along a horizontal direction that is perpendicular to the lengthwise direction of the plurality of fin cap dielectric portions  60 . 
     Referring to  FIGS. 6A and 6B , the pattern in the plurality of fin cap dielectric portions  60  is transferred into the top semiconductor layer  30 L and the single crystalline semiconductor alloy region  50 R by an etch, which can be an anisotropic etch such as a reactive ion etch. The etch removes the semiconductor materials of the top semiconductor layer  30 L and the single crystalline semiconductor alloy region  50 R employing the plurality of fin cap dielectric portions  60  as an etch mask. The etch can proceed until the top surface of the buried insulator layer  20  is physically exposed. 
     First vertical stacks including remaining portions of the top semiconductor layer  30 L and a first subset of the plurality of fin cap dielectric portions  60  are formed in regions that do not include the single crystalline semiconductor alloy material (i.e., in regions in which the single crystalline semiconductor alloy region  50 R is not present at the processing step of  FIGS. 5A and 5B ), and second vertical stacks including remaining portions of the single crystalline semiconductor alloy region  50 R and the top semiconductor layer  30 L and a second subset of the plurality of fin cap dielectric portions  60  are formed in regions that include the single crystalline semiconductor alloy material (i.e., in regions in which the single crystalline semiconductor alloy region  50 R is present at the processing step of  FIGS. 5A and 5B ). Each first vertical stack includes a first semiconductor fin  30  and a fin cap dielectric portion  60 . Each second vertical stack includes a second semiconductor fin and a fin cap dielectric portion  60 . Each second semiconductor fin includes a vertical stack of a first semiconductor material portion  32  including the first semiconductor material and a semiconductor alloy portion  50  including the second semiconductor material. Each first semiconductor material portion  32  is a single crystalline portion of the first semiconductor material. Each semiconductor alloy portion  50  is a single crystalline semiconductor alloy material portion that is epitaxially aligned to the underlying single crystalline portion of the first semiconductor material, i.e., an underlying first semiconductor material portion  32 . 
     The top surface of the buried insulator layer  20  is physically exposed by etching portions of the top semiconductor layer  30 L, which is a single crystalline semiconductor material layer, and the single crystalline semiconductor alloy region  50 R, which includes a single crystalline semiconductor alloy. Each first semiconductor fin  30  is single crystalline throughout the entirety thereof, and each second semiconductor fin ( 32 ,  50 ) is single crystalline throughout the entirety thereof. In one embodiment, each first semiconductor material portion  32  can include a single semiconductor material such as silicon, and each semiconductor alloy portion  50  can include a single crystalline semiconductor alloy of at least two semiconductor materials such as a silicon-germanium alloy or a silicon-carbon alloy. Each first semiconductor fin  30  includes the first single crystalline semiconductor material, and is located on the top surface of the buried insulator layer  20 . Each semiconductor alloy portion  50  can include a single crystalline semiconductor alloy of the first semiconductor material and a second semiconductor material different from the first semiconductor material. Each semiconductor alloy portion  50  is located over the top surface of the buried insulator layer  20 . The first single crystalline semiconductor material and the single crystalline semiconductor alloy material have an identically oriented set of crystallographic orientations. 
     Referring to  FIGS. 7A and 7B , an optional homogenization of the second semiconductor fins ( 32 ,  50 ) can be performed. As used herein, “homogenization” is a process of reducing differences in compositions of different material portions or making a transition in composition from one material portion to another material portion more gradual than before. The optional homogenization of the composition within the second semiconductor fin ( 32 ,  50 ) can be performed by inducing interdiffusion of materials across the portion of the first semiconductor material and the portion of the single crystalline semiconductor alloy, i.e., across the first semiconductor material portion  32  and the semiconductor alloy portion  50  within the second semiconductor fins ( 32 ,  50 ). The interdiffusion of materials across the first semiconductor material portion  32  and the semiconductor alloy portion  50  within the second semiconductor fins ( 32 ,  50 ) can be performed, for example, by a thermal anneal at an elevated temperature, which can be, for example, in a range from 700° C. to 1,200° C., although lesser and greater temperatures can also be employed. If homogenization is performed, the second semiconductor fins ( 32 ,  50 ) are converted into homogenized second semiconductor fins  50 ′, which does not have an atomic level interface between a first semiconductor portion  32  and a second semiconductor portion  50 . The entirety of the homogenized second semiconductor fins  50 ′ includes the second semiconductor material. 
     The homogenization of the second semiconductor fins ( 32 ,  50 ) may, or may not, be complete. If the homogenization of the second semiconductor fins ( 32 ,  50 ) is complete, an atomic concentration of an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material is constant throughout the entirety of each homogenized second semiconductor fin  50 ′. If the homogenization of the second semiconductor fins ( 32 ,  50 ) is incomplete, an atomic concentration of an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material increases with a vertical distance from the buried insulator layer at least within a bottom portion of each homogenized second semiconductor fin  50 ′. In one embodiment, the atomic concentration of an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material can increase with a vertical distance from the buried insulator layer at least throughout the entirety of each homogenized second semiconductor fin  50 ′. In another embodiment, the atomic concentration of an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material can be substantially uniform in an upper portion of said second semiconductor fin. 
     In one embodiment, the first single crystalline semiconductor material can be single crystalline silicon, and an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material can be germanium, carbon, gallium arsenide, or another compound semiconductor material. 
     Referring to  FIGS. 8A and 8B , a stack of a first gate dielectric  70 A and a first gate electrode  72 A can be formed over one or more of the first semiconductor fins. A first gate spacer  74 A can be formed around the stack of the first gate dielectric  70 A and the first gate electrode  72 A. Source and drain ion implantation can be performed, optionally after masking the homogenized second semiconductor fins  50 ′ (See  FIGS. 7A and 7B ) or the second semiconductor fins ( 32 ,  50 ) without homogenization (See  FIGS. 6A and 6B ), to form first source regions  30 S and first drain regions  30 D. Portions of the first semiconductor fins  30  that are not converted into the first source regions  30 S or the first drain regions  30 D are first body regions  30 B, which include channels of a first field effect transistor. 
     A stack of a second gate dielectric  70 B and a second gate electrode  72 B can be formed over one or more of the homogenized second semiconductor fins  50 ′ (See  FIGS. 7A and 7B ) or the second semiconductor fins ( 32 ,  50 ) without homogenization (See  FIGS. 6A and 6B ). A second gate spacer  74 B can be formed around the stack of the second gate dielectric  70 B and the second gate electrode  72 B. Source and drain ion implantation can be performed, optionally after masking the first semiconductor fins  30  (See  FIGS. 7A and 7B ), to form second source regions  505  and second drain regions  50 D. Portions of the homogenized second semiconductor fins  50 ′ (or second semiconductor fins ( 32 ,  50 ) that are not homogenized) that are not converted into the second source regions  50 S or the second drain regions  50 D are second body regions  50 B, which include channels of a second field effect transistor. 
     The different semiconductor materials in the first and second field effect transistors can be employed to optimize the performance of the first and second field effect transistors independently. In one embodiment, one of the first and second field effect transistors is a p-type field effect transistor, and the other of the first and second field effect transistors is an n-type field effect transistor. In this case, the use of two different semiconductor materials in the channels of the first and second field effect transistors enable separate optimization of the p-type field effect transistor and the n-type field effect transistor, for example, for the purpose of maximizing the on-current. 
     Referring to  FIGS. 9A and 9B , a second exemplary semiconductor structure according to a second embodiment of the present disclosure can be formed employing a bulk semiconductor substrate including a single crystalline semiconductor layer  130 L. The single crystalline semiconductor layer  130 L includes a first semiconductor material throughout an entirety thereof. The entirety of the single crystalline semiconductor layer  130 L is single crystalline. 
     A first embedded doped well  132 A and a second embedded doped well  132 B can be formed within the single crystalline semiconductor layer  130 L. In one embodiment, the first embedded doped well  132 A and the second embedded doped well  132 B may have a doping of opposite conductivity types. For example, the first embedded doped well  132 A can be a p-doped well and the second embedded doped well  132 B can be an n-doped well, or vice versa. The dopant concentration of the first embedded doped well  132 A and the second embedded doped well  132 B can be in any range known in the art for well doping. The topmost surface of the first embedded doped well  132 A and the topmost surface of the second embedded doped well  132 B are vertically spaced from the topmost surface of the single crystalline semiconductor layer  130 L by a vertical distance, which is approximately by a height of semiconductor fins to be subsequently formed. The vertical distance can be, for example, from 30 nm to 300 nm, although lesser and greater vertical distances can also be employed. 
     Referring to  FIGS. 10A and 10B , a hard mask layer  40  and a photoresist layer  47  is formed in the same manner as in the first embodiment. The opening in the photoresist layer  47  can overlie the second embedded doped well  132 B. 
     Referring to  FIGS. 11A and 11B , a single crystalline semiconductor alloy region  50 R is formed in the same manner as in the first embodiment. The single crystalline semiconductor alloy region  50 R can overlie, and can be vertically spaced from, the second embedded doped well  132 B. 
     Referring to  FIGS. 12A and 12B , the processing steps of  FIGS. 4A ,  4 B,  5 A,  5 B,  6 A, and  6 B are performed in the same manner as in the first embodiment except for the modification that the first embedded doped well  132 A and the second embedded doped well  132 B are employed as etch stop layers for the purpose of the anisotropic etch that defines semiconductor fins instead of the top surface of the buried insulator layer  20  of the first embodiment (See  FIGS. 6A and 6B ). In one embodiment, overetch may be optionally performed through the top surfaces of the first embedded doped well  132 A and the second embedded doped well  132 B. 
     First vertical stacks are formed above a horizontal surface of the first embedded doped well  132 A. First vertical stacks include remaining portions of the top semiconductor layer  30 L above the first embedded doped well  132 A, a first subset of the plurality of fin cap dielectric portions  60  located above the first embedded doped well  132 A, and optionally portions of the first embedded doped well  132 A above a horizontal recessed surface of the first embedded doped well  132 A, if the first embedded doped well  132 A includes the horizontal recessed surface. Second vertical stacks are formed above a horizontal surface of the second embedded doped well  132 B. Second vertical stacks include remaining portions of the single crystalline semiconductor alloy region  50 R above the second embedded doped well  132 B, remaining portions of the top semiconductor layer  30 L above the second embedded doped well  132 B, and a second subset of the plurality of fin cap dielectric portions  60  located above the second embedded doped well  132 B, and optionally portions of the second embedded doped well  132 B above a horizontal recessed surface of the second embedded doped well  132 B, if the second embedded doped well  132 B includes the horizontal recessed surface. Each first vertical stack includes a first semiconductor fin  30  and a fin cap dielectric portion  60  and optionally a portion of the first embedded doped well  132 A, which is herein referred to as an upper first embedded doped well portion  39 A. Each second vertical stack includes a second semiconductor fin and a fin cap dielectric portion  60  and optionally a portion of the second embedded doped well  132 B, which is herein referred to as an upper second embedded doped well portion  39 B. Each second semiconductor fin includes a vertical stack of a first semiconductor material portion  32  including the first semiconductor material and a semiconductor alloy portion  50  including the second semiconductor material. Each first semiconductor material portion  32  is a single crystalline portion of the first semiconductor material. Each semiconductor alloy portion  50  is a single crystalline semiconductor alloy portion that is epitaxially aligned to the underlying single crystalline portion of the first semiconductor material, i.e., an underlying first semiconductor material portion  32 . 
     A horizontal surface of the first embedded doped well  132 A and a horizontal surface of the second embedded doped well  132 B are physically exposed by etching portions of the top semiconductor layer  30 L, which is a single crystalline semiconductor material layer, and the single crystalline semiconductor alloy region  50 R, which includes a single crystalline semiconductor alloy. Each first semiconductor fin  30  is single crystalline throughout the entirety thereof, and each second semiconductor fin ( 32 ,  50 ) is single crystalline throughout the entirety thereof. In one embodiment, each first semiconductor material portion  32  can include a single semiconductor material such as silicon, and each semiconductor alloy portion  50  can include a single crystalline semiconductor alloy of at least two semiconductor materials such as a silicon-germanium alloy or a silicon-carbon alloy. Each first semiconductor fin  30  includes the first single crystalline semiconductor material, and is located on the top surface of the buried insulator layer  20 . Each semiconductor alloy portion  50  can include a single crystalline semiconductor alloy of the first semiconductor material and a second semiconductor material different from the first semiconductor material. Each semiconductor alloy portion  50  is located over the top surface of the buried insulator layer  20 . The first single crystalline semiconductor material and the single crystalline semiconductor alloy material have an identically oriented set of crystallographic orientations. 
     Referring to  FIGS. 13A and 13B , shallow trench isolation structures  120  can be formed on the first and second embedded doped wells ( 132 A,  132 B) and on lower portions of sidewalls of the first semiconductor fins  30  and the second semiconductor fins ( 32 ,  50 ). The shallow trench isolation structures  120  include a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, or organosilicate glass. The shallow trench isolation structures  120  can be formed, for example, by spin-coating of a dielectric material, or a combination of a deposition, a planarization, and a recess of a dielectric material. In on embodiment, the top surfaces of the shallow trench isolation structures  120  are located above the top surfaces of the first and second embedded doped wells ( 132 A,  132 B). The top surfaces of the shallow trench isolation structures  120  may be above, at, or below the plane of the interface between the horizontal plane of interfaces between the first semiconductor material portions  32  and the semiconductor alloy portions  50 . 
     Referring to  FIGS. 14A and 14B , an optional homogenization of the second semiconductor fins ( 32 ,  50 ) can be performed. The optional homogenization of the composition within the second semiconductor fin ( 32 ,  50 ) can be performed by inducing interdiffusion of materials across the portion of the first semiconductor material and the portion of the single crystalline semiconductor alloy, i.e., across the first semiconductor material portion  32  and the semiconductor alloy portion  50  within the second semiconductor fins ( 32 ,  50 ). The interdiffusion of materials across the first semiconductor material portion  32  and the semiconductor alloy portion  50  within the second semiconductor fins ( 32 ,  50 ) can be performed, for example, by a thermal anneal at an elevated temperature, which can be, for example, in a range from 700° C. to 1,000° C., although lesser and greater temperatures can also be employed provided that the outdiffusion of dopants from the first and second embedded doped wells ( 132 A,  132 B) into the first and second semiconductor fins ( 30 ,  32 ,  50 ) is maintained below a level that substantially changes the dopant concentration in the first and second semiconductor fins ( 30 ,  32 ,  50 ). If homogenization is performed, the second semiconductor fins ( 32 ,  50 ) are converted into homogenized second semiconductor fins  50 ′, which does not have an atomic level interface between a first semiconductor portion  32  and a second semiconductor portion  50 . The entirety of the homogenized second semiconductor fins  50 ′ includes the second semiconductor material. 
     The homogenization of the second semiconductor fins ( 32 ,  50 ) may, or may not, be complete. If the homogenization of the second semiconductor fins ( 32 ,  50 ) is complete, an atomic concentration of an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material is constant throughout the entirety of each homogenized second semiconductor fin  50 ′. If the homogenization of the second semiconductor fins ( 32 ,  50 ) is incomplete, an atomic concentration of an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material increases with a vertical distance from the buried insulator layer at least within a bottom portion of each homogenized second semiconductor fin  50 ′. In one embodiment, the atomic concentration of an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material can increase with a vertical distance from the buried insulator layer at least throughout the entirety of each homogenized second semiconductor fin  50 ′. In another embodiment, the atomic concentration of an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material can be substantially uniform in an upper portion of said second semiconductor fin. 
     In one embodiment, the first single crystalline semiconductor material can be single crystalline silicon, and an elemental semiconductor or a compound semiconductor material that is present in the single crystalline semiconductor alloy and not present in the first single crystalline semiconductor material can be germanium, carbon, gallium arsenide, or another compound semiconductor material. 
     Referring to  FIGS. 15A and 15B , a stack of a first gate dielectric  70 A and a first gate electrode  72 A can be formed over one or more of the first semiconductor fins. A first gate spacer  74 A can be formed around the stack of the first gate dielectric  70 A and the first gate electrode  72 A. Source and drain ion implantation can be performed, optionally after masking the homogenized second semiconductor fins  50 ′ (See  FIGS. 14A and 14B ) or the second semiconductor fins ( 32 ,  50 ) without homogenization (See  FIGS. 13A and 13B ), to form first source regions  30 S and first drain regions  30 D. Portions of the first semiconductor fins  30  that are not converted into the first source regions  30 S or the first drain regions  30 D are first body regions  30 B, which include channels of a first field effect transistor. 
     A stack of a second gate dielectric  70 B and a second gate electrode  72 B can be formed over one or more of the homogenized second semiconductor fins  50 ′ (See  FIGS. 14A and 14B ) or the second semiconductor fins ( 32 ,  50 ) without homogenization (See  FIGS. 13A and 13B ). A second gate spacer  74 B can be formed around the stack of the second gate dielectric  70 B and the second gate electrode  72 B. Source and drain ion implantation can be performed, optionally after masking the first semiconductor fins  30  (See  FIGS. 14A and 14B ), to form second source regions  505  and second drain regions  50 D. Portions of the homogenized second semiconductor fins  50 ′ (or second semiconductor fins ( 32 ,  50 ) that are not homogenized) that are not converted into the second source regions  50 S or the second drain regions  50 D are second body regions  50 B, which include channels of a second field effect transistor. 
     The different semiconductor materials in the first and second field effect transistors can be employed to optimize the performance of the first and second field effect transistors independently. In one embodiment, one of the first and second field effect transistors is a p-type field effect transistor, and the other of the first and second field effect transistors is an n-type field effect transistor. In this case, the use of two different semiconductor materials in the channels of the first and second field effect transistors enable separate optimization of the p-type field effect transistor and the n-type field effect transistor, for example, for the purpose of maximizing the on-current. 
     While the disclosure has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Each of the embodiments described herein can be implemented individually or in combination with any other embodiment unless expressly stated otherwise or clearly incompatible. Accordingly, the disclosure is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the disclosure and the following claims.