Abstract:
For a package structure of chip and the formation thereof, adhesive, conductive and metal layers are positioned on a substrate. The portions of the conductive and metal layers are removed to form multitudes of trenches therethrough, so that the metal layer is divided into chip supporters and conductive nodes isolated or electrical coupled each another. A chip is positioned on each of the chip supporter and electrically coupled to the conductive nodes. A molding compound covers the conductive layer, metal layer and chip. Then the substrate is removed. A dicing process as is applied with each chip or chipset as a unit to form the package structures of chip. There are advantages over improvement of reliability, reduction of package height, improve of level characteristic and heat dissipation, which may be applied to different types of semiconductor package.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to a package structure of chip and the package method thereof. In particular, the invention relates to a package structure of chip with more level surface and less height and the package method thereof. 
     2. Description of the Prior Art 
     With the rapid improvement of semiconductor technology, there are more and more requirements on the functions, portability and compact sizes for computers and telecommunication products. Accordingly, the manufacturers of chip package develop technology to produce the products with high power, high integrity, light and small size. Moreover, for electronics packaging, there are higher requirements on reliability and heat dissipation to be capable of transmitting signals and energy, providing good path of heat dissipation, protecting and supporting. 
     It is a trend to produce package elements of semiconductor with compact sizes, rapid speed and high integrity. However, the power consumption becomes a heavy load. Thus, it is an important issue on the heat dissipation for package elements. 
     Nowadays in processing printed circuit boards, each element is attached on the printed circuit board with soldering. Thus, when attached any element, the printed circuit board needs a well level surface to meet the high reliability of electrical element. 
     Accordingly, it is important to provide an improved package structure of chip and the formation thereof. 
     SUMMARY OF THE INVENTION 
     One of the embodiments of the present invention provides a package method for a package structure. A substrate is used as a supporter to load package elements and then removed during subsequent process, so as to provide the stable structure and improve the reliability during the package process. Such as a printed circuit board with high-quality level surface may meet a severe requirement on smooth quality. 
     The other one of the embodiments of the present invention provides a package method for a package structure. A forming process may be repeatedly applied to the package structure to form a stacked structure for multiplayer printed circuit board. Such a package method may be applied to many types of semiconductor package. 
     Another one of the embodiment of the present invention is to provide the package structure of chip and the formation thereof. One chip is positioned on the chip supporter of a metal layer to improve the heat dissipation. Moreover, the conductive nodes provide the heavy amount of leads. 
     The other one of embodiments of the present invention is to provide the package structure with the height reduction. With the height in micrometers, the package structure compared to the conventional one may reduce the whole height of package structure. 
     Accordingly, a package method for a chip is provided. A substrate is provided with at least one adhesive layer and at least one conductive layer subsequently thereon. A patterned layer is formed on the conductive layer and a film on the bottom surface of the substrate. At least one metal layer is filled into the patterned layer. The patterned layer and the film are formed. The portions of the conductive layer are removed to form a plurality of trenches through the conductive layer on the substrate, wherein the trenches divide the metal layer into a plurality of chip supporters and conductive nodes isolated each another. At least one chip is formed on each of the chip supporter, the chips electrically coupled to the conductive nodes, respectively. A molding compound is formed on the adhesive layer to encapsulate the conductive layer, the metal layer and the chips, and then the substrate is removed. Dicing is applied with each of chip or chipset as a unit to form a plurality of package structures of chip. 
     Accordingly, a package structure of chip is provided to comprise a chip supporter. A plurality of conductive nodes isolated are positioned around the chip supporter, wherein the chip supporter and the conductive nodes include at least one conductive layer, at least one metal layer thereon, and a plurality of trenches through the conductive layer and metal layer to divide the chip supporter and the conductive nodes. At least one chip is positioned on the chip supporter and electrically coupled with conductive nodes. A molding compound is formed atop the surface of the conductive layer to encapsulate the metal layer and the chip. 
    
    
     
       The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings. 
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1(   a ) to  FIG. 1(   h ) are cross-sectional diagrams illustrating a package method in accordance with one embodiment of the present invention. 
         FIG. 2  is a cross-sectional diagram illustrating a package structure in accordance with one embodiment of the present invention. 
         FIG. 3(   a ) to  FIG. 3(   i ) are cross-sectional diagrams illustrating a package method in accordance with another one embodiment of the present invention. 
         FIG. 4  is a cross-sectional diagram illustrating a substrate with trenches in accordance with one embodiment of the present invention. 
         FIG. 5  is a cross-sectional diagram illustrating the trenches through the adhesive and conductive layer in accordance with one embodiment of the present invention. 
         FIG. 6  to  FIG. 9  are cross-sectional diagrams illustrating different types of package structures from  FIG. 5  in accordance with one embodiment of the present invention. 
         FIG. 7  is a cross-sectional diagram illustrating the trenches filled with the adhesive and conductive layer in accordance with one embodiment of the present invention. 
         FIG. 8 to 11  and  FIG. 12-14  are cross-sectional diagrams illustrating different types of package structures from  FIGS. 5 and 10  in accordance with embodiments of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before describing the invention in detail, a brief discussion of some underlying concepts will first be provided to facilitate a complete understanding of the invention. 
       FIG. 1(   a ) to  FIG. 1(   h ) are cross-sectional diagrams illustrating the steps performing the package of a chip in accordance with the present invention. Shown in  FIG. 1(   a ), a substrate  20 , made of metal, glass, ceramic or polymer, is provided for subsequently applying an adhesive layer  22  and a conductive layer  24  on the substrate  20 . In one of the embodiments, the substrate  20 , adhesive layer  22  and conductive layer  24  are configured as a whole unity or a massive product. Alternatively, the adhesive layer  22 , made of metal, conductive material or polymer, is formed on the substrate  20  by attaching, printing, spin-coating, sputtering, non-electroplating or electroplating method. Next, the conductive layer  24  is formed on the adhesive layer  22  by the similar method such as attaching, printing, spin-coating, sputtering, non-electroplating or electroplating. 
     Depicted as  FIG. 1(   b ), a patterned film  26  and another film  28  are formed on the conductive layer  24  and  28 , respectively. Next, show in  FIG. 1(   c ), one or more metal layers  30  are filled into the patterned film  26 . The portions of the patterned film  26  and the whole film  28  are removed with the metal layer  30  as a mask. The procedure of etching or deep-etching is applied to the adhesive layer  22  and conductive layer  24  to form one or more patterned trenches  32  on the substrate  20 . The metal layer  30  is divided into the chip supporter  34  and the regions of conductive nodes  36  isolated or coupled each another, shown as  FIG. 1(   d ). 
     Next, shown as  FIG. 1(   e ), one or more chips  38  attached on each or one of the chip supporter  34  are electrically coupled to the conductive nodes  36  with multitudes of conductive wires  40  made of metal. A molding compound  42  on the adhesive layer  22  encapsulates the conductive layer  24 , metal layer  30  and the chip  38  or adhesive layer  22 . Next, shown as  FIG. 1(   f ), the substrate  20  is removed to form the structure as  FIG. 1(   g ). Along with the dash line, the dicing procedure is employed to form the units of chip  38  or chip sets, shown as the structure of chip package of  FIG. 1(   h ). 
     The structure of chip package in  FIG. 1(   h ) includes the chip supporter  34  surrounded by the conductive nodes  36  electrically isolated or coupled each another. Each of chip supporter  34  or each of conductive nodes  36  is consisted of the adhesive layer  22 , conductive layer  24  and the metal layer  30 . Each of the patterned trenches  32  is formed between the chip supporter  34  and conductive nodes  36  for separating the chip supporter  34  from conductive nodes  36 . One or more chip  38  are positioned on one of the chip supporter  34  and electrically coupled to one or more conductive nodes  36  with the conductive wires  40 . The molding compound  42  on the top surface of the adhesive layer  22  encapsulate the conductive layer  24 , metal layer  30  and chip  38  or adhesive layer  22 . 
     Before or after the dicing step as  FIG. 1(   g ), multitudes of bumps  44  are positioned under the adhesive layer  22  and exposed to the bottom side of the molding compound  42 , shown as  FIG. 2 . The bumps  44  are configured for soldering onto other exterior electrical apparatus. All of the elements exclusive of the bumps  44  are identical to ones shown in  FIG. 1(   h ) and not illustrated herein. 
       FIG. 3(   a ) to  FIG. 3(   i ) are cross-sectional diagrams illustrating the package method in accordance with one embodiment of the present invention. The steps employed shown in from  FIG. 3(   a ) to  FIG. 3(   c ) are similar as ones in from  FIG. 1(   a ) to  FIG. 1(   c ) and not illustrated for simplification. It is noted that the metal layer  30  is filled into the patterned film  26  followed by the removal of the patterned film  26  and chip  38 , in this embodiment. Shown in  FIG. 3(   d ), with the pattern-transferring method, the passivation layers  46  cover over the metal layer  30  of the conductive layer  24  and the bottom side of the substrate  20 , respectively. Next, the deep-etching is applied to the substrate  20  to form the patterned trenches  32  through the adhesive layer  22  and conductive layer  24 , and then the passivation layer  46  is removed to expose the portions of the conductive layer  24 , shown in  FIG. 3(   e ). The package structure of chip shown in  FIG. 3(   i ) is implemented through the steps shown from  FIG. 3(   f ) to  FIG. 3(   h ). The difference in structures between  FIGS. 1(   h ) and  3 ( i ) is that the partial surfaces of the conductive layer  24  are exposed to the metal layer  30  during the formation of the patterned trenches  32 . Moreover, the bumps  44  may be configured under the adhesive layer  22  before or after the dicing step. 
     In this embodiment, with the deep-etching or etching methods, the substrate  20  aforementioned may be partially removed to form multitudes of trenches  48 , shown in  FIG. 4 . Both of the adhesive layer  22  and conductive layer  24  are conformally formed into the trenches  48  and onto the substrate  20 , shown in  FIG. 5 . The package steps from  FIG. 1(   b ) to  FIG. 1(   g ) are employed to transfer patterns into the patterned film  26  and film  28  for forming multitudes of patterned trenches  32 . After the removal of the patterned film  26  and film  28 , the chip  38 , conductive wires  40  and molding compound  42  are subsequently employed onto the structure and then the substrate  20  is removed. Similarly, the dicing step is applied to the structure to form the chip or chip set  38 , shown as  FIGS. 6 and 7 . Moreover, similar as the steps from  FIG. 3(   b ) to  FIG. 3(   h ), the patterned film  26  and film  28  is pattern-transferred, followed by the formation of the passivation layer  46 . Next, the patterned trenches  32  are pattern-transferred formed followed by the removal of the passivation layer  46 , patterned film  26  and film  28 . The chip  38 , conductive wires  40  and molding compound  42  are subsequently configured followed by the removal of the substrate  20 . The dicing step are applied to the whole structure to form chip unit or chip set  38 , shown as the package structures in  FIGS. 8 and 9 . It is note that, for the package structures in  FIGS. 6 and 9 , the portions of the adhesive layer  22 , conductive layer  24  and metal layer  30  are exposed to the molding compound  42 . Alternatively, the deep-etching or etching method is first applied to the substrate  20  to form multitudes of trenches  48 , shown as  FIG. 4 . Then the adhesive layer  22  or conductive layer  24  is filled into or up the trenches  48 , shown as  FIG. 10 . Next, the package process is employed as the steps from  FIG. 1(   b ) to  FIG. 1(   g ) or from  FIG. 3(   b ) to  FIG. 3(   h ), so as to form the package structures as  FIGS. 11 and 14 . For the package structure as  FIG. 11  or  FIG. 14 , the portions of the adhesive layer  22  and conductive layer  24  are exposed to the molding compound  42 . 
     Alternatively, for all of the package processes aforementioned, the adhesive layer  22  and substrate  20  may be removed at the same time. That is, the package structure without the adhesive layer  22  may include the chip supporter  34  and multitudes of conductive nodes  36  around isolated or coupled each another. Each of the chip supporter  34  or conductive nodes  36  is consisted of the conductive layer  24  and the metal layer  30  thereon. Multitudes of patterned trenches  32  through the conductive layer  24  and metal layer  30  separate the chip supporter  34  from the conductive nodes  36 . One or more chips  38  are positioned on the chip supporter  34  and electrically coupled to the conductive nodes  36 . Before the repeated settlement of the chips  38 , the molding compound  42  may be formed on the top surface of the conductive layer  24  to encapsulate the metal layer  30  and chip  38 . Then the steps after the formation of stacked structure are implemented after the settlement of the chip  38 . 
     A package method for a package structure of chip is provided herein. During the package process, a substrate is used for supporting elements, which has one or more conductive layers with or without an adhesive layer. Moreover, the package element and patterned traces are implemented on the substrate, and then the substrate is removed. With the help of the substrate, the reliability of the package structure is improved and a good surface is beneficial for the subsequent steps to meet high requirement for a printed circuit board (PCB). With the application of the package steps, a stacked structure may be formed with repeated stacking steps to form a multi-layer PCB. Such a package structure may fit to the semiconductor package and be with efficient heat dissipation. 
     Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.