Abstract:
In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

Description:
This is a continuation of copending, commonly-assigned U.S. patent application Ser. No. 13/892,690, filed May 13, 2013, now U.S. Pat. No. 8,680,913, which is a continuation of commonly-assigned U.S. patent application Ser. No. 13/558,904, filed Jul. 26, 2012, now U.S. Pat. No. 8,441,314, which is a continuation of commonly-assigned U.S. patent application Ser. No. 13/283,841, filed Oct. 28, 2011, now U.S. Pat. No. 8,253,484, which is a continuation of commonly-assigned U.S. patent application Ser. No. 12/951,486, filed Nov. 22, 2010, now U.S. Pat. No. 8,072,260, which is a continuation of commonly-assigned U.S. patent application Ser. No. 12/625,718, filed Nov. 25, 2009, now U.S. Pat. No. 7,859,329, which is a division of commonly-assigned U.S. patent application Ser. No. 11/888,336, filed Jul. 30, 2007, now U.S. Pat. No. 7,646,237, which is a continuation of commonly-assigned U.S. patent application Ser. No. 11/282,876, filed Nov. 17, 2005, now U.S. Pat. No. 7,286,007, which is a continuation of commonly-assigned U.S. patent application Ser. No. 10/830,562, filed Apr. 22, 2004, now U.S. Pat. No. 7,075,365, each of which is hereby incorporated herein in its respective entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a configurable clock network for a programmable logic device. More particularly, this invention relates to a clock network that allows each of several clocks to be configurably routed to different portions of a programmable logic device. 
     High-speed serial signaling is becoming an increasingly important form of signaling between electronic devices. For example, Low Voltage Differential signaling (“LVDS”) has become a common form of signaling. Typically the data represent bytes of information that are being transmitted one after another. The usual definition of a byte is eight bits, but as used herein “byte” can refer to any plural number of bits such as eight bits, nine bits, ten bits, eleven bits, or fewer or more than these numbers of bits. When the data are received, one task that the receiving circuitry must typically perform is to find the boundaries between the successive bytes in the received serial bit stream. This may be referred to as “byte alignment” or “byte synchronization”. 
     In order to accommodate the use of high-speed serial signaling, electronic devices using such signaling must provide accurate high-speed clocks, which typically are provided using a loop circuit—i.e., a phase-locked loop (“PLL”) or a delay-locked loop (“DLL”). Typically, there is more than one high-speed serial channel on each device, and just as typically each loop circuit supplies the clock for more than one channel. The clock is used for serialization/deserialization, as well as for the above-described byte alignment process. Because of skew across the channels, the clock may be provided in a number of equally-distributed phases (i.e., each phase separated from its neighbors by the same phase angle—e.g., 45° of phase in the case of eight clock phases), and dynamic phase alignment (“DPA”) circuitry may be provided in each channel to select the correct phase of the clock to account for skew and keep the data properly aligned with the clock, particularly in the byte alignment portion of each channel&#39;s serial data interface. 
     Programmable logic devices (“PLDs”) are well known as shown, for example, by such references as Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. Pat. No. 6,407,576. In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide various components of what they need to produce. 
     It is known to use high-speed serial signaling with PLDs. PLDs designed for use with high-speed serial signaling typically include, in their input/output circuitry, programmable interfaces that can be used with one or more high-speed serial protocols, with the ability to programmably select the portions of the circuitry for a particular protocol. Similarly, multiple high-speed clock sources could be provided on the PLD, so that different ones of the programmable interfaces could operate at different clock speeds. However, heretofore the flexibility to assign a particular clock source to a particular channel was limited. For example, in one implementation, each channel is assigned to a particular clock source; in such a case, while different clock speeds are available, the user is constrained as to which channels can be used at which speeds. In another implementation, a plurality of clock buses could be provided to make each clock source available to each channel, with suitable multiplexing provided to connect each channel to the desired clock bus. The latter implementation requires a number of clock buses equal to the number of clock sources, as well as a plurality of—e.g., eight—multiplexers (each clock signal actually may be eight signals as described above) per channel per bus, imposing a high chip area cost. This latter implementation also has a high power cost unless provision is made to power down unused buses, and in some user implementations there may not be any unused buses—if even one channel uses a particular clock source, then the entire bus for that clock source must be powered up. 
     It would be desirable to be able to provide a programmable logic device having a clock network that allows the distribution of a plurality of clocks to a plurality of serial data channels without excessive area or power cost. 
     SUMMARY OF THE INVENTION 
     The present invention allows the distribution of a plurality of clocks to serial data channels without excessive area or power cost by providing a segmented clock bus to which all of the available clocks may be connected. Different segments of the bus may be connectable to different clocks, or the entire bus may be connected to one clock. 
     Thus, if more than one clock is being provided, then as long as each serial data channel is located near a segment on which the particular clock that it requires is provided, all channels can receive the correct clocks. Because only one bus is used, it is not necessary to consume area or power with multiple buses, although some additional circuitry will be required to achieve the bus segmentation and to allow the various clocks to be selectively connected to the bus. Although the user may be constrained when programming the device to place all channels requiring a particular clock near one another—or, more particularly, near the segment of the bus carrying that particular clock—the user has much greater flexibility in deciding which channels will use which clocks than in an arrangement where groups of channels are dedicated to particular clocks. And although the user may have less flexibility than in an implementation where a separate bus if provided for each clock to allow any channel to access any bus, the present invention has much lower power and chip area costs than in such a multiple bus limitation. 
     In accordance with this invention, there is provided a clock distribution network for use in a programmable logic device where the programmable logic device has a first number of serial data channels, and a second number of clock sources. The clock distribution network includes a clock bus having a plurality of bus segments for distributing clock signals to those channels, with each channel being connected to one of the bus segments. At each junction between adjacent bus segments, there is a respective programmable connection between those adjacent bus segments. A number of controllable inputs are provided, with each of the controllable inputs selectably connecting one of the clock sources to one of the segments of the clock bus. 
     This arrangement allows the bus segments to be connected, or not connected, in such a way as to allow the desired number of different clock sources to be connected to a desired number of different bus segments. Thus, if a user wants to use only one clock for all channels, then the respective programmable connections can all be turned on, creating one continuous clock bus, and one of the controllable inputs can be used to connect that single continuous clock bus to the desired clock source. Alternatively, the respective programmable connections can be turned off to create a number of individual clock buses equal to the number of available clock sources, and suitable ones of the controllable inputs can be turned on the connect the respective individual clock sources to the respective clock bus segments. 
     It will be understood, that between those extreme cases, a user may elect to turn on only some of the programmable connections to create more than one clock bus, but fewer clock buses than the number of clock bus segments. It will further be understood that preferably the various individual clock sources will be placed near different ones of the bus segments so that, as to each clock source, it may be connected to the bus segment to which it is adjacent if that bus segment is not connected to other bus segments, but at the same time may be connected to a larger bus including the bus segment to which it is adjacent (and which may include all, or fewer than all, of the available bus segments as described above). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
         FIG. 1  is a schematic representation of a programmable logic device that may incorporate the present invention; 
         FIG. 2  is a schematic representation of a first embodiment of a clock distribution network in accordance with the present invention; 
         FIG. 3  is a schematic representation of an alternate implementation of the embodiment of  FIG. 2 ; 
         FIG. 4  is a schematic representation of a second embodiment of a clock distribution network in accordance with the present invention; and 
         FIG. 5  is a simplified block diagram of an illustrative system employing a programmable logic device in accordance with the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention will now be described with reference to  FIGS. 1-4 . 
       FIG. 1  shows a representation of a PLD  10  that may incorporate the invention. PLD  10  includes a core logic area  11  which, as is well-known, may include look-up table-type logic or sum-of-products-type logic (i.e., product-term, or P-TERM, logic), as well as suitable interconnect structures as are well known. A region  12  of input/output circuitry preferably is provided along the edges of PLD  10 , and preferably includes at least some high-speed serial input/output channels  120 . For example, each of channels  120  may be designed as LVDS channels, or to be user-configurable as LVDS channels as well as other types of channels. It will be appreciated that to the extent that channels  120  are described herein, as an example, as LVDS channels, they may be any type of interface that requires a high-speed clock. PLD  10  preferably also includes a clock distribution network  13  in accordance with the present invention. 
     It should be noted that  FIG. 1  is purely schematic. Thus, although high-speed serial input/output channels  120  are shown in only one portion of I/O region  12 , and clock distribution network  13  is shown only adjacent that portion of I/O region  12 , in practice high-speed serial input/output channels  120  may be provided in any portion of I/O region  12 , and clock distribution network  13  may be placed adjacent anywhere it is needed to service any high-speed serial input/output channels that may be present. 
     As seen in  FIG. 2 , clock distribution network  13  preferably includes a clock channel  220  corresponding to each input/output channel  120 . In this particular embodiment, which is illustrative only, clock distribution network  13  is physically laid out as two separate portions  20 ,  21 , with two high-speed clock sources  22 ,  23  located between portions  20 ,  21 . An arrangement  240  of controllable inputs—in this example multiplexers  241 ,  242 —allows either clock source  22 ,  23  to be connected to either portion  20 ,  21  of clock distribution network  13 , including allowing either one of clock sources  22 ,  23  to be connected to both portions  20 ,  21  of clock distribution network  13 . 
     The traces  243  shown in arrangement  240  are not to scale. Preferably, arrangement  240  is matched and balanced, so that each of the plurality of conductors (not shown) making up a trace  243  (to carry the multiple clock phases discussed above) is the same length, so that skew does not develop as among the various phases and they remain in their predetermined—preferably equiangular—phase relationship. It is not necessary that one of traces  243  connecting, e.g., clock source  22  to clock distribution network portion  20  be the same length as that one of traces  243  connecting that clock source to clock distribution network portion  21 , as long as each of the conductors within each respective trace  243  is the same length as each other conductor in that respective trace. However, because it is possible that that clock source may be connected simultaneously to both clock distribution network portions  20 ,  21 , the difference, if any, in length between that one of traces  243  connecting, e.g., clock source  22  to clock distribution network portion  20 , and that one of traces  243  connecting, e.g., clock source  22  to clock distribution network portion  21 , preferably should be equivalent to a multiple of the phase angle difference between adjacent phases of that clock, so that aligned with each clock phase available in clock distribution network portion  20  is a clock phase available in clock distribution network portion  21 , even if it is not present on the corresponding conductor (the phase alignment circuitry in each input/output channel  120  will select the correct phase). 
     Preferably, in this embodiment there are also two additional clock sources  24 ,  25  located at the respective opposite ends of clock distribution network portions  20 ,  21 . Respective tristatable elements  26 ,  27  preferably are provided to isolate each respective clock source  24 ,  25  from respective clock distribution network portion  20 ,  21  if respective clock source  24 ,  25  is not being used. In  FIG. 2 , tristatable element  26  is shown as a tristatable buffer, while tristatable element  27  is shown as a tristatable multiplexer with clock source  25  connected to one input of that multiplexer and the other input of that multiplexer being unused. 
     Using multiplexers instead of tristatable buffers for this purpose would be particularly advantageous, as long as the multiplexer is tristatable, when still other additional clock sources (not shown) are provided, to provide an option to connect one of those additional clock sources to respective clock distribution network portion  20 ,  21  in place of clock  24 ,  25 , in which case the additional multiplexer inputs would be connected to the additional clock sources. It will be understood that while in  FIG. 2  (and  FIG. 3 , below), tristatable element  26  is shown as a tristatable buffer, while tristatable element  27  is shown as a tristatable multiplexer, any combination may be used, such that tristatable element  26  could be a tristatable multiplexer while tristatable element  27  could be a tristatable buffer, or elements  26 ,  27  could both be tristatable buffers or could both be tristatable multiplexers. 
     In the embodiment shown in  FIG. 2 , a tristatable buffer  200  is provided at every fourth channel  220 . Although each tristatable buffer  200  is shown within a respective channel  220 , it should be considered to be located between the channel  220  in which it is drawn and the channel  220  below. According to this arrangement, by turning on all tristatable buffers  200  in a respective clock distribution network portion  20 ,  21 , each channel  220  in that respective portion of clock distribution network  13  can be connected to the same clock source, which may be either of clock sources  22 ,  23 , or may be a respective one of clock sources  24 ,  25  depending on whether one is considering clock distribution network portion  20  or  21 . Alternatively, by turning off one of tristatable buffers  200  in one of clock distribution network portions  20 ,  21 , that portion  20 ,  21  can be segmented into two clock buses, one of which may be connected to either of clock sources  22 ,  23 , or to a respective one of clock sources  24 ,  25  depending on whether one is considering clock distribution network portion  20  or  21 . 
     Because the tristatable buffers  200  are located at every fourth channel  220  in the embodiment shown in  FIG. 2 , if the user desires to segment either of clock distribution network portions  20 ,  21  into two clock buses, the user would be limited as to where those divisions could be made, and therefore as to how many of channels  220  could be assigned to each of those two clock buses. In the alternate embodiment  33  of  FIG. 3 , however, tristatable buffers  200  are located at each channel  220 . Therefore, the user can segment each of clock network distribution portions  30 ,  31  at a point between any two channels, as may be desired. 
     It can be seen that in  FIGS. 2 and 3  that in embodiments  13 ,  33 , it may be possible in one configuration to have all channels  220  on a single clock bus connected to one of clock sources  22 ,  23 . In a second configuration, it is possible to have all of clock distribution network portion  20 ,  30  be one clock bus connected to any one of clock sources  22 ,  23 ,  24 , while also having clock distribution network portion  21 ,  31  be one clock bus connected to any one of clock sources  22 ,  23 ,  25 . In a third configuration, while clock distribution network portion  20 ,  30  may be configured as a single clock bus connected to any of clock sources  22 ,  23 ,  24 , clock distribution network portion  21 ,  31 , can be segmented into two bus segments, with one segment connected to one of clock sources  22 ,  23 , and the other segment connected to clock source  25 . In a fourth configuration, while clock distribution network portion  21 ,  31  may be configured as a single clock bus connected to any of clock sources  22 ,  23 ,  25 , clock distribution network portion  20 ,  30 , can be segmented into two bus segments, with one segment connected to one of clock sources  22 ,  23 , and the other-segment connected to clock source  24 . Finally, in a fifth configuration, each of clock distribution network portions  20 ,  30  and  21 ,  31  may be segmented into two bus segments, with one segment of clock distribution network portion  20 ,  30  connected to one of clock sources  22 ,  23 , and the other segment connected to clock source  24 , and with one segment of clock distribution network portion  21 ,  31  connected to one of clock sources  22 ,  23 , and the other segment connected to clock source  25 . 
     In the third, fourth and fifth configurations referred to in the previous paragraph, any segmentation of a clock distribution network portion  20 ,  21  would have to occur at the location one of the tristatable buffers  200 . Thus, in embodiment  13 , the smallest possible bus segment that could be created would be four channels long, either at the end closest to clock sources  22 ,  23 , or at the end closest to a respective one of clock sources  24 ,  25 , and the length of a bus segment would have to be a multiple of four channels (plus one additional channel in the segment closer to clock sources  22 ,  23 ). On the other hand, in those same configurations in embodiment  33 , while segmentation of a clock distribution network portion  30 ,  31  still would have to occur at the location one of the tristatable buffers  200 , those locations are at every channel  220 . Therefore, the smallest possible bus segment that could be created would be one channel long. The location of that one-channel-long bus still would be limited to either the end closest to clock sources  22 ,  23 , or the end closest to a respective one of clock sources  24 ,  25 . However, the bus segments could be any length. 
     Tristatable buffers  200  may be any suitable tristatable bidirectional buffer, as are known to those of ordinary skill in the art. Preferably, each tristatable buffer  200  can be controlled or programmed to pass signals in either or both directions, or to block signals in both directions. It should be noted that in the embodiments of  FIGS. 2 and 3 , any one or more of channels  220  may be unused in a particular user design (e.g., for layout reasons). In such a case, the tristatable buffers  200  bracketing that channel (in  FIG. 3 ) or bracketing a group of unused channels (in  FIG. 2 ) can be left on to pass the clock to channels beyond the skipped channel or channels. Alternatively, if the channels on opposite sides of the skipped channel or channels are receiving different clocks from opposite ends of clock distribution network  13 ,  33 , then the tristatable buffers  200  bracketing that channel (in  FIG. 3 ) or bracketing the group of unused channels (in  FIG. 2 ) preferably would be turned off so that no clock signals reach the skipped channel or channels. 
     In addition, it may be desirable to prevent the disconnected clock conductors in such a skipped zone from floating, and to force such conductors to a known state to prevent unnecessary power consumption. Therefore, each tristatable buffer  200  preferably includes circuitry (not shown) to connect a disconnected clock conductor to a fixed voltage supply. Such circuitry may be a simple transistor or passgate (not shown) that can be turned on when tristatable buffer  200  is tristated. In one embodiment, such a passgate would be provided on each end of tristatable buffer  200 , so that regardless of which side of tristatable buffer  200  the disconnected clock conductor segment was on, that clock conductor segment could be driven to a known state. Alternatively, because the disconnected clock conductor segment would be bracketed by two tristatable buffers  200 , the passgate could be provided at only one end of each tristatable buffer  200 , as long as all tristatable buffers  200  would always be oriented in the same direction (e.g., always away from central clock sources  22 ,  23 ). 
     In  FIGS. 2 and 3 , each clock source  22 ,  23 ,  24 ,  25  is shown having two outputs  34 ,  35 . Output  34  is the eight-phase clock output discussed above and connected to clock distribution network  13 ,  33  which is used for dynamic phase alignment. However, the front end of each channel  120  also requires a high-speed bit-rate clock, as well as a corresponding byte-rate clock, for serialization/deserialization as is any known high-speed serial interface. Although not part of the present invention, those two clocks are represented by the second output  35  of each of clock sources  22 ,  23 ,  24 ,  25 . Indeed, in a preferred embodiment, each output  35  may carry more than one bit-rate/byte-rate clock pair, plus a corresponding number of compensation signals. In the drawings, the hash marks on those outputs represent those multiple signals, as is conventional. 
     In the examples of  FIGS. 2 and 3 , each channel  220  is an LVDS interface, and the clocks  35  are distributed by LVDS clock trees  36  of known type, except that multiplexers  37 ,  38 ,  39 , are provided to allow selection of the appropriate clock source. For example, each of LVDS clock trees  36  could include multiple parallel trees with a multiplexer (not shown) provided at the output to each channel  220 . Note that each multiplexer  39  is shown with only one of its two inputs used. Multiplexer  39  could be used in such a configuration as a buffer (and could be replaced by a buffer (not shown)), or, as discussed above, additional clock sources (not shown) could be provided in addition to clock sources  24 ,  25 , and the selection between one of those additional clock sources and a respective one of clock sources  24 ,  25  could be made by multiplexer  39 . 
     A simplified embodiment  43  of a clock distribution network in accordance with the present invention, having portions  40 ,  41  corresponding to portions  20 ,  21  or  30 ,  31 , is shown in  FIG. 4 . This embodiment is similar to embodiment  13  in that tristatable buffers  200  are available only at every fourth channel  220 , but a similarly simplified embodiment (not shown) based on embodiment  33  may also be provided. In this simplified embodiment, only clock sources  22 ,  23  are provided, along with controllable input arrangement  240  including multiplexers  241 ,  242  to connect those clock sources to clock distribution network portions  20 ,  21 , are provided. Similarly, only multiplexers  37 ,  38  are needed to connect clock sources  22 ,  23  to LVDS clock trees  36 . In this embodiment, it is multiplexers  38  that have one unused input and could be replaced by buffers. 
     As in the embodiments of  FIGS. 2 and 3 , above, in embodiment  43  of  FIG. 4 , a channel or group of channels could be skipped and the clock signal passed through to adjacent channels. However, in this embodiment, if any one of tristatable buffers  200  is tristated, then no channel beyond that point would receive clock signal. Thus, in this embodiment a tristatable buffer  200  would be tristated only when it is desired to skip all channels beyond that point. Preferably, in such a case, the circuitry (e.g., a passgate) discussed above would be used to force the unused clock conductors to a known state to prevent unnecessary power consumption. 
     Thus it can be seen that in accordance with the present invention, a single bus can be used to conduct multiple clock sources to different channels. Because each of these sources is actually, as discussed above, multiple (e.g., eight) phases of a single clock, the invention provides a significant savings in the number of bus conductors that must be provided (e.g., a savings of eight conductors multiplied by the number of clock sources beyond one source). 
     PLD  10  according to the present invention, incorporating the clock distribution network  13 ,  33 ,  43  described above, may be used as part of a data processing system  900  shown in  FIG. 5 . Data processing system  900  may include one or more of the following components: a processor  901 ; memory  902 ; I/O circuitry  903 ; and peripheral devices  904 . These components are coupled together by a system bus  905  and are populated on a circuit board  906  which is contained in an end-user system  907 . 
     System  900  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD  10  can be used to perform a variety of different logic functions. For example, PLD  10  can be configured as a processor or controller that works in cooperation with processor  901 . PLD  10  may also be used as an arbiter for arbitrating access to a shared resources in system  900 . In yet another example, PLD  10  can be configured as an interface between processor  901  and one of the other components in system  900 . It should be noted that system  900  is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. 
     Various technologies can be used to implement PLDs  10  as described above and incorporating this invention. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention, and the present invention is limited only by the claims that follow.