Abstract:
A radio frequency (RF) power amplifier circuit comprising an RF gain stage formed on an integrated circuit (IC) chip comprising at least one field effect transistor configured for amplifying an RF signal to provide an amplified RF signal to an antenna at a given RF power level; a compensation circuit formed on the IC chip for generating a first voltage VS +  and a second voltage VS −  at respective first and second output terminals, the voltage difference therebetween corresponding to a level of temperature or process fluctuation from a given level associated with the RF gain stage; and a control circuit comprising an operational amplifier coupled to the output terminals of the compensation circuit for receiving the first and second voltages VS + , VS −  and outputting a control signal to the gate of the at least one FET of the RF gain stage to compensate the RF gain stage for the fluctuation, whereby a substantially constant power output to the antenna is maintained.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to communication devices, and more particularly, to a power amplifier circuit for a radio frequency communication device. 
     BACKGROUND OF THE INVENTION 
     Power amplifier circuits are used for amplifying radio frequency (RF) signals for transmission by a communication device. In operation, a power amplifier circuit receives an RF signal in the transmit path of the communication device, amplifies the RF signal, and provides the amplified signal to an antenna. To meet system requirements, the RF antenna power output must be maintained substantially constant. For example, existing standards for mobile cellular telephones specify 600 mW RF power output at the antenna. 
     Gallium arsenide (GaAs) MESFET (metal epitaxial semiconductor field effect transistor) devices are typically used in the amplification stage of power amplifier design. Such devices provide good performance across a wide frequency range, including the range from 1800 to 2000 MHZ. MESFET devices operated in depletion mode typically require a gate to source voltage (V gs ) less than zero volts to turn off the transistors. A bias voltage is supplied to the MESFET to establish the V gs . 
     The threshold or pinch off voltage (V th ) of a depletion mode MESFET has a negative temperature coefficient. That is, the threshold voltage becomes more negative with increasing temperature. When such a device is operating near pinch off, an increasingly more negative gate voltage will maintain a constant drain current as temperature increases. Constant drain current with respect to temperature results in lower RF gain of the amplification stage and lower power output, with increasing temperature. This is due to the MESFET transconductance, which has a negative temperature coefficient, and output conductance, which has a positive temperature coefficient. As a result, RF GaAs MESFET devices require a bias current which increases with increasing temperature to maintain constant gain and output power. 
     Conventional communications devices have used a closed loop feedback system for maintaining constant output power. In such a system, output power is detected at the antenna and a signal indicative of the output power is conveyed to a control circuit, such as a microprocessor, in the communication device. The controller than adjusts the bias current as required to maintain constant output power. Such conventional designs, however, significantly limit the performance of the power amplifier. For instance, a directional coupler is required for detecting output power at the antenna. The directional coupler causes excess power loss at the antenna. At maximum transmit power, the power loss could be as high as 1 dB or 25 percent. In addition, the circuit elements employed for detecting output power and adjusting bias current are not able to develop the negative (below 2 volts) gate to source voltage for biasing the depletion mode MESFET. 
     U.S. Pat. No. 5,724,004 entitled  VOLTAGE BIAS AND TEMPERATURE COMPENSATION CIRCUIT FOR RADIO FREQUENCY POWER AMPLIFIER  issued to Reif et al. on Mar. 3, 1998 attempts to overcome the aforementioned problems and discloses a power amplifier and bias circuit where the power amplifier includes a depletion mode MESFET for power amplification. The MESFET is biased via the bias circuit which includes a level shifter for providing the necessary gate to source voltage to the MESFET. The bias circuit output voltage varies over temperature to track the temperature variation of the MESFET in order to maintain a substantially constant RF output power. 
     Other implementations of temperature compensation circuits for power amplifiers typically utilize a gallium arsenide based differential input amplifier followed by a voltage level shifting buffer biased via current sources. However, current biasing causes the differential amplifier and level shifting circuitry to be less sensitive to bias voltage and temperature fluctuations. Therefore, temperature compensating control circuits currently in existence have a limited voltage control range, while temperature compensation occurs over a similarly limited temperature range. That is, current control circuits are operable to adjust only a certain amount of compensation to the power amplifier over a temperature range before requiring a complete termination of shut off or the power amplifier. Accordingly, a device that is both temperature and process sensitive and which performs level shifting and temperature compensation over a greater range of values is highly desired. 
     SUMMARY OF THE INVENTION 
     A radio frequency (RF) power amplifier circuit comprising an RF gain stage formed on an integrated circuit (IC) chip comprising at least one field effect transistor configured for amplifying an RF signal to provide an amplified RF signal to an antenna at a given RF power level; a compensation circuit formed on the IC chip for generating a first voltage VS +  and a second voltage VS −  at respective first and second output terminals, the voltage difference therebetween corresponding to a level of temperature or process fluctuation from a given level associated with the RF gain stage; and a control circuit comprising an operational amplifier coupled to the output terminals of the compensation circuit for receiving the first and second voltages VS + , VS −  and outputting a control signal to the gate of the at least one FET of the RF gain stage to compensate the RF gain stage for the fluctuation, whereby a substantially constant power output to the antenna is maintained. 
     There is also disclosed an RF power amplifier circuit comprising a plurality of MESFET amplifiers coupled together in a cascaded configuration for amplifying an RF signal to provide an amplified RF signal at an output terminal and at a given power; a sensing circuit comprising a MESFET amplifier having temperature characteristics similar to those of the plurality of MESFET amplifiers, the sensing circuit positioned adjacent the plurality such that the sensing circuit is affected by temperature fluctuations in the plurality of MESFETs, the sensing circuit having first and second output terminals for outputting first and second voltage signals respectively which correspond to a differential voltage indicative of the sensed difference in temperature from a given level of the plurality of MESFETs; and a control circuit comprising an operational amplifier for receiving the first and second differential voltage signals and responsive to a variable input control voltage for providing an output control signal to at least one gate electrode of the plurality of MESFETs to cause a change in output characteristics of the plurality to compensate for the sensed temperature fluctuation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a communication system in which the present invention is incorporated. 
     FIG. 2 is a block diagram of the power amplifying apparatus according to the present invention for use in the communication system of FIG.  1 . 
     FIG. 3 is a schematic diagram of the temperature and process compensation circuit as shown in FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to FIG. 1, there is shown in block diagram form a telecommunication system  10  in which the present invention is incorporated. The communication system  10  comprises a remote base station transceiver  12  for transmitting and receiving RF signals to/from a communication device  13  such as a mobile cellular telephone. Cellular telephone  13  includes an antenna  16  for transmitting and receiving signals to and from base station  12 , receiver circuit  18 , transmitter circuit  19 , demodulator  11 , and controller  30  which includes a microprocessor. The user interface  14  coupled to the controller  30  operates to communicate received information or voice information to and from the user. As is well known, the user interface typically includes a display unit, keypad, and microphone and speaker system. Power source  26  such as a conventional battery operates to provide electrical power to the cell phone  13 . The operation of the communication system is as follows. 
     In a receive mode, the cell phone  13  receives RF signals via antenna  16  and receiver  18  and converts the received signals into base band signals. Demodulator  11  coupled to receiver  18  demodulates the base band signals and recovers the data transmitted on the RF signals and provides the data to controller  30 . The controller operates to format the data into recognizable voice or information for communication to the user interface module. In transmit mode, the user interface  14  operates to transmit user input data to the controller which processes and formats the information for input to the transmitter circuit  19  for conversion into RF modulated signals. The transmitter circuit then sends modulated signals to antenna  16  for transmission to base station  12 . 
     The microprocessor controller further includes the digital to analog converter  24 . As illustrated, the controller outputs a base band signal RF  125  for input to the transmitter, as well as a control signal  128  (V CTL ) of a given voltage for producing a transmitted signal to the antenna at a given power level. 
     FIG. 2 illustrates operation of the transmitter circuit according to the present invention. Referring now to FIG. 2, there is shown a block diagram of the transmitter circuit amplifying apparatus. The transmitter includes an RF gain stage amplifying circuitry  140 , a temperature and process compensating circuit  150 , and a control circuit  170 . The amplifying circuitry  140  includes an input matching circuit  130  for receiving and providing impedance matching of the RF input signal  125  (RF in ) and power amplifier devices  142 ,  144 , and  146  comprising depletion mode MESFETs (metal epitaxial semiconductor field effect transistors). Each of the MESFETs is coupled in cascaded fashion to one another via corresponding capacitors C 4  and C 5 , while capacitor C 3  capacitively couples MESFET  142  with the input matching network  130 . The MESFETs are configured for amplifying an RF signal RF in  received at input terminal  110  for producing an amplified RF signal RF out  at output terminal  136 . An output matching network  138  is coupled at mode  137  between the output of the last stage MESFET  146  and the output terminal  136  for providing impedance matching. Inductor LI coupled between the supply voltage and node  137  acts as an RF choke. The output  136  of the RF power amplifying stage is coupled to the antenna  16  (see FIG. 1) for providing RF signals to the antenna at a given RF antenna power output level based on the input control voltage  128  (V CTL ). Each of the depletion mode MESFET amplifiers  142 ,  144 , and  146  have a drain electrode (D 1 ,D 2 ,D 3 ) coupled to a positive power supply source Vdd and a source electrode (S 1 ,S 2 ,S 3 ) coupled to a reference potential which is typically ground or zero volts. 
     As shown in FIG. 2, each of the gate electrodes G 1 , G 2 , and G 3  corresponding to the respective depletion mode MESFETs  142 ,  144 , and  146  are coupled to the output of control circuit  170 . Note that each of the MESFETs  142 ,  144  and  146  require biasing by a negative gate to source voltage. These MESFETs are operated by biasing with the gate to source voltage (V gs ) approximating a pinch off or threshold voltage (V th ) of the MESFET. Typically, the threshold or pinch off voltage of the depletion mode MESFETs have a nominal value of approximately −1.2 volts at room temperature so that in order to turn off the MESFETs, a gate to source voltage more negative than −1.2 volts must be applied. 
     As is well known in the art, the MESFETs are characterized by a temperature coefficient and are thus susceptible to temperature and process parameter variations. Such process parameters include sheet resistance and via resistance. Temperature and process parameter fluctuations result in a variation in threshold voltage which in turn results in a loss of gain as the MESFETs increase in temperature. This in turn results in an unstable output power level applied to the antenna. Since a one to one correspondence between the output power of the amplifier of the apparatus and a control voltage Vctl (reference numeral 128) is desired (i.e. a power output constant for a fixed input control signal), those temperature and process fluctuations occurring in the amplifying apparatus may cause undesirable power fluctuations for a given control voltage. The temperature and process compensation circuit and controller circuitry operate to compensate the amplifier for these fluctuations, as will be described herein below. 
     The temperature and process compensation circuit  150  operates to generate a differential signal voltage (VS + −VS − ) indicative of a fluctuation in temperature and/or process associated with the RF gain stage amplifiers. Circuit  150  in conjunction with control circuit  170  operates to simultaneously sense and then correct for both temperature and process variations. Temperature and process compensation circuit  150  comprises a gallium arsenide MESFET and a resistor network as shown in FIG.  3 . Circuit  150  is both temperature and process sensitive and located physically adjacent or next to (and in very close proximity to) the operating RFIC power amplifier  140 . Power amplifier  140  requires compensation to correct performance drift with temperature and process. The temperature and process compensating circuit  150  is located on the same MMIC as the power amplifier  140 . 
     Referring now to FIG. 3, there is shown the gallium arsenide based differential temperature and process sensing in compensation circuit  150  which comprises a depletion mode MESFET  152  which has temperature and process characteristics similar (preferably identical) to those of the MESFET power amplifiers  142 ,  144 , and  146  such that the temperature fluctuations associated with the amplifier MESFETs also affect the sensing circuit MESFET  152 . MESFET  152  has a drain electrode D coupled to a battery or regulated supply voltage V d  and gate G and source S electrodes coupled to a common node. Resistor R 1  has a first terminal end coupled to source S and a second terminal end connected to ground or reference potential. The drain electrode D is coupled to a first terminal end of resistor R 2 . Resistor R 2  is coupled at a second terminal end to resistor R 3  which is also connected to ground potential so that the resistors R 1 , R 2 , and R 3  form a voltage divider network  154 . The gallium arsenide based differential temperature sensing circuit is affected by the temperature rise (or fall) of the power amplifier  140  and by the drift and peak current due to process fluctuations. Preferably, resistors R 1  and R 3  have equal value and the periphery of the MESFET  152  in a current source configuration (operating at I dss ) is sized to create an identical voltage across R 1  and R 3  at room temperature. As shown in FIG. 3, the differential output VS +  represents the voltage drop across resistor R 1  while the voltage VS −  represents the voltage drop across R 3 . Accordingly, the circuit may be calibrated such that, at room temperature, the differential voltage is zero (VS + −VS − =0 volts). As the temperature drifts from ambient level to a positive or negative value, a differential voltage is generated across VS +  and VS − . This differential voltage is output from the temperature and process compensating circuit at respective output terminals  158  and  159  and input to the control circuit  170 . 
     Control circuit  170  comprises an operational amplifier  172  having differential inputs comprising inverting input terminal  173  and non inverting input terminal  174  for receiving each of the respective differential voltages VS −  and VS + . Variable control voltage V CTL  (reference numeral 128) from the DAC is also input to non-inverting input terminal  174  of operational amplifier  172 , while regulating voltage V REG  is input at inverting terminal  173 . A resistive network coupled to the operational amplifier  172  comprising resistors R 4 , R 5 , R 6 , R 7  and R 8  provide a mechanism for adjusting the gain of the operational amplifier to control the output control voltage signal V o  at output terminal  175  for compensating the RF gain stage of the power amplifier. As shown in FIG. 2, the control circuit comprising the operational amplifier is configured in a level shifting follower configuration utilizing the operating equations below. For example:            Let                   1     R   7         ≡       1     R   8       +     1     R   6                                    And                 let                   R   6       =     R   8       ,       R   4     =     R   5                              Therefore        :                     V   0       =       2   ·   Vi     -     V   REG     +         R   6       R   8            (       Vs   +     -   Vs   -     )                                
     V 0 =output negative voltage supplied to power amplifier MESFET Gate 
     Vi=input control voltage from DAC 0-2.7 V range (V CTL ) 
     V REG =stable reference voltage=2.7V (V REG ) 
     R 6 /R 8 =Process/Temperature Gain control controlled by the ratio of these resistor values. 
     (Vs + −Vs − )=differential voltage from the temperature compensation circuit 
     Typical values R 6  and R 8  are 20KΩ. The value of resistors R 4  and R 5  are user defined depending on the amount of gain, but are typically 10-15 kΩ. An associated gain value is approximately 2. 
     Thus, by appropriately sizing the resistor values in the controller circuit, the amount of polarity of temperature compensation can be user designed. An increasing or decreasing differential sense voltage (VS + , VS − ) operates to correct the output control voltage Vo of the operational amplifier which feeds the gate voltage of the power amplifier arrangement  140 . 
     The temperature and process compensation circuit operates to detect temperature and process parameter fluctuations over a range of temperatures from +80 to −40 degrees C (Celsius). Furthermore, compensation is not limited by the control circuitry  170 , as the operational amplifier coupled to the process and temperature sensitive circuit with differential outputs has much greater ideal properties than devices used in other control circuits. Such properties include a high common mode rejection ratio so as to minimize VS +  and VS −  fluctuations, a high power supply rejection ratio, and a greater inherent temperature stability. The operational amplifier  172  includes a supply terminal for receiving a negative voltage VEE from a negative voltage generator  160 . This permits the operational amplifier to swing to a negative voltage sufficient to switch off the cascaded MESFET amplifiers. By providing a high power supply rejection ratio, the gallium arsenide based generator, whose negative output voltage can drift with temperature, the operational amplifier is relatively immune to such fluctuations so as to not influence the output control voltage V 0  input to the gate of the MESFETs. This results in greater power stability and reduces the influence on the output power level of non amplifying, temperature dependent devices. Note also that as the control circuit is user definable, compensation may occur through either positive compensation or negative compensation by interchanging the output signals VS +  and VS −  with the respective input terminals  173  and  174  of the operational amplifier. 
     As can be seen from the foregoing, by temperature and process compensating the output voltage V out  at the output of the control circuit for feedback into the gates of each of the MESFET amplifiers. Temperature and process variations of the MESFETs may be tracked via circuit  150  and controlled via circuit  170  to maintain the RF antenna power output level at a substantially constant value over temperature and process. 
     It is to be understood that one skilled in the art may make many variations and modifications to that described herein. All such variations and modifications are intended to be included within the scope of the invention as defined in the appended claims.