Abstract:
A crystal oscillator and manufacturing method thereof are provided. The crystal oscillator includes: a semiconductor substrate; an interlayer dielectric layer located on the surface of the semiconductor substrate, an excitation plate and a positive electrode plug and a negative electrode plug being formed inside the interlayer dielectric layer, and the positive electrode plug and the negative electrode plug being located at the both sides of the excitation plate; a bottom cavity on top of the excitation plate, located between the positive electrode plug and the negative electrode plug; a vibrating crystal located on the surface of the interlayer dielectric layer, across the bottom cavity and connected with the positive electrode plug and the negative plug, wherein the vibrating crystal connects the positive electrode plug and the negative electrode plug at its both sides and besides the other both sides are the free ends and do not contact with the surrounding objects; an isolating layer located on top of the interlayer dielectric layer, a gap between the isolating layer and the vibrating crystal thus forming a top cavity; a covering layer formed on the surface of the isolating layer. The crystal oscillator is manufactured based on Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology, and can be integrated into the semiconductor chip easily and can meet the requirement for the miniature components.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims the priority of Chinese Patent Application No 201010193493.7, entitled “Crystal oscillator and manufacturing method thereof”, and filed Jun. 4, 2010, the entire disclosure of which is incorporated herein by reference. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to the manufacturing field for semiconductor apparatus, particularly to a crystal oscillator and manufacturing method thereof based on CMOS process. 
       BACKGROUND OF THE INVENTION 
       [0003]    A crystal oscillator is an important device in integrated circuit. The crystal oscillator generates regular oscillations in crystal material (common material comprise quartz and germanium etc) chiefly through active drive or passive reactance network. The accuracy of oscillations frequency is unbeatable and the oscillations are capable of being clock signals. The frequency of the clock signals is multiplied or divided through a frequency generator for further obtaining a conventional counting pulse and a clock cycle etc. 
         [0004]      FIG. 1  schematically illustrates a crystal oscillator in prior art. The crystal oscillator comprises an insulation shell  2 , an oscillating crystal  1 , supporting columns and a drive plate  3 . A closed cavity is surrounded by the insulation shell  2 . The oscillating crystal  1  is located in the closed cavity. Opposite terminals of the oscillating crystal  1  are supported by the supporting columns, and thus the oscillating crystal  1  is suspended in the closed cavity. The supporting columns may be an anode and a cathode which are connected with the oscillating crystal  1 . The drive plate  3  is arranged on one side of oscillating crystal  1  in the closed cavity for inducing the oscillating crystal  1  to generate oscillations. While working, the oscillating crystal  1  is electrified through the anode and the cathode, and then drive plate  3  is electrified to form electric field in the closed cavity. Thus subject to the electric field, the oscillating crystal  1  generates regular oscillations and outputs clock signals with fixed frequency through the anode and the cathode. 
         [0005]    Current crystal oscillators are encapsulated as discrete devices and are arranged outside a semiconductor chip, which is not beneficial to reduce the size of integrated circuit. As density of circuit element increases and area of circuit restricts, dimension of crystal oscillators is required higher and higher. Although MEMS (Micro-Electro-Mechanical Systems, MEMS) technology is developed and mechanical electrical devices with micron grade and submicron grade have been fabricated, current semiconductor chip manufacturing process bases on CMOS process, and crystal oscillators and semiconductor chip are difficult to be fabricated uniformly only depending on MEMS technology. Therefore, a crystal oscillator and manufacturing method of the crystal oscillator which base on CMOS process is urgently demanded. 
       SUMMARY OF THE INVENTION 
       [0006]    An object of the present invention is to provide a crystal oscillator and manufacturing method of the crystal oscillator, wherein the manufacturing method is compatible with CMOS process and crystal oscillator is easy to fabricate in a semiconductor chip. 
         [0007]    To achieve the object, the present invention provides a method for manufacturing a crystal oscillator. The method comprises following steps. A substrate is provided. An interlayer dielectric layer is formed on the substrate, and forms a drive plate therein. An anode plug and a cathode plug are provided at opposite sides of the drive plat, respectively. A part of the interlayer dielectric layer, which is located between the anode plug and the cathode plug, above the drive plate, is etched to form a groove. A first sacrifice layer is formed by filling the groove. An oscillating beam is formed on the interlayer dielectric layer and the first sacrifice layer, traversing the groove, opposite sides of the oscillating beam being connected to the anode plug and the cathode plug respectively, another opposite sides of the oscillating beam exposing the interlayer dielectric layer. A second sacrifice layer is formed on the oscillating beam. The second sacrifice layer connects with the first sacrifice layer. An isolating layer is formed on the second sacrifice layer. The isolating layer is etched for forming through holes. The through holes expose the second sacrifice layer. The first sacrifice layer and the second sacrifice layer are removed through the through holes. A covering layer is formed on the isolating layer for covering the through holes. 
         [0008]    Optionally, a bottom of the groove is spaced apart from the drive plate by a part of the interlayer dielectric layer. 
         [0009]    Optionally, side walls of the groove are respectively spaced apart from the anode plug and the cathode plug by a part of the interlayer dielectric layer. 
         [0010]    Optionally, depth of the groove ranges from 0.5 μm to 4 μm and width of the groove ranges from 5 μm to 50 μm. 
         [0011]    Optionally, the oscillating beam is made of poly silicon germanium. 
         [0012]    Optionally, thickness of the oscillating beam ranges from 3 μm to 15 μm. 
         [0013]    Optionally, thickness of the second sacrifice layer ranges from 2 μm to 20 μm. 
         [0014]    Optionally, the first sacrifice layer and the second sacrifice layer are made of amorphous carbon. 
         [0015]    Optionally, removing the first sacrifice layer and the second sacrifice layer comprises introducing oxygen to the through holes at a high temperature for oxidizing the amorphous carbon to an oxide in gaseous state. 
         [0016]    Optionally, removing the first sacrifice layer and the second sacrifice layer are implemented at a high temperature which ranges from 350 centigrade to 450 centigrade. 
         [0017]    A crystal oscillator comprises a substrate, an interlayer dielectric layer, an oscillating beam, an isolating layer and a covering layer. The interlayer dielectric layer is located on the substrate and forms a drive plate therein. An anode plug and a cathode plug are provided at opposite sides of the drive plate, respectively. A lower cavity is defined between the anode plug and the cathode plug and above the drive plate. The oscillating beam is located on interlayer dielectric layer and traverses the lower cavity for contacting and supporting the anode plug and the cathode plug. The oscillating beam is free relative to ambient except connection with the anode plug and the cathode plug. The isolating layer is located above the interlayer dielectric layer. An upper cavity is formed between the isolating layer and the oscillating beam. The covering layer is formed on the isolating layer. 
         [0018]    Optionally, a bottom of the lower cavity is spaced apart from the drive plate by a part of the interlayer dielectric layer. 
         [0019]    Optionally, depth of the lower cavity ranges from 0.5 μm to 4 μm and width of the lower cavity ranges from 5 μm to 50 μm. 
         [0020]    Optionally, the oscillating beam is made of poly silicon germanium. 
         [0021]    Optionally, thickness of the oscillating beam ranges from 3 μm to 15 μm. 
         [0022]    Optionally, the upper cavity between the isolating layer and the oscillating beam ranges from 2 μm to 20 μm. 
         [0023]    The manufacturing method of the crystal oscillator of present invention is compatible with CMOS process. Dimension of the crystal oscillator of present invention is reduced, thereby reducing size of apparatus, correspondingly. The crystal oscillator of present invention is simple in structure, and is easily fabricated and integrated in a semiconductor chip. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    The above-mentioned object, characteristics and advantages will be clearer through the detailed description of the preferred embodiments in accordance with the present invention taken in conjunction with the accompanying drawings. The same components in the drawings are denoted with the same reference signs. The drawings, not precisely plotted according to the scale, are used to show the major ideas of the present invention. In the accompanying drawings, the thicknesses of layers and regions are scaled up for the sake of clarity. 
           [0025]      FIG. 1  schematically illustrates a crystal oscillator in prior art; 
           [0026]      FIG. 2  schematically illustrates a flow chart of a method for manufacturing the crystal oscillator of the present invention; 
           [0027]      FIGS. 3-12  schematically illustrate a method for manufacturing the crystal oscillator according to an embodiment of the present invention; 
           [0028]      FIG. 7  is a cross section view taken along line  7 - 7  of  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0029]    Current oscillating crystals in crystal oscillators mostly adopt quartz and germanium. Since the quartz and germanium is not compatible with CMOS process, the crystal oscillators are fabricated according to MEMS technology or mechanical processing as discrete devices and are arranged outside a semiconductor chip. The method for manufacturing the crystal oscillator and material of crystal oscillator of present invention are compatible with CMOS process, leading to easy integration of the crystal oscillator into a semiconductor chip, thereby meeting the requirement of reduction in the size. 
         [0030]      FIG. 2  schematically illustrates a flow chart of a method for manufacturing the crystal oscillator of the present invention. The method comprises following steps. 
         [0031]    S 101 , a substrate is provided. An interlayer dielectric layer is formed on the substrate, and forms a drive plate therein. An anode plug and a cathode plug are provided at opposite sides of the drive plat, respectively. The plugs and the drive plate may be fabricated by conventional standard CMOS interconnection process. Interconnection metal is filled in contact holes to form the plugs. The drive plate may be a conductor, being formed by etching interconnection metal layer. 
         [0032]    S 102 , a part of the interlayer dielectric layer, which is located between the anode plug and the cathode plug, above the drive plate, is etched to form a groove. A first sacrifice layer is formed by filling the groove. 
         [0033]    S 103 , an oscillating beam is formed on the interlayer dielectric layer and the first sacrifice layer, traversing the groove, opposite sides of the oscillating beam being connected to the anode plug and the cathode plug respectively, another opposite sides of the oscillating beam exposing the interlayer dielectric layer. 
         [0034]    S 104 , a second sacrifice layer is formed on the oscillating beam. An isolating layer is formed on the second sacrifice layer. 
         [0035]    S 105 , through holes are formed by etching the isolating layer, exposing the surface of the second sacrifice layer. The first sacrifice layer and the second sacrifice layer are removed through the through holes. 
         [0036]    After removing the first sacrifice layer and the second sacrifice layer, a cavity receiving the oscillating beam is formed in the interior of the isolating layer. Bottom of the oscillating beam corresponds to the groove and the drive plate under the groove. Except opposite terminals of the oscillating beam are connected with the anode plug and the cathode plug, other parts of the oscillating beam are in suspension state, namely being free terminals, not contacting other object. 
         [0037]    S 106 , a covering layer is formed on the isolating layer. The covering layer may plug up the through holes, thereby spacing the oscillating beam from outside. 
         [0038]    The crystal oscillator of the present invention and the method for manufacturing the crystal oscillator will be further described with following embodiments. 
         [0039]    Referring to  FIG. 3 , a substrate  100  is provided. The substrate  100  may form metal interconnection or other semiconductor devices therein (not shown). An interlayer dielectric layer  101  is formed on the substrate  100 . The interlayer dielectric layer  101  forms a drive plate  200 , an anode plug  201  and a cathode plug  202  therein. 
         [0040]    The drive plate  200 , the anode plug  201  and the cathode plug  202  are formed in the interlayer dielectric layer  101  by metal interconnection process. The method comprises following steps. A first interlayer dielectric layer (not labeled) is formed on the substrate  100 . An interconnection metal layer is formed on the first interlayer dielectric layer, and is patterned to form the drive plate  200 . A second interlayer dielectric layer (not labeled) is formed on the first interlayer dielectric layer and the drive plate  200 . The first interlayer dielectric layer and the second interlayer dielectric layer are etched until the substrate  100  is exposed, defining two contact holes (not labeled) through the substrate  100 . The contact holes are located on two sides of the drive plate and do not contact the drive plate  200 . The anode plug  201  and the cathode plug  202  are formed by filling the contact holes with interconnection metal. The interlayer dielectric layer  101 , which includes the first interlayer dielectric layer and the second interlayer dielectric layer with the anode plug  201  and the cathode plug  202  therein, is completed. Thickness of the second interlayer dielectric layer approximately equals to the distance between the drive plate  200  and a top of the dielectric layer  101 . A groove will be defined by the second interlayer dielectric layer in following step, and has a maximum depth depending on thickness of the second interlayer dielectric layer, and a maximum width of the groove depending on space between the anode plug  201  and the cathode plug  202 . 
         [0041]    In the embodiment, the thickness of the second interlayer dielectric layer ranges from 1 μm to 5.5 μm, and the space between the anode plug  201  and the cathode plug  202  ranges from 10 μm to 55 μm. 
         [0042]    In the embodiment, the first interlayer dielectric layer and the second interlayer dielectric layer are conventional dielectric material, such as silicon oxide and silicon nitride etc. To take silicon oxide for an example in the embodiment, the first interlayer dielectric layer and the second interlayer dielectric layer may be formed by CVD (Chemical Vapor Deposition, CVD) process. The drive plate  200  is formed by etching an interconnection metal layer. The anode plug  201  and the cathode plug  202  are made of interconnection metal material. Tungsten, aluminum, cuprum and other conventional metal material may be used for being compatible with CMOS process. 
         [0043]    According to the prior art, the drive plate  200  is used for forming electric field which induces the oscillating beam to oscillate. Thus the drive plate  200  may be metal material or other conductive material. The drive plate  200  may be fabricated by other conventional COMS process. As a common knowledge, a person skilled in the art should easily deduce specific method for manufacturing the drive plate  200 . It may be redundant to describe details here. 
         [0044]    Referring to  FIG. 4 , a part of the interlayer dielectric layer  101 , which is located between the anode plug  201  and the cathode plug  202  and above the drive plate, is etched to form a groove  300 . The groove  300  is filled to form a sacrifice layer  400 . A part of the sacrifice layer  400 , which overflows the groove  300 , is removed by planarization process. The planarization process comprises following steps. A photoresist is deposited on the interlayer dielectric layer  101 . The photoresist is patterned according to the groove  300 . The patterned photoresist serving as a hardmask, the interlayer dielectric layer  101  is etched by plasma etching process for forming the groove  300 . The groove  300  is filled with the first sacrifice layer  400 . The interlayer dielectric layer  101  and the sacrifice layer  400  are planarized by CMP (Chemical-Mechanical Polishing, CMP) process after the filling process is finished. 
         [0045]    According to one embodiment, the drive plate  200  is exposed directly in a bottom of the groove  300 . According to a preferred embodiment, in order to protect the drive plate  200  in following process, the bottom of the groove  300  is spaced apart from the drive plate  200  by a part of interlayer dielectric layer. Thus depth of the groove  300  is lower than the thickness of the second interlayer dielectric layer. Side walls of the groove  300  may directly expose the anode plug  201  or the cathode plug  202 . In order to protect the anode plug  201  and the cathode plug  202  in following process, width of the groove may lower than the distance between the anode plug  201  and the cathode plug  202 . In the embodiment, while etching the groove, the width of the groove is controlled by regulating the photoresist pattern, and the depth of groove is controlled by regulating the etching time. The depth of the groove  300  ranges from 0.5 μm to 5 μm and the width of the groove  300  ranges from 5 μm to 50 μm. The bottom of the groove  300  is spaced apart from the drive plate  200  by the interlayer dielectric layer whose thickness is 0.5 μm. 
         [0046]    The first sacrifice layer  400  is used for supporting the oscillating beam in following process of forming the oscillating beam. Since the first sacrifice layer  400  will be removed finally, the material of the sacrifice layer  400  should be selected from material which is easy to remove. Preferably, the material of the first sacrifice layer  400  is selected from material with high etching rate compared with the interlayer dielectric layer  101  and oscillating beam, and thus other substance never want to be removed will be protected when removing the first sacrifice layer  400 . For example, the first sacrifice layer  400  may be metal or metal oxide which is easy to be wet etched and deposited in the groove  300  by metal plating method (on this condition, the bottom and the side walls of the groove  300  must be spaced apart from the drive plate  200 , the anode plug  201  and the cathode plug  202  by a part of interlayer dielectric layer), such as aluminum or cuprum etc. Or, the first sacrifice layer  400  may be material which is easy to be gasified and deposited on the groove  300  by CVD process, such as amorphous carbon. In the embodiment, the amorphous carbon is used as the sacrifice layer, which has following advantages. CVD process is compatible with CMOS process. The amorphous carbon fabricated by CVD is amorphous carbon which is comparatively compact and may be oxidized into carbon dioxide at a lower heating temperature (generally not exceed 500 centigrade), thus easily being oxidized to remove without remains and not effecting other parts. 
         [0047]    Referring to  FIG. 5 , a poly layer  102  is deposited on the interlayer dielectric layer  101  and the first sacrifice layer  400 . In the embodiment, the poly layer  102  is poly silicon germanium, being fabricated by CVD. Thickness of the poly layer  102  ranges 3 μm to 15 μm. Poly silicon germanium is easy to generate regular oscillations when being induced (such as being electrified), which is the same as quartz. Poly silicon germanium is a conventional semiconductor material also. The oscillating beam in present invention is made of poly silicon germanium, being compatible with CMOS process, reducing process lost. 
         [0048]    Referring to  FIG. 6 , the poly layer  102  is etched to form an oscillating beam  203 . Position of the oscillating beam  203  corresponds to the groove  300  and the drive plate  200  under the groove  300 . The oscillating beam  203  traverses the groove  300  and two terminals of the oscillating beam  203  connect the anode plug  201  and the cathode plug  202 . Since the oscillating beam  203  achieves longitudinal oscillation, cavities should be formed above and under the oscillating beam  203  respectively, and two sides of the oscillating beam  203  not connected with electrodes are free. That is, the oscillating beam is free relative to ambient except connection with the anode plug and the cathode plug. In order to remove the first sacrifice layer  400  in the groove  300  located under the oscillating beam  203  and form a low cavity, the oscillating beam  203  does not cover over the entire groove  300 . The two sides of the oscillating beam  203  which are free expose a part of the first sacrifice layer  400  in the groove  300 . 
         [0049]    Referring to  FIG. 6  and  FIG. 7 , as an embodiment of the present invention, the oscillating beam  203  is rectangle which has long side and short side. The oscillating beam  203  traverses the groove  300  along the long side direction. The oscillating beam  203  covers and connects the anode plug  201  and the cathode plug  202 . The oscillating beam  203  exposes the first sacrifice layer  400  along the short side direction. The oscillating beam  203  is equally divided by the line between the anode plug  201  and the cathode plug  202 . 
         [0050]    The oscillating beam  203  may cover over the groove  300 . When removing the first sacrifice layer  400  under the oscillating beam  203 , a part of the oscillating beam  203  is etched to form an opening and the first sacrifice layer  400  is removed through the opening. 
         [0051]    Referring to  FIG. 8 , a second sacrifice layer  401  is formed on the oscillating beam  203  and the interlayer dielectric layer  101 . The second sacrifice layer  401  is etched to surround the oscillating beam  203  and to connect the first sacrifice layer  400 . Further, in the embodiment, since the oscillating beam  203  does not cover over the groove  300 , the second sacrifice layer  401  covers the exposed first sacrifice layer  400  or covers a part of the exposed first sacrifice layer  400  or exceeds the exposed first sacrifice layer  400 , whereby the first sacrifice layer  400  and the second sacrifice layer  401  are connected together to surround the oscillating beam  203 . When the first sacrifice layer  400  and the second sacrifice layer  401  are removed, except the oscillating beam  203  are connected with the anode plug  201  and the cathode plug  202 , other parts of the oscillating beam  203  do not contact other objects, namely forming free terminals. 
         [0052]    As stated above, since the oscillating beam  203  achieves longitudinal oscillation, an upper cavity should be formed above the oscillating beam  203 , and thus the thickness of the second sacrifice layer  401  is the space of the upper cavity above the oscillating beam  203 . The lower cavity and the upper cavity compose a cavity for receiving the oscillating beam  203 . To simplify the processes, the first sacrifice layer  400  and the second sacrifice layer  401  are made of the same material which is easy to be removed in the embodiment. Please refer to the descriptions of the first sacrifice layer for detail descriptions. The thickness of the second sacrifice layer ranges from 2 μm to 20 μm. 
         [0053]    Referring to  FIG. 9 , an isolating layer  103  is formed on the second sacrifice layer  401 . The isolating layer  103  is used for insulating and protecting the oscillating beam  203  therein. The isolating layer  103  is made of silicon oxide or silicon nitride. To simplify the process, the isolating layer  103  and the interlayer dielectric layer  101  adopt silicon oxide, being deposited by CVD process. The oscillating beam  203 , the second sacrifice layer  401  and the isolating layer  103  are orderly arranged from inside to outside. 
         [0054]    Referring to  FIG. 10 , several through holes  500  exposing the second sacrifice layer  40  are formed in the isolating layer  103 . The through holes  500  are formed by plasma etching process. Gases and liquids are introduced through the through holes  500  to remove the first sacrifice layer  400  and the second sacrifice layer  401 . Depth to width ratio should not be too big, which may avoid plugging up difficultly in deposit process. The depth to width ratio should not be too small, which may influence the effect of removing the sacrifice layers. The depth to width ratio should be adjusted according to the material and removing method of the sacrifice layers. A person skilled in the art may adjust according to the principles mentioned above and a preferred range is obtained by limited experiments. The depth to width ratio of the through holes ranges from 3 to 5. 
         [0055]    Referring to  FIG. 11 , a removing material is introduced through the through holes  500  to remove the first sacrifice layer  400  and the second sacrifice layer  401 . 
         [0056]    Specifically, as stated above, if the first sacrifice layer  400  and the second sacrifice layer  401  are aluminum or cuprum, the removing material is phosphorous acid. In the embodiment, since the first sacrifice layer  400  and the second sacrifice layer  401  are compact amorphous carbon which is fabricated according CVD process, the removing material is oxygen and heating temperature ranges from  350  centigrade to  450  centigrade. At the temperature, the compact amorphous carbon will not burn intensely, but will be oxidized to carbon dioxide gas. The carbon dioxide gas is expelled from the through holes and the sacrifice layers are removed, thereby protecting other parts of the apparatus. After the first sacrifice layer  400  is removed, the oscillating beam  203  is arranged in a cavum structure being within the isolating layer  103 . 
         [0057]    Referring to  FIG. 12 , a covering layer  104  is formed on the isolating layer  103 . The covering layer  104  may be formed by CVD process. If the depth to width ratio of through holes  500  is small enough, the covering layer  104  would easy to plug up the through holes  500  and would not extend through the cavum structure being within the isolating layer  103 . To simplify the processes, the covering layer  104  is made of silicon oxide. 
         [0058]    A crystal oscillator of the present invention is formed according to the processes stated above. Referring to  FIG. 12 , the crystal oscillator comprises a substrate  100 , an interlayer dielectric layer  101 , a lower cavity, an oscillating beam  203 , an isolating layer  103  and a covering layer  104 . The interlayer dielectric layer  101  is located on the substrate  100 . The interlayer dielectric layer  101  forms a drive plate  200  therein, and an anode plug  201  and a cathode plug  202  at opposite sides of the drive plat respectively. The lower cavity is located between the anode plug  201  and the cathode plug  202 , above the drive plate  200 . The oscillating beam  203  is located on the top of interlayer dielectric layer  101  and traverses the lower cavity. The oscillating beam  203  is connected with the anode plug  201  and the cathode plug  202 . The oscillating beam  203  is free relative to ambient, except connection with the anode plug  201  and the cathode plug  202 . The isolating layer  103  is located above the interlayer dielectric layer  101 . An upper cavity is formed by spaces between the isolating layer  103  and the oscillating beam  203 . The covering layer  104  is formed on the isolating layer  103 . 
         [0059]    While working, the oscillating beam  203  establishes a current therein through the anode plug  201  and the cathode plug  202 . For example, the cathode plug  202  is grounded and a positive voltage is applied to the anode plug  201 . The potential of the drive plate  200  is adjusted to form electric field in the closed cavity, thereby inducing the oscillating beam  203  to generate regular longitudinal oscillations. Oscillations frequency is determined by the material of the oscillating beam  203 . Size of the upper cavity and the lower cavity located on two sides of the oscillating beam  203  is relevant to the thickness of the first sacrifice layer and second sacrifice layer. As known by a person skilled in the art, for the oscillating beam oscillates stably, the size of the layers may be determined according to actual conditions. The present invention is not limited by the specific implementations disclosed hereinafter. 
         [0060]    The crystal oscillator and the method for manufacturing the crystal oscillator of the present invention, especially selection of material and forming processes, are compatible with CMOS process. Thus the crystal oscillator is easily integrated in a semiconductor chip and fabricated together with the semiconductor chip, thereby reducing the fabrication cost of integrated circuit, improving density of the apparatus and meeting the requirement of reduction in the size. 
         [0061]    Apparently, those skilled in the art should recognize that various variations and modifications can be made without departing from the spirit and scope of the present invention. Therefore, if these variations and modifications fall into the scope defined by the claims of the present invention and its equivalents, then the present invention intends to cover these variations and modifications.