Abstract:
A Column Address Strobe (CAS) latency control circuit for a SDRAM and a layout of the same allows an adequate CAS latency operation allowance at a high operation frequency. The SDRAM includes a plurality of banks each having ‘n’ main amplification units, ‘n’ bit data buses disposed between the plurality of banks each shared by respective main amplification units, ‘n’ CAS latency control circuits disposed concentrated central to the data buses one to one matched to the data buses, ‘n’ DQ blocks disposed connected to outputs of respective CAS latency control circuits in lengths different from one another, and a clock buffer for applying a clock signal to the CAS latency control circuits.

Description:
This application is a continuation-in-part application of application Ser. No. 09/374,765 filed Aug. 16, 1999, now U.S. Pat. No. 6,125,064 whose entire disclosure is incorporated herein by reference thereof. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a memory device, and more particularly to a Column Address Strobe (CAS) latency control circuit for a memory device. 
     2. Background of the Related Art 
     In general, Dynamic Random Access Memories (DRAMs) are composed of capacitors and transistors, and are widely used as highly integrated semiconductor memories. However, because the operation of a DRAM is controlled by delaying command signals (RASB and CASB, etc.) and data therein is read in response to a Y-address signal, the DRAM has the disadvantage that data read time is long and slow. Consequently, Synchronous DRAMs (SDRAMs), have recently been developed with increased read and write speeds. 
     A related art CAS latency control circuit for a SDRAM will be described with reference to the attached drawings. Referring to FIG. 1, a related art SDRAM includes four banks BANK 0 , BANK 1 , BANK 2 , and BANK 3 , each having n main amplification units MA 0 i-MA 0 j, MA 1 i-MA 1 j, MA 2 i-MA 2 j, and MA 3 i-MA 3 j, which are secondary amplifier circuits. Each bank is further coupled to a n-bit data bus, and each of the main amplification units MA 0 i-MA 0 j, MA 1 i-MA 1 j, MA 2 i-MA 2 j, and MA 3 i-MA 3 j in each of the banks share data bus DATAi-DATAj of the same number in common. The SDRAM further includes n CAS latency control circuits CLCCi-CLCCj which are matched one to one to the data buses, such that the (i)th CAS latency control circuits share the (i)th data bus. 
     Chip pads in a chip are also arranged at particular locations which correspond to locations of input/output pins which are fixed in a general standard SDRAM. In FIG. 1, clock pads for clock inputs are arranged at a central portion of the chip, and DQ blocks DQi-DQj, which include data output buffers and pads, are positioned in a spread formation at the right side of the chip near BANK 2  and BANK 3 . They are sequenced in the order corresponding to locations of data pins. Therefore, since each of the n DQ blocks DQi-DQj includes a data buffer and an input/output pad, the DQ blocks DQi-DQj are positioned at particular locations, and the n CAS latency control circuits CLCCi-CLCCj are positioned at locations adjacent to the DQ blocks. Further, there is a one to one correspondence between the CAS latency control circuits and the DQ blocks, so that outputs of the CAS latency control circuits CLCCi-CLCCj are connected to respective DQ blocks DQi-DQj. Additionally, the positioning of the CAS latency control circuits and their respective DQ blocks is such that the distance between them is kept relatively small. 
     A QCLK buffer is positioned at a location adjacent to the clock pad for providing a clock signal to the CAS latency control circuits CLCCi-CLCCj, and clock signal QCLK connection lines are connected to respective CAS latency control circuits CLCCi-CLCCj. 
     Referring to FIG. 2, the related art CAS latency control circuit for a SDRAM is provided with three latches  2 ,  3 , and  4 , and a controlling circuit unit  1  for controlling the three latches  2 ,  3 , and  4 . Thus, controlling circuit unit  1  receives a clock signal QCLK for forwarding data, and provides control signals con 1 , con 2 , and con 3  for controlling respective latches  2 ,  3 , and  4 . 
     First latch  2  either forwards or latches input data depending on the control signal con 3  from the controlling circuit  1 . Second latch  3  either forwards or latches the data from the first latch  2  according to the control signal con 2  from the controlling circuit unit  1 . Third latch  4  either forwards the data from the second latch  3  to an output buffer or latches the data from the second latch  3  according to the control signal con 1  from the controlling circuit unit  1 . 
     Referring to FIG. 3, each of the latches  2 ,  3 , and  4  is provided with a first inverter  6  which inverts a control signal con 3 , con 2 , con 1  from the controlling circuit unit  1 . A first control inverter  5  passes data D when the control signal con 1 , con 2 , or con 3  is “low” in response to the control signal con 3 , con 2 , or con 1  and the signal from the first inverter  6 . This is in the open condition of the latch- A second inverter  8  inverts a signal from the first control inverter  5 , and a second control inverter  7  latches a data signal from the second inverter  8  when the control signal con 1 , con 2 , or con 3  is “high” in response to the control signal con 3 , con 2 , or con 1  and the signal from the first inverter  6 . 
     Referring to FIG. 4, the control inverter  5  or  7  in each of the latches is provided with first and second PMOS transistors  9  and  10 , and first and second NMOS transistors  11  and  12  between a constant supply voltage terminal and a ground voltage terminal. The second PMOS transistor  10  and the first NMOS transistor  11  receive a data signal D in  at gates thereof, and the first PMOS  9  receives the control signal con 3 , con 2 , or con 1  from the controlling circuit unit  1  or a signal from the first inverter  6  at a gate thereof. The second NMOS transistor  12  receives the control signal con 3 , con 2 , or con 1  from the controlling circuit unit  1  or a signal from the first inverter  6  at a gate thereof, and an output terminal  13  is provided at a node of the second PMOS transistor  10  and the first NMOS transistor  11 . 
     FIG. 5 illustrates a first timing diagram of the related art CAS latency control circuit operation, FIG. 6 illustrates a second timing diagram of the related art CAS latency control circuit operation, FIG. 7 illustrates a third timing diagram of the related art CAS latency control circuit operation, and FIG. 8 illustrates a fourth timing diagram of the related art CAS latency control circuit operation. 
     Referring to FIG. 5, the controlling circuit unit  1  provides control signals con 1 , con 2 , and con 3  all at “low” at a first rising edge of a clock signal QCLK, so that all the latches  2 ,  3 , and  4  do not latch data, but instead directly bypass the data. Therefore, the output data Dout is provided at a second rising edge of the clock signal QCLK. 
     Referring to FIG. 6, the controlling circuit unit  1  provides a control signal con 1  to be applied to the third latch  4  at “high” and control signals con 2  and con 3  to be applied to the first and second latches  2  and  3  respectively at “low” at a first rising edge of a clock signal QCLK, so that the first and second latches do not latch the data. Instead, the data is passed directly to the third latch, which receives the data. Next, the controlling circuit unit  1  controls the control signal con 1  to transition from “high” to “low” at a second rising edge of the clock signal, so that the data passes through the third latch  4  and proceeds toward the data output buffer. The controlling circuit unit  1  then transitions the control signal con 1  from “low” to “high” again before a third rising edge of the clock signal, so that the data is latched at the third latch. 
     Referring to FIG. 7, the controlling circuit unit  1  holds the control signal con 3  low and control signals con 1  and con 2  high in synchronization with the clock signal QCLK. It then transitions the control signal con 1  from high to low after a second rising edge of the clock signal QCLK, and after a prescribed time period, from low to high again. The controlling circuit unit  1  causes the control signal con 2  to transition from high to low when the control signal con 1  transitions from low to high, and then from low to high at a third rising edge of the clock signal. Accordingly, the control signals con 1  and con 2  repeat the aforementioned process in a fourth rising edge of the clock signal. As the control signal is held low, the data passes through the first latch  2  to the second latch  3 , and passes through the second latch  3  to the third latch  4  when the control signal con 2  transitions to low. 
     In this instance, as the control signal con 2  transitions to high again, the second latch  3  latches and holds the data provided to the third latch  4  until the control signal con 2  transitions to low, again. And, when the control signal con 1  transitions to low in a second cycle, the third latch  4  forwards the data toward the data output buffer, and when the control signal con 1  transitions to high again, latches the data until the control signal con 1  transitions to low and holds the data until the next cycle. 
     Referring to FIG. 8, the controlling circuit unit  1  maintains all of the control signals con 1 , con 2 , and con 3  at a high level until a second rising edge of the external clock signal QCLK, when the control signals con 1 , con 2 , and con 3  are transited to low in sequence. Therefore, when a pertinent signal transitions to low, the first latch  2  provides the latched data to the second latch  3 , the second latch  3  provides to the third latch  4 , and the third latch  4  provides to the data output buffer. Alternatively, when a pertinent control signal transitions from low to high, the data is latched. Thus, as data is provided depending on a user&#39;s selection of a mode of the first to fourth CAS latencies, the SDRAM operates faster than a general DRAM. 
     However, the related art CAS latency control circuit for a SRAM has various problems. For example, passing data through all the series connected latches, regardless of the cases of CAS latency, results in an unnecessary data transmission delay. Particularly, as the data passes directly through the first, second, and third latches without being latched by any of the latches, as in the case of the first CAS latency, or latched only by the third latch as in the case of second CAS latency, data transmission delay becomes a problem. 
     Additionally, the aforementioned related art CAS latency control circuit for a SDRAM has various problems. For example, the layout of the related art CAS latency control circuits and corresponding DQ blocks on a chip causes a clock signal QCLK skew between CAS latency control circuits CLCC located close to a clock buffer and CAS latency control circuit CLCC located far from the clock buffer. 
     Additionally, the distortion of data rates increases between reading of the first and second banks BANK 0  and BANK 1  and reading of the third and fourth banks BANK 2  and BANK 3 . This is illustrated in the timing diagram of FIG. 9, which shows a case in which there are no clock signal QCLK and data skews in operation of a related art CAS latency, and the timing diagram of FIG. 10, which illustrates a data output timing diagram in a case in which there are clock signal QCLK and data skews in operation of a related art CAS latency. In these figures, tCK denotes a clock cycle, tS denotes a CAS latency latch set up time, tH denotes a CAS latency hold time, skew 1  denotes a clock skew in each CAS latency control circuit, and skew 2  denotes data skew for each bank. If there were no QCLK and data skews, a CAS latency operation would have an adequate latch allowance. Because there are clock signal QCLK and data skews, however, the CAS latency operation has inadequate allowances tS and tH, and particularly, the CAS latency operation becomes difficult at a high frequency due to shorter clock cycle of the higher frequency, which results in a greater QCLK and data skews. 
     The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background. 
     SUMMARY OF THE INVENTION 
     The present invention substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
     An object of the present invention is to prevent the passing of data through unnecessary latches, thus preventing unnecessary data delay. 
     Another object of the present invention is to improve the operational speed. 
     Another object of the present invention is to minimizes the clock signal QCLK and data skews given to each CAS latency control circuits. 
     To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the SDRAM includes a plurality of banks each having ‘n’ main amplification units, ‘n’ bit data buses disposed between the plurality of banks each shared by respective main amplification units, ‘n’ CAS latency control circuits disposed concentrated central to the data buses one to one matched to the data buses, ‘n’ DQ blocks disposed connected to outputs of respective CAS latency control circuits in lengths different from one another, and a clock buffer for applying a clock signal to the CAS latency control circuits. 
     In order to achieve at least the above-described objects of the present invention in a whole or in parts, there is provided memory device that includes a plurality of memory banks, each bank having a plurality of main amplifiers, each main amplifier amplifying output signals from said memory bank, a plurality of data buses arranged between the plurality of banks, each shared by respective main amplification units, a latency controller concentrated in an area central to the data buses and one to one matched to the data buses to receive signals from said plurality of data buses, a plurality of DQ circuits coupled to receive the outputs of respective CAS latency control circuits, and a clock buffer for applying a clock signal to the CAS latency controller, wherein the distance of each of said plurality of DQ circuits to the CAS latency controller is different. 
     To further achieve the above-described objects of the present invention in a whole or in parts, there is provided a latency control circuit that includes a control circuit adapted to receive a clock signal to regulate data output and a plurality of input signals to provide first, second and third control signals, a first logic gate for logically combining a CAS latency control signal with data, a first latch to pass or latch data from said first logic gate in response to the third control signal from said control circuit unit, a second logic gate for logically combining a second logic gate control signal with data, a second latch to pass or latch data from said first latch or to pass or latch a data from said second logic gate in response to the second control signal from the control circuit unit, and a third latch to pass data from said second latch to a data output buffer or latch the data in response to the first control signal from said control circuit unit. 
     To further achieve the above-described objects of the present invention in a whole or in parts, there is provided a Column Address Strobe (CAS) latency control circuit that includes a first data latch responsive to a first control signal, a controller, wherein the controller receives a clock signal and generates the first control signal, the first data latch being coupled to receive first and second input signals and output a first output signal, wherein the first output signal is one of (1) the first input signal forwarded without latching through the first data latch, (2) the first input signal latched and subsequently forwarded through the first data latch, (3) the second input signal forwarded without latching through the first data latch, and (4) the second input signal latched and subsequently forwarded through the first data latch, in response to the first control signal. 
     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein: 
     FIG. 1 is a drawing which illustrates of related art CAS latency control circuits in a SDRAM; 
     FIG. 2 is a drawing illustrating a related art CAS latency control circuit for a SDRAM; 
     FIG. 3 is a drawing illustrating system of the latching unit in FIG. 2; 
     FIG. 4 is a drawing illustrating a system of the control inverter in FIG. 3; 
     FIG. 5 is a drawing illustrating an operation timing diagram of a related art first CAS latency; 
     FIG. 6 is a drawing illustrating an operation timing diagram of a related art second CAS latency; 
     FIG. 7 is a drawing illustrating an operation timing diagram of a related art third CAS latency; 
     FIG. 8 is a drawing illustrating an operation timing diagram of a related art first CAS latency; 
     FIG. 9 is a drawing which illustrates a timing diagram for data output with no clock signal QCLK and data skews in the operation of a related art CAS latency; 
     FIG. 10 is a drawing which illustrates a timing diagram for data output having clock signal QCLK and data skews in the operation of a related art CAS latency; 
     FIG. 11 is a drawing which illustrates a system of a CAS latency control circuit according to a first preferred embodiment; 
     FIG. 12 is a drawing which illustrates a first timing diagram of the CAS latency control circuit operation; 
     FIG. 13 is a drawing which illustrates a second timing diagram of the CAS latency control circuit operation; 
     FIG. 14 is a drawing which illustrates a third timing diagram of the CAS latency control circuit operation; 
     FIG. 15 is a drawing which illustrates a fourth timing diagram of the CAS latency control circuit operation; 
     FIG. 16 is a drawing which illustrates a preferred embodiment of CAS latency control circuits on a SDRAM; 
     FIG. 17 is a drawing which illustrates a CAS latency control circuit in accordance with a second preferred embodiment of the present invention; and 
     FIG. 18 is a drawing which illustrates a latch in accordance with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 11, the CAS latency control circuit according to a first preferred embodiment includes a control circuit unit  101  adapted to receive the clock signal QCLK. The control circuit  101  regulates data output by providing control signals con 1 , con 2  and con 3  which control latches  102 ,  103 ,  104 , and  105 . The circuit further includes a first AND gate  107  for logically combining a CAS latency control signal LE 34  from a mode register of the SDRAM with internal data, and a first latch  102  for forwarding or latching data from the first AND gate  107  depending on the value of the control signal con 3  from the control circuit unit  101 . Next, there is provided a second latch  103  for forwarding or latching data from the first latch  102  in accordance with the value of the control signal con 2 , and a third latch  104  for forwarding or latching a data from the second latch  103  in accordance with the value of the control signal con 1 . 
     The CAS latency control circuit also includes a second AND gate  108  for logically combining a control signal con 1  with a CAS latency control signal LE 12  from a mode register of the SDRAM. A fourth latch  105  then forwards or latches internal data in response to a signal from the second AND gate  108 , and a data path selecting unit  106  passes data either from the third latch  104  or from the fourth latch  105  to a data output buffer, as determined by the CAS latency control signal LE 12  from the mode register of the SDRAM. 
     The data path selecting unit  106  includes an inverter  106   a  for inverting a CAS latency control signal LE 12  from the mode register of the SDRAM and a first transmission gate  106   b  for transmitting an output from the third latch  104  to the data output buffer in response to the CAS latency control signal LE 12  and a signal from the inverter  106   a.  The data path selecting unit  106  further includes a second transmission gate  106   c  for transmitting data from the fourth latch  105  to the data output buffer in response to the CAS latency control signal LE 12  and a signal from the inverter  106   a.    
     The operation of the CAS latency control circuit according to the first embodiment will now be described. FIG. 11 illustrates a first timing diagram of the CAS latency control circuit operation. FIG. 12 illustrates a second timing diagram of the CAS latency control circuit operation. FIG. 13 illustrates a third timing diagram of the CAS latency control circuit operation. FIG. 14 illustrates a fourth timing diagram of art CAS latency control circuit operation. 
     Initially, in the read mode of the SDRAM, the main amplification units MA 0 i-MA 0 j, MA 1 i-MA 1 j, MA 2 i-MA 2 j, or MA 3 i-MA 3 j in a selected bank amplify data in the bank and provide it to respective data buses DATAi-DATAj. In this instance, the main amplification units MA 0 i-MA 0 j, MA 1 i-MA 1 j, MA 2 i-MA 2 j, or MA 3 i-MA 3 j in the unselected banks provide high impedances. 
     An external clock signal is provided to the QCLK buffer through the clock pads, and the QCLK buffer generates an internal clock signal QCLK. The internal clock signal QCLK and data provided through respective data buses DATAi-DATAj are then forwarded to respective CAS latency control circuits CLCCi-CLCCj. The control circuit unit  1  receives the clock signal QCLK and generates control signals con 1 , con 2 , and con 3 . Additionally, each of the CAS latency control circuits CLCCi-CLCCj receives the signals LE 2 , LE 3 , LE 4 , LE 12 , and LE 34  which are generated by a CAS latency mode setup of the SDRAM and provided from the mode register. During a first and second CAS latency operation, the signal LE 12  is set to “high” and the signal LE 34  is set to “low.” Alternatively, in a third and fourth CAS latency operation, the signal LE 12  is set to “low” and the signal LE 34  is set to “high.” Additionally, during the first CAS latency operation, all the signals LE 2 , LE 3 , and LE 4  are set to “low.” During the second, third, and fourth CAS latency operation, signals LE 2 , LE 3 , and LE 4  are set to “high” and are held at “low” in other cases. 
     Referring to FIG. 12, as the signals LE 2 , LE 3 , LE 4 , aced LE 34  transition to “low” and the signal LE 12  transitions to “high,” and the control signals con 1 , con 2 , and con 3  are all at “low” in response to the LE 2 , LE 3 , and LE 4 , the first, second, and third latches  102 ,  103 , and  104  are bypassed and receive no data. Meanwhile, the fourth latch  105  receives data, but passes the data because the control signal con 1  and the signal LE 12  are at “low.” Further, since the signal LE 12  is “low,” the data path selecting unit  106  forwards the data from the fourth latch  105  to the data output buffer. Thus, data is forwarded within one cycle from a read command. 
     Referring to FIG. 13, the signals LE 2  and LE 12  are set to “high,” the signals LE 3 , LE 4 , and LE 34  are set to “low,” a read command is received, and the clock signal QCLK is generated after one cycle. The control circuit unit  101  provides an inverted signal of the clock signal QCLK as a control signal, and the control signals con 2  and con 3  are held “low” by LE 2 , LE 3 , and LE 4 . Because the signal LE 12  is “high,” the first latch  105  and the second transmission gate  106   c  in the data path selecting unit  6  are enabled. During this operation, the fourth latch  105  releases latched data when the control signal con 1  is “low,” and latches data when the control signal con 1  is “high” for one cycle until the control signal con 1  subsequently transitions to “low” again. Because the control signal con 1  is enabled one cycle after the read command, data is presented from the SDRAM within two cycles. 
     Referring to FIG. 14, the signals LE 34  and LE 3  transition to “high” and the signals LE 12 , LE 2 , and LE 4  transition to “low.” Therefore, since the signal LE 12  is “low,” the fourth latch  105  and the second transmission gate  106   c  in the data path selecting unit  106  are turned off. Since the signal LE 34  is “high,” the first, second, and third latches  102 ,  103 , and  104  and the first transmission gate  106   b  in the data path selecting unit  106  are enabled. 
     During this operation, the control circuit unit  101  holds control signal con 3  “low” and control signals con 1  and con 2  “high” in response to the signals LE 2 , LE 3 , and LE 4 . Control signal con 1  transitions from “high” to “low” after a first rising edge of the clock signal QCLK, and from “low” to “high” again after a first time period. Control signal con 2  transitions from “high” to “low” after a first falling edge of the clock signal QCLK, and from “low” to “high” again after a second time period. The control signals con 1  and con 2  repeat this process continuously with each cycle of the clock signal QCLK. 
     Since the control signal con 3  is held at “low,” the first latch  102  passes the data to the second latch  103 . When the control signal con 2  transitions to “low,” the data passes through the second latch  103  to the third latch  104 . In this instance, since the control signal con 2  transitions to “high” again, the second latch  103  latches the data before passing it to the third latch  104  when the control signal con 2  transitions to “low” again. Further, when the control signal con 1  transitions to “low” for the second time, the third latch  104  passes the data to the data output buffer. If, however, the control signal con 1  transitions to “high” again, the third latch  104  latches data until the next cycle. Thus, data is outputted from the SDRAM within three cycles after the read command. 
     As shown in FIG. 15, signals LE 34  and LE 4  are set to “high” to enable the first, second, and third latches  102 ,  103 , and  104  and the first transmission gate  106   b  in the data path selecting unit  106 . The control circuit unit  101  thus initially provides the control signals con 1 , con 2 , and con 3  in a “high” state. As respective control signals subsequently transition to “low,” the first latch  102  releases latched data to the second latch  103 , the second latch  103  releases data to the third latch  104 , and the third latch  104  provides the data to the data output buffer. When respective signals transition from “low” to “high,” on the other hand, each respective latch latches data. Thus, data can be outputted within four cycles from the read command. 
     Referring to FIG. 16, a SDRAM according to a preferred embodiment of the present invention has four banks BANK 0 , BANK 1 , BANK 2 , and BANK 3 . Each bank has n main amplification units MA 0 i-MA 0 j, MA 1 i-MA 1 j, MA 2 i-MA 2 j, and MA 3 i-MA 3 j, which are secondary amplifier circuits. The circuit further includes n-bit data buses nbit DATA BUS between the first and second banks and the third and fourth banks. The main amplification units MA 0 i-MA 0 j, MA 1 i-MA 1 j, MA 2 i-MA 2 j, and MA 3 i-MA 3 j in each bank share respective data buses DATAi-DATAj. Since locations of input/output pins are fixed, n DQ blocks DQi-DQj, each including a data output buffer and an input/output pad, are located at prescribed locations. 
     CAS latency control circuits CLCCi-CLCCj, one to one matched to the data buses, are arranged such that they are concentrated in a position central to the data buses. That is, the (i)th CAS latency control circuits share an (i)th data bus at a location central between the first and second banks and the third and fourth banks. Further, the CAS latency control circuits CLCCi-CLCCj are arranged such that length of connection lines between outputs from the CAS latency control circuits CLCCi-CLCCj to respective DQ blocks DQi-DQj are different from one another. 
     A clock signal buffer QCLK buffer applies a clock signal QCLK to the CAS latency control circuits CLCCi-CLCCj, and is positioned adjacent to the clock pad. Connection lines from the clock signal QCLK are connected to respective CAS latency control circuits CLCCi-CLCCj. 
     Referring to FIG. 17, a second preferred embodiment includes a control circuit unit  21  for regulating data output. The control circuit is adapted to receive a clock signal QCLK and to receive control signals LE 2 , LE 3 , and LE 4  provided from a mode register of a SDRAM. The control circuit  21  control signals con 1 , con 2 , and con 3  control respective latches  24 ,  23 ,  22 . The circuit further includes an AND gate  25  for logically combining a CAS latency control signal LE 34  provided from the mode register of the SDRAM with data from the SDRAM. Also, the circuit includes a first latch  22 , which passes or latches data from the AND gate  25  in response to the control signal con 3  from the control circuit unit  21 , and a NAND gate  26 , which logically combines a CAS latency control signal LE 12  provided from the mode register of the SDRAM with data from the SDRAM. 
     Next, the circuit includes a multiplexing latch  23  for passing or latching a data from the first latch  22  or passing or latching data from the NAND gate  26 , in response to the control signal con 2  from the control circuit unit  21 . A second latch  24  passes data from the multiplexing latch  23  to a data output buffer, or latches the data in response to the control signal con 1  from the control circuit unit  21 . 
     FIG. 18 shows details of one embodiment of the multiplexing latch  23 . According to this embodiment, the multiplexing latch  23  includes an inverter  27  for inverting the control signal con 2  from the control circuit unit  21  and a first clocked inverter  28  for inverting, and either passing or blocking data D 1  from the first latch  22  in response to each of a signal from the inverter  27  and the control signal con 2 . The multiplexing latch  23  also includes a NAND gate  30  for logically combining data from the first clocked inverter  28  with data D 2  from the NAND gate  26 . The output of the NAND gate  30  is provided to the data output buffer. A second clocked inverter  29  inverts and latches data from the NAND gate  30  in response to the signal from the inverter  27  and the control signal con 2 . 
     The operation of the invention according to this embodiment of the CAS latency control circuit will now be described. The control signals con 1 , con 2 , and con 3  from the control circuit unit  21  and the control signals LE 2 , LE 3 , LE 4 , LE 12 , and LE 34  from the mode register of the SDRAM are the same as those of the related art, except that the data is provided to an input terminal D 2  on the multiplexing latch  23  through the NAND gate  26  in first and second CAS latency operations, and the path is disabled in the third and fourth CAS latency operations. 
     During the first CAS latency operation, the signals LE 2 , LE 3 , LE 4 , and LE 34  transition to “low,” and the signal LE 12  transitions to “high.” The control circuit unit  21  provides all the control signals con 1 , con 2 , and con 3  at “low” in response to the signals LE 2 , LE 3 , and LE 4 , and the AND gate  25  provides a “low” signal regardless of the value of data. Accordingly, data in the SDRAM is inverted by the NAND gate  26 , and provided to the data output buffer through the multiplexing latch  23  and the second latch  24 . 
     During the second CAS latency operation, the control signals LE 2  and LE 12  are set to “high” and the control signals LE 3 , LE 4 , and LE 34  are set to “low.” The clock signal QCLK is generated one clock cycle after reception of a read command. The control circuit unit  21  provides an inverted clock signal QCLK as the control signal con 1 , and holds the control signals con 3  and con 2  “low.” Since the control signal LE 34  is “low” and the control signal LE 12  is “high,” data in the SDRAM is forwarded through the multiplexing latch  23  and the second latch  24 . The second latch  24  releases latched data when the control signal con 1  is “low” and latches data for one cycle starting when the control signal con 1  is “high” until the control signal con 1  transitions to “low.” Since the control signal con 1  is enabled one cycle after the read command, the data is outputted from the SDRAM within two cycles. 
     During the third CAS latency operation, the control signals LE 34  and LE 3  transition to “high” and the control signals LE 12 , LE 2 , and LE 4  transition to “low.” Therefore, since signal LE 12  is “low,” the NAND gate  26  is turned off. Also, since the signal LE 34  is “high,” the first and second latch  22  and  24  and the D 1  terminal on the multiplexing latch  23  are enabled. The control circuit unit  21  holds the control signal con 3  “low” and the control signals con 1  and con 2  “high” in response to the control signals LE 2 , LE 3 , and LE 4 . Thus, the control signal con 1  transitions from “high” to “low” after a first rising edge of the clock signal QCLK and from “low” to “high” again after a time period. Further, the control signal con 2  transitions from “high” to “low” at a first falling edge of the clock signal QCLK and from “low” to “high” again after a time period. The control signals con 1  and con 2  repeat the foregoing process continuously with each cycle of clock signal QCLK. Accordingly, since the control signal con 3  is held at “low,” the data is provided to the D 1  terminal on the multiplexing latch  23  through the first latch  22 , and when the control signal con 2  transitions to “low,” the data is provided to the second latch  24  through the multiplexing latch  23 . Since the control signal con 2  transitions to “high” again, the multiplexing latch  23  latches the data, and subsequently passes it to the second latch  24  when the control signal con 2  again transitions to “low.” If the control signal con 1  transitions to “low” for the second time, the second latch  24  provides the data to the data output buffer, and when the control signal con 1  transitions to “high” again, keeps the data latched thereto until the next cycle when the control signal again transitions to “low.” 
     In the fourth CAS latency operation, as in the third CAS latency operation, the signals LE 34  and LE 4  are set to “high,” thus enabling the first and second latches  22  and  24  and the D 1  terminal on the multiplexing latch  23 . The control circuit unit  21  provides control signals con 1 , con 2 , and con 3 . Therefore, when a pertinent control signal transitions to “low,” the first latch  22  provides latched data to the D 1  terminal on the multiplexing latch  23 . The multiplexing latch  23  in turn provides data to the second latch  24 , and the second latch  24  provides data to the data output buffer, and latches the data if a pertinent control signal transitions from “low” to “high.” 
     The embodiments of the CAS latency control circuit of the present invention have at least the following advantages. The parallel data pass depending on CAS latencies can prevent passing through unnecessary latches thus reducing data delay. That is, in the first and second latency operations in the related art, the serial pass of data through the unnecessary first and second latching means caused the data delay. The prevention of data delay allows a faster SDRAM. 
     Additionally, the CAS latency control circuit of the present invention have at least the following advantages. The concentrated location of the CAS latency control circuits central to a chip facilitates elimination of clock signal QCLK skews between the CAS latency control circuits, and reduces data skews between banks. The reduction of the clock and data skews improves the operation of SDRAMs at high frequencies. 
     The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.