Abstract:
An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.

Description:
[0001]     This application claims the benefit of Taiwan application Serial No. 092128358, filed Oct. 14, 2003, the subject matter of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The invention relates to an ESD (Electrostatic Discharge) protection circuit, and more particularly to an ESD protection circuit for internal circuits using different voltage sources.  
         [0004]     2. Description of the Related Art  
         [0005]     An ESD (Electrostatic Discharge) protection circuit often applied in an integrated circuit. Owing to the large voltage of electrostatic charge, the integrated circuit must utilize the ESD protection circuit to prevent the electrostatic charge from damaging internal circuits of the integrated circuit.  
         [0006]     However, with the evolution of the technology, different voltage sources are used for the different internal circuits of the integrated circuit. Therefore, the ESD protection circuit is not only disposed between signal input and output bonding pads of the internal circuits, but also disposed between different voltage sources in the integrated circuit. The invention is disclosed with respect to this condition.  
         [0007]      FIG. 1  is a schematic illustration showing a conventional ESD protection circuit for internal circuits with different voltage sources. Referring to  FIG. 1 , the integrated circuit  100  includes an internal circuit  110  using a voltage source with two voltage terminals VDD 1  and VSS 1 , and an internal circuit  120  using another voltage source with two voltage terminals VDD 2  and VSS 2 . Besides, the output signal  121  of the internal circuit  110  can be inputted to the internal circuit  120  through inverters  123  and  125  which are used as the interface circuits for the internal circuits  110  and  120 .  
         [0008]     The ESD protection mechanism for the integrated circuit  100  is implemented by using ESD clamp circuits  130  and  140  and ESD protection circuits  150  and  160  as shown in the  FIG. 1 .  
         [0009]     For example, when the ESD occurs between the VDD 1  and the VSS 2 , the large ESD current may flow from the VDD 1  to the VSS 2 , or from the VSS 2  to the VDD 1 . In order to prevent the large ESD current from damaging the internal circuits  110  and  120  or the inverters  123  and  125 , the clamp circuits  130  and  140  are turned on to discharge the ESD current. Therefore, the large current I 1  may be discharged along the path P 1  and path P 2 . That is, the ESD current may be discharged to VSS 2  through diodes  151  and  153  of the ESD protection circuit  150  and the clamp circuit  130 , and may be discharged to VSS 2  through the clamp circuit  140  and the substrate resistor Rs of the ESD protection circuit  160 .  
         [0010]     Similarly, when the ESD occurs between the VDD 2  and the VSS 1 , the large ESD current may be discharged from the VDD 2  to the VSS 1  through the ESD protection circuit  150  and ESD claim circuit  140 , or through the ESD protection circuit  160  and the ESD clamp circuits  130 . So, the large ESD currents may be discharged without damaging the internal circuits  110  and  120  or the inverter  123  and  125 .  
         [0011]     In addition, the ESD protection circuit  150  is not only for providing discharging path, but also for isolating the two voltage terminals VDD 1  and VDD 2  from each other. Thus, the two internal circuits  110  and  120  can independently use their own voltage sources during the absence of the electrostatic charge. Therefore, the ESD protection circuit  150  must have a predetermined threshold voltage to effectively isolate the two voltage terminals VDD 1  and VDD 2  from each other.  
         [0012]     Hence, the voltage drop of the two serially connected diodes  151  and  153  being forward conducted has to be larger than the voltage difference between the VDD 1  and the VDD 2 . For instance, if the voltage of the VDD 1  is 1.8V and the voltage of the VDD 2  is 3.3V, the voltage drop of the serially connected diodes  151  and  153  being forward conducted has to be larger than 1.5V.  
         [0013]     In addition, when the voltage difference between the VDD 1  and the VDD 2  becomes larger, the number of the serially connected diodes of the ESD protection circuit  150  also has to be correspondingly increased in order to effectively isolate the VDD 1  and the VDD 2  from each other.  
         [0014]      FIG. 2  is a schematic illustration showing another conventional ESD protection circuit for an integrated circuit using hybrid voltage sources. As shown in  FIG. 2 , when the voltage difference between the voltage sources VDD 3  and VDD 4  is increased, the number of serially connected diodes in the ESD protection circuit  230  should be correspondingly increased. The diodes in the ESD protection circuit are formed based on PMOS or NMOS transistors (not shown). However, the diode of the conventional ESD protection circuit causes the following drawbacks.  
         [0015]     1. The diode has a higher leakage current and a lower breakdown voltage, and cannot effective isolate two independent voltage sources from each other.  
         [0016]     2. The capability of the diode for driving current is not very good, and thus the current caused by the ESD cannot be discharged quickly.  
         [0017]     3. The parasitic capacitance of the diode coupled between two independent powers is larger, and tends to affect the signal between the two internal circuits.  
         [0018]     In view of this, the invention proposes an ESD protection circuit to solve the above-mentioned problems.  
       SUMMARY OF THE INVENTION  
       [0019]     It is therefore an object of the invention to provide an ESD protection circuit for an IC utilizing different voltage sources. The ESD protection circuit includes a first bipolar transistor set, a second bipolar transistor set, a first detection circuit and a second detection circuit. The first bipolar transistor set comprises a first bipolar transistor and a second bipolar transistor. The collector of the first bipolar transistor and the emitter of the second bipolar transistor are coupled to a voltage terminal VDD 1 . The emitter of the first bipolar transistor and the collector of the second bipolar transistor are coupled to another voltage terminal VDD 2 .  
         [0020]     The second bipolar transistor set comprises a third bipolar transistor and a fourth bipolar transistor. The collector of the third bipolar transistor and the emitter of the fourth bipolar transistor are coupled to a voltage terminal VSS 1 . The emitter of the third bipolar transistor and the collector of the fourth bipolar transistor are coupled to another voltage terminal VSS 2 .  
         [0021]     The first detection circuit has a first connection terminal, a second connection terminal, and a trigger terminal. The first connection terminal of the first detection circuit is coupled to the VDD 1 , the second connection terminal of the first detection circuit is coupled to the VSS 1 , and the trigger terminal of the first detection circuit is respectively coupled to the bases of the first and the third bipolar transistors.  
         [0022]     Similarly, the second detection circuit has a first connection terminal, a second connection terminal and a trigger terminal. The first connection terminal of the second detection circuit is coupled to the VDD 2 , the second connection terminal of the second detection circuit is coupled to the VSS 2 , and the trigger terminal of the second detection circuit is respectively coupled to the bases of the second and the fourth bipolar transistors.  
         [0023]     Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]      FIG. 1  is a schematic illustration showing a conventional ESD protection circuit for an IC using different voltage sources.  
         [0025]      FIG. 2  is a schematic illustration showing another conventional ESD protection circuit for an integrated circuit using hybrid voltage sources.  
         [0026]      FIG. 3  is a schematic illustration showing an ESD protection circuit according to an embodiment of the invention.  
         [0027]      FIG. 4A  is a schematic illustration showing a first transistor set structure according to an embodiment of the invention.  
         [0028]      FIG. 4B  is a top view showing the first transistor set structure of  FIG. 4A . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0029]      FIG. 3  is a schematic illustration showing an ESD protection circuit according to an embodiment of the invention. As shown in  FIG. 3 , the ESD protection mechanism in the. integrated circuit  300  is implemented by using ESD detecting circuits  330  and  340  and ESD protection circuits  310  and  320 , wherein the ESD detecting circuit  330  is coupled between power source terminals VDD 1  and VSS 1 , the ESD detecting circuit  340  is coupled between power source terminals VDD 2  and VSS 2 , the ESD protection circuit  310  is coupled between the VDD 1  and the VDD 2 , and the ESD protection circuit  320  is coupled between the VSS 1  and the VSS 2 . Besides, at least a first diode (not shown) may be connected between the VDD 1  and the VSS 1  for providing a discharging path from the VSS 1  to the VDD 1 , and a second diode (not shown) may be connected between the VDD 2  and the VSS 2  for providing a discharging path from the VSS 2  to the VDD 2 .  
         [0030]     The first transistor set  310  comprises two NPN bipolar transistors  311  and  312 , and the second transistor set  320  comprises two NPN bipolar transistors  321  and  322 , wherein the bipolar transistors  311 ,  312 ,  321 , and  322  can be replaced by other kinds of transistors such as metal oxide semiconductor field effect transistors (MOSFETs). The detecting circuit  330  mainly comprises a NMOS  334 , a resistor  331 , a capacitor  332 , and an inverter  333 , and the second detecting circuit  345  comprises a NMOS  344 , a resistor  341 , a capacitor  342  and an inverter  343 . Note that the implementation of the detecting circuit  330  or  340  is not limited by this embodiment.  
         [0031]     In the normal condition which means the electrostatic charge is absent at the voltage terminals VDD 1  and VDD 2 , the capacitor  332  works as a open circuit and the voltage at the input end of the inverter  333  is the same as the voltage at the VDD 1  (assumed to be a high-level voltage 1.8 volts). Thus, the inverter  333  inverts the high-level voltage and outputs a low-level voltage to node  1  such that the NMOS transistor  334  is kept off.  
         [0032]     Similarly, in the normal condition, the capacitor  342  works as a open circuit and the voltage at the input end of the inverter  343  is the same as the voltage at the VDD 2  (assumed to be a high level voltage 3.3 volts). The inverter  343  inverts the high-level voltage and outputs a low-level voltage such that the NMOS transistor  344  is kept off.  
         [0033]     Meanwhile, the inverter  333  outputs the low-level voltage to the base of the bipolar transistor  311  and the base of the bipolar transistor  321 . Thus, the bipolar transistors  311  and  321  are kept OFF because the low-level voltage at node  1  is not high enough to turn on the bipolar transistors  311  and  321 .  
         [0034]     In addition, the inverter  343  outputs the low-level voltage to the base of the bipolar transistor  312  and the base of the bipolar transistor  322 . Therefore, the bipolar transistors  312  and  322  are also kept OFF because the low-level voltage at node  2  is not high enough to turn on the bipolar transistors  312  and  322 .  
         [0035]     Furthermore, the NPN junction structures of the bipolar transistors  311 ,  312 ,  321 , and  322  have the properties of low leakage current and high breakdown voltage.  
         [0036]     Consequently, in the normal condition, the first bipolar transistor set  310  and the second bipolar transistor set  320  are OFF, so the voltage terminals VDD 1  and VDD 2  are effectively isolated from each other.  
         [0037]     When the electrostatic charge injected into the VDD 1 , VDD 2 , VSS 1 , or VSS 2 , the ESD current may be discharged from the VDD 1  to the VSS 2 , from the VSS 2  to the VDD 1 , from the VDD 2  to the VSS 1 , or from the VSS 1  to the VDD 2 .  
         [0038]     When the electrostatic voltage is a positive large pulse injected into the VDD 1 , the large ESD current I 1  may flows from the VDD 1  to the VSS 2 . Meanwhile, the capacitor  332  and the capacitor  342  work as short circuit corresponding to the transient electrostatic voltage, and the voltages at the input ends of the inverters  333  and  343  are respectively pulled down to the low-level voltages at VSS 1  and VSS 2 . Consequently, the inverters  333  and  343  respectively invert the low-level voltages into high-level voltages for output. That is, the voltages at nodes  1  and  2  are high-level voltages and thus the bipolar transistors  311 ,  321 ,  312 , and  322  are turned on.  
         [0039]     Thus, the large ESD current I 1  may be discharged along path  1  (from the VDD 1  to the VSS 2  through the bipolar transistor  311  and the NMOS transistor  344 ) and path  2  (from the VDD 1  to the VSS 2  through the NMOS transistor  334  to the bipolar transistor  321 ).  
         [0040]     Similarly, when the ESD is a positive large pulse injected into the VDD 2 , the large ESD current may be discharged from the VDD 2  to the VSS 1  through the bipolar transistor  312  and the NMOS transistor  334 , and from the VDD 2  to the VSS 1  through the NMOS transistor  334  to the bipolar transistor  322 ).  
         [0041]     In addition, the NPN bipolar transistors  311 ,  312 ,  321  and  322  enable the ESD protection mechanism to have the higher capability for driving current (i.e., the higher capability for discharging the ESD current).  
         [0042]     In the preferred embodiment of the invention, the practical structures of the first and the second transistor set  310 ,  320  also can be implemented by using the typical CMOS triple well process. It means that BJT or BiCMOS technology is not necessary for implementing the present invention and thus the complication of the process is reduced. Explanation will be made by taking the structure of the first transistor set  310  as an example with reference to  FIG. 4A .  
         [0043]      FIG. 4A  is a schematic illustration showing the structure of the first transistor set  310  according to an embodiment of the invention. In  FIG. 4A , the structure of the bipolar transistor  311  includes a P-well  437 , a deep N-well  431 , an N-well  435  and an N-well  439  adjacent to the P-well  437 . The N+ region  441 , the P+ region  443 , the N+ region  445 , the P+ region  443  and the N+ region  441  are respectively disposed on the N-well  435 , the P-well  437  and the N-well  439 . These ion implantation regions are isolated from each other by STI (shallow trench isolation) structures  451  and  452 .  
         [0044]     Accordingly, the N+ ion implantation region  445  is the collector of the bipolar transistor  311  and is coupled to the voltage source VDD 1  of  FIG. 3 , the P+ ion implantation regions  443  is the base of the bipolar transistor  311  and is coupled to the node  1  of  FIG. 3 , and the N+ ion implantation regions  441  is the emitter of the bipolar transistor  311  and is coupled to the voltage source VDD 2  of  FIG. 3 .  
         [0045]     Therefore, when the ESD current I 1  of  FIG. 3  is discharged from the collector of the bipolar transistor  311  to the emitter thereof, the current I 1  flows from the P-well  437  into the N-wells  435  and  439  through the deep N-well  431 .  
         [0046]     Similarly, the N+ region  465  is the collector of the bipolar transistor  312  of  FIG. 3  and is coupled to the voltage source VDD 2  of  FIG. 3 . The P+ region  463  is the base of the bipolar transistor  312  and coupled to the node  2  of  FIG. 3 . The N+ region  461  is the emitter of the bipolar transistor  312  and coupled to the voltage source VDD 1  of  FIG. 3 . When the ESD current I 2  of  FIG. 3  is discharged from the collector to the emitter of the bipolar transistor  312 , the current I 2  flows from the P-well  477  into the N-wells  475  and  479  through the deep N-well  471 .  
         [0047]     In addition, in the embodiment of the invention, the ring structure formed by the triple well process is also helpful for discharging the ESD currents I 1  and I 2 .  FIG. 4B  is a top view showing the first transistor set  310  structure of  FIG. 4A . As shown in  FIG. 4B , the isolation structure  452  of  FIG. 4A  surrounds the N+ region  445 . Similarly, the P+ region  443  surrounds the isolation structure  452 . The isolation structure  451  also surrounds the P+ region  443 . Similarly, the N+ region  441  also surrounds the isolation structure  451 . The circumference of the deep N-well  431  also surrounds the circumference of the N+ region  445 .  
         [0048]     Because the first transistor set  310  may be formed as the ring structure, the bipolar transistor  311  or  312  can quickly discharge the ESD currents I 1 or I 2 . Besides, since the structure of the first transistor set  310  is formed by the triple CMOS well process, the parasitic capacitance within the NPN bipolar transistor  311  or  312  is also smaller than that of the conventional diode.  
         [0049]     In summary, the ESD protection mechanism of the invention has a smaller leakage current, a higher breakdown voltage, a higher capability for driving current, and a smaller parasitic capacitance. In addition, the ESD protection circuit can effectively isolate the different voltage terminals and quickly discharge the large ESD current. Furthermore, the signal between the internal circuits will not be easily affected due to the smaller parasitic capacitance.  
         [0050]     While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.