Abstract:
A current source circuit is provided. The circuit includes a first transistor and at least one second transistor. A first source/drain terminal of the first transistor is coupled to a bias voltage. A second source/drain terminal of the first transistor is used to receive a current signal, and the second source/drain terminal of the first transistor is coupled to a gate terminal of the first transistor. A first source/drain terminal of the second transistor is grounded. A second source/drain terminal of the second transistor is coupled to a voltage source and outputs a bias current. A gate terminal of the second transistor is coupled to the gate terminal of the first transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the priority benefit of Taiwan application serial no. 96119579, filed on May 31, 2007. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a current source circuit, and more particularly, to a current source circuit having a compensation threshold voltage. 
         [0004]    2. Description of Related Art 
         [0005]    Low-temperature poly-silicon (LTPS) technology is a new fabrication processing technology for thin film transistor liquid crystal displays (TFT-LCD). In comparison with conventional amorphous silicon (a-Si) LCD, a LTPS LCD has the advantages of fast response speed, high brightness and high resolution. 
         [0006]    Hence, the use of LTPS transistor for application in integrated circuits such as active matrix liquid crystal display (AMLCD) and active matrix organic light emitting diode (AMOLED) has been given a tremendous amount of attention. In a poly-silicon (poly-Si) TFT-LCD, the poly-Si TFT, for example, is utilized in a pixel circuit and a driving circuit on a glass substrate to lower the processing costs. In fact, many LTPS AMLCDs having driving circuits and control circuits mounted on the glass substrate can be implemented in portable systems such as mobile phones, digital cameras and notebook computers. In the future, the development of LTPS fabrication process steers towards realizing the implementation of LCD integration designs such as system-on-panel(SoP) or system-on-glass(SoG), especially display systems that are compact, low in manufacturing costs and low in power consumption. 
         [0007]    However, in LTPS fabrication process, the utilization of analog circuit design is inevitable. Hence, the need for bias voltage is arisen. During the LTPS fabrication process, if the bias voltage is not precise enough, the circuit cannot be implemented on the glass substrate. In other words, the bias voltage needs to be precise enough to be utilized on the glass substrate. Defects such as non-uniform performance may result in LTPS fabrication process, which the threshold voltage may be varied and the bias voltage become made imprecise, thus the operation of the circuit is affected. 
         [0008]      FIG. 1  is schematic view illustrating a circuit diagram of a circuit diagram of the conventional current source circuit (during an 8 μm LTPS fabrication process). Referring to  FIG. 1 , a current source circuit  100  is an NMOS transistor.  FIG. 2  is a schematic view illustrating a HSPICE simulation showing the relationship between the gate voltage V G  and the drain current I D . In this graph, the operational voltage V DD  is set to be 10V, the size of the NMOS transistor is set to be 80 μm/8 μm, the gate bias voltage is set to be between 1.3V˜4.3V, and the drain bias voltage is set to be also between 1.3V˜4.3V (for the NMOS transistor to operate in saturation). Further, the NMOS transistor has a threshold voltage variation of 50% Gaussian distribution. According to  FIG. 2 , when the gate voltage V G  is 3.8V, the difference in the drain current I D  is 22 μA, and the variation of the drain current I D  is 88% (the value is obtained by dividing the difference in the current into the average value of the current). This by dividing the difference in the current into the average value of the current). This variation will result in mismatch between the gate voltage V G  and the drain current I D , affecting the normal operation of the entire circuit. Therefore, variation in the threshold voltage affects the operation of the entire circuit. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention is directed to a current source circuit adapted for minimizing the effect of the threshold voltage on the bias current to ensure the bias current of the current source circuit is more precise. 
         [0010]    The present invention is directed to a current source circuit including a first transistor and at least one second transistor. A first source/drain terminal of the first transistor is coupled to a bias voltage, and a second source/drain terminal of the first transistor is used to receive a current signal. Further, the second source/drain terminal of the first transistor is coupled to the gate terminal of the first transistor. A first source/drain terminal of a second transistor is grounded and the second source/drain terminal of the second transistor is coupled to a voltage source to output a bias current. Further the gate terminal of the second transistor is coupled to the gate terminal of the first transistor. 
         [0011]    From another point of view, the present invention is directed to a current source circuit including a current mirror module, a voltage divider module, a first transistor, and at least one second transistor. The current mirror module has an input terminal, a first output terminal, and a second output terminal. Further, the output terminal of the current mirror module is coupled to a voltage source. The voltage divider module has an input terminal and an output terminal. Further, the input terminal of the voltage divider module is coupled to the first output terminal of the current mirror module and the output terminal of the voltage divider module is grounded. A first source/drain terminal of the first transistor is coupled to a bias voltage, and a second source/drain terminal of the first transistor is coupled to the second output terminal of the current mirror module. Further, the second source/drain terminal of the first transistor is coupled to a gate terminal of the first transistor. A first source/drain terminal of a second transistor is coupled to the output terminal of the voltage divider module and a second source/drain terminal of the second transistor is coupled to a voltage source to output a bias current. Further, a gate terminal of the second transistor is coupled to the gate terminal of the first transistor. 
         [0012]    Through the voltage divider module and the current mirror module, the present invention ensures the first transistor operates in the sub-threshold region to effectively minimize the threshold voltage variation and the bias current outputted by the second transistor being more precise. Further, when the circuit is in operation, no defect such as the non-uniform performance is resulted to affect the overall performance of the circuit. 
         [0013]    In order to the make the aforementioned and other objects, features and advantages of the present invention comprehensible, several embodiments accompanied with figures are described in below detail. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a schematic view illustrating a circuit diagram of a conventional current source circuit. 
           [0015]      FIG. 2  is a schematic view illustrating the relationship between the voltage and the current of a conventional current source circuit. 
           [0016]      FIG. 3  is a schematic view illustrating a circuit diagram of a current source circuit according to one embodiment of the present invention. 
           [0017]      FIG. 4  is a schematic view illustrating the relationship between the gate control voltage and the bias voltage according to one embodiment of the present invention. 
           [0018]      FIG. 5  is a schematic view illustrating the relationship between the gate control voltage and the bias voltage according to one embodiment of the present invention (including a threshold voltage variation of 50% Gaussian distribution). 
           [0019]      FIG. 6  is a schematic view illustrating the relationship between the bias voltage and the bias current according to one embodiment of the present invention. 
           [0020]      FIG. 7  is a schematic view illustrating the relationship between the threshold voltage variation and the gate voltage of a conventional current source circuit. 
           [0021]      FIG. 8  is a schematic view illustrating the relationship between the threshold voltage variation and the bias voltage according to one embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0022]    Generally, a transistor mounted on a glass substrate usually operates in the saturation region. In LTPS fabrication process, the transconductance g m  and the output resistance r o  of the transistor determines the small signal gain and the frequency response of the analog circuit. The parameters of the transconductance g m  and the output resistance r o  of the transistor are described as the equations listed below: 
         [0000]    
       
         
           
             
               
                 
                   
                     g 
                     m 
                   
                   = 
                   
                     
                       μ 
                        
                       
                           
                       
                        
                       
                         C 
                         ox 
                       
                        
                       
                         W 
                         L 
                       
                        
                       
                         ( 
                         
                           
                             V 
                             GS 
                           
                           - 
                           
                             V 
                             TH 
                           
                         
                         ) 
                       
                     
                     = 
                     
                       
                         2 
                          
                         
                           I 
                           D 
                         
                       
                       
                         ( 
                         
                           
                             V 
                             GS 
                           
                           - 
                           
                             V 
                             TH 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    
       
         
           
             
               
                 
                   
                     r 
                     o 
                   
                   = 
                   
                     
                       V 
                       A 
                     
                     
                       I 
                       D 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0023]    When the transistor is operated in the saturation region, the drain current I D  may be described as the equation listed below: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     μ 
                      
                     
                         
                     
                      
                     
                       C 
                       ox 
                     
                      
                     
                       W 
                       L 
                     
                      
                     
                       
                         ( 
                         
                           
                             V 
                             GS 
                           
                           - 
                           
                             V 
                             TH 
                           
                         
                         ) 
                       
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0024]    Herein, Equation (3) has not taken the channel length modulation effect and the body effect into consideration. In Equation ( 3 ), the threshold voltage of the transistor is an important parameter. If the threshold voltage varies, the drain current I D  varies as well, lowering the performance of the analog circuit on the glass substrate. Hence, the problem with the threshold voltage variation is the primary problem that the present invention is directed to solve. 
         [0025]      FIG. 3  is a schematic view illustrating a circuit diagram of a current source circuit according to one embodiment of the present invention. Referring to  FIG. 3 , a current source circuit  300  includes a current mirror module  310 , a voltage divider module  320 , a first transistor M 1 , and a second transistor M 2 . Herein, the current mirror module  310  has an input terminal  311 , a first output terminal  312 , and a second output terminal  313 . Further, the input terminal  311  of the current mirror module  310  is coupled to a voltage source V DD  (e.g. V DD  provides the operating voltage for the current source circuit  300 ). 
         [0026]    In the present embodiment, the voltage divider module  320  has an input terminal  321  and an output terminal  322 . Further, the input terminal  321  of the voltage divider module  320  is coupled to the first output terminal  312  of the current mirror module  310 , while the output terminal  322  of the voltage divider module  320  is coupled to a ground terminal GND. 
         [0027]    In addition, the first transistor M 1  may be an NMOS transistor. Herein, a first source/drain terminal of the first transistor M 1  is coupled to a bias voltage V BIAS , while a second source/drain terminal of the first transistor M 1  is coupled to the second output terminal  313  of the current mirror module  310  and the second source/drain terminal of the first transistor M 1  is coupled to a gate terminal of the first transistor M 1 . 
         [0028]    Moreover, the second transistor M 2  may be an NMOS transistor. Herein, a first source/drain terminal of the second transistor M 2  is coupled to the output terminal  322  of the voltage divider module  320 , while a second source/drain terminal of the second transistor is coupled to the voltage source V DD  to output a bias current I BIAS  and a gate terminal of the second transistor M 2  is coupled to the gate terminal of the first transistor M 1 . 
         [0029]    Referring to  FIG. 3 , the current mirror module  310  includes a third transistor M 3  and a fourth transistor M 4 . Herein, the third transistor M 3  may be a PMOS transistor. Further, a first source/drain region of the third transistor M 3  is coupled to a gate terminal of the third transistor M 3  and the input terminal  321  of the voltage divider module  320  through the first output terminal  312  of the current mirror module  310 . On the other hand, a second source/drain terminal of the third transistor M 3  is coupled to the bias current I BIAS  through the input terminal  311  of the current mirror module  310 . 
         [0030]    Moreover, the fourth transistor M 4  may be a PMOS transistor. Herein, a first source/drain region of the fourth transistor M 4  is coupled to the second source/drain terminal of the first transistor M 1  through the second output terminal  313  of the current mirror module  310 . Additionally, a gate terminal of the fourth transistor M 4  and a second source/drain terminal of the fourth transistor M 4  are respectively coupled to the gate terminal of the third transistor M 3  and the second source/drain region of the third transistor M 3 . If the parameter of the third transistor M 3  matches the parameter of the fourth transistor M 4 , the current outputted by the first output terminal  312  of the current mirror module  310  is equal to the current outputted by the second output terminal  313  of the current mirror module  310 . 
         [0031]    In the present embodiment, the voltage divider module  320  includes a fifth transistor M 5  and a sixth transistor M 6 . Herein, the fifth transistor M 5  may be a PMOS transistor. Further, a first source/drain terminal of the fifth transistor M 5  is coupled to a gate terminal of the fifth transistor M 5 . In addition, a second source/drain terminal of the fifth transistor M 5  is coupled to the first output terminal  312  of the current mirror module  310  through the input terminal  321  of the voltage divider module  320 . 
         [0032]    On the other hand, the sixth transistor M 6  may be an NMOS transistor. Herein, a first source/drain terminal of the sixth transistor M 6  is coupled to a ground terminal GND through the output terminal  322  of the voltage divider module  320 . Further, a gate terminal of the sixth transistor M 6  is coupled to the input terminal  311  of the current mirror module  310 . In addition, a second source/drain terminal of the sixth transistor M 6  is coupled to the first source/drain terminal of the fifth transistor M 5 . Through operating the voltage divider module  320 , the present invention can ensure the first transistor M 1  operates in the sub-threshold region, which is described in detail below. 
         [0033]    In the present embodiment, through adjusting the voltage of the source/drain of the six transistor M 6  by the voltage divider module  320 , the six transistor M 6  is operated in the triode region to generate a current. This current is outputted to the source/drain terminal of the first transistor M 1  through the second output terminal  313  of the current mirror module  310  so that the first transistor M 1  is operated in the sub-threshold region. Further, the gate control voltage V GC  of the first transistor M 1  is described as the equation listed below: 
         [0000]        V   GC   ≅V   BIAS   +V   TH     —     M1    (4) 
         [0034]    Herein, V TH     —     M1  represents the threshold voltage of the first transistor M 1  and V BIAS  represent the bias voltage of the source terminal of the first transistor M 1 . In addition, the gate control voltage V GC  is also the gate voltage of the second transistor M 2 . Moreover, the bias current I BIAS  outputted by the second transistor M 2  is described as the equation listed below: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           I 
                           BIAS 
                         
                         = 
                           
                          
                         
                           
                             1 
                             2 
                           
                            
                           μ 
                            
                           
                               
                           
                            
                           
                             
                               
                                 C 
                                 ox 
                               
                                
                               
                                 ( 
                                 
                                   W 
                                   L 
                                 
                                 ) 
                               
                             
                             
                               M 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                            
                           
                             
                               ( 
                               
                                 
                                   V 
                                   GC 
                                 
                                 - 
                                 
                                   V 
                                   TH_M2 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             1 
                             2 
                           
                            
                           μ 
                            
                           
                               
                           
                            
                           
                             
                               
                                 C 
                                 ox 
                               
                                
                               
                                 ( 
                                 
                                   W 
                                   L 
                                 
                                 ) 
                               
                             
                             
                               M 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                            
                           
                             
                               ( 
                               
                                 
                                   V 
                                   BIAS 
                                 
                                 + 
                                 
                                   V 
                                   TH_M1 
                                 
                                 - 
                                 
                                   V 
                                   TH_M2 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0035]    Herein, V TH     —     M2  represents the threshold voltage of the second transistor M 2 . Through the symmetric layout, the threshold voltage V TH     —     M1  of the first transistor M 1  is close to the threshold voltage V TH     —     M2  of the second transistor M 2 . Therefore, Equation (5) can be re-written as the equation listed below: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     BIAS 
                   
                   ≅ 
                   
                     
                       1 
                       2 
                     
                      
                     μ 
                      
                     
                         
                     
                      
                     
                       
                         
                           C 
                           ox 
                         
                          
                         
                           ( 
                           
                             W 
                             L 
                           
                           ) 
                         
                       
                       
                         M 
                          
                         
                             
                         
                          
                         2 
                       
                     
                      
                     
                       
                         ( 
                         
                           V 
                           BIAS 
                         
                         ) 
                       
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0036]    Based on Equation (6) above, the bias current I BIAS  outputted by the second transistor M 2  is independent of the threshold voltage. However, the current value of the bias current I BIAS  depends on the bias voltage V BIAS . Further, the voltage value of the bias voltage V BIAS  determines the current value of the bias current I BIAS . Hence, the bias current I BIAS  outputted by the second transistor M 2  is thus not affected by the threshold voltage variation, ensuring the current value of the bias current I BIAS  is more precise. 
         [0037]    Next, the HSPICE simulation result is used to illustrate the advantages of the current source circuit  300  according to the embodiment of the present invention. First,  FIG. 4  shows the relationship between the gate control voltage V GC  and the bias voltage V BIAS . As shown in  FIG. 4 , the size of the bias voltage V BIAS  increases from 0V to 3V and the size of the gate control voltage V GC  increases from 1.3V to 4.3V. Further, in an 8μm LTPS fabrication process, the threshold voltage of the NMOS transistor is close to 1.3V. In addition, V GCl ≅V   BIAS +V TH     —     M1  and the value of the gate control voltage V GC  is also the same as the gate voltage V G  of a conventional circuit. 
         [0038]    Second, in the simulation, when the first transistor M 1  has a threshold voltage variation of 50% Gaussian distribution, the relationship between the control voltage V GC  and the bias voltage V BIAS  is as shown in  FIG. 5 . As shown in  FIG. 5 , when the threshold voltage variation equals to 50%, the gate control voltage V GC  is equal to 0.648V (i.e. ΔV GC ≅V TH     —     M1 ×50% ) The aforementioned simulation result ensures/is used to ensure the gate voltage of the second transistor M 2  is the same as the gate voltage of the conventional circuit. 
         [0039]    Next, parameters that are similar to those of the conventional circuit are used to simulate the relationship between the bias current I BIAS  and the bias voltage V BIAS . Therefore, the size of the second transistor M 2  is 80 μm/8 μm and the second transistor M 2  is operated in the saturation region. The simulation results are shown in  FIG. 6 . As shown in  FIG. 6 , when the bias voltage V BIAS  is 2.5V (according to the simulation results of  FIG. 4 , the bias voltage V BIAS  is 2.5V, which is equivalent to the gate voltage V G , 3.8V, as shown in  FIG. 2 ), and the bias current variation is. Hence, the bias current variation is calculated to be 0.96%. Comparing the simulation result to that of the conventional circuit, when the current source circuit  300  according to the embodiment of the present invention is under the same threshold voltage variation (i.e. 50%), the bias current variation I BIAS  lowers significantly from 88% to 0.96%. 
         [0040]    However, the aforementioned simulation result is generated when the threshold voltage variation is fixed to 50%. Now, four different examples are used to simulate according to the threshold voltage variation and the average value of the current and the variation are defined as the equations listed below: 
         [0000]    
       
         
           
             
               Average 
                
               
                   
               
                
               Value 
             
             = 
             
               
                 
                   I 
                   
                     D 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 + 
                 
                   I 
                   
                     D 
                      
                     
                         
                     
                      
                     2 
                   
                 
                 + 
                 
                   I 
                   
                     D 
                      
                     
                         
                     
                      
                     3 
                   
                 
                 + 
                 
                   I 
                   
                     D 
                      
                     
                         
                     
                      
                     4 
                   
                 
               
               4 
             
           
         
       
       
         
           
             
               Variation 
                
               
                   
               
                
               
                 ( 
                 % 
                 ) 
               
             
             = 
             
               
                 
                   
                     Average 
                      
                     
                         
                     
                      
                     Value 
                   
                   - 
                   
                     I 
                     
                       D_ 
                        
                       # 
                     
                   
                 
                 
                   Average 
                    
                   
                       
                   
                    
                   Value 
                 
               
               × 
               100 
                
               % 
             
           
         
       
     
         [0041]    Herein, I D1 , I D2 , I D3 , and I D4  respectively represent the source currents for the four different examples 1˜4. Further, the parameters for the simulations are described as follows. 
         [0042]    The voltage V DD  is 10V, the size of the transistor is 80 μm/8 μm, the conventional voltage V G  of 1.3˜4.3V is standardized to 0˜3V to facilitate comparison, and the bias voltage V BIAS  is the same as that described in the embodiment of the present invention. Additionally, the simulation results are respectively shown in  FIG. 7  and  FIG. 8 .  FIG. 7  is a schematic view illustrating the relationship between the threshold voltage variation and the gate voltage of a conventional current source circuit.  FIG. 8  is a schematic view illustrating the relationship between the threshold voltage variation and the bias voltage according to one embodiment of the present invention. 
         [0043]    Referring to  FIG. 7 , when the gate voltage V G  increases from 0V to 3V, the threshold voltage variation lowers from 195% to 30%. Referring to  FIG. 8 , when the bias voltage V BIAS  increases from 0V to 3V, the threshold voltage variation lowers from 75% to 5%. After comparing  FIG. 7  to  FIG. 8 , it can be seen that the current source circuit  300  according to the embodiment of the present invention can effectively lower the threshold voltage variation from 30% achieved by the conventional current source circuit 100 to 5%. Therefore, the bias current I BIAS  generated by the current source circuit of the present invention is more precise than that generated by the conventional current source circuit, which is not affected by the threshold voltage variation. 
         [0044]    Those skilled in the art should know that the number of the second transistor M 2  is not limited to only 1. More specifically, the number of the second transistor M 2  can be varied according to the user&#39;s requirement to 2 or more than 2. 
         [0045]    In view of the above, through the voltage divider module and the current mirror module, the present invention ensures the first transistor operates in the sub-threshold region to effectively minimize threshold voltage variation and ensure the bias current outputted by the second transistor is more precise. Further, when the circuit is in operation, no defect such non-uniform performance is resulted to affect the overall performance of the circuit. 
         [0046]    Although the present invention has been disclosed above by the embodiments, they are not intended to limit the present invention. Anybody skilled in the art can make some modifications and alteration without departing from the spirit and scope of the present invention. Therefore, the protecting range of the present invention falls in the appended claims.