Abstract:
A integrity control system uses the address bits to enable encryption and/or protection of data stored in a system memory. The encryption and protection mechanisms are coupled to the CPU by way of a data bus and to the memory by way of a data bus. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. At least one of the address lines enabling the encryption mechanism to encrypt data before storage in the memory and to decrypt data after retrieval from memory. Another address line enables the protection mechanism to generate a hash of the data. The hash is stored and used to determine whether data has been altered while stored in system memory.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is related to commonly assigned co-pending U.S. patent Application Ser. No. ______ (MSFT-3858/308767.01), filed Aug. 27, 2004, entitled “System and Method for Using Address Bits to Form an Index into Secure Memory.”; application Ser. No. ______ (MSFT-3859/308768.01), filed Aug. 27, 2004, entitled “System and Method for Using Address Bits to Affect Encryption”; application Ser. No. ______ (MSFT-3860/308,769.01), filed Aug. 27, 2004, entitled, “System and Method for Using Address Lines To Control Memory Usage”; application Ser. No. ______, (MSFT-3861/308770.01), filed Aug. 27, 2004, entitled, “System and Method for Applying Security To Memory Reads and Writes”. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to computer systems, and more particularly, to systems and methods for secure execution of program code within a computer system.  
       BACKGROUND OF THE INVENTION  
       [0003]     Computer systems today are subject to a variety of attacks that can disrupt or disable normal operation of a computer system. Computer viruses, worms, and trojan horse programs are examples of different forms of attack. Attacks can also come directly from unscrupulous users of a computer system. Often these attacks take the form of attempts to modify existing program code executed by the computer system or attempts to inject new unauthorized program code at various stages of normal program execution within the computer system. Systems and methods for preventing such malicious attacks are becoming increasingly important.  
         [0004]     A typical computer system comprises computer hardware, an operating system, and one or more application programs. The computer hardware typically comprises a processor (sometimes also referred to as a “central processing unit” or “CPU”), a memory, and one or more system buses that facilitate communication among the various components. Other components of a typical computer system include input/output controllers, a memory controller, a graphics processing unit, an audio controller, and a power supply.  
         [0005]     Such systems generally have a small amount of on-chip memory (referred to as cache memory) and a much larger amount of off-chip memory (referred to as system memory). The off-chip memory in such systems is generally not considered to be trustworthy (cache memory may also not be considered trustworthy but can be much easier to protect through hardware mechanisms that prevent an attacker from reading the contents of cache memory). That is, data stored in the large system memory is vulnerable to attack wherein the data could be easily altered in a way that was not intended by the owners of the data. Such an attack would cause a program to operate in an unintended manner or allow a copy protection scheme to be defeated.  
         [0006]     A number of systems have been developed that try to ensure that the data retrieved from system memory and be secured. In particular, systems have employed extensive encryption techniques as well as other tamper evident mechanisms that detect alterations to data in memory.  
         [0007]     The operating system can be thought of as an interface between the application programs and the underlying hardware of the computer system. The operating system typically comprises various software routines that execute on the computer system processor and that manage the physical components of the computer system and their use by various application programs.  
         [0008]     The processor of a computer system often includes a memory management unit that manages the use of memory by the operating system and any application programs. Many of the attacks against computer systems target programs in memory. For example, portions of code that execute security checks could be defeated by simply replacing that portion of a program when it is stored in memory. Other hacks could modify computer games and change the behavior. For example, consider a situation in which a vulnerability is discovered in a multiplayer game that allows a player to gain an unfair advantage by changing the code on his local machine. Such an unfair advantage could undermine the popularity of an otherwise popular game. All of these considerations suggest that it is highly desirable to prevent unauthorized alterations to program code.  
       SUMMARY OF THE INVENTION  
       [0009]     The present invention provides a secure computing environment that maintains the security of data stored in system memory. The system comprises a CPU and a security mechanism coupled to the CPU by way of a data bus and to the memory by way of a data bus. An address bus determines the location of storage of data in the system memory and has a plurality of address lines. At least one of the address lines enabling the security mechanism to secure data before storage in the memory. The CPU and the security mechanism may be on the same integrated circuit. The security mechanism may comprise an encryption and decryption mechanism. The system may also comprise an integrity check mechanism that generates an integrity check value as a function of the data. Another one of the address lines may enable the integrity check mechanism. The integrity check value is preferably a hash of the data (either in encrypted form or clear form or a combination of both) that creates a reduced size value that can be used to determine whether the data was altered during storage in system memory. The integrity check value is preferably stored in a secure memory that may also reside on the same integrated circuit with the CPU. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The foregoing summary, as well as the following detailed description of the invention, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings exemplary constructions of the invention; however, the invention is not limited to the specific methods and instrumentalities disclosed. In the drawings:  
         [0011]      FIG. 1  is a block diagram of an exemplary computer environment in which aspects of the present invention may be implemented;  
         [0012]      FIG. 2  is a block diagram illustrating a security engine that is incorporated into a computing environment such as the computing environment of  FIG. 1 ;  
         [0013]      FIG. 3  is a block diagram illustrating the conversion of address spaces in an example computing environment;  
         [0014]      FIG. 4  is a block diagram further illustrating aspects of conversion of an effective address to a virtual address;  
         [0015]      FIG. 5  is a block diagram further illustrating aspects of conversion of a virtual address to a real address;  
         [0016]      FIG. 6  is a block diagram further illustrating aspects of the invention in which address bits are set to indicate security features of the computing system;  
         [0017]      FIG. 7  is a block diagram illustrating an aspect of the security engine for encrypting and protecting data stored in memory; and  
         [0018]      FIG. 8  is a block diagram illustrating an aspect of the security engine for decrypting and checking the data stored in memory. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     The present invention provides a secure computing environment that helps prevent attacks on a computer system involving attempts to reverse engineer, disassemble, modify or otherwise alter data including program code in a computer system memory. The present invention may be embodied in a computer system or computing device comprising an untrusted memory and a processor that has a security engine comprising an encryption and/or verification mechanism. The system uses the address bits to signal to the security engine to perform security operations on the data before storing the data in system memory. The address bits could indicate, for example, that a particular page of system memory should be encrypted. Additionally, the address bits could indicate, for example, that a particular page of memory should be protected (i.e. verifiably unaltered). In the case of protection, verification information that is a function of the data, such as a hash, is preferably stored in a tamper-resistant secure memory. A secure memory generally can be thought of as residing in a security perimeter. Typically, the security perimeter is provided by putting the secure memory on the same integrated circuit as the CPU. The verification information is reproduced from the data after it is retrieved from untrusted system memory and that verification information is compared to the stored verification information. A difference between the information indicates that the data has be altered.  
         [0020]      FIG. 1  illustrates the functional components of a multimedia console  100  in which certain aspects of the present invention may be implemented. The multimedia console  100  has a central processing unit (CPU)  101  having a level  1  cache  102 , a level  2  cache  104 , and an MMU (Memory Management Unit)  103 . The level  1  cache  102  and a level  2  cache  104  temporarily store data and hence reduce the number of memory access cycles, thereby improving processing speed and throughput. The CPU  101  may be provided having more than one core, and thus, additional level  1  and level  2  caches  102  and  104 . The MMU  103  is responsible for handling memory accesses requested by the CPU. Other functions performed by MMU  103  includes the translation of virtual addresses to physical addresses (i.e., virtual memory management), memory protection, cache control, and so on.  
         [0021]     A graphics processing unit (GPU)  108  and a video encoder/video codec (coder/decoder)  114  form a video processing pipeline for high speed and high resolution graphics processing. Data is carried from the graphics processing unit  108  to the video encoder/video codec  114  via a bus. The video processing pipeline outputs data to an A/V (audio/video) port  140  for transmission to a television or other display. A memory controller  110  is connected to the GPU  108  to facilitate processor access to various types of memory  112 , such as, but not limited to, a RAM (Random Access Memory).  
         [0022]     The multimedia console  100  includes an I/O controller  120 , a system management controller  122 , an audio processing unit  123 , a network interface controller  124 , a first USB host controller  126 , a second USB controller  128  and a front panel I/O subassembly  130  that are preferably implemented on a module  118 . The USB controllers  126  and  128  serve as hosts for peripheral controllers  142 ( 1 )- 142 ( 2 ), a wireless adapter  148 , and an external memory device  146  (e.g., flash memory, external CD/DVD ROM drive, removable media, etc.). The network interface  124  and/or wireless adapter  148  provide access to a network (e.g., the Internet, home network, etc.) and may be any of a wide variety of various wired or wireless interface components including an Ethernet card, a modem, a Bluetooth module, a cable modem, and the like.  
         [0023]     Non-volatile memory  143 , e.g., flash memory, is provided to store application data that is loaded during the boot process. A media drive  144  is provided and may comprise a DVD/CD drive, hard drive, or other removable media drive, etc. The media drive  144  may be internal or external to the multimedia console  100 . Application data may be accessed via the media drive  144  for execution, playback, etc. by the multimedia console  100 . The media drive  144  is connected to the I/O controller  120  via a bus, such as a Serial ATA bus or other high speed connection (e.g., IEEE 1394).  
         [0024]     The system management controller  122  provides a variety of service functions related to assuring availability of the multimedia console  100 . The audio processing unit  123  and an audio codec  136  form a corresponding audio processing pipeline with high fidelity and stereo processing. Audio data is carried between the audio processing unit  123  and the audio codec  126  via a communication link. The audio processing pipeline outputs data to the A/V port  140  for reproduction by an external audio player or device having audio capabilities.  
         [0025]     The front panel I/O subassembly  130  supports the functionality of the power button  150  and the eject button  152 , as well as any LEDs (light emitting diodes) or other indicators exposed on the outer surface of the multimedia console  100 . A system power supply module  136  provides power to the components of the multimedia console  100 . A fan  138  cools the circuitry within the multimedia console  100 .  
         [0026]     The CPU  101 , GPU  108 , memory controller  110 , and various other components within the multimedia console  100  are interconnected via one or more buses, including serial and parallel buses, a memory bus, a peripheral bus, and a processor or local bus using any of a variety of bus architectures.  
         [0027]     When the multimedia console  100  is powered ON, application data may be loaded from the non-volatile memory  143  into memory  112  and/or caches  102 ,  104  and executed on the CPU  101 . The application may present a graphical user interface that provides a consistent user experience when navigating to different media types available on the multimedia console  100 . In operation, applications and/or other media contained within the media drive  144  may be launched or played from the media drive  144  to provide additional functionalities to the multimedia console  100 .  
         [0028]     The multimedia console  100  may be operated as a standalone system by simply connecting the system to a television or other display. In this standalone mode, the multimedia console  100  allows one or more users to interact with the system, watch movies, or listen to music. However, with the integration of broadband connectivity made available through the network interface  124  or the wireless adapter  148 , the multimedia console  100  may further be operated as a participant in a larger network community.  
         [0029]      FIG. 2  illustrates further aspects of the system of  FIG. 1  wherein various components of the system are integrated to provide security features that prevent code changes, reverse engineering, tampering, and the like. An integrated device  20  comprises the CPU  101 , the MMU  103 , cache  104 , security engine  105  and bus interface  107 . The various components are interconnected by way of an address bus  28  and a data bus  26 . MMU  103  controls the memory stored in Cache  104  to ensure that cache lines (e.g.,  22 ) are moved in and out of cache  104  as needed by CPU  101 . Data stored in cache  104  is operated upon by CPU  101  and hence is stored in the clear. In accordance with an aspect of the present invention, as cache lines are stored in system memory  112 , the data moves through security engine  105  and may be encrypted and decrypted as it moves to and from memory  112 .  FIG. 2  illustrates that cache line  22  is stored in the clear while in cache  104  but is encrypted as cache line  22 ′ when stored in memory  112 .  
         [0030]     System memory  112  is considered to be untrusted. That is, it can be compromised by an attacker and it&#39;s entire contents can be discovered and altered. Additionally, the address and data buses  28 ,  26  connecting bus interface  107  to system memory  112  can be monitored. On the other hand, integrated device  20  is considered to be secure. The buses  28 ,  26  that are internal to device  20  can not be monitored. Cache  104  is between security engine  105  and CPU  101  and is also considered to be trusted. All writes of cache  104  to system memory  112  are secured by security engine  105  as described more fully below. In addition to the system Ram  112 , the system also contains a secure memory  23  that is considered to be trusted. Preferably this secure memory  23  is within integrated device  20  to prevent its busses  28 ,  26  from being monitored.  
         [0031]     Memory management unit  103  handles the task of ensuring that the necessary data is in cache  104  so that CPU  101  can continue to operate efficiently. To that end, MMU  103  swaps data between cache  104  when needed instructions and data are in memory  112 . According to an aspect of the invention, the security engine  105  determines the level of security to apply to data to be moved between cache  104  and system memory  112 . For example, the movement of cache line  22  to memory as secured cache line  22 ′.  
         [0032]     Insomuch as every line of cache  104  that moves to system memory  112  has the potential to have security applied to it, it is important that the security be applied as rapidly as possible to avoid a significant performance hit to the overall system. In other words, it is desirable to provide security to data written to untrusted system memory  112  but it is undesirable to pay a significant loss of performance for that added security. An aspect of the invention is to use the address bus to provide an efficient mechanism to control the application of security. To that end, the memory management scheme employed by an example system is useful to understand how the addressing mechanism is used to determine application of security. Memory management generally takes advantage of various addressing schemes that translate a program address space into a physical address space. One such addressing scheme used by PowerPC systems uses effective address to real address conversion.  FIG. 3  helps to illustrate the address translation performed in a PowerPC environment. Other addressing schemes may be used as appropriate for a different processor environment.  
         [0033]     Referring to  FIG. 3 , effective address  302  is converted into real address  310  through one or more address conversion tables such as the segment lookaside buffer  304  and the translation lookaside buffer  308 . A program generally operates in a contiguous address space (referred to as effective address space); however, the physical address space must accommodate and be shared by a number of applications. As such, physical address space is managed by the system and may contain any number of different programs or portions of programs. To resolve the needs of the various programs, a system allows a program to operate in an address space that appears to be contiguous but which is managed by a memory management unit that tracks the physical location of the program and data. The program operates in an what is referred to as effective address space. That effective address space is translated into a virtual address space (i.e. an addressing continuum that can accommodate all of the programs simultaneously).  
         [0034]     The effective address is the address generated by CPU  101  for an instruction fetch or for a data access. An address translation mechanism attempts to convert that effective address  302  to a real address  310  which is then used to access memory  112 . The first step in address translation is to convert the effective address  302  to a virtual address  306 . The second step is to convert the virtual address  306  to a real address  310 .  FIG. 4  provides further details of the process of converting from an effective address  302  to a virtual address  306 . The Segment Lookaside Buffer (SLB)  304  specifies the mapping between Effective Segment IDs (ESIDs)  402  and Virtual Segment IDs (VSIDs)  410 . The number of SLB  304  entries is implementation-dependent. The contents of the SLB  304  are generally managed by an operating system. Each SLB entry in the table  304  maps one ESID  402  to one VSID  410 . The VSID then makes up the higher order bits in the virtual address  306 . The remaining lower order bits, the page address information  404  and byte address information  406 , are mapped directly to the virtual address  306  from the effective address  302 .  
         [0035]     The second step in the address translation is to translate a virtual address to a real address. The virtual to real translation employs the use of a page table  308 ′. Conceptually, page table  308 ′ is searched by the address relocation hardware to translate every reference. For performance reasons, the hardware usually keeps a Translation Lookaside Buffer (TLB)  308  that holds page table entries that have recently been used. The TLB  308  is searched prior to searching the page table  308 ′. Alternatively, the page table may not be a table but rather an algorithm that generates TLB entries as needed. Under that arrangement, when an address translation is not found in the TLB  308 , one or more TLB entries can be generated and used to update the entries in TLB  308 .  
         [0036]      FIG. 5  provides further details of the virtual to real address mapping. Page table  308 ′ (as noted above portions of this page table are cached in TLB  308 ) is a variable-sized data structure that specifies the mapping between a virtual page number and real page numbers. The size of page table  308 ′ is generally a multiple of 4 KB, its starting address is a multiple of its size, and it is located in storage that has limited access, i.e. it is accessible only to the operating system. VSID  410  and virtual page number  404  form an index into the page table  308 ′. The page table  308 ′ then has a corresponding real page number  502 . The real page number  502  forms the higher order bits of the real address. The byte address information  406  is translated directly from the virtual address  306 .  
         [0037]      FIG. 6  illustrates the operation of the virtual to real page number mapping. The virtual page number  306  is used to look up a corresponding page table entry  602 . Each page table entry, e.g.,  502   a ,  502   b ,  502   c , contains a real page number, and page protection bits  604 . The page protection bits  604  indicate, for example, whether a page can be read, written, etc. The high order 26 bits (i.e. 0-25) of the page table entry form the real page number  502 . In addition to forming the real page address, the high order bits may also provide an indication of the security level of the page. Notably, various bits in the bits  0 - 11  (bits  606 ) provide an indication of whether a page is encrypted, protected, or neither. Additionally, the bits provide other information for encrypting and protecting a page of memory. The information stored in the real page number, including the security bits, form part of the address  310 .  
         [0038]     Turning to  FIG. 7 , the security system in accordance with an aspect of the invention is further illustrated.  FIG. 7  provides a block diagram that illustrates some of the functions performed by the security system. Nevertheless, various aspects of an implementation may vary, for example the decision box  718  may be implemented as a logic circuit. Other features may also be implemented in a variety of ways. In any event, the figure does serve to illustrate the general functionality performed in accordance with aspects of the invention.  
         [0039]     As indicated, bits  0  and  1  indicate whether the addressed location is protected or encrypted. In the present illustrative embodiment, the protection is controlled on a page level inasmuch as a single page table entry is shared by all of the memory addresses in a single page. As such, all of those memory locations are subject to the same security level. If bit  0  is set, then protection is enabled. Similarly, if bit  1  is set, then encryption is enabled.  
         [0040]     If encryption is not enabled, then gate  722  is enabled and gate  720  is disabled and the data  700  is stored as plaintext block  724  in memory  112 . On the other hand, if encryption is enabled, then data  700  moves as plaintext block  726  into the encryption engine  714 . The security engine state  710 , e.g., encryption keys and so on, are applied by the encryption engine  714  to produce ciphertext block  726 ′. The encryption technique applied can be any one of the well know encryption algorithms such as AES or some variant thereof. The relevant point is that the encryption engine is driven by the address information stored in the page table. As such, a page of memory can be set as encrypted directly through the address information.  
         [0041]     If protection is enabled (may or may not be encrypted), then a secure memory offset is determined and a hash of the data is also enabled. The secure memory offset can be a combination of the address information. Here for example, bits stored in the higher order bits, e.g., bits  3 - 8 , are combined with lower order bits  26 - 34  to provide an offset into secure memory. This offset provides where the integrity check values should be stored in secure memory. In addition to the secure memory offset, a hash function is applied to the data  700 . The hash can be a function of the ciphertext, the plaintext, or both. The particular hash function can be a secure hash function and can be any such function that is a function of data  700  but that is reduced in size. The calculated hash  728  is stored in the location in secure memory  716  pointed to by the secure memory offset  712 . Thereafter, when the data (as ciphertext  726 ′ or plaintext  724 ) is stored in memory  112  (unsecure memory), the hash value can be used to determine whether that data has been altered in memory  112 . The hash value is recalculated when the data is retrieved from memory  112  and compared to the stored hash value to determine consistency. An inconsistent value would be indicative of an unauthorized change in the data while stored in memory  112 .  
         [0042]      FIG. 8  illustrates the reverse operation of retrieving encrypted and/or protected data from memory  112 . Here, either encrypted  726 ′ or plaintext  724  data is retrieved from memory  112 . Again, the high order bits in the real address indicate the type of security to be applied. If bit  1  is set, then the data is gated through gate  820  as ciphertext (i.e., it had previously been stored as ciphertext). If bit  1  is not set, then the plaintext  724  is gated through gate  822  and stored in cache  104 . Ciphertext  726 ′, as indicated by set bit  1 , is also fed into the decryption engine  714  where it is decrypted into plaintext  726  and stored in cache  104 .  
         [0043]     If the protection bit  0  is set, then the hash value  802  is calculated on the data retrieved from memory  112 . In this example, the data is plaintext  726  is hashed; however, the hash function could be applied to the ciphertext data  726 ′ and/or plaintext data. Moreover, the protection scheme could be used without encryption. The calculated hash  802  is compared to the stored hash  728  that is retrieved from secure memory  716  as pointed to by secure memory offset  712 . If the stored hash  728  and the calculate hash are not identical, then a security exception  808  is generated indicating that the memory has been altered.  
         [0044]     Referring back to  FIG. 2 , the address bus  28  that connects the bus interface to system memory  112  preferably truncates the high order bits that are used to address memory  112 . This address is referred to as a physical address because it is the actual address used to address memory  112 . In the example implementation described herein, preferably, the twelve high-order bits ( 0 - 11 ) are truncated. That truncation would leave bits twelve through forty-one to make up the physical address.  
         [0045]     The present invention provides a system and method for ensuring the integrity and security of data stored in system memory  112 . By employing the address bits to indicate the security measures to apply to data stored in memory  112 . The security measures can be directly stored in the address translation tables without the need for a separate table that associates data with a particular security measure.  
         [0046]     The above system and method are an example description only and are not intended to indicate that a particular addressing scheme or processor architecture is required. Rather, the example is intended to indicate the use of address bits to determine security measures generally.  
         [0047]     Elements of embodiments of the invention described below may be implemented by hardware, firmware, software or any combination thereof. The term hardware generally refers to an element having a physical structure such as electronic, electromagnetic, optical, electro-optical, mechanical, electromechanical parts, while the term software generally refers to a logical structure, a method, a procedure, a program, a routine, a process, an algorithm, a formula, a function, an expression, and the like. The term firmware generally refers to a logical structure, a method, a procedure, a program, a routine, a process, an algorithm, a formula, a function, an expression, and the like that is implemented or embodied in a hardware structure (e.g., flash memory, ROM, EROM). Examples of firmware may include microcode, writable control store, and micro-programmed structure. When implemented in software or firmware, the elements of an embodiment of the present invention are essentially the code segments to perform the necessary tasks. The software/firmware may include the actual code to carry out the operations described in one embodiment of the invention, or code that emulates or simulates the operations. The program or code segments can be stored in a processor or machine accessible medium or transmitted by a computer data signal embodied in a carrier wave, or a signal modulated by a carrier, over a transmission medium. The “processor readable or accessible medium” or “machine readable or accessible medium” may include any medium that can store, transmit, or transfer information. Examples of the processor readable or machine accessible medium include an electronic circuit, a semiconductor memory device, a read only memory (ROM), a flash memory, an erasable ROM (EROM), a floppy diskette, a compact disk (CD) ROM, an optical disk, a hard disk, a fiber optic medium, a radio frequency (RF) link, and the like. The computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc. The code segments may be downloaded via computer networks such as the Internet, Intranet, etc. The machine accessible medium may be embodied in an article of manufacture. The machine accessible medium may include data that, when accessed by a machine, cause the machine to perform the operations described in the following. The machine accessible medium may also include program code embedded therein. The program code may include machine readable code to perform the operations described in the following. The term “data” here refers to any type of information that is encoded for machine-readable purposes. Therefore, it may include programs, code, data, files, and the like.  
         [0048]     All or part of an embodiment of the invention may be implemented by hardware, software, or firmware, or any combination thereof. The hardware, software, or firmware element may have several modules coupled to one another. A hardware module is coupled to another module by mechanical, electrical, optical, electromagnetic or any physical connections. A software module is coupled to another module by a function, procedure, method, subprogram, or subroutine call, a jump, a link, a parameter, variable, and argument passing, a function return, and the like. A software module is coupled to another module to receive variables, parameters, arguments, pointers, etc. and/or to generate or pass results, updated variables, pointers, and the like. A firmware module is coupled to another module by any combination of hardware and software coupling methods above. A hardware, software, or firmware module may be coupled to any one of another hardware, software, or firmware module. A module may also be a software driver or interface to interact with the operating system running on the platform. A module may also be a hardware driver to configure, set up, initialize, send and receive data to and from a hardware device. An apparatus may include any combination of hardware, software, and firmware modules.  
         [0049]     Embodiments of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.  
         [0050]     Those skilled in the art also will readily appreciate that many additional modifications are possible in the exemplary embodiment without materially departing from the novel teachings and advantages of the invention. Any such modifications are intended to be included within the scope of this invention as defined by the following exemplary claims.