Abstract:
A data transfer apparatus and method that can make efficient use of a memory and a common bus by controlling a DMA controller through descriptor control, and can thereby achieve a data transfer with increased communication processing speed. The data transfer apparatus, which executes a DMA transfer by controlling the DMA controller through the use of a descriptor, includes: a first storage mechanism for storing descriptor common information that can be shared among a plurality of descriptors; a second storage mechanism for storing descriptor individual information that differs for each individual descriptor; and a conversion circuit for taking as inputs the descriptor common information read out of the first storage mechanism and the descriptor individual information read out of the second storage mechanism, and for outputting descriptor information to be supplied to the DMA controller.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a data transfer apparatus and method, and more particularly to a data transfer apparatus having a DMA (Direct Memory Access) controller, and a method for the same.  
           [0003]    2. Description of the Related Art  
           [0004]    In small computers, DMA transfer is employed which transfers data directly between an I/O device and a memory or between memories without the intervention of the CPU, and a DMA controller is used for such DMA transfer. Loaded with a memory address, transfer size, and other values, the DMA controller is activated to execute a DMA transfer.  
           [0005]    In recent years, a method for controlling the DMA controller through descriptor control has been proposed in order to prevent system efficiency degradation which can occur when the host system controls data transfers in real time (refer, for example, to Japanese Unexamined Patent Publication No. 5-204829).  
           [0006]    [0006]FIG. 20 is a format diagram showing one example of a descriptor format according to the prior art. In the example shown here, one address information (AD) and one byte count information (BC) are paired to form one descriptor information.  
           [0007]    The address information (AD) indicates the starting point (address) of the DMA transfer data stored in a storage mechanism, and consists of 32 bits (bits  31  to  00 ). The byte count information (BC) indicates the amount of the DMA transfer data, and consists of 32 bits (bits  31  to  00 ) of which bits  31  to  14  are reserved bits and bits  13  to  00  are the actual byte count bits.  
           [0008]    [0008]FIG. 21 is a schematic diagram showing one example of the structure of a descriptor storage mechanism for storing the descriptor shown in FIG. 20. The descriptor storage mechanism shown here can hold a plurality of descriptors (in the illustrated example, five descriptors indicated by i=1, 2, . . . , 5) each comprising address information ADi and byte count information BCi.  
           [0009]    [0009]FIG. 22 is a diagram for explaining how the DMA controller fetches descriptor information according to the prior art. The DMA controller and the descriptor storage mechanism are connected via a common bus, and the DMA controller reads, via the common bus, the address information and the byte count stored in the descriptor storage mechanism. The DMA controller executes a DMA transfer based on the thus readout address information and byte count.  
           [0010]    [0010]FIG. 23 is a format diagram showing another example of the descriptor format according to the prior art. In the example shown here, one address information (AD), one byte count information (BC), and one next descriptor address (ND) together constitute one descriptor information.  
           [0011]    The difference from the example shown in FIG. 20 is that, in FIG. 23, bit  31  in the byte count information (BC) is used as a chain bit (C). This chain bit is a bit that indicates whether a plurality of DMA transfers are to be executed in succession, that is, a descriptor chain is to be executed; when this bit is ON, the next descriptor address is carried in the next area. The next descriptor address indicates the storage location of the descriptor information to be read next.  
           [0012]    [0012]FIG. 24 is a schematic diagram showing one example of the structure of a descriptor storage mechanism for storing the descriptor show in FIG. 23. As shown, the descriptor storage mechanism can hold a plurality of descriptors (in the illustrated example, five descriptors indicated by i=1, 2, . . . , 5) each comprising address information ADi, byte count information BCi, and a next descriptor address NDi.  
           [0013]    [0013]FIG. 25 is a diagram for explaining how the DMA controller fetches the descriptor information stored in the descriptor storage mechanism of FIG. 24. As shown in FIG. 25, when a descriptor chain is supported, the DMA controller executes a DMA transfer by fetching the next descriptor address in addition to the address information and the byte count.  
           [0014]    Here, when the descriptor information is stored in its entirety in the descriptor storage mechanism as described above, if the storage areas, etc. for DMA control are large in size or in number, the amount of information carried in the descriptor becomes large, necessitating a corresponding increase in the size of the storage mechanism for storing the descriptor information, and hence resulting in an increase in the amount of hardware.  
           [0015]    Furthermore, when the amount of information carried in the descriptor becomes large, as the number of transfers of the descriptor information increases, the number of times the common bus is used increases, making the common bus unavailable for other processing operations; this can result in a degradation of system performance.  
           [0016]    On top of that, if a descriptor chain is to be executed, as the next descriptor address becomes necessary, the amount of information carried in the descriptor further increases, requiring an increase in the size of the storage mechanism for storing the descriptor information, and as a result, the amount of hardware further increases.  
           [0017]    Furthermore, when the next descriptor address is added, the number of transfers of the descriptor information increases, increasing the number of times the common bus is used and thus making the common bus unavailable for other processing operations; this can result in a further degradation of system performance.  
         SUMMARY OF THE INVENTION  
         [0018]    The present invention has been devised in view of the above problems, and an object of the invention is to provide a data transfer apparatus and method that can make efficient use of the memory and the common bus and can achieve increased communication processing speed.  
           [0019]    To achieve the above object, according to one aspect of the present invention, there is provided a data transfer apparatus which executes a DMA transfer by controlling a DMA controller through the use of a descriptor, comprising: a first storage mechanism for storing descriptor common information that can be shared among a plurality of descriptors; a second storage mechanism for storing descriptor individual information that differs for each individual descriptor; and a conversion circuit for taking as inputs the descriptor common information read out of the first storage mechanism and the descriptor individual information read out of the second storage mechanism, and for outputting descriptor information to be supplied to the DMA controller.  
           [0020]    Preferably, according to the invention, the first storage mechanism is capable of storing a plurality of sets of the descriptor common information.  
           [0021]    Preferably, according to the invention, the descriptor individual information includes selection information for selecting one of the plurality of sets of the descriptor common information.  
           [0022]    Preferably, according to the invention, the descriptor common information includes information concerning a high-order address part of an address at which a DMA transfer is to be started.  
           [0023]    Preferably, according to the invention, the descriptor individual information includes information concerning a low-order address part of the address at which the DMA transfer is to be started.  
           [0024]    Preferably, according to the invention, the conversion circuit selects one of the plurality of sets of the descriptor common information based on the input descriptor individual information, creates address information by combining the high-order address part in the selected descriptor common information with the low-order address part in the descriptor individual information, and supplies the address information to the DMA controller.  
           [0025]    Preferably, according to the invention, the descriptor individual information includes information concerning a byte count indicating the amount of DMA transfer data.  
           [0026]    Preferably, according to the invention, the descriptor individual information includes chain information indicating the presence or absence of a descriptor chain.  
           [0027]    Preferably, according to the invention, the second storage mechanism has a FIFO structure for storing a plurality of sets of the descriptor individual information.  
           [0028]    According to another aspect of the present invention, there is provided a data transfer method for causing a DMA controller to execute a DMA transfer by controlling the DMA controller through the use of a descriptor, comprising the steps of: (a) storing, in a first storage mechanism, descriptor common information that can be shared among a plurality of descriptors; (b) storing, in a second storage mechanism, descriptor individual information that differs for each individual descriptor; and (c) generating descriptor information to be supplied to the DMA controller, based on the descriptor common information read out of the first storage mechanism and on the descriptor individual information read out of the second storage mechanism.  
           [0029]    With the above-described configuration, the necessary storage area, and hence the amount of hardware, can be reduced by separating the descriptor information into common information and individual information and storing them separately. Furthermore, as the descriptor common information need not be transferred each time a data transfer occurs, the amount of information to be transferred can be reduced, and bus usage thus decreases. As a result, the bus can be used for other processing operations, which serves to improve system performance.  
           [0030]    Further, in the configuration supporting a descriptor chain, a chain bit indicating the presence or absence of a descriptor chain is provided in the descriptor information, and the storage mechanism for storing the descriptor information is constructed in a FIFO structure with provisions made to automatically select the next descriptor in the FIFO when the chain bit is ON; this configuration eliminates the need for the next descriptor address and serves to reduce the amount of information to be carried in the descriptor, and hence the size of the storage mechanism for storing the descriptor information can be reduced, achieving a reduction in the amount of hardware. Furthermore, as there is no need to transfer the next descriptor address, bus usage decreases, increasing the availability of the common bus for other processing operations, and system performance can thus be improved. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0031]    Further features and advantages of the present invention will be apparent from the following description with reference to the accompanying drawings, in which:  
         [0032]    [0032]FIG. 1 is a block diagram showing the functional configuration of a first embodiment of a LAN card to which the present invention is applied;  
         [0033]    [0033]FIGS. 2A and 2B are format diagrams showing the formats of descriptor common information and descriptor individual information, respectively;  
         [0034]    [0034]FIGS. 3A and 3B are block diagrams showing the structures of a first descriptor storage mechanism and a second descriptor storage mechanism, respectively;  
         [0035]    [0035]FIG. 4 is a block diagram showing the functional configuration of a descriptor conversion circuit;  
         [0036]    [0036]FIG. 5 is a flowchart illustrating the descriptor common information transfer operation performed by a control mechanism;  
         [0037]    [0037]FIG. 6 is a flowchart illustrating the descriptor individual information transfer operation performed by the control mechanism;  
         [0038]    [0038]FIG. 7 is a flowchart illustrating the DMA transfer operation performed by a DMA processor;  
         [0039]    [0039]FIG. 8 is a timing chart showing the transfer timing of the descriptor information according to the first embodiment;  
         [0040]    [0040]FIG. 9 is a timing chart showing the transfer timing of the descriptor information according to the prior art;  
         [0041]    [0041]FIG. 10 is a block diagram showing the configuration of one embodiment of a server equipped with LAN cards to which the present invention is applied;  
         [0042]    [0042]FIG. 11 is a block diagram showing the functional configuration of a second embodiment of a LAN card to which the present invention is applied;  
         [0043]    [0043]FIG. 12 is a flowchart illustrating the descriptor information transfer operation performed by the control mechanism according to the second embodiment;  
         [0044]    [0044]FIG. 13 is a flowchart (1/2) illustrating the DMA transfer operation performed by the DMA processor according to the second embodiment;  
         [0045]    [0045]FIG. 14 is a flowchart (2/2) illustrating the DMA transfer operation performed by the DMA processor according to the second embodiment;  
         [0046]    [0046]FIGS. 15A and 15B are format diagrams showing the formats of the descriptor common information and descriptor individual information, respectively, according to a third embodiment;  
         [0047]    [0047]FIGS. 16A and 16B are block diagrams showing the structures of the first descriptor storage mechanism and the second descriptor storage mechanism, respectively, according to the third embodiment;  
         [0048]    [0048]FIG. 17 is a diagram showing the functional configuration of the descriptor conversion circuit according to the third embodiment;  
         [0049]    [0049]FIG. 18 is a flowchart illustrating the DMA transfer operation performed by the DMA processor according to the third embodiment;  
         [0050]    [0050]FIG. 19 is a timing chart showing the transfer timing of the descriptor information (for the case of a descriptor chain) according to the prior art;  
         [0051]    [0051]FIG. 20 is a format diagram showing a descriptor format according to the prior art;  
         [0052]    [0052]FIG. 21 is a schematic diagram showing a descriptor storage mechanism according to the prior art;  
         [0053]    [0053]FIG. 22 is a diagram for explaining how a DMA controller fetches descriptor information according to the prior art;  
         [0054]    [0054]FIG. 23 is a format diagram showing another example of the descriptor format according to the prior art;  
         [0055]    [0055]FIG. 24 is a schematic diagram showing one example of the structure of a descriptor storage mechanism for storing the descriptor show in FIG. 23; and  
         [0056]    [0056]FIG. 25 is a diagram for explaining how the DMA controller fetches the descriptor information stored in the descriptor storage mechanism of FIG. 24. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0057]    The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.  
         [0058]    Embodiment 1  
         [0059]    [0059]FIG. 1 is a block diagram showing the functional configuration of one embodiment of a LAN card to which the present invention is applied. The LAN card is a communication control processing device which supports a connection to a LAN (Local Area Network). As shown, the LAN card proper  10  comprises an information processor  12 , a DMA (Direct Memory Access) processor  13 , and a PCI bus (Peripheral Component Interconnect Bus) interface  14  interconnected via a common bus  11 .  
         [0060]    The information processor  12  includes a control mechanism  18  and a storage mechanism  19 . The storage mechanism  19  is a device (memory) for storing software, data, etc. and includes a DMA transfer data storage area  20 . The control mechanism  18  is a device (CPU) for executing software instructions, and accomplishes the task of writing descriptor information to a first descriptor storage mechanism  21  and a second descriptor storage mechanism  22  within the DMA processor  13  and the task of writing DMA transfer data to the DMA transfer data storage area  20  within the storage mechanism  19 .  
         [0061]    The DMA processor  13  is a device incorporating a DMA controller  24 , and comprises descriptor storage areas, i.e., the first descriptor storage mechanism  21  for storing common information and the second descriptor storage mechanism  22  for storing individual information, and a descriptor conversion circuit  23  for converting the descriptor common information and descriptor individual information and for passing the converted information to the DMA controller  24 .  
         [0062]    The PCI bus interface  14  is a device for connecting the internal common bus  11  via a PCI card edge  17  to a PCI bus in the host external to the LAN card proper.  
         [0063]    The LAN card  10  further includes a MAC (Media Access Control)  15 . The MAC  15  is connected to the DMA processor  13  via an I/O bus  25 , and has functions for converting DMA transfer data into a prescribed frame format for transmission to the outside via a LAN interface  16 , and for decoding data received in a given frame format via the LAN interface  16  and thereby determining whether the data is addressed to the LAN card  10 .  
         [0064]    [0064]FIGS. 2A and 2B are format diagrams showing the descriptor format according to the present embodiment. The descriptor information is made up of the descriptor common information shown in FIG. 2A and the descriptor individual information shown in FIG. 2B. That is, one common information and one individual information are paired to form one descriptor information.  
         [0065]    The descriptor common information consists of 32 bits, and specifies/indicates the high-order two bytes (high-order address part) of the starting address in the transmission/reception of DMA transfer data. The alignment is done in units of 64 kbytes. Bits  31  to  16  form the high-order address area (Head address), and bits  15  to  00  are reserved bits.  
         [0066]    The descriptor individual information consists of 32 bits, and specifies/indicates the starting address select code, byte count, and low-order address in the transmission/reception of DMA transfer data.  
         [0067]    More specifically, bit  31  is a select bit (S); when the value of this bit is “0”, the descriptor common information A to be described later is selected as the starting address, while when the value is “1”, the descriptor common information B to be described later is selected as the starting address.  
         [0068]    Bit  30  is a reserved bit (R), bits  29  to  16  form a byte count area, i.e., a byte-length area, and bits  15  to  00  form an offset area, i.e., the low-order address area.  
         [0069]    [0069]FIGS. 3A and 3B are schematic diagrams showing the structures of the first descriptor storage mechanism  21  and the second descriptor storage mechanism  22 , respectively, according to the present embodiment. As shown, the descriptor information is separated into the descriptor common information and the descriptor individual information and stored in the respective storage mechanisms, that is, the common information is stored in the first descriptor storage mechanism (FIG. 3A) and the individual information in the second descriptor storage mechanism (FIG. 3B); here, a plurality of sets of descriptor common information and a plurality of sets of descriptor individual information can be held in the respective storage mechanisms.  
         [0070]    In FIGS. 3A and 3B, two sets of descriptor common information, designated A and B, are stored in the first descriptor storage mechanism  21 , and five sets of descriptor individual information, indicated at  1  to  5 , are stored in the second descriptor storage mechanism  22 , but it will be appreciated that the present invention is not limited to these examples.  
         [0071]    If the descriptor common information increases, for example, from two sets (A and B) to four sets (A, B, C, and D), the select area in the descriptor individual information will be expanded to the reserved bit  30  so that one set can be selected from among the four sets of descriptor common information.  
         [0072]    [0072]FIG. 4 is a conceptual diagram showing the functional configuration of the descriptor conversion circuit  23  according to the present embodiment. The descriptor conversion circuit  23  includes a selector  41  for selecting the high-order two bits of the starting address, that is, the high-order address part (Head address) in either the descriptor common information A or the descriptor common information B stored in the first descriptor storage mechanism  21 , whichever information is selected based on the value (Select) of the select area in the descriptor individual information.  
         [0073]    The descriptor conversion circuit  23  further includes a circuit  42  for creating address information by combining (merging) the selected high-order address (the high-order two bits of the starting address) with the low-order address, that is, the offset in the descriptor individual information, and a circuit  43  for extracting the byte count from the descriptor individual information.  
         [0074]    When descriptor individual information is input to the second descriptor storage mechanism  22 , the descriptor conversion circuit  23  performs a descriptor information conversion. That is, the descriptor conversion circuit  23  selects the head address, that is, the high-order address, in the descriptor common information selected based on the value (Select) of the select area in the input descriptor individual information, and creates address information by combining the high-order address with the low-order address, i.e., the offset in the descriptor individual information, while also creating byte count information by extracting the byte count from the descriptor individual information. The thus created address information and byte count information are sent to the DMA controller  24 .  
         [0075]    Operation of the LAN card having the above configuration according to the present embodiment will be described with reference to FIG. 1 and FIGS.  5  to  7 . FIGS.  5  to  7  are flowcharts illustrating the major operations of the LAN card according to the present embodiment: FIG. 5 is a flowchart illustrating the descriptor common information transfer operation performed by the control mechanism  18 , FIG. 6 is a flowchart illustrating the descriptor individual information transfer operation performed by the control mechanism  18 , and FIG. 7 is a flowchart illustrating the DMA transfer operation performed by the DMA processor  13 .  
         [0076]    First, in FIG. 5, the control mechanism  18  checks whether the common bus  11  is available for use (step  501 ); if the common bus  11  is available, the process proceeds to step  502 , but if the common bus  11  is not available, the process waits for a predetermined length of time until the common bus  11  becomes available.  
         [0077]    When the common bus  11  is available, the control mechanism  18  stores the descriptor common information in the first descriptor storage mechanism  21  within the DMA processor  13  via the common bus  11  (step  502 ), and proceeds to another process after storing the descriptor common information.  
         [0078]    Next, in FIG. 6, when a DMA transfer request occurs (step  601 ), the control mechanism  18  checks whether the common bus  11  is available for use (step  602 ); if the common bus  11  is available, the process proceeds to step  603 , but if the common bus  11  is not available, the process waits for a predetermined length of time until the common bus  11  becomes available.  
         [0079]    When the common bus  11  is available, the control mechanism  18  in step  603  stores the DMA target data in the DMA transfer data storage area  20  within the storage mechanism  19  in the information processor  12 , and thereafter proceeds to step  604 . Then, the control mechanism  18  stores the descriptor individual information in the second descriptor storage mechanism  22  within the DMA processor  13  (step  604 ), and proceeds to another process after storing the descriptor individual information.  
         [0080]    On the other hand, in FIG. 7, the DMA processor  13  is constantly checking whether any descriptor individual information has been written to the second descriptor storage mechanism  22  (step  701 ), and when new descriptor individual information is written, the process proceeds to step  702 .  
         [0081]    Then, the descriptor conversion circuit  23  reads the thus written descriptor individual information and the already stored descriptor common information and converts the information into the address information and the byte count in the format that can be recognized by the DMA controller  24  (step  702 ), and then sends the thus converted descriptor information (address information and byte count) to the DMA controller  24  (step  703 ).  
         [0082]    Next, the DMA controller  24  analyzes the converted descriptor information (address information and byte count) (step  704 ). Then, the DMA controller  24  checks whether the common bus  11  and the I/O bus  25  are available for use (step  705 ); if the common bus  11  and the I/O bus  25  are available, the process proceeds to step  706 , but if they are not available, the process waits for a predetermined length of time until the common bus  11  and the I/O bus  25  become available.  
         [0083]    When the common bus  11  and the I/O bus  25  are available, the DMA controller  24  identifies the DMA target data within the storage mechanism  19 , and executes the DMA transfer by using the common bus  11  and the I/O bus  25  in accordance with the analyzed descriptor information (step  706 ). When the transfer is completed, the DMA processor  13  waits until the next descriptor individual information is written.  
         [0084]    [0084]FIG. 8 is a timing chart showing the transfer timing of the descriptor information according to the present embodiment. In the figure, “A” and “B” designate the descriptor common information A and the descriptor common information B, respectively, and “ 1 ” to “ 5 ” indicate the respective descriptor individual information  1  to  5 . In the DMA transfer of the present embodiment, when sending the descriptor information to the DMA processor  13 , first the descriptor common information is sent, and thereafter, when a DMA transfer becomes necessary, only the descriptor individual information is sent.  
         [0085]    In the example of FIG. 8, the descriptor common information A and the descriptor common information B are sent on cycles τ 1  and τ 2 , respectively, after which the descriptor individual information  1  is sent on cycle τ 3 , the descriptor individual information  2  is sent on cycle τ 4 , the descriptor individual information  3  is sent on cycle τ 5 , the descriptor individual information  4  is sent on cycle τ 6 , and the descriptor individual information  5  is sent on cycle τ 7 , respectively. However, the way of sending the descriptor individual information is not limited to this example; in practice, the information is sent as required in accordance with a DMA transfer request.  
         [0086]    On the other hand, FIG. 9 is a timing chart showing the transfer timing of the descriptor information according to the prior art. In the figure, “AD 1 ” to “AD 5 ” indicate the address information in the respective descriptor information, and “BC 1 ” to “BC 5 ” indicate the byte count information in the respective descriptor information.  
         [0087]    In the DMA transfer of the prior art, when sending the descriptor information to the DMA processor, the address information and byte count information carried in each descriptor information are sent in series. That is, the address information in the descriptor information  1  is sent on cycle τ 1 , and the byte count information in the descriptor  1  is sent on cycle τ 2 .  
         [0088]    Likewise, the address information in the descriptor  2  is sent on cycle τ 3  and the byte count information in the descriptor  2  is sent on cycle τ 4 ; the address information in the descriptor  3  is sent on cycle τ 5  and the byte count information in the descriptor  3  is sent on cycle τ 6 ; the address information in the descriptor  4  is sent on cycle τ 7  and the byte count information in the descriptor  4  is sent on cycle τ 8 ; and the address information in the descriptor  5  is sent on cycle τ 9  and the byte count information in the descriptor  5  is sent on cycle τ 10 .  
         [0089]    In the DMA transfer of the prior art, the time required to transfer the information of all the descriptors  1  to  5  is the sum of τ 1  to τ 10 ; in contrast, in the present embodiment, the time required to transfer the information of all the descriptors  1  to  5  is the sum of τ 1  to τ 7 , achieving a reduction in the time the common bus is occupied, and hence an improvement compared with the prior art.  
         [0090]    In this way, according to the present embodiment, by extracting the common information from the descriptor information and storing it separately, the amount of hardware can be reduced. Furthermore, as the amount of information to be transferred on the common bus is reduced, common bus usage for the information transfer decreases, increasing the availability of the common bus for other processing operations, and a performance improvement can thus be expected.  
         [0091]    [0091]FIG. 10 is a block diagram showing the configuration of one embodiment of a server equipped with LAN cards to which the present invention is applied. In the figure, the server main unit  50  comprises a CPU  51 , a memory  52 , a hard disk drive (HDD)  53 , a bus interface  54 , and a plurality of LAN cards  10 ; here, the CPU  51 , the memory  52 , and the HDD  53  are interconnected via the bus interface  54 . Each LAN card  10  is connected to the bus interface  54  via a PCI bus  55 ; the LAN card can also be connected to an external LAN via a LAN cable  56 .  
         [0092]    Embodiment 2  
         [0093]    [0093]FIG. 11 is a block diagram showing the functional configuration of another embodiment of a LAN card to which the present invention is applied. The LAN card proper  10  shown here comprises an information processor  12 , a DMA (Direct Memory Access) processor  13 , and a PCI bus (Peripheral Component Interconnect Bus) interface  14  interconnected via a common bus  11 .  
         [0094]    The information processor  12  includes a control mechanism  18  and a storage mechanism  19 . The storage mechanism  19  is a device (memory) for storing software, data, etc. and includes a DMA transfer data storage area  20 , a first descriptor storage mechanism  21 , and a second descriptor storage mechanism  22 . The control mechanism  18  is a device (CPU) for executing software instructions, and accomplishes the task of writing descriptor information to the first descriptor storage mechanism  21  and the second descriptor storage mechanism  22  within the storage mechanism  19  and the task of writing DMA transfer data to the DMA transfer data storage area  20  within the storage mechanism  19 .  
         [0095]    The DMA processor  13  is a device incorporating a DMA controller  24 , and comprises a memory  30  for holding therein the received descriptor information, and a descriptor conversion circuit  23  for converting descriptor common information and descriptor individual information and for passing the converted information to the DMA controller  24 .  
         [0096]    The PCI bus interface  14  is a device for connecting the internal common bus  11  via a PCI card edge  17  to a PCI bus in the host external to the LAN card proper.  
         [0097]    The LAN card  10  further includes a MAC (Media Access Control)  15 . The MAC  15  is connected to the DMA processor  13  via an I/O bus  25 , and has functions for converting DMA transfer data into a prescribed frame format for transmission to the outside via a LAN interface  16 , and for decoding data received in a given frame format via the LAN interface  16  and thereby determining whether the data is one addressed to the LAN card  10 .  
         [0098]    In the present embodiment, the descriptor format is the same as that described in the first embodiment with reference to FIGS. 2A and 2B, the structures of the first and second descriptor storage mechanisms are the same as those shown in FIGS. 3A and 3B, and the functional configuration of the descriptor conversion circuit  23  is the same as that shown in FIG. 4; therefore, these will not be described here.  
         [0099]    Operation of the LAN card having the above configuration according to the present embodiment will be described with reference to FIG. 11 and FIGS.  12  to  14 . FIGS.  12  to  14  are flowcharts illustrating the major operations of the LAN card according to the present embodiment: FIG. 12 is a flowchart illustrating the descriptor information transfer operation performed by the control mechanism  18 , and FIGS. 13 and 14 are flowcharts illustrating the DMA transfer operation performed by the DMA processor  13 .  
         [0100]    First, in FIG. 12, when a DMA transfer request occurs (step  1201 ), the control mechanism  18  checks whether the common bus  11  is available for use (step  1202 ); if the common bus is available, the process proceeds to step  1203 , but if the common bus is not available, the process waits for a predetermined length of time until the common bus  11  becomes available.  
         [0101]    When the common bus  11  is available, the control mechanism  18  stores the DMA target data in the DMA transfer data storage area  20  within the storage mechanism  19  in the information processor  12  (step  1203 ), and proceeds to the next step  1204 . In step  1204 , the control mechanism  18  stores the descriptor common information and the descriptor individual information in the first and second descriptor storage mechanisms  21  and  22 , respectively, and proceeds to another process after storing the descriptor information. Here, if the descriptor common information is already stored in the first descriptor storage mechanism  21 , only the descriptor individual information is stored in the above step.  
         [0102]    On the other hand, in FIG. 13, the DMA processor  13  is constantly checking a timer or like means to determine whether a predetermined time has elapsed or not (step  1301 ), and each time the predetermined time elapses, the process proceeds to step  1302  to check whether the common bus  11  is available for use; if the common bus  11  is available, the process proceeds to step  1303 , but if the common bus  11  is not available, the process waits for a predetermined length of time until the common bus  11  becomes available.  
         [0103]    When the common bus  11  is available, the DMA processor  13  reads the first and second descriptor storage mechanisms  21  and  22  in the information processor  12  (step  1303 ) to check whether there is any new descriptor information stored in the descriptor storage mechanisms (step  1304 ); if there is newly stored descriptor information, the process proceeds to step  1305 , but if there is no newly stored descriptor information, the process returns to step  1301 .  
         [0104]    When there is newly stored descriptor information stored, it is checked whether the common bus  11  is available for use (step  1305 ); if the common bus  11  is available, the process proceeds to step  1306 , but if the common bus  11  is not available, the process waits for a predetermined length of time until the common bus  11  becomes available.  
         [0105]    Then, in step  1306  of FIG. 14, the descriptor common information and the descriptor individual information are read into the memory  30  from the descriptor storage mechanisms  21  and  22 . The descriptor conversion circuit  23  converts the descriptor common information and descriptor individual information into the address information and the byte count in the format that can be recognized by the DMA controller  24 , and sends the thus converted information to the DMA controller  24  (step  1307 ).  
         [0106]    Here, if provisions are made so that the descriptor common information once read out of the first descriptor storage mechanism  21  in the information processor  12  is stored and held in the memory  30  in the DMA processor  13 , the descriptor common information need be read out only that once, and there is no need to read out the common information after that. This serves to reduce the time the common bus is occupied.  
         [0107]    Next, the DMA controller  24  analyzes the converted descriptor information (address information and byte count) (step  1308 ), and checks whether the common bus  11  and the I/O bus  25  are available for use (step  1309 ); if the common bus  11  and the I/O bus  25  are available, the process proceeds to step  1310 , but if they are not available, the process waits for a predetermined length of time until the common bus  11  and the I/O bus  25  become available.  
         [0108]    When the common bus  11  and the I/O bus  25  are available, the DMA controller  24  identifies the DMA target data within the storage mechanism  19 , and executes the DMA transfer by using the common bus  11  and the I/O bus  25  in accordance with the analyzed descriptor information (step  1310 ). When the transfer is completed, the DMA processor  13  waits until the next descriptor is written.  
         [0109]    In the foregoing first embodiment, the first descriptor storage mechanism  21  for storing the descriptor common information and the second descriptor storage mechanism  22  for storing the descriptor individual information are both provided within the DMA processor  13 , while in the second embodiment, the first descriptor storage mechanism  21  and the second descriptor storage mechanism  22  are both provided within the information processor  12 ; alternatively, the first descriptor storage mechanism  21  for storing the descriptor common information may be provided within the DMA processor  13 , and the second descriptor storage mechanism  22  for storing the descriptor individual information may be provided within the information processor  12 .  
         [0110]    Embodiment 3  
         [0111]    Lastly, a third embodiment of a LAN card according to the present invention will be described. The basic configuration of the third embodiment is the same as that of the first embodiment shown in FIG. 1, except that modifications are made to the first embodiment to support a descriptor chain.  
         [0112]    [0112]FIGS. 15A and 15B are format diagrams showing the formats of the descriptor common information and descriptor individual information, respectively, according to the present embodiment. As can be seen from a comparison with FIGS. 2A and 2B relating to the earlier described first embodiment, the descriptor common information (FIG. 15A) in the present embodiment is the same as that (FIG. 2A) in the first embodiment.  
         [0113]    On the other hand, the descriptor individual information (FIG. 15B) in the present embodiment somewhat differs from that (FIG. 2B) in the first embodiment, in that bit  30  is used as a chain bit (C). This chain bit (C) is a bit that indicates whether a plurality of DMA transfers are to be executed in succession, that is, a descriptor chain is to be executed.  
         [0114]    [0114]FIGS. 16A and 16B are schematic diagrams showing the structures of the first descriptor storage mechanism  21  and the second descriptor storage mechanism  22 , respectively, according to the present embodiment. As can be seen from a comparison with FIGS. 3A and 3B relating to the earlier described first embodiment, the first descriptor storage mechanism  21  (FIG. 16A) in the present embodiment is the same as that (FIG. 3A) in the first embodiment.  
         [0115]    On the other hand, the second descriptor storage mechanism  22  (FIG. 16B) in the present embodiment somewhat differs from that (FIG. 3B) in the first embodiment, in that bit  30  is used as a chain bit (C). Further, in the present embodiment, the second descriptor storage mechanism  22  (FIG. 16B) employs a FIFO (First In First Out) structure.  
         [0116]    [0116]FIG. 17 is a diagram showing the functional configuration of the descriptor conversion circuit  23  according to the present embodiment. As can be seen from a comparison with FIG. 4, the descriptor conversion circuit of the present embodiment differs from the descriptor conversion circuit of the first embodiment by the inclusion of a circuit  44  for extracting the chain bit from the descriptor individual information.  
         [0117]    Next, the operation of the LAN card of the third embodiment that supports a descriptor chain will be described. The descriptor common information transfer operation performed by the control mechanism  18  is the same as that shown in the flowchart of FIG. 5 relating to the earlier described first embodiment, and the descriptor individual information transfer operation performed by the control mechanism  18  is also the same as that shown in the flowchart of FIG. 6 relating to the earlier described first embodiment.  
         [0118]    On the other hand, the DMA transfer operation performed by the DMA processor  13  will be as shown in the flowchart of FIG. 18. As can be seen from a comparison between the flowchart of FIG. 18 and the flowchart of FIG. 7 relating to the earlier described first embodiment, steps  1801  to  1806  in FIG. 18 are the same as the corresponding steps  701  to  706  in FIG. 7, but in FIG. 18, new steps  1807  and  1808  are added.  
         [0119]    In step  1807 , it is determined whether the chain bit is ON or not; if the chain bit is not ON, that is, if it is OFF, the process is terminated. On the other hand, if the chain bit is ON, the process proceeds to step  1808 . In step  1808 , the descriptor conversion circuit  23  reads the next descriptor individual information in the FIFO structure, selects the corresponding descriptor common information, and creates the address information and byte count in the format that can be recognized by the DMA controller  24 . After that, the process returns to step  1803 .  
         [0120]    In this way, in the descriptor chain according to the present embodiment, as the descriptor individual information storage mechanism is constructed in a FIFO structure and is configured to automatically select the next descriptor in the FIFO when the chain bit is ON, the next descriptor address is not needed. As a result, the amount of information to be carried in the descriptor decreases, and the size of the storage mechanism for storing the descriptor information decreases accordingly, thus achieving a reduction in the amount of hardware.  
         [0121]    The timing chart for the transfer timing of the descriptor information according to the present embodiment is the same as that shown in FIG. 8 relating to the earlier described first embodiment. On the other hand, if the descriptor chain is to be supported using the next descriptor address and without separating the descriptor information into the common information and individual information, as in the prior art shown in FIG. 24, the transfer timing of the descriptor information will be as shown in FIG. 19.  
         [0122]    As is apparent from a comparison between FIG. 8 and FIG. 19, since there is no need to transfer the next descriptor address in the present embodiment, bus usage decreases, increasing the availability of the common bus for other processing operations, and system performance can thus be improved.  
         [0123]    While specific embodiments of the invention have been described with reference to drawings, it will be appreciated that various modifications can be made by those skilled in the art; for example, the present invention can be applied to various data transfer devices other than the LAN card, and other communication networks such as ADSL networks can also be employed instead of the LAN.  
         [0124]    The present invention has been described specifically dealing with embodiments in which the invention is applied to the DMA controller incorporated in a LAN card, but it will be recognized that the invention is not limited to the specific embodiments disclosed herein; for example, the invention can be applied extensively to self-contained general-purpose DMA controllers or to various terminals, workstations, etc. that form computer networks.  
         [0125]    As described above, according to the present invention, by separating the descriptor information into common information and individual information and storing them separately, the necessary storage area can be reduced, which contributes to reducing the amount of hardware. Furthermore, as the descriptor common information need not be transferred each time a data transfer occurs, the amount of information to be transferred can be reduced, and bus usage thus decreases. As a result, the bus can be used for other processing operations, which serves to improve system performance.  
         [0126]    Further, as a FIFO structure is employed in the descriptor chain, the next descriptor address is not needed; as a result, the amount of information to be carried in the descriptor decreases, and the size of the storage mechanism for storing the descriptor information decreases accordingly, achieving a reduction in the amount of hardware. Furthermore, as there is no need to transfer the next descriptor address, bus usage decreases, increasing the availability of the common bus for other processing operations, and system performance can thus be improved.  
         [0127]    The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiment is therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.