Abstract:
A power-on sense circuit accurately senses a power-on condition when a power supply voltage exceeds a desired trigger voltage level. The power-on sense circuit includes a voltage-to-current converter circuit and a beta-multiplier reference circuit. The voltage-to-current converter circuit and the beta-multiplier reference circuit generate currents that relate to the power supply voltage. By sensing a balanced current operating condition with the beta-multiplier reference circuit, the power-on sense circuit determines when a desired trigger voltage has been achieved. The trigger voltage level has a zero temperature coefficient at median operating temperatures, and has a slightly downward curvature shape without the need for high-current resistor-dividers or bandgap circuits. The power-on sense circuit may be adapted for use as a power-on reset signal. By adding an amplifier stage to the outputs signal, the power-on sense circuit may also be used as an analog reference voltage generator. The design of the power-on sense circuit is scalable and may be used under low-voltage and low-current operating conditions.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method and apparatus for detecting a power-on condition in an electronic circuit. In particular, the present invention relates to electronic power-on sense circuits that operate under low power and low current conditions. 
     BACKGROUND OF THE INVENTION 
     Various power-on detector circuits are used in electronic systems to ensure that a predictable power-up condition can be achieved. In digital circuits, it is possible that a digital logic circuit may find a trapped state or other undetermined condition during power up. Similarly, in analog circuits, a particular circuit may find a condition where transistors lock themselves in an off condition during power. Start-up and logic initialization problems may be avoided by incorporating circuitry into the electronic system that initializes each of the various circuits to a known condition. A predictable power-on reset circuit may be employed to detect the power-on condition and appropriately initialize the various circuits during a power-on sequence. 
     SUMMARY OF THE INVENTION 
     Briefly stated, in accordance with the present invention a power-on sense circuit accurately senses a power-on condition when a power supply voltage exceeds a desired trigger voltage level. The power-on sense circuit includes a voltage-to-current converter circuit and a beta-multiplier reference circuit The voltage-to-current converter circuit and the beta-multiplier reference circuit generate currents that relate to the power supply voltage. By sensing a balanced current operating condition with the beta-multiplier reference circuit, the power-on sense circuit determines when a desired trigger voltage has been achieved. The trigger voltage level has a zero temperature coefficient at median operating temperatures, and has a slightly downward curvature shape without the need for high-current resistor-dividers or bandgap circuits. The power-on sense circuit may be adapted for use as a power-on reset signal. By adding an amplifier stage to the output signal, the power-on sense circuit may also be used as an analog reference voltage generator. The design of the power-on sense circuit is scalable and maybe used under low-voltage and low-current operating conditions. 
     According to a feature of the invention, an apparatus for sensing a power-on condition in an electronic system having a power supply with an associated power supply voltage, includes: a first circuit that produces a first current in response to the power supply voltage, a second circuit that produces a second current that is a beta multiple of the first current, and a third circuit that produces an output signal in response to comparing the first current to the second current such that the output signal indicates the power-on condition when the power supply voltage reaches a trigger voltage. The first, second and third circuits may be combined into a single circuit. The first circuit may include a transistor having a gate connected to the power supply voltage such that the transistor conducts the first current by converting the power supply voltage to the first current. Similarly, the gate connection of the transistor may be coupled to another voltage that is related to the power supply voltage such that another current is produced by the transistor responsive to the power supply voltage. The first circuit may also include a current mirror circuit that produces the first current in response to another current that is related to the power supply voltage. 
     According to a further feature of the invention, the source of the transistor in the first circuit is coupled to a circuit ground through a fourth circuit. The fourth circuit may include at least one of a resistor, a transistor, and a diode. The fourth circuit is arranged to change the trigger voltage by changing the voltage that appears at a source terminal of the transistor relative to the transistors gate voltage. 
     According to another feature of the invention, the output signal is generated when currents are balanced in the first and second circuits. The second circuit is a beta-multiplier circuit. The second circuit includes a first transistor and a second transistor that share a common gate connection, wherein a ratio is associated with the beta of the first transistor and the beta of the second transistor, and the ratio is different from unity such that the first transistor and the second transistor have balanced currents at the trigger voltage. The first and second transistors are arranged to operate in weak inversion when the power supply voltage is at the trigger voltage. Also, the second circuit includes a resistor that is coupled between the source of the second transistor and a circuit ground. The first and second transistors operate at a bias point between square-law operation and exponential operation when the power supply voltage is at the trigger voltage. The output signal has a substantially zero temperature coefficient for median temperatures. An amplifier circuit may be adapted to produce an analog reference signal in response to the output signal. Also, an inverter circuit may be employed to produce a digital signal in response to the output signal. A capacitor may be coupled to the apparatus and arranged to couple the power supply voltage to at least one of the first, second, and third circuits such that the output signal is initialized to an operating state and changes in the power supply voltage require a transition time before the output signal changes to another operating state. 
     According to another feature of the invention, a method of sensing a power-on condition in an electronic system, includes: converting a power supply voltage to a sense current that is related to the power supply voltage, mirroring the sense current to produce a second current, generating a reference current that is a beta multiple of the second current, comparing the reference current to the second current, and producing an output signal in response to comparing the reference current to the second current such that the output signal indicates a first operating state when the power supply voltage is a first voltage, and a second operating state when the power supply voltage is a second voltage different from the first voltage whereby the power-on condition is sensed when the output signal indicates the second operating state. Generating the reference current includes conducting the second current with a first transistor and conducting the reference current with a second transistor that is a beta multiple of the first transistor. 
     According to still another feature of the invention, an apparatus for sensing a power-on condition, includes: a means for producing a first current related to a power supply voltage, a means for producing a second current that is a beta multiple of the first current, a means for producing an output signal that is responsive to a comparison between the first current and the second current such that the output signal indicates a power-on condition when the power supply voltage is at a trigger voltage. The apparatus may further include means for generating one of a digital signal and an analog reference voltage from the output signal. 
     A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a power-on sensor in accordance with the present invention; 
     FIG. 2 is a schematic diagram of a power-on sensor in accordance with a first embodiment of the present invention; 
     FIG. 3 is a schematic diagram of a power-on sensor in accordance with a second embodiment of the present invention; 
     FIG. 4 is a schematic diagram of a reference generator in accordance with a third embodiment of the present invention; and 
     FIG. 5 is a graph of signal waveforms in accordance with an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention uses a voltage-to-current converter to sense the power supply condition, and a beta-multiplier reference current to determine when a power-on condition has been achieved. By comparing the current that is related to the power supply voltage to a reference current, the power-on condition is sensed. The result of the comparison can be used to generate a digital signal indicating a power-on signal or an analog reference voltage. The design is scalable to lower and higher trigger voltages, and uses very little power. 
     FIG. 1 is a block diagram of an exemplary power-on sensor in accordance with the present invention. A voltage-to-current converter ( 101 ) produces a sense current (ISNS) that is related to a power supply voltage (VPWR). A beta-multiplier reference current generator ( 102 ) produces a reference current (IREF). A current comparator ( 103 ) produces an output signal (OUT) in response to the sense current (ISNS) and the reference current (IREF). Although the voltage-to-current converter ( 101 ), the beta-multiplier reference current generator ( 102 ), and the current comparator ( 103 ) are shown as different blocks, it is understood and appreciated that the blocks may be combined without departing from the present invention. 
     First Embodiment 
     FIG. 2 is a schematic diagram of a power-on sensor in accordance with a first embodiment of the present invention. As shown in the figure, the power-on sensor includes five PMOS transistors (MP 21 -MP 25 ), five NMOS transistors (MN 21 -MN 25 ), and a resistor (R 2 ). PMOS transistor MP 21  has a gate and drain connected to node N 201  (CTL 2 ), and a source connected to VDD. NMOS transistor MN 21  has a gate connected to VDD, a drain connected to node N 201 , and a source connected to VSS. PMOS transistor MP 22  has a source connected to VDD, a gate connected to node N 201  and a drain connected to node N 202 . NMOS transistor MN 22  has a drain and gate connected to node N 202 , and a source connected to VSS. PMOS transistor MP 23  has a gate and drain connected to node N 203 , and a source connected to VDD. NMOS transistor MN 23  has a gate connected to node N 202 , a drain connected to node N 203 , and a source connected to VSS. PMOS transistor MP 24  is two transistors connected in parallel with one another, each transistor having a gate connected to node N 203 , a drain connected to node N 205  (LoHi 2 ), and a source connected to VDD. NMOS transistor MN 24  is eight transistors connected in parallel with one another, each transistor having a gate connected to node N 202 , a drain connected to node N 205 , and a source connected to N 204  (VR 2 ). Resistor R 2  is connected between node N 204  and VSS. PMOS transistor MP 25  has a gate connected to node N 205 , a drain connected to OUT 2  and a source connected to VDD. NMOS transistor MN 25  has a gate connected to node N 205 , a drain connected to OUT 2 , and a source connected to VSS. 
     Transistor MN 21  is configured to act as a voltage-to-current conversion device providing a current (I 21 ) to a mirror pair formed with transistors MP 21  and MP 22 . 
     The W/L (width/length) ratio of transistor MN 21  will determine the voltage-to-current conversion level and set an operating current level over a specified operating range. For trigger levels at higher power supply voltages, the W/L ratio of transistor MN 21  may be reduced. In applications where the operating currents may be increased, the circuit device sizes may be reduced to conserve chip area. A variety of voltage-to-current conversion circuits may be used in substitution of the arrangement shown with regards transistor MN 21 . 
     Transistor MP 22  is configured to mirror the current flowing in transistor MP 21 . Transistors MP 22  and MN 22  conduct a current ( 122 ) that is proportional to the current ( 121 ) flowing in transistor MP 21 . When transistors MP 21  and MP 22  are the same size, currents  121  and  122  will be equal to one another. Transistors MN 22  and MN 23  are configured as another current mirror such that transistor MN 23  conducts a current (I 23 ) that is proportional to the current ( 122 ) flowing in transistor MN 22 . When transistors MN 22  and MN 23  are the same size, currents  122  and I 23  will be equal to one another. 
     Transistors MN 23  and MN 24 , and R 2  are configured as a beta-multiplier reference circuit, where MN 24  is eight transistors of equal size (to MN 23 ) connected in parallel to one another. When the current in MN 23  balances the current in MN 24 , then the balanced currents are the reference current, and the node LoHi 2  is at a trigger level midway between the power supply voltages (VDD, VSS). 
     Transistors MP 25  and MN 25  form an inverter cell with an input at the LoHi 2  node, and an output at the OUT 2  node. 
     Transistors MP 23  and MP 24  are configured as another current mirror where MP 24  is two transistors of equal size (to MP 23 ) connected in parallel to one another. Transistor MP 24  conducts a current (I 24 ) that is twice die current (I 23 ) in Resistor MP 23 . Although FIG. 2 shows transistor MP 24  as two transistors in parallel with one another (m=2), any number of transistors may be employed as is necessary to set a correct trip point for the power-on sense circuit. 
     The operation of the circuit shown in FIG. 2 will be discussed with reference to the signal waveforms shown in FIG.  5 . At time T 0 , the power supply voltage (VDD) is at the same potential as VSS, and the output signal (OUT 2 , shown as OUT in FIG. 5) is at the same potential as VDD. The outputs signal (OUT 2 ) will remain high until the voltage at the LoHi 2  (N 205 ) node transitions from low to high, indicating that the power-on sequence is complete. 
     The power supply voltage (VDD) increases from time T 0  through T 1 , causing the currents  121  and  122  to increase accordingly. The  122  current is mirrored by MN 22 , MN 23 , and MN 24 . The current mirrored by MP 23  and MP 24  is twice that of I 23  (m=2 for MP 24 ). Since MN 24  can support four times the current I 24  (m=8 for MN 24 ), at low current levels, the drain of transistor MN 24  holds LoHi 2  at a low logic level. As the power supply voltage increases, the current levels increase and a significant IR drop develops across resistor R 2 . The increased voltage drop across resistor R 2 , results in current I 23  increasing at a rate faster than the current levels supported by transistor MN 24 . 
     Eventually the currents (I 23 , I 24 ) reach the reference current level where the currents I 23  and I 24  are balanced. When the currents (I 23  and I 24 ) are balanced the node LoHi 2  is at a potential midway between the power supply rails. The power supply voltage that generates this balanced current value is the trigger voltage for the current comparator ( 103  in FIG.  1 ). 
     As the power supply voltage continues to increase beyond the trigger voltage the current levels rise above the reference current level. Once the currents rise above the reference level, transistor MN 24  and resistor R 2  can no longer sink all the current that transistor MP 24  provides. Then, node LoHi 2  continues to rise to the high power supply voltage (VDD) and OUT 2  transitions to a low logic level. 
     Transistors MN 23  and MN 24  are operated in weak inversion at the trigger level such that the trigger voltage occurs at a bias point that is between square-law operation and exponential operation. The first end point is calculated according to square-law operation as:              VDDT1   =       y       R   2     *   Kpn       +     Vthn   21               (   1   )               y   =         2   *   x           W   N23       L   N23       *       W   N21       L   N21                     (   2   )               x   =           (     1   -       n   m         )     2     *   2         n   2     *     b   2                 (   3   )               m   =       β   N24       β   N23               (   4   )               n   =   2           (   5   )                                
     VDDT 1  corresponds to the low end point of the trigger voltage. Parameter n corresponds to the ratio of the current in transistor MP 24  and MP 23  (shown as  2  in FIG.  2 ). Parameter m corresponds to the ratio of beta for transistors MN 24  and MN 23 . Beta is determined by the equation beta=Kp*(W/L). Kpn is the transconductance of an NMOS transistor (based on mobility and oxide capacitance), and Vthn 21  is the threshold voltage of transistor MN 21 . The W and L parameters correspond to the geometric sizes of transistors MN 23  and MN 21 . The parameter b relates to the body effect for transistor MN 24 , and is modeled as a factor that increases resistor R 2 . In one example of this application b=1.44, n=2, m=8, R=580 KΩ, VDDT 1 may be on the order of 1.5V. 
     The second end point of operation is weak inversion operation, where the trigger voltage is calculated according to an exponential law operation as:              VDDT2   =       h   *       Vu       R   2     *   Kpn           +     Vthn   21               (   6   )               h   =         2   *   eta   *     ln        (     m   n     )                 W   21       L   21                   (   7   )                                
     VDDT  2  corresponds to the high end point of the trigger voltage. As before, parameter n corresponds to the ratio of the current in transistor MP 24  and MP 23  (shown as  2  in FIG.  2 ), and parameter m corresponds to the ratio of beta for transistor MN 24  and MN 23 . Kpn is the transconductance for an NMOS transistor (based on mobility and oxide capacitance), and Vthn 21  is the threshold voltage of transistor MN 21 . Vu is the thermal voltage (26 mV at 300 deg K). Eta is the sub-threshold slope coefficient and in one example is equal to 1.68 for an NMOS transistor. For the same MOS process described previously, VDDT 2  may be on the order of 2.6V. The actual trigger voltage lies between VDDTl and VDDT 2  at roughly 2.0V. 
     Resistor R 2  and transistors MN 23  and MN 24  are at the core of the beta multiplier cell. Transistor MN 24  is a beta multiple of transistor MN 23 . In one example, at the trigger voltage, a voltage of 59 mV appears across a 580 KΩ resistor and corresponds to a current of roughly 102 nA. 
     The above embodiment is a temperature compensated power-on-detector with two different temperature coefficients based on the operating region. For the square law region of operation, the temperature coefficient is given by:        TC_VDDT1   =         (       -   y         R   2     *   Kpn       )     *     (     TC_Kpn   +     TC_R   2       )       +     TC_Vthn   21                              
     For the exponential region of operation, the temperature coefficient given by:        TC_VDDT2   =         (     0.5   *   h   *       Vu       R   2     *   Kpn           )     *     (     TC_Vu   -     TC_R   2     -   TC_Kpn     )       +     TC_Vthn   21                              
     The sign of TC_VDDT 1  and TC_VDDT 2  are opposite in direction. The opposite signed temperature coefficients results in a trigger voltage with a zero temperature coefficient for median temperatures, and has a downward temperature curvature. The temperature curvature is balanced when the low temperature and high temperature values are equal. 
     The temperature curvature is adjusted by changing the W/L ratio of transistors MN 23  and MN 24 . When the length (L) of transistors MN 23  and MN 24  are increased, the temperature curve tilts forward towards the square-law operational region (TC_VDDT  1 ). Increased lengths produces larger overdrive voltages on MN 23  and MN 24 . Also, the increased lengths result in the temperature coefficients of R 2 _TC and Kpn_TC canceling one another, leaving Vthn_TC as a dominant temperature coefficient. When the length (L) of transistors MN 23  and MN 24  are decreased, the temperature curve tilts backwards towards the exponential operational region (TC_DDT 2 ). By adjusting the lengths of the transistors, the temperature curvatures can be adjusted so that a zero temperature curve result can be achieved for a wide range of trigger voltages. 
     Second Embodiment 
     FIG. 3 is a schematic diagram of a power-on sensor in accordance with a second embodiment of the present invention. As shown in the figure, the power-on sensor includes four PMOS transistors (MP 31 , MP 33 -MP 35 ), four NMOS transistors (MN 31 , MN 33 -MN 35 ), a resistor (R 3 ), and a capacitor (C 3 ). PMOS transistor MP 31  has a gate and drain connected to node N 301  (CTL 3 ), and a source connected to VDD. NMOS transistor MN 31  has a gate connected to VDD, a drain connected to node N 301 , and a source connected to VSS. PMOS transistor MP 33  has a source connected to VDD, a gate connected to node N 301  and a drain connected to node N 302 . NMOS transistor MN 33  has a drain and gate connected to node N 302 , and a source connected to VSS. PMOS transistor MP 34  is two transistors connected in parallel with one another, each transistor having a gate connected to node N 301 , a drain connected to node N 305  (LoHi 3 ), and a source connected to VDD. NMOS transistor MN 34  is eight transistors connected in parallel with one another, each transistor having a gate connected to node N 302 , a drain connected to node N 305 , and a source connected to N 304  (VR 3 ). Resistor R 3  is connected between node N 304  and VSS. Capacitor C 3  is connected between node N 302  and VDD. PMOS transistor MP 35  has a gate connected to node N 305 , a drain connected to OUT 3  and a source connected to VDD. NMOS transistor MN 35  has a gate connected to node N 305 , a drain connected to OUT 3 , and a source connected to VSS. 
     The operation of the circuit shown in FIG. 3 is similar to the operation of the circuit described previously with respect to the first embodiment. However, transistors MN 22  and MP 22  from the first embodiment have been eliminated from use in the second embodiment. Transistor MN 23  in the first embodiment is now replaced by transistor MN 33 , which is a diode connected transistor. Additionally, a capacitor (C 3 ) has been connected between node N 302  and VDD in the second embodiment. When a fast power-up sequence is initiated with a fast change in the VDD power supply, capacitor C 3  functions to hold the voltage at node N 302  at VDD. By holding node N 302  at VDD, transistors MN 33  and MN 34  are positively turned on to ensure that OUT 3  begins in a high logic state. The voltage at node N 302  will gradually drop down to an operating voltage where OUT 3  drops to a low logic state. The capacitor (C 3 ) prevents a momentary glitch from appearing in the output signal (OUT 3 ) when the power supply (VDD) transitions rapidly. Similar to the discussion with respect to the first embodiment, the second embodiment operates by a beta multiple between transistors MP 33  and MP 34  (instead of MP 23  and MP 24 ), and another beta multiple between transistors MP 32  and MP 34  (instead of MP 23  and MP 24 ). 
     Third Embodiment 
     FIG. 4 is a schematic diagram of a reference generator in accordance with a third embodiment of the present invention. As shown in the figure, the reference generator includes four PMOS transistors (MP 41 -MP 44 ), four NMOS transistors (MN 41 -MN 44 ), a resistor (R 4 ), and an amplifier (XAMP). PMOS transistor MP 41  has a gate and drain connected to node N 401  (CTL 4 ), and a source connected to OUT 4 . NMOS transistor MN 41  has a gate connected to OUT 4 , a drain connected to node N 401 , and a source connected to VSS. PMOS transistor MP 342  has a source connected to OUT 4 , a gate connected to node N 401  and a drain connected to node N 402 . NMOS transistor MN 42  has a drain and gate connected to node N 402 , and a source connected to VSS. PMOS transistor MP 43  has a gate and drain connected to node N 403 , and a source connected to OUT 4 . NMOS transistor MN 43  has a gate connected to node N 402 , a drain connected to node N 403 , and a source connected to VSS. PMOS transistor MP 44  is two transistors connected in parallel with one another, each transistor having a gate connected to node N 403 , a drain connected to node N 405  (LoHi 4 ), and a source connected to OUT 4 . NMOS transistor MN 44  is eight transistors connected in parallel with one another, each transistor having a gate connected to node N 402 , a drain connected to node N 405 , and a source connected to N 404  (VR 4 ). Resistor R 4  is connected between node N 404  and VSS. Amplifier XAMP has an input connected to node N 405  and an output connected to OUT 4 . 
     The operation of the circuit shown in FIG. 3 is similar to the operation of the circuit described previously with respect to the first embodiment. However, instead of producing an output signal that is a logic signal (i.e. OUT 2  in FIG. 2 is driven by an inverter), the output signal (OUT 4 ) is a voltage provided by an amplifier (XAMP). 
     Amplifier XAMP is shown configured as an inverting buffer. The amplifier (XAMP) is internally connected to the VDD and VSS power supplies. Initially the output of the LoHi 4  (N 405 ) node is low (VSS) since no power is applied. As power is applied, the amplifier will begin to operate with gain. Since amplifier XAMP is an inverting amplifier with voltage gain, the output of the amplifier will be at the high power supply (VDD). Thus, the power provided to the high power supply connection (OUT 4 ) is the same as the VDD power supply provided to the first embodiment. As the power supply ramps up towards the trigger voltage, the LoHi 4  node will begin to rise rapidly as in the first embodiment. Since the trigger voltage will be balanced at a particular OUT 4  voltage, the output of the amplifier will regulate the output signal to the trigger voltage. The amplifier can also be configured to provide other voltages by appropriate configuration of the amplifier with voltage dividers or other gain setting mechanisms. 
     The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.