Abstract:
A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to a strained silicon channel semiconductor structure and method of fabricating the same. In particular, the present invention relates to a strained silicon channel semiconductor structure with better carrier mobility and method of making the same. 
         [0003]    2. Description of the Prior Art 
         [0004]    With the trend of miniaturization of semiconductor device dimensions, the scale of the gate, source and drain of a transistor is decreased in accordance with the decrease in critical dimension (CD). Due to the physical limitations of the materials used, the decrease in scale of the gate, source and drain results in the decrease of carriers that determine the magnitude of the current in the transistor element, and this can therefore adversely affect the performance of the transistor. Increasing carrier mobility in order to boost up a metal oxide semiconductor (MOS) transistor is therefore an important topic in the field of current semiconductor techniques. 
         [0005]    To boost the carrier mobility, one conventional attempt has been made by forming a strained silicon channel. The strained silicon channel can increase the mobility of an electron (e − ) group and a hole (h + ) group in the silicon channel without modifying the critical dimension of gate electrode, thereby improving the operation speed of the resulting transistor. This attempt is widely-used in the industry because it may attain better performance for semiconductor devices without complicating the original circuit design or manufacturing process. 
         [0006]    In current implementations, one method for forming a strained silicon channel is using selective epitaxial growth (SEG) to grow an epitaxial layer as a stress source in the substrate. The epitaxial layer has the same lattice arrangement but different lattice constant than the silicon substrate. Thus the epitaxial layer may exert a stress on the lattice of the abutted silicon channel region to form a strained silicon channel, thereby attaining the efficacy of increasing carrier mobility. 
         [0007]    For example, for the PMOS transistor using holes (h + ) as carrier in the channel, a SiGe (silicon-germanium) epitaxial layer may be formed in the source/drain region on the silicon substrate. Due to the lattice constant of SiGe epitaxy being inherently larger than that of Si, the SiGe epitaxial layer will exert a stress on the lattice of abutted silicon channel, thereby forming a compressive strained channel. The band-gap structure of compressive strained channel is advantageous to the transition of holes (h + ), thereby increasing the speed of PMOS device. 
         [0008]    Similarly, for the NMOS transistor using electrons (e + ) as carrier in the channel, a SiC (silicon-carbon) epitaxial layer may be formed in the source/drain region on the silicon substrate. Due to the lattice constant of SiC epitaxy being inherently smaller than that of Si, the SiC epitaxial layer will exert a stress on the lattice of abutted silicon channel, thereby forming a tensile strained channel. The band-gap structure of tensile strained channel is advantageous to the transition of electrons (e + ), thereby increasing the speed of NMOS device. 
         [0009]    Please refer now to  FIG. 1 .  FIG. 1  is a schematic cross-section view of CMOS transistor structure using the technique of a strained silicon channel in the prior art. As shown in the figure, a conventional CMOS transistor structure  100  includes a PMOS region  102  and a NMOS region  104  spaced-apart by a shallow trench isolation (STI)  105 . In addition to the conventional structures such as a gate  105 , a source/drain (not shown) and a spacer  108 , the PMOS region  102  and NMOS region  104  are also provided with recesses  110  formed on source/drain region in order to provide the space for the filling of stress material (ex. SiGe or SiC) to grow an epitaxial layer  112 . The epitaxial layer  112  formed in the recess will exert a stress on a silicon channel region  114  between the source and drain, thereby forming a strained silicon channel and attaining the efficacy of increasing carrier mobility. 
         [0010]    The semiconductor industry is still devoted to researching how to improve the carrier mobility and relevant electrical performance in semiconductor devices in order to respond to the even smaller scale of semiconductor devices in the future. Regarding the semiconductor technique based on strained silicon channel, it is still urgent for those skilled in the art to improve the structure thereof for further improving the relevant electrical performance. 
       SUMMARY OF THE INVENTION 
       [0011]    To further improve the performance of strained silicon semiconductor structures, the present invention provides an improved strained silicon semiconductor structure and method of fabricating the same. The strained silicon semiconductor structure made by this method has better carrier mobility because the epitaxial layer (as stress source) is closer to the silicon channel region. 
         [0012]    One object of the present invention is to provide a strained silicon channel semiconductor structure comprising a substrate having an upper surface, a gate structure formed on said upper surface, at least one recess formed in said substrate at lateral sides of said gate structure, wherein said recess has at least one sidewall, said sidewall has an upper sidewall and a lower sidewall concaved in the direction to said gate structure, and the included angle between said upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into said two recesses. 
         [0013]    Another object of the present invention is to provide a method of making strained silicon semiconductor structure. Said method comprises the steps of providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form at least one recesses in said substrate at lateral sides of said gate structure, performing a pre-bake process at temperature ranging between 700° C.-1000° C., and performing an epitaxy growth process to form an epitaxial layer as stress source in said two recesses. 
         [0014]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings: 
           [0016]      FIG. 1  is a schematic cross-section view of CMOS transistor structure using the technique of a strained silicon channel in the prior art. 
           [0017]      FIGS. 2-8  are schematic views illustrating the process flow of making a strained silicon channel semiconductor structure in accordance with the preferred embodiment of the present invention. 
           [0018]      FIG. 9  is an enlarged, partial schematic view illustrating the profile of a recess in strained silicon channel semiconductor structure before a pre-bake process in accordance with the present invention. 
           [0019]      FIG. 10  is an enlarged, partial schematic view illustrating the profile of the recess in strained silicon channel semiconductor structure after the pre-bake process in accordance with the present invention. 
       
    
    
       [0020]    It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. 
       DETAILED DESCRIPTION 
       [0021]      FIGS. 2-8  are schematic views illustrating the process flow of making a strained silicon channel semiconductor structure in accordance with the preferred embodiment of the present invention. Those figures will be referred in order to describe the steps of making a strained semiconductor structure of the present invention. For the simplicity of description, a horizontal direction H parallel to the surface of substrate  10  and a vertical direction V perpendicular to the surface of substrate  10  are defined in the drawings. 
         [0022]    Please refer firstly to  FIG. 2 , a substrate  10  is provided in the method. Said substrate may be a semiconductor substrate comprising but not limited to a silicon wafer or a SOI (silicon-on-isolator) substrate. A plurality of gate structures  12  is formed on said substrate  10 . Each gate structure  12  comprises agate conductive layer  14 , a gate dielectric layer  16  formed between the surface of substrate  10  and gate conductive layer  14 , and a spacer  18  formed on sidewalls around the gate conductive layer  14 . A liner is formed optionally between the spacer  18 , gate conductive layer  14  and substrate  10 . In present embodiment, the gate dielectric layer  16  may be made of SiO 2  or high-k dielectric layer. The spacer  18  may be made of a silicon-oxide layer or a silicon-nitride layer in form of single layer or composite layer. The gate conductive layer  14  maybe made of doped poly-Si, salicide or metal, etc. For simplicity, in the description of the present invention, the detailed structural and functional description for above-mentioned well-known components of gate structure  12  will not be made hereinafter. 
         [0023]    In other embodiment of present invention, the gate structure  12  may also be integrated into the gate-first process or gate-last process, wherein the gate-last process may be a gate-last process for high-k dielectric pre-layer or for high-k dielectric per-layer. The step for those conventional transistor processes will not be described herein. 
         [0024]    As shown in  FIG. 2 , after the formation of the gate structure  12 , a sacrificial material layer  20  is blanket-deposited conformingly on the substrate  10  and the gate structure  12 . The portion  20   a  of the sacrificial material layer  20  deposited right on the surface of the substrate may be relatively thinner, while the portion  20   b  of the sacrificial material layer  20  deposited right on the surface of the substrate maybe relatively thicker. In this way, the sacrificial material layer  20  may be modified to a desired pattern for serving as an etch mask in a later process, for which the details will be described in the embodiment hereafter. 
         [0025]    Please refer subsequently to  FIG. 3 . After the formation of the sacrificial material layer  20 , a first dry etching process is performed on the entire substrate  10 . This dry etching process may remove all the portion  20   a  of the sacrificial material layer covering right upon the substrate  10  and reserve a thin layer (referred to hereinafter as a sacrificial spacer  22 ) covering on the surface of the spacer  18  after the etching of the portion  20   b  of the sacrificial material layer  20 . The reserved sacrificial spacer  22  is used as an etch mask in a later etching process. 
         [0026]    Please refer subsequently to  FIG. 4 . After the formation of the sacrificial spacer  22 , a first etching process is performed on the entire substrate  10  with the sacrificial spacer  22  being used as an etch mask. Said first etching process includes a first dry etching process and a first wet etching process, wherein said first dry etching process provides downward etching, while said first wet etching process provides downward etching and lateral etching. Said first dry etching process uses SF 6 -based etchant or NF 3 -based etchant which are etch-selective to the material of the substrate  10 , thus a recess  24  structure will be etched out in the substrate  10 . Furthermore, during the first wet etching process, the etchant will etch the substrate  10  both in the horizontal direction H and the vertical direction V, wherein the etching rate in the horizontal direction H is larger than the etching rate in the vertical direction V, thereby forming a concave surface  24   a  concaved in the direction to the gate structure in the substrate  10 . 
         [0027]    Please refer to  FIG. 5 . A second wet etching process is performed subsequently after the formation of the above-mentioned first dry etch recess  24 . Said second wet etching process uses a NH 4 OH-based etchant or a TMAH-based etchant which is etch-selective to material of the substrate  10  to further etch the sidewall of said first dry etch recess  24  formed in the previous step. Furthermore, because those etchants etch the silicon substrate  10  along the crystallographic plane (110) and (111), the first dry etch recess  24  will be transformed into a diamond-shape recess  26  having distinguishing etching planes (shown as the upper sidewall  26   b  and lower sidewall  26   c  shown in the figure). An acute angle (or tip)  26   a  is formed at the intersection of said upper sidewall  26   b  and lower sidewall  26   c  on the sidewall of said diamond-shape recess  26 . 
         [0028]    Please refer subsequently to  FIG. 6 . After the formation of above-mentioned recess  26 , a pre-bake process is performed on the entire substrate  10 . Said pre-bake process will diffuse and rearrange the atoms near the sidewall of the diamond-shape recess  26 , thereby rounding the acute angle  26   a  (i.e. by increasing the angle) at the sidewall of the recess  26 . In this way, the shape of the recess  26  is transformed from the original diamond shape into a diamond-like recess  28  with a more rounded sidewall surface  29 . In a preferred embodiment of the present invention, the process parameter of pre-bake step is set to the temperature ranging between 700° C.-1000° C. and pressure under 10 torr to few hundred torr in hydrogen-containing ambiance with process time ranging from a few seconds to several minutes. The detailed structure of the above-mentioned diamond-like recess  28  will be further described in the embodiment hereafter. 
         [0029]    In the final step, please refer to  FIG. 7 , a selective epitaxial growth (SEG) process is performed for growing an epitaxial layer  30  in the diamond-like recess  28 . The epitaxial layer  30  is used as a stress source to strain the abutted silicon channel. Preferably, the upper surface of the epitaxial layer  30  should be deposited higher than the surface of the substrate  10  in order to enhance the effect of epitaxial strain. In present embodiment, the epitaxial layer  30  maybe made of SiGe (for PMOS transistor) or SiC (for NMOS transistor) which will exert a stress on abutting silicon channel region  10   a , thereby attaining the efficacy of improving carrier mobility. Please note that the epitaxy process and previous pre-bake process may be performed in the same deposition chamber, in which the epitaxial layer is subsequently grown right after the deposition chamber is heated and the pre-bake process is finished. 
         [0030]    In a further embodiment of the present invention, as shown in  FIG. 8 , an ion implantation process is optionally performed on the epitaxial layer  30  formed in the previous step. Said ion implantation process uses photo resist (not shown) or the gate structure  12  as a mask to implant the N-type dopants (such as P, As or Sb) or P-type dopants (such as B, BF 2 ) respectively combining with other co-implant species, e.g. , C, N 2 , F, Ge, Si into the corresponding epitaxial layer  30  in the NMOS or PMOS region, thereby defining the source/drain area  32   a / 32   b  in the epitaxial layer  30  at opposite sides of the gate structure  14 . So far, a complete transistor structure is finished. Please note that in other embodiments of the present invention, the step of defining the source/drain may be performed before the etching of the recess or performed concurrently with the selective epitaxial process, depending on the process requirement. In still another embodiment of the present invention, an additional spacer (not shown) may be optionally formed on the gate structure  12  to define the size of source/drain area  32   a / 32   b  before the ion implantation process. 
         [0031]    Besides, the sacrificial spacer  22  formed in the previous step may also be stripped by an additional etching process. In other embodiments, this sacrificial spacer may be reserved as a spacer structure. 
         [0032]    Please now refer concurrently to  FIG. 9  and  FIG. 10 .  FIG. 9  and  FIG. 10  are enlarged, partial cross-section views illustrating the recess of strained silicon channel semiconductor structure formed before and after a pre-bake process in accordance with the embodiment of the present invention. As shown in  FIG. 9 , because the etchant will etch the silicon substrate  10  along a specific crystallographic plane during the formation of the recess, the cross-section shape of the recess  26  will be a perfect diamond-shape. More specifically, the recess  26  is form of at least one sidewall and a bottom surface  27 . Said sidewall further includes an upper sidewall  26   b  and a lower sidewall  26   c.  Due to the effect of lateral etching in present invention, the sidewall is formed under the spacer  18  of the gate structure  12 , wherein the upper sidewall  26   b  intersects with the surface of substrate  10  right under the spacer  18  (as point A shown in the figure), while the intersection of the lower sidewall  26   c  and bottom surface  27  (as point B shown in the figure) may or may not located below the spacer  18 . The upper sidewall  26   b  and lower sidewall  26   c  (i.e. distinguishing etching planes are concaved in the direction to the gate structure  12  and intersect with each other at an intersection (or tip)  26   a.  As shown in the figure, the upper sidewall  26   b  of the recess  26  is oriented at a fixed angle θ 1 =54.5° with respect to the horizontal plane. In the present embodiment, the horizontal distance from the intersection (point A) of the upper sidewall  26   b  and the surface of the substrate to the gate conductive layer  14  is denoted as d 1 , while the vertical distance from the tip  26   a  to the surface of the substrate  10  is denoted as d 2 . The distances d 1  and d 2  have an influence on how efficiently the stress induced by the epitaxial layer maybe exerted on the silicon channel. Taking the semiconductor device with 32 nm gate CD as an example, the distance d 1  and d 2  is 130 Å and 200 Å, respectively. 
         [0033]    Please refer now to  FIG. 10 . The recess  26  in the present embodiment is transformed into a diamond-like recess  28  after a high temperature, low pressure pre-bake process. The recess  28  has a more rounded sidewall surface (that is, the angle between the upper sidewall  28   b  and the lower surface  28   c  is larger) concaved in the direction to the gate structure  14  and extended below the spacer, thereby the epitaxial layer formed thereafter may be closer to the silicon channel region  10   a.  In one implementation, after the sample undergoes an 800° C. pre-bake process, the angle θ 2  between the upper sidewall  28   b  and the horizontal plane is changed from 54.5° to 75°, the horizontal distance D 1  from the intersection of upper sidewall  28   b  and the surface of substrate  10  to gate conductive layer  14  is shrunk from 130 Å to 70 Å, and the vertical distance D 2  from tip  28   a  to the surface of substrate  10  is shrunk from 200 Å to 172 Å. The above-mentioned data shows the sidewall of the recess  28  after the pre-bake process is closer to the silicon channel region (i.e. reduced D 1  and D 2 ), thereby the epitaxial layer formed thereafter may exert more stress on the channel region and attain a better strain effect. 
         [0034]    Please note that the shape of the final recess structure in present invention may vary with different process conditions during the pre-bake step. Generally, the pre-bake process is set at the temperature ranging between 700° C.-1000° C. and at the pressure under 10 torr to several hundreds torr in hydrogen-containing ambiance with process time ranging from a few seconds to several minutes. For the diamond-like recess structure formed thereafter, the resulting angle θ 2  between the upper sidewall and the horizontal plane may range from 54.5° to 90°, preferably 75° to 90°. Also, for the scale of 35 nm gate CD circuit architecture, the distance is preferably smaller than 130 Å, while the resulting D 2  distance is preferably smaller than 200 Å. 
         [0035]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.