Abstract:
A low power oscillator circuit for a self-refresh timer in a memory array is disclosed. When a voltage (V 1 ) of a comparison node (N 1 ) exceeds a first reference voltage (Vref 1 ), a differential amplifier ( 101 ) in an oscillator ( 1 ) causes a pulse generator ( 110 ) to output a pulse. A charge/discharge circuit ( 105 ) discharges the comparison node (N 1 ) in response to pulse. In this event, a control circuit ( 4 ) disables a first control signal (CT 1 ) to halt operation of the differential amplifier ( 101 ). When the voltage (V 1 ) exceeds a second reference voltage (Vref 2 ) equivalent to the sum of threshold voltages of a discharge circuit ( 43 ) in consequence of gradually charging the comparison node (N 1 ) by the charge/discharge circuit ( 105 ) after it was discharged, the control circuit ( 4 ) activates the first control signal (CT 1 ) to operate the differential amplifier ( 101 ).

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to an oscillator and, more specifically, relates to an oscillator for use in a semiconductor memory device.  
       BACKGROUND OF THE INVENTION  
       [0002]     A dynamic random access memory (DRAM) is capable of storing information based on the amount of charge held in a storage capacitor for each memory cell in the array. Over time, the charge in the storage capacitor dissipates and must be restored to maintain the integrity of the data held in memory. Accordingly, a number of prior art schemes have been proposed to “refresh” the data held in a memory. One approach for implementing memory refresh incorporates an automatic process controlled by a timer to define the interval required for refresh. As the density of memory arrays has expanded, the charging and discharging of the storage capacitors in each cell of the memory begins to represent a significant source of power dissipation. Accordingly, if power can be reduced on a unit cell basis, then a significant power savings can be realized for an entire array.  
       SUMMARY OF THE INVENTION  
       [0003]     It is an object of the present invention to provide an oscillator for a refresh timer of a memory array that reduces overall power dissipation in the integrated circuit memory array. A DRAM (Dynamic Random Access Memory) includes an oscillator that functions as a timer upon carrying out a refresh operation. Referring to  FIG. 4 , oscillator  100  includes a differential amplifier  101  for comparing a voltage V 1  of a comparison node N 1  with a reference voltage Vref to output a timing signal TMG to node N 100 , pulse generator  110  that outputs a logic low pulse in response to timing signal TMG being asserted low, capacitor C 100  that is connected to comparison node N 1 , and a charge/discharge circuit  105  for charging/discharging the capacitor C 100 . The charge/discharge circuit  105  includes constant current source  104 , which exhibits minimal temperature dependence, and an inverter IV 101 . Charge/discharge circuit  105  charges capacitor C 100  when output signal SROSC (self-refresh oscillator) from pulse generator  110  is asserted to a logic one. As a result, the voltage V 1  of comparison node N 1  increases. Conversely, when output signal SROSC of pulse generator  110  transitions to a logic zero, charge/discharge circuit  105  discharges capacitor C 100 .  
         [0004]     Referring to  FIGS. 4 and 5 , charge/discharge circuit  105  gradually raises voltage V 1  of comparison node N 1  before time t 1 . Then, at time t 1 , voltage V 1  exceeds reference voltage Vref. In this event, timing signal TMG output from differential amplifier  101  transitions to a logic zero, which is propagated to output SROSC of pulse generator  110 . In response to pulse PL, an N-channel MOS transistor (not illustrated) in inverter IV 101  of the charge/discharge circuit  105  is turned on, providing a discharge path for capacitor C 100  and resulting in voltage V 1  decreasing at time t 12 .  
         [0005]     At time t 11 , after a lapse of a predetermined pulse width Tpw from time t 1 , pulse generator  110  asserts signal SROSC to a logic zero. Pulse width Tpw is determined by pulse width determining circuit  102 . When signal SROSC transitions low, P-channel MOS transistor P 100  is turned on so that timing signal TMG at node N 100  is clamped high.  
         [0006]     Subsequent to time t 21  after a lapse of pulse width Tpw from time t 11 , charge/discharge circuit  105  receives the inverted signal of output signal SROSC corresponding to a logic one. In this event, a P-channel MOS transistor (not illustrated) in inverter IV 101  is turned on so that the charge is fed to capacitor C 100  from constant current source  104 . As a result, voltage V 1  gradually rises after time t 21 .  
         [0007]     When voltage V 1  exceeds reference voltage Vref at time t 3  in consequence of charge/discharge circuit  105  charging capacitor C 100 , differential amplifier  101  again sets the timing signal TMG to a logic zero so that pulse generator  110  outputs logic zero pulse PL.  
         [0008]     While oscillator  100  outputs logic zero pulse PL every Tcyc, differential amplifier  101  in oscillator  100  compares voltage V 1  of comparison node N 1  with reference voltage Vref. Therefore, an operating current must flow constantly in the differential amplifier  101  and a charging current is also constantly supplied to the capacitor C 100 . However, the charging current is suppressed to ensure a long charging time and is therefore much smaller in magnitude than the operating current of differential amplifier  101 . Indeed, most of the operating current of oscillator  100  is drawn by differential amplifier  101 . Oscillator  100  is used in a self-refresh operation of a DRAM and is therefore required to operate even in a standby mode of the DRAM. Therefore, the operating current of differential amplifier  101  significantly impacts the standby current, which, in turn, affects the average operating current and total power dissipated by the array.  
         [0009]     An oscillator according to the present invention includes a comparator circuit, pulse generator, charge/discharge circuit, and control circuit. The comparator asserts a timing signal after determining when a voltage at a comparison node exceeds a first reference voltage. The pulse generator outputs a pulse in response to receipt of the asserted timing signal. The charge/discharge circuit discharges the comparison node when the pulse is received, and charges the comparison node when the pulse is not received. The control circuit halts operation of the comparator when the voltage of the comparison node does not exceed a second reference voltage lower than the first reference voltage.  
         [0010]     The oscillator according to the present invention halts operation of the comparator during the period between the discharge and charge of the comparison node to ensure the comparison node voltage exceeds the second reference voltage. This is achievable since the timing signal can be activated timely even if the comparator is operated after the voltage of the comparison node rises to the vicinity of the first reference voltage. Therefore, the current draw of the comparator can be reduced according to the present invention, thereby reducing the power consumed by the oscillator.  
         [0011]     Preferably, the control circuit includes a control node, a first charge circuit, and a first discharge circuit. The control node outputs a first control signal used for operating the comparator. The first charge circuit charges the control node when the voltage of the comparison node is lower than the second reference voltage. The first discharge circuit discharges the control node during a period in which the voltage of the comparison node exceeds the second reference voltage.  
         [0012]     In this case, the control circuit charges or discharges the control node using the first charge circuit or the first discharge circuit to enable or disable the first control signal. The first discharge circuit does not discharge the control node while the first charge circuit charges the control node, and the first charge circuit does not charge the control node while the first discharge circuit discharges the control node. Therefore, generation of a short-circuit current can be suppressed within the control circuit, thereby reducing the overall power dissipation of the oscillator.  
         [0013]     Preferably, the first charge circuit includes a pulse delay circuit and a first transistor. The pulse delay circuit outputs a delayed pulse and the first transistor is turned on in response to the delayed pulse.  
         [0014]     When the pulse generator output is enabled, the comparison node is discharged. In this event, since the voltage of the comparison node becomes lower than the second reference voltage, the first discharge circuit in the control circuit stops the discharge. That is, the first discharge circuit operates from a time when the voltage of the comparison node exceeds the second reference voltage until the pulse generator output is received. Conversely, the first charge circuit receives the delayed pulse after a lapse of a predetermined time from when the pulse generator output is enabled. That is, the first charge circuit is active for one pulse width after the pulse generator outputs a pulse. As a result, by using the pulse generator output as a trigger for the first charge circuit, the active period of the first charge circuit can be temporally displaced from the active period of the first discharge circuit. Therefore, generation of the short-circuit current can be suppressed in the control circuit thereby reducing the power dissipated in the oscillator.  
         [0015]     Preferably, the first discharge circuit includes a second transistor and a third transistor. The second transistor has a drain connected to the control node and a gate connected to the comparison node. The third transistor is connected in series to the second transistor and diode-connected thereto. Using the diode-connected third transistor, an adjustment can be made to ensure the comparator remains off for as long as possible.  
         [0016]     Preferably, the oscillator further includes a waveform shaping circuit. The waveform shaping circuit outputs a second control signal with a steeper transient that is derived from the first control signal. The waveform shaping circuit includes a reshaping node, a second charge circuit, and a second discharge circuit. The waveform shaping circuit outputs the second control signal. The second charge circuit charges the reshaping node during a period in which the first control signal is active. The second discharge circuit discharges the reshaping node during a period in which the second charge circuit does not charge the reshaping node.  
         [0017]     Because of the gradual charging of the comparison node and an effect of the diode-connected third transistors, the slope of the waveform of the first control signal output from the control circuit is shallow, and further, the first control signal does not drop to a ground potential. Due to this effect of the first control signal, short-circuit current only flows in the elements downstream to the control circuit. In this regard, the short-circuit current can be suppressed by outputting the second control signal obtained in the waveform shaping circuit by making the slope of the waveform of the first control signal steeper when it shifts to an active state.  
         [0018]     The waveform shaping circuit charges the shaping node using the second charge circuit in response to the first control signal. Since the second discharge circuit in the waveform shaping circuit has already halted its operation, the slope of a waveform, upon shifting, of the second control signal can be made steeper. Further, by halting the operation of the second discharge circuit during the operation of the second charge circuit, the short-circuit current in the waveform shaping circuit can also be suppressed.  
         [0019]     Preferably, the oscillator further includes a switch and a voltage clamp. The switch is connected between the comparator and the pulse generator. The switch is turned off when the first control signal is disabled and turned on when the first control signal is enabled. The voltage clamp disables the timing signal when the first control signal is disabled, but allows the timing signal to propagate when the first control signal is enabled.  
         [0020]     When the first control signal is disabled, the comparator is off. In this event, since the timing signal is in a high impedance state, there is a possibility that noise may added to the timing signal. To reduce the incidence of spurious noise signals corrupting the timing signal, the switch is turned off when the first control signal is disabled. Turning off the switch prevents transmission of a noisy timing signal to the pulse generator. Further, when the first control signal is disabled, the voltage of the timing signal is fixed by the voltage clamp. Therefore, it is possible to prevent transmission of noise to the pulse generator and prevent malfunction of the oscillator.  
         [0021]     Preferably, the switch is turned on after the activation of the first control signal, and the voltage clamp is disabled thereafter.  
         [0022]     When operation of the comparator is initialized, there is a possibility that noise may be superimposed on the timing signal due to metastability in the comparator logic. In the present invention, the switch remains off from the startup of the operation of the comparator. Consequently, noise occurring in the initial operation stage of the comparator is not transmitted to the pulse generator. Further, the voltage clamp continues to operate until after the switch is turned on. If the operation of the voltage clamp is interrupted simultaneously with the switch turning on, it is possible that the timing signal may become unstable due to the effect of coupling capacitance in the switch. Therefore, by turning on the switch prior to disabling the voltage clamp, it is possible to prevent the timing signal from becoming unstable so that malfunction of the oscillator can be prevented.  
         [0023]     Preferably, the oscillator further includes a latch connected to an output node of the pulse generator. The latch captures an output signal of the pulse generator while the first control signal is disabled.  
         [0024]     In this case, even if noise occurs in the pulse generator while the comparator operation is halted, the output signal of the pulse generator is held by the latch so that the influence of noise can be removed, further reducing the risk of oscillator malfunction.  
         [0025]     The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]      FIG. 1  is a functional block diagram showing a structure of an oscillator according to a preferred embodiment of the present invention;  
         [0027]      FIG. 2  is a functional block diagram showing a structure of an oscillator including several waveform shaping circuits one of which is shown in  FIG. 1 , according to a modification of the structure shown in  FIG. 1 ;  
         [0028]      FIG. 3  is a waveform diagram showing operation of the oscillator shown in  FIG. 1 ;  
         [0029]      FIG. 4  is a functional block diagram showing a structure of a conventional oscillator; and  
         [0030]      FIG. 5  is a waveform diagram showing operation of the oscillator shown in  FIG. 4 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]     Hereinbelow, a preferred embodiment of the present invention will be described in detail with reference to the drawings. The same or corresponding portions are assigned the same reference symbols in the figures to thereby avoid repetition of description thereof.  
         [0032]     Referring to  FIG. 1 , an oscillator  1  according to the preferred embodiment of the present invention includes differential amplifier  101 , pulse generator  110 , charge/discharge circuit  105 , control circuit  4 , and waveform shaping circuit  5 .  
         [0033]     Differential amplifier  101  compares voltage V 1  of comparison node N 1  with reference voltage Vref 1 , and outputs timing signal TMG, which is asserted to a logic zero at node N 10  when voltage V 1  exceeds reference voltage Vref 1 .  
         [0034]     Pulse generator  110  receives timing signal TMG and outputs an intermediate signal φM to node N 30 . When timing signal TMG becomes low, pulse generator  110  generates a logic zero pulse PL at intermediate signal φM. Pulse generator  110  includes pulse width determining circuit  102 , inverter IV 100 , NOR gate  103 , and P-channel MOS transistor PM 100 . Pulse width determining circuit  102 , inverter IV 100 , and NOR gate  103  are connected together in series. NOR gate  103  receives an output signal from inverter IV 100  and oscillator enable signal /OSCEB and outputs the result. NOR gate  103  is designed to disable operation of oscillator  1 . While oscillator  1  is in operation, the oscillator enable signal /OSCEB is held low, and therefore, NOR gate  103  operates as an inverter. The drain of P-channel MOS transistor PM 100  is connected to an input terminal of pulse width determining circuit  102 , and the gate thereof is connected to node N 30 . The intermediate signal φM is fed back to the gate of transistor PM 100 , which determines a pulse width of pulse PL.  
         [0035]     Charge/discharge circuit  105  charges and discharges comparison node N 1 . Charge/discharge circuit  105  is connected between inverter IV 102  and comparison node N 1 , and includes constant current source  104  and inverter IV 101  supplied by a source current therefrom. Constant current source  104  is connected between VCC node  20 , where an internal supply voltage VCC is applied, and a current supply node of the inverter IV 101 . When the intermediate signal φM output by pulse generator  110  is at a logic high level (i.e. when pulse generator  110  outputs no pulse PL), an output signal of the inverter IV 102  stays low. In this event, a P-channel MOS transistor (not illustrated) of the inverter IV 101  in charge/discharge circuit  105  is turned on so that the charge is fed to comparison node N 1  from constant current source  104 . Capacitor C 100 , connected to comparison node N 1 , is charged so that voltage V 1  of comparison node N 1  rises. When pulse generator  110  outputs pulse PL at logic zero, an N-channel MOS transistor (not illustrated) of the inverter IV 101  in the charge/discharge circuit  105  is turned on so that capacitor C 100  connected to comparison node N 1  is discharged. No constant current source exists between inverter IV 101  and GND node  25  where a ground voltage GND is applied. Therefore, the charge/discharge circuit  105  does not restrict a discharge current flowing to the GND node  25 . As a result, voltage V 1  of comparison node N 1  drops instantly.  
         [0036]     Control circuit  4  outputs a control signal CT 1  for starting or stopping operation of differential amplifier  101 . The control circuit  4  includes charge circuit  41  and discharge circuit  43 .  
         [0037]     Charge circuit  41  includes pulse delay circuit  42  and P-channel MOS transistor PM 0 . Pulse delay circuit  42  includes several inverters IV 5  to IV 8 . Pulse delay circuit  42  outputs delayed pulse DPL in response to pulse generator output pulse PL. Transistor PM 0  is connected between VCC node  20  and control node N 2 . Transistor PM 0  is turned on in response to receipt of delayed pulse DPL to charge control node N 2 , thereby driving control signal CT 1  high, which represents a disabled state.  
         [0038]     Discharge circuit  43  includes N-channel MOS transistors NM 0   0  to NM 0   n-1  connected in series between control node N 2  and GND node  25 . The gate of transistor NM 0   0  is connected to comparison node N 1 . Transistors NM 0   1  to NM 0   n-1  are diode-connected, respectively. Therefore, when a gate voltage of transistor NM 0   0 , i.e. voltage V 1  of comparison node N 1 , becomes higher than the sum of threshold values Vthn of transistors NM 0   0  to NM 0   n-1 (n×Vthn), transistors NM 0   0  to NM 0   n-1  are turned on. When transistors NM 0   0  to NM 0   n-1  are turned on, control node N 2  is discharged so that control signal CT 1  transitions low, which is an active state. Hereinafter, the sum of threshold values Vthn of transistors NM 0   0  to NM 0   n-1  (n×Vthn) will be referred to as reference voltage Vref 2 . Discharge circuit  43  is designed so that reference voltage Vref 2  stays lower than reference voltage Vref 1 .  
         [0039]     As described above, pulse delay circuit  42  output DPL is coupled to the gate of transistor PM 0  in charge circuit  41  to differentiate a period in which transistor PM 0  is on, from a period in which discharge circuit  43  is on. This makes it possible to suppress short-circuit current in control circuit  4 .  
         [0040]     Waveform shaping circuit  5  shapes a waveform of control signal CT 1  output from control circuit  4 . Control signal CT 1  exhibits a shallow slope when transitioning from high to low. This is because voltage V 1  of comparison node N 1  connected to the gate of transistor NM 0   0  is charged gradually. In addition, since discharge circuit  43  includes diode-connected transistors NM 0   1  to NM 0   n-1 , the amount of the charge to be dissipated is reduced as the voltage of control node N 2  approaches the total sum of threshold voltage of transistors from NM 1  to NM n-1  ((n−1)×Vthn). When the slope of the waveform is shallow, the short-circuit current occurs in the circuit elements connected to control node N 2 . To prevent short-circuit currents, it is desirable to make the slope of the waveform steep. In this regard, waveform shaping circuit  5  outputs control signal CT 2  at shaping node N 3 . Control signal CT 2  is obtained by increasing the slope of the waveform of control signal CT 1 .  
         [0041]     Waveform shaping circuit  5  includes P-channel MOS transistor PM 1 , N-channel MOS transistor NM 1 , and inverter IV 4 . Transistor PM 1  is connected between VCC node  20  and shaping node N 3 . Transistor PM 1  is turned on in response to receipt of control signal CT 1  to charge shaping node N 3 . Transistor NM 1  is connected between shaping node N 3  and GND node  25 . Transistor NM 1  is turned on by inverted delayed pulse /DPL. Inverter IV 4  outputs delayed pulse /DPL in response to the output from pulse delay circuit  42  in control circuit  4 . Because transistor PM 1  and transistor NM 1  are not simultaneously active, waveform shaping circuit  5  can also suppress short-circuit currents. Incidentally, although one waveform shaping circuit  5  is shown in  FIG. 1 , several waveform shaping circuits may be connected after control circuit  4  to further increase the slope of the waveform. For example, as shown in  FIG. 2 , waveform shaping circuit  50  may be connected after waveform shaping circuit  5  in place of inverter IV 9  shown in  FIG. 1 . Waveform shaping circuit  50  includes P-channel MOS transistor PM 50  and N-channel MOS transistor NM 50  connected in series to each other between VCC node  20  and GND node  25 . Pulse DPL is input to transistor PM 50 , while control signal CT 2  drives the gate of transistor NM 50 .  
         [0042]     If waveform shaping circuits  5  and waveform shaping circuits  50  are alternately connected, the slope of the waveform can be further increased. If the last circuit (i.e. the circuit closest to an inverter IV 10 ) of the alternately connected waveform shaping circuits is the waveform shaping circuit  5 , the inverter IV 9  is interposed between the inverter IV 10  and the last waveform shaping circuit  5 . The placement of inverter IV 9  prevents the polarity of a waveform of signal φA driving inverter IV 10  from inverting depending on the number of connections of the alternately connected waveform shaping circuits.  
         [0043]     Control signal CT 2  generated by waveform shaping circuit  5  is input to OR gate  10  after propagating through inverters IV 9  to IV 11 . Logic gate  10  receives oscillator enable signal /OSCEB and output signal AMPDIS of inverter IV 11  and evaluates a result of the logical OR operation. Oscillator enable signal /OSCEB stays low when oscillator  1  is in operation. Therefore, while oscillator  1  is in operation, differential amplifier  101  is turned on or off depending on a level of signal AMPDIS output by inverter IV 11 .  
         [0044]     Oscillator  1  further includes a switch circuit  2 , a voltage fixing circuit  8 , a latch circuit  3 , and delay circuits  6  and  7 . These circuits are provided for holding an output signal SROSC of oscillator  1  when differential amplifier  101  is off, and for preventing malfunction of the oscillator  1  caused by noise that may occur when the differential amplifier  101  is turned on.  
         [0045]     Switch circuit  2  is, for example, a CMOS transfer gate and is turned on in response to receipt of switch signal SW 1  at a logic one level and switch signal SW 2  at a logic zero level.  
         [0046]     Switch signals SW 1  and SW 2  are generated by delay circuit  6 , which includes inverters IV 12  to IV 15 . Inverters IV 12  to IV 15  are connected in series. Delay circuit  6  receives signal AMPDIS from inverter IV 11  at the input of inverter IV 12 , and outputs switch signal SW 1  from inverter IV 14  output. Further, delay circuit  6  outputs switch signal SW 2  obtained by inverting switch signal SW 1  through inverter IV 15 .  
         [0047]     When differential amplifier  101  is off, switch circuit  2  is also off. When differential amplifier  101  is turned on, switch circuit  2  is turned on after a lapse of a predetermined time ΔT 1 , and remaining off in the initial startup stage of differential amplifier  101 . As a result, even if noise occurs in the initial startup stage of differential amplifier  101 , the noise can be cut off by switch circuit  2  and therefore is not transmitted to the subsequent pulse generator  110 . The predetermined time ΔT 1  is determined by delay circuit  6 .  
         [0048]     Voltage clamp  8  includes P-channel MOS transistor PM 2 . Transistor PM 2  is connected between VCC node  20  and an input terminal of pulse generator  110 . Transistor PM 2  is turned on in response to receipt of clamping signal KP.  
         [0049]     Clamping signal KP is output by delay circuit  7 , which includes inverters IV 16  to IV 20  connected in series. Responsive to receipt of switch signal SW 2 , delay circuit  7  outputs clamping signal KP by delaying switch signal SW 2  by a predetermined time ΔT 2  and inverting it.  
         [0050]     When differential amplifier  101  is turned off, transistor PM 2  is turned on to clamp timing signal TMG at node N 20  high (inactive state). Conversely, transistor PM 2  is turned off after differential amplifier  101  is initialized and further after a lapse of predetermined time ΔT 2  from the turning-on of switch circuit  2 . Therefore, even after differential amplifier  101  is initialized and switch circuit  2  is turned on, noise, if it is generated within ΔT2 time period after circuit  2  is turned on, is not transmitted to pulse generator  110 . This is because voltage clamp  8  fixes timing signal TMG at node N 20  to a logic one.  
         [0051]     Latch circuit  3  includes inverters IV 1  and IV 2  and switch circuit  9 . Switch circuit  9  is formed by a transfer gate and turned on when switch signal SW 1  is low and switch signal SW 2  is high. Accordingly, switch circuit  9  is turned on when differential amplifier  101  is turned off. In this regard, cross coupled inverters IV 1  and IV 2 , which form a latch circuit, capture output signal SROSC of pulse generator  110 . While differential amplifier  101  is off, output signal SROSC of oscillator  1  is fixed so that malfunction due to noise can be prevented.  
         [0052]     Description will be made of the operation of oscillator  1  having the structure shown in  FIG. 1 . Oscillator  1  enables power saving by operating differential amplifier  101  only during a required period.  
         [0053]     Referring to  FIG. 3 , comparison node N 1  is charged by charge/discharge circuit  105  before time t 1 . Accordingly, voltage V 1  of comparison node N 1  gradually rises.  
         [0054]     When voltage V 1  exceeds the reference voltage Vref 1  at time t 1 , differential amplifier  101  outputs timing signal TMG at a logic zero. At time t 1 , switch circuit  2  is on and the operation of voltage clamp  8  is interrupted, and therefore, timing signal TMG is input to pulse generator  110 . Pulse generator  110  outputs intermediate signal φM to node N 30  in response to timing signal TMG at time t 11  after a delay of a predetermined time. When intermediate signal φM is output, transistor PM 100  is turned on. As a result, timing signal TMG at node N 20  transitions high at time t 11  and pulse PL is formed in the intermediate signal φM output from pulse generator  110 .  
         [0055]     At time t 12  slightly delayed from pulse PL, charge/discharge circuit  105  discharges comparison node N 1 . The time is delayed from time t 11  because of an influence of delays caused by inverters IV 101  and IV 102 . Since comparison node N 1  is discharged, voltage V 1  transitions low. Thus, transistor NM 0   0  in discharge circuit  43  of control circuit  4  is turned off. As a result, the discharge of control node N 2  stops.  
         [0056]     At time t 2  after voltage V 1  drops to turn off transistors NM 0   0  to NM 0   n-1  in discharge circuit  43 , delayed pulse DPL is output from pulse delay circuit  42 . Transistor PM 0  in charge circuit  41  is turned on in response to delayed pulse DPL. Transistor PM 0  is on during a pulse width APL of delayed pulse DPL. While transistor PM 0  is on, control node N 2  is charged. As a result, control signal CT 1  output by control node N 2  is disabled (logic one). Since transistors NM 0   0  to NM 0   n-1  in discharge circuit  43  are off, no short-circuit current results.  
         [0057]     When pulse delay circuit  42  outputs delayed pulse DPL, transistor NM 1  in waveform shaping circuit  5  receives inverted delayed pulse /DPL through inverter IV 4 . Transistor NM 1  is on when it receives inverted delayed pulse /DPL (i.e. during the pulse width ΔPL), so that shaping node N 3  is discharged. As a result, control signal CT 2  output by shaping node N 3  becomes disabled (logic zero). Since control signal CT 1  is high, transistor PM 1  is off. Therefore, the short-circuit current does not flow in waveform shaping circuit  5 .  
         [0058]     Control signal CT 2  propagates through inverters IV 9  and IV 10  and is routed to inverter IV 11 . Inverter IV 11  outputs the deactivated (logic one) signal AMPDIS in response to control signal CT 2 . As a result, differential amplifier  101  halts operation in response to receipt of the deactivated signal AMPDIS at logic one at time t 2 .  
         [0059]     At time t 3  after a lapse of predetermined time ΔT 1  from time t 2 , delay circuit  6  outputs switch signal SW 1  and switch signal SW 2 , such that the switch circuit  2  is turned off. Further, at time t 4  after a lapse of predetermined time ΔT 2  from time t 3 , delay circuit  7  outputs clamping signal KP at a logic zero level. As a result, voltage clamp  8  fixes timing signal TMG at node N 20  to the disabled state (logic one). When differential amplifier  101  halts operation, timing signal TMG is in a high impedance state. Therefore, unless switch circuit  2  is provided, noise may be introduced to output signal SROSC of oscillator  1 . In this embodiment, differential amplifier  101  and pulse generator  110  are separated from each other by switch circuit  2 , and further, timing signal TMG at node N 20  is clamped high by voltage clamp  8 , and therefore, noise is not transmitted to pulse generator  110 . Consequently, an operational interrupt of differential amplifier  101 , does not result in a malfunction of oscillator  1 .  
         [0060]     Since switch circuit  9  in latch circuit  3  is turned on at time t 3 , latch circuit  3  captures output signal SROSC of pulse generator  110 . Therefore, even if noise is generated in pulse generator  110  while differential amplifier  101  halts operation, the output of oscillator  1  is kept stable by latch circuit  3 . Switch circuit  2  and voltage clamp  8  are both off during a period from time t 3  to time t 4 , causing timing signal TMG to become unstable. Therefore, output signal SROSC of oscillator  1  should be stabilized by operating latch circuit  3  from time t 3  to time t 4 .  
         [0061]     After a lapse of pulse width APL from time t 2 , since intermediate signal φM output by pulse generator  110  becomes high, charge/discharge circuit  105  charges comparison node N 1 . Specifically, P-channel MOS transistor (not illustrated) of inverter IV 101  in charge/discharge circuit  105  is turned on so that charge/discharge circuit  105  continues to supply the charge to capacitor C 100 , causing voltage V 1  of comparison node N 1  to rise gradually.  
         [0062]     Because of its gradual rise, Voltage V 1  exceeds reference voltage Vref 2  at time t 5 . In this event, a value obtained by subtracting ground voltage GND from the gate voltage of transistor NM 0   0  (voltage V 1 ) exceeds the total threshold voltage (n×Vthn), and therefore, transistors NM 0   0  to NM n-1  are fully turned on. Consequently, control node N 2  is discharged. However, inasmuch as comparison node N 1  is charged slowly and discharge circuit  43  includes diode-connected transistors NM 0   1  to NM n-1 , control node N 2  is gradually discharged. As a result, the transition from a logic one to a logic zero ((n−1)×Vthn) of control signal CT 1  is not abrupt. While control signal CT 1  shifts from a logic one to a logic zero, transistor PM 0  remains off. Therefore, no charge is newly supplied to control node N 2  so that only the charge stored up to the level of supply voltage VCC during pulse width APL from time t 2  is discharged. Thus, the generation of the short-circuit current can be prevented.  
         [0063]     When a value obtained by subtracting a gate voltage (control signal CT 1 ) from a source voltage (internal supply voltage VCC) of transistor PM 1  in waveform shaping circuit  5  exceeds a threshold voltage |VthPM 1 | of transistor PM 1  in consequence of the gradual drop in level of the control signal CT 1  after time t 5 , transistor PM 1  is fully turned on. In this event, transistor PM 1  charges the shaping node N 3  so that control signal CT 2  gradually rises. Since transistor NM 1  in waveform shaping circuit  5  is fully off in this event, the short-circuit current is not generated although control signal CT 1  does not drop down to (n−1)×Vthn. To this end, the charge speed of shaping node N 3  is faster than the discharge speed of control node N 2 . As a result, the rising slope of the waveform of control signal CT 2  becomes steeper than the falling slope of the waveform of control signal CT 1 .  
         [0064]     Since the slope of the waveform of control signal CT 2  output by waveform shaping circuit  5  can be increased, generation of the short-circuit current in subsequent inverters IV 9  to IV 20  can be suppressed and the slope of the waveforms of their output signals also increases. For example, as shown in  FIG. 3 , the slope of the waveform of output signal φA of inverter IV 9  becomes steeper.  
         [0065]     Inverter IV 11  outputs signal AMPDIS at time t 6  in response to control signal CT 2 . Differential amplifier  101  then starts operation in response to a logic zero received from logic gate  10 .  
         [0066]     As understood from the foregoing description, differential amplifier  101  halts operation during the period from time t 2  to time t 6 . Therefore, the average power consumption of oscillator  1  can be reduced.  
         [0067]     Although differential amplifier  101  initializes operation at time t 6 , switch circuit  2  remains off until time t 7  after a lapse of predetermined time ΔT 1  from time t 6 . This prevents malfunction of pulse generator  110  due to noise because immediately after the startup of differential amplifier  101 , operation thereof is unstable so that noise may enter timing signal TMG. Similarly, for preventing malfunction of oscillator  1 , switch circuit  9  remains on up to time t 7  so that latch circuit  3  continues to capture a value of intermediate signal φM at time t 3  that is output by pulse generator  110 .  
         [0068]     At time t 7 , switch signal SW 1  output by delay circuit  6  becomes high and switch signal SW 2  becomes low. As a result, switch circuit  2  is turned on and latch circuit  3  launches output signal SROSC at a value of intermediate signal φM after time t 7 . However, timing signal TMG at node N 20  remains clamped high by voltage clamp circuit  8  at time t 7 . If switch circuit  2  is turned on and further voltage clamp circuit  8  stops operating both at time t 7 , there is a possibility that timing signal TMG at node N 20  will become unstable due to an influence of coupling capacitance in switch circuit  2 . Therefore, the voltage clamp circuit  8  halts operation at time t 8  after a lapse of predetermined time ΔT 2  from time t 7 .  
         [0069]     After the lapse of predetermined time ΔT 2  from time t 7 , i.e. at time t 8 , clamping signal KP from delay circuit  7  transitions high. Therefore, transistor PM 2  in voltage clamp circuit  8  is turned off. By time period t 8 , differential amplifier  101  has recovered from its initial power-on unstable state and outputs a stable timing signal TMG to node N 10 . Then, at time t 9  when voltage V 1  again exceeds reference voltage Vref 1 , differential amplifier  101  asserts timing signal TMG low. Operation after time t 9  is the same as operation after time t 1  so that oscillator  1  outputs a pulse PL per period Tcyc.  
         [0070]     While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.