Abstract:
A terminator circuit for use on a pin of an integrated circuit (IC) is disclosed. A preferred embodiment of the present invention includes a clamp circuit that turns on when the voltage at the pin exceeds a threshold value (either an upper or lower bound). Logic and biasing circuitry are used to allow multiple modes of operation by adjusting the threshold values. A particular mode may be selected at any given time so as to strike an appropriate balance between signal quality and power consumption with respect to a particular terminator or set of terminators. This prevents excessive power consumption due to terminator circuitry at inactive or infrequently active IC pins.

Description:
BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention is related to terminators for electrical connections in digital electronic applications. Specifically, the present invention is directed toward a terminator that allows for different modes of operation in order to balance performance and power consumption. 
   2. Description of Related Art 
   All electrical circuits exhibit non-ideal characteristics. The task of a circuit designer is to find suitable models for the behavior of the circuit being designed, so that the model closely approximates the actual behavior of a real circuit. Such a model may be used to obtain initial values for component parameters (such as resistances and capacitances). The designer may then further adjust or “tweak” the design as necessary to account for the inherent inaccuracies in the design model. This design approach is pervasive in Electrical Engineering. 
   Perhaps the most widely employed design assumption used in modeling electrical circuits is to assume that all signals in a circuit propagate through the circuit at an infinite speed (i.e., without any propagation delay). Although modern physics tells us that this assumption is entirely false, it is nonetheless a valuable analytical simplification and one that can be applied in an enormous number of settings. This assumption of a “zero propagation delay” breaks down, however, in very high speed or timing-sensitive circuits or when a signal must travel a significant distance before reaching its destination. When these sort of conditions occur, it then becomes necessary to adopt a different model. 
   When “zero propagation delay” can no longer be assumed, engineers typically employ what is known as a “transmission line” model, so called because propagation delay becomes a significant factor in the transmission lines used for power or telephone signal transmission, where electrical signals must travel relatively long distances, such that propagation delays become relevant. A transmission line has a characteristic impedance, which reflects the transmission line&#39;s tendency to impede the propagation of a signal travelling along the transmission line. 
   When a transmission line is terminated by a load (such as a resistor, transistor, or other circuit element), the impedance of the load and the characteristic impedance of the transmission line have a significant effect on the ability of the transmission line to accurately transmit the signal that is used to drive the load. The well-known “maximum power transfer theorem” from elementary circuit theory states that maximum power is transferred to the load when the load impedance matches the impedance of the driving circuit, and that less than the maximum amount of available power is transferred when there is an impedance mismatch. In the case of a transmission line, the available power that fails to be transferred to the load is “reflected” away from the load and back toward the driving circuit (note that this reflection phenomenon becomes perceptible in a transmission line model, since a non-zero propagation delay is assumed). The fraction of power that is reflected away from a mismatched load is given as 
               γ   =         Z   L     -     Z   0           Z   L     +     Z   0           ,           (   1   )             
 
where Z L  and Z 0  are the load impedance and the characteristic impedance of the transmission line, respectively.
 
   Where Z L  and Z 0  are matched, it is easy to see that γ=0. Thus, it is standard engineering practice to terminate transmission lines (or electrical connections modeled as transmission lines) in an impedance that matches the characteristic impedance of the line. For example, North American cable television cables are designed to be terminated with a 75 Ω load. Terminating a transmission line in a matching impedance not only results in an efficient transfer of power to the load, but also preserves signal integrity, as reflection due to impedance mismatching can cause signal degradation, including overshoot and undershoot (amplitude-related distortion), and jitter (phase-related distortion). 
   In modern high-speed digital circuits, transmission line effects can be observed in circuits of relatively small size. This is a particularly troublesome phenonmenon in board-level design, where the connections between integrated circuits (ICs) on a circuit board may act like transmission lines. In such instances, it is important to terminate the connections (pins) to integrated circuits in matching impedances, so as to reduce signal degradation due to transmission-line effects. A typical terminator circuit, as employed in the art, is depicted in FIG.  1 . 
   Here resistor R 1  and resistor R 2  make up the terminator. Resistors R 1  and R 2  are connected to each other and transmission line  100  at node  102 . Resistors R 1  and R 2  are also tied to ground and a positive voltage supply, respectively. Node  102  is the point of connection to an integrated circuit from transmission line  100 . The impedance of the terminator (i.e., the two resistors together) is given by 
                 R   total     =         R   1     ⁢     R   2           R   1     +     R   2           ,           (   2   )             
 
as is well-known in the art. Resistors R 1  and R 2  prevent degradation of the input signal represented by voltage source Vsrc, by matching the characteristic impedance of transmission line  100 , which connects voltage source Vsrc with the terminator comprising resistors R 1  and R 2 .
 
   One of ordinary skill in the art, however, will recognize that because resistors R 1  and R 2  themselves form a complete circuit with ground and the positive voltage supply, resistors R 1  and R 2  constantly dissipate power in the form of heat. In a very large scale integration (VLSI) circuit having many pins, even a small amount of current flowing through these terminator resistors can add up to an unacceptably high amount of power dissipation. Thus, there is a need for a terminator circuit that minimizes power dissipation in a very large scale integrated circuit design. 
   SUMMARY OF THE INVENTION 
   The present invention provides a terminator circuit for use on a pin of an integrated circuit (IC). A preferred embodiment of the present invention includes a clamp circuit that turns on when the voltage at the pin exceeds a threshold value (either an upper or lower bound). Logic and biasing circuitry are used to allow multiple modes of operation by adjusting the threshold values. A particular mode may be selected at any given time so as to strike an appropriate balance between signal quality and power consumption with respect to a particular terminator or set of terminators. This prevents excessive power consumption due to terminator circuitry at inactive or infrequently active IC pins. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
       FIG. 1  is a schematic diagram of a typical terminator circuit as known in the art; and 
       FIG. 2  is a schematic diagram of a terminator circuit in accordance with a preferred embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2  is a schematic diagram of a terminator circuit  200  in accordance with a preferred embodiment of the present invention. Terminator circuit  200  is a MOS (metal-oxide semiconductor) integrated circuit, but one of ordinary skill in the art will recognize that the teachings of the present invention may be applied to other circuit technologies, such as bipolar-transistor-based circuits, GaAs (gallium arsenide) semiconductors, and the like. 
   As is generally the case with MOS-based integrated circuits, terminator circuit  200  is comprised primarily of MOSFETs (MOS field-effect transistors). In general, N-channel MOSFETs in  FIG. 2  are generally labeled with reference symbols that begin with the letter “N” (e.g., MOSFET N 13 ), and P-channel MOSFETs are generally labeled with reference symbols that begin with the letter “P,” according to common practice. A number of MOSFETs in  FIG. 2 , however, are labeled with reference symbols that begin with the letter “R,” as resistors are generally labeled in the electronics field. Those MOSFETs in  FIG. 2  that are labeled in this way (e.g., MOSFET R 6 ) are so labeled because they are being used as resistive elements in circuit  200  (i.e., they are used as if they were resistors). 
   It is well-known in the integrated circuit field that a transistor (e.g., field-effect transistor, bipolar junction transistor (BJT), etc.) may be used as a resistive element by connecting the gate of the transistor (or the base, in the case of a BJT) to one of the other transistor terminals. This is commonly referred to as “diode-connecting” a transistor, since a diode-connected BJT will function essentially like a diode. For example, the gate of MOSFET R 6  (an N-channel MOSFET) is connected to the drain MOSFET R 6 . In the interest of conceptual clarity, then, these “R” components will be hereinafter described as “resistive elements.” The other P- and N-channel MOSFETs will be hereinafter referred to as “PFETs” and “NFETs,” respectively. 
   Terminator circuit  200  is conceptually divided into three main sections, logic section  202 , biasing section  204 , and clamp section  206 . Node  208  connects terminator circuit  200  with the electrical connection to be terminated (e.g., such as a pin of an integrated circuit). Inputs  210  and  212 , labeled “dcl” and “aggr_in” respectively, are used to select a mode of operation for terminator circuit  200 . In this preferred embodiment, terminator circuit  200  supports two modes of operation in which clamp section  206  is enabled. Terminator circuit  200  may also be disabled using “dcl” input  210 . One of ordinary skill in the art will recognize, however, that more or fewer modes may be supported by an actual embodiment without departing from the scope and spirit of the present invention 
   The “termination” function of terminator circuit  200  is primarily performed by NFETs N 41  and N 8 , PFETs P 27  and P 24 , and resistive elements R 6 , R 7 , R 1 , and R 0 , which together form two clamps connected in parallel to node  208 . The principal of operation of these clamps may be more easily understood by considering the operation of a single clamp. We thus turn our attention to the clamp formed by resistive element R 7 , NFET N 8 , PFET P 24 , and resistive element R 0 , which are connected in a cascode (totem-pole) configuration. 
   The operation of this clamp is largely controlled by the node voltages the gates of NFET N 8  and PFET  24 , as measured with respect to node  208 . When the voltage at node  208  falls sufficiently low with respect to the voltage at the gate of NFET N 8 , NFET N 8  turns on and current begins to flow from the positive supply rail (Vdd), through resistive element R 7 , to pull up the voltage at node  208 . Likewise, when the voltage at node  208  becomes sufficiently large with respect to the voltage at the gate of PFET P 24 , PFET P 24  turns on and resistive element R 0  begins to sink current from node  208  to ground, thus pulling down the voltage at node  208 . 
   Essentially, then, NFET N 8  and PFET P 24  act as switches that selectively connect and disconnect terminating impedances (resistive elements R 7  and R 0 ) to provide protection against overshoot, undershoot, and jitter, as needed. Because these impedances are switched in and out of the circuit, the average power dissipated through these impedances over time is reduced. The threshold voltage at which the impedances are switched in and out of the circuit is determined by the voltages present at the gates of NFET N 8  and PFET P 24 . Since resistive elements R 6  and R 1 , NFET N 41 , and PFET P 27  form a second clamp that is structurally identical to and connected in parallel with the clamp formed by R 7 , NFET N 8 , PFET P 24 , and resistive element R 0 , one of ordinary skill in the art will recognize that this second clamp operates in the same fashion and is biased by the same gate voltages. 
   Moving backwards through circuit  200 , it can be seen that biasing section  204  supplies bias voltages to the gates of NFETs N 41  and N 8  and to the gates of PFETs P 27  and P 24 . The actual amount of bias voltage applied to the gates of these transistors is determined according to logic section  202 , which, in turn, is controlled by “dcl” input  210  and “aggr_in” input  212 . 
   “dcl” input  210  is the “disable clamp” input to circuit  200 . When “dcl” input  210  is high (i.e., set to a logic value of 1), clamp section  206  is said to be “disabled.” Specifically, when “dcl” input  210  is high, PFETs P 30 , P 31 , and P 29  (the gates of which are directly coupled to “dcl” input  210 ) are turned off, thus preventing NFETS N 41  and N 8  from receiving the positive bias voltage necessary to enable NFETS N 41  and N 8  to turn on. NFET N 15  is simultaneously turned on by “dcl” input  210 , to bring the gate voltages of NFET N 41  and NFET N 8  to ground potential. Meanwhile, PFET P 7  and NFET N 16  form a CMOS (complementary MOS) inverter and invert the high signal from “dcl” input  210  to apply a logic low signal to the gate of PFET P 5  and to the gates of NFETs N 32 -N 35 . This causes PFET P 5  to turn on and causes NFETs N 32 -N 35  to turn off, thus bringing the gate voltages of PFETs P 27  and P 24  to Vdd (positive supply rail) potential, which prevents PFETs P 27  and P 24  from being able to turn on. 
   When “dcl” input  210  is brought to a logic low value, clamp section  206  is said to be “enabled.” NFET N 15  and PFET P 5  are turned off and PFETS P 30 , P 31 , and P 29  and NFETs N 32 -N 35  are turned on. PFETs P 30 , P 31 , and P 29 , once turned on, form a voltage divider with resistive element R 31 , to apply a positive bias voltage to the gates of NFETs N 41  and N 8 , thus enabling the “pull-up” half of clamp section  206 . Likewise, NFETs N 32 -N 35 , once turned on, form a voltage divider with resistive element N 37  to apply a positive bias voltage to the gates of PFET P 27  and PFET P 24 , thus enabling the “pull-down” half of clamp section  206 . 
   The particular positive bias voltages applied to the gates of NFETs N 41  and N 8  and PFETs P 27  and P 24  will differ according to the mode in which terminator circuit  200  is operated. The mode that is used by circuit  200 , when enabled, is determined by “aggr_in” input  212 . In this preferred embodiment, two modes of operation (and thus, two sets of positive bias voltages) are defined, namely an aggressive mode and a non-aggressive mode. These two modes are provided to allow a finer level of control over the tradeoff between performance and power dissipation to be made, over and above the control provided by “dcl” input  210 . 
   When “aggr_in” input  212  is set to a logic low value, circuit  200  is said to be operating in non-aggressive mode. Specifically, the logic low at “aggr_in” input  212  is inverted to a logic high by the CMOS inverter made up of PFET P 4  and NFET N 13 . This logic high is applied to the gates of NFETs N 14  and N 17 , which turns on NFETs N 14  and N 17 . This causes NFETs N 14  and N 17  to function as a parallel resistance in the circuit with respect to resistive element R 31 . As the overall resistance of a set of parallel resistances is lower than any of the individual resistances, this causes the ground-connected portion of the voltage divider formed with PFETs P 29 -P 30  and resistive element R 31  to have a lower resistance than the vdd-connected portion of the voltage divider (the vdd-connected portion being made up of PFETs P 29 -P 30 , and the ground-connected portion being made up of NFETs N 14  and N 17  and resistive element R 31 ). This has the effect of lowering the bias voltage applied to the gates of NFETs N 41  and N 8 , which requires node  208  to reach a higher voltage threshold to turn on NFETs N 41  and N 8  than would be necessary if NFETs N 14  and N 17  were turned off. Thus, this mode is called “non-aggressive,” because the lower bias voltage makes NFETs N 14  and N 17  less likely to turn on and, hence, less aggressive in trying to pull up the signal at node  208 . 
   The pull-down portion of circuit  200  operates similarly in non-aggressive mode. PFETs P 6  and P 3  are turned on, which reduces the effective resistance of the vdd-connected portion of the voltage divider formed with NFETs N 32 -N 35  and thus raises the bias voltage applied to the gates of PFETs P 27  and P 24 , which raises the threshold for turning on the PFETs P 27  and P 24  in the pull-down portion of clamp section  206 . 
   In aggressive mode, on the other hand, “aggr_in” is at a logic high level and NFETs N 14  and N 17 , as well as PFETs P 6  and P 3 , are turned off. This has the effect of increasing the bias voltage applied to the gates of NFETs N 41  and N 8  and decreasing the bias voltage applied to the gates of PFETs P 24  and P 27 . This causes clamp section  206  to be more aggressive in trying to pull-up or pull-down the voltage at node  208 , since the thresholds for switching on NFETs N 41  and N 8  and PFETs P 24  and P 27  are reduced (in sense that not as high a voltage is needed at node  208  to initiate a pull-down by PFETs P 27  and P 24  and not as low a voltage is needed at  208  to initiate a pull-up by NFETs N 41  and N 48 . 
   To summarize, terminator circuit  200  follows the truth table provided in Table I for determining whether clamp section  206  is to be operated in aggressive mode, non-aggressive mode, or disabled. 
   
     
       
             
             
             
             
           
         
             
                 
               TABLE I 
             
             
                 
                 
             
             
                 
               dcl 
               aggr_in 
               Mode 
             
             
                 
                 
             
           
           
             
                 
               0 
               0 
               Clamp section on in non-aggressive mode 
             
             
                 
               0 
               1 
               Clamp section on in aggressive mode 
             
             
                 
               1 
               any 
               Clamp section off (disabled) 
             
             
                 
                 
             
           
        
       
     
   
   One of ordinary skill in the art will appreciate that a terminator design in accordance with the teachings of the present invention may be used in a variety of contexts in which an electrical connection requires termination with an appropriate impedance. In particular, an integrated circuit utilizing a terminator in accordance with the teachings of the present invention to terminate integrated circuit pins may utilize the multimode features of such a terminator in order to dynamically adjust the balance between performance and power consumption as needed for the integrated circuit&#39;s task at hand. For example, pins that are not currently being used can have their terminators disabled. As a further example, pins that must receive high-speed signals can have their terminators placed in aggressive mode, for maximum performance, while less timing-critical pins can utilize pins in non-aggressive mode. 
   The description of the present invention has been presented for purposes of illustration and description, and is not intended to he exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.