Abstract:
A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to integrated circuit packaging and more specifically, to a method and assembly for packaging integrated circuit dies along with passive elements.  
         BACKGROUND OF THE INVENTION  
         [0002]    In general, electronic elements are either active or passive elements. Active elements typically include a non-linear feature and passive elements generally never operate nonlinearly while operating in their linear region. A typical example of an active element is a semiconductor die such as a transistor, an Integrated Circuit (IC) or a similar device. A typical example of a passive element is a capacitor, a resistor, an inductor or a similar device.  
           [0003]    A passive element is usually an external device electrically connected to a semiconductor package and serves to assist the operation the active element (the semiconductor die) by performing a filtering functions or other similar functions. However, when a passive element is mounted on the periphery of a semiconductor package as mentioned above, the area of the circuit is increased and the mounting density of semiconductor packages is greatly lowered.  
           [0004]    To reduce the area consumed by passive elements, a structure and method of manufacture for semiconductor packages have been recently proposed in which a passive element is directly mounted on a substrate, which is a structural element of the semiconductor package. The proposed structure will be described below.  
           [0005]    A substrate having multiple electrically conductive patterns formed on a top and bottom surface is provided. A semiconductor die is then bonded to the center of the top surface of the substrate. Multiple passive elements are mounted on the electrically conductive patterns located at the periphery of the semiconductor die and bond pads of the semiconductor die are electrically connected to the electrically conductive patterns of the top surface of the substrate by conductive connector (for example, a conductive wire). Also, multiple conductive balls are fused to the electrically conductive patterns of the bottom surface of the substrate. Finally, an encapsulant is applied over the entire top surface of the substrate so that the semiconductor die, the conductive connector and the passive elements are protected from the external environment.  
           [0006]    The passive elements can be mounted on the electrically conductive patterns of the top surface of the substrate using SMT (Surface Mount Technology) or THT (Through Hole Technology), which are typically soldered electrical and mechanical connections.  
           [0007]    However, the above-described semiconductor package has various disadvantages. First, since the passive elements are mounted on the substrate located at the periphery of the semiconductor die, the area of the substrate must be increased substantially to accommodate the passive elements. Second, to maintain a small substrate area, the passive elements are usually mounted in the vicinity of a singulation line. Therefore, if a substrate warps, passive elements can be damaged by the singulation blade due to relatively small tolerances between a body of the passive element and the singulation line, thus reducing manufacturing yield.  
           [0008]    Second, since the passive elements are mounted on the periphery of the substrate, the substrate must be uniquely designed for a particular part due to the configuration of electrically conductive patterns. Further, a cover coat cannot be applied over the passive element locations during manufacture of the substrate, since the passive elements must be subsequently connected.  
           [0009]    Third, if a semiconductor die is sensitive to interference, electromagnetic coupling from the passive elements to the semiconductor die is increased in the above-described design, reducing the electrical performance of the die and causing operational errors.  
           [0010]    Finally, the semiconductor die is present during both the passive element mounting process and during the semiconductor package mounting process (in which the package including the passive element is mounted in an external device). The above-described process subjects the substrate and the semiconductor die to thermal stress in two different steps, increasing the tendency of the substrate and the semiconductor package to crack.  
           [0011]    Therefore, it would be desirable to provide an improved semiconductor package including passive elements and manufacturing method therefor that reduces substrate area, eliminates the risk of damage during singulation, decreases electromagnetic interference between the passive elements and a semiconductor die and subjects the semiconductor die and substrate to less thermal stress during manufacture.  
         SUMMARY OF THE INVENTION  
         [0012]    The above stated objectives are achieved in various assemblies and methods for packaging a semiconductor die in conjunction with passive elements. The assemblies include a substrate formed from a resin layer having electrically conductive patterns disposed on a top and a bottom surface, multiple passive elements connected to mounting pads forming part of the electrically conductive patterns near the center of the substrate, a semiconductor die mounted above the passive elements on the substrate, multiple conductive connectors for connecting the semiconductor die to the electrically conductive patterns and an encapsulation applied over the semiconductor die and conductive connectors. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1A is a sectional view illustrating semiconductor packages according to one embodiment of the present invention;  
         [0014]    [0014]FIG. 1B is a sectional view illustrating semiconductor packages according to another embodiment of the present invention;  
         [0015]    [0015]FIG. 2A is a sectional view illustrating semiconductor package according to another embodiment of the present invention;  
         [0016]    [0016]FIG. 2B is a perspective view illustrating a state of the semiconductor package of FIG. 2A before forming the encapsulating portion;  
         [0017]    [0017]FIG. 3A is a sectional view illustrating semiconductor packages according to another embodiment of the present invention;  
         [0018]    [0018]FIG. 3B is a sectional view illustrating semiconductor packages according to another embodiment of the present invention;  
         [0019]    [0019]FIG. 4 is a sectional view illustrating semiconductor packages according to another embodiment of the present invention;  
         [0020]    [0020]FIG. 5 is a sectional view illustrating semiconductor packages according to another embodiment of the present invention;  
         [0021]    [0021]FIG. 6 is a sectional view illustrating semiconductor packages according to another embodiment of the present invention; and  
         [0022]    [0022]FIG. 7A through FIG. 7C are sectional views respectively illustrating a sequence of steps which may be employed for manufacturing the semiconductor package of FIG. 6. 
     
    
       [0023]    The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout.  
       DETAILED DESCRIPTION  
       [0024]    Referring to FIG. 1A and FIG. 1B, semiconductor packages  100   a  and  100   b  according to embodiments of the present invention are illustrated. As shown in the drawings, a substrate  110  of an planar plate including a resin layer  111  and a plurality of electrically conductive patterns  112  formed on the top and bottom surfaces of the resin layer  111  are provided. The substrate may be a printed circuit board, circuit tape or circuit film or similar structure. Therefore, when this specification is uses the term printed circuit board, it should be understood to mean a substrate such as those mentioned above.  
         [0025]    Substrate  110  includes resin layer  111  and electrically conductive patterns  112  formed on the top and bottom surfaces of resin layer  111 . Electrically conductive patterns  112  on the top surface of resin layer  111  and electrically conductive patterns  112  on the bottom surface of the resin layer  111  are electrically connected to each other by a plurality of electrically conductive vias  113 . Also, electrically conductive patterns  112  on the top surface of resin layer  111  include bond fingers  112   a  which are connected to conductive connectors  150  as described below. Electrically conductive patterns  112  on the bottom surface of the resin layer  111  include ball lands  112   b  to which conductive balls  171  as described below are fused. The surface of conductive circuit patterns  112  (with the exception of bond fingers  112   a  and ball lands  112   b ) is coated with a insulating layer  114 , thereby protecting the conductors from the external environment. However, the passive element mounting region is not coated with the insulating layer  114 .  
         [0026]    Passive elements  120  are located at the center of the top surface of substrate  110 . Passive element  120  is electrically connected to electrically conductive patterns  112  formed on the central area of the top surface of the substrate  110 . Passive elements  120  are connected to the electrically conductive patterns in a SMT (Surface Mount Technology) manner using solder  121 . The passive elements may also be connected in a THT (Through Hole Technology) manner and the present invention is not limited to any specific form of passive component mounting.  
         [0027]    A semiconductor die  141  having a plurality of bond pads  143  formed on its top surface is bonded to the top surface of the passive elements  120  by an adhesive  130 . Passive element  120  is thereby located at the region corresponding to the bottom surface of the semiconductor die  141 . Adhesive  130  may be one of a nonconductive epoxy, a nonconductive polyimide, a nonconductive double-faced adhesive tape or its equivalent. The present invention is not limited to the use of any particular adhesive material.  
         [0028]    A nonconductive epoxy or nonconductive polyimide is used for adhesive  130  in the semiconductor package  100   a  as shown in FIG. 1A. A nonconductive double-faced adhesive tape is used for adhesive  130  in the semiconductor package  100   b  as shown in FIG. 1B. When epoxy or polyimide are used for adhesive  130 , the semiconductor die  141  is bonded after the epoxy or polyimide is applied in the shape of dots or linear patterns to the region where passive elements  120  are located. When a double-faced adhesive tape is used, each semiconductor die is cut from a wafer after the double-faced adhesive tape is bonded to one surface of the wafer during the wafer mounting process. The sawed semiconductor die including double-faced adhesive tape attached to the bottom surface is then bonded to the top surface of passive elements  120 . Use of double-faced adhesive tape can effectively prevent delamination at the interface between the passive elements and the semiconductor die that may occur when using the epoxy or polyimide in addition reducing electrical interference between passive elements  120 .  
         [0029]    Bond pads  143  of semiconductor die  141  and bond fingers  112   a  of electrically conductive patterns  112  are electrically connected by a conductive connector  150 . Conductive connector  150  may be one of a gold wire (Au wire), an aluminum wire (Al wire) or an equivalent and the present invention is not limited to use of any particular conductive connector material. Finally, the top surface of the substrate  110  as well as semiconductor die  141  and conductive connectors  150  are encapsulated by an encapsulant in order to protect them from the external environment. Here, the encapsulating region is defined as an encapsulating portion  160 . The encapsulant may be any one of an epoxy molding compound, a liquefied glob top or an equivalent, and again the present invention is not limited to a particular encapsulating material. After encapsulation, a plurality of conductive balls  171  such as solder balls are fused to the lands of electrically conductive patterns  112  on the bottom surface of the substrate  110  to permit the semiconductor package to be connected to a external device.  
         [0030]    Therefore, there is no need to increase the area of substrate  110  as in the prior art to accommodate the passive elements  120 , resulting in a miniaturization of the semiconductor package by the techniques of the present invention. Further, passive elements  120  will not contact the blade during singulation in the manufacturing process, preventing damage to the passive elements.  
         [0031]    Further, the passive elements  120  are mounted in a concentrated arrangement within the central area of the top surface of substrate  110 , and as a result electrically conductive patterns  112  can be more easily designed.  
         [0032]    Referring now to FIG. 2A and FIG. 2B, a semiconductor package  200  according to another embodiment of the present invention is illustrated. Since semiconductor package  200  as shown in FIGS. 2A and 2B is similar to the semiconductor packages  100   a  and  100   b  of FIGS. 1A and 1B, only differences between the embodiments will be described in detail below.  
         [0033]    As shown in the drawings, a dam  252  which has a height greater than the maximum height of passive element  220  further formed on the top surface of the substrate at the circumference of passive elements  220 . Dam  252  prevents adhesive  230  overflow and also reduces electromagnetic interference that emanates from the passive elements. It is preferred that dam  252  be made of nonconductive materials. Further, dam  252  is larger than semiconductor die  241  and surrounds the sides of semiconductor die  241 . Adhesive  230  located at the inside of the dam  252  may be any one of a nonconductive epoxy, a nonconductive polyimide, a nonconductive double-faced adhesive tape or an equivalent and the present invention is not limited to the use of a particular adhesive.  
         [0034]    Semiconductor package  200  of the present invention as shown in FIG. 2A and FIG. 2B has all of the advantages as the embodiments depicted in FIG. 1A and FIG. 1B. Also, in the case of using the semiconductor die that is sensitive to interference, interference emanating from the passive elements is minimized, thereby preventing reduction of performance of the semiconductor die as well potential operational error.  
         [0035]    Referring next to FIG. 3A and FIG. 3B, semiconductor packages according to another embodiment of the present invention are illustrated. As the semiconductor packages as shown in FIG. 3A and FIG. 3B are similar to semiconductor packages  100   a  and  100   b  of FIG. 1A and FIG. 1B, only differences between the embodiments will be described in detail below.  
         [0036]    A recess  311   a  having a predetermined depth smaller than the height of semiconductor die  341  is formed in the central area of the top surface of a substrate  310 . Electrically conductive patterns  312  are formed at the bottom of recess  311   a  and passive elements  320  are connected to the electrically conductive patterns  312  formed in the bottom of recess  311   a . Passive elements  320  can be connected in a SMT or THT manner and it is preferred that the thickness of the passive element  320  is offset by the depth of recess  311   a . Moreover, it is preferred that the top surface of the passive element  320  does not contact the bottom surface of semiconductor die  341 . Semiconductor die  341  is bonded to the top surface of substrate  310  at the circumference of the recess  311   a  by an adhesive  330 . In the present embodiment, encapsulant does not enter the inside of recess  311   a . Since the semiconductor die  341  is bonded to the upper part of the recess  311   a  by adhesive  330  such as a nonconductive epoxy, a nonconductive polyimide, a nonconductive double-faced adhesive tape or an equivalent, the encapsulant does not fill the inside of the recess  311   a  during the encapsulating process.  
         [0037]    As shown in FIG. 3B, conductive bumps can be used as a conductive connector  350  for connecting semiconductor die  341  to bond fingers  312   a  of electrically conductive patterns  312 . In the depicted embodiment, semiconductor die  341  is connected to substrate  310  in a flip die manner. After conductive bumps are formed at bond pads  343  of semiconductor die  341 , the conductive bumps are connected to electrically conductive patterns  312  by turning the semiconductor die  341  bond pad side down. In the above-described embodiment, encapsulating portion  360  reaches the inside of recess  311   a , as the conductive bumps do not completely block the flow of encapsulant. When using the flip die method described above, since the loop height of conductive connector  350  as shown in FIG. 3A is eliminated, semiconductor package  300   b  can be made thinner than semiconductor package  300   a.    
         [0038]    Referring next to FIG. 4, a semiconductor package  400  according to another embodiment of the present invention is illustrated. Since the semiconductor package shown in FIG. 4 is similar to semiconductor packages  300   a  and  300   b  of FIG. 3A and FIG. 3B, only differences between the embodiments will be described in detail below.  
         [0039]    As shown in FIG. 4, an aperture  411   b  having a predetermined diameter or size can be further formed passing through the bottom surface of recess  11   a  to the bottom surface of substrate  411   b . Thermal transfer of the package is improved as a result of air circulation to semiconductor die  441  and passive elements  420  from the outside. Also, water can freely exit the package, preventing delamination at the interface between the semiconductor die  441  and substrate  411   b  and cracking of the semiconductor die  441  or the passive elements  420  due to steam (popcorn effect).  
         [0040]    Referring now to FIG. 5, a semiconductor package  500  according to another embodiment of the present invention is illustrated. Since semiconductor package  500  as shown in FIG. 5 is similar to semiconductor packages  100   a  and  100   b  of FIG. 1A and FIG. 1B, only differences between the embodiments will be described in detail below.  
         [0041]    As shown in FIG. 5, a first semiconductor die  541  is connected with a second semiconductor die  542  in a flip die arrangement. A stack type semiconductor package is thereby implemented so that first semiconductor die  541  and second semiconductor die  542  are electrically interconnected through a bump bond  580  which is formed at a specific bond pad  543  of first semiconductor die  541  or second semiconductor die  542 . This feature can be applied to all embodiments of the present invention. The top surface of second semiconductor die  542  and a part of the side surface of the second semiconductor die  542  are exposed to outside air, improving the thermal transfer performance of the package. Function and efficiency of the semiconductor package are improved by stacking the semiconductor dies.  
         [0042]    Referring next to FIG. 6, a semiconductor package  600  according to another embodiment of the present invention is illustrated. As shown in the drawing, a substrate  610  including a resin layer  611  having an aperture  611   c  formed at its center and a plurality of electrically conductive patterns  612  formed on the top and bottom surfaces of the resin layer is provided. Substrate  610  may be a printed circuit board, circuit tape or circuit film and or the like as described above.  
         [0043]    A plurality of passive elements  620  are mounted inside the aperture  611   c  of the substrate  610 . A semiconductor die  641  is bonded to the top surfaces of passive elements  620  by an adhesive  630  such as double-faced adhesive tape. Bond pads  643  of semiconductor die  641  and bond fingers  612   a  of electrically conductive patterns  612  are electrically connected to each other by the conductive connectors  650 . Aperture  611   c , passive elements  620 , semiconductor die  641  and conductive connectors  650  are encapsulated by an encapsulant to form an encapsulation  660 . In the depicted embodiment, the bottom surface of passive element  620  is exposed to the outside of the encapsulating portion  660 .  
         [0044]    Finally, conductive balls  671  (such as solder balls) are fused to lands  612   b  of electrically conductive patterns  612  on the bottom surface of substrate  610  and also to the bottom surface of passive elements  620  where exposed to the outside of the encapsulating portion  660  to provide connection to an external device. Passive elements  620  are not connected to electrically conductive patterns  612  but instead are directly connected to electrically conductive patterns of an external device. The depicted embodiment provides a mounting region for passive elements  620  connected to an external device but located within semiconductor package  600 , thereby greatly increasing the mounting density of the semiconductor die/passive element combination.  
         [0045]    Also, fabrication of an assembly including semiconductor package  600  and passive elements  620  can be accomplished more efficiently as all of the above-mentioned components and be installed in one step, with the additional benefit of minimizing thermal stress induced in substrate  610 , reducing the risk of cracking the semiconductor package.  
         [0046]    Referring to FIG. 7A through FIG. 7C, sectional views of one method for manufacturing one embodiment of the present invention are illustrated. The method according to the present invention will be described in a stepwise manner with reference to FIGS. 7A through 7C.  
         [0047]    As shown in FIG. 7A, an adhesive tape  680  is bonded to one surface of substrate  610  in which aperture  611   c  is formed. Then, passive elements  620  are arrayed on a region of adhesive tape  680  inside aperture  611   c.    
         [0048]    Next, semiconductor die  641  is bonded to the top surface of passive elements  620  using adhesive  630 . Then, aperture  611   c  of substrate  610 , semiconductor die  641  and conductive connectors  650  are encapsulated by an encapsulant to form encapsulation  660 , after semiconductor die  641  and the electrically conductive patterns  612  are electrically connected to each other by conductive connector  650 .  
         [0049]    Next, as shown in FIG. 7B, adhesive tape  680  is removed from the substrate  610 , so that the bottom surface of passive element  620  is exposed to the outside of the encapsulation  660 . Referring now to FIG. 7C, after fabrication of the package, conductive balls  671  are fused to lands  612   b  of electrically conductive patterns  612  on the bottom surface of substrate  610  and bottom surface of passive elements  620  to complete fabrication of the semiconductor package  600 .  
         [0050]    Therefore, according to the embodiments of the present invention and despite using the substrate having a relatively small area, a number of passive elements can be mounted on the substrate, thereby reducing circuit size and minimizing damage to the passive elements during the fabricating process (for example, damage occurring during the singulation process).  
         [0051]    Further, the passive elements are mounted in a concentrated manner at the central area of the top surface of substrate  610 , facilitating design of the electrically conductive patterns and improving the yield of the semiconductor package. Moreover, when using a semiconductor die sensitive to interference, a closure member (for example, a nonconductive adhesive and dam) is formed around the passive elements, thereby averting reduction in electric performance of the die and operational errors in the die. Efficiency and functionality of the semiconductor package may further be increased by stacking the semiconductor dies and interconnection and mounting of the semiconductor package requires one less step, reducing the risk of cracking the semiconductor package and passive elements.  
         [0052]    This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.