Abstract:
A hybrid modulator apparatus includes a modulator that amplitude modulates a power supply signal. A correction circuit coupled in parallel with the modulator reduces errors caused by the modulator. In one embodiment the modulator includes a digital pulse-width modulator (PWM) and a buck converter. The K most significant bits (MSBs) of N-bit input digital words are used by the digital PWM and a buck converter to generate an amplitude modulated power supply signal having a plurality of quantized voltage levels. The remaining N−K bits of each N-bit words may be used to dither the input drive to the PMW, to produce an error signal at the output of the modulator representing quantization errors caused by only applying the K MSBs to the PWM. The correction circuit compares the error signal to a signal formed form all N bits of the N-bit words in reducing the quantization errors.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to radio frequency (RF) transmitters. More specifically, the present invention relates to highly-efficient hybrid class-S modulators for RF transmitters. 
     BACKGROUND OF THE INVENTION 
     Conventional wireless communication transmitters typically employ a quadrature modulator (also referred to as an “I/Q” modulator) to modulate two orthogonal baseband data streams—an in-phase data stream and a quadrature-phase data stream—onto a radio frequency (RF) carrier.  FIG. 1  is a block diagram of a prior art quadrature modulator  10 . The quadrature modulator  1  comprises an I-channel mixer  10 , a Q-channel mixer  12 , a local oscillator (LO)  14 , a phase shifter  16  and a summer  17 . The I-channel mixer  10  is configured to receive the in-phase data stream and a radio frequency (RF) carrier signal from the LO  14 . At the same time, the Q-channel mixer  12  is configured to receive the quadrature-phase data stream and a ninety-degree phase shifted version of the carrier signal, by operation of the ninety-degree phase shifter  16 . The I- and Q-channel mixers  10  and  12  upconvert both the in-phase and quadrature-phase data streams to the frequency of the RF carrier. The summer  17  combines the upconverted in-phase and quadrature-phase signals and feeds the sum to an input of an RF power amplifier (RFPA)  18 . The RFPA  18  amplifies the upconverted sum and feeds the upconverted sum to an antenna  19 , which radiates the modulated RF carrier for reception by an RF receiver. 
     A significant drawback of the I/Q modulator is that it is not very power efficient, especially when used to condition and transmit non-constant-envelope signals such as EDGE ( E nhanced  D ata Rates for  G SM (Global System for Mobile Communications)  E volution) and W-CDMA ( W ideband  C ode  D ivision  M ultiple  A ccess). To minimize distortion of the signal peaks when conditioning and transmitting such signals, the drive levels to the RFPA must be reduced to prevent signal clipping, and the RFPA must be configured to amplify in a linear mode of operation. Unfortunately, linear power amplifiers are not particularly efficient. 
     A polar modulator is a type of modulator that avoids the linearity requirement of the RFPA and, because so, is considerably more efficient than the conventional I/Q modulator.  FIG. 2  is a block diagram illustrating the principle components of a typical prior art polar modulator  2 . The polar modulator  2  comprises a rectangular-to-polar converter  20 ; an amplitude modulator  22  configured within a magnitude path of the modulator  2 ; and a phase modulator  24  and voltage controlled oscillator (VCO)  26  configured within a phase path of the modulator  2 . 
     The rectangular-to-polar converter  20  converts I and Q baseband data streams into separate magnitude and phase paths. The amplitude modulator  22  receives the amplitude data ρ(t) in the magnitude path and modulates a power supply voltage (Vsupply) according to the amplitude of ρ(t). The phase modulator  24  receives the constant-amplitude phase data dφ/dt in the phase path, and drives the voltage controlled oscillator (VCO)  26  to provide an RF drive signal to the RFPA  28 . 
     The RFPA  28  in the polar modulator  2  in  FIG. 2  is configured as a highly-efficient nonlinear switched-mode RFPA. The RFPA  28  remains in compression while the drain voltage of the RFPA  28  is varied. By modulating the drain supply, the amplitude information of non-constant envelope signals such as EDGE and W-CDMA can be efficiently superimposed on the RF signal from the phase path of the modulator  2 . 
     The amplitude modulator  22  in the amplitude path of the polar modulator  2  may be formed in various ways. One known approach is to use a class-S amplitude modulator  30  to modulate the drain supply to the RFPA  32  of the polar modulator, as shown in the polar modulator  3  depicted in  FIG. 3 . Class-S modulators are more efficient than conventional linear modulators and, when configured for amplitude modulation in the magnitude path of a polar modulator, provide a highly-efficient means for modulating an RF carrier. Further, because the class-S modulator  30  is configured within the magnitude path of the polar modulator  3 , and the drive signal to the RFPA  32  is a constant-magnitude phase modulated signal within the phase path of the polar modulator  3 , distortion caused by the clipping of signal peaks in non-constant envelope signals, such as EDGE and W-CDMA, can be avoided. 
     A more detailed view of a class-S modulator  4  is shown in  FIG. 4 . The class-S modulator  4  comprises a comparator  40 , a level shifter and gate driver  41 , and a buck converter that includes a switching transistor  42 , a diode  43 , an inductor  44  and a capacitor  45 . When configured in the amplitude path of a polar modulator, the amplitude values in the amplitude path are compared to a triangular reference signal to produce a pulse-width-modulated (PWM) signal. The resulting PWM signal is comprised of a series of pulses having durations that vary in proportion to the amplitude values at the comparator input. 
     Together, the switching transistor  42  and diode  43  in the buck converter portion of the class-S modulator act as a single-pole double-throw (SPDT) switch. Current flows through switching transistor  42  when it is ON and through diode  43  when transistor  42  is OFF. Switching the buck converter with the PWM signal from the driver generates a high-level PWM signal. The high-level PWM signal is converted back into an analog signal by the low-pass output filter formed by the inductor  44  and the capacitor  45 . 
     Accurate envelope tracking of the amplitude signal requires that the switching frequency of the buck converter be about twenty to fifty times higher than the required signal envelope bandwidth. For a signal such as EDGE, the envelope bandwidth is approximately 1 MHz. This means that for EDGE type signals, the transistor in the buck converter would have to be capable of switching at a rate of 20-50 MHz rate. Unfortunately, the switching transistor (typically a silicon-based MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or BJT (Bipolar Junction Transistor)) in state-of-the-art buck converters can only be switched up to a maximum of about 5 MHz. For this reason, conventional class-S modulators are not well-suited for EDGE and other non-constant envelope signals that have high signal envelope bandwidths. 
     What is needed, therefore, is a modulator circuit for a polar modulator that has an efficiency similar to or better than a conventional class-S modulator, and which is capable of transmitting and conditioning non-constant envelope signals such as EDGE and W-CDMA, while satisfying power spectra requirements specified by these standards. 
     SUMMARY OF THE INVENTION 
     Highly-efficient hybrid class-S modulators for polar modulators are disclosed. According to an aspect of the present invention, a hybrid modulator circuit includes a modulator that is operable to modulate a power supply voltage according to amplitude characteristics of an input signal. The modulator generates a modulated power supply voltage signal at an output of the modulator. A correction circuit coupled to the modulator is configured to generate signals to reduce deviations of the modulated power supply voltage signal levels from desired voltage levels. The correction circuit may contain an operational amplifier which is operable to source or sink current to or from the output node of the modulator when the voltage levels of the modulated supply voltage signal are less than or greater than the desired voltage levels. The modulator may also contain a digital pulse-width modulator (PWM) generator that receives digital data and generates a discrete set of PWM signals that drive a buck converter, thereby providing a modulated power supply voltage signal having a plurality of quantized voltage levels. In accordance with this particular aspect of the invention, the circuit coupled to the modulator sources or sinks current to or from the output node of the modulator circuit when a magnitude of a quantized level of said plurality of quantized levels is less than or greater than a desired magnitude. 
     According to yet another aspect of the invention, a modulator circuit has an input port configured to receive a succession of N-bit digital words, where N is an integer that is greater than one. The modulator circuit also includes a modulator that is operable to modulate a power supply voltage according to values represented by the K most significant bits of each N-bit digital word, where K is a positive integer that is less than N. An output port of the modulator circuit is adapted to provide a modulated power supply voltage signal. The modulator circuit further includes a circuit coupled to the modulator that is operable to reduce deviations of voltage levels of the modulated power supply voltage signal from desired voltage levels. In accordance with this aspect of the invention, the modulator may include a pulse-width modulator (PWM) generator configured to receive the K most significant bits of each N-bit digital word and generate a modulated power supply voltage signal having a plurality of quantized voltage levels depending on pulse widths of PWM signals generated by the PWM generator. The deviation of voltage levels of the modulated power supply voltage signal from desired voltage levels may depend, at least in part, on the difference in value of an N-bit word received at the input port and the value of the K most significant bits of the N-bit word applied to PWM generator. 
     According to a related aspect of the invention, an error generated by using only K of the N bits of each N-bit word applied to the PWM is reduced by dithering the input drive and converting the error to an AC signal. According to this aspect of the invention, the N-K least significant bits (LSBs) of each N-bit input word are fed to an input of a digital oscillator, while the K most significant bits (MSBs) of each word are fed to the PWM generator. The N-K LSBs of each N-bit word represent the error resulting from using only K of the N bits at the PWM generator. The digital oscillator converts the N-K LSBs of each input word into an oscillating single LSB. The effect of dithering the input drive in this manner results in an AC error signal appearing at the output of the modulator. This oscillating error signal is fed to the inverting input of the op-amp. At the same time, the desired output voltage, which is represented by the full N bits of the N-bit input words, is coupled to the non-inverting input of the op-amp. The op-amp responds to these input signals by sourcing or sinking current into or out of the modulator output terminal, thereby removing the error attributable to using only K of the N bits at the PWM generator. 
     Other features and advantages of the present invention will be understood upon reading and understanding the detailed description of the preferred exemplary embodiments, found hereinbelow, in conjunction with reference to the drawings, a brief description of which are provided below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a prior art quadrature modulator; 
         FIG. 2  is a block diagram of a prior art polar modulator; 
         FIG. 3  is a block diagram of a polar modulator employing a class-S modulator in the amplitude path of the polar modulator; 
         FIG. 4  is a block diagram of a conventional class-S modulator; 
         FIG. 5  is a diagram of a hybrid class-S modulator, according to an embodiment of the present invention; 
         FIG. 6  is a diagram of a hybrid class-S modulator having an analog pulse-width modulator, according to an alternative embodiment of the present invention; 
         FIG. 7  is a voltage v. time graph of the output voltage waveform produced by a prior art class-S modulator; 
         FIG. 8  is a voltage v. time graph of the output voltage waveform produced by the hybrid class-S modulator shown in  FIG. 5 ; 
         FIG. 9  is a power spectral density (PSD) performance plot, within a 2 MHz span, comparing the PSD of an EDGE modulated carrier produced by the prior art class-S modulator to the EDGE 20W specification; 
         FIG. 10  is a power spectral density (PSD) performance plot, within a 2 MHz span, comparing the PSD of an EDGE modulated carrier produced by the hybrid class-S modulator in  FIG. 5  to the EDGE 20W specification; 
         FIG. 11  is a power spectral density (PSD) performance plot, within a 7 MHz span, comparing the PSD of an EDGE modulated carrier produced by the prior art class-S modulator to the EDGE 20W specification; 
         FIG. 12  is a power spectral density (PSD) performance plot comparing, within a 7 MHz span, the PSD of an EDGE modulated carrier produced by the hybrid class-S modulator in  FIG. 5  to the EDGE 20W specification; 
         FIG. 13  is a current v. time graph showing the peak current supplied by the op-amp of the feed-forward path of the hybrid class-S modulator in  FIG. 5 ; 
         FIG. 14  is a diagram of a hybrid two-inductor class-S modulator, according to an embodiment of the present invention; 
         FIG. 15  is a voltage v. time graph of the output voltage waveform produced by a prior art two-inductor class-S modulator lacking any feed-forward correction; 
         FIG. 16  is a voltage v. time graph of the output voltage waveform produced by the two-inductor hybrid class-S modulator in  FIG. 14 ; 
         FIG. 17  is a current v. time graph showing the peak current supplied by the op-amp of the feed-forward path of the two-inductor hybrid class-S modulator in  FIG. 14 ; 
         FIG. 18  is a diagram of a hybrid class-S modulator that interpolates the modulator output levels by dithering the input drive to the modulator buck converter, according to an embodiment of the present invention; and 
         FIG. 19  is a diagram of an exemplary digital oscillator that may be used in the hybrid class-S modulator in  FIG. 18 . 
     
    
    
     DETAILED DESCRIPTION 
     Those of ordinary skill in the art will realize that the following detailed description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts. 
     Referring first to  FIG. 5 , there is shown a diagram of a hybrid class-S modulator  50 , according to an embodiment of the present invention. The hybrid class-S modulator  50  comprises a modulator path and a feed-forward path. The modulator path includes a pulse-width modulator (PWM) generator  500 , a level shifter and gate driver  502 , and a buck converter that includes a switching transistor  504 , a diode  506 , an inductor  508  and a capacitor  510 . According to this exemplary embodiment, the PWM generator  500  comprises a digital signal processor (DSP) implemented in a field-programmable gate array (FPGA). Those of ordinary skill in the art will readily appreciate and understand that, while the DSP is described in the exemplary embodiment as being implemented in an FPGA, in alternative embodiment the process performed by the DSP could be implemented as software, as firmware, as other hardware (e.g. an application specific integrated circuit (ASIC)), or as any combination of these implementations. 
     The ability to implement a totally digital PWM generator follows from the ability of the class-S modulator to be driven by a digital (i.e. ON/OFF) signal. Hence, an added benefit of the completely digital PWM generator is that any nonlinear affects caused by the triangular reference and/or comparator in the conventional class-S modulator (see  FIG. 4 ) are avoided. The digital implementation is also more immune to noise, which in an analog implementation can sometimes cause the comparator to trigger when it is not desired. 
     As described above, the hybrid class-S modulator  50  comprises a modulator path and a feed-forward path. The feed-forward path comprises a digital-to-analog converter (DAC)  512 , an amplifier (e.g., an operational amplifier (“op-amp”))  514  having inverting (−) and non-inverting (+) inputs. The desired output voltage represented by the full N bits of the N-bit words (N represents a positive integer) applied to the modulator input is fed forward to the non-inverting input of the op-amp  514 , via the DAC  512 . A first resistor  516  is coupled between the output of the op-amp  514  and the output of the modulator  50 . A second resistor  518  is coupled between the inverting input of the op-amp  514  and ground. A third resistor  520  is coupled between the inverting input of the op-amp  514  and the modulator output. 
     N-bit digital input words are successively clocked into the DAC  512  in the feed-forward path of the modulator  50  while the upper significant K bits (K&lt;N) of each N-bit word are fed to the input of the PWM generator  500 . Not all N bits of each N-bit word are fed to the PWM generator  500  since cost and size constraints limit the PWM generator  500  to a processing resolution that is less than the full N-bit resolution. Accordingly, only the K most significant bits of each N-bit word are fed to the PWM generator  500 . 
     The PWM generator  500  is capable of varying the voltage of the buck converter in increments of Vsupply/(2 K ). According to an exemplary embodiment, N=14, K=7, Vsupply=26 V and fclk=416 MHz. With these parameters, one-hundred twenty-eight (128) discrete PWM signals can be generated by the PWM generator  500 . Hence, the buck converter portion of the modulator is capable of generating voltages in increments of 26/(2 7 ) V, or approximately 200 mV. Further, with fclk=416 MHz and 128 discrete PWM signal variations, the switching transistor  504  has a switching frequency of 3.25 MHz (Fsw=Fclk/128), which is well within the range of switching frequencies offered by state-of-the-art converters. 
     Because only K of the N total bits of the N-bit words applied to the class-S modulator  50  are used to generate the PWM signals, the output voltage produced for each K-bit word deviates from the full N-bit word value. This error appears as ripple at the out put of the modulator. According to an embodiment of the present invention the feed-forward circuit in  FIG. 5  is employed to reduce the ripple of the modulator output voltage waveform, as will now be described. 
     A class-S modulator operates essentially as a voltage source and its DC output impedance is close to zero ohms. However, its AC output impedance is relatively high for frequencies close to and above the cutoff frequency of its LPF (inductor  508  and capacitor  510 ). The ripple frequency of the error produced at the modulator output falls into this frequency band. To reduce or remove this error, the op-amp  514  in the feed-forward path of the hybrid class-S modulator  50  is engaged to either source or sink current into or out of the modulator output node, whenever the instantaneous voltage at the modulator output is between the discrete voltage levels provided by the digital PWM generator  500 . In other words, while the hybrid class-S modulator is providing the output waveform in Vsupply/(2 K ) increments, the parallel connected op-amp  514  “pushes” or “pulls” the output voltage to voltage levels in between in an interpolative manner. The result is an output waveform having substantially less ripple than the conventional class-S modulator  4  of  FIG. 4 . 
     Whereas a digital PWM has been described as being used in the exemplary hybrid class-S modulator  50  in  FIG. 5 , those of ordinary skill in the art will readily appreciate and understand that a similar feed-forward ripple reducing circuit could be used with an analog PWM. An exemplary hybrid class-S modulator  60  having an analog PWM and feed-forward ripple reducing circuit is shown in  FIG. 6 . Operation with the analog PWM version of the class-S modulator in  FIG. 6  is similar to the digital PWM in  FIG. 5 , except that the op-amp  514  engages whenever the instantaneous modulator output voltage VddRF is less than or greater than the “ideal” analog output voltage, rather than being engaged when the modulator output voltage is between the “ideal” quantized output values generated by the digital PWM in the embodiment shown in  FIG. 5 . 
       FIGS. 7 and 8  illustrate how the feed-forward circuit of the hybrid class-S modulator  50  in  FIG. 5  helps to reduce ripple at the output of the modulator.  FIG. 7  is a voltage v. time graph showing the output voltage waveform  700  of a prior art class-S modulator lacking any feed-forward correction. As can be seen, the output voltage waveform of the conventional class-S modulator has a peak-to-peak ripple of 2.63 V.  FIG. 8  is a voltage v. time graph showing the output voltage waveform  800  of the hybrid class-S modulator shown in  FIG. 5 . Compared to the 2.63 V peak-to-peak ripple of the conventional class-S modulator, the output waveform of the hybrid class-S modulator has a ripple of only 6.05 mV peak-to-peak. This translates to greater than a 50 dB rejection of unwanted ripple. 
     The effect of reducing the ripple in the output waveform can also be seen in the EDGE 20W PSD (power spectral density) performance plots in  FIGS. 9 and 10 .  FIG. 9  shows the power spectral density (PSD) produced by the conventional class-S modulator in  FIG. 4  for an EDGE modulated carrier centered at ˜1.8 GHz. Compliance with the EDGE standard requires that the modulator output power  900  fall under the EDGE 20W PSD specification  902 . Clearly, the specification is violated for frequencies that are more than about 300 kHz away from center frequency. By contrast, as shown in  FIG. 10 , the EDGE PSD plot  1000  for the hybrid class-S modulator in  FIG. 5  completely falls beneath the maximum PSD EDGE specification  1002 . Similar PSD curves are shown for a 7 Mhz span in  FIGS. 11 and 12 . Inspection of these PSD plots reveals that, while the PSD  1100  for the conventional class-S modulator again violates the EDGE specification  1602  for frequencies near the center frequency and frequencies approximately +/−3 MHz from the center frequency, the PSD plot  1200  for the hybrid class-S modulator is in full compliance with the EDGE PSD specification  1202 . 
     The presence of the op-amp  514  in the feed-forward path of the hybrid class-S modulator  50  in  FIG. 5  adds to the overall power consumption of the modulator. However, the additional power consumption is small since the op-amp  514  is connected in parallel with the class-S path. In fact, the op-amp  514  only has to handle a worst case load voltage change of Vsupply/(2 K ). For K=7 (following the example above) and a typical equivalent resistive load of 5 Ω at 20 V, this means that in order to change the output of the modulator from 20.00 to 20.20 V, the maximum amount of current the op-amp  514  must supply is (20.20-20.00)V/5 Ω=40 mA.  FIG. 13  is a current v. time graph showing that the peak current supplied by the op-amp  514  is 650 mA. The peak current is greater than the 40 mA theoretical current due to the op-amp quiescent current and the slight mismatch of the gain between the op-amp  514  the class-S branch.) 
     Although addition of the feed-forward path circuitry in the hybrid class-S modulator  50  in  FIG. 5  results in an increase in power consumption compared to the conventional class-S modulator in  FIG. 4 , the increase in PAE (power added efficiency) gained by the ability to use the class-S modulator for EDGE type signals, instead of a linear modulator, more than makes up for the added feed-forward path power consumption. Indeed, simulations have shown that the PAE for the hybrid class-S modulator  50  in  FIG. 5  can exceed 35%, while a conventional linear modulator approach has a PAE of only about 20%. 
     The ripple reducing effect of the hybrid class-S modulator in  FIG. 5  can be further enhanced by using a two-inductor filter configuration, as illustrated in the hybrid class-S modulator  1400  shown in  FIG. 14 , which represents an alternative embodiment of the present invention. This hybrid class-S modulator  1400  is similar to the hybrid class-S modulator  50  in  FIG. 5 , but includes an additional inductor  1410  coupled between the buck converter LPF and the modulator output. 
       FIG. 15  is a voltage v. time graph showing the output voltage waveform  1500  of a prior art class-S modulator lacking any feed-forward correction, but having a two-inductor buck converter output filter. Inspection of the graph reveals that the output voltage waveform of this two-inductor class-S modulator has a peak-to-peak ripple of 1.67 V. 
       FIG. 16  is a voltage v. time graph showing the output voltage waveform  1600  of the hybrid class-S modulator  1400  shown in  FIG. 14 . Compared to the 1.67 V peak-to-peak ripple of the conventional class-S modulator ( FIG. 15 ), the output waveform  1600  of the hybrid class-S modulator  1400  has a ripple of only 1.0 mV peak-to-peak. This translates to over a 60 dB rejection of unwanted ripple compared to the ˜50 dB rejection for the single-inductor embodiment in  FIG. 5 . 
       FIG. 17  shows the peak current required of the op-amp  514  for the two-inductor hybrid class-S modulator  1400  in  FIG. 14 . Compared to the 650 mA peak current required of the op-amp  514  in the single-inductor hybrid class-S modulator  50  in  FIG. 5 , the peak current supply required of the op-amp  514  in the two-inductor hybrid class-S modulator  1400  is only 128 mA. Hence, in addition to enhanced ripple reduction, the two-inductor hybrid class-S modulator  1400  is characterized by an enhanced PAE. 
     Referring next to  FIG. 18 , there is shown a hybrid class-S modulator  1800 , according to another embodiment of the present invention. Similar to the hybrid class-S modulator  50  in  FIG. 5 , the hybrid class-S modulator  1800  comprises a modulator path and a feed-forward path. The modulator path includes a digital PWM generator  1802 , a digital oscillator  1804 , a level shifter and gate driver  1806 , and a buck converter that includes a switching transistor  1808 , a diode  1810 , an inductor  1812  and a capacitor  1814  having a first terminal coupled to the modulator output and a second terminal. The feed-forward path includes a DAC  1816 , an op-amp  1818 , a first resistor  1820  coupled between the inverting input of the op-amp  1818  and ground, and a second resistor  1824  coupled between the inverting input of the op-amp output and ground. 
     The upper K bits of each N-bit input word (N and K are positive integers and N&gt;K) are coupled to the input of the PWM generator  1802 . This provides the PWM generator  1802  the capability of generating PWM output signals representing 2 K  discrete voltage values. Because K&lt;N, however, an error equal to the difference between the desired N-bit value and the K-bit values is presented to the PWM generator  1802 . 
     According to this embodiment, the error generated by only using K of the N bits of each N-bit word applied to the PWM generator  1802  is reduced by dithering the input drive and converting the error to an AC signal. As shown in  FIG. 18 , the N−K least significant bits (LSBs) of each N-bit input word are fed to the input of the digital oscillator  1804 , while the K most significant bits (MSBs) of each word are fed to the PWM generator  1802 . The N−K bits of each N-bit word represent the error resulting from using only K of the N bits at the PWM generator  1802 . The digital oscillator converts the N−K LSBs of each input word into an oscillating single LSB. This oscillating LSB has a duty cycle, D, where 0&lt;D&lt;1. The DC average of the output of the modulator is then a factor of D between its value for LSB=0 and LSB=1. Accordingly, the error caused by using only K bits of the N-bit input data words is converted essentially into an AC signal. 
     By dithering the input drive, an AC signal representing the error is generated and appears at the output of the modulator. This oscillating error signal is fed to the inverting input of the op-amp  1818 . The desired output voltage, which is represented by the full N bits of the N-bit input words, is coupled to the non-inverting input of the op-amp  1818 . With these signals at the op-amp inputs, the op-amp  1818  sources or sinks current into or out of the modulator output terminal to remove the error attributable to only using K of the N bits at the PWM generator  1802 . Further, because the error has been converted to an AC signal, error correction can be performed by capacitively coupling the op-amp output to the modulator output via capacitor  1814 . 
     The digital oscillator  1804  in the hybrid class-S modulator  1800  may be implemented in various ways.  FIG. 19  show an exemplary direct digital synthesis (DDS) carry-out accumulator  1900 , which can be used to implement the digital oscillator  1804 . The accumulator  1900  comprises an adder  1902  and an M-bit register  1904 , where M is an integer and 2 M  is greater than the maximum possible value of the N−K bit word. 
     During operation, a N−K bit word is applied to a first input (A) of the adder  1902  and its binary value is added to the binary value of the N−K word applied to a second input (B) of the adder  1902 . The sum of these two binary words appears at the output (+S) of the adder  1902 . The sum is clocked into the DATA input of the register  1904  on the next clock cycle of the system clock, fclk, and is also fed back to the second input B of the adder  1902 . The adder  1902  then adds this fed back sum to the N−K bit word at the first input A of the adder  1902 , to provide a new sum at the +S output. This new sum is clocked into the register  1904  on the next clock cycle of fclk, and is again fed back to the second input B of the adder, which adds the new sum to the N−K word at the first input A. The adder  1902  and register  1904  continue to operate in this manner until the cumulative sum exceeds 2 M −1. When this condition occurs, the amount by which the sum exceeds 2 M −1 is presented at the +S output and a logic high carry-out bit is generated, which appears at the CO output of the adder  1902 . The carry-out bit is clocked into the register  1904  on the next clock cycle and is an indication that the accumulator  1900  has overflowed. 
     Following generating the carry-out bit, the adder  1902  adds the amount by which the previous sum exceeded 2 M −1 (i.e., the value of the N−K bit word appearing at the +S output of the adder  1902 ) to the N−K word at the first input A of the adder  1902 . The carry-out bit of the adder  1902  is also reset to a logic low state, and the accumulation process continues until the cumulative sum once again is greater than 2 M −1, at which time the accumulator overflows to produce a logic high carry-out bit once again. 
     It can be shown that the carry-out bit of the accumulator  1900  is generated a rate of the value of (N−K) divided by 2 M . This oscillating bit can be generated for each of the N-bit words appearing a the input of the modulator  1800  in  FIG. 18  to produce an AC error signal, as described above. 
     Although preferred embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and alternations can be made without departing from the spirit and scope of the inventions as defined by the appended claims.