Abstract:
A voltage regulator having an input voltage and adapted to supply a regulated output voltage, the regulator including an AB class amplifier and a power transistor having a non-drivable terminal coupled to the input voltage, a non-drivable terminal coupled to a reference voltage and a drivable terminal coupled to the output terminal of the amplifier; the amplifier is adapted to amplify the voltage difference between a further reference voltage and a fraction of the regulated voltage.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present disclosure pertains to a low-consumption voltage regulator.  
         [0003]     2. Description of the Related Art  
         [0004]     Linear voltage regulators of the ULDO (Ultra Low Drop Out) type are known in the state of the art. ULDO regulators are widely used in portable applications, in motorcars and in medical applications. These applications are fed by batteries that require low stand-by currents to increase the lifespan and the efficiency of the battery.  
         [0005]     The efficiency of the regulator clashes with its time specifications. Indeed, a higher feeding current determines a faster response of the regulator. This is due to the charging and discharging of parasitic capacitances connected to the driving terminal of the power transistors of the voltage regulator, with parasitic capacitances on the order of hundreds of picofarads. Therefore, if the output load is varied, considerable current peaks are required by the voltage regulator to charge and discharge the parasitic capacitances in the shortest possible time.  
         [0006]     A voltage regulator of the ULDO type is described in the article “A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator” by Gabriel A. Rincon-Mora and Philip E. Allen, IEEE Journal of Solid State Circuit, vol. 33, No. 1, January 1998, and is shown in  FIG. 1 . The regulator in  FIG. 1  is a class A error operational amplifier  1  having on the inverting input a reference voltage Vref and on the non-inverting input a fraction Vr of the regulator output voltage Vout with Vr=(R 2 /(R 1 +R 2 ))*Vout. The amplifier is fed by a voltage Vin and its output is connected to a buffer stage  2  comprising an NPN common collector bipolar transistor Q 1 , a MOS transistor mirror M 1 -M 2  connected between the emitter terminal of transistor Q 1  and the drain terminal of a transistor M 3  having the source terminal connected to voltage Vin and the gate terminal connected to the emitter terminal of transistor Q 1  and to the gate terminal of power transistor Mp. The latter has the source terminal connected to voltage Vin and the drain terminal connected to the series of resistors R 1  and R 2  connected to ground. A polarization current generator Ibias is connected to the gate and drain terminals of transistor M 1 .  
         [0007]     Buffer stage  2  allows to release the parasitic capacitance Cpar of the power transistor Mp from the output terminal of error amplifier  1  but introduces in the regulator loop gain a third pole which complicates the compensation of the regulator. By recovering a fraction Iboost of output current Iload a certain stability of the system is guaranteed; in this case, indeed, the pole formed by the introduction of buffer stage  2  may be preferably shifted over the cut-off frequency of the open-loop gain of the regulator. Benefits may also be obtained in the response time of the regulator by appropriately dimensioning current Iboost.  
         [0008]     However, if the current in load Iload has a low value, the corresponding fraction of current Iboost becomes very small and practically null; in such a case, no benefit derives in terms of response in time.  
       BRIEF SUMMARY OF THE INVENTION  
       [0009]     The embodiments disclosed herein provide a low-consumption voltage regulator that overcomes the aforesaid drawback.  
         [0010]     According to one embodiment, a voltage regulator having an input voltage is adapted to supply a regulated output voltage, the regulator including an amplifier and a power transistor having a non-drivable terminal coupled to the input voltage, a non-drivable terminal coupled to a reference voltage, and a drivable terminal coupled to the output terminal of the amplifier, the amplifier adapted to amplify the difference of voltage between a further reference voltage and a fraction of the regulated voltage, wherein the amplifier is an AB class amplifier.  
         [0011]     In accordance with another embodiment, a circuit is provided that includes an AB class operational amplifier having an inverting input, a non-inverting input, an output, and a non-drivable input coupled to an input voltage; a power transistor having a gate terminal coupled to the output terminal of the operational amplifier, a source terminal coupled to the input voltage, and a drain terminal coupled to an output terminal of the regulator; a voltage divider having an input coupled to the drain terminal of the power transistor and an output coupled to the non-inverting input of the AB class amplifier; and the inverting input of the AB class amplifier coupled to a first reference voltage, the AB class amplifier adapted to amplify a voltage difference between the further reference voltage and the output of the voltage divider.  
         [0012]     In accordance with another aspect of the foregoing embodiment, the circuit includes the output of the voltage regulator is coupled to a load. Ideally, the circuit also includes a first amplifier cell and a second amplifier cell, each amplifier cell including a differential pair of transistors having a pair of input terminals connected in phase opposition, and each amplifier cell including an output terminal coupled to a common terminal of the respective differential pair of transistors.  
         [0013]     In accordance with another embodiment of the invention, a power transistor having a source terminal coupled to a voltage input, a drain terminal coupled to an output terminal, and a control terminal; a voltage divider having a first terminal coupled to the source terminal of the power transistor, a second terminal coupled to a ground reference potential, and an output terminal; and an AB class amplifier having an output coupled to the control terminal of the power transistor, a non-drivable terminal coupled to the input voltage, a non-inverting input coupled to the output terminal of the voltage divider, and an inverting input coupled to a reference voltage source, the AB class amplifier including a cascode mirror, a first amplifier cell including a first differential pair, a second amplifier cell including a second differential pair, and each amplifier cell including an output coupled to the cascode mirror and to a drivable terminal of a respective further transistor, the AB class amplifier adapted to amplify a voltage difference between the reference voltage and the output of the voltage divider. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0014]     The features and advantages of the embodiments disclosed herein will be more apparent in the following description of a practical embodiment thereof shown by way of non-limitative example in the accompanying drawings, in which:  
         [0015]      FIG. 1  is a diagram of a voltage regulator according to the known art;  
         [0016]      FIG. 2  is a diagram of a voltage regulator according to the present disclosure;  
         [0017]      FIG. 3  is a diagram of the error amplifier of the regulator in  FIG. 2  according to an embodiment of the present disclosure;  
         [0018]      FIG. 4  shows a voltage and current diagram on the load of the regulator in  FIG. 2  in certain conditions of operation;  
         [0019]      FIGS. 5 and 6  show time diagrams of the voltage output by the regulator in  FIG. 2  in other conditions of operation. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0020]      FIG. 2  shows one embodiment of a voltage regulator  10  according to the present disclosure. The regulator includes an error operational amplifier  100  having the inverting input connected to a reference voltage Vref and output terminal Vg coupled, but preferably directly connected, to the gate terminal of a MOS power transistor M having the source terminal connected to voltage Vin and the drain terminal connected in series to two resistors R 1  and R 2  connected to ground GND. The voltage on the drain terminal of transistor M is the regulator output voltage Vout, while voltage Vfb given by the resistive divider of the two resistors R 1  and R 2 , Vfb=(R 2 /(R 1 +R 2 ))*Vout, is received on the non-inverting input of the amplifier  100 . Voltage Vout is also the voltage at the terminals of a load LOAD in which a current Iload flows. Amplifier  100  is an AB class amplifier, i.e., an amplifier in which there is energy consumption only when input voltages Vref and Vfb are not the same.  
         [0021]     The use of an AB class amplifier renders the use of the voltage buffer superfluous, as in the regulator of  FIG. 1 . Furthermore, the regulator of  FIG. 2  only has two poles, and this enhances frequency compensation to improve stability; furthermore, the circuit configuration of the regulator  10  provides a faster response in time.  
         [0022]     An AB class type amplifier usable in the voltage regulator  10  according to one embodiment is described in  FIG. 3 . The amplifier  100  includes two AB class cells  101  and  102  having input terminals reciprocally connected in phase opposition and the corresponding outputs of which are reciprocally connected by means of a high-dynamic cascode current mirror  103 .  
         [0023]     Cell  101  has a differential pair of MOS transistors M 1 / a , M 2 / a , the drain terminals of which are connected to a simple current mirror M 3 , M 4  adapted to minimize the channel modulation effect of the differential pair M 1 / a , M 2 / a , and the gate terminals of which are respectively connected to voltages Vfb and Vref.  
         [0024]     Cell  102  comprises a differential pair of MOS transistors M 1 / b , M 2 / b , the drain terminals of which are connected to a simple current mirror M 5 , M 6  adapted to minimize the channel modulation effect of the differential pair M 1 / b , M 2 / b , and the gate terminals of which are connected respectively to voltages Vfb and Vref.  
         [0025]     The drain terminals of the transistors M 3 , M 4  and M 5 , M 6  of cells  101  and  102  are connected to the input voltage Vin, while the source terminals of the transistors M 1 / a , M 2 / a  and M 1 / b , M 2 / b  are connected to the drain terminals of the transistors M 14  and M 13  belonging to a circuit structure  104  adapted to supply the outputs of differential pairs M 1 / a , M 2 / a  and M 1 / b , M 2 / b  to cascode current mirror  103 .  
         [0026]     The circuit structure  104  includes a first circuit part formed by transistors M 14 -M 16  and adapted to supply the output of differential stage M 1 / a , M 2 / a  to a current mirror  103  and a second circuit part formed by transistors M 11 -M 13  and adapted to supply the output of differential stage M 1 / b , M 2 / b  to the same current mirror  103 . In the first circuit part, the transistor M 16  has a gate terminal in common with the gate terminal of transistor M 14 , and with the drain terminal of transistor M 1 / a  and has the drain terminal connected to the source terminal of transistor M 15 . The latter has the drain terminal connected to the cascode mirror  103  and the gate terminal connected to a polarization voltage Vb 2 , with for example Vb 2 =1V; the source terminals of transistors M 14  and M 16  are connected to ground GND. In the second circuit part, transistor M 12  has the gate terminal in common with the gate terminal of transistor M 13  and with the drain terminal of transistor M 2 / b , and it has the drain terminal connected to the source terminal of transistor M 11 . The latter has the drain terminal connected to the cascode mirror  103  and the gate terminal connected to a polarization voltage Vb 2 ; the source terminals of transistors M 13  and M 12  are connected to ground GND.  
         [0027]     The current mirror  103  is formed by transistors M 7 -M 10 , and the gate terminals of transistors M 10  and M 8  are connected to a polarization voltage Vb 1 , with for example Vb 1 =Vin−1V. The current mirror  103  is connected to the voltage Vin, as are mirrors M 3 , M 4  and M 5 , M 6 . Current Ib is a polarization current.  
         [0028]     The output voltage Vg at cascode mirror  103  is the driving voltage of the gate terminal of transistor M of the regulator in  FIG. 2 .  
         [0029]     The cells  101  and  102  have an AB class operation when the voltage Vfb is different from voltage Vref and in virtue of the negative feedback loops obtained by means of the electrical connection of the drain terminal of transistor M 1 / a  to the gate terminal of transistor M 14  and with the electrical connection of the drain terminal of transistor M 2 / b  to the gate terminal of transistor M 13 .  
         [0030]      FIG. 4  shows a time diagram of the current Iload on the load and a time diagram of output voltage Vout of the regulator in  FIG. 2  (with the use as amplifier  100  of the amplifier in  FIG. 3 ) when the current Iload on the load is varied from a value of 1 mA to a value of 150 mA and vice versa in a period of time of a few microseconds. The variation is detected by the regulator which will attempt to take output voltage Vout to its nominal value in the shortest possible time; the response time is calculated as the time needed by the regulator to return imbalanced voltage Vout to its nominal value.  
         [0031]     In the diagram in  FIG. 4 , the regulator in accordance with the invention is fed with a voltage Vin=2.8 Volt and by programming a nominal voltage of Vout of 1.8 Volt; a time response of 0.4 ms (4 microseconds) is obtained.  
         [0032]      FIG. 5  shows a time diagram of output voltage Vout of the regulator in  FIG. 2  with the use as amplifier  100  of the amplifier in  FIG. 3  (when current Iload on the load is varied from a value of 1 mA to a value of 150 mA and vice versa in a period of time of a few microseconds), with a different voltage value Vin, Vin=2.0 Volt. The regulator is in drop conditions, i.e., the condition in which the regulator can still regulate the input voltage Vin; normally the drop value is fixed with Vin=Vout+0.2V.  
         [0033]      FIG. 6  shows the time chart of output voltage Vout of the regulator in  FIG. 2 , using as amplifier  100  the amplifier in  FIG. 3 , when voltage Vin is varied from an initial value of 2.3 V to a value of 3.1 V and vice versa in a period of time of one microsecond with a load current Iload=1 mA. The variation is detected by the regulator which will attempt to take the output voltage Vout to its nominal value in the shortest possible time; the response time is calculated as the time needed by the regulator to return unbalanced voltage Vout to its nominal value.  
         [0034]     All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.  
         [0035]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.