Abstract:
A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to comparator circuits. More particularly, this invention relates to a circuit and a method for differential comparators with hysteresis.  
         [0003]     2. Description of the Prior Art  
         [0004]      FIG. 1  shows a prior art comparator circuit without hysteresis. It is a simple operational amplifier (op amp). The figure shows a differential comparator circuit. Devices  110  and  120  are p-channel metal oxide semiconductor field effect transistors (PMOS FETs). They are load devices with their sources and substrates connected to the power supply node  111 . The gates of devices  110  and  120  are connected in common to the rain  114  of device  120 . The drain  118  of device  110  drives inverter  180 . The output of inverter  180  is node Out  0 B ( 117 ). The output of inverter  180  feeds inverter  190 , whose output is Out 0  ( 116 ). N-channel metal oxide semiconductor field effect transistors (NMOSFETs)  130  and  140  are the logic devices for the differential amplifier. The gate of device  130  is connected to a reference voltage, VREF,  150 . The drain of device  130  is connected to node  118 . The gate of device  140  is connected to an input voltage, VIN  160 . The drain of device  140  is connected to node  114 . The sources of devices  130  and  140  are connected in common to the drain  113  of NMOS FET device  115 . Device  115  is a current source whose current is specified by its device size and gate voltage, MNVT  170 . The source of device  115  is connected to ground  112 .  
         [0005]      FIG. 1   b  shows a transfer function plot  122  with VIN vs. OUT 0 . Increasing VIN from zero, the output of the differential Op amp remains zero until VIN approaches VREF 121 . As VIN approaches VREF, Out 0  begins to increase from zero. Out 0  continues to increase until VIN is slightly above VREF. Then, Out 0  stops increasing and remains constant at a HIGH level.  
         [0006]     Similarly, in  FIG. 1   b  as VIN decreases from some voltage level above VREF, Out 0  remains at a constant HIGH level. As VIN decreases and approaches VREF, Out 0  decreases. Out 0  decreases to zero as VIN decreases to a voltage value just below VREF. Then, as VIN decreases toward zero, Out 0  remains constant at zero volts as shown in  FIG. 1   b . As we see from this description, the comparator circuit of  FIG. 1   a  does not have hysteresis.  
         [0007]     A problem with comparator circuits, which do not have hysteresis, is that they are poor for measuring temperatures or other quantities, which have alternating fluctuation.  
         [0008]     U.S. Pat. No. 6,459,306 B1 (Fischer et al.) describes a low power differential comparator with stable hysteresis. The input stage bias is used for both setting a bias level and for setting the hysteresis level of the differential comparator circuit. This multiple use of the input stage bias helps to reduce the overall current and power requirements while maintaining full operating speed.  
         [0009]     U.S. Pat. No. 6,366,136 B1 (Page) discloses a voltage comparator with hysteresis that includes a differential amplifier, voltage divider circuits and a current mirror. The input terminals of the two differential amplifier circuit branches are biased at unequal potentials by the voltage divider circuits. The output of the current mirror circuit can be implemented to include multiple branches which are selectively connectable. This allows the user to selectively vary the amount of hysteresis as a function of the differences in the input signal voltage necessary to cause the conducting differential amplifier circuit branches to alternate.  
         [0010]     U.S. Pat. No. 6,362,467 B1 (Bray) describes a fast-switching comparator with hysteresis. Fast switching is achieved in the comparator by driving the comparator stage with a gain amplifier and feeding back the output signal from the comparator to the gain amplifier.  
       SUMMARY OF THE INVENTION  
       [0011]     It is therefore an object of the present invention to provide a circuit and a method for providing a circuit and a method for differential comparators with hysteresis.  
         [0012]     The objects of this invention are achieved by a differential comparator circuit with hysteresis. This circuit contains a current source which controls the magnitude of current flow through this comparator circuit. The circuit also has a first logic device which is turned ON by a reference voltage, and which when ON feeds current to the current source. A second logic device is turned ON by a comparator input voltage, and which when ON allows current to flow to the current source. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. A first load device is connected to the first feedback device. A second load device is connected to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.  
         [0013]     The above and other objects, features and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1   a  is a prior art differential comparator circuit without hysteresis.  
         [0015]      FIG. 1   b  shows a prior art input vs. output transfer graph for the circuit of  FIG. 1   a.    
         [0016]      FIG. 2   a  shows a differential comparator circuit with hysteresis, which represents a first embodiment of this invention.  
         [0017]      FIG. 2   b  shows an input vs. output transfer graph for the circuit of  FIG. 2   a.    
         [0018]      FIG. 2   c  shows a differential comparator circuit with hysteresis, which represents a second embodiment of this invention.  
         [0019]      FIG. 2   d  shows an input vs. output transfer graph for the circuit of  FIG. 2   c.    
         [0020]      FIG. 3  shows a state diagram which illustrates the operation of the comparator circuit of this invention.  
         [0021]      FIG. 4  shows the hysteresis results of a computer simulation of the circuit shown in  FIG. 2   a.    
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0022]      FIG. 2   a  shows the main embodiment of the comparator circuit of this invention. It is a differential comparator with hysteresis. Devices  210  and  220  are p-channel metal oxide semi-conductor field effect transistors (PMOS FETs). They are load devices with their sources and substrates connected to the power supply mode  211 . The gates of devices  210  and  220  are connected in common to the drain  214  of device  220 . The drain  218  of device  210  drives inverter  280 . The output of inverter  280  is node OUT  1 B ( 217 ). The output of inverter  280  feeds inverter  290 , whose output is OUT 1  ( 216 ). N-channel metal oxide semi conductor field effect transistors (NMOS FETs)  230  and  240  are the logic devices for the differential amplifier. The gate of device  230  is connected to a reference voltage, VREF,  250 . The drain of device  230  is connected to node  251 . The gate of  240  is connected to an input voltage, VIN  260 . The drain of device  240  is connected to node  261 . The sources of devices  230  and  240  are connected in common to the drain  213  of NMOS FET device  215 . Device  215  is a current source whose current is specified by its device size and its gate voltage, MNVT  270 . The source of device  215  is connected to ground  212 .  
         [0023]     In  FIG. 2   a , NMOS FET device  231  has its drain connected to one side of 10K, resistor  232  at node  213 . Device  231  has its source connected to the other side of 10K resistor  232  at node  251 . The gate of device  231  is connected to node  217 , which is the OUT  1 B signal. NMOS FET device  241  has its drain connected to one side of 10K resistor  242  at node  214 . Device  241  has its source connected to the other side of 10K resistor  242  at node  261 . The gate of device  241  is connected to node  216 , which is the OUT 1  signal.  
         [0024]      FIG. 2   b  shows transfer function plot  222  with VIN vs. OUT 1 . Increasing VIN from zero, the output of the differential op any remains zero until VIN approaches VREF+dV ( 224 ). As VIN approaches VREF+dV ( 224 ), OUT 1  begins to increase from zero. OUT 1  continues to increase until VIN is slightly above VREF+dV ( 224 ). Then, OUT 1  stops increasing and remains constant at a HIGH level.  
         [0025]     Similarly, in  FIG. 2   b , as VIN decreases from some voltage level above VREF, OUT 1  remains at a constant HIGH level. As VIN decreases and approaches VREF−dV ( 223 ), OUT 1  decreases. OUT 1  decreases to zero as VIN decreases to a voltage value just below VREF−dv ( 223 ). Then, as VIN decreases toward zero, OUT 1  remains constant at zero volts as shown in  FIG. 2   b . This behavior shown in  FIG. 2   b  demonstrates hysteresis.  
         [0026]     The circuitry of  FIG. 2   a  produces hysteresis. Initially, devices  230  and  231  are ON, causing node  213  to be LOW. Consequently, node OUT  1 B would be HIGH at the output of inverter  280 . Initially, node OUT 1  ( 216 ) would be LOW as shown in the transfer graph in  FIG. 2   b . As seen in  FIG. 2   a , as VIN  260  increases toward VREF+dV, device  240  turns ON more fully. When VIN equals VREF+dV, the op amp comparator switches causing node  213  to go HIGH, OUT  1 B ( 217 ) to go LOW and OUT 1  ( 216 ) to go HIGH  225  as shown in the transfer plot  222  of  FIG. 2   b . Since OUT 1  is HIGH, device  241  turns ON. When this happens, current is diverted from resistor  242 . When VIN decreases, node OUT 1  remains HIGH and OUT  1 B remains LOW. Since OUT  1 B is LOW, device  231  remains OFF, and current flows through resistor  232 . The voltage drop across a resistor  232  is dV. When the voltage on VIN approaches VREF−dV, the comparator begins to switch again. When VIN equals VREF−dV, the comparator switches causing node  213  to go LOW, OUT  1 B ( 217 ) to go HIGH, and OUT 1  ( 216 ) to go LOW  226  as shown in the transfer graph  222  of  FIG. 2   b . Since OUT 1  is LOW, device  241  turns OFF. This allows current flow through parallel resistor  242 .  
         [0027]      FIG. 2   c  shows a second embodiment of the comparator circuit of this invention. It is a differential comparator with hysteresis. Devices  510  and  520  are p-channel metal oxide semi-conductor field effect transistors (PMOS FETs). They are load devices with their sources and substrates connected to the power supply mode  511 . The gates of devices  510  and  520  are connected in common to the drain  514  of device  520 . The drain  518  of device  510  drives inverter  580 . The output of inverter  580  is node OUT  1 B ( 517 ). The output of inverter  580  feeds inverter  590 , whose output is OUT 1  ( 516 ). N-channel metal oxide semi conductor field effect transistors (NMOS FETs)  530  and  540  are the logic devices for the differential amplifier. The gate of device  530  is connected to a reference voltage, VREF,  550 . The drain of device  530  is connected to node  518 . The gate of  540  is connected to an input voltage, VIN  560 . The drain of device  540  is connected to node  514 . The source of device  530  is connected to the drain of device  531 . The source of device  540  is connected to the drain of device  541 . Device  515  is a current source whose current is specified by its device size and its gate voltage  570 . The source of device  515  is connected to ground  512 .  
         [0028]     In  FIG. 2   c , NMOS FET device  531  has its drain connected to the source of device  530 . Device  531  has its source connected to the drain of device  515  at node  513 . The gate of device  531  is connected to node  517 , which is the OUT  1 B signal. NMOS FET device  541  has its drain connected to the source of device  540 . Device  541  has its source connected to the drain of device  515  at node  513 . The gate of device  541  is connected to node  516 , which is the OUT 1  signal.  
         [0029]      FIG. 2   d  shows transfer function plot  522  with VIN vs. OUT 1 . Increasing VIN from zero, the output of the differential op any remains zero until VIN approaches VREF+dV ( 524 ). As VIN approaches VREF+dV ( 524 ), OUT 1  begins to increase from zero. OUT 1  continues to increase until VIN is slightly above VREF+dV ( 524 ). Then, OUT 1  stops increasing and remains constant at a HIGH level.  
         [0030]     Similarly, in  FIG. 2   d , as VIN decreases from some voltage level above VREF, OUT 1  remains at a constant HIGH level. As VIN decreases and approaches VREF−dV ( 523 ), OUT 1  decreases. OUT 1  decreases to zero as VIN decreases to a voltage value just below VREF−dv ( 523 ). Then, as VIN decreases toward zero, OUT 1  remains constant at zero volts as shown in  FIG. 2   d . This behavior shown in  FIG. 2   d  demonstrates hysteresis.  
         [0031]     The circuitry of  FIG. 2   c  produces hysteresis. Initially, devices  530  and  531  are ON, causing node  518  to be LOW. Consequently, node OUT  1 B would be HIGH at the output of inverter  580 . Initially, node OUT 1  ( 516 ) would be LOW as shown in the transfer graph in  FIG. 2   d . As seen in  FIG. 2   c , as VIN  560  increases toward VREF+dV, device  540  turns ON more fully. When VIN equals VREF+dV, the op amp comparator switches causing node  518  to go HIGH, OUT  1 B ( 517 ) to go LOW and OUT 1  ( 516 ) to go HIGH  525  as shown in the transfer plot  522  of  FIG. 2   d . Since OUT 1  is HIGH, device  541  turns ON. When this happens, current is diverted from device  540 . When VIN decreases, node OUT 1  remains HIGH and OUT  1 B remains LOW. Since OUT  1 B is LOW, device  531  remains OFF, and current cannot flow through device  530 . This allows current flow through parallel device  532 . This is similar to the current diversion through resistor  232  in  FIG. 2   a . The voltage drop across parallel device  532  is dV. When the voltage on VIN approaches VREF−dV, the comparator begins to switch again. When VIN equals VREF−dV, the comparator switches causing node  518  to go LOW, OUT  1 B ( 517 ) to go HIGH, and OUT 1  ( 516 ) to go LOW  526  as shown in the transfer graph  522  of  FIG. 2   d . Since OUT 1  is LOW, device  541  turns OFF, and current cannot flow through device  540 . This allows current flow through parallel device  542 . This is similar to the current diversion through resistor  242  in  FIG. 2   a.    
         [0032]      FIG. 3  shows a state diagram which illustrates the Schmitt trigger hysteresis character of this embodiment of the invention. In state  310 , the trigger level is VREF+dV. When VIN=VREF+dV, there is a state transistion from state  310  to state  320 , and OUT 1  makes a transition from LOW to HIGH  330 . In state  320 , the trigger level is VREF−dV. When VIN=VREF−dV, there is a state transistion from state  320  to state  310 , and OUT 1  makes a transition from HIGH to LOW  340 .  
         [0033]      FIG. 4  shows the results of a computer simulation of a model of the circuit of  FIG. 2   a . Lines  410  and  420  illustrate the same VIN vs. OUT 1  graph behavior shown in  FIG. 2   b . Line  410  is the same OUT 1  transistion from LOW to HIGH illustrated by the  330  state transistion in  FIG. 3 . Line  420  is the same OUT 1  transistion from HIGH to LOW illustrated by the  340  state transistion in  FIG. 3 .  FIG. 4  also shows on the same axes, a plot of VIN  430  vs. VREF. When, VIN=VREF plus dV, the OUT 1  graph switches from LOW to HIGH. When, VIN=VREF minus dV, the OUT 1  graph switches from HIGH to LOW.  
         [0034]     The advantage of the first embodiment of this invention is the simple and unique addition of the first and second parallel resistors  232 ,  242  which are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character. A typical value for these resistors is 10 kilo ohms. The value of these two parallel resistors can be varied to produce a wider or narrower hysteresis loop. Typically, wider loops are necessary if there are large magnitude swings or instabilities in quantities such as temperature being measured by comparator circuitry. On the other hand, narrower loops are used if there are smaller magnitude variations or instabilities in quantities such as temperature being measured by the comparator circuitry. The second embodiment of this invention replaces parallel resistors  232  and  242  with parallel devices  532  and  542 . These devices provide a flexible alternate way of providing switching voltage offsets.  
         [0035]     While the invention has been described in terms of the preferred embodiments, those skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the invention.