Abstract:
A camera including a mount substrate, a detector on a first surface of the mount substrate, a spacer on the mount substrate, the spacer including a hole exposing the detector, a cover on the spacer, the cover covering the hole, the mount substrate, the spacer and the cover together sealing the detector, the cover having a planar surface facing the detector, and an external electrical interconnection for the detector provided outside the sealing, the external electrical interconnection being on a first surface and a second surface, different from the first surface, of the mount substrate, the external electrical interconnection adapted to connect the detector to an electrical contact pad.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This is a continuation-in-part application based on pending application Ser. No. 11/783,530, filed on Apr. 10, 2007, which in turn claims priority under 35 U.S.C. §120 as a continuation to Ser. No. 10/809,914, filed Mar. 26, 2004, now U.S. Pat. No. 7,224,856, which in turn claims priority under 35 U.S.C. §119 to U.S. Provisional Application Ser. No. 60/457,664 filed on Mar. 26, 2003, entitled “Wafer Based Optical Chassis” and under 35 U.S.C. §120 as a continuation-in-part to U.S. Application Ser. No. 09/983,278 filed Oct. 23, 2001, now U.S. Pat. No. 6,798,931 B2, entitled “Separating of Optical Integrated Modules and Structures Formed Thereby,” the entire contents of all of which are hereby incorporated by reference for all purposes. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     The present invention is directed to a wafer based optical chassis and associated methods. More particularly, the present invention is directed to protecting active elements in an optical system and realizing electrical input/output without requiring separate packaging. 
     2. Description of Related Art 
     Active elements, such as optoelectronic chips, e.g., light sources for transmitters and detectors for receivers, are typically housed in a transistor outline (TO) can. Such a TO can is typically made of metal, has a large form factor, involves an expensive serial manufacturing process and requires active alignment with external passive optical elements. This large form factor separates the active element from an external passive optic along the optical axis, resulting in the passive optic needing to handle a more divergent beam, rendering the optic bigger, thereby further increasing the size of the system. Additionally, the TO can has electrical termination concerns, limiting the speed of the active elements. 
     Current trends towards miniaturization have spurred numerous small form factor designs. Most of these designs are directed to integrating the passive optical element with some connector, separate from the TO can. While this may reduce the length of the system and simplify the manufacturing of the passive optical portion of the system, the TO can, and the problems attendant therewith, are still present. 
     SUMMARY OF THE INVENTION 
     The present invention is therefore directed to a optical chassis, camera having the same, and associated methods that substantially overcome one or more of the problems due to the limitations and disadvantages of the related art. 
     It is a feature of the present invention to protect an active element with an assembly including passive optical elements. 
     It is another feature of the present invention to provide efficient electrical coupling to and from the protected active elements. 
     It is yet another feature of the present invention to provide packaging of an active element that can at least partially be created in parallel. 
     It is yet another feature of the present invention to provide alignment that compensates for variations arising in the manufacturing process. 
     At least one of the above and other features may be realized by providing a camera, including a mount substrate, a detector on a first surface of the mount substrate, a spacer on the mount substrate, the spacer including a hole exposing the detector, a cover on the spacer, the cover covering the hole, the mount substrate, the spacer and the cover together sealing the detector, the cover having a planar surface facing the detector, and an external electrical interconnection for the detector provided outside the sealing, the external electrical interconnection being on a first surface and a second surface, different from the first surface, of the mount substrate, the external electrical interconnection adapted to connect the detector to an electrical contact pad. 
     The camera may include a passive optical element on a surface of the cover opposite the planar surface. 
     The camera may include a via extending through a bottom surface of the mount substrate, the electrical interconnection going through the via and connecting the detector on the first surface of the mount substrate to the electrical contact pad on a bottom surface of the mount substrate. The mount substrate may be a detector chip and an active area of the detector chip may be integrated in the first surface of the mount substrate. 
     The first surface may or may not be parallel with the second surface. The camera may include an optical element on a substrate, substantially planar regions of the substrate being secured to the cover. 
     The camera may include an upper substrate, a lower substrate, and a spacer between the upper and lower substrates, wherein a substantially planar region of the lower substrate, on a surface of the lower substrate opposite the second spacer, being secured to the cover. The camera may include an optical element on at least one of the upper and lower substrates. The optical element may be on a surface adjacent the spacer. The spacer may be an adhesive, e.g., a punched adhesive. The spacer may include an aperture. 
     At least one of the above and other features may be realized by providing a camera, including an upper substrate, a middle substrate, a first spacer between the upper and middle substrates, the middle and upper substrates and the first spacer defining a first interior space, a lower substrate, a second spacer between the middle and lower substrates, the middle and lower substrates and the second spacer defining a second interior space, a first optical element on the upper substrate, a second optical element on the lower substrate, at least one of the first and second optical elements being in the first interior space, a detector on the lower substrate in the second interior space, and an electrical contact coupled to the detector on the lower substrate outside the second interior space. 
     The first and second spacers may be an adhesive, e.g., a punched adhesive. 
     At least one of the above and other features may be realized by providing a method of making a camera, including providing an upper substrate, providing a middle substrate, providing a first spacer between the upper and middle substrates, the middle and upper substrates and the first spacer defining a first interior space, providing a lower substrate, providing a second spacer between the middle and lower substrates, the middle and lower substrates and the second spacer defining a second interior space, providing a first optical element on the upper substrate, providing a second optical element on the lower substrate, at least one of the first and second optical elements being in the first interior space, providing a detector on the lower substrate in the second interior space, and providing an electrical contact coupled to the detector on the lower substrate outside the second interior space. 
     At least three of the upper substrate, the first spacer, the middle substrate, the second spacer and the lower substrate may be provided on a wafer level. 
     At least one of providing the first and second spacers may include simultaneously providing an adhesive. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages of the present invention will become readily apparent to those of skill in the art by describing in detail embodiments thereof with reference to the attached drawings, in which: 
         FIG. 1  illustrates an elevational perspective view of an embodiment of the optical chassis; 
         FIG. 2  illustrates a detailed elevational perspective view of the optoelectronic devices and electrical interconnections of the optical chassis of  FIG. 1 ; 
         FIG. 3  illustrates an elevational perspective exploded view of the wafer components to be used to create the optical chassis of  FIG. 1 ; 
         FIG. 4  illustrates an elevational perspective view of the passive optical element wafers of  FIG. 3  secured together; 
         FIG. 5  illustrates an elevational perspective view of the active element wafer to be bonded to the stack of wafers in  FIG. 4  and then vertically separated to form the optical chassis of  FIG. 1 ; 
         FIG. 6  illustrates an elevational perspective view of another embodiment of the optical chassis; 
         FIG. 7  illustrates a detailed perspective bottom view of the electrical interconnections of the optical chassis shown in  FIG. 6 ; 
         FIGS. 8   a - 8   d  illustrates schematic drawings of creation and use of an electrical connection on the face of a substrate; 
         FIG. 9  illustrates a schematic side view of another embodiment of electrical connections for the optical chassis; 
         FIG. 10  illustrates a schematic side view of the optical chassis with a larger optical element bonded thereto: 
         FIG. 11  illustrates a schematic side view of the optical chassis in a common housing with a larger optical element; 
         FIG. 12A  illustrates a schematic cross-section of a specific configuration of the optical chassis of the present invention inserted in a system; 
         FIG. 12B  illustrates a schematic cross-section of the specific configuration of the optical chassis of  FIG. 12A  alone; 
         FIG. 13A  illustrates a schematic top view of alignment of the active optical element to the mirror; 
         FIG. 13B  is a schematic side view of alignment of the active optical element to the mirror; 
         FIG. 14A  illustrates a schematic top view of alignment of the active optical element to the optics block; 
         FIG. 14B  illustrates a schematic bottom view of alignment features of the optics block; 
         FIG. 15  illustrates an elevational perspective view of another embodiment of the optical chassis; and 
         FIG. 16  illustrates a cross-sectional perspective view of an optics stack for use with an optical chassis. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it may be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it may be directly under, or one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present. Like numbers refer to like elements throughout. 
     As used herein, the term “wafer” is to mean any substrate on which a plurality of components are formed on a planar surface which are to be separated through the planar surface prior to final use. Further, as used herein, the term “camera” is to mean any system including an optical imaging system relaying optical signals to a detector system, e.g. an image capture system, which outputs information, e.g., an image. 
       FIG. 1  shows an embodiment of an optical chassis  5  of the present invention having four substrates. These four substrates include a mount substrate  10 , a spacer substrate  20 , a sealer substrate  30  and an optional optics substrate  40 . The mount substrate  10  serves as a mount for optoelectronic devices, here a light source  12  and a power monitor  14 , and provides the electrical interconnections, here including a wire bond  16 , conductive patterns  17  and metalized trenches  18 . The conductive patterns  17  each include a pad for the wire bond  16  and connect the pad to the trench  18  for external communication. The conductive patterns  17  may be created by patterning conductive material on the mount substrate  10  in a known manner. The trenches  18  may be created by removing a portion of the mount substrate  10  in a conventional manner and filling this portion with conductive material. The conductive material for the trenches  18  may be provided at the same time the conductive patterns  17  are formed. The details of the mount substrate  10  can be seen more clearly in  FIG. 2 . 
     The spacer substrate  20  provides room for the beam output from the light source  12  to expand. If the optoelectronic device  12  does not have its active area on its top face, e.g., an edge emitting laser, an appropriate portion of a sidewall  22  of the spacer substrate  20  may be angled and coated with a reflective coating to appropriately direct the beam in the optical chassis  5 . A hole  24  in the spacer wafer  20  may be formed by etching a silicon wafer, producing the characteristic angled sidewall  22  from such an etch. The spacer substrate  20 , in conjunction with the sealer substrate  30 , hermetically seals and protects the optoelectronic devices  12 ,  14  from the environment. The sealer substrate  30  may also include an optical element on either surface thereof, e.g., an optical element which reduces the divergence of the beam output from the light source  12 . 
     The optional optics substrate  40  includes at least one optical element. Here, a diffractive optical element  44  on a first surface of the optics substrate  40  directs some of the light from the light source  12  to the power monitor  14 , as disclosed, for example, in commonly assigned U.S. Pat. No. 6,314,223 entitled “Diffractive Vertical Cavity Surface Emitting Laser Power Monitor and System.” A coupling element  42  on a second surface of the optics substrate  40  may couple the light between the optoelectronic device, here the light source  12 , and further applications, e.g., a fiber. Of course, more than one functionality may be incorporated into each optical element. 
     If an optical element is to be provided on one or both of the surfaces of the optional optical substrate  40  or the sealer substrate  30  adjacent to one another, a separation feature  32 , e.g., an indentation or stand off, may be provided on either the sealer substrate  30  or the optional optics substrate  40  to insure proper functioning of the optical element. The sealer substrate  30  is transparent. The sealer substrate  30  may be glass or may be some other transparent material that closely matches the coefficient of thermal expansion of the spacer substrate  20 , e.g., Pyrex when the spacer substrate is silicon. The smaller size of the chassis  5 , e.g., roughly 2 mm by 2 mm in x and y, also helps with any thermal mismatch, since there is not a lot of strain placed in the securing joints between the substrates. 
     Finally, when the optical chassis  5  is to be joined with another device, mating features may be provided on a terminal surface thereof. For example, if the optical chassis is to be mated with a fiber optic ferule, a standoff  43  encircling the optical element  42  may be provided. The standoff  43  may be SU-8 and provides both alignment of the optical chassis  5  with additional devices and provides separation of the optical element  42 . 
     As can be seen from the profile of the optical chassis  5 , a plurality of each of these substrates may be created on a wafer level, secured together with other substrates in a vertical stack, and then vertically separated to form a plurality of individual optical chassis  5 . As shown in  FIG. 3 , a mount wafer  10 ′, a spacer wafer  20 ′, a sealer wafer  30 ′ and an optional optics wafer  40 ′ are to be aligned and secured together on a wafer level. Each of these wafers includes a plurality of the respective mount substrates  10 , spacer substrates  20 , sealer substrates  30  and optional optical substrates  40 . The top three wafers  40 ′,  30 ′ and  20 ′ may be created completely on a wafer level in known fashions. These wafers may then be secured together as shown in  FIG. 4  forming a secured stack wafer  50 ′. These wafers may be aligned and secured as set forth, for example, in U.S. Pat. No. 6,096,155 entitled “Method of Dicing Wafer Level Integrated Optical Elements.” 
     For the mount wafer  10 ′, a plurality of metalized trenches  18  for providing the electrical interconnections may be formed on the wafer level. The optoelectronic elements  12 ,  14  may then be positioned on the mount wafer  10 ′, e.g., using pick-and-place techniques, and then wire bonded  16  to the metalized trenches  18 . The metalized trenches  18  may extend along the mount wafer  10 ′, so the separation of the mount wafer  10 ′ will expose the metal on the edge of the mount substrate, as can be seen in  FIGS. 1 and 2 . The secured stack wafer  50 ′ is then secured to the mount wafer  10 ′ and then vertically separated to form a plurality of optical chassis  5  as shown in  FIG. 1 . Alternatively, the secured stack wafer may be vertically separated to form secured stack substrates, which are then bonded to the mount wafer  10 ′. 
     An alternative optical chassis  55  is shown in  FIGS. 6 and 7 . Here, the optional optical substrate  40  is not included. Only a diffractive optical element  34  for power monitoring and/or efficient coupling is provided on the sealer substrate  30 . The spacer substrate  20  is the same as in  FIG. 1 . The mount substrate  60  provides different electrical connections as in  FIG. 1  for the light source  12  and the power monitor  14 . Here, the optoelectronic devices are again wire bonded, here to conductive pads  65 . Then, on the bottom of the mount substrate  60 , conductive, e.g., metalized, through holes or vias  64  and conductive structures  62 , e.g., solder balls, are used to provide the electrical interconnections to the electrooptical elements on the top surface of the mount substrate  60 . These conductive structures may be large enough to obscure the hole in the mount substrate to insure the seal, to avoid creating a thermal gradient and to avoid extra oxidation. This solution may be particularly useful if the mount substrate is a ceramic, since it is expensive to put solder on ceramic. The seal may be hermetic. 
     Another alternative for providing electrical interconnections to the optoelectronic element on a wafer level is shown in  FIGS. 8A-8D . As shown in  FIG. 8A , a saw or other etching device is used to produce V-shaped groove  81  in a wafer  80 . Then, the groove  81  and the wafer  80  are coated with an electrically conductive coating  82 , e.g., metal, as shown in  FIG. 8B . Then, the wafer  80  is separated at the V-groove  81  and at another portion to form a mount substrate  83 , as shown in  FIG. 8C . The groove  81  needs to be wide enough so that an angle remains after separation. For example, if dicing is used as the separation technique, the groove will need to be wider than the blade width of the dicing saw. 
     As shown in  FIG. 8D , an optoelectronic device  86  is mounted on the conductive coating  82  of the mount substrate  83 . A solder ball  84  or other conductive structure may then used to connect the conductive coating  82  to an electrical connection on a board  88 . The other substrates  20 ,  30  and optionally  40  may be stacked over the mount substrate  83  as shown in the other configurations. 
     Electrical input/output may also be realized as shown in  FIG. 9 , in which the substrates forming the optical chassis do not have the same width, thereby forming a ledge  15 , with the electrical connection being realized on a portion of the chassis  5  providing the ledge  15 . As shown in  FIG. 9 , the ledge  15  may be formed by having the mount substrate  10  extend further in at least one direction than the adjacent spacer substrate  20 . The electrical contacts may be formed on the surface of the ledge or a portion of the ledge  15  may be removed to form the trenches  18  therein to increase the surface for electrical contact. 
     Such a ledge may be formed by die bonding a secured stacked substrate having the spacer substrate  20  and the sealer substrate  30  to the mount substrate  10 . Forming such a ledge on wafer level may be realized in a number of manners, including using dicing saws of different thicknesses and dicing through opposite surfaces, e.g., flipping the wafer after partial dicing, of the secured stacked wafer, including the mount wafer  10 ′. Details of forming such a ledge on a wafer level are set forth in the commonly assigned, co-pending application entitled “Separating of Optical Integrated Modules and Structures Formed Thereby,” filed Oct. 23, 2001, which is hereby incorporated by reference in its entirety. 
     If customized performance of the optical chassis is known, optional optical substrate(s) may be incorporated to provide the desired performance. Otherwise, the optical chassis of the present invention may be used to simply replace the conventional TO-can element and can have the conventional optics aligned thereto, as is currently done for the TO-can optoelectronics. Two manners of achieving this are shown in shown in  FIGS. 10 and 11 . As shown in  FIG. 10 , the vertically integrated optical chassis  55  of the present invention may have an optical element  90 , including optical elements larger in the x- and/or y-direction than the optical chassis  55 , die-bonded thereto. As shown in  FIG. 11 , the optical element  90  may be separate from but aligned with the optical chassis  55 , here shown in a common housing  92 . This separation reduces the alignment tolerances for the optical element  90 . The sealer substrate  30  may still include optics thereon for improving the light from the light source  12 , e.g., collimating or at least reducing the divergence of the light. 
     A specific configuration of an optical chassis in accordance with the present invention is shown in  FIGS. 12A-12B . As can be seen therein, an optical chassis  100  is attached to a flex lead  150 , inserted into a magnet  160 , on which a fiber stop  170  and then a fiber sleeve  180  is secured. This structure may be provided on a heat sink. 
     The optical chassis  100  includes a mount substrate  110  having a ledge  115 , a spacer substrate  120  and a sealer substrate  130 . An optoelectronic device  112  and wire bonds  116  are on the mount substrate  110 . The sealer substrate  130  includes a lens  132  and an angled, reflective sidewall  122 . The angled, reflective sidewall  122  serves as a mirror to direct light between the optoelectronic device  112  and the fiber in the fiber sleeve  180 . If the active area or facet of the optoelectronic device is not on an edge thereof, this angled, reflective sidewall  122  is not needed. 
     An additional spacer substrate  136 , which may include additional spacing structures  138 , separates the lens  132  from an isolator stack  140 . The spacing structures  138  are used when a passive optical element is on one or more opposing surfaces in the stack and the surfaces would otherwise contact the passive optical element. The spacing structures may be integral with the surface or may be provided on the surface. Alternatively, these spacing structures may be on the sealer substrate  130 . The electrical connection of the optoelectronic device  116  is realized using the ledge  115 , as discussed in connection with  FIG. 9 . 
     The isolator stack  140  includes a first polarizer  142 , a Faraday rotator  144  and a second polarizer  146 . The magnet  170 , which may be a ring magnet, surrounds the isolator stack  140  when the optical chassis  100  is inserted as shown in  FIG. 12A , thereby completing the isolator. If the Faraday rotator  144  is a latching type, then the separate magnet  170  is not needed. 
     In any of the above configurations, the active elements are secured to the mount substrate such that they remain secured and withstand subsequent processing, e.g., the securing of the substrate. The construction of the optical chassis of the present invention needs to be determined in an appropriate order, with the least robust technique being performed last. The materials used for the securing of the active elements, realizing the electrical connections and the securing of the substrates must be selected in accordance with the required order. For example, the active elements may be secured on the mount substrate using a gold-tin (AuSn) solder and the substrates may then be secured using a material with a lower melting point, e.g., silver-tin (AgSn) solder. 
     Techniques for realizing alignment of the optical elements in the optical chassis are shown in  FIGS. 13A-14B . In making micro-optical elements, there are inevitable variations in characteristics, e.g., lens thickness, radius of curvature (ROC), of individual elements. By classifying these lenses by their ROC into different groups within a range, e.g., ±1%, the variation in ROC may be compensated for with the placement of the angled surface  122  of the spacer substrate  120 , as shown in  FIG. 13A-13B . Once a lens is selected for a particular optoelectronic device  112  on the mount substrate  110 , the separation d between the optoelectronic device  112  and a back edge of the angled surface  122  is determined in accordance with the ROC of the lens to be used. If the angled surface  122  has an angle of approximately 45°, this distance d will be roughly equal to the height of the spacer substrate  120 . Thus, this aligning of the optoelectronic device  112  with the angled surface  122  compensates for any variations in the thickness of the spacer substrate  120 , as well as taking the ROC of the lens into account. 
     The aligning of the lens to the optoelectronic device  112  is shown in  FIGS. 14A-14B . Here, the image of the active area of the optoelectronic device  112  in the reflective angled surface  122  may be used to align the lens. A bottom surface of the substrate having the lens thereon, which may be the sealer substrate  130  as shown in  FIGS. 12A-12B , includes alignment features  134 , here in the form of a crosshair centered on the lens on the top surface of the substrate. The alignment features  134  are then centered with the image of the active area of the optoelectronic device  112  as reflected by the angled surface  122  to insure proper alignment there between. Since the height of the optoelectronic element changes its location on the angled surface  122 , by aligning the lens to the reflection from the angled surface  122 , variations in the height of the optoelectronic element may be compensated for as well. 
     If the active area of the optoelectronic device  112  is not on a side thereof, the lens may be aligned by directly viewing the active area using alignment features  134 . The variation in height of such optoelectronic devices, i.e., in the z-direction, do not significantly affect the performance. If there are no optical elements on the sealer substrate  130 , the alignment thereof is not critical. Since the sealer substrate  130  is transparent, alignment features do not need to be provided thereon, as alignment features on surfaces below the sealer substrate may be viewed through it. If there are optical elements on other substrates, and the sealer substrate  130  is transparent, the same alignment techniques may be employed. 
     Another embodiment of an optical chassis  200  is illustrated in  FIG. 15 . As can be seen therein, the optical chassis may include a sealer substrate  230 , a spacer substrate  220 , and a mount substrate  260 . The sealer substrate  230 , the spacer substrate  220  and the mount substrate  260  may form an enclosure  240 . 
     While the mount substrate  260  is illustrated in  FIG. 15  as being larger in the x-y plane than the sealer substrate  230  and the spacer substrate  220 , the mount substrate may be the same size in the x-y plane as the remaining substrates. The spacer substrate  220  may be formed from a wafer, e.g., a silicon wafer, etc. or may be an adhesive, e.g., a punched adhesive, or simultaneously provided, as set forth, for example, in U.S. Pat. No. 6,669,803, which is hereby incorporated by reference in its entirety. 
     The sealer substrate  230  may include an optical element  232  on one or both surfaces in the x-y plane. When the optical chassis  200  is to serve as a camera, the optical element(s) may provide an image onto the detector array  262 . 
     Alternatively or additionally, by vertical stacking, i.e., in the z direction, of n/2 substrates on the sealer substrate  230  may provide up to n parallel surfaces on which optical elements may be created. An example of such an optics stack  270  is illustrated in the schematic cross-sectional perspective view of  FIG. 16 . The optics stack  270  may have a same dimension in the x-y plane as the sealer substrate  230  or may be smaller or larger in the x-y plane than the sealer substrate  230 . 
     The optics stack  270  may include a first substrate  280 , a spacer  285 , and a second substrate  290 , thereby providing four parallel surfaces on which optical elements may be formed. The first substrate  280 , the spacer  285  and the second substrate  290  may form interior space  295 . In the particular example illustrated, a first optical element  282  is on an upper surface of first substrate  280  and a second optical element  292  is on an upper surface of the second substrate  290 , i.e., within the interior space  295 . 
     As can be seen therein, and as is evident in the previous embodiments, even when optical elements are formed on these parallel surfaces, opposing substantially planar regions remain at which adjacent substrates may be readily secured, e.g., on a wafer level. The spacer  285  may be integrated with one or both of the adjacent substrates, formed from a wafer, e.g., a silicon wafer, etc. or may be an adhesive, e.g., a punched adhesive, or simultaneously provided, as set forth, for example, in U.S. Pat. No. 6,669,803, which is hereby incorporated by reference in its entirety. 
     The mount substrate  260  may be a sensor substrate, and may include detector array  262 . The detector array  262  may be in the enclosure  240 . The detector array  262  may be a CMOS photodiode array, i.e., may be monolithically integrated in the mount substrate  260 , which may be a CMOS IC substrate. The detector array  262  may receive an image output from the optical element  232 . The mount substrate may further include an array of microlenses (not shown) on the detector array  262 . 
     Then, on the bottom of the mount substrate  260 , conductive, e.g., metalized, through holes or vias (not seen in this view) and conductive structures  266 , e.g., solder balls, may be used to provide the electrical interconnections to the detector array  262  on the top surface of the mount substrate  260 . These through holes may have any appropriate cross section. 
     As shown in  FIG. 15 , the sealer substrate  230  and the spacer substrate  220  may be secured and singulated on the wafer level, with or without the optics stack  270  of  FIG. 16 . Then, a plurality of resultant structure may be secured to a corresponding plurality of detector arrays mount substrates on the wafer level. The mount substrate may then be singulated to form the optical chassis  200 . 
     Alternatively, any of the two adjacent substrates in the z direction may be secured on a wafer level, with resultant structures secured to remaining substrate(s) on wafer level. For example, the optics stack  270  may be secured on a wafer level, and singulated, then the substrates forming the optical chassis  200  may be secured on a wafer level, a plurality of optics stacks  270  may be secured to the wafer level optical chassis, and then the optical chassis may be singulated to form individual optical chassis with the optics stacks  270  thereon. Further, even when the mount substrate  260  is larger in the x-y plane than the sealer substrate  230  and the spacer substrate  220 , illustrated in  FIG. 15 , these may still be secured on a wafer level. For example, after securing the three substrates on a wafer level, a first singulation step may be used to expose an upper surface of the mount substrate  260 , then a second singulation step, which may be the same process or a different process as the first singulation step, may be used to form the individual optical chassis  200 . 
     Thus, in accordance with the present invention, an optical chassis having a small form factor may be created at least partially on a wafer level, including electrical interconnections. The optical chassis of the present invention also provides a seal without requiring a TO can or other separate housing. Further, since substrates of the optical chassis are secured to one another, rather than to a carrier as in a TO can, better alignment can be maintained for longer. 
     While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the present invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the invention would be of significant utility without undue experimentation. For example, any of the electrical interconnections shown may be used with any optical chassis embodiments. Further, additional optical substrates or elements as needed may be secured to the optical chassis. Additionally, the optics stack may be secured to any of the optics chassis. Finally, any of the configurations of the optical chassis may be created at least partially on a wafer level as discussed regarding  FIGS. 3-5 .