Abstract:
A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Description:
PRIORITY CLAIM 
       [0001]    This application is a divisional application of U.S. application patent Ser. No. 13/179,640 filed on Jul. 11, 2011, which claims priority from French Application for Patent No. 1056159 filed Jul. 27, 2010, the disclosures of which are hereby incorporated by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    This disclosure relates to the field of semiconductor devices. 
       BACKGROUND 
       [0003]    It is known to produce reconstituted wafers comprising, in locations, integrated circuit chips embedded in an encapsulation material and to saw these wafers so as to form individual semiconductor devices. 
         [0004]    Nevertheless, it is not possible at the present time to integrate into the wafers, near the chips, capacitors such as those currently used, especially due to their shape and their electrical connection means. 
       SUMMARY 
       [0005]    A process for fabricating a semiconductor device is provided. 
         [0006]    This process comprises: placing, in at least one location on a receiving surface of a carrier, an electrical connection frontside of at least one integrated circuit chip and a frontside of at least one passive component comprising conductive plates separated by dielectric plates forming capacitors; forming on the receiving surface a layer of an encapsulation material so as to obtain, in the location, a wafer comprising an encapsulation block in which the chip and the passive component are embedded and having a frontside comprising the frontside of the chip and the frontside of the passive component; then selectively connecting at least some of the conductive plates to the chip, so that at least some of the capacitors are connected to the chip. 
         [0007]    It is thus possible to prefabricate a passive component having a simple structure, to integrate it into the encapsulation block, and then to form one or more capacitors, as required, when electrical connections are made to the chip. 
         [0008]    The process may comprise: forming at least one front electrical connection track on the frontside of the wafer. 
         [0009]    The process may comprise: forming at least one back electrical connection track on the backside of the wafer, an electrical connection via through the wafer and a front electrical connection track on the frontside of the wafer, the back track and the front track being connected by the electrical connection via. 
         [0010]    The process may comprise: placing the passive component such that the plates extend perpendicularly to the receiving surface, then selectively connecting at least some of the lands of the conductive plates to the chip. 
         [0011]    The process may comprise: placing the passive component such that the plates extend parallel to the receiving surface. 
         [0012]    The process may comprise: placing a passive component having a dielectric plate on the receiving surface, then forming at least one additional conductive plate on the frontside of this dielectric plate so as to form a capacitor comprising this conductive plate and the adjacent conductive plate of the passive component, which are separated by this first dielectric plate. 
         [0013]    A semiconductor device is also provided, which comprises a wafer having a frontside and comprising at least one integrated circuit chip having an electrical connection frontside, at least one passive component having a frontside and comprising conductive plates separated by dielectric plates, forming capacitors, and an encapsulation block in which the integrated circuit chip and the passive component are embedded, a frontside of the encapsulation block, the frontside of the integrated circuit chip and the frontside of the passive component forming the frontside of the wafer, and an electrical connection means connecting at least some of the conductive plates and the integrated circuit chip, the electrical connection means being formed on the frontside of the wafer and/or on the backside of the wafer through the encapsulation block and on the frontside of the wafer. 
         [0014]    The passive component may comprise plates which extend perpendicularly to the frontside of the wafer, the electrical connection means being connected to the lands of the conductive plates. 
         [0015]    The plates may extend through the thickness of the wafer. 
         [0016]    The passive component may comprise plates which extend parallel to the frontside of the wafer. 
         [0017]    The passive component may comprise a dielectric plate adjacent to the frontside of the wafer, at least one conductive plate being formed on the frontside of this dielectric plate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    Semiconductor devices will now be described by way of non-limiting example, illustrated by the drawings in which: 
           [0019]      FIG. 1  shows a cross section of a semiconductor device; 
           [0020]      FIG. 2  shows a front view of the semiconductor device in  FIG. 1 , without a surface layer; 
           [0021]      FIG. 3  shows a perspective view of a passive component of the semiconductor device in  FIG. 1 ; 
           [0022]      FIG. 4  shows the semiconductor device in  FIG. 1 , according to one fabrication step; 
           [0023]      FIG. 5  shows the semiconductor device in  FIG. 1 , according to another fabrication step; 
           [0024]      FIG. 6  shows the semiconductor device in  FIG. 1 , according to another fabrication step; 
           [0025]      FIG. 7  shows the semiconductor device in  FIG. 1 , according to another fabrication step; 
           [0026]      FIG. 8  shows a cross section of another semiconductor device; 
           [0027]      FIG. 9  shows a front view of the semiconductor device in  FIG. 8 , without a surface layer; 
           [0028]      FIG. 10  shows a perspective view of a passive component of the semiconductor device in  FIG. 8 ; 
           [0029]      FIG. 11  shows the semiconductor device in  FIG. 8 , according to one fabrication step; 
           [0030]      FIG. 12  shows the semiconductor device in  FIG. 8 , according to another fabrication step; 
           [0031]      FIG. 13  shows the semiconductor device in  FIG. 8 , according to another fabrication step; and 
           [0032]      FIG. 14  shows the semiconductor device in  FIG. 8 , according to another fabrication step. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    A semiconductor device  1  illustrated in  FIGS. 1 to 3  comprises a wafer  2  which has a frontside  3  and a backside  4 , in parallel. 
         [0034]    The wafer  2  comprises a block of a dielectric encapsulation material  5  in which a prefabricated integrated circuit chip  6  and a prefabricated passive component  7  are embedded, these being placed so that a frontside  8  of the chip  6 , in which the integrated circuits are formed and which has electrical connection pads, a frontside  9  of the passive component  7  and a frontside  10  of the encapsulation block  5  are in the same plane forming the frontside  3  of the wafer  2 , the passive component  7  being placed at a distance to the side of the chip  6 . Thus, the frontside  8  of the chip  6  and the frontside  9  of the passive component  7  are not covered by the encapsulation block  5 . 
         [0035]    The passive component  7  comprises a plurality of superposed plates, which are placed parallel to the frontside  3  of the wafer  2 . According to the example shown, the passive component  7  comprises in succession, in the thickness direction of the wafer  2 , a dielectric plate  11  having the aforementioned side  9 , a conductive plate  12 , a dielectric plate  13  and a conductive plate  14 , the conductive plates  12  and  14  being for example metallic. The plate  12  completely covers the plate  11 , the plate  13  does not completely cover the plate  12  and the plate  14  completely covers the plate  13 , the conductive plate  14  being, in the example shown, distant from the backside  4  of the wafer  2 . 
         [0036]    On the frontside  3  of the wafer  2 , two conductive front plates  15  and  16  are formed, which are connected to electrical connection pads on the frontside  8  of the chip  6  by front electrical connection tracks  17  and  18 , the conductive plates  15  and  16  being located on the frontside  9  of the dielectric plate  11  and being distant from each other. The conductive front plates  15  and  16  have the same thickness as the front electrical connection tracks  17  and  18 . 
         [0037]    Behind the plates  12  and  14 , and between the plates  12  and  14  and the backside  4  of the wafer  2 , holes  19  and  20  are provided in the encapsulation block  5 , which are filled with a conductive material so as to form electrical connection vias  21  and  22 . 
         [0038]    According to one variant, the passive component  7  could have the same thickness as the wafer  2 . In this case, the electrical connection via  22  could be omitted. 
         [0039]    To the side of the chip  6  and the passive component  7 , and between the frontside  3  and the backside  4  of the wafer  2 , through-holes  23  and  24  are provided in the encapsulation block  5  and are filled with a conductive material so as to form electrical connection vias  25  and  26 . 
         [0040]    On the frontside  3  of the wafer  2 , front electrical connection tracks  27  and  28  are formed connecting the vias  25  and  26 , respectively, to electrical connection pads on the frontside  8  of the chip  6  and, on the backside  4  of the wafer  2 , back electrical connection tracks  29  and  30  are formed connecting the vias  21  and  22  to the vias  25  and  26 , respectively. 
         [0041]    Thus, the passive component  7  defines three capacitors connected to the chip  6 , namely a first capacitor C 1  comprising the conductive plate  12  and the conductive plate  15  which are separated by the dielectric plate  11 , a second capacitor C 2  comprising the conductive plate  12  and the conductive plate  16  which are separated by the dielectric plate  11 , and a third capacitor C 3  comprising the conductive plates  12  and  14  which are separated by the dielectric plate  13 . 
         [0042]    On the frontside  3  of the wafer  2 , and covering the conductive plates  15  and  16  and the electrical connection tracks  17 ,  18 ,  27  and  28 , a dielectric layer  31  is provided, incorporating an electrical connection network  32  allowing electrical connection pads, on the frontside  8  of the chip  6 , and external electrical connection bumps  33 , placed on a frontside of the layer  31 , to be selectively connected. 
         [0043]    A protective dielectric layer  34  is provided on the backside  4  of the wafer  2 , covering the electrical connection tracks  29  and  30 . 
         [0044]    The semiconductor device  1  may be produced in the following way, by suitably employing means used in the microelectronics field. 
         [0045]    As illustrated in  FIG. 4 , in respective adjacent, for example square, locations  35  in a receiving surface  36  of a carrier  37 , chips  6  and passive components  7  are placed, their frontsides  8  and  9  being placed against the receiving surface  36 , the receiving surface  36  being for example self-adhesive. 
         [0046]    As illustrated in  FIG. 5 , an encapsulation layer  38  is formed on the receiving surface  36  of the carrier  37 , embedding the chips  6  and the passive components  7  and layer  38  is then leveled or thinned, for example as far as the backside of the chips  6 , so as to obtain a large reconstituted wafer  39  forming, respectively in the locations  35 , encapsulation blocks  5  holding chips  6  and passive components  7 . 
         [0047]    In  FIG. 6 , holes  19 ,  20 ,  23  and  24  are produced, respectively in the locations  35 , and in the encapsulation layer  38  and these holes are filled with a conductive material so as to form vias  21 ,  22 ,  25  and  26 , respectively, in the encapsulation blocks  5 . 
         [0048]    In  FIG. 7  and more fully shown in  FIG. 1 , the layer  31  is produced on the frontside  3  of the wafer  2 , incorporating therein, respectively in the locations  35 , and on the same metallization level, the conductive plates  15  and  16 , the front electrical connection tracks  17 ,  18 ,  27  and  28 , and the electrical connection network  32 . An intermediate dielectric layer could be formed directly on the frontside of the wafer  2 , the conductive plates  15  and  16 , the front electrical connection tracks  17 ,  18 ,  27  and  28  and the electrical connection network  32  then being produced on this intermediate dielectric layer and passing through the latter in places where electrical connection is required. Moreover, the electrical connection network  32  could nevertheless comprise several metallic levels. 
         [0049]    On the backside  4  of the wafer  2 , the layer  34  is produced, incorporating therein, in the locations  35  respectively, and on the same metallization level, the back electrical connection tracks  29  and  30 . 
         [0050]    The electrical connection bumps  33  are placed on the front layer  31 . 
         [0051]    Finally, the large wafer  39  obtained is singulated, along the edges of the location  35 , for example by sawing, so as to obtain a plurality of semiconductor devices  1 . 
         [0052]    When the conductive front plates  15  and  16  are produced, at the same time as the front electrical connection tracks  17  and  18 , the capacitances of the capacitors C 1  and C 2  are defined, especially by choosing the areas of these plates  15  and  16 . Of course, one or more capacitors could be produced by forming one or more conductive plates on the frontside  3 , at the same time as one or more tracks for electrical connection to the chip  6 . 
         [0053]    In addition, being provided with a prefabricated passive component comprising several capacitors, only some of the capacitors could be connected, as a function of the chip  6  used and of the requirements related to the operation and applications of the latter. 
         [0054]    Another semiconductor device  50 , illustrated in  FIGS. 8-10 , comprises a wafer  51  which has a frontside  52  and a backside  53 , in parallel. 
         [0055]    The wafer  51  comprises a block of an encapsulation material  54  in which a prefabricated integrated circuit chip  55  and a prefabricated passive component  56  are embedded, these being placed so that an electrical connection frontside  57  of the chip  55 , a frontside  58  of the passive component  56 , and a frontside  59  of the encapsulation block  5  are in the same plane formed by the frontside  52  of the wafer  51 , the passive component  56  being placed at a distance to the side of the chip  55 . 
         [0056]    The passive component  56  comprises a plurality of superposed plates, placed perpendicular to the frontside  52  of the wafer  51 . According to the example shown, the passive component  56  comprises four parallel, for example metallic, conductive plates  60 ,  61 ,  62  and  63 , separated by three dielectric plates  64 ,  65  and  66 , so as to form three capacitors C 10 , C 11  and C 12 . 
         [0057]    The conductive plates  60 - 63  and the dielectric plates  64 - 66  are placed so as to have front lands which form the side  58  of the passive component  56  in the plane of the frontside  57  of the wafer  51 , and opposite back lands which are in the plane of the backside  53  of the wafer  51 , the conductive plates  60 - 63  and the dielectric plates  64 - 66  consequently having, between these opposite lands, a width corresponding to the thickness of the wafer  51 . 
         [0058]    By way of example, the capacitors C 10 -C 12  may be connected to the chip  55  in the following way. 
         [0059]    For example, front electrical connection tracks  67 ,  68  and  69  may be formed on the frontside  52  of the wafer  51  so as to connect the front lands of the conductive plates  60 ,  61  and  62  to front pads of the chip  55 , by extending onto these front lands and onto these pads, so that the capacitors C 10  and C 11  are connected to the chip  55  by the front tracks  67  and  68  and by the front tracks  68  and  69 , respectively. 
         [0060]    Furthermore, the encapsulation block  54  may have a through-hole  70  filled with a material forming an electrical connection via  71 , a front electrical connection track  72  possibly being formed on the frontside  52  of the wafer  51  so as to connect the via  71  and a front pad of the chip  55 , by extending over this via and this pad, and a back electrical connection track  73  possibly being formed on the backside  53  of the wafer  51  so as to connect the via  71  and the back land of the conductive plate  63 , by extending over this via and this land, so that the capacitor C 12  is connected to the chip  55  by the via  71 , the front electrical connection track  72  and the back electrical connection track  73 . 
         [0061]    On the frontside  52  of the wafer  51 , and covering the frontside of the passive component  56  and the front electrical connection tracks  67 - 69  and  72 , a dielectric layer  74  is provided, incorporating an electrical connection network  75  allowing electrical connection pads, on the frontside  57  of the chip  55 , and external electrical connection bumps  76 , placed on a frontside of the layer  74 , to be selectively connected. 
         [0062]    A protective dielectric layer  77  is provided on the backside  53  of the wafer  51 , covering the backside of the passive component  56  and the back electrical connection track  73 . 
         [0063]    The semiconductor device  50  may be produced in the following way. 
         [0064]    In  FIG. 11 , in respective adjacent locations  78  (e.g., squares) in a receiving surface  79  of a carrier  80 , chips  55  and passive components  56  are placed, their frontsides  57  and  58  being placed against the receiving surface  79 , the receiving surface  79  being for example self-adhesive. 
         [0065]    In  FIG. 12 , an encapsulation layer  81  is formed on the receiving surface  79  of the carrier  80 , embedding the chips  55  and the passive components  56  and the layer  81  is then leveled or thinned, until the backsides of the passive components  56  are exposed, so as to obtain a large reconstituted wafer  82  forming, respectively in the locations  78 , encapsulation blocks  54  holding chips  55  and passive components  56 . 
         [0066]    In  FIG. 13 , a hole  70  is produced, respectively in the locations  78 , in the encapsulation layer  81  and this hole  70  is filled with a conductive material so as to form the via  71 , respectively, in the encapsulation blocks  54 . 
         [0067]    In  FIG. 14  and more fully shown in  FIG. 8 , and in a way equivalent to that described above, with reference to  FIGS. 1 and 7 , in relation to the device  1 , on the one hand, front electrical connection tracks  67 ,  68 ,  69  and  72  and the network  75  are produced, respectively in the locations  78 , in the dielectric front layer  74  and, on the other hand, the back electrical connection track  73  is produced in the dielectric back layer  77 . 
         [0068]    Then the bumps  76  are placed in each location  7 . 
         [0069]    Finally, the large wafer  82  obtained is singulated, along the edges of the locations  78 , for example by sawing, so as to obtain a plurality of semiconductor devices  50 . 
         [0070]    In the two examples described, being provided with a prefabricated passive component comprising several capacitors, only some of the capacitors could be connected, as a function of the chip  55  used and of the requirements related to the operation and applications of the latter. 
         [0071]    According to a variant embodiment, a semiconductor device could comprise a passive component some of the capacitors of which would be connected in series or in parallel, so as to create a resultant capacitor connected to the chip. 
         [0072]    According to a variant embodiment, a semiconductor device could comprise a passive component at least one of the capacitors of which would be directly connected to one of the external electrical connection bumps. 
         [0073]    According to a variant embodiment, a semiconductor device could comprise a passive component at least one of the capacitors of which would be directly connected to another semiconductor device, for example stacked on its backside. 
         [0074]    This disclosure is not limited to the examples described above. Many other variant embodiments are possible without departing from the scope defined by the appended claims.