Abstract:
A two-phase non-overlapping clock generator ( 12 ) generating a sampling signal ( 20 ) utilizing a three transistor NAND gate ( 50 ). The NAND gate of the present invention eliminates one large PMOSFET ( 46 ), and has one NMOSFET ( 52 ) driven by the other phase and having its source grounded. The present invention yields substantial improvement on the jitter of the clock phases. Both rising and falling transitions are improved because of the greatly reduced self-loading of the NAND gate. Overshooting is eliminated, and the NAND gate body effect is minimized, providing enhanced jitter performance of the sampling signal and improving a signal to noise ratio (SNR). The principle of the present invention are also embodied in a NOR gate ( 70 ).

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention is generally related to precision signal sampling circuits, and more particularly to sampling signals sensitive to signal-to-noise ratios, such as two-phase clock generators used in analog circuits including high-speed analog-to-digital converters (ADC&#39;s).  
       BACKGROUND OF THE INVENTION  
       [0002]     In high-speed ADC applications, as well as in every other instance when sampling of an analog signal is involved (i.e. optical receivers, data stream “slicers”, etc.), the precision of the sampling instant impacts the signal-to-noise ratio (SNR) of the discrete-time signal fed into the system. Accordingly, the stability of the timing reference is of paramount importance. From the 12-bit level accuracy on, the thermal noise contribution to SNR has to be minimized to such an extent that a noise contribution coming from sampling jitter of 1 ps or higher becomes the limiting factor for SNR—at least from 70 MHz input frequency on.  
         [0003]     A very clean time reference (OCXO, or other crystal-based solution, further band-pass filtered) must be provided to the non-overlapped phase generation circuits. In turn, the on-chip circuits must provide a clean transition edge to the sampling device—usually a simple switch—driven through a carefully optimized, short path within the clock distribution tree. The thermal noise of the logic gates, and especially the voltage bounce of the supply rails, can significantly degrade the stability of the clock period, introducing perturbations on the time of occurrence of the sampling edge which are inversely proportional to the slope of the waveforms featured at every node.  
       SUMMARY OF THE INVENTION  
       [0004]     The present invention achieves technical advantages by allowing the circuit designer to simplify the NAND/NOR logic gates used in non-overlapped phase generation circuits, eliminating 1 transistor out of 4 that can be proven redundant in a synchronization application. The associated reduction in the capacitive self-loading seen at the gate output advantageously enables much steeper fronts on the output voltage, eventually ameliorating the jitter performance of the whole clock generator.  
         [0005]     The present invention may be incorporated in a novel clock structure implemented for a high speed (80 MSps) high-input frequency (for use in receivers with up to 225 MHz IF) 14-bit analog-to-digital converter (ADC), lowering the jitter from 530 fs down to 230 fs. To date, this ranks as the lowest jitter CMOS-based clock ever implemented and tested in an ADC. In turn, the jitter performance boosts the SNR performance of an ADC from about 60 dBFS at 80 MSps, 220 MHz input to as high as 67 dBFS in the same conditions.  
         [0006]     The present invention advantageously exploits the timing sequence of the signals driving a NAND gate. The present invention recognizes that since the pull-up operation of a node B 2  is dictated by a node B 1  only, keeping two PMOSFET devices in the NAND gate is redundant. In fact, the PMOSFET  46  driven by node A 4  in  FIG. 3 , which will be described in detail shortly, covers an input-to-output transition which is possible in principle, but that never happens in practice when the NAND is embedded in the classical two-phase clock loop of  FIG. 1 . According to the present invention, the structure of the NAND gate  44  is simplified whereby the NAND gate essentially becomes an inverter driven by node B 1 , whose pulldown operation is only conditioned to node A 4 . In other words, the essence of the NAND logic is preserved through the series of two NMOSFETs, whereas the active pull-up can be guaranteed by utilizing only one PMOSFET.  
         [0007]     The NAND gate of the present invention improves the clock generation and distribution on-chip, reducing the jitter of internal clock networks, and simplifies the structure of the NAND CMOS gates built inside the two-phase generator, providing an enhanced solution right at the very root of the problem. The principles and advantages of the present invention is also applicable to a NOR gate.  
         [0008]     The present invention finds particular advantages in two-phase non-overlapped clock circuits of Analog-to-Digital data converters, as well as any circuit having a two-phase non-overlapped clock generator.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a schematic of a conventional two-phase non-overlapping clock generating network, wherein a transition at the output node A 4  is not aligned with the complementary transition at output node B 4 ;  
         [0010]      FIG. 2  is a timing diagram illustrating the principles of the circuit in  FIG. 1  based on inducing a transition at the output node A 4  and which is not aligned with the complementary transition at node B 4 , forcing 3 gate delays between them due to one NAND and two inverters gates;  
         [0011]      FIG. 3  depicts a conventional NAND gate used in the application of  FIG. 1  using a well-known structure;  
         [0012]      FIG. 4  illustrates an alternative implementation of the two-phase generation circuit depicted in  FIG. 1  where the princinle of duality is applied, to show how NOR gates, being dual of NAND gates, can benefit from this invention. In fact the pull-down edge of node B 2  is solely controlled by the rising edge of the input at node B 1 ;  
         [0013]      FIG. 5  is a NAND gate accordingly to the present invention which recognizes only one PMOSFET is needed to perform the output pull-up, and that A 4  can drive the NMOSFET whose source is grounded, eliminating the body effect on the NAND device and making the pull-down transition the quickest possible;  
         [0014]      FIG. 6  depicts a NOR gate according to the principles of the present invention whereby the NMOSFET controlled by node A 4  is eliminated;  
         [0015]      FIG. 7  depicts the increased pull-up edge slope using the NAND gate of the present invention;  
         [0016]      FIG. 8  depicts the pull-down transient driven by A 4  being improved according to the present invention; and  
         [0017]      FIG. 9  depicts the increased speed of the circuit according to the present invention for the pull-down transient driven by B 1  at the circuit&#39;s start-up, due to the reduced capacitive “ballasting” at the output.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0018]     Referring to  FIG. 1 , there is shown a prior art clock generator circuit  10 , having a 2 input 6-gate loop network shown at  12  which performs non-overlapping of the two phases provided at inputs  14  and  16 , and outputs a synchronization signal to a sampling device  18  at output  20 . An inverter tree  24  receives the respective output  26  and  28  of the loop  12  and is a tapered clock distribution/edge regeneration circuitry. If the sampling device  18  receiving output  20  is modeled as a simple NMOSFET switch connected to a sampling capacitor for ease of discussion, the timing sequence in circuit  12  shown at  32 ,  33 , and  28  drives the HIGH---&gt;LOW edge that shuts down the sampling transistor  18  and constitutes the sampling event for the incoming signal.  
         [0019]     The operating principle of the loop network circuit  12  is based on inducing a transition  34  at the output node A 4  ( 26 ) of the non-overlapping network  12 , which transition  34  is not aligned with the complementary transition  36  at output node B 4  ( 28 ) of network  12 . This non-alignment is due to triggering the falling edge  34  of node A 4  on the rising edge of transition  36  of node B 4 , thus forcing  3  gate delays (1 NAND+2 inverters) between the transition fronts, as further illustrated in the timing diagram  40  of  FIG. 2 . For sake of clarity, the NAND gate  44  of circuit  12  is shown where nodes are identified by “B” letters. Since the input  15  at node A 1  of the NAND gate  42  of circuit  12  has already switched to the HIGH state synchronously with the node B 1  falling edge, the state of NAND gate  44  is exclusively controlled by the output at node B 4 .  
         [0020]     The rising edge of signal  33  at node B 2  is instead synchronized to the falling edge of the input clock at node B 1 . In fact, since the self-consistency of the loop  12  forces the rising edge at node B 2  to occur only when node A 4  is HIGH, the input at node B 1  is not “gated” by the NAND gate  44 , which is transparent to it and acts as a simple inverter. On the other hand, the pull-down operation in the NAND gate  44  is only commanded by the other input, connected to node A 4 .  
         [0021]     The standard, prior-art NAND gate  44  used for this application has the well-known structure as depicted in  FIG. 3 , and includes 2 large PMOSFET&#39;s including PMOSFET  46 . This configuration ensures coverage of all the states and output transitions of the digital “truth table” of the NAND gate  44 , in every possible combination/sequence of the two inputs.  
         [0022]     A dual solution used for the generation of non-overlapped phase clock makes use of a NOR gate  48  (and  49 ) in place of the NAND gate  42  and  44 , and is shown at  47  in  FIG. 4 . The whole timing diagram  40  in  FIG. 2  is thus reversed: e.g., the NOR gate  49  pull-up front at node B 2  is commanded by the output of the other side of the digital loop at node A 4  of  FIG. 4 , while the pull-down edge at node B 2  is solely controlled by the rising edge of the input at node B 1 . This configuration  47  can benefit as well from the present invention, through direct application of the principle of duality, as will now be discussed in considerable detail.  
         [0023]     A NAND gate of the present invention is shown in  FIG. 5  at  50 , which eliminates the one large PMOSFET  46  shown in  FIG. 3 . Since the pull-up operation of the B 2  node is dictated by B 1  only, keeping two PMOSFET devices in the NAND gate is redundant. In fact, the PMOSFET driven by A 4  in  FIG. 3  covers an input---&gt;output transition which is possible in principle, but that never happens in practice when the NAND is embedded in the classical two-phase clock loop of  FIG. 1 . The structure of the NAND gate can be simplified, becoming an inverter driven by B 1 , only, whose pull-down operation is conditioned to A 4 . Since node A 4  features a rising edge when node B 1  is in the HIGH state, the present invention advantageously recognizes node A 4  can be connected to NMOSFET  52  whose source is grounded to DVSS, rather than to NMOSFET  54 . The alternative connection (A 4  driving NMOSFET  54 ) could perturb output  60  via feedthrough charge injection. Besides avoiding this perturbation, the proposed connection eliminates the body effect on the NAND  50 , thus making the pull-down transition the quickest possible. Of course, the NMOSFET  54  controlled by node B 1  is necessarily kept in this topology, since the input at node A 4  is HIGH when the falling edge of the transition at node B 1  occurs. Without the presence of the NMOSFET  54  controlled by node B 1 , a DVDD-DVSS short with considerable “crowbar” current would engender.  
         [0024]     The simplified NAND gate  50  according to the present invention advantageously makes use of dynamic charge storage on the gates of the next inverter  17  and  19  (shown in  FIG. 1 ) for a limited interval of time (when node A 4  is LOW and node B 1  is HIGH, i.e. immediately after the transition of the input clock and for a time span on the order of T NON-OVERLAP ) where in that condition the output of NAND  50  remains effectively insulated. The NAND gate  50  does not entail any major limitation on a lower clock frequency of operation, since the charge must be stored in the output node  60  for intervals of about 300-400 ps, and sometimes less, independent on the sampling rate. Clock rates as low as 300 kHz have been successfully tested with the new NAND gate  50  configuration of the present invention.  
         [0025]     The straightforward application of the duality principle to the present invention with regard to the NAND gate  50  also is applicable to a NOR gate  70  shown in  FIG. 6 . The device which can be eliminated from a prior art NOR gate is a NMOSFET (shown hyphenated at  74 ), in parallel to NMOSFET  72  and controlled by node A 4 . It is apparent how the need for two PMOSFETs in series actually remains, still forcing the designer to employ bulky devices with less efficient channel mobility, and increased size to counteract the cascade effect. Thus, NOR gate  70  provides less of an advantage than NAND gate  50  since the device which gets eliminated in NOR gate  70  is the more effective NMOSFET transistor  74  in parallel to NMOSFET  72  in prior art realization.  
         [0026]     The simulated evidence of the beneficial application of the invention to the clock generator circuit of  FIG. 1  is shown in FIGS.  7  to  9  for the NAND gate  50 .  FIG. 7  depicts the faster transient behavior of the present invention at  80 , as compared to a transient  82  using conventional NAND  44 , simulated for the pull-up transition triggered by a falling edge of node B 1  in  FIG. 1 . This is the most important transition occurring in the schematic  10  of  FIG. 1 , namely, the falling edge of the input at node B 1  controls the operation of the sampling device  18 , opening the NMOSFET. In order to drive the sampling device  18  with as clean a signal as possible, the best choice is to derive the sampling front from the input clock through as few gates as possible, from node B 1  to node B 3 . The triggering event cannot come instead from the complementary branch, since it would have to travel through so many gates.  
         [0027]     In the Spice simulation, the load of the NAND gate  50  is an inverter  19  whose total size equals the size of the NMOS-PMOS pair  52 ,  54  of the NAND  50 , with a threshold centered to mid-rail. Even with the same loads, the absence of a bulky PMOSFET shown in the prior art NAND gate  44  (shown in  FIG. 3 ) leads to a striking improvement in the steepness of the transition, as shown at  80 . The slope of waveform  80  taken at the 1.65V threshold (3.3V supply) increases from 67.6 V/μs to 96.9 V/μs, thus improves 43%, as shown in  FIG. 7 . The advantageous enhancement can be fully capitalized into jitter reduction, provided all the other sources of instability (supply bounce, crosstalk, thermal noise of the other inverters/gates) have been properly minimized.  
         [0028]     The other most important transition after the falling edge at node B 1  is the pull-down transient, governed by node A 4 . Although the transient  84  of  FIG. 8  could be theoretically used to drive a sampling event, it is not practical for very low jitter applications, such as a 14-bit ADC converter for wireless applications, for the reasons explained above.  FIG. 8  shows the falling edge at the NAND  50  output  60  once the input source (node B 1 ) has gone high, and node A 4  features a rising edge mandated by the opposite branch of the circuit  12 . The overshoot  86  from the input is much reduced due to the lack of feedthrough from the large PMOSFET  46  which was connected to node A 4  in the prior art NAND  44  shown in  FIG. 3 , which remarkably affects, instead, such a solution. The effect is exacerbated by the extremely steep input edge (1 ps) adopted in simulation. The NAND gate  50  of present invention prevents a detrimental overshoot altogether, as shown, since the other transition (node B 1  LOW---&gt;HIGH) happens when the sampling transistor  18  is fully conducting, hence cannot be perturbed by transients superimposed to the 3.3V level. The pull-down is completed by node A 4  going HIGH, which only injects charge at node  56  between the two cascoded NMOSFETs  52  and  54  without affecting the output  60 , as shown in  FIG. 8  (see  84 ). Since node A 4  is advantageously set to drive the FET transistor  52  with grounded source, no body effect hampers the transient  84 .  
         [0029]     The new NAND gate  50  still demonstrates a clear advantage over the prior art NAND  44 . Since the NAND gate  50  has been designed to feature symmetrical in/out characteristic and pull up/down behavior, the pull-down slopes of NAND gate  50  and the prior art NAND gate  44  are almost identical to the ones previously detected during pull-up: 95.7 V/μs against 66.6 V/μs, or a 44% progress.  
         [0030]     Finally, a transition never occurring during the normal operation of the circuit using NAND  50 , but that may occur during the initial transient, is the output pull-down triggered by the input clock, or node B 1  going HIGH. Although the overshoot caused by the feed-through from the input is present in this case, and is even slightly worse due to the reduced capacitive “ballasting” at the output  60 , the speed of the NAND gate  50  still largely ameliorates the prior art: the slopes detected at  90  and  92  are respectively 98.8 V/μs versus 66.7 V/μs, or a 48% enhancement, as shown in  FIG. 9 .  
         [0031]     Despite the NAND gate  50  lacks some of the otherwise allowed transitions on the truth table (i.e. node A 4  cannot command a rising edge at the output) the NAND gate  50  does not cause any metastable states in the circuit  10  of  FIG. 1 . In fact, any “latched” voltage configuration is resolved at the next edge after half a period, hence, the network  12  comes out of metastability within 1 clock period—worst case.  
         [0032]     The NAND gate  50  is superior to any passive-load gate in terms of pull-up capability and static power consumption (zeroed) , in the same way as every CMOS implementation is superior to all NMOS schemes. The preservation of the active nature of the NAND logic gate  50 , not resorting to passive elements but always having a transistor driving the output, constitutes another advantage.  
         [0033]     The NAND gate  50  is superior to the classical CMOS implementation gate  44  in that it allows to reduce the self-loading at the gate output  60 , saving dynamic power consumption and area in the gate itself and in all the previous inverters driving it, in a tapered “domino effect”. Plain CMOS solutions  44  have been compared ceteris paribus to the NAND gate  50  in simulation and show voltage transients prone to generating jitter in the clock circuit designed on chip, unlike NAND gate  50 .  
         [0034]     One main advantage of the present invention is the enhancement in the slope of the output transitions, both LOW---&gt;HIGH and HIGH---&gt;LOW, as demonstrated in  FIGS. 7 and 8 . The advantage comes from the NAND gate  50  having the same driving devices, but one less idle transistor  46  connected to the output  60 . In the NAND gate  50 , since the device eliminated is a PMOSFET  46 , whose size exceeds the NMOS counterparts  52 ,  54  by a factor 2.5 to 3 to ensure symmetrical transfer function and optimize the noise margins, the gain in steepness is particularly dramatic. Since the RMS timing uncertainty of the clock period (σ T ) generated by the circuit  12  using NAND gate  50  is related to the RMS voltage noise at the output of each logic gate by dividing it by the slope of the waveform, such an advancement directly impacts the jitter performance of the clock. In a system like an ADC, or, more in general, for every application requiring a Sample/Hold stage, in turn this translates into the aperture uncertainty specification.  
         [0035]     For example, in one conventional 14-bit 80 MSps ADC which adopts a prior art NAND gate  44  shown in  FIG. 1 , the utilization of the NAND gate  50  advantageously contributes to a jitter figure improvement from 530 fs down to 230 fs. With IF (Intermediate Frequencies) of the transceiver chains being pushed higher than 200 MHz, and resolutions of 12-14bits, the jitter contribution becomes the dominant one, and such a reduction entails more than 6 dB of difference in SNR and possibly in SINAD, hence &gt;1 bit in ENOB.  
         [0036]     The final inverter driving node A 4  now only sees the NMOSFET  52  of the NAND gate  50 , and not PMOSFET  46 , and can be sized smaller than when driving prior art NAND  44 . In turn, given the customary adoption of an exponential tapering law for the inverters inside the loop  12  of circuit  10  of  FIG. 1  and the ensuing buffer chain, a load reduction in the inverter driving node A 4  reflects into a reduction in the inverter driving node A 3 , and in turn allows for a smaller NAND sizing to begin with. Besides optimizing jitter, the present invention thus enables a lower power consumption for the clock circuit  10  as a whole.  
         [0037]     A straightforward advantage coming from the reduction in the transistor count is the decrease in area and wiring layout complexity.  
         [0038]     As shown in  FIGS. 7-9 , the charge injection of NAND gate  50  into the output  60  is either the same as in prior art (pull-up transition), or, completely canceled out (pull-down). In fact, either the PMOS device governed by node B 1  executes the pull-up, and the transistor configuration is same as the standard gate, or, the NMOS governed by node A 4  executes the pull-down, which is not directly tied to the output  60  and allows for a transient without feedthrough. Furthermore, to start from the rail voltage, and not above it, results eventually in a faster transition.  
         [0039]     As a corollary, the lack of signal feed-through taking the output voltages beyond the rails during certain transitions implies less stressing of the driven inverter gates, or, better compliance with reliability guidelines.  
         [0040]     It has been mentioned that the new gates dynamically store charge. As opposite to the host of dynamic logics that are based onto this principle (NORA, Domino logics), the present invention a) does not employ any form of clocked precharge; and b) does not require the charge to be held for half a cycle (as shown for prior art NAND  44  in  FIG. 2 ) : T nonoverlap &gt;&gt;T cycle /2 is the required storage time.  
         [0041]     The present invention finds particular advantages in clock circuits of Analog-to-Digital data converters as well as any circuit having a two-phase non-overlapped clock generator.  
         [0042]     Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.