Abstract:
A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a full adder circuit and, in particular, a full adder circuit of a multiple logical level type using differential transistor pairs. 
     FIG. 1 shows a full adder circuit substantially similar to that shown in U.S. Pat. No. 3,519,810. This full adder circuit is of a three-input and two-output type using differential paired transistors in a tree-like configuration which is adapted for multiple logical levels. In FIG. 1 V DD  and V SS  represent a high and a low potential power source, respectively, and A, A, B, B, C, C show input signals and S, S show sum output signals. C&#39;, C&#39; represent carry output signals and Vb represents a bias power source for a current source. The full adder circuit of FIG. 1 is characterized in that a sum output signal and carry output signal are almost simultaneously output due to the adoption of the multiple logical level circuit arrangement and that an arithmetic operation is carried out at high speed within a one-gate delay time range. 
     However, this circuit arrangement uses 26 transistors and thus a very great number of elements are required so as to provide a parallel multiplier using such transistors. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a full adder circuit using differential transistor pairs which can perform an arithmetic operation at high speed, using a lesser number of elements. 
     Another object of this invention is to provide a full adder circuit which can reduce a chip occupation area when it is configured as an integral circuit. 
     Still another object of this invention is to provide a full adder circuit which is low in cost and permits a reduced percentage of failure. 
     A three-input and multiple logical level type full adder circuit can be comprised of a combination of basic logical circuits, such as exclusive OR circuits, OR circuits and AND circuits, each having paired differential transistors. The full adder circuit basically requires 20 transistors. Two pairs of differential transistors are used for a lowest level input signal and a current source transistor is connected to the respective paired transistors. According to this invention the number of transistors required can be reduced to 17, noting that for the lowest level input one pair of differential transistors is used in place of two pairs of differential transistors and that one current source transistor is employed in place of one pair of current source transistors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a full adder circuit comprised of conventional differential transistor pairs and adapted to operate at multiple logical levels; 
     FIG. 2 shows a full adder circuit comprised of basic logical circuits, such as an exclusive OR circuit, AND circuit and OR gate, which include paired differential transistors; 
     FIG. 3 shows a basic exclusive OR gate as used in FIG. 2; 
     FIG. 4 shows a basic OR circuit as used in FIG. 2; 
     FIG. 5 shows a basic AND circuit as used in FIG. 2; 
     FIG. 6 shows a full adder circuit according to a first embodiment of this invention; 
     FIG. 7 shows a symbol representation of the full adder circuit of FIG. 6; 
     FIG. 8 shows one application of the full adder circuit as shown in FIGS. 6 and 7; 
     FIG. 9 shows a practical arrangement of FIG. 8; 
     FIG. 10 shows an improved form of arrangement of FIG. 9; 
     FIG. 11 shows a circuit equivalent in operation to that of FIG. 10; 
     FIG. 12 shows another applied form of this invention; 
     FIG. 13 shows a practical arrangement of FIG. 12; and 
     FIG. 14 shows a combination of the circuits of FIGS. 10 and 11. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     According to this invention, as many transistors as practicable are shared in a multiple logical level type full adder circuit, comprised of a simple combination of basic logical circuits, to reduce the number of elements required. Before describing the full adder circuit of this invention, explanation is made of a full adder circuit, comprised of a combination of basic logical circuits, to obtain a ready understanding of this invention. In this connection, reference is invited to FIGS. 2 to 5. 
     With input binary digits representing A, B and C, an arithmetic operation is performed on the full adder circuit in the following way: 
     
         S=A⊕  B⊕ C                                         (1) 
    
     
         C&#39;=B·C+C·A+A·B                  (2) 
    
     where S denotes a sum digit and C&#39; denotes a carry digit. 
     Thus, the full adder circuit can be made by a combination of exclusive OR circuits, AND circuits and OR circuits. FIG. 2 shows a full adder circuit. FIGS. 3, 4 and 5 show an exclusive OR circuit, OR circuit and AND circuit, respectively, which constitute the full adder circuit. The transistors used in these circuits are of NPN type. Since these basic logical circuits are well known in the art, further description thereof seems unnecessary. 
     In the full adder circuit shown in FIG. 2 the exclusive OR circuits of FIG. 3 are stacked in two stages above a current source of transistor Q19 and resistor R5. 
     The full adder circuit of FIG. 2 performs an arithmetic operation in the form of: 
     
         S=A⊕(A  B)⊕ C 
    
     which is a modification of FIG. 1. On the other hand, the circuit above a current source comprised of transistor Q20 and resistor R6 in FIG. 2 shows a combination of OR circuit of FIG. 4 and AND circuit of FIG. 5. For example, the carry digit C&#39; rises to a high voltage level when a current flows through transistors Q11 and Q17 simultaneously, when a current flows through transistors Q5, Q12 and Q17 simultaneously, or when a current flows through transistors Q5, Q13 and Q18 simultaneously. This can be logically expressed in the form: ##EQU1## This is equivalent to FIG. 2. 
     The full adder circuit of FIG. 2 uses 20 transistors, which is less than the full adder circuit of FIG. 1. According to this invention, the number of elements required can be reduced through replacement of the shared transistors with a lesser number of transistors. That is, in the full adder circuit of FIG. 2, input signals A and A are applied respectively to transistors Q15 and Q16 and respectively to transistors Q17 and Q18. In consequence, the number of elements can be reduced through the replacement of transistors Q15 and Q17 with one transistor and the replacement of transistors Q16 and Q18 with one transistor. 
     A full adder circuit according to one embodiment of this invention will be described by referring to FIG. 6. In this circuit, identical reference numerals are employed to designate circuit elements corresponding to those shown in FIG. 2. 
     In FIG. 6, first and second transistors Q1 and Q2 are connected at their emitters to each other and at their collectors to a high potential power source V DD , respectively through first and second resistors R1 and R2. Similarly, third and fourth transistors Q3 and Q4 are connected at their emitters to each other and at their collectors to power source V DD  respectively through the resistors R1 and R2. Fifth and sixth transistors Q5 and Q6 are connected at their emitters to each other and at their collectors to power source V DD  respectively through resistors R3 and R4. First to fourth resistors R1 to R4 have an equal resistive value of about 1 kΩ. The bases of first, fourth and fifth transistors Q1, Q4 and Q5 are connected to receive an input signal C and the bases of second, third and sixth transistors Q2, Q3 and Q6 are connected to receive an input signal c which is complementary to the input signal C. 
     Emitter-coupled seventh and eighth transistors Q7 and Q8 have their collectors connected to commonly connected emitters of first and second transistors Q1 and Q2 and to the commonly connected emitters of transistors Q3 and Q4, respectively. Emitter-coupled ninth and tenth transistors Q9 and Q10 have their collectors connected to the commonly connected emitters of transistors Q1 and Q2 and to the commonly connected emitters of transistors Q3 and Q4, respectively. Eleventh and twelfth transistors Q11 and Q12 are connected at their emitters to the emitters of transistors Q7 and Q8. Transistor Q11 is connected at its collector to the collector of transistor Q5. Transistor Q12 is connected at its collector to the commonly connected emitters of transistors Q5 and Q6, and thirteenth and fourteenth transistors Q13 and Q14 are connected at their emitters to the emitters of transistors Q9 and Q10. Transistor Q13 is connected at its collector to the emitters of transistors Q5 and Q6 and transistor Q14 is connected at its collector to the collector of transistor Q6. 
     The bases of transistors Q7, Q11, Q10 and Q13 are commonly connected to receive an input signal B and the bases of transistors Q8, Q12, Q9 and Q14 are commonly connected to receive an input signal B complementary to the input signal B. 
     Fifteenth and sixteenth transistors Q15 (17) and Q16 (18) are connected at their emitters to a low potential power source V SS  through a current source comprised of a transistor Q19 (20) and resistor R5 (6). Transistor Q15 (17) is connected at its collector to the emitters of transistors Q7, Q8, Q11 and Q12 and transistor Q16 (18) is connected at its collector to transistors Q9, Q10, Q13 and Q14. The base of transistor Q15 is connected to receive an input signal A and the base of transistor Q15 is connected to receive an input signal A complementary to the input signal A. Transistor Q19 (20) is connected at its base to a bias power source Vb. 
     In the circuit as set out above, power source V DD  is +5 volts, power source V SS  is 0 volt and bias power source Vb is 1.5 volts. In this connection it is to be noted that the input signals C, C have a logical swing of 4.4 to 5 volts, that the input signals B, B have a logical swing of 3.7 to 4.3 volts and that the input signals A and A have a logical swing of 3.0 to 3.6 volts. Resistor R(5) has a resistive value of 0.5 kΩ. 
     The full adder circuit of this embodiment performs an arithmetic operation expressed by Eqs. 1 and 2. According to this invention, 17 transistors are used, which is three less than the number of transistors in the circuit of FIG. 2 and nine less than in the circuit of FIG. 1. Furthermore, the high-speed operation characteristics of the multiple logical level circuit is not impaired. 
     An application of the circuit of FIG. 6 will be described below. FIG. 7 shows a symbol representation of the circuit of FIG. 6. FIG. 8 shows a 4-input adder circuit obtained by provision of one NOR gate at an input of the adder circuit. This practical circuit arrangement is shown in FIG. 9. 
     That is, NOR gates for X and Y are connected at A and A inputs of FIG. 6. Stated in more detail, input signals X and X are applied to the bases of transistors Q15 and Q16, respectively and a pair of differential transistors Q21, Q22 are connected between transistor Q19 and the paired transistors Q15 and Q16. The bases of transistors Q21 and Q22 are connected to receive input signals Y and Y, respectively. More specifically, transistor Q21 is connected at its collector to the collector of transistor Q15 and transistor Q22 is connected at its collector to the emitters of transistors Q15, Q16. 
     In the circuit of FIG. 9 the logical level of input signals Y and Y have to be made smaller than that of the input signals A, A in FIG. 6. For example, the input signals Y, Y may have a logical swing of 2.3 to 2.9 volts. It may sometimes be difficult to operate when the power source voltage is not adequate. FIG. 10 shows an improved circuit arrangement. 
     In the circuit shown in FIG. 10, transistors Q22 and Q15 are connected in parallel with each other such that transistor Q22 receives an input signal Y at its base and transistor Q15 receives the input signal X. A reference voltage Vref. 1 of 3.3 volts is applied to the base of transistor Q16. In this circuit, the input signal Y may have, like the input signal X, a logical swing of 3 to 3.6 volts. When either one of the input signals X, Y has a greater magnitude than the reference voltage Vref. 1, transistors Q7, Q11, Q12 and Q8 are selected to achieve the same logical operation as in FIG. 9. In spite of a multi-stage stacked-up arrangement as shown in FIG. 6 it is still possible to perform a complex logical function. 
     FIG. 11 shows a circuit, equivalent to that shown in FIG. 10, which is obtained by incorporating NOR gates for inputs X, Y at the inputs B, B. In this circuit, a combination of transistors Q7 and Q11 is connected in parallel with a combination of transistors Q23, and Q24 and a combination of transistors Q26 and Q25 is connected in parallel with a combination of transistors Q10 and Q13. A reference voltage of 4 volts is applied to the bases of transistors Q12, Q8, Q9 and Q14. The input X is applied to the bases of transistors Q7, Q11, Q25 and Q26 and the input Y is applied to the bases of transistors Q23, Q24, Q10 and Q13. This circuit requires more transistors than those of the circuit of FIG. 10, but a better performance is obtained due to the symmetrical configuration. 
     FIG. 12 shows a full adder circuit having two NOR gate circuits incorporated, the practical circuit of which is shown in FIG. 13. From this it is appreciated that this circuit is comprised of a combination of the circuits of FIGS. 9 and 11. Another applied form of circuit is shown in FIG. 14 which corresponds to a combination of circuits of FIGS. 10 and 11. 
     Although the full adder circuit using NPN transistors has been described above, it may be possible to employ PNP transistors or GaAs MOSFETs.