Abstract:
In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.

Description:
BACKGROUND 
     Mobile computer platforms may support multiple output voltages and may operate at high speeds. Accurate current sense information for the load (CPU) is required to manage the performance of the platform against thermal and battery lifetime constraints. Accurate current sense information is required for switching power conversion. Advances in power management technology and voltage/current ratings are now making accurate current sensing a requirement. 
     On-board discrete components may be utilized for current sensing of the load but the discrete components consume area and power. In addition, an external controller has to process the sensed information. Integrated sense transistors within the switching portion of a voltage regulator (VR) may be utilized to sense load current but limit the switching speed of the VR. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features and advantages of the various embodiments will become apparent from the following detailed description in which: 
         FIG. 1  illustrates a high level block diagram of a computing platform; 
         FIG. 2  illustrates a high-level functional block diagram of an example high-speed current sensing multi-phase voltage regulator (VR), according to one embodiment; 
         FIG. 3  illustrates a more detailed functional block diagram of the example high-speed current sensing multi-phase VR of  FIG. 2 , according to one embodiment; 
         FIG. 4  illustrates a schematic diagram of the example VR of  FIG. 2 , according to one embodiment; and 
         FIG. 5  illustrates an example digital correction function used in the example VR of  FIG. 2 , according to one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates a high level block diagram of a computing platform  100 . The platform  100  includes a load (CPU)  110 , a voltage regulator (VR)  120 , external power management control (EC)  130 , and on-board voltage/current (V/I) sense elements  140 . The CPU  110  provides the processing for the system  100 . The VR  120  provides regulated voltages to the CPU  110  for various load conditions. The EC  130  monitors and manages the power consumption of the platform and performs platform diagnostics. The EC  130  requires accurate voltage and current information of all loads on the platform  100  to optimally manage the performance of the platform against thermal and battery lifetime constraints. The on board V/I sense elements  140  are utilized to sense the current and voltage for different loads and provide the sensed data to the EC  130 . The EC  130  may have to process the sensed information provided by the on board V/I sense elements  140 . The implementation of the on board V/I sense elements  140  and the processing of the sensed information by the EC  130  may be performed by the platform designers. Furthermore, the on board V/I sense elements  140  consume area/power, and suffer from sense errors due to part tolerance, drift and losses. Directly providing accurate rail current information from the VR  120  may substantially reduce the platform designers overhead by eliminating the need to do any platform (on board) current sensing or post-processing of the current sensing by the EC  130 . 
     The VR  120  may use at least one or more switch and/or rectifier elements and an inductor to implement a “phase leg” to deliver switchably controlled current from an applied voltage source to the load  110  through a regulated voltage node. When the load  110  requires more current, the one or more switches are controlled to supply the load with current from the applied voltage for longer durations within a switching period (higher duty cycle). Conversely, the current is applied for smaller durations in the period (lower duty cycle) when less current is required by the load. A multi-phase VR  120  may have several phase legs commonly coupled to the regulated voltage node to deliver to it their current. The conduction time of the individual phase legs are staggered, typically uniformly, over a switching interval to minimize output voltage/current ripple, and to reduce the size of output capacitance needed to filter switching noise. 
     Integrated sense transistors (senseFET) have been implemented in VRs  120  as a lossless sensing means that offers high sense accuracy if it is possible to integrate the sense element with the switching transistors (switch element) portion of the VR  120 . The senseFET mirrors the high-side (control) transistor current and provides an instantaneous representation of the inductor current during the charging cycle of the VR. However, the high-side FET current sensing, by itself, does not provide the load current, and requires post-processing to extract the load current. Moreover, the senseFET is typically used in VRs having a switching speed on the order of 1 MHZ. Motherboard area constraints and expectations of fast transient response as well as state transitions are forcing miniaturization of the VR  120  for close proximity to the load  110  and switching operations at very-high frequency (e.g., 30-50 MHz). 
       FIG. 2  illustrates a high-level functional block diagram of an example high-speed current sensing multi-phase VR  200 . The VR  200  performs functions in both an analog domain  210  and a digital domain  220 . Within the analog domain  210 , the VR  200  performs high-speed current sensing  230  for each phase of the VR  200  and averages the sensed currents from each phase  240 . Within the digital domain  210 , the VR  200  performs post-processing error correction  250  and reporting  260 . The average sensed current (V iavg ) may be a function of load current (I load ) and duty cycle (D) such that V iavg =(D*I load ). Accordingly, in order to accurately calculate I load  from V iavg , D needs to be measured. D can be measured  270  in the analog domain  210  and utilized in the error correction  250 . 
       FIG. 3  illustrates a more detailed functional block diagram of the example high-speed current sensing multi-phase VR  200 . Each phase  300  of the VR  200  includes a single phase bridge (e.g., switching transistors)  305 , current sensing  310 , current mirror  315 , current to voltage (I-V) converter  320 , voltage gain stage  325 , and phase balancing  330 . The current mirror  315  may mirror the current of the single phase bridge  305  and the current sensing  310  may sense the high side transistor current in the current mirror  315 . Since the current is being sensed from the current mirror  315  the duty cycle of the VR  200  may affect how the sensed current equates to the I load . The sensed current may be a fraction of the current supported by the high-side control transistor of the bridge  305  (e.g., based on the duty cycle of the VR  200 ). The current sense  310  and current mirror  315  may be used to sense current in VRs having high switching speeds (e.g., 30-50 MHz). 
     The sensed current may be provided to the I-V converter  320  where the sensed current is converted to a voltage and may band limit the voltage to reject spurious noise. The voltage gain stage  325  gains up the voltage to maximize the useable voltage range (e.g., maximize available analog-to-digital range). The output of the voltage gain stage  325  is the average sensed high-side transistor current per phase. The phase balancing  330  may utilize the per phase sensed current for phase current balance of the VR  200 . The per phase sensed current may also be used for current-mode control in a regulation feedback loop (not illustrated). The multi-phase current averaging  240  receives the sensed high-side transistor current (in the from of a voltage) for all phases and combines them together to generate an average high-side transistor current over all phases (V iavg ). 
     The duty cycle extractor  270  measures the duty cycle of the VR  200 . The duty cycle may be sensed with minimal sense error. An analog to digital converter (ADC)  245  receives the D from the duty cycle extractor  270  and the V iavg  from the multi-phase current averaging  240  and translates them to the digital domain  220 . Once in the digital domain  220  the digital correction  250  corrects for gain and offset errors. The telemetry and phase dropping  260  may perform platform diagnostics. 
       FIG. 4  illustrates a schematic diagram of the example VR  200 . The high-speed inductor current waveform is reconstructed by using mirror high-side current sense elements, with a nominal main-path to sense-path ratio. The current mirror  315  may include a stack of transistors (e.g., two positive channel transistors (PMOS) stacked on top of two negative channel transistors (NMOS)). The current sensing  315  may include a transistor (e.g., PMOS) coupled to the high side transistor of the current mirror  310 . 
     The number of active phases at any time is determined dynamically as a function of the sensed average current. The output sensed current from inactive or disabled phases floats and could corrupt the average signal. For this reason, a transmission gate (T-gate)  400  is connected at the input to the averaging amplifier  240 . The T-gate  400  disconnects the input from the disabled phase. The T-gate is connected to all phase inputs other than the reference phase, since the reference phase is always on once the rail is enabled. As a result, the output (V iavg ) of the averaging amplifier  240  is the average high-side transistor current of only the conducting phases of any given rail. 
     The VR  200  may include a multiplexer  410  that receives the V iavg  from the averaging amplifier  240  and the D from the duty cycle extractor  270  and provides the appropriate signal to the ADC  340  based on the operation of the digital correction  250 . 
     The average sensed current (V iavg ) measured may include errors. The errors may be based on the offset voltage (V os ) and gain (G) of the VR  200 . Accordingly, the V iavg  may be a function of measurement errors (V os , G), and number of active phases (N) in the VR  200  in addition to load current (I load ) and duty cycle (D), such that V iavg ={(D*N*I load )/G}+V os . In order to use V iavg  to estimate I load  appropriate corrections need to be made such that I load ={(V iavg −V os )*G}/(D*N). The corrections (modifications to V iavg ) are performed digitally by the digital correction  250 . 
     The G and the V os  can be determined at test and stored as trim values. The G and the V os  may be extracted by testing two of the rails at a common load current, but different duty ratios, or by testing a single rail at two current levels. This approach is totally independent of tolerance and losses of other elements on the board or the chip. Temperature drift of current sense characteristics is small and does not need correction. 
       FIG. 5  illustrates an example digital correction function  250 . The digital correction function  250  includes a register  500 , a summer  510 , a multiplier  520 , a divider  530 , a multiplier  540  and a phase number detector  550 . The digital correction function  250  receives the parameters (V iavg , V os , G and D) used to calculate the load current (I load ) and stores them in the register  500 . The register  500  may receive the V iavg  and D from the ADC  340 . As noted above, the V os  and G values can be trimmed at test and stored in a fuse bank  560  and the register  500  may receive them from the fuze bank  560 . The order of sensing from the register  500  is utilized to convert V iavg  to I load . The V iavg  is first offset corrected (the summer  510  subtracts the V os  from V iavg ) and then gain corrected (the multiplier  520  multiplies the output of the summer  510  by G) to extract the true V iavg . Subsequent division by the duty cycle (the divider  530  divides the output of the multiplier  520  by D) provides the average load current per phase. Multiplying the average load current per phase by N with the multiplier  540  provides the actual load current. The N is determined by the digital control logic  550  based on the sensed load current. 
     The digital correction function  250  yields the corrected current sense that equates to I load  and is available for telemetry  260 , over-current protection, phase-count detection and other functions. 
     Although the disclosure has been illustrated by reference to specific embodiments, it will be apparent that the disclosure is not limited thereto as various changes and modifications may be made thereto without departing from the scope. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described therein is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment. 
     The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.