Abstract:
Methods for preparing a surface for selective silicon-germanium epitaxy by forming a thin silicon (Si) buffer layer or a thin, low concentration SiGe buffer layer for uniform nucleation, are disclosed.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The present invention relates generally to selective epitaxial growth of silicon-germanium (SiGe), and more particularly, to methods and structure for providing a buffer layer for selective SiGe epitaxial growth to provide uniform nucleation.  
         [0003]     2. Related Art  
         [0004]     Selective silicon germanium (SiGe) epitaxial growth is used for SiGe raised source drain (RSD) or embedded SiGe structures because it allows for improved p-type field effect transistor (PFET) performance due to compressive strain in the channel and lower contact resistance. The compressive strain in the channel enhances the hole mobility.  
         [0005]     One challenge relative to SiGe selective epitaxial growth is that it is very sensitive to surface conditions. The higher the germanium (Ge) concentration, the more sensitivity exists. In contrast, selective silicon (Si) epitaxial growth is less sensitive to the surface condition. SiGe selective epitaxial growth on highly doped substrates, e.g., &gt;1×20/cm 3 , often leads to spotty growth or no growth where the highly doped substrate is exposed to ambient. In this case, a wet chemical clean and a hydrofluoric (HF) acid etch is necessary to remove the native oxide from the surface. Unfortunately, even with these cleanings steps, the highly doped surface reoxidizes easily, which causes a nucleation problem. Surfaces with residue from a spacer reactive ion etch (RIE) also cause spotty growth in selective SiGe epitaxial growth. In one example, where a 300 Angstrom (Å) thick layer of SiGe is desired, only 2 Å are possible for a highly doped (e.g., ˜1×20/cm 3 ) P+ SOI layer, while for an undoped SOI layer, 314 Å of SiGe can be grown.  
         [0006]     In view of the foregoing, there is a need in the art for a solution that solves the problems of the related art.  
       SUMMARY OF THE INVENTION  
       [0007]     The invention includes methods for performing selective silicon-germanium epitaxy on a highly doped monocrystalline silicon by forming a thin silicon (Si) buffer layer or a thin, low concentration SiGe buffer layer for uniform nucleation.  
         [0008]     A first aspect of the invention is directed to a method for performing selective silicon-germanium epitaxy on a highly doped monocrystalline silicon, the method comprising the steps of: providing a substrate including an exposed, highly doped, monocrystalline silicon region; etching surface oxide; selectively growing a buffer layer on the monocrystalline silicon region, the buffer layer including one of silicon and silicon-germanium; and selectively growing a silicon-germanium layer on the buffer layer.  
         [0009]     A second aspect of the invention is directed to a method for performing selective silicon-germanium epitaxy on a highly doped monocrystalline silicon, the method comprising the steps of: providing a monocrystalline silicon region having a dopant concentration of greater than approximately 5×10 19  per cubic centimeter; etching surface oxide from the monocrystalline silicon region; selectively growing a buffer layer on the monocrystalline silicon region, the buffer layer having a thickness of no greater than approximately 200 Å; and selectively growing silicon-germanium with a germanium concentration of less than approximately 50%.  
         [0010]     A third aspect of the invention is directed to a method for performing selective silicon-germanium epitaxy on a highly doped monocrystalline silicon, the method comprising the steps of: providing a monocrystalline silicon region having a dopant concentration of greater than approximately 5×10 19  per cubic centimeter; etching surface oxide from the monocrystalline silicon region; selectively growing a buffer layer on the monocrystalline silicon region, the buffer layer having a thickness of no greater than approximately 200 Å; and selectively growing silicon-germanium with a germanium concentration that is no less than approximately 10% and no greater than approximately 25% using a temperature of no less than approximately 500° C. and no greater than approximately 750°, and a source gas selected from the group consisting of: 1) dichlorosilane (DCS), hydrochloride (HCl) and germane (GeH 4 ), 2) silane (SiH 4 ), germane (GeH 4 ) and hydrochloride (HCl); 3) disilane (Si 2 H 6 ), germane (GeH 4 ) and hydrochloride (HCl); and 4) Si 2 H 6 , germane (GeH 4 ) and chlorine (Cl 2 ).  
         [0011]     The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:  
         [0013]      FIG. 1  shows a transistor including a silicon-germanium raised source/drain.  
         [0014]      FIG. 2  shows a transistor with embedded silicon-germanium in the source/drain region.  
         [0015]      FIGS. 3-5  show steps of methods of forming the silicon-germanium layer according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]     Selective silicon germanium (SiGe) epitaxial growth is used for SiGe raised source drain (RSD) or embedded SiGe structures because it allows for improved p-type field effect transistor (PFET) performance due to compressive strain in the channel and lower contact resistance of silicide. The compressive strain in the channel enhances the hole mobility. SiGe RSD on NFET also lowers silicide contact resistance.  
         [0017]     With reference to the accompanying drawings,  FIG. 1  illustrates a transistor  10  with a SiGe raised source drain (RSD). Transistor  10  includes: a buried oxide  12 , a shallow trench isolation (STI)  14 , a source/drain region  16 , an extension region  18 , a well  20  having a gate oxide  22  thereabove, a SiGe raised source/drain region  24 , a spacer  26 , a reoxidation area  28 , and a gate  30 .  FIG. 2  illustrates a transistor  110  with an embedded SiGe source/drain including: a buried oxide  112 , a shallow trench isolation (STI)  114 , a source/drain region  116 , an extension region  118 , a well  120  having a gate oxide  122  thereabove, a spacer  126 , a reoxidation area  128 , and a gate  130 . Transistor  110  also includes a unitary, embedded silicon-germanium (SiGe) source/drain region  140 . In these cases, the exposed substrate for selective SiGe epitaxy is highly doped, e.g., having &gt;1×20/cm 3  of dopant. Although transistors built on a silicon-on-insulator (SOI) substrate are illustrated here, the invention can also be applied to a bulk substrate.  
         [0018]     One challenge relative to SiGe selective epitaxial growth is that it is very sensitive to surface conditions. The higher the germanium (Ge) concentration, the more sensitivity exists. In contrast, selective silicon (Si) epitaxial growth is less sensitive to the surface condition. SiGe selective epitaxial growth on highly doped substrates, e.g., &gt;1×20/cm 3 , often leads to spotty growth or no growth where the highly doped substrate is exposed to ambient. In this case, a wet chemical clean and a hydrofluoric (HF) acid etch is necessary to remove the native oxide from the surface. Unfortunately, even with these cleanings steps, the highly doped surface reoxidizes easily, which causes a nucleation problem. This invention utilizes the fact that selective Si epitaxy is less sensitive to the surface condition to improve nucleation of selective SiGe epitaxy.  
         [0019]     Referring to  FIGS. 3-5 , one embodiment of a method for performing a selective silicon-germanium epitaxy on a highly doped monocrystalline silicon will now be described. A simpler structure is described here. As shown in  FIG. 3 , in a first step, a substrate  200  including an exposed, highly doped, monocrystalline silicon region  210  is provided. Highly doped silicon region  210  may be an extension region, a source/drain region, or a recessed source/drain region. In any event, silicon region  210  is doped to greater than approximately 5×10 19  per cubic centimeter. Substrate  200  also includes a dielectric region  220 , which may be STI or a dielectric spacer.  
         [0020]     A hydrofluoric acid (HF) etch process is used first to remove most of the oxide on a surface  212  of highly doped silicon region  210 . A diluted HF solution is typically used for this etching process, such as typically 10:1-500:1H 2 O:HF solution, preferably 50:1-200:1 HF solution. Cleaning processes that remove particles, metals, organic contaminations can be performed before the HF etch. After the HF etch, the wafer is dried without water rinse (HF last), or it can be rinsed with diluted HCl solution (HCl last), or de-ionized (DI) water before drying. A HF last or HCl last process is preferred as it minimizes the reoxidation of the silicon surface. Silicon surface  212  after this HF etch is passivated with hydrogen, which slows down the reoxidation during the time the wafer is exposed to an oxygen-containing environment, such as when it is transferred from the HF etch chamber to the epitaxy chamber.  
         [0021]     Substrate  200  is then transferred and loaded into an epitaxy loadlock chamber (not shown) within a time window. The time window can be as long as a few hours before silicon surface  212  starts to be reoxidized significantly in the ambient. A time window of less than 1 hour is preferred to minimize reoxidation. The loadlock chamber of the epitaxy tool is purged with high-purity inert gas, such as high-purity nitrogen. A loadlock chamber that is capable of having the ambient evacuated (pumped loadlock) is preferred as it can quickly reduce the oxygen and moisture content in the loadlock to below the parts-per-million (ppm) level during a purge cycle. The wafers can then be transferred to the epitaxy deposition chamber.  
         [0022]     Referring to  FIG. 4 , a next step includes selectively growing a buffer (or nucleation) layer  230  on monocrystalline silicon region  210 , which is shown much larger in  FIG. 4  than actual size so as to be easily discernable. In particular, buffer layer  230  preferably has a thickness of no greater than approximately 200 Å, and even more preferably of no greater than approximately 50 Å. Buffer layer  230  includes silicon or silicon-germanium. In one embodiment, buffer layer  230  is grown using a temperature of no less than approximately 550° C. and no greater than approximately 850° C., and more preferably using a temperature of no less than approximately 600° C. and no greater than approximately 750° C. A source gas may be selected from: 1) dichlorosilane (DCS) and hydrochloride (HCl) as a source gas, and 2) silane (SiH 4 ) and hydrochloride (HCl). High purity hydrogen (H 2 ) gas is typically used as a carrier gas. When buffer layer  230  includes silicon-germanium, a germanium concentration of the layer is preferably no greater than approximately 25%, and even more preferably no greater than 10%. In any event, the germanium concentration of buffer layer  230  is less than the silicon-germanium layer to be formed next.  
         [0023]     In a next step, shown in  FIG. 5 , a silicon-germanium (SiGe) layer  240  is formed on buffer layer  230 . SiGe layer  240  is formed by conducting an epitaxial selective growth of SiGe. The growing step may include using a temperature of no less than approximately 500° C. and no greater than approximately 7500. A source gas may be selected from: 1) DCS, hydrochloride (HCl) and germane (GeH 4 ), 2) silane (SiH 4 ), germane (GeH 4 ) and hydrochloride (HCl); 3) disilane (Si 2 H 6 ), germane (GeH 4 ) and hydrochloride (HCl); and 4) Si 2 H 6 , germane (GeH 4 ) and chlorine (Cl 2 ). High purity hydrogen (H 2 ) gas is typically used as carrier gas. Furthermore, in this embodiment, a germanium concentration is preferably no greater than approximately 50%, and more preferably is no less than approximately 10% and no greater than approximately 25%. In another embodiment, SiGe may be grown in intervals having increasing concentrations of germanium, e.g., Si, then SiGe with 5% Ge, then SiGe with 10% Ge, then SiGe with 15% Ge, etc.  
         [0024]     Buffer layer  230  and SiGe layer  240  are intrinsic as described above. They can be in-situ doped as well. In the case of in-situ doping, a dopant source gas is added to above mentioned source gases. B 2 H 6  is typically used as source gas for P-type doping, and AsH 3  or PH 3  is typically used for N-type doping.  
         [0025]     While this invention has-been described in conjunction with the specific embodiments outlined above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the embodiments of the invention as set forth above are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.