Abstract:
A semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying unit coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying unit in response to a control signal.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device capable of sensing and amplifying a voltage between a pair of bit lines in high speed. 
   DESCRIPTION OF RELATED ARTS 
   Generally, in a dynamic random access memory device (DRAM), it is mandated to amplify data stored into memory cells with use of a bit line sense amplifier for a read operation and a refresh operation. Particularly, when a row address is inputted, data of memory cells connected to a word line activated in response to the inputted row address are inputted in a low voltage level to a pair of bit lines. A bit line sense amplifier including a number of transistors connected with each other in latch type senses the inputted low voltage level and then amplifies the sensed voltage into a logic level. 
     FIG. 1  is a block diagram showing how bit lines and bit line sense amplifiers of a conventional DRAM are connected and arranged with each other. 
   As shown, the conventional DRAM includes L number of memory cell array blocks, i.e., a first cell array block  10  to an Lth memory cell array block  40 L. Each of the first to the Lth memory cell array blocks  10  to  40 L includes n number of word lines and m number of bit line pairs. Herein, L, n and m are positive numbers. For instance, the first memory cell array block  10  includes a first word line  1 WL 1  to an nth word line  1 WLn and a first pair of bit lines  1   bl   1  and / 1   bl   1  to an mth pair of bit lines  1   blm  and / 1   blm . Also, there are (L+1) number of bit line sense amplifier blocks for amplifying sensed data of a pair of bit lines inputted in a voltage level, i.e., a first bit line sense amplifier block  50  to an (L+1)th bit line sense amplifier block  90 L. Especially, each of the (L+1) number of bit line sense amplifier blocks is arranged correspondingly in between the each two of the Lth number of memory cell array blocks. Each of the (L+1) number of bit line sense amplifier blocks includes m number of bit line sense amplifiers. For instance, the first bit line sense amplifier block  50  includes a first bit line sense amplifier  1 SA 1  to an mth bit line sense amplifier  1 SA(m). 
   If one of the word lines, e.g., the first word line  1 WL 1  of the first memory cell array block  10  is activated, the first bit line sense amplifier block  50  and the second bit line sense amplifier block  60  of the memory cell array block  10  that includes the activated first word line  1 WL 1  amplify voltage levels of the corresponding pairs of bit lines, in this case, the first pair of bit lines to the mth pair of bit lines ( 1   bl   1 , / 1   bl   1 ,  1   bl   2 , / 1   bl   2 , . . . ,  1   blm , / 1   blm ) to which data are inputted in response to the activated first word line  1 WL 1 . 
   That is, data of the selected memory cell array block are amplified by the corresponding bit line sense amplifier blocks disposed above and beneath the selected memory cell array block. In other words, the selected bit line sense amplifier block is shared by the respective memory cell array blocks disposed above and beneath the selected bit line sense amplifier block. This specific structure of the bit line sense amplifier is called a shared bit line sense amplifier. 
     FIG. 2  is an inner circuit diagram of conventional bit line sense amplifiers. Particularly, among m number of bit line sense amplifiers of a third bit line sense amplifier block  70 , a first bit line sense amplifier  3 SA 1  and a second bit line sense amplifier  3 SA 2  shown in  FIG. 1  are selected as an example. Herein, the first bit line sense amplifier  3 SA 1  and the second bit line sense amplifier  3 SA 2  of the third bit line sense amplifier block  70  are denoted with reference numerals  71  and  72 , respectively. 
   As shown in  FIG. 2 , the first bit line sense amplifier  71  senses and amplifies voltage levels of first pairs of bit lines  1   bl   1 , / 2   bl   1  and  3   bl   1 , / 3   bl   1  connected with a top memory cell array block  210  and a bottom memory cell array block  240 , respectively. Therefore, when the top memory cell array block  210  is activated, a bottom bit line control signal bisl is inactivated, thereby blocking data of the bottom memory cell array block  240  from being inputted. The second bit line sense amplifier  72  has the same arrangement and connection to those of the first bit line sense amplifier  71 . 
   Meanwhile, in a conventional DRAM, one selected bit line sense amplifier amplifies voltage levels of each one pair of bit lines of the top memory cell array block and the bottom memory cell array block and thus, one bit line sense amplifier is placed in between two pairs of bit lines each pair belonging to the different memory cell array blocks. As a result, the bit line sense amplifier is placed within a limited area, thereby delaying a processing time for sensing and amplifying voltage levels of bit line pairs. That is, a sensing speed of the bit line sense amplifier is determined by a width of a transistor included in the bit line sense amplifier. As the occupying area of the bit line sense amplifier decreases, the width of the transistor decreases, thereby degrading performance of the bit line sense amplifier. 
   SUMMARY OF THE INVENTION 
   It is, therefore, an object of the present invention to provide a semiconductor memory device capable of improving an operation speed of sensing and amplifying a voltage level of a bit line by giving a layout that allows a width of a transistor of a bit line sense amplifier to be widened approximately twice. 
   In accordance with an aspect of the present invention, there is provided a semiconductor memory device, including: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying means coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying means in response to a control signal. 
   In accordance with another aspect of the present invention, there is provided a semiconductor memory device, including: a plurality of memory cell array blocks including a first bit line pair and a second bit line pair neighbored with each other; a first bit line sense amplifying means being disposed between a first memory cell array block and a second memory cell array block allocated in proximity among the plurality of memory cell array blocks and serving a role in sensing and amplifying a voltage level of a bit line pair selected one of each first bit line pair of the first memory cell array block and the second cell array block and each second bit line pair of a third memory cell array block and a fourth memory cell array block disposed adjacent to a top portion of the first memory cell array block and to a bottom portion of the second memory cell array block, respectively; and a second bit line sense amplifying means being disposed in a top portion of the third memory cell array block and serving a role in sensing and amplifying a voltage level of one bit line pair selected from a first bit line pair of the third memory cell array block and a second bit line pair of the first memory cell array block. 
   In accordance with still another aspect of the present invention, there is provided a semiconductor memory device, including: a plurality of pairs of bit lines extending in parallel in a column direction; a plurality of word lines extending in parallel in a row direction; a plurality of memory cell array blocks each having a predetermined number of the word lines; and a plurality of sense amplifier array blocks each disposed between the adjacent memory cell array blocks and having sense amplifiers each arranged for every four bit line pairs in view of a plane level. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram showing how bit lines and bit line sense amplifiers of memory cell array blocks are arranged and connected with each other in a conventional dynamic random access memory device; 
       FIG. 2  is an inner circuit diagram of the selected bit line sense amplifier shown in  FIG. 1 ; 
       FIG. 3  is a block diagram showing how bit lines and bit line sense amplifiers of memory cell array blocks are arranged and connected with each other in accordance with the present invention; 
       FIG. 4  is an inner circuit diagram of a bit line sense amplifier in accordance with the present invention; and 
       FIG. 5  is a graph showing a simulation result on a voltage change of bit line sense amplifiers in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   A semiconductor memory device for sensing and amplifying a voltage of a bit line in high speed in accordance with a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. 
     FIG. 3  is a block diagram showing how bit lines and bit line sense amplifiers of memory cell array blocks in a dynamic random access memory device (DRAM) are arranged and connected with each other in accordance with the present invention. 
   As shown, the DRAM includes L number of memory cell array blocks, i.e., a first memory cell array block  100  to an Lth memory cell array block  400 L. The L number of memory cell array blocks includes n number of word lines and m number of bit line pairs. Herein, L, n and m are positive numbers. For instance, the first memory cell array block  100  includes a first word line  1 WL 1  to an nth word line  1 WLn and a first pair of bit lines  1   bl   1  and / bl   1  to an mth pair of bit lines  1   blm  and / 1   blm . Also, there are (L+1) number of bit line sense amplifier blocks for sensing and amplifying voltage levels of bit line pairs (bl 1 , /bl 1 , bl 2 , /bl 2 , . . . , blm, /blm) included in each two of memory cell array blocks disposed above and beneath the selected bit line sense amplifier block. That is, there are a first bit line sense amplifier block  500  to an (L+1)th bit line sense amplifier block  900 L. 
   Also, a second pair of bit lines ( 1   bl   2 , / 1   bl   2 ) of the first memory cell array block  100  and a second pair of bit lines ( 2   bl   2 , / 2   bl   2 ) of the second memory cell array block  200  are wired with overlapped portions with each other and thus, these mentioned pairs of bit lines are denoted with different lines to distinguish these mentioned pairs of bit lines from each other. That is, in respect of a cross-sectional view, these mentioned pairs of bit lines  1   bl   2 , / 1   bl   2  and  2   bl   2 , / 2   bl   2  are connected to the corresponding bit line sense amplifiers in different layers through a first interconnection wire and a second interconnection wire, respectively. 
   Next, the arrangement of the first bit line sense amplifier block  500  to the (L+1)th bit line sense amplifier block  900 L are explained based on one exemplary bit line sense amplifier block. Herein, the third bit line sense amplifier block  700  is selected as the exemplary arrangement. Each of the first memory cell array block  100  to the Lth memory cell array block  400 L includes the first pair of bit lines bl 1  and /bl 1  and the second pair of bit lines bl 2  and /bl 2 . 
   The third bit line sense amplifier block  700  is placed between the second memory cell array block  200  and the third memory cell array block  300  and includes a number of bit line sense amplifiers  3 SA 1  to  3 SA(m/2) for sensing and amplifying voltages of the selected pair of bit lines among the first pair of bit lines  2   bl   1  and / 2   bl   1  of the second memory cell array block  200 , the first pair of bit lines  3   bl   1  and / 3   bl   1  of the third memory cell array block  300 , the second pair of bit lines  1   bl   2  and / 1   bl   2  of the first memory cell array block  100  disposed adjacently in an upper portion of the second memory cell array block  200 , and the second pair of bit lines  4   bl   2  and / 4   bl   2  of the fourth memory cell array block  400  disposed adjacently in a bottom portion of the third memory cell array block  300 . 
   In other words, it is necessary to have each two bit line sense amplifier blocks in top and bottom portions of the memory cell array block having an activated word line in order to sense and amplify the voltage level of the bit line pair as the word line is activated. 
   However, the first memory cell array block  100  includes one bit line sense amplifier block in a top position, i.e., the first bit line sense amplifier block  500  and two bit line sense amplifier blocks in a bottom position, i.e., the second bit line sense amplifier block  600  and the third bit line sense amplifier block  700 . Thus, the first memory cell array block  100  has one less top bit line sense amplifier block. As a result, this shortage of the top bit line sense amplifier block is compensated by employing conventional shared bit line sense amplifiers  1 SA_SH 1 ,  1 SA_SH 2 , . . . ,  1 SA_SH(m/2). Identically, the Lth memory cell array block  400 L disposed in the bottom most position employs the conventional shared bit line sense amplifiers LSA_SH 1 , LSA_SH 2 , . . . , LSA_SH(m/2). 
   Meanwhile, In comparison with the conventional bit line sense amplifiers, the number of bit line sense amplifiers in accordance with the present invention is one half of the bit line sense amplifiers of the first to the (L+1)th bit line sense amplifier blocks shown in  FIG. 1 . 
   In detail, if one word line, e.g., the third world line  3 WL 1 , is activated, the second and the third bit line sense amplifier blocks  600  and  700  and the fourth and the fifth bit line sense amplifier blocks  800  and  900  disposed respectively in top and bottom of the third memory cell array block  300  having the activated word line  3 WL 1  sense and amplify voltages of a number of bit line pairs (bl 1 , /bl 1 , . . . , bl 4 , /bl 4 , . . . , bln, /bln). As a result, compared with the use of conventional bit line sense amplifiers, the number of the bit line sense amplifiers can be decreased by half. 
   As a reference, since the bit line sense amplifiers in accordance with the present invention amplify data of the memory cell array blocks in extended ranges, these bit line sense amplifiers are called modified extended sense amplifiers. 
     FIG. 4  is an inner circuit diagram of a bit line sense amplifier in accordance with the present invention. Herein, the second bit line sense amplifier  3 SA 2  of the third bit line sense amplifier block  700  is exemplified. 
   As shown, the second bit line sense amplifier  3 SA 2  has a first switch block  410 , a second switch block  440 , and bit line sense amplifying unit  720 . The bit line sense amplifying unit  720  is connected with two pairs of the bit lines  2   b   15 , / 2   b   15  of the second memory cell away block  200  and  1   b   16 , / 1   b   16  of the first memory cell array block  100 , and with two pairs of the bit lines  4   b   16  and / 4   b   16  of the four memory cell array block  400 , and  3   b   15  and / 3   b   15  of the third memory cell away block  300  by the first and second switch blocks  410  and  440  to thereby sense and amplify voltage levels of these connected pairs of the bit lines  1   b   16  and / 1   b   16 ,  2   b   15  and / 2   b   15 ,  4   b   16  and / 4   b   16 , and  3   b   15  and / 3   b   15 . 
   The bit line sense amplifying unit  720  senses and amplifies voltage levels of nodes to which the above pairs of the bit lines  2   b   15  and / 2   b   15 ,  1   b   16  and / 1   b   16 ,  4   b   16  and / 4   b   16 , and  3   b   15  and / 3   b   15  are connected. Therefore, to prevent amplified signals from being inputted simultaneously to the node, the pair of bit lines connected to the node is selected through switches in the first switch blocks  410  and  440  controlled by isolation signals bislt, bisrt, bislb and bisrb. 
   As described above, the bit line sense amplifying unit  720  is disposed between four pairs of the bit lines. Hence, an overall area of the memory cell away block does not increase; however, areas of P-channel metal oxide semiconductor (PMOS) transistors and N-channel metal oxide semiconductor (NMOS) transistors which are configuration devices of an actual bit line sense amplifier increase. As a result, it is possible to rapidly sense and amplify data of the bit lines. 
     FIG. 5  is a graph showing a simulation result on a voltage change of bit line sense amplifiers in accordance with the present invention. In  FIG. 5 , ‘sa0’ represents a voltage of a conventional bit line sense amplifier that amplifies two pairs of bit lines, and ‘sa0-2’ represents a voltage of a bit line sense amplifier proposed by the present invention that amplifies four pairs of bit lines. 
   According to the graph shown in  FIG. 5 , it is confirmed that the bit line sense amplifier proposed by the present invention much rapidly senses and amplifies data of memory cell array blocks. 
   In accordance with the present invention, one bit line sense amplifier is allowed to sense and amplify four pairs of the bit lines of the different memory cell array blocks. Therefore, in a plane level, arrangement of one bit line sense amplifier per four pairs of the bit lines is obtained. As a result of this specific arrangement, a layout area of the sense amplifiers is widened, and this widened area further causes an area of MOS transistors which are configuration devices of the bit line sense amplifiers to be increased. Accordingly, it is possible to sense and amplify voltage levels of the bit lines in high speed. 
   The present application contains subject matter related to the Korean patent application No. KR 2004-0022180, filed in the Korean Patent Office on Mar. 31, 2004, the entire contents of which being incorporated herein by reference. 
   While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.