Abstract:
A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The remaining delay lines are each composed of different numbers of variable delay units to provide respective clock signals having different phases, but they do not include any of the fixed delay units. The first and a last delay line receive an input clock signal. Each of the remaining delay lines are coupled to an output of one of the fixed delay units depending on the number of variable delay units in the delay line so that the resulting clock signals have all been delayed the same number of fixed delay periods.

Description:
TECHNICAL FIELD  
       [0001]     This invention relates to clock generating systems and methods, and, more particularly, to a delay-lock loop and method for generating a multi-phased clock signal having a maximum operating frequency that is not limited by the minimum delay of voltage-controlled delay units used in the delay-lock loop.  
       BACKGROUND OF THE INVENTION  
       [0002]     Periodic digital signals are commonly used in a variety of electronic devices. Probably the most common type of periodic digital signals are clock signals that are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a clock or data strobe signal. More specifically, read data signals are typically coupled from a memory device in synchronism with a read data strobe signal. The read data strobe signal typically has the same phase as the read data signals, and it is normally generated by the same memory device that is outputting the read data signals. Write data signals are typically latched into a memory device in synchronism with a write data strobe signal. The write data strobe signal should have a phase that is the quadrature of the write data signals so that a transition of the write data strobe signal occurs during a “data eye” occurring at the center of the period in which the write data signals are valid. The write strobe signal is typically generated by the memory controller from an internal clock signal that is derived from the system clock signal, and it is coupled to the memory device into which the data are being written. Unfortunately, the phase of the system clock signal is normally substantially the same as the phase of the write data signals. Therefore, it is necessary for the memory controller to generate the write data strobe signal as a quadrature signal having a phase that is 90-degrees relative to the phase of the internal clock signal. In other cases, a quadrature clock signal used for latching write data is generated in the memory device to which the data are being written. The quadrature clock signal is typically generated in the memory device from an internal clock signal that is also derived from the system clock signal.  
         [0003]     Various techniques can be used and have been used by memory controllers and memory devices to generate a quadrature clock signal or write data strobe signal. If the frequency of the internal clock signal is fixed, a quadrature write strobe signal can be generated by a timing circuit that simply generates a transition of the write strobe signal a fixed time after a corresponding transition of the internal clock signal. However, synchronous memory devices are typically designed and sold to be operated over a wide range of clock frequencies. Therefore, it is generally not practical to use a fixed timing circuit to generate a write data strobe signal from the internal clock signal. Instead, a circuit that can adapt itself to an internal clock signal having a range of frequencies must be used.  
         [0004]     Multi-phase clock signals are also required for applications other than for use as a write data strobe signal. For example, a “frequency doubler” circuit, which generates an output clock signal having twice the frequency of an input clock signal, can be implemented using an appropriate logic circuit that receives the input clock signal and quadrature versions of the input clock signal.  
         [0005]     One conventional circuit that can generate multi-phase clock signals from an internal clock signal having a variable frequency is a delay-lock loop, such as the delay-lock loop  10  shown in  FIG. 1 . The delay-lock loop includes a tapped delay line  14  having four variable delay units (“VDUs”)  16 ,  18 ,  20 ,  22  coupled in series with each other. Each of the VDUs  16 - 22  has an input, an output, and a control input “C”. Each of the VDUs  16 - 22  couples a digital signal from its input I to its output with a delay corresponding to a delay control signal applied to its control input C. The input of the initial VDU  16  receives an internal clock signal iCLK. The outputs of all but the last VDU  22  is coupled to the input of the subsequent VDU  16 - 20 . The output of each VDU  16 - 22  also forms a respective tap of the delay line  14  to provide four clock signals, CLK 1 -CLK 4 . As explained in greater detail below, the voltage-controlled delay provided by each of the VDUs  16 - 22  is composed of two components; a variable delay t v  having a magnitude set by the control signal C and a fixed intrinsic delay t i , which is the minimum delay by which a signal can be coupled through the VDU. The delay D of each of the VDUs  16 - 22  is thus defined by the formula: 
 
 D=D   I   +D   V . 
 
 The total delay D T  of the delay line  14 , i.e., the delay of the CLK 4  signal relative to the iCLK signal, is thus given by the formula: 
 
 D   T =4 D   I +4 D   V . 
 
         [0006]     The CLK 4  signal generated at the output of the final VDU  22  is also applied to one of two inputs to a phase detector (“PD”)  26 . The other input of the phase detector  26  receives the same iCLK signal that is applied to the input of the VDU  16 . In operation, the phase detector  26  generates an error signal “E” at its output that is indicative of the lead or lag phase error of the CLK 4  signal relative to the iCLK signal. The error signal E is applied to a VDU control unit  28 , which generates a control signal that is applied to the control terminal C of the VDUs  16 - 22 . The control signal adjusts the delay of the VDUs  16 - 22  to minimize the error signal and hence the phase error between the iCLK signal and the CLK 4  signal. Therefore, the delays of the VDUs  16 - 22  are automatically adjusted until the phase of the iCLK signal is substantially equal to the phase of the CLK 4  signal.  
         [0007]     The operation of the delay-lock loop  10  will further be explained with reference to  FIG. 2 . The iCLK signal shown in the upper waveform is coupled through the first VDU  16  to produce the CLK 1  signal shown in the second waveform of  FIG. 2 . The transition of the iCLK signal that produces the corresponding transition of the CLK 1  signal are circled and linked to each other by a line in  FIG. 2 . Similarly, the indicated transition of the CLK 1  signal is coupled through the VDU  18  to produce the indicated transition of the CLK 2  signal, the indicated transition of the CLK 2  signal is coupled through the VDU  20  to produce the indicated transition of the CLK 3  signal, and the indicated transition of the CLK 3  signal is coupled through the final VDU  22  to produce the indicated transition of the CLK 4  signal. As previously explained, the delays of the VDUs  16 - 22  are automatically adjusted so that the iCLK signal has substantially the same phase at the CLK 4  signal, which can be seen by comparing the iCLK signal shown in the top waveform of  FIG. 2  to the CLK 4  signal shown in the bottom waveform. All of the VDUs  16 - 22  are substantially identical to each other and they receive the same control signal so that they each provide the same delay. As can be observed from  FIG. 2 , since there are four VDUs  16 - 22  that together delay the iCLK signal by 360 degrees, each of the VDUs  16 - 22  delay the digital signal applied to its input by 90 degrees. The CLK 1  signal thus has a phase of 90 degrees relative to the iCLK signal, the CLK 2  signal thus has a phase of 180 degrees relative to the iCLK signal, the CLK 3  signal has a phase of 270 degrees relative to the iCLK signal, and the CLK 4  signal has the same phase as the iCLK signal.  
         [0008]     The delay-lock loop  10  shown in  FIG. 1  performs well over a wide range of frequencies in many instances. However, as will be explained with reference to  FIGS. 3A and 3B , its high frequency range is limited by the intrinsic delay D I  of each of the VDUs  16 - 22 . With reference to  FIG. 3A , as previously explained, each transition of the CLK 4  signal is delayed from the corresponding edge of the iCLK signal by a total delay D T  that is equal to the sum of the voltage-controlled delay V T  and the intrinsic delay I T . Each of these delays V T  and V I  are shown in  FIG. 3A . The period P of the iCLK signal is equal to the total delay, i.e., 4D V +4D I , and the frequency of the iCLK signal is the reciprocal of its period P, i.e., 1/(4D V +4D I ). For example, if 4D V  is equal to 4 ns and 4D I  is equal to 1 ns, the frequency of the iCLK signal is 200 MHz, i.e., 1/(5*10 −9 ).  
         [0009]     The delay lock loop  10  can continue to lock the CLK 4  signal to the iCLK signal increases by simply reducing the magnitude of the voltage-controlled delay 4D V  to reduce the total delay D T . However, as shown in  FIG. 3B , as the frequency of the iCLK signal continues to increase, the voltage-controlled delay D V  is eventually reduced to zero. At this point, the total delay D T  can no longer be reduced because the intrinsic delay D I  is fixed. The maximum frequency of the iCLK signal to which the CLK 4  signal can be locked to using the delay-lock loop  10  is thus the reciprocal of 4D I . Using the above example in which the total intrinsic delay 4D I  is 1 ns, the maximum frequency of the iCLK signal is 1 GHz.  
         [0010]     The fixed intrinsic delay of delay lines used in conventional delay-lock loops can therefore severely limit the frequency range over which delay-lock loops can be used. There is therefore a need for a delay-lock loop having a frequency range that is not limited by the intrinsic delay of conventional delay lines.  
       SUMMARY OF THE INVENTION  
       [0011]     A delay-lock loop is used to generate a plurality of clock signals having predetermined phases relative to each other using an input clock signal. The system and method includes at least three delay lines. A first delay line delays the input clock signal by a delay of D F  to generate a first clock signal, where D F  is a fixed delay time. A second delay line delays the input clock signal by a delay of D F +MD V  to generate a second clock signal. The delay D V  is a variable delay time corresponding to a control signal applied to the second delay line, and M is the ratio of the phase of the second clock signal relative to the phase of the first clock signal. A third delay line delays the input clock signal by a delay of D F +D V ; to generate a third clock signal. A phase detector compares the phase of the first clock signal with the phase of the third clock signal. Based on this comparison, the phase detector being generates the control signal. Portions of the delay lines may be common to each other, and the delay-lock loop may include an additional number of delay lines using a different number for M to generate additional clock signals having different phases.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a block diagram of a typical delay-lock loop of conventional design.  
         [0013]      FIG. 2  is a timing diagram showing the operation of the delay-lock loop of  FIG. 1 .  
         [0014]      FIGS. 3A and 3B  are timing diagram illustrating the manner in which the frequency range of the delay-lock loop of  FIG. 1  is limited by the intrinsic delay of a delay line used in the delay-lock loop.  
         [0015]      FIG. 4  is a block diagram of a delay-lock loop according to one embodiment of the invention.  
         [0016]      FIG. 5  is a timing diagram showing the operation of the delay-lock loop of  FIG. 1 .  
         [0017]      FIG. 6  is a block diagram of a delay-lock loop according to another embodiment of the invention.  
         [0018]      FIG. 7  is a block diagram of a delay-lock loop according to still another embodiment of the invention.  
         [0019]      FIG. 8  is a block diagram of a duty cycle correction circuit using the multi-phase clock signals generated by the delay-lock loops of  FIG. 4, 6  or  7  or a delay-lock loop according to some other embodiment of the invention.  
         [0020]      FIG. 9  are timing diagrams showing the operation of the duty cycle correction circuit of  FIG. 8 .  
         [0021]      FIG. 10  is a block diagram of a frequency doubler circuit using the multi-phase clock signals generated by the delay-lock loops of  FIG. 4, 6  or  7  or a delay-lock loop according to some other embodiment of the invention.  
         [0022]     FIGS.  11 A-H are timing diagrams showing the operation of the frequency doubler circuit of  FIG. 10 .  
         [0023]      FIG. 12  is a block diagram of a memory device using multi-phase clock signals generated by the delay-lock loop of  FIG. 4, 6  or  7  or a delay-lock loop according to some other embodiment of the invention.  
         [0024]      FIG. 13  is a block diagram of a processor-based system using the memory device of  FIG. 12 .  
     
    
     DETAILED DESCRIPTION  
       [0025]     One embodiment of a delay-lock loop  40  for generating multi-phase clock signals is shown in  FIG. 4 . The delay-lock loop  40  receives the internal clock signal iCLK, and couples it through four paths  42 ,  44 ,  46 ,  48 , which generate CLK 1 , CLK 2 , CLK 3  and CLK 4  signals, respectively. The first path  42  includes four series coupled VDUs  50   a - d,  which have their control input coupled to a voltage to provide a zero voltage-controlled delay D V . The VDUs  50   a - d  thus each provide a delay of only the intrinsic delay D I , and they are therefore designated by the nomenclature VDUi  50   a - d.  The final VDUi  50   d  outputs a CLK 0  signal, which is delayed by four times the intrinsic delay of each VDUi  50   a - d,  i.e., 4D I .  
         [0026]     The output from the next-to-last VDUi  50   c  is coupled through a VDU  54   a,  which generates a CLK 1  signal. The VDU  54   a  delays the signal from the output of the VDUi  50   c  by the sum of the voltage controlled delay D V  and the intrinsic delay D I . As a result, the CLK 1  signal is delayed form the iCLK signal by four intrinsic delays and one variable delay, i.e., 4D I +D V . In a similar manner, the iCLK signal is coupled through the VDUi  50   a,  the VDUi  50   b,  and two VDUs  56   a,b  to generate the CLK 2  signal. The CLK 2  signal is therefore delayed from the iCLK signal by four intrinsic delays and two variable delays, i.e., 4D I +2D V . The iCLK signal is coupled through only one VDUi  50   a  and three VDUs  58   a,b,c  to generate the CLK 3  signal. The CLK 3  signal is therefore delayed from the iCLK signal by four intrinsic delays and three variable delays, i.e., 4D I +3D V . Finally, the CLK 4  signal is generated by coupling the iCLK signal through four VDUs  60   a - d  so that it is delayed from the iCLK signal by four intrinsic delays and four variable delays, i.e., 4D I +4D V . The delay of each of the clock signals CLK 0  relative to the iCLK signal is summarized in the following Table 1:  
                           TABLE 1                                   Signal   Delay                           CLK0   4D I             CLK1   4D I  + D v             CLK2   4D I  + 2D v             CLK3   4D I  + 3D v             CLK4   4D I  + 4D v                        
 
         [0027]     The CLK 0  signal and the CLK 4  signal are applied to a phase detector PD  64 , which may be the same as the phase detector  26  used in the conventional delay-lock loop  10  of  FIG. 1 . Finally, the delay-lock loop  40  includes a VDU control unit  68  that receives an error signal E from the phase detector  64 . The VDU control unit  68  may also be the same as the VDU control unit  28  used in the conventional delay-lock loop  10  of  FIG. 1 . The phase detector  64  and the VDU control unit  68  operate alone and together in the same manner as described above for the phase detector  26  and VDU control unit  60  used in the conventional delay-lock loop  10  of  FIG. 1 . As a result, the phase of the CLK 0  signal is locked to the phase of the CLK 4  signal, as shown in  FIG. 5 .  
         [0028]     It can be seen from  FIG. 5  that the CLK 0  signal is delayed from the iCLK signal by the sum of the intrinsic delays of the  50   a - d,  i.e., by 4D I . As also shown in  FIG. 5 , the CLK 1  signal is delayed from the iCLK signal by 4Di+D V  so that it is delayed from the CLK 0  signal by 90 degrees. The CLK 2  signal is delayed from the iCLK signal by 4Di+2D V  so that it is delayed from the CLK 0  signal by 180 degrees. The CLK 3  signal is delayed from the iCLK signal by 4Di+3D V  so that it is delayed from the CLK 0  signal by 270 degrees. Finally, the CLK 4  signal is delayed from the iCLK signal by 4Di+4D V  so that it is delayed from the CLK 0  signal by 360 degrees. The CLK 1 -CLK 4  signals are thus quadrature signals having transitions that are delayed from transitions of the iCLK signal by 4D I .  
         [0029]     The phase detector  64  ensures that the phase of the CLK 0  signal is equal to the phase of the CLK 4  signal delayed by 360 degrees. Thus, 4D I +360 must equal 4D I +4D V , which requires that 4D V =360 thereby making D V =90. Significantly, the only requirement for the delay-lock loop  40  to operate is that it must be possible to reduce the voltage-controlled delay D V  enough so that it is equal to one-quarter period of the iCLK signal. Since the voltage-controlled delay D V  can be reduced to zero, the frequency of the iCLK signal can theoretically be infinity, although the components in the delay-lock loop  40  would be unable to operate above some frequency. However, the frequency limit of the delay-lock loop  40  is not limited by the intrinsic delays D I  of the VDUs. In contrast, the phase detector  26  in the convention delay-lock loop  10  of  FIG. 1  compared the CLK 4  signal (which was delayed from the iCLK signal by 4D I +4D V ) with the iCLK signal. The phase detector  26  therefore ensured that the phase of the CLK 4  signal be equal to the phase of the iCLK signal delayed by 360 degrees so that 4D I +4D V  must equal 360. As a result, even if D V  is zero, 4D I  can be equal to 360 (i.e., D I =90) only as long as the intrinsic delay D I  is less than one-quarter period of the iCLK signal.  
         [0030]     Delay-lock loops that eliminate the limitations on operating frequency caused by intrinsic delays of delay elements can also be implemented using other VDU and VDUi arrangements. For example, with reference to  FIG. 6 , a delay-lock loop  70  couples the iCLK signal through four VDU&#39;s  74   a - d  to generate the CLK 4  signal. Therefore, the CLK 4  signal has a delay from the iCLK signal of 4D I +4D V  just as in the delay-lock loop  40 . The CLK 3  signal is generated by coupling the output of the VDU  74   c  through a VDUi  76  so that it has a delay from the iCLK signal of 4D I +3D V . Similarly, the CLK 2  signal is generated by coupling the output of the VDU  74   b  through two VDUi&#39;s  78   a,b  so that it has a delay from the iCLK signal of 4D I +2D V . The CLK 1  signal is generated by coupling the output of the VDU  74   a  through three VDUi&#39;s  80   a,b,c  so that it has a delay from the iCLK signal of 4D I +D V . Finally, CLK 0  signal is generated by coupling the iCLK signal through four VDUi&#39;s  82   a,b,c,d  so that it has a delay from the iCLK signal of 4D I . The CLK 0 -CLK 4  signals thus have the same delay from the iCLK signals as the CLK 0 -CLK 4  signals generated by the delay-lock loop  40  shown in  FIG. 4 . The CLK 0  signal and CLK 4  signal are applied to the phase detector  64 , which generates an error signal E to control the VDU control unit  68  in the same manner as explained above with reference to  FIG. 4 . The delay-lock loop  70  has the advantage of using fewer VDUs compared to the delay-lock loop  40  of  FIG. 4 , but is does so by using a greater number of VDUi&#39;s.  
         [0031]     As can be seen in  FIG. 5 , although the delay-lock loop  40  generates quadrature clock signals CLK 0 -CLK 4  from the iCLK signal, the transitions of the CLK 0 -CLK 4  signals are not aligned with the transitions of the iCLK signal. Instead, they are delayed from the iCLK signal by 4D I , as previously explained. A delay-lock loop  86  according to another embodiment of the invention shown in  FIG. 7  generates quadrature clock signals CLK 0 -CLK 4  that have transitions that having any desired relationship to transitions of the iCLK signal, including being aligned with the transitions of the iCLK signal. The delay-lock loop  86  uses the delay-lock loop  40  shown in  FIG. 4 , and it operates in the same manner. However, instead of coupling the iCLK signal to the VDUs and VDUi&#39;s, the delay-lock loop first couples the iCLK signal through a VDU  88 , which may be the same as or different from the VDUs used in the delay-lock loop  40 . The VDU has a delay D I +D V  that is controlled by a VDU control unit  90 , which is, in turn, controlled by a phase detector  92 . One input of the phase detector  92  receives the iCLK signal after it has been coupled to a first delay unit  94 , which provides a fixed delay, DLY 1 . The other input of the phase detector  92  receives the CLK 0  signal after it has been coupled to a second delay unit  96 , which provides a fixed delay DLY 2  that may be equal to or different from the delay of the first delay unit  94 .  
         [0032]     The operation of the delay-lock loop  86  will be initially explained with the assumption that the delays DLY 1 , DLY 2  of the delay lines  94 ,  96 , respectively, are equal to each other. Therefore, after the CLKIN signal is delayed by the 4 VDUi&#39;s to provide the CLK 0  signal, the CLK 0  signal will have the same phase as the iCLK signal. This is accomplished by the phase detector  92  and VDU control unit  90  adjusting the delay of the VDU  88  so that it is equal to the period of the iCLK signal less 4D I .  
         [0033]     The phase relationship between the CLK 0  signal and the iCLK signal can be adjusted in any manner desired by selecting delays DLY 1 , DLY 2  of the delay lines  94 ,  96 , respectively, so that they are not equal to each other. If DLY 1  is greater than DLY 2 , the iCLK signal will lead the CLK 0  signal. If DLY 1  is less than DLY 2 , the iCLK signal will lag the CLK 0  signal.  
         [0034]     Delay-lock loops according various embodiments of the invention can be used to generate other signals, such as a duty cycle corrected signal or a multiple of the iCLK signal. For example, with reference to  FIG. 8 , the delay-lock loop  40  of  FIG. 4  may be used with a set-reset flip-flop  100  to provide a duty cycle corrected version of the iCLK signal. It can be seen from  FIG. 9  that the iCLK signal does not have a 50% duty cycle. The CLK 2  signal from the delay-lock loop  40  is applied to the set input “S” of the flip-flop  100 , and the CLK 4  signal from the delay-lock loop  40  is applied to the reset input “R” of the flip-flop  100 . As a result, the output “Q” of the flip-flop  100  transitions high responsive to the CLK 2  signal at a phase of 180 degrees relative to the transition of the “Q” output low responsive to the CLK 4  signal. The resulting signal CLK-C has the same frequency as the iCLK signal, but its duty cycle has been corrected to 50%. Although the delay-lock loop of  FIGS. 4, 6  or  7 , or a delay-lock loop according to some other embodiment of the invention, can be used to correct the duty cycle of a signal as shown in  FIGS. 8 and 9 , an embodiment of a delay-lock loop according to the present invention having only two VDUs generating only two clock signals phases 180 degrees from each other can also be used.  
         [0035]     As mentioned above, various embodiments of the invention can be used to generate clock signals having frequencies that are a multiple of the frequency of the frequency of the iCLK signal. With reference to  FIG. 10 , a frequency doubler circuit  110  uses either the delay-lock loop  40 ,  70 ,  86  shown in  FIG. 4, 6  or  7 , respectively, or some other embodiment of a delay-lock loop according to the present invention to generate four clock signals CLK 1 , CLK 2 , CLK 3 , CLK 4 , which are phased 90 degrees from each other. The frequency doubler circuit  110  further includes a pair of set/reset flip-flops  112 ,  114  that are coupled to receive the clock signals from the delay-lock loop  40 ,  70  or  86 . The first flip-flop  112  is set by the CLK 4  signal and reset by the CLK 1  signal. The clock signal CLK-A at the output of the flip-flop  112  is therefore a signal that transitions high at 360 (or 0) degrees and transitions low at 90 degrees, as shown in  FIG. 11 . Similarly, the second flip-flop  114  is set by the CLK 2  signal and reset by the CLK 3  signal. The clock signal CLK-B at the output of the flip-flop  114  is therefore a signal that transitions high at 180 degrees and transitions low at 270 degrees. The outputs of the flip-flops  112 ,  114  are combined by an OR gate  116  to generate a CLK OUT  signal that has twice the frequency of the iCLK signal. Moreover, the CLK OUT  signal will always have a 50% duty cycle.  
         [0036]     Delay-lock loops according to various embodiments of the present invention can be used for a variety of purposes in electronic devices, such as memory devices. For example, with reference to  FIG. 12 , a synchronous dynamic random access memory (“SDRAM”)  200  includes a command decoder  204  that controls the operation of the SDRAM  200  responsive to high-level command signals received on a control bus  206  and coupled thorough input receivers  208 . These high level command signals, which are typically generated by a memory controller (not shown in  FIG. 12 ), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, a column address strobe signal CAS*, and a data mask signal DQM, in which the “*” designates the signal as active low. The command decoder  204  generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these command signals will be omitted.  
         [0037]     The SDRAM  200  includes an address register  212  that receives row addresses and column addresses through an address bus  214 . The address bus  214  is generally coupled through input receivers  210  and then applied to a memory controller (not shown in  FIG. 12 ). A row address is generally first received by the address register  212  and applied to a row address multiplexer  218 . The row address multiplexer  218  couples the row address to a number of components associated with either of two memory banks  220 ,  222  depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks  220 ,  222  is a respective row address latch  226 , which stores the row address, and a row decoder  228 , which decodes the row address and applies corresponding signals to one of the arrays  220  or  222 . The row address multiplexer  218  also couples row addresses to the row address latches  226  for the purpose of refreshing the memory cells in the arrays  220 ,  222 . The row addresses are generated for refresh purposes by a refresh counter  230 , which is controlled by a refresh controller  232 . The refresh controller  232  is, in turn, controlled by the command decoder  204 .  
         [0038]     After the row address has been applied to the address register  212  and stored in one of the row address latches  226 , a column address is applied to the address register  212 . The address register  212  couples the column address to a column address latch  240 . Depending on the operating mode of the SDRAM  200 , the column address is either coupled through a burst counter  242  to a column address buffer  244 , or to the burst counter  242  which applies a sequence of column addresses to the column address buffer  244  starting at the column address output by the address register  212 . In either case, the column address buffer  244  applies a column address to a column decoder  248 .  
         [0039]     Data to be read from one of the arrays  220 ,  222  is coupled to the column circuitry  254 ,  255  for one of the arrays  220 ,  222 , respectively. The data is then coupled through a data output register  256  and data output drivers  257  to a data bus  258 . The data output drivers  257  apply the read data to the data bus  258  responsive to a read data strobe signal S R  generated by the delay line  40 ,  70  or  86 , or some other embodiments of a delay line in accordance with the present invention. The SDRAM  200  shown in  FIG. 12  is a double data rate (“DDR”) SDRAM that inputs or outputs data twice each clock period. The delay line  40 ,  70  or  86  receives the periodic iCLK signal and generates the read data strobe S R  responsive to the CLK 4  signal and the CLK 2  signal, which are generated as explained above. As a result, the read data are coupled to the data bus  258  in substantially in phase with the iCLK signal and 180 degrees from the phase of the iCLK signal or some other selected phase with respect to the iCLK signal.  
         [0040]     Data to be written to one of the arrays  220 ,  222  are coupled from the data bus  258  through data input receivers  261  to a data input register  260 . The data input receivers  261  couple the write data from the data bus  258  responsive to a write data strobe signal S W  generated responsive to CLK 1  and CLK 3  signals, which are generated by the delay-lock loop  40 ,  70  or  86  or some other embodiment of a delay-lock loop in accordance with the present invention. As a result, the write data are coupled into the SDRAM  200  from the data bus  258  at the center of a “data eye” corresponding to the phase of the iCLK signal. The write data are coupled to the column circuitry  254 ,  255  where they are transferred to one of the arrays  220 ,  222 , respectively. A mask register  264  responds to a data mask DM signal to selectively alter the flow of data into and out of the column circuitry  254 ,  255 , such as by selectively masking data to be read from the arrays  220 ,  222 .  
         [0041]     The SDRAM  200  shown in  FIG. 12  can be used in various electronic systems. For example, it may be used in a processor-based system, such as a computer system  300  shown in  FIG. 13 . The computer system  300  includes a processor  302  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor  302  includes a processor bus  304  that normally includes an address bus, a control bus, and a data bus. In addition, the computer system  300  includes one or more input devices  314 , such as a keyboard or a mouse, coupled to the processor  302  to allow an operator to interface with the computer system  300 . Typically, the computer system  300  also includes one or more output devices  316  coupled to the processor  302 , such output devices typically being a printer or a video terminal. One or more data storage devices  318  are also typically coupled to the processor  302  to allow the processor  302  to store data in or retrieve data from internal or external storage media (not shown). Examples of typical storage devices  318  include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor  302  is also typically coupled to cache memory  326 , which is usually static random access memory (“SRAM”), and to the SDRAM  200  through a memory controller  330 . The memory controller  330  normally includes a control bus  336  and an address bus  338  that are coupled to the SDRAM  200 . A data bus  340  is coupled from the SDRAM  200  to the processor bus  304  either directly (as shown), through the memory controller  330 , or by some other means.  
         [0042]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, different numbers of VDU can be used to generate any number of clock signals having any desired phase relationship to each other. Accordingly, the invention is not limited except as by the appended claims.