Abstract:
A test circuit board adapted to be used on memory slot is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Chinese Patent Application No. 201510991292.4, filed Dec. 24, 2015. 
     
    
     BACKGROUND OF THE RELATED ART 
       [0002]    Technical Field 
         [0003]    The present invention relates to a circuit board, and particularly to a circuit board adapted to be used on memory slot where a first joint test activity group (JTAG) connection interface and a second JTAG connection interface are provided to form an in-series connection between test circuit boards. 
         [0004]    Related Art 
         [0005]    For the currently available the test technologies regarding a memory slot in a board to be tested, only a single test circuit board is tested in most cases, and only a single memory slot may be tested. In this case, the issue of absence of a test signal coverage is generally arisen, lending to an unfavorable effect on the test in a production process. 
         [0006]    In view of the above, it may be known that there has long been existed in the prior art of the absence of the test signal coverage on the memory slot in the board to be tested. Therefore, there is quite a need to set forth an improvement means to settle down this problem. 
       SUMMARY 
       [0007]    In view of the issues of absence of the test signal overage of the memory slot in the board to be tested in the prior art, the present invention provides a test circuit board suitable to be used on memory slot. 
         [0008]    According to the present invention, the test circuit board adapted to be used on memory slot comprises the test circuit board, further comprising a memory connection interface, forming an electrical connection being inserted into a memory slot; a first joint test action group (JTAG) connection interface, connected electrically to a test access port (TAP) controller or connected electrically to a second JTAG connection interface of another test circuit board to form an in-series connection with the another test circuit board; a second JTAG connection interface, connected electrically to the first JTAG connection interface of the another test circuit board; a JTAG signal processing chip, connected electrically to the first and second JTAG respectively, to increase a stability of a JTAG signal of the first and second JTAGs respectively; at least a JTAG control chip, connected electrically to the JTAG processing chip, to detect a plurality of pins of the memory slot, control a state of the memory slot and simulate an Inter-Integrated Circuit (IIC) of the memory slot; at least an analog-to-digital converter (ADC) chip, connected electrically to the JTAG control chip, to be used to detect a voltage of the plurality of pins of the memory slot; a switch chip, connected electrically to the JTAG control chip and the ADC chip, to be used to detect a particular signal of the plurality of pins of the memory slot through the JTAG control chip or the ADC chip; and a voltage conversion chip, providing a work voltage required by the JTAG signal processing chip, the JTAG control chip, the ADC chip and the switch chip respectively, through the memory slot by acquiring a power supply. 
         [0009]    The test circuit board of the present invention has the difference as compared to the prior art that the first and second JTAG connection interfaces of the test circuit board may form the in-series connection therebetween to reduce a required number of TAP ports in the TAP controller, and the test circuit board provides a test signal coverage on all the test signals, facilitate a use of a production line, to further reduce a cost of the test circuit board. 
         [0010]    By using the above technical means, the present invention may achieve in the technical efficacies of a reduced required TAP number in the TAP controller and a test signal coverage on all the test signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present invention will be better understood from the following detailed descriptions of the preferred embodiments according to the present invention, taken in conjunction with the accompanying drawings, in which: 
           [0012]      FIG. 1  is a schematic diagram of an architecture of a test circuit board adapted to be used on memory slot according to the present invention; and 
           [0013]      FIG. 2  is a schematic diagram of an architecture of the test circuit board adapted to be used on memory slot in a test process according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    The present invention will be apparent from the following detailed description, The present invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements. 
         [0015]    In the following, a test circuit board adapted to be used on memory slot disclosed in the present invention will be described with reference to  FIG. 1  and  FIG. 2 .  FIG. 1  is a schematic diagram of an architecture of a test circuit board adapted to be used on memory slot according to the present invention.  FIG. 2  is a schematic diagram of an architecture of the test circuit board adapted to be used on memory slot in a test process according to the present invention. 
         [0016]    The test circuit board  10  further comprises a memory connection interface  11 , a first joint test action group (JTAG) connection interface  12 , a second JTAG connection interface  13 , JTAG signal processing chip  14 , at least a JTAG control chip  15 , at least an analog-to-digital converter (ADC) chip  16 , a switch chip  17  and a voltage conversion chip  18 . 
         [0017]    A board to be tested  20  further comprises a central processing unit (CPU)  21 , a plurality of memory slots  22  and a complex programmable logic device (CPLD)  23 . 
         [0018]    The memory connection interface  11  of the test circuit board  10  is used to insert the test circuit board  10  onto the memory slot  22  of the board to be tested  20 , to form an electrical connection between the test circuit board  10  and the board to be tested  20 . Each of the memory slots  22  may be inserted onto one test circuit board  10 . 
         [0019]    The first JTAG connection interface  12  of the test circuit board  10  is used to connect electrically to a test access port (TAP) controller  30 , or the first JTAG connection interface  12  of the test circuit board  10  is used to connect electrically to the second JTAG connection interface  13  of another test circuit board  10 , so that the test circuit board  10  may be connected in series with another test circuit board. 
         [0020]    Specifically, the board to be tested  20  has a first memory slot  221  and a second memory slot  222 . The first test circuit board  101  is inserted onto a first memory slot  221  of the board to be tested  20 . The second test circuit board  102  is inserted onto the second memory slot  222 . The first JTAG connection interface  12  of the first test circuit board  101  is connected electrically to the TAP controller  30 . The second JTAG connection interface  13  of the first test circuit board  101  is connected electrically to the first JTAG connection interface  12  of the second test circuit board  102 , so that an in-series connection may be formed between the first test circuit board  101  and the second test circuit board  102 . However, this embodiment is merely an example, without limiting the present invention. 
         [0021]    The JTAG signal processing chip  14  of test circuit board  10  is connected electrically to the first JTAG connection interface  12  and the second JTAG connection interface  13  of the test board  10 . The JTAG signal processing chip  14  of the test circuit board  10  is used to increase a stability of a JTAG signal transmitted by the first JTAG connection interface  12  of the test circuit board  10  and the second JTAG connection interface  13  of the test circuit board  10 . 
         [0022]    The board to be tested  20  of the CPU  21  is used to detect the test circuit board  10  in a boundary scan. The board to be tested  20  has a complex programmable logic device (CPLD) is used to control a power state of the board to be tested  20 . 
         [0023]    The TAP controller  30  is connected electrically to the CPU  21  of the board to be tested  20  and the CPLD  23  of the board to be tested  20 . Further, the TAP controller  30  is used to control the CPLD  23  of the board to be tested  20 , to control a state of a power supply. The test TAP controller  30  is also used to control the CPU  21  of the board to be tested  20  and the CPLD  23  of the board to be tested  20  to work in a boundary scan mode. And, the test TAP controller  30  controls the board to be tested  10  through the first JTAG connection interface  12  to work in a boundary scan mode. 
         [0024]    The JTAG control chip  15  of the test circuit board  10  is connected electrically to the JTAG signal processing chip  14 . The JTAG control chip  15  of the test circuit board  10  is used to detect a plurality of pins of the memory slot  22  of the board to be tested  20 , test a state control of the test circuit board  10  and simulate an Inter Integrated circuit (IIC) bus of the test circuit board  10 . 
         [0025]    The ADC chip  16  of the test circuit board  10  is connected electrically to the JTAG control chip  15  of the test-board  10 . The ADC chip  16  of the test circuit board  10  is used to detect a voltage on the plurality of pins  22  of the memory slot  22 . 
         [0026]    The switch chip  17  of the test circuit board  10  is connected electrically to the JTAG control chip  15  of the test circuit board  10  and the ADC chip  16  of the test circuit board  10 , respectively. The switch chip  17  of the test circuit board  10  is used to detect a particular signal on the memory slot  22  of the board to be tested, so that the particular signal may be applied for a detection on the JTAG control chip  15  or the ADC chip  16 . 
         [0027]    The voltage conversion chip  18  of the test circuit board  10  is used to acquire a power supply through the memory slot  22  of the test circuit board  10  and convert the power, so that a work voltage may be provided to the JTAG signal processing chip  14 , the JTAG control chip  15 , the ADC switch chip  16  and the switch chip  17  of the test circuit board  10 . 
         [0028]    The TAP controller  30  detects the pins of the memory slot  22  of the board to be tested  20 , control a state, simulate the IIC bus, detect a voltage of the pins of the memory slot  22  of the board to be tested  20 , and detect a particular signal of the pins of the memory slot  22  of the board to be tested  20  at the time when the PLD  23  of the board to be tested  20 , the CPU  21  of the board to be tested  20 , and the test circuit board  10  operate in a boundary scan mode, through the JTAG control chip  14  of the test circuit board  10 , the ADC chip  15  of the test circuit board  10 , and the switch chip  16  of the test circuit board  10 . 
         [0029]    In summary, the test circuit board of the present invention has the difference as compared to the prior art that the first and second JTAG connection interfaces of the test circuit board may form the in-series connection there between to reduce a required number of TAP ports in the TAP controller, and the test circuit board provides a test signal coverage on all the test signals, facilitate a use of a production line, to further reduce a cost of the test circuit board. 
         [0030]    By using the technical means of the present invention, the issues long encountered in the prior art of absence of the test signal overage of the memory slot in the board to be tested may be overcome, and the technical efficacies of a reduced required TAP number in the TAP controller and a test signal coverage on all the test signals may also be achieved. 
         [0031]    Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments, will be apparent to persons skilled in the art. It is, therefore, contemplated that the appended claims will cover all modifications that fall within the true scope of the invention.