Abstract:
A circuit including an amplifier, a transistor, and first, second and third resistances. The amplifier includes an input and an output. The amplifier receives an input signal. A cycle of the input signal includes first and second pulses. The input signal is asymmetrical such that the first pulse has a different peak magnitude than the second pulse. The transistor is connected to the input and the output. The first, second, and third resistances are each connected to the input of the amplifier. The second resistance receives a first input voltage. The third resistance receives a second input voltage. The input signal is based on the first resistance and the first and second input voltages. The amplifier corrects some asymmetry of the input signal to provide an output signal. An amount of asymmetry of the output signal is based on (i) the input signal, and (ii) a state of the transistor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present disclosure is a continuation of U.S. patent application Ser. No. 13/291,782 (now U.S. Pat. No. 8,698,555), filed on Nov. 8, 2011. This application claims the benefit of U.S. Provisional Application No. 61/415,767, filed on Nov. 19, 2010. The entire disclosures of the applications referenced above are incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    Particular embodiments generally relate to amplifiers. 
         [0003]    Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. 
         [0004]    In a read channel for a hard disk drive, a signal received from a read head of the disk drive may be asymmetric. For better performance, the symmetry of the asymmetric signal should be corrected. 
         [0005]      FIG. 1   a  depicts a graph  100  of an asymmetric signal  102  and ideal signal  104 . Ideal signal  104  includes pulses in a period that have absolute peak amplitudes that are equal and asymmetric signal  102  has pulses that have unequal absolute peak amplitudes in the period. The correction of asymmetric signal  102  is performed to correct the asymmetry of asymmetric signal to be similar to the symmetry of ideal signal  104 . 
         [0006]    One way of correcting asymmetric signal  102  is to generate a square term that increases or decreases the amplitude of asymmetric signal  102 .  FIG. 1   b  depicts a graph showing the correction. A square term  106  is combined with asymmetric signal  102  to produce an output signal  108 . However, an additional path and extra circuitry are needed to generate the square term. 
         [0007]      FIG. 2  depicts a conventional asymmetry correction circuit  200 . The gain of an amplifier  202  is set by a resistance ratio for transistor M 2  and transistor M 1  (M 2 /M 1 ). That is, the resistance of transistor M 2  divided by the resistance of transistor M 1  defines the gain. A gate voltage Vgate is tuned to determine the desired resistance for transistor M 1  and transistor M 2 . For example, the resistance of transistors M 1  and M 2  may be varied based on the gate voltage applied to the transistors. Also, a gate voltage Vmrg is varied separately for transistors MR 1  and MR 2  to provide different magneto-resistive (MR) asymmetry. 
         [0008]    The resistance of transistor M 1  may vary based on a drain-source voltage across transistor M 1 . To limit the variation, gate voltage Vgate needs to be high enough to put transistor M 1  into saturation or overdrive. Because the input voltage swing (i.e., the swing between voltages INP and INM) may be large, distortion may occur. To lower the distortion, voltage Vgate may need to be higher than a supply voltage to achieve low distortion. A charge pump may be needed to generate this voltage, which introduces additional circuitry. One way to lower the distortion is to separate transistor M 1  into multiple transistors (such as two transistors in series). However, this increases the size of the transistor and introduces parasitic capacitance at a junction M located at the input of amplifier  202 . This limits the bandwidth of amplifier  202  because the capacitance is at the second pole. Also, because the input impedance of transistor M 1  varies with the input signal swing, if a source follower is driving transistor M 1 , the output resistance of the source follower needs to be the dominant factor requiring more current than is needed to be used at that stage. 
       SUMMARY 
       [0009]    In one embodiment, an apparatus an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier, the input node receiving the asymmetric signal. A second resistance is coupled to the input node of the amplifier. The second resistance includes a linear resistor. A third resistance is coupled to the second resistance. The third resistance is varied to adjust an amount of asymmetric correction provided by the amplifier to correct the asymmetric signal at the output node. The amount of asymmetric correction is a function of the first resistance and a combination of the second resistance and the third resistance. 
         [0010]    In one embodiment, the first resistance includes a transistor. 
         [0011]    In one embodiment, the linear resistor is manufactured in polysilicon. 
         [0012]    In one embodiment, a first switch is configured to be controlled during a first interval to couple the second resistance to the third resistance to increase a gain of the amplifier to correct the asymmetric signal. The third resistance is a positive resistance. A second switch is configured to be controlled during a second interval to couple the second resistance to the third resistance to decrease the gain of the amplifier to correct the asymmetric signal. The third resistance is a negative resistance. 
         [0013]    In one embodiment, the third resistance includes a resistor divider network configured to vary the third resistance. 
         [0014]    In one embodiment, the asymmetric signal includes a positive asymmetric signal and a negative asymmetric signal. The third resistance includes: a first resistor and a second resistor coupled to the negative asymmetric signal; a third resistor and a fourth resistor coupled to the positive asymmetric signal; and a transistor coupled in between the first resistor and the second resistor and coupled in between the third resistor and the fourth resistor. 
         [0015]    In another embodiment, a method includes coupling a first resistance between an input node and an output node of the amplifier; coupling a second resistance to the input node of the amplifier, the second resistance including a linear resistor; coupling a third resistance to the second resistance; receiving an asymmetric signal at the input node; and varying the third resistance to adjust an amount of asymmetric correction provided by the amplifier to correct the asymmetric signal at the output node, wherein the amount of asymmetric correction is a function of the first resistance and a combination of the second resistance and the third resistance. 
         [0016]    The following detailed description and accompanying drawings provide a more detailed understanding of the nature and advantages of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1   a  depicts a graph of an asymmetric signal and ideal signal. 
           [0018]      FIG. 1   b  depicts a graph showing asymmetric correction. 
           [0019]      FIG. 2  depicts a conventional asymmetry correction circuit. 
           [0020]      FIG. 3  shows an example of a graph showing a differential asymmetric signal according to one embodiment. 
           [0021]      FIG. 4  depicts a system for correcting an asymmetric signal according to one embodiment. 
           [0022]      FIG. 5  depicts a simplified flowchart of a method for performing asymmetric correction according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Described herein are techniques for asymmetric correction. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
         [0024]      FIG. 3  shows an example of a graph  300  showing a differential asymmetric signal according to one embodiment. A positive asymmetric signal  302   a  and a negative asymmetric signal  302   b  form the differential asymmetric signal. Also, a positive ideal signal  304   a  and a negative ideal signal  304   b  are shown. To correct asymmetric signals  302   a  and  302   b,  the gain is boosted in the signal path for asymmetric signals  302   a  and  302   b  in odd half periods, e.g., a first T/2, a third T/2, a fifth T/2, and so on. This increases the amplitude of the asymmetric signal to be closer to the amplitude of ideal signals  304   a  and  304   b,  respectively. For example, as shown in the first T/2, the amplitude of asymmetric signal  302   a  is below that of ideal signal  304   a  and increasing the amplitude of asymmetric signal  302   a  corrects the symmetry of asymmetric signal. Also, asymmetric signal  302   b  may have the gain increased in the negative direction. 
         [0025]    Also, the amplitude of asymmetric signal  302   a  and  302   b  is above the peak amplitude of ideal signal  304   a  in the even half periods. If the signal path gain is reduced for the even half periods, e.g., a second T/2, a fourth T/2, a sixth T/2, and so on, then asymmetric signals  302   a  and  302   b  have their amplitude reduced to be closer to the amplitude of ideal signals  304   a  and  304   b.    
         [0026]      FIG. 4  depicts an asymmetry correction circuit  400  according to one embodiment. Circuit  400  may be used in a read channel to process a signal received from a read-head of a hard disk drive (HDD). However, circuit  400  may be used in other applications where correction of an asymmetric signal is required. The asymmetric signal may be received from a pre-amplifier in the read channel. A corrected signal may then be output to an analog processor, such as an analog-to-digital converter (ADC). 
         [0027]    The asymmetric signal may be received at a variable gain amplifier (VGA)  402 . In one embodiment, the asymmetric signal may be a differential asymmetric signal including a signal INP and a signal INM. When used in this disclosure, the asymmetric signal may refer to a differential version or a single-ended version. 
         [0028]    A linear resistor R 3  is used to lower distortion in asymmetry correction circuit  400 . A linear resistor may be manufactured in polysilicon. For example, a gate of a transistor is not controlled to determine the resistance of linear resistor R 3 . Also, the resistance of resistor R 3  does not vary greatly when the voltage across its terminals changes in contrast to characteristics of a transistor. For example, when a gate voltage is varied in a transistor, the resistance of the transistor varies. 
         [0029]    Amplifier  402  corrects an asymmetric signal input received at input nodes INP and INM to output the corrected signal at output nodes OUTM and OUTP. The asymmetric signal is corrected by increasing or decreasing the gain of amplifier  402 . As will be described in more detail below, the gain of amplifier  402  may be decreased by adding a negative resistance to the input resistance. Also, the gain of amplifier  402  may be increased by adding a positive resistance to the input resistance. 
         [0030]    An amount of current lasym is used to vary the asymmetry correction. For example, when a gate voltage Vmrg of a transistor MR is high, transistor MR turns on and current is conducted from the input of amplifier  402  thereby decreasing gain. When the gate voltage Vmrg is low, then transistor MR is off and the amount of current flowing into the input of amplifier  402  is increased thereby increasing gain. The amount of asymmetry correction may be varied based on the gate voltage Vmrg of transistor MR. For example, 2% asymmetry may be corrected when voltage Vmrg is high, which turns on transistor MR. A 30% asymmetry correction may be performed when Vmrg is low, which turns off transistor MR. 
         [0031]    To determine the asymmetry correction, voltage Vinp-voltage Vinm is a maximum delta input swing. Vinp is a voltage at node INP and voltage Vinm is a voltage at a node INM. The asymmetry current lasym may be defined by the current input into a terminal of amplifier  402  and is equal to: 
         [0000]      lasym=( V inp− V inm)/2 *R mrg/( R mrg* R 1 +R 2 *R 2 +R 2 *R mrg),
 
         [0000]    where Rmrg is the resistance of transistor MR. The asymmetry percentage may be defined by: 
         [0000]      Asym%=lasym/( V inp− V inm)/ R 3.
 
         [0032]    Switches SWP and SWM may be opened and closed such that at one interval both of switches SWP are closed and both of switches SWM are open. During a second interval, both of switches SWP are open and both of switches SWM are closed. 
         [0033]    For signal INP, the amount of current lasym is controlled by how much resistance is added in parallel to resistor R 3 . For example, the amount of resistance in the MR path is based on resistor R 1 , R 2 , and a resistance Rmrg of transistor MR. Resistors R 1  and R 2  may also be linear resistors. However, in other embodiments, resistors R 1  and R 2  may be nonlinear resistors. The resistance in the MR path may be positive or negative. For example, when switch SWP is on, a negative resistance is added in parallel to resistor R 3 . When switch SWM is on, a positive resistance is added in parallel to resistor R 3 . Particular embodiments vary the input resistance seen at the terminals of amplifier  402  by adding the positive resistance or the negative resistance to resistor R 3 . 
         [0034]    In one embodiment, the feedback resistance is not varied by adding resistors in parallel to transistor M 2 . This may simplify the control of which resistors are added in parallel. For example, control is needed to either add the positive resistance or negative resistance in parallel to resistor R 3 . However, no control is needed to add any resistors in parallel to transistor M 2  in conjunction with adding the positive resistance or negative resistance in parallel to resistor R 3 . 
         [0035]    As discussed above, the signal path gain may be increased for the odd half periods. For the odd half periods, switches SWP may be closed. When switches SWP are closed, a positive resistance is added in parallel to resistor R 3  to reduce the input resistance. The gain may be the resistance of transistor M 2  (RM 2 ) divided by the input resistance (Rin) (gain=RM 2 /Rin). Due to the ratio of the gain, a smaller input resistance increases the signal gain accordingly. 
         [0036]    When signal gain needs to be decreased during the even half periods, switches SWM are closed. In this case, a negative resistance is added in parallel to resistor R 3 . The negative resistance appears as a negative resistance to an input of amplifier  402 . In one embodiment, the negative resistance is the same resistance value as the positive resistance, but appears as a negative resistance to the input of amplifier  402 . Adding the negative resistance increases the input resistance, which reduces the signal gain accordingly. 
         [0037]    Accordingly, the process of increasing gain for a half period and then decreasing gain for a next half period may continue for successive half periods to correct signal asymmetry. The above also applies for the path input into the negative terminal of amplifier  402 . For example, when switch SWP is closed, the input resistance is reduced to increase the gain. When switch SWM is closed, the input resistance is increased to reduce the signal gain. The increase in gain the first half period and decrease in gain in the next half period corrects the asymmetry of signal INM. 
         [0038]    The distortion in circuit  400  mainly depends on feedback transistor M 2  due to resistor R 3  being a linear resistor (and also due to resistors R 1  and R 2  being linear resistors in some cases). This eliminates a contribution of distortion from the input resistance. Also, the resistance is fixed for resistor R 3  and a source follower is not needed that would use extra current to lower the distortion than if a transistor is used at the input. Also, no junction capacitance is associated with the linear resistors, which results in less parasitic capacitance at the input. 
         [0039]      FIG. 5  depicts a simplified flowchart  500  of a method for performing asymmetric correction according to one embodiment. At  502 , an amount of asymmetric correction needed is determined. For example, a feedback circuit is used to determine the amount of asymmetry correction needed. At  504 , the voltage at the gate of transistor MR is varied based on the amount of asymmetry correction needed. For example, the voltage may be varied to increase or decrease the asymmetry correction. 
         [0040]    At  506 , an asymmetric signal is received at amplifier  402 . At  508 , during a first time interval, the gain of amplifier  402  is increased to correct the asymmetric signal. For example, a positive resistance is coupled in parallel with resistor R 3 . This decreases the input resistance and increases the gain. 
         [0041]    At  510 , during a second time interval, the gain of amplifier  402  is decreased to correct the asymmetric signal. For example, a negative resistance is coupled in parallel to resistor R 3 . This increases the input resistance and decreases the gain. At  512 , a corrected signal is output by amplifier  402 . 
         [0042]    As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. 
         [0043]    The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims.