Abstract:
A liquid crystal display comprises a power supply, a pulse adjustment circuit, and a gate driver. The pulse adjustment circuit is connected between the power supply and the gate driver. The power supply provides power signals. The pulse adjustment circuit adjusts the plurality of pulses of the power signals or selects the appropriate voltage levels for the power signals to have cutting angles or enlarged amplitudes, whereby the influence of the feedthrough voltage on the thin film transistors of the driving circuit would be reduced so that the display quality of the liquid crystal display is improved.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 11/971,627, filed Jan. 9, 2008, which claims the benefit from the priority of Taiwan Patent Application No. 096108866 filed on Mar. 15, 2007, the disclosures of which are incorporated by reference herein in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a liquid crystal display (LCD) and a pulse adjustment circuit thereof. 
     2. Descriptions of the Related Art 
     With the rapid development of consumer electronic technology, people are becoming accustomed to using various electronic products, such as electronic multimedia products. One key component of multimedia electronic products is the display. Since liquid crystal displays (LCDs) have properties such as radiation-free, low power consumption, a plane square shape, high resolution, and stable display quality, LCDs have gradually replaced the traditional cathode ray tube displays (CRT displays). Consequently, the LCD is widely used as a display panel of electronic products such as cellular phones, display screens, digital televisions, and notebooks. 
     Generally, the LCD display panels comprise a plurality pixels arranged in an array. The display panel further comprises an active matrix driving circuit for controlling the operations of each pixel of the display panel. Each pixel comprises a thin film transistor (TFT), which functions as a switch. 
     The conventional TFT has three terminals: the gate, source and drain. The gate and source/drain of the TFT of each pixel are coupled to a scan line and a data line, and the two lines are orthogonal to each other. The active matrix display panel comprises an active matrix driving circuit which comprises a plurality of scan lines and data lines thereby. The scan line is driven by a gate driver, which is used to provide a gate signal to an associated TFT. The data line is driven by a source driver, which is used to provide data signals to the pixels. 
     To reduce the cost and the dimension of the LCD, the industrial field provides a different driving technology, mainly, the multi-switch half source driving (MSHD) technology which effectively decreases the number of source drivers to half of those in the prior art. In the conventional driving method, the charge time is determined by the width of a gate clock (GCK). When adopting MSHD technology, the charging time is reduced by half and also reduced the source to half in comparison to the conventional one.  FIG. 1A  illustrates the circuit of the conventional MSHD technology, while  FIG. 1B  is the waveform chart of a gate driving signal. The gate driving signal comprises a first pulse  11 , a second pulse  13 , and a third pulse  15 , which are repeated in order. The first pulse  11  has a longer duty cycle, while the second pulse  13  and the third pulse  15  have a shorter duty cycle. 
     In  FIG. 1A  subpixels A, B, C, D and E, are used to illustrate the principle of operation with respect to the MSHD circuit. The drains of some subpixels&#39; TFTs are connected to the data line, while the gates of these subpixels&#39; TFTs are connected to the scan lines G n , G n−1 , and G n+1 . The sources are grounded via a liquid capacitance C LC  and are connected to the drains of other subpixels. The sources of the subpixels A and C are connected to the drains of the subpixels B and D, respectively. The gates of the subpixels B and D are connected to scan lines G n−1 , and G n , respectively. The sources of subpixels B and D are grounded after connecting with the liquid capacitances C LC . In the direction parallel to the data lines, the subpixels A, C, and E are defined as odd pixels, while the subpixels B and D are defined as even pixels. 
     In  FIG. 1B , GCK stands for the clock signal of the gate driving signal. The gate driving signal, comprising the first pulse  11 , the second pulse  13 , and the third pulse  15 , requires two clock cycles of time. The positive edge of the first pulse  11  occurs at the same time with the positive edge of the clock, while the negative edge of the first pulse  11  occurs earlier than the negative edge of the clock. The positive edge of the second pulse  13  occurs at the same time with the positive edge of the next clock, while the negative edge of the second pulse  13  occurs earlier than the negative edge of the next clock. The positive edge of the third pulse  15  occurs at the same time with the negative edge of the next clock, while the negative edge of the third pulse  15  occurs earlier than the positive edge of a further next clock. The timings of both adjacent scan lines differ by one pulse cycle, which means that the positive edge of the second pulse  13  of the scan line G n−1  and the positive edge of the first pulse  11  of the scan line G n  occur at the same time, and so on. 
     The alphabets in the following table represent the subpixels which are turned on for writing, i.e. charging, a data voltage, and the bold, italicized, and underlined alphabets represent the subpixels to which the data lines the data voltages will be supplied. In  FIG. 1B , when the timing is T 1 , the gate line G n  and the gate line G n−1  are turned on simultaneously, so the subpixels A, B and E are charged at the same time. However, the voltage charged by the data line is configured to supply the subpixel B and other subpixels, and the subpixels A and E will be written in with the right voltages at following timings. 
     Furthermore, when it is at the timing T 1  to write the data onto the subpixel B via charging, the scan lines G n  and G n−1  should be at the high level. At this time, the signals that are inputted to the scan lines G n  and G n−1  are at the first pulse  11  and the second pulse  13 , respectively. When it is at the timing T 2  to write the data onto the subpixel E via charging, the scan line G n−1  should be at the high level, and the signal that is inputted to the scan line G n−1  is at the third pulse  15 . By the same analogy, the third pulse is at the high level when the data voltage is charged onto the odd subpixels, while the first pulse  11  and the second pulse  13  are at the high level when charging the data voltage to the even subpixels. The data voltage is then written to the subpixels B, E, D, A and C in the sequence according to the timings of T 1 , T 2 , T 3 , T 4 , and T 5 . 
     
       
         
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 timing 
                 T1 
                 T2 
                 T3 
                 T4 
                 T5 
               
               
                   
                   
               
             
             
               
                   
                 Charged 
                 A,           , E 
                 
                           
                 
                 A, C,            
                 
                           
                 
                 
                           
                 
               
               
                   
                 subpixel 
               
               
                   
                   
               
             
          
         
       
     
     However, the MSHD driving technology would make the feedthrough voltages of the two adjacent subpixels different, and result in the final voltage difference between the odd subpixels and the even subpixels due to the turn-on times of the TFTs  117  of the two adjacent subpixels are different, as shown in  FIG. 1C . The TFTs  117  of the odd subpixel and even subpixel are both affected by the feedthrough voltages at one time. The voltage stored in the liquid crystal capacitances C LC  of the even subpixels, however, is affected by the liquid crystal capacitances C LC  of the odd subpixels when the charging of the odd subpixels has been stopped. The voltage stored in the liquid crystal capacitances C LC  of the even subpixels is halved, while the other half of the voltage is provided to charge the liquid crystal capacitances C LC  of the odd subpixels. In the end, the final voltages of the two adjacent subpixels are different, the charged data voltages in the subpixels are different, and thus, the brightness of all the colors in the subpixels is uneven enough that the display performance is affected. 
     Consequently, it is important to decrease the feedthrough voltage difference between the adjacent subpixels and to improve the display performance of the TFT LCD which adopts the MSHD driving circuit technology. 
     SUMMARY OF THE INVENTION 
     One objective of the present invention is to provide a pulse adjustment circuit. The pulse adjustment circuit is connected between a power supply and a gate driver. The power supply provides a power signal, while the pulse adjustment circuit comprises a first switch and a discharge unit. The first switch determines a timing of power signal transmission to the gate driver in response to a first control signal. The discharge unit determines a timing of discharging the power supply signal, which has been transmitted to the gate driver. The first switch and the discharge unit are turned on alternatively. 
     Another objective of the present invention is to provide a pulse adjustment circuit. The pulse adjustment circuit is connected between a power supply and a gate driver. The power supply provides a plurality of power signals with different voltages levels, while the pulse adjustment circuit comprises a signal generator and a selector. The signal generator generates a set of control signals. The selector determines a timing of power signal transmission to the gate driver in response to the set of control signals. The power signals transmitted to the gate driver determines an amplitude of input pulse signal, where the input pulse signal comprises a first pulse, second pulse, and third pulse. At least one of the amplitudes of the first pulse and the third pulse is larger than the amplitude of the second pulse. 
     The recited pulse adjustment circuit merely utilizes a pulse adjustment circuit to change a driving waveform inputted into the driving circuit. The feedthrough voltage difference between the two adjacent subpixels is then reduced. 
     Another objective of the present invention is to provide a liquid crystal display (LCD) apparatus. The LCD display apparatus comprises the aforementioned pulse adjustment circuit, a plurality of gate drivers, and a plurality of pulse adjustment circuits. The LCD apparatus comprises the aforementioned pulse adjustment circuit for adjusting the power signal provided from the power supply to the gate drivers first and then the feedthrough voltage difference between the even sub-pixels and the odd subpixels. The picture display quality of the LCD apparatus is then improved. 
     The detailed technology and preferred embodiments implemented for the subject invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic diagram of a conventional MSHD driving circuit; 
         FIG. 1B  is a timing diagram of the conventional MSHD gate driving signal; 
         FIG. 1C  is a schematic diagram of the conventional MSHD pixel affected by a feedthrough voltage; 
         FIG. 2  is a schematic diagram of a first embodiment in accordance with the present invention; 
         FIG. 2A  is a pulse adjustment circuit schematic of the first embodiment in accordance with the present invention; 
         FIG. 2B  is a timing diagram of an unadjusted gate driving signal of the first embodiment in accordance with the present invention; 
         FIG. 2C  is a timing diagram of a plurality of adjusted gate driving signals of the first embodiment in accordance with the present invention; 
         FIG. 2D  is a timing diagram of a plurality of adjusted gate driving signals of another aspect of the first embodiment in accordance with the present invention; 
         FIG. 2E  is a timing diagram of a plurality of adjusted gate driving signals of a further aspect of the first embodiment in accordance with the present invention; 
         FIG. 3A  is a pulse adjustment circuit schematic of the second embodiment in accordance with the present invention; 
         FIG. 3B  is a schematic diagram of the second embodiment in accordance with the present invention; 
         FIG. 4A  is a pulse adjustment circuit schematic of the third embodiment in accordance with the present invention; 
         FIG. 4B  is a schematic diagram of the third embodiment in accordance with the present invention; 
         FIG. 5A  is a pulse adjustment circuit schematic of the fourth embodiment in accordance with the present invention; and 
         FIG. 5B  is a schematic diagram of the fourth embodiment in accordance with the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The feedthrough voltage is calculated based on the following equation: 
                 V   feedthrough     =         C   GD         C   GD     +     C   LC     +     C   st         ⁢   Δ   ⁢           ⁢   V       ,         
where C GD  is a stray capacitance between the gate and the drain of the TFT, C LC  is a liquid crystal capacitance, and C st  is a stay capacitance. ΔV is equal to V−V GL , where V GL  is the lowest level of the waveform of an activating signal, and V is a final voltage of the waveform of the activating signal. V feedthrough  decreases as ΔV decreases, and thus the influence of the feedthrough voltage on the subpixels is reduced. Therefore, the present invention brings up the following embodiment according to this principle.
 
     The first embodiment of the present invention is an LCD apparatus  2 , especially a TFT LCD, as shown in  FIG. 2 . The LCD apparatus  2  comprises a power supply  20 , a plurality of pulse adjustment circuits  21 , a plurality of gate drivers  22 , a plurality of source drivers  23 , and an LCD panel  24 . The LCD apparatus  2  incorporates the MSHD technology and comprises fewer source drivers. 
     The details of the structural connections of the power supply  20 , one pulse adjustment circuit, and one gate driver  22  are shown in  FIG. 2A . The pulse adjustment circuit  21  is connected between the power supply  20  and the gate driver  22 . Another end of the gate driver  22  is connected to one scan line of the active matrix driving circuit. The power supply  20  provides a power signal  202 . The power signal  202  can be a direct current (DC) voltage signal in this embodiment. The pulse adjustment circuit  21  comprises a first switch  211  and a discharge unit  213 . The discharge unit  213  comprises a resistance  215  and a second switch  217  placed in series with the resistance  215 . One end of the second switch  217  is connected to the resistance  215  while the other end of the second switch  217  is grounded. The pulse adjustment circuit  21  adjusts the level of the power signal  202 , and then the adjusted power signal  202  becomes a pulse  204  through the gate driver  22  and is transmitted to the scan line of the active matrix driving circuit. 
     The pulse  204  shown in  FIG. 2B , inputted to the scan line, comprises a first pulse  204   a , a second pulse  204   b , and a third pulse  204   c , which are repeated in order. The first pulse  204   a  has a longer duty cycle while the second pulse  204   b  and the third pulse  204   c  have a shorter duty cycle. 
     The timing of transmitting the power signal  202  to the gate driver  22  is determined in response to a first control signal S 1  by the first switch  211 . When the first control signal S 1  is at the high level, the first switch  211  is turned on and the power signal  202  is then transmitted to the gate driver  204  to form the pulse  204 . The discharge timing of the power signal  202  which is transmitted to the gate driver  22  is determined according to a second control signal S 2  by the second switch  217 . When the second control signal S 2  is at the high level, the second switch  217  is turned on. So, the power signal  202  transmitted to the gate driver  22  is discharged via the grounded resistance  215  and the power signal  202  is changed so that the power signal  202  becomes a chamfered signal. The pulse  204  formed by the gate driver  22  is adjusted to a chamfered pulse. In this embodiment, the first control signal and the second control signal are reversed in phase so that the first switch  211  and the second switch  217  are turned on alternatively. Furthermore, the duty cycle of the first control signal S 1  is much longer than that of the second control signal S 2 . 
     For each of the scan lines of the driving circuit, the front end of each scan line connects to the power supply  20 , a pulse adjustment circuit  21 , and a gate driver  22 .  FIG. 2C  shows the timing diagram of the pulses  204  inputted to the scan lines G n , G n+1 , and G n+2 . Referring to this diagram, the high level of the second control signal S 2  corresponds the ends of the first pulse  204   a  and the second pulse  204   b  of the pulse  204  inputted to each scan line. Since both the first pulse  204   a  and second pulse  204   b  are used to enable the data voltages that are used to charge to the even subpixels, the final charged voltages of the even subpixels are decreased by the influence of the second control signal S 2 . That is, the level of the power signal  202  is changed during discharge, and the pulse  204  formed by the gate driver  22  becomes a chamfered signal. Therefore, the feedthrough voltage is also decreased when ΔV is decreased to ΔV′. Furthermore, the resistance value can be adjusted to change the degree of the feedthrough voltage reduction. 
     The first switch  211  and the second switch  217  of the first embodiment may have another aspect in order to modify the feedthrough voltage of the odd subpixels. The timing diagram of the pulse  204  inputted to the scan lines G n , G n+1 , and G n+2  is shown in  FIG. 2D . The high level of the second control signal S 2  corresponds to the end of the third pulse  204   c  of each pulse of each scan line in this aspect. Since the third pulse  204   c  is used to enable the data voltage charged into the odd subpixels, the final voltage charged into the odd pixels are decreased by the influence of the second control signal S 2  of the pulse adjustment circuit  21  thereby. That is, the level of the power signal  202  is changed during discharge, and the pulse  204  formed by the gate driver  22  becomes a chamfer pulse. Therefore, the feedthrough voltage of the odd subpixels decreases with decreasing ΔV to ΔV′. 
     In the first embodiment, there is another way to turn the first switch  211  and the second switch  217  off to adjust the feedthrough voltage of the odd subpixels and the even subpixels at the same time. The timing diagram of the pulses, to be inputted to the scan lines G n , G n+1 , and G n+2 , after the adjustment are shown in  FIG. 2E . The high level of the second control signal S 2  corresponds to the ends of charging of the odd and even subpixels, i.e. the ends of the first pulse  204   a , the second pulse  204   b , and the third pulse  204   c  of each pulse  204  inputted to each scan line, in this embodiment. Because the first pulse  204   a  and the second pulse  204   b  are configured to enable the data voltage which is going to be charged in the even subpixels and the third pulse  204   c  is configured to enable the data voltage which is going to be charted into the odd subpixels, the final voltage charged in the even subpixels and the odd subpixels is decreased in response to the second control signal S 2  thereby. That is, the level of the power signal  202  is changed during discharge, and the pulse  204  formed by the gate driver  22  becomes a chamfer pulse. Therefore, the feedthrough voltage of the odd subpixels decreases with decreasing ΔV to ΔV′. 
     Referring to the aforementioned equation, V feedthrough  increases with the increase of ΔV. Since the odd subpixels are turned on with only one TFT but the even subpixels are turned on with two TFTs, the display performance of the even subpixels is worse than that of the odd subpixels. Hence, the display performance of the even subpixels can be improved by decreasing the feedthrough voltage of the even subpixels by decreasing the ΔV between the first pulse and the second pulse. Alternatively, the display performance of the odd subpixels may be decreased by increasing the feedthrough voltage of the odd subpixels by increasing the ΔV of the third pulse and the second pulse. Then, the feedthrough voltage difference between the two adjacent subpixels decreases to improve the display performance of the LCD. 
     The second embodiment of the present invention is also an LCD apparatus  2  as shown in  FIG. 2 . The details of the structural connection of the power supply  20 , a pulse adjustment circuit, and a gate driver  22  are shown in  FIG. 3A . The pulse adjustment circuit  21  is connected between the power supply  20  and the gate driver  22 . Another end of the gate driver  22  is connected to one scan line of the active matrix driving circuit. The power supply  20  provides a plurality of power signals  302 . These power signals  302  have different voltage levels. The first positive level voltage signal V 1 , second positive level voltage signal V 2 , and negative level voltage signal V 3 , wherein V 1  is 25 volts, V 2  is 18 volts, and V 3  is −6 volts. 
     The pulse adjustment circuit  21  comprises a signal generator  311  and a selector  313 . The signal generator  311  generates a set of control signals S C1  and S C2 . The selector  313  determines a timing of transmitting which of the power signals  302  to the gate driver in response to the set of control signals S C1  and S C2 . The control signal S C1  is configured to determine the timing of transmitting which of the positive level voltage signal V 1  and V 2  of the determined power signals  302  to the gate driver  22 , and the control signal S C2  is configured to determine a timing of transmitting the negative level voltage signal V 3  of the determined power signals  302  to the gate driver  22 . 
     The power signals  302  selected by the selector  313  are transmitted to the gate driver  22  to form an input pulse signal  320 . The positive level voltage of the input pulse signal  320  is selected from the first positive level voltage signal V 1  and the second positive level voltage signal V 2 , while the negative level voltage of the input pulse signal  320  is the first negative level voltage signal V 3 . The input pulse signals  320  inputted to each scan line comprise a first pulse, second pulse, and third pulse, and the amplitude of the third pulse is larger than those of the first pulse and the second pulse. Then, the input pulse signal  320  is transmitted to the scan line of the active matrix driving circuit via the gate driver  22 . 
     The timing diagram of the input pulse signals  320  inputted to the scan lines G n , and G n−1 , are shown in  FIG. 3B . Referring to this figure, the voltage level of the first positive level voltage signal V 1  is higher than that of the second positive level voltage signal V 2 . Thus, the control signal S c1  controls the selector  313  to transmit the second positive level voltage signal V 2  to the gate driver  22  when generating the first pulse and the second pulse. The control signal S C1  controls the selector  313  to transmit the first positive level voltage signal V 1  to the gate driver  22  when generating the third pulse. The amplitude of the third pulse is larger than that of the first or second pulse, and thus ΔV (18−(−6)=24) of the first pulse or the second pulse is smaller than ΔV (25−(−6)=31) of the third pulse. Since the third pulse is configured to enable the data voltage that is going to be charged in the odd subpixels and since the first and second pulses are configured to enable the data voltage that is going to be charted into the even subpixels, the feedthrough voltage difference between the even subpixels and the odd subpixels are decreased. Thus, the display performance of the even subpixels is similar to that of the odd subpixels. 
     The third embodiment of the present invention is also the LCD apparatus  2  as shown in  FIG. 2 . The details of the structural connection of the power supply  20 , a pulse adjustment circuit, and a gate driver  22  are shown in  FIG. 4A . The power supply  20  provides three kinds of direct current voltage signals, which are a second positive level voltage signal V 2 , a first negative level voltage signal V 3 , and a second negative level voltage signal V 4 , wherein V 2  is 18 volts, V 3  is −6 volts, and V 4  is −10 volts. 
     The pulse adjustment circuit  21  also comprises a signal generator  411  and a selector  413 . The signal generator  411  generates a set of control signals S C1  and S C2 . The selector  413  determines a timing to transmit which of the power signals  302  to the gate driver  22  in response to the set of control signals. The control signal S C1  is configured to determine the timing of transmitting the positive level voltage signal V 2  of the determined power signals  402  to the gate driver  22 , while the control signal S C2  is configured to determine a timing of transmitting the negative level voltage signals V 3  and V 4  of the determined power signals  402  to the gate driver  22 . 
     The power signals  402  selected by the selector  413  are transmitted to the gate driver  22  to form an input pulse signal  420 . The positive level voltage of the input pulse signal  420  is the second positive level voltage signal V 2 , while the negative level voltage of the input pulse signal  420  is selected from the first negative level voltage signal V 3  and the second negative level voltage signal V 4 . The input pulse signals  420  inputted to each scan line comprise a first pulse, a second pulse, and a third pulse, wherein the amplitude of the third pulse is larger than that of the first pulse and the second pulse. Then, the input pulse signal  420  is transmitted to the scan line of the active matrix driving circuit via the gate driver  22 . 
     The timing diagram of the input pulse signals  420  inputted to the scan lines G, and G n  and G n+1  are shown in  FIG. 4B . In this figure, the voltage level of the first negative level voltage signal V 3  is higher than that of the second negative level voltage signal V 4 . The control signal S C2  controls the selector  413  to transmit the first negative level voltage signal V 3  to the gate driver  22  when generating the first pulse and the second pulse. The control signal S C2  controls the selector  413  to transmit the second negative level voltage signal V 4  to the gate driver  22  when generating the third pulse. The amplitude of the third pulse is larger than that of the first or second pulse, an thus the ΔV (18−(−6)=24) of the first pulse or the second pulse is smaller than the ΔV (18−(−10)=28) of the third pulse. Since the third pulse is configured to enable the data voltage that is going to be charged in the odd subpixels and since the first pulse and the second pulse are configured to enable the data voltage which is going to be charted into the even subpixels, the feedthrough voltage difference between the even and odd subpixels are decreased. Therefore, the display performance of the even subpixels is similar to that of the odd subpixels. 
     The fourth embodiment of the present invention is also an LCD apparatus  2  as shown in  FIG. 2 . The details of the structural connection of the power supply  20 , a pulse adjustment circuit, and a gate driver  22  is shown in  FIG. 5A . The power supply  20  provides five kinds of direct current voltage signals, which are a first positive level voltage signal V 1 , a second positive level voltage signal V 2 , a first negative level voltage signal V 3 , a second negative level voltage signal V 4 , and a third negative level voltage signal V 5 , wherein V 1  is 25 volts, V 2  is 18 volts, V 3  is −6 volts, V 4  is −10 volts, and V 5  is 0 volts. 
     The pulse adjustment circuit  21  comprises a signal generator  511  and a selector  513 . The signal generator  511  generates a set of control signals S C1  and S C2 . The selector  513  determines a timing of transmitting the determined power signals  302  to the gate driver  22  in response to this set of control signals. The control signal S C1  is configured to determine the timing of transmitting the positive level voltage signals V 1  and V 2  of the determined power signals  302  to the gate driver  22 , and the control signal S C2  is configured to determine a timing of transmitting the negative level voltage signals V 3 , V 4 , and V 5  of the determined power signals  302  to the gate driver  22 . 
     The power signals  502  selected by the selector  513  are transmitted to the gate driver  22  to form an input pulse signal  520 . The positive level voltage of the input pulse signal  520  is selected from the first positive level voltage signal V 1  and the second positive level voltage signal V 2 , while the negative level voltage of the input pulse signal  320  is selected from the first negative level voltage signal V 3 , the second negative level voltage signal V 4 , and the third negative level voltage signal V 5 . The input pulse signals  520  inputted to each scan line comprise a first pulse, a second pulse, and a third pulse. The amplitude of the third pulse is larger than that of the first pulse and the second pulse. Then, the input pulse signal  520  is transmitted to the scan line of the active matrix driving circuit via the gate driver  22 . 
     The timing diagram of the input pulse signals  520  inputted to the scan lines G n  and G n+1  are shown in  FIG. 5B . In this figure, the voltage level of the first positive level voltage signal V 1  is higher than that of the second positive level voltage signal V 2 . The control signal S C1  controls the selector  513  to transmit the second positive level voltage signal V 2  to the gate driver  22  when generating the first pulse and the second pulse. The control signal S C1  controls the selector  513  to transmit the first positive level voltage signal V 1  to the gate driver  22  when generating the third pulse. The voltage level of the second negative level voltage signal V 4  is lower than that of the third negative level voltage signal V 5 , so the control signal S C2  controls the selector  513  to transmit the third positive level voltage signal V 5  to the gate driver  22  when generating the first pulse and the second pulse. The control signal S C2  controls the selector  513  to transmit the second negative level voltage signal V 4  to the gate driver  22  when generating the third pulse. The amplitude of the third pulse is larger than that of the first or second pulse, and thus the ΔV (18−0=18) of the first pulse or the second pulse is smaller than the ΔV (25−(−10)=35) of the third pulse. Since the third pulse is configured to enable the data voltage that is going to be charged in the odd subpixels and since the first and second pulses are configured to enable the data voltage that is going to be charted into the even subpixels, the feedthrough voltage difference between the even and odd subpixels is then decreased. Therefore, the display performance of the even subpixels is similar to that of the odd subpixels. 
     The present invention adjusts the pulse provided from the power supply to the gate driver in advance. The feedthrough voltage differences of the even subpixels and the odd subpixels are decreased to improve the display performance of the LCD apparatus. 
     The above disclosure is related to the detailed technical contents and inventive features thereof. People having ordinary skills in this field may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the appended claims.