Abstract:
A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a buffering circuit of a semiconductor memory device, and more specifically to a buffering circuit including a plurality of buffers divided into some groups, of which each group is activated independent of the other.  
         BACKGROUND OF THE INVENTION  
         [0002]    In general a number of buffers are employed for converting external signal of TTL (transistor-transistor-logic) level into internal signals of CMOS (complementary metal-oxide-semiconductor) level in a semiconductor memory device. The buffers are disposed at the terminal pads to receive the external signals such as address signals, data signals, and command/control signals.  
           [0003]    [0003]FIG. 1 shows a construction of the conventional buffering circuit in a semiconductor memory device, in which command buffers and address buffers are simultaneously disabled during a refresh operation for the purpose of reduce current consumption.  
           [0004]    Referring to FIG. 1, the buffering circuit includes refresh signal generator  10 , buffer controller  20 , command buffers group  30 , and address buffers group  40 .  
           [0005]    The refresh signal generator  10  generates refresh signal REF by receiving self-refresh signal SREF and auto-refresh signal AREF and performing a logic operation of these signals through NOR gate NOR 1 , and inverter IV 2 . The buffer controller  20  receives clock enable signal CKE from clock enable latch  21 , and then generates buffer enable signal E 1  through inverter IV 1 , NOR gate NOR 2 , and inverter IV 3 . The inverter IV 1  applies an output signal of the latch  21  into the NOR gate NOR 2  which also receives the refresh signal REF. An output signal from the NOR gate NOR 2  is converted into the buffer enable signal El through the inverter IV 3 . The command buffers group  30  includes chip selection signal buffer CSBUF (hereinafter, referred to as CS buffer), row address strobe signal buffer RASBUF (hereafter, RAS buffer), column address strobe signal buffer CASBUF (hereinafter, CAS buffer), and write enable signal buffer WEBUF (hereinafter, WE buffer). The buffers CSBUF, RASBUF, CASBUF, and WEBUF are activated in response to signal E 1   a  that is logically reversed one of the buffer enable signal E 1  through inverter IV 4 . The address buffers group  40  includes a plurality of address buffers A 1 ˜An that are enabled in response to signal E 1   b  that is logically reversed one of the buffer enable signal E 1  through inverter IV 5 . The E 1   a  and E 1   b  will be referred to as the first and second reverse signals, respectively, of the buffer enable signal E 1 .  
           [0006]    The RAS buffer, the CAS buffer, and the WE buffer within the group  30  have the same circuit architecture, except for their corresponding input signals. Hence, the circuit shown in FIG. 2 can correspond to any one of the WEBUF, RASBUF, and CASBUF. Therefore, according to a kine d of buffer input signal VINZ 1  can be replaced with one of the write enable signal, the row address strobe signal, or the column address strobe signal. Also, output signal VOUTZ 1  can be replaced with one of the write enable signal, the row address strobe signal, or the column address strobe signal. The buffer of FIG. 2 is formed of well-known differential amplifier DA 1  which becomes active in response to the first reverse signal El a  and compares the input signal VINZ 1  with reference to voltage VREF, and delay circuit DL 1 , which converts an output signal into an output signal VOUTZ 1  after reverse/delay of the output signal of the amplifier DA 1 .  
           [0007]    The address buffers A 1 ˜An within the group  40  are constructed in the same constructions with that shown in FIG. 2, exept that the differential amplifier is enabled by the second reverse signal E 1   b.    
           [0008]    [0008]FIG. 3 shows a detailed circuit architecture of the CS buffer in the command buffer group  30 , including differential amplifier DA 2 , delay circuits DL 2  and DL 3 , NOR gate NOR 3 , and inverter IV 6 . The differential amplifier DA 2 , is enabled by the first reverse signal El a , and generates an output signal of comparing input signal VINZ 2  (i.e., an external CS signal) with the reference to voltage VREF. The delay circuit DL 3  converts the output signal of the differential amplifier DA 2  into the first delay signal A, and the delay circuit DL 2  converts the buffer enable signal E 1  into the second delay signal B. The first and second delay signals A and B are applied to the NOR gate NOR 3 . An output signal of the NOR gate NOR 3  turns into output signal VOUTZ 2  (i.e., the chip selection signal) through the inverter IV 6 .  
           [0009]    Referring to FIG. 4, which describes an operation of the buffering circuit shown in FIG. 1, if there is either of the self-refresh signal SREF or the auto-refresh signal AREF which goes up to a high level, the buffer enable signal E 1  is set on a high level regardless of the state of the clock enable signal CKE.  
           [0010]    In this case, the first and second reverse signals, E 1   a  and E 1   b , are low levels, causing the differential amplifiers DA 1  and DA 2  to be disable, and thereby the output signals from the differential amplifiers DA 1  and DA 2  turn into high levels. Accordingly, the output signal of the differential amplifier DA 1  that is assigned to the CAS buffer CASBUF, the RAS buffer RASBUF, or the WE buffer WEBUF is established at a low level after passing through the delay circuit DL 1 .  
           [0011]    Meanwhile, in the CS buffer CSBUF, as the first and second delay signals A and B are applied to the NOR gate NOR 3  with low and high levels, respectively, the output signal VOUTZ 2  goes up to a high level.  
           [0012]    At the time of terminating the refresh mode, t 1  in FIG. 4, the buffer enable signal E 1  turne to a low level. In the CS buffer CSBUF, the differential amplifier DA 2  is enabled in response to the first reverse signal of high level, and then outputs an amplified signal of the input signal VINZ 2 . The delay signal DL 3  inverts and delays the output signal of the differential amplifier DA 2 , and then makes the first delay signal A.  
           [0013]    The first delay signal A is applied to the NOR gate NOR 3  together with the second delay signal B that goes to a low level after the delay time. As shown in FIG. 4, after the refresh mode is terminated at the time t 1 , the second delay signal B falls down to a low level before the CS buffer CSBUF receives the input signal VINZ 2 . As a result, around t 2  after the second delay signal B has been changed to a low level, there is a period that the output signal VOUTZ 2  has a short pulse of a low level when the input signal VINZ 2  is applied thereto with a low level that makes the first delay signal turne into a high level.  
           [0014]    In conttary, at the time t 1  finishing the refresh mode, the first reverse signal E 1  a of a high level enables the RAS buffer RASBUF, the CAS buffer CASBUF, and the WE buffer WEBUF to be conductive. As the output signal VOUTZ 1  is still held on a low level because the input signal VINZ 1  has not been transferred through the differential amplifier DA 1  and the delay circuit DL 1  even after the activation of the buffer, it may occur to put the semiconductor memory device into a state of a mode register set (MRS) when the output signal VOUTZ 2  figures out at the low pulse as shown in FIG. 4.  
           [0015]    Such an abnormal entrance into the MRS mode is not intended to be designed and thereby may cause a malfunction responding to undesirable external signals.  
           [0016]    While the undesirable entrance into the MRS is prevented in the self-refresh mode by controlling an enable timing of an internal buffer where the output signal VOUTZ is buffered therethrough to be utilized as an internal command signal in the memory device, the auto-refresh mode can not be free from the malfunction at the time of terminating as aforementioned.  
           [0017]    Although there has been various ways to overcome the improper timing with the second delay circuit DL 2 , it has limits due to large fluctuation of erroneous rates involved in operational factors such as delay timings that are physically affected by supply voltages, temperature, and variations in manufacturing process, rather it reduces operating speed in the environment of high frequency data processing.  
           [0018]    Otherwise, additional control logic circuits to regulate the malfunction would make the circuit composition complicate and increase a topological size of the memory chip.  
         SUMMARY OF THE INVENTION  
         [0019]    It is, therefore, an object of the present invention to provide a buffering circuit capable of securing reliable generation of buffered output signals.  
           [0020]    It is another object of the invention to provide a buffering circuit preventing a undesirable entrance into a mode register set mode after a refresh operation.  
           [0021]    It is still another object of the invention to provide a buffering circuit which controls activation operation of input buffers properly.  
           [0022]    In order to attain the above objects, a buffering circuit according to the present invention has a plurality of signal input buffers being divided into a multiplicity of groups. The buffers of each group are controlled by an independent enable signal.  
           [0023]    Furthermore, with distinguishing operation modes into a refresh mode and non-refresh mode, as well as the refresh mode into a self-refresh and a auto-refresh, the buffers of each group are independently conductive in accordance with a state of mode.  
           [0024]    A buffer controller uses the first refresh signal for discriminating between the refresh mode and the non-refresh mode, and the second refresh signal for designating an alternative one of various refresh modes, and then generates enable signals for the signal input buffers segmented into the multiplicity of groups.  
           [0025]    The buffer controller includes the first controller for generating the first control signal to discriminate the refresh mode from and non-refresh mode and to control the signal input buffers, and the second controller for generating the second control signal to operate the signal input buffers.  
           [0026]    The signal input buffers of an input buffer group are for example divided into two operable groups by the first and second control signals, respectively. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]    The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:  
         [0028]    [0028]FIG. 1 is a schematic circuit diagram of a conventional buffering circuit;  
         [0029]    [0029]FIG. 2 is a circuit diagram of a row address strobe signal buffer, a column address strobe signal buffer, or a write enable signal buffer all shown in FIG. 1;  
         [0030]    [0030]FIG. 3 is a circuit diagram of a chip selection signal buffer shown in FIG. 1;  
         [0031]    [0031]FIG. 4 is a timing diagram of the buffering circuit shown in FIG. 1, where there is a malfunction during an operation thereof; and  
         [0032]    [0032]FIG. 5 is a schematic circuit diagram of a buffering circuit according to a preferred embodiment of the invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0033]    It should be understood that the description of the preferred embodiment is merely illustrative and that it should not be taken in a limiting sense. In the following detailed description, several specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details.  
         [0034]    [0034]FIG. 5 shows an embodiment of a buffering circuit according to the invention. It is noted that the same circuit components between FIGS. 1 and 5 are assigned to the identical reference numerals. Referring to FIG. 5, the buffering circuit includes refresh signal generator  10 , the first buffer controller  60 , the second buffer controller  70 , the first command buffer block  80 , the second command buffer block  90 , and address buffer block  40 .  
         [0035]    The refresh signal generator  10  generates the refresh signal REF by receiving the self-refresh signal SREF and the auto-refresh signal AREF and then performing a logic operation of these signals through a NOR gate NOR 1  and inverter IV 2 . SREF and AREF are command signals to force the memory device to be put into the self-refresh mode and the auto-refresh mode, respectively. Thus, the refresh signal REF optionally selects the refresh or non-refresh modes.  
         [0036]    The first buffer controller  60  receives clock enable signal CKE through the clock enable latch  61 , and then generates the first buffer enable signal E 1  through inverter IV 7 , NOR gate NOR 5 , and inverter IV 8 . The inverter IV 7  applies an output signal of the clock enable latch  61  into the NOR gate NOR 5  which also receives the refresh signal REF. The output signal from the NOR gate NOR 5  is converted into the first buffer enable signal E 1  through the inverter IV 8 .  
         [0037]    The first buffer enable signal E 1  is applied to the second buffer controller  70 . Also, the first buffer enable signal E 1  is applied to the second command buffer block  90  and the address buffer block  100  through the inverters IV 10  and IV 11 .  
         [0038]    In the second buffer controller  70 , the auto-refresh signal AREF is applied to NAND gate ND 1 , through inverter IV 9 , together with the first buffer enable signal E 1 . The NAND gate ND 1  generates the second buffer enable signal E 2 .  
         [0039]    The auto-refresh signal AREF optionally selects the auto-refresh of self-refresh modes. The second buffer enable signal E 2  from the second buffer controller  70  is applied to the WE buffer WEBUF, the RAS buffer RASBUF, and the CAS buffer CASBUF, which are disposed in the first command buffer block  80 , in order to control their activation.  
         [0040]    The circuit constructions of the buffers WEBUF, RASBUF, and CASBUF are the same as those shown in FIG. 2.  
         [0041]    Meanwhile, the CS buffer CSBUF is independently associated to the second buffer block  90 , different from the WEBUF et al. The CS buffer CSBUF is constituted to be conductive in response to the first reverse signal E 1   a , with the same circuit architecture shown in FIG. 3.  
         [0042]    The address buffers A 1 ˜An are formed to be conductive in response to the second reverse signal E 1   b  and have the same constructions shown in FIG. 2.  
         [0043]    With respect to an operation in the buffering circuit of FIG. 5, in the non-refresh mode, as the self-refresh signal SREF and the auto-refresh signal AREF are at low levels, the refresh signal REF sets a low level in the non-refresh mode. The clock enable signal CKE is applied to the NOR gate NOR 5  through the clock enable latch  61  and the inverter IV 7 . The NOR gate NOR 5  receives the reverse signal of the clock enable signal CKE and the refresh signal REF of low level, and then generates the first buffer enable signal E 1  through the inverter IV 8 . As the refresh signal REF is at a low level, the first buffer enable signal E 1  is exclusively dependent on a logic state of the clock enable signal CKE. An output signal of the inverter IV 9  is at a high level because the auto-refresh signal AREF is held on a low level. The NAND gate ND 1  receives the output signal of the inverter IV 9 , of a high level, for example, and the first buffer enable signal E 1  responding to the clock enable signal CKE, and then generates the second buffer enable signal E 2 .  
         [0044]    As a result, it can be seen that, in the non-refresh operation mode, since the first buffer enable signal E 1  is substantially established on the clock enable signal CKE and the reverse of the first buffer enable signal E 1  is the second buffer enable signal E 2 , the signal input buffers WEBUF, RASBUF, CASBUF, CSBUF, and A 1 ˜An are controlled by the clock enable signal CKE.  
         [0045]    Otherwise, in the refresh mode, either the auto-refresh signal AREF or the self-refresh signal SREF goes up to a high level, so that the refresh signal REF is changed to a high level. The refresh signal REF of high level is applied to the NOR gate NOR 5  in the first buffer controller  60 , and thereby the first buffer enable signal E 1  is forced to be a high level regardless of the logic state of the clock enable signal CKE. The first buffer enable signal E 1  of a high level is applied to the NAND gate ND 1  of the second buffer controller  70 , and then the NAND gate ND 1  generates the second buffer enable signal E 2  of a high level in response to the reverse signal of the auto-refresh signal AREF of a high level regardless of the first buffer enable signal E 1 . Thus, the second buffer enable signal E 2 , during the refresh mode, is affected by the auto-refresh signal AREF. If the auto-refresh signal AREF is at a high or low level, the second buffer enable signal E 2  is set on a low or high level.  
         [0046]    The second buffer enable signals E 1  and E 2  are respectively applied to the first command buffer block  80  and the second command buffer block  90  in order to control activation of the buffers in their corresponding blocks.  
         [0047]    In the self-refresh mode, the first command buffer block  80 , the second command buffer block  90 , and the address buffer block  40  are disabled. On the other hand, in the auto-refresh mode, the CS buffer CSBUF in the second command buffer block  90  and the address buffers A 1 ˜An in the block  40  are disabled while the buffers WEBUF, RASBUF, and CASBUF in the first command buffer block  80  are enabled.  
         [0048]    The output signal VOUTZ 2  (shown in FIG. 3) generated from the CS buffer CSBUF is buffered to be utilized as an internal command signal within the memory device. In order to prevent a unwanted entrance into the MRS state, the self-refresh mode can be free from the timing mismatch described above by means of regulating an activation time of an internal buffer treating VOUTZ 2 . And, the abnormal timing distortion as shown in FIG. 4 even in the auto-refresh mode, instead of the timing control with the internal buffer, can be overcome by activating the WE buffer WEBUF, the RAS buffer RASBUF, and the CAS buffer CASBUF using the first buffer enable signal E 1  that is independent from the second buffer enable signal assigned to the CS buffer CSBUF, and by regulating an entrance of the input signal VINZ 1  of the first command buffer shown in FIG. 2.  
         [0049]    As described above, the invention offers an advantage of protecting a undesirable transition of an operation mode such as the MRS due to a timing distortion between command signals when the refresh mode is terminated, and of providing an easy manner to control activation of the buffers because the buffers are enabled with being divided into groups in accordance with their conduction styles.  
         [0050]    Moreover, since the present buffering circuit employs a simple logic circuit to control activation of the buffers, the operation speed may enhance rather than using a physical delay in the condition of a high frequency operation and it is available to design the buffering circuit without burden of topological difficulties.