Abstract:
In a semiconductor memory device having a plurality of memory cell arrays, data input/output terminals receive information data and operations command data and also output information data read out from the memory cell arrays. An operation command buffer temporarily stores the operation command data. In response to a control signal, an operation block controls the information data to be written into the memory cell arrays and read therefrom in a manner determined by the operation command data supplied from the operation command buffer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to semiconductor memory devices and operation executing system using the same. More particularly, the present invention relates to an improvement of operation mode for such a dynamic random access memory as having a execution block contained in one chip. 
     2. Description of the Background Art 
     For example, numbers of dynamic RAMs are used in an image processing apparatus, wherein writing and reading of image data of the dynamic RAM is controlled by a CPU. However, since operation processing in a chip is more likely to reduce a processing speed required for processing some image, an integrated circuit containing a dynamic RAM and an operation execution block in one chip has been put into practical use. 
     FIG. 13 is a schematic block diagram of such integrated circuit. Referring to FIG. 13, memory cell arrays 1-4 have memory capacity of 512 rows and 512 columns corresponding to data input/output terminals DO1-D04. Each of the memory cell arrays 1-4 has a row decoder 5, a column decoder 6 and an I/O gate 7 provided therein. Address input terminals A0-A8 receive row address (X) signals and column address (Y) signals as external address signals and also receive operation command CMD in a time divisional multiplexed manner, and then the external address signals are latched in an address buffer 9. Since address is a kind of command and different from data, the operation command CMD is input to the address input terminals A0-A8 but not to the data input/output terminals D01-D04. The row address signals latched in the address buffer 9 are applied to the row decoders 5 wherein one row is selected among 512 rows of each of the memory cell arrays 1-4, while the column address signals are applied to the column decoders 6 wherein one column is selected among the 512 columns in the memory cell array 1. Read data Mi of the selected address is applied to a operation execution block 8 through the I/O gate 7. 
     The above-described operation command CMD latched in the address buffer 9 is latched in a CMD buffer 10 and then applied to the operation block 8. The input/output terminals DO1-DO4 receive input data Di, the input data Di is latched in an input buffer 12 at each timing of signals, RAS, CAS, WB/WE and DT/OE input to control input terminals and then the latched input Di is applied to the operation block 8. The operation block 8 executes operations of the read date Mi and the input data Di latched in the input buffer 12 at the operation command CMD latched in the CMD buffer 10 and data Wi which are results of the executed operations are written in the memory cell arrays 1-4. 
     FIG. 14 is a diagram explaining a outline of an operation processing by the operation execution block in FIG. 13, FIG. 15 is a table showing the operation contents executed in the operation execution block and FIG. 16 is a timing chart showing operation processing cycles of a conventional semiconductor memory device. 
     Now, referring to FIG. 13-FIG. 16, operation of the conventional semiconductor memory device will be described. As shown in FIG. 16, in the first half of the operation command setting cycle, the operation command CMD is latched in the address buffer 9 and in the latter half of the operation executing cycle, an operation processing is performed in accordance with the latched operation command CMD, so that the data Wi of the result thereof is written in the memory cell arrays 1-4. Namely, when the row address strobe signal RAS attains the &#34;L&#34; (logical low) level, the column address strobe signal CAS attains the &#34;L&#34; level, the output enable signals DT/OE attains a &#34;H&#34; (logical high) level and the write enable signal WB/WE attains the &#34;L&#34; level, so that the operation command CMD is applied to the address input terminals A0-A8, the operation command CMD is latched in the CMD buffer 10 through the address buffer 9. At this time, write mask data is applied to the data input/output terminals DO1-DO4. 
     After the operation command is latched in the CMD buffer 10, the operation is executed in the latter half of the operation cycle as shown in FIG. 16. Namely, a predetermined address of each of the memory cell arrays 1-4 is specified by the row address strobe signal RAS and the column address strobe signal CAS, so that the read data Mi is applied to the operation block 8, and the write enable signal WB/WE attains the &#34;L&#34; level, so that the input data Di input to the data input/output terminals DO1-DO4 is latched in the input buffer 12 and then applied to the operation block 8, whereby the operation is executed in accordance with the operation command CMD. As shown in FIG. 13, the operation command CMD comprises 4 bits (A0-A3) and an AND operation and an OR operation between the read data Mi and the input data Di are executed based on whether the bit is &#34;0&#34; or &#34;1&#34;. 
     As described above, in the conventional semiconductor memory device, the operation command CMD is latched in the CMD buffer 10 in the first half of the operation command setting cycle and the operation block 8 executes the operation of the input data Di and the read data Mi in accordance with the operation command CMD in the latter half of the operation executing cycle, which makes neither setting nor execution of the operation command CMD in the same cycle possible, resulting in a longer processing time period. 
     SUMMARY OF THE INVENTION 
     Therefore, a primary object of the present invention is to provide a semiconductor memory device that allows setting and execution of operation command in the same cycle and an operation executing system using the same. 
     Briefly stated, the present invention comprises a plurality of semiconductor memory elements, address signal input terminals receiving address signals, data input/output terminals receiving write data and operation command data and outputting the data read out from the semiconductor memory elements, first and second control signal input terminals receiving first and second control signals, and a buffer temporarily storing operation command data, wherein the operation command data input to the data input/output terminals are temporarily stored in the buffer in response to a level change of the first control signal input to the first control signal input terminal, so that the data input to the data input/output terminals and the data read out from the semiconductor memory elements are operated in accordance with the operation command data stored in the buffer in response to a level change of the second control signal input to the second control signal input terminal. 
     Accordingly, in accordance with the present invention, by temporarily storing the operation command data in response to the level change of the first control signal and executing the operation of the data in response to the level change of the second control signal, it is possible to set the operation command data and perform the operation processing in the same cycle. 
    
    
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of one embodiment of the present invention. 
     FIG. 2 is an electric circuit diagram of a peripheral portion of a memory cell shown in FIG. 1. 
     FIG. 3 is a specific electric circuit diagram of an operation block shown in FIG. 1. 
     FIG. 4 is a diagram showing a function block included in the operation block showing in FIG. 3. 
     FIG. 5 is a diagram showing examples of instruction words for performing an operation processing in the function block shown in FIG. 4. 
     FIG. 6 is a specific block diagram of an input buffer, a command buffer and an output buffer shown in FIG. 1. 
     FIGS. 7 and 8 are diagrams showing operation executing cycles according to one embodiment of the present invention, and particularly, FIG. 7 shows a case where the write enable signal WB/WE is set after the fall of the column address strobe signal CAS and FIG. 8 shows a case where the write enable signal WB/WE is set before the fall of the column address strobe signal CAS. 
     FIG. 9 is a timing chart of an internal clock signal. 
     FIG. 10 is an operation timing chart according to another embodiment of the present invention. 
     FIG. 11 is a schematic block diagram showing an embodiment of an application of the present invention to a SRAM. 
     FIG. 12 is a timing chart explaining operation of the embodiment shown in FIG. 11. 
     FIG. 13 is a schematic block diagram of a conventional semiconductor memory device. 
     FIG. 14 is a diagram explaining an outline of an operation processing in an operation block shown in FIG. 13. 
     FIG. 15 is a table showing contents of the operation to be executed in the operation block. 
     FIG. 16 is a timing chart showing an operation processing cycle of the conventional semiconductor memory device. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is the schematic block diagram of one embodiment of the present invention. A semiconductor memory device shown in FIG. 1 is similarly structured to that of the above-described FIG. 13 except for the following points. Namely, while in the above-described conventional semiconductor memory device of FIG. 13, the operation command CMD is input to the address signal input terminals A0-A8, in the embodiment shown in FIG. 1, the operation command CMD is applied to the data input/output terminals DO1-DO4 and then, the operation command CMD is latched in the CMD buffer 10 through the input buffer 12. 
     FIG. 2 is the electric circuit diagram of the peripheral portion of the memory cell array shown in FIG. 1. Referring to FIG. 2, included are a gate circuit 61 receiving column address signals which are 2 of y0-y8 and CA7 or CA7 output from the address buffer 9 shown in FIG. 1 and a gate circuit 62 receiving an output of the gate circuit 61 and CA0 or CA0. 
     The I/O gate circuit 7 comprises MOS transistors 71 and 72 each having a gate receiving the output of the gate circuit 62. The MOS transistor 71 has a drain connected to an I/O line and a source connected to the sense amplifier 11 of the memory cell array 1. The MOS transistor 72 has a drain connected to an I/O line and a source connected to the sense amplifier 11. The sense amplifier 11 is connected to bit lines BL and BL, a memory transistor 12 is connected between the bit line BL and a row address signal X0 and a memory transistor 15 is connected between the bit line BL and a row address signal X1. Capacitors 13 and 14 are respectively connected between sources of the memory transistors 12 and 15 and a power supply Vcp, which constitutes a dynamic RAM having one transistor and capacitor. A MOS transistor 16 has a drain and a source connected between the bit lines BL and BL and a gate receiving a clock signal φ EQ . Furthermore, a bit line voltage V BL  is applied to the bit line BL through a MOS transistor 17. 
     FIG. 3 is the specific electric circuit diagram of the operation block shown in FIG. 1, FIG. 4 is the diagram showing the function block included in the operation block shown in FIG. 3 and FIG. 5 is the diagram showing the examples of instruction words to be operated in the function block shown in FIG. 4. 
     Referring to FIG. 3, the operation block 8 comprises a preamplifier 14, a writing driver 15 and an operation processing block 16. The preamplifier 14 is for amplifying a level difference between data I/O and I/O read out from the I/O gate 7 and includes an amplifier 141 comprised of two stages of current mirror circuits. When a clock signal φ PAE  is input, the amplifier 141 amplifies the difference between the data I/O and I/O and latches the amplified difference. The clock signal Φ PAE  is applied to the operation processing block 16 through a clocked inverter 142. 
     The operation processing block 16 includes such a function block 161 as shown in FIG. 4, wherein, after inverted in inverters 162-165, instruction commands CMD0, CMD1, CMD2 and CMD3 are input to command inputs F0, F1, F2 and F3, thereby enabling execution of 16 types of instructions as shown in FIG. 5. Furthermore, read data RDi is input to an input end Mi and it is also input to an input end Mi after being inverted in an inverter 166, and write data WDi is input to an input end Di and it is also input to an input end Di after being inverted in an inverter 167 in the function block 161. A clock signal is φ ROP   applied to the function block 161 in order to precharge a node A thereof, such that penetrating currents flowing from the function block 161 to an NAND gate 169 can be reduced. 
     The execution data executed in the function block 161 is applied from the node A to one input end of the NAND gate 169, and the output of NAND gate 169 is applied to one input end of an NOR gate 173 and it is also inverted in an inverter 171 and then applied to one input end of an NOR gate 172. Write clock signal φ W   is applied to the other input ends of the NOR gates 172 and 173. Outputs of the NOR gates 172 and 173 are applied to a writing driver 15. The writing driver 15 drives the result of the operation and outputs the same to the I/O gate 7. 
     FIG. 6 is the specific block diagram of the input buffer, the command buffer and the output buffer shown in FIG. 1. Referring to FIG. 6, the input buffer 12 comprises an NOR gate 121, a clock driver 122, a latch 123 and an inverter 124. The NOR gate 121 has one input end receiving input data input to a data input/output end DOi (i=1-4) and the other input end receiving a clock signal Φ RAS . The NOR gate 121 applies the input data to the clock driver 122 in synchronization with the clock signal Φ RAS . The clock driver 122 causes the latch 123 to latch the input data in synchronization with a clock signal Φ DIL . The output of the latch 123 is inverted in the inverter 124 and the inverted output is applied as the writing data to the operation processing block 16 shown in FIG. 3. 
     Similarly to the input buffer 12, the command buffer 10 comprises an NOR gate 101, a clock driver 102, a latch 103 and an inverter 104, in which the operation command CMD input to the data input/output terminal DOi is applied to the above-described operation block 16 shown in FIG. 3. 
     The output buffer 11 comprises an NAND gate 111, inverters 112 and 113 and an output driver 114. The NAND gate 111 has one input end receiving the read data RDi output from the preamplifier 14 shown in FIG. 3 and the other input end receiving the clock signal Φ OE . The NAND gate 111 outputs the read data RDi to the data input/output end DOi through the inverters 112 and 113 and the output driver 114 in synchronization with the clock. signal Φ OE . 
     FIGS. 7 and 8 are diagrams showing operation executing cycles according to one embodiment of the present invention, FIG. 7 showing a case where WB/WE is set after the fall of the CAS signal and FIG. 8 showing a case where WB/WE is set before the rise of the CAS signal. FIG. 9 is the timing chart of the respective clock signals. 
     Now, referring to FIGS. 1-9, more specific operations according to one embodiment of the present invention will be described. When as shown in FIG. 7 (a), the row strobe signal RAS falls to the &#34;L&#34; level, as shown in FIG. 7 (b), (b), the column address strobe signal CAS attains the &#34;H&#34; level, as shown in FIG. 7 (c), the output enable signal DT/OE attains the &#34;H&#34; level and as shown in FIG. 7 (d), the write enable signal WB/WE attains the &#34;L&#34; level, comes the operation cycle. As shown in FIG. 7 (e), the address signal is latched in the address buffer 9, whereby a row address of each of the memory cell arrays 1-4 is specified by the column decoder 6, and also as shown in FIG. 7 (f), the operation command CMD input to the data input/output terminals DO1-DO4 is latched in the CMD buffer 10. 
     Namely, as shown in FIG. 9 (a), when the row address strobe signal RAS falls to the &#34;L&#34; level, the clock signal Φ RAS  is falls to the &#34;L&#34; level as shown in FIG. 9 (d), thereby causing the NOR gate 101 shown in FIG. 6 to apply the operation command CMD to the clock driver 102. As shown in FIG. 9 (e), the operation command CMD is latched in the latch 103 at the timing at which the clock signal Φ RAL   rises to the &#34;H&#34; level and then the operation command CMD is inverted by the inverter 104. Furthermore, the operation command CMD is inverted in the inverters 162-165 shown in FIG. 3 and the inverted operation command CMD is applied to the function block 161. As shown in FIG. 9 (f), when the clock signal Φ ROP  attains the &#34;H&#34; level, the node A of the function block 161 is precharged. 
     Then, as shown in FIG. 7 (b) and FIG. 9 (c), when the column address strobe signal CAS attains the &#34;L&#34; level, the column address signal Y latched in the address buffer 9 is applied to the row decoder 5, whereby the data in the specified addresses are read out from the memory cell arrays 1-4, and which data are applied to the operation block 8 through the I/O gate 7. As shown in FIG. 9 (g), when the clock signal Φ PAE  rises to the &#34;H&#34; level, the preamplifier 141 shown in FIG. 3 is driven to amplify a difference between the data I/O and I/O, so that the amplified difference is applied to the operation block 16 through the clocked inverter 142. Furthermore, as shown in FIG. 7 (d), when the write enable signal WB/WE attains the &#34;L&#34; level, the clock signal Φ DIL  attains the &#34;H&#34; level as shown in FIG. 9 (m). On this occasion, since the clock signal Φ RAS   is at the &#34;L&#34; level as shown in FIG. 9 (d), the write data input to the data input/output terminals DO1-DO4 is applied to the clock driver 122 through the NOR gate 121 shown in FIG. 6. When the clock signal Φ DIL  attains the &#34;H&#34; level, the write data is latched in the latch 123 and then applied to the operation block 16 shown in FIG. 3 through the inverter 124. Since the operation command CMD and the read data RDi are already applied to the operation block 16, an operation in accordance with the operation command CMD is executed. 
     The data of the execution result is applied to the NOR gates 172 and 173 through the NAND gate 160 and the inverter 171 from the node A of the function block 161. Then, as shown in FIG. 9 (h), when the clock signal Φ W   attains the &#34;L&#34; level, the data of the operation result is applied to the writing driver 15 through the NOR gates 172 and 173 and then applied to the memory cell arrays 1-4 through the I/O gate 7. As a result, the data of the operation result is written in the predetermined address of the memory cell array. 
     In the above-described example shown in FIG. 7, the column address signal Y is latched in the address buffer 9 at the fall of the column address strobe signal CAS, to read the data from the memory cell arrays 1-4, and the write data is latched in the input buffer 12 at the fall of the write enable signal WB/WE to perform processing and writing of the operation data. However, as shown in FIG. 8, the column address signal Y may be latched in the address buffer 9 at the fall of the column address strobe signal CAS to read the data read from the memory cell arrays 1-4 and also the write data may be latched in the input buffer 12 to perform processing and writing of the operation data by the signal of the internal timing generator 13. 
     As the foregoing, according to one embodiment of the present invention, since the operation command data input to the data input terminal is temporarily stored in response to a level change of the first control signal input to the first control signal input terminal and the data input to the data input terminal and the data read out from the semiconductor memory elements are operated in accordance with the operation command data in response to the level change of the second signal input to the second signal control input terminal, it is possible to set and perform an operation processing of the operation command data in the same cycle, enabling high-speed data processing. 
     FIG. 10 is an operation timing chart explaining operation of another embodiment of the present invention. 
     While in the above-described embodiment, the change of the row address strobe signal RAS is considered to be a point at which the first signal changes and the change of the column address strobe CAS is considered to be a point at which the second signal changes, the operation command CMD is latched in the CMD buffer 10 in response to a change of one signal to execute operation in the embodiment shown in FIG. 10. More specifically, when the row address strobe signal RAS shown in FIG. 10(a) falls to a &#34;L&#34; level, the operation command CMD is latched in the latch 103 as shown in FIG. 10(l) at a rise of the clock signals φ RAL  and φ ROP  to a &#34;H&#34; level in the same manner as described with reference to FIG. 9. 
     The row address strobe signal RAS is applied to a delay circuit (not shown) to generate an internal column address strobe signal CAS shown in FIG. 10(b). Then, the data at the designated addresses is read from the memory cell arrays 1-4 in response to a fall of the internal column address strobe signal CAS to a &#34;L&#34; level. When the internal column address stroke signal CAS falls to a &#34;L&#34; level, the block signal φ PAE  rises to a &#34;H&#34; level, thereby driving the preamplifier 141 shown in FIG. 3. The same operation as in the above-described embodiment will be performed in the reafter. 
     FIG. 11 is a block diagram showing an embodiment of an application of the present invention to a static RAM. The embodiment of FIG. 11 is a variation of the embodiment shown in FIG. 1, with the memory cell arrays 1-4 constituting the DRAM being replaced by memory cell arrays 21-24 constituting the static RAM. Then, a part of the address signals is applied to the timing generator 13. Furthermore, the timing generator 13 receives an output enable signal OE, a write signal W and a chip select signal CS. 
     FIG. 12 is a timing chart explaining operation of the embodiment shown in FIG. 11. 
     With reference to FIGS. 11 and 12, when a level of an address signal changes as shown in FIG. 12(a), the clock signal φ RAL  rises to a &#34;H&#34; level as shown in FIG. 12(c), so that the operation command CMD is latched in the command buffer 10 and applied to the operation block 8. When the clock signal φ RAL  attains the &#34;H&#34; level, the clock signal φ ROP  rises to a &#34;H&#34; level as shown in FIG. 12(d), and the node A in the operation block 161 shown in FIG. 3 is precharged, so that clock signal φ PAE  rises to a &#34;H&#34; level as shown in FIG. 12(e), thereby applying the data read from the memory cells 21-24 to the operation block 8. When the clock signal φ PAE  falls to a &#34;L&#34; level, the clock signal φ DIL  rises to a &#34;H&#34; level, so that write data is latched in the input buffer 12. At this time point, with the read data being applied to the operation block 8 and the write data being latched in the input buffer 12 and applied to the operation block 8 the operation is performed, so that the clock signal φw falls to a &#34;L&#34; level as shown in FIG. 12(f), thereby outputting the operation result data. 
     As described above, in the present embodiment, static RAMs are used as the memory cells 21-24 and the operation command CMD is latched in the command buffer 10 in response to a change of a level of a part of the address signals, in accordance with which operation command CMD, the write data applied to the data input/output terminals DO1-DO4 and the data read from the memory cells 21-24 can be operated. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.