Abstract:
A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

Description:
This application is a Divisional of Ser. No. 10/908,087, filed Apr. 27, 2005 now U.S. Pat. No. 7,309,901. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates to field effect transistors (FETs), and more specifically, to staircase silicide FETs. 
     2. Related Art 
     In a typical field effect transistor (FET), there is a trade-off balance between (a) operation control and (b) resistance. More specifically, to have a better control of the threshold voltage Vt of the FET (so-called short channel effect), the FET&#39;s source/drain (S/D) extension regions which are in direct physical contact with the FET&#39;s channel region are formed as thin as possible. However, the thinner the S/D extension regions, the higher the resistances of these S/D extension regions, which is undesirable. 
     Therefore, there is a need for an FET (and a method for forming the same) which has a better trade-off balance between operation control and resistance than that of the prior art. 
     SUMMARY OF THE INVENTION 
     The present invention provides a semiconductor structure, comprising (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, wherein the channel region is disposed between and in direct physical contact with the first and second S/D extension regions, wherein the first S/D extension region is disposed between and in direct physical contact with the first S/D region and the channel region, and wherein the second S/D extension region is disposed between and in direct physical contact with the second S/D region and the channel region; (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface; (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region; (d) a first shallow contact region in direct physical contact with the first S/D extension region; and (e) a first deep contact region in direct physical contact with the first S/D region and the first shallow contact region, wherein the first shallow contact region is physically isolated from the semiconductor layer by the first S/D region and the first S/D extension region, and wherein the first shallow contact region is thinner than the first deep contact region in the reference direction. 
     The present invention also provides a semiconductor structure fabrication method, comprising (A) providing a semiconductor structure comprising (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, wherein the channel region is disposed between and in direct physical contact with the first and second S/D extension regions, wherein the first S/D extension region is disposed between and in direct physical contact with the first S/D region and the channel region, and wherein the second S/D extension region is disposed between and in direct physical contact with the second S/D region and the channel region, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region; and (B) forming (i) a first shallow contact region in direct physical contact with the first S/D extension region, and (ii) a first deep contact region in direct physical contact with the first S/D region and the first shallow contact region, wherein the first shallow contact region is physically isolated from the semiconductor layer by the first S/D region and the first S/D extension region, and wherein the first shallow contact region is thinner than the first deep contact region in the reference direction. 
     The present invention provides an FET (and a method for forming the same) which has a better trade-off balance between operation control and resistance than that of the prior art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-7  illustrate cross-section views of a first semiconductor structure going through steps of a first fabrication method, in accordance with embodiments of the present invention. 
         FIGS. 8-11  illustrate cross-section views of a second semiconductor structure going through steps of a second fabrication method, in accordance with embodiments of the present invention. 
         FIGS. 12-15  illustrate cross-section views of a third semiconductor structure going through steps of a third fabrication method, in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIGS. 1-7  illustrate cross-section views of a first semiconductor structure  100  going through steps of a first fabrication method, in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1 , in one embodiment, the first fabrication method starts out with a semiconductor (e.g., silicon, germanium, etc.) substrate  110 . Next, a gate stack  120 , 130  is formed on top of the semiconductor substrate  110 . In one embodiment, the gate stack  120 , 130  comprises (i) a gate dielectric region  120  on the semiconductor substrate  110  and (ii) and a gate region  130  on the gate dielectric region  120 . Illustratively, the gate dielectric region  120  comprises silicon dioxide (SiO 2 ) while the gate region  130  comprises doped polysilicon. 
     In one embodiment, the gate stack  120 , 130  is formed by (a) forming a gate dielectric layer (not shown) on the substrate  110 , then (b) forming a gate layer (not shown) on the gate dielectric layer, and then (c) patterning a photoresist layer to define the gate stack, and (d) directionally etching back the gate layer and the gate dielectric layer stopping at the substrate  110  such that what remain of the gate layer and the gate dielectric layer after the etching are the gate region  130  and the gate dielectric region  120 , respectively. The directional etching in step (d) may be performed using a traditional lithography process. 
     Next, in one embodiment, with reference to  FIG. 2 , extension spacers  210   a  and  210   b  are formed on side walls of the gate stack  120 , 130 . Illustratively, the extension spacers  210   a  and  210   b  are formed by (a) depositing an extension spacer layer (not shown) on the entire structure  100  of  FIG. 1 , and then (b) directionally etching back the extension spacer layer, leaving the extension spacers  210   a  and  210   b  on side walls of the gate stack  120 , 130 . In one embodiment, the extension spacers  210   a  and  210   b  comprise silicon nitride. 
     Next, the gate stack  120 , 130  and the extension spacers  210   a  and  210   b  are used as a blocking mask for forming source/drain (S/D) extension regions  220   a  and  220   b  in the semiconductor substrate  110  by, illustratively, ion implantation. As a result, a channel region  230  in the substrate  110  is defined that is (a) directly beneath and in direct physical contact with the gate dielectric region  120  and (b) disposed between and in direct physical contact with the S/D extension regions  220   a  and  220   b.    
     If the structure  100  is to be an N channel field effect transistor (FET), then P type dopants (e.g. B and/or In) are implanted into the channel region  230  (concentration ˜10 18 -10 19  atoms/cm 3 ) and N type dopants (e.g., arsenic and/or phosphorous atoms) are implanted in the substrate  110  to form the S/D extension regions  220   a  and  220   b  with dopant concentration after S/D anneal being, illustratively, about 10 19 -10 20  atoms/cm 3 . In contrast, if the structure  100  is to be a P channel FET, then N type dopants (e.g. As and/or P) are implanted into channel region (concentration ˜10 18 -10 19  atoms/cm 3 ) and P type dopants (e.g., boron atoms) are implanted in the substrate  110  to form the S/D extension regions  220   a  and  220   b  with dopant concentration after S/D anneal being, illustratively, about 10 19 -10 20  atoms/cm 3 . In one embodiment, the thickness (depth)  222  of the S/D extension regions  220   a  and  220   b  is in a range of 20-40 nm after S/D anneal. 
     Next, with reference to  FIG. 3 , in one embodiment, S/D spacers  310   a  and  310   b  are formed on side walls of the extension spacers  210   a  and  210   b , respectively. Illustratively, the S/D spacers  310   a  and  310   b  are formed by (a) depositing an S/D spacer layer (not shown) on the entire structure  100  of  FIG. 2 , and then (b) directionally etching back the S/D spacer layer, leaving the S/D spacers  310   a  and  310   b  on side walls of the extension spacers  210   a  and  210   b , respectively. In one embodiment, the S/D spacers  310   a  and  310   b  comprise silicon dioxide (SiO 2 ). 
     Next, the gate stack  120 , 130 , the extension spacers  210   a  and  210   b , and the S/D spacers  310   a  and  310   b  are used as a blocking mask for forming S/D regions  320   a  and  320   b  in the semiconductor substrate  110  by, illustratively, ion implantation. Polysilicon region  130  receives S/D ion implantation in order to dope gate conductor to reduce resistance and electrical thickness of gate dielectrics. If the structure  100  is to be an N channel FET, then N type dopants (e.g., phosphorous atoms) are implanted in the substrate  110  to form the S/D regions  320   a  and  320   b  with dopant concentration after S/D anneal being, illustratively, 10 20  atoms/cm 3 . In contrast, if the structure  100  is to be a P channel FET, then P type dopants (e.g., boron atoms) are implanted in the substrate  110  to form the S/D regions  320   a  and  320   b  with dopant concentration after S/D anneal being, illustratively, 10 20  atoms/cm 3 . In one embodiment, after the S/D regions  320   a  and  320   b  are formed, a S/D anneal process (e.g., 950 1100 C. for 1-10 seconds and/or laser spike anneal) is performed to activate dopants in S/D extension regions  220   a  and  220   b , the S/D regions  320   a  and  320   b , and the polysilicon gate region  130 . In one embodiment, the thickness (depth)  322  of the S/D regions  320   a  and  320   b  after the S/D anneal process is in a range of 50-150 nm. 
     Next, with reference to  FIG. 4 , in one embodiment, a thick metal layer  410  is formed on top of the entire structure  100  of  FIG. 3 . Illustratively, the metal layer  410  comprises nickel (Ni) and has a thickness  412  in a range of 4-15 nm. The metal layer  410  may be formed by a physical vapor deposition process (PVD) or atomic layer deposition (ALD). 
     Next, in one embodiment, the structure  100  of  FIG. 4  is annealed (heated) at a temperature in a range of 300-450° C. for about 1-10 sec so as to cause nickel of the metal layer  410  to (a) chemically react with silicon of the substrate  110  to form silicide nickel regions  510   a  and  510   b  ( FIG. 5 ) and (b) chemically react with silicon of the polysilicon gate region  130  to form a silicide nickel region  520 . Then, the unreacted nickel is removed by, illustratively, a wet etch step. The resultant structure  100  is shown in  FIG. 5 . With reference to  FIG. 5 , in one embodiment, the thickness  512  of the silicide regions  510   a  and  510   b  is less than the thickness  322  of the S/D regions  320   a  and  320   b.    
     Next, with reference to  FIG. 6 , in one embodiment, the spacers of  310   a  and  310   b  ( FIG. 5 ) are etched away and then a thin metal layer  610  is formed on top of the entire structure  100 . Illustratively, the metal layer  610  comprises platinum (Pt) and has a thickness  612  in a range of 2-4 nm. The metal layer  610  may be formed by a physical vapor deposition (PVD) process or atomic layer deposition (ALD). 
     Next, in one embodiment, the structure  100  of  FIG. 6  is annealed (heated) at a temperature in a range of, illustratively, 300-450° C. (preferably, this temperature range is selected so as to not change the property of silicide regions  510   a  and  510   b ) for about 1-10 sec so as to cause platinum of the metal layer  610  to (a) chemically react with NiSi of the silicide regions  510   a  and  510   b  to form NiPtSi regions  710   a  and  710   b , respectively ( FIG. 7 ), (b) chemically react with silicon of the substrate  110  to form silicide platinum (PtSi) regions  720   a  and  720   b  ( FIG. 7 ), and (c) chemically react with NiSi on top of the gate region  130  to form a NiPtSi  730  ( FIG. 7 ). Then, the unreacted platinum material is removed by, illustratively, a wet etch step. The resultant structure  100  is shown in  FIG. 7 . With reference to  FIG. 7 , in one embodiment, the thickness  722  of the PtSi regions  720   a  and  720   b  is less than the depth  222  of the S/D extension regions  220   a  and  220   b , and is also less than the depth  512  of the silicide regions  510   a  and  510   b.    
       FIGS. 8-11  illustrate cross-section views of a second semiconductor structure  200  going through steps of a second fabrication method, in accordance with embodiments of the present invention. More specifically, in one embodiment, the second fabrication method starts out with the structure  100  of  FIG. 5 . The same reference numerals will be used to indicate that the regions in the figures are similar. 
     Next, with reference to  FIG. 8 , in one embodiment, a nitride layer  810  is directionally formed on top of the entire structure  100  of  FIG. 5  such that the nitride layer  810  is thinnest (corresponding to the thickness  812 ) on side walls of the S/D spacers  310   a  and  310   b . In one embodiment, the nitride layer  810  is formed by a plasma enhanced CVD process or high density plasma (HDP) deposition. 
     Next, the nitride layer  810  is isotropically etched back by, illustrative, a wet/dry etch process (non-directional) such that only portions of the nitride layer  810  that cover the S/D spacers  310   a  and  310   b  are etched. As a result, the S/D spacers  310   a  and  310   b  are partially exposed to the surrounding ambient. The resultant structure  200  is shown in  FIG. 9 . Next, the S/D spacers  310   a  and  310   b  are removed by, illustratively, a wet etch process. 
     Next, with reference to  FIG. 10 , in one embodiment, a thin metal layer  1010  is formed on top of the entire structure  100  of  FIG. 9  (with the S/D spacers  310   a  and  310   b  having been removed). Illustratively, the metal layer  1010  comprises platinum (Pt) and has a thickness  1012  in a range of 2-4 nm. The metal layer  1010  may be formed by a PVD process or atomic layer deposition (ALD). 
     Next, in one embodiment, the structure  100  of  FIG. 10  is annealed (heated) at a temperature m a range of, illustratively, 300-450° C. (preferably, this temperature range is selected so as to not change the property of silicide regions  510   a  and  510   b ) for about 1-10 sec so as to cause platinum of the metal layer  1010  to chemically react with silicon of the substrate  110  to form silicide platinum (PtSi) regions  1110   a  and  1110   b  ( FIG. 11 ). Then, the unreacted platinum material is removed by, illustratively, a wet etch step. The resultant structure  200  is shown in  FIG. 11 . With reference to  FIG. 11 , in one embodiment, the thickness  1112  of the PtSi regions  1110   a  and  1110   b  is less than the depth  222  of the S/D extension regions  220   a  and  220   b , and is also less than the depth  512  of the silicide regions  510   a  and  510   b.    
       FIGS. 12-15  illustrate cross-section views of a third semiconductor structure  300  going through steps of a third fabrication method, in accordance with embodiments of the present invention. More specifically, in one embodiment, the third fabrication method starts out with the structure  100  of  FIG. 3  with the oxide S/D spacers  310   a  and  310   b  being removed by, illustratively, a wet etch process. The same reference numerals will be used to indicate that the regions in the figures are similar. 
     Next, with reference to  FIG. 12 , in one embodiment, a thin metal layer  1210  is formed on top of the entire structure  100  of  FIG. 3  (with the oxide S/D spacers  310   a  and  310   b  having being removed). Illustratively, the metal layer  1210  comprises platinum (Pt) and has a thickness  1212  in a range of 2-4 nm. The metal layer  1210  may be formed by a PVD process or atomic layer deposition (ALD). In an alternative embodiment, the metal layer  1210  comprises a nickel platinum alloy with nickel percentage being smaller than 5% in molecule number. 
     Next, in one embodiment, the structure  300  of  FIG. 12  is annealed (heated) at a temperature in a range of, illustratively, 300-450° C. for about 10 sec so as to cause platinum of the metal layer  1210  to (a) chemically react with silicon of the substrate  110  to form silicide platinum (PtSi) regions  1310   a  and  1310   b  ( FIG. 13 ) and (b) chemically react with silicon of the polysilicon gate region  130  to form a silicide platinum region  1310   c  ( FIG. 13 ). Then, the unreacted platinum material is removed by, illustratively, a wet etch step. The resultant structure  300  is shown in  FIG. 13 . With reference to  FIG. 13 , in one embodiment, the thickness  1312  of the PtSi regions  1310   a  and  1310   b  is less than the depth  222  of the S/D extension regions  220   a  and  220   b.    
     Next, in one embodiment, spacers  1320   a  and  1320   b  are formed on side walls of the extension spacers  210   a  and  210   b , respectively. The spacers  1320   a  and  1320   b  may comprise silicon dioxide (SiO 2 ). 
     Next, with reference to  FIG. 14 , in one embodiment, a thick metal layer  1410  is formed on top of the entire structure  300  of  FIG. 13 . Illustratively, the metal layer  1410  comprises nickel (Ni or NiPt) and has a thickness  1412  in a range of 4-15 nm. The metal layer  1410  may be formed by a CVD process. 
     Next, in the embodiment in which the metal layer  1410  comprises nickel as identified supra, the structure  300  of  FIG. 14  is annealed (heated) at a temperature in a range of, illustratively, 300-450° C. (preferably, this temperature range is selected so as to not change the property of portions of the silicide regions  1310   a  and  1310   b  directly under the spacers of  1320   a  and  1320   b , respectively) for about 1-10 sec so as to cause nickel of the metal layer  1410  to (a) chemically react with PtSi of the silicide regions  1310   a  and  1310   b  to form NiPtSi regions  1510   a  and  1510   b , respectively ( FIG. 15 ), (b) diffuse down and chemically react with silicon of the substrate  110  to form silicide nickel (NiSi) regions  1520   a  and  1520   b  ( FIG. 15 ), (c) chemically react with PtSi of the silicide region  1310   c  to form a NiPtSi region  1510   c  ( FIG. 15 ), and (d) diffuse down and chemically react with silicon of the polysilicon gate region  130  to form NiSi  1520   c  ( FIG. 15 ). Then, the unreacted nickel material is removed by, illustratively, a wet etch step. The resultant structure  300  is shown in  FIG. 15 . With reference to  FIG. 15 , in one embodiment, the depth  1522  of the PtSi regions  1520   a  and  1520   b  is less than the depth  322  of the S/D regions  320   a  and  320   b , but is greater than the depth  1312  of the PtSi regions  1310   a  and  1310   b.    
     In summary, with reference to  FIGS. 7 ,  11 , and  15 , in the three structures  100 ,  200 , and  300 , portions of the S/D extension regions  220   a  and  220   b  and the S/D regions  320   a  and  320   b  are replaced by electrically conducting silicide materials (PtSi, NiSi, and NiPtSi) as much as possible, without eliminating the junctions between the S/D extension regions  220   a  and  220   b  and the substrate  110  as well as the junctions between the S/D regions  320   a  and  320   b  and the substrate  110 . In other words, the silicide regions (also referred to as the contact regions) are formed thinner in the S/D extension regions  220   a  and  220   b  and thicker in the S/D regions  320   a  and  320   b . For instance, with reference to  FIG. 7 , the contact region  510   a , 710   a , 720   a  is thinner in the S/D extension regions  220   a  (thickness  722 ) and thicker in the S/D regions  320   a  (thickness  512 ). Similarly, the contact region  510   b , 710   b , 720   b  is thinner in the S/D extension regions  220   a  and thicker in the S/D regions  320   a.    
     While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.