Abstract:
A protection circuit for protecting DCDC converter with a power MOS transistor from start-up in-rush current includes a coupling capacitor and a voltage clamping circuit. By using the coupling capacitor to turn-off the power MOS transistor, there is no current consumed during the normal operation of the circuit. Enable signal or leakage current circuit is used to discharge the capacitor so that the circuitry can work in another turning-on of power supply.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a start-up in-rush current protection circuit for DCDC converter, making use of capacitor and voltage clamping circuitry. 
     Typically, a DCDC converter is a device to control an external power MOS transistor to produce a certain regulated DC voltage. The external power MOS transistor is controlled by a signal from a driver block. The power MOS acts as a switch, turning on and off according to the driver signal which controls the gate of the power MOS transistor. 
     The driver block is usually turned-on by an Enable signal. During start-up, when power supply voltage rises, the driver block may have not been enabled. Due to parasitic capacitances of the power MOS transistor, it is possible to happen that the gate voltage of the power MOS transistor can not follow the fast rising of power supply voltage. This causes the output voltage to rise to a high voltage. This event may destroy the components connected to output voltage of DCDC converter. 
     Conventionally, as shown in  FIG. 1 , this problem is avoided by connecting a resistor R p  between the drain and gate of the power MOS transistor so that the gate voltage may follow the power supply voltage. 
     There are two drawbacks with the conventional circuit. The first drawback is that there is still possibility for the gate voltage to not follow the power supply voltage, especially when the resistance value of resistor R p  is large. The second drawback is that there is constant current consumed by the resistor after driver block is enabled. This current may be large if the resistance value of resistor Rp is small. 
     SUMMARY OF THE INVENTION 
     The purpose of this invention is to turn-off external power MOS transistor of DCDC converter while avoiding the two drawbacks mentioned in previous section. 
     The present invention makes use of capacitors and voltage clamping circuitry to turn-off the external power MOS transistor. 
     According to the present invention, a start-up in-rush current protection circuit for a DCDC converter with an output stage circuit having a power transistor, an inductor and a smoothing capacitor connected in series between a power supply and a ground, the protection circuit comprises: a coupling capacitor having a first terminal connected to said power supply, a PMOS transistor having a drain terminal connected to a gate terminal of the power transistor, a source terminal connected to the power supply, and a gate terminal connected to the power supply; a first NMOS transistor having a drain terminal connected to a gate terminal of said PMOS transistor, a source terminal connected to ground, and a gate terminal connected to a second terminal of said coupling capacitor; and a driver block having an output terminal connected to said drain terminal of said PMOS transistor, for outputting voltage driving signals to the gate terminal of the DCDC converter power transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing the conventional circuitry to avoid in-rush current during start-up. 
         FIG. 2A  is a block diagram showing the first embodiment of the present invention. 
         FIG. 2B  is a block diagram showing an example circuit according to the first embodiment of the present invention. 
         FIG. 2C  is a circuit diagram showing an example of a circuit that can be used as a driver  103 . 
         FIG. 3A  is an example of a circuit element that can be used as a voltage clamp. 
         FIG. 3B  is yet another example of a circuit that can be used as a voltage clamp. 
         FIG. 4  is a circuit diagram showing an example of a circuit that can be used as a leakage current circuit. 
         FIG. 5  is a block diagram showing the second embodiment of the present invention. 
         FIG. 6  is an example of a waveform showing the generation of the Enable signal at node EN. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following description explains the best mode embodiment of the present invention. 
     (First Embodiment) 
     Referring to  FIG. 2A , a first embodiment of a start-up in-rush current protection circuit according to the present invention is shown. 
     The start-up in-rush current protection circuit has an output stage circuit  104  for a DCDC converter which comprises a power PMOS transistor MP 1 , inductor L, zener diode  105 , smoothing capacitor C and load R load . Capacitances represented by C SG  and C GD  are parasitic capacitances present in power PMOS transistor MP 1 , effectively between the source and gate terminals, and between the drain and gate terminals respectively. Power supply (not shown) to the circuit is via terminal PVCC. A typical DCDC converter is disclosed for example in a published article by National Semiconductor: “Linear and Switching Voltage Regulator Fundamentals” on page 34, which is herein incorporated by reference. The article “Linear and Switching Voltage Regulator Fundamentals” can be obtained from the following URLs.
     http://www.national.com/appinfo/power/files/f4.pdf   http://www.national.com/appinfo/power/files/f5.pdf
 
The former covers pages 1-29, and the latter covers pages 30-62.
   

     According to the first embodiment of the present invention, a start-up in-rush current protection circuit further has a voltage clamp  100 , a voltage coupling circuit  110 , a charging circuit  111  and a leakage current circuit  102 . 
     The voltage clamp circuit  100  clamps the voltage of node A. The voltage coupling circuit  110  is connected to a power supply and node A. The voltage coupling circuit  110 , which is according to one example formed by a capacitor, couples the power supply voltage at terminal PVCC to node A. The voltage at node A will be changed proportionally to the voltage of at terminal PVCC, and it is clamped by the voltage clamp circuit  100 . 
     The charging circuit  111  is controlled by the voltage of node A. If voltage of node A is higher than a predetermined value, the charging circuit  111  charges the gate of output power transistor MP 1  and turns off the output power transistor MP 1 . If voltage of node A is lower than the predetermined value, the charging circuit  111  will be de-activated. 
     The leakage current circuit  102  is added to discharge the voltage of the node A slowly to deactivate the charging circuit  111 . 
     A further detail of the first embodiment is shown in  FIGS. 2B ,  3 A,  3 B and  4 . 
     As shown in  FIG. 2B , the voltage coupling circuit  110  is formed by a coupling capacitor Cp. 
     The charging circuit  111  has voltage clamp  101 , NMOS transistor M 1 , PMOS transistor M 2 , driver  103 , and NMOS transistor M 3 . The NMOS transistor M 3  and the driver  103  are activated by an enable signal EN. Driver  103  is exemplarily represented by  FIG. 2C . The driver  103  may exemplarily comprise of an inverter  103 A, which is herein incorporated by reference. 
     Voltage clamp  100  comprises, but not necessarily limited to, zener diode, as shown in  FIG. 3A . 
     Voltage clamp  101  comprise, but not necessarily limited to, diodes connected in series, as shown in  FIG. 3B . 
     As one example, leakage current circuit  102  is shown in  FIG. 4 . The Leakage current circuit  102  has a capacitor  201 , resistor  202 , zener diode  203  and NMOS transistor  200 . Capacitor  201  has a capacitance which is at least twice the capacitance of C p . The resistor  202  is an optional element, typically used for ESD protection, and may not necessarily be included. Also, the W/L ratio of NMOS transistor  200  is very small, so as to cause NMOS transistor  200  to sink small amount of current per unit time. 
     The operation of the first embodiment of the present invention is now described based on an exemplary implementation as shown in  FIG. 2B . 
     Upon circuit start-up, the voltage at terminal PVCC rises. Via capacitor C P , gate voltage of NMOS transistor M 1  will be charged to Vclamp 1  (the voltage determined by the Voltage Clamp  100 ). This turns NMOS transistor M 1  on. Voltage clamp  100  is connected to the gate of NMOS transistor M 1  so that NMOS transistor M 1  is protected from VGS breakdown. 
     When NMOS transistor M 1  is turned on, gate voltage of PMOS transistor M 2  becomes (PVCC−Vclamp 2 ), thus turning PMOS transistor M 2  on. Voltage clamp  101  is inserted between the gate and source of PMOS transistor M 2  so that PMOS transistor M 2  is protected from VSG breakdown. 
     Since PMOS transistor M 2  is turned on, the voltage at node HSD is short circuited to PVCC voltage, avoiding the turning on of power PMOS transistor MP 1 . Thus, the power PMOS transistor MP 1  is protected from the in-rush current. 
     Leakage current circuit  102  is a circuitry that constantly draws small current. It helps to gradually discharge the gate of NMOS transistor M 1  so that the gate voltage of NMOS transistor M 1  falls low enough to cause NMOS transistor M 1  to turn off. This in turn turns off PMOS transistor M 2 . When this happens, the gate terminal of power PMOS transistor MP 1  will no longer be tied to the PVCC voltage. 
     When the user desires to enable power PMOS transistor MP 1 , an enable signal is generated at node EN, as shown in  FIG. 6 . 
     NMOS transistor M 3  functions as a switch to discharge the gate of NMOS transistor M 1 . When Enable signal is generated at node EN, NMOS transistor M 3  turns on, and subsequently, turns off NMOS transistor M 1  and PMOS transistor M 2 . The same Enable signal generated at node EN also turns on Driver block  103 , whose output terminal is coupled to the gate terminal of the power PMOS transistor MP 1 . Therefore, Driver block  103  will take over control of the operation of power PMOS transistor MP 1 . 
     The protection circuit is now ready to work in the next turning on of the IC. 
     (Second Embodiment) 
     A second embodiment of this invention is shown in  FIG. 5 . Here, instead of the leakage current circuit  102 , an NMOS transistor M 3  is used. At the instance when the user wishes the driver block  103  to take over control of power PMOS transistor MP 1 , a signal is sent to both NMOS transistor M 3  and the driver block  103  so as to cause both NMOS transistor M 3  and driver block  103  to be enabled. The signal is sent to the driver block  103  via an ‘Enable’ terminal  103 A. The enabling of NMOS transistor M 3  causes NMOS transistor M 1  and PMOS transistor M 2  to be disabled. This allows power PMOS transistor MP 1  to be controlled by driver block  103 . Typically, the Enable signal generated at node EN is a HIGH signal, as shown in  FIG. 6 . 
     Although the present invention has been described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims, unless they depart therefrom.