Abstract:
A server and a signal analyzing device thereof are disclosed. The server includes a plurality of hard disk drive (HDDs), a plurality of indicators, at least a jumper, and a logic array. The logic array is coupled to the at least one jumper and includes a plurality of analyzing modules. The logic array selects one of the analyzing modules in response to the at least one jumper. The selected analyzing module analyzes an input signal and outputs a decoded signal. The indicators show the states of the HDDs according to the decoded signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 201410276974.2 filed in China on Jun. 20, 2014, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     Technical Field of the Invention 
     The present disclosure relates to a server and a signal analyzing device thereof, and more particularly to a server with a signal analyzing device that is capable of analyzing multiple sets of input signals. 
     Description of the Related Art 
     The hardware techniques are maturing in days in accordance with the advancement of the modern technology. Many hardware devices can not only store and access data but also execute multiple different tasks. However, if the user wants to know the current executing functions or working status of the device externally, he still needs to check the signal lamp on the backplane to get the information related to the hardware. 
     But the traditional signal analyzing chip on the backplane can only analyze one set of input signals. Therefore, the user needs to replace the signal analyzing chip to analyze other sets of input signals if he wants to use the other sets of input signals. Since the signal analyzing chip is usually soldered on the backplane, if the user wants to replace the signal analyzing chip, he has to replace the whole backplane at the same time. Consequently, the replacement cost will be very burdensome to the user. More precisely, the chip on the backplane of the hard disk drive (HDD) analyzes the status of the connected HDD according to a serial general purpose input output (SGPIO) signal. Due to that the traditional signal analyzing chip can analyze only one set of SGPIO signals, it reduces versatility and increases inconvenience. 
     SUMMARY OF THE INVENTION 
     According to one or more embodiments, a server includes a plurality of HDDs, a plurality of indicators, at least a jumper, and a logic array. The logic array is coupled to the at least one jumper and includes a plurality of analyzing modules. The logic array selects one of the analyzing modules in response to the jumper. The selected analyzing module analyzes an input signal and outputs a decoded signal. The indicators display work states of the HDDs according to the decoded signal. 
     In one embodiment of the server, the server further includes a storage controller that is coupled to the HDDs and transmits the input signal to the logic array. 
     In one embodiment of the server, the server further includes a HDD backplane that is coupled with the HDDs, and the at least one jumper, the logic array, and the indicators are disposed on the HDD backplane. 
     In one embodiment of the server, the server further includes a mother board, a CPU, and an interposer board. The CPU is disposed on the mother board, and the storage controller is disposed on the interposer board. The interposer board is coupled between the mother board and the HDD backplane, and the storage controller is coupled between the CPU and the plurality of HDDs. 
     In one embodiment of the server, the amount of the at least one jumper is n, n is greater than or equal to 1, the jumpers produce less than or equal to 2 n  sets of different jumper signals, and the amount of the analyzing modules is less than or equal to 2 n . 
     According to one or more embodiments, a signal analyzing device includes at least a jumper and a logic array. The logic array includes a plurality of analyzing modules and selects one of the analyzing modules in response to the at least one jumper, and the selected analyzing module analyzes an input signal to produce a decoded signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure will become more fully understood from the detailed description given herein below for illustration only and thus does not limit the present disclosure, wherein: 
         FIG. 1  is a functional block diagram of a server according to an embodiment of the present disclosure. 
         FIG. 2  is a flow chart of a signal analyzing method according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawings. 
     Please refer to  FIG. 1 .  FIG. 1  is a functional block diagram of a server according to an embodiment of the present disclosure. The server comprises a plurality of HDDs  10   a  and  10   b , a HDD backplane  20 , an interposer board  30 , and a mother board  40 . The HDD  10   a  and  10   b  may be any storage media accessible to the computer. 
     The HDD backplane  20  comprises a signal analyzing device  22  and indicator  24   a  and  24   b . The signal analyzing device  22  comprises a logic array  26  and at least a jumper (such as jumpers  28   a  and  28   b . The logic array  26  is coupled with the jumpers  28   a  and  28   b . The logic array  26  receives and analyzes an input signal  90  to produce a decoded signal  92  in response to at least one of the jumpers  28   a  and  28   b , where the decoded signal  92  may be a parallel signal. 
     In one or more embodiments, the aforementioned logic array  26  may be a complex programmable logic device (CPLD) or any other device capable of analyzing signals. 
     The logic array  26  may comprise a plurality of analyzing modules  27   a  and  27   b . The logic array  26  may select one of the analyzing modules  27   a  and  27   b  in response to at least one of the jumpers  28   a  and  28   b . The selected analyzing module may analyze the input signal  90  to produce the decoded signal  92 . The indicators  24   a  and  24   b  may display the working states of the HDDs  10   a  and  10   b  according to the decoded signal  92 . 
     The input signal  90  may be but not limited to a serial general purpose input output (SGPIO) signal or general purpose input output (GPIO) signal from the HDDs  10   a  and  10   b . Since the input signal  90  may carry the information of the HDDs&#39; states, the analyzing modules  27   a  and  27   b  may extract the information of the HDDs&#39; states from the input signal  90  to produce the decoded signal  92 . 
     The jumpers  28   a  and  28   b  may cooperate with other electronic components to provide the input signal to the logic array  26 . The electronic components may be but not limited to the resistors  29   a  and  29   b . As shown in the figure, the jumpers  28   a  and  28   b  are constantly in the disconnected status and the jumpers  28   a  and  28   b  are connected when the cap is disposed on the jumpers  28   a  and  28   b . The logic array  26  may select one of the analyzing modules  27   a  and  27   b  according to the configuration of at least one of the jumpers  28   a  and  28   b  or the jumper signal. The selected analyzing module may analyze the input signal  90  to produce the decoded signal  92 . One configuration may correspond to one jumper signal. 
     The logic array  26  comprises at least a pin (such as pins  26   a  and  26   b ). The jumpers  28   a  and  28   b ) are connected to the pins  26   a  and  26   b  respectively. The connection states of the jumpers  28   a  and  28   b  may be used to control the logic levels of the pins  26   a  and  26   b , so that the logic array  26  may select one of the analyzing modules  27   a  and  27   b  according to the logic level of the at least one of the pins  26   a  and  26   b  and the selected analyzing module may analyze the input signal  90  to produce the decoded signal  92 . 
     Taking two jumpers  28   a  and  28   b  for an example, every jumper has two states (as referred to be the connection states): ON state and OFF state. When the jumpers  28   a  and  28   b  are in ON state, the pins  26   a ,  26   b  may be in logical low. When the jumpers  28   a  and  28   b  are in OFF state, the pins  26   a  and  26   b  are in logical high. According to the two states of every jumper, the two jumpers  28   a  and  28   b  may provide 4 configurations (or called jumper signals): 00, 01, 10, 11, representing in a logical expression. These four configurations may correspond to the analyzing modules  27   a  and  27   b . In other words, two jumpers may pair up with 4 analyzing modules at most. Likewise, three jumpers may pair up with 8 (2 3 ) analyzing modules at most. 
     More precisely, the amount of the jumpers may be n, where n is greater than or equal to 1. The n jumpers may provide less than or equal to 2 n  configurations (i.e. jumper signals), and the amount of the analyzing modules may be less than or equal to 2 n . 
     Then, the logic array  26  may select one of the analyzing modules  27   a  and  27   b  according to the configuration of the jumper  28   a  or  28   b  or the jumper signal and analyze the input signal  90  to produce the decoded signal  92  by the selected analyzing module  27   a  or  27   b.    
     The decoded signal  92  may be applied to the indicators  24   a  and  24   b  via a plurality of output pins. Every pin is coupled to one indicator standing for the status of a HDD. The status may be but not limited to ON/OFF, reading, or writing. 
     In addition, the decoded signal  92  may also be another serial signal that may be but not limited to RS232 (i.e. standard interface for serial data communication). And, the indicators  24   a  and  24   b  may comprise a control unit to convert the decoded signal  92  to a driving signal to drive the indicators  24   a  and  24   b.    
     Moreover, the indicator may be but is not limited to a seven segment display, a light emitting diode (LED), or a liquid crystal display (LCD). 
     The aforementioned server may comprise a storage controller  32 . The storage controller  32  may be coupled with the HDDs  10   a  and  10   b  and transmit the input signal  90  to the signal analyzing device  22  (i.e. the logic array  26 ). The storage controller may be but not limited to a serial attached small computer system interface (SCSI)) expander, Southbridge chipset, or serial advanced technology attachment (SATA) expander. 
     The aforementioned HDD backplane  20  may be coupled with the HDDs  10   a  and  10   b . The jumpers  28   a  and  28   b , the logic array  26 , and the indicators  24   a  and  24   b  may be disposed on the HDD backplane  20 . 
     The aforementioned CPU  42  may be disposed on the mother board  40 . The storage controller  32  may be disposed on the interposer board  30 . The interposer board  30  may be coupled between the mother board  40  and the HDD backplane  20 . The storage controller  32  may be coupled between the CPU  42  and the HDDs  10   a  and  10   b.    
     In order to make the persons skilled in the art have a deeper understanding about the signal analyzing device  22  of the present disclosure, the signal analyzing method is described as follows. Please refer to both  FIG. 1  and  FIG. 2 .  FIG. 2  is a flow chart of the signal analyzing method according to an embodiment of the present disclosure. According to  FIG. 2 , the storage controller  32  may send an input signal  90  to the logic array  26  of the analyzing device  22  in step S 600 . In step S 602 , the logic array  26  may detect the configurations of the jumpers  28   a  and  28   b.    
     In step S 604 , the logic array  26  may select the corresponding analyzing module (e.g. the analyzing module  27   a ) from the analyzing modules  27   a  and  27   b  according to the configuration of the jumper  28   a  or  28   b . In step S 606 , the analyzing module  27   a  may analyze the input signal  90  to produce the decoded signal  92  and send it to the indicators  24   a  and  24   b . In step S 608 , the indicators  24   a  and  24   b  may provide the status signs in accordance with the decoded signal  92 . The status sign may be the aforementioned HDD&#39;s status. 
     In conclusion, the present disclosure may receive input signals. Then the logic array  26  may select the corresponding analyzing module  27   a  or  27   b  according to the configuration of the jumper  28   a  or  28   b , to analyze the input signal by the selected analyzing module  27   a  or  27   b  to produce the decoded signal  92 . Therefore, the user may not need to replace the signal analyzing device  22  in response to difference input signal sets or different configurations of the server hardware.