Abstract:
A regulator circuit to deliver a regulated boosted voltage VPP from a charge pump to electrodes of the cells of a non-volatile memory (NVM) array, such as an EPROM, integrated circuit device. The regulator includes a differential amplifier operating from a VDD voltage lower than VPP that drives a gain stage whose output is to a current mirror operating from the boosted VPP voltage. The current mirror output is taken across a voltage divider as the regulated output of the circuit. The differential amplifier has one input at a fixed voltage and the other being a feedback voltage from the voltage divider to control the gain of the differential amplifier and thereby regulate the output of the gain stage and current mirror in response to a variable load current of the integrated circuit device. The circuit is capable of providing current at the boosted VPP voltage for programming the cells of the NVM while minimizing power consumption from the VDD supply of the charge pump and having a high PSRR (power supply rejection ratio) as compared to prior art circuits.

Description:
FIELD OF THE INVENTION 
     This invention relates to voltage regulators for use in the current supply to the drain on other electrodes of the memory transistors of a non-volatile memory integrated circuit. 
     BACKGROUND OF THE INVENTION 
     In using non-volatile memory (NVM) arrays, such as EPROMs, a relatively large current is required to be delivered to the drain electrodes of the transistor memory cells. This is usually done at a boosted voltage, called VPP (typically 4-7V), which is above the standard voltage supply, called VDD (typically 1.8-3.6V). The source of the boosted voltage is usually a charge-pump. A typical charge pump for a NVM array is shown for example, in U.S. Pat. No. 5,280,420. Typically, the boosted output voltage VPP of the pump has an AC ripple which is superimposed on the DC level. In many instances, a voltage regulator is used between the output of the charge pump and the NVM to eliminate AC ripple and fix the DC voltage irrespective of process/environment variations. 
     It is important that such a regulator has a high power supply rejection ratio (designated PSRR) so that the charge pump noise or ripple does not reach the NVM transistors, such as the drain electrodes of EPROM transistor memory cells, and affect the programming or erase characteristics of the memory cells. In addition, as the efficiency of the charge pump is typically 30%, it is important for the regulator to minimize the current consumption on the charge pump in order to conserve power. 
     A prior art regulator, which minimizes current consumption on the charge pump, is shown in FIG.  1 . In this regulator there is a differential amplifier gain stage, GM 1 , and an inverting amplifier gain stage, GM 2 . Both GM 1  and GM 2  receive as operating voltage the voltage VPP from the charge pump supply (not shown). Gain stage GM 1  is basically a differential amplifier whose inverted input is from a stable reference bias voltage source IP. The output of GM 1  is applied to the gate of GM 2 , which is shown as a P-channel MOS transistor (PMOS). 
     The boosted voltage VPP from the charge pump is applied to GM 1  as its operating voltage and is also applied to the source of GM 2 . The drain of GM 2  is connected to the reference potential (ground) through a voltage divider of two series connected resistors R 1  and R 2 . A capacitor (Cm), commonly called the “Miller capacitor”, is connected to the gate of GM 2  and the output of GM 1  at n 1  and to the upper end of the voltage divider R 1  and R 2  at n 2 . The capacitor Cm is used to stabilize the operation of GM 1 . A capacitor CL is across the voltage divider R 1 -R 2  to ground. 
     The load current, I LOAD , which is the current drawn by the memory cells of the NVM, is taken off at the drain of GM 2  at node n 2 , across the two resistors R 1  and R 2  to ground. The voltage output at n 2  is set by the ratio of R 1  and R 2 . 
     There is a feedback path fb from the junction of R 1 -R 2  to the non-inverting input of the differential amplifier gain stage GM 1 . When there is a large I LOAD , the gate of the PMOS driver GM 2  adjusts itself from the feedback voltage fb to provide an appropriate current. That is, for example, as I LOAD  increases the feedback loop sets the operation point of GM 2  to drive higher current. 
     The circuit of FIG. 1 has a poor PSRR. This is because the Miller capacitor (Cm, used to stabilize the amplifier), couples the gate of GM 2  to its drain at high frequencies. Since the load capacitor CL is coupled to ground, this means that at high frequencies the gate of GM 2  effectively will be coupled to ground. When VPP is noisy at the high frequencies, the gate to source voltage (Vgs) of GM 2  will change, and the noise will reach the output at n 2 . In general, in order to have a good PSRR, the gate electrode of GM 2  must be strongly coupled to the VPP source at all frequencies so that the Vgs of GM 2  remains constant. 
     FIG. 2 shows another prior art regulator circuit which has good PSRR but does not conserve current from the charge pump. Here, the output of a differential amplifier gain stage GM 1  feeds the gate electrode of an NMOS transistor driver GM 2 . The drain of GM 2  is connected to the output. Also connected to the output is PMOS transistor P 1 , which is configured as a current source to VPP, with its source node at VPP. The gate of P 1  is connected to the gate of the current mirror input PMOS transistor P 2  whose source also is connected to VPP. There is a stabilizing capacitor C 3  for the amplifier between the output of GM 1  and the drain of P 1 . PMOS transistor, P 1 , is configured as a current source for GM 2 . The gate of P 2  is connected to its drain and the drain is DC coupled to ground by a current source shown by the intersecting circle symbol. The gate of P 1  is strongly AC coupled to VPP through the transconductance characteristic (GM) of current mirror transistor P 2 . 
     Here, the differential stage GM 1  inverted input receives the reference voltage IP and its output is coupled to the gate of GM 2 . The drain node of GM 2  is connected to the drain node of P 1  and the GM 2  source node is connected to ground. There is a voltage divider R 1 -R 2  having one end connected to the junction of the P 1  drain node and GM 2  drain node and the other end to ground. A feedback path fb is between the junction of the R 1 -R 2  divider and the non-inverted input of GM 1 . A load capacitor CL is connected across R 1 -R 2  to ground. 
     The PSRR of the circuit of FIG. 2 is determined by the characteristics of the current mirror P 1 -P 2 , such as its overdrive (Vgs-Vt or VDSAT) and transconductance (GM), as is known in the art. The PSRR of the circuit of FIG. 2 is relatively good because the current source to VPP (P 1 ) has both its gate node and source node strongly AC-coupled to VPP, such that its Vgs remains relatively constant at all frequencies. The problem with the circuit of FIG. 2 is that the current in P 1  must always be greater than the maximum possible current in I LOAD . Thus, even when I LOAD  is small, there is a significant current drain from the charge pump and VDD current is wasted. 
     OBJECTS OF THE INVENTION 
     An object of the invention is to provide a regulator for a NVM that exhibits both a high PSRR and minimal current consumption as compared to prior art regulators. 
     Another object of the present invention is to provide a high voltage VPP regulator having a differential stage that operates from a lower voltage VDD supply and an output stage connected to a VPP boosted supply. 
     An additional object is to provide a regulator to supply a boosted VPP voltage to a NVM, such as an EPROM, the regulator having an operational amplifier operating from a lower voltage VDD and receiving a feedback voltage from the load to adjust the current supply from a current mirror operating from VPP to control the load current. 
     BRIEF DESCRIPTION OF THE INVENTION 
     In accordance with the invention, a differential amplifier operating from the lower VDD voltage has one input connected to a reference bias voltage source. The amplifier output drives a gain stage that controls a current mirror operating from boosted voltage VPP, typically produced by a charge pump, and whose output is the load current that is supplied to the NVM transistor memory cells. The current mirror output flows through a voltage divider and a voltage taken from the divider is supplied as a feedback voltage to the other input of the differential amplifier. The amplifier regulates the load voltage and exhibits a good PSRR, while conserving VPP current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the present invention will become more apparent upon reference to the following specification and annexed drawings, in which: 
     FIGS. 1 and 2 show prior art regulator circuits; 
     FIG. 3 is a regulator circuit in accordance with the invention; 
     FIGS. 4A and 4B are biasing circuits for the regulator; and 
     FIG. 5 is a diagram of another embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 shows a regulator circuit in accordance with the invention that is capable of a high PSRR, while at the same time conserving current when I LOAD  is low. There is a differential amplifier GM 1 , a first gain stage, that operates from VDD (the normal supply voltage). The VDD supply is the supply of a charge pump (not shown) which generates a boosted level voltage, VPP. GM 1  does not consume any VPP current, i.e., current from the charge pump. The amplifier GM 1  is an operational type amplifier and can be formed of a differential transistor pair that, as described below, drives an active current mirror load. The differential stage GM 1  has two inputs. The inverting input receives a reference voltage, IP. The non-inverting input receives a feedback signal, FB, as will be explained below. 
     The output of GM 1  drives the rate of a PMOS source follower, transistor P 3 . The drain of P 3  is connected to ground and the output of P 3  at its source node is connected to drive the source code of a second gain stage, NMOS transistor, GM 2 . The gate of GM 2  is biased at a fixed voltage called bias  1 . The details of the biasing voltage source are discussed below with reference to FIGS. 4 and 5. 
     The drain node of GM 2  is connected at n 2  to the gate and drain nodes of a PMOS transistor P 2 . The gate of P 2  is also connected to the gate of PMOS transistor P 1 . The source nodes of P 1  and P 2  are connected to the boosted charge pump voltage, VPP. The series connected transistors P 3  and GM 2  determine the current in the branch of the circuit including P 2 . The current in the P 3 -GM 2  branch is mirrored to P 1  by P 2 . There can also be a multiplication factor between P 2  and P 1 , as is well known in the art. 
     The output, OP, of the regulator is across a voltage divider R 1 -R 2  connected between the drain of the current mirror output P 1  and ground. There is current flow from VPP through P 1  and the divider R 1 -R 2  to ground. R 1  is connected between OP and FB, the feedback supply point. R 2  is connected between FB and ground. As in the circuits of FIGS. 1 and 2, there is a load capacitor CL connected to ground. There is a feedback connection FB from the junction of R 1 -R 2  to the non-inverted input of GM 1 . The load I LOAD  is shown, which is the NVM memory cells. Also, the Miller capacitor Cm is shown connected between OP and the gate of P 3 . 
     The circuit described up to this point is a 2-stage operational amplifier with the two gain stages GM 1  and GM 2  having two high impedance nodes, n 1  and OP. The nodes n 1  and OP have high impedance because they are connected only to drains of transistors in saturation, or gates or capacitors, or large resistors. All of these elements have high impedance. 
     The stabilization of the regulator is accomplished by the Miller capacitor Cm between the high-impedance nodes n 1  and OP. In the circuit of FIG. 3 the two high impedance nodes n 1  and OP are at opposite phase because the inversion of the signal at n 1  by P 1 . That is, the signal applied to the gate of the PMOS P 1  appears inverted at its drain, which is the point OP. Because of this, the Miller capacitor provides negative feedback from OP to P 3  as is required by such compensation capacitors. 
     The dominant pole of the circuit is defined by GM 1 /Cn 1 , where Cn 1  is the total capacitance at node n 1 . The dominant capacitance at n 1  is the Miller capacitance which is approximately A 2 XCn 1  which A 2  is the second stage GM 2  gain. 
     The secondary pole is determined by the transconductance of GM 2  divided by Cl, as is known by those skilled in the art. The condition for stability in a two pole operational amplifier circuit is that the secondary pole is well below the unity-gain frequency. This is accomplished by proper choice of the gain of GM 1  and GM 2  and the value of capacitor Cm, as is well known in the art. Specifically, the gain of GM 1  should be small, the gain of GM 2  should be large and Cm should position the poles such that the secondary pole is 3x the closed loop gain frequency. This is known in the art as pole-splitting. 
     The circuit of FIG. 3 conserves current. Firstly, GM 1  operates from VDD, which is a less resource costly supply compared to the source that produces the boosted VPP. This is because the low efficiency when generating VPP. That is, the charge pump does not have to pump voltage from VDD up to the VDD level to supply it to GM 1 . Secondly, the feedback loop FB from the output to GM 1  adjusts the current in P 1  according to I LOAD  That is, for example, as I LOAD  increases, the feedback loop increases the current in the P 3 /GM 2 /P 2  path, as well as P 1 , providing just enough current to drive I LOAD  and R 2 -R 1  to the regulated output voltage. 
     There can be a multiplication factor such as for example 10:1, between P 1 :P 2  so that the middle branch (P 3 , GM 2 , P 2 ) of the circuit does not consume significant current. When I LOAD  is low, the feedback will adjust P 1  to provide just enough current to supply the load current. Thus, current from the VPP charge pump supply is not wasted, as in the circuit shown in FIG.  1 . 
     The circuit of FIG. 3 is also configured such that it has a high PSRR. The gate of P 1 , which supplies the load current from the VPP source, is strongly linked to VPP by the transconductance of P 2 . Thus, it has a PSRR similar to that of the circuit shown in FIG.  2 . That is, the Vgs of P 1  remains constant at all frequencies of VPP ripple, since both its gate and source are strongly coupled to VPP. Accordingly, the circuit of FIG. 3 has the advantages of both prior art circuits of FIGS. 1 and 2 without the disadvantages of either one. 
     FIGS. 4A and 4B show two possible biasing sources of the bias  1  voltage for the second gain stage GM 2  of FIG.  3 . FIG. 4A shows a series connected resistor RF connected between VDD and bias  1  and a capacitor CF connected between bias  1  and ground. This produces a filtered VDD at the junction of RF and CF that is the bias voltage bias  1 . That is, high frequency noise from VDD is filtered to ground by CF and is not amplified by GM 2 . 
     A second bias circuit is shown in FIG.  4 B. Here, there is a stacked Vt circuit similar to that formed by GM 2  and P 3  in FIG.  3 . This is a series connection of the source node of an NMOS transistor GM 2  to the source node of a PMOS transistor P 4 . The drain and gate nodes of GM 2  are connected to a current source from VPP or VDD. The drain and gate nodes of P 4  are connected to ground. The bias 1 voltage is taken from the gate/drain of GM 2 . Here the VDD noise is rejected since bias 1 is AC-coupled to ground. 
     A second embodiment of the invention is shown in FIG.  5 . Similar elements as in FIG. 3 have the same reference characters. Here, there is the differential amplifier GM 1  having a reference voltage IP at the inverting input and a feedback input FB, described below, at the non-inverting input. The operating voltage for GM 1  is from the VDD source. 
     The output of GM 1  is connected to the gate node of a gain stage NMOS transistor GM 2  whose source node is connected to ground. The drain node output of GM 2  is connected to the gate and drain nodes of a current mirror input PMOS transistor P 2  whose source is connected to the charge pump output voltage, VPP. The current output determined by GM 2  is mirrored via P 2  to the output PMOS transistor P 1  of the current mirror. The PMOS transistor P 1  gate node is connected to the drain node output of P 2  and the source node of P 1  is connected to VPP. 
     The drain node of P 1  is connected to the output (OP) of the regulator. The output, OP, is also connected to series connected resistors R 1  and R 2 , which form a voltage divider between OP and ground. The first terminal of R 1  is connected to OP, while the second terminal of R 1  is connected to FB. The first terminal of R 2  is connected to FB, while its second terminal is connected to ground. FB is also connected to the non-inverting input of GM 1 . The output, OP, can be connected to a load, which can be capacitive or resistive, as represented in FIG. 3 by the capacitor CL and the current source attached to OP. 
     A capacitor CL is connected from the drain node of P 1  across the voltage divide R 1 -R 2  to ground. A feedback FB signal is provided from the junction of the voltage divider R 1 -R 2  to the non-inverting input of GM 1 . 
     As seen, the circuit of FIG. 5 differs from FIG. 3 in that Cm is omitted. Also, P 3  is omitted and the output of the differential amplifier GM 1  is fed directly to the gate of gain stage transistor GM 2 . Because of the absence of P 3 , the two high impedance nodes n 1  and OP are in phase with each other, so it is not possible to use Miller capacitor compensation. The amplifier GM 1  can be stabilized by placing a very large value capacitor (not shown) at the output OP. In this manner, the dominant pole of the system becomes the one associated with OP, while the secondary pole is GM 1 /Cn 1 . It is important that the transconductance of GM 1  be very large, and that the transconductance of GM 2  and Cn 1  be small, so that the secondary pole will be below the unity gain frequency. 
     The circuit of FIG. 5 exhibits similar PSRR and VPP current consumption as the circuit shown in FIG.  3 . The advantage of this embodiment is that it has a faster response time because of the large transconductance of GM 1  and lower capacitance at n 1 . The disadvantage is that this embodiment requires a very large output capacitor to maintain stability and may be somewhat unstable at high I LOAD  values because this will cause the transconductance of GM 2  to increase. 
     It is understood that MOSFETs are symmetrical devices with respect to the source and drain and thus for purposes of the invention the designation of source and drain should be considered in the broadest sense. 
     Specific features of the invention are shown in one or more of the drawings for convenience only, as each feature may be combined with other features in accordance with the invention. Alternative embodiments will be recognized by those skilled in the art and are intended to be included within the scope of the claims.