Abstract:
An apparatus, system and method of automatically computing power consumption estimation of a chip are provided. The apparatus, system and method include determining all circuit blocks or macros embedded in the chip and retrieving from a file, into which pre-generated power consumption values of the macros are stored, the power consumption value of each macro. After doing so, the power consumption value of the chip is automatically computed. The apparatus, system and method also compute a desired power consumption estimation of the chip as well as a plurality of power densities. A desired power consumption estimation is based on a desired voltage and a desired frequency while a power density is power used in a certain area. Further, the apparatus, system and method reproduces the floorplan of the chip and represents each area within the chip by a different color to illustrate hot spots and cool spots.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Technical Field  
           [0002]    The present invention is directed generally to integrated circuit technology. More specifically, the present invention is directed to a method of automating chip power consumption estimation.  
           [0003]    2. Description of Related Art  
           [0004]    As is well known in the art, the more digital logic integrated in a chip, the more power the chip consumes. It is further well known that many important design issues and parameters are strongly dependent on the power dissipation of the chip. And, since only a limited amount of heat can be dissipated through a chip&#39;s package, it is imperative that power consumption of chips be taken into account during the design process.  
           [0005]    To this end, many techniques have been developed to estimate power consumption of chip at the design stage. One such technique includes pre-generating estimated power consumption values of circuit blocks or macros and storing the values in a file. These macros may be used once or a plurality of times to design different chips. In any event, once a chip incorporating these macros is designed, its estimated power consumption may quickly be calculated. To do so, one needs only determine the different macros as well as the number of instances each macro is used in the chip. Once this is determined, the estimated value of the macros may be obtained from the file and added together to arrive at the estimated power consumption of the chip.  
           [0006]    Presently, the above-described chip-level power estimation is performed manually. This can be quite a time-consuming and calculation-intensive endeavor. For example, a typical microprocessor may contain more than one thousand (1,000) unique macros and each macro may be used more than 20,000 times. Hence, to compute the power estimation of the chip, 1,000 different values have to be retrieved from the file and used each more than 20,000 times.  
           [0007]    Further, the design of a chip may constantly be changing. For every change, a new power estimation may have to be calculated. Thus, the amount of work that may have to be performed in obtaining the power estimation of a chip during its design process may be staggering. And, as with any task performed manually, this power estimation calculation is prone to errors.  
           [0008]    Thus, what is needed is an apparatus, system and method of automating chip power consumption estimation.  
         SUMMARY OF THE INVENTION  
         [0009]    The present invention provides an apparatus, system and method of automatically computing power consumption estimation of a chip. The apparatus, system and method include determining all circuit blocks or macros embedded in the chip and retrieving from a file, into which pre-generated power consumption values of the macros are stored, the power consumption value of each macro. After doing so, the power consumption value of the chip is automatically computed.  
           [0010]    The apparatus, system and method also compute a desired power consumption estimation of the chip as well as a plurality of power densities. A desired power consumption estimation is based on a desired voltage and a desired frequency while a power density is power used in a certain area. Further, the apparatus, system and method reproduces the floorplan of the chip and represents each area within the chip by a different color to illustrate hot spots and cool spots.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0012]    [0012]FIG. 1 is a block diagram of a chip.  
         [0013]    [0013]FIG. 2 illustrates an exemplary file associated with a chip.  
         [0014]    [0014]FIG. 3 illustrates a cross-reference table in an exemplary file associated with a first functional unit.  
         [0015]    [0015]FIG. 4 illustrates a cross-reference table in an exemplary file associated with a second functional unit.  
         [0016]    [0016]FIG. 5 illustrates a cross-reference table in an exemplary file associated with a sub-functional unit.  
         [0017]    [0017]FIG. 6 depicts a list of different orientations and their shorthand notations.  
         [0018]    [0018]FIG. 7 depicts an inverted tree-structure of a file system.  
         [0019]    [0019]FIG. 8 illustrates a first cross-reference table of a datafile used by the present invention.  
         [0020]    [0020]FIG. 9 illustrates a second cross-reference table of a datafile used by the present invention.  
         [0021]    [0021]FIG. 10 is a flow diagram of a process used to retrieve physical attributes from the files in FIGS. 2, 3,  4  and  5 .  
         [0022]    [0022]FIG. 11 is a flow diagram of a process used to automatically compute power consumption estimation.  
         [0023]    [0023]FIG. 12 is a block diagram of a data processor that may be used by the invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0024]    In the following disclosed implementation of the invention, a software program is used to retrieve information stored in files in order to reconstruct a chip floorplan. From the floorplan, instance counts of macros used in the chip may be obtained. Once the instance counts are obtained, the power consumed by each macro may be retrieved from a database to calculate the power consumption of the chip or any functional unit therein. Further, power density may be computed for any macro, functional unit or the chip itself. Power density is the power over a particular area of the chip.  
         [0025]    In designing high frequency/performance VLSI (very large scale integration) processors with significant architectural complexity, a concept known as chip integration is often used. In chip integration, a combination of critical physical design techniques is given prioritized consideration throughout all phases of the design process. These critical design techniques include power distribution, high-speed clock design, wiring methodologies, circuit macro floorplanning, chip-level timing/extraction, noise prevention, electrical analysis, design verification, and time to market. This concept is a key requirement necessary not only to achieve high frequency of operation, but also to meet area targets within a defined architecture and ensure a robust and reliable design for transistor counts from 10 to 100 million.  
         [0026]    One of the standard outputs of an integration tool is a plurality of files that contain each a list of objects and a number of their instances in the chip. An object may be a macro or a functional unit. An example of a functional unit is an instruction unit; a branch control element unit, which contains the cache and its associated controls; an execution unit, which contains both a fixed-point unit and a floating-point unit; or a register checkpoint unit, used for full error checking and processor recovery.  
         [0027]    Each generated file is associated with a functional unit. In this case, the chip itself may be regarded as a functional unit and will therefore have an associated file (i.e., a chip file). The chip file contains a list of all the macros and functional units that make up the chip. The listed functional units in the chip file will each have their own associated file (i.e., a unit file). If a functional unit comprises a sub-functional unit, the sub-functional unit will also have an associated file (i.e., a sub-unit file) and so on. For example, the execution unit listed above has a fixed-point unit and floating-point unit. Thus, if the execution unit is incorporated in the chip, it will have a unit file that lists the fixed-point unit and the floating-point unit and any additional macro that it contains. The fixed-point unit and the floating-point unit will each have an associated sub-unit file.  
         [0028]    [0028]FIG. 1, which depicts a hypothetical chip A  100 , is used as an illustration. Chip A  100  includes macros A 1    102 , A 2    104 , A 3    106  and functional units A a    120  and A b    130 . Consequently, in the file associated with chip A  100 , macros A 1    102 , A 2    104 , A 3    106  and functional units A a  and A b  will be listed. There will also be a unit file for functional units A a  and A b . The unit file for functional unit A a    120  will contain macros A a1    122 , A a2    126  and A a3    124  whereas that for the functional unit A b    130  will contain macro A b1    132  and functional unit A bA    134 . As functional unit A b    130  contains a sub-functional unit (i.e., functional unit A bA ), there will also be a sub-unit file. The sub-unit file will contain macros A bA1    136  and A bA2    138 .  
         [0029]    Thus, the different files that are associated with the chip may be regarded as an inverted tree-structure where the macros are leaves and the functional units are nodes or branches. FIG. 7 illustrates such an inverted tree-structure where file A  702 , unit files A a    706  and A b    712  as well as sub-unit file A bA    722  are nodes and macros A 1    704 , A 2    708 , A 3    710 , A a1    714 , A a2    716 , A a3    718 , A b1    720 , A bA1    724  and A bA2    726  are leaves.  
         [0030]    In addition to having a list of the macros and functional units that make up a chip and/or a functional unit, each file may provide location, orientation, shape/size of each macro and functional unit listed therein. FIG. 2 illustrates an exemplary file. The file is associated with chip A, which has reference coordinates X 0 Y 0 , orientation O 0 , width W 0  and height H 0 . The width W 0  and height H 0 , when used in conjunction with reference coordinates X 0 Y 0 , allow the shape and size of chip A to be reproduced. Particularly, the shape of all objects (i.e., chips, macros and functional units) is assumed to be a rectangle with the listed reference coordinates being the bottom left corner of the rectangle. Hence, the shape and size of the rectangle representing chip A may easily be drawn using the reference coordinates and its width and height.  
         [0031]    Orientation O 0  provides more information about Chip A. FIG. 6 depicts a list of different orientations and their shorthand notations. The letter N in N0, N90, N180 and N270 signifies that an object, when recreated, should be a true image, as opposed to a mirror image, of itself. The 0, 90, 180 and 270 are degrees of rotation. The letter Y, in the case of Y0, Y90, Y180 and Y270, denotes that a recreated object should be a mirror image of itself. And, just as before the 0, 90, 180 and 270 are degrees of rotation. Since the rectangles representing the macros and functional units integrated in chip A will be drawn relative to the rectangle representing chip A, then the coordinates X 0 Y 0  may be regarded as (0,0) and the orientation O 0  may be N0.  
         [0032]    Returning to FIG. 2, the coordinates for macro A 1  are X A1 Y A1 , and as mentioned above, they are relative to the coordinates X 0 Y 0  of Chip A. Likewise, coordinates X A2 Y A2 , X A3 Y A3 , X Aa Y Aa  and X Ab Y Ab  of macros A 2 , A 3  and functional units A a  and A b , respectively, are relative to the coordinates X 0 Y 0 . Again, using the coordinates of each object, in conjunction with the width and height of the object, allows for the object to be reproduced.  
         [0033]    [0033]FIGS. 3 and 4 depict the files associated with functional units A a  and A b  in FIG. 2 and FIG. 5 illustrates the file associated with sub-functional unit A bA  in FIG. 4. As in FIG. 2, each object in FIGS. 3, 4 and  5  has a set of reference coordinates, a width and a height as well as an orientation. The coordinates of each macro or functional unit in a unit or sub-unit file are relative to the coordinates of the object (i.e., the functional unit) with which the file is associated. Thus, to have the reference coordinates of a macro of a functional unit in a sub-unit file be relative to the coordinates of a chip, the reference coordinates of each intervening functional unit have to be summed up. For example, X AbA2 Y AbA2  of macro A bA2    138  of FIG. 1 may be made relative to the coordinates of chip A (i.e., X 0 Y 0 ) by having:  
         
       X′ 
       AbA2 
       =X 
       AbA2 
       +X 
       AbA 
       +X 
       Ab  
     
         
       Y′ 
       AbA2 
       =Y 
       AbA2 
       +Y 
       AbA 
       +Y 
       Ab  
     
         [0034]    where X′ AbA2  and Y′ AbA2  are the coordinates of the macro A bA2  that are relative to X 0 Y 0 , X AbA2  and Y AbA2  are the coordinates of macro A AbA2  relative to coordinates of functional unit A bA    134  of FIG. 1, X AbA  and Y AbA  are the coordinates of functional unit A bA  relative to coordinates of functional unit A b    130  of FIG. 1 and X Ab  and Y Ab  are the coordinates of functional unit A b  relative to coordinates of chip A  100  (i.e., X 0 Y 0 ) of FIG. 1.  
         [0035]    Likewise, the orientation of a macro or a functional unit in a unit or sub-unit file is relative to the orientation of the object with which the file is associated. As in the case of the reference coordinates, an orientation of a sub-functional unit or macro may be made relative to a chip in which the functional unit or macro is embedded by adding the orientation of all intervening functional units to the orientation of the sub-functional unit or macro. For example, if the orientation of the macro A bA2    138  was 270° and the orientation of functional unit A bA    134  was 180° and the orientation of functional unit A b    130  was 90° then the orientation of the macro A bA2  relative to chip A would be:  
         270°+180°+90°=540° or 180° 
         [0036]    As previously mentioned, the invention is a software program that uses information stored in the files described above to reconstruct a chip floorplan as well as computing the chip&#39;s power consumption estimation. The program accesses each file generated by the integration tool to obtain physical attributes of each macro or functional unit in the chip. For example, in the case of chip A in FIG. 1, the program will access the files shown in FIGS. 2, 3,  4  and  5  to obtain the reference coordinates, width, height and orientation of each macro and functional unit embedded therein. The program will also access the database where the power consumption estimation of the macros is stored to retrieve the power consumption of each macro used in chip A.  
         [0037]    As the program is accessing the files and the power database, it will build a database to store the retrieved information. FIG. 8 depicts the database in which information (including power consumption) regarding the macros and functional units used in chip A is stored. After collecting and storing the information in the database, the invention may reproduce the floorplan of the chip, compute the raw power consumption estimation of the chip as well as calculate different raw power densities.  
         [0038]    The invention may also compute desired power consumption estimations. To do so, the invention uses the following formula:  
           P   desired   =P   raw ( V   desired   /V   raw ) 2 ( F   desired   /F   raw )  
         [0039]    where P desired  is the power that is being computed, P raw  is the power estimation of the power that is being computed, V desired  is the voltage at which P desired  is to be computed, V raw  is the voltage at which P raw  was computed, F desired  is the frequency at which P desired  is to be computed and F raw  is the frequency at which P raw  was computed.  
         [0040]    Thus, if P desired  is to be computed, V desired  and F desired  are to be provided to the program, otherwise only P raw  will be computed. Note that the power consumption of each macro includes V raw  and F raw .  
         [0041]    [0041]FIG. 9 is a table into which all calculated values may be stored. This table may be part of the database built by the program. The table has a P raw  column  902  into which the P raw  of each object (i.e., chip, units and macros) is stored. The P raw  of an object may be calculated or retrieved. P raw    910  of the chip, P raw    920  of unit A a , P raw    930  of unit A b  and P raw    940  of unit A bA  are calculated whereas the ones for the macros are retrieved from files  2 ,  3 ,  4  and  5 .  
         [0042]    The table also has a P raw  density column  904 , a P desired  column  906  and P desired  density column  908 . The P raw  density, P desired  and P desired  density of all the objects are calculated. The P desired  of an object is calculated according to the equation disclosed above. The P raw  density and P desired  density are a particular power over a particular area. For example, the P raw  density of the chip is the P raw  of the chip divided by the total area of the chip.  
         [0043]    Once the different values are calculated, the database may be disseminated as a text file or as an HTML file or browser page. Further, graphical representation of the data may be generated. For instance, the chip floorplan may be reproduced with a different colored shading to illustrate areas that have a high power consumption (i.e., hot spots) or low power consumption etc.  
         [0044]    [0044]FIG. 10 is a flow chart of a procedure that may be used to retrieve physical attributes of objects from the files in FIGS.  2 - 5 . Physical attributes include reference coordinates, orientation, width and height of all objects as well as power consumption values of the macros. The process starts when the invention is asserted (step  1000 ). Generally, the chip file will be passed to the invention as an attribute. Once done, the invention will create a database into which all physical attributes retrieved will be stored. The invention will then open the chip file and read the physical attributes of the chip. After retrieving and storing the physical attributes of the chip into the database, the invention will scrutinize the first object in the chip file to determine whether it is a macro or a unit. If the first object is a macro, the invention will read and store the physical attributes of the macro into the database and scrutinize the next object. If the next object is again a macro, the invention will again read and store the physical attributes of the macro. This will continue until the physical attributes of all the objects (macros) are read and stored in the database or a (functional) unit is encountered (steps  1002 - 1016 ).  
         [0045]    When a (functional) unit is encountered, the invention will open the file associated with the unit to retrieve the unit&#39;s physical attributes. After retrieving and storing the unit&#39;s physical attributes in the database, the invention will scrutinize the first object in the file. If the first object is a macro, the macro&#39;s physical attributes will be retrieved and stored in the database. Then the next object will be scrutinized. Again, if it is a macro its physical attributes will be retrieved and stored. As stated before, this will continue until the physical attributes of all the objects (macros) are read and stored in the database or a (functional) unit is encountered (steps  1018 - 1030 ).  
         [0046]    Because there may be functional units embedded into a functional unit, there may be a plurality of unit files opened at the same time. However, the invention will only retrieve physical attributes from the last (i.e. current) unit file to have been opened. When the attributes of the last object in a unit file are read and stored, a check is made to determine whether a unit file, opened prior to the current unit file, is till opened. If so, the invention will close the current unit file and will resume retrieving physical attributes of objects from the previously opened (now current) unit file. This will be done all physical attributes of all objects in all the files (unit or chip) are retrieved and stored into the database (steps  1032 - 1034 ).  
         [0047]    After retrieving the physical attributes of all the objects associated with the chip, the invention may draw the chip floorplan and compute the power estimation and density of the chip as well as those of all the objects in the chip. Further, based on power consumption thresholds, the invention may represent different areas of the chip in different colors to denote hot and cool spots etc. Once done, the invention may store all calculations, drawings etc. into the database. This is illustrated in steps  1100 - 1116  of FIG. 11.  
         [0048]    [0048]FIG. 12 is a block diagram of a data processing system on which the invention may be executed. Data processing system  1200  employs a peripheral component interconnect (PCI) local bus architecture. Although the depicted example employs a PCI bus, other bus architectures such as Accelerated Graphics Port (AGP) and Industry Standard Architecture (ISA) may be used. Processor  1202  and main memory  1204  are connected to PCI local bus  1206  through PCI bridge  1208 . PCI bridge  1208  also may include an integrated memory controller and cache memory for processor  1202 . Additional connections to PCI local bus  1206  may be made through direct component interconnection or through add-in boards. In the depicted example, local area network (LAN) adapter  1210 , SCSI host bus adapter  1212 , and expansion bus interface  1214  are connected to PCI local bus  1206  by direct component connection. In contrast, audio adapter  1216 , graphics adapter  1218 , and audio/video adapter  1219  are connected to PCI local bus  1206  by add-in boards inserted into expansion slots. Expansion bus interface  1214  provides a connection for a keyboard and mouse adapter  1220 , modem  1222 , and additional memory  1224 . Small computer system interface (SCSI) host bus adapter  1212  provides a connection for hard disk drive  1226 , tape drive  1228 , and CD-ROM drive  1230 . Typical PCI local bus implementations will support three or four PCI expansion slots or add-in connectors.  
         [0049]    An operating system runs on processor  1202  and is used to coordinate and provide control of various components within data processing system  1200  in FIG. 12. The operating system may be a commercially available operating system, such as Windows  2000 , which is available from Microsoft Corporation. An object oriented programming system such as Java may run in conjunction with the operating system and provide calls to the operating system from Java programs or applications executing on data processing system  1200 . “Java” is a trademark of Sun Microsystems, Inc. Instructions for the operating system, the object-oriented operating system, and applications or programs are located on storage devices, such as hard disk drive  1226 , and may be loaded into main memory  1204  for execution by processor  1202 .  
         [0050]    Those of ordinary skill in the art will appreciate that the hardware in FIG. 12 may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash ROM (or equivalent nonvolatile memory) or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in FIG. 12. Also, the processes of the present invention may be applied to a multiprocessor data processing system.  
         [0051]    The depicted example in FIG. 3 is not meant to imply architectural limitations. For example, data processing system  1200  may also be a notebook computer or hand held computer. Data processing system  1200  also may be a kiosk or a Web appliance. In any case, the invention may be stored in any memory device employed by the data processing system  1200 .  
         [0052]    The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. For example, the floorplan, physical attributes etc. of a chip may also be obtained from a design instead from the files generated by the integration tool. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.