Abstract:
A display driving circuit. The circuit comprises a data driver outputting a first, second, third and fourth data signal through a data line, a scan driver outputting a first and second scan signal through a first and second scan line, a first, second, third and fourth display cell receiving the first, second, third and fourth data signal through the data line and receiving the first and second scan signal through the first and second scan line, a first switch coupling the first display cell to the data line when the first scan and data signals are asserted, and isolating them from each other when the first scan and second data signals are asserted, and a second switch coupling the third display cell to the data line when the second scan and third data signals are asserted, and isolating them from each other when the second scan and fourth data signals are asserted.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a display driving circuit and particularly to a display driving circuit with fewer data drivers. 
   2. Description of the Prior Art 
     FIG. 1  is a diagram showing a conventional display driving circuit  1 . It includes two data drivers  121  and  122 , a scan driver  11 , a pixel matrix composed of display cells  13 , and switches  161  and  162  composed of transistors. Each of the display cells  13  in the odd columns of the pixel matrix receives a data signal through a data line  151  from the data driver  121  or  122 . Each of the display cells  13  in the even columns of the pixel matrix receives a data signal through a data line  152  from the data driver  121  or  122 . The display cells  13  also receive scan signals through scan lines  14  from the scan driver  11 . To reduce the number of the data drivers, data line  151  and  152  are respectively coupled to the display cells  13  in the odd and even column of the pixel matrix share the same data terminal as the data driver through the switches  161  and  162  controlled by signals SW 1  and SW 2 . When one of the scan signals is asserted, the odd and even display cells  13  in the scanned row of the matrix receive the data signal output from the same terminal of the data driver  121  or  122  by turns. In  FIG. 1 , for example, the number of the data drivers is half of that not using the switches to share the data terminals since each data terminal provides the data signals to two columns of display cells of the pixel matrix. 
   However, in the conventional display driving circuit, the switching frequency of the switches  161  and  162  is n times the frame rate, wherein n is the number of the columns in the pixel matrix. For example, the switching frequency of the switches in a display having 768 pixel columns and a frame rate of 60 Hz. is 46080 Hz. Such a switching frequency is much higher than that of the thin-film transistors (TFTs) used in the display cells  13 . This results in high current stress which degrades the reliability of the circuit. 
   SUMMARY OF THE INVENTION 
   The object of the present invention is to provide a display driving circuit with switches for data terminal sharing individually for each of display cells. This lowers the switching frequency of the switches. 
   The present invention provides a display driving circuit comprising a data driver sequentially outputting a first, second, third and fourth data signal through a data line, a scan driver outputting a first and second scan signal through a first and second scan line respectively, a first, second, third and fourth display cell respectively receiving the first, second, third and fourth data signal through the data line, the first and second display cell commonly receiving the first scan signal through the first scan line, and the third and fourth display cell commonly receiving the second scan signal through the second scan line, and a first and second switch, the first switch electrically coupling the first display cell to the data line when the first scan and data signals are asserted, and electrically isolating the first display cell from the data line when the first scan and second data signals are asserted, and the second switch electrically coupling the third display cell to the data line when the second scan and third data signals are asserted, and electrically isolating the first display cell from the data line when the second scan and fourth data signals are asserted. 
   The present invention provides another display driving circuit comprising a data driver sequentially outputting a first, second, third and fourth data signal through a data line, a scan driver outputting a first and second scan signal through a first and second scan line respectively, a first, second, third and fourth display cell respectively receiving the first, second, third and fourth data signal through the data line, the first and second display cell commonly receiving the first scan signal through the first scan line, and the third and fourth display cell commonly receiving the second scan signal through the second scan line, and a first and second switch, the first switch electrically coupling the first display cell to receive a swing signal when the first scan signal is asserted, wherein the swing signal is asserted to couple the first display cell to receive the first data signal when the first data signal is asserted, and the second switch electrically coupling the third display cell to receive the swing signal when the second scan signal is asserted, wherein the swing signal is asserted to couple the third display cell to receive the third data signal when the third data signal is asserted. 
   The present invention provides still another display driving circuit comprising a data driver sequentially outputting a data signal through a data line, a scan driver outputting a scan signal through a scan line, a first transistor having a gate coupled to the scan line and a drain coupled to the data line, a second transistor having a gate coupled to receive a swing signal and a drain coupled to the data line, and being sequentially turned on and off by the swing signal when the scan signal is asserted, a third transistor having a gate coupled to the scan line and a drain coupled to a source of the second transistor, and a first and second capacitor respectively coupled to sources of the first and third transistor. 
   The present invention further provides a display driving circuit comprising a data driver sequentially outputting a data signal through a data line, a scan driver outputting a scan signal through a scan line, a first transistor having a gate coupled to the scan line and a drain coupled to the data line, a second transistor having a drain coupled to the data line, a third transistor having a gate coupled to the scan line, a source coupled to a gate of the second transistor and a drain coupled to receive a swing signal, wherein when the scan signal is asserted, the third transistor is turned on to electrically couple the gate of the third transistor to receive the swing signal and the second transistor is sequentially turned on and off, and a first and second capacitor respectively coupled to the sources of the first and third transistor. 
   Thus, in the present invention, each pair of display cells are equipped with a switch for data terminal sharing. The switching frequency of the switches is lowered to the frame rate, which eliminates the reliability issue in the conventional display driving circuit. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention. 
       FIG. 1  is a diagram showing a conventional display driving circuit. 
       FIGS. 2A and 2B  are diagrams showing a display driving circuit and signal timing thereof according to a first embodiment of the invention. 
       FIGS. 3A and 3B  are diagrams showing a display driving circuit and signal timing thereof according to a second embodiment of the invention. 
       FIGS. 4A and 4B  are diagrams showing a display driving circuit and signal timing thereof according to a third embodiment of the invention. 
       FIGS. 5A and 5B  are diagrams showing a display driving circuit and signal timing thereof according to a fourth embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2A  is a diagram showing a display driving circuit  2  according to a first embodiment of the invention. It includes a data driver  21 , a scan driver  22 , a pixel matrix composed of four (for example) display cells  231 ˜ 234 , and two switches  241  and  242 . The data driver  21  outputs data signals for the display cells  231 ˜ 234  through a data line  25 . The scan driver  22  outputs scan signals S 1  and S 2  through scan lines  261  and  262 . The display cells  231  and  233  commonly receive the scan signal S 1  through the scan line  261 , and the display cells  232  and  234  commonly receive the scan signal S 2  through the scan line  262 . The display cells  231 ˜ 234  respectively receive the corresponding data signals commonly through the data line  25 . The switches  241  and  242  are respectively coupled between the data line  25  and the display cell  233 , and between the data line  25  and the display cell  234 . 
   The display cells  231  and  232  in the odd columns of the pixel matrix are respectively composed of a transistor M 21  and a capacitor C 21 , and a transistor M 22  and C 22 . The transistor M 21  and M 22  have gates respectively coupled to the scan lines  261  and  262 , drains commonly coupled to the data line  25 , and sources coupled to the capacitors C 21  and C 22 . The display cells  233  and  234  in the even columns of the pixel matrix are respectively composed of a transistor M 23  and a capacitor C 23 , and a transistor M 24  and C 24 . The transistor M 23  and M 24  have gates respectively coupled to the scan lines  261  and  262 , drains respectively coupled to the switches  241  and  242 , and sources coupled to the capacitors C 23  and C 24 . The switches  241  and  242  are transistors M 25  and M 26  respectively. The transistors M 25  and M 26  have gates coupled to receive a signal Swing and drains coupled to the data line  25 . 
     FIG. 2B  is a diagram showing signal timing of the driving circuit in  FIG. 2A . 
   The scan period when the scan signal S 1  is asserted (has a logic high level) is divided into two sub-periods T 1  and T 2 . During the period T 1 , the signal Swing is asserted (has a logic high level) and turns on the transistor M 25  (closes the switch  241 ). The display cell  233  in the even column of the pixel matrix receives the data signal from the data driver  21  through the data line  25 . During the period T 2 , the transistor M 25  is turned off (the switch  241  is opened) by the signal Swing. The display cell  231  in the odd column of the pixel matrix receives the data signal from the data driver  21  through the data line  25 . It is noted that although the display cell  231  also receives the data signal for the display cell  233  during the period T 1 , it is refreshed by the data signal received during the period T 2 . 
   The next scan period when the scan signal S 2  is asserted (has a logic high level) is divided into two sub-periods T 3  and T 4 . During the period T 3 , the signal Swing is asserted (has a logic high level) and turns on the transistor M 26  (closes the switch  242 ). The display cell  234  in the even column of the pixel matrix receives the data signal from the data driver  21  through the data line  25 . During the period T 4 , the transistor M 26  is turned off (the switch  242  is opened) by the signal Swing. The display cell  232  in the odd column of the pixel matrix receives the data signal from the data driver  21  through the data line  25 . It is noted that although the display cell  232  also receives the data signal for the display cell  234  during the period T 3 , it is refreshed by the data signal received during the period T 4 . 
     FIG. 3A  is a diagram showing a display driving circuit  3  according to a second embodiment of the invention. It includes a data driver  31 , a scan driver  32 , a pixel matrix composed of four (for example) display cells  331 ˜ 334 , and two switches  341  and  342 . The data driver  31  outputs data signals for the display cells  231 ˜ 234  through a data line  35 . The scan driver  32  outputs scan signals S 1  and S 2  through scan lines  361  and  362 . The display cells  331  and  333  commonly receive the scan signal S 1  through the scan line  361 , and the display cells  332  and  334  commonly receive the scan signal S 2  through the scan line  362 . The display cells  331  and  332  respectively receive the corresponding data signals commonly through the data line  35 . The display cells  333  and  334  respectively receive the corresponding data signals via the switches  341  and  342 . The switches  341  and  342  are respectively coupled between the data line  35  and the display cell  333 , and between the data line  35  and the display cell  334 . 
   The display cells  331  and  332  in the odd columns of the pixel matrix are respectively composed of a transistor M 31  and a capacitor C 31 , and a transistor M 32  and C 32 . The transistor M 31  and M 32  have gates respectively coupled to the scan lines  361  and  362 , drains commonly coupled to the data line  35 , and sources coupled to the capacitors C 31  and C 32 . The display cells  333  and  334  in the even columns of the pixel matrix are respectively composed of a transistor M 33  and a capacitor C 33 , and a transistor M 34  and C 34 . The transistors M 33  and M 34  have gates respectively coupled to the scan lines  361  and  362 , drains respectively coupled to the switches  341  and  342 , and sources coupled to the capacitors C 33  and C 34 . The switches  341  and  342  are transistors M 35  and M 36  respectively. The transistor M 35  has a gate coupled to the scan line  362  and the transistor M 36  has a gate coupled to the scan line for the next row. 
     FIG. 3B  is a diagram showing signal timing of the driving circuit in  FIG. 3A . By comparing the signal timing shown in  FIGS. 2B and 3B , it is noted that the signal Swing is integrated into the scan signals S 1  and S 2  shown in  FIG. 3B . That is to say, the scan driver  22  outputs the scan signal comprising the signal Swing. 
   During periods T 1  and T 2 , the signal S 1  respectively carries a logic high and low level controlling the switches in a previous row (not shown) of the pixel matrix. The signal S 2  stays at the logic low level. Therefore, the display cells  331 ˜ 334  are not yet activated. 
   The scan period when the scan signal S 1  is asserted (has a logic high level) is divided into two sub-periods T 3  and T 4 , and the signal S 2  is used as the signal Swing for the switches  341  and  342 . During the period T 3 , the signal S 2  has a high logic level to turn on the transistor M 35  (closes the switch  341 ). The display cell  333  in the even column of the pixel matrix receives the data signal from the data driver  31  through the data line  35 . During the period T 4 , the transistor M 35  is turned off (the switch  341  is opened) by the signal S 2 . The display cell  331  in the odd column of the pixel matrix receives the data signal from the data driver  31  through the data line  35 . It is noted that although the display cell  331  also receives the data signal for the display cell  333  during the period T 3 , it is refreshed by the data signal received during the period T 4 . 
   The next scan period when the scan signal  52  is asserted (has a logic high level) is divided into two sub-periods T 5  and T 6 , the scan signal (not shown) for the display cells in the next row of the pixel matrix is used as the signal Swing. The transistors M 31 , M 35 , M 33  are turned off during the periods T 5  and T 6 . During the period T 6 , the transistor M 36  is turned on(the switch  342  is closes) by the next scan signal. The display cell  334  in the even column of the pixel matrix receives the data signal from the data driver  31  through the data line  35 . During the period T 6 , the transistor M 36  is turned off (the switch  342  is opened) by the next scan signal. The display cell  332  in the odd column of the pixel matrix receives the data signal from the data driver  31  through the data line  35 . It is noted that although the display cell  332  also receives the data signal for the display cell  334  during the period T 6 , it is refreshed by the data signal received during the period T 6 . 
     FIG. 4A  is a diagram showing a display driving circuit  4  according to a third embodiment of the invention. It includes a data driver  41 , a scan driver  42 , a pixel matrix composed of four (for example) display cells  431 ˜ 434 , and two switches  441  and  442 . The data driver  41  outputs data signals for the display cells  431 ˜ 434  through a data line  45 . The scan driver  42  outputs scan signals S 3  and S 4  through scan lines  461  and  462 . The display cells  431 ˜ 434  respectively receive the corresponding data signals commonly through the data line  45 . The display cells  433  and  434  receive a signal Swing via switches  441  and  442  respectively. 
   The display cells  431  and  432  in the odd columns of the pixel matrix are respectively composed of a transistor M 41  and a capacitor C 41 , and a transistor M 42  and C 42 . The transistor M 41  and M 42  have gates respectively coupled to the scan lines  461  and  462 , drains commonly coupled to the data line  45 , and sources coupled to the capacitors C 41  and C 42 . The display cells  433  and  434  in the even columns of the pixel matrix are respectively composed of a transistor M 43  and a capacitor C 43 , and a transistor M 44  and C 44 . The transistor M 43  and M 44  have gates respectively coupled to the switches  441  and  442 , drains commonly coupled to the data line  45 , and sources coupled to the capacitors C 43  and C 44 . The switches  441  and  442  are transistors M 45  and M 46  respectively. The transistors M 45  and M 46  have gates respectively coupled to the scan lines  461  and  462  and drains coupled to receive the signal Swing. 
     FIG. 4B  is a diagram showing signal timing of the driving circuit in  FIG. 4A . 
   The scan period when the scan signal S 3  is asserted (has a logic high level) is divided into two sub-periods T 1  and T 2 . The transistors M 41  and M 45  are turned on (the switches  441  is closed) during this scan period. During the period T 1 , the signal Swing is asserted (has a logic high level) and turns on the transistor M 43 . The display cell  433  in the even column of the pixel matrix receives the data signal from the data driver  41  through the data line  45 . During the period T 2 , the transistor M 43  is turned off by the signal Swing. The display cell  431  in the odd column of the pixel matrix receives the data signal from the data driver  41  through the data line  45 . It is noted that although the display cell  431  also receives the data signal for the display cell  433  during the period T 1 , it is refreshed by the data signal received during the period T 2 . 
   The next scan period when the scan signal S 4  is asserted (has a logic high level) is divided into two sub-periods T 3  and T 4 . The transistors M 42  and M 46  are turned on (the switches  442  are closed) during this scan period. During the period T 3 , the signal Swing is asserted (has a logic high level) and turns on the transistor M 4 . The display cell  434  in the even column of the pixel matrix receives the data signal from the data driver  41  through the data line  45 . During the period T 4 , the transistor M 44  is turned off by the signal Swing. The display cell  432  in the odd column of the pixel matrix receives the data signal from the data driver  41  through the data line  45 . It is noted that although the display cell  432  also receives the data signal for the display cell  434  during the period T 3 , it is refreshed by the data signal received during the period T 4 . 
     FIG. 5A  is a diagram showing a display driving circuit  5  according to a fourth embodiment of the invention. It includes a data driver  51 , a scan driver  52 , a pixel matrix composed of four (for example) display cells  531 ˜ 534 , and two switches  541  and  542 . The data driver  51  outputs data signals for the display cells  531 ˜ 534  through a data line  55 . The scan driver  52  outputs scan signals S 3  and S 4  through scan lines  561  and  562 . The display cells  531 ˜ 534  respectively receive the corresponding data signals commonly through the data line  55 . The switches  541  and  542  are respectively coupled between the scan line  562  and the display cell  533 , and between the scan line for the display cells in the next row (not shown) of the pixel matrix and the display cell  534 . 
   The display cells  531  and  532  in the odd columns of the pixel matrix are respectively composed of a transistor M 51  and a capacitor C 51 , and a transistor M 52  and C 52 . The transistor M 51  and M 52  have gates respectively coupled to the scan lines  561  and  562 , drains commonly coupled to the data line  55 , and sources coupled to the capacitors C 51  and C 52 . The display cells  533  and  534  in the even columns of the pixel matrix are respectively composed of a transistor M 53  and a capacitor C 53 , and a transistor M 54  and C 54 . The transistor M 53  and M 54  have gates respectively coupled to the switches  541  and  542 , drains commonly coupled to the data line  55 , and sources coupled to the capacitors C 53  and C 54 . The switches  541  and  542  are transistors M 55  and M 56  respectively. The transistors M 55  and M 56  has gates respectively coupled to the scan lines  561  and  562  to receive the scan signals S 3  and S 4 , and sources respectively coupled to the scan line  562  and the scan line for the next row. 
     FIG. 5B  is a diagram showing signal timing of the driving circuit in  FIG. 5A . By comparing the signal timing shown in  FIGS. 4B and 5B , it is noted that the signal Swing is integrated into the scan signals S 3  and S 4  shown in  FIG. 5B . That is to say, the scan driver  52  outputs the scan signal comprising the signal Swing. 
   During periods T 1  and T 2 , the signal S 3  respectively carries a logic high and low level controlling the switches in a previous row (not shown) of the pixel matrix. The signal S 4  stays at the logic low level. Therefore, the display cells  531 ˜ 534  are not yet activated. 
   The scan period when the scan signal S 3  is asserted (has a logic high level) is divided into two sub-periods T 3  and T 4 , and the signal S 4  is used as the signal Swing for the switches  541  and  542 . The transistors M 51  and M 55  are turned on (the switches  541  is closed) during this scan period. During the period T 3 , the signal S 4  has a high logic level to turn on the transistor M 53 . The display cell  533  in the even column of the pixel matrix receives the data signal from the data driver  51  through the data line  55 . During the period T 4 , the transistor M 53  is turned off by the signal S 4 . The display cell  531  in the odd column of the pixel matrix receives the data signal from the data driver  51  through the data line  55 . It is noted that although the display cell  531  also receives the data signal for the display cell  533  during the period T 3 , it is refreshed by the data signal received during the period T 4 . 
   The next scan period when the scan signal S 4  is asserted (has a logic high level) is divided into two sub-periods T 5  and T 6 , the scan signal (not shown) for the display cells in the next row of the pixel matrix is used as the signal Swing. The transistors M 52  and M 56  are turned on (the switches  542  is closed) during this scan period. During the period T 6 , the transistor M 54  is turned on by the next scan signal. The display cell  534  in the even column of the pixel matrix receives the data signal from the data driver  51  through the data line  55 . During the period T 6 , the transistor M 54  is turned off by the next scan signal. The display cell  532  in the odd column of the pixel matrix receives the data signal from the data driver  51  through the data line  55 . It is noted that although the display cell  532  also receives the data signal for the display cell  534  during the period T 6 , it is refreshed by the data signal received during the period T 6 . 
   In conclusion, the present invention provides a display driving circuit with fewer data drivers. Each pair of display cells is equipped with a switch for data terminal sharing. Thus, the switching frequency of the switches is lowered to the frame rate, which eliminates the reliability issue in the conventional display driving circuit. 
   The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.