Abstract:
A driver circuit for driving a line in a network comprises first driving means for driving the line, second driving means for driving the line, and switching means for switching between the first and second driving means. A method for providing multi-mode driver capability is also described. The method comprises the steps of providing a line driver circuit including both a current source and a voltage source, selecting a first or second mode of operation, operating the line driver circuit in a first configuration when the first mode of operation is selected, and operating the line driver circuit in a second configuration when the second mode of operation is selected.

Description:
FIELD OF THE INVENTION 
   This invention relates generally to line driver circuitry and in particular to line drivers suitable for use in an Ethernet environment, and is more particularly directed toward a driver circuit for use with twisted pair cable in Ethernet and Fast Ethernet architectures. 
   BACKGROUND OF THE INVENTION 
   Ethernet™ is a network communication system developed and standardized by DEC, Intel, and Xerox using baseband transmission, Carrier Sense Multiple Access/Collision Detection (CSMA/CD) access, logical bus topology, and coaxial cable. A shared media network architecture, subsequently defined in the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, it is currently the most popular architecture used in local area networks, and has been extended for operation using fiber optics, broadband, and unshielded twisted pairs. Ethernet is currently implemented using two main variants: Ethernet and Fast Ethernet. 
   The Ethernet or 10 BaseT is a variant architecture based on the foregoing standard and operates up to 10 Mbps (megabits per second), using unshielded twisted pair cable (UTP). A 10 BaseT architecture is also known as twisted pair Ethernet or UTP Ethernet. A second Ethernet standard, which includes implementations capable of 100 Mbs transmission speeds, is defined in IEEE 802.3u, and is referred to as Fast Ethernet or 100 Mbs Ethernet. A third implementation capable of 1 Gbps (gigabit per second) transmission is currently being standardised. 
   The Ethernet™ system is used to link various nodes using a specific topology within a networked system, and initially utilised a coaxial cable with nodes tapped off the cable. A node is generally a device such as a personal computer, a workstation, server, bridge, or router, which is connected to the network at a single location. The topology is the logical pattern formed by the nodes of a network; i.e., the way the nodes are interconnected. 
   Topologies are either physical or logical. A physical topology is the configuration of nodes and links and describes the physical relationship between these nodes and links, whereas the logical topology describes which pairs of nodes are able to communicate and whether or not they have a physical connection. Local area networks (LANs) are usually configured in one of three topologies: star, ring, or bus. 
   Ethernet™ generally uses a star topology having nodes connected to a hub or switch box. The standard cable for use in both Ethernet and Fast Ethernet situations is a Category 5 (CAT5) cable, supporting transmissions up to 100 Mbps, but also backwards compatible; i.e., can support 10 Mbps transmissions. Each node may be connected to a hub using up to 100 m of CAT5 cable. 
   In order to drive a signal over a network, it is necessary to use an Ethernet driver. In the star topology, the hubs or switches serve to restore a signal&#39;s amplitude and timing between nodes, as it is not possible to drive a signal using Ethernet technology more than 100 meters before amplification is required. 
   Known Fast Ethernet (100 BaseTx) and Ethernet (10 BaseT) drivers can drive a signal up to 100 meters along CAT5 twisted pair cable. Drivers may be either current or voltage driven. Ethernet drivers typically require an output voltage with an accuracy of ±12%, whereas Fast Ethernet requires improved output voltage accuracy of ±5%. 
   Although it is possible to use a current source to drive both Ethernet and Fast Ethernet, it is preferable to use a voltage source to drive Fast Ethernet, as the accuracy levels achieved are much higher. It is possible for hubs to support exclusively Ethernet, exclusively Fast Ethernet, or both modes. All systems incorporate an Ethernet controller that determines the speed at which signals should be sent, and the standard describes how initial set-up is effected. For example, a hub may initially drive a card driver at Fast Ethernet speeds, and then check to see if a valid response is obtained. If it is not, then the hub will resend using Ethernet speeds. 
   Typically, the drivers are connected to the CAT5 cable by a 1:1 transformer and an RJ45 connector, and operate with a standard 3.3V power supply over a temperature range of 0° C. to 70° C. An example of such an Ethernet driver is shown in FIG.  1 . 
   The Ethernet driver  1  takes internal differential signals, inp and inn, and generates differential output signals capable of driving the CAT5 cable  2  in the manner previously described; i.e., by way of 1:1 transformer  3 . The other end of the cable  2  connects to a second isolating 1:1 transformer  4 , and the inputs  5  to an Ethernet receiver, rxp and rxn, are terminated in 50 Ohms. The source impedance at txp and txn is also 50 Ohms. 
   In the case of Fast Ethernet (100 BaseTx), the MLT3 encoded differential output voltage (txp, txn) level is −1V to +1V. The Fast Ethernet data rate is 100 MHz and the output voltage (txp, txn), accuracy is ±5%. The edge rates are limited to 4 nS ±1 nS to reduce radiation from the cable. 
   The Ethernet (10 BaseT) output voltage (txp, txn) level is −2.5V to +2.5V. The Ethernet output voltage (txp, txn) accuracy is ±0.3V or ±12%. The signal is typically a Manchester encoded 10 BaseT signal consisting of a 10 MHz sine wave, which may be generated by a waveshaping circuit consisting of a look-up table and a digital-to-analog converter (DAC) followed by a low pass filter. The total harmonic distortion of the Ethernet signal is greater than 27 dB. 
   Further examples of existing line driver architectures are shown in  FIGS. 2 ,  3 , and  4 .  FIG. 2  illustrates that a voltage source  11  may be used to drive the line. In this driver architecture, the source voltage (txp 1 , txn 1 ) is two times the output voltage (txp, txn). In the case of a 3.3V power supply, this architecture can be used for Fast Ethernet where the source voltage is 2V, but not for Ethernet where the minimum output source voltage requirement is 4.4V. Other features shown include cable  12 , transformers  13  and  14 , and Ethernet receiver inputs  15 . 
   As shown in  FIG. 3 , a current source  21  may be used to drive the line. The output currents develop the output voltage (txp, txn) directly across the line. In the case of a 3.3V power supply, this driver architecture can be used for both Fast Ethernet, where the output voltage is 1V, and also for Ethernet where the typical output voltage is 2.5V. Other features shown include cable  22 , transformers  23  and  24 , and Ethernet receiver inputs  25 . 
   A variation on the current driver is the use of a bridge current driver  31 , as shown in FIG.  4 . This driver includes four current sources, I 1 , I 2 , I 3 , and I 4 . The line termination resistors are now connected to an additional output voltage, Vmid. Vmid is half the supply voltage or 1.65V. This driver architecture uses 3 pins, but requires half the current of a two-pin current driver. 
   In the case of Fast Ethernet, each of the current sources, I 1 , I 2 , I 3 , and I 4 , is 20 mA. A +1V (txp, txn) signal is generated when I 4  sources 20 ma, which flows through R 1 , R 2  and L 1  into I 2 . A 0V (txp,txn) signal is generated when the I 4  current flows into I 1  and the I 3  current flows into I 2 . A −1V (txp, txn) signal is generated when I 3  sources 20 ma, which flows through R 1 , R 2  and L 1  into I 1 . In the case of Ethernet, the current levels are 50 mA, generating a peak voltage (txp, txn) of 2.5V. Other features depicted in  FIG. 4  include the cable  32 , transformers  33  and  34 , and receiver inputs  35 . 
   In the early development of Ethernet, drivers were developed in single units. Although single drivers are still used in cards for installation at specific nodes, there is a requirement in hub design to increase the number of drivers that can be implemented on a single card. It is known in the prior art to provide quad drivers, wherein four drivers are implemented on a single card. Even though there has been a tendency toward hubs with 8, 16 or 32 ports, it has not been possible to improve upon the quad drivers already in existence. This is primarily due to the fact that the common power requirement of the drivers is such that if more than four drivers are implemented, the package power dissipation has been too high. There is, therefore, a need for drivers with lower power dissipation, so as to facilitate the provision of multi-port drivers in hubs and switches. 
   SUMMARY OF THE INVENTION 
   These needs and others are met by the line driver circuit of the present invention, which has a reduced power requirement, and as such can be implemented in greater numbers on an integrated circuit than the well-known quad driver. The inventive line driver circuit is a combined Ethernet/Fast Ethernet driver circuit that incorporates the necessary current driver for Ethernet combined with the accuracy offered by a voltage driver for Fast Ethernet. 
   In accordance with one embodiment of the invention, a driver circuit for driving a line in a network comprises first driving means for driving the line, second driving means for driving the line, and switching means for switching between the first and second driving means. Preferably, the switching means operates to make only one of the first or second driving means active at any one time. 
   In one aspect of the invention, the switching means comprises a first input for enabling and disabling the first driving means and a second input for enabling and disabling the second driving means, wherein, when one of the first or second driving means is enabled, the other driving means is disabled. The first driving means may comprise one or more current sources, which may be connected in a bridge configuration. 
   In another form of the invention, the driver circuit is connected to a supply voltage and further comprises a plurality of terminating elements coupled to an output voltage of the driver circuit, wherein the driver circuit operates to limit the output voltage to about one-half of the supply voltage. The second driving means may comprise a voltage source. 
   In yet another aspect of the present invention, a driver circuit for driving lines in a network comprises a plurality of current sources connected in a bridge configuration and coupled to the lines to provide a bridge current driver, a voltage source coupled to the lines to provide a voltage driver, and a plurality of terminating elements coupled to the current sources, the voltage source, and to the lines. The driver circuit further includes a supply voltage coupled to the bridge current driver and the voltage driver, wherein the supply voltage includes a mid-point termination voltage, and switching means for switching between the bridge current driver and the voltage driver, such that, when the bridge current driver is selected, the terminating elements are coupled to the mid-point termination voltage and the lines are driven from the bridge current driver. When the voltage driver is selected, the bridge current driver is disabled, and the terminating elements are coupled to the voltage driver. Preferably, the mid-point termination voltage is approximately equal to one-half the supply voltage, and the terminating elements comprise a network of resistors. 
   In still another aspect of the invention, a line driver circuit comprises a current source coupled to a first pair of terminals of a termination network and a voltage source coupled to a second pair of terminals of the termination network, wherein the voltage source operates in a first configuration to establish a first mode of operation, and in a second configuration to establish a second mode of operation. The current source may comprise a plurality of current sources. Preferably, the plurality of current sources are arranged in a bridge configuration. 
   The first mode of operation of the line driver circuit comprises voltage source drive mode. The first configuration of the line driver circuit corresponding to voltage source drive mode comprises driving the second pair of terminals of the termination network with the voltage source while the current source is maintained in an OFF state. 
   The second mode of operation of the line driver circuit comprises current source drive mode. The second configuration of the line driver circuit corresponding to current source drive mode comprises driving the first pair of terminals of the termination network with the current source while the voltage source maintains the second pair of terminals of the termination network at a predetermined, non-zero potential. The predetermined, non-zero potential preferably comprises one-half of line driver circuit supply voltage. 
   In still another form of the invention, the termination network comprises a resistive termination network. The resistive termination network preferably comprises a pair of resistors with the voltage source outputs coupled to a first end of each resistor and the current source outputs coupled to a second end of each resistor. 
   In accordance with yet another aspect of the invention, a method for providing multi-mode driver capability is described. The method comprises the steps of providing a line driver circuit including both a current source and a voltage source, selecting a first or second mode of operation, operating the line driver circuit in a first configuration when the first mode of operation is selected, and operating the line driver circuit in a second configuration when the second mode of operation is selected. 
   Further objects, features, and advantages of the present invention will become apparent from the following description and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates an Ethernet driver circuit implementation that is known in the art; 
       FIG. 2  depicts a voltage driven line driver circuit of the prior art; 
       FIG. 3  shows a current driven line driver circuit of the prior art; 
       FIG. 4  shows a bridge current driven line driver circuit, in accordance with a known architecture; 
       FIG. 5  illustrates a Fast Ethernet and Ethernet driver in accordance with the present invention; 
     FIG.  6 A and  FIG. 6B  together comprise a schematic diagram of a cable driver in accordance with the present invention; 
       FIG. 7  is a schematic of a current feedback amplifier equivalent in accordance with the present invention; 
       FIG. 8  is a schematic of a switched current feedback amplifier equivalent in accordance with the present invention; and 
       FIG. 9  is a block diagram of a fast ethernet and ethernet driver in accordance with another embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In accordance with the present invention, an Ethernet and Fast Ethernet driver is described that provides distinct advantages when compared to configurations known in the prior art. The invention may be implemented in a driver now described with reference to  FIGS. 5  to  8 , in which the Fast Ethernet driver has lower power than existing solutions, and the Ethernet bridge current generator is more accurate than existing solutions. For existing architectures, the available power supply is 3.3V ±5% or 3.165V to 3.465V. The operating temperature range is 0° C. to 70° C. 
     FIG. 5  shows a Fast Ethernet and Ethernet driver according to the present invention. The driver allows both a voltage source drive  51  to be used for Fast Ethernet and a bridge current source drive  52  to be used for Ethernet. The driver architecture uses 4 pins; current source pins txp and txn, and voltage source pins vp and vn. The expressions txp and txn are conventional terms for transmit positive and transmit negative respectively, while the expressions vp and vn indicate positive and negative termination voltages, respectively. 
   Line termination resistors  53 ,  54  connect to the two voltage source pins vp and vn. The two modes are combined by examining the termination resistors  53 ,  54 , and by having two inputs. By reconfiguring the termination resistors it is possible to implement either of the two modes. The choice of which mode is utilized is made using standard techniques such as those described previously. 
   In the case of Fast Ethernet, the bridge currents, (I 1 , I 2 , I 3  and I 4 ) are turned off, as will be described in greater detail subsequently with reference to  FIG. 8 , and the line is voltage driven from vp and vn. As Fast Ethernet is required, the txp, txn signal drive level is 0.5V to −0.5V. 
   The line termination resistor r 1  ( 53 ) is effectively in series with r 3  and r 2  ( 54 ) is in series with r 4  for an incremental signal analysis. In order to obtain the required txp, txn signal, it is necessary to supply +1V, −1V at vp, vn. The load current is thus vp/(r 1 +r 3 ) or 1V/(100 Ohms); that is, 10 mA. The presented voltage at vp, vn is such that a differential of 2V exists. As such, the on chip voltage drop is 3.3V −2V or 1.3V. This results in an on-chip power dissipation of 1.3V*10 mA, which is equal to 13 mW. 
   In the case of Ethernet, the vp and vn voltages are set to an active mid-point termination voltage, vmid. Vmid is half the supply voltage or 1.65V for a 3.3V supply. The line is then driven from the bridge currents, I 1 , I 2 , I 3 , and I 4 . The line voltage is 2.5V with a resultant load current of 2.5V/50 Ohms, or 50 mA. The on chip voltage drop is 3.3V-2.5V or 0.8V, which equates to an on-chip power dissipation of 40 mW. 
   This new architecture uses the accurate voltage drive to generate the Fast Ethernet&#39;s requisite ±5% accuracy signal, and the less accurate current drive to generate the Ethernet&#39;s ±12% accuracy signal. The Fast Ethernet signal is provided with a chip power dissipation of 13 mW, which is lower than other known architectures. This results from lower on-chip voltages and load currents. 
   A current of 10 mA is required to generate 0.5V across 50 Ohms. Known bridge current drivers, as described with reference to  FIG. 4  above, use 20 mA, as 10 mA is delivered to the line and 10 mA is required for across-the-line termination resistors. In the case of the single-ended current driver described with reference to  FIG. 3 , a 40 mA current is required. 
   Comparisons of existing architectures with Ethernet and Fast Ethernet drivers in accordance with the present invention (termed “New Driver” in the Tables) are shown in Tables 1 and 2. 
   
     
       
             
           
             
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Comparison of Fast Ethernet drivers 
             
           
        
         
             
                 
                 
                 
               On Chip 
               Power 
             
             
                 
               Architecture 
               Load Current 
               Voltage 
               Dissipation 
             
             
                 
                 
             
             
                 
               Current Drive 
               40 mA 
               2.8 V 
               112 mW  
             
             
                 
               Bridge 
               20 mA 
               2.3 V 
               16 mW 
             
             
                 
               Current Drive 
             
             
                 
               New Driver 
               10 mA  
               1.3 V 
               13 mW 
             
             
                 
                 
             
           
        
       
     
   
   
     
       
             
           
             
             
             
             
             
           
         
             
               TABLE 2 
             
           
           
             
                 
             
             
               Comparison of Ethernet drivers 
             
           
        
         
             
                 
                 
                 
               On Chip 
               Power 
             
             
                 
               Architecture 
               Load Current 
               Voltage 
               Dissipation 
             
             
                 
                 
             
             
                 
               Current Drive 
               100 mA  
               0.8 V 
               80 mW 
             
             
                 
               Bridge 
               50 mA 
               0.8 V 
               40 mW 
             
             
                 
               Current Drive 
             
             
                 
               New Driver 
               50 mA 
               0.8 V 
               40 mW 
             
             
                 
                 
             
           
        
       
     
   
   A more detailed representation of an implementation for the Fast Ethernet and Ethernet Driver of  FIG. 5  is shown in the schematic of FIG.  6 A. The cable driver includes two current feedback amplifiers with a gain of −2. In Fast Ethernet mode, the logic input, Enable, turns off the Ethernet, or 10 BaseT, output currents. The amplifier pamp 2  controls the output voltages, vp and vn, and V(vp, vn)=V(txp,txn)*2. 
   The drivers in accordance with the present invention utilize a new method to generate the bridge currents. In  FIG. 6A , the 10BaseT current supplied to the line is from the outputs, Ioutp and Ioutn, of the amplifier pamp 4 , (see  FIG. 8  for details). The currents loutp and Ioutn are ratios of the amplifier currents flowing in r 3  and r 4 . In the case of pamp 4 , mp 2  is 10 times the size of mp 20 , so the current in mp 20  is 10 times the current in mp 2 . Ethernet driver circuits are conventionally biased from a fixed bandgap voltage, Vref, and an external resistor, Rext.
         Ibias=Vref/Rext, a fixed current,   Vinp=Rinp*Ibias   Irl=Vinp/rl=Rinp*Ibias/rl, a fixed current, since the ratio Rinp/rl is constant       

   This current, Ir 1 , flows in r 3  to outp of pamp 4 , and to either mp 20  or mn 20  in pamp 4  . A multiple of Ir 1  flows to the line from mp 2  or mn 2  in pamp 4  to Ioutp (FIG.  8 ). The voltage that is presented to the line at Txp is Txp=r 3 *Ir 1  If the absolute value of r 3  is controlled to within ±12%, then the voltage on the line will be within the 10 BaseT specification, and Txp will be a fixed voltage. 
   The input voltages inp, inn, inp 1  and iin 1  are derived from an on-chip reference voltage and an external resistor. For Fast Ethernet, the input voltage, (inp and inn) to the cable driver circuit is ±0.25V into 250 Ohms (1 mA), and for Ethernet the input voltage drive is ±0.625V into 250 Ohms (2.5 mA). The single-ended voltage gain of the amplifier, Txp/inp 1 , is r 3 /r 1 . 
     FIG. 7  is an equivalent circuit of the differential current feedback amplifier, pamp 2 , of FIG.  6 A. The amplifier signals are referenced to half the power supply voltage, Vmid =1.65V. With two inputs and two outputs, the amplifier responds to the current input at inp and inn. 
   The pmos devices mp 8 , mp 7 , and mp 6  connected to the voltage bias line vbiasp can be replaced by 3 current sources flowing from Vcc. Also, the nmos devices mn 9 , mn 10 , and mn 11  connected to the voltage bias line vbiasn can be replaced by 3 current sources flowing to gnd. The input, vmid, is connected to a voltage source set between vcc and gnd or at 1.65v. 
   When the input, inp, is at the same voltage as the input, vmid, then no current flows in the input inp. When the voltage at input inp is below vmid, then there is a signal current flowing in mn 1  in addition to the Imn 9  current. This signal current is converted to a voltage gain at the gate of mp 2 . The current in mp 2  increases, providing a current at outp flowing from vcc to outp. 
   Also, when the voltage at input inp is below vmid, then the current flowing in mp 1  is the Imn 9  current minus the signal current. This signal current is converted into a voltage gain at the gate of mn 2 . The current in nm 2  decreases, providing less current flowing from outp to gnd. 
   The amplifier will try to force the voltage at inp to match the voltage at inn by forcing more or less signal current into the inp input. Similarly, because it&#39;s a differential amplifier, it will also force inn to match vmid. 
   The switched current feedback amplifier pamp 4  of  FIG. 6A  (illustrated in  FIG. 8 ) is similar to the  FIG. 7  amplifier except for the addition of a logic control, Enable, and the current outputs Ioutn and Ioutp. The logic input, Enable, switches the output of the amplifier. 
   When Enable is at gnd, enb is high and en is low. When en is low, the pmos switches mp 9  and mp 10  are on, which turns off the output currents flowing from Vcc to outp, Ioutp, outn and Ioutn. When enb is high, the nmos switches mn 12  and mn 13  are on, which turns off the output currents flowing from outp, Ioutp, outn and Ioutn to gnd. The auxiliary current outputs, Ioutp and Ioutn, match the current flowing in outp and outn. 
   When Enable is low, mp 9 , mp 10 , mn 12 , and mn 13  turn on. This shuts off the output currents in mp 2 , mp 20 , mp 4 , mp 40 , mn 2 , mn 20 , mn 4 , and mn 40 . The currents in mp 20 , mp 40 , mn 20  and mn 40  are controlled by the current feedback amplifier pamp 4 . The Ethernet bridge currents, at mp 2 , mp 4 , mn 2 , and mn 4 , are a scaled version of the amplifier currents. In this particular implementation, the scaling factor is 10 times. 
   Another embodiment is shown in  FIG. 9 , wherein respective first and second logic control signals are input to each of the first and second driving means for enabling and disabling the respective first and second driving means. In this arrangement, when one of the first or second driving means is enabled, the other driving means is disabled. 
   There has been described herein an Ethernet and Fast Ethernet driver which is improved over the prior art. It will be apparent to those skilled in the art that modifications may be made without departing from the spirit and scope of the invention. Accordingly, it is not intended that the invention be limited except as may be necessary in view of the appended claims.