Abstract:
The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    Priority to Korean patent application number 10-2010-0104854 filed on Oct. 26, 2010, the entire disclosure of which is incorporated by reference herein, is claimed. 
       BACKGROUND 
       [0002]    Exemplary embodiments relate to a nonvolatile memory device and a method of programming the same. 
         [0003]    Recently, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and which do not require a refresh function of rewriting data at specific intervals. 
         [0004]    The nonvolatile memory device can be electrically programmed and erased in such a manner that electrons within an oxide layer migrate in response to a strong electric field applied to the oxide layer, thereby shifting the threshold voltages of memory cells. 
         [0005]    The nonvolatile memory devices may be typically used in mobile devices, and thus it is necessary to develop technology in which the same characteristic can be maintained despite a change of temperature. After a program operation for the memory cells of the nonvolatile memory device, a program verification operation is performed. A sense current used as a reference current in the program verification operation may be sensitive to a change of temperature. In particular, if the program operation and the program verification operation are performed at low temperature, a change of the sense current is increased to widen a threshold voltage distribution of the memory cells. Accordingly, there has been a need for technology capable of preventing the phenomenon in which the threshold voltage distribution of memory cells may be widened at low temperature. 
       BRIEF SUMMARY 
       [0006]    According to exemplary embodiments, even though a program operation of an Incremental Step Pulse Program (ISPP) method and a program verification operation are performed at low temperature, the threshold voltage distribution of memory cells is not widened. 
         [0007]    The program method of a nonvolatile memory device according to an exemplary aspect of the present disclosure includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage. 
         [0008]    The step voltage may be set to a lower step voltage than a previous step voltage according to a decrease in the detected temperature. 
         [0009]    Performing the program operation and the program verification operation may include performing a first program operation by supplying a first program voltage to a word line coupled to memory cells, performing a first program verification operation by comparing a target threshold voltage and threshold voltages of the memory cells, and performing a second program operation by supplying the word line with a second program voltage higher than the first program voltage by the step voltage. 
         [0010]    Setting the step voltage may include, when the detected temperature is lower than a first temperature value, setting a first step voltage as the step voltage, and, when the detected temperature is the first temperature value or higher, setting a second step voltage, which is higher than the first step voltage, as the step voltage. 
         [0011]    A nonvolatile memory device according to another exemplary aspect of the present disclosure includes a memory cell block including memory cells coupled to each of word lines, an operation circuit group configured to perform a program operation of an ISPP method and a program verification operation for the memory cells, and a control circuit configured to set a step voltage, corresponding to an increment of a program voltage in the program operation, wherein the step voltage changes based on a detected temperature and to control the operation circuit group so that the program operation and the program verification operation are performed based on the set step voltage. 
         [0012]    The control circuit may set the step voltage to a lower step voltage than the previous step voltage according to a decrease in the detected temperature. 
         [0013]    The nonvolatile memory device may further include a temperature sensing circuit for detecting the temperature. 
         [0014]    The control circuit may control the operation circuit group such that a first program operation and a program verification operation are performed by supplying a first program voltage to the word line and a second program operation and a program verification operation are performed by supplying the word line with a second program voltage, which is higher than the first program voltage by the step voltage. 
         [0015]    The control circuit may set a first step voltage as the step voltage when the detected temperature is lower than a first temperature value and set a second step voltage, which is higher than the first step voltage, as the step voltage when the detected temperature is the first temperature value or higher. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a diagram illustrating the configuration of a nonvolatile memory device according to an exemplary embodiment of this disclosure; 
           [0017]      FIG. 2  is a diagram illustrating a process of the program operation and the program verification operation of the nonvolatile memory device according to an exemplary embodiment of this disclosure; 
           [0018]      FIGS. 3A and 3B  are diagrams illustrating a shift in a program voltage used in a known nonvolatile memory device and a shift in a program voltage used in a nonvolatile memory device in accordance with the exemplary embodiments of this disclosure at low temperature; and 
           [0019]      FIGS. 4A and 4B  are diagrams illustrating threshold voltage distributions of the memory cells of a known nonvolatile memory device and of the memory cells of a nonvolatile memory device in accordance with the exemplary embodiments of this disclosure at low temperature. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0020]    Hereinafter, some exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiments of the disclosure. 
         [0021]    Nonvolatile Memory Device 
         [0022]      FIG. 1  is a diagram illustrating the configuration of a nonvolatile memory device according to an exemplary embodiment of this disclosure. 
         [0023]    Referring to  FIG. 1 , the nonvolatile memory device according to the exemplary embodiment of this disclosure includes a memory cell block  110 , an operation circuit group  130 ,  140 ,  150 ,  160 ,  170 , and  180  configured to perform a program operation of an Incremental Step Pulse Program (ISPP) method and a program verification operation for memory cells included in the memory cell block  110 , a control circuit  120  configured to control the operation circuit group  130 ,  140 ,  150 ,  160 ,  170 , and  180 , and a temperature sensing circuit  190  configured to sense temperature. 
         [0024]    In the case of a NAND flash memory device, the operation circuit group includes a voltage generator  130 , a row decoder  140 , a page buffer group  150 , a column selector  160 , an I/O circuit  170 , and a pass/fail (P/F) check circuit  180 . 
         [0025]    A memory cell array includes a plurality of memory cell blocks.  FIG. 1  shows one  110  of the memory cell blocks. The memory cell block  110  includes a plurality of strings ST 1  to STk. Each, for example, ST 1 , of the strings includes a source select transistor SST coupled to a common source line CSL, a plurality of memory cells Ca 0  to Can, and a drain select transistor DST coupled to a bit line BL 1 . The gate of the source select transistor SST is coupled to a source select line SSL. The gates of the memory cells Ca 0  to Can are coupled to respective word lines WL 0  to WLn. The gate of the drain select transistor DST is coupled to a drain select line DSL. The strings ST 1  to STk are coupled to the respective bit lines BL 1  to BLk and are commonly coupled to the common source line CSL. 
         [0026]    The control circuit  120  internally generates a program operation signal PGM, a read operation signal READ, or an erase operation signal ERASE in response to a command signal CMD and also generates control signals PB SIGNALS for controlling the page buffers (not shown) of the page buffer group  150  according to a type of the operation. Furthermore, the control circuit  120  internally generates a row address signal RADD and a column address signal CADD in response to an address signal ADD. The control circuit  120  of this disclosure controls the operation circuit group  130 ,  140 ,  150 ,  160 ,  170 , and  180  so that a program operation of an ISPP method and a program verification operation can be performed. The control circuit  120  functions to set an increment, for example, a step voltage, of a program voltage in the program operation of an ISPP method according to temperature sensed by the temperature sensing circuit  190 . 
         [0027]    A voltage supply circuit  130  and  140  supplies the drain select line DSL, the word lines WL 0  to WLn, and the source select line SSL of the memory cell block  110  with operating voltages for the program operation, the erase operation, and the read operation of memory cells in response to the signals READ, PGM, ERASE, and RADD generated by the control circuit  120 . The voltage supply circuit includes the voltage generator  130  and the row decoder  140 . The voltage supply circuit  130  and  140  also supplies the program voltage for a program operation to the word lines WL 0  to WLn. 
         [0028]    The voltage generator  130  outputs the operating voltages for programming, reading, and erasing memory cells to global lines in response to the signals PGM, READ, and ERASE, for example, internal command signals, of the control circuit  120  and also outputs operating voltages, for example, Vpgm, Vpass, and Vpv[1:6], to the global lines when memory cells are programmed. 
         [0029]    The row decoder  140  transfers the operating voltages of the voltage generator  130  to the strings ST 1  to STk of the memory cell block  110  in response to the row address signal RADD of the control circuit  120 . 
         [0030]    The page buffer group  150  includes the page buffers (not shown) coupled to the respective bit lines BL 1  to BLk. The page buffer group  150  supplies the bit lines BL 1  to BLk with respective voltages necessary to store data in the memory cells Ca 0  to Ck 0  in response to the control signals PB SIGNALS of the control circuit  120 . 
         [0031]    The column selector  160  selects the page buffers of the page buffer group  150  in response to the column address signal CADD of the control circuit  120  and outputs data latched in the selected page buffers. 
         [0032]    The I/O circuit  170  transfers external data DATA to the column selector  160  under the control of the control circuit  120  in a program operation so that the data is inputted to the page buffer group  150 . 
         [0033]    The P/F check circuit  180  checks whether an error cell having a threshold voltage lower than a target voltage exists in programmed memory cells during a program verification operation performed after a program operation, and outputs a result of the check as a check signal PFS. Furthermore, the P/F check circuit  180  counts the number of error cells, and outputs a result of the count as a check signal CS. 
         [0034]    The nonvolatile memory device of this disclosure includes the temperature sensing circuit  190  for sensing temperature. Temperature sensed by the temperature sensing circuit  190  is used for the control circuit  120  to set a step voltage which is an increment of a program voltage in the program operation of an ISPP method. This is described in detail below. 
         [0035]    Program Operation and Program Verification Operation 
         [0036]      FIG. 2  is a diagram illustrating a process of the program operation and the program verification operation of the nonvolatile memory device according to an exemplary embodiment of this disclosure.  FIGS. 3A and 3B  are diagrams illustrating a shift in a program voltage used in the program operation of a known nonvolatile memory device and a shift in a program voltage used in the program operation of the nonvolatile memory device in accordance with an exemplary embodiment of this disclosure when temperature is lower than a reference temperature, which is, for example, a common temperature. 
         [0037]    A process of the program operation and the program verification operation of the nonvolatile memory device according to the exemplary embodiment of this disclosure is described with reference to  FIGS. 1 to 3 . 
         [0038]    First, the temperature sensing circuit  190  detects ambient temperature at step S 210 . To this end, the temperature sensing circuit  190  may include a specific type of temperature sensor. After the temperature is detected by the temperature sensing circuit  190 , the control circuit  120  sets an increment, for example, a step voltage Vstep, of a program voltage in a program operation of an ISPP method based on the detected temperature at step S 220 . 
         [0039]    In general, at low temperature, since a change of a sense current used in a program verification operation is increased, the entire threshold voltage distribution of memory cells may be widened. In this case, the control circuit  120  sets a lower step voltage Vstep according to a decrease in detected temperature in order to prevent the threshold voltage distribution of the memory cells from being widened according to the repetition of program operations and program verification operations. 
         [0040]    For example, when the detected temperature is less than a first temperature value, the control circuit  120  may select a first step voltage as an increment of the program voltage in the program operation of an ISPP method. When the detected temperature is the first temperature value or higher, but lower than a second temperature value, the control circuit  120  may select a second step voltage, which is higher than the first step voltage, as the increment of the program voltage. Furthermore, when the detected temperature is the second temperature value or higher, the control circuit  120  may select a third step voltage, which is higher than the second step voltage, as the increment of the program voltage in the program operation of an ISPP method. The control circuit  120  may not only set the step voltage Vstep, but also a program start voltage in the program operation of an ISPP method. 
         [0041]    Next, a program operation for memory cells coupled to a word line, for example, WLk, is performed at step S 230 . The program operation is performed by supplying a program start voltage Vpgm&lt;0&gt; to the word line WLk. The program start voltage Vpgm&lt;0&gt; may be a value set by the control circuit  120 . The value may be a common program start voltage, but may be set according to detected temperature. 
         [0042]    After the program operation, a program verification operation is performed at step S 240 . The program verification operation is performed in order to determine whether the memory cells have threshold voltages higher than a target threshold voltage by supplying a verification voltage Vverify to the word line WLk. Here, a sense current may be supplied to the memory cells. A change of the sense current is increased at lower temperature. 
         [0043]    If, as a result of the program verification operation, the program operation has not been normally performed, the program voltage is raised by the set step voltage Vstep at step S 250 . The step voltage Vstep is set by the control circuit  120 . As described above, the step voltage Vstep has a lower value according to lower temperature. Referring to  FIGS. 3A and 3B , it can be seen that, when a detected temperature is lower than typical ambient temperature, a step voltage Vstep in the ISPP method according to an exemplary embodiment of this disclosure is smaller than a step voltage Vstep in a known ISPP method. 
         [0044]    After the program voltage is raised by the step voltage Vstep, the program operation at step S 230  and the program verification operation at step S 240  are performed again using the raised program voltage Vpgm&lt;1&gt;. 
         [0045]    If, as a result of the program verification operation at step S 240 , the memory cells have been normally programmed, it is determined whether the word line WLk to which the memory cells are coupled is the last word line at step S 260 . If, as a result of the determination, the word line WLk is determined not to be the last word line, a k value indicating a word line is increased at step S 270 . The program operation and the program verification operation for a next word line WLk are performed as described above. 
         [0046]      FIGS. 4A and 4B  show the threshold voltage distributions of all memory cells of a known nonvolatile memory device and of the nonvolatile memory device of this disclosure, which are results of program operations when a detected temperature is lower than typical ambient temperature. 
         [0047]    Referring to  FIG. 4A , it can be seen that, in the known nonvolatile memory device, a change of a sense current supplied to the memory cells may be increased when a temperature is low because a constant step voltage is used in the program operation of an ISPP method irrespective of the temperature, and thus the entire threshold voltage distribution of the memory cells may be widened. However,  FIG. 4A  shows that, in the nonvolatile memory device in accordance with an exemplary embodiment of this disclosure, the entire threshold voltage distribution of the memory cells is narrower than that of the known art because a lower step voltage is used according to lower temperature. 
         [0048]    As described above, according to the present disclosure, a step voltage in a program operation of an ISPP method is set to be lower according to lower temperature. Accordingly, a phenomenon in which the entire threshold voltage distribution of memory cells is widened can be prevented.