Abstract:
A method for manufacturing a semiconductor device includes forming a barrier layer on an individual device formed on a semiconductor substrate and including a MOS transistor. An ozone process is performed on the barrier layer. A pre-metal dielectric (PMD) layer is then formed on the barrier layer.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    (a) Field of the Invention  
           [0002]    The present invention relates to a method for manufacturing a MOS (metal oxide semiconductor) transistor. More particularly, the present invention relates to a method for manufacturing a MOS transistor in which a silicon nitride layer is formed to prevent impurities from a pre-metal dielectric layer from diffusing into the transistor.  
           [0003]    (b) Description of the Related Art  
           [0004]    There are two general classes of field effect transistors (FETs), and they include the MOSFET and the JFET (junction FET). The present invention is related to the MOSFET, which typically includes the electrodes of a source, a drain, and a gate on a semiconductor substrate. Metal interconnect lines are connected to upper areas of the source, drain, and gate to enable the application of electrical signals to the same. The areas where such connections are made are referred to as contacts.  
           [0005]    To enable ohmic contact of each of the electrodes, that is, to minimize the resistance of each of the electrodes, silicide films are formed between the metal interconnect lines; and each electrode of the source, drain, and gate. Also, a silicon nitride film is deposited over an entire upper surface of the transistor including on the silicide films. The silicon nitride film acts as an etch stop layer during etching to form contacts and to prevent the diffusion of impurities from a BPSG (boron phosphorous silicate glass) layer into other elements.  
           [0006]    A conventional method for manufacturing a MOS transistor will be described with reference to FIGS. 1 a  through  1   d.    
           [0007]    Referring first to FIG. 1 a , polysilicon for use as a gate oxide layer  3  and a gate electrode  4  is formed at a predetermined width on a surface of a device region of a silicon wafer  1 . The device region of the silicon wafer  1  is defined by a field oxide layer  2 , which is formed by a LOCOS (local oxidation of silicon) process or a trench process. Next, using the gate electrode  4  as a mask, ion injection using a p-type or n-type dopant at a low concentration is performed on the device region of the silicon wafer  1 . As a result, LDDs (lightly doped drains)  5  are formed on the device region of the silicon wafer  1 , and side walls  6  are formed to both sides of the gate oxide layer  3  and the gate electrode  4 .  
           [0008]    Following this operation, a conducting dopant identical to that used for the LDDs  5  is ion-injected at a high concentration on the device region of the silicon wafer  1  using the side walls  6  and the gate electrode  4  as a mask to thereby form a source/drain  7 . A titanium silicide layer  8  is then formed on the source/drain  7  and also on the gate electrode  4  to reduce a contact resistance.  
           [0009]    Subsequently, with reference to FIG. 1 b , in order to form a liner layer that acts as an etch stop layer during etching to form contacts and also acts to prevent the diffusion of impurities from a BPSG layer into other elements, a silicon nitride layer  9  is formed over all exposed elements formed on the silicon wafer  1 . The silicon nitride layer  9  is formed by PECVD (plasma enhanced chemical vapor deposition) and at a temperature of approximately 400 Å.  
           [0010]    A large amount of approximately 20˜30 mol % of hydrogen generated in the decomposition process of silane and ammonia is contained in the silicon nitride layer  9 . The hydrogen reacts with a BPSG layer formed in a subsequent process to ionize impurities. That is, the large amount of hydrogen contained in the silicon nitride layer  9  formed by PECVD exists in various forms such as combined with silicon (Si—H, Si—H2, Si—H3) and combined with nitrogen (N—H, NH 2 ). The cohesive strength when combined with silicon, and particularly in Si—H, is especially weak such that these elements are easily separated when receiving an external chemical shock.  
           [0011]    Subsequently, with reference to FIG. 1 c , a BPSG layer  10  is formed as a pre-metal dielectric layer on the silicon nitride layer  9 . The BPSG layer  10  is formed to a thickness of approximately 14,000 Å using SACVD (subatmospheric CVD) and at a temperature of 500° C. To increase the strength of the BPSG layer  10 , heat treating is performed at 700° C. to realize densification.  
           [0012]    With respect to the BPSG layer  10  prior to densification, the bond between boron and oxygen (B—O), phosphorus and oxygen (P—O), and silicon and oxygen (Si—O) is weak such that it is easily broken by external chemical and/or mechanical shock. Therefore, the BPSG layer  10  is densified to increase (by approximately three times) its chemical and mechanical strength.  
           [0013]    However, with the formation of the BPSG layer  10 , Si—H makes contact with the B—O, P—O, and Si—O to react with the same in a state where the Si—H close to the surface of the silicon nitride layer  9  receives the thermal energy of the 500° C. used to deposit the BPSG layer such that its cohesive strength weakens. As a result, hydrogen combines with oxygen, and boron ions (B+), phosphorous ions (P+), and silicon ions (Si+) are generated.  
           [0014]    The boron ions, in particular, diffuse into the silicon nitride layer  9  because of their small atomic radius and superior mobility. As a result, the boron ions exist on the interfacial surface of the titanium silicide layer  8  or are left remaining within the silicon nitride layer  9  such that the boron ions diffuse into the silicon wafer  1  during the heat treating process to perform densification of the BPSG layer  10 .  
           [0015]    Boron diffused in this manner, and in particular, in the PMOS using boron as impurities of the source and drain, acts to reduce the threshold voltage of the same. It is also possible for the boron to cause current leakage. That is, a channel is not removed even with the elimination of an applied voltage for the removal of a gate channel, and the channel is instead weakly formed to thereby cause current leakage.  
           [0016]    Conventional arts related to such diffusion are disclosed in U.S. Pat. Nos. 6,475,847, and 6,420,752.  
         SUMMARY OF THE INVENTION  
         [0017]    In one exemplary embodiment of the present invention, there is provided a method for manufacturing a MOS (metal oxide semiconductor) transistor that prevents the diffusion of boron ions into a silicon wafer during formation of a BPSG (layer, the BPSG layer being formed by SACVD on a silicon nitride layer, which in turn is formed by PECVD.  
           [0018]    In an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a barrier layer on an individual device formed on a semiconductor substrate and including a MOS transistor. An ozone process is performed on the barrier layer, and a pre-metal dielectric (PMD) layer is then formed on the barrier layer.  
           [0019]    The ozone process performed on the barrier layer is performed at a temperature at which ozone is resolved, which is 500° C. Also, the resolved ozone is bonded with a surface of the barrier layer to stabilize the surface of the barrier layer.  
           [0020]    The ozone process performed on the barrier layer is preferably performed for 10˜30 seconds, and the ozone process performed on the barrier layer is preferably performed in a deposition chamber of the PMD layer. Also, a temperature at which the ozone process is performed and a deposition temperature of the PMD layer are preferably substantially identical.  
           [0021]    Preferably, the PMD layer is heat treated following the formation of the PMD layer, and the heat treating is performed at a temperature of 600˜800° C. and for 30˜50 seconds.  
           [0022]    Preferably, the barrier layer is a silicon nitride layer, the silicon nitride layer is formed to a thickness of 200˜400 Å, and the silicon nitride layer is formed by plasma enhanced chemical vapor deposition.  
           [0023]    The PMD layer is preferably formed of a material including boron. As an example, the PMD layer is formed of boron phosphorous silicate glass (BPSG) to thereby form a BPSG layer. The BPSG layer may be formed to a thickness of 10,000˜20,000 Å, by subatmospheric chemical vapor deposition (SACVD).  
           [0024]    The ozone process performed on the barrier layer may be performed in an SACVD chamber. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    The accompanying drawings, which together with the specification, illustrate an exemplary embodiment of the present invention, and, together with the description, serve to explain the principles of the present invention.  
         [0026]    [0026]FIGS. 1 a  through  1   c  are sectional views used to describe a conventional method of manufacturing a MOS transistor.  
         [0027]    [0027]FIGS. 2 a  through  2   d  are sectional views used to describe a method for manufacturing a MOS transistor according to an exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0028]    An exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.  
         [0029]    [0029]FIGS. 2 a  through  2   d  are sectional views used to describe a method for manufacturing a MOS transistor according to an exemplary embodiment of the present invention.  
         [0030]    As shown in FIG. 2 a , a field oxide layer  22  is formed on a predetermined region of a silicon wafer  21  through a LOCOS (local oxidation of silicon) process or a trench process. An area of the silicon wafer  21  on which the field oxide layer  22  is formed is referred to as a device isolation region, while the remainder of the silicon wafer  21  is referred to simply as a device region.  
         [0031]    Next, thermal oxidation of the silicon wafer  21  is performed to grow a gate oxide layer  23  on a surface of the device region of the silicon wafer  21 . Polysilicon is then deposited over all exposed elements of the silicon wafer  21 , then the polysilicon and the gate oxide layer  23  are patterned to a predetermined width. A gate electrode  24  is formed by patterning the polysilicon.  
         [0032]    Using the gate electrode  24  as a mask, ion injection of a p-type or n-type dopant is performed in the device region of the silicon wafer  21  such that LDDs (lightly doped drains)  25  are formed on the silicon wafer  21 , and side walls  26  are formed to both sides of the gate oxide layer  23  and the gate electrode  24 . Following this procedure, ion injection of a conducting dopant identical to that used for the LDDs  25  is performed at a high concentration in the device region of the silicon wafer  21  using the side walls  26  and the gate electrode  24  as a mask. A source/drain  27  is formed through this process.  
         [0033]    Subsequently, using a sputtering process, titanium is deposited to a thickness of approximately 300˜500 over the entire surface of the silicon wafer  21 , then rapid thermal processing (RTP) is performed for 20˜40 seconds and at a temperature of approximately 700˜800° C. while flowing nitrogen at a flow rate of 50 sccm.  
         [0034]    A titanium silicide layer  28  is formed by the reaction between the titanium and silicon. That is, the silicon of the gate electrode  24  and the source/drain  27  reacts with the titanium to form the titanium silicide  28 . Since the silicon does not react with the titanium of the side walls  26  and the filed oxide layer  22 , the titanium on these elements is left remaining as non-reacted titanium. The nonreacted titanium is removed using a solvent so that it does not interfere with device operation.  
         [0035]    Subsequently, with reference to FIG. 2 b , in order to form a barrier layer that acts as an etch stop layer during etching to form contacts and also acts to prevent the diffusion of impurities from a BPSG layer into other elements, a silicon nitride layer  29  is formed over all exposed elements formed on the silicon wafer  21 . The silicon nitride layer  29  is formed by PECVD (plasma enhanced chemical vapor deposition) to a thickness of approximately 200˜400 Å, preferably 300 Å.  
         [0036]    Next, with reference to FIG. 2 c , prior to depositing a BPSG layer as a pre-metal dielectric layer on the silicon nitride layer  29  by SACVD (subatmospheric CVD), an ozone (O 3 ) process is performed for 10˜30 seconds (preferably 20 seconds) at a temperature of approximately 500° C. By performing the ozone process, hydrogen in the Si—H, which has a weak bond, is removed in the vicinity of a silicon nitride surface, and partly replaced with oxygen.  
         [0037]    The ozone process may be performed at the same temperature as the temperature used to deposit the pre-metal dielectric layer and in the same chamber in which the pre-metal dielectric layer is deposited. However, a different temperature and a different chamber may also be used. If the ozone process is performed in an SACVD deposition chamber, that is, the chamber in which a BPSG layer is deposited, the BPSG layer may be formed immediately following the ozone process. As a result, contact with air outside the chamber, which may act as an additional supply of hydrogen, is prevented such that greater stability of boron is realized.  
         [0038]    Subsequently, with reference to FIG. 2 d , a BPSG layer  30  is deposited to a thickness of approximately 10,000 20,000 Å using SACVD. SACVD is performed at a temperature of approximately 500° C. and a pressure of approximately 200 Torr. To increase the strength of the BPSG layer  30 , heat treating is performed at a temperature of 600˜800° C. and for 30˜50 seconds to realize densification.  
         [0039]    If the ozone process is performed in an SACVD deposition chamber, the BPSG layer  30  may be formed in the same deposition chamber without interruption, in which case a source gas for forming the BPSG layer  30  is injected into the SACVD deposition chamber following the ozone process.  
         [0040]    With the formation of the BPSG layer  30 , hydrogen is removed from the surface of the silicon nitride layer  29  such that the surface is easily covered with B—O, P—O, and Si—O, and a relatively strong covalent bond is realized. Also, greater stability is realized following the heat treating process (performed for densification). In the case of B—O in particular, a compound approximating B203 is realized following the heat treating process.  
         [0041]    As described above, the ozone process is performed following the formation of the silicon nitride layer  29  and prior to the formation of the BPSG layer  30  to thereby remove hydrogen. As a result, the B—O bond in the BPSG layer  30  is strengthened to enhance the stability of boron. This, in turn, prevents boron ions from diffusing into the silicon wafer  21 .  
         [0042]    Further, since the BPSG layer  30  may be formed in the same SACVD deposition chamber that the ozone process is performed in, that is, since the BPSG layer  30  may be formed without interruption following the ozone process, contact with the air outside the chamber is prevented. This isolation of the silicon wafer  21  from the air, which is a supply source for nitrogen, prevents the situation where boron ions are generated as a result of the presence of nitrogen. Ultimately, the leakage of current resulting from the diffusion of boron ions into the silicon wafer  21  does not occur, and the resulting heating of the transistor is prevented.  
         [0043]    Although an embodiment of the present invention has been described in detail hereinabove in connection with a certain exemplary embodiment, it should be understood that the invention is not limited to the disclosed exemplary embodiment, but, on the contrary is intended to cover various modifications and/or equivalent arrangements included within the spirit and scope of the present invention, as defined in the appended claims.