Abstract:
A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a high voltage metal-oxide-semiconductor (herein after abbreviated as HV MOS) transistor device and a manufacturing method thereof, and more particularly, to a high voltage lateral double-diffused metal-oxide-semiconductor (HV-LDMOS) transistor device and a manufacturing method thereof. 
         [0003]    2. Description of the Prior Art 
         [0004]    Double-diffused MOS (DMOS) transistor devices have drawn much attention in power devices having high voltage capability. The conventional DMOS transistor devices are categorized into vertical double-diffused MOS (VDMOS) transistor device and lateral double-diffused MOS (LDMOS) transistor device. Having advantages of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other integrated circuit due to its planar structure, LDMOS transistor devices are prevalently used in high operational voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier. The essential feature of LDMOS transistor device is a lateral-diffused drift region with low dopant concentration and large area. The drift region is used to alleviate the high voltage between the drain and the source, therefore the LDMOS transistor device can have high breakdown voltage (BVD). 
         [0005]    It is well-known that characteristics of low ON-resistance (hereinafter abbreviated as R ON ) and high breakdown voltage are always required to the HV MOS transistor device. However, breakdown voltage and R ON  are conflicting parameters with a trade-off relationship. Therefore, a HV LDMOS transistor device that is able to realize high breakdown voltage and low R ON  is still in need. 
       SUMMARY OF THE INVENTION 
       [0006]    According to the claimed invention, a LDMOS transistor device is provided. The LDMOS transistor device includes a substrate having at least a shallow trench isolation (hereinafter abbreviated as STI) formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI. 
         [0007]    According to the claimed invention, another LDMOS transistor device is provided. The LDMOS transistor device includes a substrate having at least a shallow trench isolation (STI) formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the drain region, and the source region include a first conductivity type. 
         [0008]    According to the claimed invention, a method for manufacturing a LDMOS transistor device is provided. According to the method, a substrate having a shallow trench formed therein is provided. An epitaxial layer having a first conductivity type is formed to cover a surface of the shallow trench. After forming the epitaxial layer, a first insulating material is formed on the epitaxial layer and the shallow trench is filled up with the first insulating material. Consequently, a STI is formed. Next, a recess is formed in the STI, and the first insulating material is exposed in the recess. After forming the recess, a gate dielectric layer is formed on the substrate. Then a gate conductive layer is formed in the recess and followed by filling the recess with a second insulating material. 
         [0009]    According to the LDMOS transistor device and the manufacturing method thereof, the epitaxial layer is formed to encompass the STI, therefore, a current path, which is formed during operation, is forced to be closer to the edge of the STI. Consequently, a channel region having very low resistance is resulted. Furthermore, the gate is formed to extend into the bottom of the STI, and thus Ron and breakdown voltage are both improved. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIGS. 1-8  are schematic drawings illustrating a method for manufacturing a LDMOS transistor device provided by a preferred embodiment of the present invention, wherein 
           [0012]      FIG. 2  is a schematic drawing in a step subsequent to  FIG. 1 , 
           [0013]      FIG. 3  is a schematic drawing in a step subsequent to  FIG. 2 , 
           [0014]      FIG. 4  is a schematic drawing in a step subsequent to  FIG. 3 , 
           [0015]      FIG. 5  is a schematic drawing in a step subsequent to  FIG. 4 , 
           [0016]      FIG. 6  is a schematic drawing in a step subsequent to  FIG. 5 , 
           [0017]      FIG. 7  is a schematic drawing in a step subsequent to  FIG. 6 , and 
           [0018]      FIG. 8  is a schematic drawing in a step subsequent to  FIG. 7 . 
           [0019]      FIG. 9  is a schematic drawing illustrating a LDMOS transistor device provided by a modification to the preferred embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]      FIGS. 1-8  are schematic drawings illustrating a method for manufacturing a LDMOS transistor device provided by a preferred embodiment of the present invention. As shown in  FIG. 1 , a substrate  102 , such as a silicon substrate, is provided. A deep well  104  is formed in the substrate  102 . The deep well  104  includes a first conductivity type while the substrate  102  includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. In the preferred embodiment, the first conductivity type is an n type and the second conductivity type is a p type. Then, a pad oxide layer  106  and a patterned hard mask (not shown) for defining placement and size of a plurality of isolation structures are sequentially formed on the substrate  102 . Next, the pad oxide layer  106  and substrate  102  are etched with the patterned hard mask serving as an etching mask. Consequently, a plurality of shallow trenches  108  are formed in the substrate  102 . 
         [0021]    Please refer to  FIG. 2 . After forming the shallow trenches  106 , an epitaxial layer  110  is formed on inner surface of the shallow trench  108 . In the preferred embodiment, the epitaxial layer  110  is formed by performing a selective epitaxial growth (SEG) method. It is noteworthy that since the epitaxial material grows from exposed Si-surface during the SEG method, the sidewalls and bottoms surface of the shallow trench  108  is covered by the epitaxial layer  110  as shown in  FIG. 2 . In the preferred embodiment, the epitaxial layer  110  preferably includes silicon and the first conductivity type. In other words, the epitaxial layer  110  provided by the preferred embodiment is an n-Si epitaxial layer. 
         [0022]    Please refer to  FIG. 3 . After forming the epitaxial layer  110 , an insulating material is formed to fill up the shallow trenches  108  and followed by performing a planarization process. Consequently, superfluous insulating material and the pad oxide layer  106  are removed and a plurality of STIs  120  are for formed in the substrate  102 . Some of the STIs  120  are used to provide electrical isolation between the LDMOS transistor device from other devices. As shown in  FIG. 3 , one STI  120  is formed in the deep well  104 . More important, the STI  120  in the deep well  104  is encompassed by the epitaxial layer  110 . In other words, the epitaxial layer  110  contacts the bottom and the sidewalls of the STI  120 . 
         [0023]    Please still refer to  FIG. 3 , after forming the STI  120 , a first well region  130  and a second well region  150  are formed in the substrate  102 . The first well region  130  includes the first conductivity type and the second well region  150  includes the second conductivity type in the preferred embodiment. Therefore, the first well region  130  is an n-well region and the second well region  150  is a p-well region. As shown in  FIG. 3 , the first well region  130  and the second well region  150  are all formed in the deep well  104  but spaced apart from each other. Furthermore, a dopant concentration of the deep well  104  is lower than a dopant concentration of epitaxial layer  110 , and the dopant concentration of the epitaxial layer  110  is lower than a dopant concentration of the first well region  130 . 
         [0024]    Please refer to  FIG. 4 . Next, an etch process is performed to remove a portion of the insulating material from the STI  120 , and thus a recess  122  is formed in the STI  120 . It is noteworthy that a width of the recess  122  is smaller than a width of the STI  120 . Therefore, the insulating material of the STI  120  is exposed in the recess  122  as shown in  FIG. 4 . 
         [0025]    Please refer to  FIGS. 5-6 . After forming the recess  122  in the STI  120 , an insulating layer  124  and a conductive layer, such as a polysilicon layer  126  are sequentially formed on the substrate  102 . Next, the polysilicon layer  126  and the insulating layer  124  are patterned, and thus a gate  140  is obtained as shown in  FIG. 6 . It is noteworthy that the gate  140  includes a first portion  142  formed on the substrate  102  and a second portion  144  extending into the recess  122  in the STI  120 . And the second portion  144  of the gate  140  covers a sidewall and a bottom of the STI  120 . In the preferred embodiment, a length of the second portion  144  of the gate  140  is smaller than a width of the STI  120 . However, the length of the second portion  144  of the gate  140  can be not only smaller than but also equal to the width of the recess  122 . Additionally, the gate  140  is electrically isolated from the epitaxial layer  110  by the STI  120 . And a distance between the gate  140  and the epitaxial layer  110 , that is the overall thickness of the insulating layer  124  and the STI  120  between the bottom of the recess  122  and the epitaxial layer  110 , and between the sidewall of the recess  122  and the epitaxial layer  110  are preferably the same, but not limited to this. 
         [0026]    Furthermore, in another embodiment of the present invention, the epitaxial layer  110  is exposed by the recess  122 . However, the gate  140  is still electrically isolated from the epitaxial layer  110  by the insulating layer  124 . 
         [0027]    Please refer to  FIG. 7 . After forming the gate  140 , a spacer (not shown) is formed on sidewalls of the gate  140 . Next, a drain region  132 , a source region  152 , and a doped region  154  are formed in the substrate  102 . As shown in  FIG. 7 , the drain region  132  is formed in the first well region  130  while the source region  152  and the doped region  154  are formed in the second well region  150 . Furthermore, the source region  152  and the doped region  154  abut upon each other. According to the preferred embodiment, the drain region  132  and the source region  152  both include the first conductivity type and the doped region  154  includes the second conductivity type. Therefore, the preferred embodiment provides an n-drain region  132 , an n-source region  152 , and a p-doped region  154 . 
         [0028]    Please refer to  FIG. 8 . After forming the gate  130 , another insulating material  128  is formed on the substrate  102 . It is noteworthy that the recess  122  in the STI  120  is filled up with the insulating material  128 . More important, the insulating material  128  serves as an interlayer dielectric (ILD) layer according to the preferred embodiment. Consequently, a LDMOS transistor device  100  is constructed and an even surface is obtained. 
         [0029]    Please refer to  FIG. 9 , which is a schematic drawing illustrating a LDMOS transistor device provided by a modification to the preferred embodiment. Please note that elements the same in both of the preferred embodiment and the modification are designated by the same numerals. And those identical elements can include the same materials and conductivity types, therefore the related description is omitted for simplicity. More important, the modification is subsequent to forming the epitaxial layer, the STI, the first well region, and the second well region, thus  FIG. 9  can be a schematic drawing in a step subsequent to  FIG. 3 . As shown in  FIG. 9 , after forming the epitaxial layer  110 , the STI  120 , the first well region  130 , and the second well region  150 , a gate including an insulating layer  124  and a conductive layer such as a polysilicon layer  126  is formed on the substrate  102 . As shown in  FIG. 9 , the gate  140  is electrically isolated from the epitaxial layer  110  by the STI  120  and the insulating layer  124 . 
         [0030]    Please still refer to  FIG. 9 . Next, a spacer (not shown) is formed on sidewalls of the gate  140 . Next, a drain region  132 , a source region  152 , and a doped region  154  are formed in the substrate  102 , and thus a LDMOS transistor device  100  is obtained. Since the spatial relationship between those elements and conductivity types are all the same with those described in the aforementioned preferred embodiment, those details are omitted for simplicity. Then, the LDMOS transistor device  100  is covered and protected by an insulating material  128  formed on the substrate  102 . As mentioned above, the insulating material  128  serves as an interlayer dielectric layer. 
         [0031]    According to the LDMOS transistor device provided by the preferred embodiment, the epitaxial layer is formed to encompass the STI. Therefore, a current path, which is formed during operation, is forced to be closer to the edge of the STI. Consequently, a channel region having very low resistance is resulted. Furthermore, since the second portion of the gate is formed to extend into the bottom of the STI, Ron and breakdown voltage are both improved. 
         [0032]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.