Abstract:
Provided are a method of fabricating a multilayered thin film transistor using a plastic substrate and an active matrix display device including the thin film transistor fabricated by the method. The method includes: preparing a substrate formed of plastic; forming a buffer insulating layer on the plastic substrate; forming a silicon layer on the buffer insulating layer; patterning the silicon layer to form an active layer; forming a gate insulating layer on the active layer; stacking a plurality of gate metal layers on the gate insulating layer; patterning the plurality of gate metal layers; and etching a corner region of the lowest gate metal layer formed on the gate insulating layer of the patterned gate metal layers. Accordingly, a gate metal is formed which includes a multilayered gate metal layer and has an etched corner region, thereby reducing an electric field of the corner to reduce a leakage current of the TFT.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of Korean Patent Application No. 2006-123955, filed on Dec. 7, 2006,the disclosure of which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention is related to an active matrix display device formed on a plastic substrate and a method of fabricating the same, and more particularly, to a method of fabricating a thin film transistor including a multilayered gate electrode and an active matrix display device including the thin film transistor. 
         [0004]    The present invention has been produced from the work supported by the IT R&amp;D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2005-S070-02, Flexible Display] in Korea. 
         [0005]    2. Discussion of Related Art 
         [0006]      FIG. 1  is a side cross-sectional view of a conventional active matrix display device. 
         [0007]    Referring to  FIG. 1 , the conventional active matrix display device  100  includes a thin film transistor (TFT) formed on a glass substrate  110 , and a capacitor and an organic light emitting diode (OLED) which are electrically connected to the TFT. 
         [0008]    The TFT constituting the active matrix display device  100  includes a buffer insulating layer  120  formed on the glass substrate  110 , an active layer  130  formed on the buffer insulating layer  120  and having source and drain regions  132  and a channel region  131 , a gate insulating layer  140  formed on the active layer  130 , a gate electrode  150  formed on the gate insulating layer  140 , an interlayer dielectric  160  formed on the gate electrode  150 , and source and drain electrodes  170  in contact with the source and drain regions  132  through a contact hole  161  formed on the interlayer dielectric  160 . 
         [0009]    When the active matrix display device  100  is fabricated on the glass substrate  110 , in particular, when the TFT is fabricated, the doping profile of the active region  131  of the active layer  130  can be adjusted using lithography equipment to form a lightly doped drain (LDD). 
         [0010]    However, when the active matrix display device is formed of a plastic substrate, the plastic substrate, unlike the glass substrate, is apt to be thermally deformed, so that metal of a gate metal layer is broken by stress due to a post annealing process when the relatively thick gate metal layer is deposited on the plastic substrate. When several layers need to be aligned in consideration of the thermal deformation of the plastic substrate, overlay accuracy becomes severely worse so that it is difficult to form an LDD without using a self-alignment process. 
         [0011]    Further, according to a structure generated by etching of both sides of the gate metal and dopant diffusion due to subsequent laser activation for forming the self-aligned LDD on the plastic substrate (see “Fabrication of Low-Temperature Poly-Si Thin Film Transistor with Self-Aligned Graded Lightly Doped Drain Structure,” Electrochemical and Solid-State Letters, Huang-Chung Cheng), it is difficult to adjust the doping profile, and not only a leakage current but also a driving current is decreased. 
         [0012]    Depositing thin amorphous silicon on polysilicon to form a dual active structure (see “Performance improvement of polycrystalline thin film transistor by adopting a very thin amorphous silicon buffer,” J. Non-Crystalline Solids, Kyung Wook Kim) requires a gate dielectric of high quality to be formed and amorphous silicon of good quality to be formed at a low temperature. 
       SUMMARY OF THE INVENTION 
       [0013]    The present invention is directed to an active matrix display device including multilayered gate metal layers and etching a corner of at least one gate metal layer of the multilayered gate metal layers to reduce a leakage current in a TFT region, and a method of fabricating the same. 
         [0014]    One aspect of the present invention provides a method of fabricating a thin film transistor, which includes: preparing a substrate formed of plastic; forming a buffer insulating layer on the plastic substrate; forming a silicon layer on the buffer insulating layer; patterning the silicon layer to form an active layer; forming a gate insulating layer on the active layer; stacking a plurality of gate metal layers on the gate insulating layer; patterning the plurality of gate metal layers; and etching a corner region of the lowest gate metal layer formed on the gate insulating layer of the patterned gate metal layers. 
         [0015]    The method may further include etching a corner region of the highest gate metal layer when the number of the gate metal layers is more than three. The highest gate metal layer of the plurality of gate metal layers may be formed of a material having a high reflectivity such as Al, Ag, an Al alloy, or an Ag alloy. The gate metal layer in direct contact with the lowest gate metal layer of the plurality of gate metal layers may be formed of a different material from the lowest gate metal layer. 
         [0016]    Another aspect of the present invention provides an active matrix display device comprising a thin film transistor fabricated by the method according to one aspect of the present invention, and a capacitor and an organic light emitting diode which are electrically connected to the thin film transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which: 
           [0018]      FIG. 1  is a side cross-sectional view of a conventional active matrix display device; 
           [0019]      FIGS. 2A to 2E  are views illustrating a process of fabricating a TFT in accordance with a first embodiment of the present invention, and  FIG. 3  is a block diagram illustrating steps of the process of  FIGS. 2A to 2E ; 
           [0020]      FIG. 4  is a Scanning Electron Microscope (SEM) picture of an active matrix display device fabricated using chromium for a first gate metal layer and aluminum for a second gate metal layer in accordance with the present invention; 
           [0021]      FIG. 5A  is a graph illustrating changes in characteristics of a TFT fabricated by the conventional method, and  FIG. 5B  is a graph illustrating changes in characteristics of a TFT fabricated by the present invention; and 
           [0022]      FIGS. 6A to 6E  are views illustrating a process of fabricating a TFT in accordance with a second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0023]    Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
         [0024]      FIGS. 2A to 2E  are views illustrating a process of fabricating a TFT in accordance with a first embodiment of the present invention, and  FIG. 3  is a block diagram illustrating steps of the process of  FIGS. 2A to 2E . 
         [0025]    Referring to  FIGS. 2A and 3 , in order to fabricate an active matrix display device  200  according to the present invention, a plastic substrate  110  is first prepared (S 301 ). A buffer insulating layer  120  is formed on the plastic substrate  110  (S 302 ). The buffer insulating layer  120  may be formed of oxide or nitride. After amorphous silicon to be used for an active layer is deposited on the substrate  110  where the buffer insulating layer  120  is already formed, a solid crystallization method using a laser (L:↓ ↓) or the like is employed to obtain a transformed polysilicon layer  121  (S 303 ). 
         [0026]    In the next step, referring to  FIG. 2B , the transformed polysilicon layer  121  is patterned to form an active layer  130  where a channel region  131  and source and drain regions  132  are to be formed (S 304 ). A gate dielectric layer  140  is deposited on the patterned active layer  130  (S 305 ). A multilayered gate metal layer  150  is then formed on the gate dielectric layer  140 . The gate metal layer  150  is composed of a first gate metal layer  151  and a second gate metal layer  152  in the present embodiment, the first gate metal layer  151  is formed on the gate dielectric layer  140  (S 306 ), and the second gate metal layer  152  is formed on the first gate metal layer  151  (S 307 ). The first gate metal layer  151  must be deposited to a thickness enough to endure a post annealing process. The first gate metal layer  151  may be deformed when the deposited first gate metal layer  151  is too thick, so that it is deposited to a thickness of about 100 Å to about 300 Å. Any one of chromium (Cr) and molybdenum (Mo) is used for the first gate metal layer  151  in the first embodiment. The deposition thickness of the second gate metal layer  152  formed on the first gate metal layer  151  is adjusted so as to have source and drain resistances meet a design specification, and is preferably 1000 Å to 3000 Å. At this time, the second gate metal layer  152  is preferably formed of a material having a good reflectivity with respect to laser light compared to the first gate metal layer  151 . Any one of silver, aluminum, a silver alloy, and an aluminum alloy, which have good reflectivities, is used for the second gate metal layer  152 , and aluminum (Al) is used for depositing the second gate metal layer  152  in the present embodiment. Also, the first and second gate metal layers  151  and  152  have to have good wet etching selectivities. 
         [0027]    Referring to  FIG. 2B , after a photosensitive layer  155  is deposited on the second gate metal layer  152 , a photo process is used to pattern the first gate metal layer  151  and the second gate metal layer  152  (S 308 ). At this time, the gate dielectric layer  140  is patterned together. In other words, after the photosensitive layer  155  is formed by a spin-coating method, the photo process is used to etch the second gate metal layer  152  and the first gate metal layer  151 , so that the first and second gate metal layers  151  and  152  are patterned in the present embodiment. 
         [0028]    In the next step, referring to  FIGS. 2C and 2D , the gate dielectric layer  140  is etched. A doping process (D) is performed after the gate dielectric layer  140  is etched (S 309 ), so that doped source and drain regions  132  are formed (S 310 ). Ion shower doping is performed in the present embodiment. The photosensitive layer  155  is removed in the next step, and after the photosensitive layer  155  is removed, an activation step using the laser L is performed to activate the doped source and drain regions  132  (S 311 ). The patterned first gate metal layer  151  is selectively wet-etched (S 312 ). During the etching process, since the first gate metal layer  151  is deposited to a thin thickness, the first gate metal layer must be etched for a longer time, e.g., about 5 minutes to about 30 minutes, than the known etching rate. 
         [0029]    Referring to  FIG. 2E , an interlayer dielectric (ILD)  160  is formed on the gate metal layer  150  (S 313 ). After a contact hole  161  is formed in the ILD  160 , a source and drain metal  170  is deposited on the ILD  160  to be in contact with the source and drain regions  132  through the contact hole  161  (S 314 ). Accordingly, a TFT is fabricated. Although not described and illustrated in the present embodiment and the drawings, a capacitor and an OLED may be fabricated along with the TFT to fabricate an active matrix display device as in the conventional method. 
         [0030]      FIG. 4  is a SEM picture of a region of an active matrix display device including a dual gate metal layer in accordance with an embodiment of the present invention. In the present embodiment, Cr is used for the first gate metal layer  151  and Al is used for the second gate metal layer  152  in the dual gate metal layer  150 . Referring to  FIG. 4 , the first gate metal layer  151  with a depressed corner is formed on the substrate  110 . The second gate metal layer  152 , which has a relatively thick thickness compared to the first gate metal layer  151 , is formed on the first gate metal layer  151 . In the present embodiment, the first gate metal layer of Cr  151  having a thickness of 21.6 nm is deposited, and the second gate metal layer of Al  152  having a thickness of 232 nm is deposited. When wet etching is performed on the first gate metal layer  151  for 10 minutes after each of the gate metal layers is deposited as in the present embodiment, about 100 nm must be etched on the basis of an etching rate of each of the metal layers, however, the first gate metal layer  151  is relatively thinly deposited, so that it is formed to a thinner thickness than the reference etching rate and is etched by about 40 nm in the present embodiment. Accordingly, an electric field at the corner of the gate can be reduced to reduce a leakage current of the TFT. 
         [0031]      FIG. 5A  is a graph illustrating changes in characteristics of a TFT fabricated by the conventional method, and  FIG. 5B  is a graph illustrating changes in characteristics of a TFT fabricated by the present invention. 
         [0032]    Referring to  FIGS. 5A and 5B , a horizontal axis denotes a gate voltage and a vertical axis denotes a current. Comparing  FIG. 5A  with  FIG. 5B , it can be found that the leakage current is relatively lower than the TFT fabricated by the conventional method when a plurality of metal layers are stacked on the plastic substrate to fabricate a gate electrode in accordance with the present invention. 
         [0033]      FIGS. 6A to 6E  are views illustrating a process of fabricating a TFT in accordance with a second embodiment of the present invention. The same reference symbols refer to the same constitutional components as the active matrix display device according to the first embodiment illustrated in  FIGS. 2A to 2E , and some of the constitutional components refer to the description of  FIGS. 2A to 2E . 
         [0034]    Referring to  FIG. 6A , in order to fabricate an active matrix display device  600  according to the second embodiment of the present invention, a plastic substrate  110  is first prepared, and a buffer insulating layer  120  is formed on the plastic substrate  110 . The buffer insulating layer  120  may be formed of oxide or nitride. After amorphous silicon to be used for an active layer is deposited on the substrate  110  where the buffer insulating layer  120  is already formed, a crystallization method using a laser or the like is employed to obtain a transformed polysilicon layer  121 . 
         [0035]    Referring to  FIG. 6B , the polysilicon layer  121  is patterned to form an active layer  130 , and a gate dielectric layer  140  is deposited on the patterned active layer  130 . A gate metal layer  150  is formed on the gate dielectric layer  140 . The gate metal layer  150  is composed of triple layers in the present embodiment, and a first gate metal layer  151  is formed on the gate dielectric layer  140 . The first gate metal layer  151  is deposited to a thickness of about 100 Å to about 1000 Å. Any one of silver, aluminum, a silver alloy, and an aluminum alloy, which have good reflectivities, is used for the first gate metal layer, and Al is used for the deposition in the present embodiment. In this case, the greater the first gate metal layer  151  has a thickness, the smaller the corner of the gate electrode has an electric field, thereby obtaining an effect of reducing a leakage current. A second gate metal layer  152  is formed on the first gate metal layer  151 , and a third gate metal layer  153  is formed on the second gate metal layer  152 . 
         [0036]    The second gate metal layer  152  is preferably deposited to a thickness enough to endure a post annealing process, and is most preferably deposited to a thickness of 100 Å to 300 Å. The deposition thickness of the third gate metal layer  153  is adjusted so as to have source and drain resistances meet a design specification, and is preferably 1000 Å to 3000 Å. In the present embodiment, the second gate metal layer  152  is formed of any one of Cr and Mo. At this time, the third gate metal layer  153  is preferably formed of a material having a good reflectivity with respect to laser light compared to second gate metal layer  152 , and the first gate metal layer  151  and the second gate metal layer  152 , and the second gate metal layer  152  and the third gate metal layer  153 , must have good wet etching selectivities, respectively. 
         [0037]    After a photosensitive layer  155  is deposited on the third gate metal layer  153 , a photo process is used to pattern the first gate metal layer  151  to the third gate metal layer  153 . When the first gate metal layer  151  to the third gate metal layer  153  are patterned, the gate dielectric layer  140  is patterned together. The photosensitive layer  155  is formed by a spin-coating method in the present embodiment. The patterned third gate metal layer  153 , the patterned second gate metal layer  152 , and the patterned first gate metal layer  151  are then etched. 
         [0038]    In the next step, the gate dielectric layer  140  is etched. After the gate dielectric layer  140  is etched, a doping process is performed to form doped source and drain regions  132 . Ion shower doping (D) is performed in the present embodiment. The photosensitive layer  155  is then removed, and after the photosensitive layer  155  is removed, an activation step using a laser (L) is performed to activate the doped source and drain regions  132 . The patterned first gate metal layer  151  and the patterned third gate metal layer  153  are then selectively wet-etched. During the etching process, since the first gate metal layer  151  is deposited to a thin thickness, the first gate metal layer  151  must be etched for a longer time, e.g., about 5 minutes to about 30 minutes, than the known etching rate. Meanwhile, when the third gate metal layer  153  and the first gate metal layer  151  are formed of the same metal, they may be simultaneously etched. 
         [0039]    In the next step, an ILD  160  is formed on the gate electrode. After a contact hole  161  is formed on the ILD  160 , a source and drain metal  170  is formed on the ILD  160  to be in contact with the source and drain regions  132  through the contact hole  161 . Accordingly, the TFT is fabricated. Although not described above, a capacitor and an OLED may be fabricated along with the fabrication of the TFT. 
         [0040]    According to embodiments of the present invention as described above, when an active matrix display device including a multilayered gate electrode having a gate electrode layer with an etched corner is fabricated on a plastic substrate, an electric field of the etched corner can be reduced so that a leakage current of a TFT can be reduced. 
         [0041]    Also, the characteristics of an active matrix display device can be enhanced by enhancement of the characteristics of the TFT including the multilayered gate electrode. 
         [0042]    Although exemplary embodiments of the present invention have been described with reference to the attached drawings, the present invention is not limited to these embodiments, and it should be appreciated to those skilled in the art that a variety of modifications and changes can be made without departing from the spirit and scope of the present invention.