Abstract:
An automatic equalizer is provided that can suppress errors in code decisions by constraining the selection of survivor paths in a Viterbi calculation. A constraint condition selection circuit  106  inputs the received signal and outputs constraint condition selection signals for selecting constraint conditions corresponding to the regularity of the code that is to be decided, a constraint condition generation circuit inputs k M  series of candidate signals and constraint condition selection signals, selects the regularity of the code corresponding to the constraint condition selection signal, determines the constraint conditions for each of k M−1  states of a trellis diagram based on k M  series of candidate signals, and outputs the constraint condition signal, and a Viterbi calculation circuit  103  inputs the k M  estimated error signals and the constraint condition signals, and generates and outputs a decision output signal based on the k M  estimated error signals and the constraint condition signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an automatic equalizer that compensates a received signal that has been subject to distortion due to intersymbol interference, and in particular, relates to a technology for constraining the survivor paths based on the regularity of the code. 
     2. Description of the Related Art 
     Conventionally, a received signal has distortions due to the condition of its transmission channel. One method of compensating this distortion is using an automatic equalizer at the receiver. Here, a conventional automatic equalizer is explained referring to FIG.  8 . 
     FIG. 8 is a structural drawing of a conventional automatic equalizer. 
     In FIG. 8, reference numeral  501  is an estimation receiving circuit that generates k M  estimated received signals by convolutionally processing k M  series of candidate signals S scan  that are a combination of transmitted code having an M chip length (where M is a natural number) and k levels (where k is a natural number) and the impulse response h of a transmission channel having length M, and outputs these generated k M  estimated received signals S er . These k M  estimated received signals S er  are the signals that are estimated to be the received signals S r . 
     Reference numeral  502  is a subtracter that generates k M  estimated error signals S err  by subtracting the k M  estimated received signals S er , from the received signal S r , and outputting these generated k M  estimated error signals S err . 
     Reference numeral  503  is a Viterbi logic circuit that is structured from the path metric calculating circuit  504  and the survivor path selection circuit  505 , described below. 
     Reference numeral  504  is a path metric calculating circuit that inputs the k M  estimated error signals S err  and the k M−1  survivor path metric signals S pmsv  corresponding to each state of a trellis diagram, squares the absolute value of the k M  estimated error signals S err  corresponding respectively to the k M−1  survivor path metric signals S pmsv  to generate k M  path metric signals S pm , and outputs these generated k M  path metric signals S pm . 
     Reference numeral  505  is a survivor path selection circuit that inputs the k M  path metric signals S pm , determines the smallest among the k M  path metric signals S pm  for each k M−1  states, outputs these as k M−1  survivor path metric signals S pmsv , and at the same time, among the k M  series of candidate signals S scan , outputs as the decision output signals S d  a portion of the series of candidate signals S scan  corresponding to the smallest among the k M−1  survivor path metric signals S pmsv . That is, the survivor path selection circuit  505  carries out the code decision of the received signals. 
     Reference numeral  506  is an error correction circuit that generates an error correction decision output signal S ed  by correcting the decision output signal S d  by the regularity of the code, and outputs this generated error correction decision output signal S ed . 
     However, the conventional automatic equalizer as described above carries out error correction using the error correction circuit  502  after code the decision, and thus in the case that an error in the code decision is propagated, the error correction effect by the error correction circuit  502  is diminished. 
     Therefore, in consideration of this problem, it is an object of the present invention to provide a technology that can resolve the above-described problem, and improve the error correction effect even in the case that an error in the code decision in the automatic equalizer is propagated. 
     SUMMARY OF THE INVENTION 
     The above described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a k M  series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number) and a transmission channel impulse response having a length M, and estimates a received signal by respectively carrying out convolutional processing on the k M  series of candidate signals and the transmission channel impulse response having length M; a subtracter that inputs the received signal and the k M  estimated received signals, generates k M  estimated error signals by subtracting each of the k M  estimated received signals from the received signal, and outputting the generated k M  estimated error signals; a constraint condition selection circuit that inputs the received signal, generates a constraint condition selection signal that represents the regularity of the code of the received signal, and outputs this generated constraint condition selection signal; a constraint condition generation circuit that inputs the k M  series of candidate signals and the constraint condition selection signal, determines the constraint condition for each of k M−1  states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents and the k M  series of candidate signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the k M  estimated error signals and the constraint condition signal, generates decision output signals based on the k M  estimated error signals and the constraint condition signal, and outputs the generated decision output signals. 
     In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimated circuit that inputs a k M  series of candidate signals that are combinations of a transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number) and a transmission channel impulse response having a length M, and estimates a received signal by respectively carrying out convolutional processing on the k M  series of candidate signals and the transmission channel impulse response having length M; a subtracter that inputs the received signal and the k M  estimated received signals, generates k M  estimated error signals by subtracting each of the k M  estimated received signals from the received signal, and outputting the generated k M  estimated error signals; a constraint condition selection circuit that inputs decision output signals, generates constraint selection signal that represents the regularity of the code of the received signals, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the k M  series of candidate signals and the constraint condition selection signal, determines the constraint condition for each of k M−1  states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents and the k M  series of candidate signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the k M  estimated error signals and the constraint condition signal, generates decision output signals based on the k M  estimated error signals and the constraint condition signal, and outputs the generated decision output signals. 
     In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimated circuit that inputs a k M  series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number), k M−1  hypothetical output signals having an N chip length (where N is a natural number), and a transmission impulse response having a length (M+N), and estimates a received signal by carrying out convolutional processing of the combination of the k M  series of candidate signals and the k M−1  hypothetical output signals respectively corresponding to the k M  series of candidate signals and the transmission impulse response having a length (M+N); a subtracter that inputs the received signal and the k M  estimated received signals, generates k M  estimated error signals by subtracting each of the k M  estimated received signals from the received signal, and outputting the generated k M  estimated error signals; a constraint condition selection circuit that inputs the received signal, generates constraint selection signal that represents the regularity of the code of the received signals, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the k M  series of candidate signals, the k M−1  hypothetical output signals, and the constraint condition selection signal, determines the constraint condition for each of k M−1  states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents, the k M  series of candidate signals, and the k M−1  hypothetical output signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the k M  estimated error signals and the constraint condition signal, generates the decision output signals and k M−1  hypothetical output signals for each state of a trellis diagram by carrying out code decisions based on the k M  estimated error signals and the constraint condition signal, and outputs the generated decision output signals and the k M−1  hypothetical output signals for each state of the trellis diagram. 
     In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a k M  series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number), k M−1  hypothetical output signals having an N chip length (where N is a natural number), and a transmission impulse response having a length (M+N), and estimates a received signal by carrying out convolutional processing on the combination of the k M  series of candidate signals and the k M−1  hypothetical output signals respectively corresponding to the k M  series of candidate signals, and the transmission impulse response having a length (M+N); a subtracter that inputs the received signal and the k M  estimated received signals, generates k M  estimated error signals by subtracting each of the k M  estimated received signals from the received signal, and outputting these generated k M  estimated error signals; a constraint condition selection circuit that inputs the decision output signals, generates a constraint selection signal that represents the regularity of the code of the received signals, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the k M  series of candidate signals, the k M−1  hypothetical output signals, and the constraint condition selection signal, determines the constraint condition for each of k M−1  states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents, the k M  series of candidate signals, and the k M−1  hypothetical output signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the k M  estimated error signals and the constraint condition signal, generates the decision output signals and k M−1  hypothetical output signals for each state of a trellis diagram by carrying out code decisions based on the k M  estimated error signals and the constraint condition signal, and outputs the generated decision output signals and the k M−1  hypothetical output signals for each state of the trellis diagram. 
     In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a k M  series of candidate signals that are combinations of transmitted code having M chip length (where M is a natural number) and k levels (where K is a natural number), a decision output signal having an N chip length (where N is a natural number), and a transmission channel impulse response-having a length (M+N), and estimates a received signal by carrying out convolutional processing on the combination of the k M  series of candidate signals and the k M−1  hypothetical-output signals respectively corresponding to the k M  series of candidate signals with the transmission impulse response having a length (M+N) and outputs the estimated k M  estimated received signals; a subtracter that inputs the received signal and the k M  estimated received signals, generates k M  estimated error signals by subtracting each of the k M  estimated received signals from the received signal, and outputting these generated k M  estimated error signals; a constraint condition selection circuit that inputs the received signal, generates a constraint condition selection signal that represents the regularity of the code of the received signal, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the k M  series of candidate signals, the decision output signal, and the constraint condition selection signal, determines the constraint condition for each of k M−1  states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents, the k M  series of candidate signals, and the decision output signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the k M  estimated error signals and the constraint condition signal, generates decision output signals based on the k M  estimated error signals and the constraint condition signal, and outputs the generated decision output signals. 
     In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a k M  series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number), decision output signals having an N chip length (where N is a natural number), and a transmission impulse response having a length (M+N), and estimates a received signal by carrying out combinational processing of the combination of the k M  series of candidate signals and the k M−1  hypothetical output signals respectively corresponding to the k M  series of candidate signals with the transmission impulse response having a length (M+N) and outputting the estimated k M  estimated received signals; a subtracter that inputs the received signal and the k M  estimated received signals, generates k M  estimated error signals by subtracting each of the k M  estimated received signals from the received signal, and outputting these generated k M  estimated error signals; a constraint condition selection circuit that inputs the decision output signals, generates a constraint condition selection signal that represents the regularity of the code of the received signal, and outputs these generated constraint condition selection signal; a constraint condition generation circuit that inputs the k M  series of candidate signals, the decision output signals, and the constraint condition selection signal, determines the constraint condition for each of k M−1  states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents, the k M  series of candidate signals, and the decision output signals, and outputs the constraining condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the k M  estimated error signals and the constraint condition signal, generates the decision output signals based on the k M  estimated error signals and the constraint condition signal, and outputs the generated decision output signals. 
     In addition, the Viterbi calculation circuit is characterized in comprising a path metric calculation circuit that inputs the k M  estimated error signals and the k M−1  survivor path metric signals corresponding to each state of the trellis diagram, calculates the absolute value of the K M  estimated error signals respectively corresponding to the k M−1  survivor path metric signals, and outputs the generated k M  path metric signals, and a survivor path selection circuit that inputs the k M  path metric signals and the constraint condition signal, determines among the k M  path metric signals the one for which the state transition in the trellis diagram satisfy and minimize the constraint condition represented by the constraint condition signal for each of k M  conditions, and outputs the result as the k M−1  survivor path metric signals, and at the same time outputs as decision output signals a specified portion of the k M  series of candidate signals corresponding to those for which the k M−1  series of candidate signals are minimal. 
     In addition, the Viterbi calculation circuit is characterized in comprising a path metric calculation circuit that inputs the k M  estimated error signals and the k M−1  survivor path metric signals corresponding to each state of the trellis diagram, calculates the absolute value of the K M  estimated error signals respectively corresponding to the k M−1  survivor path metric signals, and outputs the generated k M  path metric signals, and a survivor path selection circuit that inputs the k M  path metric signals and the constraint condition signal, determines among the k M  path metric signals those for which the state transition in the trellis diagram satisfy and minimize the constraint condition represented by the constraint condition signal for each of k M  conditions, and outputs the result as the k M−1  survivor path metric signals, and at the same time outputs as hypothetical output signals a specified portion of the k M  series of candidate signals respectively corresponding to the k M−1  survivor path metric signals, and outputs as decision output signals a specified portion of the k M  series of candidate signals corresponding to those among the k M−1  survivor path metric signals that are minimal. 
     In addition, the Viterbi calculation circuit is characterized in comprising a path metric calculation circuit that inputs the k M  estimated error signals and the k M−1  survivor path metric signals corresponding to each state of the trellis diagram, squares the absolute value of the k M  estimated error signals corresponding respectively to the k M−1  survivor path metric signals, and outputs the results as k M  path metric signals, a path metric offset circuit that inputs the k M  path metric signals and the constraint condition signal, and outputs kM offset path metric signals having added a specified offset value only to those among the kM path metric signals for which the state transitions of the trellis diagram do not fulfill the constraint conditions represented by the constraint condition signal, and a survivor path selection circuit that inputs the k M  offset path metric signals, determines for each of the k M−1  state those among the k M  offset path metric signals that are minimal, and outputs the result as the k M−1  survivor path metric signals, and at the same time outputs as hypothetical output signals a specified portion of the series of candidate signals among the k M  series of candidate signals for which the corresponding k M−1  survivor path metric signals are minimal. 
     In addition, the Viterbi calculation circuit is characterized in comprising a path metric calculation circuit that inputs the k M  estimated error signals and the k M−1  survivor path metric signals corresponding to each state of the trellis diagram, and outputs the k M  path metric signals having added the square of the absolute value of the k M  estimated error signals corresponding respectively to the k M−1  survivor path metric signals, a path metric offset circuit that inputs the k M  path metric signals and the constraint condition signal, adds a specified offset value only to those among the k M  path metric signals for which the state transition in the trellis diagram does not satisfy the constraint condition represented by the constraint condition signal, and outputs the result as k M  offset path metric signals, and a survivor path selection circuit that inputs the k M  offset path metric signals, determines among the k M  offset path metric signals those that are minimal for each of k M−1  conditions, and outputs the result as the k M−1  survivor path metric signals, and at the same time outputs as hypothetical output signals a specified portion of the series of candidate signals among the k M  series of candidate signals that correspond respectively to the k M−1  survivor path metric signals, and in addition, outputs as the decision output signals a specified portion of the series of candidate signals among the k M  series of candidate signals those for which the corresponding k M−1  survivor path metric signals are minimal. 
     In addition, the Viterbi calculation circuit is characterized in comprising an estimated error offset circuit that inputs the k M  estimated error signals and the constraint condition signal, and among the k M  estimated error signals, outputs the k M  offset estimated error signals having added a specified offset value only to those for which the state transitions in the trellis diagram do not satisfy the constraint condition represented by the constraint condition signal, a path metric calculation circuit that inputs the k M  offset estimated error signals and the k M−1  survivor path metric signals corresponding to each condition of the trellis diagram, and outputs k M  path metric signals to which square of the absolute value of the k M  offset estimated error signals corresponding respectively to the k M−1  survivor path metric signals has been added, and a survivor path selection circuit that inputs the k M  path metric signals, determines for each of k M−1  conditions those among the k M  path metric signals that become minimum, and output the result as k M−1  survivor path metric signals, and at the same time outputs as decision output signals a specified portion of the series of candidate signals corresponding to those among the k M  series of candidate signals for which k M−1  survivor path metric signals are minimal. 
     In addition, the Viterbi calculation circuit is characterized in comprising an estimated error offset circuit that inputs the k M  estimated error signals and the constraint condition signal, and outputs the k M  offset estimated error signals having added a specified offset value only to those among the k M  estimated error signals for which the state transitions in the trellis diagram do not satisfy the constraint condition represented by the constraint condition signal, a path metric calculation circuit that inputs the k M  offset estimated error signals and the k M−1  survivor path metric signals corresponding to each state of the trellis diagram, and outputs k M  path metric signals to which square of the absolute value of the k M  offset estimated error signals corresponding respectively to the k M−1  survivor path metric signals has been added, and a survivor path selection circuit that inputs the k M  path metric signals, determines for each of k M−1  conditions those among the k M  path metric signals that become minimum, and output the result as k M−1  of survivor path metric signals, and at the same time outputs as hypothetical output signals a specified portion of the series of candidate signals respectively corresponding to the k M−1  survivor path metric signals, and in addition, outputs as decision output signals a specified portion of the series of candidate signals corresponding to those among the k M  series of candidate signals for which k M−1  survivor path metric signals that become minimum. 
     In addition, the above-described problems are resolved by an automatic equalizer that compensates a received signal that has been distorted by intersymbol interference provides a means for detecting regularity in the code of the received signals, a means for calculating and outputting the path metric signals for each condition of the received signal, and a means that determines as the most likely states those states of the received signals that satisfy the detected regularity of the code of the received signal and have minimal path metric signals. 
     In addition, the above-described problems are resolved by an automatic equalizer that compensates a received signal that has been distorted by intersymbol interference provides a means for detecting regularity in the code of the received signals, a means for calculating and outputting the path metric singles for each condition of the received signal, a means for determining whether or not the received signal satisfies the detected regularity of the code of the received signals, and only in the case that as a result of the decision the received signal satisfies the regularity of the code, adds a specified offset value to the path metric signals, and a means that determines as the most likely states those states of the received signals that satisfy the detected regularity of the code of the received signal and have minimal path metric signals. 
     In addition, the above-described problems are resolved by an automatic equalizer that compensates a received signal that has been distorted by intersymbol interference, provides a means that generates a plurality of estimation received signals that estimate received signals by using convolutional processing, a means that generates a plurality of estimated error signals by subtracting each of the estimated received signals from the received signal, a means for detecting regularity in the code of the received signal, a means for determining whether or not the received signal satisfies the detected regularity of the code of the received signal, and only in the case that as a result of the decision the received signal satisfies the regularity of the code, adds a specified offset value to the path metric signals, a means that calculates and outputs path metric signals in each state of the received signal from the estimated error signals, and a means that determines as the most likely states those states of the received signal that have minimal path metric signals. 
     In particular, the means that detects the regularity of the code in the received signals is characterized in detecting the regularity of the code based on the received signals that have already been received. The means for detecting the regularity of the code in the received signals is characterized in detecting the regularity of the code based on the condition of the most likely received signals determined by the control means. 
     That is, in the present invention, errors in code determination are reduced by constraining the selection of survivor paths based on the regularity of the code. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the automatic equalizer according to a first embodiment of the present invention. 
     FIG. 2 is a trellis diagram in the code decision according to a first and a second embodiments the present invention. 
     FIG. 3 is a block diagram of the automatic equalizer according to a second embodiment of the present invention. 
     FIG. 4 is a block diagram of the automatic equalizer according to a third embodiment of the present invention. 
     FIG. 5 is a trellis diagram in the code decision according to a third embodiment of the present invention. 
     FIG. 6 is a block diagram of the automatic equalizer according to a fourth embodiment of the present invention. 
     FIG. 7 is a trellis diagram in the code decision according to a fourth embodiment of the present invention. 
     FIG. 8 is a block diagram of a conventional automatic equalizer. 
     FIG. 9 is a block diagram of the automatic equalizer according to an embodiment of the invention. 
     FIG. 10 is a block diagram of the automatic equalizer according to an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A first embodiment of the present invention will be explained referring to FIG.  1  and FIG.  2 . 
     FIG. 1 is a block diagram of the automatic equalizer according to a first embodiment of the present invention. FIG. 2 is a trellis diagram showing the states of the code decision. 
     In FIG. 1, reference numeral  101  is a received signal estimation circuit that inputs k M  series of candidate signals S scan  that are combinations of transmitted code having an M chip length and k levels and a transmission channel impulse response h having a length M. Additionally, the received signals are estimated by carrying out convolutional processing of the respective k M  series of input candidate signals S scan  and a transmission channel impulse response h having a length M. Next, the estimated k M  estimated received signals S er  are output to the subtracter  102 , explained below. 
     Reference  102  is a subtracter that inputs the received signal S r  and the k M  estimated received signals. Additionally, k M  estimated error signals S err  are generated by subtracting each of the k M  estimated received signals S er  from the input received signal S r . Next, the generated k M  estimated error signals S err  are output to a path metric calculation circuit  104 , described below. 
     Reference numeral  103  is a Viterbi calculation circuit that is formed by the path metric calculation circuit  104  and a survivor path selection circuit  105 , described next. 
     Reference numeral  104  is a path metric calculation circuit that inputs k M  estimated error signals S err  and k M−1  survivor path metric signals S pmsv  that correspond to each of the states of the trellis diagram. In addition, the path metric calculation circuit  104  squares the absolute value of the k M  estimated error signals S err  corresponding respectively to the k M−1  survivor path metric signals S pmsv , and generates k M  path metric signals S pm . Next, these generated k M  path metric signals S pm  are output to the survivor path selection circuit  105 , described next. 
     Reference numeral  105  is a survivor path selection circuit that inputs the k M  path metric signals S pm  and the constraint condition signal S rc , described below. Additionally, among the k M  path metric signals S pm , those for which the state transitions in the trellis diagram satisfy the constraint condition represented by the constraint condition signal S rc  and whose values for the path metric signals S pm  are minimal are determined for each of k M−1  states, and the results are output to the path metric calculation circuit  104  as the k M−1  survivor path metric signals S pmsv . In addition, among the k M  series of candidate signals S scan , a specified portion of the series of candidate signals S scan , corresponding to those among the k M−1  survivor path metric signals S pmsv  that are minimal are output as decision output signals S d . For example, the lowest bit of the series of candidate signals S scan  is output as the decision output signal S d . That is, it is determined to be the most likely received signal. 
     Reference numeral  106  is a constraint condition selection circuit that inputs the received signals S r . Additionally, it detects the regularity of the code based on the received signal S r . Next, constraint condition selection signal S rcsel  is generated in order to select the constraint condition corresponding to the regularity of the detected code. In addition, the generated constraint condition selection signal S rcsel  is output to the constraint condition generation circuit  107 , described next. 
     Reference numeral  107  is a constraint condition generating circuit that inputs the k M  series of candidate signals S scan  and the constraint condition selection signal S rcsel . In addition, the constraint condition is determined for each of the k M−1  states of the trellis diagram based on the regularity of the code corresponding to the input constraint condition selection signal S rcsel  and the k M  series of candidate signals S scan . Next, the constraint condition signal S rc  that represents the determined constraint condition is generated. In addition, the generated constraint condition signal S rc  is output to the survivor path selection circuit  105 . 
     Next, the operation of the first embodiment will be explained using specific numerical values. 
     Suppose, for example, that the transmitted code has the two levels, “0” and “1”, and that the series of candidate signals S scan  have a 2-chip length. Here, a case will be explained in which the code decision is carried out at time I. 
     As shown in FIG. 2, S scan  ( 1 ) corresponds to the candidate of the decision output signal S c  (I) at time I. In addition, S scan  ( 2 ) corresponds to the candidate of the decision output signal S d  (I+1) at time (I+1). 
     Here, the constraint condition represented by the constraint condition signal S rc  is assumed to be S scan  ( 2 )=S scan  ( 1 ). It is assumed that this condition, for example, is always generated after a known transmitted code series. Thus, the constraint condition selection circuit  106  takes the correlation between the known transmission signal series and the received signals S r . Next, the constraint condition selection circuit  106  selects the condition that S scan  ( 2 )=S scan  ( 1 ) iii the case that the correlation value is equal to or greater than a specified threshold value. 
     Furthermore, the received signal S r  is assumed to be 0.5. In addition, in FIG. 2, at path  0 , the estimated received signal S er  ( 0 )=0.3, at path  1 , the estimated received signal S er  ( 1 )=0.4, at path  2 , the estimated receive signal S er  ( 2 )=0.4, and at path  3 , the estimated received signal S er  ( 3 )=0.7. At this time, each of the estimated error signals S err  is: 
     
       
           S   err ( 0 )= S   r   −S   er ( 0 )=0.5−0.3=0.2 
       
     
     
       
           S   err ( 1 )= S   r   −S   er ( 1 )=0.5−0.4=0.1 
       
     
     
       
           S   err ( 2 )= S   r   −S   er ( 2 )=0.5−0.4=0.1 
       
     
     
       
           S   err ( 3 )= S   r   −S   er ( 3 )=0.5−0.7=−02 
       
     
     In addition, the survivor path metric signal in the case that the state is “0” at time I is S pmsv  ( 0 )=0.12, and the survivor path metric signal in the case that the state is “1” is S pmsv  ( 1 )=0.1. The path metric signals S pm  corresponding to the paths  0 ,  1 ,  2 , and  3  in this case are: 
     
       
           S   pm ( 0 )= S   pmsv ( 0 )+| S   err ( 0 )| 2 =0.12+|0.2| 2 =0.16 
       
     
     
       
           S   pm ( 1 )= S   pmsv ( 0 )+| S   err ( 1 )| 2 =0.12+|0.1| 2 =0.13 
       
     
     
       
           S   pm ( 2 )= S   pmsv ( 1 )+| S   err ( 2 )| 2 =0.1+|0.1| 2 =0.11 
       
     
     
       
           S   pm ( 3 )= S   pmsv ( 1 )+| S   err ( 3 )| 2 =0.1+|−0.2| 2 =0.14 
       
     
     The survivor path metric signals having a state “0” at tine (I+1) are selected from S pm  ( 0 ) and S pm  ( 2 ). The value (0.11) of S pm  ( 2 ) is smaller than the value (0.16) of S pm  ( 0 ). However, path  0  satisfies the constraint condition S scan  ( 2 )=S scan  ( 1 ), while path  2  does not satisfy the constraint condition S scan  ( 2 )=S scan  ( 1 ). 
     The survivor path metric signals having a state “1” at time (I+1) are selected from S pm  ( 1 ) and S pm  ( 3 ). The value (0.13) of S pm  ( 1 ) is smaller than the value (0.14) of S pm  ( 3 ). However, path  3  satisfies the constraint condition S scan  ( 2 )=S scan  ( 1 ), while path  1  does not satisfy the constraint condition S scan  ( 2 )=S scan  ( 1 ). Therefore, the survivor path metric signals S pmsv  with states “0” and “1” at time (I+1) are: 
     
       
           S   pmsv ( 0 )= S   pm ( 0 )=0.16(state “0”) 
       
     
     
       
           S   pmsv ( 1 )= S   pm ( 3 )=0.14(state “1”) 
       
     
     Second Embodiment 
     Next, a second embodiment of the present invention will be explained referring to FIG.  2  and FIG.  3 . FIG. 2 is a trellis diagram showing the states of the code decision. FIG. 3 is a block diagram of the automatic equalizer according to the second embodiment of the present invention. 
     In FIG. 3, reference numeral  101  is a received signal estimation circuit that inputs k M  series of candidate signals S scan  that are combinations of transmitted code having an M chip length and k levels and a transmission channel impulse response h having a length M. Additionally, the received signals are estimated by convolutional processing of the respective k M  series of candidate signals S scan  and the transmission channel impulse response h having a length M. Next, the estimated k M  estimated received signals S er  are output to the subtracter  102 , explained next. 
     Reference  102  is a subtracter that inputs the received signals S r  and the k estimated received signals S er . Additionally k M  estimated error signals S er  are generated by subtracting each of the k M  estimated received signals S er  from the input received signal S r . Next, the generated k M  estimated error signals S err  are output to the path metric calculation circuit  104 , described below. 
     Reference numeral  103  is a Viterbi calculation circuit that is formed by a path metric calculation circuit  104  and a survivor path selection circuit  105 , described next. 
     Reference numeral  104  is a path metric calculation circuit that inputs k M  estimated error signals S err  and k M−1  survivor path metric signals S pmsv  that correspond to each of the states of the trellis diagram. In addition, the path metric calculation circuit  104  squares the absolute value of the k M  estimated error signals S err  corresponding respectively to the k M−1  survivor path metric signals S pmsv , and generates k M  path metric signals S pm . Next, these generated k M  path metric signals S pm  are output to the survivor path selection circuit  105 , described next. 
     Reference numeral  105  is a survivor path selection circuit that inputs the k M  path metric signals S pm  and the constraint condition signal S re , described below. Additionally, among the k M  path metric signals S pm , those for which the state transitions in the trellis diagram satisfy the constraint condition represented by the constraint condition signal S rc  and whose values for the path metric signals S pm  are minimal are determined for each of k M−1  states, and the results are output to the path metric calculation circuit  104  as the k M−1  survivor path metric signals S pmsv . In addition, among the k M  series of candidate signals S scan , a specified portion of the series of candidate signals S scan , corresponding to those among the k M−1  survivor path metric signals S pmsv  that are minimal are output as decision output signals S d . For example, the lowest bit of the series of candidate signals S scan  is output as the decision output signal S d . That is, it is determined to be the most likely received signal. 
     Reference numeral  201  is a constraint condition selection circuit that inputs the decision output signal S d  output from the survivor path selection circuit  105 . Additionally, constraint condition selection signal S rcsel  is generated from the input decision output signals S d  in order to select the constraint condition corresponding to the regularity of the code. In addition, the generated constraint condition selection signal S rcsel  is output to the constraint condition generation circuit  107 , described next. 
     Reference numeral  107  is a constraint condition generating circuit that inputs the k M  series of candidate signals S scan  and the constraint condition selection signal S rcsel . In addition, the constraint condition is determined for each of the k M−1  states of the trellis diagram based on the regularity of the code corresponding to the input constraint condition selection signal S rcsel  and the k M  series of candidate signals S scan . Next, the constraint condition signal S rc  that represents the determined constraint condition is generated. In addition, the generated constraint condition signal S rc  is output to the survivor path selection circuit  105 . 
     Next, the operation of the second embodiment will be explained using specific numerical values. 
     Suppose, for example, that the transmitted code has the two levels, “0” and “1”, and that the series of candidate signals S scan  has a 2-chip length. Here, a case will be explained in which the code decision is carried out at time  1 . 
     As shown in FIG. 2, S can  ( 1 ) corresponds to the candidate of the decision output signal S d  (I) in time I. In addition, S can  ( 2 ) corresponds to the candidate of the decision output signal S d  (I+1) at time (I+1). 
     Here, the constraint condition represented by the constraint condition signal S rc  is assumed to be S scan  ( 2 )=S scan  ( 1 ). It is assumed that this condition, for example, is always generated after the known transmitted code series. Thus, the constraint condition selection circuit  201  selects the condition that S scan  ( 2 )−S scan  ( 1 ) in the case that the known transmission code series matches the decision output signal S d  up to time (I−1). Moreover, the process of deciding the survivor path metric signal S scan  at time (I−1) is the same as that in the first embodiment, and thus its explanation is omitted. 
     Third Embodiment 
     Next, a third embodiment of the present invention will be explained referring to FIG.  4  and FIG.  5 . 
     FIG. 4 is a block diagram showing the automatic equalizer according to a third embodiment of the present invention. FIG. 5 is a trellis diagram in the code decision of the third embodiment. 
     In FIG. 4, reference numeral  301  is a received signal estimation circuit that inputs k M  series of candidate signals S scan  that are combinations of transmitted code having an M chip length and k levels, k m−1  series of hypothetical output signals S td  having an N chip length, and a transmission channel impulse response h having a length (M+N). Additionally, the received signal S r  is estimated by convolutional processing of the combination of k M−1  hypothetical output signals S td  corresponding respectively to the k M  series of candidate signals S scan , and the transmission channel impulse response h having a length (M+N). Next, the estimated k M  estimated received signals S er  are output to the subtracter  102 , explained next. 
     Reference  102  is a subtracter that inputs the received signal S r  and the k M  estimated received signals S er . Additionally, k M  estimated error signals S err  are generated by subtracting each of the k M  estimated received signals S er  from the input received signal S r . Next, the generated k M  estimated error signals S err  are output to the path metric calculation circuit  303 , described below. 
     Reference numeral  302  is a Viterbi calculation circuit that is formed by the path metric calculation circuit  303 , a path metric offset circuit  304 , and a survivor path selection circuit  305 , all described below. 
     Reference numeral  303  is a path metric calculation circuit that inputs k M  estimated error signals S err  and k M−1  survivor path metric signals S pmsv  that correspond to each of the states of the trellis diagram. In addition, the path metric calculation circuit  303  squares the absolute value of the k M  estimated error signals S err  corresponding respectively to the k M−1  survivor path metric signals S pmvs  and generates k M  path metric signals S pm . Next, these generated k M  path metric signals S pm  are output to the path metric offset circuit  304 , described next. 
     Reference numeral  304  is a path metric offset circuit that inputs the k M  path metric signals S pm  and the constraint condition signal S rc . In addition, k M  offset path metric signals S opm  are generated by adding a constant offset value only to those among the k M  path metric signals S pm  for which the state transitions in the trellis diagram do not satisfy the constraint condition represented by the constraint condition signal S rc . Next, the generated k M  offset path metric signals S opm  are output to the survivor path selection circuit  305 , described next. 
     Reference numeral  305  is a survivor path selection circuit that inputs the k M  path metric signals S opm . Additionally, the KM-1 survivor path metric signals S pmsv  are generated by determining which among the am offset path metric signals S omp  are minimal. Next, the generated k M−1  survivor path metric signals S pmsv  are output to the path metric calculation circuit  303 . In addition, among the k M  series of candidate signals S scan , a specified portion of the series of candidate signals S scan , corresponding respectively to those among the k M−1  survivor path metric signals S pmsv  are output as hypothetical output signals S td . For example, for specified portion, the lowest bit of the series of candidate signals S scan  is output as the hypothetical output signal S td . In addition, among the k M  series of candidate signals S scan , a specified portion of the series of candidate signals S scan , corresponding to those among the k M−1  survivor path metric signals S pmsv  that are minimal are output as decision output signals S d . For example, for a specified portion, the lowest bit of the series of candidate signals S scan  is output as the decision output signal S td . That is, it is determined to be the most likely received signal. 
     Reference numeral  106  is a constraint condition selection circuit that inputs the received signal S r . Additionally, it detects the regularity of the code based on the received signal S r . Next, constraint condition selection signal S rcsel  is generated in order to select the constraint condition corresponding to the regularity of the detected code. In addition, the generated constraint condition selection signal S rcsel  is output to the constraint condition generation circuit  306 , described next. 
     Reference numeral  306  is a constraint condition generating circuit that inputs the k M  series of candidate signals S scan , k M−1  hypothetical output signals S td , and the constraint condition selection signal S rcsel . In addition, the constraint condition is determined for each of the k M−1  states of the trellis diagram based on the regularity of the code corresponding to the constraint condition selection signals Srcsel, k M  series of candidate signals S scan , and the k M−1  hypothetical output signals S td  . Next, the constraint condition signal S rc  that represents the determined constraint condition is generated. In addition, the generated constraint condition signal S rc  is output to the path metric offset circuit  304 . 
     Next, the operation of the third embodiment will be explained using specific numerical values. 
     For example, suppose that the transmitted code has two levels “0” and “1”, the series of candidate signals S scan  has a 2-chip length, and the hypothetical output signals S td  have a 1-chip length. Here, a case will be explained in which the code decision is carried out at time I. 
     As shown in FIG. 5, S scan  ( 1 ) corresponds to the candidate of the-decision output signal S d  (I) at time I. In addition, S scan  ( 2 ) corresponds to the candidate of the decision output signal S d  (I+1) at time (I+1). 
     Here, the constraint condition represented by the constraint condition signal S rc  is assumed to be S scan  ( 2 )=S scan  ( 1 )×S td  (I−1). 
     Furthermore, the received signal S r  is assumed to be 0.5. In addition, in FIG. 5, at path  0 , the estimated received signal S er  ( 0 )=0.3, at path  1 , the estimated received signal S er  ( 1 )=0.4, at path  2 , the estimated receive signal S er  ( 2 )=0.4, and at path  3 . the estimated received signal S er  ( 3 )=0.7. At this time, each of the estimated error signals S err  is: 
     
       
           S   err ( 0 )= S   r   −S   er ( 0 )=0.5−0.3=0.2 
       
     
     
       
           S   err ( 1 )= S   r   −S   er ( 1 )=0.5−0.4=0.1 
       
     
     
       
           S   err ( 2 )= S   r   −S   er ( 2 )=0.5−0.4=0.1 
       
     
     
       
           S   err ( 3 )= S   r   −S   er ( 3 )=0.5−0.7=−0.2 
       
     
     In addition, the survivor path metric signal in the case that the state is “0” at time I is S pmsv  ( 0 )=0.12, and the survivor path metric signal in the case that the state is “1” is S pmsv  ( 1 )=0.1. The path metric signals S pm  corresponding to the paths  0 ,  1 ,  2 , and  3  in this case are: 
     
       
           S   pm ( 0 )=S pmsv ( 0 )+| S   err ( 0 )| 2 =0.12+|0.2| 2 =0.16 
       
     
     
       
           S   pm ( 1 )=S pmsv ( 0 )+| S   err ( 1 )| 2 =0.12+|0.1| 2 =0.13 
       
     
     
       
           S   pm ( 2 )=S pmsv ( 0 )+| S   err ( 2 )| 2 =0.1+|0.1| 2 =0.11 
       
     
     
       
           S   pm ( 3 )=S pmsv ( 0 )+| S   err ( 3 )| 2 =0.1+|−0.2| 2 =0.14 
       
     
     Here, path  0  and path  3  satisfy the constraint condition S scan  ( 2 )=S scan  ( 1 )×S td  (I−1), while path  1  and path  2  do not satisfy S scan  ( 2 )=S scan  ( 1 )×S td  (I−1). Therefore, the offset path metric signal S pm  corresponding to path  1  and path  2  adds a constant offset value to the path metric signals Spm having a constant offset value added thereto. For example, assuming an offset value of 0.5, the offset path metric signals S opm  corresponding to paths  0 ,  1 ,  2 , and  3  are: 
     
       
           S   opm ( 0 )= S   pm ( 0 )=0.16 
       
     
     
       
           S   opm ( 1 )= S   pm ( 1 )+0.5=0.13+0.5=0.63 
       
     
     
       
           S   opm ( 2 )= S   pm ( 2 )=0.11+0.5=0.61 
       
     
     
       
           S   opm ( 3 )= S   pm ( 3 )=0.14 
       
     
     For the smaller survivor path metric signals in state “0” at time (I+1), the smaller of S opm  ( 0 ) and S opm  ( 2 ), is selected. In addition, for survivor path metric signals instate “1” at time (I+0), the smaller of S opm  ( 1 ) and S opm  ( 3 ) is selected. Thus, the survivor path metric signals S pmsv  in states “0” and “1” at time (I+1) are: 
     
       
           S   pmv ( 0 )= S   opm ( 0 )=0.16 
       
     
     
       
           S   pmv ( 1 )= S   opm ( 3 )=0.14 
       
     
     Fourth Embodiment 
     Next, a fourth embodiment of the present invention will be explained referring to FIG.  6  and FIG.  7 . 
     FIG. 6 is a block diagram showing the automatic equalizer according to a fourth embodiment of the present invention. FIG. 7 is a trellis diagram in the code decision of the third embodiment. 
     In FIG. 6, reference numeral  401  is a received signal estimation circuit that inputs k M  series of candidate signals S scan  that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels, a decision output signal S d  having an N chip length (where N is a natural number) output from the survivor path selection circuit  405 , described below, and a transmission channel impulse response h having a length (M+N). Additionally, the received signals are estimated by carrying out convolutional processing on the combination of decision output signals S d  corresponding respectively to the k M  series of candidate signals S scan  and a transmission channel impulse response h having a length (M+N). Next, the estimated k M  estimated received signals S er  are output to the subtracter  102 , explained next. 
     Reference  102  is a subtracter that inputs the received signals S r  and the k M  estimated received signals S er . Additionally, k M  estimated error signals S err  are generated by subtracting each of the k M  estimated received signals S er  from the input received signals S r . Next, the generated k M  estimated error signals S err  are output to the estimated error offset circuit  403 , described below. 
     Reference numeral  402  is a Viterbi calculation circuit that is formed by the estimated error offset circuit  403 , a path metric offset circuit  404 , and a survivor path selection circuit  405 , all described below. 
     Reference numeral  403  is an estimated error offset circuit that inputs the k M  estimated error signals S err  and the constraint condition signal S rc . In addition, the k M  offset estimated error signals S oerr  are generated by adding a constant offset value only to those among the k M  estimated error signals S er  for which the state transitions in the estimated error diagram do not satisfy the constraint condition represented by the constraint condition signal S rc . Next, the generated k M  offset estimated error signals S oerr  are output to a path metric calculation circuit  404 , described next. 
     Reference numeral  404  is a path metric calculation circuit that inputs k M  offset estimated error signals S oerr  and k M−1  survivor path metric signals S pmsv  that correspond to each of the states of the estimated error diagram. In addition, the path metric calculation circuit  404  squares the absolute value of the k M  offset estimated error signals S oerr  corresponding respectively to the k M−1  survivor path metric signals S pmsv , and generates k M  path metric signals S pm . Next, these generated k M  path metric signals S pm  are output to the survivor path selection circuit  405 , described next. 
     Reference numeral  405  is a survivor path selection circuit that inputs the k M  path metric signals S opm . In addition, k M−1  survivor path metric signals S pmsv  are generated by determining for each of the k M−1  states those among the k M  path metric signals S pm  that are minimal. Next, the generated k M−1  survivor path metric signals S pmsv  are output to the path metric calculation circuit  404 . In addition, among the k M  series of candidate signals S scan , a specified portion of the series of candidate signals S scan  that correspond to those among the k M−1  series of candidate signals S pmsv  that are minimal are output as decision output signals S d . The specified portion, for example, is the lowest bit of the series of candidate signals S scan  output as a hypothetical output signals S td  . That is, the most likely received signals are determined. 
     Reference numeral  106  is a constraint condition selection circuit that inputs the received signals S r . Additionally, it detects the regularity of the code based on the received signals S r . Next, constraint condition selection signals S rcsel  are generated in order to select the constraint condition corresponding to the regularity of the detected code. In addition, the generated constraint condition selection signal S rcsel  is output to the constraint condition generation circuit  406 , described next. 
     Reference numeral  406  is a constraint condition generating circuit that inputs the k M  series of candidate signals S scan , decision output signals S d , and the constraint condition selection signal S rcsel . In addition, the constraint condition is determined for each of the k M−1  states of the estimated error diagram based on the regularity of the code corresponding to the constraint condition selection signal S rcsel , the k M  series of candidate signals S scan , and the decision output signals S d . Next, the constraint condition signal S rc  that represents these determined constraint condition is generated. In addition, the generated constraint condition signal S rc  is output to the estimated error offset circuit  403 . 
     Next, the operation of the fourth embodiment will be explained using specific numerical values. 
     Suppose, for example, that the transmitted code has two levels, “0” and “1”, the series of candidate signals S scan  have a 2-chip length, and the decision output signals S d  used in the received signal estimation have a 1-chip length. Here, a case will be explained in which the code decision is carried out at time I. 
     As shown in FIG. 7, S scan  ( 1 ) corresponds to the candidate of the decision output signal S d  (I) at time I. In addition, S scan  ( 2 ) corresponds to the candidate decision output signal S d  (I+1) at time (I+1). 
     Here, the constraint condition represented by the constraint condition signal S rc  is assumed to be S scan  ( 2 )=S scan  ( 1 ) 33  S td  (I−1).