Abstract:
Systems and methods for slow tail compensation are provided. A photodetector signal is pre-amplified to thereby produce an uncompensated photodetector signal that includes a fast component and a slow component. The fast component is removed from the uncompensated photodetector signal to thereby produce a compensating signal that includes the slow component of the uncompensated photodetector signal. The compensating signal is subtracted from the uncompensated photodetector signal to thereby produce a compensated photodetector signal that includes the fast component but not the slow component.

Description:
PRIORITY CLAIM  
       [0001]     The present application is a continuation of U.S. patent application Ser. No. 11/322,313, entitled “Slow Tail Compensation,” filed Dec. 30, 2005 (now allowed), which claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 60/733,047, filed Nov. 3, 2005. Each of the above applications is incorporated by reference herein. 
     
    
     FIELD OF THE INVENTION  
       [0002]     Embodiments of the present invention relate generally to systems (e.g., circuits) and methods that perform slow tail compensation. Specific embodiments of the present invention provide an effective solution to compensate for slow diffusive carriers generated in a conventional CMOS photodetector.  
       BACKGROUND  
       [0003]     For various reasons, there has recently been increased interest in fast photodetectors produced using complementary-metal-oxide semiconductor (CMOS) technology. First, CMOS circuitry is generally less expensive than other technologies, such as Gallium Arsenide or bipolar silicon technologies. Further, CMOS circuitry generally dissipates less power than other technologies. Additionally, CMOS photodetectors can be formed on the same substrate as other low power CMOS devices, such as metal-oxide semiconductor field effect transistors (MOSFETs).  
         [0004]     However, despite the potential advantages, there are various reasons why conventional CMOS technology has not been optimal for producing a fast photodetector. More specifically, photodetectors produced using CMOS technology have proven to be much slower than photodetectors produced using other technologies, such as bipolar silicon technology. The slower the photodetector, the lower the bandwidth of information that can be detected using the photodetector.  
         [0005]     In a CMOS photodetector, photo-generated electron-hole pairs in the depletion region are collected quickly through carrier drift process due to the presence of strong electric field. On the other hand, carriers generated in the neutral zone of the substrate migrate by diffusion. The diffusion-based component has a much slower time-response than the field-aided drift counterpart.  FIG. 1  illustrates the typical transient behavior of the photocurrent for carrier drift and diffusion. Accordingly, the output signal of the photodetector can be characterized by a fast time-constant τ fast  and a slow time-constant τ slow  representing carrier drift and diffusion respectively. In addition, A fast  and A slow  are the percentage contributions from carrier drift and carrier diffusion respectively. The summation of A fast  and A slow  is equal to 1.  
         [0006]     To achieve high-speed operations, A slow  should be kept to a minimum, normally less than 1% of the total amplitude. Otherwise, the transient response of photocurrent exhibits the so-called slow tail phenomena.  
         [0007]     Several schemes have been suggested to minimize the slow tail effect in silicon technologies. In one scheme, a buried collector layer is used to screen out the slow diffusive carriers in bipolar or BiCMOS technologies. However, this topology results in responsivity that is typically low. It presents the most common tradeoff, that of responsivity for speed. In another scheme, a very thick and lowly-doped substrate is used with a large reverse bias voltage in nonstandard CMOS technology. However, this topology requires extra custom processing steps. In pure CMOS technology, a spatially modulated detector is the only scheme reported so far to achieve slow tail compensation. However, this approach suffers from a low responsivity since a substantial detector area is blocked to generate the slow diffusive component. Accordingly, there is still a need to provide an effective solution to compensate for slow diffusive carriers generated in a conventional CMOS photodetector.  
       SUMMARY  
       [0008]     Embodiments of the present invention generally relate to systems (e.g., circuits) and methods that perform slow tail compensation. While especially useful with CMOS photodetectors, embodiments of the present invention are not limited to such uses.  
         [0009]     In accordance with an embodiment, a slow tail compensation system includes a preamplifier stage, a slow tail compensator stage and a summing stage. The preamplifier stage amplifies a photodetector signal to thereby produce an uncompensated photodetector signal that includes a fast component and a slow component. The slow tail compensator stage removes the fast component from the uncompensated photodetector signal to thereby produce a compensating signal that includes the slow component of the uncompensated photodetector signal. The summing stage subtracts the compensating signal from the uncompensated photodetector signal to thereby produce a compensated photodetector signal that includes the fast component but not the slow component.  
         [0010]     In accordance with an embodiment of the present invention, the slow tail compensator stage includes a low pass filter and an attenuator. The low pass filter allows the slow component of the uncompensated photodetector signal to pass without allowing the fast component of the uncompensated photodetector signal to pass. The attenuator causes the compensating signal, which is subtracted at the summing stage from the uncompensated photodetector signal, to have an amplitude corresponding to the slow component.  
         [0011]     The uncompensated photodetector signal can be characterized by a fast time-constant (τ fast ), a slow time-constant (τ slow ), a fast amplitude contribution (A fast ) and a slow amplitude contribution (A slow ). In accordance with an embodiment of the present invention, a ratio of the attenuator is set be substantially equal to the slow amplitude contribution (A slow ).  
         [0012]     In accordance with an embodiment of the present invention the low-pass filter is implemented using a simple filter including a resistor R LPF  and a capacitor C LPF , at least one of which is adjustable. In such an arrangement, the low pass-filter has a time-constant of R LPF *C LPF . In accordance with an embodiment, C LPF  (and/or R LFP ) is set such that the product of R LPF *C LPF  is equal to the slow time-constant τ slow . More generally, the time constant of the low-pass filter is set to equal the slow time-constant τ slow .  
         [0013]     In accordance with an embodiment of the present invention, a first register is used to store a value of the slow time-constant (τ slow ) and a second register is used to store a value of the slow amplitude contribution (A slow ). In such an arrangement, the overall characteristics of the slow tail compensation block can be adjusted, e.g., using a serial controller.  
         [0014]     Preamplification and slow tail compensation can be performed in the current domain, the voltage domain, or combinations thereof. For example, the preamplifier stage can include a transimpedance amplifier that converts the current output of a photodetector to the voltage domain. The slow tail compensation can then be performed in the voltage domain. Alternatively, the output of the transimpedance amplifier can be converted to a current, e.g., using a voltage to current (V2I) converter. This will enable the slow tail compensation to be performed in the current domain. In still another embodiment, a current-mode preamplifier is used in place of the transimpedance amplifier.  
         [0015]     Further and alternative embodiments, and the features, aspects, and advantages of the present invention will become more apparent from the detailed description set forth below, the drawings and the claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]      FIG. 1  is a graph of photocurrent versus time, which shows the transient behavior of a photocurrent due to carrier drift and diffusion.  
         [0017]      FIG. 2  is a high level block diagram useful for explaining how slow tail compensation can be performed in accordance with embodiments of the present invention.  
         [0018]      FIG. 3  is a high level block diagram that illustrates how a transimpedance amplifier can be used to implement the preamplifier stage of  FIG. 2 , in accordance with an embodiment of the present invention.  
         [0019]      FIG. 4  is a high level block diagram that illustrates how a current mode preamplifier can be used to implement the preamplifier stage of  FIG. 2 , in accordance with an embodiment of the present invention.  
         [0020]      FIG. 5  is a high level block diagram that illustrates how a transimpedance amplifier and a voltage-to-current (V2I) converter can be used so that preamplification is performed in the voltage domain, while slow tail compensation is performed in the current domain, in accordance with an embodiment of the present invention.  
         [0021]      FIG. 6  illustrates a circuit implementation of the embodiment of  FIG. 3 , according to an embodiment of the present invention.  
         [0022]      FIG. 7  illustrates a circuit implementation of the embodiment of  FIG. 4 , according to an embodiment of the present invention.  
         [0023]      FIG. 8  illustrates a circuit implementation of the embodiment of  FIG. 5 , according to an embodiment of the present invention.  
         [0024]      FIG. 9  illustrates how the slow time-constant τ slow  and the slow amplitude contribution A slow  can be adjusted using a pair of registers and a serial controller, in accordance with an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0025]      FIG. 2  illustrates the basic concept of the proposed slow tail compensation, according to an embodiment of the present invention. When an optical signal  200  is incident on a photodetector  202 , the photodetector  202  converts the incident optical signal  200  into electrical current signal  204  (also referred to as a photodetector signal  204 ). This photodetector signal  204  is provided to a preamplifier stage  206 . The preamplifier  206 , depending on implementation, can amplify the photodetector signal  204  in the current or voltage domain, and may output either a current or voltage signal, which is referred to hereafter as an uncompensated photodetector signal  208 . This uncompensated photodetector signal  208  goes directly to a summing stage  218 , and also goes to a slow tail compensation block  209 , which in accordance with an embodiment of the present invention, is formed by a low-pass filter  210  and an attenuator  214 .  
         [0026]     The slow tail compensation is performed by two steps. The first step is to set (e.g., adjust) the time-constant of the low-pass filter  210  to be the same as τ slow . This will cause the low-pass filter  210  to filter out the fast component, leaving only the slow component with the time-constant of τ slow . The second step is to set (e.g., adjust) the ratio of the attenuator  214  to be the same as A slow . This will cause the compensating signal  216  at the output of the attenuator  214  to include only the slow component with the amplitude of A slow . The summing stage  218  subtracts this compensating signal  216  from the uncompensated photodetector signal  208 , with the resulting output signal  220  (also referred to as the compensated photodetector signal) including the fast component with the amplitude of A fast , but not the slow component, and thus being properly compensated. It is noted that the order of low-pass filter  210  and the attenuator  214  can be exchanged (i.e., the attenuator  214  can be located before the low-pass filter  210 , or be combined with the low-pass filter) without affecting the overall slow tail compensation function.  
         [0027]     Dependent upon the configurations of the preamplifier  206 , the proposed slow tail compensation scheme can be implemented in either the voltage or current domain, as shown in  FIGS. 3 and 4 , respectively. In the embodiment of  FIG. 3 , a transimpedance amplifier, which includes an operational amplifier  306  (labeled TIA) and a feedback resistor RF, is used to implement the preamplifier  206 . In such an embodiment, the transimpedance amplifier converts the photocurrent signal  204  to a voltage, thus resulting in the uncompensated photodetector signal  208  being a voltage signal. It is noted that a transimpedance amplifier is also known as a current-to-voltage (I2V) converter, because of the function it performs.  
         [0028]     In another embodiment, shown in  FIG. 4 , the preamplifier  206  is a current-mode preamplifier, thus resulting in the uncompensated photodetector signal  208  being a current signal. Such pure current-mode preamplifiers are sometimes adopted for their superior signal handling capability.  
         [0029]     In another embodiment, shown in  FIG. 5 , a combination of a transimpedance amplifier and a voltage-to-current (V2I) converter  506  is used as the preamplifier  206 . More specifically, in the embodiment of  FIG. 5 , amplification is performed in the voltage domain using a transimpedance amplifier including the operational amplifier  306  (labeled TIA) and the feedback resistor RF. The voltage-to-current (V2I) converter  506  converts the voltage output of the transimpedance amplifier to a current, thereby enabling the slow tail compensation to be performed in the current domain. Such embodiment takes advantage of the lower input noise provided by the transimpedance amplifier, and the flexibility offered by the current-mode signal processing.  
         [0030]      FIG. 6  illustrates a circuit, according to an embodiment of the present invention, that performs slow tail compensation in the voltage domain. Accordingly,  FIG. 6  illustrates an exemplary implementation of the voltage domain embodiment of  FIG. 3 . The resistor RLPF and the capacitor CLPF form the low-pass filter (LPF)  210 , with a time-constant of RLPF*CLPF. Preferably, CLPF (and/or RLPF) is adjusted such that the product of RLPF*CLPF is equal to τ slow . Resistors R 2  and R 3  form the attenuator  214 , with the attenuation set by the ratio R 2 /R 3 . Preferably, the resistor R 3  (and/or the resistor R 2 ) is adjusted such that the ratio of R 2 /R 3  is equal to A slow . In this case the attenuator  214  is part of the summing stage  218 , as illustrated in  FIG. 6 , with the summing stage including resistors R 1 , R 2  and R 3  along with an amplifier  618  (labeled A 1 ). An inverting stage  616  (labeled −1) is inserted between the low-pass filter  210  and the resistor R 3 , so that the summing stage  218  performs the required subtracting function. One of ordinary skill in the art would appreciate, from the description herein, that alternative circuits are also within the scope of the present invention.  
         [0031]      FIG. 7  illustrates a circuit, according to an embodiment of the present invention, that performs slow tail compensation in the current domain. Accordingly,  FIG. 7  illustrates an exemplary implementation of the embodiment of  FIG. 4  where pre-amplification and slow tail compensation are both performed in the current domain. In  FIG. 7 , the low-pass filter (LPF)  210  is provided by the resistor RLPF and the capacitor CLPF, which function in a similar manner as described above with reference to  FIG. 6 . However, in this embodiment, the attenuator  214  is provided by the current mirror formed by transistors MN 1  and MN 2 , with the aspect ratio of the transistors specifying the amount of attenuation. Preferably, the ratio MN 2 /MN 1  is equal to A slow . As would be understood by one of ordinary skill in the art, transistors MN 1  and/or MN 2  could be replaced by a more complicated current mirror DAC to provide for finer resolution. One of ordinary skill in the art would appreciate, from the description herein, that alternative circuits are also within the scope of the present invention.  
         [0032]      FIG. 8  illustrates a circuit, according to an embodiment of the present invention, that uses a combination of a transimpedance amplifier and a voltage-to-current (V2I) converter. Accordingly,  FIG. 8  illustrates an exemplary implementation of the embodiment of  FIG. 5  where pre-amplification is performed in the voltage domain, and slow tail compensation is performed in the current domain. In  FIG.8 , the low-pass filter  210  is provided by the resistor RLPF and the capacitor CLPF, as was the case in  FIGS. 6 and 7  described above. The attenuator  214  is provided by the current mirror formed by transistors MN 1  and MN 2 , as was the case in  FIG. 7  described above. One of ordinary skill in the art would appreciate, from the description herein, that alternative circuits are also within the scope of the present invention.  
         [0033]     In accordance with specific embodiments of the present invention, the proposed slow tail compensation is suitable for programmable trimming via a controller, e.g., a serial control.  FIG. 9  demonstrates such an implementation. In this embodiment, a register  902  stores a value for τ slow  and a register  904  stores a value for A slow . In this arrangement, values of τ slow  and A slow  can be adjusted through a serial controller  906 , and easily stored in the registers  902  and  904 . For example, assume each register is an 8-bit register, this would allow up to 256 values for of τ slow  and 256 values for A slow  to be selectable. Other types of controllers, besides a serial controller, can also be used. In another embodiment a register bank  902  stores multiple values for τ slow  and a register bank  904  stores multiple values for A slow , and the serial controller, or some other type of controller, selects one of the values stored in registers  902  for τ slow  and one of the values stored in registers  904  for A slow .  
         [0034]     Where an adjustable capacitor CLFP is used within the low-pass filter  210 , the adjustable capacitor can be implemented, e.g., using a bank of parallel selectable capacitors, each of which has a respective switch (e.g., a switching transistor). Each capacitor can have the same capacitance, or more likely, each capacitor is differently weighted to provide for a wider range of possible capacitances. The capacitors can be weighted in a progressive fashion (e.g., C, 2C, 3C, 4C . . . ), a binary fashion (e.g., C, 2C, 4C, 8C . . . ), or in any other arrangement.  
         [0035]     Where an adjustable resistor RLFP is used within the low-pass filter  210 , the adjustable resistor can be similarly implemented, e.g., using a bank of parallel selectable resistors, each of which has a respective switch (e.g., a switching transistor). Each resistor can have the same resistance, or more likely, each resistor is differently weighted to provide for a wider range of possible resistances. A similar arrangement can be used if an adjustable resistor is used within the attenuator  214 , e.g., as shown in  FIG. 6 . It is also possible to implement an adjustable resistor using a bank of parallel transistors (e.g., CMOS transistors) arranged such that their gate or base currents can be adjusted to achieve a desired resistance.  
         [0036]     Where the attenuator  214  is implemented using a current mirror, the adjustable transistor (e.g., MN 1  in  FIGS. 7 and 8 ) of the current mirror can be implemented, e.g., using a bank of parallel selectable transistors. Preferably, the transistor bank can include transistors of different sizes that can be used to achieve a broad range of values for A slow .  
         [0037]     The present invention has been described above with the aid of functional building blocks illustrating the performance of specified functions and relationships thereof. The boundaries of these functional building blocks have often been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the invention. For example, the voltage-to-current (V2I) converter  506  in  FIGS. 5 and 8  can be considered to be inside or outside the preamplifier stage  206 .  
         [0038]     The forgoing description is of the preferred embodiments of the present invention. These embodiments have been provided for the purposes of illustration and description, but are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to a practitioner skilled in the art. Embodiments were chosen and described in order to best describe the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention. It is intended that the scope of the invention be defined by the following claims and their equivalents.