Abstract:
A charge pump circuit used for a charge pump phase-locked loop that includes a charging and discharging unit, two complementary circuit units, two operational amplifier units, an inverter unit, and a current mirror unit. The charge pump circuit resolves the matching problem of charging and discharging currents and the charge sharing problem in existing charge pump circuits. Both complementary circuit units positively and reversely compensate the charging and discharging unit to keep the charging and discharging currents of capacitors constant. Thus, the problem of the change of charging and discharging currents is resolved, the voltage linear variation of the charge pump capacitors is achieved, and the charging and discharging of the capacitors can be accurately controlled. The charge pump circuit is simple in structure, easy to integrate, high in the matching precision of the charging and discharging current sources, and suitable for low voltage and low power consumption applications.

Description:
[0001]    This application claims priority to Chinese patent application No.  201210534844 . 5  titled “CHARGE PUMP CIRCUIT FOR CHARGE PUMP PHASE-LOCKED LOOP” and filed with the Chinese State Intellectual Property Office on Dec. 12, 2012, which is incorporated herein by reference in its entirety. 
       FIELD 
       [0002]    The present disclosure relates to the technical field of electronics, relates to an integrated circuit design technique, and in particular relates to a charge pump circuit for a charge pump phase-locked loop. 
       BACKGROUND 
       [0003]    A Phase Locked Loop (PPL) is an important module in an analog integrated circuit and a hybrid digital-analog integrated circuit, and is applied widely in fields such as wireless communication, frequency synthesis and clock recovery. A charge pump phase-locked loop (CPPLL) among various phase locked loops is widely applied to chip designs due to its high stability, wide capture range, and a digitized phase frequency discriminator. 
         [0004]    The phase-locked loop is a feedback system in which a phase of an input signal is compared with a phase of an output signal. 
         [0005]      FIG. 1  shows a structural diagram of a typical charge pump phase-locked loop system, which includes modules such as a phase frequency discriminator (PFD)  100 , a charge pump (CP)  200 , a loop filter (LF)  300 , a voltage-controlled oscillator (VCO)  400  and a Multi-Modulus Divider (MMD)  500 . 
         [0006]    The CP  200  plays an important part in the system in that: the CP  200  converts a digital control signal output from the PFD  100 , including a charging control signal UP and a discharging control signal DOWN, into an analog signal, and then controls an output frequency of the VCO  400  to realize a phase-locked function. 
         [0007]    Here, the analog signal is required to have a small ripple and a good linearity degree. Thus, the CP  200  is required to meet two conditions that: a charging current and a discharging current are the same and are maintained constant within a certain range. In practice, the CP  200  has a serious current mismatch since due to limitations caused by undesired factors such as a channel modulation effect of MOS, a charge sharing and a charge injection, which is a main factor affecting the performance of the loop. 
         [0008]    As shown in  FIG. 2 , a first existing charge pump circuit includes PMOS current mirrors MP 1  and MP 2 , NMOS current mirrors MN 2  and MN 4 , a PMOS switch transistor MP 4 , an NMOS switch transistor MN 3 , a bias circuit NMOS switch transistor MN 5 , output control signals from a phase frequency discriminator, UP and DOWN, and a charge pump capacitor C cp . The main circuit may include a first branch circuit  11  and a second branch circuit  12 . 
         [0009]    The bias circuit provides a bias voltage and a bias current to a post-stage circuit. I 1  is a current flowing through the PMOS transistor MP 2  in the first branch circuit  11 . I 2  is a current flowing through the NMOS transistor MN 1  of the first branch circuit  11 . I 1 /I 2  mirrors a reference current I ref  in a certain proportion. MP 4  is switched on or switched off by the output control signal UP from the phase frequency discriminator, while MN 3  is switched on or switched off by the output control signal DOWN from the phase frequency discriminator. In a case that the signals UP and DOWN are low levels, MP 4  is switched on while MN 3  is switched off, I ch  is a current flowing through the PMOS transistor MP 4  in the second branch circuit  22 , I dis  is a current flowing through the NMOS transistor MN 3  in the second branch circuit  22 , and I dis  mirrors I 1  to charge the capacitor C cp . In a case that the signals UP and DOWN are high levels, MP 4  is switched off while MN 3  is switched on, and I dis  mirrors I 2  to discharge the capacitor C cp . In a case that MP 4  and MN 3  each are switched off, the capacitor is not charged or discharged, and V cp  is maintained constant. 
         [0010]    The above circuit has an issue of current mismatch in a current mirror and an issue of charge sharing. For the issue of current mismatch in a current mirror, due to channel modulation effect, a V ds  of the transistor MP 3  in the PMOS current mirror does not equal to a drain-source voltage V ds  of the transistor MN 4  in the NMOS current mirror. For example, if V cp  (a potential at a node Y shown in  FIG. 2 ) is high, voltages of drain electrodes of MP 4  and MN 3  are high and I ch &lt;I dis . In this case, during a pulsed reset, MP 4  and MN 3  each will be switched on, which leads to a charge release of the capacitor C cp , then V cp  is decreased correspondingly but not be maintained constant, which may affect a subordinate circuit. For the issue of charge sharing, the transistor MP 3  of the PMOS current mirror and the transistor MN 4  of the NMOS current mirror are respectively close to the power supply and the ground, the drain electrodes has certain capacitances. In this case, if the switch transistors MP 4  and MP 3  each are switched off, then the transistor MP 3  charges the node Y to VDC and MN 4  discharges a node X to zero potential. At a next phase comparison instant, if the switch transistors MP 4  and MP 3  each are switched on, the potential at the node X is increased while the potential at the node Y is decreased. If voltage drops on the switch transistors MP 4  and MP 3  are omitted, V X =V Y =V Ccp . In this case, a variation of V X  may not always equal to a variation of V Y  even if C X =C Y , and the difference between V X  and V Y  is provided by C cp , thus a jitter occurs on a voltage applied on C cp . 
         [0011]    It can be seen clearly from  FIG. 3  that, I ch  is not equal to I dis . Narrow reset pulses are introduced in the output signals UP and DOWN from the phase frequency discriminator due to a delay of an internal loop of the phase frequency discriminator. When eliminating a dead zone, the reset pulse may switch on both the PMOS switch transistor and the NMOS switch transistor. In this case, if the charging current is not equal to the discharging current, a net current flowing through the charge pump capacitor C cp  is not zero. Hence, the potential at C cp  changes fixedly in each period, and a phase error may be generated between an input and an output of the phase-locked loop to keep the phase-locked loop locking. 
         [0012]    As shown in  FIG. 4 , a second existing charge pump circuit includes PMOS current mirrors MP 2  and MP 4 , NMOS current mirrors MN 3  and MN 5 , a PMOS switch transistor MP 3 , an NMOS switch transistor MN 5 , bias circuits MN 1  and MN 2 , output control signals UP and DOWN from a phase frequency discriminator and a charge pump capacitor C cp . The subject circuit may include a third branch circuit  33  and a fourth branch circuit  44 . The circuit may be considered as an improvement of the first charge pump circuit in that: firstly, an operational transconductance amplifier is added, and with a feedback effect, potentials at a node X and a node Y are equal to each other, hence a charging current equals to a discharging current; and secondly, locations of switch transistors are exchanged with locations of current mirrors to address the issue of charge sharing. However, it can be seen from  FIG. 5  that, I ch  and I dis  may change as the output voltage changes even if I ch =I dis  in the charge pump circuit; therefore, the charging current and the discharging current are non-constant. 
       SUMMARY 
       [0013]    A charge pump circuit for a charge pump phase-locked loop is provided according to the present disclosure to address the above issue of non-constant charging and discharging currents in the above charge pump circuit. 
         [0014]    A charge pump circuit for a charge pump phase-locked loop is provided according to an embodiment of the present disclosure, which includes: a charging and discharging unit, a first complementary circuit unit, a first operational amplifier unit (A 1 ), a phase inverter unit, a second complementary circuit unit, a current mirror unit and a second operational amplifier unit (A 2 ), where
   an output terminal of the charging and discharging unit is connected to a negative input terminal of the first operational amplifier unit (A 1 );   an output terminal of the first complementary circuit unit is connected to a positive input terminal of the first operational amplifier unit (A 1 ), and an output terminal of the first operational amplifier unit (A 1 ) is connected to a first input terminal of the charging and discharging unit and a first input terminal of the first complementary circuit unit;   an input terminal of the phase inverter unit is connected to an output terminal of the first complementary circuit unit, and an output terminal of the phase inverter unit is connected to a negative input terminal of the second operational amplifier unit (A 2 );   an output terminal of the second complementary circuit unit is connected to a positive input terminal of the second operational amplifier unit (A 2 ), and an output terminal of the second operational amplifier unit is connected to an input terminal of the current mirror unit and an input terminal of the second complementary circuit unit; and   an output terminal of the current mirror unit is connected to a second input terminal of the charging and discharging unit and a second input terminal of the first complementary circuit unit.   
 
         [0020]    Preferably, the charging and discharging unit includes a PMOS transistor M 0 , a PMOS transistor M 2 , an NMOS transistor M 4  and an NMOS transistor M 6 , where
   a source electrode of the PMOS transistor M 0  is connected to a voltage source VDC, a drain electrode of the PMOS transistor M 0  is connected to a source electrode of the PMOS transistor M 2 , and a drain electrode of the PMOS transistor M 2  is connected to a drain electrode of the NMOS transistor M 4  and the connection point serves as the output terminal of the charging and discharging unit;   the output terminal of the charging and discharging unit is connected to the negative input terminal of the first operational amplifier unit (A 1 ), a source electrode of the NMOS transistor M 4  is connected to a drain electrode of the NMOS transistor M 6 , a source electrode of the NMOS transistor M 6  is connected to the ground GND, and a gate electrode of the PMOS transistor M 2  serves as the first input terminal of the charging and discharging unit; and   the first input terminal of the charging and discharging unit is connected to the output terminal of the first operational amplifier unit (A 1 ), a gate electrode of the NMOS transistor M 4  serving as the second input terminal of the charging and discharging unit is connected to the output terminal of the current mirror unit, and a gate electrode of the PMOS transistor M 0  and a gate electrode of the NMOS transistor M 6  are respectively connected to an output signal UP and an output signal DOWN which are output from a phase frequency discriminator.   
 
         [0024]    Preferably, the first complementary circuit unit includes a PMOS transistor M 1 , a PMOS transistor M 3 , an NMOS transistor M 5  and an NMOS transistor M 7 , where
   a source electrode of the PMOS transistor M 1  is connected to a voltage source VDC, a drain electrode of the PMOS transistor M 1  is connected to a source electrode of the PMOS transistor M 3 , and a drain electrode of the PMOS transistor M 3  is connected to a drain electrode of the NMOS transistor M 5  and the connection point serves as the output terminal of the first complementary circuit unit;   the output terminal of the first complementary circuit unit is connected to the positive input terminal of the first operational amplifier unit (A 1 ), a source electrode of the NMOS transistor M 5  is connected to a drain electrode of the NMOS transistor M 7 , a source electrode of the NMOS transistor M 7  is connected to the ground GND and a gate electrode of the PMOS transistor M 3  serves as the first input terminal of the first complementary circuit unit;   the first input terminal of the first complementary circuit unit is connected to the output terminal of the first operational amplifier unit (A 1 ), and a gate electrode of the NMOS transistor M 5  serves as the second input terminal of the first complementary circuit unit; and   the second input terminal of the first complementary circuit unit is connected to the output terminal of the current mirror unit, a gate electrode of the PMOS transistor M 1  is connected to the ground GND, and a gate electrode of the NMOS transistor M 7  is connected to the voltage source VDC.   
 
         [0029]    Preferably, the phase inverter unit includes a PMOS transistor M 8  and an NMOS transistor M 9 , where
   a diode connection mode of gate-drain short circuit is adopted in the PMOS transistor M 8 , a source electrode of the PMOS transistor M 8  is connected to a voltage source VDC, a drain electrode of the PMOS transistor M 8  is connected to a drain electrode of the NMOS transistor M 9  and the connection point serves as the output terminal of the phase inverter unit; and   the output terminal of the phase inverter unit is connected to the negative input terminal of the second operational amplifier unit (A 2 ), a gate electrode of the NMOS transistor M 9  serves as the input terminal of the phase inverter unit, the input terminal of the phase inverter unit is connected to the output terminal of the first complementary circuit unit and a source electrode the NMOS transistor M 9  is connected to the ground GND.   
 
         [0032]    Preferably, the current mirror unit includes a PMOS transistor M 10 , a PMOS transistor M 12 , a PMOS transistor M 14 , an NMOS transistor M 15  and an NMOS transistor M 17 , where
   a source electrode of the PMOS transistor M 10  is connected to a voltage source VDC, a drain electrode of the PMOS transistor M 10  is connected to a source electrode of the PMOS transistor M 12 , and a gate electrode of the PMOS transistor M 12  serves as the input terminal of the current mirror unit;   the input terminal of the current mirror unit is connected to the output terminal of the second operational amplifier unit (A 2 ), a drain electrode of the PMOS transistor M 12  is connected to a source electrode of the PMOS transistor M 14 , a diode connection mode of gate-drain short circuit is adopted in both the PMOS transistor M 14  and the NMOS transistor M 15 , and a drain electrode of the PMOS transistor M 14  is connected to a drain electrode of the NMOS transistor M 15  and the connection point serves as the output terminal of the current mirror unit; and   the output terminal of the current mirror unit is connected to the second input terminal of the charging and discharging unit and the second input terminal of the first complementary circuit unit, a source electrode of the NMOS transistor M 15  is connected to a drain electrode of the NMOS transistor M 17 , a gate electrode of the NMOS transistor M 17  is connected to the voltage source VDC, and a source electrode of the NMOS transistor M 17  is connected to the ground GND.   
 
         [0036]    Preferably, the second complementary circuit unit includes a PMOS transistor M 11 , a PMOS transistor M 13 , an NMOS transistor M 16  and an NMOS transistor M 18 , where
   a source electrode of the PMOS transistor M 11  is connected to a voltage source VDC, a drain electrode of the PMOS transistor M 11  is connected to a source electrode of the PMOS transistor M 13 , and a drain electrode of the PMOS transistor M 13  is connected to a drain electrode of the NMOS transistor M 16  and the connection point serves as the output terminal of the second complementary circuit unit;   the output terminal of the second complementary circuit unit is connected to the positive input terminal of the second operational amplifier unit (A 2 ), a source electrode of the NMOS transistor M 16  is connected to a drain electrode of the NMOS transistor M 18 , a source electrode of the NMOS transistor M 18  is connected to the ground GND, and a gate electrode of the PMOS transistor M 13  serves as the input terminal of the second complementary circuit unit; and   the input terminal of the second complementary circuit unit is connected to the output terminal of the second operational amplifier unit (A 2 ), a gate electrode of the NMOS transistor M 16  is connected to an external bias BIAS, a gate electrode of the PMOS transistor M 11  is connected to the ground GND, and a gate electrode of the NMOS transistor M 18  is connected to the voltage source VDC.   
 
         [0040]    As compared with the conventional technologies, the present disclosure has the following advantages.
   As compared with the first existing charge pump circuit, the matching issue of charging and discharging currents and the issue of charge sharing are addressed in the present disclosure. And as compared with the second existing charge pump circuit, two complementary circuit units and two operational amplifier units are adopted in the charge pump circuit according to the present disclosure. The two complementary circuit units respectively compensate the charging and discharging unit in a positive way and a negative way. In this case, the charging current and discharging current of the capacitor can be constant, thus the issue of non-constant charging and discharging currents is addressed, the voltage of the charge pump capacitor changes linearly, and the capacitor may be charged or discharged more precisely. The charge pump circuit according to the present disclosure is applicable to an application with low voltage and low power consumption since it has a simple structure and a high matching precision between a charging current source and a discharging current source and is easy to be integrated.   
 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0042]    The drawings to be used in the description of embodiments or the conventional technology are described briefly as follows, so that technical solutions according to the embodiments of the present disclosure or according to the conventional technology may become clearer. It is apparent that the drawings in the following description only illustrate some embodiments of the present disclosure. For those skilled in the art, other drawings may be obtained based on these drawings without any creative work. 
           [0043]      FIG. 1  is a schematic structural diagram of a charge pump phase-locked loop system; 
           [0044]      FIG. 2  is a schematic structural diagram of a first existing charge pump circuit; 
           [0045]      FIG. 3  is a schematic diagram of waveforms of an output voltage and an output current of the first existing charge pump circuit structure; 
           [0046]      FIG. 4  is a schematic structural diagram of a second existing charge pump circuit; 
           [0047]      FIG. 5  is a schematic diagram of waveforms of an output voltage and an output current of the second existing charge pump circuit structure; 
           [0048]      FIG. 6  is a schematic diagram of a charge pump circuit for a charge pump phase-locked loop according to a first embodiment of the present disclosure; 
           [0049]      FIG. 7  is a circuit diagram of a charge pump circuit for a charge pump phase-locked loop according to a second embodiment of the present disclosure; and 
           [0050]      FIG. 8  is a schematic diagram of waveforms of an output voltage and an output current of a charge pump circuit according to the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0051]    Technical solutions according to embodiments of the present disclosure are described clearly and completely hereinafter in conjunction with the drawings. It is apparent that the described embodiments are only a part rather than all of the embodiments according to the present disclosure. Any other embodiments obtained by those skilled in the art based on the embodiments in the present disclosure without any creative work fall in the scope of the present disclosure. 
         [0052]    In order that the objectives, features and advantages of the present disclosure can be more apparent and be better understood, embodiments of the present disclosure are described hereinafter in further detail in conjunction with the drawings. 
       First Embodiment 
       [0053]      FIG. 6  is a schematic diagram of a charge pump circuit for a charge pump phase-locked loop according to a first embodiment of the present disclosure. 
         [0054]    The charge pump circuit for the charge pump phase locked loop according to the embodiment includes a charging and discharging unit  601 , a first complementary circuit unit  602 , a first operational amplifier unit A 1 , a phase inverter unit  603 , a current mirror unit  604 , a second complementary circuit unit  605  and a second operational amplifier unit A 2 . 
         [0055]    An output terminal of the charging and discharging unit  601  is connected to a negative input terminal of the first operational amplifier unit A 1 , and an output terminal of the first complementary circuit unit  602  is connected to a positive input terminal of the first operational amplifier unit A 1 . 
         [0056]    An output terminal of the first operational amplifier unit A 1  is connected to a first input terminal of the charging and discharging unit  601  and a first input terminal of the first complementary circuit unit  602 . 
         [0057]    An input terminal of the phase inverter unit  603  is connected to an output terminal of the first complementary circuit unit  602 , an output terminal of the phase inverter unit  603  is connected to a negative input terminal of the second operational amplifier unit A 2 , and an output terminal of the second complementary circuit unit  605  is connected to a positive input terminal of the second operational amplifier unit A 2 . 
         [0058]    An output terminal of the second operational amplifier unit A 2  is connected to an input terminal of the current mirror unit  604  and an input terminal of the second complementary circuit unit  605 , and an output terminal of the current mirror unit  604  is connected to a second input terminal of the charging and discharging unit  601  and a second input terminal of the first complementary circuit unit  602 . 
         [0059]    It can be seen from the above connections that, the charging and discharging unit  601  and the first complementary circuit unit  602  make a charging current and a discharge current equal to each other with a feedback effect of the first operational amplifier unit A 1 . The charging and discharging unit  601 , the phase inverter unit  603  and the second complementary circuit unit  605  make the charging current and the discharging current constant with a feedback effect of the second operational amplifier unit A 2 . 
       Second Embodiment 
       [0060]    In the following, a specific implementation of a charge pump circuit for a charge pump phase-locked loop according to the present disclosure is described in detail in conjunction with  FIG. 7 . 
         [0061]      FIG. 7  is a circuit diagram of a charge pump circuit for a charge pump phase-locked loop according to a second embodiment of the present disclosure. 
         [0062]    The sub circuit units mentioned in the embodiment corresponding to  FIG. 6  are respectively described in the following. 
         [0063]    The charging and discharging unit  601  includes PMOS transistors M 0  and M 2 , and NMOS transistors M 4  and M 6 . 
         [0064]    A source electrode of the PMOS transistor M 0  is connected to a voltage source VDC. A drain electrode of the PMOS transistor M 0  is connected to a source electrode of the PMOS transistor M 2 . A drain electrode of the PMOS transistor M 2  is connected to a drain electrode of the NMOS transistor M 4 , and the connection point serves as the output terminal of the charging and discharging unit  601 . The output terminal of the charging and discharging unit  601  is connected to the negative input terminal of the first operational amplifier unit A 1 . 
         [0065]    A source electrode of the NMOS transistor M 4  is connected to a drain electrode of the NMOS transistor M 6 . A source electrode of the NMOS transistor M 6  is connected to the ground GND. A gate electrode of the PMOS transistor M 2  serves as the first input terminal of the charging and discharging unit  601 , and the first input terminal of the charging and discharging unit  601  is connected to the output terminal of the first operational amplifier unit A 1 . 
         [0066]    A gate electrode of the NMOS transistor M 4  serves as the second input terminal of the charging and discharging unit  601 , and the second input terminal of the charging and discharging unit  601  is connected to the output terminal of the current mirror unit  604 . 
         [0067]    A gate electrode of the PMOS transistor M 0  and a gate electrode of the NMOS transistor M 6  are respectively connected to output signals UP and DOWN from a phase frequency discriminator. 
         [0068]    The first complementary circuit unit  602  includes PMOS transistors M 1  and M 3 , and NMOS transistors M 5  and M 7 . 
         [0069]    A source electrode of the PMOS transistor M 1  is connected to a voltage source VDC. A drain electrode of the PMOS transistor M 1  is connected to a source electrode of the PMOS transistor M 3 . A drain electrode of the PMOS transistor M 3  is connected to a drain electrode of the NMOS transistor M 5  and the connection point serves as the output terminal of the first complementary circuit unit  602 , and the output terminal of the first complementary circuit unit  602  is connected to the positive input terminal of the first operational amplifier unit A 1 . 
         [0070]    A source electrode of the NMOS transistor M 5  is connected to a drain electrode of the NMOS transistor M 7 , and a source electrode of the NMOS transistor M 7  is connected to the ground GND. A gate electrode of the PMOS transistor M 3  serving as the first input terminal of the first complementary circuit unit  602  is connected to the output terminal of the first operational amplifier unit A 1 . A gate electrode of the NMOS transistor M 5  serving as the second input terminal of the first complementary circuit unit  602  is connected to the output terminal of the current mirror unit  604 . A gate electrode of the PMOS transistor M 1  is connected to the ground GND, and a gate electrode of the NMOS transistor M 7  is connected to the voltage source VDC. 
         [0071]    The phase inverter unit  603  includes a PMOS transistor M 8  and an NMOS transistor M 9 . 
         [0072]    A diode connection mode of gate-drain short circuit is adopted in the PMOS transistor M 8 . A source electrode of the PMOS transistor M 8  is connected to the voltage source VDC. A drain electrode of the PMOS transistor M 8  is connected to a drain electrode of the NMOS transistor M 9  and the connection point serves as the output terminal of the phase inverter unit  603 , which is connected to the negative input terminal of the second operational amplifier unit A 2 . A gate electrode of the NMOS transistor M 9  serving as the input terminal of the phase inverter unit  603  is connected to the output terminal of the first complementary circuit unit  602 . And a source electrode of the NMOS transistor M 9  is connected to the ground GND. 
         [0073]    The current mirror unit  604  includes PMOS transistors M 10 , M 12  and M 14 , and NMOS transistors M 15  and M 17 . 
         [0074]    A source electrode of the PMOS transistor M 10  is connected to a voltage source VDC. A drain electrode of the PMOS transistor M 10  is connected to a source electrode of the PMOS transistor M 12 . A gate electrode of the PMOS transistor M 12  serves as the input terminal of the current mirror unit  604 . And the input terminal of the current mirror unit  604  is connected to the output terminal of the second operational amplifier unit A 2 . 
         [0075]    A drain electrode of the PMOS transistor M 12  is connected to a source electrode of the PMOS transistor M 14 . A diode connection mode of gate-drain short circuit is adopted in both the PMOS transistor M 14  and the NMOS transistor M 15 . A drain electrode of the PMOS transistor M 14  is connected to a drain electrode of the NMOS transistor M 15  and the connection point serves as the output terminal of the current mirror unit  604 . And the output terminal of the current mirror unit  604  is connected to the second input terminal of the charging and discharging unit  601  and the second input terminal of the first complementary circuit unit  602 . A source electrode of the NMOS transistor M 15  is connected to a drain electrode of the NMOS transistor M 17 . A gate electrode of the NMOS transistor M 17  is connected to the voltage source VDC, and a source electrode of the NMOS transistor M 17  is connected to the ground GND. 
         [0076]    The second complementary circuit unit  605  includes PMOS transistors M 11  and M 13 , and NMOS transistors M 16  and M 18 . 
         [0077]    A source electrode of the PMOS transistor M 11  is connected to a voltage source VDC. A drain electrode of the PMOS transistor M 11  is connected to a source electrode of the PMOS transistor M 13 . A drain electrode of the PMOS transistor M 13  is connected to a drain electrode of the NMOS transistor M 16  and the connection point serves as the output terminal of the second complementary circuit unit  605 , and the output terminal of the second complementary circuit unit  605  is connected to the positive input terminal of the second operational amplifier unit A 2 . 
         [0078]    A source electrode of the NMOS transistor M 16  is connected to a drain electrode of the NMOS transistor M 18 . A source electrode of the NMOS transistor M 18  is connected to the ground GND. A gate electrode of the PMOS transistor M 13  serves as the input terminal of the second complementary circuit unit  605 , and the input terminal of the second complementary circuit unit  605  is connected to the output terminal of the second operational amplifier unit A 2 . A gate electrode of the NMOS transistor M 16  is connected to an external bias BIAS. A gate electrode of the PMOS transistor M 11  is connected to the ground GND. And a gate electrode of the NMOS transistor M 18  is connected to the voltage source VDC. 
         [0079]    It should be realized by those skilled in the art that, the above five modules are only examples of the present disclosure. When applied to the charge pump circuit proposed according to the present disclosure, the modules may be used separately, that is, only one or several sub-units of the modules may be used, which will not affect the implementation of the present disclosure. 
         [0080]    Herein, a working principle and a working process of the circuit according to the present disclosure are described in conjunction with the embodiment shown in  FIG. 7 . 
         [0081]    Firstly, how to address the issue of charge sharing with the charge pump circuit according to the present disclosure is described. In  FIG. 7 , locations of the current mirror and the switch transistor are changed. The capacitor of the drain electrode of the current mirror is at the same node with the capacitor C cp  of the charge pump circuit. In this case, voltage variations of capacitors of the drain electrodes of the two current mirrors are equal, and the charge sharing is avoided. 
         [0082]    In  FIG. 7 , operational amplifiers are added in the circuit according to the present disclosure. I ch  may decrease as the output voltage V cp     —     out  rises due to a channel length modulation effect. The voltage at the negative input terminal of the first operational amplifier unit A 1  rises. A decreasing of a voltage at the output terminal of the first operational amplifier unit A 1  results in a decreasing of a voltage at the gate electrode of the transistor M 3 . At this time, it is too late for the positive input terminal of the first operational amplifier unit A 1  to change. Since a voltage at the gate electrode of the transistor M 3  decreases and a drain-source voltage of the transistor M 3  does not change, a current I 1  rises and a current I 2  may also rise correspondingly. If a gate-source voltage of M 5  does not change, a voltage at the drain electrode of M 5  may rise. Finally, voltages at the positive and negative input terminals of the first operational amplifier unit A 1  are equal. That is to say, a potential at a node OUT equals to a potential at a node X, while it is ensured that the transistors M 2 , M 3 , M 4  and M 5  operate within a range of saturation region. In a case that the output signal UP from the phase frequency discriminator is a low level and the output signal DOWN from the phase frequency discriminator is a high level, the switch transistors M 0  and M 6  are switched on, the gate electrodes of the transistor M 2  and the transistor M 3  have the same bias, the drain electrodes of the transistor M 2  and the transistor M 3  are clamped by the first operational amplifier unit A 1 , hence I ch =I 1 =I 2 . Similarly, the gate electrodes of the transistor M 4  and transistor M 5  have the same bias and potentials at the drain electrodes of the transistor M 4  and transistor M 5  are the same, therefore, I dis =I 2 , and then I ch =I dis . 
         [0083]    Finally, the principle of implementing constant charging and discharging currents according to the present disclosure is described. By comparing the waveform diagram in  FIG. 5  and the waveform diagram in  FIG. 8 , it can be seen apparently that, in the second existing charge pump circuit, I ch  and I dis  are equal to each other and may change as the output voltage changes. In the improved charge pump circuit according to the present disclosure, I ch  and I dis  are equal to each other and maintained constant. Based on an equation V cp =Q/C=I·Δt/C, V cp  is directly proportional to the charging/discharging current. And the voltage V cp  across C cp  may be controlled precisely if the charging and discharging currents are constant. 
         [0084]    In the existing charge pump circuit in  FIG. 4 , an operational amplifier unit OTA is provided between a branch circuit  1  of the current mirror and a branch circuit  2  of the current mirror. Thus, potentials at nodes X and Y are the same, and I ch =I dis =I 1 /I 2 . I 1 /I 2  mirrors I ref , and I 1  is constant if the potential at the node X is constant. In fact, the voltage across the capacitor C cp  (the potential at the node Y) may change, which results in that: the potential at the node X changes as the potential at the node Y changes, and a source-drain voltage of a current mirror transistor on the branch circuit  1  changes, thereby changing I 1 /I 2  , and I ch  and I dis . 
         [0085]    In  FIG. 7 , in the charge pump circuit according to the present disclosure, the phase inverter unit  603  and the second operational amplifier unit A 2  are added. I 1 /I 2  is maintained constant with a negative feedback and then I ch  and I dis  are maintained unchanged. A specific process is as follows. If the output voltage Vcp_out rises, and the potential at the node X also rises due to a clamping of the first operational amplifier unit A 1 , that is, a drain-source voltage of M 5  rises. In this case, I 2  is increased due to the channel length modulation effect. After passing through the phase inverter unit composed of M 8  and M 9 , the potential at the node X may decrease at node Y. Since the node Y is the negative input terminal of the second operational amplifier unit A 2 , a gate voltage of the transistor M 12  in the current mirror unit rises and a gate-source voltage of the transistor M 12  decreases, a current flowing through the transistor M 12  may decrease, i.e. the current flowing through the branch circuit of the current mirror unit decreases. Since a diode connection mode is adopted in the transistor M 15 , the gate voltage of the transistor M 15  may decrease correspondingly, that is, the gate voltage of the transistor M 5  decreases, therefore, the current I 2  decreases and the current I 2  can be maintained constant. Further, since I ch =I dis =I 1 /I 2 , I ch  and I dis  are equal to each other and maintained constant. 
         [0086]    In summary, as compared with the first existing charge pump circuit, the matching issue of charging and discharging currents and the issue of charge sharing are addressed in the present disclosure. And as compared with the second existing charge pump circuit two complementary circuit units and two operational amplifier units are adopted in the charge pump circuit according to the present disclosure. The two complementary circuit units respectively compensate the charging and discharging unit in a positive way and a negative way. In this case, the charging current and discharging current of the capacitor can be constant, thus the issue of non-constant charging and discharging currents is addressed, the voltage of the charge pump capacitor changes linearly, and the capacitor may be charged or discharged more precisely. The charge pump circuit according to the present disclosure is applicable to an application with a low voltage and a low power consumption since it has a simple structure and a high matching precision between a charging current source and a discharging current source and is easy to be integrated. 
         [0087]    The above embodiments are only preferred embodiments of the present disclosure and do not limit the present disclosure in any form. Preferred embodiments of the present invention are disclosed above, which should not be interpreted as limiting the present invention. Numerous alternations, modifications, and equivalents can be made to the technical solution of the present invention by those skilled in the art in light of the methods and technical content disclosed herein without deviation from the scope of the present invention. Therefore, any alternations, modifications, and equivalents made to the embodiments above according to the technical essential of the present invention without deviation from the scope of the present invention should fall within the scope of protection of the present invention.