Abstract:
A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

Description:
RELATED APPLICATIONS 
     This application is a Continuation-In-Part (CIP) of U.S. patent application Ser. No. 11/237,099, filed Sep. 28, 2005 now U.S. Pat. No. 7,283,390 titled “HYBRID NON-VOLATILE MEMORY”, by inventor Alberto Pesavento, issued Oct. 16, 2007, which is a CIP of U.S. patent application Ser. No. 10/839,985, filed May 5, 2004, now U.S. Pat. No. 7,221,596, issued on May 22, 2007. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to nonvolatile memory. More particularly, the present invention relates to single-ended and differential-type nonvolatile memory using floating-gate p-channel field effect transistors (pFETs) to store information as electric charge. 
     BACKGROUND 
     Nonvolatile memory (NVM) is an important form of memory in today&#39;s electronic circuits. NVM is used to store serial number information, security information, settings, parameters, computer instructions (firmware), and the like. Reprogrammable NVM is particularly important in the field of tags, such as RFID (radio frequency identification) tags, which store information inexpensively and can be remotely sensed without the need to complete an actual circuit with the RFID tag itself. Such tags lack their own power supply and are powered instead by current rectified from a scanner&#39;s read-carrier RF signal received from an RFID reader/scanner. 
     SUMMARY 
     A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd), its drain providing the current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor structure having its first terminal coupled to the first voltage source and its second terminal coupled to the floating gate and a tunneling capacitor structure having its first terminal coupled to the second voltage source and its second terminal coupled to the floating gate are utilized in each embodiment. The control capacitor structure may be fabricated so that it has much more capacitance than does the tunneling capacitor structure (and assorted stray capacitance between the floating gate and various other nodes of the cell). Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) control an electric field across the capacitor structure and pFET dielectrics, thus Fowler-Nordheim tunneling of electrons onto and off of the floating gate, thus controlling the charge on the floating gate and the information value stored thereon. Both single-ended and differential memory cells are implemented. Hysteresis circuits may also be provided to supply additional write margin. Arrays of such nonvolatile memory cells are also implemented. 
     Other aspects of the inventions are described and claimed below, and a further understanding of the nature and advantages of the inventions may be realized by reference to the remaining portions of the specification and the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present invention and, together with the detailed description, serve to explain the principles and implementations of the invention. 
       In the drawings: 
         FIG. 1A  is an electrical schematic diagram illustrating an embodiment of a basic differential pFET NVM memory cell  10 , in accordance with an embodiment of the present invention. 
         FIG. 1B  is a side elevational diagram of a well-source-drain shorted pFET as used in some embodiments of the present invention for the control capacitor structure and the tunneling transistor structure. 
         FIG. 1C  is a side elevational diagram of a simplified capacitor structure as used in some embodiments of the present invention for the control capacitor structure. 
         FIG. 2  is a partial electrical schematic diagram, illustrating on the left, a portion of the schematic of  FIG. 1A  with the control transistor (also referred to herein as a control capacitor or control capacitor structure) M 1   c , shown enlarged relative to tunneling transistor (also referred to herein as a tunneling transistor or tunneling transistor structure) M 1   t . On the right of the schematic diagram symbol for a capacitor C 1   c  takes the place of transistor M 1   c  and the schematic diagram symbol for a capacitor C 1   t  takes the place of transistor M 1   t.    
         FIG. 3  is a process flow diagram formed of partial electrical schematic diagrams, like those in  FIG. 2  which illustrates the process for adding and removing electrons from a floating gate Fg, in accordance with an embodiment of the present invention. 
         FIG. 4  is an electrical schematic diagram of an NVM cell, in accordance with an embodiment of the present invention, in which the V 0  signal is coupled to the tunneling transistor M 1   t  for floating gate Fg 1  and to the control transistor M 0   c  for floating gate Fg 0 , while the V 1  signal is coupled to the control transistor M 1   c  for floating gate Fg 1  and to the tunneling transistor M 0   t  for floating gate Fg 0 . 
         FIG. 5  is a plot of Vtun (tunneling voltage) vs. floating gate voltage for the differential and single-ended cases of NVM cells. 
         FIGS. 6A ,  6 B, and  6 C illustrate various ways to implement the present invention in a single-ended circuit. In accordance with the circuit of  FIG. 6A  the second floating gate is coupled to a voltage source to provide a voltage reference for the pFET M 0 . A practical reference can be ground itself, as illustrated in  FIG. 6B . The pFET M 0  can be omitted altogether, as in  FIG. 6C , if a current reference (not shown) is available to the sense amplifier for the current comparison. 
         FIG. 7A  is a plot of Device readout current vs. Vtun (or, effectively, time) illustrating the concept of hysteresis by addition, in accordance with an embodiment of the present invention. The I 0 /I 1  curves are the nominal curves. The I 1 +I H  curve represents the I 1  curve to which hysteresis current I H  has been added. Tunneling is halted when I 1 +I H &lt;I 0 .  FIG. 7B  is a plot of Fg Voltage vs Vtun (or time) for Fg 0  and Fg 1  illustrating the increase in the size of the programming window as a result of adding the hysteresis current I H .  FIG. 7C  is a plot of Device current vs. Vtun (or time), illustrating the concept of hysteresis by subtraction. in accordance with an embodiment of the present invention. 
         FIG. 8  is an electrical schematic diagram of an NVM cell  34  in accordance with an embodiment of the present invention. The NVM cell  34  utilizes hysteresis by addition and has added pFET transistors Mh 1  and Mh 0 , which have their source and well terminals coupled to V and their drains coupled to the respective current output legs (drains) of the M 1  and M 0  readout transistors. In this way, the current from Mh 1  is added to transistor M 1 &#39;s output current and the current from Mh 0  is added to transistor M 0 &#39;s output current. The control signals Vh 1  and Vh 0  applied, respectively, to the gates of Mh 1  and Mh 0  control the hysteresis during programming. 
         FIG. 9  is an electrical schematic diagram of an NVM cell  36 , in accordance with an embodiment of the present invention. The NVM cell  36  utilizes hysteresis by addition and has added pFET transistors Mh 1 , Mhe 1 , Mh 0  and Mhe 0 . Mh 1  and Mh 0  have their source and well terminals coupled to V and Mhe 1  and Mhe 0  have their well terminals coupled to V and their sources coupled to the drains of Mh 1  and Mh 0 , respectively. The drains of Mhe 1  and Mhe 0  provide the additional hysteresis current during programming. Operation of transistors Mhe 1  and Mhe 0  is controlled by signals Vhe 1  and Vhe 0 , respectively, applied to their gates. 
         FIG. 10  is an electrical schematic diagram of an NVM cell  38 , in accordance with an embodiment of the present invention. The NVM cell  38  utilizes hysteresis by subtraction and has added nFET transistors Mh 1  and Mh 0  coupled so that their sources are coupled to ground and their drains are in common, respectively, with the drains of M 1  and M 0 , thus subtracting current when they are engaged. Control signals Vh 1  and Vh 0  applied, respectively, to the gates of Mh 1  and Mh 0  control the hysteresis function. 
         FIG. 11A  is an electrical schematic diagram of an NVM cell  40 , in accordance with an embodiment of the present invention. The NVM cell  40  includes a pair of nFET readout transistors Ms 1  and Ms 0  configured as row-select transistors, which control current flow in the drain legs of readout transistors M 1  and M 0 , respectively. 
         FIG. 11B  is an electrical schematic diagram of an NVM cell  42 , in accordance with an embodiment of the present invention. The NVM cell  42  includes a pair of pFET readout transistors Ms 1  and Ms 0  configured as row-select transistors, which control current flow in the drain legs of readout transistors M 1  and M 0 , respectively. 
         FIG. 12  is a block diagram of an array of NVM cells and an electrical schematic diagram of one of those cells, in accordance with an embodiment of the present invention. 
         FIG. 13A  is an electrical schematic diagram of an NVM cell, for use in an array of NVM cells, in accordance with a PRIOR ART embodiment. 
         FIG. 13B  is an electrical schematic diagram of an NVM cell, for use in an array of NVM cells, in accordance with an embodiment of the present invention. 
         FIG. 14A  is a table, illustrating a set of applied voltages and operating states for the NVM cell of  FIG. 13A . 
         FIG. 14B  is a table, illustrating a set of applied voltages and operating states for the NVM cell of  FIG. 13B . 
         FIG. 15  is a block diagram of an array of NVM cells, in accordance with  FIG. 13B , and an electrical schematic diagram of one of those cells, in accordance with an embodiment of the present invention. 
         FIG. 16  is an electrical schematic diagram illustrating how the present invention avoids program disturb in respect to two adjacent NVM cells within the same column. 
         FIG. 17  is an electrical schematic diagram of an NVM cell, for use in an array of NVM cells, in accordance with another embodiment of the present invention. 
         FIG. 18  is a table illustrating a set of applied voltages and operating states for the NVM cell of  FIG. 17 . 
         FIG. 19  is a simplified circuit diagram showing a FN tunneling current of the NVM cell. 
         FIG. 20  is a diagram showing the impact of source/drain bias on the FN tunneling current of the NVM cell of  FIG. 19 . 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention described in the following detailed description are directed at floating-gate nonvolatile memory cells having pFET readout transistors. Those of having ordinary skill in the art will realize that the detailed description is illustrative only and is not intended to restrict the scope of the claimed inventions in any way. Other embodiments of the present invention, beyond those embodiments described in the detailed description, will readily suggest themselves to those of ordinary skill in the art having the benefit of this disclosure. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. Where appropriate, the same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or similar parts. 
     In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer&#39;s specific goals, such as, compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure. 
     As used herein, the symbol n+ indicates an n-doped semiconductor material typically having a doping level of n-type dopants on the order of 10 21  atoms per cubic centimeter. The symbol n− indicates an n-doped semiconductor material typically having a doping level on the order of 10 17  atoms per cubic centimeter. The symbol p+ indicates a p-doped semiconductor material typically having a doping level of p-type dopants on the order of 10 21  atoms per cubic centimeter. The symbol p− indicates a p-doped semiconductor material typically having a doping level on the order of 10 17  atoms per cubic centimeter for p− wells and a doping level on the order of 10 15  atoms per cubic centimeter for p− substrate material. Those of ordinary skill in the art will now realize that the devices described herein may be formed on a conventional semiconductor substrate or they may as easily be formed as a thin film transistor (TFT) above the substrate, or in silicon on an insulator (SOI) such as glass (SOG), sapphire (SOS), or other substrates, as known to those of ordinary skill in the art. Such persons of ordinary skill in the art will now also realize that a range of doping concentrations around those described above will also work. Essentially, any process capable of forming pFETs and nFETs will work. Doped regions may be diffusions or they may be implanted. 
     A number of circuits, that may be used as NVM cells and arrays for such cells, are described in detail below. These NVM circuits are able to store information by modifying a charge (i.e., by adding or removing electrons) stored on a floating gate of one or more pFET transistors. In digital implementations of the invention, the state (i.e., either a “1” or a “0”) of the memory cell is read by measuring the current of some of the pFETs in the circuit. The use of pFETs instead of nFETs (n-channel FETs) offers better data retention, higher endurance, and requires no additional processing steps beyond what is available in standard logic CMOS processes. Obviously, if desired, these circuits can be fabricated in as complicated a process as desired; however, they are all capable of being fabricated in single-poly (single layer of polysilicon) logic CMOS processes, as supported by virtually all semiconductor foundries operating today. Conventional FLASH and EEPROM NVM require special process steps beyond those of logic CMOS and are, consequently, more difficult and more expensive to fabricate. Applications that require up to several kilobytes of NVM on the same chip with other circuitry and/or require low cost fabrication are ideal candidates for the circuits discussed herein. 
     Turning now to  FIG. 1A , a basic differential pFET NVM memory cell  10  is illustrated. This cell has two floating gates denoted Fg 0  and Fg 1 . By storing a different amount of electrons on the two floating gates, it is possible to establish a voltage differential between the two floating gates. When the NVM cell is powered, through the terminal denoted “V”, a difference in the readout currents I 0  and I 1  is present and a sense amplifier such as a conventional current sense amplifier  12  can consequently be used to discern the logic value stored in the cell. For example, the condition I 0 &gt;I 1  may be used to signify the logic value “0” and the condition I 0 &lt;I 1  may be used to signify the logic value “1”. 
     As shown in  FIG. 1A , transistors M 1 , M 1   t  and M 1   c  have floating gate Fg 1  in common. Transistors M 0 , M 0   t  and M 0   c  have floating gate Fg 0  in common. V 1   c  is the voltage terminal for transistor M 1   c ; V 1   t  is the voltage terminal for transistor M 1   t ; V is the voltage terminal for transistors M 1  and M 0 ; V 0   t  is the voltage terminal for transistor M 0   t ; and V 0   c  is the voltage terminal for transistor M 0   c . As can be seen M 1   c , M 1   t , M 0   t , and M 0   c , in accordance with this illustrated embodiment, may all be shorted pFETs in that their source, drain and well connections are all tied together as shown. The voltage terminals referred to above are therefore connected to the respective source, drain and well of the shorted pFETs. M 1   c , M 1   t , M 0   t , and M 0   c  may also be constructed as other types of transistors, such as nFETs. M 1   c  and M 0   c , which are used as control capacitors, may also be constructed as poly-poly, or poly-metal capacitors. Metal-metal capacitors can also be used for the control capacitor structures, although with existing fabrication processes this would reduce the memory retention time due to leakage from the poly contact and the metal inter-layer dielectric. By applying the appropriate voltages to terminals V 01 , V 0   t , V 1   c , V 1   t  and V, a sufficiently large electric field can be established across the oxide dielectric of any of the three pFETs connected to each floating gate Fg 0 , Fg 1 , so that the well-known mechanism of Fowler-Nordheim (FN) tunneling may be used to pass electrons through the oxide dielectric of the selected transistor. 
     In order to establish a large electric field across one of the pFETs&#39; oxides, the gate area of one of the two corresponding shorted pFETs (e.g., M 1   c  and M 1   t  shown on the left side in  FIG. 1A ) should be made sufficiently large so that it acts as a control capacitor for the floating gate itself.  FIG. 1B  is a side elevational diagram of a well-source-drain shorted pFET as used in some embodiments of the present invention for the control capacitor structure and the tunneling transistor structure. Terminals T 1  and T 2  are the capacitor terminals.  FIG. 1C  is a side elevational diagram of a simplified capacitor structure as used in some embodiments of the present invention for the control capacitor structure. Terminals T 1  and T 2  are the capacitor terminals although the device of  FIG. 1C  is not, strictly speaking, a transistor. Those of ordinary skill in the art will now realize that various other structures may be used to achieve the same purposes. 
     Turning now to  FIG. 2 , on the left is a portion of the schematic of  FIG. 1A  with the transistor M 1   c  shown enlarged relative to transistor M 1   t ; on the right capacitor C 1   c  takes the place of transistor M 1   c  and capacitor C 1   t  takes the place of transistor M 1   t . Where the physical size of transistor M 1   c  is much larger than that of transistor M 1   t  then M 1   c  behaves like a control capacitor for the floating gate Fg 1  and can be used to control the floating-gate voltage to establish a large electric field that can be applied to induce bidirectional FN tunneling. 
     Turning now to  FIG. 3 , the process for adding and removing electrons from a floating gate Fg is illustrated. The upper branch of the process is denoted  14 , and illustrates adding electrons to the floating gate to drop its voltage from 0V to −2V. The lower branch of the process is denoted  16 , and illustrates removing electrons from the floating gate to raise its voltage from 0V to +2V. 
     In more detail, starting from the rest condition  18  with Vc=0V (Vc here is the voltage applied to the source, drain and well terminals of control transistor Mc), Vt=0V (likewise, Vt here is the voltage applied to the source, drain and well terminals of tunneling transistor Mt) and Fg=0V at time t=0, one first establishes the appropriate voltage across the oxide of one of the pFETs by changing the voltage of either Vc or Vt. Due to the skewed capacitive ratio between the two pFETs Mc and Mt, the floating gate is more strongly coupled to the control voltage Vc, creating a large electric field through the oxide of the tunneling pFET Mt at time t=1 (20). Once the electric field is present, electrons start tunneling through the oxide of Mt either adding or removing charge from the floating gate at time t=2 (22). After a certain amount of time the voltage of the floating gate has changed enough to decrease the electric field to the point that the tunneling process is slowed considerably. If the rest biases (Vc=Vt=0V) are then reapplied at time t=3 (24), the net effect of the procedure is that the charge on the floating gate was modified. The voltage values in the example of  FIG. 3  are intended to be just an example. The real values will depend upon various factors such as oxide thickness and quality, desired program time, endurance and retention requirements, and the fabrication process used and are well within the skills of those of ordinary skill in the art having the benefit of this disclosure. 
     It is now easy to observe that if the opposite biasing voltages are applied to the “0” and “1” sides of the differential NVM cell, electrons can be removed from one floating gate while they are being added to the other. This can be easily accomplished by connecting the NVM cell as illustrated in  FIG. 4 . In this embodiment, the V 0  signal is coupled to the tunneling transistor M 1   t  for floating gate Fg 1  and to the control transistor M 0   c  for floating gate Fg 0  while the V 1  signal is coupled to the control transistor M 1   c  for floating gate Fg 1  and to the tunneling transistor M 0   t  for floating gate Fg 0 . 
     The use of a differential memory cell is advantageous because it allows the doubling of the storage window with respect to a single-ended memory cell. This is illustrated in  FIG. 5 , which shows a plot of Vtun (tunneling voltage) vs. floating gate voltage for the differential and single-ended cases. In a single-ended cell, a reference voltage is generally required and a viable result may be obtained in the sectors shown as shaded and denoted  26 . In the double-ended cell, no reference voltage is required and a viable result may be obtained in much larger sectors shown as shaded and denoted  28 . 
     A single-ended approach, on the other hand, has the benefit of reducing by approximately half the number of transistors in the memory cell thus providing an advantage with respect to the differential version in terms of area and cost. The memory cell of  FIG. 1A , and the other versions thereof shown and described herein, can be easily implemented as single-ended cells in accordance with the teachings herein with particular reference to  FIGS. 6A ,  6 B and  6 C. Differential memory is particularly advantageous in situations where reliable reference voltage sources are not readily available, such as, in portable devices, remotely powered devices (such as RFID tags and security cards), and the like. 
       FIGS. 6A ,  6 B and  6 C illustrate various ways to implement the present invention in a single-ended circuit. In accordance with the circuit of  FIG. 6A  the second floating gate is coupled to a voltage source to provide a voltage reference for the pFET M 0 . A practical reference can be ground itself, as illustrated in  FIG. 6B . The pFET M 0  can be omitted altogether, as in  FIG. 6C , if a current reference (not shown) is available to the sense amplifier for the current comparison. 
     In accordance with the embodiments of  FIGS. 6A ,  6 B and  6 C, to program a logic “0” in a cell that has a stored logic “1” it is necessary to apply the correct voltages to the terminals V 0  and V 1  (see, e.g.,  FIG. 4 ). Using the convention that there is a logic “0” when I 0 &gt;I 1  the correct voltages are V 0 =10V and V 1 =0V (note that, if desired, the convention could be reversed). 
     For technical reasons (to avoid overstressing the oxide with excess tunneling current) and practical reasons (limitation of the charge pump supplying the high-voltage) the high-voltage applied to program the cell is not held constant but rather is applied with a ramp-like profile. It is possible to perform a timed program operation where the high-voltage is applied for a certain amount of time that is deemed sufficient to tunnel the right amount of charge to and from the floating gates. This can be problematic where transistors are not precisely identical throughout an array or chip as size or conductivity differences may lead one cell to require a longer amount of time to achieve the same state as another cell. Another approach involves applying the high-voltage until a read operation on the memory cell reports that the desired logic value is stored in the cell. This does not pose any technical problems because the time it takes to read the cells is much less than the time it takes to write them. To insure a sufficient write margin a hysteresis mechanism can be introduced to make sure the desired programming window is achieved. Hysteresis can be achieved either by subtracting some current from the winning side (the side that is increasing its intrinsic current, also known as the high current side) or by adding some current to the losing side (the side that is decreasing its intrinsic current, also known as the low current side). This concept is illustrated in  FIGS. 7A ,  7 B, and  7 C. 
       FIG. 7A  is a plot of Device readout current vs. Vtun (or, effectively, time) and illustrating the concept of hysteresis by addition. The I 0 /I 1  curves are the nominal curves. The I 1 +I H  curve represents the I 1  curve to which has been added hysteresis current I H . Tunneling is thus halted when I 1 +I H &lt;I 0 .  FIG. 7B  is a plot of Fg Voltage vs Vtun (or time) for Fg 0  and Fg 1  illustrating the increase in the size of the programming window as a result of adding the hysteresis current I H .  FIG. 7C  is a plot of Device current vs. Vtun (or time) and illustrating the concept of hysteresis by subtraction. The I 0 /I 1  curves are the nominal curves. The I 0 −I H  curve represents the I 0  curve from which has been subtracted hysteresis current I H . Tunneling is thus halted when I 0 −I H &gt;I 1 . Extra program time to achieve the additional margin is incurred by the hysteresis—shown as  30  in  FIG. 7A ,  31  in  FIG. 7B , and  32  in  FIG. 7C . 
     In order to implement the hysteresis during programming the basic NVM cell may be modified to include transistors necessary to perform the function. Some examples of such modifications of the basic memory cell are depicted in  FIGS. 8 ,  9  and  10 . The  FIG. 8  (hysteresis by addition) NVM cell  34  has added pFET transistors Mh 1  and Mh 0 , which have their source and well terminals coupled to V and their drains coupled to the respective current output legs (drains) of the M 1  and M 0  readout transistors. In this way, the current from Mh 1  is added to transistor M 1 &#39;s output current and the current from Mh 0  is added to transistor M 0 &#39;s output current. The control signals Vh 1  and Vh 0  applied, respectively, to the gates of Mh 1  and Mh 0  control the hysteresis during programming. 
     The  FIG. 9  (hysteresis by addition) NVM cell  36  has added pFET transistors Mh 1 , Mhe 1 , Mh 0  and Mhe 0 . Mh 1  and Mh 0  have their source and well terminals coupled to V and Mhe 1  and Mhe 0  have their well terminals coupled to V and their sources coupled to the drains of Mh 1  and Mh 0 , respectively. The drains of Mhe 1  and Mhe 0  provide the additional hysteresis current during programming. Operation of transistors Mhe 1  and Mhe 0  is controlled by signals Vhe 1  and Vhe 0 , respectively, applied to their gates. Transistors Mh 1  and Mh 0  in this application have their gates coupled, respectively, to floating gates Fg 1  and Fg 0  which has the effect of making the hysteresis current proportional to the current of the readout transistor. This approach allows the combined current of the hysteresis transistor and the readout transistor to go to zero and thus guarantees that cell programming can complete. With a fixed hysteresis current, cell programming may not complete if the hysteresis current exceeds the maximum available current from the readout transistor. 
     The  FIG. 10  (hysteresis by subtraction) NVM cell  38  has added nFET transistors Mh 1  and Mh 0  coupled so that their sources are coupled to ground and their drains are in common, respectively, with the drains of M 1  and M 0 , thus subtracting current when they are engaged. Control signals Vh 1  and Vh 0  applied, respectively, to the gates of Mh 1  and Mh 0  control the hysteresis function. 
     In order to provide an array-type memory disposed in columns and rows as is common in semiconductor memories, it may be desirable to provide readout transistors to control which cells are being read out at a given moment. In NMV circuit  40  of  FIG. 11A  a pair of nFET readout transistors Ms 1  and Ms 0  configured as row-select transistors control current flow in the drain legs of readout transistors M 1  and M 0 , respectively. The Vrow signal is coupled to the gates of Ms 1  and Ms 0  to control whether they conduct or not. Similarly, in NVM circuit  42  of  FIG. 11B  a pair of pFET readout transistors Ms 1  and Ms 0  control current flow in the drain legs of readout transistors M 1  and M 0 , respectively. The Vrow signal is coupled to the gates of Ms 1  and Ms 0  to control whether they conduct or not. These may be used with, or without, the hysteresis transistors discussed above, as desired. Hysteresis current may be added before or after the row select transistors. Hysteresis current added after the row select transistors may be common to all the memory cells in the column. This reduces the total number of devices required and thus reduces memory area. 
     Once the row-select transistors are embedded in the nonvolatile memory cells, it is possible to array the cells in a row-column configuration like the one depicted in  FIG. 12 . A drawback of this approach is that every nonvolatile memory cell will be required to contain a high-voltage switch (typically a high-voltage nFET with its drain disposed in an n+ region such as an LDMOS (lateral defused MOS) or a DEMOS (drain extended MOS) cascoded with another nFET so that it can handle the relatively high voltages used for writing the NVM cells without breaking down) to provide the appropriate data-dependent voltages to the V 0  and V 1  terminals of the memory cell during programming. 
     In the array  44  of NVM cells  46  depicted in  FIG. 12 , column control signals comprise the data inputs referred to as D 1  and D 0  for the cell; row control signals comprise the row select signals and any hysteresis control signals which may be used as well as the high-voltage power for the high-voltage switch for each NVM cell. Other control signals may be also used, depending on the particular implementation, such as the choice of switch, etc. V may be applied via the row control signals to each NVM cell or it may be provided in some other way such as with the column control signals. Sense amplifiers are arranged for each column to receive the drain current from M 1  and M 0  for the selected row. 
     In this embodiment, a high-voltage switch has to be included in every cell location in order to prevent program-disturb—changing an already-programmed cell&#39;s contents while writing a different cell. In order to overcome this drawback and make a more space-efficient NVM cell, the basic NVM cell may be reconfigured to that, shown in  FIG. 13A . The  FIG. 13A  drawing shows the tunneling transistors as capacitors, denoted TJ 1  and TJ 0  and the control transistors as capacitors, denoted C 1  and C 0  for clarity, but they may be implemented with the pFETs as illustrated, for example, in  FIGS. 1 and 2 , discussed above. In this embodiment, VDD is provided at all times to bias the gates of transistors M 1   d  and M 0   d ; REN (row enable); TUN and RSB (row select bar) are provided as shown in the table of  FIG. 14A . The signals VDD, REN, TUN and RSB are the row control signals, although VDD need not be applied via a row and could instead be applied via a column. The column control signals comprise the data signals on lines D 1  and D 0  and these are applied as illustrated, for example, in the table of  FIG. 14A . Other values may also be possible. 
     The NVM cell circuit  48  of  FIG. 13A  differs from the NVM cell circuit  46  of  FIG. 12 , in that in addition to the removal of the high-voltage switch  47  from the NVM cell  46  (because the high-voltage switching can be handled once per line, per row or column), two additional pFETs M 1   d  and M 0   d  have been added. Mid and M 0   d  have their gates coupled together and to VDD and their sources, drains and well connections coupled to the corresponding sources, drains and well connections of respective readout transistors M 1  and M 0 . This is done in order to avoid disturbing the contents of the cell when it is not selected. As can be see from the table in  FIG. 14A , during read operations, the REN (row enable) line is set to VDD and with the gates of M 1   d  and M 0   d  at VDD M 1   d  and M 0   d  are not conducting and readout transistors M 1  and M 0  operate normally to provide an output current as a function of charge stored on corresponding floating gates Fg 1  and Fg 0 . During a write operation for a different cell in the same column, REN is set to approximately half the tunneling voltage. With VDD on the gates of M 1   d  and M 0   d , M 1   d  and M 0   d  conduct, effectively connecting the drain nodes of M 1  and M 0  to REN. Since the drain, source and bulk nodes of both M 1  and M 0  are set to half the tunneling voltage, there can be no tunneling across M 1  or M 0 . And since TUN is also set to half the tunneling voltage during this write protect mode, there can be no tunneling across TJ 1  or TJ 0 . 
     To make a more space-efficient NVM cell, the prior art NVM cell is reconfigured to that shown in  FIG. 13B . The  FIG. 13B  drawing shows the tunneling transistors as capacitors denoted TJ 1  and TJ 0  and the control transistors as capacitors denoted C 1  and C 0  for clarity but they may be implemented with the pFETs as illustrated, for example, in  FIGS. 1 and 2 , discussed above. In this embodiment, REN (row enable); TUN and RSB (row select bar) are provided as shown in the table of  FIG. 14B . The signals REN, TUN and RSB are the row control signals The column control signals comprise the data signals on lines D 1  and D 0  and these are applied as illustrated, for example, in the table of  FIG. 14B . Other values may also be possible. 
     Note the absence transistors M 0   d  and M 1   d , shown in  FIG. 13A , and in  FIG. 13  of issued U.S. Pat. No. 7,221,596B2. The inventors has since found that removal of these transistors has no effect of the basic operation of the NVM cell, nor does it have any detrimental effect on the program-disturb characteristic of the cell. To protect against program-disturb the behaviors of nodes N 0  and N 1  are important factors to be considered. Behaviors of this node are discussed next. 
     In  FIG. 19 , the FN tunneling currents of transistors M 0  and M 1  are shown. In  FIG. 20  the diagram shows the impact of source/drain bias on the FN tunneling currents. Where traces  206 ,  208 ,  210 , and  212  show accumulation tunneling currents at Vd_Vs (N 1 ) equals −3V, −2V, −1V, and 0V respectively. The diagram shows that FN tunneling current to transistor M 1  is independent of N 1 . Therefore holding it at a particular value, for example 5V is not necessary to protect against program disturb. Traces  202  and  204  show the inversion tunneling currents at Vd_Vs (N 0 ) equals −1V and 0V respectively. Although inversion tunneling currents show dependency of Vd−Vs, this dependency does not play any role in program disturb since node N 0  is held at REN by transistor M 0 . 
     Turning now to  FIG. 15 , an array  50  of NVM cells  48  is depicted which operates in accordance with the voltages stated in the table of  FIG. 14B . Smaller minimum feature sizes and reduced oxide thickness may reduce these voltage requirements somewhat. In this array  50  the TUN, REN and RSB signals are common for a given row and comprise the row control signals while D 1  and D 0  are common for a given column and comprise the column control signals. Sense amplifiers (or equivalent readout circuitry) is provided for each column and reads the output currents for the selected row. 
       FIG. 16  illustrates how the present invention avoids program disturb with respect to two adjacent NVM cells  48   a  and  48   b  within the same column. Cell  48   a  is having a 1 written where the previously stored data was a zero (as after the cell was erased, for example). In this case, using the figures from the table in  FIG. 14B , D 0 =0V, D 1 =10V, REN_ 0  (for this row)=0V, RSB_ 0  (for this row)=5V and TUN_ 0  (for this row)=10V. In the adjacent cell  48   b , to avoid disturbing already-stored data, D 0 =0V and D 1 =10V because these are in common with NVM cell  48   a . REN_ 1 =RSB_ 1 =TUN_ 1 =5V. This prevents disturb and also keeps any current from M 1  and M 0  of NVM cell  48   b  from contributing to the output current. 
       FIG. 17  is an electrical schematic diagram of an NVM cell for use in an array of NVM cells in accordance with another embodiment of the present invention. The difference between the cell of  FIG. 17  and the cell of  FIG. 13B  is that the well of at least some of the FET devices is not controlled directly by signal REN, but from a different signal (WELL) in the  FIG. 17  embodiment. This permits more freedom in the choice of biasing condition during various states of operation. In the embodiment of  FIG. 17 , the TUN, REN and RSB signals are common for a given row of an array of like memory cells; the D 1  and D 0  signals are common for a given column of like memory cells and the WELL signal can be shared by all like memory cells in the array. 
       FIG. 18  is a table illustrating a set of applied voltages and operating states for the NVM cell of  FIG. 17 . Those of ordinary skill in the art will now realize that other values may also work. 
     A method of operating the cells described herein includes applying the voltage signals set forth in exemplar  FIGS. 14B and 18  to the corresponding cells of  FIGS. 13B and 17 , respectively. The voltages are typically developed on chip using charge pumps for minimum size. Charge pumps may provide static voltages, or, more effectively, ramped voltages as are well known to those of ordinary skill in the art. In accordance with the claims set forth below, the “biasing” may be achieved with the control capacitor structure. The “charging” and “discharging” may be achieved with the tunneling capacitor structure to achieve Fowler-Nordheim tunneling. Note that the voltages set forth in  FIGS. 14B and 18  are exemplary voltages for use with devices built in a 0.18 micron minimum feature size logic CMOS fabrication process technology. As technology improves, minimum feature sizes steadily decrease until some possible fundamental physical limit is ultimately reached. As these sizes decrease, the voltages used will also decrease as the same electric field can be achieved with a smaller voltage over a correspondingly smaller distance. Thus, the voltages set forth in  FIGS. 14B and 18  are examples only and those of ordinary skill in the art will now realize that other voltages may be used where appropriate for the process technology used to fabricate the memory cells. 
     While embodiments and applications of this invention have been shown and described, it will now be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts disclosed herein. Therefore, the appended claims are intended to encompass within their scope all such modifications as are within the true spirit and scope of this invention