Abstract:
A circuit includes a first pre-amp circuit that provides a first pre-amp current and a second pre-amp circuit that provides a second pre-amp current. A first threshold circuit is configured to generate a first output signal responsive to a difference between a variable current and the first pre-amp current. A second threshold circuit is configured to generate a second output signal responsive to a difference between the variable current and the second pre-amp current. One of the branches of a differential interpolation circuit includes a first transistor that is connected in a current mirror configuration with the first pre-amp circuit. The first transistor has a width/length ratio equal to the product nk, where n&lt;1. A second transistor is connected in a current mirror configuration with the second pre-amp circuit. The second transistor has a width/length ratio equal to the product mk, where m&lt;1 and n+m is about 1. The interpolation circuit is configured to generate a third output signal responsive to a difference between the variable current and an interpolated reference current given by n*(first pre-amp current)+m*(second pre-amp current).

Description:
RELATED APPLICATION 
   This application claims the benefit of and priority to U.S. Provisional Patent Application No. 60/379,691, filed May 10, 2002, the disclosure of which is hereby incorporated herein by reference. 

   FEDERALLY SPONSORED RESEARCH 
   The U.S. Government may have certain rights to this invention as provided for by the terms of Contract Number 5-30494 awarded by DARPA. 

   FIELD OF THE INVENTION 
   The present invention relates generally to integrated circuit devices, and, more particularly, to sense amplifier devices and methods of operating the same. 
   BACKGROUND OF THE INVENTION 
   In general, the demand for lower cost-per-bit, multilevel non-volatile memories has increased in two major application areas: stand-alone systems and embedded systems. For embedded applications, high-speed sensing may he used during read/write memory operations. High speed sensing implementations may use a parallel sensing architecture because it typically involves a single comparison step (see, e.g.,  FIG. 1 , and C. Calligaro et al. “A High-Speed Sensing Scheme for Multi-Level Non-Volatile Memories,” in Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing. 1997, pp. 96-99.) As shown in  FIG. 1 , parallel sensing schemes, however, generally use ( 2   n − 1 , where n is the number of bits in a memory cell) copies of reference currents (Ir 1  through Ir 2   n − 1 ), pre-amplifiers, and output-stages, which may result in relatively-large area consumption on a chip and/or relatively large power consumption. To avoid these deficiencies, other architectures have been proposed, such as, for example, a serial sensing architecture or a mixed, parallel/serial sensing architecture. Examples of these architectures are discussed in C. Calligaro et al. “A New Serial Sensing Approach for Multistorage,” in Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing. 1995, pp. 21-26, and C. Calligaro et al. “Mixed Sensing Architecture for 64-Mbit 16-level-cell Non-Volatile Memories,” in Proc. 1996 IEEE Int. Conf. Innovative Systems on Silicon, pp. 133-140. 
   Nevertheless, both the serial sensing architecture and the mixed, parallel/serial sensing architecture typically use more than two comparison steps because of the serial nature of comparisons. Accordingly, this may lead to a slower operational speed than may be achieved using a parallel sensing architecture. 
   Current mode techniques may be advantageous for use in providing sensing functionality in multi-level memories. Current-mode circuitry may be particularly useful for providing relatively high-speed sensing functionality with a low-voltage power supply. (See, e.g., E. Seevinck et al. “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs,” in IEEE J. of SSC, Vol. 26, Apr. 1991, pp. 525-535.) Current-mode sensing circuits have been used in multi-level non-volatile sense amplifiers as described, for example, in C. Calligaro et al. “A High-Speed Sensing Scheme for Multi-Level Non-Volatile Memories,” in Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing. 1997, pp. 96-99, E. Seevinck et al. “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs,” in IEEE J. of SSC, Vol. 26, Apr. 1991, pp. 525-535, and P.Y. Chee et al. “High-Speed Hybrid Current-Mode Sense Amplifier for CMOS SRAMs,” in Electron Letters, Apr. 23, 1992, Vol. 28, No. 9, pp. 871-873. 
   SUMMARY OF THE INVENTION 
   According to some embodiments of the present invention, a circuit comprises a first pre-amp circuit that provides a first pre-amp current and a second pre-amp circuit that provides a second pre-amp current. A first threshold circuit is configured to generate a first output signal responsive to a difference between a variable current and the first pre-amp current. A second threshold circuit is configured to generate a second output signal responsive to a difference between the variable current and the second pre-amp current. One of the branches of a differential interpolation circuit comprises a first transistor that is connected in a current mirror configuration with the first pre-amp circuit. The first transistor has a width/length ratio equal to the product nk, where n&lt;1 and k is an arbitrary number. A second transistor is connected in a current mirror configuration with the second pre-amp circuit. The second transistor has a width/length ratio equal to the product mk, where m&lt;1 and n+m is about 1. The interpolation circuit is configured to generate a third output signal responsive to a difference between the variable current and an interpolated reference current given by n * (first pre-amp current)+m * (second pre-amp current). 
   In further embodiments of the present invention, first, second, and third detection circuits are connected to the first threshold circuit, second threshold circuit, and interpolation circuit, respectively, and are responsive to the first, second, and third output signals, respectively. 
   In still further embodiments of the present invention, the interpolation circuit further comprises third and fourth transistors that are connected in a current mirror configuration with at least one of the first and second pre-amp circuits. 
   In still further embodiments of the present invention, the first transistor, second transistor, third transistor and fourth transistor are NMOS transistors, and the interpolation circuit further comprises a fifth PMOS transistor having a drain terminal connected to a gate terminal. The drain terminal is further connected to drain terminals of the third and fourth transistors. The interpolation circuit further comprises a sixth PMOS transistor having a gate terminal connected to the gate terminal of the fifth PMOS transistor and a drain terminal connected to drain terminals of the first and second transistors. 
   Although described above primarily with respect to circuit embodiments of the present invention, it will be understood that the present invention may also be embodied as methods of operating a circuit. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other features of the present invention will be more readily understood from the following detailed description of specific embodiments thereof when read in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram that illustrates a conventional parallel sensing architecture; 
       FIG. 2  is a block diagram that illustrates interpolating sense amplifier circuits and methods of operating the same in accordance with some embodiments of the present invention; 
       FIGS. 3 and 4  are graphs that conceptually illustrate interpolating sense amplifiers and methods of operating the same, in accordance with some embodiments of the present invention; 
       FIGS. 5A and 5B  are circuit schematics that illustrate pre-amp and threshold circuits that may be used in interpolating sense amplifiers, in accordance with some embodiments of the present invention; 
       FIG. 6  illustrates an interpolation circuit that may be used as a threshold circuit in accordance with some embodiments of the present invention; 
       FIG. 7  illustrates an interpolation circuit in accordance with some other embodiments of the present invention that comprises fewer transistors than the interpolation circuit of  FIG. 6 ; 
       FIG. 8  is a circuit schematic that illustrates interpolating sense amplifiers and methods of operating the same, in accordance with some embodiments of the present invention, in which two interpolator circuits are used; 
       FIGS. 9A ,  9 B, and  9 C illustrate operations of interpolating sense amplifiers and methods of operating the same in which four outputs are obtained from two reference currents by sweeping an input current across a range spanning the reference current values; and 
       FIG. 10  is a circuit schematic that illustrates pre-amp and threshold circuits that may be used in interpolating sense amplifiers, in accordance with some embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like numbers refer to like elements throughout the description of the figures. It will also be understood that when an clement is referred to as being “connected” or “coupled” to another clement, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
   According to some embodiments of the present invention, sense amplifier circuits use signal interpolation, which may provide relatively high-speed operation, without consuming excessive chip area or dissipating excessive amounts of power.  FIG. 2  is a block diagram that illustrates interpolating sense amplifier circuits and methods of operating the same in accordance with some embodiments of the present invention. As shown in  FIG. 2 , a sense amplifier circuit  20  comprises a plurality of pre-amp circuits  22 , a plurality of interpolator circuits  24 , and a plurality of output circuits  26 . Only one interpolator circuit  24  for each pair of reference signals (Ir 1  through Ir 2   n −1) is shown in  FIG. 2 ; however, additional interpolated reference signals may be generated based on existing reference signals from the pre-amp stage for comparison with an input signal by using more interpolators. Compared with a conventional parallel sensing architecture shown in  FIG. 1 , sense amplifier circuits, in accordance with some embodiments of the present invention, may maintain ( 2   n −1) output levels while reducing the number of pre-amps and pre-amp reference signals. 
     FIGS. 3 and 4  are graphs that conceptually illustrate interpolating sense amplifiers and methods of operating the same, in accordance with some embodiments of the present invention. Referring now to  FIG. 3 , an interpolated reference signal litr may be generated by summing the halves of reference signals I 1  and I 2 , which may be provided at the pre-amp stage. The three signals I 1 , litr, and I 2  may then be used to compare with an input signal fin. Referring now to  FIG. 4 , multiple interpolated reference signals, i.e., litr 1  and litr 2 , may be generated by summing fractions of the reference signals I 1  and I 2  , where litr 1 =⅔I 1 +⅓I 2  and litr 2 +⅓I 1 +⅔I 2 . Embodiments in which multiple interpolated reference signals are derived from a pair of reference signals may be referred to as differential interpolating architectures. Thus, with the four reference signals—I 1 , I 2 , litr 1 , and litr 2 —four compared outputs can be created. 
     FIGS. 5A and 5B  are circuit schematics that illustrate pre-amp and threshold circuits that may be used in interpolating sense amplifiers, in accordance with some embodiments of the present invention. As shown in  FIG. 5A , a pre-amp circuit comprises two transistors N 1  and N 2  that are configured as shown and that generate an output current Iin′ and an output reference current Ir 1 ′ responsive to respective input currents. A threshold circuit comprises four transistors P 1 , P 2 , N 3 , and N 4  that are configured as shown. The threshold circuit is coupled to an inverter I 1 , which is used as an output circuit or output stage. Similarly,  FIG. 5B , illustrates a pre-amp circuit that comprises two transistors N 5  and N 6  that are configured as shown and that generate an output current Iin and an output reference current Ir 2 ′ responsive to respective input currents. A threshold circuit comprises four transistors P 3 , P 4 , N 7 , and N 8  that are configured as shown. The threshold circuit is coupled to an inverter I 2 , which is used as an output circuit or output stage. The NMOS transistors N 1 , N 2 , N 3 , N 4 , N 5 , N 6 , N 7 , and N 8 , have a same width/length ratio, which is given by k. The PMOS transistors P 1 , P 2 , P 3 , and P 4  have a same width/length ratio, which is given by k′. The circuits of  FIGS. 5A and 5B  may be used to generate output signals based on a comparison of the current Iin′ with the reference currents Ir 1 ′ and Ir 2 ′, respectively. 
     FIG. 6  illustrates an interpolation circuit that may be used as a threshold circuit in accordance with some embodiments of the present invention. As shown in  FIG. 6 , an interpolation circuit comprises transistors N 10 , N 11 , N 12 , N 13 , P 10 , and P 11 , which are configured as shown. The threshold circuit is coupled to an inverter I 10 , which is used as an output circuit or output stage. The gate terminals of the transistors N 10 , N 11 , N 12 , and N 13  are coupled to the nodes indicated on the pre-amp circuits of  FIGS. 5A and 5B . As discussed above, the transistors N 1 , N 2 , N 5 , and N 6  have a width/length ratio of k. In  FIG. 6 , however, transistor N 10  has a width/length ratio of ⅔k, transistor N 11  has a width/length ratio of ⅓k, transistor N 12  has a width/length ratio of ⅔k, and transistor N 13  has a width/length ratio of ⅓k. Transistors N 10  and N 11  are configured in a current-mirror configuration with transistors N 1  and N 5 , respectively, from  FIGS. 5A and 5B . Transistors N 12  and N 13  are configured in a current-mirror configuration with transistors N 2  and N 6 , respectively, from the  FIGS. 5A and 5B . Because the transistors N 12  and N 13  have width/length ratios of ⅔k and ⅓k, respectively, they may provide an interpolated reference current litr 1 =⅔r 1 ′+⅓Ir 2 ′. Thus, the interpolation circuit is configured to generate an output signal responsive to a difference between a variable current and an interpolated reference current given by n * (first pre-amp current)+m * (second pre-amp current), where n+m is about 1 in some embodiments and equal to 1 in particular embodiments. 
     FIG. 7  illustrates an interpolation circuit in accordance with some other embodiments of the present invention that comprises fewer transistors than the interpolation circuit of FIG.  6 . As shown in  FIG. 7 , the interpolation circuit comprises transistors P 20 , P 21 , N 20 , and N 21 , which are configured as shown. The threshold circuit is coupled to an inverter I 20 , which is used as an output circuit or output stage. The gate terminals of the transistors P 20 , P 21 , N 20 , and N 21  are coupled to the nodes indicated on the pre-amp circuits of  FIGS. 5A and 5B . Transistor P 20  has a width/length ratio of ⅔k′, transistor P 21  has a width/length ratio of ⅓k′, transistor N 20  has a width/length ratio of ⅔k, and transistor N 21  has a width/length ratio of ⅓k. 
     FIG. 8  is a circuit schematic that illustrates interpolating sense amplifiers and methods of operating the same, in accordance with some embodiments of the present invention, in which two interpolator circuits are used.  FIGS. 9A ,  9 B, and  9 C are a SPICE simulation of the circuit shown in FIG.  8 . Referring now to  FIG. 8 , there are two pre-amplifier circuits  1  and  2 , two threshold circuits  1  and  2 , and two interpolator circuits  1  and  2 . The configuration of a current-mode pre-amp and a differential to single-end amp threshold circuit is commonly used for parallel sensing. Four of these types of circuits are commonly used in conventional sense amplifier circuits for four level sensing as described, for example, in C. Calligaro et al. “A High-Speed Sensing Scheme for Multi-Level Non-Volatile Memories,” in Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing. 1997, pp. 96-99 and E. Seevinck et al. “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs,” in IEEE J. of SSC, Vol. 26, Apr. 1991, pp. 525-535, the disclosures of which are hereby incorporated herein by reference. Advantageously, by using current-mode interpolation as described above, only two of these types of circuits may be used to create four outputs, in accordance with some embodiments of the present invention. As shown in  FIG. 8 , four level sensing can be provided by using two pairs of current sources, sinks, and inverters. 
   NMOS transistors N 30 , N 31 , N 37 , N 38 , N 32 , and N 39  have a width/length ratio given by k. PMOS transistors P 30  and P 35  have a width/length ratio given by k′. Transistor P 31  has a width/length ratio of ⅔k′, transistor N 33  has a width/length ratio of ⅔k, transistor P 33  has a width/length ratio of ⅓k′, transistor N 35  has a width/length ratio of ⅓k, transistor P 32  has a width/length ratio of ⅓k′, transistor N 34  has a width/length ratio of ⅓k, transistor P 34  has a width/length ratio of ⅔k′, and transistor N 36  has a width/length ratio of ⅔k.  FIG. 9A  is a graph of the input current Iin being varied so as to cross the two reference current values Iref 1  and Iref 2 .  FIG. 9B  is a graph of the output voltage levels at the threshold circuit  1 , the interpolator circuit  1 , the interpolator circuit  2 , and the threshold circuit  2 .  FIG. 9C  is a graph of the output voltage levels labeled in FIG.  8 . 
     FIGS. 9A ,  9 B, and  9 C illustrate operations of interpolating sense amplifiers and methods of operating the same in which four outputs arc obtained from two reference currents by sweeping an input current across a range spanning the reference current values. Two differential-single outputs and two outputs based on interpolated referenced currents can be obtained at a low-voltaic power supply of about 2.5 volts. Four digital outputs may be generated via inverters. 
     FIG. 10  is a circuit schematic that illustrates pre-amp and threshold circuits that may be used in interpolating sense amplifiers, in accordance with some embodiments of the present invention. As shown in  FIG. 10 , a pre-amp circuit comprises two transistors N 40  and N 41  that are configured as shown and that generate an output current Iin′ and an output reference current Ir 1 ′ responsive to respective input currents. A threshold circuit comprises four transistors P 40 , P 41 , N 42 , and N 43  that are configured as shown. The threshold circuit is coupled to an inverter I 40 , which is used as an output circuit or output stage. Three switches S 1 , S 2 , and S 3  are also configured as shown. To obtain a reference level for the threshold circuit, switch S 1  may be opened and switches S 2  and S 3  may be closed so that the threshold circuit is driven solely by the reference current Iref. In this way, a “zero” or baseline level may be determined as a reference level on the capacitor C 1 . During normal operation, switch S 1  may be closed and switches S 2  and S 3  may be opened. 
   In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention, All such variations and modifications are intended to be included herein within the scope of the present invention. It will be understood that the scope of the present invention is not limited by the claims, but is intended to encompass the present disclosure, including structural and functional equivalents thereof