Abstract:
Circuitry includes a balanced amplifier and bias adjustment circuitry. The bias adjustment circuitry is coupled to the balanced amplifier and is configured to measure an RF termination voltage across an output termination impedance of the balanced amplifier and adjust a bias voltage supplied to the balanced amplifier based on the RF termination voltage. Notably, the RF termination voltage is proportional to a voltage standing wave ratio (VSWR) of the balanced amplifier, and thus enables an accurate measurement thereof. By using the RF termination voltage to adjust a bias voltage supplied to the balanced amplifier, overvoltage and/or thermally stressing conditions of the balanced amplifier as a result of high VSWR may be avoided while simultaneously avoiding the need for large or expensive isolation circuitry.

Description:
FIELD OF THE DISCLOSURE 
       [0001]    The present disclosure relates to bias circuitry for balanced amplifiers. 
       BACKGROUND 
       [0002]    Balanced amplifiers are widely used in the amplification of radio frequency (RF) signals due to their exceptional performance in many practical situations. Specifically, balanced amplifiers often exhibit, good input and output return losses, and better stability when compared to single-ended amplifiers. An exemplary conventional balanced amplifier  10  is shown in  FIG. 1 . The conventional balanced amplifier  10  includes an RF input node  12 , an RF output node  14 , an input termination impedance  16 , an output termination impedance  18 , a first amplifying device  20 , a second amplifying device  22 , an input quadrature coupler  24 , and an output quadrature coupler  26 . The input quadrature coupler  24  includes a first input node  28  coupled to the input termination impedance  16 , a second input node  30  coupled to the RF input node  12 , a first output node  32  coupled to an input of the first amplifying device  20 , and a second output node  34  coupled to an input of the second amplifying device  22 . The output quadrature coupler  26  includes a first input node  36  coupled to an output of the first amplifying device  20 , a second input node  38  coupled to an output of the second amplifying device  22 , a first output node  40  coupled to the RF output node  14 , and a second output node  42  coupled to the output termination impedance  18 . 
         [0003]    In operation, the conventional balanced amplifier  10  is configured to receive an RF input signal RF_IN at the RF input node  12  and produce an amplified RF output signal RF_OUT at the RF output node  14 . Specifically, the conventional balanced amplifier  10  is configured to receive an RF input signal RF_IN with a phase angle of zero degrees at the RF input node  12 . As the RF input signal RF_IN enters the input quadrature coupler  24 , the signal is split into an in-phase portion and a quadrature portion. The in-phase portion of the RF input signal RF_IN is equal to the RF input signal RF_IN over the square root of two (0.707 multiplied by the RF input signal RF_IN) at a phase angle of zero degrees, while the quadrature portion of the RF input signal RF_IN is equal to the RF input signal RF_IN over the square root of two (0.707 multiplied by the RF input signal RF_IN) at a phase angle of −90 degrees. The in-phase portion of the RF input signal RF_IN is delivered to and amplified by the second amplifying device  22 , while the quadrature portion of the RF input signal RF_IN is delivered to and amplified by the first amplifying device  20 . The resulting amplified in-phase portion of the RF input signal RF_IN is delivered to the second input node  38  of the output quadrature coupler  26 , while the resulting amplified quadrature portion of the RF input signal RF_IN is delivered to the first input node  36  of the output quadrature coupler  26 . 
         [0004]    The output quadrature coupler  26  shifts the amplified in-phase portion of the RF input signal RF_IN at the second input node  38  by −90 degrees and delivers both the amplified and phase-shifted in-phase portion of the RF input signal RF_IN and the amplified quadrature portion of the RF input signal RF_IN (with an unchanged phase) to the RF output node  14 . Accordingly, the amplified and phase-shifted in-phase portion of the RF input signal RF_IN and the amplified quadrature portion of the RF input signal RF_IN each have a phase equal to −90 degrees, and therefore combine to produce an RF output signal RF_OUT equal to the gain of the amplifying devices multiplied by the RF input signal RF_IN at a phase angle of −90 degrees. Further, the quadrature output coupler  28  shifts the quadrature portion of the RF input signal RF_IN by −90 degrees and delivers both the amplified and phase-shifted quadrature portion of the RF input signal RF_IN and the amplified in-phase portion of the RF input signal RF_IN (with an unchanged phase) to the output termination impedance  18 . Since the amplified and phase-shifted quadrature portion of the RF input signal RF_IN and the amplified in-phase portion of the RF input signal RF_IN are of equal magnitude and are also 180 degrees out of phase with one another, these signals effectively cancel. 
         [0005]    As the load provided at the RF output node  14  changes to become mismatched with the output termination impedance  18 , for example, due to a change in the impedance of an antenna connected to the RF output node  14 , the balanced amplifier experiences what is known as “load pull” due to a high voltage standing wave ratio (VSWR). Specifically, the magnitude of the amplified in-phase portion of the RF input signal RF_IN and the amplified quadrature portion of the RF input signal RF_IN become mismatched, and therefore the signals no longer cancel at the output termination impedance  18  as discussed above. This results in a buildup of voltage across the output termination impedance  18 , which may eventually result in damage to the output termination impedance  18  as well as damage to the first amplifying device  20  and/or second amplifying device  22 . Further, this results in thermal stress on the first amplifying device  20  and/or the second amplifying device  22 , reduced efficiency, and higher voltage swings at the device terminals. 
         [0006]    In an effort to protect the conventional balanced amplifier  10  from damage due to high VSWR conditions, external isolators have been used in conjunction with the output termination impedance  18 .  FIG. 2  shows the conventional balanced amplifier  10  including an external isolator  44  coupled in series with an additional output termination impedance  45  between the RF output node  14  and ground. The external isolator  44  may be a circulator, which may consume a large amount of area and further add expense to the surrounding circuitry of the conventional balanced amplifier  10 . Further, the external isolator  44  may degrade the efficiency of the conventional balanced amplifier  10 . As shown in  FIG. 2 , the conventional balanced amplifier  10  may be integrated onto a semiconductor die, represented by the dashed box  46  shown in  FIG. 2 . However, the external isolator  44  cannot be integrated onto the semiconductor die  46  due to the size thereof. Accordingly, there is a need for a balanced amplifier that is capable of safely dealing with high VSWR conditions while simultaneously being efficient and compact. 
       SUMMARY 
       [0007]    The present disclosure relates to bias circuitry for balanced amplifiers. In one embodiment, circuitry includes a balanced amplifier and bias adjustment circuitry. The bias adjustment circuitry is coupled to the balanced amplifier and is configured to measure an RF termination voltage across an output termination impedance of the balanced amplifier and adjust a bias voltage supplied to the balanced amplifier based on the RF termination voltage. Notably, the RF termination voltage is proportional to a voltage standing wave ratio (VSWR) of the balanced amplifier, and thus enables an accurate measurement thereof. By using the RF termination voltage to adjust a bias voltage supplied to the balanced amplifier, damage to the balanced amplifier as a result of high VSWR conditions may be avoided while maintaining the performance of the balanced amplifier and adding minimal additional area to the balanced amplifier. 
         [0008]    In one embodiment, the balanced amplifier and the bias adjustment circuitry are monolithically integrated on a semiconductor die. 
         [0009]    In one embodiment, the bias adjustment circuitry comprises termination voltage amplification circuitry configured to receive and amplify the RF termination voltage and bias adjustment voltage generation circuitry configured to generate a direct current (DC) bias adjustment voltage based on the amplified RF termination voltage. 
         [0010]    In one embodiment, the bias adjustment voltage generation circuitry comprises a bias adjustment input node, a bias adjustment output node, a load resistor coupled between the bias adjustment input node and ground, a bias adjustment capacitor coupled between the bias adjustment input node and an intermediary bias adjustment node, a first bias adjustment diode including an anode coupled to the intermediary bias adjustment node and a cathode coupled to ground, a second bias adjustment diode including a cathode coupled to the intermediary bias adjustment node and an anode, a first bias adjustment resistor coupled between the anode of the second bias adjustment diode and the bias adjustment output node, and a second bias adjustment resistor coupled between the bias adjustment output node and a nominal bias voltage input node. 
         [0011]    In one embodiment, the termination voltage amplification circuitry comprises a variable gain amplifier. 
         [0012]    In one embodiment, the balanced amplifier comprises an RF input node and an RF output node, an input termination impedance and an output termination impedance, a first amplifying device, a second amplifying device, an input quadrature coupler, and an output quadrature coupler. The input quadrature coupler includes a first input node coupled to the input termination impedance, a second input node coupled to the RF input node, a first output node coupled to an input node of the first amplifying device, and a second output node coupled to an input node of the second amplifying device. The output quadrature coupler includes a first input node coupled to an output node of the first amplifying device, a second input node coupled to an output node of the second amplifying device, a first output node coupled to the RF output node, and a second output node coupled to the output termination impedance. 
         [0013]    Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         [0014]    The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
           [0015]      FIG. 1  is a schematic representation of a conventional balanced amplifier. 
           [0016]      FIG. 2  is a schematic representation of a conventional balanced amplifier including isolation circuitry. 
           [0017]      FIG. 3  is a schematic representation of a radio frequency (RF) transmit chain according to one embodiment of the present disclosure. 
           [0018]      FIG. 4  is a schematic representation of a balanced amplifier including bias adjustment circuitry according to one embodiment of the present disclosure. 
           [0019]      FIG. 5  is a schematic representation of a balanced amplifier including bias adjustment circuitry according to an additional embodiment of the present disclosure. 
           [0020]      FIG. 6  is a schematic representation of a balanced amplifier including bias adjustment circuitry according to an additional embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0022]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0023]    It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
         [0024]    Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
         [0025]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0026]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0027]      FIG. 3  shows a radio frequency (RF) transmit chain  48  according to one embodiment of the present disclosure. The RF transmit chain  48  includes modulation circuitry  50 , a first driver stage amplifier  52 , a second driver stage amplifier  54 , a final driver stage amplifier  56 , an antenna  58 , and control circuitry  60 . The modulation circuitry  50  is coupled to an input of the first driver stage amplifier  52 . An output of the first driver stage amplifier  52  is coupled to an input of the second driver stage amplifier  54 . An output of the second driver stage amplifier  54  is coupled to an input of the final driver stage amplifier  56 , the output of which is in turn coupled to the antenna  58 . The control circuitry  60  may be connected to one or more of the first driver stage amplifier  52 , the second driver stage amplifier  54 , and the final driver stage amplifier  56  in order to control the operation thereof. Specifically, the control circuitry  60  may be configured to control the level of a bias voltage delivered to one or more of the first driver stage amplifier  52 , the second driver stage amplifier  54 , and the final driver stage amplifier  56 , and further may be configured to control the level of bias voltage adjustment accomplished by bias adjustment circuitry coupled to one or more of the first driver stage amplifier  52 , the second driver stage amplifier  54 , and the final driver stage amplifier  56 , as will be discussed in further detail below. 
         [0028]    In operation, a baseband signal BB_IN is received at the modulation circuitry  50  of the RF transmit chain  48 , where it is modulated at a desired carrier frequency and delivered to the first driver stage amplifier  52 . The first driver stage amplifier  52  amplifies the modulated baseband signal and delivers the amplified modulated baseband signal to the second driver stage amplifier  54 . The second driver stage amplifier  54  once again amplifies the modulated baseband signal and delivers the resulting signal to the final stage amplifier  56 . The final driver stage amplifier  56  further amplifies the modulated baseband signal to a level appropriate for transmission from the antenna  58  and delivers the signal to the antenna  58 , where the signal is subsequently radiated into the surrounding environment. 
         [0029]    Although two driver stage amplifiers and one final stage amplifier are shown in the RF transmit chain  48 , any number of driver stages may be used in the RF transmit chain  48  without departing from the principles of the present disclosure. Further, additional components may be included in the RF transmit chain, for example, input matching circuitry, output matching circuitry, etc. may be included in the RF transmit chain  48  without departing from the principles of the present disclosure. Finally, although not explicitly described, the principles of the present disclosure may be extended to additional applications such as RF receive chains including one or more cascaded low noise amplifiers (LNAs), all of which are contemplated herein. 
         [0030]      FIG. 4  shows a balanced amplifier  62  and accompanying bias adjustment circuitry  64  according to one embodiment of the present disclosure. The balanced amplifier  62  and the bias adjustment circuitry  64  may be used as one or more of the first driver stage amplifier  52 , the second driver stage amplifier  54 , and the final driver stage amplifier  56  in the RF transmit chain  48  discussed above. The balanced amplifier  62  is substantially similar to that shown above with respect to  FIG. 1 , such that the balanced amplifier  62  includes an RF input node  66 , an RF output node  68 , an input termination impedance  70 , an output termination impedance  72 , a first amplifying device  74 , a second amplifying device  76 , an input quadrature coupler  78 , and an output quadrature coupler  80 . The input quadrature coupler  78  includes a first input node  82  coupled to the input termination impedance  70 , a second input node  84  coupled to the RF input node  66 , a first output node  86  coupled to an input of the first amplifying device  74 , and a second output node  88  coupled to an input of the second amplifying device  76 . The output quadrature coupler  80  includes a first input node  90  coupled to an output of the first amplifying device  74 , a second input node  92  coupled to an output of the second amplifying device  76 , a first output node  94  coupled to the RF output node  68 , and a second output node  96  coupled to the output termination impedance  72 . 
         [0031]    The bias adjustment circuitry  64  includes termination voltage amplification circuitry  98  and bias adjustment voltage generation circuitry  100 . The termination voltage amplification circuitry  98  is coupled to the second output node  96  of the output quadrature coupler  80 , such that the termination voltage amplification circuitry  98  is configured to receive and amplify the voltage across the output termination impedance  72 , which is herein referred to throughout as the “RF termination voltage.” The bias adjustment voltage generation circuitry  100  is coupled to an output of the termination voltage amplification circuitry  98 , such that the bias adjustment voltage generation circuitry  100  is configured to receive an amplified version of the RF termination voltage. The bias adjustment voltage generation circuitry  100  is further coupled to a nominal bias voltage input node  102 , such that the bias adjustment voltage generation circuitry  100  is configured to receive a nominal bias voltage V_NB. Finally, the bias adjustment voltage generation circuitry  100  is coupled to each one of the first amplifying device  74  and the second amplifying device  76 . Accordingly, the bias adjustment voltage generation circuitry  100  is configured to generate a direct current (DC) bias adjustment voltage based on the amplified RF termination voltage, and deliver the bias adjustment voltage to each one of the first amplifying device  74  and the second amplifying device  76 . The control circuitry  60  may be coupled to the termination voltage amplification circuitry  98 , the bias adjustment voltage generation circuitry  100 , or both, in order to control one or more parameters of the bias adjustment circuitry  64 , as discussed in further detail below. 
         [0032]    As discussed above, as the voltage standing wave ratio (VSWR) of the balanced amplifier  62  increases, due to, for example, a changing impedance of an antenna coupled to the RF output node  68 , a proportional RF termination voltage builds across the output termination impedance  72 . Notably, the bias adjustment circuitry  64  utilizes this proportional relationship of the VSWR of the balanced amplifier  62  to that of the RF termination voltage in order to adjust a bias voltage of the first amplifying device  74  and the second amplifying device  76  and thereby protect the first amplifying device  74  and the second amplifying device  76  in the event of a high VSWR condition. Specifically, when the RF termination voltage measured across the output termination impedance  72  is above a predetermined threshold, the bias adjustment voltage generation circuitry  100  generates a bias adjustment voltage sufficient to turn the first amplifying device  74  and the second amplifying device  76  off, thereby protecting the first amplifying device  74  and the second amplifying device  76  from damage due to high VSWR conditions. Measuring the VSWR of the balanced amplifier  62  using the RF termination voltage is achieved practically for free, as it impacts the operation of the balanced amplifier  62  minimally, if at all. 
         [0033]    In one embodiment, the balanced amplifier  62  and the bias adjustment circuitry  64  are monolithically integrated on a semiconductor die. An exemplary semiconductor die is shown as the dashed box  104  shown in  FIG. 4 . As discussed in further detail below, the design of the bias adjustment circuitry  64  is such that it can be integrated onto a relatively small area of a semiconductor die at a low cost, thereby saving valuable area in a device incorporating the balanced amplifier  62  and bias adjustment circuitry  64 . 
         [0034]      FIG. 5  shows details of the termination voltage amplification circuitry  98  and the bias adjustment voltage generation circuitry  100  according to one embodiment of the present disclosure. The termination voltage amplification circuitry  98  includes a variable gain amplifier  106 . The variable gain amplifier  106  may receive and amplify the RF termination voltage across the output termination impedance  72  such that the resulting signal is suitable for processing by the bias adjustment voltage generation circuitry  100 . Notably, the input impedance of the variable gain amplifier  106  may be exceptionally high in order to mitigate the effect of the bias adjustment circuitry  64  on the functionality of the balanced amplifier  62 . Further, the variable gain amplifier  106  may be coupled to the control circuitry  60 , such that the control circuitry  60  is capable of adjusting the gain of the variable gain amplifier  106 . Adjusting the gain of the variable gain amplifier  106  results in an increase or decrease in the predetermined threshold at which the bias adjustment circuitry  64  turns off the first amplifying device  74  and the second amplifying device  76 . Accordingly, the control circuitry  60  may adjust the sensitivity of the bias adjustment circuitry  64  to the VSWR of the balanced amplifier  62 . 
         [0035]    The bias adjustment voltage generation circuitry  100  includes a bias adjustment input node  108 , a bias adjustment output node  110 , an intermediary bias adjustment node  112 , a load resistor R 1 , a first bias adjustment resistor R 2 , a second bias adjustment resistor R 3 , a first bias adjustment capacitor C 1 , a first bias adjustment diode D 1 , and a second bias adjustment diode D 2 . The load resistor R 1  is coupled between the bias adjustment input node  108  and ground. The first bias adjustment capacitor C 1  is coupled between the bias adjustment input node  108  and the intermediary bias adjustment node  112 . The first bias adjustment diode D 1  includes an anode coupled to the intermediary bias adjustment node  112  and a cathode coupled to ground. The second bias adjustment diode D 2  includes a cathode coupled to the intermediary bias adjustment node  112  and an anode. The first bias adjustment resistor R 2  is coupled between the anode of the second bias adjustment diode D 2  and the bias adjustment output node  110 , and the second bias adjustment resistor R 3  is coupled between the nominal bias voltage input node  102  and the bias adjustment output node  110 . Finally, the bias adjustment output node  110  is connected to the input of each one of the first amplifying device  74  and the second amplifying device  76 . 
         [0036]    In operation, when the amplified RF termination voltage provided by the termination voltage amplification circuitry  98  is below a predetermined threshold, a voltage sampled across the first bias adjustment capacitor C 1  is insufficient to place the first bias adjustment diode D 1  into a forward conduction mode of operation. Accordingly, the compact rectification circuit formed by the first bias adjustment diode D 1 , the second bias adjustment diode D 2 , the first bias adjustment resistor R 2 , and the second bias adjustment resistor R 3  is turned off. A nominal bias voltage provided at the nominal bias voltage input node  102  is thus provided as a bias adjustment voltage through the second bias adjustment resistor R 3  to the first amplifying device  74  and the second amplifying device  76 . Notably, the first amplifying device  74  and the second amplifying device  76  are configured such that they are active (i.e., conducting) when they receive the nominal bias voltage. 
         [0037]    When the amplified RF termination voltage is raised above the threshold voltage of the first bias adjustment diode D 1 , the compact rectification circuit formed by the first bias adjustment diode D 1 , the second bias adjustment diode D 2 , the first bias adjustment resistor R 2  and the second bias adjustment resistor R 3  is turned on, and thus produces an average or DC current (I DC ), which flows from the nominal bias voltage input node  102  to ground through the second bias adjustment resistor R 3 , the first bias adjustment resistor R 2 , the second bias adjustment diode D 2 , and the first bias adjustment diode D 1 . This in turn reduces the nominal bias voltage at each one of the first amplifying device  74  and the second amplifying device  76  and begins to turn off the first amplifying device  74  and the second amplifying device  76 . 
         [0038]    As discussed above, the RF termination voltage is proportional to the VSWR experienced by the balanced amplifier  62 . Accordingly, the bias adjustment circuitry  64  is configured to adjust the bias voltage to the first amplifying device  74  and the second amplifying device  76  based on the VSWR of the balanced amplifier  62 , turning off the first amplifying device  74  and the second amplifying device  76  when the VSWR experienced by the balanced amplifier  62  is above a predetermined threshold. Turning off the balanced amplifier  62  during high VSWR conditions effectively protects the first amplifying device  74  and the second amplifying device  76  from high power dissipation and thus breakdown conditions, thereby increasing the reliability of the balanced amplifier  62  and reducing the risk of failure. When the high VSWR condition subsides, the RF termination voltage is reduced, thereby turning off the compact rectification circuit and restoring the bias voltage provided to the first amplifying device  74  and the second amplifying device  76  to its nominal value. Accordingly, the first amplifying device  74  and the second amplifying device  76  are placed into an active mode of operation (i.e., conducting), thereby restoring the balanced amplifier  62  to its normal state of operation. 
         [0039]    In one embodiment, the first bias adjustment resistor R 2  and the second bias adjustment resistor R 3  are adjustable. Further, the first bias adjustment resistor R 2  and the second bias adjustment resistor R 3  may be connected to the control circuitry  60  such that the control circuitry  60  can adjust the resistance of the first bias adjustment resistor R 2  and the second bias adjustment resistor R 3 . Accordingly, an additional way for the control circuitry  60  to adjust the sensitivity of the bias adjustment circuitry  64  to the VSWR of the balanced amplifier  62  is provided. Although the control circuitry  60  is shown separately from the bias adjustment circuitry  64  and off the semiconductor die  104 , the control circuitry  60  may be part of the bias adjustment circuitry  64  and integrated onto the semiconductor die  104  in some embodiments. 
         [0040]      FIG. 6  shows details of the first amplifying device  74  and the second amplifying device  76  according to one embodiment of the present disclosure. The first amplifying device  74  includes a first input matching network  114 , a first amplifying transistor  116 , and a first output matching network  118 . The first input matching network  114  is connected to a gate contact (G) of the first amplifying transistor  116 . The first output matching network  118  is connected to a drain contact (D) of the first amplifying transistor  116 , which is in turn connected to a supply voltage V CC . A source contact (S) of the first amplifying transistor  116  is coupled to ground. Similarly, the second amplifying device  76  includes a second input matching network  120 , a second amplifying transistor  122 , and a second output matching network  124 . The second input matching network  120  is coupled to a gate contact (G) of the second amplifying transistor  122 . The second output matching network  124  is coupled to a drain contact (D) of the second amplifying transistor  122 , which is in turn coupled to the supply voltage V CC . A source contact (S) of the second amplifying transistor  122  is coupled to ground. 
         [0041]    The quadrature portion of the RF input signal RF_IN is delivered to the first input matching network  114  along with the bias adjustment voltage. The quadrature portion of the RF input signal RF_IN from the first output node  86  of the input quadrature coupler  78  and the bias adjustment voltage from the bias adjustment circuitry  64  are separately delivered to the first input matching network  114  and combined through one or more matching components such that the gate contact (G) of the first amplifying transistor  116  receives a combination of the two signals. Similarly, the in-phase portion of the RF input signal RF_IN from the second output node  88  of the input quadrature coupler  78  and the bias adjustment voltage from the bias adjustment circuitry  64  are separately delivered to the second input matching network  120  such that the gate contact (G) of the second amplifying transistor  122  receives a combination of the two signals. 
         [0042]    The first amplifying transistor  116  and the second amplifying transistor  122  may be field-effect transistor (FET) devices. For example, the first amplifying transistor  116  and the second amplifying transistor  122  may be metal-oxide semiconductor field-effect transistors (MOSFETs). In other embodiments, the first amplifying transistor  116  and the second amplifying transistor  122  may be high electron mobility transistors (HEMTs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), or the like. The particular configuration of the first input matching network  114 , the first output matching network  118 , the second input matching network  120 , and the second output matching network  124  may vary substantially between embodiments. In general, any suitable impedance matching network may be used for the first input matching network  114 , the first output matching network  118 , the second input matching network  120 , and the second output matching network  124 . 
         [0043]    Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.