Abstract:
Disclosed are devices, among which is a device that includes a transistor and a contact. The transistor includes two terminals that may be formed in respective legs. The contact includes a first portion extending vertically, and a second portion extending perpendicularly with respect to the first portion. The second portion is wider than the first portion.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 12/130,825, filed on May 30, 2008. 
    
    
     BACKGROUND 
     1. Field of Invention 
     Embodiments of the invention relate generally to electronic devices and, more specifically, in certain embodiments, to methods of forming connections to data cells. 
     2. Description of Related Art 
     Many types of electronic devices have data cells. Typically, the data cells each include a data element (e.g., a memory element, an imaging element, or other device configured to output data, such as various kinds of sensors) and, in some instances, an access device, such as a transistor or diode. Generally, the access device controls access to the data element, and the data element outputs signals indicative of stored or sensed data. 
     Often the data elements are arranged in an array, e.g., generally in rows and columns. Data cells within the array are accessed, e.g., written to or read from, through circuitry near the periphery of the array. For instance, sense amplifiers or other sensing circuitry are often positioned adjacent arrays of data cells for reading data. Similarly, address decoders, e.g., row and column address decoders, are often disposed adjacent the array for addressing particular data cells or groups of data cells. 
     Devices in the array often are structured differently from structures in the periphery. Array transistors may be formed from materials that are different from the materials used to form transistors in the periphery, and the dimensions, e.g., thickness, of materials in these devices may be different. In some devices, differences between the array and periphery are accommodated with multiple lithography steps. For instance, a first photolithography tool may pattern a first material in the array, and a second, different photolithography tool, may pattern a second, different material in the periphery. In this way, different design tradeoffs, e.g., size versus signal quality, may be made between the array devices and the periphery devices. 
     These differences, however, can increase the cost of electronic devices. Each lithography step adds costs, and certain lithography steps are particularly expensive. Typically, manufacturing lines use several different generations of lithography equipment, ranging from more advanced, newer equipment to less capable, older equipment. The newer equipment is typically much more expensive, so designers strive to reduce the number of manufacturing steps that use the newer lithography equipment. Patterning array and periphery devices, however, is often done with separate lithography steps on the newer equipment, adding to the cost of electronic devices. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIGS. 1-20  illustrate an example of a process for forming an array of transistors; and 
         FIGS. 21-52  illustrate an example of a process for forming connections to the array of  FIGS. 1-20  and for forming a gate of periphery transistors. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates a first step in an embodiment of a process for forming an array of transistors. The process may begin with providing a substrate  110 . The substrate  110  may include semiconductive materials such as single-crystal or poly-crystalline silicon, gallium arsenide, indium phosphide, or other materials with semiconductor properties. Alternately, or additionally, the substrate  110  may include a non-semiconductor body on which an electronic device may be constructed, e.g., a body such as a plastic or ceramic work surface. The term “substrate” encompasses these structures in a variety of stages of manufacture, including an unprocessed whole wafer, a partially-processed whole wafer, a fully-processed whole wafer, a portion of a diced wafer, or a portion of a diced wafer in a packaged electronic device. 
     The substrate  110  may include an upper doped region  112  and a lower doped region  114 . The depth of the upper doped region  112  may be generally uniform over a substantial area of the substrate  110 , and the upper doped region  112  may be doped differently from the lower doped region  114 . For example, the upper-doped region  112  may include an n+ material and the lower-doped region  114  may include a p− material or vise versa. 
     Next, several films may be formed on the substrate  110 , as illustrated by  FIG. 2 . A pad oxide  116  may be formed on the upper doped region  112 . The pad oxide  116  may have a thickness less than 300 Å, e.g., less than or equal to about 80 Å may be useful. The pad oxide  116  may be formed with a variety of techniques. For instance, it may be grown by exposing the substrate  110  to oxygen, e.g., in a diffusion furnace, or it may be deposited with atomic-layer deposition (ALD), chemical-vapor deposition (CVD), or other processes. A stop body (e.g., a layer)  118  may be formed on the pad oxide  116  with, for example, CVD. The stop body  118  may include a nitride, such as silicon nitride, and it may have a thickness less than 300 Å, e.g., about 95 Å may be useful, but like the other structures described herein, the stop body  118  is not limited to these dimensions or materials. A sacrificial body  120  may be formed on the stop body  118 . The sacrificial body  120  may be made of polysilicon and it may have a thickness between about 500 Å and about 2,000 Å, e.g., about 1000 Å may be useful. The sacrificial body  120  may be formed with CVD or other appropriate processes. A lower masking body  122  may be formed on the sacrificial body  120 . The lower masking body  122  may be made of an oxide and it may have a thickness between about 500 Å and about 2,000 Å, e.g., about 1000 Å may be useful. The lower masking body  122  may be formed with CVD, a spun-on-dielectric process, or other processes. Finally, an upper masking body  124  may be formed on the lower masking body  122 . The upper masking body  124  may be made of carbon or other materials formed with CVD or other processes, and it may have a thickness between about 1000 Å and abut 3000 Å, e.g., about 2000 Å may be useful. 
     Next, a column mask  126  may be formed, as illustrated by  FIG. 3 . (The term “column” does not refer to any particular horizontal direction on the substrate  110  other than a direction that is different from the direction that subsequently-introduced rows extend.) The column mask  126  may include a pattern of lines that define masked regions having a width  128  and exposed regions having a width  130 . The widths  128  and  130  may be generally equal to each other and each generally equal to the lithographic-resolution limit (e.g., the photolithographic-resolution limit, or minimum feature size), referred to as “F.” The column mask  126  may have a pitch  132  (e.g., a distance over which a pattern repeats) that is generally equal to 2 F. The lines formed by the column mask  126  may be generally straight, generally parallel to each other, and may generally extend in the Y-direction. These lines may be generally continuous and generally uniform in the Y-direction. In other embodiments, though, the lines formed by the column mask  126  may have other shapes, e.g., they may undulate (e.g., up and down, left and right, or both), they may vary in width in the Y-direction, or they may be formed from a plurality of shorter segments. 
     After forming the column mask  126 , a column hard mask  134  may be formed, as illustrated by  FIG. 4 . The column hard mask  134  may be formed by generally-anisotropically etching (e.g., with a directional plasma etch) the portion of the upper masking body  124  and the portion of the lower masking body  122  that are disposed under the region not covered by the column mask  126 . In some embodiments, the etch may stop on or in the sacrificial body  120 . 
     Next, the column mask  126  may be removed, and the column spacers  136  may be formed on the sidewalls of the column hard mask  134 , as illustrated by  FIG. 5 . The column spacers  136  may be formed by depositing a generally conformal film (e.g., a film that is of generally uniform thickness on both vertical and horizontal structures) and, then, anisotropically etching that film to remove it from horizontal surfaces, leaving material disposed against generally vertical surfaces on the substrate  110 . The column spacers  136  may be made of an oxide, and they may have a width  138  that is less than 100 nm, e.g., less than or equal to about 36 nm. The column spacers  136  may narrow the area exposed by the column hard mask  134  to a width  140  that is less than or equal to F, e.g., generally equal to or less than ¾ F, ½ F, or ¼ F. 
     Next, as illustrated by  FIG. 6 , column isolation trenches  142  may be formed. The column isolation trenches  142  may be formed by generally anisotropically etching the exposed regions between the column spacers  136 . The column isolation trenches  142  may have a width  141  that corresponds to (e.g., is generally equal to or is proportional to) the width  140 . The column isolation trenches  142  may generally extend in the Y-direction and may be generally parallel to each other and generally straight. The cross-sectional shape of the column isolation trenches  142  may be generally uniform in the Y-direction. In some embodiments, the column isolation trenches  142  may have a depth  144  that is between about 500 Å and about 5000 Å, e.g., about 2500 Å. 
     After forming the column isolation trenches  142 , they may be filled partially or entirely with a dielectric  146 , as illustrated by  FIG. 7 . The dielectric  146  may be made of a variety of materials, such as an oxide, and it may be lined with a variety of liner films (not shown), such as an oxide liner and a nitride liner. The dielectric  146  may be formed with a variety of processes, such as a high-density plasma CVD process. In some embodiments, prior to forming the dielectric  146 , the bottom of the column isolation trenches  142  may be implanted or diffused with a dopant (not shown) selected to further electrically isolate structures on opposing sides of the column isolation trenches  142 . 
     Next, the substrate  110  may be planarized, as illustrated by  FIG. 8 . Planarizing the substrate  110  may include etching the substrate  110  or polishing the substrate with chemical-mechanical planarization (CMP). Planarization may include removing both the upper masking body  124  and the lower masking body  122 , and planarization may stop on or in the sacrificial body  120 . Additionally, an upper portion of the dielectric  146  may be removed. 
     Next, the sacrificial body  120  may be partially or entirely removed, as illustrated by  FIG. 9 . Removing the sacrificial body  120  may include wet etching or dry etching the substrate  110  with an etch that selectively etches the sacrificial body  120  without removing a substantial portion of the exposed dielectric  146 , i.e., with an etch that is selective to the sacrificial body  120 . An etch is said to be “selective to” a material if the etch removes that material without removing a substantial amount of other types of material exposed on the substrate. After removing the sacrificial body  120 , generally vertical projections  148  formed by the dielectric  146  may extend from the substrate  110 . 
     Next, a second spacer  150  may be formed on the sidewalls of the generally vertical projections  148  of dielectric  146 , as illustrated by  FIG. 10 . As with the previously-described column spacers  136 , the second column spacers  150  may be formed by depositing a generally conformal film on the substrate  110  and anisotropically etching the film until the film is generally removed from the horizontal surfaces, leaving the material on the vertical surfaces on the substrate  110 . The second column spacers  150  may be made of the same material as the dielectric  146 , e.g., an oxide, or they may be made of a different material. The second column spacers  150  may have a width  152  that is less than or generally equal to 100 nm, e.g., less than or generally equal to 36 nm. The spacers  150  may define a width  154  between adjacent spacers  150  that is generally less than or equal to 1 F, ¾ F, ½ F, or ¼ F. 
     After forming the second group of column spaces  150 , an intra-device trench  152  may be formed, as illustrated by  FIG. 11 . The intra-device trench  152  may be formed by generally anisotropically etching the exposed regions between the second column spacers  150 . The intra-device trenches  152  may be generally parallel to each other and the column isolation trenches  142 , and they may generally extend in the Y-direction. The intra-device trenches  152  may have a depth  154  that is both less than the depth  144  ( FIG. 6 ) of the column isolation trenches  142  and greater than the depth of the upper doped region  112 . 
     Next, a dielectric  156  may be formed, as illustrated by  FIG. 12 . The dielectric  156  may be formed with a thickness that produces an overburden  158 , increasing the likelihood that the intra-device trenches  152  are filled. For example, the dielectric  156  may have a thickness less than about 800 Å, e.g., less than or equal to about 400 Å. The dielectric  156  may include or be formed primarily with tetra-ethyl-ortho silane (TEOS), e.g., with TEOS CVD, or other appropriate dielectric materials. The dielectric  156  may be densified after being formed by heating the substrate  110  to drive volatile compounds from the dielectric  156 . 
     After forming the dielectric  156 , the substrate  110  may be planarized, as illustrated by  FIG. 13 . The substrate  110  may be planarized with CMP, an etch-back process (e.g., by depositing a sacrificial planarizing material and then etching through the sacrificial planarizing material and into underlying structures), or other appropriate processes. The stop body  118  ( FIG. 2 ) may function as a planarization stop, impeding removal of material from the upper doped region  112  and the pad oxide  116 . After planarization, the material from the stop body  118  remaining on the substrate  110  may be removed, e.g., with a wet etch that stops in the pad oxide  116  or the upper doped region  112 . 
     Next, a row mask  160  may be formed, as illustrated by  FIG. 14 . The row mask  160  may be generally perpendicular to the column mask  126  ( FIG. 4 ). The row mask  160  may be formed with photoresist or it may be a hard mask, for example, and it may be patterned with photolithography or other lithographic processes, e.g., nano-imprint lithography or electron-beam lithography. For example, the row mask  160  may be formed by patterning a body of amorphous carbon that is formed on the substrate  110 . The amorphous carbon may be formed with a thickness less than about 3000 Å, e.g., a thickness less than or equal to about 2000 Å. The row mask  160  may define masked regions having a width  162  and exposed regions having a width  164 . In some embodiments, the row mask  160  may be formed with a sub-photolithographic process, e.g., a sidewall-spacer process, a resist-reflow process, or a line-width thinning process. The widths  162  or  164  may be generally equal to or less than F, ¾ F, or ½ F. The row mask  160  may define a repeating pattern of lines with a pitch  166 , or in some embodiments, the pattern may be interrupted by other structures. The masked regions of the row mask  160  may be generally straight, generally parallel to one another, and may generally extend in the X-direction. In other embodiments, the masked regions of the row mask  160  may undulate side to side or up and down, or they may be segmented. 
     Next, row trenches  168  may be formed, as illustrated by  FIG. 15 . The row trenches  168  may define fin rows  170  disposed under the masked region of the row mask  160 . The row trenches  168  may be formed with a dry etch that etches the upper doped region  112 , the lower doped region  114 , the dielectric  146 , and the dielectric  156  at generally the same rate. The row trenches  168  may have a depth  172  that is greater than the depth of the intra-device trenches  152  ( FIG. 11 ) and less than a depth of the column isolation trenches  142  ( FIG. 11 ). The depth  172  may be less than about 3000 Å, e.g., equal to or less than about 1400 Å. 
     A gate dielectric  174  may be formed in the row trenches  168 , as illustrated by  FIG. 16 . The gate dielectric  174  may be deposited, grown, or otherwise formed, and it may substantially or entirely cover the exposed portions of the upper doped region  112  and the lower doped region  114 . The gate dielectric  174  may include a variety of dielectric materials, such as oxide (e.g., silicon dioxide), oxynitride, or high-dielectric constant materials like hafnium dioxide, zirconium dioxide, and titanium dioxide. The gate dielectric  174  may have a thickness less than about 60 Å, e.g., a thickness equal to or less than about 40 Å. 
     Next, gates  176  and  178  may be formed on either side of the fin rows  170 , as illustrated by  FIG. 17 . The gates  176  and  178  may connect to one another, e.g., by wrapping around the ends (not shown) of the fin rows  170 , or they may be electrically independent. The gates  176  and  178  may partially or substantially entirely overlap the upper doped region  112 . The gates  176  and  178  may be sidewall spacers formed by depositing a conductive film on the substrate  110  and, then, anisotropically etching the conductive film until the conductive film is generally removed from horizontal surfaces, leaving conductive material disposed against generally vertical surfaces. For example, the gates  176  and  178  may include TiN, Ru, or other appropriate conductive materials. In some embodiments, after depositing the conductive material, but before etching the material to form spacers, a protective body may be formed on the conductive material. Examples of a protective body include a high-aspect-ratio-process (HARP) oxide formed on the conductive material. The conductive material may be less than about 400 Å thick, e.g., less than or equal to about 250 Å thick, and the protective body may be less than about 200 Å thick, e.g., equal to or less than about 150 Å. If a protective body is used, the protective body may be anisotropically etched, e.g., dry etched, to expose generally horizontal portions of the conductive material, and the exposed portions of the conductive material may then be dry etched or wet etched, e.g., with an SC1 etch for less than 10 minutes, e.g., generally equal to or less than five minutes. After removing the exposed portions of the conductive material, the remaining portion of the protective body  118  may be removed with another etch that selectively removes the protective body, while leaving a substantial portion of the conductive material disposed against the sidewalls of the fin rows  170 . 
     After forming the gates  176  and  178 , a dielectric  180  may be formed on the substrate  110 , as illustrated by  FIG. 18 . The dielectric  180  may be formed with an overburden  182  to increase the likelihood of covering the gates  176  and  178  over a substantial portion of the substrate  110 . The dielectric  180  may include an oxide formed with TEOS CVD or other appropriate materials. In some embodiments, the dielectric  180  is formed with a thickness of less than about 1500 Å, e.g., equal to or less than about 1000 Å. 
     Next, the substrate  110  may be planarized, as illustrated by  FIG. 19 . Planarization may include processing the substrate  110  with a CMP process, an etch-back process, or other processes that planarize. The planarization process may stop on or in the upper doped region  112 , removing the overburden  182  of the dielectric  180 . 
     As illustrated by  FIG. 19 , a plurality of transistors  184  may be formed on the substrate  110 . Each of the fin rows  170  may include a plurality of transistors  184 . The transistors  184  on a given fin row  170  may be isolated from one another by the dielectric  146 . The transistors  184  in adjacent fin rows  170  may be isolated from one another by the dielectric  180 . Each of the transistors  184  may include one or both of the gates  176  and  178  disposed on either side of the fin rows  170 . The illustrated transistors  184  may be referred to as multi-gate transistors or dual-gate transistors. Other embodiments may include transistors with more than two gates or fewer than two gates. 
       FIG. 20  illustrates the semiconductive portion of an example of a single transistor  184 . The transistor  184  includes two legs  186  and  188  separated by a notch  189  (corresponding to trench  152  in  FIG. 11 ). The distal portion of each of the legs  186  and  188  may be formed by the upper doped region  112 , and the lower portion of the legs  186  and  188  may be formed by the lower doped region  114 . The transistor  184  may generally define a fin with opposite faces  190  and  192 . 
     In operation, the transistor  184  may establish a conductive channel  194  extending between the legs  186  and  188 . This channel  194  may be formed in response to electric fields emanating from the gates  176  and  178  ( FIG. 19 ). Both of the gates  176  and  178  may be held at generally the same voltage, or they may be controlled independently. The channel  194  may extend between the upper doped region  112  of the leg  186  and the upper doped region  112  of the leg  188 , wrapping around the notch  189 . The channel  194  may include a generally horizontal component under the notch  189  and generally vertical components along each of the legs  186  and  188 . When both of the gates  176  and  178  are energized, the channel  194  may be formed adjacent both of the faces  190  and  192  of the transistor  184  or one of the faces  190  or  192 . 
       FIGS. 21-52  illustrate an example of a process for forming both connections to the transistors  184  and gates in a periphery area. As illustrated by  FIG. 21 , the above-described process may produce an array  196  and a periphery  198  on the substrate  110 . The array  196  may include a plurality of the previously described transistors  184  arranged in a pattern, e.g., a rectangular or hexagon lattice. The periphery  198  may generally surround the array  196  or be disposed near a portion of the array  196 , e.g., near one or more sides of the array  196 . At the stage illustrated by  FIG. 21 , the periphery  198  may include precursor structures for a variety of devices, such as sense amplifiers, address decoders, and drivers. In some embodiments, the periphery  198  may be doped differently from the array  196 . For example, the periphery  198  may be masked when the upper doped region  112  is formed, and separate doping steps may dope portions of the periphery  198 . The periphery  198  may include isolation trenches  199  that may isolate subsequently-formed transistors in the periphery  198 . The isolation trenches  199  may be patterned, etched, and filled generally simultaneously with the column isolation trenches  142 , or they may be formed partially or substantially entirely separately. 
     A buffer material  200  and a stop material  202  may be formed, as illustrated by  FIG. 22 . The buffer material  200  may be an oxide, e.g., an oxide formed with TEOS CVD, and the stop material  202  may be a nitride formed with CVD or other appropriate processes. The buffer material  200  may have a thickness less than about 200 Å, e.g., a thickness equal to or less than about 50 Å, and the stop material  202  may have a thickness less than about 500 Å, e.g., a thickness equal to or less than about 300 Å. 
     A mask  204  may be formed on the stop material  202 , as illustrated by  FIG. 23 . The mask  204  may cover the array  196  and leave a portion or substantially all of the periphery  198  exposed. The mask  204  may be a soft mask or a hard mask formed with photolithography or other patterning techniques. For example, the mask  204  may be formed with photolithography equipment that is older or less capable than the photolithography equipment used to form a certain other features on the substrate  110 , such as at the column mask  126  ( FIG. 3 ) or the row mask  160  ( FIG. 14 ). The mask  204  may be formed with an I-line photolithography tool (e.g., a photolithography tool having a light-source with a wavelength generally equal to or greater than 365 nm) or a G-line photolithography tool (e.g., a photolithography tool having a light source with a wavelength equal to or greater than 436 nm). In comparison, the masks  126  and  160  may be formed with a deep-UV photolithography tool (e.g., a photolithography tool having a light source with a wavelength generally equal to or less than 300 nm, a 248 nm, 193 nm, or 157 nm). The present technique is not limited to masks formed with these photolithography tools. For instance, the masks  126  and  160  may be formed with a deep-UV photolithography tool, and the mask  204  may be formed with a more advanced form of this tool, such as a deep-UV photolithography tool configured for immersion lithography or double patterning. 
     Next, the exposed portion of the stop material  202  and the mask  204  may be removed, as illustrated by  FIG. 24 . The stop material  202  may be removed with a wet etch or a dry etch that is selective to the stop material  202 . The stop material  202  may remain over the array  196 , and the buffer material  200  may be exposed in the periphery  198 . 
     Next, a lower conductive material  206 , an upper stop material  208 , a sacrificial material  210 , and an implant barrier  212  may be formed, as illustrated by  FIG. 25 . The lower conductive material  206  may be made of or include a conductive material, e.g., p+ doped polysilicon. The lower conductive material  206  may have a thickness less than about 1200 Å, e.g., a thickness equal to or less than about 700 Å. Making the lower conductive material  206  from doped polysilicon may facilitate certain subsequent higher temperature processing, as polysilicon is believed to be more resistant to oxidation than some other conductors. For instance, metals may oxidize at temperatures typically used to anneal the substrate  110  to heal etch damage to the crystal structure of the substrate  110 . Indeed, the film stack illustrated by  FIG. 25 , which as explained below, after etching, generally defines the dimensions of the gates in the periphery  198 , may be generally free of metal. In other embodiments, the lower conductive material  206  may include a metal, such as tungsten, and liners such as titanium nitride and titanium. 
     The upper stop material  208  may include or be made of a material selected to function as an etch stop. That is, the choice of the upper stop material  208  may be made in view of the etch used to etch the sacrificial material  210 . The upper stop material  208  may be selected to be relatively resistant to this etch, slowing this etch and increasing the margin for over etching the sacrificial material  210 . For example, the upper stop material  208  may be an oxide or a nitride, and the upper stop material  208  may have a thickness less than about 200 Å, e.g., a thickness equal to or less than about 100 Å. Thus, the upper stop material  208  may facilitate relatively tight control of the vertical dimension of etches through the film stack illustrated by  FIG. 25 . 
     The sacrificial material  210  may be a material selected to etch relatively anisotropically, e.g., a material that tends to form relatively vertical sidewalls when etched. For example, the sacrificial material  210  may include doped or undoped polysilicon. The sacrificial material  210  may have a thickness less than about 2500 Å, e.g., a thickness equal to or less than about 1500 Å. Making the sacrificial material  210  from polysilicon is believed to facilitate formation of sidewalls that are relatively vertical as compared to sidewalls produces by etches through other materials, such as oxide. Relatively vertical sidewalls are believed to facilitate more precise control of device dimensions. With highly sloped sidewalls, film thickness variations may affect the width of the bottom of trenches. In contrast, relatively vertical sidewalls may cause the film thickness to have less of an effect on the width of features near the bottom of the film being etched. Further, sidewall spacers may be formed on the relatively vertical sidewalls with more margin for over etch in horizontal areas, thereby reducing the likelihood of undesirable stringers between sidewalls spacers. Thus, the sacrificial material  210  may facilitate relatively precise control of the horizontal dimensions of the structures formed by etches through this film stack. 
     The implant barrier  212  may include an amorphous material, such as an oxide or amorphous carbon, and it may have a thickness equal to or less than about 1000 Å, e.g., a thickness equal to or less than about 500 Å. The implant barrier may impede implanted ions from penetrating the sacrificial material  210 , as some crystal grains in the sacrificial material  210  may align with the implant beam and may be relatively permeable to the implanted ions. It should be noted, though, that not all embodiments offer all of the advantages of the film stack illustrated by  FIG. 25 , and some embodiments offer only some of its advantages or other advantages. 
     Next, a mask  214  may be formed, as illustrated by  FIG. 26 . The mask  214  may be a soft mask or a hard mask formed with photolithography or other patterning techniques known in the art. The mask  214  may include a pattern of lines that define a mask width  216 , an exposed width  218 , and a pitch  220  in the array  196 . The pitch  220  may be generally equal to (or an integer multiple of) the pitch  132  of the column mask  126  described above with reference to  FIG. 3 . The lines of the mask  214  that define the masked width  216  may generally extend in the Y-direction and may generally be aligned with one of the legs  186  or  188  of each of the transistors  184  ( FIG. 20 ). The masked width  216  may be less than the exposed width  218  and may be less than or generally equal to F, ¾ F, or ½ F. The mask  214  may also define a masked region  222  in the periphery  198 . 
     The mask  214  may be formed by more advanced photolithography equipment relative to the photolithography equipment used to form other structures on the substrate  110 . For instance, the mask  214  may be formed by the photolithography equipment used to form the masks  126  ( FIG. 3) and 160  ( FIG. 14 ), equipment which may have a minimum feature size (F) that is smaller than the minimum feature size of the photolithography equipment used to form the mask  204  ( FIG. 23 ). F may be smaller than or generally equal to about 120 Å, 100 Å, 80 Å, or 50 Å. The masks  214 ,  126 , and  160  may be formed with deep-UV photolithograph equipment, and the mask  204  may be formed with I-line photolithography equipment. 
     The masked region  222  may define a gate of a subsequently formed transistor in the periphery  198 . Thus, in some embodiments, the mask  214  may serve dual purposes: defining the gates in the periphery  198  and, as explained below, data lines in the array  196 . Because the mask  214  may serve these dual purposes, the throughput of the more advanced photolithography equipment is economized, as dimensions of several structures may be defined simultaneously. It should be noted, though, that not all embodiments offer this advantage, and some embodiments offer other advantages. 
     After forming the mask  214 , the substrate  110  may be etched, as illustrated by  FIG. 27 . The etch may be generally anisotropic, and it may stop on or in the stop material  202  or the buffer material  200 . The etch may form generally linear recesses  224  in the array  196  and the recess  226  in the periphery  198 . The recesses  224  may be disposed over one of the legs  186  or  188  of the transistors  184  ( FIG. 20 ). The etch may be performed in two or more stages. For example, the implant barrier  212  and the sacrificial material  210  may be etched first, using the upper stop material  208  as an etch stop. The portion of the etch that consumes the sacrificial material  210  may be generally selective to polysilicon and selective against oxide. Using the upper stop material  208  as an etch stop is believed to form a relatively uniform etch front near this layer and produce relatively uniform vertical dimensions within the linear recesses  224  and the recess  226 . Next, the upper stop material  208  and the lower conductive material  206  may be etched, stopping on or in the stop material  202  or the buffer material  200 . As mentioned above, forming the sacrificial material  210  and the lower conductive material  206  from polysilicon is believed to facilitate formation of the recesses  224  and  226  with relatively vertical sidewalls. 
     The etch illustrated by  FIG. 27  may define a gate  227  in the periphery  198 . The gate  227  may be made from the lower conductive material  206 , and it may be generally free of metal. After this etch, the substrate  110  may be annealed in a furnace, e.g., at a temperature greater than 400 degrees C., e.g., greater than or equal to 800 about degrees C. 
     Next, spacer materials  228  and  230  may be formed, as illustrated by  FIG. 28 . The spacer material  228  may be a nitride deposited with CVD, and it may have a thickness less than about 300 Å, e.g., a thickness equal to or less than about 100 Å. The spacer material  230  may be an oxide deposited with CVD, and it may have a thickness less than about 400 Å, e.g., less than or equal to about 200 Å. The spacer material  230  may substantially fill the recesses  224  ( FIG. 27 ) in the array  196 . 
     The spacer materials  228  and  230  may form spacers (identified with the same reference numbers as the material from which they are formed), as illustrated by  FIG. 29 . The spacers  228  and  230  may be formed by generally anisotropically etching the substrate  110 . After forming the spacers  228  and  230 , a portion of the spacer material  230  may cover all or a portion of the spacer material  228  within the recesses  224  in the array  196 . The spacer etch may expose the top of the implant barrier  212 . 
     Next, the spacer material  230  may be removed, as illustrated by  FIG. 30 . The spacer material  230  may be removed with a wet or dry etch that is selective to the spacer material  230 . A portion of the spacer material  228  may remain along the bottom of the recesses  224  in the array, while a substantial portion of the periphery  198  may be not covered by the spacer material  228 . Thus, the spacer material  228  may be patterned differently in the array  196  and the periphery  198  without using an additional photomask. 
     A liner  232  may be formed, as illustrated by  FIG. 31 . The liner  232  may be a nitride deposited with CVD or other appropriate processes. The liner  232  may have a thickness less than about 300 Å, e.g., a thickness equal to or less than about 150 Å. 
     Next, a dielectric  234  may be formed, as illustrated by  FIG. 32 . The dielectric  234  may be an oxide or other appropriate material deposited with CVD or it may be a spun-on dielectric, for example. The dielectric  234  may be densified by heating the substrate  110  to drive volatile compounds from the dielectric  234 . The dielectric  234  may be deposited to a thickness selected to generally planarize the substrate  110 , e.g., a thickness at least greater than the depth of the recesses  224  ( FIG. 31 ). 
     The substrate  110  may be planarized, as illustrated by  FIG. 33 . Planarizing may include polishing the substrate  110  with CMP or etching the substrate  110  with an etch that is generally nonselective to the exposed materials on the substrate  110 . Planarization may stop on or in the implant barrier  212  or on or in the upper conductor  210 , for example. In some embodiments, planarization may stop in the implant barrier  212 , and the exposed portion of the implant barrier  212  may be removed with a wet or dry etch. 
     Next, the upper conductor  210  and the upper stop material  208  may be removed, as illustrated by  FIG. 34 . The upper conductor  210  may be removed with an etch, e.g. a wet etch, that is selective to the upper stop material  208 , and the upper stop material  208  may be removed with a different etch that is selective to the lower conductor  206 . One or both of these etches may remove a portion of the dielectric  234  as well. 
     A mask  236  may be formed on the substrate  110 , as illustrated by  FIG. 35 . The mask  236  may expose the array  196  and cover a portion or substantially all of the periphery  198 . The mask  236  may be a hard mask or a soft mask formed with photolithography or other patterning techniques. The mask  236  may be formed with photolithography equipment that is older or less capable than the photolithography equipment that was used to form certain other features on the substrate  110 , such as at the mask  214 . In some embodiments, the mask  236  may be formed with an I-line photolithography tool (e.g., a photolithography tool having a light-source with a wavelength generally equal to or greater than 365 nm) or a G-line photolithography tool (e.g., a photolithography tool having a light source with a wavelength equal to or greater than 436 nm), and the mask  214  ( FIG. 26 ) may be formed with a deep-UV photolithography tool (e.g., a photolithography tool having a light source with a wavelength generally equal to or less than 300 nm, a 248 nm, 193 nm, or 157 nm). The present technique, however, is not limited to the present generation of photolithography tools. As photolithography advances, and deep-UV tools are usurped with more capable systems, the mask  236  may be formed with a deep-UV photolithography system, and the mask  214  may be formed with the more advanced system, e.g., a system with a smaller minimum feature size (F), such as a system configured for double-patterning, immersion lithography, or a smaller-wavelength light source. 
     Next, the portion of the lower conductor  206  that is not covered by the mask  236  may be removed, as illustrated by  FIG. 36 . This portion of the lower conductor  206  may be removed with a dry or wet etch that is selective to the lower conductor  206 . The etch may stop on or in the stop material  202 . 
     The mask  236  may be removed, and a liner material  238  may be formed on the substrate  110 , as illustrated by  FIG. 37 . The mask  236 , like many of the other masks described herein, may be removed with an etch that is selective to the mask  236  or by combusting the mask  236  with oxygen in a furnace, for example. The liner material  238  may be a nitride, an oxide, or other appropriate material, and it may be formed with CVD or other processes. The liner material  238  may have a thickness less than about 500 Å, e.g., a thickness equal to or less than about 300 Å. 
     Next, the portion of the liner material  238  that is disposed on generally horizontal surfaces may be removed to form spacers (identified with the same reference number  238  as the material from which they are formed), as illustrated by  FIG. 38 . The liner material  238  may be etched with a generally anisotropic dry etch that is selective to the liner material  238 , e.g., a dry etch that is selective to nitride. The resulting spacer formed by the liner material  238  may narrow the recesses  242  to a width that is less than or generally equal to F, ¾ F, or ½ F. Each recess  242  may be a generally linear recess extending in the Y-direction and exposing the upper doped region  112  of one of the legs  186  or  188  ( FIG. 20 ) of the transistors  184  ( FIG. 20 ). The exposed portion of the upper doped region  112  may be implanted, e.g., with phosphorus or other dopants, to reduce contact resistance with subsequently formed conductors. The recess  240  may extend to the lower conductive material  206  in the periphery  198 . Although the recesses  240  and  242  may extend to different structures  206  and  188 , the dimensions and position of the recesses  242  and  240  may be generally defined by a single mask  214 . The other masks  204  and  236  formed by less expensive lithography equipment may determine which structures defined by the mask  214  connect to the upper doped region  112  or the lower conductive material  206 , allowing the mask  214  to serve two purposes. 
     A conductive material  244  may be formed on the substrate  110 , as illustrated by  FIG. 39 . The conductive material  244  may be doped polysilicon or a metal, such as titanium, or other appropriate materials. In some embodiments, the conductive material  244  includes a titanium nitride liner (not shown) and a titanium liner deposited with collimated physical-vapor deposition. The conductive material  244  may also include tungsten deposited on the titanium and titanium nitride liners. The tungsten may be less than about 400 Å thick, e.g., less than or equal to about 200 Å. 
     Next, the substrate  110  may be planarized, as illustrated by  FIG. 40 . Planarizing may include polishing the substrate with CMP or etching the substrate  110  with an etch-back process (e.g., by forming a sacrificial planarizing material, such as a spun on glass or resist, on the substrate  110  and etching the sacrificial material and the conductive material  244 ). Planarization may stop on or in the dielectric  234 , forming a conductive plate  246  and data lines  248  that may be isolated from one another. The data lines  248  may extend in the Y-direction and connect to one of the legs  186  or  188  of a plurality of transistors  184  ( FIG. 20 ). For instance, each data line  248  may connect to one leg  188  or  186  of one transistor  184  in each fin row  170  ( FIG. 19 ). The data lines  248  may be isolated from one another by the dielectric  234 , the liner material  238 , the liner  232 , the spacer material  228 , the remaining buffer material  200 , and the remaining stop material  202 . In other embodiments, the data lines  248  may not extend generally straight in the Y-direction, e.g., they may undulate, vary in width, or be segmented. 
     Next, a dielectric material  250 , a stop material  252 , and a sacrificial material  254  may be formed, as illustrated by  FIG. 41 . The dielectric material  250  may be an oxide or other appropriate material deposited with CVD or other processes, such as a spun-on-dielectric process. The dielectric  250  may have a thickness less than about 2000 Å, e.g., a thickness equal to or less than about 1000 Å or about 500 Å. The stop material  252  may be a nitride or other appropriate material selected to function as a stop layer for subsequent etches. The stop material  252  may have a thickness less than about 2500 Å, e.g., a thickness equal to or less than about 1500 Å or about 1000 Å. The sacrificial material  254  may include amorphous carbon deposited with CVD, PVD, or other appropriate processes, and it may have a thickness less than or equal to about 4000 Å. 
     A mask  256  may be formed on the sacrificial material  254 , as illustrated by  FIG. 42 . The mask  256  may generally cover the periphery  198  and define a plurality of openings  258  over the array  196 . The openings  258  may have a generally right-circular-cylindrical shape, a generally right-elliptical-cylindrical shape, or other shape. The openings  258  may have a diameter  260  that is generally equal to or less than F, and the openings  258  may be generally centered over one of the legs  186  or  188  of each of the transistors  184  ( FIG. 20 ). The mask  256  may be a hard mask or a soft mask formed with photolithography or other patterning techniques. 
     Next, the portions of the conductive material  254  and the stop material  252  disposed under the openings  258  may be removed to form recesses  259 , as illustrated by  FIG. 43 . These materials  252  and  254  may be removed with a wet etch or a dry etch that is generally anisotropic. The etch may stop on or in the dielectric material  250 . 
     The mask  256  may be removed, and a spacer  262  may be formed in the recesses  259 , as illustrated by  FIG. 44 . The spacer  262  may be formed by depositing a layer of spacer material and then generally anisotropically etching the spacer material to remove the spacer material from generally horizontal surfaces, leaving the spacers  262  in the recesses  259 . The spacers  262  may be made of a conductive material, such as doped polysilicon or a metal, for example, or a non-conductive material. The spacer material may be deposited with a thickness less than about 800 Å, e.g., a thickness equal to or less than about 400 Å. The spacer  262  may narrow the diameter of the openings  258  to a narrower diameter  264  that may be generally equal to or less than F, ¾ F, or ½ F. 
     Next, the substrate  110  may be etched, as illustrated by  FIG. 45 . The substrate  110  may be etched with a generally anisotropic dry etch. During the etch, the sacrificial material  254  and the spacers  262  may mask portions of the substrate  110  as the narrowed recesses  259  are extended into the substrate  110  to the buffer material  200 . 
     The substrate  110  may be etched to further remove the portion of the buffer material  200  disposed at the bottom of the recesses  259 , as illustrated by  FIG. 46 . The buffer material  200  may be removed with a hydrofluoric acid clean or other wet or dry etch. The etch may attack portions of the side wall of the recesses  259 , such as the dielectric  250  and the dielectric  234 , and widen portions of the recesses  259 . The etch may expose the surface of the upper doped region  112  ( FIG. 20 ) of one of the legs  186  or  188  of each of the transistors  184  ( FIG. 20 ). 
     A conductive material  266  may then be formed on the substrate  110 , as illustrated by  FIG. 47 . The conductive material  266  may be doped polysilicon (e.g., n+ doped polysilicon), a metal, or other appropriate materials, and it may have a thickness less than 700 Å, e.g. a thickness less than or generally equal to 400 Å. The conductive material  266  may extend to the bottom of the recesses  259  ( FIG. 46 ). The conductive material  266  may be generally free of metal, and the area where the conductive material  226  meets the upper doped region  112  may be generally free of silicides. Keeping this area generally free of silicides is believed to reduce current leakage. It should be noted, though, that not all embodiments offer this advantage, and some embodiments offer other advantages. 
     Next, the substrate  110  may be planarized, as illustrated by  FIG. 48 . Planarizing may include polishing the substrate  110  with CMP or etching the substrate with an etch-back process. Planarization may stop on or in the stop material  252 , leaving a portion of the spacer material  262  and the conductive material  266  exposed. 
     The spacer material  262  and the conductive material  266  together may form a contact  268 . The contacts  268  may extend generally along the z-axis to one of the two legs  186  or  188  of each of the transistors  184  in the array  196 . In other embodiments, the contacts  268  may extend to transistors with other structures, e.g., a source or drain of a CMOS transistor with a generally horizontal channel between its source and drain. The contacts  268  may be generally cylindrical structures with a generally horizontal flange formed by the spacer material  262  and having a diameter  270 . In some embodiments, the diameter  270  may be generally equal to or less than F. The diameter  270  and a diameter  271  of the lower portion of the contacts  268  may be generally defined by a single photolithography step, and the difference between these dimensions may be generally defined by the thickness of the spacer  262 . Forming both of these dimensions  270  and  271  with a single photolithography step is believed to economize capacity of photolithography equipment. It should be noted, though, that not all embodiments offer this advantage, and some embodiments offer other advantages. 
     In the cross-section of  FIG. 48 , the contacts  268  generally have a T-shape. The spacer material  262  may enlarge the target for subsequently-formed data elements, e.g., capacitor plates, ovonic devices, or imaging devices, thereby potentially increasing the alignment margin for these structures. The spacers  268  may be generally electrically isolated from other spacers  268  on the same fin row  170  ( FIG. 19 ) and from spacers  268  on other fin rows  170 . 
     Next, a dielectric material  272  may be formed, and a mask  274  may be formed on the dielectric material  272 , as illustrated by  FIG. 49 . The dielectric material  272  may be an oxide, such as an oxide deposited with CVD. The dielectric material  272  may cover the contacts  268 . The dielectric material  272  may have a thickness less than about 2000 Å, e.g., a thickness equal to or less than about 500 Å. The mask  274  may be a soft mask or a hard mask formed with photolithography or other lithography processes. The mask  274  may include exposed regions  276  and  278  in the periphery  198 , and it may generally mask the array  196 . 
     The areas under the exposed regions  276  and  278  may be etched, as illustrated by  FIG. 50 . The etch may be a generally anisotropic dry etch, and the etch may be generally selective against the conductive plate  246 . The etch may produce an opening  280  that extends to the conductive plate  246  and an opening  282  that extends further into or to the lower doped region  214  or other portion of the substrate. 
     Next, a conductive material  284 , a hard-mask material  286 , and a mask  288  may be formed, as illustrated by  FIG. 51 . The conductive material  284  may include liners, such as titanium and titanium nitride liners (not shown) deposited with physical-vapor deposition (PVD), and tungsten or other conductive materials deposited with, for example, PVD or other processes. The hard-mask material  286  may include carbon or other materials deposited with CVD or other processes. The mask  288  may be formed with photolithography, and it  288  may generally leave the array  196  and portions of the periphery  198  exposed. 
     Next, the substrate  110  may be etched to form contacts  290  and  292 , as illustrated by  FIG. 52 . The substrate  110  may be etched with an etch that is generally anisotropic, such as a dry etch. The etch may stop on or in the dielectric  272 . The contacts  292  may connect to the gates  176  and  178  on either side of a fin row  170  ( FIG. 19 ). The contact  292  may be referred to as a “word line contact.” The contact  292  may straddle one fin row  170 , and different contacts  292  may contact to other gates  176  and  178  on other fin rows  170  ( FIG. 19 ). The contact  290  may connect to a gate stack  294  formed from the conductive plate  246  and the lower conductive material  206 . 
     While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.