Abstract:
A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed bit a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the priority benefit of Taiwan application serial no. 97106922, filed on Feb. 27, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a logic circuit structure. More particularly, the present invention relates to a bulk input current switch logic circuit. 
         [0004]    2. Description of Related Art 
         [0005]    As functions of electronic products trend to be more complicated, digital logic circuits become favourite choices for designers. Moreover, with quick development of process capability, nanometer process is implemented. In this case, processing technique originally bottlenecked development of digital circuits is now no longer the biggest problem, instead, it is the transmission speed of a conventional logic gate circuit that limits a whole circuit performance thereof. 
         [0006]      FIG. 1  is a circuit diagram illustrating a  3 -input NOR gate circuit of a conventional static logic circuit. For such conventional logic gate circuit, if input terminals A˜C are all level “0”, three P-type transistors are then turned on, so that an output V 0  has a high level “1”. If at least one of the input terminals A˜C has the high level “1”, at least one of the N-type transistors is then turned on, so that the output V 0  has a “0” level “0”. Since such logic circuit requires a set of serially connected P-type transistors (or N-type transistors), the more the input terminals are, during one output transition, the more the transistors required to be turned on. 
         [0007]      FIG. 2  is a circuit diagram illustrating a 2-input NAND gate circuit of a conventional dynamic logic circuit. Such conventional dynamic logic circuit requires a pre-charge enable signal φ. Wherein, when the pre-charge enable signal φ has the low level “0”, the output V 0  may be pre-charged to the high level “1”. When the pre-charge enable signal φ is transmitted to the high level “1”, the output V 0  is then determined according to levels of the input B and input C. If the input B and the input C are all the high level “1”, the output V 0  is then lowered to the level “0” due to turning on of the transistor. Conversely, if at least one of the input B and the input C is not the high level “1”, the output V 0  is then maintained to be the high level “1”. 
         [0008]    Next, referring to  FIGS. 3A and 3B ,  FIG. 3A  is a circuit diagram illustrating a conventional N-type transistor differential logic circuit.  FIG. 3B  is an sample diagram of a logic unit  310  of  FIG. 3A . Such conventional logic circuit may implement a differential input via input A, input B or input C, and inverted signal input Ā, input  B  or input  C . In coordination with a conventional technique of the dynamic logic circuit, a pre-charge time is controlled via the pre-charge enable signal φ. Moreover, the conventional logic circuit may further include a latch circuit (in coordination with a transistor MP 1  of an output Q, or a transistor MP 2  of an output  Q ) for further stabilizing the output of the circuit. However, the differential logic circuit also requires a set of serially connected transistor in case of multiple inputs. 
         [0009]      FIG. 4  is a circuit diagram illustrating a conventional bulk input differential logic circuit. Referring to  FIG. 4 , via a current sense amplifier composed of transistors M 2 , M 3 , M 5  and M 7 , such conventional logic circuit may sense a current I L  generated by transistors M 41 ˜M 4n  connected in parallel, and sense a current I R  generated by transistors M 81 ˜M 8n  connected in parallel, and meanwhile generate the output Q and the output  Q  according to the sensing results. The pre-charge enable signal φ and the transistors M 1  and M 6  respectively provide a pre-charge signal and a pre-charge path. The transistor M 9  provides a ground voltage during a non pre-charge period. Regardless of the number of input terminals, such conventional logic circuit only has 3 serially connected N-type transistors, and therefore a response speed of the circuit may be effectively improved. 
       SUMMARY OF THE INVENTION 
       [0010]    Accordingly, the present invention is directed to a bulk input current switch logic circuit for providing a high speed and low power logic circuit in case of multiple logic input signals. 
         [0011]    The present invention provides a bulk input current switch logic circuit including a current sense amplifier and a logic tree. The current sense amplifier includes a first transistor to a fifth transistor. A first source/drain of the first transistor is coupled to a first voltage, a gate thereof is coupled to a pre-charge enable signal. A first source/drain of the second transistor is coupled to a second source/drain of the first transistor, a gate thereof is coupled to a first output terminal, and a second source/drain thereof is coupled to a second output terminal. A first source/drain of the third transistor is coupled to the second source/drain of the first transistor, a gate thereof is coupled to the second output terminal, and a second source/drain thereof is coupled to the first output terminal. A first source/drain of the fourth transistor is coupled to the second output terminal, and a gate thereof is coupled to the first output terminal. Moreover, a first source/drain of the fifth transistor is coupled to the first output terminal, and a gate thereof is coupled to the second output terminal. 
         [0012]    Moreover, the logic tree is coupled to the current sense amplifier for generating a first current according to a first input signal and a second input signal, and generating a second current according to a third input signal and a fourth input signal. 
         [0013]    In the present invention, based on bulk inputting and in coordination with the current latch sense amplifier, all the devices may be connected in parallel to generate complementary outputs and avoid direct current power consumption. Moreover, response speed of the current latch sense amplifier is quite high. Therefore, power consumption thereof may be effectively decreased, and working speed may be effectively improved. 
         [0014]    In order to make the aforementioned embodiment accompanied with figures is described in detail below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a circuit diagram illustrating a 3-input NOR gate circuit of a conventional static logic circuit. 
           [0016]      FIG. 2  is a circuit diagram illustrating a 2-input NAND gate circuit of a conventional dynamic logic circuit. 
           [0017]      FIG. 3A  is a circuit diagram illustrating a conventional N-type transistor differential logic circuit. 
           [0018]      FIG. 3B  is an sample diagram of a logic unit of  FIG. 3A . 
           [0019]      FIG. 4  is a circuit diagram illustrating a conventional bulk input differential logic circuit. 
           [0020]      FIG. 5  is a circuit diagram illustrating an N-type bulk input current switch logic circuit according to an embodiment of the present invention. 
           [0021]      FIG. 6  is a circuit diagram illustrating a P-type bulk input current switch logic circuit according to an embodiment of the present invention. 
           [0022]      FIG. 7  and  FIG. 8  are circuit diagrams respectively illustrating an boost circuit according to an embodiment of the present invention. 
           [0023]      FIG. 9A  is a circuit diagram illustrating an equivalent circuit of the N-type boost circuit  700  during a certain period. 
           [0024]      FIG. 9B  is a circuit diagram illustrating an equivalent circuit of the N-type boost circuit  700  during another period. 
           [0025]      FIG. 9C  is a diagram illustrating a relation between an output voltage and an input voltage of the N-type boost circuit  700 . 
           [0026]      FIG. 10A  is an embodiment of an OR gate circuit formed by N-type boost circuits. 
           [0027]      FIG. 10B  is a diagram illustrating an input and output waveforms of an OR gate circuit formed by N-type boost circuits. 
           [0028]      FIG. 11A  is an embodiment of an AND gate circuit formed by P-type boost circuits. 
           [0029]      FIG. 11B  is a diagram illustrating an input and output waveforms of an AND gate circuit formed by P-type boost circuits. 
           [0030]      FIG. 12A  is a Karnaugh map of an XOR gate. 
           [0031]      FIG. 12B  is a circuit diagram illustrating an XOR gate of a bulk input current switch logic circuit according to an embodiment of the present invention. 
           [0032]      FIG. 13A  is a Karnaugh map of a multiplexer. 
           [0033]      FIG. 13B  is a circuit diagram illustrating a multiplexer of a bulk input current switch logic circuit according to an embodiment of the present invention. 
           [0034]      FIG. 14  is a schematic diagram of a pipeline structure according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0035]    First, referring to  FIG. 5 , a circuit diagram illustrating an N-type bulk input current switch logic circuit according to an embodiment of the present invention is shown. The bulk input current switch logic circuit  500  includes a current sense amplifier  510  and a logic tree  520 . The current sense amplifier  510  includes transistors M 1 ˜M 7 , and the logic tree  520  includes at least one transistor M 8  and at least one transistor M 9 . Wherein, a gate of the transistor M 1  is coupled to a pre-charge enable signal CTL, and a first source/drain thereof is coupled to a system voltage VDD. A second source/drain of the transistor M 1 , a first source/drain of the transistor M 2  and a first source/drain of the transistor M 3  are coupled to each other. A gate of the transistor M 2  and a gate of the transistor M 3  are respectively coupled to an output terminal Q 1  and an output terminal Q 2 . Moreover, a second source/drain of the transistor M 2 , the output terminal Q 2  and a first source/drain of the transistor M 4  are coupled to each other. A gate of the transistor M 4  is coupled to the output Q 1 . Similarly, a second source/drain of the transistor M 3 , the output terminal Q 1  and a first source/drain of the transistor M 5  are coupled to each other, and a gate of the transistor M 5  is coupled to the output terminal Q 2 . 
         [0036]    Gates of the transistors M 6  and M 7  are also coupled to the pre-charge enable signal CTL, and second sources/drains of the transistors M 6  and M 7  are coupled to a ground voltage GND. A difference is that a first source/drain of the transistor M 6  is coupled to the output terminal Q 2 , and a first source/drain of the transistor M 7  is coupled to the output terminal Q 1 . A first source/drain of the transistor M 8  is coupled to the second source/drain of the transistor M 4 , and a second source/drain of the transistor M 8  is coupled to the ground voltage GND. A first source/drain of the transistor M 9  is coupled to the second source/drain of the transistor M 5 , and a second source/drain of the transistor M 9  is coupled to the ground voltage GND. When a number of the transistor M 9  or the transistor M 8  exceeds one, the transistors M 8  (or the transistors M 9 ) are connected in parallel to form the logic tree  520 . Bulks and gates of the transistors M 8  (or the transistors M 9 ) are respectively receive an input signal IN 2  and an input signal IN 1  (an input signal IN 4  and an input signal IN 3 ). 
         [0037]    It should be noted that in the present embodiment, besides the transistors M 1 ˜M 3  are P-type metal-oxide-semiconductors (MOSs), the other transistors are all N-type MOSs. Moreover, regardless of the number of the input signals, only two serially connected N-type MOSs (which are the transistors M 4  and M 8  or the transistors M 5  and M 9  in the present embodiment) are applied. 
         [0038]    In the present embodiment, operation method of the circuit may be described as follows. When the pre-charge enable signal CTL is enabled (which is level “1” in the present embodiment), levels of the output terminals Q 1  and Q 2  are lowered to the ground voltage GND, i.e. level “0” due to turning on of the transistors M 7  and M 6 . Next, the pre-charge enable signal CTL is transmitted to be disable (which is transmitted to be the level “0” in the present embodiment). Now, the system voltage VDD is transmitted to the circuit via the turned on transistor M 1 . Meanwhile, the transistors M 7  and M 6  are turned off. On the other hand, the gate of the transistor M 8  receives the input signal IN 1 , and the bulk thereof receives the input signal IN 2 . Since the transistor M 8  is the N-type MOS, the input signal IN 2  has to be less than or equal to the input signal IN 1 , otherwise a current leakage path may be generated. Moreover, the transistor M 8  may provide a current channel, and a current I 1  may be generated due to a voltage difference of the input signals IN 1  and IN 2 . Correspondingly, the gate of a transistor M 9  receives the input signal IN 3 , and the bulk thereof receives the input signal IN 4 . Since the transistor M 9  is the N-type MOS, the input signal IN 4  has to be less than or equal to the input signal IN 3 , otherwise the current leakage path may be generated. Moreover, the transistor M 9  may provide the current channel, and a current  12  may be generated due to a voltage difference of the input signals IN 3  and IN 4 . 
         [0039]    In addition, the current sense amplifier  510  is used for comparing the current I 1  to the current I 2 . If the current I 1  is greater than the current I 2 , the output terminal Q 2  outputs the level “0”, and the output terminal Q 1  outputs the level “1”. Conversely, if the current I 2  is greater than the current I 1 , the output terminal Q 2  outputs the level “1”, and the output terminal Q 1  outputs the level “0”. 
         [0040]      FIG. 6  is a circuit diagram illustrating a P-type bulk input current switch logic circuit according to an embodiment of the present invention. The bulk input current switch logic circuit  600  also includes a current sense amplifier  610  and a logic tree  620 . The current sense amplifier  610  includes transistors M 1 ˜M 7 , and the logic tree  620  includes at least a transistor M 8  or at least a transistor M 9 . Coupling method of these transistors is similar to that of the aforementioned embodiment. A difference there between is that the first source/drain of the transistor M 1  is coupled to the ground voltage GND, while the second sources/drains of the transistors M 6 , M 7 , M 8  and M 9  are coupled to the system voltage VDD. Moreover, besides the transistors M 1 ˜M 3  are the N-type MOS, the other transistors are all the P-type MOS. 
         [0041]    The operation method of the circuit may be described as follows. When the pre-charge enable signal CTL is enabled (which is level “0” in the present embodiment), levels of the output terminals Q 1  and Q 2  are respectively pulled up to the system voltage VDD, i.e. the level “1” due to turning on of the transistors M 7  and M 6 . Next, the pre-charge enable signal CTL is transmitted to be disabled (which is transmitted to be the level “1” in the present embodiment). Now, the ground voltage GND is transmitted to the circuit via the turned on transistor M 1 . Meanwhile, the transistors M 7  and M 6  are turned off. On the other hand, the gate of the transistor M 8  receives the input signal IN 1 , and the bulk thereof receives the input signal IN 2 . Since the transistor MS is the P-type MOS, the input signal IN 2  has to be greater than or equal to the input signal IN 1 , otherwise a current leakage path may be generated. Moreover, the transistor M 8  may provide a current channel, and a current I 1  may be generated due to a voltage difference of the input signals IN 1  and IN 2 . Correspondingly, the gate of a transistor M 9  receives the input signal IN 3 , and the bulk thereof receives the input signal IN 4 . Since the transistor M 9  is also the P-type MOS, the input signal IN 4  has to be greater than or equal to the input signal IN 3 , otherwise the leakage channel may be generated. Moreover, the transistor M 9  may provide the current channel, and a current I 2  may be generated due to a voltage difference of the input signals IN 3  and IN 4 . 
         [0042]    In addition, the current sense amplifier  610  is used for comparing the current I 1  to the current  12 . If the current I 1  is greater than the current  12 , the current sense amplifier  610  formed by the transistors M 2 ˜M 5  may output the level  1  via the output terminal Q 2 , and output the level “0” via the output terminal Q 1 . Conversely, if the current I 2  is greater than the current I 1 , the output terminal Q 2  outputs the level “0”, and the output terminal Q 1  outputs the level “1”. 
         [0043]    It should be noted that regardless of the N-type bulk input current switch logic circuit  500  or the P-type bulk input current switch logic circuit  600 , there is a difference between the input signals IN 1  and IN 2 , or between the input signals IN 3  and IN 4 . In a general logic circuit, for a logic of the input voltage, the system voltage VDD is generally considered to be the level “1”, and the ground voltage GND is generally considered to be the level “0”. Therefore, an boost circuit has to be included for generating a voltage higher than the system voltage VDD or a voltage lower than the ground voltage GND. To fully convey the spirit of the present invention, different types of the boost circuit are described in the following content. 
         [0044]      FIG. 7  is a circuit diagram illustrating an boost circuit according to an embodiment of the present invention. The boost circuit  700  of the present embodiment is an N-type boost circuit including a capacitor  710 , switches  720  and  730  and a transistor M 10 . Wherein, a first terminal of the capacitor  710  is coupled to a first input terminal INA 1  of the boost circuit  700 . An input terminal of the switch  720  is coupled to the first input terminal INA 1  of the boost circuit  700 , and an enable terminal thereof is coupled to a second input terminal INA 2  of the boost circuit  700 . An input terminal of the switch  730  is coupled to a second terminal of the capacitor  710 , an enable terminal thereof is coupled to the second input terminal INA 2  of the boost circuit  700 , and an output terminal thereof is coupled to an output terminal of the switch  720 . Moreover, a gate of the transistor M 10  is coupled to the output terminal of the switch  730 , a first source/drain thereof and the second terminal of the capacitor  710  are coupled to an output terminal OUT of the boost circuit  700 , and a second source/drain thereof is coupled to a third voltage. It should be noted that in the present embodiment, the capacitor  710  is formed by a transistor M 11 , and the switches  720  and  730  are respectively formed by transistors M 12  and M 13 . Here, the transistors M 10  and M 13  are the N-type MOS, the transistors M 11  and M 12  are the P-type MOS, and the third voltage is the ground voltage GND. 
         [0045]    Moreover, a first source/drain, a second source/drain and a based of the transistor M 11  forming the capacitor  710  are coupled to the first/second terminal of the capacitor  710 , a gate of the transistor M 11  is coupled to the second/first terminal of the capacitor  710 . A gate of the transistor M 12  forming the switch  720  is coupled to the enable terminal of the switch  720 , a first source/drain and a base thereof are coupled to the input terminal of the switch  720 , and a second source/drain thereof is coupled to the output terminal of the switch  720 . A gate of the transistor M 13  forming the switch  730  is coupled to the enable terminal of the switch  730 , a first source/drain and a base thereof are coupled to the input terminal of the switch  730 , and a second source/drain thereof is coupled to the output terminal of the switch  730 . 
         [0046]      FIG. 8  is a circuit diagram illustrating an boost circuit according to another embodiment of the present invention. The boost circuit  800  of the present embodiment is a P-type boost circuit including a capacitor  820 , switches  810  and  830  and a transistor M 10 . Differences between the boost circuit  800  and the aforementioned boost circuit  700  are that the transistors M 10 , M 11  and M 13  are all the P-type MOS, the transistor M 12  is the N-type MOS, and the third voltage is coupled to the system voltage VDD. Moreover, it should be noted that regardless of the N-type boost circuit  700  or the P-type boost circuit  800 , the capacitors utilized therein includes any type of transistor coupling to be the capacitor, which is not limited to be the N-type MOS shown in figures. 
         [0047]    As to the operation method of the boost circuit, please refer to  FIG. 7  and  FIG. 9A .  FIG. 9A  is a circuit diagram illustrating an equivalent circuit of the N-type boost circuit  700  during a certain period. Wherein, an input terminal IN 1  of  FIG. 9A  is equivalent to the first input terminal INA 1  of  FIG. 7 . In  FIG. 7 , a voltage of the first input terminal INTA 1  has the high level “1”, and a voltage of the second input terminal INTA 2  is an inversion with that of the first input terminal INA 1 , which has the low level “0”. Therefore, the switch  720  is enabled and the switch  730  is disabled. A gate of the transistor M 10  is now electrically connected to the high level, and therefore the transistor M 10  may be considered to be a turned on switch. The first terminal of the capacitor  710  is electrically connected to the input terminal INA 1  (i.e. the high level), and the second terminal of the capacitor  710  is equivalent to being electrically connected to the ground voltage GND, and therefore the capacitor  710  is charged. In the general logic circuit, the high level is equivalent to the system voltage VDD, namely, the first terminal of the capacitor  710  is charged to the system voltage VDD, and the output terminal OUT is electrically connected to the ground voltage GND. 
         [0048]      FIG. 9B  is a circuit diagram illustrating an equivalent circuit of the N-type boost circuit  700  during another period. Now, the voltage of the first input terminal INA 1  is transmitted to be the low level “0”, and the voltage of the second input terminal INA 2  is transmitted to be the high level “1”. Now, the switch  720  is disabled, and the switch  730  is enabled. Since the voltage of the first input terminal INA 1  is transmitted to be the low level “0”, in the logic circuit, the low level “0” generally represents the ground voltage GND, i.e. 0V. Therefore, the first terminal of the capacitor  710  is momentarily coupled to the 0V, so that the second terminal of the capacitor  710  is boosted to the −VDD. The transistor M 10  functions as a diode since a gate thereof is changed to electrically connected to the second terminal of the capacitor  710 . Meanwhile, a parasitic capacitor C L  of the output terminal OUT of the boost circuit  700  is inversely charged, so that the voltage of the output terminal OUT is −V OL . Wherein, an absolute value of the voltage −V OL  of the output terminal OUT is slightly less than the system voltage VDD. 
         [0049]      FIG. 9C  is a diagram illustrating a relation between an output voltage and an input voltage of the N-type boost circuit  700 . During a period T 1 , the first input terminal INA 1  has the system voltage VDD, and according to the above description, the output terminal OUT has the ground voltage GND (=0V). During a period T 2 , since the voltage of the first input terminal INA 1  is transmitted to the ground voltage GND, the voltage of the output terminal is then boosted to −V OL . 
         [0050]    In the present embodiment, only the N-type boost circuit  700  is described, however, operation of the P-type boost circuit  800  is similar to that of the N-type boost circuit  700 . A difference there between is that the generated voltage of the output terminal OUT is between the system voltage VDD and V OH , wherein V OH  is slightly less than twice of the system voltage VDD. 
         [0051]    Moreover, a plurality of the N-type boost circuits may further form an OR gate or an NAND gate logic circuit. Referring to  FIG. 10A , an embodiment of an OR gate circuit formed by N-type boost circuits is illustrated. Such OR gate circuit may be simply implemented by connecting the output terminals of a plurality of the N-type boost circuits to form a wire OR gate. Meanwhile, a problem of voltages confliction is avoided. In the present embodiment, three N-type boost circuits A 10 ˜A 30  are applied for respectively receiving an input A, an input B, and an input C. Referring to  FIG. 10B ,  FIG. 10B  is a diagram illustrating an input and output waveforms of an AND gate circuit formed by N-type boost circuits. 
         [0052]    When the inputs A, B and C are all level “0”, since the three boost circuits are all inversely charged, an output F has the level −V OL . If at least one of the inputs A, B and C has the level “1”, for example, if the input A has the level “1”, the output terminal of the boost circuit A 10  is then pulled to the ground voltage, which is referred to as strong pull low. Such strong pull low makes the output terminals of the boost circuits A 20  and A 30  to be pulled together to the ground voltage GND. Therefore, the voltage level of the output F is then the ground voltage GND. In the output F, since the ground voltage GND is the relatively high level, it may be considered to be the level “ 1 ”, and the −V OL  then may be considered to be the low level “0”. Moreover, if the inputs A, B and C are all inverted and input to the OR gate formed by the N-type boost circuits, a logic effect of an NAND gate then may be achieved. 
         [0053]    According to a same principle as above, an AND gate or an NOR gate logic circuit then may be easily obtained via the P-type boost circuits. Referring to  FIG. 11A , an embodiment of an AND gate circuit formed by P-type boost circuits is illustrated. Such AND gate circuit may be simply implemented by connecting the output terminals of a plurality of the P-type boost circuits to form a wire AND gate. In the present embodiment, three P-type boost circuits B 10 ˜B 30  are applied. Referring to  FIG. 11B ,  FIG. 11B  is a diagram illustrating an input and output waveforms of an AND gate circuit formed by P-type boost circuits. An operation method thereof is similar to that of the OR gate circuit formed by the N-type boost circuits, and therefore the detailed description thereof will not be repeated. 
         [0054]    Here, embodiments are provided for describing the bulk input current switch logic circuit of the present invention to those skilled in the art, for a further understanding of the present invention. 
         [0055]    First, an embodiment of an XOR gate designed based on the N-type bulk input current switch logic circuit and the N-type boost circuit is provided. Referring to  FIG. 12A , a Karnaugh map of an XOR gate is illustrated. First, output results on the Karnaugh map which include “0” and “1” are circled for obtaining a “0 1” circle C 10  and a “1 0” circle C 20 . Referring to  FIG. 12B , a circuit diagram illustrating an XOR gate of a bulk input current switch logic circuit according to an embodiment of the present invention is illustrated. To match a requirement of the “1 0” circle C 20 , when input signals A and B are all level “0”, a current of a transistor M 8 _ 1  has to be less than that of a transistor M 9 . When the input signals A and B respectively have the levels 0 1, the current of the transistor M 8 _ 1  has to be greater than that of the transistor M 9 . When the input signals A and B respectively have the levels 1 0, a current of a transistor M 8  needs to be greater than that of a transistor M 9 _ 1 . Conversely, when input signals A and B are all level “1”, the current of the transistor M 8  needs to be less than that of the transistor M 9 _ 1 . Deduced by analogy, and in coordination with N-type boost circuits C 30 ˜C 60  to shift voltage levels of input signals A, B, Ā,  B , bulk inputs of the transistors M 8 , M 9 , M 8 _ 1  and M 9 _ 1  then may be accomplished, so as to implement the XOR gate of  FIG. 12B . 
         [0056]    It should be noted that since phases of output signals of output terminals Q 1  and Q 2  of the aforementioned embodiment are inversed, the XOR may also be an XNOR gate. 
         [0057]    Next, an embodiment of a multiplexer designed based on the P-type bulk input current switch logic circuit and the P-type boost circuit is provided. Referring to  FIG. 13A ,  FIG. 13A  is a Karnaugh map of a multiplexer. Referring to  FIG. 13B , a circuit diagram illustrating a multiplexer of a bulk input current switch logic circuit according to an embodiment of the present invention is illustrated. Similarly, output results on the Karnaugh map which include “1 0” are circled for obtaining “1 0” circles D 10 ˜D 20 . To match a requirement of the “1 0” circle D 1 , a selection signal X of the multiplexer is input to the gates of the transistors M 8 _ 1  and M 9 . To match a requirement of the “1 0” circle D 20 , an inverted signal X of the selection signal X is input to the gates of the transistors M 8  and M 9 _ 1 . 
         [0058]    Moreover, as to the bulk input, and in case the requirement of the “1 0” circle D 10  is matched, when the input signal A=0 and the selection signal X=1, a discharge current of the transistor M 8 _ 1  has to be less than that of the transistor M 9 . When the input signal A=1 and the selection signal X=1, the discharge current of the transistor M 8 _ 1  has to be greater than that of the transistor M 9 . In case the requirement of the “1 0” circle D 20  is matched, when the input signal A=0 and the selection signal X=0, a discharge current of the transistor M 8  has to be less than that of the transistor M 9 _ 1 . When the input signal A=1 and the selection signal X=0, the discharge current of the transistor M 8  has to be greater than that of the transistor M 9 _ 1 . 
         [0059]    By synthesizing the requirements of the “1 0” circles D 10  and D 20 , and by inputting the input signals A and B, and the inverted signals Ā and  B  thereof into the transistors M 8 , M 9 , M 8 _ 1  and M 9 _ 1  after the voltage levels thereof being converted by the P-type boost circuits D 30 ˜D 60 , the multiplexer logic circuit of  FIG. 13B  then may be implemented. 
         [0060]    In addition, please refer to  FIG. 14  for an application of a pipeline structure,  FIG. 14  is a schematic diagram of a pipeline structure according to an embodiment of the present invention. Wherein, the pipeline structure of the bulk input current switch logic circuit utilize a single phase clock (SPC) control signal. Such structure avails a design of a high speed pipeline system. Since an inverted clock signal is not applied, a problem of clock skew is avoided, so that a clock frequency thereof is improved, an output capacitance is relatively small, a buffer design is relatively easy, and clock distribution structure considerations are reduced and a layout size of the circuit is reduced. A working principle thereof is as follows. When a clock signal φ is changed from 0 to 1, an internal current sense amplifier of a P-type bulk input current switch logic circuit H 10  start to operate, and a full-swing output is performed via the output terminals Q 1  and Q 2  for transmitting to a next stage N-type bulk input current switch logic circuit H 20 . When the clock signal φ is changed from 1 to 0, an internal current sense amplifier of a N-type bulk input current switch logic circuit H 20  start to operate, and a full-swing output is performed via the output terminals Q 1  and Q 2  for transmitting to a third stage P-type bulk input current switch logic circuit H 30 , and so on, until operation the whole pipeline structure is completed. 
         [0061]    In summary, in the present invention, by sensing current, switch of levels transition may be quickly accomplished, and by applying only two serially connected transistors, transmission speed of digital signals may be improved. 
         [0062]    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.