Abstract:
A differential amplifier has at least two pairs of transistors functioning as current dividing circuits in addition to two other conventionally employed current dividing circuits in this type of amplifier. The signal current components flowing through the two additional current dividing circuits surffer no substantial distortions as do those flowing through the conventional current dividing circuits. The output current of the differential amplifier is a sum of these signal components. Accordingly, the less the proportion of the distorted signal components to the undistorted ones is, the freer the differential amplifier from waveform and high frequency distortion becomes.

Description:
BACKGROUND OF THE INVENTION 
     Our invention relates to amplifiers, and more particularly to differential amplifiers capable of producing an output proportional to the difference between two inputs. More particularly, our invention relates to a differential amplifier whose gain is variable at will. 
     Our invention represents an improvement over variable gain differential amplifiers disclosed by U.S. Pat. No. 3,689,752 to Gilbert. When the gain is varied, their high frequency response characteristics of the prior art amplifiers change so much that the signal waveform suffers great distortions. We will later explain how such signal distortions have occurred with the prior art, with reference to some of the drawings attached hereto. 
     SUMMARY OF THE INVENTION 
     We have hereby invented an amplifier which substantially reduces distortions in the high frequency response to the variable gain. 
     Briefly, our invention may be summarized as a variable gain differential amplifier comprising a pair of input terminals connected to the bases of a first pair transistors, the emitters of which are both connected to an electric current source. A pair of output terminals are connected to a supply terminal via a pair of load resistors, respectively. A second pair of transistors have their collectors connected to the supply terminal via the first and second load resistors, respectively, and their bases connected to a pair of gain control terminals, respectively. A third pair of transistors have their emitters connected to the emitters of the second pair of transistors, their collectors cross-connected to the collectors of the second pair of transistors, and their bases connected to the pair of gain control terminals. A fourth pair of transistors have their emitters connected to the collectors of the first pair of transistors, their collectors connected to the emitters of the second and third pairs of transistors, and their bases connected to a common bias terminal. Also included are two current dividing circuits connected respectively between the second and fourth pairs of transistors. 
     Preferably, each of the two current dividing circuits comprises an additional pair of transistors. In another preferred embodiment, each current dividing circuit additionally comprises three other transistors. 
     Because of the improved circuit configurations of the differential amplifier in our invention, the signal current components flowing through the two current dividing circuits suffer no substantial distortions, whereas the components flowing through the second and third pairs of transistors do. The output current of the differential amplifier is a sum of these signal components. Accordingly, the less the proportion of the distorted signal components becomes the freer the differential amplifier is from waveform distortion and the deterioration of its high frequency characteristic. Also, the range of variable gain may be made suitably narrower. 
     The above and other advantages of our invention and the manner of realizing them will become more apparent. The invention itself will best be understood, from a study of the following description and appended claims taken together with the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a typical prior art variable gain differential amplifier bearing particular pertinence to our invention; 
     FIG. 2 is a circuit diagram equivalent to one pair of transistors included in the prior art differential amplifier of FIG. 1. The diagram is explanatory of the current dividing action of these transistors; 
     FIG. 3 is a circuit diagram equivalent to the same pair of transistors as in FIG. 2. The diagram is explanatory of the step response of the transistors; 
     FIGS. 4, 5 and 6, each consisting of (A)-(C), are a graphic representation of the step responses involved in the prior art differential amplifier of FIG. 1. The graph is explanatory of how signal distortions take place in the prior art; 
     FIG. 7 is a diagram of a first preferred embodiment of a variable gain differential amplifier according to our invention; and 
     FIG. 8 is a similar diagram of a second preferred embodiment of variable gain differential amplifier according to our invention. 
    
    
     DETAILED DESCRIPTION 
     Prior Art 
     Referring to FIG. 1, the prior art differential amplifier circuit has a pair of transistors Q 1  and Q 2  having their emitters connected together via emitter resistors R E1  and R E2  to provide a differential amplifier. A constant current source C S1  is connected between ground and the output from the transistors Q 1  and Q 2 . The bases of the transistors Q 1  and Q 2  respectively are connected to input terminals 1 and 2 from which an input signal V in  is to be supplied. 
     A second pair of transistors Q 3  and Q 5  has their emitters interconnected and further connected to the collector of the transistor Q 1  of the first recited pair of such transistors. A third pair of transistors Q 4  and Q 6  also has their emitters interconnected and further connected to the collector of the other transistor Q 2  of the first pair. The second and third pairs of transistors have their collectors respectively cross-connected to load resistors R 2  and R 1  and further to a supply terminal 3. A cascode amplifier is constituted of a serial connection of the grounded-emitter transistors Q 1  and Q 2  and the grounded-base transistors Q 3  and Q 4 . 
     A first gain control terminal 4 is connected to the bases of the transistors Q 3  and Q 4 . A second gain control terminal 5 is connected to the bases of the transistors Q 5  and Q 6 . A pair of output terminals 6 and 7, at which an output signal V out  is obtained, is connected to the collectors of the transistors Q 3  and Q 4 . 
     The gain of this known differential amplifier circuit is variable through changes in the difference LV between the potential V 1  at the first gain control terminal 4 and the potential V 2  at the second gain control terminal 5. The change in the potential difference LV results in a change in the ratio at which the collector currents I 1  and I 2  of the transistors Q 1  and Q 2  are divided by the transistors Q 3  and Q 4 , and the transistors Q 5  and Q 6 . The gain may be varied continuously through continuous changes in the potential difference LV. 
     In FIG. 2 we have illustrated a simplified circuit of the current-dividing action of the transistors Q 3  and Q 5  of the prior art differential amplifier circuit of FIG. 1. The capital E in this diagram indicates the interconnection between the emitters of the transistors Q 3  and Q 5 . As shown, connected to this interconnection E is a source of current I 1  equivalent to the collector current of the transistor Q 1  of the FIG. 1 circuit. The base-emitter impedance of the transistors Q 3  and Q 5  is respectively designated as Z BE3  and Z BE5  ; the emitter resistance of the transistors Q 3  and Q 5  is respectively designated as r e3  and r e5  ; and the base-emitter capacitance of the transistors Q 3  and Q 5  is respectively designated as C BE3  and C BE5 . 
     Generally, the emitter resistance r e  of the transistor is proportional to the reciprocal of the emitter current I E . Thus, 
     
         r.sub.e =r.sub.eo ·(1/I.sub.E)                    (1) 
    
     where r eo  is a constant. 
     The base-emitter capacitance C BE  of the transistor is defined as: 
     
         C.sub.BE =C.sub.D +C.sub.J +C.sub.o                        (2) 
    
     where 
     C D  =base diffusion capacitance, 
     C J  =base-emitter junction capacitance, 
     C o  =parasitic capacitance. 
     Being proportional to the emitter current I E , the base diffusion capacitance C D  is expressed as: 
     
         C.sub.D =C.sub.Do ·I.sub.E                        (3) 
    
     where C Do  is a constant. 
     The junction capacitance D J  is negligibly small compared to the base diffusion capacitance C D . The base-emitter impedance Z BE  may therefore be considered as a parallel connection of the emitter resistance r e  and the base-emitter capacitance C BE . Thus, ##EQU1## 
     The signal current components i 3  and i 5  flowing through the transistors Q 3  and Q 5  can be expressed as: 
     
         i.sub.3 =[Z.sub.BE5 /(Z.sub.BE3 +Z.sub.BE5)]·i.sub.1(5) 
    
     
         i.sub.5 =[Z.sub.BE3 /(Z.sub.BE3 +Z.sub.BE5)]·i.sub.1(6) 
    
     where 
     I 1  =input signal current, 
     I E3  =bias current of the transistor Q 3 , 
     I E5  =bias current of the transistor Q 5 , 
     Z BE3  =base-emitter impedance of the transistor Q 3 , 
     Z BE5  =base-emitter impedance of the transistor Q 5 . 
     The transient response characteristics, exhibited when the input current is supplied intermittently by the provision of a switch S as shown in FIG. 3, can be expressed as: ##EQU2## 
     Equations (7) and (8) can be rewritten from Equations (1) and (2) as: ##EQU3## where 
     
         A.sub.3 =(C.sub.Do ·I.sub.E3 +C.sub.o)/(C.sub.Do ·I.sub.1 +2C.sub.o) 
    
     
         A.sub.5 =(C.sub.Do ·I.sub.E5 +C.sub.o)/(C.sub.Do ·I.sub.1 +2C.sub.o) 
    
     
         B.sub.3 =I.sub.E3 /I.sub.1 
    
     
         B.sub.5 =I.sub.E5 /I.sub.1 
    
     
         α=I.sub.1 /{r.sub.eo ·(C.sub.Do ·I.sub.1 +2C.sub.o)}. 
    
     FIGS. 4-6 respectively show Equation (9) when I E3  =I E5 , I E3  =3 I E5  and 3 I E3  =I E5 . In each figure, graphs (A)-(C) respectively represent the responses exhibited by the first term of the right hand side, the second term of the right hand side and the complete right hand side of Equation (9). 
     In the step response of the first term of the right hand side of Equation (9), the current i is {(C Do  ·I E3  +C o )/C Do  ·I 1  ·2C o  }i 1  when t=0. This is composed of a component, (C Do  /C Do  ·I 1  ·2C o )I E  ·I 1 , that is proportional to the emitter current I E3 , and a component, {C o  /(C Do  ·I 1  +2C o )}i 1 , that is not. Let us assume that C Do  ·I E  =C o  when I E3  =I E5  =I 1  /2. With a change from (I E3  =I E5  =I 1  /2) to (I E3  =3/4I 1 ) and (I E5  =1/4I 1 ), the value of A 3  does not change increase in proportion to I E3  but does in proportion to (I E3  /I 1 )·i 1  when t=∞ in the step response of the second term of the right side of Equation (9). 
     The value of B 3  varies in proportion I E3 . Therefore, the step response of I 3  depicts the waveform that rises bluntly as in FIG. 5(C) when I E3  =3/4 I 1  and I E5  =1/4 I 1 . When I E3  =1/4 I 1  and I E5  =3/4 I 1 , on the other hand, it depicts the waveform that rises with an overshoot as in FIG. 6(C). These facts prove that the output signal waveform of the prior art circuit suffers distortions due to changes in the high frequency characteristic when the gain is changed by varying the current dividing ratio of the transistors Q 3  and Q 5 . 
     This drawback of the FIG. 1 prior art circuit is totally absent from the improved differential amplifier of our invention. 
     First Preferred Embodiment 
     FIG. 7 shows the first preferred embodiment of differential amplifier. The transistors Q 1  -Q 6 , load resistors R 1  -R 2 , emitter resistors R E1  and R E2 , constant current source C s1 , input terminals 1 and 2, gain control terminals 4 and 5, and output terminals 6 and 7 perform substantially the same functions as their prior art counterparts designated by the same reference indicia in FIG. 1. The connections of these conventional parts are also substantially the same reference in FIG. 1. We will therefore omit any repeated description of such known parts. 
     The improved differential amplifier newly incorporates six additional transistors Q 7  -Q 12  and bias terminals. These terminals are intended for the application of biasing potentials V a  and V b  to some selected transistors set forth hereafter. 
     The transistor Q 7  has its emitter connected to the collector of the transistor Q 1 , its collector connected to the emitters of the transistors Q 3  and Q 5 , and its base connected to the bias terminal 8. The transistor Q 8  has its emitter connected to the collector of the transistor Q 2 , its collector connected to the emitters of the transistors Q 4  and Q 6 , and its base connected to the bias terminal 8. 
     The transistors Q 9  and Q 10  form a first current dividing circuit. The transistors Q 11  and Q 12  form a second current dividing circuit. These two current dividing circuits constitute essential features of our invention. 
     The transistor Q 9  of the first current dividing circuit has its emitter connected to the emitter of the transistor Q 7 , and its base connected to the bias terminal 8. The other transistor Q 10  of the first current dividing circuit has its emitter connected to the collector of the transistor Q 9 , its collector connected to the collector of the transistor Q 3 , and its base connected to the second bias terminal 9. 
     The transistor Q 11  of the second current dividing circuit has its emitter connected to the emitter of the transistor Q 8 , and its base connected to the bias terminal 8. The other transistor Q 12  of the second current dividing circuit has its emitter connected to the collector of the transistor Q 11 , and its collector connected to the collector of the transistor Q 4 . 
     The transistors Q 7  and Q 9 , and the transistors Q 8  and Q 11 , both have their bases and emitters interconnected. Therefore, if these transistors are of the same characteristics, the collector currents I 1  and I 2  of the transistors Q 1  and Q 2  will be divided into two equal halves, and one half of each collector current will flow to the collector of the associated transistor. Thus, 
     
         I.sub.7 =I.sub.9 =I.sub.1 /2                               (1) 
    
     
         I.sub.8 =I.sub.11 =I.sub.2 /2                              (12) 
    
     where 
     I 7  =collector current of the transistor Q 7 , 
     I 8  =collector current of the transistor Q 8 , 
     I 9  =collector current of the transistor Q 9 , 
     I 11  =collector current of the transistor Q 11 . 
     As in the prior art circuit art of FIG. 1, the collector currents I 7  and I 8  of the transistors Q 7  and Q 8  respectively flow through the transistors Q 3  and Q 5  and the transistors Q 4  and Q 5 . Inevitably, therefore, these collector currents invite deterioration in the high frequency response of the differential amplifier. However, the collector currents I 9  and I 11  of the transistors Q 9  and Q 11  do not flow through the transistors Q 3  and Q 5  and the transistors Q 4  and Q 5 . These collector currents do not cause deterioration in high frequency response. 
     It will therefore be understood that in FIG. 7 under continuously variable gain the signal current is a sum of both deteriorated and nondeteriorated components in high frequency response. Consequently, the deterioration in the high frequency response according to our invention is half of that in the prior art. 
     Second Preferred Embodiment 
     FIG. 8 shows a second preferred embodiment of differential amplifier according to our invention. It has six transistors Q 13  -Q 18 , in addition to the transistors Q 1  -Q 12  of the FIG. 7 circuit, and two switching control terminals 10 and 11. 
     The transistor Q 13  has its emitter connected to the emitter of the transistor Q 7 , its collector to the emitter of the transistor Q 14 , and its base to the bias terminal 8. The transistor Q 14  has its collector connected to the collector of the transistor Q 3 , and its base to the switching control terminal 10. The serial circuit of the transistors Q 13  and Q 14  is connected in parallel with the serial circuit of the transistors Q 9  and Q 10 . Consequently, the transistors Q 13  and Q 14  constitute a current dividing circuit like the transistors Q 9  and Q 10 . 
     The transistor Q 15  has its emitter connected to the emitter of the transistor Q 8 , its collector connected to the emitter of the transistor Q 16 , and its base connected to the bias terminal 8. The transistor Q 16  has its collector connected to the collector of the transistor Q 4 , and its base connected to the switching control terminal 10. The serial circuit of the transistors Q 15  and Q 16  is connected in parallel with the serial circuit of the transistors Q 11  and Q 12 . Therefore, like the latter serial circuit, transistors Q 15  and Q 16  in the serial circuit functions as a current dividing circuit, too. 
     The transistor Q 17  has its emitter connected to the collector of the transistor Q 13 , its collector connected to the collector of the transistor Q 4 , and its base connected to the switching control terminal 11. When the transistor Q 17  is conductive, it constitutes a current dividing circuit in combination with the transistor Q 13 . 
     The transistor Q 18  has its emitter connected to the collector of the transistor Q 15 , its collector connected to the collector of the transistor Q 3 , and its base connected to the switching control terminal 11. When the transistor Q 18  is conductive, it constitutes a current dividing circuit in combination with the transistor Q 15 . 
     The control terminal 10 is connected to the bases of the transistors Q 14  and Q 16  for their on-off control. The other switching control terminal 11 is connected to the bases of the transistors Q 17  and Q 18  for their on-off control. 
     In operation, let us assume that the transistors Q 14  and Q 16  are switched on, and the transistors Q 17  and Q 18  are switched off. Then, the collector current I 1  of the transistor Q 1  will be equally divided by the three transistors Q 7 , Q 9  and Q 13 . The collector current I 2  of the transistor Q 2  will also be equally divided by the three associated transistors Q 8 , Q 11  and Q 15 . Consequently, only one third of each of the collector currents I 1  and I 2  will respectively flow into transistors Q 7  and Q 8 . The deterioration in this differential amplifier in the high frequency response is therefore only one third of that in the prior art. 
     It is also possible in the FIG. 8 circuit to make the transistors Q 17  and Q 18  conductive and the transistors Q 14  and Q 16  nonconductive. 
     Possible Modifications 
     Although we have shown and described our invention in very specific manners we do not wish our invention to be limited by the exact details of this disclosure. The following is a brief list of possible modifications or alterations of the illustrated embodiments which we believe all fall within the scope of our invention: 
     1. There may be provided a greater number of current dividing circuits than those included in the FIG. 8 circuit. 
     2. Switches may be connected to some or all of such a greater number of current dividing circuits, and 1/n of the total current may be varied continuously by providing n current dividing circuits, in order to reduce the high frequency response deterioration of the resulting amplifier to 1/n. 
     3. Either of the potentials V 1  and V 2  of the gain control terminals 4 and 5 may be made invariable.