Abstract:
A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.

Description:
BACKGROUND 
       [0001]    Metal-oxide semiconductor field-effect transistors (“MOSFETs”) are a common type of power switching device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure provided adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer. 
         [0002]    When a MOSFET device is in the on state, a voltage is applied to the gate structure to form a conduction channel region between the source and drain regions, which allows current to flow through the device. In the off state, any voltage applied to the gate structure is sufficiently low so that a conduction channel does not form, and thus current flow does not occur. In the off state, the device may support a high voltage between the source region and the drain region. 
         [0003]    Two major parameters affect the high-voltage MOSFET switch market: break down voltage (BVdss) and on-state resistance (Rdson). Breakdown voltage is the voltage at which the reverse-biased body-drift diode breaks down and significant current starts to flow between the source and drain while the gate and source are shorted together. The on-state resistance is the sum of various resistances, which may include (but are not limited to) one or more of: source diffusion resistance, channel resistance, accumulation resistance, drift region resistance, and substrate resistance. For a specific application, a minimum breakdown voltage is usually required, and designers meet the breakdown voltage requirement at the expense of on-state resistance. This trade-off in performance is a major design challenge for manufacturers and users of high-voltage power-switching devices. 
         [0004]    Recently, superjunction devices have gained in popularity to improve the trade-off between breakdown voltage and on-state resistance. However, significant challenges still exist in manufacturing the superjunction devices. Specifically, providing a fast reverse recovery and a small forward voltage for a given forward current, while at the same time preventing degradation of other electrical parameters, without introducing complexity and cost remains a challenge. 
       SUMMARY 
       [0005]    A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region. 
         [0006]    The second region may include an epitaxy of the first conductivity type. The device may further include a third region of the first conductivity type coupled to the first pillar and the second region. The first region may further include a second pillar of a second conductivity type, the first conductivity type opposite to the second conductivity type. The device may further include a fourth region of the second conductivity type, and the second pillar may include a lower doping concentration than the fourth region. The device may further include an ohmic contact coupled to the fourth region. A polysilicon-filled gate trench may be located horizontally between the first pillar and the Schottky contact. The Schottky contact may be located horizontally between two polysilicon-filled gate trenches, and the second region may divide the two polysilicon-filled gate trenches. The device may be part of a local charge balance, superjunction field effect transistor. The Schottky barrier of the Schottky contact may be 0.4 eV or less. The first region may further include a second pillar of a second conductivity type, the first conductivity type opposite to the second conductivity type. The device may further include a fourth region of the second conductivity type, the second pillar including a lower doping concentration than the fourth region. The Schottky contact may be coupled to the fourth region as well as the second region. 
         [0007]    A method of forming a semiconductor device includes providing a semiconductor substrate defining a major surface. The method further includes forming a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The method further includes forming a second region of the first conductivity type, the first pillar including a higher doping concentration than the second region. The method further includes forming a Schottky contact coupled to the second region. 
         [0008]    Forming the second region may include forming the second region using an epitaxy of the first conductivity type. The method may further include forming a third region of the first conductivity type coupled to the first pillar and the second region. The method may further include forming a second pillar of a second conductivity type in the first region, the first conductivity type opposite to the second conductivity type. The method may further include forming a fourth region of the second conductivity type, the second pillar including a lower doping concentration than the fourth region. The method may further include forming an ohmic contact coupled to the fourth region. The method may further include forming a polysilicon-filled gate trench. The polysilicon-filled gate trench may be located horizontally between the first pillar and the Schottky contact in the fully formed device. The method may further include forming two polysilicon-filled gate trenches. The Schottky contact may be located horizontally between the two polysilicon-filled gate trenches in the fully formed device. The second region may divide the two polysilicon-filled gate trenches in the fully formed device. The method may further include forming a local charge balance, superjunction field effect transistor including the device. 
         [0009]    A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type and a second pillar of a second conductivity type extending in a vertical orientation with respect to the major surface. The first conductivity type is opposite to the second conductivity type. The device further includes a second region of the first conductivity type. The second region includes a higher doping concentration than the first pillar. 
         [0010]    The device may further include a third region of the second conductivity, the third region including a higher doping concentration than the second pillar. The device may further include a fourth region blocking the second and the third region, the fourth region including a salicide. The device may further include a polysilicon-filled trench, wherein the fourth region interrupts the continuity of the polysilicon-filled trench. The device may be a three dimensional device. The device may be part of a local charge balance, superjunction field effect transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Accordingly, systems and methods for field-effect transistors with integrated Schottky contacts are disclosed herein. In the drawings: 
           [0012]      FIG. 1  is a partial view of a cross-section of an illustrative semiconductor device capable of accommodating an integrated Schottky contact; 
           [0013]      FIG. 2  is a partial view of a cross-section of an illustrative semiconductor device capable of accommodating an integrated Schottky contact; 
           [0014]      FIGS. 3A-12B  are partial views of cross-sections of illustrative semiconductor devices in various stages of manufacture that illustrate methods of forming the devices with integrated Schottky contacts; 
           [0015]      FIG. 13  is a partial isometric view of illustrative semiconductor devices capable of accommodating an integrated Schottky contact; and 
           [0016]      FIG. 14  is a partial isometric view of illustrative semiconductor devices capable of accommodating an integrated Schottky contact. 
       
    
    
       [0017]    It should be understood, however, that the specific embodiments given in the drawings and detailed description thereto do not limit the disclosure. On the contrary, they provide the foundation for one of ordinary skill to discern the alternative forms, equivalents, and modifications that are encompassed together with one or more of the given embodiments in the scope of the appended claims. 
       NOTATION AND NOMENCLATURE 
       [0018]    Certain terms are used throughout the following description and claims to refer to particular system components and configurations. As one of ordinary skill will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. Also, the term “couple” or “couples” is intended to mean either an indirect or a direct electrical or physical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through a direct physical connection, or through an indirect physical connection via other devices and connections in various embodiments. 
       DETAILED DESCRIPTION 
       [0019]    A field-effect transistor (“FET”) with an integrated Schottky contact provides fast reverse recovery, a small forward voltage for a given forward current, and simultaneously prevents degradation of other electrical parameters (BVdss, sRon, Qg, Qgd, Qrr, Trr, and the like) without introducing complexity and cost to the manufacture or operation of the FET. The integrated Schottky contact also reduces body diode conduction loss in synchronous rectification as opposed to an ion irradiation process. 
         [0020]    Using Schottky structures for the UltiMOS technology (or any other local charge balance technology) also does not increase complexity or cost. Additionally, having a relatively lowly doped N-epitaxy (a doping of around 10 14  cm −3  in at least one embodiment) enables the manufacture of Schottky contacts with a very low Schottky barrier: 0.4 eV instead of 0.6-0.7 eV. A Schottky barrier is a potential energy barrier for electrons formed at a metal-semiconductor junction. Schottky barriers have rectifying characteristics, suitable for use as a diode.  FIGS. 1 and 2  illustrate the integrated Schottky contacts with the surrounding structures. 
         [0021]      FIG. 1  is a partial view of a semiconductor device  100  built on a horizontal substrate (not shown). The substrate may have a variety of configurations, such as a bulk silicon configuration or a silicon-on-insulator (“SOI”) configuration that includes a bulk silicon layer, a buried insulation layer, and an active layer, wherein semiconductor devices are formed in and above the active layer. The substrate may also be made of materials other than silicon. 
         [0022]    The designations “N” and “P” used herein refer to negative and positive conductivity types, respectively, but the opposing types may be reversed as appropriate. The device  100  includes an N epitaxial layer  102 , an N link layer  103 , a Schottky contact  104 , a lowly-doped N layer  105 , a P pillar  106 , an N pillar  107 , an oxide layer  108 , a P body  109 , an ohmic contact  110 , a highly-doped P+ region  112 , and a polysilicon-filled gate trench  116 . 
         [0023]    The N pillar  107  extends in a vertical orientation with respect to the substrate, and includes a higher doping concentration than the lowly-doped N layer  105 , which may include an N epitaxy. In at least one embodiment, lowly-doped regions include concentrations around 10 14  cm −3  for both N and P regions. However, any combination of doping concentrations may be used as long as highly-doped regions include a higher doping concentration than lowly-doped regions. 
         [0024]    The Schottky contact  104  is coupled to the lowly-doped N layer  105 , and the Schottky barrier may be 0.4 eV or less. As such, the Schottky contact  104  is not coupled to N+ or P body wells. The high-energy N link layer  102 , which may include phosphorus, is coupled to the N pillar  107  and lowly-doped N layer  105  to provide a conduction path between the Schottky contact  104  and an N+ substrate. Specifically, the conduction path includes the Schottky contact  104 , the lowly-doped N layer  105 , the N link layer  103 , the N pillar  107 , and the N substrate. Such a conduction path does not include a P region such as the P body  109 , the highly-doped P+ region  112 , or the P pillar  106 . 
         [0025]    Based on the charge compensation principle, the excess charge in the N pillar  107  is counter-balanced by the adjacent charges in the P pillar  106 , and a uniform field distribution can thus be achieved. These pillars  106 ,  107  make it possible to achieve local charge balance. Accordingly, a low conduction path and low Schottky barrier may be implemented with high voltage capability, and leakages at the edges of the Schottky contact  104  are reduced. 
         [0026]    The P pillar  106  may include a lower doping concentration than the highly-doped P+ region  112 , which is coupled to the ohmic contact  110 . As illustrated, the Schottky contact  104  is dedicated, but in an alternative embodiment (not shown), the Schottky contact  104  is coupled to the P+ region  112  as well as the N layer  105  simultaneously. As shown, the layer of oxide  108  separates the ohmic contact  110  and Schottky contact  104 , protects the P body  109  and P pillar  106 , and covers the polysilicon-filled gate trench  116 . Here, the polysilicon-filled gate trench  116  is formed on one side of both contacts  104 ,  110 . Specifically, it is formed on the left side of both contacts  104 ,  110 , and does not horizontally separate the contact  104 ,  110 .  FIG. 2  illustrates an alternative position for the polysilicon-filled gate trench, Schottky contact, and N layer. 
         [0027]      FIG. 2  illustrates a device  200  including an N epitaxial layer  202 , an N link layer  203 , a Schottky contact  204 , a lowly-doped N layer  205 , a P pillar  206 , an N pillar  207 , an oxide layer  208 , a P body  209 , an ohmic contact  210 , a highly-doped P+ region  212 , and polysilicon-filled gate trench  216 . Here, the polysilicon-filled gate trench  216  is formed horizontally between the ohmic contact  210  and the Schottky contact  204 , i.e. between the N pillar  207  and the Schottky contact  204 . The Schottky contact  204  may be formed horizontally between two polysilicon-filled gate trenches  216 , and the lowly-doped N layer  205  may divide the two polysilicon-filled gate trenches  216  as illustrated in  FIG. 12B . The configurations of  FIG. 1  and  FIG. 2  are fully compatible with UltiMOS structures, and  FIGS. 3A-12B  illustrate methods of forming the devices  100 ,  200  in  FIGS. 1 and 2 . 
         [0028]      FIGS. 3A-12B  illustrate methods of forming one or more semiconductor devices. The Figures ending in “A” illustrate a method of forming the device  100  of  FIG. 1 , while the Figures ending in “B” illustrate a method of forming the device  200  of  FIG. 2 . Only portions of the devices are shown, e.g., the substrate (which may be horizontal layer of silicon below the structures depicted in the Figures) is not shown. 
         [0029]    The semiconductor materials forming the various layers of  FIGS. 3A-12B  may include a variety of different materials, e.g., silicon, doped silicon, silicon/germanium, germanium, a group III-V material, etc. The layers may be formed to any desired thickness using an appropriate process, e.g., an epitaxial growth process, a deposition process, an ion implantation process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an epitaxial deposition process (EPI), plasma versions of such processes, a wet or dry etching process, an anisotropic etching process, an isotropic etching process, an etching through hard mask process, timed etch, stop-on-contact etch, etc. 
         [0030]    At  FIGS. 3A and 3B , a layer of N epitaxy  300  is grown over the underlying structures, which may include a substrate. The layer  300  may be doped such that a bottom portion of the layer  300  is lowly-doped, a middle portion of the layer  300  is highly doped, and a top portion of the layer  300  is lowly-doped. An epitaxial layer can be doped during deposition by adding impurities to the source gas, such as arsine, phosphine or diborane. The concentration of impurity in the gas phase determines its concentration in the deposited layer. In the completed device, this layer  300  will form the N epitaxial layer, the N link layer, and lowly-doped N layer. 
         [0031]    At  FIGS. 4A and 4B , a layer of P material  402  is deposited into an etched portion of the N epitaxy layer, and a layer of N material  404  is deposited into an etched portion of the layer of P material  402 . The various layers may be leveled using a chemical mechanical polishing (“CMP”) process, and the shape of the etched portions, and hence the shape of the layers, may be manipulated using masking processes. In the completed device, the layer of P material will form the P body and highly-doped P+ region. 
         [0032]    At  FIGS. 5A and 5B , a masking layer  506  is deposited onto the structures in order to etch gate trenches at the positions left open by the masking layer  506 . The masking material may include a photoresist which has been patterned using photolithography. Specifically, the masking layer  506  protects the structures underneath the masking layer  506  from the etchant. 
         [0033]    At  FIGS. 6A and 6B , gate trenches  608  are etched. Specifically, an etchant is used to remove portions of the structures not protected by the masking layer. The formulas for common etchants are HNO 3 , HF, KOH, EDP, TMAH, NH 4 F, and H 3 PO 4 . Other etchants may be used as well. In the completed device, the gate trenches will form the polysilicon-filled gate trenches. 
         [0034]    At  FIGS. 7A and 7B , a polysilicon layer is deposited onto the device, thus creating a polysilicon-filled gate trench  710 . The polysilicon material outside of the gate trench may be removed via CMP. In the completed device, the polysilicon layer will form the polysilicon-filled gate trenches. 
         [0035]    At  FIGS. 8A and 8B , a hard mask layer  812  is deposited onto the device to protect the underlying structures from the superjunction trench etch. Next, the superjunction trench etch is performed, removing structures not protected by the hard mask layer  812 . 
         [0036]    At  FIGS. 9A and 9B , and sidewall structures  914  are formed via growth and etch of epitaxy materials. Specifically, an N material and P material sidewall structures  914  are grown against the sidewalls of the existing structures. The sidewall structures  914  may be doped during or after growth. In the completed device, the sidewall structures  914  form the N pillar and the P pillar. 
         [0037]    At  FIGS. 10A and 10B , P material is implanted into the structures in order to connect the P body to the P pillar. Next, an oxide layer  1016  is grown as a liner to protect and cover the underlying structures. 
         [0038]    At  FIGS. 11A and 11B , the trench is sealed by depositing a layer of oxide material  1118  onto the structures. 
         [0039]    At  FIGS. 12A and 12B , the layer of oxide material is etched to accommodate ohmic contacts. Next, an implant of P material is administered through the etched portions to form the highly-doped P+ region. The trench seal is also etched to accommodate the Schottky contact. Finally, contact material is used to fill the etched portions and form the ohmic  1222  and Schottky contacts  1220 . The contact material may be tungsten, and a CMP process may be used to level the contacts  1222 ,  1220  and the device. 
         [0040]      FIGS. 13 and 14  illustrate three dimensional local charge balance, superjunction FET devices with blocking implants  1302 ,  1402 . The devices include many of the same structures illustrated in  FIGS. 1-12B , and also include wide blocking implant  1302  and a narrow blocking implant  1402 . Specifically, the deep trenches of oxide material (reference  108  in  FIG. 1  and reference  1118  in  FIG. 11 ) are blocked by the blocking implant  1302 ,  1402 , which may include a salicided region and may optionally accommodate metal contacts. The salicide process includes the reaction of a thin metal film with silicon to form a metal silicide contact through a series of annealing and/or etch processes. In  FIG. 13 , the blocking implant  1302  is formed between the two deep trenches and extends to the gate regions of the device. In  FIG. 14 , the blocking implant  1402  is restricted to the center of the device allowing the channel region including the P body and N+ regions to be present. 
         [0041]    Numerous other modifications, equivalents, and alternatives, will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such modifications, equivalents, and alternatives where applicable.