Abstract:
A method is provided for forming a pixel of an electroluminescence device. The method provides a substrate; defines at least a first area for capacitors, a second area for a transistor on the substrate and a third area for an organic light-emitting diode (OLED) on the substrate; forms first conductive, first dielectric, second conductive, second dielectric, and third conductive layers over the first area; forming a third conductive layer over the second dielectric layer over the first area; wherein the first conductive layer over the first area is directly connected to a power supply voltage, wherein the second conductive layer is electrically connected to a fourth conductive layer and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. patent application Ser. No. 13/031,712, filed Feb. 22, 2011, which is a divisional of U.S. patent application Ser. No. 11/616,943, filed Dec. 28, 2006 (now U.S. Pat. No. 7,915,117, issued on Mar. 29, 2011), which is a divisional of U.S. patent application Ser. No. 11/005,648, filed Dec. 7, 2004 (now U.S. Pat. No. 7,586,121, filed Sep. 8, 2009), the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates in general to an electroluminescence device and, more particularly, to a storage capacitor of an electroluminescence device and a method for forming the storage capacitor. 
     2. Description of the Related Art 
     An electroluminescence (“EL”) device is a device which makes use of the phenomenon of electroluminescence to emit light. An EL device generally includes thin film transistors (“TFTs”) and light-emitting diodes (“LEDs”). Each LED further includes a light-emitting layer. If the light-emitting layer contains organic light-emitting material, the device is referred to as an organic EL device. When a current passes between a cathode and an anode of the LED device, light is emitted from the light-emitting layer. 
     Generally, an active matrix organic light emitting diode (“OLED”) device or a polymer light emitting diode (“PLED”) device, either voltage-driven or current-driven, includes an array of pixels, where each pixel comprises a set of sub-pixels. Each sub-pixel further includes a switching transistor, a driving transistor and a storage capacitor. If charging conditions permit, it is desirable to design a storage capacitor with a large capacitance in order to avoid an issue of gray scale fading due to crosstalk or feed-through effect. For bottom-emission pixels, a storage capacitor having a greater capacitance may disadvantageously result in a smaller aperture ratio. In OLED pixels, thin film transistors, scan lines, data lines and power lines included therein may further reduce the aspect ratio. It is thus desirable to have a storage capacitor that includes improved capacitance in a limited area. 
     BRIEF SUMMARY OF INVENTION 
     Consistent with embodiments of the present invention, there is provided a method for forming a pixel of an electroluminescence device that includes providing a substrate; defining at least a first area for capacitors and a second area for a transistor on the substrate; forming a first conductive layer over the first area; forming a first dielectric layer over the first conductive layer over the first area; forming a second conductive layer over the first dielectric layer over the first area; forming a second dielectric layer over the second conductive layer over the first area; forming a third conductive layer over the second dielectric layer over the first area; forming a layer of capping silicon nitride between the second dielectric layer and the third conductive layer over the first area; forming a semiconductor layer over the second area; forming a gate oxide layer over the second area; and forming a fourth conductive layer over the gate oxide layer over the second area; wherein the first conductive layer over the first area is connectable to a power supply voltage, and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer, and the third conductive layer over the first area collectively form a second one of the capacitors over the first area, and the semiconductor layer, the gate oxide layer, and the fourth conductive layer over the second area collectively form a transistor. 
     Consistent with embodiments of the present invention, there is also provided a method for forming a pixel of an electroluminescence device that includes providing a substrate; defining at least a first area for capacitors, a second area for a transistor on the substrate and a third area for an organic light-emitting diode (OLED) on the substrate; forming a first conductive layer over the first area; forming a first dielectric layer over the first conductive layer over the first area; forming a second conductive layer over the first dielectric layer over the first area; forming a second dielectric layer over the second conductive layer over the first area; forming a third conductive layer over the second dielectric layer over the first area; forming a semiconductor layer over the second area; forming a gate oxide layer over the second area; forming a fourth conductive layer over the gate oxide layer over the second area; forming the gate oxide over the first area; forming the first conductive layer over the gate oxide, wherein forming the first conductive layer and forming the fourth conductive layer comprise forming the first conductive layer and the fourth conductive layer using the same material, wherein forming the first dielectric layer comprises forming a layer of interlayer dielectric (ILD), and wherein forming the second dielectric layer comprises forming a layer of passivation silicon nitride; forming a fifth conductive layer over the third area; and forming an organic layer over the fifth conductive layer over the third area, wherein the third conductive layer is over the organic layer over the third area, and wherein the fifth conductive layer, the organic layer, and the third conductive layer over the third area collectively form the OLED, wherein the first conductive layer over the first area is connectable to a power supply voltage, and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer, and the third conductive layer over the first area collectively form a second one of the capacitors over the first area, and the semiconductor layer, the gate oxide layer, and the fourth conductive layer over the second area collectively form a transistor, and wherein forming the second conductive layer and forming the fifth conductive layer comprise forming the second conductive layer and the fifth conductive layer using the same material. 
     Consistent with embodiments of the present invention, there is also provided a method for forming a pixel of an electroluminescence device that includes providing a substrate; defining at least a first area for capacitors, a second area for a transistor on the substrate and a third area for an organic light-emitting diode (OLED) on the substrate; forming a first conductive layer over the first area; forming a first dielectric layer over the first conductive layer over the first area; forming a second conductive layer over the first dielectric layer over the first area; forming a second dielectric layer over the second conductive layer over the first area; forming a third conductive layer over the second dielectric layer over the first area; forming a layer of capping silicon nitride between the second dielectric layer and the third conductive layer over the first area; forming a semiconductor layer over the second area; forming a gate oxide layer over the first area and the second area, wherein the first conductive layer is both over the gate oxide over the first area and over the second area, the first conductive layer providing contact to the semiconductor layer over the second area; forming a fourth conductive layer over the gate oxide layer over the second area; forming a fifth conductive layer over the third area; and forming an organic layer over the fifth conductive layer over the third area, wherein the third conductive layer over the organic layer over the third area, wherein the first conductive layer over the first area is connectable to a power supply voltage, and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer, and the third conductive layer over the first area collectively form a second one of the capacitors over the first area, and the semiconductor layer, the gate oxide layer, and the fourth conductive layer over the second area collectively form a transistor, and wherein forming the first dielectric layer comprises forming a layer of passivation silicon nitride, forming the second conductive layer and forming the fifth conductive layer comprise forming the second conductive layer and the fifth conductive layer using the same material, and forming the second dielectric layer comprises forming a layer of capping silicon nitride, and wherein the fifth conductive layer, the organic layer, and the third conductive layer over the third area collectively form the OLED. 
     Consistent with embodiments of the present invention, there is also provided a method for forming a pixel of an electroluminescence device that includes providing a substrate; defining at least a first area for capacitors, a second area for a transistor on the substrate and a third area for an organic light-emitting diode (OLED) on the substrate; forming a first conductive layer over the first area; forming a first dielectric layer over the first conductive layer over the first area; forming a second conductive layer over the first dielectric layer over the first area; forming a second dielectric layer over the second conductive layer over the first area; forming a third conductive layer over the second dielectric layer over the first area; forming a semiconductor layer over the second area; forming a gate oxide layer over the second area and over the first conductive layer over the first area, wherein forming the first dielectric layer comprises forming an interlayer dielectric over the gate oxide; and forming a fourth conductive layer over the gate oxide layer over the second area; forming a fifth conductive layer over the third area; forming an organic layer over the fifth conductive layer over the third area, wherein forming the second dielectric layer comprises forming the organic layer over the second conductive layer, wherein the third conductive layer is over the organic layer over the third area; wherein the first conductive layer over the first area is connectable to a power supply voltage, and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer, and the third conductive layer over the first area collectively form a second one of the capacitors over the first area, and the semiconductor layer, the gate oxide layer, and the fourth conductive layer over the second area collectively form a transistor, and wherein forming the first conductive layer and forming the semiconductor layer comprise forming the first conductive layer and the semiconductor layer using the same semiconductor material which is provided as doped polysilicon, and wherein the fifth conductive layer, the organic layer, and the third conductive layer over the third area collectively form the OLED. 
     Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a circuit diagram of a pixel of an electroluminescence device consistent with embodiments of the present invention; 
         FIG. 2  is a cross-sectional view of a part of the pixel of  FIG. 1  and consistent with a first embodiment of the present invention; 
         FIG. 3  is a circuit diagram of a pixel of an electroluminescence device consistent with a second embodiment of the present invention; 
         FIG. 4  is a circuit diagram of a pixel of an electroluminescence device consistent with a third embodiment of the present invention; 
         FIG. 5  is a circuit diagram of a pixel of an electroluminescence device consistent with a fourth embodiment of the present invention; 
         FIG. 6  is a circuit diagram of a pixel of an electroluminescence device consistent with a fifth embodiment of the present invention; 
         FIG. 7  is a circuit diagram of a pixel of an electroluminescence device consistent with a sixth embodiment of the present invention; 
         FIG. 8  is a circuit diagram of a pixel of an electroluminescence device consistent with a seventh embodiment of the present invention; 
         FIG. 9  is a circuit diagram of a pixel of an electroluminescence device consistent with an eighth embodiment of the present invention; 
         FIG. 10  is a circuit diagram of a pixel of an electroluminescence device consistent with embodiments of the present invention; and 
         FIG. 11  is a circuit diagram of the pixel of  FIG. 10 , further showing a cross-sectional view of a part of the pixel and consistent with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF INVENTION 
     Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
     An electroluminescence (EL) device may include an array of pixels formed on a substrate such as glass and  FIG. 1  shows a circuit diagram of an exemplary pixel  100  consistent with embodiments of the present invention. Pixel  100  includes three MOS transistors  102 ,  104 , and  106 , a capacitor  108 , and an OLED  110 . In one aspect, transistor  102  is a p-type MOS transistor and transistors  104  and  106  are n-type MOS transistors. Each of transistors  102 ,  104 , and  106  has a gate (not numbered), a source (not numbered), and a drain (not numbered). It is to be understood that an MOS structure is generally symmetrical and therefore the source and drain of the MOS transistors in the descriptions herein and in the following may be interchanged without affecting the functions thereof or the scope of the present invention. 
     The gate of transistor  102  is coupled to the source of transistor  106 . The source of transistor  102  is coupled to a power supply voltage V DD . The drain of transistor  102  is coupled to drive OLED  110 . The gates of both transistors  104  and  106  are coupled to a scan line, the drain of transistor  106  is coupled to the source of transistor  104 , and the drain of transistor  104  is coupled to a data line to receive data. Capacitor  108  is coupled between the gate and source of transistor  102 . OLED  110  has an anode coupled to the drain of transistor  102  and a cathode coupled to a power supply voltage V SS . In one aspect, V SS  is ground. In operation, capacitor  108  holds a charge when transistors  104  and  106  are turned off, to maintain a voltage between the gate and source of transistor  102  for driving OLED  110 . 
     Pixel  100  further includes a capacitor  112  coupled between the gate of transistor  102  and the cathode of OLED  110 . Thus, both capacitors  108  and  112  store charge when transistors  104  and  106  are turned off, to maintain the gate voltage of transistor  102 . In this sense, capacitors  108  and  112  are coupled to each other in parallel and may be collectively viewed as a storage capacitor of pixel  100  whose capacitance is equal to the sum of the capacitances of both capacitors  108  and  112 . 
     In one aspect, capacitor  112  is physically formed over the same area of a substrate where capacitor  108  is formed. Therefore, the storage capacitance of pixel  100  is increased without a chip area thereof being increased. In another aspect, capacitor  112  is formed at the same time OLED  110  and other parts of pixel  100  are formed, without requiring additional masks. 
       FIG. 2  shows a cross-sectional view of part of pixel  100  consistent with a first embodiment of the present invention. Only a portion of OLED  110 , a portion of transistor  102 , and capacitors  108  and  112  are shown. To simplify illustration, transistors  104  and  106  are not shown in  FIG. 2 . 
     Referring to  FIG. 2 , pixel  100  is formed on a glass substrate  200 . Capacitors  108  and  112  are shown to be formed over an area A of substrate  200 , transistor  102  is shown to be formed over an area B of substrate  200 , and part of OLED  110  is shown to be formed in an area C of substrate  200 . 
     Referring to  FIG. 2 , a layer of polysilicon is doped and patterned to form a doped polysilicon  202 B and intrinsic polysilicon  202  over area B of substrate  200 . A layer of gate oxide  204  is formed over all of areas A, B, and C. A layer of first metal is deposited over gate oxide  204  and patterned to form first metal patterns  206 A and  206 B over areas A and B, respectively. A layer of interlayer dielectric (ILD)  208  is formed over first metal patterns  206 A and  206 B. A layer of second metal is deposited over ILD  208  and patterned to form second metal patterns  210 A over area A and  210 B over both areas B and C, wherein second metal pattern  210 B contacts polysilicon pattern  202 B through a via hole (not numbered) in ILD  208  and gate oxide  204 . A layer of passivation silicon nitride (SiN)  212  is formed over ILD  208  and second metal patterns  210 A and  210 B. A layer of indium tin oxide (ITO) is formed over passivation SiN  212  and patterned to form an ITO pattern  214 C over area C of substrate  200 , wherein ITO pattern  214 C contacts second metal pattern  210 B through a via hole (not numbered) in passivation SiN  212 . A layer of capping SiN  216  is deposited to cover passivation SiN  212  and ITO pattern  214 C. A layer of organics  218  is deposited over all of areas A, B, and C. Over area A, capping SiN  216  is also patterned to expose a portion of passivation SiN  212 . Thus, organic  218  is also formed on passivation SiN  212  over area A. A layer of third metal  220  is formed over organic  218 . 
     Over area A, first metal pattern  206 A, ILD  208 , and second metal pattern  210 A collectively form capacitor  108 ; and second metal pattern  210 A, passivation SiN  212 , organic  218 , and third metal  220  collectively form capacitor  112 (           ). Over area B, polysilicon pattern  202 B provides the source and drain of transistor  102  and first metal pattern  206 B serves as the gate of transistor  102 . Over area C, ITO pattern  214 C, capping SiN  216 , organic  218 , and third metal  220  collectively form part of OLED  110 . Also, first metal pattern  206 A is coupled to power supply voltage V DD , second metal pattern  210 A is coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS .
     As shown in  FIG. 2 , capacitors  108  and  112  are formed over the same area (area A) of substrate  200 . Therefore, the storage capacitance of pixel  100  is increased without increasing the area of the storage capacitor and, consequently, without decreasing an aperture ratio. Also, one skilled in the art should now appreciate that no additional masks are required to form capacitors  108  and  112 . For example, first metal pattern  206 A may be formed using an existing mask that is required for forming first metal pattern  206 B and second metal pattern  210 A may be formed using an existing mask that is required for forming second metal pattern  210 B. 
     In  FIG. 2 , ITO pattern  214 C is formed over second metal pattern  210 B. However, the layer of ITO may also be deposited and patterned prior to the deposition of the second metal and the formation of second metal patterns  210 A and  210 B. Similarly, passivation SiN  212  may also be deposited prior to the deposition of the second metal and the formation of second metal patterns  210 A and  210 B. 
     It is to be understood that the configuration of pixel  100  as shown in  FIGS. 1 and 2  is exemplary only. The present invention may be applied to any suitable EL device. For example, a pixel consistent with an aspect of the present invention may include a plurality of capacitors such as capacitors  108  and  112  formed over the same area of a substrate and one or more transistors, but may include no OLED. 
     Further, in  FIG. 2 , capacitor  108  comprises first metal pattern  206 A, ILD  208 , and second metal pattern  210 A, and capacitor  112  comprises second metal pattern  210 A, passivation SiN  212 , organic  218 , and third metal  220 . However, it is to be understood that other layers of materials required for forming pixel  100  may also be used to form capacitors  108  and  112 . 
     For example, consistent with a second embodiment of the present invention, organic  218  may be removed from area A, as shown in  FIG. 3 , which shows a circuit diagram of pixel  100  and a cross-sectional view of capacitors  108  and  112  consistent with the second embodiment of the present invention. Thus, capacitor  112  comprises second metal pattern  210 A, passivation silicon nitride  212 , and third metal  220 , while capacitor  108  comprises first metal pattern  206 A, ILD  208 , and second metal pattern  210 A. Also, first metal pattern  206 A is coupled to power supply voltage V DD , second metal pattern  210 A is coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS . 
     As shown in  FIG. 4 , which shows a circuit diagram of pixel  100  and a cross-sectional view of capacitors  108  and  112  consistent with a third embodiment of the present invention, both capping SiN  216  and organic  218  may be formed over area A and the layer of ITO may be patterned to form an ITO pattern  214 A over area A, while first metal pattern  206 A is not formed during the deposition and patterning of the layer of first metal. Thus, capacitor  108  comprises second metal pattern  210 A, passivation SiN  212 , and ITO pattern  214 A; and capacitor  112  comprises ITO pattern  214 A, capping SiN  216 , organic  218 , and third metal  220 . Also, second metal pattern  210 A is coupled to power supply voltage V DD , ITO pattern  214 A is coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS . 
       FIG. 5  shows a circuit diagram of pixel  100  and a cross-sectional view of capacitors  108  and  112  consistent with a fourth embodiment of the present invention. As shown in  FIG. 5 , capacitor  108  comprises second metal pattern  210 A, passivation silicon nitride  212 , and ITO pattern  214 A; and capacitor  112  comprises ITO pattern  214 A, capping SiN  216 , and third metal layer  220 . Also, second metal pattern  210 A is coupled to power supply voltage V DD , ITO pattern  214 A is coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS . 
       FIG. 6  shows a circuit diagram of pixel  100  and a cross-sectional view of capacitors  108  and  112  consistent with a fifth embodiment of the present invention, wherein the layer of ITO is deposited prior to the deposition of the layer of second metal. As shown in  FIG. 6 , capacitor  108  comprises first metal pattern  206 A, ILD  208 , and ITO pattern  214 A; and capacitor  112  comprises ITO pattern  214 A, passivation silicon nitride  212 , capping silicon nitride  216 , organic  218 , and third metal layer  220 . Also, first metal pattern  206 A is coupled to power supply voltage V DD , ITO pattern  214 A is coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS . 
       FIG. 7  shows a circuit diagram of pixel  100  and a cross-sectional view of capacitors  108  and  112  consistent with a sixth embodiment of the present invention, wherein the layer of ITO is deposited prior to the deposition of the layer of second metal. As shown in  FIG. 7 , capacitor  108  comprises first metal  206 A, ILD  208 , and ITO pattern  214 A; and capacitor  112  comprises ITO pattern  214 A, passivation silicon nitride  212 , capping silicon nitride  216 , and third metal layer  220 . Also, first metal pattern  206 A is coupled to power supply voltage V DD , ITO pattern  214 A is coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS . 
       FIG. 8  shows a circuit diagram of pixel  100  and a cross-sectional view of capacitors  108  and  112  consistent with a seventh embodiment of the present invention. As shown in  FIG. 8 , the layer of doped polysilicon is also patterned to form a polysilicon pattern  202 A over area A of substrate  200 . Thus, capacitor  108  comprises polysilicon pattern  202 A, oxide  204 , ILD  208 , and ITO pattern  214 A; and capacitor  112  comprises ITO pattern  214 A, capping silicon nitride  216 , organic  218 , and third metal layer  220 . Also, polysilicon pattern  202 A is coupled to power supply voltage V DD , ITO pattern  214 A is coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS . 
     Further,  FIG. 9  shows a circuit diagram of pixel  100  and a cross-sectional view of capacitors  108  and  112  consistent with an eighth embodiment of the present invention. As shown in  FIG. 9 , capacitor  108  comprises doped polysilicon pattern  202 A, oxide  204 , ILD  208 , and second metal pattern  210 A; and capacitor  112  comprises second metal pattern  210 A, passivation silicon nitride  212 , organic  218 , and third metal layer  220 . Polysilicon pattern  202 A is coupled to power supply voltage V DD , second metal pattern  210 A is coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS . 
     In  FIGS. 3-9 , both the cross-sectional views of capacitors  108  and  112  and the circuit diagram of pixel  100  are shown and only the structures of capacitors  108  and  112  are discussed in the above. The rest of the circuit of pixel  100  was previously described with reference to  FIG. 1  and is not further described herein. 
     Also consistent with embodiments of the present invention, more than two capacitors may be formed over the same area (area A) of substrate  200  and connected in parallel with one another. An example of four capacitors is shown in  FIGS. 10 and 11 , wherein  FIG. 10  is a circuit schematic of pixel  100  with four capacitors and  FIG. 11  further shows a cross-sectional view of those four capacitors formed over area A of substrate  200 . As shown in  FIG. 10 , in addition to capacitors  108  and  112 , two more capacitors  114  and  116  are also coupled between the gate and source of transistor  102 . The rest of the circuit diagram is the same as that shown in  FIG. 1  and therefore is not further described here. Thus, a storage capacitance of pixel  100  is equal to the sum of capacitors  108 ,  112 ,  114 , and  116 . Referring to  FIG. 11 , capacitor  108  comprises a doped polysilicon pattern  202 A, oxide  204 , and first metal pattern  206 A; capacitor  114  comprises first metal pattern  206 A, ILD  208 , and ITO pattern  214 A; capacitor  116  comprises ITO pattern  214 A, passivation silicon nitride  212 , and second metal pattern  210 A; and capacitor  112  comprises second metal pattern  210 A, capping silicon nitride layer  216 , organic  218 , and third metal layer  220 . Polysilicon pattern  202 A and ITO pattern  214 A are coupled to V DD , first metal pattern  206 A and second metal pattern  210 A are coupled to the gate of transistor  102 , i.e., first metal pattern  206 B, and third metal  220  is coupled to V SS . 
     One skilled in the art should appreciate that the formation of capacitors  108 ,  112 ,  114 , and  116  does not require more masks in addition to those already existing for the formation of pixel  100 . For example, doped polysilicon pattern  202 A may be formed at the same time doped polysilicon pattern  202 B is formed, first metal pattern  206 A may be formed at the same time first metal pattern  206 B is formed, and ITO pattern  214 A may be formed at the same time ITO pattern  214 C is formed. Additionally, since all of capacitors  108 , 112 ,  114 , and  116  are formed over area A of substrate  200 , the area of the storage capacitor of pixel  100  is not increased and, therefore, an aperture ratio is not decreased, while the storage capacitance is significantly increased. 
     Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.