Abstract:
A multiplying analog to digital converter (ADC) including a successive-approximation-register (SAR) analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.

Description:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     This invention was made with support under Grant No. HR0011-13-3-0002 awarded by the Department of Defense—DARPA. The government has certain rights in the invention. 
    
    
     CROSS-REFERENCE TO PRIOR FILED APPLICATIONS 
     This application is related to U.S. provisional application 62/118,903 which was filed on Feb. 20, 2015 which is incorporated herein in its entirety. 
     TECHNICAL FIELD 
     This invention relates generally to analog to digital converters and in particular machine-learning multiplying analog to digital converters. 
     BACKGROUND 
     Embedded sensing systems conventionally perform A-D conversion followed by signal processing to apply specific analyses on sensor data. In many applications, the analysis of interest is inference (e.g., classification). The challenge is that, increasingly, the sensor signals are too complex to model analytically. Machine-learning algorithms are gaining prominence since they overcome the need to model signals analytically, instead enabling data-driven methods of training a classifier. Prior classification systems employ a basic architecture that receives an analog signal for classification. The signal is amplified via an instrumentation amplifier. The amplified signal is fed into an analog to digital converter (ADC). The ADC output is then subjected to a series of digital multiply and accumulate operations (MAC). The result of these amplification, ADC and MAC operations is a classification output. What is needed is a new hardware architecture that enables direct data conversion of information during the ADC process. 
     SUMMARY OF THE INVENTION 
     A multiplying analog to digital converter (ADC) is disclosed. The multiplying ADC includes a successive-approximation-register (SAR) analog to digital converter (DAC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5. 
     The multiplying ADC may also include a multiplying input, configured to receive a quantized multiplier. The quantized multiplier may be configured with a sign bit, a scalar value and an exponent. The scalar value may have a value between 1 and 2. The multiplying ADC may include an analog storage location for storing the input signal for analog to digital conversion with multiple quantized multipliers. The analog storage location may comprise a capacitor. 
     A method of implementing a multiplying analog to digital converter is also disclosed, the method includes providing a successive-approximation-register (SAR) analog to digital converter (DAC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is provided, the feedback attenuator being disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is provide, the barrel shifter being configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5. 
     A multiplying input may be provided, the multiplying input being configured to receive a quantized multiplier. The quantized multiplier may be configured with a sign bit, a scalar value and an exponent. The scalar value may have a value between 1 and 2. The multiplying ADC may include an analog storage location for storing the input signal for analog to digital conversion with multiple quantized multipliers. The analog storage location may comprise a capacitor. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIG. 1A  is block diagram of a conventional classification system; 
         FIG. 1B  is a block diagram of an ensemble of K linear classifiers combined with linear feature extraction F in the matrix H, for implementation with a multiplying analog to digital converter (ADC); 
         FIG. 1C  is a pictorial diagram showing how AdaBoost enables an ensemble of K linear classifiers combined with linear feature extraction F in the matrix H; 
         FIG. 2A  is a block diagram of a multiplying ADC  30 , which implements multiplication within an 8-bit successive-approximation-register (SAR) architecture; 
         FIG. 2B  is a waveform diagram for the block diagram of  FIG. 2A ; 
         FIGS. 3A-3C  show the multiplying ADC results in multiplier quantization error that scales with 2MD (and thus MQUANT), giving relatively constant output SQNR for multiplication over an arbitrarily large range of multipliers; 
         FIG. 4  is a schematic diagram showing the SAR feedback path, composed of CapDAC and feedback attenuator (FB-Divider), wherein the feedback attenuator applies a switchable attenuation factor of β through capacitive division implemented with C MULT ; 
         FIGS. 5A and 5B  show two application demonstrations implemented via the multiplying ADC achieve classification performance near an SVM with estimated 9.7× and 23× lower energy, respectively, compared to a conventional system; 
         FIGS. 6A-6D  are graphs showing measurement summaries of a prototype multiplying ADC; 
         FIG. 6E  is a table that summarizes the measurement results of the prototype multiplying ADC shown in  FIG. 7 ; 
         FIG. 7  is a Die photograph of multiplying ADC, implemented in 130 nm CMOS; 
         FIGS. 8A-8D  are graphs showing the analysis of demonstrated applications shows the comparative benefits achieved by multiplying ADC, compared to conventional linear-quantized multiplication; 
         FIGS. 9A-9D  are graphs and calculations showing detailed energy comparison of the demonstrated applications, using conventional system implementation versus multiplying ADC implementation; 
         FIG. 10A  is a block diagram of an AdaBoost trainer; and 
         FIG. 10B  is a block diagram of an EACB trainer. 
     
    
    
     DETAILED DESCRIPTION 
     Disclosed herein is an analog to digital converter (ADC) that integrates multiplication of input samples. This architecture may also be configured to multiply the input samples with an arbitrary matrix. This enables direct data conversion of information for classification. The multiplying ADC is demonstrated in two applications, (1) ECG-based cardiac-arrhythmia detection and (2) image-pixel-based gender detection, wherein feature extraction and the classification kernel are computed within the ADC operation. 
       FIG. 1A  is block diagram of a conventional classification system  10 . The system  10  includes an ADC  12  configured to receive an analog input (sensor data). The system  10  also includes a feature extractor  14  and a classifier  16  configured to generate a classification output d. The ADC generates a Conventional analog computation faces two key challenges: (1) the energy scales severely with the dynamic range, making multiplication particularly problematic; and (2) the ability to implement specific functions is limited by both the precision and the particular transfer functions achievable by circuit physics. Dynamic range in the multiplying ADC is addressed by exploiting mixed digital and analog multiplication, as described below. 
       FIG. 1B  is a block diagram of classifier  20  configured with ensemble of K linear classifiers  22 . The need to implement precise functions is overcome by employing a machine-learning algorithm known as Adaptive Boosting (AdaBoost). As shown in  FIG. 1C , AdaBoost enables the ensemble of K linear classifiers {right arrow over (C l )} which can be combined with linear feature extraction F in the matrix H, for implementation with a multiplying ADC combined with linear feature extraction F in the matrix H. In general, AdaBoost uses an ensemble of weak classifiers to form a strong classifier (in machine learning, a weak classifier is defined as one that cannot be trained to fit arbitrary data statistics, a strong classifier is defined as one that can). The benefit of AdaBoost is that very low performing weak classifiers can be used, with required performance only marginally better than 50/50 guessing. This opens the possibility for circuit implementations preferred in terms of energy and hardware efficiency. In particular, linear classifiers can be used, which simply involve a dot product between a feature vector {right arrow over (u)} (derived from N-point input data {right arrow over (x)}) and a classification vector {right arrow over (C l )}. 
     As shown in  FIG. 1A , typically {right arrow over (u)} must be derived explicitly because conventional strong classifiers apply non-linear operations. However, if feature extraction is linear, as is often the case [e.g., the applications considered use discrete wavelet transform (DWT) and principal component analysis (PCA)], then an ensemble of K linear classifiers {right arrow over (c 1 )} . . . {right arrow over (c K )} can be combined with the feature-extraction matrix F, giving a single K×N matrix H. As disclosed herein, the number of weak classifiers K required in AdaBoost is typically low, making system energy with the multiplying ACD of same order as just an ADC. 
       FIG. 2A  is a block diagram of a multiplying ADC  30 , which implements multiplication within an 8-bit successive-approximation-register (SAR) architecture at negligible energy cost. The multiplying ADC  30  is based on a SAR ADC which basically implements a binary search algorithm. The ADC  30  includes a comparator  36  with a sample input  52  and an output  32  tied to a feedback path or loop  38 . The feedback path  38  is coupled to SAR logic  34 . To implement a binary search algorithm, an 8-bit register in the SAR logic  34  is coupled to digital to analog converter (DAC)  48 . The DAC  48  output is generally varied via a binary search until the output of the DAC equals the sample signal at the inverting input of the comparator  36 . The contents of the SAR logic register is output to accumulator  46  and ultimately stored as the ADC output in register  42 . 
     The multiplying ADC  30  implements mixed analog/digital multiplication, with analog multiplication implemented passively via feedback attenuation by a feedback attenuator  44  and digital multiplication implemented by a barrel shifter  50 . Implementing attenuation in the feedback loop results in multiplication at the comparator output  32 . Since the feedback attenuation is implemented using passive components, the resulting multiplication is more precise than implementations using active components to implement multiplication. In this example the feedback attenuator  44  is implemented using a capacitor divider network, additional detail are provided in  FIG. 4 . To overcome dynamic-range limitations, the ADC  30  is configured with a multiplying input  56 , configured to receive a quantized multiplier. Multiply control logic  60  generally separates the quantized multiplier M QUANT  coupled to the multiplying input  56  as follows. The quantized multiplier M QUANT  is broken into three parts: a sign bit M S , a 4-bit scalar (unsigned analog multiplier) represented by M A , and a 5-bit signed exponent M D . The final M QUANT =M S ×M A ×2 M     D   . The feedback loop  38  is coupled to a feedback attenuator  44  (FB-Divider) to implement the 4-bit scalar (unsigned analog multiplier) represented by M A . 
     M A  is applied passively through attenuation in the feedback path via the feedback attenuator  44 . Feedback attenuator  44  implements feedback attenuation β ranging from 1 to 16/(16+15)= 16/31, realizing multiplication by M A  with values ranging from 1 to 31/16 (in steps of 1/16). The ADC supports signed inputs with respect to a nominally mid-rail bias V MID . Signed multiplication is thus supported by using M S  to either pass through or give the negative of the ADC code. Digital multiplication, based on the exponent M D , is then performed on the resulting 8-b code via barrel shifter  50 , implementing multiplication by powers of 2 (2 −16 , 2 −15 , . . . 2 14 , 2 15 ). With a 5-bit M D , shifting by up to 32 bits is supported, giving a 40-bit output. It should be understood additional bits may be provided to increase the dynamic range of the ADC  30 . ADC  30  also includes control inputs SAMP and  SAMP  configured to acquire an input signal for conversion as shown generally by reference number  58 . An analog storage location  54  may be provided to hold the sample signal provided at sample input  52  for multiple A to D conversion. A plurality of quantized multipliers may then be coupled to the multiplying input  56  to support matrix multiplication. 
       FIGS. 3A-3B  expresses the overall quantized multiplier value M QUANT  (with respect to an ideal, unquantized multiplier M IDEAL ) and illustrates the multiplication achieved. The disclosed approach has two benefits. First, regardless of the overall multiplier, the analog input range is reduced by only the maximum value of M A , namely a factor of 31/16≈2 (giving analog input range 0.35V to 0.85V). Second, through barrel shifting, arbitrarily large multiplier values can be supported at low hardware cost of additional bits in the barrel shifter. The resulting multiplication has quantization noise that scales with 2 M     D    (i.e., with the multiplier value). As seen in the simulation of  FIG. 3C , traditional linear-quantized multiplication (shown for the 8- to 13-b levels) causes output SQNR to vary widely with the multiplier, resulting in inefficient use of dynamic range. This particularly degrades performance for lower-valued multipliers, which often occur with equal or substantially higher frequency in signal-processing applications (such as the two considered). Alternatively, the multiplying ADC results in relatively constant SQNR over an arbitrarily large range of multipliers, achieving performance substantially greater than the 8-b level, yet with passive 4-b multiplication hardware (FB-divider) and barrel shifting. 
     To implement matrix multiplication, an MMADC input sample must be multiplied by the K elements in each column of H. To realize this, input sampling is performed on a separate capacitor C SAMP , rather than within the DAC  48  (whose charge must be reset following each conversion). Thus, as shown in the waveforms of  FIG. 2B , an input sampled once (by SAMP) can be applied to the multiplying ADC multiple times (enable by CNVRT) with different multiplier values (M A , M D ). Row-wise accumulation of products is then performed by a digital adder (not implemented on the chip). Since the sampled input must be held for the duration of K conversions, leakage is a concern. The sampling switch consists of a series of two CMOS transmission gates (as shown in  FIG. 1 ), exploiting the stacked effect to exponentially reduce leakage. For the analog input range, simulated sample error &lt;0.5 LSB is achieved for K up to 50. 
       FIG. 4  shows the DAC  48  (CapDAC) and feedback attenuator  44  (FB-Divider). To enable bipolar inputs (and signed multiplication), both the output of the feedback attenuator  44  and the output of the CapDAC  48  are switched to V MID  at the start of a conversion (i.e., CNVRT=0). At the same time, feedback attenuation β is set by C MULT , by switching in composing unit capacitors. Nominally, the unit capacitors have a value C M  set to C DAC ∥C C . Using, C C ≈380 fF, a C M  of modest value is required (˜25 fF). Regarding parasitic capacitances, thanks to switching to V MID , C P,DAC  does not degrade ADC linearity. C P,MULT  leads to a constant term in the denominator of β, causing error in the analog multiplier (measured below). Further, separating input sampling from the CapDAC causes the voltage of critical bit decisions to vary with input, leading to non-linearity (measured below) due to variation of sampling-switch charge injection and comparator offset. However, both error sources are readily overcome thanks to the AdaBoost algorithm, where iterative training of weak classifiers enables errors in all i−1 iterations to be compensated during training of the i th  classification vector {right arrow over (C l )}. 
       FIG. 5  shows the parameters and measured performance of two applications implemented using the multiplying ADC. Patient ECG from and image-pixel data from are replayed by an arbitrary waveform generator and presented to the multiplying ADC along with multiplier values for the matrix H, which is formed from the feature-extraction matrix F (DWT and PCA, respectively) and the classification vectors {right arrow over (c 1 )} . . . {right arrow over (c K )}, derived from off-line training. As conventional, 10-fold validation is performed to divide the dataset for training and testing. The performance of a MATLAB implemented support-vector machine (SVM), a widely-used non-linear strong classifier, is also shown, illustrating that the multiplying ADC successfully achieves strong classification performance, near an ideal SVM. Convergence is achieved with 5 and 1 weak classifiers, respectively, giving overall energy savings of 9.3× and 24× compared to a conventional system, as in  FIG. 1 . 
       FIG. 7  is a Die photograph the multiplying ADC is prototyped in a 130 nm CMOS process.  FIG. 6  summarizes the measurement results. The multiplying ADC performs conversions at a rate up to 20 kS/s (scalable down at constant energy). Slight deviation of the multiplier value is measured (˜9%) due to C P,MULT . The SNDR is measured to be 45.8 dB (low frequency) and 38.9 dB (near Nyquist), giving an ADC FoM. 
       FIGS. 8A-8D  are graphs showing the analysis of demonstrated applications shows the comparative benefits achieved by multiplying ADC, compared to conventional linear-quantized multiplication. The histogram of multiplier values shows that small-valued multipliers occur with high frequency. Compared with 5-b linear quantization of the multiplier value, the multiplying ADC, which also performs 5-b quantization of the multiplier value [1-b sign (MS) and 4-b analog multiplier (MA)] but in conjunction with barrel shifting, achieves much lower effective quantization error. The resulting quantization error of multiplication (assuming uniformly distributed multiplicand) is shown in the output SQNR plot of  FIG. 3C . 
       FIGS. 9A-9D  are graphs and calculations showing detailed energy comparison of the demonstrated applications, using conventional system implementation versus multiplying ADC implementation. The estimated energy numbers for digital multiplication and addition are derived from post-layout simulation in the 130 nm technology employed (and are also found to be consistent with previous reports based on prototype measurements). By eliminating the need for explicit multiplication for feature extraction and classification, the multiplying ADC results in estimated energy savings of 9.7× and 23×, respectively. 
     It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements.