Abstract:
An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark.

Description:
REFERENCE TO RELATED APPLICATION 
     This application claims the right of priority based on U.S. Provisional Application No. 61/676,206, filed on Jul. 26, 2012 and the content of which is hereby incorporated by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present application relates to an aggregation of semiconductor devices and the method thereof. 
     DESCRIPTION OF BACKGROUND ART 
     When the semiconductor devices, e.g. light-emitting diodes and solar cell, are delivered, the semiconductor devices have to be sorted by a sorter and arranged in a specific type for the other equipment to pick up thereof. Conventionally, the semiconductor devices are sorted and arranged in a package of which the shape is square, and the equipment usually is able to access the package to pick up the semiconductor devices. But, the package, of which the shape is square, is not economical. Thus, the inventors of the application are motivated to provide a more economical method for carrying more semiconductor services at a time. 
     SUMMARY OF THE DISCLOSURE 
     An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark. 
     A method of manufacturing an aggregation of semiconductor devices comprising the steps: providing a first layer comprising an adhesive glue layer formed thereon; sequentially addressing and adhering a plurality of semiconductor devices to the adhesive glue layer; providing a second layer; and forming a second region by adhering the second layer to the first layer by the adhesive glue layer to cover the plurality of semiconductor devices, wherein the shape of the second region comprises a curve and a mark. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A˜C  show the aggregation of a plurality of semiconductor devices; 
         FIG. 2  shows that the aggregation of a plurality of semiconductor devices according to another embodiment. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings hereafter. The following embodiments are given by way of illustration to help those skilled in the art fully understand the spirit of the present application. Hence, it should be noted that the present application is not limited to the embodiments herein and can be realized by various forms. Further, the drawings are not precise scale and components may be exaggerated in view of width, height, length, etc. Herein, the similar or identical reference numerals will denote the similar or identical components throughout the drawings. 
       FIG. 1A  shows the aggregation  1  of a plurality of semiconductor devices  4 . The aggregation  1  comprises a first layer  2  for carrying the plurality of semiconductor devices  4 , a second layer  7  for covering the plurality semiconductor devices  4  and adhering to the first layer  2  such that the plurality of semiconductor devices  4  is between the first layer  2  and the second layer  7 . The shape of the first layer  2  and/or the second layer  7  comprises rectangle, square, or circle. The plurality of semiconductor devices  4  is arranged by a sorter to form an arrangement  3  as approximately a circle or a regular polygon with the number of sides being greater than 4, e.g. a regular pentagon, hexagon, heptagon, octagon, etc. Namely, the perimeter of the arrangement  3  is approximately a circle or a regular polygon with the number of sides being greater than 4. The arrangement  3  is approximately at the center of the aggregation  1 . In one embodiment, the shape of the arrangement  3  comprises a circle with a mark  3   b , e.g. a flat side, for aligning the aggregation  1  in a tester or a sorter to a predetermined orientation. The shortest distance from the center of the arrangement  3  to the mark  3   b  is less than the radius of the arrangement  3 . The mark  3   b  can also be a notch, or a mark that substantially break the continuity, smooth, or regularity of a circle or a regular polygon. The mark  3   b  is preferred parallel with one side of the first layer  2  or the second layer  7 .  FIG. 2  shows that the plurality of the semiconductor devices  4  is sequentially arranged from column to column by following the direction  4   d , and the rightmost column  4   c  of the arrangement  3  composed of the mark  3   b . In another embodiment, if the arrangement  3  is partially arranged, the shape of the arrangement  3  comprises the mark  3   b , a second flat side  3   c  parallel to the mark  3   b , and two opposite curves  3   d ,  3   e  connecting the mark  3   b  and the second flat side  3   c . A tag  9  is on and at one corner of first layer  2 . It is preferred that the tag  9  is at the up-right corner of the first layer  2  with the mark  3   b  being parallel with the left side of the first layer  2 , for identifying the product information of the plurality of semiconductor devices  4 , such as the bin code, the customer number, the wafer ID, . . . etc. The diameter  3   a  of the arrangement  3  is not greater than a predetermined value, e.g. 15 cm; or preferred not greater than 7 cm. The predetermined value may be limited by the process or equipment for testing, sorting, or packaging the semiconductor device  4  of the aggregation  1 . The plurality of semiconductor devices  4  comprises chips diced from a wafer. The chips can be LED chips, photovoltaic chips, or other semiconductor chips. If the plurality of semiconductor devices  4  are LED chips, the method for forming the aggregation  1  comprises the steps of epitaxially forming an semiconductor light-emitting stacked layer on a substrate wafer, processing the semiconductor light-emitting stacked layer to form a plurality of chip regions and a plurality of first and second conductive pads, bonding the semiconductor light-emitting stacked layer to a supporter, such as a blue tape, and dicing the semiconductor light-emitting stacked layer, according to the plurality of chip regions, into individual LED chips each of which comprises a first conductive pad and a second conductive pad. Then, the LED chips are tested by a tester. Finally, the LED chips are sorted according to a testing result from the tester and a predetermined bin structure in a sorter into a variety of bin codes defined in the predetermined bin structure. The LED chips with the same bin code are arranged together within one arrangement, e.g. the arrangement  3  as shown in  FIG. 1A . The predetermined bin structure is normally defined according to an electrical or luminous characteristic, e.g. radiation power, luminous flux, dominant wavelength, full width at half maximum (FWHM) of a luminous spectrum, color temperature, color rendering index, etc. The predetermined bin structure is normally defined by the manufacturer or a customer of the manufacturer. The process of a tester or a sorter is well-known for those skilled in the art, and is not necessary to be disclosed in detail. 
       FIG. 1B  shows the cross-section diagram of AA′ of the aggregation  1  in  FIG. 1A . The first layer  2  has a first surface  21  and a second surface  22 , wherein the first surface  21  is non-adhesive. An adhesive glue layer  23  is formed on the second surface  22 . The plurality of semiconductor devices  4  is adhered to the second surface  22  of the first layer  2  through the adhesive glue layer  23 . The first layer  2  is capable of being expanded to over 2 times of the original area. The first layer  2  comprises a flexible material or polymer, such as PVC, PE, PP, PU, PEV, or the mixture thereof. The first layer  2  is preferably cut from a tape, such as blue tape. The second layer  7  comprises a third surface  73  facing the first layer  2 . The third surface  73  comprises a first region  71  and a second region  72 . The first region  71  is adhered to the second surface  22  of the first layer  2  through the adhesive glue layer  23 . The second region  72  is on the plurality of semiconductor devices  4  and not adhered to the second surface  22  of the first layer  2 . The second region  72  of the second layer  7  and the second surface  22  of the first layer  2  are not contacting with each other, and a space  4   a  is formed between adjacent two of the plurality of semiconductor devices  4 . The second layer  7  is capable of being easily detached from the second surface  22  without damaging the third surface  73  and the adhesive glue layer  23 . The second layer  7  comprises a paper, a plastic film, or glass. The material of the plastic film comprises BCB. The paper is preferably selected from the group consisting of Super-calendered Kraft paper (SCK), clay coated Kraft paper (CCK), machine finished Kraft paper (MFK), and machine glazed paper (MG). The material of the plastic film comprises polymer, or selected from the group consisting of PET, PP, HDPE, and LDPE. In one embodiment of the present disclosure, the second layer  7  is preferably a releasing paper. 
       FIG. 1C  shows the enlarge view of the region  8  in  FIG. 1A . Each of the semiconductor devices  4  having an upper surface  45  and a back surface  44  opposite to the upper surface  45 , wherein a first conductive pad  41  and a second conductive pad  42  are formed on the upper surface  45 . The back surface  44  is adhered to the second surface  22  of the first layer  2  through the adhesive glue layer  23 . The first conductive pad  41  and the second conductive pad  42  are used for electrical connecting, e.g. wire bonding, to an external device. The semiconductor devices  4  are aligned to each other, and each of the plurality of semiconductor devices  4  is allocated within a predetermined area  4   b  of the first layer  2 , wherein the predetermined area  4   b  has a length  5  and a width  6 . Each of the length  5  and the width  6  is between 50 um and 5 mm, and preferably between 100 um and 3 mm. The length  5  and the width  6  depend on the size of the semiconductor device  4 , and can be the same or different from each other. For example, for the arrangement  3  with a diameter  3   a  of 7 cm, when the length  5  is about 1050 μm and the width  6  is about 500 μm, there are 7325 semiconductor devices in the arrangement  3 . When the length  5  is about 500 μm and the width  6  is about 500 μm, there are 15384 semiconductor devices arranged in the arrangement  3 . When the length  5  is about 800 μm and the width  6  is about 800 μm, there are 6009 semiconductor devices arranged in the arrangement  3 . 
     
       
         
               
             
               
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 The number of the semiconductor devices in the arrangement with a 
               
               
                 diameter of 7 cm vs. different sizes of the deposit region 
               
             
          
           
               
                   
                 The 
                 The 
                 The number of the 
               
               
                   
                 length of the 
                 width of the 
                 semiconductor 
               
               
                   
                 predetermined 
                 predetermined 
                 devices in the 
               
               
                   
                 area 
                 area 
                 arrangement 
               
               
                   
                   
               
             
          
           
               
                 Deposit region 1 
                 1050 μm  
                 500 μm 
                 7325 
               
               
                 Deposit region 2 
                 500 μm 
                 500 μm 
                 15384 
               
               
                 Deposit region 3 
                 800 μm 
                 800 μm 
                 6009 
               
               
                   
               
             
          
         
       
     
     The foregoing description of preferred and other embodiments in the present disclosure is not intended to limit or restrict the scope or applicability of the inventive concepts conceived by the Applicant. In exchange for disclosing the inventive concepts contained herein, the Applicant desires all patent rights afforded by the appended claims. Therefore, it is intended that the appended claims include all modifications and alterations to the full extent that they come within the scope of the following claims or the equivalents thereof.