Abstract:
An image sensor includes a semiconductor layer that filters light of different wavelengths. For example, the semiconductor layer absorbs photons of shorter wavelengths and passes more photons of longer wavelengths such that the longer wavelength photons often pass through without being absorbed. An imaging pixel having a photodiode is formed near a front side of the semiconductor layer. A dopant layer is formed below the photodiode near a back side of the semiconductor layer. A mirror that primarily reflects photons of longer visible wavelengths is disposed on the back side of the semiconductor layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a Continuation of U.S. patent application Ser. No. 12/129,599, filed on May 29, 2008. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to imaging sensors, and in particular but not exclusively, relates to front side illuminated imaging sensors. 
     BACKGROUND INFORMATION 
     Integrated circuits have been developed to reduce the size of components used to implement circuitry. For example, integrated circuits have been using ever-smaller design features, which reduces the area used to implement the circuitry, such that design features are now well under the wavelengths of visible light. With the ever-decreasing sizes of image sensors and the individual pixels that are part of a sensing array, it is important to more efficiently capture charges that are formed when incident light illuminates the sensing array. Thus, more efficiently capturing photonically generated charges helps to maintain or improve the quality of electronic images captured by the sensing arrays of ever-decreasing sizes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
         FIG. 1  is a block diagram illustrating an imaging sensor, in accordance with an embodiment of the invention. 
         FIG. 2  is a cross-sectional view of an imaging pixel of a frontside illuminated imaging sensor, in accordance with an embodiment of the invention. 
         FIGS. 3A-3D  illustrate a process of forming an imaging pixel of a frontside illuminated imaging sensor, in accordance with an embodiment of the invention. 
         FIG. 4  is a circuit diagram illustrating pixel circuitry of two four-transistor (“4T”) pixels within a frontside illuminated imaging array, in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of an image sensor with backside passivation and metal layers are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. 
     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The term “or” as used herein is normally meant to encompass a meaning of an inclusive function, such as “and/or.” 
     Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. “Quantum efficiency” is defined herein as the ratio of the number of carriers generated to the number of photons incident upon an active region of an imaging sensor. “Dark current” is defined herein as the current that flows in an imaging sensor in the absence of incident light on the imaging sensor. “White pixel defect” is defined herein as a pixel in an imaging sensor that includes an active region that has an excessive amount of current leakage. 
       FIG. 1  is a block diagram illustrating an imaging sensor  100 , in accordance with an embodiment of the invention. The illustrated embodiment of imaging sensor  100  includes a pixel array  105 , readout circuitry  110 , function logic  115 , and control circuitry  120 . 
     Pixel array  105  is a two-dimensional (“2D”) array of imaging sensors or pixels (e.g., pixels P 1 , P 2  . . . , Pn). In one embodiment, each pixel is an active pixel sensor (“APS”), such as a complementary metal-oxide-semiconductor (“CMOS”) imaging pixel. As illustrated, each pixel is arranged into a row (e.g., rows R 1  to Ry) and a column (e.g., column C 1  to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object. 
     After each pixel has acquired its image data or image charge, the image data is readout by readout circuitry  110  and transferred to function logic  115 . Readout circuitry  110  may include amplification circuitry, analog-to-digital conversion circuitry, or otherwise. Function logic  115  may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry  110  may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels simultaneously. 
     Control circuitry  120  is coupled to pixel array  105  to control operational characteristic of pixel array  105 . For example, control circuitry  120  may generate a shutter signal for controlling image acquisition. 
       FIG. 2  is a cross-sectional view of an imaging pixel  200  of a front side illuminated imaging sensor. Imaging pixel  200  is one possible implementation of at least one pixel of pixel array  105  shown in  FIG. 1 . The illustrated embodiment of imaging pixel  200  includes a semiconductor layer (i.e., P-type substrate  205 ). Formed within substrate  205  is a photodiode (i.e., N −  region  210 ), a P +  pinning layer  215 , a P +  implantation layer  220 , a shallow trench isolation (“STI”)  225 , a transfer gate  230 , and a floating diffusion (i.e., N +  region  235 ). To help illustrate certain features, the Figure is not necessarily drawn to scale. 
     Imaging pixel  200  is photosensitive to light incident upon the front surface  207  of substrate  205 . In imaging pixel  200 , the majority of photon absorption occurs near the back surface  209  of substrate  205 . To separate the electron-hole pairs created by photon absorption and drive the electrons to N− region  210 , an electric field near back surface  209  of substrate  205  is used. Thus a highly doped P +  implantation layer  220  can be created by doping the back surface  209  of substrate  205  to create this electric field. In one embodiment, P +  implantation layer  220  is created using boron implantation and laser annealing. 
     As shown in  FIG. 2 , a P +  implantation layer is implanted to an implant depth  211 , such that there is a remaining substrate thickness  213 . In general, greater remaining substrate thickness increases sensitivity of the pixel for longer wavelengths, and increase crosstalk (resulting in reduced sensitivity. 
     In the illustrated embodiment, implant depth  211  represents the distance that P +  implantation layer extends into substrate  205  as measured from back surface  209 . Remaining substrate thickness  213  represents the distance from implant depth  211  to front surface  207 . In accordance with the embodiments disclosed herein, implant depth  211 , ion concentration of P +  implantation layer  220 , and/or remaining substrate thickness  213  may be selected as to increase (e.g., optimize) the spectral and overall performance of imaging pixel  200 . For example, by careful selection of implant depth  211 , ion concentration, and/or remaining substrate thickness  213 , the quantum efficiency and spectral performance of imaging pixel  200  may be increased. In addition, dark current may also be decreased. 
     In one embodiment, P +  implantation layer  220  is a highly doped boron implantation layer. The boron implantation layer may have a concentration of boron ions selected to increase the quantum efficiency of imaging pixel  200 . The boron implantation layer may also have a concentration of boron ions selected to decrease dark current. In one embodiment, boron implantation layer may have a graded concentration of boron ions, where there is a higher concentration of boron ions near back surface  209  than there are at implant depth  211 . For example, P +  implantation layer  220  may have a boron ion concentration near back surface  209  in the range of approximately 3×10 17  ions/cm 3  to approximately 5×10 19  ions/cm 3 , while the boron ion concentration near implant depth  211  may be approximately 1×10 14  ions/cm 3  to 3×10 15  ions/cm 3 . In one embodiment, the boron implant of P +  implantation layer  220  may be implemented using boron fluoride (BF 2 ) as the dopant, or diborane (B 2 H 6 ) as the dopant source. 
     As mentioned above, implant depth  211  may also be selected so as to increase quantum efficiency, to increase sensitivity to red and near-IR wavelengths, and to decrease dark current. In one embodiment, implant depth  211  is in the range of approximately 100 nm to approximately 400 nm as measured from the back surface of P+ layer  220 . P+ layer  220  is used to passivate the back side of P-type substrate  205  (in preparation for metal layer  222 , which would otherwise tend to capture liberated electrons) of imaging pixel  200 . (Metal layer  222  can also be comprised of silicides or other suitable reflective material.) 
     In one embodiment, remaining substrate thickness  213  may have preferred values. For example, a total of remaining substrate thickness  213  and P+ layer  220  may be approximately 1-4 microns, with an exemplary value of 3 microns. Remaining substrate thickness  213  can also be chosen such that metal layer  222  is used to primarily reflect red (and longer) wavelengths of light. Thus, the metal layer formed on the back surface of the semiconductor layer can be used to primarily reflect the photons having longer wavelengths towards the N −  region. Metal depth  215  of metal layer  222  generally can be any thickness that is suitable for reflecting light. 
     Chromatic light rays R, G, and B illustrate light of red, green, and blue wavelengths, respectively. The remaining substrate thickness is chosen such that blue and green light does not generally penetrate as deeply as do longer wavelengths of light within the substrate. Remaining substrate thickness  213  can thus be chosen so that the thickness of the substrate absorbs a majority of photons having shorter wavelengths (e.g., more than half of the photons having wavelengths shorter than red wavelengths are absorbed), while a larger proportion of photons having longer wavelengths are not absorbed. As mentioned above, remaining substrate thickness  213  can also be chosen such that metal layer  222  is used to primarily reflect red (and longer) wavelengths of light (e.g., more than 50% of the photons reflected by the metal layer  222  have red or longer wavelengths of light). Thus, the sensitivity of the pixel for red (and longer) wavelengths of light can be improved by providing metal layer  222 , which reflects the typically longer wavelengths back towards the front surface  207 , where additional electron hole pairs can be generated (and n-region  210  can capture the liberated electrons). The effective depth (e.g., distance of the top surface of metal layer  222  to front surface  207 ) can be selected such that a majority of the light reflected by metal layer  222  is a red wavelength (or longer). 
       FIGS. 3A-3D  illustrate a process of forming an imaging pixel  300  of an image sensor, in accordance with an embodiment of the invention. Imaging pixel  300  is one possible implementation of at least one pixel of pixel array  105  shown in  FIG. 1 . The illustrated embodiment of imaging pixel  300  shown in  FIG. 3A  includes a semiconductor layer (i.e., substrate  305 ), a protection oxide  310 , an interlayer dielectric  315 , and a metal stack  320 . Substrate  305  is illustrated as including shallow trench isolation (“STI”) trench, photodiode  325 , a floating diffusion (“FD”), and a pinning layer  330 . Metal stack  320  is illustrated as including metal interconnect layers M 1  and M 2 , and intermetal dielectric layers  340  and  345 . Also illustrated in  FIG. 3A  is a transfer gate  355 . 
     In the illustrated embodiment of  FIG. 3A , photodiode  325  is formed within substrate  305  and is configured to receive light from front surface  307 . Photodiode  325  is illustrated as a pinned photodiode by way of optional pinning layer  330 . In one embodiment, photodiode  325  may be an unpinned photodiode or a partially pinned photodiode. Additionally, photodiode  325  may be any photosensitive element, such as a photogate or photocapacitor. Furthermore, the term pixel as used herein is meant to encompass all pixel designs, including CCD pixels. 
     Also included in imaging pixel  300  is transfer gate  335  which is coupled to transfer charge that is accumulated in photodiode  325  to floating diffusion FD. In one embodiment, transfer gate  335  is a polycrystalline silicon (i.e., polysilicon) structure. Coupled to front surface  307  is protection oxide  310  and interlayer dielectric  315 . In one embodiment interlayer dielectric  315  is silicon oxide. 
     As shown in  FIG. 3A , imaging pixel  300  includes metal stack  320 . The illustrated embodiment of metal stack  320  includes two metal layers M 1  and M 2  separated by intermetal dielectric layers  340  and  345 . Although  FIG. 3A  illustrates a two layer metal stack, metal stack  320  may include more or less metal layers for routing signals above front surface  307  of substrate  305 . In one embodiment metal interconnect layers M 1  and M 2  are a metal such as aluminum, copper, or alloys of various metals. In one embodiment, metal interconnect layers M 1  and M 2  are formed by way of sputtering, collimated sputtering, low pressure sputtering, reactive sputtering, electroplating, chemical vapor deposition or evaporation. In one embodiment, transfer gate  335  and floating diffusion FD are electrically coupled to one or more of metal interconnect layers M 1  and M 2  by way of a hole, via or other connection means (not shown) through protection oxide  310  and interlayer dielectric  315 . In one embodiment, a passivation layer (not shown) is disposed over metal stack  320 . 
     Now referring to  FIG. 3B , a boron implant is performed at back surface  309 . In one embodiment, the boron implant may be implemented using boron fluoride (BF 2 ) as the dopant, or diborane (B 2 H 6 ) as the dopant source. Improved performance of imaging pixel  300  may result from a dose range of boron ions  350  in the range of approximately 3×10 13  ions/cm 2  to approximately 5×10 15  ions/cm 2 . Further improved performance of imaging pixel  300  may result from a dose range of boron ions  350  in the range of approximately 1×10 14  ions/cm 2  to approximately 1×10 15  ions/cm 2 . 
     Turning now to  FIG. 3C , the resulting boron implantation layer  355  is shown. In one embodiment, implant depth  360  is in the range of approximately 100 nm to approximately 400 nm as measured from back surface  309 . In one embodiment, remaining substrate thickness  365  may have preferred values to reflect substantially red values of light (e.g., so that a majority of the reflected light is of a red wavelength or longer). For example, for a 1.75 micron pixel, remaining substrate thickness  365  may be approximately 3 microns. 
     As shown in  FIG. 3D , a metal layer  370  is formed on back surface  309 . An optional color filter  380  can be formed over the metal stack. For example, a pixel for detecting red light can include a color filter  380  that is red. 
       FIG. 4  is a circuit diagram illustrating pixel circuitry  400  of two four-transistor (“4T”) pixels within a backside illuminated imaging array, in accordance with an embodiment of the invention. Pixel circuitry  400  is one possible pixel circuitry architecture for implementing each pixel within pixel array  100  of  FIG. 1 , pixel  200  of  FIG. 2 , or pixel  300  of  FIG. 3D . However, it should be appreciated that embodiments of the present invention are not limited to 4T pixel architectures; but that 3T designs, 5T designs, and various other pixel architectures can be used. 
     In  FIG. 4 , pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuitry  400  includes a photodiode PD, a transfer transistor T 1 , a reset transistor T 2 , a source-follower (“SF”) transistor T 3 , and a select transistor T 4 . During operation, transfer transistor T 1  receives a transfer signal TX, which transfers the charge accumulated in photodiode PD to a floating diffusion node FD. 
     Reset transistor T 2  is coupled between a power rail VDD and the floating diffusion node FD to reset (e.g., discharge or charge the FD to a preset voltage) under control of a reset signal RST. The floating diffusion node FD is coupled to the gate of SF transistor T 3 . SF transistor T 3  is coupled between the power rail VDD and select transistor T 4 . SF transistor T 3  operates as a source-follower providing a high impedance output from floating diffusion node FD. Finally, select transistor T 4  selectively couples the output of pixel circuitry  400  to the readout column line under control of a select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuitry  120 . The TX signal, the RST signal, the SEL signal, VDD, and ground may be routed in pixel circuitry  400  by way of metal interconnect layers M 1  and M 2 . In one embodiment, transistors T 1 , T 2 , T 3 , and T 4 , photodiode PD and floating diffusion node FD may be connected as shown in  FIG. 4  by way of metal interconnect layers M 1  and M 2 . 
     The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
     These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.