Abstract:
A snubber circuit for use with, for example, a self-driven synchronous rectifier in a power converter is disclosed. The snubber circuit, in various embodiments, captures and recirculates energy from the leakage inductance of the converter in a substantially lossless manner. The snubber circuit comprises a capacitance for storing the energy accumulated in the leakage inductance of a transformer winding of the converter. The snubber circuit further includes a discontinuous inductor, and a switch for transferring, when on, the energy stored in the capacitance to the inductor. The energy in the inductor may then be discharged when the switch is off.

Description:
BACKGROUND OF THE INVENTION 
   Particularly in a bridge converter with self-driven synchronous rectifiers, there exists a large amount of leakage inductance energy that needs to be captured and either dissipated or recirculated. Otherwise, the synchronous rectifier (which is typically a MOSFET) will be subject to losses due to the leakage inductance energy imposed on the synchronous rectifier during switching transitions. This results in, among other things, reduced efficiency for the converter, and may require physically larger are more expensive components to accommodate the increased voltage levels. Moreover, dissipating the captured energy in a resistive element will produce a large amount of heat that must be managed and will also result in reduced efficiency. Accordingly, there exists a need for a mechanism to recirculate the captured leakage energy in an efficient manner. 
   SUMMARY OF THE INVENTION 
   In one general aspect, the present invention is directed to a snubber circuit for use with a self-driven synchronous rectifier in a power converter. The snubber circuit, in various embodiments, captures and recirculates energy from the leakage inductance of a transformer winding of the converter in a substantially lossless manner. According to various embodiments, the snubber circuit comprises a capacitance for storing the energy accumulated in the leakage inductance of the transformer winding of the converter. The snubber circuit further includes a discontinuous inductor, and a switch for transferring, when on, the energy stored in the capacitance to the inductor. The energy in the inductor may then be discharged when the switch is off. 
   According to various implementations, the switch may be p-channel MOSFET and the control (gate) terminal of the switch may be responsive to the voltage across the synchronous rectifier. For example, the switch may be on when the synchronous rectifier is on. Further, the discontinuous winding may include first and second windings connected to the output of the power converter. The second winding may have more windings than the first winding, and the energy transferred to the inductor may be discharged through a diode connected to the second winding. In addition, for each synchronous rectifier in the converter, the snubber circuit may include a diode for transferring the leakage inductance energy of the transformer winding to the capacitance when the associated synchronous rectifier is off. 
   In another general aspect, the present invention is directed to a power converter. According to various embodiments, the power converter comprises a transformer winding including a leakage inductance and at least one self-driven synchronous rectifier for rectifying a voltage across the transformer winding. The power converter further includes a snubber circuit, such as described above, for capturing and recirculating the energy from the leakage inductance of the transformer winding. 
   According to various implementations of the snubber circuit, as the peak voltage on the capacitance increases, the peak current in the inductor increases, and thereby the energy captured and recirculated increases. This natural tendency allows the snubber circuit to maintain a constant peak voltage on the synchronous rectifiers under different load conditions, and keeps the snubber circuit working just as hard as it needs to. These and other benefits of the present invention will be apparent from the description below. 

   
     DESCRIPTION OF THE FIGURES 
     Various embodiments of the present invention are described herein by way of example in conjunction with the following figures, wherein: 
       FIG. 1  is a schematic diagram of a power converter including a snubber circuit according to various embodiments of the present invention; 
       FIGS. 2   a–d  are idealized timing diagrams illustrating the operation of the converter of  FIG. 1  according to various embodiments of the present invention; and 
       FIGS. 3   a–e  include idealized voltage and current waveforms for components of the power converter of  FIG. 1  according to various embodiments of the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 1  is a diagram of a power converter  10  for converting an input voltage (Vin) to an output voltage (Vout) to power a load  12  according to various embodiments of the present invention. In the illustrated embodiment, the power converter  10  has a half-bridge topology, including two primary switches Q 10 , Q 11 , which may be alternately turned on and off in a periodic fashion by a control circuit (not shown) to couple the input power (Vin) to a main power transformer T 1 . The control circuit may also introduce a dead time between the on periods of the primary switches Q 10 , Q 11 , as shown in the timing diagrams of  FIG. 2 , to regulate the output, to avoid cross-conduction of the switches Q 10 , Q 11 , and to possibly realized reduced switching losses due to reduced voltage switching (e.g., zero voltage switching). The control circuit may be an open-loop control circuit (e.g., a fixed duty cycle controller) or a closed-loop control circuit (e.g., a PWM controller), and may include a commercially available controller chip. The primary switches Q 10 , Q 11  may be transistors, and are preferably MOSFETs. 
   The converter  10  of  FIG. 1 , employing the half-bridge topology, includes two capacitors C 10 , C 11  connected across the input in a center-tap configuration. The voltage across each capacitor is Vin/2. 
   In the illustrated embodiment, the transformer T 1  includes one primary winding P 1  and two secondary windings S 1 , S 2 . Two synchronous rectifiers Q 1 , Q 2  are used to rectify the voltage across the first secondary winding S 1 . The synchronous rectifiers (“SRs”) Q 1 , Q 2  may be transistors, and are preferably MOSFETs. The SRs Q 1 , Q 2  in  FIG. 1  are self-driven, meaning they are driven by a voltage on a secondary winding of the main power transformer T 1 . In the example of  FIG. 1 , the SRs Q 1 , Q 2  are driven by a voltage across the second secondary winding S 2  of the transformer T 1 . Therefore, as shown in the idealized timing diagrams of  FIG. 2 , the SR Q 1  is on (t 1  to t 4 ) when the primary switch QI 0  is off, and the SR Q 2  is on (t 0  to t 2  and t 3  to t 4 ) when the primary switch Q 11  is off. Thus, the SRs Q 1 , Q 2  may be simultaneously on for periods (t 1  to t 2  and t 3  to t 4 ) of the switching cycle τ of the converter  10 . Also, the first secondary winding S 1  of the transformer T 1  has a leakage inductance, which is shown discreetly in  FIG. 1  as Llkg 1  and Llkg 2 . 
   In the embodiment of  FIG. 1 , the converter  10  includes a current doubler configuration. As such, the converter  10  includes two output inductors L 1 , L 2 , each carrying half the load current and operating at half the switching frequency of the primary switches Q 10 , Q 11 . An output capacitor C 3  is connected across the load  12 . When Q 1  is on and Q 2  is off (time t 2 –t 3  in  FIG. 2 ), both L 1 &#39;s and L 2 &#39;s current flows through Q 1  and during this time the current is ramped up in L 2  and ramped down in L 1  (L 1  is freewheeling), and when Q 1  is off and Q 2  is on (time t 0 –t 1 ), both L 1 &#39;s and L 2 &#39;s current flows through Q 2  and during this time the current is ramped up in L 1  and ramped down in L 2  (L 2  is freewheeling). When both SRs Q 1  and Q 2  are on (t 1  to t 2  and t 3  to t 4 ), both L 1  and L 2  are freewheeling or dumping energy. The effective ripple current seen by C 3  and the load is the sum of L 1  and L 2  currents and is twice the frequency of either single inductor. This effective ripple down slope is when both Q 1  and Q 2  are on and the up slope is when either Q 1  or Q 2  is off. 
   A relatively large leakage inductance for the main power transformer T 1  is required to control the shoot-through current through S 1  and the SRs Q 1  and Q 2  when they are both on as the transformer is energized by Q 10  or Q 11 , until one of the SRs turns off (t 2  or t 4 ). At the instance Q 10  or Q 11  turns on (t 2  or t 4 ), Q 1  and Q 2  are on which creates the shoot through condition or a short across S 1  and Llkg 1  and Llkg 2 . There must be enough leakage inductance associated with S 1  to allow S 2  to develop full voltage to turn off Q 1  or Q 2  before excessive current develops in S 1 /P 1 . This leakage inductance (Llkg 1  and Llkg 2 ), however, stores a significant amount of energy (0.5*LlkgI o   2 ) that must be controlled (i.e., either dissipated or recirculated) during each switching cycle. Otherwise, the energy in the leakage inductance will cause large voltage spikes at the drain terminals (Dr) of the SRs Q 1 , Q 2  at turn on of the SRs (in embodiments where the SRs Q 1 , Q 2  are MOSFETs). 
   The snubber circuit  20  shown in  FIG. 1  is used to capture and recirculate the energy stored in the leakage inductance of T 1 . In the illustrated embodiment, the snubber circuit  20  includes a pair of diodes D 1 , D 2  connected to the SRs Q 1 , Q 2 , respectively. The energy stored in the leakage inductance is transferred by the diodes D 1 , D 2  to a bulk capacitance C b . That is, when the SR Q 1  is off, the diode D 1  transfers the energy stored in the leakage inductance Llkg 1  to the bulk capacitor C b  and, similarly, when the SR Q 2  is off, the diode D 2  transfers the energy stored in the leakage inductance Llkg 2  to the bulk capacitor C b . The bulk capacitor C b  may be embodied as a single capacitor or, as shown in  FIG. 1 , may implemented as a pair of capacitors C b1  and C b2 . In certain applications, it may be preferable to implement the bulk capacitor C b  as such a pair of capacitors to reduce parasitic capacitance from the conduction paths between the SRs Q 1 , Q 2  and the bulk capacitors. The bulk capacitor C b  is preferably large enough to clamp the voltage across the SRs Q 1 , Q 2 , as shown in the waveforms of  FIGS. 3   a, b . For the sake of convenience, in the description to follow the bulk capacitor C b  is referred to as a single capacitor. 
   The bulk capacitor C b  is connected, in various embodiments, to the source terminal of a normally-on switch Q 3 . The switch Q 3  may be implemented as a p-channel MOSFET that is on when the gate-to-source voltage is below the threshold voltage and off when the gate-to-source voltage exceeds the threshold. The drain terminal of switch Q 3  is connected to an inductor L 3 , which is connected to the output of the converter  10 . The inductor L 3  preferably includes two magnetically coupled windings (L 3   a  and L 3   b ), as shown in  FIG. 1 , to insure that the inductor L 3  stays discontinuous. The second winding L 3   b  is connected to ground through a diode D 3 . Also, the winding L 3   b  connected to D 3  preferably has more windings than L 3   a  for reasons that will be apparent from the description to follow. 
   The gate (i.e., control) terminal of the switch Q 3  is controlled by the drains Dr of the SRs Q 1 , Q 2 , via RC circuits. That is, the drain of SR Q 1  is coupled to the gate of switch Q 3  via resistor R 2  and capacitor C 2 , and the drain of SR Q 2  is coupled to the gate of switch Q 3  via resistor R 1  and capacitor C 1 . Accordingly, when the SRs Q 1 , Q 2  are both on, the drain voltages of the SRs Q 1 , Q 2  are low such that the p-channel switch Q 3  is on due to the low voltage at the gate terminal, as shown in  FIG. 3   c . The switch Q 3  being on causes the energy stored in the bulk capacitor C b  to be transferred through the switch Q 3  to the inductor L 3 , as shown in  FIG. 3   d  by the rising current through the switch Q 3  during the time periods when Q 1  and Q 2  are both on. Then, when either Q 1  or Q 2  turns off, the drain terminal of the on-turning SR (either Q 1  or Q 2 ) will go high, causing the switch Q 3  to turn off, which causes the energy in the inductor L 3  to be discharged through the diode D 3 , as shown in the waveform of  FIG. 3   e . Thus, as the peak voltage increases on the bulk capacitor Cb, the peak current increases in the inductor L 3  and the energy removed by the snubber circuit  10  increases. This natural tendency allows the snubber circuit  10  to maintain a constant peak voltage on the drains of the SRs Q 1 , Q 2  under different load conditions, and keeps the snubber circuit  10  working just as hard as it needs to recirculate the captured leakage inductance energy. 
   As mentioned above, winding L 3   b  may have more windings than L 3   a  so that there will be enough time to discharge the energy in L 3  in the discharge portion of the L 3  cycle, as shown in  FIGS. 3   e . L 3  should be sized to control the amount of energy removed from the capacitor(s) Cb. 
   As shown in  FIG. 1 , the snubber circuit  20  may also include switches Q 4  and Q 5 . The switches Q 4  and Q 5 , which may be, for example, bipolar transistors as shown in the embodiment of  FIG. 1 , operate to control the on-time (or duty cycle) of the switch Q 3  to keep the current levels on the switch Q 3  suitably low. If the output voltage drops low the on times of Q 1  and Q 2  increase which increases the on time of Q 3  which increases the peak current seen by Q 3  and L 3 . The duty cycle of the switch Q 3  is controlled by the time constant of capacitors C 1 , C 2  and resistors R 4 , R 3 . In the embodiment of  FIG. 1 , the emitter terminal of the switch Q 5  is responsive to the output voltage (Vout) of the converter  10 . As such, when the output voltage Vout drops low, the switch Q 5  will turn on, which turns on switch Q 4 , causing C 1  and C 2  to discharge and thereby reducing the duty cycle of the switch Q 3 . Accordingly, in such embodiments, the snubber circuit  10  may run at a reduced level during fault or start-up conditions. 
   As used herein, the term “on” when used in reference to the state of a transistor means that the transistor is in a low impedance state, and the term “off” when used in reference to the state of a transistor means that the transistor is in a high impedance state. Also, the term “connected” as used herein does not necessarily mean directly connected, unless so noted. 
   In  FIG. 1 , the converter  10  is shown as a half-bridge converter with a current doubler secondary configuration. In other embodiments, different converter topologies may be used. In addition, although the embodiments of the snubber circuit  20  described herein are preferably used with self-driven synchronous rectifiers, it should be noted that the snubber circuit  20  could be used to snub the energy on any type of transistor where suitable, including, for example, a control-driven SR. 
   Although the present invention has been described herein with respect to certain embodiments, those of ordinary skill in the art will recognize that many modifications and variations of the present invention may be implemented. For example, there may be additional windings magnetically coupled to the main power transformer T 1 . Also, any of the semiconductor switches described herein may be implemented as a single semiconductor switch or a number of semiconductor switches connected in parallel. The foregoing description and the following claims are intended to cover all such modifications and variations.