Abstract:
A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner rounding process is performed after forming shallow trench isolations (STIs) and exposing the corner of the substrate at the active areas in the memory cell array region.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor manufacturing process and in particular to a method of forming a dynamic random access memory (DRAM) comprising deep trench capacitors and partial vertical transistors.  
         [0003]     2. Description of the Related Art  
         [0004]     When manufacturing memory products such as trench-type DRAM, stacked-type DRAM and FLASH memory, in order to reduce the size of a chip, the conventional semiconductor process uses self-aligned contact (SAC) technology to define a reduced distance between two adjacent gate conductive structures.  
         [0005]     A DRAM structure comprising a trench capacitor and a vertical transistor is shown in  FIG. 1 . A deep trench  18  is formed in a substrate  10  comprising silicon. A trench capacitor  14  is formed in the lower portion of the deep trench  18 .  
         [0006]     A diffusion region is formed in the substrate  10  between the trench capacitor  14  and the vertical transistor  16  as a buried strap  12 . The buried strap  12  is formed by driving the dopant in an electric layer (not shown) into the substrate  100  during a thermal process.  
         [0007]     The trench top oxide (TTO)  24  is deposited on the upper electrode to electrically isolate the trench capacitor  14  and the vertical transistor  16 .  
         [0008]     The vertical transistor  16  comprises a source  26 , a drain  12 , a gate oxide layer  28 , and a gate layer  20 . The gate layer  22  extends from the surface of the deep trench  18  to the substrate  100 .  
         [0009]     However, the corner  30  of the gate oxide layer  28  is usually thinner than the vertical sidewall of the deep trench  18  and the surface of the substrate  100  because of the different rate of oxidation. Thus, performance of the vertical transistor  16  is affected.  
       SUMMARY OF THE INVENTION  
       [0010]     Accordingly, an object of the invention is to provide a double corner rounding process for a partial vertical cell to avoid unacceptably thin corners of the gate oxide layer.  
         [0011]     To achieve the above objects, the present invention provides a double corner rounding process for a partial vertical cell. First, a substrate comprising a memory cell array region and a supporting region is provided. A first mask layer is formed on the substrate. A deep trench is formed in the first mask layer and the substrate in the memory cell region. A capacitor is formed in a lower portion of the deep trench. A first insulating layer is formed in the upper portion of the deep trench, with surface lower than that of the substrate. A second mask layer is formed in the deep trench, with a surface lower than that of the first mask layer. A photoresist layer is formed on the active areas of the substrate, such that a first portion of the substrate, covered by the photoresist layer, and a second portion of the substrate, not covered by the photoresist layer, are defined. Parts of the first mask layer not covered by the photoresist layer and the second portion of the substrate are removed until the surface of the second portion of the substrate is lower than that of the first mask layer. The photoresist layer and the second mask layer are removed. The edge of the first mask layer is then removed until the corner of the first portion of the substrate is exposed. A first rounding process is subsequently performed on the corner of the first portion of the substrate. A second insulating layer is conformally formed on the first mask layer, the first insulating layer, and the substrate. An insulating plug is formed on the second insulating layer, such that the surface of the insulating plug is substantially level with that of the second insulating layer on the substrate. The insulating plug, the second insulating layer, and the first mask layer in the memory cell array are removed to expose the corner of the first portion of the substrate. Finally, a second rounding process is performed on the corner of the substrate in the memory cell array region.  
         [0012]     The first mask layer comprises stacked silicon oxide and silicon nitride layers. The second insulating layer comprises silicon nitride. As well, the insulating plug comprises silicon oxide formed by high density plasma chemical vapor deposition (HDP CVD).  
         [0013]     The second mask layer is an organic anti-reflection coating layer.  
         [0014]     Removal of the edge of the first mask layer is performed by anisotropic etching, employing etching solution comprising hydrogen fluoride (HF) and ethylene glycol (EG).  
         [0015]     The first rounding process comprises oxidizing the corner and the sidewall of the first portion of the substrate to form a sacrificial oxide layer and removing the sacrificed oxide layer. Oxidization is performed by in-situ steam generation (ISSG).  
         [0016]     The second rounding process is performed by employing an oxidation agent and a HF solution by turns. The oxidation agent comprises H 2 O 2(aq)  and HNO 3(aq) .  
         [0017]     Transistors are further formed on the active area in the memory cell array region and in the supporting region.  
         [0018]     According to the present invention, the corner of the substrate of the active areas in the memory cell array region undergoes double rounding to increase the curvature radius, such that the thickness of the gate oxide layer following formation is substantially equal to that of the other regions of the gate oxide layer, resulting in improved transistor quality.  
         [0019]     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0021]      FIG. 1  is a cross-section of a conventional structure comprising a trench capacitor and a vertical transistor;  
         [0022]      FIGS. 2A through 2I  are cross-sections of a double corner rounding process for a partial vertical cell according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]     In  FIG. 2A , a substrate  100  comprising Si or Ge is provided. The substrate  100  is divided into two parts comprising a memory cell array region I and a supporting region II. A first mask layer  102  is formed on the substrate  100 . The first mask layer  102  comprises stacked silicon oxide and silicon nitride layers.  
         [0024]     Next, the first mask layer  102  is patterned. The substrate  100  undergoes photolithography and etching to form a deep trench  112  in the memory cell region I using the patterned first mask layer  102  as a shield. A capacitor  104  is formed in a lower portion of the deep trench  112 . The trench capacitor  104  comprises a buried plate (BP) serving as a lower electrode, an upper electrode  116 , a dielectric layer deposited between the upper electrode  116  and the lower electrode. The buried plate is deposited in the doped region of the substrate  100  surrounding the lower portion of the trench  112 . The material of the electric layer  116  comprises silicon oxide or a stacked silicon oxide/silicon nitride/silicon oxide layer. The material of the upper electrode  116  comprises doped polysilicon.  
         [0025]     A first insulating layer (collar)  114  is formed on the capacitor in the upper portion of the deep trench  112 , with a surface lower than that of the substrate  100 . A trench top oxide (TTO)  122  is subsequently formed on the first insulating  114  to isolate the upper electrode  116  and the following formed transistor. The trench top oxide  122  comprises tetraethlothosilicate (TEOS).  
         [0026]     In  FIG. 2B , a second mask layer  124  is formed in the deep trench  112 , recessed below the first mask layer  102 . The material of the second insulating layer  124  comprises an organic anti-reflection coating layer. A photoresist layer  126  is then formed on the active areas of the substrate  100  in the memory cell array region and in the supporting region.  
         [0027]     In  FIG. 2C , using the photoresist layer  126  and the second mask layer  124  as a mask, the substrate  100  is etched to form a shallow trench  130  to define the active areas (AA), such that the surface of the trench  130  is lower than that of the trench top oxide  122 . The photoresist layer  126  and the second mask layer  124  are subsequently removed.  
         [0028]     In  FIG. 2D , the edge of the first mask layer  102  is then removed by anisotropic etching to expose the corner  150  of the substrate  100 , employing an etching solution comprising hydrogen fluoride (HF) and ethylene glycol (EG).  
         [0029]     A first rounding process is then performed on the corner  150  of the substrate  100  as follows. The corner  150  and the exposed sidewall of the substrate  100  undergo in-situ steam generation (ISSG) to form a sacrificial oxide layer  132 , which is then removed. Thus, the rounded corner  150  of the substrate  100  in the active areas (AA) is obtained.  
         [0030]     In  FIG. 2E , a second insulating layer  134  comprising silicon nitride is conformally formed on the first mask layer  102 , the first insulating layer  114 , and the substrate  100 . An insulating plug  136  is formed on the second insulating layer  134  by high density plasma chemical vapor deposition (HDP CVD). The insulating plug  136  undergoes chemical machine polishing (CMP) until the second insulating layer  134  is exposed, such that the surface of the insulating plug  136  is substantially level with that of the second insulating layer  134  on the substrate  100 .  
         [0031]     In  FIG. 2F , a photoresist layer  142  is formed on the second insulating layer  134  and the insulating plug  136  in the supporting region II, such that memory cell array region I is exposed.  
         [0032]     In  FIG. 2C , the insulating plug  136 , the second insulating layer  134 , and the first mask layer  102  in the memory cell array I are removed to expose the corner  150  of the substrate  100  in the active areas (AA). A second rounding process is performed on the corner  150  of the substrate  100  in the memory cell array region I. H2O 2 (aq) or HNO 3( aq) is employed to form a sacrificial oxide layer on the corner  150 . The sacrificed oxide layer is then removed by HF solution.  
         [0033]     The insulating plug  136  in the memory cell array region I is removed using the photoresist layer  142  as a shield, as shown in  FIG. 2H .  
         [0034]     The second insulating layer  134  and the first mask layer  102  are subsequently removed to expose the substrate  100  in the active areas (AA). A gate oxide layer  152  comprising silicon oxide by oxidation formation is formed on the substrate  100 . A gate layer  154  is formed on the gate oxide layer  152 , and a spacer  156  is formed on the sidewall of the gate layer  152 . Thus, transistors are obtained in the memory cell array region I and the supporting region II.  
         [0035]     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.