Abstract:
A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is related to co-pending application docket numbers YOR920090399US1, YOR920090411US1, YOR920090414US1, YOR920090505US1, YOR920090506US1, all of which are incorporated by reference herein. 
       FIELD OF INVENTION 
       [0002]    The present invention relates to semiconductor nanowire field effect transistors. 
       DESCRIPTION OF RELATED ART 
       [0003]    A nanowire field effect transistor (FET) includes doped portions of nanowire that contact the channel region and serve as source and drain regions of the device. Previous fabrication methods that used ion-implantation to dope the small diameter nanowire may result in undesirable amorphization of the nanowire or an undesirable junction doping profile. 
       BRIEF SUMMARY 
       [0004]    In one aspect of the present invention, a method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region. 
         [0005]    In another aspect of the present invention, a method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire, and portions of nanowire to form a cavity defined by the nanowire surrounded by the gate structure, and the spacer walls, and epitaxially growing a doped semiconductor material in the cavity on exposed cross sections of the nanowire. 
         [0006]    In yet another aspect of the present invention, a nanowire field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate structure disposed circumferentially around the silicon portion, a source region including a first doped epi-silicon nanowire extension contacting the first distal end of the silicon portion, and a drain region including a second doped epi-silicon nanowire extension contacting the second distal end of the silicon portion. 
         [0007]    In yet another aspect of the present invention, a nanowire field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a first cavity defined by the first distal end of the silicon portion and an inner diameter of the gate structure, a second cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, a source region including a first doped epi-silicon nanowire extension contacting the first distal end of the silicon portion in the first cavity, and a drain region including a second doped epi-silicon nanowire extension contacting the second distal end of the silicon portion in the second cavity. 
         [0008]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0009]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0010]      FIGS. 1-13B  illustrate an exemplary method for forming field effect transistor (FET) devices. 
           [0011]      FIGS. 14A-15B  illustrate an alternate exemplary method for forming field effect transistor (FET) devices. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    With reference now to  FIG. 1 , a silicon on insulator (SOI) portion  102  is defined on a buried oxide (BOX) layer  104  that is disposed on a silicon substrate  100 . The SOI portion  102  includes a SOI pad region  106 , a SOI pad region  108 , and nanowire portions  109 . The SOI portion  102  may be patterned by the use of lithography followed by an etching process such as, for example, reactive ion etching (RIE). 
         [0013]      FIG. 2  illustrates the resultant BOX layer  104  and SOI portion  102  following an isotropic etching process. The BOX layer  104  is recessed in regions not covered by SOI portion  102 . The isotropic etching results in the lateral etching of portions of the BOX layer  104  that are under the SOI portion  102 . The lateral etch suspends the nanowires  109  above the BOX layer  104 . The lateral etch forms the undercuts  202  in the BOX layer  104  and overhang portions  201  at the edges of SOI regions  106  and  108 . The isotropic etching of the BOX layer  104  may be, for example, performed using a diluted hydrofluoric acid (DHF). A 100:1 DHF etches about 2 to 3 nm of BOX layer  104  per minute at room temperature. Following the isotropic etching the nanowires portions  109  are smoothed to form elliptical shaped (and in some cases, cylindrical shaped) nanowires  110  that are suspended above the BOX layer  104  by the SOI pad region  106  and the SOI pad region  108 . The smoothing of the nanowires may be performed by, for example, annealing of the nanowires  109  in hydrogen. Example annealing temperatures may be in the range of 600° C.-900° C., and a hydrogen pressure of approximately 600 torr to 7 torr. 
         [0014]      FIG. 3  illustrates the nanowires  110  following an oxidation process that reduces the diameter of the nanowires  110 . The reduction of the diameter of the nanowires  110  may be performed by, for example, an oxidation of the nanowires  110  followed by the etching of the grown oxide. The oxidation and etching process may be repeated to achieve a desired nanowire  110  diameter. Once the diameters of the nanowires  110  have been reduced, gates are formed over the channel regions of the nanowires  110  (described below). 
         [0015]      FIG. 4A  illustrates gates  402  that are formed around the nanowires  110 , as described in further detail below, and capped with a polysilicon layer (capping layer)  404 . A hardmask layer  406 , such as, for example silicon nitride (Si 3 N 4 ) is deposited over the polysilicon layer  404 . The polysilicon layer  404  and the hardmask layer  406  may be formed by depositing polysilicon material over the BOX layer  104  and the SOI portion  102 , depositing the hardmask material over the polysilicon material, and etching by RIE to form the polysilicon layer  406  and the hardmask layer  404  illustrated in  FIG. 4A . The etching of the gate  402  may be performed by directional etching that results in straight sidewalls of the gate  402 . Following the directional etching, polysilicon  404  remains under the nanowires  110  and outside the region encapsulated by the gate  402 . Isotropic etching may be performed to remove polysilicon  404  from under the nanowires  110 . 
         [0016]      FIG. 4B  illustrates a perspective view of an exemplary alternate arrangement that includes a plurality of gates  402  that are formed on a nanowire  110  between SOI pad regions  106  and  108 . The fabrication of the arrangement shown in  FIG. 4B  may be performed using similar methods as described above for the fabrication of a single row of gates  402  line, and illustrates how the methods described herein may be used to form any number of devices on a nanowire between SOI pad regions  106  and  108 . 
         [0017]      FIG. 5  illustrates a cross sectional view of a gate  402  along the line A-A (of  FIG. 4A ). The gate  402  is formed by depositing a first gate dielectric layer  502 , such as silicon dioxide (SiO 2 ) around a channel portion of the nanowire  110 . A second gate dielectric layer  504  such as, for example, hafnium oxide (HfO 2 ) is formed around the first gate dielectric layer  502 . A metal layer  506  such as, for example, tantalum nitride (TaN) is formed around the second gate dielectric layer  504 . The metal layer  506  is surrounded by polysilicon layer  404  (of  FIG. 4A ). Doping the polysilicon layer  404  with impurities such as boron (p-type), or phosphorus (n-type) makes the polysilicon layer  404  conductive. 
         [0018]      FIGS. 6A and 6B  illustrate the spacer portions  604  formed along opposing sides of the polysilicon layer  404 . The spacers are formed by depositing a blanket dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by RIE. The spacer walls  604  are formed around portions of the nanowire  110  that extend from the polysilicon layer  404  and surround portions of the nanowires  110 .  FIGS. 6A and 6B  include spacer portions  602  that are formed under the nanowires  110 , and in the undercut regions  202  (of  FIG. 2 ). 
         [0019]      FIG. 7A  illustrates a cross-sectional view (of  FIG. 6A ).  FIG. 7B  illustrates a similar cross-sectional view of the exemplary alternate arrangement of  FIG. 6B . 
         [0020]      FIGS. 8A and 8B  illustrate cross-sectional views of the resultant structures following a selective RIE process, that removes exposed portions of the nanowires  110  and the SOI pad regions  106  and  108  (shown in  FIG. 7A ). An example of a selective RIE process includes a RIE based on HBr chemistry that etches silicon while being selective to reduce the etching of dielectrics such as silicon oxide and silicon nitride. The portions of the nanowire  110  that are surrounded by the spacer walls  604  are not etched, and have exposed cross sections defined by the spacer walls  604 . 
         [0021]      FIGS. 9A and 9B  illustrate cross-sectional views of the resultant structures following a selective epi-silicon growth to form epi-nanowire extensions  902  (nanowire extensions). The nanowire extensions  902  are epitaxially grown from the exposed cross-sectional portions of the nanowire  110  that are surrounded by the spacer walls  604 . The nanowire extensions  902  are formed by epitaxially growing, for example, in-situ doped silicon (Si) or a silicon germanium (SiGe) that may be either n-type or p-type doped. The in-situ doped epi process forms the source region and the drain region of the nanowire FET. As an example, a chemical vapor deposition (CVD) reactor may be used to perform the epitaxial growth. Precursors for silicon epitaxy include SiCl 4 , SiH 4  combined with HCL. The use of chlorine allows selective deposition of silicon only on exposed silicon surfaces. A precursor for SiGe may be GeH 4 , which may obtain deposition selectivity without HCL. Precursors for dopants may include PH 3  or AsH 3  for n-type doping and B 2 H 6  for p-type doping. Deposition temperatures may range from 550° C. to 1000° C. for pure silicon deposition, and as low as 300° C. for pure Ge deposition. 
         [0022]      FIGS. 10A-11B  illustrate an exemplary method for fabricating complementary metal-oxide-semiconductors (CMOS) having both N-FETs and P-FETs fabricated on the same chip. Since N-FETs and P-FETs have nanowire extensions with different types of dopants, the N-FET device and P-FET device nanowire extensions are grown in separately. Referring to  FIG. 10A , a P-FET and N-FET device is shown. The N-FET is covered with an epi blocking mask  1001  that blocks the growth from the exposed cross-sectional portions of the nanowire  110 . The epi blocking mask  1001  may be, for example, a deposited oxide film that is patterned to cover the N-FET devices. The P-FET cross-sectional portions of the nanowire  110  are exposed allowing the formation of the p+ doped nanowire extensions  902 P using a selective epitaxially grown silicon deposition process similar to the process described above.  FIG. 10B  illustrates a similar process as described in  FIG. 10A  for a plurality of N-FET and P-FET devices. 
         [0023]    Referring to  FIGS. 11A and 11B , following the growth of the p+ doped nanowire extensions  902 P (in  FIGS. 10A and 10B ), the epi blocking masks  1001  are removed, and a second epi blocking mask  1101  is deposited and patterned to cover the P-FET and the p+ doped nanowire extensions  902 P. Selective epitaxy with n-type in-situ doping is used to form the n+ doped nanowire extensions  902 N. Once the n+ doped nanowire extensions  902 N are formed, the second epi blocking mask  1101  may be removed. The order by which the P-FET and N-FET nanowire extensions  902  are formed may be chosen to minimize diffusion of dopants in the first grown extension during the growth of the second nanowire extension. Thus, the epitaxy of the n+ doped nanowire extensions  902 N may be formed prior to forming the p+ doped nanowire extensions  902 P. Since the formation of the nanowire extensions  902  may be carried out in separate processing steps, the extensions composition may be different. For example, SiGe nanowire extensions may be formed for the P-FET devices while pure silicon nanowire extensions may be formed for the N-FET devices. 
         [0024]      FIGS. 12A and 12B  illustrate an example of the resultant structures following a thermal process (performed after the growth of the nanowire extensions  902  described above) that diffuses the doped ions from the nanowire extensions  902  into the regions  1202  of the nanowires  110  that are surrounded by the spacer walls  604  and the gates  404  to overlap the device. The epi-nanowire extensions  902  are uniformly doped when grown; resulting in a uniform doping profile in the regions  1202  of the nanowires  110  following diffusion of the ions from the epi-nanowire extension  902  into the regions  1202 . For the CMOS devices (described above in  FIGS. 10A-11B ), a similar thermal process may be performed. When the n-type and p-type dopant diffusion properties are similar, similar doped regions of the nanowires  110  for both PFET and NFET devices will result. When the n-type and p-type dopant diffusion properties are dissimilar, the penetration of the n-type and p-type dopants may result in dissimilar regions  1202  in the nanowires  110 . The thermal process may be performed in a rapid thermal annealing (RTA) chamber. The thermal process may be performed, for example, at annealing temperatures between 900° C. to 1100° C. for 0-10 seconds in an ambient N 2  gas. The annealing temperature rate may range, for example, between 50° C./second to 300° C./second. 
         [0025]      FIGS. 13A and 13B  illustrate a resultant structure following silicidation where a silicide  1302  is formed on the nanowire extensions  902 , and over the polysilicon layer  404 . Examples of silicide forming metals include Ni, Pt, Co, and alloys such as NiPt. When Ni is used the NiSi phase is formed due to its low resistivity. For example, formation temperatures include 400-600° C. Once the silicidation process is performed, capping layers and vias for connectivity (not shown) may be formed. 
         [0026]      FIGS. 14A-15B  illustrate an alternate exemplary method for forming a nanowire FET. The alternate exemplary method is similar to the method described above in  FIGS. 1-13B . However, when the nanowires  110  are etched to remove the exposed portions of the nanowires  110 , the etching process removes a portion of the nanowires  110  that are surrounded by the spacer walls  604  and the gates  402  to recess the nanowires  110  into the gates  402 , and form cavities  1402  defined by the gates  402 , the nanowires  110  and the spacer walls  604 .  FIGS. 14A and 14B  illustrate a cross-sectional view of the resultant structure. 
         [0027]    The lateral etching process that forms cavities  1402  may be time based. Width variation in spacer  604  may lead to variations in the position of the edges of the recessed nanowires  110 . The etching rate in the cavity  1402  depends on the size of the cavity, with narrower orifice corresponding to slower etch rates. Variations in the nanowire size will therefore lead to variations in the depth of cavity  1402 . 
         [0028]    The variations described above may be reduced by bombarding the exposed ends of nanowire  110  with ions (e.g. silicon ions, germanium ions, and even dopants such as boron which do not amorphize) prior to the formation of the spacer  604  (in  FIGS. 6A and 6B ). The etching rate of the bombarded portions of nanowires  110  is several times faster than that of the un-exposed portion of nanowire  110  protected by gate material  402 . As a result, the cavity  1402  becomes self-aligned with the sidewalls of gate  402  when etched. 
         [0029]    If the deposition of spacer  604  is performed at an elevated temperature, the deposition process may anneal the exposed nanowire  110  portions (that have been bombarded with ions) and increase the etching resistance of the exposed nanowire  110  portion. For silicon nanowires  110 , the spacer  604  may be formed at a low temperature, for example, less than 500° C. to avoid annealing the bombarded portions of the nanowires  110 . If other materials are used to form the nanowires  110  are used, the formation temperature of the spacer  604  may be higher. An alternative that accommodates high temperature deposition of spacer  604  includes performing an ion implantation at an oblique angle to the substrate  100  after the deposition of the spacer  604  with an ion energy that damages the portions of the nanowires  110  that are encapsulated by spacer  604 . 
         [0030]    Referring to  FIGS. 15A and 15B , a cross-sectional view of the resultant structure having nanowire extensions  1502  that are formed from an in-situ doped epi-silicon growth process similar to the process described above in  FIGS. 9A and 9B . The epi silicon growth began in the cavity  1402  (of  FIGS. 14A and 14B ) from the exposed nanowire  110  in the gate  402  to form the nanowire extensions  1502 . Once nanowire extensions  1502  are formed, the doping may be activated by, for example, a laser or flash anneal process. The laser or flash annealing may reduce diffusion of ions into the channel region  1501  of the gate  402 , and result in a high uniform concentration of doping in the nanowire extensions  1502  with an abrupt junction in the nanowires  110 . Once the ions have been activated, silicidation similar to the process described in  FIGS. 13A and 13B  above may be performed and capping layers and vias for connectivity (not shown) may be formed. 
         [0031]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0032]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
         [0033]    The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0034]    While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.