Abstract:
An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area ‘footprint’ of the MOSFET pair. The source and drain of a high side FET high  and a low side FET low  or the drains of the respective high side FET high  and low side FET low  are bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application 61/104,784 filed by the inventors herein on Oct. 13, 2008, the disclosure of which is incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to the structural organization of MOSFET pairs and, more particularly, to MOSFET pairs having reduced PCB mounting area requirements, increased thermal efficiency, and reduced parasitic impedances. 
         [0003]    Multi-die packaging is common in power converters in which MOSFET switching transistors are used; for example and as shown in  FIGS. 1 and 1A , a circuit assembly or package  10  includes a first FET  12  and a second FET  14  in a side-by-side or lateral mounting arrangement on a common plane with a controller or driver chip  16  that is connected via bonding wires  18  between conductive pads (unnumbered) on the driver chip  16  and to contacts  20  of the respective leadframe portions and by bonding wires  18  connected to various contact pads (unnumbered) on the FET structures. A first strap or clip  22 , typically formed from shape-sustaining copper or a copper alloy in ribbon or ribbon-like form, is in electrical and thermal contact with the upper surface of the FET  14  and a second clip  24  is in electrical and thermal contact with the upper surface of the FET  12 . As shown in  FIG. 1A , the first clip  24  is generally “L-shaped” and includes a columnar portion (unnumbered) that is in contact with a contact pad  26  of the leadframe; the clip  24  is similarly shaped and is in contact with another portion (unnumbered) of the leadframe. In typical power converter operations, the clips  22  and  24  serve as substantial current carrying conductors as well as heat sinks. While not specifically shown, the various parts are electrically connecting using solder-bonding techniques. As shown in  FIG. 1A  at  28 , the structure of  FIG. 1  is typically encapsulated in a thermosetting molding compound to define a circuit package. 
         [0004]    The MOSFET package shown in  FIGS. 1 and 1A  finds use in power switching applications including use in synchronous buck converter circuits of the type shown in  FIGS. 1B and 1C . In  FIG. 1B , two n-channel MOSFETs, FET high  and FET low , are in series circuit between V in  and ground GND with a switching or phase node PN defined between the source S of FET high  and the drain D of FET low . The drain D of FET high  is connected to V in  while the source S of FET low  is connected to ground. The two FETs are alternatively turned on and off by respective on/off pulses of appropriate pulse width and timing from a driver circuit  16  to their gates G to step-down V in  into an inductor I. The circuit of  FIG. 1C  is similar to that of  FIG. 1B  except that the high-side FET is a p-channel MOSFET with its drain D connected to the drain D of FET low  to define the phase node PN; in  FIG. 1C , the FET high  and FET low  are alternatively turned on and off by respective pulses of appropriate pulse width and timing to their gates G from a driver circuit  16  to switch V in  into an inductor I. The inductor I can take the form of a planar spiral inductor formed on a substrate or a discrete inductor package. While not specifically shown, the side of the inductor I opposite to that connected to the phase node PN can be connected to one or more capacitors (and/or inductors) to smooth or otherwise condition the output. 
         [0005]    The physical organization of  FIG. 1  functions for its intended purpose; however, the side-by-side organization of  FIG. 1  militates against more compact circuit packages occupying smaller circuit board areas. 
       SUMMARY 
       [0006]    A MOSFET pair suited for use in a synchronous buck converter places the FET dies in a stacked relationship to reduce the surface area ‘footprint’; depending upon the electrical circuit used, the source and drain of the two FETs or the drains of the two FETs are connected together, either directly or through an intermediate conductive ribbon, strap, or clip, to establish a common phase or switch node. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to prior side-by-side organizations while allowing for improved heat sinking. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0007]      FIG. 1  is a plan view of a representative or example multi-die assembly in which two MOSFET structures are mounted adjacent one another in a common plane; 
           [0008]      FIG. 1A  is a cross-sectional view of the structure of  FIG. 1  taken along line  1 A- 1 A of  FIG. 1 ; 
           [0009]      FIG. 1B  is a simple circuit diagram of two n-channel enhancement-mode MOSFETs in a synchronous buck-convertor configuration; 
           [0010]      FIG. 1C  is a simple circuit diagram of an n-channel and a p-channel enhancement-mode MOSFET in a synchronous buck-convertor configuration; 
           [0011]      FIGS. 2A and 2B  are an example of a first stacked FET organization; 
           [0012]      FIG. 2C  is an simple circuit diagram representing the physical organization of  FIGS. 2A and 2B ; 
           [0013]      FIGS. 3A and 3B  represent a variation of the stacked FET organization of  FIGS. 2A and 2B ; 
           [0014]      FIG. 4  is another example a stacked FET organization; 
           [0015]      FIG. 5A  is further example a stacked FET organization; 
           [0016]      FIG. 5B  is a variation of the stacked FET organization of  FIG. 5A ; 
           [0017]      FIG. 5C  is representative physical representation of the organization of  FIG. 5B ; and 
           [0018]      FIG. 6  is further example a stacked FET organization. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]      FIG. 2A  is an idealized symbolic representation of a first MOSFET organization in which NMOS FETs are used for both the high side FET and the low side FET, and  FIG. 2B  is a representative pictorial representation of one possible embodiment of the representation of  FIG. 2A  with the corresponding electrical circuit shown in  FIG. 2C . In both  FIGS. 2A and 2B , the two FETs are shown in symbolic or idealized fashion as right parallelepipeds each having major surface-area upper and lower surfaces with the smaller-volume parallelepiped mounted on top of or stacked upon the larger-volume parallelepiped; in practice, actual FET structures are somewhat differently shaped and have different sizing and thicknesses from that illustrated depending upon the manufacturing process and design constraints. The FETs shown are vertical FETs and can be characterized as having an upper or top region or surface (which can constitutes a source or drain contact), a lower or bottom region or surface (which can constitute a drain or a source contact), and an intermediate region therebetween through which a controllable current can flow as a function of gate control signals applied to a gate electrode. 
         [0020]    In  FIG. 2A , a high side FET high  includes source S, drain D, and gate G contacts and is mounted in a bottom drain/top source orientation on an underlying die pad (not shown in  FIG. 2A ) connected to a V in  trace on the underlying printed circuit board; the die pad is typically part of a larger leadframe. The low side FET low  is also in a bottom drain/top source orientation with the drain D of the low side FET low  mounted upon and electrically connected or bonded (i.e., solder bonded) to the source S surface of high side FET high  to define the phase node PN therebetween. The phase node PN is then connected to an inductor I using a shape-sustaining clip (generally indicated as PNC), conductive ribbon, or strap. As is also known, the connection to the phase node can be implemented by a plurality of bonding wires (not shown). The source S of low side FET low  is wire bonded or otherwise connected to a ground trace on the PCB. The gates G of the high side FET high  and the low side FET low  are wire bonded to their respective driver (not shown in  FIG. 2A  of which the driver  16  of  FIG. 1  is suitable) to allow the high side FET high  and the low side FET low  to be alternately turned on and off by appropriately timed and spaced pulses to the gates G of both the high side FET high  and the low side FET low . In  FIG. 2A , the high side FET high  is larger than the low side FET low  as is the case where the ratio of V out /V in  is &gt;0.5. 
         [0021]      FIG. 2B  is representative of one possible physical or package organization of the arrangement of  FIG. 2A  using conductive clips; as shown, the bottom-drain high side FET high  is mounted upon and electrically connected or bonded to a die pad  100  of an underlying substrate SS (shown generically in dotted-line), which can take the form of leadframe (not fully shown), a substrate pad (not shown), or an underlying printed circuit board (not shown) to connect the drain D to a V in  trace or other V in  source. The drain D of the low side FET low  is mounted upon and electrically connected or bonded to the source S surface of high side FET high  to define the phase node PN therebetween. An L-shaped conductive clip PNC is in electrical contact with or electrically bonded to the phase node PN via an electrical connection to the source S surface of high side FET high  and has an columnar portion in contact with another contact pad  102  of the underlying leadframe (or other suitable substrate). In this organization, the contact pad  102  is then connected to an inductor I, which can take the form of a planar inductor or a discrete inductor mounted on the printed circuit board (not specifically shown). Another L-shaped conductive clip GC is in contact with the source S of low side FET low  and has a columnar portion in contact with another contact pad  104  of the underlying leadframe (or printed circuit board) which, in turn, is connected to circuit ground GND. The gates G of the high side FET high  and the low side FET low  are wire bonded to their respective driver (not shown in  FIG. 2B  of which the driver  16  of  FIG. 1  is an example) to allow the high side FET high  and the low side FET low  to be alternately turned on and off by pulses of appropriate pulse width and timing applied to their respective gates G. While not specifically shown, those surfaces of the FETs that are electrically connected to other components can be solder-bonded using solder paste/reflow techniques. 
         [0022]      FIG. 2C  illustrates the equivalent electrical circuit for the physical organization of  FIGS. 2A and 2B  showing the drain D of the side FET low  and the source S of the high side FET high  connected to the inductor I via the phase node PN with the source S of the low side FET low  connected to ground GND and the drain D of the high side FET high  connected to V in . The driver circuit  16  provides a succession of alternating on/off pulses of appropriate pulse width and timing to the gates G of FET high  and FET low  to turn the FETs on and off. The inductor I can take the form of a substantially planar spiral conductive path formed an a substrate or a discrete inductor device. While not specifically shown, the side of the inductor I opposite to that connected to the phase node PN can be connected to one or more capacitors and/or inductors to smooth or otherwise condition the output. 
         [0023]      FIGS. 3A and 3B  represent a variation of the arrangement and organization of  FIGS. 2A and 2B  and shows the conductive clip PNC fully interposed between and electrically connected or bonded to the drain D of the low side FET low  and the source S of the high side FET high . The  FIG. 3A  arrangement maximizes the electrical contact area and the heat transfer area at the phase node PN between the drain D of the low side FET low  and the source S of the high side FET high  to maximize heat sinking, as indicated symbolically at Q. While a fully interposed conductive clip PNC is preferred, other arrangements in which the conductive clip PNC does not fully extend between the surface of the FETs is also acceptable. 
         [0024]      FIG. 4  illustrates an embodiment better suited for use where the ratio of V out /V in  is &lt;0.5 where the low side FET low  is normally volumetrically larger than the high side FET high ; the physical organization of  FIG. 4  is electrically the same as that of  FIGS. 2A-2C . In  FIG. 4 , the high side FET high  is arranged in a bottom drain/top source organization and formed as a strip-like parallelepiped having a source S and drain D with a gate G shown to the left. The larger volume, bottom drain/top source low side FET low  is positioned above the high side FET high  with a conductive clip PNC (fabricated from a shape-sustaining copper or copper-alloy material) interposed between and electrically connected to or electrically bonded to the source S of the high side FET high  and the drain D of low side FET low  with the conductive clip PNC extending across the surface of the low side FET low  that defines the drain D to connect to the inductor I. The conductive clip PNC can be also be shaped as an L-shaped component in a manner consistent with  FIG. 3B . 
         [0025]      FIG. 5A  represents a physical organization similar to that of  FIGS. 2A and 3A  but in which a bottom drain/top source p-channel MOSFET functions as the high side FET high  and a bottom source/top drain n-channel MOSFET functions as the low side FET low  in a manner electrically consistent with  FIG. 1C . 
         [0026]    As shown in  FIG. 5A , the source S of the low side FET low  connects to ground with its gate G isolated therefrom. The drain D of the low side FET low  electrically connects to the drain D of the high side FET high  to define the phase node PN therebetween. The source S of the high side FET high  is connected to V in  with a phase node connector PNC electrically connected or bonded to the drain D of the low side FET low  to connect the phase node PN to the inductor I. As in the case of the  FIG. 2A  embodiment, the gates G of the high side FET high  and the low side FET low  are wire bonded to their respective drivers (not shown) to allow the high side FET high  and the low side FET low  to be alternately turned on and off by pulses of appropriate duration and timing applied to their respective gates. In the embodiment of  FIG. 5B , the phase node connector PNC is interposed between and electrically connected or bonded to the drain D of the low side FET low  and the drain D of the high side FET high . 
         [0027]    The arrangements of  FIGS. 5A and 5B  can be configured, as one possible physical organization, in a manner consistent with that of  FIGS. 2B and 3B . For example and as shown in  FIG. 5C , the low side FET low  is mounted upon a contact pad  100  of an underlying leadframe (not fully shown), a substrate (not shown), or an underlying printed circuit board (not shown) with its source S connected a ground trace. An L-shaped conductive clip PNC is positioned intermediate the drain D of the low side FET low  and the drain D of the high side FET high  to define the phase node PN. The conductive clip PNC has a columnar portion in contact with another contact pad  102  of the underlying leadframe (or printed circuit board). In this organization, the contact pad  102  is then connected to an inductor I, which can take the form of a planar inductor or a discrete inductor mounted on the printed circuit board (not specifically shown). Another L-shaped conductive clip V in  C is in contact with the source S of high side FET high  and has an columnar portion in contact with another contact pad  104  of the underlying leadframe (or printed circuit board) which is in contact with a V in  source. The gates G of the high side FET high  is wire bonded to its respective driver contact (not shown in  FIG. 5C  of which the driver  16  of  FIG. 1  is an example). In  FIG. 5C , the gate of the low side FET low  is not shown and is located on the underside of the FET low  facing the contact pad  100 ; in this case, an appropriately sized opening (not shown) is formed in the contact pad  100  to allow access the gate G of the low side FET low . In  FIG. 5C , the conductive clip PNC is fully interposed between the FET high  and the FET low ; if desired a conductive clip of the type shown in  FIG. 2B  can also be used. 
         [0028]      FIG. 6  illustrates an embodiment well suited for use where the ratio of V out /V in  is &gt;0.5 where the low side FET low  is normally volumetrically smaller than the high side FET high ; the physical organization of  FIG. 6  is electrically the same at that of  FIG. 1C , described above. In  FIG. 6 , the low side FET low  is formed as a strip-like parallelepiped having a source S and drain D with a gate G shown to the left. The larger volume high side FET high  is positioned above the low side FET low  with a conductive clip PNC (fabricated from a shape-sustaining copper or copper-alloy material) interposed between the drain D of the high side FET high  and the drain D of low side FET low  with the conductive clip PNC extending across the surface of the high side FET high  that defines the drain D to connect to the inductor I. 
         [0029]    The stacked organization described herein allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking. 
         [0030]    As will be apparent to those skilled in the art, various changes and modifications may be made to the illustrated embodiment of the present invention without departing from the spirit and scope of the invention as determined in the appended claims and their legal equivalent.