Abstract:
The present invention is directed to an apparatus and method for reducing a parasitic capacitance in an integrated circuit. The apparatus includes a substrate and a biasing device. The substrate has a circuit disposed thereon, wherein a first capacitance exists between the substrate and an element of the circuit. The biasing device DC biases a first portion of the substrate to a voltage different than a voltage of a second portion of the substrate, thereby inducing a second capacitance between the first portion of the substrate and the second portion of the substrate. The second capacitance is in series with the first capacitance.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of U.S. patent application Ser. No. 11/084,784 to Chen, entitled “Design and Layout Techniques for Low Parasitic Capacitance in Analog Circuit Applications” and filed Mar. 21, 2005, which claims benefit to U.S. Provisional Patent Application No. 60/620,966 to Chen, entitled “Design and Layout Techniques for Low Parasitic Capacitance in Analog Circuit Application” and filed Oct. 22, 2004, the entirety of each is incorporated by reference as if fully set forth herein. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention is related to semiconductor devices and integrated circuits. More specifically, the present invention relates to Very Large Scale Integration (VLSI) systems. 
   2. Background Art 
   In VLSI applications the parasitic capacitance of the signal lines to the substrate reduces the signal bandwidth and signal speed due to the filtering effect. The parasitic capacitance arises from an electrical coupling between the signal line and the substrate. The equation for the parasitic capacitance is given by:
 
 C=eA/d,   Eq. 1
 
where e is the dielectric constant of an insulator disposed between the signal lines and the substrate, d is the spacing between the signal lines and the substrate, and A is the area of the signal lines. The signal width times the signal length is the area of the signal lines. If, for example, the insulator is a field oxide, the dielectric constant, e, is about 3.9 and the thickness of the field oxide insulator, d, is about 0.3 μm.
 
   The above equation suggests that the parasitic capacitance can be reduced by adjusting the parameters that appear on the right side of the equal symbol (e.g., e, A and d). For example, reducing the area, A, reduces the parasitic capacitance, but at the cost of proportionally increasing the parasitic resistance, which in turn decreases the signal speed. For a given VLSI process, adjusting the thickness, d, and the dielectric constant, e, is not a viable option. This is because for a fixed VLSI fabrication process, such as a standard complementary metal oxide semiconductor (CMOS) process, the thickness and dielectric constant of the insulator disposed between the signal lines and substrate remain constant. Accordingly, it is difficult to reduce the parasitic capacitance without changing the process material or flow. 
   Therefore, what is needed is a device and method that reduces the parasitic capacitance without changing the process material or flow. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention meets the above-identified needs by providing a device and method for reducing the parasitic capacitance without changing the process material or flow. 
   An embodiment of the present invention provides an apparatus for reducing a parasitic capacitance in an integrated circuit. The apparatus includes a substrate and a biasing device. The substrate has a circuit disposed thereon, wherein a first capacitance exists between the substrate and an element of the circuit. The biasing device DC biases a first portion of the substrate to a voltage different than a voltage of a second portion of the substrate, thereby inducing a second capacitance between the first portion of the substrate and the second portion of the substrate. The second capacitance is in series with the first capacitance. 
   Another embodiment of the present invention provides a method for reducing a parasitic capacitance in an integrated circuit. First, a substrate is provided that has a circuit disposed thereon. A first capacitance exists between the substrate and an element of the circuit. Then, the first portion of the substrate is DC biased to a voltage different than a voltage of the second portion of the substrate, thereby inducing a second capacitance between the first portion of the substrate and the second portion of the substrate. The second capacitance is in series with the first capacitance. 
   Further embodiments, features, and advantages of the present invention, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES 
     The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention. 
       FIG. 1  is a cross sectional view of a conductive trace mounted on a substrate. 
       FIG. 2  is an embodiment of the invention in which an element is disposed between the conductive trace and the substrate. 
       FIG. 3  is an example in which the element between the conductive trace and the substrate comprises an NWELL. 
       FIG. 4  is an example in which the element between the conductive trace and the substrate comprises a PWELL and a deep NWELL. 
       FIGS. 5A-5E  illustrate an exemplary process for making the structure depicted in  FIG. 3 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Overview and Terminology 
   As will be described in more detail below, embodiments of the present invention reduce the parasitic capacitance between a conductive trace and a substrate in an integrated circuit device (e.g, a CMOS device), without changing the process material or flow. Terminology used to describe embodiments of the present invention is discussed below. 
   The term “NWELL” means a region of a substrate (e.g., a silicon wafer) that has a relatively high concentration of n-type dopants, so that negatively charged electrons are available for electrical conduction. Example n-type dopants can include, but are not limited to, antimony trioxide, arsenic trioxide, arsine, phosphorus oxychloride, phosphorus pentoxide, phosphine or other n-type dopants as would be apparent to one skilled in the relevant art(s). 
   The term “PWELL” means a region of a substrate (e.g., a silicon wafer) that has a relatively high concentration of p-type dopants, so that positive “holes” (or the absence of electrons) are available for electrical conduction. Example p-type dopants can include, but are not limited to, boron tribromide, boron trioxide, diborane, boron trichloride, boron nitride or other p-type dopants as would be apparent to one skilled in the relevant art(s). 
   As a person skilled in the relevant art(s) will appreciated, the combination of an NWELL and a PWELL are typically used in CMOS structures to form both n-channel and p-channel transistors. CMOS circuits are typically smaller and consume less power than comparable circuits. 
   The terms “signal line” and “conductive trace” are used interchangeably to mean an electrically conductive material that is separated from a substrate by an insulator layer, sometimes called a field oxide. Typically, a field oxide is a dielectric, like silicon dioxide (SiO 2 ), but other materials can be used as a field oxide, as is know by persons skilled in the relevant art(s). As mentioned above, examples of signal lines can include, but are not limited to, metal lines and/or polycrystaline silicon (poly) resistors. 
   Example Structures 
   In VLSI applications, a parasitic capacitance arises from an electrical coupling between a conductive trace and a substrate that are separated by an insulator layer or field oxide.  FIG. 1  is a cross sectional view of a conventional arrangement of a conductive trace  102  mounted on a substrate  106  (e.g, a silicon wafer). An insulator layer  104  is disposed between the conductive trace  102  and the substrate  106 . Insulator layer  104  produces a separation  108  between the conductive trace  102  and the substrate  106 . Insulator layer  104  can be composed of silicon dioxide or silicon nitride, or some other dielectric material as would be apparent to one skilled in the semiconductor art. 
   The arrangement in  FIG. 1  results in a parasitic capacitance (Cd) between the conductive trace  102  and the substrate  106 . This parasitic capacitance reduces the signal bandwidth and signal speed due to the filtering effect, as described above in connection with Eq. 1. 
   According to an embodiment of the present invention, the parasitic capacitance between the conductive traces and the substrate is reduced by disposing an element between the conductive trace and the substrate.  FIG. 2  is an embodiment of the invention in which an element  212  is disposed between the conductive trace  202  and the substrate  206 . The element  212  produces an additional capacitance, in series with the parasitic capacitance, between the conductive trace  202  and the substrate  206 . The series combination of the parasitic capacitance and the additional capacitance results in a reduced effective capacitance between the conductive trace  202  and the substrate  206 , which is given by the following equation: 
                     C   eff     =         C   x     ⁢     C   d           C   x     +     C   d           ,           Eq   .           ⁢   2               
where C eff  is the effective capacitance, C x  is the additional capacitance, and C d  is the capacitance across the insulator layer. From Eq. 2 it is seen that C eff  is always less than C d , which means the effective parasitic capacitance between the conductive trace  202  and the substrate  206  is less than the original parasitic capacitance.
 
   It will be apparent to a person skilled in the relevant art that the element inserted between the conductive trace and substrate can be any device that contributes an impedance, including capacitance and resistance, between the conductive trace and the substrate to result in an additional capacitance that is in series with the original capacitance between the conductive trace and the substrate.  FIGS. 3 and 4  illustrate two example elements or combinations of elements that can be disposed between the signal lines and the substrate to reduce the parasitic capacitance. 
     FIG. 3  is an example in which the element that provides a capacitance in series with the parasitic capacitance is an NWELL  312 . In this example, the substrate comprises a PWELL  306 , i.e., a region of silicon wafer substrate containing p-type dopants. 
   In order to form a capacitance (C x ) between the NWELL  312  and the PWELL  306 , the NWELL  312  must be electrically AC floating. In an embodiment, the NWELL  312  can be made electrically AC floating by coupling it to a diode  314 , which is coupled to a high voltage source (not shown), so that the NWELL  312  is biased at a higher voltage than the PWELL (substrate)  306 . In other words, NWELL  312  is in direct electrical contact with the p-type portion  316  of the PN junction of diode  314 . The high voltage source coupled to diode  314  can be, for example, a supply voltage of the IC device of which the structure depicted in  FIG. 3  is a part. Other techniques to bias NWELL  312  will become apparent to a person having ordinary skill in the pertinent art. 
   In standard CMOS technologies, the capacitance (C x ) between the PWELL  306  and the NWELL  312  is about the same as the original parasitic capacitance (C d ) between the conductive trace  302  and the PWELL  306 . Therefore, according to Eq. 2, the effective parasitic capacitance (C eff ) is about half of the original parasitic capacitance (C d ) between the conductive trace  302  and the PWELL  306 . This means that the parasitic capacitance between the conductive trace  302  and the PWELL  306  is reduced by 50%. 
   For the example of  FIG. 3 , if the conductive trace  302  is disposed on a polycrystaline layer and has a width of approximately 8 μm and a length of approximately 26 μm, then C d  (the capacitance between conductive trace  302  and NWELL  312 ) is approximately 50 fF (50×10 −15  Farads) and C x  (the capacitance between NWELL  312  and PWELL  306 ) is approximately 47 fF. Therefore, according to Eq. 2, C eff  (the effective capacitance between conductive trace  302  and PWELL  306 ) is approximately 24 fF, which represents a reduction in the typical capacitance between conductive trace  302  and PWELL  306  of approximately 51% or 26 fF. (Note: in the example quoted above, three series of diodes were used to avoid forward biasing if the signal swing is too large.) 
   To further reduce the parasitic capacitance between the conductive traces and the substrate, a second element can be disposed between the conductive traces and the substrate, thereby forming an additional capacitance in series with the parasitic capacitance. For instance,  FIG. 4  is an example in which the element between the conductive trace  402  and the substrate  406  comprises a PWELL  412  and a deep NWELL  416 . Again, the PWELL  412  and the deep NWELL  416  are kept electrically AC floating and DC reversed biased by coupling the deep NWELL  416  to a voltage source (not shown) through a reverse-biased diode  414 , in like manner to that described above with reference to  FIG. 3 . This arrangement results in a floating capacitance, C x , between the PWELL  412  and the deep NWELL  416 , and a floating capacitance, C y , between the deep NWELL  416  and the substrate  406 . Therefore, the effective parasitic capacitance between the conductive trace  402  and the substrate  406  is reduced according to the following equation: 
                   C   eff     =           C   x     ⁢     C   y     ⁢     C   d             C   x     ⁢     C   y       +       C   y     ⁢     C   d       +       C   d     ⁢     C   x           .             Eq   .           ⁢   3               
Example Method
 
   As a person skilled in the relevant art(s) will appreciate, the structures in  FIGS. 3 and 4  can be fabricated according to several different processing steps. An example fabrication process for the structure illustrated in  FIG. 3  is described below with reference to  FIGS. 5A-5E . It is to be appreciated that the fabrication process is presented by way of example only, and not limitation. Other fabrication processes can be employed to fabricate either of the structures illustrated in  FIGS. 3  or  4  without deviating from the scope and spirit of the present invention. 
   Step 1: Layering Operation. The example fabrication process begins with a portion of a substrate that is doped with p-type dopants to form a PWELL  501 , as shown in  FIG. 5A . The doping can be achieved through thermal diffusion, ion implantation, or some other doping technique as would become apparent to those skilled in the relevant art(s). PWELL  501  is then layer with a field oxide layer  503  (e.g., silicon dioxide), as shown in  FIG. 5B . Example layering techniques can include physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, sputtering, or some other technique as would be apparent to one skilled in the relevant art(s). 
   Step 2: Patterning Operation. The patterning operation leaves an opening  505  in field oxide layer  503  exposing substrate  501 , as shown in  FIG. 5C . Substrate  501  is then doped with an n-type dopant to produce an NWELL  507 . Lithography and deposition are well known techniques for these steps, as would be apparent to a person skilled in the relevant art. 
   Step 3: Layering Operation. Field oxide layer  503  is then removed by known techniques and a new field oxide layer  509  is disposed on substrate  501 , as indicated in  FIG. 5D . 
   Step 4: Etching Operation. A hole is etched in field oxide layer  509  using known techniques to expose NWELL  507 . 
   Step 5: Layering/Patterning Operation. A diode  511  is patterned and formed using well-known techniques having its PN junction reversed biased, as shown in  FIG. 5E . 
   Step 6: Layering/Patterning Operation. A conductive trace  513  is created using known layering/patterning techniques, as would be apparent to one skilled in the relevant art(s), as shown in  FIG. 5E . 
   In addition to the steps outlined above, various heat treatments may be employed to cure, alloy, and/or repair (i.e., anneal) the structure, as would be apparent to one skilled in the relevant art(s). As is well-known in the relevant art(s), heat treatments are operations in which a substrate (e.g., wafer) is heated and cooled to achieve specific results. For example, ion implantation disrupts the crystal structure of a wafer; a heat treatment can be used to repair (or anneal) the crystal structure of the wafer after ion implantation. 
   Conclusion 
   An arrangement for reducing the parasitic capacitance between a conductive trace and a substrate has been disclosed. While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the hereinabove described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.