Abstract:
A semiconductor device has: a semiconductor substrate; a number of semiconductor elements formed on the semiconductor substrate; a plurality of lower level wiring layers electrically connected to the semiconductor elements; a plurality of first insulating layers electrically separating the lower level wiring layers and having a first dielectric constant; a plurality of middle level wiring layers electrically connected to the lower level wiring layers; a plurality of second insulating layers electrically separating the middle level wiring layers and having a second dielectric constant larger than the first dielectric constant; a plurality of upper level wiring layers electrically connected to the middle level wiring layers; a plurality of third insulating layers electrically separating the upper level wiring layers and having a third dielectric constant larger than the second dielectric constant. A multilevel wiring structure is provided which has a high performance and a high reliability.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
         [0001]    This application is based on Japanese Patent Application No. 2002-145284, filed on May 20, 2002, the entire contents of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    A) Field of the Invention The present invention relates to a semiconductor device and more particularly to a semiconductor device having multilevel wiring layers.  
           [0003]    B) Description of the Related Art  
           [0004]    As semiconductor integrated circuit devices are highly integrated, the wiring scale of each device increases one generation after another. According to the road map, the total wiring length of a typical semiconductor chip in the 0.18 μm generation of 1999 was about 500 m and the number of wiring layers was three or four. The total wiring length of a typical semiconductor chip in the 0.10 μm next generation will be about 4 km and the number of wiring layers will be about ten. The total wiring length of a typical semiconductor chip of the 0.05 μm generation in about ten years may be over 200 km.  
           [0005]    Both high integration and high speed of semiconductor integrated circuits are desired. For the high speed operation, it is desired to lower the wiring resistance and the parasitic capacitance. In order to lower the wiring resistance, aluminum (Al) wiring has been replaced with copper (Cu) wiring. It is difficult to use wiring material having a resistivity lower than Cu. When reduction of the wiring resistance reaches near its limit, it becomes necessary to lower the parasitic capacitance of wiring in order to realize high speed operation.  
           [0006]    The parasitic capacitance of wiring is dependent on the dielectric constant of insulating layers dielectrically separating the wiring. Fluorine-doped silicon (FSG having a dielectric constant ε of about 3.7) is used in place of undoped silicon oxide (USG), phosphorous doped silicon oxide (PSG), boron and phosphorous doped silicon oxide (BPSG) respectively having a dielectric constant ε of about 4.1. Organic insulating material having a much lower dielectric constant (registered trademarks SiLK, FLARE and the like) is also used. Porous material (such as porous silicon oxide) realizing a further lowered dielectric constant has been proposed.  
           [0007]    [0007]FIGS. 8A, 8B and  8 C show examples of a wiring structure according to prior art.  
           [0008]    [0008]FIG. 8A shows an example of a wiring layer in the 0.18 μm generation. Between a first wiring layer M 1  and a third wiring layer M 3 , a second wiring layer M 2  buried in a silicon oxide layer  100  is disposed. For example, the line width of the second wiring layer M 2  is 260 nm and the height thereof is 545 nm. The distance between the first and second wiring layers M 1  and M 2  is, for example, about 750 nm. The sheet resistance of the wiring layer M 2  is 91 mΩ/□, and the parasitic capacitance is 253 fF/mm (0.137 fF/grid). The dielectric constant ε of the silicon oxide layer  100  is about 4.1.  
           [0009]    [0009]FIG. 8B shows an example of a wiring layer in the 0.13 μm generation. Between a first wiring layer M 1  and a third wiring layer M 3 , a second wiring layer M 2  is disposed. Insulating films burying the second wiring layer M 2  include an insulating layer  101   a  of silicon oxide under the second wiring layer, an organic insulating layer  101   b  having a dielectric constant of about 2.7 and laterally separating the main regions of the second wiring layer, and an insulating layer  101   c  of silicon oxide disposed on the organic insulating layer. For example, the line width of the second wiring layer M 2  is about 200 nm and the height thereof is about 275 nm. The distance between the first and second wiring layers M 1  and M 2  is, for example, about 350 nm. The sheet resistance of the wiring layer M 2  is about 90 mΩ/□, and the parasitic capacitance is about 214 fF/mm (0.086 fF/grid).  
           [0010]    [0010]FIG. 8C shows an example of a wiring layer in the 0.1 μm generation. Between a first wiring layer M 1  and a third wiring layer M 3 , a second wiring layer M 2  is disposed. The second wiring layer M 2  is buried in an organic insulating layer  102  having a low dielectric constant of about 2.7. For example, the line width of the second wiring layer M 2  is about 140 nm and the height thereof is about 250 nm. The distance between the first and second wiring layers M 1  and M 2  is, for example, about 300 nm. The sheet resistance of the wiring layer M 2  is about 95 mΩ/□, and the parasitic capacitance is about 185 fF/mm (0.052 fF/grid).  
           [0011]    The parasitic capacitance of wiring can be lowered by using insulating material having a low dielectric constant. However, the line width of a wiring layer in a semiconductor integrated circuit device becomes wider and the height thereof becomes higher in the upper level wiring layer.  
           [0012]    The main role of lower level wiring lines is transistor signal lines and the like, and the pitch of wiring lines is small. The smaller the parasitic capacitance of wiring lines is, the better it is for high speed operation. To this end, low dielectric constant insulating material such as an organic film is used.  
           [0013]    The main role of upper level wiring lines is power supply lines. High speed operation is not required but heat radiation and workability have a priority over the high speed operation. These requirements can be met and high reliability can be realized by using insulating films made of mainly silicon oxide which has been widely used conventionally. By using different insulating materials for upper and lower wiring lines, a high performance of semiconductor integrated circuit devices can be expected.  
           [0014]    A variety of makers have proposed low dielectric constant films such as organic films and inorganic films. These low dielectric constant materials have physical constants very different from those of insulating material made of mainly silicon oxide.  
           [0015]    If insulating layers having very different physical constants are laminated, cracks or peeling is likely to be formed between the layers.  
         SUMMARY OF THE INVENTION  
         [0016]    An object of this invention is to provide a semiconductor device having multilevel wiring layers with a high performance and a high reliability.  
           [0017]    Another object of the invention is to provide a semiconductor device capable of relaxing stress in a multilevel wiring layer structure. According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a number of semiconductor elements formed on the semiconductor substrate; a plurality of lower level wiring layers electrically connected to the semiconductor elements; a plurality of first insulating layers electrically separating the lower level wiring layers and having a first dielectric constant; a plurality of middle level wiring layers electrically connected to the lower level wiring layers; a plurality of second insulating layers electrically separating the middle level wiring layers and having a second dielectric constant larger than the first dielectric constant; a plurality of upper level wiring layers electrically connected to the middle level wiring layers; a plurality of third insulating layers electrically separating the upper level wiring layers and having a third dielectric constant larger than the second dielectric constant.  
           [0018]    According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a number of semiconductor elements formed on the semiconductor substrate; a plurality of lower level wiring layers electrically connected to the semiconductor elements; a plurality of middle level wiring layers electrically connected to the lower level wiring layers; a plurality of upper level wiring layers electrically connected to the middle level wiring layers; a plurality of first insulating layers electrically separating the lower level wiring layers and having a first physical constant; a plurality of third insulating layers electrically separating the upper level wiring layers and having a third physical constant different from the first physical constant; a plurality of second insulating layers electrically separating the middle level wiring layers and having a second physical constant having an intermediate value between the first and third physical constants.  
           [0019]    With these configurations, the reliability of a semiconductor device having multilevel wiring layers can be improved while the performance thereof is maintained high. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    [0020]FIG. 1 is a schematic cross sectional view of a semiconductor device having multilevel wiring layers according to an embodiment of the invention.  
         [0021]    [0021]FIGS. 2A and 2B are schematic cross sectional views showing a partial structure of multilevel wiring layers.  
         [0022]    [0022]FIGS. 3A and 3B are schematic cross sectional views showing a partial structure of multilevel wiring layers.  
         [0023]    [0023]FIG. 4 is a schematic cross sectional view showing a partial structure of multilevel wiring layers.  
         [0024]    [0024]FIG. 5 is a graph showing stress generated in the multilevel wiring structure shown in FIG. 1 as a function of height.  
         [0025]    [0025]FIG. 6 is a graph showing a vertical stress difference between a wiring pattern and a via conductor formed in stacked insulating layers made of various materials.  
         [0026]    [0026]FIGS. 7A, 7B and  7 C are graphs showing a relation between physical constants and a dielectric constant of various insulating materials.  
         [0027]    [0027]FIGS. 8A, 8B and  8 C are cross sectional views showing examples of a wiring structure according to prior art. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0028]    [0028]FIG. 1 is a schematic cross sectional view of a semiconductor device having multilevel wiring layers according to an embodiment of the invention. In the surface layer of an Si substrate  11 , an element separation region  12  is formed by shallow trench isolation (STI) and a number of semiconductor elements such as MOS transistors are formed. An undoped or phosphor (P) and/or boron (B) doped silicon oxide layer  14  is formed burying the semiconductor elements.  
         [0029]    Contact holes are formed through the silicon oxide layer  14 . A contact plug and/or a local interconnect  16  made of barrier metal, tungsten (W) and the like is buried in the contact holes. A Cu diffusion preventing and etch stopper layer  15  of SiC or the like is formed on the silicon oxide layer  14 , covering the surface of the contact plug and/or local interconnect. On this Cu diffusion preventing and etch stopper layer  15 , an organic insulating layer  21  of SiLK or the like having a low dielectric constant is formed. A hard mask layer  22  of SiC or the like is formed on the surface of the organic insulating layer  21 . Wiring trenches and via holes are formed in these insulating layers, and a barrier metal layer and a Cu layer are buried in these trenches and via holes to form a first wiring layer M 1 L. A Cu diffusion preventing and etch stopper layer  23  of SiC or the like is formed on the surface of the hard mask layer  22 , covering the surface of the first wiring layer M 1 L. On the Cu diffusion preventing and etch stopper layer  23 , an organic insulating layer  24  of SiLK having a low dielectric constant and a hard mask layer  25  of SiC or the like are stacked similar to the lower level layers. A second wiring layer M 2 L of Cu is buried in the organic insulating layer  24 . On the hard mask layer  25 , a third wiring layer M 3 L similar to the second wiring layer is formed by using a Cu diffusion preventing layer  26 , a low dielectric organic insulating layer  27 , a hard mask layer  28  and the third wiring layer M 3 L of barrier metal and Cu.  
         [0030]    On the third wiring layer, a fourth wiring layer M 4 L having a similar structure is formed. On the fourth wiring layer M 4 L, a Cu diffusion preventing layer  31 , an SiOC layer  32 , an etch stopper layer  33  of SiC and an SiOC layer  34  are stacked and wiring trenches and via holes are formed. A barrier metal layer and a Cu layer are buried therein to form a fifth wiring layer M 5 L.  
         [0031]    On the fifth wiring layer M 5 L, a Cu diffusion preventing layer  35 , an SiOC layer  36 , an SiC etch stopper layer  37  and an SiOC layer  38  are stacked and wiring trenches and via holes are formed. A barrier metal layer and a Cu layer are buried therein to form a sixth wiring layer M 6 L. Seventh and eighth wiring layers M 7 L and M 8 L having a similar structure are formed.  
         [0032]    On the eighth wiring layer M 8 L, a Cu diffusion preventing layer  41 , an silicon oxide layer  42 , an SiC etch stopper layer  43  and an silicon oxide layer  44  are stacked and wiring trenches and via holes are formed. A barrier metal layer and a Cu layer are buried therein to form a ninth wiring layer M 9 L.  
         [0033]    On the ninth wiring layer M 9 L, a Cu diffusion preventing layer  45  of SiC, a silicon oxide layer  46 , a Cu diffusion preventing layer  47  and a silicon oxide layer  48  are stacked and wiring trenches and via holes are formed. A barrier metal layer and a Cu layer are buried therein to form a tenth wiring layer M 10 L.  
         [0034]    On the tenth wiring layer M 10 L, a Cu diffusion preventing layer  51  of SiC and an insulating layer  52  of silicon oxide or the like are stacked and connection conductors  50  are buried penetrating through these insulating layers. An electrode layer of aluminum (Al) or the like is deposited and patterned to form an eleventh wiring layer M 11 L. A silicon oxide layer  53 , a silicon nitride layer  54  and the like are stacked covering the eleventh wiring layer M 11 L. Openings are formed through the lamination of the silicon oxide layer  53  and silicon nitride layer  54  to expose the surfaces of pads.  
         [0035]    [0035]FIG. 2A shows an example of the structure of the first wiring layer M 1 L. The distance between the conductive plug  16  and first wiring layer M 1 L is, for example, about 300 nm. For example, the line width of the first wiring layer is 0.14 μm, the wiring pitch is 0.28 μm, and the wiring thickness is 250 nm. The SiC layer  15  has a dielectric constant of 4.5 and a thickness of 50 nm. The SiLK layer  21  has a dielectric constant of 2.7 and a thickness of 250 nm+200 nm. The SiC layer  22  has a dielectric constant of 4.5 and a thickness of 50 nm. The SiC layer  23  has a thickness of 50 nm.  
         [0036]    [0036]FIG. 2B shows an example of the structure of the second to fourth wiring layers M 2 L to M 4 L. For example, the SiC layer  23  of 50 nm thick, SiLK layer  24  of 450 nm thick and SiC layer  25  of 50 nm thick are stacked and the second (third, fourth) wiring layer M 2 ( 3 ,  4 )L is buried. The wiring layer has a thickness of about 250 nm and both a line width and wiring pitch of about 0.14 μm. The distance to the lower level wiring layer is, for example, about 300 nm.  
         [0037]    [0037]FIG. 3A shows an example of the structure of the fifth wiring layer M 5 L. The SiC layer  31  having a thickness of about 70 nm, SiOC layer  32  having a thickness of about 350 nm, SiC layer  33  having a thickness of about 30 nm and SiOC layer  34  having a thickness of about 350 nm are stacked. A wiring trench is formed to a depth of about 400 nm from the surface of the laminated layer, and a via hole is formed to the remaining depth. A barrier metal layer and a Cu wiring layer are buried in the wiring trench and via hole to form the fifth wiring layer M 5 L. The SiC layer  35  is formed on the surface of the fifth wiring layer.  
         [0038]    For example, the fifth wiring layer M 5 L has a height of about 400 nm, a wiring width is 0.28 μm and the wiring pitch is 0.56 μm, and a distance to the lower level wiring layer of about 400 nm.  
         [0039]    [0039]FIG. 3B shows an example of the structure of the sixth to eighth wiring layers M 6 L to M 8 L. This structure will be described by taking the sixth wiring layer as an example. On the fifth wiring layer M 5 L, the SiC layer  35  having a thickness of about 70 nm, SiOC layer  36  having a thickness of about 550 nm, SiC layer  37  having a thickness of about 30 nm and SiOC layer  38  having a thickness of about 350 nm are stacked.  
         [0040]    A wiring trench is formed to a depth of 400 nm from the surface of the laminated layer and a via hole is formed through the remaining depth of 600 nm. A barrier metal layer and a Cu layer are buried in the wiring trench and via hole to form the sixth wiring layer M 6 L. The SiC layer  39  having a thickness of about 70 nm is formed covering the sixth wiring layer.  
         [0041]    [0041]FIG. 4 shows an example of the structure of the ninth and tenth wiring layers M 9 L and M 10 L. On the lower level wiring layer, the SiG layer  41  having a thickness of about 70 nm, silicon oxide film  42  having a thickness of about 550 nm, SiC layer  43  having a thickness of about 30 nm and silicon oxide layer  44  having a thickness of about 850 nm are stacked.  
         [0042]    A wiring trench is formed to a depth of 900 nm from the surface of the laminated layer and a via hole reaching the lower level wiring is formed. A barrier metal layer and a Cu layer are buried in the wiring trench and via hole to form the ninth wiring layer M 9 L. The SiC layer  45  is formed covering the ninth wiring layer. The ninth wiring layer M 9 L has a height of about 900 nm and a wiring width is 0.42 μm and the wiring pitch is about 0.84 μm.  
         [0043]    Reverting to FIG. 1, the structure of insulating layers of the multilevel wiring will be studied. In the studies, the Cu diffusion preventing layer, etch stopper layer, hard mask layer and the like are excluded. The interlayer insulating layers for the lower level wiring layer are made of an organic insulating layer of SiLK. The interlayer insulating layers for the upper level wiring layers of the ninth and tenth wiring layers M 9 L and M 10 L are made of a silicon oxide layer. The interlayer insulating layers for the middle level wiring layers from the fifth to eighth wiring layers M 5 L to M 8 L are made of an SiOC layer.  
         [0044]    The thermal expansion coefficient, modulus of elasticity, density, hardness and the like of SiOC take intermediate values between silicon oxide and SiLK of an organic insulating film. As compared to the multilevel wiring structure having a silicon oxide layer formed directly on an organic insulating layer, if an interlayer insulating layer of SiOC is disposed between an organic insulating layer and a silicon oxide layer, the generation of stress and the like to be caused by a difference of a physical constant between the upper and lower level layers can be suppressed.  
         [0045]    [0045]FIG. 5 shows the calculation results of stress generated in the wiring layers shown in FIG. 1. A circle plot represents an in-plane stress and a square plot represents a stress along a plane normal direction. The abscissa represents a height of a wiring layer and the ordinate represents the magnitude of stress.  
         [0046]    In the lower layers, the stress in the via hole along the normal direction takes a large minus value, and in the upper layers the stress in the via hole takes a large plus value. If these upper and lower layers are stacked directly, it is expected that a large stress difference is generated between the upper and lower layers. If SiOC middle layers are used as the interlayer insulating layers for multilevel wiring layers excluding the etch stopper layer and hard mask layer, a change in the stress can be relaxed as shown in FIG. 5. Such relaxation of the stress may be ascribed to a gradual change in the dielectric constants of the lower, middle and upper interlayer insulating layers. This gradual change may also be applied to the effective dielectric constant of a plurality of insulating layers including the etch stopper layer and hard mask layer.  
         [0047]    In the structure shown in FIG. 1, the same insulating material is used for each wiring layer, excepting the etch stopper layer and hard mask layer. The two insulating layers on an intermediate thin layer as an etch stopper layer disposed between the two layers are made of the same material. The insulating layer at the side of a wiring pattern and the insulating layer at the side of a via conductor may be made of different materials.  
         [0048]    [0048]FIG. 6 shows vertical stress differences between a wiring pattern and a via conductor when the insulating layer in which the wiring pattern is buried and the insulating layer in which the via conductor is buried are made of various materials. The abscissa represents a wiring width in the unit of μm and the ordinate represents a vertical stress difference between a wiring pattern and a via conductor in the unit of MPa. The larger the stress difference is, the higher the possibility of defects in the wiring becomes.  
         [0049]    A curve s 1  indicates a stress difference when the insulating layer on the upper surface of a wiring pattern is an organic insulating layer of SiLK, and the insulating layers at the side of a wiring pattern and at the side of a via conductor are organic insulating layers of SiLK. A curve s 2  indicates a stress difference when the insulating layer at the upper level of a wiring pattern is made of SiOC and the insulating layers at the side of a wiring pattern and at the side of a via conductor are organic insulating layers of SiLK. A curve s 3  indicates a stress difference when the insulating layer at the upper level of a wiring pattern and the insulating layer at the side of a wiring pattern and at the side of a via conductor are made of silicon oxide. A curve s 3 ′ indicates a stress difference when a portion of the insulating layer in which a wiring layer is buried is made of SiLK. A curve s 4  indicates a stress difference when the insulating layer at the upper surface of a wiring pattern is made of silicon oxide and the insulating layers at the side of a wiring pattern and at the side of a via conductor are made of SiOC.  
         [0050]    The stress difference when the insulating layer burying a wiring layer is made of SiLK is greatly different from the stress difference when the insulating layer burying a wiring layer is made of silicon oxide. A middle value between these two stress differences corresponds to the stress difference when the insulating layer burying the wiring pattern is made of silicon oxide and the insulating layer burying the via conductor is made of SiOC.  
         [0051]    It can be understood that the stress difference can be made small by disposing, between the upper and lower wiring layers, an interlayer insulating films having the mixed characteristics of the interlayer insulating layers for the upper and lower wiring layers. FIGS. 7A, 7B and  7 C show the physical constants of various insulating materials. The abscissa represents a dielectric constant, the ordinate in FIG. 7A represents a thermal expansion coefficient, the ordinate in FIG. 7B represents a modulus of elasticity, and the ordinate in FIG. 7C represents a density and a hardness.  
         [0052]    As shown in FIG. 7A, the dielectric constant is approximately in reverse proportion to the thermal expansion coefficient. As the dielectric constant lowers, the thermal expansion coefficient becomes high. Organic insulating materials such as SiLK and F-doped polyimide have a high thermal expansion coefficient. Porous silicon oxide also has a high thermal expansion coefficient. Namely, insulating materials having a low dielectric constant have a high thermal expansion coefficient. As compared to these materials, the thermal expansion coefficient of silicon oxide is lower by one digit or more. There is the tendency that the thermal expansion coefficient increases in the order of silicon oxide, F-doped silicon oxide, polyimide and SiOC.  
         [0053]    [0053]FIG. 7B shows the relation between a dielectric constant and a modulus of elasticity. There is the tendency that as the dielectric constant lowers, the modulus of elasticity lowers exponentially. FIG. 7C shows the relation between a dielectric constant and a density and the relation between a dielectric constant and a hardness. A circle plot represents the density and a square plot represents a hardness. Two plots in the vertical direction represent the same material having the same dielectric constant. There is the tendency that as the dielectric constant lowers, the density lowers generally linearly. As the dielectric constant lowers, the hardness lowers exponentially.  
         [0054]    In summary, the graphs shown in FIGS. 7A, 7B and  7 C indicate that the physical constants excepting the dielectric constant have a tight relation with the dielectric constant. Namely, if a different physical constant is selected, the other physical constants take different values. This tendency is the same for all physical constants. Therefore, even if the thermal expansion coefficient, modulus of elasticity, density, hardness or the like is used instead of the dielectric constant as the index for material selection, approximately the same results can be obtained. As compared to silicon oxide, the materials having a considerably low dielectric constant also have a large difference in the physical constants such as thermal expansion coefficient, modulus of elasticity, density and hardness. If materials having a large physical constant difference are stacked directly, a large stress difference is applied to the materials, which may become the cause of peeling, cracks, lowered tightness and the like. In such a case, an insulating film having an intermediate physical constant is inserted between the two materials so that the generated stress may be relaxed.  
         [0055]    If layers having different physical constants are laminated as shown in FIG. 6, the whole lamination structure having the intermediate physical constant can be expected. Therefore, if a plurality of different insulating layers are laminated, the intermediate physical constant can be expected.  
         [0056]    If an interlayer insulating layer is made of a plurality of layers, an average value of the physical constants of the layers may be used as an effective physical constant. A physical constant viewed from the wiring can be used as an effective physical constant of the interlayer insulating layer. If the same material is used for the etch stopper layer and the hard mask layer in the multilevel wiring structure, the effective physical constant of the interlayer insulating layers may be calculated by excluding the etch stopper layer and hard mask layer.  
         [0057]    The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It is apparent that various modifications, improvements, combinations, and the like can be made by those skilled in the art.