Abstract:
Disclosed include a control circuit adapted for a power controller powered by an operation voltage. When the operation voltage exceeds an over-voltage reference, the power controller stops power conversion provided by a power converter. The control circuit comprises a slope detector detecting a variation slope of the operation voltage. When the variation slope exceeds a drop rate, the slope detector recovers the power conversion. When the power conversion is recovered the power controller compares the operation voltage with the over-voltage reference.

Description:
BACKGROUND 
       [0001]    The present disclosure relates generally to control circuits and methods adapted for switched mode power supplies, and more particularly to control circuits and methods regarding to over voltage protection in switched mode power supplies. 
         [0002]    Power converters are always needed in most electronic devices, to provide adequate power with specific voltage or current that electronic devices require for proper operation. To protect those powering or powered from being damaged by fault operation conditions, most power converters are designed to equip with protection mechanisms, such as over-load protection (OLP), over-temperature protection (OTP), output-short protection (OSP), over-voltage protection (OVP), and the like. 
         [0003]    When a feedback loop of a power converter that, to regulate an output voltage, detects the condition of an output voltage is broken, the power converter might mistakenly interpret the output voltage is too low and continue raising its output power, causing the output voltage to rise accordingly. OVP could stop the output voltage from being over high, and prevent those powered by the output voltage from being over stressed. 
         [0004]      FIG. 1  illustrates a conventional power converter  8 , including flyback topology  10 , operation voltage supply  12 , and power controller  18 . Operation voltage supply  12  provides operation voltage V CC  at node VCC, powering power controller  18 , which might be in the form of a monolithic integrated circuit. 
         [0005]    When a feedback loop that detects the condition of output voltage V OUT  at output node OUT is broken, output voltage V OUT  might start to increase steadily. Due to the inductive coupling, operation voltage V CC  provided by operation voltage supply  12  increases as well. It can be designed that when operation voltage V CC  is determined to be over high power controller  18  stops the power conversion provided by power converter  8 , such that OVP is achieved. 
         [0006]      FIG. 2  exemplifies power controller  18  including oscillator  40 , pulse-width modulator  44 , OVP control circuit  30 , and gate logic  42 . Oscillator  40  provides clocks that power controller needs for timing. Pulse-width modulator  44  determines the duty cycle, the ON time of power switch  15  in proportion of a cycle time. OVP control circuit  30  prepares power-good signal S PG  to inform gate logic  42  whether operation voltage V CC  is good. Gate logic  42  controls power switch  15  via gate node GATE. 
         [0007]      FIG. 3A  shows operation voltage V CC  and power-good signal Sp PS  about the time when OVP is triggered due to a broken feedback loop. At the beginning of  FIG. 3A , operation voltage V CC  is out of regulation and continues to rise. At time point t 1  when operation voltage V CC  exceeds over-voltage reference V REF-OVP , comparator  34  resets SR flip flop  32 , power-good signal S PG  is deasserted to be “0” in logic, such that gate logic  42  deems operation voltage V CC  to be not good and keeps power switch  15  OFF accordingly, stopping the following power conversion. Thus, OVP is triggered. 
         [0008]    As the power conversion is stopped, operation voltage V CC  starts to decline because that power controller  18  is alive and consumes the power from operation voltage V CC . It might be designed that when operation voltage V CC  is lower than reference voltage V REF-RSTRT  power conversion is restarted or resumed to raise both output voltage V OUT  and operation voltage V CC . Nevertheless, power-good signal S PG  is kept as being “0” in logic until time point t 2 . As shown in  FIG. 3A , at time point t 2 , operation voltage V CC  exceeds reference voltage V REF-UV , comparator  36  and single-pulse generator  38  switch power-good signal S PG  to be “1” in logic, and gate logic  42  deems operation voltage V CC  good from now on. Hold-time T HOLD ) represents the time period when power conversion is paused or stopped. 
         [0009]      FIG. 3B  shows operation voltage V CC  and power-good signal S PS  about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC. As shown in  FIG. 3B , operation voltage V CC  soars at about time point t 3  because, for some reasons, voltage noise suddenly occurs at operation voltage node VCC. At time point t 3 , operation voltage V CC  exceeds over-voltage reference V REF-OVP , and OVP is triggered. Even though voltage noise subsides soon and operation voltage V CC  quickly goes back to its normal value, operation voltage V CC  cannot be deemed to be good until operation voltage V CC  experiences the similar event sequences shown in  FIG. 3A . Namely, operation voltage V CC  will decline to reference voltage V REF-RSTRT  and then rise to reference voltage V REF-UV , as shown in  FIG. 3B , such that power-good signal S PG  becomes “1” in logic at time point t 4 . As shown in  FIG. 3B , hold-time T HOLD  is considerably long. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0011]      FIG. 1  illustrates a conventional power converter; 
           [0012]      FIG. 2  exemplifies the power controller in  FIG. 1 ; 
           [0013]      FIG. 3A  shows operation voltage V CC  and power-good signal S PS  of  FIG. 2  about the time when OVP is triggered due to a broken feedback loop; 
           [0014]      FIG. 3B  shows operation voltage V CC  and power-good signal S PS  about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC; 
           [0015]      FIG. 4  demonstrates an OVP control circuit according to one embodiment of the invention; 
           [0016]      FIG. 5A  shows operation voltage V CC , inverted OVP signal S OVP-B , set signal S SET , and power-good signal S PS  of  FIG. 4 , about the time when OVP is triggered due to a broken feedback loop; and 
           [0017]      FIG. 5B  shows operation voltage V CC , inverted OVP signal S OVP-B , set signal S SET , and power-good signal S PS  of  FIG. 4 , about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]      FIG. 4  demonstrates OVP control circuit  60 , which, in one embodiment of the invention, replaces OVP control circuit  30  in  FIG. 2 . OVP control circuit  60  has advantage in recovering power conversion soon after voltage noise subsides, or in shortening hold-time T HOLD  during which power conversion is paused or stopped. 
         [0019]    OVP control circuit  60  has comparator  64 , comparator  68 , multiplexer  66 , low-pass filter  62 , and AND gate  70 . 
         [0020]    Low-pass filter  62  provides filtered voltage V CC-LPF  by low-passing operation voltage V CC . General circuit analysis can support that low-pass filter  62  limits the speed that filtered voltage V CC-LPF  responds to operation voltage V CC , and that the difference between filtered voltage V CC-LPF  and operation voltage V CC  equivalently corresponds to the variation slope of operation voltage V CC . For example, the quicker operation voltage V CC  drops, the more filtered voltage V CC-LPF  exceeds operation voltage V CC . 
         [0021]    When inverted OVP signal S OVP-B  outputted by comparator  64  is “1” in logic, multiplexer  66  couples over-voltage reference V REF-OVP  to the non-inverted input of comparator  64 . In the opposite, when inverted OVP signal S OVP-B  is “0” in logic, multiplexer  66  couples filtered voltage V CC-LPF  to the non-inverted input of comparator  64 . 
         [0022]    Accordingly, if inverted OVP signal S OVP-B  is “1”, it implies that operation voltage V CC  might not have been too high, and comparator  64  compares operation voltage V CC  with over-voltage reference V REF-OVP  to check whether operation voltage V CC  is too high at this moment. If inverted OVP signal S OVP-B  is “0”, it implies that operation voltage V CC  has been too high, and comparator  64  compares operation voltage V CC  with filtered voltage V CC-LPF , equivalently detecting the variation slope of operation voltage V CC . 
         [0023]    In one embodiment, comparator  64  has a hysteresis effect. When inverted OVP signal S OVP-B  is “1”, operation voltage V CC  need exceed over-voltage reference V REF-OVP  to switch inverted OVP signal S OVP-B  to “0”. When inverted OVP signal S SVP-B  is “0”, filtered voltage V CC-LPF  need exceed operation voltage V CC  a predetermined value, 0.5V for example, to switch inverted OVP signal S OVP-B  to “1”. This predetermined value, together with low-pass filter  62 , corresponds to a certain drop rate. In other words, comparator  64  and low-pass filter  62  together construct a slope detector detecting the voltage variation of operation voltage V CC . When the voltage variation of operation voltage V CC  exceeds the certain drop rate, meaning operation voltage V CC  drops quicker than the certain drop rate, comparator  64  switches inverted OVP signal S SVP-B  to “1” in logic. 
         [0024]    Comparator  68  compares operation voltage V CC  with reference voltage V REF-UV . If operation voltage V CC  is lower than reference voltage V REF-UV , comparator  68  asserts set signal S SET  to set comparator  64 , such that inverted OVP signal S SVP-B  is forced to be “1” in logic, and, as a result, comparator  64  is forced to compare operation voltage V CC  with over-voltage reference V REF-OVP . 
         [0025]    Only when operation voltage V CC  has a value between over-voltage reference V REF-OVP  and reference voltage  VREF-UV , it is possible for AND gate  70  to provide asserted power-good signal S PG , informing gate logic  42  that operation voltage V CC  is good. Otherwise, power-good signal S PG  is “0” in logic, meaning the operation voltage V CC  is not good. 
         [0026]      FIG. 5A  shows operation voltage V CC , inverted OVP signal S SVP-B , set signal S SET , and power-good signal S PS  of  FIG. 4 , about the time when OVP is triggered due to a broken feedback loop. At the beginning of  FIG. 5A , operation voltage V CC  is out of regulation due to a broken feedback loop and continues to rise. Inverted OVP signal S OVP-B  is “1” in logic, representing that operation voltage V CC  is lower than over-voltage reference V REF-OVP . 
         [0027]    At time point t 5 , operation voltage V CC  exceeds over-voltage reference V REF-OVP . Comparator  64  switches inverted OVP signal S OVP-B  to “0” in logic. Thus power good signal S PG  becomes “0” in logic, informing gate logic  42  that operation voltage V CC  is not good, such that power switch  15  maintains at an OFF state and power conversion is stopped. 
         [0028]    After time point t 5 , operation voltage V CC  declines mildly. As the voltage variation of operation voltage V CC  is relatively small, inverted OVP signal S OVP-B  remains as being “0” in logic. 
         [0029]    At time point t 6 , operation voltage V CC  is lower than reference voltage V REF-UV  to assert set signal S SET . Accordingly, comparator  64  is forced to compare operation voltage V CC  with over-voltage reference V REF-OVP  and makes inverted OVP signal S OVP-B  “1” because operation voltage V CC  is lower than over-voltage reference V REF-OVP  at this moment. Please note that power good signal S PG  is still “0” in logic, and power conversion is still stopped. 
         [0030]    When operation voltage V CC  is lower than reference voltage V REF-RSTRT  gate logic  42  restarts and power conversion is resumed or recovered to raise both output voltage V OUT  and operation voltage V CC . 
         [0031]    At time point t 7  operation voltage V CC  exceeds reference voltage V REF-UV  and power good signal S PG  is switched to be “1” in logic, informing gate logic  42  that operation voltage V CC  at present is good. 
         [0032]    Power good signal S PG  of  FIG. 5A  is substantially the same with that of  FIG. 3A . Accordingly, OVP control circuit  60  of  FIG. 4  provides substantially the same OVP function as OVP control circuit  30  of  FIG. 2  does. 
         [0033]      FIG. 5B  shows operation voltage V CC , inverted OVP signal S SVP-B , set signal S SET , and power-good signal S PS  of  FIG. 4 , about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC. In contrary to the lengthy hold-time T HOLD  in  FIG. 3B , hold-time T HOLD  in  FIG. 5B  is relatively short, meaning that power conversion could be resumed to become normal soon after voltage noise subsides. In comparison with the waveform of operation voltage V CC  in  FIG. 3B , the waveform of operation voltage V CC  in  FIG. 5B  is much flatter, resulting in better voltage regulation. 
         [0034]    Operation voltage V CC  soars at about time point t 8  because, for some reasons, voltage noise occurs at operation voltage node VCC. At time point t 8 , operation voltage V CC  exceeds over-voltage reference V REF-OVP , both inverted OVP signal S OVP-B  and power-good signal S PG  becomes “0” in logic, and power conversion is stopped. Hold-time T HOLD  starts. 
         [0035]    Operation voltage V CC  tends to quickly regain its normal value after voltage noise subsides. In the period from time point t 9  to time point t 10 , operation voltage V CC  drops quicker than the certain drop rate defined by comparator  64  and low-pass filter  62 , such that inverted OVP signal S OVP-B  is switched to “1” in logic, forcing comparator  64  to compare operation voltage V CC  with over-voltage reference V REF-OVP . Nevertheless, at this moment, operation voltage V CC  is still higher than over-voltage reference V REF-OVP,  such that inverted OVP signal S OVP-B  will be switch back to “0” in logic. As a result, inverted OVP signal S OVP-B  continues to toggle between “0” and “1” in logic. So does power-good signal S PG , as shown in  FIG. 5B . As power conversion is recovered very briefly, very little power, if any, is converted and operation voltage V CC  continues to drop and regain its normal value. 
         [0036]    After time point t 10 , operation voltage V CC  is surly lower than over-voltage reference V REF-OVP . Both inverted OVP signal S OVP-B  and power-good signal S PG  stay at “1” in logic. Power conversion starts to properly work, claiming the end of hold-time T HOLD  in  FIG. 5B . 
         [0037]    It can be found from  FIG. 5B  that power-good signal S PG  is stabilized to be “1” in logic soon after voltage noise subsides. According, hold-time T HOLD  of  FIG. 5B  is very short. The result shown in  FIG. 5B  also demonstrates that OVP control circuit  60  of  FIG. 4  provides better output voltage regulation than OVP control circuit  30  of  FIG. 2  does. 
         [0038]    In another embodiment of the invention, a high-pass filter is used to detect the voltage variation of operation voltage V CC , and a comparator determines whether the voltage variation exceeds a certain drop rate, to perform the functionality similar with what OVP control circuit  60  of  FIG. 4  provides. 
         [0039]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.