Abstract:
A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

Description:
PRIORITY CLAIM 
       [0001]    This application claims the priority benefit of French Application for Patent No. 1563507, filed on Dec. 31, 2015, the disclosure of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law. 
       TECHNICAL FIELD 
       [0002]    The present disclosure relates to the field of transistors, in particular to a MOS transistor formed inside and on top of a strained active area. 
       BACKGROUND 
       [0003]    The performance of certain types of MOS transistors may be improved by the presence of strain in the channel region. 
         [0004]    In particular, in a P-channel MOS transistor having a SiGe silicon-germanium channel region, directed along crystal direction &lt;100&gt;, the mobility of holes is increased by compressive strain oriented along the drain-source direction, that is, the direction of the transistor length. However, compressive strain in the direction of the transistor width decreases the mobility of holes. It is desirable to increase the mobility to increase the transistor speed. 
         [0005]    Known methods to form strained transistors raise various problems, particularly in the case of transistors having very small dimensions, formed inside and on top of active areas having a length shorter than 400 nm. 
       SUMMARY 
       [0006]    An embodiment provides a method of forming a transistor, comprising the steps of: a) forming a semiconductor layer extending on an insulating layer; b) thermally oxidizing the semiconductor layer across its entire thickness to form two bars extending in the transistor gate width direction; and c) forming insulating trenches directed along the transistor gate length direction, the semiconductor layer being strained before or after step a). 
         [0007]    An embodiment provides a method of forming a transistor comprising the steps of: a′) forming a strained semiconductor layer extending on an insulating layer; b′) thermally oxidizing the strained layer across its entire thickness to form two bars extending in the transistor gate width direction; and c′) forming insulating trenches directed along the transistor gate length direction. 
         [0008]    According to an embodiment, step b′) occurs after step a′). 
         [0009]    According to an embodiment, step a′) occurs after step b′). 
         [0010]    According to an embodiment, the strained layer is made of silicon-germanium, the strain being compressive strain. 
         [0011]    According to an embodiment, the strained layer has a thickness in the range from 5 to 8 nm. 
         [0012]    According to an embodiment, step a′) is carried out at a temperature in the range from 850 to 1,000° C. for a time period in the range from 5 to 15 min. 
         [0013]    According to an embodiment, the strained layer is made of silicon, the strain being extension strain. 
         [0014]    An embodiment provides a transistor formed inside and on top of an active area of a semiconductor layer, the active area being delimited, lengthwise, by thermal oxide bars imposing in the active area strain along the transistor gate length direction and, along the transistor gate width direction, by insulating trenches leaving the active area free of strain widthwise. 
         [0015]    According to an embodiment, the strained semiconductor layer is made of silicon-germanium and rests on a silicon oxide insulating layer, the oxide bars being made of silicon oxide and of germanium, the strain being compressive strain. 
         [0016]    According to an embodiment, the strained semiconductor layer is made of silicon, the oxide bas being made of silicon oxide, the strain being extension strain. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, wherein: 
           [0018]      FIG. 1  is a perspective view of a MOS transistor formed inside and on top of an active area; 
           [0019]      FIGS. 2A to 2C  illustrate an embodiment of a MOS transistor; 
           [0020]      FIG. 2D  illustrates the mobility of holes in P-channel MOS transistors obtained by the method illustrated in  FIGS. 2A to 2C ; 
           [0021]      FIGS. 3A to 8A and 3B to 6B, 7C and 8B  illustrate an example of a MOS transistor manufacturing method; 
           [0022]      FIGS. 9A to 12A and 9B to 12B  illustrate another example of a MOS transistor manufacturing method; 
           [0023]      FIGS. 13A and 13B  are cross-section views illustrating a method for obtaining a strained layer; and 
           [0024]      FIG. 14  illustrates compressive strains in strained layer portions. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    The same elements have been designated with the same reference numerals in the different drawings and, further, the various drawings are not to scale. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, gate structure details such as gate insulators and insulating spacers are not shown. 
         [0026]    In the following description, when reference is made to terms qualifying position, such as terms “bottom”, “upper”, etc., or terms qualifying direction such as terms “horizontal”, “vertical”, etc., reference is made to the orientation of the concerned element in  FIGS. 1, 2A to 2C and 3B to 8B . Unless otherwise specified, expression “in the order of” means to within 10%, preferably to within 5%. 
         [0027]      FIG. 1  is a perspective view of a MOS transistor formed inside and on top of a rectangular active area. The active area formed in a layer of semiconductor (Si) on insulator (SiO 2 ) is laterally delimited by insulators, not shown. The transistor comprises a gate structure G separating a drain area D from a source area S. The gate has a length l between the drain and source areas and a width W in the orthogonal direction. The transistor dimension in the gate length direction will here be called length L and its dimension in the gate width direction will be called width W of the transistor. 
         [0028]      FIGS. 2A to 2C  illustrate an embodiment of a P-channel MOS transistor. 
         [0029]      FIG. 2A  is a cross-section view of a wafer portion at an initial manufacturing step. A silicon oxide insulating layer  1  is arranged on a support  3 . A strained semiconductor layer  5 , for example, made of SiGe, extends on insulating layer  1  and is covered with a silicon oxide layer  7 . Layers  5  and  7  for example have been formed from the thin upper silicon layer of a structure of silicon-on-insulator type, SOI. To form layers  5  and  7 , a SiGe epitaxy is first carried out on the thin silicon layer. During the epitaxy, a lattice mismatch causes biaxial horizontal compressive strain  9  in the epitaxial layer. Then, the upper surface of the assembly is thermally oxidized. The silicon preferably oxidizes and the germanium migrates down-wards, while strain  9  intensifies. SiGe layer  5  is then obtained on insulating layer  1  and under silicon oxide layer  7 . 
         [0030]    As an example, SiGe layer  5  has a thickness in the range from 5 to 8 nm. Silicon oxide layer  7  may have a thickness in the range from 3 to 6 nm. The proportion of germanium in layer  5  may be in the range from 10 to 40%. 
         [0031]    At the step illustrated in  FIG. 2B , insulating trenches  10  have been etched by using masking layers  11 . Trenches  10  thoroughly cross SiGe layer  5  and surround active areas  12 . Insulating trenches  10  may thoroughly cross insulating layer  1 . For clarity, only two trenches  10  and one active area  12  are shown, the distance between trenches corresponding in the view of  FIG. 2B  to the length L of the transistor to be formed. The digging of the trenches has disengaged the edges of active area  12 . Thereby, only a residual portion  13  of the initial strain  9  remains in a central portion of active area  12 . 
         [0032]    At the step illustrated in  FIG. 2C , a P-channel MOS transistor has been obtained. Insulating trenches  10  have been filled with an insulator  14 , for example, silicon oxide. A gate structure  15  has been formed on a central portion of active area  12 . Drain and source areas  17 , for example, made of boron-doped silicon-germanium, have been formed by epitaxy on either side of gate structure  15 . 
         [0033]      FIG. 2D  illustrates the mobility of holes μ H  in arbitrary units in transistors obtained by the method of  FIGS. 2A to 2C , according to length L of the transistors. The lengthwise strain has been released on digging of the insulating trenches, the width for example being 170 nm. Residual lengthwise strain  13  is all the smaller as the transistor length is short. In a transistor shorter than 180 nm, the mobility of holes is smaller by 65% than the mobility of holes in a transistor longer than 500 nm. 
         [0034]    It is thus desired to have a method enabling to form a transistor from a strained semiconductor layer without releasing the lengthwise strain in this layer. 
         [0035]      FIGS. 3A to 8A  are top views illustrating successive steps of an example of a MOS transistor manufacturing method.  FIGS. 3B to 6B  are cross-section views along a plane BB orthogonal to the width direction, respectively corresponding to  FIGS. 3A to 6A .  FIG. 7C  is a cross-section view along plane CC of  FIG. 7A  and  FIG. 8B  is a perspective and cross-section view corresponding to  FIG. 8A . 
         [0036]    In  FIGS. 3A and 3B , a strained semiconductor layer  20 , for example, made of SiGe, extends on an insulator  22  covering a support  24 . Layer  20  has been obtained, for example from a SOI-type structure by a method similar to that described in relation with  FIG. 2A  that is, comprising a SiGe epitaxy followed by a thermal oxidation. A silicon oxide layer  25  covers SiGe layer  20 . Strain  26  in layer  20  is horizontal and biaxial. The strain has a lengthwise component  28  and a widthwise component  30 . 
         [0037]    In  FIGS. 4A and 4B , a masking layer  32 , for example, made of silicon nitride, is deposited over the upper surface of the assembly. Openings  34  are etched in the masking layer and in silicon oxide layer  25  all the way to the upper surface of strained SiGe layer  20 . The etched areas form, in top view, bands  36  parallel in the width direction. At this step, strain  26  in layer  20  is not modified. 
         [0038]    In  FIGS. 5A and 5B , a thermal oxidation is carried out in layer  20  from openings  34 . The portions of layer  20  located at the bottom of openings  34  are oxidized across their entire thickness. The formed oxide forms parallel insulating bars  38 , in contact with insulating layer  22 . The vertical dimension or height of the bars is greater than the total thickness of strained layer  20  and of silicon oxide layer  25 . A portion  40  of layer  20  is thus insulated on both sides between oxide bars  38 . 
         [0039]    It should be noted that the oxidation step does not release strain  26  in layer portion  40 . Component  28  of the strain is thus maintained by thermal oxide bars  38  along the entire length of portion  40  without being attenuated. Further, the volume increase of the oxidized portions of layer  20  may even add an additional compression to component  28 . 
         [0040]    The thermal oxidation of SiGe may be carried out in a furnace at a temperature lower than 1,000° C. for a time period in the range from a few minutes, for example, 3 minutes, to a few tens of minutes, for example, 100 minutes. This oxidation may also be performed by rapid thermal oxidation at a temperature in the range from 950 to 1,200° C. for a time period in the range from a few tens of seconds, for example, 30 seconds, to a few hundreds of seconds, for example, 1,000 seconds. 
         [0041]    In  FIGS. 6A and 6B , masking layer  32  and oxide layer  25  have been removed by etching. The height of bars  38  has been decreased by the etching of the silicon oxide layer, but remains greater than the thickness of the SiGe layer portion  20 . Strain  26  is thus maintained in portions  40  of layer  20  by oxide bars  38  which are used as stops. 
         [0042]      FIGS. 7A and 7C  illustrate the structure at a subsequent manufacturing step.  FIG. 7C  is a cross-section view along plane CC of  FIG. 7A  and not, as previously, along plane BB. Two trenches  50  have been dug in the direction of the device length. Thus, the assembly of trenches  50  and of thermal silicon oxide regions  38  delimits an active SiGe area  52 . Trenches  50  may extend in substrate  24 , conversely to openings  34  which stop at the surface of strained SiGe layer  20 . Conversely to openings  34  which preserve strain  28  in layer  20  in the direction of the device length, trenches  50  practically totally remove strain  30  in the gate width direction, as described hereabove in relation with  FIGS. 2A to 2D . Such a strain removal is all the more significant as active area  52  is narrow, which is the current case, the active areas for example having a length shorter than 300 nm and a width shorter than 200 nm. 
         [0043]      FIG. 8A  shows a subsequent step of the manufacturing method and  FIG. 8B  is a cross-section view along plane BB and in perspective. As illustrated in  FIG. 8B , trenches  50  have been filled with an insulator  54 , after which a gate  60  and epitaxial drain and source overthicknesses  62  have been formed. 
         [0044]    A transistor occupying the surface of active area  52 , with released widthwise strain and with strain  28  maintained lengthwise, is thus obtained. As previously indicated, the holding of the lengthwise strain and its suppression widthwise cause the forming of a particularly fast transistor. 
         [0045]      FIGS. 9A to 12A  are top views illustrating successive steps of another example of a MOS transistor manufacturing method.  FIGS. 9B to 12B  are cross-section views along a plane BB orthogonal to the gate width direction, respectively corresponding to  FIGS. 9A to 12A . 
         [0046]    In  FIGS. 9A and 9B , a masking layer  72 , for example, made of silicon nitride, is deposited over the upper surface of upper silicon layer  70  of an SOI structure. The SOI structure comprises, under upper layer  70 , an insulator  22  covering a support  24 . Openings  74  are etched in masking layer  72  all the way to the upper surface of layer  70 . Openings  74  form, in top view, bands  36  in the width direction. 
         [0047]    In  FIGS. 10A and 10B , semiconductor layer  70  is thermally oxidized from openings  74 . The oxidized portions of layer  70  form insulating bars  76  in contact with insulating layer  24 . As a variation, to form insulating bars  76 , layer  70  may be etched across its entire thickness from openings  74 , after which the etched portions and openings  74  may be filled with oxide. 
         [0048]    In  FIGS. 11A and 11B , masking layer  72  is first removed by etching. A SiGe layer  78  is then epitaxially grown on the upper surface of the non-oxidized portions of semiconductor layer  70 . During the epitaxy, a lattice mismatch causes compressive strain in layer  78 , as described in relation with  FIG. 2A . The obtained layer  78  is strained  80  both widthwise and lengthwise. 
         [0049]    In  FIGS. 12A and 12B , a thermal oxidation is performed. As previously described, germanium migrates downwards to form strained SiGe layer portions  82  arranged between bars  76 . During the oxidation, a silicon oxide layer  84  forms on layer  82 . 
         [0050]    After removal by etching of oxide layer  84 , an assembly corresponding to the step illustrated in  FIGS. 6A and 6B , where portions  40  of strained layer between bars  38  are replaced with equivalent layer portions  82 , is obtained. Similarly to portions  40  of  FIGS. 6A and 6B , layer portions  82  are strained  88  widthwise and are strained  86  lengthwise between bars  76  which are used as stops. 
         [0051]    A transistor is then formed after steps equivalent to the steps illustrated in top view in  FIGS. 7A and 8A , the strain in the gate width direction being released by the forming of trenches in a direction orthogonal to that of strips  36 . 
         [0052]    In the above-described methods, strained layers are obtained for enabling a particularly fast transistor to be formed. Other methods such as methods recited in patent application US 2007/0262392 or patent application US 2008/0251842 were proposed previously for obtaining a strained portion of a silicon layer by thermally oxidizing two bars at both sides of the layer. 
         [0053]      FIGS. 13A and 13B  are cross-section views illustrating such a method for obtaining a strained silicon layer portion. 
         [0054]    In  FIG. 13A , an SOI structure is provided, made of a silicon upper layer  90  positioned on an insulator (BOX)  22  covering a support  3 . A mask  92  is deposited over the SOI structure, and openings  94  are then etched in the mask down to the upper surface of silicon layer  90 . 
         [0055]    In  FIG. 13B , a thermal oxidation is carried out in layer  90  through openings  94 , down to the upper surface of the insulator  22 , and next the mask is removed. Thus, oxide bars  96  are formed in contact with insulator  22 . A lengthwise compressive strain (not shown) is obtained in a portion  98  of the layer  90  between the bars  96 . 
         [0056]      FIG. 14  shows curves illustrating lengthwise compressive strains  86  and  100  in strained layer portions, each of 120 nm in length between two bars, as a function of the distance from one of the bars. The curve  100  illustrates the strain in the silicon layer portion  98  obtained by the method of  FIGS. 13A and 13B . The curve  86  illustrates the strain in the SiGe layer portion  82  of an assembly corresponding to the step of  FIG. 6A  obtained by implementing the steps of  FIGS. 9A to 12B . 
         [0057]    The center region of each strained layer portion corresponds to a channel region of a transistor, and the higher the lengthwise compressive strain level of this channel region, the faster the transistor. On one hand, in curve  86 , the lengthwise compressive strain near the center of the strained SiGe layer is more than 0.8%, enabling a particularly fast transistor to be formed. On the other hand, the lengthwise compressive strain of curve  100  nearly vanishes near the center of the silicon layer. Therefore, transistors having channel regions obtained by manufacturing methods such as the methods of  FIGS. 3A to 8C  or  FIGS. 9A to 12B  are faster than similar transistors having channel regions obtained by the method of  FIGS. 13A and 13B  or the like. 
         [0058]    Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, although, in the above-described example of a method, the insulating trench forming step described in relation with  FIGS. 7A and 7C  occurs after the steps described in relation with  FIGS. 3A to 6A  of forming of thermal oxide bars, the insulating trenches may be formed and filled before the forming of the thermal oxide bars. 
         [0059]    Further, although the above-described examples of methods concern the forming of a P-channel MOS transistor from a compressively strained SiGe layer, a similar method may be used to form active semiconductor areas with a lengthwise strain and no widthwise strain, or conversely. In particular, an N-channel MOS transistor may be formed from a silicon layer with an extension strain. 
         [0060]    Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.