Abstract:
An ultra-low voltage rail-to-rail operational transconductance amplifier (OTA) is based on a standard digital 0.18 μm CMOS process. Techniques for designing a 0.8 volt fully differential OTA include bias and reference current generator circuits. To achieve rail-to-rail operation, complementary input differential pairs are used, where the bulk-driven technique is applied to reduce the threshold limitation of the MOSFET transistors. The OTA gain is increased by using auxiliary gain boosting amplifiers.

Description:
REFERENCE TO RELATED APPLICATION 
   The present application claims the benefit of U.S. Provisional Patent Application No. 60/479,506, filed Jun. 19, 2003, whose disclosure is hereby incorporated by reference in its entirety into the present disclosure. 

   STATEMENT OF GOVERNMENT INTEREST 
   The work leading to the present invention was supported in party by the DARPA/ITO under AFRL Contract F29601-00-K-0182, the National Science Foundation under Contract No. CCR-0304574, and the Fulbright Program under Grant No. 87481764. The government has certain rights in the invention. 

   FIELD OF THE INVENTION 
   The present invention is directed to a bulk-driven operational amplifier and more particularly to such an amplifier exhibiting high gain, suitable for use in system-on-chip applications requiring low power. 
   DESCRIPTION OF RELATED ART 
   The reduction in the minimum dimensions in VLSI technologies, along with the trend of using small portable devices, necessitates reduced power supply voltages. In order to facilitate submicrometer high density systems on a single integrated circuit (IC), voltage levels must be lowered to ensure reliability. Threshold voltages of future CMOS technologies may not decrease much below what is available today, making it difficult to design analog circuits with lower supply voltages. 
   In analog circuit design, the threshold voltage of a transistor should be lowered in proportion to the reduction in the supply voltage to appropriately bias the device. This characteristic makes standard low voltage analog circuits incompatible with CMOS technology trends. To combat this conflict without requiring the development of expensive CMOS technologies with lower threshold voltages, novel circuit design techniques must be developed that are compatible with future CMOS technologies. 
   A promising approach in low voltage analog circuits is the so-called “bulk-driven” MOSFET method. In this method, the gate-to-source voltage is set to a value sufficient to form an inversion layer, and an input signal is applied to the bulk terminal. In this manner, the threshold voltage of a MOSFET can be reduced or even removed from the signal path. 
   The concept of a bulk-driven MOS transistor was first proposed in A. Guzinski, M. Bialko, and J. C. Matheau, “Body-Driven Differential Amplifier for Application in Countinous-Time Active-C Filter,”  Proceedings of the European Conference on Circuit Theory and Design , pp. 315–319, June 1987, as active components in an OTA differential input stage. Later, in 1991, the concept was used in the practical realization of a software-programmable CMOS telephone circuit, as reported in F. Dielacher, J. Houptmann, and J. Resinger, “A Software Programmable CMOS Telephone Circuit,”  IEEE Journal of Solid - State Circuits , Vol. 26, No. 7, pp. 1015–1026, July 1991. However, not until 1998 did the method draw significant attention as a viable low-voltage analog design technique, as reported in B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, “Design 1-V Op Amps Using Standard Digital CMOS Technology,”  IEEE Transactions on Circuits and Systems II. Analog and Digital Signal Processing , Vol. 45, No. 7, pp. 769–780, July 1998. Specifically, in Blalock et al, a 1 volt Op Amp was designed in a standard CMOS digital process utilizing the depletion characteristics of bulk-driven transistors. 
   One important drawback of the bulk-driven method, however, is that the body transconductance g mb  is approximately five times smaller than the gate transconductance g m . Thus, when the input differential pair of an amplifier is composed of bulk-driven transistors, the resulting DC gain is relatively low. This behavior is the primary reason for the low gain (around 45 dB) in previously reported bulk-driven amplifiers, as reported in Blalock et al and in F. Bahmani and S. M. Fakhraie, “A Rail-to-Rail, Constant-G m , 1-Volt CMOS Opamp,”  Proceedings of the IEEE International Symposium on Circuits and Systems , Vol. 2, pp. 669–672, May 2000. 
   SUMMARY OF THE INVENTION 
   It is thus an object of the present invention to improve the gain of bulk-driven amplifiers. To achieve the above and other objects, the present invention is directed to an ultra-low voltage rail-to-rail operational transconductance amplifier (OTA) which can be based on a standard digital 0.18 μm CMOS process. To achieve rail-to-rail opera-tion, complementary input differential pairs are used, where the bulk-driven technique is applied to reduce the threshold limitation of the MOSFET transistors. The OTA gain is increased by using auxiliary gain boosting amplifiers. This additional circuitry enables the OTA to operate at 0.8 volts, achieving an open loop gain of 68 dB while consuming 94 μW. The DC gain of the amplifier is the highest gain achieved to date in bulk-driven amplifiers. 
   In a preferred embodiment, a 0.8 volt fully differential folded-cascode OTA is presented. Both PMOS and NMOS bulk-driven input differential pairs are used to achieve full rail-to-rail operation. A continuous-time common mode feedback circuit is adopted in order to suppress variations in the output common mode. Four common-source gain boosting amplifiers are used to increase the gain to the target level of 68 dB (the DC gain was around 48 dB before gain boosting). That gain is the highest gain achieved to date in bulk-driven amplifiers. A bias circuitry which generates the required bias voltages for the amplifier core along with a low-sensitivity reference current generator circuit are also used in the preferred embodiment. 
   The design of an ultra-low voltage, high performance folded-cascode OTA circuit in a standard digital CMOS process will be disclosed. To accommodate a low power supply voltage (0.8 volt), the bulk-driven MOSFET approach is used. The low gain disadvantage of the bulk-driven technique is circumvented by employing gain boosting amplifiers, permitting the achievement of a DC gain of 68 dB. Due to a lower body transconductance, bulk-driven amplifiers inherently exhibit relatively poor gain. The low gain is the primary reason why amplifiers reported in Blalock et al and in Bahmani et al have only exhibited a DC gain as high as 45 dB. The present invention offers an advantage in that that bulk-driven amplifiers can be modified to operate with low power supply voltages while still exhibiting performance levels that satisfy the demands of state-of-the-art mixed-signal circuits. 
   Aspects of the present invention are disclosed in the following paper, which is hereby incorporated by reference in its entirety into the present disclosure: Jonathan Rosenfeld, Mucahit Kozak and E. G. Friedman, “A 0.8 volt high performance OTA using bulk-driven MOSFETs for low power mixed signal SOCs,”  Proceedings of the IEEE International SOC Conference , September 2003, pp. 245–246. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A preferred embodiment of the present invention will be set forth in detail with reference to the drawings, in which: 
       FIG. 1  is a circuit diagram showing an amplifier core of an OTA according to the preferred embodiment; 
       FIG. 2  is a circuit diagram showing a bias voltage generator circuit for use with the amplifier core of  FIG. 1 ; 
       FIG. 3  is a circuit diagram showing a low sensitivity reference current generator for use with the amplifier core of  FIG. 1 ; 
       FIG. 4  is a diagram showing the physical layout of the OTA of  FIG. 1 ; and 
       FIG. 5  is a plot of simulated open loop differential gain and phase as functions of frequency as plotted on a logarithmic scale. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   A preferred embodiment of the present invention will be set forth in detail with reference to the drawings, in which like reference numerals refer to like elements throughout. 
   The amplifier core  100  of an OTA is illustrated in  FIG. 1 . This circuit is based on a fully differential topology with two complementary input pairs  102 ,  104 . The output branch  106  includes common gate amplifiers M 7 , M 8  with cascode current loads  108 ,  110  to increase the gain. A common mode feedback circuit (CMFB)  112 ,  114  is used with four auxiliary common source amplifiers. The operation of the OTA is explained in greater detail below. 
   Rail-to-rail operation is achieved using a pair of PMOS ( 102 ; M 5  and M 6 ) and NMOS ( 104 ; M 33  and M 34 ) transistors at the input stage. This strategy supports rail-to-rail (0 volt to 0.8 volt) operation of the amplifier; thus, the input common mode range (ICMR) is extended to the largest possible range. This increased range is achieved because when the input common mode voltage is low, the P-type pair is on and the N-type pair is off, while when the input common mode is high, the P-type pair is off and the N-type pair is on. In the middle range, however, both pairs are on, providing a higher overall gain. 
   The output branch  106  of the OTA includes two symmetric common gate (CG) amplifiers (M 7  and M 8 ). Both amplifiers have cascode current loads ( 108 , including M 9  and M 13 ; and  110 , including M 10  and M 14 ) to increase the gain. The bias current is provided to M 7  and M 8  by the current sources M 3  and M 4 , respectively, which also operate as current loads for the P-type input pair (M 5  and M 6 ). Note that a complementary structure is also implemented for the N-type input pair. Transistors M 13  and M 14  act as current sources for the N-type input pair. 
   Auxiliary common source (CS) amplifiers ( 116 , including M 15 , M 16 , M 21 , and M 22 ; and  118 , including M 17 , M 18 , M 19 , and M 20  shown in  FIG. 1 ) provide a target open loop gain of at least 60 dB. In this way, stacking multiple transistors in the output branch is avoided, providing more overdrive voltage to maintain the transistors in the saturation region, while simultaneously increasing the voltage gain. The output of the CS amplifier is connected to the gate of the CG amplifier so as to maintain an almost constant source voltage. This source node is fed back as the input voltage to the CS amplifier. In this way, the local feedback action reduces the variations in the bias current when the source voltage of the CG amplifier changes, thereby increasing the output resistance. 
   The CMFB circuit ( 112 , including M 24 , M 25 , M 26 , and M 27 ; and  114 , including M 30 , M 31 , M 35 , and M 36  shown in  FIG. 1 ) is used to suppress the variations in the output common mode, particularly in applications with feedback. These variations occur due to mismatches among the transistors. These mismatches cause a difference between the DC operating voltages in the outputs (V out   +  and V out   − ). Furthermore, by forcing the output common mode to a specific level (normally halfway between V DD  and ground), the range of the input common mode is increased. 
   The CMFB circuit was first proposed in B. Razavi,  Design of Analog CMOS Integrated Circuits , New York: McGraw-Hill, 2001. In this configuration, transistors M 24 , M 25 , M 26 , and M 27  operate in the linear region, acting as voltage controlled resistors. When the DC operating point at the output differs from the target common mode voltage, a change in the tail current of the input pair occurs, resulting in an increment or decrement in the bias currents. This effect restores the DC operating point to the desired voltage level. 
   In order to ensure that the transistors operate in the saturation region (or in the linear region for some of the transistors in the CMFB circuit), fixed bias voltages are applied either to the gate or body of the transistors. The bias voltage generator circuit  200  is shown in  FIG. 2 . 
   Due to limited voltage headroom, simple voltage dividers are used to generate the bias voltages (V b1  through V b7  in  FIG. 1 ). Transistors M b6 , M b10 , and M b17  act as current mirrors for the transistor M b9 , providing the appropriate currents to generate voltages V b1 , V b5 , and V b6 . A complementary structure is also applied to generate voltages V b2 , V b3 , and V b4 . Transistor M b8  is the current mirror of M b7 , which is biased with a constant current source I ref  (1 μA). 
   A low-sensitivity reference current generator circuit  300  is illustrated in  FIG. 3 . Because the gate and source of M c4  and M c2  are common for both transistors, and the aspect ratios are equal, I Dc4 =I Dc2  (neglecting channel length modulation). Furthermore, note that V GSc3 =V GSc1 +I Dc1 R Sc1 . Thus, 
                         2   ·     I   Dc2           μ   n     ·     C   ox     ·       (     W   /   L     )     Mc3           =           2   ·     I   Dc2           μ   n     ·     C   ox     ·   K   ·       (     W   /   L     )     Mc3           +       I   Dc2     ·     R   Sc1           ,           (   1   )               
where K is the ratio between the aspect ratios of M c1  and M c3 . Rearranging this expression,
 
   
     
       
         
           
             
               
                 
                   I 
                   Dc2 
                 
                 = 
                 
                   
                     2 
                     
                       
                         μ 
                         n 
                       
                       · 
                       
                         C 
                         ox 
                       
                       · 
                       
                         
                           ( 
                           
                             W 
                             / 
                             L 
                           
                           ) 
                         
                         c3 
                       
                     
                   
                   · 
                   
                     1 
                     
                       R 
                       2 
                     
                   
                   · 
                   
                     
                       
                         ( 
                         
                           1 
                           - 
                           
                             1 
                             
                               K 
                             
                           
                         
                         ) 
                       
                       2 
                     
                     . 
                   
                 
               
             
             
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
   
   In the target circuit, K=1.6 and R=5 KΩ; therefore, I Dc2 =4 μA. As expected, the current is independent of the supply voltage (to a first order approximation). Transistor M c5  mirrors this current to generate a stable 1 μA reference current, which is used in the bias circuit as shown in  FIG. 2 . 
   The aspect ratios of each of the transistors used in the OTA core ( FIG. 1 ), the bias circuit ( FIG. 2 ) and the reference current generator ( FIG. 3 ) are listed in Tables 1, 2, and 3, respectively. 
   
     
       
             
           
             
             
             
             
             
             
           
             
             
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Aspect ratios of the transistors used in the amplifier core 
             
           
        
         
             
                 
               Transistor 
               Width 
                 
               Length 
               Ratio 
             
             
                 
                 
             
           
        
         
             
                 
               M 3 , M 4 , M 29   
               5.40 
               μm 
               360 nm 
               15.0 
             
             
                 
               M 5 , M 6   
               16.20 
               μm 
               360 nm 
               45.0 
             
             
                 
               M 7 , M 8   
               2.52 
               μm 
               360 nm 
               7.0 
             
             
                 
               M 9 , M 10   
               10.80 
               μm 
               360 nm 
               30.0 
             
             
                 
               M 13 , M 14   
               21.60 
               μm 
               360 nm 
               60.0 
             
             
                 
               M 15 , M 17 , M 19 , M 21   
               5.04 
               μm 
               360 nm 
               14.0 
             
             
                 
               M 16 , M 18 , M 20 , M 22   
               1.80 
               μm 
               360 nm 
               5.0 
             
             
                 
               M 24 , M 25 , M 26 , M 27   
               20.52 
               μm 
               360 nm 
               57.0 
             
             
                 
               M 23 , M 28   
               11.16 
               μm 
               360 nm 
               31.0 
             
             
                 
               M 30 , M 3 , M 35 , M 36   
               3.42 
               μm 
               360 nm 
               9.5 
             
             
                 
               M 3 , M 34   
               1.98 
               μm 
               360 nm 
               5.5 
             
             
                 
               M 32 , M 37   
               2.88 
               μm 
               360 nm 
               8.0 
             
             
                 
               M 38   
               18.36 
               μm 
               360 nm 
               51.0 
             
             
                 
                 
             
           
        
       
     
   
   
     
       
             
           
             
             
             
             
             
             
           
             
             
             
             
             
             
           
         
             
               TABLE 2 
             
           
           
             
                 
             
             
               Aspect ratios of the transistors used in the bias circuit 
             
           
        
         
             
                 
               Transistor 
               Width 
                 
               Length 
               Ratio 
             
             
                 
                 
             
           
        
         
             
                 
               M b1 , M b13   
               5.04 
               μm 
               360 nm 
               14.0 
             
             
                 
               M b3   
               10.08 
               μm 
               360 nm 
               28.0 
             
             
                 
               M b5 , M b22   
               2.88 
               μm 
               360 nm 
               8.0 
             
             
                 
               M b6   
               18.00 
               μm 
               360 nm 
               50.0 
             
             
                 
               M b7   
               0.40 
               μm 
               360 nm 
               1.1 
             
             
                 
               M b8   
               0.47 
               μm 
               360 nm 
               1.3 
             
             
                 
               M b9   
               1.73 
               μm 
               360 nm 
               4.8 
             
             
                 
               M b10   
               15.12 
               μm 
               360 nm 
               42.0 
             
             
                 
               M b12   
               1.80 
               μm 
               360 nm 
               5.0 
             
             
                 
               M b15   
               5.40 
               μm 
               360 nm 
               15.0 
             
             
                 
               M b17   
               9.43 
               μm 
               360 nm 
               26.2 
             
             
                 
               M b18   
               0.27 
               μm 
               360 nm 
               0.7 
             
             
                 
               M b21   
               7.02 
               μm 
               360 nm 
               19.5 
             
             
                 
                 
             
           
        
       
     
   
   
     
       
             
           
             
             
             
             
             
             
           
             
             
             
             
             
             
           
         
             
               TABLE 3 
             
           
           
             
                 
             
             
               Aspect ratios of reference current transistors 
             
           
        
         
             
                 
               Transistor 
               Width 
                 
               Length 
               Ratio 
             
             
                 
                 
             
           
        
         
             
                 
               M c1   
               5.52 
               μm 
               1380 nm 
               4.0 
             
             
                 
               M c3   
               3.80 
               μm 
               1520 nm 
               2.5 
             
             
                 
               M c2 , M c4   
               25.20 
               μm 
               1400 nm 
               18.0 
             
             
                 
               M c5   
               6.16 
               μm 
               1370 nm 
               4.5 
             
             
                 
                 
             
           
        
       
     
   
   The layout of the OTA including the bias circuit and current generator is illustrated in  FIG. 4 . A 0.18 μm CMOS twin-well TSMC process is used. Because both the PMOS and NMOS transistors are body biased, a twin-well technology is required in the bulk-driven technique. The double-well only marginally complication the manufacturing process. The use of a twin-well technology, however, is not a significant limitation for the bulk-driven method, since many advanced CMOS technologies use a two-well process, as reported in S. Yan and E. Sanchez-Sinencio, “Low Voltage Analog Circuit Design Techniques: A Tutorial,”  Institute of Electronics, Information and Communication Engineers Transaction on Analog Integrated Circuits and Systems , Vol. E00-A, pp. 1–17, February 2000. As shown in  FIG. 4 , interdigitization and common-centroid methods have been applied in the design of the OTA core so as to decrease mismatches among the transistors; that matter is described in R. J. Baker, H. W. Li, and D. E. Boyce,  CMOS Circuit Design, Layout, and Simulation , New York: IEEE Press, 1998. 
   The gain and phase responses of the OTA, which are obtained from post-layout simulations, are shown in  FIG. 5 . The OTA has an open-loop DC gain of 68 dB, a phase margin of 80°, and a unity-gain bandwidth of 93 MHz, under a no-load condition. For a capacitive load of 1 pF, the phase margin increases to 89°, while the unity-gain frequency reduces to 8.12 MHz. The OTA operates from a 0.8 volt single power supply and consumes 94 μW. The simulated ICMR and output swing are 800 mV and 700 mV, respectively. 
   While a preferred embodiment of the present invention has been set forth above in detail, those skilled in the art who have reviewed the present disclosure will readily appreciate that other embodiments can be realized within the scope of the present invention. For example, numerical values are illustrative rather than limiting, as are fabrication techniques. Therefore, the present invention should be construed as limited only by the appended claims.