Abstract:
An automatic gain control circuit having a coarse analog gain adjustment section producing discrete increments of db gain and a fine digital gain adjustment section. The digital section provides for adjustment of gain through a final increment of db gain to achieve precise gain setting. The output of the digital section is squared and compared to a reference signal to derive an error signal whose value is fed to an apparatus which iteratively determines the precise coarse increment and fine digital settings to achieve the final desired gain setting.

Description:
BACKGROUND OF THE INVENTION 
     The subject invention relates to automatic gain control (AGC) circuitry and, more particularly, to an AGC circuit having both analog and digital gain adjustment portions. The subject invention finds particular utility in digital data modem implementations. 
     In such modem implementations it would be desirable to utilize a coarse analog gain control section to bring the gain within the range of an anlog to digital converter circuit, while having a digital gain control circuit at the output of the analog to digital converter to provide a steady, precise digital level for the modem circuitry to utilize. However, provision of such an automatic gain control circuit has presented the problem of how to establish cooperation among simultaneously operative analog and digital gain control sections in order to achieve smooth and rapid progression to the gain level desired. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to improve automatic gain control circuitry. 
     It is another object of the invention to provide an automatic gain control circuit having both analog and digital sections. 
     It is yet another object of the invention to provide an automatic gain control circuit for use in a digital data modem providing cooperative, fast-attack, exponential adjustment of both digital and analog gain control sections. 
     According to the invention, an automatic gain control circuit is provided having an analog gain adjustment section and a digital gain adjustment section and means for producing first and second control signals which cooperate to adjust the gain provided by both the analog and digital sections to achieve the overall gain desired. An additional inventive feature of the subject invention is the provision of coarse incremental analog adjustment and a fine incremental adjustment over a continuous gain range around the desired gain together with first and second control signals adapted to cooperatively control the analog and digital sections. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The preferred embodiment and best mode contemplated for implementing the just summarized invention will now be described in detail together with the drawings of which: 
     FIG. 1 is a block diagram illustrating the preferred embodiment of the invention. 
     FIG. 2 is a functional circuit diagram illustrating the structure and operation of the control circuitry of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The automatic gain control circuit of the preferred embodiment is illustrated in FIG. 1. The preferred embodiment includes four gain sections 11. These gain sections 11 provide analog gain of 8A, 4A, 2A and A respectively where A=2.17 db. These analog sections 11 are switched in or out of the path of the coarse input signal by a four bit number stored in a register 13 to provide sixteen possible gain combinations. The four bit number comes from the gain control circuitry 15 to be described subsequently, (FIG. 2). The four analog sections 11 comprise the coarse AGC adjustment. The output of the coarse AGC is fed to an analog to digital converter 17. The output of the analog to digital converter 17 is multiplied by a factor fA in a multiplier 19, where f is in the range of -1 to +1. The multiplying factor fA is determined by a 10 bit digital word coming from the AGC control circuitry 15 to be described. 
     The control circuitry 15 for generating the four bit word for controlling the coarse AGC and the ten bit word for controlling the fine AGC is illustrated in FIG. 2. In FIG. 2, the output of the fine AGC circuit is squared by a squaring circuit 23 and fed to a first summer 29 where a reference level is subtracted. The squaring circuit 23 could optionally be a full wave rectifier. Optionally, the output of the squarer 23 can be delayed and averaged by circuitry including delay elements 25 and an averaging circuit 27, and the output 28 of the delay and average circuit can be fed to the first summer 29. The output of the first summer 29 represents an error signal. This error signal is fed to a multiplier 31 where the error signal is multiplied by an AGC speed control constant K. If the constant K is bigger, the speed of the AGC will be faster but more error will be incurred. Likewise if K is smaller, the speed of the AGC will be slower but less error will arise. Desirably, during initial acquisition, the constant K is relatively large, and during the steady state, it is made smaller. The output of the multiplier 31 is defined as &#34;a n .&#34; The subscript &#34;n&#34; indicates the sample time during which the variable to which it is appended is generated. This output a n  is fed to a summer 33 and summed with a quantity G n  to produce an output S n . 
     This output S n  is passed to a block 34 where two quantities, G n+1  and H n  are determined. The quantity G n+1  equals S n  -[S n  /C]·C and the quantity H n  =[S/C], the quantity C being a constant equal to 0.25 and the expression [S n  /C] defining the integer part of S n  divided by C. A quantity exp(-G n ) is then calculated and is the gain of the fine portion of the AGC, that is the 10 bit number in register 21 for the next sample. G n+1  is the remainder of dividing S n  by C and exp (0.25) equals 2.17 db. G n  is initially set to zero for n=0. 
     A summer 36 subtracts H n  from F n  to produce an output F n+1  which is the four bit number controlling the analog section during the next sampling time. F n  is initially=15 for n=0. The output F n+1  is delayed one sample time by a delay element 37 to produce an output F n  which is fed back as the second input to the summer 36. The output F n  of the delay element 37 is the number which adjusts the coarse analog portion of the AGC, that is the four bit number in register 13, during the current sample time. 
     Digital circuit elements for performing the functions of the elements shown FIG. 2 are well known in the art. The preferred embodiment is preferably implemented with a digital microprocesser, such implementation being well within the skill of one of ordinary skill in the art assisted by this disclosure. The operation of the control circuitry 15 may be illustrated by an example. 
     Given a desired AGC output level of 0.5, the reference level input to summer 29 is chosen as the square of the desired value or 0.25. Other initial conditions are K=1, F 0  =15 and G 0  =0), and an incoming signal level of 0.02. With these conditions, the first three iterations of values determined by the circuitry of FIG. 2 are summarized in the following Table I. 
     
                       TABLE I______________________________________  F.sub.n       G.sub.n    exp (-G.sub.n)                             AGC Output______________________________________n = 0    15     0.0         1       .9n = 1    13     .06        .94176   .50667n = 2    13     .06671     .93546   .50328______________________________________ 
    
     The example illustrates initial setting of the coarse adjustment with subsequent fine tuning of the digital portion of the AGC. With greater deviation from the desired value, more iterations may be required to initially set the coarse AGC and some alternations about the final value of the digital setting exp (-G n ) may occur. It may be noted that the exponential value exp (-G n ) may be approximated by a power series such as 1-G n  +(G n ) 2  /2 in block 39. 
     The above circuit provides several desirable features. The analog portion provides the necessary coarse adjustment to give the required resolution for operation of the analog to digital converter. At the same time, a steady level is produced at the output of the fine digital AGC circuit enabling associated modem circuitry to properly operate. The digital AGC portion is used to compensate for the rough nature of the analog portion. A key to the operation of the circuit is a synchronization which is accomplished between the digital and analog portions in order to give a steady output signal. In other words, adjustments cooperate to allow the analog and digital portions to appear to be acting like one AGC circuit. The operation in block 34 provides a 2.17 dB hysteresis effect such that in the steady state only the digital fine AGC is operative. The exponential feedback provides a fast attack to the AGC adjustment. 
     As will be apparent to those skilled in the art, many modifications and adaptations of the just described preferred embodiment may be made without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.