Abstract:
A circuit may generate a clock signal with a variable period given by a ratio between an initial switching period and a number of phase circuits through which a current of a multi-phase PWM voltage converter flows. The circuit may include an adjustable current generator driven by a signal representing the number of phase circuits through which the current flows and configured to generate a current proportional to the number of phase circuits through which the current flows, and a tank capacitor charged by the adjustable current generator. The circuit may include a comparator of a voltage on the tank capacitor with a threshold value configured to generate a pulse of the clock signal when the threshold value is attained, and a discharge path of the tank capacitor, the discharge path being enabled during the pulses of the clock signal.

Description:
RELATED APPLICATIONS 
     This application is a continuation of Ser. No. 12/797,212 filed Jun. 9, 2010, now U.S. Pat. No. 8,258,769 issued Sep. 4, 2012, the entire disclosure of which is hereby incorporated herein by reference. 
    
    
     FIELD OF THE DISCLOSURE 
     This present disclosure relates in general to voltage converters, and more particularly, to a method of switching a pulse width modulated (PWM) multi-phase voltage converter between multiple functioning conditions. 
     BACKGROUND 
       FIG. 1  depicts a block diagram of a typical buck converter with N phases and  FIG. 2  illustrates the yield of a four-phase buck converter, i.e. of the output current and of the number of active phases (PH). For this reason, multi-phase voltage converters are controlled to adapt the number of active phases to the external load conditions, by reducing or increasing the number of phases depending on the current being delivered by the converter. 
     A problem tied to the reduction of the number of functioning phase circuits is to reduce as much as possible the undershoot of the output voltage during these transitions. In order to understand what causes the undershoot of the output voltage, reference is made to  FIG. 3  that illustrates an exemplary transition from three active phases to one active phase circuit. I L1 , I L2  and I L3  represent the currents through the inductors, I OUT  represents the sum of the currents through the inductors (the dashed part indicates the ideal I OUT  during the transition), and I LOAD  represents the current used by the load and PS (Power Saving) a signal that enables the reduction of the number of active phase circuits. 
     As far as PS=0, the output sum current I OUT  has an “updating” frequency equal to N*F SW , wherein F SW  represents the switching frequency of the single stage and N represents the number of phases of the system. In particular, during each I OUT  cycle, equal to T SW /N, wherein T SW  is the switching period of a single phase circuit, it is possible to identify a charge time during which there is always at least a phase circuit that is on and the other phase circuits are off, and a discharge time during which the other two phase circuits are off. When PS=1 (instant t 0 ), the phase circuits that may be turned off could be driven with a null duty-cycle (the low side MOS is on), as far as the respective phase currents cancel out (instants t 2  and t 3 , respectively). 
     During the interval t 0 -t 2 , when the phase current I L3  is canceled and the phase current IL 1  is not yet in a steady-state condition, the equivalent switching frequency F EQ  on the output current I OUT  reduces (in this case F EQ =3*F SW ) compared to the frequency that was present when the signal PS was logically low. This results in a drop of the equivalent output current I OUT  compared to that requested by the load I LOAD . The area Q T  represents the charge lost by the output filter C OUT  during the transition that causes the voltage drop, which may depend on the output capacitance being used. 
     During the interval t 2 -t 3 , when the phase current IL 2  is canceled out, the nominal equivalent switching frequency of a converter with two active phases and one phase off, i.e. F EQ =2*F SW , is not attained, thus causing a further charge loss on the output filter. When the phase current IL 2  becomes null (instant t 3 ), the equivalent frequency is F SW , i.e. the frequency of a converter with a single active phase circuit (mono-phase). The consequent drop of the output voltage becomes more relevant and the converter may compensate it in a slower or faster way depending on the bandwidth of the single phase circuit. 
     It may be important to eliminate, or at least limit, the output voltage undershoot during those transitions for not disturbing the functioning of the voltage control loop of the converter that intervenes for compensating the disruption. The greater the load current during the transition, the larger the current drop I OUT .  FIG. 4  illustrates a transition from three phases to one phase in low load conditions. Differently from the example of  FIG. 3 , the lost charge Q T  during the transition is smaller than in the previous case because the currents through the phase circuits to be turned off are almost null. 
     Sometimes, for simplifying the design, the phases to be turned off are set to a high impedance state as soon as PS=1. In this case, the currents are discharged with a larger slew rate because the free-wheeling diode of the low side MOS of the phase is turned on. As a result, additional charge is lost from the output filter capacitance, as shown in  FIG. 5 , wherein the dashed parts indicate the transition shown in  FIG. 3 , with the low side MOS turned on. This approach, besides generating a large undershoot of the output voltage, causes a loss of efficiency of the converter under medium load conditions and in case of switching to and resuming from a power saving mode because, while turning off the phases, the free-wheeling diodes of low side MOS switch on, thus dissipating power. 
     According to another typical technique, illustrated in  FIG. 3 , the low side MOS of the phases to be turned off is kept on until the current nullifies or reaches a pre-established threshold. This approach may be better than the previous one from the point of view of power dissipation, but implies a significant drop of the output voltage. A feedback voltage converter, a block diagram of which is depicted in  FIG. 6 , is illustrated in the published U.S. Patent Application Publication No. 2008/0272752 to Qiu et al.  FIG. 7  illustrates an exemplary time diagram of the converter of  FIG. 6  in the case in which six phase circuits are present. The signal PSI# is the logic switching signal, P 1 , P 2 , . . . , P 6  are the enabling signals of the respective phase circuits. In the last figure, there are two extra pulses that are added in correspondence of the enable pulse of the phase circuit  4  to sustain the output and to speed up the phase dropping transient. The equivalent frequency of the converter during the transition is twice the nominal frequency of the phase current IL 1  when the phase current IL 2  is not null as well as when the phase circuit is in a high impedance state with a null current (the phase circuit IL 2  is off). 
       FIG. 8  illustrates a transition from six active phase circuits to two active phase circuits with a single pulse addition for each phase circuit. As shown, the two active phase circuits are not outphased by 180 degrees as it would be desirable in a two-phase converter. In the simulation illustrated in  FIG. 9  of a three phase system, only a pulse is added because the output current is already low. The above-discussed prior patent publication is silent about the criterion used for determining the number of pulses to be added. 
     SUMMARY OF THE DISCLOSURE 
     An advantageous method of switching a multi-phase PWM converter from a functioning condition in which all N phase circuits are active to a functioning condition in which only m phase circuits are active and the other N-m phase circuits are deactivated has been found. 
     With the method, transition between the two functioning modes may be effected by leaving unchanged the equivalent frequency of the converter while letting the phase currents of the m phase circuits that remain active be uniformly outphased between them. 
     This ideal condition of the converter may be achieved by adaptively making the switching period of the active phase circuits correspond to the product between the number m of phase circuits that remain active and the ratio between the initial switching period and the number of phase circuits during which a current flows, thus correspondingly reducing the respective off time, and then updating the switching period of the m phase circuits that remain active as the N-m phase circuits are switched off. 
     The updating of the switching period may be implemented by a circuit adapted to generate a clock signal of variable period. The circuit may comprise an adjustable current generator driven by a signal representing the number of phase circuit through which a current flows, adapted to generate a current proportional to this number, a tank capacitor charged by the adjustable current generator, and a comparator of the voltage on the tank capacitor with a threshold value, adapted to generate a pulse of the clock signal when the threshold value is attained. The circuit may further comprise a discharge path of the tank capacitor that is enabled during pulses of the clock signal. It is further disclosed a multi-phase PWM voltage converter that implements the herein disclosed method. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a buck multi-phase PWM voltage converter, according to the prior art. 
         FIG. 2  is an exemplary graph of the yield of the converter of  FIG. 1  in function of the load supplied current I LOAD  of the number of PH active phases. 
         FIG. 3  is a graph of the main signals of the converter of  FIG. 1  in the case of switching from three active phase circuits to a single active phase circuit with high load using a prior art technique. 
         FIG. 4  is another graph of the main signals of the converter of  FIG. 1  in the case of switching from three active phase circuits to a single active phase circuit in low load conditions using a prior art technique. 
         FIG. 5  is a graph of the main signals of the converter of  FIG. 1  in the case of switching from three active phase circuits to a single active phase circuit in high load condition using a prior art technique. 
         FIG. 6  depicts a voltage regulator disclosed in the published U.S. Patent Application Publication No. 2008/0272752. 
         FIG. 7  is a time graph of the main signals of the regulator of  FIG. 6  in the case of switching from a functioning condition in which only a phase circuit is active. 
         FIG. 8  is a time graph of the main signals of the regulator of  FIG. 6  in the case of switching from a functioning condition in which two phase circuits are active. 
         FIG. 9  is a time graph of the main signals of the three-phase voltage regulator of  FIG. 6  in the case of switching from a functioning condition in which only a phase circuit is active, in which the addition of an extra driving pulse is highlighted when all the phase circuits are active. 
         FIG. 10  is a graph of the waveforms of the phase currents in a three-phase converter switched according to the method of the present disclosure in high load conditions. 
         FIG. 11  is a graph of the waveforms of the phase currents in a three-phase converter switched according to the method, according to the present disclosure, in low load conditions. 
         FIG. 12  is a time graph of the waveforms of the phase currents in a two-phase converter switched according to the method of the present disclosure. 
         FIG. 13  illustrates a circuit for generating a clock signal with a variable period determined by the number of active phases in a multi-phase converter, according to the present disclosure. 
         FIG. 14  is a time diagram that illustrates the relationships among the main signals of the circuit of  FIG. 13  and the typical ramp signals used for generating the driving signals of the phase circuits of a three-phase PWM voltage converter. 
         FIG. 15  illustrates in detail how the signal MAIN_RAMP of the circuit of  FIG. 13  varies when a phase circuit of the converter is turned off (ZC event). 
         FIG. 16  is a graph of the waveforms of the phase currents in a four phase converter switched according to the method, according to the present disclosure, wherein at the same time the duty-cycle of three phase circuits to be turned off are nullified. 
         FIG. 17  is an exemplary time graph of the waveforms of the phase currents in a four-phase converter switched according to the method, according to the present disclosure, wherein the duty-cycles of three phase circuits to be turned off are sequentially nullified one at the time. 
         FIG. 18  depicts waveforms obtained through simulation of a switching from three to two active phase circuits carried out according to the method, according to the present disclosure. 
         FIG. 19  depicts waveforms obtained through simulation of a switching from two active phase circuits to a single on phase circuit carried out according to the method, according to the present disclosure. 
         FIG. 20  is an exemplary block diagram of a multi-phase PWM buck voltage converter having a control circuit that generates clock signals with a variable period and drives the progressive switching off of the phase circuits of the converter, according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In order to better illustrate the disclosed embodiments, reference may be made to the case of an N-phase voltage converter that switches from a functioning condition with N active phase circuits to another functioning condition in which only one phase circuit is on. Successively, a way of generalizing the proposed method to the switching of N active phase circuits to in active phase circuits may be shown. 
     In a N-phase voltage converter, when switching from a functioning condition with N on phase circuits to a functioning condition with a single active phase circuit, the current through the active phase circuit may increase from I OUT /N to I OUT , being I OUT  the current to be delivered, with an increment of (N−1)*I OUT /N. During this transition phase, it may be necessary to reduce system perturbation to a minimum. Normally, at each interval of duration T SW /N (being T SW  the switching period of the PWM driving signals), only a phase circuit at the time is energized. 
     When a phase circuit is to be turned off, the duty-cycle of the respective PWM driving signal is nullified thus leaving on the respective low side MOS. While the phase circuits are turned off and when none of the phase currents has attained a turn-off level below which the phase circuit may be turned off, it is advisable to keep the same switching frequency of the converter and the same equivalent on time T ON  for not reducing the output current. For this reason, according to the method, the phase circuit  1  to be left active is driven with a switching frequency and a gain N times larger. 
     When a first phase current drops down to the turn-off level, that for example could be the zero current, the related phase circuit may be turned off. The number of phase circuits that are still active is reduced and the equivalent frequency and gain of the converter are reduced down to the values that they would have in an N−1 phase converter. Thus, the phase circuit  1  is driven with a frequency and a gain N−1 times larger than the nominal values of the phase circuit. 
     When another phase current decreases down to the off level, the related phase circuit is turned off. The phase circuits off that do not contribute anymore to the output current are two, and thus according to the method the phase circuit  1  is driven with a frequency and a gain N−2 times the nominal values of the phase circuit. This procedure is repeated until all N−1 phase circuits to be turned off are inactive. In this case, the sole non-null phase current may be that of the phase circuit  1 , that may be driven with a switching frequency and a gain equal to the nominal values. 
       FIG. 10  illustrates the just described turn off procedure for a three-phase converter two phase circuits of which are to be turned off and only one phase circuit is to be left active. From the instant t 0 , when the signal PS switches high, the phase circuits  2  and  3  may be driven with a null duty cycle (that is the respective low side MOS remain on) as far as the respective phase currents do not attain the turn off level that, in the case exemplified in the figure, is the zero current. In the instants t 5  and t 6 , respectively, the phase circuit  2  and the phase circuit  3  are set in a high impedance state. 
     From the instant t 0  to the instant t 5 , the phase circuit  1  is driven with a frequency three times larger than the nominal switching frequency of the phase circuit and a triple gain, in order to sustain the output voltage without modifying the on time T ON . From the instant t 5  onwards, the phase circuit  2  may not give any contribution to the total output current, thus in the time interval from t 5  to t 6  the phase circuit  1  may be driven with a frequency and gain equal to those of a two-phase converter. From the instant t 6  onwards also, the phase circuit  3  may be off and the phase circuit  1  may be driven with its nominal frequency and gain. 
       FIG. 11  shows another example in which the current used by the load is relatively low. In this case, the duration of the transition is reduced. In order to better understand what happens with the method when a phase circuit is switched off, let us consider a two-phase converter and the transition illustrated in  FIG. 13  from 2 on phase circuits to a single active phase circuit. 
     Before the signal PS switches high, thus driving the nullification of the duty cycle of the phase to be turned off, the equivalent switching frequency of the converter is 2*F SW , wherein F SW  is the nominal switching frequency of a single phase circuit and the equivalent gain of the converter is 2*G PWM  wherein G PWM  is the nominal PWM modulation gain of a single phase circuit. 
     When the signal PS switches high, the duty-cycle of the phase circuit  2  nullifies (the low side MOS is on) until its phase current becomes null, or until the turn off level is attained. In this time interval from the instant t 1  to the instant t 4 , the phase circuit  1  may have a switching frequency and PWM gain double than the nominal values. By respecting this condition, in practice there is no voltage drop on the total output current (Iout) and thus of the output voltage. 
     In the period t 5 , when the current through the phase circuit  2  attains the turn off level of the phase circuit, the total output current in the discharge portion may comprise the contributions of the phase currents  1  and  2 , in the time interval T X , and by the contribution of the sole phase current  1  in the remaining time interval. The current varies with a different slope, thus for sustaining the minimum level of delivered current and thus preventing excessive drop on the output voltage, the portion t 5  may necessarily last longer than the previous portions, such as, for example, of the portion t 4 . In order to calculate by how much t 5  should last longer than t 4 , it is sufficient to equal the respective ripple amplitudes of the output current, called ΔI 1  for the period t 4  and ΔI 2  for the period t 5 . 
     For a two-phase system, the following equations hold: 
                     Δ   ⁢           ⁢     I   1       =     2   ⁢       V   OUT     L     ⁢     (         T   SW     2     -     DT   SW       )                     Δ   ⁢           ⁢     I   2       =       2   ⁢       V   OUT     L     ⁢     (       T   X     -     DT   SW       )       +         V   OUT     L     ⁢     (         T   SW     2     -     T   X     +     Δ   ⁢           ⁢   T       )                     
in which V OUT  represents the regulated output voltage, L the value of the inductance in a phase circuit, D the duty-cycle, T SW  the nominal switching period of a single phase circuit, and T X  and ΔT the time intervals represented in  FIG. 12 .
 
     In order to not reduce the output voltage, it should be that ΔI 1 =ΔI 2  holds, thus: 
                 T   SW     ⁡     (     1   -     2   ⁢           ⁢   D       )       =       2   ⁢           ⁢     T   X       -     2   ⁢           ⁢     DT   SW       +     (         T   SW     2     -     T   X     +     Δ   ⁢           ⁢   T       )             
from which:
 
     
       
         
           
             
               Δ 
               ⁢ 
               
                   
               
               ⁢ 
               T 
             
             = 
             
               
                 
                   T 
                   SW 
                 
                 2 
               
               - 
               
                 T 
                 X 
               
             
           
         
       
     
     The time to be added to the last period of the transition (t 5 ) is independent from the value of the inductances, of the voltage and of the output duty-cycle of the converter, but depends only on the nominal switching frequency, on the number of phase circuits and on the time T X  used by the phase current to reach the turn off level (that in the shown example is 0 A). In general, it is possible to say that in a N-phase converter, the variation of the last period of the transition from N to N−1 phases is: 
               Δ   ⁢           ⁢   T     =         1     N   ⁡     (     N   -   1     )         ⁢     T   SW       -       1     N   -   1       ⁢     T   X               
This time may be defined by generating a clock signal with a variable period to be used to reset the PWM ramps used for generating the PWM driving signals of the phases to be left active.
 
       FIG. 13  illustrates a main diagram of a circuit for generating a clock signal with a variable period to be used as a main oscillator of the voltage converter, having a frequency N*F SW  wherein N represents the number of active phase circuits. In this scheme, the currents I L2 , . . . , I LN  are the currents through the phase circuits of the converter; this figure depicts also the zero-cross detection circuits of the currents (ZC DETECTOR), the block for managing the interleaving, the frequency and the number of phase circuits (PHASE MANAGEMENT), the current generator of the ramp of the main oscillator, a tank capacitor on which a voltage ramp is produced, a comparator of the voltage on the capacitor with a threshold V TH     —     OSC , and a circuit SR_CIRCUIT for generating clock pulses CK_MAIN, that is the main clock of the converter. From this clock signal, the timing signals interleaving between PWM driving signals of the single phase circuits may be generated. 
     For sake of illustration and providing an example,  FIG. 14  illustrates how the clock signal CK_MAIN could be used for obtaining four PWM ramps useful for generating four uniformly outphased PWM driving signals of a four-phase voltage converter. The turn on sequence of the phase circuits could also be different from that depicted in figure, and the type of PWM ramp (in this case a saw-tooth) could be different from the illustrated one. 
     By generating the main ramp (MAIN_RAMP) using a current proportional to the number of active phases, a situation as that depicted in  FIG. 15  occurs. The intervals T X  and ΔT have already been described, dV/dt represents the slope of the ramp MAIN_RAMP when all the phase circuits but one are driven with a null duty-cycle, N represents the number of total phase circuits of the system and ZC is the instant at which a current of the phase circuit to be turned off reaches the turn off level. The following equations hold: 
               V   TH_OSC     =     N   ⁢       ⅆ   V       ⅆ   t       ⁢       T   SW     N                     from   ⁢           ⁢   which   ⁢           ⁢     V   TH_OSC       =       N   ⁢       ⅆ   V       ⅆ   t       ⁢     T   X       +       (     N   -   1     )     ⁢       ⅆ   V       ⅆ   t       ⁢     (         T   SW     N     -     T   X     +     Δ   ⁢           ⁢   T       )                       and   ⁢           ⁢   thus   ⁢           ⁢     T   SW       =       NT   X     +       (     N   -   1     )     ⁢     (         T   SW     N     -     T   X     +     Δ   ⁢           ⁢   T       )                       Δ   ⁢           ⁢   T     =         1     N   ⁡     (     N   -   1     )         ⁢     T   SW       -       1     N   -   1       ⁢     T   X               
The obtained ΔT value is the same that has been previously calculated for theoretically eliminating the output voltage drop.
 
       FIG. 16  illustrates how to turn off three phase circuits of a four phases voltage converter according to the method of the disclosure and how the clock signal with a variable period MAIN_RAMP is modified. When the signal PS switches high at the instant t 0 , the phase circuits  2 ,  3  and  4  are driven with a null duty cycle and their phase currents diminish. In the interval from t 0  to t 1 , since at each clock cycle there are still 4 phase circuits that contribute to the overall output current, the phase circuit  1  should be driven at a frequency and gain 4 times larger that the nominal values. By supposing constant the slope of the ramp PWM_RAMP used for generating the respective PWM driving signals, the gain increase is obtained simply by resetting the relative ramp to the phase circuit  1  at a larger frequency, in this case 4 times larger, thus keeping constant the relative turn on time. 
     At the instant t 1 , the phase circuit  2  is set in a high impedance state and the relative zero-crossing signal ZC 2  switches high. The active phase circuits are three, i.e. the circuits  1 ,  3  and  4 . When the zero-crossing signal ZC 2  of the phase circuit  2  switches high, the slope of the main ramp MAIN_RAMP varies as shown in the figure. At the instant t 2  also, the signal ZC 3  switches high and the active phase circuits become 2 in number, that is the phase circuits  1  and  4 . In the interval from t 2  to t 3 , the frequency of the phase  1  should become twice the nominal frequency, but, because of the assertion of the zero-crossing signal ZC 4  of the phase circuit  4 , the period of the ramp of the main clock MAIN_RAMP is altered. From the instant t 3  onwards, the sole active phase circuit is the phase circuit  1 . In the interval from t 3  to t 4 , the system prolongs the times adaptively, and from t 4  onwards, the converter works with a single active phase circuit driven with a frequency and a gain equal to the nominal values. 
     The method may be generalized for carrying out transitions from a functioning condition with N active phase circuits to a functioning condition with only m active phase circuits. At the instant in which a transition command is given, the duty cycle of the driving signals of the phase circuits to be turned off is nullified and the turn off time of the driving signals of the phase circuits to be left active is reduced, such that the relative switching period be in times the original switching period divided by the number of phase circuits in which a current flows. As the phase circuits are turned off, the switching period is updated. It is to be noticed that the generator of  FIG. 13  is adapted to generate a clock signal CK_MAIN for implementing this transition. 
     By using the proposed method, relatively fast transitions are executed. In some applications, this could be unacceptable because the increment of the switching frequency of the driving signal of the phase circuit to be left active could be excessive and could imply stresses of the power components or could lead to saturation of the control variable of the system because of the too large gain. 
     In order to obviate to this eventual limit, it is possible to carry out a smooth transition by turning off one phase circuit at the time, as shown in  FIG. 17  in which a transition from four to one on phase circuits is illustrated. In view of the above considerations, the graph of  FIG. 17  may appear immediately self-explaining to any skilled person. 
     By carrying out the transition in this way, the frequency and the gain of the phase circuit  1  is limited to twice the nominal value and only for a short transition interval. Moreover, during transitions, the interleaving between the active phases is ensured such to reduce the input current (ms) and the switching noise of the whole system.  FIGS. 18 and 19  show simulation results of a transition from three to two active phase circuits and from two to one active phase circuit, respectively. The output voltage drop Vout is not null because of parasitic components and second order effects, but it is negligible. 
       FIG. 20  is a block diagram of a voltage regulator having the circuit ADAPTIVE PHASE DROPPING that implements the method. CK 1 , . . . , CK N  represent the reset signals of the respective ramps; PH 2   ON , . . . , PHN ON  represent the signals for commanding the turning off (setting in a high impedance state) of the respective phase; ZC 2 , . . . , ZC N  represent the zero-crossing signals of the currents of the respective phases; and PS represents the power saving logic signal with which the beginning of a transition is commanded.