Abstract:
A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This patent application claims priority to Japanese patent application No. 2004-206740 filed on Jul. 14, 2004 in the Japan Patent Office, the entire content of which is incorporated by reference herein. 
   FIELD OF THE INVENTION 
   The present invention relates to a method and apparatus for simulating a logic circuit, and more particularly to a method and apparatus for simulating a logic circuit that includes a circuit block to which power is not supplied. 
   BACKGROUND OF THE INVENTION 
   In recent years, power reduction technology for logic IC (integrated circuit) has been studied and developed. To get a low power consumption IC, a circuit configuration to which power is selectively supplied to circuit blocks has been employed. More specifically, power is supplied to the circuit blocks which need power to perform a task and not supplied to other circuit blocks which do not perform the task. 
   However, conventional logic simulators request a circuit description which represents every circuit block of the logic circuit operating under the supply of power. Therefore, the conventional logic simulators cannot handle the circuit description for a logic circuit to which power is selectively supplied to circuit blocks of the logic circuit and described with cell descriptions retrieved from cell libraries for IC design using commercial CAD tools. In order to simulate the circuit configuration using the conventional simulator, the logic circuit is required to be classified into small circuit blocks, for example, a power supply circuit block and logic circuit blocks, and each circuit block is needed to be simulated separately under different conditions. Then, all executed simulation results are collected to consider a total power consumption of the IC circuit. When the conventional simulator is used for design verification, additional manual labor may be needed to adjust connections between the circuit blocks and functional simulations are needed to perform for the individual circuit block. Consequently, it become very complicated to get the total simulation result and a lot of additional efforts are needed. 
   There has been proposed one technique which recreates a cell library by adding power terminals to all cells. However, it requires a lot of additional work to prepare new cells manually and maintain the additional new cell library besides the cell library which is commonly used for the IC design. Moreover, the processes used to add terminals to the cells and to connect the circuit blocks are not able to be implemented in RTL (register transfer level) design methodology, which is commonly used in IC design, but are instead only implemented in a gate level design methodology. 
   BRIEF SUMMARY OF THE INVENTION 
   The invention provides a novel logic circuit simulation apparatus used in designing Logic ICs. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit. 
   The invention also provides a novel logic circuit simulation apparatus which includes a delay time specifying unit which specifies a power-off delay time for the circuit block to which power is not to be supplied and specifies the power-on delay time for the circuit block to which power is to be supplied. 
   The invention further provides a novel logic circuit simulation method which has steps of creating power control signal information for specifying statuses of a plurality of power control signals, specifying delay time from a time the power control signal is changed to a time the power of the circuit block is not supplied for each circuit block, reading the power control signal information, the circuit connection information and the delay time information, generating logic circuit simulation control information based on the power control signal information, the circuit connection information and the delay time information, reading the logic circuit simulation control information for instructing a logic circuit simulation unit to fix with high impedance each input of a circuit block to which power is not supplied and simulating the logic circuit in accordance with the logic circuit simulation control information. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
       FIG. 1  illustrates a logic circuit simulation apparatus according to an embodiment of the present invention; 
       FIG. 2  illustrates an example logic circuit to be simulated by the logic circuit simulation apparatus; 
       FIG. 3  illustrates another example logic circuit; 
       FIG. 4  illustrates another example logic circuit; and 
       FIG. 5  illustrates an example description describing an operation of a buffer element circuit. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In describing preferred embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner. Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, particularly to  FIGS. 1 and 2 , a logic circuit simulation apparatus according to an embodiment of the present invention and an example logic circuit to be simulated by the logic circuit simulation apparatus is now described.  FIG. 1  illustrates the logic circuit simulation apparatus and  FIG. 2  illustrates an example logic circuit  20  which uses multiple powers and is simulated by the logic circuit simulation apparatus of  FIG. 1 . 
   In  FIG. 2 , the logic circuit  20  includes a logic circuit block A  220 , a logic circuit block B  230  and a power control circuit block C  240 . The power control circuit provides powers  21  and  22 . Power  21  is a power output from the power control circuit block C  240  and is controlled by an output of a flip flop  204  in the power control circuit block C  240 . Power  21  is supplied to a flip flop  200  in the logic circuit block A  220 . Power  22  is another power output from the power control circuit block C  240  and is controlled by the output of a flip flop  207  in the power control circuit block C  240 . Power  22  is supplied to a flip flop  209  in the logic circuit block B  230 . The flip flop  204  controls a switching transistor Ti by outputting a signal at node  202 . The signal at node  202  is called SIGA and is defined as a power control signal. The flip flop  207  controls a switching transistor T 2  by outputting a signal at node  203 . The signal at node  203  is called SIGB and is also defined as a power control signal. 
   In order to make the flip flop  200  reset, power  21  is needed to be turned on in advance. Namely, the flip flop  204  is needed to be set in advance to make power  21  active. If the power  21  is off in an initial state, node  201  is in a floating state. The flip flop  200  cannot properly be reset under the floating condition of power, even if a set signal R 1  at node  205  become logical “0” by an output of the flip flop  209  in logic circuit block B  230 . In this case, the output at node  206  of the flip flop  200  may not be predictable and the value may be logical “0” or logical “1”. 
   The logic circuit simulation apparatus in  FIG. 1  includes a power control signal specifying unit  1 , a power delay time specifying unit  10 , a logic circuit simulation control information generation unit  3 , a logic circuit simulation unit  8  (logic simulator) and various information files. The information files include a power control signal information file  2 , a power delay time information file  11 , a circuit connection information file  4 , a test pattern information file  5 , a cell library information file  6 , a logic circuit simulation information control file  7  and a logic circuit simulation result file  9 . Descriptions  12  and  13  are examples of the power control signal information file  2  and the power delay time information file  11 , respectively. Descriptions  14 ,  15 ,  16  and  17  are example statements of forcing values and releasing values to instruct the logic circuit simulation unit  8 . 
   According to a first embodiment, the power control signal specifying unit  1  specifies a signal which stops or starts to supply power and generates power control signal information. In  FIG. 2 , the signal SIGA at node  202  is an example of a power control signal. The description  12  in  FIG. 1  is an example of the power control signal information file  2 . The logic circuit blocks A and B,  220  and  230 , and the power control signals SIGA and SIGB are referred in the description of the power control signal information  12 . The description of the power control signal information  12  describes that the power to the logic circuit block A  220  is controlled by the power control signal SIGA. Moreover, the power is supplied when the power control signal SIGA is logical “1” and not supplied when power control signal SIGA is logical “0”. The specification of the power control signal can be implemented by the commercial CAD software tool, or manually. The logic circuit simulation control information generation unit  3  reads the circuit connection file  4  and the power control signal information file  2 , then generates a logic circuit simulation control information file  7 . The description  15  in  FIG. 1  shows an example of logic circuit simulation control information which is written by standard CAD language Verilog-HDL (hardware description language). The description  15  describes an instruction that command is sent to the logic simulator to fix with logical “Z” the input ports of logic circuit block A  220 , i 1  and i 2 , when the logical value of the power control signal SIGA is changed from 1 to 0. The information on the input ports i 1  and i 2  is retrieved from the circuit connection information file  4 . When the input ports i 1  and i 2  of the logic circuit block A  220  are fixed to a logical value of “Z”, the values at the input ports i 1  and i 2  of the logic circuit lock A  220  are kept as logical “Z” during the simulation even if a signal of logical “1” or logical “0” is fed from the logic circuit block B  230  to the input ports i 1  and i 2  of the logic circuit block A  220 . 
   When logical “Z” is inputted to a cell of the cell library, the cell outputs logical “X” in general. The logical “X” expresses an unfixed value which may not be logical “1” or logical “0”. This situation corresponds to the actual circuit operation to which power is not supplied. If every input of the block A is fixed to logical “Z”, logical “X” is transmitted in the block A. Therefore, it is possible to simulate the circuit including the circuit block to which power is not supplied by applying logical “Z” to the inputs of the circuit block. It is also possible to fix every output of the logic circuit block A  220  with logical “Z” in addition to the fixation of every input with logical “Z”. The logic circuit simulation unit  8  performs the simulation after reading the circuit connection information file  4 , the test pattern information file  5  and the cell library information file  6  which are commonly used in the background logic simulation and the logic circuit simulation information control file  7 . Namely, the equivalent simulation result to the actual circuit operation with no power supply to the logic circuit block A  220  can be obtained using this procedure. 
   A second embodiment introduces a power delay time specifying unit  10 . The power delay time specifying unit  10  is an additional element of the logic circuit simulation apparatus and generates the power delay time information file  11  which specifies a power delay time. The power delay time is defined as a time period from a time power control signal becomes active (logical “1”) to a time the power is supplied to the circuit block. For example, it is the power delay time from a time the power control signal SIGA becomes logical “1” to a time the power  21  goes up to a predetermined high potential. The power delay time is also defined as a time period from a time power control signal becomes non-active (logical “0”) to a time the power is stopped to supply to the circuit block. For example, it is the delay time from a time the power control signal SIGA becomes logical “0” to a time power  21  goes down to a predetermined low potential. The description  13  in  FIG. 1  is an example of the power delay time information. The description  13  describes that power  21  at node  201  goes up to the predetermined high potential upon an elapse of a time value of 10 after the power control signal SIGA becomes logical “1” and power  21  at node  201  goes down to the predetermined low potential upon an elapse of a time value of 5 after SIGA becomes logical “0”. The logic circuit simulation control information generation unit  3  reads the power control signal information file  2 , the circuit connection file  4  and the power delay time information file  11 , and accordingly generates a logic circuit simulation information control file  7 . The description  14  in  FIG. 1  is an example of the logic circuit simulation control information written by standard language Verilog-HDL. The description  14  describes that the input ports i 1  and i 2  of the logic circuit block A  220  are to be set logical “Z” upon an elapse of a time value of time 5 after SIGA is changed from logical “1” to logical “0”. The input ports i 1  and i 2  are retrieved from the circuit connection file  4 . The logic circuit simulation unit  8  performs the simulation using the circuit connection information file  4 , the test pattern information file  5  and the cell library information file  6  which are commonly used in the background logic simulation and the logic circuit simulation information control file  7 . Namely, the simulation result with the delay time equivalent to the actual case where the power is not supplied to the logic circuit block A  220  can be obtained using this procedure. 
   A third embodiment covers a situation where the power is supplied again to the circuit block which consequently begins to work. The logic circuit simulation control information with release condition is generated as shown in the description  16  in  FIG. 1 . The description  16  describes that each of the input ports i 1  and i 2  of the logic circuit block A  220  is released by an application of a fixed input value when SIGA is changed from logical “0” to logical “1”. The circuit block to which power is supplied again is now simulated in a procedure similar to the background method. Accordingly, the logic circuit operation to which the power is supplied again to the circuit block which consequently begins to work can be simulated. 
   A fourth embodiment covers a situation where the power is supplied again to the circuit block which consequently begins to work after a delay. The logic circuit simulation control information with release conditions including a delay time is generated as shown in the description  17  in  FIG. 1 . The description  17  means that each of the input ports i 1  and i 2  of the logic circuit block A  220  is released by an application of a fixed value upon an elapse of the time value of 10 after the power control signal SIGA is changed from logical “0” to logical “1”. The circuit block to which power is going to be supplied is now able to be simulated in a way similar to the background method. Accordingly, a logic circuit in which the power is supplied again to the circuit block which consequently begins to work can be simulated with consideration of delay time. 
     FIG. 3  illustrates another example of logic circuit  30  using multi-power suppliers to demonstrate fifth embodiment. The logic circuit  30  includes another logic circuit block E  330  and the power control circuit block D  350  supplies third power  33  in addition to powers  31  and  32 . When logical “Z” is inputted to the input terminal i 1  using one of commercial CAD software tools, logical “Z” may be inputted to the input terminal i 2  unintentionally because of the existence of a common line, i.e., a net N 1 . In order to avoid such erroneous input of logical “Z”, an input buffer  501  is provided to each one of the circuit blocks.  FIG. 4  illustrates an example of a logic circuit in which the input buffer  501  is arranged in the logic circuit block A  420 . By thus introducing the buffers, such as buffer  501  shown in  FIG. 4 , the output of buffer at node  502  becomes able to be set logical “Z”. An arrangement of the buffer in each one of the circuit blocks may be performed with the commercial CAD software tool. It is possible to place buffers outside of the circuit blocks instead of placing buffers inside of the circuit blocks.  FIG. 5  shows an example of the description of the buffer circuit operation. 
   Numerous additional modifications and variations are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the disclosure of this patent specification may be practiced otherwise than as specifically described herein.