Abstract:
A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

Description:
This invention was made with government support under Contract No. W-31-109-ENG-38 awarded to the Department of Energy. The Government has certain rights in this invention. 
    
    
     FIELD OF THE INVENTION 
     This invention relates generally to voltage controlled devices for logic applications. More particularly, this invention relates to voltage controlled rotation devices coupled to tunneling magneto-resistance devices. 
     BACKGROUND OF THE INVENTION 
     Logic gates incorporated into devices such as microprocessors are well known in the computer and electronics industries. Logic gates currently used in such projects have several characteristics, however, they cannot be reprogrammed to form a different type of logic gate. It is therefore desirable to construct a logic device that can be quickly reprogrammed to act as a different type of logic gate, and that would result in less power consumption and heat loss, is relatively simple to fabricate, and also would result in space and cost savings. 
     SUMMARY OF THE INVENTION 
     The term “spintronics” refers to a new generation of electronic devices that make use of the electron spin as well as its charge. It is anticipated that spintronics devices will have superior properties compared to their semiconductor counterparts based on reduced power consumption due their inherent nonvolatility, elimination of the initial booting-up of random access memory, rapid switching speed, ease of fabrication, and large number of carriers and good thermal conductivity of metals. Such devices include giant magnetoresistance (GMR) and tunneling magnetoresistance (TMR) structures that consist of ferromagnetic films separated by metallic or insulating layers, respectively. Switching of the magnetization direction of such elementary units is by means of an external magnetic field that is generated by current pulses in electrical leads that are in proximity. 
     A system whereby the magnetization direction is controlled by an applied voltage is discussed at length in U.S. Ser. No. 09/467,808, incorporated herein by reference. Such as system comprises a ferromagnetic device with first and second ferromagnetic layers. The ferromagnetic layers are disposed such that they combine to form an interlayer with exchange coupling. An insulating layer and a spacer layer are located between the ferromagnetic layers. When a direct bias voltage is applied to the interlayer with exchange coupling, the direction of magnetization of the second ferromagnetic layer will change. The structure of a voltage-controlled rotation (VCR) device represents a marriage of GMR and TMR in that the two ferromagnetic layers are separated by nanoscale layers of both a metallic spacer and an insulator. The behavior of the VCR structure was described in U.S. Ser. No. 09/467,808 based on a free-electron-like, one-dimensional approximation. The principle of operation is that a bias voltage modulates the spin-dependent reflectivities such that the magnetization direction of the two ferromagnetic layers can be rotated from parallel to anti-parallel alignment. With such a device element there are many possible applications, such as in magnetic sensors, microwave devices, optical switches, and logic devices. 
     There are several logic devices that are well-known in the art, but these have their drawbacks. In particular, it would be desirable if these logic devices could be reprogrammed in some way, so that each logic gate could be shifted from one type of device within the group of AND, OR, NAND, and NOR gates to a second part and become part of a new circuit. 
     It is therefore an object of this invention to provide a voltage-controlled rotation transistor for use in logic devices. 
     It is also an object of this invention to provide a method of constructing AND, OR, NAND, NOR and NOT gates using voltage-controlled rotation transistors. 
     It is yet another object of this invention to create a series of changeable logic gates wherein the character of a particular logic gate can change depending upon external controllable parameters. 
     It is yet another object of this invention to create a series of logic gates wherein the individual gates can be re-programmed by a user. 
     It is still another object of this invention to create a series of logic gates wherein the logic gates can be reprogrammed on nanosecond time scales. 
     The above referenced objects, advantages and features of the invention together with the organization and manner of operation thereof will become apparent from the following detailed description when taken into conjunction with the accompanying drawings wherein like elements have like numerals throughout the drawings described below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic view of a voltage-controlled rotation (VCR) structure. 
     FIG. 2 is a plot showing the magnetization direction behavior as a function of applied bias voltage, wherein the inset shows the exchange coupling energy vs applied voltage with image force correction when the dielectric constant ∈=10. 
     FIG. 3 is a schematic of the VCR-transistor (VCRT) configuration which includes VCR and TMR elements. 
     FIG. 4 is a plot showing the output voltage characteristic curve of the VCRT where M 1  is parallel to M 3  and where M 1  is antiparallel to M 3 . 
     FIG. 5 is a schematic of a VCR logic device element. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In order to illustrate various embodiments of the invention, the methodology and function are first described for the general concept behind the voltage-controlled rotation (VCR) element and then for applications to the VCR-transistor (VCRT) and corresponding logic devices. Although the manner in which the phenomena is described is one rigorous approach which explains the operation of the invention for those skilled in the art, other conventional mathematical and theoretical explanations can also be used to describe features which characterize various embodiments of the invention. The invention is therefore not limited to the description of its operation nor by the following mathematical explanations of operation. 
     The VCR structure is shown generally at  10  in FIG. 1. A bias voltage has been applied to the VCR structure  10  and which modulates the spin-dependent reflectivity at the interface between a metallic spacer layer  14  and an insulating layer  16 . Therefore, the exchange coupling energy between a harder ferromagnetic layer  12  and a softer ferromagnetic layer  18  is changed such that the magnetization of the softer ferromagnetic layer  18  can be rotated from parallel to anti-parallel to that of the harder (pinned) ferromagnetic layer  12 . Importantly, this oscillation occurs in the absence of any magnetic field. This concept is described at length in the incorporated U.S. Ser. No. 09/467,808. 
     A variety of materials can be used for the harder ferromagnetic layer  12 , the softer ferromagnetic layer  18 , the spacer layer  14 , and the insulating layer  16 . Iron or cobalt is preferably used for the first ferromagnetic layer  12  while iron, cobalt or permalloy is preferably used for the second ferromagnetic layer  16 . In the preferred embodiment of the invention, either chromium or copper can be used for the spacer layer  14 . For the insulating layer  16 , many narrow band gap semiconductors can also be used. For example, materials such as SI 3 N 4 , Al 2 O 3 , SiO 2 , magnesium oxide, silicon, or germanium are particularly useful to achieve the desired result. It should be noted, however, that there are many other materials with similar properties as those mentioned above which can also be used to achieve the functionality of the invention. 
     Each of these layers can also have a variety of thicknesses. Preferably, the first ferromagnetic layer  12  will have a thickness of between about 40 and 100 Å, while the second ferromagnetic layer  18  has a thickness of between about 10 and 50 Å. Both the spacer layer  14  and the insulating layer  16  preferably have a thickness of about 10 Å. It is possible, however, for the thicknesses of the ferromagnetic layers  22  and  24 , in addition to the spacer layer  14  and the insulating layer  16 , which can have a thickness as great as about 500 Å. 
     The following energy equations can be used to describe the magnetization orientation of the two ferromagnetic layers  12  and  18 : 
       E   tot   =J   1 ( V )cos(θ 1 −θ 2 )+ K   1   d   1  sin 2 (θ 1 −φ 1 )+ K   2   d   2  sin 2 (θ 2 −φ 2 )− HM   1   d   1  cos(θ 1 −φ 1 )− HM   2   d   2  cos(θ 2 −Φ).  (1) 
     In this equation, in-plane magnetization and an external magnetic field of zero are assumed. J 1 (V) is the interlayer exchange-coupling energy, which is a function of applied voltage V. The behavior of J 1 (V) is calculated within a free-electron-like, one-dimensional model. K i  is a uniaxial magnetic anisotropy energy, M i  is the magnitude of the magnetization, d i  is the thickness, θ i  is the magnetization direction, and φ i  is the easy axis direction of the i-th layer (where i=1 or 2). H is the magnitude of the external magnetic field, and Φ specifies the direction of the external field. Conventionally in such energy equations, J 1  possesses a constant value for a given sample, and H is varied to solve the equation. However, in this case, it is assumed that H=0, and J 1  is a function of V. The inset of FIG. 2 uses the same parameters as those in U.S. Ser. No. 09/467,808. It is assumed that the harder ferromagnetic layer  12  is much thicker than the softer ferromagnetic layer  18  (d 1 =500 Å and d 2 =20 Å). In this case, it is assumed that K 1,2 =10 4  J/m 3 , and a plot of the magnetization direction of the thinner (softer) ferromagnetic layer  18  as a function of V in shown in FIG.  2 . 
     FIG. 2 shows that the magnetization direction of the thinner (softer) ferromagnetic layer  18  switches by applying a voltage. The voltage V c1  and V c2  are defined as ‘coercive’ voltages. It is important to note that the magnetization direction of the thicker (harder) ferromagnetic layer  12  does not change while the magnetization of the thinner (softer) ferromagnetic layer  18  is rotated. The detailed behavior of the relative magnetization orientations depends on the various parameters, such as the magnitude and types of magnetic anisotropies that are present, and the component layer thicknesses. 
     A VCR-transistor (VCRT), shown generally at  20  in FIG. 3 includes a TMR structure  22  and a VCR structure  24 . The voltage V ext  is the external fixed d.c. voltage source, R L  is an external load resistance, and V in  is the applied voltage for the VCR element  24 . If d 2 &lt;&lt;d 1  to make the second ferromagnetic layer  28  softer, then the magnetization direction of the second ferromagnetic layer  28  can be controlled by the applied voltage V in  as outlined above. Furthermore, the resistance between the second ferromagnetic layer  28  and third ferromagnetic layer  30  that make up the TMR  22  depends on the relative magnetization directions of the two ferromagnetic layers  28  and  30 . Therefore, if there is a constant voltage source V ext , the voltage V ext −V out  between the second and third ferromagnetic layers  28  and  30  would vary as a function of V in . It should also be noted that the voltage level of the second ferromagnetic layer  28  is V out , not ground. Therefore, the V in  of the VCRT  20  defines the voltage difference between the first ferromagnetic layer  26  and the second ferromagnetic layer  28 . Since V in  is ˜1 V, and V out  is ˜100 mV, the change in V out  is only ˜5 mV for a typical case; thus, it is possible to ignore the effect of the change in V out  on the magnitude of V in . 
     In one orientation, it is assumed that M 3  is aligned parallel to M 1 . In other words, it is assumed that the directions of magnetization of the first and third ferromagnetic layers  26  and  30  are parallel to each other. Then when V in &lt;V c2  (see FIGS.  2 - 3 ), M 2  is also parallel to M 3  and, hence, the resistance R↑↑ is small. Increasing V in  causes M 2  to align anti-parallel to M 3  when V in  exceeds the coercive voltage V cl . Then the resistance changes to R↑↓. When V in &lt;V c2 , the resistance returns to the value R↑↑. If the relative resistances are defined as R o =R↑↑ and ΔR o =R↑η−R↑↑=R□↓−R O , the output voltage can be obtained as follows:          V   out     =         V   ext            R   L     /     (       R   L     +     R   0       )         ≡     V   out   H                 V     i                 n       ≤     V   c2               V   out     =         V   ext            R   L     /     (         R   L          R   0       +     Δ                   R   0         )         ≡     V   out   L                 V     i                 n       ≥     V   c1                            
     The output voltage dependence on input voltage is described in FIG.  4 . Usually, while ΔV out =V out   H −V out   L ≈V ext R L ΔR 0 /(R L +R 0 ) 2  is of order ˜5 mV (when R L ≈R 0 ˜kΩ, V ext ˜200 mV, and the TMR  22  is 10%), ΔV in =V c1 −V c2  has a larger value (˜100 mV). The value of ΔV in  is approximated from typical material parameters, but ΔV in  is a very sensitive function of the anisotropy, the thickness of the second ferromagnetic layer  28 , and the voltage dependence of the exchange energy. Therefore, this device cannot amplify the voltage. However, the output voltage has highly nonlinear characteristics that are an essential part of the logic device. It should be noted that if initially M 3  is aligned anti-parallel to M 1 , the output voltage characteristic curve is reversed, as shown in FIG.  4 . 
     Each logic gate consists of two identical VCRT  31  and  32  as shown in FIG.  5 . There are input voltages V in   A  and V in   B  for the VCRT A  31  and the VCRT B  32 , respectively, and the third ferromagnetic layer  34  in VCRT A  31  is connected to the third ferromagnetic layer  36  in VCRT B  32 . The definition of V in   A  and V in   B  is similar to that of the VCRT case of the previous section (the voltage difference between the first and second ferromagnetic layers  26  and  28 , etc.). The external constant voltage source is applied between the second ferromagnetic layer  40  of VCRT B  32  and the ground through the second ferromagnetic layer  40  of VCRT B  32  and the load resistance R L . As described in the previous section, the resistance between the second and third ferromagnetic layers  38  and  34  of VCRT A  31  (and for the corresponding components of VCRT B  32 ) depends on each input voltage and the initial magnetization direction of the third ferromagnetic layer  34  of VCRT A  31  and the third ferromagnetic layer  36  of VCRT B  32 . First the case for which first and third ferromagnetic layers  42  and  34  in VCRT A  31  are parallel and the corresponding components in VCRT B  32  are parallel is considered. The various output voltages are as follows:            V   out     =         R   L            V   ext     /     (       R   L     +     2        R   0         )         ≡     V   1         ,                  when                   V     i                 n     A       =       V     i                 n     B     &lt;     V   c2         ,                  V   out     =         R   L            V   ext     /     (       R   L     +     2        R   0       +     Δ                   R   0         )         ≡     V   2         ,                  when                   V     i                 n     A       &gt;       V   c1                   and                   V     i                 n     B       &lt;       V   c2                   or                   V     i                 n     B       &gt;       V   c1                   and                   V     i                 n     A       &lt;     V   c2                   V   out     =         R   L            V   ext     /     (       R   L     +     2        R   0       +     2      Δ                   R   0         )         ≡     V   3         ,                  when                   V     i                 n       A   ,   B         &gt;       V   c1     .                              
     This case assumes that R 0   A =R 0   B =R 0 . In the case where the first and third ferromagnetic layers  42  and  34  in VCRT A  31  are antiparallel and the corresponding components in VCRT B  32  are antiparallel, the various output voltages are as follows:          V   out     =         R   L            V   ext     /     (       R   L     +     2        R   0         )         ≡     V   1                   when                   V     i                 n     A       =       V     i                 n     B     &gt;     V   c2         ,                  V   out     =         R   L            V   ext     /     (       R   L     +     2        R   0       +     Δ                   R   0         )         ≡     V   2                   when                   V     i                 n     A       &gt;       V   c1                   and                   V     i                 n     B       &lt;       V   c2                   or                   V     i                 n     B       &gt;       V   c1                   and                   V     i                 n     A       &lt;     V   c2               V   out     =         R   L            V   ext     /     (       R   L     +     2        R   0       +     2      Δ                   R   0         )         ≡     V   3                 when                   V     i                 n       A   ,   B         &lt;     V   c2                            
     The characteristics of V out  for various cases are summarized in Table 1, where the input-voltage state is defined for the case V in   A,B &gt;V c1  as ‘H’, and that for V in   A,B &lt;V c2  as ‘L’, and the output voltage states as ‘H out ’ and ‘L out ’ to indicate ‘high’ and ‘low’. 
     
       
         
               
             
               
               
             
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Behavior of V out  for various cases (V 1 &gt;V 2 &gt;V 3 ). 
               
               
                 V out   cri  is the criterion voltage. If V out  &gt; V out   cri , 
               
               
                 then the stge is H out.   
               
             
          
           
               
                 M 3 ∥M 1   
                 M 3  anti-parallel to M 1   
               
             
          
           
               
                 V 2 &lt;V out   cri   
                 V 2 &gt;V out   cri   
                 V 2 &lt;V out   cri   
                 V 2 &gt;V out   cri   
               
             
          
           
               
                 V in   A   
                 V in   B   
                 V out   
                 V in   A   
                 V in   B   
                 V out   
                 V in   A   
                 V in   B   
                 V out   
                 V in   A   
                 V in   B   
                 V out   
               
               
                   
               
               
                 L 
                 L 
                 H out (=V 1 ) 
                 L 
                 L 
                 H out (=V 1 ) 
                 L 
                 L 
                 L out (=V 3 ) 
                 L 
                 L 
                 L out (=V 3 ) 
               
               
                 L 
                 H 
                 L out (=V 2 ) 
                 L 
                 H 
                 H out (=V 2 ) 
                 L 
                 H 
                 L out (=V 2 ) 
                 L 
                 H 
                 H out (=V 2 ) 
               
               
                 H 
                 L 
                 L out (=V 2 ) 
                 L 
                 L 
                 H out (=V 2 ) 
                 H 
                 L 
                 L out (=V 2 ) 
                 H 
                 L 
                 H out (=V 2 ) 
               
               
                 H 
                 H 
                 L out (=V 3 ) 
                 H 
                 H 
                 L out (=V 3 ) 
                 H 
                 H 
                 H out (=V 1 ) 
                 H 
                 H 
                 H out (=V 1 ) 
               
             
          
           
               
                 NOR 
                 NAND 
                 AND 
                 OR 
               
               
                   
               
             
          
         
       
     
     Table 1 shows the logic gate behavior for NOR, NAND, AND, and OR gates for each case. To behave as a logic device, the output of one gate must be the input of the next gate. This can be achieved in two ways: one is to tune the material parameters to fit the requirement, and the other is to attach a buffer, such as a conventional field effect transistor. The most important advantage of this VCRT logic gate is that it is programmable. The same logic gate can be an NOR, NAND, AND, or OR gate depending on the external voltage V ext  and the relative direction of M 3 . If M 3  is replaced with another VCR structure, then the orientation of M 3  can be switched by application of another external voltage. Therefore, the VCR logic device has a re-programmability feature. A processor fabricated from such VCR logic devices could, in principle, be optimally configured for a given task, and then reprogrammed within nanoseconds to optimally perform a different kind of task. According to at least one approximation, it could take as few as ten nanoseconds to reprogram such a VCR logic device. 
     While preferred embodiments have been shown and described, it should be understood that changes and modifications can be made therein without departing from the invention in its broader aspects. Various features of the invention are defined in the following claims.