Abstract:
A basic electronic circuit generates a magnitude. The circuit has certain structural characteristics and the magnitude undergoes variations in function of the structural characteristics of the circuit. The circuit comprises at least two circuit parts suitable for supplying respective fractions of the magnitude and the at least two circuit parts have different structural characteristics.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention refers to a basic electronic semiconductor circuit with reduced sensitivity to process variations. 
         [0003]    2. Description of the Related Art 
         [0004]    In the field of electronic semiconductor apparatus and above all of memory circuits there is a growing demand to obtain basic circuits, such as reference current generators, reference voltage generators, delay chains, etc., as precise as possible, that is independent from the variations of the supply voltage, from the temperature variations and from the process parameters. 
         [0005]    Currently, for example, the majority of the highest precision reference current generators are obtained by means of feedback circuits comprising a high gain amplifier. In this manner the output magnitude becomes a function of the passive network of the “ratio” type, with a transfer function that is not very sensitive to the process variations and thus acceptable in the majority of applications. 
         [0006]    The feedback circuits used in the above-mentioned reference current generators however absorb a high current for functioning; this can lead to turning them off in certain periods of time. Nevertheless said circuits take a certain period of time for turning on and thus cannot be used in those circuitries in which a precise current, ready in a very short time of the order of a few nanoseconds, is necessary. 
         [0007]    It is also necessary for the delay chains to obtain a high response speed and therefore high constructive simplicity with low occupation of area on the chip. 
         [0008]    Known reference current generators circuits are shown in  FIGS. 1 and 1   a.    
         [0009]    The circuit of  FIG. 1  is made by means of a circuit configuration with an NMOS transistor M 1  with the source terminal connected to ground GND. A current I flows in the transistor M 1  of the NMOS type and the transistor M 1  is piloted by a precise voltage signal BG and for example in output from a bandgap circuit. 
         [0010]    The circuit of  FIG. 1   a  is made by means of a circuit configuration similar to the circuit of  FIG. 1  but in which a resistance R 1  is provided between the source terminal of the transistor M 1  and the ground GND. A current I flows in the transistor M 1  of the NMOS type and the transistor M 1  is piloted by a precise voltage signal BG and for example in output from a bandgap circuit. 
         [0011]    Said reference current generators are of the non-feedback type and they have a high turn-on speed. Nevertheless said reference current generators are stable, that is with limited variations, if we assume working ideally with a very stable process, that is with structural parameters or characteristics whose variations are small. In reality in the production of devices at industrial level the process parameters vary widely; this leads to a variation of the reference current generated by a significant percentage. 
         [0012]    Considering the circuit of  FIG. 1   a , we have a dependence of the reference current on the parameters of the active element, that is on the parameters of the transistor M 1 , and on the parameters of the passive element, that is on the resistance R 1 , which are not correlated to each other. The variations of both or on only one of said elements can lead to a variation of the reference current of at least 15-20%. We have the current 
         [0000]    
       
         
           
             I 
             = 
             
               K 
                
               
                 W 
                 L 
               
                
               
                 
                   ( 
                   
                     Vgs 
                     - 
                     Vt 
                   
                   ) 
                 
                 2 
               
             
           
         
       
     
         [0000]    where Vgs is the voltage between the gate and source terminals, W is the width of the gate and L is the length of the gate of the transistor MOS M 1 , 
         [0000]    
       
         
           
             K 
             = 
             
               μ 
                
               
                 Cox 
                 2 
               
             
           
         
       
     
         [0000]    where μ is the mobility, Cox is the capacitance of the oxide that depends on the thickness Tox, Vt is the threshold voltage that depends on the temperature and 
         [0000]    
       
         
           
             R 
             = 
             
               Rs 
                
               
                 Ws 
                 Ls 
               
             
           
         
       
     
         [0000]    where Rs is the layer resistance and Ws and Ls are the width and the length of the semiconductor layer; it is not possible to have effect with project choices on the parameters μ, Vt and Rs. 
       BRIEF SUMMARY OF THE INVENTION 
       [0013]    One embodiment of the present invention provides a basic electronic semiconductor circuit with reduced sensitivity to process variations that overcomes the above-mentioned inconveniences. 
         [0014]    One embodiment of the present invention is a basic electronic circuit suitable for generating a magnitude. The circuit has certain structural characteristics and the magnitude undergoes variations in function of the structural characteristics of the circuit. The circuit includes at least two circuit parts suitable for supplying respective fractions of said magnitude. The at least two circuit parts have different structural characteristics from each other. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0015]    The characteristics and advantages of the present invention will appear evident from the following detailed description of its embodiments thereof, illustrated as non-limiting example in the enclosed drawings, in which: 
           [0016]      FIG. 1  is a circuit diagram of a reference current generator in accordance with the known art; 
           [0017]      FIG. 1   a  is another circuit diagram of a current generator in accordance with the known art; 
           [0018]      FIG. 2  is a circuit diagram of a first basic electronic circuit in accordance with the present invention; 
           [0019]      FIG. 3  is a circuit diagram of a basic electronic circuit in accordance with a construction variant of the circuit of  FIG. 1 ; 
           [0020]      FIG. 4  is a circuit diagram of a further basic circuit in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]      FIG. 2  shows a reference current generator Iref in accordance with one embodiment of the present invention. The generator comprises a circuit part  1  made up of a low voltage transistor ML and a circuit part or branch  2 , arranged in parallel with the circuit part or branch  1 , made up of a transistor for high voltages MH; at the gate terminals of the transistors ML and MH the bandgap voltages BG 1  and BG 2  are applied respectively and the source terminals are connected to ground GND. A current I 1  flows in the circuit part  1  while a current I 2  flows in the circuit part  2  such that I 1 +I 2 =Iref. Given that the threshold voltage Vtl of a low voltage transistor is not correlated by the threshold voltage Vth of a high voltage transistor, it can be said that approximately only for the transistor ML there is a variation of the current I 1  in relation to the threshold voltage Vtl. In this case the variation of the reference current Iref in relation to the threshold voltage Vtl is lower than the variation that the current Iref would undergo if it was generated by the circuit of  FIG. 1  in which the transistor M 1  is a transistor for low voltages. In general if I 1  is a fraction of the current Iref, the variation of the current Iref in relation to the threshold voltage Vtl of the circuit of  FIG. 2  is lower than the variation of the current Iref in relation to the threshold voltage of the circuit of  FIG. 1 . 
         [0022]    In regard to the variation of the current Iref in relation to the variation of the thickness of the oxide Tox, we have that if we indicate with Tox 1  the thickness of the oxide of the transistor ML and Tox 2  the thickness of the oxide of the transistor MN, we have for example that if Tox 2 =4tox 1  and making I 2 = 4 I 1  we have that the variation of the reference current Iref in relation to the variation of the thickness of the oxide is given by 
         [0000]    
       
         
           
             
               
                 ∂ 
                 Iref 
               
               
                 ∂ 
                 Tox 
               
             
             = 
             
               
                 
                   
                     
                       ∂ 
                       I 
                     
                      
                     
                         
                     
                      
                     1 
                   
                   
                     
                       ∂ 
                       Tox 
                     
                      
                     
                         
                     
                      
                     1 
                   
                 
                 + 
                 
                   
                     
                       ∂ 
                       I 
                     
                      
                     
                         
                     
                      
                     2 
                   
                   
                     
                       ∂ 
                       Tox 
                     
                      
                     
                         
                     
                      
                     2 
                   
                 
               
               = 
               
                 
                   - 
                   
                     
                       2 
                        
                       I 
                        
                       
                           
                       
                        
                       1 
                     
                     
                       Tox 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
                 = 
                 
                   - 
                   
                     
                       2 
                        
                       Iref 
                     
                     
                       5 
                        
                       Tox 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
               
             
           
         
       
     
         [0023]    which is lower than the variation Iref/Tox that would be obtained with the known circuits, for example the circuit of  FIG. 1 . 
         [0024]    Another basic circuit in accordance with the invention is shown in  FIG. 3 . Said apparatus comprises in addition to the circuit branches  1  and  2  of the apparatus of  FIG. 2 , to which have been added respectively the transistors ML 1  and MH 1  having the gate terminal connected to the voltages BG 1  and BG 2 , also two more circuit branches  3  and  4 ; the circuit branches  1 - 4  are connected in parallel. Said two circuit branches  3  and  4  are formed by two natural transistors M 3 , M 4  and by two resistances R 3  and R 4  connected to the source terminals of the transistors M 3  and M 4  and to ground and made in a different manner; for example the resistance R 3  is made by means of a region of the N type or N-well and the resistance R 4  is made by means of a semiconductor region with a diffusion of N-type or P-type doping. The resistances R 3  and R 4  have different characteristics seeing that they are made with distinct process phases that make their parameters non correlated. The variations of the fractions  13 ,  14  of the current Iref caused by the resistances R 3  and R 4  will undergo different variations and such that the current Iref will have a variation depending on the resistance which will be lower than the known reference current generators, that is when the current Iref is generated by only one of said circuit branches. 
         [0025]      FIG. 4  shows a delay circuit in accordance with the invention. Differently from the previous embodiment in which the total magnitude was obtained by summing the partial magnitudes generated by cells placed in parallel, in this case the total magnitude will be obtained by disposing the cells in cascade. The delay T is obtained thus by putting in cascade single delay cells and using similarly the approach explained at the beginning, the single delay cells will be made with circuit elements constituted with elements having process parameters that are not correlated. For one cell capacitors made by means of N-type regions or N-well could be used, for another cell capacitors could be used which are made by means of layers of polysilicon or capacitors made by means of semiconductor regions with diffusion of P or N type doping. For the transistors that instead will give rise to the discharge current here too can be used components with parameters that are not correlated such as transistors for low voltages or transistors for high voltages. Said delay circuit comprises therefore a first part  100  suitable for generating a delay T 1  and a second part  200  suitable for generating a second delay T 2 . The first part  100  comprises a transistor M 100  of the low voltage type and a capacitor C 1  while the part  200  comprises a transistor M 200  of the high voltage type with a capacitor C 2 ; the gate terminals of the transistors M 100  and M 200  are connected to two bandgap voltages BG 100  and BG 200 . 
         [0026]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.