Abstract:
A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.

Description:
RELATED APPLICATIONS  
       [0001]     This application is related to the following U.S. patent applications filled of even date with this application, and assigned to the assignee of this application, and incorporated herein by reference: High Performance Programmable Array Local Clock Generator, attorney docket POU920040012; Cache Late Select Circuit, attorney docket POU920040014; and Programmable Sense Amplifier Timing Generator, Attorney docket POU920040014. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates to an improved pulse to static converter circuit for latching the output of a CMOS static RAM cell output, and more particularly to a converter that can be set by level scan inputs, which has low transistor count in its implementation, and has a low power consumption.  
       BACKGROUND  
       [0003]     An issue in the design of high performance static RAM (SRAM) involves the conversion of the dynamic data pulse output of the SRAM cell sense amplifier to a static signal that can be driven off the SRAM macro. There a number of prior art pulse to static converters for use with CMOS SRAM. But these prior art pulse to static converters have a high transistor count or high power consumption, or both.  
       SUMMARY OF THE INVENTION  
       [0004]     An object of this invention is the provision of a pulse to static converter for CMOS SRAM&#39;s that has a low transistor count and low power consumption.  
         [0005]     An additional object of the invention is the provision of such a low transistor count, low power consumption pulse to static converter that can be latched by level scan test bits.  
         [0006]     Briefly, this invention contemplates the provision of a pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The complement of the output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair. During scan test operations, one phase of a complementary clock signal pair disable one of the FET pair (the latch feedback inverter) allowing a new state to be easily fed into the latch. The other phase of the clock re-enables the latch feedback inverter pair, allowing the latch to hold/store the scan data and block new scan data from entering the latch. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0007]      FIG. 1  is partially block and partially schematic drawing of an SRAM sense amplifier with a tri-state output.  
         [0008]      FIG. 2  is a schematic drawing of a pulse to static converter in accordance with the teachings of this invention, suitable for use with a tri-state sense amplifier of the type shown in  FIG. 1 .  
         [0009]      FIG. 3  is a drawing similar to  FIG. 1  showing an SRAM sense amplifier with a complementary output.  
         [0010]      FIG. 4  is a drawing similar to  FIG. 2  showing a pulse to static converter suitable for use with a complementary output of the type shown in  FIG. 3 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]     Referring now to  FIG. 1 , the tri-state output, which appears on the bit lines of the Sense Amp, is coupled to a Tri-State Output Driver, comprised of an FET pair p 6 -n 6  coupled to the sense amplifier output of one bit line and an FET pair p 7 -n 7  coupled to the sense amplifier output of the other bit line. The output of the driver is data_c. As will be appreciated by those skilled in the art, the output of the tri-state sense amplifier has an active high output state, and an active low output state, and in its inactive state is a high impedance state.  
         [0012]     Referring now to  FIG. 2 , here the input data_c is a tri-state input from the SRAM sense amplifier. The latch is comprised of FETs p 3 -n 3  and p 4 -n 4 . The source of p 3  is coupled to a positive operating potential (i.e. Vdd) via Fet p 2 , and the source of n 3  is coupled to ground via n 1 . P 2  and n 2  serve the scan in test mode of operation and are in a conducting state during normal operation. The sources of p 4  and n 4  are coupled to Vdd and ground respectively. The gates of p 3 -n 3  are coupled together and to the data_c input. The gates of p 4 -n 4  are coupled together and to the drains of p 30 p 4 , thus creating the latch. The drains of p 4 -n 4  are coupled to the output driver comprised of FETs p 5  and n 5 .  
         [0013]     For scan test data operation, there is an input labeled “si” to which scan in test data is coupled. The inputs labeled “at” and “ac” are complementary clock inputs active during a scan test operation. The at and ac clock signals are coupled to the gates of p 2  and n 2 , and also the gates of p 1  and n 1 ; these latter two transistors couple the si input to the latch when the clock signals are active.  
         [0014]     In the operation of the embodiment of the invention shown in  FIG. 2 , during normal (non-scan) latch operation, data enters the latch through the input port labeled “data_c”. Note that “data_c” is the complemented rendering of the data. This allows the proper polarity of the data to reach the output: “out”. During stand-by (circuit inactivity state), the upstream Sense Amp presents a high impedance state or “tristate” on the node “data_c”. This allows the previously stored “latch” data to control the voltage on “data_c”. When new data from the Sense Amp is presented to the latch, the Sense Amp will take control of the “data_c” voltage by driving it to the high or low voltage state. This will force the latch and the “out” signal to the desired state. Next, the Sense Amp will return to the “tristate” condition, allowing the latch to regain control of the node “data_c” and the output node “out”.  
         [0015]     Referring now to  FIG. 3 , here the Sense Amp has a dual phase output on its bit lines, one phase of which is coupled to the gates p 7 -n 7  in the Dual Phase Output Driver and the other phase of which is coupled to the gates of p 6 -n 6  of the Driver. The true and complement data outputs (where either output is driven to a high state and returns to zero at the end of the operation) are labeled data-c and data-t.  
         [0016]     Referring now to  FIG. 4 , it will be noted that the latch circuit and the scan in test data circuit are substantially the same as previously described in connection with  FIG. 2 . Here there are two data inputs, labeled data-c and data-t coupled to the gates of NFETs nc and nt respectively. NFET nd is connected in a source follower configuration. When the input data_c is driven to the high state, NFET nc pulls the latch node “t” to a ground state and the source follower action of nd will begin to drive the latch node “c” to the high state, which is reinforced by the latch PFET p 4 . As a result the output “out” will fall to the low state. The reverse is true for the input labeled data_t. When it is driven to the high state the latch node “c” will be driven to the ground state by the turning on of NFET nt so that the output node “out” will be correspondingly to a high voltage state.  
         [0017]     In the operation of  FIG. 4 , during normal (non-scan) latch operation, data enters the latch through the input ports labeled “data_c” and “data_t”.  
         [0018]     Note that during an active state; the inputs labeled “data_t” and “data_c” are complementary signals, meaning that either “data_t” or “data_c” will go to the high voltage state and the other will remain at it low voltage stand-by state. During stand-by (circuit inactivity state), the upstream Sense Amp (shown in  FIG. 3 ) presents a low voltage value for both “data_t” and “data_c”. This allows the previously stored “latch” data to control the voltage on the output node labeled: “out” (in  FIG. 4 ). When new data from the Sense Amp (in  FIG. 3 ) is presented to the latch, the Sense Amp will drive either “data_t” or “data_c” to a high voltage state and the other will remain at it low voltage stand-by state. This action will force the latch and the node “out” to the new data state. Next, the Sense Amp will return to the standby condition, allowing the latch to maintain control of the output node “out”.  
         [0019]     In the scan test operation, as previously explained, the “latch” input labeled “si” is the “scan-in” port to the latch in both embodiments of the invention. For example, the “si” port of the latch is feed by the “out” port of the previous latch. In this way, the data in one latch is passed to the next latch, during scanning operations. The scanning operation is controlled by clock signals “at” and “ac” where “ac” has the complement phase of “at”. Referring to  FIGS. 2 and 4 , the input ports labeled “at” and “ac” are the scan control clock inputs. During scanning, new data would be presented at the input “si” prior to the rising edge of “at” and falling edge of “ac”.  
         [0020]     When “at” and “ac” are active, the latch feedback inverter made up of p 2 , p 3 , n 3 , and n 2  is disabled allowing the new date to easily feed into the latch. When “at” and “ac” are go in-active, the latch feedback inverter made up of p 2 , p 3 , n 3 , and n 2  is re-enabled allowing latch to hold/store the new data and blocks new data from entering the latch. During normal latch operation, “at” and “ac” are in their in-active state.  
         [0021]     While the preferred embodiment of the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection of the invention described herein.