Abstract:
The present invention provides a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management schemes. In the system, NVM is used as large-capacity main memory, and DRAM is used as a cache to the NVM. Some reserved bits in the data structure of TLB and last-level page table are employed effectively to eliminate hardware costs in the conventional hardware-managed hierarchical memory architecture. The cache management in such a heterogeneous memory system is pushed to the software level. Moreover, the invention is able to reduce memory access latency in case of last-level cache misses. Considering that many applications have relatively poor data locality in big data application environments, the conventional demand-based data fetching policy for DRAM cache can aggravates cache pollution. In the present invention, an utility-based data fetching mechanism is adopted in the DRAM/NVM hierarchical memory system, and it determines whether data in the NVM should be cached in the DRAM according to current DRAM memory utilization and application memory access patterns. It improves the efficiency of the DRAM cache and bandwidth usage between the NVM main memory and the DRAM cache.

Description:
TECHNICAL FIELD 
       [0001]    The present invention belongs to the field of cache performance optimization in a DRAM/NVM heterogeneous memory environment, and in particular, a DRAM/NVM hierarchical heterogeneous memory access method and system with software-hardware cooperative management schemes are designed, and an utility-based data fetching mechanism is proposed in this system. 
       BACKGROUND ART 
       [0002]    With the development of the multi-core and multi-threading technology, Dynamic Random Access Memory (DRAM) can no longer meet the growing memory demand of applications due to restrictions in terms of power consumption and techniques. Emerging Non-Volatile Memories (NVMs), such as Phase Change Memory (PCM), Spin Transfer Torque Magneto resistive Random Access Memory (STT-MRAM), and Magnetic Random Access Memory (MRAM), have features such as byte-addressable, comparable read speed with DRAM, near-zero standby power consumption, high density (storing more data per chip), and high scalability, and may serve as a substitute for DRAM as the storage medium of main memory. However, compared with the DRAM, these new non-volatile memories still have a lot of disadvantages: (1) a relatively high read/write delay, where the read speed is approximate twice slower than that of DRAM, and the write speed is almost five times slower than that of the DRAM; (2) high write power consumption; and (3) a limited endurance life. Therefore, it is unfeasible to directly use these emerging non-volatile memories as the computer main memory. A mainstream approach at present is to integrate a large amount of non-volatile memories with a small amount of DRAMs to form a heterogeneous memory system, so that the performance, power efficiency and endurance of the memory system are improved by exploiting the advantage of large capacity of the non-volatile memory and the advantages of a low memory access delay, low write power consumption, and high endurance of the DRAM. 
         [0003]    There are mainly two types of heterogeneous memory architectures at present: flat and hierarchical heterogeneous memory architectures. 
         [0004]    In a heterogeneous memory system with a flat architecture, the NVM and the DRAM are uniformly addressable, and both NVM and DRAM are used as main memory. To improve the power efficiency and performance of the system, hot page migration is a common optimization policy adopted in this architecture. That is, frequently accessed NVM page frames are migrated to the DRAM. A migration operation is generally divided into two sequential steps: (1) copying the content of source and target page frames into a buffer; and (2) writing the data in the buffer into target addresses. Therefore, one page migration operation may generate four times of page replication, and thus the time cost of the migration operations are relatively large because the reading phase and the writing phase are performed sequentially. Besides, if a memory system supports 2 MB or 4 MB superpage to reduce TLB miss rate, the hot page migration mechanism can leads to tremendous time and space overhead. 
         [0005]    In a heterogeneous memory system with a hierarchical architecture, high-performance memories such as DRAM are used as a cache to the non-volatile memory. As memory access to DRAM cache is more efficient than that of NVM, a heterogeneous memory system with a hierarchical architecture can achieve better application performance compared with the heterogeneous memory system with a flat architecture. In a conventional hierarchical heterogeneous memory system, a DRAM cache is managed by hardware and is transparent to operating systems, and the organization of the DRAM cache is similar to a conventional on-chip cache. When a LLC miss occurs, the hardware circuit in DRAM memory controller is responsible for tag lookup of a physical page address. It determines whether data access is hit in the DRAM cache, and then performs actual data access. This implies that the hierarchical heterogeneous memory system has a relatively long access delay when a DRAM cache miss occurs. In addition, the hardware-managed DRAM cache generally adopts a demand-based data fetching mechanism. When data is not hit in DRAM cache, the NVM data block corresponding to the missing data should be fetched into DRAM cache first and then is loaded to on-chip last-level cache. In big data environments, a lot of applications have poor temporal/spatial locality, and such data fetching mechanism would aggravate cache pollution. 
       SUMMARY 
       [0006]    In view of the disadvantages of the prior techniques, the present invention provides a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management, which is aimed at eliminating large hardware costs and reducing memory access delay in a conventional hierarchical heterogeneous memory system. Moreover, DRAM cache can be managed in a more flexible manner by software, and thus the DRAM cache utilization and memory access throughput between NVM and DRAM are improved. In a hardware view, the data layout of Translation Lookaside Buffer (TLB) is modified in the present invention. In a software view, the data structure of current page table is extended to support a mapping from NVM pages to DRAM pages. Furthermore, an utility-based data fetching policy is designed to improve the utilization of DRAM cache and bandwidth usage between NVM main memory and DRAM cache. 
         [0007]    To achieve the aforementioned objectives, a hardware-managed DRAM/NVM hierarchical memory access method is provided, including: 
         [0008]    step 1: address translation in TLB: acquiring the physical page number (ppn), the P flag, and content of the overlap tlb field from an TLB entry which corresponds to a virtual page number (vpn), and translating the virtual address into an NVM physical address according to the ppn; 
         [0009]    step 2: determining whether memory access is hit in the on-chip cache; directly fetching, by a CPU, a requested data block from the on-chip cache if the memory access is hit, and ending a memory access process; otherwise, turning to step 3; 
         [0010]    step 3: determining a memory access type according to the P flag acquired in step 1; if P is 0, which indicates access to an NVM memory, turning to step 4, updating information of the overlap tlb field (where the field is used as a counter in this case) in the TLB entry, and determining, whether the NVM physical page corresponding to the virtual page should be fetched into the DRAM cache according to the fetching threshold in the dynamic threshold adjustment algorithm and the overlap tlb field acquired in step 1. Otherwise, if P is 1, which indicates access to a DRAM cache and indicates that the cache is hit, calculating the physical address of the to-be-accessed DRAM cache according to the information of the overlap tlb field acquired in step 1 and the offset of virtual address, and turning to step 6 to access the DRAM cache; 
         [0011]    step 4: looking up the TLB for an entry corresponding to an NVM main memory page if the value of the overlap tlb field acquired in step 1 is less than the fetching threshold, and increasing the value of overlap tlb field (where the field is used as a counter in this case) of the TLB by one, go to step 6 to directly access the NVM memory, where the fetching threshold is determined by a fetching threshold runtime adjustment algorithm; if the value of the overlap tlb field acquired in step 1 is greater than the fetching threshold, go to step 5 to fetch the NVM main memory page into the DRAM; 
         [0012]    step 5: prefetching the NVM page corresponding to the virtual address into the DRAM cache, and updating the TLB and the extended page table; and step 6: memory access: accessing the NVM page according to the physical address delivered to the memory controller. 
         [0013]    According to another embodiment of the present invention, a software-managed DRAM/NVM hierarchical heterogeneous memory system is provided, including modified TLB layout, extended page table, and a utility-based data fetching module, where: 
         [0014]    the modified TLB is used to cache the address mapping of virtual-to-NVM and also virtual-to-DRAM. This mechanism improves the efficiency of address translation. In addition, some reserved bits in TLB is further used to record page access frequency of applications, so as to assist the utility-based data fetching module for decision making; 
         [0015]    the extended page table stores all mapping from virtual pages to physical pages and mapping from NVM pages to DRAM cache pages, where a PD flag is used to indicate the type of a page frame recorded in a page table entry; and 
         [0016]    the utility-based data fetching module is used to replace the demand-based data fetching policy in a conventional hardware-managed cache. The module mainly includes three sub-modules: a memory monitoring module, a fetching threshold runtime adjustment module, and a data prefetcher: (1) the memory monitoring module is used to acquire DRAM cache utilization and NVM page access frequency from the modified TLB and memory controller, and use them as input information for data fetching threshold runtime adjustment module; (2) the fetching threshold runtime adjustment module is used to dynamically adjust the data fetching threshold according to the runtime information provided by the memory monitoring module, to improve DRAM cache utilization and bandwidth usage between the NVM and the DRAM; (3) the data prefetcher is used to: {circle around (1)} trigger a buddy allocator of the DRAM cache management module to allocate a DRAM page for caching a NVM memory page; {circle around (2)} copy content of the NVM memory page to the DRAM page allocated by the buddy allocator; and {circle around (3)} update the extended page table and the TLB. 
         [0017]    In general, compared with the previous techniques, the present invention have the following advantages: 
         [0018]    (1) The system modifies the TLB data structure and extends the page table, which enable uniform management of DRAM cache pages and NVM main memory pages, and eliminates hardware costs in a conventional DRAM/NVM hierarchical memory system while reducing memory access delay. 
         [0019]    (2) The system monitors memory accesses using some TLB reserved bits, and eliminates huge hardware costs compared with the conventional DRAM/NVM heterogeneous memory system that monitors the page access frequency in the memory controller. 
         [0020]    (3) The system develops a utility-based cache fetching method, and a dynamic fetching threshold adjustment algorithm is designed to dynamically adjust the fetching threshold according to application memory access locality and utilization of the DRAM cache, which improves utilization of the DRAM cache and bandwidth usage between the NVM main memory and the DRAM cache. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  is a structural diagram of a DRAM-NVM hierarchical heterogeneous memory system with software-hardware cooperative management according to the present invention; 
           [0022]      FIG. 2  shows last-level page table entry structures before and after extension according to the present invention; 
           [0023]      FIG. 3  shows TLB entry structures before and after modification according to the present invention; 
           [0024]      FIG. 4  is a working flow chart of a DRAM-NVM heterogeneous memory system according to the present invention; 
           [0025]      FIG. 5  is a flow chart of translation from a virtual address to a physical address in a DRAM-NVM hierarchical heterogeneous memory system according to the present invention; 
           [0026]      FIG. 6  is a flow chart of TLB lookup and update in a DRAM-NVM hierarchical heterogeneous memory system according to the present invention; 
           [0027]      FIG. 7  is a flow chart of page table query in a DRAM-NVM hierarchical heterogeneous memory system according to the present invention; and 
           [0028]      FIG. 8  is a flow chart of prefetching an NVM page to a DRAM cache in a DRAM-NVM hierarchical heterogeneous memory system according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    To illustrate the objectives, technical solutions and advantages of the presented invention more clearly, the following further describes the details of this invention with figures and case studies. It should be noted that, the specific cases described in this invention are only used to illustrate the present invention rather than limiting the application scenarios of this invention. 
         [0030]      FIG. 1  shows system architecture of a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management. The hardware layer includes a modified TLB, and the software layer includes extended page table, a utility-based data fetching module, and a DRAM cache management module. The extended page table is mainly used to manage the mapping from virtual pages to physical pages and the mapping from NVM memory pages to DRAM cache pages. The modified TLB caches page table entries that are frequently accessed in the extended page table, thereby improve the efficiency of address translation. In addition, some reserved bits in the modified TLB is further used to record access frequency of NVM memory pages, and to assist the utility-based data fetching module in data fetching operations. The utility-based data fetching module is mainly used to cache the NVM page in the DRAM, and it includes three sub-modules: a memory monitoring module, a fetching threshold runtime adjustment module, and a data fetcher, where the memory monitoring module is used to collect page access frequency information and cache utilization from the TLB and memory controller, respectively; the fetching threshold runtime adjustment module dynamically adjusts the page fetching threshold according to the information collected by the memory monitoring module. When access frequency of a NVM memory page is greater than the threshold, the data fetcher is invocated to cache the NVM page into the DRAM. The DRAM cache management module is mainly used to manage the DRAM cache, and mainly includes a buddy allocator sub-module. When a NVM page needs to be cached into the DRAM, the buddy allocator allocates a DRAM page to load the content of the NVM page according to a buddy allocation algorithm, and meanwhile updates the extended page table to set up a mapping from the NVM page to the DRAM page, so that the DRAM page can be written back to the corresponding NVM page when the DRAM page is reclaimed. 
         [0031]    To push the management of DRAM cache to the software level, in the present invention, DRAM cache and NVM are uniformly managed in a flat physical address space, and the data structure of last-level page table is extended, as shown in  FIG. 2 . A conventional page table entry generally includes flags such as P, R/W, U/S, D, and AVAIL, where the P flag indicates whether a page recorded in the page table entry has been fetched into the memory; the R/W flag records an read/write operation permission on the page recorded in the page table entry, where R represents that read is allowed, and W represents that write is allowed; the U/S flag indicates whether the page recorded in the page table entry is a user mode page frame or a kernel mode page frame; the D flag is used to record whether any data has been written into the page corresponding to the entry. On the basis of a conventional page table, a PD flag bit and an overlap field are added to the last-level page table entry after extension. The PD flag (1 bit) indicates the medium type of a physical page frame corresponding to a virtual page frame. When PD is 0, it indicates that the physical page frame corresponding to the virtual page frame is an NVM main memory; and when PD is 1, it indicates that the physical page frame corresponding to the virtual page frame has been fetched from the NVM main memory into the DRAM cache. The overlap field records different content according to different PD flags: when PD is 0, the field is used as a counter and records the number of memory accesses to the page referenced by the page table entry; and when PD is 1, the field records the physical address of a DRAM page corresponding to an NVM page, thereby establishing a mapping from the NVM page to the DRAM page. 
         [0032]    The TLB, as one of the most important hardware in a computer system, eliminates most of page table walk overheads by caching the recently accessed page table entries, and thus significantly improve the efficiency of translation from a virtual address to a physical address. In this invention, some reserved bits of the TLB entry are used to extend the data structure a TLB entry, so that a TLB entry can cache an extended page table entry, as shown in  FIG. 3 . On the basis of the current data structure of the TLB entry, a P flag bit and an overlap tlb field are added in the extended TLB entry. Similar to the PD flag in the page table entry, the P flag is used to indicate the medium type of a physical page frame corresponding to a virtual page frame recorded in the TLB entry. When P is 0, it indicates that the TLB entry records the mapping from a virtual page to a NVM physical page, and the overlap tlb field is used to record the number of memory accesses to a page referenced by a TLB entry. When P is 1, it indicates that the physical page recorded in the TLB entry has been fetched from the NVM main memory into the DRAM cache, and the overlap tlb field records the DRAM page number corresponding to the NVM page. 
         [0033]      FIG. 4  is a working flow chart of a DRAM-DRAM hierarchical heterogeneous memory system with software-hardware cooperative management according to the present invention, where specific steps are as follows: 
         [0034]    Step 1: TLB address translation: acquire the physical page number ppn, the P flag, and content of the overlap tlb field in a TLB entry which corresponds to a virtual page, and translate the virtual address into an NVM physical address according to the ppn. As shown in  FIG. 5 , step 1 specifically includes the following sub-steps: 
         [0035]    (1-1) TLB lookup: Look up the TLB entry by using a virtual page number as the keyword, to acquire a physical page number ppn, a P flag bit and content of an overlap tlb field corresponding to the virtual page number, as shown in  FIG. 6 a   ). 
         [0036]    (1-2) If an entry corresponding to the virtual address is found in the TLB, that is, the TLB is hit, acquire the physical page number corresponding to the virtual page, translate the virtual address into physical address, and go to step 2 to access an on-chip cache by using the physical address; otherwise, i.e., the TLB is missing, and a page table walk is needed. This process is similar to a page table walk process in conventional architectures, as shown in  FIG. 7 . It includes the following detailed steps: 
         [0037]    (1-2-1) Acquire the base address of level-1 page table by using the CR3 register; acquire the index a of level-1 page directory according to the virtual address, and add the index a to the base address of level-1 page table to calculate the base address of level-2 page directory. 
         [0038]    (1-2-2) Access the entry in level-1 page directory according to the address obtained in (1-2-1) and acquire the base address of level-2 page directory addr[a]. Add addr[a] to index b of the level-2 page directory to calculate the base address of level-3 page directory. 
         [0039]    (1-2-3) Repeat this process till a last-level page table is accessed. If the entry corresponding to the virtual address is valid, acquire the corresponding physical page number addr [c], the flag PDc which indicates the storage medium type of a page frame (when PDc is 1, meaning that the page frame is in DRAM, otherwise the PDc is 0, meaning that the page frame is in NVM), and content of an overlap field; otherwise the accessed entry is invalid, load the missing page into the NVM main memory from the external storage, update the page table, and then go to (1-2-4) to update the TLB. 
         [0040]    (1-2-4) TLB update: insert a TLB entry which sets up a mapping from the virtual address to the physical address (virtual page number vpn, physical page number addr [c], PDc, and overlap field c) into the TLB, as shown in  FIG. 6( b ) . The TLB update mainly includes the following two sub-steps: 
         [0041]    (1-2-4-1) If PDc is 0, which indicates that the physical page corresponding to the virtual page is an NVM page, set the P flag of the TLB entry to 0; otherwise, the physical page corresponding to the virtual page is a DRAM page, and the P flag of the TLB entry is set to 1. 
         [0042]    (1-2-4-2) If the TLB table has free space, create a new entry and insert (virtual page number vpn, physical page number addr[c], PDc, overlap field) into the new TLB entry, where the overlap field corresponds to the overlap tlb field in the TLB; If the TLB table is full, reclaim a TLB entry using LRU replacement algorithm, and then install a new TLB entry. 
         [0043]    Step 2: Determine whether the memory access is hit in the on-chip cache, directly fetch, by a CPU, a requested data block from the on-chip cache if the memory access is hit, and end the memory access process; otherwise, turn to step 3; 
         [0044]    step 3: determine the storage medium of memory access according to the P flag acquired in step 1; if P is 0, which indicates an NVM page access, and go to step 4, updating information of the overlap tlb field (where the field is used as a counter in this case) in the TLB entry, and determine whether the NVM physical page corresponding to the virtual page should be fetched into the DRAM cache according to the fetching threshold in the dynamic threshold adjustment algorithm and the overlap tlb field acquired in step 1. Otherwise, if P is 1, this indicates a DRAM page access and the cache is hit, and then the physical address of the to-be-accessed DRAM cache is obtained according to the overlap tlb field acquired in step 1 and the offset of virtual address, and go to step 6 to access the DRAM cache; 
         [0045]    step 4: Look up the TLB for an entry corresponding to an NVM main memory page if the value of the overlap tlb field acquired in step 1 is less than the fetching threshold, and increase the value of overlap tlb field (where this field is used as a counter in this case) in the TLB by one, go to step 6 to directly access the NVM memory, where the fetching threshold is determined by a fetching threshold runtime adjustment algorithm; if the value of the overlap tlb field acquired in step 1 is greater than the fetching threshold, go to step 5 to fetch the NVM main memory page into the DRAM; The fetching threshold runtime adjustment algorithm includes the following sub-steps: 
         [0046]    (4-1) Acquire, by a memory monitoring module, the number of NVM page fetching times n fetch , the number of cache read times n dram   _   read , and the number of cache write times n dram   _   write  from the memory controller. Assume the average read and write latencies of the NVM are t nvm   _   read  and t nvm   _   write , respectively, the average read and write latencies of the DRAM are t dram   _   read  and t dram   _   write , respectively, and the overhead of caching a DRAM page is t fetch . and calculates, every 10 9  clocks by using formula 4.1, a performance gain benefitted from caching NVM page to DRAM in every 10 9  clocks: 
         [0000]      benefit t   =n   dram   _   read ×( t   nvm   _   read   −t   dram   _   read )+ n   dram   _   write ×( t   nvm   _   write   −t   dram   _   write )− n   fetch   ×t   fetch    (Formula 4.1)
 
         [0047]    (4-2) Assume that the initial fetching threshold is fetch_thres 0  (fetch_thres 0 ≧0), the fetching threshold and performance gain in the previous 10 9 -clock period are fetch_thres t-1  and benefiet t-1 , respectively, and the fetching threshold and the performance gain of current 10 9 -clock period are fetch_thres t  and benefiet t , respectively, and the cache utilization is dram_usage. Adjust the prefetching threshold by using a hill climbing algorithm if dram_usage&gt;30%, which mainly includes the following sub-steps: 
         [0048]    4-2-1) If it is the first time adjusting the threshold, calculate the performance gain under the given fetching threshold. If benefiet t ≧0 it indicates that data block fetching can improve system performance, and if fetch_thres 0 &gt;0, fetch_thres t =fetch_thres 0 −1; otherwise benefiet t &lt;0, it indicates that data block fetching may decrease system performance, fetch_thres t =fetch_thres 0 +1. If it is not the first time adjusting the threshold, go to the next step; 
         [0049]    4-2-2) If benefit t &gt;benefit t-1 , it indicates that the fetching threshold adjusting method used in the previous 10 9 -clock period is able to improve the system performance, and the threshold adjusting method is kept the same as the action in the previous 10 9 -clock period. That is, if the fetching threshold is decreased in the previous 10 9 -clock period and fetch_thres t-1 &gt;0, fetch_thres t =fetch_thres t-1 −1; and if the fetching threshold is increased in the previous 10 9 -clock period, fetch_thres t =fetch_thres t-1 +1; Otherwise benefit t &lt;benefit t-1 , use a threshold adjusting method opposite to that of the previous 10 9 -clock period. 
         [0050]    4-2-3) Update benefiet t-1  to be benefiet t . 
         [0051]    Step 5: fetch the NVM page corresponding to the virtual address into the DRAM cache, and update the TLB and the extended page table. As shown in  FIG. 8 , this step mainly includes the following sub-steps: 
         [0052]    (5-1) If the DRAM cache is full, LRU algorithm is used to determine which DRAM cache page can be reclaimed. If the cached page is dirty, look up the extended page table to obtain the physical address of the NVM memory page corresponding to the DRAM page, and then write the modified DRAM page back to its corresponding NVM page, set the P flag of the TLB entry corresponding to the DRAM page to 0, and set the PD flag of the extended page table entry as 0 (indicating that the physical page corresponding to the virtual page is now in the NVM main memory); If the DRAM cache is not full, go to step (5-2). 
         [0053]    (5-2) Call the buddy allocator of the DRAM cache management module to allocate an free DRAM page, and assume the address of the free DRAM page is dram_ppn. 
         [0054]    (5-3) Set up the mapping from the NVM page to the DRAM cache page in the extended page table and the TLB. That is, set the overlap field of the extended page table as dram_ppn, and set the PD flag of the extended page table as 1; and set the overlap tlb field of the TLB as dram_ppn, and set the P flag of the TLB as 1. 
         [0055]    (5-4) Call the memory controller to copy the NVM page to the corresponding DRAM page. 
         [0056]    Step 6: Memory access: access the memory according to an address transmitted into the memory controller. 
         [0057]    In the present invention, a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management scheme is designed. By extending the last-level page table and TLB, step 1 and step 5 eliminate hardware costs in a conventional hardware-managed DRAM/NVM hierarchical memory systems and reduce memory access latency in case of a last-level cache miss. DRAM cache management is pushed to the software level, and thus improve the flexibility of the DRAM/NVM hierarchical heterogeneous memory systems. Considering that applications with poor data locality would cause severe cache pollution, this invention adopts an utility-based data caching algorithm to filter the DRAM cache, as described in step 3 and step 4. It improves efficiency of the DRAM cache and bandwidth usage from the NVM memory to the DRAM cache. 
       Aspects: 
       [0058]    The following numbered aspects provide further disclosure of the invention. It is noted that any of aspects 1-4 below can be combined with any of aspects 5-8. 
         [0059]    1. A DRAM/NVM hierarchical heterogeneous memory access method with software-hardware cooperative management scheme, comprising the following steps: 
         [0060]    step 1: address translation in TLB: acquiring the physical page number (ppn), the P flag, and content of the overlap TLB field from an TLB entry which corresponds to a virtual page number (vpn), and translating the virtual address into an NVM physical address according to the ppn; 
         [0061]    step 2: determining whether memory access is hit in an on-chip cache; directly fetching, by a CPU, a requested data block from the on-chip cache if the memory access is hit, and ending a memory access process; otherwise, turning to step 3; 
         [0062]    step 3: determining the storage medium of memory access according to the P flag acquired in step 1; if P is 0, this indicates an NVM page access, and go to step 4, updating information of the overlap tlb field (where the field is used as a counter in this case) in the TLB entry, and determining, according to the fetching threshold in the dynamic threshold adjustment algorithm and the overlap tlb field acquired in step 1, whether to fetch the NVM physical page corresponding to the virtual page into the DRAM cache. Otherwise, if P is 1, which indicates a DRAM page access and the cache is hit, and then the physical address of the to-be-accessed DRAM cache is obtained according to the overlap TLB field acquired in step 1 and the offset of virtual address, and go to step 6 to access the DRAM cache; 
         [0063]    step 4: looking up the TLB for an entry corresponding to an NVM main memory page if the value of the overlap TLB field acquired in step 1 is less than the fetching threshold, and increasing the value of overlap tlb field (where the field is used as a counter in this case) in the TLB by one, turning to step 6 to directly access the NVM memory, where the fetching threshold is determined by a fetching threshold runtime adjustment algorithm; turning to step 5 to fetch the NVM main memory page into the DRAM if the value of the overlap TLB field acquired in step 1 is larger than the fetching threshold; 
         [0064]    step 5: fetching the NVM page corresponding to the virtual address into the DRAM cache, and updating the TLB and the extended page table; and 
         [0065]    step 6: memory access: accessing the memory according to an address transmitted into a memory controller. 
         [0066]    2. The method according to aspect 1, wherein step 4 comprises the following sub-steps: 
         [0067]    (4-1) acquiring, by a memory monitoring module, the number of prefetching times n fetch , the number of cache read times n dram   _   read , and the number of cache write times n dram   _   write  from the memory controller, wherein in the system, the average read and write latencies of the NVM are t nvm   _   read  and t nvm   _   write , respectively, the average read and write latencies of the DRAM are t dram   _   read  and t dram   _   write , respectively, and the overhead of caching a DRAM page is t fetch . Formula 4.1 calculates the system performance gain benefitted from caching NVM page to DRAM in every 10 9  clocks: 
         [0000]      benefit t   =n   dram   _   read ×( t   nvm   _   read   −t   dram   _   read )+ n   dram   _   write ×( t   nvm   _   write   −t   dram   _   write )− n   fetch   ×t   fetch    (Formula 4.1)
 
         [0068]    (4-2) Assuming that the initial fetching threshold is fetch_thres 0  (fetch_thres 0 ≧0), the fetching threshold and performance gain in the previous 10 9 -clock period are fetch_thres t-1  and benefiet t-1 , respectively, and the fetching threshold and the performance gain of current 10 9 -clock period are fetch_thres t  and benefiet t , respectively, and the cache utilization is dram_usage. If dram_usage&gt;30%, the hill climbing algorithm is adopted to adjust the fetching threshold. 
         [0069]    3. The method according to aspect 2, wherein the adjusting the prefetching threshold by using a hill climbing algorithm in step (4-2) comprises the following sub-steps: 
         [0070]    4-2-1) If it is the first time adjusting the threshold, calculate the performance gain under the given fetching threshold. If benefiet t ≧0, it indicates that data block fetching can improve system performance, and if fetch_thres 0 &gt;0, fetch_thres t =fetch_thres 0 −1; otherwise benefiet t &lt;0, it indicates that data block fetching may decrease system performance, fetch_thres t =fetch_thres 0 +1. If it is not the first time adjusting the threshold, go to the next step; 
         [0071]    4-2-2) benefit t &gt;benefit t-1 , it indicates that the fetching threshold adjusting method used in the previous 10 9 -clock period is able to improve the system performance, and the threshold adjusting method is kept the same as the action in the previous 10 9 -clock period. That is, if the fetching threshold is decreased in the previous 10 9 -clock period and fetch_thres t-1 &gt;0, fetch_thres t =fetch_thres t-1 −1; and if the fetching threshold is increased in the previous 10 9 -clock period, fetch_thres t =fetch_thres t-1 + 1 ; Otherwise benefit t &lt;benefit t-1 , use a threshold adjusting method opposite to that of the previous 10 9 -clock period; and 4-2-3) updating benefiet t-1  to be benefiet t . 
         [0072]    4. The method according to aspect 1 or 2, wherein step 5 comprises the following sub-steps: 
         [0073]    (5-1) determining, by using an LRU algorithm, the address of a DRAM cache page to be reclaimed if the DRAM cache is full, and looking up the extended page table to obtain an address of an NVM memory page corresponding to the DRAM page if the cache page is written and dirty, writing modified cache page content back to a corresponding NVM main memory, setting a P flag of a TLB entry corresponding to the DRAM page as 0, and setting a PD flag of an entry of the extended page table as 0; or turning to step (5-2) if the DRAM cache is not full; 
         [0074]    (5-2) calling the buddy allocator of the DRAM cache management module to allocate an free DRAM page, and assume the address of the free DRAM page is dram_ppn. 
         [0075]    (5-3) setting up the mapping from the NVM page to the DRAM cache page in the extended page table and the TLB. That is, set the overlap field of the extended page table as dram_ppn, and set the PD flag of the extended page table as 1; and set the overlap tlb field of the TLB as dram_ppn, and set the P flag of the TLB as 1. 
         [0076]    (5-4) calling the memory controller to copy the NVM page to the corresponding DRAM page. 
         [0077]    5. A DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management scheme, comprising modified TLB layout, extended page table, and utility-based data fetching module. The significant features include: 
         [0078]    the modified TLB is used to cache the address mapping of virtual-to-NVM and also virtual-to-DRAM. This mechanism improves the efficiency of address translation. In addition, some reserved bits in TLB is further used to record page access frequency of applications, so as to assist the utility-based data fetching module for decision making; 
         [0079]    the extended page table stores all mapping from virtual pages to physical pages and mapping from NVM pages to DRAM cache pages, where a PD flag is used to indicate the type of a page frame recorded in a page table entry; and 
         [0080]    the utility-based data fetching module is used to replace the demand-based data fetching policy in a conventional hardware-managed cache. The module mainly includes three sub-modules: a memory monitoring module, a fetching threshold runtime adjustment module, and a data prefetcher: (1) the memory monitoring module is used to acquire DRAM cache utilization and NVM page access frequency from the modified TLB and memory controller, and use them as input information for data fetching threshold runtime adjustment module; (2) the fetching threshold runtime adjustment module is used to dynamically adjust the data fetching threshold according to the runtime information provided by the memory monitoring module, to improve DRAM cache utilization and bandwidth usage between the NVM and the DRAM; (3) the data prefetcher is used to: {circle around (1)} trigger a buddy allocator of the DRAM cache management module to allocate a DRAM page for caching a NVM memory page; {circle around (2)} copy content of the NVM memory page to the DRAM page allocated by the buddy allocator; and {circle around (3)} update the extended page table and the TLB. 
         [0081]    6. The DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management according to aspect 5, wherein the data structures of the last-level page table entry and the TLB entry are modified, and the mapping from virtual pages to physical pages and the mapping from NVM memory pages to DRAM cache pages are uniformly managed, which improves an access speed while ensuring the correctness of cache access and reclaiming, and eliminates hardware overheads of a conventional hardware-managed DRAM/NVM hierarchical memory systems. 
         [0082]    7. The DRAM-NVM hierarchical heterogeneous memory system with software-hardware cooperative management according to aspect 5 or 6, wherein an overlap tlb field is designed by using some reserved bits of the TLB entry, and this field is fully utilized to monitor the page access frequency or record the DRAM page number corresponding to an NVM page. 
         [0083]    8. The DRAM-NVM hierarchical heterogeneous memory system with software-hardware cooperative management according to aspect 5 or 6, wherein the monitoring module of the utility-based data fetching module acquires the information of page access frequency and cache utilization from TLB and memory controller; and the fetching threshold is dynamically adjusted by using a fetching threshold runtime adjustment algorithm, to improve cache efficiency and bandwidth usage between the NVM memory and the DRAM cache. 
         [0084]    Practitioners in this field can easily understand this invention. The descriptions in the above are only preferred embodiments of the presented invention, but are not intended to limit the presented invention. Any modification, equivalent replacement and improvement made within the rationale and principle of the presented invention shall fall within the protection scope of the presented invention.