Abstract:
The present disclosure is directed to a primary-controlled high power factor quasi resonant converter. The converter converts an AC power line input to a DC output to power a load, generally a string of LEDs, and may be compatible with phase-cut dimmers. The power input is fed into a transformer being controlled by a power switch. The power switch is driven by a controller having a shaping circuit. The shaping circuit uses a current generator, switched resistor and capacitor to produce a reference voltage signal. The controller drives the power switch based on the voltage reference signal, resulting in a sinusoidal input current in a primary winding of the transformer, resulting in high power factor and low total harmonic distortion for the converter.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to converters and, more particularly, to a control device for quasi-resonant AC/DC flyback converters. 
     2. Description of the Related Art 
     Converters, and particularly offline drivers of LED-based lamps for bulb replacement, are often desired to have a power factor greater than 0.9, low total harmonic distortion (THD) and safety isolation. At the same time, for cost reasons, it is desirable to regulate the output DC current required for proper LED driving without closing a feedback loop. In addition, compatibility with dimmers is becoming more and more important for LED drivers, especially dimmers based on phase-cut technology. 
     High-power-factor (high-PF) flyback converters are able to meet power factor and isolation specifications with a simple and inexpensive power stage. In a high-PF flyback converter there is not an energy reservoir capacitor directly connected to the input rectifier bridge, so that the voltage applied to the power stage is a rectified sinusoid. To achieve high-PF, the input current tracks the input voltage, thus originating a time-dependent input-to-output power flow. As a result, the output current contains a large AC component at twice the main line&#39;s frequency. 
     A quasi-resonant flyback converter has the power switch turn-on synchronized to the instant the transformer demagnetizes (i.e. the secondary current has become zero), normally after an appropriate delay. This allows the turn-on to occur on the valley of the drain voltage ringing that follows the demagnetization, often termed “valley-switching.” Most commonly, peak current mode control is used, so the turn-off of the power switch is determined by the current sense signal reaching the value programmed by the control loop that regulates the output voltage or current. 
     In a flyback converter the input current is the average of the primary current, which flows only during the ON-time of the power switch, resulting in a series of triangles separated by voids corresponding to the OFF-time of the power switch. This “chopping” causes the average value of the primary current to be lower than half the peak value and depend on the mark-space ratio of the triangles. As a result, the input current is no longer proportional to the envelope of the peaks and unlike the envelope, which is sinusoidal, the input current is not sinusoidal. Although a sinusoidal-like shape is maintained, the input current is distorted. This distorted sinusoidal input current results in a flyback converter that fails to achieve low THD or unity power factor. 
       FIG. 1  shows a high-power-factor (high-PF) flyback converter  30  according to the prior art. The hi-PF flyback converter  30  is powered from an AC power line having voltage V ac (θ) and includes an input bridge rectifier  34  having inputs  32  that receive the voltage V ac (θ), a first output connected to ground, and a second output at which the rectifier is configured to produce a rectified sinusoidal voltage V in (θ)=V PK | sin θ| and the current drawn from the power line is sinusoidal-like. 
     On the primary side, the flyback converter  30  also comprises a capacitor C in , which serves as a high-frequency smoothing filter, connected across the output terminals of the bridge rectifier  34 , with the negative end connected to ground, and a voltage divider Ra−Rb. The flyback converter  30  has a transformer  36  with a primary winding L p , connected to the positive terminal of the capacitor C in , and an auxiliary winding L aux  coupled to a resistor R ZCD . A power switch M has its drain terminal connected to the primary winding L p  and its source terminal connected to ground via a sense resistor Rs. The current flowing through the power switch M (i.e. the current flowing through the primary winding L p  when M is ON) can be read as a positive voltage drop across the sense resistor Rs. The primary side of the converter also includes a clamp circuit  37  that clamps leakage inductance of the primary winding L p . 
     On the secondary side, the transformer  36  includes a secondary winding L s , that has one end connected to a secondary ground and the other end connected to the anode of a diode D having a cathode connected to the positive plate of a capacitor C out  that has its negative plate connected to the secondary ground. 
     This flyback converter  30  generates a DC voltage V out  at its output terminals across the capacitor C out  that will supply a load  40 , which is a string of high-brightness LEDs in  FIG. 1 . 
     The flyback converter has a divider block  42  having a first input that receives a signal B(θ), and a second input that receives a signal A(θ) that is a portion of the instantaneous rectified line voltage sensed across the capacitor C in  and brought to pin MULT through the resistor divider Ra−Rb. The divider ratio Rb/(Ra+Rb) will be denoted with K p . 
     The capacitor C T  is assumed to be large enough so that the AC component (at twice the line frequency f L ) of the signal B(θ) is negligible, at least to a first approximation, with respect to its DC component B 0 . 
     The output of the divider block  42  is the division of a rectified sinusoid times a DC level, then still a rectified sinusoid whose amplitude depends on the rms line voltage and the amplitude of the control voltage B 0 ; this will be a reference voltage Vcs REF (θ) for the peak primary current. 
     The signal Vcs REF (θ) is fed to the inverting input of a pulse width modulation comparator  44  that receives at its non-inverting input the voltage Vcs(t, θ), sensed across the sense resistor Rs. The voltage Vcs(t, θ) is proportional to the instantaneous current I p (t, θ) flowing through the primary winding L p  and the power switch M when the switch M is ON. Assuming the power switch M is initially ON, the current through the primary winding L p  will be ramping up and so will the voltage across the sense resistor Rs. When Vcs(t,θ) equals Vcs REF (θ), the PWM comparator  44  resets the SR flip-flop  46  which switches off the power switch M. Therefore, the output of the divider  42 , shaped as a rectified sinusoid, determines the peak value of the current of the primary winding L p . As a result, the peak value of the primary winding current will be enveloped by a rectified sinusoid. 
     After the power switch M has been switched off, the energy stored in the primary winding L p  is transferred by magnetic coupling to the secondary winding L s  and then dumped into the output capacitor C out  and the load  40  until the secondary winding L s  is completely demagnetized. When the secondary winding L s  is demagnetized, the diode D opens and the drain node becomes floating, which was fixed at V in (θ)+V R  while the secondary winding L s  and the diode D were conducting, with V R  being the reflected voltage seen across the primary winding. The voltage at the drain node would tend to eventually reach the instantaneous line voltage V in (θ) through a damped ringing due to its parasitic capacitance that starts resonating with the primary winding L p . The quick drain voltage fall that follows the demagnetization of the transformer  36  is coupled to the pin ZCD of the controller through the auxiliary winding L aux  and the resistor R ZCD . A zero crossing detector (ZCD) block  48  releases a pulse every time it detects a falling edge going below a threshold and this pulse sets the SR flip flop  46  and drives ON the power switch M, starting a new switching cycle. 
     An OR gate  50  between the ZCD block  48  and the set input of the SR flip flop  46  allows the output of a STARTER block  52  to initiate a switching cycle. The STARTER block outputs a signal at power-on when no signal is available on the input of the ZCD block  48  and prevents the converter from getting stuck in case the signal on the input of the ZCD block  48  is lost for any reason. 
     The ZCD block  48  also generates a FW signal that is high during transformer&#39;s demagnetization, as shown in  FIG. 2 , and is used by the control loop  56  to generate the B(θ) signal. 
     Assuming θ∈(0, π), according to the control scheme under consideration the peak envelope of the primary current is given by:
 
 I   pkp (θ)= I   p ( T   ON ,θ)= IPKp  sin θ  (1)
 
     It is worth noticing that this scheme results in a constant ON-time T ON  of the power switch M: 
     
       
         
           
             
               T 
               ON 
             
             = 
             
               
                 Lp 
                 ⁢ 
                 
                   
                     
                       I 
                       PKp 
                     
                     ⁢ 
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     θ 
                   
                   
                     
                       V 
                       PK 
                     
                     ⁢ 
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     θ 
                   
                 
               
               = 
               
                 Lp 
                 ⁢ 
                 
                   
                     I 
                     PKp 
                   
                   
                     V 
                     PK 
                   
                 
               
             
           
         
       
     
     For simplicity, the OFF-time T OFF (θ) of the power switch M will be considered coincident with the time T FW (θ) during which current circulates on the secondary side. In other words, the time interval T R  during which the voltage across the power switch M rings (starting just after T FW (θ), as the current in the secondary winding L s  has gone to zero), until reaching the valley of the ringing will be neglected. This is acceptable as long as T R &lt;&lt;T OFF (θ). 
     The switching period T(θ) is therefore given by:
 
 T (θ)= T   ON   +T   FW (θ)
 
     Considering volt-second balance across the primary winding L p  it is possible to write: 
     
       
         
           
             
               
                 T 
                 FW 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 T 
                 ON 
               
               ⁢ 
               
                 
                   
                     V 
                     PK 
                   
                   ⁢ 
                   sin 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   θ 
                 
                 
                   V 
                   R 
                 
               
             
           
         
       
     
     where V R  is the reflected voltage, i.e. the output voltage V out  times the primary-to-secondary turns ratio n=N p /N s , seen across the primary winding L p  of the transformer  36  in the time interval T FW (θ):
 
 V   R   =n ( V   out   +V   F )
 
     where V F  is the forward drop on the secondary diode D. Therefore:
 
 T (θ)= T   ON (1+ K   v  sin θ)
 
     with K v =V PK /V R . 
     The input current I in  to the converter  30  is found by averaging the current I p (t,θ) in the primary winding L p  over a switching cycle. The current I p (t,θ) is the series of gray triangles in the right-hand side of  FIG. 2  so it is found that: 
     
       
         
           
             
               
                 I 
                 in 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   1 
                   2 
                 
                 ⁢ 
                 
                   
                     I 
                     pkp 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 ⁢ 
                 
                   
                     T 
                     ON 
                   
                   
                     T 
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
               
               = 
               
                 
                   1 
                   2 
                 
                 ⁢ 
                 
                   I 
                   PKp 
                 
                 ⁢ 
                 
                   
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     θ 
                   
                   
                     1 
                     + 
                     
                       
                         K 
                         v 
                       
                       ⁢ 
                       sin 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       θ 
                     
                   
                 
               
             
           
         
       
     
     This equation shows that the input current I in  is not a pure sinusoid: this current is sinusoidal only for K v =0; when K v ≠0, although a sinusoidal-like shape is maintained, the input current is distorted, the higher K v  the higher the distortion. Since K v  cannot be zero (which would require the reflected voltage to tend to infinity), the prior art QR control scheme does not permit zero Total Harmonic Distortion (THD) of the input current nor unity power factor in a flyback converter even in the ideal case. 
       FIG. 3  shows the plots of the THD of the input current and of the power factor versus K v . 
     The regulated DC output current value obtained with this control method is: 
     
       
         
           
             
               I 
               out 
             
             = 
             
               
                 nK 
                 D 
               
               
                 2 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   RsG 
                   M 
                 
                 ⁢ 
                 
                   R 
                   T 
                 
               
             
           
         
       
     
     where K D  is the gain of the divider block  42  and G M  the transconductance of a current generator  54  which produces current I CH (θ). 
     This equation shows that with the control method of  FIG. 1 , which uses only quantities available on its primary side, the DC output current I out  depends only on external, user-selectable parameters (n, Rs) and on internally fixed parameters (G M , R T , K D ) and does not depend on the output voltage V out , nor on the rms input voltage V in  or the switching frequency f sw (θ)=1/T(θ). 
     This control method makes the flyback converter  30  work as a current source. Therefore, even with a chopped AC input voltage—which happens in case the converter is operated through a phase-cut wall dimmer (e.g. leading and trailing edge dimmer as shown in  FIG. 5 )—the converter forces the preset DC output current to the load. 
     In that case, however it would be desirable to reduce the regulation setpoint depending on the dimmer firing angle (1−α) to be compatible with a dimmer: the higher α is, the lower the current set-point should be. This can be realized by modifying the circuit  56  in  FIG. 1  as shown in  FIG. 4 . The sensed input voltage is compared to a threshold voltage V th  in a dimmer comparator  60  and, if it stays below the threshold for a time longer than T ML , it is assumed that the line voltage is missing (because the dimmer is open) and an EN signal goes low. This freezes the state of the power switch M and disconnects both the current generator  54  producing current I CH (θ) and the discharge resistor R T . In this way the voltage across C T  is frozen at the value in the instant when the input voltage goes to zero. 
     The delay T ML  prevents the circuit from being improperly activated near the zero-crossings of the line voltage when this is not chopped. Note also that this delay is unidirectional: as the sensed voltage exceeds the threshold voltage V th  the enable signal EN goes high immediately. 
     The net effect of stopping the charge/discharge activity of the capacitor C T  can be regarded as an average increase of the discharge resistor R T , leading to a reduction of the preset output current I out  inversely proportion to the firing angle of the dimmer: 
     
       
         
           
             
               I 
               out 
             
             = 
             
               
                 
                   nK 
                   D 
                 
                 
                   2 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     RsG 
                     M 
                   
                   ⁢ 
                   
                     R 
                     T 
                   
                 
               
               ⁢ 
               
                 
                   ( 
                   
                     1 
                     - 
                     α 
                   
                   ) 
                 
                 . 
               
             
           
         
       
     
     Real world dimmers have typically a fire angle between 10-20% and 80-90%, and therefore if using the control scheme shown in  FIG. 4 , the minimum/maximum output current setpoint could be in the range of 10-20% and 80-90% respectively. In other words the control method shown in  FIG. 4  cannot meet the typical desired characteristic of a dimmer shown in  FIG. 6 . 
     BRIEF SUMMARY 
     One embodiment of the present disclosure is a quasi-resonant flyback converter having a sinusoidal input current in order to achieve low total harmonic distortion and high power factor. 
     One embodiment of the present disclosure is directed to a control mechanism that enables high power factor (Hi-PF) quasi-resonant (QR) flyback converters with peak current mode control using only quantities available on its primary side able to ideally draw a sinusoidal current from the input source and with an with optimized compatibility to the phase-cut wall dimmers. 
     One embodiment of the present invention is a device for controlling a power transistor of a power stage. The device includes a divider having a first input, a second input and an output, the divider being configured to produce a voltage reference signal. A first current generator configured to produce an output current. A shaper circuit configured to output to the first input of the divider a first signal based on the output current of the first current generator. A bias circuit coupled to the first current generator and configured to output a second signal to the second input of the divider; and a driver circuit having a first input configured to receive the reference signal, and an output configured to drive the power transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  shows a schematic of a primary-controlled Hi-PF QR flyback converter according to the prior art. 
         FIG. 2  shows the waveforms of the circuit in  FIG. 1  during normal operation. 
         FIG. 3  shows the plot of the total harmonic distortion of the input current and the Power Factor obtained with the circuit of  FIG. 1  for different values of K v . 
         FIG. 4  shows the modification of the circuit in the dotted box in  FIG. 1  to reduce the regulation setpoint depending on the dimmer firing angle α, according to the prior art. 
         FIG. 5  shows the typical input voltage waveform with leading-edge and trailing-edge dimmers. 
         FIG. 6  shows the typical desired output LED current characteristic when using dimmer based on phase-cut technology. 
         FIG. 7  shows the principle schematic of a primary-controlled Hi-PF QR flyback converter according to one embodiment the present disclosure. 
         FIG. 8  shows the key waveforms of the circuit in  FIG. 7  during normal operation. 
         FIG. 9  shows an alternate voltage reference circuit with a dimming detector for the circuit of  FIG. 7 . 
         FIG. 10  shows the main waveforms of the circuit in  FIG. 9 . 
         FIG. 11  shows a detailed dimming circuit for the circuit of the  FIG. 9 . 
         FIG. 12  shows the simulation results for the circuit in  FIG. 7  at 265 Vac. 
         FIG. 13  shows the simulation results for the circuit in  FIG. 7  at 90 Vac. 
         FIG. 14  shows the simulation results comparison between the prior art method and the present disclosure according to one embodiment. 
         FIG. 15  shows the simulation results comparison between the prior art method and the present disclosure for I out  output current. 
         FIG. 16  shows the simulation results for the modified circuit in  FIG. 9  at a firing angle (1−α)=0.2. 
         FIG. 17  shows the simulation results comparison between the prior art method and the present disclosure for dimming curves. 
         FIG. 18  shows an alternative embodiment to generate the signal A(θ). 
         FIG. 19  shows an alternative embodiment to generate the signal B(θ). 
         FIG. 20  shows an alternative embodiment of the circuit of  FIG. 7  with a line voltage feed-forward. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 7  shows a hi-PF QR flyback converter  100  according to one embodiment of the present disclosure. On the primary side, the QR flyback converter  100  includes a controller  102 , a bridge rectifier  104  having inputs  106  coupled to an AC power line that supplies an AC voltage V ac , an input capacitor C in , a voltage divider R a −R b  coupled to the bridge rectifier  104 , a primary winding L p  and an auxiliary winding L aux  of a transformer  108 , power switch M coupled to the transformer  108  and controlled by controller  102 , sensing resistor R s  coupled to the power switch M and controller  102 , a resistor R ZCD  coupled to the auxiliary winding L aux , and a clamp circuit  109  connected across the primary winding L p . 
     On the secondary side of the converter  100 , a secondary winding L s  of the transformer  108  has one end connected to a secondary ground and the other end connected to the anode of a diode D having the cathode connected to the positive plate of a capacitor C out  that has its negative plate connected to the secondary ground. The converter  100  provides an output voltage V out  that supplies power to a load  110 , which in  FIG. 7  is a set of LEDs, although other loads could be supplied by the converter  100 . 
     The controller  102  has a reference voltage circuit  116  that is configured to produce a reference voltage V CSREF  and includes a bias circuit  118  and a shaper circuit  120 . The controller  102  also includes a driver circuit  121  having a PWM comparator  122 , an SR flip-flop  124 , an OR gate  126 , and a driver  127  configured to drive the power switch M. The PWM comparator  122  includes an inverting input that receives the reference voltage V CSREF , a non-inverting input that receives a sense voltage V CS  from the sense resistor R s , and an output that provide a reset signal to a reset input R of the flip-flop  124 . The flip-flop  124  also includes a set input S, coupled to an output of the OR gate  126 , and an output that is coupled to an input of the driver  127 . The OR gate  126  also has first and second inputs coupled to respective outputs of a starter block  128  and a ZCD block  130 . The OR gate  126  provides a set signal to the set input S of the SR flip flop when the ZCD block  130  detects a falling edge go below a threshold, or when the starter block  128  produces a start signal as discussed above. 
     The reference voltage circuit  116  has a bias circuit  118  and a shaper circuit  120 . The shaper circuit  120  has a first current generator  140 , a resistor R t1  coupled to an output of the first current generator  140 , a switch  132  that switchably couples the resistor R t1  to ground, and a capacitor C t1  coupled between the output of the current generator  140  and ground. The first current generator  140  has an input coupled to a supply terminal Vcc and a control terminal coupled to the voltage divider R a −R b  via the pin MULT and produces a current I CH1 (θ). The switch  132  is controlled by the output Q of the flip-flop  124  and thereby connects the capacitor C t1  in parallel with the switched resistor R t1  when the power switch M is ON. 
     The bias circuit  118  includes a second current generator  142  having an input coupled to the supply terminal Vcc, a control terminal coupled to the output of the first current generator  140 , and an output at which the second current generator produces a current I CH (θ). A second switched resistor R t  is switchably coupled to the output of the second current generator  142  by a switch  134  configured to connect the resistor R t  to the second current generator  142  under the control of the signal FW provided by the ZCD block  130 . The signal FW is high when the current is flowing in the secondary winding L s . Another switch  144  is coupled to the output of the second current generator  142  and is configured to connect the output of the second current generator  142  to ground when the ZCD block  130  under control of a signal  FW  that is an inverted version of the signal FW. 
     The reference voltage circuit  116  also includes a divider block  146  having a first input that receives a signal A(θ) from the shaper circuit  120 , a second input that receives a signal B(θ) from the bias circuit  118 , and an output at which the divider provides the reference voltage V CSREF . 
     The signal A(θ) is generated by the first current generator  140  acting on the switched resistor R t1  and capacitor C t1 . The current I CH1 (θ) produced by the current generator  140  is proportional to a rectified input voltage V in  produced at the voltage divider R a −R b . 
     The resistor R t1  is connected in parallel to the capacitor C t1  by the switch  132  when the signal Q of the SR flip flop  124  is high, i.e. during the on-time of the power switch M, and is disconnected when Q is low, i.e. during the off-time of the power switch M. The voltage developed across the capacitor C t1  is A(θ) and is fed to the first input of the divider block  146 . 
     The current I ch1 (θ) provided by the current generator  140  can be expressed as:
 
 I   ch1 (θ)= g   m1   K   p ( V   PK  sin θ)
 
     where g m1  is the current-to-voltage gain of the first current generator  140 . 
     An assumption is that T(θ)&lt;&lt;R t1  C t1 &lt;&lt;1/f L . In this way, the switching frequency ripple across the capacitor C t1  is negligible and I ch1 (θ) can be considered constant within each switching cycle. 
     The A(θ) voltage developed across C t1  by charge balance is: 
     
       
         
           
             
               A 
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   R 
                   
                     t 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 ⁢ 
                 
                   
                     I 
                     
                       ch 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 ⁢ 
                 
                   
                     T 
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     
                       T 
                       ON 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
               
               = 
               
                 
                   R 
                   
                     t 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 ⁢ 
                 
                   g 
                   
                     m 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 ⁢ 
                 
                   
                     K 
                     p 
                   
                   ⁡ 
                   
                     ( 
                     
                       
                         V 
                         PK 
                       
                       ⁢ 
                       sin 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       θ 
                     
                     ) 
                   
                 
                 ⁢ 
                 
                   
                     T 
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     
                       T 
                       ON 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
               
             
           
         
       
     
     The generation of the other input signal B(θ) to the divider block  146  is similar to that of the B(θ) of  FIG. 1 . The current I CH (θ) provided by the second current generator  142  and used to generate the B(θ) signal, can be expressed as:
 
 I   CH (θ)= G   M   A (θ)
 
     where G M  is the current-to-voltage gain of the second current generator  142 . 
     Now considering the C T  by charge balance, it is possible to find the voltage B(θ) developed across the capacitor C T : 
     
       
         
           
             
               B 
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 G 
                 M 
               
               ⁢ 
               
                 R 
                 T 
               
               ⁢ 
               
                 g 
                 
                   m 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
               ⁢ 
               
                 R 
                 
                   t 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
               ⁢ 
               
                 
                   K 
                   p 
                 
                 ⁡ 
                 
                   ( 
                   
                     
                       V 
                       PK 
                     
                     ⁢ 
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     θ 
                   
                   ) 
                 
               
               ⁢ 
               
                 
                   
                     T 
                     FW 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 
                   
                     T 
                     ON 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
               
             
           
         
       
     
     The capacitor C T  is assumed to be large enough so that the AC component (at twice the line frequency f L ) of the signal B(θ) is negligible with respect to its DC component B 0 , which can be written as: 
     
       
         
           
             
               B 
               0 
             
             = 
             
               
                 
                   B 
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 _ 
               
               = 
               
                 
                   
                     1 
                     π 
                   
                   ⁢ 
                   
                     G 
                     M 
                   
                   ⁢ 
                   
                     R 
                     T 
                   
                   ⁢ 
                   
                     g 
                     
                       m 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                     R 
                     
                       t 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                     K 
                     p 
                   
                   ⁢ 
                   
                     V 
                     PK 
                   
                   ⁢ 
                   
                     
                       ∫ 
                       0 
                       π 
                     
                     ⁢ 
                     
                       sin 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       θ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         
                           
                             T 
                             FW 
                           
                           ⁡ 
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         
                           
                             T 
                             ON 
                           
                           ⁡ 
                           
                             ( 
                             θ 
                             ) 
                           
                         
                       
                       ⁢ 
                       
                         ⅆ 
                         θ 
                       
                     
                   
                 
                 = 
                 
                   
                     
                       G 
                       M 
                     
                     ⁢ 
                     
                       R 
                       T 
                     
                     ⁢ 
                     
                       g 
                       
                         m 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     ⁢ 
                     
                       R 
                       
                         t 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     ⁢ 
                     
                       K 
                       p 
                     
                     ⁢ 
                     
                       V 
                       PK 
                     
                     ⁢ 
                     
                       K 
                       V 
                     
                   
                   2 
                 
               
             
           
         
       
     
     Considering the voltage-second balance for transformer  108 , the primary on time T ON (θ) and secondary on time T FW (θ) can be expressed by the following relationship: 
     
       
         
           
             
               
                 
                   T 
                   FW 
                 
                 ⁡ 
                 
                   ( 
                   θ 
                   ) 
                 
               
               
                 
                   T 
                   ON 
                 
                 ⁡ 
                 
                   ( 
                   θ 
                   ) 
                 
               
             
             = 
             
               
                 K 
                 v 
               
               ⁢ 
               sin 
               ⁢ 
               
                   
               
               ⁢ 
               θ 
             
           
         
       
     
     The voltage reference Vcs REF (θ) is therefore: 
     
       
         
           
             
               
                 Vcs 
                 REF 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   
                     K 
                     D 
                   
                   ⁢ 
                   
                     
                       A 
                       ⁡ 
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     
                       B 
                       ⁡ 
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                 
                 ≈ 
                 
                   
                     K 
                     D 
                   
                   ⁢ 
                   
                     
                       A 
                       ⁡ 
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     
                       B 
                       0 
                     
                   
                 
               
               = 
               
                 
                   K 
                   D 
                 
                 ⁢ 
                 
                   2 
                   
                     
                       G 
                       M 
                     
                     ⁢ 
                     
                       R 
                       T 
                     
                     ⁢ 
                     
                       K 
                       v 
                     
                   
                 
                 ⁢ 
                 sin 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 θ 
                 ⁢ 
                 
                   
                     T 
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     
                       T 
                       ON 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
               
             
           
         
       
     
     where K D  is the gain of the divider block  146  and it is dimensionally a voltage. Considering that the peak primary current I pkp (θ) can be expressed as: 
     
       
         
           
             
               
                 I 
                 pkp 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   Vcs 
                   REF 
                 
                 ⁡ 
                 
                   ( 
                   θ 
                   ) 
                 
               
               Rs 
             
           
         
       
     
     The input current can be expressed as: 
     
       
         
           
             
               
                 I 
                 IN 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 1 
                 2 
               
               ⁢ 
               
                 
                   I 
                   PKP 
                 
                 ⁡ 
                 
                   ( 
                   θ 
                   ) 
                 
               
               ⁢ 
               
                 
                   
                     T 
                     ON 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 
                   T 
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 I 
                 IN 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   K 
                   D 
                 
                 
                   
                     G 
                     M 
                   
                   ⁢ 
                   
                     R 
                     T 
                   
                   ⁢ 
                   
                     K 
                     V 
                   
                 
               
               ⁢ 
               sin 
               ⁢ 
               
                   
               
               ⁢ 
               θ 
               ⁢ 
               
                 1 
                 
                   R 
                   S 
                 
               
             
           
         
       
     
     This results in a sinusoidal input current in a constant-current primary-controlled Hi-PF QR flyback converter  100 . 
     Considering that the secondary current is n=Np/Ns times the primary current, the peak secondary current I pks (θ) can be calculated as: 
     
       
         
           
             
               
                 I 
                 pks 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 nK 
                 D 
               
               ⁢ 
               
                 2 
                 
                   
                     G 
                     M 
                   
                   ⁢ 
                   
                     R 
                     T 
                   
                   ⁢ 
                   
                     K 
                     v 
                   
                 
               
               ⁢ 
               sin 
               ⁢ 
               
                   
               
               ⁢ 
               θ 
               ⁢ 
               
                 
                   T 
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 
                   
                     T 
                     ON 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
               
               ⁢ 
               
                 
                   1 
                   
                     R 
                     S 
                   
                 
                 . 
               
             
           
         
       
     
     Since the cycle-by-cycle secondary current Is(t,θ) is the series of triangles shown in left-hand side of  FIG. 8 , its average value in a switching cycle is: 
     
       
         
           
             
               
                 I 
                 o 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   1 
                   2 
                 
                 ⁢ 
                 
                   
                     I 
                     pks 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 ⁢ 
                 
                   
                     
                       T 
                       FW 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     T 
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
               
               = 
               
                 
                   
                     nK 
                     D 
                   
                   
                     
                       G 
                       M 
                     
                     ⁢ 
                     
                       R 
                       T 
                     
                     ⁢ 
                     
                       K 
                       v 
                     
                   
                 
                 ⁢ 
                 sin 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 θ 
                 ⁢ 
                 
                   
                     
                       T 
                       FW 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     
                       T 
                       ON 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
                 ⁢ 
                 
                   
                     1 
                     
                       R 
                       S 
                     
                   
                   . 
                 
               
             
           
         
       
     
     The DC output current I out  is the average of I o (θ) over a line half-cycle: 
     
       
         
           
             
               I 
               out 
             
             = 
             
               
                 
                   
                     I 
                     o 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 _ 
               
               = 
               
                 
                   1 
                   π 
                 
                 ⁢ 
                 
                   
                     ∫ 
                     0 
                     π 
                   
                   ⁢ 
                   
                     
                       
                         nK 
                         D 
                       
                       
                         
                           G 
                           M 
                         
                         ⁢ 
                         
                           R 
                           T 
                         
                         ⁢ 
                         
                           K 
                           v 
                         
                         ⁢ 
                         
                           R 
                           S 
                         
                       
                     
                     ⁢ 
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     θ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       
                         
                           T 
                           FW 
                         
                         ⁡ 
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                           ON 
                         
                         ⁡ 
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                     ⁢ 
                     
                       
                         ⅆ 
                         θ 
                       
                       . 
                     
                   
                 
               
             
           
         
       
     
     Finally, the average output current is: 
     
       
         
           
             
               I 
               out 
             
             = 
             
               
                 
                   nK 
                   D 
                 
                 
                   2 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     G 
                     M 
                   
                   ⁢ 
                   
                     R 
                     T 
                   
                   ⁢ 
                   
                     R 
                     S 
                   
                 
               
               . 
             
           
         
       
     
     The previous expression shows that the circuit of  FIG. 7  has a DC output current Iout that depends only on external, user-selectable parameters (n, Rs) and on internally fixed parameters (G M , R T , K D ) and does not depend on the output voltage Vout, nor on the RMS input voltage Vin or the switching frequency f SW (θ)=1/T(θ). 
     Therefore, it is possible to conclude that the converter  100  of  FIG. 7 , in addition to providing ideally unity power factor and zero harmonic distortion of the input current, also provides a regulated Iout using only quantities available on the primary side. 
       FIGS. 12 and 13  show simulation results of the signals of  FIG. 7  with Vin being 265 VAC and 90 VAC respectively, including A(A), B(θ), Iout, Iin, V CSREF , and the THD of the circuit. It is worth noticing the very low distortion level of the input current (around 3.3% at V in =90 Vac, around 3.8% at V in =265 Vac), due to the input EMI filter and the non-idealities considered both in the controller  102  and the bridge rectifier  104 , transformer  108  and power switch M. 
       FIG. 8  illustrates several of the waveforms of converter  100  of  FIG. 7 . On the left-hand side are the waveforms on a switching period time scale, on the right-hand side the waveforms on a line cycle time scale. 
     In  FIG. 14  are shown the simulation results comparison between the prior art converter  30  and the presently disclosed converter  100  in terms of THD (left) and PF (right).  FIG. 15  shows the simulation results comparison in terms of output current regulation. 
       FIG. 9  is a reference voltage circuit  118 ′ according to one embodiment of the present disclose and can be employed instead of the reference voltage circuit  118  of  FIG. 7  when it is desired to obtain the dimming curve shown in  FIG. 6 . The reference voltage circuit  118 ′ includes the switches  134 ,  144 , second current generator  142 , resistor R T , and capacitor C T  of the reference voltage generator  118  of  FIG. 7 . Unlike the reference voltage generator  118  of  FIG. 7 , the reference voltage circuit  118 ′ includes a phase angle detector  150  having a comparator  151 , a delay block  152 , and an AND gate  153 . The comparator  151  has an inverting input that receives a sensed input voltage from a dimmer, a non-inverting input that receives a voltage threshold V th , and an output at which the comparator produces a signal a based on a comparison of the sensed input voltage with the voltage threshold V th . The delay block  152  adds a masking time delay T MASK  and the AND gate  153  outputs an α MASK  signal. 
     The reference voltage circuit  118 ′ also includes a dimming circuit  154  that includes a dimming current generator  155 , a switch  156 , and a gain block (G DIM )  157 . An extra current L dim  is added on the B(θ) signal from dimming current generator  155 . This current L dim  is proportional to the signal B(θ) and, as shown in  FIG. 10 , is added only during a part of the dimmer off-time (basically only when α MASK  signal is high and closes the switch  156 ). 
     The reference voltage circuit  118 ′ further includes inverters  158 ,  159 , a switch  160 , and another AND gate  161 . The inverter  158  is connected between an output of the AND gate  153  and a control terminal of the switch  160 , and thereby, controls the switch  160  based on an inverted version of the α MASK  signal output by the phase angle detection circuit  150 . The inverter  159  is connected between an output of the AND gate  161  and a control terminal of the switch  144 . The AND gate  161  has first and second inputs connected respectively to the output of the ZCD block  130  that provides the FW signal and the output of the inverter  158  that provides the inverted version of the α MASK  signal. The output of the AND gate  161  is also connected to a control terminal of the switch  134 , so the AND gate  161  opens one of the switches  134 ,  144  while closing the other one of the switches  134 ,  144 , and vice versa, depending on the FW signal output by the ZCD block  130  and on the inverted version of the α MASK  signal provided by the inverter  158 . 
     The I DIM  current generator  155  is added on the C T  capacitor, increasing the B(θ) signal in function of the dimmer firing angle, resulting in a lower DC output current. In other words, the I DIM  current generator  155  increases the equivalent R T  discharging resistor based on the dimmer firing angle. 
     Considering the C T  charge balance, it is possible to find the equivalent discharging resistor: 
     
       
         
           
             
               R 
               Tequivalent 
             
             = 
             
               
                 R 
                 T 
               
               ⁡ 
               
                 [ 
                 
                   
                     R 
                     DIM 
                   
                   
                     
                       
                         R 
                         DIM 
                       
                       ⁡ 
                       
                         ( 
                         
                           1 
                           - 
                           
                             α 
                             MASK 
                           
                         
                         ) 
                       
                     
                     - 
                     
                       
                         R 
                         T 
                       
                       ⁢ 
                       
                         α 
                         MASK 
                       
                     
                   
                 
                 ] 
               
             
           
         
       
     
     The DC output current is therefore: 
     
       
         
           
             
               
                 I 
                 out 
               
               ⁡ 
               
                 [ 
                 
                   α 
                   MASK 
                 
                 ] 
               
             
             = 
             
               
                 
                   nK 
                   D 
                 
                 
                   2 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     R 
                     S 
                   
                   ⁢ 
                   
                     G 
                     M 
                   
                   ⁢ 
                   
                     R 
                     T 
                   
                 
               
               * 
               
                 [ 
                 
                   
                     
                       
                         R 
                         DIM 
                       
                       ⁡ 
                       
                         ( 
                         
                           1 
                           - 
                           
                             α 
                             MASK 
                           
                         
                         ) 
                       
                     
                     - 
                     
                       
                         R 
                         T 
                       
                       ⁢ 
                       
                         α 
                         MASK 
                       
                     
                   
                   
                     R 
                     DIM 
                   
                 
                 ] 
               
             
           
         
       
     
     where 
               α   MASK     =     α   -       T   MASK     T             
and T is the line period.
 
     The previous expression shows that the DC output current depends on the dimmer firing angle (1−α) with a relationship that has a high slope, and can be programmed through the R DIM  resistor. Because of the T MASK  delay time, the DC output current does not change until the dimmer off-time is higher than T MASK . 
       FIG. 11  shows the dimming circuit  154  of  FIG. 9  according to one embodiment. The I DIM  current generator  155  is implemented using a control transistor  162  and a current mirror that includes a diode-connected, bipolar first mirror transistor  163  and a bipolar second mirror transistor  164  having respective bases connected to each other and respective emitters connected to the supply terminal Vcc. The dimming circuit  154  also includes a resistor R DIM  and the switch  156  connected in series with the control transistor  162  and the first mirror transistor  163  between the supply terminal Vcc and ground. The switch  156  is implemented as an NPN bipolar transistor having its collector connected to the resistor R DIM , its emitter connected to ground, and its base connected to the output of the phase angle detector  150  to receive the α MASK  signal. The gain block  157  is implement using an amplifier  165  having its non-inverting input connected to receive the B(θ) signal, its inverting input connected to a node between the emitter of the control transistor  162  and the resistor R DIM , and its output connected to the base of the control transistor  162 . 
       FIG. 16  shows simulation results of the circuit of  FIG. 9  implemented in the QR converter of  FIG. 7 . In  FIG. 17  is shown a comparison between the prior art converter  30  and the present disclosure converter  100  modified with the circuit of  FIG. 9  in terms of dimming curves (output current versus dimmer firing angle). 
     Shown in  FIG. 18  is an alternative implementation of a shaper circuit  170 , which could be used in place of the shaper circuit  120  of  FIG. 7  to generate the A(θ) signal. The shaper circuit  170  of  FIG. 18  includes the resistor R t1 , capacitor C t1 , and switch  132  of the shaper circuit  120  of  FIG. 7  and also includes the resistive voltage divider R a −R b  of  FIG. 7 . The shaper circuit  170  also has a current generator  172  connected between the supply terminal Vcc and the resistor R t1  and configured to supply a current I ref1 . A multiplier block  174  has a first input connected to a node between the output of the current generator  172  and resistor R t1  and configured to receive a signal A 1 (θ), a second input connected to the mid-point of the voltage divider R a −R b  and configured to receive a signal A 2 (θ) from the voltage divider R a −R b , and an output configured to supply the A(θ) signal. Considering the C t1  charge-balance, the A 1 (θ) voltage developed across the capacitor C t1  is: 
     
       
         
           
             
               
                 I 
                 
                   ref 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
               ⁢ 
               
                 T 
                 ⁡ 
                 
                   ( 
                   θ 
                   ) 
                 
               
             
             = 
             
               
                 
                   A 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                   ⁢ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 
                   R 
                   
                     t 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
               
               ⁢ 
               
                 
                   T 
                   ON 
                 
                 ⁡ 
                 
                   ( 
                   θ 
                   ) 
                 
               
             
           
         
       
     
     where I ref1  is a constant current produced by the current generator  172 . 
     Considering that A 2 (θ)=K p  (V PK  sin θ), the A(θ) signal results: 
     
       
         
           
             
               A 
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 K 
                 M 
               
               ⁢ 
               
                 I 
                 
                   ref 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
               ⁢ 
               
                 R 
                 
                   t 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
               ⁢ 
               
                 K 
                 P 
               
               ⁢ 
               
                 V 
                 PK 
               
               ⁢ 
               sin 
               ⁢ 
               
                   
               
               ⁢ 
               θ 
               ⁢ 
               
                 
                   T 
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 
                   
                     T 
                     ON 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
               
             
           
         
       
     
     Where K M  is the gain of the multiplier block  174 . Comparing the equation for the A(θ) signal produced by the shaper circuit  120  of  FIG. 7  with the above equation for the A(θ) signal produced by the shaper circuit  170  of  FIG. 18 , the implementation shown in  FIG. 18  is equivalent to the implementation shown in  FIG. 7  if the multiplier gain, K M , is: 
     
       
         
           
             
               K 
               M 
             
             = 
             
               
                 g 
                 
                   m 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
               
                 I 
                 
                   ref 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
             
           
         
       
     
     Shown in  FIG. 19  is alternative implementation of a bias circuit  180 , which could be used in place of the bias circuit  118  of  FIG. 7  to generate the B(θ) signal. The bias circuit  180  has an amplifier  182  configured to receive the A(θ) signal and produce a signal A 1 (θ). The amplifier  182  could be configured to receive the A(θ) signal from the shaper circuit  120  of  FIG. 2 , the shaper circuit  170  of  FIG. 18 , or a shaper circuit according to an alternate embodiment in view of the above discussion. Also, the amplifier  182  could be implemented by the controlled current generator  140 , which produces the current I ch1 (θ) proportionally to the portion of the input voltage V in (θ) at the midpoint of the voltage divider R a −R b , or an alternate amplifier could be employed. A first switch  184  is coupled between the amplifier  182  and the resistor R t  and a configured to connect the amplifier  182  to the resistor R t  based on the FW signal produced by the ZCD block  130 . A second switch  186  is coupled between the first switch  184  and ground, and is configured to connect the resistor R t  to ground based on the inverted signal  FW . 
     One can determine the B(θ) voltage by considering the following C T  charge-balance: 
     
       
         
           
             
               
                 
                   
                     
                       A 
                       1 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   - 
                   
                     B 
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
                 
                   R 
                   T 
                 
               
               ⁢ 
               
                 
                   T 
                   FW 
                 
                 ⁡ 
                 
                   ( 
                   θ 
                   ) 
                 
               
             
             = 
             
               
                 
                   B 
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 
                   R 
                   T 
                 
               
               ⁢ 
               
                 
                   T 
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 . 
               
             
           
         
       
     
     Considering that A 1 (θ)=K A(θ), the B(θ) signal is: 
     
       
         
           
             
               B 
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 KA 
                 ⁡ 
                 
                   ( 
                   θ 
                   ) 
                 
               
               ⁢ 
               
                 
                   
                     T 
                     FW 
                   
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
                 
                   T 
                   ⁡ 
                   
                     ( 
                     θ 
                     ) 
                   
                 
               
             
           
         
       
     
     where K is the voltage gain of the amplifier  182 . 
     In  FIG. 20  is shown an alternative embodiment of a controller  188 , which could be employed in place of the controller  102  of  FIG. 7  to control the power switch M. The controller  188  is identical to the controller  102  of  FIG. 7  except that the controller  188  includes a shaper circuit  189  instead of the shaper circuit  120 . The shaper circuit  189  is configured to implement a line voltage feed-forward in order to eliminate the dependence of the signal B(θ) on the input voltage Vin. The shaper circuit  189  includes the same switch  132 , current generator  140 , resistor R t1 , and capacitor C t1  as in the shaper circuit  120  of  FIG. 7 . In addition, the shaper circuit  189  includes a feed-forward circuit  190 , which is composed of a peak detector  192 , a quadratic voltage divider  194 , and a multiplier  196 . The peak detector  192  detects a voltage peak of the portion of the rectified input voltage received from the midpoint of the voltage divider R a −R b  and provides an output signal representative of that peak. The quadratic voltage divider  194  receives the output signal from the peak detector  192  and produces a feed-forward signal FF equal to: 
     
       
         
           
             FF 
             = 
             
               
                 1 
                 
                   
                     ( 
                     
                       
                         K 
                         P 
                       
                       ⁢ 
                       
                         V 
                         PK 
                       
                     
                     ) 
                   
                   2 
                 
               
               . 
             
           
         
       
     
     The multiplier  196  multiplies the feed-forward signal FF from the quadratic divider  194  to the signal A(θ) produced at the intermediate node between the current generator  140  and the capacitor C t1  to produce a signal A 1 (θ): 
     
       
         
           
             
               
                 A 
                 1 
               
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   
                     g 
                     
                       m 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                     R 
                     
                       t 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
                 
                   
                     K 
                     P 
                   
                   ⁢ 
                   
                     V 
                     PK 
                   
                 
               
               ⁢ 
               sin 
               ⁢ 
               
                   
               
               ⁢ 
               θ 
               ⁢ 
               
                 
                   
                     T 
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     
                       T 
                       ON 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
                 . 
               
             
           
         
       
     
     The current I CH (θ) provided by the current generator  142 , used to generate the B(θ) signal, can be then expressed as:
 
 I   CH (θ)= G   M   A 1(θ).
 
     Now considering the C T  charge-balance it is possible to find the voltage B(θ) developed across the capacitor C T : 
     
       
         
           
             
               B 
               ⁡ 
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 G 
                 M 
               
               ⁢ 
               
                 R 
                 T 
               
               ⁢ 
               
                 
                   
                     g 
                     
                       m 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                     R 
                     
                       t 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
                 
                   
                     K 
                     P 
                   
                   ⁢ 
                   
                     V 
                     PK 
                   
                 
               
               ⁢ 
               sin 
               ⁢ 
               
                   
               
               ⁢ 
               θ 
               ⁢ 
               
                 
                   
                     
                       T 
                       FW 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     
                       T 
                       ON 
                     
                     ⁡ 
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
                 . 
               
             
           
         
       
     
     Finally the DC component of the signal B(θ) is: 
     
       
         
           
             
               B 
               0 
             
             = 
             
               
                 
                   
                     G 
                     M 
                   
                   ⁢ 
                   
                     R 
                     T 
                   
                   ⁢ 
                   
                     g 
                     
                       m 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                     R 
                     
                       t 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
                 
                   2 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     K 
                     P 
                   
                 
               
               ⁢ 
               
                 1 
                 
                   V 
                   R 
                 
               
             
           
         
       
     
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.