Abstract:
The present invention provides a data reading device capable of preventing erroneous writing during an operation of reading data from a non-volatile memory element. The data reading device includes a dummy reading circuit provided with a non-volatile memory element, the writing voltage of which is lower than that of a non-volatile memory element of a data reading circuit, and a state detection circuit that detects a written state of the non-volatile memory element of the dummy reading circuit. Upon detection of erroneous writing to the non-volatile memory element of the dummy reading circuit during a data reading operation, the data reading operation is immediately terminated.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2013-254350 filed on Dec. 9, 2013, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a data reading device that reads out data from a non-volatile memory element in a semiconductor device. 
         [0004]    2. Background Art 
         [0005]      FIG. 7  is a circuit diagram of a data reading device that reads out data from a non-volatile memory element. 
         [0006]    A data reading circuit  30  includes a PMOS transistor  31 , a non-volatile memory element  32 , a PMOS transistor  33 , an NMOS transistor  34 , and a latch circuit composed of inverter circuits  35  and  36 . 
         [0007]    The data reading circuit  30  reads out data from the non-volatile memory element  32  by performing an operation described below. 
         [0008]    First, a signal Φ 02  goes to a high level, causing the NMOS transistor  34  to turn on. The latch circuit composed of the inverter circuits  35  and  36  is reset, and an output terminal DOUT goes to a low level. Thereafter, the signal Φ 02  goes to the low level and the NMOS transistor  34  turns off. Then, a signal Φ 01  goes to the low level and the PMOS transistors  31  and  33  turn on. 
         [0009]    In a depression state in which data has been written to the non-volatile memory element  32 , the on-current of the non-volatile memory element  32  causes the latch circuit to be inverted to the high level, and the output terminal DOUT is retained at the high level. 
         [0010]    On the other hand, in an enhancement state in which no data has been written to the non-volatile memory element  32 , the output terminal DOUT is maintained at the low level (refer to, for example, Patent Document 1). 
         [0011]    The potential state around the non-volatile memory element  32  remains the same at the time of reading data and at the time of writing data. 
         [0012]    [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-192039 
         [0013]    In the data reading circuit  30 , the potential state around the non-volatile memory element  32  remains the same at the time of reading data and at the time of writing data. Hence, there has been a danger that erroneous writing to the non-volatile memory element  32  occurs if a high voltage of static electricity or the like is applied to a supply terminal during a data reading operation. 
       SUMMARY OF THE INVENTION 
       [0014]    The present invention has been devised to solve the problem described above, and it is an object of the invention to achieve a data reading device that minimizes the possibility of erroneous writing. 
         [0015]    To this end, a data reading device in accordance with the present invention includes a dummy reading circuit provided with a non-volatile memory element, the writing voltage of which is lower than that of the non-volatile memory element of a data reading circuit, and a state detection circuit that detects a written state of the non-volatile memory element of the dummy reading circuit. The data reading device is adapted to immediately terminate a data reading operation upon detection of the occurrence of erroneous writing to the non-volatile memory element of the dummy reading circuit while data is being read out. 
         [0016]    The data reading device in accordance with the present invention makes it possible to prevent erroneous writing of data to a non-volatile memory element even if a high voltage of static electricity or the like is applied while data is being read out. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a circuit diagram illustrating a data reading device according to a first embodiment; 
           [0018]      FIG. 2  is a timing chart illustrating an operation of the data reading device according to the first embodiment; 
           [0019]      FIG. 3  is another timing chart illustrating the operation of the data reading device according to the first embodiment; 
           [0020]      FIG. 4  is a circuit diagram of a data reading device according to a second embodiment; 
           [0021]      FIG. 5  is a timing chart illustrating an operation of the data reading device according to the second embodiment; 
           [0022]      FIG. 6  is a circuit diagram illustrating another example of the data reading device; and 
           [0023]      FIG. 7  is a circuit diagram illustrating a conventional data reading device. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       [0024]      FIG. 1  is a circuit diagram illustrating a data reading device according to a first embodiment. 
         [0025]    The data reading device has a data reading unit  300  and an erroneous writing prevention circuit  600 . The data reading unit  300  is composed of data reading circuits  30 A,  30 B. The data reading circuit  30 A includes PMOS transistors  31 A,  33 A, a non-volatile memory element  32 A, an NMOS transistor  34 A, and a latch circuit composed of inverter circuits  35 A,  36 A. The data reading circuit  30 B includes PMOS transistors  31 B,  33 B, a non-volatile memory element  32 B, an NMOS transistor  34 B, and a latch circuit composed of inverter circuits  35 B,  36 B. 
         [0026]    The erroneous writing prevention circuit  600  includes a dummy reading circuit  40 A, a state detection circuit  50 A, and OR circuits  61 ,  62 . 
         [0027]    The dummy reading circuit  40 A, which has the same circuit configuration as that of the data reading circuit  30 A, includes PMOS transistors  41 A,  43 A, a non-volatile memory element  42 A, an NMOS transistor  44 A, and a latch circuit composed of inverter circuits  45 A,  46 A. The initial state of the non-volatile memory element  42 A is an enhancement state in which no data has been written. The PMOS transistors  41 A,  43 A and the non-volatile memory element  42 A are adapted to be written more easily than the PMOS transistors  31 A,  33 A and the non-volatile memory element  32 A. For example, the W/L ratios of the PMOS transistors  41 A,  43 A and the non-volatile memory element  42 A are set to be larger than the W/L ratios of the PMOS transistors  31 A,  33 A and the non-volatile memory element  32 A. 
         [0028]    The state detection circuit  50 A includes PMOS transistors  51 A,  53 A,  58 A,  59 A, a non-volatile memory element  52 A, inverter circuits  55 A,  56 A,  57 A, and an NMOS transistor  54 A. 
         [0029]    The elements of the data reading circuit  30 A are connected as described below. The source of the PMOS transistor  31 A is connected to a supply terminal VDD, the gate thereof is connected to a node N5, and the drain thereof is connected to the source of the non-volatile memory element  32 A. The gate of the non-volatile memory element  32 A is floating and the drain thereof is connected to the source of the PMOS transistor  33 A. The gate of the PMOS transistor  33 A is connected to the node N5, and the drain thereof is connected to a node DOUTA. The source of the NMOS transistor  34 A is connected to a supply terminal VSS, and the drain thereof is connected to the node DOUTA. The input terminal of the inverter circuit  35 A is connected to an output terminal of the inverter circuit  36 A, and the output terminal thereof is connected to the node DOUTA and the input terminal of the inverter circuit  36 A. A signal Φ 02  is input to the gate of the NMOS transistor  34 A. 
         [0030]    The elements of the data reading circuit  30 B are connected as described below. The source of the PMOS transistor  31 B is connected to the supply terminal VDD, the gate thereof is connected to the node N5, and the drain thereof is connected to the source of the non-volatile memory element  32 B. The gate of the non-volatile memory element  32 B is floating and the drain thereof is connected to the source of the PMOS transistor  33 B. The gate of the PMOS transistor  33 B is connected to the node N5, and the drain thereof is connected to a node DOUTB. The source of the NMOS transistor  34 B is connected to the supply terminal VSS, and the drain thereof is connected to the node DOUTB. The input terminal of the inverter circuit  35 B is connected to an output terminal of the inverter circuit  36 B, and the output terminal thereof is connected to the node DOUTB and the input terminal of the inverter circuit  36 B. The signal Φ 02  is input to the gate of the NMOS transistor  34 B. 
         [0031]    The elements of the dummy reading circuit  40 A are connected as described below. The source of the PMOS transistor  41 A is connected to the supply terminal VDD, the gate thereof is connected to a node N3, and the drain thereof is connected to the source of the non-volatile memory element  42 A. The gate of the non-volatile memory element  42 A is connected to the gate of the non-volatile memory element  52 A of the state detection circuit  50 A, and the drain thereof is connected to the source of the PMOS transistor  43 A. The gate of the PMOS transistor  43 A is connected to the node N3 and the drain is connected to a node N4. The source of the NMOS transistor  44 A is connected to the supply terminal VSS, and the drain thereof is connected to the node N4. The input terminal of the inverter circuit  45 A is connected to the output terminal of the inverter circuit  46 A, and the output terminal thereof is connected to the N4 and the input terminal of the inverter circuit  46 A. The signal Φ 02  is input to the gate of the NMOS transistor  44 A. 
         [0032]    The elements of the state detection circuit  50 A are connected as described below. The source of the PMOS transistor  51 A is connected to the supply terminal VDD, and the drain thereof is connected to the source of the non-volatile memory element  52 A. The drain of the non-volatile memory element  52 A is connected to the source of the PMOS transistor  53 A. The drain of the PMOS transistor  53 A is connected to a node N1. The source of the PMOS transistor  59 A is connected to the node N1 and the drain thereof is connected to the supply terminal VSS. The input terminal of the inverter circuit  57 A is connected to the node N1, and the output terminal thereof is connected to the gate of the PMOS transistor  58 A. The source of the PMOS transistor  58 A is connected to the supply terminal VDD, and the drain thereof is connected to a node N2. The input terminal of the inverter circuit  55 A is connected to the output terminal of the inverter circuit  56 A, and the output terminal thereof is connected to the node N2 and the input terminal of the inverter circuit  56 A. The source of the NMOS transistor  54 A is connected to the supply terminal VSS, and the drain thereof is connected to the node N2. A signal Φ 03  is input to the gates of the PMOS transistor  51 A and the PMOS transistor  53 A. A signal Φ 02 X, which is an inverted signal of the signal Φ 02 , is input to the gate of the PMOS transistor  59 A. The signal Φ 02  is input to the gate of the NMOS transistor  54 A. 
         [0033]    A signal Φ 01  is input to one input terminal of the OR circuit  61 , the node N2 is connected to the other input terminal thereof, and the output terminal thereof is connected to a node N3. The signal Φ 01  is input to one input terminal of the OR circuit  62 , the node N4 is connected to the other input terminal thereof, and the output terminal thereof is connected to a node N5. 
         [0034]    The operation of the data reading device according to the first embodiment configured as described above will be described on the basis of the timing charts given in  FIG. 2  and  FIG. 3 . 
         [0035]      FIG. 2  illustrates an operation for preventing erroneous writing when the data reading device starts a reading operation and a high voltage is applied during the reading operation. 
         [0036]    When the signal Φ 02  goes to a high level at time t1, the NMOS transistors  34 A,  34 B,  44 A,  54 A turn on, and the nodes DOUTA, DOUTB, N2, N4 go to a low level. Then, the latch circuits latch the low level. At the same time, the signal Φ 02 X goes to the low level, so that the PMOS transistor  59 A turns on and the node N1 goes to the low level, causing the PMOS transistor  58 A to turn off. Further, the signals Φ 01 , Φ 03  are at the high level, so that the PMOS transistors  31 A,  33 A,  31 B,  33 B,  41 A,  43 A,  51 A,  53 A are all off. 
         [0037]    Subsequently, at time t2, the signal Φ 02  goes to the low level, the signal Φ 02 X goes to the high level, and the signal Φ 03  goes to the low level. The PMOS transistors  51 A,  53 A turn on, but no data has been written to the non-volatile memory element  42 A, so that no charges have been injected into the floating gate and no current will flow into the non-volatile memory element  52 A. Hence, the node N1 remains at the low level. The voltage of the node N1 is retained by a parasitic capacitance existing in the node N1. At this time, if a high voltage is applied to the supply terminal VDD, then the potential state around the non-volatile memory element  52 A will become the same state as that at data writing. However, the node N1 is retained in a low level state merely by the capacitance, so that current required for writing cannot be supplied and erroneous writing will not occur. 
         [0038]    At time t3, the signal Φ 03  goes to the high level, and the signal Φ 01  goes to the low level. Since the node N2 is held at the low level, the node N3, which is the output terminal of the OR circuit  61 , goes to the low level. Similarly, since the node N4 is held at the low level, the node N5, which is the output terminal of the OR circuit  62 , goes to the low level, causing the data reading unit  300  to carry out the reading operation. 
         [0039]    A description will now be given of the operation of the data reading device when an unexpected high voltage is applied to the semiconductor device at time t4. 
         [0040]    At this time, the potential around each of the non-volatile memory elements  32 A,  32 B,  42 A is the same. However, the W/L ratios of the PMOS transistors  41 A,  43 A are designed to be larger than the W/L ratios of the PMOS transistors  31 A,  33 A,  31 B,  33 B, so that the voltage drop between the source and the drain of each of the PMOS transistors  41 A,  43 A will be less. Thus, the voltage applied between the source and the drain of the non-volatile memory element  42 A will be higher than the voltage applied between the source and the drain of the non-volatile memory elements  32 A,  32 B. This makes it easier to write to the non-volatile memory element  42 A. Further, the W/L ratio of the non-volatile memory element  42 A is designed to be larger than the W/L ratios of the non-volatile memory elements  32 A,  32 B, so that a larger on-current will flow even if a write voltage remains the same, causing the node N4 to go to the high level sooner than the node DOUTA and the node DOUTB. In this case, writing to the non-volatile memory element  42 A causes the node N4 to go to the high level and also the node N5, which is the output terminal of the OR circuit  62 , to go to the high level. Thus, the data reading unit  300  stops the reading operation, preventing erroneous writing to the non-volatile memory elements  32 A,  32 B. 
         [0041]    Erroneous writing to the non-volatile memory element  42 A causes charges to be injected to the gate of the non-volatile memory element  42 A and the non-volatile memory element  52 A also passes current, but the node N1 remains at the low level, because the PMOS transistors  51 A,  53 A are off. 
         [0042]    When the signal Φ 01  goes to the high level at time t5, the node N3 goes to the high level, terminating the reading operation. 
         [0043]      FIG. 3  is a timing chart illustrating the reading operation of the data reading device after erroneous writing to the non-volatile memory element  42 A of the dummy reading circuit  40 A takes place. 
         [0044]    When the signal Φ 02  goes to the high level at time t1, the NMOS transistors  34 A,  34 B,  44 A,  54 A turn on, and the nodes DOUTA, DOUTB, N2, N4 go to the low level. Further, the latch circuits latch the low level. At the same time, the signal Φ 02 X goes to the low level, so that the PMOS transistor  59 A turns on, causing the node N1 to go to the low level and the PMOS transistor  58 A to turn off. Further, the signals Φ 01 , Φ 03  are at the high level, so that PMOS transistors  31 A,  33 A,  31 B,  33 B,  41 A,  43 A,  51 A,  53 A are all off. 
         [0045]    Then, at time t2, the signal Φ 02  goes to the low level, the signal Φ 02 X goes to the high level, and the signal Φ 03  goes to the low level. When the PMOS transistors  51 A,  53 A turn on, current flows to the non-volatile memory element  52 A, because the non-volatile memory element  42 A has been written and the charges have been injected into the floating gate. Hence, the node N1 goes to the high level, so that the PMOS transistor  58 A turns on and the latch is inverted, causing the node N2 to go to the high level. 
         [0046]    At time t3, the signal Φ 03  goes to the high level and the signal Φ 01  goes to the low level. Since the node N2 is being retained at the high level, the node N3, which is the output terminal of the OR circuit  61 , goes to the high level. Since the PMOS transistors  41 A,  43 A are off, the node N4 is retained at the low level, so that the node N5, which is the output terminal of the OR circuit  62 , goes to the low level and the data reading unit  300  carries out the reading operation. 
         [0047]    When the signal Φ 01  goes to the high level at time t5, the node N5 goes to the high level, terminating the reading operation. 
         [0048]    As described above, erroneous writing to the non-volatile memory elements can be prevented even if a high voltage is applied during the data reading operation. For a stable operation, a capacitance element may be connected to the node N1. The capacitance element in this case has to be set to a capacitance value that does not allow the passage of current required for erroneous writing as described above. Further, the description has been given of the case where, in the dummy reading circuit  40 A, the W/L ratios of the PMOS transistors  41 A,  43 A and the non-volatile memory element  42 A are set to be larger than the W/L ratios of the PMOS transistors  31 A,  33 A,  31 B,  33 B and the non-volatile memory elements  32 A,  32 B such that writing occurs more easily than in the data reading circuits  30 A,  30 B; alternatively, however, any one of the W/L ratios may be larger or a combination thereof may be used. Whether erroneous writing to the non-volatile memory element  42 A has occurred can be checked by checking whether the node N2 is at the high level or the low level in the period from time t2 to time t3. More specifically, if the node N2 is at the high level, then it indicates that erroneous writing has occurred earlier, and if the node N2 is at the low level, then it means that no writing has occurred. The number of the data reading circuits included in the data reading unit may be any number from one. 
       Second Embodiment 
       [0049]      FIG. 4  is a circuit diagram illustrating a data reading device according to a second embodiment. The data reading device is composed of a data reading unit  300  and an erroneous writing prevention circuit  700 . The data reading unit  300  is the same as that in the first embodiment, so that the description of the circuit configuration will be omitted. The erroneous writing prevention circuit  700  is composed of dummy reading circuits  40 A,  40 B, state detection circuits  50 A,  50 B, OR circuits  61 ,  64 ,  65 , and an inverter circuit  63 . The dummy reading circuit  40 A and the state detection circuit  50 A are the same as those in the first embodiment, so that the description of the circuit configurations will be omitted. The dummy reading circuit  40 B has the same circuit configuration as that of the dummy reading circuit  40 A and includes PMOS transistors  41 B,  43 B, a non-volatile memory element  42 B, an NMOS transistor  44 B, and inverters  45 B,  46 B. However, the PMOS transistors  41 B,  43 B and the non-volatile memory element  42 B are adapted to be as easy to be written as the PMOS transistors  41 A,  43 A and the non-volatile memory element  42 A. The state detection circuit  50 B has the same circuit configuration as that of the state detection circuit  50 A and includes PMOS transistors  51 B,  53 B,  58 B,  59 B, a non-volatile memory element  52 B, inverter circuits  55 B,  56 B,  57 B, and an NMOS transistor  54 B. 
         [0050]    The connections of data reading circuits  30 A,  30 B, the dummy reading circuit  40 A, and the state detection circuit  50 A are the same as those in the first embodiment, so that the description of the circuit connections will be omitted. 
         [0051]    The source of the PMOS transistor  41 B is connected to a supply terminal VDD, the gate thereof is connected to a node N8, and the drain thereof is connected to the source of the non-volatile memory element  42 B. The gate of the non-volatile memory element  42 B is connected to the gate of the non-volatile memory element  52 B, and the drain thereof is connected to the source of the PMOS transistor  43 B. The gate of the PMOS transistor  43 B is connected to the node N8, and the drain thereof is connected to a node N9. The source of the NMOS transistor  44 B is connected to a supply terminal VSS, and the drain thereof is connected to the N9. The input terminal of the inverter circuit  45 B is connected to the output terminal of the inverter circuit  46 B, and the output terminal thereof is connected to the N9 and the input terminal of the inverter circuit  46 B. 
         [0052]    The source of the PMOS transistor  51 B is connected to the supply terminal VDD, and the drain thereof is connected to the source of the non-volatile memory element  52 B. The drain of the non-volatile memory element  52 B is connected to the source of the PMOS transistor  53 B. The drain of the PMOS transistor  53 B is connected to a node N6. The source of the PMOS transistor  59 B is connected the node N6, and the drain thereof is connected to the supply terminal VSS. The input terminal of the inverter circuit  57 B is connected to the node N6, and the output terminal thereof is connected to the gate of the PMOS transistor  58 B. The source of the PMOS transistor  58 B is connected to the supply terminal VDD, and the drain thereof is connected to a node N7. The input terminal of the inverter circuit  55 B is connected to the output terminal of the inverter circuit  56 B, and the output terminal thereof is connected to the node N7 and the input terminal of the inverter circuit  56 B. The source of the NMOS transistor  54 B is connected to the supply terminal VSS, and the drain thereof is connected to the node N7. A signal Φ 01  is input to one input terminal of the OR circuit  61 , a node N2 is connected to the other input terminal thereof, and the output terminal thereof is connected to a node N3. A node N4 and a node N9 are connected to two input terminals of the OR circuit  65 , a signal Φ 01  is input to the remaining input terminal thereof, and the output terminal thereof is connected to a node N5. The inverter circuit  63  has a node N2 connected to the input terminal thereof, and a node N2X connected to the output terminal thereof. The node N2X and the node N7 are connected to two input terminals of the OR circuit  64 , the signal Φ 01  is input to the remaining input terminal thereof, and a node N8 is connected to the output terminal thereof. 
         [0053]    The operation of the data reading device according to the second embodiment configured as described above will be described with reference to the timing chart given in  FIG. 5 . 
         [0054]      FIG. 5  illustrates the operation for preventing erroneous writing when, after the non-volatile memory element  42 A is erroneously written, the data reading device starts a reading operation and a high voltage is applied during the reading operation. 
         [0055]    A signal Φ 02  goes to a high level at time t1, NMOS transistors  34 A,  34 B,  44 A,  44 B,  54 A,  54 B turn on, and nodes DOUTA, DOUTB, N2, N4, N7, N9 go to a low level. At the same time, Φ 02 X, which is an inverted signal of the signal Φ 02 , goes to a low level, so that PMOS transistors  59 A,  59 B turns on and the node N1 and the node N6 go to the low level, causing PMOS transistors  58 A,  58 B to turn off. Further, signals Φ 01 , Φ 03  are at the high level, so that PMOS transistors  31 A,  33 A,  31 B,  33 B,  41 A,  43 A,  41 B,  43 B,  51 A,  53 A,  51 B,  53 B are all off. 
         [0056]    Then, at time t2, the signal Φ 02  goes to the low level, the signal Φ 02 X goes to the high level, and the signal Φ 03  goes to the low level. Since the non-volatile memory element  42 A has been erroneously written, charges have been injected into a floating gate and current flows to a non-volatile memory element  52 A. This causes the node N1 to go to the high level, so that the PMOS transistor  58 A turns on and the node N2 goes to the high level. Since the non-volatile memory element  42 B has not been erroneously written, no charges have been injected into the floating gate, so that no current will flow to the non-volatile memory element  52 B. Thus, the node N6 remains at the low level. 
         [0057]    At time t3, the signal Φ 03  goes to the high level, and the signal Φ 01  goes to the low level. The node N2 is being retained at the high level, so that the node N3, which is the output terminal of the OR circuit  61 , goes to the high level. Since the PMOS transistors  41 A,  43 A are off, the node N4 is retained at the low level. Meanwhile, the node N2X is at the low level and the node N7 is also being retained at the low level, so that a node N8, which is the output terminal of the OR circuit  64 , goes to the low level. Although the node N8 goes to the low level and the PMOS transistors  41 B,  43 B turn on, the node N9 remains at the low level, because the non-volatile memory element  42 B has not been written. Therefore, the node N5, which is the output terminal of the OR circuit  65 , goes to the low level, and the data reading unit  300  carries out the reading operation. 
         [0058]    A description will be given of the operation of the data reading device when an unexpected high voltage is applied to a semiconductor device at time t4. 
         [0059]    At this time, the potential around each of the non-volatile memory elements  32 A,  32 B,  42 B is the same. However, the W/L ratios of the PMOS transistors  41 B,  43 B are designed to be larger than the W/L ratios of the PMOS transistors  31 A,  33 A,  31 B,  33 B, so that a voltage drop between the source and the drain of each of the PMOS transistors  41 B,  43 B will be less. Thus, the voltage applied between the source and the drain of the non-volatile memory element  42 B will be higher than the voltage applied between the source and the drain of the non-volatile memory elements  32 A,  32 B. This makes it easier to write to the non-volatile memory element  42 B. Further, the W/L ratio of the non-volatile memory element  42 B is designed to be larger than the W/L ratios of the non-volatile memory elements  32 A,  32 B, so that a larger on-current will be passed even if a write voltage remains the same, causing the node N9 to go to the high level sooner than the node DOUTA and the node DOUTB. In this case, writing to the non-volatile memory element  42 B causes the node N9 to go to the high level and also the node N5, which is the output terminal of the OR circuit  65 , to go to the high level. Thus, the data reading unit  300  stops the reading operation, preventing erroneous writing to the non-volatile memory elements  32 A,  32 B. Writing to the non-volatile memory element  42 B causes charges to be injected into the gate of the non-volatile memory element  42 B and the non-volatile memory element  52 B also passes current, but the node N6 remains at the low level, because the PMOS transistors  51 B,  53 B are off. 
         [0060]    When the signal Φ 01  goes to the high level at time t5, the node N5 goes to the high level, and the reading operation is terminated. 
         [0061]    In the present embodiment, the description has been given of the case where two each of the dummy reading circuits and the state detection circuits are disposed; however, any number of the dummy reading circuits and the state detection circuits may be disposed to permit the prevention of any number of times of erroneous writing. A dummy reading circuit that has been written can be identified by checking whether the node N2 and the node N7 are at the high level or the low level during the period from time t2 to time t3. 
         [0062]    The circuit configurations of the data reading devices in the first and the second embodiments in accordance with the present invention described above are to be considered illustrative, and may be modified to an extent that does not depart from the scope of the appended claim. 
         [0063]    For example, as illustrated in the circuit diagram of the data reading device in  FIG. 6 , the sources of non-volatile memory elements  42 A and  52 A may be directly connected to supply terminals VDD in a dummy reading circuit  60 A and a state detection circuit  70 A of an erroneous writing prevention circuit  800 . This configuration further increases the voltage applied between the source and the drain of the non-volatile memory element  42 A, thus providing an advantage that the writing thereto is easier. 
         [0064]    Further alternatively, the OR circuits may be composed of NAND circuits by inverting an input logic.