Abstract:
A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which includes a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem where the material of the first main interconnection transfers from a portion connected to the second interconnection due to electromigration to form a void, with the result that the first interconnection is disconnected from the second interconnection.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application of application Ser. No. 10/397,369 filed on Mar. 27, 2003, which is a continuation application of application Ser. No. 10/127,599, filed on Apr. 23, 2002, now U.S. Pat. No. 6,759,747, which is a continuation application of application Ser. No. 09/329,249 filed on Jun. 10, 1999, now U.S. Pat. No. 6,400,031, which are hereby incorporated by reference in their entirety for all purposes. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention generally relates to a semiconductor substrate, and more particularly, the present invention relates to a damascene interconnection structure. 
         [0004]    This application is a counterpart of Japanese application Serial Number 163304/1998, filed Jun. 11, 1998, the subject matter of which is incorporated herein by reference. 
         [0005]    2. Description of the Related Art 
         [0006]    In general, it is difficult to form a pattern by etching a Copper (Cu) interconnection. In a formation of the Cu interconnection, an insulating layer such as a SiO 2  or BPSG is formed on a semiconductor substrate. Then, a recess is formed in the insulating layer so as to shape the Cu interconnection. Then, Cu is buried in the recess. As a result, the Cu interconnection buried in the recess is a so-called damascene interconnection, which is formed on the semiconductor substrate. 
         [0007]    Such a damascene interconnection is formed as shown in  FIG. 1A-FIG .  1 D.  FIG. 1A-FIG .  1 D are cross sectional views showing a damascene interconnection structure of a conventional art. 
         [0008]    A first interconnection pattern recess is formed using photolithography techniques and etching techniques in a first SiO 2  film  12  having a thickness of 1 μm on the semiconductor substrate  10 . Then, a barrier layer  16  such as a TiN is formed on the first SiO 2  film  12  in the first interconnection pattern recess. Then, Cu is formed on the entire surface and the Cu is polished with alkaline solution having a colloidal-silica, so-called CMP (chemical mechanical polishing) method. As a result, a first interconnection including a main interconnection  19  is formed which is made up of the Cu, as shown in  FIG. 1A . A second SiO 2  film  22  having a thickness of 1 μm is formed on the first SiO 2  film  12  where the first interconnection  18  was formed. Then, a through hole  55  is formed in the second SiO 2  film  22  so that a center portion of an upper surface of the first interconnection  18  is exposed, as shown in  FIG. 1B . 
         [0009]    A second interconnection pattern recess  24  is formed so that a predetermined portion of the through hole  55  remains. Then, a barrier layer  26  such as TiN is formed in the remaining through hole  55  and the second interconnection pattern recess  24 , as shown in  FIG. 1C . 
         [0010]    Then, Cu is formed on the entire surface using a sputtering technique, and the Cu is polished using a CMP method. As a result, a second interconnection  28  including a main interconnection  29  which is made up of the Cu is formed, as shown in  FIG. 1D . 
         [0011]    In the conventional art of the method for forming the interconnections, it is desirable to avoid a problem wherein the Cu transfers from a portion connected to the second interconnection due to electromigration, whereby a void is formed at the connected portion, and the first interconnection is disconnected from the second interconnection. 
       SUMMARY OF THE INVENTION 
       [0012]    An object of the present invention is to provide a semiconductor device that can avoid the above noted problem wherein the Cu transfers from a portion connected to the second interconnection due to electromigration, whereby a void is formed at the connected portion, and the first interconnection is disconnected from the second interconnection. 
         [0013]    According to one aspect of the present invention, for achieving the above object, there is provided a semiconductor device including a first insulating layer having a through hole; a first interconnection including a first conductive layer, a first barrier layer, and a first main interconnection; the first conductive layer formed on the first insulating layer in the first through hole; the first barrier layer formed on the first conductive layer; the first main interconnection formed on the first barrier layer so as to bury the through hole; and a second interconnection connected to one of the first conductive layer and the first barrier layer. 
         [0014]    According to another aspect of the present invention, for achieving the above object, there is provided a semiconductor device including a first insulating layer having a through hole; a first interconnection including a first conductive layer, a first barrier layer, and a first main interconnection; the first conductive layer formed on the first insulating layer in the first through hole; the first barrier layer formed on the first conductive layer; the first main interconnection formed on the first barrier layer so as to bury the through hole; and a second interconnection connected to one of an edge portion of the first conductive layer exposed from an upper surface of the first insulating layer and an edge portion of the first barrier layer exposed from an upper surface of the first insulating layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    While the specification concludes claims particularly pointing out and distinctly claiming the subject matter that is regarded as the invention, the invention, along with the objects, features, and advantages thereof, will be better understood from the following description taken in connection with the accompanying drawings, in which: 
           [0016]      FIG. 1A-FIG .  1 D are cross-sectional views showing a damascene interconnection structure of a conventional art. 
           [0017]      FIG. 2  is a plan view showing a damascene interconnection structure according to a first preferred embodiment. 
           [0018]      FIG. 3  is a cross-sectional view showing a damascene interconnection structure according to the first preferred embodiment. 
           [0019]      FIGS. 4A-4F  are cross-sectional views showing a method for forming damascene interconnections structure according to the first preferred embodiment. 
           [0020]      FIGS. 5A-5F  are cross-sectional views showing a method for forming damascene interconnections structure according to a second preferred embodiment. 
           [0021]      FIG. 6  is a plan view showing a damascene interconnection structure according to a third preferred embodiment. 
           [0022]      FIG. 7  is a cross-sectional view showing a damascene interconnection structure according to a third preferred embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0023]    A storage device and an alternate processing method for defective sectors of a storage device according to first and second preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings. 
         [0024]      FIG. 2  is a plan view showing a damascene interconnection structure according to a first preferred embodiment.  FIG. 3  is a cross-sectional view showing a damascene interconnection structure according to the first preferred embodiment. 
         [0025]    As shown in  FIG. 2  and  FIG. 3 , a first damascene interconnection structure is preferably made up of a first insulating layer, as a first SiO 2    12 , having a first through hole, and a first interconnection  18  that is buried in the first through hole. The first interconnection  18  is preferably made up of a first conductive layer such as a first TiN film  16   a , a first barrier layer such as a first Ti film  17   a , and a first main interconnection  19 . The first TiN film  16   a  is formed on the first SiO 2    12  in the first through hole. The first Ti film  17   a  is formed on the first TiN film  16   a . The first main interconnection is formed on the Ti film  17   a  so as to bury the first through hole. The first through hole has a first extending direction and a second extending direction which is longer than the first extending direction, and is formed so that the second extending direction corresponds to the flow of electrons in the first interconnection  18  which is formed in the first through hole. 
         [0026]    A second damascene interconnection structure is preferably made up of a second insulating layer, as a second SiO 2    22 , having a second through hole, and a second interconnection  28  which is buried in the second through hole. The second interconnection  28  is preferably made up of a second conductive layer such as a second TiN film  26 , a second barrier layer such as a second Ti film  27 , and a second main interconnection  29 . The second TiN film  26  is formed on the second SiO 2    22  in the second through hole. The second Ti film  27  is formed on the second TiN film  26 . The second main interconnection  29  is formed on the second Ti film  27  so as to bury the second through hole. The first interconnection  18  is connected to one of the second TiN film  26  and the second Ti film  27  of the second interconnection  28 . The second interconnection  28  is connected to one of the first TiN film  16   a  and the first Ti film  17   a . The second interconnection  28  has a protrusion portion where the second interconnection  28  is connected to the first interconnection  18 . The protrusion portion of the second interconnection  28  is connected to the first interconnection  18  via the first through hole. 
         [0027]    In the structure mentioned above, when a voltage so as to become a high voltage is applied to the first interconnection  18  and a voltage so as to become a low voltage is applied to the second interconnection  28 , electrons flow from the second interconnection  28  to the first interconnection  18 . The Cu atoms in the first main interconnection  19  of the first interconnection  18  move in the opposite direction of electron flow because of electromigration. As a result, voids are formed in the first main interconnection  19  of the first interconnection  18 . However, since the second interconnection is connected to the first Ti  17   a , the first Ti  17   a  can maintain electrical connection between the first and second interconnections. 
         [0028]      FIGS. 4A-4F  are cross-sectional views showing a method for forming a damascene interconnections structure according to the first preferred embodiment. 
         [0029]    As shown in  FIG. 4A , a first SiO 2  film  12  as a first insulating film with a thickness of 1 μm is formed on a semiconductor substrate  10 . First interconnections recesses  14  with a depth of 500 nm are formed in regions which first interconnections are formed, using a photolithography technique and plasma etching with a mixed gas of C 2 F 8  and O 2 . 
         [0030]    As shown in  FIG. 4B , TiN films  16 ,  16   a  with a thickness of 30 nm are selectively formed on the first SiO 2  film  12  in the first interconnection recesses  14 . Ti films  17 ,  17   a  with a thickness of 5 nm are formed on the TiN films  16 ,  16   a . A CVD (Chemical Vapor Deposition) method and CMP (Chemical Mechanical Polishing) method are used for forming the TiN films  16 ,  16   a  and the Ti films  17 ,  17   a . Then, Cu is buried in the first interconnection recesses  14  and then is polished until the first SiO 2  film  12  is exposed, using the CMP method. As a result, a first main interconnection  19  is formed in the first interconnection recesses  14 . Therefore, a first interconnection  18  which is made up of the TiN films  16 ,  16   a , the Ti films  17 ,  17   a , and the first main interconnection  19 , are formed in the first interconnections recesses  14 . 
         [0031]    As shown in  FIG. 4C , a second SiO 2  film as a second insulating film with a thickness of 1 urn is formed on the entire surface. A first through hole  50  is formed so as to expose the first SiO 2  film  12   a  surface, a portion of the TiN films  16   a , and a portion of the Ti films  17   a  in the second SiO 2  film. A portion of the first SiO 2  film  12   a  is removed. As a result, a portion of the TiN films  16   a  sidewalls is exposed. Here, an etching depth is about the half thickness of the first main interconnection  19 . 
         [0032]    As shown in  FIG. 4D , a second interconnection recess  24  with a thickness of 500 nm is formed in the second SiO 2  film  22  using plasma etching with C 2 F 8  gas and O 2  gas. 
         [0033]    As shown in  FIG. 4E , a second TiN film  26  and a second Ti film  27  are successively formed on the second SiO 2  film in the second interconnection recess using the same manner of the forming steps for the first interconnection  18 . 
         [0034]    As shown in  FIG. 4F , Cu is buried in the second interconnection recess  24  using a sputtering method or CVD method. Then, the Cu is polished until the second SiO 2  film  22  surface is exposed. 
         [0035]    A second interconnection  28  which is made up of Cu as a second main interconnection, the second TiN film  26 , and the second Ti film  27 , are formed in the second interconnection recess  24 . Thus, the second interconnection  28  is connected to the first TiN film  16   a  and the first Ti film  17   a.    
         [0036]      FIGS. 5A-5F  are cross-sectional views showing a method for forming a damascene interconnection structure according to a second preferred embodiment. 
         [0037]    As shown in  FIG. 5A , a first insulating film  12  is preferably made up of SiO 2  film  34 , SiN film  32 , and SiO 2  film  30 . The SiO 2  film  34  with a thickness of 500 nm is formed on semiconductor substrate  10 . The SiN film  32  as an etching stop layer with a thickness of 50 nm is formed on the SiO 2  film  34 . The SiO 2  film  30  with a thickness of 500 nm is formed on the SiN film  32 . 
         [0038]    Then, the SiO 2  film  30  is etched using a photolithography technique and plasma etching with C 2 F 8  gas and O 2  gas. At this time, SiN film  32  serves as the etching stop layer against the SiO 2  film  30 . As a result, the SiO 2  film patterns  12   a ,  30  and a first interconnection recess  14  are formed, respectively. 
         [0039]    As shown in  FIG. 5B , TiN films  16 ,  16   a , Ti films  17 ,  17   a , and first main interconnections  19  are respectively formed in the first interconnection recess  14  using the same manner for forming steps of the first preferred embodiment. Here, a first interconnection  18  is made up of the TiN films  16 ,  16   a , the Ti films  17 ,  17   a , and the first main interconnections  19 . 
         [0040]    As shown in  FIG. 5C , a second insulating film  22  is preferably made up of SiO 2  film  44 , SiN film  42 , and SiO 2  film  40 . The SiO 2  film  44  with a thickness of 500 nm is formed on the entire surface. The SiN film  42  as an etching stop layer with a thickness of 50 nm is formed on the SiO 2  film  44 . The SiO 2  film  40  with a thickness of 500 nm is formed on the SiN film  42 . 
         [0041]    The SiO 2  film  40  is etched using a photolithography technique and plasma etching with C 2 F 8  gas and O 2  gas until the SiN film  42  is exposed. Then, the SiN film  42  is etched using plasma etching with SF 6  gas and O 2  gas. Then, the SiO 2  films  12 ,  44  are etched using a photolithography technique and plasma etching with C 2 F 8  gas and O 2  gas until the SiN film  32  is exposed. As a result, a through hole  50  is formed, and a sidewall of the TiN film  16   a , edge of the Ti films  17   a , and a part of the first main interconnections  19  are exposed in the through hole  50 . 
         [0042]    As shown in  FIG. 5D , a second interconnection recess  24  which is wider than the through hole  50 , is formed by etched the SiO 2  film  40  using a photolithography technique and plasma etching with C 2 F 8  gas and O 2  gas. 
         [0043]    As shown in  FIG. 5E , a second TiN film  26  mad a second Ti film  27  are successively formed in the second interconnection recess  24  and the through hole  50  using the same manner of the forming steps for the first interconnection  18 . Here, before forming the second TiN film  26  and the second Ti film  27 , another Ti film may be formed in the second interconnection recess  24  and the through hole  50 , The first main interconnections  19  are subjected to NH 3  for forming the second TiN film  26 . As a result, the first main interconnections  19  nitrides, and it is difficult to electrically connect between the first interconnection  18  and the second interconnection  28 . 
         [0044]    As shown in  FIG. 5F , Cu is buried in the second interconnection recess  24  using a sputtering method or CVD method. Then, the Cu is polished until the second SiO 2  film  22  surface is exposed. 
         [0045]    A second interconnection  28  which is made up of Cu as a second main interconnection, the second TiN film  26 , and the second Ti film  27 , are formed in the second interconnection recess  24 . Thus, the second interconnection  28  is connected to the first TiN film  16   a  and the first Ti film  17   a.    
         [0046]      FIG. 6  is a plan view showing a damascene interconnection structure according to a third preferred embodiment.  FIG. 7  is a cross-sectional view showing a damascene interconnection structure according to the third preferred embodiment. 
         [0047]    As shown in  FIG. 6  and  FIG. 7 , a first interconnection  38  is preferably made up of a TiN film  16  as a barrier layer, a Ti film  17  as a conductive layer, and a first main interconnection  19  comprising a Cu. The first interconnection  38  is formed in a first SiO 2  film  12 . A second interconnection  48  is preferably made up of a TiN film  26  as a barrier layer, a Ti film  27  as a conductive layer, and a first main interconnection  29  comprising a Cu. 
         [0048]    The second interconnection  48  is formed so as to cover an upper surface of and a sidewall of the first interconnection  38 . 
         [0049]    Since a connecting area is wider than in the conventional art, a contact resistance is low and current flow is easy. Therefore, electromigration cam be avoided. 
         [0050]    In the structure mentioned above, when a voltage so as to become a high voltage is applied to the first interconnection  38  and a voltage so as to become a low voltage is applied to the second interconnection  48 , electrons flows from the second interconnection  48  to the first interconnection  38 . The Cu atoms in the first main interconnection  19  of the first interconnection  38  move in opposite direction of electron flow because of electromigration. As a result, voids are formed in the first main interconnection  19  of the first interconnection  38 . However, since the second interconnection  48  is connected to the first Ti  17   a , the first Ti  17   a  can maintain electrical connection between the first and second interconnections. 
         [0051]    While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.