Abstract:
A CMOS transmission circuit is proposed wherein there are provided first and second transmission lines, first and second MOSFETs of opposite conductivity types which are controlled in response to an input signal and are arranged at the start points of the first and second transmission lines, and third and fourth MOSFETs serving as level shifters arranged at the end points of the first and second transmission lines, so that a high level output is obtained through the first MOSFET, the first transmission line and third MOSFET, and a low level output is obtained through the second MOSFET, the second transmission line and the fourth MOSFET, thereby decreasing the voltage amplitudes at the first and second transmission lines.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a CMOS transmission circuit used to drive a bus line arranged in a MOS-LSI. 
     A CMOS inverter 1 is used in a conventional CMOS (complementary metal oxide semiconductor) transmission circuit, as shown in FIG. 1. The source of an n-channel enhancement type MOSFET (metal-oxide-semiconductor field-effect transistor to be referred to as a MOS transistor for brevity hereafter) TN is connected to the ground (Vss). The drain of the MOS transistor TN is connected to the drain of a p-channel enhancement type MOS transistor TP. The source of the MOS transistor TP is connected to a power supply terminal 2 (Vcc). The gates of the MOS transistors TP and TN are connected to an input terminal 1a. The common drain node of the MOS transistors TP and TN is connected to a start point of a transmission line 3. The end point of the transmission line 3 is connected to an output terminal 1b. An input signal IN, supplied to the input terminal 1a, is inverted and amplified by the inverter 1, thereby obtaining an output signal OUT at the output terminal 1b. A capacitance C between the transmission line 3 and ground is a parasitic capacitance of the transmission line 3. 
     In this conventional CMOS transmission circuit having the arrangement described above, when an input signal voltage Vin changes in the range of Vcc to Vss (0 V), the voltage at the transmission line 3 changes by a corresponding magnitude within the range of Vss (0 V) to Vcc, and the parasitic capacitance C is usually very large. Therefore, a great number of carriers must be charged/discharged through the MOSFET TP or TN, and the drive capacity of the CMOS inverter 1 must be preset to be large. For this reason, high-speed signal transmission cannot be performed, and power consumption is increased. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a CMOS transmission circuit which achieves high-speed signal transmission with low power consumption. 
     According to an aspect of the present invention, there is provided a CMOS transmission circuit comprising: an input terminal which receives an input signal; a first voltage source; a second voltage source; a first MOSFET of a first conductivity type which has a gate connected to the input terminal, one terminal being connected to the first voltage source, and the other terminal; a second MOSFET of a second conductivity type which has a gate connected to the input terminal, one terminal being connected to the second voltage source, and the other terminal; a first transmission line which has a start point, connected to the other terminal of the first MOSFET, and an end point; an output terminal for generating an output signal; first reference voltage generating circuit for generating a first reference voltage; a third MOSFET of the first conductivity type which has one terminal connected to the end point of the first transmission line, the other terminal connected to the output terminal, and a gate which receives the first reference voltage generated by the first reference voltage generating circuit; a second transmission line which has a start point, connected to the other terminal of the second MOSFET, and an end point; second reference voltage generating circuit for generating a second reference voltage; and a fourth MOSFET of the second conductivity type which has one terminal connected to the end point of the second transmission line, the other terminal connected to the output terminal, and a gate which receives the second reference voltage generated by the second reference voltage generating circuit. 
     According to this arrangement, high-speed signal transmission and low power consumption can be accomplished. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional CMOS transmission circuit; 
     FIG. 2 is a circuit diagram of a CMOS transmission circuit according to an embodiment of the present invention; 
     FIG. 3 is a graph showing the input-output characteristics of the circuit shown in FIG. 2, so as to explain the operation thereof; 
     FIG. 4 is a circuit diagram of a CMOS transmission circuit according to another embodiment of the present invention; 
     FIG. 5 is a graph showing the input-output characteristics of the circuit shown in FIG. 4, so as to explain the operation thereof; 
     FIG. 6 is a circuit diagram of a CMOS transmission circuit according to still another embodiment of the present invention; and 
     FIGS. 7 to 9 are circuit diagrams showing different arrangements of constant voltage circuits in the embodiments of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 shows a CMOS transmission circuit according to an embodiment of the present invention. The source of a p-channel enhancement type first MOS transistor T1 is connected to a power supply terminal 2 which receives a power supply voltage Vcc. The gate of the MOS transistor T1 is connected to an input terminal 1a which receives an input signal IN. The drain of the MOS transistor T1 is connected to the start point of a first transmission line L1 and to one electrode of a capacitor 5 serving as a constant voltage circuit 4. The other electrode of the capacitor 5 is connected to the drain of an n-channel enhancement type second MOS transistor T2 and the start point of a second transmission line L2. The source of the MOS transistor T2 is grounded (Vss), and the gate thereof is connected to the input terminal 1a. The end point of the first transmission line L1 is connected to the source of a p-channel enhancement type third MOS transistor T3. The gate of the MOS transistor T3 receives a first reference voltage V1 and can be rendered conductive in response thereto. The drain of the MOS transistor T3 is connected to an output terminal 1b at which an output signal OUT appears. The end point of the second transmission line L2 is connected to the source of an n-channel enhancement type fourth MOS transistor T4. The gate of the MOS transistor T4 receives a second reference voltage V2 and can be rendered conductive in response thereto. The drain of the MOS transistor T4 is connected to the output terminal 1b. It should be noted that reference symbols C1 and C2 denote parasitic capacitances of the first and second transmission lines L1 and L2, respectively. The third and fourth transistors T3 and T4 serve as voltage limiting transistors. The first and second reference voltages V1 and V2 are preset so as to satisfy inequalities (1) and (2) as follows: 
     
         0&lt;V1+|VTP3|&lt;Vcc                          (1) 
    
     
         0&lt;V2-VTN4&lt;Vcc                                              (2) 
    
     where VTP3 is the threshold voltage of the p-channel third MOS transistor T3, and VTN4 is the threshold voltage of the n-channel fourth MOS transistor T4. 
     The operation of the CMOS transmission circuit having the arrangement described above will now be described with reference to the input-output characteristic curves shown in FIG. 3. Assume that the voltage Vin of the input signal IN is set at 0 V. The MOS transistor T1 is kept in the ON state, and the MOS transistor T2 is kept in the OFF state. A voltage VL1 at the first transmission line L1 is set at the Vcc level, and a source potential of the MOS transistor T3 increases to the Vcc level. The MOS transistor T3 is then turned on, so that a voltage (output signal voltage) Vout at the output terminal 1b moves to the Vcc level. In this case, a drain potential of the MOS transistor T3 increases to the Vcc level, so that a source-side potential (voltage VL2 at the second transmission line L2) of the MOS transistor T4 increases to the &#34;V2-VTN4&#34; level. In addition, upon an increase in voltage at the first transmission line L1, the second transmission line L2 is charged through the capacitor 5. Therefore, even if the drive capacities of the MOS transistors T3 and T4 are small, the second transmission line L2 can be quickly changed. 
     Next, assume that the input signal voltage Vin increases to establish &#34;Vin=VTN2&#34; for &#34;VTN2=VTN4&#34; (where VTN2 is the threshold voltage of the MOS transistor T2). The MOS transistor T2 is turned on, and the voltage VL2 at the second transmission line L2 becomes 0 V. Therefore, the source potential at the MOS transistor T4 also becomes 0 V, so that the MOS transistor T4 is turned on and the voltage Vout at the output terminal 1b decreases. 
     When the input signal voltage Vin further increases to establish &#34;Vin=Vcc-|VTP1|&#34; for &#34;VTP1=VTP3&#34; (where VTP1 is the threshold voltage of the MOS transistor T1), the MOS transistor T1 is turned off, thereby discharging the potential VL1 of the transmission line L1 through the capacitor 5 and the MOS transistor T2, the MOS transistors T3 and T4, and the transmission line L2 and the MOS transistor T2. The potential VL1 decreases to the &#34;V1+|VTP3|&#34; level. The voltage Vout at the output terminal 1b become 0 V. The charges of the transmission line L1 are discharged from the side of the capacitor 5 and the side of the MOS transistors T3 and T4, so that the MOS transistors T3 and T4 can have a small drive capacity. 
     When &#34;Vin=Vcc&#34; is established, the MOS transistor T1 is held in the OFF state, the MOS transistor T2 is held in the ON state, the MOS transistor T3 is held in the OFF state, and the MOS transistor T4 is held in the ON state. Therefore, the voltage Vout at the output terminal 1b become 0 V. 
     The voltages VL1 and VL2 at the first and second transmission lines L1 and L2 change within the ranges given by the inequalities (3) and (4) below, so that the output signal voltage Vout changes within the range of 0 V to Vcc (full range of the power supply voltage) in accordance with changes in the input signal voltage Vin. 
     
         V1+|VTP3|&lt;VL1&lt;Vcc                        (3) 
    
     
         0&lt;VL2&lt;V2-VTN4                                              (4) 
    
     Since the changes in amplitudes of voltages at the first and second transmission lines L1 and L2 are small, the time required for discharging the parasitic capacitances C1 and C2 is short, thereby allowing high-speed signal transmission. In addition, the parasitic capacitances c1 and C2 will not be subjected to charging/discharging by the full range of the power supply voltage. Therefore, power consumption can be decreased by an amount corresponding to the decreases in amplitudes of the voltages at the transmission lines. 
     FIG. 4 shows another embodiment of the present invention. The circuit shown in FIG. 2 has enhancement type transistors as the voltage limiting MOS transistors T3 and T4. However, in the circuit shown in FIG. 4, depletion type MOS transistors T5 and T6 are used in place of the MOS transistors T3 and T4 in FIG. 2. The MOS transistor T5 can be rendered conductive in response to the power supply voltage Vcc, and the MOS transistor T6 can be rendered conductive in response to the ground potential (Vss). The same reference numerals as used in FIG. 2 denote the same parts in FIG. 4, and a detailed description thereof will thus be omitted. 
     In the arrangement described above, the circuit operation can be performed in a similar manner to that of the circuit shown in FIG. 2. The input-output characteristics of the circuit shown in FIG. 4 are illustrated in FIG. 5. Referring to FIG. 5, reference symbol VTP5 denotes a threshold voltage of the p-channel MOS transistor T5, and VTN6 denotes a threshold voltage of the n-channel MOS transistor T6. 
     According to the circuit shown in FIG. 4, the Vcc power supply voltage is used as the first reference voltage V1, and the Vss power supply voltage (ground potential) is used as the second reference voltage V2. Therefore, two reference voltage generators can be omitted. 
     FIG. 6 shows still another embodiment of the present invention. The same reference numerals as used in FIG. 2 denote the same parts in FIG. 6, and a detailed description thereof will thus be omitted. The gate of a MOS transistor T3 is connected to a power supply terminal 6 through a p-channel enhancement type MOS transistor T7, whose conduction operation is controlled in response to a control signal D. The power supply terminal 6 receives a power supply voltage Vcc. The gate of the MOS transistor T3 is also connected to a terminal 8 through a transmission gate 7. The transmission gate 7 consists of a p-channel enhancement type MOS transistor T8, whose conduction operation is controlled in response to a control signal D, and an n-channel enhancement type MOS transistor T9, whose conduction operation is controlled in response to the control signal D. The terminal 8 receives a first reference voltage V1. The gate of the MOS transistor T4 is grounded (Vss) through an n-channel enhancement type MOS transistor T10, whose conduction operation is controlled in response to the control signal D. The gate of the MOS transistor T4 is also connected to a terminal 10 through a transmission gate 9. The transmission gate 9 consists of a p-channel enhancement type MOS transistor T11, whose conduction operation is controlled in response to the control signal D, and an n-channel enhancement type MOS transistor T12, whose conduction operation is controlled in response to the control signal D. The terminal 10 receives a second reference voltage V2. The common node between the MOS transistors T3 and T4 is connected to the input terminal of an inverter 11. The output terminal of the inverter 11 is connected to an output terminal 1b at which an output signal OUT appears. 
     In the circuit having the arrangement described above, while the control signal D is set at a low level and the control signal D is set at a high level, the transmission gates 7 and 9 are kept in the ON state. The reference voltages V1 and V2 are applied to the gates of the MOS transistors T3 and T4, respectively. Therefore, the circuit shown in FIG. 6 performs the same operation as that shown in FIG. 2, thereby obtaining the output signal OUT through the inverter 11. However, when the control signal D is set at a high level and the control signal D is set at a low level, the transmission gates 7 and 9 are turned off, and the MOS transistors T7 and T10 are turned on. The power supply voltage Vcc and the ground potential (Vss) are applied to the gates of the MOS transistors T3 and T4, respectively, so that the transistors T3 and T4 are turned off, thereby stopping data transmission through the first and second transmission lines. 
     According to the arrangement described above, the MOS transistors T3 and T4 can be used not only as level shifters but also as transfer gates. The amplitudes of gate voltages of the MOS transistors T3 and T4 are given to be |V1-Vcc| and |V2-Vss|, respectively, so that these amplitudes are smaller than the power supply voltage Vcc. As a result, the ON/OFF operation of the MOS transistors T3 and T4 can be controlled at high speed. This high-speed operation is effective when a plurality of transfer gates are to be simultaneously turned on/off. 
     In the embodiments described above, the capacitor 5 is used as the constant voltage circuit 4. However, instead of incorporating the constant voltage circuit 4, the drain of the MOS transistor T1 can be connected only to the start point of the transmission line L1, and the drain of the MOS transistor T2 can be connected only to the start point of the transmission line L2. In this case, the prescribed effect can still be obtained. Note that, in this case, the MOS transistors T3 and T4 comprise transistors which have a large drive capacity. 
     Constant voltage circuits shown in FIGS. 7, 8, and 9 may be used as the constant voltage circuit 4. Referring to FIG. 7, a constant voltage circuit 4 comprises series-connected diode D1, . . . , and Dn. According to this arrangement, a current supply capacity can be increased to be greater than the capacity of the capacitor 5, so that a higher transmission operation can be performed. Referring to FIG. 8, a constant voltage circuit 4 comprises a series circuit of a p-channel enhancement type MOS transistor T13, whose conduction operation is controlled in response to the first reference voltage V1, and an n-channel enhancement type MOS transistor T14, whose conduction operation is controlled in response to the second reference voltage V2. In this arrangement, a higher packing density can be achieved than in the case wherein the constant voltage circuit comprises a capacitor or diodes. On the other hand, referring to FIG. 9, a constant voltage circuit 4 comprises a series circuit of a p-channel depletion type MOS transistor T15, whose conduction operation is controlled in response to the power supply voltage Vcc, and an n-channel depletion type MOS transistor T16, whose conduction operation is controlled in response to the ground potential Vss. According to this arrangement, the two reference voltage generators for generating the reference voltages V1 and V2 shown in FIG. 8 can be omitted. In particular, when this arrangement is combined with the circuit shown in FIG. 4, the manufacturing process can be simplified.