Abstract:
Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor device, and more particularly, to a semiconductor package for protecting a semiconductor chip and connecting the semiconductor chip with an external device.  
         [0003]     2. Description of the Related Art  
         [0004]     As the integration density of semiconductor chips increases, the number of pads of each semiconductor chip increases. However, semiconductor packages are being continuously demanded to be smaller and lighter with an increasing demand for portable semiconductor products. For example, a chip scale package (CSP) can reduce the size of a semiconductor package by forming terminals on pads of a semiconductor chip.  
         [0005]     However, the terminals of the CSP are required to be large enough to form a stable electrical contact with an external device and to be separated from one another by suitable pitches. For example, when the terminals of the CSP are connected to an external device by solder balls, and the pitch between terminals is less than or equal to a predetermined value, the solder balls may adhere to each other. For example, JEDEC standards prescribe a minimum pitch between the terminals.  
         [0006]     The JEDEC Solid State Technology Association (once known as the Joint Electron Device Engineering Council), is the semiconductor engineering standardization body of the Electronic Industries Alliance (EIA), a trade association that represents all areas of the electronics industry. JEDEC was originally created in 1960 as a joint activity between EIA an NEMA, to cover the standardization of discrete semiconductor devices and later expanded in 1970 to include integrated circuits. JEDEC establishes standards for the spacing of external contacts that lead into integrated circuit and semiconductor device packages. Spacing of the external contacts are important because suppliers of die attach equipment and soldering equipment must know the spacing between the contact leads or pads of a circuit of a device into to attach the circuit or device to a printed circuit board so that the soldered contacts do not interfere with each other.  
         [0007]     However, a decrease in the number of pads of each semiconductor chip requires an increase in the number of terminals of the CSP. Hence, it is difficult to form an increased number of terminals spaced from each other at a predetermined pitch on a small semiconductor chip. As a result, the terminals may extend up to the outside of the semiconductor chip, and thus additional wires for connecting the pads on the semiconductor chip to the terminals may be needed. For example, U.S. Pat. No. 6,001,671, issued to Fjelstad, discloses a semiconductor package in which conductive pads are used as terminals and a semiconductor chip is connected to the terminals by wire bonding.  
         [0008]     However, a method of manufacturing the semiconductor package, which is disclosed in U.S. Pat. No. 6,001,671, is complicated because it requires a wire bonding process. Also, in the method, the conductive pads can only be disposed around the semiconductor chip, thus enlarging the semiconductor package.  
       SUMMARY OF THE INVENTION  
       [0009]     The present invention provides a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch.  
         [0010]     The present invention also provides a method of fabricating the semiconductor package.  
         [0011]     According to an aspect of the present invention, there is provided a semiconductor package including: a semiconductor chip comprising a top surface and a bottom surface, the bottom surface having a plurality of bumps formed thereon; redistribution layer patterns formed under the semiconductor chip, comprising a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part; a patterned insulating layer formed below the redistribution layer patterns, exposing at least a part of the second part of the redistribution layer patterns; and an encapsulation layer exposing a bottom surface of the patterned insulating layer and surrounding the semiconductor chip, the bumps, and the redistribution layer patterns.  
         [0012]     The semiconductor package may further include an organic insulating layer interposed between the redistribution layer patterns and the semiconductor chip, having conductive particles distributed in the organic insulating layer. The first parts of the redistribution layer patterns may be electrically connected to the bumps by the conductive particles of the organic insulating layer.  
         [0013]     The bumps may directly contact the first parts of the redistribution layer patterns.  
         [0014]     According to another aspect of the present invention, there is provided a method of fabricating a semiconductor package, including the operations of: forming a semiconductor chip comprising a top surface and a bottom surface, the bottom surface having a plurality of bumps formed thereon; forming a sacrificial substrate on which redistribution layer patterns comprising first parts facing the bumps and second parts electrically connected to the first parts are formed; disposing the semiconductor chip over the sacrificial substrate on which the redistribution layer patterns are formed, and electrically connecting the bumps to the first parts of the redistribution layer patterns; forming an encapsulation layer on the sacrificial substrate to surround the semiconductor chip on which the redistribution layer patterns are formed; removing the sacrificial substrate so that the redistribution layer patterns are exposed; and forming a patterned insulating layer below the exposed redistribution layer patterns, the patterned insulating layer exposing at least parts of the second parts of the redistribution layer patterns.  
         [0015]     In the operation of electrically connecting the bumps to the first parts of the redistribution layer patterns, an organic insulating layer having conductive particles distributed therein may be used.  
         [0016]     In the operation of electrically connecting the bumps to the first parts of the redistribution layer patterns, the bumps may be physically bonded to the first parts of the redistribution layer patterns. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0018]      FIG. 1  is a cross-section of a semiconductor package according to an embodiment of the present invention;  
         [0019]      FIG. 2  is a bottom view of the semiconductor package of  FIG. 1 ;  
         [0020]      FIG. 3  is a plan view of a sacrificial substrate on which redistribution layer patterns are formed;  
         [0021]      FIGS. 4 through 8  are cross-sectional views illustrating a method of manufacturing the semiconductor package of  FIG. 1 ;  
         [0022]      FIG. 9  is a cross-section of a semiconductor package according to another embodiment of the present invention; and  
         [0023]      FIGS. 10 through 13  are cross-sectional views illustrating a method of manufacturing the semiconductor package of  FIG. 9 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]     The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.  
         [0025]      FIG. 1  is a cross-section of a semiconductor package  100  according to an embodiment of the present invention.  FIG. 2  is a bottom view of the semiconductor package  100 .  FIG. 1  may be a cross-section taken along line I-I□ of  FIG. 2 .  
         [0026]     Referring to  FIG. 1 , a plurality of bumps  110  are formed on a bottom surface of a semiconductor chip  105 . For example, the bumps  110  may be formed on metal pads (not shown) of the semiconductor chip  105 . The metal pads are electrically connected to unit elements (not shown) formed therebelow. The bumps and metal pads provide input and output terminals for connecting the chip  105  to other chips. The internal structure of the semiconductor chip  105  may vary, and accordingly does not limit the scope of the present invention. For example, the semiconductor chip  105  may include a memory device or various types of logic circuits.  
         [0027]     The number of bumps  110  may depend on the number of metal pads, which may vary according to the integration density of the semiconductor chip  105 . For example, as the integration density of the semiconductor chip  105  increases, the number of metal pads increase, and accordingly, the number of bumps  110  may increase. The bumps  110  may include a conductive material, such as, copper or gold. The bumps  110  may have any shape as long as it protrudes from the bottom surface of the semiconductor chip  105 .  
         [0028]     The bumps  110  are electrically connected to redistribution layer patterns  120 . The redistribution layer patterns  120  are conductive members that may serve as terminals which are connected to an external device. Each of the redistribution layer patterns  120  includes a bump contact pattern  122  and a land pattern  124 , which are electrically connected to each other. For example, the land pattern  124  may serve as a terminal which is connected to an external device, and the bump contact pattern  122  may connect the bump  110  to the land pattern  124 . The bump contact pattern  122  and the land pattern  124  are connected by a conductive line  126 .  
         [0029]     The redistribution layer patterns  120 , which are formed on a sacrificial substrate  128  of  FIG. 4 , will now be described in greater detail with reference to  FIG. 3 . The redistribution layer patterns  120  redistribute randomly distributed bumps  110  so that the bumps  110  can be connected to the external device. The redistribution layer patterns  120  may also be used to extend the pitch between adjacent bumps  110 . In this case, the land patterns  124  may have a larger pitch than the bump contact patterns  122 . For example, although the bump contact patterns  122  do not have a JEDEC standard pitch, the land patterns  124  may have the JEDEC standard pitch.  
         [0030]     The shape of the redistribution layer patterns  120  shown in  FIG. 1  is just an example, but the bump contact patterns  122  and the land patterns  124  may have various shapes and be disposed in various configurations. For example, in contrast with  FIG. 1 , the land patterns  124  may be distributed inside and outside the bump contact patterns  122 .  
         [0031]     Furthermore, a surface area of each of the land patterns  124  is larger than that of each of the bump contact patterns  122 . Hence, by using the land patterns  124  as terminals, a sufficient area of contact with the external device can be secured. Each of the redistribution layer patterns  120  may be a gold layer, a nickel layer, a copper layer, or a complex layer which is a stack of at least one of these layers. For example, the redistribution layer pattern  120  may be a complex layer formed by stacking a gold layer, a nickel layer, a copper layer, a nickel layer, and a gold layer.  
         [0032]     Referring back to  FIG. 1 , the bumps  110  and the bump contact patterns  122  are electrically connected to each other by an organic insulating layer  115  in which conductive particles  17  are distributed. For example, the electrical connection of the bumps  110  with the bump contact patterns  122  may be achieved in such a way that a bump  110  and a bump contact pattern  122  are commonly connected to at least one of the conductive particles  117 . The organic insulating layer  115  may include an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), and an anisotropic conductive adhesive (ACA). The conductive particles  117  may include metal particles, for example, gold particles, copper particles, or nickel particles, or particles obtained by plating polymer beads with gold.  
         [0033]     Referring to  FIGS. 1 and 2 , a patterned insulating layer  135  is formed below the redistribution layer patterns  120 , more specifically, below the organic insulating layer  115  that exposes the redistribution layer patterns  120 . The insulating layer  135  has holes  140  through which at least parts of the land patterns  124  are exposed. For example, the insulating layer  135  may include a solder resist layer or a polyimide layer.  
         [0034]     The exposed parts of the land patterns  124  may electrically contact the external device. For example, the exposed parts of the land patterns  124  may be electrically connected to the external device via solder balls. Although the holes  140  are formed outside the semiconductor chip  105  in  FIG. 1 , they may be distributed inside and outside the semiconductor chip  105  according to the configuration of the land patterns  124 .  
         [0035]     A pitch between exposed land patterns  124  may be greater than that between bumps  110  or metal pads. Hence, the bump contact patterns  122 , facing the bumps  110 , may extend using the land patterns  124  having a larger pitch. Thus, the semiconductor package  100  can be reliably connected to an external device having connection pads (not shown) having a larger pitch than the bumps  110  by using the land patterns  124 . In addition, the semiconductor package  100  can be reduced in size by depositing the bumps  100  and the redistribution layer patterns  120  under the semiconductor chip  105 . In other words, the semiconductor package  100  may have a CSP structure.  
         [0036]     An encapsulation layer  130  covers the semiconductor chip  105  below which the redistribution layer patterns  120  and the patterned insulation layer  135  are formed. The encapsulation layer  130  protects the semiconductor chip  105  from external environments.  
         [0037]      FIGS. 4 through 8  are cross-sectional views illustrating a method of manufacturing the semiconductor package  100  of  FIG. 1 . The structure of the semiconductor package  100  may be described with reference to  FIGS. 1 through 3  and corresponding previous descriptions.  
         [0038]     Referring to  FIG. 4 , the semiconductor chip  105  having the plurality of bumps  110  formed thereon is prepared for. The bumps  110  may be formed on the semiconductor chip  105  in a method similar to wire bonding. The bumps  110  help the metal pads of the semiconductor chip  105  to protrude to the outside. Additionally, the bumps  110  may have good adhesion with the metal pads. Accordingly, the bumps  100  should be at least 5 μm large and may be less than several hundreds of μm so as to achieve stable flip chip bonding. For example, the diameter of each of the bumps  110  may range from 10 μm to 200 μm.  
         [0039]     Aside from the formation of the bumps  110  on the semiconductor chip  105 , the sacrificial substrate  128  having the redistribution layer patterns  120  formed thereon is provided. The redistribution layer patterns  120  and the sacrificial substrate  128  may be understood from the descriptions of  FIGS. 1 and 3 . The sacrificial substrate  128  having the redistribution layer patterns  120  formed thereon may be commercially manufactured by plating or other processes.  
         [0040]     The sacrificial substrate  128  may be formed of a material having etch selectivity with respect to the redistribution layer patterns  120 . The sacrificial substrate  128  may be a metal layer, such as, a copper layer or an aluminum layer. As described above, the redistribution layer patterns  120  may be covered with a gold layer.  
         [0041]     Referring to  FIG. 5 , the bumps  110  are electrically connected to the redistribution layer patterns  120  by the organic insulating layer  115  in which the conductive particles  117  are distributed. More specifically, the bumps  110  are electrically connected to the bump contact patterns  122  by one or more of the conductive particles  117 .  
         [0042]     For example, the organic insulating layer  115  may be inserted between the bottom surface of the semiconductor chip  105  and the sacrificial substrate  128 , more specifically; between the bumps  110  and the redistribution layer patterns  120 . The organic insulating layer  115  may be formed before or after flip chip bonding. Thereafter, thermo-compression is applied to the semiconductor chip  105  or the redistribution layer patterns  120 , so that each of the bumps  110  and each of the redistribution layer patterns  120  can commonly contact at least one of the conductive particles  117 . Hence, reliable electrical connection between the redistribution layer patterns  120  and the bumps  110  can be achieved.  
         [0043]     Referring to  FIG. 6 , the encapsulation layer  130  is formed on the sacrificial substrate  128  to surround the semiconductor chip  105  having the redistribution layer patterns  120  formed thereon. The encapsulation layer  130  may be epoxy or encapsulating molding compound (EMC). The encapsulation layer  130  protects the semiconductor chip  105  from a chemical reaction, such as, external physical impact and moisture.  
         [0044]     Referring to  FIGS. 6 and 7 , the sacrificial substrate  128  is removed so that the redistribution layer patterns  120  can be exposed. For example, only the sacrificial substrate  128  may be etched without etching the redistribution layer patterns  120 . The gold layer coated on the redistribution layer patterns  120  protects the redistribution layer patterns  120  from etching.  
         [0045]     Referring to  FIG. 8 , the patterned insulating layer  135  is formed below the redistribution layer patterns  120  which are exposed. More specifically, the patterned insulative layer  135  having the holes  140  through which parts of the land patterns  124  are exposed is formed below the organic insulating layer  115  which exposes the redistribution layer patterns  120 . For example, an insulating layer (not shown) may be formed below the organic insulating layer  115 , and the holes  140  may be formed by patterning the insulating layer using photolithography and an etching technique.  
         [0046]      FIG. 9  is a cross-section of a semiconductor package  200  according to another embodiment of the present invention. The semiconductor package  200  is a modification of the semiconductor package  100 . Hence, descriptions of identical or similar parts of the semiconductor packages  100  and  200  will be omitted, and only differences will now be described. Like reference numerals in the two semiconductor packages  100  and  200  denote like elements.  
         [0047]     Referring to  FIG. 9 , the bumps  110  directly contact the redistribution layer patterns  120 . More specifically, the bumps  110  and the bump contact patterns  122  are physically bonded together to be electrically connected to each other.  
         [0048]     An encapsulation layer  130   a  covers the top surface and lateral surfaces of the semiconductor chip  105 . The encapsulation layer,  130   a  may be further interposed between the-bottom surface of the semiconductor chip  105  and the redistribution layer patterns  120  and between the bottom surface of the semiconductor chip  105  and the patterned insulating layer  135 . In this case, the encapsulation layer  130   a  may be a single layer or a complex layer. For example, the encapsulation layer  130   a  may be a single layer, such as, an EMC layer or an epoxy layer.  
         [0049]     Alternatively, the top surface and lateral surfaces of the semiconductor chip  105  may be covered with an EMC layer or an epoxy layer, and a solder resist layer or a polyimide layer may be interposed between the bottom surface of the semiconductor chip  105  and the redistribution layer patterns  120  and between the bottom surface of the semiconductor chip  105  and the patterned insulating layer  135 .  
         [0050]     The semiconductor package  200  may have the advantages of the semiconductor package  100 . For example, the pitch between land patterns  124  may be greater than that between bumps  110  or metal pads. Thus, by using the semiconductor package  200 , terminals, namely, the land patterns  124 , may have an appropriate pitch. In addition, the semiconductor package  200  can be reduced in size by depositing the bumps  110  and the redistribution layer patterns  120  under the semiconductor chip  105 . In other words, the semiconductor package  200  may have a CSP structure.  
         [0051]      FIGS. 10 through 13  are cross-sectional views illustrating a method of manufacturing the semiconductor package  200  of  FIG. 9 . The method of  FIGS. 10 through 13  is described with reference to the method of  FIGS. 4 through 8 . Like reference numerals in the two methods denote like elements.  
         [0052]     Referring to  FIG. 4 , the semiconductor chip  105  having the plurality of bumps  110  formed on the bottom surface thereof is provided. After or before the preparation of the semiconductor chip  105 , the sacrificial substrate  128  having the redistribution layer patterns  120  formed thereon is provided. A detailed description of the sacrificial substrate  128  can be made with reference to the method of  FIGS. 4 through 8 , so it is omitted.  
         [0053]     Referring to  FIG. 10 , the bumps  110  directly contacts the bump contact patterns  122 . For example, the bumps  110  may be physically bonded to the bump contact patterns  122 . More specifically, the semiconductor chip  105  and the redistribution layer patterns  120  come close to each other so that the bumps  110  can contact the bump contact patterns  122 . Thereafter, thermosonic waves are applied to the semiconductor chip  105  and the redistribution layer patterns  120  which are close to each other. Hence, the redistribution layer patterns  120  and the bumps  110  which contact with each other can be bonded to each other and electrically connected to each other.  
         [0054]     Referring to  FIG. 11 , the encapsulation layer  130   a  is formed on the sacrificial substrate  128  to surround the semiconductor chip  105  and the redistribution layer patterns  120 . The encapsulation layer  130   a  may be a single layer or a complex layer as described above with reference to  FIG. 9 .  
         [0055]     Referring to  FIG. 12 , the sacrificial substrate  128  is removed so that the redistribution layer patterns  120  can be exposed. The removing method is the same as described above in the previous method.  
         [0056]     Referring to  FIG. 13 , the patterned insulating layer  135  is formed below the redistribution layer patterns  120  which are exposed. More specifically, the patterned insulatiive layer  135  having the holes  140  through which parts of the land patterns  124  are exposed is formed below the encapsulation layer  130   a  which exposes the redistribution layer patterns  120 . As described above, the patterned insulating layer  135  may be formed using photolithography and an etching technique.  
         [0057]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.