Abstract:
An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.

Description:
[1]    1. This is a continuation of U.S. Ser. No. 09/433,822, filed Nov. 26, 2000.  
     
    
     
       FIELD OF THE INVENTION  
         [2]    2. The present invention relates to synchronous integrated circuits generally and, more particularly, to a circuit, architecture and method for reducing power consumption in a synchronous integrated circuit.  
         BACKGROUND OF THE INVENTION  
         [3]    3. Present day electrical products often incorporate semiconductor devices. The use of semiconductor devices has enabled electrical products to accomplish tasks more quickly and efficiently than was previously possible. Improvements in the semiconductor devices have included reducing the amount of power consumed by the devices. One way that semiconductor devices can reduce power consumption is a “powered down” or “sleep” mode. In the sleep mode, input buffers and other current sinking elements are disabled. The electronic device enters the “powered down” or “sleep” mode after receiving a power reduction command signal.  
           [4]    4. An example of a conventional power reduction command signal is the Jedec-standard “ZZ” signal. A Jedec-standard package for semiconductor devices such as synchronous integrated circuits defines a “ZZ” input pin. The “ZZ” pin is configured to place the device in a “sleep” mode for reducing power consumption. A synchronous integrated circuit (e.g., an SRAM) is clocked with an externally applied clock signal. The “ZZ” sleep command signal can be activated asynchronously relative to the external clock.  
           [5]    5. According to conventional approaches, before activating the “ZZ” sleep mode, a synchronous integrated circuit is preferably first deselected by controlling chip enable input signals (e.g., CE and/or CEb). Therefore, to effectively use the reduced power “sleep” mode, (i) a relatively complex setup procedure must be followed, (ii) circuitry must be provided for generating the “ZZ” command signal, and a “ZZ” pin must be provided to receive the “ZZ” command signal.  
         SUMMARY OF THE INVENTION  
         [6]    6. The present invention concerns an apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.  
           [7]    7. The objects, features, and advantages of the present invention include providing a circuit, architecture and method for reducing power consumption in a synchronous integrated circuit that may (i) be implemented without the need for a separate sleep pin (ii) eliminate the need for circuitry to generate a sleep signal, and/or (iii) automatically power down a chip that is deselected or unused after a predetermined length of time.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [8]    8. These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:  
         [9]    9.FIG. 1 is a block diagram illustrating a preferred embodiment of the present invention;  
         [10]    10.FIG. 2 is a block diagram illustrating the circuit of FIG. 1 implemented in a synchronous integrated circuit;  
         [11]    11.FIG. 3 is a timing diagram illustrating signals of the circuit of FIG. 1; and  
         [12]    12.FIG. 4 is a block diagram illustrating an alternative embodiment.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [13]    13. Referring to FIG. 1, a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  may have an input  102 , an input  104 , an output  106 , and an output  108 . In one example, a chip enable signal (e.g., CE) may be presented to the input  102 . However, one or more chip select signals may be presented accordingly to meet the design criteria of a particular application. The signal CE may be in an active state (e.g., chip enabled) or an inactive state (e.g., chip not enabled). A clock signal (e.g., CLK) may be presented to the input  104 . The signal CLK may be an external or an internal clock signal.  
         [14]    14. The circuit  100  may be configured to generate an internal select signal (e.g., SELECT) at the output  106  in response to the signal CE. However, one or more internal select signals may be generated accordingly to meet the design criteria of a particular application. The circuit  100  may be configured to generate a sleep signal (e.g., AUTO_ZZ) at the output  108  in response to (i) the signal CE and (ii) the signal CLK. The signal AUTO_ZZ may have an active state (e.g., power consumption reduced) and an inactive state (e.g., full power operation). When the signal CE has been in the inactive state for a predetermined number of cycles of the signal CLK (e.g., N), the signal AUTO_ZZ will generally switch from the inactive state to the active state. When the signal CE enters the active state, the signal AUTO_ZZ will generally switch from the active state to the inactive state. The signal AUTO_ZZ may be used as a control signal. The signal AUTO_ZZ may be used, for example, to control the sleep control logic of a synchronous integrated circuit.  
         [15]    15. The circuit  100  generally comprises a circuit  110  and a circuit  112 . The circuit  110  may be implemented, in one example, as an input buffer. The circuit  112  may be implemented, in one example, as a counter. The circuit  110  may be configured to generate (i) the signal SELECT and (ii) a control signal (e.g., SLEEP) at an output  114  in response to the signal CE.  
         [16]    16. The signal SLEEP may be presented to an input  116  of the circuit  112 . The circuit  112  may be configured to generate the signal AUTO_ZZ in response to (i) the signal SLEEP and (ii) the signal CLK.  
         [17]    17. Referring to FIG. 2, the circuit  100  is shown implemented in the context of a synchronous integrated circuit  120 . The synchronous integrated circuit  120  may be, in one example, an SRAM. However, the circuit  100  may be implemented as other types of synchronous circuits to meet the design criteria of a particular implementation. For example, the circuit  120  may be implemented as an application specific integrated circuit (ASIC). The signal CE may be provided by chip select signals of the synchronous integrated circuit  120 . The signal CLK may be, in one example, provided by an internal clock buffer/generator  122 . The signal SELECT may be presented to select circuitry  124  of the synchronous integrated circuit  120 . The signal AUTO_ZZ may be presented to a sleep control  126  of the synchronous integrated circuit  120 .  
         [18]    18.FIG. 3 is a timing diagram illustrating signals of the circuit  100 . A portion  128  illustrates, in an example operation, that when the signal CE is active (e.g., a logic “1”, or HIGH), the signal AUTO_ZZ will generally remain inactive (e.g., a logic “0”, or LOW). When the signal CE becomes inactive (e.g., a logic “0”, or LOW) at a transition  130 , the circuit  112  generally counts pulses of the signal CLK beginning with the next edge (e.g., a transition  132 ). After the predetermined number of clock pulses N have been counted (e.g., a portion  134 ), the signal AUTO_ZZ generally becomes active (e.g., a logic “1”, or HIGH) at a transition  136 . When the signal CE becomes active (e.g., at a transition  138 ), the signal AUTO_ZZ becomes inactive (e.g., transition  140 ).  
         [19]    19. Referring to FIG. 4, a block diagram of a circuit  100 ′ is shown. The circuit  100 ′ is generally implemented similarly to the circuit  100 . The circuit  100 ′ may have an input  142  and/or an input  144 . The input  144  may be n-bits wide. A enable signal (e.g., ZZ_EN) may be presented to the input  142  of the circuit  100 ′. The signal ZZ_EN may be used to enable or disable generation of the signal AUTO_ZZ. The signal ZZ_EN may be presented, in one example, to the circuit  112 ′.  
         [20]    20. A control signal (e.g., ZZ_CNT) may be presented to the input  144  of the circuit  100 ′. The signal ZZ_CNT may be n-bits wide. The signal ZZ_CNT may be used to program the predetermined number of clock pulses N. The signal ZZ_CNT may be presented, in one example, to the circuit  112 ′.  
         [21]    21. While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. For example, the present invention may be implemented along with one or more portions of U.S. Pat. Nos. 5,935,255, 5,848,014 and 5,789,952, which are each hereby incorporated by reference in their entirety.