Abstract:
A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates in general to computers, and in particular to computer hardware. Still more particularly, the present invention relates to a system, method, and computer program for optimizing power and performance of a device through the use of networked three-dimensional (3D) Voltage Regulation Modules. 
       SUMMARY OF THE INVENTION 
       [0002]    A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event. 
         [0003]    The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed descriptions of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0005]      FIG. 1  is a block diagram of a data processing system in which the present invention may be implemented; 
           [0006]      FIG. 2  depicts exemplary components of the overall system incorporating a common 3D VRM data bus for VRM inter-communication. 
           [0007]      FIG. 3  depicts exemplary components of the overall system incorporating a host controller for direct VRM control. 
           [0008]      FIG. 4  is a high-level logical flowchart of an exemplary set of steps performed to determine if any VRMs in the system require supplemental power due to a critical event. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0009]    With reference now to  FIG. 1 , there is depicted a block diagram of an exemplary computer  100  in which the present invention may be implemented. Computer  102  includes one or more processor cores  104  that are coupled to a system bus  106 . A video adapter  108 , which drives/supports a display  110 , is also coupled to system bus  106 . System bus  106  is coupled via a bus bridge  112  to an Input/Output (I/O) bus  114 . An I/O interface  116  is coupled to I/O bus  114 . I/O interface  116  affords communication with various I/O devices, including a keyboard  118 , a mouse  120 , a Compact Disk-Read Only Memory (CD-ROM) drive  122 , a floppy disk drive  124 , and a flash drive memory  126 . The format of the ports connected to I/O interface  116  may be any known to those skilled in the art of computer architecture, including but not limited to Universal Serial Bus (USB) ports. 
         [0010]    Computer  102  is able to communicate with a software deploying server  150  via a network  128  using a network interface  130 , which is coupled to system bus  106 . Network  128  may be an external network such as the Internet, or an internal network such as an Ethernet or a Virtual Private Network (VPN). Note the software deploying server  150  may utilize a same or substantially similar architecture as computer  102 . 
         [0011]    A hard drive interface  132  is also coupled to system bus  106 . Hard drive interface  132  interfaces with a hard drive  134 . In a preferred embodiment, hard drive  134  populates a system memory  136 , which is also coupled to system bus  106 . System memory is defined as a lowest level of volatile memory in computer  102 . This volatile memory includes additional higher levels of volatile memory (not shown), including, but not limited to, cache memory, registers and buffers. Data that populates system memory  136  includes computer  102 &#39;s operating system (OS)  138  and application programs  144 . 
         [0012]    OS  138  includes a shell  140 , for providing transparent user access to resources such as application programs  144 . Generally, shell  140  is a program that provides an interpreter and an interface between the user and the operating system. More specifically, shell  140  executes commands that are entered into a command line user interface or from a file. Thus, shell  140  (also called a command processor) is generally the highest level of the operating system software hierarchy and serves as a command interpreter. The shell provides a system prompt, interprets commands entered by keyboard, mouse, or other user input media, and sends the interpreted command(s) to the appropriate lower levels of the operating system (e.g., a kernel  142 ) for processing. Note that while shell  140  is a text-based, line-oriented user interface, the present invention will equally well support other user interface modes, such as graphical, voice, gestural, etc. 
         [0013]    As depicted, OS  138  also includes kernel  142 , which includes lower levels of functionality for OS  138 , including providing essential services required by other parts of OS  138  and application programs  144 , including memory management, process and task management, disk management, and mouse and keyboard management. 
         [0014]    Application programs  144  include a browser  146 . Browser  146  includes program modules and instructions enabling a World Wide Web (WWW) client (i.e., computer  102 ) to send and receive network messages to the Internet using HyperText Transfer Protocol (HTTP) messaging, thus enabling communication with software deploying server  150 . 
         [0015]    Application programs  144  in computer  102 &#39;s system memory (as well as software deploying server  150 &#39;s system memory) also include a Voltage Regulation Module Logic (VRML)  148 . VRML  148  includes code for implementing the processes described in  FIGS. 2-4 . 
         [0016]    The hardware elements depicted in computer  102  are not intended to be exhaustive, but rather are representative to highlight essential components required by the present invention. For instance, computer  100  may include alternate memory storage devices such as magnetic cassettes, Digital Versatile Disks (DVDs), Bernoulli cartridges, and the like. These and other variations are intended to be within the spirit and scope of the present invention. 
         [0017]    Note further that, in a preferred embodiment of the present invention, software deploying server  150  performs all of the functions associated with the present invention (including execution of VRML  148 ), thus freeing computer  102  from having to use its own internal computing resources to execute VRML  148 . 
         [0018]    Note also server  150  and Host Control Circuit  302 , shown in  FIG. 3  may utilize a substantially similar architecture as that shown for computer  102 . 
         [0019]    With reference now to  FIG. 2 , a high level illustration detailing exemplary components of the overall system incorporating a common 3D VRM data bus for VRM inter-communication. A computer chip  200  on which 3D VRMs are attached is presented. While VRMs  204   a - n  are shown for exemplary purposes in a two dimensional alignment in  FIG. 2 , VRMs  204   a - n  are arranged in a 3D alignment above the computer chip  200 . VRMs  204   a - n  communicate directly with other VRMs  204   a - n  on a VRM Data Bus  202  using Communication Logics  206   a - n,  which are components of VRMs  204   a - n.  Communication Logics  206   a - n  are internal to the VRMs  204   a - n  and govern the communication of power consumption and operation data to other VRMs Bus&#39;  210   a - n,  of the Power Plane  212 , which is in turn coupled to Circuits  214   a - n,  of Power Island  216 . Concurrently, the VRMs  204   a - n  measure the current power consumption of respective Circuits  214   a - n  coupled to a specific Power Bus  210   a - n,  for which a specific VRM  204   a - n  is connected. 
         [0020]    Assuming for explanatory purposes, that the power consumption level of Circuit  214   a  exceeded a critical level, VRM  204   a  then sends notice, using Communication Logic  206   a,  to all networked VRMs  204   b - n  in Computer Chip  200  to supply surplus voltage through Voltage Vias  208   b - n  to the Power Plane  212 . VRMs  204   a  can then utilize surplus voltage from the Power Plane  212  as supplementary voltage to aid in the powering of critical Circuit  214   a,  until the critical voltage event has subsided. 
         [0021]    Note also each VRM  204   a - n  of the array may be independently preset to output specific voltage levels to guarantee adequate functionality of the Circuit  214   a - n  while and minimizing excess power. The preset voltage levels are determined through characterization and testing of the circuits. 
         [0022]    With reference now to  FIG. 3 , a high level illustration detailing exemplary components of the overall system, incorporating a common Host Control Circuit  302  for 3D VRM control. A computer chip  300  on which 3D VRMs are attached is presented. While VRMs  304   a - n  are shown for exemplary purposes in a two dimensional alignment in  FIG. 3 , VRMs  304   a - n  are arranged in a 3D alignment above the computer chip  300 . The Host Control Unit  302  measure the current power consumption of respective Circuits  306   a - n  for which a specific VRM  304   a - n  is connected. The VRMs  304   a - n  supply a fixed voltage through Voltage Vias  306   a - n  to a specific Power Bus&#39;  308   a - n,  of the Power Plane  310 . The Power Bus&#39;  308   a - n  of Power Plane  310 , are connected using a Voltage Gate  312   a - n  which can open or close to permit the transfer of voltage across Power Buses  312   a - n  of Power Plane  310 . Power Buses  308   a - n  are coupled directly to Circuits  314   a - n,  of Power Island  316  for which a specific Power Bus  308   a - n  is connected. 
         [0023]    Assuming for explanatory purposes, that the power consumption level of Circuit  314   a,  exceeded a critical level, Host Control Circuit  302 , instructs necessary Voltage Gates  312   a - n  in Computer Chip  300  to open as necessary to supply surplus voltage from Power Buses  308   b - n  of Power Plane  312  to Circuit  314   a.  Circuit  314   a  can then utilize the surplus voltage as supplementary voltage to aid in the powering of critical Circuit  314   a,  until the critical voltage event has subsided. 
         [0024]    With reference now to  FIG. 4 , a high-level logical flowchart of an exemplary set of steps performed to determine if any VRMs in the system require supplemental power due to a critical event. After initiator block  402 , the power requirements and current power usage, of associated components, are measured for each VRM in an array of VRMs (block  404 ). Logic in the VRM array then determines if any of the VRMs require additional power to maintain proper operation of connected components (block  406 ). When additional power is required at a critical VRM, the VRM&#39;s logic instructs all noncritical VRMs with surplus power to add surplus voltage to the voltage bus (block  408 ). The VRM&#39;s logic then instructs the critical VRM(s) to utilize surplus voltage from the voltage bus (block  410 ). The surplus power is supplied to components connected to the critical VRM(s) until the critical voltage event has subsided (block  412 ). The process ends at terminator block  414 . 
         [0025]    Although aspects of the present invention have been described with respect to a computer processor and software, it should be understood that at least some aspects of the present invention may alternatively be implemented as a program product for use with a data storage system or computer system. Programs defining functions of the present invention can be delivered to a data storage system or computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g. CD-ROM), writable storage media (e.g. a floppy diskette, hard disk drive, read/write CD-ROM, optical media), and communication media, such as computer and telephone networks including Ethernet. It should be understood, therefore, that such signal-bearing media, when carrying or encoding computer readable instructions that direct method functions of the present invention, represent alternative embodiments of the present invention. Further, it is understood that the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent. 
         [0026]    Having thus described the invention of the present application in detail and by reference to preferred embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims.