Abstract:
A memory storage device connectable to a bus comprises a first memory module that stores data, a second memory module that is capable of being programmed, and a memory controller that communicates with the first memory module, the second memory module, and the bus, and that determines an address mapping of selected areas of the first memory module onto the second memory module. When the memory controller receives an access request from the bus, the memory controller accesses data from the first memory module unless the address mapping specifies that the access request maps to the second memory module, whereupon the memory controller accesses replacement data from the second memory module.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/686,158, filed on Jun. 1, 2005, which is hereby incorporated by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to read-only memories, and more particularly to re-programmable memories. 
     BACKGROUND OF THE INVENTION 
     ROMs (Read-Only Memories) are used in a wide variety of applications, from the BIOS of personal computers to the firmware of consumer electronics devices such as DVD players. The primary distinction between ROMs is whether, and how many times, they can be programmed. The content of a mask ROM is determined by a physical mask used when fabricating the mask ROM. The content of the mask ROM is thus hardwired and cannot be changed after fabrication. Making any changes to future ROMs requires the creation of new masks, an expensive process, and existing ROMs may need to be discarded. Mask ROMs, however, have the advantage of being the least expensive form of ROM to produce. 
     Another form of ROM is a programmable ROM (PROM). A PROM contains internal fuses that are blown to program the chip. An erasable PROM (EPROM) was developed to allow a ROM to be used more than once. These often rely on ultra-violet light shining on the chip through a transparent window in the packaging. Using ultra-violet lamps is impractical for most consumers, and having to physically place an EPROM under a lamp is inconvenient even for sophisticated users. 
     Electrically erasable PROMs (EEPROMs) were developed, which could be erased in place without extra equipment. A variant of the EEPROM is Flash ROM, which can be programmed a great number of times. This convenience comes at the expense of greater cost, making it less than ideal for inexpensive mass production. A modern version of the EPROM is one time programmable (OTP) memory, which can generally only be programmed once. Sacrificing the ability to re-program yields a lower cost for the OTP. OTP memory may, however, be programmed section by section, yielding a pseudo-reprogramming capability (similar to a multi-session CD-R). 
     SUMMARY OF THE INVENTION 
     A memory storage device connectable to a bus comprises a first memory module that stores data, a second memory module that is capable of being programmed, and a memory controller that communicates with the first memory module, the second memory module, and the bus, and that determines an address mapping of selected areas of the first memory module onto the second memory module. When the memory controller receives an access request from the bus, the memory controller accesses data from the first memory module unless the address mapping specifies that the access request maps to the second memory module, whereupon the memory controller accesses replacement data from the second memory module. 
     In other features, the address mapping is based on mapping information stored in the second memory module. The first memory module comprises read-only memory. The first memory module comprises mask read-only memory. The second memory module comprises programmable read-only memory. The second memory module comprises one-time programmable memory. 
     In still other features, the second memory module comprises a user portion and a system portion. The system portion contains the mapping information, which is used to determine address mapping. The user portion contains the replacement data that is selectively accessed instead of data stored in the first memory module. The second memory module further comprises an error correction portion that contains error data that is used to verify contents of the second memory module. The error correction portion contains error data that is used to verify contents of the user portion and the system portion. The error correction portion includes Error-Correcting Code (ECC) data. The system portion contains mapping records. The mapping records are stored in reverse chronological order. One of the mapping records includes data specifying a start of a set of valid mapping records. 
     In other features, the address mapping provided by the memory controller has a page mode where a block of memory of a first size starting at a first address within the first memory module is mapped to a block of memory of the first size starting at a second address within the second memory module. The first address is fixed. The second address is a multiple of the first size. 
     In still other features, the address mapping provided by the memory controller includes a plurality of patches, and each patch specifies a block of memory within the first memory module that is mapped to a block of memory within the second memory module. Each of the patches has a size, starting address for the first memory module, and starting address for the second memory module, which are all set independently for each of the patches. 
     A memory controller for a memory module having a first memory and a second memory comprises a mapping memory that stores mapping data for addresses of the first memory that are to be accessed from the second memory, and a control module that populates the mapping memory with the mapping data, that accesses data from the first memory unless the mapping memory specifies that the access maps to the second memory, and that accesses replacement data from the second memory when the mapping memory specifies that the access maps to the second memory. 
     In other features, the control module stores the mapping data in the second memory. The control module loads the second memory with the mapping data and the replacement data. The control module populates the mapping memory upon at least one of power on, when the second memory changes, and when a first read request is received by the memory controller. The mapping data is read from the second memory. 
     A memory storage device connectable to a bus comprises first storage means for storing data, second storage means capable of being programmed for storing data, and control means, which communicates with the first storage means, the second storage means, and the bus, for determining an address mapping of selected areas of the first storage means to the second storage means. When the control means receives an access request from the bus, the control means accesses data from the first storage means unless the address mapping specifies that the access request maps to the second storage means, whereupon the control means accesses replacement data from the second storage means. 
     In other features, the address mapping is based on mapping information stored in the second storage means. The first storage means comprises read-only memory. The first storage means comprises mask read-only memory. The second storage means comprises programmable read-only memory. The second storage means comprises one-time programmable memory. The second storage means comprises a user portion and a system portion. The system portion contains the mapping information, which is used to determine address mapping. The user portion contains the replacement data that is selectively accessed instead of accessing data stored in the first storage means. 
     In still other features, the second storage means further comprises an error correction portion that contains error data that is used to verify contents of the second storage means. The error correction portion contains error data that is used to verify contents of the user portion and the system portion. The error correction portion includes Error-Correcting Code (ECC) data. The system portion contains mapping records. The mapping records are stored in reverse chronological order, and one of the mapping records includes data indicating a start of a set of valid mapping records. 
     In other features, the address mapping provided by the control means has a page mode, whereby a block of memory of a first size starting at a first address within the first storage means is mapped to a block of memory of the first size starting at a second address within the second storage means. The first address is fixed. The second address is a multiple of the first size. The address mapping provided by the control means includes a plurality of patches, and each patch specifies a block of memory within the first storage means that is mapped to a block of memory within the second storage means. Each of the patches has a size and the size is set independently for each of the patches. A starting address in the first storage means is set independently for each of the patches. A starting address in the second storage means is set independently for each of the patches. 
     A memory controller for a memory module having a first memory and a second memory comprises mapping storage means for storing mapping data for addresses of the first memory that are to be accessed from the second memory, and control means for populating the mapping storage means with the mapping data, for accessing data from the first memory unless the mapping storage means specifies that the access maps to the second memory, and for accessing replacement data from the second memory when the mapping storage means specifies that the access maps to the second memory. 
     In other features, the control means stores the mapping data in the second memory. The control means programs the second memory with the mapping data and the replacement data. The control means populates the mapping storage means at least one of at power on, when the second memory changes, and when a first read request is received by the memory controller. The mapping data is read from the second memory. 
     Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is a functional block diagram of an exemplary memory device according to the principles of the present invention; 
         FIG. 2  is a functional block diagram of an exemplary memory controller according to the principles of the present invention; 
         FIG. 3  is an exemplary data structure for storing mapping information within the system area; 
         FIG. 4  is an exemplary implementation of the programmable memory; 
         FIG. 5  is a diagrammatic example of contents of the system area; 
         FIG. 6  is a flow chart depicting exemplary steps performed by the initialization module; 
         FIG. 7  is a flow chart depicting exemplary steps performed by the control module; and 
         FIG. 8  is a diagrammatic example of an exemplary implementation of the ECC (Error-Correcting Code) area. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module, controller and/or device refers to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. 
     Referring now to  FIG. 1 , a block diagram of an exemplary memory device  100  according to the principles of the present invention is presented. A memory controller  102  communicates with a mask ROM (Read Only Memory)  104  and with a programmable memory  106 . The programmable memory  106  may be flash ROM, OTP (One Time Programmable) memory, or any other suitable programmable memory. The memory controller  102  communicates outside the device  100  via a bus. The programmable memory  106  contains a user area  108 , a system area  110 , and an ECC (Error-Correcting Code) area  112 . The ECC area  112  may protect both the user area  108  and the system area  110 . 
     By combining a mask ROM  104  with a smaller programmable memory  106 , the low cost of a mask ROM can be realized while still allowing for changes via the smaller programmable memory. As is further explained below, the user area  108  contains replacement data and the system area  110  contains instructions as to what portions of the mask ROM  104  are to be replaced with the replacement data from the user area  108 . When the memory controller  102  receives a data request, the memory controller  102  checks whether that access falls within one of the replaced memory regions. If it does, the data is retrieved from the user area  108 ; otherwise data is retrieved from the mask ROM  104 . 
     The memory controller  102  may support both patch mode and page mode. In patch mode, patches of definable sizes from the user area  108  are substituted for data of the mask ROM  104 . In page mode, a single block of memory from the user area  108  is substituted for a fixed block of mask ROM  104 . Page mode may allow less granularity in the size of the page, fixes the position of the page within the mask ROM address space, and has less granularity in the page&#39;s location in the user area  108  than a patch does. While there can be a number of patches, only one page is allowed by the memory controller  102  in this implementation. 
     Referring now to  FIG. 2 , a block diagram of an exemplary memory controller  140  according to the principles of the present invention is depicted. An initialization module  142  populates a map table  144  with mapping information from the system area  110  of the programmable memory  106 . The initialization module may be activated in some implementations when the memory controller  140  is powered on, when an initialization command is received, when a first read command is received, and/or based on other criteria. If an enable flag (not shown) is not set, the initialization module may be prevented from activating in some implementations. When the initialization module  142  is activated, it communicates a wait signal indicating that it is not done to a control module  146  and a multiplexer  148 . While this wait signal is being received, the control module  146  waits for the initialization module  142  to finish. 
     The multiplexer  148  selects either the control module  146  or the initialization module  142  to communicate with programmable memory interface circuitry  150 . The wait signal instructs the multiplexer  148  to choose the initialization module  142 . Once the initialization module completes, the signal it asserts switches from wait to done. At this point, the multiplexer  148  chooses the control module  146  to communicate with the programmable memory interface circuitry  150 . The control module  146  also communicates with ROM interface circuitry  152 . When the control module  146  receives a data request to a certain address from a bus, it consults the map table  144 . If the address is mapped into programmable memory, the control module  146  retrieves the data from programmable memory via the programmable memory interface circuitry  150 . Otherwise, the control module  146  retrieves the data from mask ROM via the ROM interface circuitry  152 . If the enable flag is cleared (not set), the control module  146  may not retrieve data from programmable memory. 
     Most programmable memory, including one time programmable, can be written in sections. Once a section is written, it may not be alterable, though other sections that have not yet been programmed can still be modified. To allow for more flexibility in programming the programmable memory  106  multiple times, records are defined for the system area  110  that contain patch and page information and that indicate whether they are the start of a new set of valid records within the system area. The system area can be arranged so that records are added from the bottom of the system area toward the top and are read from the top of the system area toward the bottom. In this way, the most recent records are read first. 
     Referring now to  FIG. 3 , an exemplary data structure  180  for storing mapping information within the system area  110  is presented. The data structure is an eight-byte record consisting of the bytes APM_INF, P_MODE, MASK, PADRH, PADRM, PADRL, OADRH, and OADRL. The most significant bit  182  of APM_INF, Entry Point, indicates that the data structure  180  is a new entry point of either page mode or patch mode information. In other words, this data structure is the first of a set. When Entry Point is equal to one, the P_MODE byte is valid. The next most significant bit  184  of APM_INF, Valid, indicates that the data structure  180  contains valid patch information. If Valid is equal to one, the patch for the present data structure  180  is loaded. When both Valid and Entry Point are equal to zero, the data structure  180  is not used. In other implementations, APM_INF may indicate the start or end of a set and/or indicate the number of valid records within the set. 
     The upper two bits  186  of P_MODE represent page size. The lower six bits  188  of P_MODE indicate where the replacement page is located in the user area  108  of the programmable memory  106 . P_Addr indicates the starting location of mask ROM that should be replaced by data stored in the user area  108 . O_Addr indicates the starting address within the user area  108  of the patch that will replace this corresponding area in mask ROM  104 . A patch size field indicates how much of mask ROM  104  will be replaced by data in the user area  108  for the particular patch. 
     The lower four bits  190  of MASK store the patch size field. The lower three bits  192  of PADRH are the three most significant bits ( 18  through  16 ) of P_Addr. All eight bits  194  of PADRM represent the next most significant bits ( 15  through  8 ) of P_Addr. All eight bits  196  of PADRL represent the least significant bits ( 7  through  0 ) of P_Addr. All eight bits  198  of OADRH represent the most significant bits ( 15  through  8 ) of O_Addr. All eight bits  200  of OADRL represent the least significant bits ( 7  through  0 ) of O_Addr. 
     Referring now to  FIG. 4 , an exemplary implementation  210  of the programmable memory  106  is depicted. In this implementation  210  the programmable memory is 32 KB in size. The user area is 28,672 bytes (28 KB) in length, located from address 0000h to address 6FFFh. The system area is 448 bytes in length, and occupies addresses from 7000h to 71BFh. Because patch records are eight bytes in size, the system area can hold 56 records (448÷8=56). The system area can therefore be changed a maximum of 56 times. The ECC area is 3648 bytes in length and occupies addresses from 71C0h to 7FFFh. If there is one byte of ECC for every eight bytes of data, 3640 bytes of ECC are needed for the user and system areas ((24672+448)÷8=3640). The ECC area contains the necessary 3640 bytes, plus eight extra bytes. One skilled in the art will recognize that many other implementation permutations are possible. 
     Exemplary values for the fields are now discussed. In this implementation, the page always replaces mask ROM  104  starting at address 60000h. The two-bit page size  186  specifies a 28.4 KB page for a value of 00b, a 2 KB page for a value of 01b, a 4 KB page for a value of 10b, and an 8 KB page for a value of 11b. The 28.4 KB page means that the whole of the user and system areas are devoted to the page, and the page replaces addresses 60000h to 671BFh of mask ROM  104 . 
     The six-bit page placement field  188  determines where in the user area  108  the page is stored. The binary value of the page placement field  188  is multiplied by 512 bytes to determine the programmable memory start address. For a 2 KB page, the page placement field  188  can vary between 0h and 34h. For a 4 KB page, the page placement field  188  can vary between 0h and 30h. For an 8 KB page, the page placement field  188  can vary between 0h and 28h. 
     The four-bit patch size field  190  varies between 0h and 8h. A patch size field  190  of 1h corresponds to a patch size of 64B, 2h corresponds to 512B, 4h corresponds to 2 KB, and 8h corresponds to 4 KB. The patch size field  190  invalidates low order bits from address compare logic. In other words, P_Addr will be aligned to boundaries based upon the size of the patch. For example, a 32 (2 5 ) byte patch causes the lower five bits of P_Addr to be ignored. O_Addr, meanwhile, is aligned to eight-byte boundaries, regardless of patch size. In other words, address comparators ignore the three least significant bits of O_Addr. One skilled in the art will recognize that many other values and bit constructions are possible according to the principles of the present invention. 
     Referring now to  FIG. 5 , a diagrammatic example of contents of the system area  110  is presented. The columns of a table  220  are ECC number  222 , byte address  224 , APM_INF  226 , P_MODE  228 , MASK  230 , P_Addr  232 , and O_Addr  234 . The byte address  224  assumes that the system area  110  occupies programmable memory from address 7000h to 71BFh. ECC numbers  222  are not actually stored in the system area, but are included in the table  220  for reference. Each row (or record) is protected by an ECC byte, and each row of the table  220  will be indicated by the corresponding ECC number  222 . At the time of manufacture, the system area  110  is empty (all-zero in this implementation), and since ECC  1 - 48  have not yet been programmed in this example, they contain all zeroes. ECC  56 , at the end of the system area, was written first. An APM_INF of 8Xh indicates that there is no valid patch information, and that only the page mode (P_MODE) information should be referenced. 
     ECC  54  and  55  were written next, and they supersede the previously written ECC  56 . The APM_INF of ECC  55  (CXh) indicates that there is valid patch information to be read along with P_MODE information. ECC  54  has an APM_INF of 4Xh, which indicates that more valid patch information is to be read, and ECC  54  does not constitute a new set of data records. ECC  52  and  53  were written next, superseding ECC  54  and  55 . The APM_INF of ECC  53  (CXh) indicates that there is valid patch information, as does ECC  52  (APM_INF of 4Xh). 
     Finally, ECC  49 ,  50 , and  51  were written. The APM_INF of ECC  51  (CXh) indicates that it begins a new set of patch data. ECC  50  and  51  also contain valid patch information (APM_INF of 4Xh). The initialization module finds the most recent set of records (ECC  49 - 51 ) to read. ECC  52  through  56  are thus ignored. Page mode information is taken from the first record written in the valid set-ECC  51  in this case. Patch information is taken from the patch records in this set (ECC  49 - 51 ), delineated on one side by an Entry Point bit equal to 1 (ECC  51 ) and on the other by an unwritten APM_INF of 00h (ECC  48 ). 
     The valid ECC ( 49 - 51 ) are parsed as follows. P_MODE information is read from ECC  51 , and is A8h in this case. The page size field (two most significant bits of P_MODE) is 10b, meaning that the page is 4 KB in size. The page placement field (six least significant bits of P_MODE) is 101000b (28h), which means that the 4 KB page is located at 5000h (28h*512=28h*200h=5000h). In this exemplary implementation, the page is always substituted for mask ROM starting at address 60000h. Therefore, the 4 KB section of mask ROM starting at address 60000h (60000h to 60FFFh) is replaced by programmable memory from 5000h to 5FFFh. 
     Looking now at the three valid patches (ECC  49 - 51 ), the MASK of the first patch (ECC  51 ) is 1h, which signifies a 64 byte page. The first patch has a P_Addr of 000000h and an O_Addr of 0240h, meaning that mask ROM memory from 000000h to 00003Fh is replaced with programmable memory from 0240h to 027Fh. The second patch (ECC  50 ) is 512 bytes (MASK of 2h) in size, and replaces mask ROM memory from 012200h (P_Addr is 012345h) to 0123FFh with programmable memory from 0040h (O_Addr is 0040h) to 023Fh. The starting mask ROM address is 12200h, instead of 12345h, because the 512-byte (2 9 ) patch size means that the nine least significant bits of P_Addr are ignored. The third patch is 2 KB (MASK of 4h), and replaces mask ROM memory from 02A800h (P_Addr is 02A9CDh) to 02AFFFh with programmable memory from 0280h (O_Addr is 0280h) to 0A7Fh. Again, the starting mask ROM address is 02A800h because the 11 least significant bits (2K=2 11 ) of P_Addr are ignored. 
     Referring now to  FIG. 6 , a flow chart depicts exemplary steps performed by the initialization module  142 . Control begins in step  302  where an optional ECC check of the system area is performed. If the ECC check is successful, control continues in step  304 ; otherwise control transfers to step  306 , where error handling is performed. In step  304  a memory pointer PTR is initialized to 71B8h, which is the last data record of the system area. Because records are added from bottom to top, the system area is searched from bottom to top until an all zero entry is found. The record prior to the all zero entry is the most recently written system record. The system records are then read from the most recent record down until a start of group is reached, which is signified by an APM_INF of either CXh or 8Xh. 
     In step  308  APM_INF (accessed with PTR offset by zero) is checked against a value 00h. If APM_INF is equal to 00h control transfers to step  310 ; otherwise control transfers to step  312 . In step  312  PTR is decremented and control continues with step  314 . If APM_INF is equal to 00h in step  314 , control transfers to step  316 ; otherwise control transfers to step  318 . In step  318 , if PTR is equal to 7000h, signifying that control has reached the beginning of the system area, control transfers to step  320 ; otherwise control returns to step  312 . In step  316  PTR is incremented and control continues in step  320 . In step  320 , if APM_INF is equal to 4Xh, control transfers to step  322 ; otherwise control transfers to step  324 . 
     In step  322  patch data is read, and control continues in step  323 . In step  323 , if PTR is equal to 71B8h, control transfers to step  306  for error handling; otherwise control returns to step  316 . Error handling is appropriate because the bottom-most record (71B8h) should have an Entry Point value of one (but the APM_CNT here of 4Xh has a most significant bit that is zero). In step  324 , if APM_INF is equal to CXh, control transfers to step  326 ; otherwise control transfers to step  328 . In step  326  patch data is read and control continues in step  330 . In step  328 , if APM_INF is equal to 8Xh, control transfers to step  330 ; otherwise control transfers to step  306  for error handling. Error handling is appropriate because APM_INF should only have assumed the values 4Xh, 8Xh, or CXh. In step  330  page mode information is read and control continues in step  332 , where a done signal is asserted and control ends. In step  310  P_MODE is set equal to zero and control transfers to step  332 . Control could alternately begin reading at the top of the system area in some implementations. In addition, other optimizations are possible, such as sorting the valid patches based on P_Addr to allow for faster searching when identifying whether a particular address has been replaced. 
     Referring now to  FIG. 7 , a flow chart depicts exemplary steps performed by the control module  146 . Control starts at step  382 , where control waits for a program or read request. If the request is to read, control transfers to step  384 ; otherwise control transfers to step  386 . In step  386  the programmable memory is programmed and control continues in step  388 . In step  388  the initialization module is reset, and when the initialization module completes, control returns to step  382 . 
     In step  384  the address of the requested read is latched and control transfers to step  390 . If an enable flag is set, control transfers to step  392 ; otherwise control transfers to step  393 , where the requested address is retrieved from mask ROM and control returns to step  382 . In step  392  control transfers to step  394  if patch and page mode information has been initialized; otherwise control transfers to step  396 . In step  396  the initialization module is activated and upon completion, control transfers to step  394 . 
     In step  394 , if the address is in the page space, control transfers to step  398 ; otherwise control transfers to step  400 . In step  398 , the requested address has been determined to be remapped, and is therefore retrieved from programmable memory; control then returns to step  382 . In step  400  a variable Count is set to the number of valid patches, and control transfers to step  402 . In step  402  Count is compared with zero. If Count is greater than zero, control transfers to step  404 ; otherwise control transfers to step  393 . 
     In step  404 , if the address is in the patch referenced by Count, control transfers to step  398 ; otherwise control transfers to step  408 . In step  408  count is decremented and control returns to step  402 . In step  393  Count is zero, which means that no patches have been found that contain the requested address. Therefore, in step  393 , the requested address is retrieved from mask ROM and control returns to step  382 . There are many other possible implementations of this architecture. For example, variations such as individually enabling patch mode and page mode, and automatically initializing one or the other upon power-on are contemplated. 
     Referring now to  FIG. 8 , an exemplary implementation  500  of the ECC (Error-Correcting Code) area is depicted. In this example, eight bytes of data are combined as a block and matched with one byte of ECC information. For instance, addresses 0000h through 0007h are combined as a first block and matched with an ECC byte at address 7FFFh. A second block of data, from address 0008h to 000Fh, is paired with an ECC byte at address 7FFEh. In this way, data at the top of the user area matches ECC at the bottom of the ECC area. 
     This mapping can be represented mathematically as follows. If the number of address bits is denoted as N (15 in this case), and the number of data bytes matched up with a single ECC byte is 2 raised to the power M (3 in this case), the address of the ECC byte for any given data address is equal to ((2 M −1)&lt;&lt;(N−M)) &amp; ˜(ADDR&gt;&gt;M). The operators signify the following: &lt;&lt;is the left-shift operator,&gt;&gt; is the right-shift operator, ˜ is a bitwise inversion, and &amp; is a bitwise AND. The first term, ((2 M −1)&lt;&lt;(N−M)), remains constant for a given implementation. In this implementation, it is equal to (2 3 −1)&lt;&lt;(15−3)=111b&lt;&lt;12=111000000000000b (7FFFh). For example, the ECC address for data address 000Ah is 7FFFh &amp; ˜(000Ah&gt;&gt;3)=7FFFh &amp; ˜0001h=7FFFh &amp; FFFEh=7FFEh. 
     Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.