Abstract:
An electronic organ having an automatic pedal keying circuit in which a selected pattern of pedal voice notes is played in response to depression of only a single key, which may be a pedal key. When the automatic circuit is effective, normal pedal voice keying operations are disabled, and pedal voices will be keyed in a selected pattern occurring in a timed sequence. The organ is selectively adjustable between a normal playing mode and the playing mode according to the present invention.

Description:
The present invention relates to electronic organs and is particularly concerned with a special electronic organ circuit which, when effective, causes the sounding of rhythmic bass patterns automatically in response to the depressing of a respective key. 
     In a conventional electronic organ, the depressing of a key of any of the solo and accompaniment and pedal manuals will actuate a respective keyer. Various arrangements have been arrived at, from time to time, for effecting automatic actuation of keyers in response to the depression of one or more keys of the keyboards with such automatic keyer actuation sometimes being under the control of timing circuitry. 
     The present invention proposes a sophisticated arrangement in which, when the specialized circuitry of the present invention is effective, effects the sequential sounding of pedal tones according to a predetermined rhythmic time pattern in response to the depressing of a respective pedal key. When the special circuitry of the present invention is effective, the normal pedal circuitry of the organ is made ineffective. 
     With the foregoing in mind, a primary objective of the present invention is the provision of a special circuit arrangement for incorporation in an electronic organ which, when effective, is operable to produce rhythmic bass patterns upon the depression of a respective pedal key. 
     Another object of the present invention is the provision of circuitry of the nature referred to above which is made up of relatively simple components which are readily available and which can readily be incorporated in a circuit according to the present invention. 
    
    
     The exact nature of the present invention will become more apparent upon reference to the following detailed specification taken in connection with the accompanying drawings in which: 
     FIG. 1 is a schematic showing of an organ embodying the present invention. 
     FIG. 2 is a simplified block diagram of the circuit of the present invention. 
     FIG. 3 is a schematic diagram, showing a portion of the circuit of the present invention. 
     FIG. 4 is also a schematic of a portion of the circuit of the present invention. 
     FIG. 5 is a chart indicating the relative timing of two pulse trains used in the present invention and the notes sounded in the pedal voice for each of the patterns in response to the depression of the low C pedal. 
    
    
     BRIEF SUMMARY OF THE INVENTION: 
     According to the present invention, the notes of a group of pedal notes, selected by depressing of a respective pedal key, are sounded in succession according to predetermined selectable rhythm patterns for example, according to Rock, Latin, Boogie, or Waltz patterns. Other rhythm patterns can be selected. 
     A source of pulses, which can be derived from a rhythm unit forming a part of the organ is employed, via suitable circuit components, for routing enabling signals to pedal keyers on the counts desired in conformity with the selected rhythm pattern. 
     The keyers, in turn, supply tone signals via voice circuits and amplifier means to a speaker. 
     The source of pulses is also operable, jointly with the pedal keys, to select the pedal notes to be played on the respective counts and this is accomplished via a matrix of gate elements under the joint control of a switch which is adjusted to select the desired rhythm pattern and pulses which are initiated by pulses from the rhythm unit via appropriate circuitry. 
     The output from the matrix of gate elements and an encoded signal from the pedal keyboard, control a bank of decoders having outputs connected in controlling relation to a first set of gates which gate, or key, tone signals in the form of 4 foot square waves. The 4 foot signals thus supplied are divided down to 8 foot and 16 foot signals and are supplied to respective busses via second keyers which are under the control of the pedal keys. 
     An organ embodying the present invention is a conventional organ, having solo, accompaniment, and pedal keyboards, and can be played in a conventional manner, with each key controlling a keyer for a respective tone. The organ is, however, provided with special circuitry according to the present invention which, when effective, will disable at least the pedal keyboard for normal operation and will, instead, permit playing of the organ with an automatic rhythmic bass, or pedal section, which is initiated by the depressing of a single pedal key, or, in the case of an organ, according to U.S. Pat. No. 3,708,604, by the depressing of a single chord playing key of the accompaniment manual of the organ. 
     In the present invention, a source of rhythm pulses in 3/4 time and source in 4/4 time is provided and for each rhythm pattern, a single one of the sources is selected and is operable for controlling the operation of the circuit, including the counts on which pedal notes sound. 
     The circuitry of the present invention employs integrated circuit techniques and, in most instances, negative logic. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to the drawings somewhat more in detail, and with particular reference to FIG. 1, the electronic organ schematically illustrated therein has a solo manual 1 consisting of conventional keys, an accompaniment manual 2 also consisting of keys and a pedal manual, or clavier, 3, having keys or pedals. When the organ plays in a conventional mode, each of the aforementioned keys, when depressed, will actuate a keyer which will permit a respective tone signal to pass from a tone generator through a keyer and through amplifier and voicing circuits to a speaker. 
     The conventional organ circuitry referred to is well known and is not illustrated or described in detail in the present invention, and application. 
     The organ is, however, provided with switches at 10 and 18 which control the special circuitry which is illustrated and described in detail herein. 
     Referring to FIG. 2, the switch 10 is a manually operable startstop switch which is adapted, when closed, to activate an enabling circuit 12 which, in turn, supplies an enabling signal to a decade counter 14 and to pulse train selector 16. A four position pattern selecting switch 18, in one position, provides a further signal to pulse train selector 16. Selector 16 passes one only of the two inputs 20 and 22 to the output line 23 leading to the clocking input of decade counter 14, depending on the respective position of switch 18. 
     Inputs 20 and 22 of selector 16 are in the form of pulse trains derived, for example, from a rhythm unit forming a part of the organ. The pulse supply at 20 is in 3/4 time, while the pulse supply at 22 is 4/4 time. 
     Specifically, when switch 10 is actuated, pulse train 22 in 4/4 time is selected unless switch 18 is in Waltz (W) position and, in which case, pulse train 20 in 3/4 time is selected. Switch 18, as will be seen, has Rock (R), Latin (L), Boogie (B), and Waltz (W) positions and in the first three named positions does not influence the pulse train selection while in the last named, Waltz (W), position effects, as mentioned, the selection of the 3/4 time train of pulses, 20. The pulses supplied at 20 and 22 are also used in an audio decoding circuit 26. 
     Referring now to FIG. 3, when switch 10 is closed, wire 11 goes low and enables counter 14 and, via invertor 11a, supplies a 1 to one input terminal of each of NAND gates 11c and 11d. When switch 18 is in Waltz position only, wire 11e goes low and supplies a 0 to one input terminal of gate 11d and, via invertor 11f, supplies a 1 to one input terminal of gate 11c. The third input terminal of each of gates 11c, 11d is supplied by pulse trains from the respective sources 20, 22. It will be seen that due to the described circuitry only one of gates 11c, 11d, is effective at one time. 
     Pattern selector switch 18 in each position thereof also enables a respective portion of a pattern-to-pitch selector 24 for a purpose to be explained. 
     The output side of decade counter 14 is connected to the input side of a four-bit latch 28. Latch 28 normally passes data unimpededly but when the clock line goes low, data is clamped in the latch. The output 29 of latch 28 is used as the input to a one of ten decoder 30, which enables one of ten outputs in response to a respective input received from latch 28. 
     Specifically, when an output of decoder 30 is enabled it goes low (0) and, when not enabled, stays high (1). The outputs of one of ten decoder 30 serve two purposes: firstly, the outputs 31 of decoder 30 are used to enable portions of the pattern-to-pitch selector 24, and secondly, to enable portions of the audio decoding circuit 26. 
     The output 33 of pattern-to-pitch selector 24 are supplied as inputs to a pitch transposer 32. The signal from pedal keyboard 34 is encoded into a four-bit binary digital signal by an encoder 36. Encoder 36 will produce a four bit binary word at the output whenever a pedal is depressed, with the binary word thus developed indicating which pedal has been depressed. Encoder 36 also provides a binary word whenever no pedals are depressed. The digital output of pedal board encoder 36 is supplied to and is memorized by a four-bit latch 38. 
     The outputs 39 of latch 38 are used as a further input to pitch transposer 32, while the outputs 41 of pitch transposer 32 are supplied via appropriate gating 84 (FIG. 4) to pitch switches, or gates, 86 which are operable for keying respecting 4-foot pitches covering a range of, say, 25 scale notes. The tone generator 85 supplies the tone signals to the respective keyers at 86 via a cable 87, it being understood that a single output terminal of generator 85 is connected to the input side of a respective keyer by a pertaining wire of cable 87. 
     The particular number of pitches thus keyed can, of course, be varied. The outputs of gates 86 are fed to the frequency dividing circuitry consisting of serially connected frequency dividers 42 and 44, and wherein the 4 foot signals are divided to produce 8 foot signals and 16 foot signals which are then supplied to the inputs of keyers 46 and 48, respectively, and from which keyers, signals are supplied to the voicing means 58, amplifier means 60, and speaker means 62 of the organ. 
     The binary output of pedal board encoder 36 is also fed to a pedal down detect circuit 50 which produces an enabling output whenever any pedal in the pedal board is depressed. The enabling output of pedal down detect circuit 50 is supplied by wire 51 and invertor 57 to the control terminal of a gate 52 to enable the gate whenever a key is depressed. The detect circuit supplies a (0) to the clock input of latch 28 to clamp data therein when no key in the pedal keyboard is depressed. 
     An enabling input to gate 52 from pedal down detect circuit 50 allows the output from audio decoder circuit 26 to pass to a monostable multivibrator 54. The output of multivibrator 54 is fed through a buffering and shaping circuit 56 for control of attack and decay to the control terminals of the 8 foot and 16 foot keyers 46 and 48, respectively. The outputs of keyers 46 and 48, as mentioned, are supplied to buss means leading to conventional voicing, amplifier and transducer circuits 58, 60 and 62, respectively. 
     The output of multivibrator 54, supplied to wire 55, also forms the clocking input to four bit latch 38 which, as mentioned, is connected to the output of pedal board encoding circuit 36. Thus, the output of pedal board encoder 36 is memorized each time the audio decoder circuit 26 causes multivibrator 54 to pulse. 
     The pattern to pitch selector circuit 24, shown in more detail in FIG. 3, consists of a matrix of OR gates made up of four groups, or columns, of OR gates, with each of the groups consisting of ten OR gates. The gates of the four columns of gates are distributed in ten rows with four gates in each row. Each gate has two inputs with one input of each gate in a respective column interconnected while the other input of each gate is interconnected with those of the other gates in the same row. 
     All of the gates of one of the columns of OR gates has an enabling signal (0) supplied to the said one input thereof for each position of pattern select switch 18. 
     On the other hand, the outputs of one of ten decoder 30 supply an enabling signal (0) to the said other input of the gates of a respective row thereof, namely, to the other input of one OR gate in each of the four columns of OR gates for each input signal to the decoder. Thus, for each position of pattern selector switch 18, each of the ten possible outputs of decade counter 14, will enable one OR gate only in the pattern to pitch selector circuit 24. When one of the gates of circuit 24 is enabled, the output goes low (0). 
     Each of the OR gates in the pattern-to-pitch selector circuit 24, as shown in FIG. 3, is marked with a roman numeral. 
     Specifically, the outputs of similarly marked ones of the gates of the pattern-to-pitch selector 24 are connected together or are supplied as inputs to correspondingly marked OR gates 64, each having an output connected to the enabling input of a respective one of the one of 16 decoders of the pitch transposer 32. The gates 64 are marked with the same roman numeral designation as is applied to the gates of the matrix 24 which have the outputs interconnected and connected to the input of the respective gate 64. 
     The audio decoding circuit 26 will be seen in FIG. 3 to comprise a group of NAND gates at 66, 68, 70 and 72, and a further group also NAND gates at 74, 76, 78 and 80. Selected ones of the outputs 31 of one of ten decoder 30 are used as inputs to respective ones of NAND gates, 66, 68, 70 and 72. 
     Each of NAND gates 66, 68, 70 and 72 has multiple inputs which are so connected to the outputs 31 of decoder 30 that the respective gate output stays high (1) except on certain counts of decoder 30. Thus, gate 66 for the Rock pattern is connected so the output goes high (1) on counts 1, 3, 4, 5, 6, 8, 9 and 10 of the 4/4 pulse train and low (0) on counts 2 and 7. For gate 68 for the Boogie pattern, the output goes high (1) on counts 1, 2, 4, 5, 7, 9 and 10 of the 4/4 pulse train and low (0) on counts 3 and 8, while the output of gate 70 for the Latin pattern goes high (1) on counts 1, 4, 5, 6, 9 and 10 of the 4/4 pulse train and low (0) on counts 2, 3, 7 and 8. Gate 72 for the Waltz pattern is connected so the output goes high (1) on counts 1, 5, 6 and 10 of the 3/4 pulse train and low (0) on counts 2, 3, 4, 7, 8 and 9. This relationship is illustrated in FIG. 5 wherein the 3/4 and 4/4 pulse trains are marked with Xs and the notes played for the selective rhythm pattern when a C pedal is depressed are marked below the respective Xs. 
     Each pulse train pattern will be seen to be made up of ten counts, denoted by Xs in FIG. 5. By using ten counts for each pulse pattern, a decade counter can be used at counter 14. 
     Each of gates 66, 68, 70, 72 has the output forming one input of gate 74, 76, 78 and 80, respectively. A second input to NAND gates 74, 76, 78 and 80 is from a respective invertor supplied by a pattern selector switch 18, with the switch providing an enabling level (1) signal to a respective one only of these NAND gates for each of the four positions of switch 18. The third input of each of NAND gates 74, 76 and 78 is from the 4/4 pulse train input 22, while the third input to NAND gate 80 is from the 3/4 pulse train input 20. The output sides of gates 74, 76, 78 and 80 are connected to a wire marked H in FIG. 3 which goes low whenever the output of any of the gates 74, 76, 78 and 80 connected thereto goes low. 
     It will be seen that gate 74, for example, is enabled to cause the output to go low (0) only when switch 18 is in the Rock position, and on respective pulses of the 4/4 pulse train 22 identified above, and when the output of gate 66 is high (1). 
     Gate 76 is similarly under the control of switch 18 in the Boogie position, the above identified pulses of the 4/4 pulse train, and gate 68. 
     Gate 78 is similarly under the control of switch 18 in the Latin position, the above identified pulses of the 4/4 pulse train, and gate 70. 
     Gate 80 is similarly under the control of switch 18 in the Waltz position, the above identified pulses of the 3/4 pulse train, and gate 72. 
     From FIG. 5, it will be seen that each of 4/4 pulse train 22 and 3/4 pulse train 20 utilizes ten pulses before repeating, thus accommodating the system to the use of decade counter 14. 
     The time relation between the counts on which the outputs of gates 74, 76, 78 and 80 are enabled (go low) and the respective counts of the selected pulse train can be seen in FIG. 5. The pulses of the respective pulse trains are marked X in FIG. 5 and the counts on which the outputs of gates 74, 76, 78, 80 go low and notes sound are indicated by the note markings therebeneath. As has been mentioned, the notes indicated in FIG. 5 are the notes which are played when the low C pedal is depressed. 
     The outputs of the aforementioned OR gates indicated at 64 in FIGS. 3 and 4 are used as enabling inputs to a series of nine one-of-sixteen decoders 82, each utilizing thirteen of the output terminals. 
     The outputs of pedal board encoder 36 are used as addressing inputs to each of the group of nine one-of-sixteen decoders 82, causing each to enable, namely, drive low, a respective one of the thirteen outputs utilized whenever the respective decoder is enabled from the pattern to pitch selector 24 via the the respective gate 64. Each output of each of the one-of-sixteen decoders 82 is connected to an input of a respective one of a series of 25 signal transmitting components indicated at 84 and consisting of NAND gates and inverters and having outputs on which signals (1) appear whenever an input thereof goes low due to a signal from the one-of-sixteen decoders. Specifically, a component 84 is considered enabled when the output goes high (1). 
     Each of components 84 has the output connected to a keyer to be enabled thereby. The inputs of components 84, in some cases consisting of a single input and in other cases of multiple inputs, are connected to the output terminals of the decoders 82 in conformity with the following schedule. 
     In the schedule, the decoders are marked 82-1 through 82-9 and the note designation in the columns beneath each decoder number represents an input to the correspondingly designated component 84. 
     For example, the component 84 for note C2, which is midway in the range of notes to be keyed, is a NAND gate having nine inputs, one pertaining to each decoder as will be seen in the schedule. Component 84 for note C1 which is at the bottom of the range of notes, is, on the other hand, an inverter and has only a single input connected to an output of decoder 82-9, as shown in the schedule. Similarly, for uppermost note C3 which is also an inverter which has a single input connected to an output of decoder 82-1. 
     
                       SCHEDULE______________________________________82-1  82-2   82-3   82-4  82-5  82-6 82-7 82-8  82-9______________________________________C2    B1     A=//1  A1    G     F=//1                                E1   D=//1 ClC=//2 C2     B1     A=//1 G=//1 G1   F1   E1    C=//1D2    C=//2  C2     B1    A1    G=//1                                F=//1                                     F1    D1D=//  D2     C=//2  C2    A=//1 A1   G1   F=//1 D=//1E2    D=//2  D2     C=//2 B1    A=//1                                G=//1                                     G1    E1F2    E2     D=//2  D2    C2    B1   A1   G=//1 F1F=//2 F2     E2     D=//2 C=//2 C2   A=//1                                     A1    F=//1G2    F=//2  F2     E2    D2    C=//2                                B1   A=//1 G1G= //2 G2     F=//2  F2    D=//2 D2   C2   B1    G=//1A2    G=//2  G2     F=//2 E2    D=//2                                C=//2                                     C2    A1A=//2 A2     G=//2  G2    F2    E2   D2   C=//2 A=//1B2    A=//2  A2     G=//2 F=//2 F2   D=//2                                     D2    B1C3    B2     A=//2  A2    G2    F=//2                                E2   D=//2 C2______________________________________ 
    
     The outputs of components 84 serve as keying signals to a series of 25 NAND gates generally indicated at 86. The second input to each of the gates 86 is a 4 foot square wave with the pitches distributed over a range of two octaves plus a single note, say, from a C note to the C note two octaves higher. The second inputs to keyers 86, and which are marked with note designations, make up the cable 87 leading to tone generator 85. 
     When the output of one of the gates at 84 is enabled, namely, goes high, it enables the corresponding NAND gate at 86, for passing the four foot square wave frequency to the common output buss 88, and from there to the frequency dividers 42 and 44. The output of frequency divider 42 corresponds to 8 foot tones and is delivered to keyer 46. The output of frequency divider 44 corresponds to 16 foot tones and is delivered to keyer 48. 
     The pedal down detect circuit 50, shown in FIG. 4, comprises four inverters receiving signals from encoder 36 and a fifth invertor supplied by the four invertors. The fifth, or output, invertor presents the enabling signal via invertor 57 to one of the inputs of a two input NAND gate 52 whenever a pedal is depressed. The signal to the second input of NAND gate 52 is supplied via inverter 53 from wire H which, as seen in FIG. 3, is the combined outputs of gates 74, 76, 78 and 80 of the audio decoding circuit. 
     NAND gate 52 will thus have a negative going pulse at the output in conformity with the enabling signal on wire H whenever any of the pedals in the pedal board 34 are depressed. The pulse at the output of gate 52 triggers monostable multivibrator 54, causing it to produce at the output a pulse which triggers a keyer control circuit 56 and thereby actuating keyers 46 and 48 to pass signals to the amplifier-voicing-transducer circuits 58, 60 and 62. The output of monostable multivibrator 54 is also supplied via wire 55 as a clocking input to four bit latch 38 interposed between the output of pedal board encoder 36 and the addressing input of the one-of-sixteen decoders 82. 
     The provisions of the latches, or memories, in the pedal encoder circuit and in the line between decade counter 14 and decoder 30 hold the information required to prevent a choppy sound as a pedal is released prior to actuation of the next pedal to be depressed. 
     In summary, an organist may select any of four rhythm patterns by selecting a corresponding position of selector switch 18. Once the selection has been made, and a pedal is depressed in the pedal board, notes will be sounded in the pedal voices in a pattern similar to the patterns displayed in FIG. 5. 
     The patterns of FIG. 5 show what occurs when the low C pedal is depressed. Depression of any other pedal will move this pattern up a corresponding number of notes along the displayed chart. 
     The organ can, of course, be played in a conventional manner by making the circuitry of the present invention ineffective, as by opening switch 10, and actuating a respective keyer for each key which is depressed. 
     In the conventional organ, circuitry not shown herein, each key of the organ keyboards could be connected in controlling relation to a respective keyer connected between a terminal of the tone generator and the amplifier, voicing and speaker system of the organ. In utilizing the circuit of the present invention, at least the normal pedal keyers are disabled and the keyers 86 are enabled. This can be accomplished by switching of a control voltage. If the circuit of the present invention is employed when chord playing keys of the accompaniment manual are effective, the normal pedal keyers are also disabled and keyers 86 are made effective, as before, by switching a control voltage. 
     The matrix of OR gates at 24 and forming what is referred to as the &#34;pattern-to-pitch selector&#34;, merely represents one form of a matrix arrangement that could be employed for this purpose. For example, the matrix could consist of a diode matrix or read only memorys could be employed or other types of signal transmitting components. In each case, the individual components would include two input terminals with individual columns of the matrix arrangement being selectively enabled via one input with the signals to be conveyed being supplied to the other input of the respective components. In any case, it will be appreciated that integrated circuit techniques can be employed for forming a chip corresponding to matrix 24 `pattern-to-pitch selector`. 
     With reference to the actuating pulses, these are disclosed and described as being derived from respective pulse trains at different tempos but it will be understood that a single course of pulses could be employed while utilizing a pulse stretcher in place of the pulse train selector. 
     Modifications may be made within the scope of the appended claims.