Abstract:
A digital interface for driving at least one complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references is provided. The digital interface includes a first input terminal for receiving a PWM input signal, a first counter stage connected to the first input terminal, and a second counter stage connected to an output of the first counter stage. A toggle stage is connected to the first input terminal and to an output of the second counter stage. A first output terminal is connected to an output of the toggle stage, and is to be connected to a control terminal of the first power element. A second output terminal is connected to the output of the first counter stage for receiving a delayed PWM output signal therefrom, and is to be connected to a control terminal of the second power element. The toggle stage generates a second PWM output signal for the first output terminal. The second PWM output signal is kept at a desired low level in correspondence with switching of the PWM input signal having a lower duration than a predetermined duration.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a digital interface for driving power elements, such as in PWM applications. The present invention relates particularly, but not exclusively, to a digital interface for controlling IGBT power elements, and the following description is made with reference to this field of application for convenience of illustration only.  
         BACKGROUND OF THE INVENTION  
         [0002]    Digital control systems for electronic power devices that drive electric motors are limited to the generation of an input signal, particularly of the PWM type. The input signals are conveniently modulated by digital peripherals integrated in microcontrollers connected to the motors to be driven. However, the output of these digital peripherals cannot be directly connected to the electrical power devices, such as IGBT transistors, for example.  
           [0003]    [0003]FIG. 1 schematically shows a driving stage  1  whose input is connected to a digital peripheral and whose output is connected to the motor. The driving stage  1  essentially comprises an inverting stage  2  and a power branch  3 . The power branch comprises a first power element T 1  and a second power element T 2  in series to each other between a first voltage reference and a second voltage reference. The first voltage reference may be a supply voltage Vcc, and the second voltage reference may be ground GND. The first and second power elements T 1 , T 2  may be IGBT transistors, for example.  
           [0004]    The driving stage  1  has an input terminal IN 1  coupled with the inverting stage  2 , and receives a trigger signal PWM. The driving stage  1  has an output terminal OUT 1  coinciding with the interconnection point of the first and second power elements T 1 , T 2 .  
           [0005]    The first power element T 1  is inserted between the supply voltage reference Vcc and the output terminal OUT 1 , and has a control terminal (gate) G 1  connected to the input terminal IN 1  of the driving stage  1  via the inverting stage  2 . The first power element T 1  is generally indicated as a high-side driver transistor. The second power element T 2  is inserted between the output terminal OUT 1  and the ground reference GND, and has a control terminal (gate) G 2  directly connected to the input terminal IN 1  of the driving stage  1 . The second power element T 2  is generally indicated as a low-side driver transistor.  
           [0006]    When using this type of driving stage during the PWM signal switching, it must be ensured that short-circuits between the high-side and low-side power elements T 1 , T 2  of the power branch  3  are not triggered. For this purpose, a convenient analog interface may be used for generating a delay of the PWM signal applied to the control terminals of power elements T 1  and T 2 . In particular, the analog interface is traditionally mounted on the board and comprises the driving stage  1 .  
           [0007]    One approach is to manufacture an analog interface  4  for generating a desired delay as shown in FIG. 2. The analog interface  4  is inserted between the input terminal IN 1  of the driving stage  1  and the control terminals G 1 , G 2  of the first and second power elements T 1 , T 2 . In particular, the analog interface  4  comprises a first circuit branch  5  and a second circuit branch  6  connect in parallel to each other and inserted between the input terminal IN 1  and the control terminals G 1 , G 2  of the first and second power elements T 1 , T 2 .  
           [0008]    The first circuit branch  5  comprises a first resistor R 1  inserted in parallel with a first diode D 1 , both cascade connected to a first hysteresis block IST 1 . An interconnection point X 1  between the first hysteresis block IST 1  and parallel to the first resistor R 1  and the first diode D 1  is connected to ground GND by a first capacitor C 1 .  
           [0009]    Similarly, the second circuit branch  6  comprises a second resistor R 2  inserted in parallel with a second diode D 2 , both cascade connected to a second hysteresis block IST 2 . An interconnection point X 2  between the second hysteresis block IST 2  and parallel to the second resistor R 2  and the second diode D 2  is connected to ground GND by a second capacitor C 2 . Circuitry controlling the power element collector-emitter voltage VCE can also be used. Although advantageous under many aspects, these known approaches have a major drawback linked to the insertion of additional components on the board comprising the driving stage  1 .  
         SUMMARY OF THE INVENTION  
         [0010]    An object of the present invention is to provide a digital interface for an electric motor control driving stage having structural and functional features to ensure an effective protection from a short-circuit of the power elements inserted in such a driving stage.  
           [0011]    Another object of the present invention is for the digital interface to have a straightforward architecture that can be easily integrated in the digital peripheral together with the driving stage, thus overcoming the limits still affecting prior art devices.  
           [0012]    These and other objects, advantages and features in accordance with the present invention are provided by a digital interface capable of processing the PWM input signal and generating a couple of complementary output signals to be applied to the control terminals of the power elements. These signals have a configurable time interval wherein they are both at zero.  
           [0013]    Based on this solution idea the technical problem is solved by a digital interface as previously indicated and defined in the characterizing part of claim  1 . 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The features and advantages of the interface according to the present invention will be apparent from the following description of an embodiment thereof given by way of a non-limiting example with reference to the attached drawings. In the drawings:  
         [0015]    [0015]FIG. 1 schematically shows a driving stage of power elements for controlling electric motors according to the prior art;  
         [0016]    [0016]FIG. 2 schematically shows an analog interface associated with the driving stage of FIG. 1;  
         [0017]    [0017]FIG. 3 schematically shows a digital interface according to the present invention;  
         [0018]    [0018]FIG. 4 is a timing diagram of signals in the digital interface of FIG. 3;  
         [0019]    [0019]FIGS. 5 and 6 are also timing diagrams of signals in the digital interface of FIG. 3;  
         [0020]    [0020]FIG. 7 schematically shows in detail operation of the interface of FIG. 3; and  
         [0021]    [0021]FIG. 8 schematically shows a counter as used in the digital interface of FIG. 3. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    With reference to the drawings, and particularly to FIG. 3, an embodiment of a digital interface according to the present invention is indicated by reference  10 . The digital interface  10  has at the inputs thereof a first input terminal IN receiving a PWM signal PWM IN, a set terminal INS receiving a set signal Sset, a reset terminal INR receiving a reset signal Sreset and a clock terminal INC receiving a clock signal Sclock. The digital interface  10  also has a first output terminal Out neg and a second output terminal Out dir.  
         [0023]    The digital interface  10  comprises a first counter stage  11  and a second counter stage  12 , as well as a toggle stage  13 , all cascade connected to each other between the input terminal IN and the first output terminal Out neg.  
         [0024]    The first counter  11  is connected to the input terminal IN from which it receives the signal PWM IN and to the set INS, reset INR and clock INC terminals, as well as connected to the second counter  12  for providing it with a first output signal PWM OUT. Advantageously, the first counter  11  is output connected to the second output terminal Out dir for providing it with the first output signal PWM OUT. The second counter  12  is input connected to the first counter  11  from which it receives the first output signal PWM OUT and to the set INS, reset INR and clock INC terminals. The second counter  12  is output connected to the toggle stage  13  for providing it with a delayed signal PWM DEL.  
         [0025]    The toggle stage  13  is input connected to the input terminal IN from which it receives the input signal PWM IN, as well as to the second counter  12  from which it receives the delayed signal PWM DEL, and to the reset INR and clock INC terminals. The toggle stage  13  is also output connected to the first output terminal Out neg for providing it with a second output signal PWM OUT 2 .  
         [0026]    The first output terminal Out neg is connected to a control terminal of a first power element, and the second output terminal Out dir is connected to a control terminal of a second power element. As seen with reference to the prior art, the power elements are a complementary couple of IGBT power transistors T 1  and T 2  connected in an inverter configuration having control terminals G 1  and G 2  connected to the digital interface  10 , for example.  
         [0027]    For a better understanding of the operation of the interface  10  according to the present invention, reference can be made to the signals shown in FIG. 4. In particular, FIG. 4 schematically shows the evolution in time of the input signal PWM IN, as well as the first output signal PWM OUT and the second output signal PWM OUT 2 .  
         [0028]    At time t1, the input signal PWM IN has a rising edge, and by way of the first counter  11  (shift register), it is delayed by n (configurable) periods of the clock signal Sclock for generating the first delayed output signal PWM OUT, which has a rising edge at time t2. At time t1, the second output signal PWM OUT 2  decreases.  
         [0029]    The input signal PWM IN has a decreasing edge at time t3, and as previously explained, the first output signal PWM OUT has a decreasing edge at time t4, delayed by n clock periods with respect to time t3. Only at time t5, delayed by further n clock periods with respect to time t4, the second output signal PWM OUT 2  has a rising edge. This ensures the correct operation of the digital interface  10  whose second output signal PWM OUT 2  switches only after a time period from the first output signal PWM OUT being at zero. This time period corresponds to n clock periods and is thus advantageously configurable by the first and second counters  11 ,  12 .  
         [0030]    [0030]FIG. 5 shows in greater detail the evolution in time of signals in the digital interface  10  in normal operating conditions, i.e., without a rise of the input signal PWM IN preceding the breakdown of the first output signal PWM OUT. The input signal PWM IN has a rising edge at time t1 and goes back to zero at time t3. The first output signal OWM OUT, corresponding to the input signal PWM IN delayed by n clock periods, has a rising edge at time t2 and goes back to zero at time t4.  
         [0031]    [0031]FIG. 5 also shows the evolution of the delayed signal PWM DEL output by the second counter  12 . The delayed signal PWM DEL has a rising edge at time t6, delayed by N clock periods with respect to time t2 and then by 2N clock periods with respect to time t3 when the input signal PWM IN goes back to zero. The second output signal PWM OUT 2  (having a complementary evolution with respect to the first output signal PWM OUT) has a decreasing edge at time t1 and it has again a rising edge only at time t5, delayed by N clock periods with respect to the switching of the first output signal PWM OUT (time t4) and by 2N clock periods with respect to the switching of the input signal PWM IN (time t3).  
         [0032]    [0032]FIG. 6 shows, in greater detail, the evolution in time of signals in the digital interface  10  in anomalous operating conditions, i.e., with a new input signal PWM IN preceding the output signal PWM out breakdown. The input signal PWM IN, as already described in FIG. 5, has a rising edge at time t1 and goes back to zero at time t7. Moreover, it has a new rising edge F 2  at time t8 and decreases again at time t3. The first output signal PWM OUT, corresponding to the input signal PWM IN delayed by n clock periods, rises at time t2 and goes back to zero at time t9 after the new rising edge of the input signal PWM IN (time t8). Afterwards, in response to the new rising edge of the input signal PWM IN, it rises again at time t10 and then decreases at time t4, as described also in FIG. 5.  
         [0033]    [0033]FIG. 6 also shows the evolution of the delayed signal PWM DEL output by the second counter  12 . As also described in FIG. 5, the delayed signal PWM DEL rises at time t6, delayed by N clock periods with respect to time t2 when the first output signal PWM OUT rises, and then by 2N clock periods with respect to time t1 when the input signal PWM IN rises. PWM DEL goes back to zero at time t3, delayed by N clock periods with respect to time t9 when the first output signal PWM OUT goes back to zero for the first time and by 2N clock periods with respect to time t7 when the input signal PWM IN goes back to zero for the first time. Afterwards, PWM DEL rises again at time t11, after the new rising edge F 2  of the input signal PWM IN and decreases at time t5 delayed by N clock periods with respect to time t4 when the first output signal PWM OUT decreases and is delayed by 2N clock period with respect to time t3 when the input signal PWM IN decreases.  
         [0034]    The second output signal PWM OUT 2 , similar to the description of FIG. 5, decreases at time t1 in correspondence with the rise of the input signal PWM IN and rises again only at time t5. This signal is delayed by N clock periods with respect to time t4 when the switching of the first output signal PWM OUT occurs and by 2N clock periods with respect to time t3 related to the switching of the input signal PWM IN. The input signal PWM IN has a new rising edge F 2 , at time t8, before the first output signal PWM OUT output by the first counter  11  decreases at time t9 (it has not decreased to zero yet).  
         [0035]    It results then that the low-high transition of the second output signal PWM OUT 2  (time t5) is delayed by 2N clock periods with respect to the high-low transition of the input signal PWM IN (time t3). The intermediate rising edge F 2  of the input signal PWM IN does not trigger any transition of the second output signal PWM OUT 2 . Therefore, the digital interface  10  according to the invention ensures that the second output signal PWM OUT 2  performs the low-high transition only after the first output signal PWM OUT is in the low condition, thus preventing short-circuits from being triggered in the driven inverter branch.  
         [0036]    To obtain complementary and delayed output signals, the toggle block  13  is configured as shown in FIG. 7. In particular, this FIG. 7 shows a state diagram related to the operation of toggle block  13 , whose implementation can be performed starting from this state diagram. The toggle block  13  substantially comprises a state machine having a first state S 1  referred to as IDLE state, a second state S 2  referred to as WAIT_DELAY state, a third state S 3  referred to as LOW STATE state, and a fourth state S 4  referred to as FRONT IN state and a fifth state S 5  referred to as LOW 2  STATE state.  
         [0037]    The detailed description of the toggle block  13  will not be discussed in any further detail in connection with the operation of the digital interface  10  with reference to FIGS. 5 and 6. In a normal operation of the digital interface  10  (FIG. 5), the toggle block  13  takes in time the following states: up to time t1 and after time t5: state S 1  (IDLE); from time t1 to time t6: state S 2  (WAIT_DELAY); from time t6 to time t3; state S 3  (LOW_STATE); and from time t3 to time t 5 : state S 4  (FRONT_IN). In an anomalous operation of the digital interface  10  (FIG. 6), the toggle block  13  takes in time the following states: up to time t1 and after time t5: state S 1  (IDLE); from time t1 to time t6 and from time t3 to time tll: state S 2  (WAIT_DELAY); from time t6 to time t7 and from time tll to time t4; state S 3  (LOW_STATE); from time t7 to time t8: state S 4  (FRONT_IN) and from time t4 to time t5: state S 4  (FRONT_IN); and from time t8 to time t3: state S 5  (LOW 2 _STATE).  
         [0038]    The toggle block  13  deals with generating the second output signal PWM OUT 2 . In particular, in correspondence with a reset signal Sreset of the digital interface  10 , the second output signal PWM OUT 2  is in a high condition. With particular reference to the state description of FIG. 7, it can be seen that with a rise of the input signal PWM IN (low-high transition), the toggle block  13  passes from state S 1  to state S 2  (connection L 12 ). Similarly, with a rise in the delayed signal PWM DEL, the toggle block  13  passes from state S 2  to state S 3  (connection L 23 ).  
         [0039]    Only with a decrease of the delayed signal PWM DEL (high-low transition), i.e., in the transition from state S 3  to state S 1  (connection L 31 ), and from state S 4  to state S 1  (connection L 41 ), the toggle block  13  allows the second output signal PWM OUT 2  to rise. Therefore, in normal operating conditions, the toggle block  13  cyclically passes from state S 1  to state S 2  (connection L 12 ), from state S 2  to state S 3  (connection L 23 ), from state S 3  to state S 4  (connection L 34 ) and from state S 4  to state S 1  (connection L 41 ).  
         [0040]    If, in anomalous operating conditions (FIG. 6), at time t8 a new rising edge of the input signal PWM IN occurs before the decreasing edge of the delayed signal PWM DEL (time t3), this edge must be ignored. In fact, this event occurs when the input signal PWM IN is at zero for a lower period than the value 2n*T MCK  (T MCK  is the general system clock period), and in this case the second output signal PWM OUT 2  must be still at zero.  
         [0041]    Under similar conditions to the ones just described, the toggle block  13  passes from state S 3  to state S 4  (connection L 34 ), from state S 4  to state S 5  (connection L 45 ) and from state S 5  to state S 2  (connection L 52 ) in correspondence with the high-low-high transitions of the input signal PWM IN (time t7 and t8) and with the high-low transition of the delayed signal PWM DEL (time t3). The toggle block  13  also provides a transition from state S 3  to state S 4  (connection L 34 ) and from state S 4  to state S 1  (connection L 41 ) when the delayed signal PWM DEL goes to zero before the new rising edge of the input signal PWM IN.  
         [0042]    Advantageously, according to the invention, the toggle block  13  manages the transitions of the second output signal PWM OUT 2  and allows the latter to perform a low-high transition only after 2N clock periods occurred with respect to the high-low transition of the input signal PWM IN. This also prevents also sudden switching of the input signal PWM IN from triggering corresponding switching of the second output signal PWM OUT 2 . Therefore, the digital interface  10  comprising the toggle block  13  ensures that output signals PWM OUT and PWM OUT 2  are always complementary and that there is a time in which they are both at zero, thus preventing possible short-circuits in the power transistors of an inverter branch driven by the digital interface  10 .  
         [0043]    For completeness of the description, FIG. 8 shows a counter block, such as the first counter block  11  or the second counter block  12  in the digital interface  10 . In particular, the counter block comprises a shift register having a configurable size synchronized with the general system clock signal Sclock. Moreover, the counter block comprises an output multiplexer receiving the setting signal.  
         [0044]    It is worth noting that, in the case being considered for counter blocks that are effective at generating small delays with respect to the input signal PWM period and which minimize the harmonic distortion of the latter, the shift registers should be very small sized (16 bits at most). To the extent that it is necessary to insert higher delays, it is possible to reduce the system clock signal Sclock, which is also used for generating the input signal PWM, to minimize the harmonic distortion.  
         [0045]    In conclusion, the digital interface  10 , according to the invention, allows power elements for motor control to be driven, thus ensuring prevention of short-circuits between the power elements of a same inverter branch during the input signal PWM switching. The manufactured digital interface disregards the variability of the features of the power elements being driven.  
         [0046]    The digital interface  10  manufactured according to the invention has been formed in 0.35 um CMOS technology, thus obtaining an area occupation of about 0.008 mm 2 . By comparing this area with the traditional size of a 8-bit microcontroller, manufactured in the same technology and corresponding to about 20 mm 2 , it is evident that the area increase (and thus the cost increase) due to the integration of the digital interface  10  is totally negligible if compared to the benefits in terms of operation safety and to the absence of further elements to be integrated in the board comprising the microcontroller. The advantage of performing an integrated digital control and the total absence of analog interfaces complicating the on-board system manufacture add thereto.