Abstract:
The present invention relates to a single-ended push-pull type inverter. Such inverter in the prior art generated a large through-current flowing through series-connected output transistors. This large through-current caused not only a large power consumption but also an instability of the entire circuit including the inverter. The present invention improves these disadvantages by inserting a phase inverter stage having a current regulating function just before the output transistors and includes a first transistor having a base receiving an input signal, the phase inverter stage having an input end connected to the collector of the first transistor, a second and a third transistor connected in series, the bases of the second and third transistors being electrically connected, respectively, to the collector of the first transistor and output end of the phase inverter stage and an output terminal connected to the circuit portion connecting the second and third transistors.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a single-ended push-pull circuit (hereinafter referred to as SEPP circuit) and, more particularly, to an SEPP circuit suited as an inverter. 
     SEPP circuits have been widely used in logic and linear circuits. Particularly, such circuits are successfully applied in inverters used for level conversion or for driving an external load. In inverters used for these purposes, it must be taken into consideration that the power consumed at the time of change in output level should be small and that the inversion operation should not result in instability of other circuits driven by the same power source in addition to the basic requirement that the output satisfies the required output voltage level and changes rapidly. 
     There has been widely known a circuit formed of an input transistor receiving an input signal at its base, a first output transistor having a base connected to the collector of the input transistor, a second output transistor having a base connected to the emitter of the input transistor, and a circuit portion connecting the emitter of the first output transistor and the collector of the second output transistor to an output terminal. The collector-emitter paths of the first and second output transistors are connected in series. While the second output transistor receives a signal having a same phase as the input signal, the first output transistor receives the input signal after inversion by the input transistor. Thus, in theoretical operation, the first and second output transistors turn on and off, or off and on, respectively, at the same time. However, in practice, a transistor has a delay time for switching its operational condition. Due to this delay time, after the polarity of the input signal changes, there is a time duration when both of the output transistors keep their on-state causing flow of so-called &#34;through-current&#34; through the emitter-collector paths of both output transistors. This results in lowering of the voltage of the power source. This through-current results in not only an increment of power consumption but also in instability of the circuit operation of other circuits driven by the same power source. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide an inverter using an SEPP circuit which produces little through-current. 
     It is still another object of the present invention to provide an inverter using an SEPP circuit which consumes little power at change in output level and the operation of which does not affect the operation of other circuits driven by the same power source. 
     It is another object of the present invention to provide an improved SEPP circuit suitable for an inverter. 
     An SEPP circuit according to the present invention has an input terminal and an output terminal. An input signal is applied to a first transistor through the input terminal. The output from the first transistor is applied to an input end of a phase inverter stage having an output and a common end. The output from the first transistor is also applied to a second transistor, and the signal at the output end of the phase inverter stage is supplied to a third transistor. The second and third transistors have their collector-emitter paths connected in series to effect a push-pull circuit operation. The output terminal is coupled to the circuit part interconnecting the second and third transistors. 
     The phase inverter stage includes a fourth transistor having base and collector connected respectively to the input and output ends, and a resistive element connected between the common end and the emitter of the fourth transistor. The collector current of the fourth transistor is restricted by the resistive element, and therefore the phase inverter stage has a current regulating function for regulating the current flowing therethrough to reduce its switching delay. 
     Favorably, a diode is connected between the output end of the first transistor and the input end of the second transistor, and the common end of the phase inverter stage is connected to the input end of the second transistor. Therefor, the difference is forward voltage drops between the diode and the base-emitter diode of the fourth transistor is applied between the both ends of the resistive element. Since values of the forward voltage drops are constant, a constant current flows through the resistive element and the collector current of the fourth transistor is determined by the resistavce value of the resistive element and the constant voltage difference. In other words, regulating the collector current of the fourth transistor becomes earily, and further desired current value is obtained. 
     According to the present invention, the output from the first transistor is applied to the second transistor with substantial no time delay, and is further applied to the third transistor via the plase inverter stage with phase inverted and with a sligh time delay. Therefore, the approximately simultaneous changes in operating states of the second and third transistors are attained, thereby producing a remarkable reduced through-current. 
     As mentioned above, the SEPP circuit of the present invention reduces the through-current extremely. This contributes to elimination of the large change in voltage of the power supply. Further, due to this stabilization of the power supply voltage, operation of the SEPP according to the present invention does not affect the operation of other circuits driven by the same power supply. 
     Further, difference in the threshold voltages of the second and third transistors is unavoidable. If such difference exists in an SEPP circuit, the through-current cannot be prevented by a phase inverter stage without the current regulating function. The resistive element in the phase inverter stage controls the switching time of the fourth transistor by adjusting its resistance value. Thus, the switching time of the third transistor can be controlled by the resistance element to compensate for the difference in threshold voltages of the second and third transistors. In other words, even if the threshold voltages of the second and third transistors are different from each other, the through-current can be substantially eliminated by adjusting the resistance value of the resistive element. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and further objectives, features and advantages of the present invention will become more apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings: 
     FIG. 1 is a circuit diagram which show an inverter circuit of the prior art; 
     FIGS. 2(a), 2(b) and 2(c) are waveform diagrams which show an input signal, an output signal and a power supply voltage in the circuit shown in FIG. 1; 
     FIGS. 3(a), 3(b), 3(c) and 3(d) are voltage waveform diagrams which explain the shortcoming possessed by the circuit shown in FIG. 1; 
     FIG. 4 is a circuit diagram of an inverter circuit according to one preferred embodiment of the present invention; 
     FIGS. 5(a), 5(b) and 5(c) are voltage waveform diagrams showing an input signal, an output signal and a power supply voltage of the circuit shown in FIG. 4; 
     FIGS. 6(a), 6(b), 6(c) and 6(d) are voltage waveform diagrams for explaining the advantageous operation of the circuit shown in FIG. 4; and 
     FIG. 7 is a circuit diagram of an inverter circuit according to another preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PRIOR ART 
     One example of the inverter in the prior art will be described in more detail with reference to FIG. 1. An input signal V IN  is applied to an input terminal 1 which is connected via a resistor R 1  to a base of a transistor Q 1 . The transistor Q 1  has an emitter grounded through a resistor R 3  and a collector connected via a resistor R 2  to a power supply 3 (having a voltage V CC ). Also, the collector and emitter of the transistor Q 1  are connected to bases of a transistor Q 2  and a transistor Q 3 , respectively. The collector of the transistor Q 2  is connected via a resistor R 4  to the power supply 3. The emitter of the transistor Q 3  is grounded. The emitter of the transistor Q 2  and the collector of the transistor Q 3  are connected in common to an output terminal 2. 
     When a high level signal is applied as the input signal V IN  to the input terminal 1, the transistor Q 1  becomes conducting. Hence, the transistor Q 2  is turned OFF, while the transistor Q 3  is turned ON, and thereby a low level signal can be obtained as an output signal V OUT  at the output terminal 2. On the other hand, when a low level signal is applied as the input signal V IN , the transistor Q 1  is turned ON. Hence, the transistor Q 2  is turned ON and the transistor Q 3  is turned OFF, so that a high level signal can be obtained as the output signal V OUT  at the output terminal 2. 
     Thus, as shown in FIGS. 2(a), 2(b) and 2(c), in response to an input signal V IN  applied to the input terminal 1 (FIG. 2(a)), an output signal V OUT  (FIG. 2(b)) that is an inversion of the input signal V IN  is derived from the output terminal 2. In this instance, due to delay in switching of the transistor Q 1 , during the ON period of the transistor Q 2  there exists a certain time interval when the transistor Q 1  is still ON. As a result, the aforementioned through-current flows momentarily, thereby generating a voltage drop in the power supply voltage V CC  (FIG. 2(c)). 
     FIGS. 3(a) to 3(d) illustrate signal waveforms at various points in the circuit of FIG. 1 for explaining the through-current in greater detail. When an input signal V IN  having the waveform shown in FIG. 3(a) is applied to the input terminal 1, a signal V CQ1  having a delay corresponding to a switching time possessed by the transistor Q 1  is produced at the collector of the transistor Q 1  as shown in FIG. 3(b). This signal V CQ1  is applied to the base of the transistor Q 2 . This delay is proportional to the quantity of electric charge stored in the collector of the transistor Q 1 . On the other hand, at the emitter of the transistor Q 1  is produced a signal V EQ1  having approximately the same waveform as the input signal V IN  and having little delay time as shown in FIG. 3(c). This signal V EQ1  is applied to the base of the transistor Q 3 . 
     When no input signal or low level of the input signal V IN  is applied to the input terminal 1, while a current flows into the base of the transistor Q 2  through the resistor R 2  to turn the transistor Q 2  on, the base of the transistor Q 3  receives no current to turn off. Thus, at the output terminal 2, a high level output signal V OUT  is produced. In response to a rise of the input signal V IN , the emitter voltage V EQ1  of the transistor Q 1  rises quickly as shown in FIG. 3(c). When the emitter voltage V EQ1  reaches the threshold voltage V Q3  of the transistor Q 3 , the transistor Q 3  turns on. However, the collector voltage V CQ1  of the transistor Q 1  lowers after some delay time, as shown in FIG. 3(b). When the collector voltage V CQ1  reaches the threshold voltage V Q2 , the transistor Q 2  turns off. As a result, there exists a time duration T ON1  when both the transistors Q 2  and Q 3  turn on. In the time duration T ON1 , a large through-current I CP  flows through the transistors Q 2  and Q 3  from the power supply 3. The value of the through-current I CP  is represented by the following equation: ##EQU1## where R SCQ2  and R SCQ3  represent saturated resistances of the transistors Q 2  and Q 3 , respectively, R 4  represents the resistance value of the resistor R 4 , and R CC  represents the internal resistance of the power supply. 
     This through-current I CP  makes the power consumption large. Further, due to this through-current I CP , a voltage drop V CP  determined by the internal impedance of the power supply 3 is produced in the power supply voltage V CC  as shown in FIG. 3(d). This voltage drop V CP  affects various circuits driven by the same power supply 3 such that it is applied to the various circuits as a parasitic signal and results in oscillation, and therefore, the above-described inverter in the prior art has shortcomings that the entire circuit including the inverter becomes unstable. 
     In order to obviate the above-mentioned shortcomings, it will be conceived to reduce the delay time in the collector output V CQ1  of the transistor Q 1  shown in FIG. 3(b) or to lower the through-current I CP . The lowering of the through-current I CP  can be achieved by increasing the resistance of the resistor R 4  or the saturated resistances R SCQ2  and R SCQ3  of the transistors Q 2  and Q 3  according to Equation (1). However, increase of the resistance of the resistor R 4  or the saturated resistances R SCQ2  and R SCQ3  results in an increase of voltage drop across the respective resistor or transistor. Consequently, the output signal V OUT  at the output terminal 2 would be unable to swing fully up to the ground level or the V CC  level, and so, a predetermined output level could not be realized. Moreover, since the increase of the saturated resistances R SCQ2  and R SCQ3  causes the output current of the transistors Q 2  and Q 3  to decrease, the load connected to the output terminal 2 cannot be fully driven. Reduction of the delay in the collector voltage V CQ1  of the transistor Q 1  can be realized by decreasing the quantity of electric charge stored in the collector either by reducing collector capacitance of the transistor Q 1  or by reducing current flowing through the collector. However, reduction of the collector capacitance means reduction of a collector area of the transistor Q 1 , and hence the current capacity of the transistor Q 1  becomes small. As a result, it becomes impossible to drive the transistor Q 2  to a sufficient extent, and so, the desired output signal amplitude cannot be obtained. In addition, reduction of the current flowing through the transistor Q 1  can be realized by increasing the resistance of the resistor R 2 . However, since drive of the transistor Q 2  is effected through the resistor R 2 , it becomes impossible to drive the transistor Q 2  to a sufficient extent. Moreover, as the voltage drop across the resistor R 2  is increased, it becomes impossible to realize a desired output signal amplitude because the high level of the output signal is determined by the voltage drop across the resistor R 2 . 
     As described above, although various approaches for reducing the through-current can be conceived, so long as the circuit construction as illustrated in FIG. 1 is employed, other important electrical performance is deteriorated such that drive of the load is insufficient or a desired output signal level cannot be obtained. 
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 4 is a circuit diagram of an inverter according to one preferred embodiment of the present invention. This circuit includes a first transistor Q 4  of NPN-type, a second transistor Q 5  of PNP-type, a third transistor Q 6  of NPN-type and a fourth transistor Q 7  of NPN-type. The base of the transistor Q 4  is connected via a resistor R 5  to an input terminal 1. The emitter of the transistor Q 6  is directly connected to the collector of the transistor Q 7  and to an output terminal 2. The emitter of the transistor Q 7  is grounded. The collector of the transistor Q 6  is connected via a resistor R 9  to a V CC  power supply 3. Thus, the serially-connected transistors Q 6  and Q 7  form an output stage of the inverter. 
     In addition, the collector of the transistor Q 4  is connected to the base of the transistor Q 5  and a cathode of a diode D 1 . The emitter of the transistor Q 5  is connected via a resistor R 7  to the base of the transistor Q 6  and the anode of the diode D 1 . The anode of the diode D 1  is connected to the V CC  power supply 3 through a transistor Q 9  which forms a constant current source in cooperation with transistors Q 8  and Q 10  and a resistor R 6 . The constant current source is used for the purpose of stabilization of operation levels. The collector of the transistor Q 5  is connected to the base of the transistor Q 7  and is further connected via a resistor R 8  to ground. 
     Accordingly, the circuit shown in FIG. 4 differs from the circuit shown in FIG. 1 in that a phase inverter stage including resistor R 7  and second transistor Q 5  of PNP-type, is inserted between the collector of the first transistor Q 4  and the base of the fourth transistor Q 7 . Further, the collector output of the transistor Q 4  is supplied through the diode D 1  to the base of the transistor Q 6 . The phase inverter stage has an input end connected to the collector of the transistor Q 4 , an output end connected to the base of the transistor Q 7  and a common end connected to the base of the transistor Q 6 . 
     Assuming now that a high level input signal V IN  has been applied to the input terminal 1, then the transistor Q 4  turns ON, and hence the transistor Q 5  also turns ON. Accordingly, a current fed from the transistor Q 9  flows through the transistors Q 4  and Q 5 , so that the transistor Q 7  turns ON. The conducting state of the transistor Q 4  lowers the base voltage of the transistor Q 6  to turn it OFF. As a result, a low level output signal V OUT  is obtained at the output terminal 2. In the event that a low level input signal V IN  has been applied to the input terminal 1, the transistor Q 4  is turned OFF, hence the transistor Q 5  is also turned OFF, and so, the transistor Q 7  is turned OFF. Since the current fed from the transistor Q 9  is supplied to the base of the transistor Q 6 , this transistor Q 6  is turned ON. Accordingly, a high level output signal V OUT  is obtained at the output terminal 2. In other words, as shown in FIGS. 5(a) and 5(b), an output signal V OUT  which has an inverted waveform of the input signal V IN  is derived from the output terminal 2. Furthermore, since generation of a large through-current does not flow through the transistors Q 6  and Q 7  as explained hereinafter, voltage fluctuation of the power supply 3 is very small as shown in FIG. 5(c). 
     Now the circuit operation will be explained in greater detail with reference to the signal waveforms at various points in the circuit illustrated in FIG. 6. 
     When an input signal V IN  as shown in FIG. 6(a) is applied from the input terminal 1 to the base of the transistor Q 4 , the transistor Q 4  is turned ON and produces a collector signal V CQ4  at the collector of the transistor Q 4  after some delay time corresponding to a switching time elapses, as shown in FIG. 6(b). In response to an application of the low level of this collector signal V CQ4  to the base of the transistor Q 6  through the diode D 1 , the transistor Q 6  turns off quickly. Simultaneously, the collector signal V CQ4  is applied to the base of the transistor Q 5  to turn it on. The collector signal V CQ5  is shown in FIG. 6(c). As a result of turning on the transistor Q 5 , a current from its collector turns the transistor Q 7  on. Thus, a low level output is produced at the output terminal 2. At this time, since the transistor Q 6  is turned off without substantial time delay, even if a time delay appears in the collector signal V CQ5 , very little through-current flows through the transistors Q 6  and Q 7 . 
     On the other hand, when the input signal V IN  turns to low level, the transistor Q 4  turns off to raise the signal level of the collector signal V CQ4  after some time delay, as shown in FIG. 6(b). The rise of signal level is applied to the base of the transistor Q 6  to turn it on. The rise of signal level is also applied to the transistor Q 5  to turn it off. At this time, since the collector current of the transistor Q 5  is restricted by the resistor R 7 , the transistor Q 5  outputs its collector signal V CQ5  with a slight time delay in comparison with the collector signal V CQ4  of the transistor Q 4 . Therefore, the transistor Q 6  turns to ON state almost simultaneously as the transistor Q 7  turns to OFF state. Consequently, the output signal at the output terminal 2 takes a high level, and the through-current is reduced remarkably. 
     In addition, although the transistors Q 6  and Q 7  change their operating states when their input signal voltage reaches their threshold voltages V Q6  and V Q7 , these threshold voltages V Q6  and V Q7  are rarely made the same. If these threshold voltages V Q6  and V Q7  are different from each other, simultaneous switching cannot be achieved. This is shown in FIGS. 6(b) and 6(c). By the difference of the threshold voltages, while the transistor Q 6  turns its conductive state at the time of a and a&#39;, the transistor Q 7  turns at the time of b and b&#39;. As a result, some through-current can be generated in the time duration T ON2  as shown in FIG. 6(d). 
     According to the preferred embodiment shown in FIG. 4, this difference in the threshold voltage may be compensated by the resistor R7 to coincide the times a and a&#39; with the times b and b&#39;. More specifically, the switching voltage of the transistor Q 5  can be adjusted by the resistance of the resistor R 7 . Since the collector signal V CQ4  of the transistor Q 4  has some inclination as shown in FIG. 6(c), the switching time of the transistor Q 5  can be adjusted by the resistor R 7 . This fact means that the switching time of the transistor Q 7  can also be adjusted. Thus, by controlling the resistance of the resistor R 7 , the difference in threshold voltages between the transistors Q 6  and Q 7  can be compensated to minimize the time duration when the through-current flows. 
     The resistor R 7  further gives an improvement in the switching chracteristics of the transistor Q 5  as described hereinbefore. As shown in FIGS. 6(b) and (c), the collector signal V CQ5  of the transistor Q 5  has very little time delay with respect to the collector signal V CQ4  of the transistor Q 4 . This is due to the fact that the current flowing through the transistor Q 5  is limited by the resistor R 7  and thereby the electric charges stored in the collector are reduced. More particularly, the resistor R 7  and the base-emitter path of the transistor Q 5  form a closed loop jointly with the diode D 1 . Accordingly, if the forward voltage of the diode D 1  is denoted by V F , the base-emitter voltage of the transistor Q 5  is denoted by V BEQ5  and the resistance of the resistor R 7  is denoted by R 7 , then disregarding a base current, the current flowing through the transistor Q 5  is determined by the following formula: ##EQU2## Since the parameters V F  and V BEQ5  are dependent upon the semiconductor material, the current value represented by the above formula can be controlled by the resistance of the resistor R 7 . As a matter of course, in order that the formula (2) is valid, the PN-junction area of the diode D 1  is selected to be larger than the base-emitter junction area of the transistor Q 5 . In this embodiment, the former is four times as large as the latters. By appropriately selecting the resistance of the resistor R 7 , the current flowing through the transistor Q 5  is preset and also the current value is held small so that the transistor Q 5  stores a reduced electric charge in its collector. As a result, delay of the collector output V CQ5  of the transistor Q 5  with respect to its base input is reduced to a very small value. Since the transistor Q 6  is driven by the current from the transistor Q 9 , the transistor Q 6  is fully driven in spite of the decrease in the current through the transistor Q 5 . However, since the transistor Q 7  is driven by the current from the transistor Q 5 , the current flowing through the transistor Q 5  should not be too small to drive the transistor Q 7 . Hence, from such viewpoint, in the illustrated embodiment the resistance R 7  is set at 300Ω and the current flowing through the transistor Q 5  is set at 200 μA. Further, if the transistor Q 7  is saturated by the current through the transistor Q 5 , a delay in switching of the transistor Q 7  may become a problem. Therefore, the base current of the transistor Q 7  is regulated by selecting the resistance of the resistor R 8  at 6 KΩ. Incidentally, the resistor R favorably has a value of 200 to 450Ω  from the view points of the insufficient drive and the over drive of the transistor Q 7 . As explained above, the inverter of the preferred embodiment minimizes through-current by a simple modification. For example, while the through-current of the inverter in the prior art shown in FIG. 1 is 12 mA, that of the embodiment shown in FIG. 4 is reduced to 2 mA by setting the resistances of the resistors R 7 , R 8  and R 9  at 300Ω, 6 KΩ and 200Ω, respectively. 
     FIG. 7 is a circuit diagram of an inverter according to another preferred embodiment of the present invention. 
     The difference of the circuit according to this preferred embodiment from the circuit according to FIG. 4 is only that the emitter of the output transistor Q 6  is not directly connected to the collector of the transistor Q 7  but is connected to it through a diode D 2 . This diode D 2  is inserted for the purpose of stabilizing the level at the output terminal 2. In this modified circuit also, the circuit consisting of the transistor Q 5 , diode D 1  and resistor R 7  is inserted between the driver transistor Q 4  and the output transistors Q 6  and Q 7 . Therefore, the same effect as that in the circuit according to the proposed embodiment shown in FIG. 4 can be achieved. 
     While the above description of the present invention has been constructed by the transistors Q 4 , Q 6  and Q 7  of NPN transistors and the transistor Q 5  of a PNP transistor, it is a matter of course that the present invention is equally applicable to the case where transistors of the opposite polarity type are employed. 
     As described in detail above, the inverter according to the present invention produces very little through-current and thereby reduces the voltage drop of the power supply voltage to a negligible value. Accordingly, power consumption can be reduced to a very small value. Moreover, an instability of a circuit including the inverter, such as oscillation, which has been caused by a large through voltage in the prior art, can be prevented. Still further, since insufficient drive for the output transistors will not occur, a desired output amplitude at a desired output signal level can be obtained for a desired load. 
     The present invention is not limited to only the illustrated two embodiments, but can be further modified. For instance, while a current source was constructed by a constant current source consisting of the transistors Q 8  -Q 10  and the resistor R 6 , it could be replaced by a resistor connected between the diode D 1  and the V CC  power supply. In this modified case, if the current flowing through the replaced resistor is excessively large, the output signal level decreased by the voltage drop across the resistor would influence the output signal level. On the contrary, if the current flowing through the replaced resistor is too small, the output transistor cannot be sufficiently driven, resulting in lowering also the output signal level. In this respect, if the constant current source as shown in FIG. 4 or 7 is employed, the above problem can be avoided. Thus, the use of the constant current source is more advantageous. The resistor R 9  is provided merely for the purpose of limiting current, and in principle, it is unnecessary. Furthermore, at least one of the output transistors and other transistors may be modified into a composite transistor which combines plural number of transistors so as to operate as a single transistor, such as a Darlington connection. Still further, so long as phase relation is not disturbed, additional transistors could be inserted into the illustrated circuit. In the FIGS. 4 and 7, by replacing the transistor Q 4  with the transistor of the PNP type, these modified circuits can be used as non-inverter amplifiers. 
     This invention has been described with respect to specific embodiments, but it will be recognized that there are modifications within the scope thereof that will be readily apparent to those of skill in the art.