Abstract:
A multi-layer circuit board having a connector portion of an inner layer substrate being exposed, the multi-layer circuit board comprising: an inner layer substrate in which an inner layer circuit is formed, the inner layer circuit including the connector portion; and an outer layer substrate having an outer layer circuit formed on an insulating layer and having a region corresponding to the connector portion peeled off, an inner layer circuit side of the inner layer substrate and an insulating layer side of the outer layer substrate being adhered to one another via an adhesive layer so as to face one another, and a conductor layer other than the connector portion of the inner layer circuit being adhered to the outer layer substrate directly by the adhesive layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-232220, filed on Oct. 21, 2011, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a method of manufacturing a multi-layer circuit board, and to the multi-layer circuit board. 
         [0004]    2. Description of the Related Art 
         [0005]    Regarding multi-layer circuit boards in which an inner layer substrate including an inner layer circuit and an outer layer substrate including an outer layer circuit are stacked, a method of manufacturing such a multi-layer circuit board that has a structure exposing a part of the inner layer circuit disclosed in Unexamined Japanese Patent Application Publication No. 2010-206124 A is known (refer to, Document 1). This multi-layer circuit board is manufactured as follows. That is, the outer layer substrate is stacked on a surface of a terminal exposure side of the inner layer circuit of the inner layer substrate, via an interlayer adhesive layer including an opening which is larger than an exposed portion of the terminal. 
         [0006]    Moreover, a pair of slits is formed in the outer layer substrate at positions outside the opening of the interlayer adhesive layer so as to sandwich a portion eventually to be removed, and the outer layer circuit of the outer layer substrate is formed. Finally, a punching processing is implemented straddling the slits to expose a terminal portion of the inner surface circuit. In this way for manufacturing the multi-layer circuit board, a structure that the interlayer adhesive layer is attached a terminal side end of the slits is formed after stacking, then the slits are closed by the inter-layer adhesive layer. Thus making it possible to prevent intrusion of chemicals into the terminal portion while forming the outer layer circuit by etching, and so on. 
       SUMMARY OF THE INVENTION 
       [0007]    However, in the conventional method of manufacturing disclosed in the above-mentioned Document 1, alignment of each of materials during actual manufacturing is difficult, hence whether intrusion of chemicals into the terminal portion can be reliably prevented or not is highly reliant on accuracy of alignment, resulting in a risk that costs rise and also yield falls. 
         [0008]    Moreover, there is a problem that because stacking is performed after forming the opening in the interlayer adhesive layer, an overall substrate thickness of the opening portion is small compared to that of other portions, hence pressure is insufficient during stacking thereby generating irregularity in the outer layer substrate and thus making it difficult to form a minute outer layer circuit. 
         [0009]    This invention has an object of solving the above-described problems arising from the conventional technology to thereby provide a method of manufacturing a multi-layer circuit board capable of improving yield while ensuring flatness of an outer layer substrate, easily and at low cost, and to provide the multi-layer circuit board. 
         [0010]    A first method of manufacturing a multi-layer circuit board according to one embodiment of the present invention, the multi-layer circuit board having a part of an inner layer circuit being exposed, comprises: forming one or more first slit portions in an outer layer substrate so as to conform with an outer periphery of a region corresponding to a circuit exposure portion of an inner layer substrate, the outer layer substrate having a conductor layer formed on one surface of the outer layer substrate and an adhesive layer covered by an exfoliating paper formed on the other surface of the outer layer substrate, the inner layer substrate having at least a part of the inner layer circuit being exposed, and the one or more first slit portions each penetrating the outer layer substrate while not attaining a closed circuit state; forming a half cut portion, linked to the one or more first slit portions, in the exfoliating paper of the outer layer substrate, and peeling off and thereby removing the exfoliating paper other than a residual exfoliating paper such that the exfoliating paper in the region corresponding to the circuit exposure portion remains; stacking and curing the inner layer substrate and the outer layer substrate such that an inner layer circuit side of the inner layer substrate and an adhesive layer side of the outer layer substrate face one another and the residual exfoliating paper is positioned on the circuit exposure portion; forming an outer layer circuit in the outer layer substrate; forming one or more second slit portions in the outer layer substrate, the one or more second slit portions being linked to the one or more first slit portions; and peeling off a region surrounded by the first and second slit portions of the outer layer substrate as a whole with the residual exfoliating paper to thereby expose the circuit exposure portion. 
         [0011]    Moreover, a second method of manufacturing a multi-layer circuit board according to another embodiment of the present invention, the multi-layer circuit board having a part of an inner layer circuit being exposed, comprises: applying a mask material to an adhesive layer of an outer layer substrate so as to correspond to a circuit exposure portion of an inner layer substrate, the outer layer substrate having a conductor layer formed on one surface of the outer layer substrate and the adhesive layer formed on the other surface of the outer layer substrate, the inner layer substrate having at least a part of the inner layer circuit being exposed, and the mask material having a size covering the circuit exposure portion; forming one or more first slit portions in the outer layer substrate so as to conform to a shape of the mask material, the one or more first slit portions each penetrating the outer layer substrate while not attaining a closed circuit state; stacking and curing the inner layer substrate and the outer layer substrate such that an inner layer circuit side of the inner layer substrate and an adhesive layer side of the outer layer substrate face one another and the mask material is positioned on the circuit exposure portion; forming an outer layer circuit in the outer layer substrate; forming one or more second slit portions in the outer layer substrate, the one or more second slit portions being linked to the one or more first slit portions; and peeling off a region surrounded by the first and second slit portions of the outer layer substrate as a whole with the mask material to thereby expose the circuit exposure portion. 
         [0012]    The first and second methods of manufacturing a multi-layer circuit board according to embodiments of the present invention result in each of substrates being stacked via an interlayer adhesive layer while causing an exfoliating paper or a mask material to remain on a circuit exposure portion of an inner layer circuit of an inner layer substrate, without processing the adhesive layer. As a result, flatness of an outer layer substrate during stacking can be ensured, first slit portions are filled by the adhesive layer, and chemicals for etching never intrude into the circuit exposure portion during formation of an outer layer circuit of an outer layer substrate. 
         [0013]    Moreover, the circuit exposure portion of the inner layer circuit is exposed by punching the outer layer substrate as a whole with the remaining exfoliating paper or mask material, hence the inner layer circuit can be exposed at low cost by an easy method. This allows yield of the multi-layer circuit board to be improved. 
         [0014]    Note that in one embodiment in the first method of manufacturing according to one embodiment of the present invention, a residual exfoliating paper has an area larger than that of the circuit exposure portion. 
         [0015]    Moreover, in another embodiment in the first method of manufacturing according to the present invention, one or more second slit portions are formed so as to encompass a half cut portion. 
         [0016]    A multi-layer circuit board according to one embodiment of the present invention, the multi-layer circuit board having a connector portion of an inner layer substrate being exposed, comprises: an inner layer substrate in which an inner layer circuit is formed, the inner layer circuit including the connector portion; and an outer layer substrate having an outer layer circuit formed on an insulating layer and having a region corresponding to the connector portion peeled off, an inner layer circuit side of the inner layer substrate and an insulating layer side of the outer layer substrate being adhered to one another via an adhesive layer so as to face one another, and a conductor layer other than the connector portion of the inner layer circuit being adhered to the outer layer substrate directly by the adhesive layer. 
       Effects of the Invention 
       [0017]    The present invention allows yield to be improved while ensuring flatness of an outer layer substrate, easily and at low cost. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a flowchart showing manufacturing processes of a multi-layer circuit board according to a first embodiment of the present invention. 
           [0019]      FIG. 2A  is a cross-sectional diagram showing same multi-layer circuit board in sequence of manufacturing processes according to the first embodiment of the present invention. 
           [0020]      FIG. 2B  is a cross-sectional diagram showing same multi-layer circuit board in sequence of manufacturing processes according to the first embodiment of the present invention. 
           [0021]      FIG. 2C  is a cross-sectional diagram showing same multi-layer circuit board in sequence of manufacturing processes according to the first embodiment of the present invention. 
           [0022]      FIG. 2D  is a cross-sectional diagram showing same multi-layer circuit board in sequence of manufacturing processes according to the first embodiment of the present invention. 
           [0023]      FIG. 2E  is a cross-sectional diagram showing same multi-layer circuit board in sequence of manufacturing processes according to the first embodiment of the present invention. 
           [0024]      FIG. 2F  is a cross-sectional diagram showing same multi-layer circuit board in sequence of manufacturing processes according to the first embodiment of the present invention. 
           [0025]      FIG. 3A  is a cross-sectional diagram showing in enlargement a concept of part of manufacturing processes of same multi-layer circuit board according to the first embodiment of the present invention. 
           [0026]      FIG. 3B  is a cross-sectional diagram showing in enlargement a concept of part of manufacturing processes of same multi-layer circuit board according to the first embodiment of the present invention. 
           [0027]      FIG. 3C  is a cross-sectional diagram showing in enlargement a concept of part of manufacturing processes of same multi-layer circuit board according to the first embodiment of the present invention. 
           [0028]      FIG. 4A  is a perspective diagram showing a part of manufacturing processes of same multi-layer circuit board according to the first embodiment of the present invention. 
           [0029]      FIG. 4B  is a perspective diagram showing a part of manufacturing processes of same multi-layer circuit board according to a first embodiment of the present invention. 
           [0030]      FIG. 4C  is a perspective diagram showing a part of manufacturing processes of same multi-layer circuit board according to a first embodiment of the present invention. 
           [0031]      FIG. 4D  is a perspective diagram showing a part of manufacturing processes of same multi-layer circuit board according to a first embodiment of the present invention. 
           [0032]      FIG. 5  is a cross-sectional diagram showing a completed article of same multi-layer circuit board according to the first embodiment of the present invention. 
           [0033]      FIG. 6  is a cross-sectional diagram showing a multi-layer circuit board according to a second embodiment of the present invention. 
           [0034]      FIG. 7  is a cross-sectional diagram of  FIG. 6  as seen from the direction of arrow A. 
           [0035]      FIG. 8A  is a cross-sectional diagram showing same multi-layer circuit board in sequence of manufacturing processes according to the second embodiment of the present invention. 
           [0036]      FIG. 8B  is a cross-sectional diagram showing same multi-layer circuit board in sequence of manufacturing processes according to the second embodiment of the present invention. 
           [0037]      FIG. 9  is a cross-sectional views showing an outer layer substrate of a multi-layer circuit board according to a third embodiment of the present invention. 
           [0038]      FIG. 10  is a flowchart showing manufacturing processes of the multi-layer circuit board according to the third embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0039]    A method of manufacturing a multi-layer circuit board, and the multi-layer circuit board, according to embodiments of this invention are described in detail below with reference to the accompanying drawings. 
       First Embodiment 
       [0040]      FIG. 1  is a flowchart showing manufacturing processes of a multi-layer circuit board according to a first embodiment of the present invention.  FIGS. 2A ,  2 B,  2 C,  2 D,  2 E and  2 F are cross-sectional diagrams showing this multi-layer circuit board in sequence of manufacturing processes.  FIGS. 3A ,  3 B and  3 C are cross-sectional diagrams showing in enlargement a concept of part of manufacturing processes of this multi-layer circuit board.  FIGS. 4A ,  4 B,  4 C and  4 D are perspective diagrams showing a part of manufacturing processes of this multi-layer circuit board.  FIG. 5  is a cross-sectional view showing a completed article of the multi-layer circuit board. First, as shown in  FIG. 2A , an outer layer substrate  10  comprising a single-sided copper-clad laminate (single-sided CCL) having a conductor layer  13  of copper foil or the like applied to a base substrate  11  via an adhesive agent  12 , is prepared. 
         [0041]    The base substrate  11  is configured by a resin film, for example. The following may be employed as the resin film, namely, for example, a resin film comprising a thermoplastic polyimide, polyolefin, liquid crystal polymer, or the like, or a resin film comprising a thermosetting epoxy resin, and so on. The adhesive agent  12  comprises an epoxy or acrylic adhesive agent, or the like, or an organic adhesive agent having a volatile component, or the like. The conductor layer  13  may be configured by a metal member of gold, silver, aluminum, or the like, as well as by copper foil. 
         [0042]    Next, as shown by the outline arrow in  FIG. 2A , an adhesive layer  9 , to which an exfoliating paper  8  is attached, is attached to a surface on a base substrate  11  side of the outer layer substrate  10 . This results in preparation of an outer layer substrate  10  having the exfoliating paper  8  formed via the adhesive layer  9  on a surface of the outer layer substrate  10  on an opposite side to the conductor layer  13  sandwiching the base substrate  11  (step S 100 ). 
         [0043]    The exfoliating paper  8  is configured by a resin film such as a PET film able to withstand a temperature of about 150° C. to 170° C., or by an exfoliating paper attached beforehand to a metal member, a paper material, or an adhesive agent configuring the adhesive layer  9 , and so on. Moreover, in order to regulate a thickness of the exfoliating paper  8 , a configuration may be adopted to form the exfoliating paper  8  by printing using ink and so on. 
         [0044]    Meanwhile, as shown in  FIG. 2B , an inner layer substrate  20  is prepared. The inner layer substrate  20  has inner layer circuits  23  each configured by pattern forming of a conductor layer of copper foil or the like formed on both surfaces of a base substrate  21  via an adhesive agent  22 . Moreover, a cover lay  6  is further attached via an adhesive agent  7  onto the inner layer circuit  23  on one surface side of the inner layer substrate  20 , for example. 
         [0045]    These cover lay  6  and adhesive agent  7  are removed at a certain place, hence, for example, a circuit exposure portion  23   a  of opening size a is formed in the inner layer substrate  20 . A terminal due to the inner layer circuit  23  that is to become a connector portion, for example, is formed in this circuit exposure portion  23   a.  Moreover, the inner layer substrate  20  configured in this way is prepared along with the above-described outer layer substrate  10  (step S 100 ). Note that the cover lay  6  comprises a resin film of the above-described kind, for example, and each other part configuring the inner layer substrate  20  is configured similarly to each part of the outer layer substrate  10 . 
         [0046]    Next, as shown by the straight line arrows in  FIG. 2C , a Victoria or Thomson die cutter is employed to form one or more first slit portions  17  so as to conform with an outer periphery of a region of the outer layer substrate  10  corresponding to the circuit exposure portion  23   a  of the inner layer substrate  20  when stacked, the one or more first slit portions  17  each penetrating the outer layer substrate  10  from the conductor layer  13  side while not attaining a closed circuit state, for example (step S 102 ). One example of this first slit portion  17  is shown in  FIG. 4A . In this example, the first slit portions  17  are formed in two facing sides of four sides. Each of the first slit portions  17  is formed such that, as far as possible in design terms, no gap with the outer periphery of the above-described region is provided. However, the first slit portion  17  may be formed so as to provide a gap of about 0 mm to 0.3 mm due to fluidity of the adhesive layer  9  during stacking 
         [0047]    Then, a half cut die cutter or laser is employed to form a half cut portion  18 , linked to (continuous with) the first slit portion  17 , in the exfoliating paper  8  of the outer layer substrate  10  such that the exfoliating paper  8  in the region corresponding to the circuit exposure portion  23   a  remains (step S 104 ). A size b of a region surrounded by these first slit portion  17  and half cut portion  18  is preferably larger than the opening size a. 
         [0048]    The first slit portion  17  and half cut portion  18  are formed as shown in greater detail in  FIG. 3A . That is, the first slit portion  17  is formed so as to penetrate, in a thickness direction, in order from the conductor layer  13  side as described above, the conductor layer  13 , the adhesive agent  12 , the base substrate  11 , the adhesive layer  9 , and the exfoliating paper  8 . Therefore, a cutting end surface of the adhesive layer  9  and the outer layer substrate  10  in the first slit portion  17  are identical in the thickness direction. 
         [0049]    On the other hand, the half cut portion  18  is formed so as to penetrate the exfoliating paper  8  in the thickness direction from an exfoliating paper  8  side of the outer layer substrate  10  and cut to around midway of the adhesive layer  9 . Note that the half cut portion  18  may be formed cutting as far as the base substrate  11 . If the first slit portion  17  and the half cut portion  18  are formed in this way, then, as shown in  FIG. 2D  and  FIG. 4B , the exfoliating paper  8  other than a residual exfoliating paper  8   a  of the outer layer substrate  10  is peeled off and removed from the adhesive layer  9  as shown by the arrows in  FIG. 2D . 
         [0050]    Next, as shown in  FIG. 2E , a circuit exposure portion  23   a  side of the inner layer substrate  20  and an adhesive layer  9  side of the outer layer substrate  10  are disposed facing one another and aligned such that the residual exfoliating paper  8   a  is positioned on the circuit exposure portion  23   a,  to stack and cure the outer layer substrate  10  and the inner layer substrate  20  (step S 106 ). 
         [0051]    At this time, because the adhesive layer  9  melts and then hardens, the first slit portion  17  and the half cut portion  18  achieve a filled state on an inside of the adhesive layer  9 , as shown in  FIG. 3B . That is, application of heat and pressure during stacking causes the adhesive layer  9  on the residual exfoliating paper  8   a  to flow into a periphery of the residual exfoliating paper  8   a,  hence the first slit portion  17  and the half cut portion  18  in the adhesive layer  9  are reliably blocked. 
         [0052]    Moreover, since the residual exfoliating paper  8   a  is disposed on the circuit exposure portion  23   a  in a hollow state, there is no warping and so on of the outer layer substrate  10  due to pressure variations during stacking/curing, hence flatness of the substrate overall can be ensured. This enables circuit formation, masking processing and so on in the outer layer substrate  10  to be easily performed. 
         [0053]    Note that alignment during stacking may be performed by a publicly known image analysis processing, or by, for example, during formation of the first slit portion  17 , forming a locating pin in a near vicinity of an edge (for example, four corners) of the outer layer substrate  10  and forming a locating hole, into which this locating pin is inserted, in a near vicinity of an edge of the inner layer substrate  20 , and then, during stacking, fitting together the locating pin and the locating hole. 
         [0054]    Then, etching, through-hole processing, and so on, are implemented on the conductor layer  13  of the outer layer substrate  10  to form an outer layer circuit  13   a  (refer to  FIG. 5 ) and so on (step S 108 ), and, as shown in  FIG. 2F , one or more second slit portions  19  linked to the one or more first slit portions  17  are formed in the outer layer substrate  10  (step S 110 ). 
         [0055]    As shown in greater detail in  FIG. 3C  and  FIG. 4C , these second slit portions  19  are formed in the thickness direction so as to encompass a portion where the half cut portion  18  was. Hence, it can be configured that no trace remains of the half cut portion  18  at time of completion of the multi-layer circuit board without the need for strict positioning accuracy in the thickness direction. 
         [0056]    Finally, as shown by the outline arrow in  FIG. 2F  and by  FIG. 4D , a region surrounded by the first and second slit portions  17  and  19  of the outer layer substrate  10 , that is, a region corresponding to the circuit exposure portion  23   a  of the inner layer substrate  20 , is peeled off as a whole with the residual exfoliating paper  8   a,  whereby the multi-layer circuit board as shown in  FIG. 5  is manufactured. The residual exfoliating paper  8   a  functions as a kind of reinforcing material of the portion peeled off, hence can be easily peeled off. 
       Second Embodiment 
       [0057]      FIG. 6  is a cross-sectional diagram showing a multi-layer circuit board according to a second embodiment of the present invention.  FIG. 7  is a cross-sectional diagram of  FIG. 6  as seen from the direction of arrow A.  FIGS. 8A and 8B  are cross-sectional diagrams showing the multi-layer circuit board in sequence of manufacturing processes. As shown in  FIGS. 6 and 7 , the multi-layer circuit board according to the second embodiment differs from the multi-layer circuit board according to the first embodiment in not having an adhesive agent  7  and a cover lay  6  provided on the inner layer circuit  23  of the inner layer substrate  20 . 
         [0058]    That is, as shown in  FIGS. 6 and 7 , in the multi-layer circuit board, the outer layer substrate  10  and the inner layer substrate  20  are stacked upon direct adhesion of the inner layer circuit  23  of the inner layer substrate  20  and the adhesive layer  9 . The region where the residual exfoliating paper  8   a  (not illustrated) has been disposed beforehand on the adhesive layer  9  is peeled off finally as a whole with the outer layer substrate  10  to expose the inner layer circuit  23 , whereby the circuit exposure portion  23   a  is formed. 
         [0059]    The multi-layer circuit board according to the second embodiment configured in this way is manufactured basically by similar manufacturing processes to those of the multi-layer circuit board according to the first embodiment. First, an outer layer substrate  10  as described above provided with an exfoliating paper  8  is prepared, and an inner layer substrate  20  as described above in which an inner layer circuit  23  is formed is prepared. 
         [0060]    Next, a first slit portion  17  and a half cut portion  18  of the kind shown in  FIG. 2C  are formed in the outer layer substrate  10 , and, as shown in  FIG. 2D , the exfoliating paper  8  is peeled off leaving the residual exfoliating paper  8   a  of the region corresponding to the circuit exposure portion  23   a.  Then, as shown in  FIG. 8A , alignment is performed such that the residual exfoliating paper  8   a  is positioned on a portion that is to become the circuit exposure portion  23   a  of the inner layer circuit  23 , and the outer layer substrate  10  and the inner layer substrate  20  are stacked and cured. 
         [0061]    Then, the conductor layer  13  of the outer layer substrate  10  is processed to form the outer layer circuit  13   a,  and, as shown in  FIG. 8B , having formed the second slit portion  19 , a region of the outer layer substrate  10  corresponding to the circuit exposure portion  23   a  is peeled off as a whole with the residual exfoliating paper  8   a  as shown by the outline arrow in  FIG. 8B , to thereby manufacture the multi-layer circuit board according to the second embodiment of the kind shown in  FIG. 6  and  FIG. 7 . 
         [0062]    This multi-layer circuit board according to the second embodiment, due to the cover lay  6  and the adhesive agent  7  not being provided on the inner layer circuit  23 , is capable of suppressing thickness of the substrate overall, as well as displaying similar operational advantages to those of the multi-layer circuit board according to the first embodiment. Moreover, usually when a cover lay  6  is not provided, the adhesive layer  9  during stacking/curing becomes fluid, thus making it impossible to expose the inner layer circuit  23 , but in the present embodiment, due to the existence of the residual exfoliating paper  8   a,  the problem of fluidity of the adhesive layer  9  does not occur, thus making it possible to expose the inner layer circuit  23 . Therefore, exposure of the circuit exposure portion  23   a  can be performed while suppressing material costs. 
       Third Embodiment 
       [0063]    A method of manufacturing a multi-layer circuit board according to a third embodiment differs from the methods of manufacturing a multi-layer circuit board according to the first and second embodiments as follows. That is, in the method of manufacturing a multi-layer circuit board according to the third embodiment, as shown in  FIG. 9 , the exfoliating paper  8  provided in the outer layer substrate  10  is cut so as to cover the region corresponding to the circuit exposure portion  23   a  of the inner layer circuit  23  and attached to the adhesive layer  9 , in advance. This differs from the methods of manufacturing a multi-layer circuit board according to the first and second embodiments. Note that masking tape or the like may be employed in place of the exfoliating paper  8  as a mask material. According to the embodiment, as shown in  FIG. 10 , step for applying a mask material having a size covering the circuit exposure portion  23   a  to the adhesive layer  9  of the outer layer substrate  10  so as to correspond to the circuit exposure portion  23   a  of the inner layer substrate  20  may be added (step S 101 ). However, masking the circuit exposure portion  23   a  by the mask material removes the need for the process for forming the half cut portion  18  explained using the above-described step S 104 ,  FIG. 2C  and so on, and removes the need for peeling off the exfoliating paper  8  other than the residual exfoliating paper  8   a.  Therefore, the number of manufacturing processes of the substrate overall can be reduced, thus enabling a reduction in costs to be achieved. 
       Other Embodiments 
       [0064]    In addition, in the above-mentioned embodiments, the case was described where there are three circuit layers overall. However, multi-layer circuit boards having an even greater number of layers than three may also be manufactured using the method of manufacturing according to the present invention. For example, it is possible to manufacture a multi-layer circuit board where another outer layer substrate  10  is stacked similarly on an inner layer circuit  23  on another surface side of the inner layer substrate  20  and a circuit exposure portion  23   a  is formed on both outer layer substrate  10  sides, or to manufacture a multi-layer circuit board having an even greater number of inner layer substrates  20  and outer layer substrates  10  stacked exposing the circuit exposure portion  23   a.