Abstract:
This disclosure concerns a semiconductor memory comprising Fin-type semiconductor layers (Fins) provided on the insulation layer provided on a substrate; first gate insulation films provided on first side surfaces of the Fins; second gate insulation films provided on second side surfaces of the Fins, the second side surfaces being opposite sides of the first side surfaces of the Fins; front gate electrodes provided on the first side surfaces via the first gate insulation films; and back gate electrodes provided between a second side surface of one of the Fins and a second side surface of the other Fin which is adjacent to the one of the Fins, the second side surface of the one of the Fins is opposed to the second side surface of the other Fin, wherein widths of the front gate electrodes or the back gate electrodes are smaller than the feature size (F).

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2006-177009, filed on Jun. 27, 2006, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor memory device and a manufacturing method of a semiconductor memory device, e.g., a fin-type FBC (Floating Body Cell) memory.  
         [0004]     2. Related Art  
         [0005]     Development of technology for manufacturing full-depletion FBC (“FD-FBCs”) on an SOI substrate has been underway. Each of the FD-FBCs includes a back gate to increase the signal difference (potential difference) between data “0” and “1”. A thickness of a buried oxide film (BOX) layer is preferably smaller (for example, 25 nm or less) for the back gate to facilitate controlling body bias.  
         [0006]     Nevertheless, the thickness of the BOX film is generally about 150 nm and it is technically difficult to make the thickness of the BOX layer equal to or smaller than 50 nm. To tackle the problem, a technique using a FinFET as an FBC has been developed. If the FinFET is used as the FBC, a thin gate insulating film can be formed on each side surface of a Fin (i.e., the FinFET). Therefore, the signal difference (potential difference) between the data “0” and the data “1” can be increased. In this case, the thickness of the BOX layer has no effect on characteristics of the FBC.  
         [0007]     In a conventional FBC constituted by the FinFET, a silicon part provided between two front gates is present. Because this silicon part is not electrically activated, the silicon part does not contribute to FBC operations. An area of the silicon part occupies 30% or more of that of a memory region, so that the silicon part obstructs downsizing of a semiconductor memory device.  
       SUMMARY OF THE INVENTION  
       [0008]     A semiconductor memory device according to am embodiment of the present invention comprises a semiconductor substrate; an insulation layer provided on the semiconductor substrate; a plurality of Fin-type semiconductor layers provided on the insulation layer, the Fin-type semiconductor layers including source regions, drain regions, and floating body regions in an electrically floating state provided between the source regions and the drain regions; first gate insulation films provided on first side surfaces of the Fin-type semiconductor layers; second gate insulation films provided on second side surfaces of the Fin-type semiconductor layers, the second side surfaces being opposite sides of the first side surfaces of the Fin-type semiconductor layers; front gate electrodes provided on the first side surfaces via the first gate insulation films; and back gate electrodes provided between a second side surface of one of the Fin-type semiconductor layers and a second side surface of the other Fin-type semiconductor layer which is adjacent to the one of the Fin-type semiconductor layers, the second side surface of the one of the Fin-type semiconductor layers and the second side surface of the other Fin-type semiconductor layer are opposed to each other, wherein  
         [0009]     when a smallest line width which can be formed by lithography is F, widths of the front gate electrodes or widths of the back gate electrodes are smaller than the F in a cross section perpendicular to an extension direction of the Fin-type semiconductor layers.  
         [0010]     A method of manufacturing a semiconductor memory device according to am embodiment of the present invention comprises preparing a substrate including a semiconductor layer formed on a semiconductor substrate via an insulation film; forming a mask material covering an active area on the semiconductor layer; etching an element isolation area of the semiconductor layer using the mask material to form a first trench; filling the first trench with a dummy insulation film; removing the mask material; forming a first spacer on side surfaces of the dummy insulation film exposed by removing the mask material; forming a second trench in the active area using the first spacer as a mask; forming the first trench again by removing the dummy insulation film; forming a first gate insulation film and a second gate insulation film on side surfaces of a Fin-type semiconductor layer defined by the first trench and the second trench; and filling the first trench and the second trench with a polysilicon as a front gate electrode material and a back gate electrode material, respectively. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is a schematic plan view of a Fin FBC memory device according to a first embodiment of the present invention;  
         [0012]      FIG. 2  is a cross-sectional view taken along a line  2 - 2  of  FIG. 1 ;  
         [0013]      FIG. 3  is a cross-sectional view showing a method of manufacturing the Fin FBC memory device according to the first embodiment;  
         [0014]      FIG. 4  is a cross-sectional view showing a manufacturing method following  FIG. 3 ;  
         [0015]      FIG. 5  is a plane view showing a manufacturing method following  FIG. 4 ;  
         [0016]      FIG. 6  is a cross-sectional view showing a manufacturing method following  FIG. 5 ;  
         [0017]      FIG. 7  is a cross-sectional view showing a manufacturing method following  FIG. 6 ;  
         [0018]      FIG. 8  is a plane view showing a manufacturing method following  FIG. 7 ;  
         [0019]      FIG. 9  is a cross-sectional view showing a manufacturing method following  FIG. 8 ;  
         [0020]      FIG. 10  is a cross-sectional view showing a manufacturing method following  FIG. 9 ;  
         [0021]      FIG. 11  is a cross-sectional view showing a manufacturing method following  FIG. 10 ;  
         [0022]      FIG. 12  is a cross-sectional view showing a manufacturing method following  FIG. 11 ;  
         [0023]      FIG. 13  is a plane view showing a manufacturing method following  FIG. 12 ;  
         [0024]      FIG. 14  is a cross-sectional view showing a manufacturing method following  FIG. 13 ;  
         [0025]      FIG. 15  is a cross-sectional view showing a manufacturing method following  FIG. 14 ;  
         [0026]      FIG. 16  is a plane view showing a manufacturing method following  FIG. 15 ;  
         [0027]      FIG. 17  is a plane view showing a manufacturing method following  FIG. 16 ;  
         [0028]      FIG. 18  is a schematic plan view of a Fin FBC memory device according to a second embodiment of the present invention; and  
         [0029]      FIG. 19  is a cross-sectional view taken along a line  19 - 19  of  FIG. 18 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]     Embodiments of the present invention will be explained below with reference to the accompanying drawings. The present invention is not limited to the embodiments.  
       First Embodiment  
       [0031]      FIG. 1  is a schematic plan view of a Fin FBC memory device according to a first embodiment of the present invention. The Fin FBC memory device is formed on an SOI (silicon-on-insulator) substrate. Each FBC can store therein data “1” or “1” according to the number of majority carries accumulated in a floating body FB (hereinafter, “body FB”) provided between a source and a drain. The source, the drain, and the body FB are formed in an SOI layer.  
         [0032]     In the FBC memory device according to the first embodiment, one source line SL is shared between two bit lines BLs. The bit lines BLs are connected to drains (not shown) present under the bit lines BLs via bit line contacts BLCs. Source lines SLs are connected to sources (see  FIG. 2 ) present under the source lines SLs via source line contacts SLCs. An STI (Shallow Trench Isolation) that acts as an element isolation is formed between two adjacent bit lines BLs.  
         [0033]     Front gate electrodes FGs and back gate electrodes BGs extend to be orthogonal to the source lines SL and the bit lines BLs formed on the SOI layer, and buried between adjacent bodies FBs. The front gate electrodes FGs are connected to front gate contacts FGCs. The back gate electrodes GBs are connected to back gate contacts BGCs provided outside of a memory formation region via the silicon substrate.  
         [0034]     An inter-electrode insulating film IE is buried between two adjacent front gate electrodes FG.  
         [0035]      FIG. 2  is a cross-sectional view taken along a line  2 - 2  of  FIG. 1 . The FBC memory device according to the first embodiment includes a silicon substrate  10 , a BOX layer  20  provided on the silicon substrate  10 , and Fin-type semiconductor layers  30  (hereinafter, “semiconductor layers”)  30  provided on the BOX layer  20 . The semiconductor layers  30  are formed using the SOI layer of the SOI substrate. The body FB and source-drain regions provided between respective both sides of the body FB are provided in the semiconductor layer  30 . In  FIG. 2 , only the source region is shown. Because the cross section of the drain region is the same as that of the source region, the drain region is not shown in  FIG. 2 . Furthermore, the cross section of the body FB is the same as the cross section of  FIG. 2  except that the source line SL, the source line contacts SLCs, the back gate contact BGC, and a back gate line BGL are removed from the cross section of  FIG. 2 . Therefore, the cross section of the body FB can be easily estimated from  FIG. 2 , and it is not shown in  FIG. 2 .  
         [0036]     A first gate insulating film  41  is formed on one side surface (a first side surface) of each of the semiconductor layers  30 . A second gate insulating film  42  is formed on the other side surface (a second side surface) of each of the semiconductor layers  30 . The front gate electrodes FGs are provided on the first side surfaces of the semiconductor layers  30  via the first gate insulating films  41 , respectively. The inter-electrode insulating film IE is provided between the two adjacent front gate electrodes FG. Namely, the inter-electrode insulating film IE is provided between the two front gate electrodes FG opposed to each other between the first side surface of one semiconductor layer  30  and that of another semiconductor layer  30  adjacent to the former semiconductor layer  30 .  
         [0037]     The back gate electrodes BGs are provided on the second side surfaces of the semiconductor layers  30  via the second gate insulating films  42 , respectively. Each back gate electrode BG is provided between the second side surfaces of the two adjacent semiconductor layers  30 . The back gate electrodes BGs penetrate the BOX layer  20  and reach the silicon substrate  10 . An impurity diffusion layer  50  is provided on a surface of the silicon substrate  10 . The back gate electrodes BGs are connected to the back gate contacts BGCs via the impurity diffusion layer  50 . Accordingly, potentials of the back gate electrodes BGs can be controlled by controlling a potential of the back gate line BGL.  
         [0038]      FIGS. 3 and 4  are cross-sectional views showing a method of manufacturing the Fin FBC memory device according to the first embodiment. The cross-sectional views of  FIGS. 3 and 4  are along one source line SL. As shown in  FIG. 3 , an SOI substrate is prepared. The SOI substrate includes the semiconductor layer  30  provided on the silicon substrate  10  via the BOX layer  20 . A thickness of the semiconductor layer  30  is, for example, about 100 nm. The semiconductor layer  30  is made of P-type silicon having a concentration of, for example, about 1×10 17  cm −3 . The semiconductor layer  30  can be used as an N-type MIS channel region as it is. A thickness of the BOX layer  20  is, for example, about 200 nm. The silicon substrate  10  may have a desired thickness and a desired impurity concentration.  
         [0039]     Boron ions are implanted into a memory region in the SOI substrate, thereby forming a P-type impurity layer  50  in a surface region of the silicon substrate  10 . At the time of implantation, implantation energy is about 130 keV and an impurity concentration is about 8×10 13  cm −2 . Next, a silicon nitride film  60  serving as a mask material is deposited on the semiconductor layer  30 . The silicon nitride film  60  on element isolation areas IAs is removed by photolithography and RIE (Reactive Ion Etching). A hard mask covering each active area AA is thereby formed.  
         [0040]     Using the silicon nitride film  60  as a mask, the semiconductor layer  30  in the element isolation areas IAs is anisotropically etched by photolithography and RIE. First trenches TR 1  are thereby formed in the respective element isolation areas IAs. The semiconductor layer  30  between the two adjacent element isolation areas IA acts as the active area AA. At this time, a width of each element isolation area IA is F (Feature Size) and a width of the active area AA is 2.25F. The F (Feature Size) means a minimum line width that can be formed by photolithography and etching. Accordingly, line widths that can be formed by the photolithography and the etching are all equal to or larger than F. However, if a spacer is used as a mask, line widths smaller than the F can be realized. Next, a silicon oxide film  70  serving as a dummy insulating film is filled up into each of the first trenches TR 1  formed in the element isolation areas IA, thereby obtaining a structure shown in  FIG. 4 . The silicon oxide film  70  is not left as the STI because it is removed at a later step.  
         [0041]     The silicon nitride film  60  is then removed using a hot phosphoric acid solution. Upper side surfaces of the silicon oxide film  70  are thereby exposed. Further, as shown in  FIG. 5 , a photoresist  80  covers body regions FBR by using photolithography. N-type impurity ions are then implanted into source regions SR and drain regions DR. At the time of implantation, a concentration of N-type impurities is about 1×10 21  cm −3 .  FIG. 5  is a plan view at a source-drain forming step.  
         [0042]     After removing the photoresist  80  as shown in  FIG. 6 , a silicon nitride film  90  having a thickness of F is deposited and then the silicon nitride film  90  is anisotropically etched by the RIE. As a result, as shown in  FIG. 7 , first spacers  91  are formed on side surfaces of the silicon oxide film  70  exposed by removing the silicon nitride film  60 , respectively. A width of each of the first spacers  91  is about F. Accordingly, an upper surface of the semiconductor layer  30  is exposed by as much width as 0.25F. Moreover, using the first spacers  91  as a mask, the semiconductor layer  30  and the BOX layer  20  are etched in a self-aligned fashion by the RIE. As a result, the semiconductor layer  30  is isolated into a plurality of semiconductor layers  30  and a second trench TR 2  is formed in an intermediate portions between two adjacent semiconductor layers  30 . The second trenches TR 2  reach the impurity diffusion layer  50  formed on the surface of the semiconductor substrate  10 . At this time, each of the isolated semiconductor layers  30  is formed into a fine Fin.  FIG. 8  is a plan view showing a structure after forming the second trenches R 2 . As shown in  FIG. 8 , the second trenches TR 2  extend along the first spacers  91  and the silicon oxide film (dummy insulating film)  70 . Accordingly, the second trenches TR 2  isolate the semiconductor layer  30  into a plurality of Fins.  
         [0043]     As shown in  FIG. 8 , the silicon oxide film  70  filled up into the element isolation areas IA is removed by photolithography and etching. As a result, first trenches TR 1  are formed in the respective element isolation areas IA again. The semiconductor layer  30  is exposed on inner side surfaces of the first and second trenches TR 1  and TR 2 . A sidewall of the exposed semiconductor layer  30  is thermally oxidized. The first insulating film  41  and the second insulating film  42  are thereby formed on the respective side surfaces of the semiconductor layer  30 . Thicknesses of the first and second gate insulating films  41  and  42  are about 6 nm, respectively.  
         [0044]     Next, a silicon oxide film on the silicon substrate  10  and on bottoms of the second trenches TR 2  formed at the time of forming the gate insulating films  41  and  42  is removed. As shown in  FIG. 10 , an N-type polysilicon  120  is filled up into the first and second trenches TR 1  and TR 2 . The polysilicon  120  is planarized by CDE (Chemical Dry Etching). The polysilicon  120  serves as materials of the front gate electrodes FG and the back gate electrodes BG in the first and second trenches TR 1  and TR 2 , respectively.  
         [0045]     Next, a silicon nitride film having a thickness of 0.25F is deposited and anisotropically etched by the RIE. As a result, second spacers  92  are formed on side surfaces of the first spacers  91  as shown in  FIG. 11 . The second spacers  92  are formed on the polysilicon  120  in the second trenches TR 2 . Furthermore, the deposited silicon nitride film also covers the polysilicon  120  in the first trenches TR 1 . A width of each of the second spacers  92  is about 0.25F. Accordingly, a surface of the polysilicon  120  is exposed by a width of 0.5F.  
         [0046]     Next, as shown in  FIG. 12 , using the first spacers  91  and the second spacers  92  as a mask, the polysilicon  120  in the first trenches TR 1  is etched by the RIE to reach an upper surface of the BOX layer  20 . As a result, third trenches TR 3  are formed in the polysilicon  120  in a self-aligned fashion. At this time, the front gate electrodes FGs each having a width of 0.25F and the back gate electrodes BGs each having a width of 0.25F are formed.  
         [0047]     As shown in  FIG. 13 , the polysilicon  120  outside of the memory cell region is processed into wirings by the photolithography and the RIE. The front gate electrodes FGs are extended in its extension direction by the polysilicon  120 , and connected to the front gate contacts FGCs.  FIG. 13  is a plan view after working the polysilicon  120  to form the wirings. Thereafter, the impurities in the sources, the drains, and the impurity diffusion layer  50  are activated by annealing at high temperature equal to or higher than 1000° C.  
         [0048]     After depositing a titanium film by about 20 nm, the titanium film is reacted with side surfaces of the front gate electrodes FGs by thermal treatment. As a result, titanium polycide  140  is formed on the respective side surfaces of the front gate electrodes FG. At the same time, the titanium polycide  140  is formed on side surfaces of the back gate electrodes GB. The titanium polycide  140  functions to reduce resistances of the front gate electrodes FG and the back gate electrode BG.  
         [0049]     The first and second spacers (SiN)  91  and  92  are removed using a hot phosphoric acid solution. A silicon oxide film is deposited by a depth equal to or larger than 300 nm and etched back by the CMP or the like so as to expose upper surfaces of the front gate electrodes FGs. As shown in  FIG. 15 , the inter-electrode insulating films IE are formed in the third trenches TR 3 , respectively.  
         [0050]     As shown in  FIG. 16 , openings  160  are formed in the respective element isolation areas IA in the semiconductor layers  30  by the photolithography and the RIE. The openings  160  are formed to be narrower than the semiconductor layers  30 . The openings  160  are etched to reach the front gate electrodes FG and the back gate electrodes BG by the CDE. As a result, as shown in  FIG. 17 , the semiconductor layers  30  in the element isolation areas IAs can be etched without chipping the front gate electrodes FG and the back gate electrodes BG. Next, a silicon oxide film is deposited by about 300 nm. This silicon oxide film is etched back by the CMP or the like, thereby forming the STIs between the adjacent bit line contact BLC, respectively.  
         [0051]     Referring back to  FIGS. 1 and 2 , after depositing an interlayer insulating film IL, the source line contacts SLCs, the bit line contacts BLCs (not shown in  FIG. 2 ), and the back gate contacts BGC are formed. Furthermore, as shown in  FIG. 1 , the front gate contacts FGCs are formed on the wirings made of the polysilicon  120 . Moreover, the source lines SLs, the bit lines BLs, the back gate lines BGLs, front gate lines FGL (not shown) are formed. In this manner, the Fin FBC memory device according to the first embodiment is completed.  
         [0052]     According to the first embodiment, the back gate electrodes BGs, the front gate electrodes FGs, and the inter-electrode insulating films IEs can be all formed in self-aligned fashions. Due to this, widths of the back gate electrodes BGs, the front gate electrodes FGs, and the inter-electrode insulating films IEs in the extension direction of the bit lines BL are all smaller than F. In the first embodiment, the widths of each of the back gate electrodes BGs, each of the front gate electrodes FGs, and each of the inter-electrode insulating films IEs are 0.25F, 0.25F, and 0.5F, respectively. A width of each semiconductor layer  30  is F. One back gate electrode BG and one inter-electrode insulating film IE are shared between two adjacent memory cells (FBCs). Accordingly, a width of one memory cell is 0.25F/2+0.25F+0.5F/2+F=1.625F.  
         [0053]     A length of each drain in an extension direction of the front and back gate electrodes FGs and BGs is F, that of each floating body FB is F, that of each source is F, and that of each STI is F. One source and one STI are shared between adjacent memory cells (FBCs). Accordingly, a length of one FBC is F+F+F/2+F/2=3F. Therefore, a size (an area) of one FBC is 1.65F×3F=4.875F 2  as shown in  FIG. 1 .  
         [0054]     Conventionally, widths of each back gate electrode BG and each front gate electrode FG are equal to or larger than F, respectively. Accordingly, a size (an area) of one FBC is equal to or larger than 3F×3F=9F 2 . Moreover, the presence of the silicon part that is not electrically activated between the two adjacent front gate electrodes FG obstructs downsizing of the semiconductor memory device.  
         [0055]     According to the first embodiment, the inter-electrode insulating film IE in place of the silicon part is provided between the two adjacent front gate electrodes FGs. It is thereby possible to narrow the width between the two adjacent front gate electrodes FGs. In addition, the widths of each back gate electrode BG and each inter-electrode insulating film IE are smaller than F (0.25F and 0.5F), respectively. Accordingly, in the first embodiment, the size of one FBC can be downsized to 4.875F 2  as stated. An area of the Fin FBC memory device according to the first embodiment is about 54% of that of the conventional Fin FBC memory device. In this manner, the first embodiment can realize downsizing of the memory region by making the width of each of the back gate electrodes BGs, the front gate electrodes FGs, and the inter-electrode insulating films IEs equal to or smaller than F.  
         [0056]     In the first embodiment, the widths of each back gate electrode BG, each front gate electrodes FG, and each inter-electrode insulating film IE are equal to or smaller than F, respectively. Alternatively, any one of the back gate electrode BG, the front gate electrode FG, or the inter-electrode insulating film IE may be formed to have a width smaller than F. In this case, the degree of downsizing the memory region is reduced, however, the advantage that the area of each FBC can be made smaller than 9F 2  can be maintained.  
       Second Embodiment  
       [0057]      FIG. 18  is a schematic plan view of a Fin FBC memory device according to a second embodiment of the present invention. In the second embodiment, back gate electrodes BGs are not connected to the silicon substrate  10  but provided on the BOX layer  20 . Accordingly, the back gate electrodes BGs are extended in the extension direction of the back gate electrodes BGs by the polysilicon  120 , and connected to the back gate contacts BGCs formed on the same layer as that on which the front gate contacts FGCs are formed.  
         [0058]      FIG. 19  is a cross-sectional view taken along a line  19 - 19  of  FIG. 18 . The back gate electrodes BGs do not penetrate the BOX layer  20  but are provided on the BOX layer  20 . The remaining configuration of the Fin FBC memory device according to the second embodiment may be identical to that of the Fin FBC memory device according to the first embodiment.  
         [0059]     Differences of a method of manufacturing the Fin FBC memory device according to the second embodiment from that according to the first embodiment will be described. In the method of manufacturing the Fin FBC memory device according to the second embodiment, etching of the semiconductor layer  30  is stopped on the upper surface of the BOX layer  20  at the step of forming the second trenches TR 2  shown in  FIG. 7 .  
         [0060]     At the step of working the polysilicon  120  shown in  FIG. 13 , the polysilicon  120  outside of the memory cell region is processed into wirings not only for the front gate electrodes FBs but also for the back gate electrodes BGs. By doing so, both the front gate electrodes FBs and the back gate electrodes BGs are extended in their respective extension directions by the polysilicon  120 . The other steps of manufacturing the Fin FBC memory device according to the second embodiment are identical to those of manufacturing the Fin FBC memory device according to the first embodiment.  
         [0061]     In the second embodiment, there is no need to form the second trenches TR 2  as deep as to reach the silicon substrate  10 . In the second embodiment, there is no need to form the back gate contacts BGC as deep as to reach the silicon substrate  10 . Furthermore, there is no need to form the impurity diffusion layer  50 . Therefore, it is relatively easy to manufacture the Fin FBC memory device according to the second embodiment. Further, the second embodiment can achieve the same effects as those of the first embodiment.