Abstract:
A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority under 35 USC §119 to Korean Patent Applications No. 10-2012-0093415 filed on Aug. 27, 2012, and No. 10-2013-0004203, filed on Jan. 15, 2013, in the Korean Intellectual Property Office (KIPO), the entire disclosures of which are incorporated herein by reference. 
       FIELD 
       [0002]    The present invention relates to the field of electronics, and more particularly to vertical type semiconductor devices and methods of forming the same. 
       BACKGROUND 
       [0003]    Techniques of vertically stacking cells with respect to the surface of a substrate have been developed to provide high integration levels for semiconductor devices. The number of vertically stacked cells in semiconductor devices has been increased, and so, when the height of the thin films used in the cells increases, the process may be complicated leading to process defects. 
       SUMMARY 
       [0004]    Example embodiments can provide vertical type semiconductor devices including an increased number of stacked cells. 
         [0005]    Example embodiments can provide methods of manufacturing the vertical type semiconductor device. 
         [0006]    According to some example embodiments, there is provided a vertical type semiconductor device. The vertical type semiconductor device can include a pillar structure including a semiconductor pattern that protrudes in a first direction and a channel pattern. The first direction can be a vertical direction relative to an upper surface of a substrate. The device can also include first word line structures horizontally extending to surround the pillar structure at a facing portion relative to the channel pattern. The first word line structures can include a blocking dielectric layer pattern and a metal pattern, where a height of the first word line structures can be enlarged at a portion that makes contact with the pillar structure. A first insulating structure can surround the pillar structure between the first word line structures in the first direction also is included. The first insulating structure can include a first portion that is a relatively smaller in height and makes contact with the pillar structure, and a second portion horizontally that can extend to a side direction of the first portion. 
         [0007]    In some example embodiments, the first portion of the first insulating structure may include a polysilicon the surface of which is covered with an oxide, or silicon nitride the surface of which is covered with an oxide. 
         [0008]    In some example embodiments, the first portion of the first insulating structure may include a thermal oxidation layer pattern. 
         [0009]    In some example embodiments, the second portion of the first insulating layer structure may include silicon oxide formed using chemical vapor deposition. 
         [0010]    In example embodiments, the vertical type semiconductor device may further include a second word line structure surrounding the pillar structure at a portion facing the semiconductor pattern. 
         [0011]    In some example embodiments, the pillar structure may include a first blocking dielectric layer including a tunnel insulating layer, a charge storing layer and silicon oxide stacked one by one to surround an outer wall of the channel pattern. 
         [0012]    In some example embodiments, the pillar structure may include a tunnel insulating layer and a charge storing layer stacked one by one to surround an outer wall of the channel pattern. 
         [0013]    In some example embodiments, the semiconductor pattern may have a groove shaped side wall portion that makes contact with the second word line structure, and the second word line structure may have a protruding shape at the groove shaped side wall portion and makes contact with the semiconductor pattern. 
         [0014]    In some example embodiments, a blocking dielectric layer included in the first word line structure may include a metal oxide. 
         [0015]    According to some example embodiments, there is provided a method of manufacturing a vertical type semiconductor device. In the method, a mold layer can be formed by repeatedly stacking sacrificial layers and insulating layers on a substrate. A pillar structure can be formed to penetrate the mold layer and to protrude in a first direction which can be a vertical direction relative to an upper surface of the substrate. The pillar structure includes a semiconductor pattern and a channel pattern. An oxidation target layer can be included at an exterior surface of the pillar structure. Then, the sacrificial layers can be selectively removed to expose the oxidation target layer. A portion of the oxidation target layer can be removed to form oxidation target layer patterns that make contact with the insulating interlayers and having a relatively smaller height than the insulating interlayers in the first direction. The surface of the oxidation target layer patterns can be oxidized to form an oxide to form first insulating layer structures including a first portion having a relatively smaller height and making contact with the pillar structure and the insulating interlayer horizontally extended in the side direction of the first portion. First word line structures can be formed at a gap portion between the first insulating layer structures. The first word line structures can horizontally extended to surround the pillar structure at a portion facing the channel pattern and including a blocking dielectric layer pattern and a metal pattern. A height of the first word line structure at a portion that makes contact with the pillar structure can be enlarged. 
         [0016]    In some example embodiments, the oxidation target layer may include polysilicon or silicon nitride. 
         [0017]    In some example embodiments, the polysilicon may be at least one selected from the group consisting of undoped polysilicon, p-type polysilicon, n-type polysilicon and carbon doped polysilicon. 
         [0018]    In some example embodiments, the oxidation process may include a radical oxidation process or a plasma oxidation process. 
         [0019]    In some example embodiments, a portion of the oxidation target layer or a whole of the oxidation target layer may be oxidized while conducting the oxidation process. 
         [0020]    In some example embodiments, a portion of an exposed side wall of the semiconductor pattern may be removed to form a groove when removing a portion of the oxidation target layer. 
         [0021]    In some example embodiments, the pillar structure may be formed by following method. First, channel holes penetrating the mold layer and exposing a surface of the substrate may be formed. Then, a semiconductor pattern partially filling up a lower portion of the channel holes may be formed. A silicon oxide layer, a first polysilicon layer, a first blocking dielectric layer, a charge storing layer and a tunnel insulating layer may be formed one by one on a side wall of the channel hole. A channel pattern may be formed on the tunnel insulating layer and the semiconductor pattern. Then, an insulating pattern may be formed on the channel pattern for filling up the channel hole. 
         [0022]    In some example embodiments, the first blocking dielectric layer may include silicon oxide. 
         [0023]    In some example embodiments, the pillar structure may be formed by following method. First, channel holes penetrating the mold layer and exposing a surface of the substrate may be formed. Then, a semiconductor pattern partially filling up a lower portion of the channel holes may be formed. A silicon oxide layer, a first polysilicon layer, a charge storing layer and a tunnel insulating layer may be formed one by one on a side wall of the channel hole. A channel pattern may be formed on the tunnel insulating layer and the semiconductor pattern. Then, an insulating pattern may be formed on the channel pattern for filling up the channel hole. 
         [0024]    In some example embodiments, a vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps. 
         [0025]    As described above, a vertical type semiconductor device manufactured in exemplary embodiments may have decreased vertical height of cells formed in each layer. Thus, the number of stacking of the vertical type semiconductor device may be increased. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]      FIG. 1  is a cross-sectional view illustrating a vertical type semiconductor device in accordance with some embodiments of the present inventive concept; 
           [0027]      FIG. 2  is an enlarged view of section A in  FIG. 1 ; 
           [0028]      FIG. 3  is a plan view of the vertical type semiconductor device in  FIG. 1 ; 
           [0029]      FIGS. 4A to 4J  are cross-sectional views illustrating methods of forming the vertical type semiconductor device illustrated in  FIGS. 1 to 3 ; 
           [0030]      FIGS. 5A to 5F  are enlarged views of a portion of each cross-sectional view among  FIGS. 4A to 4J ; 
           [0031]      FIGS. 6A to 6F  are cross-sectional views illustrating methods of manufacturing the vertical type semiconductor device in accordance with  FIG. 1 ; 
           [0032]      FIG. 7A  is a cross-sectional view illustrating a vertical type semiconductor device in accordance with some embodiments of the present inventive concept; 
           [0033]      FIG. 7B  is an enlarged cross-sectional view of section A in  FIG. 7A ; 
           [0034]      FIGS. 8A and 8B  are cross-sectional views illustrating methods of forming the vertical type semiconductor device illustrated in  FIG. 7A ; 
           [0035]      FIGS. 9A and 9B  are cross-sectional views illustrating methods of forming the vertical type semiconductor device illustrated in  FIG. 7A ; 
           [0036]      FIG. 10A  is a cross-sectional view of a vertical type semiconductor device in accordance with some embodiments of the present inventive concept; 
           [0037]      FIG. 10B  is an enlarged cross-sectional view on section A in  FIG. 10A ; 
           [0038]      FIGS. 11A to 11D  are cross-sectional views illustrating methods of forming the vertical type semiconductor device in  FIGS. 10A and 10B ; and 
           [0039]      FIG. 12  is a block diagram illustrating an information processing system in accordance with some embodiments of the present inventive concept. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0040]    Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The present inventive concept may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this description will be thorough and complete, and will fully convey the scope of the present inventive concept to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. 
         [0041]    It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0042]    It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept. 
         [0043]    Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
         [0044]    The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0045]    Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concept. 
         [0046]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0047]      FIG. 1  is a cross-sectional view illustrating a vertical type semiconductor device in accordance with some embodiments of the present inventive concept.  FIG. 2  is an enlarged view of section A in  FIG. 1 .  FIG. 3  is a plan view of the vertical type semiconductor device in  FIG. 1 .  FIGS. 1 and 2  are cross-sectional views taken along a line I-I′ in  FIG. 3 . 
         [0048]    Hereinafter, the vertical direction with respect to the upper surface of a substrate may be defined as a first direction, the direction in parallel with the upper surface of the substrate and vertical with respect to the extended direction of a word line may be defined as a second direction, and an extended direction of the word line may be defined as a third direction. 
         [0049]    Referring to  FIGS. 1 to 3 , a vertical type memory device may include a semiconductor pattern  132  extended in the first direction on a substrate  100  and a pillar structure  158  including channel patterns  150  and  152  having a cylinder shape and extruded and extended in the first direction, a first buried insulating layer pattern  154  filling up the inner space of the channel patterns  150  and  152 , and a tunnel insulating layer  148 , a charge storing layer  146  and a first blocking dielectric layer  144  stacked to surround the outer wall of each of the channel patterns  150  and  152  on the semiconductor pattern  132 . The vertical type memory device may include first and second word line structures  169   a  and  169   b  surrounding the side wall of the pillar structure  158  and extended in the third direction. Some of the pillar structures  158  may be provided with the first and second word line structures  169   a  and  169   b  having a stacked structure while being spaced apart in the first direction. Between the first and second word line structures  169   a  and  169   b  vertically spaced apart, first insulating layer structures  110 ,  143   b  and  162  may be provided. In addition, the vertical type memory device may further include a common source line (CSL)  178  and a bit line. 
         [0050]    In  FIG. 1 , the channel patterns  150  and  152 , the tunnel insulating layer  148 , the charge storing layer  146  and the first blocking dielectric layer  144  are illustrated as one layer  149   a . However, the layers may have a stacked structure as illustrated in  FIG. 2 . 
         [0051]    The substrate  100  may include, for example, a semiconductor material such as silicon and germanium. 
         [0052]    The semiconductor pattern  132  may make contact with the surface of the substrate  100  and have a pillar shape extruded from the surface of the substrate  100 . The semiconductor pattern  132  may include single crystalline silicon doped or undoped with impurities. The portion of the semiconductor pattern  132  contacting the second word line structure  169   b  may include grooves in the side wall. That is, the side wall portion of the semiconductor pattern  132  making contact with the second word line structure  169   b  may have a narrower width in the second direction. 
         [0053]    The channel patterns  150  and  152  may have a cylinder shape and may make contact with the upper surface of the semiconductor pattern  132 . As described above, the first burying insulating layer pattern  154  may fill up the inner space of the cylinder shaped channel patterns  150  and  152 . Alternatively, the channel patterns  150  and  152  may have a cyclic pillar shape. The channel patterns  150  and  152  may include polysilicon or single crystalline silicon doped or undoped with impurities. 
         [0054]    The tunnel insulating layer  148  may have a shape surrounding the outer wall of the channel patterns  150  and  152 . The tunnel insulating layer  148  may include an oxide such as silicon oxide. 
         [0055]    The charge storing layer  146  may be provided on the tunnel insulating layer  148  and may include a nitride such as silicon nitride. 
         [0056]    On the pillar structure  158 , a pad  156  may be provided. The pad  156  may include polysilicon or single crystalline silicon doped or undoped with impurities. The pad  156  may be electrically connected with the channel patterns  150  and  152 . 
         [0057]    The pillar structures  158  may be formed in the second and third directions. In this case, a channel array may be defined. Particularly, the channel array may include a first channel row 1 including the pillar structures disposed in a first row in the third direction, and a second channel row 2 including the pillar structures disposed in a second row in the third direction (see  FIG. 3 ). In this case, the pillar structures  158  included in the first channel row 1 and the second channel row 2 may not be disposed in parallel to each other with respect to the second direction. Accordingly, the pillar structures  158  included in the first and second rows 1 and 2 may be disposed in a zigzag type pattern in the third direction as shown in  FIG. 3 . 
         [0058]    Adjacent to the first channel row 1 and the second channel row 2, third and fourth channel rows 3 and 4 may be provided. The third and fourth channel rows 3 and 4 may be provided symmetrically to the first and second channel rows 1 and 2, respectively, with an imaginary face adjacent to the second row and defined by the first and third directions as a reference face. That is, the pillar structures included in the third channel row 3 may be disposed in parallel to the pillar structures included in the second channel row 2 in the second direction. In addition, the pillar structures  158  included in the fourth channel row 4 may be disposed in parallel to the pillar structures  158  included in the first channel row 1 in the second direction. 
         [0059]    The first to fourth channel rows 1, 2, 3 and 4 may constitute one channel set. The channel set may be disposed repeatedly. Between the channel sets, an insulating material  176  may be provided. 
         [0060]    The first word line structures  169   a  may be disposed facing the channel patterns  150  and  152 . The first word line structures  169   a  may have a shape that fills up a gap portion between the first insulating layer structures  110 ,  143   b  and  162  in each layer in the first direction. The external shape of the first word line structures  169   a  may be an extended line shape while surrounding the channel sets. 
         [0061]    The first word line structure  169   a  may include a second blocking dielectric layer  164 , a barrier metal layer  166  and a metal layer  168 . These layers may have a stacked structure. The second blocking dielectric layer  164  and the barrier metal layer  166  may be formed along the surface of the first insulating layer structures  110 ,  143   b  and  162  in upper and lower layers and the side wall profile of the pillar structure  158 . Therefore, the second blocking dielectric layer  164  and the barrier metal layer  166  may have a cylinder shape having the side surface of the pillar structure as a bottom. The metal layer  168  may have a shape filling up a gap between the first insulating structures  110 ,  143   b  and  162  on the barrier metal layer  166 . 
         [0062]    The second blocking dielectric layer  164  may include a metal oxide having a higher electric constant than silicon nitride. Particularly, the second blocking dielectric layer  164  may include a metal oxide. Examples of the metal oxide used for the second blocking dielectric layer may include aluminum oxide, hafnium oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, etc. 
         [0063]    The barrier metal layer  166  and the metal layer  168  may provide a control gate of each cell transistor. The control gate may be extended in the third direction and may function as a word line. The barrier metal layer  166  may include a conductive metal nitride, for example, titanium nitride and tantalum nitride. The metal layer  168  may include a metal having a low electric resistance. Examples of the metal used for the metal layer may include tungsten, titanium, platinum, etc. In this example embodiment, the metal layer  168  may include tungsten. 
         [0064]    Referring to the cross-sectional view illustrated in  FIG. 2 , the first word line structure  169   a  in each layer may have an extruding (i.e., protruding) shape from the side wall surface of the pillar structure  158  in the side direction. 
         [0065]    The height in the first direction of the first word line structure  169   a  making contact with the side wall of the pillar structure  158  in each layer may be relatively greater than other portions of the first word line structure  169   a . When the contacting portion of the first word line structure  169   a  with the side wall of the pillar structure is defined as a lower portion, the lower portion of the first word line structure  169   a  may have an enlarged shape in the first direction compared to the upper portion thereof. Since the contacting portion of the first insulating layer structures  110 ,  143   b  and  162  with the side wall of the pillar structure  158  may have a relatively smaller height compared with other portions of the first insulating layer structures  110 ,  143   b  and  162 , the gap at the contacting portion with the side wall of the pillar structure  158  may be relatively increased. 
         [0066]    As illustrated in  FIG. 2 , the second blocking dielectric layer  164  included in the first word line structure  169   a  may extend upward and downward at the contacting portion with the side wall of the pillar structure  158 . Since the second blocking dielectric layer  164  may fill up most of the enlarged gap portion, the barrier metal layer  166  and the metal layer  168  may hardly have a portion that extends upward and downward (in the first direction). Accordingly, the property change of a cell transistor due to the extending portion may be reduced. 
         [0067]    The first insulating layer structures  110 ,  143   b  and  162  of each layer may include a first portion making contact with the side wall of the pillar structure and a second portion at the side portion of the first portion. As described above, the first directional height of the first portion may be smaller than the first directional height of the second portion. 
         [0068]    The first portion of the first insulating layer structure  110 ,  143   b  and  162  may have a structure including an oxidation target layer pattern and an oxide layer covering the surface of the oxidation target layer pattern. The oxidation target layer pattern may include a material for forming an oxide having an insulating property through an oxidation process. The oxide layer covering the oxidation target layer pattern may be an oxidized product obtained from the material forming the oxidation target layer. Particularly, the oxidation target layer pattern may include polysilicon or silicon nitride. In addition, the oxide may be silicon oxide. 
         [0069]    Hereinafter, exemplary embodiments will be explained when using a polysilicon pattern as the oxidation target layer pattern and when using a silicon oxide layer as the oxide layer. In another embodiment, silicon nitride may be used as the oxidation target layer instead of polysilicon. The same procedure will be conducted when the silicon nitride is used as the oxidation target layer. 
         [0070]    A structure including a polysilicon pattern  142   a  and silicon oxide layers  140  and  162  covering the surface of the polysilicon pattern  142   a  may be provided. The silicon oxide layer  162  making direct contact with the upper and lower surface of the polysilicon pattern  142   a  may be a thermal oxide layer formed through a thermal oxidation of the surface of the polysilicon pattern  142   a.    
         [0071]    The second portion may include first insulating interlayers  110  comprising silicon oxide. The first insulating interlayers  110  may be silicon oxide formed through a chemical vapor deposition process. 
         [0072]    In exemplary embodiments, at the contacting portion of the first insulating layer structures  110 ,  143   b  and  162  with the pillar structure, a polysilicon pattern  142   a  may be included. The surface of the polysilicon pattern  142   a  may be surrounded by the silicon oxide layer and may be insulated. Since the first portion of the first insulating layer structures  110 ,  143   b  and  162  is lower than the second portion, the gap portion between the first portions may be relatively large. Thus, the width of the lower portion of the first word line structure may be enlarged in the first direction. 
         [0073]    The gate electrode at the first floor or at the second floor formed on the pillar structure among the first word line structures  169   a  may be provided as a string selection line (SSL). 
         [0074]    The second word line structure  169   b  may be disposed so as to face the semiconductor pattern  132  portion. The second word line structure  169   b  may be provided as a ground selection line (GSL). 
         [0075]    The second word line structure  169   b  may be formed at the side wall portion of the semiconductor pattern  132  including a groove. The second word line structure  169   b  may include a silicon oxide layer  162   a , a second blocking dielectric layer  164 , a barrier metal layer  166  and a metal layer  168 , and these layers may have a stacked structure. The silicon oxide layer  162   a  may include a thermal oxide layer. The second blocking dielectric layer  164 , the barrier metal layer  166  and the metal layer  168  may be formed by using the same material as the first word line structure  169   a  and may have the same stacked structure. 
         [0076]    Different from the first word line structure  169   a , the height of the second word line structure  169   b  at the contacting portion with the semiconductor pattern  132  may not be enlarged. The side wall of the second word line structure  169   b  making contact with the semiconductor pattern  132  may not be vertical but may have a slope along upward and downward and steeply extruded laterally. 
         [0077]    Since the width of the semiconductor pattern  132  at the portion making contact with the second word line structure  169   b  decreases, distances between neighboring semiconductor patterns  132  may be increased even further. Thus, electrical interference between neighboring semiconductor devices formed on semiconductor patterns  132  may be decreased. 
         [0078]    Alternatively, when silicon nitride is used as the oxidation target layer pattern, the width of the semiconductor pattern may be constant. In this case, the semiconductor pattern portion may have the shape as illustrated in  FIG. 10A . 
         [0079]    The first and second word line structures  169   a  and  169   b  and the first insulating layer structures may be stacked in the first direction, and the stacked structures may be extended in the third direction. Therefore, between the stacked structures, an opening portion  160  having a trench shape for separating the stacked structures may be provided. The inner portion of the opening portion  160  may be filled up with a second burying insulating layer pattern  176 . 
         [0080]    On the substrate  100  under the second burying insulating layer pattern  176 , an impurity region  178  extended in the third direction and performing the function of a common source line (CSL) may be formed. In exemplary embodiments, the impurity region  105  may include n-type impurities such as phosphor, arsenic, etc. On the impurity region  178 , a metal silicide pattern, for example, a cobalt silicide pattern and a nickel silicide pattern may be further formed even though not illustrated. 
         [0081]    The bit line may make an electric connection with the pad  156  by a bit line contact. Thus, the bit line and the channel patterns  150  and  152  may make an electric connection. The bit line may include a metal, a metal nitride, a doped polysilicon, etc. 
         [0082]      FIGS. 4A to 4J  are cross-sectional views illustrating methods of forming the vertical type semiconductor device illustrated in  FIGS. 1 to 3 .  FIGS. 5A to 5F  are enlarged views of a portion of each cross-sectional view among  FIGS. 4A to 4J . 
         [0083]    Referring to  FIG. 4A , first insulating interlayers  110  and sacrificial layers  120  may be alternately and repeatedly stacked on a substrate  100 . Thus, a plurality of the first insulating interlayers  110  and a plurality of the sacrificial layers  120  may be alternately stacked in the first direction. The substrate  100  may include a semiconductor material such as silicon, germanium, etc. 
         [0084]    The first insulating interlayers  110  and the sacrificial layers  120  may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, etc. The first insulating interlayers  110  may comprise silicon oxide and the sacrificial layers  120  may comprise a material having an etching selectivity with respect to the first insulating interlayer  110  such as silicon nitride. 
         [0085]    Through the processes described herein, a gate of each transistor may be formed at portions of the sacrificial layers in each layer. Accordingly, the number of the stacking of the first insulating interlayer and the sacrificial layers may be increased or decreased according to the number of the transistors stacked in the first direction. 
         [0086]    A trench penetrating one or two upper layers of the first insulating interlayers and the sacrificial layers  120  among the first insulating interlayers  110  and the sacrificial layers  120  may be formed, and an isolation layer pattern  112  filling the trench may be formed. The isolation layer pattern  112  may be formed to separate subsequently formed SSLs. Thus, the isolation layer pattern  112  may penetrate the sacrificial layers, which provide a mold for forming the SSL. 
         [0087]    Referring to  FIG. 4B , a plurality of channel holes  130  are formed to expose the upper surface of the substrate  100  by penetrating the first insulating interlayers  110  and the sacrificial layers  120 . 
         [0088]    The channel holes  130  may be formed by forming a hard mask on the uppermost insulating interlayer  110  and conducting a dry etching process using the hard mask as an etching mask. Due to the characteristic of the dry etching process, the width of each of the channel holes  130  may gradually become narrower with the depth of the holes  130 . 
         [0089]    A plurality of the channel holes  130  may also be formed in the second and third directions. Thus, an array of channel holes may be defined. The hole array may be disposed in the same manner as the above-described channel arrays. 
         [0090]    Referring to the channel array in  FIG. 3  along with  FIG. 4B , first holes a formed along the third direction and disposed in the first row 1, and second holes b formed along the third direction and disposed in the second row 2 may be formed. The first holes a may be nonparallel to the second holes b in the second direction, but may be disposed in a zigzag type (or pattern as shown). In addition, third holes c disposed in the third row 3 separated from the first and second rows 1 and 2, and fourth holes d disposed in the fourth row 3 may be formed. The third holes c and the fourth holes d may be disposed symmetrically to the first and second holes a and b included in the first and second rows with reference to an imaginary face defined by the first and third directions as a reference face. 
         [0091]    In the cross-sectional view in  FIG. 4   b , only the holes a and d disposed in the first and fourth rows 1 and 4 may be illustrated. Thus, the second and third holes b and c disposed in the second and third rows 2 and 3 may be illustrated in dotted lines. 
         [0092]    Referring to  FIG. 4C , a semiconductor pattern  132  partially filling up the lower portion of each of the channel holes  130  may be formed. 
         [0093]    Particularly, the semiconductor pattern  132  partially filling up the lower portion of the channel holes  130  may be formed by conducting a selective epitaxial growth (SEG) process using the upper surface of the exposed substrate  100  by the channel holes  130  as a seed. The semiconductor pattern  132  may be formed to include single crystalline silicon or single crystalline germanium, and may be doped or undoped with impurities. The semiconductor pattern  132  may be provided as a channel layer of a ground select transistor. Thus, the semiconductor pattern  132  may be formed to have an upper surface higher than the upper surface of the sacrificial layer  120  in a layer for forming GSL. 
         [0094]    Hereinafter, exemplary embodiments will be described referring to the enlarged views in  FIGS. 5A to 5F  on section A in  FIG. 1  together. 
         [0095]    Referring to  FIGS. 4D and 5A , on the inner wall of the channel holes  130 , on the upper surface of the semiconductor pattern  132  and on the upper surface of the hard mask, a first silicon oxide layer  140 , an oxidation target layer  142 , a first blocking dielectric layer  144 , a charge storing layer  146 , a tunnel insulating layer  148  and a polysilicon layer  150  may be formed one by one. 
         [0096]    The oxidation target layer  142  may include a material for forming an oxide having an insulating property through an oxidation process. Particularly, the oxidation target layer  142  may include polysilicon or silicon nitride. In exemplary embodiments, the oxidation target layer  142  may comprise polysilicon. However, the oxidation target layer  142  may comprise silicon nitride. In this case, the subsequent processes may be conducted by the same manner. Hereinafter, the oxidation target layer  142  may be called as a first polysilicon layer and the polysilicon layer  150  may be called a second polysilicon layer. 
         [0097]    Silicon oxide and silicon nitride may be further formed on the second polysilicon layer  150 . The silicon oxide and the silicon nitride may be formed to passivate the second polysilicon layer  150 . The thin layers may be formed along the inner surface profile of the channel holes  130  and may not completely fill up the channel holes  130 . That is, an inner space may remain in the channel holes  130  after forming the thin layers. 
         [0098]    Referring to  FIG. 4D , the first silicon oxide layer  140  and the first polysilicon layer  142  may be collectively referred to as a first layer  143 , which may be one layer, and the first blocking dielectric layer  144 , the charge storing layer  146 , the tunnel insulating layer  148  and the second polysilicon layer  150  may be collectively referred to as a second layer  149 , which may be another one layer. 
         [0099]    The first silicon oxide layer  140  may be a buffer layer for improving the adhesion property of the first polysilicon layer. The first silicon oxide layer  140  may be formed to have a thin thickness of a few A so as to be easily removed while conducting a removing process of the sacrificial layer in a following process. 
         [0100]    The first polysilicon layer  142  may function as an etch stopping layer when removing the sacrificial layer  120 . The first polysilicon layer  142  may be etched more slowly than silicon oxide formed by a chemical vapor deposition process when removing the sacrificial layer  120 . Since the first polysilicon layer  142  may be etched less when removing the sacrificial layer  120 , the first polysilicon layer  142  may remain almost the same thickness as deposited. In addition, the first polysilicon layer  142  may be transformed into an insulating material through an oxidation process. Thus, the first polysilicon layer  142  may be appropriately used as the etch stopping layer while removing the sacrificial layer  120 . Examples of polysilicon used as the first polysilicon layer  142  may include undoped polysilicon, p-type polysilicon, n-type polysilicon, carbon doped polysilicon, etc. 
         [0101]    In an alternative embodiment, a silicon nitride layer may be formed as the oxidation target layer instead of the first polysilicon. In this case, the first silicon oxide layer  140  may function as the etch stopping layer for removing the sacrificial layer  120 . 
         [0102]    The first blocking dielectric layer  144  may be silicon oxide formed through a chemical vapor deposition process. The first blocking dielectric layer  144  may not function as a vertical blocking sacrificial layer for preventing damage of the pillar structure previously formed while conducting a subsequent process, but may be used as a dielectric layer. 
         [0103]    The charge storing layer  146  may comprise a nitride such as silicon nitride. The tunnel insulating layer  148  may comprise an oxide such as silicon oxide. 
         [0104]    The second polysilicon layer  150  may be provided as a portion of a channel pattern in a subsequent process. The second polysilicon layer  150  may be doped or undoped with impurities. 
         [0105]    Referring to  FIGS. 4E and 5B , the bottom portion of the second polysilicon layer  150 , the tunnel insulating layer  148 , the charge storing layer  146 , the first blocking dielectric layer  144 , the first polysilicon layer  142  and the first silicon oxide layer  140  may be etched to expose the upper portion of the semiconductor pattern  132 . 
         [0106]    A second polysilicon layer  150 , a tunnel insulating layer  148 , a charge storing layer  146 , a first blocking dielectric layer  144 , a first polysilicon layer  142  and a first silicon oxide layer  140  may remain on the side wall of the channel hole  130  as a spacer shape after etching. 
         [0107]    When the silicon oxide and the silicon nitride are formed on the second polysilicon layer  150  in a previous process, the silicon oxide and the silicon nitride may be removed together while conducting the etching process. 
         [0108]    On the surface of the second polysilicon layer  150  and the semiconductor pattern  132 , a third polysilicon layer  152  may be formed. The second and third polysilicon layers  150  and  152  may be provided as channel patterns. The channel patterns  150  and  152  may make contact with the semiconductor pattern and may have a cylinder shape. 
         [0109]    In  FIGS. 4E to 4I , the first silicon oxide layer  140  and the first polysilicon layer  142  having the spacer shape are illustrated as a first layer  143   a  of one layer, and the first blocking dielectric layer  144 , the charge storing layer  146 , the tunnel insulating layer  148 , and the second and third polysilicon layers  150  and  152  are illustrated as a second layer  149   a  of another one layer. 
         [0110]    An insulating layer is formed to completely fill up the inner portion of the channel holes  130 , and a first burying insulating layer pattern  154  may be formed by polishing the insulating layer. The first burying insulating layer pattern  154  may include silicon oxide. 
         [0111]    Subsequently, a portion of the upper portion of the first burying insulating layer pattern  154  may be removed to form openings. In the openings, a polysilicon layer may be formed and polished to form a pad  156 . 
         [0112]    Through conducting the processes, pillar structures  158  may be formed in the channel holes  130 . As described referring to  FIG. 3 , the pillar structures  158  may include each of the channel sets including the first to fourth channel rows. 
         [0113]    Referring to  FIG. 4F , openings  160  penetrating the first insulating interlayers  110  and the sacrificial layers  120  may be formed to expose the upper surface of the substrate  100 . 
         [0114]    The openings  160  may be formed to define the gap portion between the word line structures. The openings  160  may be formed so as to be extended in the third direction. In addition, a plurality of the openings may be formed in the second direction. Through forming the openings  160 , the insulating interlayers  110  and the sacrificial layers  120  may have a patterned shape. 
         [0115]    The openings  160  may be disposed between the channel sets. That is, the openings  160  may divide each of the channel sets. 
         [0116]    Referring to  FIGS. 4G and 5C , the sacrificial layers  120  exposed to the side wall of the openings  160  in each layer may be removed to form a gap  122  between the first insulating interlayers  110 . A portion of the side wall of the first polysilicon layer  142  and the semiconductor pattern  132  may be exposed by the gap. 
         [0117]    The sacrificial layers  120  may be removed using a wet etching process using an etching solution having a high etching selectivity with respect to the first insulating interlayer  110 . The etching solution may include phosphoric acid. 
         [0118]    While conducting the etching process, the etching solution may readily penetrate into the sacrificial layer  120  adjacent to the opening portion  160  and so, a contacting time period with the etching solution during etching may be very long. However, the penetration of the etching solution may be delayed to the sacrificial layer  120  far from the opening portion  160  and so, the penetration may be conducted after a constant time from an initial etching to relatively shorten the contacting time period with the etching solution. Particularly, the sacrificial layer  120  making contact with the first and fourth rows adjacent to the opening portion in the channel set may have a long contacting time with the etching solution. However, since the etching solution may not readily penetrate into the sacrificial layer  120  adjacent to the second and third rows in the channel set but may penetrate after conducting the etching process for a time being to remove the sacrificial layer  120  near the first and fourth rows, the contacting time of the sacrificial layer with the etching solution may be relatively short. 
         [0119]    Thus, when the etching process is not conducted for a sufficient time period, the sacrificial layer  120  adjacent to the second and third rows may not be removed but remain. Accordingly, an over etching process may be inevitable to completely remove the sacrificial layer  120 . 
         [0120]    While conducting the removing process of the sacrificial layer  120 , the first silicon oxide layer  140  having a thin thickness may be removed together to expose the first polysilicon layer  142 . Thus, the contacting time of the first polysilicon layer with the etching solution may be different according to the position. Particularly, the first polysilicon layer positioned at the first and fourth rows may contact the etching solution for a longer time than the polysilicon layer positioned at the second and third rows. However, since the first polysilicon layer  142  may be hardly etched by the etching solution, the thickness of the first polysilicon layer  142  included in the pillar structure of the first to fourth rows may be very uniform after conducting the removing process. In addition, the first blocking dielectric layer, the charge storing layer and the tunnel insulating layer covered by the first polysilicon layer  142  may be undamaged. 
         [0121]    Accordingly, in a conventional method, after removing the sacrificial layer, the first blocking dielectric layer may be completely removed and a new first blocking dielectric layer may need to be re-deposited. However, in exemplary embodiments according to the inventive concept, since the first blocking dielectric layer may not be removed during removal of the sacrificial layer, the removal and re-deposition of the first blocking dielectric layer after removing the sacrificial layer may be avoided. 
         [0122]    Alternatively, when the oxidation target layer  142  is not formed using polysilicon but using silicon nitride, the first silicon oxide layer  140  may be used as the etch stopping layer while removing the sacrificial layer  120 . Thus, when the sacrificial layer  120  is removed the whole first silicon oxide layer  140  should not be consumed. In addition, after removing the whole sacrificial layer  120 , an additional process for removing the first silicon oxide layer  140  may be used. 
         [0123]    Referring to  FIGS. 4H and 5D , the first polysilicon layer  142  exposed to the gap portion may be removed by conducting a wet etching process to selectively and slowly etch the first polysilicon layer  142 . In addition, a portion of the first polysilicon layer making contact with the first insulating interlayer  110  may be removed. A first polysilicon pattern  142   a  having a lower height than the first insulating interlayer in each layer may be formed. In other words, the first polysilicon pattern  142   a  that remains at the removal of the sacrificial layer  120  may be further recessed between the first insulating interlayer  110  and the first blocking dielectric layer. 
         [0124]    After conducting the wet etching process to remove a portion of the first polysilicon layer  142 , the surface of the semiconductor pattern  132  exposed to the gap portion may be etched together. Thus, on the surface of the semiconductor pattern  132 , a groove narrowed in the second direction may be formed. By forming the groove, the circumference of the semiconductor pattern  132  exposed by the gap  122   b  may be decreased. 
         [0125]    Alternatively, when the oxidation target layer  140  is silicon nitride instead of polysilicon, the surface of the semiconductor pattern may not be etched. In this case, the semiconductor pattern portion may have the same shape as illustrated in  FIG. 10A . 
         [0126]    Through the above-described process, a first polysilicon pattern  142   a  having a smaller height than the first insulating interlayer  110  may be formed. As illustrated in the drawings, the gap  122   a  may have a cylinder shape with the side wall portion of the channel pattern as a bottom surface. The width at the bottom portion of the cylinder may have an enlarged shape compared to the upper width of the cylinder (away from the sidewall and closer to the opening). 
         [0127]    As described above, in the etching process to form the gaps  122   a  and  122   b , an etching solution, for example, hydrogen fluoride (HF) may not be used for directly removing the silicon oxide or cleaning the silicon oxide residue. In addition, since the etching process may be conducted by a condition having a high etching selectivity with respect to the silicon oxide, the silicon oxide may be hardly removed. Thus, the first insulating interlayer  110  formed by using silicon oxide may be hardly removed during the etching process. 
         [0128]    Since the first insulating interlayer  110  may be hardly removed as described above, the first insulating interlayer  110  may not be necessary to be formed to have excess thickness to compensate for the consumption of a portion of the first insulating interlayer  110 . Thus, the total height of the mold structure including the stacked structure of the first insulating interlayer  110  and the sacrificial layer  120  may be decreased. In addition, the number of the floors of the sacrificial layers  120  formed in the mold structure having the same height may be increased, more word line structures may be stacked, and the integration degree of semiconductor devices may be increased. 
         [0129]    Referring to  FIGS. 4I and 5E , an oxidation process may be conducted to oxidize the surfaces of the first polysilicon pattern  142   a  and the semiconductor pattern exposed to the gaps  122   a  and  122   b . The oxidation process may include a radical oxidation process or a plasma oxidation process. 
         [0130]    Through conducting the oxidation process, a second silicon oxide layer pattern  162  may be formed on the exposed surface of the first polysilicon pattern  142   a . Thus, the first polysilicon pattern may have a shape being surrounded by silicon oxide. In addition, by forming the second silicon oxide layer pattern  162 , the first polysilicon pattern  142   a  may be electrically insulated from the word line structure to be formed in a following process. 
         [0131]    In addition, the exposed surface of the semiconductor pattern  132  by the gap  122   a  may also be oxidized to form a silicon oxide layer pattern  162   a.    
         [0132]    Referring to  FIGS. 4J and 5F , a second blocking dielectric layer  164  may be formed along the profile of the first insulating interlayer  110 , the first blocking dielectric layer  144 , the first silicon oxide layer  140  and the second silicon oxide layer pattern  162  in the gap. 
         [0133]    In this example embodiment, since the first blocking dielectric layer  144  may be formed at the pillar structure in advance, a silicon oxide layer as the first blocking dielectric layer may not be re-deposited. Thus, the second blocking dielectric layer  164  may be formed on the first blocking dielectric layer  144 . 
         [0134]    Then, a barrier metal layer  166  may be formed on the second blocking dielectric layer  164 , and a metal layer  168  completely filling up the gaps  122   a  and  122   b  portion may be formed. 
         [0135]    The second blocking dielectric layer  164  may be formed by using a material having a higher dielectricity than the first blocking dielectric layer  144 . The second blocking dielectric layer  164  may comprise a metal oxide. Examples of the metal oxide used for the second blocking dielectric layer may include aluminum oxide, hafnium oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, etc. 
         [0136]    The barrier metal layer  166  and the metal layer  168  may be provided as word lines in a following process. The barrier metal layer  166  may be formed by using a metal nitride such as titanium nitride and tantalum nitride. The metal layer  168  may comprise a metal having a low electric resistance. Examples of the metal used for metal layer include tungsten, titanium, tantalum, platinum, etc. 
         [0137]    Then, the metal layer  168  and the barrier metal layer  166  formed in the opening portion  160  may be removed to form first and second word line structures respectively in the gaps  122   a  and  122   b . The removing process may include a wet etching process. 
         [0138]    The first word line structure  169   a  may be formed at the side wall portion of the channel patterns  150  and  152 . The first word line structure  169   a  making contact with the side wall portion of the channel patterns  150  and  152  may be relatively high. The first word line structure may be provided as the gate of a cell transistor and the SSL of a selecting transistor. 
         [0139]    The second word line structure  169   b  may be formed at the side wall portion of the semiconductor pattern  132 . The second word line structure  169   b  may be provided as the GSL. The second word line structure  169   b  making contact with the side wall of the semiconductor pattern  132  may not have an enlarged height but may have a decreased height. In addition, the side wall of the second word line structure  169   b  making contact with the semiconductor pattern  132  may not be vertical but may have a slope to upward and downward to have a sharp and laterally extruding (or protruding) shape. 
         [0140]    Impurities may be doped into the upper portion of the exposed substrate  100  to form an impurity region  178  ( FIG. 1 ). The impurities may include n-type impurities such as phosphor and arsenic. The impurity region  178  may be extended in the third direction and function as a common source line (CSL). 
         [0141]    On the impurity region  178 , a metal silicide pattern such as a cobalt silicide pattern or a nickel silicide pattern may be further formed. 
         [0142]    Referring to  FIG. 1  again, a second burying insulating layer pattern  176  filling up the opening  160  may be formed. 
         [0143]    An upper insulating interlayer may be formed on the thus formed structures, and contact holes exposing the upper surface of the pad  156  may be formed. In the contact holes, a bit line contact may be formed, and a bit line making contact with the upper portion of the bit line contact may be formed. 
         [0144]    According to the above-described process, the surface of the oxidation target layer may be oxidized to form an oxide having an insulating property. Thus, the oxidation target layer and other conductive patterns may be insulated from each other. Particularly, when the oxidation target layer is polysilicon, since the polysilicon has a high etching selectivity with respect to an etching solution for removing the sacrificial layer, the consumption of the first insulating interlayers may be decreased. 
         [0145]      FIGS. 6A to 6F  are cross-sectional views illustrating other methods of manufacturing the vertical type semiconductor device in accordance with Example Embodiment 1. 
         [0146]      FIGS. 6A to 6F  are enlarged views on section A in  FIG. 1 . 
         [0147]    First, the structure illustrated in  FIG. 4C  may be formed by conducting the same procedure described referring to  FIGS. 4A to 4C . 
         [0148]    Referring to  FIG. 6A , on the inner side wall of the channel holes  130 , on the upper surface of the semiconductor pattern  132  and on the upper surface of the hard mask, a first silicon oxide layer  140 , an oxidation target layer  142 , a charge storing layer  146 , a tunnel insulating layer  148  and a polysilicon layer  150  may be formed one by one. 
         [0149]    The oxidation target layer  142  may include a material for forming an oxide having an insulating property through an oxidation process. Particularly, the oxidation target layer  142  may include polysilicon or silicon nitride. Hereinafter, the oxidation target layer  142  may be called as the first polysilicon layer, and the polysilicon layer  150  may be called as a second polysilicon layer. However, silicon nitride layer may be used as the oxidation target layer. 
         [0150]    On the second polysilicon layer  150 , silicon oxide and silicon nitride may be further formed. The silicon oxide and the silicon nitride may be layers for passivating the second polysilicon layer  150 . 
         [0151]    In this example embodiment, in contrast to  FIG. 5A , the first blocking dielectric layer may not be formed in the channel holes. Thus, the first polysilicon layer  142  may have a shape making direct contact with the charge storing layer. In exemplary embodiments, the oxidation target layer  142  may substantially function as a vertical blocking sacrificial layer to prevent the damage of the pillar structure. Thus, a layer functioning as the vertical blocking sacrificial layer may not be necessary to be formed while forming the pillar structure. Thus, the first blocking dielectric layer provided as a substantial dielectric layer may be formed in a following process. 
         [0152]    Referring to  FIG. 6B , the bottom surface of the second polysilicon layer  150 , the tunnel insulating layer  148 , the charge storing layer  146 , the first polysilicon layer  142  and the first silicon oxide layer  140  may be etched to expose the upper portion of the semiconductor pattern  132 . 
         [0153]    Through conducting the etching process, the second polysilicon layer  150 , the tunnel insulating layer  148 , the charge storing layer  146 , the first polysilicon layer  142  and the first silicon oxide layer  140  may remain as a spacer shape on the side wall of the channel hole  130 . 
         [0154]    Then, on the surface of the second polysilicon layer  150  and the semiconductor pattern  132 , a third polysilicon layer  152  may be formed. The second and third polysilicon layers  150  and  152  may be provided as channel patterns. The channel patterns  150  and  152  may make contact with the semiconductor pattern and may have a cylinder shape. 
         [0155]    An insulating layer may be formed to completely fill up the inner portion of the channel holes  130 . Then, the insulating layer may be polished to form a first burying insulating layer pattern  154 . The first burying insulating layer pattern  154  may include silicon oxide. 
         [0156]    In succession, a portion of the upper portion of the first burying insulating layer pattern  154  may be removed to form openings. A polysilicon layer may be formed in the openings and polished to form a pad  156  (see  FIG. 4E ). 
         [0157]    Referring to  FIG. 6C , openings  160  (see  FIG. 4F ) penetrating the first insulating interlayers  110  and the sacrificial layers  120  may be formed to expose the upper surface of the substrate  100 . The openings  160  may be extended in the third direction. In addition, a plurality of the openings  160  may be formed in the second direction. Through forming the openings  160 , the first insulating interlayers  110  and the sacrificial layers  120  may have a patterned shape. 
         [0158]    By removing the sacrificial layers  120  exposed to the side wall of the opening  160  in each layer, a gap  122  may be formed between the first insulating interlayers  110 . By forming the gap  122 , a portion of the side wall of the first polysilicon layer and the semiconductor pattern  132  may be exposed. The sacrificial layers  120  may be removed using a wet etching process with an etching solution having a high etching selectivity with respect to the first insulating interlayer  110 . The etching solution may include phosphoric acid. 
         [0159]    The first silicon oxide layer  140  formed to have a small thickness may be removed together while conducting the removing process of the sacrificial layer  120  to expose the first polysilicon layer  142 . However, since the first polysilicon layer  142  may be hardly etched, the thickness of the first polysilicon layer  142  included in the first to fourth pillar structures may be uniform. 
         [0160]    Referring to  FIG. 6D , a wet etching process for selectively and slowly etching the first polysilicon layer  142  may be conducted to remove the exposed first polysilicon layer  142  to the gap portion. In addition, a portion of the first polysilicon layer  142  making contact with the first insulating interlayer  110  may be removed. Thus, a first polysilicon pattern  142   a  having a smaller height than the first insulating interlayer in each layer may be formed. 
         [0161]    Through conducting a wet etching process for removing a portion of the first polysilicon layer  142 , the surface of the semiconductor pattern  132  exposed to the gap  122   b  portion may be etched together. Thus, a groove narrowed in the second direction may be formed on the surface of the exposed semiconductor pattern  132 . 
         [0162]    In another embodiment, the surface of the semiconductor pattern may be hardly etched when the oxidation target layer may comprise silicon nitride instead of polysilicon. 
         [0163]    Through conducting the above process, the first polysilicon pattern  142   a  having a smaller height than the first insulating interlayer  110  may be formed. As illustrated in  FIG. 6D , the gap  122   a  may have a cylinder shape having the side wall portion of the channel pattern as a bottom surface, and the width at the bottom surface portion of the cylinder may have an enlarged shape than the upper width of the cylinder. 
         [0164]    An oxidation process may be conducted to oxidize the surface of the first polysilicon pattern  142   a  and the semiconductor pattern  132  exposed to the gaps  122   a  and  122   b . The oxidation process may include a radical oxidation process or a plasma oxidation process. Through conducting the oxidation process, a second silicon oxide layer pattern  162  may be formed on the exposed surface of the first polysilicon pattern  142   a . The silicon oxide layer pattern  162   a  may be formed on the exposed surface of the semiconductor pattern  132 . 
         [0165]    Referring to  FIG. 6E , a first blocking dielectric layer  163  may be formed along the profile of the first insulating interlayer  110 , the first silicon oxide layer  140  and the second silicon oxide layer pattern  162  in the gap. The first blocking dielectric layer  163  may be formed by depositing silicon oxide by a chemical vapor deposition method. 
         [0166]    Referring to  FIG. 6F , a second blocking dielectric layer  164  may be formed on the first blocking dielectric layer  163 . Then, a barrier metal layer  166  may be formed on the second blocking dielectric layer  164 , and a metal layer  168  completely filling up the gap portion may be formed. 
         [0167]    Then, the metal layer  168  and the barrier metal layer  166  formed on the side wall of the opening portion  160  may be removed by a wet etching process to form an opening portion again. Through conducting the above-described process, first and second word line structures  169   a  and  169   b  may be formed in the gaps  122   a  and  122   b , respectively. 
         [0168]    Through conducting the above-described process, a vertical type semiconductor device as illustrated in  FIG. 1  may be manufactured. 
         [0169]    According to the above-described process, by forming an oxide having an insulating property by oxidizing the surface of the oxidation target layer, the oxidation target layer and other conductive patterns may be insulated from each other. In addition, the process of forming the first blocking dielectric layer between the oxidation target layer and the charge storing layer may be omitted. 
         [0170]      FIG. 7A  is a cross-sectional view illustrating a vertical type semiconductor device in some embodiments according to the inventive concept.  FIG. 7B  is an enlarged cross-sectional view of section A in  FIG. 7A . 
         [0171]    The vertical type semiconductor device in this example embodiment may have the same structure as the vertical type semiconductor device illustrated in  FIG. 1  except for the first insulating layer structure. 
         [0172]    In  FIG. 7A , channel patterns  150  and  152 , a tunnel insulating layer  148 , a charge storing layer  146  and a first blocking dielectric layer  144  may be illustrated as one layer  149   a . However, the thin layers may have the same stacked structure as illustrated in  FIG. 7B . 
         [0173]    Referring to  FIGS. 7A and 7B , in a vertical type memory device, first insulating layer structures  110  and  170  in each layer may include a first portion making contact with the side wall of the pillar structure and a second portion disposed laterally from the first portion. As described above, the first direction height of the first portion may be lower than the first direction height of the second portion. 
         [0174]    In this example embodiment, the first portion of first insulating layer structures  110 ,  140  and  170  may include a second silicon oxide layer pattern  170 . The second silicon oxide layer pattern  170  may be a thermal oxidation layer formed through a thermal oxidation of the whole material constituting the oxidation target layer. 
         [0175]    The second portion may include a first insulating interlayer  110  and a first silicon oxide layer  140  formed by using silicon oxide by means of a chemical vapor deposition method. The first insulating interlayer  110  may be silicon oxide formed through the chemical vapor deposition process. 
         [0176]    In this example embodiment, the oxidation target layer pattern may not be included in the first insulating layer structures  110 ,  140  and  170 . 
         [0177]    Since the first portion of the first insulating layer structures  110 ,  140  and  170  may be lower than the second portions  110  and  140 , the gap  122   a  portion between the first portions may be relatively wide. Thus, the width of the lower portion of the first word line structure  169   a  formed at the gap  122   a  portion may be enlarged in the first direction. That is, the second silicon oxide layer pattern  170  may have a smaller height than the first insulating interlayers  110 . 
         [0178]    The second word line structure  169   b  may have the same shape as explained referring to  FIG. 1 . 
         [0179]    The first and second word line structures  169   a  and  169   b  and the first insulating layer structures may be stacked in the first direction, and the stacked structures may be extended in the third direction. Thus, an opening  160  having a trench shape for separating the stacked structures may be provided between the stacked structures. The inner portion of the opening portion  160  may be filled up with a second burying insulating layer pattern  176 . 
         [0180]    On the substrate  100  under the second burying insulating layer pattern  176 , an impurity region  178  extended in the third direction and functioning as a common source line (CSL) may be formed. 
         [0181]    A bit line may be electrically connected to a pad  156  through a bit line contact and may be electrically connected to the channel patterns  150  and  152 . The bit line may include a metal, a metal nitride, doped polysilicon, etc. 
         [0182]      FIGS. 8A and 8B  are cross-sectional views illustrating methods of manufacturing the vertical type semiconductor device illustrated in  FIG. 7A . 
         [0183]      FIGS. 8A and 8B  are an enlarged views on section A in  FIG. 7A . 
         [0184]    The same procedure explained referring to  FIGS. 4A to 4H  may be utilized in conjunction with those illustrated in  FIGS. 8A and 8B . Through conducting the above-described processes, a structure illustrated in  FIG. 8A  may be formed. Hereinafter, the oxidation target layer pattern may be explained as a first polysilicon pattern. However, the oxidation target layer pattern may be also formed by silicon nitride. 
         [0185]    Referring to  FIG. 8B , the whole first polysilicon pattern  142   a  exposed to the gap portion may be oxidized to change the first polysilicon pattern into a second silicon oxide layer pattern  170 . In this case, at the exposed side wall of the semiconductor pattern  132 , a silicon oxide layer pattern  170   a  may be formed by an oxidation reaction. The oxidation process may include a radical oxidation process or a plasma oxidation process. Thus, the second silicon oxide layer pattern  170  may be formed as a thermal oxidation layer. 
         [0186]    In a previous process, the height of the first polysilicon pattern, which may be an oxidization target may be largely decreased by the etching of polysilicon. Thus, through conducting a rapid oxidation process, a second silicon oxide layer pattern  170  may be formed. 
         [0187]    In this example embodiment, since the whole first polysilicon pattern  142   a  may be oxidized, polysilicon may not be provided in the first insulating structure. 
         [0188]    As illustrated in the drawings, the second silicon oxide layer pattern  170  may make contact with the pillar structure, and the height in the first direction may be smaller than the height of the first insulating interlayer  110 . Thus, the gap portion adjacent to the pillar structure may have an enlarged shape in a vertical direction due to the second silicon oxide layer pattern  170 . 
         [0189]    Referring to  FIG. 7B  again, a second blocking dielectric layer  164  may be formed along the profile of the insulating interlayer  110 , the first blocking dielectric layer  144 , the first silicon oxide layer  140  and the second silicon oxide layer patterns  170  and  170   a  in the gaps  122   a  and  122   b . Then, a barrier metal layer  166  may be formed on the second blocking dielectric layer  164 , and a metal layer  168  completely filling up the gap portion may be formed. Then, the metal layer  168  and the barrier metal layer  166  formed in the opening portion  160  may be removed to form first and second word line structures  169   a  and  169   b  in the gaps  122   a  and  122   b , respectively. 
         [0190]    The above-described processes may be the same as the explanation referring to  FIGS. 4J and 5F . 
         [0191]    Through conducting the above-described processes, the vertical type semiconductor device illustrated in  FIGS. 7A and 7B  may be formed. 
         [0192]    In this example embodiment, the surface of the oxidation target layer may be oxidized to form an oxide having an insulating property to insulate the oxidation target layer and other conductive patterns from each other. Particularly when polysilicon is used as the oxidation target layer, since the etching selectivity of the polysilicon layer may be high with respect to an etching solution for removing the sacrificial layer, the consumption of the first insulating interlayers may be decreased. 
         [0193]      FIGS. 9A and 9B  are cross-sectional views illustrating methods of forming the vertical type semiconductor device illustrated in  FIG. 7A . 
         [0194]      FIGS. 9A and 9B  are enlarged cross-sectional views on section A in  FIG. 7A . 
         [0195]    The structure illustrated in  FIG. 4C  may be formed by conducting the same procedure explained referring to  FIGS. 4A to 4C . Then, the same processes explained referring to  FIGS. 6A to 6C  may be conducted to form the structure illustrated in  FIG. 6C . That is, the first blocking dielectric layer may be omitted from the structure in  FIG. 6C . 
         [0196]    Hereinafter, an oxidation target layer may be explained as a first polysilicon layer, and an oxidation target layer pattern may be explained as a first polysilicon layer pattern. However, the oxidation target layer and the oxidation target layer pattern may be formed by using silicon nitride. 
         [0197]    Referring to  FIG. 9A , a wet etching process for selectively and slowly etching the first polysilicon layer  142  may be conducted to remove the first polysilicon layer  142  exposed at the gap portion. In addition, a portion of the first polysilicon layer  142  making contact with the first insulating interlayer  110  may be removed. Thus, a first polysilicon pattern having a smaller height than the first insulating interlayer in each layer may be formed. 
         [0198]    An oxidation process may be conducted to oxidize the whole first polysilicon pattern to form a second silicon oxide layer pattern  170 . The oxidation process may include a radical oxidation process or a plasma oxidation process. In the oxidation process, the semiconductor pattern  132  may be oxidized together to form a silicon oxide layer pattern  170   a  on the exposed surface of the semiconductor pattern  132 . 
         [0199]    Then, a first blocking dielectric layer  163  may be formed along the profile of the first insulating interlayer  110 , the first silicon oxide layer  140  and the second silicon oxide layer pattern  170  in the gap. The first blocking dielectric layer  163  may be formed by depositing silicon oxide by a chemical vapor deposition method. 
         [0200]    Referring to  FIG. 9B , a second blocking dielectric layer  164  may be formed on the first blocking dielectric layer  163 . Then, a barrier metal layer  166  may be formed on the second blocking dielectric layer  164 , and a metal layer  168  completely filling up the gap portion may be formed. 
         [0201]    Then, the metal layer  168  and the barrier metal layer  166  formed in the opening portion  160  may be removed to form first and second word line structures  169   a  and  169   b  respectively in the gaps  122   a  and  122   b . The removing process may include a wet etching process. 
         [0202]    Through conducting the above-described processes, the vertical type semiconductor device illustrated in  FIG. 7A  may be manufactured. 
         [0203]    In this example embodiment, by forming an oxide having an insulating property by oxidizing the surface of the oxidation target layer, the oxidation target layer and other conductive patterns may be insulated from each other. Particularly, when polysilicon is used as the oxidation target layer, since the polysilicon may have a high etching selectivity with respect to an etching solution for removing the sacrificial layer, the consumption of the first insulating interlayer may be decreased. 
         [0204]      FIG. 10A  is a cross-sectional view of a vertical type semiconductor device in accordance with Example Embodiment 3.  FIG. 10B  is an enlarged cross-sectional view on section A in  FIG. 10A . 
         [0205]    In  FIG. 10A , channel patterns  150  and  152 , a tunnel insulating layer  148  and a charge storing layer  146  may be illustrated as one layer  149   a . However, the layers may have the same stacked structure as illustrated in  FIG. 10B . 
         [0206]    Referring to  FIGS. 10A and 10B , a vertical memory device may include channel patterns  150  and  152  having a cylindrical shape and extruded and extended in the first direction, and a pillar structure  158  including channel patterns  150  and  152  having a cylinder shape and extruded and extended in the first direction, a first burying insulating layer pattern  154  filling up the inner space of each of the channel patterns  150  and  152 , and a tunnel insulating layer  148 , a charge storing layer  146  and a thermal oxidation layer  182  stacked one by one so as to surround the outer wall of each of the channel patterns  150  and  152 , on a substrate  100 . 
         [0207]    First and second word line structures  169   a  and  169   b  surrounding the side wall of the pillar structure  158  and extended in the third direction may be provided. At one pillar structure  158 , the first and second word line structures  169   a  and  169   b  having a stacked structure with a distance in the first direction may be provided. Between the vertically separated space of the first and second word line structures  169   a  and  169   b , first insulating interlayers  110  may be provided. In addition, the vertical type memory device may further include a common source line (CSL)  178  and a bit line (not illustrated). 
         [0208]    The substrate  100  may include a semiconductor material such as silicon and germanium. 
         [0209]    A semiconductor pattern  132 , channel patterns  150  and  152 , a charge storing layer  146  and a tunnel insulating layer  148  may have the same structure and disposition as explained referring to  FIGS. 1 and 2 . In addition, as explained in  FIG. 1 , a pad  156  may be provided on the pillar structure. 
         [0210]    A thermal oxidation layer  182  provided on the charge storing layer  146  may be provided as a first blocking dielectric layer. The thermal oxidation layer  182  may be an oxide formed by thermally oxidizing polysilicon or silicon nitride. The thermal oxidation layer  182  may be silicon oxide or a SiOC material. 
         [0211]    The first word line structures  190   a  may be disposed while facing the channel patterns  150  and  152  portions. The first word line structures  190   a  may have a shape for filling up a gap portion formed between the first insulating interlayers  110  in each layer in the first direction. 
         [0212]    The first word line structures  190   a  may include a second blocking dielectric layer  164 , a barrier metal layer  166  and a metal layer  168  and may have a stacked structure thereof. The second blocking dielectric layer  164  may make contact with the thermal oxidation layer  182 . Alternatively, silicon oxide may be additionally inserted between the second blocking dielectric layer  164  and the thermal oxidation layer  182 . 
         [0213]    The second word line structures  190   b  may be disposed while facing the semiconductor pattern  132  portion. The second word line structures  190   b  may include the second blocking dielectric layer  164 , a barrier metal layer  166  and a metal layer  168 , and may have a stacked structure thereof. The second blocking dielectric layer  164  may make contact with the semiconductor pattern  132 . Alternatively, silicon oxide may be inserted between the second blocking dielectric layer  164  and the semiconductor pattern  132 . 
         [0214]    The thermal oxidation layer  182  may have a higher etching selectivity with respect to silicon nitride provided as sacrificial layers when comparing with a silicon oxide layer formed by a chemical vapor deposition layer. That is, the thermal oxidation layer  182  may be etched very slowly or may be hardly etched during conducting the etching process of silicon nitride. Thus, the thermal oxidation layer  182  may not be removed ununiformly by the etching process, the thermal oxidation layer  182  may remain to a uniform thickness after conducting the etching process. Thus, processes of removing the thermal oxidation layer  182  and re-depositing the silicon oxide layer uniformly may not be necessary. In addition, the thermal oxidation layer  182  may be used as a first blocking dielectric layer. 
         [0215]      FIGS. 11A to 11D  are cross-sectional views illustrating methods of forming the vertical type semiconductor device in  FIGS. 10A and 10B . 
         [0216]      FIGS. 11A to 11D  are enlarged views on section A in  FIG. 10A . 
         [0217]    First, the structure illustrated in  FIG. 4C  may be formed by conducting the same procedure explained referring to  FIGS. 4A to 4C . 
         [0218]    Referring to  FIG. 11A , a semiconductor pattern  132  partially filling up the lower portion of each of the channel holes  130  may be formed. On the side wall of the channel hole  130  and on the upper surface of the first semiconductor pattern  132  and on a hard mask, a first polysilicon layer  180  may be formed. The first polysilicon layer  180  may be provided as an oxidation target layer for forming a thermal oxidation layer through an oxidation process in a following process. In this example embodiment, polysilicon was used as the oxidation target layer. However, silicon nitride may be used as the oxidation target layer instead of polysilicon. When silicon nitride was used as the oxidation target layer, the same subsequent procedure may be conducted. The final vertical type semiconductor device may be the same as the structure illustrated in  FIG. 10A . 
         [0219]    Referring to  FIG. 11B , the whole first polysilicon layer  180  may be oxidized to form a thermal oxidation layer  182 . The thermal oxidation layer  182  may be silicon oxide or SiOC. 
         [0220]    Referring to  FIG. 11C , a charge storing layer  146 , a tunnel insulating layer  148  and a second polysilicon layer  150  may be formed one by one on the thermal oxidation layer  182 . 
         [0221]    Then, the upper portion of the semiconductor pattern  132  may be exposed by etching the second polysilicon layer  150 , the tunnel insulating layer  148 , the charge storing layer  146  and the thermal oxidation layer  182 . On the surface of the second polysilicon layer  150  and the semiconductor pattern  132 , a third polysilicon layer  152  may be formed. In addition, a first burying insulating layer pattern  154  filling up the channel holes  130  may be formed. 
         [0222]    A portion of the upper portion of the first burying insulating layer pattern  154  may be removed to form openings. In the openings, a polysilicon layer may be formed and polished to form a pad  156  (see  FIG. 10A ). 
         [0223]    Referring to  FIG. 11D , openings  160  (see  FIG. 10A ) penetrating the first insulating interlayers  110  and the sacrificial layers  120  may be formed to expose the upper surface of the substrate  100 . The openings  160  may be formed to define the gap portion between the word line structures. The openings  160  may be formed so as to be extended in the third direction. 
         [0224]    Through removing the sacrificial layers  120  exposed to the side wall of the openings  160  in each layer, a gap  122  between the first insulating interlayers  110  may be formed. A portion of the side wall of the thermal oxidation layer and the semiconductor pattern  132  may be exposed by the gap  122 . 
         [0225]    The removing process of the sacrificial layers  120  may be conducted by a wet etching process using an etching solution having a high etching selectivity with respect to the first insulating interlayer  110 . The etching solution may include phosphoric acid. 
         [0226]    As explained in  FIG. 4F , the contacting time period of the sacrificial layer and the etching solution may be different according to the position of the sacrificial layer  120  during the etching process. Thus, the contacting time of the thermal oxidation layer  182  and the etching solution may be different according to the position of the thermal oxidation layer  182 . 
         [0227]    However, the thermal oxidation layer  182  may have a higher etching selectivity with respect to the sacrificial layer when comparing with silicon oxide formed by a chemical vapor deposition method. Thus, the thermal oxidation layer  182  may be hardly etched by the etching solution. After conducting the removing process of the sacrificial layer, the thickness of the thermal oxidation layer  182  included in the pillar structure of the first to fourth rows may be very uniform. Accordingly, the thermal oxidation layer  182  may be used as a first blocking dielectric layer. That is, the removing of the thermal oxidation layer  182  and re-depositing of the first blocking dielectric layer may be omitted. 
         [0228]    Referring to  FIG. 10B  again, a second blocking dielectric layer  164  may be formed along the surface of the gap  122  portion on the thermal oxidation layer  182 . Then, a barrier metal layer  166  may be formed on the second blocking dielectric layer  164 , and a metal layer  168  for completely filling up the gap  122  portion may be formed. 
         [0229]    Then, first and second word line structures  190   a  and  190   b  may be formed in the gap  122  by removing the metal layer  168  and the barrier metal layer  166  formed in the opening  160 . The removing process may include a wet etching process. 
         [0230]    Through conducting the above-described process, the vertical type semiconductor device having the structure illustrated in  FIG. 10A  may be manufactured. 
         [0231]    In this example embodiment, since the etching process of the polysilicon layer is omitted, the side wall of the semiconductor pattern  132  may not be etched. Accordingly, the side wall of the second word line structure  169   a  making contact with the semiconductor pattern  132  may have a vertical slope. 
         [0232]    In this example embodiment, a thermal oxidation layer formed by using silicon oxide or SiOC may be used as an etch stopping layer while removing the sacrificial layer. Thus, in the removing process of the sacrificial layer, the consumption of the first insulating interlayers may be decreased. Thus, the integration degree of the vertical type semiconductor device may be increased. 
         [0233]      FIG. 12  is a block diagram illustrating an information processing system in accordance with an example embodiment. 
         [0234]    Referring to  FIG. 12 , an information processing system  1100  may include a vertical type nonvolatile memory device  1111  in accordance with exemplary embodiments. 
         [0235]    The information processing system  1100  may include a memory system  1110 , and a modem  1120 , a central processing unit  1130 , a ram  1140  and a user interface  1150  electrically connected to a system bus  1160 , respectively. In the memory system  1110 , data processed by the central processing unit  1130  and data input from outside the system  1100  may be stored. The vertical type nonvolatile memory device  1111  in accordance with an example embodiment may be included in the memory system  1110 , and data may be stably stored by the information processing system  1100 . 
         [0236]    The information processing system  1100  may be further provided with an application chipset, a camera image processor (CIS), a mobile DRAM, an input/output apparatus, etc. 
         [0237]    As described above, the consumption of the insulating interlayer may be restrained in the removal process of the sacrificial layer according to exemplary embodiments. Thus, the height of the insulating interlayer of each layer may be decreased to provide a more highly integrated vertical type semiconductor device. The vertical type semiconductor device may be applied in diverse electronic products and telecommunication products. 
         [0238]    The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.