Abstract:
A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal, and an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and to drive a global input/output line.

Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates to a cell inferiority test circuit of a semiconductor device. 
       BACKGROUND 
       [0002]    With a rapid increase of the integration density of semiconductor memory chips in recent years, more than ten millions of cells are typically integrated in a single memory chip. Increasing number of integrated cells in the chips is inevitably accompanied by an extension of a time for testing defects of cells. For that reason, a general test inferiority test circuit often employs a data compression test mode to shorten a time for testing defects of cells. 
         [0003]    Such a data compression test mode means a scheme inputting/outputting data through a part of input/output pins DQ used in a normal mode and coincidentally testing inferiority from a plurality of cells accessed by the same address. 
         [0004]    A conventional cell inferiority test circuit using the data compression test mode is configured as follows by referring to  FIG. 1 . 
         [0005]    As shown in  FIG. 1 , the conventional cell inferiority test circuit generates compression data, which contains information about inferiority of cells, by compressing right data RDATA&lt; 1 : 16 &gt; or left data LDATA&lt; 1 : 16 &gt; selected in response to the first and second selection signals TPARA&lt; 1 : 2 &gt;. The compression data is loaded on a global input/output line GIO in sync with a strobe signal IOSTR. 
         [0006]    However, the general cell inferiority test circuit is short of loading performance on the global input/output line GIO because of an insufficient timing margin between the strobe signal IOSTR and the compression data due to PVT variations. 
       SUMMARY 
       [0007]    In an embodiment of this disclosure, a cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal, and an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and driving a global input/output line. 
         [0008]    In another embodiment of this disclosure, a cell inferiority test circuit includes a first strobe signal delay circuit configured to delay a strobe signal for a first delay period in response to a first test signal, a second strobe signal delay circuit configured to delay an output signal of the first strobe signal delay circuit for a second delay period, in response to a second test signal, and to output a delayed strobe signal, and an input/output line driver configured to receive compression data in sync with the delayed strobe signal and to drive a global input/output line. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The above and other aspects, features and other advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0010]      FIG. 1  is a block diagram of a conventional cell test circuit; 
           [0011]      FIG. 2  is a block diagram illustrating a configuration of a cell inferiority test circuit in accordance with an embodiment of this disclosure; 
           [0012]      FIG. 3  is a circuit diagram of a compression data generator included in the cell inferiority test circuit shown in  FIG. 2 ; 
           [0013]      FIG. 4  is a circuit diagram of a strobe signal delayer included in the cell inferiority test circuit shown in  FIG. 2 ; and 
           [0014]      FIG. 5  is a circuit diagram of an input/output line driver included in the cell inferiority test circuit shown in  FIG. 2 . 
       
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0015]    Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings. However, the embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. 
         [0016]      FIG. 2  is a block diagram illustrating a configuration of a cell inferiority test circuit in accordance with an embodiment of this disclosure. 
         [0017]    Referring to  FIG. 2 , the cell inferiority test circuit according to this embodiment is comprised of a compression data generator  1 , a strobe signal delayer  2 , and an input/output line driver  3 . Referring to  FIG. 3 , the compression data generator  1  includes a first sensing signal generator  10 , a second sensing signal generator  11 , a selective transmission circuit  12 , and a buffer circuit  13 . The first sensing signal generator  10  executes an exclusive-NOR operation with first through 16th right data RDATA&lt; 1 : 16 &gt; and then generates a first sensing signal SEN 1 . The first sensing signal SEN 1  is generated in a high level if all of the first through 16th right data RDATA&lt; 1 : 16 &gt; from cells of the same address are at the same level. 
         [0018]    The second sensing signal generator  11  executes an exclusive-NOR operation with first through 16th left data LDATA&lt; 1 : 16 &gt; and then generates a second sensing signal SEN 2 . The second sensing signal SEN 2  is generated in a high level if all of the first through 16th left data LDATA&lt; 1 : 16 &gt; from cells of the same address are at the same level. 
         [0019]    The selective transmission circuit  12  selectively transfers the first and second sensing signals, SEN 1  and SEN 2 , in response to first and second selection signals TPARA&lt; 1 &gt; and TPARA&lt; 2 &gt;, respectively. For instance, if the first selection signal TPARA&lt; 1 &gt; is set on a high level, the selective transmission circuit  12  transfers an inverted signal of the first sensing signal SEN 1 . If the second selection signal TPARA&lt; 2 &gt; is set on a high level, the selective transmission circuit  12  transfers an inverted signal of the second sensing signal SEN 2 . The buffer circuit  13  buffers a signal transferred from the selective transmission circuit  12  and then outputs compression data CDATA. The first selection signal TPARA&lt; 1 &gt; is enabled in a high level to select the first through 16th right data RDATA&lt; 1 : 16 &gt;, while the second selection signal TPARA&lt; 2 &gt; is enabled in a high level to select the first through 16th left data LDATA&lt; 1 : 16 &gt;. 
         [0020]    The compression data generator  1  with this configuration outputs an inverted signal of the first sensing signal SEN 1  if the first selection signal TPARA&lt; 1 &gt; is in a high level and the second selection signal TPARA&lt; 2 &gt; is in a low level. Meanwhile, the compression data CDATA is generated in a low level if all of the first through 16th right data RDATA&lt; 1 : 16 &gt; are in the same level, i.e., which means that cells of the same address storing the first through 16th right data RDATA&lt; 1 : 16 &gt; are all determined as normal cells. Otherwise, if the first through 16th right data RDATA&lt; 1 : 16 &gt; are different from each other even in one bit, the compression data generator  1  determines there is a defective cell in the cells of the same address storing the first through 16th right data RDATA&lt; 1 : 16 &gt; and then generates the compression data CDATA in a high level. In the meantime, the compression data generator  1  outputs an inverted signal of the second sensing signal SEN 2  when the first and second selection signals, TPARA&lt; 1 &gt; and TPARA&lt; 2 &gt;, are set on low and high levels, respectively. Meanwhile, if the first through 16th left data LDATA&lt; 1 : 16 &gt; are all in the same level, i.e., if all of the cells of the same address storing the first through 16th left data LDATA&lt; 1 : 16 &gt; are all determined as normal cells, the compression data CDATA is generated in a low level. Otherwise, if the first through 16th left data LDATA&lt; 1 : 16 &gt; are different from each other even in one bit, the compression data generator  1  determines there is a defective cell in the cells of the same address storing the first through 16th left data LDATA&lt; 1 : 16 &gt; and generates the compression data CDATA in a high level. Thus, the compression data CATA includes information regarding cell inferiority, that is, one or more cells do not meet performance specifications. 
         [0021]    The strobe signal delayer  2 , referring to  FIG. 4 , is comprised of a strobe signal transmission circuit  20  and a delayed strobe signal generation circuit  21 . 
         [0022]    The strobe signal transmission circuit  20  includes a logic circuit  200  executing an OR operation with the first and second selection signals TPARA&lt; 1 : 2 &gt;, and a NAND gate ND 20  acting as a transmission device for transferring a strobe signal IOSTR in response to an output signal of the logic circuit  200 . The strobe signal transmission circuit  20  with this configuration transfers an inverted signal of the strobe signal IOSTR if one of the first and second selection signals TPARA&lt; 1 : 2 &gt; is enabled to a high level. Here, the strobe signal IOSTR is designed to go to a high level if at least one of the first and second selection signals TPARA&lt; 1 : 2 &gt; is enabled to a high level. 
         [0023]    The delayed strobe signal generation circuit  21  includes a first strobe signal delay circuit  210 , a second strobe signal delay circuit  211 , and a third strobe signal delay circuit  212 . 
         [0024]    The first strobe signal delay circuit  210  is comprised of a NAND gate ND 21  transferring an output signal of the strobe signal transmission circuit  20  in response to a first test signal TM&lt; 1 &gt;, a first delay unit  213  delaying the output signal of the strobe signal transmission circuit  20  by a predetermined amount of time, a NAND gate ND 22  transferring an output signal of the first delay unit  213  in response to an inverted signal of the first test signal TM&lt; 1 &gt;, and a NAND gate ND 23  effectively transferring output signals of the NAND gates ND 21  and ND 22  in response to the first test signal TM&lt; 1 &gt;. The first strobe signal delay circuit  210  with this configuration transfers the output signal of the strobe signal transmission circuit  20  through the NAND gates ND 21  and ND 23  if the first test signal TM&lt; 1 &gt; is at a high level. If the first test signal TM&lt; 1 &gt; is at a low level, the first strobe signal delay circuit  210  transfers the output signal of the strobe signal transmission circuit  20  through the delay circuit  213  and the NAND gates ND 22  and ND 23 . 
         [0025]    The second strobe signal delay circuit  211  is comprised of a NAND gate ND 24  transferring an output signal of the first strobe signal delay circuit  210  in response to a second test signal TM&lt; 2 &gt;, a second delay unit  214  delaying the output signal of the first strobe signal delay circuit  210  in a predetermined amount of time, a NAND gate ND 25  transferring an output signal of the second delay unit  214  in response to an inverted signal of the second test signal TM&lt; 2 &gt;, and a NAND gate ND 26  effectively transferring output signals of the NAND gates ND 24  and ND 25  in response to the second test signal TM&lt; 2 &gt;. The second strobe signal delay circuit  211  with this configuration transfers the output signal of the first strobe signal delay circuit  210  through the NAND gates ND 24  and ND 26  if the second test signal TM&lt; 2 &gt; is at a high level. If the second test signal TM&lt; 2 &gt; is at a low level, the second strobe signal delay circuit  211  transfers the output signal of the first strobe signal delay circuit  210  through the delay circuit  214  and the NAND gates ND 25  and ND 26 . 
         [0026]    The third strobe signal delay circuit  212  is comprised of a NAND gate ND 27  transferring an output signal of the second strobe signal delay circuit  211  in response to a third test signal TM&lt; 3 &gt;, a third delay unit  215  delaying the output signal of the second strobe signal delay circuit  211  by a predetermined amount of time, a NAND gate ND 28  transferring an output signal of the third delay unit  215  in response to an inverted signal of the third test signal TM&lt; 3 &gt;, and a logic circuit  216  effectively transferring output signals of the NAND gates ND 27  and ND 28  as a delayed strobe signal IOSTRD in response to the third test signal TM&lt; 3 &gt;. The third strobe signal delay circuit  212  with this configuration transfers the output signal of the second strobe signal delay circuit  211  as the delayed strobe signal IOSTRD through the NAND gate ND 27  and the logic circuit  216  if the third test signal TM&lt; 3 &gt; is at a high level. If the third test signal TM&lt; 3 &gt; is at a low level, the third strobe signal delay circuit  212  transfers the output signal of the second strobe signal delay circuit  211  as the delayed strobe signal IOSTRD through the third delay circuit  215 , the NAND gate ND 28 , and the logic circuit  216 . 
         [0027]    The input/output line driver  3 , referring to  FIG. 5 , is comprised of a drive signal generation circuit  30  and a drive circuit  31 . The drive signal generation circuit  30  includes a logic circuit  300  generating a pull-up signal PU through an OR operation with the compression data CDATA and the delayed strobe signal IOSTRD, and a logic circuit  301  generating a pull-down signal PD through an OR operation with the compression data CDATA and an inverted signal of the delayed strobe signal IOSTRD. The drive circuit  31  functions to drive a global input/output line GIO in response to the pull-up and pull-down signals PU and PD. 
         [0028]    Now operation of the cell inferiority test circuit is explained. 
         [0029]    First, the compression data generator  1  outputs the compression data CDATA based on the first through 16th right data RDATA&lt; 1 : 16 &gt; or the first through 16th left data LDATA&lt; 1 : 16 &gt; depending on logical combinations of the first and second selection signals TPARA&lt; 1 : 2 &gt;. In more detail, if the first selection signal TPARA&lt; 1 &gt; is set at a high level while the second selection signal TPARA&lt; 2 &gt; is set at a low level, the inverted signal of the first sensing signal SEN 1  is transferred as the compression data CDATA by way of the NAND gates ND 10  and ND 12  of the selective transmission circuit  12  and the buffer circuit  13 . In this case, the compression data CDATA is generated in a low level if cells of the same address from which the first through 16th right data RDATA&lt; 1 : 16 &gt; are output are determined as normal cells. If the cells of the same address storing the first through 16th right data RDATA&lt; 1 : 16 &gt; are determined as including at least one defective cell, the compression data CDATA is generated in a high level. On the other hand, if the first selection signal TPARA&lt; 1 &gt; is at a low level while the second selection signal TPARA&lt; 2 &gt; is at a high level, the inverted signal of the second sensing signal SEN 2  is transferred as the compression data CDATA by way of the NAND gates ND 11  and ND 12  of the selective transmission circuit  12  and the buffer circuit  13 . In this case, the compression data CDATA is generated in a low level if cells of the same address from which the first through 16th left data LDATA&lt; 1 : 16 &gt; are output are determined as normal cells. If the cells of the same address storing the first through 16th left data LDATA&lt; 1 : 16 &gt; are determined as including at least one defective cell, the compression data CDATA is generated in a high level. 
         [0030]    Next, the strobe signal delayer  2  generates the delayed strobe signal IOSTRD by delaying the strobe signal IOSTR in response to the first through third test signals TM&lt; 1 : 3 &gt; if the first or second selection signal, TPARA&lt; 1 &gt; or TPARA&lt; 2 &gt;, is set on a high level. In more detail, the strobe signal IOSTR, which is enabled in a high level when the first selection signal TPARA&lt; 1 &gt; or the second selection signal TPARA&lt; 2 &gt; is set on a high level, is delayed by a period established through the first strobe signal delay circuit  210 , the second strobe signal delay circuit  211 , and the third strobe signal delay circuit  212  and then output as the delayed strobe signal IOSTR. During this, a time at which the delayed strobe signal IOSTRD is enabled is dependent on combinational logic with the first through third test signals TM&lt; 1 : 3 &gt;. For instance, if both of the first and third test signals TM&lt; 1 : 3 &gt; are at high levels, a delay period through the first strobe signal delay circuit  210 , the second strobe signal delay circuit  211 , and the third strobe signal delay circuit  212  is set in the shortest to make an enabling time of the delayed strobe signal IOSTRD most advanced. Meanwhile, if both of the first and third test signals TM&lt; 1 : 3 &gt; are at low levels, the delay period through the first strobe signal delay circuit  210 , the second strobe signal delay circuit  211 , and the third strobe signal delay circuit  212  is set in the longest to make an enabling time of the delayed strobe signal IOSTRD most postponed. 
         [0031]    Then, the input/output line driver  3  receives the compression data CDATA and the delayed strobe signal IOSTRD and drives the global input/output line GIO. In detail, if the compression data CDATA is conditioned in a low level, i.e., all of the cells of the same address from which data for generating the compression data CDATA are output are determined as normal cells, the pull-up signal PU is generated with a low level in a period when the delayed strobe signal IOSTRD is enabled in a low level, and the global input/output line GIO is driven in a high level. Therefore, a high level signal of the global input/output line GIO informs that all of the cells of the same address are normal cells without defects. On the other hand, if the compression data CDATA is conditioned in a high level, the global input/output line GIO is driven in a low level to inform that the cells of the same address include at least one defective cell. 
         [0032]    As described above, the cell inferiority test circuit according to this embodiment is useful in processing a data compression test mode for finding out a defect from cells of the same address even in the environment of PVT variations, in which the first through third test signals TM&lt; 1 : 3 &gt; function to control an enabling time of the delayed strobe signal IOSTRD for the purpose of adjusting a timing margin between the compression data CDATA and the delayed strobe signal IOSTRD. For instance, if a timing margin between the compression data CDATA and the delayed strobe signal IOSTR is insufficient, at least one of the first through third test signals TM&lt; 1 : 3 &gt; transitions from high to low level is to delay the enabling time of the delayed strobe signal IOSTRD. Hence, it is possible to secure a sufficient timing margin between the compression data CDATA and the delayed strobe signal IOSTRD. 
         [0033]    While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. 
         [0034]    The present application claims priority to Korean application number 10-2009-0026044, filed on Mar. 26, 2009, which is incorporated by reference in its entirety.