Abstract:
A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the priority benefit of French patent application Ser. No. 10/55050, filed on Jun. 24, 2010, entitled “Differential Successive approximation Analog to Digital Converter,” which is hereby incorporated by reference to the maximum extent allowable by law. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a differential successive approximation (SAR) analog to digital converter (ADC). In particular, the present invention relates to a differential SAR ADC and a method of performing successive approximation for analog to digital conversion based on a capacitor array. 
     2. Discussion of the Related Art 
     SAR ADC converters generally comprise one or more n-bit converters that operate in parallel. Each n-bit converter is arranged to sample an input voltage, and generates an n-bit digital value corresponding to the amplitude of the input voltage. 
     Generating the n-bit digital value generally involves sampling each component of the differential input signal by corresponding sets of capacitors each having binary weighted capacitance values corresponding to the most significant to least significant bits of the n-bit output signal. The sets of capacitors are coupled to respective inputs of a comparator, and a trial and error process is then used to determine, for each capacitor in turn, what combination of high and low voltages coupled to each capacitor balances the comparator. 
     The operating speed of such a converter is determined to some extent by the speed at which the capacitors may be recharged between each bit decision, and this is determined by the amount of charge that needs to be drawn from the supply voltages after each bit decision. If the charge can not be drawn fast enough to recharge the capacitors, the signature of the input signal may remain on the capacitors, leading to a non-linearity in the operation of the converter. Furthermore, the more charge that needs to be drawn, the greater the power consumption of the converter. 
     One option for reducing the amount of charge that needs to be transferred from the supply voltages would be to reduce the size of each of the capacitors. However, this can increase the noise and reduce linearity leading to errors in the output signal. 
     Thus there is a need for an improved differential converter that draws a reduced charge from the supply voltages. 
     SUMMARY OF THE INVENTION 
     Embodiments aim to at least partially overcome one or more needs in the prior art. 
     According to one embodiment, there is provided a differential successive approximation analog to digital converter comprising: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level. 
     According to an embodiment, the converter comprises a register arranged to store outputs of the comparator, wherein each of the first and second switches is adapted to be controlled based on values stored in the register. 
     According to another embodiment, the first and second plurality of switches are also each adapted to independently coupled the corresponding capacitor to the first or second component of the differential input signal. 
     According to another embodiment, the register comprises a plurality of latches arranged to store outputs of the comparator. 
     According to another embodiment, each of the first and second switches comprises four transistors coupled between the corresponding capacitor and a respective one of the component of the differential input signal, the first voltage level, the second voltage level and the third supply level. 
     According to another embodiment, the converter further comprises control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third voltage level at the start of a voltage conversion phase. 
     According to another embodiment, the first and second plurality of capacitors each comprises N capacitors  1  to N each having a corresponding capacitance equal to 
             C     2   i           
where the total capacitance of the first set of capacitors is equal to
 
     
       
         
           
             C 
             - 
             
               C 
               
                 2 
                 N 
               
             
           
         
       
     
     According to another embodiment, the converter further comprises a first additional capacitor coupled between the first input of the comparator and a third switch, and a second additional capacitor coupled between the second input of the comparator and a fourth switch wherein the first and second additional capacitors each have a capacitance equal to 
     
       
         
           
             C 
             
               2 
               N 
             
           
         
       
     
     According to another embodiment, there is provided an analog to digital conversion unit comprising a plurality of the above converters arranged to sample the differential input signal in turn. 
     According to an embodiment, each of the analog to digital converters is an n-bit converter, and further comprising a first output register arranged to receive the n−1 most significant bits of the n-bit output value from each converter, and a second output register arranged to receive the least significant bit of the output register. 
     According to a further embodiment, there is provided an electronic device comprising the above analog to digital conversion unit. 
     According to a further embodiment, there is provided a method for performing analog to digital conversion by a differential successive approximation converter comprising: storing on a first plurality of capacitors a first component of a differential input signal; storing on a second plurality of capacitors a second component of the differential input signal; coupling each of the first plurality of capacitors between a third supply voltage level and a first input of a comparator; coupling each of the second plurality of capacitors between a third supply voltage level and a second input of the comparator; and based on an output of the comparator, coupling a capacitor of the first plurality of capacitors to a first voltage level and coupling a capacitor of the second plurality of capacitors to a second voltage level. 
     According to an embodiment, the third supply voltage level is a voltage level other than a mid-point between the first and second voltage levels. 
     According to another embodiment, the method further comprises, after coupling the capacitors of the first and second plurality to the first and second voltage levels respectively, determining a next output bit, and coupling another capacitor of each of the first and second plurality of capacitors to one of the first and second voltage levels. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other purposes, features, aspects and advantages of the invention will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which: 
         FIG. 1  illustrates an example of a SAR ADC; 
         FIG. 2  is a flow diagram showing an example of steps for performing analog to digital conversion based on the circuit of  FIG. 1 ; 
         FIG. 3  illustrates a SAR ADC according to an embodiment; 
         FIG. 4  is a flow diagram illustrating steps in a method for performing analog to digital conversion based on the circuitry of  FIG. 3  according to embodiments; 
         FIG. 5  illustrates a switch of the circuit of  FIG. 3  in more detail according to embodiments; 
         FIG. 6  illustrates an analog to digital conversion unit according to embodiments; 
         FIG. 7  is a timing diagram showing the timing of signals in the analog to digital conversion unit of  FIG. 6  according to an embodiment; 
         FIGS. 8A ,  8 B,  9 A,  10  and  11  illustrate circuitry for generating control signals for controlling transistors of the switch of  FIG. 5  according to embodiments; 
         FIG. 9B  shows timing diagrams corresponding to the circuitry of  FIG. 9A  according to an embodiment; and 
         FIG. 12  illustrates an electronic device comprising the analog to digital conversion unit of  FIG. 6  according to embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates an example of a 4-bit SAR ADC  100 . Converter  100  comprises a comparator  101 , which provides an output to a 4-bit register  102  for storing a binary value resulting from the conversion. 
     Five switches  104  to  108  on a left-hand side of the converter, and five corresponding switches  104 ′ to  108 ′ on a right-hand side of the converter, are controlled based on the bits stored in register  102 . The switches  104  to  108  are coupled to one terminal of respective capacitors C 1  to C 5 , respectively having capacitances C/2, C/4, C/8, C/16 and C/16. Thus, the capacitance of each capacitor C 1  to C 4  is a different fraction of the total capacitance C of the capacitors C 1  to C 5 . Similarly, the switches  104 ′ to  108 ′ are coupled to one terminal of respective capacitors C 1 ′ to C 5 ′, respectively having capacitances C/2, C/4, C/8, C/16 and C/16. 
     Each of the capacitors C 1  to C 5  has its other terminal connected to a node  109 , which is, in turn, coupled to a negative input of the comparator  101 . The voltage at node  109  is labelled Vap. Likewise, each of the capacitors C 1 ′ to C 5 ′ has its other terminal connected to a node  109 ′, which is in turn coupled to the positive input terminal of comparator  101 . The voltage at node  109 ′ is labelled Van. Nodes  109  and  109 ′ are further coupled to a supply voltage Vs via respective switches  110  and  110 ′. 
     Operation of the converter  100  of  FIG. 1  will now be described with reference to the flow diagram of  FIG. 2 . 
     In a first step S 0 , a sample phase is performed, in which each of the switches  104  to  108  is coupled to a first component Vinp of the differential input signal and each of the switches  104 ′ to  108 ′ is coupled to a second component Vinn of the differential input signal. At the same time, the nodes  109  and  109 ′ are connected, via switches  110  and  110 ′ respectively, to the supply voltage Vs, which is for example at 0 V. This connection state of each of the switches is shown by the solid line of each switch. In this way the capacitors C 1  to C 5  and C 1 ′ to C 5 ′ are charged based on the differential input signal. 
     In a next step S 1 , nodes  109  and  109 ′ are isolated from the supply voltage Vs by opening switches  110  and  110 ′, and capacitors C 1  and C 2 ′ to C 5 ′ are coupled to a high supply voltage Vtop via switches  104  and  105 ′ to  108 ′ respectively, while capacitors C 1 ′ and C 2  to C 5  are coupled to a supply voltage Vbot via switches  104 ′ and  105  to  108  respectively. This connection state of each of the switches is shown by the dashed line in each switch. The voltages Vtop and Vbot are, for example, equal to 0.5 V and 0 V respectively, although other values could be used. 
     In a next step S 2 , the comparator determines whether Vap is greater than Van. In particular, with the configuration of the switches  104  to  108  and  104 ′ to  108 ′ as shown by the dashed lines in  FIG. 1 , on the left-hand side of the comparator, the capacitor C 1  has half of the total capacitance C, and the capacitors C 2  to C 5  share the other half of the total capacitance C. Similarly for the right-hand side of the converter. It can be demonstrated that in step S 2 , Vap−Van=−(Vinp−Vinn). 
     Thus if Vap is less than Van, the output of the comparator is high, and the next step is S 3 , in which the most significant bit of the binary value is determined to be equal to “1”, and the decision is made to keep C 1  coupled to Vtop, and to keep C 1 ′ coupled to the Vbot. 
     On the other hand, if Vap is greater than Van, the output of comparison is low, and the next step is S 4 , in which the most significant bit will be determined to be “0”. In this case, the coupling of capacitors C 1  and C 1 ′ is modified, such that C 1  is coupled to Vbot, and C 1 ′ is coupled to Vtop. 
     After steps S 3  and S 4 , the next step is S 5 , in which the next bit of the output value is determined, by coupling C 2  to Vtop and C 2 ′ to Vbot. 
     Next, in S 6 , again Vap is compared to Van, and then based on this comparison, steps similar to S 3  and S 4  are performed. For the sake of brevity, the subsequent steps are not illustrated in  FIG. 2 , but involve determining the value of the next bit, and deciding whether or not to keep C 2  coupled to Vtop and C 2 ′ coupled to Vbot. This same process then continues for the next capacitors C 3  and C 3 ′, and then for capacitors C 4  and C 4 ′, which correspond to the least significant bit of the 4-bit output value. However, capacitors C 5  and C 5 ′ remain coupled to Vbot and Vtop respectively. 
     Thus determining each bit value according to the method of  FIG. 2  is two-step approach: a first step of switching a corresponding capacitor to be connected to Vtop or Vbot; and a second step of deciding whether to keep this connection or to change it. 
     A disadvantage of this two-step approach is that a relative large quantity of charge flows from the supply voltages. Furthermore, the charge flow is dependent on the particular decision that is taken. In particular, charge is shifted to/from the corresponding capacitors during the first phase, and may or may not need to be shifted from/to the corresponding capacitors again during the second phase, based on the decision. Furthermore, the residue charge remaining on the capacitors after each conversion is not constant, and thus there will be a variable voltage offset leading to noise in the output signal. 
       FIG. 3  illustrates an alternative embodiment of a 4-bit SAR ADC  300 . Converter  300  comprises a comparator  101  and a 4-bit register  102  similar as to SAR ADC  100  of  FIG. 1 . A left-hand side of the converter  300  as illustrated comprises just four capacitors C 1  to C 4 , having respective capacitance values C/2, C/4, C/8 and C/8. These capacitors are coupled on one side to switches  301  to  304  respectively. Similarly, a right-hand side of the converter  300  as illustrated comprises capacitors C 1 ′ to C 4 ′, also having values C/2, C/4, C/8 and C/8 respectively, and which are respectively coupled to switches  301 ′ to  304 ′. As with the embodiment of  FIG. 1 , the other sides of capacitors C 1  to C 4  and C 1 ′ to C 4 ′ are coupled to nodes  109  and  109 ′ respectively, which are in turn coupled to the negative and positive inputs respectively of comparator  101 . Furthermore, nodes  109  and  109 ′ are coupled to a supply voltage Vs via switches  110  and  110 ′ respectively. 
     In the embodiment of  FIG. 1 , each of the switches  104  to  107  and  104 ′ to  107 ′ allows the corresponding capacitor to be coupled to one of three voltages: the input voltage Vinp or Vinn; the high supply voltage Vtop; or the low supply voltage Vbot. In the embodiment of  FIG. 3 , in addition to each of these three voltages, the switches  301  to  303  and  301 ′ to  303 ′ allow the corresponding capacitor to be connected to a supply voltage Vc. Furthermore, whereas switch  108  of  FIG. 1  allows the final capacitor C 5  to be coupled to input voltage Vinp or supply voltage Vbot, switch  304  of  FIG. 3  allows the final capacitor C 4  to be coupled to input voltage Vinp or supply voltage Vc Likewise, whereas switch  108 ′ of  FIG. 1  allows the final capacitor C 5 ′ to be coupled to input voltage Vinn or supply voltage Vtop, switch  304  of  FIG. 3  allows the final capacitor C 4  to be coupled to input voltage Vinn or supply voltage Vc. 
     The voltage Vc is a voltage level for example between Vtop and Vbot, and, for example, at the mid-point between these supply voltages, although other values are possible. For example, assuming Vtop is equal to 0.5 V and that Vbot is equal to 0 V, Vc could equal 0.25 V, or a different value, such as 0.4 V. Furthermore, because the same supply voltage Vc is provided to both sides of differential converter, this voltage may fluctuate without degrading the output signal. 
     The operation of the circuit  300  of  FIG. 3  will now be described with reference to the flow diagram of  FIG. 4 . The 4 bits of the output of the comparator will be referred to as B 3  to B 0 , where B 3  is the most significant bit (MSB). 
     In a first step S 0 , a sample phase is performed, in which, in a similar fashion to the circuit  100  of  FIG. 1 , the nodes  109  and  109 ′ are coupled to the supply voltage Vs via switches  110  and  110 ′, and at the same time each of the switches  301  to  304  is coupled to the input voltage Vinp, and each of the switches  301 ′ to  304 ′ is coupled to the input voltage Vinn. This connection state is shown by a solid line in each switch of  FIG. 3 . 
     Next, in step S 1 , the comparator inputs are isolated from supply voltage Vs by opening switches  110  and  110 ′, and the capacitors C 1  to C 4  and C 1 ′ to C 4 ′ are all coupled to supply voltage Vc. This configuration is shown by a dashed line in each switch of  FIG. 3 . 
     In a next step S 2 , the comparator determines whether Vap is greater than Van, which is the same as determining whether Vinp is greater than Vinn. In particular, initially Vap=Vs+(Vc−Vinp), while Van=Vs−(Vinn−Vc), and thus Vap Van=(Vinp−Vinn), and so the comparison is between Vinp and Vinn. 
     If it is determined in S 2  that Vinp is greater than Vinn, then the next step is S 3 , in which the MSB B 3  of the 4-bit output is set to “1”, and switches  301  and  301 ′ are switched such that capacitor C 1  is coupled to Vtop, and capacitor C 1 ′ is coupled to Vbot. 
     Alternatively, if it is determined in S 2  that Vinp is less than Vinn, then the next step is S 4 , in which the MSB B 3  of the 4-bit output is set to “0”, and switches  301  and  301 ′ are switched such that capacitor C 1  is coupled to Vbot, and capacitor C 1 ′ is coupled to Vtop. 
     After steps S 3  and S 4 , the next step is S 5 , in which again Vap and Van are compared by the comparator. Now however capacitors C 1  and C 1 ′ have been coupled to one of the supply voltages Vtop and Vbot. If C 1  was coupled to Vtop and C 1 ′ was coupled to Vbot in step S 3 , due to the binary weighting of capacitor C 1  in the capacitor array, Vap becomes equal to Vs+(Vc−Vinp)+(Vtop−Vc)/2, while Van becomes equal to Vs+(Vc−Vinn)−(Vc−Vbot)/2. Thus Vap−Van is equal to −(Vinp−Vinn)+(Vtop−Vbot)/2. Alternatively, if C 1  was coupled to Vbot and C 1 ′ to Vtop in step S 4 , Vap−Van is equal to −(Vinp−Vinn)−(Vtop−Vbot)/2. 
     If it is determined in S 5  that Vap is less than Van, the next step is S 6 , in which B 2  is set equal to “1”, capacitor C 2  is coupled to Vtop, and capacitor C 2 ′ is coupled to Vbot. 
     Alternatively, if it is determined in S 5  that Vap is greater than Van, the next step is S 7 , in which B 2  is set equal to “0”, capacitor C 2  is coupled to Vbot, and capacitor C 2 ′ is coupled to Vtop. 
     After steps S 6  and S 7 , the method continues by comparing again Vap and Van based on the new connections of the capacitors C 2  and C 2 ′, but this step and subsequent switching steps of C 1  and C 1 ′ are not illustrated for the sake of brevity. Instead, the method goes straight to a step S 8 , once each of the switches  301  to  303  and  301 ′ to  303 ′ has been connected to either Vtop or Vbot. 
     In step S 8 , the least significant bit B 0  of the output value is determined, based on a comparison of Vap and Van. 
     If in S 8  it is determined that Vap is less than Van, the next step is S 9 , in which B 0  is set to “1”. 
     Alternatively, if in S 8  it is determined that Vap is greater than Van, the next step is S 10 , in which B 0  is set to “0”. 
     It will be noted that in this final step, because the decision concerning B 0  can be taken before switching a corresponding capacitor, the switching of this capacitor doesn&#39;t need to take place, and thus there is no equivalent of capacitors C 4  and C′ 4  of  FIG. 1 , nor switches  107  and  107 ′ in converter  300 . Thus a pair of capacitors and switches may be removed. 
     Capacitors C 4  and C 4 ′, which remain coupled to Vc throughout the voltage detection process, can be omitted in alternative embodiments. The purpose of these capacitors is to bring the total capacitance to C, which results in a unity gain converter. Otherwise, gain is equal to 1½N, where N is the number of bits. 
     Thus in the conversion process of  FIG. 4 , the bit decisions are made using one step rather than two steps, by a single switching operation after each comparison. Thus, the current drawn from the supplies is the same for each of the corresponding decisions of each bit. 
     While the embodiment of  FIG. 3  is a 4-bit converter, it will be apparent to those skilled that an N-bit converter, with N, for example, a value in the range 2 to 32, could be implemented using fewer or more capacitors. 
       FIG. 5  illustrates an example of the implementation of a switch  500 , which represents any of the switches  301  to  304  of  FIG. 3 , and the same implementation could be used for any of the switches  301 ′ to  304 ′, but with the Vinp input replaced by the Vinn input. 
     Switch  500  receives, at four corresponding input terminals, the voltages Vinp, Vtop, Vc and Vbot, and allows one of these voltages to be selectively coupled to the capacitor Ci, which is, for example, any of the capacitors C 1  to C 3 . Switches  304  and  304 ′ can be implemented by similar circuitry, but without the Vtop and Vbot inputs. 
     The switch  500  comprises four transistors  501  to  504  each coupled by their main current terminals between a terminal  506  of capacitor Ci and a respective one of the input lines for receiving the voltage Vinp, Vtop, Vc or Vbot. Each of the transistors  501  to  504  is for example a MOS transistor, although other types of transistors could be used. Transistor  501  is controlled by a control signal “TRCK” at its gate node to couple the input voltage Vinp to terminal  506 . In this example, control signal “TRCK” is equal to a timing signal P 1 L, described in more detail below. The transistor  502  is controlled by a control signal Di at its gate node to couple the supply voltage Vtop to terminal  506 , while transistor  504  is controlled by a control signal  Di  at its gate node to couple the supply voltage Vbot to node  506 , which is the inverse of signal Di, except during reset. Transistor  503  is controlled by a control signal CMMLi at its gate node to couple the supply voltage Vc to terminal  506 . 
       FIG. 5  also shows the connection of capacitor Ci to node  109 , which, as represented by a dashed line  508 , is in turn coupled to the other capacitors. Furthermore, the switch  110  coupling node  109  to supply voltage Vs is illustrated, comprising a transistor, which is, for example, also a MOS transistor, and is controlled at its gate node by a control signal “SHNT”, in this example equal to the logic AND operation between two timing signals P 8 L and P 1 L described in more detail below. 
       FIG. 6  illustrates an embodiment of an analog to digital conversion unit  600 , which comprises in this example eight SAR ADCs  601  to  608  operating in a cyclic manner. Each of the converters  601  to  608  is for example similar to converter  300  of  FIG. 3 , but in this example is a 6-bit converter, and thus comprises capacitors C 1  to C 5  having capacitances C/2, C/4, C/8, C/16 and C/32 respectively, and capacitors C 1 ′ to C 5 ′ also having capacitances C/2, C/4, C/8, C/16 and C/32 respectively. It may optionally comprise sixth capacitors C 6  and C 6 ′ each having a capacitance value of C/32, and performing similar roles to capacitors C 4  and C 4 ′ of  FIG. 3 . There is a phase shift between the operations of each converter  601  to  608 , such that the differential input signal is sampled at eight times the effective supply frequency of each converter. In this example, each converter  601  to  608  comprises a digital portion  601 A to  608 A respectively, and an analog portion  601 B to  608 B respectively. 
     The digital portions  601 A to  608 A each comprise the switching control logic, in particular the circuitry for controlling switches  500  and the switches  110  and  110 ′ of  FIG. 5 . The analog portions  601 B to  608 B each comprise the switches  500  and  110 , the capacitors C 1  to C 5 , and the comparator  101 . Thus the connections, represented in  FIG. 6  by an arrow from each digital portion  601 A to  608 A to the corresponding analog portion  601 B to  608 B provide the control signals TRCK, Di and its inverse, CMMLi and SHNT, while further connections, represented in  FIG. 6  by an arrow from each analog portion  601 B to  608 B to the corresponding digital portion  601 A to  608 A, provide the output of the comparator. 
     An input  609  comprises a pair of lines for receiving the differential input signal Vinp, Vinn, which is then sampled by each of the analog portions  601 B to  608 B. The supply voltages Vtop, Vbot and Vc (not illustrated) are also provided to each analog portion  601 B to  608 B. 
     A clock signal CLK is received on an input line  610  to the conversion unit  600 , having, for example, a frequency of 1 GHz, although other frequencies are possible. The clock signal is provided to a timing distribution block  612 , which generates 8 timing signals P 1 L to P 8 L based on the clock signal CLK. These signals are all provided to each of the eight digital portions  601 A to  608 B, but in a different order, as will be explained in more detail below. The clock signal CLK is also coupled to each of the analog portions  601 B to  608 B, for controlling the decision timing of the comparator. 
     An output register  614 , for example, comprises five flip-flops, and receives output bits B 1  to B 5 , from each of the digital portions  601 A to  601 B in turn on a line  615 . A further output register  616 , for example, comprises 6 flip-flops, which receive the least significant bit B 0  from each of the digital portions  601 A to  601 B on a line  617 , and the five bits from output register  614 . The output register  616  outputs a 6-bit output signal on an output line  618 . 
     Operation of the conversion unit  600  of  FIG. 6  will now be described with reference to the timing diagrams of  FIG. 7 . 
     A first signal  701  is the clock signal CLK, as received on the input line  610 , comprising of a square wave, for example, with a frequency of 1 GHz. 
     A group of signals  702  is then shown, representing the timing signals P 1 L to P 8 L generated by the generation block  612  and provided to each of the digital portions  601 A to  608 A. As illustrated, the first timing signal P 1 L comprises one positive pulse of the clock signal CLK once every 8 periods of the clock signal CLK. The other timing signals PjL, for j equal to 2 to 8, are the same as the first timing signal P 1 L, but with their positive pulses delayed by j−1 clock periods of the clock signal CLK. Thus the positive pulse of timing signal P 8 L occurs seven clock periods after the pulse of signal P 1 L, which is one clock period before the next positive pulse of the timing signal P 1 L. 
     A next signal  703  is the control signal TRCK, which controls when the input voltage is coupled to each of the capacitors, and is identical to the first timing signal P 1 L. 
     A next signal  704  is the signal “SHNT” that controls when the nodes  109  and  109 ′ are coupled to the supply voltage Vs, and is equal to a logic AND between timing signals P 1 L and P 8 L. During the high pulse of P 1 L, the input signal is sampled to the capacitors, and thus nodes  109  and  109 ′ are coupled to Vs. The voltages at nodes  109  and  109 ′ are reset for example for offset calibration purposes, although offset calibration is optional. During offset calibration, the switches are all coupled to supply voltage Vc, the inputs of the comparator  101  are grounded, and the output of the comparator is measured. 
     The next group of signals  705  shows the control signal CMMLi for controlling when the supply voltage Vc is coupled to each capacitor C 1  to C 5 , and also, with dashed lines, the control signals Di and  Di  for controlling when supply voltages Vtop and Vbot are coupled to each capacitor. 
     Between the rising edges of the timing signals P 2 L and P 3 L, all the signals CMML 1  to CMML 5  are high. At the rising edge of timing signal P 3 L, the signal CMML 1  goes low, and either D 1  or  Di  goes high until the next rising edge of timing signal P 8 L, depending on the decision of the comparator just before CMML 1  goes low. The value of D 1  corresponds to the MSB of the output value, which in this example is bit B 5 . Next, at the rising edge of the timing signal P 4 L, the signal CMML 2  goes low, and either D 2  or  D 2    goes high until the next rising edge of the timing signal P 8 L, depending on the decision of the comparator just before CMML 2 . The value of D 2  corresponds to bit B 4  of the output value. This process continues, until the rising edge of timing signal P 7 L, when the final control signal D 5  or  D 5    goes high, and all the signals CMML 1  to  5  are low. Then, at the rising edge of timing signal P 8 L, all the signals D 1  to D 5  go low, and the signals CMML 1  to CMML 5  go high, coupling the capacitors to the supply voltage Vc while they are reset. 
     The next signal  706  shows, by a dashed line, the bit value of B 0  being output, based on the decision of the comparator during the switch configuration present between the rising edge of P 7 L and the rising edge of P 8 L. As explained above, no capacitor is switched based on this final bit value. 
     The next signal  707  shows the assertion of a write signal in respect of the bits B 5  to B 1 , which occurs between the rising edges of timing signals P 7 L and P 8 L. In particular, the values B 5  to B 1  are written to output register  614  of  FIG. 6 . 
     The next signal  708  shows the assertion of a write signal in respect of bit B 0 , which occurs between the rising edge timing signal P 8 L and the rising edge of the next pulse of timing signal P 1 L. 
     The last signal  709  of  FIG. 7  shows the clock signal of the comparator for timing decisions, which controls when the output of the comparator is stored as Di and  Di  values in a corresponding latch in the digital portions  601 A to  608 A, prior to being output as a bit value to the output register  614  or  616 . As illustrated, the decision corresponding to bit B 5  occurs just before the rising edge of timing pulse P 3 L, the decision corresponding to bit B 4  occurs just before the rising edge of timing pulse P 4 L, the decision corresponding to bit B 3  occurs just before the rising edge of timing pulse PSL, the decision corresponding to bit B 2  occurs just before the rising edge of timing pulse P 6 L, the decision corresponding to bit B 1  occurs just before the rising edge of timing pulse P 7 L, and finally the decision corresponding to bit B 0  occurs just before the rising edge of timing pulse P 8 L. Then, during the next high pulses of timing signal P 1 L, an offset pulse is asserted for offset calibration. 
     While each of the converters  601  to  608  of the conversion unit  600  of  FIG. 6  respects the same timing as shown in  FIG. 7 , the timing signals P 1 L to P 8 L received by each of the converters will be different, resulting in an out of phase, cyclic operation. In particular, as illustrated in  FIG. 6 , the signal forming P 7 L for converter  601  forms signal P 8 L for converter  602 , and forms signal P 1 L for converter  603  etc. . . . and finally forms signal P 6 L for converter  608 . Likewise for the other timing signals. 
       FIG. 8A  illustrates a latch circuit  800  for storing a decision Di and  Di  based on a signal OP equal to the output of comparator  101  received on an input line  801 , and a signal ON, equal, except during reset, to the inverse of signal OP, and received on an input line  802 . The values Di and  Di  are then used for the control of corresponding switches, in the same way as shown in  FIG. 5 . 
     The circuit comprises transistors  804  and  806  receiving the signals OP and ON respectively on one of their main current terminals, the other of their main current terminals being coupled to storage nodes  808 ,  810  respectively of a latch. The state of the voltages at nodes  808  and  810  are maintained by a pair of inverters  811 ,  812 , coupled head to tail between the nodes  808  and  810 . A similar circuit  800  is provided for each value Di, with i in this example equal from 5 to 1, and an enable signal provided to a gate node of the transistors  804 ,  806  corresponds to the timing signal P( 2 + i )L. Thus, when the signal P( 2 + i )L is high for a given latch, the latch stores the corresponding output of the comparator to the nodes  808  and  810 . 
     Transistors  814  and  816  are coupled between ground and the nodes  808 ,  810  respectively, allowing the voltage at these nodes to be reset by a reset signal Di&amp;Dib_Reset, provided on a line  818  to the gate nodes of transistors  814  and  816 . This reset signal is also provided to a reset input R of the inverters  811 ,  812 . This reset signal is provided by reset signal generation circuitry  820  comprising nodes  822  and  824  storing complementary voltages maintained by a pair of inverters coupled head to tail. The values at nodes  822  and  824  are programmed to activate the reset by coupling node  824  to ground via a transistor  826 , which is activated by the signal P 8 L. The reset is released by coupling node  822  to ground via a transistor  828  controlled at its gate node by the timing signal P( 2 + i )L. As illustrated, the value Di stored at node  808  then provides the output bit B( 6 − i ). 
     A latch for storing and outputting bit B 0  is implemented in the same way as latch circuit  800 , except that transistor  826  will be activated by the timing signal P 1 L. 
       FIG. 8B  illustrates the latch circuit  800  of  FIG. 8A  according to an alternative embodiment, and in  FIG. 8B  features in common with those of  FIG. 8A  have been labeled with like reference numerals and will not be described again in detail. 
     In  FIG. 8B , the transistors  814  and  816  have been removed, as well as the reset inputs of inverters  811  and  812 . Instead, buffers  830  and  832  are provided, respectively coupled between the nodes  808 ,  810  and respective output lines  834 ,  836 . Lines  834 ,  836  provide the data signals Di and  Di  respectively when the buffers  830 ,  832  are enabled. Each of the buffers  830 ,  832  comprises an enable input coupled to line  818 , and is enabled by a low signal. The signal on line  818  is thus labeled in  FIG. 8B  as an inverse enable signal  ENABLE . 
     Operation of the latch circuit of  FIG. 8B  is very similar to that of  FIG. 8A , and has the advantage that the data signal Di_Buf stored at node  808  is isolated from the output lines  834  and  836  by the buffers  830 ,  832 . Thus the data signal Di_Buf can be kept at node  808  irrespective of whether output signals Di and  Di  are enabled, and thus the corresponding data bit B( 6 − i ) can be provided on an output bus after the pulse P 8 L has disabled the output of buffers  830 ,  832 . Furthermore, the output bit B( 6 − i ) from each latch  800 , including the bit B 0 , can be provided on the output bus at a same time. 
       FIG. 9A  illustrates an example of a circuit  900  present in the timing signal generation block  612  of  FIG. 6 , which is repeated 8 times for generating the signals PjL, for j equal to 1 to 8, based on the signal Pj−1. The circuit  900  comprises a D-type latch  902 , which receives at a data input the signal Pj−1 on an input line  904 , and on a clock input the clock signal CLK after inversion by an inverter  906 . The output Pj of the latch and the clock signal CLK provide the inputs to a 2-input NAND gate  908 . The output of NAND gate  908  is inverted by an inverter  910  to provide the signal PjL. 
       FIG. 9B  shows the timing of the signals Pj−1, CLK, Pj and PjL. As illustrated, the signal Pj−1 is sampled on the falling edge of CLK, and when this clock signal goes low, the signal Pj goes high for one period of clock CLK. This in turn causes the output of the NAND gate  908  to go low for the duration of the high clock pulse, and thus the signal PjL has a pulse width equal to the pulse width of the clock signal CLK. 
       FIG. 10  illustrates circuitry  1000  for generating the signals CMMLi of  FIG. 7 , which control when the signal Vc is coupled to the capacitor Ci. As shown, nodes  1002  and  1004  store complementary voltages maintained by inverters  1006  and  1008  coupled head to tail. The signal at node  1004  provides the signal CMMLi. Transistors  1010  and  1012  are coupled between node  1004  and ground, and bring the signal CMMLi low when the timing signal P 1 L at the gate of transistor  1010  is high, or when the timing signal P( 2 + i )L at the gate of transistor  1012  is high. Transistors  1014  and  1016  are coupled between node  1002  and ground, and bring the voltage at node  1004  high when P 2 L or P 8 L is low. In particular, transistors  1014  and  1016  respectively receive at their gate nodes the timing signals P 2 L and P 8 L. 
       FIG. 11  illustrates an example of a circuit  1100  for generating the write signal  707  of  FIG. 7 . Nodes  1102  and  1104  store complementary voltages maintained by inventers  1106  and  1108  coupled head to tail. The voltage at node  1104  provides the write signal, which is brought high at the start of the timing pulse P 7 L, and is brought low again at the start of the timing pulse P 8 L. For this, a transistor  1110  is coupled between node  1102  and ground, and receives at its gate node the signal P 7 L, and a transistor  1112  is coupled between node  1104  and ground, and receives the signal P 8 L at its gate node. 
       FIG. 12  illustrates an electronic device  1200  comprising a SAR ADC  1202 , which for example corresponds to the analog to digital conversion unit  600  of  FIG. 6 . The SAR ADC  1202  receives an input signal on an input line  1204 , this signal for example being a differential input signal. It also receives a clock signal on an input line  1206 . Unit  1202  converts the analog signal, after sampling, into a 6-bit digital value, although a different number of bits may be generated. The output binary signal is provided on an output line  1208 , which is provided to a block  1210 , which is, for example, a processor and/or a memory device. An output signal is generated from block  1210  on an output line  1212 . 
     The device  1200  is, for example, a mobile communications device, PDA (Personal Digital Assistant), digital media player, lap top computer or other digital electronic devices. 
     An advantage of the embodiments described herein is that, by providing a voltage level Vc in addition to the voltage levels Vtop and Vbot selectable by the switches of the capacitor arrays, this voltage may be used as a neutral start point for each decision, such that the decision as to whether to couple each capacitor to the voltage level Vtop or Vbot can be made for each side of the differential converter prior to changing the connection. Due to the differential arrangement of the device, this advantageously leads to a lower quantity of charge being drawn from the voltage levels Vtop and Vbot, as during reset, the charge supplied to the capacitors will be substantially the same. 
     A further advantage of these embodiments is that, due to the differential nature of the converter, Vc is present on both inputs of the comparator, and thus cancels. This means that Vc is not limited to being at a value exactly halfway between the voltage levels Vtop and Vbot, although performance is improved when Vc is approximately at the mid-point. Furthermore, Vc need not be constant, but may fluctuate. 
     Furthermore, because the decision regarding whether to connect each capacitor to voltage Vtop or Vbot is made prior to switching that capacitor, a final capacitor corresponding to the least significant bit of the output digital value can be omitted, leading to one less pair of capacitors in the converter. Furthermore, the smallest capacitor can be larger compared to the smallest capacitor in the embodiment of  FIG. 1 , and/or the total capacitance can be reduced. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. 
     For example, while the embodiments have been described in relation to a 4 or 6-bit converter, the same principles can equally be applied to any n-bit converter, where n is between 2 and 32. 
     Furthermore, while in the described embodiments the capacitors of the capacitor arrays have a binary weighting, alternatively they could have different weightings, for example if a non-linear quantization is to be applied. 
     Furthermore, while in the embodiment of  FIG. 3  the differential input voltage has been represented as being applied by switches  301  to  304  and  301 ′ to  304 ′, it will be apparent to those skilled in the art that alternatively the supply voltage Vs could be applied via these switches, and the differential input voltage could be applied via switches  110  and  110 ′, for example with their sign reversed. 
     Furthermore, while the transistors throughout the figures are shown to be MOS transistors, it will be apparent to those skilled in the art that other types of transistors could be used. 
     The variations features described in relation to the various embodiments could be combined in alternative embodiments in any combination. 
     Such alterations, modifications and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The invention is limited only as defined in the following claims and the equivalent thereto.