Abstract:
A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a micro-sized gate of a transistor. 
         [0003]    2. Description of the Related Art 
         [0004]    The gates of transistors of semiconductor devices are gradually becoming smaller as semiconductor devices in general become more highly integrated. As a result, the significance of the affect of the electric field of a junction region on electric potential in a channel region of a transistor may increase. For example, the scaling down of a transistor may give rise to short channel effects such as the lowering of the threshold voltage of the transistor and/or punch through. The performance/quality of a semiconductor device may be undermined by such short channel effects. 
       SUMMARY OF THE INVENTION 
       [0005]    An object of the present invention is to provide a method of fabricating a micro-sized gate of a semiconductor device. 
         [0006]    Another object of the present invention is to provide a method of fabricating a semiconductor device which is improved with respect to short channel effects. 
         [0007]    According to one aspect of the present invention, there is provided a method of fabricating a semiconductor device which includes forming a gate on a substrate, and forming asymmetric junction regions in the substrate on opposite sides of the gate. To this end, a spacer is formed over the upper surface and sidewalls of the gate, and the spacer is formed so as to be asymmetric with respect to a plane that extends perpendicular to the substrate intermediate opposite sidewalls of the gate. 
         [0008]    The spacer is formed of a first spacer element, and a second spacer element. The first spacer element is formed over the upper surface and one sidewall of the gate, and the second spacer element is formed over the other sidewall of the gate. Also, the first and second spacer elements are formed so as to have different thicknesses in a widthwise direction of the gate as measured at the bottom of the gate adjacent the substrate. 
         [0009]    The first junction region is formed by doping the substrate before the first spacer element is formed to thereby form a first impurity extension region in the substrate, and by doping the substrate after the first spacer element has been formed to thereby form a first impurity region in the substrate laterally adjacent to the first spacer element. In this respect, the substrate is preferably doped at a higher concentration when forming the first impurity region than when forming the first impurity extension region. Similarly, the second junction region is formed by doping the substrate with an impurity before the second spacer element is formed to thereby form a second impurity extension region in the substrate, and by doping the substrate after the second spacer element has been formed to thereby form a second impurity region in the substrate laterally adjacent to the second spacer element. The substrate is preferably doped at a higher concentration when forming the second impurity region than when forming the second impurity extension region. Thus, the first impurity extension region and the second impurity extension region have respective lengths corresponding to the thicknesses of the first and second spacer elements, respectively. That is the second impurity extension region has a different length than the first impurity extension region. 
         [0010]    According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device which includes forming a pair of gates on a substrate, and forming asymmetric junction regions in the substrate on opposite sides of each gate. The asymmetric junction regions include an inner junction region located between the pair of gates, and outer junction regions laterally outwardly of the pair of gates. Each of the outer junction regions is asymmetric to the inner junction region with respect to a plane that extends perpendicular to the substrate intermediate the sidewalls of the gate which lies between the outer and inner junction regions. The forming of the inner and outer junction regions is facilitated by forming outer spacers on outer sidewalls of the gates, respectively, and forming inner spacers on inner sidewalls of the gates, respectively, such that the inner and outer spacers formed on each gate are asymmetrical to one another with respect to a plane that extends perpendicular to the substrate intermediate the sidewalls of the gate. 
         [0011]    The inner junction region may be formed by forming an inner source/drain region in the substrate between the pair of gates by doping the substrate with an impurity, and forming inner source/drain extension regions in the substrate below the inner spacers and adjacent opposite ends of the inner source/drain region, respectively. Preferably, the inner source/drain extension regions are formed by doping the substrate with an impurity at a concentration lower than that used to form the inner source/drain region. Similarly, the outer junction regions are formed by forming outer source/drain regions in the substrate laterally outwardly of the pair of gates by doping the substrate with an impurity, and forming outer source/drain extension regions in the substrate below the outer spacers and adjacent ends of the outer source/drain regions, respectively. Preferably, the outer source/drain extension regions are formed by doping the substrate with an impurity at a concentration lower than that used to form the outer source/drain regions. 
         [0012]    Also, the inner and outer spacers are formed on each of the gates so as to have different thicknesses in a widthwise direction of the gate as measured at the bottom of the gate adjacent the substrate. Therefore, the inner source/drain extension regions have lengths corresponding to the thicknesses of the inner spacers, respectively, and the outer source/drain extension regions have lengths corresponding to the thicknesses of the outer spacers, respectively. Accordingly, the length of each of the inner source/drain extension regions is different from the length of the outer source/drain extension region disposed across the gate therefrom. Preferably, the length of each of the outer source/drain extension regions is greater than the length of the inner source/drain extension region disposed across the gate therefrom. 
         [0013]    According to yet another aspect of the present invention, there is provided a method of fabricating a semiconductor device which includes forming micro-sized gates through a step of reducing the size of a gate mask on a conductive pattern. The resulting gate mask pattern extends over an intermediate part of the conductive pattern and exposes the upper surface of the conductive pattern at opposite sides of the conductive pattern. Then outer spacers are formed over a respective sidewall and an exposed portion of the upper surface of the conductive pattern as well as over a respective sidewall of the gate mask pattern. Subsequently, the gate mask pattern is removed to expose the intermediate portion of the conductive pattern. Also, the exposed portion of the conductive pattern is etched away to thereby form a pair of gates from the conductive pattern. The method also includes doping the substrate at appropriate times to form an inner junction region in the substrate between the pair of gates, and outer junction regions located in the substrate on opposite sides of a region of the substrate over which the conductive pattern is formed. Thus, in the final product the outer junction regions are located in the substrate laterally outwardly of the pair of gates. 
         [0014]    Preferably, the gate mask pattern is formed by a pull-back process. In this process, a conductive layer is formed on the substrate, and a gate mask is formed on the conductive layer. Then, the conductive layer is etched using the gate mask as an etching mask to form the conductive pattern. Subsequently, the gate mask is “pulled-back” from the opposite sides of the conductive pattern by etching the gate mask. 
         [0015]    The outer spacers may be formed by depositing on the substrate insulating material having an etch selectivity with respect to the material of the gate mask, and etching the resulting layer of insulating material. 
         [0016]    The method may further include forming a first insulation layer on the substrate after the outer junction regions have been formed. The first insulation layer is formed such that the gate mask pattern is left exposed. A second insulation layer may be formed on the substrate between the inner spacers after the inner junction region has been formed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    These and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments thereof made with reference to the accompanying drawings. In the drawings: 
           [0018]      FIGS. 1 through 13  are each a cross-sectional view of a substrate and together illustrate a method of fabricating a semiconductor device according to the present invention. 
       
    
    
       [0019]    Note, like reference numerals are used to designate like elements throughout the drawings. 
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0020]    A method of forming a gate of a semiconductor device according to the present invention will now be described with reference to the figures. Referring first to  FIG. 1 , an oxide layer  103  is formed on a substrate  101 . For example, the substrate  101  is a semiconductor substrate such as a silicon wafer, and the oxide layer  103  is a silicon oxide layer. Also, an active region is defined in the substrate  101  by a device isolation layer (not shown). 
         [0021]    Next, a conductive layer  105  is formed on the oxide layer  103 , and a gate mask  107  is formed on the conductive layer  105 . The conductive layer  105  may be formed by depositing polysilicon on the oxide layer  103 , and the gate mask  107  may be formed by depositing silicon nitride on the conductive layer and patterning the resulting layer of silicon nitride. 
         [0022]    Referring to  FIG. 2 , the conductive layer  105  and the oxide layer  103  may be simultaneously etched, by a dry etch process that employs the gate mask  107  as an etch mask, to form a conductive layer pattern  105   a  and an oxide layer pattern  103   a . Alternatively, the conductive layer  105  is selectively etched by a first dry etch process that employs the gate mask  107  as an etch mask to form the conductive layer pattern  105   a . Subsequently, the oxide layer  103  is selectively etched by a second dry etch process that has a process recipe different from that of the first dry etch process. The second dry etch process employs the gate mask  107  and the conductive layer pattern  105   a  as an etch mask. Consequently, the oxide layer pattern  103   a  is formed below the conductive layer pattern  105   a.    
         [0023]    Referring to  FIG. 3 , a pair of outer source/drain extension regions  109   a  is formed in the substrate  101  adjacent to the sides of the conductive layer pattern  105   a  by doping the substrate  101  with an impurity. 
         [0024]    Referring to  FIG. 4 , a pullback process is performed on the gate mask  107  to form a reduced gate mask pattern  107   a . Part of the upper surface of the conductive layer pattern  105   a  is exposed by the reduced gate mask pattern  107   a . The pullback process may be a wet etch process in which the gate mask  107  is isotropically etched (blanket-etched without using an etch mask). For example, the gate mask  107  may be wet etched using H 3 PO 4  when the gate mask  107  is of silicon nitride. Alternatively, the pullback process may be a dry etch process in which the gate mask  107  is etched using plasma. 
         [0025]    Referring to  FIG. 5 , an outer spacer  111  is formed by depositing and selectively etching an insulating material (e.g., silicon oxide or silicon nitride) on the substrate  101 . The outer spacer  111  covers the part of the upper surface and both sidewalls of the conductive layer pattern  105   a  and also both sidewalls of the gate mask pattern  107   a . Preferably, the outer spacer  111  is formed of a material having an etch selectivity with respect to that of the gate mask pattern  107   a . For example, the outer spacer  111  may be formed of silicon oxide when the gate mask pattern  107   a  is formed of silicon nitride. 
         [0026]    Referring to  FIG. 6 , the substrate  101  (adjacent to the sides of the outer spacer  111 ) is doped with an impurity to form a pair of outer source/drain regions  109   b . The impurity may be the same as that used for forming the outer source/drain extension region  109   a . The outer spacer  111  may be used as a mask during this doping process. Therefore, the outer source/drain regions  109   b  may be formed in only upper portions of the substrate  101  not covered by the outer spacer  111 . Accordingly, the outer source/drain extension regions  109   a  remain only in upper portions of the substrate below the outer spacer  111 . Also, the outer source/drain regions  109   b  may have a greater depth and a higher concentration of impurities than the outer source/drain extension region  109   a . Therefore, a pair of outer junction regions  109  is formed in the substrate  101  at a level below the conductive layer pattern  105   a . The outer junction regions  109  may constitute lightly doped drain (LDD) structures each including an outer extension region  109   a  having a low concentration of impurities and an outer region  109   b  having a high concentration of impurities. 
         [0027]    Referring to  FIG. 7 , an insulation layer  113  is formed on the substrate  101 . The insulation layer  113  may be formed by depositing silicon oxide on the substrate  101  until a layer of the silicon oxide covers the gate mask pattern  107   a , and planarizing the resulting silicon oxide layer. The planarization process may be terminated once the top of the gate mask pattern  107   a  is exposed. As a result, the insulation layer  113  is formed on the outer sides of the outer spacer  111 . 
         [0028]    Referring to  FIG. 8 , the gate mask pattern  107   a  is etched to form a first opening that exposes the conductive layer pattern  105   a . The bottom of the first opening  115  is delimited by the upper surface of the conductive layer pattern  105   a  and the sides of the first opening  115  are delimited by the inner sides of the outer spacer  111 . 
         [0029]    Referring to  FIG. 9 , a second opening  117  is formed to expose the substrate  101  between the outer spacers  111  by selectively anisotropically etching the conductive layer pattern  105   a  and the oxide layer pattern  103   a . As a result, a pair of gates  105   b  and a pair of gate oxide layers  103   b  are formed. The outer spacer  111  covers each gate  105   b  except at the side of the gate  105   b  exposed by the second opening  117 . That is, outer spacer  111  covers the outer side and top of each gate  105   b.    
         [0030]    In this part of the process, the pair of gates  105   b  and the pair of gate oxide layers  103   b  may be simultaneously formed by selectively etching the conductive layer pattern  105   a  and the oxide layer pattern  103   a  at the same time. Alternatively, the pair of gates  105   b  may be formed first by selectively etching the conductive layer pattern  105   a  using a first etch process. Then the pair of gate oxide layers  103   b  is formed by etching away the oxide layer pattern  103   a  between the gates  105   b  using a second etch process having an etch recipe different from that of the first etch process used to form the gates  105   b.    
         [0031]    Referring to  FIG. 10 , an inner source/drain extension region  119   a  is formed between the pair of gates  105   b  by doping the substrate  101 , at an upper portion thereof exposed by the second opening  117 , with an impurity. The impurity used to form the inner source/drain extension region  119   a  may be the same as the impurity used to form the outer source/drain extension regions  109   a . Also, the inner source/drain extension region  119   a  may have the same concentration of impurities as the outer source/drain extension regions  109   a.    
         [0032]    Referring to  FIG. 11 , an inner spacer  121  is formed over the inner side of each gate  105   b  exposed by the second opening  117 . The inner spacer  121  may be formed of the same material (e.g., silicon oxide or silicon nitride) as the outer spacer  111  and by generally the same method. Also, the inner spacer  121  is thinner than the outer spacer  111 . Accordingly, the inner spacer  121  and the outer spacer  111  are asymmetrical with respect to the gate  105   b.    
         [0033]    Referring to  FIG. 12 , an inner source/drain region  119   b  is formed by doping the substrate, at an upper portion of the substrate which remains exposed by the second opening  117 , with an impurity. This impurity may be the same as the impurity used for forming the inner source/drain extension regions  119   a . Also, the concentration of the impurity in the inner source/drain region  119   b  may be similar to that of the outer source/drain region  109   b , and the inner source/drain region  119   b  may be deeper and have a greater concentration of impurities than the inner source/drain extension region  119   a . Therefore, an inner junction region  119  is formed in the substrate  101  between the pair of gates  105   b . The inner junction region  119  has an LDD structure in which the inner source/drain extension regions  119   a , having a relatively low concentration of impurities, are formed at both sides of the inner source/drain region  119   b  having a higher concentration of impurities. Therefore, the inner junction region  119  can serve as a common source. 
         [0034]    The inner spacer  121  is used as a mask during this part of the process, i.e., while the upper portion of the substrate exposed by the opening  107  is being doped. Therefore, the inner source/drain region  119   b  is limited to the upper portion of the substrate  101  that spans the gates  105   b  and is not covered by the inner spacer  121 . Likewise, the inner source/drain extension region  119   a  remains only at upper portions of the substrate located below the inner spacer  121 . As mentioned above with reference to  FIG. 11 , the inner spacer  121  and the outer spacer  111  are asymmetrically formed with respect to the gates  105   b . Therefore, the inner source/drain extension region  119   a  is shorter than the outer source/drain extension region  109   a . Accordingly, the inner junction region  119  and the outer junction region  109  are asymmetric with respect to each gate  105   b  with which they are operatively associated. 
         [0035]    Referring to  FIG. 13 , an insulation layer  123  is formed to fill the second opening  117 . In this respect, the insulation layer  123  may be formed by depositing silicon oxide on the substrate and planarizing the resulting layer of silicon oxide, similar to the forming of the insulation layer  113 . Upper portions of the inner and outer spacers  111  and  121  may be removed during the planarization process of forming the insulation layer  123 . 
         [0036]    According to the present invention as described above, a pullback process is used for forming the gate mask  107 . Thus, a semiconductor device  100  having gates  105   b  which have a width of less than 20 nm may be realized. That is, the present invention facilitates the forming of stable and uniform transistor array having micro-sized gates. 
         [0037]    Furthermore, the junction regions  109  and  119  of the semiconductor device are formed so as to be asymmetrical with respect to the gates  105   b . In particular, the outer source/drain extension region  109   a  is longer than the inner source/drain extension region  119   a . Thus, the semiconductor device can be improved with respect to short channel effects. 
         [0038]    Finally, the junction regions  109  and  119  may have different impurity concentrations. For example, the outer junction region  109  may have a lower concentration of impurities than the inner junction region  119 . Therefore, the present invention can reduce the likelihood of punch through. 
         [0039]    Therefore, the present invention is particularly advantageous for use in the fabricating of a finFET, and transistors having a multi-channel, an ultra thin body (UTB), a nano-wire channel, and a multi-wire channel. Furthermore, the present invention may be applied to the fabricating of DRAM, SRAM, Logic, and non-volatile memory devices. 
         [0040]    And, although the present invention has been described in connection with the preferred embodiments thereof, it is to be understood that the scope of the present invention is not so limited. On the contrary, various modifications of and changes to the preferred embodiments will be apparent to those of ordinary skill in the art. Thus, changes to and modifications of the preferred embodiments may fall within the true spirit and scope of the invention as defined by the appended claims.