Abstract:
A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.

Description:
TECHNICAL FIELD OF THE INVENTION 
       [0001]    The invention relates to optical receivers, and, more particularly, to clock-and-data recovery (CDR) circuitry of an optical receiver that performs automatic data rate negotiation. 
       BACKGROUND OF THE INVENTION 
       [0002]    A typical optical receiver includes at least one photodiode that detects an optical data signal and converts it into an electrical current signal, at least one transimpedance amplifier (TIA) that converts the electrical current signal into an electrical voltage signal and CDR circuitry that processes the electrical voltage signal to recover the clock and then uses the recovered clock to sample the data in order to recover the data. Typical CDR circuitry includes a phase-locked loop that phase-aligns a local reference clock with transitions in the incoming data signal and then uses the phase-aligned reference clock to sample the incoming data signal. 
         [0003]    In the optical communications industry, efforts are continuously being made to increase data rates. As data rates are increased, standards committees in the optical communications industry set standards that govern the mechanical and electrical designs on optical communications modules. In addition to formal standards, multi-source agreements (MSAs) are entered into among multiple manufacturers for providing de facto standards for making products that are compatible across vendors. One such committee is the Small Form Factor (SFF) Committee. 
         [0004]    Small form factor pluggable (SFP) optical transceiver modules have a form factor and electrical interface that are specified by an MSA under the auspices of the SFF Committee. An MSA known as SFF 8419 is a 32 Gigahertz (GHz) standard that requires that newly manufactured SFP optical transceiver modules be backwards compatible with modules that operate at 16 GHz and 8 GHz data rates. Because of the backwards compatibility requirement, the newer modules are required by the MSA to meet the same form factor and electrical interface standards specified for the earlier modules. The specified electrical interface provides a single rate select bit communicated over a single input/output (I/O) pin to indicate whether the incoming data signal is a 32 GHz signal or is other than a 32 GHz signal. If the rate select bit is high, this indicates that the incoming data signal is a 32 GHz signal. If the rate select bit is low, this indicates that the incoming data signal is other than a 32 GHz signal. Thus, when the rate select bit is low, it is left up to the module to determine whether the incoming data signal is an 8 GHz signal or a 16 GHz signal and to frequency and phase lock onto the incoming data signal within a specified time frame. The process of determining the data rate of the incoming data signal and of frequency and phase locking onto the incoming data signal within a specified time frame is referred to hereinafter as automatic rate negotiation. A need exists for a CDR that is capable of performing automatic rate negotiation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  illustrates a block diagram of CDR circuitry in accordance with an illustrative embodiment for performing automatic rate negotiation. 
           [0006]      FIG. 2  is a state diagram that represents the algorithm performed by the state machine shown in  FIG. 1  in accordance with an embodiment. 
           [0007]      FIG. 3  is a flow diagram representing processes performed by the state machine shown in  FIG. 1  when the state machine is in the monitor state shown in  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    In accordance with illustrative embodiments, CDR circuitry is provided that performs automatic rate negotiation. An illustrative embodiment of a CDR that performs automatic rate negotiation to meet the requirements of MSA SFF 8419 is provided herein. It will be understood by those skilled in the art, however, that the invention is not limited to performing automatic rate negotiation in accordance with this MSA for the particular data rates referred to therein and that the principles and concepts described herein are applicable to performing automatic rate negotiation for any data rates. A few illustrative embodiments of the offset measurement and cancellation circuitry and method will now be described with reference to the  FIGS. 1-3 , in which like reference numerals represent like elements, features or components. 
         [0009]      FIG. 1  illustrates a block diagram of CDR circuitry  100  in accordance with an illustrative embodiment for performing automatic rate negotiation. In accordance with this embodiment, CDR is only performed if the incoming data signal is either a 16 GHz signal or a 32 GHz signal. If the incoming data signal is an 8 GHz signal, CDR is bypassed because it is not necessary to perform CDR for an 8 GHz signal. It should be noted that although the SFF 8419 MSA refers to 32 GHz, 16 GHz and 8 GHz rates, the actual rates are 28 GHz, 14 GHz and 8 or 8.5 GHz. For purposes of discussion, it will be assumed that the rates are 32 GHz, 16 GHz and 8 GHz because the principles and concepts described herein apply regardless of the actual rates. 
         [0010]    The CDR circuitry  100  comprises an equalizer  101 , a phase detector  103 , a loop filter  104 , a voltage controlled oscillator (VCO)  105 , a first clock divider  106 , a second clock divider  107 , a first 2-to-1 multiplexer (MUX)  108 , a second 2-to-1 MUX  109 , and data rate determination and control logic  110 . The phase detector  103 , the loop filter  104  and the VCO  105  together comprise a phase-locked loop (PLL)  115  of the CDR circuitry  100 . In accordance with an embodiment, the data rate determination and control logic  110  is a state machine that receives as input the aforementioned rate select signal and a loss of signal (LOS) indicator. The LOS indicator is output from the equalizer  101 . When the equalizer  101  detects that there is no incoming data signal, it asserts the LOS indicator to inform the data rate determination and control logic  110  that there is no incoming data. 
         [0011]    The rate select signal is typically provided by the host (not shown) and controlled by the user. When the rate select signal is asserted, the data rate determination and control logic  110  determines that the incoming data signal is a 32 GHz signal. The logic 1 input of the MUX  108  receives a 32 GHz clock signal from the VCO  105  and outputs that signal to the phase detector  103  when the rate select signal is a logic 1. The clock divider  106  also receives the 32 GHz clock signal from the VCO  105  and divides it in half to achieve a 16 GHz clock signal, which is applied to the logic 0 input of the MUX  109 . When the rate select signal is a logic 0, the MUX  109  outputs the 16 GHz clock signal to the phase detector  103 . 
         [0012]    When the incoming data signal is either a 16 GHz signal or a 32 GHz signal, the CDR circuitry  100  performs CDR in the manner in which CDR is typically performed to recover the clock and the data. The MUX  108  acts as an output of the CDR circuitry  100  whereas the equalizer  101  acts as an input of the CDR circuitry  100 . When the incoming data signal is an 8 GHz signal, the PLL  115  of the CDR circuitry  100  is bypassed such that CDR is not performed. In the latter case, the CDR mode signal is low and the output of the equalizer  101  becomes the output of the CDR circuitry  100 . When the incoming data signal is either a 16 GHz or 32 GHz signal, the CDR mode signal is high, causing the output of the phase detector  103  to become the output of the MUX  108 . When the rate select signal is low, the data rate determination and control logic  110  determines whether the incoming data signal is an 8 GHz signal or a 16 GHz signal and deasserts or asserts the CDR mode signal, respectively. The manner in which the data rate determination and control logic  110  makes these determinations is described below with reference to  FIGS. 2 and 3 . 
         [0013]    In cases where the rate select signal is low, in order for the data rate determination and control logic  110  to make the determination as to whether the incoming data signal is an 8 GHz signal or a 16 GHz signal, it receives frequency lock information from the VCO  105  and phase lock information from the phase detector  103  via VCO  105 . Based on the received frequency lock and phase lock information, the data rate determination and control logic  110  determines whether the PLL  115  is frequency and phase locked onto a 16 GHz incoming data signal. If it is not, then the data rate determination and control logic  110  determines that the incoming data signal is an 8 GHZ signal and causes the CDR mode signal to be deasserted so that the PLL  115  is bypassed. 
         [0014]      FIG. 2  is a state diagram that represents the algorithm performed by the data rate determination and control logic  110  shown in  FIG. 1 . When the algorithm starts up, the data rate determination and control logic  110  enters a wait_VCO state  201 . In this state, registers (not shown) of the VCO  105  are initialized via the VCO control signals that are sent by the data rate determination and control logic  110  to the VCO  105 , as shown in  FIG. 1 . After the VCO  105  has been initialized, the data rate determination and control logic  110  exits the wait_VCO state  201  and enters a frequency_calibration state  202 . In the frequency_calibration state  202 , the VCO calibrates itself to generate the 32 GHz clock. Once the VCO  105  has been calibrated, the data rate determination and control logic  110  exits the frequency_calibration state  202  and enters a monitor state  203 . In the monitor state  203 , the data rate determination and control logic  110  monitors the VCO  105  and controls the CDR circuitry  100  to cause various tasks to be performed, as will now be described with reference to  FIG. 3 . 
         [0015]      FIG. 3  is a flow diagram representing processes performed by the data rate determination and control logic  110  when it is in the monitor state  203  shown in  FIG. 2 . In the monitor state  203 , a determination is made as to whether the rate select signal is high or low. If the rate select signal is high, the process proceeds to block  302  where the data rate determination and control logic  110  verifies that the VCO  105  remains frequency locked to the incoming data signal. The process then proceeds to block  303  where the data rate determination and control logic  110  asserts the CDR mode signal being provided to the MUX  108 . The process then proceeds to block  304  and CDR is performed on the incoming data signal such that the output of the CDR circuit  100  output from the MUX  108  is the output of the phase detector  103 . 
         [0016]    If at block  301 , the data rate determination and control logic  110  determines that the rate select signal is low, the process proceeds to block  305  and the VCO  105  frequency locks to the incoming data signal. It should be noted that the even though the VCO  105  generates a 32 GHz clock signal, it is capable of frequency locking to an 8 or 16 GHz incoming data signal, but is only capable of phase locking to either a 16 GHz or 32 GHz incoming data signal. When the rate select signal is low, the 16 GHz clock signal output from the clock divider  106  is being provided by the MUX  109  to the phase detector  103 . Thus, the phase detector  103  will be comparing the phase of the incoming data signal with a 16 GHz clock signal when the rate select signal is low. 
         [0017]    Once frequency lock has been verified at block  305 , the process proceeds to block  306  where the data rate determination and control logic  110  determines whether the VCO  105  is phase locked to the incoming data signal. If not, this means that the incoming data signal is an 8 GHz signal rather than a 16 GHz signal, and therefore the process proceeds to block  307  where the data rate determination and control logic  110  deasserts the CDR mode signal provided to the MUX  108 . The process then proceeds to block  308  where CDR mode is bypassed such that the output of the equalizer  101  is output from the MUX  108  as the output of the CDR circuitry  100 . 
         [0018]    If the data rate determination and control logic  110  verifies at block  306  that the VCO  105  was able to phase lock onto the incoming data signal, this means that the incoming data signal is a 16 GHz signal, and therefore CDR needs to be performed. Therefore, the process proceeds to block  304  where CDR is performed such that the output of the phase detector  103  is output from the MUX  108  as the output of the CDR circuitry  100 . The phase detector  103  samples and retimes the incoming data signal to perform CDR such that the output of the MUX  108  is the retimed data signal. 
         [0019]    With reference again to  FIG. 2 , if the data rate determination and control logic  110  is not able to verify the frequency lock at blocks  302  or  305 , the data rate determination and control logic  110  exits the monitor state  203  and re-enters the wait_VCO state  201 . When the data rate determination and control logic  110  re-enters the wait_VCO state  201 , the data rate determination and control logic  110  delivers the VCO control signals to the VCO  105  to cause it to reinitialize itself. The data rate determination and control logic  110  then exits the wait_VCO state  201  and re-enters the frequency_calibration state  202 , where the VCO  105  is recalibrated. The data rate determination and control logic  110  then exits the frequency_calibration state  202  and re-enters the monitor state  203  where it resumes performing the algorithm represented by the flow diagram shown in  FIG. 3 . 
         [0020]    With reference again to  FIG. 1 , when the rate select signal is low, the 32 GHz clock signal generated by the VCO  105  is divided in half by the clock divider  106  to obtain a 16 GHz clock signal. The 16 GHz clock signal is provided to the phase detector  103 . The phase detector  103  generates pulses indicative of the phase differences between the incoming data signal and the 16 GHz clock output from MUX  109 . The loop filter  104  integrates these pulses and the VCO  105  receives the integration result and uses it to adjust the VCO clock in an attempt to phase lock the VCO  105  onto the incoming data signal (block  306  in  FIG. 3 ). If the VCO  105  is unable to phase lock onto the incoming data signal within a predetermined threshold time period, then the data rate determination and control logic  110  determines that the incoming data signal is an 8 GHz signal and deasserts the CDR mode signal so that the output of the equalizer  101  is output from the MUX  108 . In this way, the data rate determination and control logic  110  causes the CDR process to be bypassed when the incoming data signal is an 8 GHz signal. The 16 GHz clock signal generated by the clock divider  106  is further subdivided by clock divider  107  into a lower frequency (e.g., 200 to 400 Megahertz (MHz)) signal for processing by the data rate determination and control logic  110 . Processing a lower frequency signal in the data rate determination and control logic  110  allows less expensive and less complex logic to be used in the data rate determination and control logic  110 . 
         [0021]    It should be noted that in accordance with the illustrative embodiment of the CDR circuitry  100  shown in  FIG. 1 , the CDR circuitry  100  is full-rate CDR circuitry, i.e., the reference clock generated by the VCO  105  is the same as the incoming data signal having the 32 GHz data rate onto which the PLL  115  is intended to frequency and phase lock. Alternatively, the CDR circuitry could employ, for example, a half-rate design, in which case the reference clock of the VCO  105  would be one-half the data rate of the incoming data signal, or 16 GHz. In the latter case, the phase detector would be a half-rate phase detector with a serializer, driven by the VCO reference clock, at the output of the phase detector. Because the manner in which a full-rate or half-rate CDR circuit may be designed is well known to those skilled in the art, only the full-rate CDR implementation is described herein in the interest of brevity. Persons of skill in the art will understand, in view of the description provided herein, the manner in which half-rate CDR circuitry may be designed to perform automatic rate negotiation consistent with the principles and concepts described herein. 
         [0022]    The data rate determination and control logic  110  may be may type of processor capable of being programmed or configured to perform the tasks described above with reference to  FIGS. 1-3 . Suitable processors for this purpose include, for example, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic controller (PLC), and a block of combinational logic. The functions of the data rate determination and control logic  110  may be performed in software or a combination of hardware and software and/or firmware. To the extent that any of those functions are performed in software and/or firmware, the software and/or firmware is stored in a non-transitory computer-readable memory device, such as a solid state memory device, for example. 
         [0023]    It should be noted that although the illustrative embodiments have been described with reference to a few illustrative embodiments for the purpose of demonstrating the principles and concepts of the invention. Persons of skill in the art will understand how the principles and concepts of the invention can be applied to other embodiments not explicitly described herein. It should also be noted that the circuits and method described above with reference to  FIGS. 1-3  are merely examples of suitable circuit configurations and methods that demonstrate the principles and concepts of the invention. As will be understood by those skilled in the art in view of the description being provided herein, many modifications may be made to the embodiments described herein while still achieving the goals of the invention, and all such modifications are within the scope of the invention.