Abstract:
A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Description:
FIELD OF THE INVENTION  
       [0001]    The present invention relates generally to the data processing field, and more particularly, relates to a method and radiation hardened phase frequency detector (PFD) for implementing enhanced radiation immunity performance. 
       DESCRIPTION OF THE RELATED ART  
       [0002]    A need exists for a phase frequency detector capable of avoiding single event upsets and maintaining functionality while running at frequency equal to or higher than GHz ranges. 
         [0003]    CMOS circuits used in space applications are subject to a single event upset (SEU) due to the hit of Alpha particles or neutron induced radiation effects. For example, the free charge produced by impacts from incident radiation could be as high as 1 pC (pico-Coulomb) that can have 2 mA (milli-ampere) amplitude with 1 ns (nano-second) period. 
         [0004]    While a phase frequency detector is running at frequency lower than 200 Mhz, a radiation hit with 1 pC charge may not always cause soft error if the current pulse width of the radiation hit does not fall into the critical timing window of the set and hold times of any of the latches in the PFD. However, fabricated in deep submicron technology, a PFD can run up to or higher than GHz range. In this case, the vulnerable timing window of set-up and hold time of latches defining the PFD are always covered under the 1 ns or longer period of a hit. 
       SUMMARY OF THE INVENTION  
       [0005]    A principal aspect of the present invention is to provide a method and radiation hardened phase frequency detector (PFD) for implementing enhanced radiation immunity performance or radiation hardening. Other important aspects of the present invention are to provide such method and radiation hardened phase frequency detector (PFD) substantially without negative effect and that overcome many of the disadvantages of prior art arrangements. 
         [0006]    In brief, a method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, duplicated internal nodes and duplicated outputs. The duplicated components are arranged so that when there is a single event upset (SEU) hit to one node, an associated duplicated node for the one node supports the functionalities of the PFD to mitigate the attack of the single event upset. 
         [0007]    In accordance with features of the invention, at the top level of the PFD, the duplicated inputs and outputs are generated so that the mitigation can be expanded to a higher level of inputs and outputs, if needed. The radiation hardened phase frequency detector (PFD) enables an operating frequency range of greater than or equal to 1 GHz. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0008]    The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: 
           [0009]      FIG. 1  is a block diagram of an exemplary radiation hardened two input reset set latch, RH_RS_LAT_ND 2  implemented in accordance with a method of the preferred embodiment; 
           [0010]      FIG. 2  is a schematic diagram of an exemplary two input NAND NMOS pull down gate, ND 2 _NMOS of the latch of  FIG. 1  implemented in accordance with a method of the preferred embodiment; 
           [0011]      FIG. 3  is a schematic diagram of an exemplary two input NAND PMOS pull up gate, ND 2 _PMOS of the latch of  FIG. 1  implemented in accordance with a method of the preferred embodiment; 
           [0012]      FIG. 4  is a block diagram of an exemplary radiation hardened three input reset set latch, RH_RS_LAT_ND 3  implemented in accordance with a method of the preferred embodiment; 
           [0013]      FIG. 5  is a schematic diagram of an exemplary three input NAND NMOS pull down gate, ND 3 _NMOS of the latch of  FIG. 4  implemented in accordance with a method of the preferred embodiment; 
           [0014]      FIG. 6  is a schematic diagram of an exemplary three input NAND PMOS pull up gate, ND 3 _PMOS of the latch of  FIG. 4  implemented in accordance with a method of the preferred embodiment; 
           [0015]      FIG. 7  is a block diagram of an exemplary radiation hardened phase frequency detector (PFD) implemented in accordance with a method of the preferred embodiment; and 
           [0016]      FIG. 8  is a schematic diagram of dual NAND logic gate, D_ND 4  each having duplicated inputs and duplicated outputs, of the exemplary radiation hardened phase frequency detector (PFD) of  FIG. 7  implemented in accordance with a method of the preferred embodiment; 
           [0017]      FIG. 9  is a schematic diagram of dual OR logic gate, D_OR 2  each having duplicated inputs and duplicated outputs, of the exemplary radiation hardened phase frequency detector (PFD) of  FIG. 7  implemented in accordance with a method of the preferred embodiment; 
           [0018]      FIG. 10  is a schematic diagram of dual delay line logic gate, D_DLY each having duplicated inputs and duplicated outputs, of the exemplary radiation hardened phase frequency detector (PFD) of  FIG. 7  implemented in accordance with a method of the preferred embodiment; and 
           [0019]      FIG. 11  is a schematic diagram of dual multiplexers logic gate, D_MUX 21  each having duplicated inputs and duplicated outputs, of the exemplary radiation hardened phase frequency detector (PFD) of  FIG. 7  implemented in accordance with a method of the preferred embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]    In accordance with features of the preferred embodiments, a phase frequency detector (PFD) is mitigated to survive the attack of a single event upset (SEU), for example, due to the hit of Alpha particles or neutron induced radiation effects, providing radiation hardened PFDs of the preferred embodiments that function properly. Redundant components of the PFD are used to mitigate the functional blocks. Hence, the basic building blocks including latches, and combinational gates are made of duplicated components, such that when there is a hit to one node, the duplicated node supports the functionalities of the PFD. Additionally, at the top level of the PFD, duplicated inputs and outputs are generated so that the mitigation can be expanded to other higher levels when needed. 
         [0021]    Having reference now to the drawings, in  FIG. 1 , there is shown an exemplary two input latch generally designated by the reference character  100  in accordance with the preferred embodiment. The two input latch  100  is a radiation hardened reset set (RS) latch. The two input latch  100  includes RESETB_ 0 , RESETB_ 1  and SETB_ 0 , SETB_ 0 , which are two pairs of duplicated inputs. The two input latch  100  includes QB_ 0 , Q_ 0 , and QB_ 1 , Q_ 1 , which are two pairs of duplicated outputs. The two input latch  100  includes two pairs of two input NAND NMOS pull down gates, ND 2 _NMOS,  102 ,  104 ; and  106 ,  108  and two pairs of two input NAND PMOS pull up gates, ND 2 _PMOS,  110 ,  112 ; and  114 ,  116 . 
         [0022]    As shown in  FIG. 1 , input RESETB_ 0  is applied to an A 1  input of two input NAND NMOS pull down gate ND 2 _NMOS,  102  and A 0  input of two input NAND PMOS pull up gates, ND 2 _PMOS,  114 . Input RESETB_ 1  is applied to an A 1  input of two input NAND NMOS pull down gate ND 2 _NMOS,  106  and to an A 0  input of two input NAND PMOS pull up gates, ND 2 _PMOS,  110 . Input SETB_ 0  is applied to an A 1  input of two input NAND NMOS pull down gate ND 2 _NMOS,  104  and to an A 1  input of two input NAND PMOS pull up gates, ND 2 _PMOS,  116 . Input SETB_ 1  is applied to an A 1  input of two input NAND NMOS pull down gate ND 2 _NMOS,  108  and to an A 1  input of two input NAND PMOS pull up gates, ND 2 _PMOS,  112 . 
         [0023]    As shown in  FIG. 1 , the A 0  input of two input NAND NMOS pull down gate ND 2 _NMOS,  108  and the A 0  input of two input NAND PMOS pull up gate ND 2 _PMOS,  11   2  and the output of two input NAND NMOS pull down gate ND 2 _NMOS,  102  are connected to the output of two input NAND PMOS pull up gate ND 2 _PMOS,  110  at latch output QB_ 0 . The A 0  input of two input NAND NMOS pull down gate ND 2 _NMOS,  102  and the A 1  input of two input NAND PMOS pull up gate ND 2 _PMOS,  114  and the output of two input NAND NMOS pull down gate ND 2 _NMOS,  104  are connected to the output of two input NAND PMOS pull up gate ND 2 _PMOS,  112  at latch output Q_ 0 . The A 0  input of two input NAND NMOS pull down gate ND 2 _NMOS,  104  and the A 0  input of two input NAND PMOS pull up gate ND 2 _PMOS,  116  and the output of two input NAND NMOS pull down gate ND 2 _NMOS,  106  are connected to the output of two input NAND PMOS pull up gate ND 2 _PMOS,  114  at latch output QB_ 1 . The A 0  input of two input NAND NMOS pull down gate ND 2 _NMOS,  106  and the A 1  input of two input NAND PMOS pull up gate ND 2 _PMOS,  110  and the output of two input NAND NMOS pull down gate ND 2 _NMOS,  108  are connected to the output of two input NAND PMOS pull up gate ND 2 _PMOS,  116  at latch output Q_ 1 . 
         [0024]    Referring now to  FIG. 2 , there is shown an exemplary two input NAND NMOS pull down gate generally designated by the reference character  200  in accordance with the preferred embodiment. The two input NAND NMOS pull down gate  200  advantageously implements the two pairs of two input NAND NMOS pull down gates, ND 2 _NMOS,  102 , 104 ; and  106 , 108  of the RS latch  100  of  FIG. 1 . The two input NAND NMOS pull down gate  200  includes a pair of series connected N-channel field effect transistors (NFETs)  202 ,  204  connected between the output node OUT and ground. 
         [0025]    Input A 0  is applied to the gate of NFET  202  and input A 1  is applied to the gate of NFET  204 . 
         [0026]    Referring now to  FIG. 3 , there is shown an exemplary two input NAND PMOS pull up gate generally designated by the reference character  300  in accordance with the preferred embodiment. The two input NAND PMOS pull up gate  300  advantageously implements the two pairs of two input NAND PMOS pull up gates, ND 2 _PMOS,  110 ,  112 ; and  114 ,  116  of the RS latch  100  of  FIG. 1 . The two input NAND PMOS pull up gate  300  includes a pair of parallel connected P-channel field effect transistors (PFETs)  302 ,  304  connected between a voltage supply rail VDD and the output node OUT. 
         [0027]    Input A 0  is applied to the gate of PFET  302  and input A 1  is applied to the gate of PFET  304 . 
         [0028]    Operation of the radiation hardened RS latch may be understood from the following two cases that are used to describe how the mitigations work. In case  1 , there is a hit to one of the outputs; when all inputs RESETB_ 1 , RESETB_ 0 , SETB_ 1 , SETB_ 0  and the outputs Q_ 0 , Q_ 1  are high and the outputs QB_ 0 , QB_ 1  are low. Consider that there is a hit to the output Q_ 1  node to pull the Q_ 1  node to low with a negative current pulse, QB_ 1  is still low since the inputs of two input NAND PMOS pull up gates, ND 2 _PMOS,  114  A 0 , A 1  stay high, as shown in  FIG. 3 . 
         [0029]    In case  2 , there is a hit to one of the inputs including the same input and output conditions as of case  1  or with all inputs RESETB_ 1 , RESETB_ 0 , SETB_ 1 , SETB_ 0  and the outputs Q_ 0 , Q_ 1  are high and the outputs QB_ 0 , QB_ 1  are low. If a hit is to strike the output of a gate which drives to RESETB_ 0  and to pull it to low, then the transistor PFET  302  of  FIG. 3  of NAND PMOS pull up gates, ND 2 _PMOS,  114  is turned on to oppose or fight with the NFETs  202 ,  204  of  FIG. 2  of two input NAND NMOS pull down gates, ND 2 _NMOS,  106 . Hence, QB_ 1  could drift higher than ground voltage due to the fighting and potentially to fully turn on NFET  202  of  FIG. 2  of two input NAND NMOS pull down gates, ND 2 _NMOS,  104 . However, the PN ratio of ND 2 _PMOS,  114  to ND 2 _NMOS,  106  is designed such that the node voltage of QB_ 1  is kept low enough so that Q_ 0  stays high. 
         [0030]    Hence, the states of the latch outputs will not change when there is a hit to one of the latch inputs or latch outputs. Additionally, there are cases when a hit to pull a node to high from low; a similar examination can be applied to show that the radiation hardened latch  100  is also mitigated by design such that all outputs will not change when there is a hit. 
         [0031]    Referring now to  FIG. 4 , there is shown an exemplary three input radiation hardened latch generally designated by the reference character  400  implemented in accordance with a method of the preferred embodiment. The three input latch  400  includes RESET 1 B_ 0 , RESET 1 B_ 1 ; RESET 2 B_ 0 , RESET 2 B_ 1 ; SET 2 B_ 0 , SET 2 B_ 0  and SET 1 B_ 0 , SET 1 B_ 0 , which are four pairs of duplicated inputs. The three input latch  400  includes QB_ 0 , Q_ 0 , and QB_ 1 , Q_ 1 , which are two pairs of duplicated outputs. The three input latch  400  includes two pairs of three input NAND NMOS pull down gates, ND 3 _NMOS,  402 ,  404 ; and  406 ,  408  and two pairs of three input NAND PMOS pull up gates, ND 3 _PMOS,  410 ,  412 ; and  414 ,  416 . The three input latch  400  is radiation hardened including the same mitigation mechanism as the RS latch  100  with 2-input which means that as long as only one of the inputs or outputs is pulling up from ground or down from VDD by a current pulse, the outputs are maintained or stay put. The three input latch  400  is a radiation hardened reset set (RS) latch. 
         [0032]    Referring now to  FIG. 5 , there is shown an exemplary three input NAND NMOS pull down gate generally designated by the reference character  500  in accordance with the preferred embodiment. The three input NAND NMOS pull down gate  500  advantageously implements the two pairs of three input NAND NMOS pull down gates, ND 3 _NMOS,  402 ,  404 ; and  406 ,  408  of the RS latch  400  of  FIG. 4 . The three input NAND NMOS pull down gate  500  includes three series connected N-channel field effect transistors (NFETs)  502 ,  504 ,  506  connected between the output node OUT and ground. Input A 0  is applied to the gate of NFET  502 ; input A 1  is applied to the gate of NFET  504 ; and input A 2  is applied to the gate of NFET  506 . 
         [0033]    Referring now to  FIG. 6 , there is shown an exemplary three input NAND PMOS pull up gate generally designated by the reference character  600  in accordance with the preferred embodiment. The three input NAND PMOS pull up gate  600  advantageously implements the two pairs of three input NAND PMOS pull up gates, ND 3 _PMOS,  410 ,  412 ; and  414 ,  416  of the RS latch  400  of  FIG. 4 . The three input NAND PMOS pull up gate  600  includes three parallel connected P-channel field effect transistors (PFETs)  602 ,  604 ,  606  connected between a voltage supply rail VDD and the output node OUT. Input A 0  is applied to the gate of PFET  602 ; input A 1  is applied to the gate of PFET  604 ; and input A 2  is applied to the gate of PFET  606 . 
         [0034]    Referring now to  FIG. 7 , there is shown an exemplary radiation hardened phase frequency detector (PFD) generally designated by the reference character  700  implemented in accordance with a method of the preferred embodiment. The radiation hardened phase frequency detector (PFD) includes a pair of 2-input radiation hardened latches  702 ,  704  and a pair of 3-input radiation hardened latches  706 ,  708  together with logic gates including a pair of dual OR gates  710 ,  712 , a dual NAND gates  714 , a dual delay lines  716 , and a dual multiplexer  718 . As shown in  FIG. 7 , the PFD is a radiation hardened phase frequency detector, since each of the latches  702 ,  704 ,  706 ,  708  is radiation hardened having duplicated inputs and outputs. For example, latches  702 ,  704  are implemented with radiation hardened latches  100  of  FIG. 1  and latches  706 ,  706  are implemented with radiation hardened latches  400  of  FIG. 4 . 
         [0035]    As further illustrated in more detail and described with respect to  FIGS. 8 ,  9 ,  10  and  11 , each of the logic gates including dual OR gates  710 ,  712 , dual NAND gate  714 , dual delay lines  716 , and dual multiplexers  718  also must be implemented by duplicated gates. In the illustrated radiation hardened PFD  700 , each of the inputs and outputs are duplicated so that the duplication can be expanded to higher level if required for a particular application. However, only one of the duplicated inputs or outputs can also be implemented by tying the unused input of a pair to high and leave the un-used output of a pair open. 
         [0036]    As shown in the illustrated radiation hardened PFD  700 , REF B_ 0 , REF_B_ 1  inputs to dual OR gate  710  are the reference clocks; FBK_B_ 0 , FBK_B_ 1  inputs to dual OR gate  712  are the feedback clocks; and PGEN_ 0 , PGEN_ 1  are the feedback divider outputs. BINTFBK_ 0 , BINTFBK_ 1  inputs to dual OR gate  712  are low if an external feedback path is used. HIGHFREQ_ 0 , HIGHFREQ_ 1  are high during normal operation bypassing the dual delay lines  716  in the reset path to the radiation hardened 3-input latches  706 ,  708 . Duplicate outputs of the radiation hardened 3-input latches  706 ,  708 , INC_B_ 0 , INC_B_ 1  and DEC_B_ 0 , DEC_B_ 1  are the main outputs. When there is a SEU hit, since the hit is either to pull up or down of one and only one node in the radiation hardened PFD  700 , the outputs of the radiation hardened 3-input latches  706 ,  708  and the outputs of the radiation hardened 2-input latches  702 ,  704  will not be changed so that the outputs of the radiation hardened PFD  700  are maintained or stay put with a SEU hit. 
         [0037]    Referring now to  FIG. 8 , there are shown dual NAND logic gates generally designated by the reference character  800  implemented in accordance with a method of the preferred embodiment. A pair of NAND logic gates  802 ,  804  of the dual NAND logic gates  800  has duplicated inputs and outputs; there is an example of implementing dual NAND gates  714  of the exemplary radiation hardened phase frequency detector (PFD)  700 . 
         [0038]    Inputs A 0 _ 0 , A 1 _ 0 , A 2 _ 0 , A 3 _ 0  are applied to NAND logic gate  802  and duplicated inputs A 0 _ 1 , A 1 _ 1 , A 2 _ 1 , A 3 _ 1  are applied to NAND logic gate  804 . NAND logic gate  802  provides output OUT_ 0  and NAND logic gate  804  provides duplicated output OUT_ 1 . 
         [0039]    Referring now to  FIG. 9 , there are shown dual OR logic gates generally designated by the reference character  900  implemented in accordance with a method of the preferred embodiment. A pair of OR logic gates  902 ,  904  of the dual OR logic gates  900  has duplicated inputs and outputs; there is an example of implementing dual OR gates  710 ,  712  of the exemplary radiation hardened phase frequency detector (PFD)  700 . Inputs A 0 _ 0 , A 1 _ 0  are applied to OR logic gate  902  and duplicated inputs A 0 _ 1 , A 1 _ 1  are applied to OR logic gate  904 . OR logic gate  902  provides output OUT_ 0  and OR logic gate  904  provides duplicated output OUT_ 1 . 
         [0040]    Referring now to  FIG. 10 , there are shown dual delay line logic gates  30  generally designated by the reference character  1000  implemented in accordance with a method of the preferred embodiment. A pair of delay lines  1002 , 1004  has duplicated inputs and outputs, for example, for implementing dual delay lines  716  of the exemplary radiation hardened phase frequency detector (PFD)  700 . Delay line  1002  provides output OUT_ 0  and includes a plurality of series connected NAND gates  1006 ,  1008 , 1010 , 1012  with inputs A 0 _ 0 , VDD applied to the first NAND gate  1006 . Delay line  1004  provides duplicated output OUT_ 1  and includes a plurality of series connected NAND gates  1016 ,  1018 ,  1020 ,  1022  with duplicated inputs A 0 _ 1 , VDD applied to the first NAND gate  1016 . 
         [0041]    Referring now to  FIG. 11 , there are shown dual multiplexers logic gates generally designated by the reference character  1100  implemented in accordance with a method of the preferred embodiment. A pair of multiplexers  1102 ,  1104  has duplicated inputs and outputs, for example, for implementing dual multiplexers  718  of the exemplary radiation hardened phase frequency detector (PFD)  700 . Multiplexers  1102 ,  1104  are 2:1 multiplexers respectively providing duplicated outputs OUT_ 0 , OUT_ 1 . 
         [0042]    Inputs A 0 _ 0 , A 1 _ 0  and SEL_ 0  are applied to multiplexer  1102  and duplicated inputs A 0 _ 1 , A 1 _ 1  and SEL_ 1  are applied to multiplexer  1104 . The outputs OUT_ 0 , OUT_ 1  are represented by: 
         [0000]      OUT — 1 =A 0 —   i *SEL —   i+A 1 —   i *SEL —   i, i= 0, 1 
         [0043]    Simulation test results have confirmed that radiation hardened phase frequency detector (PFD)  700  is solid and robust. The illustrated logic gates as illustrated and described with respect to  FIGS. 8 ,  9 ,  10  and  11  provide fundamental techniques for radiation hardened combinational and sequential logic arrangements. Hence, any of the system logics configured in accordance with the illustrated fundamental techniques for radiation hardened combinational and sequential logic arrangements advantageously are mitigated with these techniques. Additionally, the illustrated latches  100 ,  400 , radiation hardened phase frequency detector (PFD)  700  and logic gates as illustrated and described with respect to  FIGS. 8 ,  9 ,  10  and  11  are independent of CMOS technologies; therefore, can be used for the future generation system logics. 
         [0044]    While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.