Abstract:
A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a voltage generating circuit. More particularly, the present invention relates to a charge pump circuit, which can be applied to semiconductor memory devices. 
         [0003]    2. Description of Related Art 
         [0004]    Source voltages of various voltage levels are usually required in electronic devices, thus, charge pump circuits are usually disposed to generate source voltages of different voltage levels from existing source voltages. For example,  FIG. 1  illustrates the canonical values of biases required by a memory cell of a flash memory at reading, writing (or programming), and erasing. For the reason of power saving, currently the source voltage supplied to an electronic device is generally 3.3V or lower, thus, obviously, the 5 V, 7 V, 9 V, and 10 V in  FIG. 1  are to be pulled up by charge pump circuits. 
         [0005]      FIG. 2  is a block diagram of a conventional charge pump circuit, which is disclosed in U.S. Pat. No. 6,567,309. Referring to  FIG. 2 , the charge pump circuit  200  includes a voltage detector  210 , a clock generator  220 , clock controllers  231 ˜ 234 , and charge pumps  241 ˜ 244 . The voltage detector  210  detects the voltage V P  at node P. Before the voltage V P  reaches a predetermined level (for example, 5V, 7V, 9V, or 10V in  FIG. 1 ), the voltage detector  210  enables the clock generator  220  to generate four phase shift clock signals CK 1 ˜CK 4 , which respectively drive the clock controllers  231 ˜ 234  and further drive the charge pumps  241 ˜ 244  to provide charges to node P, so that the voltage V P  is continued to be pulled up. When the voltage V P  has been pulled up to the predetermined voltage level, the voltage detector  210  disables the clock generator  220 , so that the charge pumps  241 ˜ 244  stop providing charges to node P. 
         [0006]    In the process described above, the voltage V P  is detected by the voltage detector  210  to determine whether to enable or disable all the charge pumps  241 ˜ 244 , that is, all the charge pumps  241 ˜ 244  providing charges to node P or none of the charge pumps  241 ˜ 244  providing charges to node P, and further to accomplish the purpose of adjusting the voltage V P . However, since all the charge pumps  241 ˜ 244  are enabled or disabled, the voltage V P  drifts about the predetermined voltage to a great extent when the voltage V P  is regulated at the predetermined voltage, and moreover, enabling all the charge pumps  241 ˜ 244  will consume power considerably. 
       SUMMARY OF THE INVENTION 
       [0007]    Accordingly, the present invention is directed to provide a charge pump circuit having lower power consumption. According to another aspect of the present invention, a charge pump circuit is provided, wherein when the output voltage of the charge pump circuit is pulled up to and regulated at a predetermined voltage, the output voltage drifts about the predetermined voltage to a smaller extent. 
         [0008]    According to the aforementioned and other objectives, the present invention provides a charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, an output unit, and a feedback unit. Wherein, the controlled CPs are determined whether to provide charges to a node by a plurality of control signals, and the uncontrolled CPs always provide charges to the node. The foregoing control signals are respectively generated by the corresponding control units, and the control units are coupled to the node and respectively output control signals according to the node voltage detected at the node. The higher the node voltage is, the more the controlled CPs controlled by the control signals not providing charges to the node are. Moreover, the output unit outputs an output voltage to an output node according to the node voltage at the node. The feedback unit has an input terminal and an output terminal, wherein the input terminal receives the output voltage and the output terminal sends out the output voltage which has been regulated through negative feedback. 
         [0009]    In the present invention, some of the CPs are constantly enabled and some CPs are enabled according to the requirement, thus, the power consumption of the charge pump circuit is reduced and the extent of the output voltage drifting about the predetermined voltage is also reduced. Moreover, the output voltage of the charge pump circuit is controlled through negative feedback so that the drifting extent of the output voltage about the predetermined voltage is further reduced. 
         [0010]    In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below. 
         [0011]    It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
           [0013]      FIG. 1  illustrates the canonical values of biases required by a memory cell of a flash memory at reading, writing (or programming), and erasing. 
           [0014]      FIG. 2  is a block diagram of a conventional charge pump circuit. 
           [0015]      FIG. 3  is a block diagram of a charge pump circuit according to an embodiment of the present invention. 
           [0016]      FIG. 4  is a simulative diagram of the conventional charge pump circuit and the charge pump circuit  300  in  FIG. 3 . 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0017]      FIG. 3  is a block diagram of a charge pump circuit according to an embodiment of the present invention. Referring to  FIG. 3 , the charge pump circuit  300  includes M charge pumps (CPs)  311 ˜ 31 (M), wherein N CPs are controlled CPs  311 ˜ 31 (N) and (M-N) CPs are uncontrolled CPs  31 (N+1)˜ 31 (M). In addition, the charge pump circuit  300  further includes N control units  321 ˜ 32 (N), an output unit  330  and a feedback unit  340 . Here, it is assumed that the voltage pull-up capability of each of the CPs  311 ˜ 31 (M) is the same, that is, the charges (i.e. the current) provided per unit time by each of the CPs  311 ˜ 31 (M) is the same. 
         [0018]    The foregoing M CPs  311 ˜ 31 (M) are all coupled to node P, wherein the controlled CPs  311 ˜ 31 (N) are respectively determined by the corresponding control signals CT 1 ˜CT N  whether to provide charges to node P, while the uncontrolled CPs  31 (N+1) 31 (M) respectively provide charges to node P constantly. The voltage pull-up capability of the CPs  311 ˜ 31  (M) is higher when the source voltage received by the CPs  311 ˜ 31 (M) is high voltage (for example, 3.6V) than the voltage pull-up capability thereof when the source voltage received is lower voltage (for example, 2.7V), thus, generally, it is designed that the total number of CPs (i.e. the value of M) is determined according to the number of CPs required for pulling up the voltage to. the predetermined voltage level when the source voltage is lower voltage, and then the number of uncontrolled CPs (i.e. the value of (M-N)) is determined according to the number of CPs required for pulling up the voltage to the predetermined voltage level when the source voltage is high voltage. 
         [0019]    The foregoing control units  321 ˜ 32 (N) are coupled to node P for detecting the node voltage V P  at node P and outputting the control signals CT 1 ˜CT N  accordingly. The control signals CT 1 ˜CT N  respectively control the controlled CPs  311 ˜ 31 (N) to determine whether the controlled CPs  311 ˜ 31 (N) provide charges to node P. The control unit can be designed to include a voltage dividing circuit and a comparator, wherein the voltage dividing circuit receives the node voltage V P  and generates a divided voltage, and then the comparator compares the divided voltage V P  and a reference voltage to output a control signal for controlling the corresponding controlled CP. For the convenience of design, the reference voltage in each of the control units is designed to be the same voltage level, such as V REF . Here, each of the control units can have the voltage level it can detect and can generate different control signal corresponding to the node voltage V P  by only adjusting the voltage dividing circuit in each of the control units. In an embodiment, the voltage dividing circuit includes two resistors connected in series. 
         [0020]    For example, the control unit  321  includes a voltage dividing circuit, which is composed of resistors R 11  and R 12 , and a comparator CMP 1 . If the reference voltage V REF  thereof is 1.2V, the control signal CT 1  is “1” (i.e. logic 1) when the divided voltage V 1  is lower than 1.2V, so as to control the controlled CP  311  to provide charges to node P to pull up the node voltage V P . Contrarily, the control signal CT 1  is “0” (i.e. logic 1) when the divided voltage V 1  is higher than 1.2V, so as to control the controlled CP  311  not to provide charges to node P. 
         [0021]    Assuming that the predetermined voltage is 6.5V, because V 1 =V P *R 12 /(R 11 +R 12 ), the resistors R 11  and R 12  can be respectively adjusted to be 50kΩ and 11.3 kΩ, accordingly, the control signal CT 1  is “1” when the node voltage V P  is lower than 6.5V, and the control signal CT 1  is “0” when the node voltage V P  is higher than 1.2V. Similarly, the resistors R 21  and R 22  of the control unit  322  are respectively adjusted to be 50kΩ and 10.3kΩ, so that the control signal CT 1  is “1” when the node voltage V P  is lower than 7V, and the control signal CT 1  is “0” when the node voltage V P  is higher than 7V. The other control units  323 ˜ 32 (N) can be inferred accordingly. 
         [0022]    Accordingly, when the predetermined voltage is 6.5V and the voltage levels of the different control signals the control units  321 ˜ 32 (N) can detect and generate are 6.5V, 7V, 7.5V . . . , the control signals CT 1 ˜CT N  enable all CPs  311 ˜ 31 (N) to accelerate pulling up the node voltage V P  when the node voltage V P  is lower than 6.5V; the control signals CT 1 ˜CT N  only disable the CPs  311  when the node voltage V P  is between 6.5V and 7V; and the control signals CT 1 ˜CT N  only disable the CPs  311  and  312  when the node voltage V P  is between 7V and 7.5V; . . . . Through enabling some of the CPs  311 ˜ 31 (M) permanently and disabling some other of the CPs  311 ˜ 31 (M) accordingly, the extent of the node voltage V P  drifting about the predetermined voltage when the node voltage V P  is regulated at the predetermined voltage is reduced, and moreover, since some of the CPs are enabled according to the requirement, the power consumption of the circuit is reduced. 
         [0023]    Next, to further stabilize the node voltage V P  at the predetermined voltage, in the present invention, the output unit  330  is used along with the feedback unit  340  for negative feedback controlling and the power supply of the feedback unit  340  is V DD , wherein the voltage level of the source voltage V DD  has to be able to completely turn off the pull-up transistor Q P . The output unit  330  includes a pull-up circuit Q P  and a pull-down circuit Q N  Wherein the pull-up circuit Q P  is coupled between the node P and the output node OUT to lead charges at the node P to the output node OUT according to the feedback control voltage V CTRL . The pull-down circuit Q N  is coupled between the output node OUT and the ground node GND to lead charges at the output node OUT to the ground node GND according to the feedback control voltage V CTRL . 
         [0024]    In an embodiment, the pull-up circuit Q P  is a PMOS (P-channel metal oxide semiconductor) pull-up transistor and the pull-down circuit Q N  is an NMOS pull-down transistor. Wherein the first terminal (the source) of the pull-up transistor  P  is coupled to the node P, the second terminal (the drain) of the pull-up transistor Q P  is coupled to the first terminal (the drain) of the pull-down transistor Q N , the second terminal (the source) of the pull-down transistor Q N  is coupled to the ground voltage GND, and the control terminals (the gates) of the pull-up transistor Q P  and the pull-down transistor Q N  are coupled to each other and receive the feedback control voltage V CTRL . 
         [0025]    In an embodiment, the feedback unit  340  includes a voltage dividing circuit, which has resistors R 1  and R 2 , and a comparator CMP. Wherein the voltage dividing circuit having the resistors R 1  and R 2  receives the output voltage V OUT  from the output node OUT and generates a divided voltage V 0 , and then the comparator CMP compares the divided voltage V 0  and a reference voltage V REF  and outputs the feedback control voltage V CTRL . When the output voltage V OUT  received by the input terminal X of the feedback unit  340  is large enough to make the divided voltage V 0  higher than the reference voltage V REF , the feedback control voltage V CTRL  output from the output terminal Y of the feedback unit  340  is “V DD ”. Here, the pull-up transistor Q P  is turned off and the pull-down transistor Q N  is turned on, so as to lead charges at the output node OUT to the ground node GND, and further to pull down the output voltage V OUT . Contrarily, when the output voltage V OUT  received by the input terminal X of the feedback unit  340  is small enough to make the divided voltage V 0  lower than the reference voltage V REF , the feedback control voltage V CTRL  output from the output terminal Y of the feedback unit  340  is “VGND”. Here, the pull-up transistor Q P  is turned on and the pull-down transistor Q N  is turned off, so as to lead charges at the node P to the output node OUT, and further to pull up the output voltage V OU . 
         [0026]      FIG. 4  is a simulative diagram of the conventional charge pump circuit and the charge pump circuit  300  in  FIG. 3 , wherein the present invention is simulated by the charge pump circuit  300  in  FIG. 3  while the conventional charge pump circuit is simulated by the charge pump circuit  300  in  FIG. 3  minus the control units  321 ˜ 32 (N) and the controlled CPs  311 ˜ 31 (N), which is similar to the charge pump circuit  200  in  FIG. 2 . Referring to  FIG. 4 , the abscissa is the source voltage Vcc received by the CPs, the ordinate at left is the total source current Ivcc received by the CPs, and the ordinate at right is the node voltage V P  (V P  is an output voltage to the conventional charge pump circuit; but to the charge pump circuit in the present invention, V P  is a node voltage related to the output voltage) of node P in  FIG. 3 . It can be noted from  FIG. 4  that when the source voltage Vcc is higher than 3V, the charge pump circuit  300  of the present invention in  FIG. 3  has obviously less total source current Ivcc than the conventional charge pump circuit  200  in  FIG. 2 , so that the power consumption thereof is less. 
         [0027]    In overview, according to the present invention, through enabling some CPs permanently and some other CPs according to the requirement, the power consumption of the charge pump circuit and the extent of the output voltage drifting about the predetermined voltage are reduced. Moreover, the output voltage of the charge pump circuit is further controlled through negative feedback, so that the extent of the voltage drifting about the predetermined voltage is further reduced. 
         [0028]    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.