Abstract:
Embodiments of the invention ensure both a realtime nature of a realtime processing and data integrity of a non-realtime processing and perform the both processings efficiently when the realtime processing and the non-realtime processing are performed simultaneously. In one embodiment, a time limit is set not only for a realtime processing command but also for a non-realtime processing command and, if the execution of the non-realtime processing command is not completed within the set time limit, the execution of the non-realtime processing command is interrupted forcibly and a host is informed of a data transfer status at the time of the interruption so that the host can restart the interrupted processing based on the data transfer status of the interrupted processing when a time that can be allocated for the non-realtime processing command occurs again.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims priority from Japanese Patent Application No. JP2004-128592, filed Apr. 23, 2004, the entire disclosure of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to a disk drive and its interfacing technique that ensures a realtime nature of a realtime processing and data integrity of a non-realtime processing and, further, allows both processings to be performed efficiently when the realtime and non-realtime processings are performed simultaneously. 
     In a realtime processing such as an AV data processing, in order to ensure a realtime nature, a disk drive must observe a predetermined time limit accurately to perform data transfer. 
     To this end, in ATA/ATAPI-7 (that is in the course of standardization according to ANSI standards), it is contemplated to introduce a command set that can set a command completion time limit for each stream or each command so as to ensure the realtime nature in the AV data processing that is performed in realtime. 
     Further, when the realtime and non-realtime processings are performed simultaneously, a control is performed so that the realtime processing command is executed with priority and, if it is expected that there is a sufficient time to be allocated for the non-realtime processing command, the non-realtime processing command is executed within such allocatable time. Such method for controlling command execution is disclosed in Japanese Patent Laid-open No. Hei 10-222310. 
     BRIEF SUMMARY OF THE INVENTION 
     In spite of the fact that the AV data processing command in ATA/ATAPI-7 provides a mechanism for terminating the command processing that has been started once if the process cannot be completed within a predetermined time limit so as to ensure the realtime nature of the AV data processing, when the AV data processing that is performed in realtime and the non-realtime processing such as word processing applications are performed simultaneously, there is a problem in that the time limit cannot be set for the non-realtime processing that is performed between two AV data processings and, therefore, the realtime nature of the AV data processing cannot be ensured. 
     Further, in Patent Laid-open No. Hei 10-222310, in order to strictly observe the time limit of the realtime processing, the execution time of the non-realtime processing commands is estimated in advance so that only the non-realtime processing commands that are expected to be completed within a time range that does not impair the realtime nature of the realtime processing are allowed to be executed but, there is a problem in that the non-realtime processing commands that cannot be completed within the expected time period are difficult to be executed. 
     It is a feature of the present invention to ensure both a realtime nature of a realtime processing and data integrity of a non-realtime processing, and perform both processings efficiently when the realtime processing that attaches primary importance to the realtime nature and the non-realtime processing that attaches primary importance to the data integrity are performed simultaneously. 
     In one aspect, a disk drive of the present invention sets a time limit also in a non-realtime processing so that a command can be executed only within a certain time period. However, in the non-realtime processing that attaches primary importance to data integrity, if the execution of the non-realtime processing command is not completed within the set time period, the disk drive interrupts the processing forcibly and notifies a host of a data transfer status at the time of the interruption so that the host can restart the interrupted processing based on the data transfer status of the interrupted processing when a time that can be allocated for the non-realtime processing command occurs again. 
     Thus, according to an aspect of the present invention, there is provided a disk drive comprising: a disk; a timer for managing times in the disk drive; a CPU; a ROM; a RAM; a cache for temporarily storing data read from the disk; and a hard disk controller for controlling data transfer via the cache. A time limit is set not only for a realtime processing command but also for a non-realtime processing command. If the execution of the non-realtime processing command is not completed within the set time limit, the processing is interrupted forcibly and a host is informed of a data transfer status at the time of the interruption so that the host can restart the interrupted processing based on the data transfer status of the interrupted processing when a time that can be allocated for the non-realtime processing command occurs again. Further, when the non-realtime processing is interrupted, even after the host is informed of a result of the interruption of the non-realtime processing, the non-realtime processing, which is interrupted to transfer data to the host, can continue data transfer to the cache till the host publishes the next command and a cache miss of such command is found. 
     Still further, when the time limit is set for the non-realtime processing, the disk drive described above can set the time that the host determines to be allocatable for the non-realtime processing via each command for the non-realtime processing. 
     Still further, the disk drive described above can set a time that can be allocated for the non-realtime processing command by obtaining a command publication interval required for satisfying data transfer requests by the host for each stream of the realtime processing in advance from the host via a host interface, estimating the next command publication times for each stream based on the command publication interval, and calculating a difference between the earliest command publication time among the estimated command publication times for each stream and the time when the non-realtime processing command is received. 
     Still further, the disk drive described above can set a time that can be allocated for the non-realtime processing command, during the realtime processing, by estimating a command publication interval for each stream by keeping a history of the command publication interval required for satisfying data transfer requests by the host for each stream, estimating the next command publication times for each stream based on the estimated command publication interval, and calculating a difference between the earliest command publication time among the estimated command publication times for each stream and the time when the non-realtime processing command is received. Still further, when a realtime processing command is received during an after write operation and there is a cache miss for such command, the disk drive described above can execute the AV data processing command with priority by interrupting an after write operation. 
     According to the present invention, both a realtime nature of a realtime processing and data integrity of a non-realtime processing can be ensured and the both processings can be performed efficiently when the realtime processing that attaches primary importance to the realtime nature and the non-realtime processing that attaches primary importance to the data integrity are performed simultaneously. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an exemplary configuration of a disk drive according to an embodiment of the present invention. 
         FIGS. 2   a  and  2   b  show a diagram showing a control flow for setting a time that the host can allocate for PC data processing according to an embodiment of the present invention. 
         FIG. 3  is a diagram showing an example of a PC data processing command in which a command completion time limit can be set. 
         FIG. 4  is a diagram showing a configuration of registers in which a result of execution of the PC data processing command is set according to an embodiment of the present invention. 
         FIG. 5  is a diagram showing an example of a control flow after a data transfer to the host is interrupted due to timeout. 
         FIG. 6  is a diagram showing a process flow in which the host notifies the disk drive of a command publication interval according to an embodiment of the present invention. 
         FIG. 7  is a diagram showing an example of a command for notifying the disk drive of the command publication interval. 
         FIG. 8  is a diagram showing an exemplary configuration of a table for managing the command publication interval, a latest command publication time, and a next command publication estimated time according to an embodiment of the present invention. 
         FIG. 9  is a diagram showing a process flow for performing the PC data processing by using the time that can be allocated for the PC data processing, which is calculated based on the command publication estimated time according to an embodiment of the present invention. 
         FIG. 10  is a diagram showing an example of a command publication interval management table. 
         FIG. 11  is a diagram showing a control flow when an AV data processing command is received during an after write operation according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this connection, realtime processing is represented by AV data processing and non-realtime processing is represented by PC data processing in the embodiments described below. However, it is to be noted that such representation does not intend to limit the realtime and non-realtime processing to the AV data and PC data processing, respectively. 
       FIG. 1  shows an exemplary configuration of a disk drive to which the present invention is applied. The disk drive according to the present embodiment comprises: a programmable ROM  101  for implementing a control program; a RAM  102  for storing data within a cache and a table for managing data primarily regarding a cache area; a timer  103  for managing and setting times in the disk drive; a control processor  104  that includes the ROM  101 , the RAM  102  and the timer  103  for reading and executing the control program on the ROM; a cache  105  where read request data/write request data is written temporarily; a hard disk controller (hereinafter abbreviated as HDC)  106  for controlling data transfer between the host and the cache  105  as well as between the cache  105  and the disk; a servo control section  107  for controlling to move a head to specified positions when the data is read or written; a voice coil motor (VCM)  108  for moving the head according to the instructions of the servo control section; a motor driver  109  for controlling rotation of a disk  115 ; a selector  110  for selecting only signals of a specified head from magnetic signals read through heads; a signal processing section  111  for converting analog data sent from the selector  110  into digital data or converting digital data sent from the HDC  106  into analog data; a disk formatter  112  for transferring read data sent from the signal processing section  111  to the cache  105  by opening/closing a read gate or transferring write data sent from the cache  105  to the signal processing section  111  by opening/closing a write gate; and an interface controlling section  113  for exchanging commands and data with a host. 
       FIGS. 2   a  and  2   b  show a control flow for setting a time that the host can allocate for PC data processing. 
     The host checks whether any PC data processing command is scheduled to be published (step  201 ). If there is a PC data processing command to be published, the host calculates a time that can be allocated for such PC data processing command (step  202 ). After calculating the time that can be allocated for such command, the host sets such time in a command register of the HDC  106  and publishes the PC data processing command (step  203 ). 
       FIG. 3  shows an example of a PC data processing command in which a command completion time limit can be set. The PC data processing command includes Features register  31 , Sector Count register  32 , Sector Number register  33 , Cylinder Low register  34 , Cylinder High register  35 , Device/Head register  36  and Command register  37 . Though no value is set in the Features register  31  in ATA/ATAPI- 5  specifications, in the interface of the disk drive according to the present embodiment, the host sets a time that can be allocated for the command in the Features register  31 . Then, a sector count of the data to be transferred is set in the Sector Count register  32 . Then, 0 to 7 bits of an LBA address are set in the Sector Number register  33 . Then, 8 to 15 bits of the LBA address are set in the Cylinder Low register  34 . Then, 16 to 23 bits of the LBA address are set in the Cylinder High register  35 . Then, 24 to 27 bits of the LBA address are set in bits  0  to  3  of the Device/Head register  36 . Then, a number of the selected device (a master device is numbered as  0  and a slave device is numbered as  1 ) is set in bit  4  of the Device/Head register  36 . Then, 1 is set in bit  6  of the Device/Head register  36  to indicate the LBA address. Then, 0 is set in bits  5  and  7  of the Device/Head register  36  because these bits are disused. Then, a code of the command is set in the Command register  37 . 
     Returning to  FIG. 2   a , after the command is published, the disk drive of the present embodiment calculates a time that can actually be allocated for the PC data processing command by subtracting a time to be taken for interruption processing of the command from the time set in the Features register  31  of the PC data processing command (step  204 ). Next, the time for executing the PC data processing command is set and the timer  103  is started (step  205 ). The execution of the PC data processing command is started (step  206 ). It is checked whether a timeout has occurred (step  207 ) and, if the timeout has occurred, the execution of the command is interrupted (step  208 ). The processing status at the time of the interruption is set in the registers of the HDC  106  (step  209 ). After that, the HDC  106  reports to the host that the command is terminated (step  210 ). 
     On the other hand, when it is checked whether the timeout has occurred ( 207 ), if the timeout has not occurred, it is checked whether the command is terminated (step  211 ). If the command is not terminated, the timeout is checked again (step  207 ). On the other hand, if the command is terminated, the HDC  106  reports to the host that the command is terminated (step  210 ). 
       FIG. 4  shows a configuration of registers in which a result of execution of the PC data processing command is set. Hereinafter, the data to be set in the registers for setting the execution result when the execution of the command is interrupted forcibly upon expiration of the time set in the PC data processing command will be described in detail. When the interruption processing occurs,  1  is set in bit  0  ( 42 ) of Status register  41 . Then,  1  is set in bit  2  ( 44 ) of Error register  43  to indicate that the process is interrupted due to the expiration of the time. Then, each bit of the LBA indicating the starting address of the nontransferred data when the processing has been interrupted is set in each of Sector Number ( 45 ), Cylinder Low ( 46 ), Cylinder High ( 47 ) and Device/Head ( 48 ) registers. 
     Returning to  FIG. 2   b , when the host receives the report about the termination of the command from the disk drive, the host checks whether bit  0  ( 42 ) of the Status register  41  is  1  and bit  2  ( 44 ) of the Error register ( 43 ) is  1  in the execution result (step  212 ). If bit  0  ( 42 ) of the Status register  41  is  1  and bit  2  ( 44 ) of the Error register ( 43 ) is  1 , the starting address of the nontransferred data when the processing has been interrupted is read (step  213 ). Next, the host publishes an AV data processing command (step  214 ). On the other hand, if the condition that bit  0  ( 42 ) of the Status register  41  is  1  and bit  2  ( 44 ) of the Error register ( 43 ) is  1  is not satisfied (step  212 ), the host executes various error check processes (step  215 ). When a time that can be allocated for the non-realtime processing command occurs again, the host publishes the next non-realtime processing command and sets the starting address for data transfer by using the starting address of the non-transferred data that has been read in step  213 . 
     Then, receiving the AV data processing command from the host, the disk drive executes the AV data processing command (step  216 ). If any error occurs in the AV data processing (step  217 ), the error status is set in the registers for setting the execution result of the HDC  106  (step  218 ). Next, the disk drive reports that the AV data processing command is terminated (step  219 ). On the other hand, if no error occurs in the AV data processing (step  217 ), the disk drive reports that the command is terminated as usual (step  219 ). 
     Then, receiving the termination report from the disk drive, the host reads the registers indicating the execution result and checks the status when the process is terminated (step  220 ). After the AV data processing command is completed, the process returns to step  201 . 
       FIG. 5  shows a control flow for continuing the data transfer to the cache till any cache error occurs in the subsequent AV data processing even after the data transfer to the host is interrupted upon the interruption of the PC data read processing due to the timeout. 
     Starting the PC data processing, the disk drive of the present embodiment sets a time limit for the PC data processing and starts the timer (step  501 ). Next, the PC data processing command is started (step  502 ). It is checked whether there is a timeout (step  503 ) and, if the timeout is detected, it is checked whether the data is being transferred to the host (step  504 ) and, if the data is transferred to the host at the time of the timeout, the data transfer to the cache is continued (step  505 ) and the data transfer to the host is interrupted (step  506 ). On the other hand, when the timeout is detected and it is checked whether the data is being transferred to the host (step  504 ), if the data is not being transferred, the PC data processing is interrupted (step  508 ). Next, the processing status at the time of the interruption is set in the registers (step  507 ). The execution result is reported to the host (step  511 ). 
     On the other hand, when the PC data processing command is started (step  502 ) and it is checked whether there is a timeout (step  503 ), if the timeout is not detected, it is checked whether the command processing is terminated (step  509 ). If the command processing is not terminated, the timeout is checked again (step  503 ). When it is checked whether the command processing is terminated (step  509 ), if the command processing is terminated, the execution result is set in the registers (step  510 ). The execution result is reported to the host (step  511 ). 
     Next, it is checked whether the HDC  106  receives the next command (step  512 ). If the next command is received, it is checked whether the received command is the AV data processing command (step  513 ). If it is not the AV data processing command, the disk drive reports to the host that it cannot execute the received command (step  514 ) and checks whether the command is received again (step  512 ). 
     On the other hand, when it is checked whether the received command is the AV data processing command (step  513 ), if it is the AV data processing command, it is checked whether there is a cache hit for the data of the command (step  515 ). If there is a cache hit, the data transfer to the cache for the interrupted PC data processing command is continued (step  516 ). On the other hand, if there is no cache hit for the received AV data processing command, the data transfer to the cache for the interrupted PC data processing command is discontinued (step  517 ). 
       FIG. 6  shows a process flow in which the host notifies the disk drive of a command publication interval for each stream. The host notifies the disk drive of a command publication interval that is required for maintaining a data transfer rate for each stream (step  61 ). The command publication interval is notified, for example, by using Set Features command in ATA/ATAPI-5. Receiving the command publication interval for each stream from the host, the disk drive of the present embodiment stores the command publication interval for each stream in the RAM  102  (step  62 ). 
       FIG. 7  shows parameters in the Set Features command for notifying the command publication interval for each stream. EFh code  702  representing the Set Features command is written in Command register ( 701 ). Then, 34h ( 704 ) is set in Features register  703  as Sub Command code representing the command publication interval. Then, a stream ID ( 706 ) is set in Sector Count register ( 705 ). Then, a command publication interval time ( 708 ) for each stream is set in Sector Number register ( 707 ). As Cylinder Low ( 709 ) and Cylinder High ( 710 ) registers do not have to be set to a specific value,  0  is set in these registers. Then, a number of the selected device (a master device is numbered as 0 and a slave device is numbered as 1) is set in bit  4  ( 712 ) of Device/Head register  36  ( 711 ). Then, no value is set in bits  0  to  3  and  6  of the Device/Head register ( 711 ). Then, 0 is set in bit  5  and bit  7  of the Device/Head register ( 711 ). 
       FIG. 8  shows an exemplary configuration of a command publication time management table for managing data for calculating a time that the disk drive can allocate for the PC data processing command. This table includes entries such as: a stream ID ( 81 ); a latest command publication time (ms) ( 82 ); a command publication interval (ms) ( 83 ); and a next command publication estimated time (ms) ( 84 ). In the latest command publication time ( 82 ) entry, a publication time of the latest command for each stream is registered. Then, in the command publication interval ( 83 ) entry, a command publication interval (ms) set by the host for each stream is registered. Then, in the next command publication time (ms) ( 84 ) entry, a next command publication estimated time that is calculated by adding the command publication interval to the latest command publication time for each stream is registered. 
       FIG. 9  shows a process flow for calculating the time that can be allocated for the PC data processing based on the command publication time management table described above. Upon receipt of the PC data processing command, a data processing time that can be allocated for the received command is calculated by subtracting the publication time of such command and, further, the time taken for interruption processing from the earliest command publication estimated time (step  91 ). Next, such time is set in the timer  103  and the time  103  is started (step  92 ). The Execution of the PC data processing command is started (step  93 ). 
     The timeout is checked (step  94 ) and, if the timeout is detected during the PC data processing, the PC data processing command is interrupted (step  95 ). Then the processing status at the time of the interruption is set in the registers of the HDC  106  (step  96 ). Then, the HDC  106  reports to the host that the command is terminated (step  97 ). 
     On the other hand, when the timeout is checked (step  94 ), if the timeout is not detected but the termination of the PC data processing command is detected (step  98 ), the execution result is set in the registers of the HDC  106  (step  99 ) and the host is reported that the command is terminated (step  97 ). 
     Further, when the timeout is checked (step  94 ), if the timeout is not detected and the termination of the PC data processing command cannot be detected, the process for detecting the timeout is performed again (step  94 ). 
     Alternatively, the command publication interval for each stream can be estimated by keeping a history of the command publication interval required for satisfying the data transfer requests by the host for each stream during the AV data processing. The next command publication time for each stream can be estimated based on the estimated command publication interval so that the time that can be allocated for the PC data processing can be calculated. 
       FIG. 10  shows an example of a command publication interval management table for managing a history of a command publication interval for each stream. This table includes entries such as: a stream ID ( 101 ); a latest command publication time (ms) ( 102 ); command publication intervals for the latest 10 commands (ms) ( 103 ); and an average command publication interval (ms) ( 104 ). In the latest command publication time ( 102 ) entry, a publication time of the latest command for each stream is registered. In the command publication intervals for the latest 10 commands (ms) ( 103 ) entry, the command publication intervals for the latest 10 commands for each stream are registered. In the average command publication interval (ms) ( 104 ) entry, an average value of the latest 10 commands at the maximum for each stream is registered. 
     When the command publication interval management table shown in  FIG. 10  is used, the method for calculating the execution time of the PC data processing command and the method for executing the PC data processing command are same as the process flow shown in  FIG. 9 . 
       FIG. 11  shows a control flow in which an AV data processing command can be executed with priority by interrupting an after write operation when the AV data processing command is received during the after write operation and there is a cache miss for such command. 
     When the disk drive of the present embodiment receives a command during an after write operation, it checks whether the received command is a read command (step  111 ). If it is the read command, it is checked whether it is an AV data processing command (step  112 ). If it is the AV data processing command, it is checked whether there is a writable area corresponding to the sector count requested by the received read command in the cache (step  113 ). If there is the writable area corresponding to the sector count requested by the received read command in the cache  105 , the after write operation is interrupted (step  114 ). On the other hand, if there is not the writable area corresponding to the sector count requested by the received read command in the cache  105 , the after write operation is continued till the area corresponding to the sector count requested to be read is freed (step  115 ). After that, the after write operation is interrupted (step  114 ). Next, the received AV data processing command is executed (step  116 ). 
     Further, if the received command is a read command and a PC data processing command, the process is executed after the after write operation that is being performed is finished (step  117 ). On the other hand, if the received command is a write command (step  118 ), the write data is transferred to the cache  105  and, then, queuing is performed (step  119 ). Further, if the received command is not a read command (step  111 ) and it is not a write command (step  118 ), the process is terminated. 
     It is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims alone with their full scope of equivalents.