Abstract:
A method for forming a via hole having a fine hole land with which the density of circuit patterns can be increased. The method includes forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a U.S. divisional application filed under 35 USC 1.53(b) claiming benefit of U.S. Ser. No. 11/484,708 filed in the United States on Jul. 12, 2006, which claims earlier benefit of Korean Patent Application No. 10-2005-0121752 filed in Korea on Dec. 12, 2005, the contents of which are hereby incorporated by reference. 
     
    
     FIELD 
       [0002]    The present invention relates to a via hole and a method for forming the same. More particularly, the present invention relates to a via-hole having a fine hole land, with which the density of circuit patterns can be increased, and a method for forming the same. 
       BACKGROUND 
       [0003]    With the recent evolution of electronics to slimness, lightness and high performance and with the rapid increase in the application of built-up PCBs (printed circuit boards) to light, slim and small electronic products including wireless communication terminals, digital camcorders, mobile computers, etc., multilayer PCBs are very extensively used. 
         [0004]    Multilayer PCBs enable interconnections to be achieved three dimensionally as well as in planes. Particularly, multilayer PCBs can improve the integration of functional devices, such as ICs (integrated circuit), LSICs (large scale integrated circuit), etc., allowing electronic products to have slimness, lightness, and high performance, to achieved structural integration of electric functions and to be produced in a significantly reduced assembly time period and at a low cost. 
         [0005]    Almost all the built-up PCBs employed in such applications have via-holes through which interlayer connection is achieved. The recent tendency toward slimness and lightness is causing laser drills to be the new rising technology used for the formation of the via-holes. 
         [0006]    Via-holes, corresponding to passageways for interlayer electric connection, were conventionally formed using mechanical drills. However, mechanical drilling results in too large a hole to form fine circuits, in addition to increasing the production cost. Nowadays, laser drilling is preferred. 
         [0007]    Generally representative of new, smaller vias, called “microvias”, a blind via is drilled from the surface of a PCB and terminates within the substrate. 
         [0008]    If the cross-sectional area that a via occupies decreases, the ability to utilize vias increases by a similar amount. 
         [0009]    However, the reduction of via size to microvia size means that mechanical drilling is of no commercial use, implying the generalization of some alternative processes, such as removal by way of laser or plasma. 
         [0010]    The removal of material is the result of an electrochemical reaction to laser pulse or plasma treatment, which is different from a cutting action or treatment. However, removal processes similar to laser pulse or plasma treatment eliminate materials around the central line as well. 
         [0011]    Because it primarily results in round holes, such removal, whether using laser, plasma, or others, competes with mechanical drilling. The formation of the round holes is often called ‘drilling’ due to the removal of materials around the central line, and is thus termed “micro via drilling”. 
         [0012]    With reference to  FIGS. 1A to 1D , the formation of via-holes in a PCB using a conventional laser drilling process is schematically shown in a stepwise manner. 
         [0013]    The conventional method for forming via holes in a PCB by laser drilling, as shown in  FIGS. 1A to 1D , comprises a laser drilling process, a desmearing and copper plating process, and a circuit patterning process. 
         [0014]    The formation of via holes in a PCB starts with the drilling of a copper clad laminate  101  of  FIG. 1A  to form via holes  102  which travel through two layers, as shown in  FIG. 1B . 
         [0015]    Next, as shown in  FIG. 1  C, a desmearing process is conducted, immediately followed by plating the inner walls of the holes with copper to form a copper-plated layer  103 . 
         [0016]    Subsequently, the copper-plated layer  103  is patterned to form a circuit. 
         [0017]    As a rule, the via holes  102  require hole lands for electrical interconnection. However, the hole lands of via holes act as hindrances to the increase of the degree of integration of circuit patterns. Referring to  FIG. 2A , which shows conventional via-holes in a plan view, hole lands  104   a - 104   c  prevent circuit lines  105   a - 105   c  from being arranged near each other. As shown in  FIG. 2A , although the via holes are disposed in a zigzag manner in order to reduce the distance between circuit lines  105   a - 105   c , the hole lands  104   a - 104   c  still interfere with the approach of the circuit line  105   a - 105   c  to each other. 
         [0018]      FIG. 2B  is a perspective view showing a via hole according to a conventional technology. The via hole, as shown in  FIG. 2B , comprises a hole inner wall  107  associated with an upper hole land  104   u  at its upper portion and with a down hole land  104   d  at its lower portion. The upper hole land  104   u  is extended through a circuit line  105  to a wire bonding pad while the down hole land  104   d  is associated with a solder ball pad  108 . As can be seen, the hole lands  104   u  and  104   d  still occupy large areas. 
       SUMMARY 
       [0019]    Therefore, it is an object of the present invention to provide a via hole having a fine hole land with which circuit patterns can be constructed at a high density, and a method for forming the same. 
         [0020]    In accordance with an aspect of the present invention, provided is a via hole having a fine hole land, comprising a first conductive layer formed on an inner wall in contact with an insulation layer; a second conductive layer outside the first conductive layer; and a circuit line, formed on the insulation layer, connecting to the second conductive layer, wherein the hole land is formed by the first and the second conductive layer. 
         [0021]    In a preferable embodiment, the first conductive layer is extended over the insulating layer. 
         [0022]    In another preferable embodiment, the first layer is an electroless plated layer. 
         [0023]    In a further preferable embodiment, the second conductive layer is an electroplated layer. 
         [0024]    In accordance with another aspect of the present invention, provided is a method for forming a via hole having a fine hole land, comprising: step 1 of forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; step 2 of forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and step 3 of forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0025]    The application of the preferred embodiments of the present invention is best understood with reference to the accompanying drawings, in which like reference numerals are used for like and corresponding parts, wherein: 
           [0026]      FIGS. 1A to 1D  are schematic views showing conventional processes of forming via holes in a printed circuit board using a laser drill; 
           [0027]      FIGS. 2A and 2B  are a plan view and a perspective view, respectively, showing via holes formed according to the conventional processes; 
           [0028]      FIGS. 3A and 3B  are a perspective view and a plan view, respectively, showing a via hole having a fine hole land in accordance with the present invention; 
           [0029]      FIGS. 4A to 4R  are schematic views showing processes of forming a via hole having a fine hole land in accordance with the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0030]    Below, a detailed description is given of an embodiment of the present invention with reference to the accompanying drawings. 
         [0031]    A via-hole having a fine hole land in accordance with an embodiment of the present invention is shown in the perspective view of  FIG. 3A  while  FIG. 3B . shows the arrangement of a plurality of the via holes in a plan view. 
         [0032]    In accordance with the present invention, a via hole having a fine hole land comprises a conductive inner wall layer  207 , an upper hole land  204   u  (consisting of  204   ui  and  204   uo ), a down hole land  204   d  (consisting of  204   di  and  204   do ), a wire bonding pad  206 , a solder ball pad  208 , and a circuit line  205  for connecting the wire bonding pad  206  with the upper hole land  204   u , as shown in  FIG. 3A . 
         [0033]    The hole land  204   u  is as large as the conductive inner wall layer  207  and is divided into an inner hole land  204   ui  and an outer hole land  204   uo , which extends from the inner hole land  204   ui . Preferably, the outer hole land  204   uo  ranges in thickness from 0 to 15 gm. The inner hole land  204   u i has a thickness of 10 pm. Although they are made from the same material, that is, copper, the inner hole land  204   ui  and the outer hole land  204   uo  are different in crystalline structure from each other because different processes are used. Specifically, the inner hole land  204   ui  is electroplated with copper while the outer hole land  204   uo  consists of an electroless copper plated layer and electro-copper plated layer. 
         [0034]      FIG. 3B  shows the arrangement of a plurality of the via holes having the fine hole lands  204   ui  and  204   uo  in a plan view. As shown in  FIG. 3B , the thinness of the outer hole lands  204   uoa  to  204   uoc  allows circuit lines  205   a  to  205   c  to be disposed closely adjacent to each other, increasing the degree of integration of the circuit patterns. 
         [0035]    With reference to  FIGS. 4A to 4R , a method of forming a via hole in accordance with an embodiment of the present invention is illustrated in a stepwise manner. 
         [0036]    First, as shown in  FIG. 4A , a copper clad laminate  410  comprising an insulation layer  411  with respective copper layers  412   a  and  412   b  formed on opposite faces thereof is provided. 
         [0037]    The insulation layer  411  is based on resin. Resinous materials show high insulation properties, but suffer from the disadvantage of being poor in mechanical strength and being dimensionally more unstable in response to temperature change than metallic materials. In order to overcome the disadvantages, paper, glass fiber, or glass non-woven fabric is used as a reinforcement. The reinforcement increases the strength of the resinous material in both widthwise and lengthwise directions and decreases the dimensional change with temperature. 
         [0038]    The copper clad laminate  410 , although shown having copper layers  412   a  and  412   b  on opposite faces thereof, may comprise only one copper layer. 
         [0039]      FIG. 4B  is a schematic cross sectional view after the copper clad laminate ( 410 ) is drilled to form via holes  420 . 
         [0040]    As currently available technologies for forming via holes in PCBs, there are excimer, Nd:YAG and CO2 laser drilling processes. 
         [0041]    Excimer laser is not applied to PCBs. A YAG laser using 355 nm can drill through the copper layer, but is 90% reflected by glass epoxy, which may be used in a prepreg form for the insulation layer. 
         [0042]    In contrast, a CO2 laser of 9.4 μm can be applied for drilling the copper clad laminate because it is absorbed in an amount of 80%. 
         [0043]    Afterward, as shown in  FIG. 4C , etching resists  430   a ,  430   b  are formed on either or both surfaces of the copper clad laminate  410  having the via holes  420  therein. The formation of the etching resists can be achieved in a photographic process or a screen printing process. For the photographic process, a dry film may be an etching resist, as in a D/F method, or a liquid photosensitive material may be used. 
         [0044]      FIG. 4D  is a cross sectional view after an image forming process is conducted to form a pattern of the etching resists  430   a ,  430   b  on the copper layers  412   a ,  412   b , respectively and an etchant is sprayed to remove the copper layer  412   a ,  412   b  from predetermined areas, with the pattern of the etching resists serving as a mask. The resulting copper clad laminate  410  is shown in the plan view of  FIG. 4E  and in the rear view of  FIG. 4F . As shown in  FIG. 4E , a circuit line  435   a  extends into the via hole  420 . In addition, a circuit line  435   b  is formed on the lower surface of the copper clad laminate  410  so as to extend into or over the via hole  420 , as shown in  FIG. 4F . 
         [0045]    Subsequently, as shown in  FIG. 4G , copper plating is conducted to form a seed layer  440 . The resulting copper clad laminate  410  is shown in the plan view of  FIG. 4H  and in the rear side view of  FIG. 4I . For the copper plating, electroless plating (or sputter) is performed prior to electroplating. The seed layer  440  preferably has a thickness from 0.5 to 1.5 μm. 
         [0046]    Electroless copper plating (or sputtering) is a technique for providing conductivity for insulators such as resins, ceramics, glass, etc. Performed in such a way that a substrate is immersed in a plating solution, electroless copper plating allows all parts of the substrate, including the inner wall of the hole, to be plated with copper. By this electroless copper plating, called primary copper plating, the upper copper layer is electrically connected with the lower copper layer. The primary copper plating results in a preliminary thin coat for subsequent electroplating. Due to poor physical properties, the electroless plated copper coat must be overcoated with copper through electroplating. 
         [0047]    The electric conductivity imparted to the inner wall of the hole by electroless copper plating enables electroplating to be applied thereto. The copper coat formed by electroplating is much thicker and exhibits better physical properties than the copper coat formed by electroless plating. 
         [0048]    Subsequently, as shown in  FIG. 4J , a photoresist  450   a ,  450   b  is selectively formed over the copper clad laminate  410  in such a way that only the inner wall of the via hole  420  is exposed. The photoresist  450   a ,  450   b  can be formed using a photographic method or a screen printing method. For the photographic method, a dry film may be used as an etching resist, as in a D/F method, or a liquid photosensitive material may be used. 
         [0049]    Afterwards, an image forming process is performed to remove the part of the photoresist  450   a ,  450   b  corresponding to the via hole  420  to expose the inner wall of the via hole  420 . The resulting structure of the copper clad laminate  410  is shown in the plan view of  FIG. 4K  and in a rear side view of  FIG. 4L . As shown in both  FIGS. 4K and 4L , only the inner wall of the via hole  420  is exposed. 
         [0050]      FIG. 4M  is a cross sectional view after a copper coat is formed on the inner wall of the via hole  420  with the seed layer  440  serving as a plating bar. Preferably, the copper coat  460  has a thickness of 10 .tm or greater. A 10 μm thick or thicker copper coat  460  assures reliable electric conduction between the upper and the lower layers. 
         [0051]    The resulting structure of the copper clad laminate, in which the copper coat  460  is formed on the inner wall of the via hole  420 , is shown in the plan view of  FIG. 4N  and in the rear side view of  FIG. 4O . 
         [0052]    With reference to  FIGS. 4N and 4O , the relatively thin seed layer  440  is formed on the inner wall of the via hole  420  while being coated with the relatively thick copper layer  460 . 
         [0053]    Thereafter, as shown in  FIG. 4P , the photoresist  450   a ,  450   b  is peeled off and the seed layer is removed by flash etching so as to form a circuit. 
         [0054]    Then, a photo solder resist process and subsequent processes are conducted as usual. 
         [0055]    As described hereinbefore, the present invention can decrease the area occupied by hole lands so as to increase the density of via holes, thereby realizing slimness of the PCB. 
         [0056]    That is, the present invention increases the number of circuit lines per unit area, thus increasing the density of circuit patterns. 
         [0057]    In addition, the present invention can be applied to the slimness of all electronic appliances which require fine patterns. 
         [0058]    Examples are described in terms of the preferred embodiment of present invention. However, it should be understood that such disclosure is not limited to the explicit description of the present invention. The description and the claims of present invention are to be interpreted as covering all alterations and modifications within the true scope of this invention.