Abstract:
An electrostatic discharge (ESD) protection device is provided. A proper trigger voltage is determined by providing an ESD doped injection layer into a PNPN structure and adjusting the injection energy and dosage of the ESD doped injection layer; a proper holding voltage is obtained by adjusting the size of the ESD doped injection layer, thus preventing the latch-up. The self-isolation effect of the electrostatic discharge protection device is formed on the basis of an epitaxial wafer high voltage process or a silicon-on-insulator (SOI) wafer high voltage process, the ESD protective device of the present invention can prevent the device from being falsely triggered due to noise interference. Compared with other known ESD protection devices, the device has the same electrostatic protection ability, much smaller area, and much lower cost.

Description:
FIELD OF THE INVENTION 
     The present disclosure relates to a structure of a semiconductor, and more particularly relates to an electrostatic discharge protection device. 
     BACKGROUND OF THE INVENTION 
     The Electrostatic Discharge (ESD) is a common natural phenomenon in our lives. A large current is produced in a short time when the electrostatic discharge occurs, which causes a catastrophic failure to the integrated circuit, thus it is an important issue causing failure in the production and application of the integrated circuit. For example, the Human-Body Model (HBM) usually occurs in the hundreds of nanoseconds, the maximum peak current may reach several amperes. While in the other modes, such as Machine Model (MM), and Charged-Device Model (CDM), the electrostatic discharge occurs in much shorter time, the current is much greater. Such a large current flows through the integrated circuit in a short time, and the generated power dissipation severely exceeds the allowable maximum value, thus the integrated circuit suffers a severely physical damage to failure. The problem can be solved from the environment and the circuit in the practical application. In the environment, the main solution is to reduce the generation of static electricity and eliminate the static electricity in time; such as using the materials difficult to produce static electricity, increasing humidity, increasing operating personnel and equipment grounding and so on. In the circuit, the main solution is to increase the electrostatic discharge tolerance of the integrated circuit, such as increasing an extra-ESD protection device or circuit to protect the internal circuit of the integrated circuit from being damaged by the electrostatic discharge. 
     Currently, a Silicon Controlled Rectifier (SCR) is widely used in the electrostatic discharge protection circuit of the integrated circuit due to great electrostatic discharge protection and the relatively smaller device area. Generally, the parasitic SCR according to the design of the device structure in the integrated circuit can provide an electrostatic discharge protection. 
     U.S. Pat. No. 5,012,317 discloses an SCR applied to electrostatic discharge protection. Referring to  FIG. 1 , the SCR device  10  includes a P-type substrate  11 , an N-type well  12  formed on the P-type substrate, a heavily doped P-type (P+) doped region  13  and a heavily doped N-type (N+) doped region  14  formed on the N-type well  12 . The P+ doped region  13  and the N+ doped region  14  are connected to a contact  17  (i.e. an input of the device  10 ) after connecting to each other, a heavily doped N-type (N+) doped region  15  and a heavily doped P-type (P+) doped region  16  are formed on the P-type substrate and inside the N-type well, the heavily doped N-type (N+) doped region  15  and the heavily doped P-type (P+) doped region  16  are connected to a cathode (i.e. the ground terminal of the device  10 ) after connecting to each other. When the P-N junction between the P-type substrate  11  and the N-type well  12  is avalanched, the SCR device is turned on, the SCR current flows through the P+ doped region  14 , the N-type well  12 , the P-type substrate  11 , and the N+ doped region  15  and releases energy to the ground terminal. The disadvantage of this structure is: when the trigger voltage is too high (approximately 60V) and the holding voltage is too low (approximately 10V), the integrated circuits with the operating voltage of 20V-40V cannot provide an effective electrostatic discharge protection, and the risk that the integrated circuit is failure due to the latch-up in practice is greatly increased. 
     Chinese patent 200510071001.6 discloses an electrostatic discharge device which can control the trigger voltage. Referring to  FIG. 2 , an electrostatic discharge device  20  formed in a P-type substrate  21 , which includes an N-type well  22 , a first N+ region  24   c  and a first P+ region  25   b  isolated by a field oxide, a field oxide layer  26 , a second N+ region  24   a , a second P+ region  25   a , and a third N+ region  24   b . In which, the second P+ region  25   a , the N-type well  22 , and the P-type substrate  21  form an equivalent transistor, while the N-type well  22 , the P-type substrate  21 , and the first N+ region  24   c  form another equivalent transistor. The field oxide layer  26  is used to isolate the third N+ region  24   b  and first N+ region  24   c . A first electrode is connected to the second N+ region  24   a  and the first P+ region  25   b  via a first electrical conductor  28 . A second electrode is connected to the second N+ region  24   a  and the second P+ region  25   a  via a second electrical conductor  27 . The electrical conductors  27  and  28  can be made of metal material. In which, the predetermined distance between the edge of the second field oxide layer adjacent to the third N+ region and the edge of the N-type well is d. The trigger voltage of the electrostatic discharge device is determined by adjusting the predetermined distance. The disadvantage of this structure is that the holding voltage cannot be effectively controlled; it is unable to resolve the risk that the integrated circuit is failure due to the latch-up effect. 
     SUMMARY OF THE INVENTION 
     Accordingly to this, it is desired to provide an electrostatic discharge protection device with an appropriate trigger voltage and the holding voltage. 
     An electrostatic discharge protection device includes a P-type substrate, a P-type epitaxial layer, an N-type buried layer, a first N-type well, a first P-type well, a second N-type well, an ESD doped injection layer, a first N+ region, a first P+ region, a second N+ region, and a second P+ region. The P-type epitaxial layer is disposed on the P-type substrate; the N-type buried layer is disposed between the P-type substrate and the P-type epitaxial layer; the first N-type well is disposed on the N-type buried layer, inside the P-type epitaxial layer; the first P-type well is disposed on the N-type buried layer, and adjacent to the first N-type well; the second N-type well is disposed on the N-type buried layer, between the first P-type well and the P-type epitaxial layer; the ESD doped injection layer is disposed in the first P-type well and the first N-type well; the first N+ region, and the first P+ region are disposed in the ESD doped injection layer; the second N+ region, and the second P+ region are disposed inside the ESD doped injection layer, and disposed in the first N-type well or the first P-type well with a conductivity type opposite to the ESD doped injection layer. 
     Another electrostatic discharge protection device is also provided. The electrostatic discharge protection device includes a P-type substrate, an oxide layer, a first N-type well, a first P-type well, a first trench, a second trench, an ESD doped injection layer, a first N+ region, a first P+ region, a second N+ region, and a second P+ region. The oxide layer is disposed on a side of the P-type substrate. The first N-type well is disposed on the other side of the oxide layer. The first P-type well is disposed on the side of the oxide layer, and adjacent to the first N-type well; the first N-type well and the first P-type well are on the same side of the oxide layer. The first trench is defined on a side of the oxide layer and adjacent to the first N-type well; the second trench is defined on the same side of oxide layer and adjacent to the first P-type well. The ESD doped injection layer is disposed in the P-type well and the first N-type well. The first N+ region and the first P+ region are disposed on a side of the ESD doped injection layer. The second N+ region, and the second P+ region are disposed in the first N-type well or the first P-type well with a conductivity type opposite to the ESD doped injection layer. 
     Compared with the prior art, an ESD doped injection layer is introduced to the PNPN structure of the prior art, the appropriate trigger voltage and holding voltage can be obtained by adjusting the ESD doped injection layer. A self-isolation effect formed based on an epitaxial wafer high voltage process or an SOI wafer high voltage process can prevent the device from being falsely triggered due to noise effect. In addition, compared with other conventional electrostatic protection devices, the electrostatic protection device has a much smaller area and a lower manufacturing cost on premise of the same electrostatic protection capability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional side view of a conventional SCR applied to a electrostatic protection circuit; 
         FIG. 2  is a cross-sectional side view of another conventional electrostatic protection device which can control the trigger voltage; 
         FIG. 3  is a cross-sectional view of an electrostatic protection device of a preferred embodiment of the present disclosure; 
         FIG. 4  is an equivalent circuit diagram of the electrostatic protection device shown in  FIG. 3 ; 
         FIG. 5  is a cross-sectional view of an electrostatic protection device of another preferred embodiment of the present disclosure; 
         FIG. 6  is an equivalent circuit diagram of the electrostatic protection device shown in  FIG. 5 ; 
         FIG. 7  is a cross-sectional view of an electrostatic protection device of a preferred embodiment of the present disclosure; 
         FIG. 8  is an equivalent circuit diagram of the electrostatic protection device shown in  FIG. 7 ; 
         FIG. 9  is a cross-sectional view of an electrostatic protection device of another preferred embodiment of the present disclosure; and 
         FIG. 10  is an equivalent circuit diagram of the electrostatic protection device shown in  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer the same or like parts. 
     An electrostatic protection device is provided in the present disclosure. In a preferred embodiment, the electrostatic protection device is manufactured by an epitaxial wafer high voltage process.  FIG. 3  is a cross-sectional view of an electrostatic protection device of a preferred embodiment of the present disclosure. In the illustrated embodiment, the EDS doped injection layer is N-type doping. Referring to  FIG. 3 , the electrostatic protection device includes a single electrostatic discharge protection unit  100   a , which includes a P-type substrate  101 , a P-type epitaxial layer  102 , an N-type buried layer  103 , a first N-type well  104 , a first P-type well  105 , a second N-type well  106 , an ESD doped injection layer  107   a , a first N+ region  108   a , a first P+ region  109   a , a second N+ region  108   b , a second P+ region  109   b , an anode  110 , and a cathode  111 . 
     The P-type epitaxial layer  102  is formed on the P-type substrate  101 . The N-type buried layer  103  is disposed between the P-type substrate  101  and the P-type epitaxial layer  102 . The first N-type well  104  and the first P-type well  105  are disposed on the N-type buried layer  103 , inside the P-type epitaxial layer  102 , and adjacent to each other. The N-type ESD doped injection layer  107   a  is disposed in the first N-type well  104  and the first P-type well  105 . The first N+ region  108   a  and the first P+ region  109   a  are disposed in the N-type ESD doped injection layer  107   a . The second N+ region  108   b  and the second P+ region  109   b  are disposed in the first P-type well  105  and not connected to the N-type ESD doped injection layer  107   a . The first N+ region  108   a  and the first P+ region  109   a  are connected to the anode  110 . The second N+ region  108   b  and the second P+ region  109   b  are connected to the cathode  111 . 
     Referring to  FIG. 3 , the first P+ region  109   a , the N-type ESD doped injection layer  107   a , the first N-type well  104 , the first P-type well  105 , and the second N+ region  108   b  form a P-N-N(ESD implant)-P-N device structure; the first N+ region  108   a  is the lead of the first N-type well  104 , the second P+ region  109   b  is the lead of the first P-type well  105 . When the electrostatic protection device is applied in the integrated circuit, the first N+ region  108   a  and the first P+ region  109   a  are connected to form the anode  110  and connect to a high potential; the second N+ region  108   b  and the second P+ region  109   b  are connected to form the cathode  110  and connect to a low potential. The N-type buried layer  103 , the first N-type well  104 , and the second N-type well  106  are used to isolate the electrostatic protection device and the protected integrated circuit, and prevent the device from being falsely triggered due to noise effect. 
       FIG. 4  is an equivalent circuit diagram  200   a  of the electrostatic protection device shown in  FIG. 3 . Referring to  FIG. 3  and  FIG. 4 , the first P+ region  109   a  is equivalent to a emitter of a PNP transistor  201   a ; the first N-type well  104  and the N-type ESD doped injection layer  107   a  are equivalent to a base of the transistor  201   a ; the first P-type well  105  is equivalent to a collector of the transistor  201   a . The first N-type well  104  and the N-type ESD doped injection layer  107   a  are equivalent to a collector of the NPN transistor  202   a ; the first P-type well  105  is equivalent to a base of the transistor  202   a ; the second N+ region  108   b  is equivalent to a emitter of the transistor  202   a . In the  FIG. 4 , a resistance  203   a  is regard as an equivalent resistance of the N-type ESD doped injection layer  107   a  and recorded as Rn. The resistance Rn is connected to the anode  110  via the first N-type well  104 . The trigger voltage of the self-isolation electrostatic protection device is a smaller value of the BVceo of the transistor  201   a  and the Bvceo of the transistor  202   a . The BVceo of the transistor  201   a  and the transistor  202   a  can be determined by adjusting the injection energy and dose of the N-type ESD doped injection layer  107   a , i.e. the trigger voltage can be determined by adjusting the injection energy and dose of the doped injection layer; thus the trigger voltage of the electrostatic protection device can be adjusted according to the requirement of the protection circuit. 
     In application, the electrostatic protection device is connected to an integrated circuit to be protected in parallel. The anode  110  is connected to the high potential; the cathode  111  is connected to the low potential. When the integrated circuit is in a normal operation, the electrostatic protection device will not be triggered, which is in a low leakage state similar to the reverse-biased diode. Referring to  FIG. 4 , the self-isolation electrostatic protection device is breakdown when a static electricity occurs. Due to the present of the parasitic resistance  203   a , both the transistor  201   a  and the transistor  202   a  are opened to a amplification status, the breakdown current is amplified by the transistors  201   a  to form the base current of transistor  202   a , and then is amplified by the transistor  202   a  to form the base current of the transistor  201   a . The breakdown current is constantly amplified to form a positive feedback when the product of the common base current gain is greater than 1, repeatedly, the current gain of transistor  201   a  and transistor  202   a  decreases with the increasing of the current until equilibrium, and the electrostatic discharge protection device is triggered into the low on-state. The self-isolation electrostatic discharge protection device has a great current conduction capability, thus the static current can be safely discharged. 
     Referring to  FIG. 4 , due to the presence of the parasitic resistance  203   a , the holding voltage of the self-isolation electrostatic discharge protection device after triggering is proportional to the resistance  203   a . The greater the resistance  203   a , the higher the holding voltage of the self-isolation electrostatic discharge protection device. The resistance  203   a  can reach the optimum value by adjusting the size of the ESD doped injection layer  107   a . Accordingly, the appropriate holding voltage can be obtained by adjusting the size of the ESD doped injection layer  107   a . Moreover, the holding voltage is adjusted to greater than the operating voltage to avoid the latch-up. 
       FIG. 5  is a cross-sectional view of an electrostatic protection device of another preferred embodiment of the present disclosure. In the illustrated embodiment, the ESD doped injection layer is P-type doping. Referring to  FIG. 5 , the electrostatic discharge protection device includes a single electrostatic discharge protection unit  100   b , which includes a P-type substrate  101 , a P-type epitaxial layer  102 , an N-type buried layer  103 , a first N-type well  104 , a first P-type well  105 , a second N-type well  106 , an ESD doped injection layer  107   b , a first N+ region  108   a , a first P+ region  109   a , a second N+ region  108   b , a second P+ region  109   b , an anode  110 , and a cathode  111 . 
     Referring to  FIG. 5  and  FIG. 3 , the electrostatic discharge protection unit  100   b  is the same as the electrostatic discharge protection unit  100   a  shown in  FIG. 3 , The P-type substrate  101 , the P-type epitaxial layer  102 , the N-type buried layer  103 , the first N-type well  104 , the first P-type well  105 , and the second N-type well  106  of the electrostatic discharge protection unit  100   b  and the electrostatic discharge protection unit  100   a  are similar to each other, which are not described here in detail. In the electrostatic discharge protection unit  100   b  shown in  FIG. 5 , the P-type ESD doped injection layer  107   b  is disposed in the first N-type well  104  and the first P-type well  105 . The first N+ region  108   a  and the first P+ region  109   a  are disposed in the first N-type well  104 . The second N+ region  108   b  and the second P+ region  109   b  are disposed in P-type ESD doped injection layer  107   b . The first N+ region  108   a  and the first P+ region  109   a  are not connected to the P-type ESD doped injection layer  107   b . The first N+ region  108   a  and the first P+ region  109   a  are connected to the anode  110 ; the second N+ region  108   b  and the second P+ region  109   b  are connected to the cathode  111 . 
       FIG. 6  is an equivalent circuit diagram of the electrostatic protection device shown in  FIG. 5 . Referring to  FIG. 6  and  FIG. 5 , the first P+ region  109   a  is equivalent to an emitter of a PNP transistor  201   b ; the first N-type well  104  is equivalent to a base of the transistor  201   b ; the first P-type well  105  and the N-type ESD doped injection layer  107   b  are equivalent to a collector of the transistor  201   b . The first N-type well  104  is equivalent to a collector of the NPN transistor  202   b ; the first P-type well  105  and the N-type ESD doped injection layer  107   b  are equivalent to a base of the transistor  202   b ; the second N+ region  108   b  is equivalent to a emitter of the transistor  202   b . A resistance  203   b  is regard as an equivalent resistance of the N-type ESD doped injection layer  107   b , recorded as Rp. The resistance Rp is connected to the cathode  111  via the first P-type well  105 . The trigger voltage can also be determined by adjusting the injection energy and dose of the doped injection layer  107   b ; thus the trigger voltage of the electrostatic protection device can be adjusted according to the requirement of the protection circuit. 
     Referring to  FIG. 6 , the self-isolation electrostatic protection device is breakdown when a static electricity occurs. Due to the presence of the parasitic resistance  203   b , i.e. the Rp, the working principle is the same as that shown in  FIG. 4 . The self-isolation electrostatic discharge protection device has a great current conduction capability due to the amplification of the PNP transistor  201   b  and the NPN transistor  202   b , thus the static current can be safely discharged. Due to the presence of the parasitic resistance  203   b , i.e. the Rp, the holding voltage of the self-isolation electrostatic discharge protection device after triggering is proportional to the resistance Rp. The greater the resistance Rp, the higher the holding voltage of the self-isolation electrostatic discharge protection device. The resistance Rp can reach the optimum value by adjusting the size of the ESD doped injection layer  107   a . Accordingly, the appropriate holding voltage can be obtained by adjusting the size of the ESD doped injection layer  107   a . Moreover, the holding voltage is adjusted to greater than the operating voltage to avoid the latch-up. 
       FIG. 7  is a cross-sectional view of an electrostatic protection device of a preferred embodiment of the present disclosure. In the illustrated embodiment, the electrostatic discharge protection device  1200  includes an electrostatic discharge protection unit  1100   a , an electrostatic discharge protection unit  1100   b  manufactured by the epitaxial wafer high voltage process, and a second P-type well  1302 . The structure of electrostatic discharge protection units  1100   a  and  1100   b  shown in the dashed box of  FIG. 7  are the same. Take the electrostatic discharge protection unit  1100   a  as an example, which includes a P-type substrate  1101 , a P-type epitaxial layer  1102 , an N-type buried layer  1103   a , a first N-type well  1104   a , a first P-type well  1105   a , a second N-type well  1106   a , an ESD doped injection layer  1107   a , a first N+ region  1108   a , a first P+ region  1109   a , a second N+ region  1108   b ′, a second P+ region  1109   b ′, an anode  1110 , and a cathode  1111 . The P-type epitaxial layer  1102  is formed on the P-type substrate  1101 . The N-type buried layer  1103   a  is formed between the P-type substrate  1101  and the P-type epitaxial layer  1102 . The first N-type well  1104   a  and the first P-type well  1105   a  are disposed on the N-type buried layer  1103   a  and inside the P-type epitaxial layer  1102 . The second N-type well  1106  is disposed in the P-type epitaxial layer  1102 . The first N-type well  1104   a  is adjacent to the first P-type well  1105   a . The first P-type well  1105   a  is adjacent to the second N-type well  1106 . The N-type ESD doped injection layer  1107   a  is disposed in the first N-type well  1104   a  and the first P-type well  1105   a . The first N+ region  1108   a  and the first P+ region  1109   a  are disposed in the N-type ESD doped injection layer  1107   a . The second N+ region  1108   b ′ and the second P+ region  1109   b ′ are disposed inside the N-type ESD doped injection layer  1107   a  and in the first P-type well  1105   a . The structure of the electrostatic discharge protection unit  1100   b  is the same of that of the electrostatic discharge protection unit  1100   a . The two electrostatic discharge protection units are connected via the second P-type well  1302 . The second P-type well  1302  is further connected to the N-type buried layers  1103   a  and  1103   b , the first N-type wells  1104   a  and  1104   b , and the second N-type wells  1106   a  and  1106   b , thus the electrostatic discharge protection device  1200  is isolated to the protected integrated circuit. The second N+ region  1108   b ′ and the second P+ region  1109   b ′ of the electrostatic discharge protection unit  1100   a  are electrically connected to the third N+ region  1108   a ′ and the third P+ region  1109   a ′ of the electrostatic discharge protection unit  1100   b . The first N+ region  1108   a  and the first P+ region  1109   a  of the electrostatic discharge protection unit  1100   a  are connected to the anode  1110 ; the fourth N+ region  1108   b  and the fourth P+ region  1109   b  of the electrostatic discharge protection unit  1100   b  are connected to the cathode  1111 . In the illustrated embodiment, both the ESD doped injection layers  1107   a  and  1107   b  are N-type doping. It should be noted that, alternatively, the ESD doped injection layer can be N-type doping or P-type doping, and the doping types of the ESD of the electrostatic discharge protection units connected in series can be different, which is not limited by the illustrated embodiment. 
     Referring to  FIG. 7 , the first P+ region  1109   a , the N-type ESD doped injection layer  1107   a , the first N-type well  1104   a  of the electrostatic discharge protection unit  1100   a , the N-type ESD doped injection layer  1107   b , the first P-type well  1105 , and the second N+ region  1108   b  of the electrostatic discharge protection unit  1100   b  form the P-N-N (ESD implant)-P-N device structure. The first N+ region  1108   a  of the electrostatic discharge protection unit  1100   a  is the lead of the first N-type well  1104   a ; the fourth P+ region  1109   a  of the electrostatic discharge protection unit  1100   b  is the lead of the first P-type well  1105   b . When the electrostatic protection device  1200  is applied to the integrated circuit, the first N+ region  1108   a  and the first P+ region  1109   a  of the electrostatic discharge protection unit  1100   a  are connected to the anode  1110  to connect to a high potential; the fourth N+ region  1108   b  and the fourth P+ region  1109   b  of the electrostatic discharge protection unit  1100   b  are connected the cathode  1111  to connect to a low potential. The N-type buried layer  1103   a , the first N-type well  1104   a  of the electrostatic discharge protection unit  1100   a , and the N-type buried layer  1103   b  and the second N-type well  1106   b  are used to isolate the electrostatic protection device  1200  and the protected integrated circuit to prevent the device from being falsely triggered due to noise effect. 
       FIG. 8  is an equivalent circuit diagram  1300  of the electrostatic protection device  1200  shown in  FIG. 7 . The dashed boxes  1200   a  and  1200   b  are the equivalent circuit diagram of the electrostatic protection units  1100   a  and  1100   b . Referring to  FIG. 8  and  FIG. 7 , the first P+ region  1109   a  of the electrostatic discharge protection unit  1100   a  is equivalent to a emitter of a PNP transistor  1201   a ; the first N-type well  1104   a  and the N-type ESD doped injection layer  1107   a  of the electrostatic discharge protection unit  1100   a  are equivalent to a base of the PNP transistor  1201   a ; the first P-type well  1105   a  of the electrostatic discharge protection unit  1100   a  is equivalent to a collector of the PNP transistor. The first N-type well  1104   a  and the N-type ESD doped injection layer  1107   a  of the electrostatic discharge protection unit  1100   a  are equivalent to a collector of the NPN transistor  1202   a ; the first P-type well  1105   a  of the electrostatic discharge protection unit  1100   a  is equivalent to a base of the NPN transistor  1202   a ; the second N+ region  1108   b ′ of the electrostatic discharge protection unit  1100   a  is equivalent to a emitter of the NPN transistor  1202   a . A resistance  1203   a  is regard as an equivalent resistance of the N-type ESD doped injection layer  1107   a  of the electrostatic discharge protection unit  1100   a , recorded as Rn. The resistance  1203   a  is connected to the anode  1110  via the first N-type well  1104   a  of the electrostatic discharge protection unit  1100   a . The trigger voltage of the self-isolation electrostatic protection device is the smaller value of the BVceo of the PNP transistor  1201   a  and the Bvceo of the NPN transistor  1202   a . The BVceo of the PNP transistor  1201   a  and the NPN transistor  1202   a  can be determined by adjusting the injection energy and dose of the N-type ESD doped injection layer  1107   a , i.e. the trigger voltage can be determined by adjusting the injection energy and dose of the doped injection layer; thus the trigger voltage of the electrostatic protection device can be adjusted according to the requirement of the protection circuit. The trigger voltage doubles when the electrostatic discharge protection units  1100   a  and  1100   b  are connected in series, while the doubling of the trigger voltage is limited by the withstand voltage of the peripheral isolation structure, the trigger voltage of the device can reach tens of volts after being connected in series. 
     In application, the electrostatic protection device is connected to an integrated circuit to be protected in parallel. The anode  1110  is connected to the high potential; the cathode  1111  is connected to the low potential. When the integrated circuit is in a normal operation, the electrostatic protection device will not be triggered, which is in a low leakage state similar to the reverse-biased diode. Referring to  FIG. 8 , the self-isolation electrostatic protection device is breakdown when a static electricity occurs. Due to the present of the resistance  1203   a  and resistance  1203   b , the PNP transistors  1201   a ,  1201   b , and the NPN transistors  1202   a  and  1202   b  are opened to a amplification status, the breakdown current is amplified by the PNP transistors to form the base current of the NPN transistors, and then amplified by the NPN transistors to form the base current of the PNP transistors. The breakdown current is constantly amplified to form a positive feedback when the product of the common base current gain of the PNP transistors and the NPN transistors is greater than 1, repeatedly, the current gain of the PNP transistors and the NPN transistors decreases with the increasing of the current until equilibrium, and the electrostatic discharge protection device is triggered into the low on-state. The self-isolation electrostatic discharge protection device has a great current conduction capability due to the amplification of the PNP transistors and the NPN transistors, thus static current can be safely discharged. 
     Referring to  FIG. 8 , due to the presence of the resistances  1203   a  and  1203   b , the holding voltage of the self-isolation electrostatic discharge protection device after triggering is proportional to the resistances  1203   a  and  1203   b . The greater the resistance value Rn of the resistances  1203   a  and  1203   b , the higher the holding voltage of the self-isolation electrostatic discharge protection device. The resistance value Rn of the resistances  1203   a  and  1203   b  can reach the optimum value by adjusting the size of the ESD doped injection layer  1107   a  and  1107   b . Accordingly, the appropriate holding voltage can be obtained by adjusting the size of the ESD doped injection layer. Moreover, the holding voltage is adjusted to greater than the operating voltage to avoid the latch-up. 
       FIG. 9  is a cross-sectional view of an electrostatic protection device of another preferred embodiment of the present disclosure. In a preferred embodiment, the electrostatic protection device is on the basis of the SOI wafer high voltage process. Partial structures of the electrostatic protection device of the illustrated embodiment are the same as those of the electrostatic protection device shown in the  FIG. 3  and  FIG. 5 , the reference signs are the same. Referring to  FIG. 9 , the electrostatic protection device  400  includes a P-type substrate  101 , an oxide layer  502 , a first N-type well  104 , a first P-type well  105 , a first trench  503 , a second trench  504 , an ESD doped injection layer  107 , a first N+ region  108   a , a first P+ region  109   a , a second N+ region  108   b , a second P+ region  109   b , an anode  110 , and a cathode  111 . Referring to  FIG. 9 , the oxide layer  502  is formed on the P-type substrate  101 . The first N-type well  104  and the first P-type well  105  are formed on the oxide layer  502 . The first trench  503  and the second trench  504  are defined on the oxide layer  502 . The first trench  503 , the first N-type well  104 , the first P-type well  105 , and the second trench  504  are adjacent in order. The P-type ESD doped injection layer  107   b  is formed in the first N-type well  104  and the first P-type well  105 . The second N+ region  108   b  and the second P+ region  109   b  are disposed in the P-type ESD doped injection layer  107   b . The first N+ region  108   a  and the first P+ region  109   a  are formed in the first N-type well  104  and inside the P-type ESD doped injection layer  107   b . The first N+ region  108   a  and the first P+ region  109   a  are connected to the anode  110 ; the second N+ region  108   b  and the second P+ region  109   b  are connected to the cathode  111 . 
     In the illustrated embodiment, the ESD doped injection layer  107   b  is P-type doping, it should be noted that, the ESD doped injection layer  107   b  can be N-type doping or P-type doping, which is not limited by the illustrated embodiment. The electrostatic protection device of the illustrated embodiment is similar to that shown in  FIG. 3  and  FIG. 5 , which is not described here in detail again. In the illustrated embodiment, the appropriate trigger voltage and holding voltage can be obtained by adjusting the injection dose and energy of the ESD doped injection layer  107   b.    
     Referring to  FIG. 9 , in application, the electrostatic protection device is connected to an integrated circuit to be protected in parallel. The anode  110  is connected to the high potential; the cathode  111  is connected to the low potential. When the integrated circuit is in a normal operation, the electrostatic protection device will not be triggered, which is in a low leakage state similar to the reverse-biased diode. The self-isolation electrostatic protection device is breakdown when a static electricity occurs. The working principle of the protection is the same as that of the electrostatic protection device manufactured by the epitaxial wafer high voltage process shown in  FIG. 3  and  FIG. 5 . The difference is: the isolation structure is formed by the N-type well and the N-type buried layer in the epitaxial wafer high voltage process, while the isolation structure is formed by the oxide layer and the trench in the SOI wafer high voltage process. The oxide layer  502  forms the isolation on the bottom of the device, and the first trench  203  and the second trench  504  form the isolation on the periphery of the device. The electrostatic protection device has a much higher trigger voltage because the breakdown voltage of the isolation structure of the oxide layer and the trench is much higher. 
     The electrostatic protection device of the present disclosure can be applied in the device with an operating voltage more than 5V in the high voltage environment. 
       FIG. 10  is a cross-sectional view of an electrostatic protection device of another embodiment of the present disclosure. In a preferred embodiment, the electrostatic protection device is on the basis of the SOI wafer high voltage process. Partial structures of the electrostatic protection device of the illustrated embodiment are the same as those of the electrostatic protection device shown in the  FIG. 7 , the reference signs are the same. Referring to  FIG. 10 , the electrostatic protection device includes electrostatic discharge protection units  1500   a ,  1500   b , and an isolation structure  1505 . The structures of the electrostatic discharge protection unit  1500   a  and  1500   b  shown in the dashed box of  FIG. 10  are the same. Take the electrostatic discharge protection unit  1500   a  as an example, the electrostatic protection device unit  1500   a  includes a P-type substrate  1101 , an oxide layer  1502 , a first N-type well  1104   a , a first P-type well  1105   a , a first trench  1503   a , a second trench  1504   a , an ESD doped injection layer  1107   a , a first N+ region  1108   a , a first P+ region  1109   a , a second N+ region  1108   b ′, a second P+ region  1109   b ′, an anode  1110 , and a cathode  1111 . The oxide layer  1502  is formed on the P-type substrate  1101 . The first N-type well  1104   a  and the first P-type well  1105   a  are formed on the oxide layer  1502 . The first trench  1503   a  and the second trench  1504   a  are defined on the oxide layer  1502 . The first trench  1503   a , the first N-type well  1104   a , the first P-type well  1105   a , and the second trench  1504   a  are adjacent in order. The P-type ESD doped injection layer  1107   a  is formed in the first N-type well  1104   a  and the first P-type well  1105   a . The second N+ region  1108   b ′ and the second P+ region  1109   b ′ are disposed in the P-type ESD doped injection layer  1107   a . The first N+ region  1108   a  and the first P+ region  1109   a  are formed in the first N-type well  1104   a  and inside the P-type ESD doped injection layer  1107   a . The structure of the electrostatic discharge protection unit  1500   b  is the same as that of the electrostatic discharge protection unit  1500   a . The two electrostatic discharge protection units are connected via the isolation structure  1505 , which is further connected to the oxide layer  1502 , the first trenches  1503   a  and  1503   b , and the second trenches  1504   a  and  1504   b  to isolate the electrostatic protection device  1400  and the protected integrated circuit. It should be noted that, the first N+ region  1108   a  and the first P+ region  1109   a  of the electrostatic protection unit  1500   a  are connected to form the anode  1110  and connect to a high potential; the fourth N+ region  1108   b  and the fourth P+ region  1109   b  of the electrostatic protection unit  1500   b  are connected to form the cathode  1111  and connect to a low potential. The second N+ region  1108   b ′ and the second P+ region  1109   b ′ of the electrostatic discharge protection unit  1500   a  are electrically connected to the third N+ region  1108   a ′ and the third P+ region  1109   a ′ of the electrostatic discharge protection unit  1500   b . In the illustrated embodiment, both the ESD doped injection layers  1107   a  and  1107   b  are P-type doping. It should be noted that, alternatively, the ESD doped injection layer can be N-type doping or P-type doping, and the doping types of the ESD of the electrostatic discharge protection units connected in series can be different, which is not limited by the illustrated embodiment. 
     Referring to  FIG. 10 , the electrostatic protection device  1400  is connected to an integrated circuit to be protected in parallel. The anode  1110  is connected to the high potential; the cathode  1111  is connected to the low potential. When the integrated circuit is in a normal operation, the electrostatic protection device will not be triggered, which is in a low leakage state similar to the reverse-biased diode. The self-isolation electrostatic protection device is breakdown when a static electricity occurs. The working principle of the protection is the same as that of the electrostatic protection device manufactured by the epitaxial wafer high voltage process, while the isolation structure is formed by the oxide layer and the trench in the SOI wafer high voltage process to replace the N-type well and the N-type buried layer in the epitaxial wafer high voltage process. The oxide layer  1502  forms the isolation on the bottom of the device, and the first trench  1503   a  and the second trench  1504   b  forms the isolation on the periphery of the device. The electrostatic protection device has a much higher trigger voltage because the breakdown voltage of the oxide layer and trench structure is much higher. 
     The appropriate trigger voltage and the holding voltage can be obtained by adjusting the injection energy and dose of the doped injection layer. The trigger voltage of the electrostatic protection device based on the SOI wafer high voltage process is more than 100V because the breakdown voltage of the oxide layer and trench structure is much higher. 
     The electrostatic protection device of the present disclosure can be applied to the device with an operating voltage more than 5V in the high voltage environment. 
     Although the present invention has been described with reference to the embodiments thereof and the best modes for carrying out the present invention, it is apparent to those skilled in the art that a variety of modifications and changes may be made without departing from the scope of the present invention, which is intended to be defined by the appended claims.