Abstract:
A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates generally to the fields of liquid cooling of semiconductor chip circuitry, including phenomena such as gas-assisted evaporation of the cooling fluid, wetting of the chip surface(s) to be cooled and liquid retention by capillary force. 
         [0002]    Gas-assisted direct liquid cooling (GADLC) integrated circuit devices (ICs) are known. GADLC ICs are shaped to define interior space having interior surfaces. At least one of the interior surfaces (herein referred to as the liquid/chip interface) at, or at least close to, the IC circuitry that, in operation, generates heat such that cooling is required, or at least helpful. The interior space may have, located within it, porous material, such as a porous membrane. Gas and coolant fluid are circulated through the interior space in order to remove heat from the vicinity of the heat-generating circuitry of the IC. 
         [0003]    It is conventionally recognized that conventional GADLC ICs may experience “dry spots” at the liquid/chip interface. These dry spots hamper the cooling efficiency and reliability of the technology. In order to attempt to reduce dry spots, conventional GADLC IC include a membrane (as mentioned in the previous paragraph) and a support layer. The membrane and support layer are located in the interior space. This membrane and support layer are separate parts that are not integral or unitary with the material that forms the interior surfaces of the interior space. The membrane is conventionally a micro-/nano-porous membrane to maintain the coolant in the pores, and a porous support layer at the interface to keep the nano-membrane from coming in to direct contact with the chip. 
       SUMMARY 
       [0004]    According to an aspect of the present invention, a semiconductor assembly includes: (i) a substrate member including a first chip and a top surface; and (ii) a cap member with a first recess located therein, the cap member including a first recess surface and a first set of rigid small scale structure(s) extending from at least a portion of the first recess surface into the first recess, with the first recess surface and the first set of rigid small scale structures defining the first recess. The first set of rigid small scale structure(s) include at least one of the following: (a) a structure having formed therein pores, gaps and or interstitial spaces less than 100 micrometers but more than 100 nanometers, and (b) a structure having formed therein pores, gaps and or interstitial spaces less than 100 nanometers. The first set of rigid small scale structure(s) are sized, shaped and located to provide for appropriate fluid flow when gas and liquid are circulated through the first recess for gas-assisted direct liquid cooling. The cap member is attached to the top surface of the substrate member at a location such that circulation of gas and liquid through the first recess will cool the first chip by gas-assisted direct liquid cooling. 
         [0005]    According to a further aspect of the present invention, a method of manufacturing a semiconductor assembly includes the following steps (not necessarily in the following order): (i) shaping a cap member to include a first set of small-scale-structure(s) and a first recess surface, with the first recess surface and first set of rigid small scale structure(s) defining a recess formed in the cap member; and (ii) bonding the cap member to a top surface of a first substrate which includes a first chip so that the first recess is located over at least a portion of the top surface and at least a portion of the first chip. The first set of small-scale-structure(s) are rigid. The cap member and first set of small-scale-structure(s) are sized, shaped, located and/or bonded so that: (i) the first set of small-scale-structure(s) face at least a portion of the top surface of the first chip, (ii) the first set of small-scale-structure(s) spaced away from the top surface of the first chip, and (iii) the first set of small scale structure(s) includes at least one of the following: (a) a structure having formed therein pores, gaps and or interstitial spaces less than 100 micrometers but more than 100 nanometers, and (b) a structure having formed therein pores, gaps and or interstitial spaces less than 100 nanometers. 
         [0006]    According to a further aspect of the present invention, a semiconductor assembly includes: (i) a substrate member including a plurality of chips and a top surface; and (ii) a cap member with a plurality of recesses formed therein, the cap member including a recess surface corresponding to each recess of the plurality of recesses and a plurality of sets of rigid small scale structure(s) respectively extending from at least a portion of each recess surface into each recess, with each recess surface and each set of rigid small scale structure(s) respectively defining a corresponding recess of the plurality of recesses. Each set of rigid small scale structure(s) includes a structure having formed therein pores, gaps and or interstitial spaces equal to or less than 100 micrometers. Each set of rigid small scale structure(s) are sized, shaped and located to provide for appropriate fluid flow when gas and liquid are circulated through the first recess for gas-assisted direct liquid cooling. The cap member is attached to the top surface of the substrate member at a location such that circulation of gas and liquid through each recess cools a corresponding chip of the plurality of chips by gas-assisted direct liquid cooling. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0007]      FIGS. 1 to 7A  are cross-sectional views of a semiconductor assembly corresponding respectively to seven stages of a first semiconductor fabrication method; 
           [0008]      FIG. 7B  is a plan view of the seventh stage of the first embodiment fabrication method; 
           [0009]      FIGS. 8A ,  8 B,  8 C and  8 D are cross-sectional, detail views of a nanowire formation process suitable for use in some embodiments of the present invention; 
           [0010]      FIGS. 9A ,  9 B,  9 C,  9 D,  9 E,  9 F,  9 G and  9 H are cross-sectional views of a semiconductor assembly corresponding respectively to eight stages of a second semiconductor fabrication method; 
           [0011]      FIGS. 10A ,  10 B,  10 C,  10 D and  10 E are cross-sectional views of a semiconductor assembly corresponding respectively to five stages of a third semiconductor fabrication method; 
           [0012]      FIGS. 11A ,  11 B,  11 C,  11 D,  11 E,  11 F, and  11 G are cross-sectional views of a semiconductor assembly corresponding respectively to four stages of a second semiconductor fabrication method; and 
           [0013]      FIGS. 12A ,  12 B,  12 C,  12 D and  12 E are cross-sectional views of a semiconductor assembly corresponding respectively to five stages of a second semiconductor fabrication method. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    A preliminary note on terminology will now be made. In this document, empty spaces, such as voids, apertures holes and/or recesses are said to be “defined” by the surfaces that surround the empty space. For example, the empty space inside of a cup is defined by the inner surface(s) of the cup itself. 
         [0015]    Some embodiments of the present disclosure recognize one, or more, of the following: (i) because of the membrane structure required for conventional GADLC chips conventional processes are not easily and/or feasibly scalable; and/or (ii) with conventional GADLC processing, precise control (such as, placement of the membrane and its support, the force, the gap between the membrane and the chip surface, MNS structure control) is difficult. 
         [0016]    Some embodiments of the present invention are directed to fabrication methods for making “built-in” MNSs for GADLC, such that there is no separate membrane piece, but, rather, the MNS is part of a unitary and integral cap piece that is fixed over a top surface of the semiconductor chip. Gas and/or liquid is circulated through an open space between the cap and a portion of the top surface of the semiconductor chip. The MNSs are located to extend from the main body of the cap, down into the open space between the cap and chip, where they can appropriately assist with fluid circulation (for example, GADLC fluid circulation) for chip cooling. Two basic variations of the various embodiments of the present invention are as follows: (i) providing the cap structure on a chip by chip basis; and (ii) providing the cap structure on a wafer by wafer basis. Some embodiments of the present invention are believed to be more amenable to wafer by wafer fabrication than is the conventional nano-membrane technology. Accordingly, while the embodiments to be described below will show only a single chip, some embodiments of the preferred invention will provide a single cap piece with multiple, discrete fluid spaces for multiple chip areas that reside on a single wafer. 
         [0017]    As shown in  FIGS. 1 to 7   b,  a first fabrication method includes six (6) intermediate assemblies  100   a,    100   b,    100   c,    100   d,    100   e  and  100   f  and one final assembly  100   g  (which is also shown in plan view in  FIG. 7   b ). For pedagogical purposes, it is noted that the respective assemblies  100   a  to  100   g  do not represent an exhaustive list of assembly states during manufacture, but, rather, these assemblies were chosen to efficiently assist those of skill in the art to understand the devices and/or manufacturing processes of the present invention. The following paragraphs will describe the processes involved in transforming the starting assembly  100   a  to intermediate assembly  100   b,  intermediate assembly  100   b  to intermediate assembly  100   c,  intermediate assembly  100   c  to intermediate assembly  100   d,  and so on until the final assembly of  100   g  is attained for use as an embodiment of a GADLC IC device. As shown in  FIG. 1 , in intermediate sub-assembly  100   a,  a chip sized area (shown) of a larger piece (not shown) of silicon cap material  102  (for example, silicon) is partially overlaid with a bonding layer  104 . More specifically, the bonding layer is shaped to have a square hole  106  at its central region. 
         [0018]    As manufacturing processes according to this embodiment of the present invention transform intermediate assembly  100   a  of  FIG. 1  to intermediate assembly  100   b  of  FIG. 2 , the portion of the top surface of cap  102  exposed by hole  106  of boding layer  104  has material removed in a top down fashion in order to form recess  112 . The recess may be formed, for example by conventional wet etching or conventional dry etching. 
         [0019]    As manufacturing processes according to this embodiment of the present invention transform intermediate assembly  100   b  of  FIG. 2  to intermediate assembly  100   c  of  FIG. 3 , MNSs  114  are formed at the bottom of the recess in cap  102  as shown in  FIG. 3 . This process for forming MNSs is shown in more detail in  FIGS. 8A to 8D , where: (i) in  FIG. 8A , a photoresist layer  150  is applied over semiconductor cap  102 ; (ii) in  FIG. 8B , radiation R is selectively transmitted by mask  152  so that the photoresist layer can be selectively removed, at a nano- or micro-scale; (iii) In  FIG. 8C , the semiconductor cap is etched in a top down material removal fashion, except in portions underlying remaining portions of the photoresist layer; and (iv) in  FIG. 8D , where the remaining portions of the photoresist layer are removed to expose the MNS protrusions left by the selective etching. Alternatively, a bottom up process can be used to build MNSs, where certain areas of the upper surface of the silicon cap are seeded with polymer and/or seed crystals so that silicon MNS protrusions can be selectively built up from the seeded areas only. For example, conventional chemical vapor deposition can be used to build up the silicon in the seeded areas to build bottom up MNS protrusions. It is noted that the MNSs are built into a rigid cap here, rather than being present in a conventional membrane structure. 
         [0020]    As manufacturing processes according to this embodiment of the present invention transform intermediate assembly  100   c  of  FIG. 3  to intermediate assembly  100   d  of  FIG. 4 , the cap is rotated (or, in semiconductor device fabrication parlance, “flipped”) and placed over semiconductor substrate  120 . Again, while  FIGS. 1 to 7   a  and  7   b  show only an area corresponding to a single chip, some devices according to the present invention are fabricated at the wafer scale so that both the cap portion and the semiconductor substrate portion are wafer sized and include many chips, which will usually be cut apart to form multiple discrete chips or chip stacks. In order to proceed from intermediate assembly  100   d  of  FIG. 4  to intermediate assembly  100   e  of  FIG. 5 , the cap and substrate are moved relative to each other in the vertical direction so that bonding layer  104  bonds the cap and substrate to each other, aligned so that recess  106 ,  112  is located over the central region of the semiconductor substrate. The bonding layer can be oxide, metal-metal, adhesive, etc. In some embodiments, the bonding is asymmetric bonding, but symmetric bonding can also be applied, meaning a same bonding layer (with/without the same opening/recess) can also be pre-formed on the surface of substrate  120 . 
         [0021]    As manufacturing processes according to this embodiment of the present invention transform intermediate assembly  100   e  of  FIG. 5  to intermediate assembly  100   f  of  FIG. 6 : (i) lithographic masking layer  130  with  5  through holes is applied over the top surface of cap  102 ; and (ii) cap material  102 , underlying the through holes in the masking, is removed to form five (5) channels  140 ,  142 ,  144 ,  146 , and  148 . In some embodiments, the material removal performed to remove the channels is performed by reactive ion etching (“silicon RIE”) as will be understood by those of skill in the art. It is noted that there is some concern that this material removal process could cause pieces of silicon to end up in open volume  106 ,  112 , and impede performance of the complete product when the chip is put into use and has gas and liquid running through it. In embodiments where this is a valid concern, the alternative fabrication methods, to be described below, will prevent this problem. 
         [0022]    As manufacturing processes according to this embodiment of the present invention transform intermediate assembly  100   f  of  FIG. 6  to final chip assembly  100   g  of  FIGS. 7   a  and  7   b  the lithographic masking layer is removed to yield the finished product. In wafer level fabrication processes, this is where the cutting of the wafer down to individual, capped chip assemblies can be done. The locations of the five (5) channels  140 ,  142 ,  144 ,  146  and  148  can be best understood by looking at both  FIGS. 7   a  and  7   b  in tandem. In this embodiment, when the chip assembly is operatively connected to a larger GADLC system: (i) channel  140  acts as an inlet for liquid coolant into the interior space; (ii) channels  142  and  146  act as gas outlets for the GADLC gas; (iii) channel  144  acts as a gas inlet for the GADLC gas; and (iv) channel  148  acts as a fluid inlet/outlet for the GADLC fluid. Alternatively, other channel geometries are possible. 
         [0023]    Before moving to other, alternative fabrication processes according to the present invention, some possible variations on device  100  of  FIGS. 1 to 7   a  and  7   b  will now be set forth: (i) the footprint shape of the interior space does not need to be square (for example, it could be rectangular or circular); and/or (ii) the number of through holes formed at intermediate assembly  100   f  of  FIG. 6  may be different than 5 (the number is a matter of design choice that depends, at least in part, on the gas flow and/or liquid flow requirements of a given GADLC IC design). The foregoing is by no means an exhaustive list of possible variations of the embodiment of device  100 . 
         [0024]    Before moving to other, alternative fabrication processes according to the present invention, it is noted that some embodiments of the present invention may include one, or more, of the following features, characteristics and/or advantages: (i) the built-in micro-/nano-structures do not require externally introduced membranes/support materials; (ii) during fabrication, piece parts are easier to handle and can be precisely controlled, fabricated and/or assembled by tailoring the MNSs, recession process, and bonding process; (iii) cooling structures can be fabricated in large scale semiconductor fabrication and packaging line with current process equipment and advanced printing; (iv) profiling of the cap at the micro and/or nano scale enables complex cooling structures and channels for optimal specific local cooling; (v) the MNSs are spaced apart from the major surface of the chip which they face; (vi) a built-in structure for gas-assisted direct liquid cooling in advanced thermal management; (vii) a method of fabricating the structure for gas-assisted direct liquid cooling, the method being scalable to wafer-level 3D integration and packaging; (viii) MNSs (such as MNS  114 ) in the form of a regular array of nanowires; (ix) nano-openings in the nano-structure layer that are interconnected in the x-y plane, and therefore, as a whole, only need one gas inlet and one gas outlet for the circulation purposes; (x) have a nanowire (and/or pore) layer (for example MNS  114 ) that acts similar to the membrane layer of a conventional GADLC chip, with the functions of (a) maintaining the liquid to prevent formation of dry spots, and (b) circulation in/out through gas in/out channels to improve the cooling efficiency (compared with only liquid coolant cooling); and (xi) the MNS structure may be, or include well and/or via, such as nanowells or nanovias (nanowire arrays are interconnected in the X-Y direction, but a nanowell/via array is isolated in X-Y direction so that, during cooling, the gas and/or liquid are contained in the well/via by capillary force and pressure control).Some embodiments of the present invention may include one, or more, of the following features, characteristics and/or advantages: (i) a bonding layer and a recess region constructed as a “built in” structure in a rigid cap piece that maintains an accurate separation gap between the MNSs and the upper surface of the semiconductor chip; and/or (ii) easy to control (or “tune”) the size of the gap, between the MNS layer and the upper surface of the semiconductor chip, in the range of a few microns to tens of microns. 
         [0025]      FIGS. 9A to 9H  respectively show seven (7) intermediate assemblies (assemblies  200   a,    200   b,    200   c,    200   d,    200   e,    200   f,    200   g  of, respectively  FIGS. 9A to 9G ) and one (1) final assembly (assembly  200   h  of  FIG. 9H ). These assemblies show a second example of a fabrication process according to the present disclosure called the “channel last,” MNSs first method. For pedagogical purposes, it is noted that the respective assemblies  200   a  to  200   g  do not necessarily represent an exhaustive list of assembly states during manufacture, but, rather, these assemblies were chosen to efficiently assist those of skill in the art to understand the devices and/or manufacturing processes of the present invention. The following paragraphs will describe the processes involved in transforming the starting assembly  200   a  to intermediate assembly  200   b,  intermediate assembly  200   b  to intermediate assembly  200   c,  intermediate assembly  200   c  to intermediate assembly  200   d,  and so on until the final assembly of  200   g  is attained for use as an embodiment of a GADLC IC device. 
         [0026]    As shown in  FIGS. 9A to 9H , the assemblies  200   a  to  200   h  collectively include: silicon cap layer (or, simply, “cap”)  202 ; bonding layer  204 ; rectangular hole  205 ; first photoresist layer  206 ; second photoresist layer  208 ; MNS masking region  213 ; MNS region (or nanowires/nanowells)  214 ; recesses  216 ; and channels  217 . 
         [0027]    As shown in  FIG. 9A , first intermediate assembly  200   a  is provided with bonding layer  204  overlaid on cap  202 . As in the previous fabrication embodiment, the bonding layer has a rectangular hole  205 . 
         [0028]    As manufacturing processes according to this embodiment of the present invention transform first intermediate assembly  200   a  (see  FIG. 9A ) to second intermediate assembly  200   b  ( FIG. 9B ): (i) photoresist layer  206  is overlaid over cap  202  and bonding layer  204  (for example, by spin coating); and (ii) photoresist layer  206  is patterned (for example, by litho-patterning) to include MNS masking region  213 . In order to proceed from second intermediate assembly  200   b  (see  FIG. 9B ) to third intermediate assembly  200   c  ( FIG. 9C ): (i) RIE is used to remove material from the non-masked portions in the central region of cap  202  in order to form MNS region (for example, nanowires)  214  of cap  202 ; and (ii) photoresist layer  206  is stripped away. Shape, diameter, and/or depth of the MNSs of MNS region  214  can be customized easily. Typically, characteristic length in the radial direction is tens of nanometers to a few microns. Depth lies between a couple of hundred nanometers to tens of microns. Cross-sectional shape of the MNSs can be annular, rectangular, etc. 
         [0029]    As manufacturing processes according to this embodiment of the present invention transform third intermediate assembly  200   c  (see  FIG. 9C ) to fourth intermediate assembly  200   d  ( FIG. 9D ): (i) a second photoresist layer  208  is laid on top of assembly  200   c;  and (ii) photoresist layer  208  is patterned to have five (5) circular holes (in various embodiments, this number of holes and resultant channels may be greater or smaller). 
         [0030]    As manufacturing processes according to this embodiment of the present invention transform fourth intermediate assembly  200   d  (see  FIG. 9D ) to fifth intermediate assembly  200   e  ( FIG. 9E ): (i) RIE is used to remove material from the non-masked portion MNS region  214  of cap  202  in order to remove the nanowires (or other MNS structures) of MNS region  214  in the shape of five (5) cylindrical recesses (also called “open areas”)  216 ; and (ii) second photoresist layer  208  is stripped away. Diameter(s) of the open areas in this example are on the order of tens of microns to several millimeters. 
         [0031]    As manufacturing processes according to this embodiment of the present invention transform fifth intermediate assembly  200   e  (see  FIG. 9E ) to sixth intermediate assembly  200   f  ( FIG. 9F ): (i) cap sub-assembly  202 ,  204  is flipped into position in horizontal plane alignment with chip  220 ; and (ii) the cap sub-assembly and the chip are moved into mutual contact so that bonding layer  204  bonds the cap sub-assembly to the chip to form intermediate assembly  200   f.  It is noted that a bonding layer can also be applied on the surface of the  220  substrate, with/without an opening/recess corresponding to  205  in the cap. As with the previous example fabrication process, discussed above, the second example fabrication process, now under discussion, can be performed at the wafer (with multiple chips) level, rather than at the single chip level, for example in a three dimensional integration (3Di) or packaging scenario. 
         [0032]    As manufacturing processes according to this embodiment of the present invention transform sixth intermediate assembly  200   f  (see  FIG. 9F ) to seventh intermediate assembly  200   g  ( FIG. 9G ) silicon cap layer  202  is subject to material removal to reduce its thickness. Wafer thinning can be done by grinding, wet etch, RIE, or a combination of the foregoing. The final thickness of the top wafer is on the order of tens of microns to a couple of hundreds of microns. Caps, according to various embodiments of the present invention, can be full thickness or intentionally thinned. The thinning process can be done by grinding, wet etching, or dry etching, or combined, and can be carried out before or after the bonding process. Also, a pre-thinned cap can be used, meaning the cap can also be thinned first and then patterned through the processes of intermediate assemblies  200   a - 200   e.    
         [0033]    As manufacturing processes according to this embodiment of the present invention transform seventh intermediate assembly  200   g  (see  FIG. 9G ) to final assembly  200   h  ( FIG. 9H ) five (5) channels  217  are opened by removing material from silicon cap layer  202 . As shown in  FIG. 9H , these five (5) channels are respectively aligned with the five (5) cylindrical recesses  216  so that GADLC gases and/or liquids can be communicated between the interior space of assembly  200   h  and the outside. In this example, open areas  216  have somewhat larger diameters than their respective channels  217 . This final interfacial structure between the two wafers and its enabled cooling function are different than conventional GADLC cooled chip structures. The surface of the device chip is usually capped (e.g., with NBLOK (that is dielectric cap material with a general formula of SiNxCyHz)). The silicon RIE process is selective to the capping material. 
         [0034]      FIGS. 10A to 10E  respectively show four (4) intermediate assemblies (assemblies  300   a,    300   b,    300   c,    300   d  respectively  FIGS. 10A to 10D ) and one (1) sub-assembly (assembly  300   e  of  FIG. 10E ). These assemblies show a third example of a fabrication process according to the present disclosure called the “channel last open areas first method.”). For pedagogical purposes, it is noted that the respective assemblies  300   a  to  300   d  do not represent an exhaustive list of assembly states during manufacture, but, rather, these assemblies were chosen to efficiently assist those of skill in the art to understand the devices and/or manufacturing processes of the present invention. The following paragraphs will describe the processes involved in transforming the starting assembly  300   a  to intermediate assembly  300   b,  intermediate assembly  300   b  to intermediate assembly  300   c,  and so on until the final assembly of  300   e  is attained for use as an embodiment of a GADLC IC device. 
         [0035]    As shown in  FIGS. 10A to 10E , assemblies  300   a  to  300   e  collectively include: silicon cap layer (or, simply, “cap”)  302 ; bonding layer  304 ; rectangular hole  305 ; first photoresist layer  306 ; second photoresist layer  308 ; MNS masking region  313 ; MNS region (or nanowires)  314 ; masking open areas  315 ; and recesses  316 . 
         [0036]    As shown in  FIG. 10A , first intermediate assembly  300   a  is provided with the bonding layer overlaid on cap  302 . As in the previous fabrication embodiments, the bonding layer has a rectangular hole  305 . 
         [0037]    As manufacturing processes according to this embodiment of the present invention transform first intermediate assembly  300   a  (see  FIG. 10A ) to second intermediate assembly  300   b  ( FIG. 10B ): (i) first photoresist layer  306  is overlaid over cap  302  and bonding layer  304 ; and (ii) photoresist layer  306  is patterned to include masking open areas  315 . 
         [0038]    As manufacturing processes according to this embodiment of the present invention transform second intermediate assembly  300   b  (see  FIG. 10B ) to third intermediate assembly  300   c  ( FIG. 10C ): (i) RIE is used to remove portions of cap material underlying masking open areas  315  in order to form cylindrical recesses  316 ; and (ii) first photoresist layer  306  is stripped away. 
         [0039]    As manufacturing processes according to this embodiment of the present invention transform third intermediate assembly  300   c  (see  FIG. 10C ) to fourth intermediate assembly  300   d  ( FIG. 10D ): (i) second photoresist layer  308  is laid over assembly  300   c;  and (ii) the second photoresist layer is patterned to make MNS masking region  313 . 
         [0040]    As manufacturing processes according to this embodiment of the present invention transform fourth intermediate assembly  300   d  (see  FIG. 10D ) to final assembly  300   e  ( FIG. 10E ): (i) RIE is used to form MNSs (for example, nanowires) in MNS region  314 ; and (ii) second photoresist layer  308  is stripped away. In this third example fabrication process, further processing is similar to what is shown and discussed, above, in connection with  FIGS. 9F to 9H  of the second example fabrication process. 
         [0041]      FIGS. 11A to 11G  respectively show six (6) intermediate assemblies (assemblies  400   a,    400   b,    400   c,    400   d,    400   e  and  400   f  respectively  FIGS. 11A to 11F ) and one (1) sub-assembly (assembly  400   g  of  FIG. 11G ). These assemblies show a fourth example of a fabrication process according to the present disclosure called the “channel first, MNSs last method.”). For pedagogical purposes, it is noted that the respective assemblies  400   a  to  400   f  do not represent an exhaustive list of assembly states during manufacture, but, rather, these assemblies were chosen to efficiently assist those of skill in the art to understand the devices and/or manufacturing processes of the present invention. The following paragraphs will describe the processes involved in transforming the starting assembly  400   a  to intermediate assembly  400   b,  intermediate assembly  400   b  to intermediate assembly  400   c,  intermediate assembly  400   c  to intermediate assembly  400   d,  and so on until the final assembly of  400   f  is attained for use as an embodiment of a GADLC IC device. 
         [0042]    As shown in  FIGS. 11A to 11G , assemblies  400   a  to  400   g  collectively include: silicon cap layer (or, simply, “cap”)  402 ; bonding layer  404 ; rectangular hole  405 ; first photoresist layer  406 ; second photoresist layer  408 ; channel masking region  413 ; channels  414 ; MNS masking region  415 ; and MNS region  416 . 
         [0043]    As shown in  FIG. 11A , first intermediate assembly  400   a  is provided with bonding layer  404  overlaid on cap  402 . As in the previous fabrication embodiments, the bonding layer has a rectangular hole  405 . 
         [0044]    As manufacturing processes according to this embodiment of the present invention transform first intermediate assembly  400   a  (see  FIG. 11A ) to second intermediate assembly  400   b  ( FIG. 11B ): (i) first photoresist layer  406  is overlaid over cap  402  and bonding layer  404 ; and (ii) first photoresist layer  406  is patterned to include channel masking region  413 . 
         [0045]    As manufacturing processes according to this embodiment of the present invention transform second intermediate assembly  400   b  (see  FIG. 11B ) to third intermediate assembly  400   c  ( FIG. 11C ): (i) RIE is used to remove portions of cap material underlying unmasked portions of channel masking region  413  in order to form channels  414 ; and (ii) first photoresist layer  406  is stripped away. In this step, channel diameter is on the order of tens of microns to a few millimeters, and depth is on the order of tens to hundreds of microns. The opening of the channel structure can be performed by RIE. 
         [0046]    As manufacturing processes according to this embodiment of the present invention transform third intermediate assembly  400   c  (see  FIG. 11C ) to fourth intermediate assembly  400   d  ( FIG. 11D ): (i) second photoresist layer  408  is laid over assembly  400   c;  and (ii) the second photoresist layer is patterned to make MNS masking region  415 . 
         [0047]    As manufacturing processes according to this embodiment of the present invention transform fourth intermediate assembly  400   d  (see  FIG. 11D ) to fifth intermediate assembly  400   e  ( FIG. 11E ): (i) RIE is used to form MNSs (for example, nanowires) in MNS region  416 ; and (ii) second photoresist layer  408  is stripped away. 
         [0048]    As shown in  FIGS. 11F to 11G , cap sub-assembly  402 ,  404  is flipped onto chip  420  (or larger chip bearing wafer (not shown)), bonded to it by the bonding layer and then subject to material removal from the cap so that channels  414  extend from the interior open space to the exterior surface of cap  402 . 
         [0049]      FIGS. 12A to 12E  respectively show four (4) intermediate assemblies (assemblies  500   a,    500   b,    500   c  and  500   d  respectively of  FIGS. 12A to 12D ) and one (1) final sub-assembly (assembly  500   e  of  FIG. 12E ). These assemblies show a fifth example of a fabrication process according to the present disclosure called the “MNSs first method, channels last (without open areas) method.”). For pedagogical purposes, it is noted that the respective assemblies  500   a  to  500   d  do not necessarily represent an exhaustive list of assembly states during manufacture, but, rather, these assemblies were chosen to efficiently assist those of skill in the art to understand the devices and/or manufacturing processes of the present invention. The following paragraphs will describe the processes involved in transforming the starting assembly  500   a  to intermediate assembly  500   b,  intermediate assembly  500   b  to intermediate assembly  500   c,  and so on until the final assembly of  500   d  is attained for use as an embodiment of a GADLC IC device. 
         [0050]    As shown in  FIGS. 12A to 12E , assemblies  400   a  to  400   g  collectively include: cap  502 ; bonding layer  504 ; rectangular hole  505 ; first photoresist layer  506 ; second photoresist layer  508 ; MNS masking region  513 ; MNS region  514 ; channel masking region  515 ; and channels  516 . 
         [0051]    As shown in  FIG. 12A , first intermediate assembly  500   a  is provided with bonding layer  504  overlaid on cap  502 . As in the previous fabrication embodiments, the bonding layer has a rectangular hole  505 . 
         [0052]    As manufacturing processes according to this embodiment of the present invention transform first intermediate assembly  500   a  (see  FIG. 12A ) to second intermediate assembly  500   b  ( FIG. 12B ): (i) first photoresist layer  506  is overlaid over cap  502  and bonding layer  504 ; and (ii) first photoresist layer  506  is patterned to include MNS masking region  513 . 
         [0053]    As manufacturing processes according to this embodiment of the present invention transform second intermediate assembly  500   b  (see  FIG. 12B ) to third intermediate assembly  500   c  ( FIG. 12C ): (i) RIE is used to remove portions of cap material underlying unmasked portions of MNS masking region  513  in order to form MNS region  514 ; and (ii) first photoresist layer  506  is stripped away. 
         [0054]    As manufacturing processes according to this embodiment of the present invention transform third intermediate assembly  500   c  (see  FIG. 12C ) to fourth intermediate assembly  500   d  ( FIG. 12D ): (i) second photoresist layer  508  is laid over assembly  500   c;  and (ii) the second photoresist layer is patterned to make channel masking region  515 . 
         [0055]    As manufacturing processes according to this embodiment of the present invention transform fourth intermediate assembly  500   d  (see  FIG. 12D ) to fifth intermediate assembly  500   e  ( FIG. 12E ): (i) RIE is used to form channels  516 ; and (ii) second photoresist layer  508  is stripped away. Subsequent processing (not shown in the Figures) is similar to that discussed above in connection with  FIGS. 11F and 11G  of the fourth example fabrication process. 
         [0056]    The following paragraphs set forth some definitions. 
         [0057]    Present invention: should not be taken as an absolute indication that the subject matter described by the term “present invention” is covered by either the claims as they are filed, or by the claims that may eventually issue after patent prosecution; while the term “present invention” is used to help the reader to get a general feel for which disclosures herein that are believed as maybe being new, this understanding, as indicated by use of the term “present invention,” is tentative and provisional and subject to change over the course of patent prosecution as relevant information is developed and as the claims are potentially amended. 
         [0058]    Embodiment: see definition of “present invention” above—similar cautions apply to the term “embodiment.” 
         [0059]    and/or: inclusive or; for example, A, B “and/or” C means that at least one of A or B or C is true and applicable. 
         [0060]    Micro-structure: a structure having formed therein pores, gaps and or interstitial spaces equal to or less than 100 micrometers but more than 100 nanometers; for example, a set of microwires arranged in a regular array and spaced at a center-to-center pitch of 100 micrometers would be an example (although not necessarily a preferred example) of a “micro-structure.” 
         [0061]    Nano-structure: a structure having formed therein pores, gaps and or interstitial spaces equal to or less than 100 nanometers; for example, a set of nanowires arranged in a regular array and spaced at a center-to-center pitch of 100 nanometers would be an example (although not necessarily a preferred example) of a “nano-structure.” 
         [0062]    Small-scale-structure: a micro-structure or nano-structure. 
         [0063]    Rigid: at least substantially as rigid as the least rigid of the following: silicon, SixAly, SiC, SixNy, quartz, AlN, or Al 2 O 3 ; more rigid than a polymer membrane. 
         [0064]    Surface: not limited to planar, continuous and/or smooth surfaces.