Abstract:
High-voltage n-channel and p-channel MOS transistors are formed on an insulated wafer, such as a silicon-on-insulator wafer. The heavily-doped area of the drain region is separated from the channel region by a lighter-doped area of the drain region which has a lateral width which is substantially greater than the lateral width of the sidewall spacers formed adjacent to the gates of the spacers.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to high-voltage MOS transistors and, more particularly, to a high-voltage MOS transistor which is formed on a silicon on insulator (SOI) wafer. 
     2. Description of the Related Art 
     A MOS transistor is a device that controls a channel current, which flows from the drain to the source of the transistor, in response to a voltage applied to the gate of the transistor. As a result of this ability to control the channel current, MOS transistors are commonly used as voltage-controlled switches where the transistor provides a very-low resistance current path when turned on, and a very-high resistance current path when turned off. 
     FIGS. 1A-1B show cross-sectional and schematic diagrams, respectively, that illustrate a conventional n-channel MOS transistor  100 . As shown in FIGS. 1A-1B, transistor  100  includes spaced-apart n+ source and drain regions  114  and  116  which are formed in a p-type substrate  112 , and a channel region  118  which is defined between source and drain regions  114  and  116 . In addition, transistor  100  also includes a dielectric layer  120  which is formed over channel region  118 , and a gate  122  which is formed over dielectric layer  120 . 
     In operation, transistor  100  turns on when the drain-to-source voltage V DS  is positive, the drain-to-substrate junction is reverse-biased, and the gate-to-source voltage V GS  is equal to or greater than the threshold voltage V T . Often, the positive drain-to-source voltage V DS  and the reverse-biased drain-to-substrate junction are set by tying substrate  112  and source region  114  to ground, and applying a positive voltage to drain region  116 . 
     With source region  114  tied to ground, a gate-to-source voltage V GS  which is greater than the threshold voltage V T  may be obtained by simply applying a voltage to gate  122  which is equal to or greater than the threshold voltage V T . When these conditions are met and transistor  100  turns on, a channel current I C  flows from drain region  116  to source region  114 . On the other hand, to turn transistor  100  off, and stop the channel current I C  from flowing, the voltage on gate  122  may be simply lowered so that the gate voltage is less than the threshold voltage V T . 
     MOS transistors may be used in both low-voltage and high-voltage environments. High-voltage MOS transistors, however, must be able to withstand significantly larger drain voltages without inducing avalanche breakdown. 
     Avalanche breakdown occurs when the voltage on the drain region is so large that the electric field across the reverse-biased drain-to-substrate junction accelerates thermally-generated electron-hole pairs at or near the junction. The accelerated electron-hole pairs have ionizing collisions with the lattice which form additional electron-hole pairs that quickly multiply to form a large avalanche current. 
     This large avalanche current, in turn, has numerous detrimental effects on the operation of a high-voltage transistor. 
     One technique for reducing the strength of the junction electric field of a high-voltage transistor is to surround the drain region with a lightly-doped region of the same conductivity type. FIG. 2 shows a cross-sectional diagram of a high-voltage n-channel MOS transistor  200  that illustrates this technique. 
     As shown in FIG. 2, high-voltage transistor  200 , like transistor  100 , has spaced-apart source and drain regions  214  and  216  which are formed in a p-type substrate  212 , and a channel region  218  which is defined between source and drain regions  214  and  216 . In addition, transistor  200  also has a dielectric layer  220  which is formed over channel region  218 , and a gate  222  which is formed over dielectric layer  220 . 
     As further shown in FIG. 2, transistor  200  principally differs from transistor  100  in that drain region  216  includes a n+ region  216 A and a n− region  216 B which surrounds n+ region  216 A. The purpose of n− region  216 B, which is formed as an n− well, is to absorb some of the potential of n+ region  216 A, and thereby reduce the strength of the junction electric field. 
     High-voltage MOS transistors are typically used in output circuits that often require both high-voltage n and p-channel transistors. FIG. 3 shows a cross-sectional diagram of a portion of an output circuit  300  that illustrates the use of both high-voltage n-channel and p-channel MOS transistors. 
     As shown in FIG. 3, circuit  300  includes high-voltage n-channel transistor  200 , and a high-voltage p-channel transistor  310 . P-channel transistor  310  includes spaced-apart p+ source and drain regions  314  and  316  which are formed in a deep n-well  312  which, in turn, is formed in p-type substrate  212 . Further, drain region  316  of p-channel transistor  310  includes a p+ region  316 A and a p− region  316 B which is formed from a p-well. 
     In addition, transistor  310  also includes a channel region  318  which is defined between source and drain regions  314  and  316 , a dielectric layer  320  which is formed over channel region  318 , and a gate  322  which is formed over dielectric layer  320 . 
     One problem with output circuit  300 , however, is that transistor  310  can not be formed with a standard CMOS process because conventional CMOS logic transistors do not require a deep well structure, such as deep n-well  312 . In addition, conventional bulk CMOS wafers are typically unable to accommodate a deep well structure. 
     As a result, high-voltage n-channel and p-channel transistors can not be incorporated onto a chip having CMOS logic circuitry without using non-standard bulk wafers, and altering the fabrication process. Both of these steps, however, add additional cost and complexity to the process and the finished result. 
     Thus, there is a need for n-channel and p-channel high-voltage MOS transistors which can be incorporated into a standard CMOS process. 
     SUMMARY OF THE INVENTION 
     Conventionally, high-voltage n-channel and p-channel MOS transistors can not be formed with a standard CMOS fabrication process because the high-voltage transistors require a deep well structure which, in turn, requires additional masking steps. The present invention allows both n-channel and p-channel high-voltage MOS transistors to be formed with a standard CMOS process when the CMOS logic transistors are formed on an insulated wafer, such as a silicon on insulator semiconductor wafer. 
     In accordance with the present invention, a semiconductor device comprises a semiconductor wafer and a high-voltage transistor. The semiconductor wafer includes a substrate, a first layer of insulation material which is formed on the substrate, and a layer of semiconductor material which is formed on the layer of insulation material. 
     The high-voltage transistor includes spaced-apart source and drain regions of a first conductivity type which are formed in the semiconductor material. The drain region has a first area with a first dopant concentration and a second area with a second dopant concentration which is less than the first dopant concentration. In addition, the second area contacts the first layer of insulation material. 
     The high-voltage transistor also includes a first region which is formed in the semiconductor material between the source and drain regions, a second layer of insulation material which is formed on the semiconductor material, and a gate which is formed on the second layer of insulation material over the first region and a portion of the second area. 
     The high-voltage transistor further includes spacers which are formed to contact the sidewalls of the gate. The spacers have a lateral width which is substantially smaller than the lateral width of the second area. 
     A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A-1B are cross-sectional and schematic diagrams, respectively, illustrating a conventional n-channel MOS transistor  100 . 
     FIG. 2 is a cross-sectional diagram illustrating a conventional high-voltage n-channel MOS transistor  200 . 
     FIG. 3 is a cross-sectional diagram of a portion of a conventional output circuit  300  illustrating the use of both high-voltage n-channel and p-channel MOS transistors. 
     FIG. 4A is a plan view illustrating a semiconductor device  400  in accordance with the present invention. 
     FIG. 4B is a cross-sectional view taken along line  4 B— 4 B of FIG.  4 A. 
     FIG. 4C is a cross-sectional view taken along line  4 C— 4 C of FIG.  4 A. 
     FIG. 5 is a cross-sectional view illustrating a conventional n-channel MOS transistor  500  which is formed on a semiconductor wafer, such as wafer  410 . 
     FIG. 6 is a cross-sectional view illustrating a high-voltage n-channel MOS transistor  600  in accordance with a first alternate embodiment of the present invention. 
     FIG. 7A is a plan view illustrating a semiconductor device  700  in accordance with the present invention. 
     FIG. 7B is a cross-sectional view taken along line  7 B— 7 B of FIG.  7 A. 
     FIG. 7C is a cross-sectional view taken along line  7 C— 7 C of FIG.  7 A. 
     FIG. 8 is a cross-sectional view illustrating a conventional p-channel MOS transistor  800  which is formed on a semiconductor wafer, such as wafer  410 . 
     FIG. 9 is a cross-sectional view illustrating a high-voltage p-channel MOS transistor  900  in accordance with a second alternate embodiment of the present invention. 
     FIG. 10 is a schematic diagram of a level shifter circuit  1000  illustrating how devices  400  and  700  can be used to address the 3V/5V tolerance issue in accordance with the present invention. 
     FIG. 11 is a schematic diagram of an output driver circuit  1100  illustrating another example of how devices  400  and  700  can be used to address the 3V/5V tolerance issue in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 4A shows a plan view that illustrates a semiconductor device  400  in accordance with the present invention. FIG. 4B shows a cross-sectional view taken along line  4 B 13   4 B of FIG. 4A, while FIG. 4C shows a cross-sectional view taken along line  4 C— 4 C of FIG.  4 A. 
     As shown in FIGS. 4A-4C, device  400  includes a semiconductor wafer  410  and a high-voltage n-channel MOS transistor  420 . Wafer  410  includes a substrate  412 , a layer of insulation material  414  which is formed on substrate  412 , and a layer of semiconductor material  416  which is formed on insulation layer  414 . Insulation layer  414  may be formed, for example, from silicon dioxide, while semiconductor layer  416  may be formed, for example, from single-crystal silicon. 
     Transistor  420 , in turn, includes spaced-apart source and drain regions  422  and  424  which are formed in semiconductor layer  416 , and a p-well region  430  which is formed in semiconductor layer  416  between source and drain regions  422  and  424 . 
     Source region  422  includes a n+ region  422 A and a n− region  422 B, while drain region  424  includes a n+ region  424 A and a n− region  424 B. As described in greater detail below, n− region  424 B has a higher dopant concentration than does n− region  422 B. 
     In addition, transistor  420  also includes a layer of insulation material  432  which is formed on semiconductor layer  416 , and a gate  434  which is formed on insulation layer  432  over the top surface of p-well region  430  and a portion of n− region  424 B. Gate  434  may be formed, for example, from aluminum, doped polysilicon, or doped polysilicon with an overlying layer of metal silicide, while insulation layer  432  may be formed, for example, from gate oxide. 
     Transistor  420  further includes spacers  436  (not shown in FIG. 4A) which are formed to contact the sidewalls of insulation layer  432  and gate  434 , and a p+ contact region  440  which is formed in semiconductor material  416  adjacent to source region  422  and p-well region  430 . 
     Contact region  440  allows a predefined voltage (such as the source voltage) to be placed on p-well region  430 , while a plurality of contacts  442 ,  444 ,  446 , and  448  are used to connect p+ region  440 , source region  422 , drain region  424 , and gate  434 , respectively, to the nodes of a circuit. 
     One of the advantages of the present invention is that, when CMOS logic transistors are formed on a wafer like wafer  410 , transistor  420  may be formed at the same time without any additional masking steps. In the present invention, n− region  424 B and p-well region  430  are formed at the same time that the n-and p− wells or tubs of a CMOS logic device are formed. (The top surface of p-well region  430  functions as the channel of transistor  420 , and is approximately 2× longer than the minimum length due to the requirement for overlay tolerances in the channel). 
     In addition, source region  422 B is formed at the same time that the LDD structures of the CMOS device are formed, and source and drain regions  422 A and  424 A are formed at the same time that the source and drain regions of the CMOS logic device are formed. Since n− region  424 B is formed at the same time that the wells or tubs of the CMOS logic device are formed, n− region  424 B has a dopant concentration which is higher than the dopant concentration of n− region  422 B. 
     FIG. 5 shows a cross-sectional view that illustrates a conventional n-channel MOS transistor  500  which is formed on a semiconductor wafer, such as wafer  410 . As shown in FIG. 5, transistor  500  includes spaced-apart source and drain regions  522  and  524  which are formed in a semiconductor layer, and a p-type region  530  which is formed in the semiconductor layer between source and drain regions  522  and  524 . 
     Source region  522  includes a n+ region  522 A and a n− region  522 B, while drain region  524  includes a n+ region  524 A and a n− region  524 B. N− regions  522 B and  524 B are lightly-doped-drain (LDD) regions which have the same dopant concentration. 
     In addition, prior-art transistor  500  also includes a layer of insulation material  532  which is formed on the semiconductor layer, a gate  534  which is formed on insulation layer  532  over p-type region  530  and a portion of LDD regions  522 B and  524 B, and spacers  536  which are formed to contact the sidewalls of insulation layer  532  and gate  534 . 
     Comparing transistor  420  of the present invention with prior-art transistor  500  illustrates several differences. First, the lateral width W 1  of LDD regions  522 B and  524 B is approximately as wide as the lateral width W 2  of spacers  536 . This is because LDD regions  522 B and  524 B are typically formed in a self-aligned implant that uses gate  534  (or gate  534  and an overlying mask) as the mask for the LDD implant, while n+ source and drain regions  522 A and  524 A are formed in a subsequent self-aligned implant that uses spacers  536  as the mask for the implant. 
     In contrast, as shown in FIG. 4B, the lateral width W 3  of n− region  424 B is substantially larger than the lateral width W 4  of spacers  436 . This is because n− region  424 B and p-well region  430  are formed prior to the formation of gate  434 , during the same time that the n− and p− wells or tubs of the CMOS logic device are formed. 
     The advantage of forming n− region  424 B to have a lateral width which is substantially greater than the lateral width of the spacers is that the maximum drain voltage which can be handled by transistor  420  is substantially increased. 
     Another difference between transistor  420  of the present invention and prior-art transistor  500  is that LDD regions  522 B and  524 B do not extend down to contact insulation layer  414 . On the other hand, since n− region  424 B is formed during the formation of the CMOS well implants, n− region  424 B extends down and contacts insulation layer  414 . 
     The advantage of forming n− region  424 B to contact insulation layer  414  is that the voltage along the entire drain junction is reduced, thereby preventing avalanche breakdown from occuring anywhere along the entire drain junction. 
     A further difference is that since n− region  424 B is formed during the CMOS well implant step rather than during the LDD implant step, the dopant concentration of n− region  424 B is greater than the dopant concentration of LDD regions  522 A and  524 A (and LDD region  422 B). 
     Although transistor  420  may be formed at the same time that CMOS logic transistors are formed without any additional masking steps, the maximum drain voltage which can be handled by transistor  420  can be further increased by utilizing additional masking steps to form a thicker layer of gate oxide, or to space drain region  424 A apart from spacer  436 . 
     FIG. 6 shows a cross-sectional view that illustrates a high-voltage n-channel MOS transistor  600  in accordance with a first alternate embodiment of the present invention. As shown in FIG. 6, transistor  600  is the same as transistor  420  except that drain region  424 A of transistor  600  is laterally spaced-apart from the bottom edge of spacer  436 . 
     In addition to n-channel MOS transistors, p-channel MOS transistors may also be formed in semiconductor layer  416  by simply reversing the conductivity types of the different regions. FIG. 7A shows a plan view that illustrates a semiconductor device  700  in accordance with the present invention. FIG. 7B shows a cross-sectional view taken along line  7 B— 7 B of FIG. 7A, while FIG. 7C shows a cross-sectional view taken along line  7 C— 7 C of FIG.  7 A. 
     As shown in FIGS. 7A-7C, device  700  includes semiconductor wafer  410 , and a p-channel transistor  720 . Transistor  720 , in turn, includes spaced-apart source and drain regions  722  and  724  which are formed in semiconductor layer  416 , and a n-well region  730  which is formed in semiconductor layer  416  between source and drain regions  722  and  724 . 
     Source region  722  includes a p+ region  722 A and a p− region  722 B, while drain region  724  includes a p+ region  724 A and a p− region  724 B. As described in greater detail below, p− region  724 B has a higher dopant concentration than does p− region  722 B. 
     In addition, transistor  720  also includes an insulation layer  732  which is formed on semiconductor layer  416 , and a gate  734  which is formed on insulation layer  732  over the top surface of n-well region  730  and a portion of p- region  724 B. Gate  734  may be formed from the same materials as gate  434 . 
     Transistor  720  further includes spacers  736  (not shown in FIG. 7A) which are formed to contact the sidewalls of insulation layer  732  and gate  734 , and a n+ contact region  740  which is formed in semiconductor material  416  adjacent to source region  722  and n-well region  730 . 
     Contact region  740  allows a predefined voltage (such as the source voltage) to be placed on n-well region  730 , while a plurality of contacts  742 ,  744 ,  746 , and  748  are used to connect n+ region  740 , source region  722 , drain region  724 , and gate  734 , respectively, to the nodes of a circuit. 
     As with transistor  420 , transistor  720  may also be formed at the same time that CMOS logic transistors are formed without any additional masking steps when the CMOS logic transistors are formed on a wafer like wafer  410 . P− region  724 B and n-well region  730  are formed at the same time that the n-and p− wells or tubs of a CMOS logic device are formed. (The top surface of n-well region  730  functions as the channel of transistor  720 , and is approximately 2× longer than the minimum length due to the requirement for overlay tolerances in the channel). 
     In addition, source region  722 B is formed at the same time that the LDD structures of the CMOS device are formed, and source and drain regions  722 A and  724 A are formed at the same time that the source and drain regions of the CMOS logic device are formed. Since p− region  724 B is formed at the same time that the wells or tubs of the CMOS logic device are formed, p− region  724 B has a dopant concentration which is higher than the dopant concentration of p− region  722 B. 
     FIG. 8 shows a cross-sectional view that illustrates a conventional p-channel MOS transistor  800  which is formed on a semiconductor wafer, such as wafer  410 . As shown in FIG. 8, transistor  800  includes spaced-apart source and drain regions  822  and  824  which are formed in a semiconductor layer, and a n-type region  830  which is formed in the semiconductor layer between source and drain regions  822  and  824 . 
     Source region  822  includes a p+ region  822 A and a p− region  822 B, while drain region  824  includes a p+ region  824 A and a p− region  824 B. P− regions  822 B and  824 B are lightly-doped-drain (LDD) regions which have the same dopant concentration. 
     In addition, prior-art transistor  800  also includes a layer of insulation material  832  which is formed on the semiconductor layer, a gate  834  which is formed on insulation layer  832  over n-type region  830  and a portion of LDD regions  822 B and  824 B, and spacers  836  which are formed to contact insulation layer  832  and the sidewalls of gate  834 . 
     As with transistor  420 , transistor  720  differs from prior-art transistor  800  in that the lateral width W 5  of p− region  724 B (see FIG. 7B) is substantially larger than the lateral width W 6  of spacer  736 . In addition, p− region  724 B extends down and contacts insulation layer  414 , while LDD regions  822 B and  824 B of transistor  800  do not extend down to contact insulation layer  414 . Further, the doping concentration of p− region  724 B is greater than the doping concentration of LDD regions  822 B and  824 B (and LDD region  722 B). 
     In addition, transistor  720 , like transistor  420 , may be formed with additional masking steps to form a thicker layer of gate oxide, or to laterally space drain region  724 A apart from spacer  736 , thereby increasing the maximum drain voltage that can be handled by transistor  720 . 
     FIG. 9 shows a cross-sectional view that illustrates a high-voltage p-channel MOS transistor  900  in accordance with a second alternate embodiment of the present invention. As shown in FIG. 9, transistor  900  is the same as transistor  720  except that drain region  724 A of transistor  900  is laterally spaced-apart from the bottom edge of spacer  736 . 
     Another advantage of the present invention is that high-voltage transistors  420 / 600  and  720 / 900  resolve the historical requirement of 5V tolerance for low-voltage, e.g., 3.3V, CMOS circuits. FIG. 10 shows a schematic diagram of a level shifter circuit  1000  that illustrates how devices  400  and  700  can be used to address the 3V/5V tolerance issue. Access to a 5V supply is assumed as 5V must be available in any situation where 5V tolerance is required. 
     As shown in FIG. 10, circuit  1000  includes a high-voltage p-channel transistor Q 1  which has a source connected to a 5V line, a drain connected to an output node N OUT , and a gate; and a high-voltage p-channel transistor Q 2  which has a source connected to the 5V line, a drain, and a gate connected to the gate of transistor Q 1  and the drain of transistor Q 2  as a current mirror. 
     In addition, circuit  1000  also includes a high-voltage n-channel transistor Q 3  which has a source connected to ground, a drain connected to output node N OUT , and a gate; and a high-voltage n-channel transistor Q 4  which has a source connected to ground, a drain connected to the drain of transistor Q 2 , and a gate. Transistors Q 1 , Q 2 , Q 3 , and Q 4  are formed in accordance with the present invention. 
     Further, circuit  1000  additionally includes an inverter  1010  which has an input connected to receive a logic level signal and to the gate of transistor Q 3 , and an output that is connected to the gate of transistor Q 4 . 
     In operation, when the logic level signal is in a first logic state, transistor Q 3  is turned off, while transistors Q 1 , Q 2 , and Q 4  are turned on. Transistor Q 1  mirrors the current sourced by transistor Q 2 , thereby driving current into output node N OUT  to charge up output node N OUT  to 5V rather than 3.3V. 
     On the other hand, when the logic level signal is in a second logic state, transistors Q 1 , Q 2 , and Q 4  are turned off, while transistor Q 3  is turned on. When transistor Q 3  turns on, transistor Q 3  sinks current from output node N OUT . 
     One of the advantages of circuit  1000  is that, although large gate-to-source voltages V GS  can not be used with transistors Q 1 , Q 2 , Q 3 , and Q 4  without breaking down the gate oxide, extremely large voltages may be placed on the drains as the breakdown voltages of transistors Q 1 , Q 2 , Q 3 , and Q 4 , particularly those based on transistors  600  and  900 , are extremely large. 
     FIG. 11 shows a schematic diagram of an output driver circuit  1100  that illustrates another example of how devices  400  and  700  can be used to address the 3V/5V tolerance issue. Output driver circuit  1100  may be, for example, an RS232 driver circuit. 
     As shown in FIG. 11, circuit  1100  includes a high-voltage p-channel transistor Q 1  which has a source connected to n-well region  730  and a positive voltage V+ which is greater than the internal supply, a drain connected to an output node N OUT , and a gate; and a high-voltage n-channel transistor Q 2  which has a source connected to p-well region  430  and a negative voltage V− which is less than ground, a drain connected to output node N OUT , and a gate. 
     Further, circuit  1100  additionally includes a level shift circuit  1110  which has an output connected to the gate of transistor Q 1 , an output connected to the gate of transistor Q 2 , and an input, and an inverter  1120  which has an input and an output that is connected to the input of level shift circuit  1110 . 
     In operation, when the logic level signal is in a first logic state, transistor Q 1  is turned on, driving the voltage on the output node N OUT  up to the positive voltage V+, while transistor Q 2  is turned off. When the logic level signal is in a second logic state, transistor Q 1  is turned off, while transistor Q 2  is turned on, pulling the output node N OUT  down to the negative voltage V−. 
     One of the advantages of circuit  1100  is that a connection can be made between n-well region  730  and source  722  of transistor  720 , and between p-well region  430  and source  422  of transistor  420  without interfering with the body potential of the internal circuitry, as is normally the case for RS232 driver products. 
     It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.