Abstract:
A second semiconductor chip and a junction member are mounted on a first semiconductor chip formed with a plurality of first pads on a surface thereof. A resin encapsulating body is provided which seals the first semiconductor chip, the second semiconductor chip and the junction member. The second semiconductor chip includes a plurality of second pads arranged in a central part thereof. The junction member includes first junction pads, second junction pads and connecting portions which connect the first junction pads and the second junction pads respectively. Electrical connections of the second semiconductor chip from the second pads include connections to connecting terminals and connections to the connecting terminals or the first semiconductor chip from the second junction pads via the first junction pads.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a multichip package (hereinafter abbreviated as “MCP”) wherein a plurality of semiconductor chips are mounted in one package, and particularly to an MCP with center-pad type semiconductor chips mounted therein.  
         [0003]     2. Description of the Related Art  
         [0004]     There has recently been increasingly demand for a size reduction of a semiconductor device with a request for miniaturization of electronic equipment. As one method for realizing the miniaturization of the semiconductor device, there has been proposed a semiconductor device having a multichip package (MCP) structure wherein a plurality of semiconductor chips are mounted in one package. Among others, a package with center pad type semiconductor chips mounted therein becomes a familiar sight on a DRAM (Dynamic Random Access Memory) or the like. The center pad type semiconductor chip is extremely advantageous in view of its size reduction and increase in capacity in that the area of the semiconductor chip occupied in an encapsulating resin is large as compared with a semiconductor chip having pads disposed therearound. The above-described contents have been described in the following patent document 1, for example.  
         [0005]     Patent Document 1  
         [0006]     Japanese Unexamined Patent Publication No. 2002-093993  
         [0007]     However, although the center pad type semiconductor chip is advantageous in view of its size reduction and increase in capacity as described even in the patent document 1, it is not possible to avoid an increase in the distance from each of pads to its corresponding inner lead upon wire bonding since the pads are placed in the center of the semiconductor chip. A problem arises in that with an increase in wire length, a short occurs due to wire&#39;s contact with a chip end or a short occurs between adjacent wires upon resin sealing.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention has been made to solve the foregoing problems. Therefore, the present invention aims to provide a junction member capable of keeping a wire length short and providing high yields and a multichip package using the junction member, while serving as the multichip package with the center pad type semiconductor chips mounted therein.  
         [0009]     According to one aspect of the present invention, for achieving the above object, there is provided a multichip package, comprising: 
        a first semiconductor chip formed with a plurality of first pads on a surface thereof;     a second semiconductor chip;     a junction member; and     a resin encapsulating body which seals the first semiconductor chip, the second semiconductor chip and the junction member,     the second semiconductor chip and the junction member being mounted on the first semiconductor chip,     wherein the second semiconductor chip includes a plurality of second pads arranged in a central part thereof,     wherein the junction member includes first junction pads, second junction pads and connecting portions which connect the first junction pads and the second junction pads respectively, and     wherein electrical connections of the second semiconductor chip from the second pads include connections to connecting terminals and connections to the connecting terminals or the first semiconductor chip from the second junction pads via the first junction pads.        
 
         [0018]     According to another aspect of the present invention, for achieving the above object, there is provided a rectangular junction member which transfers electric signals of a semiconductor chip having a circuit function to connecting terminals respectively, comprising: 
        a plurality of junction pads formed on a substrate; and     pad connecting portions that connect the junction pads adjacent to one another.        
 
         [0021]     In the present invention, the length of each wire can be shortened because the multichip package is configured using the junction member. It is also possible to reduce a short to a chip edge and a short between the wires at resin encapsulation due to sagging of the wire. Sine the previous junction member is configured so as to connect the plurality of junction pads by their corresponding pad connecting portions, junction members of various sizes can be fabricated. A junction member can be realized which adapts to combinations of various chip sizes. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:  
         [0023]      FIG. 1  is a cross-sectional view of a multichip package according to a first embodiment of the present invention;  
         [0024]      FIG. 2  is a top view of the multichip package according to the first embodiment of the present invention;  
         [0025]      FIG. 3  is a top view of a junction member according to a second embodiment of the present invention;  
         [0026]      FIG. 4 ( a ) is a top view of a portion A of the junction member according to the second embodiment of the present invention shown in  FIG. 3 , and  FIG. 4 ( b ) is a cross-sectional view taken along line B-B, of the junction member according to the second embodiment of the present invention;  
         [0027]      FIG. 5  is a cross-sectional view at wire bonging, of the portion A of the junction member according to the second embodiment of the present invention shown in  FIG. 3 ;  
         [0028]      FIG. 6  is a top view showing positions at the cutting of the junction member according to the second embodiment of the present invention shown in  FIG. 3 ;  
         [0029]      FIG. 7 ( a ) is a top view of a junction member according to a third embodiment of the present invention, and  FIG. 7 ( b ) is an enlarged view of a portion B of the junction member according to the third embodiment of the present invention;  
         [0030]      FIG. 8  is a top view showing positions at the cutting of the junction member according to the third embodiment shown in  FIG. 7 ; and  
         [0031]      FIG. 9  is a wired example of the junction member according to the third embodiment shown in  FIG. 7 .  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0032]     Preferred embodiments of the present invention will hereinafter be described with reference to the accompanying drawings.  
       First Embodiment  
       [0033]      FIG. 1  is a cross-sectional view showing a multichip package according to a first embodiment of the present invention.  FIG. 2  is a top view illustrating the multichip package according to the first embodiment of the present invention.  
         [0034]     A structure of the multichip package  100  shown in  FIGS. 1 and 2  will first be explained. A first semiconductor element  23  is bonded onto a die pad  25  by a first adhesive agent  24 . A second semiconductor element  27  is bonded onto the first semiconductor element  23  by a second adhesive agent  26 . A junction member  29  is adhered onto the first semiconductor element  23  by a third adhesive agent  28 . First pads  30  are formed over the first semiconductor element  23 . Second pads  22  are formed substantially in the center on the second semiconductor element  27 . Junction pads  2  and pad connecting portions  3  that electrically connect between the junction pads  2  are formed on the junction member  29 . The second semiconductor element  27  is bonded onto the first semiconductor element  23  in such a manner that the distance L 9  between the end of the second semiconductor element  27  and each of the first pads  30  ranges from approximately 0.2 to 1.0 mm. The junction member  29  is bonded onto the first semiconductor element  23  in such a manner that the distance L 10  between the end of the second semiconductor element  27  and the end of the junction member  29  ranges from approximately 0.2 to 1.0 mm and the distance L 11  between the end of the junction member  29  and each of the first pads  30  ranges from approximately 0.4 to 1.0 mm.  
         [0035]     The first pads  30  and lead frame terminals  21  are respectively electrically connected to one another by first metal wires  31 . The second pads  22  and lead frame terminals  21  are respectively electrically connected to one another by second metal wires  32 . The second pads  22  and the junction pads  2  are respectively electrically connected to one another by third metal wires  33 . The junction pads  2  and the first pads  30  are respectively electrically connected to one another by fourth metal wires  34 . Although the lead frame terminals  21  are illustrated by way of example in the present embodiment, any one may be used if connecting terminals are taken. It is needless to say that no limitation is imposed on the lead frame terminals  21 .  
         [0036]     In the present embodiment, the junction member  29  comprises the junction pads  2  and the pad connecting portions  3 . Patterning for forming each circuit is not effected on the junction member  29 . The junction member  29  has the function of bypassing electric signals sent from the second semiconductor element  27  to their corresponding first pads  30  of the first semiconductor element  23 . Also the junction member  29  has a thickness equal to or larger than that of the second semiconductor element  27 . The first semiconductor element  23 , the second semiconductor element  27  and the junction member  29  are sealed with a mold resin.  
         [0037]     The multichip package  100  according to the first embodiment of the present invention makes it possible to cause the second semiconductor element  27  to approach the first pads  30  by having the above configuration. Owing to the above configuration, the distance from each of the second pads  22  to the end of the second semiconductor element  27  can be set to more than or equal to ¾ of the distance between the first pad and the second pad. Thus, the second metal wires  32  can be kept short, thereby preventing deformation of each wire upon sealing by the mold resin  35 . It is also possible to prevent shorts between the second metal wires  32 .  
         [0038]     Owing to the mounting of the junction member  29 , the direct electrical connections of the second pads  22  to the first pads  30  are avoided so that the third metal wires  33  can be held to 3 mm or less. Since the thickness of the junction member  29  is set equal to or greater than that of the semiconductor element  27 , short-circuiting of the third metal wires  33  to the end of the second semiconductor element  27  can be prevented.  
       Second Embodiment  
       [0039]      FIG. 3  is a top view showing a junction member according to a second embodiment of the present invention.  FIG. 4 ( a ) is a top view illustrating a portion A of the junction member according to the second embodiment of the present invention shown in  FIG. 3 .  FIG. 4 ( b ) is a cross-sectional view taken along line B-B, of the junction member according to the second embodiment of the present invention shown in  FIG. 3 .  FIG. 5  is a cross-sectional view at wire bonding, of the portion A of the junction member according to the second embodiment of the present invention.  
         [0040]     As shown in  FIGS. 3 and 5 , the junction member  1  is rectangular. Although the rectangle is illustrated by way of example in the present embodiment, the present invention is not limited to it alone. Any one may be used if rectangular. It is also considered that a plurality of the junction members  1  are used according to circumstances. In the present embodiment, the length of the short side of the junction member  1  is approximately 3 mm and the length of the long side thereof is about 10 mm or so. In the junction member  1 , a first insulating film  5  is formed on a silicon substrate  4 . Junction pads  2 , pad connecting portions  3  and an interlayer insulating film  6  are formed on the first insulating film  5 . The junction pads  2  are arranged in matrix form. The junction pads  2  adjacent to one another in the short-side direction of the junction member  1  are respectively electrically connected to one another by means of the pad connecting portions  3 . In the present embodiment, the junction pads  2  and the pad connecting portions  3  are formed of metal wirings such as aluminum or copper. Areas in which the junction pads  2  and the pad connecting portions  3  are formed and an area in which the interlayer insulating film  6  is formed, are provided on the first insulating film  5 . Passivation films  7  made of glass or the like each used as a first protective film cover the interlayer insulating film  6  and the pad connecting portions  3  from thereabove. The passivation film  7  is formed even on the inner periphery of each junction pad  2  as the case may be. Now, the inner periphery of the junction pad  2  indicates the inside that extends along the outer sides of the junction pad  2 . A buffer coat film  8  made of an insulating material such as polyimide is formed on the passivation films  7  and in the inner periphery of the junction member  1 . The buffer coat film  8  may be formed in the longitudinal direction of the junction member  1  at the minimum. However, the formation of the buffer coat film  8  along only one side extending in the longitudinal direction of the junction member  1  is most suitable where the cutting-out to be described later is taken into consideration. Although the silicon substrate  4  is taken as the substrate by way of example in the present embodiment, the substrate is by no means limited to it alone. A sapphire substrate and a glass substrate or the like may be used. However, the use of the semiconductor substrate brings about the advantage that a semiconductor process is applicable using the already-existing device.  
         [0041]     A scribe line  9  corresponding to each of cut widths at fractionalizing processing of on-assembly chips is provided at the inner peripheral end of the junction member  1 . The junction member  1  according to the present embodiment does not include wirings other than the junction pads  2  and the pad connecting portions  3  and has no circuit function virtually.  
         [0042]     Referring to  FIG. 4 ( a ), the detailed sizes of the respective portions will be shown. The lengthwise and crosswise sizes of each of the junction pads  2  are both about L 1 =about 90 μm. A width L 2  of each of the pad connecting portions  3  is smaller than an interval L 3  between the mutually connected junction pads  2  and ranges from approximately 5 to 50 μm. The interval L 3  between the junction pads  2  connected to each other ranges from approximately 50 to 100 μm. Pitches L 5  of the junction pads  2  adjacent to each other in the longitudinal direction of the junction member  1  are arranged so as to range from approximately 150 to 200 μm. A width L 4  of each of the passivation films  7  on the junction pads  2  is about 5 μm. A width L 6  of the buffer coat film  8  ranges from approximately 50 to 100 μm and its thickness ranges from about 3 μm to about 8 μm.  
         [0043]      FIG. 6  is a top view showing positions at the cutting of the junction member according to the second embodiment of the present invention. A method of applying the junction member  1  will be explained with reference to  FIG. 6 . The present figure shows, as an example, the case in which the buffer coat film  8  is formed on only one side of the junction member  1 . When the required sizes are determined, scribe positions  10  are determined. The scribe positions  10  are cut in the neighborhood of the positions where the necessary sizes are obtained, with the end of the side on which the buffer coat film  8  exists being regarded as the reference. As to the cutting of the junction member  1  as viewed in its transverse direction, cutting is done between the junction pads  2  adjacent to one another in the longitudinal direction of the junction member  1 . As to the cutting of the junction member  1  as viewed in its longitudinal direction, the neighborhood of the center of each pad connecting portion  3  is cut. Incidentally, the cutting is executed in a scribed process corresponding to a conventional chip cutting process.  
         [0044]     Owing to the above configuration of the junction member  1  according to the second embodiment, the distance L 8  between each of the third metal wires  33  and a silicon exposed portion  11  exposed upon cutting of the junction member  1  can sufficiently be ensured because the buffer coat film  8  is provided, where the third metal wires  33  are wired. Thus, the third metal wire  33  and the silicon exposed portion  11  can be prevented from being electrically short-circuited.  
         [0045]     Further, since the width L 2  of each pad connecting portion  3  is set smaller than the interval L 3  between the junction pads  2  connected to one another, the length of a cut chip of the pad connecting portion  3 , which occurs upon the cutting in the scribe process, becomes shorter than the interval L 3  between the junction pads  2  connected to each other. It ranges from L 5  to L 1 ≧L 2 . Thus, it is possible to prevent a short developed between the junction pads  2  adjacent to one another in the longitudinal direction of the junction member  1  due to the cut chip.  
         [0046]     Further, the interval L 3  between the junction pads  2  connected to one another ranges from 50 μm to 100 μm and the pitch L 5  of each of the junction pads  2  adjacent to one another in the longitudinal direction of the junction member  1  ranges from 150 μm to 200 μm. Therefore, the interval necessary for the cutting in the scribe process can be set larger than 50 μm and the junction member  1  can be cut out without contacting the junction pads  2 .  
         [0047]     Furthermore, since the junction member  1  is cut out after the sizes have been determined with the end of the buffer coat film  8  as the reference, it can easily be changed to various sizes as needed, thereby improving general versatility. A spot to cut the buffer coat film  8  becomes only one spot, and the direction to cut it becomes only the transverse direction of the junction member  1 . The buffer coat film  8  has the feature that it is apt to be peeled due to damage of cutting upon the scribe process. Since, however, the number of cuttings of the buffer coat film  8  and its cut distance can be respectively suppressed to the minimum, the peeling of the buffer coat film  8  can be prevented from occurring.  
       Third Embodiment  
       [0048]     A third embodiment of the present invention will next be explained.  FIG. 7 ( a ) is a top view of a junction member according to the third embodiment.  FIG. 7 ( b ) is an enlarged view of a portion B of the junction member according to the third embodiment. Incidentally, the same elements of structure as those employed in the second embodiment are respectively identified by the same reference numerals upon explanation of a structure of the junction member according to the third embodiment and its manufacturing method.  
         [0049]     A point of difference between the structure of the junction member  1  according to the second embodiment of the present invention and the structure of the junction member  12  according to the third embodiment of the present invention resides in that sub pads  13  and sub pad connecting portions  14  have been added. The sub pads  13  are formed between pad connecting portions  2  adjacent to one another as viewed in the longitudinal direction of the junction member  12 . The sub pad connecting portions  14 , which electrically connect the adjoining sub pads  13 , are formed in the longitudinal direction of the junction member  12 . The sub pads  13  and the sub pad connecting portions  14  substantially vertically intersect an arrangement of the junction pads  2  and their corresponding pad connecting portions  3 . Since, however, the arrangement of the junction pads  2  and the pad connecting portions  3 , and the sub pads  13  and the sub pad connecting pads  14  are respectively formed in different layers, they are not short-circuited to one another.  
         [0050]     The sub pads  13  and the sub pad connecting portions  14  are arranged on alternate columns with respect to columns of the junction pads  2  as viewed in the transverse direction of the junction member  12 . However, the sub pads  13  and the sub pad connecting portions  14  may be arranged on alternate plural columns as needed and are not limited to the alternate columns. Similarly, although the sub pads  13  are arranged every rows as viewed in the longitudinal direction of the junction member  12  as shown in  FIG. 7 , the sub pads  13  may be arranged on alternate plural rows.  
         [0051]      FIG. 8  is a top view showing positions at the cutting of the junction member according to the third embodiment of the present invention shown in  FIG. 7 ( a ). A method of applying the junction member  12  will be explained with reference to  FIG. 8 . However, the description of the contents similar to  FIG. 6  illustrative of the positions at the cutting of the second embodiment of the present invention will be omitted. A description will be made of the difference between the positions at the cutting of the third embodiment of the present invention and the positions at the cutting of the second embodiment.  
         [0052]     Each of the cutting positions of the junction member  12  as viewed in the transverse direction thereof is placed between the junction pads  2  between which no sub pads  13  are disposed. Each of the cutting positions of the junction member  12  as viewed in the longitudinal direction thereof is placed between the junction pads  2  between which the sub pads  13  and the sub pad connecting portions  14  are not provided.  
         [0053]     Owing to the setting of the above cutting positions, the number of times in which the sub pad connecting portions  14  are cut, can be suppressed to the minimum. It is thus possible to prevent shorts developed between the junction pads  2  and the sub pad connecting portions  14  due to the cut chip.  
         [0054]      FIG. 9  is a wired example using the junction member according to the third embodiment of the present invention shown in  FIG. 7 . Of second pads  22  of a second semiconductor element  27 , ones marked with black dots are second pads  22  for a power supply. There may be cases in which the power supply second pads  22  are connected to their corresponding lead frame terminals  21  corresponding to power supply pins  15   a  and connected to their corresponding sub pads  13  of the junction member  12 . The sub pad  13  and its corresponding junction pad  2  are wire-bonded to each other by a pad junction wire  18 . The other junction pad  2  electrically made conductive to its corresponding previous junction pad  2 , and a lead frame terminal  21  for a power supply pin  15   b  are wire-bonded to each other by a pad junction wire  19 . The address second pads  22  of the second semiconductor element  27  are electrically connected to their corresponding lead frame terminals  21  for address pins  20   b  by wire bonding, using desired junction pads of the junction member  12 . A partial flow of an electric signal is indicated by a dotted line.  
         [0055]     Owing to the execution of above connections, the layout of the power pins  15   a  and  15   b  and the layout of the address pins  20  can freely be changed, thus making it possible to improve the degree of freedom of wiring.  
         [0056]     While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.