Abstract:
A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier ( 300   a - 300   b ) may include a capacitive switching circuit ( 304   a - 304   b ), a capacitive switching circuit ( 306   a - 306   b ), and an operational amplifier ( 302   a - 302   b ). Capacitive switching circuits ( 304   a - 304   b  and  306   a - 306   b ) may receive an analog input voltage through sample switches ( 308   a - 308   b  and  310   a - 310   b ). Capacitive switching circuit ( 304   a - 304   b ) receives an output from operational amplifier ( 302   a - 302   b ) through feedback switch ( 312   a - 312   b ). The programmable gain amplifier ( 300   a - 300   b ) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates generally to electronic circuits and, more particularly, to circuits having variable amplification of an input signal.  
         BACKGROUND OF THE INVENTION  
         [0002]    In many signal processing applications there exists a need for providing exponential gain variations based on a linearly varying input control. Exponential gain variation implies that each increment in the control signal translates into a multiplication of the present gain value by a fixed quantity. Where this gain is controlled so as to vary based on a programmed input code or a control signal, the amplifier can be considered to a programmable gain amplifier.  
           [0003]    One approach to providing exponential gain variation may take into account the exponential dependence of collector current on the base to emitter voltage of a bipolar junction transistor (BJT) device. That is, a BJT device may be used for gain control. One example of such an approach is shown in the publication, “Comlinear CLC520 Amplifier with Voltage Controlled Gain”, National Semiconductor Corporation (NSC) Data Sheet, August 1996.  
           [0004]    [0004]FIG. 1A shows exponential gain characteristics, as illustrated in the above referenced NSC data sheet. The graph of FIG. 1A includes a graph  120  that shows a gain versus the input voltage, Vg. The gain may be the ratio between an amplifier output voltage and the input voltage Vg. FIG. 1B shows these same characteristics, but with the gain measured in decibels (dB), which equals 20log(Vout/Vin). The Gain(dB) versus input voltage (Vg) curve is labeled  124 .  
           [0005]    While BJT gain control approaches, and the like, can provide exponential gain control, alternate approaches can provide a piecewise linear approximation to the exponential gain. Such approaches can include cascaded attenuators. An example of a conventional approximation approach is shown in “An Analog-to-Digital Processor for Camcorders and Digital Still Cameras”,  IEEE Transactions on Consumer Electronics,  Vol. 44, No. 3, August 1998, by Mike Koen. In Koen, the relative gain versus a control voltage is as shown in FIG. 1C as curve  128 . While Koen can provide an approximation of an exponential gain control, such an approach may be limited by noise requirements. It would be desirable to arrive at a more robust way of providing exponential gain control.  
           [0006]    Still other approaches to approximating exponential linear gain control can include amplifier circuit that include switched capacitor networks. Accordingly, by way of further background, some basic principles of switched-capacitor networks will now be described. Typically, switched-capacitor networks can include metal-oxide-semiconductor (MOS) type switches. In MOS technology, it is relatively easy to implement switches, capacitors, and operational amplifiers (op amps). However, it can be difficult to construct resistors with the necessary accuracy. Consequently, switched-capacitor circuits can allow for a basic resistor approximation by using two MOS switches and a capacitor.  
           [0007]    Extensive switched-capacitor networks, particularly those that employ the use of op amps and feedback circuitry, are well known in the art. Common applications include performing certain mathematical operations. For example, op amp circuits with switched-capacitor networks can implement signal summation, differentiation, programmable gain, and integration, to name only a few.  
           [0008]    Programmable gain amplifiers can be implemented as a circuit using many different topologies, but with different degrees of relative success. For example, a programmable gain amplifier may have an open loop configuration, where there is no feedback network present. However, open loop topologies usually suffer from a compromise of signal range and linearity. As but one example, it is believed that achieving a signal gain which is linear to a 10-bit level for a one volt scale signal for any programmed gain, can be very difficult.  
           [0009]    Closed loop, switched-capacitor programmable gain amplifiers, which include a feedback network present, are believed to provide better signal linearity than open loop approaches. Still further, in many cases switched-capacitor networks may be easily controlled by a digital interface. This can result in improved linearity of gain control (on a log scale) compared to other schemes.  
           [0010]    Switched-capacitor circuits can handle large input signals that can be programmed over a wide range. However, the accuracy of a switched capacitor can often be dominated by capacitor matching. Thus, in many conventional approaches, in order to achieve exponential gains, exponentially varying capacitor sizes are used. Unfortunately, it can be difficult to design with exponentially varying capacitor sizes because of silicon area and power requirements.  
           [0011]    A programmable gain amplifier that may include a switched-capacitor network of unit capacitors is shown in U.S. patent application Ser. No. 09/354,461, filed on Jul. 15, 1999 and titled “A Capacitor-Based Exponential Programmable Gain Amplifier” (referred to herein as Application 354,461).  
           [0012]    In general, it can be possible to implement exponential gain variation with the approximation log e  (1+x)/(1−x)=˜2x, where |x|&lt;1 is utilized. Here, x varies linearly and can correspond to the input gain setting code. A switched-capacitor stage of a programmable gain amplifier can implement a gain according relationship (a+x)/(a−x), which can be seen to vary exponentially with x. Thus, for a switched-capacitor gain stage, the gain can be determined as the ratio of the number of unit capacitors used to sample an input to the number used for feedback. In the particular equation described above, a sampling capacitance can be represented by a gain numerator term (a+x), while a feedback capacitance can be represented by a gain denominator term (a−x). Accordingly, the number of unit capacitors used for sampling corresponds to (a+x) and those used for feedback correspond to (a−x).  
           [0013]    In an approach such as Application 354,461, a sampling capacitance can be conceptualized as including (a−x) and 2x capacitors, totalling (a+x) capacitors. As is understood the feedback capacitance (a−x) is included in the sampling capacitance term. Such a splitting of terms can enable implementation of the programmable gain amplifier with a reduced number of unit capacitors. One such implementation is shown schematically in FIG. 2A. It is understood that during the operation of a circuit, switching may result in the use of some unit capacitors and the non-use of others. Unused capacitors in any gain setting can be left connected to an op amp input node, and thereby serve to reduce the variation in the feedback-factor of the closed loop amplifier.  
           [0014]    Referring again to FIG. 2A, a schematic diagram of a programmable gain amplifier according to the prior art will be described in more detail. The conventional programmable gain amplifier circuit is designated by the general reference character  200  and is shown to include an operational amplifier (op amp)  202 , capacitive switching circuits ( 204  and  206 ), switches ( 208  and  210 ), feedback switch  212 , switch  214 , and a sample precharge switch  216 .  
           [0015]    The op amp  202  has a noninverting input connected to a charge summing node  218 . The op amp  202  has an inverting input connected to node  230 . The inverting output of the op amp  202  is connected to an analog output terminal  220 , which is also labeled as Vout+, while the non-inverting output of the op amp  202  is connected to an analog output terminal  232 . Analog output node  220  is connected to the closed position input terminal of feedback switch  212 .  
           [0016]    The programmable gain amplifier receives an input signal Vin+ at analog input terminal  226 . The analog input terminal  226  is connected to the closed position input terminals sample switches  208  and  210 . A ground terminal  228  is connected to the closed position input terminal of switch  214 . The output terminals of feedback switch  212  and sample switch  208  are connected to the input terminal of the capacitive switching circuit  204 . The capacitive switching circuit  204  is a capacitor that has the value a−x. The output terminals of sample switch  210  and switch  214  are connected to the input terminal of capacitive switching circuit  206 , the capacitive switching circuit  206  is a capacitor that has the value 2x. Terminals of the capacitive switching circuits  204  and  206  are connected to the charge summing node  218 , which is also connected to the noninverting input of op amp  202  and to the output terminal of sample precharge switch  216 .  
           [0017]    A reference signal Vref is connected to the closed position input terminal of sample precharge switch  216 . As is common in the art, only one half of the symmetric fully differential circuit is shown here for simplicity.  
           [0018]    [0018]FIG. 2B shows the two phase non-overlapping clocking scheme that controls the switches in the circuit of FIG. 2A, as well as in the circuits to be discussed below. In FIG. 3A, the Sample waveform  270  rises coincident with Sample-P waveform  272 , but Sample waveform  270  remains high longer than Sample-P waveform  272 . Feedback waveform  274  is high only during the time period when both Sample waveform  270  and Sample-P waveform  272  are low.  
           [0019]    Referring again to FIG. 2A in conjunction with FIG. 2B, the Feedback signal is coupled to feedback switch  212  and switch  214 . When Feedback is high, feedback switch  212  and switch  214  connect their respective closed position input terminals to their respective output terminals. When Feedback is low, feedback switch  212  and switch  214  connect their respective open position input terminals to their respective output terminals. The Sample signal is coupled to sample switches  208  and  210 . When Sample is high, sample switches  208  and  210  connect their respective closed position input terminals to their respective output terminals. When Sample is low, sample switches  208  and  210  connect their respective open position input terminals to their respective output terminals. The Sample-P signal is coupled to sample precharge switch  216 . When Sample-P is high, the closed position input terminal is connected to the sample precharge switch  216  output terminal. When Sample-P is low, sample precharge switch  216  is configured in the open position, thus the open position input terminal of sample precharge switch  216  is connected to the sample precharge switch  216  output terminal.  
           [0020]    By viewing FIG. 2A in conjunction with FIG. 2B, the circuit operation can be ascertained. When Sample and Sample-P are both high, during Phase 1, sample precharge switch  216  and sample switches ( 208  and  210 ) are all in their closed positions. Because feedback is low at this time, feedback switch  212  and switch  214  are in their open positions. As such, the input nodes of the capacitive switching circuits  204  and  206  are both charged to Vin+ while the charge summing node  218  is charged to Vref. Such a charging occurs over parallel sampling capacitances a−x and 2x, for a total sampling capacitance of a+x. This capacitance can correspond to a numerator term of a programmable gain.  
           [0021]    When Feedback is high, during Phase 2, feedback switch  212  and switch  214  are in their closed positions, while all other switches are in their open positions. This is the state of all switches as actually illustrated in FIG. 2A. During Phase 2, the Vout+ level is connected through feedback switch  212  and to the input node of the capacitive switching circuit  204 . Also during Phase 2, the input node of the capacitive switching circuit  206  is connected to ground terminal  228  through switch  214 . A feedback voltage may thus be applied to non-inverting input by way of feedback capacitance a−x. This capacitance can correspond to a denominator term of a programmable gain. The total number of capacitors required is the sum of “a” and the maximum number of steps (x max ). For a particular gain setting “x 1 ”, there exist (a+x max )−(a+x 1 )=(x max −x 1 ) capacitors that can be unused for the gain operation. These can be unused in both the sample and feeback phase and can be left connected to node  218  in both phases for the purpose of stabilization.  
           [0022]    In review, during the Phase 1 sampling period, capacitive switching circuits  204  and  206  are connected to the input signal Vin+ through sample switches  208  and  210 , respectively. The sum of their capacitance values, or a−x+2x=a+x, gives the numerator in the overall gain equation. During the Phase 2 feedback period, only capacitive switching circuit  204  is enabled to the actual feedback signal, Vout+, through feedback switch  212 . As such, the denominator in the overall gain equation is given by the capacitance value of the capacitive switching circuit  204  (a−x). Thus, the overall gain equals (a+x)/(a−x). It is understood that x is a programmable value that may be applied to the programmable gain amplifier.  
           [0023]    In this way, one conventional approach can arrive programmable gain stage with an exponential gain control by switching to a predetermined sample capacitance and then to a predetermined feedback capacitance for all programmed gain steps.  
           [0024]    The topology considered above can include capacitor arrays that include only unit capacitors. It follows that as the number of possible gain steps (determined by value x) increases, the number of unit capacitors can increase correspondingly. However, while unit capacitors may provide for increased accuracy in arriving at sampling and feedback capacitance, such unit capacitors can require valuable area on an integrated circuit device. Further, a larger number of capacitors can translate into more stores charge, and hence greater power consumption. Thus, larger numbers of unit capacitors can work against the common goal of smaller, lower power devices.  
           [0025]    One approach to providing a programmable amplifier with gain steps that may require fewer capacitors can be to include an array of switchable weighted capacitors. Weighted capacitors may be weighted in a binary, exponential, or some other fashion. In such an approach, weighted capacitors may be switched to arrive at a desired sample and feedback capacitance. However, as noted above, gain accuracy can be reduced due to the difficulty in matching between the capacitors of different sizes.  
           [0026]    In light of the above discussion, it would be desirable to arrive at some way of providing a programmable gain amplifier that may include a given number of gain steps, but include fewer capacitors than conventional approaches.  
           [0027]    It would also be desirable to arrive at some way of providing a programmable gain amplifier that may approximate and an ideal exponential response over a wider range of gain values than conventional approaches.  
         SUMMARY OF THE INVENTION  
         [0028]    According to the present embodiments, a programmable gain amplifier may include metal-oxide-semiconductor (MOS) transistors for approximating exponential gain characteristics with linear control signals. The programmable gain amplifier may include capacitive switching circuits in which a unit or fractional unit capacitor may be added. By using an additional unit or fractional unit capacitor, a gain approximation can be used which can allow an achievable gain range in which more steps may be implemented, thus allowing finer gain programmability.  
           [0029]    According to one aspect of the embodiments, a few additional unit capacitors can allow larger gain ranges or more steps for a given range without a large increase in chip size.  
           [0030]    According to one aspect of the embodiments, the programmable gain amplifier may provide gain steps that are divided into two or more groups. One group of steps may be governed by one gain equation while another group of steps may be governed by another, different gain equation.  
           [0031]    According to one aspect of the embodiments, the gain of the programmable gain amplifier is determined by the capacitance of capacitive switching circuits.  
           [0032]    According to another aspect of the embodiments, one of the capacitive switching circuits may have a first approximate capacitance value one group of steps and a second approximate value greater than the first approximate capacitance value for another group of steps.  
           [0033]    According to another aspect of the embodiments, the programmable gain amplifier includes a sampling switch that may charge a capacitive switching circuit according to the voltage on an analog input terminal. A feedback switch may charge the capacitive switching circuit according to the voltage on an analog output terminal of a differential amplifier.  
           [0034]    According to another aspect of the embodiments, the programmable gain amplifier includes a switch coupled to charge a capacitive switching circuit to a reference level.  
           [0035]    According to another aspect of the embodiments, capacitive switching circuit capacitance can be obtained from an array of programmable capacitors.  
           [0036]    According to another aspect of the embodiments, in a group of gain steps, a capacitive switching circuit may have a capacitance of approximately (a+x), where “a” can be a predetermined capacitance value and “x” can be a programmable capacitance value determined by the gain step.  
           [0037]    According to another aspect of the embodiments, a capacitive switching circuit may have an approximate value of 2x plus the value of a programmable unit capacitor, where “x” can be a programmable capacitance value determined by the gain step.  
           [0038]    According to another aspect of the embodiments, a capacitive switching circuit has an approximate value of (a−x) and another capacitive switching circuit has an approximate value of (a+2x), where “a” can be a predetermined capacitance value and “x” can be a programmable capacitance value determined by the gain step.  
           [0039]    According to another aspect of the embodiments, the programmable gain amplifier includes an array of programmable capacitors. The programmable capacitors have essentially the same sized unit capacitors and may include at least one fractional capacitor having a value that is a fraction of a unit capacitor.  
           [0040]    According to another aspect of the embodiments, at least one capacitor not used in a capacitor switching circuit is coupled to a charge summing node and a reference voltage. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0041]    The foregoing aspects and advantages of various embodiments will become more readily appreciated by reference to the following detailed description, when taken in conjunction with the accompanying drawings listed below.  
         [0042]    [0042]FIG. 1A is a diagram illustrative of exponential gain characteristics in terms of the ratio of the output voltage to the input voltage.  
         [0043]    [0043]FIG. 1B is a diagram illustrative of exponential gain characteristics as expressed in decibels (dB).  
         [0044]    [0044]FIG. 1C is a diagram illustrative of attenuation versus the control voltage.  
         [0045]    [0045]FIG. 2A is a simplified schematic diagram illustrative of a programmable gain amplifier common in the prior art.  
         [0046]    [0046]FIG. 2B is a timing diagram illustrative of the two phase non-overlapping clocking scheme employed in many of the circuits described herein.  
         [0047]    [0047]FIG. 3A is a simplified schematic diagram illustrative of a programmable gain amplifier with half the step size, during even steps.  
         [0048]    [0048]FIG. 3B is a simplified schematic diagram illustrative of a programmable gain amplifier with half the step size, during odd steps.  
         [0049]    [0049]FIG. 4A is a simplified schematic diagram illustrative of a programmable gain amplifier with half the step size, during even steps, for the approximation (a+x)/(a−x).  
         [0050]    [0050]FIG. 4B is a simplified schematic diagram illustrative of a programmable gain amplifier with half the step size, during odd steps, for the approximation (a+x+1)/(a−x).  
         [0051]    [0051]FIG. 5A is a simplified schematic diagram illustrative of a programmable gain amplifier with half the step size, during even steps, for the approximation (a+x)/(a−x).  
         [0052]    [0052]FIG. 5B is a simplified schematic diagram illustrative of a programmable gain amplifier with half the step size, during odd steps, for the approximation (a+x)/(a−x−1).  
         [0053]    [0053]FIG. 6 is a diagram illustrative of the variation in gain obtained by embodiments of the present invention along with the associated ideal characteristics.  
         [0054]    [0054]FIG. 7 is a diagram illustrative of the differences in the characteristics of the first, second, and third embodiments of the present invention.  
         [0055]    [0055]FIG. 8 is a diagram illustrative of the differences in the characteristics of embodiments of the present invention, as ratios of gains.  
         [0056]    [0056]FIG. 9 is a simplified schematic diagram illustrative of a programmable gain amplifier implementing the function (2a)/(a−x).  
         [0057]    [0057]FIG. 10 is a simplified schematic diagram illustrative of a programmable gain amplifier implementing the function (2a+x)/(a−x).  
         [0058]    [0058]FIG. 11 is a simplified schematic diagram illustrative of a programmable gain amplifier implementing the function 1+(x/c).  
         [0059]    [0059]FIG. 12A is a diagram illustrative of the characteristics of the function (a+x)/(a−x).  
         [0060]    [0060]FIG. 12B is a diagram illustrative of the characteristics of the two segment functions (a+x)/(a−x) and (2a)/(a−x).  
         [0061]    [0061]FIG. 12C is a diagram illustrative of the characteristics of the two segment functions (a+x)/(a−x) and 2(a+x)/(a−x).  
         [0062]    [0062]FIG. 12D is a diagram illustrative of the characteristics of the function (2a+x)/(a−x).  
         [0063]    [0063]FIG. 12E is a diagram illustrative of the characteristics of the function 1+(x/c). 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0064]    Various embodiments may provide for approximate exponential gain variation with fewer capacitors and/or added accuracy over a given range of gain values by including switching circuits that may provide one sampling and/or feedback capacitance for certain gain steps while providing a different sampling and/or feedback capacitance for other gain steps.  
         [0065]    According to one particular embodiment, a programmable gain amplifier that approximates exponential gain variation may include alternating first and second gain steps. For first gain steps, a first sampling capacitance and first feedback capacitance can be used. For second gain steps, a second sampling capacitance and second feedback capacitance can be used.  
         [0066]    Such an embodiment may be best understood by example. It will first be assumed that it is desirable to arrive at an exponential gain variation between 1 and 2, in 64 steps of resolution. Each step may be 0.09 dB. Using the function (a+x)/(a−x)=2 where x=64, and solving for a (a=192), the number of unit capacitors in a conventional approach can be (a+x), or 256. Each unit capacitor is, of course, identically sized. It follows that to conventionally implement the same gain range in 128 steps with an associated step size of 0.045 dB would require the use of 512 unit capacitors.  
         [0067]    However, according to embodiments of the present invention, with the addition of just two half-unit capacitors to the 256 unit capacitors, the gain range of 1 to 2 can be spanned in 128 steps. This is illustrated by considering  
         [0068]    (a+x)/(a−x), where x=0,1, . . . 63  
         [0069]    as  
         [0070]    (a+x/2)/(a−x/2), where x=0,1, . . . 127, which allows for 128 steps, with odd values of “x” using the half size capacitors.  
         [0071]    A simplified schematic of an implementation of this scheme is shown in FIG. 3A for the even steps and FIG. 3B for the odd steps. Table 1 shows the gain equations that may be used for this example. The 2nd column illustrates how in a conventional (old) case x=0-127 to arrive at 128 gain steps while using 512 capacitors. The 2nd column also illustrates how the same gain ratio can be used for all gain steps. In contrast, the 3rd column illustrates how 128 gain steps may be achieved, while using 128 unit capacitors and two half-unit capacitors, thereby reducing overall capacitor numbers. The right columns also show how on particular gain steps (e.g., even steps) one grain ratio may be used, while on other gain steps (e.g., odd steps) a different gain ratio may be used.  
                                     TABLE 1                       Step   Ratio—old   Ratio—new                                0   (a + x)/(a − x)   (a + x)/(a − x)       1   (a + x)/(a − x)   (a + x + ½)/(a − x − ½)       2   (a + x)/(a − x)   (a + x)/(a − x)       3   (a + x)/(a − x)   (a + x + ½)/(a − x − ½)       . . .    . . .    . . .        124   (a + x)/(a − x)   (a + x)/(a − x)       125   (a + x)/(a − x)   (a + x + ½)/(a − x − ½)       126   (a + x)/(a − x)   (a + x)/(a − x)       127   (a + x)/(a − x)   (a + x + ½)/(a − x −½2)                  
 
         [0072]    It follows from the above table and dicussion that the gain steps can further be doubled by the use of just two additional one-fourth unit capacitors.  
         [0073]    Referring now to FIG. 3A, a schematic diagram of a programmable gain amplifier according to the present invention is set forth. The programmable gain amplifier can include similar constituents as the conventional case set forth in FIG. 2A. To that extent, like constituents will be referred to by the same reference character, but with the first digit being a “3” instead of “2” and ending with an “a.” 
         [0074]    The programmable gain amplifier circuit of FIG. 3A is designated by the general reference character  300   a  and is shown to may include an operational amplifier (op amp)  302   a,  capacitive switching circuits ( 304   a,  and  306   a ), sample switches ( 308   a  and  310   a ), feedback switch  312   a,  switch  314   a,  and a sample precharge switch  316   a.    
         [0075]    An op amp  302   a  may have a noninverting input connected to a charge summing node  318   a . The op amp  302   a  may have an inverting input connected to node  330   a . The inverting output of the op amp  302   a  can be connected to an analog output terminal  320   a  which is also labeled as Vout+. The non-inverting output of the op amp  302   a  can be connected to an analog output terminal  332   a . Analog output node  320   a  may be connected to the closed position input terminal of feedback switch  312   a.    
         [0076]    The programmable gain amplifier may receive an input signal Vin+ at analog input terminal  326   a . The first analog input terminal  326   a  may be connected to the closed position input terminals of sample switches  308   a  and  310   a . A ground terminal  328   a  can be connected to the closed position input terminal of switch  314   a . The output terminals of feedback switch  312   a  and sample switch  308   a  can be connected to the input terminal of the capacitive switching circuit  304   a.    
         [0077]    Unlike the conventional programmable gain amplifier  200  of FIG. 2A, the capacitive switching circuit  304   a  of the programmable gain amplifier  300   a  in the embodiment of the invention set forth in FIG. 3A may be comprised of two capacitors, a capacitor circuit  340   a  that can have the value a−x−½ and a capacitor circuit  342   a  that can have the value of ½. The output terminals of sample switch  310   a  and switch  314   a  may be connected to the input terminal of capacitive switching circuit  306   a , the capacitive switching circuit  306   a  may be a capacitor that has the value 2x.  
         [0078]    A third capacitive switching circuit  322   a  can be included that has a capacitor with a value of ½. Third capacitive swithing circuit  322   a  may has an input connected to the ground terminal  328   a  through a switch  334   a , which may be in the closed position.  
         [0079]    The second terminals of capacitive switching circuits ( 304   a ,  306   a , and  322   a ) can be connected to the charge summing node  318   a , which can also connected to the noninverting input of op amp  302   a  and to the output terminal of sample precharge switch  316   a.    
         [0080]    A reference signal Vref can be connected to the closed position input terminal of sample precharge switch  316   a . As is common in the art, only one half of the symmetric fully differential circuit is shown here for simplicity.  
         [0081]    An embodiment, such as that shown in FIGS. 3A and 3B may operate according to the same timing signals shown in FIG. 2B. The operation of the embodiment of FIGS. 3A and 3B will now be described with reference to FIG. 2B.  
         [0082]    Referring to FIG. 3A in conjunction with FIG. 2B, the Feedback signal may be coupled to feedback switch  312   a  and switch  314   a . When Feedback is high, feedback switch  312   a  and switch  314   a  may connect their respective closed position input terminals to their respective output terminals. When Feedback is low, feedback switch  312   a  and switch  314   a  may connect their respective open position input terminals to their respective output terminals. The Sample signal can be coupled to sample switches  308   a  and  310   a . When Sample is high, sample switches  308   a  and  310   a  may connect their respective closed position input terminals to their respective output terminals. When Sample is low, sample switches  308   a  and  310   a  may connect their respective open position input terminals to their respective output terminals. The Sample-P signal can be coupled to sample precharge switch  316   a . When Sample-P is high, the closed position input terminal can be connected to the sample precharge switch  316   a  output terminal. When Sample-P is low, sample precharge switch  316   a  can be configured in the open position, thus the open position input terminal of sample precharge switch  316   a  can be connected to the sample precharge switch  316   a  output terminal.  
         [0083]    By viewing FIG. 3A in conjunction with FIG. 2B, the circuit operation can be ascertained. When Sample and Sample-P are both high, during Phase 1, sample precharge switch  316   a  and sample switches ( 308   a  and  310   a ) can be all in their closed positions. Since Feedback is low at this time, feedback switch  312   a  and switch  314   a  may be in their open positions. As such, the input nodes of the capacitive switching circuits  304   a  and  306   a  may both be charged to Vin+ while the charge summing node  318   a  may be charged to Vref.  
         [0084]    When Feedback is high, during Phase 2, feedback switch  312   a  and switch  314   a  can be in their closed positions, while all other switches can be in their open positions. This can be representative of the state of all switches as actually illustrated in FIG. 2A. During Phase 2, the Vout+ level can be connected through feedback switch  312   a  and to the input node of the capacitive switching circuit  304   a . Also during Phase 2, the input node of the capacitive switching circuit  306   a  can be connected to ground terminal  328   a  through switch  314   a.    
         [0085]    The above described sampling and feedback operations can determine amplifier gain. During the Phase 1 sampling period, capacitive switching circuits  304   a  and  306   a  can be connected to the input signal Vin+ through sample switches ( 308   a  and  310   a ), respectively. The sum of their capacitance values, or a−x−½+½+2x=a+x, may give the numerator in the overall gain equation. During the Phase 2 feedback period, capacitive switching circuit  304   a  may be enabled to the actual feedback signal, Vout+, through feedback switch  312   a . As such, the denominator in the overall gain equation can be given by the capacitance value of the capacitive switching circuit  304   a , which is a−x−½+½=a−x. Thus, the overall gain can equal (a+x)/(a−x).  
         [0086]    While FIG. 3A can represent the operation of an embodiment during certain gain steps (e.g., even gain steps), an embodiment may have different sample and/or feedback capacitance values in other gain steps (e.g., odd gain steps). FIG. 3B shows the embodiment of FIG. 3A during other gain steps.  
         [0087]    Referring now to FIG. 3B, a programmable gain amplifier during aaccording to the present invention can include similar constituents as the embodiment set forth in FIG. 3A. To that extent, like constituents will be referred to by the same reference character, but with the last digit being a “b” instead of an “a.” 
         [0088]    The programmable gain amplifier circuit of FIG. 3 b  is designated by the general reference character  300   b  and may include an operational amplifier (op amp)  302   b , capacitive switching circuits ( 304   b  and  306   b ), sample switches ( 308   b  and  310   b ), feedback switch  312   b , switch  314   b , and a sample precharge switch  316   b.    
         [0089]    An op amp  302   b  can have a noninverting input connected to a charge summing node  318   b . The op amp  302   b  can have an inverting input connected to node  330   b . The inverting output of the op amp  302   b  can be connected to analog output terminal  320   b , which can also be labeled as Vout+. Non-inverting output of the op amp  302   b  can be connected to analog output terminal  332   b . Analog output node  320   b  can be connected to the closed position input terminal of feedback switch  312   b.    
         [0090]    The programmable gain amplifier may receive an input signal Vin+ at analog input terminal  326   b . The analog input terminal  326   b  can be connected to the closed position input terminals of sample switches  308   b  and  310   b . A ground terminal  328   b  can be connected to the closed position input terminal of switch  314   b . The output terminals of feedback switch  312   b  and sample switch  308   b  can be connected to the input terminal of the capacitive switching circuit  304   b . The capacitive switching circuit  304   b  may have the value of a−x−½. It is noted that this may differ from the configuration of FIG. 3A which included an additional capacitor in parallel with a value of ½.  
         [0091]    The output terminals of sample switch  310   b  and feedback switch  314   b  can be connected to the input terminal of capacitive switching circuit  306   b . Unlike the conventional programmable gain amplifier  200  of FIG. 2A, the capacitive switching circuit  306   b  of the programmable gain amplifier  300   b  in the embodiment of the invention set forth in FIG. 3B can be comprised of two capacitors, capacitor circuit  350   b  that can have the value 2x and a second capacitor circuit  352   b  that may have the value of ½+½. The second terminals of capacitive switching circuits ( 304   b  and  306   b ) can be connected to the charge summing node  318   b , which may also be connected to the noninverting input of op amp  302   b  and to the output terminal of sample precharge switch  316   b.    
         [0092]    A reference signal Vref can be connected to the closed position input terminal of sample precharge switch  316   b . As is common in the art, only one half of the symmetric fully differential circuit is shown here for simplicity.  
         [0093]    Referring again to FIG. 3B in conjunction with FIG. 2B, the Feedback signal may be coupled to feedback switch  312   b  and switch  314   b . When Feedback is high, feedback switch  312   b  and switch  314   b  can connect their respective closed position input terminals to their respective output terminals. When Feedback is low, feedback switch  312   b  and switch  314   b  may connect their respective open position input terminals to their respective output terminals. The Sample signal can be coupled to sample switches  308   b  and  310   b . When Sample is high, sample switches  308   b  and  310   b  can connect their respective closed position input terminals to their respective output terminals. When Sample is low, sample switches  308   b  and  310   b  may connect their respective open position input terminals to their respective output terminals. The Sample-P signal can be coupled to sample precharge switch  316   b . When Sample-P is high, the closed position input terminal may be connected to the sample precharge switch  316   b  output terminal. When Sample-P is low, sample precharge switch  316   b  can be configured in the open position, thus the open position input terminal of sample precharge switch  316   b  can be connected to the sample precharge switch  316   b  output terminal.  
         [0094]    By viewing FIG. 3B in conjunction with FIG. 2B, the circuit operation can be ascertained. When Sample and Sample-P are both high, during Phase 1, sample precharge switch  316   b  and sample switches ( 308   b  and  310   b ) may all be in their closed positions. Since Feedback is low at this time, feedback switch  312   b  and switch  314   b  can be in their open positions. As such, the input nodes of the capacitive switching circuits ( 304   b  and  306   b ) may both be charged to Vin+ while the charge summing node  318   b  can be charged to Vref.  
         [0095]    When Feedback is high, during Phase 2, feedback switch  312   b  and switch  314   b  can be in their closed positions, while all other switches are in their open positions. This can be the state of all switches as actually illustrated in FIG. 3B. During Phase 2, the Vout+ level can be connected through feedback switch  312   b  and to the input node of the capacitive switching circuit  304   b . Also during Phase 2, the input node of the capacitive switching circuit  306   b  can be connected to ground terminal  328   b  through switch  314   b.    
         [0096]    The above described sampling and feedback operations can determine amplifier gain. During the Phase 1 sampling period, capacitive switching circuits  304   b  and  306   b  can be connected to the input signal Vin+ through sample switches ( 308   b  and  310   b ), respectively. The sum of their capacitance values, which may be (a−x−½)+2x+(½+½)=a+x+½, can be the numerator in the overall gain equation. During the Phase 2 feedback period, capacitive switching circuit  304   b  can be singly coupled to the actual feedback signal, Vout+, through feedback switch  312   b . As such, the denominator in the overall gain equation may be given by the capacitance value of the capacitive switching circuit  304   b , which can be a−x−½. Thus, the overall gain may equal (a+x+½)/(a−x−½).  
         [0097]    Of course, various described fractional unit capacitors may be formed by connecting multiple unit capacitors in series.  
         [0098]    Exponential gain approximation may include additional half steps with the addition of a single unit capacitor to the numerator (sampling capacitors). The even steps can be represented by a gain (a+x)/(a−x) and the odd steps by a gain (a+x+1)/(a−x). Such an approach can obtain twice the number of gain steps with the addition of a single unit capacitor.  
         [0099]    This approach is shown in FIGS. 4A and 4B. Like the example of FIGS. 3A and 3B, overall gain steps for the programmable gain amplifier may be divided into alternating even and odd steps. A circuit configurations for even steps is shown in FIG. 4A, and can have a gain of (a+x)/(a−x). Odd steps are shown in FIG. 4B, and can have a gain of (a+x+1)/(a−x).  
         [0100]    Referring now to FIG. 4A, a schematic diagram of a programmable gain amplifier according to the present invention is set forth. The programmable gain amplifier can include similar constituents as the embodiment set forth in FIG. 3A. To that extent, like constituents will be referred to by the same reference character, but with the first digit being a “4” instead of a “3.” 
         [0101]    The programmable gain amplifier circuit of FIG. 4A is designated by the general reference character  400   a . The programmable gain amplifier circuit  400   a  of FIG. 4A can be different than the programmable gain amplifier of FIG. 3A in that the first and third capacitive switching circuits ( 404   a  and  422   a ) may have different values. Capacitive switching circuit  404   a  can be a capacitor that can have the value of (a−x) and capacitive switching circuit  422   a  can be a capacitor that can have the value of 1.  
         [0102]    The sum of the capacitive value of the capacitive switching circuits ( 404   a  and  406   a ), which may be a−x+2x=a+x, can be the numerator in the overall gain equation. The denominator in the overall gain equation can be given by the capacitance value of the capacitive switching circuit  404   a , which may be a−x. Thus, the overall gain for certain gain steps (e.g., even steps) can be (a+x)/(a−x).  
         [0103]    Referring now to FIG. 4B, a schematic diagram of a programmable gain amplifier according to the present invention is set forth. The programmable gain amplifier can include similar constituents as the embodiment set forth in FIG. 3B. To that extent, like constituents will be referred to by the same reference character, but with the first digit being a “4” instead of a “3.” 
         [0104]    The programmable gain amplifier circuit of FIG. 4B is designated by the general reference character  400   b . The programmable gain amplifier circuit  400   b  of FIG. 4B can be different than the programmable gain amplifier of FIG. 3B in that the capacitive switching circuit  404   b  may have a different value. Capacitive switching circuit  404   b  can be a capacitor that can have the value of a−x.  
         [0105]    The sum of the capacitive value of the capacitive switching circuits ( 404   b  and  406   b ), which may be a−x+2x+1=a+x+1, can be the numerator in the overall gain equation. The denominator in the overall gain equation can be given by the capacitance value of the capacitive switching circuit  404   b , which may be a−x. Thus, the overall gain can be (a+x+1)/(a−x).  
         [0106]    To provide yet another gain approximations, a third approach is shown in FIGS. 5A and 5B. Like the example of FIGS. 3A and 3B, overall gain steps for the programmable gain amplifier may be divided into alternating even and odd steps. A circuit configurations for even steps is shown in FIG. 5A, and can have a gain of (a+x)/(a−x). A circuit configuration for odd steps is shown in FIG. 5B, and can have a gain of (a+x)/(a−x−1).  
         [0107]    Referring now to FIG. 5A, a schematic diagram of a programmable gain amplifier according to the present invention is set forth. The programmable gain amplifier can include similar constituents as the embodiment set forth in FIG. 3A. To that extent, lke constituents will be referred to by the same reference character, but with he first digit being a “5” instead of a “3.” 
         [0108]    The programmable gain amplifier circuit of FIG. 5A is designated by the general reference character  500   a . The programmable gain amplifier circuit  500   a  of FIG. 5A can be different than the programmable gain amplifier of FIG. 3A in that the capacitive switching circuit  504   a  can include capacitor circuits  540   a  and  542   a  that can have different values than the embodiment in FIG. 3A. Capacitor circuit  540   a  can be a capacitor that can have the value of (a−x−1) and capacitor circuit  542   a  can be a capacitor that has the value of 1. Also, the programmable gain amplifier circuit  500   a  may not have a third capacitive switching circuit.  
         [0109]    The sum of the capacitive value of the capacitive switching circuits ( 504   a  and  506   a ), which may be a−x−1+2x+1=a+x, can be the numerator in the overall gain equation. The denominator in the overall gain equation can be given by the capacitance value of the capacitive switching circuit  504   a , which may be a−x−1+1=a−x. Thus, the overall gain can be (a+x)/(a−x).  
         [0110]    Referring now to FIG. 5B, a schematic diagram of a programmable gain amplifier according to the present invention is set forth. The programmable gain amplifier can include similar constituents as the embodiment set forth in FIG. 3B. To that extent, like constituents will be referred to by the same reference character, but with the first digit being a “5” instead of a “3.” 
         [0111]    The programmable gain amplifier circuit of FIG. 5B is designated by the general reference character  500   b . The programmable gain amplifier circuit  500   b  of FIG. 5B can be different than the programmable gain amplifier of FIG. 3B in that the capacitive switching circuit  504   b  can have a different value. Capacitive switching circuit  504   b  can be a capacitor that can have the value of a−x−1.  
         [0112]    The sum of the capacitive value of the capacitive switching circuits ( 504   b  and  506   b ), which may be a−x−1+2x+1=a+x, can be the numerator in the overall gain equation. The denominator in the overall gain equation can be given by the capacitance value of the capacitive switching circuit  504   b , which may be a−x−1. Thus, the overall gain can be (a+x)/(a−x−1).  
         [0113]    While the embodiment illustrated in FIGS. 4A, 4B,  5 A, and  5 B can provide an approximate programmable exponential gain, there may be some variation in step size. More particularly, for the case of a gain range of 1 to 2, with 128 steps, a deviation in step size can be as much as 0.016 dB at the maximum gain setting.  
         [0114]    Comparison of the characteristics of the three extensions discussed above to the existing scheme, as well as an ideal characteristic, is shown in FIG. 6 in curves  600  and  602 . Curve  600  can be the ideal characteristic and curve  602  can show the three extentions of (a+x)/(a−x), (a+x)/(a−x−1), and (a+x+1)/(a−x).  
         [0115]    The comparison of the three cases near the high gain end (from curve  600  of FIG. 6) can be shown in FIG. 7. Curve  650  is an illustratation of the (a+x)/(a−x−1) case, curve  652  shows the (a+x)/(a−x) case with half-unit capacitors, and curve  654  illustrates the (a+x+1)/(a−x) case. The deviation of the approximations from the existing (a+x)/(a−x) scheme is indicated in FIG. 8 with the (a+x)/(a−x−1) data points labeled  676  and symbolized as circles, and the (a+x+1)/(a−x) data points labeled  678  and symbolized as “X” characters.  
         [0116]    The above examples illustrate particular embodiments in which a programmable gain may include a number of gain steps having different sampling and/or feedback capacitance for alternating gain steps. However, different embodiments may include different sampling and/or feedback capacitance for sets of consecutive gain steps. Particular examples of such embodiments will be described below.  
         [0117]    It is noted that while particular logarithmic approximations have been shown above, other approximations can be utilized to reduce the number of unit capacitors. For example, consider the case of doubling the gain range from 1 to 2 to a gain range of 1 to 4, utilizing 64 steps in each case. The current algorithm of (a+x)/(a−x)=4, solving for ‘a’ and plugging the result in a+x, can require 170 unit capacitors, but has a maximum deviation of 0.7 dB from the ideal. To reduce this deviation, the same algorithm can be used piecewise for a gain range of 1 to 2 as (a+x)/(a−x) and then a new algorithm, 2(a+x)/(a−x), may be used for a gain range of 2 to 4.  
         [0118]    While the above approach may have less deviation from the ideal than cases employing one approximation for an entire gain range, 256 unit capacitors may be necessary. Alternatively, gain deviation may slightly increased in order to reduce overall unit capacitors. For example, a relationship (a+x)/(a−x) may be used for a gain range of 1 to 2. A second approximation 2a/(a−x) may then be used for a gain range of 2 to 4. This may require only 128 unit capacitors and may have a maximum deviation of 0.5 dB from the ideal.  
         [0119]    In some applications, a programmable gain amplifier may include coarse gain segments that each spanned by the fine gain steps. The above approach can be utilized in such an application. As but one example, a last segment can utilize the above relationship for a gain range of 2 to 4. Preceding segment(s), however, can utilize the relationship for a gain range of 1 to 2 giving a close approximation to the required characteristics. It is noted that a function 2a/(a−x) can be implemented as 1+((a+x)/(a−x)). A programmable gain amplifier configuration for generating such a relationship is illustrated in FIG. 9. It is understood that a configuration for generating the relationship (a+x)/(a−x) was previously described.  
         [0120]    Referring now to FIG. 9, a schematic diagram of a programmable gain amplifier according to the present invention is set forth. The programmable gain amplifier can include similar constituents as the embodiment set forth in FIG. 2A. To that extent, lke constituents will be referred to by the same reference character, but with he first digit being a “9” instead of a “2.” 
         [0121]    The programmable gain amplifier circuit of FIG. 9 is designated by the general reference character  900 . The programmable gain amplifier circuit  900  of FIG. 9 is different than the programmable gain amplifier of FIG. 2 in that the capacitive switching circuit  906  has a different value than the embodiment in FIG. 2. Capacitor circuit  906  is capacitor that has the value of (a+x).  
         [0122]    The sum of the capacitive value of the capacitive switching circuits ( 904  and  906 ), which may be (a−x)+(a+x)=2a, can be the numerator in the overall gain equation. The denominator in the overall gain equation can be given by the capacitance value of capacitive switching circuit  904 , which may be a−x. Thus, the overall gain can be (2a)/(a−x).  
         [0123]    While a particular pair of algorithms have been described for different gain ranges, such algorithms should be not construed as limiting the invention thereto. It is understood that algorithms other than those described may be used to approximate particular gain ranges. As but one example, to approximate a gain range of 1 to 4, the relationship (2a+x)/(a−x) may be used. Such a function can make use of the negative x-region of the approximation. At minimum value of x (negative), the gain can be 1 and when x=0, the gain can be 2. Above a gain of 2 it can become nonlinear, and thus a different approximation may be used for such higher gains. One particular programmable gain amplifier configuration for implementing the relationship (2a+x)/(a−x) is illustrated in FIG. 10.  
         [0124]    Referring now to FIG. 10, a schematic diagram of a programmable gain amplifier according to the present invention is set forth. The programmable gain amplifier can include similar constituents as the embodiment set forth in FIG. 2A. To that extent, lke constituents will be referred to by the same reference character, but with the first digit being a “10” instead of a “2.” 
         [0125]    The programmable gain amplifier circuit of FIG. 10 is designated by the general reference character  1000 . The programmable gain amplifier circuit  1000  of FIG. 10 can be different than the programmable gain amplifier of FIG. 2A in that the capacitive switching circuit  1006  can have a different value than the embodiment in FIG. 2A. Capacitor circuit  1006  can be a capacitor that can have the value of a+2x.  
         [0126]    The sum of the capacitive value of the capacitive switching circuits ( 1004  and  1006 ), which may be (a−x)+(a+2x)=2a+x, can be the numerator in the overall gain equation. The denominator in the overall gain equation can be given by the capacitance value of the first capacitive switching circuit  1004 , which may be a−x. Thus, the overall gain can be (2a+x)/(a−x).  
         [0127]    The above embodiments have shown cases where a capacitor circuit that includes a feedback capacitance can vary in order to to achieve approximate logarithmic gain characteristics. In cases, a fixed feedback capacitance may be desirable. One way to achieve desired gains with a fixed feedback capacitance may be with the approximation log e (1+x)=˜x, |x|&lt;1. As in the previous cases, such a relationship may be realized by switched-capacitor circuits. As an example, the gain range 1 to 2 can be spanned in 64 steps by the function 1+(x/c) using 128 capacitors, with c=64. One example of such an implementation is illustrated in FIG. 11.  
         [0128]    Referring now to FIG. 11, a schematic diagram of a programmable gain amplifier according to the present invention is set forth. The programmable gain amplifier can include similar constituents as the programmable gain amplifier set forth in FIG. 2A. To that extent, like constituents will be referred to by the same reference character, but with he first digit being an “11” instead of a “2.” 
         [0129]    The programmable gain amplifier circuit of FIG. 11 is designated by the general reference character  1100 . The programmable gain amplifier circuit  1100  of FIG. 11 can be different than the programmable gain amplifier of FIG. 2A in that capacitive switching circuits  1104  and  1106  can have different values than the embodiment in FIG. 2A. Capacitor circuit  1106  can have the value of c. Capacitor circuit  1104  can have the value c.  
         [0130]    The sum of the capacitive value of capacitive switching circuits ( 1104  and  1106 ), which may be c+x, can be the numerator in the overall gain equation. The denominator in the overall gain equation can be given by the capacitance value of capacitive switching circuit  1104 , which may be x. Thus, the overall gain can be (c+x)/(c), or 1+x/c.  
         [0131]    Having described approaches to providing programmable gains, and particular circuit configurations for implementing such gains, the gain characteristics for the described approaches will now be discussed.  
         [0132]    Various characteristics of the above gain systems are illustrated in FIG. 12A, FIG. 12B, FIG. 12C, FIG. 12D, and FIG. 12E.  
         [0133]    [0133]FIG. 12A shows the (a+x)/(a−x) function characteristics, where a=106, versus an ideal exponential characteristic. In such an approach, 170 unity capacitors are used for the sample and feedback stages to approximate gains of 1 to 4. Curve  1200  represents the ideal exponential case and curve  1202  represents the approximation case. In the approximation the maximum deviation from the ideal can be 0.67 dB. FIG. 12A thus represents a conventional approach in which a single relationship is used for all gain steps.  
         [0134]    [0134]FIG. 12B shows the above-described approach of one embodiment, in which a total gain range may be subdivided into gain segments. Each gain segment includes gain steps governed by a different approximation. In particular, a two segment solution is shown. The (a+x)/(a−x) function characteristics, where a=64, are shown in the 0 to 6 dB range. From 6 to 12 dB, the 2a/(a−x) function characteristics, where a=64, is shown. Curve  1210  represents the ideal exponential case and curve  1212  represents the approximation case whereby the maximum deviation from the ideal is 0.48 dB.  
         [0135]    [0135]FIG. 12C shows yet another example in which a total gain range may be subdivided into gain segements. Again, each gain segment can include a number of gain steps governed by different relationships. In particular, for a gain range of 0 to 6 dB, a relationship (a+x)/(a−x) may be employed. However, for a gain range of 6 to 12 dB, a relationship of 2(a+x)/(a−x) may be used. Curve  1220  represents the ideal exponential case and curve  1222  represents the approximation case whereby the maximum deviation from the ideal is 0.08 dB.  
         [0136]    In FIG. 12D, the 1+(a+2x)/(a−x)=(2a+x)/(a−x) function characteristics, where a=64, are shown for the 0-12 db range. Curve  1230  represents the ideal exponential case and curve  1232  represents the approximation case whereby the maximum deviation from the ideal in the 0-6 dB range is 0.26 dB. It becomes non-linear in the 6 to 12 dB range with a maximum deviation of 1.66 dB. Thus, a relationship such as that shown in FIG. 12D may be used for a one range (0-6 dB), while another relationship may be used for higher gain ranges.  
         [0137]    In FIG. 12E, the 1+(x/c) function characteristics, where c=64, in the 0 to 6 dB range are shown. Curve  1240  represents the ideal case and curve  1242  represents the approximation case whereby the maximum deviation from the ideal is 0.52 dB.  
         [0138]    The above embodiments have shown approaches to configuring programmable gain amplifiers that may reduce the number of capacitors required to provide a given number of gain steps, or a particular gain range. Reducing capacitors can lead to a reduction in power consumption, or faster circuit operation, or reductions in circuit area. Such improvements may be a significant advantage over existing methods.  
         [0139]    The above embodiments have shown approaches to obtaining exponential gain variations with a linearly varying input code. However, such embodiments are illustrative of the principles of the present invention and are not intended to limit the invention to the particular embodiments described. For example, those skilled in the art, in light of this disclosure, can implement, without undue experimentation, other embodiments of this method that are different from those described, but achieve the same or an equivalent function. Accordingly, while the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.