Abstract:
A recurring analog signal is digitized by repeatedly comparing it to a reference level, or to several reference levels, during each signal occurrence to determine where the signal has a value related to each reference level. The reference level, or levels, are changed between signal occurrences but remain constant during each occurrence. Digitization is completed after several occurrences of the signal have been analyzed in this manner.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to analog-to-digital converters, and particularly to techniques for digitizing a recurring analog signal containing high frequency components. 
     Various circuit arrangements presently used in sampling oscilloscopes can determine the amplitude of many points on a high frequency analog signal. One disadvantage of these methods is that only one sample is obtained for each repeat of the signal. If a large number of samples is required, the total time involved may be unacceptably long. 
     Various circuit arrangements, known as analog-to-digital flash converters, have been used to digitize high frequency waveforms in a single occurrence of the signal. One disadvantage of these methods is that a large number of comparators, divider components, and logic circuits are required. If the amplitude of each sample of the analog signal is to be determined to one part in 32, for example, than 32 high speed comparators are needed. The circuit becomes complex and expensive. 
     Various circuit arrangements known as successive approximation analog-to-digital converters have been used to digitize moderate frequency waveforms. One disadvantage of these methods is that the digitization rate is comparatively slow. 
     A principal object of this invention is to provide high sampling rate digitization of a repetitive analog signal with reduced complexity and expense and without the above mentioned disadvantages of existing methods. 
     SUMMARY OF THE INVENTION 
     Briefly, this and additional objects of the present invention are accomplished by a method of converting a repetitive analog signal into a digital signal wherein each occurrence of the analog signal is compared with one or more distinct reference voltage levels. The analog signal is so compared at distinct intervals throughout its occurrence and one or more digital bits of information is recorded at each comparision as to the value of the analog signal with respect to the reference level or levels. This is repeated for a number of successive occurrences of the analog signal until the reference voltages used have scanned the full voltage range of the analog signal. The digital bits of data so obtained can be used for any purpose, including the reconstruction of the analog signal on an oscilloscope. This technique can be implemented by an electronic circuit having only one or two comparators for comparing the analog signal to the reference voltages. Additional comparators may be used to reduce the total conversion time but at the expense of additional comparators and high speed memory capacity. 
    
    
     Additional objects, advantages and features of the various aspects of the present invention will become apparent from the following description of its preferred embodiments which should be taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a preferred embodiment of the present invention; 
     FIG. 2 is a timing diagram showing waveforms at various points in the circuit of FIG. 1; 
     FIG. 3 illustrates data stored in a memory of the circuit of FIG. 1; 
     FIG. 4 illustrates the processing in a memory of another embodiment of the present invention which utilizes a modified version of the circuit of FIG. 1; and 
     FIGS. 5 and 6 are software flow diagrams for the microprocessor control of the embodiment of FIGS. 1-3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring initially to FIG. 1, a particular circuit implementation of the preferred embodiment of the present invention will be described. A terminal 11 receives, with respect to some common potential, a repetitive analog signal that is desired to be digitized. An example of such a signal used to explain the operation of the circuit hereinafter is shown in FIG. 2(A). The terminal 11 is connected to the input of a unity gain amplifier 13 whose output is connected to non-inverting inputs of comparators 15, 17 and 19. The comparators 15 and 17 are utilized to compare the voltage reference levels with the analog input signal at the terminal 11 as a first step in the digitization process. The comparator 15 receives a reference voltage &#34;REF 1&#34; through a line 21 connected to its inverting input. Similarly, the comparator 17 has a refernce voltage &#34;REF 2&#34; applied through a line 23 to its inverting input. Output levels A and A of the comparator 15 are applied to a dot logic circuit 25. Similarly, output levels C and C of the comparator 17 are applied to the dot generator 25. 
     The operation of this portion of the circuit of FIG. 1 can best be seen by reference to FIG. 2(A). During a first occurrence of the repetitive analog signal 27, it is compared with a reference voltage window 29 that extends between voltage levels V1 and V2. The voltage V1 is one of the reference voltages in the lines 21 and 23 of FIG. 1 and V2 is the reference voltage in the other of those lines. The dot generating circuit 25 receives a clock signal represented in FIG. 2(B) through a clock signal line 31 of FIG. 1. At each clock pulse in the line 31, a &#34;0&#34; or &#34;1&#34; digital bit appears at an output line 33 of the circuit 25 depending upon whether at that clock time the analog signal 27 is within or without the voltage window 29. For this example, a digital bit &#34;1&#34; signifies that the analog signal 27 is within the reference voltage window and the digital bit &#34;0&#34; indicates that it is without the window at that clock time. The circuit 25 has the further logic capability of having an output of a digital &#34;1&#34; at the output line 33 when the analog signal 27 has passed through the window since the last clock pulse, even though it does not exist in the window simultaneously with the current clock pulse. This latter feature avoids any errors that might occur from the analog signal 27 passing through the window between clock pulses, and thus which might normally be undetected. 
     Referring to FIG. 2(A), a reference voltage window 35 is established during a subsequent occurrence of the analog signal 27 and that occurrence is similarly sampled through the use of the clock pulses to develop at the line 33 a series of digital bits, as discussed before. The window 35 extends between voltage ranges immediately below that of the prior window 29. The window 35 is formed by changing the voltage reference level V1 that existed on one of the lines 21 and 23 during the first occurrence, to a voltage level V3 during the second occurrence. Similarly, on the third occurrence, the voltage level V2 on one of the lines 21 and 23 is changed to a voltage level V4 to form a third window 37 that is immediately below the level 35. 
     This process of &#34;leap frogging&#34; the reference voltages in the lines 21 and 23 between successive occurrences continues until the full voltage range of interest of the analog signal 27 has been covered. The sampling occurring at each occurrence of the analog signal 27 produces a string of digital bits that are first stored in a high speed memory 39 directly from the line 33. In the time interval between the occurrences of the analog signal 27, in the particular example being described, this string of data is moved from the high speed memory 39 to a random access memory 41, thus emptying the memory 39 to receive another string of digital bits resulting from the comparison process during the next occurrence of the analog signal 27. Each string of samples is so stored in the memory 41 until, after the analog signal 27 has been completely traversed by reference voltage windows, the memory 41 contains all of the bits in a pattern illustrated in FIG. 3. FIG. 3 is a simplified diagram. In the preferred embodiment, there are 200 bits horizontally and 39 bits vertically. By way of explanation, the top row 29&#39; of bits was obtained during the first occurrence illustrated in FIG. 2(A) by comparing the analog signal 27 with the reference window 29. Similarly, the row 35&#39; of bits was obtained during the second occurrence with the use of the reference window 35, and so forth. It will be noted that the pattern of digital &#34;1&#39;s&#34; in FIG. 3 follows the analog waveform of the signal 27. This pattern is used by display electronics 43 to drive a cathode ray tube 45 to reconstruct the waveform of the analog signal 27 from the digital data stored in the memory 41. The cathode ray tube 45 is scanned in a raster pattern by vertical and horizontal scanning signals, respectively, in lines 47 and 49. The intensity of the beam is modulated through a line 51 in a manner that the beam is permitted to become bright in response to a digital &#34;1&#34; being read out of the memory 41. Thus, as the information pattern of FIG. 3 is read out of the memory 41 in a line by line manner in synchronization with the raster scanning of the electron beam of the cathode ray tube 45, the analog waveform 27 is reconstructed on the face of the cathode ray tube. This has been done without the need for the usual digital to analog converter. 
     In a particular example, the analog signal 27 is scanned in the &#34;leap frog&#34; manner described previously with a reference voltage from the top of the signal to its lower voltage extreme in thirty-nine increments, the reference windows do not need to move continuously from one extreme to the other of the analog signal 27 but rather the windows could move in some other pattern. A clock frequency in the line 31, and as illustrated in FIG. 2(B), could be 100 MHz, as an example. If the time duration of each occurrence of the analog signal 27 is ten micro-seconds, then 1000 samples would be taken during each occurrence. The high speed memory 39 may conveniently have a capacity of 1024 bits. Of course, the techniques being described herein may be applied to a wide variety of specific parameters and situations. 
     The analog signal 27 will normally repeat itself enough times without changing to complete the conversion. But another advantage of this window technique applies to signals varying from one occurrence to another. All various waveforms present will be shown in their true form in proportion to their relative frequency of occurrence. Other existing techniques show only one of multiple waveforms present or some composite waveform that does not represent any of the analog signals present. 
     The dot generator 25 of FIG. 1 contains logic elements in the form of two flip-flops 53 and 55, inverting OR gates 57, 59, 61 and 63, and an OR gate 65. The outputs A and C of the comparators 15 and 17, respectively, drive the flip-flops 53 and 55. All four output signals from the comparators 15 and 17, and the outputs of the flip-flops 53 and 55, are combined in the inverting OR gates 57-63. The outputs of these OR gates are, in turn, combined in an OR gate 65 whose output in the line 33. The line 33 gives the resulting signal described hereinbefore. 
     As is typically being done in modern circuit design, a microprocessor board 67 is utilized in place of hard wired electronic components in order to provide flexability and a reduced number of components with a resulting reduction in cost. The microprocessor board 67 contains a microprocessor and associated memory elements containing controlling programs. The microprocessor communicates with other circuit elements through a microprocessor bus 69. One of the functions accomplished by the microprocessor is to transfer a string of data bits from the high speed memory 39 to the random access memory 41. The microprocessor can at the same time do any processing that is necessary of the data, such as expanding or contracting the number of bits in the high speed memory 39 to fit the matrix of FIG. 3 that is desired to be formed in the memory 41. The display electronics 43, accesses the memory 41 to produce the X, Y and Z signals in the lines 47, 49 and 51. 
     Many other circuits are connected directly to the microprocessor bus 69. Front panel switches 71 are so connected and the programmed microprocessor periodically examines the state of these switches to see if an operator is calling for any particular function of the apparatus to be performed. A system clock oscillator 73 is operated from the bus 69 and also provides the microprocessor board 67 with a clock signal through a line 75. Decoding circuits 77 provide certain controlling signals to other circuit elements, to be described hereinafter. Similarly, encoding circuits 79 convert at least one signal into an appropriate digital code for communication with the microprocessor over the bus 69. 
     A digital to analog converter 81 is also connected to the bus 69 and provides at an output line 83 analog voltage levels that are responsive to particular digital codes communicated to it by the microprocessor 67 on the bus 69. These voltages bevels are applied to three different sample and hold circuits 85, 87 and 89. Outputs of the two sample and hold circuits 85 and 87 provide the reference voltages simultaneously in the lines 21 and 23 which, are described above, are utilized to establish the voltage windows for digitizing the analog signal 27. The sample and hold circuits are actuated by control lines 91, 93 and 95 from the decoding circuit 77. The combination of the digital to analog converter 81 and the sample and hold circuits permits three reference voltage levels to be controlled by the microprocessor, the two in the lines 21 and 23, and another in a line 97, with the use of a single digital to analog converter. Such converters are expensive so this arrangement has the advantage of reducing the cost of the apparatus. When the microprocessor 67 wants to set a particular voltage on one of the lines 21, 23 or 97, it places a digital code for that voltage on the bus 69 and the digital to analog converter 81 generates that voltage in the line 83. The microprocessor then submits a signal in the bus 69 appropriate to be decoded by the circuit 77 to enable the appropriate sample and hold circuits 85, 87 or 89 so that this voltage in the line 83 will then appear at its output. That is how the reference voltages &#34;REF 1&#34; and &#34;REF 2&#34; are manipulated in the manner described earlier with respect to FIG. 2(A). 
     Synchronization &#34;trigger&#34; pulses are utilized in order to make the various functions that have been described occur in an orderly fashion. The circuit illustrated in FIG. 1 has a capability of being synchronized to an external trigger signal applied to a terminal 101, or to an internally generated trigger signal developed by the comparator 19 from the analog signal 27. The external trigger is applied through a unity gain amplifier 103 to a noninverting input of a comparator 105. The inverting inputs of both the internal trigger comparator 19 and the external trigger comparator 105 are connected to the line 97 which is the output of the third sample and hold circuit 89. The voltage set in the line 97, under microprocessor control as described previously, determines the threshold voltage for detecting when a trigger signal occurs. 
     The inverting and non-inverting outputs of the internal trigger comparator 19 and external trigger comparator 105 are applied to a trigger source and slope selecting circuit 107 which is controlled by signals through a line 109 from the decoding circuit 77. The circuit 107 selects either the external trigger or the internal trigger by connection to the appropriate comparator 105 or 19, respectively. It also selects whether an enable signal in the line 111 will be initiated on a positive going or negative going slope of either the external trigger pulse or the analog signal 27, depending upon which is selected as the trigger source. The signal in the line 111 enables a trigger delay counter 113 to increment in response to a clock signal in the line 31. An overflow of the counter 113 is communicated through a line 115 as a &#34;EOS&#34; signal to both the high speed memory 39 and the encoding circuitry 79 for communication through the bus 69 to the microprocessor 67. The purpose of the counter 113 is to set the duration A of the occurrences of the analog signal 27 that is examined, as illustrated in FIG. 2. 
     To explain the operation of the triggering circuit, an external trigger pulse train is illustrated in FIG. 2(C). This is the signal that is applied to the terminal 101 of FIG. 1. Such a trigger signal is available in many types of circuits along with the analog signal 27. This is particularly true when the techniques of the present invention are utilized to examine analog signals occurring in logic circuits of various types in the course of troubleshooting such circuits. Logic circuits usually will have a synchronizing trigger pulse, such as that shown in FIG. 2(C), which is in synchronism with the occurrences of the analog signal 27. The pulses of FIG. 2(D) represent the &#34;EOS&#34; signal in the line 115 and is set in time a distance C from the trigger pulse through the delay of the counter 113. That delay is set upon command of the microprocessor through its bus 69 which is connected to the counter 113. The microprocessor presets the counter at a certain number so that when it is enabled with the pulse in the line 111 at the occurrence of a trigger pulse at the terminal 101, the counter will have a set number of clock pulses 31 to run before the overflow &#34;EOS&#34; signal in the line 115 is emitted. 
     The high speed memory 39 is of a type which, when clocked, stores the last 1024 bits of information given it through the line 33. When it is full, new incoming bits of information replace the oldest bits remaining in the memory 39. In order to stop this process in the memory, it responds to the &#34;EOS&#34; signal in the line 115 to freeze the data therein for a time. Once stopped, the memory 39 will receive no further information from the line 33 until those frozen bits of information are transferred from the memory 39 to the random access memory 41, as previously described. This transfer occurs during the interval B between occurrences of the analog signal 27, as shown in FIG. 2(A). If the interval B is not long enough to permit this data transfer to be completed, one or more occurrences of the analog signal will be skipped. This operation of the high speed memory 39 sets the occurrence duration A of FIG. 2(A) to a maximum of the capacity of the memory, herein being described to be 1024 bits. The duration A of the analog signal occurrence being examined can be altered by changing the sampling frequency (clock signal 31) or by changing the number of data bits utilized from the high speed memory 39. 
     It is preferred to compare each occurrence of the analog signal 27 with only a single window. The duration for converting that signal to a digital one is not prohibitively long if the analog signal is of a high frequency. The advantage is a reduced hardware complexity in cost since only two comparators 15 and 17 are required for this process. Of course, if the speed is desired to be increased, additional comparators, dot generation circuits and high speed memory could be employed to analyze a plurality of windows at each occurrence of the analog signal. The particular trade off between speed and hardware cost depends upon the particular application but still provides advantages over the prior art techniques. 
     An even simpler hardware scheme may be had by eliminating one of the comparators 15 or 17, and eliminating the dot generator 25. That is, one of the comparators 15 or 17 could be connected directly to the high speed memory 39 through the line 33, according to this alternate embodiment. The bits of information stored in the memory 39 would be of one state, say the digital bit &#34;1&#34;, when the analog signal 27 was below the threshold set on the single comparator. Conversely, the bit that would be recorded for a given clock pulse could be a &#34;0&#34; if the analog signal were greater than the threshold at a particular instant. 
     This alternate technique would provide a plurality of digital words which, in a conventional sense, could be applied to a digital to analog converter and from there directly to a standard cathode ray tube oscilloscope. The way this is done is illustrated in FIG. 4 wherein a first row of numbers 121 represents a maximum standardized value of the analog signal 27. The number forty is utilized in FIG. 4 as a convenient number for when there are thirty-nine different voltage thresholds set on the single comparator and the data is obtained over a corresponding thirty-nine occurrences of the analog signal. 
     A second row 123 of numbers represents the bits of information inputted to the memory 39 upon the first occurrence of the analog signal. What the microprocessor 67 does when it transfers this data into the memory 41 is to subtract one from the initial value forty for each place that a digital &#34;1&#34; occurs. This results in a third line 125 of numbers resulting from this intermediate step. A fourth line 127 represents data obtained during the second occurrence of the analog signal 27 in the line of numbers 129 of FIG. 4 gives a resulting intermediate set of numbers which is stored in the memory 41. This process continues through all thirty-nine, or other number, of occurrences until a set of numbers 131 representing in digital form the value of the analog signal 27 remain in the memory 41. These digital words can then be displayed through a digital to analog converter in a conventional manner. This alternate technique has the advantage of requiring a memory 41 of much less capacity than in the preferred embodiment described earlier in detail. 
     The software controlling the microprocessor 67 in the preferred embodiment described earlier with respect to FIGS. 1-3 is shown in FIGS. 5 and 6, with the actual controlling program coding being attached to this application as an Appendix. Since the techniques described herein form only a part of an actual instrument that has been designed to do many other functions as well, the program of the attached Appendix includes instructions in addition to those which are required to carry out the techniques of the present invention. Therefore, the flow chart of FIG. 5, from which the program coding has been made, has been reproduced to include portions which are not necessary to practice the present invention, as well as those portions which are used in practicing the invention. The unnecessary portions of FIG. 5 are overlayed with cross-hatching. 
     When the circuits are not being utilized to perform a test, the microprocessor is programmed to be in a mode to sequentially interrogate the various front panel switches 71 to see if some function or command is initiated by an operator of the instrument. If a trigger control switch is operated, the microprocessor then goes through the routines illustrated by the software flow charts of FIGS. 5 and 6. The notations and terminology of the flow chart are the same as and keyed to that on the program listings themselves attached hereto as an Appendix. The functions of block 14Ul of FIG. 5 are shown in expanded form in the flow chart of FIG. 6. The functions illustrated in FIG. 6 pertain to the technique of comparing the analog signal 27 to reference voltage windows, as described with respect to the circuit of FIG. 1 and the waveforms of FIG. 2(A). 
     Although the various aspects of the present invention have been described with respect to its preferred embodiments, it will be understood that the invention is entitled to protection within the full scope of the appended claims. ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6## ##SPC7## ##SPC8## ##SPC9## ##SPC10## ##SPC11##