Abstract:
A method and apparatus for reducing leakage current in an integrated circuit includes a supply voltage line, a virtual supply voltage line, a ground voltage line, a virtual ground voltage line, a first logic circuit coupled to the ground voltage line and selectively coupled to the virtual supply voltage line, a second logic circuit coupled to the supply voltage line and selectively coupled to the virtual ground voltage line, and a switch circuit configured to control the selective coupling of the first logic circuit to the virtual supply line voltage and the second logic circuit to the virtual ground voltage line.

Description:
TECHNICAL FIELD 
     This invention relates to reducing leakage currents in integrated circuits. 
     BACKGROUND 
     Standby leakage current is the current which may flow through a logic circuit when a transistor within the circuit is at high impedance and attempting to hold an output voltage at a certain level. Standby leakage current can cause a loss of the signal output and can also increase power consumption of the logic circuit. 
     Referring to FIG. 1, an approach to reducing standby leakage current in CMOS circuits was proposed in Mutoh, et al., “1- V Power Supply High-Speed Digital Circuit Technology with Multithreshold - Voltage CMOS ”, IEEE Journal of Solid-State Circuits, Vol. 30, No.8, August 1995, pp. 847-854. Mutoh, et al, proposed a CMOS logic circuit  100  including a series of CMOS logic gates  102 A- 102 B. Logic circuit  100  includes ‘sleep’ transistors Q 1  and Q 2 , which are connected between the supply voltage, Vdd, and common ground, GND, respectively, to establish ‘virtual’ supply lines, VDDV and GNDV. The source terminals  104 A- 104 B of the p-block transistors of each CMOS logic gate  102 A- 102 B are connected to VDDV, while the source terminals  106 A- 106 B of the n-block transistors are connected to GNDV. By P-block (or N-block) is meant a circuit that includes one or more p-channel (or n-channel) transistors. 
     In operation, in ‘sleep mode’, SL  120  is at logic-level ‘1’, which turns off the sleep transistors Q 1  and Q 2  and cuts off the leakage current that would otherwise pass through the logic gates  102 A- 102 B. In ‘active mode’, SL  120  is at logic-level ‘0’, turning on Q 1  and Q 2 , allowing the logic gates  102 A- 102 B to evaluate. When in ‘active’ mode, the sleep transistors produce a VDDV which is lower than Vdd due to a voltage drop through Q 1 , and produce a GNDV which is higher than common ground due to a voltage drop through Q 2 . As a result, the effective voltage seen by the logic circuits  102 A- 102 B is less than the difference between Vdd and common ground. This lower effective voltage increases the evaluation time of CMOS logic gates  102 A- 102 b and therefore reduces the overall speed of the logic circuit  100 . 
    
    
     DESCRIPTION OF DRAWINGS 
     FIG. 1 is a schematic representation of a known way of reducing leakage current in CMOS gates. 
     FIG. 2 is a schematic representation of a first embodiment. 
     FIG. 3 is a schematic representation of a second embodiment. 
     Like reference symbols in the various drawings indicate like elements. 
    
    
     DETAILED DESCRIPTION 
     So-called ‘domino circuits’ describe a series of similarly constructed logic blocks within an integrated circuit. Often, the output of one logic block within a domino circuit is connected to the input of the another logic block within the domino circuit. 
     Referring to FIG. 2, domino circuit  200  includes blocks of dynamic gates  210 A- 21 ON and blocks of static gates  220 A- 220 N with the outputs  280 A- 280 N of the dynamic gates  210 A- 210 N connected, respectively, to the inputs of static gates  220 A- 220 N. The ‘dynamic’ gates  210 A- 210 N include n-channel transistors, N-Block  212 A- 212 N, which are first pre-charged and then perform logical functions during an evaluation phase. 
     In an embodiment according to the invention, domino logic circuit  200  includes ‘standby’ transistors Q 1  and Q 2  connected to Vcc and Vss, respectively, and establishing ‘Virtual Vcc’ and ‘Virtual Vss’ lines. 
     The dynamic blocks  210 A- 210 N are connected at source terminals  230 A- 230 N of transistors P 1 A-P 1 N to ‘virtual Vcc’ and are connected to ground, Vss, at source terminals  240 A- 240 N of N-block  212 A- 212 N. Static blocks  220 A- 220 N are connected at source terminals  250 A- 250 N of P-blocks  222 A- 222 N to Vcc, and are connected at source terminals  260 A- 260 N of N-blocks  224 A- 224 N to ‘virtual Vss’. In ‘active’ mode, SL is at ‘0’, and standby transistors Q 1  and Q 2  are turned on, allowing dynamic blocks  210 A- 210 N to pre-charge and evaluate the  206 A- 206 N input signals, and static blocks  220 A- 220 N to evaluate the  130 A- 130 N input signals. 
     To understand the operation of domino logic circuit  200 , consider the following example of the operation of dynamic block  210 A and static block  220 A. Dynamic block  210 A alternates between pre-charge and evaluation phases, according to signal CLK  204 , as will be explained. The evaluation time of the dynamic block  210 A is largely determined by the transition time of N-block  212  ‘pull-down’ transistors. Because source terminal  240 A of N-Block  212  transistors are connected to Vss, the evaluation time of dynamic block  220 A is not increased significantly by the virtual Vcc connection  230 A to P 1 . Similarly, the evaluation time of static block  220 A is largely determined by the transition time of P-Block  222  ‘pull-up’ transistors. Because source terminal  260 A of P-block  222  transistors are connected to Vcc, the evaluation time of the static block  220 A is not increased significantly by the virtual Vss connection  250 A to N-Block  224 . In ‘standby’ mode, SL is at ‘1’, and Q 1  and Q 2  are off, so that the leakage current that would otherwise flow through dynamic block  210 A is significantly reduced by sleep transistor Q 1  being off. Likewise, the leakage current that would otherwise flow through static block  220 A is significantly reduced by Q 2  being off. Therefore, the domino circuit  200  reduces leakage current while maintaining high speed in domino circuits. 
     For an integrated circuit, such as a microprocessor, circuit  200  may be placed in ‘active’ mode for several successive pre-charge and evaluation phases of blocks  210 A- 210 N and  220 A- 220 N and then placed in ‘standby’ mode for long periods of time. Alternatively, the sleep transistors could be turned on and off before and after each successive evaluation phase. 
     To understand the operation of dynamic blocks  210 A- 210 N and static blocks  220 A- 220 N during pre-charge and evaluation phases, consider the following example of the operation of dynamic block  210 A and static block  220 A. In operation, in ‘active’ mode, SL  270  is at logic-level ‘0’, and Q 1  and Q 2  are on. Therefore, Q 1  is ready to ‘pull-up’ dynamic block  210 A, and Q 2  is ready to ‘pull-down’ static block  220 A. During the pre-charge phase of dynamic block  210 A, CLK  204  goes to ‘0’, P 1  is turned on, pre-charging (‘pulling up’) the output  280 A to ‘virtual Vcc’. During the evaluation phase of dynamic block  210 A, CLK  106  goes to ‘1’, P 1  is turned off, and the output voltage  280 A of N-block  212  is either discharged by the N-block  212  transistors or left high depending on the INPUT  206  signals to N-block  212 . Static block  220 A can now evaluate input  280 A from dynamic block  210 A, because Q 2  is already on and ready to pull-down N-Block  224  p-channel transistors depending on the evaluation of input  280 A. Output  290 A, from static block  220 A is then delivered to the next dynamic block,  210 B. 
     Referring to FIG. 3, a circuit  300  includes a series of primary CMOS logic blocks  310 A- 310 N and secondary CMOS logic blocks  320 A- 320 N, with the outputs  380 A- 380 N of primary block  310 A- 310 N connected, respectively, to the inputs of secondary logic blocks  320 A- 320 N. The outputs  390 A- 390 N of the secondary logic blocks  320 A- 320 N are connected to the inputs  306 B- 306 N of other primary logic blocks  310 B- 310 N. 
     Domino logic circuit  300  includes ‘standby’ transistors Q 1  and Q 2 , connected at their source terminals to Vcc and Vss, respectively, and establishing ‘Virtual Vcc’ and ‘Virtual Vss’ lines. Primary blocks  310 A- 310 N are connected at source terminals  330 A- 330 N of P-Block  314 A- 314 N to ‘virtual Vcc’, and connected to ground, Vss, at the source terminals  340 A- 340 N of N-block  312 A- 312 N. Secondary blocks  320 A- 320 N are connected at source terminals  350 A- 350 N of P-block  322 A- 322 N to Vcc, and connected at source terminals  360 A- 360 N of N-block  324 A- 324 N to ‘virtual Vss’. In ‘active’ mode, SL is at logic-level ‘0’, and standby transistors Q 1  and Q 2  are turned on, allowing primary blocks  310 A- 310 N to evaluate input  306 A- 306 N, and secondary blocks  320 A- 320 N to evaluate input  380 A- 380 N input signals. To explain the operation of circuit  300 , consider the following example of the operation of primary block  310 A and secondary block  320 A. 
     Output  380 A is first pre-set to a logic-level ‘1’ by setting input  306 A to ‘0’. Therefore, output  380 A of primary block  310 A can only make a ‘1’-to-‘0’ transition. Output  380 A at ‘1’ sets the output  390 A of CMOS block  320 A to ‘0’. Therefore, secondary block  320 A can only make a ‘0’-to-‘1’ transition at output  390 A. The evaluation time of primary block  310 A during a ‘1’-to-‘0’ transition at output  380 A, is largely determined by the transition time of N-Block  312 A transistors. Because source terminals  340 A of N-Block  210 A are connected to Vss, the evaluation time during a ‘1’-to‘0’ transition of primary block  310 A is not increased significantly. Similarly, the evaluation time of secondary block  320 A during a ‘0’-to-‘1’ transition at output  390 A, is largely determined by the transition time of P-Block  322 A transistors. Because source terminals  350 A of P-Block  322 A transistors are connected to Vcc, the evaluation time during a ‘0’-to‘1’ transition of secondary block  320 A is not increased significantly. 
     In ‘standby’ mode, SL is ‘1’, Q 1  and Q 2  are off, so that the leakage current that would otherwise flow through primary block  310 A is significantly reduced by sleep transistor Q 1  being off. Likewise, the leakage current that would otherwise flow through secondary block  320 A is significantly reduced by Q 2  being off. Therefore, circuit  300  reduces leakage current while maintaining high speed in domino-CMOS circuits. 
     Several separate domino circuits, such as those shown in FIG.  2 . and FIG. 3, could be included on a single integrated circuit. Each domino circuit could then be controlled separately, i.e., each domino circuit being put into ‘sleep’ or ‘active’ mode as required.