Abstract:
A semiconductor memory device is provided that is capable of increasing a data processing speed and the efficiency of a data input and output pin. A method is also provided for controlling the read and write of such a device. A data first-in first-out (FIFO) circuit temporarily stores write data when a read command is received during a write operation and outputs the stored write data to the memory cell array after a read operation is completed. An address FIFO circuit temporarily stores addresses corresponding to the write data when the read command is received during the write operation and outputs the stored addresses to the memory cell array after the read operation is completed. A control signal generator generates a plurality of control signals for controlling the data FIFO circuit and the address FIFO circuit in response to a write command and the read command. When the addresses received during the read operation coincide with the addresses stored in the address FIFO circuit, data is not output from the memory cell array, but instead, the write data stored in the data FIFO circuit is output. The number of write data items stored in the data FIFO circuit and the number of addresses stored in the address FIFO circuit vary according to the column address strobe (CAS) latency of the semiconductor memory device.

Description:
This application relies for priority upon Korean Patent Application No. 99-11826, filed on Apr. 6, 1999, the contents of which are herein incorporated by reference in their entirety. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device, and more particularly, to a double data rate synchronous DRAM (DDR SDRAM) and a method for controlling read and write operations of a DDR SRAM. 
     In a single data rate synchronous DRAM (SDR SDRAM), the input and output of data through a data input and output pin DQ is performed at the rising edge of a clock. In the DDR SDRAM, the input and output of data through The data input and output pin DQ is performed at the rising and falling edges of the clock. 
     In general, the amount of data processed in one clock cycle is called a prefetch unit. The prefetch unit of the SDR SDRAM is 1. The prefetch unit of the DDR SDRAM is 2. FIG. 1 is a timing diagram for comparing the data processing speed and the efficiency of the data input and output pin DQ in the SDR SDRAM with the data processing speed and the efficiency of the data input and output pin DQ in the DDR SDRAM. Here, a case where the CAS latency (CL) is 2.5 and the burst length (BL) is 4 is shown. 
     In an arithmetical sense, since a DDR SDRAM processes twice the data of a SDR SDRAM in one clock cycle, the processing speed of the DDR SDRAM should be double that of the SDR SDRAM. However, the processing speed of the DDR SDRAM is not double the processing speed of the SDR SDRAM. Namely, as shown in FIG. 1, in the DDR SDRAM, the read command (RD) should be received after write data D 0  through D 3  are completely written. 
     In other words, the read command RD should be received after the lapse of a write recovery time (t WR ), and read data Q 0  through Q 3  are output after the lapse of clock cycles corresponding to the CAS latency after the read command RD is received. Thus, the processing speed of the DDR SDRAM is not double the processing speed of the SDR SDRAM. Accordingly, the efficiency of the data input and output pin DQ in the DDR SDRAM is lower than the efficiency of the data input and output pin DQ in the SDR SDRAM. Referring to FIG. 1, the efficiency of the data input and output pin DQ in the SDR SDRAM is 67% and the efficiency of the data input and output pin DQ in the DDR SDRAM is 44%. 
     SUMMARY OF THE INVENTION 
     To solve the above problem, it is an object of the present invention to provide a DDR SDRAM capable of improving the data processing speed and the efficiency of The data input and output pin DQ. 
     It is another object of the present invention to provide a method for controlling the read and write of the DDR SDRAM that is capable of improving the data processing speed and the efficiency of the data input and output pin DQ. 
     Accordingly, to achieve the first object, the DDR SDRAM according to the present invention comprises a memory cell array storing memory data, a data storage circuit to temporarily store write data when a read command is received during a write operation and to output the stored write data to the memory cell array after a read operation is completed, an address storage circuit to temporarily store write addresses corresponding to the write data when the read command is received during the write operation and to output the stored write addresses to the memory cell array after the read operation is completed, and a control signal generator for generating a plurality of control signals for controlling the data storage circuit and the address storage circuit in response to a write command and the read command, wherein the write data stored in the data storage circuit is output when read addresses received during the read operation coincide with the write addresses stored in the address storage circuit. 
     Preferably, the data storage circuit and the address storage circuits are both first-in first-out buffers. In addition, the number of write data items stored in the data storage circuit preferably varies according to the CAS latency of the semiconductor memory device. Similarly, the number of addresses stored in the address storage circuit preferably varies according to the CAS latency of the semiconductor memory device. 
     The DDR SDRAM may also comprise a data input and output pin for providing the write data to the data storage circuit. In addition, the DDR SDRAM may also comprise a selector circuit connected to the memory array and the data storage circuit, for receiving the write data stored in the data storage circuit and outputting the received write data through the data input and output pin when the read addresses received during the read operation coincide with the write addresses stored in the address storage circuit, and for receiving the memory write data stored in the memory array and outputting the received memory data through the data input and output pin when the read addresses received during the read operation does not coincide with the write addresses stored in the address storage circuit. 
     To achieve the second object, the method for controlling the read and write of the DDR SDRAM according to the present invention comprises temporarily storing write data when a read command is received during a write operation and outputting the stored write data to the memory cell array after a read operation is completed, temporarily storing addresses corresponding to the write data when the read command is received during the write operation and outputting the stored addresses to the memory cell array after the read operation is completed, and comparing read addresses during the read operation with the stored addresses and outputting the stored write data rather than the data of the memory cell array when the read addresses during the read operation coincide with the stored addresses. 
     Preferably, the number of stored write data items and the number of stored addresses varies according to the CAS latency of the semiconductor memory device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: 
     FIG. 1 is a timing diagram for comparing the data processing speed and the to efficiency of a data input and output pin (DQ) in an SDR SDRAM with the data processing speed and the efficiency of the data input and output pin in a DDR SDRAM; 
     FIG. 2 is a block diagram of the DDR SDRAM according to a preferred embodiment of the present invention; 
     FIG. 3 is a detailed circuit diagram of the control signal generator shown in FIG. 2; 
     FIG. 4 is a detailed circuit diagram of the address first-in first-out (FIFO) circuit and related circuits shown in FIG. 2; 
     FIG. 5 is a detailed circuit diagram of the data FIFO circuit shown in FIG. 2; and 
     FIGS. 6A through 6D are timing diagrams showing the operations of the DDR SDRAM according to a preferred embodiment of the present invention, shown in FIG.  2 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will be described below in detail, with reference to the attached drawings. 
     Referring to FIG. 2, a DDR SDRAM according to the present invention includes a memory cell array  21 , a data first-in first-out (FIFO) circuit  23 , an address FIFO buffer  25 , a control signal generator  27 , and a selector  29 . The DDR SDRAM according to the present invention is constituted so as to have the same CAS latency (or CAS latency-1) in a write command as the CAS latency in a read command. 
     The control signal generator  27  generates a plurality of control signals including a read control signal RC, a first write control signal WC 1 , a FIFO flag signal F FIFO , an internal write signal IW, and first through third count signals C 1  to C 3 , all for controlling the data FIFO buffer  23  and the address FIFO buffer  25  in response to an internal clock signal ICLK, while receiving a write command and a read command, to be specific, input signals RAS, CAS, WE, B RC , and B WC  The input signal RAS is the inverted signal of a row address strobe signal (/RAS) received from the outside. The input signal CAS is the inverted signal of a column address strobe signal (/CAS) received from the outside. The input signal WE is the inverted signal of a write enable signal (/WE) received from the outside. The input signal B RC  is enabled when a burst read is completed. The input signal B WC  is enabled when a burst write is completed. 
     Here, the write command means that the signal /RAS is received in a logic “high” state, that the signal /CAS is received in a logic “low” state, and that the signal /WE is received in a logic “high” state. Also, the read command means that the signal /RAS is received in the logic “high” state, that the signal /CAS is received in the logic “low” state, and that the signal /WE is received in the logic “low” state. 
     The data FIFO buffer  23  which is a data storage means, sequentially stores the write data received through a data input and output pin DQ in response to the control signals RC, F FIFO , WC 1 , and C 1  to C 3 , the internal clock ICLK, and the address hit data signals AH 1  to AH 3  generated by the address FIFO buffer  25 . The data FIFO buffer  23  sequentially outputs the stored write data to the memory cell array  21  in order to continue a write operation after a read operation is completed, when the read command is input to the control signal generator  27  after the write command is input to the same. 
     The selector  29  which is an output multiplexer selects the data stored in the data FIFO buffer  23  and outputs the selected data through the data input and output pin DQ, in response to the address hit signal AH generated by the address FIFO buffer  25 , when the addresses during the read operation coincide with the addresses stored in the address FIFO buffer  25 . 
     Though not shown here, in the write data path from the data input and output pin DQ to the memory cell array  21 , an input buffer, an input multiplexer, and a data input and output line driver are interposed between the data input and output pin DQ and the data FIFO buffer  23 . An input and output line driver is interposed between the data FIFO buffer  23  and the memory cell array  21 . Also, in the read data path from the memory cell array  21  to the data input and output pin DQ, an input and output line multiplexer and an input and output line sense amplifier are interposed between the memory cell array  21  and the selector  29 . An output buffer is interposed between the selector  29  and the data input and output pin DQ. 
     FIG. 3 is a detailed circuit diagram of the control signal generator  27  shown in FIG.  2 . 
     Referring to FIG. 3, the control signal generator includes a read command signal generator  31 , a write command signal generator  33 , a FIFO flag signal generator  35 , an internal write signal generator  37 , and a FIFO counter  39 . 
     The read command signal generator  31  generates a read command signal RC which is enabled when the read command is received. In other words, the read command signal RC is enabled when the input signal RAS becomes logic “low,” the input signal CAS becomes logic “high,” and the input signal WE becomes logic “low.” The read command signal is disabled when the burst read is completed, i.e., when the input signal B RC  is enabled. The read command signal generator  31  includes first through third inverters  31   a ,  31   b , and  31   d , a NAND gate  31   c , and a controller  31   e . The read command signal generator  31  can include other logic gates, if necessary. 
     The write command signal generator  33  generates a first write command signal WC 1  which is enabled when the write command is received. In other words, the first write command signal WC 1  is enabled when the input signal RAS becomes logic “low,” the input signal CAS becomes logic “high,” and the signal WE becomes logic “high.” The first write command signal WC 1  is disabled after the lapse of delay time corresponding to the CAS latency, from the point of time where the burst write is completed, i.e., from the point of time where the signal B WC  is enabled. The write command signal generator  33  generates a second write command signal WC 2  whose enable point of time, i.e., the time at which it goes high, is delayed with respect to the enable point of time of the first write command signal WC 1  by the CAS latency, and whose disable point of time, i.e., the time at which it goes low, is the same as the disable point of time of the first write command signal WC 1 . The write command signal generator  33  includes first and second inverters  33   a  and  33   c , a NAND gate  33   b , a first controller  33   d , a delayer  33   e , and a second controller  33   f . The write command signal generator  33  can include other logic gates, if necessary. 
     The FIFO flag signal generator  35  generates a FIFO flag signal F FIFO  that indicates whether there is data in the data FIFO buffer  23  shown in FIG.  2 . The FIFO flag signal F FIFO  is enabled when the read command is received while the second write command signal WC 2  is enabled to logic “high,” i.e., when the read command signal RC is enabled to logic “high.” The FIFO flag signal F FIFO  is disabled when there is no data in the data FIFO buffer  23 , i.e., when the count signals C 1 , C 2 , and C 3  are all logic “low.” The FIFO flag signal generator  35  includes a NAND gate  35   a , an inverter  35   b , a NOR gate  35   c , and a controller  35   d . The FIFO flag signal generator  35  can include other logic gates, if necessary. 
     The internal write signal generator  37  generates an internal second write command signal WC 2 , which indicates that the internal write can be performed. The internal second write command signal WC 2  is enabled when there is data in the data FIFO buffer  23  (the signal F FIFO  is logic “high”), the read operation is completed (the signal RC is logic “low”), and all write data items are input to the data FIFO buffer  23  (the first write command signal WC 1  is logic “low”). The internal second write command signal WC 2  is disabled when there is no data in the data FIFO buffer  23  (the FIFO flag signal F FIFO  is logic “low”), the read operation is not completed (the read control signal RC is logic “high”), and not all the write data items are input to the data FIFO buffer  23  (the first write command signal WC 1  is logic “high”). The internal write signal generator  37  includes first through third inverters  37   a ,  37   b , and  37   d , and a NAND gate  37   c . The internal write signal generator  37  can include other logic gates, if necessary. 
     The FIFO counter  39  generates the count signals C 1 , C 2 , and C 3  and is controlled by the second write command signal WC 2  to count the number of write data items to be stored in the data FIFO buffer  23 . When the number of write data items to be stored in the data FIFO buffer  23  is 1, C 1 , C 2 , and C 3  are respectively 1, 0, and 0. When the number of write data items to be stored in the data FIFO buffer  23  is 2, C 1 , C 2 , and C 3  are respectively 1, 1, and 0. When the number of write data items to be stored in the data FIFO buffer  23  is 3, C 1 , C 2 , and C 3  are respectively 1, 1, and 1. The count signals C 1 , C 2 , and C 3  increase in response to the internal clock signal ICLK when the second write command signal WC 2  is logic “high” and the FIFO flag signal F FIFO  is logic “high,” and decrease in response to the internal clock signal ICLK when the internal write signal IW is logic “high.” The FIFO counter  39  includes a NAND gate  39   a , an inverter  39   b , and a counter  39   c . The FIFO counter can include other logic gates as necessary. 
     FIG. 4 is a detailed circuit diagram of the address FIFO buffer  25 . The FIFO buffer  25  includes a first address counter  41 , a multiplexer  43 , a second address counter  45 , an address FIFO circuit  47 , and a comparing unit  49 . 
     Referring to FIG. 4, the address FIFO circuit  47  includes a plurality of D flip-flops  47   a ,  47   c , and  47   e  and a plurality of multiplexers  47   b  and  47   d . The D flip-flops  47   a ,  47   c , and  47   e  operate in response to the internal clock signal ICLK. The number of addresses stored in the address FIFO circuit  47 , i.e., the number of stages of the address FIFO circuit  47  varies according to the CAS latency. Since the CAS latency is usually up to 3, FIG. 4 shows the case where the depth of the address FIFO circuit  47  is 3. The depth of the address FIFO circuit  47  can be extended, if necessary, however, through the addition of more D flip-flops and multiplexers. 
     During the read operation (when the read command signal RC is logic “high”) the first address counter  41  receives the address AD input through the address pin ADDR shown in FIG.  2  and generates an internal address. The internal address is output through the multiplexer  43  as an address ADI. The address ADI is then transmitted to the address decoder (not shown) of the memory cell array shown in FIG.  2 . 
     The address FIFO circuit  47  operates during a normal write operation (when the first write control signal WC 1  is logic “high” and the signal F FIFO  is logic “low”) or an internal write operation (when the internal write signal IW is logic “high”). In other words, when the CAS latency is  3  (control signals CL 1  and CL 2  both become logic “0”), during the normal write operation, the internal address generated by the second address counter  45  is output to an output stage FO, after sequentially passing through the three stages of the address FIFO circuit  47 , i.e., after sequentially passing through the flip-flop  47   a , the multiplexer  47   b , the flip-flop  47   c , the multiplexer  47   d , and the flip-flop  47   e . When the CAS latency is  2  (the control signals CL 1  and CL 2  become logic “0” and logic “1,” respectively), the internal address generated by the second address counter  45  is output to the output stage FO, after sequentially passing through two stages of the address FIFO circuit  47 , i.e., after sequentially passing through the multiplexer  47   b , the flip-flop  47   c , the multiplexer  47   d , and the flip-flop  47   e . When the CAS latency is 1 (the control signals CL 1  and CL 2  become logic “1” and logic “0,” respectively), the internal address generated by the second address counter  45  is output to the output stage FO, after passing through one stage of the address FIFO circuit  47 , i.e., after sequentially passing through the multiplexer  47   d  and the flip-flop  47   e . The internal address output to the output stage FO is output as the address ADI through the multiplexer  43 . The address ADI is transmitted to the address decoder of the memory cell array shown in FIG.  2 . 
     When the read command is received during a write operation, the F FIFO  becomes logic “high.” Accordingly, the operation of the address FIFO circuit  47  stops and the internal address input to the address FIFO circuit  47  is stored. After the read operation is completed, during the internal write operation, the internal write signal IW becomes logic “high.” Accordingly, the operation of the address FIFO circuit  47  resumes and the addresses stored in the address FIFO circuit  47  are sequentially output to the output stage FO. The address output to the output stage FO is output as the address ADI through the multiplexer  43 . The address ADI is then transmitted to the address decoder of the memory cell array shown in FIG.  2 . 
     When the read command is received (the signal RC is logic “high”) and when the FIFO flag signal F FIFO  is logic “high” (there is data in the data FIFO buffer  23  shown in FIG.  2 ), the comparing unit  49  compares the address during the read operation, i.e., the output of the first address counter  41 , with the corresponding address in the address FIFO circuit  47  and generates signals AHD 1  to AHD 3 . 
     More specifically, a first comparator  49   a  compares the output of the first address counter  41  with an address stored in the third stage of the address FIFO circuit  47 , i.e., the flip-flop  47   a , in response to the third count signal C 3 , and enables the signal AHD 3  to logic “high” when the output coincides with the address. A second comparator  49   b  compares the output of the first address counter  41  with an address stored in the second stage of the address FIFO circuit  47 , i.e., the flip-flop  47   c , in response to the second count signal C 2 , and enables the signal AHD 2  to logic “high” when the output coincides with the address. A third comparator  49   c  compares the output of the first address counter  41  with an address stored in the first stage of the address FIFO circuit  47 , i.e., the flip-flop  47   e , in response to the first count signal C 1 , and enables the signal AHD 1  to logic “high” when the output coincides with the address. When one of the signals AHD 1  to AHD 3  is enabled to logic “high,” the address hit signal AH is enabled to logic “high” by a NOR gate  49   g  and an inverter  49   h.    
     FIG. 5 is a detailed circuit diagram of the data FIFO buffer  23  shown in FIG.  2 . 
     Referring to FIG. 5, the data FIFO buffer  23  includes first through fourth data multiplexers  52 ,  54 ,  56 , and  57  and first through third data D flip-flops  51 ,  53 , and  55  which operate in response to the internal clock ICLK. FIG. 5 shows a case where the depth of the data FIFO buffer  23  is 3 stages. The depth of the data FIFO buffer  23  can be extended, however, if necessary, with additional multiplexers and D flip flops. Also, the number of data FIFO circuits  23  is determined according to the unit of the prefetch. Since the prefetch of the DDR SDRAM is 2, two data FIFO circuits  23  are necessary. 
     During a normal write operation, since the signal WC 1  becomes logic “high” and the signal F FIFO  becomes logic “low,” the write data DATA input through the input and output pin DQ is output as data DATA 2  through the multiplexer  56 . The data DATA 2  is then transmitted to the memory cell array shown in FIG.  2 . 
     When the read command is received during the write operation, the signal F FIFO  becomes logic “high,” thus operating the FIFO counter  39  shown in FIG.  3 . At this time, when the number of write data items to be stored in the data FIFO is 1, the outputs C 1 , C 2 , and C 3  of the FIFO counter  39  are 1, 0, and 0, respectively. Accordingly, the one item of write data DATA received through the input and output pin DQ is stored in the flip-flop  55  through the multiplexer  54 . When the number of write data items to be stored in the data FIFO is 2, the outputs C 1 , C 2 , and C 3  of the FIFO counter  39  are 1, 1, and 0, respectively. Accordingly, the first write data item of the two write data items DATA received through the input and output pin DQ is stored in the third flip-flop  55  through the second multiplexer  54 . The second write data item is stored in the second flip-flop  53  through the first multiplexer  52 . When the number of write data items to be stored in the data FIFO is 3, the outputs C 1 , C 2 , and C 3  of the FIFO counter  39  are 1, 1, and 1, respectively. Accordingly, the first write data item among the three write data items DATA received through the input and output pin DQ is stored in the third flip-flop  55  through the second multiplexer  54 ; the second write data item is stored in the second flip-flop  53  through the first multiplexer  52 ; and the third write data item is directly stored in the first flip-flop  51 . The number of write data items to be stored in the data FIFO varies according to the CAS latency. 
     When the address hit is generated during the read operation at a time when there is write data in the data FIFO buffer  23 , one among the data items stored in the flip-flops  51 ,  53 , and  55  is selected in response to the signals AHD 1  to AHD 3  and is output as data DATA 1  through the multiplexer  57 . To be more specific, when the signal AHD 1  becomes logic “high,” the data item stored in the third flip-flop  55  is output as the data DATA 1  through the multiplexer  57 ; when the signal AHD 2  becomes logic “high,” the data item stored in the second flip-flop  53  is output as the data DATA 1  through the multiplexer  57 ; and when the signal AHD 3  becomes logic “high,” the data item stored in the first flip-flop  51  is output as the data DATA 1  through the multiplexer  57 . At this time, since the address hit signal AH is enabled to logic “high,” the data DATA 1  is output to the input and output pin DQ through the selector  29  shown in FIG.  2 . 
     FIGS. 6A through 6D are timing diagrams of the operation of the DDR SDRAM according to a preferred embodiment of the present invention. The operation of the DDR SDRAM according to the preferred embodiment of the present invention will be described in more detail with reference to FIGS. 6A through 6D. 
     FIGS. 6A and 6B are timing diagrams of the operation of the DDR SDRAM when the CAS latency is 2.5 and the burst length is 4. The signal ECLK represents the external clock signal. 
     Referring to FIG. 6A, a first read command RD 1  is received when write data D 0  is received after the lapse of the CAS latency, which occurs 2.5 clock cycles after the rising edge of the external clock signal ECLK with which the write command WT coincides, i.e., after the falling edge of the third clock cycle of the external clock ECLK. A second read command RD 2  is received 1.5 clock cycles after the rising edge of the external clock signal ECLK with which the first read command RD 1  coincides, i.e. after the falling edge of the fifth clock cycle of the external clock ECLK. 
     In this case, two pairs of write data items D 0 /D 1  and D 2 /D 3  are stored in the two data FIFO circuits  23 . Two pairs of output data items Q 10 /Q 11  and Q 12 /Q 13  are output from the memory cell array  21  after the lapse of 2.5 clock cycles after the first read command RD 1  is received. In continuation, two pairs of output data items Q 20 /Q 21  and Q 22 /Q 23  are output from the memory cell array  21  after the lapse of 2.5 clock cycles after the second read command RD 2  is received. 
     After the read operation is completed, the two pairs of write data items D 0/D   1  and D 2 /D 3  stored in the two data FIFO circuits  23  are written to the memory cell array  21  by the internal write operation. The above operation order is shown in a column selection signal CS. R refers to the read operation. IW refers to the internal write operation. Since the column selection signal CS is widely known to anyone skilled in the art, a detailed description thereof will be omitted. 
     Referring to FIG. 6B, the first read command RD 1  is received when the write data D 0  is received after the lapse of the CAS latency, which is 2.5 clock cycles after the rising edge of the external clock signal with which WT coincides, i.e., after the falling edge of the third clock cycle of the external clock ECLK. The second read command RD 2  is received 2.5 clock cycles after the rising edge of the external clock signal with which the first read command RD 1  coincides, i.e., after the falling edge of the sixth clock cycle of the external clock ECLK. 
     In this case, since there is a temporal gap of one clock cycle between the two read commands RD 1  and RD 2 , i.e., a gap of two read operations, the internal write operation is performed between the two read operations. 
     FIG. 6C is a timing diagram of the operation of the DDR SDRAM when the CAS latency is 2.5 and the burst length is 8. 
     Referring to FIG. 6C, write data D 0  through D 3  are received after the lapse of the CAS latency, i.e., 2.5 clock cycles after the write command WT is received. The read command RD is received when write data D 4  is received. In this case, the write data D 0  through D 3  are directly written to the memory cell array  21 . The two pairs of write data items D 4 /D 5  and D 6 /D 7  received after the write data D 0  through D 3 , are stored in the two data FIFO circuits  23 . Four pairs, i.e., eight output data items Q 0  through Q 7 , are output from the memory cell array  21  after the lapse of 2.5 clock cycles after the read command RD is received. 
     After the read operation is completed, the two pairs of write data D 4 /D 5  and D 6 /D 7  stored in the data FIFO circuits  23  are written to the memory cell array  21  by the internal write operation. The above operation order is shown in the column selection signal CS. R refers to the read operation. DW refers to a direct write operation. IW refers to the internal write operation. 
     FIG. 6D is a timing diagram of the operation of the DDR SDRAM when the CAS latency is 2.5, the burst length is 8, and the address hit is generated. 
     Referring to FIG. 6D, write data D 0  through D 3  are received after the lapse of the CAS latency, that is, 2.5 clock cycles after the write command WT is received. In this case, the write data items D 0  through D 3  are directly written to the memory cell array  21 . The two pairs of write data items D 4 /D 5  and D 6 /D 7  received after the write data items D 0  through D 3  are stored in the two data FIFO circuits  23 . Four pairs, i.e., eight output data items Q 0  through Q 7 , are output from the memory cell array  21  after the lapse of 2.5 clock cycles after the read command RD is received. 
     However, when the address hit is generated during the read operation, for example, when the address stored in the first stage of the address FIFO circuit  47  is address hit, data is not output from the memory cell array  21  and the write data items D 4 /D 5  stored in the first stage of the two data FIFO circuits  23  are output as the output data items Q 0 /Q 1 . When the address stored in the second stage of the address FIFO circuit  47  is address hit, the write data items D 6 /D 7  stored in the second stage of the two data FIFO circuits  23  are output as the output data items Q 2 /Q 3 . The remaining output data items Q 4  through Q 7  are output from the memory cell array  21 . After the read operation is completed, the two pairs of write data items D 4 /D 5  and D 6 /D 7  stored in the data FIFO are written to the memory cell array  21  by the internal write operation. 
     Since the DDR SDRAM according to the present invention includes the data FIFO buffer  23  and the address FIFO buffer  25  and has the same CAS latency (or CAS latency-1) in the write command and the read command, the read command can be received during the write operation. Accordingly, it is possible to improve the data processing speed and to improve the efficiency of the input and output pin DQ. 
     Although, the invention has been described with reference to a particular embodiment, it will be apparent to one of ordinary skill in the art that modifications of the described embodiment may be made without departing from the spirit and scope of the invention.