Abstract:
A decision-feedback equalizer for use in a receiving unit for receiving an incoming data stream and for providing a stream of bit data outputs, including at least one decision-feedback equalizer block comprising a plurality of speculation units. Each speculation unit includes a dynamic preamplifier for asynchronously amplifying a voltage difference depending on an input voltage of the incoming data stream and a given threshold voltage; and an arrangement for selectively generating a transconductor current which depends on the amplified voltage difference. Also included is one dynamic regenerator for associating an output data bit to the selectively generated transconductor current.

Description:
BACKGROUND 
       [0001]    The present invention relates to a decision-feedback equalizer for use in an input buffer. In particular, the present invention relates to implementations of decision-feedback equalizers with improved power efficiency, increased bandwidth and reduced circuit area. 
         [0002]    Today&#39;s data networks require high-speed data communication with serial link data rates of more than 10 Gbit/s. In this bandwidth range, a further increase of serial link data rates is challenging due to the limited general bandwidth. The general bandwidth is usually determined by dielectric losses and reflections on the transmission channel which result in a widening of the transmitted signal pulses over more than one unit interval, so that the received signal is distorted by intersymbol interference. 
         [0003]    These signal distortions are usually compensated for by means of equalizing functions in the receiving circuitry, such as feed-forward equalizing and decision-feedback equalizing. A decision-feedback equalizer (DFE) is capable of reducing signal distortions while leaving noise or cross-talk unaffected. 
         [0004]    In general, a decision-feedback equalizer is included in the digitalized data path at an output side of an analog-digital converter and is substantially configured to compensate for the effects of one transmitted pulse onto one or more succeeding pulses of the incoming stream of digitalized data samples. The general concept of a decision-feedback equalizer implementation is to provide at least one comparator used to translate the single pulses of the stream of digitalized data samples into a bit stream. In the comparator, the digitalized data samples are each compared with a respective variable threshold value, which may be generated depending on the history of (preceding) data samples tapped from the output of the decision-feedback equalizer. The variable threshold value is obtained by delaying the bit outputs of the decision-feedback equalizer for one or more clock cycles in a number of delay stages by weighting each of the delayed bit outputs of the decision-feedback equalizer after each stage by a predetermined (preset) coefficient and by then adding the results. The coefficients are preset with respect to a standard pulse response of the specific transmission channel. In particular, the adding-up of the weighted delayed DFE outputs requires adding circuits which usually have a relatively high power and area consumption in an integrated circuit implementation. 
         [0005]    An additional approach, known as speculation or loop-unrolling, is to precompute the variable threshold values for each pattern of delayed DFE bit outputs. Speculation or loop-unrolling for DFE is a technique that implements all possible rated summations at the output of a finite impulse response (FIR) filter in the DFE feedback path in order to reduce the critical path time of the DFE coefficients&#39; summation time. All possible combinations of N post-cursors (N taps) intersymbol interference terms are accordingly generated in a speculative decision-feedback equalizer of the order N, so that a total of 2 N  combinations or speculations are generated. The correct decision is selected among the 2 N  speculations on the basis of the last N decisions. This approach should help to save area and power impact of the line of adding circuits. However, hardware complexity grows exponentially with the number N of taps, i.e. the number of considered historical data samples. As for each of the threshold values a separate comparator latch is needed, the output of which are to be selected by a multiplexer, the overall circuitry has the disadvantage of requiring a large circuit area and having a high power consumption. 
         [0006]    Document U.S. Pat. No. 7,792,187 B2 discloses a decision-feedback equalizer comprising summer circuits configured to add a dynamic feedback signal representing a dynamic feedback tap to a received input and to speculate on a speculative tap; data slicers configured to receive outputs of the summer circuits and sample the outputs of the summer circuits in accordance with a clock signal; first multiplexers, each configured to receive a first input from a corresponding data slicer; and second multiplexers, each configured to receive an output of a plurality of first multiplexers, the second multiplexers having an output fed back to a second input of the first multiplexers and the second multiplexer output being employed to provide a select signal for a second multiplexer on a different section of the DFE and to drive the dynamic feedback signal to a summer circuit on a same section of the DFE. This approach provides that a slave latch of a conventional master-slave flip-flop is replaced by a multiplexer driven by a half-rate clock. 
         [0007]    Document US 2013/0322512 A1 discloses a decision-feedback equalizer (DFE) slicer for a receiver, comprising a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages. Each of the first and second multiplexer stages comprises 4 comparator latches, each of which has a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions d n-2  and d n-3 , wherein the previous symbol decisions d n-2  and d n-3  are received from two other respective DFE slices in the receiver. The 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision d n-1  received from a third respective DFE slice in the receiver to output a slice output signal d n . 
         [0008]    Document Payandehnia, P. et al “A 4MW 3-TAP 10 GB/S DECISION-FEEDBACK EQUALIZER”, IEEE Date: 7-10 Aug. 2011 relates to a half-rate low-power 3-tap decision-feedback equalizer with an improved switched-capacitor-based summer architecture for speculating the first feedback tap. The other two taps are cancelled using a current summation technique. Further power consumption reduction is achieved by using a sense-amplifier-based slicer and a pass-gate multiplexer. 
       SUMMARY 
       [0009]    According to a first aspect, a decision-feedback equalizer for use in a receiving unit for receiving an incoming data stream and for providing a stream of bit data outputs is provided, including at least one decision-feedback equalizer block comprising:
       a plurality of speculation units, each comprising:
           a dynamic preamplifier for asynchronously amplifying a voltage difference depending on an input voltage of the incoming data stream and a given threshold voltage;   a means for selectively generating a transconductor current based on the amplified voltage difference;   
           one dynamic regenerator for associating an output data bit to the selectively generated transconductor current.       
 
         [0014]    According to a further aspect, a decision-feedback equalizer for use in a receiving unit for receiving an incoming data stream and for providing a stream of bit data outputs, including at least one decision-feedback equalizer block is provided, comprising:
       a plurality of speculation units, each comprising:
           a dynamic preamplifier for asynchronously amplifying a voltage difference depending on an input voltage of the incoming data stream and a provided threshold voltage;   a selectable voltage to current converter for selectively generating a transconductor current so that it depends on the amplified voltage difference;   
           one dynamic regenerator for associating an output data bit to the selectively generated transconductor current.       
 
         [0019]    It may be provided that the threshold voltage is respectively associated to the speculation unit. Particularly, to each of the speculation units a unique threshold voltage may be associated. 
         [0020]    According to an embodiment, a speculation logic may be provided which is configured to select exactly one of the speculation units depending on at least one previous bit data output, so that the exactly one of the speculation units provides the respective transconductor current while the other speculation units provide no transconductor current. 
         [0021]    Furthermore, the speculation units may be interconnected with their outputs to form a current summing node, wherein the input of the one dynamic regenerator is coupled to the summing node. 
         [0022]    It may be additionally or alternatively provided that the dynamic preamplifier of each speculation unit includes a differential amplifier. 
         [0023]    In particular, the differential amplifier may include a cross-coupled cascade. 
         [0024]    Furthermore, the differential amplifier may be connected as a common-gate transconductor to directly provide the transconductor current, wherein a selection transistor is provided to select the transconductor current to be supplied to the dynamic regenerator. 
         [0025]    Moreover, the means for selectively generating a transconductor current may include a transconductor to convert an output voltage of the differential amplifier to the transconductor current. 
         [0026]    Alternatively or additionally, the dynamic regenerator may include a pair of cross-coupled inverters receiving the selected transconductor current to provide an output voltage corresponding to an output data bit depending on the sign of the transconductor current. 
         [0027]    The output of the dynamic regenerator may be coupled with a domino latch to hold the spread output voltage as the output data bit which is the binary decision result of the dynamic regenerator. 
         [0028]    It may be provided that two decision-feedback equalizer blocks are configured to be operated in an interleaving manner. 
         [0029]    According to a further aspect, a receiving unit is provided comprising the above decision-feedback equalizer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]    Embodiments are described in more detail in conjunction with the accompanying drawings, in which: 
           [0031]      FIG. 1  schematically shows a receiving unit for receiving a high-speed data stream using a decision-feedback equalizer; 
           [0032]      FIG. 2  shows a diagram for illustrating an impulse response before and after a decision-feedback equalization; 
           [0033]      FIG. 3  schematically shows a full-rate decision-feedback equalizer; 
           [0034]      FIG. 4  schematically shows a half-rate decision-feedback equalizer; 
           [0035]      FIG. 5  shows an implementation of a 2-tap full-rate decision-feedback equalizer including a dynamic regenerator and the latch circuit; and 
           [0036]      FIGS. 6 a  to 6 c    show circuit diagrams of the dynamic preamplifier and a selectable transconductor in different variants with and without cascaded MOS as selector and/or with and without a cross-coupled cascade in the dynamic preamplifier. 
       
    
    
     DETAILED DESCRIPTION 
       [0037]    In the following, a decision-feedback equalizer to be implemented as an integrated circuit is disclosed. The decision-feedback equalization substantially compensates and mitigates intersymbol interferences and/or DC creep in a data stream received across a communication channel which are to be digitized to provide data samples for further evaluation. 
         [0038]    In detail,  FIG. 1  illustrates a transmission system  1  having a transmission unit  2  which is configured to transmit a serial data stream over a transmission channel  3  to be received by a receiving unit  4 . The data stream is received by way of an optional analog equalizer  5 , such as a continuous time linear equalizer, which is generally known in the art and thus not further referred to herein. 
         [0039]    In general, the bandwidth of the transmission channel  3  may be reduced by dielectric losses and reflections due to impedance discontinuities. In the time domain, the limited channel bandwidth results in a broadening of the transmitted signal pulses over more than one unit interval, so that the signal received at the receiving unit  4  is distorted by intersymbol interferences. 
         [0040]    The common method of compensating for signal distortions caused by the limited channel bandwidth is the application of equalization functions which may be implemented in a feed-forward equalizer  6  and a decision-feedback equalizer  7 . Decision-feedback equalizers  7  are usually well suited for flattening the general response, thereby reducing signal distortions. 
         [0041]      FIG. 2  shows an exemplary portion of a received data stream with one signal impulse on an input side of the receiving unit  4  and characteristics resulting after the compensation by means of decision-feedback equalization. It can be seen that for an exemplary data pulse, as shown in the waveform Si of a rectangular data pulse provided on the transmitting side, the signal response after transmission through the transmission channel  3  is shown as the waveform S 2  of the received analog signal. It can further be seen that, compared to the original data pulse, the received signal is broadened due to dielectric losses and results in signal variations following the broadened impulse caused by reflections due to impedance discontinuities. Sampling may occur at sampling times determined by the provided clock signal CLK. 
         [0042]    The values of the sampled data are indicated relative to the cursor indicating the sampling value h 0  of a main pulse portion of the transmitted signal, followed by more sampling values h 1  to h n  (first to n th  post-cursor) which are related to the respective transmitted data pulse and are caused by the signal distortion on the transmission channel  3  due to the respective transmitted data pulse. Due to the broadening of the impulse response of the transmission channel  3 , a signal distortion caused by the respective transmitted data pulse can also be observed one clock cycle before the actual sampling of the main pulse portion (main cursor h 0 ). The sampling value thereof is designated as precursor h −1 . The purpose of decision-feedback equalization is to reduce the post-cursor intersymbol interferences at their respective sampling times as much as possible. The result of such decision-feedback equalization is indicated by the equalized signal characteristics S 3 . 
         [0043]      FIG. 3  shows a full-rate decision-feedback equalizer  10  with two taps which can be applied as the decision-feedback equalizer  7  in the transmission system  1  of  FIG. 1 . 
         [0044]    The full-rate decision-feedback equalizer  10  of  FIG. 1  has an unrolled loop architecture, so that four differential threshold levels h 1 +h 2 , h 1 −h 2 , −h 1 +h 2 , −h 1 −h 2  for a comparison with a received input signal S in  are provided. A threshold level may be variably preset by a calibration unit  100  and may be particularly formed by a sum of a first post-cursor value h 1  and a second post-cursor value h 2 , which are respectively combined with different signs to provide four different threshold levels. In case of N taps, i.e. N successively delayed outputs of the DFE 2 N  threshold levels need to be provided. The first and second post-cursor values h 1 , h 2  might be variably set as digital values which are then digital-analog converted in respective digital-analog converters  11  to provide respective different analog post-cursor voltages V c1 , V c2 , V c3 , V c4 . The number of digital-analog converters  11  corresponds to the number 2 N  of threshold levels applied. 
         [0045]    The analog post-cursor voltages V c1 , V c2 , V c3 , V c4  are each applied to a separate speculation unit  12 . Each of the speculation units  12  has a dynamic preamplifier  13  in which a voltage difference V diff1 , V diff2 , V diff3 , V diff4  between the respectively applied post-cursor voltage V c1 , V c2 , V c3 , V c4  and the received input voltage V in  of an input signal S in  is amplified, so that the respective voltage difference V diff1 , V diff2 , V diff3 , V diff4  is amplified. 
         [0046]    The dynamic preamplifier  13  operates asynchronously. A sample and hold circuit to provide Vin for the input signal may be provided but is not necessary. Thereby, the sign of the voltage difference V diff1 , V diff2 , V diff3 , V diff4  which carries the information sampled from the input signal S in  is maintained. 
         [0047]    The outputs of the dynamic preamplifiers  13  are supplied to a selectable transconductor  14 , respectively. As commonly known, a transconductor  14  converts a voltage to a corresponding current. As the transconductor  14  can be enabled and disabled it can produce the corresponding current at its output or can produce a current of 0 at its output. Each of the four (2 N  for a number of N-taps) selectable transconductors  14  can be enabled by selection of a respective (individual) selection signal SEL [ 1 .. 4 ] and generates a transconductor current I diff1 , I diff2 , I diff3 , I diff4  which depends on the voltage difference V diff1 , V diff2 , V diff3 , V diff4  supplied by the respective dynamic preamplifier  13 , if enabled, or is 0, if disabled. The outputs of the transconductors  14  supplying the transconductor currents I diff1 , I diff2 , I diff3 , I diff4  are interconnected at a summing node S and commonly applied to a dynamic regenerator  15 . Preferably, the selection signals SEL[ 1 .. 4 ] are controlled such that only one of the transconductors  14  may be activated at a time. Accordingly, at the input of the dynamic regenerator  15  only the transconductor current I diff1 , I diff2 , I diff3 , I diff4  of the one activated (selected) transconductor  14  is applied. 
         [0048]    Typically, a DFE comparator comprises a dynamic preamplifier (e.g. differential pair) combined with a latch (e.g. two cross-coupled inverters plus reset switches). In the herein described embodiments multiple dynamic preamplifiers without latches or other means for holding digital states, are directly connected via a selectable transconductors to a single latch. So instead of providing a latch for each of the comparators only one latch is needed. 
         [0049]    The dynamic regenerator  15  receives the transconductor current I diff1 , I diff2 , I diff3 , I diff4  of the selected transconductor  14  and transforms the applied transconductor current I diff1 , I diff2 , I diff3 , I diff4  into a digitalized output D 0 . The digitalized output D 0  is delayed by two (or N for N taps) subsequent delay elements  16 ,  17  to obtain history data outputs D 1 , D 2 . The delay elements  16 ,  17  are configured to delay the digitalized output D 0  by one clock cycle. 
         [0050]    The history data outputs D 1 , D 2  are supplied to a speculation logic  18  which is configured to generate the selection signals SEL[ 1 ... 4 ] (SEL[ 1 .. 2   N ] for N taps) to select one of the selectable transconductors  14  to be active such that the thus selected transconductor  14  applies a transconductor current L diff1 , I diff2 , I diff3 , I diff4  depending on the voltage difference V diff1 , V diff2 , V diff3 , V diff4  provided by the preamplifier  13  while the other transconductors  14  are deactivated so as to apply a current of 0. 
         [0051]    The digital analog converter  11 , the speculation units  12  and the dynamic regenerator  15  form a decision-feedback equalizer block (DFE) block  19 . 
         [0052]      FIG. 4  schematically shows a 2-tap half-rate decision-feedback equalizer  20 . Substantially, the half-rate decision-feedback equalizer  20  of  FIG. 4  mirrors the DFE block  19  of the full-rate decision-feedback equalizer  10  of  FIG. 3 , wherein both DFE blocks  19  each are operated in an interleaved manner in each half clock cycle (as unit interval) and process data in even and odd clock cycles CLK even , CLK odd . The outputs of the DFE blocks  19  correspond to subsequent data outputs D 0 , D 1  and are coupled with delay elements  23  with a delay of a full clock cycle each, to provide a second and third order history data output corresponding to the history data output D 2  and D 3  while the history data output corresponding to D 1  is provided as the output of the respective other DFE block  19 . Furthermore, input signals V in   _   even  and V in   _   odd  are applied to the DFE blocks  19 , each sampled in an interleaved manner in each half clock rate. A speculation logic  22 , however, processes the delayed digitalized outputs D 1 , D 2  or D 2 , D 3  (depending on and even or odd clock cycle) of the circuit parts and determines a respective selection signal SEL even [ 1 .. 4 ], SEL odd  [ 1 .. 4 ] to select the respective transconductor current L diff1 , I diff2 , I diff3 , I diff4  in each of the DFE blocks  19 . 
         [0053]    The decision-feedback equalizers  10 ,  20  of the DFE in  FIGS. 3 and 4  are preferably implemented in a differential form. 
         [0054]    In  FIG. 5 , a more detailed schematic of the dynamic preamplifier  13 , the selectable transconductor  14 , and the dynamic regenerator  15  of the DFE block  19  is shown on a transistor level. 
         [0055]    The dynamic preamplifier  13  is generally formed by a differential amplifier having a first branch  31   a  and a second branch  31   b  (a, b indicating the corresponding first and second branches for all following reference signs) in each of which a first and second enable transistor  32   a,    33   a;    32   b,    33   b  are serially connected. 
         [0056]    For each branch  31   a,    31   b  the first enable transistor  32   a,    32   b  may be formed as a MOS transistor of a first conductivity type, such as an NMOS transistor, and is connected with a first terminal to a first supply potential, such as the ground potential GND, while the second terminal is connected to a first terminal of an input transistor  34   a,    34   b.  The input transistors  34   a,    34   b  can be formed as MOS transistors of a first or second conductivity type, such as NMOS or PMOS transistors, respectively. The second terminals of the input transistors  34   a,    34   b  are respectively connected to first terminals of the second enable transistors  33   a,    33   b.  The second enable transistors  33   a,    33   b  may be MOS transistors of a second conductivity type, such as PMOS transistors. The second terminals of the second enable transistors  33   a,    33   b  are coupled with a second supply potential, such as a high supply potential VDD for the given examples of conductivity types. 
         [0057]    The gate terminals of the first and second enable transistors  32   a,    33   a,    32   b,    33   b  of the first and second branches  31   a,    31   b  are connected to a clock signal CLK. The gate terminals of the first input transistors  34   a,    34   b  of the first and second branches  31   a,    31   b  are coupled with both input signal potentials V inp , V inn  of the differential input signal S in , respectively. A respective output node DAOa, DOAb of the differential amplifier, at which preamplifier output potentials can be tapped, is formed at the interconnection of the second terminals of the input transistor  34   a,    34   b  and the first terminals of the second enabling transistors  33   a,    33   b,  respectively. 
         [0058]    A threshold transistor  35   a  is provided connecting the second terminal of the first enabling transistors  32   a  of the first branch  31   a  to a second terminal of the input transistor  34   b  of the second branch  31   b.  Another threshold transistor  35   b  is provided connecting the second terminal of the first enabling transistor  32   b  of the second branch  31   b  to a second terminal of the input transistor  34   a  of the first branch  31   a.  At the gate terminals of the threshold transistors  35   a,    35   b  a threshold voltage corresponding to the respective differential threshold level h 1 +h 2 , h 1 −h 2 , −h 1 +h 2 , −h 1 −h 2  is applied. 
         [0059]    Thereby, a cross-coupling can be achieved, which sets the determination threshold of the preamplifier  13  to the voltage level applied to the gate terminals of the threshold transistors  35   a,    35   b.    
         [0060]    The preamplifier output nodes DAOa, DOAb of the first and second branch  31   a,    31   b  of the preamplifier  13  are connected to the selectable transconductor  14  which transforms the preamplifier output potentials into respective currents. The transconductor  14  has first and second branches  41   a,    41   b  associated to the first and second branches  31   a,    31   b  of the preamplifier  13 , each of which has a transconductor transistor  42   a,    42   b  which may be formed as a MOS transistor of the first conductivity type, such as an NMOS transistor, a first terminal of which is connected to the first supply potential, such as ground potential GND, and the gate terminal thereof is connected to the respective preamplifier output node DAOa, DAOb. 
         [0061]    Second terminals of the transconductor transistors  42   a,    42   b  are respectively coupled with a first terminal of a selection transistor  43   a,    43   b  whose gate terminal receives the respective selection signal SEL[ 1 .. 4 ] e.g. from the speculation logic  18 ,  22 . The second terminals of the selection transistors  43   a,    43   b  serve as current sources for the two differential signals. The second terminals of the selection transistors  43   a  of the first branch  41   a  of the speculation units  12  are interconnected and the second terminals of the selection transistors  43   b  of the second branch  41   b  of the speculation units  12  are interconnected to form two differential summing nodes Sn, Sp. 
         [0062]    The interconnections of the first branches  41   a  and the interconnections of the second branches  41   b  are connected to the dynamic regenerator  15 . The dynamic regenerator  15  is activated by the clock signal CLK and serves to hold and amplify the sign of the transconductor current I diff1 , I diff2 , I diff3 , I diff4  to a respective voltage potential and an output. 
         [0063]    The dynamic regenerator  15  is formed by two cross-coupled clocked inverters  53   a,    53   b,  so that the regenerator  15  separates the potentials at the outputs of the transconductors  14  and consequently digitalizes the sign of the current difference between the two transconductor output currents I diff1 , I diff2 , I diff3 , I diff4  of the selected transconductor  14 . 
         [0064]    The dynamic regenerator  15  has two branches  51   a,    51   b  with a series connection to transistors forming cross-coupled inverters  53   a,    53   b.  Further enabling transistors  52   a,    52   b  formed as MOS transistors of a first conductivity type, such as NMOS transistors, are coupled in series in each of the branches  51   a,    51   b,  respectively, with the inverters  53   a,    53   b  to enable the dynamic regenerator  15  based on the clock signal CLK. The outputs of the two inverters  53   a,    53   b  are each coupled with the respective input of the respective other one of the inverters  53   a,    53   b,  so that cross-coupled inverters are provided. The two inputs of the inverters  53   a,    53   b  are coupled with the outputs of the transconductors  14 , respectively. The outputs of the clocked inverters  53   a,    53   b  are interconnected by means of a reset transistor which is activated (closed) by the complementary clock signal level, so that the dynamic regenerator  15  is reset when the clock signal CLK indicates a non-activation of the preamplifier  13 . 
         [0065]    The potentials of the outputs of the transconductors  14  are drawn to voltage levels by the dynamic regenerator  15 , which is then sampled by a domino latch  60  during an active clock phase and held to output the output signal associated to the applied input voltage V inp ,V inn . The domino latch  60  has two branches  61   a,    61   b  including a clocked inverter whose outputs are coupled with a cross coupled inverter pair forming a latch  63  as well known in the art. The cross-coupled inverter pair has a clock input to enable and disable the latch function provided. 
         [0066]    In conventional DFE architectures a clocked comparator latch is provided for each threshold value and one of the comparison results is selected by a subsequent multiplexer. One idea of above embodiments for DFE is to replace such a conventional DFE architecture with a speculation unit including a single dynamic preamplifier which has no latch followed by a selectable transconductor for each threshold value. The speculation unit is applied for each threshold of the unrolled loop of speculation. As no latch and no multiplexer is needed, the combination of the dynamic preamplifier and the means for selectively generating a transconductor current can be implemented with a reduced number of transistors, so that a substantial reduction of power consumption and circuit area as well as a substantial increase in bandwidth are possible. 
         [0067]    By the use of a speculation unit  12  the selection of a comparison result provided by the dynamic preamplifier  13  is kept in the analog domain while the digitalization/sampling is performed after the selection of the respective comparison result has been made in the selectable transconductor  14 . In this manner, latching time and power consumption for performing the latching in each of the speculation units  12  can be avoided, so that power consumption as well as circuit area can be reduced. 
         [0068]      FIGS. 6 a  to 6 c    indicate alternative embodiments of the dynamic preamplifier  13  and the transconductor  14 .  FIG. 6 a    shows an additional cross-coupled cascade  36  formed by cascade transistors  37   a,    37   b  coupled between the second terminal of the input transistor  34   a,    34   b  and the first terminal of the second enable transistor  33   a,    33   b  in each of the branches  31   a,    31   b  of the preamplifier  13 , while the gate terminals are respectively coupled with the first terminal of the respective second enable transistor  33   a,    33   b  of the respective other branch. This allows to achieve a higher gain of the preamplifier  13  while the power consumption is reduced. 
         [0069]      FIG. 6 b    shows a further embodiment, wherein the transconductor  14  is formed as a common gate transconductor so that the transconductor transistors  42   a,    42   b  of the embodiment of  FIG. 5  can be omitted. So the current through the transconductor  14  is produced directly by the preamplifier  13  so that the transconductor  14  simply selects the current to its output. In other words, the preamplifier output node DAOa, DOAb is directly operated as a current source and is directly coupled with the first terminals of the selection transistors  43   a,    43   b,  respectively, so that the preamplifier output node DAOa, DOAb directly supplies the current if selected. 
         [0070]      FIG. 6 c    shows a combination of the embodiments of  FIG. 6 a   , which is the cross-coupled cascade  36 , and of  FIG. 6 b   , which is the common gate transconductor  14 . In the above decision-feedback equalizer only one dynamic regenerator  15  followed by a domino latch  60  is needed.