Abstract:
A method of testing a semiconductor apparatus performs a function test of reading data from memory cells in SRAM by applying a potential lower than a GND potential to a backgate of an n-type MOS transistor with a drain connected with a storage node and a source connected with the GND potential. Then, the method performs a function test of reading data from memory cells by applying a potential higher than the GND potential to the backgate.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method of testing a semiconductor apparatus suitable for detecting a defective cell due to a defective standby current or SNM (static noise margin) deficiency. 
         [0003]    2. Description of Related Art 
         [0004]    Normally, when testing a memory cell such as RAM (Random Access Memory), a BIST (built in self-test) is performed (step S 101 ), a fail bit is read (step S 102 ), and a defective cell is replaced with a redundancy cell by cutting a fuse (step S 103 ), as shown in  FIG. 6 . 
         [0005]    However, in some cases, a cell which places the border of a defective cell and a non-defective cell remains without being replaced. In such a case, there is a problem that memory malfunctioning is likely to occur depending on the LSI use environment, that is, by a temperature or voltage change. Defective modes include a write/read defect caused by the varying threshold of a field-effect transistor constituting a memory cell and an unstable operation caused by the deficiency of SNM, in addition to a leakage defect that has been a problem. These defective modes are aggravated as miniaturization progresses, which raises a problem of a cost increase due to the need for a high-temperature/low-temperature test for reliable removal of a defective cell or the like. 
         [0006]    Japanese Unexamined Patent Application Publication No. 2002-93195 (Shiomi) discloses a method of testing a semiconductor apparatus of which object is detecting a defect of a direct-current electricity such as a standby current defect and saving a defective cell.  FIG. 7  is a view of an SRAM disclosed by Shiomi. The method of testing a semiconductor apparatus taught by Shiomi aims at identifying and saving a defective cell when a standby current flows in the SRAM due to a minute leakage. 
         [0007]    As shown in  FIG. 7 , a memory cell Ml includes an n-channel MOS transistor  80  and an n-channel MOS transistor  82 . The n-channel MOS transistor  80  is connected between a bit line BL 1  and a storage node N 10 , and its gate is connected with a word line WL 1 . The n-channel MOS transistor  82  is connected between a bit line /BL 1  and a storage node N 11 , and its gate is connected with a word line WL 1 . 
         [0008]    The memory cell M 1  further includes an n-channel MOS transistor  74  and an n-channel MOS transistor  78 . The source of the n-channel MOS transistor  74  is connected with the ground voltage GNDM of a memory cell array, the drain is connected with a storage node N 10 , and the gate is connected with a storage node N 11 . The source of the N-channel MOS transistor  78  is connected with the ground voltage GNDM, the drain is connected with the storage node N 11 , and the gate is connected with the storage node N 10 . 
         [0009]    The memory cell M 1  further includes a p-channel MOS transistor  72  and a p-channel MOS transistor  76 . The source of the p-channel MOS transistor  72  is connected with a power supply voltage VCCM for a memory cell array, the drain is connected with the storage node N 10 , and the gate is connected with the storage node N 11 . The source of the p-channel MOS transistor  76  is connected with the power supply voltage VCCM, the drain is connected with the storage node N 11 , and the gate is connected with the storage node N 10 . 
         [0010]    It is assumed that the storage node N 11  of the memory cell M 1  is coupled with the power supply voltage VCCM of the memory cell array by a resistor R 1  to cause short-circuit. The memory cell M 1  is capable of controlling the ground voltage GNDP, which is a substrate voltage of the n-channel MOS transistors  74  and  78  that constitute a memory cell of SRAM, independently of the ground voltage GNDM, which is a source voltage. When the storage node N 11  is “L”, a through current flows in the pass indicated by the arrow. Since the through current keeps flowing in a standby condition, the semiconductor apparatus has a standby defect. When the standby current defect occurs, GNDP is set lower than GND (back bias). As a result, the drive ability of the n-channel MOS transistors  74  and  78  is weakened by body effect. This enables to detect a defect by a function test. It is therefore possible to identify a defective memory cell and replace the defective cell with a redundancy cell, thereby improving process yield. 
         [0011]    However, the method taught by Shiomi only controls a threshold to be higher by applying a back bias. Therefore, although it has a tentative effect that the memory cell which has leakage is easily identified, the method is incapable of detecting the defective mode that becomes more significant as the threshold of the field-effect transistor becomes lower (or a cell current becomes higher), such as an SNM defect. 
       SUMMARY 
       [0012]    In one embodiment, there is provided a method of testing a semiconductor apparatus including a memory including a plurality of memory cells arranged in matrix, each memory cell including a storage node to store data. The method includes performing a function test of writing data to the memory cells and/or reading data from the memory cells by applying a second potential higher than a first potential to a backgate of a field-effect transistor with a drain connected with the storage node and a source receiving the first potential, and performing a function test of writing data to the memory cells and/or reading data from the memory cells by applying a third potential lower than the first potential to the backgate of the field-effect transistor. 
         [0013]    In another embodiment, there is provided a method of testing a semiconductor apparatus including a memory including a plurality of memory cells arranged in matrix, each memory cell including a storage node to store data. The method includes performing a function test of writing data to the memory cells and/or reading data from the memory cells by applying a second potential higher than a first potential to a backgate of an n-type field-effect transistor with a drain connected with the storage node and a source receiving the first potential, and detecting a defective cell. 
         [0014]    According to the embodiments of the present invention, a memory cell is tested with a forward bias by applying a positive electric potential to a P well if a field-effect transistor is an N type and by applying a negative electric potential to an N well if a field-effect transistor is a P type. It is thereby possible to test the memory cell with small SNM and improve the detection sensitively of an SNM defect. It is also possible to improve the detection sensitively of another defective mode which is hard to detect in normal condition by controlling a bias to be applied to each well independently of each other. 
         [0015]    According to the present invention, it is possible to provide a method of testing a semiconductor apparatus which has a high detection sensitivity of the defective mode which becomes significant by a decrease in a threshold (or an increase in a cell current). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0017]      FIG. 1  is a schematic diagram showing a semiconductor apparatus according to an embodiment of the present invention; 
           [0018]      FIG. 2  is a view showing a change in a threshold voltage when a back bias is applied; 
           [0019]      FIG. 3  is a view showing a change in SNM when a forward bias is applied; 
           [0020]      FIG. 4  is a view showing the features when a forward bias is applied and when a back bias is applied as shown in  FIGS. 2 and 3 , respectively; 
           [0021]      FIG. 5  is a flow chart showing a method of testing a semiconductor apparatus according to the embodiment of the present invention; and 
           [0022]      FIG. 6  is a flow chart showing a method of testing a semiconductor apparatus according to a related art; and 
           [0023]      FIG. 7  is a view showing an SRAM disclosed by Shiomi. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0024]    The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
         [0025]    Exemplary embodiments of the present invention are described hereinafter in detail with reference to the drawings.  FIG. 1  is a schematic diagram showing a semiconductor apparatus according to an embodiment of the present invention. A semiconductor apparatus  10  includes a memory  11 , a BIST  12 , a back bias control circuit  14 , and a terminal  15  for test. The BIST  12  includes a defective cell memory  13  which stores a defective address when a defective cell is detected. The defective cell memory  13  may be placed outside of the BIST. 
         [0026]    The back bias control circuit  14  controls the back bias of the N channel and P channel transistors that constitute a memory. In this embodiment, the back bias control circuit  14  supplies a back gate of an N channel transistor with a potential higher than GND (hereinafter referred to as “forward bias”) or a potential lower than GND (hereinafter referred to as “back bias”). The back bias control circuit  14  also supplies a back gate of a P channel transistor with a potential higher than VDD (back bias) or lower than VDD (forward bias). The back bias control circuit  14  controls the biases applied to each well independently of each other. 
         [0027]    Alternatively, the back bias of the memory  11  may be controlled by connecting a tester  21  to the memory through the terminal  15  for test. The tester  21  may input not only a back bias but also a test pattern or the like to the semiconductor apparatus. 
         [0028]    The principle that enables the detection of a defect by the back bias and the forward bias is described hereinafter.  FIG. 2  is a view showing a change in a threshold voltage when a back bias is applied,  FIG. 3  is a view showing a change in SNM when a forward bias is applied, and  FIG. 4  is a view showing the features when a forward bias is applied and when a back bias is applied as shown in  FIGS. 2 and 3 , respectively. 
         [0029]    In  FIG. 2 , I 1  indicates a current of a transistor before applying a back bias, I 2  indicates a current of a transistor after applying a back bias. As shown in  FIGS. 2 and 4 , a threshold Vth becomes larger from Vth 1  to Vth 2  by the back bias application, and an ON current I ON  becomes smaller from I 1  to I 2 . Further, when a voltage=0, a leakage current I off  becomes smaller by the back bias application. 
         [0030]    As just described, the back bias application deepens a threshold voltage, lowers the driven ability of a transistor, and reduces a leakage current. Thus, the leakage current can be detected easily. Further, as a threshold voltage becomes higher, a defect that reading or writing to a memory cell fails is likely to occur. It is thereby possible to improve the detection sensitively of a defective cell transistor of which threshold varies in relatively high values. In addition, this reproduces the operating condition at a low temperature in pseudo. Thus, performing writing by applying a back bias and then performing a read test have the same effect as performing a test at a low temperature, so that a test cost decreases. 
         [0031]      FIG. 3  is a pattern diagram of a so-called butterfly curve which shows the stability of an inverter (cell). SNM is defined as shown in  FIG. 3 . A memory cell operates more stably as an SNM value is larger. Thus, the memory cell which has large SNM has high noise tolerance in keeping data. Generally, as a difference in the threshold of a pair of inverters (L, R) constituting an SRAM cell is greater, SNM is larger. By applying a positive and negative substrate bias, the SNM value can be controlled. Specifically, when a forward bias is applied, the butterfly curve changes from a solid line to a dotted line in  FIG. 3 , and SNM gets smaller. 
         [0032]    As shown  FIG. 4 , the forward bias application controls a threshold voltage to be lower, heightens the drive ability, and increases an ON current and a leakage current. Because the threshold voltage becomes lower, it is possible to improve the detection sensibility of an SNM defect as shown in  FIG. 3 . In addition, this reproduces the operating condition at a high temperature in pseudo. Thus, performing writing by applying a forward bias and then performing a read test have the same effect as performing a test at a high temperature, so that a test cost decreases. 
         [0033]    A method of testing a semiconductor apparatus according to an embodiment of the present invention is described hereinafter.  FIG. 5  is a flow chart showing the method of testing a semiconductor apparatus according to this embodiment. As shown in  FIG. 5 , first, a back bias (inverted bias) is applied to each well (step S 1 ). Specifically, if it is an n-MOS transistor, a negative potential is supplied to a P well, and if it is a p-MOS transistor, a positive potential is supplied to an N well. Then, RAM BIST is performed (step S 2 ), and a fail bit is read out (step S 3 ). By applying a back bias, a leakage defect and a cell which is difficult to write can be detected. In this bout, the defective cell memory  13  stores the address where a fail bit is generated. 
         [0034]    Next, a forward bias is applied to each well (step S 4 ). Specifically, if it is an n-MOS transistor, a positive potential is supplied to a P well, and if it is a p-MOS transistor, a negative potential is supplied to an N well. Then, RAM BIST is performed (step S 5 ), and a fail bit is read out (step S 6 ). By applying a forward bias, a defective cell having small SNM can be detected. Then, a fail cell having the fail address stored in step S 3  and the memory cell having the fail address read out in step S 6  are replaced with displacement cells by cutting a fuse (step S 7 ). In this case, two fuses are cut: one for selecting a displacement cell and one for stopping the supply of a power supply current to a defective cell. 
         [0035]    According to this embodiment, a defect detection test of a memory is performed by applying not only a back bias but also a forward bias, so that a defective cell of which threshold varies in high values as well as low values can be detected. Specifically, it is possible to produce the condition of performing a test at a high temperature and at a low temperature in pseudo, thus eliminating the need for performing a high temperature test and a low temperature test. This enables reduction of a test time and cost. By adapting this test, a defective cell due to a large variety of defect modes such as a leakage defect, a write defect and an SNM defect can be detected. 
         [0036]    The present invention is not limited to the embodiment described above, and a variety of modifications that do not depart from the gist of the invention are possible. For example, although the test shown in  FIG. 5  performs a test with the forward bias application after performing a test with the back bias application, it may perform a test with the back bias application after performing a test with the forward bias application. Further, although a test is performed by applying both a back bias and a forward bias, it may be performed by applying only a forward bias. The test with the forward bias application enables the detection of an SNM defect. Further, the detection sensitivity of other modes, which are difficult to detect in normal operation, can be improved by controlling a voltage applied to each well independently or by combining a back bias and a forward bias. 
         [0037]    Furthermore, although the RAM BIST is performed with the back bias and forward bias application in the above-described embodiment, a reading or writing test may be performed by a tester. Although a large variety of tests are performed in the memory, it is not necessary to perform a test with the back bias and forward bias application in all tests. 
         [0038]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.