Abstract:
A control circuit and control method for a power converter detects change of the output voltage of the converter, and performs the time-optimal control function when the change exceeds the default value. According to the voltage slew rate detected at the time of the change exceeding the default value, a time interval T 1  from the change exceeding the default value being detected to the current of the inductor rising to be the same as the output current of the converter is estimated, and the time intervals T 2  and T 3  are figured out based on the time interval T 1 . The parasitic resistance of the output capacitor of the converter is taken into account during estimating process such that even if the output capacitor has larger parasitic resistance, the output voltage can be back to the steady state value accurately to avoid the time-optimal control being triggered repeatedly.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to a power converter, and particularly to a control circuit and method for the power converter. 
     2. Brief Description of the Related Art 
     Due to the semiconductor technology being developed progressively, the digital products such as the computer and the peripherals thereof are capable of being upgraded continuously. The fast change of the manufacturing process for the semiconductor results in a variety of demands for the power source of the integrated circuit (IC) employed in the computer and the peripherals thereof. Hence, the pulse width modulation voltage regulators composed of various power converters such as the boost converter and the buck converter to meet the need of different integrated circuits become one of the most important factors to determine if versatile digital products are capable of being presented. 
     The output voltage of a power converter should be maintained at a steady state instead of rising or dropping corresponding to change of the load during the power converter working normally. However, when the type of the output of the power converter during the load being drawn is instantaneous step change, most part of the current output of the power converter is provided with the output capacitor and it results in the voltage rising or dropping rapidly. 
     For solving this problem, literatures “Z. Zhao, A. Prodic, Continuous-time digital controller for high-frequency DC-DC converters, IEEE TRANSACTIONS ON POWER ELECTRONICS, March 2008” and “E. Meyer, Z. Zhang, Y.-F. Liu, An optimal control method for buck converters using a practical capacitor charge balance technique, IEEE TRANSACTIONS ON POWER ELECTRONICS, JULY 2008” have proposed the nonlinear control, and the authors entitle it as time-optimal control (TOC) method. When the instantaneous step change occurs during the load being drawn, the power switch is fully ON/OFF a period of time, and it is expected that the inductance current and the output voltage are capable of meeting the steady state of the output specification at end of the time-optimal control. 
     In addition, the literature “A. Costabeber, L. Corradini, P. Mattavelli, S. Saggini, Time optimal, parameters-insensitive digital controller for DC-DC buck converter, PESC, 2008” proposes two TOC methods suitable for buck converter, time-based TOC method and voltage-based TOC method. The fundamental theories of the two control methods are based on the wave shapes of voltage and current shown in  FIG. 1  and stated hereinafter. 
     Steps of the time-based TOC method are detecting if change of the output voltage V o  of the power converter exceeds a default value ΔV th , i.e., t 0  in  FIG. 1 , and starting the control if the change exceeds the default value ΔV th , detecting the lowest point V valley  of the output voltage V o  of the power converter and setting a time interval T 1  between t 0  and time corresponding to the lowest point V valley , figuring out Q 0  and Q 1  of reducing voltages of the output capacitor and Q 2  and Q 3  of increasing voltages of the output capacitor according to the principle of electric charge equilibrium and setting Q 0 +Q 1 =Q 2 +Q 3  such that it can be expected that V o  restores to the original value thereof so as to calculate the time interval T 1 +T 2  of the power switch being fully ON and the time interval T 3  of the power switch being fully OFF. The related equation is expressed in the following: 
             {                         C   ·   Δ     ⁢           ⁢     V   th       +       ∫   0     T   1       ⁢       ∫   0   t     ⁢           V   in     -     V   ref       L     ⁢           ⁢     ⅆ   τ     ⁢           ⁢     ⅆ   t             =         ∫   0     T   2       ⁢       ∫   0   t     ⁢           V   in     -     V   ref       L     ⁢           ⁢     ⅆ   τ     ⁢           ⁢     ⅆ   t           +                   ∫   0     T   3       ⁢       ∫   0   t     ⁢         V   ref     L     ⁢           ⁢     ⅆ   τ     ⁢           ⁢     ⅆ   t                               T   2       T   3       =         V   ref         V   in     -     V   ref         =     D     1   -   D                 ⇒     
     ⁢     {             T   2     =       D     ·         T   1   2     +       2   ⁢     LC   ·   Δ     ⁢           ⁢     V   th           V   in     -     V   ref                             T   3     =         1   -   D     D     ·     T   2                         
wherein V ref  represents the reference voltage, V in  represents an input voltage of the buck converter, L represents the inductance, C represents the output capacitance, and D represents the duty cycle of the buck converter at steady state.
 
     Steps of the voltage-based TOC method are detecting if change of the output voltage V o  of the power converter exceeds a default value ΔV th , i.e., t 0  in  FIG. 1 , and starting the control if the change exceeds the default value ΔV th , detecting the lowest point V valley  of the output voltage V o  of the power converter and setting a time interval T 1  between t 0  and time corresponding to the lowest point V valley , figuring out a state transfer point V sw  with the lowest point V valley , measuring and setting a time interval T 2  between V valley  and V sw  for calculating the time interval T 1 +T 2  of the power switch being fully ON and the time interval T 3  of the power switch being fully OFF. The related equation is expressed in the following: 
                   {             V   sw     =       V   ref     -       (     1   -   D     )     ·     (       V   ref     -     V   valley       )                       T   3     =         1   -   D     D     ·     T   2                       
wherein V ref  represents the reference voltage of the buck converter, and D represents the duty cycle of the buck converter at steady state.
 
     It is ideally supposed in the preceding methods that no parasitic resistance in the output capacitor of the buck converter. In case of the parasitic resistance being taken into account, the preceding literatures propose a correction to extend time duration R c ·C for the power switch being ON, but it has been mentioned that the correction is not applied to a larger parasitic resistance. Besides, when the inductance L of the buck converter is getting smaller and the output capacitor C and the parasitic resistance are getting larger, T 1  detected with the time-based TOC method is 0, and the voltage-based TOC method is unable to figure out the voltage transfer point correctly due to the output voltage containing a voltage drop of the parasitic resistance. Hence, it is not possible for the output voltage of the power converter to restore to the steady state value at end of the TOC, and it results in the system triggering the TOC repeatedly and the circuit being incapable of working normally. 
     SUMMARY OF THE INVENTION 
     Accordingly, a main object of the present invention is to provide a control circuit and method for a power converter with which the output voltage is capable of restoring to the steady state value accurately even if greater parasitic resistance is in the output capacitor of the buck converter such that the phenomenon of the TOC being triggered repeatedly is avoided substantively. 
     In order to achieve the preceding object and other objects not mentioned above, a control circuit and method for a power converter, which are suitable for generating a stable voltage control signal to control ON/OFF of a power switch of a synchronous rectified buck converter with an inductor and an output capacitor; the control circuit comprises a difference generating circuit, a pulse width modulation circuit including such as a compensator and a pulse width modulator, a TOC circuit, and a multiplexer for performing the control method for the power converter. 
     Wherein, the difference generating circuit receives the output voltage and the reference voltage of the synchronous rectified buck converter and acquires a voltage difference between the output voltage and the reference voltage; the compensator generates a pulse width control signal based on the voltage difference; the pulse width modulator is controlled by the pulse width control signal and generates a pulse width modulation signal; the time-optimal control (TOC) circuit detects change of the output voltage, creates a time-optimal control signal and a select signal when the change exceeds a default value. 
     The time-optimal control signal is based on a voltage slew rate detected at the time of the change exceeding the default value to estimate a time interval T 1  from the change exceeding the default value being detected to the current of the inductor rising to be the same as the output current of the synchronous rectified buck converter, to figure out time intervals T 2  and T 3  based on the time interval T 1  for the time-optimal control signal maintaining at a level during the time intervals T 1  and T 2 , maintaining at another level during the time interval T 3  and generating the select signal in the time intervals T 1 , T 2  and T 3 ; the multiplexer is based on the select signal to select either the pulse width modulation signal sent out from the pulse width modulation circuit or the time-optimal control signal sent out from the TOC circuit to output the stable voltage control signal for controlling ON/OFF of the power switch of the synchronous rectified buck converter. 
     Wherein, the time interval T 1  is obtained via calculation of following equations: 
                       T     1   ⁢   up       =       LC       V   in     -     V   ref         ·       [           R   c     L     ⁢     (       V   in     -     V   ref       )       -       ⅆ       V   o     ⁡     (   t   )           ⅆ   t                t   =     t   0             ]                   T     1   ⁢   down       =       LC     V   ref       ·       [           R   c     L     ·     V   ref       +       ⅆ       V   o     ⁡     (   t   )           ⅆ   t                t   =     t   0             ]               
wherein T 1 _up represents a time interval T 1  during load increasing, T 1 _down represents a time interval T 1  during load decreasing, V in  represents an input voltage of the synchronous rectified buck converter, V o  represents the output voltage, V ref  represents the reference voltage, L represents the inductance, C represents the capacitance, and R C  represents a parasitic resistance of the output capacitor.
 
     Wherein, the time intervals T 2  and T 3  are obtained via calculation of following equations: 
               Δ   ⁢           ⁢     V     c   ⁢           ⁢   0         =       Δ   ⁢           ⁢     V   th       -     Δ   ⁢           ⁢       I   0     ·     R   c                         T     2   ⁢   up       =       D     ·         T     1   ⁢     _   ⁢   up       2     +       2   ⁢     LC   ·   Δ     ⁢           ⁢     V     c   ⁢           ⁢   0             V   in     -     V   ref                             T     3   ⁢   up       =         1   -   D     D     ·     T     2   ⁢   up                       T     2   ⁢   up       =             1   -   D       ·         T     1   ⁢   down     2     +       2   ⁢     LC   ·   Δ     ⁢           ⁢     V     c   ⁢           ⁢   0           V   ref             ⁢     
     ⁢     T     3   ⁢   down         =       D     1   -   D       ·     T     2   ⁢   down                 
wherein T 2     —     up  and T 3     —     up  represent T 2  and T 3  time intervals during load increasing, T 2     —     down  and T 3     —     down  represent T 2  and T 3  time intervals during load decreasing, ΔV th  represents the default value, ΔI o  represents increment or decrement of the output current of the synchronous rectified buck converter, and D represents a duty cycle of the pulse width modulation signal.
 
     In a preferred embodiment, the TOC circuit includes a first comparator, a second comparator and a controller to perform the steps of the control method respectively; the first compensator detects change of sudden rise of the output voltage, and outputs a voltage sudden rise signal when the change of sudden rise of the output voltage exceeds the default value; the second comparator detects change of sudden drop of the output voltage, and outputs a voltage sudden drop signal when the change of sudden drop of the output voltage exceeds the default value; the controller generates the time-optimal control signal and the select signal based on the voltage sudden rise signal and the voltage sudden drop signal. 
     As it has been previously stated, a control circuit and control method for a power converter according to the present invention has taken the parasitic resistance of the output capacitor of the buck converter into account at the time of calculating the time intervals T 1 , T 2  and T 3 . Therefore, it allows the output voltage restores to the steady state value accurately even if the output capacitor has larger parasitic resistance, and the situation regarding the TOC being triggered repeatedly can be avoid substantively. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The detailed structure, the applied principle, the function and the effectiveness of the present invention can be more fully understood with reference to the following description and accompanying drawings, in which: 
         FIG. 1  is a graph illustrating voltage and current wave shapes during the load of the buck converter increasing when the conventional method of time-optical control is applied; 
         FIG. 2  is a block diagram illustrating a preferred embodiment of a control circuit for a power converter according to the present invention; 
         FIG. 3  is a graph illustrating voltage and current wave shapes during the load of the buck converter increasing when a control method corresponding to the control circuit for a power converter shown in  FIG. 2  is applied; 
         FIG. 4  is an equivalent circuit to the synchronous rectified buck converter shown in  FIG. 2  at the time of the power switch conduction; 
         FIG. 5  is a graph illustrating voltage and current wave shapes during the load of the buck converter decreasing when a control method corresponding to the control circuit for a power converter shown in  FIG. 2  is applied; 
         FIG. 6  is a block diagram illustrating a control circuit for a power converter shown in  FIG. 2  during the load of the buck converter increasing; 
         FIG. 7  is a block diagram illustrating a control circuit for a power converter shown in  FIG. 2  during the load of the buck converter decreasing; 
         FIG. 8  is a graph shown simulating results of the time-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =5 mΩ with load increasing; 
         FIG. 9  is a graph shown simulating results of the voltage-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =5 mΩ with load increasing; 
         FIG. 10  is a graph shown simulating results of the voltage-slew-rate-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =5 mΩ with load increasing; 
         FIG. 11  is a graph shown simulating results of the time-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =10 mΩ with load increasing; 
         FIG. 12  is a graph shown simulating results of the voltage-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =10 mΩ with load increasing; 
         FIG. 13  is a graph shown simulating results of the voltage-slew-rate-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =10 mΩ with load increasing; 
         FIG. 14  is a graph shown simulating results of the time-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =10 mΩ with load decreasing; 
         FIG. 15  is a graph shown simulating results of the voltage-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =10 mΩ with load decreasing; 
         FIG. 16  is a graph shown simulating results of the voltage-slew-rate-based time-optimal control when the parasitic resistance of the output capacitor of the buck converter is R C =10 mΩ with load decreasing. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 2 , the preferred embodiment of a control circuit for a power converter according to the present invention is illustrated. In  FIG. 2 , the control circuit  20  comprises a difference generation circuit such as an adder  21 , a pulse width modulation circuit including a compensator  22  and a pulse width modulator  23 , a time-optimal control circuit  24  and a multiplexer  25 . The preceding components perform steps of the control method for the power converter, and a stable voltage control signal PWM_O can be generated to control ON/OFF of a power switch  263  of the synchronous-rectified buck converter  26  which has the inductor  261  and the output capacitor  262 . 
     Wherein the adder  21  receives an reference voltage V ref  and an output voltage V o  of the synchronous-rectified buck converter  26  to acquire an voltage difference V diff  between the output voltage V o  and the reference voltage V ref . The compensator  22 , which can be a digital compensator, references to the voltage difference V diff  sent out by the adder  21  to generate a pulse width control signal PWM_C. The pulse width modulator  23  is controlled by the pulse width control signal PWM_C to create a pulse modulation signal PWM_S. The time-optimal control (TOC) circuit  24  detects change of the output voltage V o  of the synchronous-rectified buck converter  26 . When the change of the output voltage V o  exceeds a default value ΔV th , a time-optimal control signal TOC_o and a selection signal TOC_sel are produced for the multiplexer  25  selectively generating the stable voltage control signal PWM_O. 
     Referring to  FIG. 3  with reference to  FIG. 2 ,  FIG. 3  shows the wave shapes of the voltage and the current of the buck converter in a state of load increasing when the control method applies to the control circuit of the power converter shown in  FIG. 2 . As described previously, the conventional time-based TOC method and the voltage-base TOC method reference to wave shapes of the voltage and the current shown in  FIG. 1  as the theoretical basis of control without considering the parasitic resistance R C  of the output capacitor  262 . However, it results in that the output voltage V o  of the synchronous-rectified buck converter  26  is incapable of restoring to the steady state value after the time-optimal control is done such that the system probably triggers the time-optical control repeatedly and it leads to be unable to perform the work normally. Thus, the control method adopted by the TOC control circuit  24  of the control circuit  20  for power converter shown in  FIG. 2  is to take the parasitic resistance R C  of the output capacitor  262  into account to avoid the situation of the TOC being triggered repeatedly. 
     Therefore, the time-optimal control signal TOC_o estimates a time period T 1  from the change of the output voltage V o  exceeding the default value ΔV th  to an current I L  of the inductor  261  rising to a value the same as an output current I o  of the synchronous rectified buck converter  26  according to the voltage slew rate at the time of the change of the output voltage V o  exceeding the default value ΔV th , and then figures out time periods T 2  and T 3  based on the time interval T 1  for the time-optimal control signal TOC_o being at a reference level to keep the power switch  263  being in a state of ON during the time intervals T 1  and T 2  and being at a reference level to keep the power switch  263  being in a state of OFF during the time interval T 3  and creating the aforementioned selection signal TOC_sel during the time intervals T 1 , T 2  and T 3 . 
     The selection signal TOC_sel acts as a mode switching signal of the multiplexer  25  to output the pulse width modulation signal PWM_S sent out from the pulse width modulator  23  as the stable voltage control signal PWM_O to control ON and OFF of the power switch  263  of the synchronous rectified buck converter  26  when the linear mode of normal work is selected; the time-optimal control signal TOC_o sent out from the TOC circuit  24  is output as the stable voltage control signal PWM_O to control ON and OFF of the power switch  263  of the synchronous rectified buck converter  26  when the change of the output voltage V o  exceeds the default value ΔV th  and enters the TOC mode such that the power switch  263  is in a state of ON during the time intervals T 1  and T 2  and the power switch  263  is in a state of OFF during the time interval T 3 . The way to estimate the time intervals T 1 , T 2  and T 3  is stated hereinafter. 
     When the TOC mode is entered, the power switch  263  of the synchronous rectified buck converter  26  shown in  FIG. 2  is controlled by the stable voltage control signal PWM_O and becomes ON with an equivalent circuit shown in  FIG. 4 . Therefore, the output current increment ΔI o  of the synchronous rectified buck converter  26  in time t o  is expressed as: 
                     Δ   ⁢           ⁢     I   0       =           I   0     ⁡     (     t   0     )       -       I   L     ⁡     (     t   0     )         =       -       I   C     ⁡     (     t   0     )         =         -   C     ⁢       ⅆ       V   C     ⁡     (   t   )           ⅆ   t         ⁢     ❘     t   =     t   0                       (   1   )               
wherein C represents capacitance of the output capacitor  262 . The rising slope of the current of the inductor  261  is approximate to:
 
                 ⅆ       I   L     ⁡     (   t   )           ⅆ   t       ≅         V   in     -     V   ref       L           
and
 
                 V   o     ⁢           ⁢     (   t   )       =             V   C     ⁢           ⁢     (   t   )       +       I   C     ⁢           ⁢     (   t   )     ⁢     R   C         ⇒       ⅆ       V   o     ⁡     (   t   )           ⅆ   t         =             ⅆ       V   C     ⁡     (   t   )           ⅆ   t       +       R   C     ⁢       ⅆ       I   C     ⁡     (   t   )           ⅆ   t           ⇒       ⅆ       V   o     ⁡     (   t   )           ⅆ   t         =           ⅆ       V   C     ⁡     (   t   )           ⅆ   t       +       R   C     ⁢     ⅆ     ⅆ   t       ⁢           ⁢     (         I   L     ⁢           ⁢     (   t   )       -     I   o       )         ⇒         ⅆ       V   o     ⁡     (   t   )           ⅆ   t       ≅         ⅆ       V   C     ⁡     (   t   )           ⅆ   t       +       R   C     ⁢         V   in     -     V   ref       L           ⇒         ⅆ       V   C     ⁡     (   t   )           ⅆ   t       ≅         ⅆ       V   o     ⁡     (   t   )           ⅆ   t       -       R   C     ⁢         V   in     -     V   ref       L                       
wherein V in , and V o  represent the input voltage and output voltage of the synchronous rectified buck converter  26  respectively, V ref  represents reference voltage, L represents inductance of the inductor  261 , and R c  represents parasitic resistance of the output capacitor  262 . The preceding expression is substituted in equation (1) and it can be obtained:
 
                     Δ   ⁢           ⁢     I   0       =           -   C     ⁢       ⅆ       V   C     ⁡     (   t   )           ⅆ   t         ⁢     ❘     t   =     t   0           =     C   ⁡     [             R   C     L     ⁢     (       V   in     -     V   ref       )       -       ⅆ       V   O     ⁡     (   t   )           ⅆ   t         ⁢     ❘     t   =     t   0           ]                 (   2   )               
Hence, time interval T 1  for load increasing T 1     —     up  can be obtained via calculation of the following equation:
 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
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     In  FIG. 3 , when the change of the output voltage V o  exceeding the default value ΔV th  are detected to enter the TOC mode at the time t 0 , the output capacitor  262  has lost part of electric charges Q 0 =C·ΔV CO , wherein
 
Δ V   C0   =ΔV   th   −ΔI   O   ·R   C 
 
     
       
         
           
             
               
                 
                   
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     In equation (4), when ΔV CO  is calculated as a negative value, it means the output capacitor  262  does not lose electric charges before entering the TOC mode. Under this circumference, it is correct that ΔV CO  has to be set as 0. According to the theory of electric charge equilibrium, the time intervals T 2  and T 3  for load increasing T 2     —     up  and T 3     —     up  can be obtained via calculation of the following equation: 
                   {                   C   ·   Δ     ⁢           ⁢     V     C   ⁢           ⁢   0         +       ∫   0     T   1       ⁢       ∫   0   t     ⁢           V   in     -     V   ref       L     ⁢           ⁢     ⅆ   τ     ⁢           ⁢     ⅆ   t             =         ∫   0     T   2       ⁢       ∫   0   t     ⁢           V   in     -     V   ref       L     ⁢           ⁢     ⅆ   τ     ⁢           ⁢     ⅆ   t           +       ∫   0     T   3       ⁢       ∫   0   t     ⁢         V   ref     L     ⁢           ⁢     ⅆ   τ     ⁢           ⁢     ⅆ   t                             T   2       T   3       =         V   ref         V   in     -     V   ref         =     D     1   -   D                 ⇒     {             T     1   ⁢     _   ⁢   up         =       LC       V   in     -     V   ref         ·     (             R   C     L     ⁢           ⁢     (       V   in     -     V   ref       )       -       ⅆ       V   o     ⁡     (   t   )           ⅆ   t         ⁢     ❘     t   =     t   0           )                     T     2   ⁢     _   ⁢   up         =       D     ·         T     1   ⁢     _   ⁢   up       2     +       2   ⁢     LC   ·   Δ     ⁢           ⁢     V     C   ⁢           ⁢   0             V   in     -     V   ref                             T     3   ⁢     _   ⁢   up         =         1   -   D     D     ·     T     2   ⁢     _   ⁢   up                               (   5   )               
Wherein D represents duty cycle of the pulse width modulation signal PWM_S.
 
     Referring to  FIG. 5 , the wave shapes of the voltage and the current of the buck converter in a state of load decreasing when the control method applies to the control circuit of the power converter shown in  FIG. 2 . According to the same principle, the time intervals T 1 , T 2  and T 3  for load decreasing T 1     —     down , T 2     —     down  and T 3     —     down  can be obtained via calculation of the following equation: 
     
       
         
           
             
               
                 
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                                       ⅆ 
                                       τ 
                                     
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     
                                       ⅆ 
                                       t 
                                     
                                   
                                 
                               
                             
                             = 
                             
                               
                                 
                                   ∫ 
                                   0 
                                   
                                     T 
                                     2 
                                   
                                 
                                 ⁢ 
                                 
                                   
                                     ∫ 
                                     0 
                                     t 
                                   
                                   ⁢ 
                                   
                                     
                                       
                                         V 
                                         ref 
                                       
                                       L 
                                     
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     
                                       ⅆ 
                                       τ 
                                     
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     
                                       ⅆ 
                                       t 
                                     
                                   
                                 
                               
                               + 
                               
                                 
                                   ∫ 
                                   0 
                                   
                                     T 
                                     3 
                                   
                                 
                                 ⁢ 
                                 
                                   
                                     ∫ 
                                     0 
                                     t 
                                   
                                   ⁢ 
                                   
                                     
                                       
                                         
                                           V 
                                           in 
                                         
                                         - 
                                         
                                           V 
                                           ref 
                                         
                                       
                                       L 
                                     
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     
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                                       τ 
                                     
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     
                                       ⅆ 
                                       t 
                                     
                                   
                                 
                               
                             
                           
                         
                       
                       
                         
                           
                             
                               
                                 T 
                                 2 
                               
                               
                                 T 
                                 3 
                               
                             
                             = 
                             
                               
                                 
                                   
                                     V 
                                     in 
                                   
                                   - 
                                   
                                     V 
                                     ref 
                                   
                                 
                                 
                                   V 
                                   ref 
                                 
                               
                               = 
                               
                                 
                                   1 
                                   - 
                                   D 
                                 
                                 D 
                               
                             
                           
                         
                       
                     
                     ⇒ 
                     
                       { 
                       
                         
                           
                             
                               
                                 T 
                                 
                                   1 
                                   ⁢ 
                                   
                                     _ 
                                     ⁢ 
                                     down 
                                   
                                 
                               
                               = 
                               
                                 
                                   LC 
                                   
                                     V 
                                     ref 
                                   
                                 
                                 · 
                                 
                                   ( 
                                   
                                     
                                       
                                         
                                           
                                             R 
                                             C 
                                           
                                           L 
                                         
                                         · 
                                         
                                             
                                         
                                         ⁢ 
                                         
                                           V 
                                           ref 
                                         
                                       
                                       + 
                                       
                                         
                                           ⅆ 
                                           
                                             
                                               V 
                                               o 
                                             
                                             ⁡ 
                                             
                                               ( 
                                               t 
                                               ) 
                                             
                                           
                                         
                                         
                                           ⅆ 
                                           t 
                                         
                                       
                                     
                                     ⁢ 
                                     
                                       ❘ 
                                       
                                         t 
                                         = 
                                         
                                           t 
                                           0 
                                         
                                       
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                         
                         
                           
                             
                               
                                 T 
                                 
                                   2 
                                   ⁢ 
                                   
                                     _ 
                                     ⁢ 
                                     down 
                                   
                                 
                               
                               = 
                               
                                 
                                   
                                     1 
                                     - 
                                     D 
                                   
                                 
                                 · 
                                 
                                   
                                     
                                       T 
                                       
                                         1 
                                         ⁢ 
                                         
                                           _ 
                                           ⁢ 
                                           down 
                                         
                                       
                                       2 
                                     
                                     + 
                                     
                                       
                                         2 
                                         ⁢ 
                                         
                                           LC 
                                           · 
                                           Δ 
                                         
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         
                                           V 
                                           
                                             C 
                                             ⁢ 
                                             
                                                 
                                             
                                             ⁢ 
                                             0 
                                           
                                         
                                       
                                       
                                         V 
                                         ref 
                                       
                                     
                                   
                                 
                               
                             
                           
                         
                         
                           
                             
                               
                                 T 
                                 
                                   3 
                                   ⁢ 
                                   
                                     _ 
                                     ⁢ 
                                     down 
                                   
                                 
                               
                               = 
                               
                                 
                                   D 
                                   
                                     1 
                                     - 
                                     D 
                                   
                                 
                                 · 
                                 
                                   T 
                                   
                                     2 
                                     ⁢ 
                                     
                                       _ 
                                       ⁢ 
                                       down 
                                     
                                   
                                 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     In  FIG. 2 , the TOC circuit  24  is implemented with comparators  241 ,  242  and a controller  243 . Wherein the comparator  241  detects a change of sudden rise of the output voltage V o  and sends out a sudden voltage rise signal TOC_hi at the time of the output voltage V o  suddenly rising over the default value ΔV th , and the comparator  242  detects a change of sudden drop of the output voltage V o  and sends out a sudden voltage drop signal TOC_lo at the time of the output voltage V o  suddenly dropping below the default value ΔV th . 
     The controller  243  is based on the sudden voltage rise signal TOC_hi and the sudden voltage drop signal TOC_lo and references to the equations (5) and (6) to figure out and create the aforementioned time-optimal control signal TOC_o and the selection signal TOC_sel such that the power switch  263  is ON at the time intervals T 1     —     up  and T 2     —     up  and is OFF at the time interval T 3     —     up , or is OFF at the time intervals T 1     —     down  and T 2     —     down  and is ON at the time interval T 3     —     up . In this way, the linear mode with the normal work can be resumed afterward. 
     Referring to  FIGS. 6 and 7 , the block diagrams illustrated in  FIGS. 6 and 7  are capable of implementing the controller  243  shown in  FIG. 2 . Wherein parameters a 1 , a 2 , a 3 , a 4 , a 5 , a 6 , and a 7  are obtained via rearrangement of equation (5), and parameters b 1 , b 2 , b 3 , b 4 , b 5 , b 6  and b 7  are obtained via rearrangement of equation (6). The rearrangement for equations (5) and (6) is expressed hereinafter. 
               V     O   ⁢           ⁢   _   ⁢           ⁢   SR       =           ⅆ       V   o     ⁡     (   t   )           ⅆ   t       ⁢     ❘     t   =     t   0         ⁢     
     ⁢     T     1   ⁢   _   ⁢           ⁢   up         =         LC       V   in     -     V   ref         ⁢     (           R   c     L     ⁢     (       V   in     -     V   ref       )       -     V     o   ⁢           ⁢   _   ⁢           ⁢   SR         )       =           R   c     ⁢   C     -       LC       V   in     -     V   ref         ⁢     V     o   ⁢           ⁢   _   ⁢           ⁢   SR           =       a   1     +       a   2     ⁢     V     o   ⁢           ⁢   _   ⁢           ⁢   SR                               T     2   ⁢   _   ⁢           ⁢   up       =             T     1   ⁢   _   ⁢           ⁢   up     2     ⁢   D     +         2   ⁢   LC   ⁢           ⁢   Δ   ⁢           ⁢     V   th           V   in     -     V   ref         ⁢           ⁢   D     -     2   ⁢     LCR   c     ⁢   C   ⁢           ⁢       R   c     L     ⁢           ⁢   D     +         2   ⁢     LCR   c     ⁢   C         V   in     -     V   ref         ⁢     DV     o   ⁢   _   ⁢   SR             =             a   3     ⁢           ⁢     T     1   ⁢   _   ⁢           ⁢   up     2       +     a   4     +     a   5     +       a   6     ⁢           ⁢     DV     o   ⁢   _   ⁢   SR           ⁢                               T     3   ⁢   _   ⁢           ⁢   up       =           1   -   D     D     ⁢     T     2   ⁢   _   ⁢           ⁢   up         =       a   7     ⁢           ⁢     T     2   ⁢   _   ⁢           ⁢   up                 
wherein, when ΔV C0 ≦0, T 2     —     up =√{square root over (DT 1     —     up   2 )}=√{square root over (α 3 T 1     —     up   2 )}, hence
 
               a   1     =       R   c     ⁢   C                   a   2     =     -     LC       V   in     -     V   ref                         a   3     =   D                 a   4     =         2   ⁢   LC   ⁢           ⁢   Δ   ⁢           ⁢     V   th           V   in     -     V   ref         ⁢   D                   a   5     =       -   2     ⁢     LCR   c     ⁢   C   ⁢       R   c     L     ⁢   D                   a   6     =         2   ⁢     LCR   c     ⁢   C         V   in     -     V   ref         ⁢   D                   a   7     =         1   -   D     D     ⁢           ⁢   and                   T     1   ⁢   _   ⁢           ⁢   down       =         LC     V   ref       ⁢     (           R   c     L     ⁢     V   ref       +     V     o   ⁢           ⁢   _   ⁢           ⁢   SR         )       =           R   c     ⁢   C     +       LC     V   ref       ⁢     V     o   ⁢           ⁢   _   ⁢           ⁢   SR           =       b   1     +       b   2     ⁢     V     o   ⁢           ⁢   _   ⁢           ⁢   SR                             T     2   ⁢   _   ⁢           ⁢   down       =           T     1   ⁢   _   ⁢           ⁢   down     2     =       (     1   -   D     )     +         2   ⁢   LC   ⁢           ⁢   Δ   ⁢           ⁢     V   th         V   ref       ⁢     (     1   -   D     )       -     2   ⁢     LCR   c     ⁢   C   ⁢       R   c     L     ⁢     (     1   -   D     )       -         2   ⁢     LCR   c     ⁢   C       V   ref       ⁢     (     1   -   D     )     ⁢     V     o   ⁢           ⁢   _   ⁢           ⁢   SR               =           b   3     ⁢     T     1   ⁢           ⁢   _   ⁢           ⁢   down     2       +     b   4     +     b   5     +       b   6     ⁢     V     o   ⁢           ⁢   _   ⁢           ⁢   SR                             T     3   ⁢   _   ⁢           ⁢   down       =         D     1   -   D       ⁢     T     2   ⁢   _   ⁢           ⁢   down         =       b   7     ⁢     T     2   ⁢   _   ⁢           ⁢   down                 
wherein, when ΔV C0 ≦0, T 2     —     down =√{square root over ((1)−D)·T 1     —     down   2 )}=√{square root over (α 3 T 1     —     down   2 )}, hence
 
     
       
         
           
             
               b 
               1 
             
             = 
             
               
                 R 
                 c 
               
               ⁢ 
               C 
             
           
         
       
       
         
           
             
               b 
               2 
             
             = 
             
               LC 
               
                 V 
                 ref 
               
             
           
         
       
       
         
           
             
               b 
               3 
             
             = 
             
               1 
               - 
               D 
             
           
         
       
       
         
           
             
               b 
               4 
             
             = 
             
               
                 
                   2 
                   ⁢ 
                   LC 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   Δ 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     V 
                     th 
                   
                 
                 
                   V 
                   ref 
                 
               
               ⁢ 
               
                 ( 
                 
                   1 
                   - 
                   D 
                 
                 ) 
               
             
           
         
       
       
         
           
             
               b 
               5 
             
             = 
             
               
                 - 
                 2 
               
               ⁢ 
               
                 LCR 
                 c 
               
               ⁢ 
               C 
               ⁢ 
               
                 
                   R 
                   c 
                 
                 L 
               
               ⁢ 
               
                 ( 
                 
                   1 
                   - 
                   D 
                 
                 ) 
               
             
           
         
       
       
         
           
             
               b 
               6 
             
             = 
             
               
                 - 
                 
                   
                     2 
                     ⁢ 
                     
                       LCR 
                       c 
                     
                     ⁢ 
                     C 
                   
                   
                     V 
                     ref 
                   
                 
               
               ⁢ 
               
                 ( 
                 
                   1 
                   - 
                   D 
                 
                 ) 
               
             
           
         
       
       
         
           
             
               b 
               7 
             
             = 
             
               D 
               
                 1 
                 - 
                 D 
               
             
           
         
       
     
     Referring to  FIGS. 8 to 10 , results of simulations for different TOC methods applying to load increasing are illustrated when the parasitic resistance of the output capacitor of the buck converter is R c =5 mΩ. The parameters are set as the input voltage V in =3.3V, the reference voltage V rer =1.5V, the inductance L=3.3 μH, the output capacitance C=1300 μF, and the load current increasing to 10 A from 1 A. It can be learned from the results shown in the figures that good stable effect of the output voltage can be reached under the operation condition regardless the time-based TOC shown in  FIG. 8 , the voltage-based TOC shown in  FIG. 9  and the voltage-slew-rate-based TOC shown in  FIG. 10 . 
     Referring to  FIGS. 11 to 13 , results of simulations for different TOC methods applying to load increasing are illustrated when the parasitic resistance of the output capacitor of the buck converter is R c =10 mΩ. The parameters are the same as set in  FIGS. 8 to 10 . It can be seen that only result of the voltage-slew-rate-based TOC shown in  FIG. 13  still reach good stable effects for the output voltage under the operation condition, but the result of the time-based TOC shown in  FIG. 11  has lower output voltage and the result of the voltage-based TOC shown in  FIG. 12  has higher output voltage when the work resumes to normal mode. 
     Referring to  FIGS. 14 to 16 , results of simulations for different TOC methods applying to load decreasing are illustrated when the parasitic resistance of the output capacitor of the buck converter is R c =10 mΩ. The parameters are the same as set in  FIGS. 8 to 10 . It can be seen that results of the time-based TOC shown in  FIG. 14 , or the voltage-based TOC shown in  FIG. 15  is not possible for the output voltage to return to the stable state value with the situation of the TOC being triggered repeatedly. Nevertheless, the result of the voltage-slew-rate-based TOC shown in  FIG. 16  reaches the good stable effect for the output voltage without the situation of the TOC being triggered repeatedly. 
     While the invention has been described with referencing to the preferred embodiment thereof, it is to be understood that modifications or variations may be easily made without departing from the spirit of this invention which is defined by the appended claims.