Abstract:
A relay system includes a first relay apparatus connected to a node through a first line and a second relay apparatus connected to the node through a second line. The first line and the second line belong to the same link aggregation group. The first relay apparatus includes a first control unit. The first control unit notifies, before relaying a received frame, the second relay apparatus of a source address included in the received frame in the absence of first relation information related to the source address in the first storage unit upon receiving the received frame via a port connected to the first line. The second relay apparatus includes a second control unit. The second control unit stores, in the second storage unit, second relation information regarding a relationship between the source address notified by the first relay apparatus and an output port connected to the second line.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-200254, filed on Sep. 7, 2010, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a relay system. 
       BACKGROUND 
       [0003]      FIGS. 1A and 1B  illustrate an exemplary structure of a network including switch stacking. The switch stacking is a technology to connect multiple switches (layer  2  switches) by stack connection to represent the multiple switches as one switch. The switch stacking may also be referred to as switch virtualization.  FIG. 1A  illustrates an exemplary physical structure of the network. Referring to  FIG. 1A , four switches SW-A to SW-D are connected by stack connection through stack links L 1  to L 4 .  FIG. 1B  illustrates an exemplary logical structure of the network illustrated in  FIG. 1A . Referring to  FIG. 1B , multiple switches connected by stack connection are logically represented as one switch V. In this case, a user may manage the four switches SW-A to SW-D integrally (as one switch V). 
         [0004]    On the other hand, a technology called link aggregation is in use, in which multiple physical links (lines) are grouped to be logically handled as one link. Use of the link aggregation allows the communication bandwidth to be improved and robustness due to redundancy to be ensured. The group of the physical links logically handled as one link is called a link aggregation group (LAG). 
         [0005]    When the switch stacking is applied to multiple switches, the multiple switches are logically handled as one switch. Accordingly, links belonging to the same link aggregation group may be set across multiple switches. 
         [0006]      FIG. 2  illustrates an example of link aggregation employed for switches to which the switch stacking is applied. 
         [0007]    Referring to  FIG. 2 , the switch SW-B and the switch SW-C, among the four switches SW-A to SW-D to which the switch stacking is applied, are connected to a node A through different physical links. When the link aggregation is employed for the two links in this example, the node A and one logical switch (a switch stack) including the switches SW-A to SW-D are logically handled as if the node A were connected to the switch stack through one link (link aggregation group G). 
         [0008]    However, as apparent from  FIG. 2 , connecting multiple switches to the same link aggregation group G physically forms a network loop. Accordingly, a frame storm may occur in the absence of appropriate handling. 
         [0009]    Conventional methods of handling the network loop include a control method using spanning tree protocol (STP) and a control method using frames including a time to live (TTL) value. 
         [0010]      FIG. 3  illustrates an exemplary control method using the STP. In the STP, the control is performed so that the network loop is not formed by appropriately blocking a redundant path. Referring to  FIG. 3 , a port connected to the stack link L 4  is blocked in each of the switch SW-A and the switch SW-D. 
         [0011]      FIG. 4  illustrates an exemplary control method using frames including a TTL value. In this method, a TTL value is included in each frame and the TTL value is decremented each time the frame passes through one switch. When the TTL value decreases to zero, the frame is discarded. As a result, the frame is prevented from being infinitely circulated over the network and the loop is substantially eliminated. In the example in  FIG. 4 , a frame F 1  including a TTL value of one is transmitted in a direction from the switch SW-D to the switch SW-A and a frame F 2  including a TTL value of two is transmitted in a direction from the switch SW-D to the switch SW-C. The frame F 1  is not transferred to the stack link subsequent to the switch SW-A, and the frame F 2  is not transferred to the stack link subsequent to the switch SW-B. 
         [0012]    Japanese Laid-open Patent Publication No. 2008-236212 discloses a related technique. 
       SUMMARY 
       [0013]    According to an aspect of the present invention, provided is a relay system including a first relay apparatus connected to a node through a first line and a second relay apparatus connected to the node through a second line. The first line and the second line belong to the same link aggregation group. 
         [0014]    The first relay apparatus includes a first storage unit and a first control unit. The first storage unit stores first relation information regarding a relationship between a destination address and an output port of the first relay apparatus. The first control unit notifies, before relaying a received frame, the second relay apparatus of a source address included in the received frame in the absence of first relation information related to the source address in the first storage unit upon receiving the received frame via a port connected to the first line. 
         [0015]    The second relay apparatus includes a second storage unit and a second control unit. The second storage unit stores second relation information regarding a relationship between a destination address and an output port of the second relay apparatus. The second control unit stores, in the second storage unit, second relation information regarding a relationship between the source address notified by the first relay apparatus and an output port connected to the second line. 
         [0016]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general discussion and the following detailed discussion are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0017]      FIGS. 1A and 1B  are diagrams illustrating an exemplary structure of a network including switch stacking; 
           [0018]      FIG. 2  is a diagram illustrating an example of link aggregation employed for switches to which switch stacking is applied; 
           [0019]      FIG. 3  is a diagram illustrating an exemplary control method using STP; 
           [0020]      FIG. 4  is a diagram illustrating an exemplary control method using frames including a TTL; 
           [0021]      FIG. 5  is a diagram illustrating a problem occurring when link aggregation is employed for a switch stack using TTL values; 
           [0022]      FIG. 6  is a diagram illustrating an exemplary configuration of a network according to an embodiment of the present invention; 
           [0023]      FIG. 7  is a diagram illustrating an exemplary configuration of a switch according to an embodiment of the present invention; 
           [0024]      FIG. 8  is a diagram illustrating an example of control performed by a filtering unit according to an embodiment of the present invention; 
           [0025]      FIG. 9  is a diagram illustrating an example of control performed by a filtering unit according to an embodiment of the present invention; 
           [0026]      FIG. 10  is a diagram illustrating an example of control performed by a learning control unit according to an embodiment of the present invention; 
           [0027]      FIG. 11  is a diagram illustrating an example of control performed by a learning control unit according to an embodiment of the present invention; 
           [0028]      FIG. 12  is a diagram illustrating an exemplary operation flow of a switch according to an embodiment of the present invention; 
           [0029]      FIG. 13  is a diagram illustrating an exemplary operation flow of a switch according to an embodiment of the present invention; 
           [0030]      FIG. 14  is a diagram illustrating an exemplary operation flow of a switch according to an embodiment of the present invention; and 
           [0031]      FIG. 15  is a diagram illustrating an exemplary operation flow of a switch according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0032]    However, it is difficult to effectively introduce the STP or the TTL values to the link aggregation. 
         [0033]    Since the redundant path is blocked in the STP, either of the links belonging to the same link aggregation group G is blocked in the example in  FIG. 2 . This makes difficult to effectively use the link aggregation group G. 
         [0034]    When TTL values are introduced, identical multiple frames may possibly reach the same node within a range in which the TTL values are valid, as illustrated in  FIG. 5 . 
         [0035]      FIG. 5  illustrates a problem occurring when the link aggregation is employed for a switch stack using TTL values. An example is illustrated in  FIG. 5 , in which a frame F is input into the switch SW-B. In flooding of the frame F, the switch SW-B outputs the frame F including a TTL value of one to the switch SW-A and outputs the frame F including a TTL value of two to the switch SW-C. In this case, the frame F flooded by the switch SW-B and the frame F flooded by the switch SW-C redundantly reach the node A. 
         [0036]    Accordingly, it is preferable to provide a relay system, a relay apparatus, and a relay method capable of improving the usefulness of the link aggregation connecting one node to multiple switches. 
         [0037]    The embodiments may improve the usefulness of link aggregation connecting one node to multiple switches. 
         [0038]    Embodiments of the present invention will herein be discussed with reference to the attached drawings.  FIG. 6  illustrates an exemplary configuration of a network according to an embodiment of the present invention. 
         [0039]    Referring to  FIG. 6 , a switch stack  1  includes switches SW 1 , SW 2 , and SW 3  (hereinafter referred to as a switch SW when the switches are not discriminated from each other) and is logically handled as one switch. The switch stack  1  is an example of a relay system. 
         [0040]    Each switch SW is a layer  2  switch (or also called a switching hub) and is an example of a relay apparatus relaying frames. Each switch SW is connected by stack connection to the adjacent switches in the example in  FIG. 6 . A line connecting the switches is hereinafter referred to as a stack link. Stack links L 1  to L 3  are illustrated in  FIG. 6 . The stack link L 3  is a redundant path to improve the failure tolerance of the network. As a result, a loop is formed for the switches SW 1  to SW 3 . 
         [0041]    An external node A is a network device (for example, a router) connected to the switches SW 1  and SW 2 . An external node B is a network device connected to the switches SW 2  and SW 3 . In other words, each of the external nodes A and B is connected to the switch stack  1  through two lines. However, the respective two lines are logically handled as one line by using the link aggregation. Specifically, two lines belonging to a link aggregation group Ga are logically handled as one line. Similarly, two lines belonging to a link aggregation group Gb are logically handled as one line. Accordingly, the external nodes A and B and the switch stack  1  are logically handled as if each of the external nodes A and B were connected to the switch stack  1  through one line. 
         [0042]    One or more terminals T, such as a personal computer (PC), are connected to each switch SW. For example, terminals T 1  and T 2  are connected to the switch SW 1 . The terminal T 2  is also connected to the switch SW 2 . The line connecting between the terminal T 2  and the switch SW 1  and the line connecting between the terminal T 2  and the switch SW 2  constitute one link aggregation group Gt and are logically handled as one line. 
         [0043]    Each link aggregation group is logically handled as one line according to the above discussion. However, in the present embodiment, the lines belonging to each link aggregation group are physically connected to different (separate) switches SW. Specifically, a link La 1 , which is one line belonging to the link aggregation group Ga, connects the external node A to the switch SW 1 . A link La 2 , which is the other line belonging to the link aggregation group Ga, connects the external node A to the switch SW 2 . As a result, a loop is physically formed between the external node A, the switch SW 1 , and the SW 2 . Loops are similarly formed for the link aggregation group Gb and the link aggregation group Gt. 
         [0044]      FIG. 7  illustrates an exemplary configuration of a switch according to an embodiment of the present invention. In the present embodiment, each switch SW includes a learning control unit  11 , a relay unit  12 , a relay database (DB)  13 , ports P, and so on. 
         [0045]    The learning control unit  11  is a circuit that learns the correspondence between the port P and the corresponding node on the basis of a frame that is received. Specifically, the learning control unit  11  records information indicating the correspondence between a source media access control (MAC) address of the received frame and the reception port (or an output port) in the relay DB  13 . Such information is hereinafter referred to as correspondence information. The relay DB  13  is an example of correspondence information storing means that uses a memory of the switch SW to record the correspondence information between the port P and the node (MAC address thereof). 
         [0046]    The learning control unit  11  also controls a frame that is received through a line belonging to a link aggregation group so as not to return (reflux) to the source node of the frame. For example, the learning control unit  11  controls a frame that is transmitted from the external node A through the link La 1  and that is received by the switch SW 1  so as not to be transferred from the switch SW 2  to the external node A through the link La 2 . 
         [0047]    The relay unit  12  is a circuit that relays frames, which is a basic function of the switch SW, and so on. Specifically, when the correspondence information between a destination MAC address of a received frame and a corresponding port thereto is registered in the relay DB  13 , the relay unit  12  transmits the received frame via the corresponding port. When the correspondence information between the destination MAC address of the received frame and the corresponding port thereto is not registered in the relay DB  13 , the relay unit  12  performs flooding. The flooding means that the received frame is transmitted via all the ports other than the reception port because the port to which the destination node is connected is not known when the destination of the received frame is not registered in the relay DB  13 . 
         [0048]    The functions of learning control unit  11  and the relay unit  12  may be achieved by a central processing unit (CPU)  16  of the switch SW by executing programs stored in a storage unit  17 . The relay DB  13  may be stored in the storage unit  17 . 
         [0049]    The port P is an interface to which a line is connected. Each port P includes, for example, a flooding inhibition unit  14  and a filtering unit  15 . 
         [0050]    The flooding inhibition unit  14  manages (holds) information indicating whether the corresponding port P is in a flooding inhibited state. For example, the flooding inhibition unit  14  uses a storage area corresponding to one bit in a memory in the port P. It is indicated that the port P is in the flooding inhibited state when the flooding inhibition unit  14  (the corresponding bit) has a value of ON (1), and it is indicated that the port P is not in the flooding inhibited state when the flooding inhibition unit  14  (the corresponding bit) has a value of OFF (0). The frame to be transmitted via the port P (hereinafter referred to as a flooding inhibited port) in the flooding inhibited state is limited to a frame whose destination is a MAC address corresponding to the flooding inhibited port P. In other words, no frame is transmitted via the flooding inhibited port in the flooding. Setting a port P connected to a redundant path to the flooding inhibited state prevents an occurrence of the frame storm caused by the switch stack  1  having the redundant path. The redundant path is the stack link L 3  in the present embodiment. Accordingly, as illustrated in  FIG. 8 , a port P 11  of the switch SW 1  and a port P 32  of the switch SW 3 , connected to the stack link L 3 , are in the flooding inhibited state. 
         [0051]    The filtering unit  15  is a circuit that controls identical multiple frames so as not to redundantly reach the same external node connected to the switch stack  1  through a link aggregation group. For example, the filtering unit  15  controls a frame destined for the external node A, received by the switch SW 1 , so as not to reach the external node A through the two lines: the link La 1  and the link La 1 . 
         [0052]    The filtering unit  15  will now be discussed in detail. The filtering units  15  are valid in ports P connected to lines belonging to a link aggregation group, and invalid in the remaining ports P. “Invalid” means a state equivalent to the state in which the corresponding port P has no filtering unit  15 . Ports P connected to lines belonging to a link aggregation group are hereinafter referred to as ports P constituting a link aggregation group. 
         [0053]    A condition (hereinafter referred to as a passage condition) to permit transmission of a frame in broadcasting is set in the filtering unit  15  in each of ports P constituting the same link aggregation group. The broadcasting means transmission of a frame via the ports P other than the reception port and includes the flooding in the present embodiment. The passage condition is set so that one port P is alternatively selected from multiple ports P constituting the same link aggregation group. In other words, the passage condition is set so that two or more ports P are not selected and only one port P is selected without exception. 
         [0054]      FIG. 8  illustrates a first example of the control performed by the filtering unit  15 . Referring to  FIG. 8 , ports P connected to lines belonging to a link aggregation group are denoted by black circles () or white circles (◯). 
         [0055]    The passage condition of the filtering unit  15  in the port P denoted by the black circle is that a final bit (SA[ 0 ]) of the source MAC address (SA) of the received frame has a value of zero (0). When this passage condition is denoted by f 1 , the passage condition f 1  is represented as follows. 
         [0000]      f1: SA[0]=0 
         [0056]    The passage condition f 1  is set for a port P 13 , a port P 16 , and a port P 34  in the example in  FIG. 8 . 
         [0057]    The passage condition of the filtering unit  15  in the port P denoted by the white circle is that the final bit (SA[ 0 ]) of the source MAC address (SA) of the received frame has a value of one (1). When this passage condition is denoted by f 2 , the passage condition f 2  is represented as follows. 
         [0000]      f2: SA[0]=1 
         [0058]    The passage condition f 2  is set for a port P 23 , a port P 24 , and a port P 25  in the example in  FIG. 8 . 
         [0059]    How the passage condition is set will now be discussed for each link aggregation group. As for the ports P constituting the link aggregation group Ga, the passage condition f 1  is set for the port P 13  and the passage condition f 2  is set for the port P 23 . As for the ports P constituting the link aggregation group Gb, the passage condition f 2  is set for the port P 24  and the passage condition f 1  is set for the port P 34 . As for the ports P constituting the link aggregation group Gt, the passage condition f 1  is set for the port P 16  and the passage condition f 2  is set for the port P 25 . As discussed above, the passage conditions of the respective ports P connected to the lines belonging to the same link aggregation group are exclusively or alternatively set. 
         [0060]    A relay path of a frame Ft 1  that is transmitted from the terminal T 1  and received at the port P 15  in the switch SW 1  is illustrated in the example in  FIG. 8 . It is assumed that the value of SA[ 0 ] of the frame Ft 1  is zero (0). It is also assumed that each switch SW has not learned the destination MAC address of the frame Ft 1 . 
         [0061]    Since the switch SW 1  receiving the frame Ft 1  has not learned the destination MAC address of the frame Ft 1 , the switch SW 1  attempts to flood the frame Ft 1 . However, the port P 11  is excluded from the transmission ports of the frame Ft 1  because the port P 11  is in the flooding inhibited state. As a result, the frame Ft 1  is transmitted via the ports P 13 , P 12 , and P 16 . The passage condition f 1  is set for the ports P 13  and P 16 . Since the value of SA[ 0 ] of the frame Ft 1  is zero (0), the passage condition f 1  is satisfied. Consequently, the filtering unit  15  does not exclude the port P 13  from the transmission ports. 
         [0062]    The switch SW 2  receives at the port P 21  the frame Ft 1  transmitted via the port P 12 . Since the switch SW 2  has not learned the destination MAC address of the frame Ft 1 , the switch SW 2  attempts to flood the frame Ft 1 . However, the passage condition f 2  is set for the ports P 23 , P 24 , and P 25 . Since the value of SA[ 0 ] of the frame Ft 1  is zero (0), the passage condition f 2  is not satisfied. Consequently, the filtering unit  15  in each of the ports P 23 , P 24 , and P 25  inhibits the transmission of the frame Ft 1 . As a result, the frame Ft 1  is transmitted via the ports P 22  and P 26 . 
         [0063]    The switch SW 3  receives at the port P 31  the frame Ft 1  transmitted via the port P 22 . Since the switch SW 3  has not learned the destination MAC address of the frame Ft 1 , the switch SW 3  attempts to flood the frame Ft 1 . However, the port P 32  is excluded from the transmission ports of the frame Ft 1  because the port P 32  is in the flooding inhibited state. As a result, the frame Ft 1  is transmitted via the ports P 34 , P 35 , and P 36 . The passage condition f 1  is set for the port P 34 . Since the value of SA[ 0 ] of the frame Ft 1  is zero (0), the passage condition f 1  is satisfied. Consequently, the filtering unit  15  does not exclude the port P 34  from the transmission ports. 
         [0064]      FIG. 9  illustrates a second example of the control performed by the filtering unit  15 . A relay path of a frame Ft 2  that is transmitted from the terminal T 2  and received at the port P 16  in the switch SW 1  is illustrated in the example in  FIG. 9 . It is assumed that the value of SA[ 0 ] of the frame Ft 2  is one (1). It is also assumed that each switch SW has not learned the destination MAC address of the frame Ft 2 . 
         [0065]    Since the switch SW 1  receiving the frame Ft 2  has not learned the destination MAC address of the frame Ft 2 , the switch SW 1  attempts to flood the frame Ft 2 . However, the port P 11  is excluded from the transmission ports of the frame Ft 2  because the port P 11  is in the flooding inhibited state. The passage condition f 1  is set for the port P 13 . Since the value of SA[ 0 ] of the frame Ft 2  is one (1), the passage condition f 1  is not satisfied. Consequently, the filtering unit  15  in the port P 13  inhibits the transmission of the frame Ft 2 . As a result, the frame Ft 2  is transmitted via the ports P 12  and P 15 . 
         [0066]    The switch SW 2  receives at the port P 21  the frame Ft 2  transmitted via the port P 12 . Since the switch SW 2  has not learned the destination MAC address of the frame Ft 2 , the switch SW 2  attempts to flood the frame Ft 2 . However, the passage condition f 2  is set for the ports P 23 , P 24 , and P 25 . Since the value of SA[ 0 ] of the frame Ft 2  is one (1), the passage condition f 2  is satisfied. Consequently, the filtering unit  15  in each of the ports P 23 , P 24 , and P 25  permits the transmission of the frame Ft 2 . As a result, the frame Ft 2  is transmitted via the ports P 22 , P 23 , P 24 , and P 26 . Although the passage condition f 2  is satisfied for the port P 25 , the port P 25  is excluded from the transmission ports of the frame Ft 2  because of the effect (discussed below) of the learning control unit  11 . This exclusion is performed in order to avoid reflux of the frame Ft 2  to the terminal T 2 , which is the source node of the frame Ft 2 . 
         [0067]    The switch SW 3  receives at the port P 31  the frame Ft 2  transmitted via the port P 22 . Since the switch SW 3  has not learned the destination MAC address of the frame Ft 2 , the switch SW 3  attempts to flood the frame Ft 2 . However, the port P 32  is excluded from the transmission ports of the frame Ft 2  because the port P 32  is in the flooding inhibited state. The passage condition f 1  is set for the port P 34 . Since the value of SA[ 0 ] of the frame Ft 2  is one (1), the passage condition f 1  is not satisfied. Consequently, the filtering unit  15  in the port P 34  inhibits the transmission of the frame Ft 2 . As a result, the frame Ft 2  is transmitted via the ports P 35  and P 36 . 
         [0068]    As illustrated in  FIG. 8  and  FIG. 9 , the control performed by the filtering unit  15  prevents the identical frames from being redundantly transferred to the same node (the external node A, the external node B, or the terminal T 2 ) through the lines belonging to the same link aggregation group. In addition, the use of a value, such as a source MAC address, that may vary depending on the frame as a passage condition prevents the frequency of the usage of each line belonging to the same link aggregation group from being greatly biased. For example, the lines used for the transfer of the frame Ft 1  in  FIG. 8  are different from the lines used for the transfer of the frame Ft 2  in  FIG. 9 . 
         [0069]    The passage condition is not limited to certain values as long as the result of determination is selective. For example, the passage condition may be set by using another bit or multiple bits of the source MAC address. Alternatively, among the information included in the frame to be relayed, information, such as the destination MAC address, other than the source MAC address may be employed. Alternatively, information (for example, time) other than the information that is included in the frame to be relayed may be employed to set the passage condition. When information other than the information that is included in the frame is employed, the employed information preferably dynamically varies. This is because, if the information is fixed, the result of determination of the passage condition is fixed and, thus, the lines that are used are fixed, among the lines belonging to the same link aggregation group. It is preferred that the passage condition be set for the information that may be varied depending on the frame to be relayed, as in the present embodiment, in terms of the randomness of the result of determination of the passage condition. 
         [0070]    The effectiveness of the filtering unit  15  is not limited to the case in which two lines belong the same link aggregation group. When N (N is equal to two or more) lines belong to the same link aggregation group, it is sufficient for the passage condition from which N results of determination may be exclusively acquired to be set for the ports P constituting the same link aggregation group. For example, when three lines belong to the same link aggregation group and the source MAC address is used, as in the present embodiment, the passage condition may be set for a certain value having at least two bits. In this case, zero (0) may be allocated to the two-bit value of a first line, one (1) may be allocated to the two-bit value of a second line, and two (2) and three (3) may be allocated to the two-bit value of a third line. Alternatively, in order to improve the equality of the loads of the three lines, three (3) may be allocated to different lines in accordance with other information (for example, time). Alternatively, by allocating a line number (a value from one (1) to N) to each line, the passage condition may be set for line number corresponding to the remainder after division of a common value (for example, all or part of the bits of the source MAC address). 
         [0071]    Alternatively, cyclic redundancy check (CRC) may be applied to certain information (for example, the source MAC address) and the passage condition may be set for the port number corresponding to the remainder after the CRC. 
         [0072]    The learning control unit  11  will now be discussed in detail.  FIG. 10  illustrates a first example of the control performed by the learning control unit  11 . 
         [0073]    A process performed by the learning control unit  11  when the switch SW 1  receives a frame Fa 1  from the external node A through a line belonging to the link aggregation group Ga is illustrated in the example in  FIG. 10 . It is assumed that each switch SW has not learned the source MAC address of the frame Fa 1 . 
         [0074]    Upon reception of the frame Fa 1  by the switch SW 1 , the learning control unit  11  in the switch SW 1  searches the relay DB  13  for the source MAC address of the frame Fa 1 . If the source MAC address has not been registered in the relay DB  13  (that is, the switch SW 1  has not learned the source MAC address), the learning control unit  11  notifies the switch SW 2  constituting the link aggregation group Ga of the reception, through the link aggregation group Ga, of the frame Fa 1  including an address (hereinafter referred to as an unlearned address) that has not been learned. Specifically, the learning control unit  11  transmits a control frame including the unlearned address and an identifier (hereinafter referred to as an LAG identifier) of the link aggregation group Ga to the switch SW 2 . Such a control frame is hereinafter referred to as a learning instruction frame Fc. 
         [0075]    The learning of the unlearned address is normally performed in the switch SW 1 . Specifically, the correspondence information between the port P 13  and the unlearned address is registered in the relay DB  13  in the switch SW 1 . 
         [0076]    Information indicating which link aggregation group each port P constitutes is included in, for example, topology information stored in each switch SW. Alternatively, the LAG identifier of the link aggregation group to which the port P is connected may be set for each port P constituting the link aggregation group. In either of the cases, each switch SW may determine through which link aggregation group the frame is transmitted on the basis of the reception port P of the frame. 
         [0077]    After transmitting the learning instruction frame Fc, the switch SW 1  relays the frame Fa 1 . 
         [0078]    Upon reception of the learning instruction frame Fc by the switch SW 2 , the learning control unit  11  in the switch SW 2  learns the unlearned address included in the learning instruction frame Fc in association with the port P 23 . Specifically, in the switch SW 2 , the correspondence information between the port P 23  constituting the link aggregation group Ga and the unlearned address is registered in the relay DB  13 . Referring to  FIG. 10 , an asterisk (★) indicates that the unlearned address has been learned. 
         [0079]    When three or more switches SW constitute the link aggregation group Ga, the learning instruction frame Fc is transferred to each switch SW. 
         [0080]    In other words, when a frame whose source MAC address has not been learned is received through a link aggregation group, each switch SW constituting the link aggregation group learns the unlearned address in association with the port P constituting the link aggregation group. 
         [0081]      FIG. 11  illustrates a second example of the control performed by the learning control unit  11 . 
         [0082]    A process performed by the learning control unit  11  when the switch SW 1  receives a frame Fat from the external node A through a line belonging to the link aggregation group Ga is illustrated in the example in FIG.  11 . It is assumed in  FIG. 11  that the control process in  FIG. 10  has been performed and that the source MAC address of the frame Fa 2  is the same as that of the frame Fa 1  in  FIG. 10 . 
         [0083]    Upon reception of the frame Fa 2  by the switch SW 1 , the learning control unit  11  in the switch SW 1  searches the relay DB  13  for the source MAC address of the frame Fa 2 . If the source MAC address has been registered in the relay DB  13 , the learning control unit  11  searches the relay DB  13  for the destination MAC address. If the destination MAC address has not been registered in the relay DB  13 , the switch SW 1  floods the frame Fa 2 . As a result, the frame Fa 2  is transferred to the switch SW 2 . 
         [0084]    Upon reception of the frame Fa 2  by the switch SW 2 , the learning control unit  11  in the switch SW 2  searches the relay DB  13  for the source MAC address of the frame Fa 2 . The source MAC address has been learned in association with the port P 23  in the control process in  FIG. 10 . Accordingly, relearning is normally performed for the source MAC address. Specifically, the source MAC address is learned in association with the port P 21  via which the frame Fa 2  is received. However, in the present embodiment, the learning control unit  11  does not relearn the address that has been learned when the frame is received through a stack link. Whether each port P is connected to a stack link may be determined on the basis of the topology information stored in each switch SW. Alternatively, information indicating whether each port P is connected to a stack link may be set for the port P. 
         [0085]    Referring to  FIG. 11 , the switch SW 2  receives the frame Fa 2  through the stack link. Accordingly, the learning control unit  11  in the switch SW 2  does not relearn the source MAC address of the frame Fa 2 . 
         [0086]    The reason for not updating the learning result (the relay DB  13 ) of a source MAC address of a frame in response to a frame received through the stack link is because a shortest path has already been registered for the source MAC address in response to the learning instruction frame Fc. In other words, this is because, if the learning result concerning the source MAC address is updated in association with the port P connected to the stack link, the relay path for the source MAC address is lengthened. 
         [0087]    Thereafter, the switch SW 2  relays the frame Fa 2 . In the relay process, transmission of the frame Fa 2  via the port P corresponding to the source MAC address of the frame Fa 2  is inhibited by the learning control unit  11 . As a result, the reflux of the frame Fa 2  to the external node A is avoided. Referring to  FIG. 11 , a broken-line arrow indicates that the transmission of the frame Fa 2  via the port P 23  is inhibited. 
         [0088]    An operation flow of each switch SW for performing the process discussed above with reference to  FIGS. 8 to 11  will now be discussed with reference to  FIGS. 12 to 15 . 
         [0089]      FIG. 12  illustrates an exemplary operation flow of a process performed by a switch in response to reception of a frame. The operation flow illustrated in  FIG. 12  is executed by one switch SW that has received a frame. Accordingly, the components (for example, the learning control unit  11 ) mentioned in the discussion with reference to  FIG. 12  are included in the same switch SW. 
         [0090]    In S 101 , in response to reception of a frame, the learning control unit  11  searches the relay DB  13  for the source MAC address of the received frame. 
         [0091]    In S 102 , the learning control unit  11  determines whether the source MAC address of the received frame is already registered in the relay DB  13 . 
         [0092]    In S 103 , when the source MAC address of the received frame is not yet registered in the relay DB  13  (“No” in S 102 ), the learning control unit  11  registers the correspondence information between the source MAC address and the reception port in the relay DB  13 . 
         [0093]    In S 104 , the learning control unit  11  determines whether the reception port P is connected to a stack link. 
         [0094]    In S 105 , when the reception port P is not connected to a stack link (“No” in S 104 ), the learning control unit  11  determines whether the reception port P constitutes a link aggregation group. 
         [0095]    In S 106 , when the reception port P constitutes a link aggregation group (“Yes” in S 105 ), the learning control unit  11  transmits a learning instruction frame to another switch SW having another port P constituting the link aggregation group. The learning instruction frame corresponds to the learning instruction frame Fc in  FIG. 10 . Accordingly, the learning instruction frame includes the LAG identifier of the link aggregation group and the source MAC address of the received frame. S 103  to S 106  correspond to  FIG. 10 . 
         [0096]    In S 107 , the learning control unit  11  waits for reception of a control frame as a response from the destination of the learning instruction frame. 
         [0097]    In S 111 , upon reception of the response, the learning control unit  11  determines that no relay excluded port exists. 
         [0098]    In S 112 , the learning control unit  11  causes the relay unit  12  to perform the relay process. The relay excluded port means a port P excluded from the transmission ports of the received frame. As the basic control of the switch SW, no received frame is transmitted via the reception port P. The relay excluded port is a port P, among the ports other than the reception port P, excluded from the transmission ports of the received frame in order to prevent the reflux of the received frame. 
         [0099]    When the reception port P is connected to a stack link (“Yes” in S 104 ) or when the reception port P does not constitute a link aggregation group (“No” in S 105 ), S 111  and S 112  are performed without performing the transmission of the learning instruction frame, etc. of S 106  and S 107 . 
         [0100]    In S 108 , when the source MAC address of the received frame is already registered in the relay DB  13  (“Yes” in S 102 ), the learning control unit  11  determines whether the reception port P is connected to a stack link. 
         [0101]    In S 109 , when the reception port P is connected to a stack link (“Yes” in S 108 ), the learning control unit  11  sets the port P associated with the source MAC address as a relay excluded port. 
         [0102]    In S 110 , when the reception port P is not connected to a stack link (“No” in S 108 ), the learning control unit  11  relearns the source MAC address. Specifically, the learning control unit  11  updates the relay DB  13  so that the source MAC address is associated with the reception port P. 
         [0103]    In S 111 , the learning control unit  11  determines that no relay excluded port exists. 
         [0104]    In S 112 , the learning control unit  11  causes the relay unit  12  to perform the relay process after S 109  or S 111 . 
         [0105]    S 108  to S 110  correspond to  FIG. 11 . 
         [0106]    An operation flow of a switch SW that has received the learning instruction frame transmitted in S 106  will now be discussed. 
         [0107]      FIG. 13  illustrates an exemplary operation flow of a switch that has received the learning instruction frame. 
         [0108]    In S 201 , the learning control unit  11  in the switch SW that has received the learning instruction frame updates the relay DB  13  on the basis of the learning instruction frame. Specifically, the learning control unit  11  registers in the relay DB  13  the correspondence information between the port P, that constitutes the link aggregation group concerning the LAG identifier, and the source MAC address both included in the learning instruction frame. 
         [0109]    In S 202 , the learning control unit  11  returns a frame as a response to the learning instruction frame. 
         [0110]    S 112  in  FIG. 12  will now be discussed in detail.  FIG. 14  illustrates an exemplary operation flow of the relay process performed by the relay unit  12 . 
         [0111]    In S 301 , the relay unit  12  searches the relay DB  13  for the destination MAC address of the received frame. 
         [0112]    In S 302 , the relay unit  12  determines whether the destination MAC address of the received frame is already registered in the relay DB  13 . 
         [0113]    In S 303 , when the destination MAC address of the received frame is already registered in the relay DB  13  (“Yes” in S 302 ), the relay unit  12  sets the port P registered in association with the destination MAC address as a port P (hereinafter referred to as a destination port) to which the received frame is to be transmitted. 
         [0114]    In S 304 , when the destination MAC address of the received frame is not yet registered in the relay DB  13  (“No” in S 302 ), the relay unit  12  sets all the ports P excluding the reception port P as the destination ports. 
         [0115]    In S 305 , after S 303  or S 304 , the relay unit  12  removes relay excluded ports from the destination ports. 
         [0116]    In S 306 , the relay unit  12  inputs the received frame to each destination port excluding the relay excluded port as a transmission target frame. 
         [0117]    An operation flow of a port P to which the transmission target frame is input will now be discussed. 
         [0118]      FIG. 15  illustrates an exemplary operation flow of the port P to which the transmission target frame is input. 
         [0119]    In S 401 , the flooding inhibition unit  14  in the port P determines whether the port P is in the flooding inhibited state. 
         [0120]    In S 405 , when the port P is in the flooding inhibited state (“Yes” in S 401 ), the filtering unit  15  discards the frame. In this case, no frame is transmitted via the port P. 
         [0121]    In S 402 , when the port P is not in the flooding inhibited state (“No” in S 401 ), the filtering unit  15  determines whether the passage condition is set. In other words, it is determined whether the filtering unit  15  is valid. This determination may be replaced with determination of whether the port P constitutes a link aggregation group. 
         [0122]    In S 403 , when the passage condition is set (“Yes” in S 402 ), the filtering unit  15  determines whether the passage condition is satisfied. 
         [0123]    In S 404 , when the passage condition is satisfied (“Yes” in S 403 ) or when the passage condition is not set (“No” in S 402 ), the frame is transmitted via the port P. 
         [0124]    In S 405 , when the passage condition is not satisfied (“No” in S 403 ), the filtering unit  15  discards the frame. 
         [0125]    As discussed above, according to the present embodiment, even if multiple lines belonging to a link aggregation group are connected to different switches SW, it is possible to appropriately relay a frame. In other words, redundant transfer of identical frames to the same node or reflux of a frame to a source node is avoided. Avoiding reflux of a frame may avoid frame storm caused by a loop of physical lines. Accordingly, it is possible to improve the usefulness of the link aggregation connected from one node to multiple switches. 
         [0126]    The filtering unit  15  may not necessarily be provided in each port P but one filtering unit  15  may be provided in one switch SW. In this case, the filtering unit  15  may determine via which port the frame is transmitted on the basis of the passage condition of each port P stored in the memory in the switch SW. For example, at the beginning of the operation flow illustrated in  FIG. 14 , the determination of the passage condition may be performed by the filtering unit  15  and the port that is not set as a transmission port may be added to the relay excluded ports. 
         [0127]    The passage condition is set for the filtering unit  15  in the present embodiment, however, a filtering condition may be set for the filtering unit  15 . In other words, a condition in which the frame is not transmitted may be set. 
         [0128]    The flooding inhibition unit  14  is applied as a countermeasure against the redundant path in the switch stack  1  in the present embodiment. However, a conventional method, for example, a method using Standard Template Library (STL) or the TTL, may be adopted as means for avoiding the disadvantages of the redundant path. In such a case, the switch SW may not include the flooding inhibition unit  14 . When the switch stack  1  has no redundant path, it is not necessary to prepare the means for avoiding the disadvantages of the redundant path. 
         [0129]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been discussed in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.