Abstract:
Various embodiments of switch mode power supplies, circuits, and methods of control are described herein. In one embodiment, a method of operating a switch mode power supply having a switching circuit coupled to an inductor includes modulating a duty cycle of the switching circuit to charge the inductor using pulse width modulation, supplying an output voltage from the inductor to the load, performing a comparison between the output voltage and a reference voltage, and deriving an error signal based on the comparison between the output voltage and the reference voltage. The method also includes generating a clock signal for the pulse width modulation based on the received error signal.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure is related generally to switching converters with adaptive clock signal generators and associated methods of control. 
       BACKGROUND 
       [0002]    Constant-frequency pulse-width-modulation (“PWM”) switching regulators are often used as point-of-load (“POL”) regulators to power processors, input/output logic chips, memories, and/or other digital electronic components. Constant-frequency PWM switching regulators have higher power conversion efficiencies and increased design flexibilities when compared to other types of regulators. For example, multiple output voltages of different polarities may be generated with such switching regulators based on a single input voltage. 
         [0003]    Most constant-frequency PWM switching regulators perform satisfactorily at a steady state. However, power management of digital electronic components has become more comprehensive with ever decreasing control thresholds. As a result, transient performance requirements on the POL regulators have become more stringent. Conventional control topologies for addressing transient performance of POL regulators are typically based on variable frequency or pseudo-constant frequency techniques, which may be incompatible with fixed-frequency components and/or systems. Accordingly, several improvements to POL regulators for improving transient performance while maintaining fixed frequency operation at a steady state may be desirable. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a schematic circuit diagram of a PWM switching regulator in accordance with embodiments of the present technology. 
           [0005]      FIG. 2  is a voltage versus time plot illustrating an error signal and a clock signal during a transient condition in accordance with embodiments of the present technology. 
           [0006]      FIGS. 3-5  are schematic circuit diagrams of an oscillator suitable for use in the PWM switching regulator of  FIG. 1  in accordance with embodiments of the present technology. 
           [0007]      FIG. 6  is a schematic circuit diagram of a multi-phase PWM switching regulator in accordance with embodiments of the present technology. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    Various embodiments of switch mode power supplies, circuits, and methods of control are described below. Many of the details, dimensions, angles, shapes, and other features shown in the figures are merely illustrative of particular embodiments of the technology. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to  FIGS. 1-6 . 
         [0009]      FIG. 1  is a schematic circuit diagram of a PWM switching regulator  100  in accordance with embodiments of the present technology. In the following discussion, the PWM switching regulator  100  is described as a current-mode PWM buck converter. However, in other embodiments, the switching regulator  100  can also be a voltage-mode and/or other suitable types of PWM switching regulator. In further embodiments, the PWM switching regulator  100  can also be configured as a boost converter, a buck-boost converter, and/or can have other suitable configurations. 
         [0010]    In the illustrated embodiment in  FIG. 1 , the PWM switching regulator  100  includes a switching circuit  102 , a PWM controller  104 , an oscillator  118 , a voltage feedback circuit  120 , a current comparator  116 , an inductor  106 , a capacitor  108 , and a load  110  (e.g., a CPU) operatively coupled together. For example, the capacitor  108  and the load  110  are coupled in parallel between an output voltage (V o ) of the inductor  106  and the ground. Even though only the foregoing particular components are shown in  FIG. 1 , in other embodiments, the PWM switching regulator  100  can also include additional and/or different components. 
         [0011]    As shown in  FIG. 1 , the switching circuit  102  includes a first switch  112   a  (commonly referred to as the high-side switch) and a second switch  112   b  (commonly referred to as the low-side switch) coupled in series between an input voltage (V in ) and the ground. The first switch  112   a  has a source coupled to the input voltage (V in ) and a drain coupled to both the second switch  112   b  and the inductor  106 . The second switch  112   b  includes a source coupled to the drain of the first switch  112   a  and a drain coupled to the ground. The first and second switches  112   a  and  112   b  each include a gate coupled to a first output  105   a  and a second output  105   b  of the PWM controller  104 , respectively. The first and second switches  112   a  and  112   b  can individually include a metal oxide field-effect transistor (“MOSFET”), a junction gate field-effect transistor (“JFET”), and/or other suitable types of transistor. 
         [0012]    The PWM controller  104  is configured to controllably turn on/off the first and second outputs  105   a  and  105   b  to control a duty cycle of the first and second switches  112   a  and  112   b  based on the output voltage (V o ) of feedback of the inductor  106  and a switch current (I sw ) through the first and second switches  112   a  and  112   b . As shown in  FIG. 1 , the PWM controller  104  includes a first input  104   a  and a second input  104   b . The first input  104   a  is coupled to the current comparator  116  to receive a control input. The second input  104   b  is coupled to an oscillator output  119  from the oscillator  118  to receive a clock signal (generally designated as “CLK”). 
         [0013]    The voltage feedback circuit  120  is configured to generate an error signal (generally designated as “COMP”) corresponding to a difference between the output voltage (V o ) of the inductor  106  and a reference voltage (V ref ). The voltage feedback circuit  120  is also configured to provide the error signal COMP to both the oscillator  118  and to the current comparator  116 . In the illustrated embodiment, the voltage feedback circuit  120  includes a voltage comparator  114  with a first terminal  114   a  coupled to the reference voltage (V ref ) and a second terminal  114   b , a current limiting resistor  121  coupled between the output voltage (V o ) and the second terminal  114   b , a feedback capacitor  124  and a feedback resistor  122  coupled in series between an output terminal  114   c  and the second terminal  114   b  of the voltage comparator  114 . In other embodiments, certain components of the voltage feedback circuit  120  (e.g., the feedback capacitor  124 ) may be omitted. In further embodiments, the voltage feedback circuit  120  may include additional and/or different components. 
         [0014]    The current comparator  116  is configured to compare the sensed switch current (I sw ) to the generated error signal COMP from the voltage feedback circuit  120  to generate a control signal (generally designated as “PW”). The current comparator  116  then provides the control signal PW to the PWM controller  104 . In the illustrated embodiment of  FIG. 1 , the current comparator  116  includes a first terminal  116   a  coupled to the sensed switch current (I sw ) and a second terminal  116   b  coupled to the output terminal  114   c  of the voltage comparator to receive the error signal COMP. In other embodiments, the current comparator  116  may also include feedback resistors, capacitors, and/or other suitable components. 
         [0015]    The oscillator  118  is configured to generate the clock signal CLK and provide the generated clock signal CLK to the PWM controller  104 . In the illustrated embodiment, the oscillator  118  includes an oscillator input  117  coupled to the output terminal  114   c  of the voltage comparator  114  and an oscillator output  119  coupled to the second input  104   b  of the PWM controller  104 . In other embodiments, the oscillator  118  may also be coupled to the sensed switch current (I sw ), other suitable components of the PWM regulator  100 , and/or a combination thereof. Several embodiments of the oscillator  118  are described in more detail below with reference to  FIGS. 3-5 . 
         [0016]    In operation, the PWM controller  104  alternately turning on the first and second switches  112   a  and  112   b  based on the clock signal CLK and the control signal PW. For example, at a rising edge of a pulse of the clock signal CLK, the PWM controller  104  turns on the first switch  112   a  to charge the inductor  106  and the capacitor  108  for a first period of time corresponding to the control signal PW. During the first period of time, the second switch  112   b  is turned off. After the first time period, the PWM controller  104  turns off the first switch  112   a  and turns on the second switch  112   b  to allow a current to freewheel around the inductor  106 , the capacitor  108 , and the second switching transistor  112   b  for a second period of time. The foregoing alternating operation is repeated to supply a target voltage level to the load  110 . 
         [0017]    Unlike conventional PWM devices in which the clock signal CLK has a fixed frequency at all times, embodiments of the PWM switching regulator  100  can include an oscillator  118  that is configured to generate a modulated clock signal CLK that is generally constant at a steady state but has a variable frequency during a transient state. As used hereinafter, the phrase “steady state” generally refers to a situation in which all variables of a system are generally constant with respect to time. The phrase “transient state” generally refers to a situation in which a variable of the system has been changed, and the system has not reached a steady state. 
         [0018]    The modulated clock signal CLK with the varied frequency can facilitate a more rapid response to the transient condition, and thus improving transient performance of the PWM switching regulator  100 . For example,  FIG. 2  is a voltage versus time plot illustrating the error signal COMP and the clock signal CLK during a transient condition in accordance with embodiments of the present technology. As shown in  FIG. 2 , during a first stead state (generally designated as “Period  1 ”), the error signal COMP is generally constant with a first steady state value (COMP 1 ). As a result, the oscillator  118  ( FIG. 1 ) generates a clock signal CLK with a generally fixed frequency corresponding to the generally constant error signal COMP. 
         [0019]    At time t 1 , a load increase occurs at the load  110  ( FIG. 1 ) indicating a transient condition (generally designated as “Period  2 ”). As a result, the output voltage (V o ) of the inductor  106  ( FIG. 1 ) decreases with time because of the increased demand from the load  110 . As a result, the generated error signal COMP from the voltage feedback circuit  120  ( FIG. 1 ) increases from the first steady state value COMP 1  and increases with time. In response to the increasing error signal COMP, the oscillator  118  generates a clock signal CLK with a higher frequency (as illustrated with the shorter periods in  FIG. 2 ) while the current comparator  116  ( FIG. 1 ) generates a control signal PW higher than those in the first steady state. 
         [0020]    Based on the higher frequency clock signal and the control signal PW, the PWM controller  104  ( FIG. 1 ) turns on the first switch  112   a  to charge the inductor  106  and the capacitor  108  with longer pulse widths and at higher frequencies than in steady state Period  1 . The PWM controller  104  can also turns on the second switch  112   b  with shorter pulses and at higher frequencies. As a result, the output voltage (V o ) of the inductor  106  increases, and the error signal COMP decreases over time until a second steady state (generally designated as “Period  3 ”) is reached at time t 2 . Because both the control signal PW and the clock signal CLK frequency increase over time, the output voltage (V o ) and the error signal COMP can reach the second steady state faster than in conventional devices, and thus improving transient performance of the PWM switching regulator  100 . As shown in  FIG. 2 , the error signal COMP actually overshoot its second steady state value COMP 2 . 
         [0021]    Even though the oscillator  118  is discussed above as modulating the frequency of the clock signal CLK based on the error signal COMP from the voltage feedback circuit  120 , in other embodiments, the oscillator  118  can also modulate the frequency of the clock signal CLK based on the sensed switch current (I sw ), other suitable operational parameters of the PWM regulator  100 , and/or a combination thereof. In further embodiments, the oscillator  118  may be omitted. Instead, a leading edge of a data signal from the PWM controller  104  may be used as the clock signal, and the error signal COMP may be provided directly to the PWM controller  104  to modulate the lead edge of the data signal. 
         [0022]      FIGS. 3-5  are schematic circuit diagrams of an oscillator  118  suitable for use in the PWM switching regulator of  FIG. 1  in accordance with embodiments of the present technology.  FIGS. 3 and 4  are directed to techniques of modulating the instantaneous period of the clock signal CLK by adjusting a charge/discharge voltage applied to an oscillation capacitor.  FIG. 5  is directed to techniques of modulating the instantaneous period of the clock signal CLK by adjusting an oscillation current source for discharging the oscillation capacitor. Even though only particular embodiments of the oscillator  118  are illustrated with reference to  FIGS. 3-5 , one of ordinary skill in the relevant art will recognize that the oscillator  118  may have additional and/or different implementations based upon the following discussions. 
         [0023]      FIG. 3  shows a first implementation, in which the oscillator  118  can include a charging switch  132 , an oscillation capacitor  134 , an oscillation current source  136 , an oscillator comparator  138 , an one-shot circuit  140 , a divider resistor  142 , and a resistor current source  144  operatively coupled to one another. The charging switch  132  has a source  132   a , a drain  132   b , and a gate  132   c . The source  132   a  of the charging switch  132  is coupled to the error signal COMP at the oscillator input  117 . The drain  132   b  of the charging switch  132  is coupled to (1) the oscillation capacitor  134 , (2) the oscillation current source  136 , and (3) a first input  138   a  of the oscillator comparator  138  at a junction node A. The gate  132   c  of the charging switch  132  is coupled to an output of the one-shot circuit  140 . The charging switch  132  can include a MOSFET, a JFET, and/or other suitable types of solid state switch. 
         [0024]    The divider resistor  142  is coupled in series with the resistor current source  144  between the error signal COMP and ground. As a result, a comparison signal that equals to a voltage at node B (V B ) of the oscillator  118  can be represented as follows: 
         [0000]    
       
      
       V 
       B 
       =V 
       comp 
       −iR  
      
     
         [0000]    where V cop  is a voltage at the oscillator input  117 , R is a resistance of the divider resistor  142 , and i is a current of the resistor current source  144 . 
         [0025]    The oscillation capacitor  134  and the oscillation current source  136  are in parallel to each other and coupled between the drain  132   b  of the charging switch  132  and ground. The oscillator comparator  138  has the first input  138   a  coupled to the drain  132   b  of the charging switch  132  at node A and a second input  138   b  coupled to the divider resistor  142  at node B. As a result, the oscillator comparator  138  compares the voltages at node A and node B (V A  and V B , respectively) and provide an comparison result at a comparator output  138   c  to the one-shot circuit  140 . In the illustrated embodiment, the first input  138   a  is a positive terminal, and the second input  138   b  is a negative terminal. In other embodiments, the first and second inputs  138   a  and  138   b  can have other suitable configurations. 
         [0026]    In operation, an instantaneous frequency (or period) of the clock signal CLK at the oscillator output  119  relates to a discharging rate of the oscillation capacitor  134 , and a value of the voltage at node B (V B ). Initially, the charging switch  132  is open or off. The oscillation current source  136  discharges the oscillation capacitor  134  until the oscillation capacitor  134  has a voltage (V capacitor ) equal to the voltage at node B (V B ). Once the voltage (V capacitor ) on the oscillation capacitor  134  is pulled below the voltage at node B (V B ), the oscillator comparator  138  causes the one-shot circuit  140  to provide a pulse that serves as a clock tick for the clock signal CLK. The pulse from the one-shot circuit  140  also turns on or close the charging switch  132  to charge the oscillation capacitor  134  to the error signal voltage (V COMP ), and the foregoing process repeats to generate a periodic clock signal CLK. 
         [0027]    As shown above, the voltage at node B (V B ) depends on the voltage of the error signal (V COMP ). As a result, a sudden increase in the error signal voltage (V COMP ) also increases the voltage at node B (V B ). Thus, a shorter amount of time is required to pull the capacitor voltage (V capacitor ) below the voltage at node B (V B ) and to cause the oscillator comparator  138  to trip the one-shot circuit  140 . Accordingly, the instantaneous period of the clock signal CLK can be shortened to facilitate improving transient performance of the PWM switching regulator  100  ( FIG. 1 ). 
         [0028]    Even though the oscillation capacitor  134  is charged with the error signal voltage (V COMP ) when the charging switch  132  is closed in  FIG. 3 , in other embodiments, the oscillation capacitor  134  may be charged with other suitable voltage sources (not shown). For example, in one embodiment, the oscillation capacitor  134  may be charged with a constant reference voltage (not shown). As discussed above, an increase in the error signal voltage (V COMP ) also increases the voltage at node B (V B ). A shorter amount of time is required to pull the capacitor voltage (V capacitor ) from the constant reference voltage below the voltage at node B (V B ). Thus, the instantaneous period of the clock signal CLK can be shortened. 
         [0029]      FIG. 4  shows a second implementation, in which the voltage at node B (V B ) is higher than the error signal voltage (V COMP ). As shown in  FIG. 4 , the resistor current source  144  and the divider resistor  142  is coupled between a supply voltage (V s ) and the error signal voltage (T COMP ). As a result, the voltage at node B (V B ) can be determined as follows: 
         [0000]    
       
      
       V 
       B 
       =V 
       COMP 
       +iR  
      
     
         [0000]    The oscillation current source  136  is coupled to (1) the oscillation capacitor  134 , (2) the source  132   a  of the charging switch  132 , and (3) the second input  138   b  at junction node A. The drain  132   b  of the charging switch  132  is coupled to the error signal voltage (V COMP ). The oscillator  118  shown in  FIG. 4  operates generally similarly as that shown in  FIG. 3 . As a result, operation of the oscillator  118  in  FIG. 4  is omitted for clarity. 
         [0030]      FIG. 5  shows a further implementation of the oscillator  118 , in which the instantaneous period of the clock signal CLK is modulated by adjusting the oscillation current source  136 . Unlike the embodiment of the oscillator  118  shown in  FIG. 4 , the second terminal  138   b  of the oscillation comparator  138  in  FIG. 5  is coupled to a generally constant oscillation reference voltage. 
         [0031]    As shown in  FIG. 5 , the oscillator  118  also includes a current setting circuit  146  having a current switch  150  and a current comparator  152 . The current switch  150  has a source  150   a  coupled to the resistor current source  144  and a drain  150   b  coupled to the divider resistor  142 . The current comparator  152  includes a first input  152   a  coupled to the error signal voltage (V COMP ), a second input  152   b  coupled to the divider resistor  142 , and a gate  152   c  coupled to the gate  150   c  of the current switch  150 . In operation, the current switch  150  is turned on when the voltage across the divider resistor  142  is equal to the error signal voltage (V COMP ). As a result, the error signal voltage (V COMP ) sets a current level through the divider resistor  142 . 
         [0032]    The current level set by the error signal voltage (V COMP ) can then be mirrored to the oscillator current source  136  via, for example, a current mirror  147  (shown schematically) and/or other suitable components. Thus, when the error signal voltage (V COMP ) increases, the discharge current from the oscillator current source  136  also increases, and thus resulting in a shortened instantaneous period (and higher frequency) for the clock signal CLK. When the error signal voltage (V COMP ) decreases, the discharge current from the oscillator current source  136  also decreases, and thus resulting in a lengthened instantaneous period (and lower frequency) for the clock signal CLK. 
         [0033]    Even though the PWM switching regulator  100  in  FIG. 1  is shown as a single phase regulator, the present technology can also be applied to multi-phase switching regulators. For example,  FIG. 6  is a schematic circuit diagram of a three-phase PWM switching regulator  200  in accordance with embodiments of the present technology. As shown in  FIG. 6 , unlike the PWM switching regulator  100  of  FIG. 1 , the PWM switching regulator  200  includes first, second, and third phase splitters  109   a ,  109   b , and  109   c  individually coupled to first, second, and third PWM controllers  104   a ,  104   b , and  104   c , switching circuits  102   a ,  102   b , and  102   c , and inductors  106   a ,  106   b , and  106   c . The individual phase splitters  109   a ,  109   b , and  109   c  selectively enable the respective PWM controllers  104   a ,  104   b , and  104   c  at different phases. Even though a three phase application is shown in  FIG. 6 , the present technology can also be applied to two-phase applications and/or other suitable types of applications. 
         [0034]    From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosed technology. Elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the technology is not limited except as by the appended claims.