Abstract:
There is disclosed a regulator for a charge pump having an input signal and generating an output signal at a value greater than the input signal. The charge pump comprises at least a capacitor and at least a device for charging and discharging the capacitor; the regulator comprises means having at the input said signal exiting the charge pump and a reference signal. Said means are able to generate a supply signal for said at least a device in response to the value of the difference between the output signal of the charge pump and said reference signal.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a regulator for a charge pump and a circuit that implements the regulator. 
         [0003]    2. Description of the Related Art 
         [0004]    A charge pump is a particular boosting circuit that is used to generate higher voltage than the supply voltage thereof. Normally, charge pumps are implemented in integrated circuits. In general, the operation of a charge pump is based on removing a significant charge quantity from the supply voltage and transferring the charge quantity to a series of capacitive stages that convey the charge quantity to the output. The frequency of this removal is determined by a regulating circuit that enables the output voltage to be fixed at the desired value. 
         [0005]    Current regulating circuits compare the output voltage of the charge pump and a reference voltage. On the basis of this comparison, the regulating circuits supply the enabling signals to the various stages of the charge pump to remove the charge from one stage to a successive stage of the series, with a frequency variable between zero and a clock frequency set externally. In  FIG. 1  there is shown a charge pump  1  with a regulating circuit  2  having an input voltage Vout exiting from charge pump  1  and a clock signal CK. The signal Ckin exiting from the regulator  2  enters the charge pump  1  that is supplied by a supply signal Vdd. 
         [0006]    This operating principle has the advantage of maximizing the efficiency of the pump as it is switched on only when necessary. The drawback arises from the fact that the frequency of the removal of current from the supply depends on the load attached to the pump; in fact, transmitting enabling signals to low-frequency capacitive stages generally corresponds to a loadless pump status, i.e., to the absence of a load, whilst transmitting enabling signals to the high-frequency capacitive stages corresponds to a high request from the load. In  FIG. 2  there are shown the time diagrams of the signals Ivdd, Vout and Iout. 
         [0007]    This pattern leads to variable frequency absorption spikes on the supply, and this generates a wide-spectrum noise that is reflected in the entire integrated circuit supplied by the supply voltage. In  FIG. 3  there is shown the frequency spectrum S of the current Ivdd. 
         [0008]    A charge pump in which there are provided means for reducing noise is known from patent EP 1408604. The charge pump comprises a sequence of capacitive stages and means for transferring the electric charge from each capacitive block to the next capacitive block of the sequence. The transferring means are enabled alternatively during a first phase and a second phase. The charge pump includes means for limiting the current that runs through each capacitive stage during the first phase and the second phase. 
       BRIEF SUMMARY 
       [0009]    In view of the foregoing, the present disclosure provides a regulator for a charge pump that reduces the noise in the charge pump. 
         [0010]    According to one embodiment of the present disclosure, a regulator for a charge pump having an input signal and generating an output signal at a value greater than the input signal is provided, the charge pump including at least a capacitor and at least a device for charging and discharging the capacitor. The regulator includes means such as a circuit having at the input the output signal from the charge pump and a reference signal, the means adapted to generate a supply signal for at least one device in response to the value of the difference between the output signal of the charge pump and the reference signal. 
         [0011]    In accordance with another embodiment of the present disclosure, a circuit structure is provided that includes a charge pump and a regulator of the charge pump, the charge pump having an input to receive an input signal and an output on which is generated an output signal at a value greater than the input signal, the charge pump having at least a capacitor and at least one device for charging and discharging the capacitor, said regulator comprising means having at the input said output signal from the charge pump and a reference signal, said means adapted to generate a supply signal for said at least one device in response to the value of the difference between said output signal of the charge pump and said reference signal. 
         [0012]    In accordance with another aspect of the foregoing embodiment, the means includes an operational amplifier suitable for amplifying the difference between said output signal of the charge pump and said reference signal and a transistor driven by the output signal of said operational amplifier and having a non-drivable terminal connected to a further supply voltage and generating on said other non-drivable terminal said supply signal. 
         [0013]    In accordance with another aspect of the foregoing embodiment, the charge pump includes a plurality of charge stages that each have at least one capacitor and at least one charging and discharging device for charging and discharging the capacitor, each of the charging and discharging devices receiving the signal from the regulator as a supply signal. 
         [0014]    In accordance with another embodiment of the present disclosure, a regulator circuit for a charge pump having first, second, and third inputs and an output is provided. The regulator circuit includes an operational amplifier comprising a first input coupled to the output of the charge pump, a second input adapted to receive a voltage reference value, and an output; and a switch having a control terminal coupled to the output of the operational amplifier, a first terminal coupled to a supply voltage, and a second terminal coupled to a ground reference potential and to the first input of the charge pump. 
         [0015]    In accordance with another aspect of the foregoing embodiment, the regulator circuit includes a voltage divider coupled between the output of the charge pump and the first input of the operational amplifier. 
         [0016]    In accordance with another aspect of the foregoing embodiments, the regulator circuit includes a first compensation capacitor coupled between the output of the operational amplifier and the output of the charge pump, and a second compensation capacitor coupled between the output of the operational amplifier and the second terminal of the switch. 
         [0017]    In accordance with another embodiment of the present disclosure, a circuit is provided that includes a charge pump having an input adapted to receive an input signal and an output for an output signal having a voltage value greater than the input signal at the input of the charge pump; and a regulator circuit that includes an operational amplifier having a first input coupled to the output of the charge pump, a second input adapted to receive a voltage reference value, and an output; and a switch having a control terminal coupled to the output of the operational amplifier, a first terminal coupled to a supply voltage, and a second terminal coupled to a ground reference potential and to the first input of the charge pump. 
         [0018]    In accordance with another aspect of the foregoing embodiment, the charge pump has an input to receive an input signal and an output on which is generated an output signal at a value greater than the input signal. In addition, the charge pump includes at least a capacitor and at least one device for charging and discharging the capacitor. The charging and discharging device preferably receives as a supply voltage an output of the switch. 
         [0019]    In accordance with another aspect of the foregoing embodiment, the charge pump includes a plurality of charge stages each including at least one capacitor and the at least one device for discharging and charging the capacitor, the signal generated by the regulator being the supply signal of each of the at least one devices and the input signal of only the first stage of the charge pump. 
         [0020]    In accordance with another aspect of the foregoing embodiment, the regulator circuit includes a voltage divider coupled between the output of the charge pump and the first input of the operational amplifier. Ideally, compensation capacitors are coupled between the output of the operational amplifier and the output of the charge pump and between the output of the operational amplifier and the second terminal of the switch. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0021]    The features and the advantages of the present disclosure will be clear from the following detailed description of practical embodiments thereof, illustrated by way of non-limiting example in the following attached drawings, in which: 
           [0022]      FIG. 1  shows a traditional diagram of a charge pump circuit; 
           [0023]      FIG. 2  shows the time diagrams of signals in the circuit in  FIG. 1 ; 
           [0024]      FIG. 3  shows the frequency spectrum of the current Ivdd; 
           [0025]      FIG. 4  shows a charge pump with a regulator according to the present disclosure; 
           [0026]      FIG. 5  shows the charge pump in  FIG. 4  in greater detail; 
           [0027]      FIG. 6  shows a frequency spectrum of the current Ivdd in the circuit in  FIG. 4 ; and 
           [0028]      FIG. 7  shows the temporal pattern of the signals Vout and Iload as the signal Vin varies. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    In  FIG. 4  there is shown a regulator circuit for a charge pump  1  according to one embodiment of the present disclosure. The charge pump  1  has an input signal Val and supplies with voltage Vout a load LOAD that is connected to ground GND and in which a current “Iload” flows. The regulator circuit includes a series of resistances R 1  and R 2  arranged between the voltage Vout exiting the charge pump  1  and the ground GND, a differential amplifier  3  suitable for amplifying the difference between the voltage Vr=Vout*R 2 /(R 1 +R 2 ) and a reference voltage Vref and suitable for driving, by means of the output signal Vg, a transistor M, for example a PMOS transistor, having the source terminal connected to the supply voltage Vdd and the drain terminal connected to a current generator I connected in turn to ground GND. There are the compensating capacitors Cc 1  and Cc 2  respectively arranged between the voltage Vout and the voltage Vg and the voltage Vg and the drain terminal of the transistor M. The regulator generates a voltage Vin on the drain terminal that is in input to the charge pump  1 . 
         [0030]    In this case the regulator supplies to the charge pump  1  a variable input supply voltage Vin and the charge pump operates at a fixed operating frequency CK. In this manner the frequency spectrum S of the current Ivdd has multiple-frequency harmonics of CK, as visible in  FIG. 6 . 
         [0031]    In  FIG. 5  there is shown a charge pump with two stages  10  and  11 . Stage  10  comprises a charge stage comprising two MOS transistors M 1  and M 2 , as shown in  FIG. 5  NMOS transistors, that have the gate terminals connected respectively to the drain terminals of the transistor M 2  and to the drain terminal of the transistor M 1 . The drain terminals of the transistors M 1  and M 2  are respectively connected to two capacitors C 1  and C 2  connected to two devices B 1  and B 2  having respectively the input signal Ck and the negated input signal Ck and being suitable for charging and draining the capacitors C 1  and C 2 . The source terminals of the transistors M 1  and M 2  are connected to the voltage Vdd, which is the voltage Val of  FIG. 4 . According to this embodiment, the devices B 1  and B 2  are supplied by the signal Vin exiting from the regulator. 
         [0032]    Stage  11  includes a charge stage that includes two MOS transistors M 3  and M 4 , as shown in  FIG. 5  to be PMOS transistors, that have the gate terminals connected respectively to the drain terminal of the transistor M 4  and to the drain terminal of the transistor M 3 . The drain terminals of the transistors M 3  and M 4  are respectively connected to two capacitors C 3  and C 4  connected to two devices B 3  and B 4  having respectively the input signal Ck, and the negated input signal Ck which are suitable for charging and discharging the capacitors C 3  and C 4 . According to the disclosure the devices B 3  and B 4  are supplied by the signal Vin exiting from the regulator. The source terminals of the transistors M 3  and M 4  are in common. 
         [0033]    Between the output of stage  10  and the input of stage  11  there is arranged a circuit having two PMOS transistors MP 1  and MP 2 ; the drain terminal of the transistor MP 1  is connected to the gate terminal of the transistor MP 2  and to the gate terminal of the transistor M 2  whilst the drain terminal of the transistor MP 2  is connected to the gate terminal of the transistor MP 1  and to the gate terminal of the transistor M 1  and the source terminals are in common and connected to the source terminals of the transistors M 3  and M 4 . 
         [0034]    At the output of stage  11  there is arranged a circuit having two PMOS transistors MP 3  and MP 4 ; the drain terminal of the transistor MP 3  is connected to the gate terminal of the transistor MP 4  and to the gate terminal of the transistor M 4  whilst the drain terminal of the transistor MP 4  is connected to the gate terminal of the transistor MP 3  and to the gate terminal of the transistor M 3  and the source terminals are in common and connected to a load LOAD on which there is located the output voltage Vout of the charge pump. 
         [0035]    Thus with a charge pump having a plurality of n charge stages  10 ,  11  . . .  1   n , the voltage Vin is suitable for supplying the devices B 1 , B 2  . . . Bn of the single charge stages. 
         [0036]    According to a version of this embodiment of the present disclosure, the voltage Vin is suitable for supplying the first stage of the charge pump alternatively to the voltage Vdd, as visible in  FIG. 5  where the voltage Vin, indicated by a broken line, supplies the charge stage  10  instead of the voltage Vdd. More precisely, the voltage Vin supplies only the transistors M 1  and M 2  of the first charge stage  10 , i.e., the “pumping structure” of the charge stage  10 . 
         [0037]    In  FIG. 7  there are shown the time diagrams of the output voltage Vout, of the current on the load LOAD Iload, and of the voltage Vin. The current Iload increases on a ramp from 10 ua to 300 uA, the voltage Vout is maintained stable at a value of 6.5 Volt and the voltage Vin increases from a value of 1.8 Volt with Iload at 10 uA to a value of 2.3 Volt with Iload at 300 uA. 
         [0038]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
         [0039]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.