Abstract:
An active matrix display driving circuit is disclosed. Each pixel driving circuit includes one luminance device, one transistor connected to the device, one driving transistor and one storage capacitor. There are two switching transistors at one end of the storage capacitor connecting to two voltage levels for capacitive coupling and gate voltage of the driving transistor is changed. This driving circuit is applicable to the current driving pixel circuit of Poly-Si TFT EL display panel, improves image defects resulting from uneven threshold voltage of a TFT and IR drop and solves charging/discharging time problems for low current import.

Description:
FIELD OF THE INVENTION  
       [0001]     This invention relates to a driving circuit of electro-luminescence device (EL device) is applicated in pixel of display. More particularly, the invention is directed to a driving device that improves the defect of images on an active matrix Poly-Si TFT EL device resulted from an inconsistent threshold voltage (Vth) and IR drop in addition to charging/discharging time problem.  
       BACKGROUND OF THE INVENTION  
       [0002]     An EL device display can be classified according to its driving method, passive matrix (PM-EL Display) and active matrix (AM-EL Display). AM-EL display uses TFT (Thin Film Transistor) with a capacitor for storing data signals that can control EL display gray levels of brightness.  
         [0003]     The manufacturing procedure of a PM-EL display is simpler in comparison and less costly; however, it is limited in its size (&lt;5 inches) because of its driving mode and has a lower-resolution display application. In order to produce an EL display with higher resolution and larger size, utilizing active-matrix driving is necessary. The AM-EL uses TFT with a capacitor for storing data signals, so that the pixels can maintain their brightness after line scanning; on the other hand, pixels of passive matrix drive only light up when the scan line selects them. Therefore, with active matrix driving, the brightness of EL device is not necessarily ultra-bright, resulting in longer lifetime, higher efficiency and higher resolution. Naturally, EL devices with active matrix driving are suitable for display applications of a higher resolution and excellent picture quality.  
         [0004]     LTPS (Low Temperature Poly-Silicon) and a-Si (Amorphous Silicon) are both technologies of TFT integrating on glass substrate. The obvious differences are electric characteristics and complexity of processing. Although LTPS-TFT possesses higher carrier mobility and higher mobility means more current can be supplied, the process is much more complex. However, the process of a-Si TFT is simpler and more mature, except for low carrier mobility. Therefore, a-Si process has better competitive advantage in cost.  
         [0005]     Due to limitations of LTPS process capability, threshold voltage (Vth) and mobility of TFT elements produced vary leading to different properties of each TFT element. When the driving system achieves gray scale by analog voltage modulation, an EL device produces a different output current despite having the same data voltage signal input due to the different TFT characteristics of various pixels. Therefore, the luminance of an OLED varies. Images of erroneous gray scale will show up on OLED panel and seriously damage image uniformity.  
         [0006]     The most urgent problem of the AM-EL display to be solved currently is how to reduce the impact of uneven LTPS-TFT characteristics. Such an issue requires an immediate solution for follow-up development and applications since images on the display tell the difference.  
         [0007]     U.S. Pat. No. 6,373,454 discloses ┌Active matrix electroluminescent display devices ┘ (Apr. 26, 2002), No. 6,229,506 discloses ┌Active matrix light emitting diode pixel structure and concomitant method┘ (May 26, 2001) and Toshiba publishes a thesis titled ┌A Novel Current Programmed Pixel for Active Matrix OLED Displays┘ (Society for Information Display 2003 (SID 2003)).  
         [0008]     For the above patents and thesis, the input current on the data line and output current to the EL device was 1:1. Thus, there was a defect of long charge/discharge times for the capacitor and the parasitical capacitor at low current input.  
         [0009]     U.S. Pat. No. 6,359,605 discloses ┌Active matrix electroluminescent display devices┘ (Mar. 26, 2002), U.S. Pat. No. 6,501,466 proposes ┌Active matrix type display apparatus and drive circuit thereof┘ (Dec. 26, 2002) and U.S. Pat. No. 6,535,185 presents ┌Active driving circuit for display panel┘ (Mar. 26, 2003).  
         [0010]     For the aforementioned patents, the theory of current mirror is utilized to achieve the rate of input current and output current as n:1. However, two TFTs in the current mirror have to be matched to prevent threshold voltage (Vth) difference and mobility. Thus, requirements for TFT manufacturing process are stricter.  
         [0011]     The common problem for the circuits above is the voltage discharged from the storage capacitor to the gate and source of the driving transistor (Vgs) has to be less than the threshold voltage (Vth) of the driving transistor. Nevertheless, Vgs is larger than Vth due to long discharging time. Consequently, EL device illuminates via a small current and therefore the contrast of the display panel is not good.  
         [0012]     A thesis with the subject of ┌A New Current Programmable Pixel Structure for large-Size and High-Resolution AMOLEDs┘ is released by Samsung (International Display Workshops 2002 (IDW 2002)). The theory of capacitive coupling is applied to change the gate voltage (Vg) of the driving TFT to establish a relationship between the output and input currents as output current=A×input current+B (A and B are constants). As capacitors are affected by the process or the layout, the voltage of capacitive coupling changes and the output current of the driving transistor is influenced, too. Defects of this driving method are capacitance precision and impose strict requirements for capacitor processing and layout. In addition, the aperture ratio of pixels becomes smaller as two capacitors are required to drive one pixel.  
       SUMMARY OF THE INVENTION  
       [0013]     The main purpose of this invention is to solve the said problems. This invention not only improves image defects resulting from uneven characteristics of TFT and IR drop, but also solves the problem of long charge/discharge times for low current inputs.  
         [0014]     To achieve the objective above, every pixel on the display panel comprises one scan line and one data line. A driving device of each pixel includes a first scan transistor and a second scan transistor, whose gates (G) are connected to scan line and sources (S) connected to data line. A driving transistor is also included and connected to the voltage supply line.  
         [0015]     The source (S) of connect transistor is connected to the drains (D) of the driving transistor and the second scan transistor and the gate (G) is connected to emission line.  
         [0016]     The source (S) of first switch transistor is connected to the first voltage supply and the gate is connected to the scan line; the source (S) of second switch transistor is connected to second voltage supply and the gate (G) is connected to the emission line.  
         [0017]     One end of storage capacitor connects to the drains (D) of the first and second switch transistors and the other end is connected to the drain (D) of the first scan transistor and the gate (G) of the driving transistor. The anode of luminescence element is connected to the drain of the connect transistor and the cathode is grounded. All transistors are PMOS transistors and the voltage of the second voltage supply is greater than that of the first voltage supply.  
         [0018]     The first voltage supply can connect to the emission line and the second voltage supply connect to the scan line; alternatively, the first voltage supply can connect to the voltage supply; or, the first voltage supply can connect to the voltage supply and the second voltage supply connects to the scan line.  
         [0019]     Another embodiment is to change all transistors to NMOS, and the driving circuit includes a first scan transistor and a second scan transistor, whose gates (G) connect to the scan line and sources (S) are connect to the data line. One driving transistor is also included, with the source (S) grounded. One connect transistor is included, with its source (S) connected to the drains (D) of the driving transistor and the first scan transistor and the gate (G) connected to one emission line.  
         [0020]     The source (S) of one first switch transistor is connected to one first voltage supply and the gate (G) is connected to the scan line; the source (S) of the second switch transistor is connected to second voltage supply and the gate (G) is connected to the emission line.  
         [0021]     One end of one storage capacitor connects to the drains (D) of the first and second switch transistors and the other end is connected to the drain (D) of the second scan transistor and the gate (G) of the driving transistor. The anode of one luminescence element is connected to the voltage supply and the cathode is connected to the drain (D) of the connect transistor.  
         [0022]     The same as the above driving circuit, the first voltage supply may be connected to the emission line and the second voltage supply connected to the scan line; alternatively, only the first voltage supply is grounded; or, the first voltage supply is grounded and the second voltage supply is connected to the scan line. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]      FIG. 1  is the circuit of a pixel in embodiment 1 in this invention.  
         [0024]      FIG. 2  is the circuit of a pixel in embodiment 2 in this invention.  
         [0025]      FIG. 3  is the circuit of a pixel in embodiment 3 in this invention.  
         [0026]      FIG. 4  is the circuit of a pixel in embodiment 4 in this invention.  
         [0027]      FIG. 5  is the circuit of a pixel in embodiment 5 in this invention.  
         [0028]      FIG. 6  is the circuit of a pixel in embodiment 6 in this invention.  
         [0029]      FIG. 7  is the circuit of a pixel in embodiment 7 in this invention.  
         [0030]      FIG. 8  is the circuit of a pixel in embodiment 8 in this invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     EMBODIMENT 1  
       [0031]     Refer to  FIG. 1  for the circuit of a pixel of embodiment 1 in this invention. As the Figure shows: the driving circuit of each pixel on the display panel includes one scan line  10  and one data line  20  as follows:  
         [0032]     Gates (G) of a first scan transistor TI and a second scan transistor T 2  connected to one scan line  10  and source (S) connected to a data line  20 .  
         [0033]     Source (S) of a driving transistor T 3  connected to VDD. Source (S) of connect transistor T 4  connected to drains (D) of driving transistor T 3  and second scan transistor T 2  and gate (G) connected to one emission line  30 .  
         [0034]     Source (S) of a first switch transistor T 5  connected to first voltage supply V 1  and gate (G) connected to scan line  10 . Source (S) of a second switch transistor T 6  connected to second voltage supply V 2  and gate (G) connected to emission line  30 . The above first scan transistor T 1 , second scan transistor T 2 , driving transistor T 3 , connect transistor T 4 , first switch transistor T 5  and second switch transistor T 6  are PMOS transistors. One end of storage capacitor Cs connected to drains (D) of the first switch transistor T 5  and second switch transistor T 6  and the other end connected to drain (D) of first scan transistor T 1  and gate (G) of driving transistor T 3 . Anode of a luminescence device  40  connected to drain (D) of connect transistor T 4  and cathode grounded. Luminescence device  40  is an electro-luminescence device (EL device).  
         [0035]     Gates (G) of first scan transistor TI and second scan transistor T 2  controlled by nth Scan Line  10  and sources connected to data line  20 .  
         [0036]     Gate (G) of connect transistor T 4  controlled by nth emission line  30 . Current passing by luminescence device  40  determined by gate (G) of driving transistor T 3 .  
         [0037]     Gate (G) of first switch transistor T 5  controlled by nth scan line  10  and that of second switch transistor T 6  controlled by nth emission line  30 .  
         [0038]     Actuation procedures of this invention are described as follows:  
         [0039]     1. When the system scans the nth scan line  10 , the potential is low (V S,L ), leading first scan transistor T 1 , second scan transistor T 2  and first switch transistor T 5  to become on. As the potential of the nth emission line  30  is high (V E,H ), connect transistor T 4  and second switch transistor T 6  are off. Thus, no current will pass through luminescence device  40  to prevent writing mistakes of storage capacitor Cs.  
         [0040]     One end of storage capacitor Cs connected to gate (G) of driving transistor T 3  links up with data line  20  through scan transistor T 1  and the other end is connected to first voltage supply V 1  via first switch transistor T 5 . Meanwhile, part of data current I Data  charges/discharges storage capacitor Cs through first scan transistor T 1  and first switch transistor T 5 . Gate voltage (V g3 ) of driving transistor T 3  equals voltage of first voltage supply V 1  less that of storage capacitor Cs (V 1 −V CS ).  
         [0041]     Consequently, drive current (I Drive ) passing through driving transistor T 3  is as follows: I Drive =(½)×β×(V sg3 −V th3 ) 2  (β as trans-conductance parameter of driving transistor T 3  and source gate voltage of driving transistor T 3 , V sg3 =VDD−V g3 =VDD−(V 1 −V CS ). At present, data current I Data  equals current passing through storage capacitor Cs (I CS ) plus drive current (I Drive ) passing through driving transistor T 3 ; i.e., I Data =I CS +I Drive .  
         [0042]     2. Voltage of storage capacitor Cs (V CS ) makes drive current (I Drive ) passing through driving transistor T 3  the same as data current of data line  20 ; that is, I Data =I Drive =(½)×β×(V sg3 −V th3 ) 2  and V sg3 =VDD−V g3 =VDD−(V 1 −V CS ).  
         [0043]     Data write is completed at the moment and voltage of storage capacitor Cs (V CS )=(2×I Data /β) (1/2) −(VDD−V 1 −V th3 ).  
         [0044]     3. Lastly, when potential of the nth Scan Line  10  changes from low (V S,L ) to high (V S,H ), First scan transistor T 1 , second scan transistor T 2  and first switch transistor T 5  are off. Meanwhile, potential of the nth Emission line  30  changes from high (V E,H ) to low (V E,L ), leading connect transistor T 4  and second switch transistor T 6  to become on.  
         [0045]     One end of storage capacitor Cs is connected to gate (G) of driving transistor T 3  and the other end to second voltage supply V 2  via second switch transistor T 6 . Thus, gate voltage V g3  of driving transistor T 3  equals voltage of second voltage supply V 2  less that of storage capacitor Cs; i.e., V g3 =V 2 −V CS .  
         [0046]     Drive current passing through driving transistor T 3  is as follows: I Drive =(½)×β×(V sg3 −V th3 ) 2  and V sg3 =VDD−V g3 =VDD−(V 2 −V CS ). Luminescence device  40  is illuminated as drive current (I Drive ) passes through it via connect transistor T 4 .  
         [0047]     In summary, the relationship between data current (I Data ) and drive current (I Drive ) is shown as I Drive =(½)×β×[(2×I Data /β) (1/2) +V 1 −V 2 ] 2 .  
         [0048]     According to the above theory and formula, current output to luminescence device  40  is only related to data current (I Data ) written, not threshold voltage (Vth) of driving transistor T 3 . As a result, threshold voltage difference resulted from process factors can be compensated.  
         [0049]     Voltage difference between first voltage supply V 1  and second voltage supply V 2  causes an offset at gate (G) voltage (V g3 ) of driving transistor T 3 . If voltage of second voltage supply V 2  is greater than that of first voltage supply V 1 , larger data current (I Data ) may be imported by small drive current (I Drive ) at low gray scale to reduce charging time of storage capacitor Cs and parasitical capacitor.  
       EMBODIMENT 2  
       [0050]     Refer to  FIG. 2  for the circuit of a pixel of embodiment 2 in this invention. As the Figure shows, the driving circuit of each pixel on the display panel includes one scan line  10  and one data line  20 . The driving circuit in this embodiment is about the same as that in Embodiment 1; however, the only difference is source (S) of first switch transistor T 5  connected to emission line  30  instead of first voltage supply V 1  and source (S) of second switch transistor T 6  connected to scan line  10 , not second voltage supply V 2 .  
         [0051]     Actuation procedures of Embodiment 2 are described as follows:  
         [0052]     1. When the system scans the nth scan line  10 , the potential is low (V S,L ), leading first scan transistor T 1 , second scan transistor T 2  and first switch transistor T 5  to become on. As the potential of the nth emission line  30  is high (V E,H ), connect transistor T 4  and second switch transistor T 6  are off. Thus, no current will pass through luminescence device  40  to prevent writing mistakes to the storage capacitor Cs.  
         [0053]     One end of storage capacitor Cs connected to gate (G) of driving transistor T 3  links up with data line  20  through first scan transistor T 1  and the other end is connected to nth emission line  30  via first switch transistor T 5 . Meanwhile, part of data current (I Data ) charges/discharges storage capacitor Cs through first scan transistor T 1  and first switch transistor T 5 . Gate voltage (V g3 ) of driving transistor T 3  equals voltage of emission line  30  (V E,H ) less that of storage capacitor Cs (V E,H −V CS ).  
         [0054]     Consequently, drive current (I Drive ) passing through driving transistor T 3  is as follows: I Drive =(½)×β×(V sg3 −V th3 ) 2  (β as trans-conductance parameter of driving transistor T 3  and source gate voltage of driving transistor T 3 , V sg3 =VDD−V g3 =VDD−(V E,H −V CS )). Hence, data current I Data  equals current passing through storage capacitor Cs (I CS ) plus drive current (I Drive ) passing through driving transistor T 3 ; i.e., I Data =I CS +I Drive .  
         [0055]     2. Voltage of storage capacitor Cs (V CS ) makes drive current (I Drive ) passing through driving transistor T 3  the same as data current (I Data ) of data line  20 ; that is, I Data =I Drive =(½)×β×(V sg3 −V th3 ) 2  and V sg3 =VDD−V g3 =VDD−(V E,H −V CS ).  
         [0056]     Data write is completed at the moment and voltage of storage capacitor Cs (V CS )=(2×I Data /β) (1/2) −(VDD−V E,H −V th3 ).  
         [0057]     3. Lastly, when the potential of the nth scan line  10  changes from low (V S,L ) to high (V S,H ), first scan transistor T 1 , second scan transistor T 2  and first switch transistor T 5  are OFF. Meanwhile, potential of the nth emission line  30  changes from high (V E,H ) to low (V E,L ), leading connect transistor T 4  and second switch transistor T 6  are ON.  
         [0058]     One end of storage capacitor Cs is connected to gate (G) of driving transistor T 3  and the other end to scan line  10  via second switch transistor T 6 . Thus, gate voltage V g3  of driving transistor T 3  equals voltage of scan line  10  at high potential (V S,H ) less that of storage capacitor Cs; i.e., V g3 =V S,H −V cs .  
         [0059]     Drive current passing through driving transistor T 3  is as follows: I Drive =(½)×β×(V sg3 −V th3 ) 2  and V sg3 =VDD−V g3 =VDD−(V S,H −V CS ). Luminescence device  40  is illuminated as drive current (I Drive ) passes through it via connect transistor T 4 .  
         [0060]     In summary, the relationship between data current (I Data ) and drive current (I Drive ) is shown as I Drive =(½)×β×[(2×I Data /β) (1/2) +V E,H −V S,H ] 2 .  
         [0061]     According to the above theory and formula, current output to luminescence device  40  is only related to data current (I Data ) written, not threshold voltage (Vth) of driving transistor T 3 . As a result, threshold voltage difference resulting from processing factors can be compensated for.  
         [0062]     In addition, voltage differences between scan line  10  (V S,H ) high level voltage and emission line  30  (V E,H ) high level voltage causes an offset at gate (G) voltage (V g3 ) of driving transistor T 3 . If potential of scan line  10  (V S,H ) is higher than that of emission line  30  (V E,H ), greater data current (I Data ) may be imported by small drive current (I Drive ) at low gray scale to reduce charging time of storage capacitor Cs and parasitical capacitor.  
       EMBODIMENT 3  
       [0063]     Refer to  FIG. 3  for the circuit of a pixel of embodiment 3 in this invention. As the Figure shows, the driving circuit of each pixel on the display panel includes one scan line  10  and one data line  20 . The driving circuit in this embodiment is about the same as that in Embodiment 1; however, the only difference is the source (S) of first switch transistor T 5  is connected to voltage supply VDD instead of First voltage supply V 1  and source (S) of second switch transistor T 6  still connected to second voltage supply V 2  as in Embodiment 1.  
         [0064]     Actuation procedures of Embodiment 3 are described as follows:  
         [0065]     1. When the system scans the nth scan line  10 , the potential is low (V S,L ), leading first scan transistor T 1 , second scan transistor T 2  and first switch transistor T 5  to become on. As the potential of the nth emission line  30  is high (V E,H ), connect transistor T 4  and second switch transistor T 6  are off. Thus, no current will pass through luminescence device  40  to prevent writing mistakes of storage capacitor Cs.  
         [0066]     One end of storage capacitor Cs connected to gate of driving transistor T 3  links up with data line  20  through scan transistor T 1  and the other end is connected to voltage supply VDD via first switch transistor T 5 . Meanwhile, part of data current (I Data ) charges/discharges storage capacitor Cs through first scan transistor T 1  and first switch transistor T 5 . Gate voltage (V g3 ) of driving transistor T 3  equals voltage of voltage supply VDD less that of storage capacitor Cs (VDD−V CS ).  
         [0067]     Consequently, drive current (I Drive ) passing through driving transistor T 3  is as follows: I Drive =(½)×β×(V sg3 −V th3 ) 2  (β as trans-conductance parameter of driving transistor T 3  and source gate voltage of driving transistor T 3 , V sg3 =VDD−V g3 =VDD−(VDD−V CS ). Hence, data current (I Data ) equals current passing through storage capacitor Cs (I CS ) plus drive current (I Drive ) passing through driving transistor T 3 ; i.e., I Data =I CS +I Drive .  
         [0068]     2. Voltage of storage capacitor Cs (V CS ) makes drive current (I Drive ) passing through driving transistor T 3  the same as data current (I Data ) of data line  20 ; that is, I Data =I Drive =(½)×β×(V sg3 −V th3 ) 2  and V sg3 =VDD−V g3 =VDD−(VDD−V CS ).  
         [0069]     Data write is completed at the moment and voltage of storage capacitor Cs (V CS )=(2×I Data /β) (1/2) −(VDD−VDD−V th3 ).  
         [0070]     3. Last, when potential of the nth scan line  10  changes from low (V S,L ) to high (V S,H ), first scan transistor T 1 , second scan transistor T 2  and first switch transistor T 5  are off. Meanwhile, potential of the nth emission line  30  changes from high (V E,H ) to low (V E,L ), leading connect transistor T 4  and second switch transistor T 6  to become on.  
         [0071]     One end of storage capacitor Cs is connected to gate of driving transistor T 3  and the other end to second voltage supply V 2  via second switch transistor T 6 . Thus, gate voltage (V g3 ) of driving transistor T 3  equals voltage of second voltage supply V 2  less that of storage capacitor Cs; i.e., V g3 =V 2 −V cs .  
         [0072]     Drive current passing through driving transistor T 3  is as follows: I Drive =(½)×β×(V sg3 −V th3 ) 2  and V sg3 =VDD−V g3 =VDD−(V 2 −V CS ). Luminescence device  40  is illuminated as drive current (I Drive ) passes through it via connect transistor T 4 .  
         [0073]     In summary, the relationship between data current (I Data ) and drive current (I Drive ) is shown as I Drive =(½)×β×[(2×I Data /β) (1/2) +VDD−V 2 ] 2 .  
         [0074]     According to the above theory and formula, current output to luminescence device  40  is only related to data current (I Data ) written, not threshold voltage (Vth) of driving transistor T 3 . As a result, threshold voltage difference resulted from process factors can be compensated.  
         [0075]     In addition, voltage difference between voltage supply VDD and second voltage supply V 2  causes an offset at the gate (G) of driving transistor T 3 . If voltage of second voltage supply V 2  is greater than that of voltage supply VDD, larger data current (I Data ) may be imported by small drive current (I Drive ) at low gray scale to reduce charging time of storage capacitor Cs and parasitical capacitor.  
       EMBODIMENT 4  
       [0076]     Refer to  FIG. 4  for the circuit of a pixel of embodiment 4 in this invention. As the Figure shows, the driving circuit of each pixel on the display panel includes one scan line  10  and one data line  20 . The driving circuit in this embodiment is about the same as that in Embodiment 2; however, the only difference is source (S) of first switch transistor T 5  connected to voltage supply VDD instead of emission line  30  and source (S) of second switch transistor T 6  still connected to scan line  10 .  
         [0077]     Actuation procedures of Embodiment 4 are described as follows:  
         [0078]     1. When the systems scans the nth scan line  10 , the potential is low (V S,L ), leading first scan transistor T 1 , second scan transistor T 2  and first switch transistor T 5  to become on. As the potential of the nth emission line  30  is high (V E,H ), connect transistor T 4  and second switch transistor T 6  are OFF. Thus, no current will pass through luminescence device  40  to prevent writing mistakes of storage capacitor Cs.  
         [0079]     One end of storage capacitor Cs connected to gate (G) of driving transistor T 3  links up with data line  20  through scan transistor T 1  and the other end is connected to voltage supply VDD via first switch transistor T 5 . Meanwhile, part of data current (I Data ) charges/discharges storage capacitor Cs through first scan transistor T 1  and first switch transistor T 5 . Gate voltage (V g3 ) of driving transistor T 3  equals voltage of voltage supply VDD less that of storage capacitor Cs (VDD−V CS ).  
         [0080]     Consequently, drive current (I Drive ) passing through driving transistor T 3  is as follows: I Drive =(½)×β×(V sg3 −V th3 ) 2  (βas trans-conductance parameter of driving transistor T 3  and source gate voltage of driving transistor T 3 , V sg3 =VDD−V g3 =VDD−(VDD−V CS ). Hence, data current (I Data ) equals current passing through storage capacitor Cs (I CS ) plus drive current (I Drive ) passing through driving transistor T 3 ; i.e., I Data =I CS +I Drive .  
         [0081]     2. Voltage of storage capacitor Cs (V CS ) makes drive current (I Drive ) passing through driving transistor T 3  the same as data current (I Data ) of data line  20 ; that is, I Data =I Drive =(½)×β×(V sg3 −V th3 ) 2  and V sg3 =VDD−V g3 =VDD−(VDD−V CS ).  
         [0082]     Data write is completed at the moment and voltage of storage capacitor Cs (V CS )=(2×I Data /β) (1/2) −(VDD−VDD−Vth 3 ).  
         [0083]     3. Last, when potential of the nth scan line  10  changes from low (V S,L ) to high (V S,H ), first scan transistor T 1 , second scan transistor T 2  and first switch transistor T 5  are off. Meanwhile, potential of the nth emission line  30  changes from high (V E,H ) to low (V E,L ), leading connect transistor T 4  and second switch transistor T 6  to become on.  
         [0084]     One end of storage capacitor Cs is connected to gate (G) of driving transistor T 3  and the other end to scan line  10  via second switch transistor T 6 . Thus, gate voltage (V g3 ) of driving transistor T 3  equals voltage of scan line  10  at high (V S,H ) less that of storage capacitor Cs; i.e., V g3 =V S,H −V cs .  
         [0085]     Drive current passing through driving transistor T 3  is as follows: I Drive =(½)×β×(V sg3 −V th3 ) 2  and V sg3 =VDD−V g3 =VDD−(V S,H −V CS ). Luminescence device  40  is illuminated as drive current (I Drive ) passes through it via connect transistor T 4 .  
         [0086]     In summary, the relationship between data current (I Data ) and drive current (I Drive ) is shown as I Drive =( ½)×β×[( 2×I Data /β) (1/2) +VDD−V S,H ] 2 .  
         [0087]     According to the above theory and formula, current output to luminescence device  40  is only related to data current (I Data ) written, not threshold voltage (Vth) of driving transistor T 3 . As a result, threshold voltage difference resulting from processing factors can be compensated.  
         [0088]     In addition, voltage differences between voltage supply VDD and scan line  10  high level voltage causes an offset at the gate (G) of driving transistor T 3 . If the voltage of scan line  10  (V S,H ) is greater than that of voltage supply VDD, larger data current (I Data ) may be imported by small drive current (I Drive ) at low gray scale to reduce charging time of storage capacitor Cs and parasitical capacitor.  
       EMBODIMENT 5  
       [0089]     Refer to  FIG. 5  for the circuit of a pixel of embodiment 5 in this invention. As the Figure shows, the driving circuit of each pixel on the display panel includes one scan line  10  and one data line  20  as follows:  
         [0000]     Gates (G) of a first scan transistor N 1  and a second scan transistor N 2  connected to one scan line  10  and source (S) connected to a data line  20 .  
         [0090]     Source (S) of a driving transistor N 3  is grounded. Source (S) of one connect transistor N 4  connected to drains (D) of driving transistor N 3  and first scan transistor N 1  and gate (G) connected to one emission line  30 .  
         [0091]     Source (S) of a first switch transistor N 5  connected to first voltage supply V 1  and gate (G) connected to scan line  10 . Source (S) of a second switch transistor N 6  connected to second voltage supply V 2  and gate (G) connected to emission line  30 . The above first scan transistor N 1 , second scan transistor N 2 , driving transistor N 3 , connect transistor N 4 , first switch transistor N 5  and second switch transistor N 6  are NMOS transistors.  
         [0092]     One end of the storage capacitor Cs is connected to the drains of the first switch transistor N 5  and second switch transistor N 6  and the other end connected to drain (D) of second scan transistor N 1  and gate (G) of driving transistor N 3 . Anode of a luminescence device  40  connected to voltage supply VDD and cathode connected to drain of connect transistor N 4 . Luminescence device  40  is an electro-luminescence device (EL device).  
         [0093]     Gate (G) of connect transistor N 4  controlled by nth emission line  30  and current passing through luminescence device  40  determined by gate (G) voltage of driving transistor N 3 .  
         [0094]     Gate (G) of first switch transistor N 5  also controlled by nth scan line  10 . Gate(G) of second switch transistor N 6  controlled by nth emission line  30 .  
         [0095]     It is different from Embodiment 1 in that one end of luminescence device  40  is connected to voltage supply VDD and the other end to connect transistor N 4 . Furthermore, first scan transistor N 1 , second scan transistor N 2 , driving transistor N 3 , connect transistor N 4 , first switch transistor N 5  and second switch transistor N 6  are NMOS transistors.  
         [0096]     Actuation procedures of Embodiment 5 are described as follows:  
         [0097]     1. When the systems scans the nth scan line  10 , the potential is high (V S,H ), leading first scan transistor N 1 , second scan transistor N 2  and first switch transistor N 5  to become on. As the potential of the nth emission line  30  is low (V E,L ), connect transistor N 4  and second switch transistor N 6  are off. Thus, no current will pass through luminescence device  40  to prevent writing mistakes to the storage capacitor Cs.  
         [0098]     One end of storage capacitor Cs connected to gate of driving transistor N 3  links up with data line  20  through second scan transistor N 2  and the other end is connected to first voltage supply V 1  via first switch transistor N 5 . Meanwhile, part of data current (I Data ) of data line  20  charges/discharges storage capacitor Cs through first scan transistor N 1  and first switch transistor N 5 . Gate voltage (V g3 ) of driving transistor N 3  equals voltage of first voltage supply V 1  less that of storage capacitor Cs (V 1 +V CS ).  
         [0099]     Consequently, drive current (I Drive ) passing through driving transistor N 3  is as follows: I Drive =(½)×β×(V gs3 −V th3 ) 2  (β as trans-conductance parameter of driving transistor N 3  and source gate voltage of driving transistor N 3 , V gs3 =V g3 =V 1 +V CS ). Hence, data current (I Data ) equals current passing through storage capacitor Cs (I CS ) plus drive current (I Drive ) passing through driving transistor N 3 ; i.e., I Data =I CS +I Drive .  
         [0100]     2. Voltage of storage capacitor Cs (V CS ) makes drive current (I Drive ) passing through driving transistor N 3  the same as data current (I Data ) of data line  20 ; that is, I Data =I Drive =(½)×β×(V gs3 −V th3 ) 2  and V gs3 =V g3 =V 1 +V CS . Data write is completed at the moment and voltage of storage capacitor Cs (V CS )=(2×I Data /β) (1/2) −(V 1 −V th3 ).  
         [0101]     3. Last, when potential of the nth scan line  10  changes from high (V S,H ) to low (V S,L ), first scan transistor N 1 , second scan transistor N 2  and first switch transistor N 5  are off. Meanwhile, potential of the nth emission line  30  changes from low (V E,L ) to high (V E,H ), leading connect transistor N 4  and second switch transistor N 6  to ON.  
         [0102]     One end of storage capacitor Cs is connected to gate of driving transistor N 3  and the other end to second voltage supply V 2  via second switch transistor N 6 . Thus, gate (G) voltage (V g3 ) of driving transistor N 3  is V 2 +V Cs . Drive current passing through driving transistor N 3  is as follows: I Drive =(½)×β×(V gs3 −V th3 ) 2  and V gs3 =V g3 =V 2 +V CS . Luminescence device  40  is illuminated as drive current (I Drive ) passes through it via connect transistor N 4 .  
         [0103]     In summary, the relationship between data current (I Data ) and drive current (I Drive ) is shown as I Drive =(½)×β×[(2×I Data /β) (1/2) +V 2 −V 1 ] 2 .  
         [0104]     According to the above theory and formula, current output to luminescence device  40  is only related to data current (I Data ) written, not threshold voltage (Vth) of driving transistor N 3 . As a result, threshold voltage difference resulted from process factors can be compensated.  
         [0105]     In addition, voltage difference between second voltage supply V 2  and first voltage supply V 1  causes an offset at the gate of driving transistor N 3 . If voltage of second voltage supply V 2  is less than that of first voltage supply V 1 , larger data current (I Data ) may be imported by small drive current (I Drive ) at low gray scale to reduce the long charging time of storage capacitor Cs and parasitical capacitor.  
       EMBODIMENT 6  
       [0106]     Refer to  FIG. 6  for the circuit of a pixel of embodiment 6 in this invention. As the Figure shows, the driving circuit of each pixel on the display panel includes one scan line  10  and one data line  20 . The driving circuit in this embodiment is about the same as that in Embodiment 5; however, the only difference is source (S) of first switch transistor N 5  connected to emission line  30  instead of first voltage supply V 1  and source (S) of second switch transistor N 6  connected to scan line  10  instead of second voltage supply V 2 .  
         [0107]     Actuation procedures of Embodiment 6 are described as follows:  
         [0108]     1. When the systems scans the nth scan line  10 , the potential is high (V S,H ), leading first scan transistor N 1 , second scan transistor N 2  and first switch transistor N 5  to become on. As the potential of the nth emission line  30  is low (V E,L ), connect transistor N 4  and second switch transistor N 6  are OFF. Thus, no current will pass through luminescence device  40  to prevent writing mistakes to the storage capacitor Cs.  
         [0109]     One end of storage capacitor Cs connected to gate of driving transistor N 3  links up with data line  20  through second scan transistor N 2  and the other end is connected to nth emission line  30  via first switch transistor N 5 . Meanwhile, part of data current (I Data ) of data line  20  charges/discharges storage capacitor Cs through first scan transistor N 1  and first switch transistor N 5 . Gate voltage (V g3 ) of driving transistor N 3  equals low voltage of nth emission line  30  less that of storage capacitor Cs (V CS ); i.e., V g3 =V E,L +V Cs .  
         [0110]     Consequently, drive current (I Drive ) passing through driving transistor N 3  is as follows: I Drive =(½)×β×(V gs3 −V th3 ) 2  (β as trans-conductance parameter of driving transistor N 3  and source gate voltage of driving transistor N 3 , V gs3 =V g3 =V E,L +V CS . Hence, data current (I Data ) equals current passing through storage capacitor Cs (I CS ) plus drive current (I Drive ) passing through driving transistor N 3 ; i.e., I Data =I CS +I Drive .  
         [0111]     2. Voltage of storage capacitor Cs (V CS ) makes drive current (I Drive ) passing through driving transistor N 3  the same as data current (I Data ) of data line  20 ; that is, I Data =I Drive =(½)×β×(V gs3 −V th3 ) 2  and V gs3 =V g3 =V E,L +V CS . Data write is completed at the moment and voltage of storage capacitor Cs, V CS =(2×I Data /β) (1/2) −(V E,L −V th3 ).  
         [0112]     3. Last, when potential of the nth scan line  10  changes from high (V S,H ) to low (V S,L ), first scan transistor N 1 , second scan transistor N 2  and first switch transistor N 5  are off. Meanwhile, potential of the nth emission line  30  changes from low (V E,L ) to high (V E,H ), leading connect transistor N 4  and second switch transistor N 6  to become on.  
         [0113]     One end of storage capacitor Cs is connected to gate (G) of driving transistor N 3  and the other end to scan line  10  via second switch transistor N 6 . Thus, gate (G) voltage (V g3 ) of driving transistor N 3  is V S,L +V Cs . Drive current passing through driving transistor N 3  is as follows: I Drive =(½)×β×(V gs3 −V th3 ) and V gs3 =V g3 =V S,L +V CS . Luminescence device  40  is illuminated as drive current (I Drive ) passes through it via connect transistor N 4 .  
         [0114]     In summary, the relationship between data current (I Data ) and drive current (I Drive ) is shown as I Drive =(½)×β×[(2×I Data /β) (1/2) +V S,L −V E,H ] 2 .  
         [0115]     According to the above theory and formula, current output to luminescence device  40  is only related to data current (I Data ) written and not the threshold voltage (Vth) of driving transistor N 3 . As a result, threshold voltage difference resulted from process factors can be compensated.  
         [0116]     In addition, voltage differences between scan line  10  (V S,L ) low level voltage and emission line  30  (V E,L ) low level voltage causes an offset at the gate of driving transistor N 3 . If the voltage of scan line  10  (V S,L ) is less than that of emission line  30  (V E,L ), larger data current (I Data ) may be imported by small drive current (I Drive ) at low gray scale to reduce the long charging time of storage capacitor Cs and parasitical capacitor.  
       EMBODIMENT 7  
       [0117]     Refer to  FIG. 7  for the circuit of a pixel of embodiment 7 in this invention. As the Figure shows, the driving circuit of each pixel on the display panel includes one scan line  10  and one data line  20 . The driving circuit in this embodiment is about the same as that in Embodiment 5; however, the only difference is source (S) of first switch transistor N 5  grounded instead of connecting to first voltage supply V 1  and source (S) of second switch transistor T 6  still connected to second voltage supply V 2  as in Embodiment 5.  
         [0118]     Actuation procedures of Embodiment 7 are described as follows:  
         [0119]     1. When the systems scans the nth scan line  10 , the potential is high (V S,H ), leading first scan transistor N 1 , second scan transistor N 2  and first switch transistor N 5  to ON. As the potential of the nth emission line  30  is low (V E,L ), connect transistor N 4  and Second switch transistor N 6  are off. Thus, no current will pass through luminescence device  40  in this phase to prevent writing mistakes to the storage capacitor Cs.  
         [0120]     One end of storage capacitor Cs connected to gate of driving transistor N 3  links up with data line  20  through second scan transistor N 2  and the other end is grounded via first switch transistor N 5 . Meanwhile, part of data current (I Data ) of data line  20  charges/discharges storage capacitor Cs through first scan transistor N 1  and first switch transistor N 5 . Gate voltage (V g3 ) of driving transistor N 3  equals voltage of storage capacitor Cs (V CS ); i.e., V g3 =0+V Cs .  
         [0121]     Consequently, drive current (I Drive ) passing through driving transistor N 3  is as follows: I Drive =(½)×β×(V gs3 −V th3 ) 2  (β as trans-conductance parameter of driving transistor N 3  and source gate voltage of driving transistor N 3 , V gs3 =V g3 =0+V CS . Hence, data current (I Data ) equals current passing through storage capacitor Cs (I CS ) plus drive current (I Drive ) passing through driving transistor N 3 ; i.e., I Data =I CS +I Drive .  
         [0122]     2. Voltage of Storage Capacitor Cs (V CS ) makes drive current (I Drive ) passing through Driving transistor N 3  the same as data current (I Data ) of Data Line  20 ; that is, I Data =I Drive =(½)×β×(V gs3 −V th3 ) 2  and V gs3 =V g3 =0+V CS . Data write is completed at the moment and voltage of storage capacitor Cs, V CS =(2×I Data /β) (1/2) −(0−V th3 ).  
         [0123]     3. Lastly, when the potential of the nth scan line  10  changes from high (V S,H ) to low (V S,L ), first scan transistor N 1 , second scan transistor N 2  and first switch transistor N 5  are off. Meanwhile, potential of the nth emission line  30  changes from low (V E,L ) to high (V E,H ), leading connect transistor N 4  and second switch transistor N 6  to become on.  
         [0124]     One end of storage capacitor Cs is connected to gate (G) of driving transistor N 3  and the other end to second voltage supply V 2  via second switch transistor N 6 . Thus, gate voltage (V g3 ) of driving transistor N 3  is V 2 +V Cs . Drive current passing through driving transistor N 3  is as follows: I Drive =(½)×β×(V gs3 −V th3 ) 2  and V gs3 =V g3 =V 2 +V CS . Luminescence device  40  is illuminated as drive current (I Drive ) passes through it via connect transistor N 4 .  
         [0125]     In summary, the relationship between data current (I Data ) and drive current (I Drive ) is shown as I Drive =(½)×β×[(2×I Data /β) (1/2) +V 2 −0] 2 =(½)×β×[(2×I Data /β) (1/2) +V 2 ] 2 .  
         [0126]     According to the above theory and formula, current output to luminescence device  40  is only related to data current (I Data ) written, not threshold voltage (Vth) of driving transistor N 3 . As a result, threshold voltage difference resulted from process factors can be compensated.  
         [0127]     In addition, voltage difference between second voltage supply V 2  and grounding ( 0 ) causes an offset at the gate of driving transistor N 3 . If voltage of second voltage supply V 2  is less than that of grounding ( 0 ), larger data current (I Data ) may be imported by small drive current (I Drive ) at low gray scale to reduce long charging time of storage capacitor Cs and parasitical capacitor.  
       EMBODIMENT 8  
       [0128]     Refer to  FIG. 8  for the circuit of a pixel of embodiment 8 in this invention. As the Figure shows, the driving circuit of each pixel on the display panel includes one scan line  10  and one data line  20 . The driving circuit in this embodiment is about the same as that in Embodiment 6; however, the only difference is source (S) of first switch transistor N 5  is grounded instead of connecting to emission line  30  and source (S) of second switch transistor T 6  still connected to scan line  10  as in Embodiment 6.  
         [0129]     Actuation procedures of Embodiment 8 are described as follows:  
         [0130]     1. When the systems scans the nth scan line  10 , the potential is high (V S,H ), leading first scan transistor N 1 , second scan transistor N 2  and first switch transistor N 5  to become on. As the potential of the nth emission line  30  is low (V E,L ), connect transistor N 4  and second switch transistor N 6  are OFF. Thus, no current will pass through luminescence device  40  in this phase to prevent writing mistakes to the storage capacitor Cs.  
         [0131]     One end of storage capacitor Cs connected to gate of driving transistor N 3  links up with data line  20  through second scan transistor N 2  and the other end is grounded via first switch transistor N 5 . Meanwhile, part of data current (I Data ) of data line  20  charges/discharges storage capacitor Cs through first scan transistor N 1  and first switch transistor N 5 . Gate voltage (V g3 ) of driving transistor N 3  equals voltage of storage capacitor Cs (V CS ); i.e., V g3 =0+V Cs .  
         [0132]     Consequently, drive current (I Drive ) passing through driving transistor N 3  is as follows: I Drive =(½)×β×(V gs3 −V th3 ) 2  (β as trans-conductance parameter of driving transistor N 3  and source gate voltage of driving transistor N 3 , V gs3 =V g3 =0+V CS . Hence, data current (I Data ) equals current passing through storage capacitor Cs (I CS ) plus drive current (I Drive ) passing through driving transistor N 3 ; i.e., I Data =I CS +I Drive .  
         [0133]     2. Voltage of storage capacitor Cs (V CS ) makes drive current (I Drive ) passing through driving transistor N 3  the same as data current (I Data ) of data line  20 ; that is, I Data =I drive =(½)×β×(V gs3 −Vth 3 ) 2  and V gs3 =V g3 =0+V CS .  
         [0134]     Data write is completed at the moment and voltage of Storage Capacitor Cs, V CS =(2×I Data /β) (1/2) −(0−V th3 ).  
         [0135]     3. Lastly, when potential of the nth Scan Line  10  changes from high (V S,H ) to low (V S,L ), first scan transistor N 1 , second scan transistor N 2  and first switch transistor N 5  are OFF. Meanwhile, potential of the nth emission line  30  changes from low (V E,L ) to high (V E,H ), leading connect transistor N 4  and second switch transistor N 6  to ON.  
         [0136]     One end of storage capacitor Cs is connected to gate of driving transistor N 3  and the other end to nth scan line  10  via second switch transistor N 6 . Thus, gate voltage (V g3 ) of driving transistor N 3  is V S,L +V CS . Drive current passing through driving transistor N 3  is as follows: I Drive =(½)×β×(V gs3 −V th3 ) 2  and V gs3 =V g3 =V S,L +V CS . Luminescence device  40  is illuminated as drive current (I Drive ) passes through it via connect transistor N 4 .  
         [0137]     In summary, the relationship between data current (I Data ) and drive current (I Drive ) is shown as I Drive =(½)×β×[(2×I Data /β) (1/2) +V S,L −0] 2 =(½)×β×[(2×I Data /β) (1/2) +V S,L ] 2 .  
         [0138]     According to the above theory and formula, current output to luminescence device  40  is only related to data current (I Data ) written, not threshold voltage (Vth) of driving transistor N 3 . As a result, threshold voltage difference resulted from process factors can be compensated.  
         [0139]     In addition, voltage difference between scan line  10  (V S,L ) low level voltage and grounding (V=0) causes an offset at the gate of driving transistor N 3 . If voltage of scan line  10  (V S,L ) is less than that of grounding ( 0 ), larger data current (I Data ) may be imported by small drive current (I Drive ) at low gray scale to reduce long charging time of storage capacitor Cs and parasitical capacitor.  
         [0140]     To conclude, the Active Matrix Display Driving Circuit presented by this invention has the following advantages:  
         [0141]     1. In comparison with the U.S. Pat. Nos. 6,373,454 and 6,229,506, the ratio of input current to output current in this invention can be shown as: output current=A×input current+B. It solves long charging/discharging time efficiently.  
         [0142]     2. In comparison with the U.S. Pat. Nos. 6,359,605, 6,501,466 and 6,535,185, the correlation between input current and output current (output current=A×input current+B) is based on capacitive coupling, not the structure of current mirror. The issue of matching TFT elements is not considered necessary. Consequently, influential process factors are reduced and the yield of panels increases.  
         [0143]     3. In comparison with the above patented circuits, capacitive coupling exactly ensures source gate voltage (Vgs) of the driving transistor be smaller than threshold voltage (Vth), which generates no current for the driving transistor. In this way, the luminescence device won&#39;t be illuminated and a higher contrast is developed.  
         [0144]     4. To compare with the thesis published by Samsung with the subject of A New Current Programmable Pixel Structure for large-Size and High-Resolution AMOLEDs (International Display Workshops 2002 (IDW 2002)):  
         [0145]     a. As only one capacitor is applied to achieve the correlation (output current=A×input current+B) in this invention, voltage of capacitive coupling does not change with relative values of two capacitors due to process or/and layout effect, and driving transistor affect the driving current. Consequently, influential process factors are reduced and the yield of panels increases.  
         [0146]     b. As one capacitor and two levels are used to achieve the correlation (output current=A×input current+B) in this invention instead of capacitive coupling by two capacitors, precision of the capacitor is not required. Hence, influential process factors are reduced and the yield of panels increases.  
         [0147]     c. Since merely one capacitor is utilized to achieve the correlation (output current=A×input current+B) in this invention, a higher aperture ratio is developed.  
         [0148]     5. In comparison with general voltage driving circuits, this invention is a current driving circuit that solves the problem of different properties of TFT elements and compensates threshold voltage (Vth) difference and mobility automatically.  
         [0149]     6. To compare with voltage driving circuits, the current driving circuit in this invention can solve the IR drop problem of the voltage supply line.