Abstract:
An image sensor has a core structure with a convex surface, such as a sphere or a tube. The image sensor also has an interconnect layer that is adhered to the convex surface of the core structure, and a photo-sensing layer that is connected to the interconnect layer. The photo-sensing layer collects photo-information, while the interconnect layer provides an electrical interface between the photo-sensing layer and the outside world.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an image sensor and, more particularly, to a convex image sensor and a method of forming the sensor. 
     2. Description of the Related Art 
     The rigidity of a semiconductor wafer (the resistance of the wafer to deformation) is reduced significantly as the thickness of the wafer is reduced. For example, when the thickness of a semiconductor wafer is approximately one mil, the wafer can be deformed. One application of a very thin wafer is as the photo-sensing element of an optical image sensor. 
       FIG. 1  shows a cross-sectional diagram that illustrates a prior art optical image sensor  100 . As shown in  FIG. 1 , optical image sensor  100  includes a very thin wafer  110 , and an array of photodiodes and associated photo-sensing circuitry  112  that are formed on wafer  110 . Imager  100  also includes a base structure  114  that has a concave surface  116  that supports wafer  110 . 
     In addition, image sensor  100  also includes a single low-cost lens  120  that focuses incoming light  122  on a curved focal plane  124 . Curved focal plane  124 , in turn, has a convex outer shape that approximately matches the shape of concave surface  116 . As a result, the non-rigid structure of a very thin wafer allows the array of photodiodes to be placed on the curved focal plane  124  of low-cost lens  120 , thereby forming a low-cost imager with a substantially improved optical quality. 
     SUMMARY OF THE INVENTION 
     The present invention provides a convex image sensor and a method of forming the sensor. The image sensor includes a core structure that has a convex surface, and an interconnect layer that is adhered to the convex surface of the core structure. The interconnect layer routes voltages and signals from a surface region to an external connection region. 
     The image sensor also includes a plurality of solder bumps, and a photo-sensing layer that is connected to the surface region of the interconnect layer via the plurality of solder bumps. The photo-sensing layer has a plurality of photocells that output voltages that correspond to an intensity of light received by the photocells. 
     The present invention also includes a method of forming an image sensor. The method includes the steps of forming a core structure having a convex surface, and adhering an interconnect layer to the convex surface of the core structure. The interconnect layer routes voltages and signals from a surface region to an external connection region. In addition, the method also includes the step of connecting a photo-sensing layer to the surface region of the interconnect layer. The photo-sensing layer has a plurality of photocells that output voltages that correspond to an intensity of light received by the photocells. 
     A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional diagram illustrating a prior art optical image sensor  100 . 
         FIGS. 2A-2B  are views illustrating an example of a spherical image sensor  200  in accordance with the present invention.  FIG. 2A  is a perspective view, and  FIG. 2B  is a cross-sectional view. 
         FIG. 3  is a plan view illustrating an example of a photo-sensing layer  300  in accordance with the present invention. 
         FIGS. 4A-4B  are views illustrating an example of a portion of a photocell formed in a photo-sensing section  400  in accordance with the present invention.  FIG. 4A  is a bottom view, while  FIG. 4B  is a cross-sectional view taken along line  4 B— 4 B in FIG.  4 A. 
         FIGS. 5A-5J  are cross-sectional views illustrating a method of forming a conductive region in accordance with the present invention. 
         FIG. 6  is a plan view illustrating an example of an interconnect layer  600  in accordance with the present invention. 
         FIG. 7  is a cross-sectional view illustrating an example of an interconnect section  700  in accordance with the present invention. 
         FIGS. 8A-8B  are perspective views illustrating a method of forming an imaging sphere  800  in accordance with the present invention. 
         FIG. 9  is a perspective view illustrating an example of a tubular image sensor  900  in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is directed to convex image sensors, such as spherical and tubular sensors.  FIGS. 2A-2B  show views that illustrate an example of a spherical image sensor  200  in accordance with the present invention.  FIG. 2A  shows a perspective view, while  FIG. 2B  shows a cross-sectional view. 
     As shown in  FIGS. 2A-2B , spherical image sensor  200  includes a core structure  210  that has a convex surface  212 , and an interconnect layer  214  that is adhered to the convex surface  212  of core structure  210 . Interconnect layer  214  routes voltages and signals from a surface region  214 S to an external connection region  214 E. 
     In addition, image sensor  200  includes a photo-sensing layer  216  that is connected to the surface region  214 S of interconnect layer  214  via a number of solder bumps  218 . (In addition to solder, solder bumps  218  can alternately be implemented with other adhesives that electrically and mechanically connect photo-sensing layer  216  to interconnect layer  214 .) Photo-sensing layer  216  includes a number of photocells  220  that output voltages that correspond to the intensity of light received by the photocells  220 . 
       FIG. 3  shows a plan view that illustrates an example of a photo-sensing layer  300  in accordance with the present invention. As shown in  FIG. 3 , photo-sensing layer  300  includes a series of adjacent photo-sensing sections  310 . When adjacent photo-sensing sections  310  are connected together, and the first and last photo-sensing sections  310  are connected together, the connected sections  310  form a sphere. 
     Each photo-sensing section  310  has a maximum width line W 1 , and a centerline C 1  that passes through the center of the maximum width line W 1 , and is normal to, and longer than, the maximum width line W 1 . In addition, each section  310  has a curved edge that runs from a point P 1  at an end of the maximum width line W 1 , to a point P 2  at an end of the centerline C 1 . 
     Each photo-sensing section  310  also includes an array of photocells  312  that convert incident light into voltages that represent the intensity of the light that was received. The photocells  312  can be implemented as, for example, active pixel sensor cells.  FIGS. 4A-4B  show views that illustrate an example of a portion of a photocell formed in a photo-sensing section  400  in accordance with the present invention.  FIG. 4A  shows a bottom view, while  FIG. 4B  shows a cross-sectional view taken along line  4 B— 4 B in FIG.  4 A. 
     As shown in  FIGS. 4A-4B , photo-sensing section  400  includes a p-type semiconductor wafer  410  with a top surface  412  and a bottom surface  414 , and a n+ region  416  that is formed in wafer  410 . Wafer  410  is very thin and can be, for example, approximately one mil thick. Together, n+ region  416  and p− wafer  410  form a n+/p− photodiode  418 . (The present invention can be utilized with other photodiode structures, including color photodiodes that use a number of vertically-stacked photodiodes.) 
     In addition, photo-sensing section  400  also includes a n+ drain region  422  that is formed in p− wafer  410 , and a channel region  424  that is located between n+ region  416  and drain region  422 . Section  400  further includes a gate oxide layer  426  that is formed on wafer  410  over channel region  424 , and a gate  428  that is formed on gate oxide layer  426  over channel region  424 . Together, n+ region  416 , n+ drain region  422 , channel region  424 , gate oxide layer  426 , and gate  428  form a NMOS transistor  430 . 
     In addition, photo-sensing section  400  includes a layer of isolation material  432  that is formed on the top surface  412  of wafer  410 , and a conductive region  434  that extends through wafer  410  and isolation material  432 . Isolation material  432  has a top surface  436 , while conductive region  434 , which can include metal, has a bottom surface  440  and a top surface  442 . 
     In the example of  FIGS. 4A-4B , the bottom surface  414  of wafer  410  and the bottom surface  440  of conductive region  434  lie substantially in the same plane. In addition, the top surface  436  of isolation material  432  and the top surface  442  of conductive region  434  lie substantially in the same plane. Further, a solder bump  444  is connected to bottom surface  440  of conductive region  434 . 
     Photo-sensing section  400  additionally includes a number of contacts  446 , including contacts  446 A and  446 B, that are formed through isolation layer  432 . In the example of  FIGS. 4A-4B , contacts  446 A and  446 B are formed through isolation layer  432  to make an electrical connection with gate  428  and n+ drain region  422 , respectively. 
     Further, section  400  includes a number of metal-1 traces  450 , including metal-1 traces  450 A and  450 B, that are formed on isolation layer  432  to make an electrical connection with contacts  446 . In the example of  FIGS. 4A-4B , metal-1 trace  450 A is connected to contact  446 A, while metal-1 trace  450 B is connected to contact  446 B and conductive region  434 . (Metal-1 trace  450 B is but one example of connecting drain region  422  to conductive region  434 . A metal-2 trace or a trace from any subsequent metal layer can alternately be used with interconnecting vias.) 
       FIGS. 5A-5J  show cross-sectional views that illustrate a method of forming a conductive region in accordance with the present invention. As shown in  FIGS. 5A-5J , the method, which utilizes a conventionally formed wafer  510  that has a doped region  512 , begins by forming a layer of masking material  514  on wafer  510 . Once formed, material  514  is patterned to expose a number of trench areas on the top surface of wafer  510 . 
     Referring to  FIG. 5B , once masking material  510  has been formed, the trench area of wafer  510  is anisotropically etched until a trench  516  has been formed in wafer  510 . Trench  516  can be formed to have a variety of shapes by utilizing both anisotropic and isotropic etches. 
     Trench  516  is formed to have a depth D that is greater than a final thickness of wafer  510 . For example, if the final thickness of wafer  510  is one mil (1 mil=25.4 microns), then trench  516  is formed to have depth D that is greater than one mil. Following the etch, masking material  514  is removed. 
     Referring to  FIG. 5C , after masking material  514  has been removed, a layer of insulation material  520  is formed over wafer  510 , including doped region  512  and trench  516 . Insulation layer  520  can include, for example, a first layer of oxide approximately 1000 Å thick that is formed over wafer  510 , and a layer of polysilicon-doped spin-on-glass (PSG) approximately 4000 Å thick that is formed on the first oxide layer. In addition, material  520  can also include a second layer of oxide approximately 8000 Å thick that is formed on the PSG layer. The first and second layers of oxide, in turn, can be formed using plasma-enhanced chemical-vapor-deposition (PECVD) processes. 
     Following the formation of insulation layer  520 , a layer of masking material  522  is formed on insulation layer  520 . As shown in  FIG. 5C , material  522  is then patterned to expose doped region  512  and trench  516 . Referring to  FIG. 5D , once masking material  522  has been patterned, the exposed regions of insulation material  520  are etched until insulation material  520  is removed from the surfaces of doped region  512  and trench  516 . The etch forms a contact opening  524  in insulation layer  520  that exposes doped region  512  and a trench opening  526  that exposes trench  516 . Following the etch, masking material  522  is removed. 
     Next, as shown in  FIG. 5E , a layer of contact protection material  530  is deposited on doped region  512 , trench  516 , and insulation layer  520 . After material  530  has been deposited, wafer  510  is heated to a low temperature (e.g., 250-400° C.) in a neutral ambient, such as N2, for a predetermined period of time. 
     As shown in  FIG. 5F , the heat cycle causes the contact protection material  530  that is in contact with doped region  512  and trench  516  to react with the silicon and form a layer of metal silicide  532  on the surface of doped region  512  and trench  516 . For example, metal silicide layer  532  can be implemented with platimum silicide, cobalt silicide, or titanium silicide. The unreacted contact protection material  530  (the material in contact with insulation layer  520 ) is then removed. 
     After metal silicide layer  532  has been formed on the surfaces of doped region  512  and trench  516 , a layer of diffused barrier material  534  is formed on metal silicide layer  532  and insulation layer  520 . Diffusion barrier material  534  can be implemented with, for example, titanium, titanium-tungsten, titanium nitride, and tungsten. Following this, a layer of electrically-conductive contact material  536 , such as aluminum, is formed on layer  534 . 
     As shown in  FIG. 5G , once contact material  536  has been formed, contact material  536  and then diffused barrier material  534  are planarized to remove material  534  from the top surface of insulation layer  520 . Materials  534  and  536  can be planarized using, for example, chemical-mechanical polishing (CMP) and etch back techniques. The etch forms a conductive contact  540  that makes an electrical connection with doped region  512 . The etch also forms a conductive contact  542  that extends well into wafer  510 . 
     Referring to  FIG. 5H , following the etch, a first layer of metal (metal-1)  544  is formed on insulation layer  520 , contact  540 , and contact  542 . After metal-1 layer  544  has been deposited, a first metal trace mask  546  is formed and patterned on metal-1 layer  544 . Referring to  FIG. 5I , following the patterning of mask  546 , the exposed portion of metal-1 layer  544  is etched until metal-1 layer  544  is removed from the surface of the underlying insulation layer  520 . Mask  546  is then removed. The etch defines a first metal-1 trace  548  and exposes regions of insulation layer  520 . 
     Referring to  FIG. 5J , after a number of additional interconnecting metal layers and vias are formed (not shown), the bottom side of wafer  510  is ground down so that wafer  510  has a thickness T that is less than the depth D of trench  516 . For example, current-generation back grinding equipment can reduce the thickness T to approximately one mil. At this thickness, wafer  510  can be deformed. The back grinding exposes contact  542  on the bottom side of wafer  510 . Once contact  542  has been exposed, solder bumps  550  are then formed on contact  542  adjacent to the bottom side of wafer  510 . (In addition to solder, solder bumps  550  can alternately be implemented with other adhesives that provide an electrical and mechanical connection between photo-sensing layer  216  and interconnect layer  214 .) 
       FIG. 6  shows a plan view that illustrates an example of an interconnect layer  600  in accordance with the present invention. As shown in  FIG. 6 , interconnect layer  600  includes a series of adjacent interconnect sections  610 . When adjacent interconnect sections  610  are connected together, and the first and last interconnect sections  610  are connected together, the connected sections  610  form a sphere. 
     Each interconnect section  610  is similarly shaped as photo-sensing section  310 , and has a maximum width line W 2 , and a centerline C 2  that passes through the center of the maximum width line W 2 , and is normal to, and longer than, the maximum width line W 2 . In addition, each section  610  has a curved edge that runs from a point P 1  at an end of the maximum width line W 2 , to a point P 2  at an end of the centerline C 2 . 
       FIG. 7  shows a cross-sectional view that illustrates an example of an interconnect section  700  in accordance with the present invention. As shown in  FIG. 7 , interconnect section  700  includes a semiconductor wafer  710  with a top surface  712  and a bottom surface  714 . Wafer  710  is very thin and can be, for example, approximately one mil thick. 
     As further shown in  FIG. 7 , interconnect section  700  also includes a layer of isolation material  716  that is formed on the top surface  712  of wafer  710 , and a number of metal-1 traces, including a metal-1 trace  720 , that are formed on isolation layer  716 . (Isolation layer  716  can optionally be omitted.) 
     Interconnect section  700  additionally includes a layer of isolation material  722  is that formed on metal-1 trace  720 , and a number of vias  724  that are formed through isolation layer  722  to make an electrical connection with the metal-1 traces, such as metal-1 trace  720 . Further, a number of metal-2 traces, including metal-2 traces  726  and  728 , are formed on isolation layer  722  to make electrical connections with vias  724 . 
     Further, interconnect section  700  includes a layer of isolation material  732  is that formed on metal-2 traces  726  and  728 , and a number of vias  734  that are formed through isolation layer  732  to make an electrical connection with the metal-2 traces, such as metal-2 traces  726  and  728 . Further, a number of metal pads, including pads  736  and  738 , are formed on isolation layer  732  to make electrical connections with vias  734 . 
       FIGS. 8A-8B  show perspective views that illustrate a method of forming an imaging sphere  800  in accordance with the present invention. As shown in  FIG. 8 , the method, which utilizes a spherical core  810 , begins by adhering an interconnect section  812  to core  810 . Additional interconnect sections  812  are adhered to core  810  until core  810  is covered. (Adjacent interconnect sections  812  can touch each other or be spaced apart from each other.) 
     Following this, as shown in  FIG. 8B , a photo-sensing section  814  is connected to an interconnect section  812  so that the solder bumps on photo-sensing section  814  match the pads on interconnect section  812 . Additional photo-sensing sections  814  are connected to the remaining interconnect sections  812  until the interconnects sections  812  are covered. (Adjacent photo-sensing sections  814  can touch each other or be spaced apart from each other, depending on the interconnect section  812 .) 
       FIG. 9  shows a perspective view that illustrates an example of a tubular image sensor  900  in accordance with the present invention. As shown in  FIG. 9 , tubular image sensor  900  includes a tubular core  910 , and an inner interconnect layer  912  that is adhered to the convex surface of tubular core  910 . Interconnect layer  912  routes voltages and signals from a surface region  912 S to an external connection region  912 E. 
     In addition, image sensor  900  includes a photo-sensing layer  914  that is connected to the surface region  912 S of interconnect layer  912  via a number of solder bumps  916 . (In addition to solder, solder bumps  916  can alternately be implemented with other adhesives that electrically and mechanically connect photo-sensing layer  914  to interconnect layer  912 .) Photo-sensing layer  914  includes a number of photocells  918  that output voltages that correspond to the intensity of light received by the photocells  918 . 
     Photo-sensing layer  914  and interconnect layer  912  are the same as photo-sensing layer  216  and interconnect layer  214  except that photo-sensing layer  914  and interconnect layer  912  are formed in square or rectangular sheets. Interconnect layer  912  is formed around tubular core  910  by adhering a single sheet around tubular core  910 . Alternately, tubular core  910  can be covered with multiple sheets of interconnect layer  912 , such as two sheets that each cover approximately one-half of the tubular surface. 
     It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.