Abstract:
The present invention provides a method in making a pillar-type structure (e.g. a storage node of stack capacitor) on a semiconductor substrate. By depositing a conductive polysilicon electrode layer, a nitride layer and a silicon layer on the substrate, and then required oxide pillars are formed in the silicon layer to act as a mask for etching the conductive polysilicon electrode layer.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method in making a pillar-type structure on a semiconductor substrate, and more particularly to a method in making pillar-type capacitor node on a silicon substrate. 
     BACKGROUND OF THE INVENTION 
     In U.S. Pat. No. 5,482,885 Water Lur et al. had provided a method to form a capacitor in a DRAM cell by depositing a conductive polysilicon electrode layer on the substrate. Oxide lines are then formed on the polysilicon layer. Using the oxide lines as a mask to etch the polysilicon layer, pillar-type capacitor node is formed in the plolysilicon electrode layer. 
     The present application however provides a different way to form a pillar-type capacitor node on the silicon substrate. 
     OBJECT OF THE INVENTION 
     It is therefore an object of the present invention to provide a method in making a pillar-type structure on semiconductor substrate, by depositing sequentially a conductive polysilicon electrode layer, a nitride layer and a silicon layer on the substrate, and then forming required oxide pillars in the silicon layer to act as a mask for etching the conductive polysilicon electrode layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows that a conductive polysilicon electrode layer  3 , a nitride layer  4  and a first silicon layer  5  are formed on the substrate  1 . 
     FIG. 2 shows that the first silicon layer  5  is etched being divided into a plurality of regions to be spaced apart by a distance of  5 X, and each region has a width of  3 X. 
     FIG. 3 shows that a doped SiO 2  layer  6  of thickness X is deposited. 
     FIG. 4 shows that etchingback process is conducted to form spacers  6  abutting the first silicon layer  5 . 
     FIG. 5 shows that the remained first silicon layer  5  is removed. 
     FIG. 6 shows that a second silicon layer  7  of thickness X is deposited. 
     FIG. 7 shows that etchingback process is conducted to form spacers  7  abutting the spacers  6 . 
     FIG. 8 shows that a doped SiO 2  layer  8  is deposited. 
     FIG. 9 shows that etchingback process is conducted on the SiO 2  layer  8  to form spacer  9  and stud  10 . 
     FIG. 10 shows than the spacer  7  is removed so that the distance between the remained oxide pillars is X. 
     FIG. 11 shows that an etching process is conducted on the Si 3 N 4  layer  4  and the polysilicon layer  3  below the spacer  7 . 
     FIG. 12 shows that the remained spacer  6 , spacer  9 , stud  10  and the Si 3 N 4  layer  4  are removed. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, a semiconductor silicon substrate  1  is provided first to form a diffusion region  11  (e.g. a source region) therein, then a CVD process is conducted to form a dielectric layer  2  on the semiconductor silicon substrate  1 , followed by a photolithography process and an anisotropic plasma etching process to remove part of the dielectric layer  2 , so as to form a recess to expose the diffusion region  11  of the silicon substrate  1 . 
     Next, a CVD process is conducted again to deposit a polysilicon layer  3  of thickness 3000˜8000 Å to cover the dielectric layer  2  and fill up the recess, then a CVD process is conducted for form a Si 3 N 4  layer  4  of thickness 300˜800 Å on the polysilicon layer  3 . 
     A first silicon layer  5  of thickness 2500˜5000 Å is then deposited on the Si 3 N 4  layer  4 . The first silicon layer  5  can be a doped polysilicon layer, an undoped polysilicon layer or an amorphous silicon layer, but preferably using doped polysilicon. 
     Referring to FIG. 2, which just shows the Si 3 N 4  layer  4  and the first silicon layer  5  to simplify the drawing, but the silicon substrate  1 , the dielectric layer  2  and the polysilicon layer  3  are still exist below the Si 3 N 4  layer  4 . As shown in FIG. 2, a photolithography process and an etching process are employed to etch the first silicon layer  5  to expose the Si 3 N 4  layer  4  intermittently such that the first silicon layer  5  is divided into a plurality of regions to be spaced apart by a distance of  5 X, and each region has a width of  3 X (X for example is between 100˜500 Å). 
     Referring to FIG. 3, a doped SiO 2  layer  6  of thickness X (100˜500 Å) is deposited as shown, and then etched back by fluorine plasma to form spacers  6  abutting the first silicon layer  5 , as shown in FIG.  4 . 
     Referring to FIG. 5, the remained first silicon layer  5  is removed by isotropic etching in SF 6  gas plasma, so that the distance between the spacers  6  is  3 X. 
     Referring to FIG. 6, a second silicon layer  7  of thickness X (100˜500 Å) is deposited and then etched back to form spacers  7  abutting the spacers  6 , as shown in FIG.  7 . The distance between the spacers  7  is also X. The second silicon layer  5  can be a doped polysilicon layer, an undoped polysilicon layer or an amorphous silicon layer, but preferably using doped polysilicon. 
     Referring to FIG. 8, a doped SiO 2  layer  8  is deposited to cover everything above the Si 3 N 4  layer  4  and fill up the spaces between spacer  7 . 
     Referring to FIG. 9, by etchingback the doped SiO 2  layer  8  to form spacers  9  of thickness X (100˜500 Å) abutting the the spacers  7  and form studs  10  between the the spacers  7 , as shown in the figure. 
     Referring to FIG. 10, the spacers  7  are removed by isotropic etching in SF 6  gas plasma so that the distance between the remained oxide pillars is X (100˜500 Å). 
     Referring to FIG. 11, anisotropic etching the Si 3 N 4  layer  4  and the polysilicon layer  3  below the spacers  7  to a depth without exposing the oxide layer  2  on said semiconductor silicon substrate  1 . 
     Referring to FIG. 12, removing the spacers  6 , the spacers  9 , the studs  10  and the Si 3 N 4  layer  4  that remained to expose the polysilicon layer  3 , a pillar-type capacitor node is formed on the silicon substrate  1 . 
     The scope of the present invention depends only upon the following Claims, and is not limited by the above embodiment.