Abstract:
A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.

Description:
[0001]    This patent application is a continuation of U.S. patent application Ser. No. 13/568,865 filed on Aug. 7, 2012, which is a continuation of U.S. patent application Ser. No. 13/493,854 filed on Jun. 11, 2012 and now patented as U.S. Pat. No. 8,253,488, which is a continuation of U.S. patent application Ser. No. 12/799,870 filed on May 4, 2010 and now patented as U.S. Pat. No. 8,198,940, which claims priority to U.S. Provisional Patent Application No. 61/215,303 filed on May 4, 2009. Each of these applications is herein incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of Invention 
         [0003]    This invention is related to signal gain control and in particular self-calibrating gain control to correct for signal errors. 
         [0004]    2. Description or Related Art 
         [0005]    In signal receiving circuits, such as with RF receivers, it is meaningful to have automatic gain control to insure that a constant amplitude signal is available for processing by subsequent circuitry. Error signals in the gain control circuitry often cause abrupt changes in gain compared to what is expected and provide fluctuations in the amplified signal. These unexpected changes in the gain and the resulting changes in signal strength to subsequent downstream signal processing can be disruptive to the quality of the signal results, as could be seen with RF communications between cellular phones. 
         [0006]    U.S. Pat. No. 7,555,263 B1 (Rofougaran et al.) is directed to a self-testing unit that is used to determine gain, frequency characteristics, selectivity, noise floor, and distortion behavior of a receiver and transmitter. U.S. Pat. No. 7,352,310 (Mori et al.) and U.S. Pat. No. 7,292,169 B2 (Mori et al.) is directed to a receiver comprising an A/D converter, a controller and a variable gain amplifier that adjusts the gain of the amplifier based on an m-bit and a n-bit digital signal. U.S. Pat. No. 7,222,037 B2 (Mushirahad et al.) is directed to a method of automatic gain control in both the analog and digital domain for an incoming analog signal. U.S. Pat. No. 7,215,763 B1 (Keller et al.) discloses a method for configuring a transceiver for providing data communications via residential wiring and uses a received pulse signal to adjust gain of an input circuit. In U.S. Pat. No. 6,952,132 B2 (Bhattacharjee et al.) a system and method is directed to provide automatic gain control through analog and digital techniques where overall gain is monitored by a power detection circuit. U.S. Pat. No. 6,897,729 B1 (Jin et al.) is directed to an RF low noise amplifier with gain control through control of a bias circuit to generate a bias current for the amplifier to vary gain. 
         [0007]    U.S. Pat. No. 6,784,738 B1 (Jin et al.) is directed to an amplifier to amplify an RF signal wherein the amplifier transconductance is controlled to reduce variations in gain of the amplifier under changing conditions. In U.S. Pat. No. 6,498,927 B2 (Kang et al.) an apparatus and method is directed to controlling gain in a communication system between a receiver and a baseband modem. U.S. Pat. No. 6,417,730 (Segallis et al.) is directed to an automatic gain control system comprising at least one variable gain component and a sensor for sensing signal amplitude from at least one variable gain component. In U.S. Pat. No. 6,191,626 B1 (Pryshy et al.) a method and apparatus is directed to compensating input threshold variations in input buffers by applying a bias to an RC calibration network. U.S. Pat. No. 6,100,761 (Ezell) is directed to a linear variable gain low noise amplifier, wherein gain is controlled through segmented resistor having controllable components. U.S. Pat. No. 5,917,865 (Kopmeiners et al.) is directed to an automatic gain control in which an analog amplifier is controlled by a digital signal from a digital gain control circuit. U.S. Patent Application Publication 2001/0022821 (Ichihara) is directed to an amplitude deviation correction circuit that corrects amplitude deviation between an I and a Q signal. 
       SUMMARY OF THE INVENTION 
       [0008]    It is an objective of the present invention to produce a gain correction that is connected to a gain control circuit to provide a self-calibrating gain control system. 
         [0009]    It is further an object of the present invention to detect an output signal of a digital amplifier that is coupled in series with at least one analog amplifier. 
         [0010]    It is still further an objective of the present invention to provide gain control in incremental steps in which correction of previous gain control steps are averaged with present gain correction to produce a moving average and providing a smooth gain of the output signal. 
         [0011]    A digital gain control provides gain control in discrete steps to at least one analog amplifier and a digital amplifier coupled in series with the analog amplifier. To compensate for errors in the discrete steps, a signal detector, preferably a root-mean-square (RMS) circuit, detects the output of the digital amplifier and couples a value of the output signal of the digital amplifier to a gain step correction circuit. The gain step correction circuit couples to a digital gain control circuit a correction signal that is an average of present and past RMS values. The gain step correction results in a total gain of the analog and digital amplifiers that is a smooth linear and continuous gain. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    This invention will be described with reference to the accompanying drawings, wherein: 
           [0013]      FIG. 1  is a block diagram of a gain control circuit of the present invention; 
           [0014]      FIG. 2  is a set of diagrams depicting digital stepped gain control of the present invention; 
           [0015]      FIG. 3  is a diagram of an estimation of a linear gain using a stepped gain of the present invention; and 
           [0016]      FIG. 4  is a block diagram of a gain control circuit using feed back of an output signal to provide correction to a digital gain control circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    In  FIG. 1  is shown a gain control circuit  10 . The gain control circuit  10  is divided into an analog portion  11  and a digital portion  12 . A signal in Sin is connected to a low noise amplifier (LNA)  13 . The output of the LNA  13  is coupled to a digital amplifier El  14  through an analog to digital converter (ADC)  15 . A digital gain control circuit  16  controls both the LNA  13  and the digital amplifier  14  using gain control connections GC 1  and GC 2 , respectively. Control input GCT to the gain control circuit directs either an increase or decrease in total gain of the LNA  13  and the digital amplifier El  14 , depending upon the value of the output signal detected by the signal detector  17 . The signal detector  17  is preferable a root-mean-square (RMS) detector, but other signal detectors comprising a peak detector, envelope detector and power detector can also be used. 
         [0018]    It should be noted and is within the scope of the present invention that the LNA  13  can be replaced by any digital gain controlled analog amplifier that is coupled to a digital amplifier in a fashion similar to that shown in  FIG. 1 , where the total gain from an analog signal input Sin to a digital signal out Sout is controlled by a gain control circuit  16 . 
         [0019]      FIG. 2  is a set of graphs demonstrating gain control for the circuit of  FIG. 1  The demonstrations exhibited in the graphs are an example of increasing gain in the amplifiers LNA  13  and E 1   14  under the control of the gain control circuit  16 . A similar set of graphs (not shown) would exemplify reducing the gain of the LNA and E 1  amplifiers would be the same except the direction each graph would be in the downward direction. The graph shown in  FIG. 2  (A 1 ) demonstrates an ideal gain applied to the LNA  13 . The gain is increased in equal discrete steps dG 1  to dGn from the digital gain control circuit  16 . During each of the time periods T 1  to Tn the gain control circuit  16  issues a digital signal to control the LNA  13 . In  FIG. 2  (A 2 ) manufacturing process variations and defects can produce varying discrete steps, even when the control input GC 1  is uniform. 
         [0020]    The graph of  FIG. 2  (B 1 ) demonstrates the ideal gain of the digital amplifier (E 1 )  14  under the control of the gain control circuit  16  through the gain control connection GC 2 . The maximum height of the gain control GC 2  to the digital amplifier E 1  is approximately equal to the height of each step used for the LNA shown in  FIG. 2  (A 1 ). This allows the digital amplifier gain to fill in the void between steps of the LNA and produce a smooth linear change in the total gain of the input signal Sin through to the output signal Sout. In  FIG. 2  (B 2 ) the digital amplifier gain is shown to be the same as in  FIG. 2  (B 1 ) since the continuous increments or decrements associated with the digital amplifier are a least significant bit, which are significantly smaller than the gain steps taken with the LNA and if a manufacturing process defect exist, produce a much smaller perturbation. 
         [0021]    In the graph of  FIG. 2  (C 1 ) is shown the ideal total gain control results of the amplifiers LNA  13  and E 1 , which demonstrates a smooth continuous increase in total gain of the serial coupling of the LNA  13  and the E 1   14  amplifiers. The result of gain step variation of the LNA creates perturbations in the total gain of an input signal Sin through to the output signal Sout as shown in  FIG. 2  (C 2 ). These perturbations can cause a false indication of excessive total gain adjustment of the LNA and E 1  and therefore, can call for a reduction in gain immediately thereafter. 
         [0022]      FIG. 3  demonstrates the approximation of a linear gain  19  using a stepped gain  18 . In the limit as the stepped gain  18  is reduced in amplitude and time period, the stepped gain  18  will approach the desired linear gain. This would result in slowing down the operation of changing the gain due to the slower response of the analog amplifier. Adding a digital amplifier to the gain path shown in  FIG. 1  allows in the composite of the two gains the ability to have a smooth continuous gain adjustment within a much shorter total time period. 
         [0023]    An embodiment of the present invention is shown in  FIG. 4  in which analog to digital circuitry  20  comprises an analog amplifier  13  coupled to a digital amplifier  14 , which produces a signal out Sout. An analog signal Sin is connected to a low noise amplifier (LNA)  13 . The output of the LNA is coupled to a digital amplifier  14  through an analog to digital converter (ADC)  15 . The output of the digital amplifier  14  forms the signal output of the analog to digital circuitry  20 . Both the LNA  13  and the digital amplifier  14  are controlled by a digital gain control circuit  23  that has a control input signal GCT, which determines when increased or decreased gain of the signal path from Sin to Sout is required. A signal detector monitors the output signal Sout and connects a signal value R 1  of the output signal Sout to a gain step correction circuit  22 . The signal detector is preferably a root-mean-square detector; however, other signal detectors comprising a peak detector, envelop detector and a power detector can also be used. 
         [0024]    Contained within the gain step correction circuit are previous RMS values of Sout that were collected during previous gain adjustments. The previous RMS values are filtered, for example averaged, with the present captured RMS value of the output Sout to form a gain correction signal Z 1 , and the step gain correction signal Z 1  is connected to the gain control circuit to overcome perturbations in the change of gain shown in  FIG. 2  (C 2 ), which results in a smooth, linear and continuous change in the gain between Sin and Sout similar to that shown in the graph of  FIG. 2  (C 1 ). 
         [0025]    It should be noted that the circuitry in  FIG. 4  is simplified to the minimum necessary components to perform the operation of the present invention. It is within the scope of the present invention that other electronic circuitry is connected between the signal input Sin and the signal output Sout, including additional stages of gain, which may or may not be variable gain amplifiers, which may or may not be controlled by the gain control circuit  23  shown in  FIG. 4 . Further, it should be noted that the LNA shown in  FIG. 4  can be replaced with any digitally gain controlled analog amplifier  13  coupled in series with the digital amplifier  14 , wherein the total gain of an analog input signal Sin, connected through the analog amplifier  13  and the digital amplifier  14 , is controlled by the gain control circuit  23  to produce a smooth linear and continuous gain of the analog signal through to the digital output Sout of the digital amplifier. 
         [0026]    While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.