Abstract:
A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively; one or more intermediate metal pillars disposed between and in electrical contact with an upper end of the metal pillars; and one or more separation regions of dielectric disposed below the intermediate metal pillar and between the lower ends of the first and second metal pillars.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention generally relates to the field of semiconductor fabrication. More particularly, the present invention relates to a method and apparatus for forming connections within a semiconductor device. 
       BACKGROUND 
       [0002]    In semiconductor design, particularly SRAM design, it is often desirable to create a contact bridge between contacts in very close proximity.  FIG. 1  shows a plan view of a schematic representation of design pattern for an exemplary semiconductor device  100  typically disposed on an integrated circuit (IC). The device  100  is formed on a silicon substrate (not shown). Using standard lithographic methods that are well known in the art, an etch is performed on the silicon substrate, resulting in reduced thickness of the silicon substrate (known as a shallow trench), except for the places where the lithographic method prevented the etch from occurring. These areas  104  which were not etched away are referred to as silicon traces. Continuing the process, a dielectric layer  114  is applied to cover the then exposed upper surface of the device  100 . Then, the dielectric layer  114  is partially removed, typically by polishing, so that only the upper surface of each silicon trace  104  is exposed. Continuing, a layer of polycrystalline silicon is applied to cover the then exposed upper surface of the device  100 . Using standard lithographic methods that are well known in the art, an etch is performed on the surface to form a plurality of polycrystalline silicon (referred to as polysilicon) lines or traces  106 .  FIG. 1  shows the relationship between the silicon traces  104  and polycrystalline silicon traces  106 . Continuing, a dielectric layer  112  is applied across the then exposed upper surface of the device  100 . Portions of the dielectric layer  112  are then removed using standard lithographic methods leaving sidewall spacers  112 A and  112 B on either side of silicon traces  106 . Next a dielectric layer  116  is applied across the then exposed upper surface of the device  100 . Finally, according to the prior art, conductive contacts  108 ,  109 , referred to as a CA (contact area), and contact area rectangle structures  110 , referred to as a CAREC herein, are put in place, as described below. The conductive contacts  108 ,  109  make electrical contact with the silicon traces  104  and polysilicon traces  106 , respectively. It is sometimes desirable to connect a gate of one transistor to a source or drain of another transistor in close proximity. In order to make this connection, the CAREC  110  can be used. The CAREC  110  is a form of well known local interconnect wiring. To form the contacts  108 ,  109  and CAREC  110 , the dielectric layer  116  is etched away to form cavities, such as cavity  115  in  FIG. 2 . Then a conductive material such as tungsten is deposited in the cavities to form conductive pillars. These pillars form the CAs  108 , 109  and CARECs  110 . 
         [0003]    The semiconductor device  110  is generally comprised of an arrangement of many transistors on a silicon substrate. The plurality of transistors is formed by the arrangement of the silicon traces  104  and the polysilicon traces  106 , which form the source or drain of each transistor. As shown in  FIG. 1 , the contacts  108  are in electrical contact with silicon traces  104  and contacts  109  are in electrical contact on the polysilicon traces  106 . 
         [0004]    It should clearly be understood that  FIG. 1  illustrates but an extremely small (microscopic) portion of an integrated circuit (IC) device, let alone a semiconductor wafer comprising a large plurality of such devices. For example, what is shown may have a width of only a few microns (pm) of a semiconductor wafer having a diameter of several inches. Also, in “real life” things are not so neat and clean, rectilinear and uniform as shown. However, for one of ordinary skill in the art to which the invention most nearly pertains, this and other figures presented in this patent application will be very useful, when taken in context of the associated descriptive text, for understanding the invention. 
         [0005]    The semiconductor device  100  shown in  FIG. 1  (as well as in the other Figures) is fabricated utilizing conventional processing steps well known to those skilled in the art. Since such techniques are well known and are not critical for understanding the present invention, a detailed discussion of the same is not given herein. It will be understood that various steps and materials have been omitted, for illustrative clarity, such as seed layers, adhesion layers, cleaning steps and the like. 
         [0006]      FIG. 2  shows a cross sectional view of a portion of semiconductor device  100 , as viewed along line A-A of  FIG. 1 , showing the details of CAREC  110 . The CAs  108 , 109  (shown in  FIG. 1 ) and the CARECs  110  are formed by using a selective etch to etch cavities in the dielectric  116  until the desired silicon or polysilicon layer is reached. Then a conductive material such as tungsten is deposited in the cavities to form conductive pillars. These pillars form the CAs  108 , 109  and CARECs  110 . 
         [0007]    Referring again to  FIG. 2 , CAREC  110  can be formed by first performing a reactive ion etch on the desired area to remove a portion of dielectric layer  116 . This etching forms a cavity  115  that is filled with a conductive metal, such as tungsten. The result is shown in  FIG. 2 , in which CAREC  110  is formed over polysilicon trace  106 . Polysilicon trace  106  serves as the gate of a transistor. Adjacent and on either side of polysilicon trace  106  are sidewall spacers  112 A and  112 B. The sidewall spacers  112 A and  112 B are important during the etching process to prevent damage to the doping implants under silicon trace  104  and polysilicon trace  106 . Ideally, sidewall spacers  112 A and  112 B should be approximately symmetrical. However, because, the etching of the cavities forming pillars CAs  108 , 109  and CARECs  110  occurs at the same time, sidewall spacer  112 A gets more eroded by the etch process, since on the left side, the cavity  115  is deeper so as to reach trace  104  as compared to the right side where the cavity  115  goes down to the trace  106 . The result is damage to spacer  112 A, and a portion of the upper surface of silicon trace  104 . This damage may adversely remove dopants that were put there prior to the etching step, during the implant phase of the manufacturing process. This creates a high resistance element, which degrades the performance of the semiconductor. 
         [0008]    There are multiple drawbacks to this process. First, the etching process works on a global level. Therefore, it is desirable to have one consistent shape for etching, so that dielectric material will be etched at a similar rate. The CARECs  110  have approximately double the area of the CAs  108  and  109 . The area being etched effects the rate of etch. Therefore, with shapes of various areas being etched, the etching process is not as consistent as it would be if one uniform shape was used. Second, etching the CAREC may compromise the sidewall spacer of the transistor and remove dopants, resulting in degraded semiconductor performance. As the demands of technology require more complex functionality in products having size constraints, such as portable electronics products, there is an increasing need to fit more transistors on a semiconductor device. Therefore, what is needed is an improved connection method that allows the flexibility of connecting contacts in close proximity, provides a consistent etch shape, and does not compromise the integrity of a sidewall spacer or cause unwanted removal of dopants. 
       SUMMARY OF THE INVENTION 
       [0009]    According to the present invention, there is disclosed a method for fabricating a connection between two transistor elements on a semiconductor substrate. The method comprises the following steps: providing the semiconductor substrate with a silicon line forming a first transistor element, a polysilicon line forming a second transistor element, a first side spacer on one side of second transistor element and a second side spacer on an opposite side of the second transistor element, and a dielectric layer overlying the first transistor element, the second transistor element, and the first and second side spacers; applying a layer of photo resist over an upper surface of the dielectric layer; photo patterning said photo resist layer to form at least first and second contact areas with an area of photo resist therebetween; forming at least first and second cavities corresponding to the at least first and second contact areas extending through the photo resist layer to the dielectric layer with a region of the photo resist remaining therebetween; etching the dielectric layer through the at least first and second cavities to form at least first and second contact cavities in the dielectric layer and concurrently reducing the thickness of the photo resist layer and resist region to form a first intermediate cavity between first and second contact cavities and a first separation region of the dielectric layer between the first and second contact cavities; further etching the dielectric layer until the first contact cavity contacts the first transistor element, the second contact cavity contacts the second transistor element, the first intermediate cavity extends between contact cavities and down to the first separation region of the dielectric layer between contact cavities; and depositing conductive metal in the first and second contact cavities and in the intermediate cavity to form a first, a second and an intermediate conductive metal pillar. 
         [0010]    Further according to the present invention, the method includes joining the first, second and intermediate conductive metal pillars together at an upper end top thereof and placing them in electrical contact with the first transistor element and the second transistor element at a bottom end thereof and isolating the intermediate conductive metal pillar from the first side spacer with the first separation region to form a double CA bridge structure. 
         [0011]    Still further according to the present invention, the method includes selecting the conductive metal from the group consisting of tungsten and copper. 
         [0012]    Also according to the present invention, the method includes etching with a reactive ion etch process. 
         [0013]    Yet further according to the present invention, the step of depositing conductive metal in the first and second contact cavities and the intermediate cavity creates an excess layer of conductive metal across the upper surface of the dielectric layer. The excess conductive metal can be removed from the upper surface of the dielectric layer via a chemical mechanical polish. 
         [0014]    Further according to the present invention, the method includes forming a triple CA bridge structure with first, second and third contact cavities, first and second intermediate cavities and first and second separation regions for isolating first, second and third side spacers. Then depositing conductive metal in the first, second and third contact cavities and in the first and second intermediate cavities to form first, second and third conductive metal pillars and a first and second intermediate conductive metal pillars. This causes the first intermediate conductive metal pillar to be disposed between the first and second conductive metal pillars and the second intermediate conductive metal pillar to be disposed between the second and third conductive metal pillars. Also the first separation region is disposed between the first and second conductive metal pillars and the second separation region is disposed between the second and third conductive metal pillars, thereby forming a triple CA bridge structure. 
         [0015]    Yet further according to the present invention, a quad CA bridge structure can be formed by the steps of forming first, second and third and fourth contact cavities, first, second and third intermediate cavities and first, second and third separation regions for isolating the first, second, third and fourth side spacers. Then depositing conductive metal in the first, second, third and fourth contact cavities and in the first, second and third intermediate cavities to form first, second, third and fourth conductive metal pillars and first, second and third intermediate conductive metal pillars. The first intermediate conductive metal pillar is disposed between the first and second conductive metal pillars, the second intermediate conductive metal pillar is disposed between the second and third conductive metal pillars, the third intermediate conductive metal pillar is disposed between the third and fourth conductive metal pillars. The first separation region is disposed between the first and second conductive metal pillars, the second separation region is disposed between the second and third conductive metal pillars, and the third separation region is disposed between the third and fourth conductive metal pillars thereby forming a quad CA bridge structure. When the first, second, third, and fourth conductive metal pillars are arranged linearly, a linear quad CA bridge structure is formed. Also when the first conductive metal pillar is arranged at a right angle in relation to the second, third, and fourth conductive metal pillars, a quad CA ‘L’ bridge structure is created. 
         [0016]    Also further according to the present invention, there is disclosed a semiconductor device having a contact bridge between transistor contacts in close proximity. The contact bridge comprises at least first and second metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively; at least a first intermediate metal pillar being disposed between and in electrical contact with an upper end of the first and second metal pillars; and at least a first separation region of dielectric disposed below first intermediate metal pillar and between the lower ends of the first and second metal pillars. 
         [0017]    Still further according to the present invention, the semiconductor device incorporates the first and second metal pillars, the intermediate metal pillar and the first separation region being arranged substantially vertically; the first metal pillar is oriented above and in contact with the first transistor element; the second metal pillar is oriented above and in contact with the second transistor element; first and second sidewall spacers are disposed on opposite sides of the second transistor; and first separation region of dielectric isolates the first sidewall spacer from the first intermediate metal pillar. 
         [0018]    Also further according to the present invention, the contact bridge further comprises: 
         [0019]    at least first, second and third metal pillars each having a lower end in electrical contact with first, second and third transistor elements, respectively; at least first and second intermediate metal pillars being disposed between and in electrical contact with an upper end of the first, second and third metal pillars; and at least first and second separation regions of dielectric disposed below the first and second intermediate metal pillars and between the lower ends of the first, second and third metal pillars. 
         [0020]    Still further, the semiconductor device has: the first, second and third metal pillars, the first and second intermediate metal pillars and the first and second separation regions are arranged substantially vertically; the first metal pillar is oriented above and in contact with the first transistor element; the second metal pillar is oriented above and in contact with the second transistor element; the third metal pillar is oriented above and in contact with the third transistor element; first and second sidewall spacers are disposed on opposite sides of the second transistor; and the second sidewall spacer and a third sidewall spacer are disposed on opposite sides of the third transistor; and the first separation region of dielectric isolates the first sidewall spacer from the first intermediate metal pillar and the second separation region of dielectric isolates the third sidewall spacer from the third intermediate metal pillar. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  is a plan view of a schematic of a design pattern of a prior art semiconductor device. 
           [0022]      FIG. 2  is a cross section view of a portion of the semiconductor device of  FIG. 1  showing the CAREC and the damage to a spacer and a portion of the upper surface of a silicon trace. 
           [0023]      FIG. 3  is a plan view of a design pattern placed on the upper surface of a semiconductor device prior to etching the cavities forming the contacts and twin CA structure, according to the present invention. 
           [0024]      FIGS. 4-12  is a view through line A-A of  FIG. 3  showing the various steps required to form the twin CA bridge structure. 
           [0025]      FIGS. 13A-13C  show alternate embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0026]      FIG. 3  shows a schematic illustration of an intermediate stage in the construction of an exemplary embodiment semiconductor device  300  of the present invention. Semiconductor device  300  is similar to semiconductor device  100  of  FIG. 1 , with the exception that twin CA bridge structures  350  described below have been used to replace the CARECs  110  of  FIG. 1 . That is to say, polysilicon lines  306  are similar to polysilicon lines  106  of  FIG. 1 , silicon lines  304  are similar to silicon line  104  of  FIG. 1 , and contacts  308 ,  309  are generally similar to contacts  108 ,  109  of  FIG. 1 . 
         [0027]    To form twin CA bridge structures  350 , two particular contact areas of interest, indicated as  308 A and  309 A are placed in close proximity to each other. As illustrated in  FIG. 3 , contact area  308 A is placed on a silicon trace  304 , and contact area  309 A is placed on a polysilicon trace  306 . 
         [0028]    Where previously a CAREC  110  (see  FIG. 1 ) was used to join two traces  304  and  306  in close proximity, the twin CA bridge structure  350  as described below, interconnects the two traces  304 ,  306 , without the problems of the CAREC  110 . In the semiconductor device  300  of  FIG. 3 , all of the contact areas, i.e. CAs  308  and  309 , are preferably formed with substantially the same cross sectional area and with the same square shape. Using the same configuration, makes the etching process of the CAs more efficient and predictable because, being of substantially the same size and geometry, they etch at the same rate and to the same depth in essentially the same amount of time. 
         [0029]      FIG. 4  shows an intermediate stage of the construction of a semiconductor device  300  where the first, second and third dielectric layers  314 ,  312  and  316  have already been applied. A layer  318  of photo resist is applied having a thickness in the range of 200 nanometers to 600 nanometers. 
         [0030]    Next, as shown in  FIG. 5 , a view through line B-B of  FIG. 3 , using graphic methods, first and second, substantially identical CA shaped cavities  320 A and  320 B, are formed through the surface of resist  318 . One of the CAs  320 A is aligned with polysilicon line  306 . The other one of the CAs  320 B is aligned silicon line  304  and to the left of line  306 . Between CA  320 A and CAs  320 B, a sliver region  318 A of resist aligned above a first side spacer  312 A of a dielectric  312  remains. This sliver resist region  318 A is important for forming the twin CA bridge structure  350  of the present invention, as will be described hereinafter. 
         [0031]      FIG. 6  shows the beginning of an etch step where cavities  321 A and  321 B are being etched down into dielectric layer  316 . The resist layer  318 B is also getting worn away to form a cavity  320 C between cavities  320 A and  320 B by the etch process. The cavity  321 C actually creates a single cavity with cavities  321 A and  321 B. Note that the sliver resist region  318 B is etched away at a faster rate than the rest of the resist, due to the increased ratio of surface area to volume of that feature, as compared with the rest of the photo resist  318 . 
         [0032]      FIG. 7  shows the etch process further along from  FIG. 6 . Now, cavities  321 A and  321 B project further into dielectric layer  316  and cavity  321 C is beginning to get longer in the resist layer  318 . At this stage of the process, the resist layer  318  is very thin but still intact. However, the sliver resist region  318 B is now very thin. 
         [0033]      FIG. 8  shows the sliver resist region  318 A completely removed from continued etching. The rest of the resist  318 , while thinner, is still intact. Cavities  321 A and  321 B are still deeper and intermediate cavity  321 C extends downward between cavities  321 A and  320 B. Directly below intermediate cavity  321 C is a separation region  316 A of dielectric layer  316  between cavities  321 A and  320 B. 
         [0034]      FIG. 9  shows a portion of dielectric layer  316  in between cavities  321 A and  321 B removed by further etching. Cavities  321 A and  321 B are joined at the upper portion, as the dielectric layer  316  is being etched away, by intermediate cavity  321 C. 
         [0035]    Because cavities  321 A and  321 B form contact areas when the fabrication process is complete, cavities  321 A and  321 B are referred to as contact cavities. An important aspect of the intermediate cavity  321 C is that it does not extend to the bottom of cavities  321 A and  321 B. 
         [0036]      FIG. 10  shows the step where the cavities  321 A and  321 B have been further etched through the dielectric layer  316 . Any remaining resist  318  is removed, typically, by burning it off in an oxygen plasma. Cavity  321 B extends to the silicon layer  304 . Cavity  321 A extends to the polysilicon trace  306 . Cavity  321 C, while being deeper, is in contact with the sidewalls of cavities  321 A and  321 B and is separated by a separation region  316 A of dielectric  316  above the sidewall spacer  312 A. 
         [0037]    It can now be appreciated that the resist sliver  318 B (See  FIG. 5 ) provided initial protection of the dielectric layer  316  from the etchant in the area  321 C between cavity  321 A and  321 B, and therefore cavity  321 C is not as deep as  321 A and  321 B. This construction step protected the top of polysilicon trace  306  and spacer  312 A and the silicon trace  304  in the proximity of spacer  312 A from undesired etching. By protecting the spacer  312 A, the polysilicon trace  306  and silicon trace  304 , the dopants applied to the silicon trace  304  during the implant phases (not described) are preserved. Moreover, the sidewall spacer  312 A is completely intact and able to control further implant of dopants. By comparison, in the prior art, see  FIG. 2 , a portion of the polysilicon trace  306 , sidewall spacer  312 A, and a portion of silicon trace  304  are routinely destroyed during the etching process. 
         [0038]      FIG. 11  shows where a conductive material  322  such as tungsten or copper has been deposited over the semiconductor. The tungsten fills cavities  321 A,  321 B and  321 C and forms a twin CA bridge structure  350  comprising tungsten pillars  324 A,  324 B and  324 C that are joined at the top thereof. The deposition of tungsten also forms a layer  322  on top surface  316 B of the dielectric layer  316 . This metal layer  322  shorts all the contacts, and must be removed for a properly functioning semiconductor device. 
         [0039]      FIG. 12  shows the excess tungsten layer  322  removed by conventional means such as with a chemical mechanical polish (CMP). The end result is the twin CA bridge structure  350  which provides electrical contact between silicon trace  304  and polysilicon trace  306 . The intermediate pillar  324 C, see  FIG. 11 , is filled with tungsten and forms a bridge connecting pillars  324 A and  324 B. 
         [0040]      FIGS. 13A-13C  show alternate embodiments of the present invention that extends this concept to more than two contacts bridged together. The joined CA bridge structure of the present invention can have more than two contacts. 
         [0041]      FIG. 13A  shows a cross sectional view of a joined CA structure  360  with three pillars of conducting material  328 A,  328 B, and  328 C joined together, using the same technique that was described in detail for the twin CA structure  350 . Pillar  328 A is in contact with trace  314 , pillar  328 B is in contact with silicon trace  304  and pillar  328 C is in contact with polysilicon silicon trace  306 . First and second intermediate conductive metal pillars  328 D and  328 E are formed at the upper end of the three pillars of conducting material  328 A,  328 B, and  328 C. The first intermediate conductive metal pillar  328 D is disposed between the first and second conductive metal pillars  328 A and  328 C and the second intermediate conductive metal pillar  328 E is disposed between the second and third conductive metal pillars  328 D and  328 B. A first separation region  330 A of dielectric  316  is disposed between the first and second conductive metal pillars  328 A and  328 C and a second separation region  330 B of dielectric  316  is disposed between the second and third conductive metal pillars  328 C and  328 B, thereby forming a triple CA bridge structure. 
         [0042]      FIG. 13B  shows a plan view of a schematic design pattern for a structure employing four contacts in a right angle pattern. This joined CA structure is referred to as a Quad CA structure, and is indicated as  370 . In particular, because the arrangement of contacts  308 E,  308 F,  308 G and  308 H forms a right angle, this joined CA structure  370  is referred to as a Quad CA ‘L’ structure. Using the techniques of present invention, as described in detail hereinbefore, contacts  308 E- 308 H are interconnected. Contact  308 G may be solely an intermediate contact, serving only to join contact  308 F to  308 H, i.e., contact  308 G may not directly contact a transistor element. The flexibility of this technique provides allows for many possible interconnections, even if all the contacts are not collinear, as is the case with this example. However, it is also possible to have a linear Quad CA structure, where all contacts of the Quad CA structure are collinear. This is shown in  FIG. 13C . In this case, contacts  308 J- 308 M are interconnected using a linear Quad CA structure  380 . Regardless of the number of contacts used to make a joined CA structure, the contact cavities are arranged in a sequence. The sequence may be linear, or may be formed with at least one right angle, or at angles other than 90 degrees. An intermediate cavity may be used to join two neighboring contact cavities. For example, in  FIG. 13C , contact  308 L has two neighboring contacts,  308 K and  308 M. There is an intermediate cavity in between the neighboring contact cavities. The intermediate cavity provides electrical contact between the two neighboring contacts once the metal deposition process has completed. 
         [0043]    As is apparent from the aforementioned drawings and associated written description, the present invention provides an improved method and apparatus for forming connections within a semiconductor device. 
         [0044]    It will be understood that the present invention may have various other embodiments. For example, while tungsten was used as the connecting material in the examples provided, it is possible to use the method of the present invention with other materials, such as copper. 
         [0045]    It is also understood, of course, that while the form of the invention herein shown and described constitutes a preferred embodiment of the invention, it is not intended to illustrate all possible forms thereof. It will also be understood that the words used are words of description rather than limitation, and that various changes may be made without departing from the spirit and scope of the invention disclosed. Thus, the scope of the invention should be determined by the appended claims and their legal equivalents, rather than solely by the examples given.