Abstract:
Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of Korean Patent Application No. 10-2014-0017471 filed in the Korean Intellectual Property Office on Feb. 14, 2014, the entire contents of which are incorporated herein by reference. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Aspects of example embodiments relate to a driving circuit and a display device including the same. 
         [0004]    2. Description of the Related Art 
         [0005]    A display device includes a driving circuit for generating a plurality of driving signals. The display device includes a plurality of pixels. Each pixel includes a light emitting element and a switch for supplying a driving current to the light emitting element. The driving signals include signals for controlling the switches. For example, the driving signals include a scan signal for controlling synchronizing of data writing and/or an initialization signal for initializing the pixels. 
         [0006]    However, a delay characteristic of increase and decrease times of the signals inputted to the driving circuit in order to generate the driving signals may affect an action of the driving circuit and image quality of the display device. 
         [0007]    The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form the prior art that is known to a person of ordinary skill in the art. 
       SUMMARY 
       [0008]    Aspects of example embodiments relate to avoiding a delay of a signal and a voltage drop occurring in a wire, which may affect an action of a pixel circuit and image quality of a display device. 
         [0009]    An example embodiment provides a scan driver including: a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage in series; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal; a first wire configured to transfer the first clock signal; a second wire configured to transfer the second clock signal; and a third wire configured to transfer the first signal. A width of the first wire and a width of the second wire are larger than a width of the third wire. 
         [0010]    An electrode of the third transistor may be coupled to the gate of the second transistor, another electrode of the third transistor may be configured to receive a second voltage, a gate of the third transistor may be coupled to the third wire, and a width of a fourth wire configured to transfer the first voltage may be larger than a width of a fifth wire configured to transfer the second voltage. 
         [0011]    Another example embodiment provides a scan driver including: a plurality of first unit scan driving circuits configured to receive a prior first scan signal in synchronization with a first clock signal and to respond to an enable level of the prior first scan signal to output a second clock signal as a corresponding first scan signal during one cycle of the first clock signal; a plurality of second unit scan driving circuits configured to receive the first scan signal in synchronization with a third clock signal and to respond to an enable level of the first scan signal to output a fourth clock signal as a corresponding second scan signal during one cycle of the third clock signal. A width of a first wire configured to transfer the third clock signal and a width of a second wire configured to transfer the fourth clock signal are larger than at least one of a width of a third wire configured to transfer the first clock signal and a width of a fourth wire configured to transfer the second clock signal. 
         [0012]    Each of the plurality of first unit scan driving circuits may include: a first transistor including an electrode configured to receive the second clock signal, and a gate configured to receive the prior first scan signal; a second transistor including an electrode coupled to another electrode of the first transistor, and another electrode coupled to a first voltage; and a third transistor coupled between a gate electrode of the second transistor and a second voltage and configured to be turned on according to the first clock signal. 
         [0013]    A width of a fifth wire configured to transfer the first voltage may be larger than a width of a sixth wire configured to transfer the second voltage. 
         [0014]    Each of the plurality of second unit scan driving circuits may include: a first transistor including an electrode configured to receive the fourth clock signal, and a gate configured to receive the corresponding first scan signal; a second transistor including an electrode coupled to another electrode of the first transistor, and another electrode coupled to a first voltage; and a third transistor coupled between a gate electrode of the second transistor and a second voltage and configured to be turned on according to the third clock signal. 
         [0015]    A width of a fifth wire configured to transfer the first voltage may be larger than a width of a sixth wire configured to transfer the second voltage. 
         [0016]    Yet another example embodiment provides a scan driver including: a first wire configured to transfer a first clock signal; a second wire configured to transfer a first signal; a first transistor including an electrode coupled to the first wire; and a second transistor including a gate electrode coupled to the second wire. A width of the first wire is larger than a width of the second wire. 
         [0017]    The scan driver may further include: a third wire configured to transfer a second clock signal; and a third transistor including an electrode coupled to the third wire. A width of the third wire may be larger than the width of the second wire. 
         [0018]    The scan driver may further include a fourth transistor including a gate electrode coupled to the third wire. A gate electrode of the first transistor may be coupled to an electrode of the fourth transistor. 
         [0019]    The scan driver may further include: a fourth wire configured to transfer a first voltage; a fifth wire configured to transfer a second voltage; and a fifth transistor including a gate electrode coupled to the second transistor, an electrode coupled to another electrode of the first transistor, and another electrode coupled to the fourth wire. A width of the fourth wire may be larger than a width of the fifth wire. 
         [0020]    An electrode of the second transistor may be coupled to the fifth wire, and another electrode of the second transistor may be coupled to the gate electrode of the fifth transistor. 
         [0021]    Still another example embodiment provides a scan driver including: a first wire configured to transfer a first clock signal; a second wire configured to transfer a second clock signal; a third wire configured to transfer a third clock signal; a first transistor including a gate electrode coupled to the first wire; a second transistor including a gate electrode coupled to an electrode of the first transistor; a third transistor including a gate electrode coupled to the third wire and an electrode coupled to an electrode of the second transistor; and a fourth transistor including a gate electrode coupled to another electrode of the third transistor, and an electrode coupled to the second wire. A signal is outputted through another electrode of the fourth transistor, and a width of the second wire is larger than a width of the first wire. 
         [0022]    The scan driver may further include: a fifth transistor including a gate electrode coupled to the second wire; and a sixth transistor including a gate electrode coupled to an electrode of the fifth transistor, and an electrode coupled to the third wire. Another signal may be outputted through another electrode of the sixth transistor, and a width of the third wire may be larger than the width of the first wire. 
         [0023]    The scan driver may further include: a seventh transistor including a gate electrode, an electrode coupled to another electrode of the fourth transistor, and another electrode coupled to a fourth wire configured to transfer a first voltage; and an eighth transistor including a gate electrode coupled to the gate electrode of the third transistor, an electrode coupled to a fifth wire configured to transfer a second voltage, and another electrode coupled to the gate electrode of the seventh transistor. A width of the fourth wire may be larger than a width of the fifth wire. 
         [0024]    A further example embodiment provides a display device including: a scan driver configured to generate a plurality of scan signals; and a plurality of pixels configured to receive a plurality of data voltages according to the plurality of scan signals. The scan driver includes: a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage in series; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal; a first wire configured to transfer the first clock signal; a second wire configured to transfer the second clock signal; and a third wire configured to transfer the first signal. A width of the first wire and a width of the second wire are larger than a width of the third wire. 
         [0025]    An electrode of the third transistor may be coupled to the gate of the second transistor, another electrode of the third transistor may be configured to receive a second voltage, a gate of the third transistor may be coupled to the third wire, and a width of a fourth configured to transfer the first voltage may be larger than a width of a fifth wire configured to transfer the second voltage. 
         [0026]    A still further example embodiment provides a display device including: a scan driver configured to generate a plurality of first scan signals and a plurality of second scan signals; and a plurality of pixels configured to receive a plurality of data voltages according to the plurality of second scan signals, and to be initialized according to the plurality of first scan signals. The scan driver includes: a plurality of first unit scan driving circuits configured to receive a prior first scan signal in synchronization with a first clock signal and to respond to an enable level of the prior first scan signal to output a second clock signal as a corresponding first scan signal during one cycle of the first clock signal; and a plurality of second unit scan driving circuits configured to receive the first scan signal in synchronization with a third clock signal and to respond to an enable level of the first scan signal to output a fourth clock signal as a corresponding second scan signal during one cycle of the third clock signal. A width of a first wire configured to transfer the third clock signal and a width of a second wire configured to transfer the fourth clock signal are larger than at least one of a width of a third wire configured to transfer the first clock signal and a width of a fourth wire configured to transfer the second clock signal. 
         [0027]    Each of the plurality of first unit scan driving circuits may include: a first transistor including an electrode configured to receive the second clock signal, and a gate configured to receive the prior first scan signal; a second transistor including an electrode coupled to another electrode of the first transistor, and another electrode coupled to a first voltage; and a third transistor coupled between a gate electrode of the second transistor and a second voltage, and configured to be turned on according to the first clock signal. 
         [0028]    Each of the plurality of second unit scan driving circuits may include: a first transistor including an electrode configured to receive the fourth clock signal, and a gate configured to receive the corresponding first scan signal; a second transistor including an electrode coupled to another electrode of the first transistor, and another electrode coupled to a first voltage; and a third transistor coupled between a gate electrode of the second transistor and a second voltage, and configured to be turned on according to the third clock signal. 
         [0029]    According to aspects of example embodiments, a delay of a signal and a voltage drop occurring in a wire, which may affect an action of a pixel circuit and image quality of a display device, may be reduced or avoided. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]      FIG. 1  is a view showing two consecutive stages in a scan driving circuit according to an example embodiment. 
           [0031]      FIG. 2  is a view showing a layout of unit scan driving circuits shown in  FIG. 1 . 
           [0032]      FIG. 3  is a view showing a display device including the scan driving circuit according to an example embodiment of the present invention. 
           [0033]      FIG. 4  is a view showing a pixel circuit according to an example embodiment. 
           [0034]      FIG. 5  is a view showing a scan driving circuit according to another example embodiment. 
           [0035]      FIGS. 6A and 6B  are views showing a layout of unit scan driving circuits shown in  FIG. 5 . 
           [0036]      FIG. 7  is a view showing a display device according to another example embodiment. 
           [0037]      FIG. 8  is a view showing an example of one pixel from among a plurality of pixels according to another example embodiment. 
           [0038]      FIG. 9  is a view showing a waveform chart illustrating a timing for driving the pixel shown in  FIG. 8 . 
       
    
    
     DETAILED DESCRIPTION 
       [0039]    In the following detailed description, only certain example embodiments have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. 
         [0040]    Throughout this specification and the claims that follow, when it is described that an element is “coupled” to another element, the element may be “directly coupled” to the other element or “electrically coupled” or “indirectly coupled” to the other element through one or more intervening elements. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements. 
         [0041]    Hereinafter, a driving circuit according to an example embodiment and a display device including the same will be described with reference to the drawings. Hereinafter, ordinal numbers described together with constituent elements are determined according to an order described in the specific content for carrying out the invention. 
         [0042]      FIG. 1  is a view showing two consecutive stages in a scan driving circuit according to an example embodiment. 
         [0043]    The scan driving circuit (e.g., scan driver) includes a plurality of consecutively arranged stages. Each stage (e.g., an n-th stage) receives a scan signal S[n−1] of an adjacent prior stage, generates a scan signal S[n] of a current stage, and outputs the scan signal S[n] to a next stage (e.g., an n+1-th stage). The next stage receives the scan signal (e.g., S[n]) and outputs the next scan signal (e.g., S[n+1]). 
         [0044]    Hereinafter, each one of the plurality of stages constituting the scan driving circuit will be referred to as a unit scan driving circuit. 
         [0045]    As shown in  FIG. 1 , a unit scan driving circuit SD 1   —   n  includes a plurality of transistors P 1 -P 6  and two capacitors C 1  and C 2 . A unit scan driving circuit SD 1   —   n +1 includes a plurality of transistors P 7 -P 12  and two capacitors C 3  and C 4 . 
         [0046]    The unit scan driving circuit SD 1   —   n  is synchronized with a clock signal CLK 2  (e.g., in synchronization with a clock signal) to receive the scan signal S[n−1], and responds to an enable level of the scan signal S[n−1] to output a clock signal CLK 1  as the scan signal S[n] during one cycle of the clock signal CLK 2 . 
         [0047]    The unit scan driving circuit SD 1   —   n +1 is synchronized with the clock signal CLK 1  to receive the scan signal S[n], and responds to an enable level of the scan signal S[n] to output the clock signal CLK 2  as the scan signal S[n+1] during one cycle of the clock signal CLK 1 . 
         [0048]    Since the scan driving circuit according to an example embodiment is a P-channel transistor, the enable level of the scan signal has a low level. However, example embodiments of the present invention are not limited thereto, and the enable level is determined according to a transistor channel type of the driving circuit. 
         [0049]    The clock signal CLK 1  is transferred through a wire L 1 , and the clock signal CLK 2  is transferred through a wire L 2 . An initialization signal INT 1  is transferred through a wire L 3 , and an initialization signal INT 2  is transferred through a wire L 4 . 
         [0050]    The clock signal CLK 2  is inputted to a gate of a transistor P 1 . The scan signal S[n−1] is inputted to an electrode of the transistor P 1 , and another electrode of the transistor P 1  is coupled (e.g., connected) to a node N 1 . 
         [0051]    The scan signal S[n−1] is inputted to a gate of a transistor P 2 . A source of the transistor P 2  is coupled to a voltage VGH, and a drain of the transistor P 2  is coupled to a node N 2 . 
         [0052]    A gate of a transistor P 3  is coupled to the node N 2 , a source of the transistor P 3  is coupled to the voltage VGH, and a drain of the transistor P 3  is coupled to the node N 1 . 
         [0053]    The initialization signal INT 2  is inputted to a gate of a transistor P 4 . A source of the transistor P 4  is coupled to the node N 2 , and a drain of the transistor P 4  is coupled to a voltage VGL. 
         [0054]    A gate of a transistor P 5  is coupled to the node N 2 , a source of the transistor P 5  is coupled to the voltage VGH, and a drain of the transistor P 5  is coupled to a node N 3 . The capacitor C 1  is coupled between the gate and the source of the transistor P 5  to maintain a gate-source voltage. When the transistor P 5  is turned-on, the scan signal S[n] has a high level. 
         [0055]    A gate of a transistor P 6  is coupled to the node N 1 , and a source of the transistor P 6  is coupled to the node N 3 . The clock signal CLK 1  is inputted to a drain of the transistor P 6 . The capacitor C 2  is coupled between the gate and the source of the transistor P 6  to maintain the gate-source voltage. 
         [0056]    The clock signal CLK 1  is inputted to a gate of a transistor P 7 . The scan signal S[n] is inputted to an electrode of the transistor P 7 , and another electrode of the transistor P 7  is coupled to the node N 3 . 
         [0057]    The scan signal S[n] is inputted to a gate of a transistor P 8 . A source of the transistor P 8  is coupled to the voltage VGH, and a drain of the transistor P 8  is coupled to a node N 5 . 
         [0058]    A gate of a transistor P 9  is coupled to the node N 5 , a source of the transistor P 9  is coupled to the voltage VGH, and a drain of the transistor P 9  is coupled to a node N 4 . 
         [0059]    The initialization signal INT 1  is inputted to a gate of a transistor P 10 . A source of the transistor P 10  is coupled to the node N 5 , and a drain of the transistor P 10  is coupled to the voltage VGL. 
         [0060]    A gate of a transistor P 11  is coupled to the node N 5 , a source of the transistor P 11  is coupled to the voltage VGH, and a drain of the transistor P 11  is coupled to a node N 6 . The capacitor C 3  is coupled between the gate and the source of the transistor P 11  to maintain the gate-source voltage. 
         [0061]    A gate of a transistor P 12  is coupled to the node N 4 , and a source of the transistor P 12  is coupled to the node N 6 . The clock signal CLK 2  is inputted to a drain of the transistor P 12 . The capacitor C 4  is coupled between the gate and the source of the transistor P 12  to maintain the gate-source voltage. 
         [0062]    When the clock signal CLK 2  has a low level and the scan signal S[n−1] has a low level, the voltage of the node N 1  has a low level, and thus the transistor P 6  is turned on. In this case, the gate-source voltage of the transistor P 6  is maintained by the capacitor C 2 . The clock signal CLK 1  is outputted as the scan signal S[n] during a turn-on period of the transistor P 6 . When the clock signal CLK 2  has a low level during a next cycle and the scan signal S[n−1] has a high level, the voltage of the node N 1  has a high level, and thus the transistor P 6  is turned off. When the voltage of the node N 2  becomes the voltage VGL having a low level by the initialization signal INT 2 , the transistor P 5  is turned on to allow the scan signal S[n] to have a high level. 
         [0063]    When the clock signal CLK 1  has a low level and the scan signal S[n] has a low level, the voltage of the node N 4  has a low level, and thus the transistor P 12  is turned on. In this case, the gate-source voltage of the transistor P 12  is maintained by the capacitor C 4 . The clock signal CLK 2  is outputted as the scan signal S[n+1] during a turn-on period of the transistor P 12 . When the clock signal CLK 1  has a low level during a next cycle and the scan signal S[n] has a high level, the voltage of the node N 4  has a high level, and thus the transistor P 12  is turned off. When the voltage of the node N 5  becomes the voltage VGL having a low level by the initialization signal INT 1 , the transistor P 11  is turned on to allow the scan signal S[n+1] to have a high level. 
         [0064]    As described above, the clock signals CLK 1  and CLK 2  may be output signals of the unit scan driving circuits SD 1   —   n  and SD 1   —   n +1. For example, in the unit scan driving circuit SD 1   —   n , the clock signal CLK 1  is outputted as the scan signal S[n] when the transistor P 6  is in a turn-on state. In the unit scan driving circuit SD 1   —   n +1, the clock signal CLK 2  is outputted as the scan signal S[n+1] when the transistor P 12  is in a turn-on state. 
         [0065]    Then, an RC delay of the clock signals CLK 1  and CLK 2  transferred to the drains of the transistors P 6  and P 12  affects waveforms of the scan signals S[n] and S[n+1], which affects an action of a pixel circuit acting according to the scan signal. Moreover, the RC delay affects image quality of the display device including the unit scan driving circuit shown in  FIG. 1 . 
         [0066]    On the other hand, the RC delay of the signals switching the transistor on/off does not relatively affect the waveform of the scan signal and the image quality of the display device as compared to the aforementioned clock signals. 
         [0067]    For example, the RC delay of the initialization signals INT 1  and INT 2  transferred to the gates of the transistors P 4  and P 10  to switch the transistors P 4  and P 10  on/off does not affect an action of the pixel circuit. 
         [0068]    Therefore, in the scan driving circuit according to an example embodiment, widths of the wires L 1  and L 2  through which the clock signals CLK 1  and CLK 2  are outputted as the scan signals are transferred, are larger than widths of wires of the other signals. For example, the widths of the wires L 1  and L 2  are larger than widths of the wires L 3  and L 4 , through which the initialization signals INT 1  and INT 2  are transferred. Thus, resistance of the wires may be reduced to reduce the RC delay of the corresponding signal and to reduce or minimize influence of the signal on the action of the pixel circuit and the image quality of the display device due to the RC delay. 
         [0069]      FIG. 2  is a view showing a layout of the unit scan driving circuits shown in  FIG. 1 . 
         [0070]    As shown in  FIG. 2 , the widths of the wires L 1  and L 2 , through which the clock signals CLK 1  and CLK 2  are transferred, are larger than the widths of the wires L 3  and L 4 , through which the initialization signals INT 1  and INT 2  are transferred. 
         [0071]    A gate electrode  11  of the transistor P 1  is coupled (e.g., connected) through a contact hole to the wire L 2 . An electrode  12  of the transistor P 1  is coupled through a contact hole to an electrode  13  to which the scan signal S[n−1] is transferred. An electrode  14  is another electrode of the transistor P 1  and a drain electrode of the transistor P 3 , and is coupled to a gate electrode  15  of the transistor P 6 . 
         [0072]    A gate electrode  16  is a gate electrode of the transistor P 3  and of the transistor P 5 , and is coupled through a contact hole to an electrode  18 . The source of the transistor P 3  and the source of the transistor P 5  are coupled through a contact hole to a wire  17 . The wire  17  is a wire through which the voltage VGH is transferred. The electrode  18  is coupled to the drain of the transistor P 2  and to the source of the transistor P 4 . 
         [0073]    A gate electrode  19  of the transistor P 2  is coupled through a contact hole to the electrode  12 . An electrode  20  is coupled through a contact hole to the wire  17  and to a source electrode  21  of the transistor P 2 . A gate electrode  22  of the transistor P 4  is coupled through a contact hole to the wire L 4 . A wire  23  is a wire through which the voltage VGL is transferred. The drain of the transistor P 4  is coupled through a contact hole to the wire  23 . 
         [0074]    An electrode  80  is coupled through a contact hole to the drain of the transistor P 6  and to an electrode  24 . The electrode  24  is coupled through a contact hole to the wire L 1 . An electrode  70  is coupled through a contact hole to the drain of the transistor P 5  and to the source of the transistor P 6 . An electrode  25  is coupled through a contact hole to the electrode  70 . The scan signal S[n] is outputted through the electrode  25 . 
         [0075]    An electrode  26  is coupled through the contact hole to the wire  17 . The capacitor C 1  is formed in an overlapping region of the gate electrode  16  and the electrode  26 . The capacitor C 2  is formed in an overlapping region of the electrode  25  and the gate electrode  15  of the transistor P 6 . 
         [0076]    The layout of the unit scan driving circuit SD 1   —   n +1 is similar to the aforementioned layout of the unit scan driving circuit SD 1   —   n , except for the following differences. 
         [0077]    A gate electrode  27  of the transistor P 10  is coupled through a contact hole to the wire L 3 . An electrode  28  is coupled through a contact hole to the wire L 2 . An electrode  29  is coupled through a contact hole to the wire L 1 . The scan signal S[n] is inputted through an electrode  30 , and the scan signal S[n+1] is outputted through an electrode  31 . 
         [0078]    As shown in  FIG. 2 , the width of the wire  17  through which the voltage VGH is transferred is larger than the width of the wire  23  through which the voltage VGL is transferred. High level outputs of the scan signals outputted from the scan driving circuit constituted by the P channel transistor are supplied from the voltage VGH. Then, current consumption due to the voltage VGH is larger than current consumption due to the voltage VGL. In the example embodiment of  FIG. 2 , the width of the wire  17  of the voltage VGH is set to be larger than the width of the wire  23  of the voltage VGL, thus reducing resistance of the wire  17  having larger current consumption. Accordingly, power consumption may be reduced. 
         [0079]      FIG. 3  is a view showing a display device including the scan driving circuit according to an example embodiment of the present invention. 
         [0080]    A display device  100  shown in  FIG. 3  includes a signal controller  200 , a scan driving circuit  300  (e.g., a scan driver), a data driving circuit  400  (e.g., a data driver), and a display unit  500 . 
         [0081]    The signal controller  200  generates a first driving control signal CONT 1  and a second driving control signal CONT 2  to control a display action of images according to a vertical synchronization signal Vsync for classifying frames of the images, a horizontal synchronization signal Hsync for classifying lines of one frame, a data enable signal DE for controlling an application period of a data voltage to a plurality of data lines D 1 -Dm, and a clock signal MCLK for controlling a driving frequency. The signal controller  200  receives a video signal Ims, generates image data IDATA, and transfers the image data IDATA together with the first driving control signal CONT 1  to the data driving circuit  400 . 
         [0082]    The data driving circuit  400  performs sampling and holding of an image data signal IDATA according to the first driving control signal CONT 1 . The data driving circuit  400  converts the image data signal IDATA into a plurality of data voltages VD[ 1 ]-VD[m], and transfers the image data signal to a plurality of data lines D 1 -Dm according to the first driving control signal CONT 1 . 
         [0083]    The scan driving circuit  300  generates scan signals S[ 1 ]-S[k] corresponding to scan times corresponding to a plurality of scan lines S 1 -Sk by a low level pulse according to the second driving control signal CONT 2 , and transfers the scan signals S[ 1 ]-S[k] to the scan lines S 1 -Sk. The unit scan driving circuit described with reference to  FIGS. 1 and 2  is applied to the scan driving circuit  300 . For example, the scan driving circuit  300  includes k unit scan driving circuits. 
         [0084]    The display unit  500  includes a plurality of scan lines S 1 -Sk, a plurality of data lines D 1 -Dm, and a plurality of pixels PX. 
         [0085]    Each one of the plurality of scan lines S 1 -Sk is formed in a horizontal direction. Each one of the plurality of data lines D 1 -Dm is formed in a vertical direction. 
         [0086]    Hereinafter, the pixel circuit according to an example embodiment will be described with reference to  FIG. 4 . 
         [0087]      FIG. 4  is a view showing a pixel circuit according to an example embodiment. 
         [0088]    As shown in  FIG. 4 , the pixel PX includes a driving transistor TR 1 , a switching transistor TS 1 , a capacitor CST, and an organic light emitting diode OLED. 
         [0089]    The pixel PX coupled (e.g., connected) to a data line Dj and a scan line Si from among a plurality of pixels PX is shown in  FIG. 4 . A data voltage VD[j] is supplied through the data line Dj to the pixel PX. A scan signal S[i] is supplied through the scan line Si to the pixel PX. 
         [0090]    A source of the driving transistor TR 1  is coupled to a power source voltage ELVDD, a gate of the driving transistor TR 1  is coupled to an electrode of the switching transistor TS 1 , and a drain of the driving transistor T 1  is coupled to an anode of the organic light emitting diode OLED. 
         [0091]    A cathode of the organic light emitting diode OLED is coupled to a power source voltage ELVSS. 
         [0092]    A gate of the switching transistor TS 1  is coupled to the scan line Si, and the scan signal S[i] is supplied through the scan line Si. Another electrode of the switching transistor TS 1  is coupled to the data line Dj. 
         [0093]    An electrode of the capacitor CST is coupled to the gate of the driving transistor TR 1 , and another electrode of the capacitor CST is coupled to the power source voltage ELVDD. 
         [0094]    When the switching transistor TS 1  is turned on by the scan signal S[i], the data voltage VD[j] is transferred through the data line Dj to the gate of the driving transistor TR 1 . A gate-source voltage of the driving transistor TR 1  is maintained by the capacitor CST, and the driving transistor TR 1  generates a driving current according to the gate-source voltage. The organic light emitting diode OLED emits light according to the driving current. 
         [0095]    Various example embodiments according to the present invention are feasible, and the present invention is not limited to the aforementioned example embodiments. Hereinafter, another example embodiment will be described with reference to  FIGS. 5 to 8 . 
         [0096]      FIG. 5  is a view showing a scan driving circuit according to another example embodiment. 
         [0097]    The scan driving circuit (e.g., scan driver) according to another example embodiment includes a plurality of consecutively arranged stages. Each stage (e.g., an n-th stage) receives a first scan signal GI[n−1] of an adjacent prior stage, generates a first scan signal GI[n] and a second scan signal GW[n] of a current stage, and outputs the first scan signal GI[n] to a next stage (e.g., an n+1-th stage). The next stage receives the first scan signal (e.g., GI[n]), and outputs a first scan signal GI[n+1] and a second scan signal GW[n+1]. 
         [0098]    Hereinafter, each one of the plurality of stages constituting the scan driving circuit according to another example embodiment will be referred to as a unit scan driving circuit. 
         [0099]    As shown in  FIG. 5 , a unit scan driving circuit SD 2   —   n  includes a plurality of transistors T 1 -T 7  and T 11 -T 17 , and four capacitors C 5 -C 8 . A unit scan driving circuit SD 2   —   n +1 includes a plurality of transistors T 21 -T 27  and T 31 -T 37  and four capacitors C 9 -C 12 . 
         [0100]    The unit scan driving circuit SD 2   —   n  is synchronized with a clock signal CLK 1  (e.g., in synchronization with a clock signal) to receive the first scan signal GI[n−1], and responds to an enable level of the first scan signal GI[n−1] to output a clock signal CLK 2  as the first scan signal GI[n] during one cycle of the clock signal CLK 1 . Further, the unit scan driving circuit SD 2   —   n  is synchronized with a clock signal CLK 4  to receive the first scan signal GI[n], and responds to an enable level of the first scan signal GI[n] to output a clock signal CLK 3  as the second scan signal GW[n] during one cycle of the clock signal CLK 4 . 
         [0101]    The unit scan driving circuit SD 2   —   n +1 is synchronized with the clock signal CLK 2  to receive the first scan signal GI[n], and responds to an enable level of the first scan signal GI[n] to output the clock signal CLK 1  as the first scan signal GI[n+1] during one cycle of the clock signal CLK 2 . Further, the unit scan driving circuit SD 2   —   n +1 is synchronized with the clock signal CLK 3  to receive the first scan signal GI[n+1], and responds to an enable level of the first scan signal GI[n+1] to output the clock signal CLK 4  as the second scan signal GW[n+1] during one cycle of the clock signal CLK 3 . 
         [0102]    Since the scan driving circuit according to an example embodiment is a P-channel transistor, the enable level of the scan signal is a low level. However, the present invention is not limited thereto, and the enable level is determined according to a transistor channel type of the driving circuit. 
         [0103]    The clock signal CLK 1  is transferred through a wire L 5 , and the clock signal CLK 2  is transferred through a wire L 6 . The clock signal CLK 3  is transferred through a wire L 7 , and the clock signal CLK 4  is transferred through a wire L 8 . 
         [0104]    The first scan signals (e.g., GI[n−1], GI[n], and GI[n+1] shown in  FIG. 5 ) are signals for controlling an initialization action of the capacitor of the pixel circuit. The second scan signals (e.g., GW[n−1], GW[n], and GW[n+1] shown in  FIG. 5 ) are signals for controlling threshold voltage compensation of the driving transistor, and a writing action of data on the capacitor in the pixel circuit. Influence of the second scan signal on an action of the pixel circuit and an image quality of the display device is larger than that of the first scan signal. Accordingly, in another example embodiment, widths of the wires L 7  and L 8 , through which the clock signals CLK 3  and CLK 4  are transferred, are larger than those of the wires L 5  and L 6 , through which the clock signals CLK 1  and CLK 2  are transferred. Thus, an increase/decrease time of the signal due to an RC delay may be improved. 
         [0105]    The first scan signal GI[n−1] is inputted to an electrode of the transistor T 1 , the clock signal CLK 1  is inputted to a gate of the transistor T 1 , and another electrode of the transistor T 1  is coupled (e.g., connected) to a node N 7 . 
         [0106]    The clock signal CLK 2  is inputted to a gate of a transistor T 3 . A drain of the transistor T 3  is coupled to the node N 7 , and a source of the transistor T 3  is coupled to a drain of a transistor T 2 . A gate of the transistor T 2  is coupled to a node N 8 , and a source of the transistor T 2  is coupled to a voltage VGH. 
         [0107]    A gate of a transistor T 4  is coupled to the node N 7 , and a source of the transistor T 4  is coupled to the node N 8 . The clock signal CLK 1  is inputted to a drain of the transistor T 4 . The clock signal CLK 1  is inputted to a gate of a transistor T 5 . A source of the transistor T 5  is coupled to the node N 8 , and a drain of the transistor T 5  is coupled to a voltage VGL. 
         [0108]    A gate of a transistor T 6  is coupled to the node N 8 , a source of the transistor T 6  is coupled to the voltage VGH, and a drain of the transistor T 6  is coupled to a node N 9 . A source of a transistor T 7  is coupled to the node N 9 , and a gate of the transistor T 7  is coupled to the node N 7 . The clock signal CLK 2  is inputted to a drain of the transistor T 7 . 
         [0109]    The capacitor C 5  is coupled between the gate and the source of the transistor T 6  to maintain a gate-source voltage of the transistor T 6 . The capacitor C 6  is coupled between the gate and the source of the transistor T 7  to maintain a gate-source voltage of the transistor T 7 . 
         [0110]    The first scan signal GI[n] is inputted to an electrode of a transistor T 11 , the clock signal CLK 4  is inputted to a gate of the transistor T 11 , and another electrode of the transistor T 11  is coupled to a node N 10 . 
         [0111]    The clock signal CLK 3  is inputted to a gate of a transistor T 13 . A drain of the transistor T 13  is coupled to the node N 10 , and a source of the transistor T 13  is coupled to a drain of a transistor T 12 . A gate of the transistor T 12  is coupled to a node N 11 , and a source of the transistor T 12  is coupled to the voltage VGH. 
         [0112]    A gate of a transistor T 14  is coupled to the node N 10 , and a source of the transistor T 14  is coupled to the node N 11 . The clock signal CLK 4  is inputted to a drain of the transistor T 14 . The clock signal CLK 4  is inputted to a gate of a transistor T 15 . A source of the transistor T 15  is coupled to the node N 11 , and a drain of the transistor T 15  is coupled to the voltage VGL. 
         [0113]    A gate of a transistor T 16  is coupled to the node N 11 , a source of the transistor T 16  is coupled to the voltage VGH, and a drain of the transistor T 16  is coupled to a node N 12 . A source of a transistor T 17  is coupled to the node N 12 , and a gate of the transistor T 17  is coupled to the node N 10 . The clock signal CLK 3  is inputted to a drain of the transistor T 17 . 
         [0114]    The capacitor C 7  is coupled between the gate and the source of the transistor T 16  to maintain a gate-source voltage of the transistor T 16 . The capacitor C 8  is coupled between the gate and the source of the transistor T 17  to maintain a gate-source voltage of the transistor T 17 . 
         [0115]    The first scan signal GI[n] is inputted to an electrode of a transistor T 21 , the clock signal CLK 2  is inputted to a gate of the transistor T 21 , and another electrode of the transistor T 21  is coupled (e.g., connected) to a node N 13 . 
         [0116]    The clock signal CLK 1  is inputted to a gate of a transistor T 23 . A drain of the transistor T 23  is coupled to the node N 13 , and a source of the transistor T 23  is coupled to a drain of a transistor T 22 . A gate of the transistor T 22  is coupled to a node N 14 , and a source of the transistor T 22  is coupled to the voltage VGH. 
         [0117]    A gate of a transistor T 24  is coupled to the node N 13 , and a source of the transistor T 24  is coupled to the node N 14 . The clock signal CLK 2  is inputted to a drain of the transistor T 24 . The clock signal CLK 2  is inputted to a gate of a transistor T 25 . A source of the transistor T 25  is coupled to the node N 14 , and a drain of the transistor T 25  is coupled to the voltage VGL. 
         [0118]    A gate of a transistor T 26  is coupled to the node N 14 , a source of the transistor T 26  is coupled to the voltage VGH, and a drain of the transistor T 26  is coupled to a node N 15 . A source of a transistor T 27  is coupled to the node N 15 , and a gate of the transistor T 27  is coupled to the node N 13 . The clock signal CLK 1  is inputted to a drain of the transistor T 27 . 
         [0119]    The capacitor C 9  is coupled between the gate and the source of the transistor T 26  to maintain a gate-source voltage of the transistor T 26 . The capacitor C 10  is coupled between the gate and the source of the transistor T 27  to maintain a gate-source voltage of the transistor T 27 . 
         [0120]    The first scan signal GI[n+1] is inputted to an electrode of a transistor T 31 , the clock signal CLK 3  is inputted to a gate of the transistor T 31 , and another electrode of the transistor T 31  is coupled to a node N 16 . 
         [0121]    The clock signal CLK 4  is inputted to a gate of a transistor T 33 . A drain of the transistor T 33  is coupled to the node N 16 , and a source of the transistor T 33  is coupled to a drain of a transistor T 32 . A gate of the transistor T 32  is coupled to a node N 17 , and a source of the transistor T 32  is coupled to the voltage VGH. 
         [0122]    A gate of a transistor T 34  is coupled to the node N 16 , and a source of the transistor T 34  is coupled to the node N 17 . The clock signal CLK 3  is inputted to a drain of the transistor T 34 . The clock signal CLK 3  is inputted to a gate of a transistor T 35 . A source of the transistor T 35  is coupled to the node N 17 , and a drain of the transistor T 35  is coupled to the voltage VGL. 
         [0123]    A gate of a transistor T 36  is coupled to the node N 17 , a source of the transistor T 36  is coupled to the voltage VGH, and a drain of the transistor T 36  is coupled to a node N 18 . A source of a transistor T 37  is coupled to the node N 18 , and a gate of the transistor T 37  is coupled to the node N 16 . The clock signal CLK 4  is inputted to a drain of the transistor T 37 . 
         [0124]    The capacitor C 11  is coupled between the gate and the source of the transistor T 36  to maintain a gate-source voltage of the transistor T 36 . The capacitor C 12  is coupled between the gate and the source of the transistor T 37  to maintain a gate-source voltage of the transistor T 37 . 
         [0125]    When the clock signal CLK 1  has a low level (the transistor T 1  is turned on) and the first scan signal GI[n−1] has a low level, the voltage of the node N 7  has a low level, and thus the transistor T 7  is turned on. In this case, the gate-source voltage of the transistor T 7  is maintained by the capacitor C 6 . The clock signal CLK 2  is outputted as the first scan signal GI[n]. 
         [0126]    When the clock signal CLK 1  has a low level during a next cycle and the first scan signal GI[n−1] has a high level, the voltage of the node N 7  has a high level, and thus the transistor T 7  is turned off. The transistor T 5  is turned on and the voltage of the node N 8  has a low level by the low level of the clock signal CLK 1  to turn on the transistor T 6 . The first scan signal GI[n] becomes the voltage VGH having a high level by turning on the transistor T 6 . 
         [0127]    When the clock signal CLK 4  has a low level (the transistor T 11  is turned on) and the first scan signal GI[n] has a low level, the voltage of the node N 10  has a low level, and thus the transistor T 17  is turned on. In this case, the gate-source voltage of the transistor T 17  is maintained by the capacitor C 8 . The clock signal CLK 3  is outputted as the second scan signal GW[n]. 
         [0128]    When the clock signal CLK 4  has a low level during a next cycle and the first scan signal GI[n] has a high level, the voltage of the node N 10  has a high level, and thus the transistor T 17  is turned off. The transistor T 15  is turned on and the voltage of the node N 11  has a low level by the low level of the clock signal CLK 4 , to turn on the transistor T 16 . The second scan signal GW[n] becomes the voltage VGH having a high level by turning on the transistor T 16 . 
         [0129]    When the clock signal CLK 2  has a low level (the transistor T 21  is turned on) and the first scan signal GI[n] has a low level, the voltage of the node N 13  has a low level, and thus the transistor T 27  is turned on. In this case, the gate-source voltage of the transistor T 27  is maintained by the capacitor C 10 . The clock signal CLK 1  is outputted as the first scan signal GI[n+1]. 
         [0130]    When the clock signal CLK 2  has a low level during a next cycle and the first scan signal GI[n] has a high level, the voltage of the node N 13  has a high level, and thus the transistor T 27  is turned off. The transistor T 25  is turned on and the voltage of the node N 14  has a low level by the low level of the clock signal CLK 2  to turn on the transistor T 26 . The first scan signal GI[n+1] becomes the voltage VGH having a high level by turning on the transistor T 26 . 
         [0131]    When the clock signal CLK 3  has a low level (the transistor T 31  is turned on) and the first scan signal GI[n+1] has a low level, the voltage of the node N 16  has a low level, and thus the transistor T 37  is turned on. In this case, the gate-source voltage of the transistor T 37  is maintained by the capacitor C 12 . The clock signal CLK 4  is outputted as the second scan signal GW[n+1]. 
         [0132]    When the clock signal CLK 3  has a low level during a next cycle and the first scan signal GI[n+1] has a high level, the voltage of the node N 16  has a high level, and thus the transistor T 37  is turned off. The transistor T 35  is turned on and the voltage of the node N 17  has a low level by the low level of the clock signal CLK 3 , to turn on the transistor T 36 . The second scan signal GW[n+1] becomes the voltage VGH having a high level by turning on the transistor T 36 . 
         [0133]    As described above, the clock signals CLK 3  and CLK 4  may be the second scan signals GW[n] and GW[n+1] of the unit scan driving circuits SD 2   —   n  and SD 2   —   n +1. Since the second scan signal affects the action of the pixel circuit and the image quality of the display device, the widths of the wires L 7  and L 8  are relatively larger than those of the other wires (e.g., L 5  or L 6 ). Thus, resistance of the wires may be reduced to reduce the RC delay of the corresponding signal and to reduce or minimize influence of the signal on the action of the pixel circuit and the image quality of the display device due to the RC delay. 
         [0134]      FIGS. 6A and 6B  are views showing a layout of unit scan driving circuits shown in  FIG. 5 . 
         [0135]    As shown in  FIGS. 6A and 6B , the widths of the wires L 7  and L 8 , through which the clock signals CLK 3  and CLK 4  are transferred, are larger than the widths of the wires L 5  and L 6 , through which the clock signals CLK 1  and CLK 2  are transferred. 
         [0136]    A gate electrode  32  is the gate of the transistor T 1  and of the transistor T 5 . The gate electrode  32  is coupled (e.g., connected) through a contact hole to the wire L 5 , and is coupled through a contact hole to a drain electrode  33  of the transistor T 4 . An electrode  34  of the transistor T 1  is coupled through a contact hole to a gate electrode  35 . The first scan signal GI[n−1] is inputted through the gate electrode  35 . 
         [0137]    The gate electrode  35  is coupled through a contact hole to another electrode of the transistor T 1 , and is the gate of the transistor T 7  and of the transistor T 4 . The drain of the transistor T 3  is coupled through a contact hole to the gate electrode  35 . A gate electrode  36  of the transistor T 3  is coupled through a contact hole to the wire L 6 . The gate electrode  36  of the transistor T 3  is coupled through a contact hole to an electrode  37 . The electrode  37  is coupled through a contact hole to the drain of the transistor T 7 . 
         [0138]    A gate electrode  38  is the gate of the transistor T 2  and of the transistor T 6 , and is coupled through a contact hole to an electrode  39 . The electrode  39  is coupled through a contact hole to the source of the transistor T 5  and to the source of the transistor T 4 . An electrode  40  is coupled through a contact hole to an electrode  41 . The electrode  41  is coupled through a contact hole to a wire  42 . The voltage VGH is supplied through the wire  42 . 
         [0139]    An electrode  43  is coupled through a contact hole to a wire  44 . An electrode  45  is coupled through a contact hole to the electrode  43 , and the drain of the transistor T 5  is coupled through a contact hole to the electrode  45 . 
         [0140]    The electrode  40  is coupled through a contact hole to the source of the transistor T 6 . An electrode  46  is coupled through a contact hole to the drain of the transistor T 6 . The electrode  46  is coupled through a contact hole to the source of the transistor T 7 . 
         [0141]    An electrode  47  is coupled through a contact hole to the electrode  46 . An electrode  48  is coupled through a contact hole to the electrode  46 . The first scan signal GI[n] is outputted through the electrode  47  and the electrode  48  from the electrode  46 . 
         [0142]    The capacitor C 5  is formed in an overlapping region of an electrode  49  and the gate electrode  38 . The capacitor C 6  is formed in an overlapping region of an electrode  50  and the gate electrode  35 . 
         [0143]    An electrode  51  of the transistor T 11  is coupled through a contact hole to the electrode  47 . A gate electrode  52  is coupled through a contact hole to the wire L 8 . The gate electrode  52  is the gate of the transistor T 11  and the transistor T 15 . The gate electrode  52  is coupled through a contact hole to the drain of the transistor T 14 . The first scan signal GI[n] is inputted through the electrode  47  to the electrode  51 . 
         [0144]    A gate electrode  53  is the gate of the transistor T 17  and the transistor T 14 . The gate electrode  53  is coupled through a contact hole to another electrode of the transistor T 11 . The drain of the transistor T 13  is coupled through a contact hole to the gate electrode  53 . A gate electrode  54  of the transistor T 13  is coupled through a contact hole to the wire L 7 . The gate electrode  54  of the transistor T 13  is coupled through a contact hole to an electrode  55 . The electrode  55  is coupled through a contact hole to the drain of the transistor T 17 . 
         [0145]    A gate electrode  56  is the gate of the transistor T 12  and the transistor T 16 , and is coupled through a contact hole to an electrode  57 . The electrode  57  is coupled through a contact hole to the source of the transistor T 15  and to the source of the transistor T 14 . An electrode  58  is coupled through a contact hole to an electrode  59 . The electrode  59  is coupled through a contact hole to the wire  42 . The voltage VGH is supplied through the wire  42 . 
         [0146]    An electrode  60  is coupled through a contact hole to the wire  44 . The drain of the transistor T 15  is coupled through a contact hole to the electrode  60 . The electrode  58  is coupled through a contact hole to the source of the transistor T 16 , and an electrode  61  is coupled through a contact hole to the drain of the transistor T 16 . The source of the transistor T 17  is coupled through contact holes to electrodes  61  and  62 . 
         [0147]    The electrodes  61  and  62  are coupled through the contact holes to an electrode  63 . The second scan signal GW[n] is outputted through the electrode  63 . 
         [0148]    The capacitor C 7  is formed in an overlapping region of the gate electrode  56  and the electrode  63 . The capacitor C 8  is formed in an overlapping region of the gate electrode  53  and the electrode  63 . 
         [0149]    The layouts are substantially symmetric to each other based on a boundary line A-A′. From the description of the unit scan driving circuit SD 2   —   n , the layout of the unit scan driving circuit SD 2   —   n +1 may be sufficiently understood by a person having ordinary skill in the art. Therefore, a detailed description thereof has been omitted. 
         [0150]    As shown in  FIG. 6 , the width of the wire  42  through which the voltage VGH is transferred is larger than the width of the wire  44  through which the voltage VGL is transferred. High level outputs of the scan signals outputted from the scan driving circuit constituted by the P-channel transistor are supplied from the voltage VGH. Then, current consumption due to the voltage VGH is larger than current consumption due to the voltage VGL. In the example embodiment of  FIG. 6 , the width of the wire  42  of the voltage VGH is set to be larger than the width of the wire  44  of the voltage VGL, thus reducing resistance of the wire  42  having larger current consumption. Accordingly, power consumption may be reduced. 
         [0151]    Hereinafter, a display device according to another example embodiment will be described with reference to  FIG. 7 . 
         [0152]      FIG. 7  is a view showing a display device according to another example embodiment. 
         [0153]    As shown in  FIG. 7 , a display device  600  according to another example embodiment includes a signal controller  650 , a scan driving circuit  700  (e.g., a scan driver), a data driving circuit  750  (e.g., a data driver), a light emission driving circuit  800  (e.g., an emission driver), and a display unit  850 . 
         [0154]    The signal controller  650  generates a data control signal CONT 11 , a scan control signal CONT 12 , and a light emission control signal CONT 13 , to control a display action of images according to a vertical synchronization signal Vsync for classifying frames of the images, a horizontal synchronization signal Hsync for classifying lines of one frame, a data enable signal DE for controlling an application period of a data voltage to a plurality of data lines D 1 -Dm, and a clock signal MCLK for controlling a driving frequency. 
         [0155]    The signal controller  650  processes a video signal Ims according to an action condition of the display unit  850  and the data driving circuit  750 , to generate image data signals DR, DG, and DB. The signal controller  650  transfers the scan control signal CONT 12  to the scan driving circuit  700 , transfers the data control signal CONT 11  and the image data signals DR, DG, and DB to the data driving circuit  750 , and transfers the light emission control signal CONT 13  to the light emission driving circuit  800 . 
         [0156]    The scan driving circuit  700  transfers a plurality of first and second scan signals to a plurality of scan lines Gi 1 -Gik and Gw 1 -Gwk, respectively, according to the scan control signal CONT 12 . The scan control signal CONT 12  may include the clock signals CLK 1 -CLK 4 . The scan driving circuit  700  may include the unit scan driving circuits described with reference to  FIGS. 5 and 6 . 
         [0157]    The data driving circuit  750  generates a plurality of data signals corresponding to the image data signals DR, DG, and DB, and transfers the data signals to a plurality of data lines D 1 -Dm according to the data control signal CONT 11 . 
         [0158]    The light emission driving circuit  800  transfers a plurality of light emitting signals to a plurality of light emission control lines EM 1 -EMk according to the light emission control signal CONT 13 . 
         [0159]    The display unit  850  includes a plurality of data lines D 1 -Dm extending in a column direction, a plurality of scan lines Gi 1 -Gik and Gw 1 -Gwk extending in a row direction, a plurality of light emission control lines EM 1 -EMk, and a plurality of pixels PX 1 . The plurality of data lines D 1 -Dm, the plurality of scan lines Gi 1 -Gik and Gw 1 -Gwk, and the light emission control lines EM 1 -EMk are coupled (e.g., connected) to the plurality of pixels PX 1 . 
         [0160]    A plurality of data voltages are transferred through the plurality of data lines D 1 -Dm to the plurality of pixels PX 1 . The plurality of first and second scan signals for selecting the plurality of pixels PX 1  in a row unit (e.g., row-by-row) are transferred through the plurality of first and second scan lines Gi 1 -Gik and Gw 1 -Gwk to the plurality of pixels PX 1 . The plurality of light emitting signals for controlling light emission of the plurality of pixels PX 1  in a row unit are transferred through the plurality of light emission control lines EM 1 -EMk to the plurality of pixels PX 1 . 
         [0161]      FIG. 8  is a view showing an example of one pixel from among a plurality of pixels according to another example embodiment. 
         [0162]    Referring to  FIG. 8 , one pixel PX 1  according to another example embodiment is coupled to the n-th first and second scan lines Gin and Gwn, the n-th light emission control line EMn, and the m-th data line Dm. 
         [0163]    The pixel PX includes a switching transistor Ms, a driving transistor Md, a plurality of transistors M 1 -M 4 , a capacitor CST, and an organic light emitting diode OLED.  FIG. 8  shows the transistors Ms, Md, and M 1 -M 4  as PMOS (P-channel metal oxide semiconductor) transistors as P-channel-type transistors. However, the present invention is not limited thereto, and another type of transistor may be used instead of the PMOS transistor. 
         [0164]    The switching transistor Ms includes a gate coupled (e.g., connected) to the scan line Gwn, an electrode coupled to the data line Dm, and another electrode coupled to a source of the driving transistor Md. The switching transistor Ms transfers the data voltage applied to the data line Dm to the source of the driving transistor Md when turned on by the scan signal applied to the scan line Gwn. 
         [0165]    The driving transistor Md includes the source to which the data voltage is transferred during a period when the switching transistor Ms is turned on, a gate coupled to an electrode of the capacitor CST, and a drain coupled to the source of the transistor M 4 . Another electrode of the capacitor CST is coupled to a power line to which a power source voltage ELVDD is applied. 
         [0166]    The transistor M 1  includes a gate coupled to the scan line Gwn, an electrode coupled to a gate electrode of the driving transistor Md, and another electrode coupled to a drain electrode of the driving transistor Md. The transistor M 1  is turned on by the second scan signal GW[n] applied to the scan line Gwn to diode-couple (e.g., diode-connect) the driving transistor Md. 
         [0167]    The transistor M 2  includes a gate coupled to the scan line Gin, an electrode coupled to an initialization voltage VINT, and another electrode coupled to the gate of the driving transistor Md. The transistor M 2  is turned on by the first scan signal GI[n] applied to the scan line Gin to initialize the capacitor CST. 
         [0168]    The transistor M 3  includes a gate coupled to the light emission control line EMn, a source coupled to the power line supplying the voltage ELVDD, and a drain coupled to the source of the driving transistor Md. 
         [0169]    The transistor M 4  includes a gate coupled to the light emission control line EMn, an electrode (e.g., source) coupled to the drain electrode of the driving transistor Md, and another electrode coupled to an anode electrode of the organic light emitting diode OLED. A cathode electrode of the organic light emitting diode OLED is coupled to the power line supplying the voltage ELVSS. The organic light emitting diode OLED emits light according to a current flowing through the driving transistor Md when the transistors M 3  and M 4  are turned on by the light emitting signal applied to the light emission control line EMn. 
         [0170]      FIG. 9  is a waveform chart illustrating a timing for driving the pixel shown in  FIG. 8 . 
         [0171]    As shown in  FIG. 9 , the first scan signal GI[n] having a low level is applied during a period P 1 . Then, the transistor M 2  is turned on, and thus the initialization voltage VINT is applied to the gate electrode of the driving transistor Md and the capacitor CST is charged with a voltage corresponding to ELVDD-VINT. 
         [0172]    Next, the second scan signal GW[n] having a low level is applied during a period P 2 . Then, the switching transistor Ms and the transistor M 1  are turned on. When the transistor M 1  is turned on, the driving transistor Md is in a diode-coupled (e.g., diode-connected) state. Accordingly, a gate-source voltage of the transistor Md becomes a threshold voltage of the transistor Md. 
         [0173]    In addition, the data voltage is applied from the data line Dm through the turned-on switching transistor Ms to the source of the driving transistor Md. When the data, voltage from the data line Dm is Vdata, and the threshold voltage of the driving transistor Md is Vth (e.g., a negative voltage), the gate voltage of the driving transistor Md becomes Vdata+Vth. Then, the capacitor CST is charged with a voltage corresponding to ELVDD−(Vdata+Vth). 
         [0174]    Next, the light emitting signal having a low level is applied to the light emission control line EMn during a period P 3 . Then, the transistors M 3  and M 4  are turned on, and a flowing driving current is transferred to the organic light emitting diode OLED according to a gate-source voltage difference (Vgs=(Vdata+Vth)−ELVDD)) of the driving transistor Md. In this case, the driving current is obtained by Equation 1. 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     OLED 
                   
                   = 
                   
                     
                       
                         β 
                         2 
                       
                        
                       
                         
                           ( 
                           
                             Vgs 
                             - 
                             Vth 
                           
                           ) 
                         
                         2 
                       
                     
                     = 
                     
                       
                         
                           β 
                           2 
                         
                          
                         
                           
                             ( 
                             
                               
                                 ( 
                                 
                                   Vdata 
                                   + 
                                   Vth 
                                   - 
                                   ELVDD 
                                 
                                 ) 
                               
                               - 
                               Vth 
                             
                             ) 
                           
                           2 
                         
                       
                       = 
                       
                         
                           β 
                           2 
                         
                          
                         
                           
                             ( 
                             
                               Vdata 
                               - 
                               ELVDD 
                             
                             ) 
                           
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   1 
                 
               
             
           
         
       
     
         [0175]    In Equation 1, I DLED  is a current flowing through the driving transistor Md to the organic light emitting diode OLED, and β is a constant value. 
         [0176]    Contents disclosed in the detailed description of the present application are example embodiments for describing the spirit and scope of the present invention. While this invention has been described in connection with what is presently considered to be practical example embodiments, it is to be understood that the invention is not limited to the disclosed embodiments herein, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, and their equivalents. 
       DESCRIPTION OF SOME OF THE SYMBOLS 
       [0000]    
       
         unit scan driving circuit SD 1   —   n , SD 1   —   n +1, SD 2   —   n , SD 2   —   n +1 
         transistor P 1 -P 12 , T 1 -T 7 , T 11 -T 17 , T 21 -T 27 , and T 31 -T 37   
         capacitor C 1 -C 12   
         wire L 1 -L 8 ,  17 ,  23 ,  42 , and  44   
         display device  100  and  600   
         signal controller  200  and  650   
         scan driving circuit  300  and  700   
         data driving circuit  400  and  750   
         display unit  500  and  850   
         light emission driving circuit  800   
         pixel PX and PX 1