Abstract:
A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.

Description:
RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 10/348,758 filed Jan. 23, 2003, the entire disclosure of which is incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates generally to semiconductor manufacturing and, more particularly, to germanium metal-oxide semiconductor field-effect transistor (MOSFET) devices and methods of making these devices. 
   BACKGROUND OF THE INVENTION 
   Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk MOSFET devices beyond the 0.1 μm process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance. 
   Double gate MOSFETs represent devices that are candidates for succeeding existing planar MOSFETs. In double gate MOSFETs, the use of two gates to control the channel significantly suppresses short-channel effects. A FinFET is a double gate structure that includes a channel formed in a vertical fin. Although a double gate structure, the FinFET is similar to existing planar MOSFETs in layout and fabrication techniques. The FinFET also provides a range of channel lengths, CMOS compatibility, and large packing density compared to other double gate structures. 
   SUMMARY OF THE INVENTION 
   According to one aspect, a device may include a fin and a first gate formed adjacent a first side of the fin and including a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The device may further include a second gate formed adjacent a second side of the fin opposite the first side and including a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, wherein the first thickness and the second thickness are substantially equal to a height of the fin. 
   According to another aspect, a device may include a fin and a first gate formed adjacent a first side of the fin and having a thickness ranging from approximately 1200 Å to 1500 Å. The device may further include a second gate formed adjacent a second side of the fin opposite the first side and having a thickness ranging from approximately 1200 Å to 1500 Å; and a top gate formed on top of the fin and having a thickness ranging from approximately 1200 Å to 1500 Å, where the first gate, second gate and top gate include a same gate material and wherein the same gate material comprises at least one of elemental nickel, ruthenium, rhodium, palladium, platinum, elemental titanium or ruthenium oxide. 
   According to a further aspect, a device may include a fin and a first sidewall gate structure formed adjacent a first side of the fin. The device may further include a second sidewall gate structure formed adjacent a second side of the fin and one or more additional gate structures formed under the fin, where the first sidewall gate structure, second sidewall gate structure and the one or more additional gate structures comprise at least one of elemental nickel, ruthenium, rhodium, palladium, platinum, elemental titanium or ruthenium oxide. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, explain the invention. In the drawings, 
       FIG. 1  illustrates an exemplary process for fabricating a germanium double gate MOSFET in an implementation consistent with the principles of the invention; 
       FIGS. 2-5  illustrate exemplary cross-sectional views of a germanium double gate MOSFET fabricated according to the processing described in  FIG. 1 ; 
       FIG. 6  illustrates an exemplary process for fabricating a germanium triple gate MOSFET in an implementation consistent with the principles of the invention; 
       FIGS. 7-10  illustrate exemplary cross-sectional views of a germanium triple gate MOSFET fabricated according to the processing described in  FIG. 6 ; 
       FIG. 11  illustrates an exemplary process for fabricating a germanium triple gate MOSFET in another implementation consistent with the principles of the invention; 
       FIGS. 12-17  illustrate exemplary cross-sectional views of a germanium triple gate MOSFET fabricated according to the processing described in  FIG. 11 ; 
       FIG. 18  illustrates an exemplary process for fabricating a germanium all-around gate MOSFET in an implementation consistent with the principles of the invention; 
       FIGS. 19-24  illustrate exemplary cross-sectional views of a germanium all-around gate MOSFET fabricated according to the processing described in  FIG. 18 ; 
       FIGS. 25-27  illustrate an exemplary process for thinning a FinFET channel; and 
       FIGS. 28 and 29  illustrate an exemplary process for providing local stress engineering. 
   

   DETAILED DESCRIPTION 
   The following detailed description of implementations consistent with the present invention refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements. Also, the following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims and their equivalents. 
   Implementations consistent with the principles of the invention provide germanium (Ge) FinFET devices and methods for manufacturing these devices. Using germanium to form the fin provides better mobility over other materials, such as silicon or silicon germanium, and thus, provides better drive current. 
   Exemplary Double Gate MOSFET 
     FIG. 1  illustrates an exemplary process for fabricating a germanium double gate MOSFET in an implementation consistent with the principles of the invention.  FIGS. 2-6  illustrate exemplary cross-sectional views of a MOSFET fabricated according to the processing described with regard to  FIG. 1 . 
   With reference to  FIGS. 1 and 2 , processing may begin with semiconductor device  200 . Semiconductor device  200  may include a germanium on insulator (GOD structure that includes a substrate  210 , an insulator layer  220 , and a germanium (Ge) layer  230  on the insulator layer  220 . Substrate  210  may include a germanium substrate and insulator layer  220  may include a buried oxide layer. Insulator layer  220  and germanium layer  230  may be formed on substrate  210  in a conventional manner. The thickness of insulator layer  220  may range, for example, from about 1000 Å to 5000 Å. The thickness of germanium layer  230  may range from about 200 Å to 2000 Å. It will be appreciated that germanium layer  230  is used to form the fin. 
   In alternative implementations, substrate  210  may include other semiconductor materials, such as silicon, or combinations of semiconductor materials, such as silicon germanium. Insulator layer  220  may include a silicon oxide or other types of dielectric materials. 
   A cover layer  240  (or hard mask) may be formed on top of germanium layer  230  to aid in pattern optimization and protect germanium layer  230  during subsequent processing (act  110 ). Cover layer  240  may, for example, include a silicon nitride material or some other type of material capable of protecting germanium layer  230  during the fabrication process. Cover layer  240  may be deposited, for example, by chemical vapor deposition (CVD) at a thickness ranging from approximately 200 Å to 500 Å. 
   Germanium layer  230  may be patterned by conventional lithographic techniques (e.g., optical or electron beam (EB) lithography). Germanium layer  230  and cover  240  may then be etched using well-known etching techniques to form structure  300 , as illustrated in  FIG. 3  (act  120 ). Structure  300  includes fin  310  and cover  240 . The width of fin  310  may range from approximately 75 Å to 350 Å. 
   A gate dielectric material  410  may be deposited or grown on the side surfaces of structure  300  (act  130 ), as illustrated in  FIG. 4 , Gate dielectric  410  may include a high K material (with Hf, Zr, Y, La oxide) formed by atomic layer deposition (ALD) or molecular-organic chemical vapor deposition (MOCVD). Alternatively, gate dielectric  410  may include GeON. Gate dielectric material  410  may be formed at an equivalent oxide thickness (ROT) ranging from approximately 6 Å to 14 Å. Gate dielectric  410  is shown in  FIG. 4  as being formed on the side surfaces of fin  310  and cover  240 . In alternative implementations, gate dielectric  410  may be formed only on the side surfaces of fin  310 . 
   A gate electrode layer  420  may be deposited over substrate  200 , including fin  310  (act  140 ). Gate electrode layer  420  may be formed at a thickness ranging from approximately 1000 Å to 1500 Å. A number of conductive materials may be used for gate electrode layer  420 . For example, gate electrode layer  420  may include a metal (e.g., tungsten, tantalum, aluminum, nickel, ruthenium, rhodium, palladium, platinum, titanium, molybdenum, etc.), a metal containing compound (e.g., titanium nitride, tantalum nitride, ruthenium oxide, etc.), or a doped semiconductor material (e.g., polycrystalline silicon, polycrystalline silicon-germanium, etc.). 
   Chemical-mechanical polishing (CMP) or another comparable technique may then be performed to remove excess gate material (e.g., above cover  240 ) (act  150 ), as illustrated in  FIG. 5 . As a result, gate electrode  420  may be split to form two separate gate structures, namely gates  510  and  520 . Advantageously, gates  510  and  520  are physically and electrically separated and may be separately biased based on the particular circuit requirements associated with the end device. Conventional MOSFET fabrication processing can then be used to complete the transistor (e.g., forming and implanting the source and drain regions), contacts, interconnects and inter-level dielectrics for the double gate MOSFET. 
   Exemplary Triple Gate MOSFETs 
     FIG. 6  illustrates an exemplary process for fabricating a germanium triple gate MOSFET in an implementation consistent with the principles of the invention.  FIGS. 7-10  illustrate exemplary cross-sectional views of a MOSFET fabricated according to the processing described with regard to  FIG. 6 . 
   With reference to  FIGS. 6 and 7 , processing may begin with semiconductor device  700 . Semiconductor device  700  may include a GOI structure that includes a substrate  710 , an insulator layer  720 , and a germanium (Ge) layer  730  on the insulator layer  720 . Substrate  710  may include a germanium substrate and insulator layer  720  may include a buried oxide layer. Insulator layer  720  and germanium layer  730  may be formed on substrate  710  in a conventional manner. The thickness of insulator layer  720  may range, for example, from about 1000 Å to 5000 Å. The thickness of germanium layer  730  may range from about 200 Å to 2000 Å. It will be appreciated that germanium layer  730  is used to form the fin. 
   In alternative implementations, substrate  710  may include other semiconductor materials, such as silicon, or combinations of semiconductor materials, such as silicon germanium. Insulator layer  720  may include a silicon oxide or other types of dielectric materials. 
   Germanium layer  730  may be patterned by conventional lithographic techniques (e.g., electron beam (EB) lithography). Germanium layer  730  may then be etched using well-known etching techniques to form fin  810 , as illustrated in  FIG. 8  (act  610 ). The width of fin  810  may range from approximately 75 Å to 350 Å. 
   A gate dielectric layer  910  may be deposited or grown on the surfaces of fin  810  (act  620 ), as illustrated in  FIG. 9 . Gate dielectric  910  may include a high K material (with Hf, Zr, Y, La oxide) formed by ALD or MOCVD. Alternatively, gate dielectric  910  may include GeON. Gate dielectric layer  910  may be formed at an EOT ranging from approximately 6 Å to 14 Å. 
   A gate electrode layer  920  may be formed over gate dielectric layer  910 , including fin  810  (act  630 ), as illustrated in  FIG. 9 . Gate electrode layer  920  may be formed at a thickness ranging from approximately 1000 Å to 1500 Å. A number of conductive materials may be used for gate electrode layer  920 . For example, gate electrode layer  920  may include a metal (e.g., tungsten, tantalum, aluminum, nickel, ruthenium, rhodium, palladium, platinum, titanium, molybdenum, etc.), a metal containing compound (e.g., titanium nitride, tantalum nitride, ruthenium oxide, etc.), or a doped semiconductor material (e.g., polycrystalline silicon, polycrystalline silicon-germanium, etc.). The resulting semiconductor device  700  may include three gates: gate  1010 , gate  1020 , and gate  1030 , as illustrated in  FIG. 10 . 
   Conventional MOSFET fabrication processing can then be used to complete the transistor (e.g., forming and implanting the source and drain regions), contacts, interconnects and inter-level dielectrics for the triple gate MOSFET. 
     FIG. 11  illustrates an exemplary process for fabricating a triple gate MOSFET in another implementation consistent with the principles of the invention.  FIGS. 12-17  illustrate exemplary cross-sectional views of a MOSFET fabricated according to the processing described with regard to  FIG. 11 . 
   With reference to  FIGS. 11 and 12 , processing may begin with semiconductor device  1200 . Semiconductor device  1200  may include a GOI structure that includes a substrate  1210 , an insulator layer  1220 , and a germanium (Ge) layer  1230  on the insulator layer  1220 . Substrate  1210  may include a germanium substrate and insulator layer  1220  may include a buried oxide layer. Insulator layer  1220  and germanium layer  1230  may be formed on substrate  1210  in a conventional manner. The thickness of insulator layer  1220  may range, for example, from about 1000 Å to 5000 Å. The thickness of germanium layer  1230  may range from about 200 Å to 2000 Å. It will be appreciated that germanium layer  1230  is used to form the fin. 
   In alternative implementations, substrate  1210  may include other semiconductor materials, such as silicon, or combinations of semiconductor materials, such as silicon germanium. Insulator layer  1220  may include a silicon oxide or other types of dielectric materials. 
   A gate dielectric layer  1240  may be deposited or grown on germanium layer  1230  (act  1110 ). Gate dielectric  1240  may include a high K material (with Hf, Zr, Y, La oxide) formed by ALD or MOCVD. Alternatively, gate dielectric  1240  may include GeON. Gate dielectric layer  1240  may be formed at an EOT ranging from approximately 14 Å to 16 Å. 
   A top gate electrode layer  1250  may be deposited over gate dielectric layer  1240  for forming the top gate (act  1120 ). Gate electrode layer  1250  may be formed at a thickness ranging from approximately 1000 Å to 1500 Å. A number of conductive materials may be used for gate electrode layer  1250 . For example, gate electrode layer  1250  may include a metal (e.g., tungsten, tantalum, aluminum, nickel, ruthenium, rhodium, palladium, platinum, titanium, molybdenum, etc.), a metal containing a compound (e.g., titanium nitride, tantalum nitride, ruthenium oxide, etc.), or a doped semiconductor material (e.g., polycrystalline silicon, polycrystalline silicon-germanium, etc.). 
   A cover layer  1260  (or hard mask) may be formed on top of gate electrode layer  1250  to aid in pattern optimization and protect top gate electrode layer  1250  during subsequent processing (act  1130 ). Cover layer  1260  may, for example, include a silicon nitride material or some other type of material capable of protecting the gate electrode during the fabrication process. Cover layer  1260  may be deposited, for example, by chemical vapor deposition (CVD) at a thickness ranging from approximately 200 Å to 500 Å. 
   Germanium layer  1230 , gate dielectric layer  1240 , and top gate electrode layer  1250  may be patterned by conventional lithographic techniques (e.g., optical or electron beam (EB) lithography). Germanium layer  1230 , gate dielectric layer  1240 , and top gate electrode layer  1250  may then be etched using well-known etching techniques to form structure  1300 , as illustrated in  FIG. 13  (act  1140 ). Structure  1300  includes fin  1310 , gate dielectric  1240 , top gate electrode  1250 , and cover  1260 . The width of fin  1310  may range from approximately 75 Å to 350 Å. 
   Following the formation of structure  1300 , a gate dielectric layer  1410  may be deposited or grown on the side surfaces of structure  1300  using known techniques (act  1150 ), as illustrated in  FIG. 14 . Gate dielectric  1410  may include a high K material (with Hf, Zr, Y, La oxide) formed by ALD or MOCVD. Alternatively, gate dielectric  1410  may include GeON. Gate dielectric layer  1410  may be formed at an EOT ranging from approximately 6 Å to 14 Å. 
   A gate electrode material may then be deposited over semiconductor device  1200  to form sidewall gate electrodes  1420 , as illustrated in  FIG. 14 . A gate electrode material may be formed at a thickness ranging from approximately 1000 Å to 1500 Å. Similar to top gate electrode layer  1250 , a number of materials may be used for the sidewall gate electrode material. The sidewall gate electrode material may then be planarized, using, for example, a chemical-mechanical polishing (CMP), to expose the top surface of cover  1260  and form two separate sidewall electrodes  1420 , as illustrated in  FIG. 14 . 
   Semiconductor device  1200  may then be etched to remove cover  1260  (act  1170 ), as illustrated in  FIG. 15 . During the etching, a portion of top gate electrode  1250  may be removed. For example, in one implementation, the portion of top gate electrode  1250  that is etched ranges from approximately 1000 Å to 1500 Å. 
   A top gate electrode material  1610  may then be formed on top of top gate electrode  1250  (act  1180 ), as illustrated in  FIG. 16 . For example, gate electrode material  1610  may optionally be deposited to connect sidewall gate electrodes  1420 . Gate electrode material  1610  may include a material similar to the material used for top gate electrode  1250  and gate electrodes  1420  and may be deposited to a thickness ranging from approximately 1000 Å to 1500 Å. 
   The resulting semiconductor device  1200  illustrated in  FIG. 17  may include three gates (i.e., sidewall gate  1710 , sidewall gate  1720 , and top gate  1730 ). Conventional MOSFET fabrication processing can be used to complete the transistor (e.g., forming and implanting the source and drain regions), contacts, interconnects and inter-level dielectrics for the triple gate MOSFET. 
   Exemplary All-Around Gate Mosfet 
     FIG. 18  illustrates an exemplary process for fabricating an all-around gate MOSFET in an implementation consistent with the principles of the invention.  FIGS. 19-24  illustrate exemplary cross-sectional views of a MOSFET fabricated according to the processing described with respect to  FIG. 18 . 
   With reference to  FIGS. 18 and 19 , processing may begin with semiconductor device  1900 . Semiconductor device  1900  may include a GOI structure that includes a substrate  1910 , an insulator layer  1920 , and a germanium (Ge) layer  1930  on the insulator layer  1920 . Substrate  1910  may include a germanium substrate and insulator layer  1920  may include a buried oxide layer. Insulator layer  1920  and germanium layer  1930  may be formed on substrate  1910  in a conventional manner. The thickness of insulator layer  1920  may range, for example, from about 1500 Å to 5000 Å. The thickness of germanium layer  1930  may range from about 200 Å to 1200 Å. It will be appreciated that germanium layer  1930  is used to form the fin. 
   In alternative implementations, substrate  1910  may include other semiconductor materials, such as silicon, or combinations of semiconductor materials, such as silicon germanium. Insulator layer  1920  may include a silicon oxide or other types of dielectric materials. 
   A gate dielectric layer  1940  may be deposited or grown on germanium layer  1930  (act  1810 ). Gate dielectric  1940  may include a high K material (with Hf, Zr, Y, La oxide) formed by ALD or MOCVD. Alternatively, gate dielectric  1940  may include GeON. Gate dielectric layer  1940  may be formed at an ROT ranging from approximately 6 Å to 14 Å. 
   A top gate electrode layer  1950  may be deposited over gate dielectric layer  1940  for forming the top gate (act  1820 ). Gate electrode layer  1950  may be formed at a thickness ranging from approximately 1000 Å to 1500 Å. A number of conductive materials may be used for gate electrode layer  1950 . For example, gate electrode layer  1950  may include a metal (e.g., tungsten, tantalum, aluminum, nickel, ruthenium, rhodium, palladium, platinum, titanium, molybdenum, etc.), a metal containing compound (e.g., titanium nitride, tantalum nitride, ruthenium oxide, etc.), or a doped semiconductor material (e.g., polycrystalline silicon, polycrystalline silicon-germanium, etc.). 
   A cover layer  1960  (or hard mask) may be formed on top of gate electrode layer  1950  to aid in pattern optimization and protect top gate electrode layer  1950  during subsequent processing (act  1830 ). Cover layer  1960  may, for example, include a silicon nitride material or some other type of material capable of protecting the gate electrode during the fabrication process. Cover layer  1960  may be deposited, for example, by chemical vapor deposition (CVD) at a thickness ranging from approximately 250 Å to 500 Å. 
   Germanium layer  1930 , gate dielectric layer  1940 , and gate electrode layer  1950  may be patterned by conventional lithographic techniques (e.g., optical or electron beam (EB) lithography). Germanium layer  1930 , gate dielectric layer  1940 , and gate electrode layer  1950  may then be etched using well-known etching techniques to form structure  2000 , as illustrated in  FIG. 20  (act  1840 ). Structure  2000  includes fin  2010 , gate dielectric  1940 , top gate electrode  1950 , and cover  1960 . The width of fin  2010  may range from approximately 100 Å to 500 Å. 
   Following the formation of structure  2000 , a portion of insulator layer  1920  may be removed using, for example, one or more conventional etching techniques (act  1850 ). In one implementation, insulator layer  1920  may be etched to a depth ranging from about 200 Å to about 500 Å. During the etching, a portion of insulator layer  1920  below fin  2010  may be removed, as illustrated in  FIG. 20 . For example, the etched portion of insulator layer  1920  may extend laterally below fin  2010 . In one implementation, the etched portion may extend laterally below fin  2010  about half of the width of fin  2010  from each of the side surfaces of fin  2010 . The remaining portion of insulator layer  1920  located below fin  2010  may be as small as about 0 Å, as fin  2010  is held along the source/drain direction. 
   Sidewall gates  2110  and  2120  may then be formed, as illustrated in  FIG. 21  (act  1860 ). For example, a gate dielectric layer  2130  may be deposited or grown using known techniques, such as ALD or MOCVD. Gate dielectric  2130  may include a high K material (with Hf, Zr, Y, La oxide) or GeON. Gate dielectric layer  2130  may be formed at an EOT ranging from approximately 6 Å to 14 Å. 
   A gate electrode layer  2140  may be deposited over semiconductor device  1900 . Gate electrode layer  2140  may be formed at a thickness ranging from approximately 500 Å to 1200 Å. Similar to top gate electrode layer  1950 , a number of materials may be used for gate electrode layer  2140 . Gate electrode layer  2140  may optionally be planarized, using, for example, a CMP to expose the top surface of cover  1960  and form two separate sidewall gates. 
   Cover  1960 , top gate electrode  1950 , gate dielectric  1940  may then be removed, as illustrated in  FIG. 22  (act  1870 ). For example, a conventional etching technique may be used to remove cover  1960 , top gate electrode  1950 , and gate dielectric  1940 , while minimizing effects to sidewall gates  2110  and  2120 . 
   Gate dielectric  2130  may then be grown or otherwise formed on the exposed surface(s) of fin  2010  (act  1880 ), as illustrated in  FIG. 23 . Gate dielectric  2130  may include a high K material (with Hf, Zr, Y, La oxide) formed by ALD or MOCVD. Alternatively, gate dielectric  2130  may include GeON. Gate dielectric  2130  may be grown to a thickness of about 6 Å to about 14 Å. 
   Additional gates may then be formed (act  1890 ). For example, gate electrode material  2310  may be deposited over gate dielectric material  2130  and fin  2010 , possibly connecting sidewall gates  2110  and  2120 . Gate electrode material  2310  may include a material similar to the material used for sidewall gate electrode layer  2140  and may be deposited to a thickness ranging from approximately 1000 Å to 1500 Å. Gate electrode material  2310  may then be patterned and etched to form a top gate  2410  and a bottom gate  2420 , as illustrated in  FIG. 24 . 
   The resulting semiconductor device  1900  has an all-around gate structure, with the gate material essentially surrounding fin  2010 , as illustrated in  FIG. 24 . Only a small portion of insulator layer  1920  located below fin  2010  may remain, with the rest of fin  2010  being surrounded by the gate material. The all-around gate structure may include four (or more) gates (i.e., sidewall gate  2110 , sidewall gate  2120 , top gate  2410 , and bottom gate  2420 ), as illustrated in  FIG. 24 . Conventional MOSFET fabrication processing can be used to complete the transistor (e.g., forming and implanting the source and drain regions), contacts, interconnects and inter-level dielectrics for the all-around gate MOSFET. 
   Other Implementations 
   There is a need in the art for a process for thinning a FinFET channel. This process may be performed after a damascene gate pattern and etch, but before the gate material is deposited.  FIGS. 25-27  illustrate an exemplary process for thinning a FinFET channel. As shown in the top view in  FIG. 25 , a semiconductor device  2500  may include a source region  2510  and a drain region  2520  connected by a fin  2530 . Source region  2510 , drain region  2520 , and fin  2530  may be formed using conventional techniques. 
   Gate region  2610  may then be patterned and etched, as shown in  FIG. 26 . To form the gate, a gate damascene oxide deposition may be performed and a gate opening defined. An isotropic fin etch may then be performed to reduce the exposed fin height and width, as shown by the dotted lines in  FIG. 27 . The fin height may be reduced from approximately 200-350 Å to 100-200 Å. The fin width may be reduced from approximately 30 Å to 100 Å. 
   Normally, tensile stress helps increase electron mobility, but degrades hole mobility. Compressive stress does the opposite. Therefore, there is also a need in the art for local stress engineering for a double gate MOSFET.  FIGS. 28 and 29  illustrate an exemplary process for providing local stress engineering. As shown in  FIG. 28 , semiconductor device  2800  includes an n-channel FinFET  2810  and a p-channel FinFET  2820  formed on a buried oxide layer in a conventional manner. 
   N-channel FinFET  2810  may include a fin  2812 , a gate dielectric  2814  formed on the side surfaces of fin  2812 , a cover  2816  formed on the top of fin  2812 , and a gate electrode  2818  formed covering fin  2812 . P-channel FinFET  2820  may include a fin  2822 , a gate dielectric  2824  formed on the side surfaces of fin  2822 , a cover  2826  formed on the top of fin  2822 , and a gate electrode  2828  formed covering fin  2822 . A Tetraethyl Orthosilicate (TEOS) layer  2830  may be formed covering n-channel FinFET  2810  and p-channel FinFET  2820 . 
   A photoresist  2910  may be formed covering, for example, n-channel FinFET  2810 , as shown in  FIG. 29 . An ion, such as N + , Xe + , etc., may be implanted to release stress from p-channel FinFET  2820 , while keeping the stress on n-channel FinFET  2810 . In an alternate implementation, photoresist  2910  may be formed covering p-channel FinFET  2820 . 
   CONCLUSION 
   Implementations consistent with the principles of the invention provide double, triple, and all-around gate germanium FinFET devices and methods of manufacturing these devices. 
   The foregoing description of exemplary embodiments of the present invention provides illustration and description, but is not intended to be exhaustive or to limit the invention to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. 
   For example, in the above descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of implementations consistent with the present invention. These implementations and other implementations can be practiced, however, without resorting to the details specifically set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention. In practicing the present invention, conventional deposition, photolithographic and etching techniques may be employed, and hence, the details of such techniques have not been set forth herein in detail. 
   While series of acts have been described with regard to  FIGS. 1 ,  6 ,  11 , and  18 , the order of the acts may be varied in other implementations consistent with the present invention. Moreover, non-dependent acts may be implemented in parallel. 
   No element, act, or instruction used in the description of the present application should be construed as critical or essential to the invention unless explicitly described as such. Also, as used herein, the article “a” is intended to include one or more items. Where only one item is intended, the term “one” or similar language is used. The scope of the invention is defined by the claims and their equivalents.