Abstract:
A very low power analog pulse processing system implemented as an ASIC useful for processing signals from radiation detectors, among other things. The system incorporates the functions of a charge sensitive amplifier, a shaping amplifier, a peak sample and hold circuit, and, optionally, an analog to digital converter and associated drivers.

Description:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH 
     This invention was made with Government support under Contract DEAC04-94AL85000 awarded by the U.S. Department of Energy. The Government has certain rights in the invention. 
    
    
     CROSS REFERENCE TO RELATED APPLICATIONS 
     Not applicable. 
     BACKGROUND OF THE INVENTION 
     Conventional pulse processing electronics for detectors and sensors consume relatively large amounts of power and are often unsuitable for use outside the laboratory because of their size. Lower power charge preamplifier circuits have been successfully developed. However, for long term unattended monitoring applications, the entire pulse processing system (preamplifier, shaping amplifier, sample-hold) must also be a very low power solution. Also, due to system-size constraints and ease of use it is highly desirable to integrate said pulse-processor system onto a single silicon chip. No such system exists at the present time. The system described herein satisfies this unmet need in the technology. It is particularly useful for processing the signals from semiconductor radiation detectors but can be used for other detector and sensor signals as well. 
     BRIEF SUMMARY OF THE INVENTION 
     The system of circuits disclosed herein is intended to perform the same functions as the separate charge sensitive amplifier, shaping amplifier, and peak sample and hold systems already in use in the prior art. However, the present system was created to minimize packaging volume and power consumption and is intended to be implemented as an application specific integrated circuit (ASIC). This core system can be designed to interface with an off-chip flash analog to digital converter (ADC) for subsequent height analysis, or the system can be expanded to include the ADC, with or without its drivers, as part of the ASIC albeit with a higher power budget. Low average power for the present system is achieved by making the high current functions enabled only when the desired input pulse amplitude is detected. Novel circuit design techniques are used to minimize power consumption while providing good linearity and low-noise circuit performance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of the various major subsystems in the system of this invention and how they cooperate with each other. 
     FIG. 2 is an electrical schematic of one implementation of the charge sensitive amplifier subsystem. 
     FIG. 3 is an electrical schematic of one implementation of the shaping amplifier subsystem. 
     FIG. 4 is an electrical schematic of one implementation of a circuit to provide biasing to the reference inputs of an external flash ADC. 
     FIG. 5 is an electrical schematic of one implementation of the peak sample and hold subsystem. 
     FIG. 6 is a graph showing the ASIC charge and shaping amplifier gain, showing output amplitude as a function of injected charged. 
     FIG. 7 is a graph of the pulse height spectrum of a  57 Co source measured by this ASIC. 
     FIG. 8 is a graph of the pulse height spectrum of a  133  Ba source measured by this ASIC. 
     FIG. 9 is a schematic diagram of a switch circuit used to isolate the peak sensing capacitor. 
     FIG. 10 is a schematic diagram of an alternative shaping amplifier circuit that includes a dc recovery circuit. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The circuit was designed to operate off of a 7 V (±3.5 V) power supply and to be used with a cadmium zinc telluride (CZT) detector to provide pulse height spectroscopy from 0 to 1.0 MeV with an energy resolution of at least 20 keV FWHM. Assuming a mean electron-hole pair creation energy in CZT of 5.0 eV these design specifications translate into a “charge gain” of 58.6 μV/keV (133 mV/fC) and an equivalent noise charge (ENC) of less than 1700 electrons rms. However, by altering the effective feedback capacitance in the circuit, one may alter the gain for use with other detectors besides CZT. For instance, by increasing the “charge gain” of the circuit it should be possible to use the circuit as a readout for silicon p-i-n detectors attached to scintillators. 
     DESIGN OVERVIEW 
     The ASIC performs the three analog pulse processing functions used in a semiconductor pulse height spectrometer: charge amplification, shaping, and peak sensing. A simplified block diagram of the ASIC circuit is shown in FIG.  1 . The pulse processing ASIC shown herein is designed to work with a companion flash ADC and microcontroller to function as a complete ultra low-power gammaray pulse height spectrometer. However, these functions can also be integrated into the ASIC. In addition to its pulse processing functions, the ASIC also contains a circuit for biasing the external flash ADC reference input. The ASIC contains a circuit to provide common and precise reference voltages to all pertinent circuits in the ASIC. Finally the ASIC contains logic circuits that allow circuit functions to be enabled and disabled as required for function and power management. 
     The ASIC was designed to draw approximately 2 mA of current in the “idle mode” (no valid pulses present). When a pulse of appropriate amplitude triggers the circuit, its current draw will double. The circuit will then continue to draw 4 mA for the remainder of the pulse acquisition time (&lt;10 μs). Additional current will also be drawn during pulse acquisition to provide a reference for the external flash ADC. The amount of additional current drawn will depend on the ladder network used in the external ADC. 
     This design uses a band-gap voltage reference to set the operating dc voltages of the entire system. Since the band gap voltage is very stable over temperature and power supply voltage, the system can be designed to exploit this stability. The voltage references block generates three dc voltages for the system. The 1.25 V analog reference voltage (V ref ) sets the steady state dc voltages for the charge-amplifier output. Since the dc gain of the shaper-amplifier, peak-detector and buffer amplifier is unity, the charge-amplifier sets the dc operating voltages of these function blocks. Therefore the output of the buffer is a peak-held dc voltage relative to V ref  (1.25 V). 
     The voltage reference block provides a threshold dc voltage to the comparator. This voltage is slightly above V ref  and is adjusted to reject circuit noise. When the peak-detector output rises above the threshold voltage (V thresh ) the pile-up rejection circuit and ladder bias circuits are enabled. 
     The voltage reference block also provides the high and low bias voltages to the ADC resistor ladder bias network. The high voltage is adjusted to approximately 6.0 V while the low voltage is V ref  (1.25 V). The ladder bias block takes these low-current voltage references and applies these voltages to the low-valueladder resistor of the ADC converter. For the sake of minimizing system power consumption, the ladder bias circuit is enabled by the comparator when a nuclear pulse above V thresh  is detected. The ladder resistor bias is maintained for the duration of the measurement which, in this design, is approximately 10 μs. After the sample has been digitized, the system is reset and returns to the lower power mode of operation (and remains in low power mode until another pulse of sufficient amplitude is produced by the detector). 
     The comparator block is used for four critical system functions: peak-detector bias control, ladder bias enabling, pile-up rejection and system noise rejection. These functions are enabled or disabled based on the sensing of a V thresh  pulse input. The comparator provides bias to the output of the peak-detector such that the circuit is bi-directionally linear until the comparator senses an input pulse of amplitude greater than V thresh . When the comparator senses this input pulse, the peak-detector bias is removed and the peak-detector accurately follows the peak amplitude of the input. The peak-detector capacitor holds this voltage with very little change during the time interval required for ADC conversion. 
     The comparator also enables the pile-up rejection circuit. The pile-up rejection circuit controls the ac gain of the shaper-amplifier in the embodiment illustrated in FIG.  1 . The shaper amplifier ac gain is allowed to be relatively large (20 to 30) when waiting for a V thresh  input pulse. After a pulse from the detector that is above V thresh  has tripped the comparator, the shaper-amplifier gain is allowed to stay high for a predetermined period of time (approximately 3 μs to 5 μs). This time is allowed to be long enough to completely capture one pulse. After this time, the ac gain of the shaper-amplifier is actively reduced to near unity. This gain reduction effectively eliminates the possibility of the desired pulse from being altered by a later arriving pulse greater than V thresh  in amplitude. As will be discussed in more detail below, the peak capacitor can also be isolated by an electronic switch at the capacitor to achieve the same effect. 
     As stated earlier, the buffer is a unity gain high input-impedance amplifier with very low input offset current. This buffer amplifier isolates the small peak-hold capacitor from the relatively low impedance of the ADC. This amplifier is designed to drive relatively large capacitance loads of 20 pF. This is required because the flash ADC used in the present system is essentially a string of paralleled gate inputs (vs. a single MOS input; which would be a relatively low input-capacitance). The base-currents of the input of the buffer stage were canceled by a current mirror arrangement. This technique minimizes the peak-detector droop caused by the base currents of the input stage. Base current cancellation typically results in very small effective input current although the sign of this current may be either positive or negative. Because it is nearly impossible to exactly cancel the input base currents, a very small net input current remains (though much smaller in amplitude than if one does not use a canceling technique at all). Using a BiCMOS ASIC one can use MOS transistors to design high impedance input stages with no input bias current and use the bipolar transistors in the gain stages of the amplifier for high transconductance with minimum bias current. 
     Charge Amplifier 
     A simplified schematic for the charge amplifier in the pulse processing ASIC is shown in FIG.  2 . The design intention for this amplifier was to provide a large charge-gain to bias-current ratio and make the output dc voltage fixed to a band-gap reference voltage. This dc output subsequently becomes a reference voltage for the entire pulse-processing ASIC. The use of an active-load differential-amplifier provides a high-gain per unit bias current and allows for common mode noise rejection at the front-end of the amplifier. Current sources I 1  and I 3  use emitter resistors to minimize noise. 
     The external matched JFET pair (J 1  and J 2 ) is used as a differential-amplifier configuration with Q 1  and Q 2  as the heart of the differential amplifier. Q 6  sets the bias voltage of the base of Q 2 , and- thus by feedback- the gate of J 1 . The current-mirror, Q 7  and Q 8  allow for V out  to be biased by V bias . These external JFETS could also be integrated into the ASIC. 
     This amplifier was designed to operate at approximately 0.5 mA total current draw with 40 μA (I 1  and I 3  ) of bias in each of the JFETS. This amplifier is an inverting transimpedance amplifier with R f /C f  as the feedback impedance. The differential-amplifier (Q 1 , Q 2 , Q 3 , and Q 4 ) is biased at 140 μA (I 2 ). Q 5  is a buffer transistor that also supplies a required dc bias shift from the collector Q 1  and the output, V out . The amplifier output, V out , is biased to the system V ref  (1.25 V) by the on-chip band-gap voltage reference. This bias voltage, represented by V bias  sets the dc voltage at V out . Transistors Q 6 , Q 7 , Q 8  and resistors R 1 , R 2 , and R 3  comprise a current-mirror bias circuit through which the dc voltage at V out  is set. V out  will be equal to V bias  when R 1 , R 2  and R 3  are equal values and Q 6 , Q 7 , and Q 8  are matched transistors. R 1 , R 2  and R 3  were chosen to be 15 kΩ. These resistor values provide a good compromise between circuit performance and power consumption. Ideally, for good circuit performance, R 3  should be small to allow the emitter of Q 5  to control the collector of Q 8  and the associated capacitance at this node, but this would require more power given this ASIC topology. The bias voltage is selected to be relatively low for good dynamic range yet large enough to provide adequate bias voltages around the amplifier. Given these constraints, V bias  was chosen to be 1.25 V; a standard band-gap reference voltage. This amplifier is inherently very stable and of relatively high gain due to the single-stage of inverting-gain using high-impedance active loads. The amplifier circuit is phase-compensated by using a parasitic 1 pF capacitor added to the base, collector capacitance of Q 1 . The external JFETS are n-channel epitaxial devices manufactured by Temic (part# SST404) and have a very small V GS(off)  voltage of−2.5 V maximum and −0.5 V minimum. The SST404 is a dual monolithic part in a surface mount package. The feedback resistor, R f , is a 20 MΩ surface mount resistor. To maintain a large system charge-gain with minimum power consumption, the feedback capacitor C f  is the parasitic capacitance of R f ; this capacitance is approximately 0.15 pF. 
     Sharping Amplifier 
     A simplified block diagram of the shaper-amplifier design used in this ASIC is shown in FIG.  3 . The feedback components, R 1 , C 1 , R 2 , C 2  and the impedance of Q 1  control the ac gain of this circuit. The dc gain of this circuit is unity due to C 2  which is a large value (0.1μF) capacitor. C 1  is chosen in combination with R 1  and R 2  to provide the desired gain and filtering characteristics of the shaper-amplifier function. V gain  is a digital “like” signal provided by the comparator and pile-up rejection block; V gain  either holds Q 1  in saturation or cutoff. The transistor impedance is very low when the device is in saturation (V gain  high) and therefore the ac gain of the amplifier is set by the passive feedback components. When V gain  is low, the transistor is off and the collector to emitter impedance is very high forcing the ac gain of the amplifier to unity. This gain control allows the rejection of charge- pulses after the initial sampling of a desired pulse. A gain ratio of approximately 20:1 to 40:1 is easily obtained using this technique. This range is typically enough to reject undesired pulses during the processing of a captured sample. In this design R 1  was chosen to be 30 kΩ with C 1  equal to approximately 10 pF. R 2  is set to 1.5 kΩ to provide the desired overall charge-gain of approximately 110 mV/fC and allow for a relatively large, high to low gain ratio. 
     The analog approach to pile-up rejection just described has one serious flaw. When Q 1  is turned off (immediately after a charge pulse has been peak-held) a small parasitic voltage pulse is generated at the output of the shaper-amplifier, effectively limiting the low-level sensitivity of this design. For this ASIC, the low-level limit due to this parasitic pulse is approximately 3 fC. Since this system uses a flash ADC, the system acquires a sample and resets in less than 15 μs. Thus, it is possible to use the ASIC without the pile-up rejection circuit if the rate of input pulses is relatively low. An alternative design of the pile-up rejection block has been done to eliminate the parasitic pulse. This new design leaves the shaper-amplifier gain constant but disables the peak-detector circuit instead. This new design appears to have no parasitic glitches. This design is basically a switch that isolates the peak sensing capacitor from inputs from the peak sample and hold subsystem discussed below in response to a control signal from the pile-up rejection circuit. As shown in FIG. 9, this circuit replaces the components immediately downstream from node  50  in FIG. 5, with the Peak-Hold Capacitor of FIG. 9 being the same as C peak  in FIG.  5 . 
     This type of circuit has a tendency to oscillate as the initial pulse decays. After a unidirectional pulse has been amplified, typically as a large positive pulse, the voltage is now greater than the reference voltage level at V in . The dc recovery circuit will be enabled by a reset function and will allow a low time constant circuit to charge C 2  to the desired reference voltage of the system thus allowing for improved overall precision with a fast pulse recovery. This allows for a series of pulses with a high relative frequency to be measured accurately. Those skilled in the art will understand that the performance of this subsystem in terms of recovery time and noise minimization by employing any one of a variety of known dc recovery circuits. The basic scheme for this implementation of a dc recovery circuit with the shaping amplifier is shown in FIG.  10 . The changes from FIG. 3 are to the left of node  30  in that figure and below node  30  in FIG.  10 . 
     ADC Reference Input Biasing 
     The particular pulse processing ASIC described here is designed to work with another circuit module which incorporates an ADC and histogramming memory features. The ADC in the companion module is an 8 bit flash ADC that utilizes a rather low impedance resistor “ladder” network on its reference inputs. Thus biasing the ladder consumes a sizable amount of power. To minimize system power consumption, the ASIC described here incorporates a ladder bias supply which biases the ADC only when the comparator has detected a pulse of valid amplitude 
     A diagram of the circuit used in the ASIC to supply the required dc reference voltages for the flash ADC ladder resistor network is shown in FIG.  4 . This circuit comprises two op-amp circuits, A 1  and A 2  performing a dual follower function. A 1  applies V High  to the top of R ladder  while A 2  applies V Low  to the bottom of R Ladder . These voltages represent the highest and lowest measurable voltages the ADC will process at its input. Since the ladder resistor can range from 2 kΩ to 5 kΩ and the voltage range of the input will be approximately 5 volts, 2.5 mA (max) is required to bias this resistance. To minimize the system power requirements it is highly desirable to apply this bias voltage for the least amount of time possible. Thus this circuit is designed to apply V High , and V Low  to R Ladder  only when a pulse has triggered the comparator and to be reset to zero bias shortly after the acquisition of the pulse. This is accomplished by using the comparator to bias the circuit via the V bias  node when a pulse trips the threshold voltage. 
     When biased “on”, the opamps require approximately 160 μA of current each. They are designed to turn on quickly, have low-offset voltages and operate at minimum possible current. 
     Peak Detector 
     The final stage of analog pulse processing that is performed by the ASIC is the peak sample, and hold function. In conventional pulse processing systems the peak sample and hold is usually incorporated as part of the ADC, but here it has been incorporated as part of the pulse processing ASIC. 
     A simplified schematic of the peak detector used in this ASIC design is shown in FIG. 5. I 1  is approximately 120 μA and I 2  is approximately 50 μA. I idle  is 5 μA or 0 μA and is controlled by the comparator. I idle  is turned off when the output of the comparator senses an V thresh  input pulse. C peak  is an external  400  pF capacitor, although it could also be incorporated on the ASIC. A pnp (Q 1 ,Q 2 ) based differential-amplifier was chosen for this design. The input is biased at the system V ref  (1.25 V) from the shaper-amplifier. The input is on the base of Q 1  and the feedback from the peak hold capacitor, C peak , is feedback to the base of Q 2 . After a positive going peak has been held on C peak  and the input returns to base line dc, Q 2  will be cutoff and therefore the base current of Q 2  will be near zero and not discharge C peak . Using this topology with an npn design would undesirably leave an active base on C peak  and allow a very significant discharge path. Q 3  is an emitter follower stage that guarantees that Q 2  cannot be saturated. When the circuit is idling or following a positive going signal Q 3  biases the collector to emitter voltage of Q 2  at approximately one diode drop. With I idle  “on” this circuit is essentially a low-offset, unidirectional follower circuit. For good low-level accuracy and low overshoot I idle  is sourced from emitter of Q 5  until the threshold comparator trips and then I idle  is reduced to zero and a peak-hold is obtained. The offset of this design is also low because the Q 3  base-current is relatively small compared to the collector currents of Q 1 -Q 2 ; allowing the differential amplifier to control the peak very accurately. The overshoot is essentially zero because the circuit is actively servoing the C peak  with all devices on and in the linear region of operation before V thresh  is sensed. When I idle  is turned off, the emitter current of Q 5  is determined by the charge current into C peak  and the circuit is very linear in operation. When the peak of the input has occurred and the input is decreasing, Q 2  and Q 5  are turned off and the current-leakage paths from C peak  are very low. 
     One problem with this type of peak-detector design is that there is a limit to the amplitude of the detected signal. This limitation is the reverse breakdown voltage of Q 5  (approximately 5.6 V). To make this limitation have the least impact on the system performance, diode D 1  was added. This arrangement holds the collector voltage, Q 2 , at one diode drop above ground plus the saturation voltage of Q 4  after a peak has been held and Q 4  is on hard. The addition of D 1  allows one diode drop greater peak voltage out before reverse breakdown of Q 5  occurs than if D 1  was not used (approximately 6.9 volts compared to 6.3 volts). 
     Finally, Q 6  and R 10  make up a reset network. The system reset circuitry biases V reset  high to remove the charge on C peak  while R 10  limits the current Q 5  can provide to ground during the reset process. 
     Results 
     A version of the pulse processing circuit was built using Honeywell&#39;s ALB1A bipolar ASIC fabrication process. The resulting ASIC dice were 4 mm×5 mm in size and were packaged in a 40 pin leadless chip carrier (LCC) for initial testing. The packaged ASICs were attached to a standard FR 4  printed circuit board with surface mount external components for testing. Radiation detectors were attached to the ASIC test board using microdot and BNC connectors. 
     The gain and linearity of the ASIC module were measured by injecting a voltage pulse from an Ortec 419 Precision Pulse Generator into the input of the ASIC using an Ortec “charge terminator” (2 pF capacitor terminated 100 Ω to ground). The tail pulse generator and terminator had previously been calibrated with a silicon detector and the amount of charge injected into the ASIC was known to good precision. After injecting the fixed amplitude charge pulses into the ASIC input, the distribution of pulses produced at the output of the shaping amplifier was monitored with an Aptec Series 5000 multi-channel analyzer (MCA). The centroid of the peaks produced in the pulse height spectrum were used to determine the gain and linearity of the ASIC as shown in the graph in FIG.  6 . 
     The output of the shaper amplifier was plotted in FIG. 6 versus a calibrated fixed charge pulse provided to the preamplifier input. Open symbols are measured laboratory data and the solid line is a linear fit to the data using a “least squares” algorithm. These data allow a determination of the overall system (preamplifier and shaping amplifier) gain and linearity. The slope of the least squares fit yields a system gain of 110 mV/fC (18 μV/electron), close to the original design specification. The correlation coefficient of the fit indicates a linearity of better than 0.1%. 
     By measuring the width of the peaks in the pulse height spectra (using the apparatus just described), the noise of the circuit (ENC) was found to be 538 electrons rms,(1270 electrons FWHM); well within the design specifications. 
     The ASIC was also operated in its intended mode as a gamma-ray spectrometer using two different detectors. A gamma-ray pulse height spectrum obtained by attaching a silicon p-i-n photodiode (Hamamatsu S1223) to the ASIC in an ac coupled configuration is shown in FIG.  7 . The pulse height spectrum shown in FIG. 7 was obtained by irradiating a silicon p-i-n photodiode (Hamamatsu S1223) with a  57 Co source. The pulse processing ASIC described above was used to amplify and shape the pulses from the detector. The 122 keV peak is clearly visible. 
     The same commercial pulse height analyzer (Aptec Series 5000) was used to histogram the pulse amplitudes, and a  57 Co source was used to irradiate the detector. FIG. 8 shows a pulse height spectrum obtained with a CZT detector attached to the detector, and irradiated with a  133 Ba source. 
     The pulse height spectrum was obtained by irradiating a 15 mm×15 mm×2 mm CZT detector with photons from  133 Ba and reading out the detector with the ASIC described in the text. The CZT detector was of “spectroscopic grade” and was operated at a bias of 100 V. The peak-detector circuit was also evaluated for:droop (decay of the peak held voltage as a function of time), offset and overshoot. The droop measures approximately 100 μV/μs and the offset is less than 10 μV, this offset includes the buffer circuit. The peak-detector exhibits no measurable overshoot. The droop is caused by the comparator circuit input bias current. This droop is perfectly acceptable for this application due to the rapid digitization of the flash A/D. The peak detector need only hold the sample for approximately 10 μs before digitization, which implies a 1 mV maximum error; this is well below the overall system noise floor.