Abstract:
An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 11/705,896, filed Feb. 13, 2007. This application is incorporated by reference herein in its entirety and for all purposes. 
    
    
     TECHNICAL FIELD 
     Embodiments of the invention relate to non-volatile memory devices, and, more particularly, to non-volatile memory device bit line drivers. 
     BACKGROUND OF THE INVENTION 
     Memory read, erase or program operations are conventionally executed in response to external signals provided to the memory by a controller (not shown) or other memory access device (also not shown). A bit line coupled to a selected memory cell to be read, erased or programmed must be pre-charged or prepared for executing a particular memory operation.  FIG. 1  shows a block diagram of a prior art bit line driver  101  coupled to a bit line of a memory array. The bit line driver  101  is designed to meet a number of operating requirements during a memory operation. For example, during a programming operation, the bit line driver  101  receives data to be programmed to a selected memory cell, and applies the programming data signal to the bit line. Memory having multi-level cells require multiple programming voltages and/or programming pulse widths corresponding to combinations of the multiple data bits that can be stored in the memory cell. 
     An input data bit received by the memory device are applied to an inverter  105  through an NMOS transistor  103  that is continuously turned ON by a supply voltage Vcc coupled to its gate. The output signal of the inverter  105  is applied to a node  115  through an NMOS bias transistor  110  that receives a predetermined bias voltage. A number of components are coupled to the node  115  to allow the bit line driver  101  to perform several functions. The node  115  is coupled to the corresponding bit line by an NMOS transistor  119 , and also through an NMOS transistor  117  to an output of an inverter  125 , which precharges the node  115  to a voltage Vcc or Vss depending on a voltage applied to the input of the inverter  125 . The respective gates of the transistors  117 ,  119  are coupled to an output of an inverter  123  so that both transistors  117 ,  119  are turned ON responsive to a low applied to the input of the inverter  123 . The output node  115  is also coupled to a state machine through an inverter  121  that communicates signals to the state machine during programming operations. For example, the state machine may receive an instruction set to program a particular block of memory. In response, the state machine signals the bit line driver  101  to precharge the bit line or it may cause a predetermined programming voltage to be applied to the selected bit line during a programming operation. 
     In operation, the manner in which the bit line driver  101  responds to the input data bit depends upon the initial state of the output node  115 . For example, the state machine may interpret a low at the output of the inverter  121  as indicating that a program operation is needed to change the state of a memory cell being programmed. Thus, if the output node  115  is initially at V CC , an active operation occurs in which the input data bit applied to the inverter  105  controls the state of the output node  115 . Therefore, if the input data bit is high, the output node  115  will be pulled to the low (V SS ) at the output of the inverter  105  through the transistor  110 , which is turned ON by the bias voltage. If the input data bit is low, the output of the inverter  105  will by high. In such case, the transistor  110  will be turned OFF. Although the inverter  105  will be unable to drive the output node  115  high, the output node  115  will nevertheless remain high because of the charge on a capacitor  107  that is coupled to the output node  115 . 
     If the state machine interprets a low at the output of the inverter  121  as calling for an active operation, it may interpret a high at the output of the inverter  121  as calling for a null operation in which the input data applied to the inverter  105  does not control the state of the output node  115 . In the case of a null operation, the output node  115  will initially be discharged to V SS . If the input data bit is high, the output of inverter  105  will be low, and the output node  115  will therefore remain at V SS . Finally, if the input data bit is low, the output of the inverter  105  will be high. The transistor  110  will be turned ON by the bias voltage to allow the output of the inverter  105  to charge the output node  115 . However, the voltage of the output node  115  will increase only until it reaches the bias voltage less the threshold voltage of the transistor  110 , at which point the transistor  110  will turn OFF. By choosing the magnitude of the bias voltage so that it is substantially equal to V T -V SS , where V T  is the threshold voltage of the transistor  110 , the output node  115  will remain at V SS , thereby continuing to indicate a null operation to the state machine. Thus, by keeping the magnitude of the bias voltage at substantially equal to V T -V SS , the bit line driver  101  can maintain the proper voltage on the output node  115  for all values of the input data bit in both the active operation and the null operation. The operation of the bit line driver  101  for both values of input data bits in the active operation and the null operation are summarized in Table 1, below: 
     
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                 Initial State 
                   
                 Final State 
               
               
                   
                   
                 of Node 115 
                 Input Data 
                 of Node 115 
               
               
                   
                   
               
             
             
               
                   
                 Case #1 
                 Vcc 
                 1 
                 Vss 
               
               
                   
                 Case #2 
                 Vcc 
                 0 
                 Vcc 
               
               
                   
                 Case #3 
                 Vss 
                 1 
                 Vss 
               
               
                   
                 Case #4 
                 Vss 
                 0 
                 Vss 
               
               
                   
                   
               
             
          
         
       
     
     Unfortunately, it is difficult to maintain the bias voltage at the correct magnitude since the bias voltage can vary significantly with different process variations and as the temperature of the integrated circuit substrate varies. As a result, the voltage of the output node  115  can rise to unacceptable levels in the null operation when the input data bit is low. More specifically, if the voltage of the output node  115  increases above the threshold voltage of an NMOS transistor (not shown) in the inverter  121 , the NMOS transistor and a complementary PMOS transistor (not shown) connected in series with the NMOS transistor will both be ON at the same time. Insofar as a bit line driver  101  is provided for each column of a memory device, the amount of power consumed by the transistors in the inverter  121  can be considerable. Also, in some cases, the inverter  121  may apply a signal to the state machine that incorrectly calls for an active operation. 
     There is, therefore, a need for a bit line driver in a non-volatile memory device and method for generating a bias voltage that ensures the correct operation of the bit line driver for all operating conditions despite process and temperature variations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing a bit line driver coupled to a respective bit line in an array of memory cells. 
         FIG. 2  is a block diagram showing a bias voltage circuit coupled to a bit line driver of  FIG. 1 , according to an embodiment of the invention. 
         FIG. 3  is a schematic diagram of a bias voltage circuit coupled to a bit line driver, according to an embodiment of the invention. 
         FIG. 4  is a block diagram showing a flash memory device having a bias voltage circuit coupled to a plurality of bit line drivers respectively coupled to a plurality of bit lines, according to an embodiment of the invention. 
         FIG. 5  is a simplified block diagram of a processor-based system including the flash memory device of  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the invention are directed to non-volatile memory devices whose bit lines of a memory array are coupled to bit line drivers that includes a bias voltage generator. Certain details are set forth below to provide a sufficient understanding of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention. 
       FIG. 2  shows a bit line driver system  300  that includes a bit line driver  301  coupled to receive a BIAS signal from a bias voltage circuit  350  according to an embodiment of the invention. The bit line driver  301  receives an input data signal and controls the voltage level applied to a respective bit line, as previously described. The bit line driver  301  is the same as the bit line driver  101  shown in  FIG. 1 , except that the BIAS voltage signal is generated by the bias voltage circuit  350 . The bias voltage circuit  350  includes a bias voltage generator  354  that generates the appropriate bias voltage applied to the bit line driver  301 . Because of the time required for coupling the BIAS voltage signal to each of the bit line drivers  301 , which will be described further, the bias voltage circuit  350  also includes a pre-charging circuit  352  that expedites the time for applying the BIAS signal to the gate of the transistor  110  ( FIG. 1 ) in the bit line driver circuit  101 . The combined functionality of the bias voltage generator  354  and the pre-charging circuit  352  provides advantageous operating capabilities for both values of input data bits in both active operation and null operation, as described further below. 
       FIG. 3  is a schematic drawing of a bit line driver system  400  that illustrates in more detail the bit line driver system  300  of  FIG. 2 . The bit line driver  401  is the same as the bit line driver  101  of  FIG. 1 , except that the gate of an NMOS bias transistor  410  is coupled to the output of a bias voltage circuit  450 . Several of the components in the bit line driver  401  are the same as components in the bit line driver  101  in  FIG. 1 , and are identified by the same reference numbers. In the interest of brevity, an explanation of the structure and operation of these same components will not be repeated. As described, a bias voltage circuit  450  utilizes the combination of a bias voltage generator  454  and a pre-charging circuit  452  to generate a BIAS signal that is applied to the transistor  410 . The outputs of the bias voltage circuit  450  and the pre-charging circuit  452  are coupled to a bias node  440  that provides a bias signal to control the bias transistor  410  of the bit line driver  401 . In such manner, the bias voltage circuit  450  is coupled to each of the bit line drivers  401  that are in turn coupled to each of the bit lines in the memory array. The bias node  440  is additionally coupled to a low pass filter that is formed by a series resistor  442  and a capacitor  444  coupled to ground. This low pass filter attenuates noise and other interference before the generated bias signal is applied to the bias transistor  410 . 
     The bias voltage generator  454  includes a current mirror circuit  473  having a pair of NMOS transistors  478   a,b  coupled between two voltage supplies Vcc and Vss. The current mirror circuit  473  may be the current mirror circuit  473  in the bias voltage generator  454  or any other embodiment as known in the art. The transistors  478   a,b  are coupled together in a manner such that a current is generated through the drain-to-source channel of the transistor  478   b  that mirrors a current through the drain-to-source channel of the transistor  478   a , which is generated by a current source  475  coupled to the drain of the transistor  478   a . Similarly, a pair of NMOS transistors  482   a,b  are coupled together (also between two voltage supplies Vcc and Vss) and the source of the transistor  482   a  is biased to the drain of the transistor  478   b . As a result, a current generated through the drain-to-source channels of the respective transistors  482   a,b  is also the current through the transistor  478   a . The source of the transistor  482   b  is additionally coupled to the drain and gate of an NMOS bias transistor  411  whose gate is also coupled to a first input of a comparator  474 . 
     In operation, the bias transistor  411  provides to the comparator  474  a bias voltage V BIAS  that is generated by the mirrored current through the transistor  411 . The output of the comparator  474  is coupled to the inverting input of the comparator so that it operates as a voltage follower. Therefore, the comparator  474  outputs the bias voltage V BIAS  with a low output impedance, which is applied to the gate of the bias transistor  410 . The bias transistor  411  and the bias transistor  410  have the exact same characteristics such that the bias voltage V BIAS  will vary with process and temperature variations in the same manner as the bias transistor  410 . Therefore, the bias voltage V BIAS  will track variations of the threshold voltage V T  of the transistor  410  due to process and temperature variations. 
     Although only one bias transistor  410  is shown in the embodiment of  FIG. 3  to illustrate the operation of the single bit line driver  401 , it should be noted that a bias transistor  410  is provided for each of a large number of bit lines in a memory device. Due to the heavy load of the large number of bias transistors  410 , the bias voltage can take a very long time to build up at the bias node  440 . Therefore, the pre-charging circuit  452  is used to quickly charge up the bias voltage at the bias node  440 . The pre-charging circuit  452  includes a comparator  472  having a first input coupled to the gate of an NMOS bias transistor  413 . The gate and drain of the bias transistor  413  is additionally coupled to an NMOS transistor  482   c , that is biased by coupling its gate to the gates of the transistors  482   a,b  of the mirror circuit  473 . The transistors  413 ,  482   c  are additionally coupled between two voltage supplies Vcc and Vss. Therefore, the transistor  482   c  has a drain-to-source current that is mirrored to the currents generated by the current mirror circuit  473 . This current is coupled through an NMOS transistor  413 , which provides a bias voltage (“Vbias-Δ”) to the first input of the comparator  472 . The transistor  413  is designed with a drain-to-source impedance that is slightly less than the drain-to-source impedance of the transistor  411 . As a result, the voltage Vbias-Δ is slightly less than the voltage V BIAS . 
     A second input of the comparator  472  is coupled to the output signal of the comparator  474  such that the Vbias-Δ voltage is compared to the bias voltage V BIAS  generated at the output for the comparator  474 . The output of the comparator  472  is coupled to the gate of another NMOS transistor  476 , whose drain is coupled to a high voltage supply Vcc and the source is coupled to the output of the comparator  474 . 
     In operation, if the Vbias-Δ voltage is greater than the bias voltage V BIAS , the comparator  472  turns ON the transistor  476  thereby applying V CC  to the bias node  440 . As a result, the bias node  440  is quickly charged towards the supply voltage Vcc until the bias node  440  is charged to the Vbias-Δ voltage. At that point, the comparator  472  turns OFF the transistor  476 . The comparator  474  then completes charging the bias node  440  to the bias voltage. 
     A flash memory device  600  that includes the bit line driver system according to one embodiment of the invention is shown in  FIG. 4 . The flash memory device  600  includes an array  630  of flash memory cells arranged in banks of rows and columns. Command signals, address signals and write data signals are applied to the memory device  600  as sets of sequential input/output (“I/O”) signals applied to respective input terminals  632 . Read data signals are output from the flash memory device  600  through respective output terminals  634 . In practice, the same terminals can be for some of the input terminals  632  and output terminals  634 , such as data terminals that receive write data and output read data. 
     Address signals applied to the input terminals  632  are coupled to a bit line decoder  640  and to a word line decoder  644 . The word line decoder  644  applies signals to word lines (not shown) in the array  630  based on a row address corresponding to the address signals. Similarly, the bit line decoder  640  selects one or more bit lines based on respective column addresses corresponding to the address signals. The signals generated by the bit line decoder  640  are applied to a set of bit line drivers  650 , which may be the bit line drivers  301  or  401  shown in  FIGS. 2 and 3 , respectively, or a bit line driver according to some other embodiment of the invention. The bit line decoder  640  may, for example, apply signals to the inverter  123  ( FIG. 3 ) in the bit line drivers  401 . As explained above, each of the bit line drivers  650  applies signals to respective state machines  660  indicative of the state of the respective bit line. As also explained above, the bit line drivers  650  are coupled to the array  630  through respective bit lines. 
     Write data signals applied to the input terminals  632  are applied to an input data drivers  670 , and from the drivers  670  to the input data terminals of the bit line drivers  650 , as explained above with reference to  FIG. 3 . Read data signals applied to bit lines in the array  630  are detected by sense amplifiers  680 , which apply corresponding write data signals to the output terminals  634 . 
       FIG. 5  is a block diagram of a processor-based system  700  including processor circuitry  702  having a volatile memory  710 . The processor circuitry  702  is coupled through address, data, and control buses to the volatile memory  710  to provide for writing data to and reading data from the volatile memory  710 . The processor circuitry  702  includes circuitry for performing various processing functions, such as executing specific software to perform specific calculations or tasks. The processor-based system  700  also includes one or more input devices  704  coupled to the processor circuitry  702  to allow an operator to interface with the processor-based system  700 . Examples of input devices  704  include keypads, touch screens, and scroll wheels. The processor-based system  700  also includes one or more output devices  706  coupled to the processor circuitry  702  to provide output information to the operator. In one example, the output device  706  is a visual display providing visual information to the operator. Data storage  708  is also coupled to the processor circuitry  702  to store data that is to be retained even when power is not supplied to the processor-based system  700  or to the data storage  708 . The flash memory device  600 , or a flash memory device according to some other example of the invention, can be used for the data storage  708 . 
     Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the invention. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.