Abstract:
A sample and hold circuit is disclosed that provides longer hold times. The sample and hold circuit can be used in a disc drive to provide improved read-to-write and write-to-read mode transitions. The sample and hold circuit has an input and an output, and includes at least one capacitive element for retaining a charge. The capacitive element is connected to a node between the input and the output. The sample and hold circuit includes at least one input switch to selectively connect the capacitive element to the input and at least one output switch to selectively connect the capacitive element to the output. In addition, an amplifier is connected to the node and has an offset voltage. In this manner, a voltage drop across at least one of the input and output switches is limited to the offset voltage.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to sample and hold circuits, and more particularly, to sample and hold circuits that provide longer hold times. 
   BACKGROUND OF THE INVENTION 
   Disc drives typically use magneto-resistive read heads to support high data densities. These magneto-resistive heads require a DC bias to operate (typically provided by a preamplifier). In a mobile application, however, power consumption is an important issue. Thus, a number of techniques have been proposed or suggested to reduce the power consumption of disc drives for mobile applications. Biasing of magneto resistive heads is also varied over time to extend the lifetime of the sensor. For example, sample and hold circuits have been proposed to allow the bias control circuits of the read head to be powered down when writing data to the disc while maintaining short write-to-read transition times. 
   In one proposed implementation of a sample and hold circuit, the disc drive power consumption was effectively reduced, but the maximum hold time was only on the order of 30 microseconds, due to switch leakage paths. For a number of applications, however, a longer hold time may be necessary. A need therefore exists for a disc drive having a sample and hold technique with a longer hold time. A further need exists for a disc drive employing a sample and hold technique that provides improved read-to-write and write-to-read mode transitions. 
   SUMMARY OF THE INVENTION 
   Generally, a sample and hold circuit is disclosed that provides longer hold times. The disclosed sample and hold circuit can be used in a disc drive to provide improved write-to-read mode transitions. The sample and hold circuit has an input and an output, and includes at least one capacitive element for retaining a charge. The capacitive element is connected to a node between the input and the output. The sample and hold circuit includes at least one input switch to selectively connect the capacitive element to the input and at least one output switch to selectively connect the capacitive element to the output. In addition, an amplifier is connected to multiple nodes and has an offset voltage. In this manner, a voltage drop across at least one of the input and output switches is limited to the offset voltage. 
   From a process point of view, a method is provided for reducing leakage in a sample and hold circuit having at least one capacitive element for retaining a charge. The method comprises the steps of (i) configuring at least one input switch to selectively connect the at least one capacitive element to the input; (ii) configuring at least one output switch to selectively connect the at least one capacitive element to the output; and (iii) limiting a voltage drop across at least one of the input and output switches to an offset voltage of an amplifier connected to the input or output node. 
   The disclosed sample and hold circuit can be used, for example, in a preamplifier for a head bias circuit in a storage system. In a further variation, the sample and hold circuit includes at least two switches that selectively connect at least one of the input and output switches to an output of the amplifier in a hold mode or to standard voltages in read mode, in order to reduce leakage effects due to parasitic diodes in the input and output switches. 
   A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic block diagram of a conventional preamplifier head bias circuit; 
       FIG. 2  is a schematic block diagram of a conventional sample and hold circuit that may be used in the preamplifier of  FIG. 1 ; 
       FIG. 3  illustrates a sample and hold circuit having low leakage in accordance with the present invention; 
       FIG. 4  illustrates an alternate sample and hold circuit having low leakage in accordance with the present invention; 
       FIG. 5  is a schematic diagram of an exemplary CMOS switch suitable for use in the sample and hold circuits of the present invention; and 
       FIG. 6  illustrates an alternate sample and hold circuit having low leakage in accordance with the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 1  is a schematic block diagram of a conventional preamplifier head bias circuit  100 . The preamplifier head bias circuit  100  may be used, for example, in a disk drive to bias a magneto-resistive sensor for reading. As shown in  FIG. 1 , the preamplifier head bias circuit  100  includes a transconductance (GM) cell  110 , a bias capacitor  120  in parallel with a short read head bias (SRM) switch  130 , and a head cell  150 . The output of the head cell  150  is provided to the read head (not shown). Thus, the positive and negative outputs of the head cell  150  carry both the DC bias and data signal. Generally, the transconductance cell  110  takes an input voltage and generates an output current, in a known manner. In a read mode, a feedback loop  160  is connected to the negative input of the transconductance cell  110  to force the head DC voltage to the SET_BIAS level that is set at the positive input of the transconductance cell  110 . The bandwidth of the bias loop  140  is set lower than the data spectrum to prevent data waveform distortion. To maximize read head life and minimize power dissipation, the head bias is turned off by switch SRM  130  when not reading data from the disc. The internal bias level (VBIAS) must be restored at the start of the next read period. 
   To meet the write-to-read specification (such as less than 125 ns for exemplary mobile drives), a high power, wide bandwidth feedback loop  160  is needed if VBIAS must be re-acquired at the start of each read period (the loop bandwidth is then reduced for the remainder of the read period). The loop power dissipation and complexity can be significantly reduced if the value of VBIAS is stored during write mode so the head can be quickly be set to the proper bias level at the start of the next read period. 
   Digital or analog methods can store VBIAS. The digital approach (storage register or up/down counter, digital-to-analog conversion (DAC), and comparator) offers unlimited hold time. The analog approach employs a sample and hold circuit that takes less area and power. With the analog approach, however, care must be taken to provide a hold time on the order of 200 microseconds time while in write mode without excessive VBIAS drift. The present invention extends the analog sample and hold time, for example, to a value on the order of 200 microseconds, while meeting tight area and power constraints. 
     FIG. 2  shows a conventional sample and hold circuit  200  to retain the steady state read mode VBIAS voltage while in the write mode. The sample and hold circuit  200  is typically built using metal oxide semiconductor (MOS) switches. As shown in  FIG. 2 , capacitor C 0  filters the electrical noise generated in the GM cell  110  and switch S 0 . Switch S 1  must have low resistance when closed so it will not add excessive noise to the bias voltage sent to the head cell. Switch S 1  is typically built using short channel MOS devices, which have significant leakages when powered down (open). As shown in  FIG. 2 , the leakage in an off state, represented by resistors RLEAK 0  and RLEAK 1 , causes the voltage held on capacitor C 0  to change (droop) when switches S 0  and S 1  are open. The droop rate limits the length of time the capacitor voltage stays within a given error band. 
   While the preamplifier head bias circuit  100  is in a write mode, switch SRM  130  keeps the head cell bias input at ground. At the start of the read mode, switch SRM  130  opens and switches S 0  and S 1  close. Some of the charge on the capacitor C 0  redistributes to the head cell bias line capacitance when switch S 1  closes. The loop must now restore the voltage across capacitor C 0  to the steady state level. 
   Thus, the sample and hold circuit  200  of  FIG. 2  does not provide a sufficient hold time due to the leakage paths represented by RLEAK 0  and RLEAK 1 . According to one aspect of the present invention, the preamplifier head bias circuit  100  of  FIG. 1  is modified to drive sample and hold nodes to reduce the hold switch leakage currents and thereby provide a hold time on the order of 200 microseconds. Thus, a disc drive incorporating the modified preamplifier head bias circuit can maintain a write mode for up to 200 microseconds. In this manner, the preamplifier head bias circuit in accordance with the present invention simultaneously provides (i) lower power dissipation, (ii) faster write-to-read mode transitions and (iii) longer hold modes (on the order of 200 microseconds). 
     FIG. 3  illustrates a sample and hold circuit  300  having low leakage in accordance with the present invention. The sample and hold circuit  300  reduces the effects of switch off leakage and head cell bias line capacitance. As shown in  FIG. 3 , the sample and hold switches S 0  and S 1  from  FIG. 2  have each been replaced by two switches in series, S 0  and S 1 , and S 2  and S 3 , respectively. In a read mode, switches S 0 , S 1 , S 1  and S 3  are closed and switches SRM, S 4 , and S 5  are open. The feedback loop charges capacitor C 0  to the intended voltage. 
   In a write mode, switches S 0  through S 3  are open and switches S 4 , S 5 , and SRM are closed. In accordance with the present invention, an amplifier A 1  drives nodes N 1  and N 2  to track the voltage of capacitor C 0 . In this manner, the voltage across RLEAK 1  and RLEAK 2  is reduced to the offset voltage of amplifier A 1  (on the order of milli-Volts instead of Volts). Thus, when switches S 1  and S 2  are opened, there is only a small voltage drop across the resistors RLEAK  1  and RLEAK  2 , and very little current through the resistors (thereby significantly reducing the leakage). Amplifier A 1  may be embodied, for example, as a MOS amplifier so that the small input current of amplifier A 1  has little effect on the circuit operation. The new topology allows minimum channel length switches to minimize noise added to the head bias signal without excessive signal droop when holding the bias level. 
   Proper switch sequencing can eliminate the start up charge sharing between capacitor C 0  and the head cell capacitance. For example, at the start of a read mode, switch SRM can be opened first before switch S 3  is closed. Amplifier A 1  then charges the head cell capacitance to equal the voltage on capacitor C 0  without capacitor C 0  losing charge. Thereafter, switches S 4  and S 5  are opened and switches S 0  through S 2  are closed to complete the head bias feedback loop. 
     FIG. 4  illustrates an alternate sample and hold circuit  400  having low leakage in accordance with the present invention. The sample and hold circuit  400  of  FIG. 4  is a simplification for a preamplifier application, where switch S 0  has been removed. The sample and hold circuit  400  of  FIG. 4  recognizes that the GM cell  110  of  FIG. 1  has a high impedance current source output. When in the hold mode, amplifier A 1  keeps the output of GM cell  110  close to the closed loop voltage to minimize transients when changing from the hold to closed loop modes. The amplifier A 1  controls the leakage through the resistors RLEAK 1  and RLEAK 2  and supplies current such that there is minimal drift through the resistor RLEAK 3 . 
   It is noted that the leakage of the switches in the sample and hold circuits  300 ,  400  is represented in  FIGS. 3 and 4  by resistances RLEAK 0  through RLEAK 3 , which are attributed to leakage effects of the drain to source path of the MOS devices. In addition to such drain to source leakage effects, however, there is also a leakage effect due to parasitic diodes in the MOS switches. In the sample and hold circuits  300 ,  400  of  FIGS. 3 and 4 , for example, there is a parasitic diode leakage effect. 
     FIG. 5  is a schematic diagram of an exemplary CMOS switch  500  suitable for use in the sample and hold circuits  300 ,  400  of the present invention. As shown in  FIG. 5 , in addition to the switch off resistance, the transistors also have parasitic drain and source diodes, shown as D 0 -D 3 . The NTUB is tied to a voltage that is more positive than the input signal (typically tied to VCC, VDD), so the diodes D 0  and D 1  tend to pull the signals IN and OUT up towards the power supply. The PTUB is tied to a voltage that is more negative than the input signal (typically tied to ground), so the diodes D 2  and D 3  tend to pull the signals IN and OUT towards ground. The net effect of the diode leakage currents is difficult to predict because of the variation in leakage with temperature and process. 
   Thus, according to another aspect of the present invention, a sample and hold circuit  600  is provided that reduces the leakage effects of both the drain to source paths and the parasitic diodes in the MOS switches.  FIG. 6  illustrates an alternate sample and hold circuit  600  having low leakage in accordance with the present invention. It is noted that NTUB and PTUB, shown in  FIG. 5 , are generally junction isolated from the substrate in a triple well process used for preamplifiers. 
   The sample and hold circuit  600  of  FIG. 6  recognizes that the isolated tubs can be advantageously used to reduce the diode leakage currents in a hold mode. As shown in  FIG. 6 , the sample and hold circuit  600  includes four switches  611 - 614  to control whether the MOS switches S 1  through S 3  are connected to the output of the amplifier A 1  or to standard voltages (VPOS and VNEG). The four switches  611 - 614  may each be embodied as the MOS switch  500 , shown in  FIG. 5 . 
   In a sample mode, the four switches  611 - 614  are configured to select the standard voltages (VPOS and VNEG) and thereby tie the tubs to the standard voltages to ensure that the parasitic diodes D 0 -D 3  are reverse biased for the input/output signal range. In a hold mode, the four switches  611 - 614  are configured to select the out of the amplifier A 1  which drives the switch transistor tubs and nodes N 1  and N 2 . In the hold mode, the voltage across S 1  and S 2  and their parasitic diodes are thus all reduced to the offset voltage of amplifier A 1 . In the sample mode, switches S 1 -S 3  are closed, switch S 4  and S 5  are open, and switches  611 - 614  connect the tubs to VPOS and VNEG. 
   Switch S 0  can be included in an alternate implementation of the sample and hold circuit  600  of  FIG. 6  when the sample and hold circuit  600  is driven from a lower impedance source than the GM cell  110 , in the manner described above for  FIGS. 3 and 4 . In such an alternate implementation of the sample and hold circuit  600 , the tubs of switch S 0  are connected directly to VNEG and VPOS, in a similar manner to switch S 3 . 
   It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.