Abstract:
Filtering of network packets is performed. Within a filter controller, a base address for a range of addresses is stored. A second value is also stored which further specifies the range of addresses. When a network packet is received, a network controller extracts a destination address from the network packet. The network controller forwards the destination address to the filter controller. The filter controller compares the destination address to the range of addresses specified by the base address and the second value. The filter controller generates a signal which indicates when the destination address is outside the range of addresses.

Description:
BACKGROUND 
     The present invention concerns computer networking and pertains particularly to a local area network receive filter. 
     Communication between computers and other computing equipment is achieved through various types of networks. For example, computers and computer equipment within fairly close proximity are often connected using a local area network (LAN). For computers and computer equipment separated by a greater distance, wide area networks (WAN) may be used to make the connections. 
     Often LANs and/or WANs are connected together in order for one computer on a LAN or a WAN to communicate with another computer in a different LAN or WAN. LANs and WANs may be joined, for example, using a network bridge or a network router. Each of the individual LAN and WAN may be considered a network segment of a larger network. 
     When networks are interconnected, it is desirable for a LAN to be able to reject data packets not destined for an individual local network device within the LAN. This is done, for example, by filters within a network bridge or a network router which specifically reject data packets not destined for an individual local network device on the LAN. 
     Packet addresses are generally filtered using a software routine, or by a hardware device which uses content addressable memory (CAM). 
     Filtering via software involves a processor with a fast enough clock-rate to enable the software to read and, subsequently, compare addresses from each packet sent. A comparison algorithm matches the packet destination address for each packet with a similar address in a pre-defined look-up table of local network addresses. The overhead required by such a software implementation as well as the higher cost for the fast processor make this an unattractive solution, especially for faster network protocols, such as 100VG, 100TX and Gigabit. 
     Devices which use CAM hardware filtering overcome the speed disadvantage generally inherent in software filtering implementations. The CAM allows storage of the specific local network addresses within a memory array. As packet addresses are presented to the CAM, the CAM performs the comparison logic necessary to determine if there is a match. The CAM indicates there is a match when the destination address for a packet coincides with a local network address stored in the CAM. While the use of CAM devices overcomes some of the disadvantages of software filtering implementations, the high component costs of CAM devices (and the associated circuitry) is the primary limiting factor of utilizing this technology. Another downside of a CAM implementation is the small memory array sizes currently available. 
     SUMMARY OF THE INVENTION 
     In accordance with the preferred embodiment of the present invention network packets are filtered. Within a filter controller, a base address for a range of addresses is stored. A second value, for example, an offset range limit, is also stored which further specifies the range of addresses. When a network packet is received, a network controller extracts a destination address from the network packet. The network controller forwards the destination address to the filter controller. The filter controller compares the destination address to the range of addresses specified by the base address and the second value. The filter controller generates a signal which indicates when the destination address is outside the range of addresses. 
     In the preferred embodiment, the network packet has a frame topology compatible with the IEEE 802.3 standard and the destination address is a six-byte media access control (MAC) destination address. For example, the first value is stored in six eight-bit registers, the second value is stored in two eight-bit registers. While the filter controller compares the destination address to the range of addresses specified by the base address and the offset range limit, the destination address is temporarily stored in six eight-bit registers within the filter controllers. 
     The present invention provides for simple low-cost performance of network packet filtering. The preferred embodiment additionally has a low over-head impact on system performance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram of a computing system which utilizes a local area network receive filter in accordance with a preferred embodiment of the present invention. 
     FIG. 2 is a simplified block diagram of a local area network receive filter in accordance with a preferred embodiment of the present invention. 
     FIG. 3 is a simplified block diagram which illustrates frame topology for a network package that conforms to the IEEE 802.3 standard. 
     FIG. 4 is a simplified block diagram which illustrates topology for the destination address for a network packet that conforms to the IEEE 802.3 standard. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a simplified block diagram of a computing system. The computing system is connected to a local area network (LAN)  14  via a physical media transceiver  13 . Data packets received by physical media transceiver  13  are forwarded to LAN controller  11  for processing before data is passed on to a central processing unit (CPU)  12 . 
     When a data packet is received by LAN controller  11 , a LAN receive filter (LRF) controller  15  is used to examine the destination address packets for a group (or range) of media access control (MAC) destination addresses. A clock  16  produces a clock signal used for both LAN controller  11  and LRF controller  15 . For example clock  16  produces a clock signal having a  30  megahertz frequency. 
     LAN controller  11  provides typical functionality as is generally available from LAN controllers. For example, LAN controller  11  provides an integrated interface for a PCI backplane bus by which LAN controller  11  is connected to CPU  12 . LAN controller  11  also provides a front plane bus interface for connection to physical media transceiver  13 . Non-volatile memory (such as an EEPROM) within LAN controller  11  is used to store configuration values. A random access (RAM) is used for temporary storage of both incoming and outgoing network data. Read-only memory (ROM) is used to store boot software. 
     In addition, LAN controller  11  also provides an interface to LRF controller  15 . The interface includes a four-bit address bus  17  which is used to select a MAC destination register within LRF controller  15 . An eight-bit input data bus  18  is used to load the MAC destination registers within LRF  15  when filtering is being performed. A chip select (LRFCS) signal  19  (active low) is used to activate LRF controller  15 . A clock (LRFCLK) signal  20 , synchronous to the clock signal generated by clock  16 , is used to clock packet bytes into LANMAC registers within LRF controller. A packet rejection (LRFREJ) signal  22  (active low) is used by LRF controller to indicate that a specific MAC address for a packet is not within the range of addresses specified by the MAC registers and a mask register within LRF controller. The interface between LAN controller  11  and LRF controller  15  also includes additional miscellaneous signals  23  to initialize and test operation of LRF controller  15 . 
     FIG. 2 is a simplified block diagram of LRF controller  15 . LRF controller includes six eight-bit MAC registers: a MAC 0  register  30 , a MAC 1  register  31 , a MAC 2  register  32 , a MAC 3  register  33 , a MAC 4  register  34 , and a MAC 5  register  35 . LRF controller also includes six eight-bit LANMAC registers: a LANMAC 0  register  50 , a LANMAC 1  register  51 , a LANMAC 2  register  52 , a LANMAC 3  register  53 , a LANMAC 4  register  54 , and a LANMAC 5  register  55 . 
     An eight-bit data bus  18  is used to load data into the MAC registers and from a LANMAC data register  66  into the LANMAC registers. An address decoder  49  uses four-bit values on address bus  17  to generate a MAC register enable signal  40  used to enable MAC 0  register  30 , a MAC register enable signal  41  used to enable MAC 1  register  31 , a MAC register enable signal  42  used to enable MAC 2  register  32 , a MAC register enable signal  43  used to enable MAC 3  register  33 , a MAC register enable signal  44  used to enable MAC 4  register  34  and a MAC register enable signal  45  used to enable MAC 5  register  35 . 
     An LRF clock counter  69  uses a buffered clock signal  68 , generated by an LRF buffer clock  67  from LRFCLK signal  20 , to generate a LANMAC register enable signal  60  used to enable LANMAC 0  register  50 , a LANMAC register enable signal  61  used to enable LANMAC 1  register  51 , a LANMAC register enable signal  62  used to enable LANMAC 2  register  52 , a LANMAC register enable signal  63  used to enable LANMAC 3  register  53 , a LANMAC register enable signal  64  used to enable LANMAC 4  register  54  and a LANMAC register enable signal  65  used to enable LANMAC 5  register  55 . 
     During initialization, a base MAC address is loaded into the six MAC registers. In addition, an offset range limit is loaded into a MAC mask  36 . For example, MAC mask  36  is implemented by two eight-bit registers. 
     During filtering, MAC destination addresses for packets are forwarded to LRF controller  15  through data bus  18  and loaded into the six LANMAC registers. Compare logic  39  then checks whether the MAC destination address loaded into the LANMAC registers are within the address range specified by the base MAC address loaded into the six MAC registers and the offset range limit loaded into MAC mask  36 . 
     To further illustrate the invention, FIG. 3 shows the topology for a network package  70  that conforms to the IEEE 802.3 standard. A preamble section  71  consists of eight bytes. A destination address section  72  consists of six bytes. A source address section  73  consists of six bytes. A type section  74  consists of two bytes. A data section  75  consists of 46 to 1500 bytes. A cyclical redundancy check section  76  consists of four bytes. 
     Destination address section  72  and source address section  73  each contain a six byte MAC address. FIG. 4 shows the topology for a MAC address. A vendor specific section  81  consists of three bytes which indicate a vendor specific prefix. A fixed block coding  82  consists of one and a half bytes. A variable block coding  83  consists of one and a half bytes. 
     Industry wide, MAC addresses are assigned out in blocks of 4096 (16×256) addresses (per block). The total possible number of blocks which can be assigned to one vendor is also 4096 (16×256). Therefore, the total number of MAC addresses for one specific vendor is 4096 2 =16,777,216. 
     As indicated above, in order to specify a subset of MAC addresses to be filtered for by LRF controller  15 , a base MAC address is loaded into the six MAC registers and a two byte offset range limit is loaded into a MAC mask  36 . 
     For example, the value 080009A9416A hex  is loaded into the six MAC registers. This is done by loading the value 6A hex  into MAC 0  register  30 , loading the value 41 hex  into MAC 1  register  31 , loading the value A9 hex  into MAC 2  register  32 , loading the value 09 hex  into MAC 3  register  33 , loading the value 00 hex  into MAC 4  register  34  and loading the value 08 hex  into MAC 5  register  35 . 
     In order to allow LRF controller  15  to filter for eight destination MAC addresses starting at the base address of 080009A9416A hex , the offset range limit 4171 hex  is loaded into MAC mask  36 . This allows LRF controller to filter for the following eight destination MAC addresses: 080009A9416A hex , 080009A9416B hex , 080009A9416C hex , 080009A9416D hex , 080009A9416E hex , 080009A9416F hex , 080009A94170 hex  and 080009A9471 hex . 
     When LAN controller  11  receives a packet, LAN controller  11  enables LRF controller  15  by asserting LRFCS signal  19 . LAN controller  11  then transfers to LRF controller  15  the destination MAC address for the packet. This is done one byte at a time using LRFCLK signal  20 . LRF clock counter  69  enables LANMAC 0  register  50 , LANMAC 1  register  51 , LANMAC 2  register  52 , LANMAC 3  register  53 , LANMAC 4  register  54 , and LANMAC 5  register  55  in sequence to allow the destination MAC address for the packet to be loaded into the LANMAC registers of LRF  15 . Compare logic  39  asserts LRFREJ signal  22  when the destination MAC address loaded into LANMAC 0  register  50 , LANMAC 1  register  51 , LANMAC 2  register  52 , LANMAC 3  register  53 , LANMAC 4  register  54 , and LANMAC 5  register  55  is not within the MAC address range specified by the values in MAC 0  register  30 , MAC 1  register  31 , MAC 2  register  32 , MAC 3  register  33 , MAC 4  register  34 , MAC 5  register  35  and MAC mask  36 . Compare logic  39  does not assert LRFREJ signal  22  when the destination MAC address loaded into LANMAC 0  register  50 , LANMAC 1  register  51 , LANMAC 2  register  52 , LANMAC 3  register  53 , LANMAC 4  register  54 , and LANMAC 5  register  55  is within the MAC address range specified by the values in MAC 0  register  30 , MAC 1  register  31 , MAC 2  register  32 , MAC 3  register  33 , MAC 4  register  34 , MAC 5  register  35  and MAC mask  36 . 
     The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.