Abstract:
A display device driver circuit including a first switching circuit for switching connection and disconnection between an output terminal and a first source line; a second switching circuit for switching connection and disconnection between the output terminal and a second source line; and a selecting circuit for switching a voltage output from the output terminal by controlling the first and second switching circuits. The selecting circuit controls the first and second switching circuits so that the timing for opening one of the switching circuits is faster than the timing for closing the other of the switching circuits. Consequently, a time when both switches are open occurs regularly when the voltage output is switched, so that no current will pass between the switching circuits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a display device driver circuit. A driver circuit is a circuit for converting driving voltages. The driver circuit relating to the present invention is used to drive liquid crystal displays (LCDs), for example. 
     2. Description of Related Art 
     A control circuit is used to drive display devices such as LCDs. Such a control circuit is generally constituted of logic integrated circuits. The LCD control circuit applies the driving voltage in the segment direction and driving voltage in the common direction, that is perpendicular to the segment direction, to the liquid crystal elements. Switching the orientations of the driving voltages applied to the liquid crystal elements switches the transparency and opacity to light incident to the liquid crystal element. 
     The optimum value of the driving voltage VUO applied to the liquid crystal elements varies depending on the type of liquid crystal. In a usual LCD, the optimum value of the driving voltage VUO will be about six volts at the least and about 50 volts at the most. On the other hand, the driving voltage VDD for a usual logic integrated circuit is three to five volts. The output signal voltage of a logic integrated circuit matches the voltage VDD and is therefore three to five volts. Consequently, the output signal voltage of the logic integrated circuit is preferably not applied without further processing to the LCD as the driving voltage VUO. 
     A usual LCD control circuit generates the voltage to drive the LCD by converting the output signal voltage of a logic circuit from VDD to VUO. The circuit performing this conversion is called a driver circuit. The driver circuit is established at the final stage of the LCD control circuit. 
     In order for the conversion of the output signal voltage from VDD to VUO, the voltage VUO must be supplied to the driver circuit. The voltage VUO may also be generated by a power source independent from the power source of the voltage VDD, but in many cases is generated by raising the voltage VDD with a voltage booster circuit. 
     The driving voltage output terminals of the driver circuit are connected to two switching circuits. One switching circuit connects and disconnects the output terminal and the driving voltage VUO. The other switching circuit connects and disconnects the output terminal and ground. When the switch on the voltage VUO side is closed and the switch on the ground side is open, the output terminal outputs the voltage VUO. Oppositely, when the switch on the voltage VUO side is open and the switch on the ground side is closed, the output terminal outputs zero volts. The opening and closing of these switching circuits is controlled by the output signals of the logic circuit in the previous stage. 
     When the output voltage of the driver circuit is being switched, the timing for closing one switching circuit is faster than the timing for opening the other switching circuit; as a result, a time when both switching circuits are closed will occur. In this case, pass-through current will flow from the voltage VUO side to the ground side. This pass-through current causes the level of the voltage VUO to drop. This level drop causes deterioration of the LCD image quality. When the voltage VUO is generated by the voltage booster circuit discussed above, the level drop of the voltage VUO becomes particularly great. This is because the voltage VUO generated by the voltage booster circuit is greatly dependent on changes to the size of the load. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a driver circuit wherein pass-through current is not generated during the switching of the output voltage. 
     For this reason, the display device driver circuit relating to the present invention comprises first switching means for switching connection and disconnection between the output terminal and the first source line; second switching means for switching connection and disconnection between the output terminal and the second source line; and selecting means for switching the voltage output from the output terminal by switching the first and second switching means open and closed, so that the timing for opening one switching means is faster than the timing for closing the other switching means. 
     The selecting means control the first and second switching means so that the timing for opening one switching means is faster than the timing for closing the other switching means. Consequently, a time when both switching means are closed will occur regularly when the output voltage is switched; therefore, no current will pass through these switching means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the present invention are explained with references to the following attached drawings. 
     FIG. 1 is a circuit diagram showing the constitution of the display device driver circuit relating to the first embodiment; 
     FIGS. 2,  3 A,  3 B,  4 ,  5 A and  5 B are waveform diagrams to explain the operation of the driver circuit shown in FIG. 1; 
     FIG. 6 is a circuit diagram showing the constitution of the display device driver circuit relating to the second embodiment; and 
     FIGS. 7,  8 A,  8 B,  9 ,  10 A and  10 B are waveform diagrams to explain the operation of the driver circuit shown in FIG.  6 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiments of the present invention are explained below using the drawings. In the figures, the sizes, forms, and disposition of the elements are merely for illustration so that the present invention can be understood; moreover the numerical conditions explained below are simply for illustration. 
     First Embodiment 
     FIG. 1 is a diagram of the constitution of the driver circuit relating to the first embodiment of the present invention. 
     As shown in FIG. 1, the driver circuit  100  relating to the present embodiment comprises a level shifter  110 , switching circuits  120  and  130 , and inverters  141 - 146 . The level shifter  100  and inverters  141 - 146  constitute the selecting circuit for controlling switching circuits  120  and  130 . 
     In FIG. 1, the numbers in parentheses associated with the transistors show the gate width and gate length of each transistor. The numbers in parentheses associated with the inverters show the gate width and gate length of the pMOS transistors and nMOS transistors within the inverters. 
     The driver circuit  100  receives a signal Sin from the logic circuit in the previous stage, not shown, and converts the potential of this signal Sin from VDD to VUO. The converted potential is output from the output terminal OUT. 
     The level shifter  110  converts the high level potential of the signal Sin from VDD to VUO. The converted potential is supplied to the switching circuits  120  and  130 . The level shifter  110  comprises pMOS transistors  111  and  113 , and nMOS transistors  112  and  114 . Transistors with narrow gate widths and long gate lengths are used as the pMOS transistors  111  and  113 . Specifically, as discussed below, pass-through current flows between transistors  111  and  112  and between transistors  113  and  114  in the level shifter  110 ; this increases the impedance of the pMOS transistors  111  and  113  and makes it difficult for current to flow. 
     In the pMOS transistor  111 , the gate is connected to node N 2 , the source is connected to the source line of the voltage VUO, and the drain is connected to node N 1 . In the pMOS transistor  111 , the gate width is 3 μm and the gate length is 30 μm. 
     In the nMOS transistor  112 , the gate receives the signal Sin via the inverter  141 , the source is connected to the ground line, and the drain is connected to the node N 1 . In the nMOS transistor  112 , the gate width is 30 μm and the gate length is 1 μm. 
     In the pMOS transistor  113 , the gate is connected to the node N 1 , the source is connected to the source line of the voltage VUO, and the drain is connected to the node N 2 . In the pMOS transistor  113 , the gate width is 3 μm and the gate length is 30 μm. 
     In the nMOS transistor  114 , the gate receives the signal Sin via the inverters  141  and  142 , the source is connected to the ground line, and the drain is connected to the node N 2 . In the nMOS transistor  114 , the gate width is 30 μm and the gate length is 1 μm. 
     The switching circuit  120  is a transfer gate for supplying the voltage VUO, meaning a high level potential, to the output terminal OUT. The switching circuit  120  comprises pMOS transistor  121  and nMOS transistor  122 . A transistor with a broad gate width and short gate length is used as the pMOS transistor  121 . This is because it is preferable that the impedance of the switching circuit  120  be low in order to supply a large current to the display device and cause high speed operation thereof. 
     The voltage VUO is used as the control voltage of the transistors  121  and  122 . The transistors  121  and  122  in the switching circuit  120  have large-sized gates; it is therefore difficult to use VDD as the control voltage. The signal Sin is therefore converted to the voltage VUO by the level shifter  110  and the converted signal is used to control the switching circuit  120 . 
     In the pMOS transistor  121 , the gate is connected to node N 1  via the inverter  143 , the source is connected to the source line of the voltage VUO, and the drain is connected to the output terminal OUT. In the pMOS transistor  121 , the gate width is 50 μm and the gate length is 1 μm. 
     In the nMOS transistor  122 , the gate is connected to node N 1  via the inverters  143  and  144 , the source is connected to the output terminal OUT, and the drain is connected to the source of the voltage VUO. In the nMOS transistor  122 , the gate width is 30 μm and the gate length is 1 μm. 
     The switching circuit  130  is a transfer gate for supplying the ground potential, meaning a low level potential, to the output terminal OUT. The switching circuit  130  comprises a pMOS transistor  131  and nMOS transistor  132 . For the same reasons as in the case of the switching circuit  120 , a transistor with a broad gate width and short gate length is used as the pMOS transistor  131 . In addition, for the same reasons as in the case of the switching circuit  120 , the voltage VUO is used as the control voltage of the transistors  131  and  132 . 
     In the pMOS transistor  131 , the gate is connected to node N 2  via the inverter  145 , the source is connected to the output terminal OUT, and the drain is connected to the ground line. In the pMOS transistor  131 , the gate width is 50 μm and the gate length is 1 μm. 
     In the nMOS transistor  132 , the gate is connected to node N 2  via inverters  145  and  146 , the source is connected to the ground line, and the drain is connected to the output terminal OUT. In the nMOS transistor  132 , the gate width is 30 μm and the gate length is 1 μm. 
     The inverters  141 - 146  each comprise one pMOS transistor and one nMOS transistor. The internal constitution of the inverters  141 - 146  is the same as in known inverters and is therefore not shown in the drawings. 
     In the inverter  141 , the gate width of the pMOS transistor is 10 μm and the gate length of the pMOS transistor is 1 μm; the gate width of the nMOS transistor is 10 μm and the gate length of the nMOS transistor is 1 μm. 
     In the inverter  142 , the gate width of the pMOS transistor is 10 μm and the gate length of the pMOS transistor is 1 μm; the gate width of the nMOS transistor is 10 μm and the gate length of the nMOS transistor is 1 μm. 
     In the inverter  143 , the gate width of the pMOS transistor is 3 μm and the gate length of the pMOS transistor is 1 μm; the gate width of the nMOS transistor is 3 μm and the gate length of the nMOS transistor is 1 μm. 
     In the inverter  144 , the gate width of the pMOS transistor is 10 μm and the gate length of the pMOS transistor is 1 μm; the gate width of the nMOS transistor is 5 μm and the gate length of the nMOS transistor is 1 μm. 
     In the inverter  145 , the gate width of the pMOS transistor is 3 μm and the gate length of the pMOS transistor is 1 μm; the gate width of the nMOS transistor is 3 μm and the gate length of the nMOS transistor is 1 μm. 
     In the inverter  146 , the gate width of the pMOS transistor is 10 μm and the gate length of the pMOS transistor is 1 μm; the gate width of the nMOS transistor is 5 μm and the gate length of the nMOS transistor is 1 μm. 
     Next, the operation of the driver circuit  100  shown in FIG. 1 is explained using FIGS. 2-5B. FIG. 2 is a waveform diagram showing simulation results for the signal Sin and nodes N 1  and N 2 . FIG. 3A is an enlarged detail of portion E in FIG.  2  and FIG. 3B is an enlarged detail of portion F in FIG.  2 . FIG. 4 is a waveform diagram showing simulation results for signals S 11 -S 14 . FIG. 5A is an enlarged detail of portion G in FIG. 4, and FIG. 5B is an enlarged detail of portion H in FIG.  4 . 
     As discussed above, the driver circuit  100  receives the signal Sin from the logic circuit in the preceding stage, not shown. 
     When the signal Sin is high level, a low level signal is input to the gate of the nMOS transistor  112  and a high level signal is input to the gate of the nMOS transistor  114 . Consequently, the nMOS transistor  112  is in an OFF state and the nMOS transistor  114  is in an ON state. When the nMOS transistor  114  is in an ON state, the node N 2  is connected to ground. Consequently, the potential of the node N 2  is zero volts, meaning low level. In addition, when the node N 2  is low level, the pMOS transistor  111  is in a ON state. Consequently, the voltage VUO is applied to the node N 1 . The potential of the node N 1  is VUO, or high level, because the nMOS transistor  112  is in an OFF state as discussed above. When the potential of the node N 1  is VUO, the pMOS transistor  113  is in an OFF state. 
     Because the node N 1  is high level, the output signal S 11  of the inverter  143  is low level and the output signal S 12  of the inverter  144  is high level. Consequently, the gate potential of the pMOS transistor  121  is low level and the gate potential of the nMOS transistor  122  is high level. For this reason, the pMOS transistor  121  and nMOS transistor  122  are in an ON state. Meanwhile, because the node N 2  is low level, the output signal S 13  of the inverter  145  is high level and the output signal S 14  of the inverter  146  is low level. Consequently, the gate potential of the pMOS transistor  131  is high level and the gate potential of the nMOS transistor  132  is low level. For this reason, the pMOS transistor  131  and nMOS transistor  132  are in an OFF state. As a result, the potential of the output terminal OUT is VUO, or high level. 
     When the signal Sin changes from high level to low level, the gate potential of the nMOS transistor  112  changes to high level and the gate potential of the nMOS transistor  114  changes to low level. Consequently, the nMOS transistor  12  changes to ON and the nMOS transistor  114  changes to OFF. 
     When the nMOS transistor  112  is ON, pass-through current flows in the transistors  111  and  112 . Consequently, as shown in FIG. 3A, the potential of node N 1  drops abruptly from high level to low level. Accordingly, as shown in FIG. 5A, the output signal S 11  of the inverter  143  abruptly rises and the output signal S 12  of the inverter  144  abruptly drops. Consequently, the switching circuit  120  abruptly opens. 
     When the potential of node N 1  drops and becomes lower than the threshold voltage of the pMOS transistor  113 , the pMOS transistor  113  becomes ON and as a result, the potential of the node N 2  rises from low level to high level. When the potential of node N 2  rises and becomes higher than the threshold voltage of the pMOS transistor  111 , the pMOS transistor  111  becomes OFF. As shown in FIG. 3A, the potential of the node N 2  gradually rises. Accordingly, as shown in FIG. 5A, the output signal S 13  of the inverter  145  gradually drops and the output signal S 14  of the inverter  146  gradually rises. Consequently, the switching circuit  130  slowly closes. 
     As discussed above, the switching circuit  120  opens abruptly and the switching circuit  130  closes slowly. For this reason, the time period T, wherein the switching circuits  120  and  130  are both open, occurs as shown in FIG.  5 A. 
     Next, when the signal Sin changes from low level to high level, the gate potential of the nMOS transistor  112  changes to a low level and the gate potential of the nMOS transistor  114  changes to high level. Consequently, the nMOS transistor  112  becomes OFF and the nMOS transistor  114  becomes ON. 
     When the nMOS transistor  114  becomes ON, the potential of the node N 2  drops abruptly from high level to low level as shown in FIG.  3 B. Accordingly, as shown in FIG. 5B, the output signal S 13  of the inverter  145  rises abruptly and the output signal S 14  of the inverter  146  drops abruptly. Consequently, the switching circuit  130  opens abruptly. 
     When the potential of the node N 2  drops and becomes less than the threshold voltage of the pMOS transistor  111 , the pMOS transistor  111  becomes ON; as a result, the potential of the node N 1  rises from low level to high level. When the potential of the node N 1  rises and becomes higher than the threshold voltage of the pMOS transistor  113 , the pMOS transistor  113  becomes OFF. The potential of the node N 1  rises gradually as shown in FIG.  3 B. Accordingly, as shown in FIG. 5B, the output signal S 11  of the inverter  143  drops gradually and the output signal S 12  of the inverter  144  rises gradually. Consequently, the switching circuit  120  closes gradually. 
     For this reason, the time period T, wherein both switching circuits  120  and  130  are both open, occurs as shown in FIG.  5 B. 
     As discussed above, the driver circuit  100  relating to the present embodiment utilizes the fact that the potentials of the nodes N 1  and N 2  in the level shifter  110  change quickly when rising and slowly when falling, causing the time period T wherein both switching circuits  120  and  130  are open. In other words, a time when both the switching circuits  120  and  130  are closed does not occur in the driver circuit  100 . Consequently, because there is no flow of pass-through current between switching circuits  120  and  130 , there is no degradation of image quality for the display device. Pass-through current flows between transistors  111  and  112  and between transistors  113  and  114 , but is not a factor in reduced image quality because this pass-through current does not influence the voltage level of the terminal OUT. 
     The driver circuit  100  can be constituted with few gates and consequently the layout design thereof is easy. 
     Second Embodiment 
     FIG. 6 is a diagram of the constitution of the driver circuit relating to the second embodiment of the present invention. 
     As shown in FIG. 6, the driver circuit  600  relating to the present embodiment comprises a level shifter  610 , switching circuits  620  and  630 , and inverters  141 ,  142 , and  601 - 604 . The level shifter  610  and inverters  141 ,  142 , and  601 - 604  constitute a selecting circuit for controlling the switching circuits  620  and  630 . 
     In FIG. 6, the numbers in parentheses associated with the transistors show the gate width and gate length of each transistor. The numbers in parentheses associated with the inverters show the gate width and gate length of the pMOS transistors and nMOS transistors within the inverters. 
     The driver circuit  600  receives a signal Sin from the logic circuit in the previous stage, not shown, and converts the potential of this signal Sin from VDD to VUO. The converted signal is output from the output terminal OUT. 
     The level shifter  610  converts the high level potential of the signal Sin from VDD to VUO. The converted potential is supplied to the switching circuits  620  and  630 . The level shifter  610  comprises pMOS transistors  111  and  113 , and nMOS transistors  112  and  114 . The sizes and connective relationships of the transistors  111 - 114  are the same as in the level shifter  110  in FIG.  1 . 
     The switching circuit  620  is a transfer gate for supplying the voltage VUO, meaning a high level potential, to the output terminal OUT. The switching circuit  620  comprises pMOS transistor  121  and nMOS transistor  122 . The sizes and connective relationships of the transistors  121  and  122  are the same as in the switching circuit  120  in FIG.  1 . 
     The switching circuit  630  is a transfer gate for supplying the ground potential, meaning a low level potential, to the output terminal OUT. The switching circuit  630  comprises a pMOS transistor  131  and nMOS transistor  132 . The sizes and connective relationships of the transistors  131  and  132  are the same as in the switching circuit  130  in FIG.  1 . 
     The inverters  141 ,  142 , and  601 ˜ 604  each comprise one pMOS transistor and one nMOS transistor, not shown. 
     The sizes and connective relationships of the inverters  141  and  142  are the same as in the driver circuit in FIG.  1 . 
     The input terminal of the inverter  601  is connected to the node N 3 ; the output terminal of the inverter  601  is connected to the gate of the pMOS transistor  121 . In the inverter  601 , the gate width of the pMOS transistor is 3 μm and the gate length of the pMOS transistor is 3 μm; the gate width of the nMOS transistor is 3 μm and the gate length of the nMOS transistor is 1 μm. That is, the gate length of the pMOS transistor in the inverter  601  is different from the inverter  143  in FIG.  1 . 
     In the inverter  602 , the input terminal is connected to the output terminal of the inverter  601  and the output terminal is connected to the gate of the nMOS transistor  122 . The sizes of the transistors comprising the inverter  602  are the same as in the inverter  144  in FIG.  1 . 
     The input terminal of the inverter  603  is connected to node N 3  and the output terminal of the inverter  603  is connected to the gate of the nMos transistor  132 . In the inverter  603 , the gate width of the pMOS transistor is 3 μm and the gate length of the pMOS transistor is 1 μm; the gate width of the nMOS transistor is 3 μm and the gate length of the nMOS transistor is 3 μm. That is, the connective relationships and gate length of the nMOS transistor in the inverter  603  are different from those of the inverter  145  in FIG.  1 . 
     The input terminal of the inverter  604  is connected to the output terminal of the inverter  603 ; the output terminal of the inverter  604  is connected to the gate of the pMOS transistor  131 . The sizes of the transistors comprising the inverter  604  are the same as those in the inverter  146  in FIG.  1 . Specifically, the inverter  604  differs from the inverter  146  in FIG. 1 in that the output terminal is connected to the pMOS transistor  131 . 
     As discussed above, the inverter  601  and inverter  603  have different sized transistors. Because of this difference, the inverter  601  operates more quickly than the inverter  603  when the node N 3  changes from high level to low level, and the inverter  603  operates more quickly than the inverter  601  when the node N 3  changes from low level to high level. 
     Next, the operation of the driver circuit  600  shown in FIG. 6 is explained using FIGS. 7-10B. FIG. 7 is a waveform diagram showing simulation results of the signal Sin and node N 3 . FIG. 8A is an enlarged detail of section J in FIG. 7; FIG. 8B is an enlarged detail of section K in FIG.  7 . FIG. 9 is a waveform diagram showing simulation results for signals S 61 -S 64 . FIG. 10A is an enlarged detail of section L in FIG. 9; FIG. 10B is an enlarged detail of section M in FIG.  9 . 
     As discussed above, the driver circuit  600  receives the signal Sin from the logic circuit in the preceding stage, not shown. 
     When the signal Sin is high level, a low level signal is input to the gate of the nMOS transistor  112  and a high level signal is input to the gate of the nMOS transistor  114 . Consequently, the nMOS transistor  112  is OFF and the nMOS transistor  114  is ON. When the nMOS transistor  114  is ON, the pMOS transistor  111  is ON because the gate is low level. Consequently, the voltage VUO is applied to the node N 3 . As discussed above, the nMOS transistor  112  is OFF, so the potential of the node N 3  is VUO, meaning high level. When the potential of the node N 3  is VUO, the nMOS transistor  113  is OFF. 
     When the node N 3  is high level, the output signal S 61  of the inverter  601  is low level and the output signal S 62  of the inverter  602  is high level. Consequently, the gate potential of the pMOS transistor  121  is low level and the gate potential of the nMOS transistor  122  is high level. For this reason, the pMOS transistor  121  and nMOS transistor  122  are ON. Meanwhile, when the node N 3  is high level, the output signal S 63  of the inverter  603  is low level and the output signal S 64  of the inverter  604  is high level. Consequently, the gate potential of the pMOS transistor  131  is high level and the gate potential of the nMOS transistor  132  is low level. The pMOS transistor  131  and nMOS transistor  132  are therefore OFF. As a result, the potential of the output terminal OUT is VUO, meaning high level. 
     When the signal Sin changes from high level to low level, the gate potential of the nMOS transistor  112  changes to a high level and the gate potential of the nMOS transistor  114  changes to low level. Consequently, the nMOS transistor  112  changes to ON and the nMOS transistor  114  changes to OFF. 
     When the nMOS transistor  112  is made ON, the potential of the node N 3  changes from high level to low level. As discussed above, the inverter  601  operates faster than the inverter  603  when the node N 3  changes from high level to low level. Consequently, the output signal S 61  of the inverter  601  rises abruptly and the output signal S 62  of the inverter  602  drops abruptly as shown in FIG.  10 A. Meanwhile, the output signal S 63  of the inverter  603  rises gradually and the output signal S 64  of the inverter  604  drops gradually. Accordingly, the switching circuit  620  opens abruptly and the switching circuit  630  closes gradually. 
     For this reason, the time period T, wherein both switching circuits  620  and  630  are open, occurs as shown in FIG.  10 A. 
     Next, when the signal Sin changes from low level to high level, the potential of the nMOS transistor  112  changes to a low level signal and the gate potential of the nMOS transistor  114  changes to high level. Consequently, the nMOS transistor  112  becomes OFF and the nMOS transistor  114  becomes ON. 
     When the nMOS transistor  114  goes ON, the potential of the node N 3  changes from low level to high level as shown in FIG.  8 B. As discussed above, when the node N 3  changes from low level to high level, the inverter  603  operates more quickly than the inverter  601 . Consequently, the output signal S 63  of the inverter  603  falls abruptly and the output signal S 64  of the inverter  604  rises abruptly as shown in FIG.  10 B. Meanwhile, the output signal S 61  of the inverter  601  falls gradually and the output signal S 62  of the inverter  602  rises gradually. Accordingly, the switching circuit  630  opens abruptly and the switching circuit  620  closes gradually. 
     For this reason, the time period T, wherein both switching circuits  620  and  630  are open, occurs as shown in FIG.  10 B. 
     As discussed above, the driver circuit  600  relating to the present embodiment utilizes the difference in operating speeds of the inverters  601  and  603 , causing the time period T wherein both switching circuits  620  and  630  are open. In other words, a time when both the switching circuits  620  and  630  are closed does not occur in the driver circuit  600 . Consequently, because there is no flow of pass-through current between switching circuits  620  and  630 , there is no degradation of image quality for the display device. Pass-through current flows between transistors  111  and  112  and between transistors  113  and  114 , but is not a factor in reduced image quality because this pass-through current does not influence the voltage level of the terminal OUT. 
     The driver circuit  600  can be constituted with few gates and consequently the layout design thereof is easy. 
     In the driver circuits  100  and  600  discussed above, the switching circuits  120 ,  130 ,  620 , and  630  are each constituted of two switch elements. However, these switching circuits may also each be constituted of one switching element. When the switching circuits are constituted with one switching element, some of the inverters become unnecessary. 
     In the driver circuit  600  discussed above, only one node is used; as a result, a more simple circuit can be used instead of the level shifter  610 . For example, a circuit for waveform re-shaping the logic signal Sin using the source voltage VUO can be used instead of the level shifter  610 .