Abstract:
In a signal processing circuit of an LNB (Low Noise Block down converter), a power supply circuit is driven by DC voltage applied from four tuners via four signal input/output terminals to generate supply voltage for the LNB and equally distribute consumption current of the LNB among the four signal input/output terminals. Even if the level of the DC voltage from the four tuners is changed, currents of the same value flow through the four signal input/output terminals. Therefore, there is less noise compared with the conventional circuit having a signal input/output terminal allowing current to flow that varies.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to receiving apparatuses and particularly to a receiving apparatus shared by a plurality of tuners. 
     2. Description of the Background Art 
     FIG. 5 is a block diagram showing a structure of a receiving unit of a conventional satellite broadcasting system. Referring to FIG. 5, the receiving unit of the satellite broadcasting system includes an antenna  30  having a reflector  31  and an LNB (Low Noise Block down converter)  32 , a receiver  33  having a DBS (Direct Broadcasting by Satellite) tuner  34 , an FM demodulator  35 , a video+audio circuit  36  and an amplifier  37 , and a television receiver  38 . 
     Radio waves α emitted from a satellite are supplied via reflector  31  to LNB  32 . LNB  32  extracts from the received radio waves a image signals of a plurality of channels, amplifies the signals with noise kept low, and supplies an image signal of a channel selected by DBS tuner  34  to DBS tuner  34 . An output signal of LNB  32  is supplied via DBS tuner  34  to FM demodulator  35  which FM-demodulates the output signal. 
     The FM-demodulated image signal is converted to a video signal and an audio signal by video+audio circuit  36 , amplified by amplifier  37  and then supplied to television receiver  38 . An image of the channel selected by DBS tuner  34  is displayed on the screen of television receiver  38 . 
     FIG. 6 is a perspective view showing from the outside a structure of LNB  32 . Referring to FIG. 6, LNB  32  has a casing member  41 , and a feed phone  42  and a signal input/output terminal  43  are provided on the surface of casing member  41 . Radio waves α reflected from reflector  31  of antenna  30  are supplied into an opening  42   a  of feed phone  42 . In casing  41 , a signal processing circuit is provided for processing the radio waves α supplied to feed phone  42 . Signal input/output terminal  43  is connected to DBS tuner  34  via a cable. 
     FIG. 7 is a circuit block diagram showing a structure of the signal processing circuit of LNB  32 . Referring to FIG. 7, the signal processing circuit includes LNAs (Low Noise Amplifiers)  44   a  and  44   b , bandpass filters (BPFs)  45   a - 45   d , local oscillators  46   a  and  46   b , mixers  47   a - 47   d , a selector  48 , an IF amplifier  49 , a low-pass filter (LPF)  50  and a regulator  51 . 
     A horizontally polarized wave signal φh and a vertically polarized wave signal φv received by feed phone  42  are respectively amplified by LNAs  44   a  and  44   b  with noise kept low. An output signal of LNA  44   a  is supplied to bandpass filters  45   a  and  45   c  and an output signal of LNA  44   b  is supplied to bandpass filters  45   b  and  45   d.    
     Signals φh and φv have a frequency band of 10.7-12.75 GHz. Bandpass filters  45   a  and  45   b  pass only the frequency components in the range of 10.7 to 11.7 GHz of respective signals φh and φv. Bandpass filters  45   c  and  45   d  pass only the frequency components in the range of 11.7 to 12.75 GHz of respective signals φh and φv. Respective signals φh 1 , φv 1 , φh 2  and φv 2  passed through bandpass filters  45   a - 45   d  are supplied respectively to mixers  47   a - 47   d.    
     Local oscillator  46   a  generates a high-frequency signal of 9.75 GHz and supplies it to mixers  47   a  and  47   b . Local oscillator  46   b  generates a high-frequency signal of 10.6 GHz and supplies it to mixers  47   c  and  47   d . Signals φh 1  and φv 1  are converted respectively by mixers  47   a  and  47   b  into respective IF signals φ 1  and φ 2  of 950-1950 MHz. Signals φh 2  and φv 2  are converted respectively by mixers  47   c  and  47   d  into respective IF signals φ 3  and φ 4  of 1000-2150 MHz. 
     Selector  48  selects any of four IF signals φ 1 -φ 4  according to a DC voltage V 1  and a clock signal CLK supplied from DBS tuner  34  via input/output terminal  43  and low-pass filter  50  and supplies the selected IF signal to DBS tuner  34  via IF amplifier  49  and input/output terminal  43 . The DC voltage V 1  is 18 V or 13 V. The clock signal CLK has a frequency of 22 KHz and an amplitude of 0.6 V. Low-pass filter  50  allows DC voltage V 1  and clock signal CLK to pass while it does not pass IF signals φ 1 -φ 4 . 
     If DC voltage V is 18 V, signals φ 1  and φ 3  are selected. If DC voltage V 1  is 13 V, signals φ 2  and φ 4  are selected. If no clock signal CLK is input, signals φ 1  and φ 2  are selected and signals φ 3  and φ 4  are selected if clock signal CLK is input. Accordingly, signal φ 1  is selected if DC voltage V 1  is 18 V and no clock signal CLK is input, signal φ 2  is selected if DC voltage V 1  is 13 V and no clock signal CLK is input, signal φ 3  is selected if DC voltage V 1  is 18 V and clock signal CLK is input, and signal φ 4  is selected if DC voltage V 1  is 13 V and clock signal CLK is input. 
     DC voltage V 1  is also used as the supply voltage of regulator  51 . Regulator  51  uses DC voltage V 1  as the supply voltage to generate a DC constant voltage V 2  of 9 V and a DC constant voltage V 3  of 5 V. DC constant voltage V 2  of 9 V generated by regulator  51  is applied to IF amplifier  49  as its supply voltage, and DC constant voltage V 3  of 5 V generated by regulator  51  is applied to LNAs  44   a  and  44   b  and local oscillators  46   a  and  46   b  as their supply voltage. 
     In recent years, there arises a need to share one LNB by a plurality of DBS tuners  34 . For example, referring to FIG. 8, an LNB  55  shared by two DBS tuners  34  is provided with one feed phone  57  and two signal input/output terminals  58   a  and  58   b  on a casing member  56 . 
     Regarding such an LNB  55 , there is a problem that how supply voltages V 2  and V 3  for the LNA, local oscillator and IF amplifier should be generated. For example, according to the following description in conjunction with FIG. 9, two signal input/output terminals  58   a  and  58   b  are connected to a power supply node  61   a  of a regulator  61  via respective low-pass filters  59   a  and  59   b  and respective diodes  60   a  and  60   b . Diodes  60   a  and  60   b  are provided for preventing, when one of the two signal input/output terminals  58   a  and  58   b  is supplied with 18 V and the other thereof is supplied with 13 V, current flow from one signal input/output terminal to the other signal input/output terminal to cause malfunction or breakdown of DBS tuners  34 . 
     In this case, supposing that consumption current of LNB  55  is 200 mA, if DC voltages applied respectively to two signal input/output terminals  58   a  and  58   b  are the same (18 V or 13 V), currents of the same value (100 mA) flow through respective two signal input/output terminals  58   a  and  58   b . However, if 18 V and 13 V are supplied respectively to signal input/output terminals  58   a  and  58   b , current of 200 mA flows through signal input/output terminal  58   a  and no current flows through signal input/output terminal  58   b . On the contrary, if signal input/output terminals  58   a  and  58   b  are supplied with 13 V and 18 V respectively, current of 200 mA flows through signal input/output terminal  58   b  and no current flows through signal input/output terminal  58   a . For this reason, each time a channel is switched, current flowing from two DBS tuners  34  to LNB  55  greatly varies, generating noise. This noise causes a selector to malfunction, resulting in selection of a channel different from a desired channel or disorder of an image on a television receiver  38 . 
     SUMMARY OF THE INVENTION 
     One object of the present invention is accordingly to provide a receiving apparatus which can be shared by a plurality of tuners while noise is reduced. 
     According to the present invention, a receiving apparatus includes a plurality of signal input/output terminals connected respectively to a plurality of tuners, an extraction/amplification circuit extracting/amplifying a plurality of image signals from received radio waves, a switch circuit provided correspondingly to each signal input/output terminal to select one image signal according to a level of DC voltage supplied from a corresponding tuner and supplying the selected image signal to the tuner, and a power supply circuit driven by DC voltage supplied from each signal input/output terminal to generate supply voltage for the extraction/amplification circuit and equally distribute consumption current of the extraction/amplification circuit among the signal input/output terminals. Therefore, even if DC voltages applied respectively to the signal input/output terminals have respective levels different from each other, or even if the level of the DC voltage for each signal input/output terminal is changed, a constant current flows through each signal input/output terminal. Consequently, there is less noise compared with the conventional receiving apparatus where the current flowing through each signal input/output terminal considerably varies. 
     Preferably, the power supply circuit includes a first voltage generating circuit provided correspondingly to each signal input/output terminal and driven by DC voltage applied via the corresponding signal input/output terminal to generate a first DC voltage, a second voltage generating circuit driven by DC voltage applied via at least one signal input/output terminal to generate a second DC voltage, and a transistor provided correspondingly to each first voltage generating circuit and having a first electrode receiving the first DC voltage generated by the corresponding first voltage generating circuit and an input electrode receiving the second DC voltage generated by the second voltage generating circuit for providing supply current from its second electrode to the extraction/amplification circuit. In this way, currents of the same value flow through respective transistors, and the sum of the currents of the transistors correspond to consumption current of the extraction/amplification circuit. 
     Still preferably, the power supply circuit further includes a plurality of diode elements connected respectively between the signal input/output terminals and a power supply node of the second voltage generating circuit. In this way, from any signal input/output terminal supplied with the highest DC voltage, the second voltage generating circuit receives DC voltage via a corresponding diode element. 
     Still preferably, the receiving apparatus further includes an amplification circuit provided correspondingly to each signal input/output terminal and driven by the first DC voltage generated by its corresponding first voltage generating circuit to amplify the image signal from its corresponding switch circuit and transmit the amplified image signal to the corresponding signal input/output terminal. In this way, the image signal can be amplified sufficiently. Further, as no supply voltage is applied to any amplification circuit not in use, reduction of power consumption is possible. 
    
    
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a perspective view showing from the outside a structure of an LNB according to one embodiment of the present invention. 
     FIG. 2 is a circuit block diagram showing a structure of a signal processing circuit included in the LNB shown in FIG.  1 . 
     FIG. 3 is a block diagram showing a structure of a selector in FIG.  2 . 
     FIG. 4 is a circuit block diagram showing a structure of a power supply circuit in FIG.  2 . 
     FIG. 5 is a block diagram showing a structure of a receiving unit for a conventional satellite broadcasting system. 
     FIG. 6 is a perspective view showing from the outside a structure of an LNB in FIG.  5 . 
     FIG. 7 is a circuit block diagram showing a structure of a signal processing circuit included in the LNB in FIG.  6 . 
     FIG. 8 is a perspective view showing from the outside a structure of an LNB shared by two tuners. 
     FIG. 9 is a circuit block diagram for illustration of a problem of the LNB in FIG.  8 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a perspective view showing a structure of an LNB  1  from the outside according to one embodiment of the present invention. Referring to FIG. 1, LNB  1  includes a casing member  2 , a feed phone  3  provided on the surface thereof, and four signal input/output terminals  4   a - 4   d . Radio waves α reflected from a reflector  31  of an antenna  30  are supplied to an opening  3   a  of feed phone  3 . Within casing member  2 , a signal processing circuit for processing the radio waves α supplied to feed phone  3  is housed. LNB  1  is shared by four DBS tuners  34 . Four signal input/output terminals  4   a - 4   d  are connected respectively to DBS tuners  34  via cables. 
     FIG. 2 is a circuit block diagram showing a structure of the signal processing circuit of LNB  1 . Referring to FIG. 2, the signal processing circuit includes LNAs  5   a  and  5   b , bandpass filters  6   a - 6   d , local oscillators  7   a  and  7   b , mixers  8   a - 8   d , a selector  9 , IF amplifiers  10   a - 10   d , low-pass filters  11   a - 11   d , and a power supply circuit  12 . 
     A horizontally polarized wave signal φh and a vertically polarized wave signal φv received by feed phone  3  are converted into IF signals φ 1 -φ 4  similarly to those converted in the conventional LNB  32 . Specifically, signal φh is amplified by LNA  5   a  and supplied to bandpass filters  6   a  and  6   c . Signal φv is amplified by LNA  5   b  and supplied to bandpass filters  6   b  and  6   d . Signals φh 1 , φv 1 , φh 2  and φv 2  passing through respective bandpass filters  6   a - 6   d  are supplied to respective mixers  8   a - 8   d . A high-frequency signal generated by local oscillator  7   a  is supplied to mixers  8   a  and  8   b  and a high-frequency signal generated by local oscillator  7   b  is supplied to mixers  8   c  and  8   d . Signals φh 1 , φv 1 , φh 2  and φv 2  are converted respectively by mixers  8   a - 8   d  into respective IF signals φ 1 -φ 4 . 
     Referring to FIG. 3, selector  9  includes four sets of switch circuits  13   a - 13   d  and signal detection circuits  14   a - 14   d . Signal detection circuits  14   a - 14   d  set any of four signals S 1   a -S 4   a , . . . , S 1   d -S 4   d  at “H” (logical high) level of the activation level, according to DC voltages V 1   a -V 1   d  and clock signals CLKa-CLKd supplied from four DBS tuners  34  via signal input/output terminals  4   a - 4   d  and low-pass filters  11   a - 11   d  respectively. 
     Switch circuits  13   a - 13   d  select any of IF signals φ 1 -φ 4  according to output signals S 1   a -S 4   a , . . . , S 1   d -S 4   d  of signal detection circuits  14   a - 14   d  and supply the selected IF signal to IF amplifiers  10   a - 10   d.    
     Regarding switch circuit  13   a  and signal detection circuit  14   a , if DC voltage V 1   a  is 18 V and clock signal CLKa is not input, signal S 1   a  is set at H level to select signal φ 1 . If DC voltage V 1   a  is 13 V and clock signal CLKa is not input, signal S 2   a  is set at H level to select signal φ 2 . If DC voltage V 1   a  is 18 V and clock signal CLKa is input, signal S 3   a  is set at H level to select signal φ 3 . If DC voltage V 1   a  is 13 V and clock signal CLKa is input, signal S 4   a  is set at H level to select signal φ 4 . Other switch circuits  13   b - 13   d  and signal detection circuits  14   b - 14   d  operate similarly to switch circuit  13   a  and signal detection circuit  14   a.    
     IF amplifiers  10   a - 10   d  respectively amplify IF signals from respective switch circuits  13   a - 13   d  and supply them to signal input/output terminals  4   a - 4   d . Low-pass filters  11   a - 11   d  respectively allow DC voltages V 1   a -V 1   d  and clock signals CLKa-CLKd to pass while they do not pass IF signals. DC voltages V 1   a -V 1   d  are also used as supply voltage for power supply circuit. 
     Referring to FIG. 4, power supply circuit  12  includes regulators  21   a - 21   d ,  27  and  28 , diodes  22   a   14   22   d  and  26   a - 26   d , NPN bipolar transistors  23   a - 23   d , and resistor elements  24   a - 24   d  and  25   a - 25   d.    
     Respective power supply nodes of regulators  21   a - 21   d  are connected to respective output nodes of low-pass filters  11   a - 11   d . Regulators  21   a - 21   d  respectively generate DC constant voltages V 2   a -V 2   d  of 9 V using as respective supply voltages the DC voltages V 1   a -V 1   d  passed through low-pass filters  11   a - 11   d . DC constant voltages V 2   a -V 2   d  of 9 V are used as respective supply voltages for IF amplifiers  10   a - 10   d.    
     Diodes  22   a - 22   d  are connected between respective output nodes of regulators  21   a - 21   d  and respective collectors of transistors  23   a - 23   d . Resistor elements  24   a - 24   d  are connected between respective emitters of transistors  23   a - 23   d  and a power supply node  28   a  of regulator  28 . Regulator  28  generates a DC constant voltage V 3  of 5 V using voltage applied to power supply node  28   a  as its supply voltage. DC constant voltage V 3  of 5 V is used as supply voltage for LNAs  5   a  and  5   b  and local oscillators  7   a  and  7   b.    
     Diodes  26   a - 26   d  are connected between respective output nodes of low-pass filters  11   a - 11   d  and a power supply node  27   a  of regulator  27 . Resistor elements  25   a - 25   d  are connected between an output node  27   b  of regulator  27  and respective bases of transistors  23   a - 23   d . Regulator  27  generates a DC constant voltage V 4  of 8 V using voltage applied to power supply node  27   a  as its supply voltage. DC constant voltage V 4  of 8 V is uses as base voltage for transistors  23   a - 23   d.    
     Suppose that 13 V is applied to signal input/output terminal  4   a  and 18 V is applied to signal input/output terminals  4   b - 4   d . Regulators  21   a - 21   d  output constant voltages V 2   a -V 2   d  of 9 V respectively. 18 V is applied to regulator  27  from signal input/output terminals  4   b - 4   d  via diodes  26   b - 26   d  and regulator  27  outputs DC constant voltage V 4  of 8 V. Accordingly, consumption current of LNAs  5   a  and  5   b  and local oscillators  7   a  and  7   b , i.e., consumption current  4   i 0 of regulator  28  is distributed among four transistors  23   a - 23   d  so that the same current i 0  flows through each of the transistors  23   a - 23   d . Consumption currents of regulators  21   a - 21   d  are respectively the sums of currents i 0  flowing through respective transistors  23   a - 23   d  and currents flowing through respective IF amplifiers  10   a - 10   d , therefore, respective consumption currents of regulators  21   a - 21   d  have almost the same current value. Since the base current of transistors  23   a - 23   d  is smaller enough than emitter current i0, current flowing through diodes  26   b - 26   d  is sufficiently smaller than current flowing through signal input/output terminals  4   a - 4   d.    
     In this LNB  1 , regardless of voltage (13 V, 18 V) applied to each of the four signal input/output terminals  4   a - 4   d , currents of the same value flow through respective signal input/output terminals  4   a - 4   d . Therefore, even if each of the four DBS tuners  34  connected to four input/output terminals  4   a - 4   d  switches its channel, there is no change in current flowing through signal input/output terminals  4   a - 4   d  and accordingly no noise is generated. 
     If only three signal input/output terminals  4   a - 4   c  among four signal input/output terminals  4   a - 4   d  are connected to tuners, consumption current of regulator  28  is equally distributed among three transistors  23   a - 23   c  and currents of the same value flow through three signal input/output terminals  4   a - 4   c  respectively. As no current flows through regulator  21   d  and transistor  23   d , current is never consumed wastefully. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.