Abstract:
A gain control circuit includes an audio signal attenuator circuit and a circuit for controlling the current in the audio signal attenuator circuit. The audio signal attenuator circuit is inserted between an input terminal of an amplifier circuit for amplifying an audio signal and an output terminal of a diode for detecting and rectifying part of the audio signal appearing at the output terminal of the amplifier circuit. The signal attenuator circuit and the current control circuit comprise a plurality of transistors and operate when, in response to application of an audio signal to the amplifier circuit, a DC voltage of certain level is produced at the output terminal of the rectifying diode. Part of the audio signal applied to the amplifier circuit is bypassed and attenuated, while at the same time stabilizing the DC bias in the amplifier circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a gain control circuit for the automatic record level adjustment in the sound recording circuit of a tape recorder or the like, or more in particular to a gain control circuit whose elements are adapted to be arranged in integrated circuits. 
     2. Description of the Prior Art 
     One of the conventional gain control circuits used for tape recorders or like devices is shown in FIG. 1. In this drawing, reference numeral 10 shows an input signal source for, say, an audio signal ei. Numeral 20 shows an amplifier circuit, which in this case is a differential amplifier circuit, for amplifying and introducing to the output terminal 5 the audio signal ei applied through the resistor Ra and the capacitor Ca to the input terminal (pin) 1. Reference characters Q 1  and Q 2  show an NPN differential transistor pair with the emitters thereof connected to each other on the one hand and to the ground terminal 6 through the resistor R 5  on the other. The base of the transistor Q 1  is connected to the input terminal 1 and also, through the resistors R 3  and R 1 , to the DC power supply terminal 7 supplied with a DC voltage. The base of the transistor Q 1  is further connected to the ground terminal 6 through the resistors R 3  and R 2 . The collector of the transistor Q 1  is connected through the resistor R 4  to the power supply terminal 7 on the one hand and to the base of the PNP transistor Q 3  on the other. The collector of the transistor Q 2  is connected directly to the power supply terminal 7, while its base is connected via the resistor R 6  to the terminal 4 on the one hand and to the collector of the transistor Q 3  through the resistor R 7  on the other. The collector of the transistor Q 3  is connected to the earth terminal 6 via the resistor R 9  and also to the output terminal 5. The emitter of the transistor Q 3  is connected via the resistor R 8  to the power terminal 7. Terminal 1 is grounded through the capacitor Ca, the resistor Ra  and the signal source 10. Terminal 4 is grounded through the capacitor Cc, while the terminal 6 is grounded directly. Terminal 5 is connected to the input terminal of an amplifier circuit in the next stage (not shown). Numeral 30 shows an audio signal attenuator circuit including a controlled transistor Q 4  for bypassing part of the audio signal ei to the ground terminal, and numeral 40 a rectifier circuit for detecting and rectifying part of the audio signal produced at the output terminal 5 of the amplifier circuit 20. The resulting rectified signal is used to control the controlled transistor Q 4  of the audio signal attenuator circuit 30. 
     In the circuit configuration of FIG. 1, the part defined by a dotted line shows an integrated circuit. Assume that the audio signal ei is applied to the input terminal of the amplifier circuit 20 via the resistor Ra and the capacitor Ca. An amplified audio signal is produced at the output terminal 5 of the amplifier circuit 20. Part of the audio signal is rectified by the rectifier circuit 40, and the rectified DC signal is applied to the base of the controlled transistor Q 4  of the audio signal attenuator circuit 30. As a result, the transistor Q 4  is forward biased and controlled in such a manner that the collector-emitter impedance thereof decreases with the increase in the DC signal. Part of the audio signal ei from the audio signal source 10 is thus attenuated by bypassing it via the transistor Q 4  thereby to control the gain of the whole circuit. 
     In this conventional gain control circuit in which the collector-emitter impedance of the controlled transistor Q 4  is controlled so that the input signal ei  is attenuated by bypassing a part of the input signal ei to the ground terminal via the transistor Q 4  so as to control the gain of the whole circuit, the collector-emitter DC voltage Vce of the transistor Q 4  is generally set at zero so as to provide a great change in the collector-emitter impedance of the transistor Q 4  when a DC signal is applied to the base of the controlled transistor Q 4 . In other words, unless the DC voltage Vce between the collector and emitter of the transistor Q 4  is set at zero, the collector-emitter impedance of the transistor Q 4  cannot be satisfactorily changed, thus making an effective gain control impossible. For this reason, the capacitor Ca or the like is required to be inserted between the collector terminal 2 of the transistor Q 4  and the input terminal 1 of the sound amplifier circuit 20 for providing DC isolation. This configuration, which presents no significant problem in the case of the circuit being comprised of discrete circuit elements, is very disadvantageous in the application of a monolithic integrated circuit thereto, because of the need for one additional terminal pin, which might involve a problem in the design of integrated circuits having a limited number of terminals. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a gain control circuit with a small number of terminals suitable for application of monolithic integrated circuit, in which the output terminal of the gain control circuit may be connected to the input terminal of the sound amplifier circuit in DC mode, not through a capacitor. 
     Another object of the invention is to provide a gain control circuit in which, irrespective of the magnitude of the control signal, a DC current is prevented from, say, flowing out to another circuit and affecting the bias potential of the same circuit. 
     In order to achieve the above-mentioned objects, the gain control circuit according to the present invention is characterized in that part of the audio signal from the audio signal circuit is detected and rectified, that part of the audio signal applied to the input terminal of a sound amplifier circuit in the audio circuit is bypassed and attenuated by an audio signal attenuator circuit which is actuated when a DC voltage resulting from the detection and rectification of the part of the audio signal exceeds a predetermined level, and that the output part of the audio signal attenuator circuit is floating in DC mode. The output terminal of the audio signal attenuator circuit is connected to the input terminal of the sound amplifier circuit. The potential of the output part of the audio signal attenuator circuit is set by the bias potential of the amplifier circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a conventional gain control circuit. 
     FIG. 2 is a circuit diagram showing an embodiment of the gain control circuit according to the present invention. 
     FIGS. 3a and 3b are diagrams showing equivalent circuits of the audio signal attenuator circuit and a control circuit therefor shown in FIG. 2. 
     FIGS. 4, 5 and 6 are circuit diagrams showing other embodiments of the control circuit of the audio signal attenuator circuit of FIG. 2. 
     FIGS. 7, 8, 12 and 13 are circuit diagrams showing other embodiments of the gain control circuit according to the invention. 
     FIGS. 9a and 9b are equivalent circuit diagrams of the audio signal attenuator circuit and the control circuit in FIG. 8. 
     FIGS. 10 and 11 are circuit diagrams showing other embodiments of the control circuit of the audio signal attenuator circuit of FIG. 8. 
     FIGS. 12 and 13 are circuit diagrams showing additional embodiments of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will be now described with reference to specific embodiments. A circuit diagram showing an embodiment of the invention is shown in FIG. 2. In the circuit configuration of FIG. 2, like component elements as in FIG. 1 are denoted by like reference numerals and will not be described again. 
     The circuit of FIG. 2 according to the invention is different from the conventional circuit in that in the circuit under consideration, an attenuator circuit 30 includes an audio signal attenuator circuit 31 having a plurality of transistors Q 9  and Q 10 , and a current control circuit 32 for the audio signal attenuator circuit 31, having a plurality of transistors and resistors, the current control circuit 32 including transistors Q 4 , Q 5 , Q 6 , Q 7  and Q 8 . 
     The bases of the PNP transistors Q 8  and Q 5  are connected not only to each other but also to the collector of the transistor Q 5 . The emitters of the transistors Q 8  and Q 5  are connected to the DC power terminal 7 via the resistors R 10  and R 11  respectively. The collector of the transistor Q 8  is connected to the emitter of the PNP transistor Q 6  on the one hand and to the base of the NPN transistor Q 9  of the signal attenuator circuit 31. The collector of the transistor Q 5  is connected to the collector of the NPN transistor Q 7 . The bases of the transistors Q 6  and Q 7  are connected not only to each other but also, through the resistor R 6  of the differential amplifier circuit 20, to the reverse input terminal, that is, the base of the differential transistor Q 2 . The collector of the transistor Q 6  is connected directly to the ground terminal 6, while the emitter of the transistor Q 7  is connected to the collector of the NPN transistor Q 4  and also to the base of the PNP transistor Q 10  of the signal attenuator circuit 31. The emitter of the transistor Q 4  is connected to the ground terminal 6 via the resistor R 12 , while the base thereof is connected directly to the gain control voltage supply terminal 3. The emitters of the transistors Q 9  and Q 10  of the signal attenuator circuit 31 are connected not only to each other but also to the non-reverse input terminal of the differential amplifier circuit 20, i.e., to the base of the differential transistor Q 1 . The collector of the transistor Q 10  is connected directly to the ground terminal 6. The differential amplifier circuit 20, the audio signal attenuator circuit 31 and the control circuit 32 for the circuit 31 are constructed of integrated circuits respectively. The anode of the rectifying diode Da of the rectifier circuit 40 is connected to the output terminal 5 of the differential amplifier circuit 20, while the cathode thereof is connected through the capacitor Cb to the ground on the one hand and to the gain control voltage supply terminal 3 on the other. 
     In the circuit configuration shown in FIG. 2, assume that current I 2  flows in the transistors Q 8  and Q 6  of the attenuator circuit 30, that current I 1  flows in the transistors Q 5  and Q 7 , and that currents I 3  and I 4  flow in the transistors Q 9  and Q 10  respectively. The impedances r 9  and r 10  as viewed from the emiters of the transistors Q 10  is expressed as ##EQU1## where r e6 , r e7 , r e9 , r e10  = emitter diffusion resistances of transistors Q 6 , Q 7 , Q 9 , Q 10  respectively 
     h fe9 , h fe10  = current amplification factor of emitter-grounded transistors Q 9  and Q 10  respectively 
     26 = emitter-base impedance of the transistor obtained from q/kT 
     q = electric charges 
     k = Boltzman constant 
     T = temperature 
     Also, the impedance Z 30  at the side of the attenuator circuit 30 as viewed from the input terminal 1 is, from the equivalent circuit of FIG. 3, expressed as ##EQU2## Substituting the equations (1) and (2) into the equation (3), ##EQU3## 
     The impedance Z at the side of the amplifier circuit 20, the signal attenuator circuit 31 and the control circuit 32 of the attenuator circuit 30 as viewed from the input terminal 1 is given by ##EQU4## (R&#39; = impedance of transistor Q 1 ) 
     Further, the input signal ei is attenuated by the resistance Ra and impedances of the amplifier circuit 20 and the signal attenuator circuit 31, so that the input signal ei at the input terminal 1 is ##EQU5## When substituting the equations (5) and (6) into the equation (7), ##EQU6## The equation (8) represents the value of the input signal obtained as a result of attenuation of the input signal ei by the impedance of the amplifier circuit 20 and the attenuator circuit 30. This value depends on the magnitude of the impedance Z. 
     In this circuit configuration, assume that the DC voltage at the gain control voltage supply terminal 3 in the absence of signal or presence of a small signal, i.e., the DC voltage obtained by rectifying a part of the audio output signal of the amplifier circuit 20 by the rectifying diode Da, is zero, or less than the base-emitter voltage of the transistor Q 4  in the attenuator circuit 30, i.e., the threshold voltage thereof, say, 0.6 or 0.7 V. In such a case, the transistors Q 4 , Q 5 , Q 6 , Q 7 , Q 8 , Q 9  and Q 10  of the attenuator circuit 30 are set in non-conducting state. 
     When the transistors of the attenuator circuit are in non-conductive state, the impedance Z 30 , as given by equation (3), of the signal attenuator circuit 31 and the control circuit 32 as measured at the input terminal 1 is as high as to be almost infinite. As a result, all of the input signal ei of the input signal source 10 is introduced through the resistor Ra, capacitor Ca and the input terminal 1 to the differential amplifier circuit 20 for amplification. In the process, the input signal ei is not attenuated by the signal attenuator circuit 31, though it is somewhat attenuated by the resistor Ra and the impedance of the amplifier circuit 20. 
     From the equation (8), the attenuation is ##EQU7## This attenuation, however, is very small. 
     Next, assume a case where the input signal ei is increased in level to such an extent that an increased rectifying voltage of the rectifying diode Da causes the DC voltage at the gain control voltage supply terminal 3 to be increased, with the result that the DC voltage exceeds the base-emitter voltage of the transistor Q 4  of the attenuator circuit 30. The transistor Q 4  is biased in forward direction and begins to conduct. This is followed by the conduction of the other transistors Q 5 , Q 6 , Q 7 , Q 8 , Q 9  and Q 10 . A DC current I 1  flows from the DC power terminal 7 to the earth terminal through the resistor R 11 , transistors Q 5 , Q 7  and Q 4  and resistor R 12 , while a DC current I 2  flows through the resistor R 10 , transistors Q 8  and Q 6 . Further, a DC current I 3  flows in the transistor Q 9 , and a DC current I 4  in the transistor Q 10 . If resistor R 10  = R 11 , the DC current I 1  is equal to the DC current I 2 . Also, assume that all the transistors in the circuit of FIG. 2 have the same characteristics and that the current amplification factors h fe  thereof are so large as to permit the base current to be neglected. The emitter potential of the transistors Q 9  and Q 10  of the signal attenuator circuit 31, i.e., the base potential V B1  of the transistor Q 1   of the differential amplifier circuit 20, the base potential V B2  of the transistor Q 2 , and the base potential V B2  &#39; of the transistors Q 6  and Q 7  of the control circuit 32 are equal to each other. Therefore, the base-emitter voltage V be7  of the transistor Q 7  is equal to the base-emitter voltage V be10  of the transistor Q 10 . In like manner, the base-emitter voltage V be6  of the transistor Q 6  is equal to the base-emitter voltage V be9  of the transistor Q 9 . As a result, the DC currents I 1 , I 2 , I 3  and I 4  have the relations I 1  = I 4  and I 2  = I 3 . Since I 1  = I 2 , the DC current I 3  is also equal to the current I 4 . Under this condition, the DC current at the emitter terminal of the signal attenuator circuit 31 does not flow outside or into the amplifier circuit 20. Also no DC current flows thereto from the amplifier circuit 20. Therefore, even though the output terminal of the signal attenuator circuit 31 is connected directly in DC mode to the input terminal of the differential amplifier 20, the DC bias of the amplifier circuit 20 is not affected by the signal attenuator circuit 31. In other words, the DC bias of the amplifier circuit 20 is maintained stable as it is not affected by the signal attenuator circuit 31. 
     When the transistors in the circuit 30 conduct and current flows in them as described above, the output impedance Z 30  of the attenuator circuit 30 as viewed from the input terminal 1 is reduced. 
     Now, let us consider a case involving a small signal, for example, a case where the input signal is such that the impedance of the attenuator circuit 30 is expressed as ##EQU8## The audio signal ei applied to the terminal 1 is attenuated to the effective input signal ei&#39; that is, from equations (8), (4&#39;), (5) and (6), given as ##EQU9## 
     With a further increase in the input signal, the output impedance Z 30  of the attenuator circuit 30 as viewed from the input terminal 1 is accordingly further reduced. 
     Assume a case where the input signal is such that the impedance Z 30  of the attenuator circuit 30 is ##EQU10## From the equations (8), (4&#34;), (5) and (6), the effective input signal ei&#39; is ##EQU11## The amount of attenuation of the input signal ei is thus increased. 
     When the input signal still further increases until the impedance Z 30  of the attenuator circuit 30 is expressed as ##EQU12## the input signal ei&#39; is given as below from the equations (8), (4&#39;&#39;&#39;), (5) and (6). ##EQU13## It will be seen that the amount of attenuation of the input signal ei is increased even more. 
     When the input signal is increased to such a degree that the AC signal produced at the terminal 1 exceeds several mV, the transistors Q 9  and Q 10  of the signal attenuator circuit 31 of the attenuator circuit 30 enter a non-linear region and are distorted. This distortion may be somewhat corrected by increasing the value of the resistor Ra. Since an increased resistance value of the resistor Ra is accompanied by an increased attenuation in the absence of signal as noted from equation (9), however, the allowable range of increase in the value of the resistor Ra has a certain limitation. 
     In spite of this, in view of the present target of automatic gain control in terms of variation range or effective range thereof is approximately 30 dB, the resistor Ra of 5 KΩ or more adequately serves practical purposes. 
     By the way, it will be seen that the resistors R 10  and R 11  in the circuit of FIG. 2 are basically not required. In actual circuits, however, it is impossible that all the transistors have the same characteristics and therefore the current I 3  is not equal to the current I 4 . The DC current flows either out of or into the output terminal of the signal attenuator circuit 31, thus changing the reference voltage V B1  of the differential amplifier circuit 20. The result is that the DC voltage at the output terminal of the circuit 20 undergoes a change, so that when the gain control works very effectively, the linearity of the differential amplifier circuit 20 is affected. Generally, the characteristics of a PNP transistor in integrated circuits are different from those of an NPN transistor in the same circuits. In other words, the base-emitter voltage V BE  of a PNP transistor is a little higher than that of an NPN transistor due to the same collector current. Therefore, the currents I 1 , I 4 , I 3  I 2  have relations I 1  &gt;  I 4  and I 3  &gt; I 2 . If the current I 1  is equal to the current I 2 , I 3  is larger than I 4 , thereby causing the current I x  (= I 3  - I 4 ) to flow out from the signal attenuator circuit 31 to the differential amplifier circuit 20. In order to prevent this phenomenon, the resistance value of the resistor R 10  is rendered larger than that of resistor R 11  thereby to hold a relation I 1  &gt; I 2 . Further, it is arranged to make the current I 3  equal to I 4  by adjusting the values of resistors R 10  and R 11 . 
     Another embodiment of the control circuit for the signal attenuator circuit is shown in FIG. 2. Examples of the embodiment are shown in the circuit diagrams of FIGS. 4, 5 and 6, in which like component elements are denoted by like reference numerals as in FIG. 2. 
     A current correcting circuit 33 including a pair of transistors Q 6  and Q 11  is added in the circuit of FIG. 4 for correcting the current in the gain control circuit, the transistors Q 6  and Q 11  being configured differentially. The base of the transistor Q 11  is connected to such a potential point that the base potential V B11  of the transistor Q 11  in the absence of a control signal at the terminal 3 is equal to the base potential V B2  &#39; of the transistors Q 6  and Q 7 . By so doing, in the case where in response to a control signal applied, the current I x  increases thereby to increase the base potential V B2  &#39;, the current I 2  is caused to flow to the transistor Q 11  so as to reduce the base-emitter voltage V BE6  of the transistor Q 6 , resulting in a reduced current I 3 . 
     The circuit of FIG. 5 features a current-correcting circuit 33&#39; including differentially-configured transistors Q 14 , Q 12  and Q 13  for correcting the current in the gain control circuit. The resistance values of the resistors R 13  and R 14  are so set that the base potential V B14  of the transistor Q 14  is equal to the base potential V B2  &#39; of the transistor Q 6  or Q 7 . As a result, the current I x  flows out (I 3  being larger than I 4 ) in the direction of arrow and, with the increase in the base potential V B2  &#39; of the transistors Q 6  and Q 7 , the current I 2  &#34; becomes larger than I 1  &#34;, while I 2  &#39; becomes smaller than I 1  &#39;, thereby reducing the current I 3 . The opposite is true when the current I x  flows in the direction opposite to the arrow in the case of I 3  being smaller than I 4 . In any of the above-mentioned cases, the circuit operates in such a way as to reduce the amount of current I x , thereby minimizing the variation of the base potential V B1  of the transistor Q 1 . 
     The circuit of FIG. 6 is newly provided with the current-correcting circuit 33&#34; including the transistors Q 14  and Q 15  for correcting the current in the gain control circuit. The resistance values of the resistors R 13  and R 14  are set in such a manner that the base potential V B14  of the transistor Q 14  is equal to V B1  plus the base-emitter voltage V BE14  of the transistor Q 14 . When the base potential V B1  of the transistor Q 1  is reduced by the flow of current I x  in the direction opposite to the arrow (i.e., when I 3  is smaller than I 4 ), the current I 1  &#34; increases while the current I 1  &#39; decreases. So, the current I 3  also decreases thereby to reduce the current I x . The opposite is true when the current I x  flows in the direction of arrow (when the current I 3  is larger than I 4 ). In both cases, the circuit operation is such as to reduce the current I x  . 
     Still another embodiment of the invention is illustrated in FIG. 8. In this drawing, like component parts are denoted by like reference numerals as in FIGS. 2 to 6 and will not be described again. In this circuit configuration, the bases of the NPN transistors Q 4  and Q 18  of the control circuit 32&#39; are connected to each other and also to the gain control voltage supply terminal 3. The emitters of the transistors Q 4  and Q 18  are also connected to each other and further to the earth terminal 6 through the resistor R 12 . The collector of the transistor Q 4  is connected directly to the collector of the transistor Q 5 , the base of which is connected to the base of the transistor Q 8 . The base of transistor Q 5  is connected to the collector of transistor Q 5 . The collector of the transistor Q 18  is connected to the base and collector of the PNP transistor Q 17 , the emitter of which is connected to the emitter of the NPN transistor Q 16 . The collector of the transistor Q 18  is also connected to the base of the PNP transistor Q 10 , the emitter of which is connected to the emitter of transistor Q 9  of the signal attenuator circuit 31. The emitter common to the transistors Q 16  and Q 17  is connected to the base of the transistor Q 2  of the differential amplifier circuit 20 through the resistor R 6 . The emitter common to the transistors Q 10  and Q 9  is connected directly to the signal input terminal 1 and the base of the transistor Q 1  of the differential amplifier circuit 20 respectively. The collector and base of the transistor Q 16  which are connected to each other are further connected to the collector of the transistor Q 8  and the base of the NPN transistor Q 9 . 
     In this circuit configuration, assume that no DC voltage is applied to the terminal 3. All the transistors in the attenuator circuit 30 are in non-conducting state, and the DC and AC impedances as viewed from the input terminal 1 toward the circuit 30 are very high. As a result, the input signal ei to the terminal 1 is introduced in its entirety to the differential amplifier circuit 20 through the resistor Ra and the capacitor Ca. 
     By contrast, assume that a DC voltage exceeding the base-emitter voltage of the transistors Q 18  and Q 4  is applied to the terminal 3. The DC current I 1  flows through the resistor R 11  and transistors Q 5  and Q 4 , while the DC current I 2  flows through the resistor R 10  and the transistors Q 8 , Q 16 , Q 17  and Q 18 . Since the bases of the transistors Q 8  and Q 5  are commonly connected, the current I 1  equals current I 2  if resistor R 10  is equal to resistor R 11 . Under this condition, suppose all the transistors have the same characteristics and that the emitter-grounded DC current amplification factor h fe  thereof is set so high as to permit the base current to be ignored. The base potential V B1  of the transistor Q 1 , the base potential V B2  of the transistor Q 2  and the emitter potential V B2  &#39; of the transistors Q 16  and Q 17  are equal to each other, so that the currents I 2 , I 3  and I 4  are also equal to each other, thus preventing a DC current from flowing out of or flowing into the attenuator circuit. For this reason, in spite of the fact that the output terminal of the signal attenuator circuit 31 is connected directly to the input terminal of the amplifier circuit 20 as in the embodiment of FIG. 2, the DC bias of the amplifier circuit 20 is not affected by the signal attenuator circuit 31. 
     A circuit equivalent to the circuit of FIG. 8 is shown in FIG. 9, in which the output impedance of the attenuator circuit 30 as viewed from the input terminal 1, like the preceding embodiment, is expressed as ##EQU14## On the other hand, the effective input signal ei&#39; at the input terminal 1 is given by ##EQU15## As in the preceding embodiment, the input signal is attenuated as shown in equation (10) above. 
     It will be seen that, in the embodiment of FIG. 8 also, neither resistor R 10  nor R 11  is required in principle. Due to the fact that all the transistors are not the same in characteristics in an actual circuit, however, the current I 3  is not equal to I 4 . This causes a current outflow from or inflow into the output terminal of the signal attenuator circuit 31, with the result that the reference voltage V B1  of the differential amplifier circuit 20 is changed thereby to vary the DC voltage at the output terminal 5 of the amplifier circuit 20, thus affecting the linearity of the differential amplifier circuit 20 in the case where a gain control works very effectively. 
     The circuits of FIGS. 10 and 11 feature a circuit 34 included in the current control circuit 32 for correcting the current flowing in the circuit 32. The DC voltage, for example, in the signal attenuator circuit 31 is prevented from flowing out to the side of the differential amplifier circuit 20 thereby to save the loss of the linearity of the amplifier circuit 20. In FIG. 10, the transistors Q 12 , Q 13 , Q 14  and resistors R 13 , R 14  and R 15  make up the correcting circuit 34. The base of the transistor Q 14  is connected to a point of the same potential as the base potential V B1  of the transistor Q 1  in the absence of a control signal at the terminal 3. In other words, the resistors R 13  and R 14  are set in advance in such a manner as to obtain the relation V B14  = V B1 . 
     Now, assume that current I 3  is smaller than I 4  and that the difference I x  therebetween flows in the direction of the arrow. The reference voltage V B1  of the differential amplifier 20 is reduced thereby to reduce the voltage V B2  &#39; also. The voltage V B2  &#39;becomes lower than V B14 , thereby increasing the current I 1  &#34;. Although the current I 2  also increases, the current I 2  &#39; remains unchanged. Therefore, the increment of the current I 2  is equal to the increase in the base current of the transistor Q 9 , with the result that the current I 3  increases while the current I x  decreases. In the event that the current I x  flows in the direction opposite to the arrow, by contrast, the current I 3  is larger than I 4 , so that the voltage V B1  tends to increase. In spite of this, the correcting circuit 34 works the way opposite to the preceding case. Thus, in both cases, the correcting circuit 34 functions to dampen the variation of the voltage V.sub. B1. In FIG. 10, if a resistor of several K Ω is inserted between the bases of the transistors Q 16  and Q 9  to compensate for the difference between the current amplification factors h fe  of the transistors Q 9  Q 10 , it is possible to prevent the deterioration of third harmonic distortion at the time of gain control operation. In FIG. 11, a circuit portion including the transistors Q 12  and Q 14  and resistors R 13  and R 14  makes up the current-correcting circuit 34&#39; for the attenuator circuit 30. The resistance values of the resistors R 13  and R 14  are set in such a way that the base potential V B14  of the transistor Q 14  in the signal attenuator circuit 31 is equal to V B1  plus the base-emitter voltage V BE14  of the transistor Q 14 . When the current I x  flows in the direction of the arrow (I 4  &gt; I 3 ), the voltage V B1  drops. Since the voltage V B19  also drops, the current I 1  &#34; increases, thereby causing the increase in the base current of the transistor Q 9  and the increase in the emitter current I 3 , resulting in the current I x  being decreased, as already explained with reference to FIG. 10. In this way, the circuit functions to dampen the voltage V B1 . 
     In the case where the current I x  flows in the direction opposite to the arrow (I 4  &lt; I 3 ), by contrast, the voltage V B1  and the voltage V B19  increase. Current I 1  &#34; and current I 2  &#39; are reduced, whereas the current I 2  rmains unchanged. Accordingly, the base current of the transistor Q 9  is reduced, thereby causing the reduction of current I 3  and hence the current I x , thus preventing the potential V B1  from increasing. 
     In any case, the circuit works in such a way as to reduce the variation of the base potential V B1  of the transistor Q 1 . 
     In the above-mentioned embodiment, the output terminal of the signal attenuator circuit 31 is connected to the non-reversing input terminal of the differential amplifier circuit 20, while the reference bias voltage terminal of the current control circuit 32 is DC-connected to the reversing input terminal of the differential amplifier circuit 20 for the purpose of circuit integration, thereby making it possible to reduce the number of external terminals. If no limitation is imposed on the number of external terminals, however, the reference bias voltage terminal may be connected to any point on condition that such a reference bias voltage terminal is at the same DC potential as the input terminal of the amplifier circuit in subsequent stage and that the AC impedance between the reference bias voltage terminal and ground is very low. Examples of such a circuit connection are shown in FIG. 7 and 12. The amplifier circuit is subsequent stage, which is shown as a differential type, need not necessarily be of differential type as contrast with the circuit diagram of FIG. 13. In FIG. 12, the deterioration of third harmonic distortion during the gain control operation may be prevented by inserting a resistor of several KΩ between the junction of the collector and base of the transistor Q 16  and the base of transistor Q 9 . 
     According to the present invention, the output terminal of the input signal attenuator circuit may be connected directly to the input terminal of the input signal amplifier circuit, and therefore a single terminal may be used for them, thereby reducing the number of terminals. 
     Also, the decreased number of terminals made possible by the invention facilitates the application of monolithic integrated circuits thereto. 
     Further, according to the present invention, the DC current of the input signal attenuator circuit is prevented from flowing into the audio signal amplifier circuit, so that the DC bias of the amplifier circuit is not affected by the DC current.