Abstract:
The present invention provides a chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, marks different every chip are formed in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to a chip ID applying method for specifying positions on a wafer where semiconductor chips are fabricated.  
         [0002]     An integrated circuit is generally manufactured in accordance with the following flow.  
         [0003]     (1) A large number of chips are fabricated on a wafer.  
         [0004]     (2) After the formation of each circuit on the wafer, various electrical function tests are conducted in a state in which the wafer is held as it is.  
         [0005]     The process steps (1) and (2) executed so far are generally called a pre-process or wafer process. The following process steps (3) through (5) are generally called a post-process or package process.  
         [0006]     (3) The individual chips are separated from one another to bring them into fractionization.  
         [0007]     (4) The fractionized chips are respectively encapsulated in plastic or a ceramic package.  
         [0008]     (5) After encapsulation of each chip in the package, the product is completed as the integrated circuit through a final test.  
         [0009]     The pre-process for building a large number of chips in the wafer shown in the previous process step (1) will next be explained. A technique called photolithography is normally used to build each circuit in the wafer in the pre-process. This technique is the technology of allowing circuit patterns formed in a mask (reticle) to be exposed onto the wafer using light and thereby transferring the circuit patterns. Since circuit patterns corresponding to plural chips each having the same circuit pattern are normally fabricated in a mask (e.g., 4 chips wide×4 chips deep), the circuit patterns corresponding to plural chips (e.g., 4×4=16 chips) can be transferred by one exposure (shot). Incidentally, the circuit patterns cannot be normally transferred over the whole area of one wafer by one shot alone. Therefore, in order to transfer the circuit patterns over the whole area of the one wafer, a stage with the wafer placed thereon is moved in the horizontal and vertical directions and the shot is repeated plural times, thereby transferring the circuit patterns onto the whole surface of the wafer. This system is called “a step-and-repeat system”. In the present photolithography process, only circuit patterns corresponding to one wiring layer per process step even at the maximum can be transferred. However, a complex structure or circuit having a number of wiring layers can be fabricated by repeating the photolithography process many times. In the integrated circuit manufacturing process, a few tens to a few hundreds of chips each having circuit patterns exactly identical to one another are fabricated on one wafer while the lithography process is being repeated again and again in this way.  
         [0010]     Incidentally, if it is possible to recognize whether each individual completed integrated circuit corresponds to a chip formed at any position on the wafer, then the dependence of the degree of variations in various electrical characteristics on wafer in-plane positions, and the like can be examined. Therefore, information indicative of whether each individual chip being fabricated at any location in the wafer in-plane becomes information important in light of quality management. Since such information is of information descriptive of production histories different every chip, the information is called a chip ID in the sense that it is ID for each individual chip. The information is fabricated or built in each integrated circuit as electrically-indelible information.  
         [0011]     Since the chips identical to one another are manufactured in large quantities at a time in the conventional integrated circuit manufacturing method as already described above, it is difficult to build the chip IDs at a pre-process stage. Therefore, the conventional method of manufacturing the semiconductor integrated circuit needed to provide an exclusive special-purpose process step within the post-process. Described specifically, IDs set for each chip are written by cutting off laser fuses or electric fuses provided inside the chips every chip.  
         [0012]     For instance, only a first fuse is cut off when fabricated at a position A on a wafer, and first and second fuses are cut off when fabricated at a position C. This fuse cutting-off process step is normally executed as a process step accompanying the electrical function tests at the previously-mentioned process step (2). A problem arises in that since the fuse cutting-off process step needs to cut off the fuses different every chip, their cut-off must be carried out in order one chip by one chip and hence a long period of time is required.  
         [0013]     A patent document 1 (Japanese Unexamined Patent Publication No. Hei 5 (1993)-175093) discloses a method of specifying the positions of chips in a wafer without using fuses. Here, underlaying marks for wafer-in chip position indication patterns are formed in parts of device areas of the respective chips by exposure at exposure processing in a wafer-in chip final wiring process. Thereafter, shots different in position with respect to the underlaying marks are formed by exposure and the positions of the chips in the wafer are specified by combinations of the underlaying marks and the shots.  
         [0014]     In the method shown in the above patent document 1, however, there is a need to execute dedicated process steps in addition to the need for dedicated patterns because the transfer positions of the shots exposed onto the underlaying marks are changed in order. As a result, there is a fear that complexity of a manufacturing process and an increase in manufacturing cost are encountered.  
       SUMMARY OF THE INVENTION  
       [0015]     The present invention has been made in view of the foregoing situation. It is therefore an object of the present invention to provide a method capable of specifying the positions of chips in a wafer while keeping an increase in manufacturing cost at a minimum by a simple method.  
         [0016]     According to a first aspect of the present invention, for attaining the above object, there is provided a chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying the positions thereof, comprising the steps of forming marks different every chip in a transfer mask (hereinafter referred to as “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings, preparing the mark forming mask in plural form, and specifying the positions of the chips on the wafer according to combinations of the plural marks transferred onto the wafer by a plurality of the mark forming masks.  
         [0017]     According to a second aspect of the present invention, for attaining the above object, there is provided a chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying the positions thereof, comprising the steps of forming marks different every chip in a transfer mask (hereinafter referred to as “a mark forming mask”) used to form a plurality of contact holes in an insulating layer, in addition to the formation of functional patterns (contact holes or the like), preparing the mark forming mask in plural form, and specifying the positions of the chips on the wafer by combinations of the plural marks transferred onto the wafer by a plurality of the mark forming masks. In the first aspect, the ID marks are formed in the corresponding wiring layer, whereas in the second aspect, the ID marks are formed in mask patterns for an insulating film.  
         [0018]     Preferably, the mark forming masks respectively have configurations in which a plurality of chip areas are arranged in matrix form, and linear marks are formed in the respective chip areas one by one. Among the mark forming masks, the linear marks extend in the direction to intersect one another at right angles and intersect when transferred onto the wafer, and the intersecting positions thereof are different depending on the chip forming positions on the wafer. The position of each chip on the wafer is specified based on the corresponding intersecting position.  
         [0019]     According to a third aspect of the present invention, there is provided a chip forming position specifying method for applying chip IDs indicative of positions on a wafer, where semiconductor chips having a plurality of wiring layers are formed and thereby specifying the positions thereof, comprising the steps of forming marks different every chip in a transfer mask (hereinafter referred to as “first mark forming mask”) used to form a first wiring layer of the plurality of wiring layers, in addition to normal functional wirings, forming marks different every chip in a transfer mask (hereinafter referred to as “second mark forming mask”) used to form a second wiring layer of the plurality of wiring layers, formed in a layer above the first wiring layer, in addition to normal functional wirings, constructing each of the first and second mark forming masks in such a manner that a plurality of chip areas are arranged in matrix form and forming linear marks in the respective chip areas one by one, extending the linear marks in the direction to intersect one another at right angles and intersecting the linear marks when transferred onto the wafer, between the first and second mark forming masks, and allowing the intersecting positions to differ depending on the chip forming positions on the wafer, bringing the intersecting linear marks into conduction at the intersecting positions, and specifying the positions of the chips on the wafer based on conducting states of the linear marks between the first and second mark forming masks.  
         [0020]     Here, other wiring layer having through wirings extended in a vertical direction at positions along the linear marks formed in the first and second mark forming masks is formed between the wiring layers formed using the first and second mark forming masks. The mutual marks are brought into conduction by the through wirings at the intersecting positions of the linear marks formed in the first and second mark forming masks. Currents flowing through the linear marks formed in the first mark forming mask, the through wirings and the linear marks formed in the second mark forming mask or voltages applied thereto are measured, thereby making it possible to specify the forming positions of the chips on the wafer.  
         [0021]     In the present invention as described above, chip ID marks can be transferred using a normal device forming mask. There is no need to prepare a special mask for chip IDs or add a special process step. As a result, an increase in manufacturing cost with the fabrication of the chip IDs can be kept to the minimum.  
         [0022]     Further, according to a method of specifying the position on a wafer, of each completed semiconductor chip, based on electrical conducting states of marks formed in one wiring layer and marks formed in other wiring layer, it is possible to automatically detect its position without depending on a visual examination using an electron microscope or the like and thereby perform a rationalization of a function test on each semiconductor chip. Furthermore, there is a merit that chip IDs can be confirmed without taking the semiconductor chip from the corresponding mold package. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:  
         [0024]      FIG. 1  is a schematic plan view showing a structure of a wafer applicable to the present invention;  
         [0025]      FIG. 2  is a plan view illustrating mask patterns applicable to a method according to a first embodiment of the present invention;  
         [0026]      FIG. 3  is an explanatory view showing a position process employed in the method according to the first embodiment;  
         [0027]      FIG. 4  is an explanatory view depicting a position process employed in the method according to the first embodiment;  
         [0028]      FIG. 5  is a plan view showing mask patterns applicable to a method according to a second embodiment of the present invention;  
         [0029]      FIG. 6  is a plan view illustrating mask patterns applicable to a method according to a third embodiment of the present invention;  
         [0030]      FIG. 7 (A) is a plan view showing a mask pattern applicable to the method according to the third embodiment;  
         [0031]      FIG. 7 (B) is an enlarged explanatory view showing part of a pattern formed by the method according to the third embodiment;  
         [0032]      FIG. 8  is a circuit diagram illustrating a circuit configuration applicable to the method according to the third embodiment; and  
         [0033]      FIG. 9  is a plan view depicting insulating film mask patterns employed in another form of the method according to the first embodiment. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0034]     The present invention will hereinafter be described in detail by preferred embodiments.  FIG. 1  is a schematic plan view showing a structure of a wafer applicable to the present invention. A large number of semiconductor chips  10  identical to one another in structure are formed on the wafer W. Each of the semiconductor chips  10  can be brought into a structure having a plurality of laminated wiring layers.  
       First Preferred Embodiment  
       [0035]      FIG. 2  is a plan view showing mask patterns applicable to a method according to a first embodiment of the present invention. In a semiconductor device manufacturing method according to the present embodiment, circuit patterns are transferred onto the entire surface of the wafer W using a mask  110  having a configuration shown in  FIG. 2 (A) upon a photolithography process for one wiring layer. In the present example, nine shots are made per wafer using a mask (reticle) which enables transfer corresponding to 4×4=16 chips per shot.  
         [0036]     The mask  110  comprises  16  chip areas each having the same functional wiring (device forming wiring), which are disposed in matrix form. The respective chip areas are respectively formed with marks different from one another. Although the upper-case alphabetic characters A-P are adopted as the marks in the present embodiment, characters or symbols other than the alphabet can also be used. If such a position and size as not to influence the function wiring are taken as the position and size of each mark, then each of the marks may not be placed at the end of the chip area. In  FIG. 2 (A), wirings (functional wirings) related to the functions of the semiconductor chips are not shown in the figures for convenience.  
         [0037]     A mask pattern  120  shown in  FIG. 2 (B) is used upon forming a wiring layer different from one for the mask pattern  110  shown in  FIG. 2 (A). For example, a wiring layer using the mask pattern  120  can be formed in a layer above a wiring layer using the mask pattern  110  through an insulating layer interposed therebetween. In a manner similar to the mask pattern  110 , circuit patterns are transferred onto the whole surface of the wafer by a lithography process.  
         [0038]     In the present example, sixteen shots are made per wafer using a mask that enables transfer corresponding to 3×3=9 chips per shot. The mask  120  comprises nine chip areas each having the same functional wiring, which are disposed in matrix form. The respective chip areas are respectively formed with marks different from one another. Although the lower-case alphabetic characters a-i are adopted as the marks in the present embodiment, characters or symbols other than the alphabet can also be used. If such a position and size as not to influence the function wiring are taken as the position and size of each mark, then each of the marks may not be placed at the end of the chip area. Even in  FIG. 2 (B), wirings (functional wirings) related to the functions of the semiconductor chips are not shown in the figures for convenience.  
         [0039]      FIG. 3  shows, as a first wiring layer pattern  114 , the manner in which marks are actually transferred onto a wafer W using the mask pattern  110 .  FIG. 4  shows a second wiring layer pattern  118  formed by transferring marks onto the first wiring layer pattern  114  using the mask pattern  120 . In the manufacturing method of the present embodiment, it is possible to recognize, by confirmation of the mark formed in each chip, at which position on the wafer W each individual chip is fabricated. It is understood in this example that, for instance, when the mark called “G” is confirmed at the first wiring layer pattern  114  and the mark called “g” is further configured at the second wiring layer pattern  118 , the corresponding semiconductor chip is a chip formed in the center of the wafer W.  
         [0040]     In the present embodiment, each mask capable of exposing 16 chips=4 columns deep×4 rows wide at a time is used in the first wiring layer, and each mask capable of exposing 9 chips=3 columns deep×3 rows wide at a time is used in the second wiring layer. It is therefore possible to distinguish up to 144 chips=12 columns deep×12 rows wide at the maximum from one another. The figure of “12” at this calculation is called the least common denominator between the values of 4 columns (rows) deep (or wide) in the mask  110  having the first wiring layer and the values of 3 columns (rows) deep (or wide) in the mask  120  having the second wiring layer. Assuming that a mask capable of exposing Y 1 X 1  chips=Y 1  columns deep×X 1  rows wide at a time is used in the first wiring layer, and a mask capable of exposing Y 2 X 2  chips=Y 2  columns deep×X 2  rows wide at a time is used in the second wiring layer, it is possible to distinguish up to (the least common denominator of Y 1  and Y 2 )×(the least common denominator of X 1  and X 2 ) chips at the maximum from one another.  
         [0041]     Further, if a mask capable of exposing Y 3 X 3  chips=Y 3  columns deep×X 3  rows wide at a time is used in a third wiring layer, then the distinguishable number of chips can be increased up to (the least common denominator of Y 1 , Y 2  and Y 3 )×(the least common denominator of X 1 , X 2  and X 3 ) chips at the maximum. In the method according to the present embodiment, each of the mark  110  of the first wiring layer and the mark  120  of the second wiring layer both transferred within a wafer process or a pre-process acts as a chip ID. That is, it is possible to specify the position on the wafer, of each manufactured semiconductor chip by a combination of the mark formed in the mask pattern  110  and the mark formed in the mask pattern  120 . Therefore, there is no need to provide a time-consuming fuse cutting-off process within a post-process or a package process as in the prior art.  
         [0042]     Incidentally, although the two types ( 110  and  120 ) have been used as the mask patterns for forming the ID marks in the first embodiment referred to above, three or more types (three or more layers) can also be used. Although not restricted in particular, the positions of the layers for forming the mask  110  and  120  may preferably be formed in the layers located on the upper side (including the top layer) to confirm the same visually (by an electron microscope) later.  
         [0043]      FIG. 9  is a plan view showing mask patterns for insulting films, which are employed in another form (modification) of the method according to the first embodiment. While the ID marks are formed in the wiring layer in the first embodiment, ID marks can be formed in such mask patterns as shown in  FIG. 9 . As the used ID marks, such ones as shown in  FIGS. 2 through 4  can be adopted. In the example shown in  FIG. 9 , a plurality of contact holes are formed or defined in a single insulating layer using two sheets of masks  150 A and  150 B. A pattern  152   b  of the mask  150 A and a pattern  154   a  of the mask  150 B are associated with their corresponding contact hole forming positions. A pattern  152   a  of the mask  150 A and a pattern  154   b  of the mask  150 B do not contribute to the formation of the contact holes. In the example shown in  FIG. 9 , the mask  150 A is used at the first exposure and the mask  150 B is used at the subsequent second exposure. That is, one-half the contact holes are formed (exposed) using the mask  150 A and the remaining one-half the contact holes are formed (exposed) using the mask  150 B.  
         [0044]     Even in the case in which the ID marks are formed in the wiring layer, a plurality of sheets of masks are provided and the ID marks can also be formed in a single wiring layer. In this case, the ID marks can be formed by a procedure similar to one for the insulating layer shown in  FIG. 9 .  
         [0045]     Incidentally, since the formation of the ID marks in the wiring layer is superior in visibility to the formation of the ID marks in the insulating layer, it is preferable to form them in the wiring layer practically.  
         [0046]     In an actual wafer process, functional wirings (devices) and alphabetic marks are formed in respective chip areas constituting a mask pattern  10  in advance. For example, pattern drawing is effected on a transparent glass substrate using a metal such as chromium. A mask pattern  120  is formed with functional wirings and alphabetic marks (lower-case characters) by a similar method. Such patterns as shown in  FIG. 3  are first transferred onto the wafer W using the mask pattern  110  by means of step-and-repeat executed by a scale-down projection exposure device (stepper). Thereafter, such patterns as shown in  FIG. 4  are transferred onto the wafer W using the mask pattern  120  by a similar method.  
         [0047]     Thereafter, the individual semiconductor chips are brought to completion through the known processes. Next, the fractionalized semiconductor chips are encapsulated or sealed in plastic or ceramic packages. They are completed as integrated circuits via a final test. A quality test is effected on the completed semiconductor integrated circuits. The failure- or defect-detected semiconductor integrated circuits are visually observed by, for example, an optical microscope, so that it is discriminated at which positions on the wafer they are formed. Incidentally, when each chip ID is actually confirmed, the corresponding semiconductor chip is taken out from the mold package to confirm it. Alternatively, it is confirmed before each semiconductor chip is encapsulated in the mold package.  
       Second Preferred Embodiment  
       [0048]      FIG. 5  is a plan view showing mask patterns ( 210  and  220 ) applicable to a method according to a second embodiment of the present invention. Basically, the difference between the present embodiment and the first embodiment resides in the shape of a mark constituting each chip ID. According to the mask patterns  210  and  220  employed in the present embodiment, there is a merit that their marks are superior in visibility to the alphabetic marks (character marks) shown in the first embodiment. In the second embodiment, the mask pattern  210  having line-line marks extending in the vertical direction, and the mask pattern  220  having line-like marks extending in the horizontal direction are used.  
         [0049]     The line-shaped marks different in the number of lines are respectively formed in chip areas of the mask pattern  120 . Similarly, the line-like marks different in the number of lines are respectively formed in chip areas of the mask pattern  220 . The position on a wafer W, of each semiconductor chip is specified by a combination of the two mask patterns  210  and  220 .  FIG. 5 (C) shows the manner in which they are combined together (superimposed on each other).  
         [0050]     In a method of manufacturing a semiconductor device, according to the present embodiment, circuit patterns are transferred onto the entire surface of the wafer W using such a mask  210  as shown in  FIG. 5 (A) upon a photolithography process for one wiring layer. In the present example, nine shots are done per wafer using a mask (reticle) which enables transfer corresponding to 4×4=16 chips per shot. The mask  210  comprises 16 chip areas each having the same functional wiring (device), which are disposed in matrix form. If such a position and shape as not to influence the function wiring (device) are taken, then the position, width, length and the like of each mark may not be placed at the end of each chip area. In  FIG. 5 (A), wirings (functional wirings) related to the functions of the semiconductor chips are not shown for convenience.  
         [0051]     The mask pattern  220  shown in  FIG. 5 (B) is used upon forming a wiring layer different from that for the mask pattern  210  shown in  FIG. 5 (A). For example, a wiring layer using the mask pattern  220  can be formed in a layer above a wiring layer using the mask pattern  210  through an insulating layer interposed therebetween. In a manner similar to the mask pattern  210 , circuit patterns are transferred onto the whole surface of the wafer by a lithography process. In the present example, sixteen shots are done per wafer using a mask that enables transfer corresponding to 3×3=9 chips per shot. The mask  220  comprises nine chip areas each having the same functional wiring, which are disposed in matrix form. In a manner similar to the mask pattern  210 , the position, width, length and the like of each mark may not be placed at the end of each chip area if such a position and shape as not to influence the functional wiring (device) are taken. Even in  FIG. 5 (B), wirings (functional wirings) related to the functions of the semiconductor chips are not illustrated for convenience.  
         [0052]     According to the present embodiment, it is easy to recognize each mark even where the two marks overlap each other, as compared with the first embodiment. Therefore, the mask patterns  210  and  220  can be designed in such a manner that the two marks overlap each other. It is further possible to reduce space for forming each chip ID mark to the minimum.  
       Third Preferred Embodiment  
       [0053]      FIG. 6  is a plan view showing mask patterns  310  and  320  applicable to a method according to a third embodiment of the present invention. The present embodiment is different from the first and second embodiments in terms of the shape of each mark constituting a chip ID. In the present embodiment, although explained in detail later, chip ID marks  310   a  and  320   a  are electrically detected without depending on a visual inspection. In the present embodiment, the mask pattern  310  having respective one line-line marks extending in the vertical direction every chip area, and the mask pattern  320  having respective one line-like marks extending in the horizontal direction every chip area are used. The position on a wafer W, of each semiconductor chip is specified by a combination of the two mask patterns  310  and  320 .  FIG. 6 (C) shows the manner in which they are combined together (superimposed on each other).  
         [0054]     In a method of manufacturing a semiconductor device, according to the present embodiment, circuit patterns are transferred onto the entire surface of the wafer W using such a mask  310  as shown in  FIG. 6 (A) upon a photolithography process for one wiring layer. In the present example, nine shots are made per wafer using a mask (reticle) which enables transfer corresponding to 4×4=16 chips per shot. The mask  310  comprises 16 chip areas each having the same functional wiring (device), which are disposed in matrix form. If such a position and shape as not to influence the function wiring (device) are taken, then the position, width, length and the like of each mark may not be placed at the end of each chip area. In  FIG. 6 (A), wirings (functional wirings) related to the functions of the semiconductor chips are not illustrated for convenience.  
         [0055]     The mask pattern  320  shown in  FIG. 6 (B) is used upon forming a wiring layer different from that for the mask pattern  310  shown in  FIG. 6 (A). For example, a wiring layer using the mask pattern  320  can be formed in a layer above a wiring layer using the mask pattern  310  through an insulating layer interposed therebetween. In a manner similar to the mask pattern  310 , circuit patterns are transferred onto the whole surface of the wafer by a lithography process. In the present example, sixteen shots are made per wafer using a mask that enables transfer corresponding to 3×3=9 chips per shot. The mask  320  comprises nine chip areas each having the same functional wiring, which are disposed in matrix form. In a manner similar to the mask pattern  310 , the position, width, length and the like of each mark may not be placed at the end of each chip area if such a position and shape as not to influence the functional wiring (device) are taken. Even in  FIG. 6 (B), wirings (functional wirings) related to the functions of the semiconductor chips are not shown for convenience.  
         [0056]      FIG. 7 (A) is a plan view showing a mask pattern  330  applicable to the method according to the third embodiment.  FIG. 7 (B) is an enlarged explanatory view showing part of a pattern formed by the method according to the third embodiment. The mask pattern  330  is used upon forming a wiring layer between the wiring layer using the mask pattern  310  shown in  FIG. 6 (A) and the wiring layer using the mask pattern  320  shown in  FIG. 6 (B). The mask pattern  330  has dot patterns  332  laid out and formed in matrix form at intervals each corresponding to the pitch (the amount of deviation between chip areas) between the line-like marks formed in the mask patterns  310  and  320 . The dot patterns  332  are respectively formed at positions each corresponding to an intersection point of the line-like marks  310   a  and  320   a.    
         [0057]     The dot patterns  332  may be formed at the positions corresponding to the line-line marks  310   a  and  320   a . Thus, there is no need to form the dot patterns over the entire chip area. The mask pattern  330  can be formed in the same mask as one for functional wirings if such a position and shape as not to influence the functional wirings (devices) are taken. Alternatively, a dedicated mask can also be used. The mask pattern  330  can be constituted of an arrangement of 4×4 set in a manner similar to the mask pattern  310 , or an arrangement of 3×3 set in a manner similar to the mask pattern  320 .  
         [0058]     As shown in  FIG. 7 (B), each of columnar through wirings  332   a  is formed by the dot pattern  332  to enable an electrical connection between the line-like marks  310   a  and  320   a.    
         [0059]      FIG. 8  is a circuit diagram showing a configuration of a chip ID detecting circuit applicable to the method according to the third embodiment. Output terminals D 1  through D 16  of a chip ID decoder  334  are connected to their corresponding wirings formed by the line-like marks  310   a  formed in the mask pattern  310 . Input terminals A 1  through A 9  of a chip ID detecting amplifier  336  are connected to their corresponding wirings formed by the line-like marks  320   a  formed in the mask pattern  320 . The chip ID detecting wirings formed by the mask pattern  310  are different from one another in position where they are fabricated depending on which chips of positions on the mask correspond as shown in  FIG. 6 (A). As a result, the connected output terminals D 1  through D 16  of chip ID decoder  334  are manufactured so as to differ depending on which chips of positions on the mask. In the case of, for example, the chip at the upper left corner of the mask pattern  310  shown in  FIG. 6 (A), the connected output terminal of chip ID detecting decoder  334  becomes D 1 . In the case of the chip adjoining to one right side of the uppermost left of the mask pattern  310 , the connected output terminal of chip ID detecting decoder  334  results in D 2 .  
         [0060]     The chip ID detecting wirings formed by the mask pattern  320  are different from one another in position where they are fabricated depending on which chips of positions on the mask correspond as shown in  FIG. 6 (B). As a result, the connected input terminals A 1  through A 9  of chip ID detecting amplifier  336  are manufactured so as to differ depending on which chips of positions on the mask. In the case of, for example, the chip at the upper left corner of the mask pattern  320  shown in  FIG. 6 (B), the connected input terminal of chip ID detecting amplifier  336  becomes A 1 . In the case of the chip adjoining to one right side of the uppermost left of the mask pattern  320 , the connected input terminal of chip ID detecting amplifier  336  results in A 2 .  
         [0061]     Operations of the circuit shown in  FIG. 8  will next be explained. Of the plural outputs of the chip ID decoder  334 , D 1  is first operated. For example, the voltage at the output D 1  is raised to 3V. Next, the chip ID detecting amplifier  336  is operated to confirm from which amplifier at the terminals A 1  through A 9  a signal is outputted. For instance, confirmation is made whether a voltage of 3V has been detected. Next, after completion of confirmation at the wiring D 1  connected to the decoder  334 , the output of the decoder  334  is changed from D 2  to D 16  subsequently in like manner and thereafter the above operations are repeated.  
         [0062]     For example, the chip ID detecting wirings (D 1  through D 16  and A 1  through A 9 ) respectively indicate the following behaviors at an integrated circuit having such a chip ID that the output terminal D 8  of the chip ID decoder  334  and the input terminal A 3  of the chip ID detecting amplifier  336  are connected to each other.  
         [0063]     1) When any of the outputs D 1  through D 7  and D 9  through D 16  of the decoder  334  in the chip ID detecting circuit is operated (increased in voltage), no signal is outputted from any amplifier from A 1  through A 9  of the chip ID detecting amplifier  336 .  
         [0064]     2) When the output D 8  of the decoder  334  in the chip ID detecting circuit is operated, a signal is outputted only from A 3  of the chip ID detecting amplifier  336 .  
         [0065]     Thus, if confirmation is made as to from which amplifier (A 1  through A 9 ) the signal is outputted, when any decoder output (D 1  through D 16 ) is operated, it is then possible to recognize which chip ID is contained in a target integrated circuit.  
         [0066]     In general, the semiconductor integrated circuit is placed in a state in which each semiconductor chip is encapsulated in a mold package. Thus, in order to confirm each chip ID in the first and second embodiments, the semiconductor chip is taken out from within the mold package and should be then observed. On the other hand, if the present embodiment is used, then the corresponding chip ID can be electrically confirmed without the need to take the semiconductor chip out of the mold package.  
         [0067]     While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention. The scope of the invention is to be determined solely by the following claims.