Abstract:
A programmable on-time period of a DC to DC buck converting controller is adjusted according to a level of a preset output voltage or a reference signal. Therefore, the DC to DC buck converting controller of the present invention is suitable for any applications with different requests of output voltages or different operating mode.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation-in-part application of and claims the priority benefit of U.S. application Ser. No. 13/284,974, filed on Oct. 30, 2011, now pending, which claims the priority benefit of China application serial no. 201110100828.0, filed on Apr. 21, 2011. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of specification. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a DC to DC buck converting controller, and more particularly a DC to DC buck converting controller with programmable output voltage. 
     2. Description of Related Art 
       FIG. 1  is a schematic diagram of a conventional DC to DC buck converting circuit. The DC to DC buck converting circuit comprises a controller  10 , two switches M 1  and M 2 , an inductance L, a capacitance C, a bootstrap circuit BS and a voltage divider VD. The voltage divider VD detects an output voltage of the buck converting circuit and accordingly generates a feedback signal FB. The controller  10  turns the switches M 1  and M 2  on/off according to the feedback signal FB, so as to make the DC to DC buck converting circuit to convert an input signal Vin into an output voltage Vout which is stabilized at a preset output voltage, as well as provide an output current Iload. 
     The controller  10  is packaged in a package, and comprises a comparator  12 , a on-time period circuit  14 , and a logic circuit, which has a logic control circuit  16  and two gate driving units  18 ,  20 . The comparator  12  generates a feedback control signal according to the feedback signal FB and a reference voltage Vref, which is generated inside the controller  10 . An on-time period of the on-time period circuit  14  is determined by the input voltage Vin and the output voltage Vout, and the on-time period circuit  14  generates a constant on-time signal according to the feedback control signal. The logic control circuit  16  determines conduction timing and cut-off timing of the switches M 1  and M 2 , and generates two control signals Sl and Su respectively via the gate driving units  18  and  20  to turn on and off the switches M 1  and M 2 . The switch M 2  is a N-type MOSFET. For avoiding that the gate driving unit  20  in the controller  10  cannot generate a signal which is high enough to turn on the switch M 2 . The bootstrap circuit BS is used to supply a sufficiently high voltage to the gate driving unit  20 . 
     The constant on-time period circuit  14  adjusts the constant on-time period according to the input voltage Vin and the output voltage Vout to make the DC to DC buck converting circuit operate in a quasi-constant frequency. Therefore, an electromagnetic interference (EMI) generated by the switches M 1  and M 2  can be easily filtered out, regardless of the levels of the input voltage Vin and the output voltage Vout in different applications. 
     Compared with a conventional converting controller with error amplifier structure, the DC to DC buck converting controller with on-time structure has a better transient response.  FIG. 2  shows waveform diagrams when a loading driven by the conventional converting circuit with on-time structure is changed. At a tome point t 1 , the output current Iload is raised while the loading increases. During the interval from the time point t 1  to a time point t 2 , the output voltage Vout is temporarily decreased due to that an increased output power provided by the converting circuit is not enough. After the time point t 2 , the output voltage Vout starts to be elevated and then reaches the original voltage level at a time point t 3 . The constant on-time period circuit  14  determines the on-time period in response to the input voltage Vin and the output voltage Vout. However, the output voltage Vout is lower than the original voltage level during an interval from the time point t 1  to the time point t 3 , and so the on-time periods of cycles within the interval are shorter, which is a great disadvantage for transient response. 
     SUMMARY OF THE INVENTION 
     The invention adjusts the programmable on-time period of a DC to DC buck converting controller according to a reference signal, so as to be suitable for any applications with different requests of output voltages or different operating mode, and enhance the transient response. Furthermore, the converting controller can omits a pin for obtaining the information of output voltage to lower the cost of the converting controller and a PCB board therefore. 
     To accomplish the aforementioned and other objects, an exemplary embodiment of the invention provides a DC to DC buck converting controller, which is packaged in a package and adapted to control a DC to DC buck converting circuit which converts an input voltage into an output voltage. The DC to DC buck converting controller comprises a feedback circuit and a driving circuit. The feedback circuit receives a reference signal through a pin of the package and generates a feedback control signal according to a reference signal representative of a reference voltage and a feedback signal representative of the output voltage. The driving circuit generates at least one control signal to control the DC to DC buck converting circuit according to the feedback control signal. The driving circuit comprises an on-time period circuit. The on-time period circuit sets an on-time period of the DC to DC buck converting circuit according to the level of the reference voltage. 
     It needs to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. In order to make the features and the advantages of the invention comprehensible, exemplary embodiments accompanied with figures are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will now be specified with reference to its preferred embodiment illustrated in the drawings, in which: 
         FIG. 1  is a schematic diagram of a conventional DC to DC buck converting circuit. 
         FIG. 2  shows waveform diagrams when a loading driven by the conventional converting circuit with on-time structure is changed. 
         FIG. 3  is a schematic diagram of a DC to DC buck converting circuit according to a first embodiment of the invention. 
         FIG. 4  is a schematic diagram of an on-time period circuit according to an embodiment of the invention. 
         FIG. 5  shows waveform diagrams when a loading, driven by the DC to DC buck converting circuit shown in  FIG. 3 , is changed. 
         FIG. 6  is a schematic diagram of a DC to DC buck converting circuit according to a second embodiment of the invention. 
         FIG. 7  is a schematic diagram of an anti-noise circuit according to an embodiment of the invention. 
         FIGS. 8(   a ) and ( b ) show waveform diagrams for difference reference voltages. 
         FIG. 9  shows waveform diagrams of control signals generated by the conventional converting controller and the converting controller of the invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawings. 
       FIG. 3  is a schematic diagram of a DC to DC buck converting circuit according to a first embodiment of the invention. The DC to DC buck converting circuit comprises a controller  100 , two switches M 1  and M 2 , an inductance L, a capacitance C, a bootstrap circuit BS and a voltage divider VD. The voltage divider VD detects an output voltage Vout of the DC to DC buck converting circuit and accordingly generates a feedback signal FB. The controller  100  turns the switches M 1  and M 2  on/off according to the feedback signal FB, so as to make the DC to DC buck converting circuit convert an input voltage Vin into an output voltage Vout which is stabilized at a preset output voltage and provide an output current Iload to a load (not shown). 
     The controller  100  comprises a feedback circuit  112 , a driving circuit which comprises an on-time period circuit  114 , a logic control circuit  116  and two gate driving units  118 ,  120 , which is packaged in a package with a plurality of pins. The feedback circuit  112  comprises a comparator. An inverting input terminal of the comparator receives the feedback signal FB and a non-inverting input terminal thereof receives a reference voltage Vr and accordingly outputs a feedback control signal Sfb. The on-time period circuit  114  receives the feedback control signal Sfb and the reference voltage Vr and accordingly generates an on-time signal Sto. Therefore, the on-time period circuit  114  does not need the information of the output voltage Vout and can omit one pin for coupling to the output voltage Vout, which is used to get the information of the output voltage Vout in the conventional arts. A pulse width (time period) of the on-time signal Sto is determined by a voltage level of the reference voltage Vr. A starting timing of the on-time signal Sto, i.e., rising/falling edge, is determined according to the feedback control signal Sfb. The logic control circuit  116  is coupled with a connection node of the two switches M 1  and M 2  to detect a current of the inductance L and determine turned-on timings and turned-off timings of the two switches M 1  and M 2  according to the feedback control signal Sfb and the current of the inductance L. The logic control circuit  116  generates two control signals Slg and Sug respectively via the gate driving units  18  and  20  to turn the two switches M 1  and M 2  on/off. In the present embodiment, a duty cycle of the DC to DC buck converting circuit, i.e., a time ratio of a period time to transmit the power from the input voltage Vin into the DC to DC buck converting circuit via the switch M 1  and a cycle time thereof, is determined by turned-on period of the switch M 1 . That is, when a beginning of each cycle (when the level of the feedback signal FB is lower than the level of the reference voltage Vr), the feedback circuit  112  generates a feedback control signal Sfb to make the on-time period circuit  114  to generate the on-time signal Sto with a pulse width (time period). The logic control circuit  116  turns on the switch M 1  according to the on-time signal Sto. After the pulse width (time period), the logic control circuit  116  turns the switch M 1  off and turns the switch M 2  on to make the current of the inductance L freewheel through the switch M 2 . When the current of the inductance L is decreased to zero, the switch M 2  is turned off. 
     The reference voltage Vr may be an external reference signal, input to the controller  100  through a pin of the package. The reference signal may be an analog signal having a reference voltage, or a digital signal indicative of the reference voltage. Therefore, a level of the reference voltage Vr is determined by an external circuit or set by users according to a preset output voltage. In the present embodiment, the controller  100  further comprises a reference voltage generating circuit  115 . The reference voltage generating circuit  115  generates a reference base voltage Vr 0 . The user makes the reference base voltage Vr 0  divided into a demand reference voltage Vr by a voltage divider and transmits the reference voltage Vr into the feedback circuit  112  and the on-time period circuit  114  through the pin. The voltage divider comprises the resistances RV 1 , RV 2  and a voltage division ratio thereof is set by the input voltage Vin and the preset output voltage. In addition, the voltage division ratio of the voltage divider VD may affect the ratio of the feedback signal FB and the output voltage Vout. Therefore, the ratio of the resistances RV 1 , RV 2  is set according to the voltage division ratio of the voltage divider VD. 
       FIG. 4  is a schematic diagram of an on-time period circuit according to an embodiment of the invention. The on-time period circuit  114  comprises a current source I, a period capacitance Cton and a comparator  1141 . The current of the current source I is set by a current minor MI and an on-time period resistance Rton. The on-time period resistance Rton is coupled with the input voltage Vin and so a current flowing through the on-time period resistance depends on the input voltage Vin. The current flowing through the on-time period resistance is mirrored to the current source I by the current minor MI. On the beginning of each cycle, the period capacitance Cton is charging from zero by the current source I. The comparator  1141  compares the voltage of the period capacitance Cton with one of the original voltage Vset and the reference voltage Vr to generate the on-time signal Sto, and the original voltage Vset is higher than the reference voltage Vr. On the beginning of enabling the circuit, the comparator  1141  compares the voltage of the period capacitance Cton with the original voltage Vset to make the on-time period longer and so the output voltage Vout could be increased faster. Just before or when the output voltage Vout reaches the preset voltage, the comparator  1141  compares the voltage of the period capacitance Cton with the reference voltage Vr to make the output voltage Vout to be stabilized on the preset output voltage. The on-time period circuit  114  further comprises a SR flip-flop  1142  and an inverter  1143 . A set terminal S of the SR flip-flop  1142  is coupled with the output terminal of the comparator  1141  through the inverter  1143 , a reset terminal R thereof is coupled with the feedback circuit  112  and an output terminal is coupled with the discharging unit SWd. The discharging unit SWd is coupled with two ends of the period capacitance Cton to discharge the period capacitance Cton according to the controlling of the SR flip-flop  1142 . When the voltage of the period capacitance Cton is higher than the reference voltage Vr, the on-time signal Sto is changed into low level to trigger the SR flip-flop  1142  through the inverter  1143 . Then, the discharging unit SWd discharges the period capacitance Cton. When the output voltage Vout is lower than the preset voltage, the feedback control signal Sfb is at high level and input to the reset terminal R of the SR flip-flop  1142  to make the SR flip-flop  1142  reset to stop the discharging unit SWD discharging. Therefore, on the beginning of each cycle, the output voltage Vout is lower than the preset output voltage and the period capacitance Cton is charged by the current sources I. When the voltage of period capacitance C is higher than the reference voltage Vr, the period capacitance Cton is discharged to zero voltage to wait for the next cycle. 
       FIG. 5  shows waveform diagrams when a loading, driven by the DC to DC buck converting circuit shown in  FIG. 3 , is changed. At a tome point t 4 , the output current Iload is raised while the loading of the load increases. During the interval from the time point t 4  to a time point t 5 , the output voltage Vout is temporarily decreased due to that an increased output power provided by the converting circuit is not enough. After the time point t 5 , the output voltage Vout starts to be elevated and then reaches the original voltage level at a time point t 6 . The on-time period circuit  114  determines the on-time period in response to the input voltage Vin and the reference voltage Vr regardless of the output voltage Vout. Due to that the reference voltage Vr is fixed regardless of the variation of the loading, the pulse width of the control signal Sug is fixed while the duty cycle thereof is increased. Therefore, the interval from the time point t 4  to the time point t 6  is shorter than that from time point tl to the time point t 3  shown in  FIG. 2 , i.e.: the controller  100  has a better transient response than that of the conventional constant on-time converting controller. 
       FIG. 6  is a schematic diagram of a DC to DC buck converting circuit according to a second embodiment of the invention. Compared with the embodiment shown in  FIG. 3 , the controller  200  omits the reference voltage generating circuit  115  and the voltage divider, and adds anti-noise circuit  125 . The feedback circuit  112  directly receives the reference voltage Vr through a pin of the package and compares the reference voltage Vr with the feedback signal FB to generate the feedback control signal Sfb. If a digital reference signal indicative of the reference voltage is input through the pin, the controller  200  may adds a digital to analog converter to convert the digital signal into the reference voltage Vr. The anti-noise circuit  125  is coupled between the feedback circuit  112  and the on-time period circuit  114  for avoiding noise interferences in generation of the feedback control signal Sfb. The anti-noise circuit  125  generates a trigger signal Sd to the on-time period circuit  114  when the feedback control signal Sfb is generated for an anti-noise time. The anti-noise circuit  125  also receives the reference voltage Vr and modulates the anti-noise time in response to the reference voltage.  FIG. 7  is a schematic diagram of an anti-noise circuit according to an embodiment of the invention. The anti-noise circuit comprises a bias current source Ib, a current mirror  1252 , a delay capacitance  1254 , a switch  1256 , and a comparator  1258 . A control terminal of the switch  1258  is coupled to an output end of the feedback circuit  112 , and the switch  1256  is turned on and off according to the feedback control signal Sfb. The current mirror  1252  mirrors a current provided by the bias current source Ib to discharge the capacitance  1254 . When the feedback signal FB is higher than the reference voltage Vr, the feedback control signal Sfb is at a low level. At this time, the switch  1256  is turned on to keep a voltage of the delay capacitance  1254  close to a supply voltage VDD higher than the reference voltage Vr, and so the comparator  1258  stops to generate the trigger signal Sd. When the feedback signal FB is lower than the reference voltage Vr, the feedback control signal Sfb is at a high level. At this time, the switch  1256  is turned off and so the current mirror  1252  starts to discharge the capacitance  1254 . When the voltage of the capacitance  1254  is discharged to be lower than the reference voltage Vr, the comparator  1258  outputs the trigger signal Sd to the reset terminal R of the SR flip-flop  1142 . At this moment, the on-time period circuit  114  starts to generate the on-time signal Sto. An anti-noise time is the time interval from the timing of generating the feedback control signal Sfb to the timing of generating the trigger signal Sd. 
       FIGS. 8(   a ) and ( b ) show waveform diagrams for difference reference voltages. A level of the reference voltage Vr represents the loading of the load as well as the preset output voltage. A reference voltage Vr 1  of  FIG. 8(   a ) is lower than a reference voltage Vr 2  of  FIG. 8(   b ). The anti-noise time is shortened when the reference voltage is increased, and alternatively the anti-noise time is lengthened when the reference voltage is lowered. Therefore, an anti-noise time d 1  of  FIG. 8(   a ) is longer than an anti-noise time d 2  of  FIG. 8(   b ). A ripple of the output voltage is increased with the increasing of the output voltage, and so an angle between the reference voltage Vr 2  and the feedback signal FB 2  is larger than that between the reference voltage Vr 1  and the feedback signal FB 1 . Hence, when the preset output voltage is higher, the ripple of the output voltage is larger and a stability of the converting circuit is better but a transient response is poor. At this time, the anti-noise time of the anti-noise circuit of the invention is shortened to enhance the transient response. On the other hand, when the preset output voltage is lower, the ripple of the output voltage is smaller and the transient response of the converting circuit is better but the stability is poor. At this time, the anti-noise time of the anti-noise circuit of the invention is lengthened to enhance the stability. 
       FIG. 9  shows waveform diagrams of control signals generated by the conventional converting controller and the converting controller of the invention. The on-time period of the control signal Sug is determined according to the reference voltage Vr in the present invention. In contrast, the on-time period of the control signal Su is determined according to the output voltage Vout in the conventional arts. At a time point t 7 , the loading is increased and so the output current Iload and the reference voltage Vr are synchronously increased. The on-time period of the control signal Sug is increased with the increasing of the reference voltage Vr. However, the Vout is increased after, even temporarily reduced. The on-time period of the control signal Su is still retained. Moreover, the anti-noise time of the invention is shortened. The beginning of the control signal Sug is early than that of the control signal Su. Both the longer on-time period and the shorter anti-noise time, the invention significantly improves the transient response while the loading is increasing. 
     At a time point t 8 , the loading is reduced and so the output current Iload and the reference voltage Vr are synchronously decreased. The on-time period of the control signal Sug is reduced with the reducing of the reference voltage Vr. However, the Vout is decreased after, even temporarily increased. The on-time period of the control signal Su is still retained. Moreover, the anti-noise time of the invention is lengthened. The beginning of the control signal Sug is later than that of the control signal Su. Both the shorter on-time period and the longer anti-noise time, the invention simultaneously improves the transient response and the stability while the loading is reducing. 
     All the features disclosed in this specification (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.