Abstract:
A method and circuits for testing an integrated circuit at functional lock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to the field of integrated circuit testing; more specifically, it relates to a circuit and method for testing integrated circuits at functional frequency.  
         [0003]     2. Background of the Invention  
         [0004]     Integrated circuits, especially logic circuits, are often tested using scan chain methodology, wherein test patterns are loaded into a set of scan-in latches, clocked through the combinational logic to be tested and the result pattern captured by scan-out latches for analysis. This testing has been traditionally performed at tester frequencies of about 30 to 100 MHz. However, with the advent of higher functional frequency integrated circuits, for example in about the 1 to 5 GHz range, circuits have been found to pass at tester frequency but fail at functional frequency. Therefore, there is a need for a method and circuit for testing integrated circuits at functional frequency.  
       SUMMARY OF INVENTION  
       [0005]     A first aspect of the present invention is a control circuit, an output of a first latch connected to an input of a second latch, an output of the second latch connected to an input of a third latch, the second latch having a feedback connection to an input of the first latch and the third latch having feedback connections to the first and the second latches; combinational logic coupled to the first, second and third latches, the combinational logic having a test signal input, a test clock input and a functional clock input; the feedback connection of the second latch further coupled through the combinational logic to a first control signal output; and the first latch coupled through the combinational logic to a second control signal output.  
         [0006]     A second aspect of the present invention is a method of generating control signals, comprising: connecting an output of a first latch to an input of a second latch; connecting an output of the second latch to an input of a third latch; connecting the second latch through a feedback connection to an input of the first latch; connecting the third latch through feedback connections to the first and the second latches; coupling combinational logic to the first, second and third latches, the combinational logic having a test signal input, a test clock input and a functional clock input; coupling the feedback connection of the second latch through the combinational logic to a first control signal output; and coupling the first latch through the combinational logic to a second control signal output.  
         [0007]     A third aspect of the present invention is a control circuit, comprising: an output of a first latch connected to an input of a second latch, an output of the second latch connected to an input of a third latch, the second latch having a feedback connection to an input of the first latch and the third latch having feedback connections to the first and the second latches; the combinational logic coupled to the first, second and third latches, the combinational logic having a test signal input, a scan enable input and a functional clock input; and the feedback connection of the second latch further coupled through the combinational logic to a scan control output.  
         [0008]     A fourth aspect of the present invention is a method of generating a control signal, comprising: connecting an output of a first latch to an input of a second latch; connecting an output of the second latch to an input of a third latch; connecting the second latch through a feedback connection to an input of the first latch; connecting the third latch through feedback connections to the first and the second latches; coupling combinational logic to the first, second and third latches, the combinational logic having a test signal input, a scan enable input and a functional clock input; and coupling the feedback connection of the second latch through the combinational logic to a scan control output.  
         [0009]     A fifth aspect of the present invention is an integrated circuit, a test pin, a first test clock pin, a second test clock pin, a third test clock pin a functional clock pin, a scan-in pin, a scan-out pin and an enable pin; a test controller having a test input connected to the test pin, a first test clock input connected to the first test clock pin, a functional clock input connected to the functional clock pin, a first control output and a second control output; a clock splitter having a first clock input connected to the second test clock pin, a second clock input connected to the functional clock pin, a first control input connected to the first control output of the test controller, a second control input connected to the second control output of the controller, an enable input connected to the enable pin, a ZB clock output and a ZC clock output; and an LSSD scan chain comprised of serially connected latches, a first stage of each latch having a first data input, a second data input and a C clock input connected to the ZC clock output of the clock splitter, an A CLK input connected to the third test clock pin, a second stage of each latch having a data output and a B clock input connected to the ZB clock output of the clock splitter, a data output of a previous latch connected to a first input pin of an immediately subsequent latch, a first data input of a first latch of the LSSD scan chain connected to the scan-in pin and a data output pin of a last scan chain latch of the scan chain connected to the scan-out pin.  
         [0010]     A sixth aspect of the present invention is a method of testing an integrated circuit, comprising: providing a test pin, a first test clock pin, a second test clock pin, a third test clock pin, a functional clock pin, a scan-in pin, a scan-out pin and an enable pin; providing a test controller having a test input connected to the test pin, a first test clock input connected to the first test clock pin, a functional clock input connected to the functional clock pin, a first control output and a second control output; providing a clock splitter having a first clock input connected to the second test clock pin, a second clock input connected to the functional clock pin, a first control input connected to the first control output of the test controller, a second control input connected to the second control output of the controller, an enable input connected to the enable pin, a ZB clock output and a ZC clock output; and providing an LSSD scan chain comprised of serially connected latches, a first stage of each latch having a first data input, a second data input and a C clock input connected to the ZC clock output of the clock splitter, an A clock input connected to the third test clock pin, a second stage of each latch having a data output and a B clock input connected to the ZB clock output of the clock splitter, a data output of a previous latch connected to a first input pin of an immediately subsequent latch, a first data input of a first latch of the LSSD scan chain connected to the scan-in pin and a data output pin of a last scan chain latch of the scan chain connected to the scan-out pin.  
         [0011]     A seventh aspect of the present invention is an integrated circuit, comprising: a test pin, a select enable pin, a functional clock pin, a scan-in pin and a scan-out pin; a test controller having a test input connected to the test pin, a functional clock input connected to the functional clock pin, a first control output and a second control output; a scan chain comprised of serially connected latches and corresponding multiplexers, a first stage of each latch having a data input, a clock input connected to a functional clock pin, a first control input connected to the first control output of the test controller, a second stage of each latch having a data output and a second control input connected to the second control output of the tester controller, a data output of a previous latch connected to a first selectable input of a multiplexer corresponding to an immediately subsequent latch, a selected output of the corresponding multiplexer connected to the data input of the immediately subsequent latch, a first selectable data input of a multiplexer of the scan chain connected to the scan-in pin and a data output of a last latch of the scan chain connected to the scan-out pin.  
         [0012]     An eighth aspect of the present invention is a method of testing an integrated circuit, comprising: providing a test pin, a select enable pin, a functional clock pin, a scan-in pin and a scan-out pin; providing a test controller having a test input connected to the test pin, a functional clock input connected to the functional clock pin, a first control output and a second control output; providing a scan chain comprised of serially connected latches and corresponding multiplexers, a first stage of each latch having an data input, a clock input connected to a functional clock pin, a first control input connected to the first control output of the test controller, a second stage of each latch having a data output and a second control input connected to the second control output of the tester controller, a data output of a previous latch connected to a first selectable input of a multiplexer corresponding to an immediately subsequent latch, a selected output of the corresponding multiplexer connected to the data input of the immediately subsequent latch, a first selectable data input of a multiplexer of the scan chain connected to the scan-in pin and a data output of a last latch of the scan chain connected to the scan-out pin.  
         [0013]     A ninth aspect of the present invention is a circuit for testing an integrated circuit, comprising: a test pin, a select enable pin, a functional clock pin, a scan-in pin and a scan-out pin; a test controller having a test input connected to the test pin, a select enable input connected to the select enable pin, a functional clock input connected to the functional clock pin, and a control output; a scan chain comprised of serially connected latches and corresponding de-multiplexers, a first stage of each latch having a data input and a clock input connected to a functional clock pin, a second stage of each latch having a data output, a data output of a previous latch connected to a first selectable input of a multiplexer corresponding to an immediately subsequent latch, a selected output of the corresponding multiplexer connected to the data input of the immediately subsequent latch, a first selectable data input of a multiplexer of the scan chain connected to the scan-in pin and a selected output of a last latch of the scan chain connected to the scan-out pin and each multiplexer of the scan chain having a select input connected to the control output of the test controller.  
         [0014]     A tenth aspect of the present invention is a method of testing an integrated circuit, comprising: providing a test pin, a select enable pin, a functional clock pin, a scan-in pin and a scan-out pin; providing a test controller having a test input connected to the test pin, a select enable input connected to the select enable pin, a functional clock input connected to the functional clock pin, and a control output; providing a scan chain comprised of serially connected latches and corresponding multiplexers, a first stage of each latch having a data input and a clock input connected to a functional clock pin, a second stage of each latch having a data output, a data output of a previous latch connected to a first selectable input of a multiplexer corresponding to an immediately subsequent latch, a selected output of the corresponding multiplexer connected to the data input of the immediately subsequent latch, a first selectable data input of a multiplexer of the scan chain connected to the scan-in pin and a selected output of a last latch of the scan chain connected to the scan-out pin and each multiplexer of the scan chain having a select input connected to the control output of the test controller. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0015]     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0016]      FIG. 1  is a schematic diagram of an integrated circuit test circuit according to a first embodiment of the present invention;  
         [0017]      FIG. 2  is a schematic circuit diagram of an exemplary clock splitter of  FIG. 1 ;  
         [0018]      FIG. 3  is a schematic circuit diagram of a test controller of  FIG. 1 ;  
         [0019]      FIG. 4  is a timing diagram of the integrated test circuit of  FIG. 1 ;  
         [0020]      FIG. 5  is a schematic diagram of an integrated circuit test circuit according to a second embodiment of the present invention;  
         [0021]      FIG. 6  is a schematic circuit diagram of a test controller of  FIG. 5 ;  
         [0022]      FIG. 7  is a timing diagram of the integrated test circuit of  FIG. 5 ;  
         [0023]      FIG. 8  is a schematic circuit diagram of an exemplary implementation of an master/slave scan latch of  FIG. 5 ;  
         [0024]      FIG. 9  is a schematic diagram of an integrated circuit test circuit according to a third embodiment of the present invention;  
         [0025]      FIG. 10  is a schematic circuit diagram of a test controller of  FIG. 9 ;  
         [0026]      FIG. 11  is a schematic circuit diagram of an exemplary implementation of an master/slave scan latch of  FIG. 9 ;  
         [0027]      FIG. 12  is a timing diagram of the integrated test circuit of  FIG. 9 ;  
         [0028]      FIG. 13  is a schematic circuit diagram of a first compact clock splitter according to the present invention;  
         [0029]      FIG. 14  is a timing diagram of the compact clock splitter of  FIG. 13 ;  
         [0030]      FIG. 15  is a schematic circuit diagram of a second compact clock splitter according to the present invention; and  
         [0031]      FIG. 16  is a timing diagram of the compact clock splitter of  FIG. 15 . 
     
    
     DETAILED DESCRIPTION  
       [0032]     A cycle is defined herein as a transition of a signal from a first state to a second state, continuance of the signal at said second state for a fixed period of time, transition from the second state back to the first state and continuance of the signal at the first state for the same fixed period of time. A pulse is defined as a transition of a signal from a first state to a second state, continuance of the signal at the second state for a fixed period of time and transition from the second state back to the first state. A pin is defined herein as an integrated circuit pad, a circuit input or output or a circuit node.  
         [0033]      FIG. 1  is a schematic diagram of an integrated circuit test circuit according to a first embodiment of the present invention. The first embodiment of the present invention is an application of the present invention to level sensitive scan design (LSSD) testing methodology. In  FIG. 1 , integrated circuit  100  includes a test controller  105 , a multiplicity of clock splitters  110  each supplying a ZC clock signal and a ZB clock signal to LSSD scan chains  115 , each scan chain  115  including a multiplicity of L 1 L 2  scan latches  120 . Only one scan chain  115  is illustrated in  FIG. 1 , but each clock splitter  110  is capable of supplying the ZC and ZB clock signals to other scan chains  115 .  
         [0034]     Test controller  105  includes a functional frequency clock input pin (OSC), a B test clock pin (B), a test mode pin (TEST), a first control signal output pin (CN 1 ) and a second control signal output pin (CN 2 ). Test controller receives a functional frequency clock signal OSC (this is the clock signal used during normal operational mode of the integrated circuit) at the OSC pin, a test clock B signal at the B pin and a test mode signal TEST at the TEST pin. Test controller generates a first control signal CN 1  at the CN 1  pin and a second control signal CN 2  at the CN 2  pin. Test controller  105  is illustrated in FIG. 3  and described infra.  
         [0035]     Each clock splitter  110  includes a CN 1  input pin (CN 1 ), a CN 2  input pin (CN 2 ), a C test clock input pin (C), a functional frequency clock input pin (OSC), an optional enable signal input pin (EN), a functional frequency C clock output pin (ZC) and a functional frequency B clock output pin (ZB). Each clock splitter receives from test controller  105 , the first control signal CN 1  at pin CN 1 , the second control signal CN 2  at pin CN 2 , a TEST CLK C signal at pin C, the OSC signal at pin OSC and the EN signal at pin EN. Each clock splitter  110  generates a test/functional frequency clock ZC signal at pin ZC and a test/functional frequency clock ZB signal at pin ZB. Clock splitter  110  is illustrated in FIG. 2  and described infra.  
         [0036]     Each L 1 L 2  scan latch  120  in scan chain  115  includes an L 1  section having an input pin (I), a data pin (D), an A clock signal pin (A) and a C clock signal pin (C) and an L 2  section having a output pin (Q) and a B clock input pin (B). The D and Q pins are coupled to the combinational logic (not shown) being tested and all L 1 L 2  scan latches  120  are coupled in series by connecting the Q pin of a previous L 1 L 2  scan latch to the I pin of the immediately subsequent L 1 L 2  scan latch. Test patterns are scanned in to the I pin of the first L 1 L 2  scan latch  120  in scan chain  115  and resultant patterns are scanned out through the Q pin of the last L 1 L 2  scan latch in the scan chain. The C pin of each L 1 L 2  scan latch  120  receives the ZC signal and the B pin of each L 1 L 2  scan latch receives the ZB signal from one of the clock splitters  110 . L 1 L 2  latches are well known in the art. The A pin of each L 1 L 2  scan latch receives a TEST CLK A signal.  
         [0037]     A test pattern is loaded into scan chain  115  by a series of TEST CK A-ZB pulses. The TEST CLK A pulse captures in the L 1  section data present at the I pin and the ZB pulse moves the data from the L 1  section to the L 2  section. ZB is at tester frequency (TEST B CLK frequency) during this operation. A ZC pulse then moves data at pin D into the L 1  section. The ZC pulse may be at tester frequency (TEST CLK C frequency) or functional frequency (OSC frequency). When ZC is at functional frequency, control signals CN 1  and CN 2  generated by test controller  105  eliminate the problem of “sequential depth” (the replacement of the test pattern with the data in the logic circuits upon switching ZB and ZC from tester frequency to functional frequency) by ensuring a functional frequency ZB pulse is issued first.  
         [0038]     The tester generates TEST CLK A, TEST CLK B and TEST CLK C and in one example have frequencies of about 30 to 100 MHz, however these speeds may be expected to increase as testers become faster. OSC is generated by the integrated circuit chip itself and in one example has a frequency of about 1 to 5 GHz, however this speed may be expected to increase as integrated circuits become faster. Clock signals ZC and ZB are generated by clock splitters  110  and have the same frequency and the leading and trailing pulse edges of clock signals ZB and ZC are aligned respectively to leading and trailing clock edges of clock signal OSC.  
         [0039]      FIG. 2  is a schematic circuit diagram of an exemplary clock splitter  110  of  FIG. 1 . In  FIG. 2 , clock splitter includes NAND gates N 1 , N 2 , N 3  and N 4  and inverters I 1 , I 2  and  13 . A first input of NAND gate N 1  is coupled to OSC and a second input of NAND gate N 1  is coupled to EN. The output of NAND gate N 1  is coupled to a first input of NAND gate N 2  and a second input of NAND gate N 2  is coupled to TEST CLK C. The output of NAND gate N 2  is coupled to a first input of NAND gate N 4  and to a first input of NAND gate N 3  through inverter I 1 . A second input of NAND gate N 4  is coupled to CN 2  and a second input of NAND gate N 3  is coupled to CN 1 . The output of NAND gate N 3  is coupled to the input of inverter I 2 , the output of inverter I 2  being ZC. The output of NAND gate N 4  is coupled to the input of inverter I 3 , the output of inverter  13  being ZB.  
         [0040]     When EN, CN 1 , CN 2  and TEST CLK C are high, clock splitter generates ZB and ZC at functional frequency (OSC frequency) and the state of OSC controls the state of ZB and ZC. When OSC is high, ZB is high and ZC is low. When OSC is low, ZB is low and ZB is high.  
         [0041]     When TEST CLK C is low, Clock splitter output ZC is low and ZB is controlled by CN 2 . When CN 2  is low, ZB is low and when CN 2  is high, ZB is high.  
         [0042]     When TEST CLK C is high and CN 2  is low, clock splitter ZB is low and ZC is controlled by CN 1 , OSC, and EN. When CN 1  is high and either OSC is low or EN is low, ZC is high.  
         [0043]     When CN 1  is low or when OSC and EN are both high, ZC is low.  
         [0044]      FIG. 3  is a schematic circuit diagram of test controller  105  of  FIG. 1 . In  FIG. 3 , test controller  105  includes latches Q 1 , Q 2  and Q 3  which form a state machine. Latch Q 1  includes a NAND gate N 7 , an And/Or/Invert (AOI) gate AOI 2  and a NOR gate N 8 . The output of NAND gate N 7  is connected to a first AND input of AOI 2  and the output of AOI 2  is connected to a node Q 1 B which is connected to a first input of NOR gate N 8 . A first input of NAND gate N 7  is connected to a second AND input of AOI 2  and the output of NOR gate N 8  is connected to a third AND input of AOI 2 .  
         [0045]     Latch Q 2  includes an inverter  16 , a NAND gate N 9 , and AOI 3  and a NOR gate N 10 . The output of NAND gate N 9  is connected to a first AND input of AOI 3  and the output of AOI 3  is connected to a node Q 2 B which is connected to a first input of NOR gate N 10 . The output of NOR gate N 10  is connected to a second AND input of AOI 3 . The output of NOR gate N 8  is connected to a third AND input of AOI 3 .  
         [0046]     Node Q 2 B is connected to a second input of NAND gate N 7 .  
         [0047]     Latch Q 3  includes an AOI 4  and a NOR gate N 11 . The output of AOI 4  is connected to a node Q 3 B which is connected to a first input of NOR gate N 11 . The output of NOR gate N 11  is connected to an OR input of AOI 4 . The output of NOR gate N 10  is connected to a first AND input of AOI 4 .  
         [0048]     A fourth AND input of AOI 2  and a fourth AND input of AOI 3  are connected to node Q 3 B. The first input of NAND gate N 7  is connected to a second AND input of AOI 4 .  
         [0049]     A TEST signal is supplied to the input of inverter I 5  and the output of inverter I 5  (a signal TESTB) is coupled to a second input of NOR gate N 8 , a second input of NOR gate N 10  and a second input of NOR gate N 11 . The output of NOR gate N 8  is also connected to a first input of NAND gate N 9 . TESTB is coupled to a first input of a NOR gate N 6  and OSC is coupled to a second input of NOR gate N 6 . The output of NOR gate N 6  is connected to the input of inverter I 6  as well as to the first input of NAND gate N 7  and a second AND input of AOI 4 . The output of inverter I 6  is connected to a second input of NAND gate N 9  and a fifth AND input of AOI 3 .  
         [0050]     TEST is also coupled to a first input of a NAND gate N 5 A and a first AND input of AOI 1 . Node Q 1 B is connected to a second AND input of AOI 1  and node Q 2 B is connected to a second input of AND gate N 5 A. A TEST CLK B is coupled to an input of an inverter I 4  and the output of inverter  14  is connected to the OR input of AOI 1 . The output of NAND gate N 5 A is coupled to CN 1 , and the output of AOI 1  is coupled to CN 2 .  
         [0051]     A low on input TEST resets latches Q 1 , Q 1 , Q 2  low in preparation for a test cycle at functional frequency. After TEST goes high, there are 2 startup states for Q 1 . If OSC was stopped low, Q 1  will go high and if TEST CLK B is high, turn CN 2  high in anticipation of positive functional clock pulses. If OSC was stopped high, a low in latch Q 1  holds CN 2  low until the first time OSC goes low setting Q 1  high, allowing CN 2  to go high if TEST CLK B is high. With TEST CLK B high and CN 2  high the circuit is ready to pass the first OSC pulse. When CN 2  is high, then the Slave latch of the flip-flop can be updated.  
         [0052]     At this time latch Q 2  will remain low, holding CN 1  low.  
         [0053]     This prevents the master latch of the flip-flops from being updated until the next time OSC goes high after Q 1  went high. When OSC goes high after Q 1  going high, Q 2  will go high driving CN 1  high. This then allows the master latch of the flip-flops to be updated.  
         [0054]     Latch Q 3  is low until the next time OSC goes high after Q 2  went high. Latch Q 3  starts the termination of the control sequence and will remain high insuring that the sequence does not restart until reset by the TEST signal going low.  
         [0055]     Latch Q 2  remains high holding CN 1  high until OSC goes high after which Q 2  goes low. The Master latch has been updated and Q 2  low prevents future updates.  
         [0056]     Latch Q 1  is high holding CN 2  high until OSC goes low after Q 2  has gone low. At this time Q 1  goes low. This stops the clock sequence and no further changes to the flip-flop data in either the master or slave latches can occur until the circuit has been reset by TEST going low.  
         [0057]     For the following discussion of the operation of test controller  105 , reference to the timing diagram of  FIG. 4  as well as  FIGS. 1 through 3  will be helpful. Test controller  105  is off when TEST is low causing both CN 1  and CN 2  to remain high and integrated circuit  125  is in operational mode and there are no delay or switching impacts to clock splitters  110 . Test controller  105  is in test mode when TEST is high and TEST CLK B is held high, forcing both CN 1  and CN 2  low. In test mode there is no change in CN 1  or CN 2  unless OSC is low or until the first falling edge of OSC. On the first falling edge of OSC, CN 2  goes high. On the first rising edge of OSC, CN 1  goes high. On the next rising edge of OSC CN 1  goes low. On the next falling edge of OSC, CN 2  goes low. Thereafter CN 1  and CN 2  remain low regardless of the state of OSC. Thus CN 2  is high for two OSC cycles and CN 1  is high for one OSC cycle, but CN 1  and CN 2  are a half an OSC cycle out of phase. The result of clock splitter  110  (see  FIG. 1 ) receiving these timed and coordinated CN 1  and CN 2  signals is to cause the clock splitter to generate a ZB high pulse followed by a ZC high pulse followed by a ZB high pulse, the ZC being high between ZB pulses with the ZB and ZC pulses at the OSC frequency and being a half cycle out of phase (see  FIG. 4 ). The first ZB pulse high causes data in the L 1  section of the L 1 L 2  scan latches  120  (see  FIG. 1 ) to be transferred (or launched) from the L 1  section to the L 2  section and into the combinatorial logic connected to the output Q of the L 2  section. The ZC pulse high causes data on the D pin to be captured in the L 1  section. The second ZB high pulse again moves data in the L 1  section to the L 2  section but with no further ZB or ZC pulses no further data transfer is possible. Thus, the test vector is flushed out of L 1 L 2  scan latches  120  and replaced with the response to the combination logic being tested.  
         [0058]     Because CN 2  is a half OSC cycle ahead of ZB and ZC is a half OSC cycle ahead of ZC, enablement of the data capture of L 1  stages and transfer between L 1  and L 2  stages is enabled and disabled a half OSC cycle ahead of time thus relaxing timing constraints of integrated circuit  100  (see  FIG. 1 ). Further, because subsequent OSC pulses are ignored by test controller  105  (see  FIG. 1 ), OSC can continue to run and circuits downstream on the clock tree will not be effected.  
         [0059]     Test controller  105  (see  FIG. 1 ) can be easily modified to respond to a negative clock design (i.e. where a falling OSC edge results in data transfer and a rising edge results in data capture). Test controller  105  can be further modified to provide additional transfer and/or, capture sequences by adding additional QX latch stages.  
         [0060]      FIG. 4  is a timing diagram of the integrated test circuit of  FIG. 1 . The timings of TEST CLK B, TEST CLCK C, OSC, TEST, CN 1  CN 2  have been discussed supra. Q 3 B represents the timing of the signal on node Q 3 B (see  FIG. 3 ) during operation of test controller  100  (see  FIG. 3 ).  
         [0061]      FIG. 5  is a schematic diagram of an integrated circuit test circuit according to a second embodiment of the present invention. The second embodiment of the present invention is an application of the present invention to MUX Scan Latch testing methodology. In  FIG. 5 , integrated circuit  125  includes test controller  185 , and a scan chain  130 . As this is a Mux Scan design, a separate TEST CLK B is not needed. Scan chain  130  includes a multiplicity of multiplexers  135  and a corresponding multiplicity of master/slave flip flop (MS) scan latches  140 . Each MS scan latch  140  in scan chain  130  includes a master (M) section having a data pin (D), CLK clock signal pin (CLK) and first control pin (CN 1 ) and a slave (S) section having an output pin (Q) and a second control pin (CN 2 ). MS scan latches  140  are illustrated in  FIG. 8  and described infra. Each multiplexer  135  in scan chain  130  includes an input pin (I), a data pin (D) a select enable pin (SE) which selects whether pin I or pin D is coupled to the output of the demultiplexer based on an SE signal from the tester.  
         [0062]     The D pin of each multiplexer  135  and the Q pin of each MS scan latch are coupled to the combinational logic (not shown) being tested. The output of each multiplexer  135  is connected to the D pin of a corresponding MS scan latch  140  and all MS scan latches are coupled in series by connecting the Q pin of a previous MS scan latch to the I pin of a multiplexer  135  connected to an immediately subsequent MS scan latch. The CLK pin of each MS scan latch  140  is connected to the functional clock pin. The CN 1  pin of each MS scan latch  140  is connected to the CN 1  of test controller  105  and the CN 2  pin of each MS scan latch is connected to the CN 2  pin of the test controller.  
         [0063]     While MS latches are well known in the art, MS scan latches  140  are modified to accept and function with the CN 1  and CN 2  signals. MS scan latches  140  are illustrated in  FIG. 8  and described infra. The CLK pin of each MS scan latch receives OSC. The present MS scan latches  140  generate an OSC BAR (the inverse of OSC) internally, the S section being responsive to OSC and the M section being responsive to OSC BAR. A separate OSC BAR may be supplied.  
         [0064]     Test patterns are scanned in to the I pin of the first multiplexer  135  in scan chain  130  and resultant patterns are scanned out through the Q pin of the last MS scan latch  140  in the scan chain. A test pattern is scanned into scan chain  130  by setting SE to select I inputs and TEST low (off), and OSC is cycled to load the test pattern into scan chain  130 .  
         [0065]     The operation of integrated circuit  125  is similar to that of integrated circuit  100  of  FIG. 1 . Test controller  185  is off when TEST is low causing both CN 1  and CN 2  to remain high. Integrated circuit  125  is in operation mode when TEST is low. In operational mode when SE is held low, multiplexers  135  select D. MS scan latches  140  operate normally capturing the state at the M section of MS scan latch  140  and allowing the S section of MS scan latch  140  to sample the M section and present the state of the M section at the output of the latch on the rising edge of OSC. In scan mode when SE is high, multiplexers  135  select I and MS scan latch  140  functions as described for normal operation except that the input for the M section is now from I. Integrated circuit  125  is sequenced into test mode by holding SE high while bringing TEST high, forcing both CN 1  and CN 2  low (CN 2  may remain high if OSC stopped low). This preserves the scan state of the master and S sections of latch  140  and then SE is brought low causing multiplexers  135  to select D. In test mode there is no change in CN 1  or CN 2  unless OSC is low or until the first falling edge of OSC. On the first falling edge of OSC, CN 2  goes high. This enables the slave portion of MS scan latch  140  to be updated on the next rising edge of OSC. CN 1  is low at this time preventing the M section of MS scan latch  140  from sampling D and preserving the scan in contents. On the first rising edge of OSC, the slave portion of MS scan latch  140  samples the state of the master portion of MS scan latch  140  and presents the data to the downstream logic. CN 1  also goes high enabling the M section of MS scan latch  140  to sample the logic response (D) when OSC next goes low. On the next rising edge of OSC, the S section of MS scan latch  140  now samples the state of the M section of MS scan latch  140  and presents this state to the downstream logic. Also at this time CN 1  goes low, this prevents the M section of MS scan latch  140  from changing due to the new data presented to the logic. On the next falling edge of OSC, CN 2  goes low and prevents the slave portion of MS scan latch  140  from changing. Thereafter CN 1  and CN 2  remain low and the master and S sections of MS scan latch  140  contain the response of the logic to the scanned in test vector regardless of the state of OSC. Thus CN 2  is high for two OSC cycles and CN 1  is high for one OSC cycle, but CN 1  and CN 2  are a half an OSC cycle out of phase. CN 2  going high causes data in the M section of MS scan latch  140  to be transferred (or launched) from the M section to the S section and into the combinatorial logic connected to the S section output on the next rising edge of OSC. Again, this enablement is a half an OSC clock cycle early. On a rising edge of OSC, CN 1  going high causes data on the Q pin of the previous MS scan latch  140  to be captured in the M section of the subsequent MS scan latch. Again, this enablement is a half an OSC clock cycle early. On the next rising edge of OSC, CN 1  goes low and stays low. Again, this disablement is a half an OSC cycle early. On the next OSC falling edge, CN 2  goes low and stays low. Again, this disablement is a half an OSC cycle early. Because CN 2  changes on the falling edge of OSC and CN 1  changes on the rising edge of OSC, enablement of the data capture of M stages and transfer between M and S stages is enabled and disabled a half an OSC cycle ahead of time thus relaxing timing constraints of integrated circuit  125 .  
         [0066]     Further, because further OSC pulses are ignored by test controller  185  (see  FIGS. 5 and 6 ), OSC can continue to run and circuits downstream on the clock tree will not be effected.  
         [0067]      FIG. 6  is a schematic circuit diagram of test controller  185  of  FIG. 5 . Test controller  185  is similar to test controller  105  of  FIG. 3  except the TEST CLK B pin (there is no longer a TEST CLK B), inverter  14  and AOI 1  of  FIG. 3  are replaced with a NAND gate N 5 B.  
         [0068]      FIG. 7  is a timing diagram of the integrated test circuit  125  of  FIG. 5 . The timings of OSC, SE, TEST, Q 3 B, CN 1  CN 2  have been discussed supra. Integrated circuit  125  is sequenced from scan mode to test mode and then back scan mode as shown.  
         [0069]     Test controller  185  (see  FIG. 6 ) can be easily modified to respond to a negative clock design (i.e. where a falling OSC edge results in data transfer and a rising edge results in data capture). Test controller  185  (see  FIG. 6 ) can be further modified to provide additional transfer and/or, capture sequences by adding additional QX latch stages.  
         [0070]      FIG. 8  is a schematic circuit diagram of an exemplary implementation of MS scan latch  140  of  FIG. 5 . Other implementations using a different base latch design and adding CN 1  and CN 2  inputs are possible. In  FIG. 8 , MS scan latch  140  includes an M section  145 A and an S section  145 B, AND gates  150 A and  150 B and inverters  155 A,  155 B and  155 C. M section  145 A includes PFETs T 1 , T 2 , T 5 , T 6  and T 9  and NFETs T 3 , T 4 , T 7 , T 8  and T 10  and an output node MS. S section  145 B includes PFETs T 11 , T 12 , T 15 , T 16 , T 19  and T 21  and NFETs T 13 , T 14 , T 17 , T 18 , T 20  and T 22 . AND gate  150 A includes PFETs T 23  T 26  and NFETs T 24 , T 25  and T 27  and an output node C 1 . AND gate  150 B includes PFETs T 28 , T 31  and NFETs T 29 , T 30  and T 32  and an output node C 2 . Inverter  155 A includes a PFET T 33  and an NFET T 34  and an output node C 3 . Inverter  155 B includes a PFET T 35  and an NFET T 36  and an output node C 4 . Inverter  155 C includes a PFET T 37  and an NFET T 38  and an output node C 5 .  
         [0071]     The D input pin of MS scan chain latch  140  is connected to the gates of PFET T 1  and NFET T 4  of M section  145 A, and the Q output pin of MS scan chain latch  140  is connected to the drains of PFET T 21  and NFET T 22  of S section  145 B. The CLK pin of MS scan latch  140  is connected to the drains PFET T 23  and NFET T 24  of AND gate  150 A. The CN 2  pin of MS scan chain latch  140  is connected to the gates of PFET T 26  and NFETs T 24  and T 27  of AND gate  150 A. Output node Cl of AND gate  150 A is connected to the gates of PFET T 33  and NFET T 34  (the input) of inverter  155 A. The drains of PFET T 33  and NFET T 34  (output node C 3 ) of inverter  155 A are connected to the drains of PFET T 28  and NFET T 29  of AND gate  150 B. The CN 1  pin of MS scan chain latch  140  is connected to the gates of PFET T 31  and NFETs T 29  and T 32  of AND gate  150 B. Output node C 2  of AND gate  150 B is connected to the gates of PFET T 35  and NFET T 36  (the input) of inverter  155 B. The drains of PFET T 35  and NFET T 36  (output node C 4 ) are connected to the gates of PFET T 37  and NFET T 38  (the input) of inverter  155 C. The drains of PFET T 37  and NFET T 38  (output node C 5 ) of inverter  155 C are connected to the gates of NFET T 3  and PFET T 6  of M section  145 A. Output node C 4  of inverter  155 B is connected to the gates of PFET T 2  and NFET T 7  of M section  145 A. Output node C 3  of inverter  155 A is connected to the gates of PFET T 12  and NFET T 17  of S section  145 B. Output node C 1  of AND gate  150 A is connected to the gates of PFET T 16  and NFET T 13  of S section  145 B.  
         [0072]     AND gate  150 B allows CN 1  to control latching of data on the D pin by M section  145 A by gating CLK. AND gate  150 A allows CN 2  to control transfer of data in M section  145 A into S section  145 B by gating CLK.  
         [0073]      FIG. 9  is a schematic diagram of an integrated circuit test circuit according to a third embodiment of the present invention. The third embodiment of the present invention is also an application of the present invention to MUX Scan Latch testing methodology, but using unmodified or standard MS latches. In  FIG. 9 , integrated circuit  160  includes test controller  165 , and a scan chain  170 . Scan chain  170  includes a multiplicity of multiplexers  175  and a corresponding multiplicity of MS scan latches  180 . Each MS scan latch  180  in scan chain  170  includes an M section having a data pin (D) and a clock signal pin (CLK) and an S section having a output pin (Q). Each multiplexer  175  in scan chain  170  includes an input pin (I), a data pin (D) a select enable pin (SE) which selects whether pin I or pin D is connected to the output of the de-multiplexer. MS scan latches  180  are illustrated in  FIG. 11  and described infra. Test controller  165  includes an OSC input pin, a TEST input pin (for respectively receiving the OSC and TEST signals described supra) a select enable input pin for receiving the SE signal (described supra) from the tester, and a CNSE output pin for a CNSE signal that controls the select function of each multiplexer  175 . Test controller  165  is illustrated in  FIG. 10  and described infra.  
         [0074]     The D pin of each de-multiplexer  175  and the Q pin of each MS scan latch are coupled to the combinational logic (not shown) being tested. The output of each multiplexer  175  is coupled to the D pin of a corresponding MS scan latch  180  and all MS scan latches are coupled in series by connecting the Q pin of a previous MS scan latch to the I pin of a multiplexer  175  connected to an immediately subsequent MS scan latch. The SE pin of each demultiplexer  175  is connected to the CNSE pin of test controller  165  and each CLK pin of each MS scan latch  180  is coupled to the functional clock pin. The present MS scan latches  140  generate CLK BAR (the inverse of CLK) internally, the S section being responsive to CLK and the M section being responsive to CLK BAR. A separate CLK BAR may be supplied.  
         [0075]     Test patterns are scanned in to the I pin of the first demultiplexer  175  in scan chain  170  and resultant patterns are scanned out through the Q pin of the last MS scan latch  180  in the scan chain. A test pattern is scanned into scan chain  170  by setting TEST to low (off) and SE to select the I inputs of de-multiplexers  175  and the test pattern into scan chain  170  as OSC cycles.  
         [0076]      FIG. 10  is a schematic circuit diagram of test controller  165  of  FIG. 9 . Tester control  165  is similar to tester controller  105  except AOI 1  and NAND gate N 5 A are replaced with AND gate A 12  and NOR gate N 13 , TEST CLK B is replaced with SE, CN 1  and CN 2  are replaced with CNSE. TEST is coupled to a first input of AND gate N 12  and node Q 2 B is coupled to a second input of AND gate A 12 . SE is coupled through an inverter I 19  to a first input of NOR gate N 13 , the output of AND gate A 12  (a node N 1 ) is connected to a second input of NOR gate N 13  and the output of NOR gate N 13  is connected to a CNSE output pin.  
         [0077]      FIG. 11  is a schematic circuit diagram of an exemplary implementation of MS scan latches  180  of  FIG. 9 . In  FIG. 9 , MS scan latch  180  is similar to MS scan latch  140  of  FIG. 8 , except there are no AND gates  150 A and  150 B or CN 1  or CN 2  signals, CLK is connected directly to the input of inverter  155 A and node C 3  is connected directly to the input of inverter  155 B.  
         [0078]     For the following discussion of the operation of integrated circuit  160 , reference to  FIGS. 9 through 12  will be helpful. Returning to  FIG. 9  during operation of integrated circuit  160 , test controller  165  is off when TEST is low causing CNSE to follow the state of SE. If SE is low the multiplexers and integrated circuit  160  are in operational mode and there is no delay or switching impact to scan chain  170 . Test controller  165  is in test mode when TEST is high and CNSE now has a more complex logical function. In the functional speed test mode, SE remains high and then TEST is pulled high. OSC can be stopped high or low. Then two at speed clock pulses are propagated down OSC. On a first rising edge of OSC, the S section of MS scan latch  180  samples the contents of the M section of MS latch  180  and presents this value to the logic under test. The M section of MS scan latch  180  contains the values that were scanned in for test. CNSE is also pulled low switching the multiplexer  175  from passing I to passing D to the M section of MS scan latches  180  to sample the data on their D pins on the next falling edge of OSC. Again this enablement occurs a half cycle early. On the next rising edge of OSC, the S section of MS scan latches  180  samples the data on the M section of MS scan latches  180 . CNSE also goes high and stays high. This prevents any further data captures from the combinational logic occurring on the M section of MS scan latches  180 . Further OSC cycle scan-out the test data, it would be preferred at this point to switch back to scan mode and use the slower speed scan clock. TEST would be preferably pulled high but this is not required.  
         [0079]      FIG. 12  is a timing diagram of the integrated test circuit of  FIG. 9 . The timing of SE, OSC, TEST and CNSE have been described supra. Node N 1  is high when TEST is low, goes low when TEST goes high, goes high again when CNSE goes low and goes low again (and stays low) when CNSE goes high.  
         [0080]     The first embodiment of the present invention described supra and illustrated in  FIG. 1 , utilized a separate test controller and clock splitter. The fourth and fifth embodiments of the present invention utilize a combined test controller and clock splitter circuit.  
         [0081]      FIG. 13  is a schematic circuit diagram of a first compact clock splitter according to the present invention;. In  FIG. 13 , a compact test splitter  190  includes a first latch Q 4 , a second latch Q 5 , a third latch Q 6 , (latches Q 4 , Q 5  and Q 6  forming a state machine) an output stage CS 1 , inverters I 7  and I 12 , NOR gate N 19 , AOI 5 , a C test clock pin (TEST CLK C), an enable pin (EN), an OSC pin (OSC), a B test clock pin (TEST CLK B), a mode pin (TEST) a first output pin (ZC) and a second output pin (ZB).  
         [0082]     First latch Q 4  includes NAND gates N 20  and N 21 , inverter I 11  and Or/And/Invert gate (OAI) OAI 8 . The output on NAND gate N 20  is connected to a first input of NAND gate  21 , the output of inverter I 11  is connected to a first OR input of OAI 8 . The output of OAI 8  (node Q 4 B) is connected to a second input of NAND gate N 21  and the output of NAND gate N 21  is connected to a first AND input OA 18 .  
         [0083]     Second latch Q 5  includes an OAI 6  and an OAI 7 . The output of OAI 6  (node Q 5 B) is connected to an AND input of OAI 7  and the output of OAI 7  is connected to the AND input of OAI 6 .  
         [0084]     Third latch Q 6  includes NAND gates N 22  and N 23 . The output of NAND gate N 22  is connected to a first input of NAND gate N 23 , and the output of NAND gate N 23  (node Q 6 B) is connected to a first input of NAND gate N 22 .  
         [0085]     Output stage CS 1  includes NAND gates N 14 , N 15 , and N 18 , NOR gates N 16  and N 17  and inverters I 9  and I 10 .  
         [0086]     TEST CLK C is connected to a first input of NAND gate N 15 . EN is connected to a first input of NAND gate N 14 . OSC is connected to a second input of NAND gate N 14  and a first input of NOR gate N 19 . The output of NAND gate N 14  is connected to a second input of NAND gate N 15 , and the output of NAND gate N 15  is connected to a first input of NOR gate N 17  and a first input of NAND gate N 18 . The output of NOR gate N 16  is connected to a second input of NOR gate N 17 . The output of NOR gate N 17  is coupled to ZC through serially connected inverters  18  and  19 . The output of NAND gate N 18  is coupled to ZB through inverter I 10 .  
         [0087]     Interconnections between output stage CS 1  and latch stages Q 4 , Q 5  and Q 6  are as follows: TEST CLK B is coupled to the OR input of AOI 5  through inverter I 12 . The output of AOI 5  is connected to a second input of NAND gate N 18 . TEST is coupled to a second input of NOR gate N 19  and a first input of NOR gate N 16  through inverter  17 , and is connected to a second AND input of OA 18 , a first AND input of AOI 5  and a second input of NAND gate N 23 . The output of NAND gate N 23  (Q 6 B) is also connected to a second AND input of AOI 5 , a second OR input of OA 18  and a first input of NAND gate N 20 . The output of NOR gate N 19  is connected to a second input of NAND gate N 20 , the input of inverter I 11 , a first OR input of OAI 6  and a first OR input of OAI 7 . The output of OA 18  (Q 4 B) is also connected to a second OR input of OAI 6  and a third AND input of AOI 5 . The output of OAI 7  is also connected to a second input of NAND gate N 22 , and the output of OA 16  (Q 5 B) is also connected to a second input of NOR gate N 16 , and the output of NAND gate  21  is also connected to a second OR input of OAI 17 .  
         [0088]     The operation of compact clock splitter  190  is best understood with reference to  FIGS. 14 and 15 .  FIG. 14  is a timing diagram of compact clock splitter  190  of  FIG. 13 . Compact clock splitter  190  takes OSC and generates the non-overlapping clock pulses ZB and ZC used to control LSSD scan chains as described supra. ZB goes high when OSC goes high and allows transfer of data between L 1  and L 2  latches of the L 1 /L 2  LSSD latches. ZC goes high when OSC goes low and latches data at the D pins of the L 1  latch of the L 1 /L 2  LSSD latches. The time period from the rising edge of ZB to the falling edge of ZC is the time period for data to propagate through the L 2  latch of the L 1 /L 2  LSSD latch, through the logic being tested and then be latched by the L 1  latch. The ZB-ZC pulse duration is from the first rising edge of OSC to the next rising edge of OsC.  
         [0089]     When in functional mode, TEST is low. Test low forces the output of inverter I 7  high and the output of NOR gate N 16  low, disabling ZC control. As NOR gate N 16  output is a DC non-switching level in this mode, no delay is added. TEST low also drives the AND output of AOI 5  low, removing AOI 5  from the ZB control path. TEST low also drives nodes Q 4 B and Q 6 B to high states and node Q 5 B to a low state. The output of I 7  further forces NOR gate N 19  low. This stops OSC from propagating through nodes Q 4 B, Q 5 B and Q 6 B eliminating switching power in the functional as well as any test mode where TEST is low.  
         [0090]     In test mode, TEST goes high, the output of inverter I 7  goes low and NOR gate N 16  is enabled to control ZC as a function of the state of node Q 5 B, and NOR gate N 19  is enabled to allow OSC to propagate to latches Q 4  and Q 5 . If OSC is high when TEST goes high, node Q 4 B will remain high until the falling edge of OSC to prevent ZB from going high. As node Q 4 B will be in a low state or go low at a falling edge of OSC, ZB is enabled one half cycle in advance of the first rising edge of OSC and no delay results, allowing the ZB pulse to occur with the same timing as OSC in functional mode.  
         [0091]     With the first rising edge of OSC (and node Q 4 B low), node Q 5 B goes high, returning control of ZC to OSC. As this occurs one half cycle before the falling edge of OSC, no delay results, allowing the ZC pulse to occur with the same timing as OSC in functional mode.  
         [0092]     Also with the first rising edge of OSC (and node Q 4 B low), node Q 6 B goes low, setting up latch Q 4  so node Q 4   b  will revert high on the next falling edge of OSC, and allowing node Q 5 B to go low on the next rising edge of OSC. As the logic path delay through latch Q 5  and NOR gate N 16  to NOR gate N 17  is longer than the delay from OSC through NAND gates N 14  and N 15  to NOR gate N 17 , the rising edge of OSC terminates the ZC pulse and then the falling edge of the signal at node Q 5 B arrives later and eliminates the possibility of any further ZC pulses and allowing the ZB pulse to occur with the same timing as OSC in functional mode.  
         [0093]     It should be noted that the functional operation of latches Q 4 , Q 5  and Q 6  just described is essentially the same as the operation of latches Q 1 , Q 2  and Q 3  of tester controller  105  of  FIG. 3  or  165  of  FIG. 10  described supra, except CN 1 , CN 2  and CNSE are operated upon, not ZB and ZC directly.  
         [0094]     The pattern of ZB and ZC pulses produced by compact clock splitter  190  is always ZB first, ZC second, and ZB third, the rising edge of ZC always aligned with the falling edge of the first ZB pulse and the falling edge of the ZCpulse aligned with the rising edge of the second ZB pulse. Thereafter, a series of ZB pulses are produced which cause no LSSD state changes but do consume some switching power. These “un-needed” ZB pulses are eliminated in the fifth embodiment of the present invention.  
         [0095]      FIG. 15  is a schematic circuit diagram of a second compact clock splitter according to the present invention;. In  FIG. 15 , a compact test splitter  195  includes a first latch Q 7 , a second latch Q 8 , a third latch Q 9  (latches Q 7 , Q 8  and Q 9  forming a state machine), an output stage CS 2 , a NAND gate N 37 , a C test clock pin (TEST CLK C), an enable pin (EN), an OSC pin (OSC), a B test clock pin (TEST CLK B), a mode pin (TEST) a first output pin (ZC) and a second output pin (ZB).  
         [0096]     First latch Q 7  includes NAND gates N 28 , N 29 , N 30 , N 31  and N 32  and an inverter I 16 . The output of NAND gate N 28  is connected to a first input of NAND gate N 29  and the input of inverter I 16 . The output of inverter  116  is connected to a first input of NAND gate N 30 . The output of NAND gate N 30  is connected to a first input of NAND gate N 31 . The output of NAND gate N 29  is connected to a first input of NAND gate N 32 . The output of NAND gate N 32  is connected to a second input of NAND gate N 31  and the output of NAND gate N 31  (a node Q 7 B) is connected to a second input of NAND gate N 32 .  
         [0097]     Second latch Q 8  includes NAND gates N 33 , N 34 , N 35  and N 36  and inverters I 17  and I 18 . The output of inverter I 18  is connected to a first input of NAND gate N 35  and a first input of NAND gate N 33 . The second input of NAND gate N 33  is connected to the input of inverter I 17  and the output of inverter I 17  is connected to a second input of NAND gate N 35 . The output of NAND gate N 33  is connected to a first input of NAND gate N 34  and the output of NAND gate N 35  is connected to a first input of NAND gate N 36 . The output of NAND gate N 36  is connected to a second input of NAND gate N 34  and the output of NAND gate N 34  (a node Q 8 B) is connected to a second input of NAND gate N 36 .  
         [0098]     Third latch Q 9  includes NAND gates N 38 , N 39  and N 40 . The output of NAND gate N 39  is connected to a first input of NAND gate N 40 . The output of NAND gate N 40  is connected to a first input of NAND gate N 38  and the output of NAND gate N 38  (a node Q 9 B) is connected to a second input of NAND gate N 40 .  
         [0099]     Output stage CS 2  includes NAND gates N 24 , N 25 , N 26  and N 27  and inverters  113 ,  114  and  115 . TEST CLK C is connected to a first input of NAND gate N 25 . EN is connected to first input of NAND gate N 24  and OSC is connected to a second input of NAND gate N 24 . The output of NAND gate N 24  is connected to a second input of NAND gate N 25 . The output of NAND gate N 25  is connected to a first input of NAND gate N 26  through inverter  113  and to a first input of NAND gate N 27 . TEST CLK B is connected to a second input of NAND gate N 27 . The output of NAND gate N 26  is connected through inverter I 14  to ZC and the output of NAND gate N 27  is connected through inverter I 15  to ZB.  
         [0100]     Interconnections between output stage CS 2  and latch stages Q 7 , Q 8  and Q 9  are as follows: TEST is connected to a third input of NAND gate N 31 , a third input of NAND gate N 34 , a first input of NAND gate N 37 , a second input of NAND gate N 38  and a first input of NAND gate N 39 . The output of NAND gate N 24  is also connected to a second input of NAND gate N 29 , a second input of NAND gate N 30  and the input of inverter I 18 . Node Q 7 B is also connected to the input of inverter I 17  (and thus the second input of NAND gate N 33 ). The output of node I 15  is connected to a second input of NAND gate N 39 . Node Q 8 B is also connected to a second input of NAND gate N 37  and a first input of NAND gate N 28 . Node Q 9 B is also connected to a second input of NAND gate N 28 . The output of NAND gate N 37  is connected to a second input of NAND gate N 26  and a second input of NAND gate N 27 .  
         [0101]     Compact splitter  195  operates in a similar manner as compact splitter  190  of  FIG. 1 , except only two ZB pulses are generated. Latches Q 7  and Q 8  are master/slave “D” type latches. In order to reduce transistor count, each master/slave latch could be replaced with a single latch connected to a first input of an AND gate and also connected through an inverter to a second input of the same AND gate to provide a control pulse sensitive to the rising edge of the corresponding TEST CLK B or TEST CLK C.  
         [0102]     However, the ZB and ZC pulse duration is a “designed in delay and not a delay governed by rising OSC edges.  
         [0103]      FIG. 16  is a timing diagram of compact clock splitter  195  of  FIG. 15 . The only difference between the timing diagram of  FIG. 14  and that of  FIG. 16  is there are only two ZB pulses in the timing diagram of  FIG. 16 .  
         [0104]     Thus, the present invention provides a method and circuit for testing integrated circuits at a functional frequency.  
         [0105]     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. For example, throughout the description of the present invention supra, types of latches called an L 1 L 2  or MUX scan latches were used. The use of an L 1 L 2  latch or MUX scan latch should be considered exemplary and other types of latches well known in the art may be subsituted and adjustments to the test controller of the present invention made if and as required. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.