Abstract:
A linear power amplifier utilizes active feedback pre-distortion linearization. The power amplifier is a two-stage amplifier which includes a pre-distortion active feedback driver amplifier and a power amplifier. The driver amplifier provides gain expansion and insertion phase decrease as input power is increased, which compensates for the output power amplifier&#39;s gain compression and insertion phase increase with input power, resulting in a two-stage amplifier with relatively higher linear power output power capability and associated power-added efficiency. The two-stage linear power amplifier in accordance with the present invention provides improved linear efficiency which can be mass-produced in high volume with excellent repeatability. A voltage bias circuit with an external voltage post enables the two-stage amplifier to be tuned with an external voltage for optimum performance.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a monolithic linear power amplifier, and more particularly, to a two-stage monolithic linear power amplifier which includes a pre-distortion active feedback driver amplifier and an output power amplifier which incorporates active feedback in the driver amplifier to pre-distort and amplify incoming RF signals to create amplitude and phase characteristics which compensate for the amplitude and phase characteristics of the output power amplifier stage in order to extend the linear output characteristics of the combined two-stage amplifier. 
     2. Description of the Prior Art 
     Increasing the efficiency of linear power amplifiers is key to reducing the cost, weight, size and integration complexity for various communications systems, including transmitters for satellite and terrestrial communications systems. Linear amplification is also required for communications which use non-constant envelope modulation schemes, wherein the amplitude and phase characteristics of the transmitted signal must be preserved. Examples of such systems requiring linear power transmission are: phased array, satellite down-links, and terrestrial wireless communications, such as cellular and cordless telephones. In such systems, the higher the linear efficiency, the fewer amplifier cells need to be combined in a power amplifier stage, matrix or array, also resulting in reduced DC converter peripheral hardware and harnessing. By limiting the number of amplifier cells, the overall size, weight and integration complexity of the amplifier for such applications will be reduced, which results in lower overall cost and higher performance. Such reduced size and weight is particularly desirable in certain applications, such as satellites communications systems where the weight of the spacecraft is critical. Improved efficiency linear power amplifiers are also beneficial in terrestrial communications systems, such as cellular and cordless telephone systems, wherein the improved amplifier efficiency results in improved battery life. 
     As mentioned above, for non-constant envelope-modulated communications systems, preserving the amplitude and phase characteristics of the transmitted information is crucial to system performance. As such, such systems normally require power amplifiers which employ circuitry to back off input power until the amplifier is in a region of linear operation. Such systems are known to use a power amplifier output detector and a variable gain amplifier in a controlled loop. However, there are tradeoffs to backing off the compression in order to improve the linearity of an amplifier, such as reducing the amplifier&#39;s power-added efficiency (PAE). Conventionally, linear power efficiencies of about 20 to 25 percent are typical at a few decibels backed off of compression, which is relatively poor efficiency performance with respect to the power amplifier&#39;s saturated power-added efficiency, known to range from about 35 percent to as high as 80 percent. Unfortunately, for non-constant envelope modulation systems, the power amplifier must be operated in the linear region and backed off of compression, making the efficiency even worse. 
     Several techniques are known for improving the linear power efficiency of amplifiers, such as feedforward linearization and pre-distortion techniques. Such techniques are disclosed in &#34;A Feedforward Experiment Applied to an L-4 Carrier System Amplifier&#34;, by H. Seidel, IEEE Transactions on Communication Technology, Vol. COM-19, No. 3, June 1971, pp. 320-325; &#34;Passive FET MMIC Linearizers for C, X and Ku- Band Satellite Applications&#34;, by A. Katz, S. Moochalla, and J. Klatskin, 1993 IEEE MMWMC Symp. Dig., Atlanta, Ga., pp. 155-158; &#34;A Reflective Diode Linearizer for Spacecraft Applications&#34;, by A. Katz, R. Sudarsanam and D. Aubert, 1985 IEEE MTT Symp. Dig., St. Louis, Mo., pp. 661-664; &#34;A Compact 4-GHz Linearizer for Space Use&#34;, by R. Inada, H. Ogawa, S. Kitazume and P. Desantis, IEEE Transactions on MTT, Vol. MTT-34, No. 12, December 1986, pp. 1327-1332; and U.S. Pat. No. 5,264,806. Unfortunately, such techniques involve relatively complicated methods or systems which require additional hardware, are not economically feasible in a high-volume production environment, or are very sensitive and require precise tuning. Moreover, many of these known techniques are not practical to implement in portable handset applications where low cost and small size are critical and little or no performance tuning of the part is allowed. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a linear power amplifier that solves various problems in the prior art. 
     It is yet another object of the present invention to provide a linear power amplifier with increased efficiency. 
     Briefly, the present invention relates to a linear power amplifier which utilizes active feedback pre-distortion linearization. The linear power amplifier is implemented as a two-stage amplifier with a pre-distortion active feedback driver amplifier and a power amplifier. The driver amplifier provides gain expansion and insertion phase decrease as input power is increased, which compensates for the output power amplifier&#39;s gain compression and insertion phase increase with input power, resulting in a two-stage amplifier with relatively higher linear power output power capability and associated power-added efficiency. A circuit with an external voltage bias part enables the two-stage amplifier to be tuned with an external voltage for optimum performance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     These and other objects of the present invention will be readily understood with reference to the following specification and attached drawing, wherein: 
     FIG. 1 is a block diagram of a linearized two-stage power amplifier in accordance with the present invention. 
     FIG. 2 is a schematic diagram of the pre-distortion active feedback driver amplifier of the linearized two-stage amplifier in accordance with the present invention. 
     FIG. 3A is a graphical illustration of the gain, output power P OUT  and power-added efficiency (PAE), as a function of the input power P IN  of the pre-distortion active feedback driver amplifier in accordance with the present invention. 
     FIG. 3B is a graphical illustration of the gain, output power P OUT  and normalized insertion phase as a function of the input power P IN  of the pre-distortion active feedback driver amplifier in accordance with the present invention. 
     FIG. 4 is a schematic diagram of the output power amplifier portion of the linearized two-stage power amplifier in accordance with the present invention. 
     FIG. 5A is a graphical illustration of the gain, output power P OUT  and power-added efficiency (PAE) as a function of the input power P IN  of the output power amplifier stage. 
     FIG. 5B is a graphical illustration of the gain, output power P OUT  and normalized insertion phase as a function of the input power P IN  of the output power amplifier stage. 
     FIG. 6A is a graphical illustration of the gain, output power P OUT , as well as the power-added efficiency (PAE) as a function of the input power P IN  of the linearized two-stage power amplifier in accordance with the present invention. 
     FIG. 6B is a graphical illustration of the gain, output power P OUT , and normalized insertion phase as a function of the input power P IN  of the linearized two-stage power amplifier in accordance with the present invention. 
     FIG. 7 is a schematic diagram of an alternate embodiment of the pre-distortion active feedback driver amplifier with a tuning bias circuit coupled to its active feedback transistor. 
     FIG. 8 is another alternate embodiment of the pre-distortion active feedback driver amplifier with a tuning bias circuit coupled to its balanced collector-coupled transistor. 
     FIG. 9A is a simplified schematic diagram of the circuit illustrated in FIG. 8 for a relatively high tuning voltage V afb . 
     FIG. 9B is a graphical illustration of the gain, output power P OUT  and power-added efficiency (PAE) of the circuit illustrated in FIG. 9A. 
     FIG. 9C is a graphical illustration of the gain, output power P OUT , and normalized insertion phase as a function of the input power P IN  for the circuit illustrated in FIG. 9A. 
     FIG. 10A is similar to FIG. 9A, but for a medium tuning voltage V afb . 
     FIG. 10B is a graphical illustration of the gain, output power P OUT  and power-added efficiency (PAE) as a function of the input power P IN  for the circuit illustrated in FIG. 10A. 
     FIG. 10C is a graphical illustration of the gain, output power P OUT  and normalized insertion phase as a function of the input power P IN  for the circuit illustrated in FIG. 10A. 
     FIG. 11A is a simplified schematic diagram of the pre-distortion driver circuit of FIG. 8 for a relatively low tuning voltage V afb . 
     FIG. 11B is a graphical illustration of the gain, output power P OUT  and power-added efficiency (PAE) as a function of the input power P IN  for the circuit illustrated in FIG. 11A. 
     FIG. 11C is a graphical illustration of the gain, output power P OUT , as well as the normalized insertion phase as a function of the input power P IN  for the circuit illustrated in FIG. 11A. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The power amplifier in accordance with the present invention is shown in simplified block diagram form in FIG. 1 and generally identified with the reference numeral 20. The linearized power amplifier 20 includes a pre-distortion active feedback driver amplifier 22 and a power amplifier 24, both with input and output terminals. The improved efficiency of the two-stage linearized power amplifier 20 is achieved by utilizing active feedback in the pre-distortion active feedback driver amplifier 22, which pre-distorts and amplifies the incoming RF signal RF in , which, in turn, is fed into the power amplifier 24. The pre-distortion active feedback driver amplifier 22 manipulates the amplitude and phase characteristics of the input RF signal RF in  to compensate for the amplitude and phase characteristics of the output power amplifier stage 24 in order to extend the linear output characteristics of the combined two-stage amplifier 20. For example, the driver amplifier 22 may be configured to have gain expansion and insertion phase decrease characteristics as the input power is increased, in order to compensate for the output power amplifier 24 having a characteristic of gain compression and insertion phase increase with input power, to provide a relatively higher linear output power capability and associated power-added efficiency. 
     As will be discussed in more detail below, active feedback is integrated into the driver amplifier 22 to achieve the pre-distortion pre-amp characteristics discussed above and provides several advantages over the relatively more complex pre-distortion circuits and linearization techniques known in the art. For example, the active feedback technique, in accordance with the present invention can be monolithically integrated without substantially increasing the chip size. Moreover, the two-stage linearized power amplifier 20 in accordance with the present invention incorporates RF feedback, which makes the topology inherently more stable, is easily self-biased, and can be electronically tuned in order to obtain optimum efficiency performance and can operate from low voltage supplies (i.e., 2 to 3 V bc  diode drops) to accommodate battery operated portable units. 
     A schematic diagram of the pre-distortion active feedback driver amplifier 22 is illustrated in FIG. 2. The pre-distortion active feedback driver amplifier 22 includes a bipolar transistor Q 1  with input and output matching networks 26 and 28 for input and output impedance matching, respectively, as well as an output bias network 30. The input matching network 26, output matching network 28, and output bias network 30 are well within the ordinary skill in the art. The RF signal RF in  is applied to the base of the bipolar power transistor Q 1  by way of the input matching network 26. The base of the bipolar power transistor Q 1  is biased by way of a current mirror which includes a plurality of resistors R bb1 , R bb6 , and R ref , as well as a transistor Q 6 . The transistor Q 6  is driven by a power-down emitter follower circuit, which includes a transistor Q 7  and a base resistor R b7 . The power-down emitter follower circuit is controlled by a voltage source V pd . A pair of bypass capacitors C byp1  and C byp2  are utilized on the DC supplies V pd  and V cc  to filter high-frequency noise. 
     An active feedback loop is provided by an active feedback transistor Q 4 , whose base is coupled to the collector of the power transistor Q 1  by way of a base tuning resistor R bt . The emitter of the active feedback transistor Q 4 , in turn, is coupled to the base of the power transistor Q 1  by way of a series R-C network, which includes a resistor R fb  and a capacitor C fb . The value of the resistor R fb  and capacitor C fb  as well as the base tuning resistor R bt  of the active feedback transistor Q 4 , set the RF feedback of the driver amplifier 22. 
     An emitter current bias for the active feedback transistor Q 4  is provided by a current source which includes a transistor Q 3 , which mirrors current from the transistor Q 1  base bias current mirror circuit, which includes a transistor Q 6  and a resistor R bb6 . The collector current of the active feedback transistor is biased by way of a second feedback loop which includes a biasing transistor Q 5 . In particular, the collector of the active feedback transistor Q 4  is directly connected to the collector of a transistor Q 5  for providing bias to the active feedback transistor Q 4 , as well as providing low frequency RF loading. The base of the transistor Q 5  is connected to the power supply V cc  by way of a base resistor R b5 . A current source which includes a transistor Q 2  sets the bias current I c5  of the transistor Q 5 . A compensation capacitor C cc , coupled to the collectors of the transistors Q 4  and Q 5 , provides low-pass filtering. The value of the compensation capacitor C cc  is chosen for optimum pre-distortion characteristics. 
     In operation, the transistors Q 4  and Q 5  are biased in or near saturation. In particular, if Q 4  is operating in saturation where its base-collector junction is strongly forward biased, the other transistor, Q 5 , will be operating in the forward active region near saturation but with its collector-base junction lightly forward biased. The pre-distortion characteristics rely on a degree of saturated bias of the active feedback transistor Q 4 , the value of the compensation capacitor C cc  as well as the DC coupling of the collector-connected transistors Q 4  and Q 5 . 
     FIG. 3A is a graphical illustration of the gain, output power P OUT  and power-added efficiency (PAE) of the pre-distortion active feedback driver amplifier 22 illustrated in FIG. 2 as a function of the input power of the RF signal RF in . Referring to FIG. 3A, curve 32 represents the gain of the pre-distortion active feedback driver amplifier 22 as a function of the input power of the RF signal RF in . The curve 34 represents the output power P OUT  of the pre-distortion active feedback driver amplifier 22 as a function of the input power P in , while the curve 36 represents the power-added efficiency (PAE) of the pre-distortion active feedback driver amplifier 22 as a function of the input power. Referring to the curve 32 in FIG. 3A, for increasing input power P in , the gain of the pre-distortion active feedback driver amplifier 22 increases and then rolls off at relatively high values of the input power P in  of the RF signal RF in . As illustrated in the curves 34 and 36, the output power P OUT , as well as the power-added efficiency (PAE), increases with increasing input power P in  and saturates at relatively high power levels. 
     FIG. 3B is a graphical illustration of the gain, output power P OUT  and normalized insertion phase of the pre-distortion active feedback driver amplifier 22 as a function of the input power P in . The curve 38 represents the gain of the pre-distortion active feedback driver amplifier 22 as a function of the input power. The curve 40 represents the output power of the pre-distortion active feedback driver amplifier 22 as a function of the input power P in  of the RF input signal RF in . The curves 38 and 40 are similar to the curves 32 and 34 illustrated in FIG. 3A. The curve 42 represents the normalized insertion phase of the pre-distortion active feedback driver amplifier 22 as a function of the input power P in . Referring to the curve 42, there is an input power region where the insertion phase of the pre-distortion active feedback driver amplifier 22 decreases with increasing levels of the input power P in  and subsequently increases with increasing input power levels P in  and begins to ramp back up at relatively higher power levels. As will be discussed in more detail below, the gain expansion and increasing insertion phase characteristics of the pre-distortion active feedback driver amplifier 22 act to compensate the output amplifier 24 gain compression characteristics. 
     FIG. 4 is a schematic diagram of a typical output power amplifier 24 suitable for use with the present invention, which includes a power transistor Q PA1 . The output of the pre-distortion active feedback driver amplifier 22 (FIG. 2) is coupled to the power amplifier 24 by way of an input matching network 44. In particular, the RF output from the output matching network 28 (FIG. 2) is directly coupled to the RF input terminal of the power amplifier 24. The RF input terminal R in  of the power amplifier 24, in turn, is connected to the input matching network 44 which, in turn, is connected to the base of the power transistor Q PA1 . The output RF out  of the power amplifier 24 is available at the emitter of the power transistor Q PA1  by way of a serially coupled output matching network 46. An input bias network 48, as well as an output bias network 50, are connected at the base and collector of the power transistor Q PA1 . A power-down control voltage V pd  is applied to the input bias network 48, typical of various known wireless portable handset systems. The input matching network 44, as well as the matching network 46, are utilized to optimize the performance of the power amplifier 24. These matching networks 44 and 46 are used to match the impedance of the circuits to which they are connected to optimize performance. For example, the input matching network 44 is configured to match the output impedance of the pre-distortion active feedback driver amplifier 22. The output matching network 46 is configured to match the input impedance of the circuit to which the power amplifier 24 is to be connected. The input bias network 48, as well as the output bias network 50, are used to bias the power transistor Q PA1  and force it to operate in its linear range. The input matching network 44, output matching network 46, input bias network 48, as well as the output bias network 50, are well within the ordinary skill of the art. 
     FIG. 5A is a graphical illustration of the gain, output power P out  and power-added efficiency (PAE) of the power amplifier 24 as a function of the input power (i.e., output of the pre-distortion active feedback driver amplifier 22). The curve 52 represents the gain of the power amplifier 24 as a function of the input power P in . As shown in FIG. 5A, the gain compresses for increasing levels of the input power P in  which, as mentioned above, is compensated by the gain characteristics of the pre-distortion active feedback driver amplifier 22 whose gain increases with increasing levels of the input power P in . The curves 54 and 56 illustrate that the output power P out , as well as the power-added efficiency (PAE) of the power amplifier 24 increase with increasing levels of the input power P in  and saturate at relatively high levels of the input power P in . 
     FIG. 5B is a graphical illustration of the gain, output power P out  and insertion phase of the power amplifier 24 as a function of the input power P in  for the power amplifier 24. The curves 58 and 60 represent the gain, as well as the output power P out , of the power amplifier 24 and are similar to the curves 52 and 54 illustrated in FIG. 5A. The curve 62 represents the insertion phase of the power amplifier 24 as a function of the input power P in . FIG. 5B illustrates that as the power amplifier 24 goes into compression, the insertion phase quickly ramps up and becomes non-linear with increasing levels of the input power P in . For example, at 1 dB of compression, the output power (P 1dB ) is 23 dBm, with an associated efficiency of 30 percent and an insertion phase of +3°. The 1 dB compression figure represents the upper limit of the linear power amplification just before the power amplifier 24 goes into saturation. 
     FIGS. 6A and 6B are graphical representations illustrating the combined performance of the pre-distortion active feedback driver amplifier 22, as well as the power amplifier 24 (i.e., two-stage power amplifier 20). FIG. 6A is a graphical illustration of the gain, output power P out , as well as power-added efficiency (PAE) of the combined two-stage linearized power amplifier 20. The curve 64 represents the gain, while the curve 66 represents the output power P out , of the two-stage linearized power amplifier 20 as a function of the input power P in . The curve 68 represents the power-added efficiency (PAE) of the combined two-stage linearized power amplifier 20 as a function of the input power P in . At 1 dB of compression (P 1dB ), FIG. 6 illustrates an efficiency of about 49 percent. Referring back to FIG. 5A, at 1 dB of compression (P 1dB ), the efficiency of the power amplifier 24 by itself was only 30 percent. As such, it is clear from FIG. 6A that the combined two-stage linearized power amplifier 20 at 1 dB of compression, is a 19 percent improvement in power-added efficiency (PAE). 
     FIG. 6B is a graphical illustration of the gain, output power P out , and normalized insertion phase as a function of the input power P in  of the two-stage linearized power amplifier 20, in accordance with the present invention. The curve 70 represents the gain, while the curve 72 represents the output power of the two-stage linearized power amplifier 20 as a function of the input power P in . The curves 70 and 72 are similar to the curves 64 and 66, respectively, in FIG. 6A. The curve 74 represents the normalized insertion phase of the two-stage linearized power amplifier 20 as a function of the input power P in . Referring to the curve 74 in FIG. 6B, the two-stage linearized power amplifier 20 is able to maintain phase linearity within 50 at the 1 dB compression point (P 1dB ). 
     Another important aspect of the invention is illustrated in FIGS. 7 and 8. In these embodiments, a pre-distortion active feedback driver amplifier 22 is provided with a voltage-controlled current source at the emitter of the transistors Q 5  or Q 4 , which can be adjusted for optimum power efficiency performance when combined with the power amplifier stage 24 to control the bias characteristics of the active feedback transistors Q 4  and Q 5 . With the exception of the active feedback bias tuning circuits, the balance of the schematic diagram for the pre-distortion active feedback driver amplifier 22 is essentially the same as illustrated in FIG. 2. As such, like components are identified with like reference numerals and are not discussed further. 
     Referring to FIG. 7, the pre-distortion active feedback driver amplifier 22 is provided with an active feedback bias tuning circuit 76, shown within the dashed box 76. The active feedback bias tuning circuit 76 is implemented as a current source, current mirror coupled to the emitter of the feedback transistor Q 4  in order to enable the active feedback bias current I fb  to be tuned, as well as its associated pre-distortion characteristics. The active feedback bias tuning circuit 76 includes a pair of current mirror transistors Q 3  and Q 8 , and a reference resistor R afb , used to set the bias current I fb  and an emitter follower transistor Q 9 . The emitter follower transistor Q 9  is coupled to an active feedback bias control voltage V afb  (i.e., tuning voltage) by way of the base resistor R b9 . The collector of the emitter follower transistor Q 9  is coupled to the supply voltage V cc  and bypassed with a bypass capacitor C byp3 . The supply voltage V afb  is likewise bypassed with a capacitor C byp4 . The bypass capacitors C byp3  and C byp4  provide filtering. As will be discussed below, varying the active feedback bias voltage V afb , the feedback bias current I fb  is adjusted which, in turn, adjusts the pre-distortion active feedback transistor Q 4 . 
     FIG. 8 is an altering embodiment of the pre-distortion active feedback driver amplifier 22, with a different active feedback bias tuning circuit, shown within the dashed box 78. In this embodiment, the active feedback bias tuning circuit 78 is implemented as a current source bias for the transistor Q 5 . In this embodiment, the active feedback bias tuning circuit 78 is implemented as a current source, current mirror coupled to the emitter of the transistor Q 5 . The active feedback bias tuning circuit 78 includes a mirror transistor Q 8 , a reference resistor R afb , which sets the current bias I c5  of the transistor Q 5 . The active feedback bias tuning circuit 78 also includes an emitter follower transistor Q 9  that is coupled to an active feedback bias control voltage V afb  by way of base resistor R b9 . The collector of the emitter follower transistor Q 9  coupled to the power supply voltage V cc  and bypassed with a bypass resistor C byp3 . The active feedback bias control voltage V afb  is similarly bypassed with a bypass capacitor C byp4 . 
     In this embodiment, varying the active feedback bias tuning voltage V afb  varies the current I c5  through the emitter of the transistor Q 9 , which can be adjusted to change the DC bias and impact the pre-distortion characteristics of the active feedback transistor Q 4 . More particularly, as the active feedback bias tuning voltage V afb  is increased, the current I c5  through the emitter of the transistor Q 5  is increased, which forces the base collector junction of the feedback transistor Q 4  to become more forward-biased, which biases the feedback transistor Q 4  more deeply into saturation, and thus changes the pre-distortion characteristics of the pre-distortion active feedback driver amplifier 22. 
     The effect of the active feedback bias tuning circuit 78 on the overall performance of the two-stage linearized power amplifier 20 is illustrated in FIGS. 9, 10 and 11. In particular, these FIGS. 9, 10 and 11 illustrate the performance of a two-stage linearized power amplifier 20 in which the pre-distortion active feedback driver amplifier 22 incorporates an active feedback bias tuning circuit 78, as illustrated in FIG. 8, for a relatively high, medium and low value of the active feedback bias voltage V afb . FIGS. 9A, 10A and 11A illustrate the effect of a high, medium and low active feedback bias voltage V afb  on the feedback transistor Q 4 . FIGS. 9B, 10B and 11B represent the gain, output power P out  and power-added efficiency (PAE) of the two-staged linearized power amplifier 20, incorporating the active feedback bias tuning circuit 78 as a function of the input power P in . The curves 80, 82 and 84 (FIGS. 9B, 10B and 11B) represent the gain, while the curves 86, 88 and 90 represent the output power, and the curves 92, 94 and 96 represent the power-added efficiency (PAE) of the two-stage linearized power amplifier 20, which incorporates the active feedback bias tuning circuit 78 as a function of the input power P in , for a high, medium and low value active feedback bias voltage V afb . FIGS. 9C, 10C and 11C illustrate the gain, output power P out , as well as insertion phase of the two-stage linearized power amplifier 20 incorporating an active feedback bias tuning circuit 78 as a function of the input power P in , for a high, medium and low value active feedback bias voltage V afb , respectively. The curves 98, 100 and 102 represent the gain, and are similar to the curves 80, 82 and 84, respectively, illustrated in FIGS. 9B, 10B and 11B. The curves 104, 106 and 108 (FIGS. 9C, 10C, 11C) represent the output power P out  and are similar to the curves 86, 88 and 90, respectively, illustrated in FIGS. 9B, 10B and 11B. The curves 110, 112 and 114 illustrate the insertion phase of the two-stage linearized power amplifier 20 which incorporates the active feedback bias tuning circuit 78 as a function of input power P in , for a relatively high, medium and low value of the active feedback bias voltage V afb . 
     Referring to FIGS. 9 through 11, as the active feedback bias voltage V afb  is decreased, the dc bias of the feedback transistor Q 4  is gradually moved out of deep saturation, as illustrated by the biasing current values and vectors illustrated in FIGS. 9A, 10A and 11A. As the feedback transistor Q 4  moves out of saturation, the power-added efficiency (PAE) increases only slightly from 48 percent (curve 92) to 50 percent (curve 96) at the 1 dB compression point P 1dB . However, curves 110, 112 and 114 indicate that the insertion phase degrades from only 6° to 8.5° at the 1 dB compression point P 1dB  as the active tuning voltage V afb  is decreased. 
     Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.