Abstract:
A multi-phase DC-DC converter architecture in which parameters including error signal gains and modulator gains are defined so as to balance multiple converter channel currents, irrespective of whether the converter channels are supplied with the same or different input voltages.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    The present application claims the benefit of U.S. Application Serial No. 60/368,894, filed Mar. 29, 2002, by M. Harris, entitled: “Method and Circuit for Scaling and Balancing Input and Output Currents in a Multi-Phase DC-DC Converter Using Different Input Voltages,” assigned to the assignee of the present application and the disclosure of which is incorporated herein. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates in general to DC-DC voltage converters, and is particularly directed to a multi-phase DC-DC converter architecture that is effective to balance multiple converter channel currents, irrespective of whether the converter channels are supplied with the same or different input voltages.  
         BACKGROUND OF THE INVENTION  
         [0003]    Electrical power for an integrated circuit, such as but not limited to a microprocessor chip of a personal computer, is typically supplied by one or more direct current (battery) power sources, such as a buck-mode, pulse width modulation (PWM) based, DC-DC converter of the type diagrammatically shown in FIG. 1. As shown therein, the converter has a control circuit  1  that supplies a synchronous PWM signal to a switching circuit driver  2 , for controlling the turn-on and turn-off of a pair of electronic power switching devices, to which a powered load is coupled. In the illustrated converter, the electronic power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device  3 , and a lower (or low side) power NFET device  4 , having their drain-source current flow paths connected in series between an input voltage (Vin) supply rail and ground (GND).  
           [0004]    The upper NFET device  3  is turned on and off by an upper gate switching signal UGATE applied to its gate from driver  2 , while the lower NFET device  4  is turned on and off by a lower gate switching signal LGATE supplied from driver  2 . A common node  5  between the two NFETs is coupled through an inductor  6  to a load reservoir capacitor  7  that is coupled to a reference voltage terminal (GND). The connection  8  between inductor  6  and capacitor  7  serves as an output node from which a desired (regulated) DC output voltage Vout is applied to a LOAD  9  (coupled to GND). The coupling impedance through the inductor is such that the output voltage is equal to the average value of the switched voltage except for some small ripple voltage.  
           [0005]    The output node connection  8  is also fed back via a feedback resistor  10  to error amplifier circuitry within PWM controller  1 . The error amplifier circuitry is used to regulate the converter&#39;s output DC voltage relative to a reference voltage supply value. In addition, the common node  5  between the controllably switched NFETs is coupled via a current sense resistor  11  to current-sensing circuitry within the controller  1 , in response to which the controller adjusts duty ratio of the PWM signal, as necessary, to maintain the converter&#39;s DC output within a prescribed set of parameters.  
           [0006]    Early computer circuits powered by such converters had operational voltages on the order of +/−5 VDC and drew only several amps of current. To realize improved performance, personal computers now employ relatively low operating voltages (on the order of 1.0 to 2.0 VDC), and may draw several tens and more amps of current. Because it is more economical to source such relatively large currents from multiple sources, power supply manufacturers now offer multi-phase DC-DC converters that can be driven by different voltage sources. In addition, if the power requirement of a particular circuit is so high that it cannot be supplied by only one DC source, the point-of-load regulator must obtain the needed power from more than one of the available DC sources. Thus, it is not uncommon for a DC-DC converter to deliver power to a computer motherboard by way of several distinct DC voltage sources including, for example, a 12 V source, a 5 V source, and a 3.3 V source. The current available from each DC sources is limited, so that the circuits on the computer&#39;s motherboard must adhere to a system power budget that limits the current drawn from each source.  
           [0007]    One example of a circuit having a high power requirement is a computer&#39;s graphics adapter card that uses a point-of-load regulator to convert 12 V and 3.3 V DC input voltages to a DC output voltage that is regulated to a precise level significantly less than 3.3 VDC in order to properly operate the computer&#39;s graphics processor. In this and other similar cases, the point-of-load DC-DC regulator must possess at least the following functions.  
           [0008]    First, it must regulate the DC output voltage to some level determined by a particular load. Secondly, it must regulate the DC output voltage to a precision (accuracy) dictated by a particular load. Third, it must deliver current from more than one parallel channel to a common load. Fourth, it has to balance, to a desired ratio, the currents in parallel channels sourcing a common load. Fifth, it must perform DC-DC conversion to a common load from multiple different input voltages using parallel channels. Sixth, it must regulate input current to some level dictated by the system&#39;s power budget.  
           [0009]    One circuit architecture for balancing channel currents in a multi-phase DC-DC converter is shown in FIG. 2, which corresponds to FIG. 2 of the U.S. Patent to M. Walters et al, U.S. Pat. No. 6,278,263, entitled: “Multi-Phase Converter With Balanced Currents,” assigned to the assignee of the present application and the disclosure of which is incorporated herein. In accordance with this architecture, multi-phase channel currents of a plurality of pulse width modulator (PWM) comparators (four of which are shown at  68 ,  70 ,  72  and  74 ) are appropriately balanced, by supplying a correction offset to a control signal output by an error amplifier  42 . The control signal has the proper sign and magnitude as to cause the output voltage to converge on a reference voltage REF, thus regulating the output voltage to the reference voltage. The error signal is common to the control circuitry for each channel i.  
           [0010]    Measurements of the current in each channel are weighted and summed together to produce a signal proportional to the average channel current. A voltage V ISENSEi  representative of the current in each channel is then subtracted from a signal V AVERAGE , which is proportional to the average current, to realize current-error signals that are proportional to the difference between each channel&#39;s current and the average channel current. The current error signals are combined with the control signal to produce a correction to the current in each channel. The correction is of sufficient magnitude to cause the current in each channel to converge on the average current.  
           [0011]    Now although the current balancing arrangement of FIG. 2 works well when each of the multi-phase converter channels employs the same DC input voltage, it is inadequate to balance the currents without modification when the channels&#39; DC sources have different voltage levels.  
         SUMMARY OF THE INVENTION  
         [0012]    In accordance with the present invention, this shortcoming is obviated by an augmentation of the multiphase DC-DC converter architecture of FIG. 2, that is effective to balance the various channel currents, irrespective of whether the channels&#39; DC sources supply the same or different voltage levels. Pursuant to a first embodiment, the error-signal gains of the respective channels are set equal to the same value and at very high values. With each of the gains set at a very high value, the difference between the currents in adjacent channels becomes very small, and converges on zero as the gain approaches infinity. A practical circuit implementation of this first embodiment involves incorporating the gains together with the difference nodes using an operational amplifier coupled in an integrating configuration for a respective channel.  
           [0013]    In a second embodiment, the gains of all the channels are set equal to one another. In addition, the modulator gains are set equal to each other. This may be accomplished by making the amplitudes of the sawtooth waveforms applied to the respective PWM comparators proportional to their input voltages.  
           [0014]    Pursuant to a third embodiment, rather than make the amplitudes of the sawtooth signals supplied to the respective PWM comparators proportional to input voltage, the outputs of the combining circuits that feed the PWM comparators are scaled by respective scaling circuits in inverse proportion to their associated modulator gains, to produce the same effect as the second embodiment. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    [0015]FIG. 1 diagrammatically illustrates the general architecture of a buck-mode, pulse width modulation (PWM) based, DC-DC converter;  
         [0016]    [0016]FIG. 2 corresponds to FIG. 2 of U.S. Pat. No. 6,278,263;  
         [0017]    [0017]FIG. 3 is a rearranged drawing of FIG. 2;  
         [0018]    [0018]FIG. 4 diagrammatically illustrates an augmentation of a subcomponent of an individual channel of the multi-phase architecture of FIGS. 2 and 3 in accordance with a first embodiment of the invention;  
         [0019]    [0019]FIG. 5 diagrammatically illustrates a modification of the multi-phase architecture of FIGS. 2 and 3 in accordance with a second embodiment of the invention; and  
         [0020]    [0020]FIG. 6 diagrammatically illustrates a modification of the multi-phase architecture of FIGS.  2  and  3  in accordance with a third embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0021]    In order to facilitate an appreciation of the present invention it is initially useful to examine the operation of the multi-phase converter circuit of FIG. 2. Consider the operation of the PWM comparator  68 , which generates the pulse that is used to drive a switch (FET) to connect the channel-1 input voltage through a coupling impedance to the output, as generally shown in FIG. 1 described above. The switch (FET) is closed when the voltage at its input  68   a  from subtraction circuit  58  is greater than the sawtooth voltage at input  68   b . The switch is otherwise open. As pointed out above, the coupling impedance is such that the output voltage is equal to the average value of the switched voltage except for a relatively small ripple voltage.  
         [0022]    The average value of the switched voltage is proportional to the control signal V EA  (the channel-1 input voltage), and is inversely proportional to the amplitude of the sawtooth voltage at the comparator input  68   b . This proportionality can be expressed as a gain block G shown in FIG. 3, which constitutes a redrawing of components of FIG. 2 together with the incorporation of the PWM comparators into respective PWM modulator components A 1 , A 2 , A 3  and A 4 , which are block representations of the switch mode PWM modulator components of FIG. 1. Each PWM modulator has a respective modulator gain A i  that effectively corresponds to the ratio of its associated input voltage Vin i  to the peak-to-peak excursion of its associated ramp or sawtooth waveform.  
         [0023]    In FIG. 3, the sense voltages V SENSE  are related to the channel currents by a transducer gain k, so that, for example, the voltage V SENSE,1  equals k times the current I 1 . An analysis of the steady-state current-balance error derived from FIG. 3 yields the following equation (1), in which error is expressed as the difference of currents of two of the channels, here channel-1 and channel-2. Equation (1) may be generalized to any two channel currents by simple substitution.  
           I   1 - I   2   ={V   EA   /k }{( G   2   −G   1 )/ G   2   G   1   }−{V   OUT   /k }{( A   2   G   2   −A   1   G   1 )/ A   1   G   1   A   2   G   2 }  (1)  
         [0024]    For most practical implementations of the circuit of FIGS. 2 and 3, the error-signal gains G 1 , G 2 , G 3 , G 4  are all equal. From equation (1) it can be seen that this is necessary in order to reduce the steady state error. If the error signal gains G 1 , G 2 , G 3 , and G 4  are all equal to the same value G, then equation (1) may be rewritten as the following equation (2):  
           I   1 - I   2   ={V   OUT   /k }{( A   1   −A   2 )/ GA   1   A   2 }  (2)  
         [0025]    Equation (2) reveals that the steady-state error is directly proportional to the differences between the modulator gains and inversely proportional to the error-signal gain.  
         [0026]    First Embodiment (FIG. 4)  
         [0027]    In accordance with a first embodiment of the invention, the error-signal gains of the respective channels (e.g., gains G 1 , G 2 , G 3 , and G 4  in the four channel architecture of FIGS. 2 and 3) are set equal to one another and are set to have very high values. With each of the gains at a very high value (e.g., on the order of 10,000 or more (practically infinite), the difference between I 1  and I 2  in equation (2) becomes very small. Namely, equation (2) shrinks to zero as G approaches infinity. A practical circuit implementation of this first embodiment involves incorporating the gains together with the difference nodes using an operational amplifier for a respective channel in an integrating configuration.  
         [0028]    [0028]FIG. 4 shows such a configuration for an individual channel (here, channel-1), wherein the sensed current representative voltage V SENSE,1  is coupled through a first input resistor  401  having a value R 1  to an inverting (−) input  411  of operational amplifier  410 . The average value of the sensed current representative voltage V SENSE,AVG  is coupled through a second input resistor  402 , also having a value R 1 , to an non-inverting (+) input  412  of operational amplifier  410 . The inverting input is couple to ground through a series circuit containing a resistor  403  having a value R 2  and a capacitor  404  having a value C. The output  413  of operational amplifier  410 , which produces the output voltage GV ER , is coupled to the inverting input  411  through a series circuit containing a resistor  406  having a value R 2  and a capacitor  407  of value C. The RC circuits set the circuit&#39;s frequency response. The circuit of FIG. 4 is implemented once for each difference node and gain block G of FIG. 3.  
         [0029]    Second Embodiment (FIG. 5)  
         [0030]    As described above, in the first embodiment of the invention, the error-signal gains G 1 , G 2 , G 3 , and G 4  in the four channel architecture of FIGS. 2 and 3 are equal to the same value. In accordance with a second embodiment of the invention, the gains of all the channels are set equal to one another. In addition, the modulator gains A 1 , A 2 , A 3 , and A 4  are set equal to each other. This may be readily achieved by making the amplitudes of the sawtooth waveforms applied to the second inputs  68   b ,  70   b ,  72   b  and  74   b  of the respective comparators  68 ,  70 ,  72  and  74  proportional to their associated input voltages. As circuits for generating a ramp voltage whose amplitude is proportional to input voltage are conventional, they will not be detailed here. Instead they are shown in block diagram form at  68 R,  70 R,  72 R and  74 R in FIG. 5. It may be noted that this is similar to a technique commonly referred to as feed-forward control wherein the modulator gains are adjusted in this fashion to cause a DC-DC converter to be insensitive to changes in input voltage. However, its use for the purpose of providing current balance in a multi-phase converter as described herein is new.  
         [0031]    Third Embodiment (FIG. 6)  
         [0032]    Pursuant to a third embodiment, shown in FIG. 6, which is a modification of the second embodiment, rather than make the amplitudes of the sawtooth inputs to the respective comparators proportional to input voltage, the outputs of the subtraction circuits  58 ,  60 ,  62  and  64  are coupled to the modulators through respective scaling circuits  59 ,  61 ,  63  and  65 . Each of these scaling circuits is operative to scale its input voltage inversely proportional to its associated modulator gain, or by (l/Ai), so as to produce the same effect as the second embodiment of FIG. 5.  
         [0033]    While I have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art. I therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.