Abstract:
There is provided an address counter and address counting method capable of enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external address or a previous internal address is inputted and further generating both of a path for the case a parity signal having a high state is inputted and that for the case the parity signal having a low state is provided. At the same time of producing the paths, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Moreover, an operation of latching the next address is terminated as soon as the parity signal is generated.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor memory device; and, more particularly, to an address counter and address counting method capable of enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external or a previous internal address is inputted and generating both of a path for the case a parity signal having a high state is inputted and that for the case the parity signal having a low state is provided at the same time of producing the parity signal to thereby immediately output the next internal address in response to the generation of the parity signal.  
         BACKGROUND OF THE INVENTION  
         [0002]    In general, existing DRAM, SRAM and flash memory devices employ a burst mode access function. Therefore, they need a circuit for counting addresses for the next data access operation inside the memory devices. As an operational speed of the memory devices goes faster, it is necessary to enhance an operational speed of the address counting circuit.  
           [0003]    Conventional address counting schemes can be classified into two methods. Referring to FIGS. 1 and 2, there are shown schematic flow charts of the conventional address counting methods.  
           [0004]    In FIG. 1, there is described a flow chart of one example of the conventional address counting method, which receives an external address in step S 11 , latches the external address in step S 12 , generates a first parity corresponding to a first address in step S 13  before outputting the first address in step S 14  and produces a second parity corresponding to a second address in step S 15  before outputting the second address in step S 16 .  
           [0005]    In FIG. 2, there is illustrated a flow chart of the other example of the conventional address counting method, which receives an external address in step S 21 , latches the external address in step S 22  at the same time of generating a first parity corresponding to a first address in step S 23 , outputs the first address in step S 24 , produces a second parity corresponding to a second address in step S 25  and, then, outputs the second address in step S 26 .  
           [0006]    Referring to FIG. 3, there is depicted a circuit diagram of a conventional address counter implemented as a unit block.  
           [0007]    A first NAND gate  31  receives and logically combines an external column address signal eyoz and an inverted control signal outputted from a first inverter I 31  that inverts a control signal seqx_intz determining a counting scheme. An output signal of the first NAND gate  31  is transferred to a first latch circuit  33  through a first transmission gate T 31 , which operates in response to an address latch command signal setz and an inverted address latch command signal setx.  
           [0008]    The first latch circuit  33  includes a second inverter I 32  and a third inverter I 33  that operates in response to a next address generating signal incz and an inverted next address generating signal incz when a corresponding parity signal is inputted, and latches the output signal of the first NAND gate  31 .  
           [0009]    An output signal of the first latch circuit  33  is inverted by a fourth inverter I 34 , which operates in response to the next address generating signal incx and the inverted next address generating signal incz when the parity signal is coupled, and, then, inputted to a second latch circuit  34 .  
           [0010]    The second latch circuit  34  consists of a fifth inverter I 35  and a sixth inverter I 36  that operates in response to the next address generating signal incx and the inverted next address generating signal incz when the parity signal is provided, and latches an output signal of the fourth inverter I 34 . Further, the second latch circuit  34  outputs the latched signal as a fist output signal onz.  
           [0011]    Moreover, the output signal of the first NAND gate  31  transferred through the first transmission gate T 31  is delivered to an output node of the second latch circuit  34  through a second transmission gate T 32  that operates in response to the next address generating signal incx and the inverted next address generating signal incz when the parity signal is inputted, without passing through the first and the second latch circuits  33  and  34 .  
           [0012]    Meanwhile, a second NAND gate  32  receives and logically combines the control signal seqx_intz and the external column address signal eyoz. An output signal of the second NAND gate  32  is provided to a third latch circuit  35  through a third transmission gate T 33  that operates responsive to the address latch command signal setz and the inverted address latch command signal setx.  
           [0013]    The third latch circuit  35  is composed of an eighth inverter I 38  and a ninth inverter I 39  and latches the output signal of the second NAND gate  32  transferred through the third transmission gate T 33 . A tenth inverter I 40  inverts an output signal of the third latch circuit  35  and outputs the inverted signal as a first selection signal sell. Moreover, the output signal of the third latch circuit  35  is produced as a second selection signal sel 2 .  
           [0014]    The output signal of the second latch circuit  34  is buffered by a seventh inverter I 37  and an eleventh inverter I 41  and, then, transferred through a fourth transmission gate T 34 . Further, the output signal of the second latch circuit  34  is inverted by the seventh inverter I 37  and, then, delivered through a fifth transmission gate T 35 .  
           [0015]    The fourth and the fifth transmission gates T 34  and T 35  inversely operate in response to the first and the second selection signals sell and sel 2 . As a result, a signal transmitted through the fourth or the fifth transmission gate T 34  or T 35  is inverted by a twelfth inverter I 42  and, then, outputted as a second output signal yacntz.  
           [0016]    The address counting method depicted in FIG. 1 shows a maximum operational speed of about 200 MHz while the other method explained in FIG. 2 accomplishes a maximum operational speed of about 250 MHz. Therefore, there is no problem in the operational speed so far. However, for the next generation DRAM or SRAM devices, there will be required a faster operational speed of about several hundred MHz, so that there needs to employ an address counter operating faster than the conventional address counters.  
         SUMMARY OF THE INVENTION  
         [0017]    It is, therefore, a primary object of the present invention to provide an address counter and address counting method capable of enhancing an operational speed.  
           [0018]    Another object of the present invention is to provide an address counter and address counting method having an operational speed applicable to the next generation memory devices.  
           [0019]    The present invention forms a path for outputting a corresponding output address as soon as an external or a previous internal address is inputted and generates both of a path for the case a parity signal having a high state is inputted and that for the case the parity signal having a low state is provided. At the same time of producing the two paths, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Further, an operation of latching the next address is also terminated as soon as the parity signal generated. That is, if a first address is generated, the next parity signal is produced and standing by ready without being controlled by an additional control signal to allow a second address to be instantly outputted when it is required. Therefore, a whole operational speed of the address counter only depends on a time required in outputting the parity signal and this time is about 1 ns, so that it is possible to achieve a maximum counting operation of about 1 GHz.  
           [0020]    In accordance with an aspect of the present invention, there is provided an address counter comprising a plurality of address counting blocks, wherein each address counting block includes:  
           [0021]    a first inverting unit for receiving and inverting an external address in response to a first control signal and an inverted first control signal;  
           [0022]    a second inverting unit for receiving and inverting a previous internal address in response to a second control signal and an inverted second control signal;  
           [0023]    a third inverting unit for inverting an inverted external address or an inverted previous internal address which is provided from the first or the second inverting unit to thereby output an output address;  
           [0024]    a latching unit for latching the inverted external address or the inverted previous internal address;  
           [0025]    a logic unit for generating a parity signal by logically combining an output signal of the latching unit and output signals of latching units of previous address counting blocks;  
           [0026]    a first transmission gate for providing the second inverting unit with a delayed output signal of the latching unit as the previous internal address in response to a previous parity signal and an inverted previous parity signal supplied from a preceding address counting block; and  
           [0027]    a second transmission gate for supplying the second inverting unit with an inverted delayed output signal of the latching unit as the previous internal address in response to the previous parity signal and the inverted previous parity signal, wherein the first and the second transmission gates inversely operate responsive to the previous parity signal and the inverted previous parity signal.  
           [0028]    In accordance with another aspect of the present invention, there is provided an address counting method comprising the steps of:  
           [0029]    (a) receiving an external address or a previous internal address and forming a first internal address path for the case a first parity signal having a high state is inputted and a second internal address path for the case the first parity signal having a low state is inputted at the same time of generating the first parity signal;  
           [0030]    (b) producing a current internal address by using the first or the second internal address path according to the state of the first parity signal at the same time of outputting a second parity signal;  
           [0031]    (c) if the next internal address is required, forming a third internal address path for the case the second parity signal having a high state is inputted and a fourth internal address path for the case the second parity signal having a low state is inputted by using the current internal address; and  
           [0032]    (d) generating the next internal address by using the third or the fourth internal address path according to the state of the second parity signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0033]    The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0034]    [0034]FIG. 1 is a schematic flow chart showing one example of a conventional address counting method;  
         [0035]    [0035]FIG. 2 is a schematic flow chart representing another example of the conventional address counting method;  
         [0036]    [0036]FIG. 3 provides a circuit diagram of a conventional address counter implemented as a unit block;  
         [0037]    [0037]FIG. 4 is a flow chart describing an address counting method in accordance with the present invention;  
         [0038]    [0038]FIG. 5 illustrates a circuit diagram of an address counter implemented as a unit block in accordance with the present invention;  
         [0039]    [0039]FIGS. 6A and 6B present a constitutional diagram of an address counter implemented for  11  addresses by connecting  11  numbers of unit blocks in accordance with an embodiment of the present invention; and  
         [0040]    [0040]FIG. 7 shows a simulation result of the address counter in FIGS. 6A and 6B. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0041]    Hereinafter, some preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.  
         [0042]    Referring to FIG. 4, there is shown a flow chart describing an address counting method in accordance with the present invention.  
         [0043]    If an external address or a previous internal address is inputted in step S 41 , there are formed a first address path for the case a first parity signal having a high state is inputted and that for the case the first parity signal having a low state is inputted in steps S 42  and S 43 , respectively. At the same time of performing steps S 42  and S 43 , the first parity signal is produced in step S 44 .  
         [0044]    According to a state of the first parity signal, in step S 45 , a first address is produced through the use of the previously formed first address path. Then, a second parity signal is generated in step S 46 .  
         [0045]    If the next address is required, there are formed a second address path for the case the second parity signal having a high state is inputted and that for the case the second parity signal having a low state is inputted in steps S 47  and S 48 , respectively, by using the first address. Then, a second address is outputted through the use of the second address path according to a state of the second parity signal in step S 49 .  
         [0046]    Referring to FIG. 5, there is illustrated a circuit diagram of an address counter implemented as a unit address counting block in accordance with the present invention.  
         [0047]    In FIG. 5, there are shown an external address input node for generating a first internal address and an internal address input node for producing the next internal addresses starting from a second internal address.  
         [0048]    A first inverter I 51  inverts an external address extadd in response to a signal caspcnt for use in generating the first internal address from the external address extadd and an inverted signal caspcntb of the signal caspcnt.  
         [0049]    A second inverter I 52  inverts a previous internal address intadd in response to a signal icaspcnt for producing the next internal address from the previous internal address intadd and an inverted signal icaspcntb of the signal icaspcnt.  
         [0050]    A third inverter I 53  inverts one of output signals from the first and the second inverters I 51  and I 52  to output the inverted signal as a column address signal yadd.  
         [0051]    Meanwhile, a latch circuit  51  consisting of a fourth inverter I 54  and a fifth inverter I 55  latches one of the output signals from the first and the second inverters I 51  and I 52  and provides a NAND gate  52  with the latched signal as an input signal a 0 .  
         [0052]    The NAND gate  52  logically combines several input signals, e.g., a 0 , a 1 , a 2  and a 3 , to thereby output a logically combined signal. The logically combined signal is provided to a tenth inverter I 60 , which, in turn, inverts the logically combined signal so as to output a parity signal ptyout.  
         [0053]    The latched signal outputted from the latch circuit  51  is inverted and delayed by passing through sixth to eighth inverters I 56  to I 58 . The inverted and delayed signal is inputted to the second inverter I 52  as the previous internal address intadd via a second transmission gate T 52  operating in response to a parity signal pty and a parity bar signal ptyb.  
         [0054]    Further, the latched signal outputted from the latch circuit  51  is delayed by passing through the sixth to ninth inverters I 56  to I 59  and the delayed signal is inputted to the second inverter I 52  as the previous internal address intadd via a first transmission gate T 51  operating in response to the parity signal pty and the parity bar signal ptyb.  
         [0055]    In the above, the first and the second transmission gates T 51  and T 52  inversely operate according to states of the parity signal pty and the parity bar signal ptyb. Therefore, if the parity signal pty has a low state, the signal delivered through the first transmission gate T 51  is inputted to the second inverter I 52  as the previous internal address intadd. On the other hand, if the parity signal pty has a high state, the signal transmitted through the second transmission gate T 52  is coupled to the second inverter I 52  as the previous internal address intadd. Although there is not shown in drawings, the parity bar signal ptyb is generated by logically combining an enable signal en and a parity input signal delivered from a previous address counting block by using a NAND gate and the parity signal pty is produced by inverting the parity bar signal ptyb.  
         [0056]    Referring to FIGS. 6A and 6B, there is presented a constitutional diagram of an address counter implemented for 11 numbers of address pins by connecting 11 numbers of address counting blocks  601  to  611  in accordance with an embodiment of the present invention.  
         [0057]    Hereinafter, the operation of the inventive address counter will be explained with reference to FIGS.  5  to  7 .  
         [0058]    At first, for the first address counting block  601 , if the signal caspcnt is inputted to generate a first internal address intadd 0  from an external address add 0 , the external address add 0  is simultaneously transferred to a path for producing a parity signal ptyout, a first output path for the case a parity signal pty has a high state and a second output path for the case the parity signal pty has a low state, wherein the internal address intadd 0  is outputted through the first or the second output path according to the state of the parity signal as shown in FIG. 5. The first internal address intadd 0  is coupled to the second inverter I 52  as a previous internal address so as to be used to output the next column address and the next internal address in response to the signals icaspcnt and icaspcntb. As described in FIGS. 6A and 6B, the parity signal ptyout outputted from the first address counting block  601  is provided to input nodes of transmission gates in the following address counting block  602  and, further, supplied to input nodes of NAND gates in the following three address counting blocks  602  to  604  to be used to determine parity signals ptyout of the address counting blocks  602  to  604  since a four input NAND gate is employed to produce the parity signal ptyout and, thus, the four address counting blocks, e.g.,  601  to  604 , construct one operational group. The address counting blocks  602  to  604  also operate in the same manner as in the first address counting block  601 . That is, the parity signal ptyout of the second address counting block  602  is provided to the address counting blocks  603  and  604  and that of the third address counting block  603  is supplied to the fourth address counting block  604  as illustrated in FIG. 6A.  
         [0059]    Further, according to this configuration, the fourth address counting block  604  plays a role as a first address counting block for the next operational group consisting of address counting blocks  604  to  607  and, as a result, the parity signal ptyout outputted from the fourth address counting block  604  is provided to the following address counting blocks  605  to  607 . Likewise, the above operational connection is applied to the rest of address counting blocks  608  to  611  as described in FIG. 6B.  
         [0060]    Referring back t FIG. 5, the seventh and the eighth inverters I 57  and I 58  are used to delay an internal address as much as about 1 ns to thereby keep timing with the parity signal pty provided from its previous address counting block to the input nodes of the transmission gates T 51  and T 52 . As a result, the internal address can be outputted as soon as the parity signal pty is coupled to the transmission gates T 51  and T 52  from the previous address counting block and, thus, a whole time required for the address counting operation only depends on the transmission time of the parity signal pty.  
         [0061]    That is, if the external address extadd is inputted to the address counter, the signal caspcnt is produced to deliver the external address extadd to inside of the address counter and, as a result, the external address is outputted as the column address yadd and, at the same time, latched in the latch circuit  51 . The latched address is transferred to the internal address node intadd via the inverters I 56  to I 59  and the transmission gate T 51  or T 52 . Then, if the signal icaspcnt is enabled, the transferred internal address is outputted the next column address and also latched in the latch circuit  51  for generating the next internal address. Therefore, there needs not any further control signal to produce the next internal address. However, at this time, if a pulse width of the signal icaspcnt is too long and, thus, continuously inputted during the internal address being latched after one internal address is outputted, the following internal addresses may be generated without break. Therefore, the pulse width of the signal caspcnt or the signal icaspcnt should be shorter than a whole loop time.  
         [0062]    Referring to FIG. 7, there is shown a simulation result of the address counter described in FIGS. 6A and 6B for a clock frequency of 700 MHz. It is noticed from the simulation result that the address counter normally operates at a frequency of 700 MHz. If there is found a more optimized condition, the address counter can operate at a frequency of 1 GHz.  
         [0063]    In accordance with the present invention, there is provided the address counter. Although there is shown only an address counter in memory devices as a circuit requiring a high-speed operation, the inventive high-speed circuit can be differently used in other devices such as ASIC.  
         [0064]    As described above, since the inventive address counter can accomplish a higher speed operation compared to the conventional address counter operating at a frequency ranging from 200 to 300 MHz, the present invention can implement a high-speed operation in DRAM, SRAM or flash memories. Further, since the address counting block of the inventive address counter is simpler than that of the conventional address counter and, thus, the whole configuration of the inventive address counter is also simpler than that of the conventional address counter, it is possible to reduce a whole layout area of the address counter. The use of the inventive address counter is not limited to the memory devices. For instance, the inventive counter can be applicable to ASICs requiring a faster operation than the memory devices.  
         [0065]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.