Abstract:
Disclosed is circuitry for operating a switch which sees high voltage swings across its source, gate, drain, and bulk terminals. The circuitry generates one or more bias voltages in proportion to an input voltage swing. The one or more bias voltages may be used to bias the gate and bulk terminals to provide reliable and improved turn OFF performance in the switch.

Description:
BACKGROUND 
       [0001]    Unless otherwise indicated, the foregoing is not admitted to be prior art to the claims recited herein and should not be construed as such. 
         [0002]    Radio frequency (RF) circuits typically require high power switching of passive devices for power control, multi-band tuning, and so on. RF applications (e.g., mobile communication devices and the like) often have space constraints that limit the amount of silicon area that is available to the designer. 
         [0003]    Operating a switch at high power exposes the switch to high voltage swings across its source, gate, drain, and bulk terminals. High voltage swings present a challenge in maintaining the switch in the OFF state, thus affecting high voltage switching reliability. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    With respect to the discussion to follow and in particular to the drawings, it is stressed that the particulars shown represent examples for purposes of illustrative discussion, and are presented in the cause of providing a description of principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show implementation details beyond what is needed for a fundamental understanding of the present disclosure. The discussion to follow, in conjunction with the drawings, make apparent to those of skill in the art how embodiments in accordance with the present disclosure may be practiced. In the accompanying drawings: 
           [0005]      FIG. 1  shows a schematic for a circuit in accordance with the present disclosure. 
           [0006]      FIG. 1A  shows a schematic for an alternative embodiment of a circuit in accordance with the present disclosure. 
           [0007]      FIG. 2  illustrates an example of a specific embodiments of a circuit of the present disclosure. 
           [0008]      FIG. 2A  illustrates an alternative embodiment of the circuit shown in  FIG. 2 . 
           [0009]      FIG. 3  illustrates an embodiments of an alternative circuit of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
         [0011]      FIG. 1  shows a high level block diagram of a circuit  100  for driving a load  10  in accordance with the present disclosure. The circuit  100  includes differential input terminals INP and INM, and output terminals OUT 1  and OUT 2 . The figure illustrates an example of input signals  12   a ,  12   b  that may be input to the circuit  100 . In the example shown, the input signals  12   a ,  12   b  are 180° out phase relative to each other. The peak-to-peak voltage swing may be 2V DD , about a center voltage of V DD  and peak voltages of 2V DD  and 0 volts. 
         [0012]    In some embodiments, the circuit  100  may an output circuit comprising first and second transistor devices M 1 , M 2  connected in series. In a particular embodiment, M 1  and M 2  are field effect transistors (FETs), and in particular PMOS type FET devices. However, it will be appreciated that in other embodiments M 1  and M 2  may be NMOS devices. Transistors M 1  and M 2  may be enhancement type transistors or depletion type transistors. 
         [0013]    In the embodiment shown in  FIG. 1 , the source terminal of M 1  and the drain terminal of M 2  have a common connection to a voltage source V DD . The input terminals INP, INM may be connected across transistors M 1  and M 2 . For example, input terminal INP may be connected to the drain terminal of M 1  and the input terminal INM may be connected to the source terminal of M 2 . 
         [0014]    The circuit  100  may include first and second inductive elements L to couple the input terminals INP, INM to the output terminals OUT 1 , OUT 2 . In the embodiment shown in  FIG. 1 , for example, each inductive element L may connect an input terminal INP, INM to a respective output terminal OUT 1 , OUT 2 . 
         [0015]    In accordance with the present disclosure, the circuit  100  may include a sampling circuit  102 . Inputs to the sampling circuit  102  may be connected to sense the input signals (e.g.,  12   a ,  12   b ). Inputs to the sampling circuit  102  may be connected to sense points  104 ,  106 , for example. In accordance with the present disclosure, the sense points  104 ,  106  may be any connection that allow the sampling circuit  102  to sense the input signals. Referring, for example, to  FIG. 1A , in general, the input terminals INP, INM may be coupled to the output by a general network  114 ,  116 , represented in the figure by impedances Z. The sampling circuit  102  may connect its inputs to sense points along signal paths in the network  114 ,  116  in electrical communication with the input terminals INP, INM. 
         [0016]    Returning to  FIG. 1 , the sampling circuit  102  may produce one or more voltages V G1 , V G2 , V B1 , V B2 . In some embodiments, the voltages V G1 , V G2 , V B1 , V B2  may be the same voltage; i.e., V G1 =V G2 =V B1 =V B2 . In other embodiments, V G1 , V G2 , V B1 , V B2  may be different voltages. In still other embodiments, some of the voltages V G1 , V G2 , V B1 , V B2  may be the same and some may different. 
         [0017]    In accordance with the present disclosure, the sampling  102  can generate voltages V G1 , V G2 , V B1 , V B2  that are proportional to the voltage swing V sig  at the input terminals INP, INM. In some embodiments, the levels of the voltages V G1 , V G2 , V B1 , V B2  may be produced in accordance with the following relationship: 
         [0000]      bias voltage=α× Vsig+k,  
 
         [0000]    where α is a real constant, 
         [0018]    k is a real constant, 
         [0019]    V sig  is the voltage swing (e.g., peak-to-peak value) at the input terminals, 
         [0020]    V DD  is a power rail voltage. 
         [0021]    In some embodiments, the voltages V G1  and V G2  may be connected to the gate terminals of M 1  and M 2 , respectively. Further in accordance with some embodiments, the voltages V B1  and V B2  may be connected to the bulk terminals of M 1  and M 2 , respectively. The term “bulk terminal” can be variously referred to as the body terminal, base terminal, substrate terminal, the “fourth” terminal, and so on. 
         [0022]    Refer now to  FIG. 2  for a description of a particular circuit embodiment in accordance with the present disclosure. In the particular embodiment shown in  FIG. 2 , the circuit  200  includes a sampling circuit  202  that has an output  212  connected to the gate terminals G (via resistors R G ) and bulk terminals B (via resistors R B ) of transistors M 1  and M 2 . Inputs to the sampling circuit  202  are connected to sense points  204  and  206 .  FIG. 2A  shows an example of a circuit  200 ′ where the inputs of sampling circuit  202  are connected directly to the input terminals INP, INM. 
         [0023]    Returning to  FIG. 2 , in some embodiments, the sampling circuit  202  may be a full wave rectifier circuit. The input signals  12   a ,  12   b  can be full-wave rectified by the sampling circuit  202  to produce output waveform  214  shown in  FIG. 2 . As is known by those of ordinary skill in the art, the equivalent DC level V DC  of the output waveform  214  is: 
         [0000]    
       
         
           
             
               V 
               DC 
             
             = 
             
               
                 
                   2 
                    
                   
                       
                   
                    
                   
                     V 
                     peak 
                   
                 
                 π 
               
               . 
             
           
         
       
     
         [0000]    In the embodiment shown in  FIG. 2 , V peak =(2V DD −V DD )=V DD . The computed equivalent DC level V DC  is therefore 0.64V DD . However, the output is DC shifted by V DD , and so the actual V DC  is (V DD +0.64V DD ). 
         [0024]    In accordance with the present disclosure, the output  212  may be provided to the gate terminals G and bulk terminals B of transistors M 1 , M 2  to bias the gate and bulk terminals, for example, using resistors R G  and R B . Accordingly, the gate terminals G and bulk terminals B of transistors M 1  and M 2  can be biased at a voltage level (V DD +0.64V DD ). Consequently, for transistor M 1 , the potential at gate terminal G and the potential at bulk terminal B will always be 0.64V DD  above the potential at the drain terminal D of M 1 . This ensures proper reverse biasing of the bulk diode and turn OFF of M 1 . Similarly, the potential at gate terminal G and the potential at bulk terminal B of transistor M 2  will always be 0.64V DD  above the potential at the source terminal S of M 2  to ensure proper reverse biasing of the bulk diode and turn OFF of M 2 . 
         [0025]    Circuits in accordance with the present disclosure ensure reliability as the voltage across any two terminals in the OFF mode is less than V DD . Circuits in accordance with the present disclosure require fewer switches than conventional solutions to achieve the same, or better, turn OFF performance. Since the gate and bulk are consistently maintained at a higher voltage level than the source/drain, switches used in circuits according to the present disclosure exhibit better distortion performance in the OFF state than when used in conventional solutions. 
         [0026]    As shown in  FIG. 2 , in some embodiments, the sampling circuit  202  comprises a full wave rectifier. It will be appreciated that in other embodiments, sampling circuit  202  may comprise alternative circuitry. For example, the sampling circuit  202  may comprise a peak detection circuit. In still other embodiments, the sampling circuit may comprise a self-mixing local oscillator design, and so on. The designs of these circuits are known by those of ordinary skill in the art. In some embodiments, depending on where the inputs are sensed, the sampling circuit  202  may include amplification circuitry in order to generate output having a suitable level. Generally, as explained in connection with  FIG. 1 , the sampling circuit  102  may be operable to provide one or more output voltages that are proportional to the voltage swing at the input terminals. 
         [0027]      FIG. 3  illustrates another circuit embodiment in accordance with the present disclosure. In some embodiments, a circuit  300  may comprise a single transistor device M. The circuit behavior of circuit  300  is substantially the same as explained in connection with circuit  200  in  FIG. 2 . The sampling circuit  302  may include a full wave rectifier, a peak detector, a self-mixing local oscillator, and the like. In an embodiment, where sampling circuit  312  comprises a full wave rectifier, the output wave form  314  has an equivalent DC level V DC  that can be used to bias the gate terminal G and bulk terminal B of transistor M, as explained above. 
         [0028]    The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.