Abstract:
A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Taiwan patent application No. 104120067, filed on Jun. 23, 2015, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention generally related to a semiconductor structure and a method of making the same. More particularly, the invention related to a method of fabricating a high-k metal gate semiconductor device. 
         [0004]    2. Description of the Prior Art 
         [0005]    As the size of the integrated circuit devices continues to scale down, the polysilicon gate and the silicon dioxide insulating layer of a metal-oxide-semiconductor field effect transistor (MOSFET) structure have been confronted with the physical limits of the material itself. To meet the demands of scalability, it is necessary to incorporate high-k metal gate (HK/MG) process. 
         [0006]    Today, two main integration options remain: gate-first (often referred to as MIPS, metal inserted poly-silicon) and gate-last (also called RMG, replacement metal gate). The terminology “first” and “last” refers to whether the metal electrode is deposited before or after the high temperature activation anneal of the flow. The replacement metal gate (RMG) process flow allows the use of aluminum as a conductor material. 
         [0007]    In conventional HK/MG process, the dummy poly silicon gate line is segmented (also called poly cut) before the source/drain epitaxial growth process. As a result, the epitaxial extrusion defect is very possible to occur at the distal ends of the dummy poly silicon gate segments, which impacts the process yield. Therefore, there is a need in this technical field to provide an improved semiconductor structure and manufacturing process to overcome the deficiencies described hereinabove. 
       SUMMARY OF THE INVENTION 
       [0008]    This invention provides an improved semiconductor structure and manufacturing method to overcome the deficiencies of the prior art described hereinabove. The dummy gate line is segmented after the source/drain epitaxial growth and the interlayer dielectric (ILD) planarization process. 
         [0009]    According to one embodiment of the invention, a method of making a semiconductor device is disclosed. First, a substrate having a fin structure thereon is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on either side of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to thereby reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separated dummy gates. 
         [0010]    According another embodiment of the invention, a semiconductor device structure includes a substrate, a first gate structure comprising a first distal end, and a second gate structure spaced apart from the first gate structure and aligned with the first gate structure. The second gate structure comprises a second distal end facing the first distal end. A cut slot is disposed between the first distal end and the second distal end. A liner layer is disposed on interior surface of the cut slot. A dielectric layer is disposed on the liner layer. 
         [0011]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings: 
           [0013]      FIGS. 1-11  illustrate a process of fabricating a semiconductor device according one embodiment of the invention, wherein: 
           [0014]      FIGS. 1-5  are schematic plan views showing partial layout of the semiconductor device during the manufacturing process; 
           [0015]      FIG. 1A ,  FIG. 2A ,  FIG. 3A ,  FIG. 4A  and  FIG. 5A  are cross-sectional views taken along line I-I′ in  FIG. 1  to  FIG. 5 , respectively; 
           [0016]      FIG. 2B ,  FIG. 3B ,  FIG. 4B  and  FIG. 5B  are cross-sectional views taken along line II-II′ in  FIG. 2  to  FIG. 5 , respectively; 
           [0017]      FIG. 6  to  FIG. 11  are cross-sectional views illustrating the subsequent steps as taken along line II-II′ in  FIG. 2  to  FIG. 5 ; and 
           [0018]      FIG. 12  is a schematic plan view showing the semiconductor device according to the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration of specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
         [0020]    According to one embodiment of the invention, an exemplary method of fabricating a Fin Field-Effect-Transistor (FinFET) device is provided. One major feature of this invention is that the poly cut process is performed after the source/drain epitaxial growth and the interlayer dielectric (ILD) planarization process, thereby avoiding epitaxial extrusion defects that occurs in the prior art processes. 
         [0021]    Please refer to  FIG. 1  to  FIG. 11 , which illustrate an exemplary process of fabricating a semiconductor device according to one embodiment of the invention.  FIG. 1  to  FIG. 5  are schematic plan views showing a portion of the semiconductor device during the fabrication process.  FIG. 1A ,  FIG. 2A ,  FIG. 3A ,  FIG. 4A  and  FIG. 5A  are cross-sectional views taken along line I-I′ in  FIG. 1  to  FIG. 5 , respectively.  FIG. 2B ,  FIG. 3B ,  FIG. 4B  and  FIG. 5B  are cross-sectional views taken along line II-II′ in  FIG. 2  to  FIG. 5 , respectively.  FIG. 6  to  FIG. 11  are cross-sectional views illustrating the subsequent steps as taken along line II-II′ in  FIG. 2  to  FIG. 5 . 
         [0022]    First, as shown in  FIG. 1 , a substrate  110  is provided. For example, the substrate  110  may be a silicon substrate or any other suitable semiconductor substrates. A plurality of fin structures  112  is then formed in the substrate  110 . For example, to form the fin structures  112 , a hard mask (not shown) is formed on the substrate  110 . The hard mask is patterned to define the regions corresponding to the fin structures to be formed. Subsequently, an etching process is performed to form the fin structures  112 . An isolation structure  114  is then formed between these fin structures  112 . 
         [0023]    According to one embodiment, after forming the fin structures  112 , the hard mask (not shown) may be removed, and a tri-gate MOSFET may be formed in the following process. The tri-gate MOSFET has three contacting interfaces (two sidewalls and one top surface) between the fin structure  112  and the dielectric layer formed in a later stage. In comparison with the conventional planar field effect transistor at the same channel length, the tri-gate MOSFET using the three contacting interface as the carrier flow channel, and advantageously, can provide wider channel width, making it possible to have doubled drain driving current under the same driving voltage. 
         [0024]    In another embodiment of the invention, the hard mask (not shown) is kept to construct another kind of multi-gate MOSFET in the following process, which also has fin structure, known as Fin Field-Effect-Transistor (FinFET). The hard mask (not shown) covers the top surfaces of the fin structures. Therefore, the FinFET only has two contacting interfaces between the fin structure  112  and the dielectric layer formed in a later stage. 
         [0025]    As described hereinabove, other kinds of semiconductor substrates may be employed in this invention. In another embodiment of the invention, for example, a silicon-on-insulator (SOI) substrate (not shown) may be provided. By performing photolithography and etching processes, the single crystalline silicon layer of the SOI substrate (not shown) is etched until the underlying oxide layer is exposed, thereby forming fin structures on the SOI substrate. 
         [0026]    For the sake of clarity, only four fin structures are shown in the figures. However, it is understood that single fin structure or multiple (more than four) fin structures are also applicable to other embodiments. 
         [0027]    After the fin structures  112  and the isolation structures  114  are formed, at least two parallel and continuous dummy gate lines  120  are formed. The parallel and continuous dummy gate lines  120  traverse the fin structures  112  and isolation structures  114 . The parallel and continuous dummy gate lines  120  stride across the fin structures  112 . For the sake of simplicity, only two dummy gate lines  120  are shown in the figures. But the invention is not limited thereto. To form the dummy gate lines  120 , for example, a gate material layer (not shown) is deposited on the fin structures  112  and the substrate  110  in a blanket manner. After that, a hard mask (not shown) is formed on the gate material layer and then patterned by photolithography process to define the regions where the dummy gate lines  120  are to be formed in the gate material layer. Then, through the following etching process, the pattern of the hard mask is transferred to the gate material layer, thereby forming the dummy gate lines  120 . The hard mask is then removed. 
         [0028]    According to the illustrated embodiment, the aforesaid gate material layer may comprise amorphous silicon, but not limited thereto. In other embodiments, for example, the gate material layer may comprise polysilicon or the like. Each of the dummy gate lines  120  may comprise a stack structure composed of a gate dielectric layer  121 , a sacrificial gate  122 , a lining layer  123 , and a cap layer  124 , but not limited thereto. According to the illustrated embodiment, the sacrificial gate  122  may comprise polysilicon, the lining layer  123  may comprise silicon nitride, and the cap layer  124  may comprise silicon oxide, but not limited thereto. 
         [0029]    Please refer to  FIG. 2 ,  FIG. 2A  and  FIG. 2B . A lightly doped drain (LDD) process may be carried out to form an LDD region (not shown) in the fin structures  112  on either side of each of the dummy gate lines  120 . An epitaxial process is then performed to form an epitaxial layer  162  on the fin structures  112  on either side of each of the dummy gate lines  120 . The epitaxial layer  162  may comprise, for example, SiGe for PMOS transistors and SiP for NMOS transistors, but not limited thereto. 
         [0030]    Subsequently, a spacer  150  is formed on a sidewall of each of the dummy gate lines  120 . For example, the spacer  150  may comprise a SiN spacer, but not limited thereto. Subsequently, a source/drain (S/D) doping process is carried out to forma source/drain (S/D) region  160  in the fin structures  112  on either side of each of the dummy gate lines  120 . A contact etching stop layer (CESL)  152  is then conformally deposited on the dummy gate lines  120  and the S/D regions  160 . The contact etching stop layer (CESL) may comprise a SiN layer, but not limited thereto. 
         [0031]    As shown in  FIG. 3 ,  FIG. 3A  and  FIG. 3B , a chemical vapor deposition (CVD) process, e.g. flowable CVD (FCVD), is performed to blanket deposit an interlayer dielectric layer (ILD)  180 , such as a silicon oxide layer. The ILD  180  fills up the spaces between the dummy gate lines  120 . The ILD  180  also covers the dummy gate lines  120 . 
         [0032]    As shown in  FIG. 4 ,  FIG. 4A  and  FIG. 4B , a chemical mechanical planarization (CMP) process is performed to remove a portion of the ILD  180  and the entire cap layer  124 . After the CMP process is complete, the top surface of the ILD  180  is substantially flush with the lining layer  123  of each of the dummy gate lines  120 . 
         [0033]    As shown in  FIG. 5 ,  FIG. 5A  and  FIG. 5B , a photoresist pattern  200  is then formed on the ILD  180  and the dummy gate lines  120 . The photoresist pattern  200  includes openings  200   a  which are the regions where each of the dummy gate lines  120  to be discontinued or cut. The allocation of the openings  200   a  in the figures is for illustration purposes only. Using the photoresist pattern  200  as an etching hard mask, an etching process, e.g. dry etching process, is performed to selectively remove the exposed lining layer  123  and the sacrificial gate  122  through the openings  200   a,  thereby forming openings  210 . The openings  210  are also called “cut slots”. 
         [0034]    The steps shown in  FIG. 5 ,  FIG. 5A  and  FIG. 5B  are also called segmenting of dummy gate line or “poly cut”. After the poly cut, each of the originally continuous dummy gate lines  120  is cut into a plurality of discontinuous segments of dummy gate pattern. According to the illustrated embodiment, the aforesaid etching process selectively removes the exposed lining layer  123  and the sacrificial gate  122  through the opening  200   a,  but leaves the spacer  150  intact in the opening  200   a.    
         [0035]      FIG. 6  to  FIG. 11  illustrate the subsequent steps of making the semiconductor device according to the embodiment, where  FIG. 6  to  FIG. 11  are the cross-sectional views as taken along line II-II′ in  FIG. 2  to  FIG. 5 . As shown in  FIG. 6 , the remaining photoresist pattern  200  is removed. Optionally, a liner  260  may be conformally deposited on the interior surface of the opening  210 . The liner  260  may comprise SiN, SiON, or SiO 2 . According to the illustrated embodiment, the liner  260  does not fill up the opening  210 . The liner  260  may be formed by atomic layer deposition (ALD) process, but not limited thereto. In another embodiment, for example, the liner  260  may fill up the opening  210 . Subsequently, a dielectric layer  280  is deposited on the liner  260 . According to the illustrated embodiment, the dielectric layer  280  fills up the opening  210 . The dielectric layer  280  may comprise silicon oxide and may be formed by FCVD process. 
         [0036]    As shown in  FIG. 7 , a CMP process is then performed to polish away a portion of the dielectric layer  280 . The liner  260  outside the opening  210  is removed, thereby exposing the top surface of the ILD  180 . At this point, the top surface of the ILD  180  is substantially flush with the liner layer  123  of the dummy gate line  120 . 
         [0037]    As shown in  FIG. 8 , an optional recess etching process, e.g. SiConi™ etch process, may be carried out to remove a predetermined thickness of the ILD  180  and the dielectric layer  280 , thereby revealing the upper portion of the dummy gate line  120  and the upper portion of the spacer  150 /CESL  152 /liner  260 . 
         [0038]    As shown in  FIG. 9 , an optional high-density plasma chemical vapor deposition (HDP CVD) process is performed to deposit an HDP oxide layer  380  in a blanket manner. The HDP oxide layer  380  covers the upper portion of the dummy gate line  120  protruding from the ILD  180 . The HDP oxide layer  380  also fills into the opening  210 . 
         [0039]    As shown in  FIG. 10 , another CMP process is carried out to polish away a portion of the HDP oxide layer  380  and the liner layer  123  on the dummy gate line  120 , thereby exposing the top surface of the sacrificial gate  122 . At this point, the opening  210  is collectively filled up with the dielectric layer  280  and the HDP oxide layer  380 , and surrounded by the liner  260 , thereby forming an isolation plug structure  580 . The liner  260  prevents the filling material, i.e. the dielectric layer  280  and the HDP oxide layer  380 , from direct contact with the spacer  150 . 
         [0040]    As shown in  FIG. 11 , the sacrificial gate  122  and the gate dielectric  121  are removed, thereby forming a plurality of discontinuous gate trenches. These discontinuous gate trenches are separated from one another by the isolation plug structure  580 . Subsequently, a high-k dielectric layer  421  and a replacement metal gate  422  are formed in these gate trenches. 
         [0041]    The high-k dielectric layer  421  may be composed of a material selected from the group including hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), or barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), etc. 
         [0042]    The replacement metal gate  422  may comprise, from bottom to top, a bottom barrier layer, a metal layer with desired work function, a top barrier layer and a main conducting layer. The bottom barrier layer may comprise a single or composite layer comprising tantalum nitride (TaN) or titanium nitride (TiN), etc. The metal layer may comprise a single or a composite layer with desired work function which meets the transistor&#39;s requirement. The metal layer may be composed of a material selected from the group including titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl), aluminum titanium nitride (TiAlN), etc. Similarly, the top barrier layer may comprise a single or composite layer comprising tantalum nitride (TaN) or titanium nitride (TiN), etc. The main conducting layer may comprise aluminum, tungsten, titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or those material with low resistance. 
         [0043]      FIG. 12  shows the plan view of the semiconductor device  10  according to one embodiment of the present invention. The semiconductor device  10  comprises a substrate  110 . A first gate structure  420   a  is disposed on the substrate  110 . The first gate structure  420   a  comprises a first distal end  4202 . A second gate structure  420   b  is disposed on the substrate  110 , which is spaced apart from the first gate structure  420   a  and aligned with the first gate structure  420   a.  The second gate structure  420   b  comprises a second distal end  4204  facing the first distal end  4202 . A cut slot  210  is disposed between the first distal end  4202  and the second distal end  4204 . A liner layer  260  is disposed on interior surface of the cut slot  210 . A HDP silicon oxide layer  380  is disposed on the liner layer  260 . The HDP silicon oxide layer  380  fills into the cut slot  210 . 
         [0044]    This invention provides an improved semiconductor structure and manufacturing process, which segmenting the dummy gate lines after the source/drain epitaxial growth and interlayer dielectric (ILD) planarization process, therefore the epitaxial extrusion problem occurring at the distal end of the poly silicon gate in the prior art can be avoided. 
         [0045]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.