Abstract:
A boost inverter includes a first capacitor for connection in parallel with a dc supply voltage; a second capacitor connected in series with the first capacitor; an energy transfer path including a transfer capacitor and switches connected to the transfer capacitor for cyclically transferring energy from the first capacitor to the transfer capacitor and then from the transfer capacitor to the second capacitor; a multilevel inverter circuit connected in parallel with the series combination of the first and second capacitors, the inverter having at least one phase output for connection to an electric motor; and a PWM controller that activates the energy transfer path when a desired peak-to-peak output voltage exceeds the dc supply voltage and deactivates the energy transfer means when the desired peak-to-peak output voltage is less than the dc supply voltage.

Description:
This application claims the benefits of U.S. Provisional Application No. 61/285,612, filed Dec. 11, 2009. 
    
    
     FIELD OF THE INVENTION 
     The invention relates to the art of switch-mode dc-to-ac inverters, and more particularly to a PWM inverter capable of supplying an output voltage higher than a dc supply voltage. 
     BACKGROUND OF THE INVENTION 
     Electric and/or hybrid internal combustion engine (ICE) and electric vehicles can utilize relatively large motors. For example, an electric-only vehicle may be powered by a 100 kilowatt electric motor, driven off of a 300 V battery pack. 
     At such power ratings, it is desirable to minimize the magnitude of current flowing through the inverter and electric motor to reduce I 2 R power losses and reduce the size of wires and their connectors. Lower current flows can also enable the electric motor to be made smaller and have less heat loss. However, this objective must be balanced against the voltage that the battery provides and the breakdown limitations of the inverter switches. Practical electric vehicle batteries have voltage and current limitations associated therewith as the battery can only handle a certain state of charge. And switches with high breakdown voltages tend to cost more. 
     The efficiency of the inverter is also a prime design consideration. Multi-level inverters, which utilize an array of switching devices in series to perform the power conversion in a small increase of voltage steps by synthesizing a staircase voltage from several levels of series DC capacitor voltages connected in parallel with a power source, are known in the art. The multi-level inverter has lower dv/dt stresses on the switching devices in comparison to a conventional PWM inverter due to smaller voltage increments and thus can utilize smaller rated semiconductor devices. The multi-level inverter also features a better output voltage in terms of less distortion, lower harmonic content and lower switching losses in comparison to a conventional full bridge PWM inverter. See for example Mailah et. al, “Neutral-Point-Clamped Mutlilevel Inverter Using Space Vector Modulation”, ISSN 1450-216X Vol. 28, No. 1 (2009), pp. 82-91, EuroJournals Publishing, Inc. 
     One well-known neutral-point-clamped (NPC) PWM inverter is described by Nabae et al., “A New Neutral-Point-Clamped PWM Inverter”, IEEE Transactions on Industry Applications, Vol. 1A-17, No. 5, September/October 1981 and reproduced here as  FIG. 1A . Discussing only one leg, in this inverter S 11 , S 14  are the main transistors that act as PWM switches coupling load phase A to the positive and negative bus of the power source E d . S 12 , S 13  are auxiliary transistors that, together with diodes D 11 , D 12 , clamp the output terminal (A) to the neutral point potential N. The auxiliary transistors S 13 , S 12  are driven complementary to the main transistors S 11 , S 14 , respectively.  FIG. 1B  shows the drive signals for the transistors, which may be provided utilizing conventional PWM techniques, such as by comparing a sinusoidal control voltage against a higher frequency triangular switching reference signal.  FIG. 1C  shows the output voltage waveforms for the inverter. 
     It would be desirable to utilize an inverter topology such as the NPC PWM inverter to drive an electric motor at a much higher voltage than that provided by the battery. And in such a use, it would be desirable to operate the inverter to minimize switching losses. 
     SUMMARY OF THE INVENTION 
     According to one broad aspect of the invention a boost inverter is provided. The boost inverter includes a first capacitor for connection in parallel with a dc supply voltage; a second capacitor connected in series with the first capacitor; energy transfer means including a transfer capacitor and switches connected to the transfer capacitor for cyclically transferring energy from the first capacitor to the transfer capacitor and then from the transfer capacitor to the second capacitor; a multilevel inverter circuit connected in parallel with the series combination of the first and second capacitors, the inverter having at least one phase output for connection to an electric motor; and a PWM controller that activates the energy transfer means when a desired peak-to-peak output voltage exceeds the dc supply voltage and deactivates the energy transfer means when the desired peak-to-peak output voltage is less than the dc supply voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other aspects of the invention will be more readily appreciated having reference to the drawings, wherein: 
         FIGS. 1A ,  1 B and  1 C are circuit and timing diagrams of a prior art inverter; 
         FIG. 2  is a circuit diagram of a boost multilevel inverter circuit according to a preferred embodiment which can supply a PWM voltage to drive an electric motor with a peak to peak voltage much higher than that provided by a dc source; 
         FIGS. 3A ,  3 B,  3 C and  3 D are circuit diagrams of a boost circuit shown in  FIG. 1  at various points in a switching cycle; 
         FIG. 4  is a graph illustrating changes in current and voltage over the switching cycle of the boost circuit; 
         FIG. 5  is a timing diagram of the switching cycle; 
         FIG. 6  is a schematic block diagram of a PWM controller; 
         FIG. 7A  is a schematic diagram showing the control methodology for the boost multilevel inverter circuit in a first mode of operation for driving an electric motor utilizing a peak to peak voltage less than the dc supply voltage; and 
         FIG. 7B  is a schematic diagram showing the control methodology for the boost multilevel inverter circuit in a second mode of operation for driving an electric motor utilizing a peak to peak voltage higher than the dc supply voltage. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  shows the topology of a circuit  10  according to a preferred embodiment invention which includes a voltage doubler  14  connected between a battery  12  and an inverter  16 . As described in greater detail below, the voltage doubler  14  selectively is capable of supplying the inverter  16  with a voltage approximately twice the voltage V bat  of the battery  12 . And unlike the prior art NPC PWM inverter, inverter  16  is selectively controlled in one of two modes either as a conventional PWM inverter or as a multi-level clamped inverter depending on power requirements as discussed in greater detail below. 
     More particularly, the voltage doubler  14  includes a first capacitor C 1  connected in parallel with the battery  12 . A second capacitor C 2  is connected in series with C 1  with the positive battery terminal connected to node M between C 1  and C 2 . An energy transfer path includes switches S VD1 , S VD2  disposed opposite C 2 , switches S VD3 , S VD4  disposed opposite C 1  as shown. The junction between S VD2  and S VD3  is tied to node M. An energy transfer capacitor C T  has a first end connected between switches S VD1 , S VD2  and a second end connected between switches S VD3 , S VD4 . A smoothing inductor L S  is serially connected to the energy transfer capacitor C T . 
     The illustrated inverter  16  is designed to power a 3-phase motor and thus has three parallel switching legs  20 ,  22 ,  24 , each leg having four serially arranged switches S 1 , S 2 , S 3 , and S 4 . Each leg also features clamping diodes D 1 , D 2  connected to node M and between the first and second switches S 1 , S 2  and the third and fourth switches S 3 , S 4 , respectively. The phase output (A, B, or C) of each leg is located between switches S 2  and S 3 . 
     Each switch may be implemented by a transistor such as an IGBT along with a reverse diode (as shown) as known in the art per se. 
     When activated, the voltage doubler  14  operates as follows. The battery continuously charges C 1  so as to apply a voltage V bat  across C 1 . In order to transfer energy to or from C 2 , a repetitive sequence of steps occurs. In a first step, as shown in the isolated view of  FIG. 3A , switches S VD1 , S VD3  are opened and S VD2 , S VD4  are closed for a period of time t 1  to bring C T  in parallel with C 1  through Ls. Current will increase in Ls such that it flows from a higher voltage potential to a lower potential until C 1  and Ct are at the same potential. The inductor current will then decrease, approaching zero. If C 1  started with a higher voltage potential than Ct, energy will have flowed from C 1  to Ct and Ct will now have a higher potential. Otherwise energy flowed from Ct to C 1  and now Ct will have a lower voltage potential than C 1 . As a second step, switches S VD2 , S VD4  are opened when the current through Ls is near zero and after a short deadtime, switches S VD1 , S VD3  are closed for a period of time t 2  as shown in the isolated view of  FIG. 3B  to bring C T  in parallel with C 2 . As described above, energy again flows from the capacitor with higher potential to the capacitor with lower potential Thus, a voltage 2*V bat  appears across C 1  and C 2 . During motoring, the energy in C 2  is utilized to power the motor, its charge will begin to drop, and energy will flow from C 1 , to Ct, and then to C 2 . During generating, the charge in C 2  will increase, and energy will then flow from C 2 , to Ct, and then to C 1 . 
       FIG. 5  shows the switching pattern  30  for the switches S VD1 , S VD3  and S VD2 , S VD4 . It will be noticed there is a very short dead time as one set of switches turns off and the other set of switches turn on. During the dead time, the current generated by the inductor L S  freewheels through the reverse diodes of the switches S VD2 , S VD3  or S VD1 , S VD4  depending on the direction of the current as shown in the isolated views of  FIGS. 3C and 3D . 
     The frequency of the switching pattern  30  (i.e., the switching frequency of the voltage doubler  14 ) is preferably kept constant and may vary over a wide range, depending on the application at hand. The switches S VD1 , S VD3  and S VD2 , S VD4  are preferably utilized at a duty cycle of about 45%. 
     The smoothing inductor L S  inhibits rapid current changes. The inductance of L S  along with the capacitance of C T  are preferably selected so as to provide a resonance correlated to the switching frequency.  FIG. 4  shows the current I T  during t 1  and t 2  and the voltage V LS  across the inductor L S  for the same periods. To minimize switching losses S VD1 , S VD3  and S VD2 , S VD4  are preferably switched when the current I T  is at or near zero. 
       FIGS. 7A and 7B  show the operation of the inverter  16  in relation to a PWM controller  40  that forms part of a larger motor controller  42  shown in  FIG. 6 . The motor controller  42  supplies as an input to the PWM controller a desired output voltage V O *, that is scaled by the PWM controller to a control voltage V CON . V CON  is compared against a triangular reference signal V TRI . The desired output voltage V O * ranges from 0 volts to double the battery voltage, i.e., for all intents and purposes the motor controller  42  is configured to operate on a battery having an output voltage of 2V bat . A comparator  48  determines the peak to peak voltage requested. 
     When the peak to peak of the desired voltage V O * is lower than V bat  as seen scaled in  FIG. 7A , the voltage doubler  14  is deactivated and all of its switches are turned off. This leaves capacitor C 1  in parallel with the battery such that node M is tied to the positive terminal of the battery whereby C 1  is presented with a voltage of V bat  across it but C 2  has no voltage across it. In this case, switch pair S 1 ,S 2  is off and the inverter is operated by manipulating switch pairs S 2 , S 3  and S 3 ,S 4  as seen in exemplary timing diagrams  50 ,  52 ,  54 . It will be noted that S 3  is on continuously, S 2  switches according to timing diagram  52 , and S 4  switches according to timing diagram  54 . 
     When S 2  and S 3  are on, the phase output is connected to node M or the positive terminal of the battery  12 . When S 3  and S 4  are on, the phase output is connected to the negative terminal of the battery  12 . 
     The switching losses in this mode are relatively low in that S 3  is continuously on, so there are no switching losses there. 
     This mode of operation where the voltage doubler  14  is deactivated is most likely to be utilized by the motor controller at slow motor speeds where torque demands are high requiring high current but low output voltage from the inverter  16 . 
     When the peak to peak of the desired voltage V O * is higher than V bat  as seen scaled in  FIG. 7A , the voltage doubler  14  is activated. In the application of a motor controller, the voltage doubler would be activated under any condition that the desired voltage may possibly have a step increase or sharp ramp increase such that the peak to peak of V O * is higher than V bat  (A soft start routine is provided to inhibit excess current inrush to CT and C 2 .) As discussed above, capacitor C 1  will have a voltage of V bat  across it and C 2  will have a voltage of V bat  across it. When Vo is higher than Vbat, switch pair S 3 ,S 4  is off and the inverter  16  is operated by manipulating switch pairs S 1 , S 2  and S 2 ,S 3  as seen in exemplary timing diagrams  60 ,  62 ,  64 . It will be noted that S 2  is on continuously, S 1  switches according to timing diagram  60 , and S 3  switches according to timing diagram  62 . 
     When S 1  and S 2  are on, the phase output is connected to the higher potential terminal of C 2 , thus delivering a voltage of 2V bat  to the phase output. When S 2  and S 3  are on, the phase output is connected to node M or the positive terminal of the battery  12 . 
     This mode of operation where the voltage doubler  14  is activated is most likely to be utilized by the motor controller at high motor speeds. 
     It will be appreciated from the foregoing that although the term “doubler” has been used to characterize the voltage doubler  14 , the boost voltage provided by the sub-circuit may be slightly less or greater than double the supply voltage. 
     While the above describes a particular embodiment(s) of the invention, it will be appreciated that modifications and variations may be made to the detailed embodiment(s) described herein without departing from the spirit of the invention.