Abstract:
Provided is a resistive random access memory device that includes a storage node connected to a switching device. The resistive random access memory device includes a first electrode, a resistance variable layer, and a second electrode which are sequentially stacked, wherein a diffusion blocking layer is formed between the first electrode and the resistance variable layer or between the resistance variable layer or/and the second electrode.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2007-0085558, filed on Aug. 24, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device, and more particularly, to a resistive random access memory device. 
         [0004]    2. Description of the Related Art 
         [0005]    Dynamic random access memories (DRAMs) have the advantages of having high integration density and high response speed; however, have disadvantages in terms of losing stored data when power is turned off. Nonvolatile memory devices are memory devices in which the drawbacks of DRAMs do not apply, and thus, recently various nonvolatile memory devices have been proposed. Among such nonvolatile memory devices, resistive random access memories (RRAMs) have drawn attention as nonvolatile memory devices having high integration density and high response speed like DRAMs. 
         [0006]    A conventional storage node of a RRAM has a structure in which a lower electrode, a resistance variable layer, and an upper electrode are sequentially stacked. 
         [0007]      FIG. 1  is a cross-sectional view of a conventional storage node S 1  of a conventional RRAM. 
         [0008]    Referring to  FIG. 1 , the conventional storage node S 1  has a structure in which a lower electrode  10 , a resistance variable layer  20 , and an upper electrode  30  are sequentially stacked. The lower electrode  10  and the upper electrode  30  are formed of Pt, and the resistance variable layer  20  is formed of nickel oxide (NiO x ). According to a voltage that is applied between the lower electrode  10  and the upper electrode  30 , a current path  1  is formed in the resistance variable layer  20  or the current path  1  is not formed in the resistance variable layer  20 . When the current path  1  is formed in the resistance variable layer  20 , electrical resistance in the resistance variable layer  20  is low, and this is referred to as an ON state. If the current path  1  is not formed in the resistance variable layer  20 , electrical resistance in the resistance variable layer  20  is high, and this is referred to an OFF state. 
         [0009]    The principle of generating the current path  1  in the resistance variable layer  20  will now be described in detail. When a negative voltage is applied to the resistance variable layer  20  and a positive voltage is applied to the upper electrode  30 , electrons migrate into the resistance variable layer  20  from the upper electrode  30  to the lower electrode  10 . These electrons have high energy, and thus, break the bonding between oxygen and nickel in the resistance variable layer  20 . Thus, oxygen atoms diffuse to the lower electrode  10  resulting in the generation of oxygen vacancies in the resistance variable layer  20 , and thus, the current path  1  is formed in the resistance variable layer  20  in this manner. Such diffusion of oxygen atoms is called percolation diffusion. 
         [0010]    However, the oxygen atoms not only diffuse in the resistance variable layer  20  but also out diffuse towards at least one of the lower electrode  10  and the upper electrode  30 . Therefore, an endurance of the resistance variable layer  20  and the conventional RRAM is reduced. That is, because of the out diffusion, the characteristics of the resistance variable layer  20  are easily degraded as the switching frequency increases, and in a severe case, the characteristics of the resistance variable layer  20  can be completely lost. 
       SUMMARY OF THE INVENTION 
       [0011]    To address the above and/or other problems, the present invention provides a resistive random access memory device having high endurance. 
         [0012]    According to an aspect of the present invention, there is provided a resistive random access memory device including a switching device and a storage node connected to the switching device, the storage node comprises a first electrode, a resistance variable layer, and a second electrode which are sequentially stacked, wherein a diffusion blocking layer is formed either between the first electrode and the resistance variable layer or between the resistance variable layer and the second electrode. 
         [0013]    The diffusion blocking layer may have a bonding energy greater than that of the resistance variable layer. 
         [0014]    The resistance variable layer may be a transition metal oxide layer, and the diffusion blocking layer is a nitride layer. 
         [0015]    The transition metal oxide layer may be formed of one selected from the group consisting of a nickel oxide layer, a titanium oxide layer, a zirconium oxide layer, a zinc oxide layer, and a copper oxide layer. 
         [0016]    The nitride layer may be a silicon nitride layer or a boron nitride layer. 
         [0017]    The first electrode and the second electrode may be Pt layers. 
         [0018]    The diffusion blocking layer may have a thickness T of 0&lt;T≦50 Å. 
         [0019]    The resistive random access memory device may further comprise the diffusion blocking layer either between the first electrode and the resistance variable layer or between the resistance variable layer and the second electrode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
           [0021]      FIG. 1  is a cross-sectional view of a conventional storage node of a conventional resistive random access memory (RRAM) device; 
           [0022]      FIG. 2  is a cross-sectional view of a RRAM device according to an embodiment of the present invention; 
           [0023]      FIG. 3  is a graph showing resistance variations according to a switching of a conventional RRAM and a RRAM according to an embodiment of the present invention; 
           [0024]      FIG. 4  is a cross-sectional view of a RRAM according to another embodiment of the present invention; and 
           [0025]      FIG. 5  is a cross-sectional view of a RRAM according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    The present invention will now be described more fully with reference to the accompanying drawings in which exemplary embodiments of the invention are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and like reference numerals refer to the like elements. 
         [0027]      FIG. 2  is a cross-sectional view of a RRAM device according to an embodiment of the present invention. 
         [0028]    Referring to  FIG. 2 , a switching device  200  is connected to a storage node S 2 . The switching device  200  can be a transistor or a diode. The storage node S 2  includes a lower electrode  40 , a resistance variable layer  50 , and an upper electrode  60  that are sequentially formed. A diffusion blocking layer  5  is formed between the lower electrode  40  and the resistance variable layer  50  or between the resistance variable layer  50  and the upper electrode  60 , for example, in the present embodiment, the diffusion blocking layer  5  is formed between the lower electrode  40  and the resistance variable layer  50 . The diffusion blocking layer  5  blocks the diffusion of chemical species from the resistance variable layer  50  into the lower electrode  40 . The diffusion blocking layer  5  may have a bonding energy greater than that of the resistance variable layer  50  because it is desirable that the chemical species that diffuse from the resistance variable layer  50  do not bond with chemical species of the diffusion blocking layer  5 . The resistance variable layer  50  can be a transition metal oxide layer having a non-stoichiometric composition, for example, a nickel oxide layer (a NiO x  layer), a titanium oxide layer (TiO x  layer), a zirconium oxide layer (ZrO x  layer), a zinc oxide layer (ZnO x  layer), or a copper oxide layer (CuO x  layer). The diffusion blocking layer  5  can be a nitride layer such as a silicon nitride layer (Si x N y  layer) or a boron nitride layer (B x N y  layer). For example, if the resistance variable layer  50  is a nickel oxide layer (NiO x  layer), the diffusion blocking layer  5  is a silicon nitride layer (Si x N y  layer). Si has an oxidation force lower than that of Ni, and is bonded with N in the silicon nitride layer. Thus, oxygen atoms that diffuse into the diffusion blocking layer  5  from the resistance variable layer  50  do not easily bond with the diffusion blocking layer  5 . Therefore, it is difficult for oxygen atoms to move into the lower electrode  40 , and the oxygen atoms can stay on an upper surface of the diffusion blocking layer  5  with a weak bonding force with the diffusion blocking layer  5 . The oxygen atoms present on the upper surface of the diffusion blocking layer  5  can be re-diffused into the resistance variable layer  50 . That is, the moving (diffusion) range of the oxygen atoms can be limited to the resistance variable layer  50 . In this manner, the diffusion of the oxygen atoms can be limited to not occur into the lower electrode  40  due to the diffusion blocking layer  5 , and thus, the resistance variable layer  50  and the RRAM that includes the resistance variable layer  50  can have high endurance. 
         [0029]    The diffusion blocking layer  5  can be formed to a thickness of 50 Å or less, preferably, 5 to 15 Å using a predetermined deposition method, for example, an atomic layer deposition (ALD) method. The tunneling of electrons through the diffusion blocking layer  5  having above such thickness is easy, and thus, a current path that connects the lower electrode  40  to the upper electrode  60  can be readily formed. 
         [0030]      FIG. 3  is a graph showing resistance variations according to the switching of a conventional RRAM and a RRAM, according to an embodiment of the present invention. In  FIG. 3 , first and second plots G 1  and G 2  are the resistance variations of the conventional RRAM that includes the conventional storage node S 1  of  FIG. 1 , and third and fourth plots G 3  and G 4  are the resistance variations of the RRAM having the storage node S 2  of  FIG. 2 , according to the present embodiment. The first and third plots G 1  and G 3  are the results of resistance states when a current path is formed in the resistance variable layers  20  and  50 , that is, the results corresponding to a low resistance state, and the second and fourth plots G 2  and G 4  are the resistance states when a current path is not formed in the resistance variable layers  20  and  50 , that is, the results corresponding to a high resistance state. 
         [0031]    Referring to  FIG. 3 , the first and second plots G 1  and G 2  have lengths in a horizontal axis direction shorter than those of the third and fourth plots G 3  and G 4  in a horizontal axis direction. The first and second plots G 1  and G 2  are seen until the switching is approximately 60 times. However, the third and fourth plots G 3  and G 4  are continuously seen within the measuring range. This result denotes that the switching a characteristic of the RRAM according to the present embodiment maintains longer than that of the conventional RRAM. Thus, confirming that the endurance of the RRAM according to the present embodiment of the present invention is increased due to the diffusion blocking layer  5 . 
         [0032]    The configuration of the storage node S 2  of  FIG. 2  can be modified in various ways, and thus, the present invention is not limited to the one shown. For example, the switching device  200  can be connected to the upper electrode  60  instead of to the lower electrode  40 , and the diffusion blocking layer  5  can be formed between the resistance variable layer  50  and the upper electrode  60  instead of being formed between the lower electrode  40  and the resistance variable layer  50 . Also, as depicted in  FIG. 4 , diffusion blocking layers  5  and  5 ′ can be formed between the lower electrode  40  and the resistance variable layer  50  and between the resistance variable layer  50  and the upper electrode  60 . 
         [0033]      FIG. 5  is a cross-sectional view showing an example of the embodied structure of the switching device  200  and the connection between the switching device  200  and the storage node S 2  of  FIG. 2 . 
         [0034]    Referring to  FIG. 5 , a gate  110  is formed on a substrate  100 , and first and second dopant regions  120  and  130  are formed in the substrate  100  on both sides of the gate  110 . One of the first and second dopant regions  120  and  130  is a source and the other is a drain. The gate  110  and the first and second dopant regions  120  and  130  constitute a transistor, that is, a switching device. An interlayer insulating layer  140  that covers the transistor is formed on the substrate  100 . A contact hole  150  that exposes the first dopant region  120  is formed in the interlayer insulating layer  140 , and the contact hole  150  is filled with a conductive plug  160 . The storage node S 2 , which covers an exposed portion of the conductive plug  160 , is formed on the interlayer insulating layer  140 . The storage node S 2  of  FIG. 5  can also be replaced by the storage node S 2 ′ of  FIG. 4 . Although not shown, a bit line that is electrically connected to the second dopant region  130  can be formed. According to a voltage that is applied to the gate  110  and the bit line, a voltage can be applied to the lower electrode  40 , and according to a voltage that is applied to the lower electrode  40  and the upper electrode  60 , the formation of a current path in the resistance variable layer  50  is determined. 
         [0035]    Although not shown, according to the present embodiment, the switching devices  200  of  FIGS. 2 and 4  can be diodes. In this case, the RRAM according to the present invention can be a multi-layer cross point RRAM having a unit cell of 1D(diode)-1R(resistor) structure. 
         [0036]    In RRAMs according to embodiments of the present invention, the diffusion of chemical species to the outside of a resistance variable layer is prevented or minimized using a diffusion blocking layer, and thus, the endurance of the resistance variable layer and the RRAM that includes the resistance variable layer can be increased. 
         [0037]    While the present invention has been shown and described with reference to embodiments thereof, it should not be construed as being limited to such embodiments. One skilled in this art knows that, for example, elements that constitute the storage nodes S 2  and S 2 ′ can be different and the storage nodes S 2  and S 2 ′ can have different structures as to the ones shown. Different films than the ones shown above can be formed between the lower electrode  40  and the resistance variable layer  50  and between the resistance variable layer  50  and the upper electrode  60 . The shapes of the lower electrode  40 , the resistance variable layer  50 , and the upper electrode  60  can be modified in various ways. Therefore, the scope of the invention is not defined by the detailed description of the invention however by the appended claims.