Abstract:
A semiconductor memory device, capable of being accessed at a high speed, according to the present invention, is provided, and is configured with the changeover point in time between the pre-charge operation and a word line selection operation on the far-end side of the sense amplifier being earlier than that on the near-end side of it. There are provided word selection signal input buffer, block selection signal input buffer, digit selection signal input buffer on semiconductor chip, decoders, which decode the said signals, drivers for the output signal of each decoder, memory block, which is stored with information, and gate circuit, which selects a column of memory cells in a memory block. Drivers for the word selection signal and block: selection signal are laid out in the middle of chip and near far-end side pre-charge unit, which is located the farthest from the sense amplifier (which is deployed in near-end side pre-charge unit.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the invention  
           [0002]    The present invention relates to a semiconductor memory device. In particular, it relates to a semiconductor memory device layout so that the read-out speed of the semiconductor memory device can be high.  
           [0003]    2. Description of a Related Art  
           [0004]    Efforts for improving integration and capacity of semiconductor memory devices have been continuously made so that many memory cells can be connected to pairs of digit lines. Accordingly, the capacitance on digit lines becomes large, causing the access delay to increase, preventing the high speed operation from being performed. To solve this problem, the inventor of the present invention supposed that pre-charge circuits are deployed at both ends of the digit lines, for example, so that the high speed recovery (pre-charge) after a writing is performed can be performed.  
           [0005]    [0005]FIG. 1 is a diagram showing the layout of a chip of a semiconductor memory device of a related art, supposed by the inventor. On semiconductor chip  1  input buffers such as word selection signal input buffers  2 , block selection signal input buffers  3 , and column selection signal input buffers  4  are provided; wherein for each input buffer, word signal decoder  5 , which decodes the respective each output signal of it, block signal decoder  6 , and column signal decoder  7  are provided. At the output end of each decoder, word signal driver  8 , block signal driver  9 , and column signal driver  10 , which function as buffers for the output signals of the respective decoders, are provided. These drivers  8  to  10  are deployed along the longer sides of the chip.  
           [0006]    In the middle of the chip, memory blocks BL 0  to BL 31  are laid out. A memory cell array of memory cell block  11 , near-end side pre-charge unit  12 , and far-end side pre-charge unit  13  are provided in each memory block BL 0  to BL 31 . In near-end side pre-charge unit  12 , sense amplifiers are provided. The output signals of column selection/pre-charge control NAND gates G 0  to G 15 , which select a column of memory cells in the memory block, are input to each near-end side pre-charge unit  12 .  
           [0007]    In this Figure, in order to simplify the description, it is assumed that the number of word selection signals is three, and the number of block selection signals and the number of column selection signals are four bits, respectively. The output of word selection signal input buffers  2  is decoded by word signal decoder  5 , input to word signal drivers  8 , and coupled to eight word lines in each memory block BL 0  to BL 31  through word signal lines  14 .  
           [0008]    In the same manner, the output of block selection signal input buffers  3  is decoded by block signal decoder  6 , input to block signal drivers  9 ; the output of which being then input to the respective far-end side pre-charge unit  13  for each memory block BL 0  to BL 31  and one of the input terminal of each NAND gate G 0  to G 15  through each block selection signal line  15 .  
           [0009]    The output of column selection signal input buffers  4  is decoded by column signal decoder  7 , and then input to the other input terminals of NAND gates G 0  to G 15  through each respective column signal driver  10 .  
           [0010]    With such configuration, one of eight word lines is selected for thirty-two memory blocks on a single chip so that a single line of memory cells in all the memory blocks may be selected; and the NAND gates connected to either of the two memory blocks are selected by the sixteen block selection signal lines  15 .  
           [0011]    In such a semiconductor memory device as described above, far-end side pre-charge units  13  are deployed at the farthest position from the each of the respective block signal drivers  9 . Accordingly, when the pre-charge operation of the pre-charge circuit is halted for, for example, a read-out operation, transmission of the signal therein takes time causing the halt point in time for the pre-charge operation to be later than the halt point in time of near-end side pre-charge units  12 . Besides this, the word lines for the memory cells on the far-end side pre-charge sides of the memory blocks BL are deployed far from word signal drivers  8 . Accordingly, the point in time at which a word line is selected for, for example, the read-out operation is later than the point in time at which the word line positioned near near-end side pre-charge units  12  is selected. Furthermore, the transmission time for the signal that is read out to the digit line of the memory cell, which is deployed near far-end side pre-charge unit  13 , to reach the corresponding sense amplifier is longer than the transmission time in the case where the memory cell deployed near near-end side pre-charge unit  12  is read out.  
           [0012]    In other words, the point in time at which an operation of reading out from the memory cell block deplored near far-end side pre-charge unit  13  where transmitting the read-out signal takes a longer amount of time is later than the start point in time for the memory cell block deployed near near-end side pre-charge unit  12 , making it difficult to provide high-speed operation.  
           [0013]    The subject of the present invention is to solve the above-mentioned problem, and its objective is to provide a high access speed semiconductor memory device, which is configured with the point in time at which changing from the pre-charge operation to the wordline selection operation, which is performed on the near-end side of each sense amplifier, being no later than the point in time at which the same is performed on the far-end side of each sense amplifier, in order to improve the speed at which reading out the memory cells deployed far from each sense amplifier is performed.  
         SUMMARY OF THE PRESENT INVENTION  
         [0014]    According to an aspect of the present invention, there is provided a semiconductor memory device, which includes a memory cell deployed in a column direction, a pair of digit lines connected to each memory cell, a word line, which is laid crossing said digit lines and selects each memory cell, a sense amplifier, which is positioned on one side of said digit lines, a near-end side pre-charge circuit, which is deployed near said sense amplifier of said digit lines, and a far-end side pre-charge circuit, which is deployed at the opposite end to said sense amplifier of said digit lines. This semiconductor memory device is characterized by the completion point in time of a pre-charge operation of a far-end side pre-charge circuit during a read-out operation being earlier than that of a near-end side pre-charge circuit.  
           [0015]    According to an aspect of the present invention, it is preferred that; during a read-out operation, the selection signal for the word line located near the far-end side pre-charge circuit climb up earlier than the word line located near the near-end side pre-charge circuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    The above-mentioned and other objects, features and advantages of this invention will become more apparent by referencing the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein:  
         [0017]    [0017]FIG. 1 shows a layout of a semiconductor device of a related art;  
         [0018]    [0018]FIG. 2 shows a layout of the first embodiment, according to the present invention;  
         [0019]    [0019]FIG. 3 is a circuit diagram of a memory block of the first embodiment, according to the present invention;  
         [0020]    [0020]FIG. 4 is a timing chart for the memory block of the first embodiment, according to the present invention;  
         [0021]    [0021]FIG. 5 is a diagram showing a layout of the second embodiment, according to the present invention; and  
         [0022]    [0022]FIG. 6 is a circuit diagram of a memory block of the second embodiment, according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0023]    In the following, embodiments of the present invention are described.  
         [0024]    [0024]FIG. 2 is a diagram showing the first embodiment of the present invention. It is noted here that the same parts in FIG. 2 as those in FIG. 1 are labeled with the same respective reference numerals and repetitive descriptions are omitted. What is different from the device as shown in FIG. 1 is that word signal driver  8  and block signal driver  9  are laid out in the center of semiconductor chip  1  of this embodiment.  
         [0025]    [0025]FIG. 3 is a circuit diagram of memory blocks of the first embodiment of the present invention; FIG. 4 is a timing chart showing a write and read operation of a memory block. This embodiment is an example of a configuration where a pre-charge circuit deployed on the far-end side of the sense amplifier (hereafter, referred to as a far-end side pre-charge circuit) is controlled in conformity with a signal transmitted from block. signal driver  9 ; whereas a pre-charge circuit deployed on the near-end side of the sense amplifier (hereafter, referred to as a near-end side pre-charge circuit) is controlled in conformity with signals transmitted from block signal driver  9  and column signal driver  10 .  
         [0026]    As shown in FIG. 3, for example, sixteen pairs of digit lines D 0 T (logical true) and D 0 B (logical false), . . . , D 15 T and D 15 B are deployed in each memory block. In far-end side pre-charge unit  13 , the respective drains of p-channel transistors  17  and  18  (hereafter, simply referred to as transistors) are connected to each pair of digit lines, whereas the sources of transistors  17  and  18  are connected to a power supply.  
         [0027]    In addition, the drains of transistors  17  and  18  are connected to the respective source and drain of transistor  19 , which is capable of performing equalization, with the gate thereof being connected to the gates of transistors  17  and  18 . Far-end side pre-charge control line  20  that is connected to this gate is connected to block selection signal  15  via pre-charge control circuit  40 .  
         [0028]    Eight memory cells are connected to each of the pairs of digit lines D 0 T and D 0 B, . . . , D 15 T and D 15 B (only eight cells are given for the simplification of the explanation; however, many memory cells are connected in practice). Word lines W 0  to W 7  are deployed crossing the digital lines, and connected to each memory cell.  
         [0029]    Transistors  25  and  26 , column selection switches  28  and  29  made up of p-channel transistors, and inverter  27 , which form a near-end side pre-charge circuit, are connected to the other ends of the pairs of digit lines D 0 T and D 0 B, . . .  
         [0030]    The sources of transistors  25  and  26  in the pre-charge circuit are connected to the power supply; whereas the gates thereof are connected to the output terminal of inverter  27 . Each of column selection signal lines Y 0  to Y 15 , which are the output lines of NAND gates G 0  to G 15 , is connected to the corresponding input terminal of inverter  27  and the gates of column selection switches  28  and  29 .  
         [0031]    The output lines of column selection switches  28  and  29 , which are provided along each pair of digit lines, are united into one and connected to transfer gates  33  and  34 , which are p-channel transistors. The transfer gates  33  and  34  have a function to nullify the effects of the capacitance of the digit lines by turning off while amplification is being performed by the sense amplifier.  
         [0032]    The output of transfer gates  33  and  34  is input to the input nodes  35 A and  35 B of sense amplifier  35 , respectively. Sense amplifier  35  used here is a commonly used dynamic sense amplifier made up of flip-flops, and is configured in a manner such that it is activated by having the gate of n-channel transistor  36  become high level and then latches.  
         [0033]    As described above, according to the embodiments of the present invention, the layout is devised such that the word signal driver and the block signal drivers are deployed on the side near far-end side pre-charge (equalize) unit  13 ; and the signal lines relevant to column are laid around the periphery of the chip.  
         [0034]    Next, the operation of reading out from and writing into a memory cell is explained while referencing FIG. 4. It is noted here that the case where memory cell  22  is selected is explained.  
         [0035]    Immediately before writing is performed, when far-end side pre-charge signal PC (hereafter, referred to as PC) is at a low level, transistors  17 ,  18 , and  19  turns on, causing digit lines D 0 T and D 0 B to be pre-charged onto the power supply level. When column selection signal Y 0  is at a high level, transistors  28  and  29  are turned off, and at the same time transistors  25  and  26  are turned on by inverter  27  causing digit lines D 0 T and D 0 B to be pre-charged from the sense amplifier side.  
         [0036]    Next, word line W 0  becomes high level, and memory cells  22  to  22 A are selected. At almost the same time, PC and Y 0  become high level and low level, respectively; accordingly, transistors  17 ,  18  and  19  are turned off, column selection switches  28  and  29  are turned on, and transistors  25  and  26  are turned off by inverter  27 .  
         [0037]    Accordingly, memory cell  22  is selected, separated off the pre-charge circuit and the sense amplifier, and a write operation starts. At this time, transfer signal TE is at a high level so that sense amplifier signal SA does not change and stays at a low level.  
         [0038]    [0038]FIG. 3 does not show write amplifiers; however, since they are connected to the digit lines between column switches  28  and  29  and transfer gates  33  and  34 , and column selection switches  28  and  29  are in an ON state, data provided in the write amplifiers is written in memory cell  22 .  
         [0039]    Next, W 0  and PC become low level again, causing memory cells  22  to  22 A to be de-selected, transistors  17 ,  18 , and  19  to turn on, and pre-charge and equalization operation to start. At the same time, Y 0  becomes high level and column selection switches  28  and  39  are turned off; however, transistors  25  and  26  are turned on by inverter  27 , causing the pre-charge operation to start.  
         [0040]    Next, the read-out operation is explained. W 0  and PC become high level again, causing memory cells  22  to  22 A to be selected and the pre-charge and equalization operations to end. And at the same time, Y 0  and TE become low level, causing column selection switches  28  and  29  to turn on and transistors  25  and  26  to turn off, so that the pre-charge operation ends and digit lines D 0 T and D 0 B are coupled to the sense amplifier.  
         [0041]    At this time, transfer gates  33  and  34  are in an ON state, and during the time when information from memory cell  22  is generated on digit lines D 0 T and D 0 B and a voltage difference develops between them (such time corresponding to the access time of the slowest memory cell, which is determined through simulation, and is, for example, approximately 5 ns), a high level is given to SA causing transistor  36  to turn on, and accordingly it is latched by sense amplifier  35 . TE is made to be high level in approximately 0.5 ns once the latching is completed, causing sense amplifier  35  to separate off the digit lines. This is because the drive capability of sense amplifier  35  is low and if transfer gates  33  and  34  are left in an ON state, it takes time to bring the digit lines with the added large capacitance to a stable level, thereby causing the read-out speed to be low.  
         [0042]    Alternatively, SA may be returned to low level at the point in time when TE becomes at a high level; however, since output lines  38 A and  38 B of the sense amplifier become a level that is unstable, SA may remain high level except for the cases where a latch circuit is connected on the outside.  
         [0043]    In such a manner, the read-out operation is performed by repeating the read-out and pre-charge operation every time the address changes.  
         [0044]    Considering the read-out operation of a memory cell, when memory cell  24 , which is deployed on the near-end side of sense amplifier  35 , is readout, the voltage difference is transmitted to sense amplifier  35  immediately; however, when memory cell  22  deployed on the far-end side is read out, it tales a longer time to transmit the voltage difference to sense amplifier  35 . In order to provide high speed access, the capability of performing fast access of memory cell  33 , which is deployed on the far-end side of sense amplifier  35 , is required.  
         [0045]    In other words, the operation of selecting word line  21  on the far-end side of sense amplifier  35  has to be performed earlier than the same operation on the near-end word line  23 . Besides this, it is necessary for far-end side pre-charge (equalize) unit  13  to be turned off either simultaneously or earlier than the point in time word line  21  is turned off. In this case, even if transistors  25  and  26 , which are deployed on the near-end side of sense amplifier  35 , are in an ON state, since the digit lines have a large capacitance, a read-out voltage difference can occur on the digit lines near memory cell  22  as long as far-end side pre-charge (equalize) unit  13  is in an OFF state.  
         [0046]    Accordingly, it is possible to access memory cell  22  at a high speed (i.e., it is possible for sense amplifier  35  to have an earlier latch timing). More specifically, it is important to provide a structure that allows a word line on the far-end side of sense amplifier  35  to be selected as quickly as possible and also the pre-charge (equalize) operation to be halted as quickly as possible independent from the operation on the near-end side. The semiconductor memory device, according to the present invention, has a layout structure to provide high speed operation as described above.  
         [0047]    It is noted here that if the timing for halting the pre-charge operation is earlier than the timing for a word line to be in an ON state, the read-out operation is performed in an unstable voltage state of the digit lines, possibly causing a fault to happen.  
         [0048]    Accordingly, it is possible to apply controls to prevent such a fault from occurring using an alternative control circuit obtained by modifying the timing for pre-charge control circuit  40 . It is noted here that such a control circuit is required only in the cases where the timing gap between the above-mentioned pre-charge and word line related operation is greater than approximately 5 ns; however, the control circuit is not necessary in the other cases.  
         [0049]    [0049]FIG. 5 is a diagram showing the second embodiment of the present invention. It is noted here that the same parts in FIG. 5 as those in FIG. 2 are labeled with the same respective reference numerals and repetitive descriptions are omitted. What is different from the first embodiment shown in FIG. 2 is that the second embodiment does not use a NAND gate. In the second embodiment, the pre-charge circuits deployed at either end of the digit lines are controlled in conformity with only a signal transmitted from block selection signal line  15  independent from the column selection signal.  
         [0050]    With this configuration, as is apparent from FIG. 5, block signal driver  9  is deployed in the center of the chip; the output signal of block signal driver  9  is input to far-end side pre-charge unit  13  via block selection signal line  15 , and then input to near-end side pre-charge unit  12 . Accordingly, like the first embodiment, the second embodiment is configured in such a manner that the pre-charge operation on the far-end side of the sense amplifier can halt earlier during the read-out operation. Besides this, the control of word lines is performed in the same manner as that in the first embodiment.  
         [0051]    [0051]FIG. 6 is a circuit diagram of a memory block of the second embodiment. It is noted here that the same parts in FIG. 6 as those in FIG. 3 are labeled with the same respective reference numerals and repetitive descriptions are omitted. What is different from the first embodiment is that in the second embodiment the gates of transistors  25  and  26  are commonly connected to block selection signal line  15 , which transmits the output signal of block signal driver  9 , without inverter  27 .  
         [0052]    In the third embodiment, the pre-charge control circuit  40  with the timing for halting the pre-charge operation is modified into an alternative control circuit with the timing that allows the pre-charge operation to halt after a ward signal is sensed. This aims to prevent an occurrence of a fault, which emanates from the fact that the pre-charge operation is halted too early. More specifically, this can be configured with a NAND gate, which logically NANDs the signals of word signal line  14  and block selection signal line  15 .  
         [0053]    Thus far, the preferred embodiments have been explained; however, the present invention is not limited to these embodiments; and they may be suitably modified within the scope that does not depart from the points of the present invention. For example, four or more memory block arrays, each having memory blocks (BL 0  to BL 15 , etc. arranged in a horizontal direction, may be stacked in a vertical direction; or four or more memory block arrays may be arranged in a matrix shape. Furthermore, a sub-word signal driver and/or a sub-word signal decoder may be deployed between word signal driver  8  and a word line. Furthermore, one or more additional pre-charge units may be deployed in the center of each pair of digit lines.  
         [0054]    [Results of the present invention] 
         [0055]    As described above, in the semiconductor memory devices, according to the present invention, by turning off the pre-charge (equalize) unit deployed on the far-end side of the sense amplifier earlier, but turning on a word line on the far-end side earlier, the voltage on the digit lines deployed on the far-end side, which adversely influence the access time, is increased in a short time, allowing for a high speed read-out operation.  
         [0056]    Furthermore, by combining the circuits for word selection and pre-charge timing control, an occurrence of a fault due to the fact that the pre-charge operation halts too early can be prevented.