Abstract:
A method for offloading a cache memory is disclosed. The method generally includes the steps of (A) reading all of a plurality of cache lines from the cache memory in response to an assertion of a signal to offload of the cache memory, (B) generating a plurality of blocks by dividing the cache lines in accordance with a RAID configuration and (C) writing the blocks among a plurality of nonvolatile memories in the RAID configuration, wherein each of the nonvolatile memories has a write bandwidth less than a read bandwidth of the cache memory.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to storage controllers generally and, more particularly, to a method and/or apparatus for optimizing the performance and reliability of a storage controller cache offload circuit. 
       BACKGROUND OF THE INVENTION 
       [0002]    Upon power loss of AC power, a conventional storage controller is forced to offload a cache content as quickly and reliably as possible from a cache memory to a local persistent storage device using power from a limited-reserve battery backup unit. The persistent storage device (i) is commonly local to avoid counting on remote devices to be powered up and (ii) utilizes very low amounts of power to avoid large batteries. The very low power results in the persistent storage device having a limited access bandwidth. Large batteries are very expensive and have decreasing reliability over time. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention concerns a method for offloading a cache memory. The method generally comprises the steps of (A) reading all of a plurality of cache lines from the cache memory in response to an assertion of a signal to offload of the cache memory, (B) generating a plurality of blocks by dividing the cache lines in accordance with a RAID configuration and (C) writing the blocks among a plurality of nonvolatile memories in the RAID configuration, wherein each of the nonvolatile memories has a write bandwidth less than a read bandwidth of the cache memory. 
         [0004]    The objects, features and advantages of the present invention include providing a method and/or apparatus for optimizing the performance and reliability of a storage controller cache offload circuit that may (i) arrange multiple nonvolatile memories in a RAID configuration, (ii) write two or more of the nonvolatile memories substantially simultaneously, (iii) enable a capacity expansion of the nonvolatile memories by adding more memory circuits, (iv) permit lower battery backup unit sizes compared with conventional approaches and/or (v) permit usage of super-capacitor technology as a replacement to conventional battery cells. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
           [0006]      FIG. 1  is a block diagram of a system in accordance with a preferred embodiment of the present invention; 
           [0007]      FIG. 2  is a diagram of an example implementation of a nonvolatile memory circuit; 
           [0008]      FIG. 3  is a flow diagram of an example method for offloading a cache memory; 
           [0009]      FIG. 4  is a diagram of an example RAID 0 configuration; 
           [0010]      FIG. 5  is a diagram of an example RAID 1 configuration; and 
           [0011]      FIG. 6  is a diagram of an example RAID 5 configuration. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0012]    The present invention generally achieves a rapid cache offload architecture using multiple nonvolatile drives in parallel. The nonvolatile drives may be arranged in a RAID configuration, such as a RAID 0 configuration, a RAID 1 configuration or a RAID 5 configuration. Other RAID configuration may be implemented to meet the criteria of a particular application. A parallel write nature of several RAID configurations generally allows for a higher performance and a higher reliability on the cache offload interface compared with the conventional techniques. 
         [0013]    Referring to  FIG. 1 , a block diagram of a system  100  is shown in accordance with a preferred embodiment of the present invention. The system (or apparatus)  100  may be implemented as a cache-based processing system. The system  100  generally comprises a circuit (or module)  102 , a circuit (or module)  104 , a circuit (or module)  106 , a circuit (or module)  108 , a circuit (or module)  110  and a circuit (or module)  112 . A signal (e.g., PWR) may be received by the circuit  110 . A signal (e.g., OFFLOAD) may be generated by the circuit  110  and presented to the circuit  104 . An interface  114  may enable the circuit  102  and the circuit  104  to communicate with each other. The circuit  104  may communicate with the circuit  106  through an interface  116 . An interface  118  may permit the circuit  104  to communicate with the circuit  108 . The circuit  104  may communicate with the circuit  112  through an interface  120 . 
         [0014]    The circuit  102  may be implemented as a processor circuit. The circuit  102  may be operational to perform a variety of functions by executing software programs. The circuit  102  may read and write instructions and/or data for the software programs to and from the circuits  106 ,  108  and  112  through the circuit  104 . 
         [0015]    The circuit  104  may be implemented as a memory controller circuit. The circuit  104  may be operational to control the circuit  106 , the circuit  108  and the circuit  112 . The circuit  104  may exchange the data and the instructions of the software programs with the circuit  102  through the processor interface  114 . The data and the instructions may be exchanged between the circuit  104  and (i) the circuit  106  through the cache interface  116 , (ii) the circuit  108  through the Flash interface  118  and (iii) the circuit  112  through the memory interface  120 . The circuit  104  may be further operational to offload all of the information (e.g., data and instructions) stored in the circuit  106  into the circuit  108  through the interface  118  (see arrow  128 ) in response to an asserted state (e.g., a logical low) of the signal OFFLOAD. 
         [0016]    The circuit  106  may be implemented as a volatile memory. In particular, the circuit  106  may be implemented as a volatile cache memory. The circuit  106  is generally operational to buffer the data and the instructions used and generated by the software executing in the circuit  102 . The information stored in the circuit  106  may be arranged as cache lines  124   a - 124   n . Each of the cache lines  124   a - 124   n  may be swapped with the circuit  112  based on cache hits and cache misses. The cache lines may be read from the circuit  106  at a first read bandwidth and written at a first write bandwidth. 
         [0017]    The circuit  108  may be implemented as an array of nonvolatile memories  126   a - 126   d . The memories (or components)  126   a - 126   d  may be arranged in a RAID (Redundant Array of Independent Disks) configuration. In some embodiments, each memory “disk”  126   a - 126   d  of the circuit  108  may be implemented as a Flash memory. Other nonvolatile memory technologies may be implemented to meet the criteria of a particular application. Information may be written into each of the memories  126   a - 126   d  at a second write bandwidth and read at a second read bandwidth. 
         [0018]    The circuit  110  may be implemented as a backup power unit. The circuit  110  may be operational to store, convert, regulate and/or filter electrical power received in the signal PWR into one or more power networks suitable for use by the circuits  102 ,  104 ,  106 ,  108  and  112 . The circuit  110  may also be operational to provide electrical power for a limited time suitable to operate at least the circuits  104 ,  106  and  108  for a sufficient time to offload the information from the circuit  106  into the circuit  108 . Furthermore, the circuit  110  may monitor the condition of the power flowing in via the signal PWR and assert the signal OFFLINE in response to a severe drop and/or complete loss of power in the signal PWR. In some embodiments, the circuit  110  may be implemented as one or more batteries. In at least one embodiment, the circuit  110  may be implemented as one or more super-capacitors or ultra-capacitors. 
         [0019]    The circuit  112  may be implemented as a main memory circuit. In particular, the circuit  112  may be implemented as a volatile random access memory. The circuit  112  may be operational to store the data and the instructions for the software executing on the circuit  102 . The circuit  112  may provide cache lines to the circuit  106  and receive cache lines from the circuit  106  as determined by the circuit  104 . 
         [0020]    Referring to  FIG. 2 , a diagram of an example implementation of the circuit  108  is shown. In addition to the memory components  126   a - 126   d , the circuit  108  may comprise multiple sockets  130   a - 130   d . Each of the sockets (or ports)  130   a - 130   d  is generally arranged to couple to a single memory  126   a - 126   d . Coupling may include physical connections, electrical power connections and communication connections. In at least one configuration of the system  100 , the sockets  130   a - 130   d  may be populated by a single memory component (e.g.,  126   a ). In other configurations of the system  100 , two or more memories  126   a - 126   d  may be installed in the sockets  130   a - 130   d.    
         [0021]    Referring to  FIG. 3 , a flow diagram of an example method  140  for offloading the circuit  106  is shown. The method  140  generally implements a rapid offload method that moves data from the circuit  106  to the circuit  108 . The method  140  generally comprises a step (or block)  142 , a step (or block)  144 , an optional step (or block)  146  and a step (or block)  148 . 
         [0022]    The method  140  may be triggered by an assertion of the signal OFFLOAD. Other triggers, such as a command from the circuit  102 , may also initiate the method  140 . In the step  142 , the circuit  110  may assert the signal OFFLOAD upon detecting a loss of electrical power in the signal PWR. The assertion of the signal OFFLOAD may be sensed by the circuit  104 . In response, the circuit  104  may read (offload) the cache lines  124   a - 124   n  from the circuit  106  in the step  144 . A transfer speed of the information from the circuit  106  to the circuit  104  may be governed by a read bandwidth of the circuit  106 . 
         [0023]    Depending on the particular RAID configuration being implemented in the circuit  108 , the circuit  104  may/may not stripe the information in the cache lines  124   a - 124   n  in the step  146 . The blocks of information/stripes of information and error correction information (if any) may then be written to the memories  126   a - 126   d  by the circuit  104  in the step  148 . A transfer speed of the blocks/stripes from the circuit  104  to the circuit  108  may be determined by write bandwidths of the memories  126   a - 126   d.    
         [0024]    Since the information may be written from the circuit  104  to the memories  126   a - 126   d  along multiple parallel paths substantially simultaneously, the combined write bandwidth to the memories  126   a - 126   d  may be larger (faster) than the read bandwidth from the circuit  106 . The higher combined write bandwidth generally reduces a time consumed executing the transfer compared with conventional techniques. An architecture of the system  100  may utilize removable nonvolatile memory components  126   a - 126   d  at low cost. Example memory components  126   a - 126   d  may include, but are not limited to, secure digital (SD) Flash cards and USB Flash drives. 
         [0025]    Customer specified cache sizes for the circuit  106  have grown large in recent years. Hence, low cost nonvolatile memory choices are generally unusable due to slow write times and smaller capacities. The present invention generally uses several nonvolatile memories such that the capacity and the speed of the nonvolatile memories may be increased using RAID technology to create a virtual nonvolatile memory (circuit  108 ) that is larger and faster than a single common nonvolatile memory element. 
         [0026]    By using multiple memories  126   a - 126   d , the circuit  104  and the circuit  108  may be scaled in proportion to the amount of cache ordered by the customer. For example, the circuit  104  may support cache size options of 8 gigabytes (GB), 16 GB and 32 GB in the circuit  106 . The circuit  104  may be configured to control several (e.g., four) memory components  126   a - 126   d  in the circuit  108 , each with a size of 8 GB. As such, an 8 GB cache system  100  may be built with a single 8 GB memory (e.g.,  126   a ). A 16 GB cache system  100  may be built with two 8 GB memories (e.g.,  126   a  and  126   b ). A 32 GB cache system would be built with four 8 GB memories (e.g.,  126   a - 126   d ). 
         [0027]    Consider a case where each of the memories  126   a - 126   d  has an example write speed of 20 megabytes per second (MB/sec). The 8 GB cache system  100  may use approximately 8 GB/(20 MB/sec)=400 seconds to offload the 8 GB volatile circuit  106  to the 8 GB nonvolatile circuit  108 . For the 16 GB cache system  100 , the write bandwidth to the circuit  108  is generally doubled due to using RAID technology to configure two of the memories (e.g.,  126   a  and  126   b ). A total offload time for moving information from the 16 GB circuit  106  may be 16 GB/(2×20 MB/sec)=400 seconds. The 32 GB cache system  100  may use four memory elements  126   a - 126   d , providing an effective bandwidth of 4×20 MB/sec=80 MB/sec. The larger write bandwidth may allow a cache offload time of 32 GB/(4×20 MB/sec)=400 seconds. In all three examples, the cache offload time may be maintained at approximately 400 seconds. Larger numbers of the memory components  126   a - 126   d  may be utilized to decrease the offload time, permit larger cache sizes and/or implement other RAID configurations. 
         [0028]    Referring to  FIG. 4 , a diagram of an example RAID 0 configuration is shown. The RAID 0 configuration may implement a striped array made from the memory components  126   a - 126   d . The circuit  104  may group the cache lines  124   a - 124   n  read from the circuit  106  into blocks (e.g., A-H). Each of the individual blocks A-H may be written to a single memory  126   a - 126   d , with several blocks written substantially simultaneously along parallel paths  150   a - 150   d . For example, the circuit  104  may write the block A to the memory  126   a , the block B to the memory  126   b , the block C to the memory  126   c  and the block D to the memory  126   d  in parallel or in a staggered start sequence. In the stagger start sequence, the circuit  104  may begin writing the block A while still assembling the block B from the cache lines  124   a - 124   n . Once the block B is ready, the circuit  104  may start writing the block B, continue the write of the block A and begin assembling the block C. A RAID 0 configuration is generally implemented with at least two of the memories  126   a - 126   d.    
         [0029]    Referring to  FIG. 5 , a diagram of an example RAID 1 configuration is shown. The RAID 1 configuration generally implements duplexing of mirrored pairs using multiple (e.g., eight) of the memories  126   a - 126   h . The circuit  104  may group the cache lines  124   a - 124   n  read from the circuit  106  into the blocks A-H. Each of the individual blocks A-H may be written to two of the memories  126   a - 126   h , with several blocks written substantially simultaneously along the paths  150   a - 150   h . For example, the block A may be written to both of the memories  126   a  and  126   b , the block B may be written to both of the memories  126   c  and  126   d , and so on. The RAID 1 configuration generally provides for fault tolerance of the stored information. For each memory pair, the blocks written into the pair may be recovered even if one of the memory components has failed. A RAID 1 configuration may be implemented with at least four of the memories  126   a - 126   h.    
         [0030]    Referring to  FIG. 6 , a block diagram of an example RAID 5 configuration is shown. The RAID 5 configuration may implement data striping with distributed parity. As before, the circuit  104  may read the cache lines  124   a - 124   n  from the circuit  106  in response to assertion of the signal OFFLOAD. The read information may be assembled into the blocks A-H. Each of the blocks A-H may then be striped. For example, the block A may become stripes A 0 , A 1  and A 2 , block B may become stripes B 0 , B 1  and B 3 , the block C may become stripes C 0 , C 2  and C 3 , the block D may become stripes D 1 , D 2  and D 3  and so on. The stripes of a given block may be written in order into a single memory  126   a - 126   d.    
         [0031]    A parity stripe may be calculated by the circuit  104  for all stripes in a same rank and then written into a single memory  126   a - 126   d . For example, a zero rank parity (e.g., 0 PARITY) may be generated from the stripe A 0 , a stripe B 0  and a stripe C 0  and written into the memory  126   d . A first rank parity (e.g., 1 PARITY) may be calculated for the stripe A 1 , a stripe B 1  and a stripe D 1  and written into the memory  126   c . The parity calculations may continue as each new rank is written. The RAID 5 configuration generally provides an ability to recover the stored information in the event of a single memory component  126   a - 126   d  failure. The use of the distributed parity may permit efficient use of the memories  126   a - 126   d . A RAID 5 configuration may be implemented with three or more of the memories  126   a - 126   d . Other RAID configurations may be implemented in the circuit  108  to meet the criteria of a particular application. 
         [0032]    The function performed by the diagrams of  FIGS. 1 and 3  may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). 
         [0033]    The present invention may also be implemented by the preparation of ASICs, FPGAs, or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
         [0034]    The present invention thus may also include a computer product which may be a storage medium including instructions which can be used to program a computer to perform a process in accordance with the present invention. The storage medium can include, but is not limited to, any type of disk including floppy disk, optical disk, CD-ROM, magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions. As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration. 
         [0035]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.