Abstract:
A method of fabricating a thin film transistor (TFT) flat panel display. The method merely comprises four mask steps of: (1) using the first mask process for patterning the first conductive layer/gate insulating layer/amorphous silicon layer of the TFT, (2) using the second mask process for defining the passivation layer and the etching stopper, (3) using the third mask process for forming the Source/Drain, and (4) using the fourth mask process for forming the pixel electrode, whereby simplifying the fabricating process of the TFT flat panel display.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method of fabricating a flat panel display. In particular, the present invention relates to a method of fabricating a thin film transistor (TFT) flat panel display.  
           [0003]    2. Description of the Related Art  
           [0004]    [0004]FIGS. 1A to  1 D illustrate the conventional method of fabricating a TFT liquid crystal flat panel display. Referring to FIG. 1A, a gate electrode  2  is formed on a substrate  1 , and then an insulating layer  3  is formed to cover the gate electrode  2 . Then, an amorphous silicon layer  40  and a silicon nitride  50  are formed on the insulating layer  3 . Referring to FIG. 1B, an etching stopper  5  is formed by etching the silicon nitride  50 . Referring to FIG. 1C, a doping silicon layer  6  (to be n+doped amorphous silicon) is formed on the etching stopper  5  and the amorphous silicon  40 . Referring to FIG. 1D, a metal layer is formed on the substrate  1 , and then is etched to form a source electrode  7  and a drain electrode  8 . Finally, a passivation layer  9  is formed. In the etching process, part of the metal layer and the doping silicon layer  6  are removed, and the etching stopper  5  is used for preventing the amorphous silicon layer  40  form etching damage.  
           [0005]    The conventional method can be used to fabricate TFT flat displays; however it still has the spaces for improvement and simplification.  
         SUMMARY OF THE INVENTION  
         [0006]    In order to improve and simplify the above-mentioned conventional manufacturing steps, the present invention proposes a new method of fabricating a TFT flat panel display, merely requiring four mask processes.  
           [0007]    The present invention proposes a method of fabricating a TFT flat display is characterized by: (1) using the first mask process for patterning the first conductive layer/gate insulating layer/amorphous silicon layer of the TFT, (2) using the second mask process for defining the passivation layer and the etching stopper, (3) using the third mask process for forming the Source/Drain, and (4) using the fourth mask process for forming the pixel electrode, whereby simplifying the fabricating process of the TFT flat panel display. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:  
         [0009]    [0009]FIGS. 1A to  1 D illustrate, in a cross-sectional view, the conventional method of fabricating a TFT liquid crystal flat panel display.  
         [0010]    [0010]FIGS. 2A to  2 D illustrate, in a top view, the fabricating process of the first embodiment according to the present invention.  
         [0011]    [0011]FIGS. 3A to  3 D illustrate, in a cross-sectional view, the fabricating process of the first embodiment according to the present invention.  
         [0012]    [0012]FIGS. 4A to  4 D illustrate, in a cross-sectional view, the fabricating process of the second embodiment according to the present invention.  
         [0013]    [0013]FIGS. 5A to  5 D illustrate, in a top view, the fabricating process of the third embodiment according to the present invention.  
         [0014]    [0014]FIGS. 6A to  6 D illustrate, in a cross-sectional view, the fabricating process of the third embodiment according to the present invention.  
         [0015]    [0015]FIGS. 7A to  7 D illustrate, in a top view, the fabricating process of the fourth embodiment according to the present invention.  
         [0016]    [0016]FIGS. 8A to  8 D illustrate, in a cross-sectional view, the fabricating process of the fourth embodiment according to the present invention.  
         [0017]    [0017]FIGS. 9A to  9 C illustrate, in a top view, the fabricating process of the fifth embodiment according to the present invention.  
         [0018]    [0018]FIGS. 10A to  10 C illustrate, in a cross-sectional view; the fabricating process of the fifth embodiment according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]    First Embodiment  
         [0020]    [0020]FIGS. 3A to  3 D illustrate, in a cross-sectional view, the fabricating process of the first embodiment according to the present invention. In FIGS.  3 A˜ 3 D, a thin film transistor (TFT) is formed on the I area (gate area) and a gate pad structure is formed on the II area. The I area in FIGS. 3A to  3 D corresponds to the cross section view along the A-A′ direction in FIGS. 2A to  2 D. The II area in FIGS. 3A to  3 D corresponds to the cross section view along the B-B′ direction in FIGS. 2A to  2 D.  
         [0021]    Referring to FIGS. 2A and 3A, a first conductive layer  101 , an insulating layer  102  and a semiconductor layer  103  are sequentially formed on a transparent substrate  100 . A scanning line structure (DL), a gate pad structure (DLp) and a gate structure (DLg) are formed after patterning the semiconductor layer  103 , the insulating layer  102  and the first conductive layer  101 . The gate pad structure DLp is formed at one end of the scanning line DL. The gate structure DLg extends from one side of the scanning line structure DL and the semiconductor layer  103  in the gate structure DLg serves as the channel layer of the TFT. In general, the substrate  100  is made of glass or quartz materials, the first conductive layer  101  is metal, the insulating layer  102  is silicon oxide (SiN x ) , and the semiconductor layer  103  is amorphous silicon serving as a gate electrode.  
         [0022]    Referring to FIG. 2B and 3B, a passivation layer  104  is formed to cover the scanning line structure DL, the gate structure DLg and the gate pad structure DLp on substrate  100 . The passivation layer  103  is then patterned to form a first and second openings op 1  and op 2  in the gate structure DLg and a third opening op 3  in the gate pad structure DLp to expose the corresponding semiconductor layer  103 . The above-mentioned a passivation layer is made of silicon nitride (SiN x ) or other organic polymer.  
         [0023]    Referring to FIG. 2C and 3C, a doping silicon layer  105  and a second conductive layer  106  are formed on substrate  100 . The conductive layer  106  is made of metal and the doping silicon layer is made of n+ doped silicon. The doping silicon layer  105  and the second conductive layer  106  are then patterned to form a signal line SL, a source S and a drain D on the gate structure DLg. The signal line SL is perpendicular to the scanning line structure DL. The doping silicon layer  105  in the source S and drain D are electrically connected to the semiconductor layer  103  through the openings op 1  and op 2 .  
         [0024]    The passivation layer  104  between op 1  and op 2  serves as an etching stopper IS (or an island etching stopper). The etching stopper IS is used to prevent the semiconductor layer  103  (over the gate structure DLg) from damages when etching the doping silicon layer  105  and the second conductive layer  106 .  
         [0025]    Referring to FIG. 2D and 3D, the semiconductor layer  103  and the insulating layer  102  in the gate pad structure DLp are etched to expose the conductive layer  101  in the opening op 3 . Then, a transparent electrode layer  107  is formed on the substrate  100  and covers the source S, the drain D and the gate pad structure DLp. Finally, the electrode layer  107  is patterned to form a pixel electrode PL electrically connected to the drain D and a dummy signal line FS covering the source S and the signal line SL. The etched electrode layer  107  is electrically connected to the first conductive layer  101  of the gate pad structure DLp.  
         [0026]    The above-mentioned electrode layer  107  is preferably made of indium tin oxide (ITO). The electrode layer  107  also covers the side walls of the conductive layers  106  of the source S and drain D.  
         [0027]    Second Embodiment  
         [0028]    [0028]FIGS. 4A to  4 D illustrate, in a cross-sectional view, the fabricating process of the second embodiment according to the present invention. The top view of the fabricating process of the second embodiment is the same-as that depicted in FIGS. 2A to  2 D. Only difference between the fabrication methods that described in first embodiment and in this present second embodiment is that a second insulating layer  202  forms on the semiconductor layer  103  to protect it.  
         [0029]    Referring to FIGS. 2A and 4A, a first conductive layer  101 , a first insulating layer  102 , a semiconductor layer  103  and a second insulting layer  202  are sequentially formed on a transparent substrate  100 . A scanning line structure (DL), a gate pad structure (DLp) and a gate structure (DLg) are formed after patterning the second insulting layer  202 , the semiconductor layer  103 , the first insulting layer  102  and the first conductive layer  101 . The second insulating layer  202  is preferably made of silicon nitride (SiN x ).  
         [0030]    Referring to FIGS. 2B and 4B, a passivation layer  104  is formed to cover the scanning line DL, the gate DLg and the gate pad DLp on the substrate  100 . The passivation layer  104  and the second insulating layer  202  are then patterned to form a first and second openings op 1  and op 2  on the gate structure DLg and a third opening op 3  on the gate pad structure DLp to expose the semiconductor layer  103 .  
         [0031]    Referring to FIGS. 2C and 4C, a doping silicon layer  105  and a second conductive layer  106  are formed on the substrate  100 . The second conductive layer  106  is made of metal and the doping silicon layer is made of n+ doped silicon. The doping silicon layer  105  and the second conductive layer  106  are patterned to form a signal line SL, a source S and a drain D on the gate structure DLg. The doping silicon layers  105  in the source S and drain D are electrically connected to the semiconductor layer  103  through the openings op 1  and op 2 .  
         [0032]    The passivation layer  104  and the second insulting layer  202 , between the first and second openings op 1  and op 2 , serve as a etching stopper IS (or a island etching stopper) for preventing the semiconductor layer  103  (channel layer) from damages when etching the second conductive layer  106  and the doping silicon layer  105 .  
         [0033]    Referring to FIGS. 2D and 4D, the semiconductor layer  103  and the first insulating layer  102  in the third opening op 3  on the gate pad structure DLp are removed first to reveal the first conductive layer  101  in the third opening op 3 . Then a transparent electrode layer  107  is formed on the substrate  100  and covers the source S, the drain D and the gate-pad structure DLp. Finally, the electrode layer  107  is patterned to form a pixel electrode PL which is electrically connected to the drain D through the openings op 2 , and a dummy signal line FS which is electrically connected to the source S through the opening op 1 , covering the signal line SL. The etched electrode layer  107  is electrically connected to the first conductive layer  101  of the gate pad structure DLp through the third openings op 3 .  
         [0034]    In this embodiment, a thin silicon nitride layer (the second insulating layer  202 ) is further formed on the semiconductor layer  103  to prevent the semiconductor layer from oxidation due to long-timely exposing to the air.  
         [0035]    Third Embodiment  
         [0036]    [0036]FIGS. 5A to  5 D illustrate, in a cross-sectional view, the fabricating process of the third embodiment according to the present invention. In FIGS.  6 A˜ 6 D, a thin film transistor (TFT) is formed on the I area (gate area) and a gate pad structure is formed on the II area. The I area in FIGS. 6A to  6 D correspond to the cross section view along the A-A′ direction in FIGS. 5A to  5 D. The II area in FIGS. 6A to  6 D correspond to the cross section view along the B-B′ direction in FIGS. 5A to  5 D.  
         [0037]    Referring to FIGS. 5A and 6A, a first conductive layer  101 , an insulating layer  102 , a semiconductor layer  103  are sequentially formed on a transparent substrate  100 . Then, a scanning line structure (DL), a gate pad structure (DLp) and a gate structure (DLg) are formed after patterning the semiconductor layer  103 , the insulating layer  102  and the first conductive layer  101 . The gate pad structure DLp is formed at one end of the scanning line DL. The gate structure DLg extends from one side of the scanning line DL and the semiconductor layer  103  in the gate structure DLg serves as a channel layer of the TFT. In general, the substrate  100  is made of glass or quartz materials, the first conductive layer  101  is metal, the insulating layer  102  is silicon oxide, and the semiconductor layer  103  is amorphous silicon serving as a gate electrode.  
         [0038]    Referring to FIG. 5B and 6B, a passivation layer  104  is formed to cover the scanning line DL, the gate structure DLg and the gate pad structure DLp on substrate  100 . The passivation layer  103  is then patterned to form a first and second openings op 1  and op 2  in the gate structure DLg and a third opening op 3  in the gate pad structure DLp to expose the corresponding semiconductor layer  103 . The above-mentioned a passivation layer is made of silicon nitride (SiN x ) or other organic polymer.  
         [0039]    Referring to FIG. 5C and 6C, a doping silicon layer  105  and a second conductive layer  106  are formed on the substrate  100 , and then are patterned to form a stack structure on the gate structure DLg, and a signal line SL perpendicular to the scanning line structure DL. The doping silicon layer  105  of the stack structure is electrically connected to the semiconductor layer  103  on the gate structure DLg through the openings op 1  and op 2 .  
         [0040]    Referring to FIGS. 5D and 6D, the semiconductor layer  103  and the first insulting layer  102  in the opening op 3  on the gate pad structure DLp are removed to reveal the first conductive layer  100  in the opening op 3  on the gate pad structure DLp. Then, a transparent electrode layer  107  is formed on the substrate  100 . Next, the electrode layer  107  and the stack structure (that is the second conductive layer  106  and the doping silicon layer  105  cover the gate structure DLg) are patterned to form a source S and a drain D over the gate structure DLg. Moreover, a pixel electrode PL is also formed by patterning the electrode layer  107 . The pixel electrode PL is electrically connected to the drain D. The patterned electrode  107  also covers the gate pad structure DLp and is electrically connected to the first conductive layer  101  of the gate pad structure DLp through the third opening op 3 .  
         [0041]    The above mentioned electrode layer  107  is preferably made of indium tin oxide ITO and uncovers the sidewalls of the second conductive layer  106  of the source S and drain D to reduce the size of the TFT channel.  
         [0042]    Fourth Embodiment  
         [0043]    [0043]FIGS. 7A to  7 D illustrate, in a top view, the fabricating process of the third embodiment according to the present invention. In FIGS. 8A to  8 D, a thin film transistor (TFT) is formed on the I area (gate area) and a gate pad structure is formed on the II area. The I area in FIGS. 8A to  8 D correspond to the cross-sectional view along the A-A′ direction in FIGS. 7A to  7 D. The II area in FIGS. 8A to  8 D correspond to the cross-sectional view along the B-B′ direction in FIGS. 7A to  7 D.  
         [0044]    Referring to FIGS. 7A and 8A, FIGS. 7B and 8B, a first conductive layer  101 , an insulating layer  102 , a semiconductor layer  103  and the passivation layer  104  are formed on a substrate  100 . Patterning of the above layers form a scanning line structure (DL), a gate pad structure (DLp) and a gate structure (DLg). The openings op 1 , op 2  and op 3  are formed on the gate structure DLg and the gate pad structure DLp to expose the semiconductor layer  103 . The detailed fabrication process is the same as that described in the first embodiment; therefore not described in this embodiment for brevity. Further, a second insulating layer (not shown in figures) can be formed on the semiconductor layer  103  for protection.  
         [0045]    Referring to FIGS. 7C and 8C, a second conductive layer  106  is formed and patterned on the passivation layer  104 . The patterned second conductive layer  106  serves as a signal line SL perpendicular to the scanning line structure DL.  
         [0046]    Referring to FIGS. 7D and 8D, a doping silicon layer  105  and a transparent electrode layer  107  are sequentially formed on the substrate  100  and cover the signal line SL and the gate structure DLg. Then, the doping silicon layer  105  and the electrode layer  107  are patterned to form a source S and a drain D on the gate structure DLg, and a first part TK 1  and a second part TK 2 , as depicted in FIGS. 7D and 8D. Furthermore, the first part TK 1  covers the signal line SL and is electrically connected to the source S. The second part TK 2  serves as a pixel electrode PL and electrically connects to the drain D. The doping silicon layers  105  of the source S and the drain D is electrically connected to the semiconductor layer  103  through the openings op 1  and op 2  on the gate respectively.  
         [0047]    Finally, the conductive layer  101  exposes in the opening op 3  by removing the insulating layer  102  and the semiconductor layer  103  on gate pad structure DLp.  
         [0048]    Fifth Embodiment  
         [0049]    [0049]FIGS. 9A to  9 C illustrate, in a top view, the fabricating process of the third embodiment according to the present invention. In FIGS. 10A to  10 C, a thin film transistor (TFT) is formed on the I area (gate area) and a gate pad structure is formed on the II area. The I area in FIGS. 10A to  10 C correspond to the cross-sectional view along the A-A′ direction in FIGS. 9A to  9 C. The II area in FIGS. 10A to  10 C correspond to the cross-sectional view along the B-B′ direction in FIGS. 9A to  9 C.  
         [0050]    Referring to FIGS. 9A and 10A, a first conductive layer  101 , an insulating layer  102  and a semiconductor layer  103  are formed on a substrate  100 . The above layers are patterned to form a scanning line structure (DL), a gate pad structure (DLp) and a gate structure (DLg) on the substrate  100 . The gate pad structure DLp is formed at one end of the scanning line structure DL. The gate structure DLg extends from one side of the scanning line structure DL and the semiconductor layer  103  in the gate structure DLg serves as a channel layer of the TFT.  
         [0051]    Referring to FIGS. 9B and 10B, a passivation layer  104  and a second conductive layer  106  are formed sequentially on the substrate  100 . Then, the second conductive layer  106  and the passivation layer  104  are patterned to cover the scanning line structure DL, the gate structure DLg and the gate pad structure DLp and further form a signal line SL. The signal line SL is perpendicular to the scanning line structure DL. In additional, a first and a second openings op 1  and op 2  are formed in the gate structure DLg and a third opening op 3  is formed in the gate pad DLp. The semiconductor layer  103  exposes in the openings op 1 , op 2  and op 3 .  
         [0052]    Referring to FIGS. 9C and 10C, a doping silicon layer  305  and a transparent electrode layer  107  are sequentially formed on the substrate  100 . The doping silicon layer is electrically connected to the semiconductor layer  103  through the openings op 1  and op 2 . Then, the electrode layer  107  and the doping silicon layer  305  are patterned to form a source S and a drain D on the gate structure DLg. Furthermore, the first part T 1  of the electrode layer  107  covers the signal line SL. The second part T 2  of the electrode layer  107  forms a part of the source S. The third part T 3  of the electrode layer  107  forms a pixel electrode PL, covering the drain D. The first conductive layer  101  exposes on the gate pad DLp by removing of the semiconductor layer  103  and the insulating  102  in the openings op 3 .  
         [0053]    Finally, while the invention has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed several embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.