Abstract:
An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This is a continuation of U.S. Ser. No. 09/511,020 filed Feb. 23, 2000, now issued as U.S. Pat. No. 6,297,705. 
     The present application may relate to application Ser. No. 09/511,019, filed Feb. 23, 2000, now U.S. Pat. No. 6,297,705 which is hereby incorporated by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a method and/or architecture for locking a data steam generally and, more particularly, to a method and/or architecture for locking an oscillator to a data stream. 
     BACKGROUND OF THE INVENTION 
     Conventional approaches for locking a data stream use Phase Lock Loops (PLL) and/or Delay Lock Loops (DLL) to lock or match a clock to an incoming data stream. 
     Such approaches typically require a very long training sequence and/or a continuous stream of data. Either requirement is incompatible with data communication systems like the Universal Serial Bus (USB), where the data packets can be short and bursty. For USB devices in particular, data may be present for only a very small percentage of the time, which could be less than 1%. 
     Delay Lock Loops and/or Phase Lock Loops can also suffer from the requirement of (i) long training sequences, (ii) requiring continuous input (e.g., cannot handle bursty data), and/or (iii) may need a precision timing component. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal. 
     The objects, features and advantages of the present invention include providing a method and/or architecture for locking an incoming data stream that may (i) precisely lock to a rate of the incoming data stream without an external precision timing element (e.g., without crystals, resonators, etc.), (ii) allow incoming data traffic to provide precision timing, (iii) provide multiple tuning phases during a single packet, and/or (iv) tune quickly (e.g., within one data packet). 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a block diagram of a preferred embodiment of the present invention; 
     FIG. 2 is a more detailed diagram of the oscillator circuit of FIG. 1; and 
     FIG. 3 is a detailed block diagram of the circuit of FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The structure of the circuit  100  generally comprises a control circuit  102  and an oscillator logic block (or circuit)  104 . The control circuit  102  may have an input  110  that may receive an incoming data stream (e.g., DATA), an input  112  that may receive a signal (e.g., PACKET), an output  114  that may present a control signal (e.g., CNTR), and an output  116  that may present a control signal (e.g., FACTOR), and an input  117  that may receive a signal (e.g., OUT). The incoming data stream DATA may be a series of data packets that may not necessarily be continuous. 
     The control circuit  102  generally comprises a control logic block (or circuit)  103  and a counter block (or circuit)  106 . The control logic block  103  may have an output  118  that may present an adjustment signal (e.g., C/F) and an output  119  that may present a control signal (e.g., CNTRS/S). The counter  106  may have an input  120  that may receive the signal C/F, an input  122  that may receive the signal CNTRS/S. 
     The oscillator logic circuit  104  may have an input  126  that may receive the signal CNTR, an input  128  that may receive the signal FACTOR and an output  130  that may present the signal OUT. In one example, the signal FACTOR may be implemented as a correction signal. However, the signal FACTOR may be implemented as an appropriate signal in order to meet the criteria of a particular implementation. The circuit  100  may perform measurements on the incoming data stream DATA that may produce the correction (or adjustment) signal FACTOR. The signal FACTOR may alter the frequency of oscillation of the signal OUT to match a multiple of the rate of the incoming data stream DATA. The circuit  100  may be a building block in a system (or chip) designed to automatically modify and lock the frequency oscillation of the signal OUT to a multiple of the rate of the incoming data signal DATA. An example of such an implementation may be found in applications such as the Universal Serial Bus (USB) (e.g., the Universal Serial Bus Specification  1 . 1 , published Sep. 23, 1998, which is hereby incorporated by reference in its entirety). 
     The circuit  100  may tune the oscillator logic  104  to match a multiple of the data rates of the incoming signal DATA. The circuit  100  may be implemented without precision timing elements. 
     Referring to FIG. 2, a more detailed diagram of the oscillator logic circuit  104  is shown. The structure of the oscillator logic circuit  104  generally comprises an oscillator control block (or circuit)  140  and an oscillator circuit  142 . In one example, the oscillator  142  may be implemented as a digitally controlled oscillator (DCO). In another example, the oscillator  142  may be implemented as a programmable oscillator. However, various oscillators may be implemented accordingly to meet the design criteria of a particular implementation. However, the oscillator  142  generally responds to a signal (e.g., DIGOUT) received at an input  144 . The signal DIGOUT may control the frequency of oscillation of the signal OUT. The signal DIGOUT may be implemented as a multi-bit digital word. The oscillator control circuit  140  may have an output  146  that may present the signal DIGOUT. The signal CNTR may determine when adjustments should be made in the frequency of oscillation of the signal OUT. The signal FACTOR may provide a value that may control coarse and/or a fine tuning of the signal DIGOUT. 
     Referring to FIG. 3, a more detailed diagram of the circuit  100  is shown. The counter circuit  106  generally comprises a calibration block (or circuit)  150  and a look-up table  152 . In one example, the calibration block  150  may comprise an n-bit counter, where n is an integer. However, the calibration block  150  may be implemented as other appropriate counters or circuits necessary to meet the criteria of a particular implementation. The calibration circuit  150  may have a start/stop input  122  that generally receives the signal CNTRS/S and an input  155  that may receive a feedback of the signal OUT. The calibration circuit  150  may also have an input  154  that may receive the signal C/F. The look-up table  152  may have an input  156  that may receive a signal from the counter block  150  and an input  158  that may receive the signal C/F. 
     The oscillator control block  140  generally comprises an oscillator setting block  160  and an adder block  162 . The adder block  162  may have an input  163  that may receive the signal FACTOR. The oscillator setting block  160  may have an input  164  that may receive the signal CNTR, an input  166  that may receive a signal ADD, an output  168  that may present a signal (e.g., ST) to an input  169  of the adder  162 . The adder  162  may present the signal ADD in response to the signal FACTOR and the signal ST. 
     Certain data communication systems require a precise local clock for accurate transmission (e.g., 1.5% accuracy in USB applications) and proper reception of incoming data. The circuit  100  may be implemented with a look-up table (as compared with conventional circuits that use a PLL). The look-up table  152  generally stores a fixed table of known characters that may determine how to adjust the frequency of oscillation of the signal OUT. The signal FACTOR may be an offset value that may control an adjustment in the frequency of oscillation of the signal OUT. 
     The circuit  100  may be used for generating the oscillator update signal DIGOUT by using the counter circuit  150  to calibrate the rate of oscillation of the signal OUT in response to the data rate of the incoming data stream DATA. Packet information (in the example of USB applications) may be used to distinguish appropriate data packets and/or key transitions. The look-up table  152  may hold correction terms based on interval counts and may generate the signal FACTOR that may be used to tune the frequency of oscillation of the signal OUT. The circuit  100  may be used to determine and adjust the frequency of oscillation of the signal OUT to be fixed to a multiple of the data rate of the signal DATA. The circuit  100  may be used to recover data without the conventional requirement of a crystal based oscillator or other external precision timing element. 
     Edges in the signal DATA may be recognized by the control circuit  102  to start and end various events. For example, during the early part of a data packet of the signal DATA, a coarse tuning may performed by the signal C/F. The coarse tuning may involve running the counter  150  for a pre-determined number of data edges (e.g., in the case of USB, this may be implemented to take place during the synchronizing phase where edges occur every bit time). After the target number of data bit times have passed, the counter circuit  150  is generally stopped. 
     If the clock signal OUT matches (e.g., is a multiple) the rate of the signal DATA, the count will equal the oversampling rate of the signal OUT, times the number of bit-times in the measurement. If the signal OUT is at the ideal value, the counter  150  will end at the target value, plus or minus an error due to such factors as jitter or phase error in the incoming data stream DATA, which may give an inherent ± 1  count uncertainty. 
     The output of the counter  150  may be fed directly to the look-up table  152  to find a correction factor for the particular rate of oscillation of the signal OUT. The value of the signal FACTOR may then be added to the present setting to produce a coarsely corrected frequency of oscillation. The new setting may be applied to the oscillator  142  to generate the updated frequency OUT. The new setting may remain until a subsequent adjustment is made, if such a subsequent adjustment is made. 
     Such a process may be repeated over a longer portion of the packet in order to achieve greater resolution in the correction term. The control logic block  103  may use known edges in the incoming data signal DATA to start and stop the counter block  150  another time, in one example, over a longer time period. The output of the counter  150  may then be directed to a fine-tune portion of lookup tables  152 . The value may then be added (or subtracted) from the oscillator frequency setting DIGOUT to produce the final frequency of oscillation of the signal OUT. 
     The control block  102  may also receive inputs from other circuitry that may provide useful information about the incoming data packets (e.g. whether a particular packet is erroneous or not, what portion of a particular packet is presently arriving, etc.). In one example, such information could be built into the control block  103 . In the case of USB, the USB Serial Interface Engine (SIE), already present for USB processing, may be used to supply information to the control block  103 . 
     Error checking may be made during the coarse and or fine tuning to avoid false tuning on noisy signals. Tuning may be limited (e.g., by information from the SIE) to certain appropriate types of data packets. For example, in USB, the appropriate data packets may be limited to token packets addressed to the device. In one example, the coarse tuning may occur on various packets. However, the fine tuning may be implemented, in one example, to occur during a token packet addressed to the device. 
     The circuit  100  may be tuned quickly (e.g., within one data packet). The circuit  100  may enable circuits that receive the signal OUT to run without precision timing elements (e.g., without crystals, resonators, etc.). Various options may be implemented for the tuning phases of the circuit  100 . For example, in place of the coarse/fine tuning described, the circuit  100  may be implemented with only one tuning phase with an increased accuracy. Alternatively, more than two tuning phases may be implemented to meet the design criteria of a particular implementation. 
     Additionally, in another example, some type of averaging may be implemented across several packets to reduce the number (or size) of particular frequency adjustments. 
     The present invention may provide a key block that may be used in connection with the oscillator logic block  104 . The present invention may provide a system cost saving by eliminating precision timing components (e.g., crystal, resonator, etc.) in data communications systems. While particular aspects of the present invention have been described in the context of USB applications, other applications may also be implemented. The circuit  100  may be used to achieve demanding cost targets, such as designing low-cost mouse controllers. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.