Abstract:
A method of forming a metal-insulator-metal (MIM) capacitor is disclosed. The method provides a three dimensional MIM capacitor having upgraded capacitance. A plurality of trenches are formed within the MIM capacitor to increase the charge storage area of the MIM capacitor without occupying additional planar area thereby upgrade the capacitance of the MIM capacitor and the integration.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method of forming a metal-insulator-metal capacitor, and more particularly to a method of forming a metal-insulator-metal capacitor having a three dimensional structure. 
     2. Description of the Related Art 
     Capacitor structures for semiconductor integrated circuits include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, and polysilicon-insulator-polysilicon (PIP) capacitors. Each of these capacitor structures includes at least one monocrystalline silicon layer or polycrystalline silicon layer which is used as a capacitor electrode. The use of silicon for the capacitor electrode, however, may result in a higher electrode resistance than is desired. 
     It is thus desirable to reduce the resistance of capacitor electrodes to decrease frequency dependence of the capacitor. Accordingly, metal-insulator-metal (MIM) thin film capacitors have been developed to provide low electrode resistances. Moreover, metal-insulator-metal capacitors can be used in integrated circuits requiring high speed performance. In addition, metal-insulator-metal thin film capacitors have been applied to advanced analog semiconductor devices because these capacitors have capacitance fluctuation rates dependent on voltage and temperature which are sufficiently low to provide desirable electrical characteristics. 
     In addition, there have been efforts to reduce thicknesses of dielectric layers for integrated circuit capacitors to thereby increase the performance of capacitors including these thinner dielectric layers. In particular, the capacitance of a capacitor can be increased by reducing the thickness of the dielectric layer between the two electrodes of the capacitor. There have also been efforts to increase capacitances by using dielectric layers having relatively high dielectric constants, and by increasing the surface areas of the capacitor electrodes. Furthermore, multi-wiring or multilevel interconnect processes have been applied to semiconductor manufacturing methods to facilitate the development of high-density integration and microelectronic technology. Accordingly, metal-insulator-metal thin film capacitors can be manufactured together with multi-wiring structures. FIG. 1 shows a cross-sectional diagram of a conventional metal-insulator-metal capacitor. The metal-insulator-metal capacitor comprising a lower aluminum electrode  102 , an insulating layer  106  and an upper aluminum electrode  108  is formed on a substrate  100 . A dielectric layer  110  and a titanium nitride layer  104  are also shown in this figure. In view of the demands of high integration and large capacitance, the conventional planar MIM capacitor shown in FIG. 1 will not meet the requirement of modern integrated circuits gradually. Thus it is very necessary to provide a novel process of forming MIM capacitors which can provide a new structure of the MIM capacitors having large capacitance as well as high integration of the integrated circuit. It is toward these goals that this invention specially directs. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide a process of forming a three dimensional MIM capacitor. 
     It is another object of this invention to provide a MIM capacitor having a three dimensional structure and an upgraded capacitance. 
     It is a further object of this invention to provide a three dimensional MIM capacitor which can effectively upgrade the integration of integrated circuits. 
     To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method comprising: providing a substrate having a first region and a second region; forming a first conductive layer over said substrate and a second conductive layer over said first conductive layer; transferring a plurality of trench patterns into said second conductive layer and said first conductive layer to form a plurality of trenches in said first region and said second region; conformally forming a dielectric layer over said second conductive layer and said first conductive layer; forming a third conductive layer over said dielectric layer; forming a photoresist layer to cover said first region; removing said third conductive layer on said second region to expose said dielectric layer on said second region; removing said dielectric layer on said second region to expose said second conductive layer and said first conductive layer on said second region; etching through the bottoms of said trenches in said second region to expose said substrate; and removing said photoresist layer. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 shows a cross-sectional diagram of a conventional metal-insulator-metal capacitor; 
     FIG. 2A shows a substrate having two conductive layers sequentially formed thereon; 
     FIG. 2B shows a result of etching the structure shown in FIG. 2A to form trenches therein; 
     FIG. 2C shows a result of conformally forming a dielectric layer and a conductive layer over the structure shown in FIG. 2B thereon; 
     FIG. 2D shows a result of removing the conductive layer in a periphery region; and 
     FIG. 2E shows a result of removing the exposed dielectric layer shown in FIG.  2 D and sequentially etching through the conductive layer to expose the substrate. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     It is to be understood and appreciated that the process steps and structures described below do not cover a complete process flow. The present invention can be practiced in conjunction with various integrated circuit fabrication techniques that are used in the art, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the present invention. 
     The present invention will be described in detail with reference to the accompanying drawings. It should be noted that the drawings are in greatly simplified form and they are not drawn to scale. Moreover, dimensions have been exaggerated in order to provide a clear illustration and understanding of the present invention. 
     Referring to FIG. 2A, conductive layers  202  and  204  are sequentially formed over a substrate  200 . The substrate  200  comprises, but is not limited to: a silicon dioxide substrate. The substrate  200  can also comprise other insulating substrate such as a borophosphosilicate (BPSG) substrate as well as low-k dielectric substrate such as a fluorosilicate glass (FSG) substrate, a hydrogen silsesquioxane (HSQ) substrate, a methyl silsesquioxane (MSQ) substrate and a benzocyclobutene (BCB) substrate. Furthermore, the substrate  200  usually comprises a multilevel interconnect structure which is not shown for simplicity. The conductive layer  202  preferably comprises, but is not limited to: an aluminum layer as well as an aluminum alloy layer. Other conductive layer such as a copper layer and a copper alloy layer should not be excluded. The conductive layer  202  can be formed by using conventional methods such as physical vapor deposition. The conductive layer  202  has a thickness of from about 7000 angstrom to about 10000 angstrom, and the conductive layer  202  preferably has a thickness of about 9000 angstrom. The conductive layer  204  comprises, but is not limited to: a titanium nitride layer. A titanium/titanium nitride (Ti/TiN) layer and a tantalum/tantalum nitride (Ta/TaN) layer can also be used. The conductive layer  204  can be formed by using conventional physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes. The conductive layer  204  has a thickness of from about 1000 angstrom to about 3000 angstrom, and the conductive layer  204  preferably has a thickness of about 2000 angstrom. 
     Referring to FIG. 2B, the conductive layers  202  and  204  are etched to form trenches by using conventional etching processes such as dry etching. The etching process is preferably, but is not limited to: a reactive ion etching process. These trenches have a depth of from about 6000 angstrom to about 11000 angstrom. It is noted that the depths set forth are exemplary only, the depth actually depends on the total thickness of the conductive layers  202  and  204 . The conductive layer  202  should not be etched through to expose the substrate  200 . The thickness between the bottom of these trenches and the interface of the conductive layer  202  and the substrate  200  is preferably about 2000 angstrom. 
     Referring to FIG. 2C, a dielectric layer  206  and a conductive layer  208  are sequentially formed over the structure shown in FIG.  2 B. The dielectric layer  206  comprises, but is not limited to: a silicon dioxide layer or a silicon nitride layer formed by conventional chemical vapor deposition such as plasma enhanced chemical vapor deposition. The dielectric layer  206  has a thickness of from about 100 angstrom to about 1000 angstrom. The conductive layer  208  comprises, but is not limited to: an aluminum layer or an aluminum alloy layer. A copper layer or a copper alloy layer can also be used. The conductive layer  208  can be formed by conventional methods such as physical vapor deposition. The conductive layer  208  has a thickness of from about 500 angstrom to about 10000 angstrom. The conductive layer  208  preferably has a thickness of about 2000 angstrom. 
     Referring to FIG. 2D, a region of the structure shown in FIG. 2C used to form MIM capacitors is covered by a photoresist layer  210  and the uncovered portion of the conductive layer  208  is removed by conventional methods such as etching. The etching method used to remove the exposed conductive layer  208  preferably comprises, but is not limited to: a reactive ion etching process. The exposed region of the structure shown in FIG. 2C is used to form periphery metal lines of a multilevel interconnect structure. 
     Referring to FIG. 2E, the exposed portion of the dielectric layer  206  is removed and then the underlying conductive layer  202  is further etched through to expose the substrate  200 . To form the structure shown in FIG. 2E, the exposed portion of the dielectric layer  206  is first removed by conventional etching methods such as anisotropic dry etching. This dry etching method is preferably a reactive ion etching process. The photoresist layer  210  together with the photoresist pattern used to cover the conductive layer  204  are finally removed. The remaining conductive layers  202  and  204  in this periphery region are used to form metal lines of the multilevel interconnect structure. The conductive layer  202  and  208  are the two electrodes of the MIM capacitor of this invention and the dielectric layer  206  is the insulating layer of the MIM capacitor. It is noted that although there are only two trenches in this MIM capacitor shown in FIG. 2E, this MIM capacitor can still has more than two trenches filled with the conductive layers  202 ,  208  and the dielectric layer  206 . The more the filled trenches, the larger the capacitance this MIM capacitor has. 
     The invention integrates the formations of the periphery metal lines and the three-dimensional MIM capacitor thereby not only reduces the process step needed, but also increases the capacitance of the MIM capacitor without occupying more area. The integration of this integrated circuit can be upgraded. Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.