Abstract:
The invention provides a control apparatus, a main board, and a computer wherein, the control apparatus is applied in the computing device. The computing device includes a main board, a standby power supply, and a switching means configured between the standby power supply and the at least one electronic element. The control apparatus includes a signal receiving module, a judging module for judging whether the computing device is in a turn-off mode according to the signal, and a controlling module. The standby power supply is connected with the main board through the control apparatus and the switching switch respectively, so that after the turn-off of the computer, the control apparatus switches off the connection between the standby power supply and the main board, to reduce the power consumption of the main board after the turn-off.

Description:
BACKGROUND 
       [0001]    The invention relates to a control apparatus, a main board and a computer. 
         [0002]    In existing computer systems, a main power supply supplies power to the system in both of a running (S 0 ) state and a CPU stopping operation (S 1 ) state, while a standby power supply supplies power to the system in all of the running (S 0 ) state, the CPU stopping operation (S 1 ) state, a stopping operation (S 3 ) state for all components except memory, a sleep state (S 4 ) or a shut-down state (S 5 ). That is, when the system is in the turn-off mode (S 4  sleep state or S 5  shut-down state), the elements (such as devices like SB, SIO, network card, etc.) connected with the standby power supply are still consuming power, so that the system still consumes some power in the turn-off mode. 
       SUMMARY 
       [0003]    The object of the invention is to provide a control apparatus, a main board and a computer, to reduce the power consumption of the existing computer system in the turn-off mode. The control apparatus of the invention is applied in the computing device, wherein, said computing device comprising: a main board configured with a plurality of electric elements; a standby power supply, for supplying power to at least one electronic element of said plurality of electronic elements; a switching means, configured between said standby power supply and said at least one electronic element, said control apparatus comprising: a signal receiving module, for receiving a signal representing said computing device mode; a judging module, for judging whether said computing device is in a turn-off mode according to said signal; a controlling module, for switching off the connection between said main board and said standby power supply by said switching means when said judging module judges said computing device is in a turn-off module. 
         [0004]    Said signal is a turn-on signal or a turn-off signal; if said signal receiving module receives a turn-off signal. 
         [0005]    Said judging module judges the current mode of said computing devices is the turn-off mode according to said turn-off signal. 
         [0006]    Said controlling module particularly includes: an enable signal writing unit, for writing a switch-off enable signal according to said turn-off mode; a controlling unit, for executing an operation for switching off the connection between the standby power supply and the main board according to said switch-off enable signal. 
         [0007]    Said control apparatus is a logic circuit, and includes: a signal receiving pin, for receiving said turn-on signal or said turn-off signal; an enable signal transmitting pin, for transmitting an enable signal; a control signal transmitting pin, for transmitting a control signal; said signal receiving module, particularly used for receiving said turn-on signal or said turn-off signal from said signal receiving pin; said enable signal writing unit, used for writing said switch-off enable signal through said enable signal transmitting pin, according to said turn-off mode. 
         [0008]    If said signal receiving module receives a turn-on signal, said judging module judges the current mode of said computing device is a turn-on mode according to said turn-on signal, and the enable signal writing unit of said controlling module is used for writing a switch-on enable signal according to said turn-on mode; and said controlling unit is used for executing an operation for switching on the connection between the standby power supply and the main board according to said switch-on enable signal. 
         [0009]    The enable signal written by said enable signal writing unit is generated by a program embedded in the BIOS. 
         [0010]    Said turn-off mode is the S 4  sleep state or the S 5  shut-down state. 
         [0011]    The invention further provides a main board, including a control apparatus, said control apparatus comprising: a signal receiving module, for receiving a signal representing computing device mode; a judging module, for judging whether said computing device currently is in the turn-off mode according to said signal; a controlling module, for switching off the connection between said main board and said standby power supply when said judging module judges said computing device currently is in the turn-off mode. 
         [0012]    Said signal is a turn-on signal or a turn-off signal; if said signal receiving module receives a turn-off signal, said judging module judges the current mode of said computing devices is the turn-off mode according to said turn-off signal; 
         [0013]    Said controlling module particularly includes: an enable signal writing unit, for writing a switch-off enable signal according to said turn-off mode; a controlling unit, for executing an operation for switching off the connection between the standby power supply and the main board according to said switch-off enable signal. 
         [0014]    Said control apparatus is a logic circuit, including: a signal receiving pin, for receiving said turn-on signal or said turn-off signal; an enable signal transmitting pin, for transmitting an enable signal; a control signal transmitting pin, for transmitting a control signal; said main board further including: a first switch, connected with said standby power supply, for switching off or switching on according to said control signal, to switch off or switch on the connection between said standby power supply and the main board; said signal receiving module, particularly used for receiving said turn-on signal or said turn-off signal from said signal receiving pin; said enable signal writing unit, used for writing said switch-off enable signal through said enable signal transmitting pin, according to said turn-off mode; said controlling unit, particularly used for generating a switch-off control signal, and transmitting said switch-off control signal to said first switch through said control signal transmitting pin; said first switch switches off according to said switch-off control signal, to switch off the connection between the standby power supply and the main board. 
         [0015]    If said signal receiving module receives a turn-on signal, said judging module judges the current mode of said computing device is a turn-on mode according to said turn-on signal, and the enable signal writing unit of said controlling module is used for writing a switch-on enable signal according to said turn-on mode; and said controlling unit is used for executing an operation for switching on the connection between the standby power supply and the main board according to said switch-on enable signal. 
         [0016]    The enable signal written by said enable signal writing unit is generated by a program embedded in the BIOS. 
         [0017]    Said turn-off mode is the S 4  sleep state or the S 5  shut-down state. 
         [0018]    The invention further provides a computer, including a control apparatus, said control apparatus comprising: a signal receiving module, for receiving a signal representing computing device mode; a judging module, for judging whether said computer system currently is in a turn-off mode according to said signal; a controlling module, for switching off the connection between the main board of the computer and the standby power supply when said judging module judges said computer system currently is in the turn-off mode. 
         [0019]    Said signal is: a turn-on signal or a turn-off signal; if said signal receiving module receives the turn-off signal, said judging module judges the current mode of the system is turn-off mode according to said turn-off signal; said controlling module particularly includes: an enable signal writing unit, for writing a switch-off enable signal according to said turn-off mode; a controlling unit, for executing an operation for switching off the connection between the standby power supply and the main board according to said switch-off enable signal. 
         [0020]    Said control apparatus is a logic circuit, including: a signal receiving pin, for receiving said turn-on signal or said turn-off signal; an enable signal transmitting pin, for transmitting an enable signal; a control signal transmitting pin, for transmitting a control signal; said main board further including: a first switch, connected with said standby power supply, for switching off or switching on according to said control signal, to switch off or switch on the connection between said standby power supply and the main board; said signal receiving module, particularly used for receiving said turn-on signal or said turn-off signal from said signal receiving pin; said enable signal writing unit, use for writing said switch-off enable signal through said enable signal transmitting pin, according to said turn-off mode; said controlling unit, particularly used for generating a switch-off control signal, and transmitting said switch-off control signal to said first switch through said control signal transmitting pin; said first switch switches off according to said switch-off control signal, to switch off the connection between the standby power supply and the main board. 
         [0021]    If said signal receiving module receives a turn-on signal, said judging module judges the current mode of said system is a turn-on mode according to said turn-on signal, and the enable signal writing unit of said controlling module is used for writing a switch-on enable signal according to said turn-on mode; and said controlling unit is used for executing an operation for switching on the connection between the standby power supply and the main board according to said switch-on enable signal. 
         [0022]    The enable signal written by said enable signal writing unit is generated by a program embedded in the BIOS. 
         [0023]    Said turn-off mode is the S 4  sleep state or the S 5  shut-down state. 
         [0024]    Compared to the existing technology, the invention has the following effects: 
         [0025]    The invention connects the standby power supply with the main board through the control apparatus and the switching switch, and switches on or switches off the connection between the standby power supply and the main board by the control apparatus controlling the switch-on and switch-off states of the switching switch, so that after the turn-off of the computer, the control apparatus switches off the connection between the standby power supply and the main board, to realize the purpose for reducing the power consumption of the main board after the turn-off. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]      FIG. 1  is a structural schematic diagram of the control apparatus of the invention; 
           [0027]      FIG. 2  is a structural schematic diagram of the logic circuit of an embodiment of the invention; 
           [0028]      FIG. 3  is a structural schematic diagram of the connection between the control apparatus and the main board according to an embodiment of the invention; 
           [0029]      FIG. 4  is a structural schematic diagram of an embodiment of the logic circuit of the invention; 
           [0030]      FIG. 5  is a timing schematic diagram of power-on when ES_EN=1 according to the invention; 
           [0031]      FIG. 6  is a timing schematic diagram of power-on when ES_EN=0 according to the invention; 
           [0032]      FIG. 7  is a timing schematic diagram of turn-off according to the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    The embodiment of the invention reduces the power consumption in the turn-off mode by a control apparatus, mainly using the control apparatus to control the switch-on and off states of the switching switch connected between the standby power supply and the main board. By switching off the connection between the standby power supply and the devices such as SB, IO, LAN, etc., the purpose for reducing the power consumption of the main board is realized. 
         [0034]    The embodiments of the invention will be further explained in detail in combination with the drawings. 
         [0035]    With reference to  FIG. 1 ,  FIG. 1  is a structural schematic diagram of the control apparatus of the invention, including: 
         [0036]    a signal receiving module, for receiving a signal representing a computing device mode, the received signal being a turn-on signal or a turn-off signal; 
         [0037]    a judging module, for judging whether the system currently is in the turn-off mode according to said signal. If the signal is a turn-off signal, the current mode of the system is determined as the turn-off mode. The turn-off mode of the embodiment is: the sleep (S 4 ) state or the shut-down (S 5 ) state. That is, if the signal is a turn-off signal, the system may be currently in the S 4  state, or may be currently in the S 5  state. Otherwise, if the signal is a turn-on signal, the current mode of the system is determined as the turn-on mode. The turn-on mode includes a network waking state. 
         [0038]    A controlling module is used for switching off the connection between the main board and the standby power supply when said judging module judges the system currently is in the turn-off mode. 
         [0039]    The control apparatus of the invention can be realized by an apparatus such as a microprocessor or a logic circuit or else which can generate control signals. 
         [0040]    When the control apparatus of the invention is realized by a microprocessor, it can be realized directly by utilizing the structure as shown in  FIG. 1 . 
         [0041]    When the control apparatus of the invention is realized by a logic circuit, if the judging module judges the current mode of the system is turn-off mode according to the turn-off signal, then the controlling module particularly includes: 
         [0042]    an enable signal writing unit, for writing a switch-off enable signal according to said turn-off mode; 
         [0043]    a controlling unit, for executing an operation for switching off the connection between the standby power supply and the main board according to said switch-off enable signal. 
         [0044]    In addition of the turn-off signal, the signal further includes a turn-on signal, thus, if said judging module judges the system currently is in a turn-on mode according to the turn-on signal, the enable signal writing unit of said controlling module is used for writing a switch-on enable signal according to said turn-on mode. 
         [0045]    And said controlling unit is used for executing an operation for switching on the connection between the standby power supply and the main board according to said switch-on enable signal. 
         [0046]    The structural schematic diagram including the structure of the logic circuit of an embodiment for processing the above turn-on signal and the turn-off signal is shown in  FIG. 2 . 
         [0047]    The enable signal written by said enable signal writing unit is generated by a program embedded in the BIOS. 
         [0048]    With reference to  FIG. 3 ,  FIG. 3  is a structural schematic diagram of the connection between the logic circuit and the main board of the embodiment of the invention, and the  FIG. 3  includes: a main power supply, a standby power supply, a main board, a logic circuit and a switch. The main power supply and the standby power supply both are parts of the ATX power supply. The main power supply is directly connected with the main board, for supplying power to the main board. The standby power supply is connected with the main board through the switch and the logic circuit respectively. A turn-on circuit and a turn-off circuit (not shown in drawings) on the main board are connected with the logic circuit respectively, for sending a turn-on signal and a turn-off signal to the logic circuit. For clearer representation, the logic circuit is configured on the main board, independent from the main board. 
         [0049]    In the embodiment, the main power supply and the standby power supply in the ATX power supply can be integrated together, or can be physically and/or spatially separate. The person skilled in the art can appreciate that the main power supply and the standby power supply can operate independently. 
         [0050]    After the logic circuit receives the turn-on signal, the logic circuit sends a switch-on control signal to the switch, to switch on the circuit, so as to connect the standby power supply and the main board. Then, after some logical processes, the logic circuit receives the turn-on signal sent from the main board, and after some logical processes, the logic circuit turns on the main power supply, and the main power supply supplies power to the main board. 
         [0051]    When pressing a turn-off button, after the logic circuit receives the turn-off signal, it is determined whether the current mode is the sleep (S 4 ) mode or the shut-down (S 5 ) mode, if it is the S 4  mode or the S 5  mode, the logic circuit sends a switch-off control signal to the switch, to switch off the switch, in order to disconnect the standby power supply from the main board, so as to stop supplying power to devices on the main board connected with the standby power supply, which reduces the power consumption of the main board. 
         [0052]    With reference to  FIG. 4 ,  FIG. 4  is a structural schematic diagram of an embodiment of the logic circuit of the invention. A south bridge (SB), an IO and so on are connected with the ATX power supply through a switch SW 1 . A network card is connected with the ATX power supply through a switch SW 2 . The SW 1  and the SW 2  are connected with pins  12  and  11  of the logic circuit respectively. A part of signals of the logic circuit are defined as shown in Table 1. 
         [0000]    
       
         
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Signal 
                 Definition 
               
               
                   
               
             
             
               
                 ES_EN 
                 Energy saving enable signal, the high level of which is enable, the 
               
               
                   
                 low level of which is disable, connected with the GPO of the IO or the 
               
               
                   
                 south bridge, the power of which is supplied from a resume well. If 
               
               
                   
                 the BIOS is set so that the power supply energy saving is 
               
               
                   
                 required, then the GPO is set as high in S4 or S5 state; otherwise, 
               
               
                   
                 the GPO is set as low. 
               
               
                   
                 When ES_EN = 0, +5VSB_CTL# defaults as low the SW 1 is switched 
               
               
                   
                 on, there is a default of +5VSB power supply on the main board; 
               
               
                   
                 When ES_EN = 1, +5VSB_CTL# defaults as high, the SW 1 is 
               
               
                   
                 switched off, there is a default of no +5VSB power supply on the 
               
               
                   
                 main board; 
               
               
                 POWER_BT_L 
                 Power supply button input signal, the turn-on button is connected, the 
               
               
                   
                 default is at high level, when the turn-on button is pressed, the 
               
               
                   
                 default is at low high (ATX_+5VSB power supply). 
               
               
                 POWER_BT R 
                 Power supply button signal input to the south bridge or the IO 
               
               
                   
                 (+5VSB power supply) 
               
               
                 +5VSB_CTL# 
                 Signal for controlling the SW1 to be switched on or off, when 
               
               
                   
                 5VSB_CTL# = 1, the SW1 is switched off, +5VSB is not supplied; 
               
               
                   
                 when 5VSB_CTL# = 0, the SW1 is switched on, +5VSB and 
               
               
                   
                 ATX_+5VSB are connected. 
               
               
                 PCI_EXP_WAKE# 
                 Networkawake input signal 
               
               
                 ICH_WAKE# 
                 Network awake signal input to the south bridge 
               
               
                 +5VSB_CTL# 
                 Control signal of the SW1 
               
               
                 WOL_EN# 
                 Control signal of the SW2 
               
               
                   
               
             
          
         
       
     
         [0053]    The logical functions of +5VSB_CTL# and WOL_EN# are shown in the Table 2 below. 
         [0000]    
       
         
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
             
             
               
                 +5VSB_CTL#/WOL_EN# 
                 SW1/ SW2 
               
               
                 1 
                 OFF (+5VSB OFF) (switched off) 
               
               
                 0 
                 ON (+5VSB ON) (switched on) 
               
               
                   
               
             
          
         
       
     
         [0054]    With reference to  FIG. 5 ,  FIG. 5  is a timing schematic diagram of power-on when ES_EN=1 according to the invention. When ES_EN (Energy saving enable)=1, +5VSB_CTL# defaults as high, the SW  1  is switched off, there is a default of no +5VSB power supply on the main board; When turned-on, the logic circuit responds to the turn-on button signal POWER_BT_L, as follows: 
         [0055]    1. The signal receiving module of the logic circuit receives a low pulse signal of POWER_BT_L, the judging module of the logic circuit judges the system is in the turn-on mode according to the low pulse signal of POWER_BT_L; 
         [0056]    2. The controlling unit of the logic circuit pulls the +5VSB_CTL# signal to low, the SW 1  is switched on, and there is +5VSB power supply on the main board; 
         [0057]    3. After the controlling unit of the logic circuit detects +5VSB, it is delayed by 100 ms, pulling the RSMRST# signal to high; 
         [0058]    4. The controlling unit of the logic circuit pulls the POWER_BT_R signal to low, notifying the south bridge or the IO; 
         [0059]    5. After the south bridge receives the POWER_BT_R signal, through some logics, the SLP_S 3 # signal is pulled to high, notifying the controlling unit of the logic circuit; 
         [0060]    6. The controlling unit of the logic circuit pulls the PS_ON# signal to low, the ATX power supply is turned on; 
         [0061]    7. The enable writing signal writing unit of the controlling module writes a switch-on enable signal, i.e., writes the enable signal (ES_EN)  0  set by the BIOS, at this time, the POWER_BT_L and the POWER_BT_R are connected, and at this time, the function of the turn-on button is consistent with the existing system definition. 
         [0062]    When ES_EN=0, the +5VSB_CTL# is low, the SW 1  is switched on, the standby power supply of the ATX is connected with the standby power supply of the main board, supplying power to the south bridge and the IO; 
         [0063]    Note: when first turned-on, the default value ES_EN=0. Then, after each turn-off, the BIOS will set ES_EN as 1, with the turn-off timing as follows. 
         [0064]    With reference to  FIG. 6 ,  FIG. 6  is a timing schematic diagram of power-on when ES_EN=0 according to the invention. When ES_EN=0, +5VSB_CTL# defaults as low, the SW  1  is switched on, there is default +5VSB power supply on the main board, the power-on timing at this time is consistent with the existing system as follows: 
         [0065]    1. The signal receiving module of the logic circuit receives a low pulse signal of POWER_BT_L, the judging module of the logic circuit judges the system is in turn-on mode according to the low pulse signal of POWER_BT_L; 
         [0066]    2. The controlling unit of the logic circuit pulls the POWER_BT_R signal to low, notifying the south bridge or the IO; 
         [0067]    3. The south bridge pulls the SLP_S 3 # signal is pulled to high, and notifies the controlling unit of the logic circuit; 
         [0068]    4. The controlling unit of the logic circuit pulls the PS_ON# signal to low, the ATX power supply is turned on; 
         [0069]    5. The enable writing signal writing unit of the controlling module writes a switch-on enable signal, i.e., writes the enable signal (ES_EN)  0  set by the BIOS, at this time, the POWER_BT_L and the POWER_BT_R are connected, and at this time, the function of the turn-on button is consistent with the existing system definition. 
         [0070]    Since there is a network waking function in the modern computer application, the network connection supplied by a standby power supply is processed separately, which is divided into two running modes, i.e., network waking function and non network waking function. 
         [0071]    When ES_EN=1 (the SW 1  is switched off, the main board is not connected with the standby power supply), WOL_EN#=0, the SW 2  is switched on, the ATX — 5VSB and the LAN — 5VSB are connected, and the system supports the network waking function. The power-on timing for waking will be explained as follows: 
         [0072]    1. The signal receiving module of the logic circuit receives a low pulse signal of PCI_EXP_WAKE#, the judging module of the logic circuit judges the system as the network waking state according to the low pulse signal of PCI_EXP_WAKE#; 
         [0073]    2. The controlling unit of the logic circuit pulls the +5VSB_CTL# signal to low, the SW 1  is switched on, and there is +5VSB power supply on the main board; 
         [0074]    3. After the controlling unit of the logic circuit detects +5VSB, it is delayed by 100 ms, pulling the RSMRST# signal to high; 
         [0075]    4. The controlling unit of the logic circuit pulls the ICH_WAKE# signal to low, notifying the south bridge or the IO; 
         [0076]    5. The south bridge pulls the SLP_S 3 # signal to high, and notifies the controlling unit of the logic circuit; 
         [0077]    6. The controlling unit of the logic circuit pulls PS_ON# signal to low, the ATX power supply is turned on; 
         [0078]    7. The enable writing signal writing unit of the controlling module writes a switch-on enable signal, i.e., writes the enable signal (ES_EN)  0  set by the BIOS, there is default +5VSB power supply on the main board, and the waking timing at this time is consistent with the waking timing of the existing system. 
         [0079]    When ES_EN=0 (the SW 1  is switched off, the main board is connected with the standby power supply), WOL_EN#=0, the timing for network waking will be explained as follows: 
         [0080]    1. The signal receiving module of the logic circuit receives a low pulse of PCI_EXP_WAKE#, the judging module of the logic circuit judges the system as network waking state according to the low pulse signal of PCI_EXP_WAKE#; 
         [0081]    2. The controlling unit of the logic circuit pulls the ICH_WAKE# signal to low, notifying the south bridge or the IO; 
         [0082]    3. The south bridge pulls the SLP_S 3 # signal to high, and notifies the controlling unit of the logic circuit; 
         [0083]    4. The controlling unit of the logic circuit pulls the PS_ON# signal to low, the ATX power supply is turned on; 
         [0084]    5. The enable writing signal writing unit of the controlling module writes a switch-on enable signal, i.e., writes the enable signal (ES_EN)  0  set by BIOS. 
         [0085]    When WOL_EN#=1, the SW 2  is switched off, and the system does not support the network waking function. 
         [0086]    With reference to  FIG. 7 ,  FIG. 7  is a timing schematic diagram of the turn-off of the invention, as follows: 
         [0087]    1. The signal receiving module of the logic circuit receives a low pulse signal of POWER_BT_L; 
         [0088]    The low pulse signal of POWER_BT_L is received by the signal receiving pin  2 . 
         [0089]    2. The controlling unit of the logic circuit pulls the POWER_BT_R signal to low, notifying the south bridge or the IO of the turn-off; 
         [0090]    3. The judging module of the logic circuit judges the current mode of the system according to BIOS mode signal, the BIOS will generate the mode signal of the current system according to the POWER_BT_R signal, the judging module judges the mode of the current system according to the content of the mode signal; 
         [0091]    When it is determined that the system is in the S 3  state, the enable signal writing unit of the controlling module writes the switch-on enable signal through the enable signal transmitting pin  6 , i.e., writes the enable signal (ES_EN)  0  set by the BIOS; if it is determined as the S 4  or the S 5  mode, the enable signal writing unit of the controlling module writes the switch-off enable signal through the enable signal transmitting pin  6 , i.e., writes the enable signal (ES_EN)  1  set by the BIOS; 
         [0092]    4. The south bridge pulls the SLP_S 3 # signal to low, and notifies the controlling unit of the logic circuit; 
         [0093]    5. The controlling unit of the logic circuit pulls PS_ON# signal to high. The ATX main power supply is switched off; 
         [0094]    6. If ES_EN=0, the timing ends, still remaining +5VSB power supply; if ES_EN=1, the controlling unit of the logic circuit pulls the RSMRST# signal to high, 
         [0095]    7. If ES_EN=0, the timing ends, still remaining +5VSB power supply; if ES_EN=1, the controlling unit of the logic circuit pulls the +5VSB_CTL# signal to high, and the +5VSB_CTL# control signal (switch-off control signal) pulled to high is transmitted to the SW 1  through the control signal transmitting pin  12 , the SW 1  is switched off according to the switch-off control signal, and the ATX — 5VSB and the +5VSB are disconnected. 
         [0096]    The apparatus of the invention can effectively reduce the power consumption of the main board in the turn-off mode. In the Energy star* 2007 classification /Limit, it is specified that the power consumption of the main board in the turn-off mode is &lt;2 W (when not supporting the network waking WOL), while in the case of using the logic circuit to realize the same function, it can be realized that the power consumption of the main board is &lt;0.1 W. 
         [0097]    The above explanation is only with respect to the preferred embodiments of the invention, and it is to be noted that for the person skilled in the art, without departing from the principal of the invention, the modifications and the variations can be considered to be within the protection scope of the invention.