Abstract:
A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device.

Description:
FIELD 
     The present invention relates to semiconductor devices including a doped substrate and a method for manufacturing the same, and more particularly, the present invention relates to semiconductor devices including field effect transistors and halo doped regions, and a method for making the same. 
     BACKGROUND 
     In semiconductor manufacturing, complementary metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits, such as CPUs, memory, storage devices, and the like. In FETs, a channel region may be formed in an n-doped or p-doped semiconductor substrate on which a gate structure is created. The overall fabrication process may include forming a gate structure over a channel region. The channel region may connect a source region and a drain region within the substrate. The source and drain regions may be on opposite sides of the gate, typically with some vertical overlap between the gate and the source and drain regions. 
     A desired characteristic in CMOS manufacturing is the presence of a halo region. A halo region may be generally located interposed between the source and drain regions and the channel region, and may be of converse polarity to the source and drain regions. The presence of a halo region may reduce drain-source current leakage (punch-through effect) within the FET. 
     Halo regions may typically be formed through a low energy, low current ion implantation method carried out at large angle tilt after a gate and gate dielectric are in place. The gate and gate dielectric act as an ion implantation mask allowing implanted dopants to penetrate below the edge of the metal-oxide semiconductor gate stack. This particular method may hinder halo region implantation in faceted recess structures. Furthermore, the low energy, low current ion implantation method described above may compromise performance of FET devices already on the structure, since halo ion implantation may provide undesirable halo residual atoms physically at or near the FET gate dielectric. In addition, as the industry continues to move towards smaller scale devices, halo region implantation becomes even harder due to space reduction between gates (gate shadowing), which may also increase the undesirable effects described above. Additionally, when significant substrate removal occurs during the fabrication of faceted recess structures on a semiconductor substrate, integrity of the implanted halo region may be compromised given that the highest halo concentration is located where the faceted recess is produced. 
     Therefore, it would be desirable to provide a method and a structure having a field effect transistor on a substrate, and the substrate including a well-defined halo region wherein the halo region formation does not require ion implantation. 
     SUMMARY 
     According to at least one exemplary embodiment of the present disclosure, a method of forming a semiconductor device includes: forming a gate on a semiconductor substrate, forming a gate dielectric between the gate and the substrate, forming a source recess and a drain recess in the semiconductor substrate on opposing sides of the gate, epitaxially growing an embedded halo region along a perimeter of each of the source and drain recesses, etching a bottom area along the perimeter of both the source and drain, and epitaxially growing a stressor material to fill the source and drain recesses, wherein the filled source and drain recesses form source and drain regions for conducting current through the channel. 
     According to another exemplary embodiment of the present disclosure, a semiconductor device comprises: a semiconductor substrate defining multiple recesses in the substrate, a gate located above a semiconductor substrate between the source and drain recesses, a gate dielectric between the semiconductor substrate and the gate, a source recess and a drain recess in the semiconductor substrate on opposing sides of the gate, an epitaxially grown halo region partially along a perimeter of each of the source and drain recesses, an epitaxially grown stressor material inside the source and drain recesses and communicating with a top and bottom region of the recesses, such that the recesses define a source region and a drain region in the semiconductor substrate, and a channel region positioned between the source and drain recesses. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features and advantages of the present disclosure will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. The various features of the drawings are not to scale as the illustrations are for clarity in facilitating one skilled in the art in understanding the disclosure in conjunction with the detailed description. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements. In the drawings: 
         FIG. 1  is a cross sectional side elevational view of a gate layer and sigma-shaped source and drain recesses formed onto a semiconductor substrate, according to one embodiment of the present disclosure; 
         FIG. 2  is a cross sectional side elevational view of an epitaxial halo region formed on a perimeter of the sigma-shaped source and drain recesses shown in  FIG. 1 , according to one embodiment of the present disclosure; 
         FIG. 3  is a cross sectional side elevational view depicting a bottom part of the sigma-shaped source and drain recesses being etched to remove part of the halo region shown in  FIG. 2 , according to one embodiment of the present disclosure; 
         FIG. 4  is a cross sectional side elevational view depicting an epitaxial embedded stressor material region formed between the halo regions to fill the sigma-shaped source and drain recesses shown in  FIG. 3 , according to one embodiment of the present disclosure; 
         FIG. 5  is a cross sectional side elevational view depicting an initial step in the formation of an optional first epitaxial halo region located below the channel region in each of the source and drain recesses, according to one embodiment of the present disclosure; 
         FIG. 6  is a cross sectional side elevational view depicting the formation of sigma-shaped source and drain recesses including an optional first epitaxial halo region below the channel region, according to one embodiment of the present disclosure; 
         FIG. 7  is a cross sectional side elevational view depicting a second epitaxial halo region formed adjacent to the optional first epitaxial halo region. The second epitaxial halo region located in a top portion of the perimeter of the sigma-shaped source and drain recesses, according to one embodiment of the present disclosure; 
         FIG. 8  is a cross sectional side elevational view depicting a bottom part of the sigma-shaped source and drain recesses being etched to remove part of the second halo region shown in  FIG. 7 , according to one embodiment of the present disclosure; 
         FIG. 9  is a cross sectional side elevational view depicting an epitaxial stressor material region formed in the sigma-shaped source and drain recesses shown in  FIG. 8 , according to one embodiment of the present disclosure; and 
         FIG. 10  is a flow chart showing a method for the fabrication of source and drain regions containing an epitaxial halo within a semiconductor substrate, according to one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments. 
     Referring to  FIGS. 1-10 , according to an illustrative embodiment of the present disclosure, a method for manufacturing a semiconductor structure is shown. Specifically,  FIGS. 1-10  depict a semiconductor processing technique for providing a semiconductor structure  400  shown in  FIG. 4  and an alternate structure  900  shown in  FIG. 9 . 
     Referring now to  FIG. 1 , according to an embodiment of the present disclosure, an initial structure  100  may include a semiconductor substrate embodied as a silicon substrate  102 . The semiconductor substrate may be made of any semiconductor material including, but not limited to: silicon, germanium, silicon-germanium alloy, carbon-doped silicon, carbon-doped silicon-germanium alloy, and compound semiconductor materials.  FIG. 1  illustrates the formation of a gate structure  104  above a channel region  114  of the semiconductor substrate  102 . The gate  104  may include a gate dielectric  108  which may be formed by any method known in the art. The gate dielectric  108  may include a high-k dielectric material having a dielectric constant greater than, for example, 3.9, which is the dielectric constant of silicon oxide. In some embodiments, multiple gates may be formed above the channel region  114  when fabricating multiple transistor structures having shared source and drains. The semiconductor structure  100  may further include a gate spacer  106 . The gate spacer  106  may be formed on the sidewalls of the gate  104  by deposition of a dielectric layer. The dielectric layer may be formed by any known technique in the art, for example, by chemical vapor deposition (CVD) of a dielectric material. In another embodiment of the present invention, the gate  104  may be formed in a gate last process where the initial gate structure may comprise a dummy polysilicon gate that may be replaced by a final metal gate structure  104  after device manufacturing is complete. 
     In the present embodiment, source and drain recesses  110  may be formed adjacent to a channel region  114  in a substrate  102 . The recesses may be formed by etching the semiconductor substrate  102  using a dry etching technique. Initial recesses in the semiconductor substrate  102  may have a box shape (not shown), which are then processed to the present sigma shape. Sigma-shaped source and drain recesses  110  as shown in the initial structure  100  may be made utilizing conventional techniques well known to those skilled in the art. For example, anisotropic dry-etching followed by anisotropic wet-etching. The sigma-shaped source and drain recesses  110  may also be referred to as diamond-shaped recesses. Sigma-shaped recesses  110  may be formed to increase strain force on the channel region  114  by narrowing the space between source and drain. 
     Referring now to  FIG. 2 , structure  200  illustrates epitaxial growth of a doped material layer in the device source and drain recesses. The source and drain recesses  110  may include a perimeter  112 , as shown in  FIG. 1 , defining the recesses in the substrate  102 . The epitaxial growth may be conducted along the perimeter  112  of each of the source and drain recesses  110  shown in  FIG. 1 . The epitaxial growth of the doped material layer may form a halo region  202  at each of the source and drain recesses  110 , of inverse doping characteristics to the source and drain regions (discussed below), respectively. 
     The thickness of the epitaxial halo region  202  may vary according to the device structure and the desired device characteristics, including doping of the halo region  202 . For example, the thickness of the epitaxial halo region  202  may be in the range of about 2-10 nm. The epitaxial halo region  202  may be formed from a crystalline structure which has the same lattice constant as the underlying semiconductor substrate  102 . Dopants may be incorporated into the epitaxial halo region  202  by in-situ doping. For example, for a p-FET structure an n-type halo dopant such as phosphorus or arsenic may be utilized. A phosphorus or arsenic doped silicon (Si:P or Si:As) material or phosphorus or arsenic doped silicon-germanium (SiGe:P or SiGe:As) material may be grown, where the concentration of phosphorus or arsenic may range from 5×10 17  cm −3  to 1×10 19  cm −3 . Similarly, for an n-FET structure a p-type dopant such as boron may be incorporated by in-situ doping in the epitaxial halo region. The concentration of boron may range from 5×10 17  cm −3  to 1×10 19  cm −3 . 
     The halo regions  202  provide improved channel region  114  isolation within the FET device  200 . Halo regions are areas of opposite higher dopant concentration in close proximity to the device gate. Usually halo regions are located underneath the device gate  104  and the inversion channel  114 . Halo regions are commonly used to avoid punch-through effect in short-channel devices. 
     A tilted ion implantation method is typically used to introduce the required dopant species into the substrate  102 . Because of the continuous reduction of transistor dimensions, high-angle ion implantation method may result in undesirable residual halo implantation ions at or near the gate hence compromising FET performance. In contrast, in-situ doped halo regions formed by a selective epitaxial growth process may provide well-defined halo regions with the desired dopant profile without affecting FET performance especially for 22 nm technologies and beyond. 
     Referring to  FIG. 3 , a bottom portion of the halo region  202  shown in  FIG. 2  may be removed, for example, by a directional reactive-ion etching technique (RIE). The removal of this portion of the halo region may be performed to provide a butting contact area  304  within the device  300 . The technique then includes filling the sigma-shaped recesses  110  with a stressor material, such as embedded silicon germanium (eSiGe) for p-FET devices or carbon-doped silicon (Si:C) for n-FET devices. The stressor material may apply a stress onto the channel region  114 , thus improving device performance. 
     Referring to  FIG. 4 , according to one embodiment of the present disclosure, a stressor material  402  may be grown epitaxially within the source and drain recesses  110  shown in  FIG. 3  to form the source and drain regions  404  of the semiconductor device  400 . The stressor material usually has a larger lattice constant for p-FET devices or a smaller lattice constant for n-FET devices than that of the semiconductor substrate  102  in order to apply a compressive or a tensile strain into the channel region  114  respectively. Lattice stress may be transferred from the source and drain regions  404  to the underlying semiconductor substrate  102 . 
     Source and drain regions  404  include the stressor material  402  and the halo regions  302 . The halo regions  302  can be considered adjacent to the stressor material  402  and part of the source and drain regions  404 . 
     For example, for a p-FET device, the epitaxially grown stressor material may include a silicon-germanium (SiGe) material, where the atomic concentration of germanium (Ge) may range from about 10-80%. In an embodiment of the present disclosure, the concentration of germanium (Ge) may be 25-50%. The epitaxially grown stressor material may provide a compressive strain to the channel region  114 . More specifically, the stressor material region may induce a compressive stress in the p-FET channel region  114  which enhances carrier mobility and increases drive current. Thus, the source and drain regions  404  may include enhanced carrier mobility provided by the epitaxial stressor material and effective current isolation provided by the epitaxial halo region  302 . Dopants such as boron may be incorporated into the silicon-germanium epitaxial region by in-situ doping. The percentage of boron may range from 1×10 19  cm −3  to 2×10 21  cm −3 , preferably 1×10 20  cm −3  to 1×10 21  cm −3 . 
     For example, for an n-FET device, the epitaxially grown stressor material may include a carbon-doped silicon (Si:C) material, where the atomic concentration of carbon (C) may range from about 0.4-3.0%. The epitaxially grown stressor material may provide a tensile strain to the channel region  114 . More specifically, the stressor material region may induce a tensile stress in the n-FET channel region  114  which enhances carrier mobility and increases drive current. Thus, the source and drain regions  404  may include enhanced carrier mobility provided by the epitaxial stressor material region and effective current isolation provided by the epitaxial halo region  302 . Dopants such as phosphorus or arsenic may be incorporated into the carbon-doped epitaxial region by in-situ doping. The percentage of phosphorus or arsenic may range from 1×10 19  cm −3  to 2×10 21  cm −3 , preferably 1×10 20  cm −3  to 1×10 21  cm −3 . 
     Referring to  FIG. 5 , in another embodiment of the present invention, an initial structure  500  depicts the formation of a doped material layer region in the lower part of preliminary box-shaped source and drain recesses  103 . The process may include epitaxially growing a doped sacrificial layer  504  in the box-shaped source and drain recesses  502 . The sacrificial layer  504  may comprise the epitaxial growth of silicon-germanium (SiGe) or carbon-doped silicon (Si:C) with the corresponding dopants, according to p-FET or n-FET structures. Following the formation of the sacrificial layer  504 , an in-situ etching process may be conducted to form sigma-shaped source and drain recesses. 
     Referring now to  FIG. 6 , sigma-shaped recesses  110  may be formed by etching the semiconductor substrate  102  using any suitable etching technique, for example the substrate  102  may be etched using an in-situ gas-phase hydrochloric acid (HCl) etching procedure. A bottom halo region embodied as an optional first halo region  602  may be epitaxially grown in the recesses before forming the sigma-shaped recesses  110 , as described in  FIG. 5 . This optional doped region  602  may form a first halo region located below the channel region  114  that can be extended forming a second halo region  202  (as shown in  FIG. 2 ) following the procedure previously described in  FIGS. 1-4 . In short channel devices, there is a possibility for space charge regions (SCR), associated with source and drain regions, to come into close contact with each other which in turn increases punch-through effect. The presence of a halo region near the source and drain regions and beneath the inversion channel suppresses the width of the space charge regions, hence reducing punch-through effect. 
     The thickness of the epitaxially grown first halo region  602  may vary according to the device structure and the device desired characteristics including doping of the first halo region  602 . For example, the thickness of the first epitaxial halo region  602  may be in the range of about 2-10 nm. Dopants may be incorporated into the optional halo region  602  by in-situ doping. For example, for a p-FET structure an n-type halo dopant such as phosphorus or arsenic may be utilized. A phosphorus or arsenic doped silicon (Si:P or Si:As) material or phosphorus or arsenic doped silicon-germanium (SiGe:P or SiGe:As) material may be grown, where the concentration of phosphorus or arsenic may range from 5×10 17  cm −3  to 1×10 19  cm −3 . Similarly, for an n-FET structure a p-type dopant such as boron may be incorporated by in-situ doping in the epitaxial halo region. The concentration of boron may range from 5×10 17  cm −3  to 1×10 19  cm −3 . 
     Referring now to  FIG. 7 , subsequent to the formation of the first epitaxial halo region  602 , a second doped region  202  may be epitaxially grown on a perimeter  112  of the source and drain recesses  110 . The formation of a second epitaxial halo region  202  follows the technique regarding in  FIG. 2 . Dopants may be incorporated into the second epitaxial halo region  202  by in-situ doping. For example, for a p-FET structure an n-type halo dopant such as phosphorus or arsenic may be utilized. A phosphorus or arsenic doped silicon (Si:P or Si:As) material or phosphorus or arsenic doped silicon-germanium (SiGe:P or SiGe:As) material may be grown, where the concentration of phosphorus or arsenic may range from 5×10 17  cm −3  to 1×10 19  cm −3 . Similarly, for an n-FET structure a p-type dopant such as boron may be incorporated by in-situ doping in the epitaxial halo region. The concentration of boron may range from 5×10 17  cm −3  to 1×10 19  cm −3 . 
     Referring to  FIG. 8 , the bottom part of the second halo region  202  shown in  FIG. 7  may be removed, for example, by a directional reactive-ion etching technique (RIE). The removal of this portion of the second halo region may be performed to provide a butting contact area  802  within the device  800 . The technique then may include filling the sigma-shaped recesses  110  with a stressor material, such as embedded silicon germanium (eSiGe) for p-FET devices and carbon-doped silicon (Si:C) for n-FET devices. The stressor material may apply a stress onto the channel region  114 , thus improving device performance. 
     The first epitaxial halo region  602  and the second epitaxial halo region  302  may form an extended halo region  804  along the perimeter  112  of the source and drain recesses  110 . The extended halo region  804  may further improve carrier mobility within the FET device. 
     Referring now to  FIG. 9 , a stressor material region  902  may be formed to fill the source and drain recesses  110  shown in  FIG. 8 , in order to increase the strain force applied to the channel region  114 . The stressor material region  902  may be similar to, and formed similarly to, the stressor material region  402  of  FIG. 4 . The epitaxial stressor material region  902  and the extended epitaxial halo region  804  may form the device source and drain regions  904 . 
     For example, for a p-FET device, an epitaxially grown stressor material  902  may include a silicon-germanium (SiGe) material, where the atomic concentration of germanium (Ge) may range from about 10-80%. In an embodiment of the present disclosure, the concentration of germanium (Ge) may be 25-50%. The epitaxially grown stressor material  902  embodied as an embedded silicon-germanium region in structure  900 , may provide a compressive strain to the channel region  114 . More specifically, the stressor material region  902  may induce a compressive stress in the p-FET channel region  114  which enhances carrier mobility and increases drive current. Thus, the source and drain regions  904  may include enhanced carrier mobility provided by the epitaxial stressor material region  902  and effective current isolation provided by the extended epitaxial halo region  804 . Dopants such as boron may be incorporated into the silicon-germanium epitaxial region by in-situ doping. The percentage of boron may range from 1×10 19  cm −3  to 2×10 21  cm −3 , preferably 1×10 20  cm −3  to 1×10 21  cm −3 . 
     For example, for an n-FET device, an epitaxially grown stressor material  902  may include a carbon-doped silicon (Si:C) material, where the atomic concentration of carbon (C) may range from about 0.4-3.0%. The epitaxially grown stressor material  902  embodied as an embedded carbon-doped silicon region in structure  900 , may provide a tensile strain to the channel region  114 . More specifically, the stressor material region  902  may induce a tensile stress in the n-FET channel region  114  which enhances carrier mobility and increases drive current. Thus, the source and drain regions  904  may include enhanced carrier mobility provided by the epitaxial stressor material region  902  and effective current isolation provided by the extended epitaxial halo region  804 . Dopants such as phosphorus or arsenic may be incorporated into the carbon-doped epitaxial region by in-situ doping. The percentage of phosphorus or arsenic may range from 1×10 19  cm −3  to 2×10 21  cm −3 , preferably 1×10 20  cm −3  to 1×10 21  cm −3 . 
     Referring now to  FIG. 10 , a flowchart depicting the formation of source and drain regions within a semiconductor substrate is shown. The main process consists of several consecutive steps ( 1010 ,  1012 ,  1014 ,  1018 ,  1020  and  1022 ) to achieve sigma-shaped source and drain with a well-defined halo region. The method described in  FIG. 10  includes an optional process  1016  that may comprise the formation of a first halo region in the bottom part of the source and drain recesses below the device channel region. Such optional halo region may be epitaxially grown before etching the semiconductor substrate to form sigma-shaped recesses. Once the optional first halo region  1016  is formed, a second halo region may be grown following steps  1018  and  1020 . Subsequently, an epitaxial stressor material  1022  may be grown within the source and drain recesses to ultimately obtained sigma-shaped source and drain with a well-defined extended halo region. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable other of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.