Abstract:
A method of forming a deep trench DRAM cell on a semiconductor substrate has steps of: forming a deep trench capacitor in the semiconductor substrate; using silicon-on-insulator (SOI) technology to form a silicon layer on the deep trench capacitor; and forming a vertical transistor on the silicon layer over the deep trench capacitor, wherein the vertical transistor is electrically connected to the deep trench capacitor.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a deep trench DRAM process and, more particularly, to a method of forming a deep trench DRAM device to achieve the desired characteristics of low capacitance, smaller cell size, high functionality and simplified manufacturing process.  
           [0003]    2. Description of the Related Art  
           [0004]    DRAM devices are widely applied in integrated circuits technology, in which a DRAM cell typically consists of a storage capacitor and an access transistor. There is much interest in reducing the size of DRAM devices to increase their density on an IC chip, thereby reducing size and power consumption of the chip, and allowing faster operation. In order to achieve a memory cell with a minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. This also causes reduction in capacitor area, resulting in the reduction of cell capacitance. Accordingly, an important challenge is to promote storage ability and operating stability of capacitors with decreased scale and increased integration of the DRAM device. A vertical transistor has recently been developed which can maintain the gate length at a suitable value for obtaining low leakage, without decreasing the bit line voltage or increasing the memory cell&#39;s lateral dimension. Also, a deep trench capacitor can be fabricated directly below the vertical transistor without consuming any additional wafer area.  
           [0005]    U.S. Pat. No. 5,571,730 discloses a deep trench DRAM device with a vertical transistor and a method for manufacturing the same. FIG. 1 is a top view showing the DRAM cell, wherein reference symbol WL indicates a wordline, T indicates a transistor, BC indicates a bitline contact hole, BL 1  indicates a first bitline, and BL 2  indicates a second bitline. The transistor T is formed in a shape extended in the wordline direction, and the bitline contact hole BC is located to one side of the center of the transistor T in the wordline direction. Multi-layered bitlines are formed, so that adjacent transistors T in the wordline direction are connected with the first bitline BL 1  and the second bitline BL 2 , respectively, both of which are located at different heights.  
           [0006]    [0006]FIGS. 2A to  2 E are cross-sections along line  2 - 2  in FIG. 1 showing the conventional method of forming the DRAM cell. As shown in FIG. 2A, a first semiconductor substrate  10  is etched to form silicon pillars  12 , and a source region  14  is formed on the top of the pillar  12 . An oxide film  15  is then deposited on the entire surface of the first semiconductor substrate  10  to form a groove in the space in the wordline direction. Next, a nitride film  16  is conformally deposited on the oxide film  15 , and an oxide layer  17  is deposited to completely fill the grooves between pillars  12 . Thereafter, a plurality of first contact holes  18  is formed to expose the source regions  14 , respectively.  
           [0007]    As shown in FIG. 2B, a conductive material is deposited and patterned to form a capacitor storage electrode  19  connected to the source region  14  through the first contact hole  18 . Thereafter, a dielectric film  20  is deposited on the entire surface of the capacitor storage electrode  19 , and then a plate electrode  21  is deposited on the entire surface of the dielectric film  20  to fill the under-cut portion of the storage capacitor electrode  19 . Thus, a first capacitor C 1  and a second capacitor C 2  are completed. As shown in FIG. 2C, a first insulating layer  22  is deposited on the plate electrode  21 , and a new wafer is attached on the first insulating layer  22  by a direct wafer bonding method, thus providing a second semiconductor substrate  24 . Next, after turning the backside of the first semiconductor substrate  10  upward, the backside of first semiconductor substrate  10  is etched until the oxide film  15  is exposed.  
           [0008]    As shown in FIG. 2D, a drain region  25  is formed on the upper portion of the pillar  12 , and the oxide film  15  is isotropically etched with the nitride film  16  as the etch-blocking layer. Next, a gate insulating film  26  is formed by thermally oxidizing the exposed surface of the pillars  12 . Thereafter, a conductive layer  27  is deposited on the entire surface of the resultant structure. As shown in FIG. 2E, the conductive layer  27  is etched to form a gate electrode  28  surrounding the pillar  12 . Thus, the transistors T 1 , T 2  comprised of the source region  14 , the drain region  25  and the gate electrode  28  are completed. Next, after depositing a second insulating layer  29  on the entire surface of the second semiconductor substrate  24 , a first bitline contact hole  30  is formed to expose the drain region  25  of the first transistor T 1 . Thereafter, a conductive layer filling the first bitline contact hole  30  is patterned to serve as a first bit line BL 1 . Next, a third insulating layer  31  is deposited on the entire surface of the second semiconductor substrate  24 , and then a second bitline contact hole  32  is formed to expose the drain region  25  of the second transistor T 2 . Finally, a conductive layer filling the second bitline contact hole  32  is patterned to serve as a second bit line BL 2 .  
           [0009]    However, in the above-described method for manufacturing the DRAM cell, the structures of the deep trench capacitor, the collar structure and the source region  14  are formed on the front side of first substrate  10 , and then reversed to attach the second substrate  24 . The other structures of gate electrode  28 , drain region  25 , and vertical channel are formed on the back side of the first substrate  10 . This complicated process increases process time and production cost. Thus, a simple deep trench DRAM process solving the aforementioned problems is called for.  
         SUMMARY OF THE INVENTION  
         [0010]    The present invention provides a method of forming a deep trench DRAM cell, preferably a sub-150 nm DRAM device, to achieve the desired characteristics of low capacitance, smaller cell size, high functionality and simple collar process.  
           [0011]    A method of forming a deep trench DRAM cell is performed on a semiconductor substrate, which has a collar oxide plate and a plurality of deep trenches passing through the collar oxide plate and the substrate to a predetermined depth. First, a deep trench capacitor is formed in each deep trench, wherein the deep trench capacitor has an ion diffusion region with a second conductive type in the substrate surrounding the deep trench, a dielectric layer on the sidewall and bottom of the deep trench, and a first doped polysilicon layer filling the deep trench. Then, using SOI technology, a silicon layer is formed on the planarized surface of the collar oxide plate and the first doped polysilicon layer. Next, a first ion-diffusion layer is formed on the top of the silicon layer. Next, the ion-diffusion layer and the silicon layer on the collar oxide plate are removed to form a plurality of pillars. Then, an oxide layer is formed on the entire surface of the first doped polysilicon layer. Thereafter, a second ion-diffusion layer is formed on the sidewall of the silicon layer, and then annealing treatment is used to form a third ion-diffusion layer at the bottom of the silicon layer. Next, a nitride liner is formed on the entire surface of the substrate, and a second doped polysilicon layer with the second conductive type is formed on the nitride liner, wherein the top of the second doped polysilicon layer reaches the top of the third ion diffusion region. After oxidizing the second doped polysilicon layer to form an oxidation layer, the exposed region of the nitride liner is removed. Finally, a third doped polysilicon layer is formed on the oxidization layer surrounding each of the pillars.  
           [0012]    Accordingly, it is a principal object of the invention to provide a simple process to manufacture a deep trench DRAM cell with a vertical transistor.  
           [0013]    It is another object of the invention to provide the collar oxide plate prior to the formation of the deep trench.  
           [0014]    Yet another object of the invention is to omit the buried strap (BS) process.  
           [0015]    It is a further object of the invention to decrease process time and production cost.  
           [0016]    These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 is a top view showing a DRAM cell.  
         [0018]    [0018]FIGS. 2A to  2 E are cross-sectional views along line  2 - 2  in FIG. 1 showing the conventional method of forming the DRAM cell.  
         [0019]    [0019]FIGS. 3A to  3 J are cross-sectional diagrams along line  2 - 2  in FIG. 1 showing a method of forming a deep trench DRAM cell according to the present invention. 
     
    
       [0020]    Similar reference characters denote corresponding features consistently throughout the attached drawings.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]    The present invention provides a method of forming a deep trench DRAM cell, preferably a sub-150 nm DRAM device, to achieve the desired characteristics of low capacitance, smaller cell size, high functionality and simple collar process. FIGS. 3A to  3 J are cross-sectional diagrams along line  3 - 3  in FIG. 1 showing a method of forming a deep trench DRAM cell according to the present invention. As shown in FIG. 3A, a semiconductor silicon substrate  40  for example, a p + -doped silicon substrate, is provided with a surface successively covered by a collar oxide plate  42  of 200˜300 nm, a SiN stopping layer  44  of 20˜50 nm, a BSG hard mask  45  of more than 1200 nm, a polysilicon mask layer  46 , and a patterned photoresist layer  47 . In another embodiment, a TERA hard mask may replace the polysilicon mask layer  46 . Then, using dry etching with the patterned photoresist layer  47  as the mask, exposed regions of the polysilicon mask layer  46  are removed and the photoresist layer  47  is stripped. Next, using dry etching again with the remaining polysilicon mask layer  46  as a mask, the BSG hard mask  45 , the SiN stopping layer  44 , the collar oxide plate  42  and the substrate  40  are successively removed. Thus, as shown in FIG. 3B, a plurality of deep trenches  48  is formed in the substrate  40  to reach a predetermined depth of less than 5 m. Thereafter, wet etching cleans the deep trenches  48  and a stripping process follows to remove the BSG hard mask  45 . In another embodiment, wet etching is further used to form the deep trench  48  as a bottle-shaped trench to increase the capacitance of the deep trench capacitor.  
         [0022]    As shown in FIG. 3C, using GPD/ASG deposition with annealing treatment, an n +  diffusion region  50  is formed in the substrate  40  surrounding the deep trench  48 . Then, an NO dielectric  52  comprising a silicon nitride layer and an oxide layer is formed on the sidewall and bottom of the deep trench  48 . Next, a first n + -doped polysilicon layer  54  is deposited to fill the deep trenches  48 , and then the top of the first polysilicon layer  54  surrounded by the collar oxide plate  42  and the SiN stopping layer  44  is recessed to form a plurality of openings  55 . Thereafter, wet etching is used to clean the openings  55 . This completes a deep trench capacitor consisting of the n +  diffusion region  50 , the NO dielectric  52  and first n + -doped polysilicon layer  54  in each deep trench  48 .  
         [0023]    As shown in FIG. 3D, a second n + -doped polysilicon layer  56  is deposited to fill the openings  55  and then annealing treatment is performed on it. Next, chemical mechanical polishing (CMP) is used to level off the surfaces of the second polysilicon layer  56  and the SiN stopping layer  44 . Next, after removing the SiN stopping layer  44 , CMP is used again to planarize the surfaces of the second polysilicon layer  56  and the collar oxide plate  42 . Thus, the second polysilicon layer  56  surrounded by the collar oxide plate  42  serves as a connection between the deep trench capacitor and the vertical transistor manufactured in subsequent processes. Thereafter, wet etching is used to clean the entire surface of the substrate  40 .  
         [0024]    As shown in FIG. 3E, using silicon-on-insulator (SOI) technology, a silicon layer  58  of more than 500 nm is formed on the planarized surface of the substrate  40 . Then, using ion implantation, an n + -doped layer  60  is formed on top of the silicon layer  58 . In another embodiment, annealing may be further used. Please refer to FIGS. 4A to  4 D which show the SOI process. First, as shown in FIG. 4A, a thick silicon wafer  57  is provided with an oxygen treatment to form a silicon oxide layer, and then hydrogen ion implantation is employed to form a predetermined cutting line between an ion-implanted region  571  and a non-implanted region  572  in the thick silicon wafer  57 . Next, as shown in FIG. 4B, using wafer-bonding technology, the thick silicon wafer  57  is reversed and bonded to the planarized surface of the substrate  40 . Then, as shown in FIG. 4C, using annealing at a temperature less than 600         , the non-implanted region  572  on the backside of the silicon wafer  57  serving as a sacrificial layer is cleaved off. Finally, as shown in FIG. 4D, using annealing at a temperature approximately 1100         and using CMP to planarize the ion-implanted region  571 , the remaining part of the ion-implanted region  571  formed on the planarized surface of the substrate  40  serves as the silicon layer  58 .  
         [0025]    As shown in FIG. 3F, using dry etching with a hard mask on the n + -doped layer  60 , part of the n + -doped layer  60  and the silicon layer  58  are removed, resulting in a plurality of pillars on the second polysilicon layer  56 . Then, after wet cleaning, an oxide layer  62  is formed on the entire surface of the substrate  40  by thermal oxidization. Thereafter, for tuning the threshold voltage (V t ) of the vertical transistor, angled implantation is used to form a p-doped region  64  on the sidewall of the silicon layer  58 . Then, using RTP annealing treatment, the ions in the second polysilicon layer  56  diffuse into the bottom of the silicon layer  56  to serves as a drain region  66 . Then, wet etching is used to clean the surface.  
         [0026]    As shown in FIG. 3G, a SiN liner  68  is conformally deposited on the entire surface of the oxide layer  62 , and a third doped polysilicon layer  70  is conformally deposited on the SiN liner  68 . Next, the third doped polysilicon layer  70  is recessed until the top of the third doped polysilicon layer  70  reaches the top of the drain region  66 . As shown in FIG. 3H, using thermal oxidization to oxidize the third polysilicon layer  70 , the oxide layer and the oxidized polysilicon layer  70  become an oxidation layer  72 . Meanwhile, part of the SiN liner  68  is oxidized. Then, the exposed region of the SiN liner  68  is removed and wet etching follows.  
         [0027]    As shown in FIG. 31, a fourth polysilicon layer  74  is deposited on the oxidization layer  72  and then patterned to surround the pillars. Next, using CMP to recess the top of the fourth polysilicon layer  74  and the oxidization layer  72 . Wet cleaning is followed used. Thus, the fourth polysilicon layer  74  surrounding the pillar serves as a gate electrode layer  74 , and the oxidization layer  72  on the sidewall of the pillar serves as a vertical channel between the drain region  66  and the source region  60 . This completes the vertical transistor over the deep trench capacitor. Finally, as shown in FIG. 3J, word lines  76  are patterned on the gate electrodes  74 , and a bitline contact plug  80  passing trough an inter-metal dielectric  78  is connected to a bit line  82 .  
         [0028]    According to the present invention, the collar oxide plate  42  is formed on the substrate  40  prior to the formation of deep trenches  48 , therefore the process is simplified compared with the conventional method that uses the collar process after the formation of the deep trench capacitor. Second, the second polysilicon layer  56 , serving as a connection to device, is formed in the opening  55  patterned during the formation of the deep trench  48 . Third, no buried strap (BS) process is necessary. This further simplifies the DRAM cell process to decrease process costs. Fourth, using SOI technology, the silicon layer  58  provides a long channel device, thus the vertical transistor offers sufficient gate length to ensure low leakage, without decreasing the bit line voltage or increasing the memory cell wafer area. Fifth, the deep trench capacitor established below the vertical transistor does not impose a density limitation, because it does not occupy wafer area beyond that of the vertical transistor.  
         [0029]    It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims.