Abstract:
An input signal is modified to compensate for amplifier memory effects by combining at least two versions of the input signal, each version of the input signal being offset in time with respect to one another. More specifically, an RF input signal is split into at least two split signals, a different delay is applied to each split signal, and the delayed, split signals are combined to obtain a modified input signal.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Technical Field  
           [0002]    The present invention relates generally to compensating for memory effects of an amplifier.  
           [0003]    2. Related Art  
           [0004]    The function of an amplifier is to amplify a signal with as little signal distortion as is practical. An ideal amplifier is characterized as having a transfer function (input signal compared to output signal) which is completely linear with no transfer function discontinuities including memory effects, which is a type of hysterisis effect discussed in more detail below. Unfortunately, physical processes are seldom ideal and signal amplifiers are no exception. Amplifiers are specifically designed to operate as linearly and without memory effects as possible, but amplifier nonlinearities and memory effects are a reality in many amplifiers.  
           [0005]    Because of natural and physical characteristics of amplifiers, amplified radio frequency (RF) output is often affected by hysterisis effects. Hysteresis is a distortion that is inherent to most amplifiers and affects the predistortion of amplifiers, which results in increased spectral regrowth and intermodulation. One type of hysterisis effect is known as a memory effect. Memory effects influence spectral regrowth and intermodulation distortion associated with amplifiers. The spectral regrowth and intermodulation distortion that is characteristic of memory effects of an amplifier are forms of signal distortion where extra frequencies are also transmitted. The transmission of extra frequencies can be power inefficient and cause interference to other RF systems. Memory effects are caused by signals affecting the physical properties of an amplifier such that the amplifier is residually affected by a previous signal when a present signal is being amplified. As an illustration of the above characteristics of amplifier memory effects, FIGS. 1 and 2 are provided.  
           [0006]    [0006]FIG. 1 is an exemplary block diagram of a RF amplifier according to an exemplary embodiment of the invention. The typical RF amplifier system  100  of FIG. 1 includes a RF input  110  that is connected to an amplifier  120 , the amplifier  120  outputs an amplified RF output  130 . The amplifier  120  is a non-linear amplifier with memory effects.  
           [0007]    [0007]FIG. 2 is an exemplary graph of a transfer function for an amplifier with memory effects according to an exemplary embodiment of the invention. The Y-axis represents the output voltage V out  of amplifier  120  where the amplifier  120  has memory effect characteristics. The output voltage V out  is plotted against the amplifier&#39;s input voltage V in  along the X-axis. As shown, the resultant amplifier transfer function  220  is shown as thick and curving downward as input voltage V in  increases and the resultant output voltage V out  fails to likewise increase at the same rate. The transfer function  220  is thick due to the memory effects of the amplifier  120 . The amplifier transfer function  220  curves downward in large part due to gain compression and other hysterisis factors that introduce spectral regrowth effects and intermodulation distortion.  
         SUMMARY OF THE INVENTION  
         [0008]    According to an exemplary embodiment, an input signal is modified to compensate for amplifier memory effects by combining at least two versions of the input signal, each version of the input signal being offset in time with respect to one another. More specifically an RF input signal is split into at least two split signals, a different delay is applied to each split signal, and the delayed, split signals are combined to obtain a modified input signal.  
           [0009]    According to another exemplary embodiment, an input signal is modified to compensate for amplifier memory effects by phase shifting an input signal and combining at least two versions of the phase shifted input signal, each version of the input signal being offset in time with respect to one another. More specifically, an RF signal is split into a first signal and a second signal, and the first signal is phase shifted out of phase with the second signal. A first delay and a second delay are applied to each of at least two of the phase shifted split signals. At least two versions of the phase shifted split signals are combined, to obtain a modified input signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings, wherein like elements are represented by like reference numerals, which are given by way of illustration only and thus are not limiting of the present invention and wherein:  
         [0011]    [0011]FIG. 1 is an exemplary block diagram of a prior art RF amplifier with memory effects according to an embodiment of the invention;  
         [0012]    [0012]FIG. 2 is an exemplary graph of a transfer function for an amplifier with memory effects according to an embodiment of the invention;  
         [0013]    [0013]FIG. 3 is an example block diagram of a compensator system according to an embodiment of the invention;  
         [0014]    [0014]FIG. 4 is an example block diagram of the compensator in FIG. 3 according to an embodiment of the invention;  
         [0015]    [0015]FIG. 5 is an example of the compensator in FIG. 3 that implements a quadrature split according to an embodiment of the invention;  
         [0016]    [0016]FIG. 6 shows an example transfer function of the compensator according to an embodiment of the invention; and  
         [0017]    [0017]FIG. 7 is a graph illustrating a comparison between the transfer functions of a non-linear RF amplifier with memory compensation and a non-linear RF signal amplifier without memory compensation according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0018]    In a RF environment, where a high priority is placed upon effective and efficient utilization of limited bandwidth, memory effects that introduce spectral regrowth and intermodulation distortion are undesirable. The present invention provides a system and method to substantially overcome RF amplifier inefficiencies. The invention allows a controlled addition of memory effects supplied to an amplifier using a compensator such that the transfer function of the compensator approaches a desired inverse of the amplifier&#39;s memory effects.  
         [0019]    Memory effects also limit the amount of correction achievable in a predistortion system because the transfer function used to linearize the amplifier output is not exactly the inverse function of the amplifier. The invention further allows a controlled addition of memory effects into the predistortion system such that the transfer function of the predistortion system approaches a desired inverse transfer function of the amplifier.  
         [0020]    In disclosing the invention, first described are the compensation system and various schematics of a compensator according to embodiments of the invention. This is then followed by a desired transfer function of a compensator that helps overcome the unwanted memory effects. Finally discussed, is the transfer function of the compensator and amplifier.  
         [0021]    [0021]FIG. 3 is an example block diagram of a compensator system according to an embodiment of the invention. As shown, the compensator system  300  includes a compensator  310  controlled by a first delay control signal  360  and a second delay control signal  370  supplied by baseband circuit  330 .  
         [0022]    The compensator  310  receives an RF signal  110  and outputs a memory compensated signal  350  to the amplifier  120 . The compensator  310  distorts the RF signal  110  to overcome the memory effect characteristics of the amplifier  120 .  
         [0023]    The RF amplifier  120  receives the memory compensated signal  350 , amplifies the memory compensated signal  350  by gain, G, and outputs a RF amplified output  130 .  
         [0024]    The memory compensated signal  350  and RF amplified output  130  are both inputs into the baseband circuit  330 . The baseband circuit  330  receives the memory compensated signal  350  and the RF amplified output  130 . With these two inputs  350 ,  130 , the baseband circuit  330  determines adjustments to the delay control signals  360 ,  370  to optimize the performance of the compensator  310 .  
         [0025]    [0025]FIG. 4 is an example block diagram of the compensator  310  in FIG. 3. The compensator  310  includes a  2 -way power splitter  430  which receives and splits the RF signal  110  into first and second signal signals. Each of the first and second signals travel through a separate signal path. The first signal path  475  begins at the 2-way power splitter  430  and includes a first delay circuit  450  that is connected to a first amplifier  470  which is finally connected to the 2-way combiner.  497 . The second signal path  485  also begins at the 2-way power splitter  430 , includes a second delay circuit  455  connected to a second amplifier  480 , and terminates at the 2-way combiner  497 . The first and second signal paths  475 ,  485  are parallel to each other.  
         [0026]    The first amplifier  470  and the second amplifier  480  may be set to a reasonable equal gain depending on the signal needs of the RF amplifier  120 .  
         [0027]    The first delay circuit  450  and the second delay circuit  455  are controlled by the first delay control signal  360  and the second delay control signal  370 , respectively, through connections to the baseband circuit  330 . The delay circuits  450 ,  455  are delay blocks which change the amount of delay depending on the voltage applied to them. The delay circuits  450 ,  455  are adjusted independently to produce delays and a substantial inverse of the amplifier&#39;s memory effect. The generation of the first and second delay control signals will be discussed in detail below.  
         [0028]    The baseband circuit  330  uses a digital signal processor (DSP) configured to produce the delay control signals  360 ,  370 . The baseband circuit  330  monitors its inputs  130 ,  350  to retrieve a characteristic of the signals. The baseband circuit  330  then adjusts the first delay control signal  360  and the second delay control signal  370  in accordance with values stored in the baseband circuit  330  corresponding to the retrieved characteristic. Decreased distortion is achieved when delay circuits within the compensator  310  provide different delay times. The delay control signals  360 ,  370  may simply be a change of voltage applied to delay circuits within the compensator  310 . The delay produced by the delay circuits within the compensator  310  changes as the voltage supplied to them via the control signals  360 ,  370  changes.  
         [0029]    In another embodiment, additional components may be added to the compensator  310  forming a quadrature split. In addition to the memory compensation, the quadrature split configuration of the compensator also performs phase compensation. FIG. 5 is an example of a compensator  310  implementing a quadrature split according to an embodiment of the invention. As shown, the compensator  310  receives an RF signal  110  and outputs a memory compensated signal  350 . The compensator  310 , in this embodiment, includes a 2-way power splitter  520  which receives and splits the RF signal  110  into first and second signals. The 2-way power splitter  520  in addition to splitting the RF signal  110 , introduces a phase adjustment such that the first signal is 90° out of phase with the second signal. Each of the first and second signals travel through a first signal path  591  and a second signal path  596 , respectively. The first signal path  591  and second signal path  596  are parallel to each other.  
         [0030]    The first signal path  591  begins at 2-way power splitter  520 ; includes a signal power splitter  530 , third signal path  571 , a fourth signal path  585 , and a signal combiner  590 ; and ends at 2-way combiner  597 . The 2-way power splitter  530  splits its incoming signal into the third signal path  571  and the fourth signal path  581 . The third signal path  571  begins at the 2-way power splitter  530 , includes a first delay circuit  550  connected to a first amplifier  570 , and terminates at the 2-way combiner  590 . The fourth signal path  581  also begins at the 2-way power splitter  530 , and includes a second amplifier  580  connected to the 2-way combiner  590 . The third signal path  571  and the fourth signal path  581  are parallel to each other.  
         [0031]    The second signal path  596  begins at the 2-way power splitter  520 ; includes another 2-way power splitter  535 , a fifth signal path  576 , a sixth signal path  586 , a 2-way combiner  595 ; and ends at the 2-way combiner  597 . The 2-way power splitter  535  splits its incoming signal into the fifth signal path  576  and the sixth signal path  586 . The fifth signal path  576  begins at the 2-way power splitter  535 , includes a second delay circuit  555  connected to a third amplifier  575 , and terminates at the 2-way combiner  595 . The sixth signal path  586  also begins at the 2-way power splitter  535  and includes a fourth amplifier  585  connected to the 2-way combiner  595 . The fifth signal path  576  and the sixth signal path  586  are parallel to each other.  
         [0032]    The processed first and second signals are combined at the signal combiner  597  to produce the memory compensated signal  350 . The memory compensated signal is then fed to the RF amplifier  120  (not shown).  
         [0033]    The first delay circuit  550  and the second delay circuit  555  are delay blocks, and are controlled by the first delay control signal  360  and the second delay control signal  370 , respectively, through connections to the baseband circuit  330  (not shown) in the same manner that first and second delay circuits  450  and  455  in the embodiment of FIG. 4 were controlled. Accordingly, the first and second delay circuits  550 ,  555  may be adjusted independently to produce delays and a substantial inverse of the amplifier&#39;s transfer function. While phase compensation is typically fixed, the baseband circuit may be augmented to additionally change the phase in the 2-way power splitter  520 .  
         [0034]    [0034]FIG. 6 shows an example transfer function of the compensator according to an embodiment of the invention. The x axis represents input voltage V in  and the y axis represents output voltage V out  of the compensator  310 . The diagonal thick line represents the transfer function  610  of the compensator  310 . The transfer function  610  shown is for the compensator  310  of FIG. 5, using a  5  nanosecond delay in each delay circuit  550 ,  555 . A similar graph would result for similar conditions as applied to the compensator  310  of FIG. 4. The compensator  310  intentionally distorts a signal prior to amplification, in order to compensate for the memory effects of the actual RF signal amplifier. The output of the compensator  310  is a net result of the input signal  110  and an intentional distortion introduced by the compensator  310  which anticipates and helps cancels the RF signal amplifier memory effects.  
         [0035]    [0035]FIG. 7 illustrates the transfer function  220  of the amplifier  120  as shown in FIG. 1, and further illustrates the transfer function  730  of the compensation system of FIG. 4. Component input voltage V in  is plotted along the horizontal axis, while component output voltage V out  is plotted along the vertical axis. As shown, the memory effects of the amplifier  120  are significantly reduced by the compensation system of the present invention. Although the transfer functions of FIG. 7 are represented in terms of voltages, other parameters may be used for transfer function definition (such as current or power) as would best apply to certain amplifier configurations and as would be apparent to those skilled in the art.  
         [0036]    In another alternative embodiment of the invention, the compensator  310  may include more than two delays and receive more than two delay control signals to control each of the delay circuits within.  
         [0037]    Moreover, in an alternative embodiment, the compensator  310  may be used as a distorter with memory compensation if distortion components are used instead of the amplifiers as described in FIGS. 4 and 5 below. To accomplish this with the compensator  310  shown in FIG. 4, for example, the first amplifier  470  and the second amplifier  480  may be replaced with a first predistortion component and a second predistortion component, respectively. The predistortion components may be a predistortion amplifier, predistortion diode, or other predistortion device. If predistortion amplifiers are used, each predistortion amplifier would receive and be controlled by a magnitude control signal and a phase control signal as is well known. For example, the baseband circuit  330  may be used to provide the control signals to a predistortion component. This configuration of the compensator  310  provides memory compensation to diminish memory affects and predistortion to assist in making output of the RF amplifier  120  linear.  
         [0038]    In an alternative embodiment, the compensator  310  may provide memory compensation, phase compensation characteristics, and linear predistortion characteristics. This configuration provides memory compensation to diminish memory effects, phase compensation to diminish phase effects, and linear predistortion to assist in making the RF amplifier  120  output linear. To accomplish this with, for example, the compensator  310  as shown in FIG. 5, the first through fourth amplifiers  570 ,  580 ,  575 ,  585  and may be replaced with predistortion components. The predistortion components may be a predistortion amplifier, predistortion diode, or other predistortion device. The predistortion amplifiers are controlled by a magnitude control signal and a phase control signal as is well known. For example, the baseband circuit  330  may be used to provide the control signals.  
         [0039]    In another embodiment, the compensator  310  of FIG. 4 may include multiple paths that can be added to the compensator  310  by replacing the 2-way splitter  430  and combiner  497  with an N-way splitter and N-way combiner, respectively. The resulting N identical paths each include a delay circuit and amplifier. The baseband circuit  330  supplies separate delay control signals to each delay circuit to achieve a finer control of the transfer function of the compensator  310 ; and therefore, the memory effect compensation.  
         [0040]    In still another embodiment of the compensator of FIG. 5, a third delay circuit and a fourth delay circuit could be added to the compensator  310  just before the amplifiers  570 ,  580 , respectively, and likewise connected to the baseband circuit  330  to enhance memory compensation control.  
         [0041]    The above invention has several benefits that may be applied to RF amplification. The memory effects of RF amplifiers cause extra unwanted frequencies to be transmitted which interfere with other RF systems and limit the achievable correction in a predistortion system. Moreover, memory effects reduce the efficiencies of an RF system since power is lost due to the unintended transmission of unwanted signals. The invention helps reduce the influence of memory effects on the outputs of RF amplifiers.  
         [0042]    It is noted that the functional blocks in the embodiments of FIGS. 3-5 may be implemented in hardware and/or software. Moreover, while FIGS. 3-5 show the invention used with a RF amplifier, the invention may also be used in conjunction with other components that have or do not have memory characteristics. Still further, the invention may also be used with components with linear characteristics. The hardware/software implementations may include a combination of processor(s) and article(s) of manufacture. The article(s) of manufacture may further include storage media and executable computer program(s). The executable computer program(s) may include the instructions to perform the described operations. The computer executable program(s) may also be provided as part of externally supplied propagated signal(s) either with or without carrier wave(s).  
         [0043]    This specification describes various exemplary embodiments of the method and system of the present invention. The scope of the claims are intended to cover various modifications and equivalent arrangements of the illustrative embodiments disclosed in this specification. Therefore, the following claims should be accorded the reasonably broadest interpretations to cover modifications, equivalent structures in features which are consistent with the spirit and the scope of the invention disclosed herein.