Abstract:
A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time ( 100 ); accurate scanning of the cut-in voltage: a scanning step length is shortened continuously until the scanning step length is shorter than a preset step length, and each time the scanning step length is shortened, the scanning is conducted according to the current shortened scanning step length on the basis of the cut-in voltage determined in the former time, and then the cut-in voltage under the condition of the current shortened scanning step length is determined again ( 200 ). The scanning voltage is automatically increased or decreased by the test method and system through adding high resolution and high precision test conversion into a second scanning test, and therefore the testing of the cut-in voltage becomes more efficient and more accurate.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to semiconductor test field, and more particularly, relates to a test method and system for cut-in voltage of semiconductor product. 
       REARGROUND OF THE INVENTION 
       [0002]    Field effect transistors includes junction field effect transistors and MOS field effect transistors, and are widely applied to various applications. Pinch-off voltage Vp and cut-in voltage Vth are critical direct current parameters of a field effect transistor. Generally, Vth indicates a cut-in voltage of an enhanced field effect transistor. In the enhanced field effect transistor, a voltage is applied to the gate electrode to conduct a inversion on the Si surface, and a certain voltage is applied to the drain electrode to cause a current flowing between the source electrode and the drain electrode. In a test process, the voltage on the gate electrode is scanned, and a test of the current between the source electrode and the drain electrode is conducted simultaneously. When the current on the drain electrode reaches a target current value (cut-in current), thus, the voltage on the gate electrode is deemed to be the cut-in voltage Vth. 
         [0003]    At present, since the summary of developing a circuit design and the capability of controlling windows for process verification should be provided to client. The manufacture is required to provide the client a lot of mismatch data. Because the test accuracy significantly influences the mismatch test, thus it requires a much more accuracy for the mismatch test of the cut-in voltage than that of a normal test, so as to meet the demand of the test. 
         [0004]    For current test method for cut-in voltage, a scanning is conducted on the gate electrode with a voltage increasing from 0 volts. The scanning step length is set, and the current on the drain electrode is measured. The target current value is set to be 1 μA. The drain electrode current and the target current are compared, when the drain electrode current reaches the target electrode current, the current cut-in voltage value is returned. Adopting such scanning mode, when the drain electrode current reaching the target current value is measured for one time, the test is terminated. If the set step length is too large, the test accuracy is significantly influenced. If the set step length is too small, the test efficiency is significantly influenced. 
         [0005]    Because a lot of mismatch tests of cut-in voltage are conducted in the process verification and the process development stage. Therefore, the scanning range mode of the current cut-in voltage test method is one time scanning. It cannot be reasonably set to meet the requirements of the accuracy and the efficiency of the mismatch test. 
       SUMMARY OF THE INVENTION 
       [0006]    Accordingly, it is necessary for the invention to provide a test method and system for cut-in voltage, which is capable of conducting an accurate and efficient test, meeting a requirement of cut-in voltage test such as a mismatch test requiring a very high accuracy. 
         [0007]    The invention discloses a test method for cut-in voltage, including: 
         [0008]    step A, a coarse scanning of the cut-in voltage: determining a scanning cut-in voltage at a coarse scanning step length; 
         [0009]    step B, an accurate scanning of the cut-in voltage: conducting a scanning taking a shortened scanning step length as a current scanning step length, which is on basis of the scanning cut-in voltage corresponding to previous scanning step length, and determining a scanning cut-in voltage corresponding to the shortened scanning step length; shortening the scanning step length continuously and conducting the scanning accordingly, until the previous scanning step length is shorter than a preset step length, and calculating the cut-in voltage according to the last scanning result; 
         [0010]    wherein the scanning cut-in voltage is the minimum gate electrode voltage which allows a drain electrode current to be greater than a target current at the current scanning step length. 
         [0011]    Preferably, step B specifically includes: 
         [0012]    step B 01 , determining whether a previous scanning step length is greater than the preset step length, if the previous scanning step length is greater than or equal to the preset step length, then shortening the current scanning step length to obtain the current scanning step length; if the current scanning step length is less than the preset step length, then executing step B 05 ; if else, executing step B 02 ; 
         [0013]    step B 02 , measuring the drain electrode current when the drain electrode voltage is the scanning cut-in voltage corresponding to the previous scanning step length, and comparing the drain electrode current to a target current, if the drain electrode current is less than the target current, executing step B 03 ; if else, executing step B 04 ; 
         [0014]    step B 03 , increasing the gate electrode voltage step by step according to the current scanning step length, measuring the corresponding drain electrode current, until the drain electrode current is greater than or equal to the target current for the first time, then returning the current gate electrode voltage as the scanning cut-in voltage corresponding to the current scanning step length, simultaneously returning the drain electrode current corresponding to the scanning cut-in voltage, the maximum drain electrode current which is less than the target current in the scanning, the corresponding gate electrode voltage, and executing step B 01 ; 
         [0015]    step B 04 , decreasing the gate electrode voltage step by step according to the current scanning step length, measuring the corresponding drain electrode current, until the drain electrode current is less than the target current for the first time, then returning the gate electrode voltage corresponding to the minimum drain electrode current which is greater than or equal to the target current, taking the gate electrode voltage as the current scanning step length, simultaneously returning the drain electrode current corresponding to the scanning cut-in voltage, the maximum drain electrode current which is less than the target current in the scanning, the corresponding gate electrode voltage, and executing step B 01 ; 
         [0016]    step B 05 , calculating the cut-in voltage according to the cut-in voltage returned by the last scanning result, the corresponding drain current, the maximum drain electrode current which is less than the target current, and the corresponding gate electrode voltage. 
         [0017]    Preferably, in step B 01 , shortening the current scanning step length includes multiplying the scanning step length by a shortening coefficient, the shortening coefficient λ is subject to the range 0&lt;λ&lt;1. 
         [0018]    Preferably, the shortening coefficient λ is 1/10. 
         [0019]    Preferably, step B 04  further includes: after each change of the gate electrode voltage, comparing the changed gate electrode voltage to a voltage lower limit, if the changed gate electrode voltage is less than the voltage lower limit, returning an error. 
         [0020]    Preferably, the voltage lower limit is set to be 2 times of an initial scanning gate electrode voltage. 
         [0021]    Preferably, step B 03  further includes: after each change of the gate electrode voltage, comparing the changed gate electrode voltage to a voltage upper limit, if the changed gate electrode voltage is greater than the voltage upper limit, returning an error. 
         [0022]    Preferably, the voltage upper limit is set to be 2 times of the maximum scanning gate electrode voltage. 
         [0023]    Preferably, the step of calculating the cut-in voltage according to the cut-in voltage returned by the last scanning result, the corresponding drain current, the maximum drain electrode current which is less than the target current, and the corresponding gate electrode voltage, is directly returning the scanning cut-in voltage of the last scanning as the cut-in voltage, or calculating via the following formula: 
         [0000]        K =( Id 2− Id 1)/ Vg step
 
         [0000]        B =( Vg 2* Id 1− Vg 1* Id 2)/ Vg step
 
         [0024]    the Rslt=P*(Itarget−B)/K is returned as the cut-in voltage; 
         [0025]    wherein the field effect transistor is a P-type transistor, the value of P is −1, when the field effect transistor is a N-type transistor, the value of P is 1, Vg 2  represents the scanning cut-in voltage obtained by the last scanning, Id 2  represents the drain electrode current corresponding to the Vg 2 , Id 1  represents the maximum drain electrode current value which is less than the target current at the last scanning, Vg 1  represents the gate electrode voltage corresponding to Id 1 , Vgstep represents the scanning step length at the last scanning, Itarget represents the target current. 
         [0026]    The invention further discloses a test system for cut-in voltage, including: 
         [0027]    a coarse scanning module, configured for determining a scanning cut-in voltage at a coarse scanning step length; 
         [0028]    an accurate scanning, configured for conducting a scanning taking a shortened scanning step length as current scanning step length, which is on basis of the scanning cut-in voltage corresponding to previous scanning step length, determining the scanning voltage corresponding to the shortened scanning step length; shortening the scanning step length continuously and conducting the scanning accordingly, until the previous scanning step length is shorter than a preset step length, and calculating a cut-in voltage according to the last scanning result; 
         [0029]    wherein the scanning voltage is a minimum gate electrode voltage which allows the drain electrode current to be greater than the gate electrode current value at the current scanning step length. 
         [0030]    In the technical solution according to the invention, the test value of the cut-in voltage is permitted to be more effective and accuracy, by adding a high resolution and accuracy test inversion to the accurate scanning test step, and increasing/decreasing the scanning voltage value automatically. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIG. 1  is a major flowchart of a test method for cut-in voltage according to the invention. 
           [0032]      FIG. 2  is a test flowchart for cut-in voltage, according to a specific embodiment of the invention. 
           [0033]      FIG. 3  is a schematically block diagram of a test system for cut-in voltage, according to a specific embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0034]    Embodiments of the invention are described more fully hereinafter with reference to the accompanying drawings. The various embodiments of the invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, it should be noted that, for easily illustration, only part of apparatus/method associated with the invention are shown in the accompanying figures. 
         [0035]      FIG. 1  shows a major flowchart of a test method for cut-in voltage, according to the invention. As shown in  FIG. 1 , the method includes: 
         [0036]    Step  100 , a coarse scanning of the cut-in voltage: scanning cut-in voltage at the coarse scanning step length is determined; 
         [0037]    Step  200 , an accurate scanning of the cut-in voltage: on basis of the scanning cut-in voltage corresponding to the previous scanning step length, taking the shortened scanning step length as the present scanning step length, a scanning is conducted; the scanning voltage corresponding to the shortened scanning step length is determined; the scanning step length is shortened continuously and the scanning is conducted accordingly, until the previous scanning step length is shorter than a preset step length, and thereby the cut-in voltage is calculated according to the last scanning result. 
         [0038]    The scanning cut-in voltage is the minimum gate electrode voltage which allows the drain electrode current value greater than the source electrode current value at the current scanning step length. 
         [0039]    In the technical solution according to the invention, the test value of the cut-in voltage is permitted to be more effective and accuracy, by adding a high resolution and accuracy test inversion to the accurate scanning test step, thereby increasing/decreasing the scanning voltage value automatically. 
         [0040]      FIG. 2  is a test flowchart for cut-in voltage, according to a specific embodiment of the invention. As shown in  FIG. 2 , the method includes: 
         [0041]    Step  100 , a coarse scanning of the cut-in voltage: scanning cut-in voltage executed by the coarse scanning step length is determined; 
         [0042]    Step  200 , an accurate scanning of the cut-in voltage: on basis of the scanning cut-in voltage corresponding to the previous scanning step length, taking the shortened scanning step length as the current scanning step length, a scanning is conducted; the scanning voltage corresponding to the shortened scanning step length is determined; the scanning step length is shortened continuously and the scanning is conducted accordingly, until the previous scanning step length is shorter than a preset step length, and the cut-in voltage is calculated according to the last scanning result. 
         [0043]    The step  200  specifically includes: 
         [0044]    Step  210 : the previous scanning step length Vgstep and the preset step length are compared, when the previous scanning step length Vgstep is greater than or equal to the preset step length, then the current scanning step length Vgstep is shortened; when the previous scanning step length Vgstep is less than the preset step length, then the following step  250  is executed. The less the step length, the higher the accuracy. 
         [0045]    Step  220 , when the drain electrode voltage is the scanning cut-in voltage Vg 2  corresponding to the previous scanning step length, the drain electrode current Id 2  is measured again. The drain electrode current Id 2  and the target current Itarget are compared, when the Id 2  is less than the Itarget, step  230  is executed; if else, step  240  is executed subsequently. 
         [0046]    Step  230 , Vg 1 =Vg 2  and Id 1 =Id 2  are recorded, i.e. employing Vg 1  and Id 1  to record a relative small gate electrode voltage and drain electrode voltage of the previous detection. Taking Vg 2  as the current gate electrode voltage, detection is conducted. The gate electrode voltage is adjusted according to Vg 2 =Vg 2 +Vgstep, and the corresponding drain electrode current Id 2  is measured. When the drain electrode current Id 2  is greater than the target current Itarget, the Vg 1 , Vg 2 , Id 1  and Id 2  are returned, and step  210  is executed subsequently. 
         [0047]    At this time, Vg 2  and Id 2  are the scanning cut-in voltage and the drain electrode current corresponding to the scanning cut-in voltage. Id 1  and Vg 1  are the previous adjustment of the gate electrode. Actually, they are the maximum drain electrode current value which is less than the target current in the current scanning, and the gate electrode voltage corresponding to the drain electrode current, respectively. 
         [0048]    Step  240 , Vg 2 =Vg 1  and Id 2 =Id 1  are recorded, i.e. employing Vg 2  and Id 2  to record a relative greater gate electrode voltage and drain electrode voltage of previous detection. Taking Vg 1  as the current gate electrode voltage, detection is conducted. The gate electrode voltage is adjusted according to Vg 1 =Vg 1 -Vgstep, and the corresponding drain electrode current Id 1  is measured. When the drain electrode current Id 1  is less than the target current Itarget, the Vg 1 , Vg 2 , Id 1  and Id 2  are returned, and step  210  is executed subsequently. 
         [0049]    At this time, because Id 1  is the drain electrode current value which is less than the target current for the first time, therefore, Vg 2  and Id 2 , as the gate electrode voltage and the drain electrode current in the previous detection. Id 2  is definitely the minimum drain electrode current value which is greater than the target current value. Therefore, Vd 2  is the minimum drain electrode voltage value when the drain electrode current at the current scanning step is greater than the target current value, Vd 2  can be served as the scanning cut-in voltage of the current scanning. Actually, Vg 1  and Id 1  are the maximum drain electrode current which is less than the target current in the current scanning, and the gate electrode voltage corresponding to the drain electrode, respectively. 
         [0050]    Step  250 , the cut-in voltage is acquired, according to the returned result. 
         [0051]    Actually, if the current jump does not emerge in the measuring process. The drain electrode current corresponding to the scanning cut-in voltage obtained by scanning at each scanning step length should be greater than the target current Itarget. In step  220 , when the drain electrode voltage is the scanning cut-in voltage corresponding to the previous scanning step length, the drain electrode current is measured again to avoid an occurrence of current transition on the device. When the current jump emerged in the previous detection causes the drain electrode current of the scanning cut-in voltage corresponding to the scanning before previous to be less than the target current, step  230  is executed to correct the drain electrode current in the method according to the embodiment, therefore, the gate electrode voltage is increased step by step according to the shortened scanning step length, a scanning is performed to obtain a scanning cut-in voltage corresponding to the scanning step length. 
         [0052]    Due to the adding of step  220  and step  230 , an occurrence of scanning error subjected to the current transition can be avoided, the test accurate and efficiency of the cut-in voltage is greatly enhanced. 
         [0053]    Generally, the scanning step length of the coarse scanning is far greater than the scanning step length of the accurate scanning, such that an efficiency of the coarse scanning can be enhanced. 
         [0054]    Alternatively, in step  210 , the current scanning step length can be proportionally shortened, such as Vgstep=Wgstep, the shorten coefficient λ, is subject to the range: 0&lt;λ&lt;1. λ can be 1/10, and also, the scanning can be performed by echelon, and whether the selected step length is too large can be determined automatically, thus the step length can be shortened automatically and reasonably. The step length can also be set as 0.0001 
         [0055]    Alternatively, in step  230 , further including: after each change of the Vg 2 , the Vg 2  is compared to a voltage upper limit. When the Vg 2  is greater than the voltage upper limit, the process is terminated. For example, when the voltage upper limit is set to be 2 times of Vgmax. Thereby, it can be executed efficiently, and error can be prevented timely. 
         [0056]    Alternatively, in step  240 , further including: after each change of the Vg 2 , the Vg 2  is compared to a voltage lower limit. When the Vg 2  is less than the voltage lower limit, the process is terminated. For example, when the voltage lower limit is set to be 2 times of Vgstart. Thereby, it can be executed efficiently, and error can be prevented timely. 
         [0057]    In step  250 , the returned Vg 2  can be directly taken as the cut-in voltage, and a much more accurate cut-in voltage value can be acquired via the following formula: 
         [0000]        K =( Id 2− Id 1)/ Vg step,
 
         [0000]        B =( Vg 2* Id 1− Vg 1* Id 2)/ Vg step
 
         [0058]    Rslt=P*(Itarget−B)/K, when the field effect transistor is a P-type transistor, the value of P is −1, when the field effect transistor is a N-type transistor, the value of P is 1 
         [0059]    The method of the invention can be applied on UINX operation system, and is based on  4070  programming platform. In the programming platform, above-described method is written as a subprogram, the main program fragment is illustrated as follows: 
         [0000]    
       
         
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 For Vg2=Vgstart to Vgmax STEP Vgstep 
               
               
                   
                  Force_w(G,P*Vg2,Vg2,1.E−6) 
               
               
                   
                 Measure_i(D,Id2,Icomp) 
               
               
                   
                 ld2=P*ld2 
               
               
                   
                 IF Id2&gt;=Itatget THEN Out1 
               
               
                   
                 Vg1=vg2 
               
               
                   
                 ld1=ld2 
               
               
                   
                 NEXT Vg2 
               
               
                   
                 Out1:! 
               
               
                   
                 Set_adc(1,2) 
               
               
                   
                 Set_smu_ch(32701,1,1) 
               
               
                   
                 IF ld1=0 OR ld2&lt;Itatget THEN Out2 
               
               
                   
                 While Vgstep&gt;=0.0001 
               
               
                   
                 Vgstep=Vestep/10 
               
               
                   
                 Force_v(G,P*Vg2,Vg2,1.E−6) 
               
               
                   
                 Measure_i(D,Id2,Icomp) 
               
               
                   
                 Id2=P*Id2 
               
               
                   
                 IF Id2&lt;Itarget THEN 
               
             
          
           
               
                   
                 WHILE Id2&lt;Itarget 
               
             
          
           
               
                   
                 Vg1=Vg2 
               
               
                   
                 Id1=Id2 
               
             
          
           
               
                   
                 Vg2=Vg2+Vgstep 
               
               
                   
                 IF Vg2&gt;2*Vgmax THEN Out2 
               
               
                   
                 Force_v(G,P*Vg2,Vg2,1.E−6) 
               
               
                   
                 Measure_i(D,Id2,Icomp) 
               
               
                   
                 Id2=P*Id2 
               
             
          
           
               
                   
                 END WHILE 
               
               
                   
                 Rslt=Vg2 
               
             
          
           
               
                   
                 ELSE 
               
             
          
           
               
                   
                 Vg1=Vg2 
               
               
                   
                 Id1=Id2 
               
             
          
           
               
                   
                 WHILE Id1&gt;=Itarget 
               
             
          
           
               
                   
                 Vg2=Vg1 
               
               
                   
                 Id2=Id1 
               
             
          
           
               
                   
                 Vg1=Vg1−Vgstep 
               
               
                   
                 IF Vg1&lt;2*Vgstart THEN Out2 
               
               
                   
                 Force_v(G,P*Vg1,Vg1,1.E−6) 
               
               
                   
                 Measuret_i(D,Id1,Icomp) 
               
               
                   
                 Id1=P*Id1 
               
             
          
           
               
                   
                 END WHILE 
               
               
                   
                 Rslt=Vg1 
               
             
          
           
               
                   
                 END IF 
               
               
                   
                 END WHILE 
               
               
                   
                 K=(Id2−Id1)/Vgstep 
               
               
                   
                 B=(Vg2*Id1−Vg1*Id2)/Vgstep 
               
               
                   
                 IF K=0 THEN Out2 
               
               
                   
                 Rslt=P*(Itatget−B)/K 
               
               
                   
                 Rslt=PROUND(Rslt,−5) 
               
               
                   
                 ! 
               
               
                   
                 Out2:! 
               
               
                   
                 Set_adc(0,1) 
               
               
                   
                 Set_smu_ch(32701,0,0) 
               
               
                   
                 Disable_port 
               
               
                   
                 Connect 
               
               
                   
                 SUBEND 
               
               
                   
                 ! 
               
               
                   
                   
               
             
          
         
       
     
         [0060]      FIG. 3  is a block diagram of a test system for cut-in voltage, according to an embodiment of the invention, the test system includes: 
         [0061]    a coarse scanning module, configured for determining the scanning cut-in voltage at the coarse scanning step length; 
         [0062]    an accurate scanning module, configured for conducting a scanning taking a shortened scanning step length as the present scanning step length, which is on basis of the scanning cut-in voltage corresponding to the previous scanning step length, and determining the scanning voltage corresponding to the shortened scanning step length; shortening the scanning step length continuously and conducting the scanning accordingly, until the previous scanning step length is shorter than a preset step length, and calculating the cut-in voltage according to the last scanning result. 
         [0063]    The scanning voltage is the minimum gate electrode voltage which allows the drain electrode current value to be greater than the source electrode current value at the current scanning step length. 
         [0064]    In one embodiment, the accurate scanning module of the cut-in voltage includes: 
         [0065]    a step length shortened module: configured for comparing the current scanning step length and the preset step length, when the current scanning step length Vgstep is greater than or equal to the preset step length, the current scanning step length Vgstep is shortened; when the drain electrode voltage is equal to Vg 2 , the drain electrode current Id 2  is measured again. The less the step length, the higher the accuracy, for example, the new scanning step length can be obtained by proportionally shortening, Vgstep=λVgstep, alternatively, scan be 1/10. 
         [0066]    a current comparing module, configured for comparing the drain electrode current Id 2  and the target current Itarget. 
         [0067]    a record progressive increase module, configured for recording Vg 1 =Vg 2  and Id 1 =Id 2 , adjusting the gate electrode voltage Vg 2 =Vg 2 +Vgstep, and measuring the drain electrode current Id 2 , when the drain electrode current Id 2  is less than the target current Itarget. When the current measured drain electrode current Id 2  is greater than or equal to the target current Itarget, the record progressive increase module returns Vg 1 , Vg 2 , Id 1  and Id 2  to a returning module. If else, the record progressive increase module continues to work. 
         [0068]    a record progressive decrease module, configured for recording Vg 2 =Vg 1  and Id 2 =Id 1 , adjusting the gate electrode voltage Vg 1 =Vg 1 −Vgstep, and measuring the drain electrode current Id 1 , when the drain electrode current Id 2  is greater than or equal to the target current Itarget. When the current measured drain electrode current Id 1  is less than the target current Itarget, the record progressive decrease module returns Vg 1 , Vg 2 , Id 1  and Id 2  to the returning module. If else, the record progressive decrease module continues to work. 
         [0069]    a returning module, configured for acquiring a cut-in voltage according to the returned result, when the current scanning step length is less than the preset step length. 
         [0070]    One skilled in the art can know that when above-described method is directly written into an independent subprogram, and saved in the subprogram library, it facilitates to widely applications of subsequent test, and acquires accurate test results. When newly constructed program for the mismatch test product, all the cut-in voltage test program can select and use the subprogram to conduct a test. 
         [0071]    The technical solution of the invention enables to conduct an accurate and efficient test, and meets a requirement of cut-in voltage test such as a mismatch test which requires a very high accuracy. 
         [0072]    One skilled in the art can understood that, all or part of the steps of above-described examples can be implemented by using program to execute on corresponding hardware, all the program can be saved in a computer readable storage medium (such as ROM/RAM, magnetic disks; optical disks and so on). 
         [0073]    It should be noted that, the present invention has been described with reference to the best modes and principle for carrying out the present invention, which is not intended to be limited by specific embodiment. It is apparent to those skilled in the art that a variety of modifications, changes and replacements may be made without departing from the scope of the present invention. Therefore, although the present invention is illustrated and described herein with reference to specific embodiments, the present invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the present invention.