Abstract:
A method and system for dynamic limiting of the pulse width or duty cycle of a switched DC-to-DC power supply. The system includes a first comparator coupled to the voltage to be regulated and to a reference voltage for generating an error signal. The error signal controls the duty cycle or pulse width of a PWM. A limiter circuit includes a further comparator which compares the error signal to a second reference voltage to generate a further limiting feedback signal for application to the first comparator. When the error signal tends to rise above a value established by the second reference voltage, the limiter applies a signal to the first comparator tending to reduce the error signal to thereby prevent the error signal from rising sufficiently to produce the undesired operating condition.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit, pursuant to 35 USC §119, of earlier-filed U.S. Provisional Patent Application Ser. No. 60/451,576, entitled “Dynamic Duty Cycle Clamping for Switching Converters,” filed on Mar. 3, 2003, the whole of which is incorporated by reference herein. 

   FIELD OF THE INVENTION 
   This application relates to the field of power supplies and, more specifically, to dynamically limiting the ratio of ON-time to OFF-time of a power switch in pulse-width modulated switching DC/DC converters. 
   BACKGROUND OF THE INVENTION 
   Pulse width modulated, or regulated, switched DC/DC power converters are well known in the art. In such power converters, numerous conditions may arise in which the modulating pulse duration undesirably exceeds a predetermined maximum value. Under these conditions, critical circuit components may be overstressed and may consequently fail to operate properly, or may even be degraded or fail. As one example of failure to operate properly, magnetic cores may become saturated by an excessive ON duration of a power switch, which may result in degradation of circuit performance, in turn resulting in poor voltage regulation. Methods for limiting or clamping the pulse width output to prevent overstressing or poor voltage regulation are known. 
     FIGS. 1   a  and  1   b  are representative of two generally similar methods for limiting or clamping the pulse width of a pulse width modulator to prevent component stress.  FIG. 1   a  is a simplified circuit diagram of a DC/DC converter  100  using conventional regulation with clamped maximum duty cycle. In  FIG. 1   a , a pulse width modulator (PWM)  110  is controlled by the magnitude of an error signal or voltage V e  applied to an input port  110   i  to produce pulses, illustrated as  105 , having controlled duration or width. Such pulse width modulators often include an internal sawtooth- or triangle-signal generator and a comparator, for comparing the sawtooth with the applied error voltage, to generate variable-duration, low-magnitude pulses  105 . The low-amplitude pulses  105  produced by PWM  110  of  FIG. 1   a  drive a power amplifier or power switch illustrated as a block  107 . As illustrated in block  107 , the switch is represented by a mechanical movable switch element  107 M which moves in the direction of double-headed arrow  107 A under control of the low-level pulses  105 , to periodically connect movable element M to a source  103  of unregulated voltage or B+. The resulting high magnitude pulses, illustrated in  FIG. 1   a  as  109 , are filtered by a filter, illustrated as  108 , to produce direct voltage, and the resulting direct voltage is applied to an output port  145  as the desired output voltage V o . 
   In  FIG. 1   a , the output voltage V o  produced at output port  145  is coupled by way of an attenuator  140 , a noninverting amplifier  135 , and a comparator  120  input impedance  130  illustrated as a block Zi to the inverting (−) input port  121  of comparator  120 . Those skilled in the art know that the input impedance of an input port of a comparator or amplifier is high. A reference voltage V ref  is applied by way of a terminal  160  and a filter capacitor  134  to noninverting (+) input port  122  of comparator  120 . Those skilled in the art know that a comparator is simply a high-gain amplifier, and may be considered to be such. A feedback impedance Z f    125  is coupled from the output port  120   o  of comparator  120  to inverting input terminal  121 , for interacting with input impedance  130  for controlling the gain of the comparator. Comparator  120  in conjunction with its associated gain controlling resistors  125  and  130  produces an error signal or voltage V e  at its output port  120   o  for application to input port  110   i  of PWM  110 . 
   The error signal or voltage V e  produced by comparator  120  of  FIG. 1   a  is a measure of the deviation of the output voltage V o  at terminal  145  from the desired value. The pulse width modulator  110  responds to changes in the value of the error voltage V e  by adjusting the pulse width of pulses  105  in a manner which tends to reduce the difference, all as is well known in the art. The error voltage V e  applied to pulse width modulator  110  may occasionally be of a magnitude which drives PWM  110  to produce a pulse or pulses of undesirably long duration. This might occur, for example, when the PWM is first turned ON, and the voltage at the output of filter  108  does not immediately respond to the pulses from PWM  110 . 
   The arrangement of  FIG. 1   a  includes an error voltage limiting circuit designated generally as  102 , connected to conductor  112  at a location electrically between output port  120   o  of comparator  120  and input port  110   i  of PWM  110 . As illustrated, the voltage limiter  102  includes a zener diode illustrated as  115 , having a zener voltage V z . When the error voltage V e  attempts to rise above the zener voltage of zener diode  115 , the zener diode conducts, and tends to limit the voltage rise. Those skilled in the art know that the operation of a limiter of this sort depends, at least in part, upon the impedance of the voltage source, and that it may be necessary or desirable to interpose a further impedance  149  between port  120   o  and node  150 . With zener diode  115  in place, the error voltage which drives the pulse width modulator  110  is limited, and cannot achieve values which call for the undesired pulse widths. 
   While the arrangement of  FIG. 1   a  is effective, it depends, at least in part, upon the availability of a zener diode which has a zener voltage V z , or which conducts at an error voltage V e , corresponding to the threshold between allowable and undesired pulse widths. However, zener diodes are produced only with discrete zener voltages, and a zener diode having the desired zener voltage may not be available. The arrangement of  FIG. 1   b  is similar to that of  FIG. 1   a , but the voltage limiter  103  substitutes a transistor together with a voltage source for the zener diode of limiter  102  of  FIG. 1   a . In the arrangement of  FIG. 1   b , limiter  103  includes a bipolar PNP transistor having its emitter connected to node  150  and its collector grounded. A direct voltage source illustrated by a battery symbol  175  has its negative terminal grounded and its positive terminal connected to the base of transistor  170 . The voltage of source  175  may be designated V m . Transistor  170  will be nonconductive so long as the error voltage V e  at node  150  does not exceed the sum of the voltage V m  of source  175  plus one base-emitter voltage drop (one V BE ). When the error signal or voltage V e  at node  150  exceeds V m +V BE , transistor  170  will conduct to limit the error voltage. The arrangement of  FIG. 1   b  is advantageous by comparison with that of  FIG. 1   a  because the limiting voltage of limiter  103  can be adjusted by simply adjusting the voltage of source  175 . 
   In operation of the arrangements of either  FIG. 1   a  or  FIG. 1   b , an increase of error voltage V e  tends to increase the pulse width of the pulses produced by PWM  110 . At some point during the increase of the error voltage, the limiter  102  or  103  becomes conductive, and prevents any further increase in the error voltage. Consequently, the error voltage can never reach a value such that the undesirably long pulse widths occur. 
   While these methods are commonly used to clamp the pulse width output, they suffer from long device recovery time when those conditions tending to cause the longer pulse widths are removed. For example, it is known that during a startup, greater pulse widths are produced by pulse width modulator  110  in order to quickly achieve the desired output voltage level. Elaborate schemes, referred to as soft-starts, have been developed to ensure a gradual increase in the operating duty cycle in order to prevent clamping or limiting from occurring. Absent soft-start mechanisms, transient operating conditions associated with the duty cycle may result in clamping at a maximum pulse width that extends over many tens of switching cycles and which unnecessarily overstress components. 
     FIG. 1   c  illustrates error voltage V e  and the resulting pulse-width modulated pulses  105  (of  FIG. 1   a  or  1   b ) during successive time periods of normal operation, during clamping, and during a post-clamping recovery period. In  FIG. 1   c , an interval of normal operation is designated as  182 , which is a subset of times  180 . During the interval  182  of normal operation, the error voltage V e  illustrated by plot  112  takes on a range which may be viewed as a normal range. The pulses produced by PWM  110  of  FIG. 1   a  or  1   b  have a nominal duration in interval  182 . Region  185  represents a time during which the error voltage V e  increases toward, and reaches, a limiting voltage. The limiting voltage is variously designated V z  or (V BE +Vm) to represent static (unchanging) zener-diode limiting or transistor limiting, respectively. The resulting pulse durations in region  185  are shown as wide. The condition causing the excessive error voltage V e  is presumed to end at a time lying between time duration  185  and time duration  190 . At this time, the error voltage should decrease to the normal region obtaining during the interval  182  of  FIG. 1   c . However, due to the characteristics of diodes and transistors, there is a recovery time in the interval  190  during which the clamped error voltage remains at the clamp level. Since, in the presence of such a long recovery time, the error voltage cannot decrease to the normal range rapidly during interval  190 , at least a portion of the clamped value of error voltage V e  in the interval  190  unnecessarily keeps the pulse width greater than it might otherwise be. After the recovery interval  190 , the error voltage lies in the normal range. 
   Hence, there is a need for a method and apparatus for providing a clamping that provides for more rapid recovery once the event causing duty cycle clamping is removed. 
   SUMMARY OF THE INVENTION 
   An improvement for Pulse Width Modulation (PWM) regulation of DC/DC voltage converters according to an aspect of the invention, in which at least a sample of the regulated output voltage is provided to a first input port of a feedback network and a reference voltage is applied to a second input port of the feedback network. The feedback network produces an error signal for application to a pulse width modulator. The improvement comprises a second circuit responsive to the error signal and to a second reference voltage, for providing a further signal to the first input port of the feedback network when the error signal exceeds the second reference voltage, for tending to limit the error signal. In this aspect, a preferred embodiment includes an arrangement for isolating an output of the second circuit from the first input. The second circuit may include a comparator or a linear amplifier. In a more preferred embodiment, the second circuit includes a comparator or a linear amplifier having a first input and a second input. The second reference voltage may be variable. An arrangement may be provided for monitoring or making available the output of the second circuit. 
   A method according to an avatar of the invention is for providing dynamic clamping regulation in PWM regulated DC/DC converters. The method comprises the step of providing an error signal to a first input of a comparator through a first feedback circuit. At least a sample of a DC voltage to be regulated is applied to the first input and a reference voltage is applied to a second input of the comparator. A signal responsive to the error signal is independently provided to the first input by way of a second feedback circuit when the error signal is greater than a second reference voltage. In this avatar, the independently provided signal may be isolated from the first input during those times in which the error signal is not greater than the second reference voltage. The second reference voltage may be variable and/or varied. 
   In another hypostasis of the invention, a device provides dynamic clamping regulation in a PWM regulated DC/DC converter. The device comprises a first feedback circuit operable to provide a signal responsive to an output voltage of a first comparator to a first input of the first comparator. In this hypostasis, at least a sample of a DC voltage to be regulated is also applied to the first input and a reference voltage is applied to a second input of the first comparator. A second feedback circuit is operable when the output voltage of the first comparator is greater than a second reference voltage to independently provide to the first input port of the first comparator a signal responsive to a difference between the second reference voltage and the output voltage of the first comparator. In a preferred version of this hypostasis, the device includes an arrangement for isolating the second feedback circuit output from the first input of the comparator. The preferred version of the device also includes a second circuit having a first input and a second input operable to generate an output when the output voltage of the first comparator is greater than a second reference voltage applied to the second input. The second circuit may be selected from the group consisting of (a) linear amplifier and (b) comparator. Means may be provided for monitoring or making available the output signal of the second circuit. In one version of this hypostasis, the second reference voltage may be varied. 
   An avatar of the invention is for providing dynamic clamping voltage regulation. This avatar includes a first feedback circuit operable to couple or provide a first comparator output to a first input of the comparator. A voltage to be regulated is concurrently applied to the first input and a reference voltage is applied to a second input. A second feedback circuit is operable to independently provide to the first input a signal responsive to the first comparator output when the first comparator output is greater than a second reference voltage. This avatar may include means for isolating the second feedback circuit output from the first input. The second feedback circuit may include a circuit having a first input and a second input operable to generate an output signal when the first comparator output is greater than a second reference voltage applied to the second input of the circuit. The circuit may be selected from the group consisting of (a) linear amplifier and (b) comparator. This avatar may include means for monitoring or making available the output signal of the circuit. The second reference voltage may be varied. The voltage to be regulated may be the output of a DC/DC converter. 
   Thus, the invention relates to an improvement for regulation of Pulse Width Modulation (PWM) for DC/DC voltage converters wherein at least a sample of the output voltage to be regulated is provided to a first input or input port of a network, and a reference voltage is applied to a second input or input port of the network. The network includes a degenerative feedback circuit operative to provide an error signal to a pulse width modulator. The improvement comprises a second feedback circuit responsive to the error signal, for coupling a further signal to the first input port of the network when the error signal exceeds a second reference voltage. A particular embodiment of the improvement includes an isolator for isolating the further signal from the first input. The network may include a comparator or a linear amplifier. 
   In a particular version of the improvement, the second reference voltage is variable to allow a unique response. 
   This invention takes pulse-width modulated or regulated switched DC/DC power converters to a higher robustness in performance by taking the advantage of non-saturating limit-cycle. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
       FIG. 1   a  illustrates one embodiment of a conventional regulator for a DC/DC voltage converter including a zener diode limiter,  FIG. 1   b  is similar but uses a transistor limiter, and  FIG. 1   c  illustrates voltage waveforms for an exemplary “static” clamping of the circuits shown in  FIG. 1   a  or  1   b;    
       FIG. 2   a  illustrates an exemplary embodiment of a dynamically-clamped regulator for a DC/DC voltage converter in accordance with the principles of the invention,  FIG. 2   b  illustrates voltage waveforms for one embodiment of dynamically clamped converter in accordance with the principles of the invention, and  FIG. 2   c  illustrates voltage waveforms for a second embodiment of dynamically clamped converter in accordance with the principles of the invention; 
       FIGS. 3   a  and  3   b  illustrate exemplary voltage waveforms corresponding to the voltage converter shown in  FIG. 1   a ; and 
       FIGS. 4   a ,  4   b , and  4   c  illustrate exemplary voltage waveforms corresponding to the dynamically clamped converter shown in  FIG. 2   a.    
   

   It is to be understood that these drawings are solely for purposes of illustrating the concepts of the invention and are not intended as a definition of the limits of the invention. The embodiments shown in  FIGS. 1 through 4   c  and described in the accompanying detailed description are to be used as illustrative embodiments and should not be construed as the only manner of practicing the invention. Also, the same reference numerals, possibly supplemented with reference characters where appropriate, have been used to identify similar elements. 
   DESCRIPTION OF THE INVENTION 
     FIG. 2   a  illustrates an exemplary embodiment of a dynamic clamping circuit  200  in accordance with the principles of the present invention. In this embodiment, a circuit  210  is electrically connected as a second feed-back network in parallel with feed-back network  125 . 
   In this embodiment, the output voltage V e  produced at output port  120   o  of comparator  120  is applied by way of a resistor  220  having a value of R 1  to the noninverting input port of a second comparator circuit  215  of clamping circuit  200 . The error voltage V e  produced at output port  120   o  of comparator  120  is compared in comparator  215  with a second reference voltage V m  applied by way of a resistor  230  having a value of R 2  to the inverting input port of the comparator. Comparator circuit  215  responds to the comparison of the error voltage V e  with second reference voltage V m  to produce a voltage designated V o2  at output port  217  of comparator circuit  215 . The output voltage V o2  produced at the output port  217  of comparator  215  is applied by way of a diode  240  and a resistor  235  having a value of R 3  to the inverting input port  121  of comparator  120 . In a first embodiment of the arrangement of  FIG. 2   a , comparator  215  may be a linear amplifier, and in a second aspect of the invention, circuit  215  may be a comparator. 
   During normal operation of second feedback circuit  210  of  FIG. 2   a , the output voltage V o2  of comparator circuit  215  remains at a nominally low value so long as the value of error signal or voltage V e    112  is less than the value of reference voltage (V m )  225 . When voltage V o2  is lower or more negative than the voltage applied to the noninverting input port of comparator  120 , diode  240  remains nonconductive. Thus, diode D 1    240  operates as an isolator to ensure that the output voltage V o2  of circuit  215  does not interfere with the operation of the networks Z i  and Z f  surrounding error amplifier or comparator  120  when comparator  215  finds that the error voltage V e  is less than (more negative than) second reference voltage V m . The use of diode D 1    240  is further advantageous, in that it avoids the need to have output voltage V o2  go to a value of zero volts when in a low state. Instead, voltage V o2  can, in the low state, assume any value less than the sum of the voltage at noninverting input port  121  plus one V BE . Hence, single-supply operation of circuit  215  is possible. 
   In operation of arrangement  200  of  FIG. 2   a , when error voltage V e  ( 112  of  FIG. 2   b ) exceeds reference voltage V m  applied to terminal  225 , the signal is amplified by amplifier/comparator  215  and its output voltage V o2  becomes more positive. When voltage V o2  becomes more positive by one diode voltage drop (one V BE ) than the voltage at port  121  of amplifier/comparator  120 , diode  240  conducts, and the signal V o2  is applied to high impedance port  121 . The signal V o2  may be viewed as being superposed over the signal from attenuator  140 , inverter  135 , and impedance  130 , “overriding” or “swamping” the voltage which would otherwise appear at port  121 . Thus, when the error voltage V e  produced at output port  120   o  of amplifier/comparator  120  exceeds the value of reference voltage V m , circuit  210  applies a superposing positive signal to the inverting input port of comparator  120 . Application of this additional positive voltage to inverting input port  121  tends to drive the output voltage (V e ) of comparator  120  in a negative direction, or in opposition to the increase which caused the error voltage to exceed the value of V m . This effectively limits the tendency of the error voltage to increase, much as though a conductive limiter  102  or  103  were used. 
   When diode  240  of  FIG. 2   a  conducts, comparator circuit  120  and comparator circuit  215  are coupled together in a feedback loop, in which the output port  217  of comparator  215  is coupled to input port  121  of comparator  120 , and in which output port  120   o  is coupled to the noninverting input port of comparator  215 .  FIG. 2   b  illustrates amplitude-time plots of the error voltage V e  and its relation to reference voltage V m , and the resulting clamping voltage V o2  for the case in which the comparator  215  is an amplifier. In  FIG. 2   b , the reference voltage V m , is designated  225 , and the error voltage V e  is designated  112 . Prior to the time designated t 1  in  FIG. 2   b , the error voltage is in a “normal” region in which it does not exceed voltage V m . Beginning at about time t 1  and continuing through the remainder of the illustrated interval, the error voltage may be considered to be in a limiting range. In the limiting range, the error voltage  112  shows a sawtooth “ripple” or oscillation centered about voltage V m . It will be noted that there are intervals during this ripple during which the error voltage V e  exceeds the reference voltage V m , and other intervals in which the error voltage V e  is less than the reference voltage V m . During those intervals in which the error voltage V e  exceeds the reference voltage V m , the output voltage of comparator  215  of  FIG. 2   a  on output port  217  is an amplified version of the input signal. If comparator/amplifier  215  were operated with both positive and negative direct voltage sources, its output voltage V o2  during those intervals, such as interval  217   c , in which the error voltage V e  is less than the reference voltage V m  would be a negative-going sawtooth similar to  217   a . However, in the embodiment illustrated in  FIG. 2   a , comparator  215  is operated with a single-sided supply, so there is no amplification during times such as  217   c  of  FIG. 2B , so its output voltage V o2  is zero. Thus, voltage V o2  assumes the separated-sawtooth form illustrated in  FIG. 2   b.    
   Thus,  FIG. 2   b  illustrates an example of dynamic clamping regulation in accordance with the principles of the invention. As shown in  FIG. 2   b , voltage (V e )  112  remains at a relatively nominal value similar to that shown in  FIG. 1   c . When an event or condition (not shown) occurs which tends to cause voltage V e    112  to increase, the duration or width of pulses output by PWM  110  also tends to increase, as described in conjunction with  FIG. 1   c . When voltage V e    112  is below or more negative than second reference voltage V m    225 , the output V o2    217  of network  210  remains relatively low (in this illustrated case at zero volts because of single-supply operation) and network  210  is essentially isolated from comparator  120  by the non-conducting state of diode D 1    240 . However, as voltage V e    112  tends to exceed voltage V m    225 , output  217  correspondingly increases, as represented by voltage  217   a  of  FIG. 2   b  and, in turn, places D 1    240  in a conducting state. In this situation, circuit  215  is a linear amplifier, and voltage  217   a  is proportional to the amount by which voltage V e    112  is greater than voltage (V m )  225 . 
   As the output signal V o2  ( 217  of  FIG. 2   b ) is applied to inverting input port  121  of comparator  120  of  FIG. 2   a , the combined input applied to input port  121  causes the output of comparator  120  to decrease, and the value of voltage V e    112  falls below the value of voltage V m    225 . This creates a regenerative oscillation of the error voltage V e  about the value of reference voltage V m . 
   Accordingly, as the condition causing excessive error voltage V e    112  persists, the value of the voltage V e    112  swings or oscillates about voltage V m    225 . Again the output V o2  of comparator  215  of  FIG. 2   a , represented as voltage  217   a  of  FIG. 2   b , increases proportionally to the difference between V e    112  and V m    225 . Meanwhile, the output pulse width of PWM  110  is also forced to decrease or expand cyclically about an average value. 
     FIG. 2   c  illustrates a second example of dynamic clamping in accordance with the principles of the invention. In this case, circuit  215  is representative of a high-speed voltage comparator as opposed to an amplifier. The difference between these two may be considered to be that the comparator has such high gain that its output goes to a saturated level at any finite value of input signal. Thus, a comparator may be considered to have a maximum output voltage of one polarity when the input voltage is above a reference value, and a maximum voltage of the opposite polarity when the input voltage is below the reference value. Thus, a comparator used in place of an amplifier as element  215  of  FIG. 2   a  will produce a saturated, fixed-value output voltage whenever voltage V e    112  is greater than voltage V m    225 . The generation of a fixed or discrete output from circuit  215  is similar to that disclosed with regard to  FIG. 2   b  and need not be discussed again in detail. 
   As shown in  FIGS. 2   b  and  2   c , the amplitude of the ripple of error voltage  112  about V m  (the depth of excursion) is centered around voltage V m    225 . In this case there is a cyclic reduction of the effective average duty cycle of the modulating pulses generated by PWM  110 . However, in another aspect (not shown), the depth of excursion  260  may be a swing between zero volts and voltage V m    225 . In this case, periodic suppression of a group of modulating pulses will occur in addition to a periodic reduction of the average duty cycle. In this aspect, the time period may be in the order of milliseconds and is dependent upon the delay properties of amplifier  120  and feedback network  125 . 
   Returning to  FIG. 2   a , it should be appreciated that voltage V o2  appearing at port  217  of comparator  215  may be made available to pulse width modulator  110 , as for example by way of a conductor designated  250 , for monitoring of voltage  217  or for providing feedback to PWM  110 . 
     FIGS. 3   a  and  3   b  illustrate the direct output voltage V o  generated at output terminal  145 , and the corresponding error voltage V e    112  waveforms at initial turn-on for a pulse width modulated DC/DC converter as shown in  FIG. 1   a . In the situation illustrated in  FIGS. 3   a  and  3   b , as V o    145  begins to increase from zero volts, error voltage V e    112  rises to a maximum value, in this case 15 volts. As output voltage V o    145  increases above its set value, in this case 10 volts, the voltage V e    112  decreases to zero. Voltage V e    112  remains at zero volts during those times in which output voltage V o    145  is greater than the required 10 volts (i.e. during overshoot). As voltage  145  finally approaches the desired 10 volts after the overshoot, voltage  112  increases to a nominal value to stabilize voltage V o    145  at a desired 10 volts value. 
     FIGS. 4   a  and  4   b  illustrate the output V o    145  and the error voltage V e    112  waveforms at initial turn-on for a PWM DC/DC converter as shown in  FIG. 2   a . In this case, similar to that shown in  FIG. 3   a , as output voltage V o    145  increases from zero volts, error voltage V e    112  rises to a maximum value, since voltage V o    145  is below a capture range and the dynamic clamping is not invoked. As output voltage V o    145  increases toward the intended regulation value of 10 volts, dynamic clamping occurs and captures error voltage V e    112 . 
   When output voltage V o  at output terminal  145  is below the capture range, in this case below about 8 to 10 volts, voltage V o2  at point  217  (the output of comparator/amplifier  215 ) is high. However, the superpositioning of a high V o2  and a low V o  is less than the reference voltage V ref  at terminal  160 . In this case V e    112  is therefore determined by the supply for the device  120  rather than the reference voltage V m . 
     FIG. 4   c  represents region  410  of  FIG. 4   b , expanded in both coordinates to better illustrate the oscillation caused by dynamic clamping shown in  FIG. 4   b.    
   While there has been shown, described, and pointed out fundamental novel features of the present invention as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the apparatus described, in the form and details of the devices disclosed, and in their operation, may be made by those skilled in the art without departing from the spirit of the present invention. It is expressly intended that all combinations of those elements that perform substantially the same function in substantially the same way to achieve the same results, even though the processes differ in name, form or shape, are within the scope of the invention. Substitutions of elements from one described embodiment to another are also fully intended and contemplated. 
   Many prior-art control systems may experience transients or other out-of-range conditions which result in saturation. When a portion of a control loop is saturated, the loop is, in effect, open. In other words, the control loop loses control of the controlled parameter(s). According to an aspect of the invention, the dynamic error signal clamping of the control loop tends to avoid saturation, and therefore tends to maintain its control, and regains total control rapidly after a perturbation. 
   Other embodiments of the invention will be apparent to those skilled in the art. For example, the invention may be used in most closed-loop control systems, as for example in a phase-lock loop. 
   An improvement for Pulse Width Modulation (PWM) regulation of DC/DC voltage converters ( 200 ) according to an aspect of the invention, in which at least a sample of the regulated output voltage (V o ) is provided to a first input port ( 121 ) of a feedback network ( 120 ,  125 ) and a reference voltage (V ref ) is applied to a second (+) input port ( 122 ) of the feedback network ( 120 ,  125 ). The feedback network ( 120 ,  125 ) produces an error signal (V e ) for application to a pulse width modulator ( 110 ). The improvement comprises a second circuit ( 250 ) responsive to the error signal (V e ) and to a second reference voltage (V m ), for providing a further signal (V o2 ) to the first input port ( 121 ) of the feedback network ( 120 ,  125 ) when the error signal (V e ) exceeds the second reference voltage (V m ), for tending to limit the error signal (V e ). In this aspect, a preferred embodiment includes an arrangement (D 1 ) for isolating an output of the second circuit ( 215 ) from the first input ( 121 ). The second circuit ( 215 ) may include a comparator or a linear amplifier. In a more preferred embodiment, the second circuit ( 215 ) includes a comparator or a linear amplifier having a first input (+) and a second (−) input. The second reference voltage (V m ) may be variable. An arrangement ( 250 ) may be provided for monitoring or making available the output of the second circuit ( 215 ). 
   A method according to an avatar of the invention is for providing dynamic clamping regulation in PWM regulated DC/DC converters. The method comprises the step of providing an error signal (V e ) to a first input ( 121 ) of a comparator ( 120 ) through a first feedback circuit ( 125 ). At least a sample of a DC voltage (V o ) to be regulated is applied to the first input ( 121 ) and a reference voltage (V ref ) is applied to a second input ( 122 ) of the comparator ( 120 ). A signal (V o2 ) responsive to the error signal (V e ) is independently provided to the first input ( 121 ) by way of a second feedback circuit ( 210 ) when the error signal (V e ) is greater than a second reference voltage (V m ). In this avatar, the independently provided signal (V o2 ) may be isolated from the first input ( 121 ) during those times in which the error signal (V e ) is not greater than the second reference voltage (V m ). The second reference voltage may be variable andor varied. 
   In another hypostasis of the invention, a device provides dynamic clamping regulation in a PWM regulated DC/DC converter. The device comprises a first feedback circuit ( 125 ) operable to provide a signal (V o2 ) responsive to an output voltage (V e ) of a first comparator ( 120 ) to a first input ( 121 ) of the first comparator ( 120 ). In this hypostasis, at least a sample of a DC voltage (V o ) to be regulated is also applied to the first input ( 121 ) and a reference voltage (V ref ) is applied to a second input ( 122 ) of the first comparator ( 120 ). A second feedback circuit ( 210 ) is operable when the output voltage (V e ) of the first comparator ( 120 ) is greater than a second reference voltage (V m ) to independently provide to the first input port ( 121 ) of the first comparator ( 120 ) a signal responsive to a difference between the second reference voltage (V m ) and the output voltage (V e ) of the first comparator ( 120 ). In a preferred version of this hypostasis, the device includes an arrangement (D 1 ) for isolating the second feedback circuit ( 210 ) output (V o2 ) from the first input ( 121 ) of the comparator ( 210 ). The preferred version of the device also includes a second circuit ( 215 ) having a first input (+) and a second input (−) operable to generate an output when the output voltage (V e ) of the first comparator ( 120 ) is greater than a second reference voltage (V m ) applied to the second input (−). The second circuit may be selected from the group consisting of (a) linear amplifier and (b) comparator. Means may be provided for monitoring or making available the output signal (V o2 ) of the second circuit. In one version of this hypostasis, the second reference voltage (V m ) may be varied. 
   An avatar of the invention is for providing dynamic clamping voltage regulation. This avatar includes a first feedback circuit ( 120 ,  125 ) operable to couple or provide a first comparator ( 120 ) output (V e ) to a first input ( 121 ) of the comparator ( 120 ). A voltage (V o ) to be regulated is concurrently applied to the first input ( 121 ) and a reference voltage (V ref ) is applied to a second input ( 122 ). A second feedback circuit ( 210 ) is operable to independently provide to the first input ( 121 ) a signal (V o2 ) responsive to the first comparator ( 120 ) output (V e ) when the first comparator ( 120 ) output (V e ) is greater than a second reference voltage (V m ). This avatar may include means for isolating the second feedback circuit output from the first input. The second feedback circuit ( 210 ) may include a circuit ( 215 ) having a first input (+) and a second input (−) operable to generate an output signal (V o2 ) when the first comparator ( 120 ) output (V err ) is greater than a second reference voltage (V m ) applied to the second input (−) of the circuit ( 215 ). The circuit ( 215 ) may be selected from the group consisting of (a) linear amplifier and (b) comparator. This avatar may include means for monitoring or making available the output signal (V o2 ) of the circuit ( 215 ). The second reference voltage (V m ) may be varied. The voltage to be regulated may be the output of a DC/DC converter.