Abstract:
A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Description:
FIELD OF THE INVENTION  
       [0001]    The present invention relates to error-and-erasure decoders generally and, more particularly, to a scheme for erasure locator polynomial calculation in an error-and-erasure decoder. 
       BACKGROUND OF THE INVENTION  
       [0002]    Reed-Solomon (RS) codes are a powerful class of multiple error-correcting codes. RS codes have a wide range of applications, such as optical communications, wireless communications and magnetic recording systems. When applying systematic Reed-Solomon encoding, data is transmitted in codewords that represent a combination of the original data symbols and a number of parity symbols. An RS code that uses 2t parity symbols is commonly correctable to t errors. An RS decoder uses the 2t parity symbols to correct a received message, even if the received message experiences up to t errors during transmission. 
         [0003]    In many modern communication systems, RS decoders use extra information along with the received data. A reliability value is calculated for each received data symbol. Received data symbols with very small reliability are called erasures. If a particular data symbol in a received codeword is known to be an erasure, a value of the particular symbol is ignored when the RS decoder attempts to decode the codeword. If ν errors and ρ erasures occur during transmission of a codeword, the codeword can be corrected if and only if ν+ρ≦2t. RS decoders that use information about erasures are called error-and-erasure decoders. The error-and-erasure decoding techniques involve the construction of erasure locator polynomials. The erasure locator polynomials accumulate information about all of the erasures for use in the decoding process. 
       SUMMARY OF THE INVENTION  
       [0004]    The present invention concerns a method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing a plurality of current values in a plurality of registers at a current one of a plurality of moments, (B) generating a plurality of first values by multiplying each one of the current values by a respective one of a plurality of constants, (C) generating a plurality of second values by gating at least all but one of the first values with a current one of plurality of erasure values of an erasure position vector, (D) generating a plurality of next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next one of the moments and (F) generating an output signal carrying the current values at a last of the moments such that the current values form a plurality of coefficients of the erasure locator polynomial. 
         [0005]    The objects, features and advantages of the present invention include providing a method and/or apparatus implementing a scheme for erasure locator polynomial calculation in an error-and-erasure decoder that may (i) provide space-efficient implementations, (ii) use constant Galois field multipliers and/or (iii) have a smaller timing delay than conventional implementations. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0006]    These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
           [0007]      FIG. 1  is a first set of formulae; 
           [0008]      FIG. 2  is a functional flow diagram of a system in accordance with a preferred embodiment of the present invention; 
           [0009]      FIG. 3  is a detailed functional flow diagram of a first example embodiment of a reconstruction circuit; 
           [0010]      FIG. 4  is a detailed functional flow diagram of a second example embodiment of the reconstruction circuit; 
           [0011]      FIG. 5  is a second set of formulae; 
           [0012]      FIG. 6  is a block diagram of a first example embodiment of an erasure polynomial calculator using constant Galois field multipliers; and 
           [0013]      FIG. 7  is a block diagram of a second example embodiment of the erasure polynomial calculator. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0014]    The present invention generally concerns a method and hardware scheme for calculating an erasure locator polynomial. Let F q  be a finite field with q=2 d  elements and primitive element αεF q . Let RS(n,k,t) be a primitive Reed-Solomon code over F q  with n=q−1 representing a code length, k representing a number of information symbols and t representing a number of errors. Consider a vector v=(v 0 , . . . ,v n−1 )εF q   n  identified with a polynomial v(x)=v 0 +v 1 x+ . . . +v n−1 x n−1  εF q [x]. By the definition of Reed-Solomon codes, a codeword c(x)=c 0 +c 1 x+ . . . +c n−1 x n−1 εRS(n,k,t) if any only if c(α 1 )=c(α 2 )= . . . =c(α 2t )=0. 
         [0015]    Referring to  FIG. 1 , a first set of formulae is shown. The original codeword (polynomial) c(x)εRS(n,k,t) may be sent through a channel that may induce ν errors and ρ erasures, where 2ν+ρ≦2t. Therefore, a receiving end of the channel may generate the received codeword (polynomial) v(x)=c(x)+e(x), where e(x) is an errata polynomial. The errata polynomial e(x) is generally defined by formula (1), as shown in  FIG. 1 . 
         [0016]    The received codeword v(x) may have a set of ν error positions (e.g., I={i 1 , . . . ,i ν }) that may be unknown at the time of reception. The received codeword v(x) may also have a set of ρ erasure positions (e.g., J={j 1 , . . . ,j ρ }) that may be determined ahead of the decoding by the receiver circuitry due to the low reliability of some of the received symbols. An error-and-erasure decoding generally calculates the erasure polynomial e(x) and thus may reconstruct the original codeword as c(x)=v(x)−e(x). In order to determine the set of error positions I, two polynomials may be introduces per the formulae (2) and (3), as shown in  FIG. 1 . The polynomial Λ(x) may be referred to as an error locator polynomial. The polynomial Ψ(x) may be referred to as an erasure locator polynomial. 
         [0017]    Note 1: a set {0,1, . . . ,n−1} is generally denoted as [0,n). Furthermore, if iε[0,n), then (i) Λ(α −i )=0 if and only if iεI and (ii) Ψ(α −j )=0 if any only if jεJ. 
         [0018]    A discrete Fourier transform F n :F q   n →F q   n  generally maps each vector u=(u 0 , . . . ,u n−1 ) into a vector U=(U 0 , . . . ,U n−1 ) per formula (4), shown in  FIG. 1 . The map F n :F q   n →F q   n  is commonly a bijection (a transform which is one-to-one and a surjection) and the inverse discrete Fourier transform u=F n   −1 (U) may be obtained by formula (5), shown in  FIG. 1 . The fact that U=F n (u) and u=F n   −1 (U) is generally denoted by u         U. The maps F n  and F n   −1  are commonly linear maps. For example, from u         U and w         W, then au+bw         aU+bW generally follows for any a,bεF q . 
         [0019]    Note 2: for two given vectors u,wεF n   q , (i) the vector u·wεF n   q , where (u·w) i =u i w i , i=0, . . . ,n−1, (ii) F n (u·w)=U*W, where U=F n (u), W=F n (w) and (iii) U*W may be a convolution, see formula (6) in  FIG. 1 . Hence, from u         U and w         W, then u·w         U*W generally follows. 
         [0020]    Let c         C, e         E, λ         Λ, and ψ         Ψ. From note 1, (i) λ i =Λ(α −i )=0 generally follows if and only if iεI and (ii) ψ j =Ψ(α −j )=0 if and only if jεJ. Furthermore, if e i ≠0, then iεIÅJ. Therefore, e·ψ·λ=0, and also by note 2, E*Ψ*Λ=0, where 0=(0, . . . ,0)εF q   n . The whole vector E may be unknown, but the 2t components may be obtained. By calculating syndromes S i =v(α i )=V i =C i +E i  for i=1, . . . ,2t, and using the fact that C i =c(α i )=0 for i=1, . . . ,2t, then E 1 =S 1 , . . . ,E 2t =S 2t . Thus, 2t subsequent elements of vector E may be known. By the fact that degΨ(x)=ρ≦2t, the 2t−ρ subsequent elements of a vector E*Ψ may be calculated per formula (7), shown in  FIG. 1 . 
         [0021]    Elements S′ 1 =(E*Ψ) ρ+1 , . . . ,S′ 2t−ρ =(E*Ψ) 2t  are commonly known as Forney modified syndromes. By the fact that degΛ(x)≦(2t−ρ)/2 and the relationship (E*Ψ)*Λ=0, the condition in formula (8) may be true, see  FIG. 1 . Hence, a custom Berlekamp-Massey technique may be used to find the error locator polynomial Λ(x) using Forney modified syndromes S 1 ′, . . . ,S′ 2t−ρ  instead of ordinary syndromes S 1 , . . . ,S 2t . 
         [0022]    Once the error locator polynomial Λ(x) and the erasure locator polynomial Ψ(x) are known, a set of error and erasure positions may be found using exhaustive search called a Chien search, I={iε[0,n)|Λ(α −i )=0} and J={iε[0,n)|Λ(α −i )=0}. To reconstruct the errata polynomial e(x), the error and erasure values e i1 , . . . ,e iν  and e j1 , . . . ,e jρ  may be sought. 
         [0023]    Referring to  FIG. 2 , a functional flow diagram of a system  100  is shown in accordance with a preferred embodiment of the present invention. The system (or apparatus)  100  generally implements an error-and-erasure decoder. In some embodiments, the system  100  may implement a Reed-Solomon decoder. The system  100  generally comprises a circuit (or step)  102 , a circuit (or step)  104 , a circuit (or step)  106 , a circuit (or step)  108  and a circuit (or step)  110 . A signal (e.g., IS_ERASURE) may be generated by the circuit  102  and transferred to the circuit  104 . A signal (e.g., CHANNEL) may be received by the circuit  102 . A signal (e.g., INPUT) may be generated by the circuit  102  and presented to the circuit  104 , the circuit  106  and the circuit  108 . The circuit  110  may generate and present an output signal (e.g., OUTPUT). A signal (e.g., ELP) may be generated by the circuit  104  and presented to the circuit  110 . A signal (e.g., SYN) may be generated by the circuit  106  and presented to the circuit  110 . The circuit  108  may generate a signal (e.g., DELAY) presented from the circuit  108  to the circuit  110 . 
         [0024]    The signal IS_ERASURE generally carries an erasure location vector (e.g., θ). The vector θ=(θ 0 ,θ 1 , . . . ,θ n−1 )ε{0,1} n  generally comprises a sequence of binary elements containing information about erasures, where θ j =1 indicates an erasure at position jε[0,n). A set all erasure positions {jε[0,n)|θ j =1} may be denoted by [θ]. The signal INPUT may convey a received codeword (or vector) v=(v 0 ,v 1 , . . . ,v n−1 ). The received codeword v(x) may have been encoded per the Reed-Solomon coding and transmitted through a noisy signal CHANNEL to the circuit  102 . The signal ELP may carry an erasure locator polynomial (e.g., Ψ(x)). The signal SYN may carry syndromes (e.g., S(x)). The signal DELAY may carry a delayed copy (e.g., v2) of the codewords v(x). The signal OUTPUT may convey the reconstructed codeword (or vector) c(x). 
         [0025]    The circuit  102  generally implements a receiver. The circuit  102  may be operational to covert a sequence of symbols receive through the signal CHANNEL into the signal IS_ERASURE and the signal INPUT. Generation of the signals IS_ERASURE and INPUT may be performed by common techniques. 
         [0026]    The circuit  104  may implement an erasure polynomial calculator. The circuit  104  is generally operational to calculate the polynomial Ψ(x) based on the vector θ and the codeword v(x). A design of the circuit  104  may utilize constant Galois multipliers to aid in minimizing the circuit size (e.g., number of transistors) and maximize the circuit speed (e.g., reduce propagation delay). 
         [0027]    The circuit  106  may implement a syndrome calculator. The circuit  106  is generally operational to calculate the syndromes S(x) from the codeword v(x). The syndrome calculations may be performed by common techniques. 
         [0028]    The circuit  108  may implement a buffer. The circuit  108  may hold the codeword v(x) until the circuit  110  is ready to generate the reconstructed codeword c(x). A delay through the circuit  108  may be based on the delays through the circuits  104  and  106  plus a partial delay through the circuit  110 . 
         [0029]    The circuit  110  may implement a reconstruction circuit. The circuit  110  may be operational to generate the reconstructed codeword C using the polynomial Ψ(x) the syndromes S(x) and the delayed codewords v2(x). 
         [0030]    Referring to  FIG. 3 , a detailed functional flow diagram of a first example embodiment  110   a  of the circuit  110  is shown. The circuit  110   a  generally comprises a circuit (or step)  112 , a circuit (or step)  114  and a circuit (or step)  116 . The polynomial Ψ(x) and the syndromes S(x) may be received by the circuit  112 . A signal (e.g., ERR) may be generated by the circuit  112  and presented to the circuit  114 . The circuit  112  may also generate a signal (e.g., EEP) presented to the circuit  114 . A signal (e.g., ERRATA) may be generated by the circuit  114  and presented to the circuit  116 . The circuit  116  may receive the signal ERRATA and the signal DELAY. The signal OUTPUT may be generated by the circuit  116 . 
         [0031]    The circuit  112  generally implements a calculation circuit. The circuit  112  may be operational to (i) calculate modified syndromes, (ii) generate the signal ERR using the Berlekamp-Massey technique and (iii) generate the signal EEP. 
         [0032]    The circuit  114  generally implements a calculation circuit. The circuit  114  may be operational to (i) determine the error positions by the Chien search and (ii) determine the error and erasure values using the Forney technique. The results may be presented in the signal ERRATA. 
         [0033]    The circuit  116  may implement a summation circuit. The circuit  116  is generally operational to create the codeword c(x) in the signal OUTPUT by summing the signal ERRATA and the signal DELAY. 
         [0034]    In operation, the system  100  may calculate the syndromes S(x) in the circuit  106  in accordance with formula (9), shown in  FIG. 1 . The circuit  104  may calculate the erasure locator polynomial Ψ(x) in accordance with formula (10), shown in  FIG. 1 . The circuit  108  generally calculates the modified Forney syndromes (e.g., S′(x)) per the formula (11), see  FIG. 1 . 
         [0035]    The circuit  112  may determine the error locator polynomial Λ(x) using the Berlekamp-Massey technique on the modified syndromes S 1 ′, . . . ,S′ 2t−ρ . The errata evaluator polynomial Ω(x) may be determined by the circuit  112  according to formula (12), where S(x) is a syndrome polynomial in accordance with formula (13), see  FIG. 1 . The circuit  114  may find the error positions I={iε[0,n)|Λ(α −i )=0} by a Chien search. The error and erasure values may be determined by the circuit  114  using the Forney formulae (14) and (15), as shown in  FIG. 1 . Finally, the circuit  116  may calculate the reconstructed codeword c(x)=v(x)+e(x) and present the codeword c(x) in the signal OUTPUT. 
         [0036]    Referring to  FIG. 4 , a detailed functional flow diagram of a second example embodiment  110   b  of the circuit  110  is shown. The circuit  110   b  generally comprises a circuit (or step)  122 , the circuit  114  and the circuit  116 . The polynomial Ψ(x) and the syndromes S(x) may be received by the circuit  122 . The signal ERR may be generated by the circuit  122  and presented to the circuit  114 . The circuit  122  may also generate the signal EEP that is presented to the circuit  114 . The signal ERRATA may be generated by the circuit  114  and presented to the circuit  116 . The circuit  116  may receive the signal ERRATA and the signal DELAY. The signal OUTPUT may be generated by the circuit  116 . 
         [0037]    The circuit  122  may implement a Euclidian circuit. The circuit  122  is generally operational to calculate the signal ERRATA based on the signal ERR and the signal EEP using the extended Euclidian technique. The remaining circuits  114  and  116  may operate as described above. 
         [0038]    Referring again to  FIG. 2 , the system generally receives (i) the input codeword v=(v 0 ,v 1 , . . . ,v n−1 ) and (ii) the erasure location vector θ=(θ 0 ,θ 1 , . . . ,θ n−1 )ε{0,1} n  and generates the reconstructed codeword c=(c 0 ,c 1 , . . . ,c n−1 ). 
         [0039]    A custom solution for calculating the erasure polynomial Ψ(x) for the vector θ may be in accordance with formula (16), shown in  FIG. 5 . A hardware scheme for calculating Ψ(x) “on the fly” (e.g., updating the polynomial Ψ(x) as each new element of the vector θ is received) may be implemented in the circuit  104 . The circuit  114  may (i) update the polynomial Ψ(x) as new erasures occur and (ii) be implemented using only constant Galois field multipliers. Implementations of constant Galois field multipliers are generally more space efficient on the chips than implementation of non-constant Galois field multipliers. In particular, constant Galois field multipliers may have approximately ten times fewer gates than non-constant Galois field multipliers. Hence, constant multiplier applications may have less complexity, occupy less area and consume less power than a design that uses non-constant multipliers. For implementations of multipliers for Galois field having a large number of elements (e.g., 2 12  elements), the advantages of using constant multipliers may be considerable. 
         [0040]    Referring to  FIG. 6 , a block diagram of a first example embodiment  104   a  of the circuit  104  using constant Galois field multipliers is shown. The circuit  104   a  generally comprises multiple registers (or modules)  140   a - 140   n,  several multipliers (or modules)  142   a - 142   n,  multiple gating circuits (or modules)  144   a - 144   n,  multiple summation circuits (or modules)  146   a - 146   n  and multiple gating circuits (or modules)  148   a - 148   n.  The signal IS_ERASURE may be received by each of the circuits  148   a - 148   n.  A signal (e.g., WORK) may be received by each of the circuits  144   a - 144   n.  Each of the registers  140   a - 140   n  may generate a portion of the signal ELP (e.g., Ψ 0 , Ψ 1 , . . . ,Ψ 2t ). The first circuit  146   a  may (i) receive a first input from the circuit  144   a  and (ii) a constant value (e.g., 0) as a second input. 
         [0041]    The circuit  104   a  generally contains 2t+1 registers  140   a - 140   n,  labeled R 0 ,R 1 , . . . ,R 2t  and may work as follows. Consider a moment kε{0, . . . ,n−1} when the registers  140   a - 140   n  already buffer bits θ n−1 ,θ n−2 , . . . ,θ n−k  for kε{1, . . . ,n−1} and the vector θ (k) =(θ n−k ,θ n−k+1 , . . . ,θ n−1 , 0, . . . ,0)ε{0,1} n , where θ (0) =(0, . . . ,0)ε{0,1} n . The scheme generally works so that at the moment k, the register R i  may hold a current value of Ψ i   (k) , for i=0,1, . . . ,2t, where Ψ(x) may be defined by formula (17), shown in  FIG. 5 . Therefore, the registers  140   a - 140   n  may completely define the polynomial Ψ (k) (x) at the moment k. At a final moment (e.g., k=n) when all of the elements of the vectors θ and v have been entered into the circuit  104   a,  the registers  140   a - 140   n  generally contain the coefficients Ψ 0 ,Ψ 1 , . . . ,Ψ 2t  of erasure locator polynomial Ψ(x) because θ (n) =θ and therefore Ψ (n) (x)=Ψ(x). Furthermore, R 0 =Ψ 0   (k) =1 for any k=0,1, . . . ,n−1. Hence, R 0  may be a constant (e.g., 1εF q ). 
         [0042]    At an initial moment (e.g., k=0), the signal IS_ERASURE may be set to a binary zero value (0) and the signal WORK may be deasserted to the binary zero value. Therefore, the initial values in the registers  140   a - 140   n  may be R 0 :=1,R 1 :=0, . . . ,R 2t :=0. The initial values generally correspond to the polynomial Ψ (0) (x)=1. After the initial moment, the signal WORK may be asserted to a binary one value (1) and the signal IS_ERASURE may be set to θ n−k  at each moment n≧k&gt;0. Thus, at the moment k, the registers  140   a - 140   n  may contain Ψ 0   (k) ,Ψ 1   (k) , . . . ,Ψ 2t   (k) . 
         [0043]    Each of the registers  140   a - 140   n  may present the buffered current values to the corresponding multipliers  142   a - 142   n.  Each of the multipliers  142   a - 142   n  may perform a unique (e.g., α 0 ,α 1 , . . . ,α 2t ) constant Galois field multiplication to generate first intermediate values. The first intermediate values may be received by the corresponding modules  144   a - 144   n  and  148   a - 148   n.  Once the signal WORK has been asserted, the modules  144   a - 144   n  may pass the first intermediate values unaltered to the circuit  146   a - 146   n,  respectively. The circuits  148   a - 148   n  may selectively gate the first intermediate values with the signal IS_ERASURE to generate second intermediate values. The second intermediate values may provide a second input to the circuits  146   b - 146   n.    
         [0044]    Each of the circuits  142   a - 142  generally has a single input X=(X 1 , . . . ,X d ) and a single output Y=(Y 1 , . . . ,Y d ). Each α i  for i=0, . . . ,2t, may be a constant Galois field multiplier, where α is known Galois field element. The output may be related to the input by Y=α*X in the Galois field. 
         [0045]    Each of the circuits  144   a - 144   n  and  148   a  generally has two inputs. A first input may be a 1-bit input (e.g., W) connected to the signal IS_ERASURE or the signal WORK. A second input may be a d-bit input connected to an output signal (e.g., X=(X 1 , . . . ,X d )), where d is generally the width of the Galois field (e.g., the Galois field may have 2 d  elements). Each of the circuits  144   a - 144   n  and  148   a - 148   n  may generate a single d-bit output (e.g., Z=(Z 1 , . . . ,Z d )). A function of the circuits  144   a - 144   n  and  148   a - 148   n  may be expressed as Z 1 =W AND X 1 , Z 2 =W AND X 2 , . . . , Z d =W AND X d . 
         [0046]    Each of the circuits  146   a - 146   n  generally has two inputs. Each Galois field element aεFq, where q=2 d , may be represented as binary vector (e.g., a 1 ,a 2 , . . . ,a d ). Likewise, another Galois field element bεFq may be represented as (b 1 ,b 2 , . . . ,b d ). The circuits  146   a - 146  generally calculates the sum a+b in the Galois field arithmetic as another Galois field element represented as (a 1  XOR b 1 , . . . , a d  XOR b d ). 
         [0047]    Consider the following two cases to prove that at the moment k+1 the registers  140   a - 140   n  may contain Ψ 0   (k+1) ,Ψ 1   (k+1) , . . . ,Ψ 2t   (k+1) . In a first case, let no erasure exist at the position k+1, (e.g., θ n+k−1 =0). Therefore, θ (k+1) =(0,θ n−k ,θ n−k+1 , . . . ,θ n−1 ,0, . . . ,0). As such, the vector θ (k+1)  is generally a “right shift” of the vector θ (k)  and the polynomial Ψ (k+1) (x) may be defined by formula (18), shown in  FIG. 5 . In the first case, R i :=R i α i  for i=1, . . . ,2t. 
         [0048]    In a second case, let an erasure exist at the position k+1, (e.g., θ n+k−1 =1). Therefore, θ (k+1) =(1,θ n−k ,θ n−k+1 , . . . ,θ n−1 ,0, . . . ,0) and the polynomial Ψ (k+1) (x) may be defined by formula (19), shown in  FIG. 5 . In the second case, R i :=R i−1 α i−1 +R i α i  for i=1, . . . ,2t. 
         [0049]    Referring to  FIG. 7 , a block diagram of a second example embodiment  104   b  of the circuit  104  is shown. The circuit  104   b  may be similar to the circuit  104   a  with a few modifications. Consider that the register  140   a  stores a constant value (e.g., 1) and the circuit  142   a  is a multiplication by one (e.g., α 0 =1). Therefore, the circuits  142   a,    144   a  and  146   a  may be eliminated in the circuit  104   b  and the current value of the register  140   a  may be presented directly to the input of the circuit  148   a.  Furthermore, a last of the circuits  148   n  may be eliminated as the corresponding signal generally does not feed into a next summation module. With the eliminations, the circuit  104   b  generally operates the same as the circuit  104   a  (and the circuit  104 ). 
         [0050]    The functions performed by the diagrams of  FIGS. 1-7  may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). 
         [0051]    The present invention may also be implemented by the preparation of ASICs, FPGAs, or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
         [0052]    The present invention thus may also include a computer product which may be a storage medium including instructions which can be used to program a computer to perform a process in accordance with the present invention. The storage medium can include, but is not limited to, any type of disk including floppy disk, optical disk, CD-ROM, magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions. 
         [0053]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.