Abstract:
An apparatus for receiving a microchip and having a conductor buses therein. A top surface of the apparatus receives the microchip while the bottom surface is to mount to a circuit board. A plurality of pin receptacles pass through the top surface to receive a corresponding plurality of microchip pins of the microchip. The conductor bus resides at least in part between the top surface and the bottom surface and is electrically coupled to a first plurality of the plurality of the pin receptacles.

Description:
TECHNICAL FIELD 
   This disclosure relates generally to array sockets for coupling to microchips and in particular but not exclusively, relates to providing a dedicated power/ground conductor bus within the array socket. 
   BACKGROUND INFORMATION 
   Array sockets are widely used to seat a microchip on a circuit board so that the microchip may be replaced or upgraded to improve performance at a later date. Typical microchips include, but are not limited to, memory modules, microprocessors, and BIOS chips. 
     FIG. 1  is a cross-sectional view of an exemplary array socket system  100  including a microchip  120  having microchip pins  125  seated in corresponding pin receptacles (not shown) of an array socket  110 . Array socket  110  includes a plurality of socket pins  145  that are electrically coupled within array socket  110  to the corresponding pin receptacles. Socket pins  145  are electrically connected to conductor traces  230  ( FIG. 2 ) such that signals and/or power may be delivered to/from microchip  120  from other components on circuit board  140 . 
     FIG. 2  is a view of a bottom side of circuit board  140  illustrating a plurality of pads  210 , which electrically couple to corresponding socket pins  145 . Conductor traces  230  form electrical contact with corresponding pads  210  and run outwards from pads  210  to various other electronic components mounted on or coupled to circuit board  140 . Conductor traces  230  making contact with inner pads  210  must run between outer pads  210 . As can be seen from  FIG. 2 , routing conductor traces  230  away from pads  210  can consume a large area on circuit board  140 . As the number of microchip pins  120  increases, the number of pads  210  and conductor traces  230  increases. Thus, in complex microchips, finding a workable routing scheme becomes a complex task. 
   Furthermore, as microchips become faster, more powerful, and generally speaking more complicated, they demand increasing amounts of power and I/O paths. One solution has been to increase the number of microchip pins  120  to service the increasing number of I/O paths. Generally speaking, as the number of microchip pins  125  increases, the package I/O pitch P ( FIGS. 3 and 4 ) between neighboring microchip pins  125  has continued to shrink to accommodate the added microchip pins  120  and corresponding conductor traces  230 . 
     FIG. 3  illustrates a cross-sectional view taken at line A-A′ in  FIG. 2 , and  FIG. 4  is an expanded view of an area B in FIG.  2 . Vias  310  are created in circuit board  140  to allow socket pins  145  to pass through to the under side of circuit board  140 . In a four-layer circuit board, there typically is a ground conductor layer  320 A and a power conductor layer  320 B. When via  310  is created in circuit board  140 , an anti-pad  410  is created by etching back the copper of ground conductor layer  320 A and power conductor layer  320 B. Anti-pad  410  ensures that a short circuit does not occur between pad  210  and either one of ground conductor layer  320 A or power conductor layer  320 B. Consequently, conductor traces  230  are limited in width W by the distance between neighboring anti-pads  410 . 
   Thus, as the trend continues towards tighter package I/O pitches P, width W of conductor traces  230  servicing pads  210  must also shrink. Currently, width W is 1.27 mm, but designs are in the works for package I/O pitches P ranging from 1 mm to as low as 0.4 mm. A step down to a package I/O pitch P of 1 mm results in a loss of approximately 21% in width W. As width W decreases the copper to delivery power to microchip  120  decreases. Reduced width W of conductor traces  230  results in a higher linear resistance and increased power loss and heat dissipation in conductor traces  230 . The current trend of tighter I/O package pitches P is cornering chip designers into a two-fold problem-reduced power delivery capacity and increased power supply demand. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
       FIG. 1  is a cross-sectional view of a known array socket system. 
       FIG. 2  illustrates an area of a bottom side of a known circuit board, above which an array socket may be mounted. 
       FIG. 3  is a cross-sectional view taken along line A-′ of the known circuit board in FIG.  2 . 
       FIG. 4  is an expanded view of an area B of the bottom side of the known circuit board illustrated in FIG.  2 . 
       FIG. 5  illustrates an embodiment of an array socket system having a conductor bus, in accordance with the teachings of the present invention. 
       FIG. 6  illustrates a top view of an embodiment of an array socket and a conductor bus interface, in accordance with the teachings of the present invention. 
       FIG. 7  illustrates an embodiment of a power/ground coupler for coupling to an array socket having conductor buses therein, in accordance with the teachings of the present invention. 
       FIG. 8  illustrates an embodiment of a conductor bus interface of an array socket having conductor buses therein, in accordance with the teachings of the present invention. 
       FIG. 9  illustrates an embodiment of an array socket having multiple conductor bus interfaces for connecting to multiple conductor buses, in accordance with the teachings of the present invention. 
       FIG. 10  illustrates a suitable computer system for using embodiments of an array socket having a conductor bus, in accordance with the teachings of the present invention. 
   

   DETAILED DESCRIPTION 
   Embodiments of a method and apparatus for implementing an array socket having a conductor bus are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. 
   Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. 
   Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. “Microchip” is defined to mean any integrated circuit device having more than one input/output (“I/O”) port (e.g., pin). 
     FIG. 5  illustrates an array socket system  500 , according to an embodiment of the present invention. In this embodiment, array socket system  500  includes a circuit board  502 , an array socket  510  having a conductor bus  512 , a microchip  520  having microchip pins  522 , a heat sink  504 , a conductor bus interface  800 , and a power/ground coupler  700 . Power/ground coupler  700  includes an interface adapter  730 , a conductor bridge  740 , and a power/ground interface  750  electrically coupled to ground reference conductor  562  and power supply conductor  564 . 
   The elements of array socket system  500  are interconnected as follows. In one embodiment, array socket  510  is mounted on circuit board  502  using socket conductors  514 . In some cases, socket conductors  514  may pass through vias (e.g., vias  310 ) in circuit board  502  to make electrical contact with either internal conducting layers (e.g., ground conductor layer  320 A or power conductor layer  320 B in  FIG. 3 ) or with conductor traces on a bottom side of circuit board  502 . In other cases, socket conductors make electrical contact with conductor traces on a top surface of circuit board  502  (not shown). In one embodiment, socket conductors  514  are pins protruding from a bottom side of array socket  510 . In an alternative embodiment, socket conductors  514  represent solder balls for electrically bonding contact pads on a bottom surface of array socket  510  to contact pads on the top surface of circuit board  502  and conductive vias for making electrical contact with the internal conductive layers or conductor traces (e.g., conductor traces  230 ) on the bottom side of circuit board  502 . A region of circuit board  502  where socket conductors  514  penetrate or make contact with circuit board  502  is called a pin field  570  or a ball field  570 , depending on whether pins or solder balls are used to make electrical contact. 
   In one embodiment, socket conductors  514  are electrically coupled to pin receptacles  610 A (FIG.  6 ). Pin receptacles  610 A and  610 B together receive and make electrical contact with microchip pins  522  when microchip  520  is seated in array socket  510 , as illustrated. In one embodiment, heat sink  504  is thermally bonded to a top surface of microchip  520  to dissipate excess heat generated during operation of microchip  520 . It should be appreciated that heat sink  504  may not be necessary for various types of microchips  520  used in connection with the present invention. 
     FIG. 6  illustrates a top view of array socket  510  and conductor bus interface  800  without microchip  520  seated thereon, according to an embodiment of the present invention. Conductor buses  512  are electrically coupled within array socket  510  to pin receptacles  610 B. Pin receptacles  610 A, are those pin receptacles that do not make electrical contact with conductor buses  512 . In one embodiment, pin receptacles  610 A are electrically coupled to conductor traces on or within circuit board  502  via corresponding socket conductors  514 . In one embodiment, pin receptacles  610 A deliver I/O signals (e.g., data signals, control signals, addressing signals, and the like) between microchip  520  and various other components mounted on or communicatively coupled to circuit board  502 . 
   Pin receptacles  610 B are those pin receptacles that are coupled to one of conductor buses  512 . In one embodiment, one or more conductor buses  512  deliver a power supply voltage or a power supply current to microchip  520 . In one embodiment, one or more conductor buses  512  deliver a ground reference voltage to microchip  520 . 
   In the illustrated embodiment, conductor buses  512  are housed entirely within array socket  510 . In this embodiment, conductor buses  512  run between pin receptacles  610 A and  610 B. Thus, conductor buses  512  have a width that is less than the pitch of pin receptacles  610 A and  610 B. However, a thickness of conductor buses  512  along the z-axis may vary depending upon design needs. Generally, it will be desirable to minimize the linear resistance of conductor buses  512 . To minimize linear resistance, the thickness of conductor buses  512  may be maximized within array socket  510 . Furthermore, the thickness H of array socket  510  may be varied to provide greater z-axis thickness for conductor buses  512 . 
   In one embodiment, one or more conductor buses  512  protrude above and/or below array socket  510 . In this case, either array socket  510  is raised above circuit board  502  or an insulating surface is wrapped around the protruding portions of conductor buses  512  so as to prevent an electrical short with conductor traces on the top surface of circuit board  502 . 
   Conductor buses  512  can be made of any conductive material, such as copper. Conductor buses  512  may be formed inside array socket  510  by way of insert molding or other know fabrication techniques. 
   A locking mechanism  620  is included in the illustrated embodiment of array socket  510 . When microchip  522  is seated in array socket  510 , microchip pins  520  are inserted into corresponding pin receptacles  610 A and  610 B. By rotating locking mechanism  620  such that its body is substantially parallel with array socket  510 , microchip pins  522  are both mechanically and electrically secured to pin receptacles  610 A and  610 B. It should be appreciated that various other known methods of locking microchip  520  to array socket  510  fall within the scope of the present invention. 
   Conductor bus interface  800  provides both electrical contact between conductor buses  512  and power/ground coupler  700  and it mechanically attaches one end of power/ground coupler  700  to array socket  510 .  FIG. 7  illustrates power/ground coupler  700 , in accordance with an embodiment of the present invention. This embodiment of power/ground coupler  700  includes an interface adapter  730  having adapter pins  710 A,  710 B,  710 C, and  710 D, conductor bridge  740  having conductor lines  720 A,  720 B,  720 C, and  720 D, and power/ground interface  750 . Adapter pins  710 A,  710 B,  710 C, and  710 D are electrically coupled to conductor lines  720 A,  720 B,  720 C, and  720 D, respectively. Conductor lines  720 A,  720 B,  720 C, and  720 D are each electrically coupled to ground reference conductor  562  and/or power supply conductor  564  via power/ground interface  750 . The combinations of couplings between conductor lines  720 A,  720 B,  720 C, and  720 D and ground reference conductor  562  and power supply conductor  564  can vary dependent upon power and ground needs of microchip  520 . 
   In one embodiment, conductor bridge  740  is fabricated from ridged materials, such as conductive plastic, printed circuit board having conductor traces thereon, or the like. In one embodiment, conductor bridge  740  is fabricated from flexible materials, such as flex circuit, ribbon cables, or the like. Furthermore, the length of conductor bridge  740  can vary dependent upon the distance between array socket  510  and ground reference conductor  562  and/or power supply conductor  564 . 
     FIG. 8  illustrates a top view of conductor bus interface  800 , in accordance with an embodiment of the present invention. This embodiment includes adapter pin receptacles  810 A,  810 B,  810 C, and  810 D. Adapter pin receptacles  810 A,  810 B,  810 C, and  810 D are electrically coupled to conductor buses  512 . When interface adapter  730  is connected to conductor bus interface  800 , adapter pin receptacles  810 A,  810 B,  810 C, and  810 D receive and make electrical contact with adapter pins  710 A,  710 B,  710 C, and  710 D, respectively. It should be appreciated that although four sets of adapter pins  710 A,  710 B,  710 C, and  710 D and adapter pin receptacles  810 A,  810 B,  810 C, and  810 D are illustrated in  FIGS. 7 and 8 , more or less may be utilized in practice. Furthermore, it should be appreciated that the specific structure used to couple interface adapter  730  and conductor bus interface  800  may vary. In fact, in the embodiment illustrated, interface adapter  730  and conductor bus interface  800  form an attachable-detachable connection. In an alternative embodiment, interface adapter  730  and conductor bus interface  800  form a permanent connection. 
     FIG. 9  illustrates an array socket  510  having three conductor bus interfaces  800 A,  800 B, and  800 C, in accordance with the teachings of the present invention.  FIG. 9  illustrates that more than one conductor bus interface  800  can be formed onto array socket  510  to couple to a corresponding number of power/ground couplers  700 . Although three are depicted in the illustrated embodiment, two or four may be formed or mounted on array socket  510 . If four conductor bus interfaces  800  are implemented, an alternative locking mechanism may be used. Each conductor bus interface  800  may deliver a combination of a power supply voltage and a ground reference voltage or be dedicated to delivering only one of the two. In one embodiment, conductor bus interface  800 A delivers a positive power supply voltage, conductor bus interface  800 B delivers a ground reference voltage, and conductor bus interface  800 C delivers a negative power supply voltage. Furthermore, any number of conductor buses  512  can be coupled to each of conductor bus interfaces  800 A,  800 B, and  800 C as desired. 
   Using conductor buses  512  to deliver a power supply voltage or a ground reference voltage has several advantages. First, embodiments of array socket system  500  are capable of delivering more current to microchip  520  with fewer resistive losses. By bridging pin field  570  (or ball field  570 ) conductor lines  720 A,  720 B,  720 C, and  720 D are not limited in width based on the I/O package pitch P of microchip  520 . Although conductor buses  512  are limited in width by the I/O package pitch P, this limitation can be compensated for by increasing their thickness H. 
   Second, routing power and ground conductor lines  720 A,  720 B,  720 C, and  720 D over (i.e., bridging) pin field  570  (or ball field  570 ) and the area surrounding array socket  510 , as opposed to running power/ground traces along the surface of circuit board  502 , decreases conductor trace congestion in this vital area. Reducing trace congestion in this area gives designers of circuit board  502  more flexibility in routing I/O signal traces. 
   Although the present invention is well suited for delivering power to array socket  510 , it should be appreciated that array socket system  500  may be used for other purposes as well. For instances, conductor bus  512  may be coupled to deliver a clock signal throughout microchip  520 . Similarly, other I/O signals such as data signals, control signals, and address signals can be communicated to/from microchip  520  via conductor bus  512 , conductor bus interface  800  and power/ground coupler  700 . 
     FIG. 10  illustrates an embodiment of an exemplary computer system  1000  for using array socket system  500 , in accordance with the teachings of the present invention. Computer system  1000  includes a processor chassis  1010 , a monitor  1020 , a mouse  1030  (or other pointing device), and a keyboard  1040 . The illustrated embodiment of chassis  1010  further includes a floppy disk drive  1050 , a hard disk  1060 , a power supply (not shown), and a motherboard  1070  including array socket system  500 . In this embodiment of exemplary computer system  1000 , microchip  520  is a central processing unit (“CPU”) of computer system  1000 , such as the Pentium™ 4 or the like. 
   Hard disk  1060  may comprise a single unit, or multiple units, and may optionally reside outside of computer system  1000 . Monitor  1020  is included for displaying graphics and text generated by software programs and program modules that are run by computer system  1000 . Mouse  1030  (or other pointing device) may be connected to a serial port, USB port, or other like bus port communicatively coupled to the CPU. Keyboard  1040  is communicatively coupled to motherboard  1070  in a similar manner as mouse  1030  for user entry of text and commands. In one embodiment, computer system  1000  also includes a NIC (not shown) for connecting computer system  1000  to a computer network  1080 , such as a local area network, wide area network, or the Internet. In one embodiment network  1080  is further coupled to a remote computer  1090 , such that computer system  1000  and remote computer  1090  can communicate. 
   Computer system  1000  may also optionally include a compact disk-read only memory (“CD-ROM”) drive  1100  into which a CD-ROM disk may be inserted so that executable files and data on the disk can be read or transfer to motherboard  1070  and/or hard disk  1060 . Other mass memory storage devices may be included in computer system  1000 . 
   The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
   These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.