Abstract:
A transistor bias circuit is provided that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains the mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to a circuit for biasing a transistor, and, more particularly, to a transistor bias circuit that is capable of operating from a power supply that produces a voltage that is only slightly higher than twice the base-emitter voltage of the transistor that is to be biased.  
         BACKGROUND OF THE INVENTION  
         [0002]    Modern wireless communications devices, such as cellular telephones, are held to ever-higher performance standards. Transmissions must be clear and undistorted, and the battery in the devices must be small and have a long life. In order to meet these consumer requirements, wireless telephone designers have moved away from using traditional silicon-based bipolar transistors as power amplifiers and toward using more exotic transistors, such as heterojunction bipolar transistors (“HBTs”) made of aluminum-gallium-arsenide/gallium-arsenide (“AlGaAs/GaAs”) and indium-gallium-phosphide/gallium-arsenide (“InGaP/GaAs”). Such HBTs provide outstanding power efficiency and high linearity, thus enabling cellular phones to achieve longer battery life and better signal characteristics for voice and data.  
           [0003]    Of course, an HBT, like a bipolar junction transistor (“BJT”), requires a direct-current (“DC”) bias signal (comprising both a voltage and a current) to be applied to its input terminal to establish its operating point. (The operating point of a transistor may be defined as the point on the transistor&#39;s characteristic curves at which the transistor will operate in the absence of an input signal. See, e.g., JOHN MARKUS, ELECTRONICS DICTIONARY 445 (4th ed. 1979).) Because changes in the DC bias signal affect the operating point of the HBT (and thus adversely affect the linearity of the amplifier), the DC bias signal must be very stable (preferably within 5% to 15%) and unaffected by variations in temperature or in the power supply voltage. Such a DC bias signal is normally generated by a “bias circuit.” 
           [0004]    A known bias circuit is shown in FIG. 1. Transistor Q 2  is a transistor that is to be biased. The circuit comprises: transistor Q 1 , which is preferably matched to transistor Q 2  and is connected to transistor Q 2  in a current-mirror configuration; reference resistor R 1 ; feedback transistor Q 3 ; base resistors R 2  and R 3 , which control the amount of bias current supplied to transistors Q 1  and Q 2 ; and pull-down resistor R 4 .  
           [0005]    In this circuit, resistor R 1  establishes a reference current I CM  (for example, 1 milliampere) that passes through transistor Q 1 . Because transistors Q 1  and Q 2  are connected in a current-mirror configuration, the reference current I CM  is mirrored in the matching transistor Q 2  as current I RF . If transistors Q 1  and Q 2  are matched, the circuit will be relatively insensitive to fluctuations in temperature, since the temperature characteristics of transistors Q 1  and Q 2  will be substantially the same.  
           [0006]    Feedback through transistor Q 3  and resistor R 2  stabilizes reference current I CM  to compensate for fluctuations in reference voltage V REG , in temperature, or in the parameters of the transistors. For example, if reference voltage V REG  increases, the voltage at the base of transistor Q 3 , and subsequently the voltage at the emitter of transistor Q 3 , also increases. Consequently, the amount of current flowing into the base of mirrored transistor Q 1  correspondingly increases. The collector-emitter voltage of transistor Q 1  therefore decreases, pulling down the voltage at the collector of transistor Q 1  to a value close to what it had been before reference voltage V REG  increased.  
           [0007]    Transistors Q 2  and Q 3  and resistors R 1  and R 2  thus form a negative feedback loop that provides a stable bias voltage at the emitter of transistor Q 3  and an accordingly stable current through resistor R 3  into the base of transistor Q 2 , the transistor to be biased. The effectiveness of the feedback is directly impacted by the amount of gain in the loop. Here, the total loop gain is close to the gain of transistor Q 1  and is proportional to the size of resistor R 1 : the larger the size of resistor R 1 , the more gain there is in the loop and the smaller the loop error will be.  
           [0008]    But a serious problem exists with the bias circuit of FIG. 1. Because transistors Q 1  and Q 3  are “stacked”, the circuit operates well only from a power supply voltage that is substantially higher than twice the base-emitter voltage of the transistors. An example is the case where (1) the transistors in FIG. 1. are InGaP/GaAs or AlGaAs/GaAs HBTs (which require a base-emitter voltage (V BE ) of about 1.33 V in order to operate); and (2) the power supply voltage is about 3.0 V, which is two-and-a-quarter times the base-emitter voltage of the transistors. Because the emitters of transistors Q 1  and Q 2  in this circuit are connected to ground (0 V), the voltage at the base of transistor Q 1  and the voltage at the base of transistor Q 2  must be at least about 1.33 V in order for them to operate. Since the voltage drop across resistor R 2  (and also across RF choke L 1  and resistor R 3 ) is neglible, the voltage at the emitter of transistor Q 3  must therefore be likewise about 1.33 V.  
           [0009]    Similarly, transistor Q 3  must have a voltage difference of 1.33 V between its base and its emitter. That is, the base of transistor Q 3  must be at a voltage potential that is 1.33 V higher than the voltage potential at its emitter. But since, as described above, the voltage at the emitter of transistor Q 3  must be at least 1.33 V in order for transistors Q 1  and Q 2  to operate, the voltage at the base of transistor Q 3  must be at least 2.66 V above ground potential (1.33 V at the emitter of transistor Q 3  plus the 1.33 V emitter-base junction voltage of transistor Q 3 ), for transistor Q 3  to operate.  
           [0010]    Furthermore, in order for the voltage at the base of transistor Q 3  to be 2.66 V, the voltage drop across resistor R 1  must be about 0.34 V (the supply voltage of 3.0 V minus the necessary voltage at the base of transistor Q 3  of 2.66 V=0.34 V). If the desired current I CM  is 1 mA, for example, then the resistance of resistor R 1  would be about 340 ohms (R=V/I=0.34 V/1 mA=340 ohms). When resistor R 1  is 340 ohms, the gain in the feedback loop formed by transistors Q 1  and Q 3  and resistors R 1  and R 2 —which, as described above, is proportional to the size of resistor R 1 —is generally sufficient to provide an adequately stable bias voltage and current to transistor Q 2 .  
           [0011]    The feedback in the bias circuit of FIG. 1 becomes quickly ineffective, however, if the power supply voltage is lowered from substantially higher than twice the base-emitter voltage of the transistors in the circuit to a value only slightly higher than two times their base-emitter voltage. An example of such a supply voltage is 2.7 V, where the transistors in the circuit are HBTs having V BE .=1.33 V. This supply voltage, 2.7 V, is the power supply voltage that is available in modem cellular telephones.  
           [0012]    In order for the circuit of FIG. 1 to function from a 2.7 V supply voltage, it becomes necessary to reduce the size of resistor R 1 . The resistance of resistor R 1  for this case may be calculated as follows: the supply voltage of 2.7 V minus the necessary bias voltage of 2.66 V is 0.04 V. If current I CM  is desired to be 1 mA, resistor R 1  must be 40 ohms (R=0.04 V/1 mA=40 ohms).  
           [0013]    Thus, the size of resistor R 1  when the power supply voltage is 2.7 V (40 ohms) must be more than eight times smaller than the size of resistor R 1  when the power supply voltage is 3.0 V (340 ohms). When resistor R 1  is as small as 40 ohms, however, the gain in the feedback loop, which is proportional to the size of resistor R 1 , also is small, and, as a practical matter, is insufficient to compensate adequately for variations in temperature and power supply voltage. In other words, if the temperature or power supply voltage varies by even a small amount, the DC bias signal produced by the bias circuit will reflect the variation. The performance of the bias circuit of FIG. 1 thus is unacceptable if the supply voltage is 2.7 V.  
           [0014]    This problem of biasing an HBT when the available power supply voltage is only 2.7 V is addressed in U.S. Pat. No. 6,043,714. The solution described in this patent is to substitute a bipolar junction transistor (“BJT”) for one of cascaded transistors in the bias circuit. But circuits that include both HBTs and BJTs cannot be fabricated on a single integrated circuit, because a BJT requires a silicon substrate, while an InGaP/GaAs or AlGaAs/GaAs HBT requires a gallium-arsenide substrate.  
           [0015]    Accordingly, a bias circuit for InGaP/GaAs or AlGaAs/GaAs HBTs is needed that is capable of operating from a supply voltage of as low as 2.7 V and that can be manufactured on a single integrated circuit.  
         OBJECT OF THE INVENTION  
         [0016]    It is therefore an object of the invention to provide a transistor bias circuit that is (1) capable of operating from a power supply that produces a voltage that is only slightly greater than twice the base-emitter voltage of the transistor to be biased; (2) relatively insensitive to fluctuations in supply voltage, temperature, and transistor parameters; and (3) capable of being manufactured on the same integrated circuit as the transistor to be biased.  
         SUMMARY OF THE INVENTION  
         [0017]    In accordance with the invention, a bias circuit is provided that is capable of operating with a power supply voltage that is just above twice the value of the base-emitter voltage of the transistors in the circuit. The bias circuit includes a first transistor connected in a current-mirror configuration with the transistor to be biased (“the biased transistor”) and a feedback circuit. The voltage at the collector of the first transistor is fed back via the feedback circuit to control the voltage at the bases of the first transistor and the biased transistor.  
           [0018]    The feedback circuit comprises a non-inverting amplifier connected at its input to the collector of the first transistor and at its output to a second transistor connected in an emitter-follower configuration. This second transistor is connected at its collector to the power supply and at its emitter to the node formed by the bases of the first transistor and the biased transistor. It thus establishes base currents entering the first transistor and the biased transistor. The collector-emitter current passing through the first transistor (which is mirrored in the biased transistor) is thereby maintained at a constant level via negative feedback.  
           [0019]    The non-inverting amplifier may comprise two or more transistors in a cascade. The bias circuit stage additionally comprises several current-limiting resistive elements and one or more inductors that serve as RF chokes.  
           [0020]    Also described herein is a method of biasing a first transistor having a base, emitter, and collecter via a circuit including a second transistor connected in a current-mirror configuration with the first transistor. The method includes the steps of monitoring an electrical characteristic (current or voltage) at the collector of the second transistor, amplifying the monitored characteristic, and feeding back the amplified characteristic to control the second transistor. The step of amplifying may further include the steps of inverting the monitored characteristic and then re-inverting the characteristic, such that a non-inverted characteristic is produced. In addition, the method may comprise the step of level-shifting the monitored characteristic. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    [0021]FIG. 1 shows a schematic circuit diagram illustrating a prior art bias circuit.  
         [0022]    [0022]FIG. 2 shows a schematic circuit diagram of a bias circuit according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]    A bias circuit in accordance with an embodiment of the present invention is illustrated in FIG. 2. The circuit is similar to that described for FIG. 1 above, except that a non-inverting amplifier  100  has been added. Non-inverting amplifier  100  may comprise additional transistors Q 4  and Q 5  and resistors R 5 , R 6 , R 7 , and R 8 , the resistances of which are selected to provide appropriate quiescent operating points and transistor gains.  
         [0024]    Non-inverting amplifier  100  serves two functions: (1) level-shifting the voltage at the collector of transistor Q 1  (and the base of transistor Q 4 ) to the required operating voltage of transistor Q 3  and (2) amplifying fluctuations in the voltage at the collector of transistor Q 1 . Whereas in the circuit of FIG. 1 (without non-inverting amplifier  100 ), the voltage at the collector of transistor Q 1  had to be about 2.66 V or more in order for transistors Q 2  and Q 3  to operate, in the circuit of FIG. 2 this voltage may be as low as about 1.5 V. Resistor R 1  may therefore be large, which increases the feedback loop gain and reduces the sensitivity of the bias circuit to reference voltage fluctuations. The feedback loop gain is further increased by non-inverting amplifier  100 . The bias circuit of the present invention is thus able to compensate for smaller fluctuations than the prior art circuit of FIG. 1.  
         [0025]    The operation of the circuit in FIG. 2 is as follows. Resistor R 1  establishes a reference current I CM  passing through transistor Q 1  and also a current I B,Q4  passing into the base of transistor Q 4 . If reference voltage Vref increases, both the voltage at the base of transistor Q 4  (V B,Q4 ) and the current I B,Q4  correspondingly increase. The collector-emitter current through transistor Q 4  (V CE,Q4 ) therefore increases, while the collector-emitter voltage of transistor Q 4  (V CE,Q4 ) decreases, pulling down the voltage at the base of transistor Q 5  (V B,Q5 ) and amplifying the fluctuation in voltage V B,Q4 . The decreased voltage V B,Q5  causes the collector-emitter voltage of transistor Q 5  to increase, thus pulling up the voltage V B,Q3  at the base of transistor Q 3 . The collector-emitter voltage of transistor Q 3  correspondingly decreases, thus pulling up the voltage at the emitter of transistor Q 3 . The current into the base of transistor Q 1  in turn increases, causing the collector-emitter voltage of transistor Q 1  to decrease and thereby pulling down the voltage at its collector back to the desired quiescent value.  
         [0026]    Advantageously, by the addition of non-inverting amplifier  100 , the gain in the feedback loop is made sufficient to compensate for variations in reference voltage V REG , even when the power supply voltage is as low as 2.7 V, just slightly higher than twice the base-emitter voltage of the HBT transistors in the circuit.  
         [0027]    As in the circuit of FIG. 1, inductors L 1  and L 2  serve as RF chokes. Inductor L 1  prevents the RF input signal from affecting the bias circuit, and a power supply voltage is applied through inductor L 2  to transistor Q 2 . Capacitors C 1  and C 2  are de-coupling capacitors that eliminate DC voltages in the input and output signals.  
         [0028]    In summary, there has been disclosed a bias circuit that is capable of operating from a power supply that produces a voltage that is only slightly higher that twice the base-emitter voltage of the biased transistor. In addition, the disclosed bias circuit is relatively insensitive to fluctuations in temperature, as long as and to the extent that transistor Q 1  has the same temperature characteristics as transistor Q 2 . This condition may be satisfied by manufacturing transistors Q 1  and Q 2  as matched transistors, which is well-known in the art. Finally, because transistors Q 1 , Q 3 , Q 4 , and Q 5  may be of the same transistor type as the biased transistor Q 2 , the bias circuit and the biased transistor may be integrated on the same integrated circuit.  
         [0029]    One skilled in the art will recognize that the bias circuit of the present invention will operate without inductor L 1  and resistors R 2 , R 3 , R 4 , R 5  and R 6 . Although these elements are optional, the stability of the circuit is enhanced by their presence. In addition, depending on the particular characteristics of the bias circuit and the power amplifier (including, for example, the type of transistor used, the gain in the bias circuit feedback loop, and the parameters of the non-inverting amplifier), it may also be necessary to increase the stability of the bias circuit by adding one or more phase-compensating R-C networks, which is a well-known technique in the design of RF amplifier circuits.  
         [0030]    One skilled in the art will also recognize that although a preferred embodiment of the invention has been described as a bias circuit composed of HBTs, the invention is not limited to such transistors. An alternative embodiment of the invention may be readily constructed with, e.g., npn-type or pnp-type BJTs, other varieties of HBTs, or field-effect transistors (“FETs”). The invention is particularly suited for use whenever the supply voltage is only slightly higher than twice the base-emitter voltage (for bipolar transistors) or the gate-source voltage (for FETS) of the transistors used in the bias circuit.  
         [0031]    Since the invention can be practiced using either bipolar and field-effect transistors, and since these two types of transistors have terminals that are generally known by different names, the following terms will be used herein to describe generically the terminals of the transistors used in the invention: (1) The term “control terminal” includes the gate of a FET and the base of a bipolar transistor; (2) the term “current-source terminal” includes the drain of a FET and the collector of a bipolar transistor; and (3) the term “current-sink terminal” includes the source of a FET and the emitter of a bipolar transistor.  
         [0032]    It is further understood that the embodiments described herein are merely illustrative and are not intended to limit the scope of the invention. One skilled in the art may make various changes, rearrangements and modifications to the illustrative embodiments described above without substantially departing from the principles of the invention, which is limited only in accordance with the claims. Accordingly, all such deviations and departures should be interpreted to be within the spirit and scope of the following claims.