Abstract:
A differential pair of an RF integrated circuit device is disclosed. The differential pair of the integrated circuit device includes a first MOS formed by a multiple finger configuration, having a plurality of first gate fingers; a second MOS formed by the multiple fingers configuration, having a plurality of second gate fingers, wherein each two first gate fingers interdigitate with each two second gate fingers.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to an integrated circuit device, and more particularly to a differential pair configuration of an integrated circuit device for reducing layout area and parasitic capacitance. 
         [0003]    2. Description of the Related Art 
         [0004]    High-frequency integrated circuit devices are widely applied in telecommunications equipment and broadband wireless communications. The high-frequency integrated circuit devices include circuits such as a Gilbert cell. A Gilbert cell typically incorporates a differential amplification circuit and an emitter follower. A typical Gilbert cell features a circuit formed by cross-connecting two differential amplification circuits connected in series to one differential amplification circuit.  FIG. 1  is a circuit diagram showing a circuit configuration of a typical differential pair. Two MOS transistors form the differential pair with a common source to multiply the difference between two inputs, G 1  and G 2 , by a predetermined constant, to obtain the differential gain.  FIG. 2  further illustrates the layout of the differential pair and shows an example of a conventional circuit layout of the typical differential pair. The transistor T 1  includes gate fingers G 22  to G 24  electrically connected to a gate wire W G1 , drain fingers D 22  and D 23  electrically connected to a drain wire W D1 , and source fingers S 22  and S 23  electrically connected to a source line W S1 . The transistor T 1  further comprises a guard ring  21   a  coupled to the body of the transistor T 1 . The transistor T 2  includes gate fingers G 25  to G 27  electrically connected to a gate wire W G2 , drain fingers D 25  and D 26  electrically connected to a drain wire W D2 , and source fingers S 25  and S 26  electrically connected to a source line W S2 . The transistor T 2  further comprises a guard ring  21   b  coupled to the body of the transistor T 2 . In the conventional layout, the differential pair occupies too much layout area, easily generating large parasitic capacitance due to the metal connection. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    A differential pair configuration of an integrated circuit for reducing layout area and parasitic capacitance is provided. 
         [0006]    An exemplary embodiment of an integrated circuit device comprises a first MOS formed by a multiple fingers configuration, having a plurality of first gate fingers; a second MOS formed by the multiple fingers configuration, having a plurality of second gate fingers, wherein each two first gate fingers interdigitate with each two second gate fingers. 
         [0007]    Another exemplary embodiment of the integrated circuit device comprises a plurality of first gate fingers; a plurality of second gate fingers, wherein each two first gate fingers interdigitate with each two second gate fingers; a plurality of first drain fingers formed between each two first gate fingers; a plurality of second drain fingers formed between each two second gate fingers; a plurality of common source fingers formed between one first gate finger and one second gate finger. 
         [0008]    Another exemplary embodiment of the integrated circuit device comprises a first differential pair and a second differential pair. The first differential pair comprises a first drain finger coupled to a first drain wire, a first gate finger coupled to a first gate wire, a first source finger coupled to a common source wire, a second gate finger coupled to a second gate wire, and a second drain finger coupled to a second drain wire. The second differential pair comprises a third drain finger coupled to the first drain wire, a third gate finger coupled to the first gate wire, a second source finger coupled to the common source wire, a fourth gate finger coupled to the second gate wire, and a fourth drain finger coupled to the second drain wire. 
         [0009]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0011]      FIG. 1  is a circuit diagram showing a circuit configuration of a typical differential pair. 
           [0012]      FIG. 2  shows an example of a conventional circuit layout of the typical differential pair. 
           [0013]      FIG. 3  shows a circuit layout of an embodiment of the differential pair. 
           [0014]      FIG. 4  is a cross section view of the differential pair in  FIG. 3 . 
           [0015]      FIG. 5  shows a circuit layout of another embodiment of the differential pair. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0017]    The following describes an embodiment of an integrated circuit device of the invention, with a differential pair given as an example. The differential pair relating of the invention has a circuit configuration as shown in  FIG. 1 , and is characterized by a circuit layout of the transistors, T 1  and T 2 .  FIG. 3  shows a circuit layout of an embodiment of the differential pair. The transistors T 1  and T 2  both have a multiple finger configuration. The transistor T 1  has drain fingers D 31  to D 34  (D 31 , D 32 , D 33  and D 34 ) electrically connected to a drain wire W D1 , and gate fingers G 31   a  to G 37   a  (G 31   a,  G 32   a,  G 33   a,  G 34   a,  G 35   a,  G 36   a  and G 37   a ) electrically connected to a gate line W G1 . The transistor T 2  has drain fingers D 35  to D 38  (D 35 , D 36 , D 37  and D 38 ) electrically connected to a drain wire W D2 , and gate fingers G 31   b  to G 37   b  (G 31   b,  G 32   b,  G 33   b,  G 34   b,  G 35   b,  G 36   b  and G 37   b ) electrically connected to a gate line W G2 . The transistors T 1  and T 2  share source fingers S 31  to S 37  (S 31 , S 32 , S 33 , S 34 , S 35 , S 36  and S 37 ) electrically connected to a source line W S . The source line W S  can be connected to a virtual ground. The guard ring  31  is coupled to both the bodies of the transistors T 1  and T 2 . In this layout diagram, each two gate fingers of transistor T 1  interdigitate with each two gate fingers of transistor T 2 . The drain fingers D 31  to D 34  are disposed between two gate fingers of transistor T 1 . The drain fingers D 35  to D 38  are disposed between two gate fingers of transistor T 2 . The source fingers S 31  to S 37  are disposed between one gate finger of transistor T 1  and one gate finger of transistor T 2 . According to the differential pair configuration shown in  FIG. 3 , the layout area can be reduced and the source parasitic capacitance also can be reduced due to the shared source and guard ring. 
         [0018]    It should be noted that the differential pair circuit of the invention can be utilized in integrated circuit devices operated in high frequency, such as RF devices. 
         [0019]      FIG. 4  is a cross sectional view of the differential pair shown in  FIG. 3 . In  FIG. 4 , for brevity, only the drain fingers D 31  and D 32 , gate fingers G 31   a  and G 37   b,  and source fingers S 31  and S 32  are shown, others have similar structure. A p+ region is doped on a P-substrate  41  to form the guard ring  31 . The two differential pair configurations are divided by a shallow trench isolation (STI) doped on the P-substrate. A plurality of n+ regions is doped on the P-substrate  41  to form source fingers and drain fingers. The fingers including gate fingers, drain fingers, and source fingers, are formed by a conductive layer, such as conductive layer  44 , and a metal contact pad, such as metal contact pad  45 . The remaining space, with the exception of the conductive layer and metal contact pad, is filled with isolation material. The metal contact pads of the source fingers are not disposed in the same layer in which metal contact pads of the drain fingers and gate fingers are disposed. When the metal contact pads of the drain fingers and gate fingers are formed, an isolation layer  42  covers the metal contact pads. A plurality of vias, such as via  43 , is then formed by perforating the isolation layer  42  based on the position of source fingers and filled with conductive material. The metal contact pads are then formed on the vias. According to the configuration shown in  FIG. 4 , the source parasitic capacitance can be efficiently reduced and the differential pair obtains better matching of the transistors T 1  and T 2 . 
         [0020]      FIG. 5  shows a circuit layout of another embodiment of the differential pair. The transistors T 1  and T 2  both have a multiple finger configuration. The transistor T 1  has drain fingers D 51 , D 52 , D 53  and D 54  electrically connected to a drain wire W D1 , and gate fingers G 51 , G 52 , G 53  and G 54  electrically connected to a gate line W G1 . The transistor T 2  has drain fingers D 55 , D 56 , D 57  and D 58  electrically connected to a drain wire W D2 , and gate fingers G 55 , G 56 , G 57  and G 58  electrically connected to a gate line W G2 . The transistors T 1  and T 2  share source fingers S 51 , S 52 , S 53 , and S 54  electrically connected to a source line W S . The source line W S  can be connected to a virtual ground. In the circuit layout, a guard ring  51  is provided and is coupled to both the bodies of the transistors T 1  and T 2 . In  FIG. 5 , we can find that the differential pair comprises plural differential pair units, such as the differential pair unit formed by the drain finger D 51 , the gate finger G 51 , the source finger S 51 , the gate finger G 55 , and the drain finger D 55 . In this embodiment, the differential pair comprises four differential pair units, and in another embodiment, the differential pair may only comprise one differential pair unit. The advantage of the configuration shown in  FIG. 5  is that the source parasitic capacitance can be reduced due to the shared source and guard ring. 
         [0021]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.