Abstract:
A circuit for electric fuses includes circuits for sensing status and programming that have separate paths for each operation. The circuit includes a plurality of electrically programmable fuses and, associated with each fuse, a switch for coupling a first terminal of the fuse to a ground supply for programming or to a comparator for sensing. The circuit uses a switched current source to supply current to the fuses for programming. The comparator senses a fuse status when a current source is switched through the fuse. The comparator compares a voltage across the fuse and associated switches to a comparison voltage across a comparison resistor and switches included for matching.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates generally to integrated circuit fuses and more particularly to circuits for programming and sensing the state of electrically programmable fuses. 
         [0002]    Integrated circuits may often advantageously use permanent storage for holding information such as chip identification, redundancy placement, and calibration for trimming resistors, capacitors, other analog circuit components. Permanent storage that is reliable and economical is desirable. 
         [0003]    Advantages of electrical fuses (efuses) for permanent storage in integrated circuits have been previously described, for example, in U.S. Pat. No. 7,098,721. Electrical fuses do not require special manufacturing equipment, such as laser trimming equipment needed for laser-cut fuses. Electric fuses are permanent under high stress conditions that may cause volatility problems with other permanent storage such as EEPROM. Additionally, electrical fuses do not require specialized fabrication processes. 
         [0004]    However, programming and sensing circuits must be advanced to better use electrical fuses. The sense circuit should not alter the programming of the fuse, and the programming of the fuse should be sensed reliably and quickly. 
       SUMMARY OF THE INVENTION 
       [0005]    Embodiments of the invention are directed toward circuits for sensing and programming of electric fuses in integrated circuits. 
         [0006]    An exemplary embodiment of the present invention provides an efuse circuit, including: an electrically programmable fuse; a first switch for coupling a first terminal of the fuse to a ground supply; a comparator for sensing a status of the fuse; a second switch for coupling the first terminal of the fuse to a first input terminal of the comparator; and a reference voltage circuit coupled to a second input terminal of the comparator. 
         [0007]    The efuse circuit may include a switchable circuit for programming the fuse, the switchable circuit coupled to a second terminal of the fuse. 
         [0008]    The switchable circuit may include a current source coupled to the second terminal of the fuse, and a switch for coupling the second terminal of the fuse to the ground supply. 
         [0009]    The reference voltage circuit may include: a reference current source coupled to the second input terminal of the comparator; a reference resistor; a first matching switch coupled between the reference current source and a first terminal of the reference resistor; and a second matching switch coupled between a second terminal of the reference resistor and the ground supply. 
         [0010]    The efuse circuit may include a second current source coupled to the first input of the comparator. 
         [0011]    The reference current source and second current source may be configured to supply currents having substantially the same magnitude. 
         [0012]    The efuse circuit may include a current source coupled to the second terminal of the fuse, and a switch for coupling the second terminal of the fuse to the ground supply. 
         [0013]    The first switch may include a transistor having a drain terminal coupled to the first terminal of the fuse, a gate terminal coupled to a program select signal, and a source terminal coupled to the ground supply; the second switch may include a transistor having a drain terminal coupled to the second current source, a gate terminal coupled to a sense select signal, and a source terminal coupled to the first terminal of the fuse; the first matching switch may include a transistor having a drain terminal coupled to the reference current source, a gate terminal coupled to a voltage supply, and a source terminal coupled to the first terminal of the reference resistor; the second matching switch may include a transistor having a drain terminal coupled to the second terminal of the reference resistor, a gate terminal coupled to the voltage supply, and a source terminal coupled to the ground supply; and the switch for coupling the second terminal of the fuse to the ground supply may include a transistor having a drain terminal coupled to the second terminal of the fuse, a gate terminal coupled to a programming control signal, and a source terminal coupled to the ground supply. 
         [0014]    Another exemplary embodiment of the present invention provides an efuse circuit, including: a plurality of electrically programmable fuses; a plurality of first switches for coupling a first terminal of a corresponding one of the plurality of fuses to a ground supply; a comparator for sensing statuses of the fuses; a plurality second switches for coupling the first terminal of the corresponding one of the plurality of fuses to a first input terminal of the comparator; and a reference voltage circuit coupled to a second input terminal of the comparator. 
         [0015]    The efuse circuit may include a switchable circuit for programming the fuse, the switchable circuit including a current source coupled to a second terminal of each of the plurality of fuses, and a switch for coupling the second terminals of the plurality of fuses to the ground supply. 
         [0016]    The reference voltage circuit may include: a reference current source coupled to the second input terminal of the comparator; a reference resistor; a first matching switch coupled between the reference current source and a first terminal of the reference resistor; and a second matching switch coupled between a second terminal of the reference resistor and the ground supply. 
         [0017]    The efuse circuit may include a second current source coupled to the first input of the comparator. 
         [0018]    The first switches may include transistors having drain terminals coupled to the first terminals of the plurality of fuses, gate terminals coupled to program select signals, and source terminals coupled to the ground supply; the second switches may include transistors having drain terminals coupled to the second current source, gate terminals coupled to sense select signals, and source terminals coupled to the first terminals of the plurality of fuses; the first matching switch may include a transistor having a drain terminal coupled to the reference current source, a gate terminal coupled to a voltage supply, and a source terminal coupled to the first terminal of the reference resistor; the second matching switch may include a transistor having a drain terminal coupled to the second terminal of the reference resistor, a gate terminal coupled to the voltage supply, and a source terminal coupled to the ground supply; and the switch for coupling the second terminals of the plurality of fuses to the ground supply may include a transistor having a drain terminal coupled to the second terminals of the plurality of fuses, a gate terminal coupled to a programming control signal, and a source terminal coupled to the ground supply. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    These and other features and aspects according to exemplary embodiments of the present invention will become better understood in reference to the following description, appended claims, and accompanying drawings where: 
           [0020]      FIG. 1  is a schematic diagram of a single efuse programming and sensing circuit according to an embodiment of the present invention; and 
           [0021]      FIG. 2  is a schematic diagram of a multiple efuse programming and sensing circuit according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]      FIG. 1  is a schematic diagram of an electrical fuse programming and sensing circuit according to an embodiment of the present invention. The circuit is suitable for embedding in an integrated circuit (IC). The circuit provides an electrical fuse (efuse) F&lt; 0 &gt;, circuitry for programming the state of the efuse, and circuitry for sensing the state of the efuse. The circuit includes three sub-circuits. A first sub-circuit  10  is principally configured for use in programming the efuse F&lt; 0 &gt;. A second sub-circuit  20  includes the efuse F&lt; 0 &gt;. A third sub-circuit  30  is configured for sensing the state of the electrical fuse. 
         [0023]    The first sub-circuit  10  receives a programming control signal PROGRAM that controls whether the circuit operates to program (or blow) the efuse F&lt; 0 &gt; or operates to sense the status of the efuse F&lt; 0 &gt;. When the programming control signal PROGRAM is at a high level, the circuit is configured for programming the efuse F&lt; 0 &gt;, and when the programming control signal PROGRAM is at a low level, the circuit is configured for sensing the state of the efuse F&lt; 0 &gt;. The first sub-circuit  10  receives a programming power supply VCCprogram. The programming power supply VCCprogram may supply a voltage greater than the nominal voltage of the IC. For example, in one embodiment, the programming power supply VCCprogram supplies a voltage that is nominally 5 V, whereas the IC (or parts thereof) operates with a nominal supply of 3.3 V. A higher voltage for the programming supply voltage VCCprogram may beneficially aid in routing a sufficiently large current through the efuse F&lt; 0 &gt; to program it. 
         [0024]    The first sub-circuit  10  includes an inverter  11 , a first transistor M 7 , and a first current source  12 . The inverter  11  has its input coupled to the programming control signal PROGRAM. The output of the inverter  11  is coupled to a gate terminal of the first transistor M 7 . A source terminal of the first transistor M 7  is coupled a ground supply GND. A drain terminal of the first transistor M 7  is coupled to a programming common node X. When the programming control signal PROGRAM is at a high voltage, the output of the inverter  11  is a low voltage and the first transistor M 7  is off. This condition is used for programming the efuse F&lt; 0 &gt; and the first transistor M 7  is essentially an open circuit during programming. When the programming control signal PROGRAM is at a low voltage, the output of the inverter  11  is a high voltage and the first transistor M 7  is on. This condition is used for sensing the status of the efuse F&lt; 0 &gt; and the first transistor M 7  essentially supplies the ground supply GND to the programming common node X. 
         [0025]    The first current source  12  is coupled to the programming supply voltage VCCprogram for a source of electricity. The output current of the first current source  12  is coupled to the programming common node X from which it is coupled to the efuse F&lt; 0 &gt;. The first current source  12  is a switched current source, that is, the current may be switched off or on. The first current source  12  receives the programming control signal PROGRAM to control switching the output current off and on. When the programming control signal PROGRAM is at a high voltage, the first current source  12  supplies a current of magnitude Iprogram to the programming common node X. This condition is used for programming the efuse F&lt; 0 &gt; and the current is routed through the efuse F&lt; 0 &gt; if it is to be programmed. Iprogram is designed to be sufficient to program efuse F&lt; 0 &gt;, for example, 10 mA. When the programming control signal PROGRAM is at a low voltage, the first current source  12  is turned off and does not supply current to the programming common node X. This condition is used for sensing the status of the efuse F&lt; 0 &gt; and the first current source  12  is essentially not a part of sensing fuse status. The first current source  12  may be implemented, for example, with current mirrors. 
         [0026]    Although a specific circuit arrangement is shown in  FIG. 1 , many variations of the first sub-circuit are within the scope of the invention. For example, an embodiment may invert the polarities of the programming current and make corresponding changes to power supplies and control signals. Additionally, in an embodiment, the first transistor M 7  may be replaced with a cascode of transistors to facilitate a programming supply voltage greater than the intended operating voltage of the transistors available on the IC. 
         [0027]    The second sub-circuit  20  includes the efuse F&lt; 0 &gt;, a program select transistor M 5 , and a sense select transistor M 3 . The efuse F&lt; 0 &gt; is made of a small segment of silicided polysilicon, for example, as described in “IBM System z9 eFUSE applications and methodology,” R. F. Rizzolo et al., IBM J. Res. &amp; Dev., vol. 51, no. 1/2, January/March 2007, the contents of which are incorporated herein by reference. Alternatively, efuse F&lt; 0 &gt; may utilize other suitable materials. The efuse F&lt; 0 &gt; has a relatively small resistance, for example, 200Ω, before programming. After programming, the efuse F&lt; 0 &gt; has a relatively large resistance, for example, 2000Ω. The efuse F&lt; 0 &gt; has a first terminal coupled to the programming common node X and a second terminal coupled to an internal node Z. 
         [0028]    The program select transistor M 5  receives a program select signal PROGRAM&lt; 0 &gt; at its gate. The program select transistor M 5  has a source terminal coupled to the ground supply GND and a drain terminal coupled to the internal node Z. The program select transistor M 5  operates in conjunction with the first sub-circuit  10  to program the efuse F&lt; 0 &gt;. When the program select signal PROGRAM&lt; 0 &gt; is at a high voltage, the program select transistor M 5  is on. This condition is used for programming the efuse F&lt; 0 &gt; and the program select transistor M 5  essentially connects the internal node Z to the ground supply GND. Concurrently, the programming control signal PROGRAM is at a high level. Thus, a current supplied by the first current source  12  passes through the efuse F&lt; 0 &gt; and through the program select transistor M 5  to the ground supply GND. The program select transistor M 5  is designed to have a low on resistance so that it can sink the programming current with a small voltage drop that will not interfere with programming the efuse. However, a low on resistance is associated with a large size transistor. Larger size transistors are associated with larger leakage currents that may interfere with circuit operation. Additionally, larger size transistors are associated with larger capacitances that may interfere with sensing the status of the fuse. When the program select signal PROGRAM&lt; 0 &gt; is at a low voltage, the program select transistor M 5  is off. This condition is used for sensing the status of the efuse F&lt; 0 &gt; and the program select transistor M 5  is essentially an open circuit during sensing. 
         [0029]    The sense select transistor M 3  receives a sense select signal SENSE&lt; 0 &gt; at its gate. The sense select transistor M 3  has a source terminal coupled to the internal node Z and a drain terminal coupled to a sensing common node Y. The sense select transistor M 3  operates in conjunction with the first sub-circuit  10  and the third sub-circuit  30  to sense the status of the efuse F&lt; 0 &gt;. When the sense select signal SENSE&lt; 0 &gt; is at a low voltage, the sense select transistor M 3  is off. This condition is used for programming the status of the efuse F&lt; 0 &gt; and the sense select transistor M 3  is essentially an open circuit during programming. When the sense select signal SENSE&lt; 0 &gt; is at a high voltage, the sense select transistor M 3  is on. This condition is used for sensing the status of the efuse F&lt; 0 &gt; and the sense select transistor M 3  essentially connects the internal node Z to the sensing common node Y. Concurrently, the programming control signal PROGRAM is at a low level. Thus, the programming common node X is coupled to the ground supply GND via the first transistor M 7 . Since the transistors used to switch programming current and the transistors used to switch sensing current are distinct, they may be separately designed for their intended functions. 
         [0030]    Although a specific circuit arrangement is shown in  FIG. 1 , many variations of the second sub-circuit are within the scope of the invention.  FIG. 1  shows n-type MOSFETs but other transistor types may be used. For example, an embodiment may use p-type MOSFETs and invert the polarities of the power supplies and control signals. Additionally, in an embodiment, the program select transistor M 5  or the sense select transistor M 3  may be replaced with a cascode of transistors to facilitate voltages greater than the intended operating voltage of the transistors available on the IC. 
         [0031]    The third sub-circuit  30  includes a sense current source  31 , a reference current source  32 , a comparator  35 , a first matching transistor M 1 , a second matching transistor M 2 , and a comparison resistor Rcomp. The comparator  35  has a positive input coupled to the sensing common node Y and a negative input coupled to a comparison (or reference) voltage. The comparator  35  has an output SENSEout that is a high level when the positive input of the comparator is greater than the negative input of the comparator; the comparator output SENSEout is a low level when the positive input of the comparator is less than the negative input of the comparator. 
         [0032]    The sense current source  31  supplies a current to the sensing common node Y. The supplied current, of magnitude Isense, is routed to the efuse F&lt; 0 &gt; during a sensing operation and may be chosen to be sufficiently small to avoid alter the programming of the efuse. The reference current source  32  supplies a current used to creates a voltage for comparison during sensing. More specifically, the reference current source  32  is coupled to the negative input of the comparator  35  and supplies a current of magnitude Iref. The first matching transistor M 1  has a drain terminal coupled to the reference current source  32 , a gate terminal coupled to a positive supply VCC, and a source terminal connected to a first terminal of the comparison resistor Rcomp. The second matching transistor M 2  has a drain terminal coupled to a second terminal of the comparison resistor Rcomp, a gate terminal coupled to the positive supply VCC, and a source terminal connected to the ground supply GND. The first and second matching transistors M 1 , M 2  are turned on by the positive supply VCC at their gate terminals. 
         [0033]    In one embodiment, the sense current source  31  and the reference current source  32  are constructed with current mirrors and supply currents having the same magnitude, but the invention is not so limited. The first matching transistor M 1  is designed to match the sense select transistor M 3 . That is, the first matching transistor M 1  is designed so that during sensing, the voltages between the source and drain terminals of the first matching transistor M 1  and the sense select transistor M 3  are substantially the same. When the sense current source  31  and the reference current source  32  supply currents of the same magnitude, the matching may be accomplished by making the first matching transistor M 1  be a replica of sense select transistor M 3 . Similarly, the second matching transistor M 2  is designed to match the first transistor M 7 . 
         [0034]    To further understand the sensing operation, consider the voltages at the positive and negative inputs to the comparator  35 . At the positive input, the voltage is the sum of the voltage drops across the sense select transistor M 3 , the efuse F&lt; 0 &gt;, and the first transistor M 7 . The current through each of these circuit elements is the current of magnitude Isense supplied by the sense current source  31  At the negative input of the comparator  35 , the voltage is the sum of the voltage drops across the first matching transistor M 1 , the comparison resistor Rcomp, and the second matching transistor M 2 . The current through each of these circuit elements is the current of magnitude Iref supplied by the reference current source  32 . 
         [0035]    As described above, the voltage drop across the first matching transistor M 1  matches the voltage drop across the sense select transistor M 3  and the voltage drop across the second matching transistor M 2  matches the voltage drop across the transistor M 7 . Thus, the voltage difference at the input to the comparator  35  is essentially determined by the difference in the voltage drop across the efuse F&lt; 0 &gt; and the voltage drop across the comparison resistor Rcomp. Small differences in the voltages across the transistors may exist but they are small in comparison. By designing the comparison resistor Rcomp to have a resistance between the intact and programmed resistance of the efuse F&lt; 0 &gt;, the differential voltage at the input of the comparator  35  will be positive for a programmed efuse and negative for an intact efuse. The comparator  35  may be designed to operate with high resolution ability for the expected common mode inputs, for example, by using p-type input transistors for input voltages near ground level. 
         [0036]    In one embodiment, the component values are Rcomp=1 kΩ, Isense=Iref=250 μA, and Iprogram=15 mA. A programmed efuse results in a comparison voltage of 500 mV or greater. An intact efuse results in a comparison voltage of 50 mV or less. 
         [0037]    As with the first and second sub-circuits, many variations of the third sub-circuit are within the scope of the present invention. For example, the first and second matching transistors M 1 , M 2  may be modified to match modifications to the sense select transistor M 3  and the first transistor M 7 . The sense current source  31  and the reference current source  32  may be switched so that their currents are only turned on during sensing operations. Similarly, the comparator  35  may include a clock or enable input. Additionally, the polarities of the signals and supplies may be inverted. 
         [0038]      FIG. 2  is a schematic diagram of an electrical fuse programming and sensing circuit according to an embodiment of the present invention. The circuit is similar to the embodiment of  FIG. 1  but differs in that it is adapted for multiple efuses. The circuit includes multiple efuses F&lt; 0 &gt; . . . F&lt;n&gt;. The circuit includes a first sub-circuit  10  principally configured for use in programming the efuses F&lt; 0 &gt; . . . F&lt;n&gt;. The circuit includes multiple second sub-circuits  20 . 0  . . .  20 . n,  each including an efuse and selection switches. The number of efuses corresponds to the number of bits of status to be stored by the circuit. The circuit also includes a third sub-circuit  30  configured for sensing the state of the fuses. 
         [0039]    The first sub-circuit  10  and the third sub-circuit  30  are the same as the first and third sub-circuits, respectively, of the embodiment of  FIG. 1 . The second sub-circuits  20 . 0  . . .  20 . n  correspond to the second sub-circuit of the embodiment of  FIG. 1 . Each of the second sub-circuits is essentially the same. 
         [0040]    The second sub-circuits  20 . 0  . . .  20 . n  include the efuses F&lt; 0 &gt; . . . F&lt;n&gt;, program select transistors M 5 &lt; 0 &gt; . . . M 5 &lt; n &gt;, and sense select transistors M 3 &lt; 0 &gt; . . . M 3 &lt; n &gt;. Each of the efuses F&lt; 0 &gt; . . . F&lt;n&gt; is made of a small segment of silicided polysilicon as described above regarding the embodiment of  FIG. 1 . Each efuse F&lt; 0 &gt; . . . F&lt;n&gt; has a first terminal coupled to a programming common node X and a second terminal coupled to an internal node Z&lt; 0 &gt; . . . Z&lt;n&gt;. That is, the first terminals of the efuses F&lt; 0 &gt; . . . F&lt;n&gt; are commonly connected to the programming common node X. However, the second terminals of the efuses F&lt; 0 &gt; . . . F&lt;n&gt; are coupled to internal nodes Z&lt; 0 &gt; . . . Z&lt;n&gt; that are not shared between the second sub-circuits  20 . 0  . . .  20 . n.    
         [0041]    Each of the program select transistors M 5 &lt; 0 &gt; . . . M 5 &lt; n &gt; receives a program select signal PROGRAM&lt; 0 &gt; . . . PROGRAM&lt;n&gt; at its gate. The program select transistors M 5 &lt; 0 &gt; . . . M 5 &lt; n &gt; have source terminals coupled to the ground supply GND and drain terminals coupled to the corresponding internal node Z&lt; 0 &gt; . . . Z&lt;n&gt;. The program select transistors M 5 &lt; 0 &gt; . . . M 5 &lt; n &gt; operate in conjunction with the first sub-circuit  10  to program the efuses F&lt; 0 &gt; . . . F&lt;n&gt;. When one of the program select signals PROGRAM&lt; 0 &gt; . . . PROGRAM&lt;n&gt; is at a high voltage, the corresponding one of the program select transistors M 5 &lt; 0 &gt; . . . M 5 &lt; n &gt; is on. Concurrently, the programming control signal PROGRAM is at a high level. Thus, a current supplied by the first current source  12  passes through a selected one of the efuses F&lt; 0 &gt; . . . F&lt;n&gt; and through the corresponding one of the program select transistors M 5 &lt; 0 &gt; . . . M 5 &lt; n &gt; to the ground supply GND. When the program select signals PROGRAM&lt; 0 &gt; . . . PROGRAM&lt;n&gt; are at a low voltage, the program select transistors M 5 &lt; 0 &gt; . . . M 5 &lt; n &gt; are off. This condition is used for sensing the status of the efuses F&lt; 0 &gt; . . . F&lt;n&gt;. 
         [0042]    The sense select transistors M 3 &lt; 0 &gt; . . . M 3 &lt; n &gt; receive sense select signals SENSE&lt; 0 &gt; . . . SENSE&lt;n&gt; at their gates. The sense select transistors M 3 &lt; 0 &gt; . . . M 3 &lt; n &gt; have source terminals coupled the corresponding one of the internal nodes Z&lt; 0 &gt; . . . Z&lt;n&gt; and drain terminals coupled to a sensing common node Y. The sense select transistors M 3 &lt; 0 &gt; . . . M 3 &lt; n &gt; operate in conjunction with the first sub-circuit  10  and the third sub-circuit  30  to sense the status of the efuses F&lt; 0 &gt; . . . F&lt;n&gt;. When one of the sense select signals SENSE&lt; 0 &gt; . . . SENSE&lt;n&gt; is at a low voltage, the corresponding one of sense select transistors M 3 &lt; 0 &gt; . . . M 3 &lt; n &gt; is off. This condition is used during programming and when sensing the status of another of the efuses F&lt; 0 &gt; . . . F&lt;n&gt;. When one of the sense select signals SENSE&lt; 0 &gt; . . . SENSE&lt;n&gt; is at a high voltage, the corresponding one of the sense select transistors M 3 &lt; 0 &gt; . . . M 3 &lt; n &gt; is on. This condition is used for sensing the status of the corresponding one of the efuses F&lt; 0 &gt; . . . F&lt;n&gt;. Concurrently, the programming control signal PROGRAM is at a low level and the program select signals PROGRAM&lt; 0 &gt; . . . PROGRAM&lt;N&gt; are at low levels. 
         [0043]    To further understand the sensing operation, consider a case where the status of the n-th efuse F&lt;n&gt; is to be sensed. The programming control signal PROGRAM is at a low level, which couples the programming common node X to the ground supply GND via the first transistor M 7 . All of the program select signals PROGRAM&lt; 0 &gt; . . . PROGRAM&lt;n&gt; are at low levels, which causes all the program select transistors M 5 &lt; 0 &gt; . . . M 5 &lt; n &gt; to be off. The n-th sense select signal SENSE&lt;n&gt; is at a high level, which turns on the n-th sense select transistor M 3 &lt; n &gt; and couples the n-th efuse F&lt;n&gt; to the sensing common node Y. The other sense select signals are at low levels, which turn off the other sense select transistors. Since the third sub-circuit  30  sources a current to the sensing common node Y, that current is coupled through the n-th efuse F&lt;n&gt;. The sensing operation then compares the voltage on the sensing common node Y to a comparison voltage as described for the embodiment of  FIG. 1 . Since only one of the efuses F&lt; 0 &gt; . . . F&lt;n&gt; is coupled to the comparator at a time, sensing is not slowed by capacitance associated with the other fuses or their surrounding circuitry. 
         [0044]    Although a specific circuit arrangement is shown in  FIG. 2 , many variations are within the scope of the invention. For example, the sub-circuits may be altered as described regarding the embodiment of  FIG. 1 . Additionally, the efuses F&lt; 0 &gt; . . . F&lt;n&gt; may be hierarchically organized. Additionally, the efuses F&lt; 0 &gt; . . . F&lt;n&gt; may be grouped with subsets of the efuses F&lt; 0 &gt; . . . F&lt;n&gt; coupled to one of several of the first or second sub-circuits. 
         [0045]    Although the present invention has been described in certain specific embodiments, many additional modifications and variations would be apparent to those skilled in the art. It is therefore to be understood that this invention may be practiced other than as specifically described. Thus, the present embodiments of the invention should be considered in all respects as illustrative and not restrictive and the scope of the invention determined by the claims supported by this application and their equivalents.