Abstract:
A latch circuit to perform high-speed input and output operations by reducing a load of an input circuit or an output circuit of the latch circuit. The latch circuit includes four or more inverters connected in a loop to hold a signal, a plurality of input terminals respectively connected to different nodes, and a plurality of output terminals respectively connected to different nodes. At least one input terminal of the latch circuit is used for normal operation of the latch circuit, and at least one input terminal is used for a test operation of the latch circuit. Further, at least one output terminal of the latch circuit is used for normal operation of the latch circuit, and at least one output terminal is used for a test operation of the latch circuit. The latch circuit reduces the number of circuit elements at a connecting point of an input terminal of the latch circuit or at a connecting point of an output terminal of the latch circuit. By reducing the number of circuit elements at the input or output connections, a load of the input or output can be reduced, and thereby high-speed input or output can be realized.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims priority of Japanese patent application no. 11-192375, filed Jul. 6, 1999, and is a continuation of U.S. patent application Ser. No. 09/610,982, filed Jul. 6, 2000 abandoned, the contents being incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to a latch circuit which reduces the number of circuit elements connected to an input or an output to reduce load at the input or output to thereby achieve high-speed operation. 
     2. Description of the Related Art 
     A latch circuit has the function of temporarily holding (i.e., storing) signals.  FIGS. 1–3  illustrate examples of related art latch circuits. As shown in  FIGS. 1–3 , to hold signals the related art latch circuits include a loop circuit, which is formed of two stages of inverters to hold signals. A latch circuit may be connected with a plurality of input circuits and output circuits. In such a latch circuit, the number of terminals respectively connected to input circuit and output circuits has increased. 
     The related art latch circuits shown in  FIGS. 1–3  respectively include a plurality of input circuits and output circuits connected thereto. 
     The example of the related art latch circuit shown in  FIG. 1  includes an input node N 1 , and an output node N 2 . Two input circuits (not shown) are connected at the input node N 1 , which is the input of the latch circuit. Specifically, an input I 1  from a first input circuit and an input I 2  from a second input circuit are connected at the input node N 1 . Moreover, two output circuits (not shown) are connected by the output node N 2 , which is the output of the latch circuit. Specifically, an output O 1  to a first output circuit and an output O 2  to a second output circuit are connected at the output node N 2 . 
     The example of the related art latch circuit shown in  FIG. 2  includes two input nodes N 1  and N 2 , and two output nodes N 3  and N 4 . In a manner similar to the latch circuit shown in  FIG. 1 , two input circuits (not shown) are connected to the latch circuit shown in  FIG. 2 . Specifically, an input I 1  from a first input circuit is connected at the node N 1 , while an input I 2  from a second input circuit is connected at the node N 2 . Moreover, in a manner similar to  FIG. 1 , two output circuits (not shown) are connected to the latch circuit. Specifically, an output O 1  to a first output circuit is connected at the node N 3 , while an output O 2  to a second output circuit is connected at the node N 4 . 
     The example of the related art latch circuit shown in  FIG. 3  includes two input nodes N 1  and N 2 , and two output nodes N 3  and N 4 . Similar to the latch circuit shown in  FIG. 1 , the latch circuit shown in  FIG. 3  is connected with two input circuits. Specifically, an input I 1  and an input /I 1  from a first input circuit are respectively connected to the node N 1  and the node N 2 , while an input I 2  from a second input circuit is connected at the node N 1 . 
     Moreover, similar to the latch circuit shown in  FIG. 1 , two output circuits (not shown) are connected to the latch circuit of  FIG. 3 . Specifically, an output O 1  and an output /O 1  to a first output circuit are respectively connected at the node N 3  and the node N 4 , and an output O 2  to the second output circuit is connected at the node N 2 . 
     The inputs I 1  and /I 1  and output O 1  are used for the normal operation, and the input I 2  and output O 2  are used for a test operation. High-speed input and output are required for the inputs I 1  and /I 1  and the output O 1 , while the high-speed input and output are not required for the input I 2  and output O 2 . 
     As shown in  FIG. 1 , the inputs I 1  and I 2  of the latch circuit, an input of a first inverter  1  and an output of a second inverter  2  are connected at the input node N 1 . The input I 1  requires a high-speed input. However, because the other three circuit elements connected at the node N 1  become a large load, the latch circuit cannot assure the high-speed input for the input I 1 . 
     As shown in  FIG. 2 , the input I 1  of the latch circuit, the output of the first inverter  1 , the input of the second inverter  2  and the input of the third inverter  3  are connected at the input node N 1 . The input I 1  requires high-speed input. However, because the other three circuit elements connected at the node N 1  become a large load, the latch circuit cannot assure the high-speed input for the input I 1 . 
     As shown in  FIG. 3 , the inputs I 1  and I 2  of the latch circuit, the output of the first inverter  1 , the input of the second inverter  2  and the input of the third inverter  3  are connected at the input node N 1 . The input I 1  requires high-speed input. However, because the other four circuit elements connected at the node N 1  become a large load, the latch circuit cannot assure the high speed input for the input I 1 . 
     Moreover, as shown in  FIG. 3 , an input /I 1 , which is the complement signal of the first input I 1  of the latch circuit, the output O 2  of the latch circuit, the output of the second inverter  2 , the input of the first inverter  1  and the input of the fourth inverter  4  are connected at the node N 2 . The input /I 1  requires a high-speed input. However, because the other four circuit elements connected at the node N 2  become a large load, the latch circuit cannot assure the high-speed input for the input /I 1 . 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a latch circuit to hold signals, the latch circuit including four or more inverters forming a loop to hold the signals. 
     It is an object of the present invention to provide a latch circuit having a reduced load applied to an input and output of the latch circuit. 
     It is another object of the present invention to provide a latch circuit which achieves high-speed input and output by reducing the number of circuit elements connected to a connecting point of an input or to a connecting point of an output which require high-speed operations. 
     Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a latch circuit for holding signals, the latch circuit comprising four or more inverters connected in a loop to hold a signal. The latch circuit may further comprise a plurality of input terminals respectively connected to different nodes. The latch circuit, may further comprise a plurality of output terminals respectively connected to different nodes. The latch circuit may further comprise a plurality of input terminals and output terminals respectively connected to different nodes. 
     In accordance with embodiments of the present invention, at least one input terminal of the latch circuit is used for normal operation of the latch circuit, and at least one input terminal is used for a test operation of the latch circuit. 
     In accordance with embodiments of the present invention, at least one output terminal is used for normal operation of the latch circuit, and at least one output terminal is used for a test operation of the latch circuit. 
     In accordance with embodiments of the present invention, complementary signals are supplied to at least one pair of input terminals of the latch circuit. 
     In accordance with embodiments of the present invention, the latch circuit comprises four inverters connected in a loop. 
     In accordance with embodiments of the present invention, the latch circuit comprises six inverters connected in a loop. 
     Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a latch circuit, comprising a plurality of input terminals and a plurality of output terminals, wherein the plurality of input terminals and the plurality of output terminals are respectively connected at different nodes, and at most three circuit elements are connected at the different nodes. 
     Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a latch circuit comprising a plurality of input terminals and a plurality of output terminals, wherein complementary input signals are supplied to at least one pair of input terminals, and wherein a plurality of input terminals and a plurality of output terminals are respectively connected at different nodes, and four or fewer circuit elements are respectively connected at the different nodes. 
     Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a memory, comprising a latch circuit to hold a signal, the latch circuit comprising four or more inverters connected in a loop to hold the signal. 
     Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a semiconductor chip design system to design a latch circuit, comprising a unit cell library in which a latch circuit comprising four or more inverters connected in a loop to hold a signal is registered; and a macro cell library in which a macro using the latch circuit is registered. 
     In accordance with the present invention, the semiconductor chip design system generates an RTL description based on design specifications of the latch circuit, and generates a net list for the latch circuit based on the RTL description, using any one of the unit cell library and macro cell library. 
     In accordance with the present invention, the semiconductor chip design system generates layout design data for the latch circuit based on the net list, using any one of the unit cell library and the macro cell library. 
     In accordance with the present invention, the semiconductor chip design system generates mask layout data for the latch circuit based on the layout data, using any one of the unit cell library and the macro cell library. 
     In accordance with embodiments of the present invention, the number of circuit elements at a connecting point of an input terminal of the latch circuit or at a connecting point of an output terminal of the latch circuit is reduced. By reducing the number of circuit elements at the input or output connections, a load of the input or output can be reduced, and thereby high-speed input or output can be realized. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects and advantages of the present invention will become more apparent and more readily appreciated from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings of which: 
         FIG. 1  is a circuit diagram illustrating a related art latch circuit. 
         FIG. 2  is a circuit diagram illustrating a related art latch circuit. 
         FIG. 3  is a circuit diagram illustrating a related art latch circuit. 
         FIG. 4A  is a block diagram of an SRAM in accordance with embodiments of the present invention. 
         FIG. 4B  is a block diagram of an address input latch used in the SRAM in accordance with embodiments of the present invention. 
         FIG. 5  is a diagram illustrating a latch circuit in accordance with a first embodiment of the present invention. 
         FIG. 6  is a detailed circuit diagram illustrating the latch circuit in accordance with the first embodiment of the present invention. 
         FIG. 7  is a diagram illustrating a latch circuit in accordance with a second embodiment of the present invention. 
         FIG. 8  is a detailed circuit diagram of the latch circuit in accordance with the second embodiment of the present invention. 
         FIG. 9  is a block diagram of a system for designing a latch circuit in accordance with a third embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. 
       FIG. 4A  is a block diagram of a static random access memory (SRAM) in which a latch circuit in accordance with embodiments of the present invention is incorporated. As shown in  FIG. 4A , an address input latch for an inputting an address is arranged in an area  5  of the SRAM, a predecoder for predecoding the address is arranged in an area  6 , a main decoder for decoding the address is arranged in an area  7 , an input/output buffer for inputting and outputting data, a sense amplifier and a write amplifier for amplifying data are arranged in the area  8 , and a cell array for storing data is arranged in an area  9 . 
     The latch circuit in accordance with preferred embodiments of the present invention, can be applied to an address input latch arranged in the area  5  shown in  FIG. 4A . 
       FIG. 4B  is a block diagram of the address input latch in accordance with embodiments of the present invention. As shown in  FIG. 41B , since an address is formed of four bits, address input latches  14 ,  15 ,  16  and  17  are connected in four stages. The number of address input latches is set depending on the bit format of an address. 
     An input address signal  10  is supplied to the respective address input latches  14 – 17 . An address output signal I 1  is output by the respective address input latches  14 – 17 . During normal operation of the SRAM, the input address signal  10  is input and the output address signal I 1  is output. 
     Moreover, an input scan signal  12  is supplied to the address input latch  14 , and the input scan signal  12  is output as the output scan signal  13  from the address input latch  17  via the address input latch  15  and address input latch  16 . During a test operation of the SRAM, the input scan signal  12  is input and the output scan signal  13  is output to verify operation of the address input latch. 
     As described above, in accordance with preferred embodiments of the present invention, an input address signal  10  and an input scan signal  12  are input to respective address latch circuits  14 – 17 , and an output address signal  11  and an output scan signal  13  are output from respective latch circuits. However, the present invention is not limited to one address signal, and can be adapted to a latch circuit to which a plurality of input signals are supplied and from which a plurality of output signals are output. 
     In accordance with the present invention, the SRAM is only an example of the type of memory to which the present invention is applicable. However, the present invention is not limited to an SRAM, and can also be applied to the other memory circuits, such as DRAM. 
     A first preferred embodiment of the present invention will now be described below with reference to  FIGS. 5 and 6 .  FIG. 5  illustrates a latch circuit having two inputs I 1 ,I 2  and two outputs O 1 , O 2 . The first input I 1  is connected to a first node N 1 , the second input I 2  is connected to a second node N 2 , the first output O 1  is connected to a third node N 3  and the second output O 2  is connected to a fourth node N 4 . 
     The first node N 1  is the connecting point of an output of a fourth inverter  21  and an input of a first inverter  18 . The second node N 2  is the connecting point of the output of a second inverter  19  and the input of a third inverter  20 . The third node N 3  is the connecting point of the output of the first inverter  18  and the input of the second inverter  19 . The fourth node N 4  is the connecting point of the output of the third inverter  20  and the input of the fourth inverter  21 . 
     As shown in  FIG. 5 , because the first input I 1 , the output of the fourth inverter  21  and input of the first inverter  18  are connected at the first node N 1 , the circuit elements which will become a load of the first input I 1  include only the output of the fourth inverter  21  and the input of the first inverter  18 . 
     In accordance with the first embodiment of the present invention, the number of circuit elements which will become a load for the input is reduced to two elements at the connecting point of the input of the latch circuit. Therefore, high-speed input operation of the latch circuit can be realized. 
     In accordance with the first embodiment of the present invention, the first input I 1  and first output O 1  are an input and an output, respectively, to be used during normal operation. The second input I 2  and the second output O 2  are an input and an output, respectively, to be used during the test operation. The first input I 1  and first output O 1  are required to realize high-speed input and output, and the second input I 2  and second output O 2  are not required to realize high-speed input and output. In accordance with the first embodiment of the present invention, the high-speed operation is realized during the usual operation of the latch circuit by realizing a high-speed input operation of the first input I 1  which is required to realize high speed input. 
     The second input I 2  is not required to realize the high-speed input operation described above. Therefore, the second input I 2 , which is not required to realize the high-speed operation, may be connected to the node N 2 . 
       FIG. 6  is a detailed circuit diagram of the latch circuit shown in  FIG. 5  adapted to the SRAM illustrated in  FIG. 4A  in accordance with embodiments of the present invention. 
     As shown in  FIG. 6 , the first input I 1  is an input address signal, the second input I 2  is an input scan signal, the first output O 1  is an output address signal and the second output O 2  is an output scan signal. The input address signal and a clock signal are supplied to the latch circuit via a switch circuit  22 . The switch circuit  22  comprises two P-channel transistors and two N-channel transistors, which are connected in series, and is also connected to a high-voltage power source and a low-voltage power source. 
     The input scan signal and scan clock signal are supplied to the latch circuit via a switch circuit  23 . In a manner similar to the switch circuit  22 , the switch circuit  23  also comprises two P-channel transistors and two N-channel transistors, which are connected in series, and is also connected to the high-voltage power source and the low voltage power source. 
     During normal operating conditions, the scan clock signal is stopped. More specifically, a signal “1,” which is the stop signal, is supplied as the scan clock signal and connection between the switch circuit  23  and high-voltage power source and low-voltage power source is separated. The signal “1” is supplied to the gate of one P-channel transistor, the signal “0” is supplied to the gate of one N-channel transistor via an inverter  24 , and connection between the switch circuit  23  and high-voltage power source and low-voltage power source is separated. Therefore, the input scan signal and scan clock signal are not supplied to the latch circuit, but the input address signal and clock signal are supplied to the latch circuit. 
     During the test operation, the clock signal stops. That is, the “1” signal, which is the stop signal, is supplied as the clock signal and connection between the switch circuit  22  and high-voltage power source and low voltage power source is separated. More specifically, the signal “1” is supplied to the gate of one P-channel transistor, the signal “0” is supplied to the gate of one N-channel transistor via an inverter  25 , and connection between the switch circuit  22  and high-voltage power source and low-voltage power source is separated. Therefore, the input address signal and clock signal are not supplied to the latch circuit, but the input scan signal and scan clock signal are supplied to the latch circuit. 
     The first output O 1  of the latch circuit is output as the output address signal via an inverter  26 , and the second output O 2  of the latch circuit is output as the output scan signal via an inverter  27 . The inverter  26  and inverter  27  operate as buffers. However, in the embodiment shown in  FIG. 6 , the inverter  26  and inverter  27  are not absolutely necessary, and the circuit can operate without these components. 
     A second preferred embodiment of the present invention will now be described below with reference to  FIGS. 7 and 8 . 
       FIG. 7  illustrates a latch circuit including three inputs and three outputs in accordance with the second preferred embodiment of the present invention. As shown in  FIG. 7 , a first input I 1  is connected to a first node N 1 ; a second input /I 1 , which is a complementary input to the first input I 1 , is connected to a second node N 2 ; a third input I 2  is connected to a third node N 3 ; a first output O 1  is connected to a fourth node N 4 ; a second output /O 1 , which is a complementary output to the first output O 1 , is connected to a fifth node N 5 ; and a third output O 2  is connected to a sixth node N 6 . 
     The first node N 1  is the connecting point of the first input I 1 , the output of a sixth inverter  33 , the input of a first inverter  28  and the input of a seventh inverter  34 . The second node N 2  is the connecting point of the second input /I 1 , the output of a third inverter  30 , the input of a fourth inverter  31  and the input of an eighth inverter  35 . The third node N 3  is the connecting point of the third input I 2 , the output of the fourth inverter  31  and the input of a fifth inverter  32 . The fourth node N 4  is the connecting point of the first output O 1  and the output of the seventh inverter  34 . The fifth node N 5  is the connecting point of the second output /O 1  and the output of an eighth inverter  35 . The sixth node N 6  is the connecting point of the third output O 2 , the output of the first inverter  28  and the input of a second inverter  29 . 
     Moreover, the output of the second inverter  29  is connected to the input of the third inverter  30 , while the output of the fifth inverter  32  is connected to the input of the sixth inverter  33 . 
     Because the first input I 1 , the output of sixth inverter  33 , the input of the first inverter  28  and the input of the seventh inverter  34  are connected at the first node N 1 , the circuit elements which become a load for the first input I 1  include only the output of the sixth inverter  33 , the input of the first inverter  28  and the input of the seventh inverter  34 . 
     Because the second input /I 1 , the output of the third inverter  30 , the input of the fourth inverter  31  and the input of the eighth inverter  35  are connected at the second node N 2 , the circuit elements which become a load for the second input /I 1  include only the output of the third inverter  30 , the input of the fourth inverter  31  and the input of the eighth inverter  35 . 
     In accordance with the second embodiment of the present invention, the number of circuit elements which become a load for the input at the connecting point of the input of the latch circuit are reduced to only three elements. Therefore, high-speed input operation of the latch circuit can be realized. 
     The first input I 1 , second input /I 1 , first output O 1  and second output /O 1  are assumed to be inputs and outputs used during ordinary operation. The third input I 2  and third output O 2  are assumed to be input and output, respectively, used in a test operation. The first input I 1 , second input /I 1 , the first output O 1  and the second output /O 1  are required to realize the high-speed input and output. The third input I 2  and third output O 2  are not required to realize high-speed input and output. In accordance with the second embodiment of the present invention, high-speed operation is realized during the normal operating condition of the latch circuit by realizing high-speed operation of the first input I 1  and second input /I 1  which require the high-speed operation. 
     In accordance with the second embodiment of the invention, the third input I 2  does not require high-speed operation. However, in accordance with the second embodiment of the present invention, high-speed operation is realized for the third input I 2 . 
     Because the third input I 2 , the output of the fourth inverter  31  and the input of the fifth inverter  32  are connected at the third node N 3 , the circuit elements which become a load for the third input I 2  include only of the output of the fourth inverter  31  and the input of the fifth inverter  32 . According to the second embodiment of the present invention, the number of circuit elements which become a load for the test input is reduced to two elements at the connecting point of the test input of the latch circuit. Therefore, high-speed test operation of the latch circuit may be realized. 
     On the other hand, since the third input I 2  is not required to realize high-speed operation, the other input which is not required to realize high-speed operation may be connected to the node to which the third input I 2  is connected. 
       FIG. 8  illustrates the latch circuit shown in  FIG. 6  applied to the SRAM of  FIG. 4A  in accordance with the second embodiment of the present invention. 
     As shown in  FIG. 8 , a first input I 1  is an input address signal; a second input /I 1 , which is the complement of the first input I 1 , is the complementary signal of the input address signal; a third input I 2  is an input scan signal; a first output O 1  is an output address signal; a second output /O 1 , which is the complement of the first output O 1 , is a complementary signal of the output address signal; and a third output O 2  is an output scan signal. 
     The input address signal and clock signal are supplied to the latch circuit via a switch circuit  36 . The switch circuit  36  comprises two P-channel transistors and two N-channel transistors connected in series, which are further connected to the high-voltage power source and low-voltage power source. 
     The complementary signal of the input address signal and clock signal are supplied to the latch circuit via a switch circuit  37 . The switch circuit  37  is also formed of two P-channel transistors and two N-channel transistors connected in series, which are further connected to the high-voltage power source and low-voltage power source. 
     The input scan signal and scan clock signal are supplied to the latch circuit via a switch circuit  38 . The switch circuit  38  is formed, in a manner similar to the switch circuit  36 , of two P-channel transistors and two N-channel transistors connected in series, which are further connected to the high-voltage power source and low-voltage power source. 
     During the normal operation, the scan clock signal stops. That is, connection among the switch circuit  38 , high-voltage power source and low-voltage power source is separated. More specifically, the signal “1” is supplied to the gate of one P-channel transistor, the signal “0” is supplied to the gate of one N-channel transistor via an inverter  39  and connection among the switch circuit  38 , high-voltage power source and low-voltage power source is separated. Therefore, the input scan signal and scan clock signal are not supplied to the latch circuit, and the input address signal, a complementary signal of the input address signal and the clock signal are supplied to the latch circuit. 
     At the time of a test operation, the clock signal stops. That is, the signal “1,” which is the stop signal, is supplied as the clock signal and connection among the switch circuit  36 , high-voltage power source and low-voltage power source is separated. Specifically, the signal “1” is supplied to the gate of one P-channel transistor, the signal “0” is supplied to the gate of one N-channel transistor via an inverter  40  and connection among the switch circuit  36 , high-voltage power source and low-voltage power source is separated. Moreover, the connection among the switch circuit  37 , the high-voltage power source and the low voltage power source is separated in a similar manner. Accordingly, the input address signal, the complementary signal of the input address signal and the clock signal are not supplied to the latch circuit, but the input scan signal and scan clock signal are supplied thereto. 
     The first output O 1  of the latch circuit is output as the output address signal via the inverter  34 , and the second output /O 1 , which is the complement of the first output O 1  of the latch circuit, is output as the complementary signal of the output address signal via the inverter  35 . The inverter  34  and the inverter  35  operate as buffers. However, the inverters  34  and  35  are not required, and the embodiment of the invention shown in  FIG. 8  operates without the inverter  34  and the inverter  35 . 
     A third embodiment of the invention will now be described below with reference to  FIG. 9 .  FIG. 9  is a block diagram of a semiconductor chip design system to design a latch circuit in accordance with embodiments of the present invention. 
     As shown in  FIG. 9 , a latch circuit, such as the latch circuit shown in  FIGS. 5–8 , is registered to a unit cell library  200 . Moreover, a memory (SRAM, DRAM or the like) using the latch circuit shown in  FIGS. 5–8  is registered to a macro cell library  201 . The unit cell library  200  and macro cell library  201  are used in the semiconductor design system. 
     As shown in  FIG. 9 , a system design system  101  generates a register transfer level (RTL) description (operation level logic circuit)  102  based on a semiconductor design specification  100 . A function/logic design system  103  generates a net list (i.e., a gate level logic circuit) based on the RTL description  102 . In practice, the RTL description  102  is converted to the net list  104  through logical synthesis. A layout design system  105  generates layout data  106  based on the net list  104 . A mask layout design system  107  generates mask layout data  108  based on the layout data  106 . A semiconductor chip is then manufactured based on the mask layout data  108 . 
     The unit cell library  200 , to which the latch circuit is registered, or the macro cell library  201 , to which the memory (e.g., SRAM) using the latch circuit of the present invention is registered, is used in the function/logic design system  103  to generate the net list  104  including the latch circuits shown in  FIGS. 5–8 . 
     Moreover, the unit cell library  200 , to which the latch circuits shown in  FIGS. 5–8  are registered, and/or the macro cell library  201 , to which the memory using the latch circuits shown in  FIGS. 5–8  is registered, is used in the layout design system  105  to generate the layout data  106  including the latch circuit of the present invention. 
     Furthermore, the unit cell library  200  and/or the macro cell library  201  is used in the mask layout design system  107  to generate the mask layout data  108  including the latch circuits shown in  FIGS. 5–8 . 
     In accordance with embodiments of the present invention described hereinabove, a semiconductor chip including a latch circuit is generated by utilizing the unit cell library  200  to which the latch circuit of the present invention is registered and/or the macro cell library  201  to which the memory using the latch circuit of the present invention is registered. 
     Although preferred embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principle and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.